module_content
stringlengths 18
1.05M
|
|---|
module system_axi_uartlite_0_0_cntr_incr_decr_addn_f
(SS,
Q,
fifo_full_p1,
tx_Start0,
reset_TX_FIFO_reg,
s_axi_aresetn,
fifo_Read,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1] ,
tx_Buffer_Full,
Bus_RNW_reg,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg ,
tx_Data_Enable_reg,
tx_DataBits,
tx_Start,
s_axi_aclk);
output [0:0]SS;
output [4:0]Q;
output fifo_full_p1;
output tx_Start0;
input reset_TX_FIFO_reg;
input s_axi_aresetn;
input fifo_Read;
input \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1] ;
input tx_Buffer_Full;
input Bus_RNW_reg;
input \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg ;
input tx_Data_Enable_reg;
input tx_DataBits;
input tx_Start;
input s_axi_aclk;
wire Bus_RNW_reg;
wire FIFO_Full_i_2__0_n_0;
wire \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg ;
wire \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1] ;
wire \INFERRED_GEN.cnt_i[3]_i_2__0_n_0 ;
wire \INFERRED_GEN.cnt_i[4]_i_3__0_n_0 ;
wire \INFERRED_GEN.cnt_i[4]_i_4__0_n_0 ;
wire [4:0]Q;
wire [0:0]SS;
wire [4:0]addr_i_p1;
wire fifo_Read;
wire fifo_full_p1;
wire reset_TX_FIFO_reg;
wire s_axi_aclk;
wire s_axi_aresetn;
wire tx_Buffer_Full;
wire tx_DataBits;
wire tx_Data_Enable_reg;
wire tx_Start;
wire tx_Start0;
LUT6 #(
.INIT(64'h0000000004090000))
FIFO_Full_i_1
(.I0(\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1] ),
.I1(Q[0]),
.I2(Q[4]),
.I3(fifo_Read),
.I4(Q[3]),
.I5(FIFO_Full_i_2__0_n_0),
.O(fifo_full_p1));
LUT2 #(
.INIT(4'h7))
FIFO_Full_i_2__0
(.I0(Q[1]),
.I1(Q[2]),
.O(FIFO_Full_i_2__0_n_0));
LUT6 #(
.INIT(64'hBBB4BBBB444B4444))
\INFERRED_GEN.cnt_i[0]_i_1
(.I0(Q[4]),
.I1(fifo_Read),
.I2(tx_Buffer_Full),
.I3(Bus_RNW_reg),
.I4(\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg ),
.I5(Q[0]),
.O(addr_i_p1[0]));
(* SOFT_HLUTNM = "soft_lutpair18" *)
LUT5 #(
.INIT(32'hAA9A65AA))
\INFERRED_GEN.cnt_i[1]_i_1
(.I0(Q[1]),
.I1(Q[4]),
.I2(fifo_Read),
.I3(Q[0]),
.I4(\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1] ),
.O(addr_i_p1[1]));
LUT6 #(
.INIT(64'hF4FF0B00FFBF0040))
\INFERRED_GEN.cnt_i[2]_i_1
(.I0(Q[4]),
.I1(fifo_Read),
.I2(\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1] ),
.I3(Q[0]),
.I4(Q[2]),
.I5(Q[1]),
.O(addr_i_p1[2]));
LUT6 #(
.INIT(64'hAAAA6AAAAAA9AAAA))
\INFERRED_GEN.cnt_i[3]_i_1
(.I0(Q[3]),
.I1(Q[1]),
.I2(Q[2]),
.I3(\INFERRED_GEN.cnt_i[3]_i_2__0_n_0 ),
.I4(\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1] ),
.I5(Q[0]),
.O(addr_i_p1[3]));
(* SOFT_HLUTNM = "soft_lutpair18" *)
LUT2 #(
.INIT(4'hB))
\INFERRED_GEN.cnt_i[3]_i_2__0
(.I0(Q[4]),
.I1(fifo_Read),
.O(\INFERRED_GEN.cnt_i[3]_i_2__0_n_0 ));
LUT2 #(
.INIT(4'hB))
\INFERRED_GEN.cnt_i[4]_i_1__0
(.I0(reset_TX_FIFO_reg),
.I1(s_axi_aresetn),
.O(SS));
LUT6 #(
.INIT(64'hF0F0FAFAF003F0F0))
\INFERRED_GEN.cnt_i[4]_i_2
(.I0(\INFERRED_GEN.cnt_i[4]_i_3__0_n_0 ),
.I1(fifo_Read),
.I2(Q[4]),
.I3(\INFERRED_GEN.cnt_i[4]_i_4__0_n_0 ),
.I4(Q[0]),
.I5(\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1] ),
.O(addr_i_p1[4]));
(* SOFT_HLUTNM = "soft_lutpair19" *)
LUT4 #(
.INIT(16'h0004))
\INFERRED_GEN.cnt_i[4]_i_3__0
(.I0(Q[3]),
.I1(fifo_Read),
.I2(Q[2]),
.I3(Q[1]),
.O(\INFERRED_GEN.cnt_i[4]_i_3__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair19" *)
LUT3 #(
.INIT(8'h7F))
\INFERRED_GEN.cnt_i[4]_i_4__0
(.I0(Q[2]),
.I1(Q[1]),
.I2(Q[3]),
.O(\INFERRED_GEN.cnt_i[4]_i_4__0_n_0 ));
FDSE \INFERRED_GEN.cnt_i_reg[0]
(.C(s_axi_aclk),
.CE(1'b1),
.D(addr_i_p1[0]),
.Q(Q[0]),
.S(SS));
FDSE \INFERRED_GEN.cnt_i_reg[1]
(.C(s_axi_aclk),
.CE(1'b1),
.D(addr_i_p1[1]),
.Q(Q[1]),
.S(SS));
FDSE \INFERRED_GEN.cnt_i_reg[2]
(.C(s_axi_aclk),
.CE(1'b1),
.D(addr_i_p1[2]),
.Q(Q[2]),
.S(SS));
FDSE \INFERRED_GEN.cnt_i_reg[3]
(.C(s_axi_aclk),
.CE(1'b1),
.D(addr_i_p1[3]),
.Q(Q[3]),
.S(SS));
FDSE \INFERRED_GEN.cnt_i_reg[4]
(.C(s_axi_aclk),
.CE(1'b1),
.D(addr_i_p1[4]),
.Q(Q[4]),
.S(SS));
LUT4 #(
.INIT(16'h0F02))
tx_Start_i_1
(.I0(tx_Data_Enable_reg),
.I1(Q[4]),
.I2(tx_DataBits),
.I3(tx_Start),
.O(tx_Start0));
endmodule
|
module system_axi_uartlite_0_0_cntr_incr_decr_addn_f_2
(SS,
fifo_full_p1,
Q,
Interrupt0,
reset_RX_FIFO_reg,
s_axi_aresetn,
\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0] ,
Bus_RNW_reg,
\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg ,
Bus_RNW_reg_reg,
fifo_Write,
FIFO_Full_reg,
valid_rx,
rx_Data_Present_Pre,
enable_interrupts,
\INFERRED_GEN.cnt_i_reg[4]_0 ,
tx_Buffer_Empty_Pre,
s_axi_aclk);
output [0:0]SS;
output fifo_full_p1;
output [4:0]Q;
output Interrupt0;
input reset_RX_FIFO_reg;
input s_axi_aresetn;
input \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0] ;
input Bus_RNW_reg;
input \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg ;
input Bus_RNW_reg_reg;
input fifo_Write;
input FIFO_Full_reg;
input valid_rx;
input rx_Data_Present_Pre;
input enable_interrupts;
input [0:0]\INFERRED_GEN.cnt_i_reg[4]_0 ;
input tx_Buffer_Empty_Pre;
input s_axi_aclk;
wire Bus_RNW_reg;
wire Bus_RNW_reg_reg;
wire FIFO_Full_i_2_n_0;
wire FIFO_Full_reg;
wire \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg ;
wire \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0] ;
wire \INFERRED_GEN.cnt_i[4]_i_4_n_0 ;
wire \INFERRED_GEN.cnt_i[4]_i_5__0_n_0 ;
wire \INFERRED_GEN.cnt_i[4]_i_6_n_0 ;
wire [0:0]\INFERRED_GEN.cnt_i_reg[4]_0 ;
wire Interrupt0;
wire [4:0]Q;
wire [0:0]SS;
wire [4:0]addr_i_p1;
wire enable_interrupts;
wire fifo_Write;
wire fifo_full_p1;
wire reset_RX_FIFO_reg;
wire rx_Data_Present_Pre;
wire s_axi_aclk;
wire s_axi_aresetn;
wire tx_Buffer_Empty_Pre;
wire valid_rx;
LUT6 #(
.INIT(64'h0000000009040000))
FIFO_Full_i_1__0
(.I0(\INFERRED_GEN.cnt_i[4]_i_6_n_0 ),
.I1(Q[0]),
.I2(Q[4]),
.I3(\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0] ),
.I4(Q[3]),
.I5(FIFO_Full_i_2_n_0),
.O(fifo_full_p1));
(* SOFT_HLUTNM = "soft_lutpair16" *)
LUT2 #(
.INIT(4'h7))
FIFO_Full_i_2
(.I0(Q[1]),
.I1(Q[2]),
.O(FIFO_Full_i_2_n_0));
LUT5 #(
.INIT(32'hF70808F7))
\INFERRED_GEN.cnt_i[0]_i_1__0
(.I0(Bus_RNW_reg),
.I1(\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg ),
.I2(Q[4]),
.I3(\INFERRED_GEN.cnt_i[4]_i_6_n_0 ),
.I4(Q[0]),
.O(addr_i_p1[0]));
LUT6 #(
.INIT(64'hAAAAAA6A5595AAAA))
\INFERRED_GEN.cnt_i[1]_i_1__0
(.I0(Q[1]),
.I1(Bus_RNW_reg),
.I2(\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg ),
.I3(Q[4]),
.I4(Q[0]),
.I5(\INFERRED_GEN.cnt_i[4]_i_6_n_0 ),
.O(addr_i_p1[1]));
(* SOFT_HLUTNM = "soft_lutpair16" *)
LUT5 #(
.INIT(32'hFE017F80))
\INFERRED_GEN.cnt_i[2]_i_1__0
(.I0(Q[0]),
.I1(Bus_RNW_reg_reg),
.I2(Q[1]),
.I3(Q[2]),
.I4(\INFERRED_GEN.cnt_i[4]_i_6_n_0 ),
.O(addr_i_p1[2]));
LUT6 #(
.INIT(64'hF0F0F0E178F0F0F0))
\INFERRED_GEN.cnt_i[3]_i_1__0
(.I0(Q[0]),
.I1(Bus_RNW_reg_reg),
.I2(Q[3]),
.I3(Q[1]),
.I4(Q[2]),
.I5(\INFERRED_GEN.cnt_i[4]_i_6_n_0 ),
.O(addr_i_p1[3]));
LUT2 #(
.INIT(4'hB))
\INFERRED_GEN.cnt_i[4]_i_1
(.I0(reset_RX_FIFO_reg),
.I1(s_axi_aresetn),
.O(SS));
LUT6 #(
.INIT(64'hF0F0F4F4F00AF0F0))
\INFERRED_GEN.cnt_i[4]_i_2__0
(.I0(\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0] ),
.I1(\INFERRED_GEN.cnt_i[4]_i_4_n_0 ),
.I2(Q[4]),
.I3(\INFERRED_GEN.cnt_i[4]_i_5__0_n_0 ),
.I4(Q[0]),
.I5(\INFERRED_GEN.cnt_i[4]_i_6_n_0 ),
.O(addr_i_p1[4]));
(* SOFT_HLUTNM = "soft_lutpair17" *)
LUT3 #(
.INIT(8'h01))
\INFERRED_GEN.cnt_i[4]_i_4
(.I0(Q[2]),
.I1(Q[1]),
.I2(Q[3]),
.O(\INFERRED_GEN.cnt_i[4]_i_4_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair17" *)
LUT3 #(
.INIT(8'h7F))
\INFERRED_GEN.cnt_i[4]_i_5__0
(.I0(Q[2]),
.I1(Q[1]),
.I2(Q[3]),
.O(\INFERRED_GEN.cnt_i[4]_i_5__0_n_0 ));
LUT3 #(
.INIT(8'hDF))
\INFERRED_GEN.cnt_i[4]_i_6
(.I0(fifo_Write),
.I1(FIFO_Full_reg),
.I2(valid_rx),
.O(\INFERRED_GEN.cnt_i[4]_i_6_n_0 ));
FDSE \INFERRED_GEN.cnt_i_reg[0]
(.C(s_axi_aclk),
.CE(1'b1),
.D(addr_i_p1[0]),
.Q(Q[0]),
.S(SS));
FDSE \INFERRED_GEN.cnt_i_reg[1]
(.C(s_axi_aclk),
.CE(1'b1),
.D(addr_i_p1[1]),
.Q(Q[1]),
.S(SS));
FDSE \INFERRED_GEN.cnt_i_reg[2]
(.C(s_axi_aclk),
.CE(1'b1),
.D(addr_i_p1[2]),
.Q(Q[2]),
.S(SS));
FDSE \INFERRED_GEN.cnt_i_reg[3]
(.C(s_axi_aclk),
.CE(1'b1),
.D(addr_i_p1[3]),
.Q(Q[3]),
.S(SS));
FDSE \INFERRED_GEN.cnt_i_reg[4]
(.C(s_axi_aclk),
.CE(1'b1),
.D(addr_i_p1[4]),
.Q(Q[4]),
.S(SS));
LUT5 #(
.INIT(32'h1010F010))
Interrupt_i_2
(.I0(rx_Data_Present_Pre),
.I1(Q[4]),
.I2(enable_interrupts),
.I3(\INFERRED_GEN.cnt_i_reg[4]_0 ),
.I4(tx_Buffer_Empty_Pre),
.O(Interrupt0));
endmodule
|
module system_axi_uartlite_0_0_dynshreg_f
(mux_Out,
p_4_in,
\mux_sel_reg[2] ,
\mux_sel_reg[0] ,
fifo_wr,
s_axi_wdata,
Q,
s_axi_aclk);
output mux_Out;
input p_4_in;
input \mux_sel_reg[2] ;
input \mux_sel_reg[0] ;
input fifo_wr;
input [7:0]s_axi_wdata;
input [3:0]Q;
input s_axi_aclk;
wire [3:0]Q;
wire [0:7]fifo_DOut;
wire fifo_wr;
wire mux_Out;
wire \mux_sel_reg[0] ;
wire \mux_sel_reg[2] ;
wire p_4_in;
wire s_axi_aclk;
wire [7:0]s_axi_wdata;
wire serial_Data_i_2_n_0;
wire serial_Data_i_3_n_0;
wire serial_Data_i_4_n_0;
wire serial_Data_i_5_n_0;
(* srl_bus_name = "U0/\UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15] " *)
(* srl_name = "U0/\UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15][0]_srl16 " *)
SRL16E #(
.INIT(16'h0000))
\INFERRED_GEN.data_reg[15][0]_srl16
(.A0(Q[0]),
.A1(Q[1]),
.A2(Q[2]),
.A3(Q[3]),
.CE(fifo_wr),
.CLK(s_axi_aclk),
.D(s_axi_wdata[0]),
.Q(fifo_DOut[7]));
(* srl_bus_name = "U0/\UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15] " *)
(* srl_name = "U0/\UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15][1]_srl16 " *)
SRL16E #(
.INIT(16'h0000))
\INFERRED_GEN.data_reg[15][1]_srl16
(.A0(Q[0]),
.A1(Q[1]),
.A2(Q[2]),
.A3(Q[3]),
.CE(fifo_wr),
.CLK(s_axi_aclk),
.D(s_axi_wdata[1]),
.Q(fifo_DOut[6]));
(* srl_bus_name = "U0/\UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15] " *)
(* srl_name = "U0/\UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15][2]_srl16 " *)
SRL16E #(
.INIT(16'h0000))
\INFERRED_GEN.data_reg[15][2]_srl16
(.A0(Q[0]),
.A1(Q[1]),
.A2(Q[2]),
.A3(Q[3]),
.CE(fifo_wr),
.CLK(s_axi_aclk),
.D(s_axi_wdata[2]),
.Q(fifo_DOut[5]));
(* srl_bus_name = "U0/\UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15] " *)
(* srl_name = "U0/\UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15][3]_srl16 " *)
SRL16E #(
.INIT(16'h0000))
\INFERRED_GEN.data_reg[15][3]_srl16
(.A0(Q[0]),
.A1(Q[1]),
.A2(Q[2]),
.A3(Q[3]),
.CE(fifo_wr),
.CLK(s_axi_aclk),
.D(s_axi_wdata[3]),
.Q(fifo_DOut[4]));
(* srl_bus_name = "U0/\UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15] " *)
(* srl_name = "U0/\UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15][4]_srl16 " *)
SRL16E #(
.INIT(16'h0000))
\INFERRED_GEN.data_reg[15][4]_srl16
(.A0(Q[0]),
.A1(Q[1]),
.A2(Q[2]),
.A3(Q[3]),
.CE(fifo_wr),
.CLK(s_axi_aclk),
.D(s_axi_wdata[4]),
.Q(fifo_DOut[3]));
(* srl_bus_name = "U0/\UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15] " *)
(* srl_name = "U0/\UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15][5]_srl16 " *)
SRL16E #(
.INIT(16'h0000))
\INFERRED_GEN.data_reg[15][5]_srl16
(.A0(Q[0]),
.A1(Q[1]),
.A2(Q[2]),
.A3(Q[3]),
.CE(fifo_wr),
.CLK(s_axi_aclk),
.D(s_axi_wdata[5]),
.Q(fifo_DOut[2]));
(* srl_bus_name = "U0/\UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15] " *)
(* srl_name = "U0/\UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15][6]_srl16 " *)
SRL16E #(
.INIT(16'h0000))
\INFERRED_GEN.data_reg[15][6]_srl16
(.A0(Q[0]),
.A1(Q[1]),
.A2(Q[2]),
.A3(Q[3]),
.CE(fifo_wr),
.CLK(s_axi_aclk),
.D(s_axi_wdata[6]),
.Q(fifo_DOut[1]));
(* srl_bus_name = "U0/\UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15] " *)
(* srl_name = "U0/\UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15][7]_srl16 " *)
SRL16E #(
.INIT(16'h0000))
\INFERRED_GEN.data_reg[15][7]_srl16
(.A0(Q[0]),
.A1(Q[1]),
.A2(Q[2]),
.A3(Q[3]),
.CE(fifo_wr),
.CLK(s_axi_aclk),
.D(s_axi_wdata[7]),
.Q(fifo_DOut[0]));
LUT4 #(
.INIT(16'hFFFE))
serial_Data_i_1
(.I0(serial_Data_i_2_n_0),
.I1(serial_Data_i_3_n_0),
.I2(serial_Data_i_4_n_0),
.I3(serial_Data_i_5_n_0),
.O(mux_Out));
LUT5 #(
.INIT(32'h44400040))
serial_Data_i_2
(.I0(\mux_sel_reg[2] ),
.I1(p_4_in),
.I2(fifo_DOut[2]),
.I3(\mux_sel_reg[0] ),
.I4(fifo_DOut[6]),
.O(serial_Data_i_2_n_0));
LUT5 #(
.INIT(32'h88800080))
serial_Data_i_3
(.I0(\mux_sel_reg[0] ),
.I1(\mux_sel_reg[2] ),
.I2(fifo_DOut[5]),
.I3(p_4_in),
.I4(fifo_DOut[7]),
.O(serial_Data_i_3_n_0));
LUT5 #(
.INIT(32'h44400040))
serial_Data_i_4
(.I0(\mux_sel_reg[0] ),
.I1(\mux_sel_reg[2] ),
.I2(fifo_DOut[1]),
.I3(p_4_in),
.I4(fifo_DOut[3]),
.O(serial_Data_i_4_n_0));
LUT5 #(
.INIT(32'h000A000C))
serial_Data_i_5
(.I0(fifo_DOut[4]),
.I1(fifo_DOut[0]),
.I2(p_4_in),
.I3(\mux_sel_reg[2] ),
.I4(\mux_sel_reg[0] ),
.O(serial_Data_i_5_n_0));
endmodule
|
module system_axi_uartlite_0_0_dynshreg_f_3
(out,
valid_rx,
FIFO_Full_reg,
fifo_Write,
in,
Q,
s_axi_aclk);
output [7:0]out;
input valid_rx;
input FIFO_Full_reg;
input fifo_Write;
input [0:7]in;
input [3:0]Q;
input s_axi_aclk;
wire FIFO_Full_reg;
wire [3:0]Q;
wire fifo_Write;
wire fifo_wr;
wire [0:7]in;
wire [7:0]out;
wire s_axi_aclk;
wire valid_rx;
(* srl_bus_name = "U0/\UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15] " *)
(* srl_name = "U0/\UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15][0]_srl16 " *)
SRL16E #(
.INIT(16'h0000))
\INFERRED_GEN.data_reg[15][0]_srl16
(.A0(Q[0]),
.A1(Q[1]),
.A2(Q[2]),
.A3(Q[3]),
.CE(fifo_wr),
.CLK(s_axi_aclk),
.D(in[7]),
.Q(out[0]));
LUT3 #(
.INIT(8'h20))
\INFERRED_GEN.data_reg[15][0]_srl16_i_1__0
(.I0(valid_rx),
.I1(FIFO_Full_reg),
.I2(fifo_Write),
.O(fifo_wr));
(* srl_bus_name = "U0/\UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15] " *)
(* srl_name = "U0/\UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15][1]_srl16 " *)
SRL16E #(
.INIT(16'h0000))
\INFERRED_GEN.data_reg[15][1]_srl16
(.A0(Q[0]),
.A1(Q[1]),
.A2(Q[2]),
.A3(Q[3]),
.CE(fifo_wr),
.CLK(s_axi_aclk),
.D(in[6]),
.Q(out[1]));
(* srl_bus_name = "U0/\UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15] " *)
(* srl_name = "U0/\UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15][2]_srl16 " *)
SRL16E #(
.INIT(16'h0000))
\INFERRED_GEN.data_reg[15][2]_srl16
(.A0(Q[0]),
.A1(Q[1]),
.A2(Q[2]),
.A3(Q[3]),
.CE(fifo_wr),
.CLK(s_axi_aclk),
.D(in[5]),
.Q(out[2]));
(* srl_bus_name = "U0/\UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15] " *)
(* srl_name = "U0/\UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15][3]_srl16 " *)
SRL16E #(
.INIT(16'h0000))
\INFERRED_GEN.data_reg[15][3]_srl16
(.A0(Q[0]),
.A1(Q[1]),
.A2(Q[2]),
.A3(Q[3]),
.CE(fifo_wr),
.CLK(s_axi_aclk),
.D(in[4]),
.Q(out[3]));
(* srl_bus_name = "U0/\UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15] " *)
(* srl_name = "U0/\UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15][4]_srl16 " *)
SRL16E #(
.INIT(16'h0000))
\INFERRED_GEN.data_reg[15][4]_srl16
(.A0(Q[0]),
.A1(Q[1]),
.A2(Q[2]),
.A3(Q[3]),
.CE(fifo_wr),
.CLK(s_axi_aclk),
.D(in[3]),
.Q(out[4]));
(* srl_bus_name = "U0/\UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15] " *)
(* srl_name = "U0/\UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15][5]_srl16 " *)
SRL16E #(
.INIT(16'h0000))
\INFERRED_GEN.data_reg[15][5]_srl16
(.A0(Q[0]),
.A1(Q[1]),
.A2(Q[2]),
.A3(Q[3]),
.CE(fifo_wr),
.CLK(s_axi_aclk),
.D(in[2]),
.Q(out[5]));
(* srl_bus_name = "U0/\UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15] " *)
(* srl_name = "U0/\UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15][6]_srl16 " *)
SRL16E #(
.INIT(16'h0000))
\INFERRED_GEN.data_reg[15][6]_srl16
(.A0(Q[0]),
.A1(Q[1]),
.A2(Q[2]),
.A3(Q[3]),
.CE(fifo_wr),
.CLK(s_axi_aclk),
.D(in[1]),
.Q(out[6]));
(* srl_bus_name = "U0/\UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15] " *)
(* srl_name = "U0/\UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15][7]_srl16 " *)
SRL16E #(
.INIT(16'h0000))
\INFERRED_GEN.data_reg[15][7]_srl16
(.A0(Q[0]),
.A1(Q[1]),
.A2(Q[2]),
.A3(Q[3]),
.CE(fifo_wr),
.CLK(s_axi_aclk),
.D(in[0]),
.Q(out[7]));
endmodule
|
module system_axi_uartlite_0_0_dynshreg_i_f
(p_20_out,
\SERIAL_TO_PARALLEL[2].fifo_din_reg[2] ,
p_17_out,
p_14_out,
p_11_out,
p_8_out,
p_5_out,
p_2_out,
status_reg_reg0,
fifo_Write0,
stop_Bit_Position_reg,
frame_err_ocrd_reg,
running_reg,
en_16x_Baud,
s_axi_aclk,
in,
start_Edge_Detected,
s_axi_aresetn,
stop_Bit_Position_reg_0,
scndry_out,
clr_Status,
status_reg,
valid_rx,
frame_err_ocrd,
running_reg_0);
output p_20_out;
output \SERIAL_TO_PARALLEL[2].fifo_din_reg[2] ;
output p_17_out;
output p_14_out;
output p_11_out;
output p_8_out;
output p_5_out;
output p_2_out;
output status_reg_reg0;
output fifo_Write0;
output stop_Bit_Position_reg;
output frame_err_ocrd_reg;
output running_reg;
input en_16x_Baud;
input s_axi_aclk;
input [0:7]in;
input start_Edge_Detected;
input s_axi_aresetn;
input stop_Bit_Position_reg_0;
input scndry_out;
input clr_Status;
input [0:0]status_reg;
input valid_rx;
input frame_err_ocrd;
input running_reg_0;
wire \INFERRED_GEN.data_reg[14][0]_srl15_n_0 ;
wire \INFERRED_GEN.data_reg[15] ;
wire \SERIAL_TO_PARALLEL[2].fifo_din_reg[2] ;
wire clr_Status;
wire en_16x_Baud;
wire fifo_Write0;
wire frame_err_ocrd;
wire frame_err_ocrd_reg;
wire [0:7]in;
wire p_11_out;
wire p_14_out;
wire p_17_out;
wire p_20_out;
wire p_2_out;
wire p_5_out;
wire p_8_out;
wire recycle;
wire running_reg;
wire running_reg_0;
wire s_axi_aclk;
wire s_axi_aresetn;
wire scndry_out;
wire start_Edge_Detected;
wire [0:0]status_reg;
wire \status_reg[1]_i_2_n_0 ;
wire status_reg_reg0;
wire stop_Bit_Position_reg;
wire stop_Bit_Position_reg_0;
wire valid_rx;
(* srl_bus_name = "U0/\UARTLITE_CORE_I/UARTLITE_RX_I/DELAY_16_I/INFERRED_GEN.data_reg[14] " *)
(* srl_name = "U0/\UARTLITE_CORE_I/UARTLITE_RX_I/DELAY_16_I/INFERRED_GEN.data_reg[14][0]_srl15 " *)
SRL16E #(
.INIT(16'h0000))
\INFERRED_GEN.data_reg[14][0]_srl15
(.A0(1'b0),
.A1(1'b1),
.A2(1'b1),
.A3(1'b1),
.CE(en_16x_Baud),
.CLK(s_axi_aclk),
.D(recycle),
.Q(\INFERRED_GEN.data_reg[14][0]_srl15_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair15" *)
LUT4 #(
.INIT(16'h4440))
\INFERRED_GEN.data_reg[14][0]_srl15_i_1
(.I0(stop_Bit_Position_reg_0),
.I1(valid_rx),
.I2(\INFERRED_GEN.data_reg[15] ),
.I3(start_Edge_Detected),
.O(recycle));
FDRE #(
.INIT(1'b0))
\INFERRED_GEN.data_reg[15][0]
(.C(s_axi_aclk),
.CE(en_16x_Baud),
.D(\INFERRED_GEN.data_reg[14][0]_srl15_n_0 ),
.Q(\INFERRED_GEN.data_reg[15] ),
.R(1'b0));
LUT5 #(
.INIT(32'h0A000C00))
\SERIAL_TO_PARALLEL[2].fifo_din[2]_i_1
(.I0(in[1]),
.I1(in[0]),
.I2(start_Edge_Detected),
.I3(s_axi_aresetn),
.I4(\SERIAL_TO_PARALLEL[2].fifo_din_reg[2] ),
.O(p_20_out));
LUT5 #(
.INIT(32'h0A000C00))
\SERIAL_TO_PARALLEL[3].fifo_din[3]_i_1
(.I0(in[2]),
.I1(in[1]),
.I2(start_Edge_Detected),
.I3(s_axi_aresetn),
.I4(\SERIAL_TO_PARALLEL[2].fifo_din_reg[2] ),
.O(p_17_out));
LUT5 #(
.INIT(32'h0A000C00))
\SERIAL_TO_PARALLEL[4].fifo_din[4]_i_1
(.I0(in[3]),
.I1(in[2]),
.I2(start_Edge_Detected),
.I3(s_axi_aresetn),
.I4(\SERIAL_TO_PARALLEL[2].fifo_din_reg[2] ),
.O(p_14_out));
LUT5 #(
.INIT(32'h0A000C00))
\SERIAL_TO_PARALLEL[5].fifo_din[5]_i_1
(.I0(in[4]),
.I1(in[3]),
.I2(start_Edge_Detected),
.I3(s_axi_aresetn),
.I4(\SERIAL_TO_PARALLEL[2].fifo_din_reg[2] ),
.O(p_11_out));
LUT5 #(
.INIT(32'h0A000C00))
\SERIAL_TO_PARALLEL[6].fifo_din[6]_i_1
(.I0(in[5]),
.I1(in[4]),
.I2(start_Edge_Detected),
.I3(s_axi_aresetn),
.I4(\SERIAL_TO_PARALLEL[2].fifo_din_reg[2] ),
.O(p_8_out));
LUT5 #(
.INIT(32'h0A000C00))
\SERIAL_TO_PARALLEL[7].fifo_din[7]_i_1
(.I0(in[6]),
.I1(in[5]),
.I2(start_Edge_Detected),
.I3(s_axi_aresetn),
.I4(\SERIAL_TO_PARALLEL[2].fifo_din_reg[2] ),
.O(p_5_out));
LUT5 #(
.INIT(32'h0A000C00))
\SERIAL_TO_PARALLEL[8].fifo_din[8]_i_1
(.I0(in[7]),
.I1(in[6]),
.I2(start_Edge_Detected),
.I3(s_axi_aresetn),
.I4(\SERIAL_TO_PARALLEL[2].fifo_din_reg[2] ),
.O(p_2_out));
(* SOFT_HLUTNM = "soft_lutpair13" *)
LUT3 #(
.INIT(8'hF7))
\SERIAL_TO_PARALLEL[8].fifo_din[8]_i_2
(.I0(en_16x_Baud),
.I1(\INFERRED_GEN.data_reg[15] ),
.I2(stop_Bit_Position_reg_0),
.O(\SERIAL_TO_PARALLEL[2].fifo_din_reg[2] ));
(* SOFT_HLUTNM = "soft_lutpair14" *)
LUT4 #(
.INIT(16'h8000))
fifo_Write_i_1
(.I0(\INFERRED_GEN.data_reg[15] ),
.I1(en_16x_Baud),
.I2(stop_Bit_Position_reg_0),
.I3(scndry_out),
.O(fifo_Write0));
(* SOFT_HLUTNM = "soft_lutpair14" *)
LUT5 #(
.INIT(32'h00FF0080))
frame_err_ocrd_i_1
(.I0(\INFERRED_GEN.data_reg[15] ),
.I1(en_16x_Baud),
.I2(stop_Bit_Position_reg_0),
.I3(scndry_out),
.I4(frame_err_ocrd),
.O(frame_err_ocrd_reg));
(* SOFT_HLUTNM = "soft_lutpair13" *)
LUT5 #(
.INIT(32'hBFFFA0A0))
running_i_1
(.I0(start_Edge_Detected),
.I1(\INFERRED_GEN.data_reg[15] ),
.I2(en_16x_Baud),
.I3(stop_Bit_Position_reg_0),
.I4(running_reg_0),
.O(running_reg));
LUT5 #(
.INIT(32'h0F000200))
\status_reg[1]_i_1
(.I0(\status_reg[1]_i_2_n_0 ),
.I1(scndry_out),
.I2(clr_Status),
.I3(s_axi_aresetn),
.I4(status_reg),
.O(status_reg_reg0));
(* SOFT_HLUTNM = "soft_lutpair15" *)
LUT3 #(
.INIT(8'h80))
\status_reg[1]_i_2
(.I0(stop_Bit_Position_reg_0),
.I1(en_16x_Baud),
.I2(\INFERRED_GEN.data_reg[15] ),
.O(\status_reg[1]_i_2_n_0 ));
LUT4 #(
.INIT(16'h2CCC))
stop_Bit_Position_i_1
(.I0(in[7]),
.I1(stop_Bit_Position_reg_0),
.I2(en_16x_Baud),
.I3(\INFERRED_GEN.data_reg[15] ),
.O(stop_Bit_Position_reg));
endmodule
|
module system_axi_uartlite_0_0_dynshreg_i_f__parameterized0
(tx_Data_Enable_reg,
en_16x_Baud,
s_axi_aclk,
tx_Data_Enable_reg_0);
output tx_Data_Enable_reg;
input en_16x_Baud;
input s_axi_aclk;
input tx_Data_Enable_reg_0;
wire \INFERRED_GEN.data_reg[14][0]_srl15_n_0 ;
wire \INFERRED_GEN.data_reg_n_0_[15][0] ;
wire en_16x_Baud;
wire s_axi_aclk;
wire tx_Data_Enable_reg;
wire tx_Data_Enable_reg_0;
(* srl_bus_name = "U0/\UARTLITE_CORE_I/UARTLITE_TX_I/MID_START_BIT_SRL16_I/INFERRED_GEN.data_reg[14] " *)
(* srl_name = "U0/\UARTLITE_CORE_I/UARTLITE_TX_I/MID_START_BIT_SRL16_I/INFERRED_GEN.data_reg[14][0]_srl15 " *)
SRL16E #(
.INIT(16'h0001))
\INFERRED_GEN.data_reg[14][0]_srl15
(.A0(1'b0),
.A1(1'b1),
.A2(1'b1),
.A3(1'b1),
.CE(en_16x_Baud),
.CLK(s_axi_aclk),
.D(\INFERRED_GEN.data_reg_n_0_[15][0] ),
.Q(\INFERRED_GEN.data_reg[14][0]_srl15_n_0 ));
FDRE #(
.INIT(1'b0))
\INFERRED_GEN.data_reg[15][0]
(.C(s_axi_aclk),
.CE(en_16x_Baud),
.D(\INFERRED_GEN.data_reg[14][0]_srl15_n_0 ),
.Q(\INFERRED_GEN.data_reg_n_0_[15][0] ),
.R(1'b0));
LUT3 #(
.INIT(8'h20))
tx_Data_Enable_i_1
(.I0(\INFERRED_GEN.data_reg_n_0_[15][0] ),
.I1(tx_Data_Enable_reg_0),
.I2(en_16x_Baud),
.O(tx_Data_Enable_reg));
endmodule
|
module system_axi_uartlite_0_0_pselect_f
(ce_expnd_i_3,
\bus2ip_addr_i_reg[2] ,
start2,
\bus2ip_addr_i_reg[3] );
output ce_expnd_i_3;
input \bus2ip_addr_i_reg[2] ;
input start2;
input \bus2ip_addr_i_reg[3] ;
wire \bus2ip_addr_i_reg[2] ;
wire \bus2ip_addr_i_reg[3] ;
wire ce_expnd_i_3;
wire start2;
LUT3 #(
.INIT(8'h04))
CS
(.I0(\bus2ip_addr_i_reg[2] ),
.I1(start2),
.I2(\bus2ip_addr_i_reg[3] ),
.O(ce_expnd_i_3));
endmodule
|
module system_axi_uartlite_0_0_pselect_f__parameterized1
(ce_expnd_i_1,
\bus2ip_addr_i_reg[3] ,
start2,
\bus2ip_addr_i_reg[2] );
output ce_expnd_i_1;
input \bus2ip_addr_i_reg[3] ;
input start2;
input \bus2ip_addr_i_reg[2] ;
wire \bus2ip_addr_i_reg[2] ;
wire \bus2ip_addr_i_reg[3] ;
wire ce_expnd_i_1;
wire start2;
LUT3 #(
.INIT(8'h08))
CS
(.I0(\bus2ip_addr_i_reg[3] ),
.I1(start2),
.I2(\bus2ip_addr_i_reg[2] ),
.O(ce_expnd_i_1));
endmodule
|
module system_axi_uartlite_0_0_slave_attachment
(tx_Buffer_Empty_Pre_reg,
\s_axi_rresp_i_reg[1]_0 ,
s_axi_rresp,
enable_interrupts_reg,
s_axi_rvalid,
s_axi_bvalid,
s_axi_bresp,
fifo_wr,
\INFERRED_GEN.cnt_i_reg[2] ,
\INFERRED_GEN.cnt_i_reg[2]_0 ,
s_axi_arready,
FIFO_Full_reg,
reset_TX_FIFO,
reset_RX_FIFO,
s_axi_awready,
bus2ip_rdce,
enable_interrupts_reg_0,
tx_Buffer_Empty_Pre_reg_0,
rx_Data_Present_Pre_reg,
s_axi_rdata,
bus2ip_reset,
s_axi_aclk,
tx_Buffer_Full,
Q,
out,
rx_Buffer_Full,
\INFERRED_GEN.cnt_i_reg[4] ,
enable_interrupts,
status_reg,
s_axi_arvalid,
s_axi_wdata,
s_axi_aresetn,
s_axi_awvalid,
s_axi_wvalid,
s_axi_rready,
s_axi_bready,
s_axi_awaddr,
s_axi_araddr);
output tx_Buffer_Empty_Pre_reg;
output \s_axi_rresp_i_reg[1]_0 ;
output [0:0]s_axi_rresp;
output enable_interrupts_reg;
output s_axi_rvalid;
output s_axi_bvalid;
output [0:0]s_axi_bresp;
output fifo_wr;
output \INFERRED_GEN.cnt_i_reg[2] ;
output \INFERRED_GEN.cnt_i_reg[2]_0 ;
output s_axi_arready;
output FIFO_Full_reg;
output reset_TX_FIFO;
output reset_RX_FIFO;
output s_axi_awready;
output [0:0]bus2ip_rdce;
output enable_interrupts_reg_0;
output tx_Buffer_Empty_Pre_reg_0;
output rx_Data_Present_Pre_reg;
output [7:0]s_axi_rdata;
input bus2ip_reset;
input s_axi_aclk;
input tx_Buffer_Full;
input [0:0]Q;
input [7:0]out;
input rx_Buffer_Full;
input [0:0]\INFERRED_GEN.cnt_i_reg[4] ;
input enable_interrupts;
input [1:0]status_reg;
input s_axi_arvalid;
input [2:0]s_axi_wdata;
input s_axi_aresetn;
input s_axi_awvalid;
input s_axi_wvalid;
input s_axi_rready;
input s_axi_bready;
input [1:0]s_axi_awaddr;
input [1:0]s_axi_araddr;
wire FIFO_Full_reg;
wire \INFERRED_GEN.cnt_i_reg[2] ;
wire \INFERRED_GEN.cnt_i_reg[2]_0 ;
wire [0:0]\INFERRED_GEN.cnt_i_reg[4] ;
wire I_DECODER_n_15;
wire I_DECODER_n_16;
wire I_DECODER_n_25;
wire I_DECODER_n_26;
wire I_DECODER_n_27;
wire [0:0]Q;
wire [0:7]SIn_DBus;
wire \bus2ip_addr_i[2]_i_1_n_0 ;
wire \bus2ip_addr_i[3]_i_1_n_0 ;
wire \bus2ip_addr_i[3]_i_2_n_0 ;
wire \bus2ip_addr_i_reg_n_0_[2] ;
wire \bus2ip_addr_i_reg_n_0_[3] ;
wire [0:0]bus2ip_rdce;
wire bus2ip_reset;
wire bus2ip_rnw_i;
wire bus2ip_rnw_i_i_1_n_0;
wire enable_interrupts;
wire enable_interrupts_reg;
wire enable_interrupts_reg_0;
wire fifo_wr;
wire ip2bus_error;
wire [7:0]out;
wire reset_RX_FIFO;
wire reset_TX_FIFO;
wire rst;
wire rx_Buffer_Full;
wire rx_Data_Present_Pre_reg;
wire s_axi_aclk;
wire [1:0]s_axi_araddr;
wire s_axi_aresetn;
wire s_axi_arready;
wire s_axi_arvalid;
wire [1:0]s_axi_awaddr;
wire s_axi_awready;
wire s_axi_awvalid;
wire s_axi_bready;
wire [0:0]s_axi_bresp;
wire s_axi_bvalid;
wire [7:0]s_axi_rdata;
wire s_axi_rdata_i;
wire s_axi_rready;
wire [0:0]s_axi_rresp;
wire \s_axi_rresp_i_reg[1]_0 ;
wire s_axi_rvalid;
wire [2:0]s_axi_wdata;
wire s_axi_wvalid;
wire start2;
wire start2_i_1_n_0;
wire [1:0]state;
wire \state[0]_i_2_n_0 ;
wire \state[1]_i_2_n_0 ;
wire \state[1]_i_3_n_0 ;
wire [1:0]status_reg;
wire tx_Buffer_Empty_Pre_reg;
wire tx_Buffer_Empty_Pre_reg_0;
wire tx_Buffer_Full;
system_axi_uartlite_0_0_address_decoder I_DECODER
(.D({SIn_DBus[0],SIn_DBus[1],SIn_DBus[2],SIn_DBus[3],SIn_DBus[4],SIn_DBus[5],SIn_DBus[6],SIn_DBus[7]}),
.FIFO_Full_reg(FIFO_Full_reg),
.\INFERRED_GEN.cnt_i_reg[2] (\INFERRED_GEN.cnt_i_reg[2] ),
.\INFERRED_GEN.cnt_i_reg[2]_0 (\INFERRED_GEN.cnt_i_reg[2]_0 ),
.\INFERRED_GEN.cnt_i_reg[4] (\INFERRED_GEN.cnt_i_reg[4] ),
.Q(Q),
.\bus2ip_addr_i_reg[2] (\bus2ip_addr_i_reg_n_0_[2] ),
.\bus2ip_addr_i_reg[3] (\bus2ip_addr_i_reg_n_0_[3] ),
.bus2ip_rdce(bus2ip_rdce),
.bus2ip_rnw_i(bus2ip_rnw_i),
.enable_interrupts(enable_interrupts),
.enable_interrupts_reg(enable_interrupts_reg),
.enable_interrupts_reg_0(enable_interrupts_reg_0),
.fifo_wr(fifo_wr),
.ip2bus_error(ip2bus_error),
.out(out),
.reset_RX_FIFO(reset_RX_FIFO),
.reset_TX_FIFO(reset_TX_FIFO),
.rx_Buffer_Full(rx_Buffer_Full),
.rx_Data_Present_Pre_reg(rx_Data_Present_Pre_reg),
.s_axi_aclk(s_axi_aclk),
.s_axi_aresetn(s_axi_aresetn),
.s_axi_arready(s_axi_arready),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_awready(s_axi_awready),
.s_axi_bready(s_axi_bready),
.s_axi_bresp(s_axi_bresp),
.\s_axi_bresp_i_reg[1] (I_DECODER_n_27),
.s_axi_bvalid_i_reg(I_DECODER_n_26),
.s_axi_bvalid_i_reg_0(s_axi_bvalid),
.s_axi_rready(s_axi_rready),
.\s_axi_rresp_i_reg[1] (\s_axi_rresp_i_reg[1]_0 ),
.s_axi_rvalid_i_reg(I_DECODER_n_25),
.s_axi_rvalid_i_reg_0(s_axi_rvalid),
.s_axi_wdata(s_axi_wdata),
.s_axi_wvalid(\state[1]_i_3_n_0 ),
.start2(start2),
.\state_reg[0] (\state[0]_i_2_n_0 ),
.\state_reg[1] ({I_DECODER_n_15,I_DECODER_n_16}),
.\state_reg[1]_0 (\state[1]_i_2_n_0 ),
.\state_reg[1]_1 (state),
.status_reg(status_reg),
.tx_Buffer_Empty_Pre_reg(tx_Buffer_Empty_Pre_reg),
.tx_Buffer_Empty_Pre_reg_0(tx_Buffer_Empty_Pre_reg_0),
.tx_Buffer_Full(tx_Buffer_Full));
LUT5 #(
.INIT(32'hB8FFB800))
\bus2ip_addr_i[2]_i_1
(.I0(s_axi_awaddr[0]),
.I1(\bus2ip_addr_i[3]_i_2_n_0 ),
.I2(s_axi_araddr[0]),
.I3(start2_i_1_n_0),
.I4(\bus2ip_addr_i_reg_n_0_[2] ),
.O(\bus2ip_addr_i[2]_i_1_n_0 ));
LUT5 #(
.INIT(32'hB8FFB800))
\bus2ip_addr_i[3]_i_1
(.I0(s_axi_awaddr[1]),
.I1(\bus2ip_addr_i[3]_i_2_n_0 ),
.I2(s_axi_araddr[1]),
.I3(start2_i_1_n_0),
.I4(\bus2ip_addr_i_reg_n_0_[3] ),
.O(\bus2ip_addr_i[3]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair9" *)
LUT3 #(
.INIT(8'hEF))
\bus2ip_addr_i[3]_i_2
(.I0(state[1]),
.I1(state[0]),
.I2(s_axi_arvalid),
.O(\bus2ip_addr_i[3]_i_2_n_0 ));
FDRE \bus2ip_addr_i_reg[2]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\bus2ip_addr_i[2]_i_1_n_0 ),
.Q(\bus2ip_addr_i_reg_n_0_[2] ),
.R(rst));
FDRE \bus2ip_addr_i_reg[3]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\bus2ip_addr_i[3]_i_1_n_0 ),
.Q(\bus2ip_addr_i_reg_n_0_[3] ),
.R(rst));
LUT6 #(
.INIT(64'hFFFFFFF7000000F0))
bus2ip_rnw_i_i_1
(.I0(s_axi_awvalid),
.I1(s_axi_wvalid),
.I2(s_axi_arvalid),
.I3(state[0]),
.I4(state[1]),
.I5(bus2ip_rnw_i),
.O(bus2ip_rnw_i_i_1_n_0));
FDRE bus2ip_rnw_i_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(bus2ip_rnw_i_i_1_n_0),
.Q(bus2ip_rnw_i),
.R(rst));
FDRE rst_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(bus2ip_reset),
.Q(rst),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\s_axi_bresp_i_reg[1]
(.C(s_axi_aclk),
.CE(1'b1),
.D(I_DECODER_n_27),
.Q(s_axi_bresp),
.R(rst));
FDRE #(
.INIT(1'b0))
s_axi_bvalid_i_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(I_DECODER_n_26),
.Q(s_axi_bvalid),
.R(rst));
LUT2 #(
.INIT(4'h2))
\s_axi_rdata_i[7]_i_1
(.I0(state[0]),
.I1(state[1]),
.O(s_axi_rdata_i));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[0]
(.C(s_axi_aclk),
.CE(s_axi_rdata_i),
.D(SIn_DBus[7]),
.Q(s_axi_rdata[0]),
.R(rst));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[1]
(.C(s_axi_aclk),
.CE(s_axi_rdata_i),
.D(SIn_DBus[6]),
.Q(s_axi_rdata[1]),
.R(rst));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[2]
(.C(s_axi_aclk),
.CE(s_axi_rdata_i),
.D(SIn_DBus[5]),
.Q(s_axi_rdata[2]),
.R(rst));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[3]
(.C(s_axi_aclk),
.CE(s_axi_rdata_i),
.D(SIn_DBus[4]),
.Q(s_axi_rdata[3]),
.R(rst));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[4]
(.C(s_axi_aclk),
.CE(s_axi_rdata_i),
.D(SIn_DBus[3]),
.Q(s_axi_rdata[4]),
.R(rst));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[5]
(.C(s_axi_aclk),
.CE(s_axi_rdata_i),
.D(SIn_DBus[2]),
.Q(s_axi_rdata[5]),
.R(rst));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[6]
(.C(s_axi_aclk),
.CE(s_axi_rdata_i),
.D(SIn_DBus[1]),
.Q(s_axi_rdata[6]),
.R(rst));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[7]
(.C(s_axi_aclk),
.CE(s_axi_rdata_i),
.D(SIn_DBus[0]),
.Q(s_axi_rdata[7]),
.R(rst));
FDRE #(
.INIT(1'b0))
\s_axi_rresp_i_reg[1]
(.C(s_axi_aclk),
.CE(s_axi_rdata_i),
.D(ip2bus_error),
.Q(s_axi_rresp),
.R(rst));
FDRE #(
.INIT(1'b0))
s_axi_rvalid_i_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(I_DECODER_n_25),
.Q(s_axi_rvalid),
.R(rst));
(* SOFT_HLUTNM = "soft_lutpair9" *)
LUT5 #(
.INIT(32'h000000F8))
start2_i_1
(.I0(s_axi_awvalid),
.I1(s_axi_wvalid),
.I2(s_axi_arvalid),
.I3(state[0]),
.I4(state[1]),
.O(start2_i_1_n_0));
FDRE start2_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(start2_i_1_n_0),
.Q(start2),
.R(rst));
LUT5 #(
.INIT(32'h002A2A2A))
\state[0]_i_2
(.I0(state[0]),
.I1(s_axi_rvalid),
.I2(s_axi_rready),
.I3(s_axi_bready),
.I4(s_axi_bvalid),
.O(\state[0]_i_2_n_0 ));
LUT5 #(
.INIT(32'h002A2A2A))
\state[1]_i_2
(.I0(state[1]),
.I1(s_axi_rvalid),
.I2(s_axi_rready),
.I3(s_axi_bready),
.I4(s_axi_bvalid),
.O(\state[1]_i_2_n_0 ));
LUT2 #(
.INIT(4'h8))
\state[1]_i_3
(.I0(s_axi_awvalid),
.I1(s_axi_wvalid),
.O(\state[1]_i_3_n_0 ));
FDRE \state_reg[0]
(.C(s_axi_aclk),
.CE(1'b1),
.D(I_DECODER_n_16),
.Q(state[0]),
.R(rst));
FDRE \state_reg[1]
(.C(s_axi_aclk),
.CE(1'b1),
.D(I_DECODER_n_15),
.Q(state[1]),
.R(rst));
endmodule
|
module system_axi_uartlite_0_0_srl_fifo_f
(tx_Buffer_Full,
mux_Out,
Q,
tx_Start0,
s_axi_aclk,
p_4_in,
\mux_sel_reg[2] ,
\mux_sel_reg[0] ,
reset_TX_FIFO_reg,
s_axi_aresetn,
fifo_Read,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1] ,
Bus_RNW_reg,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg ,
tx_Data_Enable_reg,
tx_DataBits,
tx_Start,
fifo_wr,
s_axi_wdata);
output tx_Buffer_Full;
output mux_Out;
output [0:0]Q;
output tx_Start0;
input s_axi_aclk;
input p_4_in;
input \mux_sel_reg[2] ;
input \mux_sel_reg[0] ;
input reset_TX_FIFO_reg;
input s_axi_aresetn;
input fifo_Read;
input \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1] ;
input Bus_RNW_reg;
input \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg ;
input tx_Data_Enable_reg;
input tx_DataBits;
input tx_Start;
input fifo_wr;
input [7:0]s_axi_wdata;
wire Bus_RNW_reg;
wire \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg ;
wire \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1] ;
wire [0:0]Q;
wire fifo_Read;
wire fifo_wr;
wire mux_Out;
wire \mux_sel_reg[0] ;
wire \mux_sel_reg[2] ;
wire p_4_in;
wire reset_TX_FIFO_reg;
wire s_axi_aclk;
wire s_axi_aresetn;
wire [7:0]s_axi_wdata;
wire tx_Buffer_Full;
wire tx_DataBits;
wire tx_Data_Enable_reg;
wire tx_Start;
wire tx_Start0;
system_axi_uartlite_0_0_srl_fifo_rbu_f I_SRL_FIFO_RBU_F
(.Bus_RNW_reg(Bus_RNW_reg),
.\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg (\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg ),
.\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1] (\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1] ),
.Q(Q),
.fifo_Read(fifo_Read),
.fifo_wr(fifo_wr),
.mux_Out(mux_Out),
.\mux_sel_reg[0] (\mux_sel_reg[0] ),
.\mux_sel_reg[2] (\mux_sel_reg[2] ),
.p_4_in(p_4_in),
.reset_TX_FIFO_reg(reset_TX_FIFO_reg),
.s_axi_aclk(s_axi_aclk),
.s_axi_aresetn(s_axi_aresetn),
.s_axi_wdata(s_axi_wdata),
.tx_Buffer_Full(tx_Buffer_Full),
.tx_DataBits(tx_DataBits),
.tx_Data_Enable_reg(tx_Data_Enable_reg),
.tx_Start(tx_Start),
.tx_Start0(tx_Start0));
endmodule
|
module system_axi_uartlite_0_0_srl_fifo_f_0
(\status_reg_reg[2] ,
Q,
Interrupt0,
\status_reg_reg[2]_0 ,
out,
s_axi_aclk,
reset_RX_FIFO_reg,
s_axi_aresetn,
\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0] ,
Bus_RNW_reg,
\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg ,
Bus_RNW_reg_reg,
valid_rx,
fifo_Write,
rx_Data_Present_Pre,
enable_interrupts,
\INFERRED_GEN.cnt_i_reg[4] ,
tx_Buffer_Empty_Pre,
status_reg,
clr_Status,
in);
output \status_reg_reg[2] ;
output [0:0]Q;
output Interrupt0;
output \status_reg_reg[2]_0 ;
output [7:0]out;
input s_axi_aclk;
input reset_RX_FIFO_reg;
input s_axi_aresetn;
input \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0] ;
input Bus_RNW_reg;
input \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg ;
input Bus_RNW_reg_reg;
input valid_rx;
input fifo_Write;
input rx_Data_Present_Pre;
input enable_interrupts;
input [0:0]\INFERRED_GEN.cnt_i_reg[4] ;
input tx_Buffer_Empty_Pre;
input [0:0]status_reg;
input clr_Status;
input [0:7]in;
wire Bus_RNW_reg;
wire Bus_RNW_reg_reg;
wire \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg ;
wire \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0] ;
wire [0:0]\INFERRED_GEN.cnt_i_reg[4] ;
wire Interrupt0;
wire [0:0]Q;
wire clr_Status;
wire enable_interrupts;
wire fifo_Write;
wire [0:7]in;
wire [7:0]out;
wire reset_RX_FIFO_reg;
wire rx_Data_Present_Pre;
wire s_axi_aclk;
wire s_axi_aresetn;
wire [0:0]status_reg;
wire \status_reg_reg[2] ;
wire \status_reg_reg[2]_0 ;
wire tx_Buffer_Empty_Pre;
wire valid_rx;
system_axi_uartlite_0_0_srl_fifo_rbu_f_1 I_SRL_FIFO_RBU_F
(.Bus_RNW_reg(Bus_RNW_reg),
.Bus_RNW_reg_reg(Bus_RNW_reg_reg),
.\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg (\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg ),
.\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0] (\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0] ),
.\INFERRED_GEN.cnt_i_reg[4] (\INFERRED_GEN.cnt_i_reg[4] ),
.Interrupt0(Interrupt0),
.Q(Q),
.clr_Status(clr_Status),
.enable_interrupts(enable_interrupts),
.fifo_Write(fifo_Write),
.in(in),
.out(out),
.reset_RX_FIFO_reg(reset_RX_FIFO_reg),
.rx_Data_Present_Pre(rx_Data_Present_Pre),
.s_axi_aclk(s_axi_aclk),
.s_axi_aresetn(s_axi_aresetn),
.status_reg(status_reg),
.\status_reg_reg[2] (\status_reg_reg[2] ),
.\status_reg_reg[2]_0 (\status_reg_reg[2]_0 ),
.tx_Buffer_Empty_Pre(tx_Buffer_Empty_Pre),
.valid_rx(valid_rx));
endmodule
|
module system_axi_uartlite_0_0_srl_fifo_rbu_f
(tx_Buffer_Full,
mux_Out,
Q,
tx_Start0,
s_axi_aclk,
p_4_in,
\mux_sel_reg[2] ,
\mux_sel_reg[0] ,
reset_TX_FIFO_reg,
s_axi_aresetn,
fifo_Read,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1] ,
Bus_RNW_reg,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg ,
tx_Data_Enable_reg,
tx_DataBits,
tx_Start,
fifo_wr,
s_axi_wdata);
output tx_Buffer_Full;
output mux_Out;
output [0:0]Q;
output tx_Start0;
input s_axi_aclk;
input p_4_in;
input \mux_sel_reg[2] ;
input \mux_sel_reg[0] ;
input reset_TX_FIFO_reg;
input s_axi_aresetn;
input fifo_Read;
input \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1] ;
input Bus_RNW_reg;
input \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg ;
input tx_Data_Enable_reg;
input tx_DataBits;
input tx_Start;
input fifo_wr;
input [7:0]s_axi_wdata;
wire Bus_RNW_reg;
wire CNTR_INCR_DECR_ADDN_F_I_n_2;
wire CNTR_INCR_DECR_ADDN_F_I_n_3;
wire CNTR_INCR_DECR_ADDN_F_I_n_4;
wire CNTR_INCR_DECR_ADDN_F_I_n_5;
wire \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg ;
wire \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1] ;
wire [0:0]Q;
wire TX_FIFO_Reset;
wire fifo_Read;
wire fifo_full_p1;
wire fifo_wr;
wire mux_Out;
wire \mux_sel_reg[0] ;
wire \mux_sel_reg[2] ;
wire p_4_in;
wire reset_TX_FIFO_reg;
wire s_axi_aclk;
wire s_axi_aresetn;
wire [7:0]s_axi_wdata;
wire tx_Buffer_Full;
wire tx_DataBits;
wire tx_Data_Enable_reg;
wire tx_Start;
wire tx_Start0;
system_axi_uartlite_0_0_cntr_incr_decr_addn_f CNTR_INCR_DECR_ADDN_F_I
(.Bus_RNW_reg(Bus_RNW_reg),
.\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg (\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg ),
.\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1] (\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1] ),
.Q({Q,CNTR_INCR_DECR_ADDN_F_I_n_2,CNTR_INCR_DECR_ADDN_F_I_n_3,CNTR_INCR_DECR_ADDN_F_I_n_4,CNTR_INCR_DECR_ADDN_F_I_n_5}),
.SS(TX_FIFO_Reset),
.fifo_Read(fifo_Read),
.fifo_full_p1(fifo_full_p1),
.reset_TX_FIFO_reg(reset_TX_FIFO_reg),
.s_axi_aclk(s_axi_aclk),
.s_axi_aresetn(s_axi_aresetn),
.tx_Buffer_Full(tx_Buffer_Full),
.tx_DataBits(tx_DataBits),
.tx_Data_Enable_reg(tx_Data_Enable_reg),
.tx_Start(tx_Start),
.tx_Start0(tx_Start0));
system_axi_uartlite_0_0_dynshreg_f DYNSHREG_F_I
(.Q({CNTR_INCR_DECR_ADDN_F_I_n_2,CNTR_INCR_DECR_ADDN_F_I_n_3,CNTR_INCR_DECR_ADDN_F_I_n_4,CNTR_INCR_DECR_ADDN_F_I_n_5}),
.fifo_wr(fifo_wr),
.mux_Out(mux_Out),
.\mux_sel_reg[0] (\mux_sel_reg[0] ),
.\mux_sel_reg[2] (\mux_sel_reg[2] ),
.p_4_in(p_4_in),
.s_axi_aclk(s_axi_aclk),
.s_axi_wdata(s_axi_wdata));
FDRE FIFO_Full_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(fifo_full_p1),
.Q(tx_Buffer_Full),
.R(TX_FIFO_Reset));
endmodule
|
module system_axi_uartlite_0_0_srl_fifo_rbu_f_1
(\status_reg_reg[2] ,
Q,
Interrupt0,
\status_reg_reg[2]_0 ,
out,
s_axi_aclk,
reset_RX_FIFO_reg,
s_axi_aresetn,
\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0] ,
Bus_RNW_reg,
\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg ,
Bus_RNW_reg_reg,
valid_rx,
fifo_Write,
rx_Data_Present_Pre,
enable_interrupts,
\INFERRED_GEN.cnt_i_reg[4] ,
tx_Buffer_Empty_Pre,
status_reg,
clr_Status,
in);
output \status_reg_reg[2] ;
output [0:0]Q;
output Interrupt0;
output \status_reg_reg[2]_0 ;
output [7:0]out;
input s_axi_aclk;
input reset_RX_FIFO_reg;
input s_axi_aresetn;
input \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0] ;
input Bus_RNW_reg;
input \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg ;
input Bus_RNW_reg_reg;
input valid_rx;
input fifo_Write;
input rx_Data_Present_Pre;
input enable_interrupts;
input [0:0]\INFERRED_GEN.cnt_i_reg[4] ;
input tx_Buffer_Empty_Pre;
input [0:0]status_reg;
input clr_Status;
input [0:7]in;
wire Bus_RNW_reg;
wire Bus_RNW_reg_reg;
wire CNTR_INCR_DECR_ADDN_F_I_n_3;
wire CNTR_INCR_DECR_ADDN_F_I_n_4;
wire CNTR_INCR_DECR_ADDN_F_I_n_5;
wire CNTR_INCR_DECR_ADDN_F_I_n_6;
wire \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg ;
wire \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0] ;
wire [0:0]\INFERRED_GEN.cnt_i_reg[4] ;
wire Interrupt0;
wire [0:0]Q;
wire RX_FIFO_Reset;
wire clr_Status;
wire enable_interrupts;
wire fifo_Write;
wire fifo_full_p1;
wire [0:7]in;
wire [7:0]out;
wire reset_RX_FIFO_reg;
wire rx_Data_Present_Pre;
wire s_axi_aclk;
wire s_axi_aresetn;
wire [0:0]status_reg;
wire \status_reg_reg[2] ;
wire \status_reg_reg[2]_0 ;
wire tx_Buffer_Empty_Pre;
wire valid_rx;
system_axi_uartlite_0_0_cntr_incr_decr_addn_f_2 CNTR_INCR_DECR_ADDN_F_I
(.Bus_RNW_reg(Bus_RNW_reg),
.Bus_RNW_reg_reg(Bus_RNW_reg_reg),
.FIFO_Full_reg(\status_reg_reg[2] ),
.\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg (\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg ),
.\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0] (\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0] ),
.\INFERRED_GEN.cnt_i_reg[4]_0 (\INFERRED_GEN.cnt_i_reg[4] ),
.Interrupt0(Interrupt0),
.Q({Q,CNTR_INCR_DECR_ADDN_F_I_n_3,CNTR_INCR_DECR_ADDN_F_I_n_4,CNTR_INCR_DECR_ADDN_F_I_n_5,CNTR_INCR_DECR_ADDN_F_I_n_6}),
.SS(RX_FIFO_Reset),
.enable_interrupts(enable_interrupts),
.fifo_Write(fifo_Write),
.fifo_full_p1(fifo_full_p1),
.reset_RX_FIFO_reg(reset_RX_FIFO_reg),
.rx_Data_Present_Pre(rx_Data_Present_Pre),
.s_axi_aclk(s_axi_aclk),
.s_axi_aresetn(s_axi_aresetn),
.tx_Buffer_Empty_Pre(tx_Buffer_Empty_Pre),
.valid_rx(valid_rx));
system_axi_uartlite_0_0_dynshreg_f_3 DYNSHREG_F_I
(.FIFO_Full_reg(\status_reg_reg[2] ),
.Q({CNTR_INCR_DECR_ADDN_F_I_n_3,CNTR_INCR_DECR_ADDN_F_I_n_4,CNTR_INCR_DECR_ADDN_F_I_n_5,CNTR_INCR_DECR_ADDN_F_I_n_6}),
.fifo_Write(fifo_Write),
.in(in),
.out(out),
.s_axi_aclk(s_axi_aclk),
.valid_rx(valid_rx));
FDRE FIFO_Full_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(fifo_full_p1),
.Q(\status_reg_reg[2] ),
.R(RX_FIFO_Reset));
LUT5 #(
.INIT(32'h0000EA00))
\status_reg[2]_i_1
(.I0(status_reg),
.I1(fifo_Write),
.I2(\status_reg_reg[2] ),
.I3(s_axi_aresetn),
.I4(clr_Status),
.O(\status_reg_reg[2]_0 ));
endmodule
|
module system_axi_uartlite_0_0_uartlite_core
(status_reg,
bus2ip_reset,
rx_Buffer_Full,
tx_Buffer_Full,
tx,
interrupt,
enable_interrupts,
Q,
FIFO_Full_reg,
out,
s_axi_aclk,
reset_TX_FIFO,
reset_RX_FIFO,
bus2ip_rdce,
\GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg[3] ,
\INFERRED_GEN.cnt_i_reg[4] ,
\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0] ,
s_axi_aresetn,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1] ,
Bus_RNW_reg,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg ,
\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]_0 ,
\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg ,
Bus_RNW_reg_reg,
rx,
fifo_wr,
s_axi_wdata);
output [1:0]status_reg;
output bus2ip_reset;
output rx_Buffer_Full;
output tx_Buffer_Full;
output tx;
output interrupt;
output enable_interrupts;
output [0:0]Q;
output [0:0]FIFO_Full_reg;
output [7:0]out;
input s_axi_aclk;
input reset_TX_FIFO;
input reset_RX_FIFO;
input [0:0]bus2ip_rdce;
input \GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg[3] ;
input \INFERRED_GEN.cnt_i_reg[4] ;
input \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0] ;
input s_axi_aresetn;
input \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1] ;
input Bus_RNW_reg;
input \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg ;
input \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]_0 ;
input \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg ;
input Bus_RNW_reg_reg;
input rx;
input fifo_wr;
input [7:0]s_axi_wdata;
wire Bus_RNW_reg;
wire Bus_RNW_reg_reg;
wire [0:0]FIFO_Full_reg;
wire \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg ;
wire \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0] ;
wire \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]_0 ;
wire \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg ;
wire \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1] ;
wire \GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg[3] ;
wire \INFERRED_GEN.cnt_i_reg[4] ;
wire Interrupt0;
wire [0:0]Q;
wire UARTLITE_RX_I_n_5;
wire [0:0]bus2ip_rdce;
wire bus2ip_reset;
wire clr_Status;
wire en_16x_Baud;
wire enable_interrupts;
wire fifo_wr;
wire interrupt;
wire [7:0]out;
wire reset_RX_FIFO;
wire reset_RX_FIFO_reg_n_0;
wire reset_TX_FIFO;
wire reset_TX_FIFO_reg_n_0;
wire rx;
wire rx_Buffer_Full;
wire rx_Data_Present_Pre;
wire s_axi_aclk;
wire s_axi_aresetn;
wire [7:0]s_axi_wdata;
wire [1:0]status_reg;
wire status_reg_reg0;
wire tx;
wire tx_Buffer_Empty_Pre;
wire tx_Buffer_Full;
system_axi_uartlite_0_0_baudrate BAUD_RATE_I
(.SR(bus2ip_reset),
.en_16x_Baud(en_16x_Baud),
.s_axi_aclk(s_axi_aclk));
FDRE Interrupt_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(Interrupt0),
.Q(interrupt),
.R(bus2ip_reset));
system_axi_uartlite_0_0_uartlite_rx UARTLITE_RX_I
(.Bus_RNW_reg(Bus_RNW_reg),
.Bus_RNW_reg_reg(Bus_RNW_reg_reg),
.\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg (\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg ),
.\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0] (\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]_0 ),
.\INFERRED_GEN.cnt_i_reg[4] (Q),
.Interrupt0(Interrupt0),
.Q(FIFO_Full_reg),
.SR(bus2ip_reset),
.clr_Status(clr_Status),
.en_16x_Baud(en_16x_Baud),
.enable_interrupts(enable_interrupts),
.out(out),
.reset_RX_FIFO_reg(reset_RX_FIFO_reg_n_0),
.rx(rx),
.rx_Data_Present_Pre(rx_Data_Present_Pre),
.s_axi_aclk(s_axi_aclk),
.s_axi_aresetn(s_axi_aresetn),
.status_reg(status_reg),
.status_reg_reg0(status_reg_reg0),
.\status_reg_reg[2] (rx_Buffer_Full),
.\status_reg_reg[2]_0 (UARTLITE_RX_I_n_5),
.tx_Buffer_Empty_Pre(tx_Buffer_Empty_Pre));
system_axi_uartlite_0_0_uartlite_tx UARTLITE_TX_I
(.Bus_RNW_reg(Bus_RNW_reg),
.\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg (\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg ),
.\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1] (\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1] ),
.Q(Q),
.SR(bus2ip_reset),
.en_16x_Baud(en_16x_Baud),
.fifo_wr(fifo_wr),
.reset_TX_FIFO_reg(reset_TX_FIFO_reg_n_0),
.s_axi_aclk(s_axi_aclk),
.s_axi_aresetn(s_axi_aresetn),
.s_axi_wdata(s_axi_wdata),
.tx(tx),
.tx_Buffer_Full(tx_Buffer_Full));
FDRE clr_Status_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(bus2ip_rdce),
.Q(clr_Status),
.R(bus2ip_reset));
FDRE enable_interrupts_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(\GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg[3] ),
.Q(enable_interrupts),
.R(bus2ip_reset));
FDSE reset_RX_FIFO_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(reset_RX_FIFO),
.Q(reset_RX_FIFO_reg_n_0),
.S(bus2ip_reset));
FDSE reset_TX_FIFO_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(reset_TX_FIFO),
.Q(reset_TX_FIFO_reg_n_0),
.S(bus2ip_reset));
FDRE rx_Data_Present_Pre_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0] ),
.Q(rx_Data_Present_Pre),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\status_reg_reg[1]
(.C(s_axi_aclk),
.CE(1'b1),
.D(status_reg_reg0),
.Q(status_reg[1]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\status_reg_reg[2]
(.C(s_axi_aclk),
.CE(1'b1),
.D(UARTLITE_RX_I_n_5),
.Q(status_reg[0]),
.R(1'b0));
FDRE tx_Buffer_Empty_Pre_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(\INFERRED_GEN.cnt_i_reg[4] ),
.Q(tx_Buffer_Empty_Pre),
.R(1'b0));
endmodule
|
module system_axi_uartlite_0_0_uartlite_rx
(\status_reg_reg[2] ,
SR,
status_reg_reg0,
Q,
Interrupt0,
\status_reg_reg[2]_0 ,
out,
s_axi_aclk,
en_16x_Baud,
s_axi_aresetn,
clr_Status,
status_reg,
reset_RX_FIFO_reg,
\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0] ,
Bus_RNW_reg,
\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg ,
Bus_RNW_reg_reg,
rx_Data_Present_Pre,
enable_interrupts,
\INFERRED_GEN.cnt_i_reg[4] ,
tx_Buffer_Empty_Pre,
rx);
output \status_reg_reg[2] ;
output [0:0]SR;
output status_reg_reg0;
output [0:0]Q;
output Interrupt0;
output \status_reg_reg[2]_0 ;
output [7:0]out;
input s_axi_aclk;
input en_16x_Baud;
input s_axi_aresetn;
input clr_Status;
input [1:0]status_reg;
input reset_RX_FIFO_reg;
input \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0] ;
input Bus_RNW_reg;
input \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg ;
input Bus_RNW_reg_reg;
input rx_Data_Present_Pre;
input enable_interrupts;
input [0:0]\INFERRED_GEN.cnt_i_reg[4] ;
input tx_Buffer_Empty_Pre;
input rx;
wire Bus_RNW_reg;
wire Bus_RNW_reg_reg;
wire DELAY_16_I_n_1;
wire DELAY_16_I_n_10;
wire DELAY_16_I_n_11;
wire DELAY_16_I_n_12;
wire \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg ;
wire \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0] ;
wire [0:0]\INFERRED_GEN.cnt_i_reg[4] ;
wire Interrupt0;
wire [0:0]Q;
wire RX_D2;
wire [0:0]SR;
wire clr_Status;
wire en_16x_Baud;
wire enable_interrupts;
wire fifo_Write;
wire fifo_Write0;
wire [1:8]fifo_din;
wire frame_err_ocrd;
wire [7:0]out;
wire p_11_out;
wire p_14_out;
wire p_17_out;
wire p_20_out;
wire p_26_out;
wire p_2_out;
wire p_5_out;
wire p_8_out;
wire reset_RX_FIFO_reg;
wire running_reg_n_0;
wire rx;
wire rx_1;
wire rx_2;
wire rx_3;
wire rx_4;
wire rx_5;
wire rx_6;
wire rx_7;
wire rx_8;
wire rx_9;
wire rx_Data_Present_Pre;
wire s_axi_aclk;
wire s_axi_aresetn;
wire start_Edge_Detected;
wire start_Edge_Detected0;
wire start_Edge_Detected_i_2_n_0;
wire [1:0]status_reg;
wire status_reg_reg0;
wire \status_reg_reg[2] ;
wire \status_reg_reg[2]_0 ;
wire stop_Bit_Position_reg_n_0;
wire tx_Buffer_Empty_Pre;
wire valid_rx;
wire valid_rx_i_1_n_0;
system_axi_uartlite_0_0_dynshreg_i_f DELAY_16_I
(.\SERIAL_TO_PARALLEL[2].fifo_din_reg[2] (DELAY_16_I_n_1),
.clr_Status(clr_Status),
.en_16x_Baud(en_16x_Baud),
.fifo_Write0(fifo_Write0),
.frame_err_ocrd(frame_err_ocrd),
.frame_err_ocrd_reg(DELAY_16_I_n_11),
.in(fifo_din),
.p_11_out(p_11_out),
.p_14_out(p_14_out),
.p_17_out(p_17_out),
.p_20_out(p_20_out),
.p_2_out(p_2_out),
.p_5_out(p_5_out),
.p_8_out(p_8_out),
.running_reg(DELAY_16_I_n_12),
.running_reg_0(running_reg_n_0),
.s_axi_aclk(s_axi_aclk),
.s_axi_aresetn(s_axi_aresetn),
.scndry_out(RX_D2),
.start_Edge_Detected(start_Edge_Detected),
.status_reg(status_reg[1]),
.status_reg_reg0(status_reg_reg0),
.stop_Bit_Position_reg(DELAY_16_I_n_10),
.stop_Bit_Position_reg_0(stop_Bit_Position_reg_n_0),
.valid_rx(valid_rx));
system_axi_uartlite_0_0_cdc_sync INPUT_DOUBLE_REGS3
(.EN_16x_Baud_reg(DELAY_16_I_n_1),
.in(fifo_din[1]),
.p_26_out(p_26_out),
.rx(rx),
.s_axi_aclk(s_axi_aclk),
.s_axi_aresetn(s_axi_aresetn),
.scndry_out(RX_D2),
.start_Edge_Detected(start_Edge_Detected));
LUT1 #(
.INIT(2'h1))
Interrupt_i_1
(.I0(s_axi_aresetn),
.O(SR));
FDRE \SERIAL_TO_PARALLEL[1].fifo_din_reg[1]
(.C(s_axi_aclk),
.CE(1'b1),
.D(p_26_out),
.Q(fifo_din[1]),
.R(1'b0));
FDRE \SERIAL_TO_PARALLEL[2].fifo_din_reg[2]
(.C(s_axi_aclk),
.CE(1'b1),
.D(p_20_out),
.Q(fifo_din[2]),
.R(1'b0));
FDRE \SERIAL_TO_PARALLEL[3].fifo_din_reg[3]
(.C(s_axi_aclk),
.CE(1'b1),
.D(p_17_out),
.Q(fifo_din[3]),
.R(1'b0));
FDRE \SERIAL_TO_PARALLEL[4].fifo_din_reg[4]
(.C(s_axi_aclk),
.CE(1'b1),
.D(p_14_out),
.Q(fifo_din[4]),
.R(1'b0));
FDRE \SERIAL_TO_PARALLEL[5].fifo_din_reg[5]
(.C(s_axi_aclk),
.CE(1'b1),
.D(p_11_out),
.Q(fifo_din[5]),
.R(1'b0));
FDRE \SERIAL_TO_PARALLEL[6].fifo_din_reg[6]
(.C(s_axi_aclk),
.CE(1'b1),
.D(p_8_out),
.Q(fifo_din[6]),
.R(1'b0));
FDRE \SERIAL_TO_PARALLEL[7].fifo_din_reg[7]
(.C(s_axi_aclk),
.CE(1'b1),
.D(p_5_out),
.Q(fifo_din[7]),
.R(1'b0));
FDRE \SERIAL_TO_PARALLEL[8].fifo_din_reg[8]
(.C(s_axi_aclk),
.CE(1'b1),
.D(p_2_out),
.Q(fifo_din[8]),
.R(1'b0));
system_axi_uartlite_0_0_srl_fifo_f_0 SRL_FIFO_I
(.Bus_RNW_reg(Bus_RNW_reg),
.Bus_RNW_reg_reg(Bus_RNW_reg_reg),
.\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg (\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg ),
.\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0] (\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0] ),
.\INFERRED_GEN.cnt_i_reg[4] (\INFERRED_GEN.cnt_i_reg[4] ),
.Interrupt0(Interrupt0),
.Q(Q),
.clr_Status(clr_Status),
.enable_interrupts(enable_interrupts),
.fifo_Write(fifo_Write),
.in(fifo_din),
.out(out),
.reset_RX_FIFO_reg(reset_RX_FIFO_reg),
.rx_Data_Present_Pre(rx_Data_Present_Pre),
.s_axi_aclk(s_axi_aclk),
.s_axi_aresetn(s_axi_aresetn),
.status_reg(status_reg[0]),
.\status_reg_reg[2] (\status_reg_reg[2] ),
.\status_reg_reg[2]_0 (\status_reg_reg[2]_0 ),
.tx_Buffer_Empty_Pre(tx_Buffer_Empty_Pre),
.valid_rx(valid_rx));
FDRE fifo_Write_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(fifo_Write0),
.Q(fifo_Write),
.R(SR));
FDRE frame_err_ocrd_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(DELAY_16_I_n_11),
.Q(frame_err_ocrd),
.R(SR));
FDRE running_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(DELAY_16_I_n_12),
.Q(running_reg_n_0),
.R(SR));
FDRE rx_1_reg
(.C(s_axi_aclk),
.CE(en_16x_Baud),
.D(RX_D2),
.Q(rx_1),
.R(SR));
FDRE rx_2_reg
(.C(s_axi_aclk),
.CE(en_16x_Baud),
.D(rx_1),
.Q(rx_2),
.R(SR));
FDRE rx_3_reg
(.C(s_axi_aclk),
.CE(en_16x_Baud),
.D(rx_2),
.Q(rx_3),
.R(SR));
FDRE rx_4_reg
(.C(s_axi_aclk),
.CE(en_16x_Baud),
.D(rx_3),
.Q(rx_4),
.R(SR));
FDRE rx_5_reg
(.C(s_axi_aclk),
.CE(en_16x_Baud),
.D(rx_4),
.Q(rx_5),
.R(SR));
FDRE rx_6_reg
(.C(s_axi_aclk),
.CE(en_16x_Baud),
.D(rx_5),
.Q(rx_6),
.R(SR));
FDRE rx_7_reg
(.C(s_axi_aclk),
.CE(en_16x_Baud),
.D(rx_6),
.Q(rx_7),
.R(SR));
FDRE rx_8_reg
(.C(s_axi_aclk),
.CE(en_16x_Baud),
.D(rx_7),
.Q(rx_8),
.R(SR));
FDRE rx_9_reg
(.C(s_axi_aclk),
.CE(en_16x_Baud),
.D(rx_8),
.Q(rx_9),
.R(SR));
LUT6 #(
.INIT(64'h0000000000000010))
start_Edge_Detected_i_1
(.I0(rx_8),
.I1(rx_2),
.I2(start_Edge_Detected_i_2_n_0),
.I3(rx_3),
.I4(rx_1),
.I5(frame_err_ocrd),
.O(start_Edge_Detected0));
LUT6 #(
.INIT(64'h0000000000000010))
start_Edge_Detected_i_2
(.I0(rx_5),
.I1(rx_7),
.I2(rx_9),
.I3(running_reg_n_0),
.I4(rx_6),
.I5(rx_4),
.O(start_Edge_Detected_i_2_n_0));
FDRE start_Edge_Detected_reg
(.C(s_axi_aclk),
.CE(en_16x_Baud),
.D(start_Edge_Detected0),
.Q(start_Edge_Detected),
.R(SR));
FDRE stop_Bit_Position_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(DELAY_16_I_n_10),
.Q(stop_Bit_Position_reg_n_0),
.R(SR));
LUT3 #(
.INIT(8'hBA))
valid_rx_i_1
(.I0(start_Edge_Detected),
.I1(fifo_Write),
.I2(valid_rx),
.O(valid_rx_i_1_n_0));
FDRE valid_rx_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(valid_rx_i_1_n_0),
.Q(valid_rx),
.R(SR));
endmodule
|
module system_axi_uartlite_0_0_uartlite_tx
(tx_Buffer_Full,
tx,
Q,
s_axi_aclk,
SR,
en_16x_Baud,
reset_TX_FIFO_reg,
s_axi_aresetn,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1] ,
Bus_RNW_reg,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg ,
fifo_wr,
s_axi_wdata);
output tx_Buffer_Full;
output tx;
output [0:0]Q;
input s_axi_aclk;
input [0:0]SR;
input en_16x_Baud;
input reset_TX_FIFO_reg;
input s_axi_aresetn;
input \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1] ;
input Bus_RNW_reg;
input \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg ;
input fifo_wr;
input [7:0]s_axi_wdata;
wire Bus_RNW_reg;
wire \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg ;
wire \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1] ;
wire MID_START_BIT_SRL16_I_n_0;
wire [0:0]Q;
wire [0:0]SR;
wire TX0;
wire en_16x_Baud;
wire fifo_Read;
wire fifo_Read0;
wire fifo_wr;
wire mux_Out;
wire \mux_sel[0]_i_1_n_0 ;
wire \mux_sel[1]_i_1_n_0 ;
wire \mux_sel[2]_i_1_n_0 ;
wire \mux_sel_reg_n_0_[0] ;
wire \mux_sel_reg_n_0_[2] ;
wire p_4_in;
wire reset_TX_FIFO_reg;
wire s_axi_aclk;
wire s_axi_aresetn;
wire [7:0]s_axi_wdata;
wire serial_Data;
wire tx;
wire tx_Buffer_Full;
wire tx_DataBits;
wire tx_DataBits0;
wire tx_Data_Enable_reg_n_0;
wire tx_Start;
wire tx_Start0;
system_axi_uartlite_0_0_dynshreg_i_f__parameterized0 MID_START_BIT_SRL16_I
(.en_16x_Baud(en_16x_Baud),
.s_axi_aclk(s_axi_aclk),
.tx_Data_Enable_reg(MID_START_BIT_SRL16_I_n_0),
.tx_Data_Enable_reg_0(tx_Data_Enable_reg_n_0));
system_axi_uartlite_0_0_srl_fifo_f SRL_FIFO_I
(.Bus_RNW_reg(Bus_RNW_reg),
.\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg (\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg ),
.\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1] (\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1] ),
.Q(Q),
.fifo_Read(fifo_Read),
.fifo_wr(fifo_wr),
.mux_Out(mux_Out),
.\mux_sel_reg[0] (\mux_sel_reg_n_0_[0] ),
.\mux_sel_reg[2] (\mux_sel_reg_n_0_[2] ),
.p_4_in(p_4_in),
.reset_TX_FIFO_reg(reset_TX_FIFO_reg),
.s_axi_aclk(s_axi_aclk),
.s_axi_aresetn(s_axi_aresetn),
.s_axi_wdata(s_axi_wdata),
.tx_Buffer_Full(tx_Buffer_Full),
.tx_DataBits(tx_DataBits),
.tx_Data_Enable_reg(tx_Data_Enable_reg_n_0),
.tx_Start(tx_Start),
.tx_Start0(tx_Start0));
LUT3 #(
.INIT(8'h31))
TX_i_1
(.I0(tx_DataBits),
.I1(tx_Start),
.I2(serial_Data),
.O(TX0));
FDSE TX_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(TX0),
.Q(tx),
.S(SR));
LUT4 #(
.INIT(16'h0100))
fifo_Read_i_1
(.I0(\mux_sel_reg_n_0_[0] ),
.I1(\mux_sel_reg_n_0_[2] ),
.I2(p_4_in),
.I3(tx_Data_Enable_reg_n_0),
.O(fifo_Read0));
FDRE fifo_Read_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(fifo_Read0),
.Q(fifo_Read),
.R(SR));
(* SOFT_HLUTNM = "soft_lutpair20" *)
LUT5 #(
.INIT(32'hE1F0F1F0))
\mux_sel[0]_i_1
(.I0(p_4_in),
.I1(\mux_sel_reg_n_0_[2] ),
.I2(\mux_sel_reg_n_0_[0] ),
.I3(tx_Data_Enable_reg_n_0),
.I4(tx_DataBits),
.O(\mux_sel[0]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair20" *)
LUT5 #(
.INIT(32'h99AAABAA))
\mux_sel[1]_i_1
(.I0(p_4_in),
.I1(\mux_sel_reg_n_0_[2] ),
.I2(\mux_sel_reg_n_0_[0] ),
.I3(tx_Data_Enable_reg_n_0),
.I4(tx_DataBits),
.O(\mux_sel[1]_i_1_n_0 ));
LUT5 #(
.INIT(32'h7777888C))
\mux_sel[2]_i_1
(.I0(tx_DataBits),
.I1(tx_Data_Enable_reg_n_0),
.I2(\mux_sel_reg_n_0_[0] ),
.I3(p_4_in),
.I4(\mux_sel_reg_n_0_[2] ),
.O(\mux_sel[2]_i_1_n_0 ));
FDSE \mux_sel_reg[0]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\mux_sel[0]_i_1_n_0 ),
.Q(\mux_sel_reg_n_0_[0] ),
.S(SR));
FDSE \mux_sel_reg[1]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\mux_sel[1]_i_1_n_0 ),
.Q(p_4_in),
.S(SR));
FDSE \mux_sel_reg[2]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\mux_sel[2]_i_1_n_0 ),
.Q(\mux_sel_reg_n_0_[2] ),
.S(SR));
FDRE serial_Data_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(mux_Out),
.Q(serial_Data),
.R(SR));
LUT4 #(
.INIT(16'h0F08))
tx_DataBits_i_1
(.I0(tx_Start),
.I1(tx_Data_Enable_reg_n_0),
.I2(fifo_Read),
.I3(tx_DataBits),
.O(tx_DataBits0));
FDRE tx_DataBits_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(tx_DataBits0),
.Q(tx_DataBits),
.R(SR));
FDRE tx_Data_Enable_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(MID_START_BIT_SRL16_I_n_0),
.Q(tx_Data_Enable_reg_n_0),
.R(SR));
FDRE tx_Start_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(tx_Start0),
.Q(tx_Start),
.R(SR));
endmodule
|
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
|
module mrx_io (/*AUTOARG*/
// Outputs
io_access, io_packet,
// Inputs
nreset, rx_clk, ddr_mode, lsbfirst, framepol, rx_packet, rx_access
);
//#####################################################################
//# INTERFACE
//#####################################################################
//parameters
parameter NMIO = 16;
//RESET
input nreset; // async active low reset
input rx_clk; // clock for IO
input ddr_mode; // select between sdr/ddr data
input lsbfirst; // shufle data in msbfirst mode
input framepol; // frame polarity
//IO interface
input [NMIO-1:0] rx_packet; // data for IO
input rx_access; // access signal for IO
//FIFO interface (core side)
output io_access; // fifo packet valid
output [2*NMIO-1:0] io_packet; // fifo packet
//#####################################################################
//# BODY
//#####################################################################
//regs
reg io_access;
wire [2*NMIO-1:0] ddr_data;
reg [2*NMIO-1:0] sdr_data;
reg byte0_sel;
wire io_nreset;
wire rx_frame;
//########################################
//# CLOCK, RESET
//########################################
//synchronize reset to rx_clk
oh_rsync oh_rsync(.nrst_out (io_nreset),
.clk (rx_clk),
.nrst_in (nreset)
);
//########################################
//# SELECT FRAME POLARITY
//########################################
assign rx_frame = framepol ^ rx_access;
//########################################
//# ACCESS (SDR)
//########################################
always @ (posedge rx_clk or negedge io_nreset)
if(!io_nreset)
io_access <= 1'b0;
else
io_access <= rx_frame;
//########################################
//# DATA (DDR)
//########################################
oh_iddr #(.DW(NMIO))
data_iddr(.q1 (ddr_data[NMIO-1:0]),
.q2 (ddr_data[2*NMIO-1:NMIO]),
.clk (rx_clk),
.ce (rx_frame),
.din (rx_packet[NMIO-1:0]));
//########################################
//# DATA (SDR)
//########################################
//select 2nd byte (stall on this signal)
always @ (posedge rx_clk)
if(~rx_frame)
byte0_sel <= 1'b1;
else if (~ddr_mode)
byte0_sel <= rx_frame ^ byte0_sel;
always @ (posedge rx_clk)
if(byte0_sel)
sdr_data[NMIO-1:0] <= rx_packet[NMIO-1:0];
else
sdr_data[2*NMIO-1:NMIO] <= rx_packet[NMIO-1:0];
//########################################
//# HANDL DDR/SDR
//########################################
assign io_packet[2*NMIO-1:0] = ~ddr_mode ? sdr_data[2*NMIO-1:0] :
ddr_mode & ~lsbfirst ? {ddr_data[NMIO-1:0],
ddr_data[2*NMIO-1:NMIO]} :
ddr_data[2*NMIO-1:0];
endmodule
|
module Decoder4_16(D0, D1, D2, D3, D4, D5, D6, D7, D8, D9, D10, D11, D12, D13, D14, D15, A, E);
output D0;
output D1;
output D2;
output D3;
output D4;
output D5;
output D6;
output D7;
output D8;
output D9;
output D10;
output D11;
output D12;
output D13;
output D14;
output D15;
input [3:0] A;
input E;
reg D0;
reg D1;
reg D2;
reg D3;
reg D4;
reg D5;
reg D6;
reg D7;
reg D8;
reg D9;
reg D10;
reg D11;
reg D12;
reg D13;
reg D14;
reg D15;
always @ (A or E)
begin
if(!E)
{D15, D14, D13, D12, D11, D10, D9, D8, D7, D6, D5, D4, D3, D2, D1, D0} <= 16'b0000_0000_0000_0000;
else
begin
case(A)
4'b0000 : {D15, D14, D13, D12, D11, D10, D9, D8, D7, D6, D5, D4, D3, D2, D1, D0} <= 16'b0000_0000_0000_0001;
4'b0001 : {D15, D14, D13, D12, D11, D10, D9, D8, D7, D6, D5, D4, D3, D2, D1, D0} <= 16'b0000_0000_0000_0010;
4'b0010 : {D15, D14, D13, D12, D11, D10, D9, D8, D7, D6, D5, D4, D3, D2, D1, D0} <= 16'b0000_0000_0000_0100;
4'b0011 : {D15, D14, D13, D12, D11, D10, D9, D8, D7, D6, D5, D4, D3, D2, D1, D0} <= 16'b0000_0000_0000_1000;
4'b0100 : {D15, D14, D13, D12, D11, D10, D9, D8, D7, D6, D5, D4, D3, D2, D1, D0} <= 16'b0000_0000_0001_0000;
4'b0101 : {D15, D14, D13, D12, D11, D10, D9, D8, D7, D6, D5, D4, D3, D2, D1, D0} <= 16'b0000_0000_0010_0000;
4'b0110 : {D15, D14, D13, D12, D11, D10, D9, D8, D7, D6, D5, D4, D3, D2, D1, D0} <= 16'b0000_0000_0100_0000;
4'b0111 : {D15, D14, D13, D12, D11, D10, D9, D8, D7, D6, D5, D4, D3, D2, D1, D0} <= 16'b0000_0000_1000_0000;
4'b1000 : {D15, D14, D13, D12, D11, D10, D9, D8, D7, D6, D5, D4, D3, D2, D1, D0} <= 16'b0000_0001_0000_0000;
4'b1001 : {D15, D14, D13, D12, D11, D10, D9, D8, D7, D6, D5, D4, D3, D2, D1, D0} <= 16'b0000_0010_0000_0000;
4'b1010 : {D15, D14, D13, D12, D11, D10, D9, D8, D7, D6, D5, D4, D3, D2, D1, D0} <= 16'b0000_0100_0000_0000;
4'b1011 : {D15, D14, D13, D12, D11, D10, D9, D8, D7, D6, D5, D4, D3, D2, D1, D0} <= 16'b0000_1000_0000_0000;
4'b1100 : {D15, D14, D13, D12, D11, D10, D9, D8, D7, D6, D5, D4, D3, D2, D1, D0} <= 16'b0001_0000_0000_0000;
4'b1101 : {D15, D14, D13, D12, D11, D10, D9, D8, D7, D6, D5, D4, D3, D2, D1, D0} <= 16'b0010_0000_0000_0000;
4'b1110 : {D15, D14, D13, D12, D11, D10, D9, D8, D7, D6, D5, D4, D3, D2, D1, D0} <= 16'b0100_0000_0000_0000;
4'b1111 : {D15, D14, D13, D12, D11, D10, D9, D8, D7, D6, D5, D4, D3, D2, D1, D0} <= 16'b1000_0000_0000_0000;
endcase
end
end
endmodule
|
module sky130_fd_sc_hd__lpflow_bleeder (
//# {{power|Power}}
input SHORT,
input VPB ,
inout VPWR ,
input VGND ,
input VNB
);
endmodule
|
module sky130_fd_sc_hd__o211a (
X ,
A1,
A2,
B1,
C1
);
// Module ports
output X ;
input A1;
input A2;
input B1;
input C1;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire or0_out ;
wire and0_out_X;
// Name Output Other arguments
or or0 (or0_out , A2, A1 );
and and0 (and0_out_X, or0_out, B1, C1);
buf buf0 (X , and0_out_X );
endmodule
|
module padder1(in, byte_num, out);
input [31:0] in;
input [1:0] byte_num;
output reg [31:0] out;
always @ (*)
case (byte_num)
0: out = 32'h1000000;
1: out = {in[31:24], 24'h010000};
2: out = {in[31:16], 16'h0100};
3: out = {in[31:8], 8'h01};
endcase
endmodule
|
module vga_sync
(
input wire clk, reset,
output wire hsync, vsync, video_on, p_tick,
// hysnc, vsync is the output sync signal
// ptick is used for other circuit such as the pixel generation circuit
output wire [9:0] pixel_x, pixel_y
// piexl_x and pixel_y output the counter of hsync and vsync
);
// constant declaration
// VGA 640-by-480 sync parameters
localparam HD = 640; // horizontal display area
localparam HF = 48 ; // h. front (left) border
localparam HB = 16 ; // h. back (right) border
localparam HR = 96 ; // h. retrace
localparam VD = 480; // vertical display area
localparam VF = 27; // v. front (top) border
localparam VB = 16; // v. back (bottom) border
localparam VR = 2; // v. retrace
// mod-2 counter
reg mod2_reg;
wire mod2_next;
// sync counters
reg [9:0] h_count_reg, h_count_next;
reg [9:0] v_count_reg, v_count_next;
// output buffer
reg v_sync_reg, h_sync_reg;
wire v_sync_next, h_sync_next;
// status signal
wire h_end, v_end, pixel_tick;
// First and foremost, let us make another clock.
// The clock information and any other information that can not be found in this document will be found in the pdf file
// converted from a md file.
// Or the information can be found in my Github pages: named ZJUPWWU
// mod-2 circuit to generate 25 MHz enable tick
assign mod2_next = ~mod2_reg;
assign pixel_tick = mod2_reg;
// clock finished
// state switch
always @(posedge clk, posedge reset)
if (reset)
begin
mod2_reg <= 1'b0;
v_count_reg <= 0;
h_count_reg <= 0;
v_sync_reg <= 1'b0;
h_sync_reg <= 1'b0;
end
else
// next is inputted to the state machine
begin
mod2_reg <= mod2_next;
v_count_reg <= v_count_next;
h_count_reg <= h_count_next;
v_sync_reg <= v_sync_next;
h_sync_reg <= h_sync_next;
end
// status signals
// end of horizontal counter (799)
// end of vertical counter (524)
assign h_end = (h_count_reg==(HD+HF+HB+HR-1));
assign v_end = (v_count_reg==(VD+VF+VB+VR-1));
// next-state logic of mod-800 horizontal sync counter
always @ (*)
if (pixel_tick) // 25 MHz pulse
if (h_end)
h_count_next = 0;
else
h_count_next = h_count_reg + 1;
else
h_count_next = h_count_reg;
// next-state logic of mod-525 vertical sync counter
always @ (*)
if (pixel_tick & h_end)
if (v_end)
v_count_next = 0;
else
v_count_next = v_count_reg + 1;
else
v_count_next = v_count_reg;
// horizontal and vertical sync, buffered to avoid glitch
// h_sync_next asserted between 656 and 751
assign h_sync_next = (h_count_reg>=(HD+HB) &&
h_count_reg<=(HD+HB+HR-1));
// vh_sync_next asserted between 490 and 491
assign v_sync_next = (v_count_reg>=(VD+VB) &&
v_count_reg<=(VD+VB+VR-1));
// video on/off
assign video_on = (h_count_reg<HD) && (v_count_reg<VD);
// output
assign hsync = h_sync_reg;
assign vsync = v_sync_reg;
assign pixel_x = h_count_reg;
assign pixel_y = v_count_reg;
assign p_tick = pixel_tick;
endmodule
|
module sky130_fd_sc_ms__nor4b_2 (
Y ,
A ,
B ,
C ,
D_N ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input B ;
input C ;
input D_N ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ms__nor4b base (
.Y(Y),
.A(A),
.B(B),
.C(C),
.D_N(D_N),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
|
module sky130_fd_sc_ms__nor4b_2 (
Y ,
A ,
B ,
C ,
D_N
);
output Y ;
input A ;
input B ;
input C ;
input D_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__nor4b base (
.Y(Y),
.A(A),
.B(B),
.C(C),
.D_N(D_N)
);
endmodule
|
module sky130_fd_io__top_power_lvc_wpad (
P_PAD ,
AMUXBUS_A,
AMUXBUS_B
);
inout P_PAD ;
inout AMUXBUS_A;
inout AMUXBUS_B;
// Voltage supply signals
supply0 SRC_BDY_LVC1;
supply0 SRC_BDY_LVC2;
supply1 OGC_LVC ;
supply1 DRN_LVC1 ;
supply1 BDY2_B2B ;
supply0 DRN_LVC2 ;
supply1 P_CORE ;
supply1 VDDIO ;
supply1 VDDIO_Q ;
supply1 VDDA ;
supply1 VCCD ;
supply1 VSWITCH ;
supply1 VCCHIB ;
supply0 VSSA ;
supply0 VSSD ;
supply0 VSSIO_Q ;
supply0 VSSIO ;
endmodule
|
module sky130_fd_sc_ms__maj3 (
X,
A,
B,
C
);
// Module ports
output X;
input A;
input B;
input C;
// Local signals
wire or0_out ;
wire and0_out ;
wire and1_out ;
wire or1_out_X;
// Name Output Other arguments
or or0 (or0_out , B, A );
and and0 (and0_out , or0_out, C );
and and1 (and1_out , A, B );
or or1 (or1_out_X, and1_out, and0_out);
buf buf0 (X , or1_out_X );
endmodule
|
module sky130_fd_sc_hd__lpflow_inputisolatch (
//# {{data|Data Signals}}
input D ,
output Q ,
//# {{power|Power}}
input SLEEP_B,
input VPB ,
input VPWR ,
input VGND ,
input VNB
);
endmodule
|
module HaarFilter #(
parameter STAGES = 4, ///< Number of stages
parameter INTERNAL_WIDTH = 18, ///< Internal bit width used for calculations
parameter IN_WIDTH = 16, ///< Width of input signal
parameter OUT_WIDTH = 16 ///< Width of output signals from filter bank
)
(
input clk, ///< System clock
input rst, ///< Reset, synchronous and active high
input en, ///< Enable (once per new sample)
input signed [IN_WIDTH-1:0] dataIn, ///< Input samples
output reg [STAGES:0] outStrobes, ///< Strobes for each output
output reg [OUT_WIDTH*(STAGES+1)-1:0] dataOut ///< Outputs from analysis filter
);
///////////////////////////////////////////////////////////////////////////
// Parameter Declarations
///////////////////////////////////////////////////////////////////////////
// Verify Parameters are correct
initial begin
if (STAGES < 2 || STAGES > 8) begin
$display("Attribute STAGES on HaarFilter instance %m is set to %d. Valid range is 2 to 8", STAGES);
#1 $finish;
end
if (INTERNAL_WIDTH < 2) begin
$display("Attribute INTERNAL_WIDTH on HaarFilter instance %m is set to %d. Must be at least 2.", INTERNAL_WIDTH);
#1 $finish;
end
if (IN_WIDTH < 2) begin
$display("Attribute IN_WIDTH on HaarFilter instance %m is set to %d. Must be at least 2.", IN_WIDTH);
#1 $finish;
end
if (OUT_WIDTH < 2) begin
$display("Attribute OUT_WIDTH on HaarFilter instance %m is set to %d. Must be at least 2.", OUT_WIDTH);
#1 $finish;
end
end
///////////////////////////////////////////////////////////////////////////
// Signal Declarations
///////////////////////////////////////////////////////////////////////////
reg signed [INTERNAL_WIDTH-1:0] lowPass [STAGES-1:0];
reg signed [INTERNAL_WIDTH-1:0] prevArray [STAGES-1:0];
reg signed [INTERNAL_WIDTH-1:0] highPass [STAGES-1:0];
reg [7:0] counter;
integer outArray;
integer i;
///////////////////////////////////////////////////////////////////////////
// Calculation Engine
///////////////////////////////////////////////////////////////////////////
wire signed [INTERNAL_WIDTH:0] calcOut;
wire signed [INTERNAL_WIDTH-1:0] in0;
wire signed [INTERNAL_WIDTH-1:0] in1;
reg signed [IN_WIDTH-1:0] dataInD1;
reg [3:0] index;
reg [3:0] index2;
reg enD1;
wire step0;
wire step1;
always @(counter) begin
if (counter[0] == 1'b0) index = 'd0;
else if (counter[1:0] == 2'b01) index = 'd1;
else if (counter[2:0] == 3'b011) index = 'd2;
else if (counter[3:0] == 4'b0111) index = 'd3;
else if (counter[4:0] == 5'b01111) index = 'd4;
else if (counter[5:0] == 6'b011111) index = 'd5;
else if (counter[6:0] == 7'b0111111) index = 'd6;
else if (counter[7:0] == 8'b01111111) index = 'd7;
else index = 'd8; // Used to avoid updating values
if (counter[0] == 1'b0) index2 = 'd8;
else if (counter[1:0] == 2'b01) index2 = 'd0;
else if (counter[2:0] == 3'b011) index2 = 'd1;
else if (counter[3:0] == 4'b0111) index2 = 'd2;
else if (counter[4:0] == 5'b01111) index2 = 'd3;
else if (counter[5:0] == 6'b011111) index2 = 'd4;
else if (counter[6:0] == 7'b0111111) index2 = 'd5;
else if (counter[7:0] == 8'b01111111) index2 = 'd6;
else index2 = 'd7; // Used to avoid updating values
end
if (IN_WIDTH > INTERNAL_WIDTH) begin
assign in0 = counter[0] ? prevArray[index2] : (dataInD1 >>> (IN_WIDTH-INTERNAL_WIDTH));
assign in1 = counter[0] ? lowPass[index2] : (dataIn >>> (IN_WIDTH-INTERNAL_WIDTH));
end
else begin
assign in0 = counter[0] ? prevArray[index2] : (dataInD1 <<< (INTERNAL_WIDTH-IN_WIDTH));
assign in1 = counter[0] ? lowPass[index2] : (dataIn <<< (INTERNAL_WIDTH-IN_WIDTH));
end
assign step0 = en && !enD1;
assign step1 = !en && enD1;
assign calcOut = (step1) ? (in1 - in0) : (in1 + in0);
always @(posedge clk) begin
if (rst) begin
counter <= 'd0;
enD1 <= 'd0;
outStrobes <= 'd0;
dataInD1 <= 'd0;
for (i=0; i<STAGES; i=i+1) begin
lowPass[i] <= 'd0;
highPass[i] <= 'd0;
prevArray[i] <= 'd0;
end
end
else begin
enD1 <= en;
if (step1) begin
counter <= counter + 2'd1;
end
if (step1) dataInD1 <= dataIn;
for (i=0; i<STAGES; i=i+1) begin
// High-pass outputs
if (index == i && step1) begin
highPass[i] <= calcOut[INTERNAL_WIDTH:1];
outStrobes[STAGES-i] <= 1'b1;
end
else begin
outStrobes[STAGES-i] <= 1'b0;
end
// Low-pass outputs
if (index == i && step0) begin
lowPass[i] <= calcOut[INTERNAL_WIDTH:1];
prevArray[i] <= lowPass[i];
end
end
// Final low-pass output strobe
if (index == STAGES-1 && step0) begin
outStrobes[0] <= 1'b1;
end
else begin
outStrobes[0] <= 1'b0;
end
end
end
///////////////////////////////////////////////////////////////////////////
// Output Mapping
///////////////////////////////////////////////////////////////////////////
// Map filter outputs onto output array
if (INTERNAL_WIDTH > OUT_WIDTH) begin
always @(*) begin
dataOut[0+:OUT_WIDTH] = lowPass[STAGES-1] >>> (INTERNAL_WIDTH-OUT_WIDTH);
for (outArray=0; outArray<STAGES; outArray = outArray+1) begin
dataOut[(OUT_WIDTH*(outArray+1))+:OUT_WIDTH] = highPass[STAGES-1-outArray] >>> (INTERNAL_WIDTH-OUT_WIDTH);
end
end
end
else begin
always @(*) begin
dataOut[0+:OUT_WIDTH] = lowPass[STAGES-1] <<< (OUT_WIDTH-INTERNAL_WIDTH);
for (outArray=0; outArray<STAGES; outArray = outArray+1) begin
dataOut[(OUT_WIDTH*(outArray+1))+:OUT_WIDTH] = highPass[STAGES-1-outArray] <<< (OUT_WIDTH-INTERNAL_WIDTH);
end
end
end
endmodule
|
module BRAM2(CLKA,
ENA,
WEA,
ADDRA,
DIA,
DOA,
CLKB,
ENB,
WEB,
ADDRB,
DIB,
DOB
);
parameter PIPELINED = 0;
parameter ADDR_WIDTH = 1;
parameter DATA_WIDTH = 1;
parameter MEMSIZE = 1;
input CLKA;
input ENA;
input WEA;
input [ADDR_WIDTH-1:0] ADDRA;
input [DATA_WIDTH-1:0] DIA;
output [DATA_WIDTH-1:0] DOA;
input CLKB;
input ENB;
input WEB;
input [ADDR_WIDTH-1:0] ADDRB;
input [DATA_WIDTH-1:0] DIB;
output [DATA_WIDTH-1:0] DOB;
reg [DATA_WIDTH-1:0] RAM[0:MEMSIZE-1] /* synthesis syn_ramstyle="no_rw_check" */ ;
reg [DATA_WIDTH-1:0] DOA_R;
reg [DATA_WIDTH-1:0] DOB_R;
reg [DATA_WIDTH-1:0] DOA_R2;
reg [DATA_WIDTH-1:0] DOB_R2;
`ifdef BSV_NO_INITIAL_BLOCKS
`else
// synopsys translate_off
integer i;
initial
begin : init_block
for (i = 0; i < MEMSIZE; i = i + 1) begin
RAM[i] = { ((DATA_WIDTH+1)/2) { 2'b10 } };
end
DOA_R = { ((DATA_WIDTH+1)/2) { 2'b10 } };
DOB_R = { ((DATA_WIDTH+1)/2) { 2'b10 } };
DOA_R2 = { ((DATA_WIDTH+1)/2) { 2'b10 } };
DOB_R2 = { ((DATA_WIDTH+1)/2) { 2'b10 } };
end
// synopsys translate_on
`endif // !`ifdef BSV_NO_INITIAL_BLOCKS
always @(posedge CLKA) begin
if (ENA) begin
if (WEA) begin
RAM[ADDRA] <= `BSV_ASSIGNMENT_DELAY DIA;
DOA_R <= `BSV_ASSIGNMENT_DELAY DIA;
end
else begin
DOA_R <= `BSV_ASSIGNMENT_DELAY RAM[ADDRA];
end
end
DOA_R2 <= `BSV_ASSIGNMENT_DELAY DOA_R;
end
always @(posedge CLKB) begin
if (ENB) begin
if (WEB) begin
RAM[ADDRB] <= `BSV_ASSIGNMENT_DELAY DIB;
DOB_R <= `BSV_ASSIGNMENT_DELAY DIB;
end
else begin
DOB_R <= `BSV_ASSIGNMENT_DELAY RAM[ADDRB];
end
end
DOB_R2 <= `BSV_ASSIGNMENT_DELAY DOB_R;
end
// Output drivers
assign DOA = (PIPELINED) ? DOA_R2 : DOA_R;
assign DOB = (PIPELINED) ? DOB_R2 : DOB_R;
endmodule
|
module sky130_fd_sc_ms__o22ai (
Y ,
A1,
A2,
B1,
B2
);
output Y ;
input A1;
input A2;
input B1;
input B2;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
|
module ddr3_s4_uniphy_example_sim (
input wire pll_ref_clk, // pll_ref_clk.clk
input wire global_reset_n, // global_reset.reset_n
input wire soft_reset_n, // soft_reset.reset_n
input wire oct_rdn, // oct.rdn
input wire oct_rup, // .rup
output wire local_powerdn_ack, // local_powerdown.local_powerdn_ack
input wire local_powerdn_req // .local_powerdn_req
);
ddr3_s4_uniphy_example_sim_ddr3_s4_uniphy_example_sim #(
.ENABLE_VCDPLUS (0)
) ddr3_s4_uniphy_example_sim_inst (
.pll_ref_clk (pll_ref_clk), // pll_ref_clk.clk
.global_reset_n (global_reset_n), // global_reset.reset_n
.soft_reset_n (soft_reset_n), // soft_reset.reset_n
.oct_rdn (oct_rdn), // oct.rdn
.oct_rup (oct_rup), // .rup
.local_powerdn_ack (local_powerdn_ack), // local_powerdown.local_powerdn_ack
.local_powerdn_req (local_powerdn_req) // .local_powerdn_req
);
endmodule
|
module BRAM
(DOBDO,
ETH_CLK_OBUF,
ADDRBWRADDR,
pwropt);
output [3:0]DOBDO;
input ETH_CLK_OBUF;
input [12:0]ADDRBWRADDR;
input pwropt;
wire [12:0]ADDRBWRADDR;
wire [3:0]DOBDO;
wire ETH_CLK_OBUF;
wire pwropt;
wire NLW_MEMORY_reg_0_CASCADEOUTA_UNCONNECTED;
wire NLW_MEMORY_reg_0_CASCADEOUTB_UNCONNECTED;
wire NLW_MEMORY_reg_0_DBITERR_UNCONNECTED;
wire NLW_MEMORY_reg_0_INJECTDBITERR_UNCONNECTED;
wire NLW_MEMORY_reg_0_INJECTSBITERR_UNCONNECTED;
wire NLW_MEMORY_reg_0_REGCEAREGCE_UNCONNECTED;
wire NLW_MEMORY_reg_0_REGCEB_UNCONNECTED;
wire NLW_MEMORY_reg_0_SBITERR_UNCONNECTED;
wire [31:0]NLW_MEMORY_reg_0_DOADO_UNCONNECTED;
wire [31:4]NLW_MEMORY_reg_0_DOBDO_UNCONNECTED;
wire [3:0]NLW_MEMORY_reg_0_DOPADOP_UNCONNECTED;
wire [3:0]NLW_MEMORY_reg_0_DOPBDOP_UNCONNECTED;
wire [7:0]NLW_MEMORY_reg_0_ECCPARITY_UNCONNECTED;
wire [8:0]NLW_MEMORY_reg_0_RDADDRECC_UNCONNECTED;
(* IS_CLOCK_GATED *)
(* METHODOLOGY_DRC_VIOS = "{SYNTH-6 {cell *THIS*}}" *)
(* POWER_OPTED_CE = "ENBWREN=NEW" *)
(* RTL_RAM_BITS = "60000" *)
(* RTL_RAM_NAME = "MEMORY" *)
(* bram_addr_begin = "0" *)
(* bram_addr_end = "8191" *)
(* bram_slice_begin = "0" *)
(* bram_slice_end = "3" *)
RAMB36E1 #(
.DOA_REG(0),
.DOB_REG(0),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.IS_ENBWREN_INVERTED(1'b1),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
.READ_WIDTH_A(4),
.READ_WIDTH_B(4),
.RSTREG_PRIORITY_A("RSTREG"),
.RSTREG_PRIORITY_B("RSTREG"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("NO_CHANGE"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(4),
.WRITE_WIDTH_B(4))
MEMORY_reg_0
(.ADDRARDADDR({1'b1,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b1,1'b1}),
.ADDRBWRADDR({1'b1,ADDRBWRADDR,1'b1,1'b1}),
.CASCADEINA(1'b1),
.CASCADEINB(1'b1),
.CASCADEOUTA(NLW_MEMORY_reg_0_CASCADEOUTA_UNCONNECTED),
.CASCADEOUTB(NLW_MEMORY_reg_0_CASCADEOUTB_UNCONNECTED),
.CLKARDCLK(ETH_CLK_OBUF),
.CLKBWRCLK(ETH_CLK_OBUF),
.DBITERR(NLW_MEMORY_reg_0_DBITERR_UNCONNECTED),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b1,1'b1,1'b1,1'b1}),
.DIPADIP({1'b0,1'b0,1'b0,1'b0}),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO(NLW_MEMORY_reg_0_DOADO_UNCONNECTED[31:0]),
.DOBDO({NLW_MEMORY_reg_0_DOBDO_UNCONNECTED[31:4],DOBDO}),
.DOPADOP(NLW_MEMORY_reg_0_DOPADOP_UNCONNECTED[3:0]),
.DOPBDOP(NLW_MEMORY_reg_0_DOPBDOP_UNCONNECTED[3:0]),
.ECCPARITY(NLW_MEMORY_reg_0_ECCPARITY_UNCONNECTED[7:0]),
.ENARDEN(1'b1),
.ENBWREN(pwropt),
.INJECTDBITERR(NLW_MEMORY_reg_0_INJECTDBITERR_UNCONNECTED),
.INJECTSBITERR(NLW_MEMORY_reg_0_INJECTSBITERR_UNCONNECTED),
.RDADDRECC(NLW_MEMORY_reg_0_RDADDRECC_UNCONNECTED[8:0]),
.REGCEAREGCE(NLW_MEMORY_reg_0_REGCEAREGCE_UNCONNECTED),
.REGCEB(NLW_MEMORY_reg_0_REGCEB_UNCONNECTED),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(NLW_MEMORY_reg_0_SBITERR_UNCONNECTED),
.WEA({1'b1,1'b1,1'b1,1'b1}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
endmodule
|
module BSP
(CLK_IN,
RST,
ETH_CLK,
PHY_RESET_N,
RXDV,
RXER,
RXD,
TXD,
TXEN,
JC,
SDA,
SCL,
KD,
KC,
AUDIO,
AUDIO_EN,
VGA_R,
VGA_G,
VGA_B,
HSYNCH,
VSYNCH,
GPIO_LEDS,
GPIO_SWITCHES,
GPIO_BUTTONS,
LED_R_PWM,
LED_G_PWM,
LED_B_PWM,
SEVEN_SEGMENT_CATHODE,
SEVEN_SEGMENT_ANNODE,
RS232_RX,
RS232_TX);
input CLK_IN;
input RST;
output ETH_CLK;
output PHY_RESET_N;
input RXDV;
input RXER;
input [1:0]RXD;
output [1:0]TXD;
output TXEN;
inout [7:0]JC;
inout SDA;
inout SCL;
input KD;
input KC;
output AUDIO;
output AUDIO_EN;
output [3:0]VGA_R;
output [3:0]VGA_G;
output [3:0]VGA_B;
output HSYNCH;
output VSYNCH;
output [15:0]GPIO_LEDS;
input [15:0]GPIO_SWITCHES;
input [4:0]GPIO_BUTTONS;
output LED_R_PWM;
output LED_G_PWM;
output LED_B_PWM;
output [6:0]SEVEN_SEGMENT_CATHODE;
output [7:0]SEVEN_SEGMENT_ANNODE;
input RS232_RX;
output RS232_TX;
wire AUDIO;
wire AUDIO_EN;
wire CLKFB;
wire CLKIN;
(* IBUF_LOW_PWR *) wire CLK_IN;
wire ETH_CLK;
wire ETH_CLK_OBUF;
wire \GPIO_BUTTONS[0] ;
wire \GPIO_BUTTONS[0]_IBUF ;
wire \GPIO_BUTTONS[1] ;
wire \GPIO_BUTTONS[1]_IBUF ;
wire \GPIO_BUTTONS[2] ;
wire \GPIO_BUTTONS[2]_IBUF ;
wire \GPIO_BUTTONS[3] ;
wire \GPIO_BUTTONS[3]_IBUF ;
wire \GPIO_BUTTONS[4] ;
wire \GPIO_BUTTONS[4]_IBUF ;
wire [15:0]GPIO_LEDS;
wire \GPIO_SWITCHES[0] ;
wire \GPIO_SWITCHES[0]_IBUF ;
wire \GPIO_SWITCHES[10] ;
wire \GPIO_SWITCHES[10]_IBUF ;
wire \GPIO_SWITCHES[11] ;
wire \GPIO_SWITCHES[11]_IBUF ;
wire \GPIO_SWITCHES[12] ;
wire \GPIO_SWITCHES[12]_IBUF ;
wire \GPIO_SWITCHES[13] ;
wire \GPIO_SWITCHES[13]_IBUF ;
wire \GPIO_SWITCHES[14] ;
wire \GPIO_SWITCHES[14]_IBUF ;
wire \GPIO_SWITCHES[15] ;
wire \GPIO_SWITCHES[15]_IBUF ;
wire \GPIO_SWITCHES[1] ;
wire \GPIO_SWITCHES[1]_IBUF ;
wire \GPIO_SWITCHES[2] ;
wire \GPIO_SWITCHES[2]_IBUF ;
wire \GPIO_SWITCHES[3] ;
wire \GPIO_SWITCHES[3]_IBUF ;
wire \GPIO_SWITCHES[4] ;
wire \GPIO_SWITCHES[4]_IBUF ;
wire \GPIO_SWITCHES[5] ;
wire \GPIO_SWITCHES[5]_IBUF ;
wire \GPIO_SWITCHES[6] ;
wire \GPIO_SWITCHES[6]_IBUF ;
wire \GPIO_SWITCHES[7] ;
wire \GPIO_SWITCHES[7]_IBUF ;
wire \GPIO_SWITCHES[8] ;
wire \GPIO_SWITCHES[8]_IBUF ;
wire \GPIO_SWITCHES[9] ;
wire \GPIO_SWITCHES[9]_IBUF ;
wire HSYNCH;
wire HSYNCH_OBUF;
wire IN1_ACK;
wire IN1_STB;
wire INTERNAL_RST_reg_n_0;
wire [7:0]JC;
wire [1:1]JC_IBUF;
wire KC;
wire KC_IBUF;
wire KD;
wire KD_IBUF;
wire LED_B_PWM;
wire LED_B_PWM_OBUF;
wire LED_G_PWM;
wire LED_G_PWM_OBUF;
wire LED_R_PWM;
wire LED_R_PWM_OBUF;
wire NOT_LOCKED;
wire NOT_LOCKED_i_1_n_0;
wire [7:0]OUT1;
wire OUT1_ACK;
wire OUT1_STB;
wire PHY_RESET_N;
wire PHY_RESET_N_OBUF;
wire RS232_RX;
wire RS232_RX_IBUF;
wire RS232_TX;
wire RS232_TX_OBUF;
wire RST;
wire RST_IBUF;
wire RXDV;
wire RXDV_IBUF;
wire \RXD[0] ;
wire \RXD[0]_IBUF ;
wire \RXD[1] ;
wire \RXD[1]_IBUF ;
wire RXER;
wire RXER_IBUF;
(* DRIVE = "12" *) (* IBUF_LOW_PWR *) (* SLEW = "SLOW" *) wire SCL;
wire SCL_IBUF;
wire SCL_TRI;
wire SDA;
wire SDA_IBUF;
wire SDA_TRI;
wire [7:0]SEVEN_SEGMENT_ANNODE;
wire [6:0]SEVEN_SEGMENT_CATHODE;
wire [1:0]TXD;
wire [1:0]TXD_OBUF;
wire TXEN;
wire TXEN_OBUF;
wire USER_DESIGN_INST_1_n_2;
wire USER_DESIGN_INST_1_n_3;
wire USER_DESIGN_INST_1_n_4;
wire USER_DESIGN_INST_1_n_5;
wire USER_DESIGN_INST_1_n_6;
wire USER_DESIGN_INST_1_n_7;
wire USER_DESIGN_INST_1_n_8;
wire USER_DESIGN_INST_1_n_9;
wire [3:0]VGA_B;
wire [0:0]VGA_B_OBUF;
wire [3:0]VGA_G;
wire [3:0]VGA_R;
wire VSYNCH;
wire VSYNCH_OBUF;
wire clk0;
wire clkdv;
wire locked_internal;
wire NLW_dcm_sp_inst_CLKFBOUTB_UNCONNECTED;
wire NLW_dcm_sp_inst_CLKFBSTOPPED_UNCONNECTED;
wire NLW_dcm_sp_inst_CLKINSTOPPED_UNCONNECTED;
wire NLW_dcm_sp_inst_CLKOUT0_UNCONNECTED;
wire NLW_dcm_sp_inst_CLKOUT0B_UNCONNECTED;
wire NLW_dcm_sp_inst_CLKOUT1_UNCONNECTED;
wire NLW_dcm_sp_inst_CLKOUT1B_UNCONNECTED;
wire NLW_dcm_sp_inst_CLKOUT2_UNCONNECTED;
wire NLW_dcm_sp_inst_CLKOUT2B_UNCONNECTED;
wire NLW_dcm_sp_inst_CLKOUT3_UNCONNECTED;
wire NLW_dcm_sp_inst_CLKOUT3B_UNCONNECTED;
wire NLW_dcm_sp_inst_CLKOUT5_UNCONNECTED;
wire NLW_dcm_sp_inst_CLKOUT6_UNCONNECTED;
wire NLW_dcm_sp_inst_DRDY_UNCONNECTED;
wire NLW_dcm_sp_inst_PSDONE_UNCONNECTED;
wire [15:0]NLW_dcm_sp_inst_DO_UNCONNECTED;
wire NLW_ethernet_inst_1_RXDV_IBUF_UNCONNECTED;
wire NLW_ethernet_inst_1_RXER_IBUF_UNCONNECTED;
wire [1:0]NLW_ethernet_inst_1_D_UNCONNECTED;
PULLUP pullup_KC
(.O(KC));
PULLUP pullup_KD
(.O(KD));
initial begin
$sdf_annotate("cpu_impl_netlist.sdf",,,,"tool_control");
end
assign \GPIO_BUTTONS[0] = GPIO_BUTTONS[0];
assign \GPIO_BUTTONS[1] = GPIO_BUTTONS[1];
assign \GPIO_BUTTONS[2] = GPIO_BUTTONS[2];
assign \GPIO_BUTTONS[3] = GPIO_BUTTONS[3];
assign \GPIO_BUTTONS[4] = GPIO_BUTTONS[4];
assign \GPIO_SWITCHES[0] = GPIO_SWITCHES[0];
assign \GPIO_SWITCHES[10] = GPIO_SWITCHES[10];
assign \GPIO_SWITCHES[11] = GPIO_SWITCHES[11];
assign \GPIO_SWITCHES[12] = GPIO_SWITCHES[12];
assign \GPIO_SWITCHES[13] = GPIO_SWITCHES[13];
assign \GPIO_SWITCHES[14] = GPIO_SWITCHES[14];
assign \GPIO_SWITCHES[15] = GPIO_SWITCHES[15];
assign \GPIO_SWITCHES[1] = GPIO_SWITCHES[1];
assign \GPIO_SWITCHES[2] = GPIO_SWITCHES[2];
assign \GPIO_SWITCHES[3] = GPIO_SWITCHES[3];
assign \GPIO_SWITCHES[4] = GPIO_SWITCHES[4];
assign \GPIO_SWITCHES[5] = GPIO_SWITCHES[5];
assign \GPIO_SWITCHES[6] = GPIO_SWITCHES[6];
assign \GPIO_SWITCHES[7] = GPIO_SWITCHES[7];
assign \GPIO_SWITCHES[8] = GPIO_SWITCHES[8];
assign \GPIO_SWITCHES[9] = GPIO_SWITCHES[9];
assign \RXD[0] = RXD[0];
assign \RXD[1] = RXD[1];
OBUF AUDIO_EN_OBUF_inst
(.I(1'b1),
.O(AUDIO_EN));
OBUF AUDIO_OBUF_inst
(.I(1'b0),
.O(AUDIO));
(* box_type = "PRIMITIVE" *)
BUFG BUFG_INST1
(.I(clkdv),
.O(ETH_CLK_OBUF));
(* box_type = "PRIMITIVE" *)
BUFG BUFG_INST2
(.I(clk0),
.O(CLKFB));
CHARSVGA CHARSVGA_INST_1
(.ETH_CLK_OBUF(ETH_CLK_OBUF),
.HSYNCH(HSYNCH_OBUF),
.INTERNAL_RST_reg(INTERNAL_RST_reg_n_0),
.VGA_B_OBUF(VGA_B_OBUF),
.VSYNCH(VSYNCH_OBUF));
OBUF ETH_CLK_OBUF_inst
(.I(ETH_CLK_OBUF),
.O(ETH_CLK));
(* OPT_INSERTED *)
IBUF \GPIO_BUTTONS[0]_IBUF_inst
(.I(\GPIO_BUTTONS[0] ),
.O(\GPIO_BUTTONS[0]_IBUF ));
(* OPT_INSERTED *)
IBUF \GPIO_BUTTONS[1]_IBUF_inst
(.I(\GPIO_BUTTONS[1] ),
.O(\GPIO_BUTTONS[1]_IBUF ));
(* OPT_INSERTED *)
IBUF \GPIO_BUTTONS[2]_IBUF_inst
(.I(\GPIO_BUTTONS[2] ),
.O(\GPIO_BUTTONS[2]_IBUF ));
(* OPT_INSERTED *)
IBUF \GPIO_BUTTONS[3]_IBUF_inst
(.I(\GPIO_BUTTONS[3] ),
.O(\GPIO_BUTTONS[3]_IBUF ));
(* OPT_INSERTED *)
IBUF \GPIO_BUTTONS[4]_IBUF_inst
(.I(\GPIO_BUTTONS[4] ),
.O(\GPIO_BUTTONS[4]_IBUF ));
OBUF \GPIO_LEDS_OBUF[0]_inst
(.I(1'b0),
.O(GPIO_LEDS[0]));
OBUF \GPIO_LEDS_OBUF[10]_inst
(.I(1'b0),
.O(GPIO_LEDS[10]));
OBUF \GPIO_LEDS_OBUF[11]_inst
(.I(1'b0),
.O(GPIO_LEDS[11]));
OBUF \GPIO_LEDS_OBUF[12]_inst
(.I(1'b0),
.O(GPIO_LEDS[12]));
OBUF \GPIO_LEDS_OBUF[13]_inst
(.I(1'b0),
.O(GPIO_LEDS[13]));
OBUF \GPIO_LEDS_OBUF[14]_inst
(.I(1'b0),
.O(GPIO_LEDS[14]));
OBUF \GPIO_LEDS_OBUF[15]_inst
(.I(1'b0),
.O(GPIO_LEDS[15]));
OBUF \GPIO_LEDS_OBUF[1]_inst
(.I(1'b0),
.O(GPIO_LEDS[1]));
OBUF \GPIO_LEDS_OBUF[2]_inst
(.I(1'b0),
.O(GPIO_LEDS[2]));
OBUF \GPIO_LEDS_OBUF[3]_inst
(.I(1'b0),
.O(GPIO_LEDS[3]));
OBUF \GPIO_LEDS_OBUF[4]_inst
(.I(1'b0),
.O(GPIO_LEDS[4]));
OBUF \GPIO_LEDS_OBUF[5]_inst
(.I(1'b0),
.O(GPIO_LEDS[5]));
OBUF \GPIO_LEDS_OBUF[6]_inst
(.I(1'b0),
.O(GPIO_LEDS[6]));
OBUF \GPIO_LEDS_OBUF[7]_inst
(.I(1'b0),
.O(GPIO_LEDS[7]));
OBUF \GPIO_LEDS_OBUF[8]_inst
(.I(1'b0),
.O(GPIO_LEDS[8]));
OBUF \GPIO_LEDS_OBUF[9]_inst
(.I(1'b0),
.O(GPIO_LEDS[9]));
(* OPT_INSERTED *)
IBUF \GPIO_SWITCHES[0]_IBUF_inst
(.I(\GPIO_SWITCHES[0] ),
.O(\GPIO_SWITCHES[0]_IBUF ));
(* OPT_INSERTED *)
IBUF \GPIO_SWITCHES[10]_IBUF_inst
(.I(\GPIO_SWITCHES[10] ),
.O(\GPIO_SWITCHES[10]_IBUF ));
(* OPT_INSERTED *)
IBUF \GPIO_SWITCHES[11]_IBUF_inst
(.I(\GPIO_SWITCHES[11] ),
.O(\GPIO_SWITCHES[11]_IBUF ));
(* OPT_INSERTED *)
IBUF \GPIO_SWITCHES[12]_IBUF_inst
(.I(\GPIO_SWITCHES[12] ),
.O(\GPIO_SWITCHES[12]_IBUF ));
(* OPT_INSERTED *)
IBUF \GPIO_SWITCHES[13]_IBUF_inst
(.I(\GPIO_SWITCHES[13] ),
.O(\GPIO_SWITCHES[13]_IBUF ));
(* OPT_INSERTED *)
IBUF \GPIO_SWITCHES[14]_IBUF_inst
(.I(\GPIO_SWITCHES[14] ),
.O(\GPIO_SWITCHES[14]_IBUF ));
(* OPT_INSERTED *)
IBUF \GPIO_SWITCHES[15]_IBUF_inst
(.I(\GPIO_SWITCHES[15] ),
.O(\GPIO_SWITCHES[15]_IBUF ));
(* OPT_INSERTED *)
IBUF \GPIO_SWITCHES[1]_IBUF_inst
(.I(\GPIO_SWITCHES[1] ),
.O(\GPIO_SWITCHES[1]_IBUF ));
(* OPT_INSERTED *)
IBUF \GPIO_SWITCHES[2]_IBUF_inst
(.I(\GPIO_SWITCHES[2] ),
.O(\GPIO_SWITCHES[2]_IBUF ));
(* OPT_INSERTED *)
IBUF \GPIO_SWITCHES[3]_IBUF_inst
(.I(\GPIO_SWITCHES[3] ),
.O(\GPIO_SWITCHES[3]_IBUF ));
(* OPT_INSERTED *)
IBUF \GPIO_SWITCHES[4]_IBUF_inst
(.I(\GPIO_SWITCHES[4] ),
.O(\GPIO_SWITCHES[4]_IBUF ));
(* OPT_INSERTED *)
IBUF \GPIO_SWITCHES[5]_IBUF_inst
(.I(\GPIO_SWITCHES[5] ),
.O(\GPIO_SWITCHES[5]_IBUF ));
(* OPT_INSERTED *)
IBUF \GPIO_SWITCHES[6]_IBUF_inst
(.I(\GPIO_SWITCHES[6] ),
.O(\GPIO_SWITCHES[6]_IBUF ));
(* OPT_INSERTED *)
IBUF \GPIO_SWITCHES[7]_IBUF_inst
(.I(\GPIO_SWITCHES[7] ),
.O(\GPIO_SWITCHES[7]_IBUF ));
(* OPT_INSERTED *)
IBUF \GPIO_SWITCHES[8]_IBUF_inst
(.I(\GPIO_SWITCHES[8] ),
.O(\GPIO_SWITCHES[8]_IBUF ));
(* OPT_INSERTED *)
IBUF \GPIO_SWITCHES[9]_IBUF_inst
(.I(\GPIO_SWITCHES[9] ),
.O(\GPIO_SWITCHES[9]_IBUF ));
OBUF HSYNCH_OBUF_inst
(.I(HSYNCH_OBUF),
.O(HSYNCH));
I2C I2C_INST_1
(.ETH_CLK_OBUF(ETH_CLK_OBUF),
.INTERNAL_RST_reg(INTERNAL_RST_reg_n_0),
.SCL_IBUF(SCL_IBUF),
.SCL_TRI(SCL_TRI),
.SDA_IBUF(SDA_IBUF),
.SDA_TRI(SDA_TRI));
FDRE INTERNAL_RST_reg
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(NOT_LOCKED),
.Q(INTERNAL_RST_reg_n_0),
.R(1'b0));
OBUF \JC_OBUF[0]_inst
(.I(1'b1),
.O(JC[0]));
OBUF \JC_OBUF[1]_inst
(.I(JC_IBUF),
.O(JC[1]));
(* OPT_INSERTED *)
IBUF KC_IBUF_inst
(.I(KC),
.O(KC_IBUF));
(* OPT_INSERTED *)
IBUF KD_IBUF_inst
(.I(KD),
.O(KD_IBUF));
OBUF LED_B_PWM_OBUF_inst
(.I(LED_B_PWM_OBUF),
.O(LED_B_PWM));
OBUF LED_G_PWM_OBUF_inst
(.I(LED_G_PWM_OBUF),
.O(LED_G_PWM));
OBUF LED_R_PWM_OBUF_inst
(.I(LED_R_PWM_OBUF),
.O(LED_R_PWM));
LUT1 #(
.INIT(2'h1))
NOT_LOCKED_i_1
(.I0(locked_internal),
.O(NOT_LOCKED_i_1_n_0));
FDRE NOT_LOCKED_reg
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(NOT_LOCKED_i_1_n_0),
.Q(NOT_LOCKED),
.R(1'b0));
OBUF PHY_RESET_N_OBUF_inst
(.I(PHY_RESET_N_OBUF),
.O(PHY_RESET_N));
LUT1 #(
.INIT(2'h1))
PHY_RESET_N_OBUF_inst_i_1
(.I0(INTERNAL_RST_reg_n_0),
.O(PHY_RESET_N_OBUF));
PWM PWM_INST_1
(.ETH_CLK_OBUF(ETH_CLK_OBUF),
.LED_R_PWM_OBUF(LED_R_PWM_OBUF));
PWM_0 PWM_INST_2
(.ETH_CLK_OBUF(ETH_CLK_OBUF),
.LED_G_PWM_OBUF(LED_G_PWM_OBUF));
PWM_1 PWM_INST_3
(.ETH_CLK_OBUF(ETH_CLK_OBUF),
.LED_B_PWM_OBUF(LED_B_PWM_OBUF));
IBUF RS232_RX_IBUF_inst
(.I(RS232_RX),
.O(RS232_RX_IBUF));
OBUF RS232_TX_OBUF_inst
(.I(RS232_TX_OBUF),
.O(RS232_TX));
IBUF RST_IBUF_inst
(.I(RST),
.O(RST_IBUF));
(* OPT_INSERTED *)
IBUF RXDV_IBUF_inst
(.I(RXDV),
.O(RXDV_IBUF));
(* OPT_INSERTED *)
IBUF \RXD[0]_IBUF_inst
(.I(\RXD[0] ),
.O(\RXD[0]_IBUF ));
(* OPT_INSERTED *)
IBUF \RXD[1]_IBUF_inst
(.I(\RXD[1] ),
.O(\RXD[1]_IBUF ));
(* OPT_INSERTED *)
IBUF RXER_IBUF_inst
(.I(RXER),
.O(RXER_IBUF));
IOBUF_HD3 SCL_IOBUF_inst
(.I(1'b0),
.IO(SCL),
.O(SCL_IBUF),
.T(SCL_TRI));
IOBUF_UNIQ_BASE_ SDA_IOBUF_inst
(.I(1'b0),
.IO(SDA),
.O(SDA_IBUF),
.T(SDA_TRI));
SERIAL_INPUT SERIAL_INPUT_INST_1
(.ETH_CLK_OBUF(ETH_CLK_OBUF),
.INTERNAL_RST_reg(INTERNAL_RST_reg_n_0),
.OUT1(OUT1),
.OUT1_ACK(OUT1_ACK),
.OUT1_STB(OUT1_STB),
.RX(RS232_RX_IBUF));
serial_output SERIAL_OUTPUT_INST_1
(.ETH_CLK_OBUF(ETH_CLK_OBUF),
.IN1_ACK(IN1_ACK),
.IN1_STB(IN1_STB),
.INTERNAL_RST_reg(INTERNAL_RST_reg_n_0),
.Q({USER_DESIGN_INST_1_n_2,USER_DESIGN_INST_1_n_3,USER_DESIGN_INST_1_n_4,USER_DESIGN_INST_1_n_5,USER_DESIGN_INST_1_n_6,USER_DESIGN_INST_1_n_7,USER_DESIGN_INST_1_n_8,USER_DESIGN_INST_1_n_9}),
.RS232_TX_OBUF(RS232_TX_OBUF));
OBUF \SEVEN_SEGMENT_ANNODE_OBUF[0]_inst
(.I(1'b1),
.O(SEVEN_SEGMENT_ANNODE[0]));
OBUF \SEVEN_SEGMENT_ANNODE_OBUF[1]_inst
(.I(1'b1),
.O(SEVEN_SEGMENT_ANNODE[1]));
OBUF \SEVEN_SEGMENT_ANNODE_OBUF[2]_inst
(.I(1'b1),
.O(SEVEN_SEGMENT_ANNODE[2]));
OBUF \SEVEN_SEGMENT_ANNODE_OBUF[3]_inst
(.I(1'b1),
.O(SEVEN_SEGMENT_ANNODE[3]));
OBUF \SEVEN_SEGMENT_ANNODE_OBUF[4]_inst
(.I(1'b1),
.O(SEVEN_SEGMENT_ANNODE[4]));
OBUF \SEVEN_SEGMENT_ANNODE_OBUF[5]_inst
(.I(1'b1),
.O(SEVEN_SEGMENT_ANNODE[5]));
OBUF \SEVEN_SEGMENT_ANNODE_OBUF[6]_inst
(.I(1'b1),
.O(SEVEN_SEGMENT_ANNODE[6]));
OBUF \SEVEN_SEGMENT_ANNODE_OBUF[7]_inst
(.I(1'b1),
.O(SEVEN_SEGMENT_ANNODE[7]));
OBUF \SEVEN_SEGMENT_CATHODE_OBUF[0]_inst
(.I(1'b1),
.O(SEVEN_SEGMENT_CATHODE[0]));
OBUF \SEVEN_SEGMENT_CATHODE_OBUF[1]_inst
(.I(1'b1),
.O(SEVEN_SEGMENT_CATHODE[1]));
OBUF \SEVEN_SEGMENT_CATHODE_OBUF[2]_inst
(.I(1'b1),
.O(SEVEN_SEGMENT_CATHODE[2]));
OBUF \SEVEN_SEGMENT_CATHODE_OBUF[3]_inst
(.I(1'b1),
.O(SEVEN_SEGMENT_CATHODE[3]));
OBUF \SEVEN_SEGMENT_CATHODE_OBUF[4]_inst
(.I(1'b1),
.O(SEVEN_SEGMENT_CATHODE[4]));
OBUF \SEVEN_SEGMENT_CATHODE_OBUF[5]_inst
(.I(1'b1),
.O(SEVEN_SEGMENT_CATHODE[5]));
OBUF \SEVEN_SEGMENT_CATHODE_OBUF[6]_inst
(.I(1'b1),
.O(SEVEN_SEGMENT_CATHODE[6]));
OBUF \TXD_OBUF[0]_inst
(.I(TXD_OBUF[0]),
.O(TXD[0]));
OBUF \TXD_OBUF[1]_inst
(.I(TXD_OBUF[1]),
.O(TXD[1]));
OBUF TXEN_OBUF_inst
(.I(TXEN_OBUF),
.O(TXEN));
user_design USER_DESIGN_INST_1
(.ETH_CLK_OBUF(ETH_CLK_OBUF),
.IN1_ACK(IN1_ACK),
.IN1_STB(IN1_STB),
.INTERNAL_RST_reg(INTERNAL_RST_reg_n_0),
.OUT1(OUT1),
.OUT1_ACK(OUT1_ACK),
.OUT1_STB(OUT1_STB),
.output_rs232_out({USER_DESIGN_INST_1_n_2,USER_DESIGN_INST_1_n_3,USER_DESIGN_INST_1_n_4,USER_DESIGN_INST_1_n_5,USER_DESIGN_INST_1_n_6,USER_DESIGN_INST_1_n_7,USER_DESIGN_INST_1_n_8,USER_DESIGN_INST_1_n_9}));
OBUF \VGA_B_OBUF[0]_inst
(.I(VGA_B_OBUF),
.O(VGA_B[0]));
OBUF \VGA_B_OBUF[1]_inst
(.I(VGA_B_OBUF),
.O(VGA_B[1]));
OBUF \VGA_B_OBUF[2]_inst
(.I(VGA_B_OBUF),
.O(VGA_B[2]));
OBUF \VGA_B_OBUF[3]_inst
(.I(VGA_B_OBUF),
.O(VGA_B[3]));
OBUF \VGA_G_OBUF[0]_inst
(.I(VGA_B_OBUF),
.O(VGA_G[0]));
OBUF \VGA_G_OBUF[1]_inst
(.I(VGA_B_OBUF),
.O(VGA_G[1]));
OBUF \VGA_G_OBUF[2]_inst
(.I(VGA_B_OBUF),
.O(VGA_G[2]));
OBUF \VGA_G_OBUF[3]_inst
(.I(VGA_B_OBUF),
.O(VGA_G[3]));
OBUF \VGA_R_OBUF[0]_inst
(.I(VGA_B_OBUF),
.O(VGA_R[0]));
OBUF \VGA_R_OBUF[1]_inst
(.I(VGA_B_OBUF),
.O(VGA_R[1]));
OBUF \VGA_R_OBUF[2]_inst
(.I(VGA_B_OBUF),
.O(VGA_R[2]));
OBUF \VGA_R_OBUF[3]_inst
(.I(VGA_B_OBUF),
.O(VGA_R[3]));
OBUF VSYNCH_OBUF_inst
(.I(VSYNCH_OBUF),
.O(VSYNCH));
(* CAPACITANCE = "DONT_CARE" *)
(* IBUF_DELAY_VALUE = "0" *)
(* XILINX_LEGACY_PRIM = "IBUFG" *)
(* box_type = "PRIMITIVE" *)
IBUF #(
.IOSTANDARD("DEFAULT"))
clkin1_buf
(.I(CLK_IN),
.O(CLKIN));
(* XILINX_LEGACY_PRIM = "DCM_SP" *)
(* XILINX_TRANSFORM_PINMAP = "STATUS[7]:DO[7] STATUS[6]:DO[6] STATUS[5]:DO[5] STATUS[4]:DO[4] STATUS[3]:DO[3] STATUS[2]:DO[2] STATUS[1]:DO[1] STATUS[0]:DO[0] CLKIN:CLKIN1 CLKFX:CLKOUT0 CLKFX180:CLKOUT0B CLK2X:CLKOUT1 CLK2X180:CLKOUT1B CLK90:CLKOUT2 CLK270:CLKOUT2B CLKDV:CLKOUT4 CLK0:CLKFBOUT CLK180:CLKFBOUTB CLKFB:CLKFBIN" *)
(* box_type = "PRIMITIVE" *)
MMCME2_ADV #(
.BANDWIDTH("OPTIMIZED"),
.CLKFBOUT_MULT_F(8.000000),
.CLKFBOUT_PHASE(0.000000),
.CLKFBOUT_USE_FINE_PS("FALSE"),
.CLKIN1_PERIOD(10.000000),
.CLKIN2_PERIOD(0.000000),
.CLKOUT0_DIVIDE_F(2.000000),
.CLKOUT0_DUTY_CYCLE(0.500000),
.CLKOUT0_PHASE(0.000000),
.CLKOUT0_USE_FINE_PS("FALSE"),
.CLKOUT1_DIVIDE(4),
.CLKOUT1_DUTY_CYCLE(0.500000),
.CLKOUT1_PHASE(0.000000),
.CLKOUT1_USE_FINE_PS("FALSE"),
.CLKOUT2_DIVIDE(8),
.CLKOUT2_DUTY_CYCLE(0.500000),
.CLKOUT2_PHASE(90.000000),
.CLKOUT2_USE_FINE_PS("FALSE"),
.CLKOUT3_DIVIDE(8),
.CLKOUT3_DUTY_CYCLE(0.500000),
.CLKOUT3_PHASE(0.000000),
.CLKOUT3_USE_FINE_PS("FALSE"),
.CLKOUT4_CASCADE("FALSE"),
.CLKOUT4_DIVIDE(16),
.CLKOUT4_DUTY_CYCLE(0.500000),
.CLKOUT4_PHASE(0.000000),
.CLKOUT4_USE_FINE_PS("FALSE"),
.CLKOUT5_DIVIDE(1),
.CLKOUT5_DUTY_CYCLE(0.500000),
.CLKOUT5_PHASE(0.000000),
.CLKOUT5_USE_FINE_PS("FALSE"),
.CLKOUT6_DIVIDE(1),
.CLKOUT6_DUTY_CYCLE(0.500000),
.CLKOUT6_PHASE(0.000000),
.CLKOUT6_USE_FINE_PS("FALSE"),
.COMPENSATION("ZHOLD"),
.DIVCLK_DIVIDE(1),
.IS_PSINCDEC_INVERTED(1'b1),
.IS_RST_INVERTED(1'b1),
.REF_JITTER1(0.010000),
.REF_JITTER2(0.010000),
.STARTUP_WAIT("FALSE"))
dcm_sp_inst
(.CLKFBIN(CLKFB),
.CLKFBOUT(clk0),
.CLKFBOUTB(NLW_dcm_sp_inst_CLKFBOUTB_UNCONNECTED),
.CLKFBSTOPPED(NLW_dcm_sp_inst_CLKFBSTOPPED_UNCONNECTED),
.CLKIN1(CLKIN),
.CLKIN2(1'b0),
.CLKINSEL(1'b1),
.CLKINSTOPPED(NLW_dcm_sp_inst_CLKINSTOPPED_UNCONNECTED),
.CLKOUT0(NLW_dcm_sp_inst_CLKOUT0_UNCONNECTED),
.CLKOUT0B(NLW_dcm_sp_inst_CLKOUT0B_UNCONNECTED),
.CLKOUT1(NLW_dcm_sp_inst_CLKOUT1_UNCONNECTED),
.CLKOUT1B(NLW_dcm_sp_inst_CLKOUT1B_UNCONNECTED),
.CLKOUT2(NLW_dcm_sp_inst_CLKOUT2_UNCONNECTED),
.CLKOUT2B(NLW_dcm_sp_inst_CLKOUT2B_UNCONNECTED),
.CLKOUT3(NLW_dcm_sp_inst_CLKOUT3_UNCONNECTED),
.CLKOUT3B(NLW_dcm_sp_inst_CLKOUT3B_UNCONNECTED),
.CLKOUT4(clkdv),
.CLKOUT5(NLW_dcm_sp_inst_CLKOUT5_UNCONNECTED),
.CLKOUT6(NLW_dcm_sp_inst_CLKOUT6_UNCONNECTED),
.DADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DCLK(1'b0),
.DEN(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DO(NLW_dcm_sp_inst_DO_UNCONNECTED[15:0]),
.DRDY(NLW_dcm_sp_inst_DRDY_UNCONNECTED),
.DWE(1'b0),
.LOCKED(locked_internal),
.PSCLK(1'b0),
.PSDONE(NLW_dcm_sp_inst_PSDONE_UNCONNECTED),
.PSEN(1'b0),
.PSINCDEC(1'b0),
.PWRDWN(1'b0),
.RST(RST_IBUF));
rmii_ethernet ethernet_inst_1
(.D(NLW_ethernet_inst_1_D_UNCONNECTED[1:0]),
.ETH_CLK_OBUF(ETH_CLK_OBUF),
.INTERNAL_RST_reg(INTERNAL_RST_reg_n_0),
.RXDV_IBUF(NLW_ethernet_inst_1_RXDV_IBUF_UNCONNECTED),
.RXER_IBUF(NLW_ethernet_inst_1_RXER_IBUF_UNCONNECTED),
.TXD_OBUF(TXD_OBUF),
.TXEN_OBUF(TXEN_OBUF));
pwm_audio pwm_audio_inst_1
(.ETH_CLK_OBUF(ETH_CLK_OBUF),
.INTERNAL_RST_reg(INTERNAL_RST_reg_n_0),
.JC_IBUF(JC_IBUF));
endmodule
|
module CHARSVGA
(HSYNCH,
VSYNCH,
VGA_B_OBUF,
ETH_CLK_OBUF,
INTERNAL_RST_reg);
output HSYNCH;
output VSYNCH;
output [0:0]VGA_B_OBUF;
input ETH_CLK_OBUF;
input INTERNAL_RST_reg;
wire [12:1]AOUT;
wire BLANK;
wire BLANK_DEL;
wire BLANK_DEL_DEL;
wire [3:0]DOUT;
wire ETH_CLK_OBUF;
wire HSYNCH;
wire HSYNCH_DEL;
wire INTERNAL_RST_reg;
wire [2:0]PIXCOL_DEL;
wire \PIXCOL_DEL_DEL_reg_n_0_[0] ;
wire \PIXCOL_DEL_DEL_reg_n_0_[1] ;
wire \PIXCOL_DEL_DEL_reg_n_0_[2] ;
wire [7:0]PIXELS_reg__0;
wire TIMEING1_n_0;
wire TIMEING1_n_1;
wire TIMEING1_n_15;
wire TIMEING1_n_16;
wire TIMEING1_n_17;
wire TIMEING1_n_18;
wire TIMEING1_n_19;
wire TIMEING1_n_2;
wire TIMEING1_n_20;
wire [0:0]VGA_B_OBUF;
wire \VGA_R_OBUF[3]_inst_i_2_n_0 ;
wire \VGA_R_OBUF[3]_inst_i_3_n_0 ;
wire VSYNCH;
wire VSYNCH_DEL;
wire [2:0]sel;
wire NLW_PIXELS_reg_REGCEAREGCE_UNCONNECTED;
wire NLW_PIXELS_reg_REGCEB_UNCONNECTED;
wire [15:8]NLW_PIXELS_reg_DOADO_UNCONNECTED;
wire [15:0]NLW_PIXELS_reg_DOBDO_UNCONNECTED;
wire [1:0]NLW_PIXELS_reg_DOPADOP_UNCONNECTED;
wire [1:0]NLW_PIXELS_reg_DOPBDOP_UNCONNECTED;
FDRE BLANK_DEL_DEL_reg
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(BLANK_DEL),
.Q(BLANK_DEL_DEL),
.R(1'b0));
FDRE BLANK_DEL_reg
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(BLANK),
.Q(BLANK_DEL),
.R(1'b0));
BRAM BRAM_INST_1
(.ADDRBWRADDR({AOUT,TIMEING1_n_15}),
.DOBDO(DOUT),
.ETH_CLK_OBUF(ETH_CLK_OBUF),
.pwropt(BLANK));
FDRE HSYNCH_DEL_reg
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(TIMEING1_n_19),
.Q(HSYNCH_DEL),
.R(1'b0));
FDRE HSYNCH_reg
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(HSYNCH_DEL),
.Q(HSYNCH),
.R(1'b0));
FDRE \PIXCOL_DEL_DEL_reg[0]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(PIXCOL_DEL[0]),
.Q(\PIXCOL_DEL_DEL_reg_n_0_[0] ),
.R(1'b0));
FDRE \PIXCOL_DEL_DEL_reg[1]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(PIXCOL_DEL[1]),
.Q(\PIXCOL_DEL_DEL_reg_n_0_[1] ),
.R(1'b0));
FDRE \PIXCOL_DEL_DEL_reg[2]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(PIXCOL_DEL[2]),
.Q(\PIXCOL_DEL_DEL_reg_n_0_[2] ),
.R(1'b0));
FDRE \PIXCOL_DEL_reg[0]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(TIMEING1_n_0),
.Q(PIXCOL_DEL[0]),
.R(1'b0));
FDRE \PIXCOL_DEL_reg[1]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(TIMEING1_n_1),
.Q(PIXCOL_DEL[1]),
.R(1'b0));
FDRE \PIXCOL_DEL_reg[2]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(TIMEING1_n_2),
.Q(PIXCOL_DEL[2]),
.R(1'b0));
(* IS_CLOCK_GATED *)
(* METHODOLOGY_DRC_VIOS = "{SYNTH-6 {cell *THIS*}}" *)
(* POWER_OPTED_CE = "ENARDEN=NEW" *)
(* RTL_RAM_BITS = "16384" *)
(* RTL_RAM_NAME = "PIXELS" *)
(* bram_addr_begin = "0" *)
(* bram_addr_end = "2047" *)
(* bram_slice_begin = "0" *)
(* bram_slice_end = "17" *)
RAMB18E1 #(
.DOA_REG(0),
.DOB_REG(0),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000143E143E1400000000000000141400000800080808080000000000000000),
.INIT_09(256'h0000000000000808006C12320C12120C00E2A4E8102E4A8E00081E281C0A3C08),
.INIT_0A(256'h00101010FE1010100000000022143E0800081020202010080008040202020408),
.INIT_0B(256'h00000204081020400000080000000000000000003E0000000008080000000000),
.INIT_0C(256'h00001C222010221C00003E040810221C00003E0808080C0800001C262A2A321C),
.INIT_0D(256'h000008081020223E00001C221E02221C00001C22203E023E00003C103E121418),
.INIT_0E(256'h0008080000000800000008000000080000001C22203C221C00001C22221C221C),
.INIT_0F(256'h000008000818221C000204081008040200003E00003E00000010080402040810),
.INIT_10(256'h00001C220202221C00001E22221E221E00002222223E221C006CA2BAAABA827C),
.INIT_11(256'h00001C223A02221C00000202021E023E00003E02021E023E00001E222222221E),
.INIT_12(256'h000022120A060A1200000C121010103800003E080808083E00002222223E2222),
.INIT_13(256'h00001C222222221C000022322A262222000022222A2A362200003E0202020202),
.INIT_14(256'h00001E20201C023C000022120A1E221E00681C222222221C000002021E22221E),
.INIT_15(256'h0000142A2A222222000008141422222200001C2222222222000008080808083E),
.INIT_16(256'h001808080808081800003E020408103E00000808081C22220000221408081422),
.INIT_17(256'h00FF000000000000000000000022140800181010101010180000402010080402),
.INIT_18(256'h00001C2202021C0000001E22261A020200005C223C201C000000000000001008),
.INIT_19(256'h001C203C22223C00000002020E02221C00001C023E221C0000003C22322C2020),
.INIT_1A(256'h000022120E0A1202000C12101018001000001C08080C000800002222261A0202),
.INIT_1B(256'h00001C2222221C000000242424241A0000002A2A2A2A160000003E080808080C),
.INIT_1C(256'h00001E201C023C000000040404241A000020203C22322C000002021E22221E00),
.INIT_1D(256'h0000142A2A222200000008141422220000002C121212120000001C22020E0202),
.INIT_1E(256'h001008080408081000003E0408103E00001C203C222222000000221408142200),
.INIT_1F(256'h000000000000000000000060920C000000040808100808040008080808080808),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000143E143E1400000000000000141400000800080808080000000000000000),
.INIT_29(256'h0000000000000808006C12320C12120C00E2A4E8102E4A8E00081E281C0A3C08),
.INIT_2A(256'h00101010FE1010100000000022143E0800081020202010080008040202020408),
.INIT_2B(256'h00000204081020400000080000000000000000003E0000000008080000000000),
.INIT_2C(256'h00001C222010221C00003E040810221C00003E0808080C0800001C262A2A321C),
.INIT_2D(256'h000008081020223E00001C221E02221C00001C22203E023E00003C103E121418),
.INIT_2E(256'h0008080000000800000008000000080000001C22203C221C00001C22221C221C),
.INIT_2F(256'h000008000818221C000204081008040200003E00003E00000010080402040810),
.INIT_30(256'h00001C220202221C00001E22221E221E00002222223E221C006CA2BAAABA827C),
.INIT_31(256'h00001C223A02221C00000202021E023E00003E02021E023E00001E222222221E),
.INIT_32(256'h000022120A060A1200000C121010103800003E080808083E00002222223E2222),
.INIT_33(256'h00001C222222221C000022322A262222000022222A2A362200003E0202020202),
.INIT_34(256'h00001E20201C023C000022120A1E221E00681C222222221C000002021E22221E),
.INIT_35(256'h0000142A2A222222000008141422222200001C2222222222000008080808083E),
.INIT_36(256'h001808080808081800003E020408103E00000808081C22220000221408081422),
.INIT_37(256'h00FF000000000000000000000022140800181010101010180000402010080402),
.INIT_38(256'h00001C2202021C0000001E22261A020200005C223C201C000000000000001008),
.INIT_39(256'h001C203C22223C00000002020E02221C00001C023E221C0000003C22322C2020),
.INIT_3A(256'h000022120E0A1202000C12101018001000001C08080C000800002222261A0202),
.INIT_3B(256'h00001C2222221C000000242424241A0000002A2A2A2A160000003E080808080C),
.INIT_3C(256'h00001E201C023C000000040404241A000020203C22322C000002021E22221E00),
.INIT_3D(256'h0000142A2A222200000008141422220000002C121212120000001C22020E0202),
.INIT_3E(256'h001008080408081000003E0408103E00001C203C222222000000221408142200),
.INIT_3F(256'h000000000000000000000060920C000000040808100808040008080808080808),
.INIT_A(18'h00000),
.INIT_B(18'h00000),
.IS_ENARDEN_INVERTED(1'b1),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("PERFORMANCE"),
.READ_WIDTH_A(9),
.READ_WIDTH_B(0),
.RSTREG_PRIORITY_A("RSTREG"),
.RSTREG_PRIORITY_B("RSTREG"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(18'h00000),
.SRVAL_B(18'h00000),
.WRITE_MODE_A("WRITE_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(9),
.WRITE_WIDTH_B(0))
PIXELS_reg
(.ADDRARDADDR({DOUT,DOUT,sel,1'b0,1'b0,1'b0}),
.ADDRBWRADDR({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
.CLKARDCLK(ETH_CLK_OBUF),
.CLKBWRCLK(1'b0),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
.DIBDI({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
.DIPADIP({1'b0,1'b0}),
.DIPBDIP({1'b1,1'b1}),
.DOADO({NLW_PIXELS_reg_DOADO_UNCONNECTED[15:8],PIXELS_reg__0}),
.DOBDO(NLW_PIXELS_reg_DOBDO_UNCONNECTED[15:0]),
.DOPADOP(NLW_PIXELS_reg_DOPADOP_UNCONNECTED[1:0]),
.DOPBDOP(NLW_PIXELS_reg_DOPBDOP_UNCONNECTED[1:0]),
.ENARDEN(BLANK_DEL),
.ENBWREN(1'b0),
.REGCEAREGCE(NLW_PIXELS_reg_REGCEAREGCE_UNCONNECTED),
.REGCEB(NLW_PIXELS_reg_REGCEB_UNCONNECTED),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.WEA({1'b0,1'b0}),
.WEBWE({1'b0,1'b0,1'b0,1'b0}));
FDRE \PIXROW_DEL_reg[0]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(TIMEING1_n_16),
.Q(sel[0]),
.R(1'b0));
FDRE \PIXROW_DEL_reg[1]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(TIMEING1_n_17),
.Q(sel[1]),
.R(1'b0));
FDRE \PIXROW_DEL_reg[2]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(TIMEING1_n_18),
.Q(sel[2]),
.R(1'b0));
VIDEO_TIME_GEN TIMEING1
(.ADDRBWRADDR({AOUT,TIMEING1_n_15}),
.BLANK(BLANK),
.D(TIMEING1_n_18),
.ETH_CLK_OBUF(ETH_CLK_OBUF),
.HSYNCH_DEL_reg(TIMEING1_n_19),
.INTERNAL_RST_reg(INTERNAL_RST_reg),
.\PIXCOL_DEL_reg[0] (TIMEING1_n_0),
.\PIXCOL_DEL_reg[1] (TIMEING1_n_1),
.\PIXCOL_DEL_reg[2] (TIMEING1_n_2),
.\PIXROW_DEL_reg[0] (TIMEING1_n_16),
.\PIXROW_DEL_reg[1] (TIMEING1_n_17),
.VSYNCH_DEL_reg(TIMEING1_n_20));
LUT4 #(
.INIT(16'h00E2))
\VGA_R_OBUF[3]_inst_i_1
(.I0(\VGA_R_OBUF[3]_inst_i_2_n_0 ),
.I1(\PIXCOL_DEL_DEL_reg_n_0_[2] ),
.I2(\VGA_R_OBUF[3]_inst_i_3_n_0 ),
.I3(BLANK_DEL_DEL),
.O(VGA_B_OBUF));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\VGA_R_OBUF[3]_inst_i_2
(.I0(PIXELS_reg__0[3]),
.I1(PIXELS_reg__0[2]),
.I2(\PIXCOL_DEL_DEL_reg_n_0_[1] ),
.I3(PIXELS_reg__0[1]),
.I4(\PIXCOL_DEL_DEL_reg_n_0_[0] ),
.I5(PIXELS_reg__0[0]),
.O(\VGA_R_OBUF[3]_inst_i_2_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\VGA_R_OBUF[3]_inst_i_3
(.I0(PIXELS_reg__0[7]),
.I1(PIXELS_reg__0[6]),
.I2(\PIXCOL_DEL_DEL_reg_n_0_[1] ),
.I3(PIXELS_reg__0[5]),
.I4(\PIXCOL_DEL_DEL_reg_n_0_[0] ),
.I5(PIXELS_reg__0[4]),
.O(\VGA_R_OBUF[3]_inst_i_3_n_0 ));
FDRE VSYNCH_DEL_reg
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(TIMEING1_n_20),
.Q(VSYNCH_DEL),
.R(1'b0));
FDRE VSYNCH_reg
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(VSYNCH_DEL),
.Q(VSYNCH),
.R(1'b0));
endmodule
|
module I2C
(SDA_TRI,
SCL_TRI,
ETH_CLK_OBUF,
SCL_IBUF,
INTERNAL_RST_reg,
SDA_IBUF);
output SDA_TRI;
output SCL_TRI;
input ETH_CLK_OBUF;
input SCL_IBUF;
input INTERNAL_RST_reg;
input SDA_IBUF;
wire BIT_i_1_n_0;
wire BIT_i_2_n_0;
wire BIT_i_3_n_0;
wire BIT_reg_n_0;
wire [2:0]COUNT;
wire \COUNT[0]_i_1__0_n_0 ;
wire \COUNT[1]_i_1__0_n_0 ;
wire \COUNT[2]_i_1_n_0 ;
wire \COUNT[2]_i_2_n_0 ;
wire ETH_CLK_OBUF;
wire [3:0]GET_BIT_RETURN;
wire \GET_BIT_RETURN[0]_i_1_n_0 ;
wire \GET_BIT_RETURN[3]_i_1_n_0 ;
wire INTERNAL_RST_reg;
wire SCL_IBUF;
wire SCL_I_D;
wire SCL_I_SYNCH;
wire SCL_O_i_1_n_0;
wire SCL_O_i_2_n_0;
wire SCL_O_i_3_n_0;
wire SCL_O_i_4_n_0;
wire SCL_TRI;
wire SDA_IBUF;
wire SDA_I_D;
wire SDA_I_SYNCH;
wire SDA_O_i_1_n_0;
wire SDA_O_i_2_n_0;
wire SDA_TRI;
wire [3:0]SEND_BIT_RETURN;
wire \SEND_BIT_RETURN[0]_i_1_n_0 ;
wire \SEND_BIT_RETURN[3]_i_1_n_0 ;
wire STARTED;
wire STARTED_i_1_n_0;
wire STARTED_i_2_n_0;
wire \STATE[0]_i_2_n_0 ;
wire \STATE[0]_i_3_n_0 ;
wire \STATE[1]_i_1_n_0 ;
wire \STATE[1]_i_2_n_0 ;
wire \STATE[1]_i_3_n_0 ;
wire \STATE[1]_i_4_n_0 ;
wire \STATE[2]_i_1_n_0 ;
wire \STATE[3]_i_2_n_0 ;
wire \STATE[3]_i_3_n_0 ;
wire \STATE[4]_i_1_n_0 ;
wire \STATE[4]_i_2_n_0 ;
wire \STATE[4]_i_3_n_0 ;
wire \STATE[4]_i_4_n_0 ;
wire \STATE[4]_i_5_n_0 ;
wire \STATE[4]_i_6_n_0 ;
wire \STATE_reg[0]_i_1_n_0 ;
wire \STATE_reg[3]_i_1_n_0 ;
wire \STATE_reg_n_0_[0] ;
wire \STATE_reg_n_0_[1] ;
wire \STATE_reg_n_0_[2] ;
wire \STATE_reg_n_0_[3] ;
wire \STATE_reg_n_0_[4] ;
wire S_I2C_IN_ACK_i_1_n_0;
wire S_I2C_IN_ACK_reg_n_0;
wire S_I2C_OUT_STB_i_1_n_0;
wire S_I2C_OUT_STB_reg_n_0;
wire \TIMER[0]_i_1_n_0 ;
wire \TIMER[0]_i_2_n_0 ;
wire \TIMER[0]_i_3_n_0 ;
wire \TIMER[10]_i_1_n_0 ;
wire \TIMER[10]_i_2_n_0 ;
wire \TIMER[10]_i_3_n_0 ;
wire \TIMER[10]_i_5_n_0 ;
wire \TIMER[10]_i_6_n_0 ;
wire \TIMER[10]_i_7_n_0 ;
wire \TIMER[11]_i_1_n_0 ;
wire \TIMER[1]_i_1__2_n_0 ;
wire \TIMER[2]_i_1_n_0 ;
wire \TIMER[3]_i_1__2_n_0 ;
wire \TIMER[4]_i_1__2_n_0 ;
wire \TIMER[4]_i_3_n_0 ;
wire \TIMER[4]_i_4_n_0 ;
wire \TIMER[4]_i_5_n_0 ;
wire \TIMER[4]_i_6_n_0 ;
wire \TIMER[5]_i_1__2_n_0 ;
wire \TIMER[5]_i_3_n_0 ;
wire \TIMER[5]_i_4_n_0 ;
wire \TIMER[5]_i_5_n_0 ;
wire \TIMER[5]_i_6_n_0 ;
wire \TIMER[6]_i_1_n_0 ;
wire \TIMER[7]_i_1_n_0 ;
wire \TIMER[8]_i_1_n_0 ;
wire \TIMER[9]_i_1__2_n_0 ;
wire \TIMER_reg[10]_i_4_n_5 ;
wire \TIMER_reg[10]_i_4_n_6 ;
wire \TIMER_reg[10]_i_4_n_7 ;
wire \TIMER_reg[4]_i_2_n_0 ;
wire \TIMER_reg[4]_i_2_n_4 ;
wire \TIMER_reg[4]_i_2_n_5 ;
wire \TIMER_reg[4]_i_2_n_6 ;
wire \TIMER_reg[4]_i_2_n_7 ;
wire \TIMER_reg[5]_i_2_n_0 ;
wire \TIMER_reg[5]_i_2_n_4 ;
wire \TIMER_reg[5]_i_2_n_5 ;
wire \TIMER_reg[5]_i_2_n_6 ;
wire \TIMER_reg[5]_i_2_n_7 ;
wire \TIMER_reg_n_0_[0] ;
wire \TIMER_reg_n_0_[10] ;
wire \TIMER_reg_n_0_[11] ;
wire \TIMER_reg_n_0_[1] ;
wire \TIMER_reg_n_0_[2] ;
wire \TIMER_reg_n_0_[3] ;
wire \TIMER_reg_n_0_[4] ;
wire \TIMER_reg_n_0_[5] ;
wire \TIMER_reg_n_0_[6] ;
wire \TIMER_reg_n_0_[7] ;
wire \TIMER_reg_n_0_[8] ;
wire \TIMER_reg_n_0_[9] ;
wire g0_b0_n_0;
wire [3:0]\NLW_TIMER_reg[10]_i_4_CO_UNCONNECTED ;
wire [3:3]\NLW_TIMER_reg[10]_i_4_O_UNCONNECTED ;
wire [2:0]\NLW_TIMER_reg[4]_i_2_CO_UNCONNECTED ;
wire [2:0]\NLW_TIMER_reg[5]_i_2_CO_UNCONNECTED ;
LUT6 #(
.INIT(64'hFFF0FA3300000A00))
BIT_i_1
(.I0(SDA_I_SYNCH),
.I1(BIT_i_2_n_0),
.I2(BIT_i_3_n_0),
.I3(\STATE_reg_n_0_[4] ),
.I4(\STATE_reg_n_0_[2] ),
.I5(BIT_reg_n_0),
.O(BIT_i_1_n_0));
LUT3 #(
.INIT(8'h40))
BIT_i_2
(.I0(\STATE_reg_n_0_[1] ),
.I1(\STATE_reg_n_0_[0] ),
.I2(\STATE_reg_n_0_[3] ),
.O(BIT_i_2_n_0));
LUT3 #(
.INIT(8'hEF))
BIT_i_3
(.I0(\STATE_reg_n_0_[0] ),
.I1(\STATE_reg_n_0_[3] ),
.I2(\STATE_reg_n_0_[1] ),
.O(BIT_i_3_n_0));
FDRE BIT_reg
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(BIT_i_1_n_0),
.Q(BIT_reg_n_0),
.R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair23" *)
LUT4 #(
.INIT(16'h1FF0))
\COUNT[0]_i_1__0
(.I0(\STATE_reg_n_0_[2] ),
.I1(\STATE_reg_n_0_[1] ),
.I2(\COUNT[2]_i_2_n_0 ),
.I3(COUNT[0]),
.O(\COUNT[0]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair23" *)
LUT5 #(
.INIT(32'hF1FF1F00))
\COUNT[1]_i_1__0
(.I0(\STATE_reg_n_0_[1] ),
.I1(\STATE_reg_n_0_[2] ),
.I2(COUNT[0]),
.I3(\COUNT[2]_i_2_n_0 ),
.I4(COUNT[1]),
.O(\COUNT[1]_i_1__0_n_0 ));
LUT6 #(
.INIT(64'hFFF1FFFF111F0000))
\COUNT[2]_i_1
(.I0(\STATE_reg_n_0_[2] ),
.I1(\STATE_reg_n_0_[1] ),
.I2(COUNT[0]),
.I3(COUNT[1]),
.I4(\COUNT[2]_i_2_n_0 ),
.I5(COUNT[2]),
.O(\COUNT[2]_i_1_n_0 ));
LUT5 #(
.INIT(32'h00100401))
\COUNT[2]_i_2
(.I0(\STATE_reg_n_0_[4] ),
.I1(\STATE_reg_n_0_[3] ),
.I2(\STATE_reg_n_0_[2] ),
.I3(\STATE_reg_n_0_[1] ),
.I4(\STATE_reg_n_0_[0] ),
.O(\COUNT[2]_i_2_n_0 ));
FDRE \COUNT_reg[0]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(\COUNT[0]_i_1__0_n_0 ),
.Q(COUNT[0]),
.R(1'b0));
FDRE \COUNT_reg[1]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(\COUNT[1]_i_1__0_n_0 ),
.Q(COUNT[1]),
.R(1'b0));
FDRE \COUNT_reg[2]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(\COUNT[2]_i_1_n_0 ),
.Q(COUNT[2]),
.R(1'b0));
LUT6 #(
.INIT(64'hFBFFFFFF00000010))
\GET_BIT_RETURN[0]_i_1
(.I0(\STATE_reg_n_0_[4] ),
.I1(\STATE_reg_n_0_[3] ),
.I2(\STATE_reg_n_0_[2] ),
.I3(\STATE_reg_n_0_[1] ),
.I4(\STATE_reg_n_0_[0] ),
.I5(GET_BIT_RETURN[0]),
.O(\GET_BIT_RETURN[0]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFEF04000000))
\GET_BIT_RETURN[3]_i_1
(.I0(\STATE_reg_n_0_[4] ),
.I1(\STATE_reg_n_0_[3] ),
.I2(\STATE_reg_n_0_[2] ),
.I3(\STATE_reg_n_0_[1] ),
.I4(\STATE_reg_n_0_[0] ),
.I5(GET_BIT_RETURN[3]),
.O(\GET_BIT_RETURN[3]_i_1_n_0 ));
FDRE \GET_BIT_RETURN_reg[0]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(\GET_BIT_RETURN[0]_i_1_n_0 ),
.Q(GET_BIT_RETURN[0]),
.R(1'b0));
FDRE \GET_BIT_RETURN_reg[3]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(\GET_BIT_RETURN[3]_i_1_n_0 ),
.Q(GET_BIT_RETURN[3]),
.R(1'b0));
FDRE SCL_I_D_reg
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(SCL_IBUF),
.Q(SCL_I_D),
.R(1'b0));
FDRE SCL_I_SYNCH_reg
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(SCL_I_D),
.Q(SCL_I_SYNCH),
.R(1'b0));
LUT6 #(
.INIT(64'h403FFFFF403F0000))
SCL_O_i_1
(.I0(\STATE_reg_n_0_[0] ),
.I1(\STATE_reg_n_0_[3] ),
.I2(\STATE_reg_n_0_[2] ),
.I3(\STATE_reg_n_0_[1] ),
.I4(SCL_O_i_2_n_0),
.I5(SCL_TRI),
.O(SCL_O_i_1_n_0));
LUT6 #(
.INIT(64'hFFFFFFFF01000000))
SCL_O_i_2
(.I0(\TIMER[0]_i_2_n_0 ),
.I1(SCL_O_i_3_n_0),
.I2(\TIMER_reg_n_0_[0] ),
.I3(\STATE_reg_n_0_[2] ),
.I4(\STATE_reg_n_0_[0] ),
.I5(SCL_O_i_4_n_0),
.O(SCL_O_i_2_n_0));
LUT2 #(
.INIT(4'h1))
SCL_O_i_3
(.I0(\STATE_reg_n_0_[4] ),
.I1(\STATE_reg_n_0_[3] ),
.O(SCL_O_i_3_n_0));
LUT6 #(
.INIT(64'h3C0C0C2C3C000000))
SCL_O_i_4
(.I0(\TIMER[10]_i_3_n_0 ),
.I1(\STATE_reg_n_0_[0] ),
.I2(\STATE_reg_n_0_[1] ),
.I3(\STATE_reg_n_0_[2] ),
.I4(\STATE_reg_n_0_[3] ),
.I5(\STATE_reg_n_0_[4] ),
.O(SCL_O_i_4_n_0));
FDSE SCL_O_reg
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(SCL_O_i_1_n_0),
.Q(SCL_TRI),
.S(INTERNAL_RST_reg));
FDRE SDA_I_D_reg
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(SDA_IBUF),
.Q(SDA_I_D),
.R(1'b0));
FDRE SDA_I_SYNCH_reg
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(SDA_I_D),
.Q(SDA_I_SYNCH),
.R(1'b0));
LUT6 #(
.INIT(64'hADA5FFFFADA50000))
SDA_O_i_1
(.I0(\STATE_reg_n_0_[3] ),
.I1(BIT_reg_n_0),
.I2(\STATE_reg_n_0_[1] ),
.I3(\STATE_reg_n_0_[2] ),
.I4(SDA_O_i_2_n_0),
.I5(SDA_TRI),
.O(SDA_O_i_1_n_0));
LUT6 #(
.INIT(64'h9098803080988030))
SDA_O_i_2
(.I0(\STATE_reg_n_0_[2] ),
.I1(\STATE_reg_n_0_[0] ),
.I2(\STATE_reg_n_0_[4] ),
.I3(\STATE_reg_n_0_[1] ),
.I4(\STATE_reg_n_0_[3] ),
.I5(\TIMER[10]_i_3_n_0 ),
.O(SDA_O_i_2_n_0));
FDSE SDA_O_reg
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(SDA_O_i_1_n_0),
.Q(SDA_TRI),
.S(INTERNAL_RST_reg));
LUT6 #(
.INIT(64'hFFFFFFBF01000000))
\SEND_BIT_RETURN[0]_i_1
(.I0(\STATE_reg_n_0_[4] ),
.I1(\STATE_reg_n_0_[3] ),
.I2(\STATE_reg_n_0_[0] ),
.I3(\STATE_reg_n_0_[1] ),
.I4(\STATE_reg_n_0_[2] ),
.I5(SEND_BIT_RETURN[0]),
.O(\SEND_BIT_RETURN[0]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFEFFFFFF00000040))
\SEND_BIT_RETURN[3]_i_1
(.I0(\STATE_reg_n_0_[4] ),
.I1(\STATE_reg_n_0_[3] ),
.I2(\STATE_reg_n_0_[0] ),
.I3(\STATE_reg_n_0_[1] ),
.I4(\STATE_reg_n_0_[2] ),
.I5(SEND_BIT_RETURN[3]),
.O(\SEND_BIT_RETURN[3]_i_1_n_0 ));
FDRE \SEND_BIT_RETURN_reg[0]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(\SEND_BIT_RETURN[0]_i_1_n_0 ),
.Q(SEND_BIT_RETURN[0]),
.R(1'b0));
FDRE \SEND_BIT_RETURN_reg[3]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(\SEND_BIT_RETURN[3]_i_1_n_0 ),
.Q(SEND_BIT_RETURN[3]),
.R(1'b0));
LUT6 #(
.INIT(64'h7FFDFFFD08000000))
STARTED_i_1
(.I0(STARTED_i_2_n_0),
.I1(\STATE_reg_n_0_[4] ),
.I2(\STATE_reg_n_0_[3] ),
.I3(\STATE_reg_n_0_[2] ),
.I4(\TIMER[10]_i_3_n_0 ),
.I5(STARTED),
.O(STARTED_i_1_n_0));
LUT4 #(
.INIT(16'hEAAB))
STARTED_i_2
(.I0(\STATE_reg_n_0_[3] ),
.I1(\STATE_reg_n_0_[1] ),
.I2(\STATE_reg_n_0_[2] ),
.I3(\STATE_reg_n_0_[0] ),
.O(STARTED_i_2_n_0));
FDRE STARTED_reg
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(STARTED_i_1_n_0),
.Q(STARTED),
.R(1'b0));
LUT5 #(
.INIT(32'hB0FC3CCF))
\STATE[0]_i_2
(.I0(SEND_BIT_RETURN[0]),
.I1(\STATE_reg_n_0_[3] ),
.I2(\STATE_reg_n_0_[1] ),
.I3(\STATE_reg_n_0_[0] ),
.I4(\STATE_reg_n_0_[2] ),
.O(\STATE[0]_i_2_n_0 ));
LUT6 #(
.INIT(64'h040004005F5F5A5F))
\STATE[0]_i_3
(.I0(\STATE_reg_n_0_[3] ),
.I1(STARTED),
.I2(\STATE_reg_n_0_[2] ),
.I3(\STATE_reg_n_0_[1] ),
.I4(GET_BIT_RETURN[0]),
.I5(\STATE_reg_n_0_[0] ),
.O(\STATE[0]_i_3_n_0 ));
LUT2 #(
.INIT(4'h2))
\STATE[1]_i_1
(.I0(\STATE[1]_i_2_n_0 ),
.I1(\STATE[1]_i_3_n_0 ),
.O(\STATE[1]_i_1_n_0 ));
LUT6 #(
.INIT(64'h12781258FFFFFFFF))
\STATE[1]_i_2
(.I0(\STATE_reg_n_0_[1] ),
.I1(\STATE_reg_n_0_[2] ),
.I2(\STATE_reg_n_0_[0] ),
.I3(\STATE_reg_n_0_[3] ),
.I4(STARTED),
.I5(\STATE_reg_n_0_[4] ),
.O(\STATE[1]_i_2_n_0 ));
LUT6 #(
.INIT(64'h0005010555155055))
\STATE[1]_i_3
(.I0(\STATE_reg_n_0_[4] ),
.I1(\STATE[1]_i_4_n_0 ),
.I2(\STATE_reg_n_0_[3] ),
.I3(\STATE_reg_n_0_[0] ),
.I4(\STATE_reg_n_0_[1] ),
.I5(\STATE_reg_n_0_[2] ),
.O(\STATE[1]_i_3_n_0 ));
LUT3 #(
.INIT(8'h01))
\STATE[1]_i_4
(.I0(COUNT[2]),
.I1(COUNT[1]),
.I2(COUNT[0]),
.O(\STATE[1]_i_4_n_0 ));
LUT6 #(
.INIT(64'h406EB828406E3828))
\STATE[2]_i_1
(.I0(\STATE_reg_n_0_[2] ),
.I1(\STATE_reg_n_0_[1] ),
.I2(\STATE_reg_n_0_[0] ),
.I3(\STATE_reg_n_0_[3] ),
.I4(\STATE_reg_n_0_[4] ),
.I5(SEND_BIT_RETURN[0]),
.O(\STATE[2]_i_1_n_0 ));
LUT5 #(
.INIT(32'h8F00F5F0))
\STATE[3]_i_2
(.I0(\STATE_reg_n_0_[2] ),
.I1(SEND_BIT_RETURN[3]),
.I2(\STATE_reg_n_0_[1] ),
.I3(\STATE_reg_n_0_[3] ),
.I4(\STATE_reg_n_0_[0] ),
.O(\STATE[3]_i_2_n_0 ));
LUT5 #(
.INIT(32'h0F0F0200))
\STATE[3]_i_3
(.I0(GET_BIT_RETURN[3]),
.I1(\STATE_reg_n_0_[0] ),
.I2(\STATE_reg_n_0_[2] ),
.I3(\STATE_reg_n_0_[1] ),
.I4(\STATE_reg_n_0_[3] ),
.O(\STATE[3]_i_3_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFFF4F4F0FF))
\STATE[4]_i_1
(.I0(\STATE[4]_i_3_n_0 ),
.I1(\STATE_reg_n_0_[0] ),
.I2(\STATE[4]_i_4_n_0 ),
.I3(\STATE[4]_i_5_n_0 ),
.I4(\STATE_reg_n_0_[1] ),
.I5(\STATE[4]_i_6_n_0 ),
.O(\STATE[4]_i_1_n_0 ));
LUT5 #(
.INIT(32'h1301FD80))
\STATE[4]_i_2
(.I0(\STATE_reg_n_0_[1] ),
.I1(\STATE_reg_n_0_[3] ),
.I2(\STATE_reg_n_0_[0] ),
.I3(\STATE_reg_n_0_[4] ),
.I4(\STATE_reg_n_0_[2] ),
.O(\STATE[4]_i_2_n_0 ));
LUT6 #(
.INIT(64'hEEEEEE0FEE00EE0F))
\STATE[4]_i_3
(.I0(\TIMER_reg_n_0_[0] ),
.I1(\TIMER[0]_i_2_n_0 ),
.I2(S_I2C_OUT_STB_reg_n_0),
.I3(\STATE_reg_n_0_[3] ),
.I4(\STATE_reg_n_0_[4] ),
.I5(\STATE_reg_n_0_[2] ),
.O(\STATE[4]_i_3_n_0 ));
LUT5 #(
.INIT(32'h80AA8000))
\STATE[4]_i_4
(.I0(\TIMER[10]_i_3_n_0 ),
.I1(\STATE_reg_n_0_[2] ),
.I2(\STATE_reg_n_0_[3] ),
.I3(\STATE_reg_n_0_[0] ),
.I4(\STATE_reg_n_0_[4] ),
.O(\STATE[4]_i_4_n_0 ));
LUT6 #(
.INIT(64'hFC0C0CDCFCFCDCDC))
\STATE[4]_i_5
(.I0(S_I2C_IN_ACK_reg_n_0),
.I1(\STATE_reg_n_0_[4] ),
.I2(\STATE_reg_n_0_[0] ),
.I3(\STATE_reg_n_0_[3] ),
.I4(\STATE_reg_n_0_[2] ),
.I5(SCL_I_SYNCH),
.O(\STATE[4]_i_5_n_0 ));
LUT5 #(
.INIT(32'h004075BB))
\STATE[4]_i_6
(.I0(\STATE_reg_n_0_[2] ),
.I1(\STATE_reg_n_0_[0] ),
.I2(SCL_I_SYNCH),
.I3(\STATE_reg_n_0_[3] ),
.I4(\STATE_reg_n_0_[4] ),
.O(\STATE[4]_i_6_n_0 ));
FDRE \STATE_reg[0]
(.C(ETH_CLK_OBUF),
.CE(\STATE[4]_i_1_n_0 ),
.D(\STATE_reg[0]_i_1_n_0 ),
.Q(\STATE_reg_n_0_[0] ),
.R(INTERNAL_RST_reg));
MUXF7 \STATE_reg[0]_i_1
(.I0(\STATE[0]_i_2_n_0 ),
.I1(\STATE[0]_i_3_n_0 ),
.O(\STATE_reg[0]_i_1_n_0 ),
.S(\STATE_reg_n_0_[4] ));
FDRE \STATE_reg[1]
(.C(ETH_CLK_OBUF),
.CE(\STATE[4]_i_1_n_0 ),
.D(\STATE[1]_i_1_n_0 ),
.Q(\STATE_reg_n_0_[1] ),
.R(INTERNAL_RST_reg));
FDRE \STATE_reg[2]
(.C(ETH_CLK_OBUF),
.CE(\STATE[4]_i_1_n_0 ),
.D(\STATE[2]_i_1_n_0 ),
.Q(\STATE_reg_n_0_[2] ),
.R(INTERNAL_RST_reg));
FDRE \STATE_reg[3]
(.C(ETH_CLK_OBUF),
.CE(\STATE[4]_i_1_n_0 ),
.D(\STATE_reg[3]_i_1_n_0 ),
.Q(\STATE_reg_n_0_[3] ),
.R(INTERNAL_RST_reg));
MUXF7 \STATE_reg[3]_i_1
(.I0(\STATE[3]_i_2_n_0 ),
.I1(\STATE[3]_i_3_n_0 ),
.O(\STATE_reg[3]_i_1_n_0 ),
.S(\STATE_reg_n_0_[4] ));
FDRE \STATE_reg[4]
(.C(ETH_CLK_OBUF),
.CE(\STATE[4]_i_1_n_0 ),
.D(\STATE[4]_i_2_n_0 ),
.Q(\STATE_reg_n_0_[4] ),
.R(INTERNAL_RST_reg));
LUT6 #(
.INIT(64'hFFFEFFFF00010000))
S_I2C_IN_ACK_i_1
(.I0(\STATE_reg_n_0_[2] ),
.I1(\STATE_reg_n_0_[1] ),
.I2(\STATE_reg_n_0_[3] ),
.I3(\STATE_reg_n_0_[4] ),
.I4(\STATE_reg_n_0_[0] ),
.I5(S_I2C_IN_ACK_reg_n_0),
.O(S_I2C_IN_ACK_i_1_n_0));
FDRE S_I2C_IN_ACK_reg
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(S_I2C_IN_ACK_i_1_n_0),
.Q(S_I2C_IN_ACK_reg_n_0),
.R(1'b0));
LUT6 #(
.INIT(64'hFFFDFFFF00020000))
S_I2C_OUT_STB_i_1
(.I0(\STATE_reg_n_0_[1] ),
.I1(\STATE_reg_n_0_[2] ),
.I2(\STATE_reg_n_0_[3] ),
.I3(\STATE_reg_n_0_[4] ),
.I4(\STATE_reg_n_0_[0] ),
.I5(S_I2C_OUT_STB_reg_n_0),
.O(S_I2C_OUT_STB_i_1_n_0));
FDRE S_I2C_OUT_STB_reg
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(S_I2C_OUT_STB_i_1_n_0),
.Q(S_I2C_OUT_STB_reg_n_0),
.R(INTERNAL_RST_reg));
LUT5 #(
.INIT(32'h00FFA800))
\TIMER[0]_i_1
(.I0(\TIMER[0]_i_2_n_0 ),
.I1(\STATE_reg_n_0_[4] ),
.I2(\STATE_reg_n_0_[3] ),
.I3(g0_b0_n_0),
.I4(\TIMER_reg_n_0_[0] ),
.O(\TIMER[0]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFFFFFFFFFE))
\TIMER[0]_i_2
(.I0(\TIMER_reg_n_0_[3] ),
.I1(\TIMER_reg_n_0_[11] ),
.I2(\TIMER_reg_n_0_[7] ),
.I3(\TIMER_reg_n_0_[2] ),
.I4(\TIMER_reg_n_0_[1] ),
.I5(\TIMER[0]_i_3_n_0 ),
.O(\TIMER[0]_i_2_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFFFFFFFFFE))
\TIMER[0]_i_3
(.I0(\TIMER_reg_n_0_[6] ),
.I1(\TIMER_reg_n_0_[8] ),
.I2(\TIMER_reg_n_0_[9] ),
.I3(\TIMER_reg_n_0_[10] ),
.I4(\TIMER_reg_n_0_[5] ),
.I5(\TIMER_reg_n_0_[4] ),
.O(\TIMER[0]_i_3_n_0 ));
LUT2 #(
.INIT(4'h8))
\TIMER[10]_i_1
(.I0(\TIMER[10]_i_3_n_0 ),
.I1(g0_b0_n_0),
.O(\TIMER[10]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair30" *)
LUT3 #(
.INIT(8'hA8))
\TIMER[10]_i_2
(.I0(\TIMER_reg[10]_i_4_n_6 ),
.I1(\STATE_reg_n_0_[3] ),
.I2(\STATE_reg_n_0_[4] ),
.O(\TIMER[10]_i_2_n_0 ));
LUT2 #(
.INIT(4'h1))
\TIMER[10]_i_3
(.I0(\TIMER_reg_n_0_[0] ),
.I1(\TIMER[0]_i_2_n_0 ),
.O(\TIMER[10]_i_3_n_0 ));
LUT1 #(
.INIT(2'h1))
\TIMER[10]_i_5
(.I0(\TIMER_reg_n_0_[11] ),
.O(\TIMER[10]_i_5_n_0 ));
LUT1 #(
.INIT(2'h1))
\TIMER[10]_i_6
(.I0(\TIMER_reg_n_0_[10] ),
.O(\TIMER[10]_i_6_n_0 ));
LUT1 #(
.INIT(2'h1))
\TIMER[10]_i_7
(.I0(\TIMER_reg_n_0_[9] ),
.O(\TIMER[10]_i_7_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair28" *)
LUT3 #(
.INIT(8'hAB))
\TIMER[11]_i_1
(.I0(\TIMER_reg[10]_i_4_n_5 ),
.I1(\STATE_reg_n_0_[3] ),
.I2(\STATE_reg_n_0_[4] ),
.O(\TIMER[11]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair30" *)
LUT3 #(
.INIT(8'hA8))
\TIMER[1]_i_1__2
(.I0(\TIMER_reg[4]_i_2_n_7 ),
.I1(\STATE_reg_n_0_[3] ),
.I2(\STATE_reg_n_0_[4] ),
.O(\TIMER[1]_i_1__2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair27" *)
LUT3 #(
.INIT(8'hAB))
\TIMER[2]_i_1
(.I0(\TIMER_reg[4]_i_2_n_6 ),
.I1(\STATE_reg_n_0_[3] ),
.I2(\STATE_reg_n_0_[4] ),
.O(\TIMER[2]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair31" *)
LUT3 #(
.INIT(8'hA8))
\TIMER[3]_i_1__2
(.I0(\TIMER_reg[4]_i_2_n_5 ),
.I1(\STATE_reg_n_0_[3] ),
.I2(\STATE_reg_n_0_[4] ),
.O(\TIMER[3]_i_1__2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair32" *)
LUT3 #(
.INIT(8'hA8))
\TIMER[4]_i_1__2
(.I0(\TIMER_reg[4]_i_2_n_4 ),
.I1(\STATE_reg_n_0_[3] ),
.I2(\STATE_reg_n_0_[4] ),
.O(\TIMER[4]_i_1__2_n_0 ));
LUT1 #(
.INIT(2'h1))
\TIMER[4]_i_3
(.I0(\TIMER_reg_n_0_[4] ),
.O(\TIMER[4]_i_3_n_0 ));
LUT1 #(
.INIT(2'h1))
\TIMER[4]_i_4
(.I0(\TIMER_reg_n_0_[3] ),
.O(\TIMER[4]_i_4_n_0 ));
LUT1 #(
.INIT(2'h1))
\TIMER[4]_i_5
(.I0(\TIMER_reg_n_0_[2] ),
.O(\TIMER[4]_i_5_n_0 ));
LUT1 #(
.INIT(2'h1))
\TIMER[4]_i_6
(.I0(\TIMER_reg_n_0_[1] ),
.O(\TIMER[4]_i_6_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair32" *)
LUT3 #(
.INIT(8'hA8))
\TIMER[5]_i_1__2
(.I0(\TIMER_reg[5]_i_2_n_7 ),
.I1(\STATE_reg_n_0_[3] ),
.I2(\STATE_reg_n_0_[4] ),
.O(\TIMER[5]_i_1__2_n_0 ));
LUT1 #(
.INIT(2'h1))
\TIMER[5]_i_3
(.I0(\TIMER_reg_n_0_[8] ),
.O(\TIMER[5]_i_3_n_0 ));
LUT1 #(
.INIT(2'h1))
\TIMER[5]_i_4
(.I0(\TIMER_reg_n_0_[7] ),
.O(\TIMER[5]_i_4_n_0 ));
LUT1 #(
.INIT(2'h1))
\TIMER[5]_i_5
(.I0(\TIMER_reg_n_0_[6] ),
.O(\TIMER[5]_i_5_n_0 ));
LUT1 #(
.INIT(2'h1))
\TIMER[5]_i_6
(.I0(\TIMER_reg_n_0_[5] ),
.O(\TIMER[5]_i_6_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair28" *)
LUT3 #(
.INIT(8'hAB))
\TIMER[6]_i_1
(.I0(\TIMER_reg[5]_i_2_n_6 ),
.I1(\STATE_reg_n_0_[3] ),
.I2(\STATE_reg_n_0_[4] ),
.O(\TIMER[6]_i_1_n_0 ));
LUT3 #(
.INIT(8'hAB))
\TIMER[7]_i_1
(.I0(\TIMER_reg[5]_i_2_n_5 ),
.I1(\STATE_reg_n_0_[3] ),
.I2(\STATE_reg_n_0_[4] ),
.O(\TIMER[7]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair27" *)
LUT3 #(
.INIT(8'hAB))
\TIMER[8]_i_1
(.I0(\TIMER_reg[5]_i_2_n_4 ),
.I1(\STATE_reg_n_0_[3] ),
.I2(\STATE_reg_n_0_[4] ),
.O(\TIMER[8]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair31" *)
LUT3 #(
.INIT(8'hA8))
\TIMER[9]_i_1__2
(.I0(\TIMER_reg[10]_i_4_n_7 ),
.I1(\STATE_reg_n_0_[3] ),
.I2(\STATE_reg_n_0_[4] ),
.O(\TIMER[9]_i_1__2_n_0 ));
FDRE \TIMER_reg[0]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(\TIMER[0]_i_1_n_0 ),
.Q(\TIMER_reg_n_0_[0] ),
.R(1'b0));
FDRE \TIMER_reg[10]
(.C(ETH_CLK_OBUF),
.CE(g0_b0_n_0),
.D(\TIMER[10]_i_2_n_0 ),
.Q(\TIMER_reg_n_0_[10] ),
.R(\TIMER[10]_i_1_n_0 ));
CARRY4 \TIMER_reg[10]_i_4
(.CI(\TIMER_reg[5]_i_2_n_0 ),
.CO(\NLW_TIMER_reg[10]_i_4_CO_UNCONNECTED [3:0]),
.CYINIT(1'b0),
.DI({1'b0,1'b0,\TIMER_reg_n_0_[10] ,\TIMER_reg_n_0_[9] }),
.O({\NLW_TIMER_reg[10]_i_4_O_UNCONNECTED [3],\TIMER_reg[10]_i_4_n_5 ,\TIMER_reg[10]_i_4_n_6 ,\TIMER_reg[10]_i_4_n_7 }),
.S({1'b0,\TIMER[10]_i_5_n_0 ,\TIMER[10]_i_6_n_0 ,\TIMER[10]_i_7_n_0 }));
FDSE \TIMER_reg[11]
(.C(ETH_CLK_OBUF),
.CE(g0_b0_n_0),
.D(\TIMER[11]_i_1_n_0 ),
.Q(\TIMER_reg_n_0_[11] ),
.S(\TIMER[10]_i_1_n_0 ));
FDRE \TIMER_reg[1]
(.C(ETH_CLK_OBUF),
.CE(g0_b0_n_0),
.D(\TIMER[1]_i_1__2_n_0 ),
.Q(\TIMER_reg_n_0_[1] ),
.R(\TIMER[10]_i_1_n_0 ));
FDSE \TIMER_reg[2]
(.C(ETH_CLK_OBUF),
.CE(g0_b0_n_0),
.D(\TIMER[2]_i_1_n_0 ),
.Q(\TIMER_reg_n_0_[2] ),
.S(\TIMER[10]_i_1_n_0 ));
FDRE \TIMER_reg[3]
(.C(ETH_CLK_OBUF),
.CE(g0_b0_n_0),
.D(\TIMER[3]_i_1__2_n_0 ),
.Q(\TIMER_reg_n_0_[3] ),
.R(\TIMER[10]_i_1_n_0 ));
FDRE \TIMER_reg[4]
(.C(ETH_CLK_OBUF),
.CE(g0_b0_n_0),
.D(\TIMER[4]_i_1__2_n_0 ),
.Q(\TIMER_reg_n_0_[4] ),
.R(\TIMER[10]_i_1_n_0 ));
CARRY4 \TIMER_reg[4]_i_2
(.CI(1'b0),
.CO({\TIMER_reg[4]_i_2_n_0 ,\NLW_TIMER_reg[4]_i_2_CO_UNCONNECTED [2:0]}),
.CYINIT(\TIMER_reg_n_0_[0] ),
.DI({\TIMER_reg_n_0_[4] ,\TIMER_reg_n_0_[3] ,\TIMER_reg_n_0_[2] ,\TIMER_reg_n_0_[1] }),
.O({\TIMER_reg[4]_i_2_n_4 ,\TIMER_reg[4]_i_2_n_5 ,\TIMER_reg[4]_i_2_n_6 ,\TIMER_reg[4]_i_2_n_7 }),
.S({\TIMER[4]_i_3_n_0 ,\TIMER[4]_i_4_n_0 ,\TIMER[4]_i_5_n_0 ,\TIMER[4]_i_6_n_0 }));
FDRE \TIMER_reg[5]
(.C(ETH_CLK_OBUF),
.CE(g0_b0_n_0),
.D(\TIMER[5]_i_1__2_n_0 ),
.Q(\TIMER_reg_n_0_[5] ),
.R(\TIMER[10]_i_1_n_0 ));
CARRY4 \TIMER_reg[5]_i_2
(.CI(\TIMER_reg[4]_i_2_n_0 ),
.CO({\TIMER_reg[5]_i_2_n_0 ,\NLW_TIMER_reg[5]_i_2_CO_UNCONNECTED [2:0]}),
.CYINIT(1'b0),
.DI({\TIMER_reg_n_0_[8] ,\TIMER_reg_n_0_[7] ,\TIMER_reg_n_0_[6] ,\TIMER_reg_n_0_[5] }),
.O({\TIMER_reg[5]_i_2_n_4 ,\TIMER_reg[5]_i_2_n_5 ,\TIMER_reg[5]_i_2_n_6 ,\TIMER_reg[5]_i_2_n_7 }),
.S({\TIMER[5]_i_3_n_0 ,\TIMER[5]_i_4_n_0 ,\TIMER[5]_i_5_n_0 ,\TIMER[5]_i_6_n_0 }));
FDSE \TIMER_reg[6]
(.C(ETH_CLK_OBUF),
.CE(g0_b0_n_0),
.D(\TIMER[6]_i_1_n_0 ),
.Q(\TIMER_reg_n_0_[6] ),
.S(\TIMER[10]_i_1_n_0 ));
FDSE \TIMER_reg[7]
(.C(ETH_CLK_OBUF),
.CE(g0_b0_n_0),
.D(\TIMER[7]_i_1_n_0 ),
.Q(\TIMER_reg_n_0_[7] ),
.S(\TIMER[10]_i_1_n_0 ));
FDSE \TIMER_reg[8]
(.C(ETH_CLK_OBUF),
.CE(g0_b0_n_0),
.D(\TIMER[8]_i_1_n_0 ),
.Q(\TIMER_reg_n_0_[8] ),
.S(\TIMER[10]_i_1_n_0 ));
FDRE \TIMER_reg[9]
(.C(ETH_CLK_OBUF),
.CE(g0_b0_n_0),
.D(\TIMER[9]_i_1__2_n_0 ),
.Q(\TIMER_reg_n_0_[9] ),
.R(\TIMER[10]_i_1_n_0 ));
LUT5 #(
.INIT(32'h1DD5A001))
g0_b0
(.I0(\STATE_reg_n_0_[0] ),
.I1(\STATE_reg_n_0_[1] ),
.I2(\STATE_reg_n_0_[2] ),
.I3(\STATE_reg_n_0_[3] ),
.I4(\STATE_reg_n_0_[4] ),
.O(g0_b0_n_0));
endmodule
|
module IOBUF_UNIQ_BASE_
(IO,
O,
I,
T);
inout IO;
output O;
input I;
input T;
wire I;
wire IO;
wire O;
wire T;
IBUF IBUF
(.I(IO),
.O(O));
OBUFT OBUFT
(.I(I),
.O(IO),
.T(T));
endmodule
|
module IOBUF_HD3
(IO,
O,
I,
T);
inout IO;
output O;
input I;
input T;
wire I;
wire IO;
wire O;
wire T;
IBUF #(
.IOSTANDARD("DEFAULT"))
IBUF
(.I(IO),
.O(O));
OBUFT #(
.IOSTANDARD("DEFAULT"))
OBUFT
(.I(I),
.O(IO),
.T(T));
endmodule
|
module PWM
(LED_R_PWM_OBUF,
ETH_CLK_OBUF);
output LED_R_PWM_OBUF;
input ETH_CLK_OBUF;
wire \COUNT[0]_i_1__1_n_0 ;
wire \COUNT[1]_i_1__1_n_0 ;
wire \COUNT[1]_i_2_n_0 ;
wire \COUNT[2]_i_1__0_n_0 ;
wire \COUNT[3]_i_1_n_0 ;
wire \COUNT[3]_i_2_n_0 ;
wire \COUNT[4]_i_1_n_0 ;
wire \COUNT[5]_i_1_n_0 ;
wire \COUNT[6]_i_1_n_0 ;
wire \COUNT[7]_i_1_n_0 ;
wire \COUNT[7]_i_2_n_0 ;
wire \COUNT[7]_i_3_n_0 ;
wire \COUNT_reg_n_0_[0] ;
wire \COUNT_reg_n_0_[1] ;
wire \COUNT_reg_n_0_[2] ;
wire \COUNT_reg_n_0_[3] ;
wire \COUNT_reg_n_0_[4] ;
wire \COUNT_reg_n_0_[5] ;
wire \COUNT_reg_n_0_[6] ;
wire \COUNT_reg_n_0_[7] ;
wire ETH_CLK_OBUF;
wire LED_R_PWM_OBUF;
wire OUT_BIT_i_10_n_0;
wire OUT_BIT_i_1_n_0;
wire OUT_BIT_i_3_n_0;
wire OUT_BIT_i_4_n_0;
wire OUT_BIT_i_5_n_0;
wire OUT_BIT_i_6_n_0;
wire OUT_BIT_i_7_n_0;
wire OUT_BIT_i_8_n_0;
wire OUT_BIT_i_9_n_0;
wire [9:0]TIMER;
wire \TIMER[4]_i_2_n_0 ;
wire \TIMER[9]_i_2_n_0 ;
wire \TIMER_reg_n_0_[0] ;
wire \TIMER_reg_n_0_[1] ;
wire \TIMER_reg_n_0_[2] ;
wire \TIMER_reg_n_0_[3] ;
wire \TIMER_reg_n_0_[4] ;
wire \TIMER_reg_n_0_[5] ;
wire \TIMER_reg_n_0_[6] ;
wire \TIMER_reg_n_0_[7] ;
wire \TIMER_reg_n_0_[8] ;
wire \TIMER_reg_n_0_[9] ;
wire p_0_in;
wire [2:0]NLW_OUT_BIT_reg_i_2_CO_UNCONNECTED;
wire [3:0]NLW_OUT_BIT_reg_i_2_O_UNCONNECTED;
LUT6 #(
.INIT(64'h2333333333333333))
\COUNT[0]_i_1__1
(.I0(\COUNT[7]_i_3_n_0 ),
.I1(\COUNT_reg_n_0_[0] ),
.I2(\COUNT_reg_n_0_[5] ),
.I3(\COUNT_reg_n_0_[4] ),
.I4(\COUNT_reg_n_0_[7] ),
.I5(\COUNT_reg_n_0_[6] ),
.O(\COUNT[0]_i_1__1_n_0 ));
LUT5 #(
.INIT(32'h00FFBF00))
\COUNT[1]_i_1__1
(.I0(\COUNT[1]_i_2_n_0 ),
.I1(\COUNT_reg_n_0_[3] ),
.I2(\COUNT_reg_n_0_[2] ),
.I3(\COUNT_reg_n_0_[1] ),
.I4(\COUNT_reg_n_0_[0] ),
.O(\COUNT[1]_i_1__1_n_0 ));
LUT4 #(
.INIT(16'h7FFF))
\COUNT[1]_i_2
(.I0(\COUNT_reg_n_0_[5] ),
.I1(\COUNT_reg_n_0_[4] ),
.I2(\COUNT_reg_n_0_[7] ),
.I3(\COUNT_reg_n_0_[6] ),
.O(\COUNT[1]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair36" *)
LUT5 #(
.INIT(32'hFFC011C0))
\COUNT[2]_i_1__0
(.I0(\COUNT_reg_n_0_[3] ),
.I1(\COUNT_reg_n_0_[0] ),
.I2(\COUNT_reg_n_0_[1] ),
.I3(\COUNT_reg_n_0_[2] ),
.I4(\COUNT[3]_i_2_n_0 ),
.O(\COUNT[2]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair36" *)
LUT5 #(
.INIT(32'hFF805580))
\COUNT[3]_i_1
(.I0(\COUNT_reg_n_0_[2] ),
.I1(\COUNT_reg_n_0_[1] ),
.I2(\COUNT_reg_n_0_[0] ),
.I3(\COUNT_reg_n_0_[3] ),
.I4(\COUNT[3]_i_2_n_0 ),
.O(\COUNT[3]_i_1_n_0 ));
LUT6 #(
.INIT(64'h15555555FFFFFFFF))
\COUNT[3]_i_2
(.I0(\COUNT_reg_n_0_[0] ),
.I1(\COUNT_reg_n_0_[5] ),
.I2(\COUNT_reg_n_0_[4] ),
.I3(\COUNT_reg_n_0_[7] ),
.I4(\COUNT_reg_n_0_[6] ),
.I5(\COUNT_reg_n_0_[1] ),
.O(\COUNT[3]_i_2_n_0 ));
LUT6 #(
.INIT(64'hFF00FF7F00FF0000))
\COUNT[4]_i_1
(.I0(\COUNT_reg_n_0_[7] ),
.I1(\COUNT_reg_n_0_[6] ),
.I2(\COUNT_reg_n_0_[5] ),
.I3(\COUNT[7]_i_3_n_0 ),
.I4(\COUNT_reg_n_0_[0] ),
.I5(\COUNT_reg_n_0_[4] ),
.O(\COUNT[4]_i_1_n_0 ));
LUT6 #(
.INIT(64'hAABFFFFF55000000))
\COUNT[5]_i_1
(.I0(\COUNT[7]_i_3_n_0 ),
.I1(\COUNT_reg_n_0_[7] ),
.I2(\COUNT_reg_n_0_[6] ),
.I3(\COUNT_reg_n_0_[0] ),
.I4(\COUNT_reg_n_0_[4] ),
.I5(\COUNT_reg_n_0_[5] ),
.O(\COUNT[5]_i_1_n_0 ));
LUT6 #(
.INIT(64'hF01CF0F0F0F0F0F0))
\COUNT[6]_i_1
(.I0(\COUNT_reg_n_0_[7] ),
.I1(\COUNT_reg_n_0_[0] ),
.I2(\COUNT_reg_n_0_[6] ),
.I3(\COUNT[7]_i_3_n_0 ),
.I4(\COUNT_reg_n_0_[5] ),
.I5(\COUNT_reg_n_0_[4] ),
.O(\COUNT[6]_i_1_n_0 ));
LUT6 #(
.INIT(64'h0000000000000001))
\COUNT[7]_i_1
(.I0(\TIMER_reg_n_0_[9] ),
.I1(\TIMER_reg_n_0_[7] ),
.I2(\TIMER_reg_n_0_[5] ),
.I3(\TIMER_reg_n_0_[6] ),
.I4(\TIMER_reg_n_0_[8] ),
.I5(\TIMER[9]_i_2_n_0 ),
.O(\COUNT[7]_i_1_n_0 ));
LUT6 #(
.INIT(64'hF7FFF7FF08000000))
\COUNT[7]_i_2
(.I0(\COUNT_reg_n_0_[4] ),
.I1(\COUNT_reg_n_0_[5] ),
.I2(\COUNT[7]_i_3_n_0 ),
.I3(\COUNT_reg_n_0_[6] ),
.I4(\COUNT_reg_n_0_[0] ),
.I5(\COUNT_reg_n_0_[7] ),
.O(\COUNT[7]_i_2_n_0 ));
LUT3 #(
.INIT(8'h7F))
\COUNT[7]_i_3
(.I0(\COUNT_reg_n_0_[3] ),
.I1(\COUNT_reg_n_0_[2] ),
.I2(\COUNT_reg_n_0_[1] ),
.O(\COUNT[7]_i_3_n_0 ));
FDRE #(
.INIT(1'b0))
\COUNT_reg[0]
(.C(ETH_CLK_OBUF),
.CE(\COUNT[7]_i_1_n_0 ),
.D(\COUNT[0]_i_1__1_n_0 ),
.Q(\COUNT_reg_n_0_[0] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\COUNT_reg[1]
(.C(ETH_CLK_OBUF),
.CE(\COUNT[7]_i_1_n_0 ),
.D(\COUNT[1]_i_1__1_n_0 ),
.Q(\COUNT_reg_n_0_[1] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\COUNT_reg[2]
(.C(ETH_CLK_OBUF),
.CE(\COUNT[7]_i_1_n_0 ),
.D(\COUNT[2]_i_1__0_n_0 ),
.Q(\COUNT_reg_n_0_[2] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\COUNT_reg[3]
(.C(ETH_CLK_OBUF),
.CE(\COUNT[7]_i_1_n_0 ),
.D(\COUNT[3]_i_1_n_0 ),
.Q(\COUNT_reg_n_0_[3] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\COUNT_reg[4]
(.C(ETH_CLK_OBUF),
.CE(\COUNT[7]_i_1_n_0 ),
.D(\COUNT[4]_i_1_n_0 ),
.Q(\COUNT_reg_n_0_[4] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\COUNT_reg[5]
(.C(ETH_CLK_OBUF),
.CE(\COUNT[7]_i_1_n_0 ),
.D(\COUNT[5]_i_1_n_0 ),
.Q(\COUNT_reg_n_0_[5] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\COUNT_reg[6]
(.C(ETH_CLK_OBUF),
.CE(\COUNT[7]_i_1_n_0 ),
.D(\COUNT[6]_i_1_n_0 ),
.Q(\COUNT_reg_n_0_[6] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\COUNT_reg[7]
(.C(ETH_CLK_OBUF),
.CE(\COUNT[7]_i_1_n_0 ),
.D(\COUNT[7]_i_2_n_0 ),
.Q(\COUNT_reg_n_0_[7] ),
.R(1'b0));
LUT1 #(
.INIT(2'h1))
OUT_BIT_i_1
(.I0(p_0_in),
.O(OUT_BIT_i_1_n_0));
LUT2 #(
.INIT(4'h1))
OUT_BIT_i_10
(.I0(\COUNT_reg_n_0_[0] ),
.I1(\COUNT_reg_n_0_[1] ),
.O(OUT_BIT_i_10_n_0));
LUT2 #(
.INIT(4'hE))
OUT_BIT_i_3
(.I0(\COUNT_reg_n_0_[6] ),
.I1(\COUNT_reg_n_0_[7] ),
.O(OUT_BIT_i_3_n_0));
LUT2 #(
.INIT(4'hE))
OUT_BIT_i_4
(.I0(\COUNT_reg_n_0_[4] ),
.I1(\COUNT_reg_n_0_[5] ),
.O(OUT_BIT_i_4_n_0));
LUT2 #(
.INIT(4'hE))
OUT_BIT_i_5
(.I0(\COUNT_reg_n_0_[2] ),
.I1(\COUNT_reg_n_0_[3] ),
.O(OUT_BIT_i_5_n_0));
LUT2 #(
.INIT(4'hE))
OUT_BIT_i_6
(.I0(\COUNT_reg_n_0_[0] ),
.I1(\COUNT_reg_n_0_[1] ),
.O(OUT_BIT_i_6_n_0));
LUT2 #(
.INIT(4'h1))
OUT_BIT_i_7
(.I0(\COUNT_reg_n_0_[6] ),
.I1(\COUNT_reg_n_0_[7] ),
.O(OUT_BIT_i_7_n_0));
LUT2 #(
.INIT(4'h1))
OUT_BIT_i_8
(.I0(\COUNT_reg_n_0_[4] ),
.I1(\COUNT_reg_n_0_[5] ),
.O(OUT_BIT_i_8_n_0));
LUT2 #(
.INIT(4'h1))
OUT_BIT_i_9
(.I0(\COUNT_reg_n_0_[2] ),
.I1(\COUNT_reg_n_0_[3] ),
.O(OUT_BIT_i_9_n_0));
FDRE OUT_BIT_reg
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(OUT_BIT_i_1_n_0),
.Q(LED_R_PWM_OBUF),
.R(1'b0));
CARRY4 OUT_BIT_reg_i_2
(.CI(1'b0),
.CO({p_0_in,NLW_OUT_BIT_reg_i_2_CO_UNCONNECTED[2:0]}),
.CYINIT(1'b1),
.DI({OUT_BIT_i_3_n_0,OUT_BIT_i_4_n_0,OUT_BIT_i_5_n_0,OUT_BIT_i_6_n_0}),
.O(NLW_OUT_BIT_reg_i_2_O_UNCONNECTED[3:0]),
.S({OUT_BIT_i_7_n_0,OUT_BIT_i_8_n_0,OUT_BIT_i_9_n_0,OUT_BIT_i_10_n_0}));
(* SOFT_HLUTNM = "soft_lutpair37" *)
LUT1 #(
.INIT(2'h1))
\TIMER[0]_i_1__0
(.I0(\TIMER_reg_n_0_[0] ),
.O(TIMER[0]));
(* SOFT_HLUTNM = "soft_lutpair37" *)
LUT2 #(
.INIT(4'h9))
\TIMER[1]_i_1
(.I0(\TIMER_reg_n_0_[1] ),
.I1(\TIMER_reg_n_0_[0] ),
.O(TIMER[1]));
LUT3 #(
.INIT(8'hA9))
\TIMER[2]_i_1__0
(.I0(\TIMER_reg_n_0_[2] ),
.I1(\TIMER_reg_n_0_[0] ),
.I2(\TIMER_reg_n_0_[1] ),
.O(TIMER[2]));
LUT6 #(
.INIT(64'hF0F0F0F0F0F0F00E))
\TIMER[3]_i_1
(.I0(\TIMER[4]_i_2_n_0 ),
.I1(\TIMER_reg_n_0_[4] ),
.I2(\TIMER_reg_n_0_[3] ),
.I3(\TIMER_reg_n_0_[1] ),
.I4(\TIMER_reg_n_0_[0] ),
.I5(\TIMER_reg_n_0_[2] ),
.O(TIMER[3]));
LUT6 #(
.INIT(64'hFFFE0001FFFE0000))
\TIMER[4]_i_1
(.I0(\TIMER_reg_n_0_[3] ),
.I1(\TIMER_reg_n_0_[1] ),
.I2(\TIMER_reg_n_0_[0] ),
.I3(\TIMER_reg_n_0_[2] ),
.I4(\TIMER_reg_n_0_[4] ),
.I5(\TIMER[4]_i_2_n_0 ),
.O(TIMER[4]));
LUT5 #(
.INIT(32'hFFFFFFFE))
\TIMER[4]_i_2
(.I0(\TIMER_reg_n_0_[8] ),
.I1(\TIMER_reg_n_0_[6] ),
.I2(\TIMER_reg_n_0_[5] ),
.I3(\TIMER_reg_n_0_[7] ),
.I4(\TIMER_reg_n_0_[9] ),
.O(\TIMER[4]_i_2_n_0 ));
LUT6 #(
.INIT(64'hAAAAAAAAAAAAAAA9))
\TIMER[5]_i_1
(.I0(\TIMER_reg_n_0_[5] ),
.I1(\TIMER_reg_n_0_[3] ),
.I2(\TIMER_reg_n_0_[1] ),
.I3(\TIMER_reg_n_0_[0] ),
.I4(\TIMER_reg_n_0_[2] ),
.I5(\TIMER_reg_n_0_[4] ),
.O(TIMER[5]));
LUT3 #(
.INIT(8'hE1))
\TIMER[6]_i_1__0
(.I0(\TIMER[9]_i_2_n_0 ),
.I1(\TIMER_reg_n_0_[5] ),
.I2(\TIMER_reg_n_0_[6] ),
.O(TIMER[6]));
(* SOFT_HLUTNM = "soft_lutpair34" *)
LUT4 #(
.INIT(16'hFE01))
\TIMER[7]_i_1__0
(.I0(\TIMER[9]_i_2_n_0 ),
.I1(\TIMER_reg_n_0_[6] ),
.I2(\TIMER_reg_n_0_[5] ),
.I3(\TIMER_reg_n_0_[7] ),
.O(TIMER[7]));
(* SOFT_HLUTNM = "soft_lutpair34" *)
LUT5 #(
.INIT(32'hFFFE0001))
\TIMER[8]_i_1__0
(.I0(\TIMER[9]_i_2_n_0 ),
.I1(\TIMER_reg_n_0_[7] ),
.I2(\TIMER_reg_n_0_[5] ),
.I3(\TIMER_reg_n_0_[6] ),
.I4(\TIMER_reg_n_0_[8] ),
.O(TIMER[8]));
LUT6 #(
.INIT(64'hFFFFFFFE00000001))
\TIMER[9]_i_1
(.I0(\TIMER[9]_i_2_n_0 ),
.I1(\TIMER_reg_n_0_[8] ),
.I2(\TIMER_reg_n_0_[6] ),
.I3(\TIMER_reg_n_0_[5] ),
.I4(\TIMER_reg_n_0_[7] ),
.I5(\TIMER_reg_n_0_[9] ),
.O(TIMER[9]));
LUT5 #(
.INIT(32'hFFFFFFFE))
\TIMER[9]_i_2
(.I0(\TIMER_reg_n_0_[3] ),
.I1(\TIMER_reg_n_0_[1] ),
.I2(\TIMER_reg_n_0_[0] ),
.I3(\TIMER_reg_n_0_[2] ),
.I4(\TIMER_reg_n_0_[4] ),
.O(\TIMER[9]_i_2_n_0 ));
FDRE #(
.INIT(1'b1))
\TIMER_reg[0]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(TIMER[0]),
.Q(\TIMER_reg_n_0_[0] ),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\TIMER_reg[1]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(TIMER[1]),
.Q(\TIMER_reg_n_0_[1] ),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\TIMER_reg[2]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(TIMER[2]),
.Q(\TIMER_reg_n_0_[2] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\TIMER_reg[3]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(TIMER[3]),
.Q(\TIMER_reg_n_0_[3] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\TIMER_reg[4]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(TIMER[4]),
.Q(\TIMER_reg_n_0_[4] ),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\TIMER_reg[5]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(TIMER[5]),
.Q(\TIMER_reg_n_0_[5] ),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\TIMER_reg[6]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(TIMER[6]),
.Q(\TIMER_reg_n_0_[6] ),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\TIMER_reg[7]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(TIMER[7]),
.Q(\TIMER_reg_n_0_[7] ),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\TIMER_reg[8]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(TIMER[8]),
.Q(\TIMER_reg_n_0_[8] ),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\TIMER_reg[9]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(TIMER[9]),
.Q(\TIMER_reg_n_0_[9] ),
.R(1'b0));
endmodule
|
module PWM_0
(LED_G_PWM_OBUF,
ETH_CLK_OBUF);
output LED_G_PWM_OBUF;
input ETH_CLK_OBUF;
wire \COUNT[0]_i_1__2_n_0 ;
wire \COUNT[1]_i_1__2_n_0 ;
wire \COUNT[1]_i_2__0_n_0 ;
wire \COUNT[2]_i_1__1_n_0 ;
wire \COUNT[3]_i_1__0_n_0 ;
wire \COUNT[3]_i_2__0_n_0 ;
wire \COUNT[4]_i_1__0_n_0 ;
wire \COUNT[5]_i_1__0_n_0 ;
wire \COUNT[6]_i_1__0_n_0 ;
wire \COUNT[7]_i_1__0_n_0 ;
wire \COUNT[7]_i_2__0_n_0 ;
wire \COUNT[7]_i_3__0_n_0 ;
wire \COUNT_reg_n_0_[0] ;
wire \COUNT_reg_n_0_[1] ;
wire \COUNT_reg_n_0_[2] ;
wire \COUNT_reg_n_0_[3] ;
wire \COUNT_reg_n_0_[4] ;
wire \COUNT_reg_n_0_[5] ;
wire \COUNT_reg_n_0_[6] ;
wire \COUNT_reg_n_0_[7] ;
wire ETH_CLK_OBUF;
wire LED_G_PWM_OBUF;
wire OUT_BIT_i_10__0_n_0;
wire OUT_BIT_i_1__0_n_0;
wire OUT_BIT_i_3__0_n_0;
wire OUT_BIT_i_4__0_n_0;
wire OUT_BIT_i_5__0_n_0;
wire OUT_BIT_i_6__0_n_0;
wire OUT_BIT_i_7__0_n_0;
wire OUT_BIT_i_8__0_n_0;
wire OUT_BIT_i_9__0_n_0;
wire [9:0]TIMER;
wire \TIMER[4]_i_2__0_n_0 ;
wire \TIMER[9]_i_2__0_n_0 ;
wire \TIMER_reg_n_0_[0] ;
wire \TIMER_reg_n_0_[1] ;
wire \TIMER_reg_n_0_[2] ;
wire \TIMER_reg_n_0_[3] ;
wire \TIMER_reg_n_0_[4] ;
wire \TIMER_reg_n_0_[5] ;
wire \TIMER_reg_n_0_[6] ;
wire \TIMER_reg_n_0_[7] ;
wire \TIMER_reg_n_0_[8] ;
wire \TIMER_reg_n_0_[9] ;
wire p_0_in;
wire [2:0]NLW_OUT_BIT_reg_i_2__0_CO_UNCONNECTED;
wire [3:0]NLW_OUT_BIT_reg_i_2__0_O_UNCONNECTED;
LUT6 #(
.INIT(64'h2333333333333333))
\COUNT[0]_i_1__2
(.I0(\COUNT[7]_i_3__0_n_0 ),
.I1(\COUNT_reg_n_0_[0] ),
.I2(\COUNT_reg_n_0_[5] ),
.I3(\COUNT_reg_n_0_[4] ),
.I4(\COUNT_reg_n_0_[7] ),
.I5(\COUNT_reg_n_0_[6] ),
.O(\COUNT[0]_i_1__2_n_0 ));
LUT5 #(
.INIT(32'h00FFBF00))
\COUNT[1]_i_1__2
(.I0(\COUNT[1]_i_2__0_n_0 ),
.I1(\COUNT_reg_n_0_[3] ),
.I2(\COUNT_reg_n_0_[2] ),
.I3(\COUNT_reg_n_0_[1] ),
.I4(\COUNT_reg_n_0_[0] ),
.O(\COUNT[1]_i_1__2_n_0 ));
LUT4 #(
.INIT(16'h7FFF))
\COUNT[1]_i_2__0
(.I0(\COUNT_reg_n_0_[5] ),
.I1(\COUNT_reg_n_0_[4] ),
.I2(\COUNT_reg_n_0_[7] ),
.I3(\COUNT_reg_n_0_[6] ),
.O(\COUNT[1]_i_2__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair41" *)
LUT5 #(
.INIT(32'hFFC011C0))
\COUNT[2]_i_1__1
(.I0(\COUNT_reg_n_0_[3] ),
.I1(\COUNT_reg_n_0_[0] ),
.I2(\COUNT_reg_n_0_[1] ),
.I3(\COUNT_reg_n_0_[2] ),
.I4(\COUNT[3]_i_2__0_n_0 ),
.O(\COUNT[2]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair41" *)
LUT5 #(
.INIT(32'hFF805580))
\COUNT[3]_i_1__0
(.I0(\COUNT_reg_n_0_[2] ),
.I1(\COUNT_reg_n_0_[1] ),
.I2(\COUNT_reg_n_0_[0] ),
.I3(\COUNT_reg_n_0_[3] ),
.I4(\COUNT[3]_i_2__0_n_0 ),
.O(\COUNT[3]_i_1__0_n_0 ));
LUT6 #(
.INIT(64'h15555555FFFFFFFF))
\COUNT[3]_i_2__0
(.I0(\COUNT_reg_n_0_[0] ),
.I1(\COUNT_reg_n_0_[5] ),
.I2(\COUNT_reg_n_0_[4] ),
.I3(\COUNT_reg_n_0_[7] ),
.I4(\COUNT_reg_n_0_[6] ),
.I5(\COUNT_reg_n_0_[1] ),
.O(\COUNT[3]_i_2__0_n_0 ));
LUT6 #(
.INIT(64'hFF00FF7F00FF0000))
\COUNT[4]_i_1__0
(.I0(\COUNT_reg_n_0_[7] ),
.I1(\COUNT_reg_n_0_[6] ),
.I2(\COUNT_reg_n_0_[5] ),
.I3(\COUNT[7]_i_3__0_n_0 ),
.I4(\COUNT_reg_n_0_[0] ),
.I5(\COUNT_reg_n_0_[4] ),
.O(\COUNT[4]_i_1__0_n_0 ));
LUT6 #(
.INIT(64'hAABFFFFF55000000))
\COUNT[5]_i_1__0
(.I0(\COUNT[7]_i_3__0_n_0 ),
.I1(\COUNT_reg_n_0_[7] ),
.I2(\COUNT_reg_n_0_[6] ),
.I3(\COUNT_reg_n_0_[0] ),
.I4(\COUNT_reg_n_0_[4] ),
.I5(\COUNT_reg_n_0_[5] ),
.O(\COUNT[5]_i_1__0_n_0 ));
LUT6 #(
.INIT(64'hF01CF0F0F0F0F0F0))
\COUNT[6]_i_1__0
(.I0(\COUNT_reg_n_0_[7] ),
.I1(\COUNT_reg_n_0_[0] ),
.I2(\COUNT_reg_n_0_[6] ),
.I3(\COUNT[7]_i_3__0_n_0 ),
.I4(\COUNT_reg_n_0_[5] ),
.I5(\COUNT_reg_n_0_[4] ),
.O(\COUNT[6]_i_1__0_n_0 ));
LUT6 #(
.INIT(64'h0000000000000001))
\COUNT[7]_i_1__0
(.I0(\TIMER_reg_n_0_[9] ),
.I1(\TIMER_reg_n_0_[7] ),
.I2(\TIMER_reg_n_0_[5] ),
.I3(\TIMER_reg_n_0_[6] ),
.I4(\TIMER_reg_n_0_[8] ),
.I5(\TIMER[9]_i_2__0_n_0 ),
.O(\COUNT[7]_i_1__0_n_0 ));
LUT6 #(
.INIT(64'hF7FFF7FF08000000))
\COUNT[7]_i_2__0
(.I0(\COUNT_reg_n_0_[4] ),
.I1(\COUNT_reg_n_0_[5] ),
.I2(\COUNT[7]_i_3__0_n_0 ),
.I3(\COUNT_reg_n_0_[6] ),
.I4(\COUNT_reg_n_0_[0] ),
.I5(\COUNT_reg_n_0_[7] ),
.O(\COUNT[7]_i_2__0_n_0 ));
LUT3 #(
.INIT(8'h7F))
\COUNT[7]_i_3__0
(.I0(\COUNT_reg_n_0_[3] ),
.I1(\COUNT_reg_n_0_[2] ),
.I2(\COUNT_reg_n_0_[1] ),
.O(\COUNT[7]_i_3__0_n_0 ));
FDRE #(
.INIT(1'b0))
\COUNT_reg[0]
(.C(ETH_CLK_OBUF),
.CE(\COUNT[7]_i_1__0_n_0 ),
.D(\COUNT[0]_i_1__2_n_0 ),
.Q(\COUNT_reg_n_0_[0] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\COUNT_reg[1]
(.C(ETH_CLK_OBUF),
.CE(\COUNT[7]_i_1__0_n_0 ),
.D(\COUNT[1]_i_1__2_n_0 ),
.Q(\COUNT_reg_n_0_[1] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\COUNT_reg[2]
(.C(ETH_CLK_OBUF),
.CE(\COUNT[7]_i_1__0_n_0 ),
.D(\COUNT[2]_i_1__1_n_0 ),
.Q(\COUNT_reg_n_0_[2] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\COUNT_reg[3]
(.C(ETH_CLK_OBUF),
.CE(\COUNT[7]_i_1__0_n_0 ),
.D(\COUNT[3]_i_1__0_n_0 ),
.Q(\COUNT_reg_n_0_[3] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\COUNT_reg[4]
(.C(ETH_CLK_OBUF),
.CE(\COUNT[7]_i_1__0_n_0 ),
.D(\COUNT[4]_i_1__0_n_0 ),
.Q(\COUNT_reg_n_0_[4] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\COUNT_reg[5]
(.C(ETH_CLK_OBUF),
.CE(\COUNT[7]_i_1__0_n_0 ),
.D(\COUNT[5]_i_1__0_n_0 ),
.Q(\COUNT_reg_n_0_[5] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\COUNT_reg[6]
(.C(ETH_CLK_OBUF),
.CE(\COUNT[7]_i_1__0_n_0 ),
.D(\COUNT[6]_i_1__0_n_0 ),
.Q(\COUNT_reg_n_0_[6] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\COUNT_reg[7]
(.C(ETH_CLK_OBUF),
.CE(\COUNT[7]_i_1__0_n_0 ),
.D(\COUNT[7]_i_2__0_n_0 ),
.Q(\COUNT_reg_n_0_[7] ),
.R(1'b0));
LUT2 #(
.INIT(4'h1))
OUT_BIT_i_10__0
(.I0(\COUNT_reg_n_0_[0] ),
.I1(\COUNT_reg_n_0_[1] ),
.O(OUT_BIT_i_10__0_n_0));
LUT1 #(
.INIT(2'h1))
OUT_BIT_i_1__0
(.I0(p_0_in),
.O(OUT_BIT_i_1__0_n_0));
LUT2 #(
.INIT(4'hE))
OUT_BIT_i_3__0
(.I0(\COUNT_reg_n_0_[6] ),
.I1(\COUNT_reg_n_0_[7] ),
.O(OUT_BIT_i_3__0_n_0));
LUT2 #(
.INIT(4'hE))
OUT_BIT_i_4__0
(.I0(\COUNT_reg_n_0_[4] ),
.I1(\COUNT_reg_n_0_[5] ),
.O(OUT_BIT_i_4__0_n_0));
LUT2 #(
.INIT(4'hE))
OUT_BIT_i_5__0
(.I0(\COUNT_reg_n_0_[2] ),
.I1(\COUNT_reg_n_0_[3] ),
.O(OUT_BIT_i_5__0_n_0));
LUT2 #(
.INIT(4'hE))
OUT_BIT_i_6__0
(.I0(\COUNT_reg_n_0_[0] ),
.I1(\COUNT_reg_n_0_[1] ),
.O(OUT_BIT_i_6__0_n_0));
LUT2 #(
.INIT(4'h1))
OUT_BIT_i_7__0
(.I0(\COUNT_reg_n_0_[6] ),
.I1(\COUNT_reg_n_0_[7] ),
.O(OUT_BIT_i_7__0_n_0));
LUT2 #(
.INIT(4'h1))
OUT_BIT_i_8__0
(.I0(\COUNT_reg_n_0_[4] ),
.I1(\COUNT_reg_n_0_[5] ),
.O(OUT_BIT_i_8__0_n_0));
LUT2 #(
.INIT(4'h1))
OUT_BIT_i_9__0
(.I0(\COUNT_reg_n_0_[2] ),
.I1(\COUNT_reg_n_0_[3] ),
.O(OUT_BIT_i_9__0_n_0));
FDRE OUT_BIT_reg
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(OUT_BIT_i_1__0_n_0),
.Q(LED_G_PWM_OBUF),
.R(1'b0));
CARRY4 OUT_BIT_reg_i_2__0
(.CI(1'b0),
.CO({p_0_in,NLW_OUT_BIT_reg_i_2__0_CO_UNCONNECTED[2:0]}),
.CYINIT(1'b1),
.DI({OUT_BIT_i_3__0_n_0,OUT_BIT_i_4__0_n_0,OUT_BIT_i_5__0_n_0,OUT_BIT_i_6__0_n_0}),
.O(NLW_OUT_BIT_reg_i_2__0_O_UNCONNECTED[3:0]),
.S({OUT_BIT_i_7__0_n_0,OUT_BIT_i_8__0_n_0,OUT_BIT_i_9__0_n_0,OUT_BIT_i_10__0_n_0}));
(* SOFT_HLUTNM = "soft_lutpair42" *)
LUT1 #(
.INIT(2'h1))
\TIMER[0]_i_1__1
(.I0(\TIMER_reg_n_0_[0] ),
.O(TIMER[0]));
(* SOFT_HLUTNM = "soft_lutpair42" *)
LUT2 #(
.INIT(4'h9))
\TIMER[1]_i_1__0
(.I0(\TIMER_reg_n_0_[1] ),
.I1(\TIMER_reg_n_0_[0] ),
.O(TIMER[1]));
LUT3 #(
.INIT(8'hA9))
\TIMER[2]_i_1__1
(.I0(\TIMER_reg_n_0_[2] ),
.I1(\TIMER_reg_n_0_[0] ),
.I2(\TIMER_reg_n_0_[1] ),
.O(TIMER[2]));
LUT6 #(
.INIT(64'hF0F0F0F0F0F0F00E))
\TIMER[3]_i_1__0
(.I0(\TIMER[4]_i_2__0_n_0 ),
.I1(\TIMER_reg_n_0_[4] ),
.I2(\TIMER_reg_n_0_[3] ),
.I3(\TIMER_reg_n_0_[1] ),
.I4(\TIMER_reg_n_0_[0] ),
.I5(\TIMER_reg_n_0_[2] ),
.O(TIMER[3]));
LUT6 #(
.INIT(64'hFFFE0001FFFE0000))
\TIMER[4]_i_1__0
(.I0(\TIMER_reg_n_0_[3] ),
.I1(\TIMER_reg_n_0_[1] ),
.I2(\TIMER_reg_n_0_[0] ),
.I3(\TIMER_reg_n_0_[2] ),
.I4(\TIMER_reg_n_0_[4] ),
.I5(\TIMER[4]_i_2__0_n_0 ),
.O(TIMER[4]));
LUT5 #(
.INIT(32'hFFFFFFFE))
\TIMER[4]_i_2__0
(.I0(\TIMER_reg_n_0_[8] ),
.I1(\TIMER_reg_n_0_[6] ),
.I2(\TIMER_reg_n_0_[5] ),
.I3(\TIMER_reg_n_0_[7] ),
.I4(\TIMER_reg_n_0_[9] ),
.O(\TIMER[4]_i_2__0_n_0 ));
LUT6 #(
.INIT(64'hAAAAAAAAAAAAAAA9))
\TIMER[5]_i_1__0
(.I0(\TIMER_reg_n_0_[5] ),
.I1(\TIMER_reg_n_0_[3] ),
.I2(\TIMER_reg_n_0_[1] ),
.I3(\TIMER_reg_n_0_[0] ),
.I4(\TIMER_reg_n_0_[2] ),
.I5(\TIMER_reg_n_0_[4] ),
.O(TIMER[5]));
LUT3 #(
.INIT(8'hE1))
\TIMER[6]_i_1__1
(.I0(\TIMER[9]_i_2__0_n_0 ),
.I1(\TIMER_reg_n_0_[5] ),
.I2(\TIMER_reg_n_0_[6] ),
.O(TIMER[6]));
(* SOFT_HLUTNM = "soft_lutpair39" *)
LUT4 #(
.INIT(16'hFE01))
\TIMER[7]_i_1__1
(.I0(\TIMER[9]_i_2__0_n_0 ),
.I1(\TIMER_reg_n_0_[6] ),
.I2(\TIMER_reg_n_0_[5] ),
.I3(\TIMER_reg_n_0_[7] ),
.O(TIMER[7]));
(* SOFT_HLUTNM = "soft_lutpair39" *)
LUT5 #(
.INIT(32'hFFFE0001))
\TIMER[8]_i_1__1
(.I0(\TIMER[9]_i_2__0_n_0 ),
.I1(\TIMER_reg_n_0_[7] ),
.I2(\TIMER_reg_n_0_[5] ),
.I3(\TIMER_reg_n_0_[6] ),
.I4(\TIMER_reg_n_0_[8] ),
.O(TIMER[8]));
LUT6 #(
.INIT(64'hFFFFFFFE00000001))
\TIMER[9]_i_1__0
(.I0(\TIMER[9]_i_2__0_n_0 ),
.I1(\TIMER_reg_n_0_[8] ),
.I2(\TIMER_reg_n_0_[6] ),
.I3(\TIMER_reg_n_0_[5] ),
.I4(\TIMER_reg_n_0_[7] ),
.I5(\TIMER_reg_n_0_[9] ),
.O(TIMER[9]));
LUT5 #(
.INIT(32'hFFFFFFFE))
\TIMER[9]_i_2__0
(.I0(\TIMER_reg_n_0_[3] ),
.I1(\TIMER_reg_n_0_[1] ),
.I2(\TIMER_reg_n_0_[0] ),
.I3(\TIMER_reg_n_0_[2] ),
.I4(\TIMER_reg_n_0_[4] ),
.O(\TIMER[9]_i_2__0_n_0 ));
FDRE #(
.INIT(1'b1))
\TIMER_reg[0]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(TIMER[0]),
.Q(\TIMER_reg_n_0_[0] ),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\TIMER_reg[1]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(TIMER[1]),
.Q(\TIMER_reg_n_0_[1] ),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\TIMER_reg[2]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(TIMER[2]),
.Q(\TIMER_reg_n_0_[2] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\TIMER_reg[3]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(TIMER[3]),
.Q(\TIMER_reg_n_0_[3] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\TIMER_reg[4]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(TIMER[4]),
.Q(\TIMER_reg_n_0_[4] ),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\TIMER_reg[5]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(TIMER[5]),
.Q(\TIMER_reg_n_0_[5] ),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\TIMER_reg[6]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(TIMER[6]),
.Q(\TIMER_reg_n_0_[6] ),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\TIMER_reg[7]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(TIMER[7]),
.Q(\TIMER_reg_n_0_[7] ),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\TIMER_reg[8]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(TIMER[8]),
.Q(\TIMER_reg_n_0_[8] ),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\TIMER_reg[9]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(TIMER[9]),
.Q(\TIMER_reg_n_0_[9] ),
.R(1'b0));
endmodule
|
module PWM_1
(LED_B_PWM_OBUF,
ETH_CLK_OBUF);
output LED_B_PWM_OBUF;
input ETH_CLK_OBUF;
wire \COUNT[0]_i_1__3_n_0 ;
wire \COUNT[1]_i_1__3_n_0 ;
wire \COUNT[1]_i_2__1_n_0 ;
wire \COUNT[2]_i_1__2_n_0 ;
wire \COUNT[3]_i_1__1_n_0 ;
wire \COUNT[3]_i_2__1_n_0 ;
wire \COUNT[4]_i_1__1_n_0 ;
wire \COUNT[5]_i_1__1_n_0 ;
wire \COUNT[6]_i_1__1_n_0 ;
wire \COUNT[7]_i_1__1_n_0 ;
wire \COUNT[7]_i_2__1_n_0 ;
wire \COUNT[7]_i_3__1_n_0 ;
wire \COUNT_reg_n_0_[0] ;
wire \COUNT_reg_n_0_[1] ;
wire \COUNT_reg_n_0_[2] ;
wire \COUNT_reg_n_0_[3] ;
wire \COUNT_reg_n_0_[4] ;
wire \COUNT_reg_n_0_[5] ;
wire \COUNT_reg_n_0_[6] ;
wire \COUNT_reg_n_0_[7] ;
wire ETH_CLK_OBUF;
wire LED_B_PWM_OBUF;
wire OUT_BIT_i_10__1_n_0;
wire OUT_BIT_i_1__1_n_0;
wire OUT_BIT_i_3__1_n_0;
wire OUT_BIT_i_4__1_n_0;
wire OUT_BIT_i_5__1_n_0;
wire OUT_BIT_i_6__1_n_0;
wire OUT_BIT_i_7__1_n_0;
wire OUT_BIT_i_8__1_n_0;
wire OUT_BIT_i_9__1_n_0;
wire [9:0]TIMER;
wire \TIMER[4]_i_2__1_n_0 ;
wire \TIMER[9]_i_2__1_n_0 ;
wire \TIMER_reg_n_0_[0] ;
wire \TIMER_reg_n_0_[1] ;
wire \TIMER_reg_n_0_[2] ;
wire \TIMER_reg_n_0_[3] ;
wire \TIMER_reg_n_0_[4] ;
wire \TIMER_reg_n_0_[5] ;
wire \TIMER_reg_n_0_[6] ;
wire \TIMER_reg_n_0_[7] ;
wire \TIMER_reg_n_0_[8] ;
wire \TIMER_reg_n_0_[9] ;
wire p_0_in;
wire [2:0]NLW_OUT_BIT_reg_i_2__1_CO_UNCONNECTED;
wire [3:0]NLW_OUT_BIT_reg_i_2__1_O_UNCONNECTED;
LUT6 #(
.INIT(64'h2333333333333333))
\COUNT[0]_i_1__3
(.I0(\COUNT[7]_i_3__1_n_0 ),
.I1(\COUNT_reg_n_0_[0] ),
.I2(\COUNT_reg_n_0_[5] ),
.I3(\COUNT_reg_n_0_[4] ),
.I4(\COUNT_reg_n_0_[7] ),
.I5(\COUNT_reg_n_0_[6] ),
.O(\COUNT[0]_i_1__3_n_0 ));
LUT5 #(
.INIT(32'h00FFBF00))
\COUNT[1]_i_1__3
(.I0(\COUNT[1]_i_2__1_n_0 ),
.I1(\COUNT_reg_n_0_[3] ),
.I2(\COUNT_reg_n_0_[2] ),
.I3(\COUNT_reg_n_0_[1] ),
.I4(\COUNT_reg_n_0_[0] ),
.O(\COUNT[1]_i_1__3_n_0 ));
LUT4 #(
.INIT(16'h7FFF))
\COUNT[1]_i_2__1
(.I0(\COUNT_reg_n_0_[5] ),
.I1(\COUNT_reg_n_0_[4] ),
.I2(\COUNT_reg_n_0_[7] ),
.I3(\COUNT_reg_n_0_[6] ),
.O(\COUNT[1]_i_2__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair46" *)
LUT5 #(
.INIT(32'hFFC011C0))
\COUNT[2]_i_1__2
(.I0(\COUNT_reg_n_0_[3] ),
.I1(\COUNT_reg_n_0_[0] ),
.I2(\COUNT_reg_n_0_[1] ),
.I3(\COUNT_reg_n_0_[2] ),
.I4(\COUNT[3]_i_2__1_n_0 ),
.O(\COUNT[2]_i_1__2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair46" *)
LUT5 #(
.INIT(32'hFF805580))
\COUNT[3]_i_1__1
(.I0(\COUNT_reg_n_0_[2] ),
.I1(\COUNT_reg_n_0_[1] ),
.I2(\COUNT_reg_n_0_[0] ),
.I3(\COUNT_reg_n_0_[3] ),
.I4(\COUNT[3]_i_2__1_n_0 ),
.O(\COUNT[3]_i_1__1_n_0 ));
LUT6 #(
.INIT(64'h15555555FFFFFFFF))
\COUNT[3]_i_2__1
(.I0(\COUNT_reg_n_0_[0] ),
.I1(\COUNT_reg_n_0_[5] ),
.I2(\COUNT_reg_n_0_[4] ),
.I3(\COUNT_reg_n_0_[7] ),
.I4(\COUNT_reg_n_0_[6] ),
.I5(\COUNT_reg_n_0_[1] ),
.O(\COUNT[3]_i_2__1_n_0 ));
LUT6 #(
.INIT(64'hFF00FF7F00FF0000))
\COUNT[4]_i_1__1
(.I0(\COUNT_reg_n_0_[7] ),
.I1(\COUNT_reg_n_0_[6] ),
.I2(\COUNT_reg_n_0_[5] ),
.I3(\COUNT[7]_i_3__1_n_0 ),
.I4(\COUNT_reg_n_0_[0] ),
.I5(\COUNT_reg_n_0_[4] ),
.O(\COUNT[4]_i_1__1_n_0 ));
LUT6 #(
.INIT(64'hAABFFFFF55000000))
\COUNT[5]_i_1__1
(.I0(\COUNT[7]_i_3__1_n_0 ),
.I1(\COUNT_reg_n_0_[7] ),
.I2(\COUNT_reg_n_0_[6] ),
.I3(\COUNT_reg_n_0_[0] ),
.I4(\COUNT_reg_n_0_[4] ),
.I5(\COUNT_reg_n_0_[5] ),
.O(\COUNT[5]_i_1__1_n_0 ));
LUT6 #(
.INIT(64'hF01CF0F0F0F0F0F0))
\COUNT[6]_i_1__1
(.I0(\COUNT_reg_n_0_[7] ),
.I1(\COUNT_reg_n_0_[0] ),
.I2(\COUNT_reg_n_0_[6] ),
.I3(\COUNT[7]_i_3__1_n_0 ),
.I4(\COUNT_reg_n_0_[5] ),
.I5(\COUNT_reg_n_0_[4] ),
.O(\COUNT[6]_i_1__1_n_0 ));
LUT6 #(
.INIT(64'h0000000000000001))
\COUNT[7]_i_1__1
(.I0(\TIMER_reg_n_0_[9] ),
.I1(\TIMER_reg_n_0_[7] ),
.I2(\TIMER_reg_n_0_[5] ),
.I3(\TIMER_reg_n_0_[6] ),
.I4(\TIMER_reg_n_0_[8] ),
.I5(\TIMER[9]_i_2__1_n_0 ),
.O(\COUNT[7]_i_1__1_n_0 ));
LUT6 #(
.INIT(64'hF7FFF7FF08000000))
\COUNT[7]_i_2__1
(.I0(\COUNT_reg_n_0_[4] ),
.I1(\COUNT_reg_n_0_[5] ),
.I2(\COUNT[7]_i_3__1_n_0 ),
.I3(\COUNT_reg_n_0_[6] ),
.I4(\COUNT_reg_n_0_[0] ),
.I5(\COUNT_reg_n_0_[7] ),
.O(\COUNT[7]_i_2__1_n_0 ));
LUT3 #(
.INIT(8'h7F))
\COUNT[7]_i_3__1
(.I0(\COUNT_reg_n_0_[3] ),
.I1(\COUNT_reg_n_0_[2] ),
.I2(\COUNT_reg_n_0_[1] ),
.O(\COUNT[7]_i_3__1_n_0 ));
FDRE #(
.INIT(1'b0))
\COUNT_reg[0]
(.C(ETH_CLK_OBUF),
.CE(\COUNT[7]_i_1__1_n_0 ),
.D(\COUNT[0]_i_1__3_n_0 ),
.Q(\COUNT_reg_n_0_[0] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\COUNT_reg[1]
(.C(ETH_CLK_OBUF),
.CE(\COUNT[7]_i_1__1_n_0 ),
.D(\COUNT[1]_i_1__3_n_0 ),
.Q(\COUNT_reg_n_0_[1] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\COUNT_reg[2]
(.C(ETH_CLK_OBUF),
.CE(\COUNT[7]_i_1__1_n_0 ),
.D(\COUNT[2]_i_1__2_n_0 ),
.Q(\COUNT_reg_n_0_[2] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\COUNT_reg[3]
(.C(ETH_CLK_OBUF),
.CE(\COUNT[7]_i_1__1_n_0 ),
.D(\COUNT[3]_i_1__1_n_0 ),
.Q(\COUNT_reg_n_0_[3] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\COUNT_reg[4]
(.C(ETH_CLK_OBUF),
.CE(\COUNT[7]_i_1__1_n_0 ),
.D(\COUNT[4]_i_1__1_n_0 ),
.Q(\COUNT_reg_n_0_[4] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\COUNT_reg[5]
(.C(ETH_CLK_OBUF),
.CE(\COUNT[7]_i_1__1_n_0 ),
.D(\COUNT[5]_i_1__1_n_0 ),
.Q(\COUNT_reg_n_0_[5] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\COUNT_reg[6]
(.C(ETH_CLK_OBUF),
.CE(\COUNT[7]_i_1__1_n_0 ),
.D(\COUNT[6]_i_1__1_n_0 ),
.Q(\COUNT_reg_n_0_[6] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\COUNT_reg[7]
(.C(ETH_CLK_OBUF),
.CE(\COUNT[7]_i_1__1_n_0 ),
.D(\COUNT[7]_i_2__1_n_0 ),
.Q(\COUNT_reg_n_0_[7] ),
.R(1'b0));
LUT2 #(
.INIT(4'h1))
OUT_BIT_i_10__1
(.I0(\COUNT_reg_n_0_[0] ),
.I1(\COUNT_reg_n_0_[1] ),
.O(OUT_BIT_i_10__1_n_0));
LUT1 #(
.INIT(2'h1))
OUT_BIT_i_1__1
(.I0(p_0_in),
.O(OUT_BIT_i_1__1_n_0));
LUT2 #(
.INIT(4'hE))
OUT_BIT_i_3__1
(.I0(\COUNT_reg_n_0_[6] ),
.I1(\COUNT_reg_n_0_[7] ),
.O(OUT_BIT_i_3__1_n_0));
LUT2 #(
.INIT(4'hE))
OUT_BIT_i_4__1
(.I0(\COUNT_reg_n_0_[4] ),
.I1(\COUNT_reg_n_0_[5] ),
.O(OUT_BIT_i_4__1_n_0));
LUT2 #(
.INIT(4'hE))
OUT_BIT_i_5__1
(.I0(\COUNT_reg_n_0_[2] ),
.I1(\COUNT_reg_n_0_[3] ),
.O(OUT_BIT_i_5__1_n_0));
LUT2 #(
.INIT(4'hE))
OUT_BIT_i_6__1
(.I0(\COUNT_reg_n_0_[0] ),
.I1(\COUNT_reg_n_0_[1] ),
.O(OUT_BIT_i_6__1_n_0));
LUT2 #(
.INIT(4'h1))
OUT_BIT_i_7__1
(.I0(\COUNT_reg_n_0_[6] ),
.I1(\COUNT_reg_n_0_[7] ),
.O(OUT_BIT_i_7__1_n_0));
LUT2 #(
.INIT(4'h1))
OUT_BIT_i_8__1
(.I0(\COUNT_reg_n_0_[4] ),
.I1(\COUNT_reg_n_0_[5] ),
.O(OUT_BIT_i_8__1_n_0));
LUT2 #(
.INIT(4'h1))
OUT_BIT_i_9__1
(.I0(\COUNT_reg_n_0_[2] ),
.I1(\COUNT_reg_n_0_[3] ),
.O(OUT_BIT_i_9__1_n_0));
FDRE OUT_BIT_reg
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(OUT_BIT_i_1__1_n_0),
.Q(LED_B_PWM_OBUF),
.R(1'b0));
CARRY4 OUT_BIT_reg_i_2__1
(.CI(1'b0),
.CO({p_0_in,NLW_OUT_BIT_reg_i_2__1_CO_UNCONNECTED[2:0]}),
.CYINIT(1'b1),
.DI({OUT_BIT_i_3__1_n_0,OUT_BIT_i_4__1_n_0,OUT_BIT_i_5__1_n_0,OUT_BIT_i_6__1_n_0}),
.O(NLW_OUT_BIT_reg_i_2__1_O_UNCONNECTED[3:0]),
.S({OUT_BIT_i_7__1_n_0,OUT_BIT_i_8__1_n_0,OUT_BIT_i_9__1_n_0,OUT_BIT_i_10__1_n_0}));
(* SOFT_HLUTNM = "soft_lutpair47" *)
LUT1 #(
.INIT(2'h1))
\TIMER[0]_i_1__2
(.I0(\TIMER_reg_n_0_[0] ),
.O(TIMER[0]));
(* SOFT_HLUTNM = "soft_lutpair47" *)
LUT2 #(
.INIT(4'h9))
\TIMER[1]_i_1__1
(.I0(\TIMER_reg_n_0_[1] ),
.I1(\TIMER_reg_n_0_[0] ),
.O(TIMER[1]));
LUT3 #(
.INIT(8'hA9))
\TIMER[2]_i_1__2
(.I0(\TIMER_reg_n_0_[2] ),
.I1(\TIMER_reg_n_0_[0] ),
.I2(\TIMER_reg_n_0_[1] ),
.O(TIMER[2]));
LUT6 #(
.INIT(64'hF0F0F0F0F0F0F00E))
\TIMER[3]_i_1__1
(.I0(\TIMER[4]_i_2__1_n_0 ),
.I1(\TIMER_reg_n_0_[4] ),
.I2(\TIMER_reg_n_0_[3] ),
.I3(\TIMER_reg_n_0_[1] ),
.I4(\TIMER_reg_n_0_[0] ),
.I5(\TIMER_reg_n_0_[2] ),
.O(TIMER[3]));
LUT6 #(
.INIT(64'hFFFE0001FFFE0000))
\TIMER[4]_i_1__1
(.I0(\TIMER_reg_n_0_[3] ),
.I1(\TIMER_reg_n_0_[1] ),
.I2(\TIMER_reg_n_0_[0] ),
.I3(\TIMER_reg_n_0_[2] ),
.I4(\TIMER_reg_n_0_[4] ),
.I5(\TIMER[4]_i_2__1_n_0 ),
.O(TIMER[4]));
LUT5 #(
.INIT(32'hFFFFFFFE))
\TIMER[4]_i_2__1
(.I0(\TIMER_reg_n_0_[8] ),
.I1(\TIMER_reg_n_0_[6] ),
.I2(\TIMER_reg_n_0_[5] ),
.I3(\TIMER_reg_n_0_[7] ),
.I4(\TIMER_reg_n_0_[9] ),
.O(\TIMER[4]_i_2__1_n_0 ));
LUT6 #(
.INIT(64'hAAAAAAAAAAAAAAA9))
\TIMER[5]_i_1__1
(.I0(\TIMER_reg_n_0_[5] ),
.I1(\TIMER_reg_n_0_[3] ),
.I2(\TIMER_reg_n_0_[1] ),
.I3(\TIMER_reg_n_0_[0] ),
.I4(\TIMER_reg_n_0_[2] ),
.I5(\TIMER_reg_n_0_[4] ),
.O(TIMER[5]));
LUT3 #(
.INIT(8'hE1))
\TIMER[6]_i_1__2
(.I0(\TIMER[9]_i_2__1_n_0 ),
.I1(\TIMER_reg_n_0_[5] ),
.I2(\TIMER_reg_n_0_[6] ),
.O(TIMER[6]));
(* SOFT_HLUTNM = "soft_lutpair44" *)
LUT4 #(
.INIT(16'hFE01))
\TIMER[7]_i_1__2
(.I0(\TIMER[9]_i_2__1_n_0 ),
.I1(\TIMER_reg_n_0_[6] ),
.I2(\TIMER_reg_n_0_[5] ),
.I3(\TIMER_reg_n_0_[7] ),
.O(TIMER[7]));
(* SOFT_HLUTNM = "soft_lutpair44" *)
LUT5 #(
.INIT(32'hFFFE0001))
\TIMER[8]_i_1__2
(.I0(\TIMER[9]_i_2__1_n_0 ),
.I1(\TIMER_reg_n_0_[7] ),
.I2(\TIMER_reg_n_0_[5] ),
.I3(\TIMER_reg_n_0_[6] ),
.I4(\TIMER_reg_n_0_[8] ),
.O(TIMER[8]));
LUT6 #(
.INIT(64'hFFFFFFFE00000001))
\TIMER[9]_i_1__1
(.I0(\TIMER[9]_i_2__1_n_0 ),
.I1(\TIMER_reg_n_0_[8] ),
.I2(\TIMER_reg_n_0_[6] ),
.I3(\TIMER_reg_n_0_[5] ),
.I4(\TIMER_reg_n_0_[7] ),
.I5(\TIMER_reg_n_0_[9] ),
.O(TIMER[9]));
LUT5 #(
.INIT(32'hFFFFFFFE))
\TIMER[9]_i_2__1
(.I0(\TIMER_reg_n_0_[3] ),
.I1(\TIMER_reg_n_0_[1] ),
.I2(\TIMER_reg_n_0_[0] ),
.I3(\TIMER_reg_n_0_[2] ),
.I4(\TIMER_reg_n_0_[4] ),
.O(\TIMER[9]_i_2__1_n_0 ));
FDRE #(
.INIT(1'b1))
\TIMER_reg[0]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(TIMER[0]),
.Q(\TIMER_reg_n_0_[0] ),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\TIMER_reg[1]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(TIMER[1]),
.Q(\TIMER_reg_n_0_[1] ),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\TIMER_reg[2]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(TIMER[2]),
.Q(\TIMER_reg_n_0_[2] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\TIMER_reg[3]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(TIMER[3]),
.Q(\TIMER_reg_n_0_[3] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\TIMER_reg[4]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(TIMER[4]),
.Q(\TIMER_reg_n_0_[4] ),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\TIMER_reg[5]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(TIMER[5]),
.Q(\TIMER_reg_n_0_[5] ),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\TIMER_reg[6]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(TIMER[6]),
.Q(\TIMER_reg_n_0_[6] ),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\TIMER_reg[7]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(TIMER[7]),
.Q(\TIMER_reg_n_0_[7] ),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\TIMER_reg[8]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(TIMER[8]),
.Q(\TIMER_reg_n_0_[8] ),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\TIMER_reg[9]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(TIMER[9]),
.Q(\TIMER_reg_n_0_[9] ),
.R(1'b0));
endmodule
|
module RAM32M_UNIQ_BASE_
(DOA,
DOB,
DOC,
DOD,
ADDRA,
ADDRB,
ADDRC,
ADDRD,
DIA,
DIB,
DIC,
DID,
WCLK,
WE);
output [1:0]DOA;
output [1:0]DOB;
output [1:0]DOC;
output [1:0]DOD;
input [4:0]ADDRA;
input [4:0]ADDRB;
input [4:0]ADDRC;
input [4:0]ADDRD;
input [1:0]DIA;
input [1:0]DIB;
input [1:0]DIC;
input [1:0]DID;
input WCLK;
input WE;
wire ADDRA0;
wire ADDRA1;
wire ADDRA2;
wire ADDRA3;
wire ADDRA4;
wire ADDRB0;
wire ADDRB1;
wire ADDRB2;
wire ADDRB3;
wire ADDRB4;
wire ADDRC0;
wire ADDRC1;
wire ADDRC2;
wire ADDRC3;
wire ADDRC4;
wire ADDRD0;
wire ADDRD1;
wire ADDRD2;
wire ADDRD3;
wire ADDRD4;
wire DIA0;
wire DIA1;
wire DIB0;
wire DIB1;
wire DIC0;
wire DIC1;
wire DID0;
wire DID1;
wire DOA0;
wire DOA1;
wire DOB0;
wire DOB1;
wire DOC0;
wire DOC1;
wire DOD0;
wire DOD1;
wire WCLK;
wire WE;
assign ADDRA0 = ADDRA[0];
assign ADDRA1 = ADDRA[1];
assign ADDRA2 = ADDRA[2];
assign ADDRA3 = ADDRA[3];
assign ADDRA4 = ADDRA[4];
assign ADDRB0 = ADDRB[0];
assign ADDRB1 = ADDRB[1];
assign ADDRB2 = ADDRB[2];
assign ADDRB3 = ADDRB[3];
assign ADDRB4 = ADDRB[4];
assign ADDRC0 = ADDRC[0];
assign ADDRC1 = ADDRC[1];
assign ADDRC2 = ADDRC[2];
assign ADDRC3 = ADDRC[3];
assign ADDRC4 = ADDRC[4];
assign ADDRD0 = ADDRD[0];
assign ADDRD1 = ADDRD[1];
assign ADDRD2 = ADDRD[2];
assign ADDRD3 = ADDRD[3];
assign ADDRD4 = ADDRD[4];
assign DIA0 = DIA[0];
assign DIA1 = DIA[1];
assign DIB0 = DIB[0];
assign DIB1 = DIB[1];
assign DIC0 = DIC[0];
assign DIC1 = DIC[1];
assign DID0 = DID[0];
assign DID1 = DID[1];
assign DOA[1] = DOA1;
assign DOA[0] = DOA0;
assign DOB[1] = DOB1;
assign DOB[0] = DOB0;
assign DOC[1] = DOC1;
assign DOC[0] = DOC0;
assign DOD[1] = DOD1;
assign DOD[0] = DOD0;
RAMD32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMA
(.CLK(WCLK),
.I(DIA0),
.O(DOA0),
.RADR0(ADDRA0),
.RADR1(ADDRA1),
.RADR2(ADDRA2),
.RADR3(ADDRA3),
.RADR4(ADDRA4),
.WADR0(ADDRD0),
.WADR1(ADDRD1),
.WADR2(ADDRD2),
.WADR3(ADDRD3),
.WADR4(ADDRD4),
.WE(WE));
RAMD32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMA_D1
(.CLK(WCLK),
.I(DIA1),
.O(DOA1),
.RADR0(ADDRA0),
.RADR1(ADDRA1),
.RADR2(ADDRA2),
.RADR3(ADDRA3),
.RADR4(ADDRA4),
.WADR0(ADDRD0),
.WADR1(ADDRD1),
.WADR2(ADDRD2),
.WADR3(ADDRD3),
.WADR4(ADDRD4),
.WE(WE));
RAMD32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMB
(.CLK(WCLK),
.I(DIB0),
.O(DOB0),
.RADR0(ADDRB0),
.RADR1(ADDRB1),
.RADR2(ADDRB2),
.RADR3(ADDRB3),
.RADR4(ADDRB4),
.WADR0(ADDRD0),
.WADR1(ADDRD1),
.WADR2(ADDRD2),
.WADR3(ADDRD3),
.WADR4(ADDRD4),
.WE(WE));
RAMD32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMB_D1
(.CLK(WCLK),
.I(DIB1),
.O(DOB1),
.RADR0(ADDRB0),
.RADR1(ADDRB1),
.RADR2(ADDRB2),
.RADR3(ADDRB3),
.RADR4(ADDRB4),
.WADR0(ADDRD0),
.WADR1(ADDRD1),
.WADR2(ADDRD2),
.WADR3(ADDRD3),
.WADR4(ADDRD4),
.WE(WE));
RAMD32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMC
(.CLK(WCLK),
.I(DIC0),
.O(DOC0),
.RADR0(ADDRC0),
.RADR1(ADDRC1),
.RADR2(ADDRC2),
.RADR3(ADDRC3),
.RADR4(ADDRC4),
.WADR0(ADDRD0),
.WADR1(ADDRD1),
.WADR2(ADDRD2),
.WADR3(ADDRD3),
.WADR4(ADDRD4),
.WE(WE));
RAMD32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMC_D1
(.CLK(WCLK),
.I(DIC1),
.O(DOC1),
.RADR0(ADDRC0),
.RADR1(ADDRC1),
.RADR2(ADDRC2),
.RADR3(ADDRC3),
.RADR4(ADDRC4),
.WADR0(ADDRD0),
.WADR1(ADDRD1),
.WADR2(ADDRD2),
.WADR3(ADDRD3),
.WADR4(ADDRD4),
.WE(WE));
RAMS32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMD
(.ADR0(ADDRD0),
.ADR1(ADDRD1),
.ADR2(ADDRD2),
.ADR3(ADDRD3),
.ADR4(ADDRD4),
.CLK(WCLK),
.I(DID0),
.O(DOD0),
.WE(WE));
RAMS32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMD_D1
(.ADR0(ADDRD0),
.ADR1(ADDRD1),
.ADR2(ADDRD2),
.ADR3(ADDRD3),
.ADR4(ADDRD4),
.CLK(WCLK),
.I(DID1),
.O(DOD1),
.WE(WE));
endmodule
|
module RAM32M_HD10
(DOA,
DOB,
DOC,
DOD,
ADDRA,
ADDRB,
ADDRC,
ADDRD,
DIA,
DIB,
DIC,
DID,
WCLK,
WE);
output [1:0]DOA;
output [1:0]DOB;
output [1:0]DOC;
output [1:0]DOD;
input [4:0]ADDRA;
input [4:0]ADDRB;
input [4:0]ADDRC;
input [4:0]ADDRD;
input [1:0]DIA;
input [1:0]DIB;
input [1:0]DIC;
input [1:0]DID;
input WCLK;
input WE;
wire ADDRA0;
wire ADDRA1;
wire ADDRA2;
wire ADDRA3;
wire ADDRA4;
wire ADDRB0;
wire ADDRB1;
wire ADDRB2;
wire ADDRB3;
wire ADDRB4;
wire ADDRC0;
wire ADDRC1;
wire ADDRC2;
wire ADDRC3;
wire ADDRC4;
wire ADDRD0;
wire ADDRD1;
wire ADDRD2;
wire ADDRD3;
wire ADDRD4;
wire DIA0;
wire DIA1;
wire DIB0;
wire DIB1;
wire DIC0;
wire DIC1;
wire DID0;
wire DID1;
wire DOA0;
wire DOA1;
wire DOB0;
wire DOB1;
wire DOC0;
wire DOC1;
wire DOD0;
wire DOD1;
wire WCLK;
wire WE;
assign ADDRA0 = ADDRA[0];
assign ADDRA1 = ADDRA[1];
assign ADDRA2 = ADDRA[2];
assign ADDRA3 = ADDRA[3];
assign ADDRA4 = ADDRA[4];
assign ADDRB0 = ADDRB[0];
assign ADDRB1 = ADDRB[1];
assign ADDRB2 = ADDRB[2];
assign ADDRB3 = ADDRB[3];
assign ADDRB4 = ADDRB[4];
assign ADDRC0 = ADDRC[0];
assign ADDRC1 = ADDRC[1];
assign ADDRC2 = ADDRC[2];
assign ADDRC3 = ADDRC[3];
assign ADDRC4 = ADDRC[4];
assign ADDRD0 = ADDRD[0];
assign ADDRD1 = ADDRD[1];
assign ADDRD2 = ADDRD[2];
assign ADDRD3 = ADDRD[3];
assign ADDRD4 = ADDRD[4];
assign DIA0 = DIA[0];
assign DIA1 = DIA[1];
assign DIB0 = DIB[0];
assign DIB1 = DIB[1];
assign DIC0 = DIC[0];
assign DIC1 = DIC[1];
assign DID0 = DID[0];
assign DID1 = DID[1];
assign DOA[1] = DOA1;
assign DOA[0] = DOA0;
assign DOB[1] = DOB1;
assign DOB[0] = DOB0;
assign DOC[1] = DOC1;
assign DOC[0] = DOC0;
assign DOD[1] = DOD1;
assign DOD[0] = DOD0;
RAMD32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMA
(.CLK(WCLK),
.I(DIA0),
.O(DOA0),
.RADR0(ADDRA0),
.RADR1(ADDRA1),
.RADR2(ADDRA2),
.RADR3(ADDRA3),
.RADR4(ADDRA4),
.WADR0(ADDRD0),
.WADR1(ADDRD1),
.WADR2(ADDRD2),
.WADR3(ADDRD3),
.WADR4(ADDRD4),
.WE(WE));
RAMD32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMA_D1
(.CLK(WCLK),
.I(DIA1),
.O(DOA1),
.RADR0(ADDRA0),
.RADR1(ADDRA1),
.RADR2(ADDRA2),
.RADR3(ADDRA3),
.RADR4(ADDRA4),
.WADR0(ADDRD0),
.WADR1(ADDRD1),
.WADR2(ADDRD2),
.WADR3(ADDRD3),
.WADR4(ADDRD4),
.WE(WE));
RAMD32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMB
(.CLK(WCLK),
.I(DIB0),
.O(DOB0),
.RADR0(ADDRB0),
.RADR1(ADDRB1),
.RADR2(ADDRB2),
.RADR3(ADDRB3),
.RADR4(ADDRB4),
.WADR0(ADDRD0),
.WADR1(ADDRD1),
.WADR2(ADDRD2),
.WADR3(ADDRD3),
.WADR4(ADDRD4),
.WE(WE));
RAMD32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMB_D1
(.CLK(WCLK),
.I(DIB1),
.O(DOB1),
.RADR0(ADDRB0),
.RADR1(ADDRB1),
.RADR2(ADDRB2),
.RADR3(ADDRB3),
.RADR4(ADDRB4),
.WADR0(ADDRD0),
.WADR1(ADDRD1),
.WADR2(ADDRD2),
.WADR3(ADDRD3),
.WADR4(ADDRD4),
.WE(WE));
RAMD32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMC
(.CLK(WCLK),
.I(DIC0),
.O(DOC0),
.RADR0(ADDRC0),
.RADR1(ADDRC1),
.RADR2(ADDRC2),
.RADR3(ADDRC3),
.RADR4(ADDRC4),
.WADR0(ADDRD0),
.WADR1(ADDRD1),
.WADR2(ADDRD2),
.WADR3(ADDRD3),
.WADR4(ADDRD4),
.WE(WE));
RAMD32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMC_D1
(.CLK(WCLK),
.I(DIC1),
.O(DOC1),
.RADR0(ADDRC0),
.RADR1(ADDRC1),
.RADR2(ADDRC2),
.RADR3(ADDRC3),
.RADR4(ADDRC4),
.WADR0(ADDRD0),
.WADR1(ADDRD1),
.WADR2(ADDRD2),
.WADR3(ADDRD3),
.WADR4(ADDRD4),
.WE(WE));
RAMS32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMD
(.ADR0(ADDRD0),
.ADR1(ADDRD1),
.ADR2(ADDRD2),
.ADR3(ADDRD3),
.ADR4(ADDRD4),
.CLK(WCLK),
.I(DID0),
.O(DOD0),
.WE(WE));
RAMS32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMD_D1
(.ADR0(ADDRD0),
.ADR1(ADDRD1),
.ADR2(ADDRD2),
.ADR3(ADDRD3),
.ADR4(ADDRD4),
.CLK(WCLK),
.I(DID1),
.O(DOD1),
.WE(WE));
endmodule
|
module RAM32M_HD11
(DOA,
DOB,
DOC,
DOD,
ADDRA,
ADDRB,
ADDRC,
ADDRD,
DIA,
DIB,
DIC,
DID,
WCLK,
WE);
output [1:0]DOA;
output [1:0]DOB;
output [1:0]DOC;
output [1:0]DOD;
input [4:0]ADDRA;
input [4:0]ADDRB;
input [4:0]ADDRC;
input [4:0]ADDRD;
input [1:0]DIA;
input [1:0]DIB;
input [1:0]DIC;
input [1:0]DID;
input WCLK;
input WE;
wire ADDRA0;
wire ADDRA1;
wire ADDRA2;
wire ADDRA3;
wire ADDRA4;
wire ADDRB0;
wire ADDRB1;
wire ADDRB2;
wire ADDRB3;
wire ADDRB4;
wire ADDRC0;
wire ADDRC1;
wire ADDRC2;
wire ADDRC3;
wire ADDRC4;
wire ADDRD0;
wire ADDRD1;
wire ADDRD2;
wire ADDRD3;
wire ADDRD4;
wire DIA0;
wire DIA1;
wire DIB0;
wire DIB1;
wire DIC0;
wire DIC1;
wire DID0;
wire DID1;
wire DOA0;
wire DOA1;
wire DOB0;
wire DOB1;
wire DOC0;
wire DOC1;
wire DOD0;
wire DOD1;
wire WCLK;
wire WE;
assign ADDRA0 = ADDRA[0];
assign ADDRA1 = ADDRA[1];
assign ADDRA2 = ADDRA[2];
assign ADDRA3 = ADDRA[3];
assign ADDRA4 = ADDRA[4];
assign ADDRB0 = ADDRB[0];
assign ADDRB1 = ADDRB[1];
assign ADDRB2 = ADDRB[2];
assign ADDRB3 = ADDRB[3];
assign ADDRB4 = ADDRB[4];
assign ADDRC0 = ADDRC[0];
assign ADDRC1 = ADDRC[1];
assign ADDRC2 = ADDRC[2];
assign ADDRC3 = ADDRC[3];
assign ADDRC4 = ADDRC[4];
assign ADDRD0 = ADDRD[0];
assign ADDRD1 = ADDRD[1];
assign ADDRD2 = ADDRD[2];
assign ADDRD3 = ADDRD[3];
assign ADDRD4 = ADDRD[4];
assign DIA0 = DIA[0];
assign DIA1 = DIA[1];
assign DIB0 = DIB[0];
assign DIB1 = DIB[1];
assign DIC0 = DIC[0];
assign DIC1 = DIC[1];
assign DID0 = DID[0];
assign DID1 = DID[1];
assign DOA[1] = DOA1;
assign DOA[0] = DOA0;
assign DOB[1] = DOB1;
assign DOB[0] = DOB0;
assign DOC[1] = DOC1;
assign DOC[0] = DOC0;
assign DOD[1] = DOD1;
assign DOD[0] = DOD0;
RAMD32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMA
(.CLK(WCLK),
.I(DIA0),
.O(DOA0),
.RADR0(ADDRA0),
.RADR1(ADDRA1),
.RADR2(ADDRA2),
.RADR3(ADDRA3),
.RADR4(ADDRA4),
.WADR0(ADDRD0),
.WADR1(ADDRD1),
.WADR2(ADDRD2),
.WADR3(ADDRD3),
.WADR4(ADDRD4),
.WE(WE));
RAMD32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMA_D1
(.CLK(WCLK),
.I(DIA1),
.O(DOA1),
.RADR0(ADDRA0),
.RADR1(ADDRA1),
.RADR2(ADDRA2),
.RADR3(ADDRA3),
.RADR4(ADDRA4),
.WADR0(ADDRD0),
.WADR1(ADDRD1),
.WADR2(ADDRD2),
.WADR3(ADDRD3),
.WADR4(ADDRD4),
.WE(WE));
RAMD32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMB
(.CLK(WCLK),
.I(DIB0),
.O(DOB0),
.RADR0(ADDRB0),
.RADR1(ADDRB1),
.RADR2(ADDRB2),
.RADR3(ADDRB3),
.RADR4(ADDRB4),
.WADR0(ADDRD0),
.WADR1(ADDRD1),
.WADR2(ADDRD2),
.WADR3(ADDRD3),
.WADR4(ADDRD4),
.WE(WE));
RAMD32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMB_D1
(.CLK(WCLK),
.I(DIB1),
.O(DOB1),
.RADR0(ADDRB0),
.RADR1(ADDRB1),
.RADR2(ADDRB2),
.RADR3(ADDRB3),
.RADR4(ADDRB4),
.WADR0(ADDRD0),
.WADR1(ADDRD1),
.WADR2(ADDRD2),
.WADR3(ADDRD3),
.WADR4(ADDRD4),
.WE(WE));
RAMD32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMC
(.CLK(WCLK),
.I(DIC0),
.O(DOC0),
.RADR0(ADDRC0),
.RADR1(ADDRC1),
.RADR2(ADDRC2),
.RADR3(ADDRC3),
.RADR4(ADDRC4),
.WADR0(ADDRD0),
.WADR1(ADDRD1),
.WADR2(ADDRD2),
.WADR3(ADDRD3),
.WADR4(ADDRD4),
.WE(WE));
RAMD32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMC_D1
(.CLK(WCLK),
.I(DIC1),
.O(DOC1),
.RADR0(ADDRC0),
.RADR1(ADDRC1),
.RADR2(ADDRC2),
.RADR3(ADDRC3),
.RADR4(ADDRC4),
.WADR0(ADDRD0),
.WADR1(ADDRD1),
.WADR2(ADDRD2),
.WADR3(ADDRD3),
.WADR4(ADDRD4),
.WE(WE));
RAMS32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMD
(.ADR0(ADDRD0),
.ADR1(ADDRD1),
.ADR2(ADDRD2),
.ADR3(ADDRD3),
.ADR4(ADDRD4),
.CLK(WCLK),
.I(DID0),
.O(DOD0),
.WE(WE));
RAMS32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMD_D1
(.ADR0(ADDRD0),
.ADR1(ADDRD1),
.ADR2(ADDRD2),
.ADR3(ADDRD3),
.ADR4(ADDRD4),
.CLK(WCLK),
.I(DID1),
.O(DOD1),
.WE(WE));
endmodule
|
module RAM32M_HD12
(DOA,
DOB,
DOC,
DOD,
ADDRA,
ADDRB,
ADDRC,
ADDRD,
DIA,
DIB,
DIC,
DID,
WCLK,
WE);
output [1:0]DOA;
output [1:0]DOB;
output [1:0]DOC;
output [1:0]DOD;
input [4:0]ADDRA;
input [4:0]ADDRB;
input [4:0]ADDRC;
input [4:0]ADDRD;
input [1:0]DIA;
input [1:0]DIB;
input [1:0]DIC;
input [1:0]DID;
input WCLK;
input WE;
wire ADDRA0;
wire ADDRA1;
wire ADDRA2;
wire ADDRA3;
wire ADDRA4;
wire ADDRB0;
wire ADDRB1;
wire ADDRB2;
wire ADDRB3;
wire ADDRB4;
wire ADDRC0;
wire ADDRC1;
wire ADDRC2;
wire ADDRC3;
wire ADDRC4;
wire ADDRD0;
wire ADDRD1;
wire ADDRD2;
wire ADDRD3;
wire ADDRD4;
wire DIA0;
wire DIA1;
wire DIB0;
wire DIB1;
wire DIC0;
wire DIC1;
wire DID0;
wire DID1;
wire DOA0;
wire DOA1;
wire DOB0;
wire DOB1;
wire DOC0;
wire DOC1;
wire DOD0;
wire DOD1;
wire WCLK;
wire WE;
assign ADDRA0 = ADDRA[0];
assign ADDRA1 = ADDRA[1];
assign ADDRA2 = ADDRA[2];
assign ADDRA3 = ADDRA[3];
assign ADDRA4 = ADDRA[4];
assign ADDRB0 = ADDRB[0];
assign ADDRB1 = ADDRB[1];
assign ADDRB2 = ADDRB[2];
assign ADDRB3 = ADDRB[3];
assign ADDRB4 = ADDRB[4];
assign ADDRC0 = ADDRC[0];
assign ADDRC1 = ADDRC[1];
assign ADDRC2 = ADDRC[2];
assign ADDRC3 = ADDRC[3];
assign ADDRC4 = ADDRC[4];
assign ADDRD0 = ADDRD[0];
assign ADDRD1 = ADDRD[1];
assign ADDRD2 = ADDRD[2];
assign ADDRD3 = ADDRD[3];
assign ADDRD4 = ADDRD[4];
assign DIA0 = DIA[0];
assign DIA1 = DIA[1];
assign DIB0 = DIB[0];
assign DIB1 = DIB[1];
assign DIC0 = DIC[0];
assign DIC1 = DIC[1];
assign DID0 = DID[0];
assign DID1 = DID[1];
assign DOA[1] = DOA1;
assign DOA[0] = DOA0;
assign DOB[1] = DOB1;
assign DOB[0] = DOB0;
assign DOC[1] = DOC1;
assign DOC[0] = DOC0;
assign DOD[1] = DOD1;
assign DOD[0] = DOD0;
RAMD32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMA
(.CLK(WCLK),
.I(DIA0),
.O(DOA0),
.RADR0(ADDRA0),
.RADR1(ADDRA1),
.RADR2(ADDRA2),
.RADR3(ADDRA3),
.RADR4(ADDRA4),
.WADR0(ADDRD0),
.WADR1(ADDRD1),
.WADR2(ADDRD2),
.WADR3(ADDRD3),
.WADR4(ADDRD4),
.WE(WE));
RAMD32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMA_D1
(.CLK(WCLK),
.I(DIA1),
.O(DOA1),
.RADR0(ADDRA0),
.RADR1(ADDRA1),
.RADR2(ADDRA2),
.RADR3(ADDRA3),
.RADR4(ADDRA4),
.WADR0(ADDRD0),
.WADR1(ADDRD1),
.WADR2(ADDRD2),
.WADR3(ADDRD3),
.WADR4(ADDRD4),
.WE(WE));
RAMD32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMB
(.CLK(WCLK),
.I(DIB0),
.O(DOB0),
.RADR0(ADDRB0),
.RADR1(ADDRB1),
.RADR2(ADDRB2),
.RADR3(ADDRB3),
.RADR4(ADDRB4),
.WADR0(ADDRD0),
.WADR1(ADDRD1),
.WADR2(ADDRD2),
.WADR3(ADDRD3),
.WADR4(ADDRD4),
.WE(WE));
RAMD32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMB_D1
(.CLK(WCLK),
.I(DIB1),
.O(DOB1),
.RADR0(ADDRB0),
.RADR1(ADDRB1),
.RADR2(ADDRB2),
.RADR3(ADDRB3),
.RADR4(ADDRB4),
.WADR0(ADDRD0),
.WADR1(ADDRD1),
.WADR2(ADDRD2),
.WADR3(ADDRD3),
.WADR4(ADDRD4),
.WE(WE));
RAMD32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMC
(.CLK(WCLK),
.I(DIC0),
.O(DOC0),
.RADR0(ADDRC0),
.RADR1(ADDRC1),
.RADR2(ADDRC2),
.RADR3(ADDRC3),
.RADR4(ADDRC4),
.WADR0(ADDRD0),
.WADR1(ADDRD1),
.WADR2(ADDRD2),
.WADR3(ADDRD3),
.WADR4(ADDRD4),
.WE(WE));
RAMD32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMC_D1
(.CLK(WCLK),
.I(DIC1),
.O(DOC1),
.RADR0(ADDRC0),
.RADR1(ADDRC1),
.RADR2(ADDRC2),
.RADR3(ADDRC3),
.RADR4(ADDRC4),
.WADR0(ADDRD0),
.WADR1(ADDRD1),
.WADR2(ADDRD2),
.WADR3(ADDRD3),
.WADR4(ADDRD4),
.WE(WE));
RAMS32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMD
(.ADR0(ADDRD0),
.ADR1(ADDRD1),
.ADR2(ADDRD2),
.ADR3(ADDRD3),
.ADR4(ADDRD4),
.CLK(WCLK),
.I(DID0),
.O(DOD0),
.WE(WE));
RAMS32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMD_D1
(.ADR0(ADDRD0),
.ADR1(ADDRD1),
.ADR2(ADDRD2),
.ADR3(ADDRD3),
.ADR4(ADDRD4),
.CLK(WCLK),
.I(DID1),
.O(DOD1),
.WE(WE));
endmodule
|
module RAM32M_HD13
(DOA,
DOB,
DOC,
DOD,
ADDRA,
ADDRB,
ADDRC,
ADDRD,
DIA,
DIB,
DIC,
DID,
WCLK,
WE);
output [1:0]DOA;
output [1:0]DOB;
output [1:0]DOC;
output [1:0]DOD;
input [4:0]ADDRA;
input [4:0]ADDRB;
input [4:0]ADDRC;
input [4:0]ADDRD;
input [1:0]DIA;
input [1:0]DIB;
input [1:0]DIC;
input [1:0]DID;
input WCLK;
input WE;
wire ADDRA0;
wire ADDRA1;
wire ADDRA2;
wire ADDRA3;
wire ADDRA4;
wire ADDRB0;
wire ADDRB1;
wire ADDRB2;
wire ADDRB3;
wire ADDRB4;
wire ADDRC0;
wire ADDRC1;
wire ADDRC2;
wire ADDRC3;
wire ADDRC4;
wire ADDRD0;
wire ADDRD1;
wire ADDRD2;
wire ADDRD3;
wire ADDRD4;
wire DIA0;
wire DIA1;
wire DIB0;
wire DIB1;
wire DIC0;
wire DIC1;
wire DID0;
wire DID1;
wire DOA0;
wire DOA1;
wire DOB0;
wire DOB1;
wire DOC0;
wire DOC1;
wire DOD0;
wire DOD1;
wire WCLK;
wire WE;
assign ADDRA0 = ADDRA[0];
assign ADDRA1 = ADDRA[1];
assign ADDRA2 = ADDRA[2];
assign ADDRA3 = ADDRA[3];
assign ADDRA4 = ADDRA[4];
assign ADDRB0 = ADDRB[0];
assign ADDRB1 = ADDRB[1];
assign ADDRB2 = ADDRB[2];
assign ADDRB3 = ADDRB[3];
assign ADDRB4 = ADDRB[4];
assign ADDRC0 = ADDRC[0];
assign ADDRC1 = ADDRC[1];
assign ADDRC2 = ADDRC[2];
assign ADDRC3 = ADDRC[3];
assign ADDRC4 = ADDRC[4];
assign ADDRD0 = ADDRD[0];
assign ADDRD1 = ADDRD[1];
assign ADDRD2 = ADDRD[2];
assign ADDRD3 = ADDRD[3];
assign ADDRD4 = ADDRD[4];
assign DIA0 = DIA[0];
assign DIA1 = DIA[1];
assign DIB0 = DIB[0];
assign DIB1 = DIB[1];
assign DIC0 = DIC[0];
assign DIC1 = DIC[1];
assign DID0 = DID[0];
assign DID1 = DID[1];
assign DOA[1] = DOA1;
assign DOA[0] = DOA0;
assign DOB[1] = DOB1;
assign DOB[0] = DOB0;
assign DOC[1] = DOC1;
assign DOC[0] = DOC0;
assign DOD[1] = DOD1;
assign DOD[0] = DOD0;
RAMD32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMA
(.CLK(WCLK),
.I(DIA0),
.O(DOA0),
.RADR0(ADDRA0),
.RADR1(ADDRA1),
.RADR2(ADDRA2),
.RADR3(ADDRA3),
.RADR4(ADDRA4),
.WADR0(ADDRD0),
.WADR1(ADDRD1),
.WADR2(ADDRD2),
.WADR3(ADDRD3),
.WADR4(ADDRD4),
.WE(WE));
RAMD32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMA_D1
(.CLK(WCLK),
.I(DIA1),
.O(DOA1),
.RADR0(ADDRA0),
.RADR1(ADDRA1),
.RADR2(ADDRA2),
.RADR3(ADDRA3),
.RADR4(ADDRA4),
.WADR0(ADDRD0),
.WADR1(ADDRD1),
.WADR2(ADDRD2),
.WADR3(ADDRD3),
.WADR4(ADDRD4),
.WE(WE));
RAMD32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMB
(.CLK(WCLK),
.I(DIB0),
.O(DOB0),
.RADR0(ADDRB0),
.RADR1(ADDRB1),
.RADR2(ADDRB2),
.RADR3(ADDRB3),
.RADR4(ADDRB4),
.WADR0(ADDRD0),
.WADR1(ADDRD1),
.WADR2(ADDRD2),
.WADR3(ADDRD3),
.WADR4(ADDRD4),
.WE(WE));
RAMD32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMB_D1
(.CLK(WCLK),
.I(DIB1),
.O(DOB1),
.RADR0(ADDRB0),
.RADR1(ADDRB1),
.RADR2(ADDRB2),
.RADR3(ADDRB3),
.RADR4(ADDRB4),
.WADR0(ADDRD0),
.WADR1(ADDRD1),
.WADR2(ADDRD2),
.WADR3(ADDRD3),
.WADR4(ADDRD4),
.WE(WE));
RAMD32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMC
(.CLK(WCLK),
.I(DIC0),
.O(DOC0),
.RADR0(ADDRC0),
.RADR1(ADDRC1),
.RADR2(ADDRC2),
.RADR3(ADDRC3),
.RADR4(ADDRC4),
.WADR0(ADDRD0),
.WADR1(ADDRD1),
.WADR2(ADDRD2),
.WADR3(ADDRD3),
.WADR4(ADDRD4),
.WE(WE));
RAMD32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMC_D1
(.CLK(WCLK),
.I(DIC1),
.O(DOC1),
.RADR0(ADDRC0),
.RADR1(ADDRC1),
.RADR2(ADDRC2),
.RADR3(ADDRC3),
.RADR4(ADDRC4),
.WADR0(ADDRD0),
.WADR1(ADDRD1),
.WADR2(ADDRD2),
.WADR3(ADDRD3),
.WADR4(ADDRD4),
.WE(WE));
RAMS32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMD
(.ADR0(ADDRD0),
.ADR1(ADDRD1),
.ADR2(ADDRD2),
.ADR3(ADDRD3),
.ADR4(ADDRD4),
.CLK(WCLK),
.I(DID0),
.O(DOD0),
.WE(WE));
RAMS32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMD_D1
(.ADR0(ADDRD0),
.ADR1(ADDRD1),
.ADR2(ADDRD2),
.ADR3(ADDRD3),
.ADR4(ADDRD4),
.CLK(WCLK),
.I(DID1),
.O(DOD1),
.WE(WE));
endmodule
|
module RAM32M_HD14
(DOA,
DOB,
DOC,
DOD,
ADDRA,
ADDRB,
ADDRC,
ADDRD,
DIA,
DIB,
DIC,
DID,
WCLK,
WE);
output [1:0]DOA;
output [1:0]DOB;
output [1:0]DOC;
output [1:0]DOD;
input [4:0]ADDRA;
input [4:0]ADDRB;
input [4:0]ADDRC;
input [4:0]ADDRD;
input [1:0]DIA;
input [1:0]DIB;
input [1:0]DIC;
input [1:0]DID;
input WCLK;
input WE;
wire ADDRA0;
wire ADDRA1;
wire ADDRA2;
wire ADDRA3;
wire ADDRA4;
wire ADDRB0;
wire ADDRB1;
wire ADDRB2;
wire ADDRB3;
wire ADDRB4;
wire ADDRC0;
wire ADDRC1;
wire ADDRC2;
wire ADDRC3;
wire ADDRC4;
wire ADDRD0;
wire ADDRD1;
wire ADDRD2;
wire ADDRD3;
wire ADDRD4;
wire DIA0;
wire DIA1;
wire DIB0;
wire DIB1;
wire DIC0;
wire DIC1;
wire DID0;
wire DID1;
wire DOA0;
wire DOA1;
wire DOB0;
wire DOB1;
wire DOC0;
wire DOC1;
wire DOD0;
wire DOD1;
wire WCLK;
wire WE;
assign ADDRA0 = ADDRA[0];
assign ADDRA1 = ADDRA[1];
assign ADDRA2 = ADDRA[2];
assign ADDRA3 = ADDRA[3];
assign ADDRA4 = ADDRA[4];
assign ADDRB0 = ADDRB[0];
assign ADDRB1 = ADDRB[1];
assign ADDRB2 = ADDRB[2];
assign ADDRB3 = ADDRB[3];
assign ADDRB4 = ADDRB[4];
assign ADDRC0 = ADDRC[0];
assign ADDRC1 = ADDRC[1];
assign ADDRC2 = ADDRC[2];
assign ADDRC3 = ADDRC[3];
assign ADDRC4 = ADDRC[4];
assign ADDRD0 = ADDRD[0];
assign ADDRD1 = ADDRD[1];
assign ADDRD2 = ADDRD[2];
assign ADDRD3 = ADDRD[3];
assign ADDRD4 = ADDRD[4];
assign DIA0 = DIA[0];
assign DIA1 = DIA[1];
assign DIB0 = DIB[0];
assign DIB1 = DIB[1];
assign DIC0 = DIC[0];
assign DIC1 = DIC[1];
assign DID0 = DID[0];
assign DID1 = DID[1];
assign DOA[1] = DOA1;
assign DOA[0] = DOA0;
assign DOB[1] = DOB1;
assign DOB[0] = DOB0;
assign DOC[1] = DOC1;
assign DOC[0] = DOC0;
assign DOD[1] = DOD1;
assign DOD[0] = DOD0;
RAMD32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMA
(.CLK(WCLK),
.I(DIA0),
.O(DOA0),
.RADR0(ADDRA0),
.RADR1(ADDRA1),
.RADR2(ADDRA2),
.RADR3(ADDRA3),
.RADR4(ADDRA4),
.WADR0(ADDRD0),
.WADR1(ADDRD1),
.WADR2(ADDRD2),
.WADR3(ADDRD3),
.WADR4(ADDRD4),
.WE(WE));
RAMD32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMA_D1
(.CLK(WCLK),
.I(DIA1),
.O(DOA1),
.RADR0(ADDRA0),
.RADR1(ADDRA1),
.RADR2(ADDRA2),
.RADR3(ADDRA3),
.RADR4(ADDRA4),
.WADR0(ADDRD0),
.WADR1(ADDRD1),
.WADR2(ADDRD2),
.WADR3(ADDRD3),
.WADR4(ADDRD4),
.WE(WE));
RAMD32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMB
(.CLK(WCLK),
.I(DIB0),
.O(DOB0),
.RADR0(ADDRB0),
.RADR1(ADDRB1),
.RADR2(ADDRB2),
.RADR3(ADDRB3),
.RADR4(ADDRB4),
.WADR0(ADDRD0),
.WADR1(ADDRD1),
.WADR2(ADDRD2),
.WADR3(ADDRD3),
.WADR4(ADDRD4),
.WE(WE));
RAMD32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMB_D1
(.CLK(WCLK),
.I(DIB1),
.O(DOB1),
.RADR0(ADDRB0),
.RADR1(ADDRB1),
.RADR2(ADDRB2),
.RADR3(ADDRB3),
.RADR4(ADDRB4),
.WADR0(ADDRD0),
.WADR1(ADDRD1),
.WADR2(ADDRD2),
.WADR3(ADDRD3),
.WADR4(ADDRD4),
.WE(WE));
RAMD32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMC
(.CLK(WCLK),
.I(DIC0),
.O(DOC0),
.RADR0(ADDRC0),
.RADR1(ADDRC1),
.RADR2(ADDRC2),
.RADR3(ADDRC3),
.RADR4(ADDRC4),
.WADR0(ADDRD0),
.WADR1(ADDRD1),
.WADR2(ADDRD2),
.WADR3(ADDRD3),
.WADR4(ADDRD4),
.WE(WE));
RAMD32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMC_D1
(.CLK(WCLK),
.I(DIC1),
.O(DOC1),
.RADR0(ADDRC0),
.RADR1(ADDRC1),
.RADR2(ADDRC2),
.RADR3(ADDRC3),
.RADR4(ADDRC4),
.WADR0(ADDRD0),
.WADR1(ADDRD1),
.WADR2(ADDRD2),
.WADR3(ADDRD3),
.WADR4(ADDRD4),
.WE(WE));
RAMS32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMD
(.ADR0(ADDRD0),
.ADR1(ADDRD1),
.ADR2(ADDRD2),
.ADR3(ADDRD3),
.ADR4(ADDRD4),
.CLK(WCLK),
.I(DID0),
.O(DOD0),
.WE(WE));
RAMS32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMD_D1
(.ADR0(ADDRD0),
.ADR1(ADDRD1),
.ADR2(ADDRD2),
.ADR3(ADDRD3),
.ADR4(ADDRD4),
.CLK(WCLK),
.I(DID1),
.O(DOD1),
.WE(WE));
endmodule
|
module RAM32M_HD4
(DOA,
DOB,
DOC,
DOD,
ADDRA,
ADDRB,
ADDRC,
ADDRD,
DIA,
DIB,
DIC,
DID,
WCLK,
WE);
output [1:0]DOA;
output [1:0]DOB;
output [1:0]DOC;
output [1:0]DOD;
input [4:0]ADDRA;
input [4:0]ADDRB;
input [4:0]ADDRC;
input [4:0]ADDRD;
input [1:0]DIA;
input [1:0]DIB;
input [1:0]DIC;
input [1:0]DID;
input WCLK;
input WE;
wire ADDRA0;
wire ADDRA1;
wire ADDRA2;
wire ADDRA3;
wire ADDRA4;
wire ADDRB0;
wire ADDRB1;
wire ADDRB2;
wire ADDRB3;
wire ADDRB4;
wire ADDRC0;
wire ADDRC1;
wire ADDRC2;
wire ADDRC3;
wire ADDRC4;
wire ADDRD0;
wire ADDRD1;
wire ADDRD2;
wire ADDRD3;
wire ADDRD4;
wire DIA0;
wire DIA1;
wire DIB0;
wire DIB1;
wire DIC0;
wire DIC1;
wire DID0;
wire DID1;
wire DOA0;
wire DOA1;
wire DOB0;
wire DOB1;
wire DOC0;
wire DOC1;
wire DOD0;
wire DOD1;
wire WCLK;
wire WE;
assign ADDRA0 = ADDRA[0];
assign ADDRA1 = ADDRA[1];
assign ADDRA2 = ADDRA[2];
assign ADDRA3 = ADDRA[3];
assign ADDRA4 = ADDRA[4];
assign ADDRB0 = ADDRB[0];
assign ADDRB1 = ADDRB[1];
assign ADDRB2 = ADDRB[2];
assign ADDRB3 = ADDRB[3];
assign ADDRB4 = ADDRB[4];
assign ADDRC0 = ADDRC[0];
assign ADDRC1 = ADDRC[1];
assign ADDRC2 = ADDRC[2];
assign ADDRC3 = ADDRC[3];
assign ADDRC4 = ADDRC[4];
assign ADDRD0 = ADDRD[0];
assign ADDRD1 = ADDRD[1];
assign ADDRD2 = ADDRD[2];
assign ADDRD3 = ADDRD[3];
assign ADDRD4 = ADDRD[4];
assign DIA0 = DIA[0];
assign DIA1 = DIA[1];
assign DIB0 = DIB[0];
assign DIB1 = DIB[1];
assign DIC0 = DIC[0];
assign DIC1 = DIC[1];
assign DID0 = DID[0];
assign DID1 = DID[1];
assign DOA[1] = DOA1;
assign DOA[0] = DOA0;
assign DOB[1] = DOB1;
assign DOB[0] = DOB0;
assign DOC[1] = DOC1;
assign DOC[0] = DOC0;
assign DOD[1] = DOD1;
assign DOD[0] = DOD0;
RAMD32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMA
(.CLK(WCLK),
.I(DIA0),
.O(DOA0),
.RADR0(ADDRA0),
.RADR1(ADDRA1),
.RADR2(ADDRA2),
.RADR3(ADDRA3),
.RADR4(ADDRA4),
.WADR0(ADDRD0),
.WADR1(ADDRD1),
.WADR2(ADDRD2),
.WADR3(ADDRD3),
.WADR4(ADDRD4),
.WE(WE));
RAMD32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMA_D1
(.CLK(WCLK),
.I(DIA1),
.O(DOA1),
.RADR0(ADDRA0),
.RADR1(ADDRA1),
.RADR2(ADDRA2),
.RADR3(ADDRA3),
.RADR4(ADDRA4),
.WADR0(ADDRD0),
.WADR1(ADDRD1),
.WADR2(ADDRD2),
.WADR3(ADDRD3),
.WADR4(ADDRD4),
.WE(WE));
RAMD32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMB
(.CLK(WCLK),
.I(DIB0),
.O(DOB0),
.RADR0(ADDRB0),
.RADR1(ADDRB1),
.RADR2(ADDRB2),
.RADR3(ADDRB3),
.RADR4(ADDRB4),
.WADR0(ADDRD0),
.WADR1(ADDRD1),
.WADR2(ADDRD2),
.WADR3(ADDRD3),
.WADR4(ADDRD4),
.WE(WE));
RAMD32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMB_D1
(.CLK(WCLK),
.I(DIB1),
.O(DOB1),
.RADR0(ADDRB0),
.RADR1(ADDRB1),
.RADR2(ADDRB2),
.RADR3(ADDRB3),
.RADR4(ADDRB4),
.WADR0(ADDRD0),
.WADR1(ADDRD1),
.WADR2(ADDRD2),
.WADR3(ADDRD3),
.WADR4(ADDRD4),
.WE(WE));
RAMD32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMC
(.CLK(WCLK),
.I(DIC0),
.O(DOC0),
.RADR0(ADDRC0),
.RADR1(ADDRC1),
.RADR2(ADDRC2),
.RADR3(ADDRC3),
.RADR4(ADDRC4),
.WADR0(ADDRD0),
.WADR1(ADDRD1),
.WADR2(ADDRD2),
.WADR3(ADDRD3),
.WADR4(ADDRD4),
.WE(WE));
RAMD32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMC_D1
(.CLK(WCLK),
.I(DIC1),
.O(DOC1),
.RADR0(ADDRC0),
.RADR1(ADDRC1),
.RADR2(ADDRC2),
.RADR3(ADDRC3),
.RADR4(ADDRC4),
.WADR0(ADDRD0),
.WADR1(ADDRD1),
.WADR2(ADDRD2),
.WADR3(ADDRD3),
.WADR4(ADDRD4),
.WE(WE));
RAMS32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMD
(.ADR0(ADDRD0),
.ADR1(ADDRD1),
.ADR2(ADDRD2),
.ADR3(ADDRD3),
.ADR4(ADDRD4),
.CLK(WCLK),
.I(DID0),
.O(DOD0),
.WE(WE));
RAMS32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMD_D1
(.ADR0(ADDRD0),
.ADR1(ADDRD1),
.ADR2(ADDRD2),
.ADR3(ADDRD3),
.ADR4(ADDRD4),
.CLK(WCLK),
.I(DID1),
.O(DOD1),
.WE(WE));
endmodule
|
module RAM32M_HD5
(DOA,
DOB,
DOC,
DOD,
ADDRA,
ADDRB,
ADDRC,
ADDRD,
DIA,
DIB,
DIC,
DID,
WCLK,
WE);
output [1:0]DOA;
output [1:0]DOB;
output [1:0]DOC;
output [1:0]DOD;
input [4:0]ADDRA;
input [4:0]ADDRB;
input [4:0]ADDRC;
input [4:0]ADDRD;
input [1:0]DIA;
input [1:0]DIB;
input [1:0]DIC;
input [1:0]DID;
input WCLK;
input WE;
wire ADDRA0;
wire ADDRA1;
wire ADDRA2;
wire ADDRA3;
wire ADDRA4;
wire ADDRB0;
wire ADDRB1;
wire ADDRB2;
wire ADDRB3;
wire ADDRB4;
wire ADDRC0;
wire ADDRC1;
wire ADDRC2;
wire ADDRC3;
wire ADDRC4;
wire ADDRD0;
wire ADDRD1;
wire ADDRD2;
wire ADDRD3;
wire ADDRD4;
wire DIA0;
wire DIA1;
wire DIB0;
wire DIB1;
wire DIC0;
wire DIC1;
wire DID0;
wire DID1;
wire DOA0;
wire DOA1;
wire DOB0;
wire DOB1;
wire DOC0;
wire DOC1;
wire DOD0;
wire DOD1;
wire WCLK;
wire WE;
assign ADDRA0 = ADDRA[0];
assign ADDRA1 = ADDRA[1];
assign ADDRA2 = ADDRA[2];
assign ADDRA3 = ADDRA[3];
assign ADDRA4 = ADDRA[4];
assign ADDRB0 = ADDRB[0];
assign ADDRB1 = ADDRB[1];
assign ADDRB2 = ADDRB[2];
assign ADDRB3 = ADDRB[3];
assign ADDRB4 = ADDRB[4];
assign ADDRC0 = ADDRC[0];
assign ADDRC1 = ADDRC[1];
assign ADDRC2 = ADDRC[2];
assign ADDRC3 = ADDRC[3];
assign ADDRC4 = ADDRC[4];
assign ADDRD0 = ADDRD[0];
assign ADDRD1 = ADDRD[1];
assign ADDRD2 = ADDRD[2];
assign ADDRD3 = ADDRD[3];
assign ADDRD4 = ADDRD[4];
assign DIA0 = DIA[0];
assign DIA1 = DIA[1];
assign DIB0 = DIB[0];
assign DIB1 = DIB[1];
assign DIC0 = DIC[0];
assign DIC1 = DIC[1];
assign DID0 = DID[0];
assign DID1 = DID[1];
assign DOA[1] = DOA1;
assign DOA[0] = DOA0;
assign DOB[1] = DOB1;
assign DOB[0] = DOB0;
assign DOC[1] = DOC1;
assign DOC[0] = DOC0;
assign DOD[1] = DOD1;
assign DOD[0] = DOD0;
RAMD32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMA
(.CLK(WCLK),
.I(DIA0),
.O(DOA0),
.RADR0(ADDRA0),
.RADR1(ADDRA1),
.RADR2(ADDRA2),
.RADR3(ADDRA3),
.RADR4(ADDRA4),
.WADR0(ADDRD0),
.WADR1(ADDRD1),
.WADR2(ADDRD2),
.WADR3(ADDRD3),
.WADR4(ADDRD4),
.WE(WE));
RAMD32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMA_D1
(.CLK(WCLK),
.I(DIA1),
.O(DOA1),
.RADR0(ADDRA0),
.RADR1(ADDRA1),
.RADR2(ADDRA2),
.RADR3(ADDRA3),
.RADR4(ADDRA4),
.WADR0(ADDRD0),
.WADR1(ADDRD1),
.WADR2(ADDRD2),
.WADR3(ADDRD3),
.WADR4(ADDRD4),
.WE(WE));
RAMD32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMB
(.CLK(WCLK),
.I(DIB0),
.O(DOB0),
.RADR0(ADDRB0),
.RADR1(ADDRB1),
.RADR2(ADDRB2),
.RADR3(ADDRB3),
.RADR4(ADDRB4),
.WADR0(ADDRD0),
.WADR1(ADDRD1),
.WADR2(ADDRD2),
.WADR3(ADDRD3),
.WADR4(ADDRD4),
.WE(WE));
RAMD32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMB_D1
(.CLK(WCLK),
.I(DIB1),
.O(DOB1),
.RADR0(ADDRB0),
.RADR1(ADDRB1),
.RADR2(ADDRB2),
.RADR3(ADDRB3),
.RADR4(ADDRB4),
.WADR0(ADDRD0),
.WADR1(ADDRD1),
.WADR2(ADDRD2),
.WADR3(ADDRD3),
.WADR4(ADDRD4),
.WE(WE));
RAMD32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMC
(.CLK(WCLK),
.I(DIC0),
.O(DOC0),
.RADR0(ADDRC0),
.RADR1(ADDRC1),
.RADR2(ADDRC2),
.RADR3(ADDRC3),
.RADR4(ADDRC4),
.WADR0(ADDRD0),
.WADR1(ADDRD1),
.WADR2(ADDRD2),
.WADR3(ADDRD3),
.WADR4(ADDRD4),
.WE(WE));
RAMD32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMC_D1
(.CLK(WCLK),
.I(DIC1),
.O(DOC1),
.RADR0(ADDRC0),
.RADR1(ADDRC1),
.RADR2(ADDRC2),
.RADR3(ADDRC3),
.RADR4(ADDRC4),
.WADR0(ADDRD0),
.WADR1(ADDRD1),
.WADR2(ADDRD2),
.WADR3(ADDRD3),
.WADR4(ADDRD4),
.WE(WE));
RAMS32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMD
(.ADR0(ADDRD0),
.ADR1(ADDRD1),
.ADR2(ADDRD2),
.ADR3(ADDRD3),
.ADR4(ADDRD4),
.CLK(WCLK),
.I(DID0),
.O(DOD0),
.WE(WE));
RAMS32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMD_D1
(.ADR0(ADDRD0),
.ADR1(ADDRD1),
.ADR2(ADDRD2),
.ADR3(ADDRD3),
.ADR4(ADDRD4),
.CLK(WCLK),
.I(DID1),
.O(DOD1),
.WE(WE));
endmodule
|
module RAM32M_HD6
(DOA,
DOB,
DOC,
DOD,
ADDRA,
ADDRB,
ADDRC,
ADDRD,
DIA,
DIB,
DIC,
DID,
WCLK,
WE);
output [1:0]DOA;
output [1:0]DOB;
output [1:0]DOC;
output [1:0]DOD;
input [4:0]ADDRA;
input [4:0]ADDRB;
input [4:0]ADDRC;
input [4:0]ADDRD;
input [1:0]DIA;
input [1:0]DIB;
input [1:0]DIC;
input [1:0]DID;
input WCLK;
input WE;
wire ADDRA0;
wire ADDRA1;
wire ADDRA2;
wire ADDRA3;
wire ADDRA4;
wire ADDRB0;
wire ADDRB1;
wire ADDRB2;
wire ADDRB3;
wire ADDRB4;
wire ADDRC0;
wire ADDRC1;
wire ADDRC2;
wire ADDRC3;
wire ADDRC4;
wire ADDRD0;
wire ADDRD1;
wire ADDRD2;
wire ADDRD3;
wire ADDRD4;
wire DIA0;
wire DIA1;
wire DIB0;
wire DIB1;
wire DIC0;
wire DIC1;
wire DID0;
wire DID1;
wire DOA0;
wire DOA1;
wire DOB0;
wire DOB1;
wire DOC0;
wire DOC1;
wire DOD0;
wire DOD1;
wire WCLK;
wire WE;
assign ADDRA0 = ADDRA[0];
assign ADDRA1 = ADDRA[1];
assign ADDRA2 = ADDRA[2];
assign ADDRA3 = ADDRA[3];
assign ADDRA4 = ADDRA[4];
assign ADDRB0 = ADDRB[0];
assign ADDRB1 = ADDRB[1];
assign ADDRB2 = ADDRB[2];
assign ADDRB3 = ADDRB[3];
assign ADDRB4 = ADDRB[4];
assign ADDRC0 = ADDRC[0];
assign ADDRC1 = ADDRC[1];
assign ADDRC2 = ADDRC[2];
assign ADDRC3 = ADDRC[3];
assign ADDRC4 = ADDRC[4];
assign ADDRD0 = ADDRD[0];
assign ADDRD1 = ADDRD[1];
assign ADDRD2 = ADDRD[2];
assign ADDRD3 = ADDRD[3];
assign ADDRD4 = ADDRD[4];
assign DIA0 = DIA[0];
assign DIA1 = DIA[1];
assign DIB0 = DIB[0];
assign DIB1 = DIB[1];
assign DIC0 = DIC[0];
assign DIC1 = DIC[1];
assign DID0 = DID[0];
assign DID1 = DID[1];
assign DOA[1] = DOA1;
assign DOA[0] = DOA0;
assign DOB[1] = DOB1;
assign DOB[0] = DOB0;
assign DOC[1] = DOC1;
assign DOC[0] = DOC0;
assign DOD[1] = DOD1;
assign DOD[0] = DOD0;
RAMD32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMA
(.CLK(WCLK),
.I(DIA0),
.O(DOA0),
.RADR0(ADDRA0),
.RADR1(ADDRA1),
.RADR2(ADDRA2),
.RADR3(ADDRA3),
.RADR4(ADDRA4),
.WADR0(ADDRD0),
.WADR1(ADDRD1),
.WADR2(ADDRD2),
.WADR3(ADDRD3),
.WADR4(ADDRD4),
.WE(WE));
RAMD32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMA_D1
(.CLK(WCLK),
.I(DIA1),
.O(DOA1),
.RADR0(ADDRA0),
.RADR1(ADDRA1),
.RADR2(ADDRA2),
.RADR3(ADDRA3),
.RADR4(ADDRA4),
.WADR0(ADDRD0),
.WADR1(ADDRD1),
.WADR2(ADDRD2),
.WADR3(ADDRD3),
.WADR4(ADDRD4),
.WE(WE));
RAMD32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMB
(.CLK(WCLK),
.I(DIB0),
.O(DOB0),
.RADR0(ADDRB0),
.RADR1(ADDRB1),
.RADR2(ADDRB2),
.RADR3(ADDRB3),
.RADR4(ADDRB4),
.WADR0(ADDRD0),
.WADR1(ADDRD1),
.WADR2(ADDRD2),
.WADR3(ADDRD3),
.WADR4(ADDRD4),
.WE(WE));
RAMD32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMB_D1
(.CLK(WCLK),
.I(DIB1),
.O(DOB1),
.RADR0(ADDRB0),
.RADR1(ADDRB1),
.RADR2(ADDRB2),
.RADR3(ADDRB3),
.RADR4(ADDRB4),
.WADR0(ADDRD0),
.WADR1(ADDRD1),
.WADR2(ADDRD2),
.WADR3(ADDRD3),
.WADR4(ADDRD4),
.WE(WE));
RAMD32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMC
(.CLK(WCLK),
.I(DIC0),
.O(DOC0),
.RADR0(ADDRC0),
.RADR1(ADDRC1),
.RADR2(ADDRC2),
.RADR3(ADDRC3),
.RADR4(ADDRC4),
.WADR0(ADDRD0),
.WADR1(ADDRD1),
.WADR2(ADDRD2),
.WADR3(ADDRD3),
.WADR4(ADDRD4),
.WE(WE));
RAMD32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMC_D1
(.CLK(WCLK),
.I(DIC1),
.O(DOC1),
.RADR0(ADDRC0),
.RADR1(ADDRC1),
.RADR2(ADDRC2),
.RADR3(ADDRC3),
.RADR4(ADDRC4),
.WADR0(ADDRD0),
.WADR1(ADDRD1),
.WADR2(ADDRD2),
.WADR3(ADDRD3),
.WADR4(ADDRD4),
.WE(WE));
RAMS32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMD
(.ADR0(ADDRD0),
.ADR1(ADDRD1),
.ADR2(ADDRD2),
.ADR3(ADDRD3),
.ADR4(ADDRD4),
.CLK(WCLK),
.I(DID0),
.O(DOD0),
.WE(WE));
RAMS32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMD_D1
(.ADR0(ADDRD0),
.ADR1(ADDRD1),
.ADR2(ADDRD2),
.ADR3(ADDRD3),
.ADR4(ADDRD4),
.CLK(WCLK),
.I(DID1),
.O(DOD1),
.WE(WE));
endmodule
|
module RAM32M_HD7
(DOA,
DOB,
DOC,
DOD,
ADDRA,
ADDRB,
ADDRC,
ADDRD,
DIA,
DIB,
DIC,
DID,
WCLK,
WE);
output [1:0]DOA;
output [1:0]DOB;
output [1:0]DOC;
output [1:0]DOD;
input [4:0]ADDRA;
input [4:0]ADDRB;
input [4:0]ADDRC;
input [4:0]ADDRD;
input [1:0]DIA;
input [1:0]DIB;
input [1:0]DIC;
input [1:0]DID;
input WCLK;
input WE;
wire ADDRA0;
wire ADDRA1;
wire ADDRA2;
wire ADDRA3;
wire ADDRA4;
wire ADDRB0;
wire ADDRB1;
wire ADDRB2;
wire ADDRB3;
wire ADDRB4;
wire ADDRC0;
wire ADDRC1;
wire ADDRC2;
wire ADDRC3;
wire ADDRC4;
wire ADDRD0;
wire ADDRD1;
wire ADDRD2;
wire ADDRD3;
wire ADDRD4;
wire DIA0;
wire DIA1;
wire DIB0;
wire DIB1;
wire DIC0;
wire DIC1;
wire DID0;
wire DID1;
wire DOA0;
wire DOA1;
wire DOB0;
wire DOB1;
wire DOC0;
wire DOC1;
wire DOD0;
wire DOD1;
wire WCLK;
wire WE;
assign ADDRA0 = ADDRA[0];
assign ADDRA1 = ADDRA[1];
assign ADDRA2 = ADDRA[2];
assign ADDRA3 = ADDRA[3];
assign ADDRA4 = ADDRA[4];
assign ADDRB0 = ADDRB[0];
assign ADDRB1 = ADDRB[1];
assign ADDRB2 = ADDRB[2];
assign ADDRB3 = ADDRB[3];
assign ADDRB4 = ADDRB[4];
assign ADDRC0 = ADDRC[0];
assign ADDRC1 = ADDRC[1];
assign ADDRC2 = ADDRC[2];
assign ADDRC3 = ADDRC[3];
assign ADDRC4 = ADDRC[4];
assign ADDRD0 = ADDRD[0];
assign ADDRD1 = ADDRD[1];
assign ADDRD2 = ADDRD[2];
assign ADDRD3 = ADDRD[3];
assign ADDRD4 = ADDRD[4];
assign DIA0 = DIA[0];
assign DIA1 = DIA[1];
assign DIB0 = DIB[0];
assign DIB1 = DIB[1];
assign DIC0 = DIC[0];
assign DIC1 = DIC[1];
assign DID0 = DID[0];
assign DID1 = DID[1];
assign DOA[1] = DOA1;
assign DOA[0] = DOA0;
assign DOB[1] = DOB1;
assign DOB[0] = DOB0;
assign DOC[1] = DOC1;
assign DOC[0] = DOC0;
assign DOD[1] = DOD1;
assign DOD[0] = DOD0;
RAMD32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMA
(.CLK(WCLK),
.I(DIA0),
.O(DOA0),
.RADR0(ADDRA0),
.RADR1(ADDRA1),
.RADR2(ADDRA2),
.RADR3(ADDRA3),
.RADR4(ADDRA4),
.WADR0(ADDRD0),
.WADR1(ADDRD1),
.WADR2(ADDRD2),
.WADR3(ADDRD3),
.WADR4(ADDRD4),
.WE(WE));
RAMD32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMA_D1
(.CLK(WCLK),
.I(DIA1),
.O(DOA1),
.RADR0(ADDRA0),
.RADR1(ADDRA1),
.RADR2(ADDRA2),
.RADR3(ADDRA3),
.RADR4(ADDRA4),
.WADR0(ADDRD0),
.WADR1(ADDRD1),
.WADR2(ADDRD2),
.WADR3(ADDRD3),
.WADR4(ADDRD4),
.WE(WE));
RAMD32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMB
(.CLK(WCLK),
.I(DIB0),
.O(DOB0),
.RADR0(ADDRB0),
.RADR1(ADDRB1),
.RADR2(ADDRB2),
.RADR3(ADDRB3),
.RADR4(ADDRB4),
.WADR0(ADDRD0),
.WADR1(ADDRD1),
.WADR2(ADDRD2),
.WADR3(ADDRD3),
.WADR4(ADDRD4),
.WE(WE));
RAMD32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMB_D1
(.CLK(WCLK),
.I(DIB1),
.O(DOB1),
.RADR0(ADDRB0),
.RADR1(ADDRB1),
.RADR2(ADDRB2),
.RADR3(ADDRB3),
.RADR4(ADDRB4),
.WADR0(ADDRD0),
.WADR1(ADDRD1),
.WADR2(ADDRD2),
.WADR3(ADDRD3),
.WADR4(ADDRD4),
.WE(WE));
RAMD32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMC
(.CLK(WCLK),
.I(DIC0),
.O(DOC0),
.RADR0(ADDRC0),
.RADR1(ADDRC1),
.RADR2(ADDRC2),
.RADR3(ADDRC3),
.RADR4(ADDRC4),
.WADR0(ADDRD0),
.WADR1(ADDRD1),
.WADR2(ADDRD2),
.WADR3(ADDRD3),
.WADR4(ADDRD4),
.WE(WE));
RAMD32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMC_D1
(.CLK(WCLK),
.I(DIC1),
.O(DOC1),
.RADR0(ADDRC0),
.RADR1(ADDRC1),
.RADR2(ADDRC2),
.RADR3(ADDRC3),
.RADR4(ADDRC4),
.WADR0(ADDRD0),
.WADR1(ADDRD1),
.WADR2(ADDRD2),
.WADR3(ADDRD3),
.WADR4(ADDRD4),
.WE(WE));
RAMS32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMD
(.ADR0(ADDRD0),
.ADR1(ADDRD1),
.ADR2(ADDRD2),
.ADR3(ADDRD3),
.ADR4(ADDRD4),
.CLK(WCLK),
.I(DID0),
.O(DOD0),
.WE(WE));
RAMS32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMD_D1
(.ADR0(ADDRD0),
.ADR1(ADDRD1),
.ADR2(ADDRD2),
.ADR3(ADDRD3),
.ADR4(ADDRD4),
.CLK(WCLK),
.I(DID1),
.O(DOD1),
.WE(WE));
endmodule
|
module RAM32M_HD8
(DOA,
DOB,
DOC,
DOD,
ADDRA,
ADDRB,
ADDRC,
ADDRD,
DIA,
DIB,
DIC,
DID,
WCLK,
WE);
output [1:0]DOA;
output [1:0]DOB;
output [1:0]DOC;
output [1:0]DOD;
input [4:0]ADDRA;
input [4:0]ADDRB;
input [4:0]ADDRC;
input [4:0]ADDRD;
input [1:0]DIA;
input [1:0]DIB;
input [1:0]DIC;
input [1:0]DID;
input WCLK;
input WE;
wire ADDRA0;
wire ADDRA1;
wire ADDRA2;
wire ADDRA3;
wire ADDRA4;
wire ADDRB0;
wire ADDRB1;
wire ADDRB2;
wire ADDRB3;
wire ADDRB4;
wire ADDRC0;
wire ADDRC1;
wire ADDRC2;
wire ADDRC3;
wire ADDRC4;
wire ADDRD0;
wire ADDRD1;
wire ADDRD2;
wire ADDRD3;
wire ADDRD4;
wire DIA0;
wire DIA1;
wire DIB0;
wire DIB1;
wire DIC0;
wire DIC1;
wire DID0;
wire DID1;
wire DOA0;
wire DOA1;
wire DOB0;
wire DOB1;
wire DOC0;
wire DOC1;
wire DOD0;
wire DOD1;
wire WCLK;
wire WE;
assign ADDRA0 = ADDRA[0];
assign ADDRA1 = ADDRA[1];
assign ADDRA2 = ADDRA[2];
assign ADDRA3 = ADDRA[3];
assign ADDRA4 = ADDRA[4];
assign ADDRB0 = ADDRB[0];
assign ADDRB1 = ADDRB[1];
assign ADDRB2 = ADDRB[2];
assign ADDRB3 = ADDRB[3];
assign ADDRB4 = ADDRB[4];
assign ADDRC0 = ADDRC[0];
assign ADDRC1 = ADDRC[1];
assign ADDRC2 = ADDRC[2];
assign ADDRC3 = ADDRC[3];
assign ADDRC4 = ADDRC[4];
assign ADDRD0 = ADDRD[0];
assign ADDRD1 = ADDRD[1];
assign ADDRD2 = ADDRD[2];
assign ADDRD3 = ADDRD[3];
assign ADDRD4 = ADDRD[4];
assign DIA0 = DIA[0];
assign DIA1 = DIA[1];
assign DIB0 = DIB[0];
assign DIB1 = DIB[1];
assign DIC0 = DIC[0];
assign DIC1 = DIC[1];
assign DID0 = DID[0];
assign DID1 = DID[1];
assign DOA[1] = DOA1;
assign DOA[0] = DOA0;
assign DOB[1] = DOB1;
assign DOB[0] = DOB0;
assign DOC[1] = DOC1;
assign DOC[0] = DOC0;
assign DOD[1] = DOD1;
assign DOD[0] = DOD0;
RAMD32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMA
(.CLK(WCLK),
.I(DIA0),
.O(DOA0),
.RADR0(ADDRA0),
.RADR1(ADDRA1),
.RADR2(ADDRA2),
.RADR3(ADDRA3),
.RADR4(ADDRA4),
.WADR0(ADDRD0),
.WADR1(ADDRD1),
.WADR2(ADDRD2),
.WADR3(ADDRD3),
.WADR4(ADDRD4),
.WE(WE));
RAMD32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMA_D1
(.CLK(WCLK),
.I(DIA1),
.O(DOA1),
.RADR0(ADDRA0),
.RADR1(ADDRA1),
.RADR2(ADDRA2),
.RADR3(ADDRA3),
.RADR4(ADDRA4),
.WADR0(ADDRD0),
.WADR1(ADDRD1),
.WADR2(ADDRD2),
.WADR3(ADDRD3),
.WADR4(ADDRD4),
.WE(WE));
RAMD32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMB
(.CLK(WCLK),
.I(DIB0),
.O(DOB0),
.RADR0(ADDRB0),
.RADR1(ADDRB1),
.RADR2(ADDRB2),
.RADR3(ADDRB3),
.RADR4(ADDRB4),
.WADR0(ADDRD0),
.WADR1(ADDRD1),
.WADR2(ADDRD2),
.WADR3(ADDRD3),
.WADR4(ADDRD4),
.WE(WE));
RAMD32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMB_D1
(.CLK(WCLK),
.I(DIB1),
.O(DOB1),
.RADR0(ADDRB0),
.RADR1(ADDRB1),
.RADR2(ADDRB2),
.RADR3(ADDRB3),
.RADR4(ADDRB4),
.WADR0(ADDRD0),
.WADR1(ADDRD1),
.WADR2(ADDRD2),
.WADR3(ADDRD3),
.WADR4(ADDRD4),
.WE(WE));
RAMD32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMC
(.CLK(WCLK),
.I(DIC0),
.O(DOC0),
.RADR0(ADDRC0),
.RADR1(ADDRC1),
.RADR2(ADDRC2),
.RADR3(ADDRC3),
.RADR4(ADDRC4),
.WADR0(ADDRD0),
.WADR1(ADDRD1),
.WADR2(ADDRD2),
.WADR3(ADDRD3),
.WADR4(ADDRD4),
.WE(WE));
RAMD32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMC_D1
(.CLK(WCLK),
.I(DIC1),
.O(DOC1),
.RADR0(ADDRC0),
.RADR1(ADDRC1),
.RADR2(ADDRC2),
.RADR3(ADDRC3),
.RADR4(ADDRC4),
.WADR0(ADDRD0),
.WADR1(ADDRD1),
.WADR2(ADDRD2),
.WADR3(ADDRD3),
.WADR4(ADDRD4),
.WE(WE));
RAMS32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMD
(.ADR0(ADDRD0),
.ADR1(ADDRD1),
.ADR2(ADDRD2),
.ADR3(ADDRD3),
.ADR4(ADDRD4),
.CLK(WCLK),
.I(DID0),
.O(DOD0),
.WE(WE));
RAMS32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMD_D1
(.ADR0(ADDRD0),
.ADR1(ADDRD1),
.ADR2(ADDRD2),
.ADR3(ADDRD3),
.ADR4(ADDRD4),
.CLK(WCLK),
.I(DID1),
.O(DOD1),
.WE(WE));
endmodule
|
module RAM32M_HD9
(DOA,
DOB,
DOC,
DOD,
ADDRA,
ADDRB,
ADDRC,
ADDRD,
DIA,
DIB,
DIC,
DID,
WCLK,
WE);
output [1:0]DOA;
output [1:0]DOB;
output [1:0]DOC;
output [1:0]DOD;
input [4:0]ADDRA;
input [4:0]ADDRB;
input [4:0]ADDRC;
input [4:0]ADDRD;
input [1:0]DIA;
input [1:0]DIB;
input [1:0]DIC;
input [1:0]DID;
input WCLK;
input WE;
wire ADDRA0;
wire ADDRA1;
wire ADDRA2;
wire ADDRA3;
wire ADDRA4;
wire ADDRB0;
wire ADDRB1;
wire ADDRB2;
wire ADDRB3;
wire ADDRB4;
wire ADDRC0;
wire ADDRC1;
wire ADDRC2;
wire ADDRC3;
wire ADDRC4;
wire ADDRD0;
wire ADDRD1;
wire ADDRD2;
wire ADDRD3;
wire ADDRD4;
wire DIA0;
wire DIA1;
wire DIB0;
wire DIB1;
wire DIC0;
wire DIC1;
wire DID0;
wire DID1;
wire DOA0;
wire DOA1;
wire DOB0;
wire DOB1;
wire DOC0;
wire DOC1;
wire DOD0;
wire DOD1;
wire WCLK;
wire WE;
assign ADDRA0 = ADDRA[0];
assign ADDRA1 = ADDRA[1];
assign ADDRA2 = ADDRA[2];
assign ADDRA3 = ADDRA[3];
assign ADDRA4 = ADDRA[4];
assign ADDRB0 = ADDRB[0];
assign ADDRB1 = ADDRB[1];
assign ADDRB2 = ADDRB[2];
assign ADDRB3 = ADDRB[3];
assign ADDRB4 = ADDRB[4];
assign ADDRC0 = ADDRC[0];
assign ADDRC1 = ADDRC[1];
assign ADDRC2 = ADDRC[2];
assign ADDRC3 = ADDRC[3];
assign ADDRC4 = ADDRC[4];
assign ADDRD0 = ADDRD[0];
assign ADDRD1 = ADDRD[1];
assign ADDRD2 = ADDRD[2];
assign ADDRD3 = ADDRD[3];
assign ADDRD4 = ADDRD[4];
assign DIA0 = DIA[0];
assign DIA1 = DIA[1];
assign DIB0 = DIB[0];
assign DIB1 = DIB[1];
assign DIC0 = DIC[0];
assign DIC1 = DIC[1];
assign DID0 = DID[0];
assign DID1 = DID[1];
assign DOA[1] = DOA1;
assign DOA[0] = DOA0;
assign DOB[1] = DOB1;
assign DOB[0] = DOB0;
assign DOC[1] = DOC1;
assign DOC[0] = DOC0;
assign DOD[1] = DOD1;
assign DOD[0] = DOD0;
RAMD32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMA
(.CLK(WCLK),
.I(DIA0),
.O(DOA0),
.RADR0(ADDRA0),
.RADR1(ADDRA1),
.RADR2(ADDRA2),
.RADR3(ADDRA3),
.RADR4(ADDRA4),
.WADR0(ADDRD0),
.WADR1(ADDRD1),
.WADR2(ADDRD2),
.WADR3(ADDRD3),
.WADR4(ADDRD4),
.WE(WE));
RAMD32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMA_D1
(.CLK(WCLK),
.I(DIA1),
.O(DOA1),
.RADR0(ADDRA0),
.RADR1(ADDRA1),
.RADR2(ADDRA2),
.RADR3(ADDRA3),
.RADR4(ADDRA4),
.WADR0(ADDRD0),
.WADR1(ADDRD1),
.WADR2(ADDRD2),
.WADR3(ADDRD3),
.WADR4(ADDRD4),
.WE(WE));
RAMD32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMB
(.CLK(WCLK),
.I(DIB0),
.O(DOB0),
.RADR0(ADDRB0),
.RADR1(ADDRB1),
.RADR2(ADDRB2),
.RADR3(ADDRB3),
.RADR4(ADDRB4),
.WADR0(ADDRD0),
.WADR1(ADDRD1),
.WADR2(ADDRD2),
.WADR3(ADDRD3),
.WADR4(ADDRD4),
.WE(WE));
RAMD32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMB_D1
(.CLK(WCLK),
.I(DIB1),
.O(DOB1),
.RADR0(ADDRB0),
.RADR1(ADDRB1),
.RADR2(ADDRB2),
.RADR3(ADDRB3),
.RADR4(ADDRB4),
.WADR0(ADDRD0),
.WADR1(ADDRD1),
.WADR2(ADDRD2),
.WADR3(ADDRD3),
.WADR4(ADDRD4),
.WE(WE));
RAMD32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMC
(.CLK(WCLK),
.I(DIC0),
.O(DOC0),
.RADR0(ADDRC0),
.RADR1(ADDRC1),
.RADR2(ADDRC2),
.RADR3(ADDRC3),
.RADR4(ADDRC4),
.WADR0(ADDRD0),
.WADR1(ADDRD1),
.WADR2(ADDRD2),
.WADR3(ADDRD3),
.WADR4(ADDRD4),
.WE(WE));
RAMD32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMC_D1
(.CLK(WCLK),
.I(DIC1),
.O(DOC1),
.RADR0(ADDRC0),
.RADR1(ADDRC1),
.RADR2(ADDRC2),
.RADR3(ADDRC3),
.RADR4(ADDRC4),
.WADR0(ADDRD0),
.WADR1(ADDRD1),
.WADR2(ADDRD2),
.WADR3(ADDRD3),
.WADR4(ADDRD4),
.WE(WE));
RAMS32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMD
(.ADR0(ADDRD0),
.ADR1(ADDRD1),
.ADR2(ADDRD2),
.ADR3(ADDRD3),
.ADR4(ADDRD4),
.CLK(WCLK),
.I(DID0),
.O(DOD0),
.WE(WE));
RAMS32 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
RAMD_D1
(.ADR0(ADDRD0),
.ADR1(ADDRD1),
.ADR2(ADDRD2),
.ADR3(ADDRD3),
.ADR4(ADDRD4),
.CLK(WCLK),
.I(DID1),
.O(DOD1),
.WE(WE));
endmodule
|
module SERIAL_INPUT
(OUT1,
OUT1_STB,
INTERNAL_RST_reg,
ETH_CLK_OBUF,
OUT1_ACK,
RX);
output [7:0]OUT1;
output OUT1_STB;
input INTERNAL_RST_reg;
input ETH_CLK_OBUF;
input OUT1_ACK;
input RX;
wire [11:0]BAUD_COUNT;
wire \BAUD_COUNT[11]_i_2_n_0 ;
wire \BAUD_COUNT[11]_i_3_n_0 ;
wire \BAUD_COUNT[11]_i_5_n_0 ;
wire \BAUD_COUNT_reg[4]_i_2__0_n_0 ;
wire \BAUD_COUNT_reg[8]_i_2__0_n_0 ;
wire \BAUD_COUNT_reg_n_0_[0] ;
wire \BAUD_COUNT_reg_n_0_[10] ;
wire \BAUD_COUNT_reg_n_0_[11] ;
wire \BAUD_COUNT_reg_n_0_[1] ;
wire \BAUD_COUNT_reg_n_0_[2] ;
wire \BAUD_COUNT_reg_n_0_[3] ;
wire \BAUD_COUNT_reg_n_0_[4] ;
wire \BAUD_COUNT_reg_n_0_[5] ;
wire \BAUD_COUNT_reg_n_0_[6] ;
wire \BAUD_COUNT_reg_n_0_[7] ;
wire \BAUD_COUNT_reg_n_0_[8] ;
wire \BAUD_COUNT_reg_n_0_[9] ;
wire \BIT_SPACING[0]_i_1_n_0 ;
wire \BIT_SPACING[0]_i_2_n_0 ;
wire \BIT_SPACING[1]_i_1_n_0 ;
wire \BIT_SPACING[2]_i_1_n_0 ;
wire \BIT_SPACING[2]_i_2_n_0 ;
wire \BIT_SPACING[2]_i_3_n_0 ;
wire \BIT_SPACING[3]_i_1_n_0 ;
wire \BIT_SPACING[3]_i_2_n_0 ;
wire \BIT_SPACING[3]_i_3_n_0 ;
wire \BIT_SPACING[3]_i_4_n_0 ;
wire \BIT_SPACING[3]_i_5_n_0 ;
wire \BIT_SPACING_reg_n_0_[0] ;
wire \BIT_SPACING_reg_n_0_[1] ;
wire \BIT_SPACING_reg_n_0_[2] ;
wire \BIT_SPACING_reg_n_0_[3] ;
wire \COUNT[0]_i_1_n_0 ;
wire \COUNT[1]_i_1_n_0 ;
wire \COUNT_reg_n_0_[0] ;
wire \COUNT_reg_n_0_[1] ;
wire ETH_CLK_OBUF;
wire \FSM_sequential_STATE[0]_i_1__0_n_0 ;
wire \FSM_sequential_STATE[1]_i_1__0_n_0 ;
wire \FSM_sequential_STATE[2]_i_1__0_n_0 ;
wire \FSM_sequential_STATE[3]_i_1__0_n_0 ;
wire \FSM_sequential_STATE[3]_i_2__0_n_0 ;
wire \FSM_sequential_STATE[3]_i_3__0_n_0 ;
wire \FSM_sequential_STATE[3]_i_4_n_0 ;
wire \FSM_sequential_STATE[3]_i_5_n_0 ;
wire \FSM_sequential_STATE[3]_i_6_n_0 ;
wire \FSM_sequential_STATE[3]_i_7_n_0 ;
wire INTERNAL_RST_reg;
wire INT_SERIAL_i_1_n_0;
wire INT_SERIAL_reg_n_0;
wire [7:0]OUT1;
wire \OUT1[0]_i_1_n_0 ;
wire \OUT1[1]_i_1_n_0 ;
wire \OUT1[2]_i_1_n_0 ;
wire \OUT1[3]_i_1_n_0 ;
wire \OUT1[3]_i_2_n_0 ;
wire \OUT1[4]_i_1_n_0 ;
wire \OUT1[4]_i_2_n_0 ;
wire \OUT1[5]_i_1_n_0 ;
wire \OUT1[5]_i_2_n_0 ;
wire \OUT1[6]_i_1_n_0 ;
wire \OUT1[7]_i_1_n_0 ;
wire OUT1_ACK;
wire OUT1_STB;
wire OUT1_STB_i_1_n_0;
wire OUT1_STB_i_2_n_0;
wire RX;
(* RTL_KEEP = "yes" *) wire [3:0]STATE;
wire X16CLK_EN7_out;
wire X16CLK_EN_reg_n_0;
wire [11:1]data0;
wire p_0_in;
wire p_0_in3_in;
wire [1:1]p_0_in__0;
wire [3:0]\NLW_BAUD_COUNT_reg[11]_i_4__0_CO_UNCONNECTED ;
wire [3:3]\NLW_BAUD_COUNT_reg[11]_i_4__0_O_UNCONNECTED ;
wire [2:0]\NLW_BAUD_COUNT_reg[4]_i_2__0_CO_UNCONNECTED ;
wire [2:0]\NLW_BAUD_COUNT_reg[8]_i_2__0_CO_UNCONNECTED ;
(* SOFT_HLUTNM = "soft_lutpair52" *)
LUT3 #(
.INIT(8'h0E))
\BAUD_COUNT[0]_i_1__0
(.I0(\BAUD_COUNT[11]_i_2_n_0 ),
.I1(\BAUD_COUNT[11]_i_3_n_0 ),
.I2(\BAUD_COUNT_reg_n_0_[0] ),
.O(BAUD_COUNT[0]));
(* SOFT_HLUTNM = "soft_lutpair56" *)
LUT3 #(
.INIT(8'hE0))
\BAUD_COUNT[10]_i_1
(.I0(\BAUD_COUNT[11]_i_2_n_0 ),
.I1(\BAUD_COUNT[11]_i_3_n_0 ),
.I2(data0[10]),
.O(BAUD_COUNT[10]));
(* SOFT_HLUTNM = "soft_lutpair57" *)
LUT3 #(
.INIT(8'hE0))
\BAUD_COUNT[11]_i_1
(.I0(\BAUD_COUNT[11]_i_2_n_0 ),
.I1(\BAUD_COUNT[11]_i_3_n_0 ),
.I2(data0[11]),
.O(BAUD_COUNT[11]));
LUT5 #(
.INIT(32'hFFFFFFFE))
\BAUD_COUNT[11]_i_2
(.I0(\BAUD_COUNT_reg_n_0_[10] ),
.I1(\BAUD_COUNT_reg_n_0_[11] ),
.I2(\BAUD_COUNT_reg_n_0_[9] ),
.I3(\BAUD_COUNT_reg_n_0_[8] ),
.I4(\BAUD_COUNT_reg_n_0_[7] ),
.O(\BAUD_COUNT[11]_i_2_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFF0707FF07))
\BAUD_COUNT[11]_i_3
(.I0(\BAUD_COUNT_reg_n_0_[4] ),
.I1(\BAUD_COUNT_reg_n_0_[3] ),
.I2(\BAUD_COUNT_reg_n_0_[5] ),
.I3(\BAUD_COUNT_reg_n_0_[6] ),
.I4(\BAUD_COUNT_reg_n_0_[7] ),
.I5(\BAUD_COUNT[11]_i_5_n_0 ),
.O(\BAUD_COUNT[11]_i_3_n_0 ));
LUT6 #(
.INIT(64'hFFFDFFFFFFFFFFFF))
\BAUD_COUNT[11]_i_5
(.I0(\BAUD_COUNT_reg_n_0_[4] ),
.I1(\BAUD_COUNT_reg_n_0_[8] ),
.I2(\BAUD_COUNT_reg_n_0_[5] ),
.I3(\BAUD_COUNT_reg_n_0_[2] ),
.I4(\BAUD_COUNT_reg_n_0_[0] ),
.I5(\BAUD_COUNT_reg_n_0_[1] ),
.O(\BAUD_COUNT[11]_i_5_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair53" *)
LUT3 #(
.INIT(8'hE0))
\BAUD_COUNT[1]_i_1
(.I0(\BAUD_COUNT[11]_i_2_n_0 ),
.I1(\BAUD_COUNT[11]_i_3_n_0 ),
.I2(data0[1]),
.O(BAUD_COUNT[1]));
(* SOFT_HLUTNM = "soft_lutpair54" *)
LUT3 #(
.INIT(8'hE0))
\BAUD_COUNT[2]_i_1
(.I0(\BAUD_COUNT[11]_i_2_n_0 ),
.I1(\BAUD_COUNT[11]_i_3_n_0 ),
.I2(data0[2]),
.O(BAUD_COUNT[2]));
(* SOFT_HLUTNM = "soft_lutpair53" *)
LUT3 #(
.INIT(8'hE0))
\BAUD_COUNT[3]_i_1
(.I0(\BAUD_COUNT[11]_i_2_n_0 ),
.I1(\BAUD_COUNT[11]_i_3_n_0 ),
.I2(data0[3]),
.O(BAUD_COUNT[3]));
(* SOFT_HLUTNM = "soft_lutpair52" *)
LUT3 #(
.INIT(8'hE0))
\BAUD_COUNT[4]_i_1
(.I0(\BAUD_COUNT[11]_i_2_n_0 ),
.I1(\BAUD_COUNT[11]_i_3_n_0 ),
.I2(data0[4]),
.O(BAUD_COUNT[4]));
(* SOFT_HLUTNM = "soft_lutpair55" *)
LUT3 #(
.INIT(8'hE0))
\BAUD_COUNT[5]_i_1
(.I0(\BAUD_COUNT[11]_i_2_n_0 ),
.I1(\BAUD_COUNT[11]_i_3_n_0 ),
.I2(data0[5]),
.O(BAUD_COUNT[5]));
(* SOFT_HLUTNM = "soft_lutpair56" *)
LUT3 #(
.INIT(8'hE0))
\BAUD_COUNT[6]_i_1
(.I0(\BAUD_COUNT[11]_i_2_n_0 ),
.I1(\BAUD_COUNT[11]_i_3_n_0 ),
.I2(data0[6]),
.O(BAUD_COUNT[6]));
(* SOFT_HLUTNM = "soft_lutpair55" *)
LUT3 #(
.INIT(8'hE0))
\BAUD_COUNT[7]_i_1
(.I0(\BAUD_COUNT[11]_i_2_n_0 ),
.I1(\BAUD_COUNT[11]_i_3_n_0 ),
.I2(data0[7]),
.O(BAUD_COUNT[7]));
(* SOFT_HLUTNM = "soft_lutpair54" *)
LUT3 #(
.INIT(8'hE0))
\BAUD_COUNT[8]_i_1
(.I0(\BAUD_COUNT[11]_i_2_n_0 ),
.I1(\BAUD_COUNT[11]_i_3_n_0 ),
.I2(data0[8]),
.O(BAUD_COUNT[8]));
(* SOFT_HLUTNM = "soft_lutpair57" *)
LUT3 #(
.INIT(8'hE0))
\BAUD_COUNT[9]_i_1
(.I0(\BAUD_COUNT[11]_i_2_n_0 ),
.I1(\BAUD_COUNT[11]_i_3_n_0 ),
.I2(data0[9]),
.O(BAUD_COUNT[9]));
FDRE \BAUD_COUNT_reg[0]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(BAUD_COUNT[0]),
.Q(\BAUD_COUNT_reg_n_0_[0] ),
.R(INTERNAL_RST_reg));
FDRE \BAUD_COUNT_reg[10]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(BAUD_COUNT[10]),
.Q(\BAUD_COUNT_reg_n_0_[10] ),
.R(INTERNAL_RST_reg));
FDRE \BAUD_COUNT_reg[11]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(BAUD_COUNT[11]),
.Q(\BAUD_COUNT_reg_n_0_[11] ),
.R(INTERNAL_RST_reg));
CARRY4 \BAUD_COUNT_reg[11]_i_4__0
(.CI(\BAUD_COUNT_reg[8]_i_2__0_n_0 ),
.CO(\NLW_BAUD_COUNT_reg[11]_i_4__0_CO_UNCONNECTED [3:0]),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O({\NLW_BAUD_COUNT_reg[11]_i_4__0_O_UNCONNECTED [3],data0[11:9]}),
.S({1'b0,\BAUD_COUNT_reg_n_0_[11] ,\BAUD_COUNT_reg_n_0_[10] ,\BAUD_COUNT_reg_n_0_[9] }));
FDRE \BAUD_COUNT_reg[1]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(BAUD_COUNT[1]),
.Q(\BAUD_COUNT_reg_n_0_[1] ),
.R(INTERNAL_RST_reg));
FDRE \BAUD_COUNT_reg[2]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(BAUD_COUNT[2]),
.Q(\BAUD_COUNT_reg_n_0_[2] ),
.R(INTERNAL_RST_reg));
FDRE \BAUD_COUNT_reg[3]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(BAUD_COUNT[3]),
.Q(\BAUD_COUNT_reg_n_0_[3] ),
.R(INTERNAL_RST_reg));
FDRE \BAUD_COUNT_reg[4]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(BAUD_COUNT[4]),
.Q(\BAUD_COUNT_reg_n_0_[4] ),
.R(INTERNAL_RST_reg));
CARRY4 \BAUD_COUNT_reg[4]_i_2__0
(.CI(1'b0),
.CO({\BAUD_COUNT_reg[4]_i_2__0_n_0 ,\NLW_BAUD_COUNT_reg[4]_i_2__0_CO_UNCONNECTED [2:0]}),
.CYINIT(\BAUD_COUNT_reg_n_0_[0] ),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(data0[4:1]),
.S({\BAUD_COUNT_reg_n_0_[4] ,\BAUD_COUNT_reg_n_0_[3] ,\BAUD_COUNT_reg_n_0_[2] ,\BAUD_COUNT_reg_n_0_[1] }));
FDRE \BAUD_COUNT_reg[5]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(BAUD_COUNT[5]),
.Q(\BAUD_COUNT_reg_n_0_[5] ),
.R(INTERNAL_RST_reg));
FDRE \BAUD_COUNT_reg[6]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(BAUD_COUNT[6]),
.Q(\BAUD_COUNT_reg_n_0_[6] ),
.R(INTERNAL_RST_reg));
FDRE \BAUD_COUNT_reg[7]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(BAUD_COUNT[7]),
.Q(\BAUD_COUNT_reg_n_0_[7] ),
.R(INTERNAL_RST_reg));
FDRE \BAUD_COUNT_reg[8]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(BAUD_COUNT[8]),
.Q(\BAUD_COUNT_reg_n_0_[8] ),
.R(INTERNAL_RST_reg));
CARRY4 \BAUD_COUNT_reg[8]_i_2__0
(.CI(\BAUD_COUNT_reg[4]_i_2__0_n_0 ),
.CO({\BAUD_COUNT_reg[8]_i_2__0_n_0 ,\NLW_BAUD_COUNT_reg[8]_i_2__0_CO_UNCONNECTED [2:0]}),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(data0[8:5]),
.S({\BAUD_COUNT_reg_n_0_[8] ,\BAUD_COUNT_reg_n_0_[7] ,\BAUD_COUNT_reg_n_0_[6] ,\BAUD_COUNT_reg_n_0_[5] }));
FDRE \BAUD_COUNT_reg[9]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(BAUD_COUNT[9]),
.Q(\BAUD_COUNT_reg_n_0_[9] ),
.R(INTERNAL_RST_reg));
LUT6 #(
.INIT(64'h3222332232223222))
\BIT_SPACING[0]_i_1
(.I0(\FSM_sequential_STATE[3]_i_4_n_0 ),
.I1(\BIT_SPACING_reg_n_0_[0] ),
.I2(\BIT_SPACING[3]_i_4_n_0 ),
.I3(\BIT_SPACING[0]_i_2_n_0 ),
.I4(p_0_in),
.I5(\FSM_sequential_STATE[3]_i_6_n_0 ),
.O(\BIT_SPACING[0]_i_1_n_0 ));
LUT4 #(
.INIT(16'h7FFF))
\BIT_SPACING[0]_i_2
(.I0(\BIT_SPACING_reg_n_0_[3] ),
.I1(\BIT_SPACING_reg_n_0_[2] ),
.I2(\BIT_SPACING_reg_n_0_[0] ),
.I3(\BIT_SPACING_reg_n_0_[1] ),
.O(\BIT_SPACING[0]_i_2_n_0 ));
LUT6 #(
.INIT(64'h6660666666606660))
\BIT_SPACING[1]_i_1
(.I0(\BIT_SPACING_reg_n_0_[1] ),
.I1(\BIT_SPACING_reg_n_0_[0] ),
.I2(\FSM_sequential_STATE[3]_i_4_n_0 ),
.I3(\BIT_SPACING[3]_i_4_n_0 ),
.I4(p_0_in),
.I5(\FSM_sequential_STATE[3]_i_6_n_0 ),
.O(\BIT_SPACING[1]_i_1_n_0 ));
LUT6 #(
.INIT(64'hF888FF88F888F888))
\BIT_SPACING[2]_i_1
(.I0(\FSM_sequential_STATE[3]_i_4_n_0 ),
.I1(\BIT_SPACING[2]_i_2_n_0 ),
.I2(\BIT_SPACING[3]_i_4_n_0 ),
.I3(\BIT_SPACING[2]_i_3_n_0 ),
.I4(p_0_in),
.I5(\FSM_sequential_STATE[3]_i_6_n_0 ),
.O(\BIT_SPACING[2]_i_1_n_0 ));
LUT3 #(
.INIT(8'h6C))
\BIT_SPACING[2]_i_2
(.I0(\BIT_SPACING_reg_n_0_[1] ),
.I1(\BIT_SPACING_reg_n_0_[2] ),
.I2(\BIT_SPACING_reg_n_0_[0] ),
.O(\BIT_SPACING[2]_i_2_n_0 ));
LUT3 #(
.INIT(8'h78))
\BIT_SPACING[2]_i_3
(.I0(\BIT_SPACING_reg_n_0_[1] ),
.I1(\BIT_SPACING_reg_n_0_[0] ),
.I2(\BIT_SPACING_reg_n_0_[2] ),
.O(\BIT_SPACING[2]_i_3_n_0 ));
LUT5 #(
.INIT(32'h55FF0001))
\BIT_SPACING[3]_i_1
(.I0(STATE[3]),
.I1(STATE[0]),
.I2(STATE[1]),
.I3(STATE[2]),
.I4(X16CLK_EN_reg_n_0),
.O(\BIT_SPACING[3]_i_1_n_0 ));
LUT6 #(
.INIT(64'hF888FF88F888F888))
\BIT_SPACING[3]_i_2
(.I0(\FSM_sequential_STATE[3]_i_4_n_0 ),
.I1(\BIT_SPACING[3]_i_3_n_0 ),
.I2(\BIT_SPACING[3]_i_4_n_0 ),
.I3(\BIT_SPACING[3]_i_5_n_0 ),
.I4(p_0_in),
.I5(\FSM_sequential_STATE[3]_i_6_n_0 ),
.O(\BIT_SPACING[3]_i_2_n_0 ));
LUT5 #(
.INIT(32'h52F0F0F0))
\BIT_SPACING[3]_i_3
(.I0(\BIT_SPACING_reg_n_0_[1] ),
.I1(X16CLK_EN_reg_n_0),
.I2(\BIT_SPACING_reg_n_0_[3] ),
.I3(\BIT_SPACING_reg_n_0_[2] ),
.I4(\BIT_SPACING_reg_n_0_[0] ),
.O(\BIT_SPACING[3]_i_3_n_0 ));
LUT4 #(
.INIT(16'h4000))
\BIT_SPACING[3]_i_4
(.I0(STATE[2]),
.I1(STATE[3]),
.I2(STATE[1]),
.I3(STATE[0]),
.O(\BIT_SPACING[3]_i_4_n_0 ));
LUT4 #(
.INIT(16'h7F80))
\BIT_SPACING[3]_i_5
(.I0(\BIT_SPACING_reg_n_0_[1] ),
.I1(\BIT_SPACING_reg_n_0_[0] ),
.I2(\BIT_SPACING_reg_n_0_[2] ),
.I3(\BIT_SPACING_reg_n_0_[3] ),
.O(\BIT_SPACING[3]_i_5_n_0 ));
LUT5 #(
.INIT(32'h80000000))
\BIT_SPACING[3]_i_6
(.I0(\BIT_SPACING_reg_n_0_[3] ),
.I1(\BIT_SPACING_reg_n_0_[1] ),
.I2(\BIT_SPACING_reg_n_0_[0] ),
.I3(\BIT_SPACING_reg_n_0_[2] ),
.I4(X16CLK_EN_reg_n_0),
.O(p_0_in));
FDRE \BIT_SPACING_reg[0]
(.C(ETH_CLK_OBUF),
.CE(\BIT_SPACING[3]_i_1_n_0 ),
.D(\BIT_SPACING[0]_i_1_n_0 ),
.Q(\BIT_SPACING_reg_n_0_[0] ),
.R(1'b0));
FDRE \BIT_SPACING_reg[1]
(.C(ETH_CLK_OBUF),
.CE(\BIT_SPACING[3]_i_1_n_0 ),
.D(\BIT_SPACING[1]_i_1_n_0 ),
.Q(\BIT_SPACING_reg_n_0_[1] ),
.R(1'b0));
FDRE \BIT_SPACING_reg[2]
(.C(ETH_CLK_OBUF),
.CE(\BIT_SPACING[3]_i_1_n_0 ),
.D(\BIT_SPACING[2]_i_1_n_0 ),
.Q(\BIT_SPACING_reg_n_0_[2] ),
.R(1'b0));
FDRE \BIT_SPACING_reg[3]
(.C(ETH_CLK_OBUF),
.CE(\BIT_SPACING[3]_i_1_n_0 ),
.D(\BIT_SPACING[3]_i_2_n_0 ),
.Q(\BIT_SPACING_reg_n_0_[3] ),
.R(1'b0));
LUT4 #(
.INIT(16'h8FE0))
\COUNT[0]_i_1
(.I0(p_0_in3_in),
.I1(\COUNT_reg_n_0_[1] ),
.I2(X16CLK_EN_reg_n_0),
.I3(\COUNT_reg_n_0_[0] ),
.O(\COUNT[0]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair49" *)
LUT4 #(
.INIT(16'hECC4))
\COUNT[1]_i_1
(.I0(X16CLK_EN_reg_n_0),
.I1(\COUNT_reg_n_0_[1] ),
.I2(p_0_in3_in),
.I3(\COUNT_reg_n_0_[0] ),
.O(\COUNT[1]_i_1_n_0 ));
FDRE \COUNT_reg[0]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(\COUNT[0]_i_1_n_0 ),
.Q(\COUNT_reg_n_0_[0] ),
.R(1'b0));
FDRE \COUNT_reg[1]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(\COUNT[1]_i_1_n_0 ),
.Q(\COUNT_reg_n_0_[1] ),
.R(1'b0));
LUT3 #(
.INIT(8'h07))
\FSM_sequential_STATE[0]_i_1__0
(.I0(STATE[2]),
.I1(STATE[3]),
.I2(STATE[0]),
.O(\FSM_sequential_STATE[0]_i_1__0_n_0 ));
LUT4 #(
.INIT(16'h152A))
\FSM_sequential_STATE[1]_i_1__0
(.I0(STATE[1]),
.I1(STATE[2]),
.I2(STATE[3]),
.I3(STATE[0]),
.O(\FSM_sequential_STATE[1]_i_1__0_n_0 ));
LUT4 #(
.INIT(16'h006A))
\FSM_sequential_STATE[2]_i_1__0
(.I0(STATE[2]),
.I1(STATE[1]),
.I2(STATE[0]),
.I3(STATE[3]),
.O(\FSM_sequential_STATE[2]_i_1__0_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFFFFA8FF20))
\FSM_sequential_STATE[3]_i_1__0
(.I0(\FSM_sequential_STATE[3]_i_3__0_n_0 ),
.I1(\BIT_SPACING_reg_n_0_[3] ),
.I2(\FSM_sequential_STATE[3]_i_4_n_0 ),
.I3(\FSM_sequential_STATE[3]_i_5_n_0 ),
.I4(\FSM_sequential_STATE[3]_i_6_n_0 ),
.I5(\FSM_sequential_STATE[3]_i_7_n_0 ),
.O(\FSM_sequential_STATE[3]_i_1__0_n_0 ));
LUT4 #(
.INIT(16'h1580))
\FSM_sequential_STATE[3]_i_2__0
(.I0(STATE[2]),
.I1(STATE[1]),
.I2(STATE[0]),
.I3(STATE[3]),
.O(\FSM_sequential_STATE[3]_i_2__0_n_0 ));
LUT4 #(
.INIT(16'h8000))
\FSM_sequential_STATE[3]_i_3__0
(.I0(X16CLK_EN_reg_n_0),
.I1(\BIT_SPACING_reg_n_0_[2] ),
.I2(\BIT_SPACING_reg_n_0_[0] ),
.I3(\BIT_SPACING_reg_n_0_[1] ),
.O(\FSM_sequential_STATE[3]_i_3__0_n_0 ));
LUT4 #(
.INIT(16'h0004))
\FSM_sequential_STATE[3]_i_4
(.I0(STATE[3]),
.I1(STATE[0]),
.I2(STATE[2]),
.I3(STATE[1]),
.O(\FSM_sequential_STATE[3]_i_4_n_0 ));
LUT6 #(
.INIT(64'h0000000000000010))
\FSM_sequential_STATE[3]_i_5
(.I0(STATE[1]),
.I1(STATE[2]),
.I2(X16CLK_EN_reg_n_0),
.I3(INT_SERIAL_reg_n_0),
.I4(STATE[3]),
.I5(STATE[0]),
.O(\FSM_sequential_STATE[3]_i_5_n_0 ));
LUT4 #(
.INIT(16'h337C))
\FSM_sequential_STATE[3]_i_6
(.I0(STATE[0]),
.I1(STATE[3]),
.I2(STATE[1]),
.I3(STATE[2]),
.O(\FSM_sequential_STATE[3]_i_6_n_0 ));
LUT5 #(
.INIT(32'h00800000))
\FSM_sequential_STATE[3]_i_7
(.I0(STATE[0]),
.I1(STATE[1]),
.I2(STATE[3]),
.I3(STATE[2]),
.I4(OUT1_ACK),
.O(\FSM_sequential_STATE[3]_i_7_n_0 ));
(* KEEP = "yes" *)
FDRE \FSM_sequential_STATE_reg[0]
(.C(ETH_CLK_OBUF),
.CE(\FSM_sequential_STATE[3]_i_1__0_n_0 ),
.D(\FSM_sequential_STATE[0]_i_1__0_n_0 ),
.Q(STATE[0]),
.R(INTERNAL_RST_reg));
(* KEEP = "yes" *)
FDRE \FSM_sequential_STATE_reg[1]
(.C(ETH_CLK_OBUF),
.CE(\FSM_sequential_STATE[3]_i_1__0_n_0 ),
.D(\FSM_sequential_STATE[1]_i_1__0_n_0 ),
.Q(STATE[1]),
.R(INTERNAL_RST_reg));
(* KEEP = "yes" *)
FDRE \FSM_sequential_STATE_reg[2]
(.C(ETH_CLK_OBUF),
.CE(\FSM_sequential_STATE[3]_i_1__0_n_0 ),
.D(\FSM_sequential_STATE[2]_i_1__0_n_0 ),
.Q(STATE[2]),
.R(INTERNAL_RST_reg));
(* KEEP = "yes" *)
FDRE \FSM_sequential_STATE_reg[3]
(.C(ETH_CLK_OBUF),
.CE(\FSM_sequential_STATE[3]_i_1__0_n_0 ),
.D(\FSM_sequential_STATE[3]_i_2__0_n_0 ),
.Q(STATE[3]),
.R(INTERNAL_RST_reg));
(* SOFT_HLUTNM = "soft_lutpair49" *)
LUT5 #(
.INIT(32'hEAAAA8AA))
INT_SERIAL_i_1
(.I0(INT_SERIAL_reg_n_0),
.I1(\COUNT_reg_n_0_[1] ),
.I2(\COUNT_reg_n_0_[0] ),
.I3(X16CLK_EN_reg_n_0),
.I4(p_0_in3_in),
.O(INT_SERIAL_i_1_n_0));
FDRE INT_SERIAL_reg
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(INT_SERIAL_i_1_n_0),
.Q(INT_SERIAL_reg_n_0),
.R(1'b0));
LUT6 #(
.INIT(64'hFFBFFFFF00800000))
\OUT1[0]_i_1
(.I0(INT_SERIAL_reg_n_0),
.I1(p_0_in),
.I2(STATE[1]),
.I3(STATE[2]),
.I4(\OUT1[4]_i_2_n_0 ),
.I5(OUT1[0]),
.O(\OUT1[0]_i_1_n_0 ));
LUT6 #(
.INIT(64'hF8FFFFFF08000000))
\OUT1[1]_i_1
(.I0(INT_SERIAL_reg_n_0),
.I1(\OUT1[3]_i_2_n_0 ),
.I2(STATE[2]),
.I3(p_0_in),
.I4(\OUT1[5]_i_2_n_0 ),
.I5(OUT1[1]),
.O(\OUT1[1]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFFBFFFFF00800000))
\OUT1[2]_i_1
(.I0(INT_SERIAL_reg_n_0),
.I1(STATE[2]),
.I2(\OUT1[4]_i_2_n_0 ),
.I3(STATE[1]),
.I4(p_0_in),
.I5(OUT1[2]),
.O(\OUT1[2]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFFBFFFFF00800000))
\OUT1[3]_i_1
(.I0(INT_SERIAL_reg_n_0),
.I1(STATE[2]),
.I2(\OUT1[3]_i_2_n_0 ),
.I3(STATE[1]),
.I4(p_0_in),
.I5(OUT1[3]),
.O(\OUT1[3]_i_1_n_0 ));
LUT2 #(
.INIT(4'h2))
\OUT1[3]_i_2
(.I0(STATE[0]),
.I1(STATE[3]),
.O(\OUT1[3]_i_2_n_0 ));
LUT6 #(
.INIT(64'hBFFFFFFF80000000))
\OUT1[4]_i_1
(.I0(INT_SERIAL_reg_n_0),
.I1(p_0_in),
.I2(STATE[1]),
.I3(STATE[2]),
.I4(\OUT1[4]_i_2_n_0 ),
.I5(OUT1[4]),
.O(\OUT1[4]_i_1_n_0 ));
LUT2 #(
.INIT(4'h1))
\OUT1[4]_i_2
(.I0(STATE[0]),
.I1(STATE[3]),
.O(\OUT1[4]_i_2_n_0 ));
LUT5 #(
.INIT(32'hBFFF8000))
\OUT1[5]_i_1
(.I0(INT_SERIAL_reg_n_0),
.I1(STATE[2]),
.I2(p_0_in),
.I3(\OUT1[5]_i_2_n_0 ),
.I4(OUT1[5]),
.O(\OUT1[5]_i_1_n_0 ));
LUT3 #(
.INIT(8'h08))
\OUT1[5]_i_2
(.I0(STATE[1]),
.I1(STATE[0]),
.I2(STATE[3]),
.O(\OUT1[5]_i_2_n_0 ));
LUT6 #(
.INIT(64'hFFEFFFFF00200000))
\OUT1[6]_i_1
(.I0(INT_SERIAL_reg_n_0),
.I1(STATE[0]),
.I2(STATE[3]),
.I3(STATE[1]),
.I4(p_0_in),
.I5(OUT1[6]),
.O(\OUT1[6]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFFBFFFFF00800000))
\OUT1[7]_i_1
(.I0(INT_SERIAL_reg_n_0),
.I1(STATE[3]),
.I2(STATE[0]),
.I3(STATE[1]),
.I4(p_0_in),
.I5(OUT1[7]),
.O(\OUT1[7]_i_1_n_0 ));
LUT5 #(
.INIT(32'h10FF1000))
OUT1_STB_i_1
(.I0(STATE[2]),
.I1(STATE[0]),
.I2(p_0_in),
.I3(OUT1_STB_i_2_n_0),
.I4(OUT1_STB),
.O(OUT1_STB_i_1_n_0));
LUT6 #(
.INIT(64'h080C000008000000))
OUT1_STB_i_2
(.I0(OUT1_ACK),
.I1(STATE[3]),
.I2(STATE[2]),
.I3(STATE[0]),
.I4(STATE[1]),
.I5(p_0_in),
.O(OUT1_STB_i_2_n_0));
FDRE OUT1_STB_reg
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(OUT1_STB_i_1_n_0),
.Q(OUT1_STB),
.R(INTERNAL_RST_reg));
FDRE \OUT1_reg[0]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(\OUT1[0]_i_1_n_0 ),
.Q(OUT1[0]),
.R(1'b0));
FDRE \OUT1_reg[1]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(\OUT1[1]_i_1_n_0 ),
.Q(OUT1[1]),
.R(1'b0));
FDRE \OUT1_reg[2]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(\OUT1[2]_i_1_n_0 ),
.Q(OUT1[2]),
.R(1'b0));
FDRE \OUT1_reg[3]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(\OUT1[3]_i_1_n_0 ),
.Q(OUT1[3]),
.R(1'b0));
FDRE \OUT1_reg[4]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(\OUT1[4]_i_1_n_0 ),
.Q(OUT1[4]),
.R(1'b0));
FDRE \OUT1_reg[5]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(\OUT1[5]_i_1_n_0 ),
.Q(OUT1[5]),
.R(1'b0));
FDRE \OUT1_reg[6]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(\OUT1[6]_i_1_n_0 ),
.Q(OUT1[6]),
.R(1'b0));
FDRE \OUT1_reg[7]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(\OUT1[7]_i_1_n_0 ),
.Q(OUT1[7]),
.R(1'b0));
FDSE \SERIAL_DEGLITCH_reg[0]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(RX),
.Q(p_0_in__0),
.S(INTERNAL_RST_reg));
FDSE \SERIAL_DEGLITCH_reg[1]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(p_0_in__0),
.Q(p_0_in3_in),
.S(INTERNAL_RST_reg));
LUT3 #(
.INIT(8'h01))
X16CLK_EN_i_1
(.I0(INTERNAL_RST_reg),
.I1(\BAUD_COUNT[11]_i_2_n_0 ),
.I2(\BAUD_COUNT[11]_i_3_n_0 ),
.O(X16CLK_EN7_out));
FDRE X16CLK_EN_reg
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(X16CLK_EN7_out),
.Q(X16CLK_EN_reg_n_0),
.R(1'b0));
endmodule
|
module VIDEO_TIME_GEN
(\PIXCOL_DEL_reg[0] ,
\PIXCOL_DEL_reg[1] ,
\PIXCOL_DEL_reg[2] ,
ADDRBWRADDR,
\PIXROW_DEL_reg[0] ,
\PIXROW_DEL_reg[1] ,
D,
HSYNCH_DEL_reg,
VSYNCH_DEL_reg,
BLANK,
ETH_CLK_OBUF,
INTERNAL_RST_reg);
output \PIXCOL_DEL_reg[0] ;
output \PIXCOL_DEL_reg[1] ;
output \PIXCOL_DEL_reg[2] ;
output [12:0]ADDRBWRADDR;
output \PIXROW_DEL_reg[0] ;
output \PIXROW_DEL_reg[1] ;
output [0:0]D;
output HSYNCH_DEL_reg;
output VSYNCH_DEL_reg;
output BLANK;
input ETH_CLK_OBUF;
input INTERNAL_RST_reg;
wire [12:0]ADDRBWRADDR;
wire BLANK;
wire \COL_ADDRESS[0]_i_1_n_0 ;
wire \COL_ADDRESS[1]_i_1_n_0 ;
wire \COL_ADDRESS[2]_i_1_n_0 ;
wire \COL_ADDRESS[3]_i_1_n_0 ;
wire \COL_ADDRESS[4]_i_1_n_0 ;
wire \COL_ADDRESS[5]_i_1_n_0 ;
wire \COL_ADDRESS[6]_i_1_n_0 ;
wire \COL_ADDRESS[6]_i_2_n_0 ;
wire \COL_ADDRESS[6]_i_3_n_0 ;
wire \COL_ADDRESS_reg_n_0_[1] ;
wire \COL_ADDRESS_reg_n_0_[2] ;
wire \COL_ADDRESS_reg_n_0_[3] ;
wire \COL_ADDRESS_reg_n_0_[4] ;
wire \COL_ADDRESS_reg_n_0_[5] ;
wire \COL_ADDRESS_reg_n_0_[6] ;
wire [0:0]D;
wire ETH_CLK_OBUF;
wire HBLANK_i_1_n_0;
wire HBLANK_i_2_n_0;
wire HBLANK_i_3_n_0;
wire HBLANK_i_4_n_0;
wire HBLANK_i_5_n_0;
wire HBLANK_i_6_n_0;
wire HBLANK_reg_n_0;
wire HSYNCH_DEL_reg;
wire [10:0]HTIMER;
wire \HTIMER[0]_i_2_n_0 ;
wire \HTIMER[0]_i_3_n_0 ;
wire \HTIMER[10]_i_2_n_0 ;
wire \HTIMER[10]_i_3_n_0 ;
wire \HTIMER[10]_i_4_n_0 ;
wire \HTIMER[2]_i_1_n_0 ;
wire \HTIMER[4]_i_2_n_0 ;
wire \HTIMER[5]_i_1_n_0 ;
wire \HTIMER[6]_i_1_n_0 ;
wire \HTIMER[9]_i_2_n_0 ;
wire INTERNAL_RST_reg;
wire INTHSYNCH_i_1_n_0;
wire INTVSYNCH2_out;
wire INTVSYNCH_i_1_n_0;
wire INTVSYNCH_i_3_n_0;
wire MEMORY_reg_0_i_11_n_0;
wire MEMORY_reg_0_i_12_n_0;
wire MEMORY_reg_0_i_13_n_0;
wire MEMORY_reg_0_i_14_n_0;
wire MEMORY_reg_0_i_15_n_0;
wire MEMORY_reg_0_i_16_n_0;
wire MEMORY_reg_0_i_2_n_0;
wire MEMORY_reg_0_i_3_n_0;
wire \PIXCOL_DEL_reg[0] ;
wire \PIXCOL_DEL_reg[1] ;
wire \PIXCOL_DEL_reg[2] ;
wire \PIXROW_DEL_reg[0] ;
wire \PIXROW_DEL_reg[1] ;
wire \PIX_COL_ADDRESS[0]_i_1_n_0 ;
wire \PIX_COL_ADDRESS[1]_i_1_n_0 ;
wire \PIX_COL_ADDRESS[2]_i_1_n_0 ;
wire \PIX_ROW_ADDRESS[0]_i_1_n_0 ;
wire \PIX_ROW_ADDRESS[1]_i_1_n_0 ;
wire \PIX_ROW_ADDRESS[2]_i_1_n_0 ;
wire \PIX_ROW_ADDRESS[2]_i_2_n_0 ;
wire \PIX_ROW_ADDRESS[2]_i_3_n_0 ;
wire [12:1]ROW_ADDRESS;
wire \ROW_ADDRESS[12]_i_1_n_0 ;
wire \ROW_ADDRESS[12]_i_3_n_0 ;
wire \ROW_ADDRESS[12]_i_4_n_0 ;
wire \ROW_ADDRESS[4]_i_5_n_0 ;
wire \ROW_ADDRESS[8]_i_5_n_0 ;
wire \ROW_ADDRESS[8]_i_6_n_0 ;
wire [12:1]ROW_ADDRESS_0;
wire \ROW_ADDRESS_reg[12]_i_5_n_4 ;
wire \ROW_ADDRESS_reg[12]_i_5_n_5 ;
wire \ROW_ADDRESS_reg[12]_i_5_n_6 ;
wire \ROW_ADDRESS_reg[12]_i_5_n_7 ;
wire \ROW_ADDRESS_reg[4]_i_2_n_0 ;
wire \ROW_ADDRESS_reg[4]_i_2_n_4 ;
wire \ROW_ADDRESS_reg[4]_i_2_n_5 ;
wire \ROW_ADDRESS_reg[4]_i_2_n_6 ;
wire \ROW_ADDRESS_reg[4]_i_2_n_7 ;
wire \ROW_ADDRESS_reg[8]_i_2_n_0 ;
wire \ROW_ADDRESS_reg[8]_i_2_n_4 ;
wire \ROW_ADDRESS_reg[8]_i_2_n_5 ;
wire \ROW_ADDRESS_reg[8]_i_2_n_6 ;
wire \ROW_ADDRESS_reg[8]_i_2_n_7 ;
wire VBLANK_i_1_n_0;
wire VBLANK_i_2_n_0;
wire VBLANK_i_3_n_0;
wire VBLANK_i_4_n_0;
wire VBLANK_i_5_n_0;
wire VBLANK_i_6_n_0;
wire VBLANK_i_7_n_0;
wire VBLANK_reg_n_0;
wire VSYNCH_DEL_reg;
wire [9:0]VTIMER;
wire \VTIMER[0]_i_1_n_0 ;
wire \VTIMER[2]_i_2_n_0 ;
wire \VTIMER[2]_i_3_n_0 ;
wire \VTIMER[5]_i_1_n_0 ;
wire \VTIMER[9]_i_2_n_0 ;
wire \VTIMER[9]_i_3_n_0 ;
wire \VTIMER[9]_i_4_n_0 ;
wire \VTIMER[9]_i_5_n_0 ;
wire [9:1]VTIMER_1;
wire VTIMER_EN;
wire VTIMER_EN_i_1_n_0;
wire [10:0]sel0;
wire [3:0]NLW_MEMORY_reg_0_i_1_CO_UNCONNECTED;
wire [2:0]NLW_MEMORY_reg_0_i_2_CO_UNCONNECTED;
wire [2:0]NLW_MEMORY_reg_0_i_3_CO_UNCONNECTED;
wire [0:0]NLW_MEMORY_reg_0_i_3_O_UNCONNECTED;
wire [3:0]\NLW_ROW_ADDRESS_reg[12]_i_5_CO_UNCONNECTED ;
wire [2:0]\NLW_ROW_ADDRESS_reg[4]_i_2_CO_UNCONNECTED ;
wire [2:0]\NLW_ROW_ADDRESS_reg[8]_i_2_CO_UNCONNECTED ;
LUT2 #(
.INIT(4'hE))
BLANK_DEL_i_1
(.I0(VBLANK_reg_n_0),
.I1(HBLANK_reg_n_0),
.O(BLANK));
LUT1 #(
.INIT(2'h1))
\COL_ADDRESS[0]_i_1
(.I0(ADDRBWRADDR[0]),
.O(\COL_ADDRESS[0]_i_1_n_0 ));
LUT2 #(
.INIT(4'h6))
\COL_ADDRESS[1]_i_1
(.I0(\COL_ADDRESS_reg_n_0_[1] ),
.I1(ADDRBWRADDR[0]),
.O(\COL_ADDRESS[1]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFFFF00000000EFFF))
\COL_ADDRESS[2]_i_1
(.I0(\COL_ADDRESS_reg_n_0_[4] ),
.I1(\COL_ADDRESS_reg_n_0_[3] ),
.I2(\COL_ADDRESS_reg_n_0_[6] ),
.I3(\COL_ADDRESS_reg_n_0_[5] ),
.I4(\COL_ADDRESS[6]_i_3_n_0 ),
.I5(\COL_ADDRESS_reg_n_0_[2] ),
.O(\COL_ADDRESS[2]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair4" *)
LUT4 #(
.INIT(16'h6AAA))
\COL_ADDRESS[3]_i_1
(.I0(\COL_ADDRESS_reg_n_0_[3] ),
.I1(\COL_ADDRESS_reg_n_0_[1] ),
.I2(ADDRBWRADDR[0]),
.I3(\COL_ADDRESS_reg_n_0_[2] ),
.O(\COL_ADDRESS[3]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair4" *)
LUT5 #(
.INIT(32'h6AAAAAAA))
\COL_ADDRESS[4]_i_1
(.I0(\COL_ADDRESS_reg_n_0_[4] ),
.I1(\COL_ADDRESS_reg_n_0_[2] ),
.I2(ADDRBWRADDR[0]),
.I3(\COL_ADDRESS_reg_n_0_[1] ),
.I4(\COL_ADDRESS_reg_n_0_[3] ),
.O(\COL_ADDRESS[4]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFF3FFFFD00C00000))
\COL_ADDRESS[5]_i_1
(.I0(\COL_ADDRESS_reg_n_0_[6] ),
.I1(\COL_ADDRESS_reg_n_0_[4] ),
.I2(\COL_ADDRESS_reg_n_0_[2] ),
.I3(\COL_ADDRESS[6]_i_3_n_0 ),
.I4(\COL_ADDRESS_reg_n_0_[3] ),
.I5(\COL_ADDRESS_reg_n_0_[5] ),
.O(\COL_ADDRESS[5]_i_1_n_0 ));
LUT5 #(
.INIT(32'h00000080))
\COL_ADDRESS[6]_i_1
(.I0(\PIXCOL_DEL_reg[0] ),
.I1(\PIXCOL_DEL_reg[1] ),
.I2(\PIXCOL_DEL_reg[2] ),
.I3(HBLANK_reg_n_0),
.I4(VBLANK_reg_n_0),
.O(\COL_ADDRESS[6]_i_1_n_0 ));
LUT6 #(
.INIT(64'hDFFEFFFF20000000))
\COL_ADDRESS[6]_i_2
(.I0(\COL_ADDRESS_reg_n_0_[3] ),
.I1(\COL_ADDRESS[6]_i_3_n_0 ),
.I2(\COL_ADDRESS_reg_n_0_[2] ),
.I3(\COL_ADDRESS_reg_n_0_[4] ),
.I4(\COL_ADDRESS_reg_n_0_[5] ),
.I5(\COL_ADDRESS_reg_n_0_[6] ),
.O(\COL_ADDRESS[6]_i_2_n_0 ));
LUT2 #(
.INIT(4'h7))
\COL_ADDRESS[6]_i_3
(.I0(\COL_ADDRESS_reg_n_0_[1] ),
.I1(ADDRBWRADDR[0]),
.O(\COL_ADDRESS[6]_i_3_n_0 ));
FDRE \COL_ADDRESS_reg[0]
(.C(ETH_CLK_OBUF),
.CE(\COL_ADDRESS[6]_i_1_n_0 ),
.D(\COL_ADDRESS[0]_i_1_n_0 ),
.Q(ADDRBWRADDR[0]),
.R(INTERNAL_RST_reg));
FDRE \COL_ADDRESS_reg[1]
(.C(ETH_CLK_OBUF),
.CE(\COL_ADDRESS[6]_i_1_n_0 ),
.D(\COL_ADDRESS[1]_i_1_n_0 ),
.Q(\COL_ADDRESS_reg_n_0_[1] ),
.R(INTERNAL_RST_reg));
FDRE \COL_ADDRESS_reg[2]
(.C(ETH_CLK_OBUF),
.CE(\COL_ADDRESS[6]_i_1_n_0 ),
.D(\COL_ADDRESS[2]_i_1_n_0 ),
.Q(\COL_ADDRESS_reg_n_0_[2] ),
.R(INTERNAL_RST_reg));
FDRE \COL_ADDRESS_reg[3]
(.C(ETH_CLK_OBUF),
.CE(\COL_ADDRESS[6]_i_1_n_0 ),
.D(\COL_ADDRESS[3]_i_1_n_0 ),
.Q(\COL_ADDRESS_reg_n_0_[3] ),
.R(INTERNAL_RST_reg));
FDRE \COL_ADDRESS_reg[4]
(.C(ETH_CLK_OBUF),
.CE(\COL_ADDRESS[6]_i_1_n_0 ),
.D(\COL_ADDRESS[4]_i_1_n_0 ),
.Q(\COL_ADDRESS_reg_n_0_[4] ),
.R(INTERNAL_RST_reg));
FDRE \COL_ADDRESS_reg[5]
(.C(ETH_CLK_OBUF),
.CE(\COL_ADDRESS[6]_i_1_n_0 ),
.D(\COL_ADDRESS[5]_i_1_n_0 ),
.Q(\COL_ADDRESS_reg_n_0_[5] ),
.R(INTERNAL_RST_reg));
FDRE \COL_ADDRESS_reg[6]
(.C(ETH_CLK_OBUF),
.CE(\COL_ADDRESS[6]_i_1_n_0 ),
.D(\COL_ADDRESS[6]_i_2_n_0 ),
.Q(\COL_ADDRESS_reg_n_0_[6] ),
.R(INTERNAL_RST_reg));
LUT6 #(
.INIT(64'hFFFFFFFFFFF70000))
HBLANK_i_1
(.I0(HBLANK_i_2_n_0),
.I1(sel0[7]),
.I2(sel0[8]),
.I3(sel0[6]),
.I4(HBLANK_reg_n_0),
.I5(HBLANK_i_3_n_0),
.O(HBLANK_i_1_n_0));
LUT6 #(
.INIT(64'h0000000010000000))
HBLANK_i_2
(.I0(sel0[9]),
.I1(sel0[10]),
.I2(sel0[5]),
.I3(sel0[4]),
.I4(sel0[3]),
.I5(HBLANK_i_4_n_0),
.O(HBLANK_i_2_n_0));
LUT6 #(
.INIT(64'hAAAAABAAAAAAAAAA))
HBLANK_i_3
(.I0(INTERNAL_RST_reg),
.I1(HBLANK_i_5_n_0),
.I2(sel0[0]),
.I3(sel0[3]),
.I4(HBLANK_i_6_n_0),
.I5(\HTIMER[0]_i_3_n_0 ),
.O(HBLANK_i_3_n_0));
LUT3 #(
.INIT(8'hFE))
HBLANK_i_4
(.I0(sel0[2]),
.I1(sel0[1]),
.I2(sel0[0]),
.O(HBLANK_i_4_n_0));
LUT3 #(
.INIT(8'hBF))
HBLANK_i_5
(.I0(sel0[10]),
.I1(sel0[8]),
.I2(sel0[9]),
.O(HBLANK_i_5_n_0));
LUT2 #(
.INIT(4'h7))
HBLANK_i_6
(.I0(sel0[7]),
.I1(sel0[6]),
.O(HBLANK_i_6_n_0));
FDRE HBLANK_reg
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(HBLANK_i_1_n_0),
.Q(HBLANK_reg_n_0),
.R(1'b0));
LUT5 #(
.INIT(32'h0000FDFF))
\HTIMER[0]_i_1
(.I0(\HTIMER[0]_i_2_n_0 ),
.I1(sel0[6]),
.I2(sel0[3]),
.I3(\HTIMER[0]_i_3_n_0 ),
.I4(sel0[0]),
.O(HTIMER[0]));
LUT4 #(
.INIT(16'h0010))
\HTIMER[0]_i_2
(.I0(sel0[8]),
.I1(sel0[7]),
.I2(sel0[10]),
.I3(sel0[9]),
.O(\HTIMER[0]_i_2_n_0 ));
LUT4 #(
.INIT(16'h0010))
\HTIMER[0]_i_3
(.I0(sel0[2]),
.I1(sel0[1]),
.I2(sel0[4]),
.I3(sel0[5]),
.O(\HTIMER[0]_i_3_n_0 ));
LUT5 #(
.INIT(32'h3AAAAAAA))
\HTIMER[10]_i_1
(.I0(\HTIMER[10]_i_2_n_0 ),
.I1(sel0[10]),
.I2(sel0[8]),
.I3(sel0[9]),
.I4(\HTIMER[10]_i_3_n_0 ),
.O(HTIMER[10]));
LUT6 #(
.INIT(64'hAAAAAAA8AAAAAAAA))
\HTIMER[10]_i_2
(.I0(sel0[10]),
.I1(sel0[8]),
.I2(sel0[6]),
.I3(sel0[9]),
.I4(sel0[7]),
.I5(\HTIMER[10]_i_4_n_0 ),
.O(\HTIMER[10]_i_2_n_0 ));
LUT3 #(
.INIT(8'h40))
\HTIMER[10]_i_3
(.I0(\HTIMER[9]_i_2_n_0 ),
.I1(sel0[6]),
.I2(sel0[7]),
.O(\HTIMER[10]_i_3_n_0 ));
LUT6 #(
.INIT(64'h0000000000000010))
\HTIMER[10]_i_4
(.I0(sel0[5]),
.I1(sel0[3]),
.I2(sel0[4]),
.I3(sel0[2]),
.I4(sel0[1]),
.I5(sel0[0]),
.O(\HTIMER[10]_i_4_n_0 ));
LUT2 #(
.INIT(4'h6))
\HTIMER[1]_i_1
(.I0(sel0[0]),
.I1(sel0[1]),
.O(HTIMER[1]));
(* SOFT_HLUTNM = "soft_lutpair8" *)
LUT3 #(
.INIT(8'h6A))
\HTIMER[2]_i_1
(.I0(sel0[2]),
.I1(sel0[1]),
.I2(sel0[0]),
.O(\HTIMER[2]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair8" *)
LUT4 #(
.INIT(16'h6AAA))
\HTIMER[3]_i_1
(.I0(sel0[3]),
.I1(sel0[1]),
.I2(sel0[0]),
.I3(sel0[2]),
.O(HTIMER[3]));
LUT6 #(
.INIT(64'h1555555540000000))
\HTIMER[4]_i_1
(.I0(\HTIMER[4]_i_2_n_0 ),
.I1(sel0[2]),
.I2(sel0[0]),
.I3(sel0[1]),
.I4(sel0[3]),
.I5(sel0[4]),
.O(HTIMER[4]));
LUT6 #(
.INIT(64'h0000000000000200))
\HTIMER[4]_i_2
(.I0(\HTIMER[10]_i_4_n_0 ),
.I1(sel0[8]),
.I2(sel0[7]),
.I3(sel0[10]),
.I4(sel0[9]),
.I5(sel0[6]),
.O(\HTIMER[4]_i_2_n_0 ));
LUT6 #(
.INIT(64'h6AAAAAAAAAAAAAAA))
\HTIMER[5]_i_1
(.I0(sel0[5]),
.I1(sel0[4]),
.I2(sel0[3]),
.I3(sel0[1]),
.I4(sel0[0]),
.I5(sel0[2]),
.O(\HTIMER[5]_i_1_n_0 ));
LUT2 #(
.INIT(4'h9))
\HTIMER[6]_i_1
(.I0(sel0[6]),
.I1(\HTIMER[9]_i_2_n_0 ),
.O(\HTIMER[6]_i_1_n_0 ));
LUT3 #(
.INIT(8'h9A))
\HTIMER[7]_i_1
(.I0(sel0[7]),
.I1(\HTIMER[9]_i_2_n_0 ),
.I2(sel0[6]),
.O(HTIMER[7]));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT4 #(
.INIT(16'hAA6A))
\HTIMER[8]_i_1
(.I0(sel0[8]),
.I1(sel0[7]),
.I2(sel0[6]),
.I3(\HTIMER[9]_i_2_n_0 ),
.O(HTIMER[8]));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT5 #(
.INIT(32'h9AAAAAAA))
\HTIMER[9]_i_1
(.I0(sel0[9]),
.I1(\HTIMER[9]_i_2_n_0 ),
.I2(sel0[6]),
.I3(sel0[7]),
.I4(sel0[8]),
.O(HTIMER[9]));
LUT6 #(
.INIT(64'h7FFFFFFFFFFFFFFF))
\HTIMER[9]_i_2
(.I0(sel0[4]),
.I1(sel0[3]),
.I2(sel0[1]),
.I3(sel0[0]),
.I4(sel0[2]),
.I5(sel0[5]),
.O(\HTIMER[9]_i_2_n_0 ));
FDRE \HTIMER_reg[0]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(HTIMER[0]),
.Q(sel0[0]),
.R(INTERNAL_RST_reg));
FDRE \HTIMER_reg[10]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(HTIMER[10]),
.Q(sel0[10]),
.R(INTERNAL_RST_reg));
FDRE \HTIMER_reg[1]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(HTIMER[1]),
.Q(sel0[1]),
.R(INTERNAL_RST_reg));
FDRE \HTIMER_reg[2]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(\HTIMER[2]_i_1_n_0 ),
.Q(sel0[2]),
.R(INTERNAL_RST_reg));
FDRE \HTIMER_reg[3]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(HTIMER[3]),
.Q(sel0[3]),
.R(INTERNAL_RST_reg));
FDRE \HTIMER_reg[4]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(HTIMER[4]),
.Q(sel0[4]),
.R(INTERNAL_RST_reg));
FDRE \HTIMER_reg[5]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(\HTIMER[5]_i_1_n_0 ),
.Q(sel0[5]),
.R(INTERNAL_RST_reg));
FDRE \HTIMER_reg[6]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(\HTIMER[6]_i_1_n_0 ),
.Q(sel0[6]),
.R(INTERNAL_RST_reg));
FDRE \HTIMER_reg[7]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(HTIMER[7]),
.Q(sel0[7]),
.R(INTERNAL_RST_reg));
FDRE \HTIMER_reg[8]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(HTIMER[8]),
.Q(sel0[8]),
.R(INTERNAL_RST_reg));
FDRE \HTIMER_reg[9]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(HTIMER[9]),
.Q(sel0[9]),
.R(INTERNAL_RST_reg));
LUT6 #(
.INIT(64'h00000000AAAEAAAA))
INTHSYNCH_i_1
(.I0(HSYNCH_DEL_reg),
.I1(HBLANK_i_2_n_0),
.I2(sel0[7]),
.I3(sel0[8]),
.I4(sel0[6]),
.I5(VTIMER_EN_i_1_n_0),
.O(INTHSYNCH_i_1_n_0));
FDRE INTHSYNCH_reg
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(INTHSYNCH_i_1_n_0),
.Q(HSYNCH_DEL_reg),
.R(1'b0));
LUT6 #(
.INIT(64'h00000000EEEE0EEE))
INTVSYNCH_i_1
(.I0(VSYNCH_DEL_reg),
.I1(INTVSYNCH2_out),
.I2(\VTIMER[2]_i_2_n_0 ),
.I3(VTIMER_EN),
.I4(VTIMER[0]),
.I5(INTERNAL_RST_reg),
.O(INTVSYNCH_i_1_n_0));
LUT6 #(
.INIT(64'h0000000000000002))
INTVSYNCH_i_2
(.I0(VBLANK_i_2_n_0),
.I1(VTIMER[0]),
.I2(INTVSYNCH_i_3_n_0),
.I3(VTIMER[3]),
.I4(VTIMER[5]),
.I5(VTIMER[4]),
.O(INTVSYNCH2_out));
LUT2 #(
.INIT(4'h7))
INTVSYNCH_i_3
(.I0(VTIMER[1]),
.I1(VTIMER[2]),
.O(INTVSYNCH_i_3_n_0));
FDRE INTVSYNCH_reg
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(INTVSYNCH_i_1_n_0),
.Q(VSYNCH_DEL_reg),
.R(1'b0));
CARRY4 MEMORY_reg_0_i_1
(.CI(MEMORY_reg_0_i_2_n_0),
.CO(NLW_MEMORY_reg_0_i_1_CO_UNCONNECTED[3:0]),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(ADDRBWRADDR[12:9]),
.S(ROW_ADDRESS[12:9]));
LUT2 #(
.INIT(4'h6))
MEMORY_reg_0_i_11
(.I0(ROW_ADDRESS[6]),
.I1(\COL_ADDRESS_reg_n_0_[6] ),
.O(MEMORY_reg_0_i_11_n_0));
LUT2 #(
.INIT(4'h6))
MEMORY_reg_0_i_12
(.I0(ROW_ADDRESS[5]),
.I1(\COL_ADDRESS_reg_n_0_[5] ),
.O(MEMORY_reg_0_i_12_n_0));
LUT2 #(
.INIT(4'h6))
MEMORY_reg_0_i_13
(.I0(ROW_ADDRESS[4]),
.I1(\COL_ADDRESS_reg_n_0_[4] ),
.O(MEMORY_reg_0_i_13_n_0));
LUT2 #(
.INIT(4'h6))
MEMORY_reg_0_i_14
(.I0(ROW_ADDRESS[3]),
.I1(\COL_ADDRESS_reg_n_0_[3] ),
.O(MEMORY_reg_0_i_14_n_0));
LUT2 #(
.INIT(4'h6))
MEMORY_reg_0_i_15
(.I0(ROW_ADDRESS[2]),
.I1(\COL_ADDRESS_reg_n_0_[2] ),
.O(MEMORY_reg_0_i_15_n_0));
LUT2 #(
.INIT(4'h6))
MEMORY_reg_0_i_16
(.I0(ROW_ADDRESS[1]),
.I1(\COL_ADDRESS_reg_n_0_[1] ),
.O(MEMORY_reg_0_i_16_n_0));
CARRY4 MEMORY_reg_0_i_2
(.CI(MEMORY_reg_0_i_3_n_0),
.CO({MEMORY_reg_0_i_2_n_0,NLW_MEMORY_reg_0_i_2_CO_UNCONNECTED[2:0]}),
.CYINIT(1'b0),
.DI({1'b0,1'b0,ROW_ADDRESS[6:5]}),
.O(ADDRBWRADDR[8:5]),
.S({ROW_ADDRESS[8:7],MEMORY_reg_0_i_11_n_0,MEMORY_reg_0_i_12_n_0}));
CARRY4 MEMORY_reg_0_i_3
(.CI(1'b0),
.CO({MEMORY_reg_0_i_3_n_0,NLW_MEMORY_reg_0_i_3_CO_UNCONNECTED[2:0]}),
.CYINIT(1'b0),
.DI(ROW_ADDRESS[4:1]),
.O({ADDRBWRADDR[4:2],NLW_MEMORY_reg_0_i_3_O_UNCONNECTED[0]}),
.S({MEMORY_reg_0_i_13_n_0,MEMORY_reg_0_i_14_n_0,MEMORY_reg_0_i_15_n_0,MEMORY_reg_0_i_16_n_0}));
LUT2 #(
.INIT(4'h6))
MEMORY_reg_0_i_4
(.I0(ROW_ADDRESS[1]),
.I1(\COL_ADDRESS_reg_n_0_[1] ),
.O(ADDRBWRADDR[1]));
LUT3 #(
.INIT(8'hE1))
\PIX_COL_ADDRESS[0]_i_1
(.I0(VBLANK_reg_n_0),
.I1(HBLANK_reg_n_0),
.I2(\PIXCOL_DEL_reg[0] ),
.O(\PIX_COL_ADDRESS[0]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT4 #(
.INIT(16'hFD02))
\PIX_COL_ADDRESS[1]_i_1
(.I0(\PIXCOL_DEL_reg[0] ),
.I1(HBLANK_reg_n_0),
.I2(VBLANK_reg_n_0),
.I3(\PIXCOL_DEL_reg[1] ),
.O(\PIX_COL_ADDRESS[1]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT5 #(
.INIT(32'hFFF70008))
\PIX_COL_ADDRESS[2]_i_1
(.I0(\PIXCOL_DEL_reg[0] ),
.I1(\PIXCOL_DEL_reg[1] ),
.I2(HBLANK_reg_n_0),
.I3(VBLANK_reg_n_0),
.I4(\PIXCOL_DEL_reg[2] ),
.O(\PIX_COL_ADDRESS[2]_i_1_n_0 ));
FDRE \PIX_COL_ADDRESS_reg[0]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(\PIX_COL_ADDRESS[0]_i_1_n_0 ),
.Q(\PIXCOL_DEL_reg[0] ),
.R(INTERNAL_RST_reg));
FDRE \PIX_COL_ADDRESS_reg[1]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(\PIX_COL_ADDRESS[1]_i_1_n_0 ),
.Q(\PIXCOL_DEL_reg[1] ),
.R(INTERNAL_RST_reg));
FDRE \PIX_COL_ADDRESS_reg[2]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(\PIX_COL_ADDRESS[2]_i_1_n_0 ),
.Q(\PIXCOL_DEL_reg[2] ),
.R(INTERNAL_RST_reg));
LUT2 #(
.INIT(4'h6))
\PIX_ROW_ADDRESS[0]_i_1
(.I0(\PIX_ROW_ADDRESS[2]_i_2_n_0 ),
.I1(\PIXROW_DEL_reg[0] ),
.O(\PIX_ROW_ADDRESS[0]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair5" *)
LUT3 #(
.INIT(8'h78))
\PIX_ROW_ADDRESS[1]_i_1
(.I0(\PIXROW_DEL_reg[0] ),
.I1(\PIX_ROW_ADDRESS[2]_i_2_n_0 ),
.I2(\PIXROW_DEL_reg[1] ),
.O(\PIX_ROW_ADDRESS[1]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair5" *)
LUT4 #(
.INIT(16'h7F80))
\PIX_ROW_ADDRESS[2]_i_1
(.I0(\PIXROW_DEL_reg[0] ),
.I1(\PIXROW_DEL_reg[1] ),
.I2(\PIX_ROW_ADDRESS[2]_i_2_n_0 ),
.I3(D),
.O(\PIX_ROW_ADDRESS[2]_i_1_n_0 ));
LUT6 #(
.INIT(64'h0000000010000000))
\PIX_ROW_ADDRESS[2]_i_2
(.I0(VBLANK_reg_n_0),
.I1(HBLANK_reg_n_0),
.I2(\PIXCOL_DEL_reg[2] ),
.I3(\PIXCOL_DEL_reg[1] ),
.I4(\PIXCOL_DEL_reg[0] ),
.I5(\PIX_ROW_ADDRESS[2]_i_3_n_0 ),
.O(\PIX_ROW_ADDRESS[2]_i_2_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFFFFFFFFF7))
\PIX_ROW_ADDRESS[2]_i_3
(.I0(\COL_ADDRESS_reg_n_0_[5] ),
.I1(\COL_ADDRESS_reg_n_0_[6] ),
.I2(\COL_ADDRESS_reg_n_0_[2] ),
.I3(\COL_ADDRESS_reg_n_0_[3] ),
.I4(\COL_ADDRESS_reg_n_0_[4] ),
.I5(\COL_ADDRESS[6]_i_3_n_0 ),
.O(\PIX_ROW_ADDRESS[2]_i_3_n_0 ));
FDRE \PIX_ROW_ADDRESS_reg[0]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(\PIX_ROW_ADDRESS[0]_i_1_n_0 ),
.Q(\PIXROW_DEL_reg[0] ),
.R(INTERNAL_RST_reg));
FDRE \PIX_ROW_ADDRESS_reg[1]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(\PIX_ROW_ADDRESS[1]_i_1_n_0 ),
.Q(\PIXROW_DEL_reg[1] ),
.R(INTERNAL_RST_reg));
FDRE \PIX_ROW_ADDRESS_reg[2]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(\PIX_ROW_ADDRESS[2]_i_1_n_0 ),
.Q(D),
.R(INTERNAL_RST_reg));
(* SOFT_HLUTNM = "soft_lutpair17" *)
LUT3 #(
.INIT(8'h70))
\ROW_ADDRESS[10]_i_1
(.I0(\ROW_ADDRESS[12]_i_3_n_0 ),
.I1(\ROW_ADDRESS[12]_i_4_n_0 ),
.I2(\ROW_ADDRESS_reg[12]_i_5_n_6 ),
.O(ROW_ADDRESS_0[10]));
(* SOFT_HLUTNM = "soft_lutpair16" *)
LUT3 #(
.INIT(8'h70))
\ROW_ADDRESS[11]_i_1
(.I0(\ROW_ADDRESS[12]_i_3_n_0 ),
.I1(\ROW_ADDRESS[12]_i_4_n_0 ),
.I2(\ROW_ADDRESS_reg[12]_i_5_n_5 ),
.O(ROW_ADDRESS_0[11]));
LUT4 #(
.INIT(16'h8000))
\ROW_ADDRESS[12]_i_1
(.I0(\PIX_ROW_ADDRESS[2]_i_2_n_0 ),
.I1(D),
.I2(\PIXROW_DEL_reg[0] ),
.I3(\PIXROW_DEL_reg[1] ),
.O(\ROW_ADDRESS[12]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair15" *)
LUT3 #(
.INIT(8'h70))
\ROW_ADDRESS[12]_i_2
(.I0(\ROW_ADDRESS[12]_i_3_n_0 ),
.I1(\ROW_ADDRESS[12]_i_4_n_0 ),
.I2(\ROW_ADDRESS_reg[12]_i_5_n_4 ),
.O(ROW_ADDRESS_0[12]));
LUT6 #(
.INIT(64'h0040000000000000))
\ROW_ADDRESS[12]_i_3
(.I0(ROW_ADDRESS[9]),
.I1(ROW_ADDRESS[10]),
.I2(ROW_ADDRESS[7]),
.I3(ROW_ADDRESS[8]),
.I4(ROW_ADDRESS[11]),
.I5(ROW_ADDRESS[12]),
.O(\ROW_ADDRESS[12]_i_3_n_0 ));
LUT6 #(
.INIT(64'h0000000000000080))
\ROW_ADDRESS[12]_i_4
(.I0(ROW_ADDRESS[6]),
.I1(ROW_ADDRESS[5]),
.I2(ROW_ADDRESS[3]),
.I3(ROW_ADDRESS[4]),
.I4(ROW_ADDRESS[1]),
.I5(ROW_ADDRESS[2]),
.O(\ROW_ADDRESS[12]_i_4_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair15" *)
LUT3 #(
.INIT(8'h70))
\ROW_ADDRESS[1]_i_1
(.I0(\ROW_ADDRESS[12]_i_3_n_0 ),
.I1(\ROW_ADDRESS[12]_i_4_n_0 ),
.I2(\ROW_ADDRESS_reg[4]_i_2_n_7 ),
.O(ROW_ADDRESS_0[1]));
(* SOFT_HLUTNM = "soft_lutpair16" *)
LUT3 #(
.INIT(8'h70))
\ROW_ADDRESS[2]_i_1
(.I0(\ROW_ADDRESS[12]_i_3_n_0 ),
.I1(\ROW_ADDRESS[12]_i_4_n_0 ),
.I2(\ROW_ADDRESS_reg[4]_i_2_n_6 ),
.O(ROW_ADDRESS_0[2]));
(* SOFT_HLUTNM = "soft_lutpair17" *)
LUT3 #(
.INIT(8'h70))
\ROW_ADDRESS[3]_i_1
(.I0(\ROW_ADDRESS[12]_i_3_n_0 ),
.I1(\ROW_ADDRESS[12]_i_4_n_0 ),
.I2(\ROW_ADDRESS_reg[4]_i_2_n_5 ),
.O(ROW_ADDRESS_0[3]));
(* SOFT_HLUTNM = "soft_lutpair19" *)
LUT3 #(
.INIT(8'h70))
\ROW_ADDRESS[4]_i_1
(.I0(\ROW_ADDRESS[12]_i_3_n_0 ),
.I1(\ROW_ADDRESS[12]_i_4_n_0 ),
.I2(\ROW_ADDRESS_reg[4]_i_2_n_4 ),
.O(ROW_ADDRESS_0[4]));
LUT1 #(
.INIT(2'h1))
\ROW_ADDRESS[4]_i_5
(.I0(ROW_ADDRESS[2]),
.O(\ROW_ADDRESS[4]_i_5_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair20" *)
LUT3 #(
.INIT(8'h70))
\ROW_ADDRESS[5]_i_1
(.I0(\ROW_ADDRESS[12]_i_3_n_0 ),
.I1(\ROW_ADDRESS[12]_i_4_n_0 ),
.I2(\ROW_ADDRESS_reg[8]_i_2_n_7 ),
.O(ROW_ADDRESS_0[5]));
(* SOFT_HLUTNM = "soft_lutpair21" *)
LUT3 #(
.INIT(8'h70))
\ROW_ADDRESS[6]_i_1
(.I0(\ROW_ADDRESS[12]_i_3_n_0 ),
.I1(\ROW_ADDRESS[12]_i_4_n_0 ),
.I2(\ROW_ADDRESS_reg[8]_i_2_n_6 ),
.O(ROW_ADDRESS_0[6]));
(* SOFT_HLUTNM = "soft_lutpair21" *)
LUT3 #(
.INIT(8'h70))
\ROW_ADDRESS[7]_i_1
(.I0(\ROW_ADDRESS[12]_i_3_n_0 ),
.I1(\ROW_ADDRESS[12]_i_4_n_0 ),
.I2(\ROW_ADDRESS_reg[8]_i_2_n_5 ),
.O(ROW_ADDRESS_0[7]));
(* SOFT_HLUTNM = "soft_lutpair20" *)
LUT3 #(
.INIT(8'h70))
\ROW_ADDRESS[8]_i_1
(.I0(\ROW_ADDRESS[12]_i_3_n_0 ),
.I1(\ROW_ADDRESS[12]_i_4_n_0 ),
.I2(\ROW_ADDRESS_reg[8]_i_2_n_4 ),
.O(ROW_ADDRESS_0[8]));
LUT1 #(
.INIT(2'h1))
\ROW_ADDRESS[8]_i_5
(.I0(ROW_ADDRESS[6]),
.O(\ROW_ADDRESS[8]_i_5_n_0 ));
LUT1 #(
.INIT(2'h1))
\ROW_ADDRESS[8]_i_6
(.I0(ROW_ADDRESS[5]),
.O(\ROW_ADDRESS[8]_i_6_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair19" *)
LUT3 #(
.INIT(8'h70))
\ROW_ADDRESS[9]_i_1
(.I0(\ROW_ADDRESS[12]_i_3_n_0 ),
.I1(\ROW_ADDRESS[12]_i_4_n_0 ),
.I2(\ROW_ADDRESS_reg[12]_i_5_n_7 ),
.O(ROW_ADDRESS_0[9]));
FDRE \ROW_ADDRESS_reg[10]
(.C(ETH_CLK_OBUF),
.CE(\ROW_ADDRESS[12]_i_1_n_0 ),
.D(ROW_ADDRESS_0[10]),
.Q(ROW_ADDRESS[10]),
.R(INTERNAL_RST_reg));
FDRE \ROW_ADDRESS_reg[11]
(.C(ETH_CLK_OBUF),
.CE(\ROW_ADDRESS[12]_i_1_n_0 ),
.D(ROW_ADDRESS_0[11]),
.Q(ROW_ADDRESS[11]),
.R(INTERNAL_RST_reg));
FDRE \ROW_ADDRESS_reg[12]
(.C(ETH_CLK_OBUF),
.CE(\ROW_ADDRESS[12]_i_1_n_0 ),
.D(ROW_ADDRESS_0[12]),
.Q(ROW_ADDRESS[12]),
.R(INTERNAL_RST_reg));
CARRY4 \ROW_ADDRESS_reg[12]_i_5
(.CI(\ROW_ADDRESS_reg[8]_i_2_n_0 ),
.CO(\NLW_ROW_ADDRESS_reg[12]_i_5_CO_UNCONNECTED [3:0]),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O({\ROW_ADDRESS_reg[12]_i_5_n_4 ,\ROW_ADDRESS_reg[12]_i_5_n_5 ,\ROW_ADDRESS_reg[12]_i_5_n_6 ,\ROW_ADDRESS_reg[12]_i_5_n_7 }),
.S(ROW_ADDRESS[12:9]));
FDRE \ROW_ADDRESS_reg[1]
(.C(ETH_CLK_OBUF),
.CE(\ROW_ADDRESS[12]_i_1_n_0 ),
.D(ROW_ADDRESS_0[1]),
.Q(ROW_ADDRESS[1]),
.R(INTERNAL_RST_reg));
FDRE \ROW_ADDRESS_reg[2]
(.C(ETH_CLK_OBUF),
.CE(\ROW_ADDRESS[12]_i_1_n_0 ),
.D(ROW_ADDRESS_0[2]),
.Q(ROW_ADDRESS[2]),
.R(INTERNAL_RST_reg));
FDRE \ROW_ADDRESS_reg[3]
(.C(ETH_CLK_OBUF),
.CE(\ROW_ADDRESS[12]_i_1_n_0 ),
.D(ROW_ADDRESS_0[3]),
.Q(ROW_ADDRESS[3]),
.R(INTERNAL_RST_reg));
FDRE \ROW_ADDRESS_reg[4]
(.C(ETH_CLK_OBUF),
.CE(\ROW_ADDRESS[12]_i_1_n_0 ),
.D(ROW_ADDRESS_0[4]),
.Q(ROW_ADDRESS[4]),
.R(INTERNAL_RST_reg));
CARRY4 \ROW_ADDRESS_reg[4]_i_2
(.CI(1'b0),
.CO({\ROW_ADDRESS_reg[4]_i_2_n_0 ,\NLW_ROW_ADDRESS_reg[4]_i_2_CO_UNCONNECTED [2:0]}),
.CYINIT(1'b0),
.DI({1'b0,1'b0,ROW_ADDRESS[2],1'b0}),
.O({\ROW_ADDRESS_reg[4]_i_2_n_4 ,\ROW_ADDRESS_reg[4]_i_2_n_5 ,\ROW_ADDRESS_reg[4]_i_2_n_6 ,\ROW_ADDRESS_reg[4]_i_2_n_7 }),
.S({ROW_ADDRESS[4:3],\ROW_ADDRESS[4]_i_5_n_0 ,ROW_ADDRESS[1]}));
FDRE \ROW_ADDRESS_reg[5]
(.C(ETH_CLK_OBUF),
.CE(\ROW_ADDRESS[12]_i_1_n_0 ),
.D(ROW_ADDRESS_0[5]),
.Q(ROW_ADDRESS[5]),
.R(INTERNAL_RST_reg));
FDRE \ROW_ADDRESS_reg[6]
(.C(ETH_CLK_OBUF),
.CE(\ROW_ADDRESS[12]_i_1_n_0 ),
.D(ROW_ADDRESS_0[6]),
.Q(ROW_ADDRESS[6]),
.R(INTERNAL_RST_reg));
FDRE \ROW_ADDRESS_reg[7]
(.C(ETH_CLK_OBUF),
.CE(\ROW_ADDRESS[12]_i_1_n_0 ),
.D(ROW_ADDRESS_0[7]),
.Q(ROW_ADDRESS[7]),
.R(INTERNAL_RST_reg));
FDRE \ROW_ADDRESS_reg[8]
(.C(ETH_CLK_OBUF),
.CE(\ROW_ADDRESS[12]_i_1_n_0 ),
.D(ROW_ADDRESS_0[8]),
.Q(ROW_ADDRESS[8]),
.R(INTERNAL_RST_reg));
CARRY4 \ROW_ADDRESS_reg[8]_i_2
(.CI(\ROW_ADDRESS_reg[4]_i_2_n_0 ),
.CO({\ROW_ADDRESS_reg[8]_i_2_n_0 ,\NLW_ROW_ADDRESS_reg[8]_i_2_CO_UNCONNECTED [2:0]}),
.CYINIT(1'b0),
.DI({1'b0,1'b0,ROW_ADDRESS[6:5]}),
.O({\ROW_ADDRESS_reg[8]_i_2_n_4 ,\ROW_ADDRESS_reg[8]_i_2_n_5 ,\ROW_ADDRESS_reg[8]_i_2_n_6 ,\ROW_ADDRESS_reg[8]_i_2_n_7 }),
.S({ROW_ADDRESS[8:7],\ROW_ADDRESS[8]_i_5_n_0 ,\ROW_ADDRESS[8]_i_6_n_0 }));
FDRE \ROW_ADDRESS_reg[9]
(.C(ETH_CLK_OBUF),
.CE(\ROW_ADDRESS[12]_i_1_n_0 ),
.D(ROW_ADDRESS_0[9]),
.Q(ROW_ADDRESS[9]),
.R(INTERNAL_RST_reg));
LUT4 #(
.INIT(16'hFFD0))
VBLANK_i_1
(.I0(VBLANK_i_2_n_0),
.I1(VBLANK_i_3_n_0),
.I2(VBLANK_reg_n_0),
.I3(VBLANK_i_4_n_0),
.O(VBLANK_i_1_n_0));
LUT5 #(
.INIT(32'h00000004))
VBLANK_i_2
(.I0(VTIMER[7]),
.I1(VTIMER_EN),
.I2(VTIMER[8]),
.I3(VTIMER[9]),
.I4(VTIMER[6]),
.O(VBLANK_i_2_n_0));
LUT6 #(
.INIT(64'hFFFFFBFFFFFFFFFF))
VBLANK_i_3
(.I0(VTIMER[2]),
.I1(VTIMER[0]),
.I2(VTIMER[1]),
.I3(VTIMER[5]),
.I4(VTIMER[4]),
.I5(VTIMER[3]),
.O(VBLANK_i_3_n_0));
LUT6 #(
.INIT(64'hAAAAAAAAAAAAAABA))
VBLANK_i_4
(.I0(INTERNAL_RST_reg),
.I1(VBLANK_i_5_n_0),
.I2(VTIMER_EN),
.I3(VBLANK_i_6_n_0),
.I4(VTIMER[6]),
.I5(VBLANK_i_7_n_0),
.O(VBLANK_i_4_n_0));
LUT3 #(
.INIT(8'hFE))
VBLANK_i_5
(.I0(VTIMER[3]),
.I1(VTIMER[5]),
.I2(VTIMER[4]),
.O(VBLANK_i_5_n_0));
LUT3 #(
.INIT(8'hFB))
VBLANK_i_6
(.I0(VTIMER[1]),
.I1(VTIMER[0]),
.I2(VTIMER[2]),
.O(VBLANK_i_6_n_0));
LUT3 #(
.INIT(8'hDF))
VBLANK_i_7
(.I0(VTIMER[9]),
.I1(VTIMER[8]),
.I2(VTIMER[7]),
.O(VBLANK_i_7_n_0));
FDRE VBLANK_reg
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(VBLANK_i_1_n_0),
.Q(VBLANK_reg_n_0),
.R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair14" *)
LUT2 #(
.INIT(4'h1))
\VTIMER[0]_i_1
(.I0(VTIMER[0]),
.I1(\VTIMER[2]_i_2_n_0 ),
.O(\VTIMER[0]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair14" *)
LUT3 #(
.INIT(8'h06))
\VTIMER[1]_i_1
(.I0(VTIMER[0]),
.I1(VTIMER[1]),
.I2(\VTIMER[2]_i_2_n_0 ),
.O(VTIMER_1[1]));
LUT4 #(
.INIT(16'h0078))
\VTIMER[2]_i_1
(.I0(VTIMER[1]),
.I1(VTIMER[0]),
.I2(VTIMER[2]),
.I3(\VTIMER[2]_i_2_n_0 ),
.O(VTIMER_1[2]));
LUT6 #(
.INIT(64'h0222000000000000))
\VTIMER[2]_i_2
(.I0(\VTIMER[2]_i_3_n_0 ),
.I1(VTIMER[5]),
.I2(VTIMER[3]),
.I3(VTIMER[4]),
.I4(VTIMER[1]),
.I5(VTIMER[2]),
.O(\VTIMER[2]_i_2_n_0 ));
LUT6 #(
.INIT(64'h0000000000400000))
\VTIMER[2]_i_3
(.I0(VTIMER[8]),
.I1(VTIMER[9]),
.I2(VTIMER[4]),
.I3(VTIMER[5]),
.I4(VTIMER[7]),
.I5(VTIMER[6]),
.O(\VTIMER[2]_i_3_n_0 ));
LUT4 #(
.INIT(16'h6AAA))
\VTIMER[3]_i_1
(.I0(VTIMER[3]),
.I1(VTIMER[2]),
.I2(VTIMER[1]),
.I3(VTIMER[0]),
.O(VTIMER_1[3]));
LUT6 #(
.INIT(64'h000000007FFF8000))
\VTIMER[4]_i_1
(.I0(VTIMER[0]),
.I1(VTIMER[1]),
.I2(VTIMER[2]),
.I3(VTIMER[3]),
.I4(VTIMER[4]),
.I5(\VTIMER[9]_i_3_n_0 ),
.O(VTIMER_1[4]));
LUT6 #(
.INIT(64'h6AAAAAAAAAAAAAAA))
\VTIMER[5]_i_1
(.I0(VTIMER[5]),
.I1(VTIMER[4]),
.I2(VTIMER[0]),
.I3(VTIMER[1]),
.I4(VTIMER[2]),
.I5(VTIMER[3]),
.O(\VTIMER[5]_i_1_n_0 ));
LUT2 #(
.INIT(4'h6))
\VTIMER[6]_i_1
(.I0(VTIMER[6]),
.I1(\VTIMER[9]_i_2_n_0 ),
.O(VTIMER_1[6]));
(* SOFT_HLUTNM = "soft_lutpair10" *)
LUT4 #(
.INIT(16'h1540))
\VTIMER[7]_i_1
(.I0(\VTIMER[9]_i_3_n_0 ),
.I1(\VTIMER[9]_i_2_n_0 ),
.I2(VTIMER[6]),
.I3(VTIMER[7]),
.O(VTIMER_1[7]));
(* SOFT_HLUTNM = "soft_lutpair10" *)
LUT4 #(
.INIT(16'h6AAA))
\VTIMER[8]_i_1
(.I0(VTIMER[8]),
.I1(VTIMER[7]),
.I2(VTIMER[6]),
.I3(\VTIMER[9]_i_2_n_0 ),
.O(VTIMER_1[8]));
LUT6 #(
.INIT(64'h000000006AAAAAAA))
\VTIMER[9]_i_1
(.I0(VTIMER[9]),
.I1(\VTIMER[9]_i_2_n_0 ),
.I2(VTIMER[6]),
.I3(VTIMER[7]),
.I4(VTIMER[8]),
.I5(\VTIMER[9]_i_3_n_0 ),
.O(VTIMER_1[9]));
LUT6 #(
.INIT(64'h8000000000000000))
\VTIMER[9]_i_2
(.I0(VTIMER[5]),
.I1(VTIMER[4]),
.I2(VTIMER[0]),
.I3(VTIMER[1]),
.I4(VTIMER[2]),
.I5(VTIMER[3]),
.O(\VTIMER[9]_i_2_n_0 ));
LUT5 #(
.INIT(32'h00000020))
\VTIMER[9]_i_3
(.I0(VTIMER[7]),
.I1(\VTIMER[9]_i_4_n_0 ),
.I2(VTIMER[9]),
.I3(VTIMER[8]),
.I4(\VTIMER[9]_i_5_n_0 ),
.O(\VTIMER[9]_i_3_n_0 ));
LUT4 #(
.INIT(16'hF8FF))
\VTIMER[9]_i_4
(.I0(VTIMER[6]),
.I1(VTIMER[7]),
.I2(VTIMER[5]),
.I3(VTIMER[4]),
.O(\VTIMER[9]_i_4_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFFFFF7F7F7))
\VTIMER[9]_i_5
(.I0(VTIMER[1]),
.I1(VTIMER[2]),
.I2(VTIMER[0]),
.I3(VTIMER[4]),
.I4(VTIMER[3]),
.I5(VTIMER[5]),
.O(\VTIMER[9]_i_5_n_0 ));
LUT2 #(
.INIT(4'hE))
VTIMER_EN_i_1
(.I0(INTERNAL_RST_reg),
.I1(\HTIMER[4]_i_2_n_0 ),
.O(VTIMER_EN_i_1_n_0));
FDRE VTIMER_EN_reg
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(VTIMER_EN_i_1_n_0),
.Q(VTIMER_EN),
.R(1'b0));
FDRE \VTIMER_reg[0]
(.C(ETH_CLK_OBUF),
.CE(VTIMER_EN),
.D(\VTIMER[0]_i_1_n_0 ),
.Q(VTIMER[0]),
.R(INTERNAL_RST_reg));
FDRE \VTIMER_reg[1]
(.C(ETH_CLK_OBUF),
.CE(VTIMER_EN),
.D(VTIMER_1[1]),
.Q(VTIMER[1]),
.R(INTERNAL_RST_reg));
FDRE \VTIMER_reg[2]
(.C(ETH_CLK_OBUF),
.CE(VTIMER_EN),
.D(VTIMER_1[2]),
.Q(VTIMER[2]),
.R(INTERNAL_RST_reg));
FDRE \VTIMER_reg[3]
(.C(ETH_CLK_OBUF),
.CE(VTIMER_EN),
.D(VTIMER_1[3]),
.Q(VTIMER[3]),
.R(INTERNAL_RST_reg));
FDRE \VTIMER_reg[4]
(.C(ETH_CLK_OBUF),
.CE(VTIMER_EN),
.D(VTIMER_1[4]),
.Q(VTIMER[4]),
.R(INTERNAL_RST_reg));
FDRE \VTIMER_reg[5]
(.C(ETH_CLK_OBUF),
.CE(VTIMER_EN),
.D(\VTIMER[5]_i_1_n_0 ),
.Q(VTIMER[5]),
.R(INTERNAL_RST_reg));
FDRE \VTIMER_reg[6]
(.C(ETH_CLK_OBUF),
.CE(VTIMER_EN),
.D(VTIMER_1[6]),
.Q(VTIMER[6]),
.R(INTERNAL_RST_reg));
FDRE \VTIMER_reg[7]
(.C(ETH_CLK_OBUF),
.CE(VTIMER_EN),
.D(VTIMER_1[7]),
.Q(VTIMER[7]),
.R(INTERNAL_RST_reg));
FDRE \VTIMER_reg[8]
(.C(ETH_CLK_OBUF),
.CE(VTIMER_EN),
.D(VTIMER_1[8]),
.Q(VTIMER[8]),
.R(INTERNAL_RST_reg));
FDRE \VTIMER_reg[9]
(.C(ETH_CLK_OBUF),
.CE(VTIMER_EN),
.D(VTIMER_1[9]),
.Q(VTIMER[9]),
.R(INTERNAL_RST_reg));
endmodule
|
module main_0
(IN1_STB,
OUT1_ACK,
output_rs232_out,
INTERNAL_RST_reg,
OUT1,
IN1_ACK,
ETH_CLK_OBUF,
OUT1_STB);
output IN1_STB;
output OUT1_ACK;
output [7:0]output_rs232_out;
input INTERNAL_RST_reg;
input [7:0]OUT1;
input IN1_ACK;
input ETH_CLK_OBUF;
input OUT1_STB;
wire ETH_CLK_OBUF;
wire IN1_ACK;
wire IN1_STB;
wire INTERNAL_RST_reg;
wire [7:0]OUT1;
wire OUT1_ACK;
wire OUT1_STB;
wire [3:0]address_a;
wire [3:0]address_a_2;
wire [3:0]address_b_2;
wire [3:0]address_z;
wire [3:0]address_z_2;
wire [3:0]address_z_3;
wire \address_z_3[3]_i_1_n_0 ;
wire data10;
wire data12;
wire [16:1]data2;
wire data4;
wire [31:0]data5;
wire data6;
wire [31:20]data7;
wire instruction0;
wire [31:0]load_data;
wire memory_reg_0_i_1_n_0;
wire memory_reg_0_i_2_n_0;
wire memory_reg_1_ENARDEN_cooolgate_en_sig_1;
wire memory_reg_2_ENARDEN_cooolgate_en_sig_2;
wire memory_reg_3_ENARDEN_cooolgate_en_sig_3;
wire memory_reg_4_ENARDEN_cooolgate_en_sig_4;
wire memory_reg_5_ENARDEN_cooolgate_en_sig_5;
wire memory_reg_6_ENARDEN_cooolgate_en_sig_6;
wire memory_reg_7_ENARDEN_cooolgate_en_sig_7;
wire [4:0]opcode;
wire [4:0]opcode_2;
wire opcode_20;
wire operand_a1;
wire operand_b1;
wire out0;
wire [7:0]output_rs232_out;
wire \program_counter[0]_i_2_n_0 ;
wire \program_counter[0]_i_3_n_0 ;
wire \program_counter[0]_i_4_n_0 ;
wire \program_counter[10]_i_2_n_0 ;
wire \program_counter[10]_i_3_n_0 ;
wire \program_counter[10]_i_4_n_0 ;
wire \program_counter[11]_i_2_n_0 ;
wire \program_counter[11]_i_3_n_0 ;
wire \program_counter[11]_i_4_n_0 ;
wire \program_counter[12]_i_3_n_0 ;
wire \program_counter[12]_i_4_n_0 ;
wire \program_counter[12]_i_5_n_0 ;
wire \program_counter[13]_i_2_n_0 ;
wire \program_counter[13]_i_3_n_0 ;
wire \program_counter[13]_i_4_n_0 ;
wire \program_counter[14]_i_2_n_0 ;
wire \program_counter[14]_i_3_n_0 ;
wire \program_counter[14]_i_4_n_0 ;
wire \program_counter[15]_i_13_n_0 ;
wire \program_counter[15]_i_14_n_0 ;
wire \program_counter[15]_i_15_n_0 ;
wire \program_counter[15]_i_16_n_0 ;
wire \program_counter[15]_i_17_n_0 ;
wire \program_counter[15]_i_18_n_0 ;
wire \program_counter[15]_i_19_n_0 ;
wire \program_counter[15]_i_20_n_0 ;
wire \program_counter[15]_i_21_n_0 ;
wire \program_counter[15]_i_3_n_0 ;
wire \program_counter[15]_i_5_n_0 ;
wire \program_counter[15]_i_6_n_0 ;
wire \program_counter[15]_i_7_n_0 ;
wire \program_counter[15]_i_8_n_0 ;
wire \program_counter[15]_i_9_n_0 ;
wire \program_counter[1]_i_2_n_0 ;
wire \program_counter[1]_i_3_n_0 ;
wire \program_counter[1]_i_4_n_0 ;
wire \program_counter[2]_i_2_n_0 ;
wire \program_counter[2]_i_3_n_0 ;
wire \program_counter[2]_i_4_n_0 ;
wire \program_counter[3]_i_2_n_0 ;
wire \program_counter[3]_i_3_n_0 ;
wire \program_counter[3]_i_4_n_0 ;
wire \program_counter[4]_i_3_n_0 ;
wire \program_counter[4]_i_4_n_0 ;
wire \program_counter[4]_i_5_n_0 ;
wire \program_counter[5]_i_2_n_0 ;
wire \program_counter[5]_i_3_n_0 ;
wire \program_counter[5]_i_4_n_0 ;
wire \program_counter[6]_i_2_n_0 ;
wire \program_counter[6]_i_3_n_0 ;
wire \program_counter[6]_i_4_n_0 ;
wire \program_counter[7]_i_2_n_0 ;
wire \program_counter[7]_i_3_n_0 ;
wire \program_counter[7]_i_4_n_0 ;
wire \program_counter[8]_i_3_n_0 ;
wire \program_counter[8]_i_4_n_0 ;
wire \program_counter[8]_i_5_n_0 ;
wire \program_counter[9]_i_2_n_0 ;
wire \program_counter[9]_i_3_n_0 ;
wire \program_counter[9]_i_4_n_0 ;
wire [15:0]program_counter_1;
wire [15:0]program_counter_2;
wire \program_counter_reg[12]_i_2_n_0 ;
wire \program_counter_reg[12]_i_2_n_4 ;
wire \program_counter_reg[12]_i_2_n_5 ;
wire \program_counter_reg[12]_i_2_n_6 ;
wire \program_counter_reg[12]_i_2_n_7 ;
wire \program_counter_reg[15]_i_4_n_5 ;
wire \program_counter_reg[15]_i_4_n_6 ;
wire \program_counter_reg[15]_i_4_n_7 ;
wire \program_counter_reg[4]_i_2_n_0 ;
wire \program_counter_reg[4]_i_2_n_4 ;
wire \program_counter_reg[4]_i_2_n_5 ;
wire \program_counter_reg[4]_i_2_n_6 ;
wire \program_counter_reg[4]_i_2_n_7 ;
wire \program_counter_reg[8]_i_2_n_0 ;
wire \program_counter_reg[8]_i_2_n_4 ;
wire \program_counter_reg[8]_i_2_n_5 ;
wire \program_counter_reg[8]_i_2_n_6 ;
wire \program_counter_reg[8]_i_2_n_7 ;
wire \program_counter_reg_n_0_[0] ;
wire \program_counter_reg_n_0_[10] ;
wire \program_counter_reg_n_0_[11] ;
wire \program_counter_reg_n_0_[12] ;
wire \program_counter_reg_n_0_[13] ;
wire \program_counter_reg_n_0_[14] ;
wire \program_counter_reg_n_0_[15] ;
wire \program_counter_reg_n_0_[1] ;
wire \program_counter_reg_n_0_[2] ;
wire \program_counter_reg_n_0_[3] ;
wire \program_counter_reg_n_0_[4] ;
wire \program_counter_reg_n_0_[5] ;
wire \program_counter_reg_n_0_[6] ;
wire \program_counter_reg_n_0_[7] ;
wire \program_counter_reg_n_0_[8] ;
wire \program_counter_reg_n_0_[9] ;
wire program_counter_reg_rep_0_REGCEAREGCE_cooolgate_en_sig_11;
wire program_counter_reg_rep_0_i_10_n_0;
wire program_counter_reg_rep_0_i_11_n_0;
wire program_counter_reg_rep_0_i_12_n_0;
wire program_counter_reg_rep_0_i_13_n_0;
wire program_counter_reg_rep_0_i_14_n_0;
wire program_counter_reg_rep_0_i_15_n_0;
wire program_counter_reg_rep_0_i_16_n_0;
wire program_counter_reg_rep_0_i_17_n_0;
wire program_counter_reg_rep_0_i_18_n_0;
wire program_counter_reg_rep_0_i_19_n_0;
wire program_counter_reg_rep_0_i_1_n_0;
wire program_counter_reg_rep_0_i_20_n_0;
wire program_counter_reg_rep_0_i_21_n_0;
wire program_counter_reg_rep_0_i_22_n_0;
wire program_counter_reg_rep_0_i_23_n_0;
wire program_counter_reg_rep_0_i_24_n_0;
wire program_counter_reg_rep_0_i_25_n_0;
wire program_counter_reg_rep_0_i_26_n_0;
wire program_counter_reg_rep_0_i_27_n_0;
wire program_counter_reg_rep_0_i_2_n_0;
wire program_counter_reg_rep_0_i_3_n_0;
wire program_counter_reg_rep_0_i_4_n_0;
wire program_counter_reg_rep_0_i_5_n_0;
wire program_counter_reg_rep_0_i_6_n_0;
wire program_counter_reg_rep_0_i_7_n_0;
wire program_counter_reg_rep_0_i_8_n_0;
wire program_counter_reg_rep_0_i_9_n_0;
wire program_counter_reg_rep_0_n_32;
wire program_counter_reg_rep_0_n_33;
wire program_counter_reg_rep_0_n_34;
wire program_counter_reg_rep_0_n_35;
wire program_counter_reg_rep_1_n_32;
wire program_counter_reg_rep_1_n_33;
wire program_counter_reg_rep_1_n_34;
wire program_counter_reg_rep_1_n_35;
wire program_counter_reg_rep_2_n_32;
wire program_counter_reg_rep_2_n_33;
wire program_counter_reg_rep_2_n_34;
wire program_counter_reg_rep_2_n_35;
wire program_counter_reg_rep_3_n_32;
wire program_counter_reg_rep_3_n_33;
wire program_counter_reg_rep_3_n_34;
wire program_counter_reg_rep_3_n_35;
wire [31:0]read_input;
wire \read_input[0]_i_1_n_0 ;
wire \read_input[10]_i_1_n_0 ;
wire \read_input[11]_i_1_n_0 ;
wire \read_input[12]_i_1_n_0 ;
wire \read_input[13]_i_1_n_0 ;
wire \read_input[14]_i_1_n_0 ;
wire \read_input[15]_i_1_n_0 ;
wire \read_input[16]_i_1_n_0 ;
wire \read_input[17]_i_1_n_0 ;
wire \read_input[18]_i_1_n_0 ;
wire \read_input[19]_i_1_n_0 ;
wire \read_input[1]_i_1_n_0 ;
wire \read_input[20]_i_1_n_0 ;
wire \read_input[21]_i_1_n_0 ;
wire \read_input[22]_i_1_n_0 ;
wire \read_input[23]_i_1_n_0 ;
wire \read_input[24]_i_1_n_0 ;
wire \read_input[25]_i_1_n_0 ;
wire \read_input[26]_i_1_n_0 ;
wire \read_input[27]_i_1_n_0 ;
wire \read_input[28]_i_1_n_0 ;
wire \read_input[29]_i_1_n_0 ;
wire \read_input[2]_i_1_n_0 ;
wire \read_input[30]_i_1_n_0 ;
wire \read_input[31]_i_1_n_0 ;
wire \read_input[31]_i_2_n_0 ;
wire \read_input[31]_i_3_n_0 ;
wire \read_input[31]_i_4_n_0 ;
wire \read_input[31]_i_5_n_0 ;
wire \read_input[3]_i_1_n_0 ;
wire \read_input[4]_i_1_n_0 ;
wire \read_input[5]_i_1_n_0 ;
wire \read_input[6]_i_1_n_0 ;
wire \read_input[7]_i_1_n_0 ;
wire \read_input[8]_i_1_n_0 ;
wire \read_input[9]_i_1_n_0 ;
wire [31:0]register_a;
wire [31:0]register_b;
wire [31:0]result;
wire \result[0]_i_100_n_0 ;
wire \result[0]_i_101_n_0 ;
wire \result[0]_i_102_n_0 ;
wire \result[0]_i_103_n_0 ;
wire \result[0]_i_104_n_0 ;
wire \result[0]_i_105_n_0 ;
wire \result[0]_i_106_n_0 ;
wire \result[0]_i_107_n_0 ;
wire \result[0]_i_108_n_0 ;
wire \result[0]_i_109_n_0 ;
wire \result[0]_i_110_n_0 ;
wire \result[0]_i_111_n_0 ;
wire \result[0]_i_112_n_0 ;
wire \result[0]_i_113_n_0 ;
wire \result[0]_i_114_n_0 ;
wire \result[0]_i_115_n_0 ;
wire \result[0]_i_116_n_0 ;
wire \result[0]_i_117_n_0 ;
wire \result[0]_i_118_n_0 ;
wire \result[0]_i_119_n_0 ;
wire \result[0]_i_11_n_0 ;
wire \result[0]_i_120_n_0 ;
wire \result[0]_i_15_n_0 ;
wire \result[0]_i_16_n_0 ;
wire \result[0]_i_17_n_0 ;
wire \result[0]_i_18_n_0 ;
wire \result[0]_i_19_n_0 ;
wire \result[0]_i_1_n_0 ;
wire \result[0]_i_20_n_0 ;
wire \result[0]_i_21_n_0 ;
wire \result[0]_i_22_n_0 ;
wire \result[0]_i_24_n_0 ;
wire \result[0]_i_25_n_0 ;
wire \result[0]_i_26_n_0 ;
wire \result[0]_i_27_n_0 ;
wire \result[0]_i_28_n_0 ;
wire \result[0]_i_2_n_0 ;
wire \result[0]_i_30_n_0 ;
wire \result[0]_i_31_n_0 ;
wire \result[0]_i_32_n_0 ;
wire \result[0]_i_34_n_0 ;
wire \result[0]_i_35_n_0 ;
wire \result[0]_i_36_n_0 ;
wire \result[0]_i_37_n_0 ;
wire \result[0]_i_39_n_0 ;
wire \result[0]_i_3_n_0 ;
wire \result[0]_i_40_n_0 ;
wire \result[0]_i_41_n_0 ;
wire \result[0]_i_42_n_0 ;
wire \result[0]_i_43_n_0 ;
wire \result[0]_i_44_n_0 ;
wire \result[0]_i_45_n_0 ;
wire \result[0]_i_46_n_0 ;
wire \result[0]_i_47_n_0 ;
wire \result[0]_i_48_n_0 ;
wire \result[0]_i_49_n_0 ;
wire \result[0]_i_4_n_0 ;
wire \result[0]_i_50_n_0 ;
wire \result[0]_i_51_n_0 ;
wire \result[0]_i_53_n_0 ;
wire \result[0]_i_54_n_0 ;
wire \result[0]_i_55_n_0 ;
wire \result[0]_i_56_n_0 ;
wire \result[0]_i_58_n_0 ;
wire \result[0]_i_59_n_0 ;
wire \result[0]_i_5_n_0 ;
wire \result[0]_i_60_n_0 ;
wire \result[0]_i_61_n_0 ;
wire \result[0]_i_62_n_0 ;
wire \result[0]_i_63_n_0 ;
wire \result[0]_i_65_n_0 ;
wire \result[0]_i_66_n_0 ;
wire \result[0]_i_67_n_0 ;
wire \result[0]_i_68_n_0 ;
wire \result[0]_i_6_n_0 ;
wire \result[0]_i_70_n_0 ;
wire \result[0]_i_71_n_0 ;
wire \result[0]_i_72_n_0 ;
wire \result[0]_i_73_n_0 ;
wire \result[0]_i_74_n_0 ;
wire \result[0]_i_75_n_0 ;
wire \result[0]_i_76_n_0 ;
wire \result[0]_i_77_n_0 ;
wire \result[0]_i_78_n_0 ;
wire \result[0]_i_79_n_0 ;
wire \result[0]_i_80_n_0 ;
wire \result[0]_i_81_n_0 ;
wire \result[0]_i_83_n_0 ;
wire \result[0]_i_84_n_0 ;
wire \result[0]_i_85_n_0 ;
wire \result[0]_i_86_n_0 ;
wire \result[0]_i_87_n_0 ;
wire \result[0]_i_88_n_0 ;
wire \result[0]_i_89_n_0 ;
wire \result[0]_i_8_n_0 ;
wire \result[0]_i_90_n_0 ;
wire \result[0]_i_91_n_0 ;
wire \result[0]_i_92_n_0 ;
wire \result[0]_i_93_n_0 ;
wire \result[0]_i_94_n_0 ;
wire \result[0]_i_96_n_0 ;
wire \result[0]_i_97_n_0 ;
wire \result[0]_i_98_n_0 ;
wire \result[0]_i_99_n_0 ;
wire \result[0]_i_9_n_0 ;
wire \result[10]_i_1_n_0 ;
wire \result[10]_i_2_n_0 ;
wire \result[10]_i_3_n_0 ;
wire \result[10]_i_4_n_0 ;
wire \result[10]_i_5_n_0 ;
wire \result[10]_i_6_n_0 ;
wire \result[10]_i_7_n_0 ;
wire \result[11]_i_10_n_0 ;
wire \result[11]_i_11_n_0 ;
wire \result[11]_i_12_n_0 ;
wire \result[11]_i_1_n_0 ;
wire \result[11]_i_2_n_0 ;
wire \result[11]_i_3_n_0 ;
wire \result[11]_i_4_n_0 ;
wire \result[11]_i_5_n_0 ;
wire \result[11]_i_6_n_0 ;
wire \result[11]_i_7_n_0 ;
wire \result[11]_i_9_n_0 ;
wire \result[12]_i_1_n_0 ;
wire \result[12]_i_2_n_0 ;
wire \result[12]_i_3_n_0 ;
wire \result[12]_i_4_n_0 ;
wire \result[12]_i_5_n_0 ;
wire \result[12]_i_6_n_0 ;
wire \result[12]_i_7_n_0 ;
wire \result[13]_i_1_n_0 ;
wire \result[13]_i_2_n_0 ;
wire \result[13]_i_3_n_0 ;
wire \result[13]_i_4_n_0 ;
wire \result[13]_i_5_n_0 ;
wire \result[13]_i_6_n_0 ;
wire \result[13]_i_7_n_0 ;
wire \result[13]_i_8_n_0 ;
wire \result[14]_i_1_n_0 ;
wire \result[14]_i_2_n_0 ;
wire \result[14]_i_3_n_0 ;
wire \result[14]_i_4_n_0 ;
wire \result[14]_i_5_n_0 ;
wire \result[14]_i_6_n_0 ;
wire \result[14]_i_7_n_0 ;
wire \result[14]_i_8_n_0 ;
wire \result[15]_i_12_n_0 ;
wire \result[15]_i_13_n_0 ;
wire \result[15]_i_14_n_0 ;
wire \result[15]_i_15_n_0 ;
wire \result[15]_i_17_n_0 ;
wire \result[15]_i_18_n_0 ;
wire \result[15]_i_19_n_0 ;
wire \result[15]_i_1_n_0 ;
wire \result[15]_i_20_n_0 ;
wire \result[15]_i_21_n_0 ;
wire \result[15]_i_22_n_0 ;
wire \result[15]_i_23_n_0 ;
wire \result[15]_i_24_n_0 ;
wire \result[15]_i_25_n_0 ;
wire \result[15]_i_26_n_0 ;
wire \result[15]_i_27_n_0 ;
wire \result[15]_i_28_n_0 ;
wire \result[15]_i_29_n_0 ;
wire \result[15]_i_2_n_0 ;
wire \result[15]_i_30_n_0 ;
wire \result[15]_i_31_n_0 ;
wire \result[15]_i_32_n_0 ;
wire \result[15]_i_3_n_0 ;
wire \result[15]_i_4_n_0 ;
wire \result[15]_i_5_n_0 ;
wire \result[15]_i_6_n_0 ;
wire \result[15]_i_9_n_0 ;
wire \result[16]_i_1_n_0 ;
wire \result[16]_i_2_n_0 ;
wire \result[16]_i_3_n_0 ;
wire \result[16]_i_4_n_0 ;
wire \result[16]_i_5_n_0 ;
wire \result[16]_i_6_n_0 ;
wire \result[16]_i_8_n_0 ;
wire \result[16]_i_9_n_0 ;
wire \result[17]_i_1_n_0 ;
wire \result[17]_i_2_n_0 ;
wire \result[17]_i_3_n_0 ;
wire \result[17]_i_4_n_0 ;
wire \result[17]_i_5_n_0 ;
wire \result[17]_i_6_n_0 ;
wire \result[17]_i_7_n_0 ;
wire \result[17]_i_8_n_0 ;
wire \result[18]_i_1_n_0 ;
wire \result[18]_i_2_n_0 ;
wire \result[18]_i_3_n_0 ;
wire \result[18]_i_4_n_0 ;
wire \result[18]_i_5_n_0 ;
wire \result[18]_i_6_n_0 ;
wire \result[18]_i_7_n_0 ;
wire \result[18]_i_8_n_0 ;
wire \result[19]_i_10_n_0 ;
wire \result[19]_i_12_n_0 ;
wire \result[19]_i_13_n_0 ;
wire \result[19]_i_14_n_0 ;
wire \result[19]_i_15_n_0 ;
wire \result[19]_i_16_n_0 ;
wire \result[19]_i_17_n_0 ;
wire \result[19]_i_18_n_0 ;
wire \result[19]_i_19_n_0 ;
wire \result[19]_i_1_n_0 ;
wire \result[19]_i_20_n_0 ;
wire \result[19]_i_21_n_0 ;
wire \result[19]_i_22_n_0 ;
wire \result[19]_i_23_n_0 ;
wire \result[19]_i_2_n_0 ;
wire \result[19]_i_3_n_0 ;
wire \result[19]_i_4_n_0 ;
wire \result[19]_i_5_n_0 ;
wire \result[19]_i_8_n_0 ;
wire \result[19]_i_9_n_0 ;
wire \result[1]_i_10_n_0 ;
wire \result[1]_i_11_n_0 ;
wire \result[1]_i_12_n_0 ;
wire \result[1]_i_13_n_0 ;
wire \result[1]_i_1_n_0 ;
wire \result[1]_i_2_n_0 ;
wire \result[1]_i_3_n_0 ;
wire \result[1]_i_4_n_0 ;
wire \result[1]_i_5_n_0 ;
wire \result[1]_i_7_n_0 ;
wire \result[1]_i_8_n_0 ;
wire \result[1]_i_9_n_0 ;
wire \result[20]_i_1_n_0 ;
wire \result[20]_i_2_n_0 ;
wire \result[20]_i_3_n_0 ;
wire \result[20]_i_4_n_0 ;
wire \result[20]_i_5_n_0 ;
wire \result[20]_i_6_n_0 ;
wire \result[20]_i_7_n_0 ;
wire \result[20]_i_8_n_0 ;
wire \result[21]_i_1_n_0 ;
wire \result[21]_i_2_n_0 ;
wire \result[21]_i_3_n_0 ;
wire \result[21]_i_4_n_0 ;
wire \result[21]_i_5_n_0 ;
wire \result[21]_i_6_n_0 ;
wire \result[21]_i_7_n_0 ;
wire \result[21]_i_8_n_0 ;
wire \result[22]_i_1_n_0 ;
wire \result[22]_i_2_n_0 ;
wire \result[22]_i_3_n_0 ;
wire \result[22]_i_4_n_0 ;
wire \result[22]_i_5_n_0 ;
wire \result[22]_i_6_n_0 ;
wire \result[22]_i_7_n_0 ;
wire \result[22]_i_8_n_0 ;
wire \result[23]_i_11_n_0 ;
wire \result[23]_i_12_n_0 ;
wire \result[23]_i_13_n_0 ;
wire \result[23]_i_14_n_0 ;
wire \result[23]_i_15_n_0 ;
wire \result[23]_i_16_n_0 ;
wire \result[23]_i_17_n_0 ;
wire \result[23]_i_18_n_0 ;
wire \result[23]_i_19_n_0 ;
wire \result[23]_i_1_n_0 ;
wire \result[23]_i_20_n_0 ;
wire \result[23]_i_21_n_0 ;
wire \result[23]_i_22_n_0 ;
wire \result[23]_i_23_n_0 ;
wire \result[23]_i_2_n_0 ;
wire \result[23]_i_3_n_0 ;
wire \result[23]_i_4_n_0 ;
wire \result[23]_i_5_n_0 ;
wire \result[23]_i_6_n_0 ;
wire \result[23]_i_9_n_0 ;
wire \result[24]_i_1_n_0 ;
wire \result[24]_i_2_n_0 ;
wire \result[24]_i_3_n_0 ;
wire \result[24]_i_4_n_0 ;
wire \result[24]_i_5_n_0 ;
wire \result[24]_i_6_n_0 ;
wire \result[24]_i_7_n_0 ;
wire \result[24]_i_8_n_0 ;
wire \result[25]_i_1_n_0 ;
wire \result[25]_i_2_n_0 ;
wire \result[25]_i_3_n_0 ;
wire \result[25]_i_4_n_0 ;
wire \result[25]_i_5_n_0 ;
wire \result[25]_i_6_n_0 ;
wire \result[25]_i_7_n_0 ;
wire \result[25]_i_8_n_0 ;
wire \result[26]_i_1_n_0 ;
wire \result[26]_i_2_n_0 ;
wire \result[26]_i_3_n_0 ;
wire \result[26]_i_4_n_0 ;
wire \result[26]_i_5_n_0 ;
wire \result[26]_i_6_n_0 ;
wire \result[26]_i_7_n_0 ;
wire \result[26]_i_8_n_0 ;
wire \result[27]_i_12_n_0 ;
wire \result[27]_i_13_n_0 ;
wire \result[27]_i_14_n_0 ;
wire \result[27]_i_15_n_0 ;
wire \result[27]_i_16_n_0 ;
wire \result[27]_i_17_n_0 ;
wire \result[27]_i_18_n_0 ;
wire \result[27]_i_19_n_0 ;
wire \result[27]_i_1_n_0 ;
wire \result[27]_i_20_n_0 ;
wire \result[27]_i_21_n_0 ;
wire \result[27]_i_22_n_0 ;
wire \result[27]_i_23_n_0 ;
wire \result[27]_i_24_n_0 ;
wire \result[27]_i_25_n_0 ;
wire \result[27]_i_26_n_0 ;
wire \result[27]_i_27_n_0 ;
wire \result[27]_i_28_n_0 ;
wire \result[27]_i_29_n_0 ;
wire \result[27]_i_2_n_0 ;
wire \result[27]_i_30_n_0 ;
wire \result[27]_i_31_n_0 ;
wire \result[27]_i_32_n_0 ;
wire \result[27]_i_33_n_0 ;
wire \result[27]_i_34_n_0 ;
wire \result[27]_i_3_n_0 ;
wire \result[27]_i_4_n_0 ;
wire \result[27]_i_5_n_0 ;
wire \result[27]_i_6_n_0 ;
wire \result[27]_i_7_n_0 ;
wire \result[27]_i_8_n_0 ;
wire \result[27]_i_9_n_0 ;
wire \result[28]_i_10_n_0 ;
wire \result[28]_i_1_n_0 ;
wire \result[28]_i_2_n_0 ;
wire \result[28]_i_4_n_0 ;
wire \result[28]_i_5_n_0 ;
wire \result[28]_i_6_n_0 ;
wire \result[28]_i_7_n_0 ;
wire \result[28]_i_9_n_0 ;
wire \result[29]_i_10_n_0 ;
wire \result[29]_i_11_n_0 ;
wire \result[29]_i_1_n_0 ;
wire \result[29]_i_2_n_0 ;
wire \result[29]_i_4_n_0 ;
wire \result[29]_i_5_n_0 ;
wire \result[29]_i_6_n_0 ;
wire \result[29]_i_7_n_0 ;
wire \result[29]_i_8_n_0 ;
wire \result[29]_i_9_n_0 ;
wire \result[2]_i_1_n_0 ;
wire \result[2]_i_2_n_0 ;
wire \result[2]_i_3_n_0 ;
wire \result[2]_i_4_n_0 ;
wire \result[2]_i_5_n_0 ;
wire \result[2]_i_6_n_0 ;
wire \result[2]_i_7_n_0 ;
wire \result[30]_i_10_n_0 ;
wire \result[30]_i_11_n_0 ;
wire \result[30]_i_1_n_0 ;
wire \result[30]_i_2_n_0 ;
wire \result[30]_i_4_n_0 ;
wire \result[30]_i_5_n_0 ;
wire \result[30]_i_6_n_0 ;
wire \result[30]_i_7_n_0 ;
wire \result[30]_i_8_n_0 ;
wire \result[30]_i_9_n_0 ;
wire \result[31]_i_10_n_0 ;
wire \result[31]_i_11_n_0 ;
wire \result[31]_i_12_n_0 ;
wire \result[31]_i_13_n_0 ;
wire \result[31]_i_17_n_0 ;
wire \result[31]_i_18_n_0 ;
wire \result[31]_i_19_n_0 ;
wire \result[31]_i_1_n_0 ;
wire \result[31]_i_20_n_0 ;
wire \result[31]_i_21_n_0 ;
wire \result[31]_i_22_n_0 ;
wire \result[31]_i_23_n_0 ;
wire \result[31]_i_24_n_0 ;
wire \result[31]_i_25_n_0 ;
wire \result[31]_i_26_n_0 ;
wire \result[31]_i_27_n_0 ;
wire \result[31]_i_28_n_0 ;
wire \result[31]_i_29_n_0 ;
wire \result[31]_i_2_n_0 ;
wire \result[31]_i_30_n_0 ;
wire \result[31]_i_31_n_0 ;
wire \result[31]_i_32_n_0 ;
wire \result[31]_i_33_n_0 ;
wire \result[31]_i_34_n_0 ;
wire \result[31]_i_35_n_0 ;
wire \result[31]_i_36_n_0 ;
wire \result[31]_i_37_n_0 ;
wire \result[31]_i_38_n_0 ;
wire \result[31]_i_39_n_0 ;
wire \result[31]_i_3_n_0 ;
wire \result[31]_i_40_n_0 ;
wire \result[31]_i_41_n_0 ;
wire \result[31]_i_4_n_0 ;
wire \result[31]_i_5_n_0 ;
wire \result[31]_i_7_n_0 ;
wire \result[31]_i_8_n_0 ;
wire \result[3]_i_10_n_0 ;
wire \result[3]_i_11_n_0 ;
wire \result[3]_i_12_n_0 ;
wire \result[3]_i_13_n_0 ;
wire \result[3]_i_14_n_0 ;
wire \result[3]_i_15_n_0 ;
wire \result[3]_i_16_n_0 ;
wire \result[3]_i_17_n_0 ;
wire \result[3]_i_1_n_0 ;
wire \result[3]_i_2_n_0 ;
wire \result[3]_i_3_n_0 ;
wire \result[3]_i_4_n_0 ;
wire \result[3]_i_5_n_0 ;
wire \result[3]_i_6_n_0 ;
wire \result[3]_i_7_n_0 ;
wire \result[4]_i_1_n_0 ;
wire \result[4]_i_2_n_0 ;
wire \result[4]_i_3_n_0 ;
wire \result[4]_i_4_n_0 ;
wire \result[4]_i_5_n_0 ;
wire \result[4]_i_6_n_0 ;
wire \result[4]_i_7_n_0 ;
wire \result[5]_i_1_n_0 ;
wire \result[5]_i_2_n_0 ;
wire \result[5]_i_3_n_0 ;
wire \result[5]_i_4_n_0 ;
wire \result[5]_i_5_n_0 ;
wire \result[5]_i_6_n_0 ;
wire \result[5]_i_7_n_0 ;
wire \result[6]_i_1_n_0 ;
wire \result[6]_i_2_n_0 ;
wire \result[6]_i_3_n_0 ;
wire \result[6]_i_4_n_0 ;
wire \result[6]_i_5_n_0 ;
wire \result[6]_i_6_n_0 ;
wire \result[6]_i_7_n_0 ;
wire \result[7]_i_12_n_0 ;
wire \result[7]_i_13_n_0 ;
wire \result[7]_i_14_n_0 ;
wire \result[7]_i_15_n_0 ;
wire \result[7]_i_16_n_0 ;
wire \result[7]_i_17_n_0 ;
wire \result[7]_i_18_n_0 ;
wire \result[7]_i_19_n_0 ;
wire \result[7]_i_1_n_0 ;
wire \result[7]_i_20_n_0 ;
wire \result[7]_i_21_n_0 ;
wire \result[7]_i_22_n_0 ;
wire \result[7]_i_23_n_0 ;
wire \result[7]_i_2_n_0 ;
wire \result[7]_i_3_n_0 ;
wire \result[7]_i_4_n_0 ;
wire \result[7]_i_5_n_0 ;
wire \result[7]_i_6_n_0 ;
wire \result[7]_i_7_n_0 ;
wire \result[7]_i_8_n_0 ;
wire \result[8]_i_1_n_0 ;
wire \result[8]_i_2_n_0 ;
wire \result[8]_i_3_n_0 ;
wire \result[8]_i_4_n_0 ;
wire \result[8]_i_5_n_0 ;
wire \result[8]_i_6_n_0 ;
wire \result[8]_i_7_n_0 ;
wire \result[9]_i_1_n_0 ;
wire \result[9]_i_2_n_0 ;
wire \result[9]_i_3_n_0 ;
wire \result[9]_i_4_n_0 ;
wire \result[9]_i_5_n_0 ;
wire \result[9]_i_6_n_0 ;
wire \result[9]_i_7_n_0 ;
wire \result_reg[0]_i_14_n_0 ;
wire \result_reg[0]_i_23_n_0 ;
wire \result_reg[0]_i_29_n_0 ;
wire \result_reg[0]_i_33_n_0 ;
wire \result_reg[0]_i_38_n_0 ;
wire \result_reg[0]_i_52_n_0 ;
wire \result_reg[0]_i_57_n_0 ;
wire \result_reg[0]_i_64_n_0 ;
wire \result_reg[0]_i_69_n_0 ;
wire \result_reg[0]_i_82_n_0 ;
wire \result_reg[0]_i_95_n_0 ;
wire \result_reg[11]_i_8_n_0 ;
wire \result_reg[11]_i_8_n_4 ;
wire \result_reg[11]_i_8_n_5 ;
wire \result_reg[11]_i_8_n_6 ;
wire \result_reg[11]_i_8_n_7 ;
wire \result_reg[15]_i_10_n_0 ;
wire \result_reg[15]_i_10_n_4 ;
wire \result_reg[15]_i_10_n_5 ;
wire \result_reg[15]_i_10_n_6 ;
wire \result_reg[15]_i_10_n_7 ;
wire \result_reg[15]_i_11_n_0 ;
wire \result_reg[15]_i_16_n_0 ;
wire \result_reg[15]_i_16_n_4 ;
wire \result_reg[15]_i_16_n_5 ;
wire \result_reg[15]_i_16_n_6 ;
wire \result_reg[15]_i_16_n_7 ;
wire \result_reg[15]_i_7_n_0 ;
wire \result_reg[15]_i_8_n_0 ;
wire \result_reg[15]_i_8_n_4 ;
wire \result_reg[15]_i_8_n_5 ;
wire \result_reg[15]_i_8_n_6 ;
wire \result_reg[15]_i_8_n_7 ;
wire \result_reg[16]_i_10_n_0 ;
wire \result_reg[19]_i_11_n_0 ;
wire \result_reg[19]_i_11_n_4 ;
wire \result_reg[19]_i_11_n_5 ;
wire \result_reg[19]_i_11_n_6 ;
wire \result_reg[19]_i_11_n_7 ;
wire \result_reg[19]_i_6_n_0 ;
wire \result_reg[19]_i_7_n_0 ;
wire \result_reg[19]_i_7_n_4 ;
wire \result_reg[19]_i_7_n_5 ;
wire \result_reg[19]_i_7_n_6 ;
wire \result_reg[19]_i_7_n_7 ;
wire \result_reg[1]_i_6_n_0 ;
wire \result_reg[1]_i_6_n_4 ;
wire \result_reg[1]_i_6_n_5 ;
wire \result_reg[1]_i_6_n_6 ;
wire \result_reg[1]_i_6_n_7 ;
wire \result_reg[23]_i_10_n_0 ;
wire \result_reg[23]_i_10_n_4 ;
wire \result_reg[23]_i_10_n_5 ;
wire \result_reg[23]_i_10_n_6 ;
wire \result_reg[23]_i_10_n_7 ;
wire \result_reg[23]_i_7_n_0 ;
wire \result_reg[23]_i_7_n_4 ;
wire \result_reg[23]_i_7_n_5 ;
wire \result_reg[23]_i_7_n_6 ;
wire \result_reg[23]_i_7_n_7 ;
wire \result_reg[23]_i_8_n_0 ;
wire \result_reg[27]_i_10_n_0 ;
wire \result_reg[27]_i_10_n_4 ;
wire \result_reg[27]_i_10_n_5 ;
wire \result_reg[27]_i_10_n_6 ;
wire \result_reg[27]_i_10_n_7 ;
wire \result_reg[27]_i_11_n_0 ;
wire \result_reg[28]_i_3_n_0 ;
wire \result_reg[29]_i_3_n_0 ;
wire \result_reg[30]_i_3_n_0 ;
wire \result_reg[31]_i_15_n_4 ;
wire \result_reg[31]_i_15_n_5 ;
wire \result_reg[31]_i_15_n_6 ;
wire \result_reg[31]_i_15_n_7 ;
wire \result_reg[31]_i_16_n_0 ;
wire \result_reg[31]_i_16_n_4 ;
wire \result_reg[31]_i_16_n_5 ;
wire \result_reg[31]_i_16_n_6 ;
wire \result_reg[31]_i_16_n_7 ;
wire \result_reg[31]_i_6_n_0 ;
wire \result_reg[31]_i_9_n_4 ;
wire \result_reg[31]_i_9_n_5 ;
wire \result_reg[31]_i_9_n_6 ;
wire \result_reg[31]_i_9_n_7 ;
wire \result_reg[3]_i_8_n_0 ;
wire \result_reg[3]_i_9_n_0 ;
wire \result_reg[3]_i_9_n_4 ;
wire \result_reg[3]_i_9_n_5 ;
wire \result_reg[3]_i_9_n_6 ;
wire \result_reg[3]_i_9_n_7 ;
wire \result_reg[4]_i_8_n_0 ;
wire \result_reg[7]_i_10_n_0 ;
wire \result_reg[7]_i_11_n_0 ;
wire \result_reg[7]_i_11_n_4 ;
wire \result_reg[7]_i_11_n_5 ;
wire \result_reg[7]_i_11_n_6 ;
wire \result_reg[7]_i_11_n_7 ;
wire \result_reg[7]_i_9_n_0 ;
wire \result_reg[7]_i_9_n_4 ;
wire \result_reg[7]_i_9_n_5 ;
wire \result_reg[7]_i_9_n_6 ;
wire \result_reg[7]_i_9_n_7 ;
wire \result_reg[8]_i_8_n_0 ;
wire \s_input_rs232_in_ack[0]_i_1_n_0 ;
wire \s_input_rs232_in_ack[0]_i_2_n_0 ;
wire \s_input_rs232_in_ack[0]_i_3_n_0 ;
wire \s_input_rs232_in_ack[0]_i_4_n_0 ;
wire \s_input_rs232_in_ack[0]_i_5_n_0 ;
wire \s_input_rs232_in_ack[0]_i_6_n_0 ;
wire \s_input_rs232_in_ack[0]_i_7_n_0 ;
wire \s_input_rs232_in_ack[0]_i_8_n_0 ;
wire \s_output_rs232_out[7]_i_1_n_0 ;
wire \s_output_rs232_out[7]_i_2_n_0 ;
wire \s_output_rs232_out[7]_i_3_n_0 ;
wire \s_output_rs232_out[7]_i_4_n_0 ;
wire \s_output_rs232_out[7]_i_5_n_0 ;
wire \s_output_rs232_out[7]_i_6_n_0 ;
wire \s_output_rs232_out[7]_i_7_n_0 ;
wire \s_output_rs232_out[7]_i_8_n_0 ;
wire \s_output_rs232_out_stb[0]_i_1_n_0 ;
wire [15:0]sel;
wire \state[0]_i_1_n_0 ;
wire \state[0]_i_2_n_0 ;
wire \state[0]_i_3_n_0 ;
wire \state[1]_i_1_n_0 ;
wire \state[1]_i_2_n_0 ;
wire \state[2]_i_1_n_0 ;
wire \state[2]_i_2_n_0 ;
wire \state[2]_i_3_n_0 ;
wire \state[2]_i_4_n_0 ;
wire \state[2]_i_5_n_0 ;
wire \state[2]_i_6_n_0 ;
wire \state_reg_n_0_[0] ;
wire \state_reg_n_0_[1] ;
wire \state_reg_n_0_[2] ;
wire [31:0]store_data;
wire write_enable_reg_n_0;
wire [31:0]write_output;
wire [7:0]write_value;
wire \write_value[7]_i_2_n_0 ;
wire \write_value[7]_i_3_n_0 ;
wire NLW_memory_reg_0_CASCADEOUTA_UNCONNECTED;
wire NLW_memory_reg_0_CASCADEOUTB_UNCONNECTED;
wire NLW_memory_reg_0_DBITERR_UNCONNECTED;
wire NLW_memory_reg_0_INJECTDBITERR_UNCONNECTED;
wire NLW_memory_reg_0_INJECTSBITERR_UNCONNECTED;
wire NLW_memory_reg_0_REGCEAREGCE_UNCONNECTED;
wire NLW_memory_reg_0_REGCEB_UNCONNECTED;
wire NLW_memory_reg_0_SBITERR_UNCONNECTED;
wire [31:4]NLW_memory_reg_0_DOADO_UNCONNECTED;
wire [31:0]NLW_memory_reg_0_DOBDO_UNCONNECTED;
wire [3:0]NLW_memory_reg_0_DOPADOP_UNCONNECTED;
wire [3:0]NLW_memory_reg_0_DOPBDOP_UNCONNECTED;
wire [7:0]NLW_memory_reg_0_ECCPARITY_UNCONNECTED;
wire [8:0]NLW_memory_reg_0_RDADDRECC_UNCONNECTED;
wire NLW_memory_reg_1_CASCADEOUTA_UNCONNECTED;
wire NLW_memory_reg_1_CASCADEOUTB_UNCONNECTED;
wire NLW_memory_reg_1_DBITERR_UNCONNECTED;
wire NLW_memory_reg_1_INJECTDBITERR_UNCONNECTED;
wire NLW_memory_reg_1_INJECTSBITERR_UNCONNECTED;
wire NLW_memory_reg_1_REGCEAREGCE_UNCONNECTED;
wire NLW_memory_reg_1_REGCEB_UNCONNECTED;
wire NLW_memory_reg_1_SBITERR_UNCONNECTED;
wire [31:4]NLW_memory_reg_1_DOADO_UNCONNECTED;
wire [31:0]NLW_memory_reg_1_DOBDO_UNCONNECTED;
wire [3:0]NLW_memory_reg_1_DOPADOP_UNCONNECTED;
wire [3:0]NLW_memory_reg_1_DOPBDOP_UNCONNECTED;
wire [7:0]NLW_memory_reg_1_ECCPARITY_UNCONNECTED;
wire [8:0]NLW_memory_reg_1_RDADDRECC_UNCONNECTED;
wire NLW_memory_reg_2_CASCADEOUTA_UNCONNECTED;
wire NLW_memory_reg_2_CASCADEOUTB_UNCONNECTED;
wire NLW_memory_reg_2_DBITERR_UNCONNECTED;
wire NLW_memory_reg_2_INJECTDBITERR_UNCONNECTED;
wire NLW_memory_reg_2_INJECTSBITERR_UNCONNECTED;
wire NLW_memory_reg_2_REGCEAREGCE_UNCONNECTED;
wire NLW_memory_reg_2_REGCEB_UNCONNECTED;
wire NLW_memory_reg_2_SBITERR_UNCONNECTED;
wire [31:4]NLW_memory_reg_2_DOADO_UNCONNECTED;
wire [31:0]NLW_memory_reg_2_DOBDO_UNCONNECTED;
wire [3:0]NLW_memory_reg_2_DOPADOP_UNCONNECTED;
wire [3:0]NLW_memory_reg_2_DOPBDOP_UNCONNECTED;
wire [7:0]NLW_memory_reg_2_ECCPARITY_UNCONNECTED;
wire [8:0]NLW_memory_reg_2_RDADDRECC_UNCONNECTED;
wire NLW_memory_reg_3_CASCADEOUTA_UNCONNECTED;
wire NLW_memory_reg_3_CASCADEOUTB_UNCONNECTED;
wire NLW_memory_reg_3_DBITERR_UNCONNECTED;
wire NLW_memory_reg_3_INJECTDBITERR_UNCONNECTED;
wire NLW_memory_reg_3_INJECTSBITERR_UNCONNECTED;
wire NLW_memory_reg_3_REGCEAREGCE_UNCONNECTED;
wire NLW_memory_reg_3_REGCEB_UNCONNECTED;
wire NLW_memory_reg_3_SBITERR_UNCONNECTED;
wire [31:4]NLW_memory_reg_3_DOADO_UNCONNECTED;
wire [31:0]NLW_memory_reg_3_DOBDO_UNCONNECTED;
wire [3:0]NLW_memory_reg_3_DOPADOP_UNCONNECTED;
wire [3:0]NLW_memory_reg_3_DOPBDOP_UNCONNECTED;
wire [7:0]NLW_memory_reg_3_ECCPARITY_UNCONNECTED;
wire [8:0]NLW_memory_reg_3_RDADDRECC_UNCONNECTED;
wire NLW_memory_reg_4_CASCADEOUTA_UNCONNECTED;
wire NLW_memory_reg_4_CASCADEOUTB_UNCONNECTED;
wire NLW_memory_reg_4_DBITERR_UNCONNECTED;
wire NLW_memory_reg_4_INJECTDBITERR_UNCONNECTED;
wire NLW_memory_reg_4_INJECTSBITERR_UNCONNECTED;
wire NLW_memory_reg_4_REGCEAREGCE_UNCONNECTED;
wire NLW_memory_reg_4_REGCEB_UNCONNECTED;
wire NLW_memory_reg_4_SBITERR_UNCONNECTED;
wire [31:4]NLW_memory_reg_4_DOADO_UNCONNECTED;
wire [31:0]NLW_memory_reg_4_DOBDO_UNCONNECTED;
wire [3:0]NLW_memory_reg_4_DOPADOP_UNCONNECTED;
wire [3:0]NLW_memory_reg_4_DOPBDOP_UNCONNECTED;
wire [7:0]NLW_memory_reg_4_ECCPARITY_UNCONNECTED;
wire [8:0]NLW_memory_reg_4_RDADDRECC_UNCONNECTED;
wire NLW_memory_reg_5_CASCADEOUTA_UNCONNECTED;
wire NLW_memory_reg_5_CASCADEOUTB_UNCONNECTED;
wire NLW_memory_reg_5_DBITERR_UNCONNECTED;
wire NLW_memory_reg_5_INJECTDBITERR_UNCONNECTED;
wire NLW_memory_reg_5_INJECTSBITERR_UNCONNECTED;
wire NLW_memory_reg_5_REGCEAREGCE_UNCONNECTED;
wire NLW_memory_reg_5_REGCEB_UNCONNECTED;
wire NLW_memory_reg_5_SBITERR_UNCONNECTED;
wire [31:4]NLW_memory_reg_5_DOADO_UNCONNECTED;
wire [31:0]NLW_memory_reg_5_DOBDO_UNCONNECTED;
wire [3:0]NLW_memory_reg_5_DOPADOP_UNCONNECTED;
wire [3:0]NLW_memory_reg_5_DOPBDOP_UNCONNECTED;
wire [7:0]NLW_memory_reg_5_ECCPARITY_UNCONNECTED;
wire [8:0]NLW_memory_reg_5_RDADDRECC_UNCONNECTED;
wire NLW_memory_reg_6_CASCADEOUTA_UNCONNECTED;
wire NLW_memory_reg_6_CASCADEOUTB_UNCONNECTED;
wire NLW_memory_reg_6_DBITERR_UNCONNECTED;
wire NLW_memory_reg_6_INJECTDBITERR_UNCONNECTED;
wire NLW_memory_reg_6_INJECTSBITERR_UNCONNECTED;
wire NLW_memory_reg_6_REGCEAREGCE_UNCONNECTED;
wire NLW_memory_reg_6_REGCEB_UNCONNECTED;
wire NLW_memory_reg_6_SBITERR_UNCONNECTED;
wire [31:4]NLW_memory_reg_6_DOADO_UNCONNECTED;
wire [31:0]NLW_memory_reg_6_DOBDO_UNCONNECTED;
wire [3:0]NLW_memory_reg_6_DOPADOP_UNCONNECTED;
wire [3:0]NLW_memory_reg_6_DOPBDOP_UNCONNECTED;
wire [7:0]NLW_memory_reg_6_ECCPARITY_UNCONNECTED;
wire [8:0]NLW_memory_reg_6_RDADDRECC_UNCONNECTED;
wire NLW_memory_reg_7_CASCADEOUTA_UNCONNECTED;
wire NLW_memory_reg_7_CASCADEOUTB_UNCONNECTED;
wire NLW_memory_reg_7_DBITERR_UNCONNECTED;
wire NLW_memory_reg_7_INJECTDBITERR_UNCONNECTED;
wire NLW_memory_reg_7_INJECTSBITERR_UNCONNECTED;
wire NLW_memory_reg_7_REGCEAREGCE_UNCONNECTED;
wire NLW_memory_reg_7_REGCEB_UNCONNECTED;
wire NLW_memory_reg_7_SBITERR_UNCONNECTED;
wire [31:4]NLW_memory_reg_7_DOADO_UNCONNECTED;
wire [31:0]NLW_memory_reg_7_DOBDO_UNCONNECTED;
wire [3:0]NLW_memory_reg_7_DOPADOP_UNCONNECTED;
wire [3:0]NLW_memory_reg_7_DOPBDOP_UNCONNECTED;
wire [7:0]NLW_memory_reg_7_ECCPARITY_UNCONNECTED;
wire [8:0]NLW_memory_reg_7_RDADDRECC_UNCONNECTED;
wire [2:0]\NLW_program_counter_reg[12]_i_2_CO_UNCONNECTED ;
wire [3:0]\NLW_program_counter_reg[15]_i_4_CO_UNCONNECTED ;
wire [3:3]\NLW_program_counter_reg[15]_i_4_O_UNCONNECTED ;
wire [2:0]\NLW_program_counter_reg[4]_i_2_CO_UNCONNECTED ;
wire [2:0]\NLW_program_counter_reg[8]_i_2_CO_UNCONNECTED ;
wire NLW_program_counter_reg_rep_0_CASCADEOUTA_UNCONNECTED;
wire NLW_program_counter_reg_rep_0_CASCADEOUTB_UNCONNECTED;
wire NLW_program_counter_reg_rep_0_DBITERR_UNCONNECTED;
wire NLW_program_counter_reg_rep_0_INJECTDBITERR_UNCONNECTED;
wire NLW_program_counter_reg_rep_0_INJECTSBITERR_UNCONNECTED;
wire NLW_program_counter_reg_rep_0_REGCEB_UNCONNECTED;
wire NLW_program_counter_reg_rep_0_SBITERR_UNCONNECTED;
wire [31:4]NLW_program_counter_reg_rep_0_DOADO_UNCONNECTED;
wire [31:0]NLW_program_counter_reg_rep_0_DOBDO_UNCONNECTED;
wire [3:0]NLW_program_counter_reg_rep_0_DOPADOP_UNCONNECTED;
wire [3:0]NLW_program_counter_reg_rep_0_DOPBDOP_UNCONNECTED;
wire [7:0]NLW_program_counter_reg_rep_0_ECCPARITY_UNCONNECTED;
wire [8:0]NLW_program_counter_reg_rep_0_RDADDRECC_UNCONNECTED;
wire NLW_program_counter_reg_rep_1_CASCADEOUTA_UNCONNECTED;
wire NLW_program_counter_reg_rep_1_CASCADEOUTB_UNCONNECTED;
wire NLW_program_counter_reg_rep_1_DBITERR_UNCONNECTED;
wire NLW_program_counter_reg_rep_1_INJECTDBITERR_UNCONNECTED;
wire NLW_program_counter_reg_rep_1_INJECTSBITERR_UNCONNECTED;
wire NLW_program_counter_reg_rep_1_REGCEB_UNCONNECTED;
wire NLW_program_counter_reg_rep_1_SBITERR_UNCONNECTED;
wire [31:4]NLW_program_counter_reg_rep_1_DOADO_UNCONNECTED;
wire [31:0]NLW_program_counter_reg_rep_1_DOBDO_UNCONNECTED;
wire [3:0]NLW_program_counter_reg_rep_1_DOPADOP_UNCONNECTED;
wire [3:0]NLW_program_counter_reg_rep_1_DOPBDOP_UNCONNECTED;
wire [7:0]NLW_program_counter_reg_rep_1_ECCPARITY_UNCONNECTED;
wire [8:0]NLW_program_counter_reg_rep_1_RDADDRECC_UNCONNECTED;
wire NLW_program_counter_reg_rep_2_CASCADEOUTA_UNCONNECTED;
wire NLW_program_counter_reg_rep_2_CASCADEOUTB_UNCONNECTED;
wire NLW_program_counter_reg_rep_2_DBITERR_UNCONNECTED;
wire NLW_program_counter_reg_rep_2_INJECTDBITERR_UNCONNECTED;
wire NLW_program_counter_reg_rep_2_INJECTSBITERR_UNCONNECTED;
wire NLW_program_counter_reg_rep_2_REGCEB_UNCONNECTED;
wire NLW_program_counter_reg_rep_2_SBITERR_UNCONNECTED;
wire [31:4]NLW_program_counter_reg_rep_2_DOADO_UNCONNECTED;
wire [31:0]NLW_program_counter_reg_rep_2_DOBDO_UNCONNECTED;
wire [3:0]NLW_program_counter_reg_rep_2_DOPADOP_UNCONNECTED;
wire [3:0]NLW_program_counter_reg_rep_2_DOPBDOP_UNCONNECTED;
wire [7:0]NLW_program_counter_reg_rep_2_ECCPARITY_UNCONNECTED;
wire [8:0]NLW_program_counter_reg_rep_2_RDADDRECC_UNCONNECTED;
wire NLW_program_counter_reg_rep_3_CASCADEOUTA_UNCONNECTED;
wire NLW_program_counter_reg_rep_3_CASCADEOUTB_UNCONNECTED;
wire NLW_program_counter_reg_rep_3_DBITERR_UNCONNECTED;
wire NLW_program_counter_reg_rep_3_INJECTDBITERR_UNCONNECTED;
wire NLW_program_counter_reg_rep_3_INJECTSBITERR_UNCONNECTED;
wire NLW_program_counter_reg_rep_3_REGCEB_UNCONNECTED;
wire NLW_program_counter_reg_rep_3_SBITERR_UNCONNECTED;
wire [31:4]NLW_program_counter_reg_rep_3_DOADO_UNCONNECTED;
wire [31:0]NLW_program_counter_reg_rep_3_DOBDO_UNCONNECTED;
wire [3:0]NLW_program_counter_reg_rep_3_DOPADOP_UNCONNECTED;
wire [3:0]NLW_program_counter_reg_rep_3_DOPBDOP_UNCONNECTED;
wire [7:0]NLW_program_counter_reg_rep_3_ECCPARITY_UNCONNECTED;
wire [8:0]NLW_program_counter_reg_rep_3_RDADDRECC_UNCONNECTED;
wire NLW_program_counter_reg_rep_4_CASCADEOUTA_UNCONNECTED;
wire NLW_program_counter_reg_rep_4_CASCADEOUTB_UNCONNECTED;
wire NLW_program_counter_reg_rep_4_DBITERR_UNCONNECTED;
wire NLW_program_counter_reg_rep_4_INJECTDBITERR_UNCONNECTED;
wire NLW_program_counter_reg_rep_4_INJECTSBITERR_UNCONNECTED;
wire NLW_program_counter_reg_rep_4_REGCEB_UNCONNECTED;
wire NLW_program_counter_reg_rep_4_SBITERR_UNCONNECTED;
wire [31:4]NLW_program_counter_reg_rep_4_DOADO_UNCONNECTED;
wire [31:0]NLW_program_counter_reg_rep_4_DOBDO_UNCONNECTED;
wire [3:0]NLW_program_counter_reg_rep_4_DOPADOP_UNCONNECTED;
wire [3:0]NLW_program_counter_reg_rep_4_DOPBDOP_UNCONNECTED;
wire [7:0]NLW_program_counter_reg_rep_4_ECCPARITY_UNCONNECTED;
wire [8:0]NLW_program_counter_reg_rep_4_RDADDRECC_UNCONNECTED;
wire NLW_program_counter_reg_rep_5_CASCADEOUTA_UNCONNECTED;
wire NLW_program_counter_reg_rep_5_CASCADEOUTB_UNCONNECTED;
wire NLW_program_counter_reg_rep_5_DBITERR_UNCONNECTED;
wire NLW_program_counter_reg_rep_5_INJECTDBITERR_UNCONNECTED;
wire NLW_program_counter_reg_rep_5_INJECTSBITERR_UNCONNECTED;
wire NLW_program_counter_reg_rep_5_REGCEB_UNCONNECTED;
wire NLW_program_counter_reg_rep_5_SBITERR_UNCONNECTED;
wire [31:4]NLW_program_counter_reg_rep_5_DOADO_UNCONNECTED;
wire [31:0]NLW_program_counter_reg_rep_5_DOBDO_UNCONNECTED;
wire [3:0]NLW_program_counter_reg_rep_5_DOPADOP_UNCONNECTED;
wire [3:0]NLW_program_counter_reg_rep_5_DOPBDOP_UNCONNECTED;
wire [7:0]NLW_program_counter_reg_rep_5_ECCPARITY_UNCONNECTED;
wire [8:0]NLW_program_counter_reg_rep_5_RDADDRECC_UNCONNECTED;
wire NLW_program_counter_reg_rep_6_CASCADEOUTA_UNCONNECTED;
wire NLW_program_counter_reg_rep_6_CASCADEOUTB_UNCONNECTED;
wire NLW_program_counter_reg_rep_6_DBITERR_UNCONNECTED;
wire NLW_program_counter_reg_rep_6_INJECTDBITERR_UNCONNECTED;
wire NLW_program_counter_reg_rep_6_INJECTSBITERR_UNCONNECTED;
wire NLW_program_counter_reg_rep_6_REGCEB_UNCONNECTED;
wire NLW_program_counter_reg_rep_6_SBITERR_UNCONNECTED;
wire [31:4]NLW_program_counter_reg_rep_6_DOADO_UNCONNECTED;
wire [31:0]NLW_program_counter_reg_rep_6_DOBDO_UNCONNECTED;
wire [3:0]NLW_program_counter_reg_rep_6_DOPADOP_UNCONNECTED;
wire [3:0]NLW_program_counter_reg_rep_6_DOPBDOP_UNCONNECTED;
wire [7:0]NLW_program_counter_reg_rep_6_ECCPARITY_UNCONNECTED;
wire [8:0]NLW_program_counter_reg_rep_6_RDADDRECC_UNCONNECTED;
wire NLW_program_counter_reg_rep_7_REGCEB_UNCONNECTED;
wire [15:1]NLW_program_counter_reg_rep_7_DOADO_UNCONNECTED;
wire [15:0]NLW_program_counter_reg_rep_7_DOBDO_UNCONNECTED;
wire [1:0]NLW_program_counter_reg_rep_7_DOPADOP_UNCONNECTED;
wire [1:0]NLW_program_counter_reg_rep_7_DOPBDOP_UNCONNECTED;
wire [1:0]NLW_registers_reg_r1_0_15_0_5_DOD_UNCONNECTED;
wire [1:0]NLW_registers_reg_r1_0_15_12_17_DOD_UNCONNECTED;
wire [1:0]NLW_registers_reg_r1_0_15_18_23_DOD_UNCONNECTED;
wire [1:0]NLW_registers_reg_r1_0_15_24_29_DOD_UNCONNECTED;
wire [1:0]NLW_registers_reg_r1_0_15_30_31_DOB_UNCONNECTED;
wire [1:0]NLW_registers_reg_r1_0_15_30_31_DOC_UNCONNECTED;
wire [1:0]NLW_registers_reg_r1_0_15_30_31_DOD_UNCONNECTED;
wire [1:0]NLW_registers_reg_r1_0_15_6_11_DOD_UNCONNECTED;
wire [1:0]NLW_registers_reg_r2_0_15_0_5_DOD_UNCONNECTED;
wire [1:0]NLW_registers_reg_r2_0_15_12_17_DOD_UNCONNECTED;
wire [1:0]NLW_registers_reg_r2_0_15_18_23_DOD_UNCONNECTED;
wire [1:0]NLW_registers_reg_r2_0_15_24_29_DOD_UNCONNECTED;
wire [1:0]NLW_registers_reg_r2_0_15_30_31_DOB_UNCONNECTED;
wire [1:0]NLW_registers_reg_r2_0_15_30_31_DOC_UNCONNECTED;
wire [1:0]NLW_registers_reg_r2_0_15_30_31_DOD_UNCONNECTED;
wire [1:0]NLW_registers_reg_r2_0_15_6_11_DOD_UNCONNECTED;
wire [2:0]\NLW_result_reg[0]_i_10_CO_UNCONNECTED ;
wire [3:0]\NLW_result_reg[0]_i_10_O_UNCONNECTED ;
wire [3:0]\NLW_result_reg[0]_i_12_CO_UNCONNECTED ;
wire [3:0]\NLW_result_reg[0]_i_12_O_UNCONNECTED ;
wire [2:0]\NLW_result_reg[0]_i_13_CO_UNCONNECTED ;
wire [3:0]\NLW_result_reg[0]_i_13_O_UNCONNECTED ;
wire [2:0]\NLW_result_reg[0]_i_14_CO_UNCONNECTED ;
wire [3:0]\NLW_result_reg[0]_i_14_O_UNCONNECTED ;
wire [2:0]\NLW_result_reg[0]_i_23_CO_UNCONNECTED ;
wire [3:0]\NLW_result_reg[0]_i_23_O_UNCONNECTED ;
wire [2:0]\NLW_result_reg[0]_i_29_CO_UNCONNECTED ;
wire [3:0]\NLW_result_reg[0]_i_29_O_UNCONNECTED ;
wire [2:0]\NLW_result_reg[0]_i_33_CO_UNCONNECTED ;
wire [3:0]\NLW_result_reg[0]_i_33_O_UNCONNECTED ;
wire [2:0]\NLW_result_reg[0]_i_38_CO_UNCONNECTED ;
wire [3:0]\NLW_result_reg[0]_i_38_O_UNCONNECTED ;
wire [2:0]\NLW_result_reg[0]_i_52_CO_UNCONNECTED ;
wire [3:0]\NLW_result_reg[0]_i_52_O_UNCONNECTED ;
wire [2:0]\NLW_result_reg[0]_i_57_CO_UNCONNECTED ;
wire [3:0]\NLW_result_reg[0]_i_57_O_UNCONNECTED ;
wire [2:0]\NLW_result_reg[0]_i_64_CO_UNCONNECTED ;
wire [3:0]\NLW_result_reg[0]_i_64_O_UNCONNECTED ;
wire [2:0]\NLW_result_reg[0]_i_69_CO_UNCONNECTED ;
wire [3:0]\NLW_result_reg[0]_i_69_O_UNCONNECTED ;
wire [2:0]\NLW_result_reg[0]_i_7_CO_UNCONNECTED ;
wire [3:0]\NLW_result_reg[0]_i_7_O_UNCONNECTED ;
wire [2:0]\NLW_result_reg[0]_i_82_CO_UNCONNECTED ;
wire [3:0]\NLW_result_reg[0]_i_82_O_UNCONNECTED ;
wire [2:0]\NLW_result_reg[0]_i_95_CO_UNCONNECTED ;
wire [3:0]\NLW_result_reg[0]_i_95_O_UNCONNECTED ;
wire [2:0]\NLW_result_reg[11]_i_8_CO_UNCONNECTED ;
wire [2:0]\NLW_result_reg[15]_i_10_CO_UNCONNECTED ;
wire [2:0]\NLW_result_reg[15]_i_11_CO_UNCONNECTED ;
wire [2:0]\NLW_result_reg[15]_i_16_CO_UNCONNECTED ;
wire [2:0]\NLW_result_reg[15]_i_7_CO_UNCONNECTED ;
wire [2:0]\NLW_result_reg[15]_i_8_CO_UNCONNECTED ;
wire [2:0]\NLW_result_reg[16]_i_10_CO_UNCONNECTED ;
wire [2:0]\NLW_result_reg[16]_i_7_CO_UNCONNECTED ;
wire [3:3]\NLW_result_reg[16]_i_7_O_UNCONNECTED ;
wire [2:0]\NLW_result_reg[19]_i_11_CO_UNCONNECTED ;
wire [2:0]\NLW_result_reg[19]_i_6_CO_UNCONNECTED ;
wire [2:0]\NLW_result_reg[19]_i_7_CO_UNCONNECTED ;
wire [2:0]\NLW_result_reg[1]_i_6_CO_UNCONNECTED ;
wire [2:0]\NLW_result_reg[23]_i_10_CO_UNCONNECTED ;
wire [2:0]\NLW_result_reg[23]_i_7_CO_UNCONNECTED ;
wire [2:0]\NLW_result_reg[23]_i_8_CO_UNCONNECTED ;
wire [2:0]\NLW_result_reg[27]_i_10_CO_UNCONNECTED ;
wire [2:0]\NLW_result_reg[27]_i_11_CO_UNCONNECTED ;
wire [3:0]\NLW_result_reg[31]_i_14_CO_UNCONNECTED ;
wire [3:0]\NLW_result_reg[31]_i_15_CO_UNCONNECTED ;
wire [2:0]\NLW_result_reg[31]_i_16_CO_UNCONNECTED ;
wire [3:0]\NLW_result_reg[31]_i_9_CO_UNCONNECTED ;
wire [2:0]\NLW_result_reg[3]_i_8_CO_UNCONNECTED ;
wire [2:0]\NLW_result_reg[3]_i_9_CO_UNCONNECTED ;
wire [2:0]\NLW_result_reg[4]_i_8_CO_UNCONNECTED ;
wire [2:0]\NLW_result_reg[7]_i_10_CO_UNCONNECTED ;
wire [2:0]\NLW_result_reg[7]_i_11_CO_UNCONNECTED ;
wire [2:0]\NLW_result_reg[7]_i_9_CO_UNCONNECTED ;
wire [2:0]\NLW_result_reg[8]_i_8_CO_UNCONNECTED ;
FDRE \address_a_2_reg[0]
(.C(ETH_CLK_OBUF),
.CE(opcode_20),
.D(address_a[0]),
.Q(address_a_2[0]),
.R(1'b0));
FDRE \address_a_2_reg[1]
(.C(ETH_CLK_OBUF),
.CE(opcode_20),
.D(address_a[1]),
.Q(address_a_2[1]),
.R(1'b0));
FDRE \address_a_2_reg[2]
(.C(ETH_CLK_OBUF),
.CE(opcode_20),
.D(address_a[2]),
.Q(address_a_2[2]),
.R(1'b0));
FDRE \address_a_2_reg[3]
(.C(ETH_CLK_OBUF),
.CE(opcode_20),
.D(address_a[3]),
.Q(address_a_2[3]),
.R(1'b0));
FDRE \address_b_2_reg[0]
(.C(ETH_CLK_OBUF),
.CE(opcode_20),
.D(program_counter_reg_rep_0_n_35),
.Q(address_b_2[0]),
.R(1'b0));
FDRE \address_b_2_reg[1]
(.C(ETH_CLK_OBUF),
.CE(opcode_20),
.D(program_counter_reg_rep_0_n_34),
.Q(address_b_2[1]),
.R(1'b0));
FDRE \address_b_2_reg[2]
(.C(ETH_CLK_OBUF),
.CE(opcode_20),
.D(program_counter_reg_rep_0_n_33),
.Q(address_b_2[2]),
.R(1'b0));
FDRE \address_b_2_reg[3]
(.C(ETH_CLK_OBUF),
.CE(opcode_20),
.D(program_counter_reg_rep_0_n_32),
.Q(address_b_2[3]),
.R(1'b0));
FDRE \address_z_2_reg[0]
(.C(ETH_CLK_OBUF),
.CE(opcode_20),
.D(address_z[0]),
.Q(address_z_2[0]),
.R(1'b0));
FDRE \address_z_2_reg[1]
(.C(ETH_CLK_OBUF),
.CE(opcode_20),
.D(address_z[1]),
.Q(address_z_2[1]),
.R(1'b0));
FDRE \address_z_2_reg[2]
(.C(ETH_CLK_OBUF),
.CE(opcode_20),
.D(address_z[2]),
.Q(address_z_2[2]),
.R(1'b0));
FDRE \address_z_2_reg[3]
(.C(ETH_CLK_OBUF),
.CE(opcode_20),
.D(address_z[3]),
.Q(address_z_2[3]),
.R(1'b0));
LUT3 #(
.INIT(8'h40))
\address_z_3[3]_i_1
(.I0(\state_reg_n_0_[2] ),
.I1(\state_reg_n_0_[1] ),
.I2(\state_reg_n_0_[0] ),
.O(\address_z_3[3]_i_1_n_0 ));
FDRE \address_z_3_reg[0]
(.C(ETH_CLK_OBUF),
.CE(\address_z_3[3]_i_1_n_0 ),
.D(address_z_2[0]),
.Q(address_z_3[0]),
.R(INTERNAL_RST_reg));
FDRE \address_z_3_reg[1]
(.C(ETH_CLK_OBUF),
.CE(\address_z_3[3]_i_1_n_0 ),
.D(address_z_2[1]),
.Q(address_z_3[1]),
.R(INTERNAL_RST_reg));
FDRE \address_z_3_reg[2]
(.C(ETH_CLK_OBUF),
.CE(\address_z_3[3]_i_1_n_0 ),
.D(address_z_2[2]),
.Q(address_z_3[2]),
.R(INTERNAL_RST_reg));
FDRE \address_z_3_reg[3]
(.C(ETH_CLK_OBUF),
.CE(\address_z_3[3]_i_1_n_0 ),
.D(address_z_2[3]),
.Q(address_z_3[3]),
.R(INTERNAL_RST_reg));
LUT2 #(
.INIT(4'h2))
\literal_2[15]_i_1
(.I0(\state_reg_n_0_[1] ),
.I1(\state_reg_n_0_[2] ),
.O(opcode_20));
FDRE \literal_2_reg[10]
(.C(ETH_CLK_OBUF),
.CE(opcode_20),
.D(program_counter_reg_rep_2_n_33),
.Q(data7[26]),
.R(1'b0));
FDRE \literal_2_reg[11]
(.C(ETH_CLK_OBUF),
.CE(opcode_20),
.D(program_counter_reg_rep_2_n_32),
.Q(data7[27]),
.R(1'b0));
FDRE \literal_2_reg[12]
(.C(ETH_CLK_OBUF),
.CE(opcode_20),
.D(program_counter_reg_rep_3_n_35),
.Q(data7[28]),
.R(1'b0));
FDRE \literal_2_reg[13]
(.C(ETH_CLK_OBUF),
.CE(opcode_20),
.D(program_counter_reg_rep_3_n_34),
.Q(data7[29]),
.R(1'b0));
FDRE \literal_2_reg[14]
(.C(ETH_CLK_OBUF),
.CE(opcode_20),
.D(program_counter_reg_rep_3_n_33),
.Q(data7[30]),
.R(1'b0));
FDRE \literal_2_reg[15]
(.C(ETH_CLK_OBUF),
.CE(opcode_20),
.D(program_counter_reg_rep_3_n_32),
.Q(data7[31]),
.R(1'b0));
FDRE \literal_2_reg[4]
(.C(ETH_CLK_OBUF),
.CE(opcode_20),
.D(program_counter_reg_rep_1_n_35),
.Q(data7[20]),
.R(1'b0));
FDRE \literal_2_reg[5]
(.C(ETH_CLK_OBUF),
.CE(opcode_20),
.D(program_counter_reg_rep_1_n_34),
.Q(data7[21]),
.R(1'b0));
FDRE \literal_2_reg[6]
(.C(ETH_CLK_OBUF),
.CE(opcode_20),
.D(program_counter_reg_rep_1_n_33),
.Q(data7[22]),
.R(1'b0));
FDRE \literal_2_reg[7]
(.C(ETH_CLK_OBUF),
.CE(opcode_20),
.D(program_counter_reg_rep_1_n_32),
.Q(data7[23]),
.R(1'b0));
FDRE \literal_2_reg[8]
(.C(ETH_CLK_OBUF),
.CE(opcode_20),
.D(program_counter_reg_rep_2_n_35),
.Q(data7[24]),
.R(1'b0));
FDRE \literal_2_reg[9]
(.C(ETH_CLK_OBUF),
.CE(opcode_20),
.D(program_counter_reg_rep_2_n_34),
.Q(data7[25]),
.R(1'b0));
(* METHODOLOGY_DRC_VIOS = "{SYNTH-6 {cell *THIS*}}" *)
(* RTL_RAM_BITS = "131104" *)
(* RTL_RAM_NAME = "memory" *)
(* bram_addr_begin = "0" *)
(* bram_addr_end = "8191" *)
(* bram_slice_begin = "0" *)
(* bram_slice_end = "3" *)
RAMB36E1 #(
.DOA_REG(0),
.DOB_REG(0),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("PERFORMANCE"),
.READ_WIDTH_A(4),
.READ_WIDTH_B(0),
.RSTREG_PRIORITY_A("RSTREG"),
.RSTREG_PRIORITY_B("RSTREG"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("READ_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(4),
.WRITE_WIDTH_B(0))
memory_reg_0
(.ADDRARDADDR({1'b1,\read_input[12]_i_1_n_0 ,\read_input[11]_i_1_n_0 ,\read_input[10]_i_1_n_0 ,\read_input[9]_i_1_n_0 ,\read_input[8]_i_1_n_0 ,\read_input[7]_i_1_n_0 ,\read_input[6]_i_1_n_0 ,\read_input[5]_i_1_n_0 ,\read_input[4]_i_1_n_0 ,\read_input[3]_i_1_n_0 ,\read_input[2]_i_1_n_0 ,\read_input[1]_i_1_n_0 ,\read_input[0]_i_1_n_0 ,1'b1,1'b1}),
.ADDRBWRADDR({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
.CASCADEINA(1'b1),
.CASCADEINB(1'b0),
.CASCADEOUTA(NLW_memory_reg_0_CASCADEOUTA_UNCONNECTED),
.CASCADEOUTB(NLW_memory_reg_0_CASCADEOUTB_UNCONNECTED),
.CLKARDCLK(ETH_CLK_OBUF),
.CLKBWRCLK(1'b0),
.DBITERR(NLW_memory_reg_0_DBITERR_UNCONNECTED),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,store_data[3:0]}),
.DIBDI({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
.DIPADIP({1'b0,1'b0,1'b0,1'b0}),
.DIPBDIP({1'b1,1'b1,1'b1,1'b1}),
.DOADO({NLW_memory_reg_0_DOADO_UNCONNECTED[31:4],load_data[3:0]}),
.DOBDO(NLW_memory_reg_0_DOBDO_UNCONNECTED[31:0]),
.DOPADOP(NLW_memory_reg_0_DOPADOP_UNCONNECTED[3:0]),
.DOPBDOP(NLW_memory_reg_0_DOPBDOP_UNCONNECTED[3:0]),
.ECCPARITY(NLW_memory_reg_0_ECCPARITY_UNCONNECTED[7:0]),
.ENARDEN(1'b1),
.ENBWREN(1'b0),
.INJECTDBITERR(NLW_memory_reg_0_INJECTDBITERR_UNCONNECTED),
.INJECTSBITERR(NLW_memory_reg_0_INJECTSBITERR_UNCONNECTED),
.RDADDRECC(NLW_memory_reg_0_RDADDRECC_UNCONNECTED[8:0]),
.REGCEAREGCE(NLW_memory_reg_0_REGCEAREGCE_UNCONNECTED),
.REGCEB(NLW_memory_reg_0_REGCEB_UNCONNECTED),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(NLW_memory_reg_0_SBITERR_UNCONNECTED),
.WEA({1'b0,1'b0,1'b0,memory_reg_0_i_1_n_0}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
LUT6 #(
.INIT(64'h0000000002000000))
memory_reg_0_i_1
(.I0(opcode_2[1]),
.I1(opcode_2[2]),
.I2(opcode_2[0]),
.I3(opcode_20),
.I4(\state_reg_n_0_[0] ),
.I5(memory_reg_0_i_2_n_0),
.O(memory_reg_0_i_1_n_0));
LUT2 #(
.INIT(4'hE))
memory_reg_0_i_2
(.I0(opcode_2[4]),
.I1(opcode_2[3]),
.O(memory_reg_0_i_2_n_0));
(* IS_CLOCK_GATED *)
(* METHODOLOGY_DRC_VIOS = "{SYNTH-6 {cell *THIS*}}" *)
(* POWER_OPTED_CE = "ENARDEN=NEW" *)
(* RTL_RAM_BITS = "131104" *)
(* RTL_RAM_NAME = "memory" *)
(* bram_addr_begin = "0" *)
(* bram_addr_end = "8191" *)
(* bram_slice_begin = "4" *)
(* bram_slice_end = "7" *)
RAMB36E1 #(
.DOA_REG(0),
.DOB_REG(0),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("PERFORMANCE"),
.READ_WIDTH_A(4),
.READ_WIDTH_B(0),
.RSTREG_PRIORITY_A("RSTREG"),
.RSTREG_PRIORITY_B("RSTREG"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("READ_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(4),
.WRITE_WIDTH_B(0))
memory_reg_1
(.ADDRARDADDR({1'b1,\read_input[12]_i_1_n_0 ,\read_input[11]_i_1_n_0 ,\read_input[10]_i_1_n_0 ,\read_input[9]_i_1_n_0 ,\read_input[8]_i_1_n_0 ,\read_input[7]_i_1_n_0 ,\read_input[6]_i_1_n_0 ,\read_input[5]_i_1_n_0 ,\read_input[4]_i_1_n_0 ,\read_input[3]_i_1_n_0 ,\read_input[2]_i_1_n_0 ,\read_input[1]_i_1_n_0 ,\read_input[0]_i_1_n_0 ,1'b1,1'b1}),
.ADDRBWRADDR({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
.CASCADEINA(1'b1),
.CASCADEINB(1'b0),
.CASCADEOUTA(NLW_memory_reg_1_CASCADEOUTA_UNCONNECTED),
.CASCADEOUTB(NLW_memory_reg_1_CASCADEOUTB_UNCONNECTED),
.CLKARDCLK(ETH_CLK_OBUF),
.CLKBWRCLK(1'b0),
.DBITERR(NLW_memory_reg_1_DBITERR_UNCONNECTED),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,store_data[7:4]}),
.DIBDI({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
.DIPADIP({1'b0,1'b0,1'b0,1'b0}),
.DIPBDIP({1'b1,1'b1,1'b1,1'b1}),
.DOADO({NLW_memory_reg_1_DOADO_UNCONNECTED[31:4],load_data[7:4]}),
.DOBDO(NLW_memory_reg_1_DOBDO_UNCONNECTED[31:0]),
.DOPADOP(NLW_memory_reg_1_DOPADOP_UNCONNECTED[3:0]),
.DOPBDOP(NLW_memory_reg_1_DOPBDOP_UNCONNECTED[3:0]),
.ECCPARITY(NLW_memory_reg_1_ECCPARITY_UNCONNECTED[7:0]),
.ENARDEN(memory_reg_1_ENARDEN_cooolgate_en_sig_1),
.ENBWREN(1'b0),
.INJECTDBITERR(NLW_memory_reg_1_INJECTDBITERR_UNCONNECTED),
.INJECTSBITERR(NLW_memory_reg_1_INJECTSBITERR_UNCONNECTED),
.RDADDRECC(NLW_memory_reg_1_RDADDRECC_UNCONNECTED[8:0]),
.REGCEAREGCE(NLW_memory_reg_1_REGCEAREGCE_UNCONNECTED),
.REGCEB(NLW_memory_reg_1_REGCEB_UNCONNECTED),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(NLW_memory_reg_1_SBITERR_UNCONNECTED),
.WEA({1'b0,1'b0,1'b0,memory_reg_0_i_1_n_0}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
LUT4 #(
.INIT(16'hff02))
memory_reg_1_ENARDEN_cooolgate_en_gate_1
(.I0(\state[2]_i_1_n_0 ),
.I1(\state[1]_i_1_n_0 ),
.I2(INTERNAL_RST_reg),
.I3(memory_reg_0_i_1_n_0),
.O(memory_reg_1_ENARDEN_cooolgate_en_sig_1));
(* IS_CLOCK_GATED *)
(* METHODOLOGY_DRC_VIOS = "{SYNTH-6 {cell *THIS*}}" *)
(* POWER_OPTED_CE = "ENARDEN=NEW" *)
(* RTL_RAM_BITS = "131104" *)
(* RTL_RAM_NAME = "memory" *)
(* bram_addr_begin = "0" *)
(* bram_addr_end = "8191" *)
(* bram_slice_begin = "8" *)
(* bram_slice_end = "11" *)
RAMB36E1 #(
.DOA_REG(0),
.DOB_REG(0),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("PERFORMANCE"),
.READ_WIDTH_A(4),
.READ_WIDTH_B(0),
.RSTREG_PRIORITY_A("RSTREG"),
.RSTREG_PRIORITY_B("RSTREG"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("READ_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(4),
.WRITE_WIDTH_B(0))
memory_reg_2
(.ADDRARDADDR({1'b1,\read_input[12]_i_1_n_0 ,\read_input[11]_i_1_n_0 ,\read_input[10]_i_1_n_0 ,\read_input[9]_i_1_n_0 ,\read_input[8]_i_1_n_0 ,\read_input[7]_i_1_n_0 ,\read_input[6]_i_1_n_0 ,\read_input[5]_i_1_n_0 ,\read_input[4]_i_1_n_0 ,\read_input[3]_i_1_n_0 ,\read_input[2]_i_1_n_0 ,\read_input[1]_i_1_n_0 ,\read_input[0]_i_1_n_0 ,1'b1,1'b1}),
.ADDRBWRADDR({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
.CASCADEINA(1'b1),
.CASCADEINB(1'b0),
.CASCADEOUTA(NLW_memory_reg_2_CASCADEOUTA_UNCONNECTED),
.CASCADEOUTB(NLW_memory_reg_2_CASCADEOUTB_UNCONNECTED),
.CLKARDCLK(ETH_CLK_OBUF),
.CLKBWRCLK(1'b0),
.DBITERR(NLW_memory_reg_2_DBITERR_UNCONNECTED),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,store_data[11:8]}),
.DIBDI({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
.DIPADIP({1'b0,1'b0,1'b0,1'b0}),
.DIPBDIP({1'b1,1'b1,1'b1,1'b1}),
.DOADO({NLW_memory_reg_2_DOADO_UNCONNECTED[31:4],load_data[11:8]}),
.DOBDO(NLW_memory_reg_2_DOBDO_UNCONNECTED[31:0]),
.DOPADOP(NLW_memory_reg_2_DOPADOP_UNCONNECTED[3:0]),
.DOPBDOP(NLW_memory_reg_2_DOPBDOP_UNCONNECTED[3:0]),
.ECCPARITY(NLW_memory_reg_2_ECCPARITY_UNCONNECTED[7:0]),
.ENARDEN(memory_reg_2_ENARDEN_cooolgate_en_sig_2),
.ENBWREN(1'b0),
.INJECTDBITERR(NLW_memory_reg_2_INJECTDBITERR_UNCONNECTED),
.INJECTSBITERR(NLW_memory_reg_2_INJECTSBITERR_UNCONNECTED),
.RDADDRECC(NLW_memory_reg_2_RDADDRECC_UNCONNECTED[8:0]),
.REGCEAREGCE(NLW_memory_reg_2_REGCEAREGCE_UNCONNECTED),
.REGCEB(NLW_memory_reg_2_REGCEB_UNCONNECTED),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(NLW_memory_reg_2_SBITERR_UNCONNECTED),
.WEA({1'b0,1'b0,1'b0,memory_reg_0_i_1_n_0}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
LUT4 #(
.INIT(16'hff02))
memory_reg_2_ENARDEN_cooolgate_en_gate_3
(.I0(\state[2]_i_1_n_0 ),
.I1(\state[1]_i_1_n_0 ),
.I2(INTERNAL_RST_reg),
.I3(memory_reg_0_i_1_n_0),
.O(memory_reg_2_ENARDEN_cooolgate_en_sig_2));
LUT5 #(
.INIT(32'hFFFB0008))
memory_reg_2_i_1
(.I0(result[11]),
.I1(write_enable_reg_n_0),
.I2(\write_value[7]_i_2_n_0 ),
.I3(\write_value[7]_i_3_n_0 ),
.I4(register_b[11]),
.O(store_data[11]));
LUT5 #(
.INIT(32'hFFFB0008))
memory_reg_2_i_2
(.I0(result[10]),
.I1(write_enable_reg_n_0),
.I2(\write_value[7]_i_2_n_0 ),
.I3(\write_value[7]_i_3_n_0 ),
.I4(register_b[10]),
.O(store_data[10]));
LUT5 #(
.INIT(32'hFFFB0008))
memory_reg_2_i_3
(.I0(result[9]),
.I1(write_enable_reg_n_0),
.I2(\write_value[7]_i_2_n_0 ),
.I3(\write_value[7]_i_3_n_0 ),
.I4(register_b[9]),
.O(store_data[9]));
LUT5 #(
.INIT(32'hFFFB0008))
memory_reg_2_i_4
(.I0(result[8]),
.I1(write_enable_reg_n_0),
.I2(\write_value[7]_i_2_n_0 ),
.I3(\write_value[7]_i_3_n_0 ),
.I4(register_b[8]),
.O(store_data[8]));
(* IS_CLOCK_GATED *)
(* METHODOLOGY_DRC_VIOS = "{SYNTH-6 {cell *THIS*}}" *)
(* POWER_OPTED_CE = "ENARDEN=NEW" *)
(* RTL_RAM_BITS = "131104" *)
(* RTL_RAM_NAME = "memory" *)
(* bram_addr_begin = "0" *)
(* bram_addr_end = "8191" *)
(* bram_slice_begin = "12" *)
(* bram_slice_end = "15" *)
RAMB36E1 #(
.DOA_REG(0),
.DOB_REG(0),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("PERFORMANCE"),
.READ_WIDTH_A(4),
.READ_WIDTH_B(0),
.RSTREG_PRIORITY_A("RSTREG"),
.RSTREG_PRIORITY_B("RSTREG"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("READ_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(4),
.WRITE_WIDTH_B(0))
memory_reg_3
(.ADDRARDADDR({1'b1,\read_input[12]_i_1_n_0 ,\read_input[11]_i_1_n_0 ,\read_input[10]_i_1_n_0 ,\read_input[9]_i_1_n_0 ,\read_input[8]_i_1_n_0 ,\read_input[7]_i_1_n_0 ,\read_input[6]_i_1_n_0 ,\read_input[5]_i_1_n_0 ,\read_input[4]_i_1_n_0 ,\read_input[3]_i_1_n_0 ,\read_input[2]_i_1_n_0 ,\read_input[1]_i_1_n_0 ,\read_input[0]_i_1_n_0 ,1'b1,1'b1}),
.ADDRBWRADDR({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
.CASCADEINA(1'b1),
.CASCADEINB(1'b0),
.CASCADEOUTA(NLW_memory_reg_3_CASCADEOUTA_UNCONNECTED),
.CASCADEOUTB(NLW_memory_reg_3_CASCADEOUTB_UNCONNECTED),
.CLKARDCLK(ETH_CLK_OBUF),
.CLKBWRCLK(1'b0),
.DBITERR(NLW_memory_reg_3_DBITERR_UNCONNECTED),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,store_data[15:12]}),
.DIBDI({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
.DIPADIP({1'b0,1'b0,1'b0,1'b0}),
.DIPBDIP({1'b1,1'b1,1'b1,1'b1}),
.DOADO({NLW_memory_reg_3_DOADO_UNCONNECTED[31:4],load_data[15:12]}),
.DOBDO(NLW_memory_reg_3_DOBDO_UNCONNECTED[31:0]),
.DOPADOP(NLW_memory_reg_3_DOPADOP_UNCONNECTED[3:0]),
.DOPBDOP(NLW_memory_reg_3_DOPBDOP_UNCONNECTED[3:0]),
.ECCPARITY(NLW_memory_reg_3_ECCPARITY_UNCONNECTED[7:0]),
.ENARDEN(memory_reg_3_ENARDEN_cooolgate_en_sig_3),
.ENBWREN(1'b0),
.INJECTDBITERR(NLW_memory_reg_3_INJECTDBITERR_UNCONNECTED),
.INJECTSBITERR(NLW_memory_reg_3_INJECTSBITERR_UNCONNECTED),
.RDADDRECC(NLW_memory_reg_3_RDADDRECC_UNCONNECTED[8:0]),
.REGCEAREGCE(NLW_memory_reg_3_REGCEAREGCE_UNCONNECTED),
.REGCEB(NLW_memory_reg_3_REGCEB_UNCONNECTED),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(NLW_memory_reg_3_SBITERR_UNCONNECTED),
.WEA({1'b0,1'b0,1'b0,memory_reg_0_i_1_n_0}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
LUT4 #(
.INIT(16'hff02))
memory_reg_3_ENARDEN_cooolgate_en_gate_5
(.I0(\state[2]_i_1_n_0 ),
.I1(\state[1]_i_1_n_0 ),
.I2(INTERNAL_RST_reg),
.I3(memory_reg_0_i_1_n_0),
.O(memory_reg_3_ENARDEN_cooolgate_en_sig_3));
LUT5 #(
.INIT(32'hFFFB0008))
memory_reg_3_i_1
(.I0(result[15]),
.I1(write_enable_reg_n_0),
.I2(\write_value[7]_i_2_n_0 ),
.I3(\write_value[7]_i_3_n_0 ),
.I4(register_b[15]),
.O(store_data[15]));
LUT5 #(
.INIT(32'hFFFB0008))
memory_reg_3_i_2
(.I0(result[14]),
.I1(write_enable_reg_n_0),
.I2(\write_value[7]_i_2_n_0 ),
.I3(\write_value[7]_i_3_n_0 ),
.I4(register_b[14]),
.O(store_data[14]));
LUT5 #(
.INIT(32'hFFFB0008))
memory_reg_3_i_3
(.I0(result[13]),
.I1(write_enable_reg_n_0),
.I2(\write_value[7]_i_2_n_0 ),
.I3(\write_value[7]_i_3_n_0 ),
.I4(register_b[13]),
.O(store_data[13]));
LUT5 #(
.INIT(32'hFFFB0008))
memory_reg_3_i_4
(.I0(result[12]),
.I1(write_enable_reg_n_0),
.I2(\write_value[7]_i_2_n_0 ),
.I3(\write_value[7]_i_3_n_0 ),
.I4(register_b[12]),
.O(store_data[12]));
(* IS_CLOCK_GATED *)
(* METHODOLOGY_DRC_VIOS = "{SYNTH-6 {cell *THIS*}}" *)
(* POWER_OPTED_CE = "ENARDEN=NEW" *)
(* RTL_RAM_BITS = "131104" *)
(* RTL_RAM_NAME = "memory" *)
(* bram_addr_begin = "0" *)
(* bram_addr_end = "8191" *)
(* bram_slice_begin = "16" *)
(* bram_slice_end = "19" *)
RAMB36E1 #(
.DOA_REG(0),
.DOB_REG(0),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("PERFORMANCE"),
.READ_WIDTH_A(4),
.READ_WIDTH_B(0),
.RSTREG_PRIORITY_A("RSTREG"),
.RSTREG_PRIORITY_B("RSTREG"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("READ_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(4),
.WRITE_WIDTH_B(0))
memory_reg_4
(.ADDRARDADDR({1'b1,\read_input[12]_i_1_n_0 ,\read_input[11]_i_1_n_0 ,\read_input[10]_i_1_n_0 ,\read_input[9]_i_1_n_0 ,\read_input[8]_i_1_n_0 ,\read_input[7]_i_1_n_0 ,\read_input[6]_i_1_n_0 ,\read_input[5]_i_1_n_0 ,\read_input[4]_i_1_n_0 ,\read_input[3]_i_1_n_0 ,\read_input[2]_i_1_n_0 ,\read_input[1]_i_1_n_0 ,\read_input[0]_i_1_n_0 ,1'b1,1'b1}),
.ADDRBWRADDR({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
.CASCADEINA(1'b1),
.CASCADEINB(1'b0),
.CASCADEOUTA(NLW_memory_reg_4_CASCADEOUTA_UNCONNECTED),
.CASCADEOUTB(NLW_memory_reg_4_CASCADEOUTB_UNCONNECTED),
.CLKARDCLK(ETH_CLK_OBUF),
.CLKBWRCLK(1'b0),
.DBITERR(NLW_memory_reg_4_DBITERR_UNCONNECTED),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,store_data[19:16]}),
.DIBDI({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
.DIPADIP({1'b0,1'b0,1'b0,1'b0}),
.DIPBDIP({1'b1,1'b1,1'b1,1'b1}),
.DOADO({NLW_memory_reg_4_DOADO_UNCONNECTED[31:4],load_data[19:16]}),
.DOBDO(NLW_memory_reg_4_DOBDO_UNCONNECTED[31:0]),
.DOPADOP(NLW_memory_reg_4_DOPADOP_UNCONNECTED[3:0]),
.DOPBDOP(NLW_memory_reg_4_DOPBDOP_UNCONNECTED[3:0]),
.ECCPARITY(NLW_memory_reg_4_ECCPARITY_UNCONNECTED[7:0]),
.ENARDEN(memory_reg_4_ENARDEN_cooolgate_en_sig_4),
.ENBWREN(1'b0),
.INJECTDBITERR(NLW_memory_reg_4_INJECTDBITERR_UNCONNECTED),
.INJECTSBITERR(NLW_memory_reg_4_INJECTSBITERR_UNCONNECTED),
.RDADDRECC(NLW_memory_reg_4_RDADDRECC_UNCONNECTED[8:0]),
.REGCEAREGCE(NLW_memory_reg_4_REGCEAREGCE_UNCONNECTED),
.REGCEB(NLW_memory_reg_4_REGCEB_UNCONNECTED),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(NLW_memory_reg_4_SBITERR_UNCONNECTED),
.WEA({1'b0,1'b0,1'b0,memory_reg_0_i_1_n_0}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
LUT4 #(
.INIT(16'hff02))
memory_reg_4_ENARDEN_cooolgate_en_gate_7
(.I0(\state[2]_i_1_n_0 ),
.I1(\state[1]_i_1_n_0 ),
.I2(INTERNAL_RST_reg),
.I3(memory_reg_0_i_1_n_0),
.O(memory_reg_4_ENARDEN_cooolgate_en_sig_4));
LUT5 #(
.INIT(32'hFFFB0008))
memory_reg_4_i_1
(.I0(result[19]),
.I1(write_enable_reg_n_0),
.I2(\write_value[7]_i_2_n_0 ),
.I3(\write_value[7]_i_3_n_0 ),
.I4(register_b[19]),
.O(store_data[19]));
LUT5 #(
.INIT(32'hFFFB0008))
memory_reg_4_i_2
(.I0(result[18]),
.I1(write_enable_reg_n_0),
.I2(\write_value[7]_i_2_n_0 ),
.I3(\write_value[7]_i_3_n_0 ),
.I4(register_b[18]),
.O(store_data[18]));
LUT5 #(
.INIT(32'hFFFB0008))
memory_reg_4_i_3
(.I0(result[17]),
.I1(write_enable_reg_n_0),
.I2(\write_value[7]_i_2_n_0 ),
.I3(\write_value[7]_i_3_n_0 ),
.I4(register_b[17]),
.O(store_data[17]));
LUT5 #(
.INIT(32'hFFFB0008))
memory_reg_4_i_4
(.I0(result[16]),
.I1(write_enable_reg_n_0),
.I2(\write_value[7]_i_2_n_0 ),
.I3(\write_value[7]_i_3_n_0 ),
.I4(register_b[16]),
.O(store_data[16]));
(* IS_CLOCK_GATED *)
(* METHODOLOGY_DRC_VIOS = "{SYNTH-6 {cell *THIS*}}" *)
(* POWER_OPTED_CE = "ENARDEN=NEW" *)
(* RTL_RAM_BITS = "131104" *)
(* RTL_RAM_NAME = "memory" *)
(* bram_addr_begin = "0" *)
(* bram_addr_end = "8191" *)
(* bram_slice_begin = "20" *)
(* bram_slice_end = "23" *)
RAMB36E1 #(
.DOA_REG(0),
.DOB_REG(0),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("PERFORMANCE"),
.READ_WIDTH_A(4),
.READ_WIDTH_B(0),
.RSTREG_PRIORITY_A("RSTREG"),
.RSTREG_PRIORITY_B("RSTREG"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("READ_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(4),
.WRITE_WIDTH_B(0))
memory_reg_5
(.ADDRARDADDR({1'b1,\read_input[12]_i_1_n_0 ,\read_input[11]_i_1_n_0 ,\read_input[10]_i_1_n_0 ,\read_input[9]_i_1_n_0 ,\read_input[8]_i_1_n_0 ,\read_input[7]_i_1_n_0 ,\read_input[6]_i_1_n_0 ,\read_input[5]_i_1_n_0 ,\read_input[4]_i_1_n_0 ,\read_input[3]_i_1_n_0 ,\read_input[2]_i_1_n_0 ,\read_input[1]_i_1_n_0 ,\read_input[0]_i_1_n_0 ,1'b1,1'b1}),
.ADDRBWRADDR({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
.CASCADEINA(1'b1),
.CASCADEINB(1'b0),
.CASCADEOUTA(NLW_memory_reg_5_CASCADEOUTA_UNCONNECTED),
.CASCADEOUTB(NLW_memory_reg_5_CASCADEOUTB_UNCONNECTED),
.CLKARDCLK(ETH_CLK_OBUF),
.CLKBWRCLK(1'b0),
.DBITERR(NLW_memory_reg_5_DBITERR_UNCONNECTED),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,store_data[23:20]}),
.DIBDI({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
.DIPADIP({1'b0,1'b0,1'b0,1'b0}),
.DIPBDIP({1'b1,1'b1,1'b1,1'b1}),
.DOADO({NLW_memory_reg_5_DOADO_UNCONNECTED[31:4],load_data[23:20]}),
.DOBDO(NLW_memory_reg_5_DOBDO_UNCONNECTED[31:0]),
.DOPADOP(NLW_memory_reg_5_DOPADOP_UNCONNECTED[3:0]),
.DOPBDOP(NLW_memory_reg_5_DOPBDOP_UNCONNECTED[3:0]),
.ECCPARITY(NLW_memory_reg_5_ECCPARITY_UNCONNECTED[7:0]),
.ENARDEN(memory_reg_5_ENARDEN_cooolgate_en_sig_5),
.ENBWREN(1'b0),
.INJECTDBITERR(NLW_memory_reg_5_INJECTDBITERR_UNCONNECTED),
.INJECTSBITERR(NLW_memory_reg_5_INJECTSBITERR_UNCONNECTED),
.RDADDRECC(NLW_memory_reg_5_RDADDRECC_UNCONNECTED[8:0]),
.REGCEAREGCE(NLW_memory_reg_5_REGCEAREGCE_UNCONNECTED),
.REGCEB(NLW_memory_reg_5_REGCEB_UNCONNECTED),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(NLW_memory_reg_5_SBITERR_UNCONNECTED),
.WEA({1'b0,1'b0,1'b0,memory_reg_0_i_1_n_0}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
LUT4 #(
.INIT(16'hff02))
memory_reg_5_ENARDEN_cooolgate_en_gate_9
(.I0(\state[2]_i_1_n_0 ),
.I1(\state[1]_i_1_n_0 ),
.I2(INTERNAL_RST_reg),
.I3(memory_reg_0_i_1_n_0),
.O(memory_reg_5_ENARDEN_cooolgate_en_sig_5));
LUT5 #(
.INIT(32'hFFFB0008))
memory_reg_5_i_1
(.I0(result[23]),
.I1(write_enable_reg_n_0),
.I2(\write_value[7]_i_2_n_0 ),
.I3(\write_value[7]_i_3_n_0 ),
.I4(register_b[23]),
.O(store_data[23]));
LUT5 #(
.INIT(32'hFFFB0008))
memory_reg_5_i_2
(.I0(result[22]),
.I1(write_enable_reg_n_0),
.I2(\write_value[7]_i_2_n_0 ),
.I3(\write_value[7]_i_3_n_0 ),
.I4(register_b[22]),
.O(store_data[22]));
LUT5 #(
.INIT(32'hFFFB0008))
memory_reg_5_i_3
(.I0(result[21]),
.I1(write_enable_reg_n_0),
.I2(\write_value[7]_i_2_n_0 ),
.I3(\write_value[7]_i_3_n_0 ),
.I4(register_b[21]),
.O(store_data[21]));
LUT5 #(
.INIT(32'hFFFB0008))
memory_reg_5_i_4
(.I0(result[20]),
.I1(write_enable_reg_n_0),
.I2(\write_value[7]_i_2_n_0 ),
.I3(\write_value[7]_i_3_n_0 ),
.I4(register_b[20]),
.O(store_data[20]));
(* IS_CLOCK_GATED *)
(* METHODOLOGY_DRC_VIOS = "{SYNTH-6 {cell *THIS*}}" *)
(* POWER_OPTED_CE = "ENARDEN=NEW" *)
(* RTL_RAM_BITS = "131104" *)
(* RTL_RAM_NAME = "memory" *)
(* bram_addr_begin = "0" *)
(* bram_addr_end = "8191" *)
(* bram_slice_begin = "24" *)
(* bram_slice_end = "27" *)
RAMB36E1 #(
.DOA_REG(0),
.DOB_REG(0),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("PERFORMANCE"),
.READ_WIDTH_A(4),
.READ_WIDTH_B(0),
.RSTREG_PRIORITY_A("RSTREG"),
.RSTREG_PRIORITY_B("RSTREG"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("READ_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(4),
.WRITE_WIDTH_B(0))
memory_reg_6
(.ADDRARDADDR({1'b1,\read_input[12]_i_1_n_0 ,\read_input[11]_i_1_n_0 ,\read_input[10]_i_1_n_0 ,\read_input[9]_i_1_n_0 ,\read_input[8]_i_1_n_0 ,\read_input[7]_i_1_n_0 ,\read_input[6]_i_1_n_0 ,\read_input[5]_i_1_n_0 ,\read_input[4]_i_1_n_0 ,\read_input[3]_i_1_n_0 ,\read_input[2]_i_1_n_0 ,\read_input[1]_i_1_n_0 ,\read_input[0]_i_1_n_0 ,1'b1,1'b1}),
.ADDRBWRADDR({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
.CASCADEINA(1'b1),
.CASCADEINB(1'b0),
.CASCADEOUTA(NLW_memory_reg_6_CASCADEOUTA_UNCONNECTED),
.CASCADEOUTB(NLW_memory_reg_6_CASCADEOUTB_UNCONNECTED),
.CLKARDCLK(ETH_CLK_OBUF),
.CLKBWRCLK(1'b0),
.DBITERR(NLW_memory_reg_6_DBITERR_UNCONNECTED),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,store_data[27:24]}),
.DIBDI({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
.DIPADIP({1'b0,1'b0,1'b0,1'b0}),
.DIPBDIP({1'b1,1'b1,1'b1,1'b1}),
.DOADO({NLW_memory_reg_6_DOADO_UNCONNECTED[31:4],load_data[27:24]}),
.DOBDO(NLW_memory_reg_6_DOBDO_UNCONNECTED[31:0]),
.DOPADOP(NLW_memory_reg_6_DOPADOP_UNCONNECTED[3:0]),
.DOPBDOP(NLW_memory_reg_6_DOPBDOP_UNCONNECTED[3:0]),
.ECCPARITY(NLW_memory_reg_6_ECCPARITY_UNCONNECTED[7:0]),
.ENARDEN(memory_reg_6_ENARDEN_cooolgate_en_sig_6),
.ENBWREN(1'b0),
.INJECTDBITERR(NLW_memory_reg_6_INJECTDBITERR_UNCONNECTED),
.INJECTSBITERR(NLW_memory_reg_6_INJECTSBITERR_UNCONNECTED),
.RDADDRECC(NLW_memory_reg_6_RDADDRECC_UNCONNECTED[8:0]),
.REGCEAREGCE(NLW_memory_reg_6_REGCEAREGCE_UNCONNECTED),
.REGCEB(NLW_memory_reg_6_REGCEB_UNCONNECTED),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(NLW_memory_reg_6_SBITERR_UNCONNECTED),
.WEA({1'b0,1'b0,1'b0,memory_reg_0_i_1_n_0}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
LUT4 #(
.INIT(16'hff02))
memory_reg_6_ENARDEN_cooolgate_en_gate_11
(.I0(\state[2]_i_1_n_0 ),
.I1(\state[1]_i_1_n_0 ),
.I2(INTERNAL_RST_reg),
.I3(memory_reg_0_i_1_n_0),
.O(memory_reg_6_ENARDEN_cooolgate_en_sig_6));
LUT5 #(
.INIT(32'hFFFB0008))
memory_reg_6_i_1
(.I0(result[27]),
.I1(write_enable_reg_n_0),
.I2(\write_value[7]_i_2_n_0 ),
.I3(\write_value[7]_i_3_n_0 ),
.I4(register_b[27]),
.O(store_data[27]));
LUT3 #(
.INIT(8'hB8))
memory_reg_6_i_2
(.I0(result[26]),
.I1(operand_b1),
.I2(register_b[26]),
.O(store_data[26]));
LUT3 #(
.INIT(8'hB8))
memory_reg_6_i_3
(.I0(result[25]),
.I1(operand_b1),
.I2(register_b[25]),
.O(store_data[25]));
LUT3 #(
.INIT(8'hB8))
memory_reg_6_i_4
(.I0(result[24]),
.I1(operand_b1),
.I2(register_b[24]),
.O(store_data[24]));
(* IS_CLOCK_GATED *)
(* METHODOLOGY_DRC_VIOS = "{SYNTH-6 {cell *THIS*}}" *)
(* POWER_OPTED_CE = "ENARDEN=NEW" *)
(* RTL_RAM_BITS = "131104" *)
(* RTL_RAM_NAME = "memory" *)
(* bram_addr_begin = "0" *)
(* bram_addr_end = "8191" *)
(* bram_slice_begin = "28" *)
(* bram_slice_end = "31" *)
RAMB36E1 #(
.DOA_REG(0),
.DOB_REG(0),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("PERFORMANCE"),
.READ_WIDTH_A(4),
.READ_WIDTH_B(0),
.RSTREG_PRIORITY_A("RSTREG"),
.RSTREG_PRIORITY_B("RSTREG"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("READ_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(4),
.WRITE_WIDTH_B(0))
memory_reg_7
(.ADDRARDADDR({1'b1,\read_input[12]_i_1_n_0 ,\read_input[11]_i_1_n_0 ,\read_input[10]_i_1_n_0 ,\read_input[9]_i_1_n_0 ,\read_input[8]_i_1_n_0 ,\read_input[7]_i_1_n_0 ,\read_input[6]_i_1_n_0 ,\read_input[5]_i_1_n_0 ,\read_input[4]_i_1_n_0 ,\read_input[3]_i_1_n_0 ,\read_input[2]_i_1_n_0 ,\read_input[1]_i_1_n_0 ,\read_input[0]_i_1_n_0 ,1'b1,1'b1}),
.ADDRBWRADDR({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
.CASCADEINA(1'b1),
.CASCADEINB(1'b0),
.CASCADEOUTA(NLW_memory_reg_7_CASCADEOUTA_UNCONNECTED),
.CASCADEOUTB(NLW_memory_reg_7_CASCADEOUTB_UNCONNECTED),
.CLKARDCLK(ETH_CLK_OBUF),
.CLKBWRCLK(1'b0),
.DBITERR(NLW_memory_reg_7_DBITERR_UNCONNECTED),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,store_data[31:28]}),
.DIBDI({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
.DIPADIP({1'b0,1'b0,1'b0,1'b0}),
.DIPBDIP({1'b1,1'b1,1'b1,1'b1}),
.DOADO({NLW_memory_reg_7_DOADO_UNCONNECTED[31:4],load_data[31:28]}),
.DOBDO(NLW_memory_reg_7_DOBDO_UNCONNECTED[31:0]),
.DOPADOP(NLW_memory_reg_7_DOPADOP_UNCONNECTED[3:0]),
.DOPBDOP(NLW_memory_reg_7_DOPBDOP_UNCONNECTED[3:0]),
.ECCPARITY(NLW_memory_reg_7_ECCPARITY_UNCONNECTED[7:0]),
.ENARDEN(memory_reg_7_ENARDEN_cooolgate_en_sig_7),
.ENBWREN(1'b0),
.INJECTDBITERR(NLW_memory_reg_7_INJECTDBITERR_UNCONNECTED),
.INJECTSBITERR(NLW_memory_reg_7_INJECTSBITERR_UNCONNECTED),
.RDADDRECC(NLW_memory_reg_7_RDADDRECC_UNCONNECTED[8:0]),
.REGCEAREGCE(NLW_memory_reg_7_REGCEAREGCE_UNCONNECTED),
.REGCEB(NLW_memory_reg_7_REGCEB_UNCONNECTED),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(NLW_memory_reg_7_SBITERR_UNCONNECTED),
.WEA({1'b0,1'b0,1'b0,memory_reg_0_i_1_n_0}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
LUT4 #(
.INIT(16'hff02))
memory_reg_7_ENARDEN_cooolgate_en_gate_13
(.I0(\state[2]_i_1_n_0 ),
.I1(\state[1]_i_1_n_0 ),
.I2(INTERNAL_RST_reg),
.I3(memory_reg_0_i_1_n_0),
.O(memory_reg_7_ENARDEN_cooolgate_en_sig_7));
LUT5 #(
.INIT(32'hFFFB0008))
memory_reg_7_i_1
(.I0(result[31]),
.I1(write_enable_reg_n_0),
.I2(\write_value[7]_i_2_n_0 ),
.I3(\write_value[7]_i_3_n_0 ),
.I4(register_b[31]),
.O(store_data[31]));
LUT5 #(
.INIT(32'hFFFB0008))
memory_reg_7_i_2
(.I0(result[30]),
.I1(write_enable_reg_n_0),
.I2(\write_value[7]_i_2_n_0 ),
.I3(\write_value[7]_i_3_n_0 ),
.I4(register_b[30]),
.O(store_data[30]));
LUT5 #(
.INIT(32'hFFFB0008))
memory_reg_7_i_3
(.I0(result[29]),
.I1(write_enable_reg_n_0),
.I2(\write_value[7]_i_2_n_0 ),
.I3(\write_value[7]_i_3_n_0 ),
.I4(register_b[29]),
.O(store_data[29]));
LUT3 #(
.INIT(8'hB8))
memory_reg_7_i_4
(.I0(result[28]),
.I1(operand_b1),
.I2(register_b[28]),
.O(store_data[28]));
FDRE \opcode_2_reg[0]
(.C(ETH_CLK_OBUF),
.CE(opcode_20),
.D(opcode[0]),
.Q(opcode_2[0]),
.R(1'b0));
FDRE \opcode_2_reg[1]
(.C(ETH_CLK_OBUF),
.CE(opcode_20),
.D(opcode[1]),
.Q(opcode_2[1]),
.R(1'b0));
FDRE \opcode_2_reg[2]
(.C(ETH_CLK_OBUF),
.CE(opcode_20),
.D(opcode[2]),
.Q(opcode_2[2]),
.R(1'b0));
FDRE \opcode_2_reg[3]
(.C(ETH_CLK_OBUF),
.CE(opcode_20),
.D(opcode[3]),
.Q(opcode_2[3]),
.R(1'b0));
FDRE \opcode_2_reg[4]
(.C(ETH_CLK_OBUF),
.CE(opcode_20),
.D(opcode[4]),
.Q(opcode_2[4]),
.R(1'b0));
LUT6 #(
.INIT(64'h111111111111FFF1))
\program_counter[0]_i_1
(.I0(\program_counter[15]_i_3_n_0 ),
.I1(\program_counter_reg_n_0_[0] ),
.I2(\read_input[31]_i_3_n_0 ),
.I3(\program_counter[0]_i_2_n_0 ),
.I4(\program_counter[0]_i_3_n_0 ),
.I5(\program_counter[0]_i_4_n_0 ),
.O(sel[0]));
LUT6 #(
.INIT(64'h000000000000C5CC))
\program_counter[0]_i_2
(.I0(\program_counter_reg_n_0_[0] ),
.I1(address_b_2[0]),
.I2(\program_counter[15]_i_8_n_0 ),
.I3(opcode_2[2]),
.I4(opcode_2[4]),
.I5(opcode_2[3]),
.O(\program_counter[0]_i_2_n_0 ));
LUT6 #(
.INIT(64'hAAA2AAAA8AA2AAAA))
\program_counter[0]_i_3
(.I0(\program_counter[15]_i_13_n_0 ),
.I1(opcode_2[3]),
.I2(opcode_2[2]),
.I3(opcode_2[4]),
.I4(address_b_2[0]),
.I5(\program_counter[15]_i_8_n_0 ),
.O(\program_counter[0]_i_3_n_0 ));
LUT6 #(
.INIT(64'h0000FF1DFFFFFFFF))
\program_counter[0]_i_4
(.I0(register_a[0]),
.I1(operand_a1),
.I2(result[0]),
.I3(\program_counter[15]_i_14_n_0 ),
.I4(opcode_2[0]),
.I5(\program_counter[15]_i_15_n_0 ),
.O(\program_counter[0]_i_4_n_0 ));
LUT6 #(
.INIT(64'h444F444F444F4444))
\program_counter[10]_i_1
(.I0(\program_counter[15]_i_3_n_0 ),
.I1(\program_counter_reg[12]_i_2_n_6 ),
.I2(\program_counter[10]_i_2_n_0 ),
.I3(\program_counter[10]_i_3_n_0 ),
.I4(\read_input[31]_i_3_n_0 ),
.I5(\program_counter[10]_i_4_n_0 ),
.O(sel[10]));
LUT6 #(
.INIT(64'hAAA2AAAA8AA2AAAA))
\program_counter[10]_i_2
(.I0(\program_counter[15]_i_13_n_0 ),
.I1(opcode_2[3]),
.I2(opcode_2[2]),
.I3(opcode_2[4]),
.I4(data7[26]),
.I5(\program_counter[15]_i_8_n_0 ),
.O(\program_counter[10]_i_2_n_0 ));
LUT6 #(
.INIT(64'h0000FF1DFFFFFFFF))
\program_counter[10]_i_3
(.I0(register_a[10]),
.I1(operand_a1),
.I2(result[10]),
.I3(\program_counter[15]_i_14_n_0 ),
.I4(opcode_2[0]),
.I5(\program_counter[15]_i_15_n_0 ),
.O(\program_counter[10]_i_3_n_0 ));
LUT6 #(
.INIT(64'h1010101011001010))
\program_counter[10]_i_4
(.I0(opcode_2[4]),
.I1(opcode_2[3]),
.I2(data7[26]),
.I3(\program_counter_reg[12]_i_2_n_6 ),
.I4(opcode_2[2]),
.I5(\program_counter[15]_i_8_n_0 ),
.O(\program_counter[10]_i_4_n_0 ));
LUT6 #(
.INIT(64'h444F444F444F4444))
\program_counter[11]_i_1
(.I0(\program_counter[15]_i_3_n_0 ),
.I1(\program_counter_reg[12]_i_2_n_5 ),
.I2(\program_counter[11]_i_2_n_0 ),
.I3(\program_counter[11]_i_3_n_0 ),
.I4(\read_input[31]_i_3_n_0 ),
.I5(\program_counter[11]_i_4_n_0 ),
.O(sel[11]));
LUT6 #(
.INIT(64'hAAA2AAAA8AA2AAAA))
\program_counter[11]_i_2
(.I0(\program_counter[15]_i_13_n_0 ),
.I1(opcode_2[3]),
.I2(opcode_2[2]),
.I3(opcode_2[4]),
.I4(data7[27]),
.I5(\program_counter[15]_i_8_n_0 ),
.O(\program_counter[11]_i_2_n_0 ));
LUT6 #(
.INIT(64'h0000FF1DFFFFFFFF))
\program_counter[11]_i_3
(.I0(register_a[11]),
.I1(operand_a1),
.I2(result[11]),
.I3(\program_counter[15]_i_14_n_0 ),
.I4(opcode_2[0]),
.I5(\program_counter[15]_i_15_n_0 ),
.O(\program_counter[11]_i_3_n_0 ));
LUT6 #(
.INIT(64'h1010101011001010))
\program_counter[11]_i_4
(.I0(opcode_2[4]),
.I1(opcode_2[3]),
.I2(data7[27]),
.I3(\program_counter_reg[12]_i_2_n_5 ),
.I4(opcode_2[2]),
.I5(\program_counter[15]_i_8_n_0 ),
.O(\program_counter[11]_i_4_n_0 ));
LUT6 #(
.INIT(64'h444F444F444F4444))
\program_counter[12]_i_1
(.I0(\program_counter[15]_i_3_n_0 ),
.I1(\program_counter_reg[12]_i_2_n_4 ),
.I2(\program_counter[12]_i_3_n_0 ),
.I3(\program_counter[12]_i_4_n_0 ),
.I4(\read_input[31]_i_3_n_0 ),
.I5(\program_counter[12]_i_5_n_0 ),
.O(sel[12]));
LUT6 #(
.INIT(64'hAAA2AAAA8AA2AAAA))
\program_counter[12]_i_3
(.I0(\program_counter[15]_i_13_n_0 ),
.I1(opcode_2[3]),
.I2(opcode_2[2]),
.I3(opcode_2[4]),
.I4(data7[28]),
.I5(\program_counter[15]_i_8_n_0 ),
.O(\program_counter[12]_i_3_n_0 ));
LUT6 #(
.INIT(64'h0000FF1DFFFFFFFF))
\program_counter[12]_i_4
(.I0(register_a[12]),
.I1(operand_a1),
.I2(result[12]),
.I3(\program_counter[15]_i_14_n_0 ),
.I4(opcode_2[0]),
.I5(\program_counter[15]_i_15_n_0 ),
.O(\program_counter[12]_i_4_n_0 ));
LUT6 #(
.INIT(64'h1010101011001010))
\program_counter[12]_i_5
(.I0(opcode_2[4]),
.I1(opcode_2[3]),
.I2(data7[28]),
.I3(\program_counter_reg[12]_i_2_n_4 ),
.I4(opcode_2[2]),
.I5(\program_counter[15]_i_8_n_0 ),
.O(\program_counter[12]_i_5_n_0 ));
LUT6 #(
.INIT(64'h1110FFFF11101110))
\program_counter[13]_i_1
(.I0(\program_counter[13]_i_2_n_0 ),
.I1(\program_counter[13]_i_3_n_0 ),
.I2(\read_input[31]_i_3_n_0 ),
.I3(\program_counter[13]_i_4_n_0 ),
.I4(\program_counter[15]_i_3_n_0 ),
.I5(\program_counter_reg[15]_i_4_n_7 ),
.O(sel[13]));
LUT6 #(
.INIT(64'hAAA2AAAA8AA2AAAA))
\program_counter[13]_i_2
(.I0(\program_counter[15]_i_13_n_0 ),
.I1(opcode_2[3]),
.I2(opcode_2[2]),
.I3(opcode_2[4]),
.I4(data7[29]),
.I5(\program_counter[15]_i_8_n_0 ),
.O(\program_counter[13]_i_2_n_0 ));
LUT6 #(
.INIT(64'h0000FF1DFFFFFFFF))
\program_counter[13]_i_3
(.I0(register_a[13]),
.I1(operand_a1),
.I2(result[13]),
.I3(\program_counter[15]_i_14_n_0 ),
.I4(opcode_2[0]),
.I5(\program_counter[15]_i_15_n_0 ),
.O(\program_counter[13]_i_3_n_0 ));
LUT6 #(
.INIT(64'h000000000000CACC))
\program_counter[13]_i_4
(.I0(\program_counter_reg[15]_i_4_n_7 ),
.I1(data7[29]),
.I2(\program_counter[15]_i_8_n_0 ),
.I3(opcode_2[2]),
.I4(opcode_2[4]),
.I5(opcode_2[3]),
.O(\program_counter[13]_i_4_n_0 ));
LUT6 #(
.INIT(64'h444F444F444F4444))
\program_counter[14]_i_1
(.I0(\program_counter[15]_i_3_n_0 ),
.I1(\program_counter_reg[15]_i_4_n_6 ),
.I2(\program_counter[14]_i_2_n_0 ),
.I3(\program_counter[14]_i_3_n_0 ),
.I4(\read_input[31]_i_3_n_0 ),
.I5(\program_counter[14]_i_4_n_0 ),
.O(sel[14]));
LUT6 #(
.INIT(64'hAAA2AAAA8AA2AAAA))
\program_counter[14]_i_2
(.I0(\program_counter[15]_i_13_n_0 ),
.I1(opcode_2[3]),
.I2(opcode_2[2]),
.I3(opcode_2[4]),
.I4(data7[30]),
.I5(\program_counter[15]_i_8_n_0 ),
.O(\program_counter[14]_i_2_n_0 ));
LUT6 #(
.INIT(64'h0000FF1DFFFFFFFF))
\program_counter[14]_i_3
(.I0(register_a[14]),
.I1(operand_a1),
.I2(result[14]),
.I3(\program_counter[15]_i_14_n_0 ),
.I4(opcode_2[0]),
.I5(\program_counter[15]_i_15_n_0 ),
.O(\program_counter[14]_i_3_n_0 ));
LUT6 #(
.INIT(64'h000000000000BA8A))
\program_counter[14]_i_4
(.I0(data7[30]),
.I1(\program_counter[15]_i_8_n_0 ),
.I2(opcode_2[2]),
.I3(\program_counter_reg[15]_i_4_n_6 ),
.I4(opcode_2[4]),
.I5(opcode_2[3]),
.O(\program_counter[14]_i_4_n_0 ));
LUT3 #(
.INIT(8'h32))
\program_counter[15]_i_1
(.I0(\state_reg_n_0_[1] ),
.I1(\state_reg_n_0_[2] ),
.I2(\state_reg_n_0_[0] ),
.O(instruction0));
LUT2 #(
.INIT(4'h2))
\program_counter[15]_i_13
(.I0(opcode_2[0]),
.I1(opcode_2[1]),
.O(\program_counter[15]_i_13_n_0 ));
LUT4 #(
.INIT(16'hEFFF))
\program_counter[15]_i_14
(.I0(opcode_2[2]),
.I1(opcode_2[4]),
.I2(opcode_2[1]),
.I3(opcode_2[3]),
.O(\program_counter[15]_i_14_n_0 ));
LUT2 #(
.INIT(4'h8))
\program_counter[15]_i_15
(.I0(\state_reg_n_0_[0] ),
.I1(\state_reg_n_0_[1] ),
.O(\program_counter[15]_i_15_n_0 ));
LUT6 #(
.INIT(64'h0000000000000001))
\program_counter[15]_i_16
(.I0(\read_input[10]_i_1_n_0 ),
.I1(\read_input[9]_i_1_n_0 ),
.I2(\read_input[14]_i_1_n_0 ),
.I3(\read_input[15]_i_1_n_0 ),
.I4(\read_input[12]_i_1_n_0 ),
.I5(\read_input[13]_i_1_n_0 ),
.O(\program_counter[15]_i_16_n_0 ));
LUT6 #(
.INIT(64'h0000000000000001))
\program_counter[15]_i_17
(.I0(\read_input[24]_i_1_n_0 ),
.I1(\read_input[23]_i_1_n_0 ),
.I2(\read_input[28]_i_1_n_0 ),
.I3(\read_input[29]_i_1_n_0 ),
.I4(\read_input[25]_i_1_n_0 ),
.I5(\read_input[26]_i_1_n_0 ),
.O(\program_counter[15]_i_17_n_0 ));
LUT6 #(
.INIT(64'h0001000000010101))
\program_counter[15]_i_18
(.I0(\read_input[2]_i_1_n_0 ),
.I1(\read_input[1]_i_1_n_0 ),
.I2(\read_input[8]_i_1_n_0 ),
.I3(result[4]),
.I4(operand_a1),
.I5(register_a[4]),
.O(\program_counter[15]_i_18_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFFFFFFFFFE))
\program_counter[15]_i_19
(.I0(\read_input[11]_i_1_n_0 ),
.I1(\read_input[7]_i_1_n_0 ),
.I2(\read_input[18]_i_1_n_0 ),
.I3(\read_input[19]_i_1_n_0 ),
.I4(\read_input[16]_i_1_n_0 ),
.I5(\read_input[17]_i_1_n_0 ),
.O(\program_counter[15]_i_19_n_0 ));
LUT6 #(
.INIT(64'h444F444F444F4444))
\program_counter[15]_i_2
(.I0(\program_counter[15]_i_3_n_0 ),
.I1(\program_counter_reg[15]_i_4_n_5 ),
.I2(\program_counter[15]_i_5_n_0 ),
.I3(\program_counter[15]_i_6_n_0 ),
.I4(\read_input[31]_i_3_n_0 ),
.I5(\program_counter[15]_i_7_n_0 ),
.O(sel[15]));
LUT6 #(
.INIT(64'hFFFFFFFFFFFFFFFE))
\program_counter[15]_i_20
(.I0(\read_input[21]_i_1_n_0 ),
.I1(\read_input[20]_i_1_n_0 ),
.I2(\read_input[30]_i_1_n_0 ),
.I3(\read_input[31]_i_2_n_0 ),
.I4(\read_input[22]_i_1_n_0 ),
.I5(\read_input[27]_i_1_n_0 ),
.O(\program_counter[15]_i_20_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFFFFFFEFEA))
\program_counter[15]_i_21
(.I0(\read_input[3]_i_1_n_0 ),
.I1(result[0]),
.I2(operand_a1),
.I3(register_a[0]),
.I4(\read_input[6]_i_1_n_0 ),
.I5(\read_input[5]_i_1_n_0 ),
.O(\program_counter[15]_i_21_n_0 ));
LUT5 #(
.INIT(32'h00000B4B))
\program_counter[15]_i_3
(.I0(opcode_2[1]),
.I1(opcode_2[2]),
.I2(opcode_2[4]),
.I3(\program_counter[15]_i_8_n_0 ),
.I4(\program_counter[15]_i_9_n_0 ),
.O(\program_counter[15]_i_3_n_0 ));
LUT6 #(
.INIT(64'hAAA2AAAA8AA2AAAA))
\program_counter[15]_i_5
(.I0(\program_counter[15]_i_13_n_0 ),
.I1(opcode_2[3]),
.I2(opcode_2[2]),
.I3(opcode_2[4]),
.I4(data7[31]),
.I5(\program_counter[15]_i_8_n_0 ),
.O(\program_counter[15]_i_5_n_0 ));
LUT6 #(
.INIT(64'h0000FF1DFFFFFFFF))
\program_counter[15]_i_6
(.I0(register_a[15]),
.I1(operand_a1),
.I2(result[15]),
.I3(\program_counter[15]_i_14_n_0 ),
.I4(opcode_2[0]),
.I5(\program_counter[15]_i_15_n_0 ),
.O(\program_counter[15]_i_6_n_0 ));
LUT6 #(
.INIT(64'h000000000000BA8A))
\program_counter[15]_i_7
(.I0(data7[31]),
.I1(\program_counter[15]_i_8_n_0 ),
.I2(opcode_2[2]),
.I3(\program_counter_reg[15]_i_4_n_5 ),
.I4(opcode_2[4]),
.I5(opcode_2[3]),
.O(\program_counter[15]_i_7_n_0 ));
LUT6 #(
.INIT(64'h0000000000000080))
\program_counter[15]_i_8
(.I0(\program_counter[15]_i_16_n_0 ),
.I1(\program_counter[15]_i_17_n_0 ),
.I2(\program_counter[15]_i_18_n_0 ),
.I3(\program_counter[15]_i_19_n_0 ),
.I4(\program_counter[15]_i_20_n_0 ),
.I5(\program_counter[15]_i_21_n_0 ),
.O(\program_counter[15]_i_8_n_0 ));
LUT6 #(
.INIT(64'hFFBFBFFF3FFF7FFF))
\program_counter[15]_i_9
(.I0(opcode_2[2]),
.I1(\state_reg_n_0_[0] ),
.I2(\state_reg_n_0_[1] ),
.I3(opcode_2[0]),
.I4(opcode_2[1]),
.I5(opcode_2[3]),
.O(\program_counter[15]_i_9_n_0 ));
LUT6 #(
.INIT(64'h444F444F444F4444))
\program_counter[1]_i_1
(.I0(\program_counter[15]_i_3_n_0 ),
.I1(\program_counter_reg[4]_i_2_n_7 ),
.I2(\program_counter[1]_i_2_n_0 ),
.I3(\program_counter[1]_i_3_n_0 ),
.I4(\read_input[31]_i_3_n_0 ),
.I5(\program_counter[1]_i_4_n_0 ),
.O(sel[1]));
LUT6 #(
.INIT(64'hAAA2AAAA8AA2AAAA))
\program_counter[1]_i_2
(.I0(\program_counter[15]_i_13_n_0 ),
.I1(opcode_2[3]),
.I2(opcode_2[2]),
.I3(opcode_2[4]),
.I4(address_b_2[1]),
.I5(\program_counter[15]_i_8_n_0 ),
.O(\program_counter[1]_i_2_n_0 ));
LUT6 #(
.INIT(64'h0000FF1DFFFFFFFF))
\program_counter[1]_i_3
(.I0(register_a[1]),
.I1(operand_a1),
.I2(result[1]),
.I3(\program_counter[15]_i_14_n_0 ),
.I4(opcode_2[0]),
.I5(\program_counter[15]_i_15_n_0 ),
.O(\program_counter[1]_i_3_n_0 ));
LUT6 #(
.INIT(64'h000000000000BA8A))
\program_counter[1]_i_4
(.I0(address_b_2[1]),
.I1(\program_counter[15]_i_8_n_0 ),
.I2(opcode_2[2]),
.I3(\program_counter_reg[4]_i_2_n_7 ),
.I4(opcode_2[4]),
.I5(opcode_2[3]),
.O(\program_counter[1]_i_4_n_0 ));
LUT6 #(
.INIT(64'h444F444F444F4444))
\program_counter[2]_i_1
(.I0(\program_counter[15]_i_3_n_0 ),
.I1(\program_counter_reg[4]_i_2_n_6 ),
.I2(\program_counter[2]_i_2_n_0 ),
.I3(\program_counter[2]_i_3_n_0 ),
.I4(\read_input[31]_i_3_n_0 ),
.I5(\program_counter[2]_i_4_n_0 ),
.O(sel[2]));
LUT6 #(
.INIT(64'hAAA2AAAA8AA2AAAA))
\program_counter[2]_i_2
(.I0(\program_counter[15]_i_13_n_0 ),
.I1(opcode_2[3]),
.I2(opcode_2[2]),
.I3(opcode_2[4]),
.I4(address_b_2[2]),
.I5(\program_counter[15]_i_8_n_0 ),
.O(\program_counter[2]_i_2_n_0 ));
LUT6 #(
.INIT(64'h0000FF1DFFFFFFFF))
\program_counter[2]_i_3
(.I0(register_a[2]),
.I1(operand_a1),
.I2(result[2]),
.I3(\program_counter[15]_i_14_n_0 ),
.I4(opcode_2[0]),
.I5(\program_counter[15]_i_15_n_0 ),
.O(\program_counter[2]_i_3_n_0 ));
LUT6 #(
.INIT(64'h000000000000BA8A))
\program_counter[2]_i_4
(.I0(address_b_2[2]),
.I1(\program_counter[15]_i_8_n_0 ),
.I2(opcode_2[2]),
.I3(\program_counter_reg[4]_i_2_n_6 ),
.I4(opcode_2[4]),
.I5(opcode_2[3]),
.O(\program_counter[2]_i_4_n_0 ));
LUT6 #(
.INIT(64'h1110FFFF11101110))
\program_counter[3]_i_1
(.I0(\program_counter[3]_i_2_n_0 ),
.I1(\program_counter[3]_i_3_n_0 ),
.I2(\read_input[31]_i_3_n_0 ),
.I3(\program_counter[3]_i_4_n_0 ),
.I4(\program_counter[15]_i_3_n_0 ),
.I5(\program_counter_reg[4]_i_2_n_5 ),
.O(sel[3]));
LUT6 #(
.INIT(64'hAAA2AAAA8AA2AAAA))
\program_counter[3]_i_2
(.I0(\program_counter[15]_i_13_n_0 ),
.I1(opcode_2[3]),
.I2(opcode_2[2]),
.I3(opcode_2[4]),
.I4(address_b_2[3]),
.I5(\program_counter[15]_i_8_n_0 ),
.O(\program_counter[3]_i_2_n_0 ));
LUT6 #(
.INIT(64'h0000FF1DFFFFFFFF))
\program_counter[3]_i_3
(.I0(register_a[3]),
.I1(operand_a1),
.I2(result[3]),
.I3(\program_counter[15]_i_14_n_0 ),
.I4(opcode_2[0]),
.I5(\program_counter[15]_i_15_n_0 ),
.O(\program_counter[3]_i_3_n_0 ));
LUT6 #(
.INIT(64'h000000000000CACC))
\program_counter[3]_i_4
(.I0(\program_counter_reg[4]_i_2_n_5 ),
.I1(address_b_2[3]),
.I2(\program_counter[15]_i_8_n_0 ),
.I3(opcode_2[2]),
.I4(opcode_2[4]),
.I5(opcode_2[3]),
.O(\program_counter[3]_i_4_n_0 ));
LUT6 #(
.INIT(64'h444F444F444F4444))
\program_counter[4]_i_1
(.I0(\program_counter[15]_i_3_n_0 ),
.I1(\program_counter_reg[4]_i_2_n_4 ),
.I2(\program_counter[4]_i_3_n_0 ),
.I3(\program_counter[4]_i_4_n_0 ),
.I4(\read_input[31]_i_3_n_0 ),
.I5(\program_counter[4]_i_5_n_0 ),
.O(sel[4]));
LUT6 #(
.INIT(64'hAAA2AAAA8AA2AAAA))
\program_counter[4]_i_3
(.I0(\program_counter[15]_i_13_n_0 ),
.I1(opcode_2[3]),
.I2(opcode_2[2]),
.I3(opcode_2[4]),
.I4(data7[20]),
.I5(\program_counter[15]_i_8_n_0 ),
.O(\program_counter[4]_i_3_n_0 ));
LUT6 #(
.INIT(64'h0000FF1DFFFFFFFF))
\program_counter[4]_i_4
(.I0(register_a[4]),
.I1(operand_a1),
.I2(result[4]),
.I3(\program_counter[15]_i_14_n_0 ),
.I4(opcode_2[0]),
.I5(\program_counter[15]_i_15_n_0 ),
.O(\program_counter[4]_i_4_n_0 ));
LUT6 #(
.INIT(64'h000000000000CACC))
\program_counter[4]_i_5
(.I0(\program_counter_reg[4]_i_2_n_4 ),
.I1(data7[20]),
.I2(\program_counter[15]_i_8_n_0 ),
.I3(opcode_2[2]),
.I4(opcode_2[4]),
.I5(opcode_2[3]),
.O(\program_counter[4]_i_5_n_0 ));
LUT6 #(
.INIT(64'h444F444F444F4444))
\program_counter[5]_i_1
(.I0(\program_counter[15]_i_3_n_0 ),
.I1(\program_counter_reg[8]_i_2_n_7 ),
.I2(\program_counter[5]_i_2_n_0 ),
.I3(\program_counter[5]_i_3_n_0 ),
.I4(\read_input[31]_i_3_n_0 ),
.I5(\program_counter[5]_i_4_n_0 ),
.O(sel[5]));
LUT6 #(
.INIT(64'hAAA2AAAA8AA2AAAA))
\program_counter[5]_i_2
(.I0(\program_counter[15]_i_13_n_0 ),
.I1(opcode_2[3]),
.I2(opcode_2[2]),
.I3(opcode_2[4]),
.I4(data7[21]),
.I5(\program_counter[15]_i_8_n_0 ),
.O(\program_counter[5]_i_2_n_0 ));
LUT6 #(
.INIT(64'h0000FF1DFFFFFFFF))
\program_counter[5]_i_3
(.I0(register_a[5]),
.I1(operand_a1),
.I2(result[5]),
.I3(\program_counter[15]_i_14_n_0 ),
.I4(opcode_2[0]),
.I5(\program_counter[15]_i_15_n_0 ),
.O(\program_counter[5]_i_3_n_0 ));
LUT6 #(
.INIT(64'h000000000000BA8A))
\program_counter[5]_i_4
(.I0(data7[21]),
.I1(\program_counter[15]_i_8_n_0 ),
.I2(opcode_2[2]),
.I3(\program_counter_reg[8]_i_2_n_7 ),
.I4(opcode_2[4]),
.I5(opcode_2[3]),
.O(\program_counter[5]_i_4_n_0 ));
LUT6 #(
.INIT(64'h444F444F444F4444))
\program_counter[6]_i_1
(.I0(\program_counter[15]_i_3_n_0 ),
.I1(\program_counter_reg[8]_i_2_n_6 ),
.I2(\program_counter[6]_i_2_n_0 ),
.I3(\program_counter[6]_i_3_n_0 ),
.I4(\read_input[31]_i_3_n_0 ),
.I5(\program_counter[6]_i_4_n_0 ),
.O(sel[6]));
LUT6 #(
.INIT(64'hAAA2AAAA8AA2AAAA))
\program_counter[6]_i_2
(.I0(\program_counter[15]_i_13_n_0 ),
.I1(opcode_2[3]),
.I2(opcode_2[2]),
.I3(opcode_2[4]),
.I4(data7[22]),
.I5(\program_counter[15]_i_8_n_0 ),
.O(\program_counter[6]_i_2_n_0 ));
LUT6 #(
.INIT(64'h0000FF1DFFFFFFFF))
\program_counter[6]_i_3
(.I0(register_a[6]),
.I1(operand_a1),
.I2(result[6]),
.I3(\program_counter[15]_i_14_n_0 ),
.I4(opcode_2[0]),
.I5(\program_counter[15]_i_15_n_0 ),
.O(\program_counter[6]_i_3_n_0 ));
LUT6 #(
.INIT(64'h000000000000BA8A))
\program_counter[6]_i_4
(.I0(data7[22]),
.I1(\program_counter[15]_i_8_n_0 ),
.I2(opcode_2[2]),
.I3(\program_counter_reg[8]_i_2_n_6 ),
.I4(opcode_2[4]),
.I5(opcode_2[3]),
.O(\program_counter[6]_i_4_n_0 ));
LUT6 #(
.INIT(64'h444F444F444F4444))
\program_counter[7]_i_1
(.I0(\program_counter[15]_i_3_n_0 ),
.I1(\program_counter_reg[8]_i_2_n_5 ),
.I2(\program_counter[7]_i_2_n_0 ),
.I3(\program_counter[7]_i_3_n_0 ),
.I4(\read_input[31]_i_3_n_0 ),
.I5(\program_counter[7]_i_4_n_0 ),
.O(sel[7]));
LUT6 #(
.INIT(64'hAAA2AAAA8AA2AAAA))
\program_counter[7]_i_2
(.I0(\program_counter[15]_i_13_n_0 ),
.I1(opcode_2[3]),
.I2(opcode_2[2]),
.I3(opcode_2[4]),
.I4(data7[23]),
.I5(\program_counter[15]_i_8_n_0 ),
.O(\program_counter[7]_i_2_n_0 ));
LUT6 #(
.INIT(64'h0000FF1DFFFFFFFF))
\program_counter[7]_i_3
(.I0(register_a[7]),
.I1(operand_a1),
.I2(result[7]),
.I3(\program_counter[15]_i_14_n_0 ),
.I4(opcode_2[0]),
.I5(\program_counter[15]_i_15_n_0 ),
.O(\program_counter[7]_i_3_n_0 ));
LUT6 #(
.INIT(64'h000000000000BA8A))
\program_counter[7]_i_4
(.I0(data7[23]),
.I1(\program_counter[15]_i_8_n_0 ),
.I2(opcode_2[2]),
.I3(\program_counter_reg[8]_i_2_n_5 ),
.I4(opcode_2[4]),
.I5(opcode_2[3]),
.O(\program_counter[7]_i_4_n_0 ));
LUT6 #(
.INIT(64'h444F444F444F4444))
\program_counter[8]_i_1
(.I0(\program_counter[15]_i_3_n_0 ),
.I1(\program_counter_reg[8]_i_2_n_4 ),
.I2(\program_counter[8]_i_3_n_0 ),
.I3(\program_counter[8]_i_4_n_0 ),
.I4(\read_input[31]_i_3_n_0 ),
.I5(\program_counter[8]_i_5_n_0 ),
.O(sel[8]));
LUT6 #(
.INIT(64'hAAA2AAAA8AA2AAAA))
\program_counter[8]_i_3
(.I0(\program_counter[15]_i_13_n_0 ),
.I1(opcode_2[3]),
.I2(opcode_2[2]),
.I3(opcode_2[4]),
.I4(data7[24]),
.I5(\program_counter[15]_i_8_n_0 ),
.O(\program_counter[8]_i_3_n_0 ));
LUT6 #(
.INIT(64'h0000FF1DFFFFFFFF))
\program_counter[8]_i_4
(.I0(register_a[8]),
.I1(operand_a1),
.I2(result[8]),
.I3(\program_counter[15]_i_14_n_0 ),
.I4(opcode_2[0]),
.I5(\program_counter[15]_i_15_n_0 ),
.O(\program_counter[8]_i_4_n_0 ));
LUT6 #(
.INIT(64'h000000000000BA8A))
\program_counter[8]_i_5
(.I0(data7[24]),
.I1(\program_counter[15]_i_8_n_0 ),
.I2(opcode_2[2]),
.I3(\program_counter_reg[8]_i_2_n_4 ),
.I4(opcode_2[4]),
.I5(opcode_2[3]),
.O(\program_counter[8]_i_5_n_0 ));
LUT6 #(
.INIT(64'h444F444F444F4444))
\program_counter[9]_i_1
(.I0(\program_counter[15]_i_3_n_0 ),
.I1(\program_counter_reg[12]_i_2_n_7 ),
.I2(\program_counter[9]_i_2_n_0 ),
.I3(\program_counter[9]_i_3_n_0 ),
.I4(\read_input[31]_i_3_n_0 ),
.I5(\program_counter[9]_i_4_n_0 ),
.O(sel[9]));
LUT6 #(
.INIT(64'hAAA2AAAA8AA2AAAA))
\program_counter[9]_i_2
(.I0(\program_counter[15]_i_13_n_0 ),
.I1(opcode_2[3]),
.I2(opcode_2[2]),
.I3(opcode_2[4]),
.I4(data7[25]),
.I5(\program_counter[15]_i_8_n_0 ),
.O(\program_counter[9]_i_2_n_0 ));
LUT6 #(
.INIT(64'h0000FF1DFFFFFFFF))
\program_counter[9]_i_3
(.I0(register_a[9]),
.I1(operand_a1),
.I2(result[9]),
.I3(\program_counter[15]_i_14_n_0 ),
.I4(opcode_2[0]),
.I5(\program_counter[15]_i_15_n_0 ),
.O(\program_counter[9]_i_3_n_0 ));
LUT6 #(
.INIT(64'h1010101011001010))
\program_counter[9]_i_4
(.I0(opcode_2[4]),
.I1(opcode_2[3]),
.I2(data7[25]),
.I3(\program_counter_reg[12]_i_2_n_7 ),
.I4(opcode_2[2]),
.I5(\program_counter[15]_i_8_n_0 ),
.O(\program_counter[9]_i_4_n_0 ));
FDRE \program_counter_1_reg[0]
(.C(ETH_CLK_OBUF),
.CE(instruction0),
.D(\program_counter_reg_n_0_[0] ),
.Q(program_counter_1[0]),
.R(1'b0));
FDRE \program_counter_1_reg[10]
(.C(ETH_CLK_OBUF),
.CE(instruction0),
.D(\program_counter_reg_n_0_[10] ),
.Q(program_counter_1[10]),
.R(1'b0));
FDRE \program_counter_1_reg[11]
(.C(ETH_CLK_OBUF),
.CE(instruction0),
.D(\program_counter_reg_n_0_[11] ),
.Q(program_counter_1[11]),
.R(1'b0));
FDRE \program_counter_1_reg[12]
(.C(ETH_CLK_OBUF),
.CE(instruction0),
.D(\program_counter_reg_n_0_[12] ),
.Q(program_counter_1[12]),
.R(1'b0));
FDRE \program_counter_1_reg[13]
(.C(ETH_CLK_OBUF),
.CE(instruction0),
.D(\program_counter_reg_n_0_[13] ),
.Q(program_counter_1[13]),
.R(1'b0));
FDRE \program_counter_1_reg[14]
(.C(ETH_CLK_OBUF),
.CE(instruction0),
.D(\program_counter_reg_n_0_[14] ),
.Q(program_counter_1[14]),
.R(1'b0));
FDRE \program_counter_1_reg[15]
(.C(ETH_CLK_OBUF),
.CE(instruction0),
.D(\program_counter_reg_n_0_[15] ),
.Q(program_counter_1[15]),
.R(1'b0));
FDRE \program_counter_1_reg[1]
(.C(ETH_CLK_OBUF),
.CE(instruction0),
.D(\program_counter_reg_n_0_[1] ),
.Q(program_counter_1[1]),
.R(1'b0));
FDRE \program_counter_1_reg[2]
(.C(ETH_CLK_OBUF),
.CE(instruction0),
.D(\program_counter_reg_n_0_[2] ),
.Q(program_counter_1[2]),
.R(1'b0));
FDRE \program_counter_1_reg[3]
(.C(ETH_CLK_OBUF),
.CE(instruction0),
.D(\program_counter_reg_n_0_[3] ),
.Q(program_counter_1[3]),
.R(1'b0));
FDRE \program_counter_1_reg[4]
(.C(ETH_CLK_OBUF),
.CE(instruction0),
.D(\program_counter_reg_n_0_[4] ),
.Q(program_counter_1[4]),
.R(1'b0));
FDRE \program_counter_1_reg[5]
(.C(ETH_CLK_OBUF),
.CE(instruction0),
.D(\program_counter_reg_n_0_[5] ),
.Q(program_counter_1[5]),
.R(1'b0));
FDRE \program_counter_1_reg[6]
(.C(ETH_CLK_OBUF),
.CE(instruction0),
.D(\program_counter_reg_n_0_[6] ),
.Q(program_counter_1[6]),
.R(1'b0));
FDRE \program_counter_1_reg[7]
(.C(ETH_CLK_OBUF),
.CE(instruction0),
.D(\program_counter_reg_n_0_[7] ),
.Q(program_counter_1[7]),
.R(1'b0));
FDRE \program_counter_1_reg[8]
(.C(ETH_CLK_OBUF),
.CE(instruction0),
.D(\program_counter_reg_n_0_[8] ),
.Q(program_counter_1[8]),
.R(1'b0));
FDRE \program_counter_1_reg[9]
(.C(ETH_CLK_OBUF),
.CE(instruction0),
.D(\program_counter_reg_n_0_[9] ),
.Q(program_counter_1[9]),
.R(1'b0));
FDRE \program_counter_2_reg[0]
(.C(ETH_CLK_OBUF),
.CE(opcode_20),
.D(program_counter_1[0]),
.Q(program_counter_2[0]),
.R(1'b0));
FDRE \program_counter_2_reg[10]
(.C(ETH_CLK_OBUF),
.CE(opcode_20),
.D(program_counter_1[10]),
.Q(program_counter_2[10]),
.R(1'b0));
FDRE \program_counter_2_reg[11]
(.C(ETH_CLK_OBUF),
.CE(opcode_20),
.D(program_counter_1[11]),
.Q(program_counter_2[11]),
.R(1'b0));
FDRE \program_counter_2_reg[12]
(.C(ETH_CLK_OBUF),
.CE(opcode_20),
.D(program_counter_1[12]),
.Q(program_counter_2[12]),
.R(1'b0));
FDRE \program_counter_2_reg[13]
(.C(ETH_CLK_OBUF),
.CE(opcode_20),
.D(program_counter_1[13]),
.Q(program_counter_2[13]),
.R(1'b0));
FDRE \program_counter_2_reg[14]
(.C(ETH_CLK_OBUF),
.CE(opcode_20),
.D(program_counter_1[14]),
.Q(program_counter_2[14]),
.R(1'b0));
FDRE \program_counter_2_reg[15]
(.C(ETH_CLK_OBUF),
.CE(opcode_20),
.D(program_counter_1[15]),
.Q(program_counter_2[15]),
.R(1'b0));
FDRE \program_counter_2_reg[1]
(.C(ETH_CLK_OBUF),
.CE(opcode_20),
.D(program_counter_1[1]),
.Q(program_counter_2[1]),
.R(1'b0));
FDRE \program_counter_2_reg[2]
(.C(ETH_CLK_OBUF),
.CE(opcode_20),
.D(program_counter_1[2]),
.Q(program_counter_2[2]),
.R(1'b0));
FDRE \program_counter_2_reg[3]
(.C(ETH_CLK_OBUF),
.CE(opcode_20),
.D(program_counter_1[3]),
.Q(program_counter_2[3]),
.R(1'b0));
FDRE \program_counter_2_reg[4]
(.C(ETH_CLK_OBUF),
.CE(opcode_20),
.D(program_counter_1[4]),
.Q(program_counter_2[4]),
.R(1'b0));
FDRE \program_counter_2_reg[5]
(.C(ETH_CLK_OBUF),
.CE(opcode_20),
.D(program_counter_1[5]),
.Q(program_counter_2[5]),
.R(1'b0));
FDRE \program_counter_2_reg[6]
(.C(ETH_CLK_OBUF),
.CE(opcode_20),
.D(program_counter_1[6]),
.Q(program_counter_2[6]),
.R(1'b0));
FDRE \program_counter_2_reg[7]
(.C(ETH_CLK_OBUF),
.CE(opcode_20),
.D(program_counter_1[7]),
.Q(program_counter_2[7]),
.R(1'b0));
FDRE \program_counter_2_reg[8]
(.C(ETH_CLK_OBUF),
.CE(opcode_20),
.D(program_counter_1[8]),
.Q(program_counter_2[8]),
.R(1'b0));
FDRE \program_counter_2_reg[9]
(.C(ETH_CLK_OBUF),
.CE(opcode_20),
.D(program_counter_1[9]),
.Q(program_counter_2[9]),
.R(1'b0));
FDRE \program_counter_reg[0]
(.C(ETH_CLK_OBUF),
.CE(instruction0),
.D(sel[0]),
.Q(\program_counter_reg_n_0_[0] ),
.R(INTERNAL_RST_reg));
FDRE \program_counter_reg[10]
(.C(ETH_CLK_OBUF),
.CE(instruction0),
.D(sel[10]),
.Q(\program_counter_reg_n_0_[10] ),
.R(INTERNAL_RST_reg));
FDRE \program_counter_reg[11]
(.C(ETH_CLK_OBUF),
.CE(instruction0),
.D(sel[11]),
.Q(\program_counter_reg_n_0_[11] ),
.R(INTERNAL_RST_reg));
FDRE \program_counter_reg[12]
(.C(ETH_CLK_OBUF),
.CE(instruction0),
.D(sel[12]),
.Q(\program_counter_reg_n_0_[12] ),
.R(INTERNAL_RST_reg));
CARRY4 \program_counter_reg[12]_i_2
(.CI(\program_counter_reg[8]_i_2_n_0 ),
.CO({\program_counter_reg[12]_i_2_n_0 ,\NLW_program_counter_reg[12]_i_2_CO_UNCONNECTED [2:0]}),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O({\program_counter_reg[12]_i_2_n_4 ,\program_counter_reg[12]_i_2_n_5 ,\program_counter_reg[12]_i_2_n_6 ,\program_counter_reg[12]_i_2_n_7 }),
.S({\program_counter_reg_n_0_[12] ,\program_counter_reg_n_0_[11] ,\program_counter_reg_n_0_[10] ,\program_counter_reg_n_0_[9] }));
FDRE \program_counter_reg[13]
(.C(ETH_CLK_OBUF),
.CE(instruction0),
.D(sel[13]),
.Q(\program_counter_reg_n_0_[13] ),
.R(INTERNAL_RST_reg));
FDRE \program_counter_reg[14]
(.C(ETH_CLK_OBUF),
.CE(instruction0),
.D(sel[14]),
.Q(\program_counter_reg_n_0_[14] ),
.R(INTERNAL_RST_reg));
FDRE \program_counter_reg[15]
(.C(ETH_CLK_OBUF),
.CE(instruction0),
.D(sel[15]),
.Q(\program_counter_reg_n_0_[15] ),
.R(INTERNAL_RST_reg));
CARRY4 \program_counter_reg[15]_i_4
(.CI(\program_counter_reg[12]_i_2_n_0 ),
.CO(\NLW_program_counter_reg[15]_i_4_CO_UNCONNECTED [3:0]),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O({\NLW_program_counter_reg[15]_i_4_O_UNCONNECTED [3],\program_counter_reg[15]_i_4_n_5 ,\program_counter_reg[15]_i_4_n_6 ,\program_counter_reg[15]_i_4_n_7 }),
.S({1'b0,\program_counter_reg_n_0_[15] ,\program_counter_reg_n_0_[14] ,\program_counter_reg_n_0_[13] }));
FDRE \program_counter_reg[1]
(.C(ETH_CLK_OBUF),
.CE(instruction0),
.D(sel[1]),
.Q(\program_counter_reg_n_0_[1] ),
.R(INTERNAL_RST_reg));
FDRE \program_counter_reg[2]
(.C(ETH_CLK_OBUF),
.CE(instruction0),
.D(sel[2]),
.Q(\program_counter_reg_n_0_[2] ),
.R(INTERNAL_RST_reg));
FDRE \program_counter_reg[3]
(.C(ETH_CLK_OBUF),
.CE(instruction0),
.D(sel[3]),
.Q(\program_counter_reg_n_0_[3] ),
.R(INTERNAL_RST_reg));
FDRE \program_counter_reg[4]
(.C(ETH_CLK_OBUF),
.CE(instruction0),
.D(sel[4]),
.Q(\program_counter_reg_n_0_[4] ),
.R(INTERNAL_RST_reg));
CARRY4 \program_counter_reg[4]_i_2
(.CI(1'b0),
.CO({\program_counter_reg[4]_i_2_n_0 ,\NLW_program_counter_reg[4]_i_2_CO_UNCONNECTED [2:0]}),
.CYINIT(\program_counter_reg_n_0_[0] ),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O({\program_counter_reg[4]_i_2_n_4 ,\program_counter_reg[4]_i_2_n_5 ,\program_counter_reg[4]_i_2_n_6 ,\program_counter_reg[4]_i_2_n_7 }),
.S({\program_counter_reg_n_0_[4] ,\program_counter_reg_n_0_[3] ,\program_counter_reg_n_0_[2] ,\program_counter_reg_n_0_[1] }));
FDRE \program_counter_reg[5]
(.C(ETH_CLK_OBUF),
.CE(instruction0),
.D(sel[5]),
.Q(\program_counter_reg_n_0_[5] ),
.R(INTERNAL_RST_reg));
FDRE \program_counter_reg[6]
(.C(ETH_CLK_OBUF),
.CE(instruction0),
.D(sel[6]),
.Q(\program_counter_reg_n_0_[6] ),
.R(INTERNAL_RST_reg));
FDRE \program_counter_reg[7]
(.C(ETH_CLK_OBUF),
.CE(instruction0),
.D(sel[7]),
.Q(\program_counter_reg_n_0_[7] ),
.R(INTERNAL_RST_reg));
FDRE \program_counter_reg[8]
(.C(ETH_CLK_OBUF),
.CE(instruction0),
.D(sel[8]),
.Q(\program_counter_reg_n_0_[8] ),
.R(INTERNAL_RST_reg));
CARRY4 \program_counter_reg[8]_i_2
(.CI(\program_counter_reg[4]_i_2_n_0 ),
.CO({\program_counter_reg[8]_i_2_n_0 ,\NLW_program_counter_reg[8]_i_2_CO_UNCONNECTED [2:0]}),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O({\program_counter_reg[8]_i_2_n_4 ,\program_counter_reg[8]_i_2_n_5 ,\program_counter_reg[8]_i_2_n_6 ,\program_counter_reg[8]_i_2_n_7 }),
.S({\program_counter_reg_n_0_[8] ,\program_counter_reg_n_0_[7] ,\program_counter_reg_n_0_[6] ,\program_counter_reg_n_0_[5] }));
FDRE \program_counter_reg[9]
(.C(ETH_CLK_OBUF),
.CE(instruction0),
.D(sel[9]),
.Q(\program_counter_reg_n_0_[9] ),
.R(INTERNAL_RST_reg));
(* IS_CLOCK_GATED *)
(* METHODOLOGY_DRC_VIOS = "" *)
(* POWER_OPTED_CE = "REGCEAREGCE=AUG" *)
(* RTL_RAM_BITS = "237568" *)
(* RTL_RAM_NAME = "program_counter" *)
(* bram_addr_begin = "0" *)
(* bram_addr_end = "8191" *)
(* bram_slice_begin = "0" *)
(* bram_slice_end = "3" *)
RAMB36E1 #(
.DOA_REG(1),
.DOB_REG(0),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h18408338258188088F98E78DF8C48BE8AA89688187486785C84683D82B815700),
.INIT_01(256'hDD8CD8BD8AD89D88D84083A82E81A8008FA8EE8DA8C08B18AA89388287286985),
.INIT_02(256'h85384583C8268158028F08EE8D289088087A86A85D84D83D82D81D80D8FD8ED8),
.INIT_03(256'h68C48B288087A86285084E83782E8158008F98E38DE8CD8B18A889088287F864),
.INIT_04(256'h2381580D8FB8E18D78C78B98A589988E87A86685884483282081380C8FA8E88D),
.INIT_05(256'h89788287686885984C83182A81D80A8F58D08CA8BE8AA89088A86085684F8318),
.INIT_06(256'h48FF8E28D08CE8B489088487786885B84983082381480E8FF8E58D18C28B38A6),
.INIT_07(256'h5C84083982A81E80D8F18E88D08C38BE8AF89988487986385F84083082281F80),
.INIT_08(256'h8AE89588087486885784983282081C8058FC8E48D48C98BD8A089C8848768658),
.INIT_09(256'h98348248158038F08E78DE8C98B28A089E88383082081A8018F18E18D08CE8B7),
.INIT_0A(256'h9188887086985784E83582C81C8058F48E38D78CE8B98A289888087386785E84),
.INIT_0B(256'h8E98D28C08BC8A589C88487486985D84083C8248168058FC8E08D98CA8BE8AD8),
.INIT_0C(256'hE8308298148018F58E28D18C08BA8A189188187086E85784E8358208148088F7),
.INIT_0D(256'h9088A87386E85F84983482981380F8F08E08D28CF8B48AF89288087A86E85E84),
.INIT_0E(256'h8018F58EB8D48C38B78A789888A87286485584983F82181980A8F08E68D68A08),
.INIT_0F(256'hC85884E8348238108058F98E48D98C78B28A289A88687086C85884D83E822813),
.INIT_10(256'hC58B28A989388B87486A85183082A81B8038F58E68DF8C18BA8AD89788187886),
.INIT_11(256'h8108008F58E58DF8C68B68A989088E87A86785184383D8248178088FC8E28D88),
.INIT_12(256'h387186885584283981080A8F58EE8D98C88B38A189D88087186D85784983E825),
.INIT_13(256'hD08C48B18AA89688787386A85684283582981D80B8FF8E78DE8C88B08A489C88),
.INIT_14(256'h84083382781E8098F48E48D58C38B08AC89588587886785084E8318008F08EA8),
.INIT_15(256'h589C88087986585E84D8318288108098F58E78D18CC8BE8A589A88C871867858),
.INIT_16(256'hF78EE8D58C08B48A889788987286085C84583C8248148098FD8E08DC8C48B68A),
.INIT_17(256'h84183982181A80A8F08E68DF8C38B58A089A88E87A86085A84383282181080E8),
.INIT_18(256'h8100DE0A0086085A84283782D8138048FB8E78D48C68BE8AC898888872869855),
.INIT_19(256'h017168C18018618718518618420F01838A20F018B8B20F01858520F018183009),
.INIT_1A(256'h018D171600F0FF900183171600F0FF900188171600F0FF900182171600F0F000),
.INIT_1B(256'h0171680000F0FF90018E171600F0FF90018B171600F0FF900188171600F0FF90),
.INIT_1C(256'hF0FF40018A0F11800BB17165A0F000180B020F0FFE00180011716810C0F0F040),
.INIT_1D(256'hFF90018E171600F0FF40018A0F11800DB171600F0FF40018A0F11800CB171600),
.INIT_1E(256'h00018600F0FF400180B0F0FEB00180A0F0FF50018001171618B17161716500F0),
.INIT_1F(256'h1C070F0FF000180011716C0F80A0F00018118000A00F0FF40018A17168008A0F),
.INIT_20(256'h90017168B020F0F0900171685020F0F0900171600F0FF90018A1716AA0F00118),
.INIT_21(256'h0F0F0E00171600F0FF90018D17165A0F001182B80000F0F000017168A020F0F0),
.INIT_22(256'h686040F0F0500171600F0FF90018117160A0F001183B80000F0F000017168409),
.INIT_23(256'h871716BA0F001184B80000F0F0000171687040F0F0500171685040F0F0500171),
.INIT_24(256'h0017168C040F0F0500171680040F0F0500171686040F0F0500171600F0FF9001),
.INIT_25(256'h18006180071800518006180041800A1800B1800518B17164000BCB80000F0F00),
.INIT_26(256'h0018000171600F0FF40018006171600F0FF900189171600F0F5C001800C18000),
.INIT_27(256'h80F0B00518A0F00D181500000F0FF900188171600F0FF4001800C171600F0FF4),
.INIT_28(256'h0F0900518A0F0020FA1800718180F0D00518A0F00F18180F0C00518A0F00E181),
.INIT_29(256'hF0700518A0F00B18180F0600518A0F00A18180F0A00518A0F0020FA180081818),
.INIT_2A(256'h41800718180A0F0020F00418006181CA0FA1800484080F0800518A0F00C18180),
.INIT_2B(256'h8A0051800083A0F0020F0041800918182A0F0020F0041800818181A0F0020F00),
.INIT_2C(256'h80F020F0E0F0FFF0018004171618E0051800180F020F0E0F0FFF001800417161),
.INIT_2D(256'h04171680F020F0041800051800380F020F0E0F0FFF0018004171618400518002),
.INIT_2E(256'h20F00118C005180E0F0FFF0018004171680F020F000188005180E0F0FFF00180),
.INIT_2F(256'h000080F84A0F0041811800480F020F002182005180E0F0FFF0018004171680F0),
.INIT_30(256'h0E800384A0F00F180083A0F00E180060008E010F0FE10018A18A0F00F18A1716),
.INIT_31(256'h058003850A0F0FE500180011800017168100FEA0F01800FB0048000EBA0F0180),
.INIT_32(256'h82081080030008A007090F0FE6001800F1800E171600008100585005BA0F0180),
.INIT_33(256'h218FC80A0F0001800F81A0F001181CA0F0001800F780A0F0001817A0F00E1800),
.INIT_34(256'h700008EA0F00E18180A0F00018181A0F0011810F82A0F002181180028C8A0F00),
.INIT_35(256'h1800E1800FF0020F0001800E800100000F0FE400180011800F17160000890018),
.INIT_36(256'h100008C00030000080F00F1800100008100F80A0F00018118000080F0020F000),
.INIT_37(256'h165A0F00C00E1800900E400082A0FA1800F6A0F00F1816A0FA1800F2A0F00F18),
.INIT_38(256'h0E1811716EA0F00D00E1800A00E580F0B00E180E0F0FFF0018A0F00B00E18117),
.INIT_39(256'hD00E180E0F0FFF0018A0F00D00E1811716E80F0C00E180E0F0FFF0018A0F00C0),
.INIT_3A(256'h0031800D00E1800800E171618400E1800D00E1800800E171683A0F00F18180F0),
.INIT_3B(256'hE1800C00E1800700E1716830E0F0FFF0018A0FA0F0020F0E0F0FFF0018A0FA0F),
.INIT_3C(256'hFFF0018A0FA0F0020F0E0F0FFF0018A0FA0F0031800C00E1800700E171618E00),
.INIT_3D(256'h18A0FA0F0031800B00E1800600E171618A00E1800B00E1800600E1716830E0F0),
.INIT_3E(256'hE1800600E1716830020F00318000E830E0F0FFF0018A0FA0F0020F0E0F0FFF00),
.INIT_3F(256'h0FA0F0020F0E0F0FFF0018A0FA0F0031800B00E1800600E171618800E1800B00),
.INIT_40(256'h0031800C00E1800700E171618C00E1800C00E1800700E1716830E0F0FFF0018A),
.INIT_41(256'hE1800D00E1800800E1716830E0F0FFF0018A0FA0F0020F0E0F0FFF0018A0FA0F),
.INIT_42(256'hFFF0018A0FA0F0020F0E0F0FFF0018A0FA0F0031800D00E1800800E171618200),
.INIT_43(256'hF70008AA0FA0F00F181181F0A0F0FF7001800F171600008BA0F003181830E0F0),
.INIT_44(256'h001716100087A0F91800F4A0F00F18000008AA0FA1800FBA0F00F18100008A00),
.INIT_45(256'h0F00018380008220F01858A0F00018210008220F01811A0F000181800C0F0F04),
.INIT_46(256'h61AD0008220F0188DA0F00018560008220F018B6A0F000184F0008220F018BFA),
.INIT_47(256'h000171618260008920F018F6A0F0A0F0FF500180001716181800C0F0F0400171),
.INIT_48(256'h8920F018D4A0F0A0F0FF500180001716183D0008920F0183DA0F0A0F0FF50018),
.INIT_49(256'h0840A0F0FF5001800017163020F0FFE00180001716800C0F0F040017161F4000),
.INIT_4A(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF6300),
.INIT_4B(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_4C(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_4D(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_4E(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_4F(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_50(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_51(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_52(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_53(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_54(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_55(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_56(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_57(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_58(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_59(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_5A(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_5B(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_5C(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_5D(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_5E(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_5F(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_60(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_61(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_62(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_63(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_64(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_65(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_66(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_67(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_68(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_69(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_6A(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_6B(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_6C(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_6D(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_6E(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_6F(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_70(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_71(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_72(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_73(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_74(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_75(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_76(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_77(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_78(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_79(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_7A(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_7B(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_7C(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_7D(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_7E(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_7F(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("PERFORMANCE"),
.READ_WIDTH_A(4),
.READ_WIDTH_B(0),
.RSTREG_PRIORITY_A("RSTREG"),
.RSTREG_PRIORITY_B("RSTREG"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("WRITE_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(4),
.WRITE_WIDTH_B(0))
program_counter_reg_rep_0
(.ADDRARDADDR({1'b1,program_counter_reg_rep_0_i_2_n_0,program_counter_reg_rep_0_i_3_n_0,program_counter_reg_rep_0_i_4_n_0,program_counter_reg_rep_0_i_5_n_0,program_counter_reg_rep_0_i_6_n_0,program_counter_reg_rep_0_i_7_n_0,program_counter_reg_rep_0_i_8_n_0,program_counter_reg_rep_0_i_9_n_0,program_counter_reg_rep_0_i_10_n_0,program_counter_reg_rep_0_i_11_n_0,program_counter_reg_rep_0_i_12_n_0,program_counter_reg_rep_0_i_13_n_0,program_counter_reg_rep_0_i_14_n_0,1'b0,1'b0}),
.ADDRBWRADDR({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
.CASCADEINA(1'b1),
.CASCADEINB(1'b0),
.CASCADEOUTA(NLW_program_counter_reg_rep_0_CASCADEOUTA_UNCONNECTED),
.CASCADEOUTB(NLW_program_counter_reg_rep_0_CASCADEOUTB_UNCONNECTED),
.CLKARDCLK(ETH_CLK_OBUF),
.CLKBWRCLK(1'b0),
.DBITERR(NLW_program_counter_reg_rep_0_DBITERR_UNCONNECTED),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b1,1'b1,1'b1,1'b1}),
.DIBDI({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
.DIPADIP({1'b0,1'b0,1'b0,1'b0}),
.DIPBDIP({1'b1,1'b1,1'b1,1'b1}),
.DOADO({NLW_program_counter_reg_rep_0_DOADO_UNCONNECTED[31:4],program_counter_reg_rep_0_n_32,program_counter_reg_rep_0_n_33,program_counter_reg_rep_0_n_34,program_counter_reg_rep_0_n_35}),
.DOBDO(NLW_program_counter_reg_rep_0_DOBDO_UNCONNECTED[31:0]),
.DOPADOP(NLW_program_counter_reg_rep_0_DOPADOP_UNCONNECTED[3:0]),
.DOPBDOP(NLW_program_counter_reg_rep_0_DOPBDOP_UNCONNECTED[3:0]),
.ECCPARITY(NLW_program_counter_reg_rep_0_ECCPARITY_UNCONNECTED[7:0]),
.ENARDEN(program_counter_reg_rep_0_i_1_n_0),
.ENBWREN(1'b0),
.INJECTDBITERR(NLW_program_counter_reg_rep_0_INJECTDBITERR_UNCONNECTED),
.INJECTSBITERR(NLW_program_counter_reg_rep_0_INJECTSBITERR_UNCONNECTED),
.RDADDRECC(NLW_program_counter_reg_rep_0_RDADDRECC_UNCONNECTED[8:0]),
.REGCEAREGCE(program_counter_reg_rep_0_REGCEAREGCE_cooolgate_en_sig_11),
.REGCEB(NLW_program_counter_reg_rep_0_REGCEB_UNCONNECTED),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(NLW_program_counter_reg_rep_0_SBITERR_UNCONNECTED),
.WEA({1'b0,1'b0,1'b0,1'b0}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
LUT3 #(
.INIT(8'h20))
program_counter_reg_rep_0_REGCEAREGCE_cooolgate_en_gate_21
(.I0(instruction0),
.I1(INTERNAL_RST_reg),
.I2(instruction0),
.O(program_counter_reg_rep_0_REGCEAREGCE_cooolgate_en_sig_11));
LUT4 #(
.INIT(16'hAFAE))
program_counter_reg_rep_0_i_1
(.I0(INTERNAL_RST_reg),
.I1(\state_reg_n_0_[0] ),
.I2(\state_reg_n_0_[2] ),
.I3(\state_reg_n_0_[1] ),
.O(program_counter_reg_rep_0_i_1_n_0));
LUT6 #(
.INIT(64'h000000000202FF02))
program_counter_reg_rep_0_i_10
(.I0(program_counter_reg_rep_0_i_23_n_0),
.I1(\program_counter[4]_i_4_n_0 ),
.I2(\program_counter[4]_i_3_n_0 ),
.I3(\program_counter_reg[4]_i_2_n_4 ),
.I4(\program_counter[15]_i_3_n_0 ),
.I5(INTERNAL_RST_reg),
.O(program_counter_reg_rep_0_i_10_n_0));
LUT6 #(
.INIT(64'h00000000222222F2))
program_counter_reg_rep_0_i_11
(.I0(\program_counter_reg[4]_i_2_n_5 ),
.I1(\program_counter[15]_i_3_n_0 ),
.I2(program_counter_reg_rep_0_i_24_n_0),
.I3(\program_counter[3]_i_3_n_0 ),
.I4(\program_counter[3]_i_2_n_0 ),
.I5(INTERNAL_RST_reg),
.O(program_counter_reg_rep_0_i_11_n_0));
LUT6 #(
.INIT(64'h000000000202FF02))
program_counter_reg_rep_0_i_12
(.I0(program_counter_reg_rep_0_i_25_n_0),
.I1(\program_counter[2]_i_3_n_0 ),
.I2(\program_counter[2]_i_2_n_0 ),
.I3(\program_counter_reg[4]_i_2_n_6 ),
.I4(\program_counter[15]_i_3_n_0 ),
.I5(INTERNAL_RST_reg),
.O(program_counter_reg_rep_0_i_12_n_0));
LUT6 #(
.INIT(64'h000000000202FF02))
program_counter_reg_rep_0_i_13
(.I0(program_counter_reg_rep_0_i_26_n_0),
.I1(\program_counter[1]_i_3_n_0 ),
.I2(\program_counter[1]_i_2_n_0 ),
.I3(\program_counter_reg[4]_i_2_n_7 ),
.I4(\program_counter[15]_i_3_n_0 ),
.I5(INTERNAL_RST_reg),
.O(program_counter_reg_rep_0_i_13_n_0));
LUT6 #(
.INIT(64'h00000000101010FF))
program_counter_reg_rep_0_i_14
(.I0(\program_counter[0]_i_4_n_0 ),
.I1(\program_counter[0]_i_3_n_0 ),
.I2(program_counter_reg_rep_0_i_27_n_0),
.I3(\program_counter_reg_n_0_[0] ),
.I4(\program_counter[15]_i_3_n_0 ),
.I5(INTERNAL_RST_reg),
.O(program_counter_reg_rep_0_i_14_n_0));
LUT6 #(
.INIT(64'hAAAAAAAAFFEFBAAA))
program_counter_reg_rep_0_i_15
(.I0(\read_input[31]_i_3_n_0 ),
.I1(\program_counter[15]_i_8_n_0 ),
.I2(opcode_2[2]),
.I3(\program_counter_reg[12]_i_2_n_4 ),
.I4(data7[28]),
.I5(memory_reg_0_i_2_n_0),
.O(program_counter_reg_rep_0_i_15_n_0));
LUT6 #(
.INIT(64'hAAAAAAAAFFEFBAAA))
program_counter_reg_rep_0_i_16
(.I0(\read_input[31]_i_3_n_0 ),
.I1(\program_counter[15]_i_8_n_0 ),
.I2(opcode_2[2]),
.I3(\program_counter_reg[12]_i_2_n_5 ),
.I4(data7[27]),
.I5(memory_reg_0_i_2_n_0),
.O(program_counter_reg_rep_0_i_16_n_0));
LUT6 #(
.INIT(64'hAAAAAAAAFFEFBAAA))
program_counter_reg_rep_0_i_17
(.I0(\read_input[31]_i_3_n_0 ),
.I1(\program_counter[15]_i_8_n_0 ),
.I2(opcode_2[2]),
.I3(\program_counter_reg[12]_i_2_n_6 ),
.I4(data7[26]),
.I5(memory_reg_0_i_2_n_0),
.O(program_counter_reg_rep_0_i_17_n_0));
LUT6 #(
.INIT(64'hAAAAAAAAFFEFBAAA))
program_counter_reg_rep_0_i_18
(.I0(\read_input[31]_i_3_n_0 ),
.I1(\program_counter[15]_i_8_n_0 ),
.I2(opcode_2[2]),
.I3(\program_counter_reg[12]_i_2_n_7 ),
.I4(data7[25]),
.I5(memory_reg_0_i_2_n_0),
.O(program_counter_reg_rep_0_i_18_n_0));
LUT6 #(
.INIT(64'hBBBBBABBAAAABAAA))
program_counter_reg_rep_0_i_19
(.I0(\read_input[31]_i_3_n_0 ),
.I1(memory_reg_0_i_2_n_0),
.I2(\program_counter_reg[8]_i_2_n_4 ),
.I3(opcode_2[2]),
.I4(\program_counter[15]_i_8_n_0 ),
.I5(data7[24]),
.O(program_counter_reg_rep_0_i_19_n_0));
LUT6 #(
.INIT(64'h000000000202FF02))
program_counter_reg_rep_0_i_2
(.I0(program_counter_reg_rep_0_i_15_n_0),
.I1(\program_counter[12]_i_4_n_0 ),
.I2(\program_counter[12]_i_3_n_0 ),
.I3(\program_counter_reg[12]_i_2_n_4 ),
.I4(\program_counter[15]_i_3_n_0 ),
.I5(INTERNAL_RST_reg),
.O(program_counter_reg_rep_0_i_2_n_0));
LUT6 #(
.INIT(64'hBBBBBABBAAAABAAA))
program_counter_reg_rep_0_i_20
(.I0(\read_input[31]_i_3_n_0 ),
.I1(memory_reg_0_i_2_n_0),
.I2(\program_counter_reg[8]_i_2_n_5 ),
.I3(opcode_2[2]),
.I4(\program_counter[15]_i_8_n_0 ),
.I5(data7[23]),
.O(program_counter_reg_rep_0_i_20_n_0));
LUT6 #(
.INIT(64'hBBBBBABBAAAABAAA))
program_counter_reg_rep_0_i_21
(.I0(\read_input[31]_i_3_n_0 ),
.I1(memory_reg_0_i_2_n_0),
.I2(\program_counter_reg[8]_i_2_n_6 ),
.I3(opcode_2[2]),
.I4(\program_counter[15]_i_8_n_0 ),
.I5(data7[22]),
.O(program_counter_reg_rep_0_i_21_n_0));
LUT6 #(
.INIT(64'hBBBBBABBAAAABAAA))
program_counter_reg_rep_0_i_22
(.I0(\read_input[31]_i_3_n_0 ),
.I1(memory_reg_0_i_2_n_0),
.I2(\program_counter_reg[8]_i_2_n_7 ),
.I3(opcode_2[2]),
.I4(\program_counter[15]_i_8_n_0 ),
.I5(data7[21]),
.O(program_counter_reg_rep_0_i_22_n_0));
LUT6 #(
.INIT(64'hBBBBAABABBABAAAA))
program_counter_reg_rep_0_i_23
(.I0(\read_input[31]_i_3_n_0 ),
.I1(memory_reg_0_i_2_n_0),
.I2(opcode_2[2]),
.I3(\program_counter[15]_i_8_n_0 ),
.I4(data7[20]),
.I5(\program_counter_reg[4]_i_2_n_4 ),
.O(program_counter_reg_rep_0_i_23_n_0));
LUT6 #(
.INIT(64'hBBBBAABABBABAAAA))
program_counter_reg_rep_0_i_24
(.I0(\read_input[31]_i_3_n_0 ),
.I1(memory_reg_0_i_2_n_0),
.I2(opcode_2[2]),
.I3(\program_counter[15]_i_8_n_0 ),
.I4(address_b_2[3]),
.I5(\program_counter_reg[4]_i_2_n_5 ),
.O(program_counter_reg_rep_0_i_24_n_0));
LUT6 #(
.INIT(64'hBBBBBABBAAAABAAA))
program_counter_reg_rep_0_i_25
(.I0(\read_input[31]_i_3_n_0 ),
.I1(memory_reg_0_i_2_n_0),
.I2(\program_counter_reg[4]_i_2_n_6 ),
.I3(opcode_2[2]),
.I4(\program_counter[15]_i_8_n_0 ),
.I5(address_b_2[2]),
.O(program_counter_reg_rep_0_i_25_n_0));
LUT6 #(
.INIT(64'hBBBBBABBAAAABAAA))
program_counter_reg_rep_0_i_26
(.I0(\read_input[31]_i_3_n_0 ),
.I1(memory_reg_0_i_2_n_0),
.I2(\program_counter_reg[4]_i_2_n_7 ),
.I3(opcode_2[2]),
.I4(\program_counter[15]_i_8_n_0 ),
.I5(address_b_2[1]),
.O(program_counter_reg_rep_0_i_26_n_0));
LUT6 #(
.INIT(64'hBBABAAAABBBBAABA))
program_counter_reg_rep_0_i_27
(.I0(\read_input[31]_i_3_n_0 ),
.I1(memory_reg_0_i_2_n_0),
.I2(opcode_2[2]),
.I3(\program_counter[15]_i_8_n_0 ),
.I4(address_b_2[0]),
.I5(\program_counter_reg_n_0_[0] ),
.O(program_counter_reg_rep_0_i_27_n_0));
LUT6 #(
.INIT(64'h000000000202FF02))
program_counter_reg_rep_0_i_3
(.I0(program_counter_reg_rep_0_i_16_n_0),
.I1(\program_counter[11]_i_3_n_0 ),
.I2(\program_counter[11]_i_2_n_0 ),
.I3(\program_counter_reg[12]_i_2_n_5 ),
.I4(\program_counter[15]_i_3_n_0 ),
.I5(INTERNAL_RST_reg),
.O(program_counter_reg_rep_0_i_3_n_0));
LUT6 #(
.INIT(64'h000000000202FF02))
program_counter_reg_rep_0_i_4
(.I0(program_counter_reg_rep_0_i_17_n_0),
.I1(\program_counter[10]_i_3_n_0 ),
.I2(\program_counter[10]_i_2_n_0 ),
.I3(\program_counter_reg[12]_i_2_n_6 ),
.I4(\program_counter[15]_i_3_n_0 ),
.I5(INTERNAL_RST_reg),
.O(program_counter_reg_rep_0_i_4_n_0));
LUT6 #(
.INIT(64'h000000000202FF02))
program_counter_reg_rep_0_i_5
(.I0(program_counter_reg_rep_0_i_18_n_0),
.I1(\program_counter[9]_i_3_n_0 ),
.I2(\program_counter[9]_i_2_n_0 ),
.I3(\program_counter_reg[12]_i_2_n_7 ),
.I4(\program_counter[15]_i_3_n_0 ),
.I5(INTERNAL_RST_reg),
.O(program_counter_reg_rep_0_i_5_n_0));
LUT6 #(
.INIT(64'h000000000202FF02))
program_counter_reg_rep_0_i_6
(.I0(program_counter_reg_rep_0_i_19_n_0),
.I1(\program_counter[8]_i_4_n_0 ),
.I2(\program_counter[8]_i_3_n_0 ),
.I3(\program_counter_reg[8]_i_2_n_4 ),
.I4(\program_counter[15]_i_3_n_0 ),
.I5(INTERNAL_RST_reg),
.O(program_counter_reg_rep_0_i_6_n_0));
LUT6 #(
.INIT(64'h000000000202FF02))
program_counter_reg_rep_0_i_7
(.I0(program_counter_reg_rep_0_i_20_n_0),
.I1(\program_counter[7]_i_3_n_0 ),
.I2(\program_counter[7]_i_2_n_0 ),
.I3(\program_counter_reg[8]_i_2_n_5 ),
.I4(\program_counter[15]_i_3_n_0 ),
.I5(INTERNAL_RST_reg),
.O(program_counter_reg_rep_0_i_7_n_0));
LUT6 #(
.INIT(64'h000000000202FF02))
program_counter_reg_rep_0_i_8
(.I0(program_counter_reg_rep_0_i_21_n_0),
.I1(\program_counter[6]_i_3_n_0 ),
.I2(\program_counter[6]_i_2_n_0 ),
.I3(\program_counter_reg[8]_i_2_n_6 ),
.I4(\program_counter[15]_i_3_n_0 ),
.I5(INTERNAL_RST_reg),
.O(program_counter_reg_rep_0_i_8_n_0));
LUT6 #(
.INIT(64'h000000000202FF02))
program_counter_reg_rep_0_i_9
(.I0(program_counter_reg_rep_0_i_22_n_0),
.I1(\program_counter[5]_i_3_n_0 ),
.I2(\program_counter[5]_i_2_n_0 ),
.I3(\program_counter_reg[8]_i_2_n_7 ),
.I4(\program_counter[15]_i_3_n_0 ),
.I5(INTERNAL_RST_reg),
.O(program_counter_reg_rep_0_i_9_n_0));
(* METHODOLOGY_DRC_VIOS = "" *)
(* RTL_RAM_BITS = "237568" *)
(* RTL_RAM_NAME = "program_counter" *)
(* bram_addr_begin = "0" *)
(* bram_addr_end = "8191" *)
(* bram_slice_begin = "4" *)
(* bram_slice_end = "7" *)
RAMB36E1 #(
.DOA_REG(1),
.DOB_REG(0),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h4015015015015014005005004005004005005005004004004004004004004E00),
.INIT_01(256'h2302302302302302302002002302002001001301001001501401401501401401),
.INIT_02(256'h0460460460460460450320320330300300300300330330330330330330230230),
.INIT_03(256'h4054054050050056052052056052056052042046043042046042042047046047),
.INIT_04(256'h7507507406406406406506406406506406506506506506506506406405405405),
.INIT_05(256'h0850840850850850840840850840840740700700730700700700700750740750),
.INIT_06(256'h7096095092092093090094094094094094095095095094084085085085084084),
.INIT_07(256'hB60B20B20B70B30B20A60A20A20A70A60A60A60A70A60A70A60A70A20A70A60A),
.INIT_08(256'h0C20C60C20C70C60C60C60C70C20C20C60B60B60B60B60B60B20B20B70B60B60),
.INIT_09(256'h60E70E70E60E70D20D60D60D60D50D20D20D30D00D00D00D60C60C60C20C20C6),
.INIT_0A(256'hF60F20F20F20F60F60F70F60F60F60E70E70E60E60E60E50E20E20E70E60E60E),
.INIT_0B(256'h0060070020020060060060060060060020020070060060F60F20F20F70F30F20),
.INIT_0C(256'h2022027026026016017010010010016016016012012016012016012017016006),
.INIT_0D(256'hF20F30F70F60F60F60F70F60F70F60E70E20E70E60E70E60E502002002202202),
.INIT_0E(256'h0150050040050040040050050050050040040050040040040040F50F50F40F00),
.INIT_0F(256'h4024024024025025025015015014014015014015015010014014014014014015),
.INIT_10(256'h3503503403503403403403403003503403402402402402502402402502402502),
.INIT_11(256'h0500500440440440450440450450440450440450440440450450440340340350),
.INIT_12(256'h5065064065065065060060056056056056056056054052056056056056056054),
.INIT_13(256'h7007507407407507507407507407407407407407406406406406506506406406),
.INIT_14(256'h0920970960960960870870860870820860860860860850820820830800720730),
.INIT_15(256'h60A60A20A20A30A30A20A30A20A20A2096096096096096096097096096095092),
.INIT_16(256'hB60B20B60B20B70B60B60B60B70B20B20B60B60B60B60B60A60A20A20A70A60A),
.INIT_17(256'h0D50D50D40D40D50C50C50C40C50C40C00C00C30C00C00C00C30C30C30C20C20),
.INIT_18(256'h05001103000E00E40E40E50E40E40E40D40D40D50D40D40D40D50D40D50D40D5),
.INIT_19(256'h000000F40040240740240D40D00F00060200F00050300F00030D00F00000D003),
.INIT_1A(256'h0003000000F0FF400008000000F0FF400002000000F0FF400005000000F0F050),
.INIT_1B(256'h0000000000F0FF400001000000F0FF400009000000F0FF40000D000000F0FF40),
.INIT_1C(256'hF0FFA000000F40000B20000800F000000E080F0FFB0000000000000030F0F0B0),
.INIT_1D(256'hFF400007000000F0FFA000000F40000B2000000F0FFA000000F40000B2000000),
.INIT_1E(256'h00000400F0FFA00000F0F0FFE0000090F0FFD0000000000000200000000800F0),
.INIT_1F(256'h34020F0FF20000000000040F0000F00000000000E00F0FFA000000000000D00F),
.INIT_20(256'h300000003060F0F030000000D060F0F0300000000F0FF4000070000500F00000),
.INIT_21(256'h0F0F0B00000000F0FF4000010000900F000003400000F0F0500000002060F0F0),
.INIT_22(256'h00D030F0F0400000000F0FF4000020000F00F000003400000F0F050000000D05),
.INIT_23(256'h0C0000400F000003400000F0F0500000007030F0F0400000002030F0F0400000),
.INIT_24(256'h0000000F030F0F0400000000030F0F0400000002030F0F0400000000F0FF4000),
.INIT_25(256'h0000200007000020000D0000D00002000030000D00200001000F4400000F0F05),
.INIT_26(256'h0000000000000F0FFA0000002000000F0FF40000E000000F0FFE000000F00000),
.INIT_27(256'h00F0B00F0000F00F004000000F0FF400007000000F0FFA000000F000000F0FFA),
.INIT_28(256'h0F0B00F0000F0000F10000F00400F0B00F0000F00F00400F0B00F0000F00F004),
.INIT_29(256'hF0B00F0000F00F00400F0B00F0000F00F00400F0B00F0000F0000F10000F0040),
.INIT_2A(256'h00000F0040000F0000F0000000F004F00F10000000000F0B00F0000F00F00400),
.INIT_2B(256'h0100F000000000F0000F0000000F0040000F0000F0000000F0040000F0000F00),
.INIT_2C(256'h00F000F070F0FFF0000000000000400F0000000F000F070F0FFF000000000000),
.INIT_2D(256'h00000000F000F00000000F0000000F000F070F0FFF0000000000000300F00000),
.INIT_2E(256'h00F00000900F00070F0FFF0000000000000F000F00000600F00070F0FFF00000),
.INIT_2F(256'h000090F0000F0000000000000F000F00000800F00070F0FFF0000000000000F0),
.INIT_30(256'h0F40000000F00F00000000F00F0000000007080F0FF2000010000F00F0010000),
.INIT_31(256'h00800000030F0FF900000000000000000000F500F00000F50000000F400F0000),
.INIT_32(256'h00000000000000300D020F0FFB000000F0000F000000000800000000800F0000),
.INIT_33(256'h0001F0000F0000000F0000F000000F00F0000000FD0000F000000D00F00F0000),
.INIT_34(256'hD000C0F00F00F0000000F0000000000F0000000F0000F0000000000003000F00),
.INIT_35(256'h0000F0000F90000F0000000F000000000F0FF600000050000F00000000020000),
.INIT_36(256'h4000003000D0000000F00F0000500006AA0F0000F00000000000000F0000F000),
.INIT_37(256'h00200F00B00F0000B00F00000800F70000FE00F00F006E00F50000FD00F00F00),
.INIT_38(256'h0F0000000500F00B00F0000B00F200F0B00F00070F0FFF000000F00B00F00000),
.INIT_39(256'hB00F00070F0FFF000000F00B00F0000000500F0B00F00070F0FFF000000F00B0),
.INIT_3A(256'h0000000B00F0000B00F000000300F0000B00F0000B00F00000000F00F00400F0),
.INIT_3B(256'hF0000B00F0000B00F000000070F0FFF000000F00F0000F070F0FFF000000F00F),
.INIT_3C(256'hFFF000000F00F0000F070F0FFF000000F00F0000000B00F0000B00F000000400),
.INIT_3D(256'h0000F00F0000000B00F0000B00F000000100F0000B00F0000B00F000000070F0),
.INIT_3E(256'hF0000B00F0000000000F00000000F00070F0FFF000000F00F0000F070F0FFF00),
.INIT_3F(256'h0F00F0000F070F0FFF000000F00F0000000B00F0000B00F000000600F0000B00),
.INIT_40(256'h0000000B00F0000B00F000000900F0000B00F0000B00F000000070F0FFF00000),
.INIT_41(256'hF0000B00F0000B00F000000070F0FFF000000F00F0000F070F0FFF000000F00F),
.INIT_42(256'hFFF000000F00F0000F070F0FFF000000F00F0000000B00F0000B00F000000800),
.INIT_43(256'hF00000900F00F00F006004F050F0FF0000000F000000000F00F00000400070F0),
.INIT_44(256'h00000000000200F30000F300F00F00300000500F70000F100F00F00600000900),
.INIT_45(256'h0F00000370000600F0003700F00000360000600F0000600F00000300030F0F0B),
.INIT_46(256'h003B0000600F0001B00F000003A0000600F000CA00F00000380000600F000580),
.INIT_47(256'h0000000004F0000500F0007F00F090F0FFD0000000000000400030F0F0B00000),
.INIT_48(256'h0500F000F400F090F0FFD0000000000000410000500F0006100F090F0FFD0000),
.INIT_49(256'h003090F0FFD000000000008080F0FFB0000000000000030F0F0B0000000B4000),
.INIT_4A(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF4800),
.INIT_4B(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_4C(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_4D(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_4E(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_4F(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_50(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_51(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_52(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_53(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_54(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_55(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_56(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_57(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_58(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_59(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_5A(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_5B(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_5C(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_5D(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_5E(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_5F(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_60(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_61(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_62(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_63(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_64(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_65(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_66(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_67(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_68(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_69(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_6A(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_6B(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_6C(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_6D(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_6E(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_6F(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_70(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_71(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_72(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_73(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_74(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_75(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_76(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_77(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_78(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_79(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_7A(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_7B(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_7C(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_7D(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_7E(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_7F(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("PERFORMANCE"),
.READ_WIDTH_A(4),
.READ_WIDTH_B(0),
.RSTREG_PRIORITY_A("RSTREG"),
.RSTREG_PRIORITY_B("RSTREG"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("WRITE_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(4),
.WRITE_WIDTH_B(0))
program_counter_reg_rep_1
(.ADDRARDADDR({1'b1,program_counter_reg_rep_0_i_2_n_0,program_counter_reg_rep_0_i_3_n_0,program_counter_reg_rep_0_i_4_n_0,program_counter_reg_rep_0_i_5_n_0,program_counter_reg_rep_0_i_6_n_0,program_counter_reg_rep_0_i_7_n_0,program_counter_reg_rep_0_i_8_n_0,program_counter_reg_rep_0_i_9_n_0,program_counter_reg_rep_0_i_10_n_0,program_counter_reg_rep_0_i_11_n_0,program_counter_reg_rep_0_i_12_n_0,program_counter_reg_rep_0_i_13_n_0,program_counter_reg_rep_0_i_14_n_0,1'b0,1'b0}),
.ADDRBWRADDR({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
.CASCADEINA(1'b1),
.CASCADEINB(1'b0),
.CASCADEOUTA(NLW_program_counter_reg_rep_1_CASCADEOUTA_UNCONNECTED),
.CASCADEOUTB(NLW_program_counter_reg_rep_1_CASCADEOUTB_UNCONNECTED),
.CLKARDCLK(ETH_CLK_OBUF),
.CLKBWRCLK(1'b0),
.DBITERR(NLW_program_counter_reg_rep_1_DBITERR_UNCONNECTED),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b1,1'b1,1'b1,1'b1}),
.DIBDI({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
.DIPADIP({1'b0,1'b0,1'b0,1'b0}),
.DIPBDIP({1'b1,1'b1,1'b1,1'b1}),
.DOADO({NLW_program_counter_reg_rep_1_DOADO_UNCONNECTED[31:4],program_counter_reg_rep_1_n_32,program_counter_reg_rep_1_n_33,program_counter_reg_rep_1_n_34,program_counter_reg_rep_1_n_35}),
.DOBDO(NLW_program_counter_reg_rep_1_DOBDO_UNCONNECTED[31:0]),
.DOPADOP(NLW_program_counter_reg_rep_1_DOPADOP_UNCONNECTED[3:0]),
.DOPBDOP(NLW_program_counter_reg_rep_1_DOPBDOP_UNCONNECTED[3:0]),
.ECCPARITY(NLW_program_counter_reg_rep_1_ECCPARITY_UNCONNECTED[7:0]),
.ENARDEN(program_counter_reg_rep_0_i_1_n_0),
.ENBWREN(1'b0),
.INJECTDBITERR(NLW_program_counter_reg_rep_1_INJECTDBITERR_UNCONNECTED),
.INJECTSBITERR(NLW_program_counter_reg_rep_1_INJECTSBITERR_UNCONNECTED),
.RDADDRECC(NLW_program_counter_reg_rep_1_RDADDRECC_UNCONNECTED[8:0]),
.REGCEAREGCE(instruction0),
.REGCEB(NLW_program_counter_reg_rep_1_REGCEB_UNCONNECTED),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(NLW_program_counter_reg_rep_1_SBITERR_UNCONNECTED),
.WEA({1'b0,1'b0,1'b0,1'b0}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
(* IS_CLOCK_GATED *)
(* METHODOLOGY_DRC_VIOS = "" *)
(* POWER_OPTED_CE = "REGCEAREGCE=AUG" *)
(* RTL_RAM_BITS = "237568" *)
(* RTL_RAM_NAME = "program_counter" *)
(* bram_addr_begin = "0" *)
(* bram_addr_end = "8191" *)
(* bram_slice_begin = "8" *)
(* bram_slice_end = "11" *)
RAMB36E1 #(
.DOA_REG(1),
.DOB_REG(0),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000200),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0100100100100100100100100100100100100100100100000000000000000000),
.INIT_0C(256'h0010010010010010010010010010010010010010010010010010010010010010),
.INIT_0D(256'h1001001001001001001001001001001001001001001001001001001001001001),
.INIT_0E(256'h0200200200200200200200200200200200200200200200200200100100100100),
.INIT_0F(256'h0020020020020020020020020020020020020020020020020020020020020020),
.INIT_10(256'h2002002002002002002002002002002002002002002002002002002002002002),
.INIT_11(256'h0200200200200200200200200200200200200200200200200200200200200200),
.INIT_12(256'h0020020020020020020020020020020020020020020020020020020020020020),
.INIT_13(256'h2002002002002002002002002002002002002002002002002002002002002002),
.INIT_14(256'h0200200200200200200200200200200200200200200200200200200200200200),
.INIT_15(256'h0020020020020020020020020020020020020020020020020020020020020020),
.INIT_16(256'h2002002002002002002002002002002002002002002002002002002002002002),
.INIT_17(256'h0200200200200200200200200200200200200200200200200200200200200200),
.INIT_18(256'h0200110600020020020020020020020020020020020020020020020020020020),
.INIT_19(256'h000000100000000000000000000F00020100F00000000F00020000F000000000),
.INIT_1A(256'h0000000000F0FFD00002000000F0FFD00000000000F0FFD00002000000F0F090),
.INIT_1B(256'h0000000000F0FFD00001000000F0FFD00000000000F0FFD00000000000F0FFD0),
.INIT_1C(256'hF0FFD000000F00000010000700F0000007020F0FFD0000000000000000F0F0D0),
.INIT_1D(256'hFFD00002000000F0FFD000000F0000001000000F0FFD000000F0000001000000),
.INIT_1E(256'h00000000F0FFD0000010F0FFD0000000F0FF00000000000000100000000700F0),
.INIT_1F(256'h09000F0FF10000000000090F0000F00000000000700F0FFD000000000000700F),
.INIT_20(256'h100000000020F0F0100000000020F0F0100000000F0FFD000000000800F00000),
.INIT_21(256'h0F0F0100000000F0FFD000000000800F000000900000F0F0900000001020F0F0),
.INIT_22(256'h000020F0F0200000000F0FFD000000000800F000000900000F0F090000000000),
.INIT_23(256'h020000900F000000900000F0F0900000000020F0F0200000000020F0F0200000),
.INIT_24(256'h00000001020F0F0200000000020F0F0200000000020F0F0200000000F0FFD000),
.INIT_25(256'h00000000000000000000000000000100000000000010000000069900000F0F09),
.INIT_26(256'h0000000000000F0FFD0000000000000F0FFD00001000000F0FF9000000100000),
.INIT_27(256'h00F0000F0000F00F000000000F0FFD00000000000F0FFD0000001000000F0FFD),
.INIT_28(256'h0F0000F0000F0000F00000F00000F0000F0000F00F00000F0000F0000F00F000),
.INIT_29(256'hF0000F0000F00F00000F0000F0000F00F00000F0000F0000F0000F00000F0000),
.INIT_2A(256'h00000F0000000F0000F0000000F000B00F00000000000F0000F0000F00F00000),
.INIT_2B(256'h0000F000000000F0000F0000000F0000000F0000F0000000F0000000F0000F00),
.INIT_2C(256'h00F000F000F0FFB0000000000000000F0000000F000F000F0FFB000000000000),
.INIT_2D(256'h00000000F000F00000000F0000000F000F000F0FFB0000000000000000F00000),
.INIT_2E(256'h00F00000000F00000F0FFB0000000000000F000F00000000F00000F0FFB00000),
.INIT_2F(256'h0000A0F0000F0000000000000F000F00000000F00000F0FFB0000000000000F0),
.INIT_30(256'h0FC0000000F00F00000000F00F0000000000020F0FFC000000000F00F0000000),
.INIT_31(256'h00C00000000F0FFC00000000000000000000FC00F00000FC0000000FC00F0000),
.INIT_32(256'h000000000000000000010F0FFC000000F0000F000000000200000000C00F0000),
.INIT_33(256'h0000C0000F0000000F0000F000000C00F0000000FC0000F000000C00F00F0000),
.INIT_34(256'h0000C0F00F00F0000000F0000000000F0000000F0000F00000000000DDD00F00),
.INIT_35(256'h0000F0000FD0000F0000000F000000000F0FFD00000020000F00000000010000),
.INIT_36(256'h000000000000000000F00F000020000DDD0F0000F00000000000000F0000F000),
.INIT_37(256'h00E00F00000F0000000F00000200F00000FD00F00F000D00F00000FD00F00F00),
.INIT_38(256'h0F0000000E00F00000F0000000FE00F0000F00000F0FFB000000F00000F00000),
.INIT_39(256'h000F00000F0FFB000000F00000F0000000E00F0000F00000F0FFB000000F0000),
.INIT_3A(256'h0000000000F0000000F000000000F0000000F0000000F00000000F00F00000F0),
.INIT_3B(256'hF0000000F0000000F000000000F0FFB000000F00F0000F000F0FFB000000F00F),
.INIT_3C(256'hFFB000000F00F0000F000F0FFB000000F00F0000000000F0000000F000000000),
.INIT_3D(256'h0000F00F0000000000F0000000F000000000F0000000F0000000F000000000F0),
.INIT_3E(256'hF0000000F0000000000F00000000F00000F0FFB000000F00F0000F000F0FFB00),
.INIT_3F(256'h0F00F0000F000F0FFB000000F00F0000000000F0000000F000000000F0000000),
.INIT_40(256'h0000000000F0000000F000000000F0000000F0000000F000000000F0FFB00000),
.INIT_41(256'hF0000000F0000000F000000000F0FFB000000F00F0000F000F0FFB000000F00F),
.INIT_42(256'hFFB000000F00F0000F000F0FFB000000F00F0000000000F0000000F000000000),
.INIT_43(256'hF10000000F00F00F0000000000F0FF1000000F000000000100F00000000000F0),
.INIT_44(256'h00000000000000F00000F100F00F00000000000F00000F100F00F00000000000),
.INIT_45(256'h0F00000010000200F0002100F00000010000200F0000100F00000000000F0F0D),
.INIT_46(256'h00110000200F0002100F00000010000200F0002100F00000010000200F000010),
.INIT_47(256'h000000000010000000F0000100F000F0FF00000000000000000000F0F0D00000),
.INIT_48(256'h0000F0001200F000F0FF00000000000000020000000F0002200F000F0FF00000),
.INIT_49(256'h002000F0FF0000000000002020F0FFD0000000000000000F0F0D000000012000),
.INIT_4A(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF2200),
.INIT_4B(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_4C(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_4D(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_4E(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_4F(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_50(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_51(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_52(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_53(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_54(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_55(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_56(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_57(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_58(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_59(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_5A(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_5B(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_5C(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_5D(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_5E(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_5F(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_60(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_61(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_62(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_63(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_64(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_65(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_66(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_67(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_68(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_69(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_6A(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_6B(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_6C(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_6D(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_6E(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_6F(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_70(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_71(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_72(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_73(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_74(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_75(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_76(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_77(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_78(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_79(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_7A(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_7B(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_7C(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_7D(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_7E(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_7F(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("PERFORMANCE"),
.READ_WIDTH_A(4),
.READ_WIDTH_B(0),
.RSTREG_PRIORITY_A("RSTREG"),
.RSTREG_PRIORITY_B("RSTREG"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("WRITE_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(4),
.WRITE_WIDTH_B(0))
program_counter_reg_rep_2
(.ADDRARDADDR({1'b1,program_counter_reg_rep_0_i_2_n_0,program_counter_reg_rep_0_i_3_n_0,program_counter_reg_rep_0_i_4_n_0,program_counter_reg_rep_0_i_5_n_0,program_counter_reg_rep_0_i_6_n_0,program_counter_reg_rep_0_i_7_n_0,program_counter_reg_rep_0_i_8_n_0,program_counter_reg_rep_0_i_9_n_0,program_counter_reg_rep_0_i_10_n_0,program_counter_reg_rep_0_i_11_n_0,program_counter_reg_rep_0_i_12_n_0,program_counter_reg_rep_0_i_13_n_0,program_counter_reg_rep_0_i_14_n_0,1'b0,1'b0}),
.ADDRBWRADDR({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
.CASCADEINA(1'b1),
.CASCADEINB(1'b0),
.CASCADEOUTA(NLW_program_counter_reg_rep_2_CASCADEOUTA_UNCONNECTED),
.CASCADEOUTB(NLW_program_counter_reg_rep_2_CASCADEOUTB_UNCONNECTED),
.CLKARDCLK(ETH_CLK_OBUF),
.CLKBWRCLK(1'b0),
.DBITERR(NLW_program_counter_reg_rep_2_DBITERR_UNCONNECTED),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b1,1'b1,1'b1,1'b1}),
.DIBDI({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
.DIPADIP({1'b0,1'b0,1'b0,1'b0}),
.DIPBDIP({1'b1,1'b1,1'b1,1'b1}),
.DOADO({NLW_program_counter_reg_rep_2_DOADO_UNCONNECTED[31:4],program_counter_reg_rep_2_n_32,program_counter_reg_rep_2_n_33,program_counter_reg_rep_2_n_34,program_counter_reg_rep_2_n_35}),
.DOBDO(NLW_program_counter_reg_rep_2_DOBDO_UNCONNECTED[31:0]),
.DOPADOP(NLW_program_counter_reg_rep_2_DOPADOP_UNCONNECTED[3:0]),
.DOPBDOP(NLW_program_counter_reg_rep_2_DOPBDOP_UNCONNECTED[3:0]),
.ECCPARITY(NLW_program_counter_reg_rep_2_ECCPARITY_UNCONNECTED[7:0]),
.ENARDEN(program_counter_reg_rep_0_i_1_n_0),
.ENBWREN(1'b0),
.INJECTDBITERR(NLW_program_counter_reg_rep_2_INJECTDBITERR_UNCONNECTED),
.INJECTSBITERR(NLW_program_counter_reg_rep_2_INJECTSBITERR_UNCONNECTED),
.RDADDRECC(NLW_program_counter_reg_rep_2_RDADDRECC_UNCONNECTED[8:0]),
.REGCEAREGCE(program_counter_reg_rep_0_REGCEAREGCE_cooolgate_en_sig_11),
.REGCEB(NLW_program_counter_reg_rep_2_REGCEB_UNCONNECTED),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(NLW_program_counter_reg_rep_2_SBITERR_UNCONNECTED),
.WEA({1'b0,1'b0,1'b0,1'b0}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
(* METHODOLOGY_DRC_VIOS = "" *)
(* RTL_RAM_BITS = "237568" *)
(* RTL_RAM_NAME = "program_counter" *)
(* bram_addr_begin = "0" *)
(* bram_addr_end = "8191" *)
(* bram_slice_begin = "12" *)
(* bram_slice_end = "15" *)
RAMB36E1 #(
.DOA_REG(1),
.DOB_REG(0),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h000000000000000000000000000F00000000F00000000F00000000F000000000),
.INIT_1A(256'h0000000000F0FF000000000000F0FF000000000000F0FF000000000000F0F000),
.INIT_1B(256'h0000000000F0FF000000000000F0FF000000000000F0FF000000000000F0FF00),
.INIT_1C(256'hF0FF0000000F00000000000000F0000000000F0FF00000000000000000F0F000),
.INIT_1D(256'hFF000000000000F0FF0000000F0000000000000F0FF0000000F0000000000000),
.INIT_1E(256'h00000000F0FF00000000F0FF00000000F0FF10000000000000000000000000F0),
.INIT_1F(256'h00000F0FF10000000000000F0000F00000000000000F0FF0000000000000000F),
.INIT_20(256'h100000000000F0F0100000000000F0F0100000000F0FF0000000000000F00000),
.INIT_21(256'h0F0F0100000000F0FF0000000000000F000000000000F0F0000000000000F0F0),
.INIT_22(256'h000000F0F0100000000F0FF0000000000000F000000000000F0F000000000000),
.INIT_23(256'h000000000F000000000000F0F0000000000000F0F0100000000000F0F0100000),
.INIT_24(256'h00000000000F0F0100000000000F0F0100000000000F0F0100000000F0FF0000),
.INIT_25(256'h00000000000000000000000000000000000000000000000000000000000F0F00),
.INIT_26(256'h0000000000000F0FF00000000000000F0FF000000000000F0FF0000000000000),
.INIT_27(256'h00F0000F0000F00F000000000F0FF000000000000F0FF00000000000000F0FF0),
.INIT_28(256'h0F0000F0000F0000F00000F00000F0000F0000F00F00000F0000F0000F00F000),
.INIT_29(256'hF0000F0000F00F00000F0000F0000F00F00000F0000F0000F0000F00000F0000),
.INIT_2A(256'h00000F0000000F0000F0000000F000000F00000000000F0000F0000F00F00000),
.INIT_2B(256'h0000F000000000F0000F0000000F0000000F0000F0000000F0000000F0000F00),
.INIT_2C(256'h00F000F000F0FF00000000000000000F0000000F000F000F0FF0000000000000),
.INIT_2D(256'h00000000F000F00000000F0000000F000F000F0FF00000000000000000F00000),
.INIT_2E(256'h00F00000000F00000F0FF00000000000000F000F00000000F00000F0FF000000),
.INIT_2F(256'h000000F0000F0000000000000F000F00000000F00000F0FF00000000000000F0),
.INIT_30(256'h0F00000000F00F00800000F00F0080000000000F0FF0000000000F00F0000000),
.INIT_31(256'h00000000000F0FF000000000000000000000F000F00000F00000000F000F0000),
.INIT_32(256'h000000000000000000000F0FF0000000F0000F000000000000000000000F0000),
.INIT_33(256'h000000000F0000000F0000F000000000F0000000F00000F000000000F00F0080),
.INIT_34(256'h000000F00F00F0000000F0000000000F0000000F0000F0000000000000000F00),
.INIT_35(256'h0000F0000F00000F0000000F000000000F0FF000000000000F00000000000000),
.INIT_36(256'h000000000000000000F00F0000000000000F0000F00000000000000F0000F000),
.INIT_37(256'h00000F00000F0000000F00000000F00000F000F00F000000F00000F000F00F00),
.INIT_38(256'h0F0000000000F00000F0000000F000F0000F00000F0FF0000000F00000F00000),
.INIT_39(256'h000F00000F0FF0000000F00000F0000000000F0000F00000F0FF0000000F0000),
.INIT_3A(256'h0000000000F0000000F000000000F0000000F0000000F00000000F00F00000F0),
.INIT_3B(256'hF0000000F0000000F000000000F0FF0000000F00F0000F000F0FF0000000F00F),
.INIT_3C(256'hFF0000000F00F0000F000F0FF0000000F00F0000000000F0000000F000000000),
.INIT_3D(256'h0000F00F0000000000F0000000F000000000F0000000F0000000F000000000F0),
.INIT_3E(256'hF0000000F0000000000F00000000F00000F0FF0000000F00F0000F000F0FF000),
.INIT_3F(256'h0F00F0000F000F0FF0000000F00F0000000000F0000000F000000000F0000000),
.INIT_40(256'h0000000000F0000000F000000000F0000000F0000000F000000000F0FF000000),
.INIT_41(256'hF0000000F0000000F000000000F0FF0000000F00F0000F000F0FF0000000F00F),
.INIT_42(256'hFF0000000F00F0000F000F0FF0000000F00F0000000000F0000000F000000000),
.INIT_43(256'hF10000000F00F00F0000001000F0FF1000000F000000000000F00000000000F0),
.INIT_44(256'h00000000000000F00000F100F00F00000000000F00000F100F00F00000000000),
.INIT_45(256'h0F00000010000000F0000100F00000010000000F0000100F00000000000F0F00),
.INIT_46(256'h00110000000F0000100F00000010000000F0000100F00000010000000F000010),
.INIT_47(256'h000000000010000000F0000100F000F0FF10000000000000000000F0F0000000),
.INIT_48(256'h0000F0000100F000F0FF10000000000000010000000F0000100F000F0FF10000),
.INIT_49(256'h000000F0FF1000000000001000F0FF00000000000000000F0F00000000011000),
.INIT_4A(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF1100),
.INIT_4B(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_4C(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_4D(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_4E(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_4F(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_50(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_51(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_52(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_53(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_54(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_55(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_56(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_57(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_58(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_59(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_5A(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_5B(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_5C(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_5D(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_5E(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_5F(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_60(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_61(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_62(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_63(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_64(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_65(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_66(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_67(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_68(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_69(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_6A(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_6B(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_6C(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_6D(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_6E(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_6F(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_70(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_71(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_72(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_73(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_74(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_75(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_76(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_77(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_78(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_79(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_7A(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_7B(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_7C(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_7D(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_7E(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_7F(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("PERFORMANCE"),
.READ_WIDTH_A(4),
.READ_WIDTH_B(0),
.RSTREG_PRIORITY_A("RSTREG"),
.RSTREG_PRIORITY_B("RSTREG"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("WRITE_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(4),
.WRITE_WIDTH_B(0))
program_counter_reg_rep_3
(.ADDRARDADDR({1'b1,program_counter_reg_rep_0_i_2_n_0,program_counter_reg_rep_0_i_3_n_0,program_counter_reg_rep_0_i_4_n_0,program_counter_reg_rep_0_i_5_n_0,program_counter_reg_rep_0_i_6_n_0,program_counter_reg_rep_0_i_7_n_0,program_counter_reg_rep_0_i_8_n_0,program_counter_reg_rep_0_i_9_n_0,program_counter_reg_rep_0_i_10_n_0,program_counter_reg_rep_0_i_11_n_0,program_counter_reg_rep_0_i_12_n_0,program_counter_reg_rep_0_i_13_n_0,program_counter_reg_rep_0_i_14_n_0,1'b0,1'b0}),
.ADDRBWRADDR({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
.CASCADEINA(1'b1),
.CASCADEINB(1'b0),
.CASCADEOUTA(NLW_program_counter_reg_rep_3_CASCADEOUTA_UNCONNECTED),
.CASCADEOUTB(NLW_program_counter_reg_rep_3_CASCADEOUTB_UNCONNECTED),
.CLKARDCLK(ETH_CLK_OBUF),
.CLKBWRCLK(1'b0),
.DBITERR(NLW_program_counter_reg_rep_3_DBITERR_UNCONNECTED),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b1,1'b1,1'b1,1'b1}),
.DIBDI({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
.DIPADIP({1'b0,1'b0,1'b0,1'b0}),
.DIPBDIP({1'b1,1'b1,1'b1,1'b1}),
.DOADO({NLW_program_counter_reg_rep_3_DOADO_UNCONNECTED[31:4],program_counter_reg_rep_3_n_32,program_counter_reg_rep_3_n_33,program_counter_reg_rep_3_n_34,program_counter_reg_rep_3_n_35}),
.DOBDO(NLW_program_counter_reg_rep_3_DOBDO_UNCONNECTED[31:0]),
.DOPADOP(NLW_program_counter_reg_rep_3_DOPADOP_UNCONNECTED[3:0]),
.DOPBDOP(NLW_program_counter_reg_rep_3_DOPBDOP_UNCONNECTED[3:0]),
.ECCPARITY(NLW_program_counter_reg_rep_3_ECCPARITY_UNCONNECTED[7:0]),
.ENARDEN(program_counter_reg_rep_0_i_1_n_0),
.ENBWREN(1'b0),
.INJECTDBITERR(NLW_program_counter_reg_rep_3_INJECTDBITERR_UNCONNECTED),
.INJECTSBITERR(NLW_program_counter_reg_rep_3_INJECTSBITERR_UNCONNECTED),
.RDADDRECC(NLW_program_counter_reg_rep_3_RDADDRECC_UNCONNECTED[8:0]),
.REGCEAREGCE(instruction0),
.REGCEB(NLW_program_counter_reg_rep_3_REGCEB_UNCONNECTED),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(NLW_program_counter_reg_rep_3_SBITERR_UNCONNECTED),
.WEA({1'b0,1'b0,1'b0,1'b0}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
(* IS_CLOCK_GATED *)
(* METHODOLOGY_DRC_VIOS = "" *)
(* POWER_OPTED_CE = "REGCEAREGCE=AUG" *)
(* RTL_RAM_BITS = "237568" *)
(* RTL_RAM_NAME = "program_counter" *)
(* bram_addr_begin = "0" *)
(* bram_addr_end = "8191" *)
(* bram_slice_begin = "16" *)
(* bram_slice_end = "19" *)
RAMB36E1 #(
.DOA_REG(1),
.DOB_REG(0),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0200200200200200200200200200200200200200200200200200200200200300),
.INIT_01(256'h0020020020020020020020020020020020020020020020020020020020020020),
.INIT_02(256'h2002002002002002002002002002002002002002002002002002002002002002),
.INIT_03(256'h0200200200200200200200200200200200200200200200200200200200200200),
.INIT_04(256'h0020020020020020020020020020020020020020020020020020020020020020),
.INIT_05(256'h2002002002002002002002002002002002002002002002002002002002002002),
.INIT_06(256'h0200200200200200200200200200200200200200200200200200200200200200),
.INIT_07(256'h0020020020020020020020020020020020020020020020020020020020020020),
.INIT_08(256'h2002002002002002002002002002002002002002002002002002002002002002),
.INIT_09(256'h0200200200200200200200200200200200200200200200200200200200200200),
.INIT_0A(256'h0020020020020020020020020020020020020020020020020020020020020020),
.INIT_0B(256'h2002002002002002002002002002002002002002002002002002002002002002),
.INIT_0C(256'h0200200200200200200200200200200200200200200200200200200200200200),
.INIT_0D(256'h0020020020020020020020020020020020020020020020020020020020020020),
.INIT_0E(256'h2002002002002002002002002002002002002002002002002002002002002002),
.INIT_0F(256'h0200200200200200200200200200200200200200200200200200200200200200),
.INIT_10(256'h0020020020020020020020020020020020020020020020020020020020020020),
.INIT_11(256'h2002002002002002002002002002002002002002002002002002002002002002),
.INIT_12(256'h0200200200200200200200200200200200200200200200200200200200200200),
.INIT_13(256'h0020020020020020020020020020020020020020020020020020020020020020),
.INIT_14(256'h2002002002002002002002002002002002002002002002002002002002002002),
.INIT_15(256'h0200200200200200200200200200200200200200200200200200200200200200),
.INIT_16(256'h0020020020020020020020020020020020020020020020020020020020020020),
.INIT_17(256'h2002002002002002002002002002002002002002002002002002002002002002),
.INIT_18(256'h2028030034200200200200200200200200200200200200200200200200200200),
.INIT_19(256'h4333320020020020020020020833033020833033020833033020833033020280),
.INIT_1A(256'h4330333333333303433033333333330343303333333333034330333333333303),
.INIT_1B(256'h4333324033333303433033333333330343303333333333034330333333333303),
.INIT_1C(256'h3333034338330332880333388332843308203333303433284333324203333303),
.INIT_1D(256'h3303433033333333330343383303328803333333333034338330332880333333),
.INIT_1E(256'h2843303333330343320333330343320333330343328433333303333333303333),
.INIT_1F(256'h0820333330343328433330332483328433033284033333303433033332408833),
.INIT_20(256'h0343333202033333034333320203333303433333333330343303333883328433),
.INIT_21(256'h3333303433333333330343303333883328433002403333330343333202033333),
.INIT_22(256'h3202033333034333333333303433033338833284330024033333303433332020),
.INIT_23(256'h3033338833284330024033333303433332020333330343333202033333034333),
.INIT_24(256'h3433332020333330343333202033333034333320203333303433333333330343),
.INIT_25(256'h3328033280332803328033280332803328033280330333336740002403333330),
.INIT_26(256'h3433280333333333303433280333333333303433033333333330343328033280),
.INIT_27(256'h2338828433833284330367433333303433033333333330343328033333333330),
.INIT_28(256'h3388284338332883303328433023388284338332843302338828433833284330),
.INIT_29(256'h3882843383328433023388284338332843302338828433833288330332843302),
.INIT_2A(256'h4332843302483328833284332843308833033284240233882843383328433023),
.INIT_2B(256'h3828433284248332883328433284330248332883328433284330248332883328),
.INIT_2C(256'h2338833203333303433284333333828433284233883320333330343328433333),
.INIT_2D(256'h8433332338833284338284332842338833203333303433284333333828433284),
.INIT_2E(256'h8332843382843320333330343328433332338833284338284332033333034332),
.INIT_2F(256'h3674033248332843303328423388332843382843320333330343328433332338),
.INIT_30(256'h8482842483328433802483328433803674202033333034330338332843303333),
.INIT_31(256'h8482842420333330343328433284333324284883303328482842428488330332),
.INIT_32(256'h2402402403674202802033333034332843328433333674202842428488330332),
.INIT_33(256'h4330024833284332842483328433088332843328402483328433088332843380),
.INIT_34(256'h0284024833284330248332843302483328433033248332843303328400883328),
.INIT_35(256'h3328433284828833284332842403674333333034332803328433333674202842),
.INIT_36(256'h0367420828036743033284332803674000332483328433033284303328833284),
.INIT_37(256'h3388332882843328828436742083303328488332843308833033284883328433),
.INIT_38(256'h8433033338833288284332882840233882843320333330343383328828433033),
.INIT_39(256'h8284332033333034338332882843303333023388284332033333034338332882),
.INIT_3A(256'h2843328828433288284333333828433288284332882843333248332843302338),
.INIT_3B(256'h4332882843328828433332420333330343383383328833203333303433833833),
.INIT_3C(256'h3303433833833288332033333034338338332843328828433288284333333828),
.INIT_3D(256'h3383383328433288284332882843333338284332882843328828433332420333),
.INIT_3E(256'h4332882843333242883328433828424203333303433833833288332033333034),
.INIT_3F(256'h3383328833203333303433833833284332882843328828433333382843328828),
.INIT_40(256'h2843328828433288284333333828433288284332882843333242033333034338),
.INIT_41(256'h4332882843328828433332420333330343383383328833203333303433833833),
.INIT_42(256'h3303433833833288332033333034338338332843328828433288284333333828),
.INIT_43(256'h4067420833833284330330820333330343328433333674208332843302420333),
.INIT_44(256'h3433333674208330332848833284330367420833033284883328433036742028),
.INIT_45(256'h3328433006742083303308833284330067420833033088332843302420333330),
.INIT_46(256'h3300674208330330883328433006742083303308833284330067420833033088),
.INIT_47(256'h2843333330067420833033088332033333034332843333330242033333034333),
.INIT_48(256'h2083303308833203333303433284333333006742083303308833203333303433),
.INIT_49(256'h4202033333034332843333820333330343328433332420333330343333300674),
.INIT_4A(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF0067),
.INIT_4B(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_4C(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_4D(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_4E(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_4F(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_50(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_51(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_52(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_53(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_54(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_55(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_56(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_57(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_58(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_59(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_5A(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_5B(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_5C(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_5D(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_5E(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_5F(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_60(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_61(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_62(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_63(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_64(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_65(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_66(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_67(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_68(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_69(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_6A(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_6B(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_6C(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_6D(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_6E(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_6F(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_70(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_71(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_72(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_73(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_74(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_75(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_76(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_77(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_78(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_79(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_7A(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_7B(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_7C(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_7D(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_7E(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_7F(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("PERFORMANCE"),
.READ_WIDTH_A(4),
.READ_WIDTH_B(0),
.RSTREG_PRIORITY_A("RSTREG"),
.RSTREG_PRIORITY_B("RSTREG"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("WRITE_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(4),
.WRITE_WIDTH_B(0))
program_counter_reg_rep_4
(.ADDRARDADDR({1'b1,program_counter_reg_rep_0_i_2_n_0,program_counter_reg_rep_0_i_3_n_0,program_counter_reg_rep_0_i_4_n_0,program_counter_reg_rep_0_i_5_n_0,program_counter_reg_rep_0_i_6_n_0,program_counter_reg_rep_0_i_7_n_0,program_counter_reg_rep_0_i_8_n_0,program_counter_reg_rep_0_i_9_n_0,program_counter_reg_rep_0_i_10_n_0,program_counter_reg_rep_0_i_11_n_0,program_counter_reg_rep_0_i_12_n_0,program_counter_reg_rep_0_i_13_n_0,program_counter_reg_rep_0_i_14_n_0,1'b0,1'b0}),
.ADDRBWRADDR({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
.CASCADEINA(1'b1),
.CASCADEINB(1'b0),
.CASCADEOUTA(NLW_program_counter_reg_rep_4_CASCADEOUTA_UNCONNECTED),
.CASCADEOUTB(NLW_program_counter_reg_rep_4_CASCADEOUTB_UNCONNECTED),
.CLKARDCLK(ETH_CLK_OBUF),
.CLKBWRCLK(1'b0),
.DBITERR(NLW_program_counter_reg_rep_4_DBITERR_UNCONNECTED),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b1,1'b1,1'b1,1'b1}),
.DIBDI({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
.DIPADIP({1'b0,1'b0,1'b0,1'b0}),
.DIPBDIP({1'b1,1'b1,1'b1,1'b1}),
.DOADO({NLW_program_counter_reg_rep_4_DOADO_UNCONNECTED[31:4],address_a}),
.DOBDO(NLW_program_counter_reg_rep_4_DOBDO_UNCONNECTED[31:0]),
.DOPADOP(NLW_program_counter_reg_rep_4_DOPADOP_UNCONNECTED[3:0]),
.DOPBDOP(NLW_program_counter_reg_rep_4_DOPBDOP_UNCONNECTED[3:0]),
.ECCPARITY(NLW_program_counter_reg_rep_4_ECCPARITY_UNCONNECTED[7:0]),
.ENARDEN(program_counter_reg_rep_0_i_1_n_0),
.ENBWREN(1'b0),
.INJECTDBITERR(NLW_program_counter_reg_rep_4_INJECTDBITERR_UNCONNECTED),
.INJECTSBITERR(NLW_program_counter_reg_rep_4_INJECTSBITERR_UNCONNECTED),
.RDADDRECC(NLW_program_counter_reg_rep_4_RDADDRECC_UNCONNECTED[8:0]),
.REGCEAREGCE(program_counter_reg_rep_0_REGCEAREGCE_cooolgate_en_sig_11),
.REGCEB(NLW_program_counter_reg_rep_4_REGCEB_UNCONNECTED),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(NLW_program_counter_reg_rep_4_SBITERR_UNCONNECTED),
.WEA({1'b0,1'b0,1'b0,1'b0}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
(* IS_CLOCK_GATED *)
(* METHODOLOGY_DRC_VIOS = "" *)
(* POWER_OPTED_CE = "REGCEAREGCE=AUG" *)
(* RTL_RAM_BITS = "237568" *)
(* RTL_RAM_NAME = "program_counter" *)
(* bram_addr_begin = "0" *)
(* bram_addr_end = "8191" *)
(* bram_slice_begin = "20" *)
(* bram_slice_end = "23" *)
RAMB36E1 #(
.DOA_REG(1),
.DOB_REG(0),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h8028028028028028028028028028028028028028028028028028028028028343),
.INIT_01(256'h2802802802802802802802802802802802802802802802802802802802802802),
.INIT_02(256'h0280280280280280280280280280280280280280280280280280280280280280),
.INIT_03(256'h8028028028028028028028028028028028028028028028028028028028028028),
.INIT_04(256'h2802802802802802802802802802802802802802802802802802802802802802),
.INIT_05(256'h0280280280280280280280280280280280280280280280280280280280280280),
.INIT_06(256'h8028028028028028028028028028028028028028028028028028028028028028),
.INIT_07(256'h2802802802802802802802802802802802802802802802802802802802802802),
.INIT_08(256'h0280280280280280280280280280280280280280280280280280280280280280),
.INIT_09(256'h8028028028028028028028028028028028028028028028028028028028028028),
.INIT_0A(256'h2802802802802802802802802802802802802802802802802802802802802802),
.INIT_0B(256'h0280280280280280280280280280280280280280280280280280280280280280),
.INIT_0C(256'h8028028028028028028028028028028028028028028028028028028028028028),
.INIT_0D(256'h2802802802802802802802802802802802802802802802802802802802802802),
.INIT_0E(256'h0280280280280280280280280280280280280280280280280280280280280280),
.INIT_0F(256'h8028028028028028028028028028028028028028028028028028028028028028),
.INIT_10(256'h2802802802802802802802802802802802802802802802802802802802802802),
.INIT_11(256'h0280280280280280280280280280280280280280280280280280280280280280),
.INIT_12(256'h8028028028028028028028028028028028028028028028028028028028028028),
.INIT_13(256'h2802802802802802802802802802802802802802802802802802802802802802),
.INIT_14(256'h0280280280280280280280280280280280280280280280280280280280280280),
.INIT_15(256'h8028028028028028028028028028028028028028028028028028028028028028),
.INIT_16(256'h2802802802802802802802802802802802802802802802802802802802802802),
.INIT_17(256'h0280280280280280280280280280280280280280280280280280280280280280),
.INIT_18(256'h0282830647028028028028028028028028028028028028028028028028028028),
.INIT_19(256'h7303002802802802802802802823830802823830802823830802823830802828),
.INIT_1A(256'h7308303036373364730830303637336473083030363733647308303036373364),
.INIT_1B(256'h7303002836373364730830303637336473083030363733647308303036373364),
.INIT_1C(256'h3733647308A38308288303008A38283080826373364730828303002826373364),
.INIT_1D(256'h336473083030363733647308A383082883030363733647308A38308288303036),
.INIT_1E(256'h8283083637336473082637336473082637336473082830303083030303003637),
.INIT_1F(256'h808263733647308283030083028A3828308308280363733647308303002808A3),
.INIT_20(256'h647303002826373364730300282637336473030363733647308303008A382830),
.INIT_21(256'h637336473030363733647308303008A382830800283637336473030028263733),
.INIT_22(256'h00282637336473030363733647308303008A3828308002836373364730300282),
.INIT_23(256'h08303008A3828308002836373364730300282637336473030028263733647303),
.INIT_24(256'h4730300282637336473030028263733647303002826373364730303637336473),
.INIT_25(256'h3082830828308283082830828308283082830828308303030430000283637336),
.INIT_26(256'h4730828303036373364730828303036373364730830303637336473082830828),
.INIT_27(256'h08328828308A3828308304336373364730830303637336473082830303637336),
.INIT_28(256'h8328828308A38282383082830808328828308A382830808328828308A3828308),
.INIT_29(256'h328828308A382830808328828308A382830808328828308A3828238308283080),
.INIT_2A(256'h830828308028A3828238283082830808A383082802808328828308A382830808),
.INIT_2B(256'h0882830828028A38282382830828308028A38282382830828308028A38282382),
.INIT_2C(256'h0832823826373364730828303030882830828083282382637336473082830303),
.INIT_2D(256'h2830300832823828308828308280832823826373364730828303030882830828),
.INIT_2E(256'h8238283088283082637336473082830300832823828308828308263733647308),
.INIT_2F(256'h3043083028A38283083082808328238283088283082637336473082830300832),
.INIT_30(256'h280828028A38283088028A382830883043028263733647308308A38283083030),
.INIT_31(256'h280828028263733647308283082830300282808A383082808280282808A38308),
.INIT_32(256'h0280280283043028288263733647308283082830303043028280282808A38308),
.INIT_33(256'h83080028A382830828028A382830808A3828308280028A382830808A38283088),
.INIT_34(256'h28280028A3828308028A3828308028A382830883028A3828308308280008A382),
.INIT_35(256'h3082830828082823828308280283043363733647308283082830303043028280),
.INIT_36(256'h830430288283043300382830828304300083028A382830830828300382823828),
.INIT_37(256'h3008A3828828308288283043028A383082808A382830808A383082808A382830),
.INIT_38(256'h28308303008A382882830828828008328828308263733647308A382882830830),
.INIT_39(256'h8828308263733647308A38288283083030008328828308263733647308A38288),
.INIT_3A(256'h8283082882830828828303030882830828828308288283030028A38283080832),
.INIT_3B(256'h830828828308288283030028263733647308A38A3828238263733647308A38A3),
.INIT_3C(256'h33647308A38A3828238263733647308A38A38283082882830828828303030882),
.INIT_3D(256'h308A38A382830828828308288283030308828308288283082882830300282637),
.INIT_3E(256'h83082882830300282823828308828028263733647308A38A3828238263733647),
.INIT_3F(256'hA38A3828238263733647308A38A3828308288283082882830303088283082882),
.INIT_40(256'h8283082882830828828303030882830828828308288283030028263733647308),
.INIT_41(256'h830828828308288283030028263733647308A38A3828238263733647308A38A3),
.INIT_42(256'h33647308A38A3828238263733647308A38A38283082882830828828303030882),
.INIT_43(256'h80043028A38A3828308308082637336473082830303043028A38283080282637),
.INIT_44(256'h4730303043028A383082808A38283083043028A383082808A382830830430282),
.INIT_45(256'hA3828308004302823830808A3828308004302823830808A38283080282637336),
.INIT_46(256'h030004302823830808A3828308004302823830808A3828308004302823830808),
.INIT_47(256'h8283030308004302823830808A38263733647308283030308028263733647303),
.INIT_48(256'h02823830808A38263733647308283030308004302823830808A3826373364730),
.INIT_49(256'h3028263733647308283030082637336473082830300282637336473030300043),
.INIT_4A(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF0004),
.INIT_4B(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_4C(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_4D(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_4E(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_4F(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_50(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_51(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_52(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_53(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_54(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_55(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_56(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_57(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_58(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_59(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_5A(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_5B(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_5C(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_5D(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_5E(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_5F(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_60(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_61(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_62(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_63(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_64(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_65(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_66(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_67(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_68(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_69(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_6A(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_6B(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_6C(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_6D(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_6E(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_6F(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_70(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_71(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_72(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_73(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_74(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_75(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_76(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_77(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_78(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_79(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_7A(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_7B(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_7C(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_7D(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_7E(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_7F(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("PERFORMANCE"),
.READ_WIDTH_A(4),
.READ_WIDTH_B(0),
.RSTREG_PRIORITY_A("RSTREG"),
.RSTREG_PRIORITY_B("RSTREG"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("WRITE_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(4),
.WRITE_WIDTH_B(0))
program_counter_reg_rep_5
(.ADDRARDADDR({1'b1,program_counter_reg_rep_0_i_2_n_0,program_counter_reg_rep_0_i_3_n_0,program_counter_reg_rep_0_i_4_n_0,program_counter_reg_rep_0_i_5_n_0,program_counter_reg_rep_0_i_6_n_0,program_counter_reg_rep_0_i_7_n_0,program_counter_reg_rep_0_i_8_n_0,program_counter_reg_rep_0_i_9_n_0,program_counter_reg_rep_0_i_10_n_0,program_counter_reg_rep_0_i_11_n_0,program_counter_reg_rep_0_i_12_n_0,program_counter_reg_rep_0_i_13_n_0,program_counter_reg_rep_0_i_14_n_0,1'b0,1'b0}),
.ADDRBWRADDR({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
.CASCADEINA(1'b1),
.CASCADEINB(1'b0),
.CASCADEOUTA(NLW_program_counter_reg_rep_5_CASCADEOUTA_UNCONNECTED),
.CASCADEOUTB(NLW_program_counter_reg_rep_5_CASCADEOUTB_UNCONNECTED),
.CLKARDCLK(ETH_CLK_OBUF),
.CLKBWRCLK(1'b0),
.DBITERR(NLW_program_counter_reg_rep_5_DBITERR_UNCONNECTED),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b1,1'b1,1'b1,1'b1}),
.DIBDI({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
.DIPADIP({1'b0,1'b0,1'b0,1'b0}),
.DIPBDIP({1'b1,1'b1,1'b1,1'b1}),
.DOADO({NLW_program_counter_reg_rep_5_DOADO_UNCONNECTED[31:4],address_z}),
.DOBDO(NLW_program_counter_reg_rep_5_DOBDO_UNCONNECTED[31:0]),
.DOPADOP(NLW_program_counter_reg_rep_5_DOPADOP_UNCONNECTED[3:0]),
.DOPBDOP(NLW_program_counter_reg_rep_5_DOPBDOP_UNCONNECTED[3:0]),
.ECCPARITY(NLW_program_counter_reg_rep_5_ECCPARITY_UNCONNECTED[7:0]),
.ENARDEN(program_counter_reg_rep_0_i_1_n_0),
.ENBWREN(1'b0),
.INJECTDBITERR(NLW_program_counter_reg_rep_5_INJECTDBITERR_UNCONNECTED),
.INJECTSBITERR(NLW_program_counter_reg_rep_5_INJECTSBITERR_UNCONNECTED),
.RDADDRECC(NLW_program_counter_reg_rep_5_RDADDRECC_UNCONNECTED[8:0]),
.REGCEAREGCE(program_counter_reg_rep_0_REGCEAREGCE_cooolgate_en_sig_11),
.REGCEB(NLW_program_counter_reg_rep_5_REGCEB_UNCONNECTED),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(NLW_program_counter_reg_rep_5_SBITERR_UNCONNECTED),
.WEA({1'b0,1'b0,1'b0,1'b0}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
(* IS_CLOCK_GATED *)
(* METHODOLOGY_DRC_VIOS = "" *)
(* POWER_OPTED_CE = "REGCEAREGCE=AUG" *)
(* RTL_RAM_BITS = "237568" *)
(* RTL_RAM_NAME = "program_counter" *)
(* bram_addr_begin = "0" *)
(* bram_addr_end = "8191" *)
(* bram_slice_begin = "24" *)
(* bram_slice_end = "27" *)
RAMB36E1 #(
.DOA_REG(1),
.DOB_REG(0),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0200200200200200200200200200200200200200200200200200200200200100),
.INIT_01(256'h0020020020020020020020020020020020020020020020020020020020020020),
.INIT_02(256'h2002002002002002002002002002002002002002002002002002002002002002),
.INIT_03(256'h0200200200200200200200200200200200200200200200200200200200200200),
.INIT_04(256'h0020020020020020020020020020020020020020020020020020020020020020),
.INIT_05(256'h2002002002002002002002002002002002002002002002002002002002002002),
.INIT_06(256'h0200200200200200200200200200200200200200200200200200200200200200),
.INIT_07(256'h0020020020020020020020020020020020020020020020020020020020020020),
.INIT_08(256'h2002002002002002002002002002002002002002002002002002002002002002),
.INIT_09(256'h0200200200200200200200200200200200200200200200200200200200200200),
.INIT_0A(256'h0020020020020020020020020020020020020020020020020020020020020020),
.INIT_0B(256'h2002002002002002002002002002002002002002002002002002002002002002),
.INIT_0C(256'h0200200200200200200200200200200200200200200200200200200200200200),
.INIT_0D(256'h0020020020020020020020020020020020020020020020020020020020020020),
.INIT_0E(256'h2002002002002002002002002002002002002002002002002002002002002002),
.INIT_0F(256'h0200200200200200200200200200200200200200200200200200200200200200),
.INIT_10(256'h0020020020020020020020020020020020020020020020020020020020020020),
.INIT_11(256'h2002002002002002002002002002002002002002002002002002002002002002),
.INIT_12(256'h0200200200200200200200200200200200200200200200200200200200200200),
.INIT_13(256'h0020020020020020020020020020020020020020020020020020020020020020),
.INIT_14(256'h2002002002002002002002002002002002002002002002002002002002002002),
.INIT_15(256'h0200200200200200200200200200200200200200200200200200200200200200),
.INIT_16(256'h0020020020020020020020020020020020020020020020020020020020020020),
.INIT_17(256'h2002002002002002002002002002002002002002002002002002002002002002),
.INIT_18(256'h2051014311200200200200200200200200200200200200200200200200200200),
.INIT_19(256'h1121220020020020020020020651012020651012020651012020651012020510),
.INIT_1A(256'h1120121215151131112012121515113111201212151511311120121215151131),
.INIT_1B(256'h1121221015151131112012121515113111201212151511311120121215151131),
.INIT_1C(256'h1511311126510125110121278515111207505151131112511121221505151131),
.INIT_1D(256'h1131112012121515113111265101251101212151511311126510125110121215),
.INIT_1E(256'h5111201515113111250515113111250515113111251112121201212121291515),
.INIT_1F(256'h0750515113111251112129512165151112012511915151131112012122107851),
.INIT_20(256'h3111212205051511311121220505151131112121515113111201212785151112),
.INIT_21(256'h5151131112121515113111201212785151112092101515113111212205051511),
.INIT_22(256'h2205051511311121215151131112012127851511120921015151131112122050),
.INIT_23(256'h2012127851511120921015151131112122050515113111212205051511311121),
.INIT_24(256'h1112122050515113111212205051511311121220505151131112121515113111),
.INIT_25(256'h125101251012510125101251012510125101251012012121A119992101515113),
.INIT_26(256'h1112510121215151131112510121215151131112012121515113111251012510),
.INIT_27(256'h2511151112B515111201A1115151131112012121515113111251012121515113),
.INIT_28(256'h511151112B51516510125111202511151112B515111202511151112B51511120),
.INIT_29(256'h11151112B515111202511151112B515111202511151112B51516510125111202),
.INIT_2A(256'h11251112021B5151651511125111207C510125112102511151112B5151112025),
.INIT_2B(256'h215111251121B51516515111251112021B51516515111251112021B515165151),
.INIT_2C(256'h2511651505151131112511121212151112511251165150515113111251112121),
.INIT_2D(256'h1112122511651511121511125112511651505151131112511121212151112511),
.INIT_2E(256'h6515111215111250515113111251112122511651511121511125051511311125),
.INIT_2F(256'h1A11951216515111201251125116515111215111250515113111251112122511),
.INIT_30(256'h11751121E5151112D021E5151112D01A11205051511311120126515111201212),
.INIT_31(256'h11751121505151131112511125111212215119B510125117511215119B510125),
.INIT_32(256'h2102102101A11205105051511311125111251112121A1120511215119B510125),
.INIT_33(256'h1120921B515111251121F51511120705151112511921F515111207E5151112D0),
.INIT_34(256'h0511921151511120211515111202115151112051216515111201251199785151),
.INIT_35(256'h1251112511751651511125112101A11151511311125101251112121A11205112),
.INIT_36(256'h01A112035101A111251511125101A11999512165151112012511125151651511),
.INIT_37(256'h127851511511125115111A112045101251174515111205451012511745151112),
.INIT_38(256'h1112012127851511511125115119251115111250515113111265151151112012),
.INIT_39(256'h1511125051511311126515115111201212925111511125051511311126515115),
.INIT_3A(256'h511125115111251151112121215111251151112511511121221B515111202511),
.INIT_3B(256'h11251151112511511121221505151131112651B5151651505151131112B51651),
.INIT_3C(256'h1131112651B5151651505151131112B516515111251151112511511121212151),
.INIT_3D(256'h12B5165151112511511125115111212121511125115111251151112122150515),
.INIT_3E(256'h1125115111212215165151112151121505151131112651B51516515051511311),
.INIT_3F(256'h51B5151651505151131112B51651511125115111251151112121215111251151),
.INIT_40(256'h5111251151112511511121212151112511511125115111212215051511311126),
.INIT_41(256'h11251151112511511121221505151131112651B5151651505151131112B51651),
.INIT_42(256'h1131112651B5151651505151131112B516515111251151112511511121212151),
.INIT_43(256'h19A1120651B51511120120750515113111251112121A11206515111202150515),
.INIT_44(256'h1112121A112045101251174515111201A112045101251174515111201A112051),
.INIT_45(256'h515111209A1120651012078515111209A1120651012078515111202150515113),
.INIT_46(256'h2199A1120651012078515111209A1120651012078515111209A1120651012078),
.INIT_47(256'h51112121209A1120651012078515051511311125111212120215051511311121),
.INIT_48(256'h206510120785150515113111251112121209A112065101207851505151131112),
.INIT_49(256'h1205051511311125111212750515113111251112122150515113111212199A11),
.INIT_4A(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF99A1),
.INIT_4B(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_4C(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_4D(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_4E(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_4F(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_50(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_51(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_52(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_53(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_54(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_55(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_56(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_57(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_58(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_59(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_5A(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_5B(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_5C(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_5D(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_5E(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_5F(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_60(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_61(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_62(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_63(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_64(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_65(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_66(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_67(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_68(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_69(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_6A(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_6B(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_6C(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_6D(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_6E(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_6F(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_70(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_71(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_72(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_73(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_74(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_75(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_76(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_77(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_78(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_79(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_7A(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_7B(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_7C(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_7D(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_7E(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_7F(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("PERFORMANCE"),
.READ_WIDTH_A(4),
.READ_WIDTH_B(0),
.RSTREG_PRIORITY_A("RSTREG"),
.RSTREG_PRIORITY_B("RSTREG"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("WRITE_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(4),
.WRITE_WIDTH_B(0))
program_counter_reg_rep_6
(.ADDRARDADDR({1'b1,program_counter_reg_rep_0_i_2_n_0,program_counter_reg_rep_0_i_3_n_0,program_counter_reg_rep_0_i_4_n_0,program_counter_reg_rep_0_i_5_n_0,program_counter_reg_rep_0_i_6_n_0,program_counter_reg_rep_0_i_7_n_0,program_counter_reg_rep_0_i_8_n_0,program_counter_reg_rep_0_i_9_n_0,program_counter_reg_rep_0_i_10_n_0,program_counter_reg_rep_0_i_11_n_0,program_counter_reg_rep_0_i_12_n_0,program_counter_reg_rep_0_i_13_n_0,program_counter_reg_rep_0_i_14_n_0,1'b0,1'b0}),
.ADDRBWRADDR({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
.CASCADEINA(1'b1),
.CASCADEINB(1'b0),
.CASCADEOUTA(NLW_program_counter_reg_rep_6_CASCADEOUTA_UNCONNECTED),
.CASCADEOUTB(NLW_program_counter_reg_rep_6_CASCADEOUTB_UNCONNECTED),
.CLKARDCLK(ETH_CLK_OBUF),
.CLKBWRCLK(1'b0),
.DBITERR(NLW_program_counter_reg_rep_6_DBITERR_UNCONNECTED),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b1,1'b1,1'b1,1'b1}),
.DIBDI({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
.DIPADIP({1'b0,1'b0,1'b0,1'b0}),
.DIPBDIP({1'b1,1'b1,1'b1,1'b1}),
.DOADO({NLW_program_counter_reg_rep_6_DOADO_UNCONNECTED[31:4],opcode[3:0]}),
.DOBDO(NLW_program_counter_reg_rep_6_DOBDO_UNCONNECTED[31:0]),
.DOPADOP(NLW_program_counter_reg_rep_6_DOPADOP_UNCONNECTED[3:0]),
.DOPBDOP(NLW_program_counter_reg_rep_6_DOPBDOP_UNCONNECTED[3:0]),
.ECCPARITY(NLW_program_counter_reg_rep_6_ECCPARITY_UNCONNECTED[7:0]),
.ENARDEN(program_counter_reg_rep_0_i_1_n_0),
.ENBWREN(1'b0),
.INJECTDBITERR(NLW_program_counter_reg_rep_6_INJECTDBITERR_UNCONNECTED),
.INJECTSBITERR(NLW_program_counter_reg_rep_6_INJECTSBITERR_UNCONNECTED),
.RDADDRECC(NLW_program_counter_reg_rep_6_RDADDRECC_UNCONNECTED[8:0]),
.REGCEAREGCE(program_counter_reg_rep_0_REGCEAREGCE_cooolgate_en_sig_11),
.REGCEB(NLW_program_counter_reg_rep_6_REGCEB_UNCONNECTED),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(NLW_program_counter_reg_rep_6_SBITERR_UNCONNECTED),
.WEA({1'b0,1'b0,1'b0,1'b0}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
(* IS_CLOCK_GATED *)
(* METHODOLOGY_DRC_VIOS = "" *)
(* POWER_OPTED_CE = "REGCEAREGCE=AUG" *)
(* RTL_RAM_BITS = "237568" *)
(* RTL_RAM_NAME = "program_counter" *)
(* bram_addr_begin = "0" *)
(* bram_addr_end = "8191" *)
(* bram_slice_begin = "28" *)
(* bram_slice_end = "31" *)
RAMB18E1 #(
.DOA_REG(1),
.DOB_REG(0),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000004000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000010000040000100000000000000000),
.INIT_1B(256'h0000000000000400004000140000400000010000400000000000000000100000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000040000400000010000100000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF00),
.INIT_26(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_27(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_28(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_29(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_2A(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_2B(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_2C(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_2D(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_2E(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_2F(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_30(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_31(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_32(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_33(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_34(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_35(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_36(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_37(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_38(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_39(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_3A(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_3B(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_3C(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_3D(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_3E(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_3F(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_A(18'h00000),
.INIT_B(18'h00000),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("PERFORMANCE"),
.READ_WIDTH_A(2),
.READ_WIDTH_B(0),
.RSTREG_PRIORITY_A("RSTREG"),
.RSTREG_PRIORITY_B("RSTREG"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(18'h00000),
.SRVAL_B(18'h00000),
.WRITE_MODE_A("WRITE_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(2),
.WRITE_WIDTH_B(0))
program_counter_reg_rep_7
(.ADDRARDADDR({program_counter_reg_rep_0_i_2_n_0,program_counter_reg_rep_0_i_3_n_0,program_counter_reg_rep_0_i_4_n_0,program_counter_reg_rep_0_i_5_n_0,program_counter_reg_rep_0_i_6_n_0,program_counter_reg_rep_0_i_7_n_0,program_counter_reg_rep_0_i_8_n_0,program_counter_reg_rep_0_i_9_n_0,program_counter_reg_rep_0_i_10_n_0,program_counter_reg_rep_0_i_11_n_0,program_counter_reg_rep_0_i_12_n_0,program_counter_reg_rep_0_i_13_n_0,program_counter_reg_rep_0_i_14_n_0,1'b0}),
.ADDRBWRADDR({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
.CLKARDCLK(ETH_CLK_OBUF),
.CLKBWRCLK(1'b0),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b1}),
.DIBDI({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
.DIPADIP({1'b0,1'b0}),
.DIPBDIP({1'b1,1'b1}),
.DOADO({NLW_program_counter_reg_rep_7_DOADO_UNCONNECTED[15:1],opcode[4]}),
.DOBDO(NLW_program_counter_reg_rep_7_DOBDO_UNCONNECTED[15:0]),
.DOPADOP(NLW_program_counter_reg_rep_7_DOPADOP_UNCONNECTED[1:0]),
.DOPBDOP(NLW_program_counter_reg_rep_7_DOPBDOP_UNCONNECTED[1:0]),
.ENARDEN(program_counter_reg_rep_0_i_1_n_0),
.ENBWREN(1'b0),
.REGCEAREGCE(program_counter_reg_rep_0_REGCEAREGCE_cooolgate_en_sig_11),
.REGCEB(NLW_program_counter_reg_rep_7_REGCEB_UNCONNECTED),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.WEA({1'b0,1'b0}),
.WEBWE({1'b0,1'b0,1'b0,1'b0}));
LUT5 #(
.INIT(32'hFFFB0008))
\read_input[0]_i_1
(.I0(result[0]),
.I1(write_enable_reg_n_0),
.I2(\read_input[31]_i_4_n_0 ),
.I3(\read_input[31]_i_5_n_0 ),
.I4(register_a[0]),
.O(\read_input[0]_i_1_n_0 ));
LUT5 #(
.INIT(32'hFFFB0008))
\read_input[10]_i_1
(.I0(result[10]),
.I1(write_enable_reg_n_0),
.I2(\read_input[31]_i_4_n_0 ),
.I3(\read_input[31]_i_5_n_0 ),
.I4(register_a[10]),
.O(\read_input[10]_i_1_n_0 ));
LUT5 #(
.INIT(32'hFFFB0008))
\read_input[11]_i_1
(.I0(result[11]),
.I1(write_enable_reg_n_0),
.I2(\read_input[31]_i_4_n_0 ),
.I3(\read_input[31]_i_5_n_0 ),
.I4(register_a[11]),
.O(\read_input[11]_i_1_n_0 ));
LUT5 #(
.INIT(32'hFFFB0008))
\read_input[12]_i_1
(.I0(result[12]),
.I1(write_enable_reg_n_0),
.I2(\read_input[31]_i_4_n_0 ),
.I3(\read_input[31]_i_5_n_0 ),
.I4(register_a[12]),
.O(\read_input[12]_i_1_n_0 ));
LUT5 #(
.INIT(32'hFFFB0008))
\read_input[13]_i_1
(.I0(result[13]),
.I1(write_enable_reg_n_0),
.I2(\read_input[31]_i_4_n_0 ),
.I3(\read_input[31]_i_5_n_0 ),
.I4(register_a[13]),
.O(\read_input[13]_i_1_n_0 ));
LUT5 #(
.INIT(32'hFFFB0008))
\read_input[14]_i_1
(.I0(result[14]),
.I1(write_enable_reg_n_0),
.I2(\read_input[31]_i_4_n_0 ),
.I3(\read_input[31]_i_5_n_0 ),
.I4(register_a[14]),
.O(\read_input[14]_i_1_n_0 ));
LUT5 #(
.INIT(32'hFFFB0008))
\read_input[15]_i_1
(.I0(result[15]),
.I1(write_enable_reg_n_0),
.I2(\read_input[31]_i_4_n_0 ),
.I3(\read_input[31]_i_5_n_0 ),
.I4(register_a[15]),
.O(\read_input[15]_i_1_n_0 ));
LUT5 #(
.INIT(32'hFFFB0008))
\read_input[16]_i_1
(.I0(result[16]),
.I1(write_enable_reg_n_0),
.I2(\read_input[31]_i_4_n_0 ),
.I3(\read_input[31]_i_5_n_0 ),
.I4(register_a[16]),
.O(\read_input[16]_i_1_n_0 ));
LUT5 #(
.INIT(32'hFFFB0008))
\read_input[17]_i_1
(.I0(result[17]),
.I1(write_enable_reg_n_0),
.I2(\read_input[31]_i_4_n_0 ),
.I3(\read_input[31]_i_5_n_0 ),
.I4(register_a[17]),
.O(\read_input[17]_i_1_n_0 ));
LUT5 #(
.INIT(32'hFFFB0008))
\read_input[18]_i_1
(.I0(result[18]),
.I1(write_enable_reg_n_0),
.I2(\read_input[31]_i_4_n_0 ),
.I3(\read_input[31]_i_5_n_0 ),
.I4(register_a[18]),
.O(\read_input[18]_i_1_n_0 ));
LUT5 #(
.INIT(32'hFFFB0008))
\read_input[19]_i_1
(.I0(result[19]),
.I1(write_enable_reg_n_0),
.I2(\read_input[31]_i_4_n_0 ),
.I3(\read_input[31]_i_5_n_0 ),
.I4(register_a[19]),
.O(\read_input[19]_i_1_n_0 ));
LUT5 #(
.INIT(32'hFFFB0008))
\read_input[1]_i_1
(.I0(result[1]),
.I1(write_enable_reg_n_0),
.I2(\read_input[31]_i_4_n_0 ),
.I3(\read_input[31]_i_5_n_0 ),
.I4(register_a[1]),
.O(\read_input[1]_i_1_n_0 ));
LUT5 #(
.INIT(32'hFFFB0008))
\read_input[20]_i_1
(.I0(result[20]),
.I1(write_enable_reg_n_0),
.I2(\read_input[31]_i_4_n_0 ),
.I3(\read_input[31]_i_5_n_0 ),
.I4(register_a[20]),
.O(\read_input[20]_i_1_n_0 ));
LUT5 #(
.INIT(32'hFFFB0008))
\read_input[21]_i_1
(.I0(result[21]),
.I1(write_enable_reg_n_0),
.I2(\read_input[31]_i_4_n_0 ),
.I3(\read_input[31]_i_5_n_0 ),
.I4(register_a[21]),
.O(\read_input[21]_i_1_n_0 ));
LUT5 #(
.INIT(32'hFFFB0008))
\read_input[22]_i_1
(.I0(result[22]),
.I1(write_enable_reg_n_0),
.I2(\read_input[31]_i_4_n_0 ),
.I3(\read_input[31]_i_5_n_0 ),
.I4(register_a[22]),
.O(\read_input[22]_i_1_n_0 ));
LUT5 #(
.INIT(32'hFFFB0008))
\read_input[23]_i_1
(.I0(result[23]),
.I1(write_enable_reg_n_0),
.I2(\read_input[31]_i_4_n_0 ),
.I3(\read_input[31]_i_5_n_0 ),
.I4(register_a[23]),
.O(\read_input[23]_i_1_n_0 ));
LUT5 #(
.INIT(32'hFFFB0008))
\read_input[24]_i_1
(.I0(result[24]),
.I1(write_enable_reg_n_0),
.I2(\read_input[31]_i_4_n_0 ),
.I3(\read_input[31]_i_5_n_0 ),
.I4(register_a[24]),
.O(\read_input[24]_i_1_n_0 ));
LUT5 #(
.INIT(32'hFFFB0008))
\read_input[25]_i_1
(.I0(result[25]),
.I1(write_enable_reg_n_0),
.I2(\read_input[31]_i_4_n_0 ),
.I3(\read_input[31]_i_5_n_0 ),
.I4(register_a[25]),
.O(\read_input[25]_i_1_n_0 ));
LUT5 #(
.INIT(32'hFFFB0008))
\read_input[26]_i_1
(.I0(result[26]),
.I1(write_enable_reg_n_0),
.I2(\read_input[31]_i_4_n_0 ),
.I3(\read_input[31]_i_5_n_0 ),
.I4(register_a[26]),
.O(\read_input[26]_i_1_n_0 ));
LUT5 #(
.INIT(32'hFFFB0008))
\read_input[27]_i_1
(.I0(result[27]),
.I1(write_enable_reg_n_0),
.I2(\read_input[31]_i_4_n_0 ),
.I3(\read_input[31]_i_5_n_0 ),
.I4(register_a[27]),
.O(\read_input[27]_i_1_n_0 ));
LUT5 #(
.INIT(32'hFFFB0008))
\read_input[28]_i_1
(.I0(result[28]),
.I1(write_enable_reg_n_0),
.I2(\read_input[31]_i_4_n_0 ),
.I3(\read_input[31]_i_5_n_0 ),
.I4(register_a[28]),
.O(\read_input[28]_i_1_n_0 ));
LUT5 #(
.INIT(32'hFFFB0008))
\read_input[29]_i_1
(.I0(result[29]),
.I1(write_enable_reg_n_0),
.I2(\read_input[31]_i_4_n_0 ),
.I3(\read_input[31]_i_5_n_0 ),
.I4(register_a[29]),
.O(\read_input[29]_i_1_n_0 ));
LUT5 #(
.INIT(32'hFFFB0008))
\read_input[2]_i_1
(.I0(result[2]),
.I1(write_enable_reg_n_0),
.I2(\read_input[31]_i_4_n_0 ),
.I3(\read_input[31]_i_5_n_0 ),
.I4(register_a[2]),
.O(\read_input[2]_i_1_n_0 ));
LUT5 #(
.INIT(32'hFFFB0008))
\read_input[30]_i_1
(.I0(result[30]),
.I1(write_enable_reg_n_0),
.I2(\read_input[31]_i_4_n_0 ),
.I3(\read_input[31]_i_5_n_0 ),
.I4(register_a[30]),
.O(\read_input[30]_i_1_n_0 ));
LUT6 #(
.INIT(64'h0000000000000080))
\read_input[31]_i_1
(.I0(opcode_2[4]),
.I1(opcode_20),
.I2(\state_reg_n_0_[0] ),
.I3(\read_input[31]_i_3_n_0 ),
.I4(opcode_2[2]),
.I5(opcode_2[3]),
.O(\read_input[31]_i_1_n_0 ));
LUT5 #(
.INIT(32'hFFFB0008))
\read_input[31]_i_2
(.I0(result[31]),
.I1(write_enable_reg_n_0),
.I2(\read_input[31]_i_4_n_0 ),
.I3(\read_input[31]_i_5_n_0 ),
.I4(register_a[31]),
.O(\read_input[31]_i_2_n_0 ));
LUT2 #(
.INIT(4'h7))
\read_input[31]_i_3
(.I0(opcode_2[0]),
.I1(opcode_2[1]),
.O(\read_input[31]_i_3_n_0 ));
LUT4 #(
.INIT(16'h6FF6))
\read_input[31]_i_4
(.I0(address_a_2[2]),
.I1(address_z_3[2]),
.I2(address_a_2[1]),
.I3(address_z_3[1]),
.O(\read_input[31]_i_4_n_0 ));
LUT4 #(
.INIT(16'h6FF6))
\read_input[31]_i_5
(.I0(address_a_2[0]),
.I1(address_z_3[0]),
.I2(address_a_2[3]),
.I3(address_z_3[3]),
.O(\read_input[31]_i_5_n_0 ));
LUT5 #(
.INIT(32'hFFFB0008))
\read_input[3]_i_1
(.I0(result[3]),
.I1(write_enable_reg_n_0),
.I2(\read_input[31]_i_4_n_0 ),
.I3(\read_input[31]_i_5_n_0 ),
.I4(register_a[3]),
.O(\read_input[3]_i_1_n_0 ));
LUT5 #(
.INIT(32'hFFFB0008))
\read_input[4]_i_1
(.I0(result[4]),
.I1(write_enable_reg_n_0),
.I2(\read_input[31]_i_4_n_0 ),
.I3(\read_input[31]_i_5_n_0 ),
.I4(register_a[4]),
.O(\read_input[4]_i_1_n_0 ));
LUT5 #(
.INIT(32'hFFFB0008))
\read_input[5]_i_1
(.I0(result[5]),
.I1(write_enable_reg_n_0),
.I2(\read_input[31]_i_4_n_0 ),
.I3(\read_input[31]_i_5_n_0 ),
.I4(register_a[5]),
.O(\read_input[5]_i_1_n_0 ));
LUT5 #(
.INIT(32'hFFFB0008))
\read_input[6]_i_1
(.I0(result[6]),
.I1(write_enable_reg_n_0),
.I2(\read_input[31]_i_4_n_0 ),
.I3(\read_input[31]_i_5_n_0 ),
.I4(register_a[6]),
.O(\read_input[6]_i_1_n_0 ));
LUT5 #(
.INIT(32'hFFFB0008))
\read_input[7]_i_1
(.I0(result[7]),
.I1(write_enable_reg_n_0),
.I2(\read_input[31]_i_4_n_0 ),
.I3(\read_input[31]_i_5_n_0 ),
.I4(register_a[7]),
.O(\read_input[7]_i_1_n_0 ));
LUT5 #(
.INIT(32'hFFFB0008))
\read_input[8]_i_1
(.I0(result[8]),
.I1(write_enable_reg_n_0),
.I2(\read_input[31]_i_4_n_0 ),
.I3(\read_input[31]_i_5_n_0 ),
.I4(register_a[8]),
.O(\read_input[8]_i_1_n_0 ));
LUT5 #(
.INIT(32'hFFFB0008))
\read_input[9]_i_1
(.I0(result[9]),
.I1(write_enable_reg_n_0),
.I2(\read_input[31]_i_4_n_0 ),
.I3(\read_input[31]_i_5_n_0 ),
.I4(register_a[9]),
.O(\read_input[9]_i_1_n_0 ));
FDRE \read_input_reg[0]
(.C(ETH_CLK_OBUF),
.CE(\read_input[31]_i_1_n_0 ),
.D(\read_input[0]_i_1_n_0 ),
.Q(read_input[0]),
.R(1'b0));
FDRE \read_input_reg[10]
(.C(ETH_CLK_OBUF),
.CE(\read_input[31]_i_1_n_0 ),
.D(\read_input[10]_i_1_n_0 ),
.Q(read_input[10]),
.R(1'b0));
FDRE \read_input_reg[11]
(.C(ETH_CLK_OBUF),
.CE(\read_input[31]_i_1_n_0 ),
.D(\read_input[11]_i_1_n_0 ),
.Q(read_input[11]),
.R(1'b0));
FDRE \read_input_reg[12]
(.C(ETH_CLK_OBUF),
.CE(\read_input[31]_i_1_n_0 ),
.D(\read_input[12]_i_1_n_0 ),
.Q(read_input[12]),
.R(1'b0));
FDRE \read_input_reg[13]
(.C(ETH_CLK_OBUF),
.CE(\read_input[31]_i_1_n_0 ),
.D(\read_input[13]_i_1_n_0 ),
.Q(read_input[13]),
.R(1'b0));
FDRE \read_input_reg[14]
(.C(ETH_CLK_OBUF),
.CE(\read_input[31]_i_1_n_0 ),
.D(\read_input[14]_i_1_n_0 ),
.Q(read_input[14]),
.R(1'b0));
FDRE \read_input_reg[15]
(.C(ETH_CLK_OBUF),
.CE(\read_input[31]_i_1_n_0 ),
.D(\read_input[15]_i_1_n_0 ),
.Q(read_input[15]),
.R(1'b0));
FDRE \read_input_reg[16]
(.C(ETH_CLK_OBUF),
.CE(\read_input[31]_i_1_n_0 ),
.D(\read_input[16]_i_1_n_0 ),
.Q(read_input[16]),
.R(1'b0));
FDRE \read_input_reg[17]
(.C(ETH_CLK_OBUF),
.CE(\read_input[31]_i_1_n_0 ),
.D(\read_input[17]_i_1_n_0 ),
.Q(read_input[17]),
.R(1'b0));
FDRE \read_input_reg[18]
(.C(ETH_CLK_OBUF),
.CE(\read_input[31]_i_1_n_0 ),
.D(\read_input[18]_i_1_n_0 ),
.Q(read_input[18]),
.R(1'b0));
FDRE \read_input_reg[19]
(.C(ETH_CLK_OBUF),
.CE(\read_input[31]_i_1_n_0 ),
.D(\read_input[19]_i_1_n_0 ),
.Q(read_input[19]),
.R(1'b0));
FDRE \read_input_reg[1]
(.C(ETH_CLK_OBUF),
.CE(\read_input[31]_i_1_n_0 ),
.D(\read_input[1]_i_1_n_0 ),
.Q(read_input[1]),
.R(1'b0));
FDRE \read_input_reg[20]
(.C(ETH_CLK_OBUF),
.CE(\read_input[31]_i_1_n_0 ),
.D(\read_input[20]_i_1_n_0 ),
.Q(read_input[20]),
.R(1'b0));
FDRE \read_input_reg[21]
(.C(ETH_CLK_OBUF),
.CE(\read_input[31]_i_1_n_0 ),
.D(\read_input[21]_i_1_n_0 ),
.Q(read_input[21]),
.R(1'b0));
FDRE \read_input_reg[22]
(.C(ETH_CLK_OBUF),
.CE(\read_input[31]_i_1_n_0 ),
.D(\read_input[22]_i_1_n_0 ),
.Q(read_input[22]),
.R(1'b0));
FDRE \read_input_reg[23]
(.C(ETH_CLK_OBUF),
.CE(\read_input[31]_i_1_n_0 ),
.D(\read_input[23]_i_1_n_0 ),
.Q(read_input[23]),
.R(1'b0));
FDRE \read_input_reg[24]
(.C(ETH_CLK_OBUF),
.CE(\read_input[31]_i_1_n_0 ),
.D(\read_input[24]_i_1_n_0 ),
.Q(read_input[24]),
.R(1'b0));
FDRE \read_input_reg[25]
(.C(ETH_CLK_OBUF),
.CE(\read_input[31]_i_1_n_0 ),
.D(\read_input[25]_i_1_n_0 ),
.Q(read_input[25]),
.R(1'b0));
FDRE \read_input_reg[26]
(.C(ETH_CLK_OBUF),
.CE(\read_input[31]_i_1_n_0 ),
.D(\read_input[26]_i_1_n_0 ),
.Q(read_input[26]),
.R(1'b0));
FDRE \read_input_reg[27]
(.C(ETH_CLK_OBUF),
.CE(\read_input[31]_i_1_n_0 ),
.D(\read_input[27]_i_1_n_0 ),
.Q(read_input[27]),
.R(1'b0));
FDRE \read_input_reg[28]
(.C(ETH_CLK_OBUF),
.CE(\read_input[31]_i_1_n_0 ),
.D(\read_input[28]_i_1_n_0 ),
.Q(read_input[28]),
.R(1'b0));
FDRE \read_input_reg[29]
(.C(ETH_CLK_OBUF),
.CE(\read_input[31]_i_1_n_0 ),
.D(\read_input[29]_i_1_n_0 ),
.Q(read_input[29]),
.R(1'b0));
FDRE \read_input_reg[2]
(.C(ETH_CLK_OBUF),
.CE(\read_input[31]_i_1_n_0 ),
.D(\read_input[2]_i_1_n_0 ),
.Q(read_input[2]),
.R(1'b0));
FDRE \read_input_reg[30]
(.C(ETH_CLK_OBUF),
.CE(\read_input[31]_i_1_n_0 ),
.D(\read_input[30]_i_1_n_0 ),
.Q(read_input[30]),
.R(1'b0));
FDRE \read_input_reg[31]
(.C(ETH_CLK_OBUF),
.CE(\read_input[31]_i_1_n_0 ),
.D(\read_input[31]_i_2_n_0 ),
.Q(read_input[31]),
.R(1'b0));
FDRE \read_input_reg[3]
(.C(ETH_CLK_OBUF),
.CE(\read_input[31]_i_1_n_0 ),
.D(\read_input[3]_i_1_n_0 ),
.Q(read_input[3]),
.R(1'b0));
FDRE \read_input_reg[4]
(.C(ETH_CLK_OBUF),
.CE(\read_input[31]_i_1_n_0 ),
.D(\read_input[4]_i_1_n_0 ),
.Q(read_input[4]),
.R(1'b0));
FDRE \read_input_reg[5]
(.C(ETH_CLK_OBUF),
.CE(\read_input[31]_i_1_n_0 ),
.D(\read_input[5]_i_1_n_0 ),
.Q(read_input[5]),
.R(1'b0));
FDRE \read_input_reg[6]
(.C(ETH_CLK_OBUF),
.CE(\read_input[31]_i_1_n_0 ),
.D(\read_input[6]_i_1_n_0 ),
.Q(read_input[6]),
.R(1'b0));
FDRE \read_input_reg[7]
(.C(ETH_CLK_OBUF),
.CE(\read_input[31]_i_1_n_0 ),
.D(\read_input[7]_i_1_n_0 ),
.Q(read_input[7]),
.R(1'b0));
FDRE \read_input_reg[8]
(.C(ETH_CLK_OBUF),
.CE(\read_input[31]_i_1_n_0 ),
.D(\read_input[8]_i_1_n_0 ),
.Q(read_input[8]),
.R(1'b0));
FDRE \read_input_reg[9]
(.C(ETH_CLK_OBUF),
.CE(\read_input[31]_i_1_n_0 ),
.D(\read_input[9]_i_1_n_0 ),
.Q(read_input[9]),
.R(1'b0));
(* INIT_A = "64'h0000000000000000" *)
(* INIT_B = "64'h0000000000000000" *)
(* INIT_C = "64'h0000000000000000" *)
(* INIT_D = "64'h0000000000000000" *)
RAM32M_UNIQ_BASE_ registers_reg_r1_0_15_0_5
(.ADDRA({1'b0,address_b_2}),
.ADDRB({1'b0,address_b_2}),
.ADDRC({1'b0,address_b_2}),
.ADDRD({1'b0,address_z_3}),
.DIA(result[1:0]),
.DIB(result[3:2]),
.DIC(result[5:4]),
.DID({1'b0,1'b0}),
.DOA(register_b[1:0]),
.DOB(register_b[3:2]),
.DOC(register_b[5:4]),
.DOD(NLW_registers_reg_r1_0_15_0_5_DOD_UNCONNECTED[1:0]),
.WCLK(ETH_CLK_OBUF),
.WE(write_enable_reg_n_0));
(* INIT_A = "64'h0000000000000000" *)
(* INIT_B = "64'h0000000000000000" *)
(* INIT_C = "64'h0000000000000000" *)
(* INIT_D = "64'h0000000000000000" *)
RAM32M_HD5 registers_reg_r1_0_15_12_17
(.ADDRA({1'b0,address_b_2}),
.ADDRB({1'b0,address_b_2}),
.ADDRC({1'b0,address_b_2}),
.ADDRD({1'b0,address_z_3}),
.DIA(result[13:12]),
.DIB(result[15:14]),
.DIC(result[17:16]),
.DID({1'b0,1'b0}),
.DOA(register_b[13:12]),
.DOB(register_b[15:14]),
.DOC(register_b[17:16]),
.DOD(NLW_registers_reg_r1_0_15_12_17_DOD_UNCONNECTED[1:0]),
.WCLK(ETH_CLK_OBUF),
.WE(write_enable_reg_n_0));
(* INIT_A = "64'h0000000000000000" *)
(* INIT_B = "64'h0000000000000000" *)
(* INIT_C = "64'h0000000000000000" *)
(* INIT_D = "64'h0000000000000000" *)
RAM32M_HD6 registers_reg_r1_0_15_18_23
(.ADDRA({1'b0,address_b_2}),
.ADDRB({1'b0,address_b_2}),
.ADDRC({1'b0,address_b_2}),
.ADDRD({1'b0,address_z_3}),
.DIA(result[19:18]),
.DIB(result[21:20]),
.DIC(result[23:22]),
.DID({1'b0,1'b0}),
.DOA(register_b[19:18]),
.DOB(register_b[21:20]),
.DOC(register_b[23:22]),
.DOD(NLW_registers_reg_r1_0_15_18_23_DOD_UNCONNECTED[1:0]),
.WCLK(ETH_CLK_OBUF),
.WE(write_enable_reg_n_0));
(* INIT_A = "64'h0000000000000000" *)
(* INIT_B = "64'h0000000000000000" *)
(* INIT_C = "64'h0000000000000000" *)
(* INIT_D = "64'h0000000000000000" *)
RAM32M_HD7 registers_reg_r1_0_15_24_29
(.ADDRA({1'b0,address_b_2}),
.ADDRB({1'b0,address_b_2}),
.ADDRC({1'b0,address_b_2}),
.ADDRD({1'b0,address_z_3}),
.DIA(result[25:24]),
.DIB(result[27:26]),
.DIC(result[29:28]),
.DID({1'b0,1'b0}),
.DOA(register_b[25:24]),
.DOB(register_b[27:26]),
.DOC(register_b[29:28]),
.DOD(NLW_registers_reg_r1_0_15_24_29_DOD_UNCONNECTED[1:0]),
.WCLK(ETH_CLK_OBUF),
.WE(write_enable_reg_n_0));
(* INIT_A = "64'h0000000000000000" *)
(* INIT_B = "64'h0000000000000000" *)
(* INIT_C = "64'h0000000000000000" *)
(* INIT_D = "64'h0000000000000000" *)
RAM32M_HD8 registers_reg_r1_0_15_30_31
(.ADDRA({1'b0,address_b_2}),
.ADDRB({1'b0,address_b_2}),
.ADDRC({1'b0,address_b_2}),
.ADDRD({1'b0,address_z_3}),
.DIA(result[31:30]),
.DIB({1'b0,1'b0}),
.DIC({1'b0,1'b0}),
.DID({1'b0,1'b0}),
.DOA(register_b[31:30]),
.DOB(NLW_registers_reg_r1_0_15_30_31_DOB_UNCONNECTED[1:0]),
.DOC(NLW_registers_reg_r1_0_15_30_31_DOC_UNCONNECTED[1:0]),
.DOD(NLW_registers_reg_r1_0_15_30_31_DOD_UNCONNECTED[1:0]),
.WCLK(ETH_CLK_OBUF),
.WE(write_enable_reg_n_0));
(* INIT_A = "64'h0000000000000000" *)
(* INIT_B = "64'h0000000000000000" *)
(* INIT_C = "64'h0000000000000000" *)
(* INIT_D = "64'h0000000000000000" *)
RAM32M_HD4 registers_reg_r1_0_15_6_11
(.ADDRA({1'b0,address_b_2}),
.ADDRB({1'b0,address_b_2}),
.ADDRC({1'b0,address_b_2}),
.ADDRD({1'b0,address_z_3}),
.DIA(result[7:6]),
.DIB(result[9:8]),
.DIC(result[11:10]),
.DID({1'b0,1'b0}),
.DOA(register_b[7:6]),
.DOB(register_b[9:8]),
.DOC(register_b[11:10]),
.DOD(NLW_registers_reg_r1_0_15_6_11_DOD_UNCONNECTED[1:0]),
.WCLK(ETH_CLK_OBUF),
.WE(write_enable_reg_n_0));
(* INIT_A = "64'h0000000000000000" *)
(* INIT_B = "64'h0000000000000000" *)
(* INIT_C = "64'h0000000000000000" *)
(* INIT_D = "64'h0000000000000000" *)
RAM32M_HD9 registers_reg_r2_0_15_0_5
(.ADDRA({1'b0,address_a_2}),
.ADDRB({1'b0,address_a_2}),
.ADDRC({1'b0,address_a_2}),
.ADDRD({1'b0,address_z_3}),
.DIA(result[1:0]),
.DIB(result[3:2]),
.DIC(result[5:4]),
.DID({1'b0,1'b0}),
.DOA(register_a[1:0]),
.DOB(register_a[3:2]),
.DOC(register_a[5:4]),
.DOD(NLW_registers_reg_r2_0_15_0_5_DOD_UNCONNECTED[1:0]),
.WCLK(ETH_CLK_OBUF),
.WE(write_enable_reg_n_0));
(* INIT_A = "64'h0000000000000000" *)
(* INIT_B = "64'h0000000000000000" *)
(* INIT_C = "64'h0000000000000000" *)
(* INIT_D = "64'h0000000000000000" *)
RAM32M_HD11 registers_reg_r2_0_15_12_17
(.ADDRA({1'b0,address_a_2}),
.ADDRB({1'b0,address_a_2}),
.ADDRC({1'b0,address_a_2}),
.ADDRD({1'b0,address_z_3}),
.DIA(result[13:12]),
.DIB(result[15:14]),
.DIC(result[17:16]),
.DID({1'b0,1'b0}),
.DOA(register_a[13:12]),
.DOB(register_a[15:14]),
.DOC(register_a[17:16]),
.DOD(NLW_registers_reg_r2_0_15_12_17_DOD_UNCONNECTED[1:0]),
.WCLK(ETH_CLK_OBUF),
.WE(write_enable_reg_n_0));
(* INIT_A = "64'h0000000000000000" *)
(* INIT_B = "64'h0000000000000000" *)
(* INIT_C = "64'h0000000000000000" *)
(* INIT_D = "64'h0000000000000000" *)
RAM32M_HD12 registers_reg_r2_0_15_18_23
(.ADDRA({1'b0,address_a_2}),
.ADDRB({1'b0,address_a_2}),
.ADDRC({1'b0,address_a_2}),
.ADDRD({1'b0,address_z_3}),
.DIA(result[19:18]),
.DIB(result[21:20]),
.DIC(result[23:22]),
.DID({1'b0,1'b0}),
.DOA(register_a[19:18]),
.DOB(register_a[21:20]),
.DOC(register_a[23:22]),
.DOD(NLW_registers_reg_r2_0_15_18_23_DOD_UNCONNECTED[1:0]),
.WCLK(ETH_CLK_OBUF),
.WE(write_enable_reg_n_0));
(* INIT_A = "64'h0000000000000000" *)
(* INIT_B = "64'h0000000000000000" *)
(* INIT_C = "64'h0000000000000000" *)
(* INIT_D = "64'h0000000000000000" *)
RAM32M_HD13 registers_reg_r2_0_15_24_29
(.ADDRA({1'b0,address_a_2}),
.ADDRB({1'b0,address_a_2}),
.ADDRC({1'b0,address_a_2}),
.ADDRD({1'b0,address_z_3}),
.DIA(result[25:24]),
.DIB(result[27:26]),
.DIC(result[29:28]),
.DID({1'b0,1'b0}),
.DOA(register_a[25:24]),
.DOB(register_a[27:26]),
.DOC(register_a[29:28]),
.DOD(NLW_registers_reg_r2_0_15_24_29_DOD_UNCONNECTED[1:0]),
.WCLK(ETH_CLK_OBUF),
.WE(write_enable_reg_n_0));
(* INIT_A = "64'h0000000000000000" *)
(* INIT_B = "64'h0000000000000000" *)
(* INIT_C = "64'h0000000000000000" *)
(* INIT_D = "64'h0000000000000000" *)
RAM32M_HD14 registers_reg_r2_0_15_30_31
(.ADDRA({1'b0,address_a_2}),
.ADDRB({1'b0,address_a_2}),
.ADDRC({1'b0,address_a_2}),
.ADDRD({1'b0,address_z_3}),
.DIA(result[31:30]),
.DIB({1'b0,1'b0}),
.DIC({1'b0,1'b0}),
.DID({1'b0,1'b0}),
.DOA(register_a[31:30]),
.DOB(NLW_registers_reg_r2_0_15_30_31_DOB_UNCONNECTED[1:0]),
.DOC(NLW_registers_reg_r2_0_15_30_31_DOC_UNCONNECTED[1:0]),
.DOD(NLW_registers_reg_r2_0_15_30_31_DOD_UNCONNECTED[1:0]),
.WCLK(ETH_CLK_OBUF),
.WE(write_enable_reg_n_0));
(* INIT_A = "64'h0000000000000000" *)
(* INIT_B = "64'h0000000000000000" *)
(* INIT_C = "64'h0000000000000000" *)
(* INIT_D = "64'h0000000000000000" *)
RAM32M_HD10 registers_reg_r2_0_15_6_11
(.ADDRA({1'b0,address_a_2}),
.ADDRB({1'b0,address_a_2}),
.ADDRC({1'b0,address_a_2}),
.ADDRD({1'b0,address_z_3}),
.DIA(result[7:6]),
.DIB(result[9:8]),
.DIC(result[11:10]),
.DID({1'b0,1'b0}),
.DOA(register_a[7:6]),
.DOB(register_a[9:8]),
.DOC(register_a[11:10]),
.DOD(NLW_registers_reg_r2_0_15_6_11_DOD_UNCONNECTED[1:0]),
.WCLK(ETH_CLK_OBUF),
.WE(write_enable_reg_n_0));
LUT6 #(
.INIT(64'hFFFFFFFFFF350000))
\result[0]_i_1
(.I0(\result[0]_i_2_n_0 ),
.I1(\result[0]_i_3_n_0 ),
.I2(opcode_2[0]),
.I3(\result[0]_i_4_n_0 ),
.I4(\state_reg_n_0_[0] ),
.I5(\result[0]_i_5_n_0 ),
.O(\result[0]_i_1_n_0 ));
LUT6 #(
.INIT(64'h444444D4D4D444D4))
\result[0]_i_100
(.I0(store_data[7]),
.I1(\read_input[7]_i_1_n_0 ),
.I2(\read_input[6]_i_1_n_0 ),
.I3(register_b[6]),
.I4(operand_b1),
.I5(result[6]),
.O(\result[0]_i_100_n_0 ));
LUT6 #(
.INIT(64'h47004700FF474700))
\result[0]_i_101
(.I0(result[5]),
.I1(operand_b1),
.I2(register_b[5]),
.I3(\read_input[5]_i_1_n_0 ),
.I4(\read_input[4]_i_1_n_0 ),
.I5(store_data[4]),
.O(\result[0]_i_101_n_0 ));
LUT6 #(
.INIT(64'h5404FFFF00005404))
\result[0]_i_102
(.I0(store_data[2]),
.I1(register_a[2]),
.I2(operand_a1),
.I3(result[2]),
.I4(store_data[3]),
.I5(\read_input[3]_i_1_n_0 ),
.O(\result[0]_i_102_n_0 ));
LUT6 #(
.INIT(64'h44444444DDD444D4))
\result[0]_i_103
(.I0(store_data[1]),
.I1(\read_input[1]_i_1_n_0 ),
.I2(register_a[0]),
.I3(operand_a1),
.I4(result[0]),
.I5(store_data[0]),
.O(\result[0]_i_103_n_0 ));
LUT6 #(
.INIT(64'h5454540151510451))
\result[0]_i_104
(.I0(\result[0]_i_115_n_0 ),
.I1(register_a[6]),
.I2(operand_a1),
.I3(register_b[6]),
.I4(operand_b1),
.I5(result[6]),
.O(\result[0]_i_104_n_0 ));
LUT6 #(
.INIT(64'h9099900009000999))
\result[0]_i_105
(.I0(store_data[4]),
.I1(\read_input[4]_i_1_n_0 ),
.I2(result[5]),
.I3(operand_b1),
.I4(register_b[5]),
.I5(\read_input[5]_i_1_n_0 ),
.O(\result[0]_i_105_n_0 ));
LUT6 #(
.INIT(64'hE21D00000000E21D))
\result[0]_i_106
(.I0(register_a[3]),
.I1(operand_a1),
.I2(result[3]),
.I3(store_data[3]),
.I4(\read_input[2]_i_1_n_0 ),
.I5(store_data[2]),
.O(\result[0]_i_106_n_0 ));
LUT6 #(
.INIT(64'hE21D00000000E21D))
\result[0]_i_107
(.I0(register_a[1]),
.I1(operand_a1),
.I2(result[1]),
.I3(store_data[1]),
.I4(\read_input[0]_i_1_n_0 ),
.I5(store_data[0]),
.O(\result[0]_i_107_n_0 ));
LUT5 #(
.INIT(32'h124712B8))
\result[0]_i_108
(.I0(result[11]),
.I1(operand_b1),
.I2(register_b[11]),
.I3(operand_a1),
.I4(register_a[11]),
.O(\result[0]_i_108_n_0 ));
LUT5 #(
.INIT(32'h124712B8))
\result[0]_i_109
(.I0(result[8]),
.I1(operand_b1),
.I2(register_b[8]),
.I3(operand_a1),
.I4(register_a[8]),
.O(\result[0]_i_109_n_0 ));
LUT6 #(
.INIT(64'h4555454545555555))
\result[0]_i_11
(.I0(opcode_2[1]),
.I1(opcode_2[4]),
.I2(opcode_2[0]),
.I3(\read_input[0]_i_1_n_0 ),
.I4(opcode_2[2]),
.I5(\result_reg[1]_i_6_n_7 ),
.O(\result[0]_i_11_n_0 ));
LUT6 #(
.INIT(64'h5454540151510451))
\result[0]_i_110
(.I0(\result[0]_i_115_n_0 ),
.I1(register_a[6]),
.I2(operand_a1),
.I3(register_b[6]),
.I4(operand_b1),
.I5(result[6]),
.O(\result[0]_i_110_n_0 ));
LUT6 #(
.INIT(64'h9099900009000999))
\result[0]_i_111
(.I0(store_data[4]),
.I1(\read_input[4]_i_1_n_0 ),
.I2(result[5]),
.I3(operand_b1),
.I4(register_b[5]),
.I5(\read_input[5]_i_1_n_0 ),
.O(\result[0]_i_111_n_0 ));
LUT6 #(
.INIT(64'hE21D00000000E21D))
\result[0]_i_112
(.I0(register_a[3]),
.I1(operand_a1),
.I2(result[3]),
.I3(store_data[3]),
.I4(\read_input[2]_i_1_n_0 ),
.I5(store_data[2]),
.O(\result[0]_i_112_n_0 ));
LUT6 #(
.INIT(64'hE21D00000000E21D))
\result[0]_i_113
(.I0(register_a[1]),
.I1(operand_a1),
.I2(result[1]),
.I3(store_data[1]),
.I4(\read_input[0]_i_1_n_0 ),
.I5(store_data[0]),
.O(\result[0]_i_113_n_0 ));
LUT6 #(
.INIT(64'h5454540151510451))
\result[0]_i_114
(.I0(\result[0]_i_108_n_0 ),
.I1(register_a[10]),
.I2(operand_a1),
.I3(register_b[10]),
.I4(operand_b1),
.I5(result[10]),
.O(\result[0]_i_114_n_0 ));
LUT5 #(
.INIT(32'h124712B8))
\result[0]_i_115
(.I0(result[7]),
.I1(operand_b1),
.I2(register_b[7]),
.I3(operand_a1),
.I4(register_a[7]),
.O(\result[0]_i_115_n_0 ));
LUT5 #(
.INIT(32'h124712B8))
\result[0]_i_116
(.I0(result[5]),
.I1(operand_b1),
.I2(register_b[5]),
.I3(operand_a1),
.I4(register_a[5]),
.O(\result[0]_i_116_n_0 ));
LUT6 #(
.INIT(64'h5454540151510451))
\result[0]_i_117
(.I0(\result[0]_i_115_n_0 ),
.I1(register_a[6]),
.I2(operand_a1),
.I3(register_b[6]),
.I4(operand_b1),
.I5(result[6]),
.O(\result[0]_i_117_n_0 ));
LUT6 #(
.INIT(64'h9099900009000999))
\result[0]_i_118
(.I0(store_data[4]),
.I1(\read_input[4]_i_1_n_0 ),
.I2(result[5]),
.I3(operand_b1),
.I4(register_b[5]),
.I5(\read_input[5]_i_1_n_0 ),
.O(\result[0]_i_118_n_0 ));
LUT6 #(
.INIT(64'hE21D00000000E21D))
\result[0]_i_119
(.I0(register_a[3]),
.I1(operand_a1),
.I2(result[3]),
.I3(store_data[3]),
.I4(\read_input[2]_i_1_n_0 ),
.I5(store_data[2]),
.O(\result[0]_i_119_n_0 ));
LUT6 #(
.INIT(64'hE21D00000000E21D))
\result[0]_i_120
(.I0(register_a[1]),
.I1(operand_a1),
.I2(result[1]),
.I3(store_data[1]),
.I4(\read_input[0]_i_1_n_0 ),
.I5(store_data[0]),
.O(\result[0]_i_120_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFF02470200))
\result[0]_i_15
(.I0(result[31]),
.I1(operand_b1),
.I2(register_b[31]),
.I3(operand_a1),
.I4(register_a[31]),
.I5(\result[0]_i_47_n_0 ),
.O(\result[0]_i_15_n_0 ));
LUT6 #(
.INIT(64'h02A202A2ABFB02A2))
\result[0]_i_16
(.I0(\read_input[29]_i_1_n_0 ),
.I1(register_b[29]),
.I2(operand_b1),
.I3(result[29]),
.I4(\read_input[28]_i_1_n_0 ),
.I5(store_data[28]),
.O(\result[0]_i_16_n_0 ));
LUT6 #(
.INIT(64'h02A202A2ABFB02A2))
\result[0]_i_17
(.I0(\read_input[27]_i_1_n_0 ),
.I1(register_b[27]),
.I2(operand_b1),
.I3(result[27]),
.I4(\read_input[26]_i_1_n_0 ),
.I5(store_data[26]),
.O(\result[0]_i_17_n_0 ));
LUT6 #(
.INIT(64'h22222222BBB222B2))
\result[0]_i_18
(.I0(\read_input[25]_i_1_n_0 ),
.I1(store_data[25]),
.I2(register_a[24]),
.I3(operand_a1),
.I4(result[24]),
.I5(store_data[24]),
.O(\result[0]_i_18_n_0 ));
LUT6 #(
.INIT(64'h5451454054511015))
\result[0]_i_19
(.I0(\result[0]_i_48_n_0 ),
.I1(result[30]),
.I2(operand_b1),
.I3(register_b[30]),
.I4(operand_a1),
.I5(register_a[30]),
.O(\result[0]_i_19_n_0 ));
LUT6 #(
.INIT(64'h7C7F7C7C7C7F7F7F))
\result[0]_i_2
(.I0(\result[0]_i_6_n_0 ),
.I1(opcode_2[2]),
.I2(opcode_2[3]),
.I3(data10),
.I4(opcode_2[4]),
.I5(address_b_2[0]),
.O(\result[0]_i_2_n_0 ));
LUT6 #(
.INIT(64'h5451454054511015))
\result[0]_i_20
(.I0(\result[0]_i_49_n_0 ),
.I1(result[28]),
.I2(operand_b1),
.I3(register_b[28]),
.I4(operand_a1),
.I5(register_a[28]),
.O(\result[0]_i_20_n_0 ));
LUT6 #(
.INIT(64'h5451454054511015))
\result[0]_i_21
(.I0(\result[0]_i_50_n_0 ),
.I1(result[26]),
.I2(operand_b1),
.I3(register_b[26]),
.I4(operand_a1),
.I5(register_a[26]),
.O(\result[0]_i_21_n_0 ));
LUT6 #(
.INIT(64'h00000000EDB8ED47))
\result[0]_i_22
(.I0(result[24]),
.I1(operand_b1),
.I2(register_b[24]),
.I3(operand_a1),
.I4(register_a[24]),
.I5(\result[0]_i_51_n_0 ),
.O(\result[0]_i_22_n_0 ));
LUT6 #(
.INIT(64'hAAAEBABFAAAEAAAA))
\result[0]_i_24
(.I0(\result[0]_i_47_n_0 ),
.I1(result[31]),
.I2(operand_a1),
.I3(register_a[31]),
.I4(operand_b1),
.I5(register_b[31]),
.O(\result[0]_i_24_n_0 ));
LUT6 #(
.INIT(64'h5451454054511015))
\result[0]_i_25
(.I0(\result[0]_i_48_n_0 ),
.I1(result[30]),
.I2(operand_b1),
.I3(register_b[30]),
.I4(operand_a1),
.I5(register_a[30]),
.O(\result[0]_i_25_n_0 ));
LUT6 #(
.INIT(64'h5451454054511015))
\result[0]_i_26
(.I0(\result[0]_i_49_n_0 ),
.I1(result[28]),
.I2(operand_b1),
.I3(register_b[28]),
.I4(operand_a1),
.I5(register_a[28]),
.O(\result[0]_i_26_n_0 ));
LUT6 #(
.INIT(64'h5451454054511015))
\result[0]_i_27
(.I0(\result[0]_i_50_n_0 ),
.I1(result[26]),
.I2(operand_b1),
.I3(register_b[26]),
.I4(operand_a1),
.I5(register_a[26]),
.O(\result[0]_i_27_n_0 ));
LUT6 #(
.INIT(64'h00000000EDB8ED47))
\result[0]_i_28
(.I0(result[24]),
.I1(operand_b1),
.I2(register_b[24]),
.I3(operand_a1),
.I4(register_a[24]),
.I5(\result[0]_i_51_n_0 ),
.O(\result[0]_i_28_n_0 ));
LUT6 #(
.INIT(64'h777F777F777F7700))
\result[0]_i_3
(.I0(opcode_2[2]),
.I1(opcode_2[1]),
.I2(\read_input[0]_i_1_n_0 ),
.I3(store_data[0]),
.I4(\result[0]_i_8_n_0 ),
.I5(\result[27]_i_8_n_0 ),
.O(\result[0]_i_3_n_0 ));
LUT6 #(
.INIT(64'h5451454054511015))
\result[0]_i_30
(.I0(\result[0]_i_48_n_0 ),
.I1(result[30]),
.I2(operand_b1),
.I3(register_b[30]),
.I4(operand_a1),
.I5(register_a[30]),
.O(\result[0]_i_30_n_0 ));
LUT6 #(
.INIT(64'hA8A28A80A8A2202A))
\result[0]_i_31
(.I0(\result[0]_i_62_n_0 ),
.I1(result[27]),
.I2(operand_b1),
.I3(register_b[27]),
.I4(operand_a1),
.I5(register_a[27]),
.O(\result[0]_i_31_n_0 ));
LUT6 #(
.INIT(64'hA8A28A80A8A2202A))
\result[0]_i_32
(.I0(\result[0]_i_63_n_0 ),
.I1(result[26]),
.I2(operand_b1),
.I3(register_b[26]),
.I4(operand_a1),
.I5(register_a[26]),
.O(\result[0]_i_32_n_0 ));
LUT6 #(
.INIT(64'h5451454054511015))
\result[0]_i_34
(.I0(\result[0]_i_48_n_0 ),
.I1(result[30]),
.I2(operand_b1),
.I3(register_b[30]),
.I4(operand_a1),
.I5(register_a[30]),
.O(\result[0]_i_34_n_0 ));
LUT6 #(
.INIT(64'h5451454054511015))
\result[0]_i_35
(.I0(\result[0]_i_49_n_0 ),
.I1(result[28]),
.I2(operand_b1),
.I3(register_b[28]),
.I4(operand_a1),
.I5(register_a[28]),
.O(\result[0]_i_35_n_0 ));
LUT6 #(
.INIT(64'h5451454054511015))
\result[0]_i_36
(.I0(\result[0]_i_50_n_0 ),
.I1(result[26]),
.I2(operand_b1),
.I3(register_b[26]),
.I4(operand_a1),
.I5(register_a[26]),
.O(\result[0]_i_36_n_0 ));
LUT6 #(
.INIT(64'h00000000EDB8ED47))
\result[0]_i_37
(.I0(result[24]),
.I1(operand_b1),
.I2(register_b[24]),
.I3(operand_a1),
.I4(register_a[24]),
.I5(\result[0]_i_51_n_0 ),
.O(\result[0]_i_37_n_0 ));
LUT6 #(
.INIT(64'h222222B2B2B222B2))
\result[0]_i_39
(.I0(\read_input[23]_i_1_n_0 ),
.I1(store_data[23]),
.I2(\read_input[22]_i_1_n_0 ),
.I3(register_b[22]),
.I4(operand_b1),
.I5(result[22]),
.O(\result[0]_i_39_n_0 ));
LUT6 #(
.INIT(64'h0A80AAAA0080AAAA))
\result[0]_i_4
(.I0(\result[0]_i_9_n_0 ),
.I1(data12),
.I2(opcode_2[2]),
.I3(opcode_2[3]),
.I4(\result[0]_i_11_n_0 ),
.I5(data4),
.O(\result[0]_i_4_n_0 ));
LUT6 #(
.INIT(64'h222222B2B2B222B2))
\result[0]_i_40
(.I0(\read_input[21]_i_1_n_0 ),
.I1(store_data[21]),
.I2(\read_input[20]_i_1_n_0 ),
.I3(register_b[20]),
.I4(operand_b1),
.I5(result[20]),
.O(\result[0]_i_40_n_0 ));
LUT6 #(
.INIT(64'h222222B2B2B222B2))
\result[0]_i_41
(.I0(\read_input[19]_i_1_n_0 ),
.I1(store_data[19]),
.I2(\read_input[18]_i_1_n_0 ),
.I3(register_b[18]),
.I4(operand_b1),
.I5(result[18]),
.O(\result[0]_i_41_n_0 ));
LUT6 #(
.INIT(64'h222222B2B2B222B2))
\result[0]_i_42
(.I0(\read_input[17]_i_1_n_0 ),
.I1(store_data[17]),
.I2(\read_input[16]_i_1_n_0 ),
.I3(register_b[16]),
.I4(operand_b1),
.I5(result[16]),
.O(\result[0]_i_42_n_0 ));
LUT6 #(
.INIT(64'h5451454054511015))
\result[0]_i_43
(.I0(\result[0]_i_78_n_0 ),
.I1(result[22]),
.I2(operand_b1),
.I3(register_b[22]),
.I4(operand_a1),
.I5(register_a[22]),
.O(\result[0]_i_43_n_0 ));
LUT6 #(
.INIT(64'h00000000EDB8ED47))
\result[0]_i_44
(.I0(result[21]),
.I1(operand_b1),
.I2(register_b[21]),
.I3(operand_a1),
.I4(register_a[21]),
.I5(\result[0]_i_79_n_0 ),
.O(\result[0]_i_44_n_0 ));
LUT6 #(
.INIT(64'h5451454054511015))
\result[0]_i_45
(.I0(\result[0]_i_80_n_0 ),
.I1(result[18]),
.I2(operand_b1),
.I3(register_b[18]),
.I4(operand_a1),
.I5(register_a[18]),
.O(\result[0]_i_45_n_0 ));
LUT6 #(
.INIT(64'h5451454054511015))
\result[0]_i_46
(.I0(\result[0]_i_81_n_0 ),
.I1(result[16]),
.I2(operand_b1),
.I3(register_b[16]),
.I4(operand_a1),
.I5(register_a[16]),
.O(\result[0]_i_46_n_0 ));
LUT6 #(
.INIT(64'h0000000002470200))
\result[0]_i_47
(.I0(result[30]),
.I1(operand_b1),
.I2(register_b[30]),
.I3(operand_a1),
.I4(register_a[30]),
.I5(\result[0]_i_48_n_0 ),
.O(\result[0]_i_47_n_0 ));
LUT5 #(
.INIT(32'h111E22D2))
\result[0]_i_48
(.I0(register_a[31]),
.I1(operand_a1),
.I2(register_b[31]),
.I3(operand_b1),
.I4(result[31]),
.O(\result[0]_i_48_n_0 ));
LUT5 #(
.INIT(32'h111E22D2))
\result[0]_i_49
(.I0(register_a[29]),
.I1(operand_a1),
.I2(register_b[29]),
.I3(operand_b1),
.I4(result[29]),
.O(\result[0]_i_49_n_0 ));
LUT4 #(
.INIT(16'hE200))
\result[0]_i_5
(.I0(load_data[0]),
.I1(\state_reg_n_0_[1] ),
.I2(OUT1[0]),
.I3(\state_reg_n_0_[2] ),
.O(\result[0]_i_5_n_0 ));
LUT5 #(
.INIT(32'h111E22D2))
\result[0]_i_50
(.I0(register_a[27]),
.I1(operand_a1),
.I2(register_b[27]),
.I3(operand_b1),
.I4(result[27]),
.O(\result[0]_i_50_n_0 ));
LUT5 #(
.INIT(32'h111E22D2))
\result[0]_i_51
(.I0(register_a[25]),
.I1(operand_a1),
.I2(register_b[25]),
.I3(operand_b1),
.I4(result[25]),
.O(\result[0]_i_51_n_0 ));
LUT6 #(
.INIT(64'h5451454054511015))
\result[0]_i_53
(.I0(\result[0]_i_78_n_0 ),
.I1(result[22]),
.I2(operand_b1),
.I3(register_b[22]),
.I4(operand_a1),
.I5(register_a[22]),
.O(\result[0]_i_53_n_0 ));
LUT6 #(
.INIT(64'h00000000EDB8ED47))
\result[0]_i_54
(.I0(result[21]),
.I1(operand_b1),
.I2(register_b[21]),
.I3(operand_a1),
.I4(register_a[21]),
.I5(\result[0]_i_79_n_0 ),
.O(\result[0]_i_54_n_0 ));
LUT6 #(
.INIT(64'h5451454054511015))
\result[0]_i_55
(.I0(\result[0]_i_80_n_0 ),
.I1(result[18]),
.I2(operand_b1),
.I3(register_b[18]),
.I4(operand_a1),
.I5(register_a[18]),
.O(\result[0]_i_55_n_0 ));
LUT6 #(
.INIT(64'h5451454054511015))
\result[0]_i_56
(.I0(\result[0]_i_81_n_0 ),
.I1(result[16]),
.I2(operand_b1),
.I3(register_b[16]),
.I4(operand_a1),
.I5(register_a[16]),
.O(\result[0]_i_56_n_0 ));
LUT6 #(
.INIT(64'hEEE1DD2D00000000))
\result[0]_i_58
(.I0(register_a[21]),
.I1(operand_a1),
.I2(register_b[21]),
.I3(operand_b1),
.I4(result[21]),
.I5(\result[0]_i_91_n_0 ),
.O(\result[0]_i_58_n_0 ));
LUT6 #(
.INIT(64'h000000000000A959))
\result[0]_i_59
(.I0(\read_input[18]_i_1_n_0 ),
.I1(register_b[18]),
.I2(operand_b1),
.I3(result[18]),
.I4(\result[0]_i_80_n_0 ),
.I5(\result[0]_i_79_n_0 ),
.O(\result[0]_i_59_n_0 ));
LUT6 #(
.INIT(64'hE200FFFFE2000000))
\result[0]_i_6
(.I0(register_a[0]),
.I1(operand_a1),
.I2(result[0]),
.I3(store_data[0]),
.I4(opcode_2[1]),
.I5(data6),
.O(\result[0]_i_6_n_0 ));
LUT6 #(
.INIT(64'hEDB8ED4700000000))
\result[0]_i_60
(.I0(result[15]),
.I1(operand_b1),
.I2(register_b[15]),
.I3(operand_a1),
.I4(register_a[15]),
.I5(\result[0]_i_92_n_0 ),
.O(\result[0]_i_60_n_0 ));
LUT6 #(
.INIT(64'h000000000000B847))
\result[0]_i_61
(.I0(result[12]),
.I1(operand_b1),
.I2(register_b[12]),
.I3(\read_input[12]_i_1_n_0 ),
.I4(\result[0]_i_93_n_0 ),
.I5(\result[0]_i_94_n_0 ),
.O(\result[0]_i_61_n_0 ));
LUT6 #(
.INIT(64'h5451454054511015))
\result[0]_i_62
(.I0(\result[0]_i_49_n_0 ),
.I1(result[28]),
.I2(operand_b1),
.I3(register_b[28]),
.I4(operand_a1),
.I5(register_a[28]),
.O(\result[0]_i_62_n_0 ));
LUT6 #(
.INIT(64'h00000000EDB8ED47))
\result[0]_i_63
(.I0(result[24]),
.I1(operand_b1),
.I2(register_b[24]),
.I3(operand_a1),
.I4(register_a[24]),
.I5(\result[0]_i_51_n_0 ),
.O(\result[0]_i_63_n_0 ));
LUT6 #(
.INIT(64'h5451454054511015))
\result[0]_i_65
(.I0(\result[0]_i_78_n_0 ),
.I1(result[22]),
.I2(operand_b1),
.I3(register_b[22]),
.I4(operand_a1),
.I5(register_a[22]),
.O(\result[0]_i_65_n_0 ));
LUT6 #(
.INIT(64'h00000000EDB8ED47))
\result[0]_i_66
(.I0(result[21]),
.I1(operand_b1),
.I2(register_b[21]),
.I3(operand_a1),
.I4(register_a[21]),
.I5(\result[0]_i_79_n_0 ),
.O(\result[0]_i_66_n_0 ));
LUT6 #(
.INIT(64'h5451454054511015))
\result[0]_i_67
(.I0(\result[0]_i_80_n_0 ),
.I1(result[18]),
.I2(operand_b1),
.I3(register_b[18]),
.I4(operand_a1),
.I5(register_a[18]),
.O(\result[0]_i_67_n_0 ));
LUT6 #(
.INIT(64'h5451454054511015))
\result[0]_i_68
(.I0(\result[0]_i_81_n_0 ),
.I1(result[16]),
.I2(operand_b1),
.I3(register_b[16]),
.I4(operand_a1),
.I5(register_a[16]),
.O(\result[0]_i_68_n_0 ));
LUT6 #(
.INIT(64'h444444D4D4D444D4))
\result[0]_i_70
(.I0(store_data[15]),
.I1(\read_input[15]_i_1_n_0 ),
.I2(\read_input[14]_i_1_n_0 ),
.I3(register_b[14]),
.I4(operand_b1),
.I5(result[14]),
.O(\result[0]_i_70_n_0 ));
LUT6 #(
.INIT(64'h444444D4D4D444D4))
\result[0]_i_71
(.I0(store_data[13]),
.I1(\read_input[13]_i_1_n_0 ),
.I2(\read_input[12]_i_1_n_0 ),
.I3(register_b[12]),
.I4(operand_b1),
.I5(result[12]),
.O(\result[0]_i_71_n_0 ));
LUT6 #(
.INIT(64'h444444D4D4D444D4))
\result[0]_i_72
(.I0(store_data[11]),
.I1(\read_input[11]_i_1_n_0 ),
.I2(\read_input[10]_i_1_n_0 ),
.I3(register_b[10]),
.I4(operand_b1),
.I5(result[10]),
.O(\result[0]_i_72_n_0 ));
LUT6 #(
.INIT(64'h444444D4D4D444D4))
\result[0]_i_73
(.I0(store_data[9]),
.I1(\read_input[9]_i_1_n_0 ),
.I2(\read_input[8]_i_1_n_0 ),
.I3(register_b[8]),
.I4(operand_b1),
.I5(result[8]),
.O(\result[0]_i_73_n_0 ));
LUT6 #(
.INIT(64'h00000000EEE1DD2D))
\result[0]_i_74
(.I0(register_a[15]),
.I1(operand_a1),
.I2(register_b[15]),
.I3(operand_b1),
.I4(result[15]),
.I5(\result[0]_i_94_n_0 ),
.O(\result[0]_i_74_n_0 ));
LUT6 #(
.INIT(64'h5454540151510451))
\result[0]_i_75
(.I0(\result[0]_i_93_n_0 ),
.I1(register_a[12]),
.I2(operand_a1),
.I3(register_b[12]),
.I4(operand_b1),
.I5(result[12]),
.O(\result[0]_i_75_n_0 ));
LUT6 #(
.INIT(64'h5454540151510451))
\result[0]_i_76
(.I0(\result[0]_i_108_n_0 ),
.I1(register_a[10]),
.I2(operand_a1),
.I3(register_b[10]),
.I4(operand_b1),
.I5(result[10]),
.O(\result[0]_i_76_n_0 ));
LUT6 #(
.INIT(64'h00000000EEE1DD2D))
\result[0]_i_77
(.I0(register_a[9]),
.I1(operand_a1),
.I2(register_b[9]),
.I3(operand_b1),
.I4(result[9]),
.I5(\result[0]_i_109_n_0 ),
.O(\result[0]_i_77_n_0 ));
LUT5 #(
.INIT(32'h111E22D2))
\result[0]_i_78
(.I0(register_a[23]),
.I1(operand_a1),
.I2(register_b[23]),
.I3(operand_b1),
.I4(result[23]),
.O(\result[0]_i_78_n_0 ));
LUT5 #(
.INIT(32'h111E22D2))
\result[0]_i_79
(.I0(register_a[20]),
.I1(operand_a1),
.I2(register_b[20]),
.I3(operand_b1),
.I4(result[20]),
.O(\result[0]_i_79_n_0 ));
LUT5 #(
.INIT(32'hFFFFFEFF))
\result[0]_i_8
(.I0(store_data[1]),
.I1(store_data[2]),
.I2(store_data[3]),
.I3(\read_input[0]_i_1_n_0 ),
.I4(store_data[4]),
.O(\result[0]_i_8_n_0 ));
LUT5 #(
.INIT(32'h111E22D2))
\result[0]_i_80
(.I0(register_a[19]),
.I1(operand_a1),
.I2(register_b[19]),
.I3(operand_b1),
.I4(result[19]),
.O(\result[0]_i_80_n_0 ));
LUT5 #(
.INIT(32'h111E22D2))
\result[0]_i_81
(.I0(register_a[17]),
.I1(operand_a1),
.I2(register_b[17]),
.I3(operand_b1),
.I4(result[17]),
.O(\result[0]_i_81_n_0 ));
LUT6 #(
.INIT(64'h00000000EEE1DD2D))
\result[0]_i_83
(.I0(register_a[15]),
.I1(operand_a1),
.I2(register_b[15]),
.I3(operand_b1),
.I4(result[15]),
.I5(\result[0]_i_94_n_0 ),
.O(\result[0]_i_83_n_0 ));
LUT6 #(
.INIT(64'h5454540151510451))
\result[0]_i_84
(.I0(\result[0]_i_93_n_0 ),
.I1(register_a[12]),
.I2(operand_a1),
.I3(register_b[12]),
.I4(operand_b1),
.I5(result[12]),
.O(\result[0]_i_84_n_0 ));
LUT6 #(
.INIT(64'h5454540151510451))
\result[0]_i_85
(.I0(\result[0]_i_108_n_0 ),
.I1(register_a[10]),
.I2(operand_a1),
.I3(register_b[10]),
.I4(operand_b1),
.I5(result[10]),
.O(\result[0]_i_85_n_0 ));
LUT6 #(
.INIT(64'h00000000EEE1DD2D))
\result[0]_i_86
(.I0(register_a[9]),
.I1(operand_a1),
.I2(register_b[9]),
.I3(operand_b1),
.I4(result[9]),
.I5(\result[0]_i_109_n_0 ),
.O(\result[0]_i_86_n_0 ));
LUT6 #(
.INIT(64'hEDB8ED4700000000))
\result[0]_i_87
(.I0(result[9]),
.I1(operand_b1),
.I2(register_b[9]),
.I3(operand_a1),
.I4(register_a[9]),
.I5(\result[0]_i_114_n_0 ),
.O(\result[0]_i_87_n_0 ));
LUT6 #(
.INIT(64'h000000000000B847))
\result[0]_i_88
(.I0(result[6]),
.I1(operand_b1),
.I2(register_b[6]),
.I3(\read_input[6]_i_1_n_0 ),
.I4(\result[0]_i_115_n_0 ),
.I5(\result[0]_i_109_n_0 ),
.O(\result[0]_i_88_n_0 ));
LUT5 #(
.INIT(32'h00009009))
\result[0]_i_89
(.I0(store_data[3]),
.I1(\read_input[3]_i_1_n_0 ),
.I2(store_data[4]),
.I3(\read_input[4]_i_1_n_0 ),
.I4(\result[0]_i_116_n_0 ),
.O(\result[0]_i_89_n_0 ));
LUT6 #(
.INIT(64'h55FFDD5F5555DD5F))
\result[0]_i_9
(.I0(opcode_2[1]),
.I1(data5[0]),
.I2(program_counter_2[0]),
.I3(opcode_2[3]),
.I4(opcode_2[2]),
.I5(\result_reg[3]_i_9_n_7 ),
.O(\result[0]_i_9_n_0 ));
LUT6 #(
.INIT(64'h9009000000009009))
\result[0]_i_90
(.I0(store_data[0]),
.I1(\read_input[0]_i_1_n_0 ),
.I2(store_data[1]),
.I3(\read_input[1]_i_1_n_0 ),
.I4(store_data[2]),
.I5(\read_input[2]_i_1_n_0 ),
.O(\result[0]_i_90_n_0 ));
LUT6 #(
.INIT(64'h5451454054511015))
\result[0]_i_91
(.I0(\result[0]_i_78_n_0 ),
.I1(result[22]),
.I2(operand_b1),
.I3(register_b[22]),
.I4(operand_a1),
.I5(register_a[22]),
.O(\result[0]_i_91_n_0 ));
LUT6 #(
.INIT(64'h5451454054511015))
\result[0]_i_92
(.I0(\result[0]_i_81_n_0 ),
.I1(result[16]),
.I2(operand_b1),
.I3(register_b[16]),
.I4(operand_a1),
.I5(register_a[16]),
.O(\result[0]_i_92_n_0 ));
LUT5 #(
.INIT(32'h124712B8))
\result[0]_i_93
(.I0(result[13]),
.I1(operand_b1),
.I2(register_b[13]),
.I3(operand_a1),
.I4(register_a[13]),
.O(\result[0]_i_93_n_0 ));
LUT5 #(
.INIT(32'h124712B8))
\result[0]_i_94
(.I0(result[14]),
.I1(operand_b1),
.I2(register_b[14]),
.I3(operand_a1),
.I4(register_a[14]),
.O(\result[0]_i_94_n_0 ));
LUT6 #(
.INIT(64'h00000000EEE1DD2D))
\result[0]_i_96
(.I0(register_a[15]),
.I1(operand_a1),
.I2(register_b[15]),
.I3(operand_b1),
.I4(result[15]),
.I5(\result[0]_i_94_n_0 ),
.O(\result[0]_i_96_n_0 ));
LUT6 #(
.INIT(64'h5454540151510451))
\result[0]_i_97
(.I0(\result[0]_i_93_n_0 ),
.I1(register_a[12]),
.I2(operand_a1),
.I3(register_b[12]),
.I4(operand_b1),
.I5(result[12]),
.O(\result[0]_i_97_n_0 ));
LUT6 #(
.INIT(64'h5454540151510451))
\result[0]_i_98
(.I0(\result[0]_i_108_n_0 ),
.I1(register_a[10]),
.I2(operand_a1),
.I3(register_b[10]),
.I4(operand_b1),
.I5(result[10]),
.O(\result[0]_i_98_n_0 ));
LUT6 #(
.INIT(64'h00000000EEE1DD2D))
\result[0]_i_99
(.I0(register_a[9]),
.I1(operand_a1),
.I2(register_b[9]),
.I3(operand_b1),
.I4(result[9]),
.I5(\result[0]_i_109_n_0 ),
.O(\result[0]_i_99_n_0 ));
LUT6 #(
.INIT(64'hFFFF20FF20202020))
\result[10]_i_1
(.I0(\state_reg_n_0_[2] ),
.I1(\state_reg_n_0_[1] ),
.I2(load_data[10]),
.I3(\result[10]_i_2_n_0 ),
.I4(\result[10]_i_3_n_0 ),
.I5(\state_reg_n_0_[0] ),
.O(\result[10]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFF470000FFFFFFFF))
\result[10]_i_2
(.I0(\result[10]_i_4_n_0 ),
.I1(store_data[0]),
.I2(\result[11]_i_4_n_0 ),
.I3(\result[27]_i_8_n_0 ),
.I4(\result[10]_i_5_n_0 ),
.I5(opcode_2[0]),
.O(\result[10]_i_2_n_0 ));
LUT6 #(
.INIT(64'hAEAEAEAEFFAEAEAE))
\result[10]_i_3
(.I0(\result[10]_i_6_n_0 ),
.I1(data7[26]),
.I2(\result[14]_i_7_n_0 ),
.I3(store_data[10]),
.I4(\read_input[10]_i_1_n_0 ),
.I5(\result[31]_i_12_n_0 ),
.O(\result[10]_i_3_n_0 ));
LUT3 #(
.INIT(8'hB8))
\result[10]_i_4
(.I0(\result[10]_i_7_n_0 ),
.I1(store_data[1]),
.I2(\result[12]_i_7_n_0 ),
.O(\result[10]_i_4_n_0 ));
LUT6 #(
.INIT(64'h3030FCFF7777FCFF))
\result[10]_i_5
(.I0(store_data[10]),
.I1(opcode_2[1]),
.I2(opcode_2[4]),
.I3(\result_reg[11]_i_8_n_5 ),
.I4(opcode_2[2]),
.I5(\read_input[10]_i_1_n_0 ),
.O(\result[10]_i_5_n_0 ));
LUT6 #(
.INIT(64'h33E200E200000000))
\result[10]_i_6
(.I0(data2[10]),
.I1(opcode_2[3]),
.I2(data5[10]),
.I3(opcode_2[2]),
.I4(\result_reg[15]_i_16_n_5 ),
.I5(opcode_2[1]),
.O(\result[10]_i_6_n_0 ));
LUT5 #(
.INIT(32'h00000B08))
\result[10]_i_7
(.I0(\read_input[3]_i_1_n_0 ),
.I1(store_data[2]),
.I2(store_data[4]),
.I3(\read_input[7]_i_1_n_0 ),
.I4(store_data[3]),
.O(\result[10]_i_7_n_0 ));
LUT6 #(
.INIT(64'hFFFF20FF20202020))
\result[11]_i_1
(.I0(\state_reg_n_0_[2] ),
.I1(\state_reg_n_0_[1] ),
.I2(load_data[11]),
.I3(\result[11]_i_2_n_0 ),
.I4(\result[11]_i_3_n_0 ),
.I5(\state_reg_n_0_[0] ),
.O(\result[11]_i_1_n_0 ));
LUT4 #(
.INIT(16'h1DE2))
\result[11]_i_10
(.I0(register_a[10]),
.I1(operand_a1),
.I2(result[10]),
.I3(data7[26]),
.O(\result[11]_i_10_n_0 ));
LUT4 #(
.INIT(16'h1DE2))
\result[11]_i_11
(.I0(register_a[9]),
.I1(operand_a1),
.I2(result[9]),
.I3(data7[25]),
.O(\result[11]_i_11_n_0 ));
LUT4 #(
.INIT(16'h1DE2))
\result[11]_i_12
(.I0(register_a[8]),
.I1(operand_a1),
.I2(result[8]),
.I3(data7[24]),
.O(\result[11]_i_12_n_0 ));
LUT6 #(
.INIT(64'hFF470000FFFFFFFF))
\result[11]_i_2
(.I0(\result[11]_i_4_n_0 ),
.I1(store_data[0]),
.I2(\result[12]_i_4_n_0 ),
.I3(\result[27]_i_8_n_0 ),
.I4(\result[11]_i_5_n_0 ),
.I5(opcode_2[0]),
.O(\result[11]_i_2_n_0 ));
LUT6 #(
.INIT(64'hAEAEAEAEFFAEAEAE))
\result[11]_i_3
(.I0(\result[11]_i_6_n_0 ),
.I1(data7[27]),
.I2(\result[14]_i_7_n_0 ),
.I3(store_data[11]),
.I4(\read_input[11]_i_1_n_0 ),
.I5(\result[31]_i_12_n_0 ),
.O(\result[11]_i_3_n_0 ));
LUT3 #(
.INIT(8'hB8))
\result[11]_i_4
(.I0(\result[11]_i_7_n_0 ),
.I1(store_data[1]),
.I2(\result[13]_i_8_n_0 ),
.O(\result[11]_i_4_n_0 ));
LUT6 #(
.INIT(64'h3030FCFF7777FCFF))
\result[11]_i_5
(.I0(store_data[11]),
.I1(opcode_2[1]),
.I2(opcode_2[4]),
.I3(\result_reg[11]_i_8_n_4 ),
.I4(opcode_2[2]),
.I5(\read_input[11]_i_1_n_0 ),
.O(\result[11]_i_5_n_0 ));
LUT6 #(
.INIT(64'h33E200E200000000))
\result[11]_i_6
(.I0(data2[11]),
.I1(opcode_2[3]),
.I2(data5[11]),
.I3(opcode_2[2]),
.I4(\result_reg[15]_i_16_n_4 ),
.I5(opcode_2[1]),
.O(\result[11]_i_6_n_0 ));
LUT6 #(
.INIT(64'h0000000030BB3088))
\result[11]_i_7
(.I0(\read_input[4]_i_1_n_0 ),
.I1(store_data[2]),
.I2(\read_input[0]_i_1_n_0 ),
.I3(store_data[3]),
.I4(\read_input[8]_i_1_n_0 ),
.I5(store_data[4]),
.O(\result[11]_i_7_n_0 ));
LUT4 #(
.INIT(16'h1DE2))
\result[11]_i_9
(.I0(register_a[11]),
.I1(operand_a1),
.I2(result[11]),
.I3(data7[27]),
.O(\result[11]_i_9_n_0 ));
LUT6 #(
.INIT(64'hFFFF20FF20202020))
\result[12]_i_1
(.I0(\state_reg_n_0_[2] ),
.I1(\state_reg_n_0_[1] ),
.I2(load_data[12]),
.I3(\result[12]_i_2_n_0 ),
.I4(\result[12]_i_3_n_0 ),
.I5(\state_reg_n_0_[0] ),
.O(\result[12]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFF470000FFFFFFFF))
\result[12]_i_2
(.I0(\result[12]_i_4_n_0 ),
.I1(store_data[0]),
.I2(\result[13]_i_5_n_0 ),
.I3(\result[27]_i_8_n_0 ),
.I4(\result[12]_i_5_n_0 ),
.I5(opcode_2[0]),
.O(\result[12]_i_2_n_0 ));
LUT6 #(
.INIT(64'hAEAEAEAEFFAEAEAE))
\result[12]_i_3
(.I0(\result[12]_i_6_n_0 ),
.I1(data7[28]),
.I2(\result[14]_i_7_n_0 ),
.I3(store_data[12]),
.I4(\read_input[12]_i_1_n_0 ),
.I5(\result[31]_i_12_n_0 ),
.O(\result[12]_i_3_n_0 ));
LUT3 #(
.INIT(8'hB8))
\result[12]_i_4
(.I0(\result[12]_i_7_n_0 ),
.I1(store_data[1]),
.I2(\result[14]_i_8_n_0 ),
.O(\result[12]_i_4_n_0 ));
LUT6 #(
.INIT(64'h3030FCFF7777FCFF))
\result[12]_i_5
(.I0(store_data[12]),
.I1(opcode_2[1]),
.I2(opcode_2[4]),
.I3(\result_reg[15]_i_10_n_7 ),
.I4(opcode_2[2]),
.I5(\read_input[12]_i_1_n_0 ),
.O(\result[12]_i_5_n_0 ));
LUT6 #(
.INIT(64'h33E200E200000000))
\result[12]_i_6
(.I0(data2[12]),
.I1(opcode_2[3]),
.I2(data5[12]),
.I3(opcode_2[2]),
.I4(\result_reg[15]_i_8_n_7 ),
.I5(opcode_2[1]),
.O(\result[12]_i_6_n_0 ));
LUT6 #(
.INIT(64'h0000000030BB3088))
\result[12]_i_7
(.I0(\read_input[5]_i_1_n_0 ),
.I1(store_data[2]),
.I2(\read_input[1]_i_1_n_0 ),
.I3(store_data[3]),
.I4(\read_input[9]_i_1_n_0 ),
.I5(store_data[4]),
.O(\result[12]_i_7_n_0 ));
LUT6 #(
.INIT(64'hFFFFFF8F88888888))
\result[13]_i_1
(.I0(\result[27]_i_2_n_0 ),
.I1(load_data[13]),
.I2(\result[13]_i_2_n_0 ),
.I3(\result[13]_i_3_n_0 ),
.I4(\result[13]_i_4_n_0 ),
.I5(\state_reg_n_0_[0] ),
.O(\result[13]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFF1D0000FFFFFFFF))
\result[13]_i_2
(.I0(\result[14]_i_4_n_0 ),
.I1(store_data[0]),
.I2(\result[13]_i_5_n_0 ),
.I3(\result[27]_i_8_n_0 ),
.I4(\result[13]_i_6_n_0 ),
.I5(opcode_2[0]),
.O(\result[13]_i_2_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFF00000004))
\result[13]_i_3
(.I0(opcode_2[0]),
.I1(data7[29]),
.I2(opcode_2[2]),
.I3(opcode_2[3]),
.I4(opcode_2[4]),
.I5(\result[13]_i_7_n_0 ),
.O(\result[13]_i_3_n_0 ));
LUT6 #(
.INIT(64'h33E200E200000000))
\result[13]_i_4
(.I0(data2[13]),
.I1(opcode_2[3]),
.I2(data5[13]),
.I3(opcode_2[2]),
.I4(\result_reg[15]_i_8_n_6 ),
.I5(opcode_2[1]),
.O(\result[13]_i_4_n_0 ));
LUT5 #(
.INIT(32'hB8BBB888))
\result[13]_i_5
(.I0(\result[13]_i_8_n_0 ),
.I1(store_data[1]),
.I2(\result[15]_i_9_n_0 ),
.I3(store_data[2]),
.I4(\result[19]_i_9_n_0 ),
.O(\result[13]_i_5_n_0 ));
LUT6 #(
.INIT(64'h3030FCFF7777FCFF))
\result[13]_i_6
(.I0(store_data[13]),
.I1(opcode_2[1]),
.I2(opcode_2[4]),
.I3(\result_reg[15]_i_10_n_6 ),
.I4(opcode_2[2]),
.I5(\read_input[13]_i_1_n_0 ),
.O(\result[13]_i_6_n_0 ));
LUT6 #(
.INIT(64'h00000000A8B8A800))
\result[13]_i_7
(.I0(result[13]),
.I1(operand_b1),
.I2(register_b[13]),
.I3(operand_a1),
.I4(register_a[13]),
.I5(\result[31]_i_12_n_0 ),
.O(\result[13]_i_7_n_0 ));
LUT6 #(
.INIT(64'h0000000030BB3088))
\result[13]_i_8
(.I0(\read_input[6]_i_1_n_0 ),
.I1(store_data[2]),
.I2(\read_input[2]_i_1_n_0 ),
.I3(store_data[3]),
.I4(\read_input[10]_i_1_n_0 ),
.I5(store_data[4]),
.O(\result[13]_i_8_n_0 ));
LUT6 #(
.INIT(64'hFFFF20FF20202020))
\result[14]_i_1
(.I0(\state_reg_n_0_[2] ),
.I1(\state_reg_n_0_[1] ),
.I2(load_data[14]),
.I3(\result[14]_i_2_n_0 ),
.I4(\result[14]_i_3_n_0 ),
.I5(\state_reg_n_0_[0] ),
.O(\result[14]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFF1D0000FFFFFFFF))
\result[14]_i_2
(.I0(\result[15]_i_5_n_0 ),
.I1(store_data[0]),
.I2(\result[14]_i_4_n_0 ),
.I3(\result[27]_i_8_n_0 ),
.I4(\result[14]_i_5_n_0 ),
.I5(opcode_2[0]),
.O(\result[14]_i_2_n_0 ));
LUT6 #(
.INIT(64'hAEAEAEAEFFAEAEAE))
\result[14]_i_3
(.I0(\result[14]_i_6_n_0 ),
.I1(data7[30]),
.I2(\result[14]_i_7_n_0 ),
.I3(store_data[14]),
.I4(\read_input[14]_i_1_n_0 ),
.I5(\result[31]_i_12_n_0 ),
.O(\result[14]_i_3_n_0 ));
LUT5 #(
.INIT(32'hB8BBB888))
\result[14]_i_4
(.I0(\result[14]_i_8_n_0 ),
.I1(store_data[1]),
.I2(\result[16]_i_8_n_0 ),
.I3(store_data[2]),
.I4(\result[20]_i_7_n_0 ),
.O(\result[14]_i_4_n_0 ));
LUT6 #(
.INIT(64'h3030FCFF7777FCFF))
\result[14]_i_5
(.I0(store_data[14]),
.I1(opcode_2[1]),
.I2(opcode_2[4]),
.I3(\result_reg[15]_i_10_n_5 ),
.I4(opcode_2[2]),
.I5(\read_input[14]_i_1_n_0 ),
.O(\result[14]_i_5_n_0 ));
LUT6 #(
.INIT(64'h33E200E200000000))
\result[14]_i_6
(.I0(data2[14]),
.I1(opcode_2[3]),
.I2(data5[14]),
.I3(opcode_2[2]),
.I4(\result_reg[15]_i_8_n_5 ),
.I5(opcode_2[1]),
.O(\result[14]_i_6_n_0 ));
LUT4 #(
.INIT(16'hFFFE))
\result[14]_i_7
(.I0(opcode_2[0]),
.I1(opcode_2[4]),
.I2(opcode_2[3]),
.I3(opcode_2[2]),
.O(\result[14]_i_7_n_0 ));
LUT6 #(
.INIT(64'h0000000033B800B8))
\result[14]_i_8
(.I0(\read_input[7]_i_1_n_0 ),
.I1(store_data[2]),
.I2(\read_input[11]_i_1_n_0 ),
.I3(store_data[3]),
.I4(\read_input[3]_i_1_n_0 ),
.I5(store_data[4]),
.O(\result[14]_i_8_n_0 ));
LUT6 #(
.INIT(64'hFFFFFF8F88888888))
\result[15]_i_1
(.I0(\result[27]_i_2_n_0 ),
.I1(load_data[15]),
.I2(\result[15]_i_2_n_0 ),
.I3(\result[15]_i_3_n_0 ),
.I4(\result[15]_i_4_n_0 ),
.I5(\state_reg_n_0_[0] ),
.O(\result[15]_i_1_n_0 ));
LUT5 #(
.INIT(32'hEEE1DD2D))
\result[15]_i_12
(.I0(register_a[15]),
.I1(operand_a1),
.I2(register_b[15]),
.I3(operand_b1),
.I4(result[15]),
.O(\result[15]_i_12_n_0 ));
LUT5 #(
.INIT(32'hEEE1DD2D))
\result[15]_i_13
(.I0(register_a[14]),
.I1(operand_a1),
.I2(register_b[14]),
.I3(operand_b1),
.I4(result[14]),
.O(\result[15]_i_13_n_0 ));
LUT5 #(
.INIT(32'hEEE1DD2D))
\result[15]_i_14
(.I0(register_a[13]),
.I1(operand_a1),
.I2(register_b[13]),
.I3(operand_b1),
.I4(result[13]),
.O(\result[15]_i_14_n_0 ));
LUT5 #(
.INIT(32'hEEE1DD2D))
\result[15]_i_15
(.I0(register_a[12]),
.I1(operand_a1),
.I2(register_b[12]),
.I3(operand_b1),
.I4(result[12]),
.O(\result[15]_i_15_n_0 ));
LUT5 #(
.INIT(32'h124712B8))
\result[15]_i_17
(.I0(result[15]),
.I1(operand_b1),
.I2(register_b[15]),
.I3(operand_a1),
.I4(register_a[15]),
.O(\result[15]_i_17_n_0 ));
LUT5 #(
.INIT(32'h124712B8))
\result[15]_i_18
(.I0(result[14]),
.I1(operand_b1),
.I2(register_b[14]),
.I3(operand_a1),
.I4(register_a[14]),
.O(\result[15]_i_18_n_0 ));
LUT5 #(
.INIT(32'h124712B8))
\result[15]_i_19
(.I0(result[13]),
.I1(operand_b1),
.I2(register_b[13]),
.I3(operand_a1),
.I4(register_a[13]),
.O(\result[15]_i_19_n_0 ));
LUT6 #(
.INIT(64'hFF1D0000FFFFFFFF))
\result[15]_i_2
(.I0(\result[16]_i_5_n_0 ),
.I1(store_data[0]),
.I2(\result[15]_i_5_n_0 ),
.I3(\result[27]_i_8_n_0 ),
.I4(\result[15]_i_6_n_0 ),
.I5(opcode_2[0]),
.O(\result[15]_i_2_n_0 ));
LUT5 #(
.INIT(32'h124712B8))
\result[15]_i_20
(.I0(result[12]),
.I1(operand_b1),
.I2(register_b[12]),
.I3(operand_a1),
.I4(register_a[12]),
.O(\result[15]_i_20_n_0 ));
LUT4 #(
.INIT(16'h1DE2))
\result[15]_i_21
(.I0(register_a[15]),
.I1(operand_a1),
.I2(result[15]),
.I3(data7[31]),
.O(\result[15]_i_21_n_0 ));
LUT4 #(
.INIT(16'h1DE2))
\result[15]_i_22
(.I0(register_a[14]),
.I1(operand_a1),
.I2(result[14]),
.I3(data7[30]),
.O(\result[15]_i_22_n_0 ));
LUT4 #(
.INIT(16'h1DE2))
\result[15]_i_23
(.I0(register_a[13]),
.I1(operand_a1),
.I2(result[13]),
.I3(data7[29]),
.O(\result[15]_i_23_n_0 ));
LUT4 #(
.INIT(16'h1DE2))
\result[15]_i_24
(.I0(register_a[12]),
.I1(operand_a1),
.I2(result[12]),
.I3(data7[28]),
.O(\result[15]_i_24_n_0 ));
LUT5 #(
.INIT(32'hEEE1DD2D))
\result[15]_i_25
(.I0(register_a[11]),
.I1(operand_a1),
.I2(register_b[11]),
.I3(operand_b1),
.I4(result[11]),
.O(\result[15]_i_25_n_0 ));
LUT5 #(
.INIT(32'hEEE1DD2D))
\result[15]_i_26
(.I0(register_a[10]),
.I1(operand_a1),
.I2(register_b[10]),
.I3(operand_b1),
.I4(result[10]),
.O(\result[15]_i_26_n_0 ));
LUT5 #(
.INIT(32'hEEE1DD2D))
\result[15]_i_27
(.I0(register_a[9]),
.I1(operand_a1),
.I2(register_b[9]),
.I3(operand_b1),
.I4(result[9]),
.O(\result[15]_i_27_n_0 ));
LUT5 #(
.INIT(32'hEEE1DD2D))
\result[15]_i_28
(.I0(register_a[8]),
.I1(operand_a1),
.I2(register_b[8]),
.I3(operand_b1),
.I4(result[8]),
.O(\result[15]_i_28_n_0 ));
LUT5 #(
.INIT(32'h124712B8))
\result[15]_i_29
(.I0(result[11]),
.I1(operand_b1),
.I2(register_b[11]),
.I3(operand_a1),
.I4(register_a[11]),
.O(\result[15]_i_29_n_0 ));
LUT6 #(
.INIT(64'hBABABAAAAAAABAAA))
\result[15]_i_3
(.I0(\result[31]_i_13_n_0 ),
.I1(\result[31]_i_12_n_0 ),
.I2(\read_input[15]_i_1_n_0 ),
.I3(register_b[15]),
.I4(operand_b1),
.I5(result[15]),
.O(\result[15]_i_3_n_0 ));
LUT5 #(
.INIT(32'h124712B8))
\result[15]_i_30
(.I0(result[10]),
.I1(operand_b1),
.I2(register_b[10]),
.I3(operand_a1),
.I4(register_a[10]),
.O(\result[15]_i_30_n_0 ));
LUT5 #(
.INIT(32'h124712B8))
\result[15]_i_31
(.I0(result[9]),
.I1(operand_b1),
.I2(register_b[9]),
.I3(operand_a1),
.I4(register_a[9]),
.O(\result[15]_i_31_n_0 ));
LUT5 #(
.INIT(32'h124712B8))
\result[15]_i_32
(.I0(result[8]),
.I1(operand_b1),
.I2(register_b[8]),
.I3(operand_a1),
.I4(register_a[8]),
.O(\result[15]_i_32_n_0 ));
LUT6 #(
.INIT(64'h33E200E200000000))
\result[15]_i_4
(.I0(data2[15]),
.I1(opcode_2[3]),
.I2(data5[15]),
.I3(opcode_2[2]),
.I4(\result_reg[15]_i_8_n_4 ),
.I5(opcode_2[1]),
.O(\result[15]_i_4_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\result[15]_i_5
(.I0(\result[15]_i_9_n_0 ),
.I1(\result[19]_i_9_n_0 ),
.I2(store_data[1]),
.I3(\result[17]_i_7_n_0 ),
.I4(store_data[2]),
.I5(\result[21]_i_7_n_0 ),
.O(\result[15]_i_5_n_0 ));
LUT6 #(
.INIT(64'h3030FCFF7777FCFF))
\result[15]_i_6
(.I0(store_data[15]),
.I1(opcode_2[1]),
.I2(opcode_2[4]),
.I3(\result_reg[15]_i_10_n_4 ),
.I4(opcode_2[2]),
.I5(\read_input[15]_i_1_n_0 ),
.O(\result[15]_i_6_n_0 ));
LUT6 #(
.INIT(64'h00000000B8FFB800))
\result[15]_i_9
(.I0(result[0]),
.I1(operand_a1),
.I2(register_a[0]),
.I3(store_data[3]),
.I4(\read_input[8]_i_1_n_0 ),
.I5(store_data[4]),
.O(\result[15]_i_9_n_0 ));
LUT6 #(
.INIT(64'hFFFFFF8F88888888))
\result[16]_i_1
(.I0(\result[27]_i_2_n_0 ),
.I1(load_data[16]),
.I2(\result[16]_i_2_n_0 ),
.I3(\result[16]_i_3_n_0 ),
.I4(\result[16]_i_4_n_0 ),
.I5(\state_reg_n_0_[0] ),
.O(\result[16]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFF1D0000FFFFFFFF))
\result[16]_i_2
(.I0(\result[17]_i_4_n_0 ),
.I1(store_data[0]),
.I2(\result[16]_i_5_n_0 ),
.I3(\result[27]_i_8_n_0 ),
.I4(\result[16]_i_6_n_0 ),
.I5(opcode_2[0]),
.O(\result[16]_i_2_n_0 ));
LUT6 #(
.INIT(64'h33E200E200000000))
\result[16]_i_3
(.I0(data2[16]),
.I1(opcode_2[3]),
.I2(data5[16]),
.I3(opcode_2[2]),
.I4(\result_reg[19]_i_7_n_7 ),
.I5(opcode_2[1]),
.O(\result[16]_i_3_n_0 ));
LUT6 #(
.INIT(64'hBABABAAAAAAABAAA))
\result[16]_i_4
(.I0(\result[31]_i_13_n_0 ),
.I1(\result[31]_i_12_n_0 ),
.I2(\read_input[16]_i_1_n_0 ),
.I3(register_b[16]),
.I4(operand_b1),
.I5(result[16]),
.O(\result[16]_i_4_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\result[16]_i_5
(.I0(\result[16]_i_8_n_0 ),
.I1(\result[20]_i_7_n_0 ),
.I2(store_data[1]),
.I3(\result[18]_i_7_n_0 ),
.I4(store_data[2]),
.I5(\result[22]_i_7_n_0 ),
.O(\result[16]_i_5_n_0 ));
LUT6 #(
.INIT(64'hB8B8B8BBBBBBB8BB))
\result[16]_i_6
(.I0(\result[16]_i_9_n_0 ),
.I1(opcode_2[1]),
.I2(opcode_2[4]),
.I3(\result_reg[19]_i_11_n_7 ),
.I4(opcode_2[2]),
.I5(address_b_2[0]),
.O(\result[16]_i_6_n_0 ));
LUT6 #(
.INIT(64'h00000000B8FFB800))
\result[16]_i_8
(.I0(result[1]),
.I1(operand_a1),
.I2(register_a[1]),
.I3(store_data[3]),
.I4(\read_input[9]_i_1_n_0 ),
.I5(store_data[4]),
.O(\result[16]_i_8_n_0 ));
LUT6 #(
.INIT(64'h45004547FFFFFFFF))
\result[16]_i_9
(.I0(result[16]),
.I1(operand_b1),
.I2(register_b[16]),
.I3(operand_a1),
.I4(register_a[16]),
.I5(opcode_2[2]),
.O(\result[16]_i_9_n_0 ));
LUT6 #(
.INIT(64'hFFFF20FF20202020))
\result[17]_i_1
(.I0(\state_reg_n_0_[2] ),
.I1(\state_reg_n_0_[1] ),
.I2(load_data[17]),
.I3(\result[17]_i_2_n_0 ),
.I4(\result[17]_i_3_n_0 ),
.I5(\state_reg_n_0_[0] ),
.O(\result[17]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFF470000FFFFFFFF))
\result[17]_i_2
(.I0(\result[17]_i_4_n_0 ),
.I1(store_data[0]),
.I2(\result[18]_i_4_n_0 ),
.I3(\result[27]_i_8_n_0 ),
.I4(\result[17]_i_5_n_0 ),
.I5(opcode_2[0]),
.O(\result[17]_i_2_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFF38080000))
\result[17]_i_3
(.I0(data5[17]),
.I1(opcode_2[3]),
.I2(opcode_2[2]),
.I3(\result_reg[19]_i_7_n_6 ),
.I4(opcode_2[1]),
.I5(\result[17]_i_6_n_0 ),
.O(\result[17]_i_3_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\result[17]_i_4
(.I0(\result[17]_i_7_n_0 ),
.I1(\result[21]_i_7_n_0 ),
.I2(store_data[1]),
.I3(\result[19]_i_9_n_0 ),
.I4(store_data[2]),
.I5(\result[23]_i_9_n_0 ),
.O(\result[17]_i_4_n_0 ));
LUT6 #(
.INIT(64'hB8B8B8BBBBBBB8BB))
\result[17]_i_5
(.I0(\result[17]_i_8_n_0 ),
.I1(opcode_2[1]),
.I2(opcode_2[4]),
.I3(\result_reg[19]_i_11_n_6 ),
.I4(opcode_2[2]),
.I5(address_b_2[1]),
.O(\result[17]_i_5_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFF44400040))
\result[17]_i_6
(.I0(\result[31]_i_12_n_0 ),
.I1(\read_input[17]_i_1_n_0 ),
.I2(register_b[17]),
.I3(operand_b1),
.I4(result[17]),
.I5(\result[31]_i_13_n_0 ),
.O(\result[17]_i_6_n_0 ));
LUT6 #(
.INIT(64'h00000000E2FFE200))
\result[17]_i_7
(.I0(register_a[2]),
.I1(operand_a1),
.I2(result[2]),
.I3(store_data[3]),
.I4(\read_input[10]_i_1_n_0 ),
.I5(store_data[4]),
.O(\result[17]_i_7_n_0 ));
LUT6 #(
.INIT(64'h45004547FFFFFFFF))
\result[17]_i_8
(.I0(result[17]),
.I1(operand_b1),
.I2(register_b[17]),
.I3(operand_a1),
.I4(register_a[17]),
.I5(opcode_2[2]),
.O(\result[17]_i_8_n_0 ));
LUT6 #(
.INIT(64'hFFFF20FF20202020))
\result[18]_i_1
(.I0(\state_reg_n_0_[2] ),
.I1(\state_reg_n_0_[1] ),
.I2(load_data[18]),
.I3(\result[18]_i_2_n_0 ),
.I4(\result[18]_i_3_n_0 ),
.I5(\state_reg_n_0_[0] ),
.O(\result[18]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFF1D0000FFFFFFFF))
\result[18]_i_2
(.I0(\result[19]_i_4_n_0 ),
.I1(store_data[0]),
.I2(\result[18]_i_4_n_0 ),
.I3(\result[27]_i_8_n_0 ),
.I4(\result[18]_i_5_n_0 ),
.I5(opcode_2[0]),
.O(\result[18]_i_2_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFF38080000))
\result[18]_i_3
(.I0(data5[18]),
.I1(opcode_2[3]),
.I2(opcode_2[2]),
.I3(\result_reg[19]_i_7_n_5 ),
.I4(opcode_2[1]),
.I5(\result[18]_i_6_n_0 ),
.O(\result[18]_i_3_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\result[18]_i_4
(.I0(\result[18]_i_7_n_0 ),
.I1(\result[22]_i_7_n_0 ),
.I2(store_data[1]),
.I3(\result[20]_i_7_n_0 ),
.I4(store_data[2]),
.I5(\result[24]_i_7_n_0 ),
.O(\result[18]_i_4_n_0 ));
LUT6 #(
.INIT(64'hB8B8B8BBBBBBB8BB))
\result[18]_i_5
(.I0(\result[18]_i_8_n_0 ),
.I1(opcode_2[1]),
.I2(opcode_2[4]),
.I3(\result_reg[19]_i_11_n_5 ),
.I4(opcode_2[2]),
.I5(address_b_2[2]),
.O(\result[18]_i_5_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFF44400040))
\result[18]_i_6
(.I0(\result[31]_i_12_n_0 ),
.I1(\read_input[18]_i_1_n_0 ),
.I2(register_b[18]),
.I3(operand_b1),
.I4(result[18]),
.I5(\result[31]_i_13_n_0 ),
.O(\result[18]_i_6_n_0 ));
LUT6 #(
.INIT(64'h00000000EEE222E2))
\result[18]_i_7
(.I0(\read_input[11]_i_1_n_0 ),
.I1(store_data[3]),
.I2(register_a[3]),
.I3(operand_a1),
.I4(result[3]),
.I5(store_data[4]),
.O(\result[18]_i_7_n_0 ));
LUT6 #(
.INIT(64'h45004547FFFFFFFF))
\result[18]_i_8
(.I0(result[18]),
.I1(operand_b1),
.I2(register_b[18]),
.I3(operand_a1),
.I4(register_a[18]),
.I5(opcode_2[2]),
.O(\result[18]_i_8_n_0 ));
LUT6 #(
.INIT(64'hFFFF20FF20202020))
\result[19]_i_1
(.I0(\state_reg_n_0_[2] ),
.I1(\state_reg_n_0_[1] ),
.I2(load_data[19]),
.I3(\result[19]_i_2_n_0 ),
.I4(\result[19]_i_3_n_0 ),
.I5(\state_reg_n_0_[0] ),
.O(\result[19]_i_1_n_0 ));
LUT6 #(
.INIT(64'h45004547FFFFFFFF))
\result[19]_i_10
(.I0(result[19]),
.I1(operand_b1),
.I2(register_b[19]),
.I3(operand_a1),
.I4(register_a[19]),
.I5(opcode_2[2]),
.O(\result[19]_i_10_n_0 ));
LUT5 #(
.INIT(32'hEDB8ED47))
\result[19]_i_12
(.I0(result[19]),
.I1(operand_b1),
.I2(register_b[19]),
.I3(operand_a1),
.I4(register_a[19]),
.O(\result[19]_i_12_n_0 ));
LUT5 #(
.INIT(32'hEDB8ED47))
\result[19]_i_13
(.I0(result[18]),
.I1(operand_b1),
.I2(register_b[18]),
.I3(operand_a1),
.I4(register_a[18]),
.O(\result[19]_i_13_n_0 ));
LUT5 #(
.INIT(32'hEDB8ED47))
\result[19]_i_14
(.I0(result[17]),
.I1(operand_b1),
.I2(register_b[17]),
.I3(operand_a1),
.I4(register_a[17]),
.O(\result[19]_i_14_n_0 ));
LUT5 #(
.INIT(32'hEDB8ED47))
\result[19]_i_15
(.I0(result[16]),
.I1(operand_b1),
.I2(register_b[16]),
.I3(operand_a1),
.I4(register_a[16]),
.O(\result[19]_i_15_n_0 ));
LUT5 #(
.INIT(32'h111E22D2))
\result[19]_i_16
(.I0(register_a[19]),
.I1(operand_a1),
.I2(register_b[19]),
.I3(operand_b1),
.I4(result[19]),
.O(\result[19]_i_16_n_0 ));
LUT5 #(
.INIT(32'h111E22D2))
\result[19]_i_17
(.I0(register_a[18]),
.I1(operand_a1),
.I2(register_b[18]),
.I3(operand_b1),
.I4(result[18]),
.O(\result[19]_i_17_n_0 ));
LUT5 #(
.INIT(32'h111E22D2))
\result[19]_i_18
(.I0(register_a[17]),
.I1(operand_a1),
.I2(register_b[17]),
.I3(operand_b1),
.I4(result[17]),
.O(\result[19]_i_18_n_0 ));
LUT5 #(
.INIT(32'h111E22D2))
\result[19]_i_19
(.I0(register_a[16]),
.I1(operand_a1),
.I2(register_b[16]),
.I3(operand_b1),
.I4(result[16]),
.O(\result[19]_i_19_n_0 ));
LUT6 #(
.INIT(64'hFF1D0000FFFFFFFF))
\result[19]_i_2
(.I0(\result[20]_i_5_n_0 ),
.I1(store_data[0]),
.I2(\result[19]_i_4_n_0 ),
.I3(\result[27]_i_8_n_0 ),
.I4(\result[19]_i_5_n_0 ),
.I5(opcode_2[0]),
.O(\result[19]_i_2_n_0 ));
LUT5 #(
.INIT(32'hFFFB0008))
\result[19]_i_20
(.I0(result[19]),
.I1(write_enable_reg_n_0),
.I2(\read_input[31]_i_4_n_0 ),
.I3(\read_input[31]_i_5_n_0 ),
.I4(register_a[19]),
.O(\result[19]_i_20_n_0 ));
LUT5 #(
.INIT(32'hFFFB0008))
\result[19]_i_21
(.I0(result[18]),
.I1(write_enable_reg_n_0),
.I2(\read_input[31]_i_4_n_0 ),
.I3(\read_input[31]_i_5_n_0 ),
.I4(register_a[18]),
.O(\result[19]_i_21_n_0 ));
LUT5 #(
.INIT(32'hFFFB0008))
\result[19]_i_22
(.I0(result[17]),
.I1(write_enable_reg_n_0),
.I2(\read_input[31]_i_4_n_0 ),
.I3(\read_input[31]_i_5_n_0 ),
.I4(register_a[17]),
.O(\result[19]_i_22_n_0 ));
LUT5 #(
.INIT(32'hFFFB0008))
\result[19]_i_23
(.I0(result[16]),
.I1(write_enable_reg_n_0),
.I2(\read_input[31]_i_4_n_0 ),
.I3(\read_input[31]_i_5_n_0 ),
.I4(register_a[16]),
.O(\result[19]_i_23_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFF38080000))
\result[19]_i_3
(.I0(data5[19]),
.I1(opcode_2[3]),
.I2(opcode_2[2]),
.I3(\result_reg[19]_i_7_n_4 ),
.I4(opcode_2[1]),
.I5(\result[19]_i_8_n_0 ),
.O(\result[19]_i_3_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\result[19]_i_4
(.I0(\result[19]_i_9_n_0 ),
.I1(\result[23]_i_9_n_0 ),
.I2(store_data[1]),
.I3(\result[21]_i_7_n_0 ),
.I4(store_data[2]),
.I5(\result[25]_i_7_n_0 ),
.O(\result[19]_i_4_n_0 ));
LUT6 #(
.INIT(64'hB8B8B8BBBBBBB8BB))
\result[19]_i_5
(.I0(\result[19]_i_10_n_0 ),
.I1(opcode_2[1]),
.I2(opcode_2[4]),
.I3(\result_reg[19]_i_11_n_4 ),
.I4(opcode_2[2]),
.I5(address_b_2[3]),
.O(\result[19]_i_5_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFF44400040))
\result[19]_i_8
(.I0(\result[31]_i_12_n_0 ),
.I1(\read_input[19]_i_1_n_0 ),
.I2(register_b[19]),
.I3(operand_b1),
.I4(result[19]),
.I5(\result[31]_i_13_n_0 ),
.O(\result[19]_i_8_n_0 ));
LUT6 #(
.INIT(64'h00000000E2FFE200))
\result[19]_i_9
(.I0(register_a[4]),
.I1(operand_a1),
.I2(result[4]),
.I3(store_data[3]),
.I4(\read_input[12]_i_1_n_0 ),
.I5(store_data[4]),
.O(\result[19]_i_9_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFFFFA20000))
\result[1]_i_1
(.I0(opcode_2[0]),
.I1(\result[1]_i_2_n_0 ),
.I2(\result[1]_i_3_n_0 ),
.I3(\result[1]_i_4_n_0 ),
.I4(\state_reg_n_0_[0] ),
.I5(\result[1]_i_5_n_0 ),
.O(\result[1]_i_1_n_0 ));
LUT4 #(
.INIT(16'h1DE2))
\result[1]_i_10
(.I0(register_a[3]),
.I1(operand_a1),
.I2(result[3]),
.I3(address_b_2[3]),
.O(\result[1]_i_10_n_0 ));
LUT4 #(
.INIT(16'h1DE2))
\result[1]_i_11
(.I0(register_a[2]),
.I1(operand_a1),
.I2(result[2]),
.I3(address_b_2[2]),
.O(\result[1]_i_11_n_0 ));
LUT4 #(
.INIT(16'h1DE2))
\result[1]_i_12
(.I0(register_a[1]),
.I1(operand_a1),
.I2(result[1]),
.I3(address_b_2[1]),
.O(\result[1]_i_12_n_0 ));
LUT4 #(
.INIT(16'h1DE2))
\result[1]_i_13
(.I0(register_a[0]),
.I1(operand_a1),
.I2(result[0]),
.I3(address_b_2[0]),
.O(\result[1]_i_13_n_0 ));
LUT6 #(
.INIT(64'h3030FCFF7777FCFF))
\result[1]_i_2
(.I0(store_data[1]),
.I1(opcode_2[1]),
.I2(opcode_2[4]),
.I3(\result_reg[1]_i_6_n_6 ),
.I4(opcode_2[2]),
.I5(\read_input[1]_i_1_n_0 ),
.O(\result[1]_i_2_n_0 ));
LUT6 #(
.INIT(64'h00000000000C000A))
\result[1]_i_3
(.I0(\result[1]_i_7_n_0 ),
.I1(\result[1]_i_8_n_0 ),
.I2(store_data[2]),
.I3(store_data[1]),
.I4(store_data[0]),
.I5(\result[27]_i_8_n_0 ),
.O(\result[1]_i_3_n_0 ));
LUT6 #(
.INIT(64'hAEAEAEAEFFAEAEAE))
\result[1]_i_4
(.I0(\result[1]_i_9_n_0 ),
.I1(address_b_2[1]),
.I2(\result[14]_i_7_n_0 ),
.I3(store_data[1]),
.I4(\read_input[1]_i_1_n_0 ),
.I5(\result[31]_i_12_n_0 ),
.O(\result[1]_i_4_n_0 ));
LUT4 #(
.INIT(16'hE200))
\result[1]_i_5
(.I0(load_data[1]),
.I1(\state_reg_n_0_[1] ),
.I2(OUT1[1]),
.I3(\state_reg_n_0_[2] ),
.O(\result[1]_i_5_n_0 ));
LUT6 #(
.INIT(64'h0030000000305050))
\result[1]_i_7
(.I0(register_b[3]),
.I1(result[3]),
.I2(\read_input[1]_i_1_n_0 ),
.I3(result[4]),
.I4(operand_b1),
.I5(register_b[4]),
.O(\result[1]_i_7_n_0 ));
LUT6 #(
.INIT(64'h0030000000305050))
\result[1]_i_8
(.I0(register_b[3]),
.I1(result[3]),
.I2(\read_input[0]_i_1_n_0 ),
.I3(result[4]),
.I4(operand_b1),
.I5(register_b[4]),
.O(\result[1]_i_8_n_0 ));
LUT6 #(
.INIT(64'h33E200E200000000))
\result[1]_i_9
(.I0(data2[1]),
.I1(opcode_2[3]),
.I2(data5[1]),
.I3(opcode_2[2]),
.I4(\result_reg[3]_i_9_n_6 ),
.I5(opcode_2[1]),
.O(\result[1]_i_9_n_0 ));
LUT6 #(
.INIT(64'hFFFFF8FF88888888))
\result[20]_i_1
(.I0(\result[27]_i_2_n_0 ),
.I1(load_data[20]),
.I2(\result[20]_i_2_n_0 ),
.I3(\result[20]_i_3_n_0 ),
.I4(\result[20]_i_4_n_0 ),
.I5(\state_reg_n_0_[0] ),
.O(\result[20]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFF44400040))
\result[20]_i_2
(.I0(\result[31]_i_12_n_0 ),
.I1(\read_input[20]_i_1_n_0 ),
.I2(register_b[20]),
.I3(operand_b1),
.I4(result[20]),
.I5(\result[31]_i_13_n_0 ),
.O(\result[20]_i_2_n_0 ));
LUT6 #(
.INIT(64'hFF470000FFFFFFFF))
\result[20]_i_3
(.I0(\result[20]_i_5_n_0 ),
.I1(store_data[0]),
.I2(\result[21]_i_5_n_0 ),
.I3(\result[27]_i_8_n_0 ),
.I4(\result[20]_i_6_n_0 ),
.I5(opcode_2[0]),
.O(\result[20]_i_3_n_0 ));
LUT5 #(
.INIT(32'h0A800080))
\result[20]_i_4
(.I0(opcode_2[1]),
.I1(\result_reg[23]_i_7_n_7 ),
.I2(opcode_2[2]),
.I3(opcode_2[3]),
.I4(data5[20]),
.O(\result[20]_i_4_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\result[20]_i_5
(.I0(\result[20]_i_7_n_0 ),
.I1(\result[24]_i_7_n_0 ),
.I2(store_data[1]),
.I3(\result[22]_i_7_n_0 ),
.I4(store_data[2]),
.I5(\result[26]_i_7_n_0 ),
.O(\result[20]_i_5_n_0 ));
LUT6 #(
.INIT(64'hCFC0CFCFCFC5CFC5))
\result[20]_i_6
(.I0(\result_reg[23]_i_10_n_7 ),
.I1(\result[20]_i_8_n_0 ),
.I2(opcode_2[1]),
.I3(opcode_2[4]),
.I4(data7[20]),
.I5(opcode_2[2]),
.O(\result[20]_i_6_n_0 ));
LUT6 #(
.INIT(64'h00000000BBB888B8))
\result[20]_i_7
(.I0(\read_input[5]_i_1_n_0 ),
.I1(store_data[3]),
.I2(register_a[13]),
.I3(operand_a1),
.I4(result[13]),
.I5(store_data[4]),
.O(\result[20]_i_7_n_0 ));
LUT6 #(
.INIT(64'h45004547FFFFFFFF))
\result[20]_i_8
(.I0(result[20]),
.I1(operand_b1),
.I2(register_b[20]),
.I3(operand_a1),
.I4(register_a[20]),
.I5(opcode_2[2]),
.O(\result[20]_i_8_n_0 ));
LUT6 #(
.INIT(64'hFFFFF8FF88888888))
\result[21]_i_1
(.I0(\result[27]_i_2_n_0 ),
.I1(load_data[21]),
.I2(\result[21]_i_2_n_0 ),
.I3(\result[21]_i_3_n_0 ),
.I4(\result[21]_i_4_n_0 ),
.I5(\state_reg_n_0_[0] ),
.O(\result[21]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFF44400040))
\result[21]_i_2
(.I0(\result[31]_i_12_n_0 ),
.I1(\read_input[21]_i_1_n_0 ),
.I2(register_b[21]),
.I3(operand_b1),
.I4(result[21]),
.I5(\result[31]_i_13_n_0 ),
.O(\result[21]_i_2_n_0 ));
LUT6 #(
.INIT(64'hFF1D0000FFFFFFFF))
\result[21]_i_3
(.I0(\result[22]_i_5_n_0 ),
.I1(store_data[0]),
.I2(\result[21]_i_5_n_0 ),
.I3(\result[27]_i_8_n_0 ),
.I4(\result[21]_i_6_n_0 ),
.I5(opcode_2[0]),
.O(\result[21]_i_3_n_0 ));
LUT5 #(
.INIT(32'h0A800080))
\result[21]_i_4
(.I0(opcode_2[1]),
.I1(\result_reg[23]_i_7_n_6 ),
.I2(opcode_2[2]),
.I3(opcode_2[3]),
.I4(data5[21]),
.O(\result[21]_i_4_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\result[21]_i_5
(.I0(\result[21]_i_7_n_0 ),
.I1(\result[25]_i_7_n_0 ),
.I2(store_data[1]),
.I3(\result[23]_i_9_n_0 ),
.I4(store_data[2]),
.I5(\result[27]_i_12_n_0 ),
.O(\result[21]_i_5_n_0 ));
LUT6 #(
.INIT(64'hCFC0CFCFCFC5CFC5))
\result[21]_i_6
(.I0(\result_reg[23]_i_10_n_6 ),
.I1(\result[21]_i_8_n_0 ),
.I2(opcode_2[1]),
.I3(opcode_2[4]),
.I4(data7[21]),
.I5(opcode_2[2]),
.O(\result[21]_i_6_n_0 ));
LUT6 #(
.INIT(64'h00000000BBB888B8))
\result[21]_i_7
(.I0(\read_input[6]_i_1_n_0 ),
.I1(store_data[3]),
.I2(register_a[14]),
.I3(operand_a1),
.I4(result[14]),
.I5(store_data[4]),
.O(\result[21]_i_7_n_0 ));
LUT6 #(
.INIT(64'h45004547FFFFFFFF))
\result[21]_i_8
(.I0(result[21]),
.I1(operand_b1),
.I2(register_b[21]),
.I3(operand_a1),
.I4(register_a[21]),
.I5(opcode_2[2]),
.O(\result[21]_i_8_n_0 ));
LUT6 #(
.INIT(64'hFFFFF8FF88888888))
\result[22]_i_1
(.I0(\result[27]_i_2_n_0 ),
.I1(load_data[22]),
.I2(\result[22]_i_2_n_0 ),
.I3(\result[22]_i_3_n_0 ),
.I4(\result[22]_i_4_n_0 ),
.I5(\state_reg_n_0_[0] ),
.O(\result[22]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFF44400040))
\result[22]_i_2
(.I0(\result[31]_i_12_n_0 ),
.I1(\read_input[22]_i_1_n_0 ),
.I2(register_b[22]),
.I3(operand_b1),
.I4(result[22]),
.I5(\result[31]_i_13_n_0 ),
.O(\result[22]_i_2_n_0 ));
LUT6 #(
.INIT(64'hFF470000FFFFFFFF))
\result[22]_i_3
(.I0(\result[22]_i_5_n_0 ),
.I1(store_data[0]),
.I2(\result[23]_i_5_n_0 ),
.I3(\result[27]_i_8_n_0 ),
.I4(\result[22]_i_6_n_0 ),
.I5(opcode_2[0]),
.O(\result[22]_i_3_n_0 ));
LUT5 #(
.INIT(32'h0A800080))
\result[22]_i_4
(.I0(opcode_2[1]),
.I1(\result_reg[23]_i_7_n_5 ),
.I2(opcode_2[2]),
.I3(opcode_2[3]),
.I4(data5[22]),
.O(\result[22]_i_4_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\result[22]_i_5
(.I0(\result[22]_i_7_n_0 ),
.I1(\result[26]_i_7_n_0 ),
.I2(store_data[1]),
.I3(\result[24]_i_7_n_0 ),
.I4(store_data[2]),
.I5(\result[27]_i_16_n_0 ),
.O(\result[22]_i_5_n_0 ));
LUT6 #(
.INIT(64'hCFC0CFCFCFC5CFC5))
\result[22]_i_6
(.I0(\result_reg[23]_i_10_n_5 ),
.I1(\result[22]_i_8_n_0 ),
.I2(opcode_2[1]),
.I3(opcode_2[4]),
.I4(data7[22]),
.I5(opcode_2[2]),
.O(\result[22]_i_6_n_0 ));
LUT6 #(
.INIT(64'h00000000BBB888B8))
\result[22]_i_7
(.I0(\read_input[7]_i_1_n_0 ),
.I1(store_data[3]),
.I2(register_a[15]),
.I3(operand_a1),
.I4(result[15]),
.I5(store_data[4]),
.O(\result[22]_i_7_n_0 ));
LUT6 #(
.INIT(64'h45004547FFFFFFFF))
\result[22]_i_8
(.I0(result[22]),
.I1(operand_b1),
.I2(register_b[22]),
.I3(operand_a1),
.I4(register_a[22]),
.I5(opcode_2[2]),
.O(\result[22]_i_8_n_0 ));
LUT6 #(
.INIT(64'hFFFFF8FF88888888))
\result[23]_i_1
(.I0(\result[27]_i_2_n_0 ),
.I1(load_data[23]),
.I2(\result[23]_i_2_n_0 ),
.I3(\result[23]_i_3_n_0 ),
.I4(\result[23]_i_4_n_0 ),
.I5(\state_reg_n_0_[0] ),
.O(\result[23]_i_1_n_0 ));
LUT6 #(
.INIT(64'h45004547FFFFFFFF))
\result[23]_i_11
(.I0(result[23]),
.I1(operand_b1),
.I2(register_b[23]),
.I3(operand_a1),
.I4(register_a[23]),
.I5(opcode_2[2]),
.O(\result[23]_i_11_n_0 ));
LUT5 #(
.INIT(32'h111E22D2))
\result[23]_i_12
(.I0(register_a[23]),
.I1(operand_a1),
.I2(register_b[23]),
.I3(operand_b1),
.I4(result[23]),
.O(\result[23]_i_12_n_0 ));
LUT5 #(
.INIT(32'h111E22D2))
\result[23]_i_13
(.I0(register_a[22]),
.I1(operand_a1),
.I2(register_b[22]),
.I3(operand_b1),
.I4(result[22]),
.O(\result[23]_i_13_n_0 ));
LUT5 #(
.INIT(32'h111E22D2))
\result[23]_i_14
(.I0(register_a[21]),
.I1(operand_a1),
.I2(register_b[21]),
.I3(operand_b1),
.I4(result[21]),
.O(\result[23]_i_14_n_0 ));
LUT5 #(
.INIT(32'h111E22D2))
\result[23]_i_15
(.I0(register_a[20]),
.I1(operand_a1),
.I2(register_b[20]),
.I3(operand_b1),
.I4(result[20]),
.O(\result[23]_i_15_n_0 ));
LUT5 #(
.INIT(32'hEDB8ED47))
\result[23]_i_16
(.I0(result[23]),
.I1(operand_b1),
.I2(register_b[23]),
.I3(operand_a1),
.I4(register_a[23]),
.O(\result[23]_i_16_n_0 ));
LUT5 #(
.INIT(32'hEDB8ED47))
\result[23]_i_17
(.I0(result[22]),
.I1(operand_b1),
.I2(register_b[22]),
.I3(operand_a1),
.I4(register_a[22]),
.O(\result[23]_i_17_n_0 ));
LUT5 #(
.INIT(32'hEDB8ED47))
\result[23]_i_18
(.I0(result[21]),
.I1(operand_b1),
.I2(register_b[21]),
.I3(operand_a1),
.I4(register_a[21]),
.O(\result[23]_i_18_n_0 ));
LUT5 #(
.INIT(32'hEDB8ED47))
\result[23]_i_19
(.I0(result[20]),
.I1(operand_b1),
.I2(register_b[20]),
.I3(operand_a1),
.I4(register_a[20]),
.O(\result[23]_i_19_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFF44400040))
\result[23]_i_2
(.I0(\result[31]_i_12_n_0 ),
.I1(\read_input[23]_i_1_n_0 ),
.I2(register_b[23]),
.I3(operand_b1),
.I4(result[23]),
.I5(\result[31]_i_13_n_0 ),
.O(\result[23]_i_2_n_0 ));
LUT5 #(
.INIT(32'hFFFB0008))
\result[23]_i_20
(.I0(result[23]),
.I1(write_enable_reg_n_0),
.I2(\read_input[31]_i_4_n_0 ),
.I3(\read_input[31]_i_5_n_0 ),
.I4(register_a[23]),
.O(\result[23]_i_20_n_0 ));
LUT5 #(
.INIT(32'hFFFB0008))
\result[23]_i_21
(.I0(result[22]),
.I1(write_enable_reg_n_0),
.I2(\read_input[31]_i_4_n_0 ),
.I3(\read_input[31]_i_5_n_0 ),
.I4(register_a[22]),
.O(\result[23]_i_21_n_0 ));
LUT5 #(
.INIT(32'hFFFB0008))
\result[23]_i_22
(.I0(result[21]),
.I1(write_enable_reg_n_0),
.I2(\read_input[31]_i_4_n_0 ),
.I3(\read_input[31]_i_5_n_0 ),
.I4(register_a[21]),
.O(\result[23]_i_22_n_0 ));
LUT5 #(
.INIT(32'hFFFB0008))
\result[23]_i_23
(.I0(result[20]),
.I1(write_enable_reg_n_0),
.I2(\read_input[31]_i_4_n_0 ),
.I3(\read_input[31]_i_5_n_0 ),
.I4(register_a[20]),
.O(\result[23]_i_23_n_0 ));
LUT6 #(
.INIT(64'hFF1D0000FFFFFFFF))
\result[23]_i_3
(.I0(\result[24]_i_5_n_0 ),
.I1(store_data[0]),
.I2(\result[23]_i_5_n_0 ),
.I3(\result[27]_i_8_n_0 ),
.I4(\result[23]_i_6_n_0 ),
.I5(opcode_2[0]),
.O(\result[23]_i_3_n_0 ));
LUT5 #(
.INIT(32'h0A800080))
\result[23]_i_4
(.I0(opcode_2[1]),
.I1(\result_reg[23]_i_7_n_4 ),
.I2(opcode_2[2]),
.I3(opcode_2[3]),
.I4(data5[23]),
.O(\result[23]_i_4_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\result[23]_i_5
(.I0(\result[23]_i_9_n_0 ),
.I1(\result[27]_i_12_n_0 ),
.I2(store_data[1]),
.I3(\result[25]_i_7_n_0 ),
.I4(store_data[2]),
.I5(\result[27]_i_14_n_0 ),
.O(\result[23]_i_5_n_0 ));
LUT6 #(
.INIT(64'hCFC0CFCFCFC5CFC5))
\result[23]_i_6
(.I0(\result_reg[23]_i_10_n_4 ),
.I1(\result[23]_i_11_n_0 ),
.I2(opcode_2[1]),
.I3(opcode_2[4]),
.I4(data7[23]),
.I5(opcode_2[2]),
.O(\result[23]_i_6_n_0 ));
LUT5 #(
.INIT(32'h30BB3088))
\result[23]_i_9
(.I0(\read_input[8]_i_1_n_0 ),
.I1(store_data[3]),
.I2(\read_input[0]_i_1_n_0 ),
.I3(store_data[4]),
.I4(\read_input[16]_i_1_n_0 ),
.O(\result[23]_i_9_n_0 ));
LUT6 #(
.INIT(64'hFFFFF8FF88888888))
\result[24]_i_1
(.I0(\result[27]_i_2_n_0 ),
.I1(load_data[24]),
.I2(\result[24]_i_2_n_0 ),
.I3(\result[24]_i_3_n_0 ),
.I4(\result[24]_i_4_n_0 ),
.I5(\state_reg_n_0_[0] ),
.O(\result[24]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFF54040000))
\result[24]_i_2
(.I0(\result[31]_i_12_n_0 ),
.I1(register_a[24]),
.I2(operand_a1),
.I3(result[24]),
.I4(store_data[24]),
.I5(\result[31]_i_13_n_0 ),
.O(\result[24]_i_2_n_0 ));
LUT6 #(
.INIT(64'hFF470000FFFFFFFF))
\result[24]_i_3
(.I0(\result[24]_i_5_n_0 ),
.I1(store_data[0]),
.I2(\result[25]_i_5_n_0 ),
.I3(\result[27]_i_8_n_0 ),
.I4(\result[24]_i_6_n_0 ),
.I5(opcode_2[0]),
.O(\result[24]_i_3_n_0 ));
LUT5 #(
.INIT(32'h0A800080))
\result[24]_i_4
(.I0(opcode_2[1]),
.I1(\result_reg[27]_i_10_n_7 ),
.I2(opcode_2[2]),
.I3(opcode_2[3]),
.I4(data5[24]),
.O(\result[24]_i_4_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\result[24]_i_5
(.I0(\result[24]_i_7_n_0 ),
.I1(\result[27]_i_16_n_0 ),
.I2(store_data[1]),
.I3(\result[26]_i_7_n_0 ),
.I4(store_data[2]),
.I5(\result[27]_i_18_n_0 ),
.O(\result[24]_i_5_n_0 ));
LUT6 #(
.INIT(64'hCFC0CFCFCFC5CFC5))
\result[24]_i_6
(.I0(\result_reg[31]_i_16_n_7 ),
.I1(\result[24]_i_8_n_0 ),
.I2(opcode_2[1]),
.I3(opcode_2[4]),
.I4(data7[24]),
.I5(opcode_2[2]),
.O(\result[24]_i_6_n_0 ));
LUT5 #(
.INIT(32'h30BB3088))
\result[24]_i_7
(.I0(\read_input[9]_i_1_n_0 ),
.I1(store_data[3]),
.I2(\read_input[1]_i_1_n_0 ),
.I3(store_data[4]),
.I4(\read_input[17]_i_1_n_0 ),
.O(\result[24]_i_7_n_0 ));
LUT6 #(
.INIT(64'h45004547FFFFFFFF))
\result[24]_i_8
(.I0(result[24]),
.I1(operand_b1),
.I2(register_b[24]),
.I3(operand_a1),
.I4(register_a[24]),
.I5(opcode_2[2]),
.O(\result[24]_i_8_n_0 ));
LUT6 #(
.INIT(64'hFFFFF8FF88888888))
\result[25]_i_1
(.I0(\result[27]_i_2_n_0 ),
.I1(load_data[25]),
.I2(\result[25]_i_2_n_0 ),
.I3(\result[25]_i_3_n_0 ),
.I4(\result[25]_i_4_n_0 ),
.I5(\state_reg_n_0_[0] ),
.O(\result[25]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFF54040000))
\result[25]_i_2
(.I0(\result[31]_i_12_n_0 ),
.I1(register_a[25]),
.I2(operand_a1),
.I3(result[25]),
.I4(store_data[25]),
.I5(\result[31]_i_13_n_0 ),
.O(\result[25]_i_2_n_0 ));
LUT6 #(
.INIT(64'hFF470000FFFFFFFF))
\result[25]_i_3
(.I0(\result[25]_i_5_n_0 ),
.I1(store_data[0]),
.I2(\result[26]_i_5_n_0 ),
.I3(\result[27]_i_8_n_0 ),
.I4(\result[25]_i_6_n_0 ),
.I5(opcode_2[0]),
.O(\result[25]_i_3_n_0 ));
LUT5 #(
.INIT(32'h0A800080))
\result[25]_i_4
(.I0(opcode_2[1]),
.I1(\result_reg[27]_i_10_n_6 ),
.I2(opcode_2[2]),
.I3(opcode_2[3]),
.I4(data5[25]),
.O(\result[25]_i_4_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\result[25]_i_5
(.I0(\result[25]_i_7_n_0 ),
.I1(\result[27]_i_14_n_0 ),
.I2(store_data[1]),
.I3(\result[27]_i_12_n_0 ),
.I4(store_data[2]),
.I5(\result[27]_i_13_n_0 ),
.O(\result[25]_i_5_n_0 ));
LUT6 #(
.INIT(64'hCFC0CFCFCFC5CFC5))
\result[25]_i_6
(.I0(\result_reg[31]_i_16_n_6 ),
.I1(\result[25]_i_8_n_0 ),
.I2(opcode_2[1]),
.I3(opcode_2[4]),
.I4(data7[25]),
.I5(opcode_2[2]),
.O(\result[25]_i_6_n_0 ));
LUT5 #(
.INIT(32'h30BB3088))
\result[25]_i_7
(.I0(\read_input[10]_i_1_n_0 ),
.I1(store_data[3]),
.I2(\read_input[2]_i_1_n_0 ),
.I3(store_data[4]),
.I4(\read_input[18]_i_1_n_0 ),
.O(\result[25]_i_7_n_0 ));
LUT6 #(
.INIT(64'h45004547FFFFFFFF))
\result[25]_i_8
(.I0(result[25]),
.I1(operand_b1),
.I2(register_b[25]),
.I3(operand_a1),
.I4(register_a[25]),
.I5(opcode_2[2]),
.O(\result[25]_i_8_n_0 ));
LUT6 #(
.INIT(64'hFFFFF8FF88888888))
\result[26]_i_1
(.I0(\result[27]_i_2_n_0 ),
.I1(load_data[26]),
.I2(\result[26]_i_2_n_0 ),
.I3(\result[26]_i_3_n_0 ),
.I4(\result[26]_i_4_n_0 ),
.I5(\state_reg_n_0_[0] ),
.O(\result[26]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFF54040000))
\result[26]_i_2
(.I0(\result[31]_i_12_n_0 ),
.I1(register_a[26]),
.I2(operand_a1),
.I3(result[26]),
.I4(store_data[26]),
.I5(\result[31]_i_13_n_0 ),
.O(\result[26]_i_2_n_0 ));
LUT6 #(
.INIT(64'hFF1D0000FFFFFFFF))
\result[26]_i_3
(.I0(\result[27]_i_6_n_0 ),
.I1(store_data[0]),
.I2(\result[26]_i_5_n_0 ),
.I3(\result[27]_i_8_n_0 ),
.I4(\result[26]_i_6_n_0 ),
.I5(opcode_2[0]),
.O(\result[26]_i_3_n_0 ));
LUT5 #(
.INIT(32'h0A800080))
\result[26]_i_4
(.I0(opcode_2[1]),
.I1(\result_reg[27]_i_10_n_5 ),
.I2(opcode_2[2]),
.I3(opcode_2[3]),
.I4(data5[26]),
.O(\result[26]_i_4_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\result[26]_i_5
(.I0(\result[26]_i_7_n_0 ),
.I1(\result[27]_i_18_n_0 ),
.I2(store_data[1]),
.I3(\result[27]_i_16_n_0 ),
.I4(store_data[2]),
.I5(\result[27]_i_17_n_0 ),
.O(\result[26]_i_5_n_0 ));
LUT6 #(
.INIT(64'hCFC0CFCFCFC5CFC5))
\result[26]_i_6
(.I0(\result_reg[31]_i_16_n_5 ),
.I1(\result[26]_i_8_n_0 ),
.I2(opcode_2[1]),
.I3(opcode_2[4]),
.I4(data7[26]),
.I5(opcode_2[2]),
.O(\result[26]_i_6_n_0 ));
LUT5 #(
.INIT(32'h30BB3088))
\result[26]_i_7
(.I0(\read_input[11]_i_1_n_0 ),
.I1(store_data[3]),
.I2(\read_input[3]_i_1_n_0 ),
.I3(store_data[4]),
.I4(\read_input[19]_i_1_n_0 ),
.O(\result[26]_i_7_n_0 ));
LUT6 #(
.INIT(64'h45004547FFFFFFFF))
\result[26]_i_8
(.I0(result[26]),
.I1(operand_b1),
.I2(register_b[26]),
.I3(operand_a1),
.I4(register_a[26]),
.I5(opcode_2[2]),
.O(\result[26]_i_8_n_0 ));
LUT6 #(
.INIT(64'hFFFFF8FF88888888))
\result[27]_i_1
(.I0(\result[27]_i_2_n_0 ),
.I1(load_data[27]),
.I2(\result[27]_i_3_n_0 ),
.I3(\result[27]_i_4_n_0 ),
.I4(\result[27]_i_5_n_0 ),
.I5(\state_reg_n_0_[0] ),
.O(\result[27]_i_1_n_0 ));
LUT5 #(
.INIT(32'h30BB3088))
\result[27]_i_12
(.I0(\read_input[12]_i_1_n_0 ),
.I1(store_data[3]),
.I2(\read_input[4]_i_1_n_0 ),
.I3(store_data[4]),
.I4(\read_input[20]_i_1_n_0 ),
.O(\result[27]_i_12_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\result[27]_i_13
(.I0(\read_input[0]_i_1_n_0 ),
.I1(\read_input[16]_i_1_n_0 ),
.I2(store_data[3]),
.I3(\read_input[8]_i_1_n_0 ),
.I4(store_data[4]),
.I5(\read_input[24]_i_1_n_0 ),
.O(\result[27]_i_13_n_0 ));
LUT5 #(
.INIT(32'h30BB3088))
\result[27]_i_14
(.I0(\read_input[14]_i_1_n_0 ),
.I1(store_data[3]),
.I2(\read_input[6]_i_1_n_0 ),
.I3(store_data[4]),
.I4(\read_input[22]_i_1_n_0 ),
.O(\result[27]_i_14_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\result[27]_i_15
(.I0(\read_input[2]_i_1_n_0 ),
.I1(\read_input[18]_i_1_n_0 ),
.I2(store_data[3]),
.I3(\read_input[10]_i_1_n_0 ),
.I4(store_data[4]),
.I5(\read_input[26]_i_1_n_0 ),
.O(\result[27]_i_15_n_0 ));
LUT5 #(
.INIT(32'h30BB3088))
\result[27]_i_16
(.I0(\read_input[13]_i_1_n_0 ),
.I1(store_data[3]),
.I2(\read_input[5]_i_1_n_0 ),
.I3(store_data[4]),
.I4(\read_input[21]_i_1_n_0 ),
.O(\result[27]_i_16_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\result[27]_i_17
(.I0(\read_input[1]_i_1_n_0 ),
.I1(\read_input[17]_i_1_n_0 ),
.I2(store_data[3]),
.I3(\read_input[9]_i_1_n_0 ),
.I4(store_data[4]),
.I5(\read_input[25]_i_1_n_0 ),
.O(\result[27]_i_17_n_0 ));
LUT5 #(
.INIT(32'h30BB3088))
\result[27]_i_18
(.I0(\read_input[15]_i_1_n_0 ),
.I1(store_data[3]),
.I2(\read_input[7]_i_1_n_0 ),
.I3(store_data[4]),
.I4(\read_input[23]_i_1_n_0 ),
.O(\result[27]_i_18_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\result[27]_i_19
(.I0(\read_input[3]_i_1_n_0 ),
.I1(\read_input[19]_i_1_n_0 ),
.I2(store_data[3]),
.I3(\read_input[11]_i_1_n_0 ),
.I4(store_data[4]),
.I5(\read_input[27]_i_1_n_0 ),
.O(\result[27]_i_19_n_0 ));
LUT2 #(
.INIT(4'h2))
\result[27]_i_2
(.I0(\state_reg_n_0_[2] ),
.I1(\state_reg_n_0_[1] ),
.O(\result[27]_i_2_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFFFFFFEFEA))
\result[27]_i_20
(.I0(store_data[29]),
.I1(result[28]),
.I2(operand_b1),
.I3(register_b[28]),
.I4(store_data[31]),
.I5(store_data[30]),
.O(\result[27]_i_20_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFFFFFFFFFE))
\result[27]_i_21
(.I0(store_data[13]),
.I1(store_data[12]),
.I2(store_data[8]),
.I3(store_data[9]),
.I4(store_data[14]),
.I5(store_data[15]),
.O(\result[27]_i_21_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFFFFFFFEFF))
\result[27]_i_22
(.I0(store_data[11]),
.I1(store_data[10]),
.I2(store_data[7]),
.I3(opcode_2[4]),
.I4(store_data[5]),
.I5(store_data[6]),
.O(\result[27]_i_22_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFFFFFFEFEA))
\result[27]_i_23
(.I0(store_data[27]),
.I1(result[26]),
.I2(operand_b1),
.I3(register_b[26]),
.I4(store_data[21]),
.I5(store_data[20]),
.O(\result[27]_i_23_n_0 ));
LUT5 #(
.INIT(32'hFFFACCFA))
\result[27]_i_24
(.I0(register_b[24]),
.I1(result[24]),
.I2(register_b[25]),
.I3(operand_b1),
.I4(result[25]),
.O(\result[27]_i_24_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFFFFFFFFFE))
\result[27]_i_25
(.I0(store_data[23]),
.I1(store_data[22]),
.I2(store_data[18]),
.I3(store_data[19]),
.I4(store_data[16]),
.I5(store_data[17]),
.O(\result[27]_i_25_n_0 ));
LUT6 #(
.INIT(64'h45004547FFFFFFFF))
\result[27]_i_26
(.I0(result[27]),
.I1(operand_b1),
.I2(register_b[27]),
.I3(operand_a1),
.I4(register_a[27]),
.I5(opcode_2[2]),
.O(\result[27]_i_26_n_0 ));
LUT5 #(
.INIT(32'h111E22D2))
\result[27]_i_27
(.I0(register_a[27]),
.I1(operand_a1),
.I2(register_b[27]),
.I3(operand_b1),
.I4(result[27]),
.O(\result[27]_i_27_n_0 ));
LUT5 #(
.INIT(32'h111E22D2))
\result[27]_i_28
(.I0(register_a[26]),
.I1(operand_a1),
.I2(register_b[26]),
.I3(operand_b1),
.I4(result[26]),
.O(\result[27]_i_28_n_0 ));
LUT5 #(
.INIT(32'h111E22D2))
\result[27]_i_29
(.I0(register_a[25]),
.I1(operand_a1),
.I2(register_b[25]),
.I3(operand_b1),
.I4(result[25]),
.O(\result[27]_i_29_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFF44400040))
\result[27]_i_3
(.I0(\result[31]_i_12_n_0 ),
.I1(\read_input[27]_i_1_n_0 ),
.I2(register_b[27]),
.I3(operand_b1),
.I4(result[27]),
.I5(\result[31]_i_13_n_0 ),
.O(\result[27]_i_3_n_0 ));
LUT5 #(
.INIT(32'h111E22D2))
\result[27]_i_30
(.I0(register_a[24]),
.I1(operand_a1),
.I2(register_b[24]),
.I3(operand_b1),
.I4(result[24]),
.O(\result[27]_i_30_n_0 ));
LUT5 #(
.INIT(32'hEDB8ED47))
\result[27]_i_31
(.I0(result[27]),
.I1(operand_b1),
.I2(register_b[27]),
.I3(operand_a1),
.I4(register_a[27]),
.O(\result[27]_i_31_n_0 ));
LUT5 #(
.INIT(32'hEDB8ED47))
\result[27]_i_32
(.I0(result[26]),
.I1(operand_b1),
.I2(register_b[26]),
.I3(operand_a1),
.I4(register_a[26]),
.O(\result[27]_i_32_n_0 ));
LUT5 #(
.INIT(32'hEDB8ED47))
\result[27]_i_33
(.I0(result[25]),
.I1(operand_b1),
.I2(register_b[25]),
.I3(operand_a1),
.I4(register_a[25]),
.O(\result[27]_i_33_n_0 ));
LUT5 #(
.INIT(32'hEDB8ED47))
\result[27]_i_34
(.I0(result[24]),
.I1(operand_b1),
.I2(register_b[24]),
.I3(operand_a1),
.I4(register_a[24]),
.O(\result[27]_i_34_n_0 ));
LUT6 #(
.INIT(64'hFF470000FFFFFFFF))
\result[27]_i_4
(.I0(\result[27]_i_6_n_0 ),
.I1(store_data[0]),
.I2(\result[27]_i_7_n_0 ),
.I3(\result[27]_i_8_n_0 ),
.I4(\result[27]_i_9_n_0 ),
.I5(opcode_2[0]),
.O(\result[27]_i_4_n_0 ));
LUT5 #(
.INIT(32'h0A800080))
\result[27]_i_5
(.I0(opcode_2[1]),
.I1(\result_reg[27]_i_10_n_4 ),
.I2(opcode_2[2]),
.I3(opcode_2[3]),
.I4(data5[27]),
.O(\result[27]_i_5_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\result[27]_i_6
(.I0(\result[27]_i_12_n_0 ),
.I1(\result[27]_i_13_n_0 ),
.I2(store_data[1]),
.I3(\result[27]_i_14_n_0 ),
.I4(store_data[2]),
.I5(\result[27]_i_15_n_0 ),
.O(\result[27]_i_6_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\result[27]_i_7
(.I0(\result[27]_i_16_n_0 ),
.I1(\result[27]_i_17_n_0 ),
.I2(store_data[1]),
.I3(\result[27]_i_18_n_0 ),
.I4(store_data[2]),
.I5(\result[27]_i_19_n_0 ),
.O(\result[27]_i_7_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFFFFFFFFFE))
\result[27]_i_8
(.I0(\result[27]_i_20_n_0 ),
.I1(\result[27]_i_21_n_0 ),
.I2(\result[27]_i_22_n_0 ),
.I3(\result[27]_i_23_n_0 ),
.I4(\result[27]_i_24_n_0 ),
.I5(\result[27]_i_25_n_0 ),
.O(\result[27]_i_8_n_0 ));
LUT6 #(
.INIT(64'hCFC0CFCFCFC5CFC5))
\result[27]_i_9
(.I0(\result_reg[31]_i_16_n_4 ),
.I1(\result[27]_i_26_n_0 ),
.I2(opcode_2[1]),
.I3(opcode_2[4]),
.I4(data7[27]),
.I5(opcode_2[2]),
.O(\result[27]_i_9_n_0 ));
LUT6 #(
.INIT(64'hFFBBAAAAFFFBAAAA))
\result[28]_i_1
(.I0(\result[28]_i_2_n_0 ),
.I1(\result_reg[28]_i_3_n_0 ),
.I2(opcode_2[1]),
.I3(\result[28]_i_4_n_0 ),
.I4(\state_reg_n_0_[0] ),
.I5(\result[28]_i_5_n_0 ),
.O(\result[28]_i_1_n_0 ));
LUT6 #(
.INIT(64'h1F10FFF01F1FFFF0))
\result[28]_i_10
(.I0(store_data[28]),
.I1(\read_input[28]_i_1_n_0 ),
.I2(opcode_2[1]),
.I3(opcode_2[4]),
.I4(opcode_2[2]),
.I5(data7[28]),
.O(\result[28]_i_10_n_0 ));
LUT3 #(
.INIT(8'h20))
\result[28]_i_2
(.I0(load_data[28]),
.I1(\state_reg_n_0_[1] ),
.I2(\state_reg_n_0_[2] ),
.O(\result[28]_i_2_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFF54040000))
\result[28]_i_4
(.I0(\result[31]_i_12_n_0 ),
.I1(register_a[28]),
.I2(operand_a1),
.I3(result[28]),
.I4(store_data[28]),
.I5(\result[31]_i_13_n_0 ),
.O(\result[28]_i_4_n_0 ));
LUT4 #(
.INIT(16'hC7F7))
\result[28]_i_5
(.I0(data5[28]),
.I1(opcode_2[3]),
.I2(opcode_2[2]),
.I3(\result_reg[31]_i_15_n_7 ),
.O(\result[28]_i_5_n_0 ));
LUT6 #(
.INIT(64'hFF1D0000FFFFFFFF))
\result[28]_i_6
(.I0(\result[29]_i_8_n_0 ),
.I1(store_data[0]),
.I2(\result[27]_i_7_n_0 ),
.I3(\result[27]_i_8_n_0 ),
.I4(\result[28]_i_9_n_0 ),
.I5(opcode_2[0]),
.O(\result[28]_i_6_n_0 ));
LUT6 #(
.INIT(64'hFF1D0000FFFFFFFF))
\result[28]_i_7
(.I0(\result[29]_i_8_n_0 ),
.I1(store_data[0]),
.I2(\result[27]_i_7_n_0 ),
.I3(\result[27]_i_8_n_0 ),
.I4(\result[28]_i_10_n_0 ),
.I5(opcode_2[0]),
.O(\result[28]_i_7_n_0 ));
LUT6 #(
.INIT(64'h2002000000002002))
\result[28]_i_8
(.I0(write_enable_reg_n_0),
.I1(\read_input[31]_i_4_n_0 ),
.I2(address_a_2[0]),
.I3(address_z_3[0]),
.I4(address_a_2[3]),
.I5(address_z_3[3]),
.O(operand_a1));
LUT6 #(
.INIT(64'h1F101F1FFFFFFFFF))
\result[28]_i_9
(.I0(store_data[28]),
.I1(\read_input[28]_i_1_n_0 ),
.I2(opcode_2[1]),
.I3(opcode_2[4]),
.I4(data7[28]),
.I5(opcode_2[2]),
.O(\result[28]_i_9_n_0 ));
LUT6 #(
.INIT(64'hFFBBAAAAFFFBAAAA))
\result[29]_i_1
(.I0(\result[29]_i_2_n_0 ),
.I1(\result_reg[29]_i_3_n_0 ),
.I2(opcode_2[1]),
.I3(\result[29]_i_4_n_0 ),
.I4(\state_reg_n_0_[0] ),
.I5(\result[29]_i_5_n_0 ),
.O(\result[29]_i_1_n_0 ));
LUT5 #(
.INIT(32'hB8B8BBB8))
\result[29]_i_10
(.I0(\result[29]_i_11_n_0 ),
.I1(opcode_2[1]),
.I2(opcode_2[4]),
.I3(opcode_2[2]),
.I4(data7[29]),
.O(\result[29]_i_10_n_0 ));
LUT6 #(
.INIT(64'h45004547FFFFFFFF))
\result[29]_i_11
(.I0(result[29]),
.I1(operand_b1),
.I2(register_b[29]),
.I3(operand_a1),
.I4(register_a[29]),
.I5(opcode_2[2]),
.O(\result[29]_i_11_n_0 ));
LUT3 #(
.INIT(8'h20))
\result[29]_i_2
(.I0(load_data[29]),
.I1(\state_reg_n_0_[1] ),
.I2(\state_reg_n_0_[2] ),
.O(\result[29]_i_2_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFF44400040))
\result[29]_i_4
(.I0(\result[31]_i_12_n_0 ),
.I1(\read_input[29]_i_1_n_0 ),
.I2(register_b[29]),
.I3(operand_b1),
.I4(result[29]),
.I5(\result[31]_i_13_n_0 ),
.O(\result[29]_i_4_n_0 ));
LUT4 #(
.INIT(16'hC7F7))
\result[29]_i_5
(.I0(data5[29]),
.I1(opcode_2[3]),
.I2(opcode_2[2]),
.I3(\result_reg[31]_i_15_n_6 ),
.O(\result[29]_i_5_n_0 ));
LUT6 #(
.INIT(64'hFF470000FFFFFFFF))
\result[29]_i_6
(.I0(\result[29]_i_8_n_0 ),
.I1(store_data[0]),
.I2(\result[30]_i_8_n_0 ),
.I3(\result[27]_i_8_n_0 ),
.I4(\result[29]_i_9_n_0 ),
.I5(opcode_2[0]),
.O(\result[29]_i_6_n_0 ));
LUT6 #(
.INIT(64'hFF470000FFFFFFFF))
\result[29]_i_7
(.I0(\result[29]_i_8_n_0 ),
.I1(store_data[0]),
.I2(\result[30]_i_8_n_0 ),
.I3(\result[27]_i_8_n_0 ),
.I4(\result[29]_i_10_n_0 ),
.I5(opcode_2[0]),
.O(\result[29]_i_7_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\result[29]_i_8
(.I0(\result[27]_i_14_n_0 ),
.I1(\result[27]_i_15_n_0 ),
.I2(store_data[1]),
.I3(\result[27]_i_13_n_0 ),
.I4(store_data[2]),
.I5(\result[31]_i_39_n_0 ),
.O(\result[29]_i_8_n_0 ));
LUT5 #(
.INIT(32'hB8BBBBBB))
\result[29]_i_9
(.I0(\result[29]_i_11_n_0 ),
.I1(opcode_2[1]),
.I2(opcode_2[4]),
.I3(data7[29]),
.I4(opcode_2[2]),
.O(\result[29]_i_9_n_0 ));
LUT5 #(
.INIT(32'hFFFFF200))
\result[2]_i_1
(.I0(opcode_2[0]),
.I1(\result[2]_i_2_n_0 ),
.I2(\result[2]_i_3_n_0 ),
.I3(\state_reg_n_0_[0] ),
.I4(\result[2]_i_4_n_0 ),
.O(\result[2]_i_1_n_0 ));
LUT6 #(
.INIT(64'hAA8A8888AA8AAAAA))
\result[2]_i_2
(.I0(\result[2]_i_5_n_0 ),
.I1(\result[27]_i_8_n_0 ),
.I2(\result[2]_i_6_n_0 ),
.I3(store_data[1]),
.I4(store_data[0]),
.I5(\result[3]_i_5_n_0 ),
.O(\result[2]_i_2_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFF2222F222))
\result[2]_i_3
(.I0(address_b_2[2]),
.I1(\result[14]_i_7_n_0 ),
.I2(store_data[2]),
.I3(\read_input[2]_i_1_n_0 ),
.I4(\result[31]_i_12_n_0 ),
.I5(\result[2]_i_7_n_0 ),
.O(\result[2]_i_3_n_0 ));
LUT4 #(
.INIT(16'hE200))
\result[2]_i_4
(.I0(load_data[2]),
.I1(\state_reg_n_0_[1] ),
.I2(OUT1[2]),
.I3(\state_reg_n_0_[2] ),
.O(\result[2]_i_4_n_0 ));
LUT6 #(
.INIT(64'h3030FCFF7777FCFF))
\result[2]_i_5
(.I0(store_data[2]),
.I1(opcode_2[1]),
.I2(opcode_2[4]),
.I3(\result_reg[1]_i_6_n_5 ),
.I4(opcode_2[2]),
.I5(\read_input[2]_i_1_n_0 ),
.O(\result[2]_i_5_n_0 ));
LUT6 #(
.INIT(64'h0000000000005404))
\result[2]_i_6
(.I0(store_data[4]),
.I1(register_a[1]),
.I2(operand_a1),
.I3(result[1]),
.I4(store_data[3]),
.I5(store_data[2]),
.O(\result[2]_i_6_n_0 ));
LUT6 #(
.INIT(64'h33E200E200000000))
\result[2]_i_7
(.I0(data2[2]),
.I1(opcode_2[3]),
.I2(data5[2]),
.I3(opcode_2[2]),
.I4(\result_reg[3]_i_9_n_5 ),
.I5(opcode_2[1]),
.O(\result[2]_i_7_n_0 ));
LUT6 #(
.INIT(64'hFFBBAAAAFFFBAAAA))
\result[30]_i_1
(.I0(\result[30]_i_2_n_0 ),
.I1(\result_reg[30]_i_3_n_0 ),
.I2(opcode_2[1]),
.I3(\result[30]_i_4_n_0 ),
.I4(\state_reg_n_0_[0] ),
.I5(\result[30]_i_5_n_0 ),
.O(\result[30]_i_1_n_0 ));
LUT5 #(
.INIT(32'hB8B8BBB8))
\result[30]_i_10
(.I0(\result[30]_i_11_n_0 ),
.I1(opcode_2[1]),
.I2(opcode_2[4]),
.I3(opcode_2[2]),
.I4(data7[30]),
.O(\result[30]_i_10_n_0 ));
LUT6 #(
.INIT(64'h45004547FFFFFFFF))
\result[30]_i_11
(.I0(result[30]),
.I1(operand_b1),
.I2(register_b[30]),
.I3(operand_a1),
.I4(register_a[30]),
.I5(opcode_2[2]),
.O(\result[30]_i_11_n_0 ));
LUT3 #(
.INIT(8'h20))
\result[30]_i_2
(.I0(load_data[30]),
.I1(\state_reg_n_0_[1] ),
.I2(\state_reg_n_0_[2] ),
.O(\result[30]_i_2_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFF44400040))
\result[30]_i_4
(.I0(\result[31]_i_12_n_0 ),
.I1(\read_input[30]_i_1_n_0 ),
.I2(register_b[30]),
.I3(operand_b1),
.I4(result[30]),
.I5(\result[31]_i_13_n_0 ),
.O(\result[30]_i_4_n_0 ));
LUT4 #(
.INIT(16'hC7F7))
\result[30]_i_5
(.I0(data5[30]),
.I1(opcode_2[3]),
.I2(opcode_2[2]),
.I3(\result_reg[31]_i_15_n_5 ),
.O(\result[30]_i_5_n_0 ));
LUT6 #(
.INIT(64'hFF1D0000FFFFFFFF))
\result[30]_i_6
(.I0(\result[31]_i_22_n_0 ),
.I1(store_data[0]),
.I2(\result[30]_i_8_n_0 ),
.I3(\result[27]_i_8_n_0 ),
.I4(\result[30]_i_9_n_0 ),
.I5(opcode_2[0]),
.O(\result[30]_i_6_n_0 ));
LUT6 #(
.INIT(64'hFF1D0000FFFFFFFF))
\result[30]_i_7
(.I0(\result[31]_i_22_n_0 ),
.I1(store_data[0]),
.I2(\result[30]_i_8_n_0 ),
.I3(\result[27]_i_8_n_0 ),
.I4(\result[30]_i_10_n_0 ),
.I5(opcode_2[0]),
.O(\result[30]_i_7_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\result[30]_i_8
(.I0(\result[27]_i_18_n_0 ),
.I1(\result[27]_i_19_n_0 ),
.I2(store_data[1]),
.I3(\result[27]_i_17_n_0 ),
.I4(store_data[2]),
.I5(\result[31]_i_37_n_0 ),
.O(\result[30]_i_8_n_0 ));
LUT5 #(
.INIT(32'hB8BBBBBB))
\result[30]_i_9
(.I0(\result[30]_i_11_n_0 ),
.I1(opcode_2[1]),
.I2(opcode_2[4]),
.I3(data7[30]),
.I4(opcode_2[2]),
.O(\result[30]_i_9_n_0 ));
LUT5 #(
.INIT(32'h04FF0400))
\result[31]_i_1
(.I0(\state_reg_n_0_[2] ),
.I1(\state_reg_n_0_[1] ),
.I2(\result[31]_i_3_n_0 ),
.I3(\state_reg_n_0_[0] ),
.I4(\result[31]_i_4_n_0 ),
.O(\result[31]_i_1_n_0 ));
LUT6 #(
.INIT(64'hCEFE0000FFFFFFFF))
\result[31]_i_10
(.I0(\result[31]_i_21_n_0 ),
.I1(\result[27]_i_8_n_0 ),
.I2(store_data[0]),
.I3(\result[31]_i_22_n_0 ),
.I4(\result[31]_i_23_n_0 ),
.I5(opcode_2[0]),
.O(\result[31]_i_10_n_0 ));
LUT6 #(
.INIT(64'hCEFE0000FFFFFFFF))
\result[31]_i_11
(.I0(\result[31]_i_21_n_0 ),
.I1(\result[27]_i_8_n_0 ),
.I2(store_data[0]),
.I3(\result[31]_i_22_n_0 ),
.I4(\result[31]_i_24_n_0 ),
.I5(opcode_2[0]),
.O(\result[31]_i_11_n_0 ));
LUT3 #(
.INIT(8'hBF))
\result[31]_i_12
(.I0(opcode_2[0]),
.I1(opcode_2[1]),
.I2(opcode_2[3]),
.O(\result[31]_i_12_n_0 ));
LUT5 #(
.INIT(32'h00000002))
\result[31]_i_13
(.I0(data7[31]),
.I1(opcode_2[2]),
.I2(opcode_2[3]),
.I3(opcode_2[4]),
.I4(opcode_2[0]),
.O(\result[31]_i_13_n_0 ));
LUT5 #(
.INIT(32'hFFFB0008))
\result[31]_i_17
(.I0(result[31]),
.I1(write_enable_reg_n_0),
.I2(\read_input[31]_i_4_n_0 ),
.I3(\read_input[31]_i_5_n_0 ),
.I4(register_a[31]),
.O(\result[31]_i_17_n_0 ));
LUT5 #(
.INIT(32'hFFFB0008))
\result[31]_i_18
(.I0(result[30]),
.I1(write_enable_reg_n_0),
.I2(\read_input[31]_i_4_n_0 ),
.I3(\read_input[31]_i_5_n_0 ),
.I4(register_a[30]),
.O(\result[31]_i_18_n_0 ));
LUT5 #(
.INIT(32'hFFFB0008))
\result[31]_i_19
(.I0(result[29]),
.I1(write_enable_reg_n_0),
.I2(\read_input[31]_i_4_n_0 ),
.I3(\read_input[31]_i_5_n_0 ),
.I4(register_a[29]),
.O(\result[31]_i_19_n_0 ));
LUT6 #(
.INIT(64'hFFBBAAAAFFFBAAAA))
\result[31]_i_2
(.I0(\result[31]_i_5_n_0 ),
.I1(\result_reg[31]_i_6_n_0 ),
.I2(opcode_2[1]),
.I3(\result[31]_i_7_n_0 ),
.I4(\state_reg_n_0_[0] ),
.I5(\result[31]_i_8_n_0 ),
.O(\result[31]_i_2_n_0 ));
LUT5 #(
.INIT(32'hFFFB0008))
\result[31]_i_20
(.I0(result[28]),
.I1(write_enable_reg_n_0),
.I2(\read_input[31]_i_4_n_0 ),
.I3(\read_input[31]_i_5_n_0 ),
.I4(register_a[28]),
.O(\result[31]_i_20_n_0 ));
LUT6 #(
.INIT(64'h505F3030505F3F3F))
\result[31]_i_21
(.I0(\result[27]_i_17_n_0 ),
.I1(\result[31]_i_37_n_0 ),
.I2(store_data[1]),
.I3(\result[27]_i_19_n_0 ),
.I4(store_data[2]),
.I5(\result[31]_i_38_n_0 ),
.O(\result[31]_i_21_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\result[31]_i_22
(.I0(\result[27]_i_13_n_0 ),
.I1(\result[31]_i_39_n_0 ),
.I2(store_data[1]),
.I3(\result[27]_i_15_n_0 ),
.I4(store_data[2]),
.I5(\result[31]_i_40_n_0 ),
.O(\result[31]_i_22_n_0 ));
LUT5 #(
.INIT(32'hB8BBBBBB))
\result[31]_i_23
(.I0(\result[31]_i_41_n_0 ),
.I1(opcode_2[1]),
.I2(opcode_2[4]),
.I3(data7[31]),
.I4(opcode_2[2]),
.O(\result[31]_i_23_n_0 ));
LUT5 #(
.INIT(32'hB8B8BBB8))
\result[31]_i_24
(.I0(\result[31]_i_41_n_0 ),
.I1(opcode_2[1]),
.I2(opcode_2[4]),
.I3(opcode_2[2]),
.I4(data7[31]),
.O(\result[31]_i_24_n_0 ));
LUT5 #(
.INIT(32'hEDB8ED47))
\result[31]_i_25
(.I0(result[31]),
.I1(operand_b1),
.I2(register_b[31]),
.I3(operand_a1),
.I4(register_a[31]),
.O(\result[31]_i_25_n_0 ));
LUT5 #(
.INIT(32'hEDB8ED47))
\result[31]_i_26
(.I0(result[30]),
.I1(operand_b1),
.I2(register_b[30]),
.I3(operand_a1),
.I4(register_a[30]),
.O(\result[31]_i_26_n_0 ));
LUT5 #(
.INIT(32'hEDB8ED47))
\result[31]_i_27
(.I0(result[29]),
.I1(operand_b1),
.I2(register_b[29]),
.I3(operand_a1),
.I4(register_a[29]),
.O(\result[31]_i_27_n_0 ));
LUT5 #(
.INIT(32'hEDB8ED47))
\result[31]_i_28
(.I0(result[28]),
.I1(operand_b1),
.I2(register_b[28]),
.I3(operand_a1),
.I4(register_a[28]),
.O(\result[31]_i_28_n_0 ));
LUT5 #(
.INIT(32'h111E22D2))
\result[31]_i_29
(.I0(register_a[31]),
.I1(operand_a1),
.I2(register_b[31]),
.I3(operand_b1),
.I4(result[31]),
.O(\result[31]_i_29_n_0 ));
LUT5 #(
.INIT(32'hBABCAF98))
\result[31]_i_3
(.I0(opcode_2[4]),
.I1(opcode_2[3]),
.I2(opcode_2[2]),
.I3(opcode_2[1]),
.I4(opcode_2[0]),
.O(\result[31]_i_3_n_0 ));
LUT5 #(
.INIT(32'h111E22D2))
\result[31]_i_30
(.I0(register_a[30]),
.I1(operand_a1),
.I2(register_b[30]),
.I3(operand_b1),
.I4(result[30]),
.O(\result[31]_i_30_n_0 ));
LUT5 #(
.INIT(32'h111E22D2))
\result[31]_i_31
(.I0(register_a[29]),
.I1(operand_a1),
.I2(register_b[29]),
.I3(operand_b1),
.I4(result[29]),
.O(\result[31]_i_31_n_0 ));
LUT5 #(
.INIT(32'h111E22D2))
\result[31]_i_32
(.I0(register_a[28]),
.I1(operand_a1),
.I2(register_b[28]),
.I3(operand_b1),
.I4(result[28]),
.O(\result[31]_i_32_n_0 ));
LUT5 #(
.INIT(32'hFFFB0008))
\result[31]_i_33
(.I0(result[27]),
.I1(write_enable_reg_n_0),
.I2(\read_input[31]_i_4_n_0 ),
.I3(\read_input[31]_i_5_n_0 ),
.I4(register_a[27]),
.O(\result[31]_i_33_n_0 ));
LUT5 #(
.INIT(32'hFFFB0008))
\result[31]_i_34
(.I0(result[26]),
.I1(write_enable_reg_n_0),
.I2(\read_input[31]_i_4_n_0 ),
.I3(\read_input[31]_i_5_n_0 ),
.I4(register_a[26]),
.O(\result[31]_i_34_n_0 ));
LUT5 #(
.INIT(32'hFFFB0008))
\result[31]_i_35
(.I0(result[25]),
.I1(write_enable_reg_n_0),
.I2(\read_input[31]_i_4_n_0 ),
.I3(\read_input[31]_i_5_n_0 ),
.I4(register_a[25]),
.O(\result[31]_i_35_n_0 ));
LUT5 #(
.INIT(32'hFFFB0008))
\result[31]_i_36
(.I0(result[24]),
.I1(write_enable_reg_n_0),
.I2(\read_input[31]_i_4_n_0 ),
.I3(\read_input[31]_i_5_n_0 ),
.I4(register_a[24]),
.O(\result[31]_i_36_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\result[31]_i_37
(.I0(\read_input[5]_i_1_n_0 ),
.I1(\read_input[21]_i_1_n_0 ),
.I2(store_data[3]),
.I3(\read_input[13]_i_1_n_0 ),
.I4(store_data[4]),
.I5(\read_input[29]_i_1_n_0 ),
.O(\result[31]_i_37_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\result[31]_i_38
(.I0(\read_input[7]_i_1_n_0 ),
.I1(\read_input[23]_i_1_n_0 ),
.I2(store_data[3]),
.I3(\read_input[15]_i_1_n_0 ),
.I4(store_data[4]),
.I5(\read_input[31]_i_2_n_0 ),
.O(\result[31]_i_38_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\result[31]_i_39
(.I0(\read_input[4]_i_1_n_0 ),
.I1(\read_input[20]_i_1_n_0 ),
.I2(store_data[3]),
.I3(\read_input[12]_i_1_n_0 ),
.I4(store_data[4]),
.I5(\read_input[28]_i_1_n_0 ),
.O(\result[31]_i_39_n_0 ));
LUT5 #(
.INIT(32'hD5005500))
\result[31]_i_4
(.I0(\state_reg_n_0_[1] ),
.I1(OUT1_STB),
.I2(OUT1_ACK),
.I3(\state_reg_n_0_[2] ),
.I4(\s_input_rs232_in_ack[0]_i_2_n_0 ),
.O(\result[31]_i_4_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\result[31]_i_40
(.I0(\read_input[6]_i_1_n_0 ),
.I1(\read_input[22]_i_1_n_0 ),
.I2(store_data[3]),
.I3(\read_input[14]_i_1_n_0 ),
.I4(store_data[4]),
.I5(\read_input[30]_i_1_n_0 ),
.O(\result[31]_i_40_n_0 ));
LUT6 #(
.INIT(64'h45004547FFFFFFFF))
\result[31]_i_41
(.I0(result[31]),
.I1(operand_b1),
.I2(register_b[31]),
.I3(operand_a1),
.I4(register_a[31]),
.I5(opcode_2[2]),
.O(\result[31]_i_41_n_0 ));
LUT3 #(
.INIT(8'h20))
\result[31]_i_5
(.I0(load_data[31]),
.I1(\state_reg_n_0_[1] ),
.I2(\state_reg_n_0_[2] ),
.O(\result[31]_i_5_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFF44400040))
\result[31]_i_7
(.I0(\result[31]_i_12_n_0 ),
.I1(\read_input[31]_i_2_n_0 ),
.I2(register_b[31]),
.I3(operand_b1),
.I4(result[31]),
.I5(\result[31]_i_13_n_0 ),
.O(\result[31]_i_7_n_0 ));
LUT4 #(
.INIT(16'hC7F7))
\result[31]_i_8
(.I0(data5[31]),
.I1(opcode_2[3]),
.I2(opcode_2[2]),
.I3(\result_reg[31]_i_15_n_4 ),
.O(\result[31]_i_8_n_0 ));
LUT4 #(
.INIT(16'hFFD0))
\result[3]_i_1
(.I0(\result[3]_i_2_n_0 ),
.I1(\result[3]_i_3_n_0 ),
.I2(\state_reg_n_0_[0] ),
.I3(\result[3]_i_4_n_0 ),
.O(\result[3]_i_1_n_0 ));
LUT5 #(
.INIT(32'hEEE1DD2D))
\result[3]_i_10
(.I0(register_a[3]),
.I1(operand_a1),
.I2(register_b[3]),
.I3(operand_b1),
.I4(result[3]),
.O(\result[3]_i_10_n_0 ));
LUT5 #(
.INIT(32'hEEE1DD2D))
\result[3]_i_11
(.I0(register_a[2]),
.I1(operand_a1),
.I2(register_b[2]),
.I3(operand_b1),
.I4(result[2]),
.O(\result[3]_i_11_n_0 ));
LUT4 #(
.INIT(16'hE21D))
\result[3]_i_12
(.I0(register_a[1]),
.I1(operand_a1),
.I2(result[1]),
.I3(store_data[1]),
.O(\result[3]_i_12_n_0 ));
LUT4 #(
.INIT(16'hE21D))
\result[3]_i_13
(.I0(register_a[0]),
.I1(operand_a1),
.I2(result[0]),
.I3(store_data[0]),
.O(\result[3]_i_13_n_0 ));
LUT5 #(
.INIT(32'h124712B8))
\result[3]_i_14
(.I0(result[3]),
.I1(operand_b1),
.I2(register_b[3]),
.I3(operand_a1),
.I4(register_a[3]),
.O(\result[3]_i_14_n_0 ));
LUT5 #(
.INIT(32'h124712B8))
\result[3]_i_15
(.I0(result[2]),
.I1(operand_b1),
.I2(register_b[2]),
.I3(operand_a1),
.I4(register_a[2]),
.O(\result[3]_i_15_n_0 ));
LUT4 #(
.INIT(16'h656A))
\result[3]_i_16
(.I0(store_data[1]),
.I1(result[1]),
.I2(operand_a1),
.I3(register_a[1]),
.O(\result[3]_i_16_n_0 ));
LUT4 #(
.INIT(16'h656A))
\result[3]_i_17
(.I0(store_data[0]),
.I1(result[0]),
.I2(operand_a1),
.I3(register_a[0]),
.O(\result[3]_i_17_n_0 ));
LUT6 #(
.INIT(64'hFF470000FFFFFFFF))
\result[3]_i_2
(.I0(\result[3]_i_5_n_0 ),
.I1(store_data[0]),
.I2(\result[4]_i_5_n_0 ),
.I3(\result[27]_i_8_n_0 ),
.I4(\result[3]_i_6_n_0 ),
.I5(opcode_2[0]),
.O(\result[3]_i_2_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFF2222F222))
\result[3]_i_3
(.I0(address_b_2[3]),
.I1(\result[14]_i_7_n_0 ),
.I2(store_data[3]),
.I3(\read_input[3]_i_1_n_0 ),
.I4(\result[31]_i_12_n_0 ),
.I5(\result[3]_i_7_n_0 ),
.O(\result[3]_i_3_n_0 ));
LUT4 #(
.INIT(16'hE200))
\result[3]_i_4
(.I0(load_data[3]),
.I1(\state_reg_n_0_[1] ),
.I2(OUT1[3]),
.I3(\state_reg_n_0_[2] ),
.O(\result[3]_i_4_n_0 ));
LUT6 #(
.INIT(64'h0000000000000B08))
\result[3]_i_5
(.I0(\read_input[0]_i_1_n_0 ),
.I1(store_data[1]),
.I2(store_data[3]),
.I3(\read_input[2]_i_1_n_0 ),
.I4(store_data[4]),
.I5(store_data[2]),
.O(\result[3]_i_5_n_0 ));
LUT6 #(
.INIT(64'h3030FCFF7777FCFF))
\result[3]_i_6
(.I0(store_data[3]),
.I1(opcode_2[1]),
.I2(opcode_2[4]),
.I3(\result_reg[1]_i_6_n_4 ),
.I4(opcode_2[2]),
.I5(\read_input[3]_i_1_n_0 ),
.O(\result[3]_i_6_n_0 ));
LUT6 #(
.INIT(64'h33E200E200000000))
\result[3]_i_7
(.I0(data2[3]),
.I1(opcode_2[3]),
.I2(data5[3]),
.I3(opcode_2[2]),
.I4(\result_reg[3]_i_9_n_4 ),
.I5(opcode_2[1]),
.O(\result[3]_i_7_n_0 ));
LUT4 #(
.INIT(16'hFFD0))
\result[4]_i_1
(.I0(\result[4]_i_2_n_0 ),
.I1(\result[4]_i_3_n_0 ),
.I2(\state_reg_n_0_[0] ),
.I3(\result[4]_i_4_n_0 ),
.O(\result[4]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFF1D0000FFFFFFFF))
\result[4]_i_2
(.I0(\result[5]_i_5_n_0 ),
.I1(store_data[0]),
.I2(\result[4]_i_5_n_0 ),
.I3(\result[27]_i_8_n_0 ),
.I4(\result[4]_i_6_n_0 ),
.I5(opcode_2[0]),
.O(\result[4]_i_2_n_0 ));
LUT6 #(
.INIT(64'hAEAEAEAEFFAEAEAE))
\result[4]_i_3
(.I0(\result[4]_i_7_n_0 ),
.I1(data7[20]),
.I2(\result[14]_i_7_n_0 ),
.I3(store_data[4]),
.I4(\read_input[4]_i_1_n_0 ),
.I5(\result[31]_i_12_n_0 ),
.O(\result[4]_i_3_n_0 ));
LUT4 #(
.INIT(16'hE200))
\result[4]_i_4
(.I0(load_data[4]),
.I1(\state_reg_n_0_[1] ),
.I2(OUT1[4]),
.I3(\state_reg_n_0_[2] ),
.O(\result[4]_i_4_n_0 ));
LUT6 #(
.INIT(64'h0000000000000B08))
\result[4]_i_5
(.I0(\read_input[1]_i_1_n_0 ),
.I1(store_data[1]),
.I2(store_data[3]),
.I3(\read_input[3]_i_1_n_0 ),
.I4(store_data[4]),
.I5(store_data[2]),
.O(\result[4]_i_5_n_0 ));
LUT6 #(
.INIT(64'h3030FCFF7777FCFF))
\result[4]_i_6
(.I0(store_data[4]),
.I1(opcode_2[1]),
.I2(opcode_2[4]),
.I3(\result_reg[7]_i_9_n_7 ),
.I4(opcode_2[2]),
.I5(\read_input[4]_i_1_n_0 ),
.O(\result[4]_i_6_n_0 ));
LUT6 #(
.INIT(64'h33E200E200000000))
\result[4]_i_7
(.I0(data2[4]),
.I1(opcode_2[3]),
.I2(data5[4]),
.I3(opcode_2[2]),
.I4(\result_reg[7]_i_11_n_7 ),
.I5(opcode_2[1]),
.O(\result[4]_i_7_n_0 ));
LUT4 #(
.INIT(16'hFFD0))
\result[5]_i_1
(.I0(\result[5]_i_2_n_0 ),
.I1(\result[5]_i_3_n_0 ),
.I2(\state_reg_n_0_[0] ),
.I3(\result[5]_i_4_n_0 ),
.O(\result[5]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFF1D0000FFFFFFFF))
\result[5]_i_2
(.I0(\result[6]_i_5_n_0 ),
.I1(store_data[0]),
.I2(\result[5]_i_5_n_0 ),
.I3(\result[27]_i_8_n_0 ),
.I4(\result[5]_i_6_n_0 ),
.I5(opcode_2[0]),
.O(\result[5]_i_2_n_0 ));
LUT6 #(
.INIT(64'hAAEAAAEAFFFFAAEA))
\result[5]_i_3
(.I0(\result[5]_i_7_n_0 ),
.I1(store_data[5]),
.I2(\read_input[5]_i_1_n_0 ),
.I3(\result[31]_i_12_n_0 ),
.I4(data7[21]),
.I5(\result[14]_i_7_n_0 ),
.O(\result[5]_i_3_n_0 ));
LUT4 #(
.INIT(16'hE200))
\result[5]_i_4
(.I0(load_data[5]),
.I1(\state_reg_n_0_[1] ),
.I2(OUT1[5]),
.I3(\state_reg_n_0_[2] ),
.O(\result[5]_i_4_n_0 ));
LUT6 #(
.INIT(64'h0004FFFF00040000))
\result[5]_i_5
(.I0(store_data[3]),
.I1(\read_input[2]_i_1_n_0 ),
.I2(store_data[4]),
.I3(store_data[2]),
.I4(store_data[1]),
.I5(\result[7]_i_8_n_0 ),
.O(\result[5]_i_5_n_0 ));
LUT6 #(
.INIT(64'h3030FCFF7777FCFF))
\result[5]_i_6
(.I0(store_data[5]),
.I1(opcode_2[1]),
.I2(opcode_2[4]),
.I3(\result_reg[7]_i_9_n_6 ),
.I4(opcode_2[2]),
.I5(\read_input[5]_i_1_n_0 ),
.O(\result[5]_i_6_n_0 ));
LUT6 #(
.INIT(64'h33E200E200000000))
\result[5]_i_7
(.I0(data2[5]),
.I1(opcode_2[3]),
.I2(data5[5]),
.I3(opcode_2[2]),
.I4(\result_reg[7]_i_11_n_6 ),
.I5(opcode_2[1]),
.O(\result[5]_i_7_n_0 ));
LUT4 #(
.INIT(16'hFFD0))
\result[6]_i_1
(.I0(\result[6]_i_2_n_0 ),
.I1(\result[6]_i_3_n_0 ),
.I2(\state_reg_n_0_[0] ),
.I3(\result[6]_i_4_n_0 ),
.O(\result[6]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFF1D0000FFFFFFFF))
\result[6]_i_2
(.I0(\result[7]_i_5_n_0 ),
.I1(store_data[0]),
.I2(\result[6]_i_5_n_0 ),
.I3(\result[27]_i_8_n_0 ),
.I4(\result[6]_i_6_n_0 ),
.I5(opcode_2[0]),
.O(\result[6]_i_2_n_0 ));
LUT6 #(
.INIT(64'hAEAEAEAEFFAEAEAE))
\result[6]_i_3
(.I0(\result[6]_i_7_n_0 ),
.I1(data7[22]),
.I2(\result[14]_i_7_n_0 ),
.I3(store_data[6]),
.I4(\read_input[6]_i_1_n_0 ),
.I5(\result[31]_i_12_n_0 ),
.O(\result[6]_i_3_n_0 ));
LUT4 #(
.INIT(16'hE200))
\result[6]_i_4
(.I0(load_data[6]),
.I1(\state_reg_n_0_[1] ),
.I2(OUT1[6]),
.I3(\state_reg_n_0_[2] ),
.O(\result[6]_i_4_n_0 ));
LUT6 #(
.INIT(64'h0004FFFF00040000))
\result[6]_i_5
(.I0(store_data[3]),
.I1(\read_input[3]_i_1_n_0 ),
.I2(store_data[4]),
.I3(store_data[2]),
.I4(store_data[1]),
.I5(\result[8]_i_7_n_0 ),
.O(\result[6]_i_5_n_0 ));
LUT6 #(
.INIT(64'h3030FCFF7777FCFF))
\result[6]_i_6
(.I0(store_data[6]),
.I1(opcode_2[1]),
.I2(opcode_2[4]),
.I3(\result_reg[7]_i_9_n_5 ),
.I4(opcode_2[2]),
.I5(\read_input[6]_i_1_n_0 ),
.O(\result[6]_i_6_n_0 ));
LUT6 #(
.INIT(64'h33E200E200000000))
\result[6]_i_7
(.I0(data2[6]),
.I1(opcode_2[3]),
.I2(data5[6]),
.I3(opcode_2[2]),
.I4(\result_reg[7]_i_11_n_5 ),
.I5(opcode_2[1]),
.O(\result[6]_i_7_n_0 ));
LUT4 #(
.INIT(16'hFFD0))
\result[7]_i_1
(.I0(\result[7]_i_2_n_0 ),
.I1(\result[7]_i_3_n_0 ),
.I2(\state_reg_n_0_[0] ),
.I3(\result[7]_i_4_n_0 ),
.O(\result[7]_i_1_n_0 ));
LUT4 #(
.INIT(16'h1DE2))
\result[7]_i_12
(.I0(register_a[7]),
.I1(operand_a1),
.I2(result[7]),
.I3(data7[23]),
.O(\result[7]_i_12_n_0 ));
LUT4 #(
.INIT(16'h1DE2))
\result[7]_i_13
(.I0(register_a[6]),
.I1(operand_a1),
.I2(result[6]),
.I3(data7[22]),
.O(\result[7]_i_13_n_0 ));
LUT4 #(
.INIT(16'h1DE2))
\result[7]_i_14
(.I0(register_a[5]),
.I1(operand_a1),
.I2(result[5]),
.I3(data7[21]),
.O(\result[7]_i_14_n_0 ));
LUT4 #(
.INIT(16'h1DE2))
\result[7]_i_15
(.I0(register_a[4]),
.I1(operand_a1),
.I2(result[4]),
.I3(data7[20]),
.O(\result[7]_i_15_n_0 ));
LUT5 #(
.INIT(32'hEEE1DD2D))
\result[7]_i_16
(.I0(register_a[7]),
.I1(operand_a1),
.I2(register_b[7]),
.I3(operand_b1),
.I4(result[7]),
.O(\result[7]_i_16_n_0 ));
LUT5 #(
.INIT(32'hEEE1DD2D))
\result[7]_i_17
(.I0(register_a[6]),
.I1(operand_a1),
.I2(register_b[6]),
.I3(operand_b1),
.I4(result[6]),
.O(\result[7]_i_17_n_0 ));
LUT5 #(
.INIT(32'hEEE1DD2D))
\result[7]_i_18
(.I0(register_a[5]),
.I1(operand_a1),
.I2(register_b[5]),
.I3(operand_b1),
.I4(result[5]),
.O(\result[7]_i_18_n_0 ));
LUT5 #(
.INIT(32'hEEE1DD2D))
\result[7]_i_19
(.I0(register_a[4]),
.I1(operand_a1),
.I2(register_b[4]),
.I3(operand_b1),
.I4(result[4]),
.O(\result[7]_i_19_n_0 ));
LUT6 #(
.INIT(64'hFF470000FFFFFFFF))
\result[7]_i_2
(.I0(\result[7]_i_5_n_0 ),
.I1(store_data[0]),
.I2(\result[8]_i_4_n_0 ),
.I3(\result[27]_i_8_n_0 ),
.I4(\result[7]_i_6_n_0 ),
.I5(opcode_2[0]),
.O(\result[7]_i_2_n_0 ));
LUT5 #(
.INIT(32'h124712B8))
\result[7]_i_20
(.I0(result[7]),
.I1(operand_b1),
.I2(register_b[7]),
.I3(operand_a1),
.I4(register_a[7]),
.O(\result[7]_i_20_n_0 ));
LUT5 #(
.INIT(32'h124712B8))
\result[7]_i_21
(.I0(result[6]),
.I1(operand_b1),
.I2(register_b[6]),
.I3(operand_a1),
.I4(register_a[6]),
.O(\result[7]_i_21_n_0 ));
LUT5 #(
.INIT(32'h124712B8))
\result[7]_i_22
(.I0(result[5]),
.I1(operand_b1),
.I2(register_b[5]),
.I3(operand_a1),
.I4(register_a[5]),
.O(\result[7]_i_22_n_0 ));
LUT5 #(
.INIT(32'h124712B8))
\result[7]_i_23
(.I0(result[4]),
.I1(operand_b1),
.I2(register_b[4]),
.I3(operand_a1),
.I4(register_a[4]),
.O(\result[7]_i_23_n_0 ));
LUT6 #(
.INIT(64'hAEAEAEAEFFAEAEAE))
\result[7]_i_3
(.I0(\result[7]_i_7_n_0 ),
.I1(data7[23]),
.I2(\result[14]_i_7_n_0 ),
.I3(store_data[7]),
.I4(\read_input[7]_i_1_n_0 ),
.I5(\result[31]_i_12_n_0 ),
.O(\result[7]_i_3_n_0 ));
LUT4 #(
.INIT(16'hE200))
\result[7]_i_4
(.I0(load_data[7]),
.I1(\state_reg_n_0_[1] ),
.I2(OUT1[7]),
.I3(\state_reg_n_0_[2] ),
.O(\result[7]_i_4_n_0 ));
LUT3 #(
.INIT(8'hB8))
\result[7]_i_5
(.I0(\result[7]_i_8_n_0 ),
.I1(store_data[1]),
.I2(\result[9]_i_7_n_0 ),
.O(\result[7]_i_5_n_0 ));
LUT6 #(
.INIT(64'h3030FCFF7777FCFF))
\result[7]_i_6
(.I0(store_data[7]),
.I1(opcode_2[1]),
.I2(opcode_2[4]),
.I3(\result_reg[7]_i_9_n_4 ),
.I4(opcode_2[2]),
.I5(\read_input[7]_i_1_n_0 ),
.O(\result[7]_i_6_n_0 ));
LUT6 #(
.INIT(64'h33E200E200000000))
\result[7]_i_7
(.I0(data2[7]),
.I1(opcode_2[3]),
.I2(data5[7]),
.I3(opcode_2[2]),
.I4(\result_reg[7]_i_11_n_4 ),
.I5(opcode_2[1]),
.O(\result[7]_i_7_n_0 ));
LUT5 #(
.INIT(32'h00000B08))
\result[7]_i_8
(.I0(\read_input[0]_i_1_n_0 ),
.I1(store_data[2]),
.I2(store_data[4]),
.I3(\read_input[4]_i_1_n_0 ),
.I4(store_data[3]),
.O(\result[7]_i_8_n_0 ));
LUT6 #(
.INIT(64'hFFFF20FF20202020))
\result[8]_i_1
(.I0(\state_reg_n_0_[2] ),
.I1(\state_reg_n_0_[1] ),
.I2(load_data[8]),
.I3(\result[8]_i_2_n_0 ),
.I4(\result[8]_i_3_n_0 ),
.I5(\state_reg_n_0_[0] ),
.O(\result[8]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFF1D0000FFFFFFFF))
\result[8]_i_2
(.I0(\result[9]_i_4_n_0 ),
.I1(store_data[0]),
.I2(\result[8]_i_4_n_0 ),
.I3(\result[27]_i_8_n_0 ),
.I4(\result[8]_i_5_n_0 ),
.I5(opcode_2[0]),
.O(\result[8]_i_2_n_0 ));
LUT6 #(
.INIT(64'hAAEAAAEAFFFFAAEA))
\result[8]_i_3
(.I0(\result[8]_i_6_n_0 ),
.I1(store_data[8]),
.I2(\read_input[8]_i_1_n_0 ),
.I3(\result[31]_i_12_n_0 ),
.I4(data7[24]),
.I5(\result[14]_i_7_n_0 ),
.O(\result[8]_i_3_n_0 ));
LUT3 #(
.INIT(8'hB8))
\result[8]_i_4
(.I0(\result[8]_i_7_n_0 ),
.I1(store_data[1]),
.I2(\result[10]_i_7_n_0 ),
.O(\result[8]_i_4_n_0 ));
LUT6 #(
.INIT(64'h3030FCFF7777FCFF))
\result[8]_i_5
(.I0(store_data[8]),
.I1(opcode_2[1]),
.I2(opcode_2[4]),
.I3(\result_reg[11]_i_8_n_7 ),
.I4(opcode_2[2]),
.I5(\read_input[8]_i_1_n_0 ),
.O(\result[8]_i_5_n_0 ));
LUT6 #(
.INIT(64'h33E200E200000000))
\result[8]_i_6
(.I0(data2[8]),
.I1(opcode_2[3]),
.I2(data5[8]),
.I3(opcode_2[2]),
.I4(\result_reg[15]_i_16_n_7 ),
.I5(opcode_2[1]),
.O(\result[8]_i_6_n_0 ));
LUT5 #(
.INIT(32'h00000B08))
\result[8]_i_7
(.I0(\read_input[1]_i_1_n_0 ),
.I1(store_data[2]),
.I2(store_data[4]),
.I3(\read_input[5]_i_1_n_0 ),
.I4(store_data[3]),
.O(\result[8]_i_7_n_0 ));
LUT6 #(
.INIT(64'hFFFF20FF20202020))
\result[9]_i_1
(.I0(\state_reg_n_0_[2] ),
.I1(\state_reg_n_0_[1] ),
.I2(load_data[9]),
.I3(\result[9]_i_2_n_0 ),
.I4(\result[9]_i_3_n_0 ),
.I5(\state_reg_n_0_[0] ),
.O(\result[9]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFF470000FFFFFFFF))
\result[9]_i_2
(.I0(\result[9]_i_4_n_0 ),
.I1(store_data[0]),
.I2(\result[10]_i_4_n_0 ),
.I3(\result[27]_i_8_n_0 ),
.I4(\result[9]_i_5_n_0 ),
.I5(opcode_2[0]),
.O(\result[9]_i_2_n_0 ));
LUT6 #(
.INIT(64'hAAEAAAEAFFFFAAEA))
\result[9]_i_3
(.I0(\result[9]_i_6_n_0 ),
.I1(store_data[9]),
.I2(\read_input[9]_i_1_n_0 ),
.I3(\result[31]_i_12_n_0 ),
.I4(data7[25]),
.I5(\result[14]_i_7_n_0 ),
.O(\result[9]_i_3_n_0 ));
LUT3 #(
.INIT(8'hB8))
\result[9]_i_4
(.I0(\result[9]_i_7_n_0 ),
.I1(store_data[1]),
.I2(\result[11]_i_7_n_0 ),
.O(\result[9]_i_4_n_0 ));
LUT6 #(
.INIT(64'h3030FCFF7777FCFF))
\result[9]_i_5
(.I0(store_data[9]),
.I1(opcode_2[1]),
.I2(opcode_2[4]),
.I3(\result_reg[11]_i_8_n_6 ),
.I4(opcode_2[2]),
.I5(\read_input[9]_i_1_n_0 ),
.O(\result[9]_i_5_n_0 ));
LUT6 #(
.INIT(64'h33E200E200000000))
\result[9]_i_6
(.I0(data2[9]),
.I1(opcode_2[3]),
.I2(data5[9]),
.I3(opcode_2[2]),
.I4(\result_reg[15]_i_16_n_6 ),
.I5(opcode_2[1]),
.O(\result[9]_i_6_n_0 ));
LUT5 #(
.INIT(32'h00000B08))
\result[9]_i_7
(.I0(\read_input[2]_i_1_n_0 ),
.I1(store_data[2]),
.I2(store_data[4]),
.I3(\read_input[6]_i_1_n_0 ),
.I4(store_data[3]),
.O(\result[9]_i_7_n_0 ));
FDRE \result_reg[0]
(.C(ETH_CLK_OBUF),
.CE(\result[31]_i_1_n_0 ),
.D(\result[0]_i_1_n_0 ),
.Q(result[0]),
.R(INTERNAL_RST_reg));
CARRY4 \result_reg[0]_i_10
(.CI(\result_reg[0]_i_23_n_0 ),
.CO({data12,\NLW_result_reg[0]_i_10_CO_UNCONNECTED [2:0]}),
.CYINIT(1'b0),
.DI({\result[0]_i_24_n_0 ,\result[0]_i_16_n_0 ,\result[0]_i_17_n_0 ,\result[0]_i_18_n_0 }),
.O(\NLW_result_reg[0]_i_10_O_UNCONNECTED [3:0]),
.S({\result[0]_i_25_n_0 ,\result[0]_i_26_n_0 ,\result[0]_i_27_n_0 ,\result[0]_i_28_n_0 }));
CARRY4 \result_reg[0]_i_12
(.CI(\result_reg[0]_i_29_n_0 ),
.CO({\NLW_result_reg[0]_i_12_CO_UNCONNECTED [3],data4,\NLW_result_reg[0]_i_12_CO_UNCONNECTED [1:0]}),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(\NLW_result_reg[0]_i_12_O_UNCONNECTED [3:0]),
.S({1'b0,\result[0]_i_30_n_0 ,\result[0]_i_31_n_0 ,\result[0]_i_32_n_0 }));
CARRY4 \result_reg[0]_i_13
(.CI(\result_reg[0]_i_33_n_0 ),
.CO({data6,\NLW_result_reg[0]_i_13_CO_UNCONNECTED [2:0]}),
.CYINIT(1'b0),
.DI({\result[0]_i_24_n_0 ,\result[0]_i_16_n_0 ,\result[0]_i_17_n_0 ,\result[0]_i_18_n_0 }),
.O(\NLW_result_reg[0]_i_13_O_UNCONNECTED [3:0]),
.S({\result[0]_i_34_n_0 ,\result[0]_i_35_n_0 ,\result[0]_i_36_n_0 ,\result[0]_i_37_n_0 }));
CARRY4 \result_reg[0]_i_14
(.CI(\result_reg[0]_i_38_n_0 ),
.CO({\result_reg[0]_i_14_n_0 ,\NLW_result_reg[0]_i_14_CO_UNCONNECTED [2:0]}),
.CYINIT(1'b0),
.DI({\result[0]_i_39_n_0 ,\result[0]_i_40_n_0 ,\result[0]_i_41_n_0 ,\result[0]_i_42_n_0 }),
.O(\NLW_result_reg[0]_i_14_O_UNCONNECTED [3:0]),
.S({\result[0]_i_43_n_0 ,\result[0]_i_44_n_0 ,\result[0]_i_45_n_0 ,\result[0]_i_46_n_0 }));
CARRY4 \result_reg[0]_i_23
(.CI(\result_reg[0]_i_52_n_0 ),
.CO({\result_reg[0]_i_23_n_0 ,\NLW_result_reg[0]_i_23_CO_UNCONNECTED [2:0]}),
.CYINIT(1'b0),
.DI({\result[0]_i_39_n_0 ,\result[0]_i_40_n_0 ,\result[0]_i_41_n_0 ,\result[0]_i_42_n_0 }),
.O(\NLW_result_reg[0]_i_23_O_UNCONNECTED [3:0]),
.S({\result[0]_i_53_n_0 ,\result[0]_i_54_n_0 ,\result[0]_i_55_n_0 ,\result[0]_i_56_n_0 }));
CARRY4 \result_reg[0]_i_29
(.CI(\result_reg[0]_i_57_n_0 ),
.CO({\result_reg[0]_i_29_n_0 ,\NLW_result_reg[0]_i_29_CO_UNCONNECTED [2:0]}),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(\NLW_result_reg[0]_i_29_O_UNCONNECTED [3:0]),
.S({\result[0]_i_58_n_0 ,\result[0]_i_59_n_0 ,\result[0]_i_60_n_0 ,\result[0]_i_61_n_0 }));
CARRY4 \result_reg[0]_i_33
(.CI(\result_reg[0]_i_64_n_0 ),
.CO({\result_reg[0]_i_33_n_0 ,\NLW_result_reg[0]_i_33_CO_UNCONNECTED [2:0]}),
.CYINIT(1'b0),
.DI({\result[0]_i_39_n_0 ,\result[0]_i_40_n_0 ,\result[0]_i_41_n_0 ,\result[0]_i_42_n_0 }),
.O(\NLW_result_reg[0]_i_33_O_UNCONNECTED [3:0]),
.S({\result[0]_i_65_n_0 ,\result[0]_i_66_n_0 ,\result[0]_i_67_n_0 ,\result[0]_i_68_n_0 }));
CARRY4 \result_reg[0]_i_38
(.CI(\result_reg[0]_i_69_n_0 ),
.CO({\result_reg[0]_i_38_n_0 ,\NLW_result_reg[0]_i_38_CO_UNCONNECTED [2:0]}),
.CYINIT(1'b0),
.DI({\result[0]_i_70_n_0 ,\result[0]_i_71_n_0 ,\result[0]_i_72_n_0 ,\result[0]_i_73_n_0 }),
.O(\NLW_result_reg[0]_i_38_O_UNCONNECTED [3:0]),
.S({\result[0]_i_74_n_0 ,\result[0]_i_75_n_0 ,\result[0]_i_76_n_0 ,\result[0]_i_77_n_0 }));
CARRY4 \result_reg[0]_i_52
(.CI(\result_reg[0]_i_82_n_0 ),
.CO({\result_reg[0]_i_52_n_0 ,\NLW_result_reg[0]_i_52_CO_UNCONNECTED [2:0]}),
.CYINIT(1'b0),
.DI({\result[0]_i_70_n_0 ,\result[0]_i_71_n_0 ,\result[0]_i_72_n_0 ,\result[0]_i_73_n_0 }),
.O(\NLW_result_reg[0]_i_52_O_UNCONNECTED [3:0]),
.S({\result[0]_i_83_n_0 ,\result[0]_i_84_n_0 ,\result[0]_i_85_n_0 ,\result[0]_i_86_n_0 }));
CARRY4 \result_reg[0]_i_57
(.CI(1'b0),
.CO({\result_reg[0]_i_57_n_0 ,\NLW_result_reg[0]_i_57_CO_UNCONNECTED [2:0]}),
.CYINIT(1'b1),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(\NLW_result_reg[0]_i_57_O_UNCONNECTED [3:0]),
.S({\result[0]_i_87_n_0 ,\result[0]_i_88_n_0 ,\result[0]_i_89_n_0 ,\result[0]_i_90_n_0 }));
CARRY4 \result_reg[0]_i_64
(.CI(\result_reg[0]_i_95_n_0 ),
.CO({\result_reg[0]_i_64_n_0 ,\NLW_result_reg[0]_i_64_CO_UNCONNECTED [2:0]}),
.CYINIT(1'b0),
.DI({\result[0]_i_70_n_0 ,\result[0]_i_71_n_0 ,\result[0]_i_72_n_0 ,\result[0]_i_73_n_0 }),
.O(\NLW_result_reg[0]_i_64_O_UNCONNECTED [3:0]),
.S({\result[0]_i_96_n_0 ,\result[0]_i_97_n_0 ,\result[0]_i_98_n_0 ,\result[0]_i_99_n_0 }));
CARRY4 \result_reg[0]_i_69
(.CI(1'b0),
.CO({\result_reg[0]_i_69_n_0 ,\NLW_result_reg[0]_i_69_CO_UNCONNECTED [2:0]}),
.CYINIT(1'b1),
.DI({\result[0]_i_100_n_0 ,\result[0]_i_101_n_0 ,\result[0]_i_102_n_0 ,\result[0]_i_103_n_0 }),
.O(\NLW_result_reg[0]_i_69_O_UNCONNECTED [3:0]),
.S({\result[0]_i_104_n_0 ,\result[0]_i_105_n_0 ,\result[0]_i_106_n_0 ,\result[0]_i_107_n_0 }));
CARRY4 \result_reg[0]_i_7
(.CI(\result_reg[0]_i_14_n_0 ),
.CO({data10,\NLW_result_reg[0]_i_7_CO_UNCONNECTED [2:0]}),
.CYINIT(1'b0),
.DI({\result[0]_i_15_n_0 ,\result[0]_i_16_n_0 ,\result[0]_i_17_n_0 ,\result[0]_i_18_n_0 }),
.O(\NLW_result_reg[0]_i_7_O_UNCONNECTED [3:0]),
.S({\result[0]_i_19_n_0 ,\result[0]_i_20_n_0 ,\result[0]_i_21_n_0 ,\result[0]_i_22_n_0 }));
CARRY4 \result_reg[0]_i_82
(.CI(1'b0),
.CO({\result_reg[0]_i_82_n_0 ,\NLW_result_reg[0]_i_82_CO_UNCONNECTED [2:0]}),
.CYINIT(1'b1),
.DI({\result[0]_i_100_n_0 ,\result[0]_i_101_n_0 ,\result[0]_i_102_n_0 ,\result[0]_i_103_n_0 }),
.O(\NLW_result_reg[0]_i_82_O_UNCONNECTED [3:0]),
.S({\result[0]_i_110_n_0 ,\result[0]_i_111_n_0 ,\result[0]_i_112_n_0 ,\result[0]_i_113_n_0 }));
CARRY4 \result_reg[0]_i_95
(.CI(1'b0),
.CO({\result_reg[0]_i_95_n_0 ,\NLW_result_reg[0]_i_95_CO_UNCONNECTED [2:0]}),
.CYINIT(1'b0),
.DI({\result[0]_i_100_n_0 ,\result[0]_i_101_n_0 ,\result[0]_i_102_n_0 ,\result[0]_i_103_n_0 }),
.O(\NLW_result_reg[0]_i_95_O_UNCONNECTED [3:0]),
.S({\result[0]_i_117_n_0 ,\result[0]_i_118_n_0 ,\result[0]_i_119_n_0 ,\result[0]_i_120_n_0 }));
FDRE \result_reg[10]
(.C(ETH_CLK_OBUF),
.CE(\result[31]_i_1_n_0 ),
.D(\result[10]_i_1_n_0 ),
.Q(result[10]),
.R(INTERNAL_RST_reg));
FDRE \result_reg[11]
(.C(ETH_CLK_OBUF),
.CE(\result[31]_i_1_n_0 ),
.D(\result[11]_i_1_n_0 ),
.Q(result[11]),
.R(INTERNAL_RST_reg));
CARRY4 \result_reg[11]_i_8
(.CI(\result_reg[7]_i_9_n_0 ),
.CO({\result_reg[11]_i_8_n_0 ,\NLW_result_reg[11]_i_8_CO_UNCONNECTED [2:0]}),
.CYINIT(1'b0),
.DI({\read_input[11]_i_1_n_0 ,\read_input[10]_i_1_n_0 ,\read_input[9]_i_1_n_0 ,\read_input[8]_i_1_n_0 }),
.O({\result_reg[11]_i_8_n_4 ,\result_reg[11]_i_8_n_5 ,\result_reg[11]_i_8_n_6 ,\result_reg[11]_i_8_n_7 }),
.S({\result[11]_i_9_n_0 ,\result[11]_i_10_n_0 ,\result[11]_i_11_n_0 ,\result[11]_i_12_n_0 }));
FDRE \result_reg[12]
(.C(ETH_CLK_OBUF),
.CE(\result[31]_i_1_n_0 ),
.D(\result[12]_i_1_n_0 ),
.Q(result[12]),
.R(INTERNAL_RST_reg));
FDRE \result_reg[13]
(.C(ETH_CLK_OBUF),
.CE(\result[31]_i_1_n_0 ),
.D(\result[13]_i_1_n_0 ),
.Q(result[13]),
.R(INTERNAL_RST_reg));
FDRE \result_reg[14]
(.C(ETH_CLK_OBUF),
.CE(\result[31]_i_1_n_0 ),
.D(\result[14]_i_1_n_0 ),
.Q(result[14]),
.R(INTERNAL_RST_reg));
FDRE \result_reg[15]
(.C(ETH_CLK_OBUF),
.CE(\result[31]_i_1_n_0 ),
.D(\result[15]_i_1_n_0 ),
.Q(result[15]),
.R(INTERNAL_RST_reg));
CARRY4 \result_reg[15]_i_10
(.CI(\result_reg[11]_i_8_n_0 ),
.CO({\result_reg[15]_i_10_n_0 ,\NLW_result_reg[15]_i_10_CO_UNCONNECTED [2:0]}),
.CYINIT(1'b0),
.DI({\read_input[15]_i_1_n_0 ,\read_input[14]_i_1_n_0 ,\read_input[13]_i_1_n_0 ,\read_input[12]_i_1_n_0 }),
.O({\result_reg[15]_i_10_n_4 ,\result_reg[15]_i_10_n_5 ,\result_reg[15]_i_10_n_6 ,\result_reg[15]_i_10_n_7 }),
.S({\result[15]_i_21_n_0 ,\result[15]_i_22_n_0 ,\result[15]_i_23_n_0 ,\result[15]_i_24_n_0 }));
CARRY4 \result_reg[15]_i_11
(.CI(\result_reg[7]_i_10_n_0 ),
.CO({\result_reg[15]_i_11_n_0 ,\NLW_result_reg[15]_i_11_CO_UNCONNECTED [2:0]}),
.CYINIT(1'b0),
.DI({\read_input[11]_i_1_n_0 ,\read_input[10]_i_1_n_0 ,\read_input[9]_i_1_n_0 ,\read_input[8]_i_1_n_0 }),
.O(data5[11:8]),
.S({\result[15]_i_25_n_0 ,\result[15]_i_26_n_0 ,\result[15]_i_27_n_0 ,\result[15]_i_28_n_0 }));
CARRY4 \result_reg[15]_i_16
(.CI(\result_reg[7]_i_11_n_0 ),
.CO({\result_reg[15]_i_16_n_0 ,\NLW_result_reg[15]_i_16_CO_UNCONNECTED [2:0]}),
.CYINIT(1'b0),
.DI({\read_input[11]_i_1_n_0 ,\read_input[10]_i_1_n_0 ,\read_input[9]_i_1_n_0 ,\read_input[8]_i_1_n_0 }),
.O({\result_reg[15]_i_16_n_4 ,\result_reg[15]_i_16_n_5 ,\result_reg[15]_i_16_n_6 ,\result_reg[15]_i_16_n_7 }),
.S({\result[15]_i_29_n_0 ,\result[15]_i_30_n_0 ,\result[15]_i_31_n_0 ,\result[15]_i_32_n_0 }));
CARRY4 \result_reg[15]_i_7
(.CI(\result_reg[15]_i_11_n_0 ),
.CO({\result_reg[15]_i_7_n_0 ,\NLW_result_reg[15]_i_7_CO_UNCONNECTED [2:0]}),
.CYINIT(1'b0),
.DI({\read_input[15]_i_1_n_0 ,\read_input[14]_i_1_n_0 ,\read_input[13]_i_1_n_0 ,\read_input[12]_i_1_n_0 }),
.O(data5[15:12]),
.S({\result[15]_i_12_n_0 ,\result[15]_i_13_n_0 ,\result[15]_i_14_n_0 ,\result[15]_i_15_n_0 }));
CARRY4 \result_reg[15]_i_8
(.CI(\result_reg[15]_i_16_n_0 ),
.CO({\result_reg[15]_i_8_n_0 ,\NLW_result_reg[15]_i_8_CO_UNCONNECTED [2:0]}),
.CYINIT(1'b0),
.DI({\read_input[15]_i_1_n_0 ,\read_input[14]_i_1_n_0 ,\read_input[13]_i_1_n_0 ,\read_input[12]_i_1_n_0 }),
.O({\result_reg[15]_i_8_n_4 ,\result_reg[15]_i_8_n_5 ,\result_reg[15]_i_8_n_6 ,\result_reg[15]_i_8_n_7 }),
.S({\result[15]_i_17_n_0 ,\result[15]_i_18_n_0 ,\result[15]_i_19_n_0 ,\result[15]_i_20_n_0 }));
FDRE \result_reg[16]
(.C(ETH_CLK_OBUF),
.CE(\result[31]_i_1_n_0 ),
.D(\result[16]_i_1_n_0 ),
.Q(result[16]),
.R(INTERNAL_RST_reg));
CARRY4 \result_reg[16]_i_10
(.CI(\result_reg[8]_i_8_n_0 ),
.CO({\result_reg[16]_i_10_n_0 ,\NLW_result_reg[16]_i_10_CO_UNCONNECTED [2:0]}),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(data2[12:9]),
.S(program_counter_2[12:9]));
CARRY4 \result_reg[16]_i_7
(.CI(\result_reg[16]_i_10_n_0 ),
.CO({data2[16],\NLW_result_reg[16]_i_7_CO_UNCONNECTED [2:0]}),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O({\NLW_result_reg[16]_i_7_O_UNCONNECTED [3],data2[15:13]}),
.S({1'b1,program_counter_2[15:13]}));
FDRE \result_reg[17]
(.C(ETH_CLK_OBUF),
.CE(\result[31]_i_1_n_0 ),
.D(\result[17]_i_1_n_0 ),
.Q(result[17]),
.R(INTERNAL_RST_reg));
FDRE \result_reg[18]
(.C(ETH_CLK_OBUF),
.CE(\result[31]_i_1_n_0 ),
.D(\result[18]_i_1_n_0 ),
.Q(result[18]),
.R(INTERNAL_RST_reg));
FDRE \result_reg[19]
(.C(ETH_CLK_OBUF),
.CE(\result[31]_i_1_n_0 ),
.D(\result[19]_i_1_n_0 ),
.Q(result[19]),
.R(INTERNAL_RST_reg));
CARRY4 \result_reg[19]_i_11
(.CI(\result_reg[15]_i_10_n_0 ),
.CO({\result_reg[19]_i_11_n_0 ,\NLW_result_reg[19]_i_11_CO_UNCONNECTED [2:0]}),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O({\result_reg[19]_i_11_n_4 ,\result_reg[19]_i_11_n_5 ,\result_reg[19]_i_11_n_6 ,\result_reg[19]_i_11_n_7 }),
.S({\result[19]_i_20_n_0 ,\result[19]_i_21_n_0 ,\result[19]_i_22_n_0 ,\result[19]_i_23_n_0 }));
CARRY4 \result_reg[19]_i_6
(.CI(\result_reg[15]_i_7_n_0 ),
.CO({\result_reg[19]_i_6_n_0 ,\NLW_result_reg[19]_i_6_CO_UNCONNECTED [2:0]}),
.CYINIT(1'b0),
.DI({\read_input[19]_i_1_n_0 ,\read_input[18]_i_1_n_0 ,\read_input[17]_i_1_n_0 ,\read_input[16]_i_1_n_0 }),
.O(data5[19:16]),
.S({\result[19]_i_12_n_0 ,\result[19]_i_13_n_0 ,\result[19]_i_14_n_0 ,\result[19]_i_15_n_0 }));
CARRY4 \result_reg[19]_i_7
(.CI(\result_reg[15]_i_8_n_0 ),
.CO({\result_reg[19]_i_7_n_0 ,\NLW_result_reg[19]_i_7_CO_UNCONNECTED [2:0]}),
.CYINIT(1'b0),
.DI({\read_input[19]_i_1_n_0 ,\read_input[18]_i_1_n_0 ,\read_input[17]_i_1_n_0 ,\read_input[16]_i_1_n_0 }),
.O({\result_reg[19]_i_7_n_4 ,\result_reg[19]_i_7_n_5 ,\result_reg[19]_i_7_n_6 ,\result_reg[19]_i_7_n_7 }),
.S({\result[19]_i_16_n_0 ,\result[19]_i_17_n_0 ,\result[19]_i_18_n_0 ,\result[19]_i_19_n_0 }));
FDRE \result_reg[1]
(.C(ETH_CLK_OBUF),
.CE(\result[31]_i_1_n_0 ),
.D(\result[1]_i_1_n_0 ),
.Q(result[1]),
.R(INTERNAL_RST_reg));
CARRY4 \result_reg[1]_i_6
(.CI(1'b0),
.CO({\result_reg[1]_i_6_n_0 ,\NLW_result_reg[1]_i_6_CO_UNCONNECTED [2:0]}),
.CYINIT(1'b0),
.DI({\read_input[3]_i_1_n_0 ,\read_input[2]_i_1_n_0 ,\read_input[1]_i_1_n_0 ,\read_input[0]_i_1_n_0 }),
.O({\result_reg[1]_i_6_n_4 ,\result_reg[1]_i_6_n_5 ,\result_reg[1]_i_6_n_6 ,\result_reg[1]_i_6_n_7 }),
.S({\result[1]_i_10_n_0 ,\result[1]_i_11_n_0 ,\result[1]_i_12_n_0 ,\result[1]_i_13_n_0 }));
FDRE \result_reg[20]
(.C(ETH_CLK_OBUF),
.CE(\result[31]_i_1_n_0 ),
.D(\result[20]_i_1_n_0 ),
.Q(result[20]),
.R(INTERNAL_RST_reg));
FDRE \result_reg[21]
(.C(ETH_CLK_OBUF),
.CE(\result[31]_i_1_n_0 ),
.D(\result[21]_i_1_n_0 ),
.Q(result[21]),
.R(INTERNAL_RST_reg));
FDRE \result_reg[22]
(.C(ETH_CLK_OBUF),
.CE(\result[31]_i_1_n_0 ),
.D(\result[22]_i_1_n_0 ),
.Q(result[22]),
.R(INTERNAL_RST_reg));
FDRE \result_reg[23]
(.C(ETH_CLK_OBUF),
.CE(\result[31]_i_1_n_0 ),
.D(\result[23]_i_1_n_0 ),
.Q(result[23]),
.R(INTERNAL_RST_reg));
CARRY4 \result_reg[23]_i_10
(.CI(\result_reg[19]_i_11_n_0 ),
.CO({\result_reg[23]_i_10_n_0 ,\NLW_result_reg[23]_i_10_CO_UNCONNECTED [2:0]}),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O({\result_reg[23]_i_10_n_4 ,\result_reg[23]_i_10_n_5 ,\result_reg[23]_i_10_n_6 ,\result_reg[23]_i_10_n_7 }),
.S({\result[23]_i_20_n_0 ,\result[23]_i_21_n_0 ,\result[23]_i_22_n_0 ,\result[23]_i_23_n_0 }));
CARRY4 \result_reg[23]_i_7
(.CI(\result_reg[19]_i_7_n_0 ),
.CO({\result_reg[23]_i_7_n_0 ,\NLW_result_reg[23]_i_7_CO_UNCONNECTED [2:0]}),
.CYINIT(1'b0),
.DI({\read_input[23]_i_1_n_0 ,\read_input[22]_i_1_n_0 ,\read_input[21]_i_1_n_0 ,\read_input[20]_i_1_n_0 }),
.O({\result_reg[23]_i_7_n_4 ,\result_reg[23]_i_7_n_5 ,\result_reg[23]_i_7_n_6 ,\result_reg[23]_i_7_n_7 }),
.S({\result[23]_i_12_n_0 ,\result[23]_i_13_n_0 ,\result[23]_i_14_n_0 ,\result[23]_i_15_n_0 }));
CARRY4 \result_reg[23]_i_8
(.CI(\result_reg[19]_i_6_n_0 ),
.CO({\result_reg[23]_i_8_n_0 ,\NLW_result_reg[23]_i_8_CO_UNCONNECTED [2:0]}),
.CYINIT(1'b0),
.DI({\read_input[23]_i_1_n_0 ,\read_input[22]_i_1_n_0 ,\read_input[21]_i_1_n_0 ,\read_input[20]_i_1_n_0 }),
.O(data5[23:20]),
.S({\result[23]_i_16_n_0 ,\result[23]_i_17_n_0 ,\result[23]_i_18_n_0 ,\result[23]_i_19_n_0 }));
FDRE \result_reg[24]
(.C(ETH_CLK_OBUF),
.CE(\result[31]_i_1_n_0 ),
.D(\result[24]_i_1_n_0 ),
.Q(result[24]),
.R(INTERNAL_RST_reg));
FDRE \result_reg[25]
(.C(ETH_CLK_OBUF),
.CE(\result[31]_i_1_n_0 ),
.D(\result[25]_i_1_n_0 ),
.Q(result[25]),
.R(INTERNAL_RST_reg));
FDRE \result_reg[26]
(.C(ETH_CLK_OBUF),
.CE(\result[31]_i_1_n_0 ),
.D(\result[26]_i_1_n_0 ),
.Q(result[26]),
.R(INTERNAL_RST_reg));
FDRE \result_reg[27]
(.C(ETH_CLK_OBUF),
.CE(\result[31]_i_1_n_0 ),
.D(\result[27]_i_1_n_0 ),
.Q(result[27]),
.R(INTERNAL_RST_reg));
CARRY4 \result_reg[27]_i_10
(.CI(\result_reg[23]_i_7_n_0 ),
.CO({\result_reg[27]_i_10_n_0 ,\NLW_result_reg[27]_i_10_CO_UNCONNECTED [2:0]}),
.CYINIT(1'b0),
.DI({\read_input[27]_i_1_n_0 ,\read_input[26]_i_1_n_0 ,\read_input[25]_i_1_n_0 ,\read_input[24]_i_1_n_0 }),
.O({\result_reg[27]_i_10_n_4 ,\result_reg[27]_i_10_n_5 ,\result_reg[27]_i_10_n_6 ,\result_reg[27]_i_10_n_7 }),
.S({\result[27]_i_27_n_0 ,\result[27]_i_28_n_0 ,\result[27]_i_29_n_0 ,\result[27]_i_30_n_0 }));
CARRY4 \result_reg[27]_i_11
(.CI(\result_reg[23]_i_8_n_0 ),
.CO({\result_reg[27]_i_11_n_0 ,\NLW_result_reg[27]_i_11_CO_UNCONNECTED [2:0]}),
.CYINIT(1'b0),
.DI({\read_input[27]_i_1_n_0 ,\read_input[26]_i_1_n_0 ,\read_input[25]_i_1_n_0 ,\read_input[24]_i_1_n_0 }),
.O(data5[27:24]),
.S({\result[27]_i_31_n_0 ,\result[27]_i_32_n_0 ,\result[27]_i_33_n_0 ,\result[27]_i_34_n_0 }));
FDRE \result_reg[28]
(.C(ETH_CLK_OBUF),
.CE(\result[31]_i_1_n_0 ),
.D(\result[28]_i_1_n_0 ),
.Q(result[28]),
.R(INTERNAL_RST_reg));
MUXF7 \result_reg[28]_i_3
(.I0(\result[28]_i_6_n_0 ),
.I1(\result[28]_i_7_n_0 ),
.O(\result_reg[28]_i_3_n_0 ),
.S(\result_reg[31]_i_9_n_7 ));
FDRE \result_reg[29]
(.C(ETH_CLK_OBUF),
.CE(\result[31]_i_1_n_0 ),
.D(\result[29]_i_1_n_0 ),
.Q(result[29]),
.R(INTERNAL_RST_reg));
MUXF7 \result_reg[29]_i_3
(.I0(\result[29]_i_6_n_0 ),
.I1(\result[29]_i_7_n_0 ),
.O(\result_reg[29]_i_3_n_0 ),
.S(\result_reg[31]_i_9_n_6 ));
FDRE \result_reg[2]
(.C(ETH_CLK_OBUF),
.CE(\result[31]_i_1_n_0 ),
.D(\result[2]_i_1_n_0 ),
.Q(result[2]),
.R(INTERNAL_RST_reg));
FDRE \result_reg[30]
(.C(ETH_CLK_OBUF),
.CE(\result[31]_i_1_n_0 ),
.D(\result[30]_i_1_n_0 ),
.Q(result[30]),
.R(INTERNAL_RST_reg));
MUXF7 \result_reg[30]_i_3
(.I0(\result[30]_i_6_n_0 ),
.I1(\result[30]_i_7_n_0 ),
.O(\result_reg[30]_i_3_n_0 ),
.S(\result_reg[31]_i_9_n_5 ));
FDRE \result_reg[31]
(.C(ETH_CLK_OBUF),
.CE(\result[31]_i_1_n_0 ),
.D(\result[31]_i_2_n_0 ),
.Q(result[31]),
.R(INTERNAL_RST_reg));
CARRY4 \result_reg[31]_i_14
(.CI(\result_reg[27]_i_11_n_0 ),
.CO(\NLW_result_reg[31]_i_14_CO_UNCONNECTED [3:0]),
.CYINIT(1'b0),
.DI({1'b0,\read_input[30]_i_1_n_0 ,\read_input[29]_i_1_n_0 ,\read_input[28]_i_1_n_0 }),
.O(data5[31:28]),
.S({\result[31]_i_25_n_0 ,\result[31]_i_26_n_0 ,\result[31]_i_27_n_0 ,\result[31]_i_28_n_0 }));
CARRY4 \result_reg[31]_i_15
(.CI(\result_reg[27]_i_10_n_0 ),
.CO(\NLW_result_reg[31]_i_15_CO_UNCONNECTED [3:0]),
.CYINIT(1'b0),
.DI({1'b0,\read_input[30]_i_1_n_0 ,\read_input[29]_i_1_n_0 ,\read_input[28]_i_1_n_0 }),
.O({\result_reg[31]_i_15_n_4 ,\result_reg[31]_i_15_n_5 ,\result_reg[31]_i_15_n_6 ,\result_reg[31]_i_15_n_7 }),
.S({\result[31]_i_29_n_0 ,\result[31]_i_30_n_0 ,\result[31]_i_31_n_0 ,\result[31]_i_32_n_0 }));
CARRY4 \result_reg[31]_i_16
(.CI(\result_reg[23]_i_10_n_0 ),
.CO({\result_reg[31]_i_16_n_0 ,\NLW_result_reg[31]_i_16_CO_UNCONNECTED [2:0]}),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O({\result_reg[31]_i_16_n_4 ,\result_reg[31]_i_16_n_5 ,\result_reg[31]_i_16_n_6 ,\result_reg[31]_i_16_n_7 }),
.S({\result[31]_i_33_n_0 ,\result[31]_i_34_n_0 ,\result[31]_i_35_n_0 ,\result[31]_i_36_n_0 }));
MUXF7 \result_reg[31]_i_6
(.I0(\result[31]_i_10_n_0 ),
.I1(\result[31]_i_11_n_0 ),
.O(\result_reg[31]_i_6_n_0 ),
.S(\result_reg[31]_i_9_n_4 ));
CARRY4 \result_reg[31]_i_9
(.CI(\result_reg[31]_i_16_n_0 ),
.CO(\NLW_result_reg[31]_i_9_CO_UNCONNECTED [3:0]),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O({\result_reg[31]_i_9_n_4 ,\result_reg[31]_i_9_n_5 ,\result_reg[31]_i_9_n_6 ,\result_reg[31]_i_9_n_7 }),
.S({\result[31]_i_17_n_0 ,\result[31]_i_18_n_0 ,\result[31]_i_19_n_0 ,\result[31]_i_20_n_0 }));
FDRE \result_reg[3]
(.C(ETH_CLK_OBUF),
.CE(\result[31]_i_1_n_0 ),
.D(\result[3]_i_1_n_0 ),
.Q(result[3]),
.R(INTERNAL_RST_reg));
CARRY4 \result_reg[3]_i_8
(.CI(1'b0),
.CO({\result_reg[3]_i_8_n_0 ,\NLW_result_reg[3]_i_8_CO_UNCONNECTED [2:0]}),
.CYINIT(1'b1),
.DI({\read_input[3]_i_1_n_0 ,\read_input[2]_i_1_n_0 ,\read_input[1]_i_1_n_0 ,\read_input[0]_i_1_n_0 }),
.O(data5[3:0]),
.S({\result[3]_i_10_n_0 ,\result[3]_i_11_n_0 ,\result[3]_i_12_n_0 ,\result[3]_i_13_n_0 }));
CARRY4 \result_reg[3]_i_9
(.CI(1'b0),
.CO({\result_reg[3]_i_9_n_0 ,\NLW_result_reg[3]_i_9_CO_UNCONNECTED [2:0]}),
.CYINIT(1'b0),
.DI({\read_input[3]_i_1_n_0 ,\read_input[2]_i_1_n_0 ,\read_input[1]_i_1_n_0 ,\read_input[0]_i_1_n_0 }),
.O({\result_reg[3]_i_9_n_4 ,\result_reg[3]_i_9_n_5 ,\result_reg[3]_i_9_n_6 ,\result_reg[3]_i_9_n_7 }),
.S({\result[3]_i_14_n_0 ,\result[3]_i_15_n_0 ,\result[3]_i_16_n_0 ,\result[3]_i_17_n_0 }));
FDRE \result_reg[4]
(.C(ETH_CLK_OBUF),
.CE(\result[31]_i_1_n_0 ),
.D(\result[4]_i_1_n_0 ),
.Q(result[4]),
.R(INTERNAL_RST_reg));
CARRY4 \result_reg[4]_i_8
(.CI(1'b0),
.CO({\result_reg[4]_i_8_n_0 ,\NLW_result_reg[4]_i_8_CO_UNCONNECTED [2:0]}),
.CYINIT(program_counter_2[0]),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(data2[4:1]),
.S(program_counter_2[4:1]));
FDRE \result_reg[5]
(.C(ETH_CLK_OBUF),
.CE(\result[31]_i_1_n_0 ),
.D(\result[5]_i_1_n_0 ),
.Q(result[5]),
.R(INTERNAL_RST_reg));
FDRE \result_reg[6]
(.C(ETH_CLK_OBUF),
.CE(\result[31]_i_1_n_0 ),
.D(\result[6]_i_1_n_0 ),
.Q(result[6]),
.R(INTERNAL_RST_reg));
FDRE \result_reg[7]
(.C(ETH_CLK_OBUF),
.CE(\result[31]_i_1_n_0 ),
.D(\result[7]_i_1_n_0 ),
.Q(result[7]),
.R(INTERNAL_RST_reg));
CARRY4 \result_reg[7]_i_10
(.CI(\result_reg[3]_i_8_n_0 ),
.CO({\result_reg[7]_i_10_n_0 ,\NLW_result_reg[7]_i_10_CO_UNCONNECTED [2:0]}),
.CYINIT(1'b0),
.DI({\read_input[7]_i_1_n_0 ,\read_input[6]_i_1_n_0 ,\read_input[5]_i_1_n_0 ,\read_input[4]_i_1_n_0 }),
.O(data5[7:4]),
.S({\result[7]_i_16_n_0 ,\result[7]_i_17_n_0 ,\result[7]_i_18_n_0 ,\result[7]_i_19_n_0 }));
CARRY4 \result_reg[7]_i_11
(.CI(\result_reg[3]_i_9_n_0 ),
.CO({\result_reg[7]_i_11_n_0 ,\NLW_result_reg[7]_i_11_CO_UNCONNECTED [2:0]}),
.CYINIT(1'b0),
.DI({\read_input[7]_i_1_n_0 ,\read_input[6]_i_1_n_0 ,\read_input[5]_i_1_n_0 ,\read_input[4]_i_1_n_0 }),
.O({\result_reg[7]_i_11_n_4 ,\result_reg[7]_i_11_n_5 ,\result_reg[7]_i_11_n_6 ,\result_reg[7]_i_11_n_7 }),
.S({\result[7]_i_20_n_0 ,\result[7]_i_21_n_0 ,\result[7]_i_22_n_0 ,\result[7]_i_23_n_0 }));
CARRY4 \result_reg[7]_i_9
(.CI(\result_reg[1]_i_6_n_0 ),
.CO({\result_reg[7]_i_9_n_0 ,\NLW_result_reg[7]_i_9_CO_UNCONNECTED [2:0]}),
.CYINIT(1'b0),
.DI({\read_input[7]_i_1_n_0 ,\read_input[6]_i_1_n_0 ,\read_input[5]_i_1_n_0 ,\read_input[4]_i_1_n_0 }),
.O({\result_reg[7]_i_9_n_4 ,\result_reg[7]_i_9_n_5 ,\result_reg[7]_i_9_n_6 ,\result_reg[7]_i_9_n_7 }),
.S({\result[7]_i_12_n_0 ,\result[7]_i_13_n_0 ,\result[7]_i_14_n_0 ,\result[7]_i_15_n_0 }));
FDRE \result_reg[8]
(.C(ETH_CLK_OBUF),
.CE(\result[31]_i_1_n_0 ),
.D(\result[8]_i_1_n_0 ),
.Q(result[8]),
.R(INTERNAL_RST_reg));
CARRY4 \result_reg[8]_i_8
(.CI(\result_reg[4]_i_8_n_0 ),
.CO({\result_reg[8]_i_8_n_0 ,\NLW_result_reg[8]_i_8_CO_UNCONNECTED [2:0]}),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(data2[8:5]),
.S(program_counter_2[8:5]));
FDRE \result_reg[9]
(.C(ETH_CLK_OBUF),
.CE(\result[31]_i_1_n_0 ),
.D(\result[9]_i_1_n_0 ),
.Q(result[9]),
.R(INTERNAL_RST_reg));
LUT6 #(
.INIT(64'hFFFF7FFF0000C000))
\s_input_rs232_in_ack[0]_i_1
(.I0(OUT1_STB),
.I1(\s_input_rs232_in_ack[0]_i_2_n_0 ),
.I2(\state_reg_n_0_[1] ),
.I3(\state_reg_n_0_[2] ),
.I4(\state_reg_n_0_[0] ),
.I5(OUT1_ACK),
.O(\s_input_rs232_in_ack[0]_i_1_n_0 ));
LUT6 #(
.INIT(64'h8000000000000000))
\s_input_rs232_in_ack[0]_i_2
(.I0(\s_input_rs232_in_ack[0]_i_3_n_0 ),
.I1(\s_input_rs232_in_ack[0]_i_4_n_0 ),
.I2(\s_input_rs232_in_ack[0]_i_5_n_0 ),
.I3(\s_input_rs232_in_ack[0]_i_6_n_0 ),
.I4(\s_input_rs232_in_ack[0]_i_7_n_0 ),
.I5(\s_input_rs232_in_ack[0]_i_8_n_0 ),
.O(\s_input_rs232_in_ack[0]_i_2_n_0 ));
LUT6 #(
.INIT(64'h0000000000000001))
\s_input_rs232_in_ack[0]_i_3
(.I0(read_input[12]),
.I1(read_input[6]),
.I2(read_input[4]),
.I3(read_input[9]),
.I4(read_input[17]),
.I5(read_input[18]),
.O(\s_input_rs232_in_ack[0]_i_3_n_0 ));
LUT2 #(
.INIT(4'h1))
\s_input_rs232_in_ack[0]_i_4
(.I0(read_input[8]),
.I1(read_input[31]),
.O(\s_input_rs232_in_ack[0]_i_4_n_0 ));
LUT6 #(
.INIT(64'h0000000000000001))
\s_input_rs232_in_ack[0]_i_5
(.I0(read_input[11]),
.I1(read_input[10]),
.I2(read_input[14]),
.I3(read_input[20]),
.I4(read_input[7]),
.I5(read_input[19]),
.O(\s_input_rs232_in_ack[0]_i_5_n_0 ));
LUT6 #(
.INIT(64'h0000000000000001))
\s_input_rs232_in_ack[0]_i_6
(.I0(read_input[29]),
.I1(read_input[0]),
.I2(read_input[26]),
.I3(read_input[30]),
.I4(read_input[13]),
.I5(read_input[15]),
.O(\s_input_rs232_in_ack[0]_i_6_n_0 ));
LUT6 #(
.INIT(64'h0000000000000001))
\s_input_rs232_in_ack[0]_i_7
(.I0(read_input[24]),
.I1(read_input[1]),
.I2(read_input[2]),
.I3(read_input[23]),
.I4(read_input[3]),
.I5(read_input[28]),
.O(\s_input_rs232_in_ack[0]_i_7_n_0 ));
LUT6 #(
.INIT(64'h0000000000000001))
\s_input_rs232_in_ack[0]_i_8
(.I0(read_input[27]),
.I1(read_input[21]),
.I2(read_input[16]),
.I3(read_input[22]),
.I4(read_input[5]),
.I5(read_input[25]),
.O(\s_input_rs232_in_ack[0]_i_8_n_0 ));
FDRE \s_input_rs232_in_ack_reg[0]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(\s_input_rs232_in_ack[0]_i_1_n_0 ),
.Q(OUT1_ACK),
.R(INTERNAL_RST_reg));
LUT3 #(
.INIT(8'h80))
\s_output_rs232_out[7]_i_1
(.I0(\state_reg_n_0_[2] ),
.I1(\state_reg_n_0_[1] ),
.I2(\s_output_rs232_out[7]_i_2_n_0 ),
.O(\s_output_rs232_out[7]_i_1_n_0 ));
LUT6 #(
.INIT(64'h8000000000000000))
\s_output_rs232_out[7]_i_2
(.I0(\s_output_rs232_out[7]_i_3_n_0 ),
.I1(\s_output_rs232_out[7]_i_4_n_0 ),
.I2(\s_output_rs232_out[7]_i_5_n_0 ),
.I3(\s_output_rs232_out[7]_i_6_n_0 ),
.I4(\s_output_rs232_out[7]_i_7_n_0 ),
.I5(\s_output_rs232_out[7]_i_8_n_0 ),
.O(\s_output_rs232_out[7]_i_2_n_0 ));
LUT6 #(
.INIT(64'h0000000000000001))
\s_output_rs232_out[7]_i_3
(.I0(write_output[15]),
.I1(write_output[12]),
.I2(write_output[20]),
.I3(write_output[21]),
.I4(write_output[6]),
.I5(write_output[23]),
.O(\s_output_rs232_out[7]_i_3_n_0 ));
LUT3 #(
.INIT(8'h01))
\s_output_rs232_out[7]_i_4
(.I0(write_output[31]),
.I1(write_output[27]),
.I2(write_output[30]),
.O(\s_output_rs232_out[7]_i_4_n_0 ));
LUT6 #(
.INIT(64'h0000000000000001))
\s_output_rs232_out[7]_i_5
(.I0(write_output[8]),
.I1(write_output[16]),
.I2(write_output[26]),
.I3(write_output[24]),
.I4(write_output[10]),
.I5(write_output[22]),
.O(\s_output_rs232_out[7]_i_5_n_0 ));
LUT6 #(
.INIT(64'h0000000000000010))
\s_output_rs232_out[7]_i_6
(.I0(write_output[13]),
.I1(write_output[29]),
.I2(\state_reg_n_0_[0] ),
.I3(write_output[25]),
.I4(write_output[18]),
.I5(write_output[1]),
.O(\s_output_rs232_out[7]_i_6_n_0 ));
LUT6 #(
.INIT(64'h0000000000000001))
\s_output_rs232_out[7]_i_7
(.I0(write_output[11]),
.I1(write_output[3]),
.I2(write_output[5]),
.I3(write_output[9]),
.I4(write_output[7]),
.I5(write_output[14]),
.O(\s_output_rs232_out[7]_i_7_n_0 ));
LUT6 #(
.INIT(64'h0000000000000010))
\s_output_rs232_out[7]_i_8
(.I0(write_output[19]),
.I1(write_output[2]),
.I2(write_output[0]),
.I3(write_output[28]),
.I4(write_output[4]),
.I5(write_output[17]),
.O(\s_output_rs232_out[7]_i_8_n_0 ));
FDRE \s_output_rs232_out_reg[0]
(.C(ETH_CLK_OBUF),
.CE(\s_output_rs232_out[7]_i_1_n_0 ),
.D(write_value[0]),
.Q(output_rs232_out[0]),
.R(1'b0));
FDRE \s_output_rs232_out_reg[1]
(.C(ETH_CLK_OBUF),
.CE(\s_output_rs232_out[7]_i_1_n_0 ),
.D(write_value[1]),
.Q(output_rs232_out[1]),
.R(1'b0));
FDRE \s_output_rs232_out_reg[2]
(.C(ETH_CLK_OBUF),
.CE(\s_output_rs232_out[7]_i_1_n_0 ),
.D(write_value[2]),
.Q(output_rs232_out[2]),
.R(1'b0));
FDRE \s_output_rs232_out_reg[3]
(.C(ETH_CLK_OBUF),
.CE(\s_output_rs232_out[7]_i_1_n_0 ),
.D(write_value[3]),
.Q(output_rs232_out[3]),
.R(1'b0));
FDRE \s_output_rs232_out_reg[4]
(.C(ETH_CLK_OBUF),
.CE(\s_output_rs232_out[7]_i_1_n_0 ),
.D(write_value[4]),
.Q(output_rs232_out[4]),
.R(1'b0));
FDRE \s_output_rs232_out_reg[5]
(.C(ETH_CLK_OBUF),
.CE(\s_output_rs232_out[7]_i_1_n_0 ),
.D(write_value[5]),
.Q(output_rs232_out[5]),
.R(1'b0));
FDRE \s_output_rs232_out_reg[6]
(.C(ETH_CLK_OBUF),
.CE(\s_output_rs232_out[7]_i_1_n_0 ),
.D(write_value[6]),
.Q(output_rs232_out[6]),
.R(1'b0));
FDRE \s_output_rs232_out_reg[7]
(.C(ETH_CLK_OBUF),
.CE(\s_output_rs232_out[7]_i_1_n_0 ),
.D(write_value[7]),
.Q(output_rs232_out[7]),
.R(1'b0));
LUT5 #(
.INIT(32'h7FFF8080))
\s_output_rs232_out_stb[0]_i_1
(.I0(\state_reg_n_0_[2] ),
.I1(\state_reg_n_0_[1] ),
.I2(\s_output_rs232_out[7]_i_2_n_0 ),
.I3(IN1_ACK),
.I4(IN1_STB),
.O(\s_output_rs232_out_stb[0]_i_1_n_0 ));
FDRE \s_output_rs232_out_stb_reg[0]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(\s_output_rs232_out_stb[0]_i_1_n_0 ),
.Q(IN1_STB),
.R(INTERNAL_RST_reg));
LUT6 #(
.INIT(64'hAAAAAEFFAAAAA200))
\state[0]_i_1
(.I0(\state[0]_i_2_n_0 ),
.I1(\state[2]_i_3_n_0 ),
.I2(\state[2]_i_4_n_0 ),
.I3(instruction0),
.I4(\state[2]_i_5_n_0 ),
.I5(\state_reg_n_0_[0] ),
.O(\state[0]_i_1_n_0 ));
LUT3 #(
.INIT(8'hBF))
\state[0]_i_2
(.I0(\state_reg_n_0_[2] ),
.I1(\state_reg_n_0_[0] ),
.I2(\state[0]_i_3_n_0 ),
.O(\state[0]_i_2_n_0 ));
LUT6 #(
.INIT(64'hFDFFFFDFDFD7FF7F))
\state[0]_i_3
(.I0(\state_reg_n_0_[1] ),
.I1(opcode_2[3]),
.I2(opcode_2[1]),
.I3(opcode_2[2]),
.I4(opcode_2[0]),
.I5(opcode_2[4]),
.O(\state[0]_i_3_n_0 ));
LUT6 #(
.INIT(64'hAAAAAEFFAAAAA200))
\state[1]_i_1
(.I0(\state[1]_i_2_n_0 ),
.I1(\state[2]_i_3_n_0 ),
.I2(\state[2]_i_4_n_0 ),
.I3(instruction0),
.I4(\state[2]_i_5_n_0 ),
.I5(\state_reg_n_0_[1] ),
.O(\state[1]_i_1_n_0 ));
LUT6 #(
.INIT(64'h0020FFFFFFFFFFFF))
\state[1]_i_2
(.I0(opcode_2[4]),
.I1(opcode_2[2]),
.I2(opcode_2[1]),
.I3(opcode_2[3]),
.I4(\state_reg_n_0_[0] ),
.I5(opcode_20),
.O(\state[1]_i_2_n_0 ));
LUT6 #(
.INIT(64'hAAAAAEFFAAAAA200))
\state[2]_i_1
(.I0(\state[2]_i_2_n_0 ),
.I1(\state[2]_i_3_n_0 ),
.I2(\state[2]_i_4_n_0 ),
.I3(instruction0),
.I4(\state[2]_i_5_n_0 ),
.I5(\state_reg_n_0_[2] ),
.O(\state[2]_i_1_n_0 ));
LUT6 #(
.INIT(64'h000C002000000000))
\state[2]_i_2
(.I0(opcode_2[0]),
.I1(opcode_2[1]),
.I2(opcode_2[2]),
.I3(opcode_2[3]),
.I4(opcode_2[4]),
.I5(\address_z_3[3]_i_1_n_0 ),
.O(\state[2]_i_2_n_0 ));
LUT6 #(
.INIT(64'hFBABFBEFEBEBFBEF))
\state[2]_i_3
(.I0(opcode_2[3]),
.I1(opcode_2[1]),
.I2(opcode_2[2]),
.I3(opcode_2[4]),
.I4(opcode_2[0]),
.I5(\program_counter[15]_i_8_n_0 ),
.O(\state[2]_i_3_n_0 ));
LUT6 #(
.INIT(64'h0006FFFFFFFFFFFF))
\state[2]_i_4
(.I0(opcode_2[0]),
.I1(opcode_2[1]),
.I2(opcode_2[4]),
.I3(\state[2]_i_6_n_0 ),
.I4(\state_reg_n_0_[1] ),
.I5(\state_reg_n_0_[0] ),
.O(\state[2]_i_4_n_0 ));
LUT6 #(
.INIT(64'hF444444444444444))
\state[2]_i_5
(.I0(\program_counter[15]_i_15_n_0 ),
.I1(\result[31]_i_4_n_0 ),
.I2(IN1_ACK),
.I3(IN1_STB),
.I4(\state_reg_n_0_[2] ),
.I5(\s_output_rs232_out[7]_i_2_n_0 ),
.O(\state[2]_i_5_n_0 ));
LUT2 #(
.INIT(4'hB))
\state[2]_i_6
(.I0(opcode_2[2]),
.I1(opcode_2[3]),
.O(\state[2]_i_6_n_0 ));
FDSE \state_reg[0]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(\state[0]_i_1_n_0 ),
.Q(\state_reg_n_0_[0] ),
.S(INTERNAL_RST_reg));
FDRE \state_reg[1]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(\state[1]_i_1_n_0 ),
.Q(\state_reg_n_0_[1] ),
.R(INTERNAL_RST_reg));
FDRE \state_reg[2]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(\state[2]_i_1_n_0 ),
.Q(\state_reg_n_0_[2] ),
.R(INTERNAL_RST_reg));
FDRE write_enable_reg
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(\result[31]_i_1_n_0 ),
.Q(write_enable_reg_n_0),
.R(1'b0));
LUT6 #(
.INIT(64'h0000000000080000))
\write_output[31]_i_1
(.I0(opcode_2[4]),
.I1(\address_z_3[3]_i_1_n_0 ),
.I2(opcode_2[0]),
.I3(opcode_2[2]),
.I4(opcode_2[1]),
.I5(opcode_2[3]),
.O(out0));
FDRE \write_output_reg[0]
(.C(ETH_CLK_OBUF),
.CE(out0),
.D(\read_input[0]_i_1_n_0 ),
.Q(write_output[0]),
.R(1'b0));
FDRE \write_output_reg[10]
(.C(ETH_CLK_OBUF),
.CE(out0),
.D(\read_input[10]_i_1_n_0 ),
.Q(write_output[10]),
.R(1'b0));
FDRE \write_output_reg[11]
(.C(ETH_CLK_OBUF),
.CE(out0),
.D(\read_input[11]_i_1_n_0 ),
.Q(write_output[11]),
.R(1'b0));
FDRE \write_output_reg[12]
(.C(ETH_CLK_OBUF),
.CE(out0),
.D(\read_input[12]_i_1_n_0 ),
.Q(write_output[12]),
.R(1'b0));
FDRE \write_output_reg[13]
(.C(ETH_CLK_OBUF),
.CE(out0),
.D(\read_input[13]_i_1_n_0 ),
.Q(write_output[13]),
.R(1'b0));
FDRE \write_output_reg[14]
(.C(ETH_CLK_OBUF),
.CE(out0),
.D(\read_input[14]_i_1_n_0 ),
.Q(write_output[14]),
.R(1'b0));
FDRE \write_output_reg[15]
(.C(ETH_CLK_OBUF),
.CE(out0),
.D(\read_input[15]_i_1_n_0 ),
.Q(write_output[15]),
.R(1'b0));
FDRE \write_output_reg[16]
(.C(ETH_CLK_OBUF),
.CE(out0),
.D(\read_input[16]_i_1_n_0 ),
.Q(write_output[16]),
.R(1'b0));
FDRE \write_output_reg[17]
(.C(ETH_CLK_OBUF),
.CE(out0),
.D(\read_input[17]_i_1_n_0 ),
.Q(write_output[17]),
.R(1'b0));
FDRE \write_output_reg[18]
(.C(ETH_CLK_OBUF),
.CE(out0),
.D(\read_input[18]_i_1_n_0 ),
.Q(write_output[18]),
.R(1'b0));
FDRE \write_output_reg[19]
(.C(ETH_CLK_OBUF),
.CE(out0),
.D(\read_input[19]_i_1_n_0 ),
.Q(write_output[19]),
.R(1'b0));
FDRE \write_output_reg[1]
(.C(ETH_CLK_OBUF),
.CE(out0),
.D(\read_input[1]_i_1_n_0 ),
.Q(write_output[1]),
.R(1'b0));
FDRE \write_output_reg[20]
(.C(ETH_CLK_OBUF),
.CE(out0),
.D(\read_input[20]_i_1_n_0 ),
.Q(write_output[20]),
.R(1'b0));
FDRE \write_output_reg[21]
(.C(ETH_CLK_OBUF),
.CE(out0),
.D(\read_input[21]_i_1_n_0 ),
.Q(write_output[21]),
.R(1'b0));
FDRE \write_output_reg[22]
(.C(ETH_CLK_OBUF),
.CE(out0),
.D(\read_input[22]_i_1_n_0 ),
.Q(write_output[22]),
.R(1'b0));
FDRE \write_output_reg[23]
(.C(ETH_CLK_OBUF),
.CE(out0),
.D(\read_input[23]_i_1_n_0 ),
.Q(write_output[23]),
.R(1'b0));
FDRE \write_output_reg[24]
(.C(ETH_CLK_OBUF),
.CE(out0),
.D(\read_input[24]_i_1_n_0 ),
.Q(write_output[24]),
.R(1'b0));
FDRE \write_output_reg[25]
(.C(ETH_CLK_OBUF),
.CE(out0),
.D(\read_input[25]_i_1_n_0 ),
.Q(write_output[25]),
.R(1'b0));
FDRE \write_output_reg[26]
(.C(ETH_CLK_OBUF),
.CE(out0),
.D(\read_input[26]_i_1_n_0 ),
.Q(write_output[26]),
.R(1'b0));
FDRE \write_output_reg[27]
(.C(ETH_CLK_OBUF),
.CE(out0),
.D(\read_input[27]_i_1_n_0 ),
.Q(write_output[27]),
.R(1'b0));
FDRE \write_output_reg[28]
(.C(ETH_CLK_OBUF),
.CE(out0),
.D(\read_input[28]_i_1_n_0 ),
.Q(write_output[28]),
.R(1'b0));
FDRE \write_output_reg[29]
(.C(ETH_CLK_OBUF),
.CE(out0),
.D(\read_input[29]_i_1_n_0 ),
.Q(write_output[29]),
.R(1'b0));
FDRE \write_output_reg[2]
(.C(ETH_CLK_OBUF),
.CE(out0),
.D(\read_input[2]_i_1_n_0 ),
.Q(write_output[2]),
.R(1'b0));
FDRE \write_output_reg[30]
(.C(ETH_CLK_OBUF),
.CE(out0),
.D(\read_input[30]_i_1_n_0 ),
.Q(write_output[30]),
.R(1'b0));
FDRE \write_output_reg[31]
(.C(ETH_CLK_OBUF),
.CE(out0),
.D(\read_input[31]_i_2_n_0 ),
.Q(write_output[31]),
.R(1'b0));
FDRE \write_output_reg[3]
(.C(ETH_CLK_OBUF),
.CE(out0),
.D(\read_input[3]_i_1_n_0 ),
.Q(write_output[3]),
.R(1'b0));
FDRE \write_output_reg[4]
(.C(ETH_CLK_OBUF),
.CE(out0),
.D(\read_input[4]_i_1_n_0 ),
.Q(write_output[4]),
.R(1'b0));
FDRE \write_output_reg[5]
(.C(ETH_CLK_OBUF),
.CE(out0),
.D(\read_input[5]_i_1_n_0 ),
.Q(write_output[5]),
.R(1'b0));
FDRE \write_output_reg[6]
(.C(ETH_CLK_OBUF),
.CE(out0),
.D(\read_input[6]_i_1_n_0 ),
.Q(write_output[6]),
.R(1'b0));
FDRE \write_output_reg[7]
(.C(ETH_CLK_OBUF),
.CE(out0),
.D(\read_input[7]_i_1_n_0 ),
.Q(write_output[7]),
.R(1'b0));
FDRE \write_output_reg[8]
(.C(ETH_CLK_OBUF),
.CE(out0),
.D(\read_input[8]_i_1_n_0 ),
.Q(write_output[8]),
.R(1'b0));
FDRE \write_output_reg[9]
(.C(ETH_CLK_OBUF),
.CE(out0),
.D(\read_input[9]_i_1_n_0 ),
.Q(write_output[9]),
.R(1'b0));
LUT3 #(
.INIT(8'hB8))
\write_value[0]_i_1
(.I0(result[0]),
.I1(operand_b1),
.I2(register_b[0]),
.O(store_data[0]));
LUT3 #(
.INIT(8'hB8))
\write_value[1]_i_1
(.I0(result[1]),
.I1(operand_b1),
.I2(register_b[1]),
.O(store_data[1]));
LUT6 #(
.INIT(64'h2002000000002002))
\write_value[1]_i_2
(.I0(write_enable_reg_n_0),
.I1(\write_value[7]_i_2_n_0 ),
.I2(address_z_3[0]),
.I3(address_b_2[0]),
.I4(address_z_3[3]),
.I5(address_b_2[3]),
.O(operand_b1));
LUT5 #(
.INIT(32'hFFFB0008))
\write_value[2]_i_1
(.I0(result[2]),
.I1(write_enable_reg_n_0),
.I2(\write_value[7]_i_2_n_0 ),
.I3(\write_value[7]_i_3_n_0 ),
.I4(register_b[2]),
.O(store_data[2]));
LUT5 #(
.INIT(32'hFFFB0008))
\write_value[3]_i_1
(.I0(result[3]),
.I1(write_enable_reg_n_0),
.I2(\write_value[7]_i_2_n_0 ),
.I3(\write_value[7]_i_3_n_0 ),
.I4(register_b[3]),
.O(store_data[3]));
LUT5 #(
.INIT(32'hFFFB0008))
\write_value[4]_i_1
(.I0(result[4]),
.I1(write_enable_reg_n_0),
.I2(\write_value[7]_i_2_n_0 ),
.I3(\write_value[7]_i_3_n_0 ),
.I4(register_b[4]),
.O(store_data[4]));
LUT5 #(
.INIT(32'hFFFB0008))
\write_value[5]_i_1
(.I0(result[5]),
.I1(write_enable_reg_n_0),
.I2(\write_value[7]_i_2_n_0 ),
.I3(\write_value[7]_i_3_n_0 ),
.I4(register_b[5]),
.O(store_data[5]));
LUT5 #(
.INIT(32'hFFFB0008))
\write_value[6]_i_1
(.I0(result[6]),
.I1(write_enable_reg_n_0),
.I2(\write_value[7]_i_2_n_0 ),
.I3(\write_value[7]_i_3_n_0 ),
.I4(register_b[6]),
.O(store_data[6]));
LUT5 #(
.INIT(32'hFFFB0008))
\write_value[7]_i_1
(.I0(result[7]),
.I1(write_enable_reg_n_0),
.I2(\write_value[7]_i_2_n_0 ),
.I3(\write_value[7]_i_3_n_0 ),
.I4(register_b[7]),
.O(store_data[7]));
LUT4 #(
.INIT(16'h6FF6))
\write_value[7]_i_2
(.I0(address_z_3[2]),
.I1(address_b_2[2]),
.I2(address_z_3[1]),
.I3(address_b_2[1]),
.O(\write_value[7]_i_2_n_0 ));
LUT4 #(
.INIT(16'h6FF6))
\write_value[7]_i_3
(.I0(address_z_3[0]),
.I1(address_b_2[0]),
.I2(address_z_3[3]),
.I3(address_b_2[3]),
.O(\write_value[7]_i_3_n_0 ));
FDRE \write_value_reg[0]
(.C(ETH_CLK_OBUF),
.CE(out0),
.D(store_data[0]),
.Q(write_value[0]),
.R(1'b0));
FDRE \write_value_reg[1]
(.C(ETH_CLK_OBUF),
.CE(out0),
.D(store_data[1]),
.Q(write_value[1]),
.R(1'b0));
FDRE \write_value_reg[2]
(.C(ETH_CLK_OBUF),
.CE(out0),
.D(store_data[2]),
.Q(write_value[2]),
.R(1'b0));
FDRE \write_value_reg[3]
(.C(ETH_CLK_OBUF),
.CE(out0),
.D(store_data[3]),
.Q(write_value[3]),
.R(1'b0));
FDRE \write_value_reg[4]
(.C(ETH_CLK_OBUF),
.CE(out0),
.D(store_data[4]),
.Q(write_value[4]),
.R(1'b0));
FDRE \write_value_reg[5]
(.C(ETH_CLK_OBUF),
.CE(out0),
.D(store_data[5]),
.Q(write_value[5]),
.R(1'b0));
FDRE \write_value_reg[6]
(.C(ETH_CLK_OBUF),
.CE(out0),
.D(store_data[6]),
.Q(write_value[6]),
.R(1'b0));
FDRE \write_value_reg[7]
(.C(ETH_CLK_OBUF),
.CE(out0),
.D(store_data[7]),
.Q(write_value[7]),
.R(1'b0));
endmodule
|
module pwm_audio
(JC_IBUF,
INTERNAL_RST_reg,
ETH_CLK_OBUF);
output [0:0]JC_IBUF;
input INTERNAL_RST_reg;
input ETH_CLK_OBUF;
wire \COUNT[10]_i_2_n_0 ;
wire \COUNT[10]_i_4_n_0 ;
wire \COUNT[10]_i_5_n_0 ;
wire \COUNT[10]_i_6_n_0 ;
wire \COUNT[9]_i_2_n_0 ;
wire [10:0]COUNT_reg__0;
wire ETH_CLK_OBUF;
wire INTERNAL_RST_reg;
wire [0:0]JC_IBUF;
wire STATE;
wire STATE_i_1_n_0;
wire STATE_reg_n_0;
wire S_DATA_IN_ACK_i_1_n_0;
wire [10:0]p_0_in;
(* SOFT_HLUTNM = "soft_lutpair168" *)
LUT1 #(
.INIT(2'h1))
\COUNT[0]_i_1__4
(.I0(COUNT_reg__0[0]),
.O(p_0_in[0]));
LUT2 #(
.INIT(4'h2))
\COUNT[10]_i_1
(.I0(JC_IBUF),
.I1(STATE_reg_n_0),
.O(STATE));
LUT2 #(
.INIT(4'h2))
\COUNT[10]_i_2
(.I0(STATE_reg_n_0),
.I1(\COUNT[10]_i_4_n_0 ),
.O(\COUNT[10]_i_2_n_0 ));
LUT3 #(
.INIT(8'h6A))
\COUNT[10]_i_3
(.I0(COUNT_reg__0[10]),
.I1(\COUNT[10]_i_5_n_0 ),
.I2(COUNT_reg__0[9]),
.O(p_0_in[10]));
LUT6 #(
.INIT(64'h0000800000000000))
\COUNT[10]_i_4
(.I0(COUNT_reg__0[2]),
.I1(COUNT_reg__0[3]),
.I2(COUNT_reg__0[6]),
.I3(COUNT_reg__0[5]),
.I4(COUNT_reg__0[7]),
.I5(\COUNT[10]_i_6_n_0 ),
.O(\COUNT[10]_i_4_n_0 ));
LUT5 #(
.INIT(32'h80000000))
\COUNT[10]_i_5
(.I0(COUNT_reg__0[8]),
.I1(COUNT_reg__0[7]),
.I2(\COUNT[9]_i_2_n_0 ),
.I3(COUNT_reg__0[6]),
.I4(COUNT_reg__0[5]),
.O(\COUNT[10]_i_5_n_0 ));
LUT6 #(
.INIT(64'h0000000000000004))
\COUNT[10]_i_6
(.I0(COUNT_reg__0[9]),
.I1(COUNT_reg__0[10]),
.I2(COUNT_reg__0[4]),
.I3(COUNT_reg__0[8]),
.I4(COUNT_reg__0[0]),
.I5(COUNT_reg__0[1]),
.O(\COUNT[10]_i_6_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair168" *)
LUT2 #(
.INIT(4'h6))
\COUNT[1]_i_1__4
(.I0(COUNT_reg__0[0]),
.I1(COUNT_reg__0[1]),
.O(p_0_in[1]));
(* SOFT_HLUTNM = "soft_lutpair167" *)
LUT3 #(
.INIT(8'h78))
\COUNT[2]_i_1__3
(.I0(COUNT_reg__0[0]),
.I1(COUNT_reg__0[1]),
.I2(COUNT_reg__0[2]),
.O(p_0_in[2]));
(* SOFT_HLUTNM = "soft_lutpair167" *)
LUT4 #(
.INIT(16'h6AAA))
\COUNT[3]_i_1__2
(.I0(COUNT_reg__0[3]),
.I1(COUNT_reg__0[0]),
.I2(COUNT_reg__0[1]),
.I3(COUNT_reg__0[2]),
.O(p_0_in[3]));
LUT5 #(
.INIT(32'h7FFF8000))
\COUNT[4]_i_1__2
(.I0(COUNT_reg__0[1]),
.I1(COUNT_reg__0[0]),
.I2(COUNT_reg__0[3]),
.I3(COUNT_reg__0[2]),
.I4(COUNT_reg__0[4]),
.O(p_0_in[4]));
LUT6 #(
.INIT(64'h6AAAAAAAAAAAAAAA))
\COUNT[5]_i_1__2
(.I0(COUNT_reg__0[5]),
.I1(COUNT_reg__0[1]),
.I2(COUNT_reg__0[0]),
.I3(COUNT_reg__0[3]),
.I4(COUNT_reg__0[2]),
.I5(COUNT_reg__0[4]),
.O(p_0_in[5]));
(* SOFT_HLUTNM = "soft_lutpair166" *)
LUT3 #(
.INIT(8'h6A))
\COUNT[6]_i_1__2
(.I0(COUNT_reg__0[6]),
.I1(\COUNT[9]_i_2_n_0 ),
.I2(COUNT_reg__0[5]),
.O(p_0_in[6]));
(* SOFT_HLUTNM = "soft_lutpair166" *)
LUT4 #(
.INIT(16'h6AAA))
\COUNT[7]_i_1__2
(.I0(COUNT_reg__0[7]),
.I1(COUNT_reg__0[5]),
.I2(COUNT_reg__0[6]),
.I3(\COUNT[9]_i_2_n_0 ),
.O(p_0_in[7]));
LUT5 #(
.INIT(32'h6AAAAAAA))
\COUNT[8]_i_1
(.I0(COUNT_reg__0[8]),
.I1(COUNT_reg__0[7]),
.I2(\COUNT[9]_i_2_n_0 ),
.I3(COUNT_reg__0[6]),
.I4(COUNT_reg__0[5]),
.O(p_0_in[8]));
LUT6 #(
.INIT(64'h6AAAAAAAAAAAAAAA))
\COUNT[9]_i_1
(.I0(COUNT_reg__0[9]),
.I1(COUNT_reg__0[5]),
.I2(COUNT_reg__0[6]),
.I3(\COUNT[9]_i_2_n_0 ),
.I4(COUNT_reg__0[7]),
.I5(COUNT_reg__0[8]),
.O(p_0_in[9]));
LUT5 #(
.INIT(32'h80000000))
\COUNT[9]_i_2
(.I0(COUNT_reg__0[4]),
.I1(COUNT_reg__0[2]),
.I2(COUNT_reg__0[3]),
.I3(COUNT_reg__0[0]),
.I4(COUNT_reg__0[1]),
.O(\COUNT[9]_i_2_n_0 ));
FDRE \COUNT_reg[0]
(.C(ETH_CLK_OBUF),
.CE(\COUNT[10]_i_2_n_0 ),
.D(p_0_in[0]),
.Q(COUNT_reg__0[0]),
.R(STATE));
FDRE \COUNT_reg[10]
(.C(ETH_CLK_OBUF),
.CE(\COUNT[10]_i_2_n_0 ),
.D(p_0_in[10]),
.Q(COUNT_reg__0[10]),
.R(STATE));
FDRE \COUNT_reg[1]
(.C(ETH_CLK_OBUF),
.CE(\COUNT[10]_i_2_n_0 ),
.D(p_0_in[1]),
.Q(COUNT_reg__0[1]),
.R(STATE));
FDRE \COUNT_reg[2]
(.C(ETH_CLK_OBUF),
.CE(\COUNT[10]_i_2_n_0 ),
.D(p_0_in[2]),
.Q(COUNT_reg__0[2]),
.R(STATE));
FDRE \COUNT_reg[3]
(.C(ETH_CLK_OBUF),
.CE(\COUNT[10]_i_2_n_0 ),
.D(p_0_in[3]),
.Q(COUNT_reg__0[3]),
.R(STATE));
FDRE \COUNT_reg[4]
(.C(ETH_CLK_OBUF),
.CE(\COUNT[10]_i_2_n_0 ),
.D(p_0_in[4]),
.Q(COUNT_reg__0[4]),
.R(STATE));
FDRE \COUNT_reg[5]
(.C(ETH_CLK_OBUF),
.CE(\COUNT[10]_i_2_n_0 ),
.D(p_0_in[5]),
.Q(COUNT_reg__0[5]),
.R(STATE));
FDRE \COUNT_reg[6]
(.C(ETH_CLK_OBUF),
.CE(\COUNT[10]_i_2_n_0 ),
.D(p_0_in[6]),
.Q(COUNT_reg__0[6]),
.R(STATE));
FDRE \COUNT_reg[7]
(.C(ETH_CLK_OBUF),
.CE(\COUNT[10]_i_2_n_0 ),
.D(p_0_in[7]),
.Q(COUNT_reg__0[7]),
.R(STATE));
FDRE \COUNT_reg[8]
(.C(ETH_CLK_OBUF),
.CE(\COUNT[10]_i_2_n_0 ),
.D(p_0_in[8]),
.Q(COUNT_reg__0[8]),
.R(STATE));
FDRE \COUNT_reg[9]
(.C(ETH_CLK_OBUF),
.CE(\COUNT[10]_i_2_n_0 ),
.D(p_0_in[9]),
.Q(COUNT_reg__0[9]),
.R(STATE));
LUT3 #(
.INIT(8'h4E))
STATE_i_1
(.I0(STATE_reg_n_0),
.I1(JC_IBUF),
.I2(\COUNT[10]_i_4_n_0 ),
.O(STATE_i_1_n_0));
FDRE STATE_reg
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(STATE_i_1_n_0),
.Q(STATE_reg_n_0),
.R(INTERNAL_RST_reg));
LUT3 #(
.INIT(8'h09))
S_DATA_IN_ACK_i_1
(.I0(STATE_reg_n_0),
.I1(JC_IBUF),
.I2(INTERNAL_RST_reg),
.O(S_DATA_IN_ACK_i_1_n_0));
FDRE S_DATA_IN_ACK_reg
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(S_DATA_IN_ACK_i_1_n_0),
.Q(JC_IBUF),
.R(1'b0));
endmodule
|
module rmii_ethernet
(TXEN_OBUF,
TXD_OBUF,
ETH_CLK_OBUF,
RXDV_IBUF,
RXER_IBUF,
INTERNAL_RST_reg,
D);
output TXEN_OBUF;
output [1:0]TXD_OBUF;
input ETH_CLK_OBUF;
input RXDV_IBUF;
input RXER_IBUF;
input INTERNAL_RST_reg;
input [1:0]D;
wire DONE;
wire DONE_DEL;
wire DONE_SYNC;
wire DONE_i_1_n_0;
wire ETH_CLK_OBUF;
wire GO;
wire GO_DEL;
wire GO_SYNC;
wire GO_i_1_n_0;
wire INTERNAL_RST_reg;
wire NEXTCRC32_D80177_out;
wire NEXTCRC32_D80181_out;
wire NEXTCRC32_D80189_out;
wire NEXTCRC32_D80195_out;
wire NEXTCRC32_D80203_out;
wire NEXTCRC32_D80217_out;
wire NEXTCRC32_D8070_out;
wire NEXTCRC32_D8074_out;
wire \PREAMBLE_COUNT[0]_i_1_n_0 ;
wire \PREAMBLE_COUNT[1]_i_1_n_0 ;
wire \PREAMBLE_COUNT[2]_i_1_n_0 ;
wire \PREAMBLE_COUNT[3]_i_1_n_0 ;
wire \PREAMBLE_COUNT[4]_i_1_n_0 ;
wire \PREAMBLE_COUNT[4]_i_2_n_0 ;
wire \PREAMBLE_COUNT[4]_i_3_n_0 ;
wire \PREAMBLE_COUNT[4]_i_4_n_0 ;
wire \PREAMBLE_COUNT_reg_n_0_[0] ;
wire \PREAMBLE_COUNT_reg_n_0_[1] ;
wire \PREAMBLE_COUNT_reg_n_0_[2] ;
wire \PREAMBLE_COUNT_reg_n_0_[3] ;
wire \PREAMBLE_COUNT_reg_n_0_[4] ;
wire S_TX_ACK_i_1_n_0;
wire S_TX_ACK_reg_n_0;
wire \TXD[0]_i_10_n_0 ;
wire \TXD[0]_i_11_n_0 ;
wire \TXD[0]_i_1_n_0 ;
wire \TXD[0]_i_2_n_0 ;
wire \TXD[0]_i_3_n_0 ;
wire \TXD[0]_i_6_n_0 ;
wire \TXD[0]_i_7_n_0 ;
wire \TXD[0]_i_8_n_0 ;
wire \TXD[0]_i_9_n_0 ;
wire \TXD[1]_i_10_n_0 ;
wire \TXD[1]_i_11_n_0 ;
wire \TXD[1]_i_12_n_0 ;
wire \TXD[1]_i_1_n_0 ;
wire \TXD[1]_i_2_n_0 ;
wire \TXD[1]_i_3_n_0 ;
wire \TXD[1]_i_4_n_0 ;
wire \TXD[1]_i_7_n_0 ;
wire \TXD[1]_i_8_n_0 ;
wire \TXD[1]_i_9_n_0 ;
wire [1:0]TXD_OBUF;
wire \TXD_reg[0]_i_4_n_0 ;
wire \TXD_reg[0]_i_5_n_0 ;
wire \TXD_reg[1]_i_5_n_0 ;
wire \TXD_reg[1]_i_6_n_0 ;
wire TXEN_OBUF;
wire TXEN_i_1_n_0;
wire \TX_CRC[0]_i_1_n_0 ;
wire \TX_CRC[0]_i_2_n_0 ;
wire \TX_CRC[10]_i_3_n_0 ;
wire \TX_CRC[10]_i_4_n_0 ;
wire \TX_CRC[10]_i_5_n_0 ;
wire \TX_CRC[11]_i_1_n_0 ;
wire \TX_CRC[11]_i_2_n_0 ;
wire \TX_CRC[11]_i_3_n_0 ;
wire \TX_CRC[11]_i_4_n_0 ;
wire \TX_CRC[12]_i_2_n_0 ;
wire \TX_CRC[12]_i_3_n_0 ;
wire \TX_CRC[12]_i_4_n_0 ;
wire \TX_CRC[12]_i_5_n_0 ;
wire \TX_CRC[12]_i_6_n_0 ;
wire \TX_CRC[12]_i_7_n_0 ;
wire \TX_CRC[12]_i_8_n_0 ;
wire \TX_CRC[13]_i_3_n_0 ;
wire \TX_CRC[13]_i_4_n_0 ;
wire \TX_CRC[14]_i_2_n_0 ;
wire \TX_CRC[14]_i_3_n_0 ;
wire \TX_CRC[14]_i_4_n_0 ;
wire \TX_CRC[14]_i_5_n_0 ;
wire \TX_CRC[15]_i_1_n_0 ;
wire \TX_CRC[15]_i_2_n_0 ;
wire \TX_CRC[15]_i_3_n_0 ;
wire \TX_CRC[15]_i_4_n_0 ;
wire \TX_CRC[15]_i_5_n_0 ;
wire \TX_CRC[16]_i_1_n_0 ;
wire \TX_CRC[16]_i_2_n_0 ;
wire \TX_CRC[16]_i_3_n_0 ;
wire \TX_CRC[17]_i_3_n_0 ;
wire \TX_CRC[17]_i_5_n_0 ;
wire \TX_CRC[18]_i_2_n_0 ;
wire \TX_CRC[18]_i_3_n_0 ;
wire \TX_CRC[18]_i_4_n_0 ;
wire \TX_CRC[19]_i_1_n_0 ;
wire \TX_CRC[19]_i_2_n_0 ;
wire \TX_CRC[1]_i_2_n_0 ;
wire \TX_CRC[20]_i_1_n_0 ;
wire \TX_CRC[21]_i_1_n_0 ;
wire \TX_CRC[22]_i_1_n_0 ;
wire \TX_CRC[23]_i_1_n_0 ;
wire \TX_CRC[23]_i_2_n_0 ;
wire \TX_CRC[23]_i_3_n_0 ;
wire \TX_CRC[24]_i_3_n_0 ;
wire \TX_CRC[24]_i_4_n_0 ;
wire \TX_CRC[25]_i_2_n_0 ;
wire \TX_CRC[25]_i_3_n_0 ;
wire \TX_CRC[26]_i_1_n_0 ;
wire \TX_CRC[26]_i_2_n_0 ;
wire \TX_CRC[26]_i_3_n_0 ;
wire \TX_CRC[26]_i_4_n_0 ;
wire \TX_CRC[27]_i_1_n_0 ;
wire \TX_CRC[27]_i_2_n_0 ;
wire \TX_CRC[27]_i_3_n_0 ;
wire \TX_CRC[27]_i_4_n_0 ;
wire \TX_CRC[28]_i_1_n_0 ;
wire \TX_CRC[28]_i_2_n_0 ;
wire \TX_CRC[28]_i_3_n_0 ;
wire \TX_CRC[29]_i_2_n_0 ;
wire \TX_CRC[29]_i_3_n_0 ;
wire \TX_CRC[29]_i_4_n_0 ;
wire \TX_CRC[29]_i_5_n_0 ;
wire \TX_CRC[2]_i_1_n_0 ;
wire \TX_CRC[2]_i_2_n_0 ;
wire \TX_CRC[2]_i_3_n_0 ;
wire \TX_CRC[2]_i_4_n_0 ;
wire \TX_CRC[30]_i_2_n_0 ;
wire \TX_CRC[30]_i_3_n_0 ;
wire \TX_CRC[31]_i_1_n_0 ;
wire \TX_CRC[31]_i_2_n_0 ;
wire \TX_CRC[31]_i_3_n_0 ;
wire \TX_CRC[3]_i_3_n_0 ;
wire \TX_CRC[3]_i_4_n_0 ;
wire \TX_CRC[4]_i_2_n_0 ;
wire \TX_CRC[4]_i_3_n_0 ;
wire \TX_CRC[4]_i_4_n_0 ;
wire \TX_CRC[4]_i_5_n_0 ;
wire \TX_CRC[5]_i_4_n_0 ;
wire \TX_CRC[5]_i_5_n_0 ;
wire \TX_CRC[5]_i_6_n_0 ;
wire \TX_CRC[5]_i_7_n_0 ;
wire \TX_CRC[5]_i_8_n_0 ;
wire \TX_CRC[5]_i_9_n_0 ;
wire \TX_CRC[6]_i_2_n_0 ;
wire \TX_CRC[6]_i_3_n_0 ;
wire \TX_CRC[6]_i_4_n_0 ;
wire \TX_CRC[6]_i_5_n_0 ;
wire \TX_CRC[6]_i_6_n_0 ;
wire \TX_CRC[7]_i_1_n_0 ;
wire \TX_CRC[7]_i_2_n_0 ;
wire \TX_CRC[7]_i_3_n_0 ;
wire \TX_CRC[7]_i_4_n_0 ;
wire \TX_CRC[8]_i_1_n_0 ;
wire \TX_CRC[9]_i_1_n_0 ;
wire \TX_CRC[9]_i_2_n_0 ;
wire \TX_CRC[9]_i_3_n_0 ;
wire \TX_CRC[9]_i_4_n_0 ;
wire \TX_CRC_reg[10]_i_1_n_0 ;
wire \TX_CRC_reg[12]_i_1_n_0 ;
wire \TX_CRC_reg[13]_i_1_n_0 ;
wire \TX_CRC_reg[14]_i_1_n_0 ;
wire \TX_CRC_reg[17]_i_1_n_0 ;
wire \TX_CRC_reg[18]_i_1_n_0 ;
wire \TX_CRC_reg[1]_i_1_n_0 ;
wire \TX_CRC_reg[24]_i_1_n_0 ;
wire \TX_CRC_reg[25]_i_1_n_0 ;
wire \TX_CRC_reg[29]_i_1_n_0 ;
wire \TX_CRC_reg[30]_i_1_n_0 ;
wire \TX_CRC_reg[3]_i_1_n_0 ;
wire \TX_CRC_reg[4]_i_1_n_0 ;
wire \TX_CRC_reg[5]_i_1_n_0 ;
wire \TX_CRC_reg[6]_i_1_n_0 ;
wire \TX_CRC_reg_n_0_[0] ;
wire \TX_CRC_reg_n_0_[10] ;
wire \TX_CRC_reg_n_0_[11] ;
wire \TX_CRC_reg_n_0_[12] ;
wire \TX_CRC_reg_n_0_[13] ;
wire \TX_CRC_reg_n_0_[14] ;
wire \TX_CRC_reg_n_0_[15] ;
wire \TX_CRC_reg_n_0_[16] ;
wire \TX_CRC_reg_n_0_[17] ;
wire \TX_CRC_reg_n_0_[18] ;
wire \TX_CRC_reg_n_0_[19] ;
wire \TX_CRC_reg_n_0_[20] ;
wire \TX_CRC_reg_n_0_[21] ;
wire \TX_CRC_reg_n_0_[22] ;
wire \TX_CRC_reg_n_0_[23] ;
wire \TX_CRC_reg_n_0_[8] ;
wire \TX_CRC_reg_n_0_[9] ;
wire [10:1]TX_IN_COUNT;
wire \TX_IN_COUNT[10]_i_1_n_0 ;
wire \TX_IN_COUNT[10]_i_2_n_0 ;
wire \TX_IN_COUNT[10]_i_3_n_0 ;
wire \TX_IN_COUNT[10]_i_4_n_0 ;
wire \TX_IN_COUNT[1]_i_1_n_0 ;
wire \TX_IN_COUNT[2]_i_1_n_0 ;
wire \TX_IN_COUNT[3]_i_1_n_0 ;
wire \TX_IN_COUNT[4]_i_1_n_0 ;
wire \TX_IN_COUNT[5]_i_1_n_0 ;
wire \TX_IN_COUNT[6]_i_1_n_0 ;
wire \TX_IN_COUNT[7]_i_1_n_0 ;
wire \TX_IN_COUNT[8]_i_1_n_0 ;
wire \TX_IN_COUNT[9]_i_1_n_0 ;
wire TX_MEMORY_reg_ENBWREN_cooolgate_en_sig_9;
wire TX_MEMORY_reg_n_59;
wire TX_MEMORY_reg_n_67;
wire [0:0]TX_OUT_COUNT0_in;
wire \TX_OUT_COUNT[10]_i_1_n_0 ;
wire \TX_OUT_COUNT[10]_i_2_n_0 ;
wire \TX_OUT_COUNT[10]_i_3_n_0 ;
wire \TX_OUT_COUNT[10]_i_4_n_0 ;
wire \TX_OUT_COUNT[10]_i_5_n_0 ;
wire \TX_OUT_COUNT[10]_i_6_n_0 ;
wire \TX_OUT_COUNT[10]_i_7_n_0 ;
wire \TX_OUT_COUNT[10]_i_8_n_0 ;
wire \TX_OUT_COUNT[1]_i_1_n_0 ;
wire \TX_OUT_COUNT[2]_i_1_n_0 ;
wire \TX_OUT_COUNT[3]_i_1_n_0 ;
wire \TX_OUT_COUNT[4]_i_1_n_0 ;
wire \TX_OUT_COUNT[5]_i_1_n_0 ;
wire \TX_OUT_COUNT[6]_i_1_n_0 ;
wire \TX_OUT_COUNT[7]_i_1_n_0 ;
wire \TX_OUT_COUNT[8]_i_1_n_0 ;
wire \TX_OUT_COUNT[8]_i_2_n_0 ;
wire \TX_OUT_COUNT[9]_i_1_n_0 ;
wire \TX_OUT_COUNT_reg_n_0_[0] ;
wire \TX_OUT_COUNT_reg_n_0_[10] ;
wire \TX_OUT_COUNT_reg_n_0_[1] ;
wire \TX_OUT_COUNT_reg_n_0_[2] ;
wire \TX_OUT_COUNT_reg_n_0_[3] ;
wire \TX_OUT_COUNT_reg_n_0_[4] ;
wire \TX_OUT_COUNT_reg_n_0_[5] ;
wire \TX_OUT_COUNT_reg_n_0_[6] ;
wire \TX_OUT_COUNT_reg_n_0_[7] ;
wire \TX_OUT_COUNT_reg_n_0_[8] ;
wire \TX_OUT_COUNT_reg_n_0_[9] ;
wire \TX_PACKET_STATE[0]_i_1_n_0 ;
wire \TX_PACKET_STATE[1]_i_10_n_0 ;
wire \TX_PACKET_STATE[1]_i_11_n_0 ;
wire \TX_PACKET_STATE[1]_i_12_n_0 ;
wire \TX_PACKET_STATE[1]_i_13_n_0 ;
wire \TX_PACKET_STATE[1]_i_1_n_0 ;
wire \TX_PACKET_STATE[1]_i_4_n_0 ;
wire \TX_PACKET_STATE[1]_i_5_n_0 ;
wire \TX_PACKET_STATE[1]_i_6_n_0 ;
wire \TX_PACKET_STATE[1]_i_7_n_0 ;
wire \TX_PACKET_STATE[1]_i_8_n_0 ;
wire \TX_PACKET_STATE[1]_i_9_n_0 ;
wire \TX_PACKET_STATE_reg[1]_i_2_n_2 ;
wire \TX_PACKET_STATE_reg[1]_i_3_n_0 ;
wire \TX_PACKET_STATE_reg_n_0_[0] ;
wire \TX_PACKET_STATE_reg_n_0_[1] ;
wire \TX_PHY_STATE[0]_i_1_n_0 ;
wire \TX_PHY_STATE[1]_i_1_n_0 ;
wire \TX_PHY_STATE[2]_i_1_n_0 ;
wire \TX_PHY_STATE[2]_i_2_n_0 ;
wire \TX_PHY_STATE[2]_i_3_n_0 ;
wire \TX_PHY_STATE[2]_i_4_n_0 ;
wire \TX_PHY_STATE[3]_i_1_n_0 ;
wire \TX_PHY_STATE[3]_i_2_n_0 ;
wire \TX_PHY_STATE[3]_i_3_n_0 ;
wire \TX_PHY_STATE[3]_i_4_n_0 ;
wire \TX_PHY_STATE[3]_i_5_n_0 ;
wire \TX_PHY_STATE[4]_i_1_n_0 ;
wire \TX_PHY_STATE[4]_i_2_n_0 ;
wire \TX_PHY_STATE[4]_i_3_n_0 ;
wire \TX_PHY_STATE[4]_i_4_n_0 ;
wire \TX_PHY_STATE_reg_n_0_[0] ;
wire \TX_PHY_STATE_reg_n_0_[1] ;
wire \TX_PHY_STATE_reg_n_0_[2] ;
wire \TX_PHY_STATE_reg_n_0_[3] ;
wire \TX_PHY_STATE_reg_n_0_[4] ;
wire [10:0]TX_READ_ADDRESS;
wire [10:1]TX_READ_ADDRESS0;
wire \TX_READ_ADDRESS_rep[0]_i_1_n_0 ;
wire \TX_READ_ADDRESS_rep[9]_i_1_n_0 ;
wire \TX_READ_ADDRESS_rep[9]_i_2_n_0 ;
wire \TX_READ_ADDRESS_rep[9]_i_4_n_0 ;
wire TX_WRITE;
wire [10:0]TX_WRITE_ADDRESS;
wire \TX_WRITE_ADDRESS[0]_i_1_n_0 ;
wire \TX_WRITE_ADDRESS[10]_i_1_n_0 ;
wire \TX_WRITE_ADDRESS[10]_i_2_n_0 ;
wire \TX_WRITE_ADDRESS[10]_i_3_n_0 ;
wire \TX_WRITE_ADDRESS[1]_i_1_n_0 ;
wire \TX_WRITE_ADDRESS[2]_i_1_n_0 ;
wire \TX_WRITE_ADDRESS[3]_i_1_n_0 ;
wire \TX_WRITE_ADDRESS[4]_i_1_n_0 ;
wire \TX_WRITE_ADDRESS[5]_i_1_n_0 ;
wire \TX_WRITE_ADDRESS[5]_i_2_n_0 ;
wire \TX_WRITE_ADDRESS[6]_i_1_n_0 ;
wire \TX_WRITE_ADDRESS[7]_i_1_n_0 ;
wire \TX_WRITE_ADDRESS[8]_i_1_n_0 ;
wire \TX_WRITE_ADDRESS[9]_i_1_n_0 ;
wire \TX_WRITE_ADDRESS[9]_i_2_n_0 ;
wire [10:0]TX_WRITE_ADDRESS_DEL;
wire TX_WRITE_i_1_n_0;
wire p_0_in167_in;
wire p_0_in66_in;
wire [1:0]p_16_in;
wire [1:0]p_17_in;
wire [1:0]p_18_in;
wire p_1_in126_in;
wire p_1_in128_in;
wire p_1_in130_in;
wire p_1_in132_in;
wire p_1_in133_in;
wire p_1_in135_in;
wire p_1_in136_in;
wire p_202_in;
wire p_206_in;
wire [1:0]p_20_in;
wire p_214_in;
wire p_216_in;
wire [1:0]p_21_in;
wire [1:0]p_22_in;
wire [7:0]slv1_out;
wire NLW_TX_MEMORY_reg_CASCADEOUTA_UNCONNECTED;
wire NLW_TX_MEMORY_reg_CASCADEOUTB_UNCONNECTED;
wire NLW_TX_MEMORY_reg_DBITERR_UNCONNECTED;
wire NLW_TX_MEMORY_reg_INJECTDBITERR_UNCONNECTED;
wire NLW_TX_MEMORY_reg_INJECTSBITERR_UNCONNECTED;
wire NLW_TX_MEMORY_reg_REGCEAREGCE_UNCONNECTED;
wire NLW_TX_MEMORY_reg_REGCEB_UNCONNECTED;
wire NLW_TX_MEMORY_reg_SBITERR_UNCONNECTED;
wire [31:0]NLW_TX_MEMORY_reg_DOADO_UNCONNECTED;
wire [31:16]NLW_TX_MEMORY_reg_DOBDO_UNCONNECTED;
wire [3:0]NLW_TX_MEMORY_reg_DOPADOP_UNCONNECTED;
wire [3:0]NLW_TX_MEMORY_reg_DOPBDOP_UNCONNECTED;
wire [7:0]NLW_TX_MEMORY_reg_ECCPARITY_UNCONNECTED;
wire [8:0]NLW_TX_MEMORY_reg_RDADDRECC_UNCONNECTED;
wire [3:0]\NLW_TX_PACKET_STATE_reg[1]_i_2_CO_UNCONNECTED ;
wire [3:0]\NLW_TX_PACKET_STATE_reg[1]_i_2_O_UNCONNECTED ;
wire [2:0]\NLW_TX_PACKET_STATE_reg[1]_i_3_CO_UNCONNECTED ;
wire [3:0]\NLW_TX_PACKET_STATE_reg[1]_i_3_O_UNCONNECTED ;
FDRE DONE_DEL_reg
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(DONE),
.Q(DONE_DEL),
.R(1'b0));
FDRE DONE_SYNC_reg
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(DONE_DEL),
.Q(DONE_SYNC),
.R(1'b0));
LUT6 #(
.INIT(64'hBFFFFFFF80000000))
DONE_i_1
(.I0(GO_SYNC),
.I1(\TX_PHY_STATE_reg_n_0_[4] ),
.I2(\TX_PHY_STATE_reg_n_0_[3] ),
.I3(\TX_PHY_STATE_reg_n_0_[1] ),
.I4(\TX_PHY_STATE_reg_n_0_[2] ),
.I5(DONE),
.O(DONE_i_1_n_0));
FDRE DONE_reg
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(DONE_i_1_n_0),
.Q(DONE),
.R(INTERNAL_RST_reg));
FDRE GO_DEL_reg
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(GO),
.Q(GO_DEL),
.R(1'b0));
FDRE GO_SYNC_reg
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(GO_DEL),
.Q(GO_SYNC),
.R(1'b0));
LUT4 #(
.INIT(16'hF704))
GO_i_1
(.I0(DONE_SYNC),
.I1(\TX_PACKET_STATE_reg_n_0_[1] ),
.I2(\TX_PACKET_STATE_reg_n_0_[0] ),
.I3(GO),
.O(GO_i_1_n_0));
FDRE GO_reg
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(GO_i_1_n_0),
.Q(GO),
.R(INTERNAL_RST_reg));
LUT1 #(
.INIT(2'h1))
\PREAMBLE_COUNT[0]_i_1
(.I0(\PREAMBLE_COUNT_reg_n_0_[0] ),
.O(\PREAMBLE_COUNT[0]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair135" *)
LUT2 #(
.INIT(4'h9))
\PREAMBLE_COUNT[1]_i_1
(.I0(\PREAMBLE_COUNT_reg_n_0_[0] ),
.I1(\PREAMBLE_COUNT_reg_n_0_[1] ),
.O(\PREAMBLE_COUNT[1]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFDFDFDDD00000020))
\PREAMBLE_COUNT[2]_i_1
(.I0(\PREAMBLE_COUNT[4]_i_4_n_0 ),
.I1(\TX_PHY_STATE_reg_n_0_[4] ),
.I2(\TX_PHY_STATE_reg_n_0_[0] ),
.I3(\PREAMBLE_COUNT_reg_n_0_[0] ),
.I4(\PREAMBLE_COUNT_reg_n_0_[1] ),
.I5(\PREAMBLE_COUNT_reg_n_0_[2] ),
.O(\PREAMBLE_COUNT[2]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair135" *)
LUT4 #(
.INIT(16'hFE01))
\PREAMBLE_COUNT[3]_i_1
(.I0(\PREAMBLE_COUNT_reg_n_0_[2] ),
.I1(\PREAMBLE_COUNT_reg_n_0_[0] ),
.I2(\PREAMBLE_COUNT_reg_n_0_[1] ),
.I3(\PREAMBLE_COUNT_reg_n_0_[3] ),
.O(\PREAMBLE_COUNT[3]_i_1_n_0 ));
LUT3 #(
.INIT(8'h02))
\PREAMBLE_COUNT[4]_i_1
(.I0(\PREAMBLE_COUNT[4]_i_4_n_0 ),
.I1(\TX_PHY_STATE_reg_n_0_[4] ),
.I2(\TX_PHY_STATE_reg_n_0_[0] ),
.O(\PREAMBLE_COUNT[4]_i_1_n_0 ));
LUT2 #(
.INIT(4'h2))
\PREAMBLE_COUNT[4]_i_2
(.I0(\PREAMBLE_COUNT[4]_i_4_n_0 ),
.I1(\TX_PHY_STATE_reg_n_0_[4] ),
.O(\PREAMBLE_COUNT[4]_i_2_n_0 ));
LUT5 #(
.INIT(32'hFFFE0001))
\PREAMBLE_COUNT[4]_i_3
(.I0(\PREAMBLE_COUNT_reg_n_0_[3] ),
.I1(\PREAMBLE_COUNT_reg_n_0_[1] ),
.I2(\PREAMBLE_COUNT_reg_n_0_[0] ),
.I3(\PREAMBLE_COUNT_reg_n_0_[2] ),
.I4(\PREAMBLE_COUNT_reg_n_0_[4] ),
.O(\PREAMBLE_COUNT[4]_i_3_n_0 ));
LUT6 #(
.INIT(64'h0000000001110100))
\PREAMBLE_COUNT[4]_i_4
(.I0(\TX_PHY_STATE_reg_n_0_[1] ),
.I1(\TX_PHY_STATE_reg_n_0_[2] ),
.I2(\TX_PHY_STATE[4]_i_4_n_0 ),
.I3(\TX_PHY_STATE_reg_n_0_[0] ),
.I4(GO_SYNC),
.I5(\TX_PHY_STATE_reg_n_0_[3] ),
.O(\PREAMBLE_COUNT[4]_i_4_n_0 ));
FDSE \PREAMBLE_COUNT_reg[0]
(.C(ETH_CLK_OBUF),
.CE(\PREAMBLE_COUNT[4]_i_2_n_0 ),
.D(\PREAMBLE_COUNT[0]_i_1_n_0 ),
.Q(\PREAMBLE_COUNT_reg_n_0_[0] ),
.S(\PREAMBLE_COUNT[4]_i_1_n_0 ));
FDSE \PREAMBLE_COUNT_reg[1]
(.C(ETH_CLK_OBUF),
.CE(\PREAMBLE_COUNT[4]_i_2_n_0 ),
.D(\PREAMBLE_COUNT[1]_i_1_n_0 ),
.Q(\PREAMBLE_COUNT_reg_n_0_[1] ),
.S(\PREAMBLE_COUNT[4]_i_1_n_0 ));
FDRE \PREAMBLE_COUNT_reg[2]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(\PREAMBLE_COUNT[2]_i_1_n_0 ),
.Q(\PREAMBLE_COUNT_reg_n_0_[2] ),
.R(1'b0));
FDSE \PREAMBLE_COUNT_reg[3]
(.C(ETH_CLK_OBUF),
.CE(\PREAMBLE_COUNT[4]_i_2_n_0 ),
.D(\PREAMBLE_COUNT[3]_i_1_n_0 ),
.Q(\PREAMBLE_COUNT_reg_n_0_[3] ),
.S(\PREAMBLE_COUNT[4]_i_1_n_0 ));
FDSE \PREAMBLE_COUNT_reg[4]
(.C(ETH_CLK_OBUF),
.CE(\PREAMBLE_COUNT[4]_i_2_n_0 ),
.D(\PREAMBLE_COUNT[4]_i_3_n_0 ),
.Q(\PREAMBLE_COUNT_reg_n_0_[4] ),
.S(\PREAMBLE_COUNT[4]_i_1_n_0 ));
LUT4 #(
.INIT(16'hAE55))
S_TX_ACK_i_1
(.I0(\TX_PACKET_STATE_reg_n_0_[1] ),
.I1(\TX_PACKET_STATE_reg_n_0_[0] ),
.I2(\TX_PACKET_STATE_reg[1]_i_2_n_2 ),
.I3(S_TX_ACK_reg_n_0),
.O(S_TX_ACK_i_1_n_0));
FDRE S_TX_ACK_reg
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(S_TX_ACK_i_1_n_0),
.Q(S_TX_ACK_reg_n_0),
.R(INTERNAL_RST_reg));
(* SOFT_HLUTNM = "soft_lutpair152" *)
LUT3 #(
.INIT(8'hB8))
\TXD[0]_i_1
(.I0(\TXD[0]_i_2_n_0 ),
.I1(\TXD[1]_i_3_n_0 ),
.I2(TXD_OBUF[0]),
.O(\TXD[0]_i_1_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\TXD[0]_i_10
(.I0(p_18_in[0]),
.I1(TX_MEMORY_reg_n_67),
.I2(\TX_PHY_STATE_reg_n_0_[1] ),
.I3(p_20_in[0]),
.I4(\TX_PHY_STATE_reg_n_0_[0] ),
.I5(p_21_in[0]),
.O(\TXD[0]_i_10_n_0 ));
LUT6 #(
.INIT(64'h5F503F3F5F503030))
\TXD[0]_i_11
(.I0(slv1_out[5]),
.I1(slv1_out[7]),
.I2(\TX_PHY_STATE_reg_n_0_[1] ),
.I3(p_16_in[0]),
.I4(\TX_PHY_STATE_reg_n_0_[0] ),
.I5(p_17_in[0]),
.O(\TXD[0]_i_11_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\TXD[0]_i_2
(.I0(\TXD[0]_i_3_n_0 ),
.I1(\TXD_reg[0]_i_4_n_0 ),
.I2(\TX_PHY_STATE_reg_n_0_[4] ),
.I3(\TXD_reg[0]_i_5_n_0 ),
.I4(\TX_PHY_STATE_reg_n_0_[3] ),
.I5(\TXD[0]_i_6_n_0 ),
.O(\TXD[0]_i_2_n_0 ));
LUT5 #(
.INIT(32'h47FF4700))
\TXD[0]_i_3
(.I0(p_1_in126_in),
.I1(\TX_PHY_STATE_reg_n_0_[0] ),
.I2(p_1_in130_in),
.I3(\TX_PHY_STATE_reg_n_0_[2] ),
.I4(\TXD[0]_i_7_n_0 ),
.O(\TXD[0]_i_3_n_0 ));
LUT5 #(
.INIT(32'hDFD5FFFF))
\TXD[0]_i_6
(.I0(\TX_PHY_STATE_reg_n_0_[1] ),
.I1(p_22_in[0]),
.I2(\TX_PHY_STATE_reg_n_0_[0] ),
.I3(TX_MEMORY_reg_n_59),
.I4(\TX_PHY_STATE_reg_n_0_[2] ),
.O(\TXD[0]_i_6_n_0 ));
LUT6 #(
.INIT(64'h505F3030505F3F3F))
\TXD[0]_i_7
(.I0(p_1_in133_in),
.I1(p_1_in136_in),
.I2(\TX_PHY_STATE_reg_n_0_[1] ),
.I3(\TX_CRC_reg_n_0_[9] ),
.I4(\TX_PHY_STATE_reg_n_0_[0] ),
.I5(\TX_CRC_reg_n_0_[11] ),
.O(\TXD[0]_i_7_n_0 ));
LUT6 #(
.INIT(64'h505F3030505F3F3F))
\TXD[0]_i_8
(.I0(\TX_CRC_reg_n_0_[21] ),
.I1(\TX_CRC_reg_n_0_[23] ),
.I2(\TX_PHY_STATE_reg_n_0_[1] ),
.I3(slv1_out[1]),
.I4(\TX_PHY_STATE_reg_n_0_[0] ),
.I5(slv1_out[3]),
.O(\TXD[0]_i_8_n_0 ));
LUT6 #(
.INIT(64'h505F3030505F3F3F))
\TXD[0]_i_9
(.I0(\TX_CRC_reg_n_0_[13] ),
.I1(\TX_CRC_reg_n_0_[15] ),
.I2(\TX_PHY_STATE_reg_n_0_[1] ),
.I3(\TX_CRC_reg_n_0_[17] ),
.I4(\TX_PHY_STATE_reg_n_0_[0] ),
.I5(\TX_CRC_reg_n_0_[19] ),
.O(\TXD[0]_i_9_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair152" *)
LUT3 #(
.INIT(8'hB8))
\TXD[1]_i_1
(.I0(\TXD[1]_i_2_n_0 ),
.I1(\TXD[1]_i_3_n_0 ),
.I2(TXD_OBUF[1]),
.O(\TXD[1]_i_1_n_0 ));
LUT6 #(
.INIT(64'h505F3030505F3F3F))
\TXD[1]_i_10
(.I0(\TX_CRC_reg_n_0_[12] ),
.I1(\TX_CRC_reg_n_0_[14] ),
.I2(\TX_PHY_STATE_reg_n_0_[1] ),
.I3(\TX_CRC_reg_n_0_[16] ),
.I4(\TX_PHY_STATE_reg_n_0_[0] ),
.I5(\TX_CRC_reg_n_0_[18] ),
.O(\TXD[1]_i_10_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\TXD[1]_i_11
(.I0(p_18_in[1]),
.I1(p_0_in66_in),
.I2(\TX_PHY_STATE_reg_n_0_[1] ),
.I3(p_20_in[1]),
.I4(\TX_PHY_STATE_reg_n_0_[0] ),
.I5(p_21_in[1]),
.O(\TXD[1]_i_11_n_0 ));
LUT6 #(
.INIT(64'h5F503F3F5F503030))
\TXD[1]_i_12
(.I0(slv1_out[4]),
.I1(slv1_out[6]),
.I2(\TX_PHY_STATE_reg_n_0_[1] ),
.I3(p_16_in[1]),
.I4(\TX_PHY_STATE_reg_n_0_[0] ),
.I5(p_17_in[1]),
.O(\TXD[1]_i_12_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\TXD[1]_i_2
(.I0(\TXD[1]_i_4_n_0 ),
.I1(\TXD_reg[1]_i_5_n_0 ),
.I2(\TX_PHY_STATE_reg_n_0_[4] ),
.I3(\TXD_reg[1]_i_6_n_0 ),
.I4(\TX_PHY_STATE_reg_n_0_[3] ),
.I5(\TXD[1]_i_7_n_0 ),
.O(\TXD[1]_i_2_n_0 ));
LUT5 #(
.INIT(32'hBFFFFFFE))
\TXD[1]_i_3
(.I0(\TX_PHY_STATE_reg_n_0_[0] ),
.I1(\TX_PHY_STATE_reg_n_0_[3] ),
.I2(\TX_PHY_STATE_reg_n_0_[4] ),
.I3(\TX_PHY_STATE_reg_n_0_[1] ),
.I4(\TX_PHY_STATE_reg_n_0_[2] ),
.O(\TXD[1]_i_3_n_0 ));
LUT5 #(
.INIT(32'h47FF4700))
\TXD[1]_i_4
(.I0(\TX_CRC_reg_n_0_[0] ),
.I1(\TX_PHY_STATE_reg_n_0_[0] ),
.I2(p_1_in128_in),
.I3(\TX_PHY_STATE_reg_n_0_[2] ),
.I4(\TXD[1]_i_8_n_0 ),
.O(\TXD[1]_i_4_n_0 ));
LUT5 #(
.INIT(32'hA8882808))
\TXD[1]_i_7
(.I0(\TX_PHY_STATE_reg_n_0_[2] ),
.I1(\TX_PHY_STATE_reg_n_0_[0] ),
.I2(\TX_PHY_STATE_reg_n_0_[1] ),
.I3(p_0_in167_in),
.I4(p_22_in[1]),
.O(\TXD[1]_i_7_n_0 ));
LUT6 #(
.INIT(64'h505F3030505F3F3F))
\TXD[1]_i_8
(.I0(p_1_in132_in),
.I1(p_1_in135_in),
.I2(\TX_PHY_STATE_reg_n_0_[1] ),
.I3(\TX_CRC_reg_n_0_[8] ),
.I4(\TX_PHY_STATE_reg_n_0_[0] ),
.I5(\TX_CRC_reg_n_0_[10] ),
.O(\TXD[1]_i_8_n_0 ));
LUT6 #(
.INIT(64'h505F3030505F3F3F))
\TXD[1]_i_9
(.I0(\TX_CRC_reg_n_0_[20] ),
.I1(\TX_CRC_reg_n_0_[22] ),
.I2(\TX_PHY_STATE_reg_n_0_[1] ),
.I3(slv1_out[0]),
.I4(\TX_PHY_STATE_reg_n_0_[0] ),
.I5(slv1_out[2]),
.O(\TXD[1]_i_9_n_0 ));
FDRE \TXD_reg[0]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(\TXD[0]_i_1_n_0 ),
.Q(TXD_OBUF[0]),
.R(INTERNAL_RST_reg));
MUXF7 \TXD_reg[0]_i_4
(.I0(\TXD[0]_i_8_n_0 ),
.I1(\TXD[0]_i_9_n_0 ),
.O(\TXD_reg[0]_i_4_n_0 ),
.S(\TX_PHY_STATE_reg_n_0_[2] ));
MUXF7 \TXD_reg[0]_i_5
(.I0(\TXD[0]_i_10_n_0 ),
.I1(\TXD[0]_i_11_n_0 ),
.O(\TXD_reg[0]_i_5_n_0 ),
.S(\TX_PHY_STATE_reg_n_0_[2] ));
FDRE \TXD_reg[1]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(\TXD[1]_i_1_n_0 ),
.Q(TXD_OBUF[1]),
.R(INTERNAL_RST_reg));
MUXF7 \TXD_reg[1]_i_5
(.I0(\TXD[1]_i_9_n_0 ),
.I1(\TXD[1]_i_10_n_0 ),
.O(\TXD_reg[1]_i_5_n_0 ),
.S(\TX_PHY_STATE_reg_n_0_[2] ));
MUXF7 \TXD_reg[1]_i_6
(.I0(\TXD[1]_i_11_n_0 ),
.I1(\TXD[1]_i_12_n_0 ),
.O(\TXD_reg[1]_i_6_n_0 ),
.S(\TX_PHY_STATE_reg_n_0_[2] ));
LUT6 #(
.INIT(64'h7F7FFFFF00000100))
TXEN_i_1
(.I0(\TX_PHY_STATE_reg_n_0_[4] ),
.I1(\TX_PHY_STATE_reg_n_0_[3] ),
.I2(\TX_PHY_STATE_reg_n_0_[2] ),
.I3(\TX_PHY_STATE_reg_n_0_[0] ),
.I4(\TX_PHY_STATE_reg_n_0_[1] ),
.I5(TXEN_OBUF),
.O(TXEN_i_1_n_0));
FDRE TXEN_reg
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(TXEN_i_1_n_0),
.Q(TXEN_OBUF),
.R(INTERNAL_RST_reg));
LUT6 #(
.INIT(64'h8BB8744774478BB8))
\TX_CRC[0]_i_1
(.I0(\TX_CRC[0]_i_2_n_0 ),
.I1(\TX_PHY_STATE_reg_n_0_[2] ),
.I2(p_0_in167_in),
.I3(p_20_in[1]),
.I4(slv1_out[6]),
.I5(slv1_out[0]),
.O(\TX_CRC[0]_i_1_n_0 ));
LUT2 #(
.INIT(4'h6))
\TX_CRC[0]_i_2
(.I0(p_16_in[1]),
.I1(p_0_in66_in),
.O(\TX_CRC[0]_i_2_n_0 ));
LUT5 #(
.INIT(32'h96696996))
\TX_CRC[10]_i_2
(.I0(p_21_in[1]),
.I1(p_20_in[1]),
.I2(\TX_CRC[10]_i_4_n_0 ),
.I3(p_21_in[0]),
.I4(p_22_in[0]),
.O(NEXTCRC32_D80189_out));
LUT5 #(
.INIT(32'h96696996))
\TX_CRC[10]_i_3
(.I0(slv1_out[2]),
.I1(slv1_out[3]),
.I2(p_18_in[0]),
.I3(slv1_out[0]),
.I4(\TX_CRC[10]_i_5_n_0 ),
.O(\TX_CRC[10]_i_3_n_0 ));
LUT5 #(
.INIT(32'h96696996))
\TX_CRC[10]_i_4
(.I0(p_1_in128_in),
.I1(slv1_out[5]),
.I2(slv1_out[0]),
.I3(slv1_out[3]),
.I4(slv1_out[2]),
.O(\TX_CRC[10]_i_4_n_0 ));
LUT5 #(
.INIT(32'h96696996))
\TX_CRC[10]_i_5
(.I0(slv1_out[5]),
.I1(p_1_in128_in),
.I2(p_16_in[1]),
.I3(p_17_in[1]),
.I4(p_17_in[0]),
.O(\TX_CRC[10]_i_5_n_0 ));
LUT6 #(
.INIT(64'hF0660F990F99F066))
\TX_CRC[11]_i_1
(.I0(p_22_in[1]),
.I1(\TX_CRC[11]_i_2_n_0 ),
.I2(\TX_CRC[11]_i_3_n_0 ),
.I3(\TX_PHY_STATE_reg_n_0_[2] ),
.I4(p_1_in130_in),
.I5(slv1_out[4]),
.O(\TX_CRC[11]_i_1_n_0 ));
LUT6 #(
.INIT(64'h6996966996696996))
\TX_CRC[11]_i_2
(.I0(p_20_in[0]),
.I1(p_20_in[1]),
.I2(slv1_out[1]),
.I3(slv1_out[0]),
.I4(slv1_out[3]),
.I5(p_21_in[0]),
.O(\TX_CRC[11]_i_2_n_0 ));
LUT6 #(
.INIT(64'h6996966996696996))
\TX_CRC[11]_i_3
(.I0(p_16_in[1]),
.I1(p_17_in[0]),
.I2(slv1_out[0]),
.I3(p_16_in[0]),
.I4(slv1_out[1]),
.I5(\TX_CRC[11]_i_4_n_0 ),
.O(\TX_CRC[11]_i_3_n_0 ));
LUT2 #(
.INIT(4'h6))
\TX_CRC[11]_i_4
(.I0(slv1_out[3]),
.I1(p_18_in[1]),
.O(\TX_CRC[11]_i_4_n_0 ));
LUT6 #(
.INIT(64'h6996966996696996))
\TX_CRC[12]_i_2
(.I0(slv1_out[0]),
.I1(\TX_CRC[12]_i_4_n_0 ),
.I2(slv1_out[4]),
.I3(slv1_out[1]),
.I4(p_22_in[1]),
.I5(\TX_CRC[12]_i_5_n_0 ),
.O(\TX_CRC[12]_i_2_n_0 ));
LUT5 #(
.INIT(32'h96696996))
\TX_CRC[12]_i_3
(.I0(p_18_in[0]),
.I1(p_16_in[0]),
.I2(p_16_in[1]),
.I3(p_0_in66_in),
.I4(\TX_CRC[12]_i_6_n_0 ),
.O(\TX_CRC[12]_i_3_n_0 ));
LUT2 #(
.INIT(4'h6))
\TX_CRC[12]_i_4
(.I0(slv1_out[6]),
.I1(slv1_out[2]),
.O(\TX_CRC[12]_i_4_n_0 ));
LUT6 #(
.INIT(64'h6996966996696996))
\TX_CRC[12]_i_5
(.I0(\TX_CRC[18]_i_4_n_0 ),
.I1(p_22_in[0]),
.I2(p_20_in[0]),
.I3(slv1_out[5]),
.I4(p_1_in132_in),
.I5(p_20_in[1]),
.O(\TX_CRC[12]_i_5_n_0 ));
LUT6 #(
.INIT(64'h6996966996696996))
\TX_CRC[12]_i_6
(.I0(p_17_in[1]),
.I1(p_1_in132_in),
.I2(slv1_out[5]),
.I3(p_18_in[1]),
.I4(\TX_CRC[12]_i_7_n_0 ),
.I5(\TX_CRC[12]_i_8_n_0 ),
.O(\TX_CRC[12]_i_6_n_0 ));
LUT2 #(
.INIT(4'h6))
\TX_CRC[12]_i_7
(.I0(slv1_out[4]),
.I1(slv1_out[1]),
.O(\TX_CRC[12]_i_7_n_0 ));
LUT3 #(
.INIT(8'h96))
\TX_CRC[12]_i_8
(.I0(slv1_out[0]),
.I1(slv1_out[2]),
.I2(slv1_out[6]),
.O(\TX_CRC[12]_i_8_n_0 ));
LUT6 #(
.INIT(64'h6996966996696996))
\TX_CRC[13]_i_2
(.I0(p_22_in[0]),
.I1(p_21_in[0]),
.I2(TX_MEMORY_reg_n_59),
.I3(\TX_CRC[13]_i_4_n_0 ),
.I4(\TX_CRC[18]_i_4_n_0 ),
.I5(p_20_in[0]),
.O(NEXTCRC32_D80195_out));
LUT6 #(
.INIT(64'h6996966996696996))
\TX_CRC[13]_i_3
(.I0(p_17_in[1]),
.I1(p_17_in[0]),
.I2(TX_MEMORY_reg_n_67),
.I3(\TX_CRC[13]_i_4_n_0 ),
.I4(p_18_in[0]),
.I5(\TX_CRC[17]_i_5_n_0 ),
.O(\TX_CRC[13]_i_3_n_0 ));
LUT5 #(
.INIT(32'h96696996))
\TX_CRC[13]_i_4
(.I0(p_1_in133_in),
.I1(slv1_out[6]),
.I2(slv1_out[1]),
.I3(slv1_out[5]),
.I4(\TX_CRC[3]_i_4_n_0 ),
.O(\TX_CRC[13]_i_4_n_0 ));
LUT6 #(
.INIT(64'h6996966996696996))
\TX_CRC[14]_i_2
(.I0(p_21_in[1]),
.I1(p_0_in167_in),
.I2(p_21_in[0]),
.I3(\TX_CRC[14]_i_4_n_0 ),
.I4(TX_MEMORY_reg_n_59),
.I5(p_22_in[1]),
.O(\TX_CRC[14]_i_2_n_0 ));
LUT6 #(
.INIT(64'h6996966996696996))
\TX_CRC[14]_i_3
(.I0(p_18_in[1]),
.I1(slv1_out[3]),
.I2(p_17_in[1]),
.I3(\TX_CRC[14]_i_5_n_0 ),
.I4(TX_MEMORY_reg_n_67),
.I5(p_0_in66_in),
.O(\TX_CRC[14]_i_3_n_0 ));
LUT6 #(
.INIT(64'h6996966996696996))
\TX_CRC[14]_i_4
(.I0(p_1_in135_in),
.I1(slv1_out[7]),
.I2(slv1_out[4]),
.I3(slv1_out[3]),
.I4(slv1_out[6]),
.I5(slv1_out[2]),
.O(\TX_CRC[14]_i_4_n_0 ));
LUT6 #(
.INIT(64'h6996966996696996))
\TX_CRC[14]_i_5
(.I0(p_17_in[0]),
.I1(slv1_out[2]),
.I2(slv1_out[6]),
.I3(slv1_out[4]),
.I4(slv1_out[7]),
.I5(p_1_in135_in),
.O(\TX_CRC[14]_i_5_n_0 ));
LUT6 #(
.INIT(64'h9F90606F909F6F60))
\TX_CRC[15]_i_1
(.I0(\TX_CRC[15]_i_2_n_0 ),
.I1(\TX_CRC[15]_i_3_n_0 ),
.I2(\TX_PHY_STATE_reg_n_0_[2] ),
.I3(\TX_CRC[15]_i_4_n_0 ),
.I4(slv1_out[3]),
.I5(\TX_CRC[15]_i_5_n_0 ),
.O(\TX_CRC[15]_i_1_n_0 ));
LUT2 #(
.INIT(4'h6))
\TX_CRC[15]_i_2
(.I0(p_18_in[1]),
.I1(slv1_out[4]),
.O(\TX_CRC[15]_i_2_n_0 ));
LUT6 #(
.INIT(64'h6996966996696996))
\TX_CRC[15]_i_3
(.I0(TX_MEMORY_reg_n_67),
.I1(p_17_in[0]),
.I2(slv1_out[5]),
.I3(p_18_in[0]),
.I4(slv1_out[7]),
.I5(p_1_in136_in),
.O(\TX_CRC[15]_i_3_n_0 ));
LUT2 #(
.INIT(4'h6))
\TX_CRC[15]_i_4
(.I0(slv1_out[4]),
.I1(p_22_in[1]),
.O(\TX_CRC[15]_i_4_n_0 ));
LUT6 #(
.INIT(64'h6996966996696996))
\TX_CRC[15]_i_5
(.I0(p_21_in[0]),
.I1(p_22_in[0]),
.I2(slv1_out[5]),
.I3(TX_MEMORY_reg_n_59),
.I4(slv1_out[7]),
.I5(p_1_in136_in),
.O(\TX_CRC[15]_i_5_n_0 ));
LUT6 #(
.INIT(64'h9F90606F909F6F60))
\TX_CRC[16]_i_1
(.I0(p_18_in[1]),
.I1(\TX_CRC[16]_i_2_n_0 ),
.I2(\TX_PHY_STATE_reg_n_0_[2] ),
.I3(slv1_out[4]),
.I4(slv1_out[0]),
.I5(\TX_CRC[16]_i_3_n_0 ),
.O(\TX_CRC[16]_i_1_n_0 ));
LUT5 #(
.INIT(32'h96696996))
\TX_CRC[16]_i_2
(.I0(p_18_in[0]),
.I1(slv1_out[4]),
.I2(slv1_out[5]),
.I3(\TX_CRC_reg_n_0_[8] ),
.I4(p_16_in[1]),
.O(\TX_CRC[16]_i_2_n_0 ));
LUT5 #(
.INIT(32'h96696996))
\TX_CRC[16]_i_3
(.I0(p_20_in[1]),
.I1(p_22_in[1]),
.I2(p_22_in[0]),
.I3(slv1_out[5]),
.I4(\TX_CRC_reg_n_0_[8] ),
.O(\TX_CRC[16]_i_3_n_0 ));
LUT6 #(
.INIT(64'h6996966996696996))
\TX_CRC[17]_i_2
(.I0(slv1_out[5]),
.I1(p_202_in),
.I2(p_20_in[0]),
.I3(slv1_out[1]),
.I4(p_22_in[0]),
.I5(p_0_in167_in),
.O(NEXTCRC32_D80203_out));
LUT6 #(
.INIT(64'h6996966996696996))
\TX_CRC[17]_i_3
(.I0(slv1_out[5]),
.I1(\TX_CRC[17]_i_5_n_0 ),
.I2(\TX_CRC_reg_n_0_[9] ),
.I3(slv1_out[6]),
.I4(slv1_out[1]),
.I5(p_18_in[0]),
.O(\TX_CRC[17]_i_3_n_0 ));
LUT2 #(
.INIT(4'h6))
\TX_CRC[17]_i_4
(.I0(slv1_out[6]),
.I1(\TX_CRC_reg_n_0_[9] ),
.O(p_202_in));
LUT2 #(
.INIT(4'h6))
\TX_CRC[17]_i_5
(.I0(p_0_in66_in),
.I1(p_16_in[0]),
.O(\TX_CRC[17]_i_5_n_0 ));
LUT6 #(
.INIT(64'h6996966996696996))
\TX_CRC[18]_i_2
(.I0(slv1_out[6]),
.I1(TX_MEMORY_reg_n_59),
.I2(\TX_CRC_reg_n_0_[10] ),
.I3(slv1_out[7]),
.I4(slv1_out[2]),
.I5(\TX_CRC[18]_i_4_n_0 ),
.O(\TX_CRC[18]_i_2_n_0 ));
LUT6 #(
.INIT(64'h6996966996696996))
\TX_CRC[18]_i_3
(.I0(slv1_out[6]),
.I1(\TX_CRC[29]_i_5_n_0 ),
.I2(\TX_CRC_reg_n_0_[10] ),
.I3(slv1_out[7]),
.I4(slv1_out[2]),
.I5(p_17_in[1]),
.O(\TX_CRC[18]_i_3_n_0 ));
LUT2 #(
.INIT(4'h6))
\TX_CRC[18]_i_4
(.I0(p_0_in167_in),
.I1(p_21_in[1]),
.O(\TX_CRC[18]_i_4_n_0 ));
LUT6 #(
.INIT(64'h8778B44BB44B8778))
\TX_CRC[19]_i_1
(.I0(\TX_CRC[19]_i_2_n_0 ),
.I1(\TX_PHY_STATE_reg_n_0_[2] ),
.I2(slv1_out[3]),
.I3(p_206_in),
.I4(TX_MEMORY_reg_n_59),
.I5(p_21_in[0]),
.O(\TX_CRC[19]_i_1_n_0 ));
LUT2 #(
.INIT(4'h6))
\TX_CRC[19]_i_2
(.I0(TX_MEMORY_reg_n_67),
.I1(p_17_in[0]),
.O(\TX_CRC[19]_i_2_n_0 ));
LUT2 #(
.INIT(4'h6))
\TX_CRC[19]_i_3
(.I0(slv1_out[7]),
.I1(\TX_CRC_reg_n_0_[11] ),
.O(p_206_in));
LUT6 #(
.INIT(64'h6996966996696996))
\TX_CRC[1]_i_2
(.I0(\TX_CRC[23]_i_3_n_0 ),
.I1(slv1_out[1]),
.I2(slv1_out[7]),
.I3(TX_MEMORY_reg_n_59),
.I4(slv1_out[0]),
.I5(slv1_out[6]),
.O(\TX_CRC[1]_i_2_n_0 ));
LUT5 #(
.INIT(32'h96696996))
\TX_CRC[1]_i_3
(.I0(\TX_CRC[23]_i_2_n_0 ),
.I1(slv1_out[0]),
.I2(TX_MEMORY_reg_n_67),
.I3(slv1_out[7]),
.I4(slv1_out[1]),
.O(NEXTCRC32_D8070_out));
LUT5 #(
.INIT(32'hB84747B8))
\TX_CRC[20]_i_1
(.I0(p_18_in[1]),
.I1(\TX_PHY_STATE_reg_n_0_[2] ),
.I2(p_22_in[1]),
.I3(slv1_out[4]),
.I4(\TX_CRC_reg_n_0_[12] ),
.O(\TX_CRC[20]_i_1_n_0 ));
LUT5 #(
.INIT(32'hB84747B8))
\TX_CRC[21]_i_1
(.I0(p_18_in[0]),
.I1(\TX_PHY_STATE_reg_n_0_[2] ),
.I2(p_22_in[0]),
.I3(\TX_CRC_reg_n_0_[13] ),
.I4(slv1_out[5]),
.O(\TX_CRC[21]_i_1_n_0 ));
LUT5 #(
.INIT(32'hB84747B8))
\TX_CRC[22]_i_1
(.I0(p_16_in[1]),
.I1(\TX_PHY_STATE_reg_n_0_[2] ),
.I2(p_20_in[1]),
.I3(\TX_CRC_reg_n_0_[14] ),
.I4(slv1_out[0]),
.O(\TX_CRC[22]_i_1_n_0 ));
LUT6 #(
.INIT(64'h87B4784BB4874B78))
\TX_CRC[23]_i_1
(.I0(\TX_CRC[23]_i_2_n_0 ),
.I1(\TX_PHY_STATE_reg_n_0_[2] ),
.I2(slv1_out[0]),
.I3(\TX_CRC[23]_i_3_n_0 ),
.I4(p_214_in),
.I5(slv1_out[6]),
.O(\TX_CRC[23]_i_1_n_0 ));
LUT4 #(
.INIT(16'h6996))
\TX_CRC[23]_i_2
(.I0(p_0_in66_in),
.I1(p_16_in[1]),
.I2(p_16_in[0]),
.I3(slv1_out[6]),
.O(\TX_CRC[23]_i_2_n_0 ));
LUT3 #(
.INIT(8'h96))
\TX_CRC[23]_i_3
(.I0(p_20_in[1]),
.I1(p_20_in[0]),
.I2(p_0_in167_in),
.O(\TX_CRC[23]_i_3_n_0 ));
LUT2 #(
.INIT(4'h6))
\TX_CRC[23]_i_4
(.I0(slv1_out[1]),
.I1(\TX_CRC_reg_n_0_[15] ),
.O(p_214_in));
LUT6 #(
.INIT(64'h6996966996696996))
\TX_CRC[24]_i_2
(.I0(\TX_CRC[24]_i_4_n_0 ),
.I1(TX_MEMORY_reg_n_59),
.I2(slv1_out[2]),
.I3(\TX_CRC_reg_n_0_[16] ),
.I4(p_20_in[0]),
.I5(p_21_in[1]),
.O(NEXTCRC32_D80217_out));
LUT6 #(
.INIT(64'h6996966996696996))
\TX_CRC[24]_i_3
(.I0(slv1_out[7]),
.I1(p_16_in[0]),
.I2(TX_MEMORY_reg_n_67),
.I3(p_216_in),
.I4(slv1_out[1]),
.I5(p_17_in[1]),
.O(\TX_CRC[24]_i_3_n_0 ));
LUT2 #(
.INIT(4'h6))
\TX_CRC[24]_i_4
(.I0(slv1_out[7]),
.I1(slv1_out[1]),
.O(\TX_CRC[24]_i_4_n_0 ));
LUT2 #(
.INIT(4'h6))
\TX_CRC[24]_i_5
(.I0(\TX_CRC_reg_n_0_[16] ),
.I1(slv1_out[2]),
.O(p_216_in));
LUT5 #(
.INIT(32'h96696996))
\TX_CRC[25]_i_2
(.I0(slv1_out[3]),
.I1(\TX_CRC_reg_n_0_[17] ),
.I2(slv1_out[2]),
.I3(p_21_in[1]),
.I4(p_21_in[0]),
.O(\TX_CRC[25]_i_2_n_0 ));
LUT5 #(
.INIT(32'h96696996))
\TX_CRC[25]_i_3
(.I0(slv1_out[2]),
.I1(p_17_in[1]),
.I2(slv1_out[3]),
.I3(\TX_CRC_reg_n_0_[17] ),
.I4(p_17_in[0]),
.O(\TX_CRC[25]_i_3_n_0 ));
LUT6 #(
.INIT(64'h6996FFFF69960000))
\TX_CRC[26]_i_1
(.I0(p_16_in[1]),
.I1(\TX_CRC[26]_i_2_n_0 ),
.I2(p_0_in66_in),
.I3(p_17_in[0]),
.I4(\TX_PHY_STATE_reg_n_0_[2] ),
.I5(\TX_CRC[26]_i_3_n_0 ),
.O(\TX_CRC[26]_i_1_n_0 ));
LUT6 #(
.INIT(64'h6996966996696996))
\TX_CRC[26]_i_2
(.I0(p_18_in[1]),
.I1(slv1_out[6]),
.I2(slv1_out[3]),
.I3(slv1_out[0]),
.I4(\TX_CRC_reg_n_0_[18] ),
.I5(slv1_out[4]),
.O(\TX_CRC[26]_i_2_n_0 ));
LUT4 #(
.INIT(16'h6996))
\TX_CRC[26]_i_3
(.I0(p_0_in167_in),
.I1(p_20_in[1]),
.I2(\TX_CRC[26]_i_4_n_0 ),
.I3(p_22_in[1]),
.O(\TX_CRC[26]_i_3_n_0 ));
LUT6 #(
.INIT(64'h6996966996696996))
\TX_CRC[26]_i_4
(.I0(p_21_in[0]),
.I1(slv1_out[6]),
.I2(slv1_out[3]),
.I3(slv1_out[0]),
.I4(\TX_CRC_reg_n_0_[18] ),
.I5(slv1_out[4]),
.O(\TX_CRC[26]_i_4_n_0 ));
LUT6 #(
.INIT(64'h6F90906F609F9F60))
\TX_CRC[27]_i_1
(.I0(p_18_in[1]),
.I1(\TX_CRC[27]_i_2_n_0 ),
.I2(\TX_PHY_STATE_reg_n_0_[2] ),
.I3(slv1_out[4]),
.I4(slv1_out[7]),
.I5(\TX_CRC[27]_i_3_n_0 ),
.O(\TX_CRC[27]_i_1_n_0 ));
LUT6 #(
.INIT(64'h6996966996696996))
\TX_CRC[27]_i_2
(.I0(p_18_in[0]),
.I1(p_16_in[0]),
.I2(slv1_out[1]),
.I3(slv1_out[5]),
.I4(\TX_CRC_reg_n_0_[19] ),
.I5(TX_MEMORY_reg_n_67),
.O(\TX_CRC[27]_i_2_n_0 ));
LUT6 #(
.INIT(64'h6996966996696996))
\TX_CRC[27]_i_3
(.I0(\TX_CRC[27]_i_4_n_0 ),
.I1(p_22_in[1]),
.I2(slv1_out[1]),
.I3(TX_MEMORY_reg_n_59),
.I4(slv1_out[5]),
.I5(\TX_CRC_reg_n_0_[19] ),
.O(\TX_CRC[27]_i_3_n_0 ));
LUT2 #(
.INIT(4'h6))
\TX_CRC[27]_i_4
(.I0(p_22_in[0]),
.I1(p_20_in[0]),
.O(\TX_CRC[27]_i_4_n_0 ));
LUT5 #(
.INIT(32'h906F9F60))
\TX_CRC[28]_i_1
(.I0(slv1_out[2]),
.I1(\TX_CRC[28]_i_2_n_0 ),
.I2(\TX_PHY_STATE_reg_n_0_[2] ),
.I3(slv1_out[5]),
.I4(\TX_CRC[28]_i_3_n_0 ),
.O(\TX_CRC[28]_i_1_n_0 ));
LUT5 #(
.INIT(32'h96696996))
\TX_CRC[28]_i_2
(.I0(slv1_out[6]),
.I1(\TX_CRC_reg_n_0_[20] ),
.I2(p_0_in66_in),
.I3(p_17_in[1]),
.I4(p_18_in[0]),
.O(\TX_CRC[28]_i_2_n_0 ));
LUT6 #(
.INIT(64'h6996966996696996))
\TX_CRC[28]_i_3
(.I0(p_0_in167_in),
.I1(p_22_in[0]),
.I2(slv1_out[2]),
.I3(p_21_in[1]),
.I4(slv1_out[6]),
.I5(\TX_CRC_reg_n_0_[20] ),
.O(\TX_CRC[28]_i_3_n_0 ));
LUT6 #(
.INIT(64'h6996966996696996))
\TX_CRC[29]_i_2
(.I0(\TX_CRC[29]_i_4_n_0 ),
.I1(p_0_in167_in),
.I2(p_21_in[0]),
.I3(\TX_CRC_reg_n_0_[21] ),
.I4(slv1_out[7]),
.I5(TX_MEMORY_reg_n_59),
.O(\TX_CRC[29]_i_2_n_0 ));
LUT6 #(
.INIT(64'h6996966996696996))
\TX_CRC[29]_i_3
(.I0(slv1_out[3]),
.I1(p_17_in[0]),
.I2(\TX_CRC_reg_n_0_[21] ),
.I3(slv1_out[7]),
.I4(slv1_out[6]),
.I5(\TX_CRC[29]_i_5_n_0 ),
.O(\TX_CRC[29]_i_3_n_0 ));
LUT2 #(
.INIT(4'h6))
\TX_CRC[29]_i_4
(.I0(slv1_out[3]),
.I1(slv1_out[6]),
.O(\TX_CRC[29]_i_4_n_0 ));
LUT2 #(
.INIT(4'h6))
\TX_CRC[29]_i_5
(.I0(TX_MEMORY_reg_n_67),
.I1(p_0_in66_in),
.O(\TX_CRC[29]_i_5_n_0 ));
LUT5 #(
.INIT(32'hB4874B78))
\TX_CRC[2]_i_1
(.I0(\TX_CRC[2]_i_2_n_0 ),
.I1(\TX_PHY_STATE_reg_n_0_[2] ),
.I2(slv1_out[0]),
.I3(\TX_CRC[2]_i_3_n_0 ),
.I4(\TX_CRC[2]_i_4_n_0 ),
.O(\TX_CRC[2]_i_1_n_0 ));
LUT5 #(
.INIT(32'h96696996))
\TX_CRC[2]_i_2
(.I0(TX_MEMORY_reg_n_67),
.I1(p_0_in66_in),
.I2(p_16_in[0]),
.I3(p_17_in[1]),
.I4(p_16_in[1]),
.O(\TX_CRC[2]_i_2_n_0 ));
LUT5 #(
.INIT(32'h96696996))
\TX_CRC[2]_i_3
(.I0(p_20_in[0]),
.I1(p_0_in167_in),
.I2(p_21_in[1]),
.I3(p_20_in[1]),
.I4(TX_MEMORY_reg_n_59),
.O(\TX_CRC[2]_i_3_n_0 ));
LUT4 #(
.INIT(16'h6996))
\TX_CRC[2]_i_4
(.I0(slv1_out[6]),
.I1(slv1_out[7]),
.I2(slv1_out[1]),
.I3(slv1_out[2]),
.O(\TX_CRC[2]_i_4_n_0 ));
LUT5 #(
.INIT(32'h96696996))
\TX_CRC[30]_i_2
(.I0(p_22_in[1]),
.I1(slv1_out[4]),
.I2(TX_MEMORY_reg_n_59),
.I3(slv1_out[7]),
.I4(\TX_CRC_reg_n_0_[22] ),
.O(\TX_CRC[30]_i_2_n_0 ));
LUT5 #(
.INIT(32'h96696996))
\TX_CRC[30]_i_3
(.I0(slv1_out[4]),
.I1(p_18_in[1]),
.I2(slv1_out[7]),
.I3(\TX_CRC_reg_n_0_[22] ),
.I4(TX_MEMORY_reg_n_67),
.O(\TX_CRC[30]_i_3_n_0 ));
LUT5 #(
.INIT(32'h00000008))
\TX_CRC[31]_i_1
(.I0(\TX_PHY_STATE_reg_n_0_[2] ),
.I1(\TX_PHY_STATE_reg_n_0_[0] ),
.I2(\TX_PHY_STATE_reg_n_0_[1] ),
.I3(\TX_PHY_STATE_reg_n_0_[4] ),
.I4(\TX_PHY_STATE_reg_n_0_[3] ),
.O(\TX_CRC[31]_i_1_n_0 ));
LUT5 #(
.INIT(32'h10101000))
\TX_CRC[31]_i_2
(.I0(\TX_PHY_STATE_reg_n_0_[4] ),
.I1(\TX_PHY_STATE_reg_n_0_[1] ),
.I2(\TX_PHY_STATE_reg_n_0_[0] ),
.I3(\TX_PHY_STATE_reg_n_0_[2] ),
.I4(\TX_PHY_STATE_reg_n_0_[3] ),
.O(\TX_CRC[31]_i_2_n_0 ));
LUT5 #(
.INIT(32'hB84747B8))
\TX_CRC[31]_i_3
(.I0(p_18_in[0]),
.I1(\TX_PHY_STATE_reg_n_0_[2] ),
.I2(p_22_in[0]),
.I3(\TX_CRC_reg_n_0_[23] ),
.I4(slv1_out[5]),
.O(\TX_CRC[31]_i_3_n_0 ));
LUT6 #(
.INIT(64'h6996966996696996))
\TX_CRC[3]_i_2
(.I0(\TX_CRC[3]_i_4_n_0 ),
.I1(p_21_in[1]),
.I2(p_21_in[0]),
.I3(TX_MEMORY_reg_n_59),
.I4(slv1_out[1]),
.I5(p_20_in[0]),
.O(NEXTCRC32_D80177_out));
LUT6 #(
.INIT(64'h6996966996696996))
\TX_CRC[3]_i_3
(.I0(\TX_CRC[3]_i_4_n_0 ),
.I1(p_16_in[0]),
.I2(TX_MEMORY_reg_n_67),
.I3(p_17_in[0]),
.I4(slv1_out[1]),
.I5(p_17_in[1]),
.O(\TX_CRC[3]_i_3_n_0 ));
LUT3 #(
.INIT(8'h96))
\TX_CRC[3]_i_4
(.I0(slv1_out[7]),
.I1(slv1_out[2]),
.I2(slv1_out[3]),
.O(\TX_CRC[3]_i_4_n_0 ));
LUT5 #(
.INIT(32'h96696996))
\TX_CRC[4]_i_2
(.I0(p_21_in[1]),
.I1(p_0_in167_in),
.I2(\TX_CRC[4]_i_4_n_0 ),
.I3(p_22_in[1]),
.I4(p_21_in[0]),
.O(\TX_CRC[4]_i_2_n_0 ));
LUT5 #(
.INIT(32'h96696996))
\TX_CRC[4]_i_3
(.I0(slv1_out[4]),
.I1(slv1_out[3]),
.I2(slv1_out[0]),
.I3(p_18_in[1]),
.I4(\TX_CRC[4]_i_5_n_0 ),
.O(\TX_CRC[4]_i_3_n_0 ));
LUT6 #(
.INIT(64'h6996966996696996))
\TX_CRC[4]_i_4
(.I0(p_20_in[1]),
.I1(slv1_out[2]),
.I2(slv1_out[6]),
.I3(slv1_out[3]),
.I4(slv1_out[0]),
.I5(slv1_out[4]),
.O(\TX_CRC[4]_i_4_n_0 ));
LUT6 #(
.INIT(64'h6996966996696996))
\TX_CRC[4]_i_5
(.I0(p_17_in[1]),
.I1(slv1_out[6]),
.I2(slv1_out[2]),
.I3(p_17_in[0]),
.I4(p_16_in[1]),
.I5(p_0_in66_in),
.O(\TX_CRC[4]_i_5_n_0 ));
LUT6 #(
.INIT(64'h6996966996696996))
\TX_CRC[5]_i_2
(.I0(\TX_CRC[5]_i_4_n_0 ),
.I1(p_20_in[1]),
.I2(p_0_in167_in),
.I3(TX_MEMORY_reg_n_59),
.I4(\TX_CRC[5]_i_5_n_0 ),
.I5(\TX_CRC[5]_i_6_n_0 ),
.O(NEXTCRC32_D80181_out));
LUT5 #(
.INIT(32'h96696996))
\TX_CRC[5]_i_3
(.I0(TX_MEMORY_reg_n_67),
.I1(p_17_in[0]),
.I2(p_16_in[1]),
.I3(p_0_in66_in),
.I4(\TX_CRC[5]_i_7_n_0 ),
.O(NEXTCRC32_D8074_out));
LUT2 #(
.INIT(4'h6))
\TX_CRC[5]_i_4
(.I0(p_21_in[0]),
.I1(p_22_in[0]),
.O(\TX_CRC[5]_i_4_n_0 ));
LUT6 #(
.INIT(64'h6996966996696996))
\TX_CRC[5]_i_5
(.I0(p_20_in[0]),
.I1(\TX_CRC[6]_i_6_n_0 ),
.I2(slv1_out[0]),
.I3(slv1_out[5]),
.I4(slv1_out[6]),
.I5(slv1_out[3]),
.O(\TX_CRC[5]_i_5_n_0 ));
LUT2 #(
.INIT(4'h6))
\TX_CRC[5]_i_6
(.I0(p_22_in[1]),
.I1(slv1_out[1]),
.O(\TX_CRC[5]_i_6_n_0 ));
LUT6 #(
.INIT(64'h6996966996696996))
\TX_CRC[5]_i_7
(.I0(\TX_CRC[5]_i_8_n_0 ),
.I1(slv1_out[1]),
.I2(slv1_out[4]),
.I3(slv1_out[7]),
.I4(\TX_CRC[5]_i_9_n_0 ),
.I5(p_18_in[1]),
.O(\TX_CRC[5]_i_7_n_0 ));
LUT2 #(
.INIT(4'h6))
\TX_CRC[5]_i_8
(.I0(p_18_in[0]),
.I1(p_16_in[0]),
.O(\TX_CRC[5]_i_8_n_0 ));
LUT4 #(
.INIT(16'h6996))
\TX_CRC[5]_i_9
(.I0(slv1_out[0]),
.I1(slv1_out[5]),
.I2(slv1_out[6]),
.I3(slv1_out[3]),
.O(\TX_CRC[5]_i_9_n_0 ));
LUT6 #(
.INIT(64'h6996966996696996))
\TX_CRC[6]_i_2
(.I0(\TX_CRC[18]_i_4_n_0 ),
.I1(p_22_in[1]),
.I2(slv1_out[1]),
.I3(\TX_CRC[6]_i_4_n_0 ),
.I4(p_22_in[0]),
.I5(p_20_in[0]),
.O(\TX_CRC[6]_i_2_n_0 ));
LUT6 #(
.INIT(64'h6996966996696996))
\TX_CRC[6]_i_3
(.I0(p_18_in[0]),
.I1(p_16_in[0]),
.I2(slv1_out[2]),
.I3(slv1_out[6]),
.I4(p_17_in[1]),
.I5(\TX_CRC[6]_i_5_n_0 ),
.O(\TX_CRC[6]_i_3_n_0 ));
LUT6 #(
.INIT(64'h6996966996696996))
\TX_CRC[6]_i_4
(.I0(TX_MEMORY_reg_n_59),
.I1(slv1_out[2]),
.I2(slv1_out[6]),
.I3(slv1_out[5]),
.I4(slv1_out[7]),
.I5(slv1_out[4]),
.O(\TX_CRC[6]_i_4_n_0 ));
LUT6 #(
.INIT(64'h6996966996696996))
\TX_CRC[6]_i_5
(.I0(p_0_in66_in),
.I1(TX_MEMORY_reg_n_67),
.I2(\TX_CRC[6]_i_6_n_0 ),
.I3(slv1_out[5]),
.I4(slv1_out[1]),
.I5(p_18_in[1]),
.O(\TX_CRC[6]_i_5_n_0 ));
LUT2 #(
.INIT(4'h6))
\TX_CRC[6]_i_6
(.I0(slv1_out[7]),
.I1(slv1_out[4]),
.O(\TX_CRC[6]_i_6_n_0 ));
LUT6 #(
.INIT(64'h690096FF69FF9600))
\TX_CRC[7]_i_1
(.I0(slv1_out[5]),
.I1(p_18_in[0]),
.I2(\TX_CRC[7]_i_2_n_0 ),
.I3(\TX_PHY_STATE_reg_n_0_[2] ),
.I4(\TX_CRC[7]_i_3_n_0 ),
.I5(\TX_CRC[7]_i_4_n_0 ),
.O(\TX_CRC[7]_i_1_n_0 ));
LUT4 #(
.INIT(16'h6996))
\TX_CRC[7]_i_2
(.I0(TX_MEMORY_reg_n_67),
.I1(p_16_in[1]),
.I2(p_17_in[1]),
.I3(p_17_in[0]),
.O(\TX_CRC[7]_i_2_n_0 ));
LUT4 #(
.INIT(16'h6996))
\TX_CRC[7]_i_3
(.I0(slv1_out[3]),
.I1(slv1_out[2]),
.I2(slv1_out[7]),
.I3(slv1_out[0]),
.O(\TX_CRC[7]_i_3_n_0 ));
LUT6 #(
.INIT(64'h6996966996696996))
\TX_CRC[7]_i_4
(.I0(p_20_in[1]),
.I1(p_21_in[1]),
.I2(slv1_out[5]),
.I3(TX_MEMORY_reg_n_59),
.I4(p_21_in[0]),
.I5(p_22_in[0]),
.O(\TX_CRC[7]_i_4_n_0 ));
LUT6 #(
.INIT(64'hF0660F990F99F066))
\TX_CRC[8]_i_1
(.I0(p_22_in[1]),
.I1(\TX_CRC[11]_i_2_n_0 ),
.I2(\TX_CRC[11]_i_3_n_0 ),
.I3(\TX_PHY_STATE_reg_n_0_[2] ),
.I4(\TX_CRC_reg_n_0_[0] ),
.I5(slv1_out[4]),
.O(\TX_CRC[8]_i_1_n_0 ));
LUT6 #(
.INIT(64'h6996FFFF69960000))
\TX_CRC[9]_i_1
(.I0(slv1_out[4]),
.I1(slv1_out[1]),
.I2(p_18_in[1]),
.I3(\TX_CRC[9]_i_2_n_0 ),
.I4(\TX_PHY_STATE_reg_n_0_[2] ),
.I5(\TX_CRC[9]_i_3_n_0 ),
.O(\TX_CRC[9]_i_1_n_0 ));
LUT6 #(
.INIT(64'h6996966996696996))
\TX_CRC[9]_i_2
(.I0(slv1_out[2]),
.I1(p_17_in[1]),
.I2(slv1_out[5]),
.I3(p_1_in126_in),
.I4(p_18_in[0]),
.I5(p_16_in[0]),
.O(\TX_CRC[9]_i_2_n_0 ));
LUT6 #(
.INIT(64'h6996966996696996))
\TX_CRC[9]_i_3
(.I0(\TX_CRC[9]_i_4_n_0 ),
.I1(p_1_in126_in),
.I2(slv1_out[5]),
.I3(p_21_in[1]),
.I4(slv1_out[2]),
.I5(\TX_CRC[27]_i_4_n_0 ),
.O(\TX_CRC[9]_i_3_n_0 ));
LUT3 #(
.INIT(8'h96))
\TX_CRC[9]_i_4
(.I0(slv1_out[4]),
.I1(slv1_out[1]),
.I2(p_22_in[1]),
.O(\TX_CRC[9]_i_4_n_0 ));
FDSE \TX_CRC_reg[0]
(.C(ETH_CLK_OBUF),
.CE(\TX_CRC[31]_i_2_n_0 ),
.D(\TX_CRC[0]_i_1_n_0 ),
.Q(\TX_CRC_reg_n_0_[0] ),
.S(\TX_CRC[31]_i_1_n_0 ));
FDSE \TX_CRC_reg[10]
(.C(ETH_CLK_OBUF),
.CE(\TX_CRC[31]_i_2_n_0 ),
.D(\TX_CRC_reg[10]_i_1_n_0 ),
.Q(\TX_CRC_reg_n_0_[10] ),
.S(\TX_CRC[31]_i_1_n_0 ));
MUXF7 \TX_CRC_reg[10]_i_1
(.I0(NEXTCRC32_D80189_out),
.I1(\TX_CRC[10]_i_3_n_0 ),
.O(\TX_CRC_reg[10]_i_1_n_0 ),
.S(\TX_PHY_STATE_reg_n_0_[2] ));
FDSE \TX_CRC_reg[11]
(.C(ETH_CLK_OBUF),
.CE(\TX_CRC[31]_i_2_n_0 ),
.D(\TX_CRC[11]_i_1_n_0 ),
.Q(\TX_CRC_reg_n_0_[11] ),
.S(\TX_CRC[31]_i_1_n_0 ));
FDSE \TX_CRC_reg[12]
(.C(ETH_CLK_OBUF),
.CE(\TX_CRC[31]_i_2_n_0 ),
.D(\TX_CRC_reg[12]_i_1_n_0 ),
.Q(\TX_CRC_reg_n_0_[12] ),
.S(\TX_CRC[31]_i_1_n_0 ));
MUXF7 \TX_CRC_reg[12]_i_1
(.I0(\TX_CRC[12]_i_2_n_0 ),
.I1(\TX_CRC[12]_i_3_n_0 ),
.O(\TX_CRC_reg[12]_i_1_n_0 ),
.S(\TX_PHY_STATE_reg_n_0_[2] ));
FDSE \TX_CRC_reg[13]
(.C(ETH_CLK_OBUF),
.CE(\TX_CRC[31]_i_2_n_0 ),
.D(\TX_CRC_reg[13]_i_1_n_0 ),
.Q(\TX_CRC_reg_n_0_[13] ),
.S(\TX_CRC[31]_i_1_n_0 ));
MUXF7 \TX_CRC_reg[13]_i_1
(.I0(NEXTCRC32_D80195_out),
.I1(\TX_CRC[13]_i_3_n_0 ),
.O(\TX_CRC_reg[13]_i_1_n_0 ),
.S(\TX_PHY_STATE_reg_n_0_[2] ));
FDSE \TX_CRC_reg[14]
(.C(ETH_CLK_OBUF),
.CE(\TX_CRC[31]_i_2_n_0 ),
.D(\TX_CRC_reg[14]_i_1_n_0 ),
.Q(\TX_CRC_reg_n_0_[14] ),
.S(\TX_CRC[31]_i_1_n_0 ));
MUXF7 \TX_CRC_reg[14]_i_1
(.I0(\TX_CRC[14]_i_2_n_0 ),
.I1(\TX_CRC[14]_i_3_n_0 ),
.O(\TX_CRC_reg[14]_i_1_n_0 ),
.S(\TX_PHY_STATE_reg_n_0_[2] ));
FDSE \TX_CRC_reg[15]
(.C(ETH_CLK_OBUF),
.CE(\TX_CRC[31]_i_2_n_0 ),
.D(\TX_CRC[15]_i_1_n_0 ),
.Q(\TX_CRC_reg_n_0_[15] ),
.S(\TX_CRC[31]_i_1_n_0 ));
FDSE \TX_CRC_reg[16]
(.C(ETH_CLK_OBUF),
.CE(\TX_CRC[31]_i_2_n_0 ),
.D(\TX_CRC[16]_i_1_n_0 ),
.Q(\TX_CRC_reg_n_0_[16] ),
.S(\TX_CRC[31]_i_1_n_0 ));
FDSE \TX_CRC_reg[17]
(.C(ETH_CLK_OBUF),
.CE(\TX_CRC[31]_i_2_n_0 ),
.D(\TX_CRC_reg[17]_i_1_n_0 ),
.Q(\TX_CRC_reg_n_0_[17] ),
.S(\TX_CRC[31]_i_1_n_0 ));
MUXF7 \TX_CRC_reg[17]_i_1
(.I0(NEXTCRC32_D80203_out),
.I1(\TX_CRC[17]_i_3_n_0 ),
.O(\TX_CRC_reg[17]_i_1_n_0 ),
.S(\TX_PHY_STATE_reg_n_0_[2] ));
FDSE \TX_CRC_reg[18]
(.C(ETH_CLK_OBUF),
.CE(\TX_CRC[31]_i_2_n_0 ),
.D(\TX_CRC_reg[18]_i_1_n_0 ),
.Q(\TX_CRC_reg_n_0_[18] ),
.S(\TX_CRC[31]_i_1_n_0 ));
MUXF7 \TX_CRC_reg[18]_i_1
(.I0(\TX_CRC[18]_i_2_n_0 ),
.I1(\TX_CRC[18]_i_3_n_0 ),
.O(\TX_CRC_reg[18]_i_1_n_0 ),
.S(\TX_PHY_STATE_reg_n_0_[2] ));
FDSE \TX_CRC_reg[19]
(.C(ETH_CLK_OBUF),
.CE(\TX_CRC[31]_i_2_n_0 ),
.D(\TX_CRC[19]_i_1_n_0 ),
.Q(\TX_CRC_reg_n_0_[19] ),
.S(\TX_CRC[31]_i_1_n_0 ));
FDSE \TX_CRC_reg[1]
(.C(ETH_CLK_OBUF),
.CE(\TX_CRC[31]_i_2_n_0 ),
.D(\TX_CRC_reg[1]_i_1_n_0 ),
.Q(p_1_in126_in),
.S(\TX_CRC[31]_i_1_n_0 ));
MUXF7 \TX_CRC_reg[1]_i_1
(.I0(\TX_CRC[1]_i_2_n_0 ),
.I1(NEXTCRC32_D8070_out),
.O(\TX_CRC_reg[1]_i_1_n_0 ),
.S(\TX_PHY_STATE_reg_n_0_[2] ));
FDSE \TX_CRC_reg[20]
(.C(ETH_CLK_OBUF),
.CE(\TX_CRC[31]_i_2_n_0 ),
.D(\TX_CRC[20]_i_1_n_0 ),
.Q(\TX_CRC_reg_n_0_[20] ),
.S(\TX_CRC[31]_i_1_n_0 ));
FDSE \TX_CRC_reg[21]
(.C(ETH_CLK_OBUF),
.CE(\TX_CRC[31]_i_2_n_0 ),
.D(\TX_CRC[21]_i_1_n_0 ),
.Q(\TX_CRC_reg_n_0_[21] ),
.S(\TX_CRC[31]_i_1_n_0 ));
FDSE \TX_CRC_reg[22]
(.C(ETH_CLK_OBUF),
.CE(\TX_CRC[31]_i_2_n_0 ),
.D(\TX_CRC[22]_i_1_n_0 ),
.Q(\TX_CRC_reg_n_0_[22] ),
.S(\TX_CRC[31]_i_1_n_0 ));
FDSE \TX_CRC_reg[23]
(.C(ETH_CLK_OBUF),
.CE(\TX_CRC[31]_i_2_n_0 ),
.D(\TX_CRC[23]_i_1_n_0 ),
.Q(\TX_CRC_reg_n_0_[23] ),
.S(\TX_CRC[31]_i_1_n_0 ));
FDSE \TX_CRC_reg[24]
(.C(ETH_CLK_OBUF),
.CE(\TX_CRC[31]_i_2_n_0 ),
.D(\TX_CRC_reg[24]_i_1_n_0 ),
.Q(slv1_out[0]),
.S(\TX_CRC[31]_i_1_n_0 ));
MUXF7 \TX_CRC_reg[24]_i_1
(.I0(NEXTCRC32_D80217_out),
.I1(\TX_CRC[24]_i_3_n_0 ),
.O(\TX_CRC_reg[24]_i_1_n_0 ),
.S(\TX_PHY_STATE_reg_n_0_[2] ));
FDSE \TX_CRC_reg[25]
(.C(ETH_CLK_OBUF),
.CE(\TX_CRC[31]_i_2_n_0 ),
.D(\TX_CRC_reg[25]_i_1_n_0 ),
.Q(slv1_out[1]),
.S(\TX_CRC[31]_i_1_n_0 ));
MUXF7 \TX_CRC_reg[25]_i_1
(.I0(\TX_CRC[25]_i_2_n_0 ),
.I1(\TX_CRC[25]_i_3_n_0 ),
.O(\TX_CRC_reg[25]_i_1_n_0 ),
.S(\TX_PHY_STATE_reg_n_0_[2] ));
FDSE \TX_CRC_reg[26]
(.C(ETH_CLK_OBUF),
.CE(\TX_CRC[31]_i_2_n_0 ),
.D(\TX_CRC[26]_i_1_n_0 ),
.Q(slv1_out[2]),
.S(\TX_CRC[31]_i_1_n_0 ));
FDSE \TX_CRC_reg[27]
(.C(ETH_CLK_OBUF),
.CE(\TX_CRC[31]_i_2_n_0 ),
.D(\TX_CRC[27]_i_1_n_0 ),
.Q(slv1_out[3]),
.S(\TX_CRC[31]_i_1_n_0 ));
FDSE \TX_CRC_reg[28]
(.C(ETH_CLK_OBUF),
.CE(\TX_CRC[31]_i_2_n_0 ),
.D(\TX_CRC[28]_i_1_n_0 ),
.Q(slv1_out[4]),
.S(\TX_CRC[31]_i_1_n_0 ));
FDSE \TX_CRC_reg[29]
(.C(ETH_CLK_OBUF),
.CE(\TX_CRC[31]_i_2_n_0 ),
.D(\TX_CRC_reg[29]_i_1_n_0 ),
.Q(slv1_out[5]),
.S(\TX_CRC[31]_i_1_n_0 ));
MUXF7 \TX_CRC_reg[29]_i_1
(.I0(\TX_CRC[29]_i_2_n_0 ),
.I1(\TX_CRC[29]_i_3_n_0 ),
.O(\TX_CRC_reg[29]_i_1_n_0 ),
.S(\TX_PHY_STATE_reg_n_0_[2] ));
FDSE \TX_CRC_reg[2]
(.C(ETH_CLK_OBUF),
.CE(\TX_CRC[31]_i_2_n_0 ),
.D(\TX_CRC[2]_i_1_n_0 ),
.Q(p_1_in128_in),
.S(\TX_CRC[31]_i_1_n_0 ));
FDSE \TX_CRC_reg[30]
(.C(ETH_CLK_OBUF),
.CE(\TX_CRC[31]_i_2_n_0 ),
.D(\TX_CRC_reg[30]_i_1_n_0 ),
.Q(slv1_out[6]),
.S(\TX_CRC[31]_i_1_n_0 ));
MUXF7 \TX_CRC_reg[30]_i_1
(.I0(\TX_CRC[30]_i_2_n_0 ),
.I1(\TX_CRC[30]_i_3_n_0 ),
.O(\TX_CRC_reg[30]_i_1_n_0 ),
.S(\TX_PHY_STATE_reg_n_0_[2] ));
FDSE \TX_CRC_reg[31]
(.C(ETH_CLK_OBUF),
.CE(\TX_CRC[31]_i_2_n_0 ),
.D(\TX_CRC[31]_i_3_n_0 ),
.Q(slv1_out[7]),
.S(\TX_CRC[31]_i_1_n_0 ));
FDSE \TX_CRC_reg[3]
(.C(ETH_CLK_OBUF),
.CE(\TX_CRC[31]_i_2_n_0 ),
.D(\TX_CRC_reg[3]_i_1_n_0 ),
.Q(p_1_in130_in),
.S(\TX_CRC[31]_i_1_n_0 ));
MUXF7 \TX_CRC_reg[3]_i_1
(.I0(NEXTCRC32_D80177_out),
.I1(\TX_CRC[3]_i_3_n_0 ),
.O(\TX_CRC_reg[3]_i_1_n_0 ),
.S(\TX_PHY_STATE_reg_n_0_[2] ));
FDSE \TX_CRC_reg[4]
(.C(ETH_CLK_OBUF),
.CE(\TX_CRC[31]_i_2_n_0 ),
.D(\TX_CRC_reg[4]_i_1_n_0 ),
.Q(p_1_in132_in),
.S(\TX_CRC[31]_i_1_n_0 ));
MUXF7 \TX_CRC_reg[4]_i_1
(.I0(\TX_CRC[4]_i_2_n_0 ),
.I1(\TX_CRC[4]_i_3_n_0 ),
.O(\TX_CRC_reg[4]_i_1_n_0 ),
.S(\TX_PHY_STATE_reg_n_0_[2] ));
FDSE \TX_CRC_reg[5]
(.C(ETH_CLK_OBUF),
.CE(\TX_CRC[31]_i_2_n_0 ),
.D(\TX_CRC_reg[5]_i_1_n_0 ),
.Q(p_1_in133_in),
.S(\TX_CRC[31]_i_1_n_0 ));
MUXF7 \TX_CRC_reg[5]_i_1
(.I0(NEXTCRC32_D80181_out),
.I1(NEXTCRC32_D8074_out),
.O(\TX_CRC_reg[5]_i_1_n_0 ),
.S(\TX_PHY_STATE_reg_n_0_[2] ));
FDSE \TX_CRC_reg[6]
(.C(ETH_CLK_OBUF),
.CE(\TX_CRC[31]_i_2_n_0 ),
.D(\TX_CRC_reg[6]_i_1_n_0 ),
.Q(p_1_in135_in),
.S(\TX_CRC[31]_i_1_n_0 ));
MUXF7 \TX_CRC_reg[6]_i_1
(.I0(\TX_CRC[6]_i_2_n_0 ),
.I1(\TX_CRC[6]_i_3_n_0 ),
.O(\TX_CRC_reg[6]_i_1_n_0 ),
.S(\TX_PHY_STATE_reg_n_0_[2] ));
FDSE \TX_CRC_reg[7]
(.C(ETH_CLK_OBUF),
.CE(\TX_CRC[31]_i_2_n_0 ),
.D(\TX_CRC[7]_i_1_n_0 ),
.Q(p_1_in136_in),
.S(\TX_CRC[31]_i_1_n_0 ));
FDSE \TX_CRC_reg[8]
(.C(ETH_CLK_OBUF),
.CE(\TX_CRC[31]_i_2_n_0 ),
.D(\TX_CRC[8]_i_1_n_0 ),
.Q(\TX_CRC_reg_n_0_[8] ),
.S(\TX_CRC[31]_i_1_n_0 ));
FDSE \TX_CRC_reg[9]
(.C(ETH_CLK_OBUF),
.CE(\TX_CRC[31]_i_2_n_0 ),
.D(\TX_CRC[9]_i_1_n_0 ),
.Q(\TX_CRC_reg_n_0_[9] ),
.S(\TX_CRC[31]_i_1_n_0 ));
LUT3 #(
.INIT(8'h02))
\TX_IN_COUNT[10]_i_1
(.I0(S_TX_ACK_reg_n_0),
.I1(\TX_PACKET_STATE_reg_n_0_[1] ),
.I2(\TX_PACKET_STATE_reg_n_0_[0] ),
.O(\TX_IN_COUNT[10]_i_1_n_0 ));
LUT4 #(
.INIT(16'h0444))
\TX_IN_COUNT[10]_i_2
(.I0(\TX_PACKET_STATE_reg_n_0_[1] ),
.I1(S_TX_ACK_reg_n_0),
.I2(\TX_PACKET_STATE_reg_n_0_[0] ),
.I3(\TX_PACKET_STATE_reg[1]_i_2_n_2 ),
.O(\TX_IN_COUNT[10]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair86" *)
LUT5 #(
.INIT(32'hAAAA6AAA))
\TX_IN_COUNT[10]_i_3
(.I0(TX_IN_COUNT[10]),
.I1(TX_IN_COUNT[9]),
.I2(TX_IN_COUNT[8]),
.I3(TX_IN_COUNT[7]),
.I4(\TX_IN_COUNT[10]_i_4_n_0 ),
.O(\TX_IN_COUNT[10]_i_3_n_0 ));
LUT6 #(
.INIT(64'h7FFFFFFFFFFFFFFF))
\TX_IN_COUNT[10]_i_4
(.I0(TX_IN_COUNT[5]),
.I1(TX_IN_COUNT[3]),
.I2(TX_IN_COUNT[1]),
.I3(TX_IN_COUNT[2]),
.I4(TX_IN_COUNT[4]),
.I5(TX_IN_COUNT[6]),
.O(\TX_IN_COUNT[10]_i_4_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair85" *)
LUT5 #(
.INIT(32'hFFBF0444))
\TX_IN_COUNT[1]_i_1
(.I0(\TX_PACKET_STATE_reg_n_0_[1] ),
.I1(S_TX_ACK_reg_n_0),
.I2(\TX_PACKET_STATE_reg_n_0_[0] ),
.I3(\TX_PACKET_STATE_reg[1]_i_2_n_2 ),
.I4(TX_IN_COUNT[1]),
.O(\TX_IN_COUNT[1]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFFCFDFCF00002000))
\TX_IN_COUNT[2]_i_1
(.I0(TX_IN_COUNT[1]),
.I1(\TX_PACKET_STATE_reg_n_0_[1] ),
.I2(S_TX_ACK_reg_n_0),
.I3(\TX_PACKET_STATE_reg_n_0_[0] ),
.I4(\TX_PACKET_STATE_reg[1]_i_2_n_2 ),
.I5(TX_IN_COUNT[2]),
.O(\TX_IN_COUNT[2]_i_1_n_0 ));
LUT3 #(
.INIT(8'h6A))
\TX_IN_COUNT[3]_i_1
(.I0(TX_IN_COUNT[3]),
.I1(TX_IN_COUNT[2]),
.I2(TX_IN_COUNT[1]),
.O(\TX_IN_COUNT[3]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair96" *)
LUT4 #(
.INIT(16'h6AAA))
\TX_IN_COUNT[4]_i_1
(.I0(TX_IN_COUNT[4]),
.I1(TX_IN_COUNT[3]),
.I2(TX_IN_COUNT[1]),
.I3(TX_IN_COUNT[2]),
.O(\TX_IN_COUNT[4]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair96" *)
LUT5 #(
.INIT(32'h6AAAAAAA))
\TX_IN_COUNT[5]_i_1
(.I0(TX_IN_COUNT[5]),
.I1(TX_IN_COUNT[4]),
.I2(TX_IN_COUNT[2]),
.I3(TX_IN_COUNT[1]),
.I4(TX_IN_COUNT[3]),
.O(\TX_IN_COUNT[5]_i_1_n_0 ));
LUT6 #(
.INIT(64'h6AAAAAAAAAAAAAAA))
\TX_IN_COUNT[6]_i_1
(.I0(TX_IN_COUNT[6]),
.I1(TX_IN_COUNT[5]),
.I2(TX_IN_COUNT[3]),
.I3(TX_IN_COUNT[1]),
.I4(TX_IN_COUNT[2]),
.I5(TX_IN_COUNT[4]),
.O(\TX_IN_COUNT[6]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair154" *)
LUT2 #(
.INIT(4'h9))
\TX_IN_COUNT[7]_i_1
(.I0(TX_IN_COUNT[7]),
.I1(\TX_IN_COUNT[10]_i_4_n_0 ),
.O(\TX_IN_COUNT[7]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair154" *)
LUT3 #(
.INIT(8'hA6))
\TX_IN_COUNT[8]_i_1
(.I0(TX_IN_COUNT[8]),
.I1(TX_IN_COUNT[7]),
.I2(\TX_IN_COUNT[10]_i_4_n_0 ),
.O(\TX_IN_COUNT[8]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair86" *)
LUT4 #(
.INIT(16'h9AAA))
\TX_IN_COUNT[9]_i_1
(.I0(TX_IN_COUNT[9]),
.I1(\TX_IN_COUNT[10]_i_4_n_0 ),
.I2(TX_IN_COUNT[7]),
.I3(TX_IN_COUNT[8]),
.O(\TX_IN_COUNT[9]_i_1_n_0 ));
FDRE \TX_IN_COUNT_reg[10]
(.C(ETH_CLK_OBUF),
.CE(\TX_IN_COUNT[10]_i_2_n_0 ),
.D(\TX_IN_COUNT[10]_i_3_n_0 ),
.Q(TX_IN_COUNT[10]),
.R(\TX_IN_COUNT[10]_i_1_n_0 ));
FDRE \TX_IN_COUNT_reg[1]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(\TX_IN_COUNT[1]_i_1_n_0 ),
.Q(TX_IN_COUNT[1]),
.R(1'b0));
FDRE \TX_IN_COUNT_reg[2]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(\TX_IN_COUNT[2]_i_1_n_0 ),
.Q(TX_IN_COUNT[2]),
.R(1'b0));
FDRE \TX_IN_COUNT_reg[3]
(.C(ETH_CLK_OBUF),
.CE(\TX_IN_COUNT[10]_i_2_n_0 ),
.D(\TX_IN_COUNT[3]_i_1_n_0 ),
.Q(TX_IN_COUNT[3]),
.R(\TX_IN_COUNT[10]_i_1_n_0 ));
FDRE \TX_IN_COUNT_reg[4]
(.C(ETH_CLK_OBUF),
.CE(\TX_IN_COUNT[10]_i_2_n_0 ),
.D(\TX_IN_COUNT[4]_i_1_n_0 ),
.Q(TX_IN_COUNT[4]),
.R(\TX_IN_COUNT[10]_i_1_n_0 ));
FDRE \TX_IN_COUNT_reg[5]
(.C(ETH_CLK_OBUF),
.CE(\TX_IN_COUNT[10]_i_2_n_0 ),
.D(\TX_IN_COUNT[5]_i_1_n_0 ),
.Q(TX_IN_COUNT[5]),
.R(\TX_IN_COUNT[10]_i_1_n_0 ));
FDRE \TX_IN_COUNT_reg[6]
(.C(ETH_CLK_OBUF),
.CE(\TX_IN_COUNT[10]_i_2_n_0 ),
.D(\TX_IN_COUNT[6]_i_1_n_0 ),
.Q(TX_IN_COUNT[6]),
.R(\TX_IN_COUNT[10]_i_1_n_0 ));
FDRE \TX_IN_COUNT_reg[7]
(.C(ETH_CLK_OBUF),
.CE(\TX_IN_COUNT[10]_i_2_n_0 ),
.D(\TX_IN_COUNT[7]_i_1_n_0 ),
.Q(TX_IN_COUNT[7]),
.R(\TX_IN_COUNT[10]_i_1_n_0 ));
FDRE \TX_IN_COUNT_reg[8]
(.C(ETH_CLK_OBUF),
.CE(\TX_IN_COUNT[10]_i_2_n_0 ),
.D(\TX_IN_COUNT[8]_i_1_n_0 ),
.Q(TX_IN_COUNT[8]),
.R(\TX_IN_COUNT[10]_i_1_n_0 ));
FDRE \TX_IN_COUNT_reg[9]
(.C(ETH_CLK_OBUF),
.CE(\TX_IN_COUNT[10]_i_2_n_0 ),
.D(\TX_IN_COUNT[9]_i_1_n_0 ),
.Q(TX_IN_COUNT[9]),
.R(\TX_IN_COUNT[10]_i_1_n_0 ));
(* IS_CLOCK_GATED *)
(* METHODOLOGY_DRC_VIOS = "{SYNTH-6 {cell *THIS*}}" *)
(* POWER_OPTED_CE = "ENBWREN=NEW" *)
(* RTL_RAM_BITS = "16400" *)
(* RTL_RAM_NAME = "TX_MEMORY" *)
(* bram_addr_begin = "0" *)
(* bram_addr_end = "2047" *)
(* bram_slice_begin = "0" *)
(* bram_slice_end = "17" *)
RAMB36E1 #(
.DOA_REG(0),
.DOB_REG(0),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
.READ_WIDTH_A(18),
.READ_WIDTH_B(18),
.RSTREG_PRIORITY_A("RSTREG"),
.RSTREG_PRIORITY_B("RSTREG"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("NO_CHANGE"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(18),
.WRITE_WIDTH_B(18))
TX_MEMORY_reg
(.ADDRARDADDR({1'b1,TX_WRITE_ADDRESS_DEL,1'b1,1'b1,1'b1,1'b1}),
.ADDRBWRADDR({1'b1,TX_READ_ADDRESS,1'b1,1'b1,1'b1,1'b1}),
.CASCADEINA(1'b1),
.CASCADEINB(1'b1),
.CASCADEOUTA(NLW_TX_MEMORY_reg_CASCADEOUTA_UNCONNECTED),
.CASCADEOUTB(NLW_TX_MEMORY_reg_CASCADEOUTB_UNCONNECTED),
.CLKARDCLK(ETH_CLK_OBUF),
.CLKBWRCLK(ETH_CLK_OBUF),
.DBITERR(NLW_TX_MEMORY_reg_DBITERR_UNCONNECTED),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
.DIPADIP({1'b0,1'b0,1'b0,1'b0}),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO(NLW_TX_MEMORY_reg_DOADO_UNCONNECTED[31:0]),
.DOBDO({NLW_TX_MEMORY_reg_DOBDO_UNCONNECTED[31:16],p_20_in,p_21_in,p_22_in,p_0_in167_in,TX_MEMORY_reg_n_59,p_16_in,p_17_in,p_18_in,p_0_in66_in,TX_MEMORY_reg_n_67}),
.DOPADOP(NLW_TX_MEMORY_reg_DOPADOP_UNCONNECTED[3:0]),
.DOPBDOP(NLW_TX_MEMORY_reg_DOPBDOP_UNCONNECTED[3:0]),
.ECCPARITY(NLW_TX_MEMORY_reg_ECCPARITY_UNCONNECTED[7:0]),
.ENARDEN(TX_WRITE),
.ENBWREN(TX_MEMORY_reg_ENBWREN_cooolgate_en_sig_9),
.INJECTDBITERR(NLW_TX_MEMORY_reg_INJECTDBITERR_UNCONNECTED),
.INJECTSBITERR(NLW_TX_MEMORY_reg_INJECTSBITERR_UNCONNECTED),
.RDADDRECC(NLW_TX_MEMORY_reg_RDADDRECC_UNCONNECTED[8:0]),
.REGCEAREGCE(NLW_TX_MEMORY_reg_REGCEAREGCE_UNCONNECTED),
.REGCEB(NLW_TX_MEMORY_reg_REGCEB_UNCONNECTED),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(NLW_TX_MEMORY_reg_SBITERR_UNCONNECTED),
.WEA({1'b0,1'b0,1'b1,1'b1}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
LUT4 #(
.INIT(16'hff35))
TX_MEMORY_reg_ENBWREN_cooolgate_en_gate_17
(.I0(\TX_PHY_STATE_reg_n_0_[4] ),
.I1(\TX_PHY_STATE[4]_i_2_n_0 ),
.I2(\TX_PHY_STATE[4]_i_1_n_0 ),
.I3(INTERNAL_RST_reg),
.O(TX_MEMORY_reg_ENBWREN_cooolgate_en_sig_9));
(* SOFT_HLUTNM = "soft_lutpair147" *)
LUT2 #(
.INIT(4'h7))
\TX_OUT_COUNT[0]_i_1
(.I0(\TX_OUT_COUNT_reg_n_0_[0] ),
.I1(\TX_PHY_STATE_reg_n_0_[3] ),
.O(TX_OUT_COUNT0_in));
LUT6 #(
.INIT(64'h00000000AA100010))
\TX_OUT_COUNT[10]_i_1
(.I0(\TX_PHY_STATE_reg_n_0_[3] ),
.I1(\TX_PHY_STATE_reg_n_0_[2] ),
.I2(GO_SYNC),
.I3(\TX_PHY_STATE_reg_n_0_[0] ),
.I4(\TX_OUT_COUNT[10]_i_3_n_0 ),
.I5(\TX_OUT_COUNT[10]_i_4_n_0 ),
.O(\TX_OUT_COUNT[10]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair144" *)
LUT4 #(
.INIT(16'hE133))
\TX_OUT_COUNT[10]_i_2
(.I0(\TX_OUT_COUNT_reg_n_0_[9] ),
.I1(\TX_OUT_COUNT[10]_i_5_n_0 ),
.I2(\TX_OUT_COUNT_reg_n_0_[10] ),
.I3(\TX_PHY_STATE_reg_n_0_[3] ),
.O(\TX_OUT_COUNT[10]_i_2_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFFFFFFFF7F))
\TX_OUT_COUNT[10]_i_3
(.I0(\TX_OUT_COUNT[10]_i_6_n_0 ),
.I1(\TX_OUT_COUNT[10]_i_7_n_0 ),
.I2(\TX_OUT_COUNT[10]_i_8_n_0 ),
.I3(\TX_OUT_COUNT_reg_n_0_[0] ),
.I4(\TX_OUT_COUNT_reg_n_0_[1] ),
.I5(\TX_OUT_COUNT_reg_n_0_[2] ),
.O(\TX_OUT_COUNT[10]_i_3_n_0 ));
LUT2 #(
.INIT(4'hE))
\TX_OUT_COUNT[10]_i_4
(.I0(\TX_PHY_STATE_reg_n_0_[1] ),
.I1(\TX_PHY_STATE_reg_n_0_[4] ),
.O(\TX_OUT_COUNT[10]_i_4_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFEF0F0F0F0))
\TX_OUT_COUNT[10]_i_5
(.I0(\TX_OUT_COUNT_reg_n_0_[7] ),
.I1(\TX_OUT_COUNT_reg_n_0_[5] ),
.I2(\TX_OUT_COUNT[8]_i_2_n_0 ),
.I3(\TX_OUT_COUNT_reg_n_0_[6] ),
.I4(\TX_OUT_COUNT_reg_n_0_[8] ),
.I5(\TX_PHY_STATE_reg_n_0_[3] ),
.O(\TX_OUT_COUNT[10]_i_5_n_0 ));
LUT3 #(
.INIT(8'h01))
\TX_OUT_COUNT[10]_i_6
(.I0(\TX_OUT_COUNT_reg_n_0_[3] ),
.I1(\TX_OUT_COUNT_reg_n_0_[4] ),
.I2(\TX_OUT_COUNT_reg_n_0_[5] ),
.O(\TX_OUT_COUNT[10]_i_6_n_0 ));
LUT2 #(
.INIT(4'h1))
\TX_OUT_COUNT[10]_i_7
(.I0(\TX_OUT_COUNT_reg_n_0_[10] ),
.I1(\TX_OUT_COUNT_reg_n_0_[9] ),
.O(\TX_OUT_COUNT[10]_i_7_n_0 ));
LUT3 #(
.INIT(8'h01))
\TX_OUT_COUNT[10]_i_8
(.I0(\TX_OUT_COUNT_reg_n_0_[6] ),
.I1(\TX_OUT_COUNT_reg_n_0_[8] ),
.I2(\TX_OUT_COUNT_reg_n_0_[7] ),
.O(\TX_OUT_COUNT[10]_i_8_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair147" *)
LUT3 #(
.INIT(8'h9F))
\TX_OUT_COUNT[1]_i_1
(.I0(\TX_OUT_COUNT_reg_n_0_[0] ),
.I1(\TX_OUT_COUNT_reg_n_0_[1] ),
.I2(\TX_PHY_STATE_reg_n_0_[3] ),
.O(\TX_OUT_COUNT[1]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair91" *)
LUT4 #(
.INIT(16'hE1FF))
\TX_OUT_COUNT[2]_i_1
(.I0(\TX_OUT_COUNT_reg_n_0_[1] ),
.I1(\TX_OUT_COUNT_reg_n_0_[0] ),
.I2(\TX_OUT_COUNT_reg_n_0_[2] ),
.I3(\TX_PHY_STATE_reg_n_0_[3] ),
.O(\TX_OUT_COUNT[2]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair91" *)
LUT5 #(
.INIT(32'hFE01FFFF))
\TX_OUT_COUNT[3]_i_1
(.I0(\TX_OUT_COUNT_reg_n_0_[2] ),
.I1(\TX_OUT_COUNT_reg_n_0_[0] ),
.I2(\TX_OUT_COUNT_reg_n_0_[1] ),
.I3(\TX_OUT_COUNT_reg_n_0_[3] ),
.I4(\TX_PHY_STATE_reg_n_0_[3] ),
.O(\TX_OUT_COUNT[3]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFFFE0001FFFFFFFF))
\TX_OUT_COUNT[4]_i_1
(.I0(\TX_OUT_COUNT_reg_n_0_[3] ),
.I1(\TX_OUT_COUNT_reg_n_0_[1] ),
.I2(\TX_OUT_COUNT_reg_n_0_[0] ),
.I3(\TX_OUT_COUNT_reg_n_0_[2] ),
.I4(\TX_OUT_COUNT_reg_n_0_[4] ),
.I5(\TX_PHY_STATE_reg_n_0_[3] ),
.O(\TX_OUT_COUNT[4]_i_1_n_0 ));
LUT3 #(
.INIT(8'h95))
\TX_OUT_COUNT[5]_i_1
(.I0(\TX_OUT_COUNT[8]_i_2_n_0 ),
.I1(\TX_OUT_COUNT_reg_n_0_[5] ),
.I2(\TX_PHY_STATE_reg_n_0_[3] ),
.O(\TX_OUT_COUNT[5]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair83" *)
LUT4 #(
.INIT(16'hE133))
\TX_OUT_COUNT[6]_i_1
(.I0(\TX_OUT_COUNT_reg_n_0_[5] ),
.I1(\TX_OUT_COUNT[8]_i_2_n_0 ),
.I2(\TX_OUT_COUNT_reg_n_0_[6] ),
.I3(\TX_PHY_STATE_reg_n_0_[3] ),
.O(\TX_OUT_COUNT[6]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair83" *)
LUT5 #(
.INIT(32'hFE013333))
\TX_OUT_COUNT[7]_i_1
(.I0(\TX_OUT_COUNT_reg_n_0_[6] ),
.I1(\TX_OUT_COUNT[8]_i_2_n_0 ),
.I2(\TX_OUT_COUNT_reg_n_0_[5] ),
.I3(\TX_OUT_COUNT_reg_n_0_[7] ),
.I4(\TX_PHY_STATE_reg_n_0_[3] ),
.O(\TX_OUT_COUNT[7]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFFFE00010F0F0F0F))
\TX_OUT_COUNT[8]_i_1
(.I0(\TX_OUT_COUNT_reg_n_0_[7] ),
.I1(\TX_OUT_COUNT_reg_n_0_[5] ),
.I2(\TX_OUT_COUNT[8]_i_2_n_0 ),
.I3(\TX_OUT_COUNT_reg_n_0_[6] ),
.I4(\TX_OUT_COUNT_reg_n_0_[8] ),
.I5(\TX_PHY_STATE_reg_n_0_[3] ),
.O(\TX_OUT_COUNT[8]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFE00000000))
\TX_OUT_COUNT[8]_i_2
(.I0(\TX_OUT_COUNT_reg_n_0_[3] ),
.I1(\TX_OUT_COUNT_reg_n_0_[1] ),
.I2(\TX_OUT_COUNT_reg_n_0_[0] ),
.I3(\TX_OUT_COUNT_reg_n_0_[2] ),
.I4(\TX_OUT_COUNT_reg_n_0_[4] ),
.I5(\TX_PHY_STATE_reg_n_0_[3] ),
.O(\TX_OUT_COUNT[8]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair144" *)
LUT3 #(
.INIT(8'h95))
\TX_OUT_COUNT[9]_i_1
(.I0(\TX_OUT_COUNT[10]_i_5_n_0 ),
.I1(\TX_OUT_COUNT_reg_n_0_[9] ),
.I2(\TX_PHY_STATE_reg_n_0_[3] ),
.O(\TX_OUT_COUNT[9]_i_1_n_0 ));
FDRE \TX_OUT_COUNT_reg[0]
(.C(ETH_CLK_OBUF),
.CE(\TX_OUT_COUNT[10]_i_1_n_0 ),
.D(TX_OUT_COUNT0_in),
.Q(\TX_OUT_COUNT_reg_n_0_[0] ),
.R(1'b0));
FDRE \TX_OUT_COUNT_reg[10]
(.C(ETH_CLK_OBUF),
.CE(\TX_OUT_COUNT[10]_i_1_n_0 ),
.D(\TX_OUT_COUNT[10]_i_2_n_0 ),
.Q(\TX_OUT_COUNT_reg_n_0_[10] ),
.R(1'b0));
FDRE \TX_OUT_COUNT_reg[1]
(.C(ETH_CLK_OBUF),
.CE(\TX_OUT_COUNT[10]_i_1_n_0 ),
.D(\TX_OUT_COUNT[1]_i_1_n_0 ),
.Q(\TX_OUT_COUNT_reg_n_0_[1] ),
.R(1'b0));
FDRE \TX_OUT_COUNT_reg[2]
(.C(ETH_CLK_OBUF),
.CE(\TX_OUT_COUNT[10]_i_1_n_0 ),
.D(\TX_OUT_COUNT[2]_i_1_n_0 ),
.Q(\TX_OUT_COUNT_reg_n_0_[2] ),
.R(1'b0));
FDRE \TX_OUT_COUNT_reg[3]
(.C(ETH_CLK_OBUF),
.CE(\TX_OUT_COUNT[10]_i_1_n_0 ),
.D(\TX_OUT_COUNT[3]_i_1_n_0 ),
.Q(\TX_OUT_COUNT_reg_n_0_[3] ),
.R(1'b0));
FDRE \TX_OUT_COUNT_reg[4]
(.C(ETH_CLK_OBUF),
.CE(\TX_OUT_COUNT[10]_i_1_n_0 ),
.D(\TX_OUT_COUNT[4]_i_1_n_0 ),
.Q(\TX_OUT_COUNT_reg_n_0_[4] ),
.R(1'b0));
FDRE \TX_OUT_COUNT_reg[5]
(.C(ETH_CLK_OBUF),
.CE(\TX_OUT_COUNT[10]_i_1_n_0 ),
.D(\TX_OUT_COUNT[5]_i_1_n_0 ),
.Q(\TX_OUT_COUNT_reg_n_0_[5] ),
.R(1'b0));
FDRE \TX_OUT_COUNT_reg[6]
(.C(ETH_CLK_OBUF),
.CE(\TX_OUT_COUNT[10]_i_1_n_0 ),
.D(\TX_OUT_COUNT[6]_i_1_n_0 ),
.Q(\TX_OUT_COUNT_reg_n_0_[6] ),
.R(1'b0));
FDRE \TX_OUT_COUNT_reg[7]
(.C(ETH_CLK_OBUF),
.CE(\TX_OUT_COUNT[10]_i_1_n_0 ),
.D(\TX_OUT_COUNT[7]_i_1_n_0 ),
.Q(\TX_OUT_COUNT_reg_n_0_[7] ),
.R(1'b0));
FDRE \TX_OUT_COUNT_reg[8]
(.C(ETH_CLK_OBUF),
.CE(\TX_OUT_COUNT[10]_i_1_n_0 ),
.D(\TX_OUT_COUNT[8]_i_1_n_0 ),
.Q(\TX_OUT_COUNT_reg_n_0_[8] ),
.R(1'b0));
FDRE \TX_OUT_COUNT_reg[9]
(.C(ETH_CLK_OBUF),
.CE(\TX_OUT_COUNT[10]_i_1_n_0 ),
.D(\TX_OUT_COUNT[9]_i_1_n_0 ),
.Q(\TX_OUT_COUNT_reg_n_0_[9] ),
.R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair87" *)
LUT5 #(
.INIT(32'hFF007C7C))
\TX_PACKET_STATE[0]_i_1
(.I0(\TX_PACKET_STATE_reg[1]_i_2_n_2 ),
.I1(\TX_PACKET_STATE_reg_n_0_[0] ),
.I2(S_TX_ACK_reg_n_0),
.I3(DONE_SYNC),
.I4(\TX_PACKET_STATE_reg_n_0_[1] ),
.O(\TX_PACKET_STATE[0]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair87" *)
LUT5 #(
.INIT(32'hFF338080))
\TX_PACKET_STATE[1]_i_1
(.I0(\TX_PACKET_STATE_reg[1]_i_2_n_2 ),
.I1(\TX_PACKET_STATE_reg_n_0_[0] ),
.I2(S_TX_ACK_reg_n_0),
.I3(DONE_SYNC),
.I4(\TX_PACKET_STATE_reg_n_0_[1] ),
.O(\TX_PACKET_STATE[1]_i_1_n_0 ));
LUT2 #(
.INIT(4'h1))
\TX_PACKET_STATE[1]_i_10
(.I0(TX_IN_COUNT[6]),
.I1(TX_IN_COUNT[7]),
.O(\TX_PACKET_STATE[1]_i_10_n_0 ));
LUT2 #(
.INIT(4'h1))
\TX_PACKET_STATE[1]_i_11
(.I0(TX_IN_COUNT[4]),
.I1(TX_IN_COUNT[5]),
.O(\TX_PACKET_STATE[1]_i_11_n_0 ));
LUT2 #(
.INIT(4'h1))
\TX_PACKET_STATE[1]_i_12
(.I0(TX_IN_COUNT[2]),
.I1(TX_IN_COUNT[3]),
.O(\TX_PACKET_STATE[1]_i_12_n_0 ));
LUT1 #(
.INIT(2'h1))
\TX_PACKET_STATE[1]_i_13
(.I0(TX_IN_COUNT[1]),
.O(\TX_PACKET_STATE[1]_i_13_n_0 ));
LUT2 #(
.INIT(4'hE))
\TX_PACKET_STATE[1]_i_4
(.I0(TX_IN_COUNT[9]),
.I1(TX_IN_COUNT[8]),
.O(\TX_PACKET_STATE[1]_i_4_n_0 ));
LUT1 #(
.INIT(2'h1))
\TX_PACKET_STATE[1]_i_5
(.I0(TX_IN_COUNT[10]),
.O(\TX_PACKET_STATE[1]_i_5_n_0 ));
LUT2 #(
.INIT(4'h1))
\TX_PACKET_STATE[1]_i_6
(.I0(TX_IN_COUNT[8]),
.I1(TX_IN_COUNT[9]),
.O(\TX_PACKET_STATE[1]_i_6_n_0 ));
LUT2 #(
.INIT(4'hE))
\TX_PACKET_STATE[1]_i_7
(.I0(TX_IN_COUNT[7]),
.I1(TX_IN_COUNT[6]),
.O(\TX_PACKET_STATE[1]_i_7_n_0 ));
LUT2 #(
.INIT(4'hE))
\TX_PACKET_STATE[1]_i_8
(.I0(TX_IN_COUNT[5]),
.I1(TX_IN_COUNT[4]),
.O(\TX_PACKET_STATE[1]_i_8_n_0 ));
LUT2 #(
.INIT(4'hE))
\TX_PACKET_STATE[1]_i_9
(.I0(TX_IN_COUNT[3]),
.I1(TX_IN_COUNT[2]),
.O(\TX_PACKET_STATE[1]_i_9_n_0 ));
FDRE \TX_PACKET_STATE_reg[0]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(\TX_PACKET_STATE[0]_i_1_n_0 ),
.Q(\TX_PACKET_STATE_reg_n_0_[0] ),
.R(INTERNAL_RST_reg));
FDRE \TX_PACKET_STATE_reg[1]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(\TX_PACKET_STATE[1]_i_1_n_0 ),
.Q(\TX_PACKET_STATE_reg_n_0_[1] ),
.R(INTERNAL_RST_reg));
CARRY4 \TX_PACKET_STATE_reg[1]_i_2
(.CI(\TX_PACKET_STATE_reg[1]_i_3_n_0 ),
.CO({\NLW_TX_PACKET_STATE_reg[1]_i_2_CO_UNCONNECTED [3:2],\TX_PACKET_STATE_reg[1]_i_2_n_2 ,\NLW_TX_PACKET_STATE_reg[1]_i_2_CO_UNCONNECTED [0]}),
.CYINIT(1'b0),
.DI({1'b0,1'b0,TX_IN_COUNT[10],\TX_PACKET_STATE[1]_i_4_n_0 }),
.O(\NLW_TX_PACKET_STATE_reg[1]_i_2_O_UNCONNECTED [3:0]),
.S({1'b0,1'b0,\TX_PACKET_STATE[1]_i_5_n_0 ,\TX_PACKET_STATE[1]_i_6_n_0 }));
CARRY4 \TX_PACKET_STATE_reg[1]_i_3
(.CI(1'b0),
.CO({\TX_PACKET_STATE_reg[1]_i_3_n_0 ,\NLW_TX_PACKET_STATE_reg[1]_i_3_CO_UNCONNECTED [2:0]}),
.CYINIT(1'b1),
.DI({\TX_PACKET_STATE[1]_i_7_n_0 ,\TX_PACKET_STATE[1]_i_8_n_0 ,\TX_PACKET_STATE[1]_i_9_n_0 ,TX_IN_COUNT[1]}),
.O(\NLW_TX_PACKET_STATE_reg[1]_i_3_O_UNCONNECTED [3:0]),
.S({\TX_PACKET_STATE[1]_i_10_n_0 ,\TX_PACKET_STATE[1]_i_11_n_0 ,\TX_PACKET_STATE[1]_i_12_n_0 ,\TX_PACKET_STATE[1]_i_13_n_0 }));
LUT6 #(
.INIT(64'h80000000DFFFFFFF))
\TX_PHY_STATE[0]_i_1
(.I0(\TX_PHY_STATE_reg_n_0_[2] ),
.I1(GO_SYNC),
.I2(\TX_PHY_STATE_reg_n_0_[1] ),
.I3(\TX_PHY_STATE_reg_n_0_[3] ),
.I4(\TX_PHY_STATE_reg_n_0_[4] ),
.I5(\TX_PHY_STATE_reg_n_0_[0] ),
.O(\TX_PHY_STATE[0]_i_1_n_0 ));
LUT6 #(
.INIT(64'h8000FFFFDFFF0000))
\TX_PHY_STATE[1]_i_1
(.I0(\TX_PHY_STATE_reg_n_0_[2] ),
.I1(GO_SYNC),
.I2(\TX_PHY_STATE_reg_n_0_[3] ),
.I3(\TX_PHY_STATE_reg_n_0_[4] ),
.I4(\TX_PHY_STATE_reg_n_0_[1] ),
.I5(\TX_PHY_STATE_reg_n_0_[0] ),
.O(\TX_PHY_STATE[1]_i_1_n_0 ));
LUT6 #(
.INIT(64'h8ABABA8ABA8ABA8A))
\TX_PHY_STATE[2]_i_1
(.I0(\TX_PHY_STATE[2]_i_2_n_0 ),
.I1(\TX_PHY_STATE_reg_n_0_[3] ),
.I2(\TX_PHY_STATE_reg_n_0_[4] ),
.I3(\TX_PHY_STATE_reg_n_0_[2] ),
.I4(\TX_PHY_STATE_reg_n_0_[0] ),
.I5(\TX_PHY_STATE_reg_n_0_[1] ),
.O(\TX_PHY_STATE[2]_i_1_n_0 ));
LUT6 #(
.INIT(64'hB8B8BB88BBBB8888))
\TX_PHY_STATE[2]_i_2
(.I0(\TX_PHY_STATE[2]_i_3_n_0 ),
.I1(\TX_PHY_STATE[2]_i_4_n_0 ),
.I2(GO_SYNC),
.I3(\TX_PHY_STATE_reg_n_0_[0] ),
.I4(\TX_PHY_STATE_reg_n_0_[2] ),
.I5(\TX_PHY_STATE_reg_n_0_[1] ),
.O(\TX_PHY_STATE[2]_i_2_n_0 ));
LUT5 #(
.INIT(32'h0FF0F8F0))
\TX_PHY_STATE[2]_i_3
(.I0(\TX_PHY_STATE[3]_i_5_n_0 ),
.I1(\TX_PHY_STATE_reg_n_0_[3] ),
.I2(\TX_PHY_STATE_reg_n_0_[2] ),
.I3(\TX_PHY_STATE_reg_n_0_[0] ),
.I4(\TX_PHY_STATE_reg_n_0_[1] ),
.O(\TX_PHY_STATE[2]_i_3_n_0 ));
LUT3 #(
.INIT(8'h5D))
\TX_PHY_STATE[2]_i_4
(.I0(\TX_PHY_STATE_reg_n_0_[4] ),
.I1(\TX_PHY_STATE_reg_n_0_[2] ),
.I2(\TX_PHY_STATE_reg_n_0_[3] ),
.O(\TX_PHY_STATE[2]_i_4_n_0 ));
LUT6 #(
.INIT(64'hCFAAC0AAC0AAC0AA))
\TX_PHY_STATE[3]_i_1
(.I0(\TX_PHY_STATE[3]_i_2_n_0 ),
.I1(\TX_PHY_STATE[3]_i_3_n_0 ),
.I2(\TX_PHY_STATE_reg_n_0_[3] ),
.I3(\TX_PHY_STATE_reg_n_0_[4] ),
.I4(\TX_PHY_STATE_reg_n_0_[2] ),
.I5(\TX_PHY_STATE[3]_i_4_n_0 ),
.O(\TX_PHY_STATE[3]_i_1_n_0 ));
LUT5 #(
.INIT(32'h3CCC8CCC))
\TX_PHY_STATE[3]_i_2
(.I0(\TX_PHY_STATE[3]_i_5_n_0 ),
.I1(\TX_PHY_STATE_reg_n_0_[3] ),
.I2(\TX_PHY_STATE_reg_n_0_[2] ),
.I3(\TX_PHY_STATE_reg_n_0_[0] ),
.I4(\TX_PHY_STATE_reg_n_0_[1] ),
.O(\TX_PHY_STATE[3]_i_2_n_0 ));
LUT3 #(
.INIT(8'hBF))
\TX_PHY_STATE[3]_i_3
(.I0(GO_SYNC),
.I1(\TX_PHY_STATE_reg_n_0_[2] ),
.I2(\TX_PHY_STATE_reg_n_0_[1] ),
.O(\TX_PHY_STATE[3]_i_3_n_0 ));
LUT2 #(
.INIT(4'h8))
\TX_PHY_STATE[3]_i_4
(.I0(\TX_PHY_STATE_reg_n_0_[1] ),
.I1(\TX_PHY_STATE_reg_n_0_[0] ),
.O(\TX_PHY_STATE[3]_i_4_n_0 ));
LUT6 #(
.INIT(64'h0000000000000080))
\TX_PHY_STATE[3]_i_5
(.I0(\TX_OUT_COUNT[10]_i_6_n_0 ),
.I1(\TX_OUT_COUNT[10]_i_7_n_0 ),
.I2(\TX_OUT_COUNT[10]_i_8_n_0 ),
.I3(\TX_OUT_COUNT_reg_n_0_[0] ),
.I4(\TX_OUT_COUNT_reg_n_0_[1] ),
.I5(\TX_OUT_COUNT_reg_n_0_[2] ),
.O(\TX_PHY_STATE[3]_i_5_n_0 ));
LUT5 #(
.INIT(32'hAFBEAABE))
\TX_PHY_STATE[4]_i_1
(.I0(\TX_PHY_STATE[4]_i_3_n_0 ),
.I1(GO_SYNC),
.I2(\TX_PHY_STATE_reg_n_0_[1] ),
.I3(\TX_PHY_STATE_reg_n_0_[0] ),
.I4(\TX_PHY_STATE[4]_i_4_n_0 ),
.O(\TX_PHY_STATE[4]_i_1_n_0 ));
LUT6 #(
.INIT(64'hF5FF8800FFFF0000))
\TX_PHY_STATE[4]_i_2
(.I0(\TX_PHY_STATE_reg_n_0_[1] ),
.I1(\TX_PHY_STATE_reg_n_0_[0] ),
.I2(GO_SYNC),
.I3(\TX_PHY_STATE_reg_n_0_[2] ),
.I4(\TX_PHY_STATE_reg_n_0_[4] ),
.I5(\TX_PHY_STATE_reg_n_0_[3] ),
.O(\TX_PHY_STATE[4]_i_2_n_0 ));
LUT4 #(
.INIT(16'h7FFE))
\TX_PHY_STATE[4]_i_3
(.I0(\TX_PHY_STATE_reg_n_0_[1] ),
.I1(\TX_PHY_STATE_reg_n_0_[2] ),
.I2(\TX_PHY_STATE_reg_n_0_[3] ),
.I3(\TX_PHY_STATE_reg_n_0_[4] ),
.O(\TX_PHY_STATE[4]_i_3_n_0 ));
LUT5 #(
.INIT(32'h00000001))
\TX_PHY_STATE[4]_i_4
(.I0(\PREAMBLE_COUNT_reg_n_0_[3] ),
.I1(\PREAMBLE_COUNT_reg_n_0_[1] ),
.I2(\PREAMBLE_COUNT_reg_n_0_[0] ),
.I3(\PREAMBLE_COUNT_reg_n_0_[4] ),
.I4(\PREAMBLE_COUNT_reg_n_0_[2] ),
.O(\TX_PHY_STATE[4]_i_4_n_0 ));
FDRE \TX_PHY_STATE_reg[0]
(.C(ETH_CLK_OBUF),
.CE(\TX_PHY_STATE[4]_i_1_n_0 ),
.D(\TX_PHY_STATE[0]_i_1_n_0 ),
.Q(\TX_PHY_STATE_reg_n_0_[0] ),
.R(INTERNAL_RST_reg));
FDRE \TX_PHY_STATE_reg[1]
(.C(ETH_CLK_OBUF),
.CE(\TX_PHY_STATE[4]_i_1_n_0 ),
.D(\TX_PHY_STATE[1]_i_1_n_0 ),
.Q(\TX_PHY_STATE_reg_n_0_[1] ),
.R(INTERNAL_RST_reg));
FDRE \TX_PHY_STATE_reg[2]
(.C(ETH_CLK_OBUF),
.CE(\TX_PHY_STATE[4]_i_1_n_0 ),
.D(\TX_PHY_STATE[2]_i_1_n_0 ),
.Q(\TX_PHY_STATE_reg_n_0_[2] ),
.R(INTERNAL_RST_reg));
FDRE \TX_PHY_STATE_reg[3]
(.C(ETH_CLK_OBUF),
.CE(\TX_PHY_STATE[4]_i_1_n_0 ),
.D(\TX_PHY_STATE[3]_i_1_n_0 ),
.Q(\TX_PHY_STATE_reg_n_0_[3] ),
.R(INTERNAL_RST_reg));
FDRE \TX_PHY_STATE_reg[4]
(.C(ETH_CLK_OBUF),
.CE(\TX_PHY_STATE[4]_i_1_n_0 ),
.D(\TX_PHY_STATE[4]_i_2_n_0 ),
.Q(\TX_PHY_STATE_reg_n_0_[4] ),
.R(INTERNAL_RST_reg));
FDRE \TX_READ_ADDRESS_reg_rep[0]
(.C(ETH_CLK_OBUF),
.CE(\TX_READ_ADDRESS_rep[9]_i_2_n_0 ),
.D(\TX_READ_ADDRESS_rep[0]_i_1_n_0 ),
.Q(TX_READ_ADDRESS[0]),
.R(\TX_READ_ADDRESS_rep[9]_i_1_n_0 ));
FDRE \TX_READ_ADDRESS_reg_rep[10]
(.C(ETH_CLK_OBUF),
.CE(\TX_READ_ADDRESS_rep[9]_i_2_n_0 ),
.D(TX_READ_ADDRESS0[10]),
.Q(TX_READ_ADDRESS[10]),
.R(\TX_READ_ADDRESS_rep[9]_i_1_n_0 ));
FDRE \TX_READ_ADDRESS_reg_rep[1]
(.C(ETH_CLK_OBUF),
.CE(\TX_READ_ADDRESS_rep[9]_i_2_n_0 ),
.D(TX_READ_ADDRESS0[1]),
.Q(TX_READ_ADDRESS[1]),
.R(\TX_READ_ADDRESS_rep[9]_i_1_n_0 ));
FDRE \TX_READ_ADDRESS_reg_rep[2]
(.C(ETH_CLK_OBUF),
.CE(\TX_READ_ADDRESS_rep[9]_i_2_n_0 ),
.D(TX_READ_ADDRESS0[2]),
.Q(TX_READ_ADDRESS[2]),
.R(\TX_READ_ADDRESS_rep[9]_i_1_n_0 ));
FDRE \TX_READ_ADDRESS_reg_rep[3]
(.C(ETH_CLK_OBUF),
.CE(\TX_READ_ADDRESS_rep[9]_i_2_n_0 ),
.D(TX_READ_ADDRESS0[3]),
.Q(TX_READ_ADDRESS[3]),
.R(\TX_READ_ADDRESS_rep[9]_i_1_n_0 ));
FDRE \TX_READ_ADDRESS_reg_rep[4]
(.C(ETH_CLK_OBUF),
.CE(\TX_READ_ADDRESS_rep[9]_i_2_n_0 ),
.D(TX_READ_ADDRESS0[4]),
.Q(TX_READ_ADDRESS[4]),
.R(\TX_READ_ADDRESS_rep[9]_i_1_n_0 ));
FDRE \TX_READ_ADDRESS_reg_rep[5]
(.C(ETH_CLK_OBUF),
.CE(\TX_READ_ADDRESS_rep[9]_i_2_n_0 ),
.D(TX_READ_ADDRESS0[5]),
.Q(TX_READ_ADDRESS[5]),
.R(\TX_READ_ADDRESS_rep[9]_i_1_n_0 ));
FDRE \TX_READ_ADDRESS_reg_rep[6]
(.C(ETH_CLK_OBUF),
.CE(\TX_READ_ADDRESS_rep[9]_i_2_n_0 ),
.D(TX_READ_ADDRESS0[6]),
.Q(TX_READ_ADDRESS[6]),
.R(\TX_READ_ADDRESS_rep[9]_i_1_n_0 ));
FDRE \TX_READ_ADDRESS_reg_rep[7]
(.C(ETH_CLK_OBUF),
.CE(\TX_READ_ADDRESS_rep[9]_i_2_n_0 ),
.D(TX_READ_ADDRESS0[7]),
.Q(TX_READ_ADDRESS[7]),
.R(\TX_READ_ADDRESS_rep[9]_i_1_n_0 ));
FDRE \TX_READ_ADDRESS_reg_rep[8]
(.C(ETH_CLK_OBUF),
.CE(\TX_READ_ADDRESS_rep[9]_i_2_n_0 ),
.D(TX_READ_ADDRESS0[8]),
.Q(TX_READ_ADDRESS[8]),
.R(\TX_READ_ADDRESS_rep[9]_i_1_n_0 ));
FDRE \TX_READ_ADDRESS_reg_rep[9]
(.C(ETH_CLK_OBUF),
.CE(\TX_READ_ADDRESS_rep[9]_i_2_n_0 ),
.D(TX_READ_ADDRESS0[9]),
.Q(TX_READ_ADDRESS[9]),
.R(\TX_READ_ADDRESS_rep[9]_i_1_n_0 ));
LUT1 #(
.INIT(2'h1))
\TX_READ_ADDRESS_rep[0]_i_1
(.I0(TX_READ_ADDRESS[0]),
.O(\TX_READ_ADDRESS_rep[0]_i_1_n_0 ));
LUT6 #(
.INIT(64'h7FFFFFFF80000000))
\TX_READ_ADDRESS_rep[10]_i_1
(.I0(TX_READ_ADDRESS[8]),
.I1(TX_READ_ADDRESS[6]),
.I2(\TX_READ_ADDRESS_rep[9]_i_4_n_0 ),
.I3(TX_READ_ADDRESS[7]),
.I4(TX_READ_ADDRESS[9]),
.I5(TX_READ_ADDRESS[10]),
.O(TX_READ_ADDRESS0[10]));
(* SOFT_HLUTNM = "soft_lutpair145" *)
LUT2 #(
.INIT(4'h6))
\TX_READ_ADDRESS_rep[1]_i_1
(.I0(TX_READ_ADDRESS[0]),
.I1(TX_READ_ADDRESS[1]),
.O(TX_READ_ADDRESS0[1]));
(* SOFT_HLUTNM = "soft_lutpair145" *)
LUT3 #(
.INIT(8'h78))
\TX_READ_ADDRESS_rep[2]_i_1
(.I0(TX_READ_ADDRESS[0]),
.I1(TX_READ_ADDRESS[1]),
.I2(TX_READ_ADDRESS[2]),
.O(TX_READ_ADDRESS0[2]));
(* SOFT_HLUTNM = "soft_lutpair121" *)
LUT4 #(
.INIT(16'h7F80))
\TX_READ_ADDRESS_rep[3]_i_1
(.I0(TX_READ_ADDRESS[1]),
.I1(TX_READ_ADDRESS[0]),
.I2(TX_READ_ADDRESS[2]),
.I3(TX_READ_ADDRESS[3]),
.O(TX_READ_ADDRESS0[3]));
(* SOFT_HLUTNM = "soft_lutpair121" *)
LUT5 #(
.INIT(32'h7FFF8000))
\TX_READ_ADDRESS_rep[4]_i_1
(.I0(TX_READ_ADDRESS[2]),
.I1(TX_READ_ADDRESS[0]),
.I2(TX_READ_ADDRESS[1]),
.I3(TX_READ_ADDRESS[3]),
.I4(TX_READ_ADDRESS[4]),
.O(TX_READ_ADDRESS0[4]));
LUT6 #(
.INIT(64'h7FFFFFFF80000000))
\TX_READ_ADDRESS_rep[5]_i_1
(.I0(TX_READ_ADDRESS[3]),
.I1(TX_READ_ADDRESS[1]),
.I2(TX_READ_ADDRESS[0]),
.I3(TX_READ_ADDRESS[2]),
.I4(TX_READ_ADDRESS[4]),
.I5(TX_READ_ADDRESS[5]),
.O(TX_READ_ADDRESS0[5]));
(* SOFT_HLUTNM = "soft_lutpair148" *)
LUT2 #(
.INIT(4'h6))
\TX_READ_ADDRESS_rep[6]_i_1
(.I0(\TX_READ_ADDRESS_rep[9]_i_4_n_0 ),
.I1(TX_READ_ADDRESS[6]),
.O(TX_READ_ADDRESS0[6]));
(* SOFT_HLUTNM = "soft_lutpair148" *)
LUT3 #(
.INIT(8'h78))
\TX_READ_ADDRESS_rep[7]_i_1
(.I0(\TX_READ_ADDRESS_rep[9]_i_4_n_0 ),
.I1(TX_READ_ADDRESS[6]),
.I2(TX_READ_ADDRESS[7]),
.O(TX_READ_ADDRESS0[7]));
(* SOFT_HLUTNM = "soft_lutpair122" *)
LUT4 #(
.INIT(16'h7F80))
\TX_READ_ADDRESS_rep[8]_i_1
(.I0(TX_READ_ADDRESS[6]),
.I1(\TX_READ_ADDRESS_rep[9]_i_4_n_0 ),
.I2(TX_READ_ADDRESS[7]),
.I3(TX_READ_ADDRESS[8]),
.O(TX_READ_ADDRESS0[8]));
LUT6 #(
.INIT(64'h0000000000000004))
\TX_READ_ADDRESS_rep[9]_i_1
(.I0(\TX_PHY_STATE_reg_n_0_[2] ),
.I1(GO_SYNC),
.I2(\TX_PHY_STATE_reg_n_0_[4] ),
.I3(\TX_PHY_STATE_reg_n_0_[0] ),
.I4(\TX_PHY_STATE_reg_n_0_[1] ),
.I5(\TX_PHY_STATE_reg_n_0_[3] ),
.O(\TX_READ_ADDRESS_rep[9]_i_1_n_0 ));
LUT6 #(
.INIT(64'h0100010000010000))
\TX_READ_ADDRESS_rep[9]_i_2
(.I0(\TX_PHY_STATE_reg_n_0_[1] ),
.I1(\TX_PHY_STATE_reg_n_0_[0] ),
.I2(\TX_PHY_STATE_reg_n_0_[4] ),
.I3(\TX_PHY_STATE_reg_n_0_[3] ),
.I4(GO_SYNC),
.I5(\TX_PHY_STATE_reg_n_0_[2] ),
.O(\TX_READ_ADDRESS_rep[9]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair122" *)
LUT5 #(
.INIT(32'h7FFF8000))
\TX_READ_ADDRESS_rep[9]_i_3
(.I0(TX_READ_ADDRESS[7]),
.I1(\TX_READ_ADDRESS_rep[9]_i_4_n_0 ),
.I2(TX_READ_ADDRESS[6]),
.I3(TX_READ_ADDRESS[8]),
.I4(TX_READ_ADDRESS[9]),
.O(TX_READ_ADDRESS0[9]));
LUT6 #(
.INIT(64'h8000000000000000))
\TX_READ_ADDRESS_rep[9]_i_4
(.I0(TX_READ_ADDRESS[5]),
.I1(TX_READ_ADDRESS[3]),
.I2(TX_READ_ADDRESS[1]),
.I3(TX_READ_ADDRESS[0]),
.I4(TX_READ_ADDRESS[2]),
.I5(TX_READ_ADDRESS[4]),
.O(\TX_READ_ADDRESS_rep[9]_i_4_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair142" *)
LUT2 #(
.INIT(4'h1))
\TX_WRITE_ADDRESS[0]_i_1
(.I0(\TX_PACKET_STATE_reg_n_0_[1] ),
.I1(TX_WRITE_ADDRESS[0]),
.O(\TX_WRITE_ADDRESS[0]_i_1_n_0 ));
LUT4 #(
.INIT(16'h04F0))
\TX_WRITE_ADDRESS[10]_i_1
(.I0(\TX_PACKET_STATE_reg[1]_i_2_n_2 ),
.I1(S_TX_ACK_reg_n_0),
.I2(\TX_PACKET_STATE_reg_n_0_[1] ),
.I3(\TX_PACKET_STATE_reg_n_0_[0] ),
.O(\TX_WRITE_ADDRESS[10]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair142" *)
LUT4 #(
.INIT(16'h0078))
\TX_WRITE_ADDRESS[10]_i_2
(.I0(\TX_WRITE_ADDRESS[10]_i_3_n_0 ),
.I1(TX_WRITE_ADDRESS[9]),
.I2(TX_WRITE_ADDRESS[10]),
.I3(\TX_PACKET_STATE_reg_n_0_[1] ),
.O(\TX_WRITE_ADDRESS[10]_i_2_n_0 ));
LUT4 #(
.INIT(16'h0800))
\TX_WRITE_ADDRESS[10]_i_3
(.I0(TX_WRITE_ADDRESS[8]),
.I1(TX_WRITE_ADDRESS[7]),
.I2(\TX_WRITE_ADDRESS[9]_i_2_n_0 ),
.I3(TX_WRITE_ADDRESS[6]),
.O(\TX_WRITE_ADDRESS[10]_i_3_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair149" *)
LUT3 #(
.INIT(8'h06))
\TX_WRITE_ADDRESS[1]_i_1
(.I0(TX_WRITE_ADDRESS[1]),
.I1(TX_WRITE_ADDRESS[0]),
.I2(\TX_PACKET_STATE_reg_n_0_[1] ),
.O(\TX_WRITE_ADDRESS[1]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair95" *)
LUT4 #(
.INIT(16'h1540))
\TX_WRITE_ADDRESS[2]_i_1
(.I0(\TX_PACKET_STATE_reg_n_0_[1] ),
.I1(TX_WRITE_ADDRESS[0]),
.I2(TX_WRITE_ADDRESS[1]),
.I3(TX_WRITE_ADDRESS[2]),
.O(\TX_WRITE_ADDRESS[2]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair95" *)
LUT5 #(
.INIT(32'h15554000))
\TX_WRITE_ADDRESS[3]_i_1
(.I0(\TX_PACKET_STATE_reg_n_0_[1] ),
.I1(TX_WRITE_ADDRESS[1]),
.I2(TX_WRITE_ADDRESS[0]),
.I3(TX_WRITE_ADDRESS[2]),
.I4(TX_WRITE_ADDRESS[3]),
.O(\TX_WRITE_ADDRESS[3]_i_1_n_0 ));
LUT6 #(
.INIT(64'h1555555540000000))
\TX_WRITE_ADDRESS[4]_i_1
(.I0(\TX_PACKET_STATE_reg_n_0_[1] ),
.I1(TX_WRITE_ADDRESS[2]),
.I2(TX_WRITE_ADDRESS[0]),
.I3(TX_WRITE_ADDRESS[1]),
.I4(TX_WRITE_ADDRESS[3]),
.I5(TX_WRITE_ADDRESS[4]),
.O(\TX_WRITE_ADDRESS[4]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair149" *)
LUT3 #(
.INIT(8'h41))
\TX_WRITE_ADDRESS[5]_i_1
(.I0(\TX_PACKET_STATE_reg_n_0_[1] ),
.I1(\TX_WRITE_ADDRESS[5]_i_2_n_0 ),
.I2(TX_WRITE_ADDRESS[5]),
.O(\TX_WRITE_ADDRESS[5]_i_1_n_0 ));
LUT5 #(
.INIT(32'h7FFFFFFF))
\TX_WRITE_ADDRESS[5]_i_2
(.I0(TX_WRITE_ADDRESS[3]),
.I1(TX_WRITE_ADDRESS[1]),
.I2(TX_WRITE_ADDRESS[0]),
.I3(TX_WRITE_ADDRESS[2]),
.I4(TX_WRITE_ADDRESS[4]),
.O(\TX_WRITE_ADDRESS[5]_i_2_n_0 ));
LUT3 #(
.INIT(8'h41))
\TX_WRITE_ADDRESS[6]_i_1
(.I0(\TX_PACKET_STATE_reg_n_0_[1] ),
.I1(\TX_WRITE_ADDRESS[9]_i_2_n_0 ),
.I2(TX_WRITE_ADDRESS[6]),
.O(\TX_WRITE_ADDRESS[6]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair84" *)
LUT4 #(
.INIT(16'h4510))
\TX_WRITE_ADDRESS[7]_i_1
(.I0(\TX_PACKET_STATE_reg_n_0_[1] ),
.I1(\TX_WRITE_ADDRESS[9]_i_2_n_0 ),
.I2(TX_WRITE_ADDRESS[6]),
.I3(TX_WRITE_ADDRESS[7]),
.O(\TX_WRITE_ADDRESS[7]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair84" *)
LUT5 #(
.INIT(32'h51550400))
\TX_WRITE_ADDRESS[8]_i_1
(.I0(\TX_PACKET_STATE_reg_n_0_[1] ),
.I1(TX_WRITE_ADDRESS[6]),
.I2(\TX_WRITE_ADDRESS[9]_i_2_n_0 ),
.I3(TX_WRITE_ADDRESS[7]),
.I4(TX_WRITE_ADDRESS[8]),
.O(\TX_WRITE_ADDRESS[8]_i_1_n_0 ));
LUT6 #(
.INIT(64'h5515555500400000))
\TX_WRITE_ADDRESS[9]_i_1
(.I0(\TX_PACKET_STATE_reg_n_0_[1] ),
.I1(TX_WRITE_ADDRESS[8]),
.I2(TX_WRITE_ADDRESS[7]),
.I3(\TX_WRITE_ADDRESS[9]_i_2_n_0 ),
.I4(TX_WRITE_ADDRESS[6]),
.I5(TX_WRITE_ADDRESS[9]),
.O(\TX_WRITE_ADDRESS[9]_i_1_n_0 ));
LUT6 #(
.INIT(64'h7FFFFFFFFFFFFFFF))
\TX_WRITE_ADDRESS[9]_i_2
(.I0(TX_WRITE_ADDRESS[4]),
.I1(TX_WRITE_ADDRESS[2]),
.I2(TX_WRITE_ADDRESS[0]),
.I3(TX_WRITE_ADDRESS[1]),
.I4(TX_WRITE_ADDRESS[3]),
.I5(TX_WRITE_ADDRESS[5]),
.O(\TX_WRITE_ADDRESS[9]_i_2_n_0 ));
FDRE \TX_WRITE_ADDRESS_DEL_reg[0]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(TX_WRITE_ADDRESS[0]),
.Q(TX_WRITE_ADDRESS_DEL[0]),
.R(1'b0));
FDRE \TX_WRITE_ADDRESS_DEL_reg[10]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(TX_WRITE_ADDRESS[10]),
.Q(TX_WRITE_ADDRESS_DEL[10]),
.R(1'b0));
FDRE \TX_WRITE_ADDRESS_DEL_reg[1]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(TX_WRITE_ADDRESS[1]),
.Q(TX_WRITE_ADDRESS_DEL[1]),
.R(1'b0));
FDRE \TX_WRITE_ADDRESS_DEL_reg[2]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(TX_WRITE_ADDRESS[2]),
.Q(TX_WRITE_ADDRESS_DEL[2]),
.R(1'b0));
FDRE \TX_WRITE_ADDRESS_DEL_reg[3]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(TX_WRITE_ADDRESS[3]),
.Q(TX_WRITE_ADDRESS_DEL[3]),
.R(1'b0));
FDRE \TX_WRITE_ADDRESS_DEL_reg[4]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(TX_WRITE_ADDRESS[4]),
.Q(TX_WRITE_ADDRESS_DEL[4]),
.R(1'b0));
FDRE \TX_WRITE_ADDRESS_DEL_reg[5]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(TX_WRITE_ADDRESS[5]),
.Q(TX_WRITE_ADDRESS_DEL[5]),
.R(1'b0));
FDRE \TX_WRITE_ADDRESS_DEL_reg[6]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(TX_WRITE_ADDRESS[6]),
.Q(TX_WRITE_ADDRESS_DEL[6]),
.R(1'b0));
FDRE \TX_WRITE_ADDRESS_DEL_reg[7]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(TX_WRITE_ADDRESS[7]),
.Q(TX_WRITE_ADDRESS_DEL[7]),
.R(1'b0));
FDRE \TX_WRITE_ADDRESS_DEL_reg[8]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(TX_WRITE_ADDRESS[8]),
.Q(TX_WRITE_ADDRESS_DEL[8]),
.R(1'b0));
FDRE \TX_WRITE_ADDRESS_DEL_reg[9]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(TX_WRITE_ADDRESS[9]),
.Q(TX_WRITE_ADDRESS_DEL[9]),
.R(1'b0));
FDRE \TX_WRITE_ADDRESS_reg[0]
(.C(ETH_CLK_OBUF),
.CE(\TX_WRITE_ADDRESS[10]_i_1_n_0 ),
.D(\TX_WRITE_ADDRESS[0]_i_1_n_0 ),
.Q(TX_WRITE_ADDRESS[0]),
.R(INTERNAL_RST_reg));
FDRE \TX_WRITE_ADDRESS_reg[10]
(.C(ETH_CLK_OBUF),
.CE(\TX_WRITE_ADDRESS[10]_i_1_n_0 ),
.D(\TX_WRITE_ADDRESS[10]_i_2_n_0 ),
.Q(TX_WRITE_ADDRESS[10]),
.R(INTERNAL_RST_reg));
FDRE \TX_WRITE_ADDRESS_reg[1]
(.C(ETH_CLK_OBUF),
.CE(\TX_WRITE_ADDRESS[10]_i_1_n_0 ),
.D(\TX_WRITE_ADDRESS[1]_i_1_n_0 ),
.Q(TX_WRITE_ADDRESS[1]),
.R(INTERNAL_RST_reg));
FDRE \TX_WRITE_ADDRESS_reg[2]
(.C(ETH_CLK_OBUF),
.CE(\TX_WRITE_ADDRESS[10]_i_1_n_0 ),
.D(\TX_WRITE_ADDRESS[2]_i_1_n_0 ),
.Q(TX_WRITE_ADDRESS[2]),
.R(INTERNAL_RST_reg));
FDRE \TX_WRITE_ADDRESS_reg[3]
(.C(ETH_CLK_OBUF),
.CE(\TX_WRITE_ADDRESS[10]_i_1_n_0 ),
.D(\TX_WRITE_ADDRESS[3]_i_1_n_0 ),
.Q(TX_WRITE_ADDRESS[3]),
.R(INTERNAL_RST_reg));
FDRE \TX_WRITE_ADDRESS_reg[4]
(.C(ETH_CLK_OBUF),
.CE(\TX_WRITE_ADDRESS[10]_i_1_n_0 ),
.D(\TX_WRITE_ADDRESS[4]_i_1_n_0 ),
.Q(TX_WRITE_ADDRESS[4]),
.R(INTERNAL_RST_reg));
FDRE \TX_WRITE_ADDRESS_reg[5]
(.C(ETH_CLK_OBUF),
.CE(\TX_WRITE_ADDRESS[10]_i_1_n_0 ),
.D(\TX_WRITE_ADDRESS[5]_i_1_n_0 ),
.Q(TX_WRITE_ADDRESS[5]),
.R(INTERNAL_RST_reg));
FDRE \TX_WRITE_ADDRESS_reg[6]
(.C(ETH_CLK_OBUF),
.CE(\TX_WRITE_ADDRESS[10]_i_1_n_0 ),
.D(\TX_WRITE_ADDRESS[6]_i_1_n_0 ),
.Q(TX_WRITE_ADDRESS[6]),
.R(INTERNAL_RST_reg));
FDRE \TX_WRITE_ADDRESS_reg[7]
(.C(ETH_CLK_OBUF),
.CE(\TX_WRITE_ADDRESS[10]_i_1_n_0 ),
.D(\TX_WRITE_ADDRESS[7]_i_1_n_0 ),
.Q(TX_WRITE_ADDRESS[7]),
.R(INTERNAL_RST_reg));
FDRE \TX_WRITE_ADDRESS_reg[8]
(.C(ETH_CLK_OBUF),
.CE(\TX_WRITE_ADDRESS[10]_i_1_n_0 ),
.D(\TX_WRITE_ADDRESS[8]_i_1_n_0 ),
.Q(TX_WRITE_ADDRESS[8]),
.R(INTERNAL_RST_reg));
FDRE \TX_WRITE_ADDRESS_reg[9]
(.C(ETH_CLK_OBUF),
.CE(\TX_WRITE_ADDRESS[10]_i_1_n_0 ),
.D(\TX_WRITE_ADDRESS[9]_i_1_n_0 ),
.Q(TX_WRITE_ADDRESS[9]),
.R(INTERNAL_RST_reg));
(* SOFT_HLUTNM = "soft_lutpair85" *)
LUT3 #(
.INIT(8'h20))
TX_WRITE_i_1
(.I0(S_TX_ACK_reg_n_0),
.I1(\TX_PACKET_STATE_reg_n_0_[1] ),
.I2(\TX_PACKET_STATE_reg_n_0_[0] ),
.O(TX_WRITE_i_1_n_0));
FDRE TX_WRITE_reg
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(TX_WRITE_i_1_n_0),
.Q(TX_WRITE),
.R(1'b0));
endmodule
|
module serial_output
(IN1_ACK,
RS232_TX_OBUF,
INTERNAL_RST_reg,
ETH_CLK_OBUF,
IN1_STB,
Q);
output IN1_ACK;
output RS232_TX_OBUF;
input INTERNAL_RST_reg;
input ETH_CLK_OBUF;
input IN1_STB;
input [7:0]Q;
wire [11:0]BAUD_COUNT;
wire \BAUD_COUNT[11]_i_2__0_n_0 ;
wire \BAUD_COUNT[11]_i_3__0_n_0 ;
wire \BAUD_COUNT_reg[4]_i_2_n_0 ;
wire \BAUD_COUNT_reg[8]_i_2_n_0 ;
wire \BAUD_COUNT_reg_n_0_[0] ;
wire \BAUD_COUNT_reg_n_0_[10] ;
wire \BAUD_COUNT_reg_n_0_[11] ;
wire \BAUD_COUNT_reg_n_0_[1] ;
wire \BAUD_COUNT_reg_n_0_[2] ;
wire \BAUD_COUNT_reg_n_0_[3] ;
wire \BAUD_COUNT_reg_n_0_[4] ;
wire \BAUD_COUNT_reg_n_0_[5] ;
wire \BAUD_COUNT_reg_n_0_[6] ;
wire \BAUD_COUNT_reg_n_0_[7] ;
wire \BAUD_COUNT_reg_n_0_[8] ;
wire \BAUD_COUNT_reg_n_0_[9] ;
wire \DATA[7]_i_1_n_0 ;
wire \DATA_reg_n_0_[0] ;
wire ETH_CLK_OBUF;
wire \FSM_sequential_STATE[0]_i_1_n_0 ;
wire \FSM_sequential_STATE[1]_i_1_n_0 ;
wire \FSM_sequential_STATE[2]_i_1_n_0 ;
wire \FSM_sequential_STATE[3]_i_1_n_0 ;
wire \FSM_sequential_STATE[3]_i_2_n_0 ;
wire IN1_ACK;
wire IN1_STB;
wire INTERNAL_RST_reg;
wire [7:0]Q;
wire RS232_TX_OBUF;
(* RTL_KEEP = "yes" *) wire [3:0]STATE;
wire S_IN1_ACK1;
wire S_IN1_ACK_i_1_n_0;
wire TX_i_1_n_0;
wire TX_i_3_n_0;
wire TX_i_4_n_0;
wire TX_i_5_n_0;
wire TX_i_6_n_0;
wire TX_reg_i_2_n_0;
wire X16CLK_EN_i_1__0_n_0;
wire X16CLK_EN_reg_n_0;
wire [11:1]data0;
wire p_0_in;
wire p_1_in;
wire p_2_in;
wire p_3_in;
wire p_4_in;
wire p_5_in;
wire p_6_in;
wire [3:0]\NLW_BAUD_COUNT_reg[11]_i_4_CO_UNCONNECTED ;
wire [3:3]\NLW_BAUD_COUNT_reg[11]_i_4_O_UNCONNECTED ;
wire [2:0]\NLW_BAUD_COUNT_reg[4]_i_2_CO_UNCONNECTED ;
wire [2:0]\NLW_BAUD_COUNT_reg[8]_i_2_CO_UNCONNECTED ;
LUT1 #(
.INIT(2'h1))
\BAUD_COUNT[0]_i_1
(.I0(\BAUD_COUNT_reg_n_0_[0] ),
.O(BAUD_COUNT[0]));
(* SOFT_HLUTNM = "soft_lutpair62" *)
LUT3 #(
.INIT(8'hE0))
\BAUD_COUNT[10]_i_1__0
(.I0(\BAUD_COUNT[11]_i_2__0_n_0 ),
.I1(\BAUD_COUNT[11]_i_3__0_n_0 ),
.I2(data0[10]),
.O(BAUD_COUNT[10]));
(* SOFT_HLUTNM = "soft_lutpair63" *)
LUT3 #(
.INIT(8'hE0))
\BAUD_COUNT[11]_i_1__0
(.I0(\BAUD_COUNT[11]_i_2__0_n_0 ),
.I1(\BAUD_COUNT[11]_i_3__0_n_0 ),
.I2(data0[11]),
.O(BAUD_COUNT[11]));
LUT6 #(
.INIT(64'hFFFFFEFFFFFFFFFF))
\BAUD_COUNT[11]_i_2__0
(.I0(\BAUD_COUNT_reg_n_0_[10] ),
.I1(\BAUD_COUNT_reg_n_0_[9] ),
.I2(\BAUD_COUNT_reg_n_0_[6] ),
.I3(\BAUD_COUNT_reg_n_0_[7] ),
.I4(\BAUD_COUNT_reg_n_0_[11] ),
.I5(\BAUD_COUNT_reg_n_0_[5] ),
.O(\BAUD_COUNT[11]_i_2__0_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFFFFFFDFFF))
\BAUD_COUNT[11]_i_3__0
(.I0(\BAUD_COUNT_reg_n_0_[8] ),
.I1(\BAUD_COUNT_reg_n_0_[1] ),
.I2(\BAUD_COUNT_reg_n_0_[4] ),
.I3(\BAUD_COUNT_reg_n_0_[0] ),
.I4(\BAUD_COUNT_reg_n_0_[2] ),
.I5(\BAUD_COUNT_reg_n_0_[3] ),
.O(\BAUD_COUNT[11]_i_3__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair59" *)
LUT3 #(
.INIT(8'hE0))
\BAUD_COUNT[1]_i_1__0
(.I0(\BAUD_COUNT[11]_i_2__0_n_0 ),
.I1(\BAUD_COUNT[11]_i_3__0_n_0 ),
.I2(data0[1]),
.O(BAUD_COUNT[1]));
(* SOFT_HLUTNM = "soft_lutpair59" *)
LUT3 #(
.INIT(8'hE0))
\BAUD_COUNT[2]_i_1__0
(.I0(\BAUD_COUNT[11]_i_2__0_n_0 ),
.I1(\BAUD_COUNT[11]_i_3__0_n_0 ),
.I2(data0[2]),
.O(BAUD_COUNT[2]));
(* SOFT_HLUTNM = "soft_lutpair60" *)
LUT3 #(
.INIT(8'hE0))
\BAUD_COUNT[3]_i_1__0
(.I0(\BAUD_COUNT[11]_i_2__0_n_0 ),
.I1(\BAUD_COUNT[11]_i_3__0_n_0 ),
.I2(data0[3]),
.O(BAUD_COUNT[3]));
(* SOFT_HLUTNM = "soft_lutpair60" *)
LUT3 #(
.INIT(8'hE0))
\BAUD_COUNT[4]_i_1__0
(.I0(\BAUD_COUNT[11]_i_2__0_n_0 ),
.I1(\BAUD_COUNT[11]_i_3__0_n_0 ),
.I2(data0[4]),
.O(BAUD_COUNT[4]));
(* SOFT_HLUTNM = "soft_lutpair61" *)
LUT3 #(
.INIT(8'hE0))
\BAUD_COUNT[5]_i_1__0
(.I0(\BAUD_COUNT[11]_i_2__0_n_0 ),
.I1(\BAUD_COUNT[11]_i_3__0_n_0 ),
.I2(data0[5]),
.O(BAUD_COUNT[5]));
(* SOFT_HLUTNM = "soft_lutpair58" *)
LUT3 #(
.INIT(8'hE0))
\BAUD_COUNT[6]_i_1__0
(.I0(\BAUD_COUNT[11]_i_2__0_n_0 ),
.I1(\BAUD_COUNT[11]_i_3__0_n_0 ),
.I2(data0[6]),
.O(BAUD_COUNT[6]));
(* SOFT_HLUTNM = "soft_lutpair61" *)
LUT3 #(
.INIT(8'hE0))
\BAUD_COUNT[7]_i_1__0
(.I0(\BAUD_COUNT[11]_i_2__0_n_0 ),
.I1(\BAUD_COUNT[11]_i_3__0_n_0 ),
.I2(data0[7]),
.O(BAUD_COUNT[7]));
(* SOFT_HLUTNM = "soft_lutpair62" *)
LUT3 #(
.INIT(8'hE0))
\BAUD_COUNT[8]_i_1__0
(.I0(\BAUD_COUNT[11]_i_2__0_n_0 ),
.I1(\BAUD_COUNT[11]_i_3__0_n_0 ),
.I2(data0[8]),
.O(BAUD_COUNT[8]));
(* SOFT_HLUTNM = "soft_lutpair63" *)
LUT3 #(
.INIT(8'hE0))
\BAUD_COUNT[9]_i_1__0
(.I0(\BAUD_COUNT[11]_i_2__0_n_0 ),
.I1(\BAUD_COUNT[11]_i_3__0_n_0 ),
.I2(data0[9]),
.O(BAUD_COUNT[9]));
FDRE #(
.INIT(1'b0))
\BAUD_COUNT_reg[0]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(BAUD_COUNT[0]),
.Q(\BAUD_COUNT_reg_n_0_[0] ),
.R(INTERNAL_RST_reg));
FDRE #(
.INIT(1'b0))
\BAUD_COUNT_reg[10]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(BAUD_COUNT[10]),
.Q(\BAUD_COUNT_reg_n_0_[10] ),
.R(INTERNAL_RST_reg));
FDRE #(
.INIT(1'b0))
\BAUD_COUNT_reg[11]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(BAUD_COUNT[11]),
.Q(\BAUD_COUNT_reg_n_0_[11] ),
.R(INTERNAL_RST_reg));
CARRY4 \BAUD_COUNT_reg[11]_i_4
(.CI(\BAUD_COUNT_reg[8]_i_2_n_0 ),
.CO(\NLW_BAUD_COUNT_reg[11]_i_4_CO_UNCONNECTED [3:0]),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O({\NLW_BAUD_COUNT_reg[11]_i_4_O_UNCONNECTED [3],data0[11:9]}),
.S({1'b0,\BAUD_COUNT_reg_n_0_[11] ,\BAUD_COUNT_reg_n_0_[10] ,\BAUD_COUNT_reg_n_0_[9] }));
FDRE #(
.INIT(1'b0))
\BAUD_COUNT_reg[1]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(BAUD_COUNT[1]),
.Q(\BAUD_COUNT_reg_n_0_[1] ),
.R(INTERNAL_RST_reg));
FDRE #(
.INIT(1'b0))
\BAUD_COUNT_reg[2]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(BAUD_COUNT[2]),
.Q(\BAUD_COUNT_reg_n_0_[2] ),
.R(INTERNAL_RST_reg));
FDRE #(
.INIT(1'b0))
\BAUD_COUNT_reg[3]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(BAUD_COUNT[3]),
.Q(\BAUD_COUNT_reg_n_0_[3] ),
.R(INTERNAL_RST_reg));
FDRE #(
.INIT(1'b0))
\BAUD_COUNT_reg[4]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(BAUD_COUNT[4]),
.Q(\BAUD_COUNT_reg_n_0_[4] ),
.R(INTERNAL_RST_reg));
CARRY4 \BAUD_COUNT_reg[4]_i_2
(.CI(1'b0),
.CO({\BAUD_COUNT_reg[4]_i_2_n_0 ,\NLW_BAUD_COUNT_reg[4]_i_2_CO_UNCONNECTED [2:0]}),
.CYINIT(\BAUD_COUNT_reg_n_0_[0] ),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(data0[4:1]),
.S({\BAUD_COUNT_reg_n_0_[4] ,\BAUD_COUNT_reg_n_0_[3] ,\BAUD_COUNT_reg_n_0_[2] ,\BAUD_COUNT_reg_n_0_[1] }));
FDRE #(
.INIT(1'b0))
\BAUD_COUNT_reg[5]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(BAUD_COUNT[5]),
.Q(\BAUD_COUNT_reg_n_0_[5] ),
.R(INTERNAL_RST_reg));
FDRE #(
.INIT(1'b0))
\BAUD_COUNT_reg[6]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(BAUD_COUNT[6]),
.Q(\BAUD_COUNT_reg_n_0_[6] ),
.R(INTERNAL_RST_reg));
FDRE #(
.INIT(1'b0))
\BAUD_COUNT_reg[7]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(BAUD_COUNT[7]),
.Q(\BAUD_COUNT_reg_n_0_[7] ),
.R(INTERNAL_RST_reg));
FDRE #(
.INIT(1'b0))
\BAUD_COUNT_reg[8]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(BAUD_COUNT[8]),
.Q(\BAUD_COUNT_reg_n_0_[8] ),
.R(INTERNAL_RST_reg));
CARRY4 \BAUD_COUNT_reg[8]_i_2
(.CI(\BAUD_COUNT_reg[4]_i_2_n_0 ),
.CO({\BAUD_COUNT_reg[8]_i_2_n_0 ,\NLW_BAUD_COUNT_reg[8]_i_2_CO_UNCONNECTED [2:0]}),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(data0[8:5]),
.S({\BAUD_COUNT_reg_n_0_[8] ,\BAUD_COUNT_reg_n_0_[7] ,\BAUD_COUNT_reg_n_0_[6] ,\BAUD_COUNT_reg_n_0_[5] }));
FDRE #(
.INIT(1'b0))
\BAUD_COUNT_reg[9]
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(BAUD_COUNT[9]),
.Q(\BAUD_COUNT_reg_n_0_[9] ),
.R(INTERNAL_RST_reg));
LUT6 #(
.INIT(64'h0000000000001000))
\DATA[7]_i_1
(.I0(STATE[1]),
.I1(STATE[3]),
.I2(IN1_ACK),
.I3(IN1_STB),
.I4(STATE[2]),
.I5(STATE[0]),
.O(\DATA[7]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\DATA_reg[0]
(.C(ETH_CLK_OBUF),
.CE(\DATA[7]_i_1_n_0 ),
.D(Q[0]),
.Q(\DATA_reg_n_0_[0] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\DATA_reg[1]
(.C(ETH_CLK_OBUF),
.CE(\DATA[7]_i_1_n_0 ),
.D(Q[1]),
.Q(p_6_in),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\DATA_reg[2]
(.C(ETH_CLK_OBUF),
.CE(\DATA[7]_i_1_n_0 ),
.D(Q[2]),
.Q(p_5_in),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\DATA_reg[3]
(.C(ETH_CLK_OBUF),
.CE(\DATA[7]_i_1_n_0 ),
.D(Q[3]),
.Q(p_4_in),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\DATA_reg[4]
(.C(ETH_CLK_OBUF),
.CE(\DATA[7]_i_1_n_0 ),
.D(Q[4]),
.Q(p_3_in),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\DATA_reg[5]
(.C(ETH_CLK_OBUF),
.CE(\DATA[7]_i_1_n_0 ),
.D(Q[5]),
.Q(p_2_in),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\DATA_reg[6]
(.C(ETH_CLK_OBUF),
.CE(\DATA[7]_i_1_n_0 ),
.D(Q[6]),
.Q(p_1_in),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\DATA_reg[7]
(.C(ETH_CLK_OBUF),
.CE(\DATA[7]_i_1_n_0 ),
.D(Q[7]),
.Q(p_0_in),
.R(1'b0));
LUT3 #(
.INIT(8'h07))
\FSM_sequential_STATE[0]_i_1
(.I0(STATE[2]),
.I1(STATE[3]),
.I2(STATE[0]),
.O(\FSM_sequential_STATE[0]_i_1_n_0 ));
LUT4 #(
.INIT(16'h152A))
\FSM_sequential_STATE[1]_i_1
(.I0(STATE[0]),
.I1(STATE[2]),
.I2(STATE[3]),
.I3(STATE[1]),
.O(\FSM_sequential_STATE[1]_i_1_n_0 ));
LUT4 #(
.INIT(16'h0078))
\FSM_sequential_STATE[2]_i_1
(.I0(STATE[1]),
.I1(STATE[0]),
.I2(STATE[2]),
.I3(STATE[3]),
.O(\FSM_sequential_STATE[2]_i_1_n_0 ));
LUT6 #(
.INIT(64'h0F00FF010F00FE00))
\FSM_sequential_STATE[3]_i_1
(.I0(STATE[0]),
.I1(STATE[1]),
.I2(STATE[2]),
.I3(X16CLK_EN_reg_n_0),
.I4(STATE[3]),
.I5(S_IN1_ACK1),
.O(\FSM_sequential_STATE[3]_i_1_n_0 ));
LUT4 #(
.INIT(16'h0870))
\FSM_sequential_STATE[3]_i_2
(.I0(STATE[1]),
.I1(STATE[0]),
.I2(STATE[3]),
.I3(STATE[2]),
.O(\FSM_sequential_STATE[3]_i_2_n_0 ));
LUT2 #(
.INIT(4'h8))
\FSM_sequential_STATE[3]_i_3
(.I0(IN1_ACK),
.I1(IN1_STB),
.O(S_IN1_ACK1));
(* KEEP = "yes" *)
FDRE \FSM_sequential_STATE_reg[0]
(.C(ETH_CLK_OBUF),
.CE(\FSM_sequential_STATE[3]_i_1_n_0 ),
.D(\FSM_sequential_STATE[0]_i_1_n_0 ),
.Q(STATE[0]),
.R(INTERNAL_RST_reg));
(* KEEP = "yes" *)
FDRE \FSM_sequential_STATE_reg[1]
(.C(ETH_CLK_OBUF),
.CE(\FSM_sequential_STATE[3]_i_1_n_0 ),
.D(\FSM_sequential_STATE[1]_i_1_n_0 ),
.Q(STATE[1]),
.R(INTERNAL_RST_reg));
(* KEEP = "yes" *)
FDRE \FSM_sequential_STATE_reg[2]
(.C(ETH_CLK_OBUF),
.CE(\FSM_sequential_STATE[3]_i_1_n_0 ),
.D(\FSM_sequential_STATE[2]_i_1_n_0 ),
.Q(STATE[2]),
.R(INTERNAL_RST_reg));
(* KEEP = "yes" *)
FDRE \FSM_sequential_STATE_reg[3]
(.C(ETH_CLK_OBUF),
.CE(\FSM_sequential_STATE[3]_i_1_n_0 ),
.D(\FSM_sequential_STATE[3]_i_2_n_0 ),
.Q(STATE[3]),
.R(INTERNAL_RST_reg));
LUT6 #(
.INIT(64'hFFFFFFFD00000003))
S_IN1_ACK_i_1
(.I0(IN1_STB),
.I1(STATE[1]),
.I2(STATE[3]),
.I3(STATE[2]),
.I4(STATE[0]),
.I5(IN1_ACK),
.O(S_IN1_ACK_i_1_n_0));
FDRE #(
.INIT(1'b0))
S_IN1_ACK_reg
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(S_IN1_ACK_i_1_n_0),
.Q(IN1_ACK),
.R(INTERNAL_RST_reg));
LUT6 #(
.INIT(64'hFFAAAABA00AAAA8A))
TX_i_1
(.I0(TX_reg_i_2_n_0),
.I1(STATE[1]),
.I2(STATE[0]),
.I3(STATE[3]),
.I4(STATE[2]),
.I5(RS232_TX_OBUF),
.O(TX_i_1_n_0));
LUT6 #(
.INIT(64'h0AC0FFFF0AC00000))
TX_i_3
(.I0(p_4_in),
.I1(p_0_in),
.I2(STATE[3]),
.I3(STATE[2]),
.I4(STATE[1]),
.I5(TX_i_5_n_0),
.O(TX_i_3_n_0));
LUT6 #(
.INIT(64'h0AFCFFFF0AFC0000))
TX_i_4
(.I0(p_3_in),
.I1(\DATA_reg_n_0_[0] ),
.I2(STATE[3]),
.I3(STATE[2]),
.I4(STATE[1]),
.I5(TX_i_6_n_0),
.O(TX_i_4_n_0));
LUT4 #(
.INIT(16'h0ACF))
TX_i_5
(.I0(p_6_in),
.I1(p_2_in),
.I2(STATE[3]),
.I3(STATE[2]),
.O(TX_i_5_n_0));
LUT4 #(
.INIT(16'h30BB))
TX_i_6
(.I0(p_5_in),
.I1(STATE[2]),
.I2(p_1_in),
.I3(STATE[3]),
.O(TX_i_6_n_0));
FDSE #(
.INIT(1'b1))
TX_reg
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(TX_i_1_n_0),
.Q(RS232_TX_OBUF),
.S(INTERNAL_RST_reg));
MUXF7 TX_reg_i_2
(.I0(TX_i_3_n_0),
.I1(TX_i_4_n_0),
.O(TX_reg_i_2_n_0),
.S(STATE[0]));
(* SOFT_HLUTNM = "soft_lutpair58" *)
LUT2 #(
.INIT(4'h1))
X16CLK_EN_i_1__0
(.I0(\BAUD_COUNT[11]_i_2__0_n_0 ),
.I1(\BAUD_COUNT[11]_i_3__0_n_0 ),
.O(X16CLK_EN_i_1__0_n_0));
FDRE #(
.INIT(1'b0))
X16CLK_EN_reg
(.C(ETH_CLK_OBUF),
.CE(1'b1),
.D(X16CLK_EN_i_1__0_n_0),
.Q(X16CLK_EN_reg_n_0),
.R(INTERNAL_RST_reg));
endmodule
|
module user_design
(IN1_STB,
OUT1_ACK,
output_rs232_out,
INTERNAL_RST_reg,
OUT1,
IN1_ACK,
ETH_CLK_OBUF,
OUT1_STB);
output IN1_STB;
output OUT1_ACK;
output [7:0]output_rs232_out;
input INTERNAL_RST_reg;
input [7:0]OUT1;
input IN1_ACK;
input ETH_CLK_OBUF;
input OUT1_STB;
wire ETH_CLK_OBUF;
wire IN1_ACK;
wire IN1_STB;
wire INTERNAL_RST_reg;
wire [7:0]OUT1;
wire OUT1_ACK;
wire OUT1_STB;
wire [7:0]output_rs232_out;
main_0 main_0_139931273178792
(.ETH_CLK_OBUF(ETH_CLK_OBUF),
.IN1_ACK(IN1_ACK),
.IN1_STB(IN1_STB),
.INTERNAL_RST_reg(INTERNAL_RST_reg),
.OUT1(OUT1),
.OUT1_ACK(OUT1_ACK),
.OUT1_STB(OUT1_STB),
.output_rs232_out(output_rs232_out));
endmodule
|
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
|
module bw_io_dtl_pad_pack12(se_buf ,up_open_buf ,down_25_buf ,cbu1 ,ref
,si ,clk ,vddo ,cbu0 ,cbd0 ,j_pack1 ,pack0_en ,rst_val_up_buf ,
pack1_en ,bsr_si ,j_pack0 ,jpack5 ,rst_val_dn_buf ,pack5 ,so ,bso ,
pack4 ,update_dr_buf ,por_l_buf ,rst_io_l_buf ,hiz_l_buf ,
reset_l_buf ,sel_bypass_buf ,clock_dr_buf ,cbd1 ,mode_ctl_buf ,
jpack4 ,jpack1 ,jpack0 ,shift_dr_buf );
output [2:0] pack5 ;
output [2:0] pack4 ;
input [1:0] se_buf ;
input [1:0] up_open_buf ;
input [1:0] down_25_buf ;
input [8:1] cbu1 ;
input [8:1] cbu0 ;
input [8:1] cbd0 ;
input [2:0] j_pack1 ;
input [1:0] rst_val_up_buf ;
input [2:0] j_pack0 ;
input [1:0] rst_val_dn_buf ;
input [1:0] update_dr_buf ;
input [1:0] por_l_buf ;
input [1:0] rst_io_l_buf ;
input [1:0] hiz_l_buf ;
input [1:0] reset_l_buf ;
input [1:0] sel_bypass_buf ;
input [1:0] clock_dr_buf ;
input [8:1] cbd1 ;
input [1:0] mode_ctl_buf ;
input [1:0] shift_dr_buf ;
inout [2:0] jpack5 ;
inout [2:0] jpack4 ;
inout [2:0] jpack1 ;
inout [2:0] jpack0 ;
output so ;
output bso ;
input ref ;
input si ;
input clk ;
input vddo ;
input pack0_en ;
input pack1_en ;
input bsr_si ;
supply1 vdd ;
supply0 vss ;
wire [2:0] pack0out ;
wire [11:1] bscan ;
wire [2:0] pack1out ;
wire [11:1] scan ;
wire [5:0] net64 ;
wire [2:0] net98 ;
wire [2:0] net132 ;
wire ck0 ;
wire ck1 ;
wire ck2 ;
wire ck3 ;
terminator I58_4_ (
.TERM (net64[1] ) );
terminator I61_2_ (
.TERM (net98[0] ) );
bw_io_dtl_pad I2_3_ (
.cbu ({cbu0 } ),
.cbd ({cbd0 } ),
.bypass_enable (vss ),
.so (scan[4] ),
.por_l (por_l_buf[0] ),
.clock_dr (clock_dr_buf[0] ),
.bypass_in (vss ),
.serial_in (vss ),
.update_dr (update_dr_buf[0] ),
.clk (ck0 ),
.reset_l (reset_l_buf[0] ),
.hiz_l (hiz_l_buf[0] ),
.ps_select (vss ),
.out_type (vss ),
.shift_dr (shift_dr_buf[0] ),
.rst_io_l (rst_io_l_buf[0] ),
.rst_val_up (rst_val_up_buf[0] ),
.bso (bscan[4] ),
.serial_out (net64[2] ),
.bsr_si (bscan[5] ),
.rst_val_dn (rst_val_dn_buf[0] ),
.mode_ctl (mode_ctl_buf[0] ),
.si (scan[5] ),
.oe (vss ),
.data (vdd ),
.se (se_buf[0] ),
.up_open (up_open_buf[0] ),
.down_25 (down_25_buf[0] ),
.to_core (pack4[1] ),
.ref (ref ),
.pad (jpack4[1] ),
.vddo (vddo ),
.sel_bypass (sel_bypass_buf[0] ) );
bw_io_dtl_pad dtl0_2_ (
.cbu ({cbu1 } ),
.cbd ({cbd1 } ),
.bypass_enable (vss ),
.so (scan[11] ),
.por_l (por_l_buf[1] ),
.clock_dr (clock_dr_buf[1] ),
.bypass_in (vss ),
.serial_in (vss ),
.update_dr (update_dr_buf[1] ),
.clk (ck2 ),
.reset_l (reset_l_buf[1] ),
.hiz_l (hiz_l_buf[1] ),
.ps_select (vss ),
.out_type (vss ),
.shift_dr (shift_dr_buf[1] ),
.rst_io_l (rst_io_l_buf[1] ),
.rst_val_up (rst_val_up_buf[1] ),
.bso (bscan[11] ),
.serial_out (net132[0] ),
.bsr_si (bscan[1] ),
.rst_val_dn (rst_val_dn_buf[1] ),
.mode_ctl (mode_ctl_buf[1] ),
.si (scan[1] ),
.oe (pack0_en ),
.data (j_pack0[0] ),
.se (se_buf[1] ),
.up_open (up_open_buf[1] ),
.down_25 (down_25_buf[1] ),
.to_core (pack0out[0] ),
.ref (ref ),
.pad (jpack0[0] ),
.vddo (vddo ),
.sel_bypass (sel_bypass_buf[1] ) );
bw_io_dtl_pad dtl1_0_ (
.cbu ({cbu1 } ),
.cbd ({cbd1 } ),
.bypass_enable (vss ),
.so (so ),
.por_l (por_l_buf[1] ),
.clock_dr (clock_dr_buf[1] ),
.bypass_in (vss ),
.serial_in (vss ),
.update_dr (update_dr_buf[1] ),
.clk (ck3 ),
.reset_l (reset_l_buf[1] ),
.hiz_l (hiz_l_buf[1] ),
.ps_select (vss ),
.out_type (vss ),
.shift_dr (shift_dr_buf[1] ),
.rst_io_l (rst_io_l_buf[1] ),
.rst_val_up (rst_val_up_buf[1] ),
.bso (bso ),
.serial_out (net98[2] ),
.bsr_si (bscan[7] ),
.rst_val_dn (rst_val_dn_buf[1] ),
.mode_ctl (mode_ctl_buf[1] ),
.si (scan[7] ),
.oe (pack1_en ),
.data (j_pack1[2] ),
.se (se_buf[1] ),
.up_open (up_open_buf[1] ),
.down_25 (down_25_buf[1] ),
.to_core (pack1out[2] ),
.ref (ref ),
.pad (jpack1[2] ),
.vddo (vddo ),
.sel_bypass (sel_bypass_buf[1] ) );
bw_u1_ckbuf_30x I62 (
.clk (ck2 ),
.rclk (clk ) );
bw_u1_ckbuf_30x I64 (
.clk (ck3 ),
.rclk (clk ) );
bw_u1_ckbuf_30x I65 (
.clk (ck0 ),
.rclk (clk ) );
terminator I58_5_ (
.TERM (net64[0] ) );
bw_io_dtl_pad I2_4_ (
.cbu ({cbu0 } ),
.cbd ({cbd0 } ),
.bypass_enable (vss ),
.so (scan[5] ),
.por_l (por_l_buf[0] ),
.clock_dr (clock_dr_buf[0] ),
.bypass_in (vss ),
.serial_in (vss ),
.update_dr (update_dr_buf[0] ),
.clk (ck0 ),
.reset_l (reset_l_buf[0] ),
.hiz_l (hiz_l_buf[0] ),
.ps_select (vss ),
.out_type (vss ),
.shift_dr (shift_dr_buf[0] ),
.rst_io_l (rst_io_l_buf[0] ),
.rst_val_up (rst_val_up_buf[0] ),
.bso (bscan[5] ),
.serial_out (net64[1] ),
.bsr_si (bscan[6] ),
.rst_val_dn (rst_val_dn_buf[0] ),
.mode_ctl (mode_ctl_buf[0] ),
.si (scan[6] ),
.oe (vss ),
.data (vdd ),
.se (se_buf[0] ),
.up_open (up_open_buf[0] ),
.down_25 (down_25_buf[0] ),
.to_core (pack5[0] ),
.ref (ref ),
.pad (jpack5[0] ),
.vddo (vddo ),
.sel_bypass (sel_bypass_buf[0] ) );
bw_io_dtl_pad dtl0_1_ (
.cbu ({cbu1 } ),
.cbd ({cbd1 } ),
.bypass_enable (vss ),
.so (scan[9] ),
.por_l (por_l_buf[1] ),
.clock_dr (clock_dr_buf[1] ),
.bypass_in (vss ),
.serial_in (vss ),
.update_dr (update_dr_buf[1] ),
.clk (ck2 ),
.reset_l (reset_l_buf[1] ),
.hiz_l (hiz_l_buf[1] ),
.ps_select (vss ),
.out_type (vss ),
.shift_dr (shift_dr_buf[1] ),
.rst_io_l (rst_io_l_buf[1] ),
.rst_val_up (rst_val_up_buf[1] ),
.bso (bscan[9] ),
.serial_out (net132[1] ),
.bsr_si (bscan[10] ),
.rst_val_dn (rst_val_dn_buf[1] ),
.mode_ctl (mode_ctl_buf[1] ),
.si (scan[10] ),
.oe (pack0_en ),
.data (j_pack0[1] ),
.se (se_buf[1] ),
.up_open (up_open_buf[1] ),
.down_25 (down_25_buf[1] ),
.to_core (pack0out[1] ),
.ref (ref ),
.pad (jpack0[1] ),
.vddo (vddo ),
.sel_bypass (sel_bypass_buf[1] ) );
terminator I57_0_ (
.TERM (net132[2] ) );
bw_io_dtl_pad I2_5_ (
.cbu ({cbu0 } ),
.cbd ({cbd0 } ),
.bypass_enable (vss ),
.so (scan[6] ),
.por_l (por_l_buf[0] ),
.clock_dr (clock_dr_buf[0] ),
.bypass_in (vss ),
.serial_in (vss ),
.update_dr (update_dr_buf[0] ),
.clk (ck0 ),
.reset_l (reset_l_buf[0] ),
.hiz_l (hiz_l_buf[0] ),
.ps_select (vss ),
.out_type (vss ),
.shift_dr (shift_dr_buf[0] ),
.rst_io_l (rst_io_l_buf[0] ),
.rst_val_up (rst_val_up_buf[0] ),
.bso (bscan[6] ),
.serial_out (net64[0] ),
.bsr_si (bsr_si ),
.rst_val_dn (rst_val_dn_buf[0] ),
.mode_ctl (mode_ctl_buf[0] ),
.si (si ),
.oe (vss ),
.data (vdd ),
.se (se_buf[0] ),
.up_open (up_open_buf[0] ),
.down_25 (down_25_buf[0] ),
.to_core (pack4[0] ),
.ref (ref ),
.pad (jpack4[0] ),
.vddo (vddo ),
.sel_bypass (sel_bypass_buf[0] ) );
bw_io_dtl_pad dtl1_2_ (
.cbu ({cbu1 } ),
.cbd ({cbd1 } ),
.bypass_enable (vss ),
.so (scan[10] ),
.por_l (por_l_buf[1] ),
.clock_dr (clock_dr_buf[1] ),
.bypass_in (vss ),
.serial_in (vss ),
.update_dr (update_dr_buf[1] ),
.clk (ck3 ),
.reset_l (reset_l_buf[1] ),
.hiz_l (hiz_l_buf[1] ),
.ps_select (vss ),
.out_type (vss ),
.shift_dr (shift_dr_buf[1] ),
.rst_io_l (rst_io_l_buf[1] ),
.rst_val_up (rst_val_up_buf[1] ),
.bso (bscan[10] ),
.serial_out (net98[0] ),
.bsr_si (bscan[11] ),
.rst_val_dn (rst_val_dn_buf[1] ),
.mode_ctl (mode_ctl_buf[1] ),
.si (scan[11] ),
.oe (pack1_en ),
.data (j_pack1[0] ),
.se (se_buf[1] ),
.up_open (up_open_buf[1] ),
.down_25 (down_25_buf[1] ),
.to_core (pack1out[0] ),
.ref (ref ),
.pad (jpack1[0] ),
.vddo (vddo ),
.sel_bypass (sel_bypass_buf[1] ) );
bw_u1_ckbuf_30x I85 (
.clk (ck1 ),
.rclk (clk ) );
terminator I57_1_ (
.TERM (net132[1] ) );
bw_io_dtl_pad dtl1_1_ (
.cbu ({cbu1 } ),
.cbd ({cbd1 } ),
.bypass_enable (vss ),
.so (scan[8] ),
.por_l (por_l_buf[1] ),
.clock_dr (clock_dr_buf[1] ),
.bypass_in (vss ),
.serial_in (vss ),
.update_dr (update_dr_buf[1] ),
.clk (ck3 ),
.reset_l (reset_l_buf[1] ),
.hiz_l (hiz_l_buf[1] ),
.ps_select (vss ),
.out_type (vss ),
.shift_dr (shift_dr_buf[1] ),
.rst_io_l (rst_io_l_buf[1] ),
.rst_val_up (rst_val_up_buf[1] ),
.bso (bscan[8] ),
.serial_out (net98[1] ),
.bsr_si (bscan[9] ),
.rst_val_dn (rst_val_dn_buf[1] ),
.mode_ctl (mode_ctl_buf[1] ),
.si (scan[9] ),
.oe (pack1_en ),
.data (j_pack1[1] ),
.se (se_buf[1] ),
.up_open (up_open_buf[1] ),
.down_25 (down_25_buf[1] ),
.to_core (pack1out[1] ),
.ref (ref ),
.pad (jpack1[1] ),
.vddo (vddo ),
.sel_bypass (sel_bypass_buf[1] ) );
terminator I58_0_ (
.TERM (net64[5] ) );
terminator I57_2_ (
.TERM (net132[0] ) );
terminator I58_1_ (
.TERM (net64[4] ) );
bw_io_dtl_pad I2_0_ (
.cbu ({cbu0 } ),
.cbd ({cbd0 } ),
.bypass_enable (vss ),
.so (scan[1] ),
.por_l (por_l_buf[0] ),
.clock_dr (clock_dr_buf[0] ),
.bypass_in (vss ),
.serial_in (vss ),
.update_dr (update_dr_buf[0] ),
.clk (ck1 ),
.reset_l (reset_l_buf[0] ),
.hiz_l (hiz_l_buf[0] ),
.ps_select (vss ),
.out_type (vss ),
.shift_dr (shift_dr_buf[0] ),
.rst_io_l (rst_io_l_buf[0] ),
.rst_val_up (rst_val_up_buf[0] ),
.bso (bscan[1] ),
.serial_out (net64[5] ),
.bsr_si (bscan[2] ),
.rst_val_dn (rst_val_dn_buf[0] ),
.mode_ctl (mode_ctl_buf[0] ),
.si (scan[2] ),
.oe (vss ),
.data (vdd ),
.se (se_buf[0] ),
.up_open (up_open_buf[0] ),
.down_25 (down_25_buf[0] ),
.to_core (pack5[2] ),
.ref (ref ),
.pad (jpack5[2] ),
.vddo (vddo ),
.sel_bypass (sel_bypass_buf[0] ) );
terminator I58_2_ (
.TERM (net64[3] ) );
terminator I61_0_ (
.TERM (net98[2] ) );
bw_io_dtl_pad I2_1_ (
.cbu ({cbu0 } ),
.cbd ({cbd0 } ),
.bypass_enable (vss ),
.so (scan[2] ),
.por_l (por_l_buf[0] ),
.clock_dr (clock_dr_buf[0] ),
.bypass_in (vss ),
.serial_in (vss ),
.update_dr (update_dr_buf[0] ),
.clk (ck1 ),
.reset_l (reset_l_buf[0] ),
.hiz_l (hiz_l_buf[0] ),
.ps_select (vss ),
.out_type (vss ),
.shift_dr (shift_dr_buf[0] ),
.rst_io_l (rst_io_l_buf[0] ),
.rst_val_up (rst_val_up_buf[0] ),
.bso (bscan[2] ),
.serial_out (net64[4] ),
.bsr_si (bscan[3] ),
.rst_val_dn (rst_val_dn_buf[0] ),
.mode_ctl (mode_ctl_buf[0] ),
.si (scan[3] ),
.oe (vss ),
.data (vdd ),
.se (se_buf[0] ),
.up_open (up_open_buf[0] ),
.down_25 (down_25_buf[0] ),
.to_core (pack4[2] ),
.ref (ref ),
.pad (jpack4[2] ),
.vddo (vddo ),
.sel_bypass (sel_bypass_buf[0] ) );
bw_io_dtl_pad dtl0_0_ (
.cbu ({cbu1 } ),
.cbd ({cbd1 } ),
.bypass_enable (vss ),
.so (scan[7] ),
.por_l (por_l_buf[1] ),
.clock_dr (clock_dr_buf[1] ),
.bypass_in (vss ),
.serial_in (vss ),
.update_dr (update_dr_buf[1] ),
.clk (ck2 ),
.reset_l (reset_l_buf[1] ),
.hiz_l (hiz_l_buf[1] ),
.ps_select (vss ),
.out_type (vss ),
.shift_dr (shift_dr_buf[1] ),
.rst_io_l (rst_io_l_buf[1] ),
.rst_val_up (rst_val_up_buf[1] ),
.bso (bscan[7] ),
.serial_out (net132[2] ),
.bsr_si (bscan[8] ),
.rst_val_dn (rst_val_dn_buf[1] ),
.mode_ctl (mode_ctl_buf[1] ),
.si (scan[8] ),
.oe (pack0_en ),
.data (j_pack0[2] ),
.se (se_buf[1] ),
.up_open (up_open_buf[1] ),
.down_25 (down_25_buf[1] ),
.to_core (pack0out[2] ),
.ref (ref ),
.pad (jpack0[2] ),
.vddo (vddo ),
.sel_bypass (sel_bypass_buf[1] ) );
terminator I58_3_ (
.TERM (net64[2] ) );
terminator I61_1_ (
.TERM (net98[1] ) );
bw_io_dtl_pad I2_2_ (
.cbu ({cbu0 } ),
.cbd ({cbd0 } ),
.bypass_enable (vss ),
.so (scan[3] ),
.por_l (por_l_buf[0] ),
.clock_dr (clock_dr_buf[0] ),
.bypass_in (vss ),
.serial_in (vss ),
.update_dr (update_dr_buf[0] ),
.clk (ck1 ),
.reset_l (reset_l_buf[0] ),
.hiz_l (hiz_l_buf[0] ),
.ps_select (vss ),
.out_type (vss ),
.shift_dr (shift_dr_buf[0] ),
.rst_io_l (rst_io_l_buf[0] ),
.rst_val_up (rst_val_up_buf[0] ),
.bso (bscan[3] ),
.serial_out (net64[3] ),
.bsr_si (bscan[4] ),
.rst_val_dn (rst_val_dn_buf[0] ),
.mode_ctl (mode_ctl_buf[0] ),
.si (scan[4] ),
.oe (vss ),
.data (vdd ),
.se (se_buf[0] ),
.up_open (up_open_buf[0] ),
.down_25 (down_25_buf[0] ),
.to_core (pack5[1] ),
.ref (ref ),
.pad (jpack5[1] ),
.vddo (vddo ),
.sel_bypass (sel_bypass_buf[0] ) );
terminator I122 (
.TERM (pack0out[2] ) );
terminator I51 (
.TERM (pack0out[1] ) );
terminator I52 (
.TERM (pack0out[0] ) );
terminator I53 (
.TERM (pack1out[2] ) );
terminator I54 (
.TERM (pack1out[1] ) );
terminator I55 (
.TERM (pack1out[0] ) );
endmodule
|
module usb_avalon_16bit
(
input clk,
input reset,
// avs_ctrl
input avs_ctrl_address,
input avs_ctrl_write,
input [7:0]avs_ctrl_writedata,
input avs_ctrl_read,
output [7:0]avs_ctrl_readdata,
// asi_uplink
output ready,
input valid,
input [15:0]data,
input startofpacket,
input endofpacket,
input empty,
// tx fifo interface
output tx_write,
output [15:0]tx_data,
output [1:0]tx_mask,
input tx_full,
// rx fifo interface
output rx_read,
input [15:0]rx_data,
input rx_mask,
input rx_empty
);
// === avs_ctrl ===========================================================
wire [7:0]readdata_fifo;
wire [7:0]status = { 7'b0000000, !rx_empty };
wire si_request; // request for send immediate
assign si_request = avs_ctrl_write && avs_ctrl_address && avs_ctrl_writedata[0];
assign avs_ctrl_readdata = avs_ctrl_read ?
(avs_ctrl_address ? status : readdata_fifo) : 8'd0;
// --- data register
reg rx_upper;
assign readdata_fifo = rx_upper ? rx_data[15:8] : rx_data[7:0];
assign rx_read = avs_ctrl_read && !avs_ctrl_address && !rx_empty && (!rx_mask || rx_upper);
always @(posedge clk or posedge reset)
begin
if (reset) rx_upper <= 0;
else if (avs_ctrl_read && !avs_ctrl_address && !rx_empty)
rx_upper <= !rx_upper && rx_mask;
end
// === asi_uplink =========================================================
assign ready = !tx_full;
wire tx_empty = endofpacket && empty;
wire tx_write_dat = valid && ready;
reg si; // send immediate request received
wire si_send = si && ready && !valid;
always @(posedge clk or posedge reset)
begin
if (reset) si <= 0;
else if (si_send) si <= 0;
else if (si_request) si <= 1;
end
assign tx_data = {data[7:0], data[15:8]};
assign tx_mask = si_send ? 2'b00 : {!tx_empty, 1'b1};
assign tx_write = si_send || tx_write_dat;
endmodule
|
module oq_regs_eval_full
#(
parameter SRAM_ADDR_WIDTH = 13,
parameter CTRL_WIDTH = 8,
parameter UDP_REG_SRC_WIDTH = 2,
parameter NUM_OUTPUT_QUEUES = 8,
parameter NUM_OQ_WIDTH = log2(NUM_OUTPUT_QUEUES),
parameter PKT_LEN_WIDTH = 11,
parameter PKT_WORDS_WIDTH = PKT_LEN_WIDTH-log2(CTRL_WIDTH),
parameter MAX_PKT = 2048/CTRL_WIDTH, // allow for 2K bytes,
parameter MIN_PKT = 60/CTRL_WIDTH + 1,
parameter PKTS_IN_RAM_WIDTH = log2((2**SRAM_ADDR_WIDTH)/MIN_PKT)
)
(
// --- Inputs from dst update ---
input dst_update,
input [NUM_OQ_WIDTH-1:0] dst_oq,
input [PKTS_IN_RAM_WIDTH-1:0] dst_max_pkts_in_q,
input [PKTS_IN_RAM_WIDTH-1:0] dst_num_pkts_in_q,
input dst_num_pkts_in_q_done,
input [SRAM_ADDR_WIDTH-1:0] dst_oq_full_thresh,
input [SRAM_ADDR_WIDTH-1:0] dst_num_words_left,
input dst_num_words_left_done,
// --- Inputs from src update ---
input src_update,
input [NUM_OQ_WIDTH-1:0] src_oq,
input [PKTS_IN_RAM_WIDTH-1:0] src_max_pkts_in_q,
input [PKTS_IN_RAM_WIDTH-1:0] src_num_pkts_in_q,
input src_num_pkts_in_q_done,
input [SRAM_ADDR_WIDTH-1:0] src_oq_full_thresh,
input [SRAM_ADDR_WIDTH-1:0] src_num_words_left,
input src_num_words_left_done,
// --- Clear the flag ---
input initialize,
input [NUM_OQ_WIDTH-1:0] initialize_oq,
output [NUM_OUTPUT_QUEUES-1:0] full,
// --- Misc
input clk,
input reset
);
function integer log2;
input integer number;
begin
log2=0;
while(2**log2<number) begin
log2=log2+1;
end
end
endfunction // log2
// ------------- Internal parameters --------------
// ------------- Wires/reg ------------------
reg [NUM_OUTPUT_QUEUES-1:0] full_pkts_in_q;
reg [NUM_OUTPUT_QUEUES-1:0] full_words_left;
wire src_full_pkts_in_q;
reg src_full_pkts_in_q_held;
wire dst_full_pkts_in_q;
wire src_full_words_left;
reg src_full_words_left_held;
wire dst_full_words_left;
reg dst_update_d1;
reg src_update_d1;
reg [PKTS_IN_RAM_WIDTH-1:0] dst_max_pkts_in_q_held;
reg [PKTS_IN_RAM_WIDTH-1:0] src_max_pkts_in_q_held;
reg [PKTS_IN_RAM_WIDTH-1:0] dst_oq_full_thresh_held;
reg [PKTS_IN_RAM_WIDTH-1:0] src_oq_full_thresh_held;
reg [NUM_OQ_WIDTH-1:0] dst_oq_held;
reg [NUM_OQ_WIDTH-1:0] src_oq_held;
reg src_num_pkts_in_q_done_held;
reg src_num_words_left_done_held;
// ------------- Logic ------------------
assign full = full_pkts_in_q | full_words_left;
assign src_full_pkts_in_q = src_num_pkts_in_q >= src_max_pkts_in_q_held &&
src_max_pkts_in_q_held != 0;
assign dst_full_pkts_in_q = dst_num_pkts_in_q >= dst_max_pkts_in_q_held &&
dst_max_pkts_in_q_held != 0;
assign src_full_words_left = src_num_words_left <= src_oq_full_thresh_held ||
src_num_words_left < 2 * MAX_PKT;
assign dst_full_words_left = dst_num_words_left <= dst_oq_full_thresh_held ||
dst_num_words_left < 2 * MAX_PKT;
always @(posedge clk)
begin
dst_update_d1 <= dst_update;
src_update_d1 <= src_update;
if (reset) begin
full_pkts_in_q <= 'h0;
full_words_left <= 'h0;
end
else begin
if (dst_update) begin
dst_oq_held <= dst_oq;
end
if (src_update) begin
src_oq_held <= src_oq;
end
// Latch the maximums the cycle immediately following the update
// notifications. The update notifications are linked to the read
// ports of the appropriate registers so the read value will always
// be returned in the next cycle.
if (dst_update_d1) begin
dst_max_pkts_in_q_held <= dst_max_pkts_in_q;
dst_oq_full_thresh_held <= dst_oq_full_thresh;
end
if (src_update_d1) begin
src_max_pkts_in_q_held <= src_max_pkts_in_q;
src_oq_full_thresh_held <= src_oq_full_thresh;
end
// Update the full status giving preference to stores over removes
// since we don't want to accidentally try adding to a full queue
// Number of packets in queue
if (dst_num_pkts_in_q_done) begin
full_pkts_in_q[dst_oq_held] <= dst_full_pkts_in_q;
src_num_pkts_in_q_done_held <= src_num_pkts_in_q_done;
src_full_pkts_in_q_held <= src_full_pkts_in_q;
end
else if (src_num_pkts_in_q_done) begin
full_pkts_in_q[src_oq_held] <= src_full_pkts_in_q;
end
else if (src_num_pkts_in_q_done_held) begin
full_pkts_in_q[src_oq_held] <= src_full_pkts_in_q_held;
end
else if (initialize) begin
full_pkts_in_q[initialize_oq] <= 1'b0;
end
// Number of words left:
if (dst_num_words_left_done) begin
full_words_left[dst_oq_held] <= dst_full_words_left;
src_num_words_left_done_held <= src_num_words_left_done;
src_full_words_left_held <= src_full_words_left;
end
else if (src_num_words_left_done) begin
full_words_left[src_oq_held] <= src_full_words_left;
end
else if (src_num_words_left_done_held) begin
full_words_left[src_oq_held] <= src_full_words_left_held;
end
else if (initialize) begin
full_words_left[initialize_oq] <= 1'b0;
end
end
end
endmodule
|
module sky130_fd_sc_hdll__dfstp (
Q ,
CLK ,
D ,
SET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
// Module ports
output Q ;
input CLK ;
input D ;
input SET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
// Local signals
wire buf_Q;
wire SET ;
// Delay Name Output Other arguments
not not0 (SET , SET_B );
sky130_fd_sc_hdll__udp_dff$PS_pp$PG$N `UNIT_DELAY dff0 (buf_Q , D, CLK, SET, , VPWR, VGND);
buf buf0 (Q , buf_Q );
endmodule
|
module top();
// Inputs are registered
reg D;
reg RESET;
// Outputs are wires
wire Q;
initial
begin
// Initial state is x for all inputs.
D = 1'bX;
RESET = 1'bX;
#20 D = 1'b0;
#40 RESET = 1'b0;
#60 D = 1'b1;
#80 RESET = 1'b1;
#100 D = 1'b0;
#120 RESET = 1'b0;
#140 RESET = 1'b1;
#160 D = 1'b1;
#180 RESET = 1'bx;
#200 D = 1'bx;
end
// Create a clock
reg GATE;
initial
begin
GATE = 1'b0;
end
always
begin
#5 GATE = ~GATE;
end
sky130_fd_sc_ms__udp_dlatch$PR dut (.D(D), .RESET(RESET), .Q(Q), .GATE(GATE));
endmodule
|
module rem_onestate
(
clk,
rst,
is_sticky,
delay_valid,
delay_cycles,
pred_valid,
pred_match,
pred_index,
act_input,
act_output,
act_index
);
input clk;
input rst;
input is_sticky;
input pred_valid;
input pred_match;
input [15:0] pred_index;
input delay_valid;
input [3:0] delay_cycles;
input act_input;
output reg act_output;
output reg [15:0] act_index;
reg activated;
reg [3:0] delay_cycles_reg;
reg [2+15:0] delay_shift;
always @(posedge clk ) begin
if (delay_valid==1) delay_cycles_reg <= delay_cycles;
if (rst) begin
act_output <= 0;
activated <= 0;
end
else
begin
delay_shift <= {delay_shift[14:2],act_input,2'b00};
activated <= (delay_cycles_reg>1) ? delay_shift[delay_cycles_reg] : act_input;
if (pred_valid) begin
if ((delay_cycles_reg==0 && act_input==1) || (delay_cycles_reg!=0 && activated==1) && pred_match==1) begin
act_output <= pred_match;
if (act_output==0) act_index <= pred_index;
end
else begin
if (is_sticky) begin
act_output <= act_output;
end else begin
act_output <= 0;
end
end
end
end
end
endmodule
|
module tvout (
input pixel_clk,
input rst,
output reg [8:0] cntHS,
output reg [8:0] cntVS,
output wire vbl,
output wire hsync,
output wire out_sync
);
wire screen_sync = (cntHS < 37) ? 1'b0 : 1'b1;
wire in_vbl = ((cntVS >= 5) & (cntVS < 309)) ? 1'b0 : 1'b1;
reg vbl_sync;
reg interlace;
always @ (posedge pixel_clk) begin
if (rst) begin
cntHS <= 0;
cntVS <= 0;
interlace <= 0;
end else begin
if (cntHS == 511) begin
cntHS <= 0;
if ((cntVS == 312) || ((cntVS == 311) && interlace)) begin
cntVS <= 0;
interlace <= ~interlace;
end else cntVS <= cntVS + 1'b1;
end else cntHS <= cntHS + 1'b1;
if (cntVS < 2) begin
if ((cntHS < 240) || ((cntHS >= 256) && (cntHS < 496))) vbl_sync <= 0;
else vbl_sync <= 1;
end else if (cntVS == 2) begin
if ((cntHS < 240) || ((cntHS >= 256) && (cntHS < 272))) vbl_sync <= 0;
else vbl_sync <= 1;
end else if (cntVS == 312) begin
if ((cntHS < 16) || ((cntHS >= 256) && (cntHS < 496))) vbl_sync <= 0;
else vbl_sync <= 1;
end else begin
if ((cntHS < 16) || ((cntHS >= 256) && (cntHS < 272))) vbl_sync <= 0;
else vbl_sync <= 1;
end
end
end
assign vbl = in_vbl;
assign hsync = ~screen_sync;
assign out_sync = in_vbl?vbl_sync:screen_sync;
endmodule
|
module fp_divide_altfp_div_pst_8qe
(
aclr,
clk_en,
clock,
dataa,
datab,
result) ;
input aclr;
input clk_en;
input clock;
input [31:0] dataa;
input [31:0] datab;
output [31:0] result;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
tri1 clk_en;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [8:0] wire_altsyncram3_q_a;
reg a_is_infinity_dffe_0;
reg a_is_infinity_dffe_1;
reg a_is_infinity_dffe_10;
reg a_is_infinity_dffe_11;
reg a_is_infinity_dffe_12;
reg a_is_infinity_dffe_2;
reg a_is_infinity_dffe_3;
reg a_is_infinity_dffe_4;
reg a_is_infinity_dffe_5;
reg a_is_infinity_dffe_6;
reg a_is_infinity_dffe_7;
reg a_is_infinity_dffe_8;
reg a_is_infinity_dffe_9;
reg a_zero_b_not_dffe_0;
reg a_zero_b_not_dffe_1;
reg a_zero_b_not_dffe_10;
reg a_zero_b_not_dffe_11;
reg a_zero_b_not_dffe_12;
reg a_zero_b_not_dffe_2;
reg a_zero_b_not_dffe_3;
reg a_zero_b_not_dffe_4;
reg a_zero_b_not_dffe_5;
reg a_zero_b_not_dffe_6;
reg a_zero_b_not_dffe_7;
reg a_zero_b_not_dffe_8;
reg a_zero_b_not_dffe_9;
reg [33:0] b1_dffe_0;
reg [33:0] b1_dffe_1;
reg b_is_infinity_dffe_0;
reg b_is_infinity_dffe_1;
reg b_is_infinity_dffe_10;
reg b_is_infinity_dffe_11;
reg b_is_infinity_dffe_12;
reg b_is_infinity_dffe_2;
reg b_is_infinity_dffe_3;
reg b_is_infinity_dffe_4;
reg b_is_infinity_dffe_5;
reg b_is_infinity_dffe_6;
reg b_is_infinity_dffe_7;
reg b_is_infinity_dffe_8;
reg b_is_infinity_dffe_9;
reg both_exp_zeros_dffe;
reg divbyzero_pipe_dffe_0;
reg divbyzero_pipe_dffe_1;
reg divbyzero_pipe_dffe_10;
reg divbyzero_pipe_dffe_11;
reg divbyzero_pipe_dffe_12;
reg divbyzero_pipe_dffe_2;
reg divbyzero_pipe_dffe_3;
reg divbyzero_pipe_dffe_4;
reg divbyzero_pipe_dffe_5;
reg divbyzero_pipe_dffe_6;
reg divbyzero_pipe_dffe_7;
reg divbyzero_pipe_dffe_8;
reg divbyzero_pipe_dffe_9;
reg [16:0] e1_dffe_0;
reg [16:0] e1_dffe_1;
reg [16:0] e1_dffe_perf_0;
reg [16:0] e1_dffe_perf_1;
reg [16:0] e1_dffe_perf_2;
reg [16:0] e1_dffe_perf_3;
reg [7:0] exp_result_dffe_0;
reg [7:0] exp_result_dffe_1;
reg [7:0] exp_result_dffe_10;
reg [7:0] exp_result_dffe_11;
reg [7:0] exp_result_dffe_2;
reg [7:0] exp_result_dffe_3;
reg [7:0] exp_result_dffe_4;
reg [7:0] exp_result_dffe_5;
reg [7:0] exp_result_dffe_6;
reg [7:0] exp_result_dffe_7;
reg [7:0] exp_result_dffe_8;
reg [7:0] exp_result_dffe_9;
reg frac_a_smaller_dffe1;
reg [22:0] man_a_dffe1_dffe1;
reg [22:0] man_b_dffe1_dffe1;
reg [22:0] man_result_dffe;
reg nan_pipe_dffe_0;
reg nan_pipe_dffe_1;
reg nan_pipe_dffe_10;
reg nan_pipe_dffe_11;
reg nan_pipe_dffe_12;
reg nan_pipe_dffe_2;
reg nan_pipe_dffe_3;
reg nan_pipe_dffe_4;
reg nan_pipe_dffe_5;
reg nan_pipe_dffe_6;
reg nan_pipe_dffe_7;
reg nan_pipe_dffe_8;
reg nan_pipe_dffe_9;
reg over_under_dffe_0;
reg over_under_dffe_1;
reg over_under_dffe_10;
reg over_under_dffe_2;
reg over_under_dffe_3;
reg over_under_dffe_4;
reg over_under_dffe_5;
reg over_under_dffe_6;
reg over_under_dffe_7;
reg over_under_dffe_8;
reg over_under_dffe_9;
reg [33:0] q_partial_perf_dffe_0;
reg [33:0] q_partial_perf_dffe_1;
reg [16:0] quotient_j_dffe;
reg [16:0] quotient_k_dffe_0;
reg [16:0] quotient_k_dffe_perf_0;
reg [16:0] quotient_k_dffe_perf_1;
reg [16:0] quotient_k_dffe_perf_2;
reg [16:0] quotient_k_dffe_perf_3;
reg [49:0] remainder_j_dffe_0;
reg [49:0] remainder_j_dffe_1;
reg [49:0] remainder_j_dffe_perf_0;
reg [49:0] remainder_j_dffe_perf_1;
reg [49:0] remainder_j_dffe_perf_2;
reg sign_pipe_dffe_0;
reg sign_pipe_dffe_1;
reg sign_pipe_dffe_10;
reg sign_pipe_dffe_11;
reg sign_pipe_dffe_12;
reg sign_pipe_dffe_13;
reg sign_pipe_dffe_2;
reg sign_pipe_dffe_3;
reg sign_pipe_dffe_4;
reg sign_pipe_dffe_5;
reg sign_pipe_dffe_6;
reg sign_pipe_dffe_7;
reg sign_pipe_dffe_8;
reg sign_pipe_dffe_9;
wire wire_bias_addition_overflow;
wire [8:0] wire_bias_addition_result;
wire [8:0] wire_exp_sub_result;
wire [30:0] wire_quotient_process_result;
wire [49:0] wire_remainder_sub_0_result;
wire wire_cmpr2_alb;
wire [34:0] wire_a1_prod_result;
wire [33:0] wire_b1_prod_result;
wire [33:0] wire_q_partial_0_result;
wire [33:0] wire_q_partial_1_result;
wire [50:0] wire_remainder_mult_0_result;
wire [7:0]wire_exp_result_muxa_dataout;
wire [24:0]wire_man_a_adjusteda_dataout;
wire [22:0]wire_man_result_muxa_dataout;
wire [8:0]wire_select_bias_2a_dataout;
wire [8:0]wire_select_biasa_dataout;
wire a_is_infinity_w;
wire a_is_nan_w;
wire a_zero_b_not;
wire [33:0] b1_dffe_w;
wire b_is_infinity_w;
wire b_is_nan_w;
wire bias_addition_overf_w;
wire [7:0] bias_addition_w;
wire both_exp_zeros;
wire [8:0] e0_dffe1_wo;
wire [8:0] e0_w;
wire [50:0] e1_w;
wire [7:0] exp_a_all_one_w;
wire [7:0] exp_a_not_zero_w;
wire [7:0] exp_add_output_all_one;
wire [7:0] exp_add_output_not_zero;
wire [7:0] exp_b_all_one_w;
wire [7:0] exp_b_not_zero_w;
wire [7:0] exp_result_mux_out;
wire exp_result_mux_sel_w;
wire [7:0] exp_result_w;
wire exp_sign_w;
wire [8:0] exp_sub_a_w;
wire [8:0] exp_sub_b_w;
wire [8:0] exp_sub_w;
wire frac_a_smaller_dffe1_wi;
wire frac_a_smaller_dffe1_wo;
wire frac_a_smaller_w;
wire guard_bit;
wire [24:0] man_a_adjusted_w;
wire [22:0] man_a_dffe1_wi;
wire [22:0] man_a_dffe1_wo;
wire [22:0] man_a_not_zero_w;
wire [23:0] man_b_adjusted_w;
wire [22:0] man_b_dffe1_wi;
wire [22:0] man_b_dffe1_wo;
wire [22:0] man_b_not_zero_w;
wire [22:0] man_result_dffe_wi;
wire [22:0] man_result_dffe_wo;
wire man_result_mux_select;
wire [22:0] man_result_w;
wire [22:0] man_zeros_w;
wire [7:0] overflow_ones_w;
wire overflow_underflow;
wire overflow_w;
wire [61:0] quotient_accumulate_w;
wire quotient_process_cin_w;
wire [99:0] remainder_j_w;
wire round_bit;
wire [8:0] select_bias_out_2_w;
wire [8:0] select_bias_out_w;
wire [4:0] sticky_bits;
wire underflow_w;
wire [7:0] underflow_zeros_w;
wire [8:0] value_add_one_w;
wire [8:0] value_normal_w;
wire [8:0] value_zero_w;
altsyncram altsyncram3
(
.address_a(datab[22:14]),
.clock0(clock),
.clocken0(clk_en),
.eccstatus(),
.q_a(wire_altsyncram3_q_a),
.q_b()
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr0(1'b0),
.aclr1(1'b0),
.address_b({1{1'b1}}),
.addressstall_a(1'b0),
.addressstall_b(1'b0),
.byteena_a({1{1'b1}}),
.byteena_b({1{1'b1}}),
.clock1(1'b1),
.clocken1(1'b1),
.clocken2(1'b1),
.clocken3(1'b1),
.data_a({9{1'b1}}),
.data_b({1{1'b1}}),
.rden_a(1'b1),
.rden_b(1'b1),
.wren_a(1'b0),
.wren_b(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
altsyncram3.init_file = "fp_divide.hex",
altsyncram3.operation_mode = "ROM",
altsyncram3.width_a = 9,
altsyncram3.widthad_a = 9,
altsyncram3.intended_device_family = "Cyclone V",
altsyncram3.lpm_type = "altsyncram";
// synopsys translate_off
initial
a_is_infinity_dffe_0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) a_is_infinity_dffe_0 <= 1'b0;
else if (clk_en == 1'b1) a_is_infinity_dffe_0 <= a_is_infinity_w;
// synopsys translate_off
initial
a_is_infinity_dffe_1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) a_is_infinity_dffe_1 <= 1'b0;
else if (clk_en == 1'b1) a_is_infinity_dffe_1 <= a_is_infinity_dffe_0;
// synopsys translate_off
initial
a_is_infinity_dffe_10 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) a_is_infinity_dffe_10 <= 1'b0;
else if (clk_en == 1'b1) a_is_infinity_dffe_10 <= a_is_infinity_dffe_9;
// synopsys translate_off
initial
a_is_infinity_dffe_11 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) a_is_infinity_dffe_11 <= 1'b0;
else if (clk_en == 1'b1) a_is_infinity_dffe_11 <= a_is_infinity_dffe_10;
// synopsys translate_off
initial
a_is_infinity_dffe_12 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) a_is_infinity_dffe_12 <= 1'b0;
else if (clk_en == 1'b1) a_is_infinity_dffe_12 <= a_is_infinity_dffe_11;
// synopsys translate_off
initial
a_is_infinity_dffe_2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) a_is_infinity_dffe_2 <= 1'b0;
else if (clk_en == 1'b1) a_is_infinity_dffe_2 <= a_is_infinity_dffe_1;
// synopsys translate_off
initial
a_is_infinity_dffe_3 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) a_is_infinity_dffe_3 <= 1'b0;
else if (clk_en == 1'b1) a_is_infinity_dffe_3 <= a_is_infinity_dffe_2;
// synopsys translate_off
initial
a_is_infinity_dffe_4 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) a_is_infinity_dffe_4 <= 1'b0;
else if (clk_en == 1'b1) a_is_infinity_dffe_4 <= a_is_infinity_dffe_3;
// synopsys translate_off
initial
a_is_infinity_dffe_5 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) a_is_infinity_dffe_5 <= 1'b0;
else if (clk_en == 1'b1) a_is_infinity_dffe_5 <= a_is_infinity_dffe_4;
// synopsys translate_off
initial
a_is_infinity_dffe_6 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) a_is_infinity_dffe_6 <= 1'b0;
else if (clk_en == 1'b1) a_is_infinity_dffe_6 <= a_is_infinity_dffe_5;
// synopsys translate_off
initial
a_is_infinity_dffe_7 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) a_is_infinity_dffe_7 <= 1'b0;
else if (clk_en == 1'b1) a_is_infinity_dffe_7 <= a_is_infinity_dffe_6;
// synopsys translate_off
initial
a_is_infinity_dffe_8 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) a_is_infinity_dffe_8 <= 1'b0;
else if (clk_en == 1'b1) a_is_infinity_dffe_8 <= a_is_infinity_dffe_7;
// synopsys translate_off
initial
a_is_infinity_dffe_9 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) a_is_infinity_dffe_9 <= 1'b0;
else if (clk_en == 1'b1) a_is_infinity_dffe_9 <= a_is_infinity_dffe_8;
// synopsys translate_off
initial
a_zero_b_not_dffe_0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) a_zero_b_not_dffe_0 <= 1'b0;
else if (clk_en == 1'b1) a_zero_b_not_dffe_0 <= a_zero_b_not;
// synopsys translate_off
initial
a_zero_b_not_dffe_1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) a_zero_b_not_dffe_1 <= 1'b0;
else if (clk_en == 1'b1) a_zero_b_not_dffe_1 <= a_zero_b_not_dffe_0;
// synopsys translate_off
initial
a_zero_b_not_dffe_10 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) a_zero_b_not_dffe_10 <= 1'b0;
else if (clk_en == 1'b1) a_zero_b_not_dffe_10 <= a_zero_b_not_dffe_9;
// synopsys translate_off
initial
a_zero_b_not_dffe_11 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) a_zero_b_not_dffe_11 <= 1'b0;
else if (clk_en == 1'b1) a_zero_b_not_dffe_11 <= a_zero_b_not_dffe_10;
// synopsys translate_off
initial
a_zero_b_not_dffe_12 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) a_zero_b_not_dffe_12 <= 1'b0;
else if (clk_en == 1'b1) a_zero_b_not_dffe_12 <= a_zero_b_not_dffe_11;
// synopsys translate_off
initial
a_zero_b_not_dffe_2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) a_zero_b_not_dffe_2 <= 1'b0;
else if (clk_en == 1'b1) a_zero_b_not_dffe_2 <= a_zero_b_not_dffe_1;
// synopsys translate_off
initial
a_zero_b_not_dffe_3 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) a_zero_b_not_dffe_3 <= 1'b0;
else if (clk_en == 1'b1) a_zero_b_not_dffe_3 <= a_zero_b_not_dffe_2;
// synopsys translate_off
initial
a_zero_b_not_dffe_4 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) a_zero_b_not_dffe_4 <= 1'b0;
else if (clk_en == 1'b1) a_zero_b_not_dffe_4 <= a_zero_b_not_dffe_3;
// synopsys translate_off
initial
a_zero_b_not_dffe_5 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) a_zero_b_not_dffe_5 <= 1'b0;
else if (clk_en == 1'b1) a_zero_b_not_dffe_5 <= a_zero_b_not_dffe_4;
// synopsys translate_off
initial
a_zero_b_not_dffe_6 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) a_zero_b_not_dffe_6 <= 1'b0;
else if (clk_en == 1'b1) a_zero_b_not_dffe_6 <= a_zero_b_not_dffe_5;
// synopsys translate_off
initial
a_zero_b_not_dffe_7 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) a_zero_b_not_dffe_7 <= 1'b0;
else if (clk_en == 1'b1) a_zero_b_not_dffe_7 <= a_zero_b_not_dffe_6;
// synopsys translate_off
initial
a_zero_b_not_dffe_8 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) a_zero_b_not_dffe_8 <= 1'b0;
else if (clk_en == 1'b1) a_zero_b_not_dffe_8 <= a_zero_b_not_dffe_7;
// synopsys translate_off
initial
a_zero_b_not_dffe_9 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) a_zero_b_not_dffe_9 <= 1'b0;
else if (clk_en == 1'b1) a_zero_b_not_dffe_9 <= a_zero_b_not_dffe_8;
// synopsys translate_off
initial
b1_dffe_0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) b1_dffe_0 <= 34'b0;
else if (clk_en == 1'b1) b1_dffe_0 <= wire_b1_prod_result;
// synopsys translate_off
initial
b1_dffe_1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) b1_dffe_1 <= 34'b0;
else if (clk_en == 1'b1) b1_dffe_1 <= b1_dffe_0;
// synopsys translate_off
initial
b_is_infinity_dffe_0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) b_is_infinity_dffe_0 <= 1'b0;
else if (clk_en == 1'b1) b_is_infinity_dffe_0 <= b_is_infinity_w;
// synopsys translate_off
initial
b_is_infinity_dffe_1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) b_is_infinity_dffe_1 <= 1'b0;
else if (clk_en == 1'b1) b_is_infinity_dffe_1 <= b_is_infinity_dffe_0;
// synopsys translate_off
initial
b_is_infinity_dffe_10 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) b_is_infinity_dffe_10 <= 1'b0;
else if (clk_en == 1'b1) b_is_infinity_dffe_10 <= b_is_infinity_dffe_9;
// synopsys translate_off
initial
b_is_infinity_dffe_11 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) b_is_infinity_dffe_11 <= 1'b0;
else if (clk_en == 1'b1) b_is_infinity_dffe_11 <= b_is_infinity_dffe_10;
// synopsys translate_off
initial
b_is_infinity_dffe_12 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) b_is_infinity_dffe_12 <= 1'b0;
else if (clk_en == 1'b1) b_is_infinity_dffe_12 <= b_is_infinity_dffe_11;
// synopsys translate_off
initial
b_is_infinity_dffe_2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) b_is_infinity_dffe_2 <= 1'b0;
else if (clk_en == 1'b1) b_is_infinity_dffe_2 <= b_is_infinity_dffe_1;
// synopsys translate_off
initial
b_is_infinity_dffe_3 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) b_is_infinity_dffe_3 <= 1'b0;
else if (clk_en == 1'b1) b_is_infinity_dffe_3 <= b_is_infinity_dffe_2;
// synopsys translate_off
initial
b_is_infinity_dffe_4 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) b_is_infinity_dffe_4 <= 1'b0;
else if (clk_en == 1'b1) b_is_infinity_dffe_4 <= b_is_infinity_dffe_3;
// synopsys translate_off
initial
b_is_infinity_dffe_5 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) b_is_infinity_dffe_5 <= 1'b0;
else if (clk_en == 1'b1) b_is_infinity_dffe_5 <= b_is_infinity_dffe_4;
// synopsys translate_off
initial
b_is_infinity_dffe_6 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) b_is_infinity_dffe_6 <= 1'b0;
else if (clk_en == 1'b1) b_is_infinity_dffe_6 <= b_is_infinity_dffe_5;
// synopsys translate_off
initial
b_is_infinity_dffe_7 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) b_is_infinity_dffe_7 <= 1'b0;
else if (clk_en == 1'b1) b_is_infinity_dffe_7 <= b_is_infinity_dffe_6;
// synopsys translate_off
initial
b_is_infinity_dffe_8 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) b_is_infinity_dffe_8 <= 1'b0;
else if (clk_en == 1'b1) b_is_infinity_dffe_8 <= b_is_infinity_dffe_7;
// synopsys translate_off
initial
b_is_infinity_dffe_9 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) b_is_infinity_dffe_9 <= 1'b0;
else if (clk_en == 1'b1) b_is_infinity_dffe_9 <= b_is_infinity_dffe_8;
// synopsys translate_off
initial
both_exp_zeros_dffe = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) both_exp_zeros_dffe <= 1'b0;
else if (clk_en == 1'b1) both_exp_zeros_dffe <= ((~ exp_b_not_zero_w[7]) & (~ exp_a_not_zero_w[7]));
// synopsys translate_off
initial
divbyzero_pipe_dffe_0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) divbyzero_pipe_dffe_0 <= 1'b0;
else if (clk_en == 1'b1) divbyzero_pipe_dffe_0 <= ((((~ exp_b_not_zero_w[7]) & (~ a_is_nan_w)) & exp_a_not_zero_w[7]) & (~ a_is_infinity_w));
// synopsys translate_off
initial
divbyzero_pipe_dffe_1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) divbyzero_pipe_dffe_1 <= 1'b0;
else if (clk_en == 1'b1) divbyzero_pipe_dffe_1 <= divbyzero_pipe_dffe_0;
// synopsys translate_off
initial
divbyzero_pipe_dffe_10 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) divbyzero_pipe_dffe_10 <= 1'b0;
else if (clk_en == 1'b1) divbyzero_pipe_dffe_10 <= divbyzero_pipe_dffe_9;
// synopsys translate_off
initial
divbyzero_pipe_dffe_11 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) divbyzero_pipe_dffe_11 <= 1'b0;
else if (clk_en == 1'b1) divbyzero_pipe_dffe_11 <= divbyzero_pipe_dffe_10;
// synopsys translate_off
initial
divbyzero_pipe_dffe_12 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) divbyzero_pipe_dffe_12 <= 1'b0;
else if (clk_en == 1'b1) divbyzero_pipe_dffe_12 <= divbyzero_pipe_dffe_11;
// synopsys translate_off
initial
divbyzero_pipe_dffe_2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) divbyzero_pipe_dffe_2 <= 1'b0;
else if (clk_en == 1'b1) divbyzero_pipe_dffe_2 <= divbyzero_pipe_dffe_1;
// synopsys translate_off
initial
divbyzero_pipe_dffe_3 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) divbyzero_pipe_dffe_3 <= 1'b0;
else if (clk_en == 1'b1) divbyzero_pipe_dffe_3 <= divbyzero_pipe_dffe_2;
// synopsys translate_off
initial
divbyzero_pipe_dffe_4 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) divbyzero_pipe_dffe_4 <= 1'b0;
else if (clk_en == 1'b1) divbyzero_pipe_dffe_4 <= divbyzero_pipe_dffe_3;
// synopsys translate_off
initial
divbyzero_pipe_dffe_5 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) divbyzero_pipe_dffe_5 <= 1'b0;
else if (clk_en == 1'b1) divbyzero_pipe_dffe_5 <= divbyzero_pipe_dffe_4;
// synopsys translate_off
initial
divbyzero_pipe_dffe_6 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) divbyzero_pipe_dffe_6 <= 1'b0;
else if (clk_en == 1'b1) divbyzero_pipe_dffe_6 <= divbyzero_pipe_dffe_5;
// synopsys translate_off
initial
divbyzero_pipe_dffe_7 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) divbyzero_pipe_dffe_7 <= 1'b0;
else if (clk_en == 1'b1) divbyzero_pipe_dffe_7 <= divbyzero_pipe_dffe_6;
// synopsys translate_off
initial
divbyzero_pipe_dffe_8 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) divbyzero_pipe_dffe_8 <= 1'b0;
else if (clk_en == 1'b1) divbyzero_pipe_dffe_8 <= divbyzero_pipe_dffe_7;
// synopsys translate_off
initial
divbyzero_pipe_dffe_9 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) divbyzero_pipe_dffe_9 <= 1'b0;
else if (clk_en == 1'b1) divbyzero_pipe_dffe_9 <= divbyzero_pipe_dffe_8;
// synopsys translate_off
initial
e1_dffe_0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) e1_dffe_0 <= 17'b0;
else if (clk_en == 1'b1) e1_dffe_0 <= e1_w[16:0];
// synopsys translate_off
initial
e1_dffe_1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) e1_dffe_1 <= 17'b0;
else if (clk_en == 1'b1) e1_dffe_1 <= e1_w[33:17];
// synopsys translate_off
initial
e1_dffe_perf_0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) e1_dffe_perf_0 <= 17'b0;
else if (clk_en == 1'b1) e1_dffe_perf_0 <= e1_dffe_0;
// synopsys translate_off
initial
e1_dffe_perf_1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) e1_dffe_perf_1 <= 17'b0;
else if (clk_en == 1'b1) e1_dffe_perf_1 <= e1_dffe_perf_0;
// synopsys translate_off
initial
e1_dffe_perf_2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) e1_dffe_perf_2 <= 17'b0;
else if (clk_en == 1'b1) e1_dffe_perf_2 <= e1_dffe_perf_1;
// synopsys translate_off
initial
e1_dffe_perf_3 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) e1_dffe_perf_3 <= 17'b0;
else if (clk_en == 1'b1) e1_dffe_perf_3 <= e1_dffe_perf_2;
// synopsys translate_off
initial
exp_result_dffe_0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exp_result_dffe_0 <= 8'b0;
else if (clk_en == 1'b1) exp_result_dffe_0 <= exp_result_mux_out;
// synopsys translate_off
initial
exp_result_dffe_1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exp_result_dffe_1 <= 8'b0;
else if (clk_en == 1'b1) exp_result_dffe_1 <= exp_result_dffe_0;
// synopsys translate_off
initial
exp_result_dffe_10 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exp_result_dffe_10 <= 8'b0;
else if (clk_en == 1'b1) exp_result_dffe_10 <= exp_result_dffe_9;
// synopsys translate_off
initial
exp_result_dffe_11 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exp_result_dffe_11 <= 8'b0;
else if (clk_en == 1'b1) exp_result_dffe_11 <= exp_result_dffe_10;
// synopsys translate_off
initial
exp_result_dffe_2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exp_result_dffe_2 <= 8'b0;
else if (clk_en == 1'b1) exp_result_dffe_2 <= exp_result_dffe_1;
// synopsys translate_off
initial
exp_result_dffe_3 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exp_result_dffe_3 <= 8'b0;
else if (clk_en == 1'b1) exp_result_dffe_3 <= exp_result_dffe_2;
// synopsys translate_off
initial
exp_result_dffe_4 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exp_result_dffe_4 <= 8'b0;
else if (clk_en == 1'b1) exp_result_dffe_4 <= exp_result_dffe_3;
// synopsys translate_off
initial
exp_result_dffe_5 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exp_result_dffe_5 <= 8'b0;
else if (clk_en == 1'b1) exp_result_dffe_5 <= exp_result_dffe_4;
// synopsys translate_off
initial
exp_result_dffe_6 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exp_result_dffe_6 <= 8'b0;
else if (clk_en == 1'b1) exp_result_dffe_6 <= exp_result_dffe_5;
// synopsys translate_off
initial
exp_result_dffe_7 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exp_result_dffe_7 <= 8'b0;
else if (clk_en == 1'b1) exp_result_dffe_7 <= exp_result_dffe_6;
// synopsys translate_off
initial
exp_result_dffe_8 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exp_result_dffe_8 <= 8'b0;
else if (clk_en == 1'b1) exp_result_dffe_8 <= exp_result_dffe_7;
// synopsys translate_off
initial
exp_result_dffe_9 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exp_result_dffe_9 <= 8'b0;
else if (clk_en == 1'b1) exp_result_dffe_9 <= exp_result_dffe_8;
// synopsys translate_off
initial
frac_a_smaller_dffe1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) frac_a_smaller_dffe1 <= 1'b0;
else if (clk_en == 1'b1) frac_a_smaller_dffe1 <= frac_a_smaller_dffe1_wi;
// synopsys translate_off
initial
man_a_dffe1_dffe1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) man_a_dffe1_dffe1 <= 23'b0;
else if (clk_en == 1'b1) man_a_dffe1_dffe1 <= man_a_dffe1_wi;
// synopsys translate_off
initial
man_b_dffe1_dffe1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) man_b_dffe1_dffe1 <= 23'b0;
else if (clk_en == 1'b1) man_b_dffe1_dffe1 <= man_b_dffe1_wi;
// synopsys translate_off
initial
man_result_dffe = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) man_result_dffe <= 23'b0;
else if (clk_en == 1'b1) man_result_dffe <= man_result_dffe_wi;
// synopsys translate_off
initial
nan_pipe_dffe_0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) nan_pipe_dffe_0 <= 1'b0;
else if (clk_en == 1'b1) nan_pipe_dffe_0 <= (((a_is_nan_w | b_is_nan_w) | (a_is_infinity_w & b_is_infinity_w)) | ((~ exp_a_not_zero_w[7]) & (~ exp_b_not_zero_w[7])));
// synopsys translate_off
initial
nan_pipe_dffe_1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) nan_pipe_dffe_1 <= 1'b0;
else if (clk_en == 1'b1) nan_pipe_dffe_1 <= nan_pipe_dffe_0;
// synopsys translate_off
initial
nan_pipe_dffe_10 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) nan_pipe_dffe_10 <= 1'b0;
else if (clk_en == 1'b1) nan_pipe_dffe_10 <= nan_pipe_dffe_9;
// synopsys translate_off
initial
nan_pipe_dffe_11 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) nan_pipe_dffe_11 <= 1'b0;
else if (clk_en == 1'b1) nan_pipe_dffe_11 <= nan_pipe_dffe_10;
// synopsys translate_off
initial
nan_pipe_dffe_12 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) nan_pipe_dffe_12 <= 1'b0;
else if (clk_en == 1'b1) nan_pipe_dffe_12 <= nan_pipe_dffe_11;
// synopsys translate_off
initial
nan_pipe_dffe_2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) nan_pipe_dffe_2 <= 1'b0;
else if (clk_en == 1'b1) nan_pipe_dffe_2 <= nan_pipe_dffe_1;
// synopsys translate_off
initial
nan_pipe_dffe_3 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) nan_pipe_dffe_3 <= 1'b0;
else if (clk_en == 1'b1) nan_pipe_dffe_3 <= nan_pipe_dffe_2;
// synopsys translate_off
initial
nan_pipe_dffe_4 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) nan_pipe_dffe_4 <= 1'b0;
else if (clk_en == 1'b1) nan_pipe_dffe_4 <= nan_pipe_dffe_3;
// synopsys translate_off
initial
nan_pipe_dffe_5 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) nan_pipe_dffe_5 <= 1'b0;
else if (clk_en == 1'b1) nan_pipe_dffe_5 <= nan_pipe_dffe_4;
// synopsys translate_off
initial
nan_pipe_dffe_6 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) nan_pipe_dffe_6 <= 1'b0;
else if (clk_en == 1'b1) nan_pipe_dffe_6 <= nan_pipe_dffe_5;
// synopsys translate_off
initial
nan_pipe_dffe_7 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) nan_pipe_dffe_7 <= 1'b0;
else if (clk_en == 1'b1) nan_pipe_dffe_7 <= nan_pipe_dffe_6;
// synopsys translate_off
initial
nan_pipe_dffe_8 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) nan_pipe_dffe_8 <= 1'b0;
else if (clk_en == 1'b1) nan_pipe_dffe_8 <= nan_pipe_dffe_7;
// synopsys translate_off
initial
nan_pipe_dffe_9 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) nan_pipe_dffe_9 <= 1'b0;
else if (clk_en == 1'b1) nan_pipe_dffe_9 <= nan_pipe_dffe_8;
// synopsys translate_off
initial
over_under_dffe_0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) over_under_dffe_0 <= 1'b0;
else if (clk_en == 1'b1) over_under_dffe_0 <= overflow_underflow;
// synopsys translate_off
initial
over_under_dffe_1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) over_under_dffe_1 <= 1'b0;
else if (clk_en == 1'b1) over_under_dffe_1 <= over_under_dffe_0;
// synopsys translate_off
initial
over_under_dffe_10 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) over_under_dffe_10 <= 1'b0;
else if (clk_en == 1'b1) over_under_dffe_10 <= over_under_dffe_9;
// synopsys translate_off
initial
over_under_dffe_2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) over_under_dffe_2 <= 1'b0;
else if (clk_en == 1'b1) over_under_dffe_2 <= over_under_dffe_1;
// synopsys translate_off
initial
over_under_dffe_3 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) over_under_dffe_3 <= 1'b0;
else if (clk_en == 1'b1) over_under_dffe_3 <= over_under_dffe_2;
// synopsys translate_off
initial
over_under_dffe_4 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) over_under_dffe_4 <= 1'b0;
else if (clk_en == 1'b1) over_under_dffe_4 <= over_under_dffe_3;
// synopsys translate_off
initial
over_under_dffe_5 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) over_under_dffe_5 <= 1'b0;
else if (clk_en == 1'b1) over_under_dffe_5 <= over_under_dffe_4;
// synopsys translate_off
initial
over_under_dffe_6 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) over_under_dffe_6 <= 1'b0;
else if (clk_en == 1'b1) over_under_dffe_6 <= over_under_dffe_5;
// synopsys translate_off
initial
over_under_dffe_7 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) over_under_dffe_7 <= 1'b0;
else if (clk_en == 1'b1) over_under_dffe_7 <= over_under_dffe_6;
// synopsys translate_off
initial
over_under_dffe_8 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) over_under_dffe_8 <= 1'b0;
else if (clk_en == 1'b1) over_under_dffe_8 <= over_under_dffe_7;
// synopsys translate_off
initial
over_under_dffe_9 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) over_under_dffe_9 <= 1'b0;
else if (clk_en == 1'b1) over_under_dffe_9 <= over_under_dffe_8;
// synopsys translate_off
initial
q_partial_perf_dffe_0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) q_partial_perf_dffe_0 <= 34'b0;
else if (clk_en == 1'b1) q_partial_perf_dffe_0 <= wire_q_partial_0_result;
// synopsys translate_off
initial
q_partial_perf_dffe_1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) q_partial_perf_dffe_1 <= 34'b0;
else if (clk_en == 1'b1) q_partial_perf_dffe_1 <= wire_q_partial_1_result;
// synopsys translate_off
initial
quotient_j_dffe = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) quotient_j_dffe <= 17'b0;
else if (clk_en == 1'b1) quotient_j_dffe <= q_partial_perf_dffe_0[32:16];
// synopsys translate_off
initial
quotient_k_dffe_0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) quotient_k_dffe_0 <= 17'b0;
else if (clk_en == 1'b1) quotient_k_dffe_0 <= quotient_k_dffe_perf_3;
// synopsys translate_off
initial
quotient_k_dffe_perf_0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) quotient_k_dffe_perf_0 <= 17'b0;
else if (clk_en == 1'b1) quotient_k_dffe_perf_0 <= quotient_accumulate_w[30:14];
// synopsys translate_off
initial
quotient_k_dffe_perf_1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) quotient_k_dffe_perf_1 <= 17'b0;
else if (clk_en == 1'b1) quotient_k_dffe_perf_1 <= quotient_k_dffe_perf_0;
// synopsys translate_off
initial
quotient_k_dffe_perf_2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) quotient_k_dffe_perf_2 <= 17'b0;
else if (clk_en == 1'b1) quotient_k_dffe_perf_2 <= quotient_k_dffe_perf_1;
// synopsys translate_off
initial
quotient_k_dffe_perf_3 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) quotient_k_dffe_perf_3 <= 17'b0;
else if (clk_en == 1'b1) quotient_k_dffe_perf_3 <= quotient_k_dffe_perf_2;
// synopsys translate_off
initial
remainder_j_dffe_0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) remainder_j_dffe_0 <= 50'b0;
else if (clk_en == 1'b1) remainder_j_dffe_0 <= remainder_j_w[49:0];
// synopsys translate_off
initial
remainder_j_dffe_1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) remainder_j_dffe_1 <= 50'b0;
else if (clk_en == 1'b1) remainder_j_dffe_1 <= remainder_j_dffe_perf_2;
// synopsys translate_off
initial
remainder_j_dffe_perf_0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) remainder_j_dffe_perf_0 <= 50'b0;
else if (clk_en == 1'b1) remainder_j_dffe_perf_0 <= remainder_j_dffe_0;
// synopsys translate_off
initial
remainder_j_dffe_perf_1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) remainder_j_dffe_perf_1 <= 50'b0;
else if (clk_en == 1'b1) remainder_j_dffe_perf_1 <= remainder_j_dffe_perf_0;
// synopsys translate_off
initial
remainder_j_dffe_perf_2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) remainder_j_dffe_perf_2 <= 50'b0;
else if (clk_en == 1'b1) remainder_j_dffe_perf_2 <= remainder_j_dffe_perf_1;
// synopsys translate_off
initial
sign_pipe_dffe_0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_pipe_dffe_0 <= 1'b0;
else if (clk_en == 1'b1) sign_pipe_dffe_0 <= (dataa[31] ^ datab[31]);
// synopsys translate_off
initial
sign_pipe_dffe_1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_pipe_dffe_1 <= 1'b0;
else if (clk_en == 1'b1) sign_pipe_dffe_1 <= sign_pipe_dffe_0;
// synopsys translate_off
initial
sign_pipe_dffe_10 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_pipe_dffe_10 <= 1'b0;
else if (clk_en == 1'b1) sign_pipe_dffe_10 <= sign_pipe_dffe_9;
// synopsys translate_off
initial
sign_pipe_dffe_11 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_pipe_dffe_11 <= 1'b0;
else if (clk_en == 1'b1) sign_pipe_dffe_11 <= sign_pipe_dffe_10;
// synopsys translate_off
initial
sign_pipe_dffe_12 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_pipe_dffe_12 <= 1'b0;
else if (clk_en == 1'b1) sign_pipe_dffe_12 <= sign_pipe_dffe_11;
// synopsys translate_off
initial
sign_pipe_dffe_13 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_pipe_dffe_13 <= 1'b0;
else if (clk_en == 1'b1) sign_pipe_dffe_13 <= sign_pipe_dffe_12;
// synopsys translate_off
initial
sign_pipe_dffe_2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_pipe_dffe_2 <= 1'b0;
else if (clk_en == 1'b1) sign_pipe_dffe_2 <= sign_pipe_dffe_1;
// synopsys translate_off
initial
sign_pipe_dffe_3 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_pipe_dffe_3 <= 1'b0;
else if (clk_en == 1'b1) sign_pipe_dffe_3 <= sign_pipe_dffe_2;
// synopsys translate_off
initial
sign_pipe_dffe_4 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_pipe_dffe_4 <= 1'b0;
else if (clk_en == 1'b1) sign_pipe_dffe_4 <= sign_pipe_dffe_3;
// synopsys translate_off
initial
sign_pipe_dffe_5 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_pipe_dffe_5 <= 1'b0;
else if (clk_en == 1'b1) sign_pipe_dffe_5 <= sign_pipe_dffe_4;
// synopsys translate_off
initial
sign_pipe_dffe_6 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_pipe_dffe_6 <= 1'b0;
else if (clk_en == 1'b1) sign_pipe_dffe_6 <= sign_pipe_dffe_5;
// synopsys translate_off
initial
sign_pipe_dffe_7 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_pipe_dffe_7 <= 1'b0;
else if (clk_en == 1'b1) sign_pipe_dffe_7 <= sign_pipe_dffe_6;
// synopsys translate_off
initial
sign_pipe_dffe_8 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_pipe_dffe_8 <= 1'b0;
else if (clk_en == 1'b1) sign_pipe_dffe_8 <= sign_pipe_dffe_7;
// synopsys translate_off
initial
sign_pipe_dffe_9 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_pipe_dffe_9 <= 1'b0;
else if (clk_en == 1'b1) sign_pipe_dffe_9 <= sign_pipe_dffe_8;
lpm_add_sub bias_addition
(
.aclr(aclr),
.clken(clk_en),
.clock(clock),
.cout(),
.dataa(exp_sub_w),
.datab(select_bias_out_2_w),
.overflow(wire_bias_addition_overflow),
.result(wire_bias_addition_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.add_sub(1'b1),
.cin()
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
bias_addition.lpm_direction = "ADD",
bias_addition.lpm_pipeline = 1,
bias_addition.lpm_representation = "SIGNED",
bias_addition.lpm_width = 9,
bias_addition.lpm_type = "lpm_add_sub";
lpm_add_sub exp_sub
(
.aclr(aclr),
.clken(clk_en),
.clock(clock),
.cout(),
.dataa(exp_sub_a_w),
.datab(exp_sub_b_w),
.overflow(),
.result(wire_exp_sub_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.add_sub(1'b1),
.cin()
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
exp_sub.lpm_direction = "SUB",
exp_sub.lpm_pipeline = 1,
exp_sub.lpm_representation = "SIGNED",
exp_sub.lpm_width = 9,
exp_sub.lpm_type = "lpm_add_sub";
lpm_add_sub quotient_process
(
.aclr(aclr),
.cin(quotient_process_cin_w),
.clken(clk_en),
.clock(clock),
.cout(),
.dataa({quotient_accumulate_w[61:45], {14{1'b0}}}),
.datab({{14{1'b0}}, q_partial_perf_dffe_1[32:22], {6{1'b1}}}),
.overflow(),
.result(wire_quotient_process_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.add_sub(1'b1)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
quotient_process.lpm_direction = "ADD",
quotient_process.lpm_pipeline = 1,
quotient_process.lpm_representation = "UNSIGNED",
quotient_process.lpm_width = 31,
quotient_process.lpm_type = "lpm_add_sub";
lpm_add_sub remainder_sub_0
(
.aclr(aclr),
.clken(clk_en),
.clock(clock),
.cout(),
.dataa({remainder_j_dffe_1[49:15], {15{1'b0}}}),
.datab(wire_remainder_mult_0_result[49:0]),
.overflow(),
.result(wire_remainder_sub_0_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.add_sub(1'b1),
.cin()
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
remainder_sub_0.lpm_direction = "SUB",
remainder_sub_0.lpm_pipeline = 1,
remainder_sub_0.lpm_representation = "UNSIGNED",
remainder_sub_0.lpm_width = 50,
remainder_sub_0.lpm_type = "lpm_add_sub";
lpm_compare cmpr2
(
.aeb(),
.agb(),
.ageb(),
.alb(wire_cmpr2_alb),
.aleb(),
.aneb(),
.dataa(dataa[22:0]),
.datab(datab[22:0])
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
cmpr2.lpm_representation = "UNSIGNED",
cmpr2.lpm_width = 23,
cmpr2.lpm_type = "lpm_compare";
lpm_mult a1_prod
(
.aclr(aclr),
.clken(clk_en),
.clock(clock),
.dataa(man_a_adjusted_w),
.datab({1'b1, e0_dffe1_wo}),
.result(wire_a1_prod_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.sum({1{1'b0}})
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
a1_prod.lpm_pipeline = 3,
a1_prod.lpm_representation = "UNSIGNED",
a1_prod.lpm_widtha = 25,
a1_prod.lpm_widthb = 10,
a1_prod.lpm_widthp = 35,
a1_prod.lpm_type = "lpm_mult",
a1_prod.lpm_hint = "DEDICATED_MULTIPLIER_CIRCUITRY=YES";
lpm_mult b1_prod
(
.aclr(aclr),
.clken(clk_en),
.clock(clock),
.dataa(man_b_adjusted_w),
.datab({1'b1, e0_dffe1_wo}),
.result(wire_b1_prod_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.sum({1{1'b0}})
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
b1_prod.lpm_pipeline = 3,
b1_prod.lpm_representation = "UNSIGNED",
b1_prod.lpm_widtha = 24,
b1_prod.lpm_widthb = 10,
b1_prod.lpm_widthp = 34,
b1_prod.lpm_type = "lpm_mult",
b1_prod.lpm_hint = "DEDICATED_MULTIPLIER_CIRCUITRY=YES";
lpm_mult q_partial_0
(
.aclr(aclr),
.clken(clk_en),
.clock(clock),
.dataa(remainder_j_w[49:33]),
.datab(e1_w[16:0]),
.result(wire_q_partial_0_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.sum({1{1'b0}})
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
q_partial_0.lpm_pipeline = 1,
q_partial_0.lpm_representation = "UNSIGNED",
q_partial_0.lpm_widtha = 17,
q_partial_0.lpm_widthb = 17,
q_partial_0.lpm_widthp = 34,
q_partial_0.lpm_type = "lpm_mult",
q_partial_0.lpm_hint = "DEDICATED_MULTIPLIER_CIRCUITRY=YES";
lpm_mult q_partial_1
(
.aclr(aclr),
.clken(clk_en),
.clock(clock),
.dataa(remainder_j_w[99:83]),
.datab(e1_w[50:34]),
.result(wire_q_partial_1_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.sum({1{1'b0}})
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
q_partial_1.lpm_pipeline = 1,
q_partial_1.lpm_representation = "UNSIGNED",
q_partial_1.lpm_widtha = 17,
q_partial_1.lpm_widthb = 17,
q_partial_1.lpm_widthp = 34,
q_partial_1.lpm_type = "lpm_mult",
q_partial_1.lpm_hint = "DEDICATED_MULTIPLIER_CIRCUITRY=YES";
lpm_mult remainder_mult_0
(
.aclr(aclr),
.clken(clk_en),
.clock(clock),
.dataa(b1_dffe_w[33:0]),
.datab(q_partial_perf_dffe_0[32:16]),
.result(wire_remainder_mult_0_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.sum({1{1'b0}})
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
remainder_mult_0.lpm_pipeline = 3,
remainder_mult_0.lpm_representation = "UNSIGNED",
remainder_mult_0.lpm_widtha = 34,
remainder_mult_0.lpm_widthb = 17,
remainder_mult_0.lpm_widthp = 51,
remainder_mult_0.lpm_type = "lpm_mult",
remainder_mult_0.lpm_hint = "DEDICATED_MULTIPLIER_CIRCUITRY=YES";
assign wire_exp_result_muxa_dataout = (exp_result_mux_sel_w === 1'b1) ? underflow_zeros_w : exp_result_w;
assign wire_man_a_adjusteda_dataout = (frac_a_smaller_dffe1_wo === 1'b1) ? {1'b1, man_a_dffe1_wo, 1'b0} : {1'b0, 1'b1, man_a_dffe1_wo};
assign wire_man_result_muxa_dataout = (man_result_mux_select === 1'b1) ? {nan_pipe_dffe_12, man_zeros_w[21:0]} : wire_quotient_process_result[28:6];
assign wire_select_bias_2a_dataout = (both_exp_zeros === 1'b1) ? value_zero_w : select_bias_out_w;
assign wire_select_biasa_dataout = (frac_a_smaller_dffe1_wo === 1'b1) ? value_normal_w : value_add_one_w;
assign
a_is_infinity_w = (exp_a_all_one_w[7] & (~ man_a_not_zero_w[22])),
a_is_nan_w = (exp_a_all_one_w[7] & man_a_not_zero_w[22]),
a_zero_b_not = (exp_b_not_zero_w[7] & (~ exp_a_not_zero_w[7])),
b1_dffe_w = {b1_dffe_1},
b_is_infinity_w = (exp_b_all_one_w[7] & (~ man_b_not_zero_w[22])),
b_is_nan_w = (exp_b_all_one_w[7] & man_b_not_zero_w[22]),
bias_addition_overf_w = wire_bias_addition_overflow,
bias_addition_w = wire_bias_addition_result[7:0],
both_exp_zeros = both_exp_zeros_dffe,
e0_dffe1_wo = e0_w,
e0_w = wire_altsyncram3_q_a,
e1_w = {e1_dffe_1, e1_dffe_perf_3, (~ wire_b1_prod_result[33:17])},
exp_a_all_one_w = {(dataa[30] & exp_a_all_one_w[6]), (dataa[29] & exp_a_all_one_w[5]), (dataa[28] & exp_a_all_one_w[4]), (dataa[27] & exp_a_all_one_w[3]), (dataa[26] & exp_a_all_one_w[2]), (dataa[25] & exp_a_all_one_w[1]), (dataa[24] & exp_a_all_one_w[0]), dataa[23]},
exp_a_not_zero_w = {(dataa[30] | exp_a_not_zero_w[6]), (dataa[29] | exp_a_not_zero_w[5]), (dataa[28] | exp_a_not_zero_w[4]), (dataa[27] | exp_a_not_zero_w[3]), (dataa[26] | exp_a_not_zero_w[2]), (dataa[25] | exp_a_not_zero_w[1]), (dataa[24] | exp_a_not_zero_w[0]), dataa[23]},
exp_add_output_all_one = {(bias_addition_w[7] & exp_add_output_all_one[6]), (bias_addition_w[6] & exp_add_output_all_one[5]), (bias_addition_w[5] & exp_add_output_all_one[4]), (bias_addition_w[4] & exp_add_output_all_one[3]), (bias_addition_w[3] & exp_add_output_all_one[2]), (bias_addition_w[2] & exp_add_output_all_one[1]), (bias_addition_w[1] & exp_add_output_all_one[0]), bias_addition_w[0]},
exp_add_output_not_zero = {(bias_addition_w[7] | exp_add_output_not_zero[6]), (bias_addition_w[6] | exp_add_output_not_zero[5]), (bias_addition_w[5] | exp_add_output_not_zero[4]), (bias_addition_w[4] | exp_add_output_not_zero[3]), (bias_addition_w[3] | exp_add_output_not_zero[2]), (bias_addition_w[2] | exp_add_output_not_zero[1]), (bias_addition_w[1] | exp_add_output_not_zero[0]), bias_addition_w[0]},
exp_b_all_one_w = {(datab[30] & exp_b_all_one_w[6]), (datab[29] & exp_b_all_one_w[5]), (datab[28] & exp_b_all_one_w[4]), (datab[27] & exp_b_all_one_w[3]), (datab[26] & exp_b_all_one_w[2]), (datab[25] & exp_b_all_one_w[1]), (datab[24] & exp_b_all_one_w[0]), datab[23]},
exp_b_not_zero_w = {(datab[30] | exp_b_not_zero_w[6]), (datab[29] | exp_b_not_zero_w[5]), (datab[28] | exp_b_not_zero_w[4]), (datab[27] | exp_b_not_zero_w[3]), (datab[26] | exp_b_not_zero_w[2]), (datab[25] | exp_b_not_zero_w[1]), (datab[24] | exp_b_not_zero_w[0]), datab[23]},
exp_result_mux_out = wire_exp_result_muxa_dataout,
exp_result_mux_sel_w = ((((a_zero_b_not_dffe_1 | b_is_infinity_dffe_1) | ((~ bias_addition_overf_w) & exp_sign_w)) | (((~ exp_add_output_not_zero[7]) & (~ bias_addition_overf_w)) & (~ exp_sign_w))) & (~ nan_pipe_dffe_1)),
exp_result_w = (({8{((~ bias_addition_overf_w) & (~ exp_sign_w))}} & bias_addition_w) | ({8{(((bias_addition_overf_w | divbyzero_pipe_dffe_1) | nan_pipe_dffe_1) | a_is_infinity_dffe_1)}} & overflow_ones_w)),
exp_sign_w = wire_bias_addition_result[8],
exp_sub_a_w = {1'b0, dataa[30:23]},
exp_sub_b_w = {1'b0, datab[30:23]},
exp_sub_w = wire_exp_sub_result,
frac_a_smaller_dffe1_wi = frac_a_smaller_w,
frac_a_smaller_dffe1_wo = frac_a_smaller_dffe1,
frac_a_smaller_w = wire_cmpr2_alb,
guard_bit = q_partial_perf_dffe_1[22],
man_a_adjusted_w = wire_man_a_adjusteda_dataout,
man_a_dffe1_wi = dataa[22:0],
man_a_dffe1_wo = man_a_dffe1_dffe1,
man_a_not_zero_w = {(dataa[22] | man_a_not_zero_w[21]), (dataa[21] | man_a_not_zero_w[20]), (dataa[20] | man_a_not_zero_w[19]), (dataa[19] | man_a_not_zero_w[18]), (dataa[18] | man_a_not_zero_w[17]), (dataa[17] | man_a_not_zero_w[16]), (dataa[16] | man_a_not_zero_w[15]), (dataa[15] | man_a_not_zero_w[14]), (dataa[14] | man_a_not_zero_w[13]), (dataa[13] | man_a_not_zero_w[12]), (dataa[12] | man_a_not_zero_w[11]), (dataa[11] | man_a_not_zero_w[10]), (dataa[10] | man_a_not_zero_w[9]), (dataa[9] | man_a_not_zero_w[8]), (dataa[8] | man_a_not_zero_w[7]), (dataa[7] | man_a_not_zero_w[6]), (dataa[6] | man_a_not_zero_w[5]), (dataa[5] | man_a_not_zero_w[4]), (dataa[4] | man_a_not_zero_w[3]), (dataa[3] | man_a_not_zero_w[2]), (dataa[2] | man_a_not_zero_w[1]), (dataa[1] | man_a_not_zero_w[0]), dataa[0]},
man_b_adjusted_w = {1'b1, man_b_dffe1_wo},
man_b_dffe1_wi = datab[22:0],
man_b_dffe1_wo = man_b_dffe1_dffe1,
man_b_not_zero_w = {(datab[22] | man_b_not_zero_w[21]), (datab[21] | man_b_not_zero_w[20]), (datab[20] | man_b_not_zero_w[19]), (datab[19] | man_b_not_zero_w[18]), (datab[18] | man_b_not_zero_w[17]), (datab[17] | man_b_not_zero_w[16]), (datab[16] | man_b_not_zero_w[15]), (datab[15] | man_b_not_zero_w[14]), (datab[14] | man_b_not_zero_w[13]), (datab[13] | man_b_not_zero_w[12]), (datab[12] | man_b_not_zero_w[11]), (datab[11] | man_b_not_zero_w[10]), (datab[10] | man_b_not_zero_w[9]), (datab[9] | man_b_not_zero_w[8]), (datab[8] | man_b_not_zero_w[7]), (datab[7] | man_b_not_zero_w[6]), (datab[6] | man_b_not_zero_w[5]), (datab[5] | man_b_not_zero_w[4]), (datab[4] | man_b_not_zero_w[3]), (datab[3] | man_b_not_zero_w[2]), (datab[2] | man_b_not_zero_w[1]), (datab[1] | man_b_not_zero_w[0]), datab[0]},
man_result_dffe_wi = man_result_w,
man_result_dffe_wo = man_result_dffe,
man_result_mux_select = (((((over_under_dffe_10 | a_zero_b_not_dffe_12) | nan_pipe_dffe_12) | b_is_infinity_dffe_12) | a_is_infinity_dffe_12) | divbyzero_pipe_dffe_12),
man_result_w = wire_man_result_muxa_dataout,
man_zeros_w = {23{1'b0}},
overflow_ones_w = {8{1'b1}},
overflow_underflow = (overflow_w | underflow_w),
overflow_w = ((bias_addition_overf_w | ((exp_add_output_all_one[7] & (~ bias_addition_overf_w)) & (~ exp_sign_w))) & (((~ nan_pipe_dffe_1) & (~ a_is_infinity_dffe_1)) & (~ divbyzero_pipe_dffe_1))),
quotient_accumulate_w = {quotient_k_dffe_0, {14{1'b0}}, quotient_j_dffe, {14{1'b0}}},
quotient_process_cin_w = (round_bit & (guard_bit | sticky_bits[4])),
remainder_j_w = {wire_remainder_sub_0_result[35:0], {14{1'b0}}, wire_a1_prod_result[34:0], {15{1'b0}}},
result = {sign_pipe_dffe_13, exp_result_dffe_11, man_result_dffe_wo},
round_bit = q_partial_perf_dffe_1[21],
select_bias_out_2_w = wire_select_bias_2a_dataout,
select_bias_out_w = wire_select_biasa_dataout,
sticky_bits = {(q_partial_perf_dffe_1[20] | sticky_bits[3]), (q_partial_perf_dffe_1[19] | sticky_bits[2]), (q_partial_perf_dffe_1[18] | sticky_bits[1]), (q_partial_perf_dffe_1[17] | sticky_bits[0]), q_partial_perf_dffe_1[16]},
underflow_w = ((((((~ bias_addition_overf_w) & exp_sign_w) | (((~ exp_add_output_not_zero[7]) & (~ bias_addition_overf_w)) & (~ exp_sign_w))) & (~ nan_pipe_dffe_1)) & (~ a_zero_b_not_dffe_1)) & (~ b_is_infinity_dffe_1)),
underflow_zeros_w = {8{1'b0}},
value_add_one_w = 9'b001111111,
value_normal_w = 9'b001111110,
value_zero_w = {9{1'b0}};
endmodule
|
module fp_divide_altfp_div_b6h
(
clock,
dataa,
datab,
result) ;
input clock;
input [31:0] dataa;
input [31:0] datab;
output [31:0] result;
wire [31:0] wire_altfp_div_pst1_result;
wire aclr;
wire clk_en;
fp_divide_altfp_div_pst_8qe altfp_div_pst1
(
.aclr(aclr),
.clk_en(clk_en),
.clock(clock),
.dataa(dataa),
.datab(datab),
.result(wire_altfp_div_pst1_result));
assign
aclr = 1'b0,
clk_en = 1'b1,
result = wire_altfp_div_pst1_result;
endmodule
|
module fp_divide (
clock,
dataa,
datab,
result);
input clock;
input [31:0] dataa;
input [31:0] datab;
output [31:0] result;
wire [31:0] sub_wire0;
wire [31:0] result = sub_wire0[31:0];
fp_divide_altfp_div_b6h fp_divide_altfp_div_b6h_component (
.clock (clock),
.dataa (dataa),
.datab (datab),
.result (sub_wire0));
endmodule
|
module FPU_PIPELINED_FPADDSUB_W32_EW8_SW23_SWR26_EWR5 ( clk, rst, beg_OP,
Data_X, Data_Y, add_subt, busy, overflow_flag, underflow_flag,
zero_flag, ready, final_result_ieee );
input [31:0] Data_X;
input [31:0] Data_Y;
output [31:0] final_result_ieee;
input clk, rst, beg_OP, add_subt;
output busy, overflow_flag, underflow_flag, zero_flag, ready;
wire Shift_reg_FLAGS_7_6, intAS, SIGN_FLAG_EXP, OP_FLAG_EXP, ZERO_FLAG_EXP,
SIGN_FLAG_SHT1, OP_FLAG_SHT1, ZERO_FLAG_SHT1, left_right_SHT2,
SIGN_FLAG_SHT2, OP_FLAG_SHT2, ZERO_FLAG_SHT2, SIGN_FLAG_SHT1SHT2,
ZERO_FLAG_SHT1SHT2, SIGN_FLAG_NRM, ZERO_FLAG_NRM, SIGN_FLAG_SFG,
OP_FLAG_SFG, ZERO_FLAG_SFG, inst_FSM_INPUT_ENABLE_state_next_1_, n463,
n464, n465, n466, n467, n468, n469, n470, n471, n472, n473, n474,
n475, n476, n477, n478, n479, n480, n481, n482, n483, n484, n485,
n486, n487, n488, n489, n490, n491, n492, n493, n494, n495, n496,
n497, n498, n499, n500, n501, n502, n503, n504, n505, n506, n507,
n508, n509, n510, n511, n512, n513, n514, n515, n516, n517, n518,
n519, n520, n521, n522, n523, n524, n525, n526, n527, n528, n529,
n530, n531, n532, n533, n534, n535, n536, n537, n538, n539, n540,
n541, n542, n543, n544, n545, n546, n547, n548, n549, n550, n551,
n552, n553, n554, n555, n556, n557, n558, n559, n560, n561, n562,
n563, n564, n565, n566, n567, n568, n569, n570, n571, n572, n573,
n574, n575, n576, n577, n578, n579, n580, n581, n582, n583, n584,
n585, n586, n587, n588, n589, n590, n591, n592, n593, n594, n595,
n596, n597, n598, n599, n600, n601, n602, n603, n604, n605, n606,
n607, n608, n609, n610, n611, n612, n613, n614, n615, n616, n617,
n618, n619, n620, n621, n622, n623, n624, n625, n626, n627, n628,
n629, n630, n631, n632, n633, n634, n635, n636, n637, n638, n639,
n640, n641, n642, n643, n644, n645, n646, n647, n648, n649, n650,
n651, n652, n653, n654, n655, n656, n657, n658, n659, n660, n661,
n662, n663, n664, n665, n666, n667, n668, n669, n670, n671, n672,
n673, n674, n675, n676, n677, n678, n679, n680, n681, n682, n683,
n684, n685, n686, n687, n688, n689, n690, n691, n692, n693, n694,
n695, n696, n697, n698, n699, n700, n701, n702, n703, n704, n705,
n706, n707, n708, n709, n710, n711, n712, n713, n714, n715, n716,
n717, n718, n719, n720, n721, n722, n723, n724, n725, n726, n727,
n728, n729, n730, n731, n732, n733, n734, n735, n736, n737, n738,
n739, n740, n741, n742, n743, n744, n745, n746, n747, n748, n749,
n750, n751, n752, n753, n754, n755, n756, n757, n758, n759, n760,
n761, n762, n763, n764, n765, n766, n767, n769, n770, n771, n772,
n773, n774, n775, n776, n777, n778, n779, n780, n781, n782, n783,
n784, n785, n786, n787, n788, n789, n790, n791, n792, n793, n794,
n795, n796, n797, n798, n799, n800, n801, n802, n803, n804, n805,
n806, n807, n808, n809, n810, n811, n812, n813, n814, n815, n816,
n817, n818, n819, n820, n821, n822, n823, n824, n825, n826, n827,
n828, n829, n830, n831, n832, n833, n834, n835, n836, n837, n838,
n839, n840, n841, n842, n843, n844, n845, n846, n847, n848, n849,
n850, n851, n852, n853, n854, n855, n856, n857, n858, n859, n860,
n861, n862, n863, n864, n865, n866, n867, n868, n869, n870, n871,
DP_OP_15J30_123_3372_n8, DP_OP_15J30_123_3372_n7,
DP_OP_15J30_123_3372_n6, DP_OP_15J30_123_3372_n5,
DP_OP_15J30_123_3372_n4, intadd_25_B_12_, intadd_25_B_11_,
intadd_25_B_10_, intadd_25_B_9_, intadd_25_B_8_, intadd_25_B_7_,
intadd_25_B_6_, intadd_25_B_5_, intadd_25_B_4_, intadd_25_B_3_,
intadd_25_B_2_, intadd_25_B_1_, intadd_25_B_0_, intadd_25_CI,
intadd_25_SUM_12_, intadd_25_SUM_11_, intadd_25_SUM_10_,
intadd_25_SUM_9_, intadd_25_SUM_8_, intadd_25_SUM_7_,
intadd_25_SUM_6_, intadd_25_SUM_5_, intadd_25_SUM_4_,
intadd_25_SUM_3_, intadd_25_SUM_2_, intadd_25_SUM_1_,
intadd_25_SUM_0_, intadd_25_n13, intadd_25_n12, intadd_25_n11,
intadd_25_n10, intadd_25_n9, intadd_25_n8, intadd_25_n7, intadd_25_n6,
intadd_25_n5, intadd_25_n4, intadd_25_n3, intadd_25_n2, intadd_25_n1,
intadd_26_A_2_, intadd_26_A_1_, intadd_26_B_2_, intadd_26_B_1_,
intadd_26_B_0_, intadd_26_CI, intadd_26_SUM_2_, intadd_26_SUM_1_,
intadd_26_SUM_0_, intadd_26_n3, intadd_26_n2, intadd_26_n1,
intadd_27_A_2_, intadd_27_A_1_, intadd_27_B_1_, intadd_27_B_0_,
intadd_27_CI, intadd_27_SUM_2_, intadd_27_SUM_1_, intadd_27_SUM_0_,
intadd_27_n3, intadd_27_n2, intadd_27_n1, n872, n873, n874, n875,
n876, n877, n878, n879, n880, n881, n882, n883, n884, n885, n886,
n887, n888, n889, n890, n891, n892, n893, n894, n895, n896, n897,
n898, n899, n900, n901, n902, n903, n904, n905, n906, n907, n908,
n909, n910, n911, n912, n913, n914, n915, n916, n917, n918, n919,
n920, n921, n922, n923, n924, n925, n926, n927, n928, n929, n930,
n931, n932, n933, n934, n935, n936, n937, n938, n939, n940, n941,
n942, n943, n944, n945, n946, n947, n948, n949, n950, n951, n952,
n953, n954, n955, n956, n957, n958, n959, n960, n961, n962, n963,
n964, n965, n966, n967, n968, n969, n970, n971, n972, n973, n974,
n975, n976, n977, n978, n979, n980, n981, n982, n983, n984, n985,
n986, n987, n988, n989, n990, n991, n992, n993, n994, n995, n996,
n997, n998, n999, n1000, n1001, n1002, n1003, n1004, n1005, n1006,
n1007, n1008, n1009, n1010, n1011, n1012, n1013, n1014, n1015, n1016,
n1017, n1018, n1019, n1020, n1021, n1022, n1023, n1024, n1025, n1026,
n1027, n1028, n1029, n1030, n1031, n1032, n1033, n1034, n1035, n1036,
n1037, n1038, n1039, n1040, n1041, n1042, n1043, n1044, n1045, n1046,
n1047, n1048, n1049, n1050, n1051, n1052, n1053, n1054, n1055, n1056,
n1057, n1058, n1059, n1060, n1061, n1062, n1063, n1064, n1065, n1066,
n1067, n1068, n1069, n1070, n1071, n1072, n1073, n1074, n1075, n1076,
n1077, n1078, n1079, n1080, n1081, n1082, n1083, n1084, n1085, n1086,
n1087, n1088, n1089, n1090, n1091, n1092, n1093, n1094, n1095, n1096,
n1097, n1098, n1099, n1100, n1101, n1102, n1103, n1104, n1105, n1106,
n1107, n1108, n1109, n1110, n1111, n1112, n1113, n1114, n1115, n1116,
n1117, n1118, n1119, n1120, n1121, n1122, n1123, n1124, n1125, n1126,
n1127, n1128, n1129, n1130, n1131, n1132, n1133, n1134, n1135, n1136,
n1137, n1138, n1139, n1140, n1141, n1142, n1143, n1144, n1145, n1146,
n1147, n1148, n1149, n1150, n1151, n1152, n1153, n1154, n1155, n1156,
n1157, n1158, n1159, n1160, n1161, n1162, n1163, n1164, n1165, n1166,
n1167, n1168, n1169, n1170, n1171, n1172, n1173, n1174, n1175, n1176,
n1177, n1178, n1179, n1180, n1181, n1182, n1183, n1184, n1185, n1186,
n1187, n1188, n1189, n1190, n1191, n1192, n1193, n1194, n1195, n1196,
n1197, n1198, n1199, n1200, n1201, n1202, n1203, n1204, n1205, n1206,
n1207, n1208, n1209, n1210, n1211, n1212, n1213, n1214, n1215, n1216,
n1217, n1218, n1219, n1220, n1221, n1223, n1225, n1226, n1227, n1228,
n1229, n1230, n1231, n1232, n1233, n1234, n1235, n1236, n1237, n1238,
n1239, n1240, n1241, n1242, n1243, n1244, n1245, n1246, n1247, n1248,
n1249, n1250, n1251, n1252, n1253, n1254, n1255, n1256, n1257, n1258,
n1259, n1260, n1261, n1262, n1263, n1264, n1265, n1266, n1267, n1268,
n1269, n1270, n1271, n1272, n1273, n1274, n1275, n1276, n1277, n1278,
n1279, n1280, n1281, n1282, n1283, n1284, n1285, n1286, n1287, n1288,
n1289, n1291, n1292, n1293, n1294, n1295, n1296, n1297, n1298, n1299,
n1300, n1301, n1302, n1303, n1304, n1305, n1306, n1307, n1308, n1309,
n1310, n1311, n1312, n1313, n1314, n1315, n1316, n1317, n1318, n1319,
n1320, n1321, n1322, n1323, n1324, n1325, n1327, n1328, n1329, n1330,
n1332, n1333, n1334, n1335, n1336, n1337, n1341, n1342, n1343, n1344,
n1345, n1346, n1347, n1348, n1349, n1350, n1351, n1352, n1353, n1354,
n1355, n1357, n1358, n1359, n1360, n1361, n1362, n1363, n1364, n1365,
n1366, n1367, n1368, n1369, n1370, n1371, n1372, n1373, n1374, n1375,
n1376, n1377, n1378, n1379, n1380, n1381, n1382, n1383, n1384, n1385,
n1386, n1387, n1388, n1389, n1390, n1391, n1392, n1393, n1394, n1395,
n1396, n1397, n1398, n1399, n1400, n1401, n1402, n1403, n1404, n1405,
n1406, n1407, n1408, n1409, n1410, n1411, n1412, n1413, n1414, n1415,
n1416, n1417, n1418, n1419, n1420, n1421, n1422, n1423, n1424, n1425,
n1426, n1428, n1429, n1430, n1431, n1432, n1433, n1434, n1435, n1436,
n1437, n1438, n1439, n1440, n1441, n1442, n1443, n1444, n1445, n1446,
n1447, n1448, n1449, n1450, n1451, n1452, n1453, n1454, n1455, n1456,
n1457, n1458, n1459, n1460, n1461, n1462, n1463, n1464, n1465, n1466,
n1467, n1468, n1469, n1470, n1471, n1472, n1474, n1475, n1476, n1477,
n1478, n1479, n1480, n1481, n1482, n1483, n1484, n1485, n1486, n1487,
n1488, n1489, n1490, n1491, n1492, n1493, n1494, n1495, n1496, n1497,
n1498, n1499, n1500, n1501, n1502, n1503, n1504, n1505, n1506, n1507,
n1508, n1509, n1510, n1511, n1512, n1513, n1514, n1515, n1516, n1517,
n1518, n1519, n1520, n1521, n1522, n1523, n1524, n1525, n1526, n1527,
n1528, n1529, n1530, n1531, n1532, n1533, n1534, n1535, n1536, n1537,
n1538, n1539, n1540, n1541, n1542, n1543, n1544, n1545, n1546, n1547,
n1548, n1549, n1550, n1551, n1552, n1553, n1554, n1555, n1556, n1557,
n1558, n1559, n1560, n1561, n1562, n1563, n1564, n1565, n1566, n1567,
n1568, n1569, n1570, n1571, n1572, n1573, n1574, n1575, n1576, n1577,
n1578, n1579, n1581, n1582, n1583, n1584, n1585, n1586, n1587, n1588,
n1589, n1590, n1591, n1592, n1593, n1594, n1595, n1596, n1597, n1598,
n1599, n1600, n1601, n1602, n1603, n1604, n1605, n1606, n1607, n1608,
n1609, n1610, n1612, n1613, n1614;
wire [1:0] Shift_reg_FLAGS_7;
wire [31:1] intDX_EWSW;
wire [31:0] intDY_EWSW;
wire [30:0] DMP_EXP_EWSW;
wire [27:0] DmP_EXP_EWSW;
wire [30:0] DMP_SHT1_EWSW;
wire [22:0] DmP_mant_SHT1_SW;
wire [4:0] Shift_amount_SHT1_EWR;
wire [25:0] Raw_mant_NRM_SWR;
wire [25:0] Data_array_SWR;
wire [30:0] DMP_SHT2_EWSW;
wire [4:2] shift_value_SHT2_EWR;
wire [7:0] DMP_exp_NRM2_EW;
wire [7:0] DMP_exp_NRM_EW;
wire [4:0] LZD_output_NRM2_EW;
wire [4:1] exp_rslt_NRM2_EW1;
wire [30:0] DMP_SFG;
wire [25:0] DmP_mant_SFG_SWR;
wire [2:0] inst_FSM_INPUT_ENABLE_state_reg;
DFFRXLTS inst_ShiftRegister_Q_reg_3_ ( .D(n866), .CK(clk), .RN(n1588), .QN(
n884) );
DFFRXLTS INPUT_STAGE_OPERANDX_Q_reg_0_ ( .D(n862), .CK(clk), .RN(n1583),
.QN(n878) );
DFFRXLTS SHT2_STAGE_SHFTVARS2_Q_reg_1_ ( .D(n829), .CK(clk), .RN(n1582), .Q(
left_right_SHT2) );
DFFRXLTS Ready_reg_Q_reg_0_ ( .D(Shift_reg_FLAGS_7[0]), .CK(clk), .RN(n1583),
.Q(ready) );
DFFRXLTS SHT1_STAGE_sft_amount_Q_reg_1_ ( .D(n765), .CK(clk), .RN(n1587),
.Q(Shift_amount_SHT1_EWR[1]) );
DFFRXLTS SHT1_STAGE_sft_amount_Q_reg_2_ ( .D(n764), .CK(clk), .RN(n1586),
.Q(Shift_amount_SHT1_EWR[2]) );
DFFRXLTS SHT1_STAGE_sft_amount_Q_reg_3_ ( .D(n763), .CK(clk), .RN(n1590),
.Q(Shift_amount_SHT1_EWR[3]) );
DFFRXLTS SHT1_STAGE_sft_amount_Q_reg_4_ ( .D(n762), .CK(clk), .RN(n1591),
.Q(Shift_amount_SHT1_EWR[4]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_23_ ( .D(n761), .CK(clk), .RN(n1607), .Q(
final_result_ieee[23]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_24_ ( .D(n760), .CK(clk), .RN(n1582), .Q(
final_result_ieee[24]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_25_ ( .D(n759), .CK(clk), .RN(n1592), .Q(
final_result_ieee[25]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_26_ ( .D(n758), .CK(clk), .RN(n1595), .Q(
final_result_ieee[26]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_27_ ( .D(n757), .CK(clk), .RN(n1593), .Q(
final_result_ieee[27]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_28_ ( .D(n756), .CK(clk), .RN(n1596), .Q(
final_result_ieee[28]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_29_ ( .D(n755), .CK(clk), .RN(n1599), .Q(
final_result_ieee[29]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_30_ ( .D(n754), .CK(clk), .RN(n1599), .Q(
final_result_ieee[30]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_0_ ( .D(n753), .CK(clk), .RN(n1589), .Q(
DMP_EXP_EWSW[0]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_1_ ( .D(n752), .CK(clk), .RN(n1587), .Q(
DMP_EXP_EWSW[1]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_2_ ( .D(n751), .CK(clk), .RN(n1587), .Q(
DMP_EXP_EWSW[2]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_3_ ( .D(n750), .CK(clk), .RN(n1586), .Q(
DMP_EXP_EWSW[3]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_4_ ( .D(n749), .CK(clk), .RN(n1590), .Q(
DMP_EXP_EWSW[4]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_5_ ( .D(n748), .CK(clk), .RN(n1591), .Q(
DMP_EXP_EWSW[5]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_6_ ( .D(n747), .CK(clk), .RN(n1589), .Q(
DMP_EXP_EWSW[6]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_7_ ( .D(n746), .CK(clk), .RN(n1587), .Q(
DMP_EXP_EWSW[7]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_8_ ( .D(n745), .CK(clk), .RN(n876), .Q(
DMP_EXP_EWSW[8]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_9_ ( .D(n744), .CK(clk), .RN(n1585), .Q(
DMP_EXP_EWSW[9]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_10_ ( .D(n743), .CK(clk), .RN(n1588), .Q(
DMP_EXP_EWSW[10]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_11_ ( .D(n742), .CK(clk), .RN(n1582), .Q(
DMP_EXP_EWSW[11]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_12_ ( .D(n741), .CK(clk), .RN(n1595), .Q(
DMP_EXP_EWSW[12]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_13_ ( .D(n740), .CK(clk), .RN(n1583), .Q(
DMP_EXP_EWSW[13]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_14_ ( .D(n739), .CK(clk), .RN(n1584), .Q(
DMP_EXP_EWSW[14]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_15_ ( .D(n738), .CK(clk), .RN(n1585), .Q(
DMP_EXP_EWSW[15]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_16_ ( .D(n737), .CK(clk), .RN(n1588), .Q(
DMP_EXP_EWSW[16]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_17_ ( .D(n736), .CK(clk), .RN(n1582), .Q(
DMP_EXP_EWSW[17]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_18_ ( .D(n735), .CK(clk), .RN(n1588), .Q(
DMP_EXP_EWSW[18]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_19_ ( .D(n734), .CK(clk), .RN(n1583), .Q(
DMP_EXP_EWSW[19]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_20_ ( .D(n733), .CK(clk), .RN(n1584), .Q(
DMP_EXP_EWSW[20]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_21_ ( .D(n732), .CK(clk), .RN(n1599), .Q(
DMP_EXP_EWSW[21]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_22_ ( .D(n731), .CK(clk), .RN(n1608), .Q(
DMP_EXP_EWSW[22]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_27_ ( .D(n726), .CK(clk), .RN(n1596), .QN(n885)
);
DFFRXLTS EXP_STAGE_DMP_Q_reg_28_ ( .D(n725), .CK(clk), .RN(n1593), .Q(
DMP_EXP_EWSW[28]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_29_ ( .D(n724), .CK(clk), .RN(n1599), .Q(
DMP_EXP_EWSW[29]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_30_ ( .D(n723), .CK(clk), .RN(n1596), .Q(
DMP_EXP_EWSW[30]) );
DFFRXLTS EXP_STAGE_FLAGS_Q_reg_1_ ( .D(n722), .CK(clk), .RN(n1608), .Q(
OP_FLAG_EXP) );
DFFRXLTS EXP_STAGE_FLAGS_Q_reg_0_ ( .D(n721), .CK(clk), .RN(n1599), .Q(
ZERO_FLAG_EXP) );
DFFRXLTS EXP_STAGE_FLAGS_Q_reg_2_ ( .D(n720), .CK(clk), .RN(n1599), .Q(
SIGN_FLAG_EXP) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_0_ ( .D(n719), .CK(clk), .RN(n1599), .Q(
DMP_SHT1_EWSW[0]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_0_ ( .D(n718), .CK(clk), .RN(n1596), .Q(
DMP_SHT2_EWSW[0]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_1_ ( .D(n716), .CK(clk), .RN(n1593), .Q(
DMP_SHT1_EWSW[1]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_1_ ( .D(n715), .CK(clk), .RN(n1595), .Q(
DMP_SHT2_EWSW[1]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_2_ ( .D(n713), .CK(clk), .RN(n1592), .Q(
DMP_SHT1_EWSW[2]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_2_ ( .D(n712), .CK(clk), .RN(n1608), .Q(
DMP_SHT2_EWSW[2]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_3_ ( .D(n710), .CK(clk), .RN(n1584), .Q(
DMP_SHT1_EWSW[3]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_3_ ( .D(n709), .CK(clk), .RN(n1608), .Q(
DMP_SHT2_EWSW[3]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_3_ ( .D(n708), .CK(clk), .RN(n1594), .Q(
DMP_SFG[3]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_4_ ( .D(n707), .CK(clk), .RN(n1597), .Q(
DMP_SHT1_EWSW[4]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_4_ ( .D(n706), .CK(clk), .RN(n1607), .Q(
DMP_SHT2_EWSW[4]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_4_ ( .D(n705), .CK(clk), .RN(n1604), .Q(
DMP_SFG[4]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_5_ ( .D(n704), .CK(clk), .RN(n1609), .Q(
DMP_SHT1_EWSW[5]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_5_ ( .D(n703), .CK(clk), .RN(n893), .Q(
DMP_SHT2_EWSW[5]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_6_ ( .D(n701), .CK(clk), .RN(n1594), .Q(
DMP_SHT1_EWSW[6]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_6_ ( .D(n700), .CK(clk), .RN(n1597), .Q(
DMP_SHT2_EWSW[6]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_7_ ( .D(n698), .CK(clk), .RN(n1597), .Q(
DMP_SHT1_EWSW[7]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_7_ ( .D(n697), .CK(clk), .RN(n1603), .Q(
DMP_SHT2_EWSW[7]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_7_ ( .D(n696), .CK(clk), .RN(n1604), .Q(
DMP_SFG[7]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_8_ ( .D(n695), .CK(clk), .RN(n1609), .Q(
DMP_SHT1_EWSW[8]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_8_ ( .D(n694), .CK(clk), .RN(n893), .Q(
DMP_SHT2_EWSW[8]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_8_ ( .D(n693), .CK(clk), .RN(n1594), .Q(
DMP_SFG[8]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_9_ ( .D(n692), .CK(clk), .RN(n1597), .Q(
DMP_SHT1_EWSW[9]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_9_ ( .D(n691), .CK(clk), .RN(n1597), .Q(
DMP_SHT2_EWSW[9]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_10_ ( .D(n689), .CK(clk), .RN(n1601), .Q(
DMP_SHT1_EWSW[10]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_10_ ( .D(n688), .CK(clk), .RN(n1594), .Q(
DMP_SHT2_EWSW[10]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_11_ ( .D(n686), .CK(clk), .RN(n1605), .Q(
DMP_SHT1_EWSW[11]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_11_ ( .D(n685), .CK(clk), .RN(n1597), .Q(
DMP_SHT2_EWSW[11]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_12_ ( .D(n683), .CK(clk), .RN(n1593), .Q(
DMP_SHT1_EWSW[12]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_12_ ( .D(n682), .CK(clk), .RN(n1596), .Q(
DMP_SHT2_EWSW[12]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_13_ ( .D(n680), .CK(clk), .RN(n1592), .Q(
DMP_SHT1_EWSW[13]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_13_ ( .D(n679), .CK(clk), .RN(n1583), .Q(
DMP_SHT2_EWSW[13]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_14_ ( .D(n677), .CK(clk), .RN(n1599), .Q(
DMP_SHT1_EWSW[14]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_14_ ( .D(n676), .CK(clk), .RN(n1595), .Q(
DMP_SHT2_EWSW[14]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_15_ ( .D(n674), .CK(clk), .RN(n1596), .Q(
DMP_SHT1_EWSW[15]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_15_ ( .D(n673), .CK(clk), .RN(n1608), .Q(
DMP_SHT2_EWSW[15]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_16_ ( .D(n671), .CK(clk), .RN(n1593), .Q(
DMP_SHT1_EWSW[16]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_16_ ( .D(n670), .CK(clk), .RN(n1595), .Q(
DMP_SHT2_EWSW[16]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_17_ ( .D(n668), .CK(clk), .RN(n1592), .Q(
DMP_SHT1_EWSW[17]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_17_ ( .D(n667), .CK(clk), .RN(n1595), .Q(
DMP_SHT2_EWSW[17]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_18_ ( .D(n665), .CK(clk), .RN(n1608), .Q(
DMP_SHT1_EWSW[18]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_18_ ( .D(n664), .CK(clk), .RN(n1599), .Q(
DMP_SHT2_EWSW[18]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_19_ ( .D(n662), .CK(clk), .RN(n1596), .Q(
DMP_SHT1_EWSW[19]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_19_ ( .D(n661), .CK(clk), .RN(n1593), .Q(
DMP_SHT2_EWSW[19]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_20_ ( .D(n659), .CK(clk), .RN(n893), .Q(
DMP_SHT1_EWSW[20]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_20_ ( .D(n658), .CK(clk), .RN(n1594), .Q(
DMP_SHT2_EWSW[20]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_21_ ( .D(n656), .CK(clk), .RN(n1605), .Q(
DMP_SHT1_EWSW[21]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_21_ ( .D(n655), .CK(clk), .RN(n1597), .Q(
DMP_SHT2_EWSW[21]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_22_ ( .D(n653), .CK(clk), .RN(n1603), .Q(
DMP_SHT1_EWSW[22]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_22_ ( .D(n652), .CK(clk), .RN(n1604), .Q(
DMP_SHT2_EWSW[22]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_23_ ( .D(n650), .CK(clk), .RN(n1609), .Q(
DMP_SHT1_EWSW[23]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_23_ ( .D(n649), .CK(clk), .RN(n893), .Q(
DMP_SHT2_EWSW[23]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_23_ ( .D(n648), .CK(clk), .RN(n1594), .Q(
DMP_SFG[23]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_0_ ( .D(n647), .CK(clk), .RN(n1594), .Q(
DMP_exp_NRM_EW[0]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_24_ ( .D(n645), .CK(clk), .RN(n1597), .Q(
DMP_SHT1_EWSW[24]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_24_ ( .D(n644), .CK(clk), .RN(n1607), .Q(
DMP_SHT2_EWSW[24]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_24_ ( .D(n643), .CK(clk), .RN(n1604), .Q(
DMP_SFG[24]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_1_ ( .D(n642), .CK(clk), .RN(n1609), .Q(
DMP_exp_NRM_EW[1]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_25_ ( .D(n640), .CK(clk), .RN(n1594), .Q(
DMP_SHT1_EWSW[25]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_25_ ( .D(n639), .CK(clk), .RN(n1597), .Q(
DMP_SHT2_EWSW[25]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_25_ ( .D(n638), .CK(clk), .RN(n1597), .Q(
DMP_SFG[25]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_2_ ( .D(n637), .CK(clk), .RN(n893), .Q(
DMP_exp_NRM_EW[2]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_26_ ( .D(n635), .CK(clk), .RN(n1603), .Q(
DMP_SHT1_EWSW[26]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_26_ ( .D(n634), .CK(clk), .RN(n1594), .Q(
DMP_SHT2_EWSW[26]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_26_ ( .D(n633), .CK(clk), .RN(n876), .Q(
DMP_SFG[26]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_3_ ( .D(n632), .CK(clk), .RN(n1602), .Q(
DMP_exp_NRM_EW[3]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_27_ ( .D(n630), .CK(clk), .RN(n1582), .Q(
DMP_SHT1_EWSW[27]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_27_ ( .D(n629), .CK(clk), .RN(n1598), .Q(
DMP_SHT2_EWSW[27]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_27_ ( .D(n628), .CK(clk), .RN(n1605), .Q(
DMP_SFG[27]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_4_ ( .D(n627), .CK(clk), .RN(n1605), .Q(
DMP_exp_NRM_EW[4]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_28_ ( .D(n625), .CK(clk), .RN(n876), .Q(
DMP_SHT1_EWSW[28]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_28_ ( .D(n624), .CK(clk), .RN(n1602), .Q(
DMP_SHT2_EWSW[28]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_28_ ( .D(n623), .CK(clk), .RN(n1588), .Q(
DMP_SFG[28]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_5_ ( .D(n622), .CK(clk), .RN(n1598), .Q(
DMP_exp_NRM_EW[5]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_29_ ( .D(n620), .CK(clk), .RN(n1605), .Q(
DMP_SHT1_EWSW[29]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_29_ ( .D(n619), .CK(clk), .RN(n925), .Q(
DMP_SHT2_EWSW[29]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_29_ ( .D(n618), .CK(clk), .RN(n1592), .Q(
DMP_SFG[29]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_6_ ( .D(n617), .CK(clk), .RN(n1608), .Q(
DMP_exp_NRM_EW[6]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_30_ ( .D(n615), .CK(clk), .RN(n1585), .Q(
DMP_SHT1_EWSW[30]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_30_ ( .D(n614), .CK(clk), .RN(n1608), .Q(
DMP_SHT2_EWSW[30]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_30_ ( .D(n613), .CK(clk), .RN(n1596), .Q(
DMP_SFG[30]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_7_ ( .D(n612), .CK(clk), .RN(n1593), .Q(
DMP_exp_NRM_EW[7]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_0_ ( .D(n610), .CK(clk), .RN(n1595), .Q(
DmP_EXP_EWSW[0]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_1_ ( .D(n608), .CK(clk), .RN(n1592), .Q(
DmP_EXP_EWSW[1]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_2_ ( .D(n606), .CK(clk), .RN(n1596), .Q(
DmP_EXP_EWSW[2]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_3_ ( .D(n604), .CK(clk), .RN(n1606), .Q(
DmP_EXP_EWSW[3]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_4_ ( .D(n602), .CK(clk), .RN(n1603), .Q(
DmP_EXP_EWSW[4]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_4_ ( .D(n601), .CK(clk), .RN(n1600), .QN(
n889) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_5_ ( .D(n600), .CK(clk), .RN(n925), .Q(
DmP_EXP_EWSW[5]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_5_ ( .D(n599), .CK(clk), .RN(n1601), .QN(
n886) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_6_ ( .D(n598), .CK(clk), .RN(n1607), .Q(
DmP_EXP_EWSW[6]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_7_ ( .D(n596), .CK(clk), .RN(n1606), .Q(
DmP_EXP_EWSW[7]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_8_ ( .D(n594), .CK(clk), .RN(n1603), .Q(
DmP_EXP_EWSW[8]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_9_ ( .D(n592), .CK(clk), .RN(n925), .Q(
DmP_EXP_EWSW[9]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_9_ ( .D(n591), .CK(clk), .RN(n1601), .QN(
n890) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_10_ ( .D(n590), .CK(clk), .RN(n1606), .Q(
DmP_EXP_EWSW[10]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_11_ ( .D(n588), .CK(clk), .RN(n1606), .Q(
DmP_EXP_EWSW[11]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_11_ ( .D(n587), .CK(clk), .RN(n1607),
.QN(n887) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_12_ ( .D(n586), .CK(clk), .RN(n1603), .Q(
DmP_EXP_EWSW[12]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_13_ ( .D(n584), .CK(clk), .RN(n1607), .Q(
DmP_EXP_EWSW[13]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_14_ ( .D(n582), .CK(clk), .RN(n1600), .Q(
DmP_EXP_EWSW[14]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_15_ ( .D(n580), .CK(clk), .RN(n876), .Q(
DmP_EXP_EWSW[15]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_16_ ( .D(n578), .CK(clk), .RN(n1602), .Q(
DmP_EXP_EWSW[16]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_17_ ( .D(n576), .CK(clk), .RN(n1596), .Q(
DmP_EXP_EWSW[17]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_18_ ( .D(n574), .CK(clk), .RN(n1598), .Q(
DmP_EXP_EWSW[18]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_19_ ( .D(n572), .CK(clk), .RN(n1605), .Q(
DmP_EXP_EWSW[19]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_19_ ( .D(n571), .CK(clk), .RN(n876), .QN(
n888) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_20_ ( .D(n570), .CK(clk), .RN(n1602), .Q(
DmP_EXP_EWSW[20]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_21_ ( .D(n568), .CK(clk), .RN(n1602), .Q(
DmP_EXP_EWSW[21]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_22_ ( .D(n566), .CK(clk), .RN(n1595), .Q(
DmP_EXP_EWSW[22]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_23_ ( .D(n564), .CK(clk), .RN(n1605), .Q(
DmP_EXP_EWSW[23]) );
DFFRXLTS FRMT_STAGE_FLAGS_Q_reg_1_ ( .D(n559), .CK(clk), .RN(n1585), .Q(
underflow_flag) );
DFFRXLTS FRMT_STAGE_FLAGS_Q_reg_2_ ( .D(n558), .CK(clk), .RN(n1592), .Q(
overflow_flag) );
DFFRXLTS SHT1_STAGE_FLAGS_Q_reg_0_ ( .D(n557), .CK(clk), .RN(n1598), .Q(
ZERO_FLAG_SHT1) );
DFFRXLTS SHT2_STAGE_FLAGS_Q_reg_0_ ( .D(n556), .CK(clk), .RN(n876), .Q(
ZERO_FLAG_SHT2) );
DFFRXLTS SGF_STAGE_FLAGS_Q_reg_0_ ( .D(n555), .CK(clk), .RN(n1600), .Q(
ZERO_FLAG_SFG) );
DFFRXLTS NRM_STAGE_FLAGS_Q_reg_0_ ( .D(n554), .CK(clk), .RN(n925), .Q(
ZERO_FLAG_NRM) );
DFFRXLTS SFT2FRMT_STAGE_FLAGS_Q_reg_0_ ( .D(n553), .CK(clk), .RN(n1601), .Q(
ZERO_FLAG_SHT1SHT2) );
DFFRXLTS FRMT_STAGE_FLAGS_Q_reg_0_ ( .D(n552), .CK(clk), .RN(n1607), .Q(
zero_flag) );
DFFRXLTS SHT1_STAGE_FLAGS_Q_reg_1_ ( .D(n551), .CK(clk), .RN(n1606), .Q(
OP_FLAG_SHT1) );
DFFRXLTS SHT2_STAGE_FLAGS_Q_reg_1_ ( .D(n550), .CK(clk), .RN(n1603), .Q(
OP_FLAG_SHT2) );
DFFRXLTS SHT1_STAGE_FLAGS_Q_reg_2_ ( .D(n548), .CK(clk), .RN(n1600), .Q(
SIGN_FLAG_SHT1) );
DFFRXLTS SHT2_STAGE_FLAGS_Q_reg_2_ ( .D(n547), .CK(clk), .RN(n925), .Q(
SIGN_FLAG_SHT2) );
DFFRXLTS SGF_STAGE_FLAGS_Q_reg_2_ ( .D(n546), .CK(clk), .RN(n1601), .Q(
SIGN_FLAG_SFG) );
DFFRXLTS NRM_STAGE_FLAGS_Q_reg_1_ ( .D(n545), .CK(clk), .RN(n1607), .Q(
SIGN_FLAG_NRM) );
DFFRXLTS SFT2FRMT_STAGE_FLAGS_Q_reg_1_ ( .D(n544), .CK(clk), .RN(n1606), .Q(
SIGN_FLAG_SHT1SHT2) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_31_ ( .D(n543), .CK(clk), .RN(n1588), .Q(
final_result_ieee[31]) );
DFFRXLTS SFT2FRMT_STAGE_VARS_Q_reg_8_ ( .D(n515), .CK(clk), .RN(n1604), .Q(
LZD_output_NRM2_EW[0]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_10_ ( .D(n511), .CK(clk), .RN(n1605), .Q(
final_result_ieee[10]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_11_ ( .D(n510), .CK(clk), .RN(n1593), .Q(
final_result_ieee[11]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_9_ ( .D(n509), .CK(clk), .RN(n1598), .Q(
final_result_ieee[9]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_12_ ( .D(n508), .CK(clk), .RN(n1583), .Q(
final_result_ieee[12]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_8_ ( .D(n507), .CK(clk), .RN(n1605), .Q(
final_result_ieee[8]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_13_ ( .D(n506), .CK(clk), .RN(n876), .Q(
final_result_ieee[13]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_7_ ( .D(n505), .CK(clk), .RN(n1602), .Q(
final_result_ieee[7]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_14_ ( .D(n504), .CK(clk), .RN(n1584), .Q(
final_result_ieee[14]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_6_ ( .D(n503), .CK(clk), .RN(n1598), .Q(
final_result_ieee[6]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_15_ ( .D(n502), .CK(clk), .RN(n1605), .Q(
final_result_ieee[15]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_5_ ( .D(n501), .CK(clk), .RN(n1606), .Q(
final_result_ieee[5]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_16_ ( .D(n500), .CK(clk), .RN(n1603), .Q(
final_result_ieee[16]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_4_ ( .D(n499), .CK(clk), .RN(n1600), .Q(
final_result_ieee[4]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_17_ ( .D(n498), .CK(clk), .RN(n925), .Q(
final_result_ieee[17]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_3_ ( .D(n497), .CK(clk), .RN(n1601), .Q(
final_result_ieee[3]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_18_ ( .D(n496), .CK(clk), .RN(n1607), .Q(
final_result_ieee[18]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_2_ ( .D(n495), .CK(clk), .RN(n1606), .Q(
final_result_ieee[2]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_19_ ( .D(n494), .CK(clk), .RN(n925), .Q(
final_result_ieee[19]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_1_ ( .D(n493), .CK(clk), .RN(n1603), .Q(
final_result_ieee[1]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_0_ ( .D(n492), .CK(clk), .RN(n1600), .Q(
final_result_ieee[0]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_20_ ( .D(n491), .CK(clk), .RN(n1601), .Q(
final_result_ieee[20]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_21_ ( .D(n490), .CK(clk), .RN(n1606), .Q(
final_result_ieee[21]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_22_ ( .D(n489), .CK(clk), .RN(n1603), .Q(
final_result_ieee[22]) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_0_ ( .D(n488), .CK(clk), .RN(n1600), .Q(
DmP_mant_SFG_SWR[0]) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_1_ ( .D(n487), .CK(clk), .RN(n925), .Q(
DmP_mant_SFG_SWR[1]), .QN(n914) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_2_ ( .D(n486), .CK(clk), .RN(n1601), .Q(
DmP_mant_SFG_SWR[2]), .QN(n915) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_3_ ( .D(n485), .CK(clk), .RN(n1607), .Q(
DmP_mant_SFG_SWR[3]), .QN(n916) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_4_ ( .D(n484), .CK(clk), .RN(n1606), .Q(
DmP_mant_SFG_SWR[4]), .QN(n917) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_5_ ( .D(n483), .CK(clk), .RN(n1603), .Q(
DmP_mant_SFG_SWR[5]), .QN(n918) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_6_ ( .D(n482), .CK(clk), .RN(n1600), .Q(
DmP_mant_SFG_SWR[6]), .QN(n921) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_7_ ( .D(n481), .CK(clk), .RN(n925), .Q(
DmP_mant_SFG_SWR[7]), .QN(n922) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_8_ ( .D(n480), .CK(clk), .RN(n1601), .Q(
DmP_mant_SFG_SWR[8]), .QN(n920) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_9_ ( .D(n479), .CK(clk), .RN(n1607), .Q(
DmP_mant_SFG_SWR[9]), .QN(n923) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_16_ ( .D(n472), .CK(clk), .RN(n1608), .Q(
DmP_mant_SFG_SWR[16]), .QN(n919) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_17_ ( .D(n471), .CK(clk), .RN(n1599), .Q(
DmP_mant_SFG_SWR[17]), .QN(n912) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_18_ ( .D(n470), .CK(clk), .RN(n1596), .Q(
DmP_mant_SFG_SWR[18]) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_19_ ( .D(n469), .CK(clk), .RN(n1593), .Q(
DmP_mant_SFG_SWR[19]) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_20_ ( .D(n468), .CK(clk), .RN(n1595), .Q(
DmP_mant_SFG_SWR[20]) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_21_ ( .D(n467), .CK(clk), .RN(n1592), .Q(
DmP_mant_SFG_SWR[21]) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_22_ ( .D(n466), .CK(clk), .RN(n1593), .Q(
DmP_mant_SFG_SWR[22]) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_23_ ( .D(n465), .CK(clk), .RN(n1596), .Q(
DmP_mant_SFG_SWR[23]) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_24_ ( .D(n464), .CK(clk), .RN(n1593), .Q(
DmP_mant_SFG_SWR[24]) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_25_ ( .D(n463), .CK(clk), .RN(n1595), .Q(
DmP_mant_SFG_SWR[25]), .QN(n913) );
CMPR32X2TS intadd_25_U14 ( .A(n1520), .B(intadd_25_B_0_), .C(intadd_25_CI),
.CO(intadd_25_n13), .S(intadd_25_SUM_0_) );
CMPR32X2TS intadd_25_U13 ( .A(n1526), .B(intadd_25_B_1_), .C(intadd_25_n13),
.CO(intadd_25_n12), .S(intadd_25_SUM_1_) );
CMPR32X2TS intadd_25_U12 ( .A(n1525), .B(intadd_25_B_2_), .C(intadd_25_n12),
.CO(intadd_25_n11), .S(intadd_25_SUM_2_) );
CMPR32X2TS intadd_25_U11 ( .A(n1531), .B(intadd_25_B_3_), .C(intadd_25_n11),
.CO(intadd_25_n10), .S(intadd_25_SUM_3_) );
CMPR32X2TS intadd_25_U10 ( .A(n1530), .B(intadd_25_B_4_), .C(intadd_25_n10),
.CO(intadd_25_n9), .S(intadd_25_SUM_4_) );
CMPR32X2TS intadd_25_U9 ( .A(n1537), .B(intadd_25_B_5_), .C(intadd_25_n9),
.CO(intadd_25_n8), .S(intadd_25_SUM_5_) );
CMPR32X2TS intadd_25_U8 ( .A(n1559), .B(intadd_25_B_6_), .C(intadd_25_n8),
.CO(intadd_25_n7), .S(intadd_25_SUM_6_) );
CMPR32X2TS intadd_25_U7 ( .A(n1558), .B(intadd_25_B_7_), .C(intadd_25_n7),
.CO(intadd_25_n6), .S(intadd_25_SUM_7_) );
CMPR32X2TS intadd_25_U6 ( .A(n1566), .B(intadd_25_B_8_), .C(intadd_25_n6),
.CO(intadd_25_n5), .S(intadd_25_SUM_8_) );
CMPR32X2TS intadd_25_U5 ( .A(n1565), .B(intadd_25_B_9_), .C(intadd_25_n5),
.CO(intadd_25_n4), .S(intadd_25_SUM_9_) );
CMPR32X2TS intadd_25_U4 ( .A(n1574), .B(intadd_25_B_10_), .C(intadd_25_n4),
.CO(intadd_25_n3), .S(intadd_25_SUM_10_) );
CMPR32X2TS intadd_25_U3 ( .A(n1573), .B(intadd_25_B_11_), .C(intadd_25_n3),
.CO(intadd_25_n2), .S(intadd_25_SUM_11_) );
CMPR32X2TS intadd_25_U2 ( .A(n1578), .B(intadd_25_B_12_), .C(intadd_25_n2),
.CO(intadd_25_n1), .S(intadd_25_SUM_12_) );
CMPR32X2TS intadd_26_U4 ( .A(n1563), .B(intadd_26_B_0_), .C(intadd_26_CI),
.CO(intadd_26_n3), .S(intadd_26_SUM_0_) );
CMPR32X2TS intadd_26_U3 ( .A(intadd_26_A_1_), .B(intadd_26_B_1_), .C(
intadd_26_n3), .CO(intadd_26_n2), .S(intadd_26_SUM_1_) );
CMPR32X2TS intadd_26_U2 ( .A(intadd_26_A_2_), .B(intadd_26_B_2_), .C(
intadd_26_n2), .CO(intadd_26_n1), .S(intadd_26_SUM_2_) );
CMPR32X2TS intadd_27_U4 ( .A(n1562), .B(intadd_27_B_0_), .C(intadd_27_CI),
.CO(intadd_27_n3), .S(intadd_27_SUM_0_) );
CMPR32X2TS intadd_27_U3 ( .A(intadd_27_A_1_), .B(intadd_27_B_1_), .C(
intadd_27_n3), .CO(intadd_27_n2), .S(intadd_27_SUM_1_) );
CMPR32X2TS intadd_27_U2 ( .A(intadd_27_A_2_), .B(n897), .C(intadd_27_n2),
.CO(intadd_27_n1), .S(intadd_27_SUM_2_) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_24_ ( .D(n838), .CK(clk), .RN(n1583),
.Q(intDX_EWSW[24]), .QN(n1571) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_14_ ( .D(n785), .CK(clk), .RN(n1586), .Q(
Data_array_SWR[14]), .QN(n1570) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_12_ ( .D(n783), .CK(clk), .RN(n1589), .Q(
Data_array_SWR[12]), .QN(n1569) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_23_ ( .D(n794), .CK(clk), .RN(n1584), .Q(
Data_array_SWR[23]), .QN(n1568) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_3_ ( .D(n539), .CK(clk), .RN(n1604), .Q(
Raw_mant_NRM_SWR[3]), .QN(n1561) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_18_ ( .D(n810), .CK(clk), .RN(n1590),
.Q(intDY_EWSW[18]), .QN(n1556) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_30_ ( .D(n798), .CK(clk), .RN(n1583),
.Q(intDY_EWSW[30]), .QN(n1554) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_23_ ( .D(n805), .CK(clk), .RN(n1586),
.Q(intDY_EWSW[23]), .QN(n1553) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_26_ ( .D(n802), .CK(clk), .RN(n1587),
.Q(intDY_EWSW[26]), .QN(n1551) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_20_ ( .D(n808), .CK(clk), .RN(n1587),
.Q(intDY_EWSW[20]), .QN(n1550) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_14_ ( .D(n814), .CK(clk), .RN(n1587),
.Q(intDY_EWSW[14]), .QN(n1548) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_12_ ( .D(n816), .CK(clk), .RN(n1590),
.Q(intDY_EWSW[12]), .QN(n1547) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_8_ ( .D(n820), .CK(clk), .RN(n1591), .Q(
intDY_EWSW[8]), .QN(n1544) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_1_ ( .D(n827), .CK(clk), .RN(n1583), .Q(
intDY_EWSW[1]), .QN(n1543) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_21_ ( .D(n807), .CK(clk), .RN(n876), .Q(
intDY_EWSW[21]), .QN(n1542) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_13_ ( .D(n815), .CK(clk), .RN(n876), .Q(
intDY_EWSW[13]), .QN(n1541) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_3_ ( .D(n825), .CK(clk), .RN(n1586), .Q(
intDY_EWSW[3]), .QN(n1539) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_6_ ( .D(n856), .CK(clk), .RN(n1585), .Q(
intDX_EWSW[6]), .QN(n1524) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_16_ ( .D(n846), .CK(clk), .RN(n1584),
.Q(intDX_EWSW[16]), .QN(n1523) );
DFFRX2TS SHT2_STAGE_SHFTVARS1_Q_reg_4_ ( .D(n767), .CK(clk), .RN(n1590), .Q(
shift_value_SHT2_EWR[4]), .QN(n1521) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_5_ ( .D(n857), .CK(clk), .RN(n1583), .Q(
intDX_EWSW[5]), .QN(n1518) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_25_ ( .D(n837), .CK(clk), .RN(n1585),
.Q(intDX_EWSW[25]), .QN(n1511) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_29_ ( .D(n799), .CK(clk), .RN(n1593),
.Q(intDY_EWSW[29]), .QN(n1505) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_22_ ( .D(n806), .CK(clk), .RN(n1589),
.Q(intDY_EWSW[22]), .QN(n1504) );
DFFRX2TS inst_FSM_INPUT_ENABLE_state_reg_reg_1_ ( .D(
inst_FSM_INPUT_ENABLE_state_next_1_), .CK(clk), .RN(n1585), .Q(
inst_FSM_INPUT_ENABLE_state_reg[1]), .QN(n1501) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_7_ ( .D(n855), .CK(clk), .RN(n1588), .Q(
intDX_EWSW[7]), .QN(n1500) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_4_ ( .D(n858), .CK(clk), .RN(n1595), .Q(
intDX_EWSW[4]), .QN(n1499) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_11_ ( .D(n531), .CK(clk), .RN(n925), .Q(
Raw_mant_NRM_SWR[11]), .QN(n1486) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_25_ ( .D(n803), .CK(clk), .RN(n1586),
.Q(intDY_EWSW[25]), .QN(n1614) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_15_ ( .D(n813), .CK(clk), .RN(n1591),
.Q(intDY_EWSW[15]), .QN(n1613) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_11_ ( .D(n817), .CK(clk), .RN(n1589),
.Q(intDY_EWSW[11]), .QN(n1612) );
DFFRX1TS SFT2FRMT_STAGE_VARS_Q_reg_7_ ( .D(n611), .CK(clk), .RN(n925), .Q(
DMP_exp_NRM2_EW[7]), .QN(n1564) );
DFFRX1TS SFT2FRMT_STAGE_VARS_Q_reg_6_ ( .D(n616), .CK(clk), .RN(n1607), .Q(
DMP_exp_NRM2_EW[6]), .QN(n1557) );
DFFRX1TS SFT2FRMT_STAGE_VARS_Q_reg_5_ ( .D(n621), .CK(clk), .RN(n1597), .Q(
DMP_exp_NRM2_EW[5]), .QN(n1536) );
DFFRX1TS SFT2FRMT_STAGE_VARS_Q_reg_0_ ( .D(n646), .CK(clk), .RN(n1597), .Q(
DMP_exp_NRM2_EW[0]), .QN(n1519) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_1_ ( .D(n541), .CK(clk), .RN(n1603), .Q(
Raw_mant_NRM_SWR[1]), .QN(n1567) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_0_ ( .D(n542), .CK(clk), .RN(n893), .Q(
Raw_mant_NRM_SWR[0]), .QN(n1489) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_2_ ( .D(n540), .CK(clk), .RN(n1594), .Q(
Raw_mant_NRM_SWR[2]), .QN(n1515) );
DFFRX1TS SGF_STAGE_FLAGS_Q_reg_1_ ( .D(n549), .CK(clk), .RN(n1606), .Q(
OP_FLAG_SFG), .QN(n1498) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_5_ ( .D(n537), .CK(clk), .RN(n1597), .Q(
Raw_mant_NRM_SWR[5]), .QN(n1522) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_8_ ( .D(n534), .CK(clk), .RN(n1604), .Q(
Raw_mant_NRM_SWR[8]), .QN(n1490) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_6_ ( .D(n536), .CK(clk), .RN(n1609), .Q(
Raw_mant_NRM_SWR[6]), .QN(n1493) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_7_ ( .D(n535), .CK(clk), .RN(n893), .Q(
Raw_mant_NRM_SWR[7]), .QN(n1488) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_9_ ( .D(n533), .CK(clk), .RN(n893), .Q(
Raw_mant_NRM_SWR[9]), .QN(n1492) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_13_ ( .D(n529), .CK(clk), .RN(n876), .Q(
Raw_mant_NRM_SWR[13]), .QN(n1509) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_10_ ( .D(n532), .CK(clk), .RN(n1594), .Q(
Raw_mant_NRM_SWR[10]), .QN(n1487) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_14_ ( .D(n528), .CK(clk), .RN(n876), .Q(
Raw_mant_NRM_SWR[14]), .QN(n1497) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_15_ ( .D(n527), .CK(clk), .RN(n1602), .Q(
Raw_mant_NRM_SWR[15]), .QN(n1496) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_16_ ( .D(n526), .CK(clk), .RN(n1597), .Q(
Raw_mant_NRM_SWR[16]), .QN(n1485) );
DFFRX1TS inst_FSM_INPUT_ENABLE_state_reg_reg_0_ ( .D(n870), .CK(clk), .RN(
n1588), .Q(inst_FSM_INPUT_ENABLE_state_reg[0]), .QN(n1535) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_17_ ( .D(n525), .CK(clk), .RN(n1598), .Q(
Raw_mant_NRM_SWR[17]), .QN(n1514) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_19_ ( .D(n809), .CK(clk), .RN(n1587),
.Q(intDY_EWSW[19]), .QN(n1506) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_27_ ( .D(n801), .CK(clk), .RN(n1582),
.Q(intDY_EWSW[27]), .QN(n1555) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_24_ ( .D(n804), .CK(clk), .RN(n1586),
.Q(intDY_EWSW[24]), .QN(n1491) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_16_ ( .D(n812), .CK(clk), .RN(n1591),
.Q(intDY_EWSW[16]), .QN(n1549) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_9_ ( .D(n819), .CK(clk), .RN(n1591), .Q(
intDY_EWSW[9]), .QN(n1540) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_6_ ( .D(n822), .CK(clk), .RN(n1590), .Q(
intDY_EWSW[6]), .QN(n1533) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_28_ ( .D(n800), .CK(clk), .RN(n1584),
.Q(intDY_EWSW[28]), .QN(n1552) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_0_ ( .D(n828), .CK(clk), .RN(n1585), .Q(
intDY_EWSW[0]), .QN(n1503) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_2_ ( .D(n826), .CK(clk), .RN(n1588), .Q(
intDY_EWSW[2]), .QN(n1545) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_4_ ( .D(n824), .CK(clk), .RN(n1589), .Q(
intDY_EWSW[4]), .QN(n1546) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_7_ ( .D(n821), .CK(clk), .RN(n1587), .Q(
intDY_EWSW[7]), .QN(n1534) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_5_ ( .D(n823), .CK(clk), .RN(n876), .Q(
intDY_EWSW[5]), .QN(n1502) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_26_ ( .D(n836), .CK(clk), .RN(n1582),
.Q(intDX_EWSW[26]), .QN(n1575) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_28_ ( .D(n834), .CK(clk), .RN(n1584),
.Q(intDX_EWSW[28]), .QN(n1529) );
DFFRX1TS EXP_STAGE_DmP_Q_reg_26_ ( .D(n561), .CK(clk), .RN(n876), .Q(
DmP_EXP_EWSW[26]), .QN(n1510) );
DFFRX1TS EXP_STAGE_DmP_Q_reg_24_ ( .D(n563), .CK(clk), .RN(n1602), .Q(
DmP_EXP_EWSW[24]), .QN(n1507) );
DFFRX1TS EXP_STAGE_DmP_Q_reg_25_ ( .D(n562), .CK(clk), .RN(n1605), .Q(
DmP_EXP_EWSW[25]), .QN(n1572) );
DFFRX1TS EXP_STAGE_DMP_Q_reg_25_ ( .D(n728), .CK(clk), .RN(n1599), .Q(
DMP_EXP_EWSW[25]), .QN(n1560) );
DFFRX1TS EXP_STAGE_DMP_Q_reg_26_ ( .D(n727), .CK(clk), .RN(n1599), .Q(
DMP_EXP_EWSW[26]), .QN(n1512) );
DFFRX1TS EXP_STAGE_DMP_Q_reg_24_ ( .D(n729), .CK(clk), .RN(n1595), .Q(
DMP_EXP_EWSW[24]), .QN(n1508) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_21_ ( .D(n521), .CK(clk), .RN(n1605), .Q(
Raw_mant_NRM_SWR[21]), .QN(n1517) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_22_ ( .D(n520), .CK(clk), .RN(n1605), .Q(
Raw_mant_NRM_SWR[22]), .QN(n1513) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_23_ ( .D(n519), .CK(clk), .RN(n876), .Q(
Raw_mant_NRM_SWR[23]), .QN(n1483) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_24_ ( .D(n518), .CK(clk), .RN(n1585), .Q(
Raw_mant_NRM_SWR[24]), .QN(n1484) );
DFFRX1TS SHT2_STAGE_SHFTVARS1_Q_reg_3_ ( .D(n769), .CK(clk), .RN(n1596), .Q(
shift_value_SHT2_EWR[3]), .QN(n1516) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_25_ ( .D(n517), .CK(clk), .RN(n1598), .Q(
Raw_mant_NRM_SWR[25]), .QN(n1495) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_10_ ( .D(n781), .CK(clk), .RN(n1587), .Q(
Data_array_SWR[10]), .QN(n1576) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_16_ ( .D(n669), .CK(clk), .RN(n1595), .Q(
DMP_SFG[16]), .QN(n1559) );
DFFRXLTS SFT2FRMT_STAGE_VARS_Q_reg_11_ ( .D(n516), .CK(clk), .RN(n1609), .Q(
LZD_output_NRM2_EW[3]), .QN(n1532) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_3_ ( .D(n859), .CK(clk), .RN(n1582), .Q(
intDX_EWSW[3]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_15_ ( .D(n847), .CK(clk), .RN(n1588),
.Q(intDX_EWSW[15]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_21_ ( .D(n841), .CK(clk), .RN(n1582),
.Q(intDX_EWSW[21]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_13_ ( .D(n849), .CK(clk), .RN(n1584),
.Q(intDX_EWSW[13]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_23_ ( .D(n839), .CK(clk), .RN(n1585),
.Q(intDX_EWSW[23]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_22_ ( .D(n793), .CK(clk), .RN(n1585), .Q(
Data_array_SWR[22]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_25_ ( .D(n796), .CK(clk), .RN(n1588), .Q(
Data_array_SWR[25]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_24_ ( .D(n795), .CK(clk), .RN(n1582), .Q(
Data_array_SWR[24]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_20_ ( .D(n522), .CK(clk), .RN(n876), .Q(
Raw_mant_NRM_SWR[20]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_17_ ( .D(n845), .CK(clk), .RN(n1588),
.Q(intDX_EWSW[17]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_11_ ( .D(n851), .CK(clk), .RN(n1584),
.Q(intDX_EWSW[11]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_8_ ( .D(n854), .CK(clk), .RN(n1588), .Q(
intDX_EWSW[8]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_1_ ( .D(n861), .CK(clk), .RN(n1588), .Q(
intDX_EWSW[1]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_9_ ( .D(n853), .CK(clk), .RN(n1585), .Q(
intDX_EWSW[9]) );
DFFRX2TS SHT2_STAGE_SHFTVARS1_Q_reg_2_ ( .D(n770), .CK(clk), .RN(n1584), .Q(
shift_value_SHT2_EWR[2]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_15_ ( .D(n786), .CK(clk), .RN(n1589), .Q(
Data_array_SWR[15]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_13_ ( .D(n784), .CK(clk), .RN(n1591), .Q(
Data_array_SWR[13]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_12_ ( .D(n530), .CK(clk), .RN(n1602), .Q(
Raw_mant_NRM_SWR[12]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_19_ ( .D(n523), .CK(clk), .RN(n876), .Q(
Raw_mant_NRM_SWR[19]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_18_ ( .D(n844), .CK(clk), .RN(n1582),
.Q(intDX_EWSW[18]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_29_ ( .D(n833), .CK(clk), .RN(n1588),
.Q(intDX_EWSW[29]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_27_ ( .D(n835), .CK(clk), .RN(n1585),
.Q(intDX_EWSW[27]) );
DFFRX2TS inst_FSM_INPUT_ENABLE_state_reg_reg_2_ ( .D(n871), .CK(clk), .RN(
n1582), .Q(inst_FSM_INPUT_ENABLE_state_reg[2]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_8_ ( .D(n779), .CK(clk), .RN(n1587), .Q(
Data_array_SWR[8]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_19_ ( .D(n790), .CK(clk), .RN(n1586), .Q(
Data_array_SWR[19]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_16_ ( .D(n787), .CK(clk), .RN(n1591), .Q(
Data_array_SWR[16]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_4_ ( .D(n538), .CK(clk), .RN(n1609), .Q(
Raw_mant_NRM_SWR[4]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_18_ ( .D(n524), .CK(clk), .RN(n1605), .Q(
Raw_mant_NRM_SWR[18]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_6_ ( .D(n777), .CK(clk), .RN(n1590), .Q(
Data_array_SWR[6]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_7_ ( .D(n778), .CK(clk), .RN(n1589), .Q(
Data_array_SWR[7]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_4_ ( .D(n775), .CK(clk), .RN(n876), .Q(
Data_array_SWR[4]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_5_ ( .D(n776), .CK(clk), .RN(n1587), .Q(
Data_array_SWR[5]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_9_ ( .D(n690), .CK(clk), .RN(n1594), .Q(
DMP_SFG[9]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_5_ ( .D(n702), .CK(clk), .RN(n893), .Q(
DMP_SFG[5]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_1_ ( .D(n714), .CK(clk), .RN(n1592), .Q(
DMP_SFG[1]) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_31_ ( .D(n831), .CK(clk), .RN(n1584),
.Q(intDX_EWSW[31]) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_10_ ( .D(n818), .CK(clk), .RN(n1589),
.Q(intDY_EWSW[10]), .QN(n879) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_7_ ( .D(n595), .CK(clk), .RN(n925), .Q(
DmP_mant_SHT1_SW[7]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_3_ ( .D(n603), .CK(clk), .RN(n1603), .Q(
DmP_mant_SHT1_SW[3]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_20_ ( .D(n569), .CK(clk), .RN(n876), .Q(
DmP_mant_SHT1_SW[20]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_17_ ( .D(n575), .CK(clk), .RN(n1602), .Q(
DmP_mant_SHT1_SW[17]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_16_ ( .D(n577), .CK(clk), .RN(n1584), .Q(
DmP_mant_SHT1_SW[16]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_21_ ( .D(n567), .CK(clk), .RN(n1583), .Q(
DmP_mant_SHT1_SW[21]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_8_ ( .D(n593), .CK(clk), .RN(n1600), .Q(
DmP_mant_SHT1_SW[8]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_13_ ( .D(n583), .CK(clk), .RN(n1603), .Q(
DmP_mant_SHT1_SW[13]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_14_ ( .D(n581), .CK(clk), .RN(n1600), .Q(
DmP_mant_SHT1_SW[14]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_10_ ( .D(n589), .CK(clk), .RN(n1601), .Q(
DmP_mant_SHT1_SW[10]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_18_ ( .D(n573), .CK(clk), .RN(n1598), .Q(
DmP_mant_SHT1_SW[18]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_12_ ( .D(n585), .CK(clk), .RN(n925), .Q(
DmP_mant_SHT1_SW[12]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_15_ ( .D(n579), .CK(clk), .RN(n1605), .Q(
DmP_mant_SHT1_SW[15]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_6_ ( .D(n597), .CK(clk), .RN(n1601), .Q(
DmP_mant_SHT1_SW[6]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_2_ ( .D(n605), .CK(clk), .RN(n1595), .Q(
DmP_mant_SHT1_SW[2]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_1_ ( .D(n607), .CK(clk), .RN(n1596), .Q(
DmP_mant_SHT1_SW[1]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_0_ ( .D(n609), .CK(clk), .RN(n1593), .Q(
DmP_mant_SHT1_SW[0]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_0_ ( .D(n717), .CK(clk), .RN(n1608), .Q(
DMP_SFG[0]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_11_ ( .D(n477), .CK(clk), .RN(n876), .Q(
DmP_mant_SFG_SWR[11]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_10_ ( .D(n478), .CK(clk), .RN(n1607), .Q(
DmP_mant_SFG_SWR[10]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_15_ ( .D(n473), .CK(clk), .RN(n1608), .Q(
DmP_mant_SFG_SWR[15]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_14_ ( .D(n474), .CK(clk), .RN(n1595), .Q(
DmP_mant_SFG_SWR[14]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_13_ ( .D(n475), .CK(clk), .RN(n1596), .Q(
DmP_mant_SFG_SWR[13]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_12_ ( .D(n476), .CK(clk), .RN(n1592), .Q(
DmP_mant_SFG_SWR[12]) );
DFFRX1TS SHT1_STAGE_sft_amount_Q_reg_0_ ( .D(n766), .CK(clk), .RN(n1586),
.Q(Shift_amount_SHT1_EWR[0]) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_17_ ( .D(n811), .CK(clk), .RN(n1591),
.Q(intDY_EWSW[17]), .QN(n1581) );
DFFRX1TS EXP_STAGE_DMP_Q_reg_23_ ( .D(n730), .CK(clk), .RN(n1599), .Q(
DMP_EXP_EWSW[23]) );
DFFRX1TS SFT2FRMT_STAGE_VARS_Q_reg_4_ ( .D(n626), .CK(clk), .RN(n1607), .Q(
DMP_exp_NRM2_EW[4]) );
DFFRX1TS SFT2FRMT_STAGE_VARS_Q_reg_3_ ( .D(n631), .CK(clk), .RN(n1604), .Q(
DMP_exp_NRM2_EW[3]) );
DFFRX1TS SFT2FRMT_STAGE_VARS_Q_reg_2_ ( .D(n636), .CK(clk), .RN(n1609), .Q(
DMP_exp_NRM2_EW[2]) );
DFFRX1TS SFT2FRMT_STAGE_VARS_Q_reg_1_ ( .D(n641), .CK(clk), .RN(n893), .Q(
DMP_exp_NRM2_EW[1]) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_31_ ( .D(n797), .CK(clk), .RN(n1583),
.Q(intDY_EWSW[31]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_12_ ( .D(n850), .CK(clk), .RN(n1582),
.Q(intDX_EWSW[12]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_20_ ( .D(n842), .CK(clk), .RN(n1584),
.Q(intDX_EWSW[20]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_14_ ( .D(n848), .CK(clk), .RN(n1583),
.Q(intDX_EWSW[14]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_22_ ( .D(n840), .CK(clk), .RN(n1583),
.Q(intDX_EWSW[22]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_2_ ( .D(n860), .CK(clk), .RN(n1583), .Q(
intDX_EWSW[2]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_10_ ( .D(n852), .CK(clk), .RN(n1585),
.Q(intDX_EWSW[10]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_30_ ( .D(n832), .CK(clk), .RN(n1582),
.Q(intDX_EWSW[30]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_19_ ( .D(n843), .CK(clk), .RN(n1584),
.Q(intDX_EWSW[19]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_9_ ( .D(n780), .CK(clk), .RN(n1590), .Q(
Data_array_SWR[9]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_11_ ( .D(n782), .CK(clk), .RN(n1590), .Q(
Data_array_SWR[11]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_21_ ( .D(n792), .CK(clk), .RN(n1588), .Q(
Data_array_SWR[21]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_18_ ( .D(n789), .CK(clk), .RN(n876), .Q(
Data_array_SWR[18]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_17_ ( .D(n788), .CK(clk), .RN(n1587), .Q(
Data_array_SWR[17]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_20_ ( .D(n791), .CK(clk), .RN(n1587), .Q(
Data_array_SWR[20]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_22_ ( .D(n565), .CK(clk), .RN(n1598), .Q(
DmP_mant_SHT1_SW[22]) );
DFFRX1TS INPUT_STAGE_FLAGS_Q_reg_0_ ( .D(n830), .CK(clk), .RN(n1584), .Q(
intAS) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_3_ ( .D(n774), .CK(clk), .RN(n1586), .Q(
Data_array_SWR[3]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_2_ ( .D(n773), .CK(clk), .RN(n1590), .Q(
Data_array_SWR[2]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_1_ ( .D(n772), .CK(clk), .RN(n1591), .Q(
Data_array_SWR[1]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_0_ ( .D(n771), .CK(clk), .RN(n1589), .Q(
Data_array_SWR[0]) );
DFFRX1TS EXP_STAGE_DmP_Q_reg_27_ ( .D(n560), .CK(clk), .RN(n1605), .Q(
DmP_EXP_EWSW[27]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_14_ ( .D(n675), .CK(clk), .RN(n1599), .Q(
DMP_SFG[14]), .QN(n1530) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_12_ ( .D(n681), .CK(clk), .RN(n1595), .Q(
DMP_SFG[12]), .QN(n1525) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_2_ ( .D(n711), .CK(clk), .RN(n1605), .Q(
DMP_SFG[2]), .QN(n1562) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_18_ ( .D(n663), .CK(clk), .RN(n1593), .Q(
DMP_SFG[18]), .QN(n1566) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_10_ ( .D(n687), .CK(clk), .RN(n1600), .Q(
DMP_SFG[10]), .QN(n1520) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_19_ ( .D(n660), .CK(clk), .RN(n1594), .Q(
DMP_SFG[19]), .QN(n1565) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_17_ ( .D(n666), .CK(clk), .RN(n1596), .Q(
DMP_SFG[17]), .QN(n1558) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_15_ ( .D(n672), .CK(clk), .RN(n1599), .Q(
DMP_SFG[15]), .QN(n1537) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_13_ ( .D(n678), .CK(clk), .RN(n1599), .Q(
DMP_SFG[13]), .QN(n1531) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_11_ ( .D(n684), .CK(clk), .RN(n1593), .Q(
DMP_SFG[11]), .QN(n1526) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_6_ ( .D(n699), .CK(clk), .RN(n1594), .Q(
DMP_SFG[6]), .QN(n1563) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_22_ ( .D(n651), .CK(clk), .RN(n1594), .Q(
DMP_SFG[22]), .QN(n1578) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_21_ ( .D(n654), .CK(clk), .RN(n1597), .Q(
DMP_SFG[21]), .QN(n1573) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_20_ ( .D(n657), .CK(clk), .RN(n925), .Q(
DMP_SFG[20]), .QN(n1574) );
DFFRXLTS SFT2FRMT_STAGE_VARS_Q_reg_10_ ( .D(n514), .CK(clk), .RN(n1597), .Q(
LZD_output_NRM2_EW[2]), .QN(n1528) );
DFFRXLTS SFT2FRMT_STAGE_VARS_Q_reg_12_ ( .D(n512), .CK(clk), .RN(n1604), .Q(
LZD_output_NRM2_EW[4]), .QN(n1538) );
DFFRXLTS SFT2FRMT_STAGE_VARS_Q_reg_9_ ( .D(n513), .CK(clk), .RN(n1609), .Q(
LZD_output_NRM2_EW[1]), .QN(n1527) );
DFFRX2TS inst_ShiftRegister_Q_reg_5_ ( .D(n868), .CK(clk), .RN(n1583), .Q(
n1494), .QN(n1577) );
ADDFX1TS DP_OP_15J30_123_3372_U8 ( .A(n1527), .B(DMP_exp_NRM2_EW[1]), .CI(
DP_OP_15J30_123_3372_n8), .CO(DP_OP_15J30_123_3372_n7), .S(
exp_rslt_NRM2_EW1[1]) );
ADDFX1TS DP_OP_15J30_123_3372_U7 ( .A(n1528), .B(DMP_exp_NRM2_EW[2]), .CI(
DP_OP_15J30_123_3372_n7), .CO(DP_OP_15J30_123_3372_n6), .S(
exp_rslt_NRM2_EW1[2]) );
ADDFX1TS DP_OP_15J30_123_3372_U6 ( .A(n1532), .B(DMP_exp_NRM2_EW[3]), .CI(
DP_OP_15J30_123_3372_n6), .CO(DP_OP_15J30_123_3372_n5), .S(
exp_rslt_NRM2_EW1[3]) );
ADDFX1TS DP_OP_15J30_123_3372_U5 ( .A(n1538), .B(DMP_exp_NRM2_EW[4]), .CI(
DP_OP_15J30_123_3372_n5), .CO(DP_OP_15J30_123_3372_n4), .S(
exp_rslt_NRM2_EW1[4]) );
DFFRX4TS inst_ShiftRegister_Q_reg_1_ ( .D(n864), .CK(clk), .RN(n1582), .Q(
Shift_reg_FLAGS_7[1]), .QN(n874) );
DFFRX4TS inst_ShiftRegister_Q_reg_4_ ( .D(n867), .CK(clk), .RN(n1585), .Q(
n873), .QN(n1579) );
DFFRX4TS inst_ShiftRegister_Q_reg_6_ ( .D(n869), .CK(clk), .RN(n1585), .Q(
Shift_reg_FLAGS_7_6), .QN(n877) );
DFFRX4TS inst_ShiftRegister_Q_reg_0_ ( .D(n863), .CK(clk), .RN(n1593), .Q(
Shift_reg_FLAGS_7[0]), .QN(n872) );
DFFRX4TS inst_ShiftRegister_Q_reg_2_ ( .D(n865), .CK(clk), .RN(n1582), .Q(
n924), .QN(n1610) );
NAND2X4TS U897 ( .A(n898), .B(n1423), .Y(n1324) );
NAND2X4TS U898 ( .A(n1161), .B(n1283), .Y(n1147) );
AOI222X4TS U899 ( .A0(Data_array_SWR[21]), .A1(n1404), .B0(
Data_array_SWR[17]), .B1(n1403), .C0(Data_array_SWR[25]), .C1(n1389),
.Y(n1426) );
NOR2X4TS U900 ( .A(n1161), .B(n1203), .Y(n1162) );
NAND2X4TS U901 ( .A(n1143), .B(n1299), .Y(n1142) );
AOI211X2TS U902 ( .A0(Raw_mant_NRM_SWR[6]), .A1(n1130), .B0(n1255), .C0(
n1129), .Y(n1144) );
INVX2TS U903 ( .A(n1135), .Y(n1137) );
OAI21XLTS U904 ( .A0(Raw_mant_NRM_SWR[6]), .A1(Raw_mant_NRM_SWR[7]), .B0(
n1113), .Y(n1114) );
CLKINVX6TS U905 ( .A(n1293), .Y(n1159) );
INVX3TS U906 ( .A(n1285), .Y(n906) );
NAND3X1TS U907 ( .A(n1115), .B(n1249), .C(Raw_mant_NRM_SWR[1]), .Y(n1243) );
NAND3X1TS U908 ( .A(n1136), .B(n1122), .C(n1244), .Y(n1255) );
OAI211X1TS U909 ( .A0(Raw_mant_NRM_SWR[4]), .A1(n1121), .B0(n1248), .C0(
n1522), .Y(n1122) );
BUFX4TS U910 ( .A(n1029), .Y(n896) );
NOR2X4TS U911 ( .A(n1009), .B(n1067), .Y(n1017) );
INVX4TS U912 ( .A(n1272), .Y(n875) );
AND2X4TS U913 ( .A(beg_OP), .B(n1266), .Y(n1270) );
NOR2X6TS U914 ( .A(n1438), .B(n1414), .Y(n1368) );
NOR2X6TS U915 ( .A(shift_value_SHT2_EWR[4]), .B(n1383), .Y(n1366) );
BUFX6TS U916 ( .A(n893), .Y(n876) );
CLKBUFX2TS U917 ( .A(n923), .Y(n891) );
CLKBUFX2TS U918 ( .A(n918), .Y(n892) );
NAND3X1TS U919 ( .A(n1514), .B(n1496), .C(n1485), .Y(n1241) );
CLKINVX6TS U920 ( .A(rst), .Y(n925) );
NAND2BXLTS U921 ( .AN(intDX_EWSW[2]), .B(intDY_EWSW[2]), .Y(n959) );
NAND2BXLTS U922 ( .AN(intDX_EWSW[19]), .B(intDY_EWSW[19]), .Y(n993) );
NAND2BXLTS U923 ( .AN(intDX_EWSW[27]), .B(intDY_EWSW[27]), .Y(n947) );
NAND2BXLTS U924 ( .AN(intDX_EWSW[9]), .B(intDY_EWSW[9]), .Y(n972) );
NAND2BXLTS U925 ( .AN(intDX_EWSW[13]), .B(intDY_EWSW[13]), .Y(n968) );
NAND2BXLTS U926 ( .AN(intDX_EWSW[21]), .B(intDY_EWSW[21]), .Y(n987) );
NAND3XLTS U927 ( .A(n1551), .B(n947), .C(intDX_EWSW[26]), .Y(n949) );
NAND3BXLTS U928 ( .AN(n991), .B(n989), .C(n988), .Y(n1007) );
INVX2TS U929 ( .A(n880), .Y(n897) );
AO22XLTS U930 ( .A0(DmP_mant_SFG_SWR[6]), .A1(n1358), .B0(n1354), .B1(n921),
.Y(n880) );
AOI222X4TS U931 ( .A0(Data_array_SWR[14]), .A1(n1366), .B0(
Data_array_SWR[22]), .B1(n1430), .C0(Data_array_SWR[18]), .C1(n1429),
.Y(n1379) );
AOI222X4TS U932 ( .A0(Data_array_SWR[23]), .A1(n1430), .B0(
Data_array_SWR[19]), .B1(n1429), .C0(Data_array_SWR[15]), .C1(n1366),
.Y(n1375) );
AOI222X4TS U933 ( .A0(Data_array_SWR[24]), .A1(n1430), .B0(
Data_array_SWR[20]), .B1(n1429), .C0(Data_array_SWR[16]), .C1(n1366),
.Y(n1371) );
AOI222X4TS U934 ( .A0(Data_array_SWR[21]), .A1(n1429), .B0(
Data_array_SWR[17]), .B1(n1366), .C0(Data_array_SWR[25]), .C1(n1430),
.Y(n1372) );
NAND2BXLTS U935 ( .AN(n1257), .B(n940), .Y(n942) );
OAI21XLTS U936 ( .A0(n1522), .A1(n1285), .B0(n1185), .Y(n1186) );
AOI222X1TS U937 ( .A0(Raw_mant_NRM_SWR[14]), .A1(n906), .B0(n910), .B1(n901),
.C0(n1282), .C1(DmP_mant_SHT1_SW[10]), .Y(n1218) );
AOI222X1TS U938 ( .A0(Raw_mant_NRM_SWR[20]), .A1(n906), .B0(n910), .B1(
DmP_mant_SHT1_SW[3]), .C0(n1282), .C1(n899), .Y(n1176) );
AOI222X1TS U939 ( .A0(Raw_mant_NRM_SWR[21]), .A1(n906), .B0(n910), .B1(
DmP_mant_SHT1_SW[2]), .C0(n1282), .C1(DmP_mant_SHT1_SW[3]), .Y(n1172)
);
AOI222X1TS U940 ( .A0(Raw_mant_NRM_SWR[16]), .A1(n906), .B0(n910), .B1(
DmP_mant_SHT1_SW[7]), .C0(n1282), .C1(DmP_mant_SHT1_SW[8]), .Y(n1179)
);
AOI222X1TS U941 ( .A0(n1228), .A1(DMP_SFG[1]), .B0(n1228), .B1(n894), .C0(
DMP_SFG[1]), .C1(n894), .Y(intadd_27_CI) );
AOI222X1TS U942 ( .A0(Raw_mant_NRM_SWR[17]), .A1(n906), .B0(n910), .B1(
DmP_mant_SHT1_SW[6]), .C0(n1282), .C1(DmP_mant_SHT1_SW[7]), .Y(n1200)
);
AOI222X1TS U943 ( .A0(Raw_mant_NRM_SWR[8]), .A1(n906), .B0(n910), .B1(
DmP_mant_SHT1_SW[15]), .C0(n1282), .C1(DmP_mant_SHT1_SW[16]), .Y(n1227) );
AOI211X1TS U944 ( .A0(DmP_mant_SHT1_SW[22]), .A1(n874), .B0(n1205), .C0(
n1204), .Y(n1276) );
NAND4XLTS U945 ( .A(n1245), .B(n1244), .C(n1243), .D(n1250), .Y(n1246) );
AO22XLTS U946 ( .A0(DmP_mant_SFG_SWR[7]), .A1(n1354), .B0(n1358), .B1(n922),
.Y(n882) );
OAI211XLTS U947 ( .A0(n1253), .A1(n1252), .B0(n1251), .C0(n1250), .Y(n1254)
);
OAI21XLTS U948 ( .A0(n1489), .A1(n1116), .B0(n1243), .Y(n1117) );
AO22XLTS U949 ( .A0(DmP_mant_SFG_SWR[3]), .A1(n1354), .B0(n1358), .B1(n916),
.Y(n881) );
OAI21XLTS U950 ( .A0(n1509), .A1(n1285), .B0(n1284), .Y(n1286) );
OAI21XLTS U951 ( .A0(n1492), .A1(n1285), .B0(n1189), .Y(n1190) );
OAI21XLTS U952 ( .A0(n1486), .A1(n1285), .B0(n1279), .Y(n1280) );
INVX4TS U953 ( .A(n1324), .Y(n1482) );
AOI222X1TS U954 ( .A0(n1391), .A1(n1478), .B0(Data_array_SWR[8]), .B1(n1368),
.C0(n1390), .C1(n1411), .Y(n1460) );
AOI222X1TS U955 ( .A0(n1391), .A1(n1438), .B0(Data_array_SWR[8]), .B1(n1479),
.C0(n1390), .C1(n1410), .Y(n1447) );
AOI222X1TS U956 ( .A0(n1386), .A1(n1478), .B0(Data_array_SWR[9]), .B1(n1368),
.C0(n1385), .C1(n1411), .Y(n1459) );
AOI222X1TS U957 ( .A0(n1386), .A1(n1438), .B0(Data_array_SWR[9]), .B1(n1479),
.C0(n1385), .C1(n1410), .Y(n1448) );
AO22XLTS U958 ( .A0(n1335), .A1(DmP_EXP_EWSW[22]), .B0(n1329), .B1(
DmP_mant_SHT1_SW[22]), .Y(n565) );
OAI21XLTS U959 ( .A0(n1197), .A1(n1142), .B0(n1196), .Y(n791) );
OAI211XLTS U960 ( .A0(n1227), .A1(n1142), .B0(n1226), .C0(n1225), .Y(n788)
);
OAI21XLTS U961 ( .A0(n1197), .A1(n1159), .B0(n1188), .Y(n789) );
OAI211XLTS U962 ( .A0(n1179), .A1(n1142), .B0(n1178), .C0(n1177), .Y(n780)
);
AOI2BB2XLTS U963 ( .B0(Raw_mant_NRM_SWR[15]), .B1(n1291), .A0N(n1218), .A1N(
n1159), .Y(n1177) );
AO22XLTS U964 ( .A0(n1269), .A1(Data_X[19]), .B0(n1274), .B1(intDX_EWSW[19]),
.Y(n843) );
AO22XLTS U965 ( .A0(n1270), .A1(Data_X[30]), .B0(n1267), .B1(intDX_EWSW[30]),
.Y(n832) );
AO22XLTS U966 ( .A0(n1275), .A1(Data_X[10]), .B0(n1274), .B1(intDX_EWSW[10]),
.Y(n852) );
AO22XLTS U967 ( .A0(n1275), .A1(Data_Y[31]), .B0(n875), .B1(intDY_EWSW[31]),
.Y(n797) );
AO22XLTS U968 ( .A0(n1455), .A1(DMP_SHT2_EWSW[0]), .B0(n1324), .B1(
DMP_SFG[0]), .Y(n717) );
AO22XLTS U969 ( .A0(n1494), .A1(DmP_EXP_EWSW[0]), .B0(n1336), .B1(
DmP_mant_SHT1_SW[0]), .Y(n609) );
AO22XLTS U970 ( .A0(n1494), .A1(DmP_EXP_EWSW[1]), .B0(n1329), .B1(
DmP_mant_SHT1_SW[1]), .Y(n607) );
AO22XLTS U971 ( .A0(n1494), .A1(DmP_EXP_EWSW[2]), .B0(n1329), .B1(
DmP_mant_SHT1_SW[2]), .Y(n605) );
AO22XLTS U972 ( .A0(n1494), .A1(DmP_EXP_EWSW[6]), .B0(n1327), .B1(
DmP_mant_SHT1_SW[6]), .Y(n597) );
AO22XLTS U973 ( .A0(n1335), .A1(DmP_EXP_EWSW[15]), .B0(n1329), .B1(
DmP_mant_SHT1_SW[15]), .Y(n579) );
AO22XLTS U974 ( .A0(n1335), .A1(DmP_EXP_EWSW[12]), .B0(n1329), .B1(
DmP_mant_SHT1_SW[12]), .Y(n585) );
AO22XLTS U975 ( .A0(n1335), .A1(DmP_EXP_EWSW[18]), .B0(n1329), .B1(
DmP_mant_SHT1_SW[18]), .Y(n573) );
AO22XLTS U976 ( .A0(n1335), .A1(DmP_EXP_EWSW[14]), .B0(n1329), .B1(
DmP_mant_SHT1_SW[14]), .Y(n581) );
AO22XLTS U977 ( .A0(n1335), .A1(DmP_EXP_EWSW[13]), .B0(n1329), .B1(
DmP_mant_SHT1_SW[13]), .Y(n583) );
AO22XLTS U978 ( .A0(n1494), .A1(DmP_EXP_EWSW[8]), .B0(n1329), .B1(
DmP_mant_SHT1_SW[8]), .Y(n593) );
AO22XLTS U979 ( .A0(n1335), .A1(DmP_EXP_EWSW[21]), .B0(n1329), .B1(
DmP_mant_SHT1_SW[21]), .Y(n567) );
AO22XLTS U980 ( .A0(n1335), .A1(DmP_EXP_EWSW[16]), .B0(n1329), .B1(
DmP_mant_SHT1_SW[16]), .Y(n577) );
AO22XLTS U981 ( .A0(n1335), .A1(DmP_EXP_EWSW[17]), .B0(n1329), .B1(
DmP_mant_SHT1_SW[17]), .Y(n575) );
AO22XLTS U982 ( .A0(n1335), .A1(DmP_EXP_EWSW[20]), .B0(n1329), .B1(
DmP_mant_SHT1_SW[20]), .Y(n569) );
AO22XLTS U983 ( .A0(n1275), .A1(Data_X[31]), .B0(n1273), .B1(intDX_EWSW[31]),
.Y(n831) );
AO22XLTS U984 ( .A0(n1455), .A1(DMP_SHT2_EWSW[1]), .B0(n1324), .B1(
DMP_SFG[1]), .Y(n714) );
OAI211XLTS U985 ( .A0(n1172), .A1(n1142), .B0(n1154), .C0(n1153), .Y(n775)
);
OAI211XLTS U986 ( .A0(n1179), .A1(n1159), .B0(n1164), .C0(n1163), .Y(n778)
);
OAI211XLTS U987 ( .A0(n1200), .A1(n1159), .B0(n1167), .C0(n1166), .Y(n777)
);
OAI211XLTS U988 ( .A0(n1223), .A1(n1142), .B0(n1221), .C0(n1220), .Y(n790)
);
OAI21XLTS U989 ( .A0(n1289), .A1(n1159), .B0(n1202), .Y(n779) );
AO22XLTS U990 ( .A0(n1275), .A1(Data_X[27]), .B0(n875), .B1(intDX_EWSW[27]),
.Y(n835) );
AO22XLTS U991 ( .A0(n1269), .A1(Data_X[29]), .B0(n875), .B1(intDX_EWSW[29]),
.Y(n833) );
AO22XLTS U992 ( .A0(n1272), .A1(Data_X[18]), .B0(n875), .B1(intDX_EWSW[18]),
.Y(n844) );
OAI211XLTS U993 ( .A0(n1213), .A1(n1142), .B0(n1212), .C0(n1211), .Y(n786)
);
AOI32X1TS U994 ( .A0(Shift_amount_SHT1_EWR[2]), .A1(n1299), .A2(n874), .B0(
shift_value_SHT2_EWR[2]), .B1(n1296), .Y(n1298) );
AO22XLTS U995 ( .A0(n1271), .A1(Data_X[1]), .B0(n875), .B1(intDX_EWSW[1]),
.Y(n861) );
OAI21XLTS U996 ( .A0(n1515), .A1(n1147), .B0(n1208), .Y(n793) );
AOI2BB1XLTS U997 ( .A0N(Shift_reg_FLAGS_7[1]), .A1N(LZD_output_NRM2_EW[3]),
.B0(n1301), .Y(n516) );
AO22XLTS U998 ( .A0(n1264), .A1(n1353), .B0(n1265), .B1(n898), .Y(n865) );
OAI211XLTS U999 ( .A0(n1299), .A1(n1521), .B0(n1239), .C0(n1119), .Y(n767)
);
AO22XLTS U1000 ( .A0(n1335), .A1(DmP_EXP_EWSW[19]), .B0(n1329), .B1(n900),
.Y(n571) );
AO22XLTS U1001 ( .A0(n1335), .A1(DmP_EXP_EWSW[9]), .B0(n1327), .B1(n901),
.Y(n591) );
AO22XLTS U1002 ( .A0(n1494), .A1(DmP_EXP_EWSW[5]), .B0(n1329), .B1(n903),
.Y(n599) );
AO22XLTS U1003 ( .A0(n1494), .A1(DmP_EXP_EWSW[4]), .B0(n1329), .B1(n899),
.Y(n601) );
OAI21XLTS U1004 ( .A0(n1109), .A1(n1067), .B0(n1106), .Y(n1107) );
AO22XLTS U1005 ( .A0(n1271), .A1(Data_X[0]), .B0(n1274), .B1(n911), .Y(n862)
);
AO22XLTS U1006 ( .A0(n1265), .A1(busy), .B0(n1264), .B1(n898), .Y(n866) );
OR2X1TS U1007 ( .A(Shift_reg_FLAGS_7[1]), .B(Shift_amount_SHT1_EWR[0]), .Y(
n883) );
OAI211XLTS U1008 ( .A0(n1150), .A1(n1142), .B0(n1149), .C0(n1148), .Y(n772)
);
OAI211XLTS U1009 ( .A0(n1172), .A1(n1159), .B0(n1171), .C0(n1170), .Y(n773)
);
OAI211XLTS U1010 ( .A0(n1176), .A1(n1159), .B0(n1175), .C0(n1174), .Y(n774)
);
BUFX4TS U1011 ( .A(n925), .Y(n1603) );
BUFX4TS U1012 ( .A(n925), .Y(n1607) );
NOR2BX2TS U1013 ( .AN(n1253), .B(n1252), .Y(n1126) );
NOR2X2TS U1014 ( .A(Raw_mant_NRM_SWR[6]), .B(n1120), .Y(n1248) );
BUFX6TS U1015 ( .A(n1594), .Y(n1605) );
BUFX4TS U1016 ( .A(n1324), .Y(n1480) );
BUFX3TS U1017 ( .A(n1577), .Y(n1328) );
OAI211XLTS U1018 ( .A0(n950), .A1(n1072), .B0(n949), .C0(n948), .Y(n955) );
OAI21X2TS U1019 ( .A0(intDX_EWSW[26]), .A1(n1551), .B0(n947), .Y(n1072) );
BUFX4TS U1020 ( .A(n1602), .Y(n1593) );
BUFX4TS U1021 ( .A(n1586), .Y(n1595) );
BUFX4TS U1022 ( .A(n1598), .Y(n1596) );
BUFX4TS U1023 ( .A(n1605), .Y(n1599) );
BUFX3TS U1024 ( .A(n1603), .Y(n893) );
BUFX4TS U1025 ( .A(n925), .Y(n1597) );
BUFX4TS U1026 ( .A(n1607), .Y(n1594) );
BUFX4TS U1027 ( .A(n1587), .Y(n1584) );
INVX2TS U1028 ( .A(n881), .Y(n894) );
INVX2TS U1029 ( .A(n882), .Y(n895) );
NOR2X2TS U1030 ( .A(Raw_mant_NRM_SWR[13]), .B(n1242), .Y(n1135) );
BUFX4TS U1031 ( .A(n1591), .Y(n1582) );
BUFX4TS U1032 ( .A(n1590), .Y(n1588) );
BUFX4TS U1033 ( .A(n1589), .Y(n1585) );
BUFX4TS U1034 ( .A(n1587), .Y(n1583) );
XNOR2X2TS U1035 ( .A(DMP_exp_NRM2_EW[7]), .B(n931), .Y(n941) );
XNOR2X2TS U1036 ( .A(DMP_exp_NRM2_EW[5]), .B(DP_OP_15J30_123_3372_n4), .Y(
n944) );
NOR2X4TS U1037 ( .A(shift_value_SHT2_EWR[4]), .B(n1478), .Y(n1411) );
BUFX6TS U1038 ( .A(left_right_SHT2), .Y(n1478) );
BUFX4TS U1039 ( .A(n1012), .Y(n1321) );
INVX2TS U1040 ( .A(n884), .Y(n898) );
INVX2TS U1041 ( .A(n889), .Y(n899) );
INVX2TS U1042 ( .A(n888), .Y(n900) );
INVX2TS U1043 ( .A(n890), .Y(n901) );
INVX2TS U1044 ( .A(n887), .Y(n902) );
INVX2TS U1045 ( .A(n886), .Y(n903) );
INVX2TS U1046 ( .A(n885), .Y(n904) );
NOR4BX2TS U1047 ( .AN(n1141), .B(n1140), .C(n1139), .D(n1138), .Y(n1161) );
INVX2TS U1048 ( .A(n1285), .Y(n905) );
BUFX4TS U1049 ( .A(n1367), .Y(n1479) );
BUFX4TS U1050 ( .A(n1365), .Y(n1429) );
BUFX4TS U1051 ( .A(n1067), .Y(n1263) );
INVX2TS U1052 ( .A(n1142), .Y(n907) );
INVX2TS U1053 ( .A(n907), .Y(n908) );
CLKINVX3TS U1054 ( .A(n883), .Y(n909) );
INVX3TS U1055 ( .A(n883), .Y(n910) );
INVX3TS U1056 ( .A(n1359), .Y(n1358) );
CLKINVX3TS U1057 ( .A(n1324), .Y(n1476) );
AOI222X4TS U1058 ( .A0(Data_array_SWR[24]), .A1(n1389), .B0(
Data_array_SWR[20]), .B1(n1404), .C0(Data_array_SWR[16]), .C1(n1403),
.Y(n1434) );
OAI211XLTS U1059 ( .A0(n1218), .A1(n908), .B0(n1217), .C0(n1216), .Y(n782)
);
AOI32X1TS U1060 ( .A0(n1556), .A1(n993), .A2(intDX_EWSW[18]), .B0(
intDX_EWSW[19]), .B1(n1506), .Y(n994) );
AOI221X1TS U1061 ( .A0(n1556), .A1(intDX_EWSW[18]), .B0(intDX_EWSW[19]),
.B1(n1506), .C0(n1079), .Y(n1084) );
AOI221X1TS U1062 ( .A0(n1554), .A1(intDX_EWSW[30]), .B0(intDX_EWSW[17]),
.B1(n1581), .C0(n1078), .Y(n1085) );
AOI221X4TS U1063 ( .A0(intDX_EWSW[30]), .A1(n1554), .B0(intDX_EWSW[29]),
.B1(n1505), .C0(n952), .Y(n954) );
INVX2TS U1064 ( .A(n878), .Y(n911) );
AOI221X1TS U1065 ( .A0(n879), .A1(intDX_EWSW[10]), .B0(intDX_EWSW[11]), .B1(
n1612), .C0(n1087), .Y(n1092) );
AOI221X1TS U1066 ( .A0(n1545), .A1(intDX_EWSW[2]), .B0(intDX_EWSW[3]), .B1(
n1539), .C0(n1095), .Y(n1100) );
AOI221X1TS U1067 ( .A0(n1504), .A1(intDX_EWSW[22]), .B0(intDX_EWSW[23]),
.B1(n1553), .C0(n1081), .Y(n1082) );
AOI221X1TS U1068 ( .A0(n1548), .A1(intDX_EWSW[14]), .B0(intDX_EWSW[15]),
.B1(n1613), .C0(n1089), .Y(n1090) );
OAI211X2TS U1069 ( .A0(intDX_EWSW[20]), .A1(n1550), .B0(n1001), .C0(n987),
.Y(n996) );
AOI221X1TS U1070 ( .A0(n1550), .A1(intDX_EWSW[20]), .B0(intDX_EWSW[21]),
.B1(n1542), .C0(n1080), .Y(n1083) );
OAI211X2TS U1071 ( .A0(intDX_EWSW[12]), .A1(n1547), .B0(n982), .C0(n968),
.Y(n984) );
AOI221X1TS U1072 ( .A0(n1547), .A1(intDX_EWSW[12]), .B0(intDX_EWSW[13]),
.B1(n1541), .C0(n1088), .Y(n1091) );
INVX1TS U1073 ( .A(DMP_SFG[3]), .Y(intadd_27_A_1_) );
INVX1TS U1074 ( .A(DMP_SFG[4]), .Y(intadd_27_A_2_) );
INVX1TS U1075 ( .A(DMP_SFG[7]), .Y(intadd_26_A_1_) );
INVX1TS U1076 ( .A(DMP_SFG[8]), .Y(intadd_26_A_2_) );
OAI31XLTS U1077 ( .A0(n1323), .A1(n1109), .A2(n1332), .B0(n1108), .Y(n720)
);
NOR2X2TS U1078 ( .A(n1302), .B(DMP_EXP_EWSW[23]), .Y(n1307) );
BUFX4TS U1079 ( .A(n1604), .Y(n1587) );
XNOR2X2TS U1080 ( .A(DMP_exp_NRM2_EW[0]), .B(n1237), .Y(n943) );
INVX1TS U1081 ( .A(LZD_output_NRM2_EW[0]), .Y(n1237) );
XNOR2X2TS U1082 ( .A(DMP_exp_NRM2_EW[6]), .B(n928), .Y(n1257) );
CLKINVX6TS U1083 ( .A(n1063), .Y(n1042) );
NOR2X4TS U1084 ( .A(shift_value_SHT2_EWR[4]), .B(n1438), .Y(n1410) );
CLKINVX6TS U1085 ( .A(n1478), .Y(n1438) );
AOI2BB2X2TS U1086 ( .B0(DmP_mant_SFG_SWR[10]), .B1(n1358), .A0N(n1358),
.A1N(DmP_mant_SFG_SWR[10]), .Y(intadd_26_B_2_) );
AOI2BB2X2TS U1087 ( .B0(DmP_mant_SFG_SWR[11]), .B1(n1354), .A0N(n1359),
.A1N(DmP_mant_SFG_SWR[11]), .Y(n1350) );
AOI222X1TS U1088 ( .A0(Raw_mant_NRM_SWR[10]), .A1(n905), .B0(
DmP_mant_SHT1_SW[14]), .B1(n1282), .C0(n909), .C1(DmP_mant_SHT1_SW[13]), .Y(n1213) );
AOI222X4TS U1089 ( .A0(Raw_mant_NRM_SWR[7]), .A1(n905), .B0(n909), .B1(
DmP_mant_SHT1_SW[16]), .C0(n1282), .C1(DmP_mant_SHT1_SW[17]), .Y(n1191) );
AOI222X1TS U1090 ( .A0(Raw_mant_NRM_SWR[6]), .A1(n906), .B0(n910), .B1(
DmP_mant_SHT1_SW[17]), .C0(n1282), .C1(DmP_mant_SHT1_SW[18]), .Y(n1223) );
AOI222X4TS U1091 ( .A0(Raw_mant_NRM_SWR[3]), .A1(n905), .B0(n910), .B1(
DmP_mant_SHT1_SW[20]), .C0(n1282), .C1(DmP_mant_SHT1_SW[21]), .Y(n1206) );
NOR2XLTS U1092 ( .A(n970), .B(intDY_EWSW[10]), .Y(n971) );
NOR2X4TS U1093 ( .A(n1364), .B(n1363), .Y(n1384) );
OAI2BB1X2TS U1094 ( .A0N(n934), .A1N(n933), .B0(Shift_reg_FLAGS_7[0]), .Y(
n1363) );
INVX4TS U1095 ( .A(n1270), .Y(n1273) );
CLKINVX6TS U1096 ( .A(n1579), .Y(busy) );
NAND2X2TS U1097 ( .A(n874), .B(n1579), .Y(n1299) );
AOI222X4TS U1098 ( .A0(DMP_SFG[5]), .A1(n895), .B0(DMP_SFG[5]), .B1(n1233),
.C0(n895), .C1(n1233), .Y(intadd_26_CI) );
AOI222X4TS U1099 ( .A0(DMP_SFG[9]), .A1(n1350), .B0(DMP_SFG[9]), .B1(n1236),
.C0(n1350), .C1(n1236), .Y(intadd_25_B_0_) );
AOI222X1TS U1100 ( .A0(n1405), .A1(n1438), .B0(n1479), .B1(Data_array_SWR[5]), .C0(n1406), .C1(n1410), .Y(n1444) );
AOI222X1TS U1101 ( .A0(n1405), .A1(n1478), .B0(Data_array_SWR[5]), .B1(n1368), .C0(n1406), .C1(n1411), .Y(n1466) );
AOI222X1TS U1102 ( .A0(n1413), .A1(n1438), .B0(n1479), .B1(Data_array_SWR[4]), .C0(n1412), .C1(n1410), .Y(n1443) );
AOI222X1TS U1103 ( .A0(n1413), .A1(n1478), .B0(Data_array_SWR[4]), .B1(n1368), .C0(n1412), .C1(n1411), .Y(n1468) );
AOI222X1TS U1104 ( .A0(n1395), .A1(n1438), .B0(Data_array_SWR[7]), .B1(n1479), .C0(n1394), .C1(n1410), .Y(n1446) );
AOI222X1TS U1105 ( .A0(n1395), .A1(n1478), .B0(Data_array_SWR[7]), .B1(n1368), .C0(n1394), .C1(n1411), .Y(n1462) );
AOI222X1TS U1106 ( .A0(n1400), .A1(n1438), .B0(Data_array_SWR[6]), .B1(n1479), .C0(n1399), .C1(n1410), .Y(n1445) );
AOI222X1TS U1107 ( .A0(n1400), .A1(n1478), .B0(Data_array_SWR[6]), .B1(n1368), .C0(n1399), .C1(n1411), .Y(n1464) );
AOI22X2TS U1108 ( .A0(DmP_mant_SFG_SWR[9]), .A1(n1355), .B0(n1354), .B1(n891), .Y(intadd_26_B_1_) );
AOI22X2TS U1109 ( .A0(DmP_mant_SFG_SWR[5]), .A1(n1355), .B0(n1354), .B1(n892), .Y(intadd_27_B_1_) );
INVX4TS U1110 ( .A(n1359), .Y(n1355) );
INVX4TS U1111 ( .A(n1610), .Y(n1357) );
INVX3TS U1112 ( .A(Shift_reg_FLAGS_7[0]), .Y(n1423) );
AOI222X1TS U1113 ( .A0(Raw_mant_NRM_SWR[4]), .A1(n905), .B0(n909), .B1(n900),
.C0(n1282), .C1(DmP_mant_SHT1_SW[20]), .Y(n1219) );
OAI21XLTS U1114 ( .A0(n1281), .A1(n1142), .B0(n1193), .Y(n787) );
NOR2X2TS U1115 ( .A(inst_FSM_INPUT_ENABLE_state_reg[2]), .B(n1535), .Y(n1262) );
AOI221X1TS U1116 ( .A0(n1551), .A1(intDX_EWSW[26]), .B0(intDX_EWSW[27]),
.B1(n1555), .C0(n1072), .Y(n1076) );
OAI21X2TS U1117 ( .A0(intDX_EWSW[18]), .A1(n1556), .B0(n993), .Y(n1079) );
NOR3X1TS U1118 ( .A(Raw_mant_NRM_SWR[21]), .B(Raw_mant_NRM_SWR[19]), .C(
Raw_mant_NRM_SWR[20]), .Y(n1253) );
NOR2X2TS U1119 ( .A(Raw_mant_NRM_SWR[12]), .B(n1128), .Y(n1247) );
AOI222X1TS U1120 ( .A0(Raw_mant_NRM_SWR[12]), .A1(n905), .B0(n909), .B1(n902), .C0(n1282), .C1(DmP_mant_SHT1_SW[12]), .Y(n1215) );
OAI211XLTS U1121 ( .A0(n1215), .A1(n908), .B0(n1210), .C0(n1209), .Y(n784)
);
NOR3X1TS U1122 ( .A(shift_value_SHT2_EWR[4]), .B(shift_value_SHT2_EWR[2]),
.C(n1516), .Y(n1365) );
NOR2X4TS U1123 ( .A(shift_value_SHT2_EWR[2]), .B(shift_value_SHT2_EWR[3]),
.Y(n1403) );
NOR2XLTS U1124 ( .A(n1612), .B(intDX_EWSW[11]), .Y(n970) );
OAI21XLTS U1125 ( .A0(intDX_EWSW[15]), .A1(n1613), .B0(intDX_EWSW[14]), .Y(
n978) );
NOR2XLTS U1126 ( .A(n991), .B(intDY_EWSW[16]), .Y(n992) );
OAI21XLTS U1127 ( .A0(intDX_EWSW[23]), .A1(n1553), .B0(intDX_EWSW[22]), .Y(
n997) );
OAI21XLTS U1128 ( .A0(intDX_EWSW[21]), .A1(n1542), .B0(intDX_EWSW[20]), .Y(
n990) );
NOR2XLTS U1129 ( .A(Raw_mant_NRM_SWR[17]), .B(Raw_mant_NRM_SWR[16]), .Y(
n1131) );
AOI31XLTS U1130 ( .A0(n1126), .A1(Raw_mant_NRM_SWR[16]), .A2(n1514), .B0(
n1125), .Y(n1127) );
OR2X1TS U1131 ( .A(n942), .B(n941), .Y(n1229) );
OAI21XLTS U1132 ( .A0(n1497), .A1(n1203), .B0(n1198), .Y(n1199) );
OAI21XLTS U1133 ( .A0(n1567), .A1(n1203), .B0(n1181), .Y(n1182) );
NOR2XLTS U1134 ( .A(n1364), .B(SIGN_FLAG_SHT1SHT2), .Y(n1230) );
OAI21XLTS U1135 ( .A0(n1506), .A1(n1330), .B0(n1060), .Y(n572) );
OAI21XLTS U1136 ( .A0(n1547), .A1(n1106), .B0(n1044), .Y(n586) );
OAI21XLTS U1137 ( .A0(n1502), .A1(n1106), .B0(n1050), .Y(n600) );
OAI21XLTS U1138 ( .A0(n1544), .A1(n1042), .B0(n1037), .Y(n745) );
OAI211XLTS U1139 ( .A0(n1176), .A1(n908), .B0(n1158), .C0(n1157), .Y(n776)
);
OAI21XLTS U1140 ( .A0(n1278), .A1(n1159), .B0(n1184), .Y(n792) );
BUFX3TS U1141 ( .A(n1609), .Y(n1598) );
BUFX3TS U1142 ( .A(n925), .Y(n1600) );
BUFX3TS U1143 ( .A(n925), .Y(n1601) );
BUFX3TS U1144 ( .A(n1609), .Y(n1591) );
BUFX3TS U1145 ( .A(n1605), .Y(n1608) );
BUFX3TS U1146 ( .A(n1609), .Y(n1590) );
BUFX3TS U1147 ( .A(n1604), .Y(n1589) );
BUFX3TS U1148 ( .A(n925), .Y(n1606) );
BUFX3TS U1149 ( .A(n1604), .Y(n1602) );
BUFX3TS U1150 ( .A(n1592), .Y(n1586) );
BUFX3TS U1151 ( .A(n1603), .Y(n1609) );
BUFX3TS U1152 ( .A(n1605), .Y(n1592) );
BUFX3TS U1153 ( .A(n1607), .Y(n1604) );
INVX2TS U1154 ( .A(DP_OP_15J30_123_3372_n4), .Y(n926) );
NAND2X1TS U1155 ( .A(n1536), .B(n926), .Y(n928) );
INVX2TS U1156 ( .A(n928), .Y(n927) );
NAND2X1TS U1157 ( .A(n1557), .B(n927), .Y(n931) );
AND4X1TS U1158 ( .A(exp_rslt_NRM2_EW1[3]), .B(n943), .C(exp_rslt_NRM2_EW1[2]), .D(exp_rslt_NRM2_EW1[1]), .Y(n929) );
AND4X1TS U1159 ( .A(n1257), .B(n944), .C(exp_rslt_NRM2_EW1[4]), .D(n929),
.Y(n930) );
CLKAND2X2TS U1160 ( .A(n941), .B(n930), .Y(n934) );
INVX2TS U1161 ( .A(n931), .Y(n932) );
CLKAND2X2TS U1162 ( .A(n1564), .B(n932), .Y(n933) );
INVX2TS U1163 ( .A(n1363), .Y(n935) );
AO22XLTS U1164 ( .A0(n935), .A1(n941), .B0(n1423), .B1(final_result_ieee[30]), .Y(n754) );
NOR2XLTS U1165 ( .A(n943), .B(exp_rslt_NRM2_EW1[1]), .Y(n938) );
INVX2TS U1166 ( .A(exp_rslt_NRM2_EW1[3]), .Y(n937) );
INVX2TS U1167 ( .A(exp_rslt_NRM2_EW1[2]), .Y(n936) );
NAND4BXLTS U1168 ( .AN(exp_rslt_NRM2_EW1[4]), .B(n938), .C(n937), .D(n936),
.Y(n939) );
NOR2XLTS U1169 ( .A(n939), .B(n944), .Y(n940) );
NAND2X2TS U1170 ( .A(n1229), .B(Shift_reg_FLAGS_7[0]), .Y(n1258) );
OA22X1TS U1171 ( .A0(n1258), .A1(exp_rslt_NRM2_EW1[3]), .B0(
Shift_reg_FLAGS_7[0]), .B1(final_result_ieee[26]), .Y(n758) );
OA22X1TS U1172 ( .A0(n1258), .A1(n943), .B0(Shift_reg_FLAGS_7[0]), .B1(
final_result_ieee[23]), .Y(n761) );
OA22X1TS U1173 ( .A0(n1258), .A1(exp_rslt_NRM2_EW1[4]), .B0(
Shift_reg_FLAGS_7[0]), .B1(final_result_ieee[27]), .Y(n757) );
OA22X1TS U1174 ( .A0(n1258), .A1(exp_rslt_NRM2_EW1[2]), .B0(
Shift_reg_FLAGS_7[0]), .B1(final_result_ieee[25]), .Y(n759) );
OA22X1TS U1175 ( .A0(n1258), .A1(exp_rslt_NRM2_EW1[1]), .B0(
Shift_reg_FLAGS_7[0]), .B1(final_result_ieee[24]), .Y(n760) );
OA22X1TS U1176 ( .A0(n1258), .A1(n944), .B0(Shift_reg_FLAGS_7[0]), .B1(
final_result_ieee[28]), .Y(n756) );
OAI21XLTS U1177 ( .A0(n873), .A1(n1438), .B0(n874), .Y(n829) );
AOI2BB2XLTS U1178 ( .B0(beg_OP), .B1(n1501), .A0N(n1501), .A1N(
inst_FSM_INPUT_ENABLE_state_reg[2]), .Y(n945) );
NAND3XLTS U1179 ( .A(inst_FSM_INPUT_ENABLE_state_reg[2]), .B(n1501), .C(
n1535), .Y(n1259) );
OAI21XLTS U1180 ( .A0(n1262), .A1(n945), .B0(n1259), .Y(n870) );
NOR2X1TS U1181 ( .A(n1614), .B(intDX_EWSW[25]), .Y(n1004) );
NOR2XLTS U1182 ( .A(n1004), .B(intDY_EWSW[24]), .Y(n946) );
AOI22X1TS U1183 ( .A0(intDX_EWSW[25]), .A1(n1614), .B0(intDX_EWSW[24]), .B1(
n946), .Y(n950) );
NAND2BXLTS U1184 ( .AN(intDY_EWSW[27]), .B(intDX_EWSW[27]), .Y(n948) );
NOR2X1TS U1185 ( .A(n1554), .B(intDX_EWSW[30]), .Y(n953) );
NOR2X1TS U1186 ( .A(n1505), .B(intDX_EWSW[29]), .Y(n951) );
AOI211X1TS U1187 ( .A0(intDY_EWSW[28]), .A1(n1529), .B0(n953), .C0(n951),
.Y(n1003) );
NOR3XLTS U1188 ( .A(n1529), .B(n951), .C(intDY_EWSW[28]), .Y(n952) );
AOI2BB2X1TS U1189 ( .B0(n955), .B1(n1003), .A0N(n954), .A1N(n953), .Y(n1008)
);
NOR2X1TS U1190 ( .A(n1581), .B(intDX_EWSW[17]), .Y(n991) );
OAI22X1TS U1191 ( .A0(n879), .A1(intDX_EWSW[10]), .B0(n1612), .B1(
intDX_EWSW[11]), .Y(n1087) );
INVX2TS U1192 ( .A(n1087), .Y(n975) );
OAI211XLTS U1193 ( .A0(intDX_EWSW[8]), .A1(n1544), .B0(n972), .C0(n975), .Y(
n986) );
OAI2BB1X1TS U1194 ( .A0N(n1518), .A1N(intDY_EWSW[5]), .B0(intDX_EWSW[4]),
.Y(n956) );
OAI22X1TS U1195 ( .A0(intDY_EWSW[4]), .A1(n956), .B0(n1518), .B1(
intDY_EWSW[5]), .Y(n967) );
OAI2BB1X1TS U1196 ( .A0N(n1500), .A1N(intDY_EWSW[7]), .B0(intDX_EWSW[6]),
.Y(n957) );
OAI22X1TS U1197 ( .A0(intDY_EWSW[6]), .A1(n957), .B0(n1500), .B1(
intDY_EWSW[7]), .Y(n966) );
OAI21XLTS U1198 ( .A0(intDX_EWSW[1]), .A1(n1543), .B0(n911), .Y(n958) );
OAI2BB2XLTS U1199 ( .B0(intDY_EWSW[0]), .B1(n958), .A0N(intDX_EWSW[1]),
.A1N(n1543), .Y(n960) );
OAI211XLTS U1200 ( .A0(n1539), .A1(intDX_EWSW[3]), .B0(n960), .C0(n959), .Y(
n963) );
OAI21XLTS U1201 ( .A0(intDX_EWSW[3]), .A1(n1539), .B0(intDX_EWSW[2]), .Y(
n961) );
AOI2BB2XLTS U1202 ( .B0(intDX_EWSW[3]), .B1(n1539), .A0N(intDY_EWSW[2]),
.A1N(n961), .Y(n962) );
AOI222X1TS U1203 ( .A0(intDY_EWSW[4]), .A1(n1499), .B0(n963), .B1(n962),
.C0(intDY_EWSW[5]), .C1(n1518), .Y(n965) );
AOI22X1TS U1204 ( .A0(intDY_EWSW[7]), .A1(n1500), .B0(intDY_EWSW[6]), .B1(
n1524), .Y(n964) );
OAI32X1TS U1205 ( .A0(n967), .A1(n966), .A2(n965), .B0(n964), .B1(n966), .Y(
n985) );
OA22X1TS U1206 ( .A0(n1548), .A1(intDX_EWSW[14]), .B0(n1613), .B1(
intDX_EWSW[15]), .Y(n982) );
OAI21XLTS U1207 ( .A0(intDX_EWSW[13]), .A1(n1541), .B0(intDX_EWSW[12]), .Y(
n969) );
OAI2BB2XLTS U1208 ( .B0(intDY_EWSW[12]), .B1(n969), .A0N(intDX_EWSW[13]),
.A1N(n1541), .Y(n981) );
AOI22X1TS U1209 ( .A0(intDX_EWSW[11]), .A1(n1612), .B0(intDX_EWSW[10]), .B1(
n971), .Y(n977) );
NAND2BXLTS U1210 ( .AN(intDY_EWSW[9]), .B(intDX_EWSW[9]), .Y(n974) );
NAND3XLTS U1211 ( .A(n1544), .B(n972), .C(intDX_EWSW[8]), .Y(n973) );
AOI21X1TS U1212 ( .A0(n974), .A1(n973), .B0(n984), .Y(n976) );
OAI2BB2XLTS U1213 ( .B0(n977), .B1(n984), .A0N(n976), .A1N(n975), .Y(n980)
);
OAI2BB2XLTS U1214 ( .B0(intDY_EWSW[14]), .B1(n978), .A0N(intDX_EWSW[15]),
.A1N(n1613), .Y(n979) );
AOI211X1TS U1215 ( .A0(n982), .A1(n981), .B0(n980), .C0(n979), .Y(n983) );
OAI31X1TS U1216 ( .A0(n986), .A1(n985), .A2(n984), .B0(n983), .Y(n989) );
OA22X1TS U1217 ( .A0(n1504), .A1(intDX_EWSW[22]), .B0(n1553), .B1(
intDX_EWSW[23]), .Y(n1001) );
AOI211XLTS U1218 ( .A0(intDY_EWSW[16]), .A1(n1523), .B0(n996), .C0(n1079),
.Y(n988) );
OAI2BB2XLTS U1219 ( .B0(intDY_EWSW[20]), .B1(n990), .A0N(intDX_EWSW[21]),
.A1N(n1542), .Y(n1000) );
AOI22X1TS U1220 ( .A0(intDX_EWSW[17]), .A1(n1581), .B0(intDX_EWSW[16]), .B1(
n992), .Y(n995) );
OAI32X1TS U1221 ( .A0(n1079), .A1(n996), .A2(n995), .B0(n994), .B1(n996),
.Y(n999) );
OAI2BB2XLTS U1222 ( .B0(intDY_EWSW[22]), .B1(n997), .A0N(intDX_EWSW[23]),
.A1N(n1553), .Y(n998) );
AOI211X1TS U1223 ( .A0(n1001), .A1(n1000), .B0(n999), .C0(n998), .Y(n1006)
);
NAND2BXLTS U1224 ( .AN(intDX_EWSW[24]), .B(intDY_EWSW[24]), .Y(n1002) );
NAND4BBX1TS U1225 ( .AN(n1072), .BN(n1004), .C(n1003), .D(n1002), .Y(n1005)
);
AOI32X1TS U1226 ( .A0(n1008), .A1(n1007), .A2(n1006), .B0(n1005), .B1(n1008),
.Y(n1009) );
INVX2TS U1227 ( .A(Shift_reg_FLAGS_7_6), .Y(n1012) );
INVX4TS U1228 ( .A(n1017), .Y(n1332) );
AND2X2TS U1229 ( .A(Shift_reg_FLAGS_7_6), .B(n1009), .Y(n1032) );
AOI22X1TS U1230 ( .A0(n904), .A1(n1263), .B0(intDX_EWSW[27]), .B1(n1032),
.Y(n1010) );
OAI21XLTS U1231 ( .A0(n1555), .A1(n1332), .B0(n1010), .Y(n726) );
AOI22X1TS U1232 ( .A0(intDX_EWSW[1]), .A1(n1032), .B0(DMP_EXP_EWSW[1]), .B1(
n1321), .Y(n1011) );
OAI21XLTS U1233 ( .A0(n1543), .A1(n1332), .B0(n1011), .Y(n752) );
BUFX3TS U1234 ( .A(n1032), .Y(n1029) );
BUFX4TS U1235 ( .A(n1012), .Y(n1067) );
AOI22X1TS U1236 ( .A0(intDX_EWSW[28]), .A1(n1029), .B0(DMP_EXP_EWSW[28]),
.B1(n1067), .Y(n1013) );
OAI21XLTS U1237 ( .A0(n1552), .A1(n1332), .B0(n1013), .Y(n725) );
AOI22X1TS U1238 ( .A0(intDX_EWSW[29]), .A1(n1029), .B0(DMP_EXP_EWSW[29]),
.B1(n1067), .Y(n1014) );
OAI21XLTS U1239 ( .A0(n1505), .A1(n1332), .B0(n1014), .Y(n724) );
AOI22X1TS U1240 ( .A0(intDX_EWSW[30]), .A1(n1029), .B0(DMP_EXP_EWSW[30]),
.B1(n1321), .Y(n1015) );
OAI21XLTS U1241 ( .A0(n1554), .A1(n1332), .B0(n1015), .Y(n723) );
AOI22X1TS U1242 ( .A0(DMP_EXP_EWSW[23]), .A1(n1263), .B0(intDX_EWSW[23]),
.B1(n1029), .Y(n1016) );
OAI21XLTS U1243 ( .A0(n1553), .A1(n1332), .B0(n1016), .Y(n730) );
BUFX3TS U1244 ( .A(n1017), .Y(n1063) );
AOI22X1TS U1245 ( .A0(intDX_EWSW[21]), .A1(n1029), .B0(DMP_EXP_EWSW[21]),
.B1(n1067), .Y(n1018) );
OAI21XLTS U1246 ( .A0(n1542), .A1(n1042), .B0(n1018), .Y(n732) );
AOI22X1TS U1247 ( .A0(intDX_EWSW[20]), .A1(n1029), .B0(DMP_EXP_EWSW[20]),
.B1(n1321), .Y(n1019) );
OAI21XLTS U1248 ( .A0(n1550), .A1(n1042), .B0(n1019), .Y(n733) );
AOI22X1TS U1249 ( .A0(intDX_EWSW[18]), .A1(n1029), .B0(DMP_EXP_EWSW[18]),
.B1(n1321), .Y(n1020) );
OAI21XLTS U1250 ( .A0(n1556), .A1(n1042), .B0(n1020), .Y(n735) );
AOI22X1TS U1251 ( .A0(intDX_EWSW[17]), .A1(n1029), .B0(DMP_EXP_EWSW[17]),
.B1(n1067), .Y(n1021) );
OAI21XLTS U1252 ( .A0(n1581), .A1(n1042), .B0(n1021), .Y(n736) );
AOI22X1TS U1253 ( .A0(intDX_EWSW[22]), .A1(n1029), .B0(DMP_EXP_EWSW[22]),
.B1(n1321), .Y(n1022) );
OAI21XLTS U1254 ( .A0(n1504), .A1(n1042), .B0(n1022), .Y(n731) );
AOI22X1TS U1255 ( .A0(intDX_EWSW[7]), .A1(n1032), .B0(DMP_EXP_EWSW[7]), .B1(
n1321), .Y(n1023) );
OAI21XLTS U1256 ( .A0(n1534), .A1(n1042), .B0(n1023), .Y(n746) );
AOI22X1TS U1257 ( .A0(intDX_EWSW[6]), .A1(n1032), .B0(DMP_EXP_EWSW[6]), .B1(
n1067), .Y(n1024) );
OAI21XLTS U1258 ( .A0(n1533), .A1(n1042), .B0(n1024), .Y(n747) );
AOI22X1TS U1259 ( .A0(intDX_EWSW[4]), .A1(n1032), .B0(DMP_EXP_EWSW[4]), .B1(
n1067), .Y(n1025) );
OAI21XLTS U1260 ( .A0(n1546), .A1(n1042), .B0(n1025), .Y(n749) );
AOI22X1TS U1261 ( .A0(n911), .A1(n1029), .B0(DMP_EXP_EWSW[0]), .B1(n1321),
.Y(n1026) );
OAI21XLTS U1262 ( .A0(n1503), .A1(n1042), .B0(n1026), .Y(n753) );
AOI22X1TS U1263 ( .A0(intDX_EWSW[2]), .A1(n1032), .B0(DMP_EXP_EWSW[2]), .B1(
n1067), .Y(n1027) );
OAI21XLTS U1264 ( .A0(n1545), .A1(n1042), .B0(n1027), .Y(n751) );
AOI22X1TS U1265 ( .A0(intDX_EWSW[19]), .A1(n1029), .B0(DMP_EXP_EWSW[19]),
.B1(n1067), .Y(n1028) );
OAI21XLTS U1266 ( .A0(n1506), .A1(n1042), .B0(n1028), .Y(n734) );
AOI22X1TS U1267 ( .A0(intDX_EWSW[5]), .A1(n896), .B0(DMP_EXP_EWSW[5]), .B1(
n1067), .Y(n1030) );
OAI21XLTS U1268 ( .A0(n1502), .A1(n1332), .B0(n1030), .Y(n748) );
AOI22X1TS U1269 ( .A0(intDX_EWSW[16]), .A1(n896), .B0(DMP_EXP_EWSW[16]),
.B1(n1067), .Y(n1031) );
OAI21XLTS U1270 ( .A0(n1549), .A1(n1042), .B0(n1031), .Y(n737) );
AOI222X1TS U1271 ( .A0(n1063), .A1(intDX_EWSW[23]), .B0(DmP_EXP_EWSW[23]),
.B1(n1321), .C0(intDY_EWSW[23]), .C1(n1032), .Y(n1033) );
INVX2TS U1272 ( .A(n1033), .Y(n564) );
AOI22X1TS U1273 ( .A0(intDX_EWSW[10]), .A1(n896), .B0(DMP_EXP_EWSW[10]),
.B1(n1321), .Y(n1034) );
OAI21XLTS U1274 ( .A0(n879), .A1(n1042), .B0(n1034), .Y(n743) );
AOI22X1TS U1275 ( .A0(intDX_EWSW[9]), .A1(n896), .B0(DMP_EXP_EWSW[9]), .B1(
n1067), .Y(n1035) );
OAI21XLTS U1276 ( .A0(n1540), .A1(n1332), .B0(n1035), .Y(n744) );
AOI22X1TS U1277 ( .A0(intDX_EWSW[14]), .A1(n896), .B0(DMP_EXP_EWSW[14]),
.B1(n1263), .Y(n1036) );
OAI21XLTS U1278 ( .A0(n1548), .A1(n1042), .B0(n1036), .Y(n739) );
AOI22X1TS U1279 ( .A0(intDX_EWSW[8]), .A1(n896), .B0(DMP_EXP_EWSW[8]), .B1(
n1263), .Y(n1037) );
AOI22X1TS U1280 ( .A0(intDX_EWSW[12]), .A1(n896), .B0(DMP_EXP_EWSW[12]),
.B1(n1263), .Y(n1038) );
OAI21XLTS U1281 ( .A0(n1547), .A1(n1042), .B0(n1038), .Y(n741) );
AOI22X1TS U1282 ( .A0(intDX_EWSW[11]), .A1(n896), .B0(DMP_EXP_EWSW[11]),
.B1(n1067), .Y(n1039) );
OAI21XLTS U1283 ( .A0(n1612), .A1(n1042), .B0(n1039), .Y(n742) );
AOI22X1TS U1284 ( .A0(intDX_EWSW[13]), .A1(n896), .B0(DMP_EXP_EWSW[13]),
.B1(n1321), .Y(n1040) );
OAI21XLTS U1285 ( .A0(n1541), .A1(n1042), .B0(n1040), .Y(n740) );
AOI22X1TS U1286 ( .A0(intDX_EWSW[15]), .A1(n896), .B0(DMP_EXP_EWSW[15]),
.B1(n1321), .Y(n1041) );
OAI21XLTS U1287 ( .A0(n1613), .A1(n1042), .B0(n1041), .Y(n738) );
AOI22X1TS U1288 ( .A0(intDX_EWSW[3]), .A1(n896), .B0(DMP_EXP_EWSW[3]), .B1(
n1321), .Y(n1043) );
OAI21XLTS U1289 ( .A0(n1539), .A1(n1332), .B0(n1043), .Y(n750) );
INVX3TS U1290 ( .A(n896), .Y(n1106) );
AOI22X1TS U1291 ( .A0(intDX_EWSW[12]), .A1(n1063), .B0(DmP_EXP_EWSW[12]),
.B1(n1012), .Y(n1044) );
AOI22X1TS U1292 ( .A0(DmP_EXP_EWSW[27]), .A1(n1263), .B0(intDX_EWSW[27]),
.B1(n1063), .Y(n1045) );
OAI21XLTS U1293 ( .A0(n1555), .A1(n1106), .B0(n1045), .Y(n560) );
CLKBUFX3TS U1294 ( .A(n1063), .Y(n1069) );
AOI22X1TS U1295 ( .A0(intDX_EWSW[13]), .A1(n1069), .B0(DmP_EXP_EWSW[13]),
.B1(n1263), .Y(n1046) );
OAI21XLTS U1296 ( .A0(n1541), .A1(n1106), .B0(n1046), .Y(n584) );
AOI22X1TS U1297 ( .A0(intDX_EWSW[8]), .A1(n1063), .B0(DmP_EXP_EWSW[8]), .B1(
n1321), .Y(n1047) );
OAI21XLTS U1298 ( .A0(n1544), .A1(n1106), .B0(n1047), .Y(n594) );
AOI22X1TS U1299 ( .A0(intDX_EWSW[15]), .A1(n1069), .B0(DmP_EXP_EWSW[15]),
.B1(n1263), .Y(n1048) );
OAI21XLTS U1300 ( .A0(n1613), .A1(n1106), .B0(n1048), .Y(n580) );
AOI22X1TS U1301 ( .A0(intDX_EWSW[14]), .A1(n1069), .B0(DmP_EXP_EWSW[14]),
.B1(n1012), .Y(n1049) );
OAI21XLTS U1302 ( .A0(n1548), .A1(n1106), .B0(n1049), .Y(n582) );
AOI22X1TS U1303 ( .A0(intDX_EWSW[5]), .A1(n1063), .B0(DmP_EXP_EWSW[5]), .B1(
n1321), .Y(n1050) );
AOI22X1TS U1304 ( .A0(intDX_EWSW[6]), .A1(n1063), .B0(DmP_EXP_EWSW[6]), .B1(
n1321), .Y(n1051) );
OAI21XLTS U1305 ( .A0(n1533), .A1(n1106), .B0(n1051), .Y(n598) );
AOI22X1TS U1306 ( .A0(intDX_EWSW[4]), .A1(n1017), .B0(DmP_EXP_EWSW[4]), .B1(
n1321), .Y(n1052) );
OAI21XLTS U1307 ( .A0(n1546), .A1(n1106), .B0(n1052), .Y(n602) );
AOI22X1TS U1308 ( .A0(intDX_EWSW[9]), .A1(n1017), .B0(DmP_EXP_EWSW[9]), .B1(
n1263), .Y(n1053) );
OAI21XLTS U1309 ( .A0(n1540), .A1(n1106), .B0(n1053), .Y(n592) );
AOI22X1TS U1310 ( .A0(intDX_EWSW[7]), .A1(n1017), .B0(DmP_EXP_EWSW[7]), .B1(
n1012), .Y(n1054) );
OAI21XLTS U1311 ( .A0(n1534), .A1(n1106), .B0(n1054), .Y(n596) );
AOI22X1TS U1312 ( .A0(intDX_EWSW[11]), .A1(n1063), .B0(DmP_EXP_EWSW[11]),
.B1(n1012), .Y(n1055) );
OAI21XLTS U1313 ( .A0(n1612), .A1(n1106), .B0(n1055), .Y(n588) );
AOI22X1TS U1314 ( .A0(intDX_EWSW[10]), .A1(n1017), .B0(DmP_EXP_EWSW[10]),
.B1(n1067), .Y(n1056) );
OAI21XLTS U1315 ( .A0(n879), .A1(n1106), .B0(n1056), .Y(n590) );
INVX4TS U1316 ( .A(n896), .Y(n1330) );
AOI22X1TS U1317 ( .A0(intDX_EWSW[21]), .A1(n1069), .B0(DmP_EXP_EWSW[21]),
.B1(n1263), .Y(n1057) );
OAI21XLTS U1318 ( .A0(n1542), .A1(n1330), .B0(n1057), .Y(n568) );
AOI22X1TS U1319 ( .A0(intDX_EWSW[2]), .A1(n1063), .B0(DmP_EXP_EWSW[2]), .B1(
n1263), .Y(n1058) );
OAI21XLTS U1320 ( .A0(n1545), .A1(n1330), .B0(n1058), .Y(n606) );
AOI22X1TS U1321 ( .A0(intDX_EWSW[1]), .A1(n1063), .B0(DmP_EXP_EWSW[1]), .B1(
n1067), .Y(n1059) );
OAI21XLTS U1322 ( .A0(n1543), .A1(n1330), .B0(n1059), .Y(n608) );
AOI22X1TS U1323 ( .A0(intDX_EWSW[19]), .A1(n1069), .B0(DmP_EXP_EWSW[19]),
.B1(n1263), .Y(n1060) );
AOI22X1TS U1324 ( .A0(intDX_EWSW[22]), .A1(n1069), .B0(DmP_EXP_EWSW[22]),
.B1(n1263), .Y(n1061) );
OAI21XLTS U1325 ( .A0(n1504), .A1(n1330), .B0(n1061), .Y(n566) );
AOI22X1TS U1326 ( .A0(intDX_EWSW[16]), .A1(n1069), .B0(DmP_EXP_EWSW[16]),
.B1(n1263), .Y(n1062) );
OAI21XLTS U1327 ( .A0(n1549), .A1(n1330), .B0(n1062), .Y(n578) );
AOI22X1TS U1328 ( .A0(intDX_EWSW[3]), .A1(n1063), .B0(DmP_EXP_EWSW[3]), .B1(
n1012), .Y(n1064) );
OAI21XLTS U1329 ( .A0(n1539), .A1(n1330), .B0(n1064), .Y(n604) );
AOI22X1TS U1330 ( .A0(intDX_EWSW[20]), .A1(n1069), .B0(DmP_EXP_EWSW[20]),
.B1(n1263), .Y(n1065) );
OAI21XLTS U1331 ( .A0(n1550), .A1(n1330), .B0(n1065), .Y(n570) );
AOI22X1TS U1332 ( .A0(intDX_EWSW[18]), .A1(n1017), .B0(DmP_EXP_EWSW[18]),
.B1(n1263), .Y(n1066) );
OAI21XLTS U1333 ( .A0(n1556), .A1(n1330), .B0(n1066), .Y(n574) );
AOI22X1TS U1334 ( .A0(n911), .A1(n1069), .B0(DmP_EXP_EWSW[0]), .B1(n1067),
.Y(n1068) );
OAI21XLTS U1335 ( .A0(n1503), .A1(n1330), .B0(n1068), .Y(n610) );
AOI22X1TS U1336 ( .A0(intDX_EWSW[17]), .A1(n1069), .B0(DmP_EXP_EWSW[17]),
.B1(n1263), .Y(n1070) );
OAI21XLTS U1337 ( .A0(n1581), .A1(n1330), .B0(n1070), .Y(n576) );
OAI22X1TS U1338 ( .A0(n1543), .A1(intDX_EWSW[1]), .B0(n1614), .B1(
intDX_EWSW[25]), .Y(n1071) );
AOI221X1TS U1339 ( .A0(n1543), .A1(intDX_EWSW[1]), .B0(intDX_EWSW[25]), .B1(
n1614), .C0(n1071), .Y(n1077) );
OAI22X1TS U1340 ( .A0(n1552), .A1(intDX_EWSW[28]), .B0(n1505), .B1(
intDX_EWSW[29]), .Y(n1073) );
AOI221X1TS U1341 ( .A0(n1552), .A1(intDX_EWSW[28]), .B0(intDX_EWSW[29]),
.B1(n1505), .C0(n1073), .Y(n1075) );
AOI2BB2XLTS U1342 ( .B0(intDX_EWSW[7]), .B1(n1534), .A0N(n1534), .A1N(
intDX_EWSW[7]), .Y(n1074) );
NAND4XLTS U1343 ( .A(n1077), .B(n1076), .C(n1075), .D(n1074), .Y(n1105) );
OAI22X1TS U1344 ( .A0(n1554), .A1(intDX_EWSW[30]), .B0(n1581), .B1(
intDX_EWSW[17]), .Y(n1078) );
OAI22X1TS U1345 ( .A0(n1550), .A1(intDX_EWSW[20]), .B0(n1542), .B1(
intDX_EWSW[21]), .Y(n1080) );
OAI22X1TS U1346 ( .A0(n1504), .A1(intDX_EWSW[22]), .B0(n1553), .B1(
intDX_EWSW[23]), .Y(n1081) );
NAND4XLTS U1347 ( .A(n1085), .B(n1084), .C(n1083), .D(n1082), .Y(n1104) );
OAI22X1TS U1348 ( .A0(n1491), .A1(intDX_EWSW[24]), .B0(n1540), .B1(
intDX_EWSW[9]), .Y(n1086) );
AOI221X1TS U1349 ( .A0(n1491), .A1(intDX_EWSW[24]), .B0(intDX_EWSW[9]), .B1(
n1540), .C0(n1086), .Y(n1093) );
OAI22X1TS U1350 ( .A0(n1547), .A1(intDX_EWSW[12]), .B0(n1541), .B1(
intDX_EWSW[13]), .Y(n1088) );
OAI22X1TS U1351 ( .A0(n1548), .A1(intDX_EWSW[14]), .B0(n1613), .B1(
intDX_EWSW[15]), .Y(n1089) );
NAND4XLTS U1352 ( .A(n1093), .B(n1092), .C(n1091), .D(n1090), .Y(n1103) );
OAI22X1TS U1353 ( .A0(n1549), .A1(intDX_EWSW[16]), .B0(n1503), .B1(n911),
.Y(n1094) );
AOI221X1TS U1354 ( .A0(n1549), .A1(intDX_EWSW[16]), .B0(n911), .B1(n1503),
.C0(n1094), .Y(n1101) );
OAI22X1TS U1355 ( .A0(n1545), .A1(intDX_EWSW[2]), .B0(n1539), .B1(
intDX_EWSW[3]), .Y(n1095) );
OAI22X1TS U1356 ( .A0(n1546), .A1(intDX_EWSW[4]), .B0(n1502), .B1(
intDX_EWSW[5]), .Y(n1096) );
AOI221X1TS U1357 ( .A0(n1546), .A1(intDX_EWSW[4]), .B0(intDX_EWSW[5]), .B1(
n1502), .C0(n1096), .Y(n1099) );
OAI22X1TS U1358 ( .A0(n1544), .A1(intDX_EWSW[8]), .B0(n1533), .B1(
intDX_EWSW[6]), .Y(n1097) );
AOI221X1TS U1359 ( .A0(n1544), .A1(intDX_EWSW[8]), .B0(intDX_EWSW[6]), .B1(
n1533), .C0(n1097), .Y(n1098) );
NAND4XLTS U1360 ( .A(n1101), .B(n1100), .C(n1099), .D(n1098), .Y(n1102) );
NOR4X1TS U1361 ( .A(n1105), .B(n1104), .C(n1103), .D(n1102), .Y(n1323) );
CLKXOR2X2TS U1362 ( .A(intDY_EWSW[31]), .B(intAS), .Y(n1320) );
INVX2TS U1363 ( .A(n1320), .Y(n1109) );
AOI22X1TS U1364 ( .A0(intDX_EWSW[31]), .A1(n1107), .B0(SIGN_FLAG_EXP), .B1(
n877), .Y(n1108) );
NOR2XLTS U1365 ( .A(Raw_mant_NRM_SWR[8]), .B(Raw_mant_NRM_SWR[9]), .Y(n1111)
);
NAND4X1TS U1366 ( .A(n1495), .B(n1484), .C(n1483), .D(n1513), .Y(n1252) );
NOR2BX1TS U1367 ( .AN(n1126), .B(Raw_mant_NRM_SWR[18]), .Y(n1240) );
NOR2BX1TS U1368 ( .AN(n1240), .B(n1241), .Y(n1123) );
NAND2X1TS U1369 ( .A(n1123), .B(n1497), .Y(n1242) );
NAND2X1TS U1370 ( .A(n1135), .B(n1486), .Y(n1128) );
NAND2X1TS U1371 ( .A(n1247), .B(n1487), .Y(n1110) );
NOR2X1TS U1372 ( .A(Raw_mant_NRM_SWR[4]), .B(Raw_mant_NRM_SWR[5]), .Y(n1112)
);
NOR3X1TS U1373 ( .A(Raw_mant_NRM_SWR[8]), .B(Raw_mant_NRM_SWR[9]), .C(n1110),
.Y(n1113) );
NAND2X1TS U1374 ( .A(n1113), .B(n1488), .Y(n1120) );
OAI22X1TS U1375 ( .A0(n1111), .A1(n1110), .B0(n1112), .B1(n1120), .Y(n1118)
);
NOR2X1TS U1376 ( .A(Raw_mant_NRM_SWR[3]), .B(Raw_mant_NRM_SWR[2]), .Y(n1115)
);
NAND2X1TS U1377 ( .A(n1248), .B(n1112), .Y(n1116) );
OAI21X1TS U1378 ( .A0(n1115), .A1(n1116), .B0(n1114), .Y(n1139) );
INVX2TS U1379 ( .A(n1116), .Y(n1249) );
OAI31X1TS U1380 ( .A0(n1118), .A1(n1139), .A2(n1117), .B0(
Shift_reg_FLAGS_7[1]), .Y(n1239) );
NAND3XLTS U1381 ( .A(n873), .B(Shift_amount_SHT1_EWR[4]), .C(n874), .Y(n1119) );
INVX2TS U1382 ( .A(n1120), .Y(n1130) );
AOI22X1TS U1383 ( .A0(Raw_mant_NRM_SWR[18]), .A1(n1126), .B0(n1247), .B1(
Raw_mant_NRM_SWR[10]), .Y(n1136) );
OAI32X1TS U1384 ( .A0(Raw_mant_NRM_SWR[3]), .A1(Raw_mant_NRM_SWR[1]), .A2(
n1489), .B0(n1515), .B1(Raw_mant_NRM_SWR[3]), .Y(n1121) );
NAND2X1TS U1385 ( .A(Raw_mant_NRM_SWR[12]), .B(n1135), .Y(n1244) );
NAND2X1TS U1386 ( .A(Raw_mant_NRM_SWR[14]), .B(n1123), .Y(n1141) );
AOI32X1TS U1387 ( .A0(Raw_mant_NRM_SWR[20]), .A1(n1483), .A2(n1517), .B0(
Raw_mant_NRM_SWR[22]), .B1(n1483), .Y(n1124) );
AOI32X1TS U1388 ( .A0(n1484), .A1(n1141), .A2(n1124), .B0(
Raw_mant_NRM_SWR[25]), .B1(n1141), .Y(n1125) );
OAI31X1TS U1389 ( .A0(Raw_mant_NRM_SWR[9]), .A1(n1128), .A2(n1490), .B0(
n1127), .Y(n1129) );
NAND2X2TS U1390 ( .A(Shift_reg_FLAGS_7[1]), .B(n1144), .Y(n1285) );
NOR2BX1TS U1391 ( .AN(Shift_amount_SHT1_EWR[0]), .B(Shift_reg_FLAGS_7[1]),
.Y(n1180) );
CLKBUFX2TS U1392 ( .A(n1180), .Y(n1205) );
BUFX4TS U1393 ( .A(n1205), .Y(n1282) );
AOI22X1TS U1394 ( .A0(Raw_mant_NRM_SWR[24]), .A1(n906), .B0(n1282), .B1(
DmP_mant_SHT1_SW[0]), .Y(n1150) );
NOR2XLTS U1395 ( .A(Raw_mant_NRM_SWR[23]), .B(Raw_mant_NRM_SWR[22]), .Y(
n1134) );
NOR2X1TS U1396 ( .A(Raw_mant_NRM_SWR[21]), .B(Raw_mant_NRM_SWR[20]), .Y(
n1132) );
AOI32X1TS U1397 ( .A0(Raw_mant_NRM_SWR[15]), .A1(n1132), .A2(n1131), .B0(
Raw_mant_NRM_SWR[19]), .B1(n1132), .Y(n1133) );
AOI211X1TS U1398 ( .A0(n1134), .A1(n1133), .B0(Raw_mant_NRM_SWR[25]), .C0(
Raw_mant_NRM_SWR[24]), .Y(n1140) );
OAI31X1TS U1399 ( .A0(Raw_mant_NRM_SWR[12]), .A1(n1486), .A2(n1137), .B0(
n1136), .Y(n1138) );
NOR2X1TS U1400 ( .A(n1161), .B(n874), .Y(n1256) );
AOI21X1TS U1401 ( .A0(Shift_amount_SHT1_EWR[1]), .A1(n874), .B0(n1256), .Y(
n1143) );
INVX2TS U1402 ( .A(n1299), .Y(n1214) );
BUFX4TS U1403 ( .A(n1214), .Y(n1296) );
NOR2X2TS U1404 ( .A(n1296), .B(n1143), .Y(n1293) );
NOR2X4TS U1405 ( .A(n1144), .B(n874), .Y(n1283) );
AOI22X1TS U1406 ( .A0(Raw_mant_NRM_SWR[21]), .A1(n1283), .B0(n1205), .B1(
DmP_mant_SHT1_SW[2]), .Y(n1146) );
AOI22X1TS U1407 ( .A0(Raw_mant_NRM_SWR[22]), .A1(n905), .B0(n909), .B1(
DmP_mant_SHT1_SW[1]), .Y(n1145) );
NAND2X1TS U1408 ( .A(n1146), .B(n1145), .Y(n1173) );
AOI22X1TS U1409 ( .A0(n1214), .A1(Data_array_SWR[1]), .B0(n1293), .B1(n1173),
.Y(n1149) );
INVX2TS U1410 ( .A(n1147), .Y(n1291) );
NAND2X1TS U1411 ( .A(Raw_mant_NRM_SWR[23]), .B(n1291), .Y(n1148) );
AOI22X1TS U1412 ( .A0(Raw_mant_NRM_SWR[18]), .A1(n1283), .B0(n1205), .B1(
n903), .Y(n1152) );
AOI22X1TS U1413 ( .A0(Raw_mant_NRM_SWR[19]), .A1(n905), .B0(n909), .B1(n899),
.Y(n1151) );
NAND2X1TS U1414 ( .A(n1152), .B(n1151), .Y(n1165) );
AOI22X1TS U1415 ( .A0(n1214), .A1(Data_array_SWR[4]), .B0(n1293), .B1(n1165),
.Y(n1154) );
NAND2X1TS U1416 ( .A(Raw_mant_NRM_SWR[20]), .B(n1291), .Y(n1153) );
AOI22X1TS U1417 ( .A0(Raw_mant_NRM_SWR[17]), .A1(n1283), .B0(n1205), .B1(
DmP_mant_SHT1_SW[6]), .Y(n1156) );
AOI22X1TS U1418 ( .A0(Raw_mant_NRM_SWR[18]), .A1(n905), .B0(n909), .B1(n903),
.Y(n1155) );
NAND2X1TS U1419 ( .A(n1156), .B(n1155), .Y(n1160) );
AOI22X1TS U1420 ( .A0(n1296), .A1(Data_array_SWR[5]), .B0(n1293), .B1(n1160),
.Y(n1158) );
NAND2X1TS U1421 ( .A(Raw_mant_NRM_SWR[19]), .B(n1291), .Y(n1157) );
AOI22X1TS U1422 ( .A0(n1214), .A1(Data_array_SWR[7]), .B0(n907), .B1(n1160),
.Y(n1164) );
INVX2TS U1423 ( .A(n1283), .Y(n1203) );
NAND2X1TS U1424 ( .A(Raw_mant_NRM_SWR[15]), .B(n1162), .Y(n1163) );
AOI22X1TS U1425 ( .A0(n1214), .A1(Data_array_SWR[6]), .B0(n907), .B1(n1165),
.Y(n1167) );
NAND2X1TS U1426 ( .A(Raw_mant_NRM_SWR[16]), .B(n1162), .Y(n1166) );
AOI22X1TS U1427 ( .A0(Raw_mant_NRM_SWR[22]), .A1(n1283), .B0(n1282), .B1(
DmP_mant_SHT1_SW[1]), .Y(n1169) );
AOI22X1TS U1428 ( .A0(Raw_mant_NRM_SWR[23]), .A1(n905), .B0(n909), .B1(
DmP_mant_SHT1_SW[0]), .Y(n1168) );
NAND2X1TS U1429 ( .A(n1169), .B(n1168), .Y(n1292) );
AOI22X1TS U1430 ( .A0(n1296), .A1(Data_array_SWR[2]), .B0(n907), .B1(n1292),
.Y(n1171) );
NAND2X1TS U1431 ( .A(Raw_mant_NRM_SWR[20]), .B(n1162), .Y(n1170) );
AOI22X1TS U1432 ( .A0(n1214), .A1(Data_array_SWR[3]), .B0(n907), .B1(n1173),
.Y(n1175) );
NAND2X1TS U1433 ( .A(Raw_mant_NRM_SWR[19]), .B(n1162), .Y(n1174) );
AOI22X1TS U1434 ( .A0(n1214), .A1(Data_array_SWR[9]), .B0(
Raw_mant_NRM_SWR[13]), .B1(n1162), .Y(n1178) );
AOI22X1TS U1435 ( .A0(n909), .A1(DmP_mant_SHT1_SW[21]), .B0(n1180), .B1(
DmP_mant_SHT1_SW[22]), .Y(n1181) );
AOI21X1TS U1436 ( .A0(Raw_mant_NRM_SWR[2]), .A1(n906), .B0(n1182), .Y(n1278)
);
OAI22X1TS U1437 ( .A0(n1219), .A1(n908), .B0(n1561), .B1(n1147), .Y(n1183)
);
AOI21X1TS U1438 ( .A0(n1296), .A1(Data_array_SWR[21]), .B0(n1183), .Y(n1184)
);
AOI22X1TS U1439 ( .A0(Raw_mant_NRM_SWR[4]), .A1(n1283), .B0(n1282), .B1(n900), .Y(n1185) );
AOI21X1TS U1440 ( .A0(n910), .A1(DmP_mant_SHT1_SW[18]), .B0(n1186), .Y(n1197) );
OAI22X1TS U1441 ( .A0(n1191), .A1(n908), .B0(n1493), .B1(n1147), .Y(n1187)
);
AOI21X1TS U1442 ( .A0(n1296), .A1(Data_array_SWR[18]), .B0(n1187), .Y(n1188)
);
AOI22X1TS U1443 ( .A0(Raw_mant_NRM_SWR[8]), .A1(n1283), .B0(
DmP_mant_SHT1_SW[15]), .B1(n1205), .Y(n1189) );
AOI21X1TS U1444 ( .A0(DmP_mant_SHT1_SW[14]), .A1(n910), .B0(n1190), .Y(n1281) );
INVX2TS U1445 ( .A(n1162), .Y(n1194) );
OAI22X1TS U1446 ( .A0(n1191), .A1(n1159), .B0(n1493), .B1(n1194), .Y(n1192)
);
AOI21X1TS U1447 ( .A0(n1296), .A1(Data_array_SWR[16]), .B0(n1192), .Y(n1193)
);
OAI22X1TS U1448 ( .A0(n1206), .A1(n1159), .B0(n1515), .B1(n1194), .Y(n1195)
);
AOI21X1TS U1449 ( .A0(n1296), .A1(Data_array_SWR[20]), .B0(n1195), .Y(n1196)
);
AOI22X1TS U1450 ( .A0(n909), .A1(DmP_mant_SHT1_SW[8]), .B0(n1282), .B1(n901),
.Y(n1198) );
AOI21X1TS U1451 ( .A0(Raw_mant_NRM_SWR[15]), .A1(n906), .B0(n1199), .Y(n1289) );
OAI22X1TS U1452 ( .A0(n1200), .A1(n908), .B0(n1485), .B1(n1147), .Y(n1201)
);
AOI21X1TS U1453 ( .A0(n1296), .A1(Data_array_SWR[8]), .B0(n1201), .Y(n1202)
);
OAI22X1TS U1454 ( .A0(n1567), .A1(n1285), .B0(n1489), .B1(n1203), .Y(n1204)
);
OAI22X1TS U1455 ( .A0(n1276), .A1(n1159), .B0(n1206), .B1(n908), .Y(n1207)
);
AOI21X1TS U1456 ( .A0(n1296), .A1(Data_array_SWR[22]), .B0(n1207), .Y(n1208)
);
AOI22X1TS U1457 ( .A0(n1296), .A1(Data_array_SWR[13]), .B0(
Raw_mant_NRM_SWR[9]), .B1(n1162), .Y(n1210) );
OA22X1TS U1458 ( .A0(n1486), .A1(n1147), .B0(n1213), .B1(n1159), .Y(n1209)
);
AOI22X1TS U1459 ( .A0(n1296), .A1(Data_array_SWR[15]), .B0(
Raw_mant_NRM_SWR[7]), .B1(n1162), .Y(n1212) );
OA22X1TS U1460 ( .A0(n1492), .A1(n1147), .B0(n1227), .B1(n1159), .Y(n1211)
);
AOI22X1TS U1461 ( .A0(n1214), .A1(Data_array_SWR[11]), .B0(
Raw_mant_NRM_SWR[11]), .B1(n1162), .Y(n1217) );
OA22X1TS U1462 ( .A0(n1509), .A1(n1147), .B0(n1215), .B1(n1159), .Y(n1216)
);
AOI22X1TS U1463 ( .A0(n1296), .A1(Data_array_SWR[19]), .B0(
Raw_mant_NRM_SWR[3]), .B1(n1162), .Y(n1221) );
OA22X1TS U1464 ( .A0(n1522), .A1(n1147), .B0(n1219), .B1(n1159), .Y(n1220)
);
AOI22X1TS U1465 ( .A0(n1296), .A1(Data_array_SWR[17]), .B0(
Raw_mant_NRM_SWR[5]), .B1(n1162), .Y(n1226) );
OA22X1TS U1466 ( .A0(n1488), .A1(n1147), .B0(n1223), .B1(n1159), .Y(n1225)
);
BUFX4TS U1467 ( .A(OP_FLAG_SFG), .Y(n1354) );
CLKBUFX2TS U1468 ( .A(OP_FLAG_SFG), .Y(n1359) );
AOI22X1TS U1469 ( .A0(DmP_mant_SFG_SWR[2]), .A1(n1354), .B0(n1358), .B1(n915), .Y(n1343) );
NAND2X1TS U1470 ( .A(n1343), .B(DMP_SFG[0]), .Y(n1345) );
INVX2TS U1471 ( .A(n1345), .Y(n1228) );
INVX2TS U1472 ( .A(n1229), .Y(n1364) );
OAI2BB2XLTS U1473 ( .B0(n1230), .B1(n1363), .A0N(n1423), .A1N(
final_result_ieee[31]), .Y(n543) );
AOI22X1TS U1474 ( .A0(DmP_mant_SFG_SWR[4]), .A1(n1358), .B0(n1354), .B1(n917), .Y(intadd_27_B_0_) );
AOI21X1TS U1475 ( .A0(intadd_27_A_1_), .A1(intadd_27_B_1_), .B0(
intadd_27_B_0_), .Y(n1231) );
AOI2BB2X1TS U1476 ( .B0(DMP_SFG[2]), .B1(n1231), .A0N(intadd_27_A_1_), .A1N(
intadd_27_B_1_), .Y(n1232) );
AOI222X1TS U1477 ( .A0(n1232), .A1(intadd_27_A_2_), .B0(n1232), .B1(n897),
.C0(intadd_27_A_2_), .C1(n897), .Y(n1233) );
AOI22X1TS U1478 ( .A0(DmP_mant_SFG_SWR[8]), .A1(n1355), .B0(n1354), .B1(n920), .Y(intadd_26_B_0_) );
AOI21X1TS U1479 ( .A0(intadd_26_A_1_), .A1(intadd_26_B_1_), .B0(
intadd_26_B_0_), .Y(n1234) );
AOI2BB2X1TS U1480 ( .B0(DMP_SFG[6]), .B1(n1234), .A0N(intadd_26_A_1_), .A1N(
intadd_26_B_1_), .Y(n1235) );
AOI222X1TS U1481 ( .A0(n1235), .A1(intadd_26_A_2_), .B0(n1235), .B1(
intadd_26_B_2_), .C0(intadd_26_A_2_), .C1(intadd_26_B_2_), .Y(n1236)
);
INVX2TS U1482 ( .A(n1237), .Y(n1238) );
NAND2X1TS U1483 ( .A(n1519), .B(n1238), .Y(DP_OP_15J30_123_3372_n8) );
MX2X1TS U1484 ( .A(DMP_exp_NRM2_EW[7]), .B(DMP_exp_NRM_EW[7]), .S0(
Shift_reg_FLAGS_7[1]), .Y(n611) );
MX2X1TS U1485 ( .A(DMP_exp_NRM2_EW[6]), .B(DMP_exp_NRM_EW[6]), .S0(
Shift_reg_FLAGS_7[1]), .Y(n616) );
MX2X1TS U1486 ( .A(DMP_exp_NRM2_EW[5]), .B(DMP_exp_NRM_EW[5]), .S0(
Shift_reg_FLAGS_7[1]), .Y(n621) );
MX2X1TS U1487 ( .A(DMP_exp_NRM2_EW[4]), .B(DMP_exp_NRM_EW[4]), .S0(
Shift_reg_FLAGS_7[1]), .Y(n626) );
MX2X1TS U1488 ( .A(DMP_exp_NRM2_EW[3]), .B(DMP_exp_NRM_EW[3]), .S0(
Shift_reg_FLAGS_7[1]), .Y(n631) );
MX2X1TS U1489 ( .A(DMP_exp_NRM2_EW[2]), .B(DMP_exp_NRM_EW[2]), .S0(
Shift_reg_FLAGS_7[1]), .Y(n636) );
MX2X1TS U1490 ( .A(DMP_exp_NRM2_EW[1]), .B(DMP_exp_NRM_EW[1]), .S0(
Shift_reg_FLAGS_7[1]), .Y(n641) );
MX2X1TS U1491 ( .A(DMP_exp_NRM2_EW[0]), .B(DMP_exp_NRM_EW[0]), .S0(
Shift_reg_FLAGS_7[1]), .Y(n646) );
OAI2BB1X1TS U1492 ( .A0N(LZD_output_NRM2_EW[4]), .A1N(n874), .B0(n1239), .Y(
n512) );
OAI32X1TS U1493 ( .A0(n874), .A1(Raw_mant_NRM_SWR[14]), .A2(n1241), .B0(
n1240), .B1(n874), .Y(n1245) );
AO21XLTS U1494 ( .A0(n1486), .A1(n1509), .B0(n1242), .Y(n1250) );
AOI21X1TS U1495 ( .A0(n1247), .A1(Raw_mant_NRM_SWR[10]), .B0(n1246), .Y(
n1301) );
AOI22X1TS U1496 ( .A0(Raw_mant_NRM_SWR[3]), .A1(n1249), .B0(n1248), .B1(
Raw_mant_NRM_SWR[5]), .Y(n1251) );
OAI21X1TS U1497 ( .A0(n1255), .A1(n1254), .B0(Shift_reg_FLAGS_7[1]), .Y(
n1297) );
OAI2BB1X1TS U1498 ( .A0N(LZD_output_NRM2_EW[2]), .A1N(n874), .B0(n1297), .Y(
n514) );
AO21XLTS U1499 ( .A0(LZD_output_NRM2_EW[1]), .A1(n874), .B0(n1256), .Y(n513)
);
AO21XLTS U1500 ( .A0(LZD_output_NRM2_EW[0]), .A1(n874), .B0(n1283), .Y(n515)
);
OA22X1TS U1501 ( .A0(n1258), .A1(n1257), .B0(Shift_reg_FLAGS_7[0]), .B1(
final_result_ieee[29]), .Y(n755) );
OA21XLTS U1502 ( .A0(Shift_reg_FLAGS_7[0]), .A1(overflow_flag), .B0(n1363),
.Y(n558) );
INVX2TS U1503 ( .A(n1262), .Y(n1260) );
AOI22X1TS U1504 ( .A0(inst_FSM_INPUT_ENABLE_state_reg[1]), .A1(
inst_FSM_INPUT_ENABLE_state_reg[0]), .B0(n1260), .B1(n1501), .Y(
inst_FSM_INPUT_ENABLE_state_next_1_) );
NAND2X1TS U1505 ( .A(n1260), .B(n1259), .Y(n871) );
NOR2XLTS U1506 ( .A(inst_FSM_INPUT_ENABLE_state_reg[2]), .B(
inst_FSM_INPUT_ENABLE_state_reg[1]), .Y(n1261) );
AOI32X4TS U1507 ( .A0(inst_FSM_INPUT_ENABLE_state_reg[1]), .A1(
inst_FSM_INPUT_ENABLE_state_reg[0]), .A2(
inst_FSM_INPUT_ENABLE_state_reg[2]), .B0(n1261), .B1(n1535), .Y(n1265)
);
INVX2TS U1508 ( .A(n1265), .Y(n1264) );
AOI22X1TS U1509 ( .A0(inst_FSM_INPUT_ENABLE_state_reg[1]), .A1(n1262), .B0(
inst_FSM_INPUT_ENABLE_state_reg[2]), .B1(n1501), .Y(n1266) );
AO22XLTS U1510 ( .A0(n1264), .A1(Shift_reg_FLAGS_7_6), .B0(n1265), .B1(n1266), .Y(n869) );
AOI22X1TS U1511 ( .A0(n1265), .A1(n1263), .B0(n1328), .B1(n1264), .Y(n868)
);
AOI22X1TS U1512 ( .A0(n1265), .A1(n1328), .B0(n1579), .B1(n1264), .Y(n867)
);
INVX4TS U1513 ( .A(n1610), .Y(n1353) );
AOI22X1TS U1514 ( .A0(n1265), .A1(n1610), .B0(n874), .B1(n1264), .Y(n864) );
AOI22X1TS U1515 ( .A0(n1265), .A1(n874), .B0(n1423), .B1(n1264), .Y(n863) );
BUFX4TS U1516 ( .A(n1270), .Y(n1271) );
BUFX3TS U1517 ( .A(n1270), .Y(n1272) );
BUFX3TS U1518 ( .A(n1270), .Y(n1269) );
AO22XLTS U1519 ( .A0(n1269), .A1(Data_X[2]), .B0(n875), .B1(intDX_EWSW[2]),
.Y(n860) );
BUFX3TS U1520 ( .A(n1270), .Y(n1275) );
AO22XLTS U1521 ( .A0(n1275), .A1(Data_X[3]), .B0(n875), .B1(intDX_EWSW[3]),
.Y(n859) );
AO22XLTS U1522 ( .A0(n1272), .A1(Data_X[4]), .B0(n1274), .B1(intDX_EWSW[4]),
.Y(n858) );
AO22XLTS U1523 ( .A0(n1271), .A1(Data_X[5]), .B0(n875), .B1(intDX_EWSW[5]),
.Y(n857) );
AO22XLTS U1524 ( .A0(n1271), .A1(Data_X[6]), .B0(n875), .B1(intDX_EWSW[6]),
.Y(n856) );
AO22XLTS U1525 ( .A0(n1270), .A1(Data_X[7]), .B0(n1274), .B1(intDX_EWSW[7]),
.Y(n855) );
AO22XLTS U1526 ( .A0(n1275), .A1(Data_X[8]), .B0(n875), .B1(intDX_EWSW[8]),
.Y(n854) );
AO22XLTS U1527 ( .A0(n1275), .A1(Data_X[9]), .B0(n875), .B1(intDX_EWSW[9]),
.Y(n853) );
AO22XLTS U1528 ( .A0(n1275), .A1(Data_X[11]), .B0(n1274), .B1(intDX_EWSW[11]), .Y(n851) );
AO22XLTS U1529 ( .A0(n1271), .A1(Data_X[12]), .B0(n875), .B1(intDX_EWSW[12]),
.Y(n850) );
AO22XLTS U1530 ( .A0(n1272), .A1(Data_X[13]), .B0(n875), .B1(intDX_EWSW[13]),
.Y(n849) );
AO22XLTS U1531 ( .A0(n1270), .A1(Data_X[14]), .B0(n1274), .B1(intDX_EWSW[14]), .Y(n848) );
INVX2TS U1532 ( .A(n1272), .Y(n1274) );
AO22XLTS U1533 ( .A0(n1271), .A1(Data_X[15]), .B0(n1274), .B1(intDX_EWSW[15]), .Y(n847) );
AO22XLTS U1534 ( .A0(n1269), .A1(Data_X[16]), .B0(n875), .B1(intDX_EWSW[16]),
.Y(n846) );
AO22XLTS U1535 ( .A0(n1271), .A1(Data_X[17]), .B0(n875), .B1(intDX_EWSW[17]),
.Y(n845) );
AO22XLTS U1536 ( .A0(n1270), .A1(Data_X[20]), .B0(n1274), .B1(intDX_EWSW[20]), .Y(n842) );
AO22XLTS U1537 ( .A0(n1272), .A1(Data_X[21]), .B0(n875), .B1(intDX_EWSW[21]),
.Y(n841) );
AO22XLTS U1538 ( .A0(n1272), .A1(Data_X[22]), .B0(n875), .B1(intDX_EWSW[22]),
.Y(n840) );
AO22XLTS U1539 ( .A0(n1269), .A1(Data_X[23]), .B0(n1274), .B1(intDX_EWSW[23]), .Y(n839) );
INVX2TS U1540 ( .A(n1270), .Y(n1267) );
AO22XLTS U1541 ( .A0(n1267), .A1(intDX_EWSW[24]), .B0(n1270), .B1(Data_X[24]), .Y(n838) );
AO22XLTS U1542 ( .A0(n1267), .A1(intDX_EWSW[25]), .B0(n1275), .B1(Data_X[25]), .Y(n837) );
AO22XLTS U1543 ( .A0(n1267), .A1(intDX_EWSW[26]), .B0(n1270), .B1(Data_X[26]), .Y(n836) );
AO22XLTS U1544 ( .A0(n1275), .A1(Data_X[28]), .B0(n875), .B1(intDX_EWSW[28]),
.Y(n834) );
AO22XLTS U1545 ( .A0(n1271), .A1(add_subt), .B0(n1267), .B1(intAS), .Y(n830)
);
AO22XLTS U1546 ( .A0(n1267), .A1(intDY_EWSW[0]), .B0(n1275), .B1(Data_Y[0]),
.Y(n828) );
AO22XLTS U1547 ( .A0(n1267), .A1(intDY_EWSW[1]), .B0(n1269), .B1(Data_Y[1]),
.Y(n827) );
AO22XLTS U1548 ( .A0(n1267), .A1(intDY_EWSW[2]), .B0(n1269), .B1(Data_Y[2]),
.Y(n826) );
AO22XLTS U1549 ( .A0(n1267), .A1(intDY_EWSW[3]), .B0(n1269), .B1(Data_Y[3]),
.Y(n825) );
AO22XLTS U1550 ( .A0(n1268), .A1(intDY_EWSW[4]), .B0(n1269), .B1(Data_Y[4]),
.Y(n824) );
AO22XLTS U1551 ( .A0(n1273), .A1(intDY_EWSW[5]), .B0(n1269), .B1(Data_Y[5]),
.Y(n823) );
INVX2TS U1552 ( .A(n1270), .Y(n1268) );
AO22XLTS U1553 ( .A0(n1273), .A1(intDY_EWSW[6]), .B0(n1269), .B1(Data_Y[6]),
.Y(n822) );
AO22XLTS U1554 ( .A0(n1268), .A1(intDY_EWSW[7]), .B0(n1269), .B1(Data_Y[7]),
.Y(n821) );
AO22XLTS U1555 ( .A0(n1273), .A1(intDY_EWSW[8]), .B0(n1269), .B1(Data_Y[8]),
.Y(n820) );
AO22XLTS U1556 ( .A0(n1268), .A1(intDY_EWSW[9]), .B0(n1270), .B1(Data_Y[9]),
.Y(n819) );
AO22XLTS U1557 ( .A0(n1273), .A1(intDY_EWSW[10]), .B0(n1271), .B1(Data_Y[10]), .Y(n818) );
AO22XLTS U1558 ( .A0(n1268), .A1(intDY_EWSW[11]), .B0(n1272), .B1(Data_Y[11]), .Y(n817) );
AO22XLTS U1559 ( .A0(n1273), .A1(intDY_EWSW[12]), .B0(n1271), .B1(Data_Y[12]), .Y(n816) );
AO22XLTS U1560 ( .A0(n1273), .A1(intDY_EWSW[13]), .B0(n1271), .B1(Data_Y[13]), .Y(n815) );
AO22XLTS U1561 ( .A0(n1268), .A1(intDY_EWSW[14]), .B0(n1271), .B1(Data_Y[14]), .Y(n814) );
AO22XLTS U1562 ( .A0(n1273), .A1(intDY_EWSW[15]), .B0(n1271), .B1(Data_Y[15]), .Y(n813) );
AO22XLTS U1563 ( .A0(n1273), .A1(intDY_EWSW[16]), .B0(n1271), .B1(Data_Y[16]), .Y(n812) );
AO22XLTS U1564 ( .A0(n1268), .A1(intDY_EWSW[17]), .B0(n1271), .B1(Data_Y[17]), .Y(n811) );
AO22XLTS U1565 ( .A0(n1273), .A1(intDY_EWSW[18]), .B0(n1271), .B1(Data_Y[18]), .Y(n810) );
AO22XLTS U1566 ( .A0(n1273), .A1(intDY_EWSW[19]), .B0(n1271), .B1(Data_Y[19]), .Y(n809) );
AO22XLTS U1567 ( .A0(n1268), .A1(intDY_EWSW[20]), .B0(n1271), .B1(Data_Y[20]), .Y(n808) );
AO22XLTS U1568 ( .A0(n1273), .A1(intDY_EWSW[21]), .B0(n1271), .B1(Data_Y[21]), .Y(n807) );
AO22XLTS U1569 ( .A0(n1273), .A1(intDY_EWSW[22]), .B0(n1275), .B1(Data_Y[22]), .Y(n806) );
AO22XLTS U1570 ( .A0(n1268), .A1(intDY_EWSW[23]), .B0(n1275), .B1(Data_Y[23]), .Y(n805) );
AO22XLTS U1571 ( .A0(n1268), .A1(intDY_EWSW[24]), .B0(n1275), .B1(Data_Y[24]), .Y(n804) );
AO22XLTS U1572 ( .A0(n1273), .A1(intDY_EWSW[25]), .B0(n1270), .B1(Data_Y[25]), .Y(n803) );
AO22XLTS U1573 ( .A0(n1273), .A1(intDY_EWSW[26]), .B0(n1269), .B1(Data_Y[26]), .Y(n802) );
AO22XLTS U1574 ( .A0(n1273), .A1(intDY_EWSW[27]), .B0(n1270), .B1(Data_Y[27]), .Y(n801) );
AO22XLTS U1575 ( .A0(n1273), .A1(intDY_EWSW[28]), .B0(n1270), .B1(Data_Y[28]), .Y(n800) );
AO22XLTS U1576 ( .A0(n1268), .A1(intDY_EWSW[29]), .B0(n1271), .B1(Data_Y[29]), .Y(n799) );
AO22XLTS U1577 ( .A0(n1273), .A1(intDY_EWSW[30]), .B0(n1272), .B1(Data_Y[30]), .Y(n798) );
AOI21X1TS U1578 ( .A0(n906), .A1(Raw_mant_NRM_SWR[0]), .B0(n910), .Y(n1277)
);
OAI2BB2XLTS U1579 ( .B0(n1277), .B1(n1142), .A0N(n1296), .A1N(
Data_array_SWR[25]), .Y(n796) );
OAI2BB2XLTS U1580 ( .B0(n1276), .B1(n1142), .A0N(n1296), .A1N(
Data_array_SWR[24]), .Y(n795) );
OAI222X1TS U1581 ( .A0(n1568), .A1(n1299), .B0(n1142), .B1(n1278), .C0(n1159), .C1(n1277), .Y(n794) );
AOI22X1TS U1582 ( .A0(Raw_mant_NRM_SWR[10]), .A1(n1283), .B0(n1282), .B1(
DmP_mant_SHT1_SW[13]), .Y(n1279) );
AOI21X1TS U1583 ( .A0(n910), .A1(DmP_mant_SHT1_SW[12]), .B0(n1280), .Y(n1287) );
OAI222X1TS U1584 ( .A0(n1299), .A1(n1570), .B0(n1142), .B1(n1287), .C0(n1159), .C1(n1281), .Y(n785) );
AOI22X1TS U1585 ( .A0(Raw_mant_NRM_SWR[12]), .A1(n1283), .B0(n1282), .B1(
n902), .Y(n1284) );
AOI21X1TS U1586 ( .A0(n910), .A1(DmP_mant_SHT1_SW[10]), .B0(n1286), .Y(n1288) );
OAI222X1TS U1587 ( .A0(n1569), .A1(n1299), .B0(n1142), .B1(n1288), .C0(n1159), .C1(n1287), .Y(n783) );
OAI222X1TS U1588 ( .A0(n1576), .A1(n1299), .B0(n1142), .B1(n1289), .C0(n1159), .C1(n1288), .Y(n781) );
AOI22X1TS U1589 ( .A0(n1296), .A1(Data_array_SWR[0]), .B0(
Raw_mant_NRM_SWR[24]), .B1(n1291), .Y(n1295) );
AOI22X1TS U1590 ( .A0(Raw_mant_NRM_SWR[25]), .A1(n906), .B0(n1293), .B1(
n1292), .Y(n1294) );
NAND2X1TS U1591 ( .A(n1295), .B(n1294), .Y(n771) );
NAND2X1TS U1592 ( .A(n1298), .B(n1297), .Y(n770) );
AOI21X1TS U1593 ( .A0(n873), .A1(Shift_amount_SHT1_EWR[3]), .B0(
Shift_reg_FLAGS_7[1]), .Y(n1300) );
OAI22X1TS U1594 ( .A0(n1301), .A1(n1300), .B0(n1299), .B1(n1516), .Y(n769)
);
INVX4TS U1595 ( .A(n1328), .Y(n1335) );
CLKINVX1TS U1596 ( .A(DmP_EXP_EWSW[23]), .Y(n1302) );
AOI21X1TS U1597 ( .A0(DMP_EXP_EWSW[23]), .A1(n1302), .B0(n1307), .Y(n1303)
);
INVX4TS U1598 ( .A(n1328), .Y(n1337) );
AOI2BB2XLTS U1599 ( .B0(n1335), .B1(n1303), .A0N(Shift_amount_SHT1_EWR[0]),
.A1N(n1337), .Y(n766) );
NOR2X1TS U1600 ( .A(n1507), .B(DMP_EXP_EWSW[24]), .Y(n1306) );
AOI21X1TS U1601 ( .A0(DMP_EXP_EWSW[24]), .A1(n1507), .B0(n1306), .Y(n1304)
);
XNOR2X1TS U1602 ( .A(n1307), .B(n1304), .Y(n1305) );
AO22XLTS U1603 ( .A0(n1337), .A1(n1305), .B0(n1328), .B1(
Shift_amount_SHT1_EWR[1]), .Y(n765) );
INVX4TS U1604 ( .A(n1328), .Y(n1325) );
OAI22X1TS U1605 ( .A0(n1307), .A1(n1306), .B0(DmP_EXP_EWSW[24]), .B1(n1508),
.Y(n1310) );
NAND2X1TS U1606 ( .A(DmP_EXP_EWSW[25]), .B(n1560), .Y(n1311) );
OAI21XLTS U1607 ( .A0(DmP_EXP_EWSW[25]), .A1(n1560), .B0(n1311), .Y(n1308)
);
XNOR2X1TS U1608 ( .A(n1310), .B(n1308), .Y(n1309) );
AO22XLTS U1609 ( .A0(n1325), .A1(n1309), .B0(n1577), .B1(
Shift_amount_SHT1_EWR[2]), .Y(n764) );
AOI22X1TS U1610 ( .A0(DMP_EXP_EWSW[25]), .A1(n1572), .B0(n1311), .B1(n1310),
.Y(n1314) );
NOR2X1TS U1611 ( .A(n1510), .B(DMP_EXP_EWSW[26]), .Y(n1315) );
AOI21X1TS U1612 ( .A0(DMP_EXP_EWSW[26]), .A1(n1510), .B0(n1315), .Y(n1312)
);
XNOR2X1TS U1613 ( .A(n1314), .B(n1312), .Y(n1313) );
AO22XLTS U1614 ( .A0(n1337), .A1(n1313), .B0(n1577), .B1(
Shift_amount_SHT1_EWR[3]), .Y(n763) );
OAI22X1TS U1615 ( .A0(n1315), .A1(n1314), .B0(DmP_EXP_EWSW[26]), .B1(n1512),
.Y(n1317) );
XNOR2X1TS U1616 ( .A(DmP_EXP_EWSW[27]), .B(n904), .Y(n1316) );
XOR2XLTS U1617 ( .A(n1317), .B(n1316), .Y(n1318) );
BUFX3TS U1618 ( .A(n1577), .Y(n1327) );
AO22XLTS U1619 ( .A0(n1325), .A1(n1318), .B0(n1327), .B1(
Shift_amount_SHT1_EWR[4]), .Y(n762) );
OAI222X1TS U1620 ( .A0(n1330), .A1(n1571), .B0(n1508), .B1(
Shift_reg_FLAGS_7_6), .C0(n1491), .C1(n1332), .Y(n729) );
OAI222X1TS U1621 ( .A0(n1330), .A1(n1511), .B0(n1560), .B1(
Shift_reg_FLAGS_7_6), .C0(n1614), .C1(n1332), .Y(n728) );
OAI222X1TS U1622 ( .A0(n1330), .A1(n1575), .B0(n1512), .B1(
Shift_reg_FLAGS_7_6), .C0(n1551), .C1(n1332), .Y(n727) );
OAI21XLTS U1623 ( .A0(n1320), .A1(intDX_EWSW[31]), .B0(Shift_reg_FLAGS_7_6),
.Y(n1319) );
AOI21X1TS U1624 ( .A0(n1320), .A1(intDX_EWSW[31]), .B0(n1319), .Y(n1322) );
AO21XLTS U1625 ( .A0(OP_FLAG_EXP), .A1(n1321), .B0(n1322), .Y(n722) );
AO22XLTS U1626 ( .A0(n1323), .A1(n1322), .B0(ZERO_FLAG_EXP), .B1(n1321), .Y(
n721) );
AO22XLTS U1627 ( .A0(n1325), .A1(DMP_EXP_EWSW[0]), .B0(n1327), .B1(
DMP_SHT1_EWSW[0]), .Y(n719) );
AO22XLTS U1628 ( .A0(busy), .A1(DMP_SHT1_EWSW[0]), .B0(n1579), .B1(
DMP_SHT2_EWSW[0]), .Y(n718) );
BUFX3TS U1629 ( .A(n1324), .Y(n1458) );
INVX4TS U1630 ( .A(n1458), .Y(n1455) );
AO22XLTS U1631 ( .A0(n1337), .A1(DMP_EXP_EWSW[1]), .B0(n1327), .B1(
DMP_SHT1_EWSW[1]), .Y(n716) );
AO22XLTS U1632 ( .A0(busy), .A1(DMP_SHT1_EWSW[1]), .B0(n1579), .B1(
DMP_SHT2_EWSW[1]), .Y(n715) );
AO22XLTS U1633 ( .A0(n1325), .A1(DMP_EXP_EWSW[2]), .B0(n1327), .B1(
DMP_SHT1_EWSW[2]), .Y(n713) );
AO22XLTS U1634 ( .A0(busy), .A1(DMP_SHT1_EWSW[2]), .B0(n1579), .B1(
DMP_SHT2_EWSW[2]), .Y(n712) );
BUFX3TS U1635 ( .A(n1458), .Y(n1442) );
INVX4TS U1636 ( .A(n1458), .Y(n1457) );
AO22XLTS U1637 ( .A0(n1442), .A1(DMP_SFG[2]), .B0(n1457), .B1(
DMP_SHT2_EWSW[2]), .Y(n711) );
AO22XLTS U1638 ( .A0(n1325), .A1(DMP_EXP_EWSW[3]), .B0(n1327), .B1(
DMP_SHT1_EWSW[3]), .Y(n710) );
AO22XLTS U1639 ( .A0(busy), .A1(DMP_SHT1_EWSW[3]), .B0(n1579), .B1(
DMP_SHT2_EWSW[3]), .Y(n709) );
AO22XLTS U1640 ( .A0(n1442), .A1(DMP_SFG[3]), .B0(n1457), .B1(
DMP_SHT2_EWSW[3]), .Y(n708) );
AO22XLTS U1641 ( .A0(n1325), .A1(DMP_EXP_EWSW[4]), .B0(n1327), .B1(
DMP_SHT1_EWSW[4]), .Y(n707) );
AO22XLTS U1642 ( .A0(busy), .A1(DMP_SHT1_EWSW[4]), .B0(n1579), .B1(
DMP_SHT2_EWSW[4]), .Y(n706) );
AO22XLTS U1643 ( .A0(n1442), .A1(DMP_SFG[4]), .B0(n1457), .B1(
DMP_SHT2_EWSW[4]), .Y(n705) );
AO22XLTS U1644 ( .A0(n1325), .A1(DMP_EXP_EWSW[5]), .B0(n1327), .B1(
DMP_SHT1_EWSW[5]), .Y(n704) );
AO22XLTS U1645 ( .A0(busy), .A1(DMP_SHT1_EWSW[5]), .B0(n1579), .B1(
DMP_SHT2_EWSW[5]), .Y(n703) );
AO22XLTS U1646 ( .A0(n1476), .A1(DMP_SHT2_EWSW[5]), .B0(n1480), .B1(
DMP_SFG[5]), .Y(n702) );
AO22XLTS U1647 ( .A0(n1325), .A1(DMP_EXP_EWSW[6]), .B0(n1327), .B1(
DMP_SHT1_EWSW[6]), .Y(n701) );
AO22XLTS U1648 ( .A0(busy), .A1(DMP_SHT1_EWSW[6]), .B0(n1579), .B1(
DMP_SHT2_EWSW[6]), .Y(n700) );
BUFX3TS U1649 ( .A(n1458), .Y(n1451) );
AO22XLTS U1650 ( .A0(n1451), .A1(DMP_SFG[6]), .B0(n1457), .B1(
DMP_SHT2_EWSW[6]), .Y(n699) );
AO22XLTS U1651 ( .A0(n1325), .A1(DMP_EXP_EWSW[7]), .B0(n1327), .B1(
DMP_SHT1_EWSW[7]), .Y(n698) );
AO22XLTS U1652 ( .A0(busy), .A1(DMP_SHT1_EWSW[7]), .B0(n1579), .B1(
DMP_SHT2_EWSW[7]), .Y(n697) );
AO22XLTS U1653 ( .A0(n1442), .A1(DMP_SFG[7]), .B0(n1457), .B1(
DMP_SHT2_EWSW[7]), .Y(n696) );
AO22XLTS U1654 ( .A0(n1325), .A1(DMP_EXP_EWSW[8]), .B0(n1327), .B1(
DMP_SHT1_EWSW[8]), .Y(n695) );
AO22XLTS U1655 ( .A0(busy), .A1(DMP_SHT1_EWSW[8]), .B0(n1579), .B1(
DMP_SHT2_EWSW[8]), .Y(n694) );
AO22XLTS U1656 ( .A0(n1442), .A1(DMP_SFG[8]), .B0(n1457), .B1(
DMP_SHT2_EWSW[8]), .Y(n693) );
AO22XLTS U1657 ( .A0(n1325), .A1(DMP_EXP_EWSW[9]), .B0(n1327), .B1(
DMP_SHT1_EWSW[9]), .Y(n692) );
AO22XLTS U1658 ( .A0(busy), .A1(DMP_SHT1_EWSW[9]), .B0(n1579), .B1(
DMP_SHT2_EWSW[9]), .Y(n691) );
AO22XLTS U1659 ( .A0(n1476), .A1(DMP_SHT2_EWSW[9]), .B0(n1480), .B1(
DMP_SFG[9]), .Y(n690) );
AO22XLTS U1660 ( .A0(n1325), .A1(DMP_EXP_EWSW[10]), .B0(n1327), .B1(
DMP_SHT1_EWSW[10]), .Y(n689) );
BUFX4TS U1661 ( .A(n1579), .Y(n1334) );
AO22XLTS U1662 ( .A0(n873), .A1(DMP_SHT1_EWSW[10]), .B0(n1334), .B1(
DMP_SHT2_EWSW[10]), .Y(n688) );
AO22XLTS U1663 ( .A0(n1442), .A1(DMP_SFG[10]), .B0(n1455), .B1(
DMP_SHT2_EWSW[10]), .Y(n687) );
BUFX4TS U1664 ( .A(n1577), .Y(n1329) );
AO22XLTS U1665 ( .A0(n1325), .A1(DMP_EXP_EWSW[11]), .B0(n1329), .B1(
DMP_SHT1_EWSW[11]), .Y(n686) );
AO22XLTS U1666 ( .A0(n873), .A1(DMP_SHT1_EWSW[11]), .B0(n1334), .B1(
DMP_SHT2_EWSW[11]), .Y(n685) );
AO22XLTS U1667 ( .A0(n1451), .A1(DMP_SFG[11]), .B0(n1457), .B1(
DMP_SHT2_EWSW[11]), .Y(n684) );
AO22XLTS U1668 ( .A0(n1325), .A1(DMP_EXP_EWSW[12]), .B0(n1577), .B1(
DMP_SHT1_EWSW[12]), .Y(n683) );
AO22XLTS U1669 ( .A0(n873), .A1(DMP_SHT1_EWSW[12]), .B0(n1334), .B1(
DMP_SHT2_EWSW[12]), .Y(n682) );
AO22XLTS U1670 ( .A0(n1442), .A1(DMP_SFG[12]), .B0(n1457), .B1(
DMP_SHT2_EWSW[12]), .Y(n681) );
BUFX3TS U1671 ( .A(n1577), .Y(n1336) );
AO22XLTS U1672 ( .A0(n1325), .A1(DMP_EXP_EWSW[13]), .B0(n1336), .B1(
DMP_SHT1_EWSW[13]), .Y(n680) );
AO22XLTS U1673 ( .A0(n873), .A1(DMP_SHT1_EWSW[13]), .B0(n1334), .B1(
DMP_SHT2_EWSW[13]), .Y(n679) );
AO22XLTS U1674 ( .A0(n1451), .A1(DMP_SFG[13]), .B0(n1457), .B1(
DMP_SHT2_EWSW[13]), .Y(n678) );
AO22XLTS U1675 ( .A0(n1325), .A1(DMP_EXP_EWSW[14]), .B0(n1329), .B1(
DMP_SHT1_EWSW[14]), .Y(n677) );
AO22XLTS U1676 ( .A0(n873), .A1(DMP_SHT1_EWSW[14]), .B0(n1334), .B1(
DMP_SHT2_EWSW[14]), .Y(n676) );
AO22XLTS U1677 ( .A0(n1442), .A1(DMP_SFG[14]), .B0(n1457), .B1(
DMP_SHT2_EWSW[14]), .Y(n675) );
AO22XLTS U1678 ( .A0(n1325), .A1(DMP_EXP_EWSW[15]), .B0(n1577), .B1(
DMP_SHT1_EWSW[15]), .Y(n674) );
AO22XLTS U1679 ( .A0(n873), .A1(DMP_SHT1_EWSW[15]), .B0(n1334), .B1(
DMP_SHT2_EWSW[15]), .Y(n673) );
AO22XLTS U1680 ( .A0(n1451), .A1(DMP_SFG[15]), .B0(n1457), .B1(
DMP_SHT2_EWSW[15]), .Y(n672) );
AO22XLTS U1681 ( .A0(n1325), .A1(DMP_EXP_EWSW[16]), .B0(n1336), .B1(
DMP_SHT1_EWSW[16]), .Y(n671) );
AO22XLTS U1682 ( .A0(busy), .A1(DMP_SHT1_EWSW[16]), .B0(n1334), .B1(
DMP_SHT2_EWSW[16]), .Y(n670) );
AO22XLTS U1683 ( .A0(n1442), .A1(DMP_SFG[16]), .B0(n1455), .B1(
DMP_SHT2_EWSW[16]), .Y(n669) );
AO22XLTS U1684 ( .A0(n1337), .A1(DMP_EXP_EWSW[17]), .B0(n1329), .B1(
DMP_SHT1_EWSW[17]), .Y(n668) );
AO22XLTS U1685 ( .A0(busy), .A1(DMP_SHT1_EWSW[17]), .B0(n1334), .B1(
DMP_SHT2_EWSW[17]), .Y(n667) );
AO22XLTS U1686 ( .A0(n1451), .A1(DMP_SFG[17]), .B0(n1457), .B1(
DMP_SHT2_EWSW[17]), .Y(n666) );
AO22XLTS U1687 ( .A0(n1337), .A1(DMP_EXP_EWSW[18]), .B0(n1328), .B1(
DMP_SHT1_EWSW[18]), .Y(n665) );
AO22XLTS U1688 ( .A0(busy), .A1(DMP_SHT1_EWSW[18]), .B0(n1334), .B1(
DMP_SHT2_EWSW[18]), .Y(n664) );
AO22XLTS U1689 ( .A0(n1442), .A1(DMP_SFG[18]), .B0(n1455), .B1(
DMP_SHT2_EWSW[18]), .Y(n663) );
AO22XLTS U1690 ( .A0(n1337), .A1(DMP_EXP_EWSW[19]), .B0(n1336), .B1(
DMP_SHT1_EWSW[19]), .Y(n662) );
AO22XLTS U1691 ( .A0(busy), .A1(DMP_SHT1_EWSW[19]), .B0(n1334), .B1(
DMP_SHT2_EWSW[19]), .Y(n661) );
AO22XLTS U1692 ( .A0(n1451), .A1(DMP_SFG[19]), .B0(n1457), .B1(
DMP_SHT2_EWSW[19]), .Y(n660) );
AO22XLTS U1693 ( .A0(n1337), .A1(DMP_EXP_EWSW[20]), .B0(n1329), .B1(
DMP_SHT1_EWSW[20]), .Y(n659) );
AO22XLTS U1694 ( .A0(busy), .A1(DMP_SHT1_EWSW[20]), .B0(n1334), .B1(
DMP_SHT2_EWSW[20]), .Y(n658) );
AO22XLTS U1695 ( .A0(n1451), .A1(DMP_SFG[20]), .B0(n1455), .B1(
DMP_SHT2_EWSW[20]), .Y(n657) );
AO22XLTS U1696 ( .A0(n1337), .A1(DMP_EXP_EWSW[21]), .B0(n1328), .B1(
DMP_SHT1_EWSW[21]), .Y(n656) );
AO22XLTS U1697 ( .A0(busy), .A1(DMP_SHT1_EWSW[21]), .B0(n1334), .B1(
DMP_SHT2_EWSW[21]), .Y(n655) );
AO22XLTS U1698 ( .A0(n1451), .A1(DMP_SFG[21]), .B0(n1455), .B1(
DMP_SHT2_EWSW[21]), .Y(n654) );
AO22XLTS U1699 ( .A0(n1337), .A1(DMP_EXP_EWSW[22]), .B0(n1336), .B1(
DMP_SHT1_EWSW[22]), .Y(n653) );
AO22XLTS U1700 ( .A0(busy), .A1(DMP_SHT1_EWSW[22]), .B0(n1579), .B1(
DMP_SHT2_EWSW[22]), .Y(n652) );
AO22XLTS U1701 ( .A0(n1451), .A1(DMP_SFG[22]), .B0(n1455), .B1(
DMP_SHT2_EWSW[22]), .Y(n651) );
AO22XLTS U1702 ( .A0(n1337), .A1(DMP_EXP_EWSW[23]), .B0(n1336), .B1(
DMP_SHT1_EWSW[23]), .Y(n650) );
AO22XLTS U1703 ( .A0(n873), .A1(DMP_SHT1_EWSW[23]), .B0(n1579), .B1(
DMP_SHT2_EWSW[23]), .Y(n649) );
AO22XLTS U1704 ( .A0(n1476), .A1(DMP_SHT2_EWSW[23]), .B0(n1324), .B1(
DMP_SFG[23]), .Y(n648) );
AO22XLTS U1705 ( .A0(n1353), .A1(DMP_SFG[23]), .B0(n1361), .B1(
DMP_exp_NRM_EW[0]), .Y(n647) );
AO22XLTS U1706 ( .A0(n1337), .A1(DMP_EXP_EWSW[24]), .B0(n1336), .B1(
DMP_SHT1_EWSW[24]), .Y(n645) );
AO22XLTS U1707 ( .A0(n873), .A1(DMP_SHT1_EWSW[24]), .B0(n1334), .B1(
DMP_SHT2_EWSW[24]), .Y(n644) );
AO22XLTS U1708 ( .A0(n1455), .A1(DMP_SHT2_EWSW[24]), .B0(n1324), .B1(
DMP_SFG[24]), .Y(n643) );
AO22XLTS U1709 ( .A0(n1353), .A1(DMP_SFG[24]), .B0(n1610), .B1(
DMP_exp_NRM_EW[1]), .Y(n642) );
AO22XLTS U1710 ( .A0(n1337), .A1(DMP_EXP_EWSW[25]), .B0(n1336), .B1(
DMP_SHT1_EWSW[25]), .Y(n640) );
AO22XLTS U1711 ( .A0(n873), .A1(DMP_SHT1_EWSW[25]), .B0(n1334), .B1(
DMP_SHT2_EWSW[25]), .Y(n639) );
AO22XLTS U1712 ( .A0(n1476), .A1(DMP_SHT2_EWSW[25]), .B0(n1324), .B1(
DMP_SFG[25]), .Y(n638) );
AO22XLTS U1713 ( .A0(n1353), .A1(DMP_SFG[25]), .B0(n1610), .B1(
DMP_exp_NRM_EW[2]), .Y(n637) );
AO22XLTS U1714 ( .A0(n1337), .A1(DMP_EXP_EWSW[26]), .B0(n1336), .B1(
DMP_SHT1_EWSW[26]), .Y(n635) );
AO22XLTS U1715 ( .A0(n873), .A1(DMP_SHT1_EWSW[26]), .B0(n1334), .B1(
DMP_SHT2_EWSW[26]), .Y(n634) );
AO22XLTS U1716 ( .A0(n1476), .A1(DMP_SHT2_EWSW[26]), .B0(n1324), .B1(
DMP_SFG[26]), .Y(n633) );
AO22XLTS U1717 ( .A0(n1353), .A1(DMP_SFG[26]), .B0(n1610), .B1(
DMP_exp_NRM_EW[3]), .Y(n632) );
AO22XLTS U1718 ( .A0(n1337), .A1(n904), .B0(n1336), .B1(DMP_SHT1_EWSW[27]),
.Y(n630) );
AO22XLTS U1719 ( .A0(n873), .A1(DMP_SHT1_EWSW[27]), .B0(n1334), .B1(
DMP_SHT2_EWSW[27]), .Y(n629) );
AO22XLTS U1720 ( .A0(n1455), .A1(DMP_SHT2_EWSW[27]), .B0(n1324), .B1(
DMP_SFG[27]), .Y(n628) );
AO22XLTS U1721 ( .A0(n1353), .A1(DMP_SFG[27]), .B0(n1610), .B1(
DMP_exp_NRM_EW[4]), .Y(n627) );
AO22XLTS U1722 ( .A0(n1337), .A1(DMP_EXP_EWSW[28]), .B0(n1336), .B1(
DMP_SHT1_EWSW[28]), .Y(n625) );
AO22XLTS U1723 ( .A0(n873), .A1(DMP_SHT1_EWSW[28]), .B0(n1334), .B1(
DMP_SHT2_EWSW[28]), .Y(n624) );
AO22XLTS U1724 ( .A0(n1455), .A1(DMP_SHT2_EWSW[28]), .B0(n1442), .B1(
DMP_SFG[28]), .Y(n623) );
AO22XLTS U1725 ( .A0(n1353), .A1(DMP_SFG[28]), .B0(n1610), .B1(
DMP_exp_NRM_EW[5]), .Y(n622) );
AO22XLTS U1726 ( .A0(n1337), .A1(DMP_EXP_EWSW[29]), .B0(n1336), .B1(
DMP_SHT1_EWSW[29]), .Y(n620) );
AO22XLTS U1727 ( .A0(n873), .A1(DMP_SHT1_EWSW[29]), .B0(n1334), .B1(
DMP_SHT2_EWSW[29]), .Y(n619) );
AO22XLTS U1728 ( .A0(n1476), .A1(DMP_SHT2_EWSW[29]), .B0(n1480), .B1(
DMP_SFG[29]), .Y(n618) );
BUFX4TS U1729 ( .A(n1610), .Y(n1361) );
AO22XLTS U1730 ( .A0(n1353), .A1(DMP_SFG[29]), .B0(n1361), .B1(
DMP_exp_NRM_EW[6]), .Y(n617) );
AO22XLTS U1731 ( .A0(n1494), .A1(DMP_EXP_EWSW[30]), .B0(n1336), .B1(
DMP_SHT1_EWSW[30]), .Y(n615) );
AO22XLTS U1732 ( .A0(n873), .A1(DMP_SHT1_EWSW[30]), .B0(n1334), .B1(
DMP_SHT2_EWSW[30]), .Y(n614) );
AO22XLTS U1733 ( .A0(n1455), .A1(DMP_SHT2_EWSW[30]), .B0(n1324), .B1(
DMP_SFG[30]), .Y(n613) );
AO22XLTS U1734 ( .A0(n1353), .A1(DMP_SFG[30]), .B0(n1361), .B1(
DMP_exp_NRM_EW[7]), .Y(n612) );
AO22XLTS U1735 ( .A0(n1494), .A1(DmP_EXP_EWSW[3]), .B0(n1577), .B1(
DmP_mant_SHT1_SW[3]), .Y(n603) );
AO22XLTS U1736 ( .A0(n1494), .A1(DmP_EXP_EWSW[7]), .B0(n1328), .B1(
DmP_mant_SHT1_SW[7]), .Y(n595) );
AO22XLTS U1737 ( .A0(n1335), .A1(DmP_EXP_EWSW[10]), .B0(n1328), .B1(
DmP_mant_SHT1_SW[10]), .Y(n589) );
AO22XLTS U1738 ( .A0(n1335), .A1(DmP_EXP_EWSW[11]), .B0(n1328), .B1(n902),
.Y(n587) );
OAI222X1TS U1739 ( .A0(n1332), .A1(n1571), .B0(n1507), .B1(
Shift_reg_FLAGS_7_6), .C0(n1491), .C1(n1330), .Y(n563) );
OAI222X1TS U1740 ( .A0(n1332), .A1(n1511), .B0(n1572), .B1(
Shift_reg_FLAGS_7_6), .C0(n1614), .C1(n1330), .Y(n562) );
OAI222X1TS U1741 ( .A0(n1332), .A1(n1575), .B0(n1510), .B1(
Shift_reg_FLAGS_7_6), .C0(n1551), .C1(n1330), .Y(n561) );
NAND2X1TS U1742 ( .A(n1364), .B(Shift_reg_FLAGS_7[0]), .Y(n1333) );
OAI2BB1X1TS U1743 ( .A0N(underflow_flag), .A1N(n872), .B0(n1333), .Y(n559)
);
AO22XLTS U1744 ( .A0(n1335), .A1(ZERO_FLAG_EXP), .B0(n1328), .B1(
ZERO_FLAG_SHT1), .Y(n557) );
AO22XLTS U1745 ( .A0(n873), .A1(ZERO_FLAG_SHT1), .B0(n1334), .B1(
ZERO_FLAG_SHT2), .Y(n556) );
AO22XLTS U1746 ( .A0(n1455), .A1(ZERO_FLAG_SHT2), .B0(n1480), .B1(
ZERO_FLAG_SFG), .Y(n555) );
AO22XLTS U1747 ( .A0(n1353), .A1(ZERO_FLAG_SFG), .B0(n1361), .B1(
ZERO_FLAG_NRM), .Y(n554) );
AO22XLTS U1748 ( .A0(Shift_reg_FLAGS_7[1]), .A1(ZERO_FLAG_NRM), .B0(n874),
.B1(ZERO_FLAG_SHT1SHT2), .Y(n553) );
AO22XLTS U1749 ( .A0(Shift_reg_FLAGS_7[0]), .A1(ZERO_FLAG_SHT1SHT2), .B0(
n872), .B1(zero_flag), .Y(n552) );
AO22XLTS U1750 ( .A0(n1335), .A1(OP_FLAG_EXP), .B0(OP_FLAG_SHT1), .B1(n1577),
.Y(n551) );
AO22XLTS U1751 ( .A0(n873), .A1(OP_FLAG_SHT1), .B0(n1579), .B1(OP_FLAG_SHT2),
.Y(n550) );
AO22XLTS U1752 ( .A0(n1451), .A1(OP_FLAG_SFG), .B0(n1455), .B1(OP_FLAG_SHT2),
.Y(n549) );
AO22XLTS U1753 ( .A0(n1337), .A1(SIGN_FLAG_EXP), .B0(n1336), .B1(
SIGN_FLAG_SHT1), .Y(n548) );
AO22XLTS U1754 ( .A0(n873), .A1(SIGN_FLAG_SHT1), .B0(n1579), .B1(
SIGN_FLAG_SHT2), .Y(n547) );
AO22XLTS U1755 ( .A0(n1455), .A1(SIGN_FLAG_SHT2), .B0(n1324), .B1(
SIGN_FLAG_SFG), .Y(n546) );
AO22XLTS U1756 ( .A0(n1353), .A1(SIGN_FLAG_SFG), .B0(n1610), .B1(
SIGN_FLAG_NRM), .Y(n545) );
AO22XLTS U1757 ( .A0(Shift_reg_FLAGS_7[1]), .A1(SIGN_FLAG_NRM), .B0(n874),
.B1(SIGN_FLAG_SHT1SHT2), .Y(n544) );
INVX1TS U1758 ( .A(DmP_mant_SFG_SWR[0]), .Y(n1435) );
AOI22X1TS U1759 ( .A0(DmP_mant_SFG_SWR[0]), .A1(n1355), .B0(n1359), .B1(
n1435), .Y(n1341) );
AOI22X1TS U1760 ( .A0(n1357), .A1(n1341), .B0(n1489), .B1(n1361), .Y(n542)
);
AOI22X1TS U1761 ( .A0(DmP_mant_SFG_SWR[1]), .A1(n1358), .B0(n1354), .B1(n914), .Y(n1342) );
AOI22X1TS U1762 ( .A0(n1357), .A1(n1342), .B0(n1567), .B1(n1361), .Y(n541)
);
OAI21XLTS U1763 ( .A0(n1343), .A1(DMP_SFG[0]), .B0(n1345), .Y(n1344) );
AOI22X1TS U1764 ( .A0(n1357), .A1(n1344), .B0(n1515), .B1(n1361), .Y(n540)
);
XNOR2X1TS U1765 ( .A(DMP_SFG[1]), .B(n1345), .Y(n1346) );
XNOR2X1TS U1766 ( .A(n1346), .B(n894), .Y(n1347) );
AOI22X1TS U1767 ( .A0(n1357), .A1(n1347), .B0(n1561), .B1(n1361), .Y(n539)
);
AOI2BB2XLTS U1768 ( .B0(n924), .B1(intadd_27_SUM_0_), .A0N(
Raw_mant_NRM_SWR[4]), .A1N(n1353), .Y(n538) );
AOI22X1TS U1769 ( .A0(n924), .A1(intadd_27_SUM_1_), .B0(n1522), .B1(n1361),
.Y(n537) );
AOI22X1TS U1770 ( .A0(n924), .A1(intadd_27_SUM_2_), .B0(n1493), .B1(n1361),
.Y(n536) );
XNOR2X1TS U1771 ( .A(DMP_SFG[5]), .B(n895), .Y(n1348) );
XNOR2X1TS U1772 ( .A(intadd_27_n1), .B(n1348), .Y(n1349) );
AOI22X1TS U1773 ( .A0(n1357), .A1(n1349), .B0(n1488), .B1(n1361), .Y(n535)
);
AOI22X1TS U1774 ( .A0(n1357), .A1(intadd_26_SUM_0_), .B0(n1490), .B1(n1361),
.Y(n534) );
AOI22X1TS U1775 ( .A0(n924), .A1(intadd_26_SUM_1_), .B0(n1492), .B1(n1361),
.Y(n533) );
AOI22X1TS U1776 ( .A0(n924), .A1(intadd_26_SUM_2_), .B0(n1487), .B1(n1361),
.Y(n532) );
XNOR2X1TS U1777 ( .A(DMP_SFG[9]), .B(n1350), .Y(n1351) );
XNOR2X1TS U1778 ( .A(intadd_26_n1), .B(n1351), .Y(n1352) );
AOI22X1TS U1779 ( .A0(n924), .A1(n1352), .B0(n1486), .B1(n1361), .Y(n531) );
AOI2BB2XLTS U1780 ( .B0(DmP_mant_SFG_SWR[12]), .B1(n1358), .A0N(n1498),
.A1N(DmP_mant_SFG_SWR[12]), .Y(intadd_25_CI) );
AOI2BB2XLTS U1781 ( .B0(n1353), .B1(intadd_25_SUM_0_), .A0N(
Raw_mant_NRM_SWR[12]), .A1N(n1353), .Y(n530) );
AOI2BB2XLTS U1782 ( .B0(DmP_mant_SFG_SWR[13]), .B1(n1358), .A0N(n1498),
.A1N(DmP_mant_SFG_SWR[13]), .Y(intadd_25_B_1_) );
AOI22X1TS U1783 ( .A0(n1357), .A1(intadd_25_SUM_1_), .B0(n1509), .B1(n1361),
.Y(n529) );
AOI2BB2XLTS U1784 ( .B0(DmP_mant_SFG_SWR[14]), .B1(n1358), .A0N(n1498),
.A1N(DmP_mant_SFG_SWR[14]), .Y(intadd_25_B_2_) );
AOI22X1TS U1785 ( .A0(n1357), .A1(intadd_25_SUM_2_), .B0(n1497), .B1(n1361),
.Y(n528) );
AOI2BB2XLTS U1786 ( .B0(DmP_mant_SFG_SWR[15]), .B1(n1358), .A0N(n1498),
.A1N(DmP_mant_SFG_SWR[15]), .Y(intadd_25_B_3_) );
AOI22X1TS U1787 ( .A0(n1357), .A1(intadd_25_SUM_3_), .B0(n1496), .B1(n1361),
.Y(n527) );
AOI22X1TS U1788 ( .A0(DmP_mant_SFG_SWR[16]), .A1(n1355), .B0(n1354), .B1(
n919), .Y(intadd_25_B_4_) );
AOI22X1TS U1789 ( .A0(n1357), .A1(intadd_25_SUM_4_), .B0(n1485), .B1(n1610),
.Y(n526) );
AOI22X1TS U1790 ( .A0(DmP_mant_SFG_SWR[17]), .A1(n1355), .B0(n1354), .B1(
n912), .Y(intadd_25_B_5_) );
AOI22X1TS U1791 ( .A0(n1357), .A1(intadd_25_SUM_5_), .B0(n1514), .B1(n1610),
.Y(n525) );
INVX1TS U1792 ( .A(DmP_mant_SFG_SWR[18]), .Y(n1461) );
AOI22X1TS U1793 ( .A0(DmP_mant_SFG_SWR[18]), .A1(n1355), .B0(n1354), .B1(
n1461), .Y(intadd_25_B_6_) );
AOI2BB2XLTS U1794 ( .B0(n924), .B1(intadd_25_SUM_6_), .A0N(
Raw_mant_NRM_SWR[18]), .A1N(n1353), .Y(n524) );
INVX1TS U1795 ( .A(DmP_mant_SFG_SWR[19]), .Y(n1463) );
AOI22X1TS U1796 ( .A0(DmP_mant_SFG_SWR[19]), .A1(n1355), .B0(n1354), .B1(
n1463), .Y(intadd_25_B_7_) );
AOI2BB2XLTS U1797 ( .B0(n1353), .B1(intadd_25_SUM_7_), .A0N(
Raw_mant_NRM_SWR[19]), .A1N(n1353), .Y(n523) );
INVX1TS U1798 ( .A(DmP_mant_SFG_SWR[20]), .Y(n1465) );
AOI22X1TS U1799 ( .A0(DmP_mant_SFG_SWR[20]), .A1(n1355), .B0(n1354), .B1(
n1465), .Y(intadd_25_B_8_) );
AOI2BB2XLTS U1800 ( .B0(n924), .B1(intadd_25_SUM_8_), .A0N(
Raw_mant_NRM_SWR[20]), .A1N(n1353), .Y(n522) );
INVX1TS U1801 ( .A(DmP_mant_SFG_SWR[21]), .Y(n1467) );
AOI22X1TS U1802 ( .A0(DmP_mant_SFG_SWR[21]), .A1(n1355), .B0(n1354), .B1(
n1467), .Y(intadd_25_B_9_) );
AOI22X1TS U1803 ( .A0(n1357), .A1(intadd_25_SUM_9_), .B0(n1517), .B1(n1610),
.Y(n521) );
INVX1TS U1804 ( .A(DmP_mant_SFG_SWR[22]), .Y(n1469) );
AOI22X1TS U1805 ( .A0(DmP_mant_SFG_SWR[22]), .A1(n1355), .B0(n1354), .B1(
n1469), .Y(intadd_25_B_10_) );
AOI22X1TS U1806 ( .A0(n1357), .A1(intadd_25_SUM_10_), .B0(n1513), .B1(n1610),
.Y(n520) );
INVX1TS U1807 ( .A(DmP_mant_SFG_SWR[23]), .Y(n1471) );
AOI22X1TS U1808 ( .A0(DmP_mant_SFG_SWR[23]), .A1(n1355), .B0(n1359), .B1(
n1471), .Y(intadd_25_B_11_) );
AOI22X1TS U1809 ( .A0(n1357), .A1(intadd_25_SUM_11_), .B0(n1483), .B1(n1610),
.Y(n519) );
INVX1TS U1810 ( .A(DmP_mant_SFG_SWR[24]), .Y(n1474) );
AOI22X1TS U1811 ( .A0(DmP_mant_SFG_SWR[24]), .A1(n1355), .B0(n1354), .B1(
n1474), .Y(intadd_25_B_12_) );
AOI22X1TS U1812 ( .A0(n1357), .A1(intadd_25_SUM_12_), .B0(n1484), .B1(n1610),
.Y(n518) );
AOI22X1TS U1813 ( .A0(DmP_mant_SFG_SWR[25]), .A1(n1359), .B0(n1358), .B1(
n913), .Y(n1360) );
XNOR2X1TS U1814 ( .A(intadd_25_n1), .B(n1360), .Y(n1362) );
AOI22X1TS U1815 ( .A0(n924), .A1(n1362), .B0(n1495), .B1(n1361), .Y(n517) );
AND3X4TS U1816 ( .A(shift_value_SHT2_EWR[2]), .B(n1521), .C(
shift_value_SHT2_EWR[3]), .Y(n1430) );
NAND2X1TS U1817 ( .A(shift_value_SHT2_EWR[2]), .B(n1516), .Y(n1383) );
NAND2X1TS U1818 ( .A(n1403), .B(n1521), .Y(n1414) );
NOR2XLTS U1819 ( .A(n1478), .B(n1414), .Y(n1367) );
AOI22X1TS U1820 ( .A0(Data_array_SWR[12]), .A1(n1479), .B0(
Data_array_SWR[13]), .B1(n1368), .Y(n1369) );
OAI221X1TS U1821 ( .A0(n1478), .A1(n1371), .B0(n1438), .B1(n1372), .C0(n1369), .Y(n1452) );
AO22XLTS U1822 ( .A0(final_result_ieee[10]), .A1(n872), .B0(n1384), .B1(
n1452), .Y(n511) );
AOI22X1TS U1823 ( .A0(Data_array_SWR[12]), .A1(n1368), .B0(
Data_array_SWR[13]), .B1(n1479), .Y(n1370) );
OAI221X1TS U1824 ( .A0(n1478), .A1(n1372), .B0(n1438), .B1(n1371), .C0(n1370), .Y(n1453) );
AO22XLTS U1825 ( .A0(n1384), .A1(n1453), .B0(final_result_ieee[11]), .B1(
n872), .Y(n510) );
AOI22X1TS U1826 ( .A0(Data_array_SWR[22]), .A1(n1429), .B0(
Data_array_SWR[18]), .B1(n1366), .Y(n1376) );
AOI22X1TS U1827 ( .A0(Data_array_SWR[14]), .A1(n1368), .B0(
Data_array_SWR[11]), .B1(n1479), .Y(n1373) );
OAI221X1TS U1828 ( .A0(n1478), .A1(n1375), .B0(n1438), .B1(n1376), .C0(n1373), .Y(n1450) );
AO22XLTS U1829 ( .A0(n1384), .A1(n1450), .B0(final_result_ieee[9]), .B1(n872), .Y(n509) );
AOI22X1TS U1830 ( .A0(Data_array_SWR[14]), .A1(n1479), .B0(
Data_array_SWR[11]), .B1(n1368), .Y(n1374) );
OAI221X1TS U1831 ( .A0(n1478), .A1(n1376), .B0(n1438), .B1(n1375), .C0(n1374), .Y(n1454) );
AO22XLTS U1832 ( .A0(n1384), .A1(n1454), .B0(final_result_ieee[12]), .B1(
n872), .Y(n508) );
AOI22X1TS U1833 ( .A0(Data_array_SWR[23]), .A1(n1429), .B0(
Data_array_SWR[19]), .B1(n1366), .Y(n1380) );
AOI22X1TS U1834 ( .A0(Data_array_SWR[10]), .A1(n1479), .B0(
Data_array_SWR[15]), .B1(n1368), .Y(n1377) );
OAI221X1TS U1835 ( .A0(n1478), .A1(n1379), .B0(n1438), .B1(n1380), .C0(n1377), .Y(n1449) );
AO22XLTS U1836 ( .A0(n1384), .A1(n1449), .B0(final_result_ieee[8]), .B1(n872), .Y(n507) );
AOI22X1TS U1837 ( .A0(Data_array_SWR[10]), .A1(n1368), .B0(
Data_array_SWR[15]), .B1(n1479), .Y(n1378) );
OAI221X1TS U1838 ( .A0(n1478), .A1(n1380), .B0(n1438), .B1(n1379), .C0(n1378), .Y(n1456) );
AO22XLTS U1839 ( .A0(n1384), .A1(n1456), .B0(final_result_ieee[13]), .B1(
n872), .Y(n506) );
AOI22X1TS U1840 ( .A0(Data_array_SWR[17]), .A1(n1429), .B0(
Data_array_SWR[13]), .B1(n1366), .Y(n1382) );
CLKAND2X2TS U1841 ( .A(n1403), .B(shift_value_SHT2_EWR[4]), .Y(n1396) );
AOI22X1TS U1842 ( .A0(Data_array_SWR[21]), .A1(n1430), .B0(
Data_array_SWR[25]), .B1(n1396), .Y(n1381) );
NAND2X1TS U1843 ( .A(n1382), .B(n1381), .Y(n1386) );
NOR2X1TS U1844 ( .A(shift_value_SHT2_EWR[2]), .B(n1516), .Y(n1389) );
INVX2TS U1845 ( .A(n1383), .Y(n1404) );
INVX2TS U1846 ( .A(n1434), .Y(n1385) );
INVX4TS U1847 ( .A(n1384), .Y(n1428) );
OAI2BB2XLTS U1848 ( .B0(n1448), .B1(n1428), .A0N(final_result_ieee[7]),
.A1N(n872), .Y(n505) );
OAI2BB2XLTS U1849 ( .B0(n1459), .B1(n1428), .A0N(final_result_ieee[14]),
.A1N(n872), .Y(n504) );
AOI22X1TS U1850 ( .A0(Data_array_SWR[12]), .A1(n1366), .B0(
Data_array_SWR[16]), .B1(n1429), .Y(n1388) );
AOI22X1TS U1851 ( .A0(Data_array_SWR[24]), .A1(n1396), .B0(
Data_array_SWR[20]), .B1(n1430), .Y(n1387) );
NAND2X1TS U1852 ( .A(n1388), .B(n1387), .Y(n1391) );
INVX2TS U1853 ( .A(n1426), .Y(n1390) );
OAI2BB2XLTS U1854 ( .B0(n1447), .B1(n1428), .A0N(final_result_ieee[6]),
.A1N(n872), .Y(n503) );
OAI2BB2XLTS U1855 ( .B0(n1460), .B1(n1428), .A0N(final_result_ieee[15]),
.A1N(n872), .Y(n502) );
AOI22X1TS U1856 ( .A0(Data_array_SWR[15]), .A1(n1429), .B0(
Data_array_SWR[11]), .B1(n1366), .Y(n1393) );
AOI22X1TS U1857 ( .A0(Data_array_SWR[23]), .A1(n1396), .B0(
Data_array_SWR[19]), .B1(n1430), .Y(n1392) );
NAND2X1TS U1858 ( .A(n1393), .B(n1392), .Y(n1395) );
AOI22X1TS U1859 ( .A0(Data_array_SWR[22]), .A1(n1404), .B0(
Data_array_SWR[18]), .B1(n1403), .Y(n1420) );
INVX2TS U1860 ( .A(n1420), .Y(n1394) );
OAI2BB2XLTS U1861 ( .B0(n1446), .B1(n1428), .A0N(final_result_ieee[5]),
.A1N(n872), .Y(n501) );
OAI2BB2XLTS U1862 ( .B0(n1462), .B1(n1428), .A0N(final_result_ieee[16]),
.A1N(n872), .Y(n500) );
AOI22X1TS U1863 ( .A0(Data_array_SWR[14]), .A1(n1429), .B0(
Data_array_SWR[10]), .B1(n1366), .Y(n1398) );
AOI22X1TS U1864 ( .A0(Data_array_SWR[22]), .A1(n1396), .B0(
Data_array_SWR[18]), .B1(n1430), .Y(n1397) );
NAND2X1TS U1865 ( .A(n1398), .B(n1397), .Y(n1400) );
AOI22X1TS U1866 ( .A0(Data_array_SWR[23]), .A1(n1404), .B0(
Data_array_SWR[19]), .B1(n1403), .Y(n1417) );
INVX2TS U1867 ( .A(n1417), .Y(n1399) );
OAI2BB2XLTS U1868 ( .B0(n1445), .B1(n1428), .A0N(final_result_ieee[4]),
.A1N(n1423), .Y(n499) );
OAI2BB2XLTS U1869 ( .B0(n1464), .B1(n1428), .A0N(final_result_ieee[17]),
.A1N(n1423), .Y(n498) );
AOI22X1TS U1870 ( .A0(Data_array_SWR[21]), .A1(n1403), .B0(
Data_array_SWR[25]), .B1(n1404), .Y(n1409) );
AOI22X1TS U1871 ( .A0(Data_array_SWR[13]), .A1(n1429), .B0(Data_array_SWR[9]), .B1(n1366), .Y(n1402) );
NAND2X1TS U1872 ( .A(Data_array_SWR[17]), .B(n1430), .Y(n1401) );
OAI211X1TS U1873 ( .A0(n1409), .A1(n1521), .B0(n1402), .C0(n1401), .Y(n1405)
);
AO22X1TS U1874 ( .A0(Data_array_SWR[24]), .A1(n1404), .B0(Data_array_SWR[20]), .B1(n1403), .Y(n1406) );
OAI2BB2XLTS U1875 ( .B0(n1444), .B1(n1428), .A0N(final_result_ieee[3]),
.A1N(n1423), .Y(n497) );
OAI2BB2XLTS U1876 ( .B0(n1466), .B1(n1428), .A0N(final_result_ieee[18]),
.A1N(n1423), .Y(n496) );
AOI22X1TS U1877 ( .A0(Data_array_SWR[12]), .A1(n1429), .B0(Data_array_SWR[8]), .B1(n1366), .Y(n1408) );
AOI22X1TS U1878 ( .A0(Data_array_SWR[16]), .A1(n1430), .B0(
shift_value_SHT2_EWR[4]), .B1(n1406), .Y(n1407) );
NAND2X1TS U1879 ( .A(n1408), .B(n1407), .Y(n1413) );
INVX2TS U1880 ( .A(n1409), .Y(n1412) );
OAI2BB2XLTS U1881 ( .B0(n1443), .B1(n1428), .A0N(final_result_ieee[2]),
.A1N(n1423), .Y(n495) );
OAI2BB2XLTS U1882 ( .B0(n1468), .B1(n1428), .A0N(final_result_ieee[19]),
.A1N(n1423), .Y(n494) );
AOI22X1TS U1883 ( .A0(Data_array_SWR[15]), .A1(n1430), .B0(
Data_array_SWR[11]), .B1(n1429), .Y(n1416) );
INVX2TS U1884 ( .A(n1414), .Y(n1431) );
AOI22X1TS U1885 ( .A0(Data_array_SWR[7]), .A1(n1366), .B0(Data_array_SWR[3]),
.B1(n1431), .Y(n1415) );
OAI211X1TS U1886 ( .A0(n1417), .A1(n1521), .B0(n1416), .C0(n1415), .Y(n1421)
);
AOI22X1TS U1887 ( .A0(Data_array_SWR[22]), .A1(n1368), .B0(n1438), .B1(n1421), .Y(n1441) );
OAI2BB2XLTS U1888 ( .B0(n1441), .B1(n1428), .A0N(final_result_ieee[1]),
.A1N(n1423), .Y(n493) );
AOI22X1TS U1889 ( .A0(Data_array_SWR[14]), .A1(n1430), .B0(
Data_array_SWR[10]), .B1(n1429), .Y(n1419) );
AOI22X1TS U1890 ( .A0(Data_array_SWR[6]), .A1(n1366), .B0(Data_array_SWR[2]),
.B1(n1431), .Y(n1418) );
OAI211X1TS U1891 ( .A0(n1420), .A1(n1521), .B0(n1419), .C0(n1418), .Y(n1422)
);
AOI22X1TS U1892 ( .A0(Data_array_SWR[23]), .A1(n1368), .B0(n1438), .B1(n1422), .Y(n1440) );
OAI2BB2XLTS U1893 ( .B0(n1440), .B1(n1428), .A0N(final_result_ieee[0]),
.A1N(n1423), .Y(n492) );
AOI22X1TS U1894 ( .A0(Data_array_SWR[22]), .A1(n1479), .B0(n1478), .B1(n1421), .Y(n1470) );
OAI2BB2XLTS U1895 ( .B0(n1470), .B1(n1428), .A0N(final_result_ieee[20]),
.A1N(n1423), .Y(n491) );
AOI22X1TS U1896 ( .A0(Data_array_SWR[23]), .A1(n1479), .B0(n1478), .B1(n1422), .Y(n1472) );
OAI2BB2XLTS U1897 ( .B0(n1472), .B1(n1428), .A0N(final_result_ieee[21]),
.A1N(n1423), .Y(n490) );
AOI22X1TS U1898 ( .A0(Data_array_SWR[13]), .A1(n1430), .B0(Data_array_SWR[9]), .B1(n1429), .Y(n1425) );
AOI22X1TS U1899 ( .A0(Data_array_SWR[5]), .A1(n1366), .B0(Data_array_SWR[1]),
.B1(n1431), .Y(n1424) );
OAI211X1TS U1900 ( .A0(n1426), .A1(n1521), .B0(n1425), .C0(n1424), .Y(n1437)
);
AOI22X1TS U1901 ( .A0(Data_array_SWR[24]), .A1(n1479), .B0(n1478), .B1(n1437), .Y(n1475) );
OAI2BB2XLTS U1902 ( .B0(n1475), .B1(n1428), .A0N(final_result_ieee[22]),
.A1N(n872), .Y(n489) );
AOI22X1TS U1903 ( .A0(Data_array_SWR[12]), .A1(n1430), .B0(Data_array_SWR[8]), .B1(n1429), .Y(n1433) );
AOI22X1TS U1904 ( .A0(Data_array_SWR[4]), .A1(n1366), .B0(Data_array_SWR[0]),
.B1(n1431), .Y(n1432) );
OAI211X1TS U1905 ( .A0(n1434), .A1(n1521), .B0(n1433), .C0(n1432), .Y(n1477)
);
AOI22X1TS U1906 ( .A0(Data_array_SWR[25]), .A1(n1368), .B0(n1438), .B1(n1477), .Y(n1436) );
AOI22X1TS U1907 ( .A0(n1482), .A1(n1436), .B0(n1435), .B1(n1451), .Y(n488)
);
AOI22X1TS U1908 ( .A0(Data_array_SWR[24]), .A1(n1368), .B0(n1438), .B1(n1437), .Y(n1439) );
AOI22X1TS U1909 ( .A0(n1482), .A1(n1439), .B0(n1451), .B1(n914), .Y(n487) );
AOI22X1TS U1910 ( .A0(n1482), .A1(n1440), .B0(n1458), .B1(n915), .Y(n486) );
AOI22X1TS U1911 ( .A0(n1482), .A1(n1441), .B0(n1480), .B1(n916), .Y(n485) );
AOI22X1TS U1912 ( .A0(n1476), .A1(n1443), .B0(n1442), .B1(n917), .Y(n484) );
AOI22X1TS U1913 ( .A0(n1482), .A1(n1444), .B0(n892), .B1(n1480), .Y(n483) );
AOI22X1TS U1914 ( .A0(n1482), .A1(n1445), .B0(n1458), .B1(n921), .Y(n482) );
AOI22X1TS U1915 ( .A0(n1476), .A1(n1446), .B0(n1480), .B1(n922), .Y(n481) );
AOI22X1TS U1916 ( .A0(n1476), .A1(n1447), .B0(n1458), .B1(n920), .Y(n480) );
AOI22X1TS U1917 ( .A0(n1476), .A1(n1448), .B0(n891), .B1(n1480), .Y(n479) );
AO22XLTS U1918 ( .A0(n1458), .A1(DmP_mant_SFG_SWR[10]), .B0(n1457), .B1(
n1449), .Y(n478) );
AO22XLTS U1919 ( .A0(n1451), .A1(DmP_mant_SFG_SWR[11]), .B0(n1457), .B1(
n1450), .Y(n477) );
AO22XLTS U1920 ( .A0(n1458), .A1(DmP_mant_SFG_SWR[12]), .B0(n1457), .B1(
n1452), .Y(n476) );
AO22XLTS U1921 ( .A0(n1458), .A1(DmP_mant_SFG_SWR[13]), .B0(n1455), .B1(
n1453), .Y(n475) );
AO22XLTS U1922 ( .A0(n1458), .A1(DmP_mant_SFG_SWR[14]), .B0(n1455), .B1(
n1454), .Y(n474) );
AO22XLTS U1923 ( .A0(n1458), .A1(DmP_mant_SFG_SWR[15]), .B0(n1457), .B1(
n1456), .Y(n473) );
AOI22X1TS U1924 ( .A0(n1476), .A1(n1459), .B0(n1480), .B1(n919), .Y(n472) );
AOI22X1TS U1925 ( .A0(n1482), .A1(n1460), .B0(n1480), .B1(n912), .Y(n471) );
AOI22X1TS U1926 ( .A0(n1482), .A1(n1462), .B0(n1461), .B1(n1480), .Y(n470)
);
AOI22X1TS U1927 ( .A0(n1482), .A1(n1464), .B0(n1463), .B1(n1480), .Y(n469)
);
AOI22X1TS U1928 ( .A0(n1482), .A1(n1466), .B0(n1465), .B1(n1480), .Y(n468)
);
AOI22X1TS U1929 ( .A0(n1482), .A1(n1468), .B0(n1467), .B1(n1324), .Y(n467)
);
AOI22X1TS U1930 ( .A0(n1482), .A1(n1470), .B0(n1469), .B1(n1324), .Y(n466)
);
AOI22X1TS U1931 ( .A0(n1482), .A1(n1472), .B0(n1471), .B1(n1324), .Y(n465)
);
AOI22X1TS U1932 ( .A0(n1482), .A1(n1475), .B0(n1474), .B1(n1324), .Y(n464)
);
AOI22X1TS U1933 ( .A0(Data_array_SWR[25]), .A1(n1479), .B0(n1478), .B1(n1477), .Y(n1481) );
AOI22X1TS U1934 ( .A0(n1482), .A1(n1481), .B0(n1480), .B1(n913), .Y(n463) );
initial $sdf_annotate("FPU_PIPELINED_FPADDSUB_ASIC_fpadd_approx_syn_constraints_clk30.tcl_ACAIIN16Q8_syn.sdf");
endmodule
|
module top();
// Inputs are registered
reg A;
reg B;
reg C;
reg D;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
B = 1'bX;
C = 1'bX;
D = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 B = 1'b0;
#60 C = 1'b0;
#80 D = 1'b0;
#100 VGND = 1'b0;
#120 VNB = 1'b0;
#140 VPB = 1'b0;
#160 VPWR = 1'b0;
#180 A = 1'b1;
#200 B = 1'b1;
#220 C = 1'b1;
#240 D = 1'b1;
#260 VGND = 1'b1;
#280 VNB = 1'b1;
#300 VPB = 1'b1;
#320 VPWR = 1'b1;
#340 A = 1'b0;
#360 B = 1'b0;
#380 C = 1'b0;
#400 D = 1'b0;
#420 VGND = 1'b0;
#440 VNB = 1'b0;
#460 VPB = 1'b0;
#480 VPWR = 1'b0;
#500 VPWR = 1'b1;
#520 VPB = 1'b1;
#540 VNB = 1'b1;
#560 VGND = 1'b1;
#580 D = 1'b1;
#600 C = 1'b1;
#620 B = 1'b1;
#640 A = 1'b1;
#660 VPWR = 1'bx;
#680 VPB = 1'bx;
#700 VNB = 1'bx;
#720 VGND = 1'bx;
#740 D = 1'bx;
#760 C = 1'bx;
#780 B = 1'bx;
#800 A = 1'bx;
end
sky130_fd_sc_ms__or4 dut (.A(A), .B(B), .C(C), .D(D), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .X(X));
endmodule
|
module dacclk_mmcm_tb ();
// Clock to Q delay of 100ps
localparam TCQ = 100;
// timescale is 1ps/1ps
localparam ONE_NS = 1000;
localparam PHASE_ERR_MARGIN = 100; // 100ps
// how many cycles to run
localparam COUNT_PHASE = 1024;
// we'll be using the period in many locations
localparam time PER1 = 7.812*ONE_NS;
localparam time PER1_1 = PER1/2;
localparam time PER1_2 = PER1 - PER1/2;
// Declare the input clock signals
reg CLK_IN1 = 1;
// The high bits of the sampling counters
wire [5:1] COUNT;
// Status and control signals
wire LOCKED;
reg COUNTER_RESET = 0;
wire [5:1] CLK_OUT;
//Freq Check using the M & D values setting and actual Frequency generated
real period1;
real ref_period1;
localparam ref_period1_clkin1 = (7.812*1*8.000*1000/8.000);
time prev_rise1;
real period2;
real ref_period2;
localparam ref_period2_clkin1 = (7.812*1*8*1000/8.000);
time prev_rise2;
real period3;
real ref_period3;
localparam ref_period3_clkin1 = (7.812*1*8*1000/8.000);
time prev_rise3;
real period4;
real ref_period4;
localparam ref_period4_clkin1 = (7.812*1*8*1000/8.000);
time prev_rise4;
real period5;
real ref_period5;
localparam ref_period5_clkin1 = (7.812*1*4*1000/8.000);
time prev_rise5;
reg [13:0] timeout_counter = 14'b00000000000000;
// Input clock generation
//------------------------------------
always begin
CLK_IN1 = #PER1_1 ~CLK_IN1;
CLK_IN1 = #PER1_2 ~CLK_IN1;
end
// Test sequence
reg [15*8-1:0] test_phase = "";
initial begin
// Set up any display statements using time to be readable
$timeformat(-12, 2, "ps", 10);
$display ("Timing checks are not valid");
COUNTER_RESET = 0;
test_phase = "wait lock";
`wait_lock;
#(PER1*6);
COUNTER_RESET = 1;
#(PER1*19.5)
COUNTER_RESET = 0;
#(PER1*1)
$display ("Timing checks are valid");
test_phase = "counting";
#(PER1*COUNT_PHASE);
if ((period1 -ref_period1_clkin1) <= 100 && (period1 -ref_period1_clkin1) >= -100) begin
$display("Freq of CLK_OUT[1] ( in MHz ) : %0f\n", 1000000/period1);
end else
$display("ERROR: Freq of CLK_OUT[1] is not correct");
if ((period2 -ref_period2_clkin1) <= 100 && (period2 -ref_period2_clkin1) >= -100) begin
$display("Freq of CLK_OUT[2] ( in MHz ) : %0f\n", 1000000/period2);
end else
$display("ERROR: Freq of CLK_OUT[2] is not correct");
if ((period3 -ref_period3_clkin1) <= 100 && (period3 -ref_period3_clkin1) >= -100) begin
$display("Freq of CLK_OUT[3] ( in MHz ) : %0f\n", 1000000/period3);
end else
$display("ERROR: Freq of CLK_OUT[3] is not correct");
if ((period4 -ref_period4_clkin1) <= 100 && (period4 -ref_period4_clkin1) >= -100) begin
$display("Freq of CLK_OUT[4] ( in MHz ) : %0f\n", 1000000/period4);
end else
$display("ERROR: Freq of CLK_OUT[4] is not correct");
if ((period5 -ref_period5_clkin1) <= 100 && (period5 -ref_period5_clkin1) >= -100) begin
$display("Freq of CLK_OUT[5] ( in MHz ) : %0f\n", 1000000/period5);
end else
$display("ERROR: Freq of CLK_OUT[5] is not correct");
$display("SIMULATION PASSED");
$display("SYSTEM_CLOCK_COUNTER : %0d\n",$time/PER1);
$finish;
end
always@(posedge CLK_IN1) begin
timeout_counter <= timeout_counter + 1'b1;
if (timeout_counter == 14'b10000000000000) begin
if (LOCKED != 1'b1) begin
$display("ERROR : NO LOCK signal");
$display("SYSTEM_CLOCK_COUNTER : %0d\n",$time/PER1);
$finish;
end
end
end
// Instantiation of the example design containing the clock
// network and sampling counters
//---------------------------------------------------------
dacclk_mmcm_exdes
dut
(// Clock in ports
.CLK_IN1 (CLK_IN1),
// Reset for logic in example design
.COUNTER_RESET (COUNTER_RESET),
.CLK_OUT (CLK_OUT),
// High bits of the counters
.COUNT (COUNT),
// Status and control signals
.LOCKED (LOCKED));
// Freq Check
initial
prev_rise1 = 0;
always @(posedge CLK_OUT[1])
begin
if (prev_rise1 != 0)
period1 = $time - prev_rise1;
prev_rise1 = $time;
end
initial
prev_rise2 = 0;
always @(posedge CLK_OUT[2])
begin
if (prev_rise2 != 0)
period2 = $time - prev_rise2;
prev_rise2 = $time;
end
initial
prev_rise3 = 0;
always @(posedge CLK_OUT[3])
begin
if (prev_rise3 != 0)
period3 = $time - prev_rise3;
prev_rise3 = $time;
end
initial
prev_rise4 = 0;
always @(posedge CLK_OUT[4])
begin
if (prev_rise4 != 0)
period4 = $time - prev_rise4;
prev_rise4 = $time;
end
initial
prev_rise5 = 0;
always @(posedge CLK_OUT[5])
begin
if (prev_rise5 != 0)
period5 = $time - prev_rise5;
prev_rise5 = $time;
end
endmodule
|
module sky130_fd_sc_hdll__o22a (
X ,
A1,
A2,
B1,
B2
);
// Module ports
output X ;
input A1;
input A2;
input B1;
input B2;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire or0_out ;
wire or1_out ;
wire and0_out_X;
// Name Output Other arguments
or or0 (or0_out , A2, A1 );
or or1 (or1_out , B2, B1 );
and and0 (and0_out_X, or0_out, or1_out);
buf buf0 (X , and0_out_X );
endmodule
|
module sky130_fd_sc_hs__o22ai (
VPWR,
VGND,
Y ,
A1 ,
A2 ,
B1 ,
B2
);
// Module ports
input VPWR;
input VGND;
output Y ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
// Local signals
wire B2 nor0_out ;
wire B2 nor1_out ;
wire or0_out_Y ;
wire u_vpwr_vgnd0_out_Y;
// Name Output Other arguments
nor nor0 (nor0_out , B1, B2 );
nor nor1 (nor1_out , A1, A2 );
or or0 (or0_out_Y , nor1_out, nor0_out );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_Y, or0_out_Y, VPWR, VGND);
buf buf0 (Y , u_vpwr_vgnd0_out_Y );
endmodule
|
module bsg_nonsynth_clk_gen_tester
#(parameter `BSG_INV_PARAM(fast_sim_p)
, num_adgs_p="inv"
, ds_width_p="inv"
, tag_els_p="inv"
, tag_node_base_p=0
, osc_final_val_p=0
, ds_final_val_p=0
, clk_mux_final_val_p=2'b00
, version_p = 1
)
(input ext_clk_i
, input bsg_tag_clk_i
, output logic bsg_tag_en_o
, output logic bsg_tag_data_o
, output logic [1:0] bsg_clk_gen_sel_o
, output logic bsg_clk_gen_async_reset_o // async reset (to clock geneartor)
, input bsg_clk_gen_i
// starts on posedge of this signal
, input start_i
, output logic done_o
);
longint sim_iteration;
`declare_bsg_clk_gen_osc_tag_payload_s(num_adgs_p)
`declare_bsg_clk_gen_ds_tag_payload_s(ds_width_p)
localparam max_payload_length_lp = `BSG_MAX($bits(bsg_clk_gen_osc_tag_payload_s),$bits(bsg_clk_gen_ds_tag_payload_s));
localparam lg_max_payload_length_lp = $clog2(max_payload_length_lp+1);
`declare_bsg_tag_header_s(tag_els_p,lg_max_payload_length_lp)
// Used to count ticks between clock edges
//
longint ticks = 0;
longint t1 = 0;
longint per_old = 0;
longint per_new = 0;
longint min_per = 0;
bsg_nonsynth_clk_watcher #(.tolerance_p(1)) wtch (.clk_i(bsg_clk_gen_i));
bsg_tag_header_s ds_tag_header;
bsg_tag_header_s osc_tag_header;
// used for V2 of bsg_clk_gen
bsg_tag_header_s osc_trigger_tag_header;
bsg_clk_gen_osc_tag_payload_s osc_tag_payload;
logic osc_trigger_tag_payload;
bsg_clk_gen_ds_tag_payload_s ds_tag_payload;
localparam osc_pkt_size_lp = $bits(bsg_tag_header_s)+$bits(bsg_clk_gen_osc_tag_payload_s)+1+1;
wire [osc_pkt_size_lp-1:0] osc_pkt = { 1'b0, osc_tag_payload, osc_tag_header,1'b1 };
localparam ds_pkt_size_lp = $bits(bsg_tag_header_s)+$bits(bsg_clk_gen_ds_tag_payload_s)+1+1;
wire [ds_pkt_size_lp-1:0] ds_pkt = { 1'b0, ds_tag_payload, ds_tag_header,1'b1 };
localparam osc_trigger_pkt_size_lp = $bits(bsg_tag_header_s)+1+1+1;
wire [osc_trigger_pkt_size_lp-1:0] osc_trigger_pkt
= { 1'b0, osc_trigger_tag_payload, osc_trigger_tag_header, 1'b1};
localparam check_times_lp = 0;
string output_string = "";
string temp_string = "";
// All testing happens here
//
initial
begin
$display("## INFO 0: detaching bsg_tag chain receive side (%m)");
bsg_tag_en_o = 0;
bsg_tag_data_o = 0;
@(posedge bsg_tag_clk_i);
@(posedge bsg_tag_clk_i);
done_o = 1'b0;
#10
while (start_i==0)
begin
@(posedge bsg_tag_clk_i);
end
$display("*%m");
$display("***********************************************************");
$display("* *");
$display("* bsg_nonsynth_clk_gen_tester BEGIN *");
$display("* *");
$display("***********************************************************");
$display(" ");
/*******************************************************************/
/* */
/* BOOT SEQUENCE */
/* */
/*******************************************************************/
$display("## INFO 1: performing async reset on oscillator (bsg_clk_gen_sel_o=0)");
// perform an async reset. should see life in the clock generator
//
#100ns;
bsg_clk_gen_async_reset_o = 1'b1;
#100ns;
bsg_clk_gen_async_reset_o = 1'b0;
$display("## INFO 2: testing for live oscillator (bsg_clk_gen_sel_o=0)");
// will stall if the generator doesn't boot
//
bsg_clk_gen_sel_o = 2'b00;
for (integer i = 0; i < 10; i++)
@(posedge bsg_clk_gen_i);
$display("## PASS 0: Counted 10 clock positive edges (bsg_clk_gen_sel_o=0)");
$display("## INFO 3b: beginning bsg_tag master reset transmit ");
// reset zero's counter
@(negedge bsg_tag_clk_i);
bsg_tag_data_o = 1'b1;
// transmit lots of zeros
@(negedge bsg_tag_clk_i);
bsg_tag_data_o = 1'b0;
for (integer i = 0; i < `bsg_tag_reset_len(bsg_tag_els_lp,lg_max_payload_length_lp); i=i+1)
@(negedge bsg_tag_clk_i);
$display("## INFO 3e: end bsg_tag master reset transmit");
$display("## INFO 4b: begin bsg_tag_client reset transmit for oscillator");
osc_tag_header.nodeID = tag_node_base_p;
osc_tag_header.data_not_reset = 0;
osc_tag_header.len = $size(osc_tag_payload);
osc_trigger_tag_header.nodeID = tag_node_base_p+2;
osc_trigger_tag_header.data_not_reset = 1;
osc_trigger_tag_header.len = 1;
osc_trigger_tag_payload = 1'b0; // == block transmitted data
// stream of ones will reset bsg_tag_client node
osc_tag_payload = { $bits(osc_tag_payload) {1'b1} };
if (version_p == 1)
begin
for (integer i = 0; i < osc_pkt_size_lp; i=i+1)
begin
@(negedge bsg_tag_clk_i);
bsg_tag_data_o = osc_pkt[i];
end
end
else
// for version 2, we don't need to reset the client node
// but we need to clear the trigger register
begin
for (integer i = 0; i < osc_trigger_pkt_size_lp; i=i+1)
begin
@(negedge bsg_tag_clk_i);
bsg_tag_data_o = osc_trigger_pkt[i];
end
end
// let the data percolate through synchronizers etc
// before attaching bsg_tag
for (integer i = 0; i < 5; i++)
begin
@(posedge bsg_clk_gen_i);
@(posedge bsg_tag_clk_i);
end
$display("## INFO 4e: end bsg_tag_client reset transmit for oscillator ");
$display("## INFO 5: attaching recv side of nodes to bsg_tag (bsg_tag_en_o=1)");
// at this point, we can enable bsg_tag
bsg_tag_en_o = 1;
$display("## INFO 6: testing for live oscillator (bsg_clk_gen_sel_o=%b)",bsg_clk_gen_sel_o);
// will stall if the generator isn't working anymore
//
bsg_clk_gen_sel_o = 2'b00;
for (integer i = 0; i < 10; i++)
@(posedge bsg_clk_gen_i);
$display("## PASS 1: Counted 10 clock positive edges (bsg_clk_gen_sel_o=0)");
$display("## INFO 7b: begin bsg_tag_client reset transmit for downsampler");
ds_tag_header.nodeID = tag_node_base_p+1;
ds_tag_header.data_not_reset = 0;
ds_tag_header.len = $bits(ds_tag_payload);
ds_tag_payload = { $bits(ds_tag_payload) {1'b1} };
for (integer i = 0; i < ds_pkt_size_lp; i=i+1)
begin
@(negedge bsg_tag_clk_i);
bsg_tag_data_o = ds_pkt[i];
end
$display("## INFO 7e: end bsg_tag_client reset transmit for downsampler ");
$display("## INFO 8s: begin resetting downsampler and using val=0 ");
ds_tag_header.data_not_reset = 1;
ds_tag_payload.reset = 1;
ds_tag_payload.val = 0;
for (integer i = 0; i < ds_pkt_size_lp; i=i+1)
begin
@(negedge bsg_tag_clk_i);
bsg_tag_data_o = ds_pkt[i];
end
// we keep the reset asserted for several cycles in each clock
// domain to allow the data to percolate through the synchronizers
for (integer i = 0; i < 3; i++)
begin
@(posedge bsg_clk_gen_i);
@(posedge bsg_tag_clk_i);
end
ds_tag_payload.reset = 0;
for (integer i = 0; i < ds_pkt_size_lp; i=i+1)
begin
@(negedge bsg_tag_clk_i);
bsg_tag_data_o = ds_pkt[i];
end
// let the data percolate through synchronizers etc
// before attaching bsg_tag
for (integer i = 0; i < 4; i++)
begin
@(posedge bsg_clk_gen_i);
@(posedge bsg_tag_clk_i);
end
$display("## INFO 8e: end resetting downsampler and using val=0");
$display("## INFO 9: Testing downsampler generates a clock (bsg_clk_gen_sel_o=01)");
// will stall if the downsampler doesn't get reset properly
//
bsg_clk_gen_sel_o = 2'b01;
for (integer i = 0; i < 10; i++)
@(posedge bsg_clk_gen_i);
$display("## PASS 9: downsampler appears to generate a clock (bsg_clk_gen_sel_o=01)");
$display("## INFO 10: Testing external clock pass-through (bsg_clk_gen_sel_o=10)");
// quick check to make sure the external clock pass-though is working
//
bsg_clk_gen_sel_o = 2'b10;
for (integer i = 0; i < 10; i++)
begin
@(posedge bsg_clk_gen_i);
assert(bsg_clk_gen_i == ext_clk_i);
end
$display("## PASS 10: external clock appears to work (bsg_clk_gen_sel_o=01)");
// end boot sequence, let's start testing!
//
$display("## PASS 11: Clock generator is alive... ramping from slowest to fastest");
/*******************************************************************/
/* */
/* INCREASE CLOCK SPEED */
/* */
/*******************************************************************/
bsg_clk_gen_sel_o = 2'b00; // switch to raw clock generator
per_old = 2**32; // make large for first test to pass
min_per = per_old;
output_string = { output_string, "Setting:" };
for (integer i = 0; i < 1 << $bits(bsg_clk_gen_osc_tag_payload_s); i++)
output_string = { output_string, $sformatf("%6d",i) };
output_string = { output_string, "\nPeriod : " };
// go through each clock speed setting
for (integer i = 0; i < 1 << $bits(bsg_clk_gen_osc_tag_payload_s); i++)
begin
$display("## bsg_taging payload %b",i[0+:$bits(bsg_clk_gen_osc_tag_payload_s)]);
osc_tag_header.data_not_reset = 1;
osc_tag_payload = i;
for (integer j = 0; j < osc_pkt_size_lp; j=j+1)
begin
@(negedge bsg_tag_clk_i);
bsg_tag_data_o = osc_pkt[j];
end
if (version_p == 2)
begin
osc_trigger_tag_payload = 1'b1; // == pass transmitted data
for (integer i = 0; i < osc_trigger_pkt_size_lp; i=i+1)
begin
@(negedge bsg_tag_clk_i);
bsg_tag_data_o = osc_trigger_pkt[i];
end
osc_trigger_tag_payload = 1'b0; // == block transmitted data
for (integer i = 0; i < osc_trigger_pkt_size_lp; i=i+1)
begin
@(negedge bsg_tag_clk_i);
bsg_tag_data_o = osc_trigger_pkt[i];
end
end
// wait a few clock cycles to make sure the packet propagates
// and the syncronizer registers have been passed
//
for (integer j = 0; j < 4; j++)
@(posedge bsg_tag_clk_i);
for (integer j = 0; j < 10; j++)
@(posedge bsg_clk_gen_i);
// Measure the clock period
//
@(posedge bsg_clk_gen_i);
t1 = $time;
@(posedge bsg_clk_gen_i);
per_new = $time -t1;
// Make sure the period is now less than it was.
//
// We actually should expect that the new clock period is strictly
// less than the old one, but the FDT stage of the clock generator
// uses loading capacitance to affect the speed which is not modeled
// in RTL therefore changes in the FDT will show up as identical
// periods.
//
if (check_times_lp)
begin
assert(per_new <= per_old)
$write("%6d",per_new);
// $display("Passed: old per=%-d -- new per=%-d", per_old, per_new);
else
$display("\n***FAILED: old per=%-d -- new per=%-d", per_old, per_new);
end
else
output_string = { output_string, $sformatf ("%2.3f ", real ' (per_new) / 1000.0) };
// Shift for next iteration
//
per_old = per_new;
if (per_new < min_per)
min_per = per_new;
end // for (integer i = 0; i < 1 << $bits(bsg_clk_gen_osc_tag_payload_s); i++)
$display(output_string);
$display("## PASS 12b: BEGIN JAM clock from fastest to slowest");
// now jam from fastest to slowest
osc_tag_payload = 0;
for (integer j = 0; j < osc_pkt_size_lp; j=j+1)
begin
@(negedge bsg_tag_clk_i);
bsg_tag_data_o = osc_pkt[j];
end
if (version_p == 2)
begin
osc_trigger_tag_payload = 1'b1; // == pass transmitted data
for (integer i = 0; i < osc_trigger_pkt_size_lp; i=i+1)
begin
@(negedge bsg_tag_clk_i);
bsg_tag_data_o = osc_trigger_pkt[i];
end
osc_trigger_tag_payload = 1'b0; // == block transmitted data
for (integer i = 0; i < osc_trigger_pkt_size_lp; i=i+1)
begin
@(negedge bsg_tag_clk_i);
bsg_tag_data_o = osc_trigger_pkt[i];
end
end
for (integer j = 0; j < 4; j++)
@(posedge bsg_tag_clk_i);
for (integer j = 0; j < 4; j++)
@(posedge bsg_clk_gen_i);
$display("## PASS 12e: END JAM clock from fastest to slowest");
$display("## PASS 13b: BEGIN JAM clock from slowest to fastest");
// now jam from slowest to fastest
osc_tag_payload = 6'b111111;
for (integer j = 0; j < osc_pkt_size_lp; j=j+1)
begin
@(negedge bsg_tag_clk_i);
bsg_tag_data_o = osc_pkt[j];
end
if (version_p == 2)
begin
osc_trigger_tag_payload = 1'b1; // == pass transmitted data
for (integer i = 0; i < osc_trigger_pkt_size_lp; i=i+1)
begin
@(negedge bsg_tag_clk_i);
bsg_tag_data_o = osc_trigger_pkt[i];
end
osc_trigger_tag_payload = 1'b0; // == block transmitted data
for (integer i = 0; i < osc_trigger_pkt_size_lp; i=i+1)
begin
@(negedge bsg_tag_clk_i);
bsg_tag_data_o = osc_trigger_pkt[i];
end
end
for (integer j = 0; j < 10; j++)
@(posedge bsg_tag_clk_i);
for (integer j = 0; j < 10; j++)
@(posedge bsg_clk_gen_i);
$display("## PASS 13e: END JAM clock from slowest to fastest");
/*******************************************************************/
/* */
/* INCREASE DOWNSAMPLE */
/* */
/*******************************************************************/
$display("## PASS 14: Switching to Downsampled clock (bsg_clk_gen_sel_o=%b)",bsg_clk_gen_sel_o);
bsg_clk_gen_sel_o = 2'b01; // look at the downsampled clock
// simulation iterations
if (fast_sim_p)
sim_iteration = 4;
else
sim_iteration = (1 << ds_width_p);
// go through each downsample amount
for (integer i = 0; i < sim_iteration; i++)
begin
if (i[5:0] == 0)
output_string = { output_string, "\nDwnsmpl: "};
ds_tag_header.data_not_reset = 1;
ds_tag_payload.val = i;
for (integer j = 0; j < ds_pkt_size_lp; j=j+1)
begin
@(negedge bsg_tag_clk_i);
bsg_tag_data_o = ds_pkt[j];
end
// wait a few clock cycles to make sure the packet propagates
// through synchronizers
for (integer j = 0; j < 4; j++)
@(posedge bsg_tag_clk_i);
for (integer j = 0; j < 3; j++)
@(posedge bsg_clk_gen_i);
// Measure the clock period
//
@(posedge bsg_clk_gen_i);
t1 = $time;
@(posedge bsg_clk_gen_i);
per_new = $time - t1 ;
// Make sure the period is now the correct downsampled factor of the
// original clock period
//
if (check_times_lp)
begin
assert(per_new == min_per*(i+1)*2)
$write("%6d",per_new);
//$display("Passed: per=%-d -- expected per=%-d*%-d=%-d", per_new, per_old, (i+1)*2, per_old*(i+1)*2);
else
$display("***FAILED: per=%-d -- expected per=%-d*%-d=%-d", per_new, min_per, (i+1)*2, min_per*(i+1)*2);
end
else
begin
if (per_new >= 999.9*1000.0)
output_string = { output_string, $sformatf ("%5.0f ", real ' (per_new) / 1000.0) };
else
output_string = { output_string, $sformatf ("%5.2f ", real ' (per_new) / 1000.0) };
end
end // for (integer i = 0; i < (1 << ds_width_p) ; i++)
$display(output_string);
$display("* %m ");
$display("***********************************************************");
$display("* *");
$display("* CLOCK GEN TESTER FINISHED *");
$display("* *");
$display("***********************************************************");
$display(" ");
$display("## Setting clk mux final value: %b (%m).",clk_mux_final_val_p);
bsg_clk_gen_sel_o = clk_mux_final_val_p;
osc_tag_header.data_not_reset = 1;
osc_tag_payload = osc_final_val_p;
$display("## Setting final osc value: %b (%m)",osc_final_val_p);
for (integer j = 0; j < osc_pkt_size_lp; j=j+1)
begin
@(negedge bsg_tag_clk_i);
bsg_tag_data_o = osc_pkt[j];
end
if (version_p == 2)
begin
osc_trigger_tag_payload = 1'b1; // == pass transmitted data
for (integer i = 0; i < osc_trigger_pkt_size_lp; i=i+1)
begin
@(negedge bsg_tag_clk_i);
bsg_tag_data_o = osc_trigger_pkt[i];
end
osc_trigger_tag_payload = 1'b0; // == block transmitted data
for (integer i = 0; i < osc_trigger_pkt_size_lp; i=i+1)
begin
@(negedge bsg_tag_clk_i);
bsg_tag_data_o = osc_trigger_pkt[i];
end
end
for (integer j = 0; j < 10; j++)
@(posedge bsg_tag_clk_i);
for (integer j = 0; j < 10; j++)
@(posedge bsg_clk_gen_i);
ds_tag_payload.val = ds_final_val_p;
$display("## Setting final downsampler to %b (%m)",ds_final_val_p);
for (integer j = 0; j < ds_pkt_size_lp; j=j+1)
begin
@(negedge bsg_tag_clk_i);
bsg_tag_data_o = ds_pkt[j];
end
// wait a few clock cycles to make sure the packet propagates
// through synchronizers
for (integer j = 0; j < 8; j++)
@(posedge bsg_tag_clk_i);
for (integer j = 0; j < 8; j++)
@(posedge bsg_clk_gen_i);
// end by disabling jtag tag so it may be used in a wired-or config
bsg_tag_en_o = 1'b0;
bsg_tag_data_o = 1'b0;
done_o=1'b1;
end // initial begin
endmodule
|
module sky130_fd_sc_ls__dlymetal6s2s (
X,
A
);
// Module ports
output X;
input A;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire buf0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X, A );
buf buf1 (X , buf0_out_X );
endmodule
|
module nios_solo_nios2_gen2_0_cpu_test_bench (
// inputs:
D_iw,
D_iw_op,
D_iw_opx,
D_valid,
E_valid,
F_pcb,
F_valid,
R_ctrl_ld,
R_ctrl_ld_non_io,
R_dst_regnum,
R_wr_dst_reg,
W_valid,
W_vinst,
W_wr_data,
av_ld_data_aligned_unfiltered,
clk,
d_address,
d_byteenable,
d_read,
d_write,
i_address,
i_read,
i_readdata,
i_waitrequest,
reset_n,
// outputs:
av_ld_data_aligned_filtered,
test_has_ended
)
;
output [ 31: 0] av_ld_data_aligned_filtered;
output test_has_ended;
input [ 31: 0] D_iw;
input [ 5: 0] D_iw_op;
input [ 5: 0] D_iw_opx;
input D_valid;
input E_valid;
input [ 29: 0] F_pcb;
input F_valid;
input R_ctrl_ld;
input R_ctrl_ld_non_io;
input [ 4: 0] R_dst_regnum;
input R_wr_dst_reg;
input W_valid;
input [ 71: 0] W_vinst;
input [ 31: 0] W_wr_data;
input [ 31: 0] av_ld_data_aligned_unfiltered;
input clk;
input [ 31: 0] d_address;
input [ 3: 0] d_byteenable;
input d_read;
input d_write;
input [ 29: 0] i_address;
input i_read;
input [ 31: 0] i_readdata;
input i_waitrequest;
input reset_n;
wire D_is_opx_inst;
wire D_op_add;
wire D_op_addi;
wire D_op_and;
wire D_op_andhi;
wire D_op_andi;
wire D_op_beq;
wire D_op_bge;
wire D_op_bgeu;
wire D_op_blt;
wire D_op_bltu;
wire D_op_bne;
wire D_op_br;
wire D_op_break;
wire D_op_bret;
wire D_op_call;
wire D_op_callr;
wire D_op_cmpeq;
wire D_op_cmpeqi;
wire D_op_cmpge;
wire D_op_cmpgei;
wire D_op_cmpgeu;
wire D_op_cmpgeui;
wire D_op_cmplt;
wire D_op_cmplti;
wire D_op_cmpltu;
wire D_op_cmpltui;
wire D_op_cmpne;
wire D_op_cmpnei;
wire D_op_crst;
wire D_op_custom;
wire D_op_div;
wire D_op_divu;
wire D_op_eret;
wire D_op_flushd;
wire D_op_flushda;
wire D_op_flushi;
wire D_op_flushp;
wire D_op_hbreak;
wire D_op_initd;
wire D_op_initda;
wire D_op_initi;
wire D_op_intr;
wire D_op_jmp;
wire D_op_jmpi;
wire D_op_ldb;
wire D_op_ldbio;
wire D_op_ldbu;
wire D_op_ldbuio;
wire D_op_ldh;
wire D_op_ldhio;
wire D_op_ldhu;
wire D_op_ldhuio;
wire D_op_ldl;
wire D_op_ldw;
wire D_op_ldwio;
wire D_op_mul;
wire D_op_muli;
wire D_op_mulxss;
wire D_op_mulxsu;
wire D_op_mulxuu;
wire D_op_nextpc;
wire D_op_nor;
wire D_op_op_rsv02;
wire D_op_op_rsv09;
wire D_op_op_rsv10;
wire D_op_op_rsv17;
wire D_op_op_rsv18;
wire D_op_op_rsv25;
wire D_op_op_rsv26;
wire D_op_op_rsv33;
wire D_op_op_rsv34;
wire D_op_op_rsv41;
wire D_op_op_rsv42;
wire D_op_op_rsv49;
wire D_op_op_rsv57;
wire D_op_op_rsv61;
wire D_op_op_rsv62;
wire D_op_op_rsv63;
wire D_op_opx_rsv00;
wire D_op_opx_rsv10;
wire D_op_opx_rsv15;
wire D_op_opx_rsv17;
wire D_op_opx_rsv21;
wire D_op_opx_rsv25;
wire D_op_opx_rsv33;
wire D_op_opx_rsv34;
wire D_op_opx_rsv35;
wire D_op_opx_rsv42;
wire D_op_opx_rsv43;
wire D_op_opx_rsv44;
wire D_op_opx_rsv47;
wire D_op_opx_rsv50;
wire D_op_opx_rsv51;
wire D_op_opx_rsv55;
wire D_op_opx_rsv56;
wire D_op_opx_rsv60;
wire D_op_opx_rsv63;
wire D_op_or;
wire D_op_orhi;
wire D_op_ori;
wire D_op_rdctl;
wire D_op_rdprs;
wire D_op_ret;
wire D_op_rol;
wire D_op_roli;
wire D_op_ror;
wire D_op_sll;
wire D_op_slli;
wire D_op_sra;
wire D_op_srai;
wire D_op_srl;
wire D_op_srli;
wire D_op_stb;
wire D_op_stbio;
wire D_op_stc;
wire D_op_sth;
wire D_op_sthio;
wire D_op_stw;
wire D_op_stwio;
wire D_op_sub;
wire D_op_sync;
wire D_op_trap;
wire D_op_wrctl;
wire D_op_wrprs;
wire D_op_xor;
wire D_op_xorhi;
wire D_op_xori;
wire [ 31: 0] av_ld_data_aligned_filtered;
wire av_ld_data_aligned_unfiltered_0_is_x;
wire av_ld_data_aligned_unfiltered_10_is_x;
wire av_ld_data_aligned_unfiltered_11_is_x;
wire av_ld_data_aligned_unfiltered_12_is_x;
wire av_ld_data_aligned_unfiltered_13_is_x;
wire av_ld_data_aligned_unfiltered_14_is_x;
wire av_ld_data_aligned_unfiltered_15_is_x;
wire av_ld_data_aligned_unfiltered_16_is_x;
wire av_ld_data_aligned_unfiltered_17_is_x;
wire av_ld_data_aligned_unfiltered_18_is_x;
wire av_ld_data_aligned_unfiltered_19_is_x;
wire av_ld_data_aligned_unfiltered_1_is_x;
wire av_ld_data_aligned_unfiltered_20_is_x;
wire av_ld_data_aligned_unfiltered_21_is_x;
wire av_ld_data_aligned_unfiltered_22_is_x;
wire av_ld_data_aligned_unfiltered_23_is_x;
wire av_ld_data_aligned_unfiltered_24_is_x;
wire av_ld_data_aligned_unfiltered_25_is_x;
wire av_ld_data_aligned_unfiltered_26_is_x;
wire av_ld_data_aligned_unfiltered_27_is_x;
wire av_ld_data_aligned_unfiltered_28_is_x;
wire av_ld_data_aligned_unfiltered_29_is_x;
wire av_ld_data_aligned_unfiltered_2_is_x;
wire av_ld_data_aligned_unfiltered_30_is_x;
wire av_ld_data_aligned_unfiltered_31_is_x;
wire av_ld_data_aligned_unfiltered_3_is_x;
wire av_ld_data_aligned_unfiltered_4_is_x;
wire av_ld_data_aligned_unfiltered_5_is_x;
wire av_ld_data_aligned_unfiltered_6_is_x;
wire av_ld_data_aligned_unfiltered_7_is_x;
wire av_ld_data_aligned_unfiltered_8_is_x;
wire av_ld_data_aligned_unfiltered_9_is_x;
wire test_has_ended;
assign D_op_call = D_iw_op == 0;
assign D_op_jmpi = D_iw_op == 1;
assign D_op_op_rsv02 = D_iw_op == 2;
assign D_op_ldbu = D_iw_op == 3;
assign D_op_addi = D_iw_op == 4;
assign D_op_stb = D_iw_op == 5;
assign D_op_br = D_iw_op == 6;
assign D_op_ldb = D_iw_op == 7;
assign D_op_cmpgei = D_iw_op == 8;
assign D_op_op_rsv09 = D_iw_op == 9;
assign D_op_op_rsv10 = D_iw_op == 10;
assign D_op_ldhu = D_iw_op == 11;
assign D_op_andi = D_iw_op == 12;
assign D_op_sth = D_iw_op == 13;
assign D_op_bge = D_iw_op == 14;
assign D_op_ldh = D_iw_op == 15;
assign D_op_cmplti = D_iw_op == 16;
assign D_op_op_rsv17 = D_iw_op == 17;
assign D_op_op_rsv18 = D_iw_op == 18;
assign D_op_initda = D_iw_op == 19;
assign D_op_ori = D_iw_op == 20;
assign D_op_stw = D_iw_op == 21;
assign D_op_blt = D_iw_op == 22;
assign D_op_ldw = D_iw_op == 23;
assign D_op_cmpnei = D_iw_op == 24;
assign D_op_op_rsv25 = D_iw_op == 25;
assign D_op_op_rsv26 = D_iw_op == 26;
assign D_op_flushda = D_iw_op == 27;
assign D_op_xori = D_iw_op == 28;
assign D_op_stc = D_iw_op == 29;
assign D_op_bne = D_iw_op == 30;
assign D_op_ldl = D_iw_op == 31;
assign D_op_cmpeqi = D_iw_op == 32;
assign D_op_op_rsv33 = D_iw_op == 33;
assign D_op_op_rsv34 = D_iw_op == 34;
assign D_op_ldbuio = D_iw_op == 35;
assign D_op_muli = D_iw_op == 36;
assign D_op_stbio = D_iw_op == 37;
assign D_op_beq = D_iw_op == 38;
assign D_op_ldbio = D_iw_op == 39;
assign D_op_cmpgeui = D_iw_op == 40;
assign D_op_op_rsv41 = D_iw_op == 41;
assign D_op_op_rsv42 = D_iw_op == 42;
assign D_op_ldhuio = D_iw_op == 43;
assign D_op_andhi = D_iw_op == 44;
assign D_op_sthio = D_iw_op == 45;
assign D_op_bgeu = D_iw_op == 46;
assign D_op_ldhio = D_iw_op == 47;
assign D_op_cmpltui = D_iw_op == 48;
assign D_op_op_rsv49 = D_iw_op == 49;
assign D_op_custom = D_iw_op == 50;
assign D_op_initd = D_iw_op == 51;
assign D_op_orhi = D_iw_op == 52;
assign D_op_stwio = D_iw_op == 53;
assign D_op_bltu = D_iw_op == 54;
assign D_op_ldwio = D_iw_op == 55;
assign D_op_rdprs = D_iw_op == 56;
assign D_op_op_rsv57 = D_iw_op == 57;
assign D_op_flushd = D_iw_op == 59;
assign D_op_xorhi = D_iw_op == 60;
assign D_op_op_rsv61 = D_iw_op == 61;
assign D_op_op_rsv62 = D_iw_op == 62;
assign D_op_op_rsv63 = D_iw_op == 63;
assign D_op_opx_rsv00 = (D_iw_opx == 0) & D_is_opx_inst;
assign D_op_eret = (D_iw_opx == 1) & D_is_opx_inst;
assign D_op_roli = (D_iw_opx == 2) & D_is_opx_inst;
assign D_op_rol = (D_iw_opx == 3) & D_is_opx_inst;
assign D_op_flushp = (D_iw_opx == 4) & D_is_opx_inst;
assign D_op_ret = (D_iw_opx == 5) & D_is_opx_inst;
assign D_op_nor = (D_iw_opx == 6) & D_is_opx_inst;
assign D_op_mulxuu = (D_iw_opx == 7) & D_is_opx_inst;
assign D_op_cmpge = (D_iw_opx == 8) & D_is_opx_inst;
assign D_op_bret = (D_iw_opx == 9) & D_is_opx_inst;
assign D_op_opx_rsv10 = (D_iw_opx == 10) & D_is_opx_inst;
assign D_op_ror = (D_iw_opx == 11) & D_is_opx_inst;
assign D_op_flushi = (D_iw_opx == 12) & D_is_opx_inst;
assign D_op_jmp = (D_iw_opx == 13) & D_is_opx_inst;
assign D_op_and = (D_iw_opx == 14) & D_is_opx_inst;
assign D_op_opx_rsv15 = (D_iw_opx == 15) & D_is_opx_inst;
assign D_op_cmplt = (D_iw_opx == 16) & D_is_opx_inst;
assign D_op_opx_rsv17 = (D_iw_opx == 17) & D_is_opx_inst;
assign D_op_slli = (D_iw_opx == 18) & D_is_opx_inst;
assign D_op_sll = (D_iw_opx == 19) & D_is_opx_inst;
assign D_op_wrprs = (D_iw_opx == 20) & D_is_opx_inst;
assign D_op_opx_rsv21 = (D_iw_opx == 21) & D_is_opx_inst;
assign D_op_or = (D_iw_opx == 22) & D_is_opx_inst;
assign D_op_mulxsu = (D_iw_opx == 23) & D_is_opx_inst;
assign D_op_cmpne = (D_iw_opx == 24) & D_is_opx_inst;
assign D_op_opx_rsv25 = (D_iw_opx == 25) & D_is_opx_inst;
assign D_op_srli = (D_iw_opx == 26) & D_is_opx_inst;
assign D_op_srl = (D_iw_opx == 27) & D_is_opx_inst;
assign D_op_nextpc = (D_iw_opx == 28) & D_is_opx_inst;
assign D_op_callr = (D_iw_opx == 29) & D_is_opx_inst;
assign D_op_xor = (D_iw_opx == 30) & D_is_opx_inst;
assign D_op_mulxss = (D_iw_opx == 31) & D_is_opx_inst;
assign D_op_cmpeq = (D_iw_opx == 32) & D_is_opx_inst;
assign D_op_opx_rsv33 = (D_iw_opx == 33) & D_is_opx_inst;
assign D_op_opx_rsv34 = (D_iw_opx == 34) & D_is_opx_inst;
assign D_op_opx_rsv35 = (D_iw_opx == 35) & D_is_opx_inst;
assign D_op_divu = (D_iw_opx == 36) & D_is_opx_inst;
assign D_op_div = (D_iw_opx == 37) & D_is_opx_inst;
assign D_op_rdctl = (D_iw_opx == 38) & D_is_opx_inst;
assign D_op_mul = (D_iw_opx == 39) & D_is_opx_inst;
assign D_op_cmpgeu = (D_iw_opx == 40) & D_is_opx_inst;
assign D_op_initi = (D_iw_opx == 41) & D_is_opx_inst;
assign D_op_opx_rsv42 = (D_iw_opx == 42) & D_is_opx_inst;
assign D_op_opx_rsv43 = (D_iw_opx == 43) & D_is_opx_inst;
assign D_op_opx_rsv44 = (D_iw_opx == 44) & D_is_opx_inst;
assign D_op_trap = (D_iw_opx == 45) & D_is_opx_inst;
assign D_op_wrctl = (D_iw_opx == 46) & D_is_opx_inst;
assign D_op_opx_rsv47 = (D_iw_opx == 47) & D_is_opx_inst;
assign D_op_cmpltu = (D_iw_opx == 48) & D_is_opx_inst;
assign D_op_add = (D_iw_opx == 49) & D_is_opx_inst;
assign D_op_opx_rsv50 = (D_iw_opx == 50) & D_is_opx_inst;
assign D_op_opx_rsv51 = (D_iw_opx == 51) & D_is_opx_inst;
assign D_op_break = (D_iw_opx == 52) & D_is_opx_inst;
assign D_op_hbreak = (D_iw_opx == 53) & D_is_opx_inst;
assign D_op_sync = (D_iw_opx == 54) & D_is_opx_inst;
assign D_op_opx_rsv55 = (D_iw_opx == 55) & D_is_opx_inst;
assign D_op_opx_rsv56 = (D_iw_opx == 56) & D_is_opx_inst;
assign D_op_sub = (D_iw_opx == 57) & D_is_opx_inst;
assign D_op_srai = (D_iw_opx == 58) & D_is_opx_inst;
assign D_op_sra = (D_iw_opx == 59) & D_is_opx_inst;
assign D_op_opx_rsv60 = (D_iw_opx == 60) & D_is_opx_inst;
assign D_op_intr = (D_iw_opx == 61) & D_is_opx_inst;
assign D_op_crst = (D_iw_opx == 62) & D_is_opx_inst;
assign D_op_opx_rsv63 = (D_iw_opx == 63) & D_is_opx_inst;
assign D_is_opx_inst = D_iw_op == 58;
assign test_has_ended = 1'b0;
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
//Clearing 'X' data bits
assign av_ld_data_aligned_unfiltered_0_is_x = ^(av_ld_data_aligned_unfiltered[0]) === 1'bx;
assign av_ld_data_aligned_filtered[0] = (av_ld_data_aligned_unfiltered_0_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[0];
assign av_ld_data_aligned_unfiltered_1_is_x = ^(av_ld_data_aligned_unfiltered[1]) === 1'bx;
assign av_ld_data_aligned_filtered[1] = (av_ld_data_aligned_unfiltered_1_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[1];
assign av_ld_data_aligned_unfiltered_2_is_x = ^(av_ld_data_aligned_unfiltered[2]) === 1'bx;
assign av_ld_data_aligned_filtered[2] = (av_ld_data_aligned_unfiltered_2_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[2];
assign av_ld_data_aligned_unfiltered_3_is_x = ^(av_ld_data_aligned_unfiltered[3]) === 1'bx;
assign av_ld_data_aligned_filtered[3] = (av_ld_data_aligned_unfiltered_3_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[3];
assign av_ld_data_aligned_unfiltered_4_is_x = ^(av_ld_data_aligned_unfiltered[4]) === 1'bx;
assign av_ld_data_aligned_filtered[4] = (av_ld_data_aligned_unfiltered_4_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[4];
assign av_ld_data_aligned_unfiltered_5_is_x = ^(av_ld_data_aligned_unfiltered[5]) === 1'bx;
assign av_ld_data_aligned_filtered[5] = (av_ld_data_aligned_unfiltered_5_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[5];
assign av_ld_data_aligned_unfiltered_6_is_x = ^(av_ld_data_aligned_unfiltered[6]) === 1'bx;
assign av_ld_data_aligned_filtered[6] = (av_ld_data_aligned_unfiltered_6_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[6];
assign av_ld_data_aligned_unfiltered_7_is_x = ^(av_ld_data_aligned_unfiltered[7]) === 1'bx;
assign av_ld_data_aligned_filtered[7] = (av_ld_data_aligned_unfiltered_7_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[7];
assign av_ld_data_aligned_unfiltered_8_is_x = ^(av_ld_data_aligned_unfiltered[8]) === 1'bx;
assign av_ld_data_aligned_filtered[8] = (av_ld_data_aligned_unfiltered_8_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[8];
assign av_ld_data_aligned_unfiltered_9_is_x = ^(av_ld_data_aligned_unfiltered[9]) === 1'bx;
assign av_ld_data_aligned_filtered[9] = (av_ld_data_aligned_unfiltered_9_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[9];
assign av_ld_data_aligned_unfiltered_10_is_x = ^(av_ld_data_aligned_unfiltered[10]) === 1'bx;
assign av_ld_data_aligned_filtered[10] = (av_ld_data_aligned_unfiltered_10_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[10];
assign av_ld_data_aligned_unfiltered_11_is_x = ^(av_ld_data_aligned_unfiltered[11]) === 1'bx;
assign av_ld_data_aligned_filtered[11] = (av_ld_data_aligned_unfiltered_11_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[11];
assign av_ld_data_aligned_unfiltered_12_is_x = ^(av_ld_data_aligned_unfiltered[12]) === 1'bx;
assign av_ld_data_aligned_filtered[12] = (av_ld_data_aligned_unfiltered_12_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[12];
assign av_ld_data_aligned_unfiltered_13_is_x = ^(av_ld_data_aligned_unfiltered[13]) === 1'bx;
assign av_ld_data_aligned_filtered[13] = (av_ld_data_aligned_unfiltered_13_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[13];
assign av_ld_data_aligned_unfiltered_14_is_x = ^(av_ld_data_aligned_unfiltered[14]) === 1'bx;
assign av_ld_data_aligned_filtered[14] = (av_ld_data_aligned_unfiltered_14_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[14];
assign av_ld_data_aligned_unfiltered_15_is_x = ^(av_ld_data_aligned_unfiltered[15]) === 1'bx;
assign av_ld_data_aligned_filtered[15] = (av_ld_data_aligned_unfiltered_15_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[15];
assign av_ld_data_aligned_unfiltered_16_is_x = ^(av_ld_data_aligned_unfiltered[16]) === 1'bx;
assign av_ld_data_aligned_filtered[16] = (av_ld_data_aligned_unfiltered_16_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[16];
assign av_ld_data_aligned_unfiltered_17_is_x = ^(av_ld_data_aligned_unfiltered[17]) === 1'bx;
assign av_ld_data_aligned_filtered[17] = (av_ld_data_aligned_unfiltered_17_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[17];
assign av_ld_data_aligned_unfiltered_18_is_x = ^(av_ld_data_aligned_unfiltered[18]) === 1'bx;
assign av_ld_data_aligned_filtered[18] = (av_ld_data_aligned_unfiltered_18_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[18];
assign av_ld_data_aligned_unfiltered_19_is_x = ^(av_ld_data_aligned_unfiltered[19]) === 1'bx;
assign av_ld_data_aligned_filtered[19] = (av_ld_data_aligned_unfiltered_19_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[19];
assign av_ld_data_aligned_unfiltered_20_is_x = ^(av_ld_data_aligned_unfiltered[20]) === 1'bx;
assign av_ld_data_aligned_filtered[20] = (av_ld_data_aligned_unfiltered_20_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[20];
assign av_ld_data_aligned_unfiltered_21_is_x = ^(av_ld_data_aligned_unfiltered[21]) === 1'bx;
assign av_ld_data_aligned_filtered[21] = (av_ld_data_aligned_unfiltered_21_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[21];
assign av_ld_data_aligned_unfiltered_22_is_x = ^(av_ld_data_aligned_unfiltered[22]) === 1'bx;
assign av_ld_data_aligned_filtered[22] = (av_ld_data_aligned_unfiltered_22_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[22];
assign av_ld_data_aligned_unfiltered_23_is_x = ^(av_ld_data_aligned_unfiltered[23]) === 1'bx;
assign av_ld_data_aligned_filtered[23] = (av_ld_data_aligned_unfiltered_23_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[23];
assign av_ld_data_aligned_unfiltered_24_is_x = ^(av_ld_data_aligned_unfiltered[24]) === 1'bx;
assign av_ld_data_aligned_filtered[24] = (av_ld_data_aligned_unfiltered_24_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[24];
assign av_ld_data_aligned_unfiltered_25_is_x = ^(av_ld_data_aligned_unfiltered[25]) === 1'bx;
assign av_ld_data_aligned_filtered[25] = (av_ld_data_aligned_unfiltered_25_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[25];
assign av_ld_data_aligned_unfiltered_26_is_x = ^(av_ld_data_aligned_unfiltered[26]) === 1'bx;
assign av_ld_data_aligned_filtered[26] = (av_ld_data_aligned_unfiltered_26_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[26];
assign av_ld_data_aligned_unfiltered_27_is_x = ^(av_ld_data_aligned_unfiltered[27]) === 1'bx;
assign av_ld_data_aligned_filtered[27] = (av_ld_data_aligned_unfiltered_27_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[27];
assign av_ld_data_aligned_unfiltered_28_is_x = ^(av_ld_data_aligned_unfiltered[28]) === 1'bx;
assign av_ld_data_aligned_filtered[28] = (av_ld_data_aligned_unfiltered_28_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[28];
assign av_ld_data_aligned_unfiltered_29_is_x = ^(av_ld_data_aligned_unfiltered[29]) === 1'bx;
assign av_ld_data_aligned_filtered[29] = (av_ld_data_aligned_unfiltered_29_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[29];
assign av_ld_data_aligned_unfiltered_30_is_x = ^(av_ld_data_aligned_unfiltered[30]) === 1'bx;
assign av_ld_data_aligned_filtered[30] = (av_ld_data_aligned_unfiltered_30_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[30];
assign av_ld_data_aligned_unfiltered_31_is_x = ^(av_ld_data_aligned_unfiltered[31]) === 1'bx;
assign av_ld_data_aligned_filtered[31] = (av_ld_data_aligned_unfiltered_31_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[31];
always @(posedge clk)
begin
if (reset_n)
if (^(F_valid) === 1'bx)
begin
$write("%0d ns: ERROR: nios_solo_nios2_gen2_0_cpu_test_bench/F_valid is 'x'\n", $time);
$stop;
end
end
always @(posedge clk)
begin
if (reset_n)
if (^(D_valid) === 1'bx)
begin
$write("%0d ns: ERROR: nios_solo_nios2_gen2_0_cpu_test_bench/D_valid is 'x'\n", $time);
$stop;
end
end
always @(posedge clk)
begin
if (reset_n)
if (^(E_valid) === 1'bx)
begin
$write("%0d ns: ERROR: nios_solo_nios2_gen2_0_cpu_test_bench/E_valid is 'x'\n", $time);
$stop;
end
end
always @(posedge clk)
begin
if (reset_n)
if (^(W_valid) === 1'bx)
begin
$write("%0d ns: ERROR: nios_solo_nios2_gen2_0_cpu_test_bench/W_valid is 'x'\n", $time);
$stop;
end
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
end
else if (W_valid)
if (^(R_wr_dst_reg) === 1'bx)
begin
$write("%0d ns: ERROR: nios_solo_nios2_gen2_0_cpu_test_bench/R_wr_dst_reg is 'x'\n", $time);
$stop;
end
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
end
else if (W_valid & R_wr_dst_reg)
if (^(W_wr_data) === 1'bx)
begin
$write("%0d ns: ERROR: nios_solo_nios2_gen2_0_cpu_test_bench/W_wr_data is 'x'\n", $time);
$stop;
end
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
end
else if (W_valid & R_wr_dst_reg)
if (^(R_dst_regnum) === 1'bx)
begin
$write("%0d ns: ERROR: nios_solo_nios2_gen2_0_cpu_test_bench/R_dst_regnum is 'x'\n", $time);
$stop;
end
end
always @(posedge clk)
begin
if (reset_n)
if (^(d_write) === 1'bx)
begin
$write("%0d ns: ERROR: nios_solo_nios2_gen2_0_cpu_test_bench/d_write is 'x'\n", $time);
$stop;
end
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
end
else if (d_write)
if (^(d_byteenable) === 1'bx)
begin
$write("%0d ns: ERROR: nios_solo_nios2_gen2_0_cpu_test_bench/d_byteenable is 'x'\n", $time);
$stop;
end
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
end
else if (d_write | d_read)
if (^(d_address) === 1'bx)
begin
$write("%0d ns: ERROR: nios_solo_nios2_gen2_0_cpu_test_bench/d_address is 'x'\n", $time);
$stop;
end
end
always @(posedge clk)
begin
if (reset_n)
if (^(d_read) === 1'bx)
begin
$write("%0d ns: ERROR: nios_solo_nios2_gen2_0_cpu_test_bench/d_read is 'x'\n", $time);
$stop;
end
end
always @(posedge clk)
begin
if (reset_n)
if (^(i_read) === 1'bx)
begin
$write("%0d ns: ERROR: nios_solo_nios2_gen2_0_cpu_test_bench/i_read is 'x'\n", $time);
$stop;
end
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
end
else if (i_read)
if (^(i_address) === 1'bx)
begin
$write("%0d ns: ERROR: nios_solo_nios2_gen2_0_cpu_test_bench/i_address is 'x'\n", $time);
$stop;
end
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
end
else if (i_read & ~i_waitrequest)
if (^(i_readdata) === 1'bx)
begin
$write("%0d ns: ERROR: nios_solo_nios2_gen2_0_cpu_test_bench/i_readdata is 'x'\n", $time);
$stop;
end
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
end
else if (W_valid & R_ctrl_ld)
if (^(av_ld_data_aligned_unfiltered) === 1'bx)
begin
$write("%0d ns: WARNING: nios_solo_nios2_gen2_0_cpu_test_bench/av_ld_data_aligned_unfiltered is 'x'\n", $time);
end
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
end
else if (W_valid & R_wr_dst_reg)
if (^(W_wr_data) === 1'bx)
begin
$write("%0d ns: WARNING: nios_solo_nios2_gen2_0_cpu_test_bench/W_wr_data is 'x'\n", $time);
end
end
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
//synthesis read_comments_as_HDL on
//
// assign av_ld_data_aligned_filtered = av_ld_data_aligned_unfiltered;
//
//synthesis read_comments_as_HDL off
endmodule
|
module sky130_fd_sc_hs__sdfbbn (
//# {{data|Data Signals}}
input D ,
output Q ,
output Q_N ,
//# {{control|Control Signals}}
input RESET_B,
input SET_B ,
//# {{scanchain|Scan Chain}}
input SCD ,
input SCE ,
//# {{clocks|Clocking}}
input CLK_N ,
//# {{power|Power}}
input VPWR ,
input VGND
);
endmodule
|
module sky130_fd_sc_hdll__and4 (
X ,
A ,
B ,
C ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input B ;
input C ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire and0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
and and0 (and0_out_X , A, B, C, D );
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, and0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
|
module top();
// Inputs are registered
reg A;
reg B;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Y;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
B = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 B = 1'b0;
#60 VGND = 1'b0;
#80 VNB = 1'b0;
#100 VPB = 1'b0;
#120 VPWR = 1'b0;
#140 A = 1'b1;
#160 B = 1'b1;
#180 VGND = 1'b1;
#200 VNB = 1'b1;
#220 VPB = 1'b1;
#240 VPWR = 1'b1;
#260 A = 1'b0;
#280 B = 1'b0;
#300 VGND = 1'b0;
#320 VNB = 1'b0;
#340 VPB = 1'b0;
#360 VPWR = 1'b0;
#380 VPWR = 1'b1;
#400 VPB = 1'b1;
#420 VNB = 1'b1;
#440 VGND = 1'b1;
#460 B = 1'b1;
#480 A = 1'b1;
#500 VPWR = 1'bx;
#520 VPB = 1'bx;
#540 VNB = 1'bx;
#560 VGND = 1'bx;
#580 B = 1'bx;
#600 A = 1'bx;
end
sky130_fd_sc_ls__xnor2 dut (.A(A), .B(B), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Y(Y));
endmodule
|
module sky130_fd_sc_lp__sdfrtp_ov2 (
Q ,
CLK ,
D ,
SCD ,
SCE ,
RESET_B
);
// Module ports
output Q ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input RESET_B;
// Local signals
wire buf_Q ;
wire RESET ;
wire mux_out;
// Delay Name Output Other arguments
not not0 (RESET , RESET_B );
sky130_fd_sc_lp__udp_mux_2to1 mux_2to10 (mux_out, D, SCD, SCE );
sky130_fd_sc_lp__udp_dff$PR `UNIT_DELAY dff0 (buf_Q , mux_out, CLK, RESET);
buf buf0 (Q , buf_Q );
endmodule
|
module clk_gen(clk100MHz, rst, clk_4sec, clk_5KHz);
// input clk100MHz, rst;
// output clk_4sec, clk_5KHz;
// reg clk_4sec, clk_5KHz;
// integer count, count1;
// always@(posedge clk100MHz)
// begin
// if(rst) begin
// count = 0;
// count1 = 0;
// clk_4sec = 0;
// clk_5KHz =0;
// end
// else begin
// if(count == 200000000) begin
// clk_4sec = ~clk_4sec;
// count = 0;
// end
// if(count1 == 10000) begin
// clk_5KHz = ~clk_5KHz;
// count1 = 0;
// end
// count = count + 1;
// count1 = count1 + 1;
// end
// end
// endmodule
|
module clk_gen(
input wire clk100MHz,
input wire rst,
output reg clk1MHz,
output reg clk5KHz,
output reg clk200Hz
);
integer count;
integer ledmux;
integer highspeed;
always@(posedge clk100MHz or posedge rst)
begin
if(rst) begin
count = 0;
highspeed = 0;
ledmux = 0;
clk1MHz = 0;
clk5KHz = 0;
clk200Hz = 0;
end
else begin
if(count == 250000) begin //125000 @ 100MHz
clk200Hz = ~clk200Hz;
count = 0;
end
if(ledmux == 5000) begin //10000 @ 1KHz
clk5KHz = ~clk5KHz;
ledmux = 0;
end
if(highspeed == 50) begin //125000 @ 100MHz
clk1MHz = ~clk1MHz;
highspeed = 0;
end
count = count + 1;
highspeed = highspeed + 1;
ledmux = ledmux + 1;
end
end
endmodule
|
module sky130_fd_sc_ls__dlxtp (
Q ,
D ,
GATE
);
// Module ports
output Q ;
input D ;
input GATE;
// Local signals
wire buf_Q;
// Name Output Other arguments
sky130_fd_sc_ls__udp_dlatch$P dlatch0 (buf_Q , D, GATE );
buf buf0 (Q , buf_Q );
endmodule
|
module PATTERN(
clk,
rst_n,
in_valid,
in_a,
in_b,
in_mode,
out_valid,
out
);
//---------------------------------
// input and output declaration
//---------------------------------
output clk;
output rst_n;
output in_valid;
output [15:0] in_a;
output [15:0] in_b;
output in_mode;
input out_valid;
input [35:0] out;
//----------------------------------
// reg and wire declaration
//---------------------------------
reg clk;
reg rst_n;
reg in_valid;
reg [15:0] in_a;
reg [15:0] in_b;
reg in_mode;
reg [7:0] a_real, a_img;
reg [7:0] b_real, b_img;
reg [17:0] out_real, out_img;
//reg [35:0] Y_out, C_out;
integer file_in_ar, file_in_ai, file_in_br, file_in_bi;
integer file_outr,file_outi,file_mod, scan_filein, scan_fileout;
integer i, pn, in_num, out_num, pass_num;
integer latency, total_latency, correct;
integer mode;
initial begin
clk = 1'b0;
forever #(`clk_PERIOD/2.0) clk = ~clk;
end
initial begin
file_in_ar = $fopen("IN_A_REAL.txt","r");
file_in_ai = $fopen("IN_A_IMG.txt","r");
file_in_br = $fopen("IN_B_REAL.txt","r");
file_in_bi = $fopen("IN_B_IMG.txt","r");
file_outr = $fopen("OUT_REAL.txt","r");
file_outi = $fopen("OUT_IMG.txt","r");
file_mod = $fopen("MODE.txt","r");
latency=0;
rst_n <= 1'b1;
in_valid <= 1'b0;
in_a <= 8'dx;
in_b <= 8'dx;
@(posedge clk);
rst_n <= 1'b0;
@(posedge clk);
rst_n <= 1'b1;
@(negedge clk);
check_reset;
for(i = 0; i < `PATTERN_NUM; i = i + 1)
begin
@(posedge clk);
@(posedge clk);
out_num = 0;
latency=0;
for(pn = 0; pn < 3; pn = pn + 1)
begin
in_valid <= 1'b1;
scan_filein=$fscanf(file_in_ar, "%d\n", a_real);
scan_filein=$fscanf(file_in_ai, "%d\n", a_img);
scan_filein=$fscanf(file_in_br, "%d\n", b_real);
scan_filein=$fscanf(file_in_bi, "%d\n", b_img);
in_a <= {a_real,a_img};
in_b <= {b_real,b_img};
if(pn==0) begin
scan_filein=$fscanf(file_mod, "%d\n", in_mode);
mode <= in_mode;
end
else
in_mode <= 'dx;
@(negedge clk);
check_reset;
@(posedge clk);
end
in_valid <= 1'b0;
in_a <= 8'dx;
in_b <= 8'dx;
in_mode <= 1'bx;
@(negedge clk);
while(!(out_valid === 1'b1))
begin
if(latency >= 100)
begin
$display("");
$display("=================================================");
$display(" Latency more than 100 !!!! ");
$display("=================================================");
$display("");
$finish;
end
latency = latency + 1;
@(negedge clk);
end
out_num = 0;
while(out_valid === 1'b1)
begin
if(out_num>1&&mode==1)
begin
$display("");
$display("=================================================");
$display(" out_valid more than 1 cycle !!!! ");
$display("=================================================");
$display("");
@(negedge clk);
$finish;
end
if(out_num > 5)
begin
$display("");
$display("=================================================");
$display(" out_valid more than 5 cycle !!!! ");
$display("=================================================");
$display("");
@(negedge clk);
$finish;
end
scan_fileout=$fscanf(file_outr, "%d\n", out_real);
scan_fileout=$fscanf(file_outi, "%d\n", out_img);
//C_OUT <= {out_real,out_img};
if(out_real !== out[35:18] || out_img !== out[17:0])
begin
$display("");
$display("=================================================");
$display(" Failed!! PATTERN %3d is wrong! ", i+1);
$display("=================================================");
$display("");
@(negedge clk);
$finish;
end
out_num = out_num + 1;
@(negedge clk);
end
if(out_num != 5 && mode == 0) begin
$display("");
$display("=================================================");
$display(" out_valid less than 5 cycle !!!! ");
$display("=================================================");
$display("");
@(negedge clk);
$finish;
end
$display("");
$display(" Pass pattern %3d ", i+1);
end
$display("\033[0;33m======================================================================\033[m");
$display("\033[1;35m ij1PXqSur, \033[m");
$display("\033[1;35m ,i:, :7: \033[0;32m CONGRATULATION!! \033[m");
$display("\033[1;35m i7i 5. i2r \033[0;32m You pass all pattern!! \033[m");
$display("\033[1;35m L. :. : r7 \033[m");
$display("\033[1;35m .q v7 i \033[0;32m \033[m");
$display("\033[1;35m M M .: .i. \033[m");
$display("\033[1;35m iX j@; : : : . \033[m");
$display("\033[1;35m Y7 ,@@ J .. ::i \033[m");
$display("\033[1;35m r7 @Bu JB7 :iii. \033[m");
$display("\033[1;35m @ .@@ .B r: \033[m");
$display("\033[1;35m uE , T 8 u \033[m");
$display("\033[1;35m Pu U :B Fi :v \033[m");
$display("\033[1;35m rEi iU S: N \033[m");
$display("\033[1;35m USv, :7 F. \033[m");
$display("\033[1;35m .,:irLr, . J: \033[m");
$display("\033[1;35m .::irvrrL7 .S. \033[m");
$display("\033[1;35m ,ui i: :r \033[m");
$display("\033[1;35m r5 : 7: \033[m");
$display("\033[1;35m iu :.B,. 2 \033[0;35m LNSQu. ML vB; :MF. HB. @M \033[m");
$display("\033[1;35m :r .: j r. \033[0;35m M@iiX@; @:B :@q@@ OOMBQ K@ Bk \033[m");
$display("\033[1;35m ,u:i:.i::.i. vi \033[0;35m BB 0B @::@ P@: Y .@0 V 5B @I \033[m");
$display("\033[1;35m .:i ,r, 1r \033[0;35m MBM5; qB Ju N5. '@Ei B@ .BH \033[m");
$display("\033[1;35m ,rv ;1, \033[0;35m BX .@qi8BM: u :@u :u :F@ \033[m");
$display("\033[1;35m .::.,.J .rv: \033[0;35m 7N JL iL. Jv;, LYru: rU 5M \033[m");
$display("\033[1;35m .r.;:.i.. .::. \033[m");
$display("\033[0;33m======================================================================\033[m");
$finish;
end
task check_reset;
if(out_valid !== 1'b0 || out !== 36'd0) begin
$display("");
$display("=================================================");
$display(" output should be reset !!!! ");
$display("=================================================");
$display("");
@(negedge clk);
$finish;
end
endtask
endmodule
|
module j4(
input wire clk,
input wire resetq,
output wire io_rd,
output wire io_wr,
output wire [15:0] mem_addr,
output wire mem_wr,
output wire [`WIDTH-1:0] dout,
input wire [`WIDTH-1:0] io_din, //note: this is always a cycle late, as io_addr_ is registered because EASE_IO_TIMING is always defined in j4a.v
output wire [12:0] code_addr,
input wire [15:0] insn,
output wire [1:0] io_slot,
output wire [15:0] return_top,
input wire [3:0] kill_slot_rq);
reg [1:0] slot, slotN; // slot select
greycount tc(.last(slot), .next(slotN));
reg [4:0] dsp, dspN;// data stack pointers, -N is not registered,
reg [14:0] dspD; // -D is the delay shift register.
reg [`WIDTH-1:0] st0, st0N;// top of data stacks
reg [3*`WIDTH-1:0] st0D; // top delay
reg [12:0] pc /* verilator public_flat */, pcN; // program counters
reg [38:0] pcD; // pc Delay
wire [12:0] pc_plus_1 = pc + 13'd1;
reg reboot = 1;
reg [3:0] kill_slot = 4'h0;
assign mem_addr = st0[15:0];
assign code_addr = pcD[25:13];// was pcN;. The read for next context needs to be pre-fetched from the ram.
// because this *was* pcN, we will instead use what will be pc one clock cycle in the future, which is pcD[12:0]. But wait:
// We make this two clock cycles into the future, and then register again insn so
// that the instruction is already available, not needing to be read from ram... This is why it's pcD[25:13], then:
reg [15:0] insn_now = 0;
// adds a clock delay, but this is fine.
always @(posedge clk) insn_now <= insn;
// note every reference below here which was to insn will now be to inst_now instead.
// this automatically includes all memory reads, instructions or otherwise.
// io_din is registered once in j4a.v, so it still needs 3 delays to be good.
reg [3*`WIDTH-1:0] io_din_delay = 0;
always @(posedge clk) io_din_delay <= {io_din, io_din_delay[3*`WIDTH-1:`WIDTH]};
wire [`WIDTH-1:0] io_din_now = io_din_delay[`WIDTH-1:0];
// The D and R stacks
wire [`WIDTH-1:0] st1, rst0;
// stack delta controls
wire [1:0] dspI, rspI;
reg dstkW,rstkW; // data stack write / return stack write
wire [`WIDTH-1:0] rstkD; // return stack write value
stack2pipe4 #(.DEPTH(16)) dstack_(.clk(clk), .rd(st1), .we(dstkW), .wd(st0), .delta(dspI));
stack2pipe4 #(.DEPTH(19)) rstack_(.clk(clk), .rd(rst0), .we(rstkW), .wd(rstkD), .delta(rspI));
// stack2 #(.DEPTH(24)) dstack(.clk(clk), .rd(st1), .we(dstkW), .wd(st0), .delta(dspI));
// stack2 #(.DEPTH(24)) rstack(.clk(clk), .rd(rst0), .we(rstkW), .wd(rstkD), .delta(rspI));
always @*
begin
// Compute the new value of st0. Could be pipelined now.
casez ({pc[12], insn_now[15:8]})
9'b1_???_?????: st0N = insn_now; // fetch from ram cycle. pc[12] isn't part of ram memory, rather is used to signify that a fetch from ram was requested, not a call.
9'b0_1??_?????: st0N = { {(`WIDTH - 15){1'b0}}, insn_now[14:0] }; // literal
9'b0_000_?????: st0N = st0; // jump
9'b0_010_?????: st0N = st0; // call, or fetch from ram if insn[12] is set.
9'b0_001_?????: st0N = st1; // conditional jump
9'b0_011_?0000: st0N = st0; // ALU operations...
9'b0_011_?0001: st0N = st1;
9'b0_011_?0010: st0N = st0 + st1;
9'b0_011_?0011: st0N = st0 & st1;
9'b0_011_?0100: st0N = st0 | st1;
9'b0_011_?0101: st0N = st0 ^ st1;
9'b0_011_?0110: st0N = ~st0;
9'b0_011_?0111: st0N = {`WIDTH{(st1 == st0)}};
9'b0_011_?1000: st0N = {`WIDTH{($signed(st1) < $signed(st0))}};
9'b0_011_?1001: st0N = {st0[`WIDTH - 1], st0[`WIDTH - 1:1]};
9'b0_011_?1010: st0N = {st0[`WIDTH - 2:0], 1'b0};
9'b0_011_?1011: st0N = rst0;
9'b0_011_?1100: st0N = io_din_now; // was io_din, which was a cycle late like insn and st0/st1/rst0/pc/dsp etc
9'b0_011_?1101: st0N = io_din_now;
9'b0_011_?1110: st0N = {{(`WIDTH - 5){1'b0}}, dsp};
9'b0_011_?1111: st0N = {`WIDTH{(st1 < st0)}};
default: st0N = {`WIDTH{1'bx}};
endcase
end
wire func_T_N = (insn_now[6:4] == 1);
wire func_T_R = (insn_now[6:4] == 2);
wire func_write = (insn_now[6:4] == 3);
wire func_iow = (insn_now[6:4] == 4);
wire func_ior = (insn_now[6:4] == 5);
wire is_alu = !pc[12] & (insn_now[15:13] == 3'b011);
assign mem_wr = !reboot & is_alu & func_write;
assign dout = st1;
assign io_wr = !reboot & is_alu & func_iow;
assign io_rd = !reboot & is_alu & func_ior;
assign io_slot = slot;
// return stack pushes pc_plus_1 for call only, or pushes st0 if the opcode asks.
assign rstkD = (insn_now[13] == 1'b0) ? {{(`WIDTH - 14){1'b0}}, pc_plus_1, 1'b0} : st0;
always @*
begin
casez ({pc[12], insn_now[15:13]})
4'b1_???, /* load from ram 2nd cycle */
4'b0_1??: /* immediate */ {dstkW, dspI} = {1'b1, 2'b01}; // push st0
4'b0_001: /* 0branch */ {dstkW, dspI} = {1'b0, 2'b11}; // pop d
4'b0_011: /* ALU */ {dstkW, dspI} = {func_T_N, {insn_now[1:0]}}; // as ALU opcode asks
default: {dstkW, dspI} = {1'b0, 2'b00}; // nop d stack
endcase
dspN = dsp + {dspI[1], dspI[1], dspI[1], dspI};
casez ({pc[12], insn_now[15:13]})
4'b1_???: /* readram */ {rstkW, rspI} = {1'b0, 2'b11};// pop r to pcN, so execution continues after an inserted fetch from ram cycle
4'b0_010: /* call */ {rstkW, rspI} = {1'b1, 2'b01}; // push PC+1 to rstkD. Abused with 13th bit set to allow fetches from ram.
4'b0_011: /* ALU */ {rstkW, rspI} = {func_T_R, insn_now[3:2]}; // as ALU opcode asks.
default: {rstkW, rspI} = {1'b0, 2'b00}; // nop r stack, same on jumps.
endcase
casez ({reboot, pc[12], insn_now[15:13], insn_now[7], |st0})
7'b1_?_???_?_?: pcN = 0; // reboot request must override all else, even a fetch cycle.
7'b0_0_000_?_?,
7'b0_0_010_?_?,
7'b0_0_001_?_0: pcN = insn_now[12:0];
7'b0_1_???_?_?, /* fetch from ram cycle, abuses instruction fetch to load the stack instead */
7'b0_0_011_1_?: pcN = rst0[13:1]; // r stack is 16 bits wide, but PC is always even.
default: pcN = pc_plus_1;
endcase
end
assign return_top = {2'b0,rst0[13:0]};
always @(posedge clk) begin
pcD <= {pcN, pcD[38:13]};
dspD <= {dspN, dspD[14:5]};
st0D <= {st0N, st0D[47:16]};
end
always @(negedge resetq or posedge clk) begin
if (!resetq) begin
reboot <= 1'b1;
{ pc, dsp, st0} <= 0;
slot <= 2'b00;
kill_slot <= 4'hf;
end else begin
// reboot needs to be set a clock in advance of the targeted slot.
// kill_slot_rq is read-ahead in case the next thread to execute's time should be up already.
reboot <= kill_slot[slotN] | kill_slot_rq[slotN];
// kill_slot register holds the signals until the right time, and are auto-cleared as each slot is reached, as it will already have been reset by the clock before.
kill_slot[3] <= kill_slot_rq[3] ? 1'b1 : ( (slot == 2'd3) ? 1'b0 : kill_slot[3]) ;
kill_slot[2] <= kill_slot_rq[2] ? 1'b1 : ( (slot == 2'd2) ? 1'b0 : kill_slot[2]) ;
kill_slot[1] <= kill_slot_rq[1] ? 1'b1 : ( (slot == 2'd1) ? 1'b0 : kill_slot[1]) ;
kill_slot[0] <= kill_slot_rq[0] ? 1'b1 : ( (slot == 2'd0) ? 1'b0 : kill_slot[0]) ;
pc <= pcD[12:0];
dsp <= dspD[4:0];
st0 <= st0D[15:0];
slot <= slotN;
end
end
endmodule
|
module FPU_Multiplication_Function_W64_EW11_SW52 ( clk, rst, beg_FSM, ack_FSM,
Data_MX, Data_MY, round_mode, overflow_flag, underflow_flag, ready,
final_result_ieee );
input [63:0] Data_MX;
input [63:0] Data_MY;
input [1:0] round_mode;
output [63:0] final_result_ieee;
input clk, rst, beg_FSM, ack_FSM;
output overflow_flag, underflow_flag, ready;
wire zero_flag, FSM_add_overflow_flag, FSM_selector_A, FSM_selector_C,
Exp_module_Overflow_flag_A, Sgf_operation_ODD1_left_N51,
Sgf_operation_ODD1_left_N50, Sgf_operation_ODD1_left_N49,
Sgf_operation_ODD1_left_N48, Sgf_operation_ODD1_left_N47,
Sgf_operation_ODD1_left_N46, Sgf_operation_ODD1_left_N45,
Sgf_operation_ODD1_left_N44, Sgf_operation_ODD1_left_N43,
Sgf_operation_ODD1_left_N42, Sgf_operation_ODD1_left_N41,
Sgf_operation_ODD1_left_N40, Sgf_operation_ODD1_left_N39,
Sgf_operation_ODD1_left_N38, Sgf_operation_ODD1_left_N37,
Sgf_operation_ODD1_left_N36, Sgf_operation_ODD1_left_N35,
Sgf_operation_ODD1_left_N34, Sgf_operation_ODD1_left_N33,
Sgf_operation_ODD1_left_N32, Sgf_operation_ODD1_left_N31,
Sgf_operation_ODD1_left_N30, Sgf_operation_ODD1_left_N29,
Sgf_operation_ODD1_left_N28, Sgf_operation_ODD1_left_N27,
Sgf_operation_ODD1_left_N26, Sgf_operation_ODD1_left_N25,
Sgf_operation_ODD1_left_N24, Sgf_operation_ODD1_left_N23,
Sgf_operation_ODD1_left_N22, Sgf_operation_ODD1_left_N21,
Sgf_operation_ODD1_left_N20, Sgf_operation_ODD1_left_N19,
Sgf_operation_ODD1_left_N18, Sgf_operation_ODD1_left_N17,
Sgf_operation_ODD1_left_N16, Sgf_operation_ODD1_left_N15,
Sgf_operation_ODD1_left_N14, Sgf_operation_ODD1_left_N13,
Sgf_operation_ODD1_left_N12, Sgf_operation_ODD1_left_N11,
Sgf_operation_ODD1_left_N10, Sgf_operation_ODD1_left_N9,
Sgf_operation_ODD1_left_N8, Sgf_operation_ODD1_left_N7,
Sgf_operation_ODD1_left_N6, Sgf_operation_ODD1_left_N5,
Sgf_operation_ODD1_left_N4, Sgf_operation_ODD1_left_N3,
Sgf_operation_ODD1_left_N2, Sgf_operation_ODD1_left_N1,
Sgf_operation_ODD1_right_N53, Sgf_operation_ODD1_right_N52,
Sgf_operation_ODD1_right_N51, Sgf_operation_ODD1_right_N50,
Sgf_operation_ODD1_right_N49, Sgf_operation_ODD1_right_N48,
Sgf_operation_ODD1_right_N47, Sgf_operation_ODD1_right_N46,
Sgf_operation_ODD1_right_N45, Sgf_operation_ODD1_right_N44,
Sgf_operation_ODD1_right_N43, Sgf_operation_ODD1_right_N42,
Sgf_operation_ODD1_right_N41, Sgf_operation_ODD1_right_N40,
Sgf_operation_ODD1_right_N39, Sgf_operation_ODD1_right_N38,
Sgf_operation_ODD1_right_N37, Sgf_operation_ODD1_right_N36,
Sgf_operation_ODD1_right_N35, Sgf_operation_ODD1_right_N34,
Sgf_operation_ODD1_right_N33, Sgf_operation_ODD1_right_N32,
Sgf_operation_ODD1_right_N31, Sgf_operation_ODD1_right_N30,
Sgf_operation_ODD1_right_N29, Sgf_operation_ODD1_right_N28,
Sgf_operation_ODD1_right_N27, Sgf_operation_ODD1_right_N26,
Sgf_operation_ODD1_right_N25, Sgf_operation_ODD1_right_N24,
Sgf_operation_ODD1_right_N23, Sgf_operation_ODD1_right_N22,
Sgf_operation_ODD1_right_N21, Sgf_operation_ODD1_right_N20,
Sgf_operation_ODD1_right_N19, Sgf_operation_ODD1_right_N18,
Sgf_operation_ODD1_right_N17, Sgf_operation_ODD1_right_N16,
Sgf_operation_ODD1_right_N15, Sgf_operation_ODD1_right_N14,
Sgf_operation_ODD1_right_N13, Sgf_operation_ODD1_right_N12,
Sgf_operation_ODD1_right_N11, Sgf_operation_ODD1_right_N10,
Sgf_operation_ODD1_right_N9, Sgf_operation_ODD1_right_N8,
Sgf_operation_ODD1_right_N7, Sgf_operation_ODD1_right_N6,
Sgf_operation_ODD1_right_N5, Sgf_operation_ODD1_right_N4,
Sgf_operation_ODD1_right_N3, Sgf_operation_ODD1_right_N2,
Sgf_operation_ODD1_right_N1, Sgf_operation_ODD1_middle_N55,
Sgf_operation_ODD1_middle_N54, Sgf_operation_ODD1_middle_N53,
Sgf_operation_ODD1_middle_N52, Sgf_operation_ODD1_middle_N51,
Sgf_operation_ODD1_middle_N50, Sgf_operation_ODD1_middle_N49,
Sgf_operation_ODD1_middle_N48, Sgf_operation_ODD1_middle_N47,
Sgf_operation_ODD1_middle_N46, Sgf_operation_ODD1_middle_N45,
Sgf_operation_ODD1_middle_N44, Sgf_operation_ODD1_middle_N43,
Sgf_operation_ODD1_middle_N42, Sgf_operation_ODD1_middle_N41,
Sgf_operation_ODD1_middle_N40, Sgf_operation_ODD1_middle_N39,
Sgf_operation_ODD1_middle_N38, Sgf_operation_ODD1_middle_N37,
Sgf_operation_ODD1_middle_N36, Sgf_operation_ODD1_middle_N35,
Sgf_operation_ODD1_middle_N34, Sgf_operation_ODD1_middle_N33,
Sgf_operation_ODD1_middle_N32, Sgf_operation_ODD1_middle_N31,
Sgf_operation_ODD1_middle_N30, Sgf_operation_ODD1_middle_N29,
Sgf_operation_ODD1_middle_N28, Sgf_operation_ODD1_middle_N27,
Sgf_operation_ODD1_middle_N26, Sgf_operation_ODD1_middle_N25,
Sgf_operation_ODD1_middle_N24, Sgf_operation_ODD1_middle_N23,
Sgf_operation_ODD1_middle_N22, Sgf_operation_ODD1_middle_N21,
Sgf_operation_ODD1_middle_N20, Sgf_operation_ODD1_middle_N19,
Sgf_operation_ODD1_middle_N18, Sgf_operation_ODD1_middle_N17,
Sgf_operation_ODD1_middle_N16, Sgf_operation_ODD1_middle_N15,
Sgf_operation_ODD1_middle_N14, Sgf_operation_ODD1_middle_N13,
Sgf_operation_ODD1_middle_N12, Sgf_operation_ODD1_middle_N11,
Sgf_operation_ODD1_middle_N10, Sgf_operation_ODD1_middle_N9,
Sgf_operation_ODD1_middle_N8, Sgf_operation_ODD1_middle_N7,
Sgf_operation_ODD1_middle_N6, Sgf_operation_ODD1_middle_N5,
Sgf_operation_ODD1_middle_N4, Sgf_operation_ODD1_middle_N3,
Sgf_operation_ODD1_middle_N2, n287, n289, n290, n291, n292, n293,
n294, n295, n296, n297, n298, n299, n300, n301, n302, n303, n304,
n305, n306, n307, n308, n309, n310, n311, n312, n313, n314, n315,
n316, n317, n318, n319, n320, n321, n322, n323, n324, n325, n326,
n327, n328, n329, n330, n331, n332, n333, n334, n335, n336, n337,
n338, n339, n340, n341, n342, n343, n344, n345, n346, n347, n348,
n349, n350, n351, n352, n353, n354, n355, n356, n357, n358, n359,
n360, n361, n362, n363, n364, n365, n366, n367, n368, n369, n370,
n371, n372, n373, n374, n375, n376, n377, n378, n379, n380, n381,
n382, n383, n384, n385, n386, n387, n388, n389, n390, n391, n392,
n393, n394, n395, n396, n397, n398, n399, n400, n401, n402, n403,
n404, n405, n406, n407, n408, n409, n410, n411, n412, n413, n414,
n415, n416, n417, n418, n419, n420, n421, n422, n423, n424, n425,
n426, n427, n428, n429, n430, n431, n432, n433, n434, n435, n436,
n437, n438, n439, n440, n441, n442, n443, n444, n445, n446, n447,
n448, n449, n450, n451, n452, n453, n454, n455, n456, n457, n458,
n459, n460, n461, n462, n463, n464, n465, n466, n467, n468, n469,
n470, n471, n472, n473, n474, n475, n476, n477, n478, n479, n480,
n481, n482, n483, n484, n485, n486, n487, n488, n489, n490, n491,
n492, n493, n494, n495, n496, n497, n498, n499, n500, n501, n502,
n503, n504, n505, n506, n507, n508, n509, n510, n511, n512, n513,
n514, n515, n516, n517, n518, n519, n520, n521, n522, n523, n524,
n525, n526, n527, n528, n529, n530, n531, n532, n533, n534, n535,
n536, n537, n538, n539, n540, n541, n542, n543, n544, n545, n546,
n547, n548, n549, n550, n551, n552, n553, n554, n555, n556, n557,
n558, n559, n560, n561, n562, n563, n564, n565, n566, n567, n568,
n569, n570, n571, n572, n573, n574, n575, n576, n577, n578, n579,
n580, n581, n582, n583, n584, n585, n586, n587, n588, n589, n590,
n591, n592, n593, n594, n595, n596, n597, n598, n599, n600, n601,
n602, n603, n604, n605, n606, n607, n608, n609, n610, n611, n612,
n613, n614, n615, n616, n617, n618, n619, n620, n621, n622, n623,
n624, n625, n626, n627, n628, n629, n630, n631, n632, n633, n634,
n635, n636, n637, n638, n639, n640, n641, n642, n643, n644, n645,
n646, n647, n648, n649, n650, n651, n652, n653, n654, n655, n656,
n657, n658, n659, n660, n661, n662, n663, n664, n665, n666, n667,
n668, n669, n670, n671, n672, n673, n674, n675, n676, n677, n678,
n679, n680, n681, n682, n683, n684, n685, n686, n687, n688, n689,
n690, n691, n692, n693, n694, n695, n696, n697, n698, n699, n700,
n701, n702, n703, n704, n705, n706, n707, n708, n709, n710, n711,
n712, n713, n714, n715, DP_OP_36J43_124_1029_n28,
DP_OP_36J43_124_1029_n27, DP_OP_36J43_124_1029_n26,
DP_OP_36J43_124_1029_n25, DP_OP_36J43_124_1029_n24,
DP_OP_36J43_124_1029_n23, DP_OP_36J43_124_1029_n22,
DP_OP_36J43_124_1029_n21, DP_OP_36J43_124_1029_n20,
DP_OP_36J43_124_1029_n19, DP_OP_36J43_124_1029_n18,
DP_OP_36J43_124_1029_n12, DP_OP_36J43_124_1029_n11,
DP_OP_36J43_124_1029_n10, DP_OP_36J43_124_1029_n9,
DP_OP_36J43_124_1029_n8, DP_OP_36J43_124_1029_n7,
DP_OP_36J43_124_1029_n6, DP_OP_36J43_124_1029_n5,
DP_OP_36J43_124_1029_n4, DP_OP_36J43_124_1029_n3,
DP_OP_36J43_124_1029_n2, DP_OP_36J43_124_1029_n1,
DP_OP_169J43_123_4229_n2318, DP_OP_169J43_123_4229_n1756,
DP_OP_169J43_123_4229_n1755, DP_OP_169J43_123_4229_n1754,
DP_OP_169J43_123_4229_n1753, DP_OP_169J43_123_4229_n1752,
DP_OP_169J43_123_4229_n1751, DP_OP_169J43_123_4229_n1750,
DP_OP_169J43_123_4229_n1749, DP_OP_169J43_123_4229_n1748,
DP_OP_169J43_123_4229_n1747, DP_OP_169J43_123_4229_n1746,
DP_OP_169J43_123_4229_n1745, DP_OP_169J43_123_4229_n1744,
DP_OP_169J43_123_4229_n1743, DP_OP_169J43_123_4229_n1742,
DP_OP_169J43_123_4229_n1741, DP_OP_169J43_123_4229_n1740,
DP_OP_169J43_123_4229_n1739, DP_OP_169J43_123_4229_n1738,
DP_OP_169J43_123_4229_n1737, DP_OP_169J43_123_4229_n1736,
DP_OP_169J43_123_4229_n1735, DP_OP_169J43_123_4229_n1734,
DP_OP_169J43_123_4229_n1729, DP_OP_169J43_123_4229_n1728,
DP_OP_169J43_123_4229_n1727, DP_OP_169J43_123_4229_n1726,
DP_OP_169J43_123_4229_n1725, DP_OP_169J43_123_4229_n1724,
DP_OP_169J43_123_4229_n1723, DP_OP_169J43_123_4229_n1722,
DP_OP_169J43_123_4229_n1721, DP_OP_169J43_123_4229_n1720,
DP_OP_169J43_123_4229_n1719, DP_OP_169J43_123_4229_n1718,
DP_OP_169J43_123_4229_n1717, DP_OP_169J43_123_4229_n1716,
DP_OP_169J43_123_4229_n1715, DP_OP_169J43_123_4229_n1714,
DP_OP_169J43_123_4229_n1713, DP_OP_169J43_123_4229_n1712,
DP_OP_169J43_123_4229_n1711, DP_OP_169J43_123_4229_n1710,
DP_OP_169J43_123_4229_n1709, DP_OP_169J43_123_4229_n1708,
DP_OP_169J43_123_4229_n1707, DP_OP_169J43_123_4229_n1706,
DP_OP_169J43_123_4229_n1705, DP_OP_169J43_123_4229_n1701,
DP_OP_169J43_123_4229_n1700, DP_OP_169J43_123_4229_n1699,
DP_OP_169J43_123_4229_n1698, DP_OP_169J43_123_4229_n1697,
DP_OP_169J43_123_4229_n1696, DP_OP_169J43_123_4229_n1695,
DP_OP_169J43_123_4229_n1694, DP_OP_169J43_123_4229_n1693,
DP_OP_169J43_123_4229_n1692, DP_OP_169J43_123_4229_n1691,
DP_OP_169J43_123_4229_n1690, DP_OP_169J43_123_4229_n1689,
DP_OP_169J43_123_4229_n1688, DP_OP_169J43_123_4229_n1687,
DP_OP_169J43_123_4229_n1686, DP_OP_169J43_123_4229_n1685,
DP_OP_169J43_123_4229_n1684, DP_OP_169J43_123_4229_n1683,
DP_OP_169J43_123_4229_n1682, DP_OP_169J43_123_4229_n1681,
DP_OP_169J43_123_4229_n1680, DP_OP_169J43_123_4229_n1679,
DP_OP_169J43_123_4229_n1678, DP_OP_169J43_123_4229_n1677,
DP_OP_169J43_123_4229_n1676, DP_OP_169J43_123_4229_n1675,
DP_OP_169J43_123_4229_n1674, DP_OP_169J43_123_4229_n1673,
DP_OP_169J43_123_4229_n1669, DP_OP_169J43_123_4229_n1668,
DP_OP_169J43_123_4229_n1667, DP_OP_169J43_123_4229_n1666,
DP_OP_169J43_123_4229_n1665, DP_OP_169J43_123_4229_n1664,
DP_OP_169J43_123_4229_n1663, DP_OP_169J43_123_4229_n1662,
DP_OP_169J43_123_4229_n1661, DP_OP_169J43_123_4229_n1660,
DP_OP_169J43_123_4229_n1659, DP_OP_169J43_123_4229_n1658,
DP_OP_169J43_123_4229_n1657, DP_OP_169J43_123_4229_n1656,
DP_OP_169J43_123_4229_n1655, DP_OP_169J43_123_4229_n1654,
DP_OP_169J43_123_4229_n1653, DP_OP_169J43_123_4229_n1652,
DP_OP_169J43_123_4229_n1651, DP_OP_169J43_123_4229_n1650,
DP_OP_169J43_123_4229_n1649, DP_OP_169J43_123_4229_n1648,
DP_OP_169J43_123_4229_n1647, DP_OP_169J43_123_4229_n1646,
DP_OP_169J43_123_4229_n1645, DP_OP_169J43_123_4229_n1641,
DP_OP_169J43_123_4229_n1640, DP_OP_169J43_123_4229_n1639,
DP_OP_169J43_123_4229_n1638, DP_OP_169J43_123_4229_n1637,
DP_OP_169J43_123_4229_n1636, DP_OP_169J43_123_4229_n1635,
DP_OP_169J43_123_4229_n1634, DP_OP_169J43_123_4229_n1633,
DP_OP_169J43_123_4229_n1632, DP_OP_169J43_123_4229_n1631,
DP_OP_169J43_123_4229_n1630, DP_OP_169J43_123_4229_n1629,
DP_OP_169J43_123_4229_n1628, DP_OP_169J43_123_4229_n1627,
DP_OP_169J43_123_4229_n1626, DP_OP_169J43_123_4229_n1625,
DP_OP_169J43_123_4229_n1624, DP_OP_169J43_123_4229_n1623,
DP_OP_169J43_123_4229_n1622, DP_OP_169J43_123_4229_n1621,
DP_OP_169J43_123_4229_n1620, DP_OP_169J43_123_4229_n1619,
DP_OP_169J43_123_4229_n1618, DP_OP_169J43_123_4229_n1617,
DP_OP_169J43_123_4229_n1616, DP_OP_169J43_123_4229_n1615,
DP_OP_169J43_123_4229_n1614, DP_OP_169J43_123_4229_n1613,
DP_OP_169J43_123_4229_n1609, DP_OP_169J43_123_4229_n1608,
DP_OP_169J43_123_4229_n1607, DP_OP_169J43_123_4229_n1606,
DP_OP_169J43_123_4229_n1605, DP_OP_169J43_123_4229_n1604,
DP_OP_169J43_123_4229_n1603, DP_OP_169J43_123_4229_n1602,
DP_OP_169J43_123_4229_n1601, DP_OP_169J43_123_4229_n1600,
DP_OP_169J43_123_4229_n1599, DP_OP_169J43_123_4229_n1598,
DP_OP_169J43_123_4229_n1597, DP_OP_169J43_123_4229_n1596,
DP_OP_169J43_123_4229_n1595, DP_OP_169J43_123_4229_n1594,
DP_OP_169J43_123_4229_n1593, DP_OP_169J43_123_4229_n1592,
DP_OP_169J43_123_4229_n1591, DP_OP_169J43_123_4229_n1590,
DP_OP_169J43_123_4229_n1589, DP_OP_169J43_123_4229_n1588,
DP_OP_169J43_123_4229_n1587, DP_OP_169J43_123_4229_n1586,
DP_OP_169J43_123_4229_n1585, DP_OP_169J43_123_4229_n1581,
DP_OP_169J43_123_4229_n1580, DP_OP_169J43_123_4229_n1579,
DP_OP_169J43_123_4229_n1578, DP_OP_169J43_123_4229_n1577,
DP_OP_169J43_123_4229_n1576, DP_OP_169J43_123_4229_n1575,
DP_OP_169J43_123_4229_n1574, DP_OP_169J43_123_4229_n1573,
DP_OP_169J43_123_4229_n1572, DP_OP_169J43_123_4229_n1571,
DP_OP_169J43_123_4229_n1570, DP_OP_169J43_123_4229_n1569,
DP_OP_169J43_123_4229_n1568, DP_OP_169J43_123_4229_n1567,
DP_OP_169J43_123_4229_n1566, DP_OP_169J43_123_4229_n1565,
DP_OP_169J43_123_4229_n1564, DP_OP_169J43_123_4229_n1563,
DP_OP_169J43_123_4229_n1562, DP_OP_169J43_123_4229_n1561,
DP_OP_169J43_123_4229_n1560, DP_OP_169J43_123_4229_n1559,
DP_OP_169J43_123_4229_n1558, DP_OP_169J43_123_4229_n1557,
DP_OP_169J43_123_4229_n1556, DP_OP_169J43_123_4229_n1555,
DP_OP_169J43_123_4229_n1554, DP_OP_169J43_123_4229_n1553,
DP_OP_169J43_123_4229_n1549, DP_OP_169J43_123_4229_n1548,
DP_OP_169J43_123_4229_n1547, DP_OP_169J43_123_4229_n1546,
DP_OP_169J43_123_4229_n1545, DP_OP_169J43_123_4229_n1544,
DP_OP_169J43_123_4229_n1543, DP_OP_169J43_123_4229_n1542,
DP_OP_169J43_123_4229_n1541, DP_OP_169J43_123_4229_n1540,
DP_OP_169J43_123_4229_n1539, DP_OP_169J43_123_4229_n1538,
DP_OP_169J43_123_4229_n1537, DP_OP_169J43_123_4229_n1536,
DP_OP_169J43_123_4229_n1535, DP_OP_169J43_123_4229_n1534,
DP_OP_169J43_123_4229_n1533, DP_OP_169J43_123_4229_n1532,
DP_OP_169J43_123_4229_n1531, DP_OP_169J43_123_4229_n1530,
DP_OP_169J43_123_4229_n1529, DP_OP_169J43_123_4229_n1528,
DP_OP_169J43_123_4229_n1527, DP_OP_169J43_123_4229_n1526,
DP_OP_169J43_123_4229_n1521, DP_OP_169J43_123_4229_n1520,
DP_OP_169J43_123_4229_n1519, DP_OP_169J43_123_4229_n1518,
DP_OP_169J43_123_4229_n1517, DP_OP_169J43_123_4229_n1516,
DP_OP_169J43_123_4229_n1515, DP_OP_169J43_123_4229_n1514,
DP_OP_169J43_123_4229_n1513, DP_OP_169J43_123_4229_n1512,
DP_OP_169J43_123_4229_n1511, DP_OP_169J43_123_4229_n1510,
DP_OP_169J43_123_4229_n1509, DP_OP_169J43_123_4229_n1508,
DP_OP_169J43_123_4229_n1507, DP_OP_169J43_123_4229_n1506,
DP_OP_169J43_123_4229_n1505, DP_OP_169J43_123_4229_n1504,
DP_OP_169J43_123_4229_n1503, DP_OP_169J43_123_4229_n1502,
DP_OP_169J43_123_4229_n1501, DP_OP_169J43_123_4229_n1500,
DP_OP_169J43_123_4229_n1499, DP_OP_169J43_123_4229_n1498,
DP_OP_169J43_123_4229_n1497, DP_OP_169J43_123_4229_n1496,
DP_OP_169J43_123_4229_n1495, DP_OP_169J43_123_4229_n1494,
DP_OP_169J43_123_4229_n1493, DP_OP_169J43_123_4229_n1489,
DP_OP_169J43_123_4229_n1488, DP_OP_169J43_123_4229_n1487,
DP_OP_169J43_123_4229_n1486, DP_OP_169J43_123_4229_n1485,
DP_OP_169J43_123_4229_n1484, DP_OP_169J43_123_4229_n1483,
DP_OP_169J43_123_4229_n1482, DP_OP_169J43_123_4229_n1481,
DP_OP_169J43_123_4229_n1480, DP_OP_169J43_123_4229_n1479,
DP_OP_169J43_123_4229_n1478, DP_OP_169J43_123_4229_n1477,
DP_OP_169J43_123_4229_n1476, DP_OP_169J43_123_4229_n1475,
DP_OP_169J43_123_4229_n1474, DP_OP_169J43_123_4229_n1473,
DP_OP_169J43_123_4229_n1472, DP_OP_169J43_123_4229_n1471,
DP_OP_169J43_123_4229_n1470, DP_OP_169J43_123_4229_n1469,
DP_OP_169J43_123_4229_n1468, DP_OP_169J43_123_4229_n1467,
DP_OP_169J43_123_4229_n1466, DP_OP_169J43_123_4229_n1461,
DP_OP_169J43_123_4229_n1460, DP_OP_169J43_123_4229_n1459,
DP_OP_169J43_123_4229_n1458, DP_OP_169J43_123_4229_n1457,
DP_OP_169J43_123_4229_n1456, DP_OP_169J43_123_4229_n1455,
DP_OP_169J43_123_4229_n1454, DP_OP_169J43_123_4229_n1453,
DP_OP_169J43_123_4229_n1452, DP_OP_169J43_123_4229_n1451,
DP_OP_169J43_123_4229_n1450, DP_OP_169J43_123_4229_n1449,
DP_OP_169J43_123_4229_n1448, DP_OP_169J43_123_4229_n1447,
DP_OP_169J43_123_4229_n1446, DP_OP_169J43_123_4229_n1445,
DP_OP_169J43_123_4229_n1444, DP_OP_169J43_123_4229_n1443,
DP_OP_169J43_123_4229_n1442, DP_OP_169J43_123_4229_n1441,
DP_OP_169J43_123_4229_n1440, DP_OP_169J43_123_4229_n1439,
DP_OP_169J43_123_4229_n1438, DP_OP_169J43_123_4229_n1437,
DP_OP_169J43_123_4229_n1436, DP_OP_169J43_123_4229_n1435,
DP_OP_169J43_123_4229_n1434, DP_OP_169J43_123_4229_n1433,
DP_OP_169J43_123_4229_n1429, DP_OP_169J43_123_4229_n1428,
DP_OP_169J43_123_4229_n1427, DP_OP_169J43_123_4229_n1426,
DP_OP_169J43_123_4229_n1425, DP_OP_169J43_123_4229_n1424,
DP_OP_169J43_123_4229_n1423, DP_OP_169J43_123_4229_n1422,
DP_OP_169J43_123_4229_n1421, DP_OP_169J43_123_4229_n1420,
DP_OP_169J43_123_4229_n1419, DP_OP_169J43_123_4229_n1418,
DP_OP_169J43_123_4229_n1417, DP_OP_169J43_123_4229_n1416,
DP_OP_169J43_123_4229_n1415, DP_OP_169J43_123_4229_n1414,
DP_OP_169J43_123_4229_n1413, DP_OP_169J43_123_4229_n1412,
DP_OP_169J43_123_4229_n1411, DP_OP_169J43_123_4229_n1410,
DP_OP_169J43_123_4229_n1409, DP_OP_169J43_123_4229_n1408,
DP_OP_169J43_123_4229_n1407, DP_OP_169J43_123_4229_n1406,
DP_OP_169J43_123_4229_n1401, DP_OP_169J43_123_4229_n1400,
DP_OP_169J43_123_4229_n1399, DP_OP_169J43_123_4229_n1398,
DP_OP_169J43_123_4229_n1397, DP_OP_169J43_123_4229_n1396,
DP_OP_169J43_123_4229_n1395, DP_OP_169J43_123_4229_n1394,
DP_OP_169J43_123_4229_n1393, DP_OP_169J43_123_4229_n1392,
DP_OP_169J43_123_4229_n1391, DP_OP_169J43_123_4229_n1390,
DP_OP_169J43_123_4229_n1388, DP_OP_169J43_123_4229_n1387,
DP_OP_169J43_123_4229_n1386, DP_OP_169J43_123_4229_n1385,
DP_OP_169J43_123_4229_n1384, DP_OP_169J43_123_4229_n1383,
DP_OP_169J43_123_4229_n1382, DP_OP_169J43_123_4229_n1380,
DP_OP_169J43_123_4229_n1379, DP_OP_169J43_123_4229_n1378,
DP_OP_169J43_123_4229_n1376, DP_OP_169J43_123_4229_n1375,
DP_OP_169J43_123_4229_n1374, DP_OP_169J43_123_4229_n1373,
DP_OP_169J43_123_4229_n1368, DP_OP_169J43_123_4229_n1367,
DP_OP_169J43_123_4229_n1366, DP_OP_169J43_123_4229_n1364,
DP_OP_169J43_123_4229_n1363, DP_OP_169J43_123_4229_n1362,
DP_OP_169J43_123_4229_n1360, DP_OP_169J43_123_4229_n1359,
DP_OP_169J43_123_4229_n1358, DP_OP_169J43_123_4229_n1357,
DP_OP_169J43_123_4229_n1356, DP_OP_169J43_123_4229_n1355,
DP_OP_169J43_123_4229_n1354, DP_OP_169J43_123_4229_n1353,
DP_OP_169J43_123_4229_n1352, DP_OP_169J43_123_4229_n1351,
DP_OP_169J43_123_4229_n1350, DP_OP_169J43_123_4229_n1349,
DP_OP_169J43_123_4229_n1348, DP_OP_169J43_123_4229_n1347,
DP_OP_169J43_123_4229_n1346, DP_OP_169J43_123_4229_n1339,
DP_OP_169J43_123_4229_n1337, DP_OP_169J43_123_4229_n1335,
DP_OP_169J43_123_4229_n1333, DP_OP_169J43_123_4229_n1331,
DP_OP_169J43_123_4229_n1329, DP_OP_169J43_123_4229_n1308,
DP_OP_169J43_123_4229_n1305, DP_OP_169J43_123_4229_n1304,
DP_OP_169J43_123_4229_n1303, DP_OP_169J43_123_4229_n1302,
DP_OP_169J43_123_4229_n1300, DP_OP_169J43_123_4229_n1299,
DP_OP_169J43_123_4229_n1298, DP_OP_169J43_123_4229_n1297,
DP_OP_169J43_123_4229_n1295, DP_OP_169J43_123_4229_n1294,
DP_OP_169J43_123_4229_n1293, DP_OP_169J43_123_4229_n1291,
DP_OP_169J43_123_4229_n1290, DP_OP_169J43_123_4229_n1289,
DP_OP_169J43_123_4229_n1288, DP_OP_169J43_123_4229_n1287,
DP_OP_169J43_123_4229_n1286, DP_OP_169J43_123_4229_n1285,
DP_OP_169J43_123_4229_n1284, DP_OP_169J43_123_4229_n1283,
DP_OP_169J43_123_4229_n1282, DP_OP_169J43_123_4229_n1281,
DP_OP_169J43_123_4229_n1280, DP_OP_169J43_123_4229_n1279,
DP_OP_169J43_123_4229_n1277, DP_OP_169J43_123_4229_n1276,
DP_OP_169J43_123_4229_n1275, DP_OP_169J43_123_4229_n1274,
DP_OP_169J43_123_4229_n1273, DP_OP_169J43_123_4229_n1272,
DP_OP_169J43_123_4229_n1271, DP_OP_169J43_123_4229_n1269,
DP_OP_169J43_123_4229_n1268, DP_OP_169J43_123_4229_n1267,
DP_OP_169J43_123_4229_n1266, DP_OP_169J43_123_4229_n1265,
DP_OP_169J43_123_4229_n1264, DP_OP_169J43_123_4229_n1262,
DP_OP_169J43_123_4229_n1261, DP_OP_169J43_123_4229_n1260,
DP_OP_169J43_123_4229_n1259, DP_OP_169J43_123_4229_n1258,
DP_OP_169J43_123_4229_n1257, DP_OP_169J43_123_4229_n1256,
DP_OP_169J43_123_4229_n1255, DP_OP_169J43_123_4229_n1254,
DP_OP_169J43_123_4229_n1253, DP_OP_169J43_123_4229_n1252,
DP_OP_169J43_123_4229_n1251, DP_OP_169J43_123_4229_n1250,
DP_OP_169J43_123_4229_n1249, DP_OP_169J43_123_4229_n1248,
DP_OP_169J43_123_4229_n1247, DP_OP_169J43_123_4229_n1246,
DP_OP_169J43_123_4229_n1245, DP_OP_169J43_123_4229_n1244,
DP_OP_169J43_123_4229_n1242, DP_OP_169J43_123_4229_n1241,
DP_OP_169J43_123_4229_n1240, DP_OP_169J43_123_4229_n1239,
DP_OP_169J43_123_4229_n1238, DP_OP_169J43_123_4229_n1237,
DP_OP_169J43_123_4229_n1236, DP_OP_169J43_123_4229_n1235,
DP_OP_169J43_123_4229_n1234, DP_OP_169J43_123_4229_n1233,
DP_OP_169J43_123_4229_n1231, DP_OP_169J43_123_4229_n1230,
DP_OP_169J43_123_4229_n1229, DP_OP_169J43_123_4229_n1228,
DP_OP_169J43_123_4229_n1227, DP_OP_169J43_123_4229_n1226,
DP_OP_169J43_123_4229_n1225, DP_OP_169J43_123_4229_n1224,
DP_OP_169J43_123_4229_n1223, DP_OP_169J43_123_4229_n1221,
DP_OP_169J43_123_4229_n1220, DP_OP_169J43_123_4229_n1219,
DP_OP_169J43_123_4229_n1218, DP_OP_169J43_123_4229_n1217,
DP_OP_169J43_123_4229_n1216, DP_OP_169J43_123_4229_n1215,
DP_OP_169J43_123_4229_n1214, DP_OP_169J43_123_4229_n1213,
DP_OP_169J43_123_4229_n1212, DP_OP_169J43_123_4229_n1211,
DP_OP_169J43_123_4229_n1210, DP_OP_169J43_123_4229_n1209,
DP_OP_169J43_123_4229_n1208, DP_OP_169J43_123_4229_n1207,
DP_OP_169J43_123_4229_n1206, DP_OP_169J43_123_4229_n1205,
DP_OP_169J43_123_4229_n1204, DP_OP_169J43_123_4229_n1203,
DP_OP_169J43_123_4229_n1202, DP_OP_169J43_123_4229_n1201,
DP_OP_169J43_123_4229_n1200, DP_OP_169J43_123_4229_n1199,
DP_OP_169J43_123_4229_n1198, DP_OP_169J43_123_4229_n1197,
DP_OP_169J43_123_4229_n1195, DP_OP_169J43_123_4229_n1194,
DP_OP_169J43_123_4229_n1193, DP_OP_169J43_123_4229_n1192,
DP_OP_169J43_123_4229_n1191, DP_OP_169J43_123_4229_n1190,
DP_OP_169J43_123_4229_n1189, DP_OP_169J43_123_4229_n1188,
DP_OP_169J43_123_4229_n1187, DP_OP_169J43_123_4229_n1186,
DP_OP_169J43_123_4229_n1185, DP_OP_169J43_123_4229_n1184,
DP_OP_169J43_123_4229_n1183, DP_OP_169J43_123_4229_n1181,
DP_OP_169J43_123_4229_n1180, DP_OP_169J43_123_4229_n1179,
DP_OP_169J43_123_4229_n1178, DP_OP_169J43_123_4229_n1177,
DP_OP_169J43_123_4229_n1176, DP_OP_169J43_123_4229_n1175,
DP_OP_169J43_123_4229_n1174, DP_OP_169J43_123_4229_n1173,
DP_OP_169J43_123_4229_n1172, DP_OP_169J43_123_4229_n1171,
DP_OP_169J43_123_4229_n1170, DP_OP_169J43_123_4229_n1168,
DP_OP_169J43_123_4229_n1167, DP_OP_169J43_123_4229_n1166,
DP_OP_169J43_123_4229_n1165, DP_OP_169J43_123_4229_n1164,
DP_OP_169J43_123_4229_n1163, DP_OP_169J43_123_4229_n1162,
DP_OP_169J43_123_4229_n1161, DP_OP_169J43_123_4229_n1160,
DP_OP_169J43_123_4229_n1159, DP_OP_169J43_123_4229_n1158,
DP_OP_169J43_123_4229_n1157, DP_OP_169J43_123_4229_n1156,
DP_OP_169J43_123_4229_n1155, DP_OP_169J43_123_4229_n1154,
DP_OP_169J43_123_4229_n1153, DP_OP_169J43_123_4229_n1152,
DP_OP_169J43_123_4229_n1151, DP_OP_169J43_123_4229_n1150,
DP_OP_169J43_123_4229_n1149, DP_OP_169J43_123_4229_n1148,
DP_OP_169J43_123_4229_n1147, DP_OP_169J43_123_4229_n1146,
DP_OP_169J43_123_4229_n1145, DP_OP_169J43_123_4229_n1144,
DP_OP_169J43_123_4229_n1143, DP_OP_169J43_123_4229_n1142,
DP_OP_169J43_123_4229_n1141, DP_OP_169J43_123_4229_n1140,
DP_OP_169J43_123_4229_n1139, DP_OP_169J43_123_4229_n1138,
DP_OP_169J43_123_4229_n1136, DP_OP_169J43_123_4229_n1135,
DP_OP_169J43_123_4229_n1134, DP_OP_169J43_123_4229_n1133,
DP_OP_169J43_123_4229_n1132, DP_OP_169J43_123_4229_n1131,
DP_OP_169J43_123_4229_n1130, DP_OP_169J43_123_4229_n1129,
DP_OP_169J43_123_4229_n1128, DP_OP_169J43_123_4229_n1127,
DP_OP_169J43_123_4229_n1126, DP_OP_169J43_123_4229_n1125,
DP_OP_169J43_123_4229_n1124, DP_OP_169J43_123_4229_n1123,
DP_OP_169J43_123_4229_n1122, DP_OP_169J43_123_4229_n1121,
DP_OP_169J43_123_4229_n1119, DP_OP_169J43_123_4229_n1118,
DP_OP_169J43_123_4229_n1117, DP_OP_169J43_123_4229_n1116,
DP_OP_169J43_123_4229_n1115, DP_OP_169J43_123_4229_n1114,
DP_OP_169J43_123_4229_n1113, DP_OP_169J43_123_4229_n1112,
DP_OP_169J43_123_4229_n1111, DP_OP_169J43_123_4229_n1110,
DP_OP_169J43_123_4229_n1109, DP_OP_169J43_123_4229_n1108,
DP_OP_169J43_123_4229_n1107, DP_OP_169J43_123_4229_n1106,
DP_OP_169J43_123_4229_n1105, DP_OP_169J43_123_4229_n1103,
DP_OP_169J43_123_4229_n1102, DP_OP_169J43_123_4229_n1101,
DP_OP_169J43_123_4229_n1100, DP_OP_169J43_123_4229_n1099,
DP_OP_169J43_123_4229_n1098, DP_OP_169J43_123_4229_n1097,
DP_OP_169J43_123_4229_n1096, DP_OP_169J43_123_4229_n1095,
DP_OP_169J43_123_4229_n1094, DP_OP_169J43_123_4229_n1093,
DP_OP_169J43_123_4229_n1092, DP_OP_169J43_123_4229_n1091,
DP_OP_169J43_123_4229_n1090, DP_OP_169J43_123_4229_n1089,
DP_OP_169J43_123_4229_n1088, DP_OP_169J43_123_4229_n1087,
DP_OP_169J43_123_4229_n1086, DP_OP_169J43_123_4229_n1085,
DP_OP_169J43_123_4229_n1084, DP_OP_169J43_123_4229_n1083,
DP_OP_169J43_123_4229_n1082, DP_OP_169J43_123_4229_n1081,
DP_OP_169J43_123_4229_n1080, DP_OP_169J43_123_4229_n1079,
DP_OP_169J43_123_4229_n1078, DP_OP_169J43_123_4229_n1077,
DP_OP_169J43_123_4229_n1076, DP_OP_169J43_123_4229_n1075,
DP_OP_169J43_123_4229_n1074, DP_OP_169J43_123_4229_n1073,
DP_OP_169J43_123_4229_n1072, DP_OP_169J43_123_4229_n1071,
DP_OP_169J43_123_4229_n1070, DP_OP_169J43_123_4229_n1069,
DP_OP_169J43_123_4229_n1068, DP_OP_169J43_123_4229_n1067,
DP_OP_169J43_123_4229_n1065, DP_OP_169J43_123_4229_n1064,
DP_OP_169J43_123_4229_n1063, DP_OP_169J43_123_4229_n1062,
DP_OP_169J43_123_4229_n1061, DP_OP_169J43_123_4229_n1060,
DP_OP_169J43_123_4229_n1059, DP_OP_169J43_123_4229_n1058,
DP_OP_169J43_123_4229_n1057, DP_OP_169J43_123_4229_n1056,
DP_OP_169J43_123_4229_n1055, DP_OP_169J43_123_4229_n1054,
DP_OP_169J43_123_4229_n1053, DP_OP_169J43_123_4229_n1052,
DP_OP_169J43_123_4229_n1051, DP_OP_169J43_123_4229_n1050,
DP_OP_169J43_123_4229_n1049, DP_OP_169J43_123_4229_n1048,
DP_OP_169J43_123_4229_n1047, DP_OP_169J43_123_4229_n1046,
DP_OP_169J43_123_4229_n1045, DP_OP_169J43_123_4229_n1044,
DP_OP_169J43_123_4229_n1043, DP_OP_169J43_123_4229_n1042,
DP_OP_169J43_123_4229_n1041, DP_OP_169J43_123_4229_n1040,
DP_OP_169J43_123_4229_n1039, DP_OP_169J43_123_4229_n1038,
DP_OP_169J43_123_4229_n1037, DP_OP_169J43_123_4229_n1036,
DP_OP_169J43_123_4229_n1035, DP_OP_169J43_123_4229_n1034,
DP_OP_169J43_123_4229_n1033, DP_OP_169J43_123_4229_n1032,
DP_OP_169J43_123_4229_n1031, DP_OP_169J43_123_4229_n1030,
DP_OP_169J43_123_4229_n1029, DP_OP_169J43_123_4229_n1028,
DP_OP_169J43_123_4229_n1026, DP_OP_169J43_123_4229_n1025,
DP_OP_169J43_123_4229_n1024, DP_OP_169J43_123_4229_n1023,
DP_OP_169J43_123_4229_n1022, DP_OP_169J43_123_4229_n1021,
DP_OP_169J43_123_4229_n1020, DP_OP_169J43_123_4229_n1019,
DP_OP_169J43_123_4229_n1018, DP_OP_169J43_123_4229_n1017,
DP_OP_169J43_123_4229_n1016, DP_OP_169J43_123_4229_n1015,
DP_OP_169J43_123_4229_n1014, DP_OP_169J43_123_4229_n1013,
DP_OP_169J43_123_4229_n1012, DP_OP_169J43_123_4229_n1011,
DP_OP_169J43_123_4229_n1010, DP_OP_169J43_123_4229_n1009,
DP_OP_169J43_123_4229_n1008, DP_OP_169J43_123_4229_n1007,
DP_OP_169J43_123_4229_n1004, DP_OP_169J43_123_4229_n1003,
DP_OP_169J43_123_4229_n1002, DP_OP_169J43_123_4229_n1001,
DP_OP_169J43_123_4229_n1000, DP_OP_169J43_123_4229_n999,
DP_OP_169J43_123_4229_n998, DP_OP_169J43_123_4229_n997,
DP_OP_169J43_123_4229_n996, DP_OP_169J43_123_4229_n995,
DP_OP_169J43_123_4229_n994, DP_OP_169J43_123_4229_n993,
DP_OP_169J43_123_4229_n992, DP_OP_169J43_123_4229_n991,
DP_OP_169J43_123_4229_n990, DP_OP_169J43_123_4229_n989,
DP_OP_169J43_123_4229_n988, DP_OP_169J43_123_4229_n987,
DP_OP_169J43_123_4229_n986, DP_OP_169J43_123_4229_n985,
DP_OP_169J43_123_4229_n984, DP_OP_169J43_123_4229_n983,
DP_OP_169J43_123_4229_n982, DP_OP_169J43_123_4229_n981,
DP_OP_169J43_123_4229_n980, DP_OP_169J43_123_4229_n979,
DP_OP_169J43_123_4229_n978, DP_OP_169J43_123_4229_n977,
DP_OP_169J43_123_4229_n976, DP_OP_169J43_123_4229_n975,
DP_OP_169J43_123_4229_n974, DP_OP_169J43_123_4229_n973,
DP_OP_169J43_123_4229_n972, DP_OP_169J43_123_4229_n971,
DP_OP_169J43_123_4229_n970, DP_OP_169J43_123_4229_n969,
DP_OP_169J43_123_4229_n968, DP_OP_169J43_123_4229_n967,
DP_OP_169J43_123_4229_n966, DP_OP_169J43_123_4229_n965,
DP_OP_169J43_123_4229_n964, DP_OP_169J43_123_4229_n963,
DP_OP_169J43_123_4229_n962, DP_OP_169J43_123_4229_n961,
DP_OP_169J43_123_4229_n960, DP_OP_169J43_123_4229_n959,
DP_OP_169J43_123_4229_n958, DP_OP_169J43_123_4229_n957,
DP_OP_169J43_123_4229_n956, DP_OP_169J43_123_4229_n955,
DP_OP_169J43_123_4229_n954, DP_OP_169J43_123_4229_n953,
DP_OP_169J43_123_4229_n952, DP_OP_169J43_123_4229_n951,
DP_OP_169J43_123_4229_n950, DP_OP_169J43_123_4229_n949,
DP_OP_169J43_123_4229_n948, DP_OP_169J43_123_4229_n947,
DP_OP_169J43_123_4229_n946, DP_OP_169J43_123_4229_n945,
DP_OP_169J43_123_4229_n944, DP_OP_169J43_123_4229_n943,
DP_OP_169J43_123_4229_n942, DP_OP_169J43_123_4229_n941,
DP_OP_169J43_123_4229_n940, DP_OP_169J43_123_4229_n939,
DP_OP_169J43_123_4229_n938, DP_OP_169J43_123_4229_n937,
DP_OP_169J43_123_4229_n936, DP_OP_169J43_123_4229_n935,
DP_OP_169J43_123_4229_n934, DP_OP_169J43_123_4229_n933,
DP_OP_169J43_123_4229_n932, DP_OP_169J43_123_4229_n931,
DP_OP_169J43_123_4229_n930, DP_OP_169J43_123_4229_n929,
DP_OP_169J43_123_4229_n928, DP_OP_169J43_123_4229_n927,
DP_OP_169J43_123_4229_n924, DP_OP_169J43_123_4229_n923,
DP_OP_169J43_123_4229_n922, DP_OP_169J43_123_4229_n921,
DP_OP_169J43_123_4229_n920, DP_OP_169J43_123_4229_n919,
DP_OP_169J43_123_4229_n918, DP_OP_169J43_123_4229_n917,
DP_OP_169J43_123_4229_n916, DP_OP_169J43_123_4229_n915,
DP_OP_169J43_123_4229_n914, DP_OP_169J43_123_4229_n913,
DP_OP_169J43_123_4229_n912, DP_OP_169J43_123_4229_n911,
DP_OP_169J43_123_4229_n910, DP_OP_169J43_123_4229_n909,
DP_OP_169J43_123_4229_n908, DP_OP_169J43_123_4229_n907,
DP_OP_169J43_123_4229_n906, DP_OP_169J43_123_4229_n905,
DP_OP_169J43_123_4229_n904, DP_OP_169J43_123_4229_n903,
DP_OP_169J43_123_4229_n902, DP_OP_169J43_123_4229_n901,
DP_OP_169J43_123_4229_n900, DP_OP_169J43_123_4229_n899,
DP_OP_169J43_123_4229_n898, DP_OP_169J43_123_4229_n897,
DP_OP_169J43_123_4229_n896, DP_OP_169J43_123_4229_n895,
DP_OP_169J43_123_4229_n894, DP_OP_169J43_123_4229_n893,
DP_OP_169J43_123_4229_n892, DP_OP_169J43_123_4229_n891,
DP_OP_169J43_123_4229_n890, DP_OP_169J43_123_4229_n889,
DP_OP_169J43_123_4229_n888, DP_OP_169J43_123_4229_n887,
DP_OP_169J43_123_4229_n886, DP_OP_169J43_123_4229_n885,
DP_OP_169J43_123_4229_n884, DP_OP_169J43_123_4229_n883,
DP_OP_169J43_123_4229_n882, DP_OP_169J43_123_4229_n881,
DP_OP_169J43_123_4229_n880, DP_OP_169J43_123_4229_n879,
DP_OP_169J43_123_4229_n878, DP_OP_169J43_123_4229_n877,
DP_OP_169J43_123_4229_n876, DP_OP_169J43_123_4229_n875,
DP_OP_169J43_123_4229_n874, DP_OP_169J43_123_4229_n873,
DP_OP_169J43_123_4229_n872, DP_OP_169J43_123_4229_n871,
DP_OP_169J43_123_4229_n870, DP_OP_169J43_123_4229_n869,
DP_OP_169J43_123_4229_n868, DP_OP_169J43_123_4229_n867,
DP_OP_169J43_123_4229_n866, DP_OP_169J43_123_4229_n865,
DP_OP_169J43_123_4229_n864, DP_OP_169J43_123_4229_n863,
DP_OP_169J43_123_4229_n862, DP_OP_169J43_123_4229_n861,
DP_OP_169J43_123_4229_n860, DP_OP_169J43_123_4229_n859,
DP_OP_169J43_123_4229_n856, DP_OP_169J43_123_4229_n855,
DP_OP_169J43_123_4229_n854, DP_OP_169J43_123_4229_n853,
DP_OP_169J43_123_4229_n852, DP_OP_169J43_123_4229_n851,
DP_OP_169J43_123_4229_n850, DP_OP_169J43_123_4229_n849,
DP_OP_169J43_123_4229_n848, DP_OP_169J43_123_4229_n847,
DP_OP_169J43_123_4229_n846, DP_OP_169J43_123_4229_n845,
DP_OP_169J43_123_4229_n844, DP_OP_169J43_123_4229_n843,
DP_OP_169J43_123_4229_n842, DP_OP_169J43_123_4229_n841,
DP_OP_169J43_123_4229_n840, DP_OP_169J43_123_4229_n839,
DP_OP_169J43_123_4229_n838, DP_OP_169J43_123_4229_n837,
DP_OP_169J43_123_4229_n836, DP_OP_169J43_123_4229_n835,
DP_OP_169J43_123_4229_n834, DP_OP_169J43_123_4229_n833,
DP_OP_169J43_123_4229_n832, DP_OP_169J43_123_4229_n831,
DP_OP_169J43_123_4229_n830, DP_OP_169J43_123_4229_n829,
DP_OP_169J43_123_4229_n828, DP_OP_169J43_123_4229_n827,
DP_OP_169J43_123_4229_n826, DP_OP_169J43_123_4229_n825,
DP_OP_169J43_123_4229_n824, DP_OP_169J43_123_4229_n823,
DP_OP_169J43_123_4229_n822, DP_OP_169J43_123_4229_n821,
DP_OP_169J43_123_4229_n820, DP_OP_169J43_123_4229_n819,
DP_OP_169J43_123_4229_n818, DP_OP_169J43_123_4229_n817,
DP_OP_169J43_123_4229_n816, DP_OP_169J43_123_4229_n815,
DP_OP_169J43_123_4229_n814, DP_OP_169J43_123_4229_n813,
DP_OP_169J43_123_4229_n812, DP_OP_169J43_123_4229_n811,
DP_OP_169J43_123_4229_n810, DP_OP_169J43_123_4229_n809,
DP_OP_169J43_123_4229_n808, DP_OP_169J43_123_4229_n807,
DP_OP_169J43_123_4229_n806, DP_OP_169J43_123_4229_n805,
DP_OP_169J43_123_4229_n804, DP_OP_169J43_123_4229_n803,
DP_OP_169J43_123_4229_n800, DP_OP_169J43_123_4229_n799,
DP_OP_169J43_123_4229_n798, DP_OP_169J43_123_4229_n797,
DP_OP_169J43_123_4229_n796, DP_OP_169J43_123_4229_n795,
DP_OP_169J43_123_4229_n794, DP_OP_169J43_123_4229_n793,
DP_OP_169J43_123_4229_n792, DP_OP_169J43_123_4229_n791,
DP_OP_169J43_123_4229_n790, DP_OP_169J43_123_4229_n789,
DP_OP_169J43_123_4229_n788, DP_OP_169J43_123_4229_n787,
DP_OP_169J43_123_4229_n786, DP_OP_169J43_123_4229_n785,
DP_OP_169J43_123_4229_n784, DP_OP_169J43_123_4229_n783,
DP_OP_169J43_123_4229_n782, DP_OP_169J43_123_4229_n781,
DP_OP_169J43_123_4229_n780, DP_OP_169J43_123_4229_n779,
DP_OP_169J43_123_4229_n778, DP_OP_169J43_123_4229_n777,
DP_OP_169J43_123_4229_n776, DP_OP_169J43_123_4229_n775,
DP_OP_169J43_123_4229_n774, DP_OP_169J43_123_4229_n773,
DP_OP_169J43_123_4229_n772, DP_OP_169J43_123_4229_n771,
DP_OP_169J43_123_4229_n770, DP_OP_169J43_123_4229_n769,
DP_OP_169J43_123_4229_n768, DP_OP_169J43_123_4229_n767,
DP_OP_169J43_123_4229_n766, DP_OP_169J43_123_4229_n765,
DP_OP_169J43_123_4229_n764, DP_OP_169J43_123_4229_n763,
DP_OP_169J43_123_4229_n762, DP_OP_169J43_123_4229_n761,
DP_OP_169J43_123_4229_n760, DP_OP_169J43_123_4229_n759,
DP_OP_169J43_123_4229_n756, DP_OP_169J43_123_4229_n755,
DP_OP_169J43_123_4229_n754, DP_OP_169J43_123_4229_n753,
DP_OP_169J43_123_4229_n752, DP_OP_169J43_123_4229_n751,
DP_OP_169J43_123_4229_n750, DP_OP_169J43_123_4229_n749,
DP_OP_169J43_123_4229_n748, DP_OP_169J43_123_4229_n747,
DP_OP_169J43_123_4229_n746, DP_OP_169J43_123_4229_n745,
DP_OP_169J43_123_4229_n744, DP_OP_169J43_123_4229_n743,
DP_OP_169J43_123_4229_n742, DP_OP_169J43_123_4229_n741,
DP_OP_169J43_123_4229_n740, DP_OP_169J43_123_4229_n739,
DP_OP_169J43_123_4229_n738, DP_OP_169J43_123_4229_n737,
DP_OP_169J43_123_4229_n736, DP_OP_169J43_123_4229_n735,
DP_OP_169J43_123_4229_n734, DP_OP_169J43_123_4229_n733,
DP_OP_169J43_123_4229_n732, DP_OP_169J43_123_4229_n731,
DP_OP_169J43_123_4229_n730, DP_OP_169J43_123_4229_n729,
DP_OP_169J43_123_4229_n728, DP_OP_169J43_123_4229_n727,
DP_OP_169J43_123_4229_n724, DP_OP_169J43_123_4229_n723,
DP_OP_169J43_123_4229_n722, DP_OP_169J43_123_4229_n721,
DP_OP_169J43_123_4229_n720, DP_OP_169J43_123_4229_n719,
DP_OP_169J43_123_4229_n718, DP_OP_169J43_123_4229_n717,
DP_OP_169J43_123_4229_n716, DP_OP_169J43_123_4229_n715,
DP_OP_169J43_123_4229_n714, DP_OP_169J43_123_4229_n713,
DP_OP_169J43_123_4229_n712, DP_OP_169J43_123_4229_n711,
DP_OP_169J43_123_4229_n710, DP_OP_169J43_123_4229_n709,
DP_OP_169J43_123_4229_n708, DP_OP_169J43_123_4229_n707,
DP_OP_169J43_123_4229_n646, mult_x_24_n2066, mult_x_24_n1564,
mult_x_24_n1563, mult_x_24_n1562, mult_x_24_n1561, mult_x_24_n1560,
mult_x_24_n1558, mult_x_24_n1557, mult_x_24_n1556, mult_x_24_n1555,
mult_x_24_n1554, mult_x_24_n1553, mult_x_24_n1552, mult_x_24_n1551,
mult_x_24_n1550, mult_x_24_n1549, mult_x_24_n1548, mult_x_24_n1547,
mult_x_24_n1546, mult_x_24_n1545, mult_x_24_n1537, mult_x_24_n1536,
mult_x_24_n1535, mult_x_24_n1534, mult_x_24_n1533, mult_x_24_n1532,
mult_x_24_n1531, mult_x_24_n1530, mult_x_24_n1529, mult_x_24_n1528,
mult_x_24_n1527, mult_x_24_n1526, mult_x_24_n1525, mult_x_24_n1524,
mult_x_24_n1523, mult_x_24_n1522, mult_x_24_n1521, mult_x_24_n1520,
mult_x_24_n1519, mult_x_24_n1518, mult_x_24_n1517, mult_x_24_n1516,
mult_x_24_n1515, mult_x_24_n1510, mult_x_24_n1509, mult_x_24_n1508,
mult_x_24_n1507, mult_x_24_n1506, mult_x_24_n1505, mult_x_24_n1504,
mult_x_24_n1503, mult_x_24_n1502, mult_x_24_n1501, mult_x_24_n1500,
mult_x_24_n1498, mult_x_24_n1497, mult_x_24_n1496, mult_x_24_n1495,
mult_x_24_n1494, mult_x_24_n1493, mult_x_24_n1492, mult_x_24_n1491,
mult_x_24_n1490, mult_x_24_n1489, mult_x_24_n1488, mult_x_24_n1487,
mult_x_24_n1486, mult_x_24_n1485, mult_x_24_n1477, mult_x_24_n1476,
mult_x_24_n1475, mult_x_24_n1474, mult_x_24_n1473, mult_x_24_n1472,
mult_x_24_n1471, mult_x_24_n1470, mult_x_24_n1469, mult_x_24_n1468,
mult_x_24_n1467, mult_x_24_n1466, mult_x_24_n1465, mult_x_24_n1464,
mult_x_24_n1463, mult_x_24_n1462, mult_x_24_n1461, mult_x_24_n1460,
mult_x_24_n1459, mult_x_24_n1458, mult_x_24_n1457, mult_x_24_n1456,
mult_x_24_n1455, mult_x_24_n1450, mult_x_24_n1449, mult_x_24_n1448,
mult_x_24_n1447, mult_x_24_n1446, mult_x_24_n1445, mult_x_24_n1444,
mult_x_24_n1443, mult_x_24_n1442, mult_x_24_n1441, mult_x_24_n1440,
mult_x_24_n1438, mult_x_24_n1437, mult_x_24_n1436, mult_x_24_n1435,
mult_x_24_n1434, mult_x_24_n1433, mult_x_24_n1432, mult_x_24_n1431,
mult_x_24_n1430, mult_x_24_n1429, mult_x_24_n1428, mult_x_24_n1427,
mult_x_24_n1426, mult_x_24_n1417, mult_x_24_n1416, mult_x_24_n1415,
mult_x_24_n1414, mult_x_24_n1413, mult_x_24_n1412, mult_x_24_n1411,
mult_x_24_n1410, mult_x_24_n1409, mult_x_24_n1408, mult_x_24_n1407,
mult_x_24_n1406, mult_x_24_n1405, mult_x_24_n1404, mult_x_24_n1403,
mult_x_24_n1402, mult_x_24_n1401, mult_x_24_n1400, mult_x_24_n1399,
mult_x_24_n1398, mult_x_24_n1397, mult_x_24_n1396, mult_x_24_n1395,
mult_x_24_n1390, mult_x_24_n1389, mult_x_24_n1388, mult_x_24_n1387,
mult_x_24_n1386, mult_x_24_n1385, mult_x_24_n1384, mult_x_24_n1383,
mult_x_24_n1382, mult_x_24_n1381, mult_x_24_n1380, mult_x_24_n1379,
mult_x_24_n1378, mult_x_24_n1377, mult_x_24_n1376, mult_x_24_n1375,
mult_x_24_n1374, mult_x_24_n1373, mult_x_24_n1371, mult_x_24_n1370,
mult_x_24_n1369, mult_x_24_n1368, mult_x_24_n1367, mult_x_24_n1366,
mult_x_24_n1357, mult_x_24_n1356, mult_x_24_n1355, mult_x_24_n1354,
mult_x_24_n1353, mult_x_24_n1352, mult_x_24_n1351, mult_x_24_n1350,
mult_x_24_n1349, mult_x_24_n1348, mult_x_24_n1347, mult_x_24_n1346,
mult_x_24_n1345, mult_x_24_n1344, mult_x_24_n1343, mult_x_24_n1342,
mult_x_24_n1341, mult_x_24_n1340, mult_x_24_n1339, mult_x_24_n1338,
mult_x_24_n1337, mult_x_24_n1336, mult_x_24_n1335, mult_x_24_n1330,
mult_x_24_n1329, mult_x_24_n1328, mult_x_24_n1327, mult_x_24_n1326,
mult_x_24_n1325, mult_x_24_n1322, mult_x_24_n1321, mult_x_24_n1320,
mult_x_24_n1319, mult_x_24_n1318, mult_x_24_n1317, mult_x_24_n1316,
mult_x_24_n1315, mult_x_24_n1314, mult_x_24_n1313, mult_x_24_n1311,
mult_x_24_n1310, mult_x_24_n1309, mult_x_24_n1308, mult_x_24_n1307,
mult_x_24_n963, mult_x_24_n962, mult_x_24_n961, mult_x_24_n960,
mult_x_24_n959, mult_x_24_n958, mult_x_24_n954, mult_x_24_n953,
mult_x_24_n952, mult_x_24_n948, mult_x_24_n947, mult_x_24_n946,
mult_x_24_n942, mult_x_24_n941, mult_x_24_n940, mult_x_24_n921,
mult_x_24_n918, mult_x_24_n916, mult_x_24_n915, mult_x_24_n914,
mult_x_24_n913, mult_x_24_n911, mult_x_24_n910, mult_x_24_n909,
mult_x_24_n908, mult_x_24_n906, mult_x_24_n905, mult_x_24_n904,
mult_x_24_n901, mult_x_24_n899, mult_x_24_n898, mult_x_24_n897,
mult_x_24_n894, mult_x_24_n893, mult_x_24_n892, mult_x_24_n891,
mult_x_24_n890, mult_x_24_n888, mult_x_24_n887, mult_x_24_n886,
mult_x_24_n885, mult_x_24_n884, mult_x_24_n883, mult_x_24_n882,
mult_x_24_n880, mult_x_24_n879, mult_x_24_n878, mult_x_24_n877,
mult_x_24_n876, mult_x_24_n875, mult_x_24_n874, mult_x_24_n872,
mult_x_24_n871, mult_x_24_n870, mult_x_24_n869, mult_x_24_n868,
mult_x_24_n867, mult_x_24_n866, mult_x_24_n864, mult_x_24_n863,
mult_x_24_n862, mult_x_24_n861, mult_x_24_n860, mult_x_24_n859,
mult_x_24_n856, mult_x_24_n854, mult_x_24_n853, mult_x_24_n852,
mult_x_24_n851, mult_x_24_n850, mult_x_24_n849, mult_x_24_n846,
mult_x_24_n845, mult_x_24_n844, mult_x_24_n843, mult_x_24_n842,
mult_x_24_n841, mult_x_24_n840, mult_x_24_n839, mult_x_24_n837,
mult_x_24_n836, mult_x_24_n835, mult_x_24_n834, mult_x_24_n833,
mult_x_24_n832, mult_x_24_n831, mult_x_24_n830, mult_x_24_n829,
mult_x_24_n828, mult_x_24_n826, mult_x_24_n825, mult_x_24_n824,
mult_x_24_n823, mult_x_24_n822, mult_x_24_n821, mult_x_24_n820,
mult_x_24_n819, mult_x_24_n818, mult_x_24_n817, mult_x_24_n815,
mult_x_24_n814, mult_x_24_n813, mult_x_24_n812, mult_x_24_n811,
mult_x_24_n810, mult_x_24_n809, mult_x_24_n808, mult_x_24_n807,
mult_x_24_n806, mult_x_24_n804, mult_x_24_n803, mult_x_24_n802,
mult_x_24_n801, mult_x_24_n800, mult_x_24_n799, mult_x_24_n798,
mult_x_24_n797, mult_x_24_n796, mult_x_24_n793, mult_x_24_n791,
mult_x_24_n790, mult_x_24_n789, mult_x_24_n788, mult_x_24_n787,
mult_x_24_n786, mult_x_24_n785, mult_x_24_n784, mult_x_24_n783,
mult_x_24_n780, mult_x_24_n779, mult_x_24_n778, mult_x_24_n777,
mult_x_24_n776, mult_x_24_n775, mult_x_24_n774, mult_x_24_n773,
mult_x_24_n772, mult_x_24_n771, mult_x_24_n770, mult_x_24_n768,
mult_x_24_n767, mult_x_24_n766, mult_x_24_n765, mult_x_24_n764,
mult_x_24_n763, mult_x_24_n762, mult_x_24_n761, mult_x_24_n760,
mult_x_24_n759, mult_x_24_n758, mult_x_24_n757, mult_x_24_n756,
mult_x_24_n755, mult_x_24_n754, mult_x_24_n753, mult_x_24_n752,
mult_x_24_n751, mult_x_24_n750, mult_x_24_n749, mult_x_24_n748,
mult_x_24_n747, mult_x_24_n746, mult_x_24_n745, mult_x_24_n744,
mult_x_24_n743, mult_x_24_n742, mult_x_24_n741, mult_x_24_n740,
mult_x_24_n739, mult_x_24_n738, mult_x_24_n737, mult_x_24_n736,
mult_x_24_n735, mult_x_24_n734, mult_x_24_n733, mult_x_24_n732,
mult_x_24_n731, mult_x_24_n730, mult_x_24_n729, mult_x_24_n728,
mult_x_24_n727, mult_x_24_n726, mult_x_24_n725, mult_x_24_n724,
mult_x_24_n723, mult_x_24_n722, mult_x_24_n721, mult_x_24_n720,
mult_x_24_n719, mult_x_24_n718, mult_x_24_n717, mult_x_24_n716,
mult_x_24_n715, mult_x_24_n714, mult_x_24_n713, mult_x_24_n712,
mult_x_24_n711, mult_x_24_n710, mult_x_24_n709, mult_x_24_n708,
mult_x_24_n707, mult_x_24_n706, mult_x_24_n705, mult_x_24_n704,
mult_x_24_n703, mult_x_24_n702, mult_x_24_n701, mult_x_24_n700,
mult_x_24_n699, mult_x_24_n698, mult_x_24_n697, mult_x_24_n696,
mult_x_24_n695, mult_x_24_n694, mult_x_24_n693, mult_x_24_n692,
mult_x_24_n691, mult_x_24_n690, mult_x_24_n689, mult_x_24_n688,
mult_x_24_n687, mult_x_24_n686, mult_x_24_n685, mult_x_24_n683,
mult_x_24_n682, mult_x_24_n681, mult_x_24_n680, mult_x_24_n679,
mult_x_24_n678, mult_x_24_n677, mult_x_24_n676, mult_x_24_n675,
mult_x_24_n674, mult_x_24_n673, mult_x_24_n671, mult_x_24_n670,
mult_x_24_n669, mult_x_24_n668, mult_x_24_n667, mult_x_24_n666,
mult_x_24_n665, mult_x_24_n664, mult_x_24_n663, mult_x_24_n662,
mult_x_24_n661, mult_x_24_n660, mult_x_24_n659, mult_x_24_n658,
mult_x_24_n657, mult_x_24_n656, mult_x_24_n655, mult_x_24_n654,
mult_x_24_n653, mult_x_24_n652, mult_x_24_n651, mult_x_24_n650,
mult_x_24_n649, mult_x_24_n648, mult_x_24_n647, mult_x_24_n646,
mult_x_24_n645, mult_x_24_n644, mult_x_24_n643, mult_x_24_n642,
mult_x_24_n641, mult_x_24_n640, mult_x_24_n638, mult_x_24_n637,
mult_x_24_n636, mult_x_24_n635, mult_x_24_n634, mult_x_24_n633,
mult_x_24_n632, mult_x_24_n631, mult_x_24_n630, mult_x_24_n629,
mult_x_24_n628, mult_x_24_n627, mult_x_24_n626, mult_x_24_n625,
mult_x_24_n624, mult_x_24_n623, mult_x_24_n622, mult_x_24_n621,
mult_x_24_n619, mult_x_24_n618, mult_x_24_n617, mult_x_24_n616,
mult_x_24_n615, mult_x_24_n614, mult_x_24_n613, mult_x_24_n612,
mult_x_24_n610, mult_x_24_n609, mult_x_24_n608, mult_x_24_n607,
mult_x_24_n606, mult_x_24_n605, mult_x_24_n604, mult_x_24_n603,
mult_x_24_n602, mult_x_24_n601, mult_x_24_n600, mult_x_24_n599,
mult_x_24_n598, mult_x_24_n597, mult_x_24_n596, mult_x_24_n595,
mult_x_24_n594, mult_x_24_n593, mult_x_24_n592, mult_x_24_n591,
mult_x_24_n590, mult_x_24_n589, mult_x_24_n588, mult_x_24_n586,
mult_x_24_n585, mult_x_24_n584, mult_x_24_n583, mult_x_24_n582,
mult_x_24_n581, mult_x_24_n580, mult_x_24_n579, mult_x_24_n578,
mult_x_24_n577, mult_x_24_n576, mult_x_24_n575, mult_x_24_n573,
mult_x_24_n572, mult_x_24_n571, mult_x_24_n570, mult_x_24_n569,
mult_x_24_n567, mult_x_24_n566, mult_x_24_n565, mult_x_24_n564,
mult_x_24_n563, mult_x_24_n562, mult_x_24_n561, mult_x_24_n560,
mult_x_24_n559, mult_x_24_n558, mult_x_24_n557, mult_x_24_n556,
mult_x_24_n555, mult_x_24_n554, mult_x_24_n552, mult_x_24_n551,
mult_x_24_n550, mult_x_24_n549, mult_x_24_n548, mult_x_24_n547,
mult_x_23_n1930, mult_x_23_n1359, mult_x_23_n1358, mult_x_23_n1357,
mult_x_23_n1356, mult_x_23_n1355, mult_x_23_n1354, mult_x_23_n1353,
mult_x_23_n1352, mult_x_23_n1351, mult_x_23_n1350, mult_x_23_n1349,
mult_x_23_n1348, mult_x_23_n1347, mult_x_23_n1346, mult_x_23_n1345,
mult_x_23_n1344, mult_x_23_n1343, mult_x_23_n1342, mult_x_23_n1341,
mult_x_23_n1333, mult_x_23_n1332, mult_x_23_n1331, mult_x_23_n1330,
mult_x_23_n1329, mult_x_23_n1328, mult_x_23_n1327, mult_x_23_n1326,
mult_x_23_n1325, mult_x_23_n1324, mult_x_23_n1323, mult_x_23_n1322,
mult_x_23_n1321, mult_x_23_n1320, mult_x_23_n1319, mult_x_23_n1318,
mult_x_23_n1317, mult_x_23_n1316, mult_x_23_n1315, mult_x_23_n1314,
mult_x_23_n1313, mult_x_23_n1312, mult_x_23_n1307, mult_x_23_n1306,
mult_x_23_n1305, mult_x_23_n1304, mult_x_23_n1303, mult_x_23_n1301,
mult_x_23_n1300, mult_x_23_n1299, mult_x_23_n1298, mult_x_23_n1297,
mult_x_23_n1296, mult_x_23_n1295, mult_x_23_n1294, mult_x_23_n1293,
mult_x_23_n1292, mult_x_23_n1291, mult_x_23_n1290, mult_x_23_n1289,
mult_x_23_n1288, mult_x_23_n1287, mult_x_23_n1286, mult_x_23_n1285,
mult_x_23_n1284, mult_x_23_n1283, mult_x_23_n1275, mult_x_23_n1274,
mult_x_23_n1273, mult_x_23_n1272, mult_x_23_n1271, mult_x_23_n1270,
mult_x_23_n1269, mult_x_23_n1268, mult_x_23_n1267, mult_x_23_n1266,
mult_x_23_n1265, mult_x_23_n1264, mult_x_23_n1263, mult_x_23_n1262,
mult_x_23_n1261, mult_x_23_n1260, mult_x_23_n1259, mult_x_23_n1258,
mult_x_23_n1257, mult_x_23_n1256, mult_x_23_n1255, mult_x_23_n1249,
mult_x_23_n1248, mult_x_23_n1247, mult_x_23_n1246, mult_x_23_n1245,
mult_x_23_n1243, mult_x_23_n1242, mult_x_23_n1241, mult_x_23_n1240,
mult_x_23_n1239, mult_x_23_n1238, mult_x_23_n1237, mult_x_23_n1236,
mult_x_23_n1235, mult_x_23_n1234, mult_x_23_n1233, mult_x_23_n1232,
mult_x_23_n1231, mult_x_23_n1230, mult_x_23_n1229, mult_x_23_n1228,
mult_x_23_n1227, mult_x_23_n1226, mult_x_23_n1225, mult_x_23_n1217,
mult_x_23_n1216, mult_x_23_n1215, mult_x_23_n1214, mult_x_23_n1213,
mult_x_23_n1212, mult_x_23_n1211, mult_x_23_n1210, mult_x_23_n1209,
mult_x_23_n1208, mult_x_23_n1207, mult_x_23_n1206, mult_x_23_n1205,
mult_x_23_n1204, mult_x_23_n1203, mult_x_23_n1202, mult_x_23_n1201,
mult_x_23_n1200, mult_x_23_n1199, mult_x_23_n1198, mult_x_23_n1191,
mult_x_23_n1190, mult_x_23_n1189, mult_x_23_n1188, mult_x_23_n1187,
mult_x_23_n1183, mult_x_23_n1182, mult_x_23_n1181, mult_x_23_n1180,
mult_x_23_n1179, mult_x_23_n1178, mult_x_23_n1177, mult_x_23_n1176,
mult_x_23_n1175, mult_x_23_n1174, mult_x_23_n1173, mult_x_23_n1172,
mult_x_23_n1171, mult_x_23_n1170, mult_x_23_n1169, mult_x_23_n1168,
mult_x_23_n1167, mult_x_23_n1158, mult_x_23_n1155, mult_x_23_n1154,
mult_x_23_n1153, mult_x_23_n1152, mult_x_23_n1150, mult_x_23_n1148,
mult_x_23_n1147, mult_x_23_n1146, mult_x_23_n1145, mult_x_23_n1144,
mult_x_23_n1142, mult_x_23_n1141, mult_x_23_n1140, mult_x_23_n1129,
mult_x_23_n1128, mult_x_23_n1126, mult_x_23_n1125, mult_x_23_n1124,
mult_x_23_n1122, mult_x_23_n1121, mult_x_23_n1120, mult_x_23_n836,
mult_x_23_n833, mult_x_23_n831, mult_x_23_n830, mult_x_23_n829,
mult_x_23_n828, mult_x_23_n826, mult_x_23_n825, mult_x_23_n824,
mult_x_23_n823, mult_x_23_n821, mult_x_23_n820, mult_x_23_n819,
mult_x_23_n816, mult_x_23_n814, mult_x_23_n813, mult_x_23_n812,
mult_x_23_n809, mult_x_23_n808, mult_x_23_n807, mult_x_23_n806,
mult_x_23_n805, mult_x_23_n803, mult_x_23_n802, mult_x_23_n801,
mult_x_23_n800, mult_x_23_n799, mult_x_23_n798, mult_x_23_n797,
mult_x_23_n795, mult_x_23_n794, mult_x_23_n793, mult_x_23_n792,
mult_x_23_n791, mult_x_23_n790, mult_x_23_n789, mult_x_23_n787,
mult_x_23_n786, mult_x_23_n785, mult_x_23_n784, mult_x_23_n783,
mult_x_23_n782, mult_x_23_n781, mult_x_23_n779, mult_x_23_n778,
mult_x_23_n777, mult_x_23_n776, mult_x_23_n775, mult_x_23_n774,
mult_x_23_n771, mult_x_23_n769, mult_x_23_n768, mult_x_23_n767,
mult_x_23_n766, mult_x_23_n765, mult_x_23_n764, mult_x_23_n761,
mult_x_23_n760, mult_x_23_n759, mult_x_23_n758, mult_x_23_n757,
mult_x_23_n756, mult_x_23_n755, mult_x_23_n754, mult_x_23_n752,
mult_x_23_n751, mult_x_23_n750, mult_x_23_n749, mult_x_23_n748,
mult_x_23_n747, mult_x_23_n746, mult_x_23_n745, mult_x_23_n744,
mult_x_23_n743, mult_x_23_n741, mult_x_23_n740, mult_x_23_n739,
mult_x_23_n738, mult_x_23_n737, mult_x_23_n736, mult_x_23_n735,
mult_x_23_n734, mult_x_23_n733, mult_x_23_n732, mult_x_23_n730,
mult_x_23_n729, mult_x_23_n728, mult_x_23_n727, mult_x_23_n726,
mult_x_23_n725, mult_x_23_n724, mult_x_23_n723, mult_x_23_n722,
mult_x_23_n721, mult_x_23_n719, mult_x_23_n718, mult_x_23_n717,
mult_x_23_n716, mult_x_23_n715, mult_x_23_n714, mult_x_23_n713,
mult_x_23_n712, mult_x_23_n711, mult_x_23_n710, mult_x_23_n708,
mult_x_23_n707, mult_x_23_n706, mult_x_23_n705, mult_x_23_n704,
mult_x_23_n703, mult_x_23_n702, mult_x_23_n701, mult_x_23_n700,
mult_x_23_n699, mult_x_23_n698, mult_x_23_n697, mult_x_23_n696,
mult_x_23_n695, mult_x_23_n694, mult_x_23_n693, mult_x_23_n692,
mult_x_23_n691, mult_x_23_n690, mult_x_23_n689, mult_x_23_n688,
mult_x_23_n687, mult_x_23_n686, mult_x_23_n685, mult_x_23_n684,
mult_x_23_n683, mult_x_23_n682, mult_x_23_n681, mult_x_23_n680,
mult_x_23_n679, mult_x_23_n678, mult_x_23_n677, mult_x_23_n676,
mult_x_23_n675, mult_x_23_n674, mult_x_23_n673, mult_x_23_n672,
mult_x_23_n671, mult_x_23_n670, mult_x_23_n669, mult_x_23_n668,
mult_x_23_n667, mult_x_23_n666, mult_x_23_n665, mult_x_23_n664,
mult_x_23_n663, mult_x_23_n662, mult_x_23_n661, mult_x_23_n660,
mult_x_23_n659, mult_x_23_n658, mult_x_23_n657, mult_x_23_n656,
mult_x_23_n655, mult_x_23_n654, mult_x_23_n653, mult_x_23_n652,
mult_x_23_n651, mult_x_23_n650, mult_x_23_n649, mult_x_23_n648,
mult_x_23_n647, mult_x_23_n646, mult_x_23_n645, mult_x_23_n644,
mult_x_23_n643, mult_x_23_n642, mult_x_23_n641, mult_x_23_n640,
mult_x_23_n639, mult_x_23_n638, mult_x_23_n637, mult_x_23_n636,
mult_x_23_n635, mult_x_23_n634, mult_x_23_n633, mult_x_23_n632,
mult_x_23_n631, mult_x_23_n630, mult_x_23_n629, mult_x_23_n628,
mult_x_23_n627, mult_x_23_n626, mult_x_23_n625, mult_x_23_n624,
mult_x_23_n623, mult_x_23_n622, mult_x_23_n621, mult_x_23_n620,
mult_x_23_n619, mult_x_23_n618, mult_x_23_n617, mult_x_23_n616,
mult_x_23_n615, mult_x_23_n614, mult_x_23_n613, mult_x_23_n611,
mult_x_23_n610, mult_x_23_n609, mult_x_23_n608, mult_x_23_n607,
mult_x_23_n606, mult_x_23_n605, mult_x_23_n604, mult_x_23_n603,
mult_x_23_n602, mult_x_23_n601, mult_x_23_n600, mult_x_23_n599,
mult_x_23_n598, mult_x_23_n597, mult_x_23_n596, mult_x_23_n595,
mult_x_23_n594, mult_x_23_n592, mult_x_23_n591, mult_x_23_n590,
mult_x_23_n589, mult_x_23_n588, mult_x_23_n587, mult_x_23_n586,
mult_x_23_n585, mult_x_23_n584, mult_x_23_n581, mult_x_23_n580,
mult_x_23_n579, mult_x_23_n578, mult_x_23_n577, mult_x_23_n576,
mult_x_23_n575, mult_x_23_n574, mult_x_23_n573, mult_x_23_n572,
mult_x_23_n571, mult_x_23_n570, mult_x_23_n569, mult_x_23_n568,
mult_x_23_n567, mult_x_23_n566, mult_x_23_n565, mult_x_23_n564,
mult_x_23_n563, mult_x_23_n562, mult_x_23_n561, mult_x_23_n560,
mult_x_23_n559, mult_x_23_n557, mult_x_23_n556, mult_x_23_n555,
mult_x_23_n554, mult_x_23_n553, mult_x_23_n552, mult_x_23_n551,
mult_x_23_n550, mult_x_23_n549, mult_x_23_n548, mult_x_23_n547,
mult_x_23_n546, mult_x_23_n544, mult_x_23_n543, mult_x_23_n542,
mult_x_23_n541, mult_x_23_n540, mult_x_23_n539, mult_x_23_n536,
mult_x_23_n535, mult_x_23_n534, mult_x_23_n533, mult_x_23_n532,
mult_x_23_n531, mult_x_23_n530, mult_x_23_n529, mult_x_23_n528,
mult_x_23_n527, mult_x_23_n526, mult_x_23_n525, mult_x_23_n524,
mult_x_23_n523, mult_x_23_n521, mult_x_23_n520, mult_x_23_n519,
mult_x_23_n518, mult_x_23_n517, mult_x_23_n516, mult_x_23_n515,
DP_OP_168J43_122_1342_n499, DP_OP_168J43_122_1342_n498,
DP_OP_168J43_122_1342_n497, DP_OP_168J43_122_1342_n496,
DP_OP_168J43_122_1342_n495, DP_OP_168J43_122_1342_n494,
DP_OP_168J43_122_1342_n493, DP_OP_168J43_122_1342_n492,
DP_OP_168J43_122_1342_n491, DP_OP_168J43_122_1342_n490,
DP_OP_168J43_122_1342_n489, DP_OP_168J43_122_1342_n488,
DP_OP_168J43_122_1342_n487, DP_OP_168J43_122_1342_n486,
DP_OP_168J43_122_1342_n485, DP_OP_168J43_122_1342_n484,
DP_OP_168J43_122_1342_n483, DP_OP_168J43_122_1342_n482,
DP_OP_168J43_122_1342_n481, DP_OP_168J43_122_1342_n480,
DP_OP_168J43_122_1342_n479, DP_OP_168J43_122_1342_n478,
DP_OP_168J43_122_1342_n477, DP_OP_168J43_122_1342_n476,
DP_OP_168J43_122_1342_n475, DP_OP_168J43_122_1342_n474,
DP_OP_168J43_122_1342_n473, DP_OP_168J43_122_1342_n472,
DP_OP_168J43_122_1342_n471, DP_OP_168J43_122_1342_n470,
DP_OP_168J43_122_1342_n469, DP_OP_168J43_122_1342_n468,
DP_OP_168J43_122_1342_n467, DP_OP_168J43_122_1342_n466,
DP_OP_168J43_122_1342_n465, DP_OP_168J43_122_1342_n464,
DP_OP_168J43_122_1342_n463, DP_OP_168J43_122_1342_n462,
DP_OP_168J43_122_1342_n461, DP_OP_168J43_122_1342_n460,
DP_OP_168J43_122_1342_n459, DP_OP_168J43_122_1342_n458,
DP_OP_168J43_122_1342_n457, DP_OP_168J43_122_1342_n456,
DP_OP_168J43_122_1342_n455, DP_OP_168J43_122_1342_n454,
DP_OP_168J43_122_1342_n447, DP_OP_168J43_122_1342_n446,
DP_OP_168J43_122_1342_n445, DP_OP_168J43_122_1342_n444,
DP_OP_168J43_122_1342_n443, DP_OP_168J43_122_1342_n442,
DP_OP_168J43_122_1342_n441, DP_OP_168J43_122_1342_n440,
DP_OP_168J43_122_1342_n439, DP_OP_168J43_122_1342_n438,
DP_OP_168J43_122_1342_n437, DP_OP_168J43_122_1342_n436,
DP_OP_168J43_122_1342_n435, DP_OP_168J43_122_1342_n434,
DP_OP_168J43_122_1342_n433, DP_OP_168J43_122_1342_n432,
DP_OP_168J43_122_1342_n431, DP_OP_168J43_122_1342_n430,
DP_OP_168J43_122_1342_n429, DP_OP_168J43_122_1342_n428,
DP_OP_168J43_122_1342_n427, DP_OP_168J43_122_1342_n426,
DP_OP_168J43_122_1342_n425, DP_OP_168J43_122_1342_n424,
DP_OP_168J43_122_1342_n423, DP_OP_168J43_122_1342_n422,
DP_OP_168J43_122_1342_n421, DP_OP_168J43_122_1342_n420,
DP_OP_168J43_122_1342_n419, DP_OP_168J43_122_1342_n418,
DP_OP_168J43_122_1342_n417, DP_OP_168J43_122_1342_n416,
DP_OP_168J43_122_1342_n415, DP_OP_168J43_122_1342_n414,
DP_OP_168J43_122_1342_n413, DP_OP_168J43_122_1342_n412,
DP_OP_168J43_122_1342_n411, DP_OP_168J43_122_1342_n410,
DP_OP_168J43_122_1342_n407, DP_OP_168J43_122_1342_n406,
DP_OP_168J43_122_1342_n405, DP_OP_168J43_122_1342_n404,
DP_OP_168J43_122_1342_n403, DP_OP_168J43_122_1342_n402,
DP_OP_168J43_122_1342_n401, n729, n730, n731, n732, n733, n734, n735,
n736, n737, n738, n739, n740, n741, n742, n743, n744, n745, n746,
n747, n748, n749, n750, n751, n752, n753, n754, n755, n756, n757,
n758, n759, n760, n761, n762, n763, n764, n765, n766, n767, n768,
n769, n770, n771, n772, n773, n774, n775, n776, n777, n778, n779,
n780, n781, n782, n783, n784, n785, n786, n788, n789, n790, n791,
n792, n793, n794, n795, n796, n797, n798, n799, n800, n801, n802,
n803, n804, n805, n807, n809, n810, n811, n812, n813, n814, n815,
n816, n817, n818, n819, n820, n821, n822, n823, n824, n825, n826,
n827, n828, n829, n830, n831, n832, n833, n834, n835, n836, n837,
n838, n839, n840, n841, n842, n843, n844, n845, n846, n847, n848,
n849, n850, n851, n852, n853, n854, n855, n856, n857, n858, n859,
n860, n861, n862, n863, n864, n865, n866, n867, n868, n869, n870,
n871, n872, n873, n874, n875, n876, n877, n878, n879, n880, n881,
n882, n883, n884, n885, n886, n887, n888, n889, n890, n891, n892,
n893, n894, n895, n896, n897, n898, n899, n900, n901, n902, n903,
n904, n905, n906, n907, n908, n909, n910, n911, n912, n913, n914,
n915, n916, n917, n918, n919, n920, n921, n922, n923, n924, n925,
n926, n927, n928, n929, n930, n931, n932, n933, n934, n935, n936,
n937, n938, n939, n940, n941, n942, n943, n944, n945, n946, n947,
n948, n949, n950, n951, n952, n953, n954, n955, n956, n957, n958,
n959, n960, n961, n962, n963, n964, n965, n966, n967, n968, n969,
n970, n971, n972, n973, n974, n975, n976, n977, n978, n979, n980,
n981, n982, n983, n984, n985, n986, n987, n988, n989, n990, n991,
n992, n993, n994, n995, n996, n997, n998, n999, n1000, n1001, n1002,
n1003, n1004, n1005, n1006, n1007, n1008, n1009, n1010, n1011, n1012,
n1013, n1014, n1015, n1016, n1017, n1018, n1019, n1020, n1021, n1022,
n1023, n1024, n1025, n1026, n1027, n1028, n1029, n1030, n1031, n1032,
n1033, n1034, n1035, n1036, n1037, n1038, n1039, n1040, n1041, n1042,
n1043, n1044, n1045, n1046, n1047, n1048, n1049, n1050, n1051, n1052,
n1053, n1054, n1055, n1056, n1057, n1058, n1059, n1060, n1061, n1062,
n1063, n1064, n1065, n1066, n1067, n1068, n1069, n1070, n1071, n1072,
n1073, n1074, n1075, n1076, n1077, n1078, n1079, n1080, n1081, n1082,
n1083, n1084, n1085, n1086, n1087, n1088, n1089, n1090, n1091, n1092,
n1093, n1094, n1095, n1096, n1097, n1098, n1099, n1100, n1101, n1102,
n1103, n1104, n1105, n1106, n1107, n1108, n1109, n1110, n1111, n1112,
n1113, n1114, n1115, n1116, n1117, n1118, n1119, n1120, n1121, n1122,
n1123, n1124, n1125, n1126, n1127, n1128, n1129, n1130, n1131, n1132,
n1133, n1134, n1135, n1136, n1137, n1138, n1139, n1140, n1141, n1142,
n1143, n1144, n1145, n1146, n1147, n1148, n1149, n1150, n1151, n1152,
n1153, n1154, n1155, n1156, n1157, n1158, n1159, n1160, n1161, n1162,
n1163, n1164, n1165, n1166, n1167, n1168, n1169, n1170, n1171, n1172,
n1173, n1174, n1175, n1176, n1177, n1178, n1179, n1180, n1181, n1182,
n1183, n1184, n1185, n1186, n1187, n1188, n1189, n1190, n1191, n1192,
n1193, n1194, n1195, n1196, n1197, n1198, n1199, n1200, n1201, n1202,
n1203, n1204, n1205, n1206, n1207, n1208, n1209, n1210, n1211, n1212,
n1213, n1214, n1215, n1216, n1217, n1218, n1219, n1220, n1221, n1222,
n1223, n1224, n1225, n1226, n1227, n1228, n1229, n1230, n1231, n1232,
n1233, n1234, n1235, n1236, n1237, n1238, n1239, n1240, n1241, n1242,
n1243, n1244, n1245, n1246, n1247, n1248, n1249, n1250, n1251, n1252,
n1253, n1254, n1255, n1256, n1257, n1258, n1259, n1260, n1261, n1262,
n1263, n1264, n1265, n1266, n1267, n1268, n1269, n1270, n1271, n1272,
n1273, n1274, n1275, n1276, n1277, n1278, n1279, n1280, n1281, n1282,
n1283, n1284, n1285, n1286, n1287, n1288, n1289, n1290, n1291, n1292,
n1293, n1294, n1295, n1296, n1297, n1298, n1299, n1300, n1301, n1302,
n1303, n1304, n1305, n1306, n1307, n1308, n1309, n1310, n1311, n1312,
n1313, n1314, n1315, n1316, n1317, n1318, n1319, n1320, n1321, n1322,
n1323, n1324, n1325, n1326, n1327, n1328, n1329, n1330, n1331, n1332,
n1333, n1334, n1335, n1336, n1337, n1338, n1339, n1340, n1341, n1342,
n1343, n1344, n1345, n1346, n1347, n1348, n1349, n1350, n1351, n1352,
n1353, n1354, n1355, n1356, n1357, n1358, n1359, n1360, n1361, n1362,
n1363, n1364, n1365, n1366, n1367, n1368, n1369, n1370, n1371, n1372,
n1373, n1374, n1375, n1376, n1377, n1378, n1379, n1380, n1381, n1382,
n1383, n1384, n1385, n1386, n1387, n1388, n1389, n1390, n1391, n1392,
n1393, n1394, n1395, n1396, n1397, n1398, n1399, n1400, n1401, n1402,
n1403, n1404, n1405, n1406, n1407, n1408, n1409, n1410, n1411, n1412,
n1413, n1414, n1415, n1416, n1417, n1418, n1419, n1420, n1421, n1422,
n1423, n1424, n1425, n1426, n1427, n1428, n1429, n1430, n1431, n1432,
n1433, n1434, n1435, n1436, n1437, n1438, n1439, n1440, n1441, n1442,
n1443, n1444, n1445, n1446, n1447, n1448, n1449, n1450, n1451, n1452,
n1453, n1454, n1455, n1456, n1457, n1458, n1459, n1460, n1461, n1462,
n1463, n1464, n1465, n1466, n1467, n1468, n1469, n1470, n1471, n1472,
n1473, n1474, n1475, n1476, n1477, n1478, n1479, n1480, n1481, n1482,
n1483, n1484, n1485, n1486, n1487, n1488, n1489, n1490, n1491, n1492,
n1493, n1494, n1495, n1496, n1497, n1498, n1499, n1500, n1501, n1502,
n1503, n1504, n1505, n1506, n1507, n1508, n1509, n1510, n1511, n1512,
n1513, n1514, n1515, n1516, n1517, n1518, n1519, n1520, n1521, n1522,
n1523, n1524, n1525, n1526, n1527, n1528, n1529, n1530, n1531, n1532,
n1533, n1534, n1535, n1536, n1537, n1538, n1539, n1540, n1541, n1542,
n1543, n1544, n1545, n1546, n1547, n1548, n1549, n1550, n1551, n1552,
n1553, n1554, n1555, n1556, n1557, n1558, n1559, n1560, n1561, n1562,
n1563, n1564, n1565, n1566, n1567, n1568, n1569, n1570, n1571, n1572,
n1573, n1574, n1575, n1576, n1577, n1578, n1579, n1580, n1581, n1582,
n1583, n1584, n1585, n1586, n1587, n1588, n1589, n1590, n1591, n1592,
n1593, n1594, n1595, n1596, n1597, n1598, n1599, n1600, n1601, n1602,
n1603, n1604, n1605, n1606, n1607, n1608, n1609, n1610, n1611, n1612,
n1613, n1614, n1615, n1616, n1617, n1618, n1619, n1620, n1621, n1622,
n1623, n1624, n1625, n1626, n1627, n1628, n1629, n1630, n1631, n1632,
n1633, n1634, n1635, n1636, n1637, n1638, n1639, n1640, n1641, n1642,
n1643, n1644, n1645, n1646, n1647, n1648, n1649, n1650, n1651, n1652,
n1653, n1654, n1655, n1656, n1657, n1658, n1659, n1660, n1661, n1662,
n1663, n1664, n1665, n1666, n1667, n1668, n1669, n1670, n1671, n1672,
n1673, n1674, n1675, n1676, n1677, n1678, n1679, n1680, n1681, n1682,
n1683, n1684, n1685, n1686, n1687, n1688, n1689, n1690, n1691, n1692,
n1693, n1694, n1695, n1696, n1697, n1698, n1699, n1700, n1701, n1702,
n1703, n1704, n1705, n1706, n1707, n1708, n1709, n1710, n1711, n1712,
n1713, n1714, n1715, n1716, n1717, n1718, n1719, n1720, n1721, n1722,
n1723, n1724, n1725, n1726, n1727, n1728, n1729, n1730, n1731, n1732,
n1733, n1734, n1735, n1736, n1737, n1738, n1739, n1740, n1741, n1742,
n1743, n1744, n1745, n1746, n1747, n1748, n1749, n1750, n1751, n1752,
n1753, n1754, n1755, n1756, n1757, n1758, n1759, n1760, n1761, n1762,
n1763, n1764, n1765, n1766, n1767, n1768, n1769, n1770, n1771, n1772,
n1773, n1774, n1775, n1776, n1777, n1778, n1779, n1780, n1781, n1782,
n1783, n1784, n1785, n1786, n1787, n1788, n1789, n1790, n1791, n1792,
n1793, n1794, n1795, n1796, n1797, n1798, n1799, n1800, n1801, n1802,
n1803, n1804, n1805, n1806, n1807, n1808, n1809, n1810, n1811, n1812,
n1813, n1814, n1815, n1816, n1817, n1818, n1819, n1820, n1821, n1822,
n1823, n1824, n1825, n1826, n1827, n1828, n1829, n1830, n1831, n1832,
n1833, n1834, n1835, n1836, n1837, n1838, n1839, n1840, n1841, n1842,
n1843, n1844, n1845, n1846, n1847, n1848, n1849, n1850, n1851, n1852,
n1853, n1854, n1855, n1856, n1857, n1858, n1859, n1860, n1861, n1862,
n1863, n1864, n1865, n1866, n1867, n1868, n1869, n1870, n1871, n1872,
n1873, n1874, n1875, n1876, n1877, n1878, n1879, n1880, n1881, n1882,
n1883, n1884, n1885, n1886, n1887, n1888, n1889, n1890, n1891, n1892,
n1893, n1894, n1895, n1896, n1897, n1898, n1899, n1900, n1901, n1902,
n1903, n1904, n1905, n1906, n1907, n1908, n1909, n1910, n1911, n1912,
n1913, n1914, n1915, n1916, n1917, n1918, n1919, n1920, n1921, n1922,
n1923, n1924, n1925, n1926, n1927, n1928, n1929, n1930, n1931, n1932,
n1933, n1934, n1935, n1936, n1937, n1938, n1939, n1940, n1941, n1942,
n1943, n1944, n1945, n1946, n1947, n1948, n1949, n1950, n1951, n1952,
n1953, n1954, n1955, n1956, n1957, n1958, n1959, n1960, n1961, n1962,
n1963, n1964, n1965, n1966, n1967, n1968, n1969, n1970, n1971, n1972,
n1973, n1974, n1975, n1976, n1977, n1978, n1979, n1980, n1981, n1982,
n1983, n1984, n1985, n1986, n1987, n1988, n1989, n1990, n1991, n1992,
n1993, n1994, n1995, n1996, n1997, n1998, n1999, n2000, n2001, n2002,
n2003, n2004, n2005, n2006, n2007, n2008, n2009, n2010, n2011, n2012,
n2013, n2014, n2015, n2016, n2017, n2018, n2019, n2020, n2021, n2022,
n2023, n2024, n2025, n2026, n2027, n2028, n2029, n2030, n2031, n2032,
n2033, n2034, n2035, n2036, n2037, n2038, n2039, n2040, n2041, n2042,
n2043, n2044, n2045, n2046, n2047, n2048, n2049, n2050, n2051, n2052,
n2053, n2054, n2055, n2056, n2057, n2058, n2059, n2060, n2061, n2062,
n2063, n2064, n2065, n2066, n2067, n2068, n2069, n2070, n2071, n2072,
n2073, n2074, n2075, n2076, n2077, n2078, n2079, n2080, n2081, n2082,
n2083, n2084, n2085, n2086, n2087, n2088, n2089, n2090, n2091, n2092,
n2093, n2094, n2095, n2096, n2097, n2098, n2099, n2100, n2101, n2102,
n2103, n2104, n2105, n2106, n2107, n2108, n2109, n2110, n2111, n2112,
n2113, n2114, n2115, n2116, n2117, n2118, n2119, n2120, n2121, n2122,
n2123, n2124, n2125, n2126, n2127, n2128, n2129, n2130, n2131, n2132,
n2133, n2134, n2135, n2136, n2137, n2138, n2139, n2140, n2141, n2142,
n2143, n2144, n2145, n2146, n2147, n2148, n2149, n2150, n2151, n2152,
n2153, n2154, n2155, n2156, n2157, n2158, n2159, n2160, n2161, n2162,
n2163, n2164, n2165, n2166, n2167, n2168, n2169, n2170, n2171, n2172,
n2173, n2174, n2175, n2176, n2177, n2178, n2179, n2180, n2181, n2182,
n2183, n2184, n2185, n2186, n2187, n2188, n2189, n2190, n2191, n2192,
n2193, n2194, n2195, n2196, n2197, n2198, n2199, n2200, n2201, n2202,
n2203, n2204, n2205, n2206, n2207, n2208, n2209, n2210, n2211, n2212,
n2213, n2214, n2215, n2216, n2217, n2218, n2219, n2220, n2221, n2222,
n2223, n2224, n2225, n2226, n2227, n2228, n2229, n2230, n2231, n2232,
n2233, n2234, n2235, n2236, n2237, n2238, n2239, n2240, n2241, n2242,
n2243, n2244, n2245, n2246, n2247, n2248, n2249, n2250, n2251, n2252,
n2253, n2254, n2255, n2256, n2257, n2258, n2259, n2260, n2261, n2262,
n2263, n2264, n2265, n2266, n2267, n2268, n2269, n2270, n2271, n2272,
n2273, n2274, n2275, n2276, n2277, n2278, n2279, n2280, n2281, n2282,
n2283, n2284, n2285, n2286, n2287, n2288, n2289, n2290, n2291, n2292,
n2293, n2294, n2295, n2296, n2297, n2298, n2299, n2300, n2301, n2302,
n2303, n2304, n2305, n2306, n2307, n2308, n2309, n2310, n2311, n2312,
n2313, n2314, n2315, n2316, n2317, n2318, n2319, n2320, n2321, n2322,
n2323, n2324, n2325, n2326, n2327, n2328, n2329, n2330, n2331, n2332,
n2333, n2334, n2335, n2336, n2337, n2338, n2339, n2340, n2341, n2342,
n2343, n2344, n2345, n2346, n2347, n2348, n2349, n2350, n2351, n2352,
n2353, n2354, n2355, n2356, n2357, n2358, n2359, n2360, n2361, n2362,
n2363, n2364, n2365, n2366, n2367, n2368, n2369, n2370, n2371, n2372,
n2373, n2374, n2375, n2376, n2377, n2378, n2379, n2380, n2381, n2382,
n2383, n2384, n2385, n2386, n2387, n2388, n2389, n2390, n2391, n2392,
n2393, n2394, n2395, n2396, n2397, n2398, n2399, n2400, n2401, n2402,
n2403, n2404, n2405, n2406, n2407, n2408, n2409, n2410, n2411, n2412,
n2413, n2414, n2415, n2416, n2417, n2418, n2419, n2420, n2421, n2422,
n2423, n2424, n2425, n2426, n2427, n2428, n2429, n2430, n2431, n2432,
n2433, n2434, n2435, n2436, n2437, n2438, n2439, n2440, n2441, n2442,
n2443, n2444, n2445, n2446, n2447, n2448, n2449, n2450, n2451, n2452,
n2453, n2454, n2455, n2456, n2457, n2458, n2459, n2460, n2461, n2462,
n2463, n2464, n2465, n2466, n2467, n2468, n2469, n2470, n2471, n2472,
n2473, n2474, n2475, n2476, n2477, n2478, n2479, n2480, n2481, n2482,
n2483, n2484, n2485, n2486, n2487, n2488, n2489, n2490, n2491, n2492,
n2493, n2494, n2495, n2496, n2497, n2498, n2499, n2500, n2501, n2502,
n2503, n2504, n2505, n2506, n2507, n2508, n2509, n2510, n2511, n2512,
n2513, n2514, n2515, n2516, n2517, n2518, n2519, n2520, n2521, n2522,
n2523, n2524, n2525, n2526, n2527, n2528, n2529, n2530, n2531, n2532,
n2533, n2534, n2535, n2536, n2537, n2538, n2539, n2540, n2541, n2542,
n2543, n2544, n2545, n2546, n2547, n2548, n2549, n2550, n2551, n2552,
n2553, n2554, n2555, n2556, n2557, n2558, n2559, n2560, n2561, n2562,
n2563, n2564, n2565, n2566, n2567, n2568, n2569, n2570, n2571, n2572,
n2573, n2574, n2575, n2576, n2577, n2578, n2579, n2580, n2581, n2582,
n2583, n2584, n2585, n2586, n2587, n2588, n2589, n2590, n2591, n2592,
n2593, n2594, n2595, n2596, n2597, n2598, n2599, n2600, n2601, n2602,
n2603, n2604, n2605, n2606, n2607, n2608, n2609, n2610, n2611, n2612,
n2613, n2614, n2615, n2616, n2617, n2618, n2619, n2620, n2621, n2622,
n2623, n2624, n2625, n2626, n2627, n2628, n2629, n2630, n2631, n2632,
n2633, n2634, n2635, n2636, n2637, n2638, n2639, n2640, n2641, n2642,
n2643, n2644, n2645, n2646, n2647, n2648, n2649, n2650, n2651, n2652,
n2653, n2654, n2655, n2656, n2657, n2658, n2659, n2660, n2661, n2662,
n2663, n2664, n2665, n2666, n2667, n2668, n2669, n2670, n2671, n2672,
n2673, n2674, n2675, n2676, n2677, n2678, n2679, n2680, n2681, n2682,
n2683, n2684, n2685, n2686, n2687, n2688, n2689, n2690, n2691, n2692,
n2693, n2694, n2695, n2696, n2697, n2698, n2699, n2700, n2701, n2702,
n2703, n2704, n2705, n2706, n2707, n2708, n2709, n2710, n2711, n2712,
n2713, n2714, n2715, n2716, n2717, n2718, n2719, n2720, n2721, n2722,
n2723, n2724, n2725, n2726, n2727, n2728, n2729, n2730, n2731, n2732,
n2733, n2734, n2735, n2736, n2737, n2738, n2739, n2740, n2741, n2742,
n2743, n2744, n2745, n2746, n2747, n2748, n2749, n2750, n2751, n2752,
n2753, n2754, n2755, n2756, n2757, n2758, n2759, n2760, n2761, n2762,
n2763, n2764, n2765, n2766, n2767, n2768, n2769, n2770, n2771, n2772,
n2773, n2774, n2775, n2776, n2777, n2778, n2779, n2780, n2781, n2782,
n2783, n2784, n2785, n2786, n2787, n2788, n2789, n2790, n2791, n2792,
n2793, n2794, n2795, n2796, n2797, n2798, n2799, n2800, n2801, n2802,
n2803, n2804, n2805, n2806, n2807, n2808, n2809, n2810, n2811, n2812,
n2813, n2814, n2815, n2816, n2817, n2818, n2819, n2820, n2821, n2822,
n2823, n2824, n2825, n2826, n2827, n2828, n2829, n2830, n2831, n2832,
n2833, n2834, n2835, n2836, n2837, n2838, n2839, n2840, n2841, n2842,
n2843, n2844, n2845, n2846, n2847, n2848, n2849, n2850, n2851, n2852,
n2853, n2854, n2855, n2856, n2857, n2858, n2859, n2860, n2861, n2862,
n2863, n2864, n2865, n2866, n2867, n2868, n2869, n2870, n2871, n2872,
n2873, n2874, n2875, n2876, n2877, n2878, n2879, n2880, n2881, n2882,
n2883, n2884, n2885, n2886, n2887, n2888, n2889, n2890, n2891, n2892,
n2893, n2894, n2895, n2896, n2897, n2898, n2899, n2900, n2901, n2902,
n2903, n2904, n2905, n2906, n2907, n2908, n2909, n2910, n2911, n2912,
n2913, n2914, n2915, n2916, n2917, n2918, n2919, n2920, n2921, n2922,
n2923, n2924, n2925, n2926, n2927, n2928, n2929, n2930, n2931, n2932,
n2933, n2934, n2935, n2936, n2937, n2938, n2939, n2940, n2941, n2942,
n2943, n2944, n2945, n2946, n2947, n2948, n2950, n2951, n2952, n2953,
n2954, n2955, n2956, n2957, n2958, n2959, n2960, n2961, n2962, n2963,
n2964, n2965, n2966, n2967, n2968, n2969, n2970, n2971, n2972, n2973,
n2974, n2975, n2976, n2977, n2978, n2979, n2980, n2981, n2982, n2983,
n2984, n2985, n2986, n2987, n2988, n2989, n2990, n2991, n2992, n2993,
n2994, n2995, n2996, n2997, n2998, n2999, n3000, n3001, n3002, n3003,
n3004, n3005, n3006, n3007, n3008, n3009, n3010, n3011, n3012, n3013,
n3014, n3015, n3016, n3017, n3018, n3019, n3020, n3021, n3022, n3023,
n3024, n3025, n3026, n3027, n3028, n3029, n3030, n3031, n3032, n3033,
n3034, n3035, n3036, n3037, n3038, n3039, n3040, n3041, n3042, n3043,
n3044, n3045, n3046, n3047, n3048, n3049, n3050, n3051, n3052, n3053,
n3054, n3055, n3056, n3057, n3058, n3059, n3060, n3061, n3062, n3063,
n3064, n3065, n3066, n3067, n3068, n3069, n3070, n3071, n3072, n3073,
n3074, n3075, n3076, n3077, n3078, n3079, n3080, n3081, n3082, n3083,
n3084, n3085, n3086, n3087, n3088, n3089, n3090, n3091, n3092, n3093,
n3094, n3095, n3096, n3097, n3098, n3099, n3100, n3101, n3102, n3103,
n3104, n3105, n3106, n3107, n3108, n3109, n3110, n3111, n3112, n3113,
n3114, n3115, n3116, n3117, n3118, n3119, n3120, n3121, n3122, n3123,
n3124, n3125, n3126, n3127, n3128, n3129, n3130, n3131, n3132, n3133,
n3134, n3135, n3136, n3137, n3138, n3139, n3140, n3141, n3142, n3143,
n3144, n3145, n3146, n3147, n3148, n3149, n3150, n3151, n3152, n3153,
n3154, n3155, n3156, n3157, n3158, n3159, n3160, n3161, n3162, n3163,
n3164, n3165, n3166, n3167, n3168, n3169, n3170, n3171, n3172, n3173,
n3174, n3175, n3176, n3177, n3178, n3179, n3180, n3181, n3182, n3183,
n3184, n3185, n3186, n3187, n3188, n3189, n3190, n3191, n3192, n3193,
n3194, n3195, n3196, n3197, n3198, n3199, n3200, n3201, n3202, n3203,
n3204, n3205, n3206, n3207, n3208, n3209, n3210, n3211, n3212, n3213,
n3214, n3215, n3216, n3217, n3218, n3219, n3220, n3221, n3222, n3223,
n3224, n3225, n3226, n3227, n3228, n3229, n3230, n3231, n3232, n3233,
n3234, n3235, n3236, n3237, n3238, n3239, n3240, n3241, n3242, n3243,
n3244, n3245, n3246, n3247, n3248, n3249, n3250, n3251, n3252, n3253,
n3254, n3255, n3256, n3257, n3258, n3259, n3260, n3261, n3262, n3263,
n3264, n3265, n3266, n3267, n3268, n3269, n3270, n3271, n3272, n3273,
n3274, n3275, n3276, n3277, n3278, n3279, n3280, n3281, n3282, n3283,
n3284, n3285, n3286, n3287, n3288, n3289, n3290, n3291, n3292, n3293,
n3294, n3295, n3296, n3297, n3298, n3299, n3300, n3301, n3302, n3303,
n3304, n3305, n3306, n3307, n3308, n3309, n3310, n3311, n3312, n3313,
n3314, n3315, n3316, n3317, n3319, n3320, n3321, n3322, n3323, n3324,
n3325, n3326, n3327, n3328, n3329, n3330, n3331, n3332, n3333, n3334,
n3335, n3336, n3337, n3338, n3339, n3340, n3341, n3342, n3343, n3344,
n3345, n3346, n3347, n3348, n3349, n3350, n3351, n3352, n3353, n3354,
n3355, n3356, n3357, n3358, n3359, n3360, n3361, n3362, n3363, n3364,
n3365, n3366, n3367, n3368, n3369, n3370, n3371, n3372, n3373, n3374,
n3375, n3376, n3377, n3378, n3379, n3380, n3381, n3382, n3383, n3384,
n3385, n3386, n3387, n3388, n3389, n3390, n3391, n3392, n3393, n3394,
n3395, n3396, n3397, n3398, n3399, n3400, n3401, n3402, n3403, n3404,
n3405, n3406, n3407, n3408, n3409, n3410, n3411, n3412, n3413, n3414,
n3415, n3416, n3417, n3418, n3419, n3420, n3421, n3422, n3423, n3424,
n3425, n3426, n3427, n3428, n3429, n3430, n3431, n3432, n3433, n3434,
n3435, n3436, n3437, n3438, n3439, n3440, n3441, n3442, n3443, n3444,
n3445, n3446, n3447, n3448, n3449, n3450, n3451, n3452, n3453, n3454,
n3455, n3456, n3457, n3458, n3459, n3460, n3461, n3462, n3463, n3464,
n3465, n3466, n3467, n3468, n3469, n3470, n3471, n3472, n3473, n3474,
n3475, n3476, n3477, n3478, n3479, n3480, n3481, n3482, n3483, n3484,
n3485, n3486, n3487, n3488, n3489, n3490, n3491, n3492, n3493, n3494,
n3495, n3496, n3497, n3498, n3499, n3500, n3501, n3502, n3503, n3504,
n3505, n3506, n3507, n3508, n3509, n3510, n3511, n3512, n3513, n3514,
n3515, n3516, n3517, n3518, n3519, n3520, n3521, n3522, n3523, n3524,
n3525, n3526, n3527, n3528, n3529, n3530, n3531, n3532, n3533, n3534,
n3535, n3536, n3537, n3538, n3539, n3540, n3541, n3542, n3543, n3544,
n3545, n3546, n3547, n3548, n3549, n3550, n3551, n3552, n3553, n3554,
n3555, n3556, n3557, n3558, n3559, n3560, n3561, n3562, n3563, n3564,
n3565, n3566, n3567, n3568, n3569, n3570, n3571, n3572, n3573, n3574,
n3575, n3576, n3577, n3578, n3579, n3580, n3581, n3582, n3583, n3584,
n3585, n3586, n3587, n3588, n3589, n3590, n3591, n3592, n3593, n3594,
n3595, n3596, n3597, n3598, n3599, n3600, n3601, n3602, n3603, n3604,
n3605, n3606, n3607, n3608, n3609, n3610, n3611, n3612, n3613, n3614,
n3615, n3616, n3617, n3618, n3619, n3620, n3621, n3622, n3623, n3624,
n3625, n3626, n3627, n3628, n3629, n3630, n3631, n3632, n3633, n3634,
n3635, n3636, n3637, n3638, n3639, n3640, n3641, n3642, n3643, n3644,
n3645, n3646, n3647, n3648, n3649, n3650, n3651, n3652, n3653, n3654,
n3655, n3656, n3657, n3658, n3659, n3660, n3661, n3662, n3663, n3664,
n3665, n3666, n3667, n3668, n3669, n3670, n3671, n3672, n3673, n3674,
n3675, n3676, n3677, n3678, n3679, n3680, n3681, n3682, n3683, n3684,
n3685, n3686, n3687, n3688, n3689, n3690, n3691, n3692, n3693, n3694,
n3695, n3696, n3697, n3698, n3699, n3700, n3701, n3702, n3703, n3704,
n3705, n3706, n3707, n3708, n3709, n3710, n3711, n3712, n3713, n3714,
n3715, n3716, n3717, n3718, n3719, n3720, n3721, n3722, n3723, n3724,
n3725, n3726, n3727, n3728, n3729, n3730, n3731, n3732, n3733, n3734,
n3735, n3736, n3737, n3738, n3739, n3740, n3741, n3742, n3743, n3744,
n3745, n3746, n3747, n3748, n3749, n3750, n3751, n3752, n3753, n3754,
n3755, n3756, n3757, n3758, n3759, n3760, n3761, n3762, n3763, n3764,
n3765, n3766, n3767, n3768, n3769, n3770, n3771, n3772, n3773, n3774,
n3775, n3776, n3777, n3778, n3779, n3780, n3781, n3782, n3783, n3784,
n3785, n3786, n3787, n3788, n3789, n3790, n3791, n3792, n3793, n3794,
n3795, n3796, n3797, n3798, n3799, n3800, n3801, n3802, n3803, n3804,
n3805, n3806, n3807, n3809, n3810, n3811, n3812, n3813, n3814, n3815,
n3816, n3817, n3818, n3819, n3820, n3821, n3822, n3823, n3824, n3825,
n3826, n3827, n3828, n3829, n3830, n3831, n3832, n3833, n3834, n3835,
n3836, n3837, n3838, n3839, n3840, n3841, n3842, n3843, n3844, n3845,
n3846, n3847, n3848, n3849, n3850, n3851, n3852, n3853, n3854, n3855,
n3856, n3857, n3858, n3859, n3860, n3861, n3862, n3863, n3864, n3865,
n3866, n3867, n3868, n3869, n3870, n3871, n3872, n3873, n3874, n3875,
n3876, n3877, n3878, n3879, n3880, n3881, n3882, n3883, n3884, n3885,
n3886, n3887, n3888, n3889, n3890, n3891, n3892, n3893, n3894, n3895,
n3896, n3897, n3898, n3899, n3900, n3901, n3902, n3903, n3904, n3905,
n3906, n3907, n3908, n3909, n3910, n3911, n3912, n3913, n3914, n3915,
n3916, n3917, n3918, n3919, n3920, n3921, n3922, n3923, n3924, n3925,
n3926, n3927, n3928, n3929, n3930, n3931, n3932, n3933, n3934, n3935,
n3936, n3937, n3938, n3939, n3940, n3941, n3942, n3943, n3944, n3945,
n3946, n3947, n3948, n3949, n3950, n3951, n3952, n3953, n3954, n3955,
n3956, n3957, n3958, n3959, n3960, n3961, n3962, n3963, n3964, n3965,
n3966, n3967, n3968, n3969, n3970, n3971, n3972, n3973, n3974, n3975,
n3976, n3977, n3978, n3979, n3980, n3981, n3982, n3983, n3984, n3985,
n3986, n3987, n3988, n3989, n3990, n3991, n3992, n3993, n3994, n3995,
n3996, n3997, n3998, n3999, n4000, n4001, n4002, n4003, n4004, n4005,
n4006, n4007, n4008, n4009, n4010, n4011, n4012, n4013, n4014, n4015,
n4016, n4017, n4018, n4019, n4020, n4021, n4022, n4023, n4024, n4025,
n4026, n4027, n4028, n4029, n4030, n4031, n4032, n4033, n4034, n4035,
n4036, n4037, n4038, n4039, n4040, n4041, n4042, n4043, n4044, n4045,
n4046, n4047, n4048, n4049, n4050, n4051, n4052, n4053, n4054, n4055,
n4056, n4057, n4058, n4059, n4060, n4061, n4062, n4063, n4064, n4065,
n4066, n4067, n4068, n4069, n4070, n4071, n4072, n4073, n4074, n4075,
n4076, n4077, n4078, n4079, n4080, n4081, n4082, n4083, n4084, n4085,
n4086, n4087, n4088, n4089, n4090, n4091, n4092, n4093, n4094, n4095,
n4096, n4097, n4098, n4099, n4100, n4101, n4102, n4103, n4104, n4105,
n4106, n4107, n4108, n4109, n4110, n4111, n4112, n4113, n4114, n4115,
n4116, n4117, n4118, n4119, n4120, n4121, n4122, n4123, n4124, n4125,
n4126, n4127, n4128, n4129, n4130, n4131, n4132, n4133, n4134, n4135,
n4136, n4137, n4138, n4139, n4140, n4141, n4142, n4143, n4144, n4145,
n4146, n4147, n4148, n4149, n4150, n4151, n4152, n4153, n4154, n4155,
n4156, n4157, n4158, n4159, n4160, n4161, n4162, n4163, n4164, n4165,
n4166, n4167, n4168, n4169, n4170, n4171, n4172, n4173, n4174, n4175,
n4176, n4177, n4178, n4179, n4180, n4181, n4182, n4183, n4184, n4185,
n4186, n4187, n4188, n4189, n4190, n4191, n4192, n4193, n4194, n4195,
n4196, n4197, n4198, n4199, n4200, n4201, n4202, n4203, n4204, n4205,
n4206, n4207, n4208, n4209, n4210, n4211, n4212, n4213, n4214, n4215,
n4216, n4217, n4218, n4219, n4220, n4221, n4222, n4223, n4224, n4225,
n4226, n4227, n4228, n4229, n4230, n4231, n4232, n4233, n4234, n4235,
n4236, n4237, n4238, n4239, n4240, n4241, n4242, n4243, n4244, n4245,
n4246, n4247, n4248, n4249, n4250, n4251, n4252, n4253, n4254, n4255,
n4256, n4257, n4258, n4259, n4260, n4261, n4262, n4263, n4264, n4265,
n4266, n4267, n4268, n4269, n4270, n4271, n4272, n4273, n4274, n4275,
n4276, n4277, n4278, n4279, n4280, n4281, n4282, n4283, n4284, n4285,
n4286, n4287, n4288, n4289, n4290, n4291, n4292, n4293, n4294, n4295,
n4296, n4297, n4298, n4299, n4300, n4301, n4302, n4303, n4304, n4305,
n4306, n4307, n4308, n4309, n4310, n4311, n4312, n4313, n4314, n4315,
n4316, n4317, n4318, n4319, n4320, n4321, n4322, n4323, n4324, n4325,
n4326, n4327, n4328, n4329, n4330, n4331, n4332, n4333, n4334, n4335,
n4336, n4337, n4338, n4339, n4340, n4341, n4342, n4343, n4344, n4345,
n4346, n4347, n4348, n4349, n4350, n4351, n4352, n4353, n4354, n4355,
n4356, n4357, n4358, n4359, n4360, n4361, n4362, n4363, n4364, n4365,
n4366, n4367, n4368, n4369, n4370, n4371, n4372, n4373, n4374, n4375,
n4376, n4377, n4378, n4379, n4380, n4381, n4382, n4383, n4384, n4385,
n4386, n4387, n4388, n4389, n4390, n4391, n4392, n4393, n4394, n4395,
n4396, n4397, n4398, n4399, n4400, n4401, n4402, n4403, n4404, n4405,
n4406, n4407, n4408, n4409, n4410, n4411, n4412, n4413, n4414, n4415,
n4416, n4417, n4418, n4419, n4420, n4421, n4422, n4423, n4424, n4425,
n4426, n4427, n4428, n4429, n4430, n4431, n4432, n4433, n4434, n4435,
n4436, n4437, n4438, n4439, n4440, n4441, n4442, n4443, n4444, n4445,
n4446, n4447, n4448, n4449, n4450, n4451, n4452, n4453, n4454, n4455,
n4456, n4457, n4458, n4459, n4460, n4461, n4462, n4463, n4464, n4465,
n4466, n4467, n4468, n4469, n4470, n4471, n4472, n4474, n4475, n4476,
n4477, n4478, n4479, n4480, n4481, n4482, n4483, n4484, n4485, n4486,
n4487, n4488, n4489, n4490, n4491, n4492, n4493, n4494, n4495, n4496,
n4497, n4498, n4499, n4500, n4501, n4502, n4503, n4504, n4505, n4506,
n4507, n4508, n4509, n4510, n4511, n4512, n4513, n4514, n4515, n4516,
n4517, n4518, n4519, n4520, n4521, n4522, n4523, n4524, n4525, n4526,
n4527, n4528, n4529, n4530, n4531, n4532, n4533, n4534, n4535, n4536,
n4537, n4538, n4539, n4540, n4541, n4542, n4543, n4544, n4545, n4546,
n4547, n4548, n4549, n4550, n4551, n4552, n4553, n4554, n4555, n4556,
n4557, n4558, n4559, n4560, n4561, n4562, n4563, n4564, n4565, n4566,
n4567, n4568, n4569, n4570, n4571, n4572, n4573, n4574, n4575, n4576,
n4577, n4578, n4579, n4580, n4581, n4582, n4583, n4584, n4585, n4586,
n4587, n4588, n4589, n4590, n4591, n4592, n4593, n4594, n4595, n4596,
n4597, n4598, n4599, n4600, n4601, n4602, n4603, n4604, n4605, n4606,
n4607, n4608, n4609, n4610, n4611, n4612, n4613, n4614, n4615, n4616,
n4617, n4618, n4619, n4620, n4621, n4622, n4623, n4624, n4625, n4626,
n4627, n4628, n4629, n4630, n4631, n4632, n4633, n4634, n4635, n4636,
n4637, n4638, n4639, n4640, n4641, n4642, n4643, n4644, n4645, n4646,
n4647, n4648, n4649, n4650, n4651, n4652, n4653, n4654, n4655, n4656,
n4657, n4658, n4659, n4660, n4661, n4662, n4663, n4664, n4665, n4666,
n4667, n4668, n4669, n4670, n4671, n4672, n4673, n4674, n4675, n4676,
n4677, n4678, n4679, n4680, n4681, n4682, n4683, n4684, n4685, n4686,
n4687, n4688, n4689, n4690, n4691, n4692, n4693, n4694, n4695, n4696,
n4697, n4698, n4699, n4700, n4701, n4702, n4703, n4704, n4705, n4706,
n4707, n4708, n4709, n4710, n4711, n4712, n4713, n4714, n4715, n4716,
n4717, n4718, n4719, n4720, n4721, n4722, n4723, n4724, n4725, n4726,
n4727, n4728, n4729, n4730, n4731, n4732, n4733, n4734, n4735, n4736,
n4737, n4738, n4739, n4740, n4741, n4742, n4743, n4744, n4745, n4746,
n4747, n4748, n4749, n4750, n4751, n4752, n4753, n4754, n4755, n4756,
n4757, n4758, n4759, n4760, n4761, n4762, n4763, n4764, n4765, n4766,
n4767, n4768, n4769, n4770, n4771, n4772, n4773, n4774, n4775, n4776,
n4777, n4778, n4779, n4780, n4781, n4782, n4783, n4784, n4785, n4786,
n4787, n4788, n4789, n4790, n4791, n4792, n4793, n4794, n4795, n4796,
n4797, n4798, n4799, n4800, n4801, n4802, n4803, n4804, n4805, n4806,
n4807, n4808, n4809, n4810, n4811, n4812, n4813, n4814, n4815, n4816,
n4817, n4818, n4819, n4820, n4821, n4822, n4823, n4824, n4825, n4826,
n4827, n4828, n4829, n4830, n4831, n4832, n4833, n4834, n4835, n4836,
n4837, n4838, n4839, n4840, n4841, n4842, n4843, n4844, n4845, n4846,
n4847, n4848, n4849, n4850, n4851, n4852, n4853, n4854, n4855, n4856,
n4857, n4858, n4859, n4860, n4861, n4862, n4863, n4864, n4865, n4866,
n4867, n4868, n4869, n4870, n4871, n4872, n4873, n4874, n4875, n4876,
n4877, n4878, n4879, n4880, n4881, n4882, n4883, n4884, n4885, n4886,
n4887, n4888, n4889, n4890, n4891, n4892, n4893, n4894, n4895, n4896,
n4897, n4898, n4899, n4900, n4901, n4902, n4903, n4904, n4905, n4906,
n4907, n4908, n4909, n4910, n4911, n4912, n4913, n4914, n4915, n4916,
n4917, n4918, n4919, n4920, n4921, n4922, n4923, n4924, n4925, n4926,
n4927, n4928, n4929, n4930, n4931, n4932, n4933, n4934, n4935, n4936,
n4937, n4938, n4939, n4940, n4941, n4942, n4943, n4944, n4945, n4946,
n4947, n4948, n4949, n4950, n4951, n4952, n4953, n4954, n4955, n4956,
n4957, n4958, n4959, n4960, n4961, n4962, n4963, n4964, n4965, n4966,
n4967, n4968, n4969, n4970, n4971, n4972, n4973, n4974, n4975, n4976,
n4977, n4978, n4979, n4980, n4981, n4982, n4983, n4984, n4985, n4986,
n4987, n4988, n4989, n4990, n4991, n4992, n4993, n4994, n4995, n4996,
n4997, n4998, n4999, n5000, n5001, n5002, n5003, n5004, n5005, n5006,
n5007, n5008, n5009, n5010, n5011, n5012, n5013, n5014, n5015, n5016,
n5017, n5018, n5019, n5020, n5021, n5022, n5023, n5024, n5025, n5026,
n5027, n5028, n5029, n5030, n5031, n5032, n5033, n5034, n5035, n5036,
n5037, n5038, n5039, n5040, n5041, n5042, n5043, n5044, n5045, n5046,
n5047, n5048, n5049, n5050, n5051, n5052, n5053, n5054, n5055, n5056,
n5057, n5058, n5059, n5060, n5061, n5062, n5063, n5064, n5065, n5066,
n5067, n5068, n5069, n5070, n5071, n5072, n5073, n5074, n5075, n5076,
n5077, n5078, n5079, n5080, n5081, n5082, n5083, n5084, n5085, n5086,
n5087, n5088, n5089, n5090, n5091, n5092, n5093, n5094, n5095, n5096,
n5097, n5098, n5099, n5100, n5101, n5102, n5103, n5104, n5105, n5106,
n5107, n5108, n5109, n5110, n5111, n5112, n5113, n5114, n5115, n5116,
n5117, n5118, n5119, n5120, n5121, n5122, n5123, n5124, n5125, n5126,
n5127, n5128, n5129, n5130, n5131, n5132, n5133, n5134, n5136, n5137,
n5138, n5139, n5140, n5141, n5142, n5143, n5144, n5145, n5146, n5147,
n5148, n5149, n5150, n5151, n5152, n5153, n5154, n5155, n5156, n5157,
n5158, n5159, n5160, n5161, n5162, n5163, n5164, n5165, n5166, n5167,
n5168, n5169, n5170, n5171, n5172, n5173, n5174, n5175, n5176, n5177,
n5178, n5179, n5180, n5181, n5182, n5183, n5184, n5185, n5186, n5187,
n5188, n5189, n5190, n5191, n5192, n5193, n5194, n5195, n5196, n5197,
n5198, n5199, n5200, n5201, n5202, n5203, n5204, n5205, n5206, n5207,
n5208, n5209, n5210, n5211, n5212, n5213, n5214, n5215, n5216, n5217,
n5218, n5219, n5220, n5221, n5222, n5223, n5224, n5225, n5226, n5227,
n5228, n5229, n5230, n5231, n5232, n5233, n5234, n5235, n5236, n5237,
n5238, n5239, n5240, n5241, n5242, n5243, n5244, n5245, n5246, n5247,
n5248, n5249, n5250, n5251, n5252, n5253, n5254, n5255, n5256, n5257,
n5258, n5259, n5260, n5261, n5262, n5263, n5264, n5265, n5266, n5267,
n5268, n5269, n5270, n5271, n5272, n5273, n5274, n5275, n5276, n5277,
n5278, n5279, n5280, n5281, n5282, n5283, n5284, n5285, n5286, n5287,
n5288, n5289, n5290, n5291, n5292, n5293, n5294, n5295, n5296, n5297,
n5298, n5299, n5300, n5301, n5302, n5303, n5304, n5305, n5306, n5307,
n5308, n5309, n5310, n5311, n5312, n5313, n5314, n5315, n5316, n5317,
n5318, n5319, n5320, n5321, n5322, n5323, n5324, n5325, n5326, n5327,
n5328, n5329, n5330, n5331, n5332, n5333, n5334, n5335, n5336, n5337,
n5338, n5339, n5340, n5341, n5342, n5343, n5344, n5345, n5346, n5347,
n5348, n5349, n5350, n5351, n5352, n5353, n5354, n5355, n5356, n5357,
n5358, n5359, n5360, n5361, n5362, n5363, n5364, n5365, n5366, n5367,
n5368, n5369, n5370, n5371, n5372, n5373, n5374, n5375, n5376, n5377,
n5378, n5379, n5380, n5381, n5382, n5383, n5384, n5385, n5386, n5387,
n5388, n5389, n5390, n5391, n5392, n5393, n5394, n5395, n5396, n5397,
n5398, n5399, n5400, n5401, n5402, n5403, n5404, n5405, n5406, n5407,
n5408, n5409, n5410, n5411, n5412, n5413, n5414, n5415, n5416, n5417,
n5418, n5419, n5420, n5421, n5422, n5423, n5424, n5425, n5426, n5427,
n5428, n5429, n5430, n5431, n5432, n5433, n5434, n5435, n5436, n5437,
n5438, n5439, n5440, n5441, n5442, n5443, n5444, n5445, n5446, n5447,
n5448, n5449, n5450, n5451, n5452, n5453, n5454, n5455, n5456, n5457,
n5458, n5459, n5460, n5461, n5462, n5463, n5464, n5465, n5466, n5467,
n5468, n5469, n5470, n5471, n5472, n5473, n5474, n5475, n5476, n5477,
n5478, n5479, n5480, n5481, n5482, n5483, n5484, n5485, n5486, n5487,
n5488, n5489, n5490, n5491, n5492, n5493, n5494, n5495, n5496, n5497,
n5498, n5499, n5500, n5501, n5502, n5503, n5504, n5505, n5506, n5507,
n5508, n5509, n5510, n5511, n5512, n5513, n5514, n5515, n5516, n5517,
n5518, n5519, n5520, n5521, n5522, n5523, n5524, n5525, n5526, n5527,
n5528, n5529, n5530, n5531, n5532, n5533, n5534, n5535, n5536, n5537,
n5538, n5539, n5540, n5541, n5542, n5543, n5544, n5545, n5546, n5547,
n5548, n5549, n5550, n5551, n5552, n5553, n5554, n5555, n5556, n5557,
n5558, n5559, n5560, n5561, n5562, n5563, n5564, n5565, n5566, n5567,
n5568, n5569, n5570, n5571, n5572, n5573, n5574, n5575, n5576, n5577,
n5578, n5579, n5580, n5581, n5582, n5583, n5584, n5585, n5586, n5587,
n5588, n5589, n5590, n5591, n5592, n5594, n5595, n5596, n5597, n5598,
n5599, n5600, n5601, n5602, n5603, n5604, n5605, n5606, n5607, n5608,
n5609, n5610, n5611, n5612, n5613, n5614, n5615, n5616, n5617, n5618,
n5619, n5620, n5621, n5622, n5623, n5624, n5625, n5626, n5627, n5628,
n5629, n5630, n5631, n5632, n5633, n5634, n5635, n5636, n5637, n5638,
n5639, n5640, n5641, n5642, n5643, n5644, n5645, n5646, n5647, n5648,
n5649, n5650, n5651, n5652, n5653, n5654, n5655, n5656, n5657, n5658,
n5659, n5660, n5661, n5662, n5663, n5664, n5665, n5666, n5667, n5668,
n5669, n5670, n5671, n5672, n5673, n5674, n5675, n5676, n5677, n5678,
n5679, n5680, n5681, n5682, n5683, n5684, n5685, n5686, n5687, n5688,
n5689, n5690, n5691, n5692, n5693, n5694, n5695, n5696, n5697, n5698,
n5699, n5700, n5701, n5702, n5703, n5704, n5705, n5706, n5707, n5708,
n5709, n5710, n5711, n5712, n5713, n5714, n5715, n5716, n5717, n5718,
n5719, n5720, n5721, n5722, n5723, n5724, n5725, n5726, n5727, n5728,
n5729, n5730, n5731, n5732, n5733, n5734, n5735, n5736, n5737, n5738,
n5739, n5740, n5741, n5742, n5743, n5744, n5745, n5746, n5747, n5748,
n5749, n5750, n5751, n5752, n5753, n5754, n5755, n5756, n5757, n5758,
n5759, n5760, n5761, n5762, n5763, n5764, n5765, n5766, n5767, n5768,
n5769, n5770, n5771, n5772, n5773, n5774, n5775, n5776, n5777, n5778,
n5779, n5780, n5781, n5782, n5783, n5784, n5785, n5786, n5787, n5788,
n5789, n5790, n5791, n5792, n5793, n5794, n5795, n5796, n5797, n5798,
n5799, n5800, n5801, n5802, n5803, n5804, n5805, n5806, n5807, n5808,
n5809, n5810, n5811, n5812, n5813, n5814, n5815, n5816, n5817, n5818,
n5819, n5820, n5821, n5822, n5823, n5824, n5825, n5826, n5827, n5828,
n5829, n5830, n5831, n5832, n5833, n5834, n5835, n5836, n5837, n5838,
n5839, n5840, n5841, n5842, n5843, n5844, n5845, n5846, n5847, n5848,
n5849, n5850, n5851, n5852, n5853, n5854, n5855, n5856, n5857, n5858,
n5859, n5860, n5861, n5862, n5863, n5864, n5865, n5866, n5867, n5868,
n5869, n5870, n5871, n5872, n5873, n5874, n5875, n5876, n5877, n5878,
n5879, n5880, n5881, n5882, n5883, n5884, n5885, n5886, n5887, n5888,
n5889, n5890, n5891, n5892, n5893, n5894, n5895, n5896, n5897, n5898,
n5899, n5900, n5901, n5902, n5903, n5904, n5905, n5906, n5907, n5908,
n5909, n5910, n5911, n5912, n5913, n5914, n5915, n5916, n5917, n5918,
n5919, n5920, n5921, n5922, n5923, n5924, n5925, n5926, n5927, n5928,
n5929, n5930, n5931, n5932, n5933, n5934, n5935, n5936, n5937, n5938,
n5939, n5940, n5941, n5942, n5943, n5944, n5945, n5946, n5947, n5948,
n5949, n5950, n5951, n5952, n5953, n5954, n5955, n5956, n5957, n5958,
n5959, n5960, n5961, n5962, n5963, n5964, n5965, n5966, n5967, n5968,
n5969, n5970, n5971, n5972, n5973, n5974, n5975, n5976, n5977, n5978,
n5979, n5980, n5981, n5982, n5983, n5984, n5985, n5986, n5987, n5988,
n5989, n5990, n5991, n5992, n5993, n5994, n5995, n5996, n5997, n5998,
n5999, n6000, n6001, n6002, n6003, n6004, n6005, n6006, n6007, n6008,
n6009, n6010, n6011, n6012, n6013, n6014, n6015, n6016, n6017, n6018,
n6019, n6020, n6021, n6022, n6023, n6024, n6025, n6026, n6027, n6028,
n6029, n6030, n6031, n6032, n6033, n6034, n6035, n6036, n6037, n6038,
n6039, n6040, n6041, n6042, n6043, n6044, n6045, n6046, n6047, n6048,
n6049, n6050, n6051, n6052, n6053, n6054, n6055, n6056, n6057, n6058,
n6059, n6060, n6061, n6062, n6063, n6064, n6065, n6066, n6067, n6068,
n6069, n6070, n6071, n6072, n6073, n6074, n6075, n6076, n6077, n6078,
n6079, n6080, n6081, n6082, n6083, n6084, n6085, n6086, n6087, n6088,
n6089, n6090, n6091, n6092, n6093, n6094, n6095, n6096, n6097, n6098,
n6099, n6100, n6101, n6102, n6103, n6104, n6105, n6106, n6107, n6108,
n6109, n6110, n6111, n6112, n6113, n6114, n6115, n6116, n6117, n6118,
n6119, n6120, n6121, n6122, n6123, n6124, n6125, n6126, n6127, n6128,
n6129, n6130, n6131, n6132, n6133, n6134, n6135, n6136, n6137, n6138,
n6139, n6140, n6141, n6142, n6143, n6144, n6145, n6146, n6147, n6148,
n6149, n6150, n6151, n6152, n6153, n6154, n6155, n6156, n6157, n6158,
n6159, n6160, n6161, n6162, n6163, n6164, n6165, n6166, n6167, n6168,
n6169, n6170, n6171, n6172, n6173, n6174, n6175, n6176, n6177, n6178,
n6179, n6180, n6181, n6182, n6183, n6184, n6185, n6186, n6187, n6188,
n6189, n6190, n6191, n6192, n6193, n6194, n6195, n6196, n6197, n6198,
n6199, n6200, n6201, n6202, n6203, n6204, n6205, n6206, n6207, n6208,
n6209, n6210, n6211, n6212, n6213, n6214, n6215, n6216, n6217, n6218,
n6219, n6220, n6221, n6222, n6223, n6224, n6225, n6226, n6227, n6228,
n6229, n6230, n6231, n6232, n6233, n6234, n6235, n6236, n6237, n6238,
n6239, n6240, n6241, n6242, n6243, n6244, n6245, n6246, n6247, n6248,
n6249, n6250, n6251, n6252, n6253, n6254, n6255, n6256, n6257, n6258,
n6259, n6260, n6261, n6262, n6263, n6264, n6265, n6266, n6267, n6268,
n6269, n6270, n6271, n6272, n6273, n6274, n6275, n6276, n6277, n6278,
n6279, n6280, n6281, n6282, n6283, n6284, n6285, n6286, n6287, n6288,
n6289, n6290, n6291, n6292, n6293, n6294, n6295, n6296, n6297, n6298,
n6299, n6300, n6301, n6302, n6303, n6304, n6305, n6306, n6307, n6308,
n6309, n6310, n6311, n6312, n6313, n6314, n6315, n6316, n6317, n6318,
n6319, n6320, n6321, n6322, n6323, n6324, n6325, n6326, n6327, n6328,
n6329, n6330, n6331, n6332, n6333, n6334, n6335, n6336, n6338, n6339,
n6340, n6341, n6342, n6343, n6344, n6345, n6346, n6347, n6348, n6349,
n6350, n6351, n6352, n6353, n6354, n6355, n6356, n6357, n6358, n6359,
n6360, n6361, n6362, n6363, n6364, n6365, n6366, n6367, n6368, n6369,
n6370, n6371, n6372, n6373, n6374, n6375, n6376, n6377, n6378, n6379,
n6380, n6381, n6382, n6383, n6384, n6385, n6386, n6387, n6388, n6389,
n6390, n6391, n6392, n6393, n6394, n6395, n6396, n6397, n6398, n6399,
n6400, n6401, n6402, n6403, n6404, n6405, n6535, n6536, n6537, n6538,
n6539, n6540, n6541, n6542, n6543, n6544, n6545, n6546, n6547, n6548,
n6549, n6550, n6551, n6552, n6553, n6554, n6555, n6556, n6557, n6558,
n6559, n6560, n6561, n6562, n6563, n6564, n6565, n6566, n6567, n6568,
n6569, n6570, n6571, n6572, n6573, n6574, n6575, n6576, n6577, n6578,
n6579, n6580, n6581, n6582, n6583, n6584, n6585, n6586, n6587, n6588,
n6589, n6590, n6591, n6592, n6593, n6594, n6595, n6596, n6597, n6598,
n6599, n6600, n6601, n6602, n6603, n6604, n6605, n6606, n6607, n6608,
n6609, n6610, n6611, n6612, n6613, n6614, n6615, n6616, n6617, n6618,
n6619, n6620, n6621, n6622, n6623, n6624, n6625, n6626, n6627, n6628,
n6629, n6630, n6631;
wire [105:0] P_Sgf;
wire [1:0] FSM_selector_B;
wire [63:0] Op_MX;
wire [63:0] Op_MY;
wire [11:0] exp_oper_result;
wire [11:0] S_Oper_A_exp;
wire [52:0] Add_result;
wire [52:0] Sgf_normalized_result;
wire [3:0] FS_Module_state_reg;
wire [11:0] Exp_module_Data_S;
wire [26:0] Sgf_operation_Result;
wire [55:0] Sgf_operation_ODD1_Q_middle;
wire [53:27] Sgf_operation_ODD1_Q_right;
wire [51:0] Sgf_operation_ODD1_Q_left;
DFFQX1TS Sgf_operation_ODD1_left_DatO_reg_46_ ( .D(
Sgf_operation_ODD1_left_N46), .CK(clk), .Q(
Sgf_operation_ODD1_Q_left[46]) );
DFFQX1TS Sgf_operation_ODD1_left_DatO_reg_47_ ( .D(
Sgf_operation_ODD1_left_N47), .CK(clk), .Q(
Sgf_operation_ODD1_Q_left[47]) );
DFFQX1TS Sgf_operation_ODD1_left_DatO_reg_48_ ( .D(
Sgf_operation_ODD1_left_N48), .CK(clk), .Q(
Sgf_operation_ODD1_Q_left[48]) );
DFFQX1TS Sgf_operation_ODD1_left_DatO_reg_49_ ( .D(
Sgf_operation_ODD1_left_N49), .CK(clk), .Q(
Sgf_operation_ODD1_Q_left[49]) );
DFFQX1TS Sgf_operation_ODD1_left_DatO_reg_50_ ( .D(
Sgf_operation_ODD1_left_N50), .CK(clk), .Q(
Sgf_operation_ODD1_Q_left[50]) );
DFFQX1TS Sgf_operation_ODD1_left_DatO_reg_51_ ( .D(
Sgf_operation_ODD1_left_N51), .CK(clk), .Q(
Sgf_operation_ODD1_Q_left[51]) );
DFFQX1TS Sgf_operation_ODD1_right_DatO_reg_38_ ( .D(
Sgf_operation_ODD1_right_N38), .CK(clk), .Q(
Sgf_operation_ODD1_Q_right[38]) );
DFFQX1TS Sgf_operation_ODD1_right_DatO_reg_39_ ( .D(
Sgf_operation_ODD1_right_N39), .CK(clk), .Q(
Sgf_operation_ODD1_Q_right[39]) );
DFFQX1TS Sgf_operation_ODD1_right_DatO_reg_47_ ( .D(
Sgf_operation_ODD1_right_N47), .CK(clk), .Q(
Sgf_operation_ODD1_Q_right[47]) );
DFFQX1TS Sgf_operation_ODD1_right_DatO_reg_48_ ( .D(
Sgf_operation_ODD1_right_N48), .CK(clk), .Q(
Sgf_operation_ODD1_Q_right[48]) );
DFFQX1TS Sgf_operation_ODD1_right_DatO_reg_49_ ( .D(
Sgf_operation_ODD1_right_N49), .CK(clk), .Q(
Sgf_operation_ODD1_Q_right[49]) );
DFFQX1TS Sgf_operation_ODD1_right_DatO_reg_50_ ( .D(
Sgf_operation_ODD1_right_N50), .CK(clk), .Q(
Sgf_operation_ODD1_Q_right[50]) );
DFFQX1TS Sgf_operation_ODD1_right_DatO_reg_51_ ( .D(
Sgf_operation_ODD1_right_N51), .CK(clk), .Q(
Sgf_operation_ODD1_Q_right[51]) );
DFFQX1TS Sgf_operation_ODD1_right_DatO_reg_52_ ( .D(
Sgf_operation_ODD1_right_N52), .CK(clk), .Q(
Sgf_operation_ODD1_Q_right[52]) );
DFFQX1TS Sgf_operation_ODD1_right_DatO_reg_53_ ( .D(
Sgf_operation_ODD1_right_N53), .CK(clk), .Q(
Sgf_operation_ODD1_Q_right[53]) );
DFFQX1TS Sgf_operation_ODD1_middle_DatO_reg_28_ ( .D(
Sgf_operation_ODD1_middle_N28), .CK(clk), .Q(
Sgf_operation_ODD1_Q_middle[28]) );
DFFQX1TS Sgf_operation_ODD1_middle_DatO_reg_36_ ( .D(
Sgf_operation_ODD1_middle_N36), .CK(clk), .Q(
Sgf_operation_ODD1_Q_middle[36]) );
DFFQX1TS Sgf_operation_ODD1_middle_DatO_reg_40_ ( .D(
Sgf_operation_ODD1_middle_N40), .CK(clk), .Q(
Sgf_operation_ODD1_Q_middle[40]) );
DFFQX1TS Sgf_operation_ODD1_middle_DatO_reg_41_ ( .D(
Sgf_operation_ODD1_middle_N41), .CK(clk), .Q(
Sgf_operation_ODD1_Q_middle[41]) );
DFFQX1TS Sgf_operation_ODD1_middle_DatO_reg_42_ ( .D(
Sgf_operation_ODD1_middle_N42), .CK(clk), .Q(
Sgf_operation_ODD1_Q_middle[42]) );
DFFQX1TS Sgf_operation_ODD1_middle_DatO_reg_43_ ( .D(
Sgf_operation_ODD1_middle_N43), .CK(clk), .Q(
Sgf_operation_ODD1_Q_middle[43]) );
DFFQX1TS Sgf_operation_ODD1_middle_DatO_reg_44_ ( .D(
Sgf_operation_ODD1_middle_N44), .CK(clk), .Q(
Sgf_operation_ODD1_Q_middle[44]) );
DFFQX1TS Sgf_operation_ODD1_middle_DatO_reg_45_ ( .D(
Sgf_operation_ODD1_middle_N45), .CK(clk), .Q(
Sgf_operation_ODD1_Q_middle[45]) );
DFFQX1TS Sgf_operation_ODD1_middle_DatO_reg_49_ ( .D(
Sgf_operation_ODD1_middle_N49), .CK(clk), .Q(
Sgf_operation_ODD1_Q_middle[49]) );
DFFQX1TS Sgf_operation_ODD1_middle_DatO_reg_50_ ( .D(
Sgf_operation_ODD1_middle_N50), .CK(clk), .Q(
Sgf_operation_ODD1_Q_middle[50]) );
DFFQX1TS Sgf_operation_ODD1_middle_DatO_reg_51_ ( .D(
Sgf_operation_ODD1_middle_N51), .CK(clk), .Q(
Sgf_operation_ODD1_Q_middle[51]) );
DFFQX1TS Sgf_operation_ODD1_middle_DatO_reg_52_ ( .D(
Sgf_operation_ODD1_middle_N52), .CK(clk), .Q(
Sgf_operation_ODD1_Q_middle[52]) );
DFFQX1TS Sgf_operation_ODD1_middle_DatO_reg_53_ ( .D(
Sgf_operation_ODD1_middle_N53), .CK(clk), .Q(
Sgf_operation_ODD1_Q_middle[53]) );
DFFQX1TS Sgf_operation_ODD1_middle_DatO_reg_54_ ( .D(
Sgf_operation_ODD1_middle_N54), .CK(clk), .Q(
Sgf_operation_ODD1_Q_middle[54]) );
DFFQX1TS Sgf_operation_ODD1_middle_DatO_reg_55_ ( .D(
Sgf_operation_ODD1_middle_N55), .CK(clk), .Q(
Sgf_operation_ODD1_Q_middle[55]) );
DFFRXLTS Operands_load_reg_YMRegister_Q_reg_63_ ( .D(n715), .CK(clk), .RN(
n6619), .Q(Op_MY[63]) );
DFFRXLTS Zero_Result_Detect_Zero_Info_Mult_Q_reg_0_ ( .D(n581), .CK(clk),
.RN(n6615), .Q(zero_flag) );
DFFRXLTS Operands_load_reg_XMRegister_Q_reg_24_ ( .D(n670), .CK(clk), .RN(
n6617), .QN(n735) );
DFFRXLTS Operands_load_reg_XMRegister_Q_reg_22_ ( .D(n668), .CK(clk), .RN(
n1633), .Q(n733), .QN(n749) );
DFFRXLTS Operands_load_reg_XMRegister_Q_reg_18_ ( .D(n664), .CK(clk), .RN(
n6620), .Q(n737), .QN(n738) );
DFFRXLTS Operands_load_reg_XMRegister_Q_reg_17_ ( .D(n663), .CK(clk), .RN(
n6617), .Q(n734), .QN(n736) );
DFFRXLTS Operands_load_reg_XMRegister_Q_reg_16_ ( .D(n662), .CK(clk), .RN(
n1633), .Q(n730), .QN(n747) );
DFFRXLTS Operands_load_reg_XMRegister_Q_reg_11_ ( .D(n657), .CK(clk), .RN(
n6615), .Q(n732), .QN(n746) );
DFFRXLTS Operands_load_reg_XMRegister_Q_reg_10_ ( .D(n656), .CK(clk), .RN(
n6614), .Q(n744), .QN(n748) );
DFFRXLTS Operands_load_reg_XMRegister_Q_reg_6_ ( .D(n652), .CK(clk), .RN(
n6618), .Q(n731), .QN(n745) );
DFFRXLTS Adder_M_Add_Subt_Result_Q_reg_0_ ( .D(n579), .CK(clk), .RN(n6624),
.Q(Add_result[0]) );
DFFRXLTS Sgf_operation_ODD1_finalreg_Q_reg_52_ ( .D(n473), .CK(clk), .RN(
n6600), .Q(P_Sgf[52]) );
DFFRXLTS Sgf_operation_ODD1_finalreg_Q_reg_51_ ( .D(n472), .CK(clk), .RN(
n6601), .Q(P_Sgf[51]) );
DFFRXLTS Sgf_operation_ODD1_finalreg_Q_reg_47_ ( .D(n468), .CK(clk), .RN(
n784), .Q(P_Sgf[47]) );
DFFRXLTS Sgf_operation_ODD1_finalreg_Q_reg_46_ ( .D(n467), .CK(clk), .RN(
n6607), .Q(P_Sgf[46]) );
DFFRXLTS Sgf_operation_ODD1_finalreg_Q_reg_45_ ( .D(n466), .CK(clk), .RN(
n6603), .Q(P_Sgf[45]) );
DFFRXLTS Sgf_operation_ODD1_finalreg_Q_reg_44_ ( .D(n465), .CK(clk), .RN(
n6600), .Q(P_Sgf[44]) );
DFFRXLTS Sgf_operation_ODD1_finalreg_Q_reg_43_ ( .D(n464), .CK(clk), .RN(
n6604), .Q(P_Sgf[43]) );
DFFRXLTS Sgf_operation_ODD1_finalreg_Q_reg_42_ ( .D(n463), .CK(clk), .RN(
n6602), .Q(P_Sgf[42]) );
DFFRXLTS Sgf_operation_ODD1_finalreg_Q_reg_41_ ( .D(n462), .CK(clk), .RN(
n6599), .Q(P_Sgf[41]) );
DFFRXLTS Sgf_operation_ODD1_finalreg_Q_reg_40_ ( .D(n461), .CK(clk), .RN(
n784), .Q(P_Sgf[40]) );
DFFRXLTS Sgf_operation_ODD1_finalreg_Q_reg_39_ ( .D(n460), .CK(clk), .RN(
n6605), .Q(P_Sgf[39]) );
DFFRXLTS Sgf_operation_ODD1_finalreg_Q_reg_35_ ( .D(n456), .CK(clk), .RN(
n6602), .Q(P_Sgf[35]) );
DFFRXLTS Sgf_operation_ODD1_finalreg_Q_reg_31_ ( .D(n452), .CK(clk), .RN(
n6601), .Q(P_Sgf[31]) );
DFFRXLTS Sgf_operation_ODD1_finalreg_Q_reg_27_ ( .D(n448), .CK(clk), .RN(
n6599), .Q(P_Sgf[27]) );
DFFRXLTS Sgf_operation_ODD1_finalreg_Q_reg_23_ ( .D(n444), .CK(clk), .RN(
n6600), .Q(P_Sgf[23]) );
DFFRXLTS Sgf_operation_ODD1_finalreg_Q_reg_19_ ( .D(n440), .CK(clk), .RN(
n6606), .Q(P_Sgf[19]) );
DFFRXLTS Sgf_operation_ODD1_finalreg_Q_reg_15_ ( .D(n436), .CK(clk), .RN(
n6607), .Q(P_Sgf[15]) );
DFFRXLTS Sgf_operation_ODD1_finalreg_Q_reg_11_ ( .D(n432), .CK(clk), .RN(
n6601), .Q(P_Sgf[11]) );
DFFRXLTS Sgf_operation_ODD1_finalreg_Q_reg_7_ ( .D(n428), .CK(clk), .RN(
n6604), .Q(P_Sgf[7]) );
DFFRXLTS Sgf_operation_ODD1_finalreg_Q_reg_3_ ( .D(n424), .CK(clk), .RN(n784), .Q(P_Sgf[3]) );
DFFRXLTS Barrel_Shifter_module_Output_Reg_Q_reg_52_ ( .D(n580), .CK(clk),
.RN(n6611), .Q(Sgf_normalized_result[52]) );
DFFRXLTS Barrel_Shifter_module_Output_Reg_Q_reg_3_ ( .D(n356), .CK(clk),
.RN(n6613), .QN(n739) );
CMPR32X2TS DP_OP_36J43_124_1029_U13 ( .A(S_Oper_A_exp[0]), .B(n766), .C(
DP_OP_36J43_124_1029_n28), .CO(DP_OP_36J43_124_1029_n12), .S(
Exp_module_Data_S[0]) );
CMPR32X2TS DP_OP_36J43_124_1029_U12 ( .A(DP_OP_36J43_124_1029_n27), .B(
S_Oper_A_exp[1]), .C(DP_OP_36J43_124_1029_n12), .CO(
DP_OP_36J43_124_1029_n11), .S(Exp_module_Data_S[1]) );
CMPR32X2TS DP_OP_36J43_124_1029_U11 ( .A(DP_OP_36J43_124_1029_n26), .B(
S_Oper_A_exp[2]), .C(DP_OP_36J43_124_1029_n11), .CO(
DP_OP_36J43_124_1029_n10), .S(Exp_module_Data_S[2]) );
CMPR32X2TS DP_OP_36J43_124_1029_U10 ( .A(DP_OP_36J43_124_1029_n25), .B(
S_Oper_A_exp[3]), .C(DP_OP_36J43_124_1029_n10), .CO(
DP_OP_36J43_124_1029_n9), .S(Exp_module_Data_S[3]) );
CMPR32X2TS DP_OP_36J43_124_1029_U9 ( .A(DP_OP_36J43_124_1029_n24), .B(
S_Oper_A_exp[4]), .C(DP_OP_36J43_124_1029_n9), .CO(
DP_OP_36J43_124_1029_n8), .S(Exp_module_Data_S[4]) );
CMPR32X2TS DP_OP_36J43_124_1029_U8 ( .A(DP_OP_36J43_124_1029_n23), .B(
S_Oper_A_exp[5]), .C(DP_OP_36J43_124_1029_n8), .CO(
DP_OP_36J43_124_1029_n7), .S(Exp_module_Data_S[5]) );
CMPR32X2TS DP_OP_36J43_124_1029_U7 ( .A(DP_OP_36J43_124_1029_n22), .B(
S_Oper_A_exp[6]), .C(DP_OP_36J43_124_1029_n7), .CO(
DP_OP_36J43_124_1029_n6), .S(Exp_module_Data_S[6]) );
CMPR32X2TS DP_OP_36J43_124_1029_U6 ( .A(DP_OP_36J43_124_1029_n21), .B(
S_Oper_A_exp[7]), .C(DP_OP_36J43_124_1029_n6), .CO(
DP_OP_36J43_124_1029_n5), .S(Exp_module_Data_S[7]) );
CMPR32X2TS DP_OP_36J43_124_1029_U5 ( .A(DP_OP_36J43_124_1029_n20), .B(
S_Oper_A_exp[8]), .C(DP_OP_36J43_124_1029_n5), .CO(
DP_OP_36J43_124_1029_n4), .S(Exp_module_Data_S[8]) );
CMPR32X2TS DP_OP_36J43_124_1029_U4 ( .A(DP_OP_36J43_124_1029_n19), .B(
S_Oper_A_exp[9]), .C(DP_OP_36J43_124_1029_n4), .CO(
DP_OP_36J43_124_1029_n3), .S(Exp_module_Data_S[9]) );
CMPR32X2TS DP_OP_36J43_124_1029_U3 ( .A(DP_OP_36J43_124_1029_n18), .B(
S_Oper_A_exp[10]), .C(DP_OP_36J43_124_1029_n3), .CO(
DP_OP_36J43_124_1029_n2), .S(Exp_module_Data_S[10]) );
CMPR32X2TS DP_OP_36J43_124_1029_U2 ( .A(n6582), .B(S_Oper_A_exp[11]), .C(
DP_OP_36J43_124_1029_n2), .CO(DP_OP_36J43_124_1029_n1), .S(
Exp_module_Data_S[11]) );
CMPR42X1TS DP_OP_169J43_123_4229_U975 ( .A(DP_OP_169J43_123_4229_n1673), .B(
DP_OP_169J43_123_4229_n1701), .C(DP_OP_169J43_123_4229_n1308), .D(
DP_OP_169J43_123_4229_n1729), .ICI(DP_OP_169J43_123_4229_n1756), .S(
DP_OP_169J43_123_4229_n1305), .ICO(DP_OP_169J43_123_4229_n1303), .CO(
DP_OP_169J43_123_4229_n1304) );
CMPR42X1TS DP_OP_169J43_123_4229_U973 ( .A(DP_OP_169J43_123_4229_n1302), .B(
DP_OP_169J43_123_4229_n1700), .C(DP_OP_169J43_123_4229_n1303), .D(
DP_OP_169J43_123_4229_n1728), .ICI(DP_OP_169J43_123_4229_n1755), .S(
DP_OP_169J43_123_4229_n1300), .ICO(DP_OP_169J43_123_4229_n1298), .CO(
DP_OP_169J43_123_4229_n1299) );
CMPR42X1TS DP_OP_169J43_123_4229_U971 ( .A(DP_OP_169J43_123_4229_n1699), .B(
DP_OP_169J43_123_4229_n1297), .C(DP_OP_169J43_123_4229_n1727), .D(
DP_OP_169J43_123_4229_n1754), .ICI(DP_OP_169J43_123_4229_n1298), .S(
DP_OP_169J43_123_4229_n1295), .ICO(DP_OP_169J43_123_4229_n1293), .CO(
DP_OP_169J43_123_4229_n1294) );
CMPR42X1TS DP_OP_169J43_123_4229_U968 ( .A(DP_OP_169J43_123_4229_n1698), .B(
DP_OP_169J43_123_4229_n1753), .C(DP_OP_169J43_123_4229_n1726), .D(
DP_OP_169J43_123_4229_n1290), .ICI(DP_OP_169J43_123_4229_n1293), .S(
DP_OP_169J43_123_4229_n1288), .ICO(DP_OP_169J43_123_4229_n1286), .CO(
DP_OP_169J43_123_4229_n1287) );
CMPR42X1TS DP_OP_169J43_123_4229_U967 ( .A(DP_OP_169J43_123_4229_n1613), .B(
DP_OP_169J43_123_4229_n1641), .C(DP_OP_169J43_123_4229_n1291), .D(
DP_OP_169J43_123_4229_n1669), .ICI(DP_OP_169J43_123_4229_n1697), .S(
DP_OP_169J43_123_4229_n1285), .ICO(DP_OP_169J43_123_4229_n1283), .CO(
DP_OP_169J43_123_4229_n1284) );
CMPR42X1TS DP_OP_169J43_123_4229_U964 ( .A(DP_OP_169J43_123_4229_n1279), .B(
DP_OP_169J43_123_4229_n1640), .C(DP_OP_169J43_123_4229_n1283), .D(
DP_OP_169J43_123_4229_n1668), .ICI(DP_OP_169J43_123_4229_n1751), .S(
DP_OP_169J43_123_4229_n1277), .ICO(DP_OP_169J43_123_4229_n1275), .CO(
DP_OP_169J43_123_4229_n1276) );
CMPR42X1TS DP_OP_169J43_123_4229_U961 ( .A(DP_OP_169J43_123_4229_n1639), .B(
DP_OP_169J43_123_4229_n1271), .C(DP_OP_169J43_123_4229_n1667), .D(
DP_OP_169J43_123_4229_n1695), .ICI(DP_OP_169J43_123_4229_n1275), .S(
DP_OP_169J43_123_4229_n1269), .ICO(DP_OP_169J43_123_4229_n1267), .CO(
DP_OP_169J43_123_4229_n1268) );
CMPR42X1TS DP_OP_169J43_123_4229_U960 ( .A(DP_OP_169J43_123_4229_n1750), .B(
DP_OP_169J43_123_4229_n1723), .C(DP_OP_169J43_123_4229_n1276), .D(
DP_OP_169J43_123_4229_n1272), .ICI(DP_OP_169J43_123_4229_n1269), .S(
DP_OP_169J43_123_4229_n1266), .ICO(DP_OP_169J43_123_4229_n1264), .CO(
DP_OP_169J43_123_4229_n1265) );
CMPR42X1TS DP_OP_169J43_123_4229_U957 ( .A(DP_OP_169J43_123_4229_n1638), .B(
DP_OP_169J43_123_4229_n1694), .C(DP_OP_169J43_123_4229_n1749), .D(
DP_OP_169J43_123_4229_n1261), .ICI(DP_OP_169J43_123_4229_n1267), .S(
DP_OP_169J43_123_4229_n1259), .ICO(DP_OP_169J43_123_4229_n1257), .CO(
DP_OP_169J43_123_4229_n1258) );
CMPR42X1TS DP_OP_169J43_123_4229_U955 ( .A(DP_OP_169J43_123_4229_n1553), .B(
DP_OP_169J43_123_4229_n1581), .C(DP_OP_169J43_123_4229_n1262), .D(
DP_OP_169J43_123_4229_n1609), .ICI(DP_OP_169J43_123_4229_n1637), .S(
DP_OP_169J43_123_4229_n1253), .ICO(DP_OP_169J43_123_4229_n1251), .CO(
DP_OP_169J43_123_4229_n1252) );
CMPR42X1TS DP_OP_169J43_123_4229_U954 ( .A(DP_OP_169J43_123_4229_n1260), .B(
DP_OP_169J43_123_4229_n1748), .C(DP_OP_169J43_123_4229_n1721), .D(
DP_OP_169J43_123_4229_n1693), .ICI(DP_OP_169J43_123_4229_n1257), .S(
DP_OP_169J43_123_4229_n1250), .ICO(DP_OP_169J43_123_4229_n1248), .CO(
DP_OP_169J43_123_4229_n1249) );
CMPR42X1TS DP_OP_169J43_123_4229_U953 ( .A(DP_OP_169J43_123_4229_n1665), .B(
DP_OP_169J43_123_4229_n1253), .C(DP_OP_169J43_123_4229_n1258), .D(
DP_OP_169J43_123_4229_n1254), .ICI(DP_OP_169J43_123_4229_n1250), .S(
DP_OP_169J43_123_4229_n1247), .ICO(DP_OP_169J43_123_4229_n1245), .CO(
DP_OP_169J43_123_4229_n1246) );
CMPR42X1TS DP_OP_169J43_123_4229_U951 ( .A(DP_OP_169J43_123_4229_n1244), .B(
DP_OP_169J43_123_4229_n1580), .C(DP_OP_169J43_123_4229_n1251), .D(
DP_OP_169J43_123_4229_n1608), .ICI(DP_OP_169J43_123_4229_n1692), .S(
DP_OP_169J43_123_4229_n1242), .ICO(DP_OP_169J43_123_4229_n1240), .CO(
DP_OP_169J43_123_4229_n1241) );
CMPR42X1TS DP_OP_169J43_123_4229_U950 ( .A(DP_OP_169J43_123_4229_n1664), .B(
DP_OP_169J43_123_4229_n1636), .C(DP_OP_169J43_123_4229_n1720), .D(
DP_OP_169J43_123_4229_n1747), .ICI(DP_OP_169J43_123_4229_n1248), .S(
DP_OP_169J43_123_4229_n1239), .ICO(DP_OP_169J43_123_4229_n1237), .CO(
DP_OP_169J43_123_4229_n1238) );
CMPR42X1TS DP_OP_169J43_123_4229_U949 ( .A(DP_OP_169J43_123_4229_n1252), .B(
DP_OP_169J43_123_4229_n1242), .C(DP_OP_169J43_123_4229_n1249), .D(
DP_OP_169J43_123_4229_n1239), .ICI(DP_OP_169J43_123_4229_n1245), .S(
DP_OP_169J43_123_4229_n1236), .ICO(DP_OP_169J43_123_4229_n1234), .CO(
DP_OP_169J43_123_4229_n1235) );
CMPR42X1TS DP_OP_169J43_123_4229_U947 ( .A(DP_OP_169J43_123_4229_n1579), .B(
DP_OP_169J43_123_4229_n1233), .C(DP_OP_169J43_123_4229_n1607), .D(
DP_OP_169J43_123_4229_n1635), .ICI(DP_OP_169J43_123_4229_n1746), .S(
DP_OP_169J43_123_4229_n1231), .ICO(DP_OP_169J43_123_4229_n1229), .CO(
DP_OP_169J43_123_4229_n1230) );
CMPR42X1TS DP_OP_169J43_123_4229_U946 ( .A(DP_OP_169J43_123_4229_n1719), .B(
DP_OP_169J43_123_4229_n1691), .C(DP_OP_169J43_123_4229_n1663), .D(
DP_OP_169J43_123_4229_n1240), .ICI(DP_OP_169J43_123_4229_n1241), .S(
DP_OP_169J43_123_4229_n1228), .ICO(DP_OP_169J43_123_4229_n1226), .CO(
DP_OP_169J43_123_4229_n1227) );
CMPR42X1TS DP_OP_169J43_123_4229_U942 ( .A(DP_OP_169J43_123_4229_n1578), .B(
DP_OP_169J43_123_4229_n1634), .C(DP_OP_169J43_123_4229_n1718), .D(
DP_OP_169J43_123_4229_n1220), .ICI(DP_OP_169J43_123_4229_n1226), .S(
DP_OP_169J43_123_4229_n1218), .ICO(DP_OP_169J43_123_4229_n1216), .CO(
DP_OP_169J43_123_4229_n1217) );
CMPR42X1TS DP_OP_169J43_123_4229_U941 ( .A(DP_OP_169J43_123_4229_n1606), .B(
DP_OP_169J43_123_4229_n1662), .C(DP_OP_169J43_123_4229_n1690), .D(
DP_OP_169J43_123_4229_n1229), .ICI(DP_OP_169J43_123_4229_n1745), .S(
DP_OP_169J43_123_4229_n1215), .ICO(DP_OP_169J43_123_4229_n1213), .CO(
DP_OP_169J43_123_4229_n1214) );
CMPR42X1TS DP_OP_169J43_123_4229_U940 ( .A(DP_OP_169J43_123_4229_n1230), .B(
DP_OP_169J43_123_4229_n1218), .C(DP_OP_169J43_123_4229_n1227), .D(
DP_OP_169J43_123_4229_n1215), .ICI(DP_OP_169J43_123_4229_n1223), .S(
DP_OP_169J43_123_4229_n1212), .ICO(DP_OP_169J43_123_4229_n1210), .CO(
DP_OP_169J43_123_4229_n1211) );
CMPR42X1TS DP_OP_169J43_123_4229_U939 ( .A(DP_OP_169J43_123_4229_n1493), .B(
DP_OP_169J43_123_4229_n1521), .C(DP_OP_169J43_123_4229_n1221), .D(
DP_OP_169J43_123_4229_n1549), .ICI(DP_OP_169J43_123_4229_n1577), .S(
DP_OP_169J43_123_4229_n1209), .ICO(DP_OP_169J43_123_4229_n1207), .CO(
DP_OP_169J43_123_4229_n1208) );
CMPR42X1TS DP_OP_169J43_123_4229_U938 ( .A(DP_OP_169J43_123_4229_n1219), .B(
DP_OP_169J43_123_4229_n1689), .C(DP_OP_169J43_123_4229_n1633), .D(
DP_OP_169J43_123_4229_n1717), .ICI(DP_OP_169J43_123_4229_n1213), .S(
DP_OP_169J43_123_4229_n1206), .ICO(DP_OP_169J43_123_4229_n1204), .CO(
DP_OP_169J43_123_4229_n1205) );
CMPR42X1TS DP_OP_169J43_123_4229_U937 ( .A(DP_OP_169J43_123_4229_n1605), .B(
DP_OP_169J43_123_4229_n1661), .C(DP_OP_169J43_123_4229_n1744), .D(
DP_OP_169J43_123_4229_n1209), .ICI(DP_OP_169J43_123_4229_n1216), .S(
DP_OP_169J43_123_4229_n1203), .ICO(DP_OP_169J43_123_4229_n1201), .CO(
DP_OP_169J43_123_4229_n1202) );
CMPR42X1TS DP_OP_169J43_123_4229_U934 ( .A(DP_OP_169J43_123_4229_n1197), .B(
DP_OP_169J43_123_4229_n1520), .C(DP_OP_169J43_123_4229_n1207), .D(
DP_OP_169J43_123_4229_n1548), .ICI(DP_OP_169J43_123_4229_n1660), .S(
DP_OP_169J43_123_4229_n1195), .ICO(DP_OP_169J43_123_4229_n1193), .CO(
DP_OP_169J43_123_4229_n1194) );
CMPR42X1TS DP_OP_169J43_123_4229_U933 ( .A(DP_OP_169J43_123_4229_n1604), .B(
DP_OP_169J43_123_4229_n1576), .C(DP_OP_169J43_123_4229_n1688), .D(
DP_OP_169J43_123_4229_n1632), .ICI(DP_OP_169J43_123_4229_n1201), .S(
DP_OP_169J43_123_4229_n1192), .ICO(DP_OP_169J43_123_4229_n1190), .CO(
DP_OP_169J43_123_4229_n1191) );
CMPR42X1TS DP_OP_169J43_123_4229_U932 ( .A(DP_OP_169J43_123_4229_n1208), .B(
DP_OP_169J43_123_4229_n1716), .C(DP_OP_169J43_123_4229_n1743), .D(
DP_OP_169J43_123_4229_n1204), .ICI(DP_OP_169J43_123_4229_n1195), .S(
DP_OP_169J43_123_4229_n1189), .ICO(DP_OP_169J43_123_4229_n1187), .CO(
DP_OP_169J43_123_4229_n1188) );
CMPR42X1TS DP_OP_169J43_123_4229_U931 ( .A(DP_OP_169J43_123_4229_n1205), .B(
DP_OP_169J43_123_4229_n1192), .C(DP_OP_169J43_123_4229_n1202), .D(
DP_OP_169J43_123_4229_n1189), .ICI(DP_OP_169J43_123_4229_n1198), .S(
DP_OP_169J43_123_4229_n1186), .ICO(DP_OP_169J43_123_4229_n1184), .CO(
DP_OP_169J43_123_4229_n1185) );
CMPR42X1TS DP_OP_169J43_123_4229_U929 ( .A(DP_OP_169J43_123_4229_n1519), .B(
DP_OP_169J43_123_4229_n1183), .C(DP_OP_169J43_123_4229_n1547), .D(
DP_OP_169J43_123_4229_n1575), .ICI(DP_OP_169J43_123_4229_n1687), .S(
DP_OP_169J43_123_4229_n1181), .ICO(DP_OP_169J43_123_4229_n1179), .CO(
DP_OP_169J43_123_4229_n1180) );
CMPR42X1TS DP_OP_169J43_123_4229_U928 ( .A(DP_OP_169J43_123_4229_n1659), .B(
DP_OP_169J43_123_4229_n1631), .C(DP_OP_169J43_123_4229_n1603), .D(
DP_OP_169J43_123_4229_n1193), .ICI(DP_OP_169J43_123_4229_n1187), .S(
DP_OP_169J43_123_4229_n1178), .ICO(DP_OP_169J43_123_4229_n1176), .CO(
DP_OP_169J43_123_4229_n1177) );
CMPR42X1TS DP_OP_169J43_123_4229_U927 ( .A(DP_OP_169J43_123_4229_n1742), .B(
DP_OP_169J43_123_4229_n1715), .C(DP_OP_169J43_123_4229_n1190), .D(
DP_OP_169J43_123_4229_n1194), .ICI(DP_OP_169J43_123_4229_n1181), .S(
DP_OP_169J43_123_4229_n1175), .ICO(DP_OP_169J43_123_4229_n1173), .CO(
DP_OP_169J43_123_4229_n1174) );
CMPR42X1TS DP_OP_169J43_123_4229_U923 ( .A(DP_OP_169J43_123_4229_n1518), .B(
DP_OP_169J43_123_4229_n1574), .C(DP_OP_169J43_123_4229_n1602), .D(
DP_OP_169J43_123_4229_n1167), .ICI(DP_OP_169J43_123_4229_n1176), .S(
DP_OP_169J43_123_4229_n1165), .ICO(DP_OP_169J43_123_4229_n1163), .CO(
DP_OP_169J43_123_4229_n1164) );
CMPR42X1TS DP_OP_169J43_123_4229_U922 ( .A(DP_OP_169J43_123_4229_n1546), .B(
DP_OP_169J43_123_4229_n1630), .C(DP_OP_169J43_123_4229_n1658), .D(
DP_OP_169J43_123_4229_n1179), .ICI(DP_OP_169J43_123_4229_n1741), .S(
DP_OP_169J43_123_4229_n1162), .ICO(DP_OP_169J43_123_4229_n1160), .CO(
DP_OP_169J43_123_4229_n1161) );
CMPR42X1TS DP_OP_169J43_123_4229_U920 ( .A(DP_OP_169J43_123_4229_n1177), .B(
DP_OP_169J43_123_4229_n1162), .C(DP_OP_169J43_123_4229_n1174), .D(
DP_OP_169J43_123_4229_n1170), .ICI(DP_OP_169J43_123_4229_n1159), .S(
DP_OP_169J43_123_4229_n1156), .ICO(DP_OP_169J43_123_4229_n1154), .CO(
DP_OP_169J43_123_4229_n1155) );
CMPR42X1TS DP_OP_169J43_123_4229_U919 ( .A(DP_OP_169J43_123_4229_n1433), .B(
DP_OP_169J43_123_4229_n1461), .C(DP_OP_169J43_123_4229_n1168), .D(
DP_OP_169J43_123_4229_n1489), .ICI(DP_OP_169J43_123_4229_n1517), .S(
DP_OP_169J43_123_4229_n1153), .ICO(DP_OP_169J43_123_4229_n1151), .CO(
DP_OP_169J43_123_4229_n1152) );
CMPR42X1TS DP_OP_169J43_123_4229_U918 ( .A(DP_OP_169J43_123_4229_n1166), .B(
DP_OP_169J43_123_4229_n1629), .C(DP_OP_169J43_123_4229_n1601), .D(
DP_OP_169J43_123_4229_n1657), .ICI(DP_OP_169J43_123_4229_n1160), .S(
DP_OP_169J43_123_4229_n1150), .ICO(DP_OP_169J43_123_4229_n1148), .CO(
DP_OP_169J43_123_4229_n1149) );
CMPR42X1TS DP_OP_169J43_123_4229_U917 ( .A(DP_OP_169J43_123_4229_n1545), .B(
DP_OP_169J43_123_4229_n1573), .C(DP_OP_169J43_123_4229_n1713), .D(
DP_OP_169J43_123_4229_n1740), .ICI(DP_OP_169J43_123_4229_n1163), .S(
DP_OP_169J43_123_4229_n1147), .ICO(DP_OP_169J43_123_4229_n1145), .CO(
DP_OP_169J43_123_4229_n1146) );
CMPR42X1TS DP_OP_169J43_123_4229_U916 ( .A(DP_OP_169J43_123_4229_n1685), .B(
DP_OP_169J43_123_4229_n1153), .C(DP_OP_169J43_123_4229_n1164), .D(
DP_OP_169J43_123_4229_n1161), .ICI(DP_OP_169J43_123_4229_n1157), .S(
DP_OP_169J43_123_4229_n1144), .ICO(DP_OP_169J43_123_4229_n1142), .CO(
DP_OP_169J43_123_4229_n1143) );
CMPR42X1TS DP_OP_169J43_123_4229_U913 ( .A(DP_OP_169J43_123_4229_n1138), .B(
DP_OP_169J43_123_4229_n1460), .C(DP_OP_169J43_123_4229_n1151), .D(
DP_OP_169J43_123_4229_n1488), .ICI(DP_OP_169J43_123_4229_n1600), .S(
DP_OP_169J43_123_4229_n1136), .ICO(DP_OP_169J43_123_4229_n1134), .CO(
DP_OP_169J43_123_4229_n1135) );
CMPR42X1TS DP_OP_169J43_123_4229_U912 ( .A(DP_OP_169J43_123_4229_n1544), .B(
DP_OP_169J43_123_4229_n1516), .C(DP_OP_169J43_123_4229_n1628), .D(
DP_OP_169J43_123_4229_n1572), .ICI(DP_OP_169J43_123_4229_n1145), .S(
DP_OP_169J43_123_4229_n1133), .ICO(DP_OP_169J43_123_4229_n1131), .CO(
DP_OP_169J43_123_4229_n1132) );
CMPR42X1TS DP_OP_169J43_123_4229_U911 ( .A(DP_OP_169J43_123_4229_n1152), .B(
DP_OP_169J43_123_4229_n1739), .C(DP_OP_169J43_123_4229_n1712), .D(
DP_OP_169J43_123_4229_n1148), .ICI(DP_OP_169J43_123_4229_n1136), .S(
DP_OP_169J43_123_4229_n1130), .ICO(DP_OP_169J43_123_4229_n1128), .CO(
DP_OP_169J43_123_4229_n1129) );
CMPR42X1TS DP_OP_169J43_123_4229_U910 ( .A(DP_OP_169J43_123_4229_n1656), .B(
DP_OP_169J43_123_4229_n1684), .C(DP_OP_169J43_123_4229_n1149), .D(
DP_OP_169J43_123_4229_n1133), .ICI(DP_OP_169J43_123_4229_n1146), .S(
DP_OP_169J43_123_4229_n1127), .ICO(DP_OP_169J43_123_4229_n1125), .CO(
DP_OP_169J43_123_4229_n1126) );
CMPR42X1TS DP_OP_169J43_123_4229_U907 ( .A(DP_OP_169J43_123_4229_n1459), .B(
DP_OP_169J43_123_4229_n1121), .C(DP_OP_169J43_123_4229_n1487), .D(
DP_OP_169J43_123_4229_n1515), .ICI(DP_OP_169J43_123_4229_n1627), .S(
DP_OP_169J43_123_4229_n1119), .ICO(DP_OP_169J43_123_4229_n1117), .CO(
DP_OP_169J43_123_4229_n1118) );
CMPR42X1TS DP_OP_169J43_123_4229_U906 ( .A(DP_OP_169J43_123_4229_n1571), .B(
DP_OP_169J43_123_4229_n1543), .C(DP_OP_169J43_123_4229_n1599), .D(
DP_OP_169J43_123_4229_n1134), .ICI(DP_OP_169J43_123_4229_n1128), .S(
DP_OP_169J43_123_4229_n1116), .ICO(DP_OP_169J43_123_4229_n1114), .CO(
DP_OP_169J43_123_4229_n1115) );
CMPR42X1TS DP_OP_169J43_123_4229_U905 ( .A(DP_OP_169J43_123_4229_n1738), .B(
DP_OP_169J43_123_4229_n1655), .C(DP_OP_169J43_123_4229_n1683), .D(
DP_OP_169J43_123_4229_n1131), .ICI(DP_OP_169J43_123_4229_n1119), .S(
DP_OP_169J43_123_4229_n1113), .ICO(DP_OP_169J43_123_4229_n1111), .CO(
DP_OP_169J43_123_4229_n1112) );
CMPR42X1TS DP_OP_169J43_123_4229_U904 ( .A(DP_OP_169J43_123_4229_n1711), .B(
DP_OP_169J43_123_4229_n1135), .C(DP_OP_169J43_123_4229_n1132), .D(
DP_OP_169J43_123_4229_n1116), .ICI(DP_OP_169J43_123_4229_n1129), .S(
DP_OP_169J43_123_4229_n1110), .ICO(DP_OP_169J43_123_4229_n1108), .CO(
DP_OP_169J43_123_4229_n1109) );
CMPR42X1TS DP_OP_169J43_123_4229_U900 ( .A(DP_OP_169J43_123_4229_n1458), .B(
DP_OP_169J43_123_4229_n1514), .C(DP_OP_169J43_123_4229_n1598), .D(
DP_OP_169J43_123_4229_n1102), .ICI(DP_OP_169J43_123_4229_n1114), .S(
DP_OP_169J43_123_4229_n1100), .ICO(DP_OP_169J43_123_4229_n1098), .CO(
DP_OP_169J43_123_4229_n1099) );
CMPR42X1TS DP_OP_169J43_123_4229_U899 ( .A(DP_OP_169J43_123_4229_n1486), .B(
DP_OP_169J43_123_4229_n1570), .C(DP_OP_169J43_123_4229_n1542), .D(
DP_OP_169J43_123_4229_n1117), .ICI(DP_OP_169J43_123_4229_n1111), .S(
DP_OP_169J43_123_4229_n1097), .ICO(DP_OP_169J43_123_4229_n1095), .CO(
DP_OP_169J43_123_4229_n1096) );
CMPR42X1TS DP_OP_169J43_123_4229_U898 ( .A(DP_OP_169J43_123_4229_n1626), .B(
DP_OP_169J43_123_4229_n1654), .C(DP_OP_169J43_123_4229_n1682), .D(
DP_OP_169J43_123_4229_n1710), .ICI(DP_OP_169J43_123_4229_n1118), .S(
DP_OP_169J43_123_4229_n1094), .ICO(DP_OP_169J43_123_4229_n1092), .CO(
DP_OP_169J43_123_4229_n1093) );
CMPR42X1TS DP_OP_169J43_123_4229_U897 ( .A(DP_OP_169J43_123_4229_n1737), .B(
DP_OP_169J43_123_4229_n1100), .C(DP_OP_169J43_123_4229_n1115), .D(
DP_OP_169J43_123_4229_n1097), .ICI(DP_OP_169J43_123_4229_n1112), .S(
DP_OP_169J43_123_4229_n1091), .ICO(DP_OP_169J43_123_4229_n1089), .CO(
DP_OP_169J43_123_4229_n1090) );
CMPR42X1TS DP_OP_169J43_123_4229_U896 ( .A(DP_OP_169J43_123_4229_n1108), .B(
DP_OP_169J43_123_4229_n1094), .C(DP_OP_169J43_123_4229_n1109), .D(
DP_OP_169J43_123_4229_n1091), .ICI(DP_OP_169J43_123_4229_n1105), .S(
DP_OP_169J43_123_4229_n1088), .ICO(DP_OP_169J43_123_4229_n1086), .CO(
DP_OP_169J43_123_4229_n1087) );
CMPR42X1TS DP_OP_169J43_123_4229_U895 ( .A(DP_OP_169J43_123_4229_n1373), .B(
DP_OP_169J43_123_4229_n1401), .C(DP_OP_169J43_123_4229_n1103), .D(
DP_OP_169J43_123_4229_n1429), .ICI(DP_OP_169J43_123_4229_n1457), .S(
DP_OP_169J43_123_4229_n1085), .ICO(DP_OP_169J43_123_4229_n1083), .CO(
DP_OP_169J43_123_4229_n1084) );
CMPR42X1TS DP_OP_169J43_123_4229_U893 ( .A(DP_OP_169J43_123_4229_n1485), .B(
DP_OP_169J43_123_4229_n1569), .C(DP_OP_169J43_123_4229_n1653), .D(
DP_OP_169J43_123_4229_n1625), .ICI(DP_OP_169J43_123_4229_n1095), .S(
DP_OP_169J43_123_4229_n1079), .ICO(DP_OP_169J43_123_4229_n1077), .CO(
DP_OP_169J43_123_4229_n1078) );
CMPR42X1TS DP_OP_169J43_123_4229_U892 ( .A(DP_OP_169J43_123_4229_n1736), .B(
DP_OP_169J43_123_4229_n1681), .C(DP_OP_169J43_123_4229_n1085), .D(
DP_OP_169J43_123_4229_n1098), .ICI(DP_OP_169J43_123_4229_n1099), .S(
DP_OP_169J43_123_4229_n1076), .ICO(DP_OP_169J43_123_4229_n1074), .CO(
DP_OP_169J43_123_4229_n1075) );
CMPR42X1TS DP_OP_169J43_123_4229_U891 ( .A(DP_OP_169J43_123_4229_n1709), .B(
DP_OP_169J43_123_4229_n1096), .C(DP_OP_169J43_123_4229_n1082), .D(
DP_OP_169J43_123_4229_n1079), .ICI(DP_OP_169J43_123_4229_n1093), .S(
DP_OP_169J43_123_4229_n1073), .ICO(DP_OP_169J43_123_4229_n1071), .CO(
DP_OP_169J43_123_4229_n1072) );
CMPR42X1TS DP_OP_169J43_123_4229_U888 ( .A(DP_OP_169J43_123_4229_n1067), .B(
DP_OP_169J43_123_4229_n1400), .C(DP_OP_169J43_123_4229_n1083), .D(
DP_OP_169J43_123_4229_n1428), .ICI(DP_OP_169J43_123_4229_n1540), .S(
DP_OP_169J43_123_4229_n1065), .ICO(DP_OP_169J43_123_4229_n1063), .CO(
DP_OP_169J43_123_4229_n1064) );
CMPR42X1TS DP_OP_169J43_123_4229_U887 ( .A(DP_OP_169J43_123_4229_n1484), .B(
DP_OP_169J43_123_4229_n1456), .C(DP_OP_169J43_123_4229_n1568), .D(
DP_OP_169J43_123_4229_n1512), .ICI(DP_OP_169J43_123_4229_n1077), .S(
DP_OP_169J43_123_4229_n1062), .ICO(DP_OP_169J43_123_4229_n1060), .CO(
DP_OP_169J43_123_4229_n1061) );
CMPR42X1TS DP_OP_169J43_123_4229_U886 ( .A(DP_OP_169J43_123_4229_n1084), .B(
DP_OP_169J43_123_4229_n1680), .C(DP_OP_169J43_123_4229_n1708), .D(
DP_OP_169J43_123_4229_n1080), .ICI(DP_OP_169J43_123_4229_n1065), .S(
DP_OP_169J43_123_4229_n1059), .ICO(DP_OP_169J43_123_4229_n1057), .CO(
DP_OP_169J43_123_4229_n1058) );
CMPR42X1TS DP_OP_169J43_123_4229_U885 ( .A(DP_OP_169J43_123_4229_n1596), .B(
DP_OP_169J43_123_4229_n1735), .C(DP_OP_169J43_123_4229_n1624), .D(
DP_OP_169J43_123_4229_n1652), .ICI(DP_OP_169J43_123_4229_n1074), .S(
DP_OP_169J43_123_4229_n1056), .ICO(DP_OP_169J43_123_4229_n1054), .CO(
DP_OP_169J43_123_4229_n1055) );
CMPR42X1TS DP_OP_169J43_123_4229_U881 ( .A(DP_OP_169J43_123_4229_n1399), .B(
DP_OP_169J43_123_4229_n1047), .C(DP_OP_169J43_123_4229_n1427), .D(
DP_OP_169J43_123_4229_n1455), .ICI(DP_OP_169J43_123_4229_n1567), .S(
DP_OP_169J43_123_4229_n1045), .ICO(DP_OP_169J43_123_4229_n1043), .CO(
DP_OP_169J43_123_4229_n1044) );
CMPR42X1TS DP_OP_169J43_123_4229_U880 ( .A(DP_OP_169J43_123_4229_n1539), .B(
DP_OP_169J43_123_4229_n1511), .C(DP_OP_169J43_123_4229_n1734), .D(
DP_OP_169J43_123_4229_n1063), .ICI(DP_OP_169J43_123_4229_n1057), .S(
DP_OP_169J43_123_4229_n1042), .ICO(DP_OP_169J43_123_4229_n1040), .CO(
DP_OP_169J43_123_4229_n1041) );
CMPR42X1TS DP_OP_169J43_123_4229_U879 ( .A(DP_OP_169J43_123_4229_n1483), .B(
DP_OP_169J43_123_4229_n1595), .C(DP_OP_169J43_123_4229_n1651), .D(
DP_OP_169J43_123_4229_n1707), .ICI(DP_OP_169J43_123_4229_n1054), .S(
DP_OP_169J43_123_4229_n1039), .ICO(DP_OP_169J43_123_4229_n1037), .CO(
DP_OP_169J43_123_4229_n1038) );
CMPR42X1TS DP_OP_169J43_123_4229_U878 ( .A(DP_OP_169J43_123_4229_n1679), .B(
DP_OP_169J43_123_4229_n1623), .C(DP_OP_169J43_123_4229_n1060), .D(
DP_OP_169J43_123_4229_n1064), .ICI(DP_OP_169J43_123_4229_n1045), .S(
DP_OP_169J43_123_4229_n1036), .ICO(DP_OP_169J43_123_4229_n1034), .CO(
DP_OP_169J43_123_4229_n1035) );
CMPR42X1TS DP_OP_169J43_123_4229_U873 ( .A(DP_OP_169J43_123_4229_n1046), .B(
DP_OP_169J43_123_4229_n1026), .C(DP_OP_169J43_123_4229_n1398), .D(
DP_OP_169J43_123_4229_n1454), .ICI(DP_OP_169J43_123_4229_n1040), .S(
DP_OP_169J43_123_4229_n1024), .ICO(DP_OP_169J43_123_4229_n1022), .CO(
DP_OP_169J43_123_4229_n1023) );
CMPR42X1TS DP_OP_169J43_123_4229_U870 ( .A(DP_OP_169J43_123_4229_n1706), .B(
DP_OP_169J43_123_4229_n1566), .C(DP_OP_169J43_123_4229_n1678), .D(
DP_OP_169J43_123_4229_n1034), .ICI(DP_OP_169J43_123_4229_n1044), .S(
DP_OP_169J43_123_4229_n1015), .ICO(DP_OP_169J43_123_4229_n1013), .CO(
DP_OP_169J43_123_4229_n1014) );
CMPR42X1TS DP_OP_169J43_123_4229_U868 ( .A(DP_OP_169J43_123_4229_n1018), .B(
DP_OP_169J43_123_4229_n1015), .C(DP_OP_169J43_123_4229_n1032), .D(
DP_OP_169J43_123_4229_n1012), .ICI(DP_OP_169J43_123_4229_n1028), .S(
DP_OP_169J43_123_4229_n1009), .ICO(DP_OP_169J43_123_4229_n1007), .CO(
DP_OP_169J43_123_4229_n1008) );
CMPR42X1TS DP_OP_169J43_123_4229_U865 ( .A(DP_OP_169J43_123_4229_n1025), .B(
DP_OP_169J43_123_4229_n1004), .C(DP_OP_169J43_123_4229_n1397), .D(
DP_OP_169J43_123_4229_n1425), .ICI(DP_OP_169J43_123_4229_n1019), .S(
DP_OP_169J43_123_4229_n1002), .ICO(DP_OP_169J43_123_4229_n1000), .CO(
DP_OP_169J43_123_4229_n1001) );
CMPR42X1TS DP_OP_169J43_123_4229_U863 ( .A(DP_OP_169J43_123_4229_n1453), .B(
DP_OP_169J43_123_4229_n1509), .C(DP_OP_169J43_123_4229_n1621), .D(
DP_OP_169J43_123_4229_n1677), .ICI(DP_OP_169J43_123_4229_n1013), .S(
DP_OP_169J43_123_4229_n996), .ICO(DP_OP_169J43_123_4229_n994), .CO(
DP_OP_169J43_123_4229_n995) );
CMPR42X1TS DP_OP_169J43_123_4229_U862 ( .A(DP_OP_169J43_123_4229_n1649), .B(
DP_OP_169J43_123_4229_n1565), .C(DP_OP_169J43_123_4229_n1593), .D(
DP_OP_169J43_123_4229_n1023), .ICI(DP_OP_169J43_123_4229_n1002), .S(
DP_OP_169J43_123_4229_n993), .ICO(DP_OP_169J43_123_4229_n991), .CO(
DP_OP_169J43_123_4229_n992) );
CMPR42X1TS DP_OP_169J43_123_4229_U860 ( .A(DP_OP_169J43_123_4229_n1014), .B(
DP_OP_169J43_123_4229_n1010), .C(DP_OP_169J43_123_4229_n1011), .D(
DP_OP_169J43_123_4229_n990), .ICI(DP_OP_169J43_123_4229_n1007), .S(
DP_OP_169J43_123_4229_n987), .ICO(DP_OP_169J43_123_4229_n985), .CO(
DP_OP_169J43_123_4229_n986) );
CMPR42X1TS DP_OP_169J43_123_4229_U858 ( .A(DP_OP_169J43_123_4229_n984), .B(
DP_OP_169J43_123_4229_n1003), .C(DP_OP_169J43_123_4229_n1368), .D(
DP_OP_169J43_123_4229_n1424), .ICI(DP_OP_169J43_123_4229_n1536), .S(
DP_OP_169J43_123_4229_n982), .ICO(DP_OP_169J43_123_4229_n980), .CO(
DP_OP_169J43_123_4229_n981) );
CMPR42X1TS DP_OP_169J43_123_4229_U856 ( .A(DP_OP_169J43_123_4229_n1000), .B(
DP_OP_169J43_123_4229_n1592), .C(DP_OP_169J43_123_4229_n1564), .D(
DP_OP_169J43_123_4229_n1620), .ICI(DP_OP_169J43_123_4229_n982), .S(
DP_OP_169J43_123_4229_n976), .ICO(DP_OP_169J43_123_4229_n974), .CO(
DP_OP_169J43_123_4229_n975) );
CMPR42X1TS DP_OP_169J43_123_4229_U854 ( .A(DP_OP_169J43_123_4229_n998), .B(
DP_OP_169J43_123_4229_n979), .C(DP_OP_169J43_123_4229_n995), .D(
DP_OP_169J43_123_4229_n976), .ICI(DP_OP_169J43_123_4229_n988), .S(
DP_OP_169J43_123_4229_n970), .ICO(DP_OP_169J43_123_4229_n968), .CO(
DP_OP_169J43_123_4229_n969) );
CMPR42X1TS DP_OP_169J43_123_4229_U853 ( .A(DP_OP_169J43_123_4229_n992), .B(
DP_OP_169J43_123_4229_n973), .C(DP_OP_169J43_123_4229_n989), .D(
DP_OP_169J43_123_4229_n970), .ICI(DP_OP_169J43_123_4229_n985), .S(
DP_OP_169J43_123_4229_n967), .ICO(DP_OP_169J43_123_4229_n965), .CO(
DP_OP_169J43_123_4229_n966) );
CMPR42X1TS DP_OP_169J43_123_4229_U851 ( .A(DP_OP_169J43_123_4229_n964), .B(
DP_OP_169J43_123_4229_n983), .C(DP_OP_169J43_123_4229_n1367), .D(
DP_OP_169J43_123_4229_n1395), .ICI(DP_OP_169J43_123_4229_n1479), .S(
DP_OP_169J43_123_4229_n962), .ICO(DP_OP_169J43_123_4229_n960), .CO(
DP_OP_169J43_123_4229_n961) );
CMPR42X1TS DP_OP_169J43_123_4229_U850 ( .A(DP_OP_169J43_123_4229_n1423), .B(
DP_OP_169J43_123_4229_n1675), .C(DP_OP_169J43_123_4229_n1507), .D(
DP_OP_169J43_123_4229_n980), .ICI(DP_OP_169J43_123_4229_n981), .S(
DP_OP_169J43_123_4229_n959), .ICO(DP_OP_169J43_123_4229_n957), .CO(
DP_OP_169J43_123_4229_n958) );
CMPR42X1TS DP_OP_169J43_123_4229_U849 ( .A(DP_OP_169J43_123_4229_n1451), .B(
DP_OP_169J43_123_4229_n1647), .C(DP_OP_169J43_123_4229_n1563), .D(
DP_OP_169J43_123_4229_n1619), .ICI(DP_OP_169J43_123_4229_n974), .S(
DP_OP_169J43_123_4229_n956), .ICO(DP_OP_169J43_123_4229_n954), .CO(
DP_OP_169J43_123_4229_n955) );
CMPR42X1TS DP_OP_169J43_123_4229_U848 ( .A(DP_OP_169J43_123_4229_n1591), .B(
DP_OP_169J43_123_4229_n1535), .C(DP_OP_169J43_123_4229_n977), .D(
DP_OP_169J43_123_4229_n971), .ICI(DP_OP_169J43_123_4229_n962), .S(
DP_OP_169J43_123_4229_n953), .ICO(DP_OP_169J43_123_4229_n951), .CO(
DP_OP_169J43_123_4229_n952) );
CMPR42X1TS DP_OP_169J43_123_4229_U846 ( .A(DP_OP_169J43_123_4229_n956), .B(
DP_OP_169J43_123_4229_n968), .C(DP_OP_169J43_123_4229_n969), .D(
DP_OP_169J43_123_4229_n950), .ICI(DP_OP_169J43_123_4229_n965), .S(
DP_OP_169J43_123_4229_n947), .ICO(DP_OP_169J43_123_4229_n945), .CO(
DP_OP_169J43_123_4229_n946) );
CMPR42X1TS DP_OP_169J43_123_4229_U845 ( .A(DP_OP_169J43_123_4229_n1674), .B(
DP_OP_169J43_123_4229_n963), .C(DP_OP_169J43_123_4229_n1339), .D(
DP_OP_169J43_123_4229_n1394), .ICI(DP_OP_169J43_123_4229_n1366), .S(
DP_OP_169J43_123_4229_n944), .ICO(DP_OP_169J43_123_4229_n942), .CO(
DP_OP_169J43_123_4229_n943) );
CMPR42X1TS DP_OP_169J43_123_4229_U844 ( .A(DP_OP_169J43_123_4229_n1478), .B(
DP_OP_169J43_123_4229_n1422), .C(DP_OP_169J43_123_4229_n1450), .D(
DP_OP_169J43_123_4229_n960), .ICI(DP_OP_169J43_123_4229_n954), .S(
DP_OP_169J43_123_4229_n941), .ICO(DP_OP_169J43_123_4229_n939), .CO(
DP_OP_169J43_123_4229_n940) );
CMPR42X1TS DP_OP_169J43_123_4229_U842 ( .A(DP_OP_169J43_123_4229_n1646), .B(
DP_OP_169J43_123_4229_n1534), .C(DP_OP_169J43_123_4229_n1562), .D(
DP_OP_169J43_123_4229_n951), .ICI(DP_OP_169J43_123_4229_n961), .S(
DP_OP_169J43_123_4229_n935), .ICO(DP_OP_169J43_123_4229_n933), .CO(
DP_OP_169J43_123_4229_n934) );
CMPR42X1TS DP_OP_169J43_123_4229_U841 ( .A(DP_OP_169J43_123_4229_n958), .B(
DP_OP_169J43_123_4229_n941), .C(DP_OP_169J43_123_4229_n955), .D(
DP_OP_169J43_123_4229_n938), .ICI(DP_OP_169J43_123_4229_n948), .S(
DP_OP_169J43_123_4229_n932), .ICO(DP_OP_169J43_123_4229_n930), .CO(
DP_OP_169J43_123_4229_n931) );
CMPR42X1TS DP_OP_169J43_123_4229_U836 ( .A(DP_OP_169J43_123_4229_n1449), .B(
DP_OP_169J43_123_4229_n1505), .C(DP_OP_169J43_123_4229_n1561), .D(
DP_OP_169J43_123_4229_n1617), .ICI(DP_OP_169J43_123_4229_n933), .S(
DP_OP_169J43_123_4229_n919), .ICO(DP_OP_169J43_123_4229_n917), .CO(
DP_OP_169J43_123_4229_n918) );
CMPR42X1TS DP_OP_169J43_123_4229_U835 ( .A(DP_OP_169J43_123_4229_n1589), .B(
DP_OP_169J43_123_4229_n1533), .C(DP_OP_169J43_123_4229_n939), .D(
DP_OP_169J43_123_4229_n924), .ICI(DP_OP_169J43_123_4229_n943), .S(
DP_OP_169J43_123_4229_n916), .ICO(DP_OP_169J43_123_4229_n914), .CO(
DP_OP_169J43_123_4229_n915) );
CMPR42X1TS DP_OP_169J43_123_4229_U834 ( .A(DP_OP_169J43_123_4229_n940), .B(
DP_OP_169J43_123_4229_n922), .C(DP_OP_169J43_123_4229_n937), .D(
DP_OP_169J43_123_4229_n919), .ICI(DP_OP_169J43_123_4229_n930), .S(
DP_OP_169J43_123_4229_n913), .ICO(DP_OP_169J43_123_4229_n911), .CO(
DP_OP_169J43_123_4229_n912) );
CMPR42X1TS DP_OP_169J43_123_4229_U833 ( .A(DP_OP_169J43_123_4229_n934), .B(
DP_OP_169J43_123_4229_n916), .C(DP_OP_169J43_123_4229_n931), .D(
DP_OP_169J43_123_4229_n913), .ICI(DP_OP_169J43_123_4229_n927), .S(
DP_OP_169J43_123_4229_n910), .ICO(DP_OP_169J43_123_4229_n908), .CO(
DP_OP_169J43_123_4229_n909) );
CMPR42X1TS DP_OP_169J43_123_4229_U831 ( .A(DP_OP_169J43_123_4229_n1364), .B(
DP_OP_169J43_123_4229_n1392), .C(DP_OP_169J43_123_4229_n1420), .D(
DP_OP_169J43_123_4229_n907), .ICI(DP_OP_169J43_123_4229_n923), .S(
DP_OP_169J43_123_4229_n905), .ICO(DP_OP_169J43_123_4229_n903), .CO(
DP_OP_169J43_123_4229_n904) );
CMPR42X1TS DP_OP_169J43_123_4229_U830 ( .A(DP_OP_169J43_123_4229_n1448), .B(
DP_OP_169J43_123_4229_n1476), .C(DP_OP_169J43_123_4229_n1616), .D(
DP_OP_169J43_123_4229_n1560), .ICI(DP_OP_169J43_123_4229_n917), .S(
DP_OP_169J43_123_4229_n902), .ICO(DP_OP_169J43_123_4229_n900), .CO(
DP_OP_169J43_123_4229_n901) );
CMPR42X1TS DP_OP_169J43_123_4229_U828 ( .A(DP_OP_169J43_123_4229_n921), .B(
DP_OP_169J43_123_4229_n905), .C(DP_OP_169J43_123_4229_n918), .D(
DP_OP_169J43_123_4229_n902), .ICI(DP_OP_169J43_123_4229_n911), .S(
DP_OP_169J43_123_4229_n896), .ICO(DP_OP_169J43_123_4229_n894), .CO(
DP_OP_169J43_123_4229_n895) );
CMPR42X1TS DP_OP_169J43_123_4229_U827 ( .A(DP_OP_169J43_123_4229_n915), .B(
DP_OP_169J43_123_4229_n899), .C(DP_OP_169J43_123_4229_n912), .D(
DP_OP_169J43_123_4229_n896), .ICI(DP_OP_169J43_123_4229_n908), .S(
DP_OP_169J43_123_4229_n893), .ICO(DP_OP_169J43_123_4229_n891), .CO(
DP_OP_169J43_123_4229_n892) );
CMPR42X1TS DP_OP_169J43_123_4229_U825 ( .A(DP_OP_169J43_123_4229_n890), .B(
DP_OP_169J43_123_4229_n1391), .C(DP_OP_169J43_123_4229_n1419), .D(
DP_OP_169J43_123_4229_n1363), .ICI(DP_OP_169J43_123_4229_n903), .S(
DP_OP_169J43_123_4229_n888), .ICO(DP_OP_169J43_123_4229_n886), .CO(
DP_OP_169J43_123_4229_n887) );
CMPR42X1TS DP_OP_169J43_123_4229_U824 ( .A(DP_OP_169J43_123_4229_n1615), .B(
DP_OP_169J43_123_4229_n906), .C(DP_OP_169J43_123_4229_n1447), .D(
DP_OP_169J43_123_4229_n1475), .ICI(DP_OP_169J43_123_4229_n897), .S(
DP_OP_169J43_123_4229_n885), .ICO(DP_OP_169J43_123_4229_n883), .CO(
DP_OP_169J43_123_4229_n884) );
CMPR42X1TS DP_OP_169J43_123_4229_U822 ( .A(DP_OP_169J43_123_4229_n904), .B(
DP_OP_169J43_123_4229_n888), .C(DP_OP_169J43_123_4229_n885), .D(
DP_OP_169J43_123_4229_n901), .ICI(DP_OP_169J43_123_4229_n894), .S(
DP_OP_169J43_123_4229_n879), .ICO(DP_OP_169J43_123_4229_n877), .CO(
DP_OP_169J43_123_4229_n878) );
CMPR42X1TS DP_OP_169J43_123_4229_U820 ( .A(DP_OP_169J43_123_4229_n1614), .B(
DP_OP_169J43_123_4229_n889), .C(DP_OP_169J43_123_4229_n1337), .D(
DP_OP_169J43_123_4229_n1390), .ICI(DP_OP_169J43_123_4229_n1418), .S(
DP_OP_169J43_123_4229_n873), .ICO(DP_OP_169J43_123_4229_n871), .CO(
DP_OP_169J43_123_4229_n872) );
CMPR42X1TS DP_OP_169J43_123_4229_U819 ( .A(DP_OP_169J43_123_4229_n1362), .B(
DP_OP_169J43_123_4229_n1446), .C(DP_OP_169J43_123_4229_n1586), .D(
DP_OP_169J43_123_4229_n1530), .ICI(DP_OP_169J43_123_4229_n880), .S(
DP_OP_169J43_123_4229_n870), .ICO(DP_OP_169J43_123_4229_n868), .CO(
DP_OP_169J43_123_4229_n869) );
CMPR42X1TS DP_OP_169J43_123_4229_U818 ( .A(DP_OP_169J43_123_4229_n1558), .B(
DP_OP_169J43_123_4229_n1474), .C(DP_OP_169J43_123_4229_n886), .D(
DP_OP_169J43_123_4229_n883), .ICI(DP_OP_169J43_123_4229_n887), .S(
DP_OP_169J43_123_4229_n867), .ICO(DP_OP_169J43_123_4229_n865), .CO(
DP_OP_169J43_123_4229_n866) );
CMPR42X1TS DP_OP_169J43_123_4229_U817 ( .A(DP_OP_169J43_123_4229_n1502), .B(
DP_OP_169J43_123_4229_n873), .C(DP_OP_169J43_123_4229_n884), .D(
DP_OP_169J43_123_4229_n870), .ICI(DP_OP_169J43_123_4229_n881), .S(
DP_OP_169J43_123_4229_n864), .ICO(DP_OP_169J43_123_4229_n862), .CO(
DP_OP_169J43_123_4229_n863) );
CMPR42X1TS DP_OP_169J43_123_4229_U816 ( .A(DP_OP_169J43_123_4229_n867), .B(
DP_OP_169J43_123_4229_n877), .C(DP_OP_169J43_123_4229_n878), .D(
DP_OP_169J43_123_4229_n864), .ICI(DP_OP_169J43_123_4229_n874), .S(
DP_OP_169J43_123_4229_n861), .ICO(DP_OP_169J43_123_4229_n859), .CO(
DP_OP_169J43_123_4229_n860) );
CMPR42X1TS DP_OP_169J43_123_4229_U813 ( .A(DP_OP_169J43_123_4229_n1585), .B(
DP_OP_169J43_123_4229_n871), .C(DP_OP_169J43_123_4229_n1417), .D(
DP_OP_169J43_123_4229_n1445), .ICI(DP_OP_169J43_123_4229_n865), .S(
DP_OP_169J43_123_4229_n854), .ICO(DP_OP_169J43_123_4229_n852), .CO(
DP_OP_169J43_123_4229_n853) );
CMPR42X1TS DP_OP_169J43_123_4229_U811 ( .A(DP_OP_169J43_123_4229_n1501), .B(
DP_OP_169J43_123_4229_n868), .C(DP_OP_169J43_123_4229_n854), .D(
DP_OP_169J43_123_4229_n869), .ICI(DP_OP_169J43_123_4229_n866), .S(
DP_OP_169J43_123_4229_n848), .ICO(DP_OP_169J43_123_4229_n846), .CO(
DP_OP_169J43_123_4229_n847) );
CMPR42X1TS DP_OP_169J43_123_4229_U810 ( .A(DP_OP_169J43_123_4229_n851), .B(
DP_OP_169J43_123_4229_n862), .C(DP_OP_169J43_123_4229_n863), .D(
DP_OP_169J43_123_4229_n848), .ICI(DP_OP_169J43_123_4229_n859), .S(
DP_OP_169J43_123_4229_n845), .ICO(DP_OP_169J43_123_4229_n843), .CO(
DP_OP_169J43_123_4229_n844) );
CMPR42X1TS DP_OP_169J43_123_4229_U808 ( .A(DP_OP_169J43_123_4229_n1360), .B(
DP_OP_169J43_123_4229_n1388), .C(DP_OP_169J43_123_4229_n842), .D(
DP_OP_169J43_123_4229_n1556), .ICI(DP_OP_169J43_123_4229_n849), .S(
DP_OP_169J43_123_4229_n840), .ICO(DP_OP_169J43_123_4229_n838), .CO(
DP_OP_169J43_123_4229_n839) );
CMPR42X1TS DP_OP_169J43_123_4229_U807 ( .A(DP_OP_169J43_123_4229_n1416), .B(
DP_OP_169J43_123_4229_n1528), .C(DP_OP_169J43_123_4229_n1500), .D(
DP_OP_169J43_123_4229_n855), .ICI(DP_OP_169J43_123_4229_n852), .S(
DP_OP_169J43_123_4229_n837), .ICO(DP_OP_169J43_123_4229_n835), .CO(
DP_OP_169J43_123_4229_n836) );
CMPR42X1TS DP_OP_169J43_123_4229_U803 ( .A(DP_OP_169J43_123_4229_n828), .B(
DP_OP_169J43_123_4229_n1359), .C(DP_OP_169J43_123_4229_n1555), .D(
DP_OP_169J43_123_4229_n1387), .ICI(DP_OP_169J43_123_4229_n838), .S(
DP_OP_169J43_123_4229_n826), .ICO(DP_OP_169J43_123_4229_n824), .CO(
DP_OP_169J43_123_4229_n825) );
CMPR42X1TS DP_OP_169J43_123_4229_U802 ( .A(DP_OP_169J43_123_4229_n841), .B(
DP_OP_169J43_123_4229_n1471), .C(DP_OP_169J43_123_4229_n1527), .D(
DP_OP_169J43_123_4229_n1499), .ICI(DP_OP_169J43_123_4229_n835), .S(
DP_OP_169J43_123_4229_n823), .ICO(DP_OP_169J43_123_4229_n821), .CO(
DP_OP_169J43_123_4229_n822) );
CMPR42X1TS DP_OP_169J43_123_4229_U801 ( .A(DP_OP_169J43_123_4229_n1443), .B(
DP_OP_169J43_123_4229_n1415), .C(DP_OP_169J43_123_4229_n839), .D(
DP_OP_169J43_123_4229_n826), .ICI(DP_OP_169J43_123_4229_n836), .S(
DP_OP_169J43_123_4229_n820), .ICO(DP_OP_169J43_123_4229_n818), .CO(
DP_OP_169J43_123_4229_n819) );
CMPR42X1TS DP_OP_169J43_123_4229_U799 ( .A(DP_OP_169J43_123_4229_n1554), .B(
DP_OP_169J43_123_4229_n827), .C(DP_OP_169J43_123_4229_n1335), .D(
DP_OP_169J43_123_4229_n1358), .ICI(DP_OP_169J43_123_4229_n1526), .S(
DP_OP_169J43_123_4229_n814), .ICO(DP_OP_169J43_123_4229_n812), .CO(
DP_OP_169J43_123_4229_n813) );
CMPR42X1TS DP_OP_169J43_123_4229_U798 ( .A(DP_OP_169J43_123_4229_n1386), .B(
DP_OP_169J43_123_4229_n1414), .C(DP_OP_169J43_123_4229_n1498), .D(
DP_OP_169J43_123_4229_n824), .ICI(DP_OP_169J43_123_4229_n814), .S(
DP_OP_169J43_123_4229_n811), .ICO(DP_OP_169J43_123_4229_n809), .CO(
DP_OP_169J43_123_4229_n810) );
CMPR42X1TS DP_OP_169J43_123_4229_U792 ( .A(DP_OP_169J43_123_4229_n1441), .B(
DP_OP_169J43_123_4229_n1385), .C(DP_OP_169J43_123_4229_n800), .D(
DP_OP_169J43_123_4229_n809), .ICI(DP_OP_169J43_123_4229_n806), .S(
DP_OP_169J43_123_4229_n795), .ICO(DP_OP_169J43_123_4229_n793), .CO(
DP_OP_169J43_123_4229_n794) );
CMPR42X1TS DP_OP_169J43_123_4229_U791 ( .A(DP_OP_169J43_123_4229_n810), .B(
DP_OP_169J43_123_4229_n798), .C(DP_OP_169J43_123_4229_n795), .D(
DP_OP_169J43_123_4229_n807), .ICI(DP_OP_169J43_123_4229_n803), .S(
DP_OP_169J43_123_4229_n792), .ICO(DP_OP_169J43_123_4229_n790), .CO(
DP_OP_169J43_123_4229_n791) );
CMPR42X1TS DP_OP_169J43_123_4229_U789 ( .A(DP_OP_169J43_123_4229_n789), .B(
DP_OP_169J43_123_4229_n1356), .C(DP_OP_169J43_123_4229_n1384), .D(
DP_OP_169J43_123_4229_n1412), .ICI(DP_OP_169J43_123_4229_n793), .S(
DP_OP_169J43_123_4229_n787), .ICO(DP_OP_169J43_123_4229_n785), .CO(
DP_OP_169J43_123_4229_n786) );
CMPR42X1TS DP_OP_169J43_123_4229_U788 ( .A(DP_OP_169J43_123_4229_n1496), .B(
DP_OP_169J43_123_4229_n1468), .C(DP_OP_169J43_123_4229_n1440), .D(
DP_OP_169J43_123_4229_n799), .ICI(DP_OP_169J43_123_4229_n796), .S(
DP_OP_169J43_123_4229_n784), .ICO(DP_OP_169J43_123_4229_n782), .CO(
DP_OP_169J43_123_4229_n783) );
CMPR42X1TS DP_OP_169J43_123_4229_U787 ( .A(DP_OP_169J43_123_4229_n797), .B(
DP_OP_169J43_123_4229_n787), .C(DP_OP_169J43_123_4229_n794), .D(
DP_OP_169J43_123_4229_n784), .ICI(DP_OP_169J43_123_4229_n790), .S(
DP_OP_169J43_123_4229_n781), .ICO(DP_OP_169J43_123_4229_n779), .CO(
DP_OP_169J43_123_4229_n780) );
CMPR42X1TS DP_OP_169J43_123_4229_U785 ( .A(DP_OP_169J43_123_4229_n778), .B(
DP_OP_169J43_123_4229_n1495), .C(DP_OP_169J43_123_4229_n788), .D(
DP_OP_169J43_123_4229_n1467), .ICI(DP_OP_169J43_123_4229_n782), .S(
DP_OP_169J43_123_4229_n776), .ICO(DP_OP_169J43_123_4229_n774), .CO(
DP_OP_169J43_123_4229_n775) );
CMPR42X1TS DP_OP_169J43_123_4229_U782 ( .A(DP_OP_169J43_123_4229_n1494), .B(
DP_OP_169J43_123_4229_n777), .C(DP_OP_169J43_123_4229_n1333), .D(
DP_OP_169J43_123_4229_n1466), .ICI(DP_OP_169J43_123_4229_n1382), .S(
DP_OP_169J43_123_4229_n767), .ICO(DP_OP_169J43_123_4229_n765), .CO(
DP_OP_169J43_123_4229_n766) );
CMPR42X1TS DP_OP_169J43_123_4229_U781 ( .A(DP_OP_169J43_123_4229_n1438), .B(
DP_OP_169J43_123_4229_n1354), .C(DP_OP_169J43_123_4229_n1410), .D(
DP_OP_169J43_123_4229_n774), .ICI(DP_OP_169J43_123_4229_n771), .S(
DP_OP_169J43_123_4229_n764), .ICO(DP_OP_169J43_123_4229_n762), .CO(
DP_OP_169J43_123_4229_n763) );
CMPR42X1TS DP_OP_169J43_123_4229_U777 ( .A(DP_OP_169J43_123_4229_n1353), .B(
DP_OP_169J43_123_4229_n1437), .C(DP_OP_169J43_123_4229_n1409), .D(
DP_OP_169J43_123_4229_n765), .ICI(DP_OP_169J43_123_4229_n766), .S(
DP_OP_169J43_123_4229_n754), .ICO(DP_OP_169J43_123_4229_n752), .CO(
DP_OP_169J43_123_4229_n753) );
CMPR42X1TS DP_OP_169J43_123_4229_U776 ( .A(DP_OP_169J43_123_4229_n756), .B(
DP_OP_169J43_123_4229_n762), .C(DP_OP_169J43_123_4229_n763), .D(
DP_OP_169J43_123_4229_n754), .ICI(DP_OP_169J43_123_4229_n759), .S(
DP_OP_169J43_123_4229_n751), .ICO(DP_OP_169J43_123_4229_n749), .CO(
DP_OP_169J43_123_4229_n750) );
CMPR42X1TS DP_OP_169J43_123_4229_U773 ( .A(DP_OP_169J43_123_4229_n1352), .B(
DP_OP_169J43_123_4229_n755), .C(DP_OP_169J43_123_4229_n753), .D(
DP_OP_169J43_123_4229_n746), .ICI(DP_OP_169J43_123_4229_n749), .S(
DP_OP_169J43_123_4229_n743), .ICO(DP_OP_169J43_123_4229_n741), .CO(
DP_OP_169J43_123_4229_n742) );
CMPR42X1TS DP_OP_169J43_123_4229_U771 ( .A(DP_OP_169J43_123_4229_n1435), .B(
DP_OP_169J43_123_4229_n740), .C(DP_OP_169J43_123_4229_n1407), .D(
DP_OP_169J43_123_4229_n1351), .ICI(DP_OP_169J43_123_4229_n744), .S(
DP_OP_169J43_123_4229_n738), .ICO(DP_OP_169J43_123_4229_n736), .CO(
DP_OP_169J43_123_4229_n737) );
CMPR42X1TS DP_OP_169J43_123_4229_U770 ( .A(DP_OP_169J43_123_4229_n1379), .B(
DP_OP_169J43_123_4229_n747), .C(DP_OP_169J43_123_4229_n738), .D(
DP_OP_169J43_123_4229_n745), .ICI(DP_OP_169J43_123_4229_n741), .S(
DP_OP_169J43_123_4229_n735), .ICO(DP_OP_169J43_123_4229_n733), .CO(
DP_OP_169J43_123_4229_n734) );
CMPR42X1TS DP_OP_169J43_123_4229_U768 ( .A(DP_OP_169J43_123_4229_n1350), .B(
DP_OP_169J43_123_4229_n736), .C(DP_OP_169J43_123_4229_n737), .D(
DP_OP_169J43_123_4229_n732), .ICI(DP_OP_169J43_123_4229_n733), .S(
DP_OP_169J43_123_4229_n729), .ICO(DP_OP_169J43_123_4229_n727), .CO(
DP_OP_169J43_123_4229_n728) );
CMPR42X1TS DP_OP_169J43_123_4229_U765 ( .A(DP_OP_169J43_123_4229_n1349), .B(
DP_OP_169J43_123_4229_n730), .C(DP_OP_169J43_123_4229_n724), .D(
DP_OP_169J43_123_4229_n731), .ICI(DP_OP_169J43_123_4229_n727), .S(
DP_OP_169J43_123_4229_n722), .ICO(DP_OP_169J43_123_4229_n720), .CO(
DP_OP_169J43_123_4229_n721) );
CMPR42X1TS mult_x_24_U741 ( .A(mult_x_24_n918), .B(mult_x_24_n1510), .C(
mult_x_24_n921), .D(mult_x_24_n1537), .ICI(mult_x_24_n1564), .S(
mult_x_24_n916), .ICO(mult_x_24_n914), .CO(mult_x_24_n915) );
CMPR42X1TS mult_x_24_U739 ( .A(mult_x_24_n913), .B(mult_x_24_n1509), .C(
mult_x_24_n914), .D(mult_x_24_n1563), .ICI(mult_x_24_n1536), .S(
mult_x_24_n911), .ICO(mult_x_24_n909), .CO(mult_x_24_n910) );
CMPR42X1TS mult_x_24_U734 ( .A(mult_x_24_n1507), .B(mult_x_24_n901), .C(
mult_x_24_n1534), .D(mult_x_24_n1561), .ICI(mult_x_24_n904), .S(
mult_x_24_n899), .ICO(mult_x_24_n897), .CO(mult_x_24_n898) );
CMPR42X1TS mult_x_24_U731 ( .A(mult_x_24_n1533), .B(mult_x_24_n1506), .C(
mult_x_24_n1560), .D(mult_x_24_n894), .ICI(mult_x_24_n897), .S(
mult_x_24_n892), .ICO(mult_x_24_n890), .CO(mult_x_24_n891) );
CMPR42X1TS mult_x_24_U728 ( .A(mult_x_24_n1505), .B(mult_x_24_n1532), .C(
mult_x_24_n893), .D(mult_x_24_n887), .ICI(mult_x_24_n890), .S(
mult_x_24_n885), .ICO(mult_x_24_n883), .CO(mult_x_24_n884) );
CMPR42X1TS mult_x_24_U726 ( .A(mult_x_24_n882), .B(mult_x_24_n1450), .C(
mult_x_24_n888), .D(mult_x_24_n1477), .ICI(mult_x_24_n1504), .S(
mult_x_24_n880), .ICO(mult_x_24_n878), .CO(mult_x_24_n879) );
CMPR42X1TS mult_x_24_U725 ( .A(mult_x_24_n1531), .B(mult_x_24_n886), .C(
mult_x_24_n1558), .D(mult_x_24_n883), .ICI(mult_x_24_n880), .S(
mult_x_24_n877), .ICO(mult_x_24_n875), .CO(mult_x_24_n876) );
CMPR42X1TS mult_x_24_U723 ( .A(mult_x_24_n874), .B(mult_x_24_n1449), .C(
mult_x_24_n878), .D(mult_x_24_n1476), .ICI(mult_x_24_n1503), .S(
mult_x_24_n872), .ICO(mult_x_24_n870), .CO(mult_x_24_n871) );
CMPR42X1TS mult_x_24_U722 ( .A(mult_x_24_n1530), .B(mult_x_24_n1557), .C(
mult_x_24_n879), .D(mult_x_24_n875), .ICI(mult_x_24_n872), .S(
mult_x_24_n869), .ICO(mult_x_24_n867), .CO(mult_x_24_n868) );
CMPR42X1TS mult_x_24_U719 ( .A(mult_x_24_n1502), .B(mult_x_24_n1556), .C(
mult_x_24_n867), .D(mult_x_24_n871), .ICI(mult_x_24_n864), .S(
mult_x_24_n861), .ICO(mult_x_24_n859), .CO(mult_x_24_n860) );
CMPR42X1TS mult_x_24_U716 ( .A(mult_x_24_n1447), .B(mult_x_24_n856), .C(
mult_x_24_n1474), .D(mult_x_24_n1501), .ICI(mult_x_24_n862), .S(
mult_x_24_n854), .ICO(mult_x_24_n852), .CO(mult_x_24_n853) );
CMPR42X1TS mult_x_24_U715 ( .A(mult_x_24_n1555), .B(mult_x_24_n1528), .C(
mult_x_24_n863), .D(mult_x_24_n854), .ICI(mult_x_24_n859), .S(
mult_x_24_n851), .ICO(mult_x_24_n849), .CO(mult_x_24_n850) );
CMPR42X1TS mult_x_24_U712 ( .A(mult_x_24_n1446), .B(mult_x_24_n1473), .C(
mult_x_24_n1500), .D(mult_x_24_n846), .ICI(mult_x_24_n852), .S(
mult_x_24_n844), .ICO(mult_x_24_n842), .CO(mult_x_24_n843) );
CMPR42X1TS mult_x_24_U708 ( .A(mult_x_24_n1445), .B(mult_x_24_n1472), .C(
mult_x_24_n845), .D(mult_x_24_n836), .ICI(mult_x_24_n842), .S(
mult_x_24_n834), .ICO(mult_x_24_n832), .CO(mult_x_24_n833) );
CMPR42X1TS mult_x_24_U705 ( .A(mult_x_24_n828), .B(mult_x_24_n1390), .C(
mult_x_24_n837), .D(mult_x_24_n1417), .ICI(mult_x_24_n1444), .S(
mult_x_24_n826), .ICO(mult_x_24_n824), .CO(mult_x_24_n825) );
CMPR42X1TS mult_x_24_U704 ( .A(mult_x_24_n1471), .B(mult_x_24_n835), .C(
mult_x_24_n1498), .D(mult_x_24_n1552), .ICI(mult_x_24_n826), .S(
mult_x_24_n823), .ICO(mult_x_24_n821), .CO(mult_x_24_n822) );
CMPR42X1TS mult_x_24_U701 ( .A(mult_x_24_n817), .B(mult_x_24_n1389), .C(
mult_x_24_n824), .D(mult_x_24_n1416), .ICI(mult_x_24_n1443), .S(
mult_x_24_n815), .ICO(mult_x_24_n813), .CO(mult_x_24_n814) );
CMPR42X1TS mult_x_24_U700 ( .A(mult_x_24_n1470), .B(mult_x_24_n1551), .C(
mult_x_24_n1497), .D(mult_x_24_n1524), .ICI(mult_x_24_n821), .S(
mult_x_24_n812), .ICO(mult_x_24_n810), .CO(mult_x_24_n811) );
CMPR42X1TS mult_x_24_U699 ( .A(mult_x_24_n825), .B(mult_x_24_n815), .C(
mult_x_24_n822), .D(mult_x_24_n812), .ICI(mult_x_24_n818), .S(
mult_x_24_n809), .ICO(mult_x_24_n807), .CO(mult_x_24_n808) );
CMPR42X1TS mult_x_24_U697 ( .A(mult_x_24_n806), .B(mult_x_24_n1469), .C(
mult_x_24_n1388), .D(mult_x_24_n1415), .ICI(mult_x_24_n813), .S(
mult_x_24_n804), .ICO(mult_x_24_n802), .CO(mult_x_24_n803) );
CMPR42X1TS mult_x_24_U696 ( .A(mult_x_24_n1442), .B(mult_x_24_n1523), .C(
mult_x_24_n1496), .D(mult_x_24_n1550), .ICI(mult_x_24_n814), .S(
mult_x_24_n801), .ICO(mult_x_24_n799), .CO(mult_x_24_n800) );
CMPR42X1TS mult_x_24_U695 ( .A(mult_x_24_n810), .B(mult_x_24_n804), .C(
mult_x_24_n811), .D(mult_x_24_n801), .ICI(mult_x_24_n807), .S(
mult_x_24_n798), .ICO(mult_x_24_n796), .CO(mult_x_24_n797) );
CMPR42X1TS mult_x_24_U692 ( .A(mult_x_24_n1387), .B(mult_x_24_n793), .C(
mult_x_24_n1414), .D(mult_x_24_n1441), .ICI(mult_x_24_n802), .S(
mult_x_24_n791), .ICO(mult_x_24_n789), .CO(mult_x_24_n790) );
CMPR42X1TS mult_x_24_U691 ( .A(mult_x_24_n1495), .B(mult_x_24_n1468), .C(
mult_x_24_n1522), .D(mult_x_24_n1549), .ICI(mult_x_24_n791), .S(
mult_x_24_n788), .ICO(mult_x_24_n786), .CO(mult_x_24_n787) );
CMPR42X1TS mult_x_24_U690 ( .A(mult_x_24_n799), .B(mult_x_24_n803), .C(
mult_x_24_n800), .D(mult_x_24_n788), .ICI(mult_x_24_n796), .S(
mult_x_24_n785), .ICO(mult_x_24_n783), .CO(mult_x_24_n784) );
CMPR42X1TS mult_x_24_U687 ( .A(mult_x_24_n1386), .B(mult_x_24_n1413), .C(
mult_x_24_n1440), .D(mult_x_24_n780), .ICI(mult_x_24_n786), .S(
mult_x_24_n778), .ICO(mult_x_24_n776), .CO(mult_x_24_n777) );
CMPR42X1TS mult_x_24_U686 ( .A(mult_x_24_n1494), .B(mult_x_24_n1467), .C(
mult_x_24_n789), .D(mult_x_24_n1548), .ICI(mult_x_24_n790), .S(
mult_x_24_n775), .ICO(mult_x_24_n773), .CO(mult_x_24_n774) );
CMPR42X1TS mult_x_24_U685 ( .A(mult_x_24_n1521), .B(mult_x_24_n778), .C(
mult_x_24_n787), .D(mult_x_24_n775), .ICI(mult_x_24_n783), .S(
mult_x_24_n772), .ICO(mult_x_24_n770), .CO(mult_x_24_n771) );
CMPR42X1TS mult_x_24_U682 ( .A(mult_x_24_n1385), .B(mult_x_24_n1412), .C(
mult_x_24_n779), .D(mult_x_24_n767), .ICI(mult_x_24_n773), .S(
mult_x_24_n765), .ICO(mult_x_24_n763), .CO(mult_x_24_n764) );
CMPR42X1TS mult_x_24_U681 ( .A(mult_x_24_n1493), .B(mult_x_24_n1466), .C(
mult_x_24_n1520), .D(mult_x_24_n1547), .ICI(mult_x_24_n776), .S(
mult_x_24_n762), .ICO(mult_x_24_n760), .CO(mult_x_24_n761) );
CMPR42X1TS mult_x_24_U679 ( .A(mult_x_24_n963), .B(mult_x_24_n1330), .C(
mult_x_24_n768), .D(mult_x_24_n1357), .ICI(mult_x_24_n1384), .S(
mult_x_24_n756), .ICO(mult_x_24_n754), .CO(mult_x_24_n755) );
CMPR42X1TS mult_x_24_U678 ( .A(mult_x_24_n1411), .B(mult_x_24_n766), .C(
mult_x_24_n1465), .D(mult_x_24_n1438), .ICI(mult_x_24_n760), .S(
mult_x_24_n753), .ICO(mult_x_24_n751), .CO(mult_x_24_n752) );
CMPR42X1TS mult_x_24_U677 ( .A(mult_x_24_n1492), .B(mult_x_24_n1546), .C(
mult_x_24_n1519), .D(mult_x_24_n763), .ICI(mult_x_24_n756), .S(
mult_x_24_n750), .ICO(mult_x_24_n748), .CO(mult_x_24_n749) );
CMPR42X1TS mult_x_24_U675 ( .A(mult_x_24_n962), .B(mult_x_24_n1329), .C(
mult_x_24_n754), .D(mult_x_24_n1356), .ICI(mult_x_24_n1383), .S(
mult_x_24_n744), .ICO(mult_x_24_n742), .CO(mult_x_24_n743) );
CMPR42X1TS mult_x_24_U673 ( .A(mult_x_24_n1464), .B(mult_x_24_n755), .C(
mult_x_24_n1518), .D(mult_x_24_n748), .ICI(mult_x_24_n744), .S(
mult_x_24_n738), .ICO(mult_x_24_n736), .CO(mult_x_24_n737) );
CMPR42X1TS mult_x_24_U672 ( .A(mult_x_24_n752), .B(mult_x_24_n741), .C(
mult_x_24_n749), .D(mult_x_24_n738), .ICI(mult_x_24_n745), .S(
mult_x_24_n735), .ICO(mult_x_24_n733), .CO(mult_x_24_n734) );
CMPR42X1TS mult_x_24_U671 ( .A(n6598), .B(mult_x_24_n961), .C(
mult_x_24_n1409), .D(mult_x_24_n1328), .ICI(mult_x_24_n1355), .S(
mult_x_24_n732), .ICO(mult_x_24_n730), .CO(mult_x_24_n731) );
CMPR42X1TS mult_x_24_U670 ( .A(mult_x_24_n1382), .B(mult_x_24_n742), .C(
mult_x_24_n1436), .D(mult_x_24_n1463), .ICI(mult_x_24_n736), .S(
mult_x_24_n729), .ICO(mult_x_24_n727), .CO(mult_x_24_n728) );
CMPR42X1TS mult_x_24_U669 ( .A(mult_x_24_n1517), .B(mult_x_24_n1490), .C(
mult_x_24_n739), .D(mult_x_24_n743), .ICI(mult_x_24_n732), .S(
mult_x_24_n726), .ICO(mult_x_24_n724), .CO(mult_x_24_n725) );
CMPR42X1TS mult_x_24_U668 ( .A(mult_x_24_n740), .B(mult_x_24_n729), .C(
mult_x_24_n737), .D(mult_x_24_n726), .ICI(mult_x_24_n733), .S(
mult_x_24_n723), .ICO(mult_x_24_n721), .CO(mult_x_24_n722) );
CMPR42X1TS mult_x_24_U665 ( .A(mult_x_24_n1408), .B(mult_x_24_n1489), .C(
mult_x_24_n727), .D(mult_x_24_n720), .ICI(mult_x_24_n724), .S(
mult_x_24_n714), .ICO(mult_x_24_n712), .CO(mult_x_24_n713) );
CMPR42X1TS mult_x_24_U664 ( .A(mult_x_24_n728), .B(mult_x_24_n717), .C(
mult_x_24_n725), .D(mult_x_24_n721), .ICI(mult_x_24_n714), .S(
mult_x_24_n711), .ICO(mult_x_24_n709), .CO(mult_x_24_n710) );
CMPR42X1TS mult_x_24_U663 ( .A(n6598), .B(mult_x_24_n959), .C(mult_x_24_n718), .D(mult_x_24_n1326), .ICI(mult_x_24_n1353), .S(mult_x_24_n708), .ICO(
mult_x_24_n706), .CO(mult_x_24_n707) );
CMPR42X1TS mult_x_24_U661 ( .A(mult_x_24_n1434), .B(mult_x_24_n1488), .C(
mult_x_24_n715), .D(mult_x_24_n708), .ICI(mult_x_24_n712), .S(
mult_x_24_n702), .ICO(mult_x_24_n700), .CO(mult_x_24_n701) );
CMPR42X1TS mult_x_24_U660 ( .A(mult_x_24_n705), .B(mult_x_24_n716), .C(
mult_x_24_n713), .D(mult_x_24_n702), .ICI(mult_x_24_n709), .S(
mult_x_24_n699), .ICO(mult_x_24_n697), .CO(mult_x_24_n698) );
CMPR42X1TS mult_x_24_U659 ( .A(n6551), .B(n6549), .C(mult_x_24_n958), .D(
mult_x_24_n1379), .ICI(mult_x_24_n1325), .S(mult_x_24_n696), .ICO(
mult_x_24_n694), .CO(mult_x_24_n695) );
CMPR42X1TS mult_x_24_U657 ( .A(mult_x_24_n1487), .B(mult_x_24_n1460), .C(
mult_x_24_n696), .D(mult_x_24_n707), .ICI(mult_x_24_n700), .S(
mult_x_24_n690), .ICO(mult_x_24_n688), .CO(mult_x_24_n689) );
CMPR42X1TS mult_x_24_U653 ( .A(mult_x_24_n1351), .B(mult_x_24_n1405), .C(
mult_x_24_n1378), .D(mult_x_24_n1432), .ICI(mult_x_24_n691), .S(
mult_x_24_n681), .ICO(mult_x_24_n679), .CO(mult_x_24_n680) );
CMPR42X1TS mult_x_24_U647 ( .A(mult_x_24_n1404), .B(mult_x_24_n682), .C(
mult_x_24_n1458), .D(mult_x_24_n671), .ICI(mult_x_24_n676), .S(
mult_x_24_n666), .ICO(mult_x_24_n664), .CO(mult_x_24_n665) );
CMPR42X1TS mult_x_24_U644 ( .A(mult_x_24_n660), .B(mult_x_24_n1349), .C(
mult_x_24_n1322), .D(mult_x_24_n1403), .ICI(mult_x_24_n1376), .S(
mult_x_24_n658), .ICO(mult_x_24_n656), .CO(mult_x_24_n657) );
CMPR42X1TS mult_x_24_U643 ( .A(mult_x_24_n670), .B(mult_x_24_n1430), .C(
mult_x_24_n1457), .D(mult_x_24_n667), .ICI(mult_x_24_n664), .S(
mult_x_24_n655), .ICO(mult_x_24_n653), .CO(mult_x_24_n654) );
CMPR42X1TS mult_x_24_U640 ( .A(mult_x_24_n649), .B(mult_x_24_n659), .C(
mult_x_24_n1321), .D(mult_x_24_n1348), .ICI(mult_x_24_n1402), .S(
mult_x_24_n648), .ICO(mult_x_24_n646), .CO(mult_x_24_n647) );
CMPR42X1TS mult_x_24_U639 ( .A(mult_x_24_n1375), .B(mult_x_24_n656), .C(
mult_x_24_n1456), .D(mult_x_24_n1429), .ICI(mult_x_24_n657), .S(
mult_x_24_n645), .ICO(mult_x_24_n643), .CO(mult_x_24_n644) );
CMPR42X1TS mult_x_24_U635 ( .A(mult_x_24_n1401), .B(mult_x_24_n1347), .C(
mult_x_24_n646), .D(mult_x_24_n1428), .ICI(mult_x_24_n647), .S(
mult_x_24_n635), .ICO(mult_x_24_n633), .CO(mult_x_24_n634) );
CMPR42X1TS mult_x_24_U632 ( .A(mult_x_24_n1346), .B(mult_x_24_n636), .C(
mult_x_24_n1427), .D(mult_x_24_n1400), .ICI(mult_x_24_n637), .S(
mult_x_24_n626), .ICO(mult_x_24_n624), .CO(mult_x_24_n625) );
CMPR42X1TS mult_x_24_U628 ( .A(mult_x_24_n1345), .B(mult_x_24_n1318), .C(
mult_x_24_n1426), .D(mult_x_24_n1399), .ICI(mult_x_24_n624), .S(
mult_x_24_n617), .ICO(mult_x_24_n615), .CO(mult_x_24_n616) );
CMPR42X1TS mult_x_24_U621 ( .A(mult_x_24_n602), .B(mult_x_24_n1316), .C(
mult_x_24_n1343), .D(mult_x_24_n609), .ICI(mult_x_24_n1397), .S(
mult_x_24_n600), .ICO(mult_x_24_n598), .CO(mult_x_24_n599) );
CMPR42X1TS mult_x_24_U620 ( .A(mult_x_24_n1370), .B(mult_x_24_n606), .C(
mult_x_24_n607), .D(mult_x_24_n600), .ICI(mult_x_24_n603), .S(
mult_x_24_n597), .ICO(mult_x_24_n595), .CO(mult_x_24_n596) );
CMPR42X1TS mult_x_24_U618 ( .A(mult_x_24_n594), .B(mult_x_24_n601), .C(
mult_x_24_n1342), .D(mult_x_24_n1315), .ICI(mult_x_24_n1396), .S(
mult_x_24_n593), .ICO(mult_x_24_n591), .CO(mult_x_24_n592) );
CMPR42X1TS mult_x_24_U617 ( .A(mult_x_24_n1369), .B(mult_x_24_n598), .C(
mult_x_24_n593), .D(mult_x_24_n599), .ICI(mult_x_24_n595), .S(
mult_x_24_n590), .ICO(mult_x_24_n588), .CO(mult_x_24_n589) );
CMPR42X1TS mult_x_24_U613 ( .A(n6561), .B(mult_x_24_n948), .C(mult_x_24_n946), .D(mult_x_24_n1313), .ICI(mult_x_24_n1367), .S(mult_x_24_n580), .ICO(
mult_x_24_n578), .CO(mult_x_24_n579) );
CMPR42X1TS mult_x_24_U602 ( .A(mult_x_24_n557), .B(mult_x_24_n561), .C(
mult_x_24_n1336), .D(mult_x_24_n1309), .ICI(mult_x_24_n558), .S(
mult_x_24_n556), .ICO(mult_x_24_n554), .CO(mult_x_24_n555) );
CMPR42X1TS mult_x_24_U599 ( .A(n6565), .B(mult_x_24_n942), .C(mult_x_24_n940), .D(mult_x_24_n1307), .ICI(mult_x_24_n550), .S(mult_x_24_n549), .ICO(
mult_x_24_n547), .CO(mult_x_24_n548) );
CMPR42X1TS mult_x_23_U682 ( .A(mult_x_23_n833), .B(mult_x_23_n1307), .C(
mult_x_23_n836), .D(mult_x_23_n1333), .ICI(mult_x_23_n1359), .S(
mult_x_23_n831), .ICO(mult_x_23_n829), .CO(mult_x_23_n830) );
CMPR42X1TS mult_x_23_U680 ( .A(mult_x_23_n828), .B(mult_x_23_n1306), .C(
mult_x_23_n829), .D(mult_x_23_n1358), .ICI(mult_x_23_n1332), .S(
mult_x_23_n826), .ICO(mult_x_23_n824), .CO(mult_x_23_n825) );
CMPR42X1TS mult_x_23_U678 ( .A(mult_x_23_n823), .B(mult_x_23_n1331), .C(
mult_x_23_n1305), .D(mult_x_23_n824), .ICI(mult_x_23_n1357), .S(
mult_x_23_n821), .ICO(mult_x_23_n819), .CO(mult_x_23_n820) );
CMPR42X1TS mult_x_23_U675 ( .A(mult_x_23_n1304), .B(mult_x_23_n816), .C(
mult_x_23_n1330), .D(mult_x_23_n1356), .ICI(mult_x_23_n819), .S(
mult_x_23_n814), .ICO(mult_x_23_n812), .CO(mult_x_23_n813) );
CMPR42X1TS mult_x_23_U672 ( .A(mult_x_23_n1329), .B(mult_x_23_n1303), .C(
mult_x_23_n809), .D(mult_x_23_n812), .ICI(mult_x_23_n1355), .S(
mult_x_23_n807), .ICO(mult_x_23_n805), .CO(mult_x_23_n806) );
CMPR42X1TS mult_x_23_U669 ( .A(mult_x_23_n1354), .B(mult_x_23_n808), .C(
mult_x_23_n802), .D(mult_x_23_n1328), .ICI(mult_x_23_n805), .S(
mult_x_23_n800), .ICO(mult_x_23_n798), .CO(mult_x_23_n799) );
CMPR42X1TS mult_x_23_U667 ( .A(mult_x_23_n797), .B(mult_x_23_n1249), .C(
mult_x_23_n803), .D(mult_x_23_n1275), .ICI(mult_x_23_n1327), .S(
mult_x_23_n795), .ICO(mult_x_23_n793), .CO(mult_x_23_n794) );
CMPR42X1TS mult_x_23_U666 ( .A(mult_x_23_n1301), .B(mult_x_23_n801), .C(
mult_x_23_n1353), .D(mult_x_23_n798), .ICI(mult_x_23_n795), .S(
mult_x_23_n792), .ICO(mult_x_23_n790), .CO(mult_x_23_n791) );
CMPR42X1TS mult_x_23_U664 ( .A(mult_x_23_n789), .B(mult_x_23_n1248), .C(
mult_x_23_n793), .D(mult_x_23_n1300), .ICI(mult_x_23_n1352), .S(
mult_x_23_n787), .ICO(mult_x_23_n785), .CO(mult_x_23_n786) );
CMPR42X1TS mult_x_23_U663 ( .A(mult_x_23_n1274), .B(mult_x_23_n1326), .C(
mult_x_23_n794), .D(mult_x_23_n790), .ICI(mult_x_23_n787), .S(
mult_x_23_n784), .ICO(mult_x_23_n782), .CO(mult_x_23_n783) );
CMPR42X1TS mult_x_23_U661 ( .A(mult_x_23_n781), .B(mult_x_23_n1273), .C(
mult_x_23_n1247), .D(mult_x_23_n1325), .ICI(mult_x_23_n785), .S(
mult_x_23_n779), .ICO(mult_x_23_n777), .CO(mult_x_23_n778) );
CMPR42X1TS mult_x_23_U660 ( .A(mult_x_23_n1299), .B(mult_x_23_n1351), .C(
mult_x_23_n786), .D(mult_x_23_n782), .ICI(mult_x_23_n779), .S(
mult_x_23_n776), .ICO(mult_x_23_n774), .CO(mult_x_23_n775) );
CMPR42X1TS mult_x_23_U657 ( .A(mult_x_23_n1246), .B(mult_x_23_n771), .C(
mult_x_23_n1298), .D(mult_x_23_n1272), .ICI(mult_x_23_n1324), .S(
mult_x_23_n769), .ICO(mult_x_23_n767), .CO(mult_x_23_n768) );
CMPR42X1TS mult_x_23_U656 ( .A(mult_x_23_n777), .B(mult_x_23_n1350), .C(
mult_x_23_n778), .D(mult_x_23_n769), .ICI(mult_x_23_n774), .S(
mult_x_23_n766), .ICO(mult_x_23_n764), .CO(mult_x_23_n765) );
CMPR42X1TS mult_x_23_U653 ( .A(mult_x_23_n1271), .B(mult_x_23_n1245), .C(
mult_x_23_n1323), .D(mult_x_23_n761), .ICI(mult_x_23_n1297), .S(
mult_x_23_n759), .ICO(mult_x_23_n757), .CO(mult_x_23_n758) );
CMPR42X1TS mult_x_23_U649 ( .A(mult_x_23_n1296), .B(mult_x_23_n760), .C(
mult_x_23_n1348), .D(mult_x_23_n751), .ICI(mult_x_23_n1322), .S(
mult_x_23_n749), .ICO(mult_x_23_n747), .CO(mult_x_23_n748) );
CMPR42X1TS mult_x_23_U648 ( .A(mult_x_23_n757), .B(mult_x_23_n1270), .C(
mult_x_23_n758), .D(mult_x_23_n749), .ICI(mult_x_23_n754), .S(
mult_x_23_n746), .ICO(mult_x_23_n744), .CO(mult_x_23_n745) );
CMPR42X1TS mult_x_23_U646 ( .A(mult_x_23_n743), .B(mult_x_23_n1191), .C(
mult_x_23_n752), .D(mult_x_23_n1217), .ICI(mult_x_23_n1243), .S(
mult_x_23_n741), .ICO(mult_x_23_n739), .CO(mult_x_23_n740) );
CMPR42X1TS mult_x_23_U645 ( .A(mult_x_23_n1269), .B(mult_x_23_n750), .C(
mult_x_23_n1321), .D(mult_x_23_n1295), .ICI(mult_x_23_n747), .S(
mult_x_23_n738), .ICO(mult_x_23_n736), .CO(mult_x_23_n737) );
CMPR42X1TS mult_x_23_U644 ( .A(mult_x_23_n1347), .B(mult_x_23_n741), .C(
mult_x_23_n748), .D(mult_x_23_n738), .ICI(mult_x_23_n744), .S(
mult_x_23_n735), .ICO(mult_x_23_n733), .CO(mult_x_23_n734) );
CMPR42X1TS mult_x_23_U642 ( .A(mult_x_23_n732), .B(mult_x_23_n1190), .C(
mult_x_23_n739), .D(mult_x_23_n1242), .ICI(mult_x_23_n1216), .S(
mult_x_23_n730), .ICO(mult_x_23_n728), .CO(mult_x_23_n729) );
CMPR42X1TS mult_x_23_U641 ( .A(mult_x_23_n1294), .B(mult_x_23_n1346), .C(
mult_x_23_n1268), .D(mult_x_23_n740), .ICI(mult_x_23_n736), .S(
mult_x_23_n727), .ICO(mult_x_23_n725), .CO(mult_x_23_n726) );
CMPR42X1TS mult_x_23_U640 ( .A(mult_x_23_n1320), .B(mult_x_23_n730), .C(
mult_x_23_n737), .D(mult_x_23_n733), .ICI(mult_x_23_n727), .S(
mult_x_23_n724), .ICO(mult_x_23_n722), .CO(mult_x_23_n723) );
CMPR42X1TS mult_x_23_U638 ( .A(mult_x_23_n721), .B(mult_x_23_n1215), .C(
mult_x_23_n1189), .D(mult_x_23_n1267), .ICI(mult_x_23_n728), .S(
mult_x_23_n719), .ICO(mult_x_23_n717), .CO(mult_x_23_n718) );
CMPR42X1TS mult_x_23_U637 ( .A(mult_x_23_n1319), .B(mult_x_23_n1241), .C(
mult_x_23_n1293), .D(mult_x_23_n729), .ICI(mult_x_23_n719), .S(
mult_x_23_n716), .ICO(mult_x_23_n714), .CO(mult_x_23_n715) );
CMPR42X1TS mult_x_23_U634 ( .A(mult_x_23_n1188), .B(mult_x_23_n710), .C(
mult_x_23_n1240), .D(mult_x_23_n1214), .ICI(mult_x_23_n1266), .S(
mult_x_23_n708), .ICO(mult_x_23_n706), .CO(mult_x_23_n707) );
CMPR42X1TS mult_x_23_U632 ( .A(mult_x_23_n714), .B(mult_x_23_n708), .C(
mult_x_23_n715), .D(mult_x_23_n711), .ICI(mult_x_23_n705), .S(
mult_x_23_n702), .ICO(mult_x_23_n700), .CO(mult_x_23_n701) );
CMPR42X1TS mult_x_23_U630 ( .A(mult_x_23_n1213), .B(mult_x_23_n1187), .C(
mult_x_23_n1265), .D(mult_x_23_n699), .ICI(mult_x_23_n703), .S(
mult_x_23_n697), .ICO(mult_x_23_n695), .CO(mult_x_23_n696) );
CMPR42X1TS mult_x_23_U629 ( .A(mult_x_23_n1317), .B(mult_x_23_n706), .C(
mult_x_23_n1239), .D(mult_x_23_n1343), .ICI(mult_x_23_n707), .S(
mult_x_23_n694), .ICO(mult_x_23_n692), .CO(mult_x_23_n693) );
CMPR42X1TS mult_x_23_U626 ( .A(mult_x_23_n1238), .B(mult_x_23_n698), .C(
mult_x_23_n1342), .D(mult_x_23_n1290), .ICI(mult_x_23_n1264), .S(
mult_x_23_n686), .ICO(mult_x_23_n684), .CO(mult_x_23_n685) );
CMPR42X1TS mult_x_23_U625 ( .A(mult_x_23_n688), .B(mult_x_23_n695), .C(
mult_x_23_n1212), .D(mult_x_23_n1316), .ICI(mult_x_23_n692), .S(
mult_x_23_n683), .ICO(mult_x_23_n681), .CO(mult_x_23_n682) );
CMPR42X1TS mult_x_23_U624 ( .A(mult_x_23_n696), .B(mult_x_23_n686), .C(
mult_x_23_n693), .D(mult_x_23_n683), .ICI(mult_x_23_n689), .S(
mult_x_23_n680), .ICO(mult_x_23_n678), .CO(mult_x_23_n679) );
CMPR42X1TS mult_x_23_U622 ( .A(mult_x_23_n1211), .B(mult_x_23_n1341), .C(
mult_x_23_n687), .D(mult_x_23_n1315), .ICI(mult_x_23_n684), .S(
mult_x_23_n675), .ICO(mult_x_23_n673), .CO(mult_x_23_n674) );
CMPR42X1TS mult_x_23_U620 ( .A(mult_x_23_n685), .B(mult_x_23_n675), .C(
mult_x_23_n682), .D(mult_x_23_n672), .ICI(mult_x_23_n678), .S(
mult_x_23_n669), .ICO(mult_x_23_n667), .CO(mult_x_23_n668) );
CMPR42X1TS mult_x_23_U617 ( .A(mult_x_23_n666), .B(mult_x_23_n1210), .C(
mult_x_23_n1262), .D(mult_x_23_n1314), .ICI(mult_x_23_n670), .S(
mult_x_23_n661), .ICO(mult_x_23_n659), .CO(mult_x_23_n660) );
CMPR42X1TS mult_x_23_U616 ( .A(mult_x_23_n674), .B(mult_x_23_n664), .C(
mult_x_23_n671), .D(mult_x_23_n661), .ICI(mult_x_23_n667), .S(
mult_x_23_n658), .ICO(mult_x_23_n656), .CO(mult_x_23_n657) );
CMPR42X1TS mult_x_23_U614 ( .A(mult_x_23_n1209), .B(mult_x_23_n1313), .C(
mult_x_23_n655), .D(mult_x_23_n665), .ICI(mult_x_23_n662), .S(
mult_x_23_n653), .ICO(mult_x_23_n651), .CO(mult_x_23_n652) );
CMPR42X1TS mult_x_23_U612 ( .A(mult_x_23_n663), .B(mult_x_23_n653), .C(
mult_x_23_n660), .D(mult_x_23_n650), .ICI(mult_x_23_n656), .S(
mult_x_23_n647), .ICO(mult_x_23_n645), .CO(mult_x_23_n646) );
CMPR42X1TS mult_x_23_U606 ( .A(mult_x_23_n1155), .B(mult_x_23_n1207), .C(
mult_x_23_n633), .D(mult_x_23_n643), .ICI(mult_x_23_n640), .S(
mult_x_23_n631), .ICO(mult_x_23_n629), .CO(mult_x_23_n630) );
CMPR42X1TS mult_x_23_U605 ( .A(mult_x_23_n1259), .B(mult_x_23_n1181), .C(
mult_x_23_n1233), .D(mult_x_23_n1285), .ICI(mult_x_23_n637), .S(
mult_x_23_n628), .ICO(mult_x_23_n626), .CO(mult_x_23_n627) );
CMPR42X1TS mult_x_23_U604 ( .A(mult_x_23_n641), .B(mult_x_23_n631), .C(
mult_x_23_n638), .D(mult_x_23_n628), .ICI(mult_x_23_n634), .S(
mult_x_23_n625), .ICO(mult_x_23_n623), .CO(mult_x_23_n624) );
CMPR42X1TS mult_x_23_U601 ( .A(mult_x_23_n629), .B(mult_x_23_n1154), .C(
mult_x_23_n1206), .D(mult_x_23_n1258), .ICI(mult_x_23_n626), .S(
mult_x_23_n618), .ICO(mult_x_23_n616), .CO(mult_x_23_n617) );
CMPR42X1TS mult_x_23_U598 ( .A(mult_x_23_n622), .B(mult_x_23_n1129), .C(
mult_x_23_n1153), .D(mult_x_23_n1283), .ICI(mult_x_23_n1257), .S(
mult_x_23_n610), .ICO(mult_x_23_n608), .CO(mult_x_23_n609) );
CMPR42X1TS mult_x_23_U595 ( .A(n6550), .B(mult_x_23_n611), .C(
mult_x_23_n1128), .D(mult_x_23_n1178), .ICI(mult_x_23_n1230), .S(
mult_x_23_n601), .ICO(mult_x_23_n592), .CO(mult_x_23_n600) );
CMPR42X1TS mult_x_23_U594 ( .A(mult_x_23_n608), .B(mult_x_23_n1152), .C(
mult_x_23_n1204), .D(mult_x_23_n1256), .ICI(mult_x_23_n609), .S(
mult_x_23_n599), .ICO(mult_x_23_n597), .CO(mult_x_23_n598) );
CMPR42X1TS mult_x_23_U585 ( .A(mult_x_23_n581), .B(mult_x_23_n1202), .C(
mult_x_23_n588), .D(mult_x_23_n579), .ICI(mult_x_23_n584), .S(
mult_x_23_n576), .ICO(mult_x_23_n574), .CO(mult_x_23_n575) );
CMPR42X1TS mult_x_23_U583 ( .A(mult_x_23_n1126), .B(mult_x_23_n1201), .C(
mult_x_23_n573), .D(mult_x_23_n580), .ICI(mult_x_23_n577), .S(
mult_x_23_n571), .ICO(mult_x_23_n569), .CO(mult_x_23_n570) );
CMPR42X1TS mult_x_23_U577 ( .A(mult_x_23_n565), .B(mult_x_23_n1125), .C(
mult_x_23_n1225), .D(mult_x_23_n1147), .ICI(mult_x_23_n1199), .S(
mult_x_23_n556), .ICO(mult_x_23_n554), .CO(mult_x_23_n555) );
CMPR42X1TS mult_x_23_U576 ( .A(mult_x_23_n562), .B(mult_x_23_n1173), .C(
mult_x_23_n563), .D(mult_x_23_n556), .ICI(mult_x_23_n559), .S(
mult_x_23_n553), .ICO(mult_x_23_n551), .CO(mult_x_23_n552) );
CMPR42X1TS mult_x_23_U571 ( .A(mult_x_23_n1145), .B(mult_x_23_n543), .C(
mult_x_23_n1171), .D(mult_x_23_n549), .ICI(mult_x_23_n546), .S(
mult_x_23_n541), .ICO(mult_x_23_n539), .CO(mult_x_23_n540) );
CMPR42X1TS mult_x_23_U566 ( .A(mult_x_23_n1122), .B(mult_x_23_n535), .C(
mult_x_23_n531), .D(mult_x_23_n1169), .ICI(mult_x_23_n532), .S(
mult_x_23_n529), .ICO(mult_x_23_n527), .CO(mult_x_23_n528) );
CMPR42X1TS mult_x_23_U562 ( .A(mult_x_23_n526), .B(mult_x_23_n1167), .C(
mult_x_23_n1141), .D(mult_x_23_n1121), .ICI(mult_x_23_n523), .S(
mult_x_23_n520), .ICO(mult_x_23_n518), .CO(mult_x_23_n519) );
CMPR42X1TS mult_x_23_U561 ( .A(n6563), .B(mult_x_23_n521), .C(
mult_x_23_n1120), .D(mult_x_23_n518), .ICI(mult_x_23_n1140), .S(
mult_x_23_n517), .ICO(mult_x_23_n515), .CO(mult_x_23_n516) );
DFFRX1TS Exp_module_Underflow_m_Q_reg_0_ ( .D(n352), .CK(clk), .RN(n6630),
.Q(underflow_flag), .QN(n6581) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_63_ ( .D(n287),
.CK(clk), .RN(n6614), .Q(final_result_ieee[63]), .QN(n6580) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_7_ ( .D(n360), .CK(clk),
.RN(n6608), .Q(Sgf_normalized_result[7]), .QN(n6579) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_13_ ( .D(n366), .CK(clk),
.RN(n6615), .Q(Sgf_normalized_result[13]), .QN(n6578) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_15_ ( .D(n368), .CK(clk),
.RN(n6618), .Q(Sgf_normalized_result[15]), .QN(n6577) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_9_ ( .D(n362), .CK(clk),
.RN(n6615), .Q(Sgf_normalized_result[9]), .QN(n6576) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_11_ ( .D(n364), .CK(clk),
.RN(n6619), .Q(Sgf_normalized_result[11]), .QN(n6575) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_14_ ( .D(n367), .CK(clk),
.RN(n6614), .Q(Sgf_normalized_result[14]), .QN(n6573) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_6_ ( .D(n359), .CK(clk),
.RN(n6618), .Q(Sgf_normalized_result[6]), .QN(n6572) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_12_ ( .D(n365), .CK(clk),
.RN(n6618), .Q(Sgf_normalized_result[12]), .QN(n6571) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_8_ ( .D(n361), .CK(clk),
.RN(n6619), .Q(Sgf_normalized_result[8]), .QN(n6570) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_10_ ( .D(n363), .CK(clk),
.RN(n6614), .Q(Sgf_normalized_result[10]), .QN(n6569) );
DFFRX1TS Adder_M_Add_overflow_Result_Q_reg_0_ ( .D(n526), .CK(clk), .RN(
n6609), .Q(FSM_add_overflow_flag), .QN(n6568) );
DFFRX1TS Sel_B_Q_reg_0_ ( .D(n419), .CK(clk), .RN(n797), .Q(
FSM_selector_B[0]), .QN(n6559) );
DFFRX2TS Operands_load_reg_YMRegister_Q_reg_25_ ( .D(n607), .CK(clk), .RN(
n6609), .Q(Op_MY[25]), .QN(n6543) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_16_ ( .D(n369), .CK(clk),
.RN(n6613), .Q(Sgf_normalized_result[16]), .QN(n6542) );
DFFRX1TS Sel_C_Q_reg_0_ ( .D(n709), .CK(clk), .RN(n6611), .Q(FSM_selector_C),
.QN(n6541) );
DFFRX2TS FS_Module_state_reg_reg_2_ ( .D(n711), .CK(clk), .RN(n6631), .Q(
FS_Module_state_reg[2]), .QN(n6540) );
DFFRX2TS Sel_B_Q_reg_1_ ( .D(n418), .CK(clk), .RN(n6630), .Q(
FSM_selector_B[1]), .QN(n6539) );
DFFRX2TS Operands_load_reg_YMRegister_Q_reg_0_ ( .D(n582), .CK(clk), .RN(
n6629), .Q(Op_MY[0]), .QN(n6537) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_29_ ( .D(n675), .CK(clk), .RN(
n6625), .Q(Op_MX[29]), .QN(n6552) );
DFFRX2TS FS_Module_state_reg_reg_3_ ( .D(n714), .CK(clk), .RN(n6604), .Q(
FS_Module_state_reg[3]), .QN(n6567) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_47_ ( .D(n693), .CK(clk), .RN(
n6621), .Q(Op_MX[47]), .QN(n6563) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_35_ ( .D(n681), .CK(clk), .RN(
n796), .Q(Op_MX[35]), .QN(n6550) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_41_ ( .D(n687), .CK(clk), .RN(
n6621), .Q(Op_MX[41]), .QN(n6557) );
DFFRX2TS FS_Module_state_reg_reg_0_ ( .D(n713), .CK(clk), .RN(n6599), .Q(
FS_Module_state_reg[0]), .QN(n6535) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_0_ ( .D(n351),
.CK(clk), .RN(n6621), .Q(final_result_ieee[0]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_1_ ( .D(n350),
.CK(clk), .RN(n6621), .Q(final_result_ieee[1]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_2_ ( .D(n349),
.CK(clk), .RN(n6621), .Q(final_result_ieee[2]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_3_ ( .D(n348),
.CK(clk), .RN(n6623), .Q(final_result_ieee[3]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_4_ ( .D(n347),
.CK(clk), .RN(n785), .Q(final_result_ieee[4]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_5_ ( .D(n346),
.CK(clk), .RN(n6630), .Q(final_result_ieee[5]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_6_ ( .D(n345),
.CK(clk), .RN(n6608), .Q(final_result_ieee[6]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_7_ ( .D(n344),
.CK(clk), .RN(n785), .Q(final_result_ieee[7]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_8_ ( .D(n343),
.CK(clk), .RN(n6612), .Q(final_result_ieee[8]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_9_ ( .D(n342),
.CK(clk), .RN(n6623), .Q(final_result_ieee[9]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_10_ ( .D(n341),
.CK(clk), .RN(n6619), .Q(final_result_ieee[10]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_11_ ( .D(n340),
.CK(clk), .RN(n6615), .Q(final_result_ieee[11]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_12_ ( .D(n339),
.CK(clk), .RN(n6614), .Q(final_result_ieee[12]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_13_ ( .D(n338),
.CK(clk), .RN(n6618), .Q(final_result_ieee[13]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_14_ ( .D(n337),
.CK(clk), .RN(n6608), .Q(final_result_ieee[14]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_15_ ( .D(n336),
.CK(clk), .RN(n785), .Q(final_result_ieee[15]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_16_ ( .D(n335),
.CK(clk), .RN(n6612), .Q(final_result_ieee[16]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_17_ ( .D(n334),
.CK(clk), .RN(n6623), .Q(final_result_ieee[17]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_18_ ( .D(n333),
.CK(clk), .RN(n6622), .Q(final_result_ieee[18]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_19_ ( .D(n332),
.CK(clk), .RN(n6625), .Q(final_result_ieee[19]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_20_ ( .D(n331),
.CK(clk), .RN(n796), .Q(final_result_ieee[20]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_21_ ( .D(n330),
.CK(clk), .RN(n6616), .Q(final_result_ieee[21]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_22_ ( .D(n329),
.CK(clk), .RN(n6624), .Q(final_result_ieee[22]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_23_ ( .D(n328),
.CK(clk), .RN(n6609), .Q(final_result_ieee[23]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_24_ ( .D(n327),
.CK(clk), .RN(n797), .Q(final_result_ieee[24]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_25_ ( .D(n326),
.CK(clk), .RN(n6630), .Q(final_result_ieee[25]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_26_ ( .D(n325),
.CK(clk), .RN(n6630), .Q(final_result_ieee[26]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_27_ ( .D(n324),
.CK(clk), .RN(n6629), .Q(final_result_ieee[27]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_28_ ( .D(n323),
.CK(clk), .RN(n6622), .Q(final_result_ieee[28]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_29_ ( .D(n322),
.CK(clk), .RN(n6625), .Q(final_result_ieee[29]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_30_ ( .D(n321),
.CK(clk), .RN(n1630), .Q(final_result_ieee[30]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_31_ ( .D(n320),
.CK(clk), .RN(n6620), .Q(final_result_ieee[31]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_32_ ( .D(n319),
.CK(clk), .RN(n6617), .Q(final_result_ieee[32]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_33_ ( .D(n318),
.CK(clk), .RN(n1630), .Q(final_result_ieee[33]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_34_ ( .D(n317),
.CK(clk), .RN(n6620), .Q(final_result_ieee[34]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_35_ ( .D(n316),
.CK(clk), .RN(n6617), .Q(final_result_ieee[35]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_36_ ( .D(n315),
.CK(clk), .RN(n1633), .Q(final_result_ieee[36]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_37_ ( .D(n314),
.CK(clk), .RN(n6620), .Q(final_result_ieee[37]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_38_ ( .D(n313),
.CK(clk), .RN(n6617), .Q(final_result_ieee[38]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_39_ ( .D(n312),
.CK(clk), .RN(n1630), .Q(final_result_ieee[39]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_40_ ( .D(n311),
.CK(clk), .RN(n6620), .Q(final_result_ieee[40]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_41_ ( .D(n310),
.CK(clk), .RN(n6617), .Q(final_result_ieee[41]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_42_ ( .D(n309),
.CK(clk), .RN(n6608), .Q(final_result_ieee[42]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_43_ ( .D(n308),
.CK(clk), .RN(n785), .Q(final_result_ieee[43]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_44_ ( .D(n307),
.CK(clk), .RN(n6612), .Q(final_result_ieee[44]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_45_ ( .D(n306),
.CK(clk), .RN(n6623), .Q(final_result_ieee[45]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_46_ ( .D(n305),
.CK(clk), .RN(n6619), .Q(final_result_ieee[46]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_47_ ( .D(n304),
.CK(clk), .RN(n6615), .Q(final_result_ieee[47]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_48_ ( .D(n303),
.CK(clk), .RN(n6614), .Q(final_result_ieee[48]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_49_ ( .D(n302),
.CK(clk), .RN(n6618), .Q(final_result_ieee[49]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_50_ ( .D(n301),
.CK(clk), .RN(n6608), .Q(final_result_ieee[50]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_51_ ( .D(n300),
.CK(clk), .RN(n785), .Q(final_result_ieee[51]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_52_ ( .D(n299),
.CK(clk), .RN(n6612), .Q(final_result_ieee[52]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_53_ ( .D(n298),
.CK(clk), .RN(n6623), .Q(final_result_ieee[53]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_54_ ( .D(n297),
.CK(clk), .RN(n6618), .Q(final_result_ieee[54]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_55_ ( .D(n296),
.CK(clk), .RN(n6608), .Q(final_result_ieee[55]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_56_ ( .D(n295),
.CK(clk), .RN(n785), .Q(final_result_ieee[56]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_57_ ( .D(n294),
.CK(clk), .RN(n6612), .Q(final_result_ieee[57]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_58_ ( .D(n293),
.CK(clk), .RN(n6623), .Q(final_result_ieee[58]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_59_ ( .D(n292),
.CK(clk), .RN(n6619), .Q(final_result_ieee[59]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_60_ ( .D(n291),
.CK(clk), .RN(n6615), .Q(final_result_ieee[60]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_61_ ( .D(n290),
.CK(clk), .RN(n6614), .Q(final_result_ieee[61]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_62_ ( .D(n289),
.CK(clk), .RN(n6618), .Q(final_result_ieee[62]) );
DFFRXLTS Exp_module_Oflow_A_m_Q_reg_0_ ( .D(n405), .CK(clk), .RN(n797), .Q(
Exp_module_Overflow_flag_A) );
DFFRX1TS Exp_module_exp_result_m_Q_reg_11_ ( .D(n406), .CK(clk), .RN(n6628),
.Q(exp_oper_result[11]) );
DFFRHQX2TS Operands_load_reg_XMRegister_Q_reg_51_ ( .D(n697), .CK(clk), .RN(
n6620), .Q(n6584) );
DFFRHQX2TS Operands_load_reg_XMRegister_Q_reg_25_ ( .D(n671), .CK(clk), .RN(
n6620), .Q(n6583) );
DFFRX2TS Operands_load_reg_YMRegister_Q_reg_3_ ( .D(n585), .CK(clk), .RN(
n6625), .Q(Op_MY[3]) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_27_ ( .D(n673), .CK(clk), .RN(
n6622), .Q(Op_MX[27]), .QN(mult_x_23_n1930) );
DFFTRX1TS Sgf_operation_ODD1_middle_DatO_reg_0_ ( .D(n6538), .RN(
DP_OP_169J43_123_4229_n2318), .CK(clk), .Q(
Sgf_operation_ODD1_Q_middle[0]) );
DFFTRX1TS Sgf_operation_ODD1_left_DatO_reg_0_ ( .D(Op_MX[27]), .RN(Op_MY[27]), .CK(clk), .Q(Sgf_operation_ODD1_Q_left[0]), .QN(DP_OP_168J43_122_1342_n499)
);
DFFTRX1TS Sgf_operation_ODD1_middle_DatO_reg_1_ ( .D(n6562), .RN(
DP_OP_169J43_123_4229_n646), .CK(clk), .Q(
Sgf_operation_ODD1_Q_middle[1]) );
DFFTRX2TS Sgf_operation_ODD1_left_DatO_reg_45_ ( .D(1'b1), .RN(
Sgf_operation_ODD1_left_N45), .CK(clk), .QN(DP_OP_168J43_122_1342_n454) );
DFFTRX2TS Sgf_operation_ODD1_left_DatO_reg_37_ ( .D(1'b1), .RN(
Sgf_operation_ODD1_left_N37), .CK(clk), .QN(DP_OP_168J43_122_1342_n462) );
DFFTRX2TS Sgf_operation_ODD1_left_DatO_reg_43_ ( .D(1'b1), .RN(
Sgf_operation_ODD1_left_N43), .CK(clk), .QN(DP_OP_168J43_122_1342_n456) );
DFFTRX2TS Sgf_operation_ODD1_left_DatO_reg_39_ ( .D(1'b1), .RN(
Sgf_operation_ODD1_left_N39), .CK(clk), .QN(DP_OP_168J43_122_1342_n460) );
DFFTRX2TS Sgf_operation_ODD1_left_DatO_reg_33_ ( .D(1'b1), .RN(
Sgf_operation_ODD1_left_N33), .CK(clk), .QN(DP_OP_168J43_122_1342_n466) );
DFFTRX2TS Sgf_operation_ODD1_left_DatO_reg_35_ ( .D(1'b1), .RN(
Sgf_operation_ODD1_left_N35), .CK(clk), .QN(DP_OP_168J43_122_1342_n464) );
DFFTRX1TS Sgf_operation_ODD1_middle_DatO_reg_48_ ( .D(1'b1), .RN(
Sgf_operation_ODD1_middle_N48), .CK(clk), .Q(
Sgf_operation_ODD1_Q_middle[48]) );
DFFTRX1TS Sgf_operation_ODD1_middle_DatO_reg_26_ ( .D(1'b1), .RN(
Sgf_operation_ODD1_middle_N26), .CK(clk), .Q(
Sgf_operation_ODD1_Q_middle[26]) );
DFFTRX1TS Sgf_operation_ODD1_left_DatO_reg_21_ ( .D(1'b1), .RN(
Sgf_operation_ODD1_left_N21), .CK(clk), .Q(
Sgf_operation_ODD1_Q_left[21]), .QN(DP_OP_168J43_122_1342_n478) );
DFFTRX1TS Sgf_operation_ODD1_middle_DatO_reg_15_ ( .D(1'b1), .RN(
Sgf_operation_ODD1_middle_N15), .CK(clk), .Q(
Sgf_operation_ODD1_Q_middle[15]) );
DFFTRX1TS Sgf_operation_ODD1_left_DatO_reg_11_ ( .D(1'b1), .RN(
Sgf_operation_ODD1_left_N11), .CK(clk), .Q(
Sgf_operation_ODD1_Q_left[11]), .QN(DP_OP_168J43_122_1342_n488) );
DFFTRX1TS Sgf_operation_ODD1_left_DatO_reg_6_ ( .D(1'b1), .RN(
Sgf_operation_ODD1_left_N6), .CK(clk), .Q(Sgf_operation_ODD1_Q_left[6]), .QN(DP_OP_168J43_122_1342_n493) );
DFFTRX1TS Sgf_operation_ODD1_right_DatO_reg_1_ ( .D(1'b1), .RN(
Sgf_operation_ODD1_right_N1), .CK(clk), .Q(Sgf_operation_Result[1]),
.QN(DP_OP_168J43_122_1342_n446) );
DFFTRX1TS Sgf_operation_ODD1_middle_DatO_reg_46_ ( .D(1'b1), .RN(
Sgf_operation_ODD1_middle_N46), .CK(clk), .Q(
Sgf_operation_ODD1_Q_middle[46]) );
DFFTRX1TS Sgf_operation_ODD1_left_DatO_reg_31_ ( .D(1'b1), .RN(
Sgf_operation_ODD1_left_N31), .CK(clk), .Q(
Sgf_operation_ODD1_Q_left[31]), .QN(DP_OP_168J43_122_1342_n468) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_1_ ( .D(n647), .CK(clk), .RN(
n6624), .Q(Op_MX[1]) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_8_ ( .D(n654), .CK(clk), .RN(
n6615), .Q(Op_MX[8]) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_4_ ( .D(n650), .CK(clk), .RN(
n6614), .Q(Op_MX[4]) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_23_ ( .D(n669), .CK(clk), .RN(
n6620), .Q(Op_MX[23]) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_20_ ( .D(n666), .CK(clk), .RN(
n1633), .Q(Op_MX[20]) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_49_ ( .D(n695), .CK(clk), .RN(
n6621), .Q(Op_MX[49]) );
DFFRX1TS Operands_load_reg_YMRegister_Q_reg_5_ ( .D(n587), .CK(clk), .RN(
n797), .Q(n6597), .QN(n6549) );
DFFRX1TS Operands_load_reg_YMRegister_Q_reg_14_ ( .D(n596), .CK(clk), .RN(
n6608), .Q(n6594), .QN(n6558) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_23_ ( .D(n605), .CK(clk), .RN(
n6629), .Q(n6591), .QN(n6565) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_42_ ( .D(n688), .CK(clk), .RN(
n6621), .Q(Op_MX[42]) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_30_ ( .D(n676), .CK(clk), .RN(
n6616), .Q(Op_MX[30]) );
DFFRX2TS Operands_load_reg_YMRegister_Q_reg_29_ ( .D(n611), .CK(clk), .RN(
n797), .Q(Op_MY[29]) );
DFFRX2TS Operands_load_reg_YMRegister_Q_reg_36_ ( .D(n618), .CK(clk), .RN(
n6630), .Q(Op_MY[36]) );
DFFRX2TS Operands_load_reg_YMRegister_Q_reg_38_ ( .D(n620), .CK(clk), .RN(
n6610), .Q(Op_MY[38]) );
DFFRX2TS Operands_load_reg_YMRegister_Q_reg_40_ ( .D(n622), .CK(clk), .RN(
n6626), .Q(Op_MY[40]) );
DFFRX2TS Operands_load_reg_YMRegister_Q_reg_21_ ( .D(n603), .CK(clk), .RN(
n6630), .Q(Op_MY[21]) );
DFFRX2TS Operands_load_reg_YMRegister_Q_reg_7_ ( .D(n589), .CK(clk), .RN(
n6619), .Q(Op_MY[7]) );
DFFRX2TS Operands_load_reg_YMRegister_Q_reg_49_ ( .D(n631), .CK(clk), .RN(
n1632), .Q(Op_MY[49]) );
DFFRX2TS Operands_load_reg_YMRegister_Q_reg_12_ ( .D(n594), .CK(clk), .RN(
n6614), .Q(Op_MY[12]) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_34_ ( .D(n680), .CK(clk), .RN(
n6624), .Q(Op_MX[34]) );
DFFRX2TS Operands_load_reg_YMRegister_Q_reg_16_ ( .D(n598), .CK(clk), .RN(
n6615), .Q(Op_MY[16]) );
DFFRX2TS Operands_load_reg_YMRegister_Q_reg_46_ ( .D(n628), .CK(clk), .RN(
n1632), .Q(Op_MY[46]) );
DFFRX2TS Barrel_Shifter_module_Output_Reg_Q_reg_4_ ( .D(n357), .CK(clk),
.RN(n6629), .Q(Sgf_normalized_result[4]) );
DFFRX2TS Barrel_Shifter_module_Output_Reg_Q_reg_2_ ( .D(n355), .CK(clk),
.RN(n797), .Q(Sgf_normalized_result[2]) );
DFFRX4TS Operands_load_reg_XMRegister_Q_reg_32_ ( .D(n678), .CK(clk), .RN(
n6609), .Q(n6589), .QN(n6553) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_5_ ( .D(n358), .CK(clk),
.RN(n6614), .Q(Sgf_normalized_result[5]) );
DFFRX2TS Operands_load_reg_YMRegister_Q_reg_30_ ( .D(n612), .CK(clk), .RN(
n6630), .Q(Op_MY[30]) );
DFFRX2TS Operands_load_reg_YMRegister_Q_reg_33_ ( .D(n615), .CK(clk), .RN(
n796), .Q(Op_MY[33]) );
DFFRX2TS Operands_load_reg_YMRegister_Q_reg_41_ ( .D(n623), .CK(clk), .RN(
n6628), .Q(Op_MY[41]) );
DFFRX2TS Operands_load_reg_YMRegister_Q_reg_44_ ( .D(n626), .CK(clk), .RN(
n1631), .Q(Op_MY[44]) );
DFFRX2TS Operands_load_reg_YMRegister_Q_reg_48_ ( .D(n630), .CK(clk), .RN(
n6611), .Q(Op_MY[48]) );
DFFRX2TS Operands_load_reg_YMRegister_Q_reg_39_ ( .D(n621), .CK(clk), .RN(
n6610), .Q(Op_MY[39]) );
DFFRX2TS Operands_load_reg_YMRegister_Q_reg_35_ ( .D(n617), .CK(clk), .RN(
n6616), .Q(Op_MY[35]) );
DFFRX2TS Operands_load_reg_YMRegister_Q_reg_37_ ( .D(n619), .CK(clk), .RN(
n6626), .Q(Op_MY[37]) );
DFFRX2TS Operands_load_reg_YMRegister_Q_reg_50_ ( .D(n632), .CK(clk), .RN(
n6628), .Q(Op_MY[50]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_17_ ( .D(n370), .CK(clk),
.RN(n6613), .Q(Sgf_normalized_result[17]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_19_ ( .D(n372), .CK(clk),
.RN(n6613), .Q(Sgf_normalized_result[19]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_21_ ( .D(n374), .CK(clk),
.RN(n6613), .Q(Sgf_normalized_result[21]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_23_ ( .D(n376), .CK(clk),
.RN(n6613), .Q(Sgf_normalized_result[23]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_25_ ( .D(n378), .CK(clk),
.RN(n6613), .Q(Sgf_normalized_result[25]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_27_ ( .D(n380), .CK(clk),
.RN(n6613), .Q(Sgf_normalized_result[27]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_29_ ( .D(n382), .CK(clk),
.RN(n6608), .Q(Sgf_normalized_result[29]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_31_ ( .D(n384), .CK(clk),
.RN(n785), .Q(Sgf_normalized_result[31]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_33_ ( .D(n386), .CK(clk),
.RN(n6623), .Q(Sgf_normalized_result[33]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_35_ ( .D(n388), .CK(clk),
.RN(n6612), .Q(Sgf_normalized_result[35]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_37_ ( .D(n390), .CK(clk),
.RN(n6619), .Q(Sgf_normalized_result[37]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_39_ ( .D(n392), .CK(clk),
.RN(n6615), .Q(Sgf_normalized_result[39]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_41_ ( .D(n394), .CK(clk),
.RN(n6610), .Q(Sgf_normalized_result[41]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_104_ ( .D(n520), .CK(clk), .RN(
n6631), .Q(P_Sgf[104]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_18_ ( .D(n371), .CK(clk),
.RN(n6613), .Q(Sgf_normalized_result[18]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_20_ ( .D(n373), .CK(clk),
.RN(n6613), .Q(Sgf_normalized_result[20]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_22_ ( .D(n375), .CK(clk),
.RN(n6613), .Q(Sgf_normalized_result[22]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_24_ ( .D(n377), .CK(clk),
.RN(n6613), .Q(Sgf_normalized_result[24]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_26_ ( .D(n379), .CK(clk),
.RN(n6613), .Q(Sgf_normalized_result[26]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_28_ ( .D(n381), .CK(clk),
.RN(n6614), .Q(Sgf_normalized_result[28]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_30_ ( .D(n383), .CK(clk),
.RN(n6618), .Q(Sgf_normalized_result[30]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_32_ ( .D(n385), .CK(clk),
.RN(n6608), .Q(Sgf_normalized_result[32]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_34_ ( .D(n387), .CK(clk),
.RN(n785), .Q(Sgf_normalized_result[34]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_36_ ( .D(n389), .CK(clk),
.RN(n6623), .Q(Sgf_normalized_result[36]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_38_ ( .D(n391), .CK(clk),
.RN(n6612), .Q(Sgf_normalized_result[38]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_40_ ( .D(n393), .CK(clk),
.RN(n6626), .Q(Sgf_normalized_result[40]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_42_ ( .D(n395), .CK(clk),
.RN(n1631), .Q(Sgf_normalized_result[42]) );
DFFRX1TS Operands_load_reg_XMRegister_Q_reg_55_ ( .D(n701), .CK(clk), .RN(
n1633), .Q(Op_MX[55]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_52_ ( .D(n527), .CK(clk), .RN(n6624),
.Q(Add_result[52]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_105_ ( .D(n420), .CK(clk), .RN(
n6607), .Q(P_Sgf[105]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_4_ ( .D(n575), .CK(clk), .RN(n6616),
.Q(Add_result[4]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_7_ ( .D(n572), .CK(clk), .RN(n796),
.Q(Add_result[7]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_8_ ( .D(n571), .CK(clk), .RN(n6627),
.Q(Add_result[8]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_9_ ( .D(n570), .CK(clk), .RN(n6617),
.Q(Add_result[9]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_10_ ( .D(n569), .CK(clk), .RN(n6620),
.Q(Add_result[10]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_11_ ( .D(n568), .CK(clk), .RN(n6625),
.Q(Add_result[11]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_12_ ( .D(n567), .CK(clk), .RN(n6617),
.Q(Add_result[12]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_13_ ( .D(n566), .CK(clk), .RN(n6620),
.Q(Add_result[13]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_14_ ( .D(n565), .CK(clk), .RN(n1633),
.Q(Add_result[14]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_15_ ( .D(n564), .CK(clk), .RN(n6617),
.Q(Add_result[15]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_43_ ( .D(n396), .CK(clk),
.RN(n1632), .Q(Sgf_normalized_result[43]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_44_ ( .D(n397), .CK(clk),
.RN(n6628), .Q(Sgf_normalized_result[44]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_45_ ( .D(n398), .CK(clk),
.RN(n6611), .Q(Sgf_normalized_result[45]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_46_ ( .D(n399), .CK(clk),
.RN(n6610), .Q(Sgf_normalized_result[46]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_47_ ( .D(n400), .CK(clk),
.RN(n6626), .Q(Sgf_normalized_result[47]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_48_ ( .D(n401), .CK(clk),
.RN(n6611), .Q(Sgf_normalized_result[48]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_49_ ( .D(n402), .CK(clk),
.RN(n6610), .Q(Sgf_normalized_result[49]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_50_ ( .D(n403), .CK(clk),
.RN(n6626), .Q(Sgf_normalized_result[50]) );
DFFRX1TS Operands_load_reg_YMRegister_Q_reg_57_ ( .D(n639), .CK(clk), .RN(
n6626), .Q(Op_MY[57]) );
DFFRX1TS Operands_load_reg_YMRegister_Q_reg_61_ ( .D(n643), .CK(clk), .RN(
n6622), .Q(Op_MY[61]) );
DFFRX1TS Operands_load_reg_XMRegister_Q_reg_61_ ( .D(n707), .CK(clk), .RN(
n6620), .Q(Op_MX[61]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_103_ ( .D(n525), .CK(clk), .RN(
n784), .Q(P_Sgf[103]) );
DFFRX1TS Operands_load_reg_YMRegister_Q_reg_52_ ( .D(n634), .CK(clk), .RN(
n1631), .Q(Op_MY[52]) );
DFFRX1TS Operands_load_reg_XMRegister_Q_reg_62_ ( .D(n708), .CK(clk), .RN(
n6617), .Q(Op_MX[62]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_66_ ( .D(n487), .CK(clk), .RN(
n6603), .Q(P_Sgf[66]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_67_ ( .D(n488), .CK(clk), .RN(
n6600), .Q(P_Sgf[67]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_68_ ( .D(n489), .CK(clk), .RN(
n6604), .Q(P_Sgf[68]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_53_ ( .D(n474), .CK(clk), .RN(
n6603), .Q(P_Sgf[53]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_55_ ( .D(n476), .CK(clk), .RN(
n6604), .Q(P_Sgf[55]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_58_ ( .D(n479), .CK(clk), .RN(
n6601), .Q(P_Sgf[58]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_59_ ( .D(n480), .CK(clk), .RN(
n6605), .Q(P_Sgf[59]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_60_ ( .D(n481), .CK(clk), .RN(
n6606), .Q(P_Sgf[60]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_61_ ( .D(n482), .CK(clk), .RN(
n6599), .Q(P_Sgf[61]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_62_ ( .D(n483), .CK(clk), .RN(
n6602), .Q(P_Sgf[62]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_63_ ( .D(n484), .CK(clk), .RN(
n784), .Q(P_Sgf[63]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_64_ ( .D(n485), .CK(clk), .RN(
n6607), .Q(P_Sgf[64]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_65_ ( .D(n486), .CK(clk), .RN(
n6603), .Q(P_Sgf[65]) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_48_ ( .D(n694), .CK(clk), .RN(
n6621), .Q(Op_MX[48]) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_9_ ( .D(n655), .CK(clk), .RN(
n6618), .Q(Op_MX[9]) );
DFFRX2TS Operands_load_reg_YMRegister_Q_reg_43_ ( .D(n625), .CK(clk), .RN(
n1632), .Q(Op_MY[43]) );
DFFRX2TS Operands_load_reg_YMRegister_Q_reg_19_ ( .D(n601), .CK(clk), .RN(
n6629), .Q(Op_MY[19]) );
DFFRX2TS Operands_load_reg_YMRegister_Q_reg_15_ ( .D(n597), .CK(clk), .RN(
n6618), .Q(Op_MY[15]) );
DFFRX2TS Operands_load_reg_YMRegister_Q_reg_42_ ( .D(n624), .CK(clk), .RN(
n6628), .Q(Op_MY[42]) );
DFFRX1TS Exp_module_exp_result_m_Q_reg_1_ ( .D(n416), .CK(clk), .RN(n6609),
.Q(exp_oper_result[1]) );
DFFRX1TS Exp_module_exp_result_m_Q_reg_0_ ( .D(n417), .CK(clk), .RN(n6630),
.Q(exp_oper_result[0]) );
DFFRX2TS Operands_load_reg_YMRegister_Q_reg_1_ ( .D(n583), .CK(clk), .RN(
n6624), .Q(Op_MY[1]) );
DFFRX2TS Operands_load_reg_YMRegister_Q_reg_4_ ( .D(n586), .CK(clk), .RN(
n6616), .Q(Op_MY[4]) );
DFFRX2TS Operands_load_reg_YMRegister_Q_reg_6_ ( .D(n588), .CK(clk), .RN(
n796), .Q(Op_MY[6]) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_39_ ( .D(n685), .CK(clk), .RN(
n6621), .Q(Op_MX[39]) );
DFFRX4TS FS_Module_state_reg_reg_1_ ( .D(n712), .CK(clk), .RN(n6602), .Q(
n6585), .QN(n6536) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_0_ ( .D(n421), .CK(clk), .RN(
n6600), .Q(P_Sgf[0]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_4_ ( .D(n425), .CK(clk), .RN(
n6606), .Q(P_Sgf[4]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_8_ ( .D(n429), .CK(clk), .RN(
n6602), .Q(P_Sgf[8]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_12_ ( .D(n433), .CK(clk), .RN(
n6599), .Q(P_Sgf[12]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_16_ ( .D(n437), .CK(clk), .RN(
n6600), .Q(P_Sgf[16]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_20_ ( .D(n441), .CK(clk), .RN(
n6601), .Q(P_Sgf[20]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_24_ ( .D(n445), .CK(clk), .RN(
n6605), .Q(P_Sgf[24]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_28_ ( .D(n449), .CK(clk), .RN(
n6601), .Q(P_Sgf[28]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_32_ ( .D(n453), .CK(clk), .RN(
n6605), .Q(P_Sgf[32]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_36_ ( .D(n457), .CK(clk), .RN(
n6606), .Q(P_Sgf[36]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_48_ ( .D(n469), .CK(clk), .RN(
n784), .Q(P_Sgf[48]) );
DFFRX1TS Operands_load_reg_XMRegister_Q_reg_63_ ( .D(n645), .CK(clk), .RN(
n6629), .Q(Op_MX[63]) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_13_ ( .D(n659), .CK(clk), .RN(
n6608), .Q(Op_MX[13]) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_19_ ( .D(n665), .CK(clk), .RN(
n1633), .Q(Op_MX[19]) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_14_ ( .D(n660), .CK(clk), .RN(
n1633), .Q(Op_MX[14]) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_15_ ( .D(n661), .CK(clk), .RN(
n1633), .Q(Op_MX[15]) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_7_ ( .D(n653), .CK(clk), .RN(
n785), .Q(Op_MX[7]) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_12_ ( .D(n658), .CK(clk), .RN(
n6612), .Q(Op_MX[12]) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_31_ ( .D(n677), .CK(clk), .RN(
n6622), .Q(Op_MX[31]) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_43_ ( .D(n689), .CK(clk), .RN(
n6621), .Q(Op_MX[43]) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_37_ ( .D(n683), .CK(clk), .RN(
n797), .Q(Op_MX[37]) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_36_ ( .D(n682), .CK(clk), .RN(
n6630), .Q(Op_MX[36]) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_45_ ( .D(n691), .CK(clk), .RN(
n6621), .Q(Op_MX[45]) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_21_ ( .D(n667), .CK(clk), .RN(
n1633), .Q(Op_MX[21]) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_33_ ( .D(n679), .CK(clk), .RN(
n6629), .Q(Op_MX[33]) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_2_ ( .D(n648), .CK(clk), .RN(
n6623), .Q(Op_MX[2]) );
DFFRX2TS Operands_load_reg_YMRegister_Q_reg_34_ ( .D(n616), .CK(clk), .RN(
n796), .Q(Op_MY[34]) );
DFFRX2TS Operands_load_reg_YMRegister_Q_reg_32_ ( .D(n614), .CK(clk), .RN(
n6616), .Q(Op_MY[32]) );
DFFRX2TS Operands_load_reg_YMRegister_Q_reg_28_ ( .D(n610), .CK(clk), .RN(
n6609), .Q(Op_MY[28]) );
DFFRX2TS Operands_load_reg_YMRegister_Q_reg_22_ ( .D(n604), .CK(clk), .RN(
n6624), .Q(Op_MY[22]) );
DFFRX2TS Operands_load_reg_YMRegister_Q_reg_13_ ( .D(n595), .CK(clk), .RN(
n785), .Q(Op_MY[13]) );
DFFRX2TS Operands_load_reg_YMRegister_Q_reg_24_ ( .D(n606), .CK(clk), .RN(
n6609), .Q(Op_MY[24]) );
DFFRX2TS Operands_load_reg_YMRegister_Q_reg_47_ ( .D(n629), .CK(clk), .RN(
n1631), .Q(Op_MY[47]) );
DFFRX2TS Operands_load_reg_YMRegister_Q_reg_31_ ( .D(n613), .CK(clk), .RN(
n6624), .Q(Op_MY[31]) );
DFFRX2TS Operands_load_reg_YMRegister_Q_reg_9_ ( .D(n591), .CK(clk), .RN(
n6623), .Q(Op_MY[9]) );
DFFRX2TS Operands_load_reg_YMRegister_Q_reg_45_ ( .D(n627), .CK(clk), .RN(
n6611), .Q(Op_MY[45]) );
DFFRX2TS Operands_load_reg_YMRegister_Q_reg_10_ ( .D(n592), .CK(clk), .RN(
n6612), .Q(Op_MY[10]) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_46_ ( .D(n692), .CK(clk), .RN(
n6621), .Q(Op_MX[46]) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_28_ ( .D(n674), .CK(clk), .RN(
n6625), .Q(Op_MX[28]) );
DFFRX2TS Operands_load_reg_YMRegister_Q_reg_18_ ( .D(n600), .CK(clk), .RN(
n6615), .Q(Op_MY[18]) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_40_ ( .D(n686), .CK(clk), .RN(
n6621), .Q(Op_MX[40]) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_3_ ( .D(n649), .CK(clk), .RN(
n6619), .Q(Op_MX[3]) );
DFFRX1TS Operands_load_reg_XMRegister_Q_reg_58_ ( .D(n704), .CK(clk), .RN(
n797), .Q(Op_MX[58]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_102_ ( .D(n524), .CK(clk), .RN(
n6607), .Q(P_Sgf[102]) );
DFFRX1TS Operands_load_reg_YMRegister_Q_reg_53_ ( .D(n635), .CK(clk), .RN(
n1632), .Q(Op_MY[53]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_100_ ( .D(n522), .CK(clk), .RN(
n6603), .Q(P_Sgf[100]) );
DFFRX1TS Operands_load_reg_XMRegister_Q_reg_59_ ( .D(n705), .CK(clk), .RN(
n6608), .Q(Op_MX[59]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_16_ ( .D(n563), .CK(clk), .RN(n796),
.Q(Add_result[16]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_17_ ( .D(n562), .CK(clk), .RN(n6616),
.Q(Add_result[17]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_18_ ( .D(n561), .CK(clk), .RN(n6629),
.Q(Add_result[18]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_19_ ( .D(n560), .CK(clk), .RN(n797),
.Q(Add_result[19]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_57_ ( .D(n478), .CK(clk), .RN(
n6607), .Q(P_Sgf[57]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_56_ ( .D(n477), .CK(clk), .RN(
n784), .Q(P_Sgf[56]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_1_ ( .D(n578), .CK(clk), .RN(n6629),
.Q(Add_result[1]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_2_ ( .D(n577), .CK(clk), .RN(n6619),
.Q(Add_result[2]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_3_ ( .D(n576), .CK(clk), .RN(n6622),
.Q(Add_result[3]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_5_ ( .D(n574), .CK(clk), .RN(n796),
.Q(Add_result[5]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_6_ ( .D(n573), .CK(clk), .RN(n6616),
.Q(Add_result[6]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_49_ ( .D(n470), .CK(clk), .RN(
n6606), .Q(P_Sgf[49]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_51_ ( .D(n528), .CK(clk), .RN(n6622),
.Q(Add_result[51]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_50_ ( .D(n529), .CK(clk), .RN(n6625),
.Q(Add_result[50]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_49_ ( .D(n530), .CK(clk), .RN(n796),
.Q(Add_result[49]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_37_ ( .D(n458), .CK(clk), .RN(
n6604), .Q(P_Sgf[37]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_33_ ( .D(n546), .CK(clk), .RN(n6630),
.Q(Add_result[33]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_34_ ( .D(n545), .CK(clk), .RN(n6609),
.Q(Add_result[34]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_35_ ( .D(n544), .CK(clk), .RN(n6624),
.Q(Add_result[35]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_36_ ( .D(n543), .CK(clk), .RN(n6616),
.Q(Add_result[36]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_37_ ( .D(n542), .CK(clk), .RN(n796),
.Q(Add_result[37]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_38_ ( .D(n541), .CK(clk), .RN(n6625),
.Q(Add_result[38]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_39_ ( .D(n540), .CK(clk), .RN(n6622),
.Q(Add_result[39]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_40_ ( .D(n539), .CK(clk), .RN(n6629),
.Q(Add_result[40]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_41_ ( .D(n538), .CK(clk), .RN(n6630),
.Q(Add_result[41]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_42_ ( .D(n537), .CK(clk), .RN(n797),
.Q(Add_result[42]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_43_ ( .D(n536), .CK(clk), .RN(n6629),
.Q(Add_result[43]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_44_ ( .D(n535), .CK(clk), .RN(n6630),
.Q(Add_result[44]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_45_ ( .D(n534), .CK(clk), .RN(n797),
.Q(Add_result[45]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_46_ ( .D(n533), .CK(clk), .RN(n6609),
.Q(Add_result[46]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_47_ ( .D(n532), .CK(clk), .RN(n6624),
.Q(Add_result[47]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_48_ ( .D(n531), .CK(clk), .RN(n6616),
.Q(Add_result[48]) );
DFFRX1TS Operands_load_reg_XMRegister_Q_reg_54_ ( .D(n700), .CK(clk), .RN(
n6617), .Q(Op_MX[54]) );
DFFRX1TS Operands_load_reg_XMRegister_Q_reg_57_ ( .D(n703), .CK(clk), .RN(
n6613), .Q(Op_MX[57]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_20_ ( .D(n559), .CK(clk), .RN(n6610),
.Q(Add_result[20]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_21_ ( .D(n558), .CK(clk), .RN(n6611),
.Q(Add_result[21]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_22_ ( .D(n557), .CK(clk), .RN(n6626),
.Q(Add_result[22]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_23_ ( .D(n556), .CK(clk), .RN(n6628),
.Q(Add_result[23]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_24_ ( .D(n555), .CK(clk), .RN(n1632),
.Q(Add_result[24]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_25_ ( .D(n554), .CK(clk), .RN(n1631),
.Q(Add_result[25]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_26_ ( .D(n553), .CK(clk), .RN(n6610),
.Q(Add_result[26]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_27_ ( .D(n552), .CK(clk), .RN(n6611),
.Q(Add_result[27]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_28_ ( .D(n551), .CK(clk), .RN(n6626),
.Q(Add_result[28]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_29_ ( .D(n550), .CK(clk), .RN(n6628),
.Q(Add_result[29]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_30_ ( .D(n549), .CK(clk), .RN(n1632),
.Q(Add_result[30]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_31_ ( .D(n548), .CK(clk), .RN(n1631),
.Q(Add_result[31]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_32_ ( .D(n547), .CK(clk), .RN(n6630),
.Q(Add_result[32]) );
DFFRX1TS Operands_load_reg_XMRegister_Q_reg_56_ ( .D(n702), .CK(clk), .RN(
n6620), .Q(Op_MX[56]) );
DFFRX1TS Operands_load_reg_XMRegister_Q_reg_60_ ( .D(n706), .CK(clk), .RN(
n6617), .Q(Op_MX[60]) );
DFFRX1TS Operands_load_reg_XMRegister_Q_reg_52_ ( .D(n698), .CK(clk), .RN(
n6620), .Q(Op_MX[52]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_51_ ( .D(n404), .CK(clk),
.RN(n6610), .Q(Sgf_normalized_result[51]) );
DFFRX1TS Operands_load_reg_XMRegister_Q_reg_53_ ( .D(n699), .CK(clk), .RN(
n6613), .Q(Op_MX[53]) );
DFFRX1TS Operands_load_reg_YMRegister_Q_reg_62_ ( .D(n644), .CK(clk), .RN(
n6612), .Q(Op_MY[62]) );
DFFRX1TS Operands_load_reg_YMRegister_Q_reg_55_ ( .D(n637), .CK(clk), .RN(
n6611), .Q(Op_MY[55]) );
DFFRX1TS Operands_load_reg_YMRegister_Q_reg_59_ ( .D(n641), .CK(clk), .RN(
n1632), .Q(Op_MY[59]) );
DFFRX1TS Exp_module_exp_result_m_Q_reg_10_ ( .D(n407), .CK(clk), .RN(n6628),
.Q(exp_oper_result[10]) );
DFFRX1TS Exp_module_exp_result_m_Q_reg_9_ ( .D(n408), .CK(clk), .RN(n1632),
.Q(exp_oper_result[9]) );
DFFRX1TS Exp_module_exp_result_m_Q_reg_2_ ( .D(n415), .CK(clk), .RN(n1631),
.Q(exp_oper_result[2]) );
DFFRX1TS Exp_module_exp_result_m_Q_reg_3_ ( .D(n414), .CK(clk), .RN(n1632),
.Q(exp_oper_result[3]) );
DFFRX1TS Exp_module_exp_result_m_Q_reg_7_ ( .D(n410), .CK(clk), .RN(n6610),
.Q(exp_oper_result[7]) );
DFFRX1TS Exp_module_exp_result_m_Q_reg_8_ ( .D(n409), .CK(clk), .RN(n1631),
.Q(exp_oper_result[8]) );
DFFRX1TS Operands_load_reg_YMRegister_Q_reg_60_ ( .D(n642), .CK(clk), .RN(
n1631), .Q(Op_MY[60]) );
DFFRX1TS Operands_load_reg_YMRegister_Q_reg_56_ ( .D(n638), .CK(clk), .RN(
n6626), .Q(Op_MY[56]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_101_ ( .D(n523), .CK(clk), .RN(
n6604), .Q(P_Sgf[101]) );
DFFRX1TS Operands_load_reg_YMRegister_Q_reg_58_ ( .D(n640), .CK(clk), .RN(
n6628), .Q(Op_MY[58]) );
DFFRX1TS Operands_load_reg_YMRegister_Q_reg_54_ ( .D(n636), .CK(clk), .RN(
n6610), .Q(Op_MY[54]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_1_ ( .D(n354), .CK(clk),
.RN(n6630), .Q(Sgf_normalized_result[1]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_0_ ( .D(n353), .CK(clk),
.RN(n6609), .Q(Sgf_normalized_result[0]) );
DFFRX1TS Exp_module_exp_result_m_Q_reg_4_ ( .D(n413), .CK(clk), .RN(n6628),
.Q(exp_oper_result[4]) );
DFFRX1TS Exp_module_exp_result_m_Q_reg_5_ ( .D(n412), .CK(clk), .RN(n6626),
.Q(exp_oper_result[5]) );
DFFRX1TS Exp_module_exp_result_m_Q_reg_6_ ( .D(n411), .CK(clk), .RN(n6611),
.Q(exp_oper_result[6]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_99_ ( .D(n521), .CK(clk), .RN(
n6606), .Q(P_Sgf[99]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_98_ ( .D(n519), .CK(clk), .RN(
n6605), .Q(P_Sgf[98]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_97_ ( .D(n518), .CK(clk), .RN(
n6601), .Q(P_Sgf[97]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_96_ ( .D(n517), .CK(clk), .RN(
n6600), .Q(P_Sgf[96]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_95_ ( .D(n516), .CK(clk), .RN(
n6603), .Q(P_Sgf[95]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_94_ ( .D(n515), .CK(clk), .RN(
n6607), .Q(P_Sgf[94]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_93_ ( .D(n514), .CK(clk), .RN(
n784), .Q(P_Sgf[93]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_92_ ( .D(n513), .CK(clk), .RN(
n6599), .Q(P_Sgf[92]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_91_ ( .D(n512), .CK(clk), .RN(
n6599), .Q(P_Sgf[91]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_90_ ( .D(n511), .CK(clk), .RN(
n6602), .Q(P_Sgf[90]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_89_ ( .D(n510), .CK(clk), .RN(
n6604), .Q(P_Sgf[89]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_88_ ( .D(n509), .CK(clk), .RN(
n6606), .Q(P_Sgf[88]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_87_ ( .D(n508), .CK(clk), .RN(
n6605), .Q(P_Sgf[87]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_86_ ( .D(n507), .CK(clk), .RN(
n6601), .Q(P_Sgf[86]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_85_ ( .D(n506), .CK(clk), .RN(
n6600), .Q(P_Sgf[85]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_84_ ( .D(n505), .CK(clk), .RN(
n6603), .Q(P_Sgf[84]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_83_ ( .D(n504), .CK(clk), .RN(
n6607), .Q(P_Sgf[83]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_82_ ( .D(n503), .CK(clk), .RN(
n784), .Q(P_Sgf[82]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_81_ ( .D(n502), .CK(clk), .RN(
n6599), .Q(P_Sgf[81]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_80_ ( .D(n501), .CK(clk), .RN(
n6602), .Q(P_Sgf[80]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_79_ ( .D(n500), .CK(clk), .RN(
n784), .Q(P_Sgf[79]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_78_ ( .D(n499), .CK(clk), .RN(
n6599), .Q(P_Sgf[78]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_77_ ( .D(n498), .CK(clk), .RN(
n6602), .Q(P_Sgf[77]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_76_ ( .D(n497), .CK(clk), .RN(
n6604), .Q(P_Sgf[76]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_75_ ( .D(n496), .CK(clk), .RN(
n6606), .Q(P_Sgf[75]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_74_ ( .D(n495), .CK(clk), .RN(
n6605), .Q(P_Sgf[74]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_73_ ( .D(n494), .CK(clk), .RN(
n6601), .Q(P_Sgf[73]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_72_ ( .D(n493), .CK(clk), .RN(
n6600), .Q(P_Sgf[72]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_71_ ( .D(n492), .CK(clk), .RN(
n6603), .Q(P_Sgf[71]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_70_ ( .D(n491), .CK(clk), .RN(
n6607), .Q(P_Sgf[70]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_69_ ( .D(n490), .CK(clk), .RN(
n784), .Q(P_Sgf[69]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_54_ ( .D(n475), .CK(clk), .RN(
n6601), .Q(P_Sgf[54]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_50_ ( .D(n471), .CK(clk), .RN(
n6605), .Q(P_Sgf[50]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_38_ ( .D(n459), .CK(clk), .RN(
n6606), .Q(P_Sgf[38]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_34_ ( .D(n455), .CK(clk), .RN(
n6599), .Q(P_Sgf[34]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_30_ ( .D(n451), .CK(clk), .RN(
n6605), .Q(P_Sgf[30]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_26_ ( .D(n447), .CK(clk), .RN(
n6607), .Q(P_Sgf[26]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_22_ ( .D(n443), .CK(clk), .RN(
n6601), .Q(P_Sgf[22]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_18_ ( .D(n439), .CK(clk), .RN(
n6604), .Q(P_Sgf[18]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_14_ ( .D(n435), .CK(clk), .RN(
n6603), .Q(P_Sgf[14]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_10_ ( .D(n431), .CK(clk), .RN(
n6605), .Q(P_Sgf[10]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_6_ ( .D(n427), .CK(clk), .RN(
n6602), .Q(P_Sgf[6]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_2_ ( .D(n423), .CK(clk), .RN(
n6607), .Q(P_Sgf[2]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_33_ ( .D(n454), .CK(clk), .RN(
n6600), .Q(P_Sgf[33]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_29_ ( .D(n450), .CK(clk), .RN(
n6606), .Q(P_Sgf[29]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_25_ ( .D(n446), .CK(clk), .RN(
n6603), .Q(P_Sgf[25]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_21_ ( .D(n442), .CK(clk), .RN(
n6605), .Q(P_Sgf[21]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_17_ ( .D(n438), .CK(clk), .RN(
n6602), .Q(P_Sgf[17]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_13_ ( .D(n434), .CK(clk), .RN(
n6600), .Q(P_Sgf[13]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_9_ ( .D(n430), .CK(clk), .RN(
n6606), .Q(P_Sgf[9]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_5_ ( .D(n426), .CK(clk), .RN(
n6599), .Q(P_Sgf[5]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_1_ ( .D(n422), .CK(clk), .RN(
n6603), .Q(P_Sgf[1]) );
DFFRX1TS Operands_load_reg_YMRegister_Q_reg_20_ ( .D(n602), .CK(clk), .RN(
n6622), .Q(n6592), .QN(n6564) );
DFFRX1TS Operands_load_reg_YMRegister_Q_reg_17_ ( .D(n599), .CK(clk), .RN(
n6623), .Q(n6593), .QN(n6561) );
DFFRX1TS Operands_load_reg_YMRegister_Q_reg_11_ ( .D(n593), .CK(clk), .RN(
n6612), .Q(n6595), .QN(n6555) );
DFFRX1TS Operands_load_reg_YMRegister_Q_reg_8_ ( .D(n590), .CK(clk), .RN(
n785), .Q(n6596), .QN(n6554) );
DFFRX1TS Operands_load_reg_YMRegister_Q_reg_51_ ( .D(n633), .CK(clk), .RN(
n1631), .Q(n6590), .QN(n6544) );
DFFTRX1TS Sgf_operation_ODD1_left_DatO_reg_38_ ( .D(1'b1), .RN(
Sgf_operation_ODD1_left_N38), .CK(clk), .Q(
Sgf_operation_ODD1_Q_left[38]), .QN(DP_OP_168J43_122_1342_n461) );
DFFTRX1TS Sgf_operation_ODD1_middle_DatO_reg_34_ ( .D(1'b1), .RN(
Sgf_operation_ODD1_middle_N34), .CK(clk), .Q(
Sgf_operation_ODD1_Q_middle[34]) );
DFFTRX1TS Sgf_operation_ODD1_middle_DatO_reg_35_ ( .D(1'b1), .RN(
Sgf_operation_ODD1_middle_N35), .CK(clk), .Q(
Sgf_operation_ODD1_Q_middle[35]) );
DFFTRX1TS Sgf_operation_ODD1_middle_DatO_reg_27_ ( .D(1'b1), .RN(
Sgf_operation_ODD1_middle_N27), .CK(clk), .Q(
Sgf_operation_ODD1_Q_middle[27]) );
DFFTRX1TS Sgf_operation_ODD1_right_DatO_reg_46_ ( .D(1'b1), .RN(
Sgf_operation_ODD1_right_N46), .CK(clk), .Q(
Sgf_operation_ODD1_Q_right[46]), .QN(DP_OP_168J43_122_1342_n401) );
DFFTRX1TS Sgf_operation_ODD1_left_DatO_reg_44_ ( .D(1'b1), .RN(
Sgf_operation_ODD1_left_N44), .CK(clk), .Q(
Sgf_operation_ODD1_Q_left[44]), .QN(DP_OP_168J43_122_1342_n455) );
DFFTRX1TS Sgf_operation_ODD1_right_DatO_reg_37_ ( .D(1'b1), .RN(
Sgf_operation_ODD1_right_N37), .CK(clk), .Q(
Sgf_operation_ODD1_Q_right[37]), .QN(DP_OP_168J43_122_1342_n410) );
DFFTRX1TS Sgf_operation_ODD1_right_DatO_reg_33_ ( .D(1'b1), .RN(
Sgf_operation_ODD1_right_N33), .CK(clk), .Q(
Sgf_operation_ODD1_Q_right[33]), .QN(DP_OP_168J43_122_1342_n414) );
DFFTRX1TS Sgf_operation_ODD1_left_DatO_reg_34_ ( .D(1'b1), .RN(
Sgf_operation_ODD1_left_N34), .CK(clk), .Q(
Sgf_operation_ODD1_Q_left[34]), .QN(DP_OP_168J43_122_1342_n465) );
DFFTRX1TS Sgf_operation_ODD1_middle_DatO_reg_33_ ( .D(1'b1), .RN(
Sgf_operation_ODD1_middle_N33), .CK(clk), .Q(
Sgf_operation_ODD1_Q_middle[33]) );
DFFTRX1TS Sgf_operation_ODD1_middle_DatO_reg_47_ ( .D(1'b1), .RN(
Sgf_operation_ODD1_middle_N47), .CK(clk), .Q(
Sgf_operation_ODD1_Q_middle[47]) );
DFFTRX1TS Sgf_operation_ODD1_middle_DatO_reg_30_ ( .D(1'b1), .RN(
Sgf_operation_ODD1_middle_N30), .CK(clk), .Q(
Sgf_operation_ODD1_Q_middle[30]) );
DFFTRX1TS Sgf_operation_ODD1_middle_DatO_reg_37_ ( .D(1'b1), .RN(
Sgf_operation_ODD1_middle_N37), .CK(clk), .Q(
Sgf_operation_ODD1_Q_middle[37]) );
DFFTRX1TS Sgf_operation_ODD1_middle_DatO_reg_31_ ( .D(1'b1), .RN(
Sgf_operation_ODD1_middle_N31), .CK(clk), .Q(
Sgf_operation_ODD1_Q_middle[31]) );
DFFTRX1TS Sgf_operation_ODD1_left_DatO_reg_30_ ( .D(1'b1), .RN(
Sgf_operation_ODD1_left_N30), .CK(clk), .Q(
Sgf_operation_ODD1_Q_left[30]), .QN(DP_OP_168J43_122_1342_n469) );
DFFTRX1TS Sgf_operation_ODD1_right_DatO_reg_45_ ( .D(1'b1), .RN(
Sgf_operation_ODD1_right_N45), .CK(clk), .Q(
Sgf_operation_ODD1_Q_right[45]), .QN(DP_OP_168J43_122_1342_n402) );
DFFTRX1TS Sgf_operation_ODD1_right_DatO_reg_41_ ( .D(1'b1), .RN(
Sgf_operation_ODD1_right_N41), .CK(clk), .Q(
Sgf_operation_ODD1_Q_right[41]), .QN(DP_OP_168J43_122_1342_n406) );
DFFTRX1TS Sgf_operation_ODD1_right_DatO_reg_42_ ( .D(1'b1), .RN(
Sgf_operation_ODD1_right_N42), .CK(clk), .Q(
Sgf_operation_ODD1_Q_right[42]), .QN(DP_OP_168J43_122_1342_n405) );
DFFTRX1TS Sgf_operation_ODD1_right_DatO_reg_36_ ( .D(1'b1), .RN(
Sgf_operation_ODD1_right_N36), .CK(clk), .Q(
Sgf_operation_ODD1_Q_right[36]), .QN(DP_OP_168J43_122_1342_n411) );
DFFTRX1TS Sgf_operation_ODD1_left_DatO_reg_26_ ( .D(1'b1), .RN(
Sgf_operation_ODD1_left_N26), .CK(clk), .Q(
Sgf_operation_ODD1_Q_left[26]), .QN(DP_OP_168J43_122_1342_n473) );
DFFTRX1TS Sgf_operation_ODD1_right_DatO_reg_35_ ( .D(1'b1), .RN(
Sgf_operation_ODD1_right_N35), .CK(clk), .Q(
Sgf_operation_ODD1_Q_right[35]), .QN(DP_OP_168J43_122_1342_n412) );
DFFTRX1TS Sgf_operation_ODD1_left_DatO_reg_36_ ( .D(1'b1), .RN(
Sgf_operation_ODD1_left_N36), .CK(clk), .Q(
Sgf_operation_ODD1_Q_left[36]), .QN(DP_OP_168J43_122_1342_n463) );
DFFTRX1TS Sgf_operation_ODD1_left_DatO_reg_40_ ( .D(1'b1), .RN(
Sgf_operation_ODD1_left_N40), .CK(clk), .Q(
Sgf_operation_ODD1_Q_left[40]), .QN(DP_OP_168J43_122_1342_n459) );
DFFTRX1TS Sgf_operation_ODD1_right_DatO_reg_29_ ( .D(1'b1), .RN(
Sgf_operation_ODD1_right_N29), .CK(clk), .Q(
Sgf_operation_ODD1_Q_right[29]), .QN(DP_OP_168J43_122_1342_n418) );
DFFTRX1TS Sgf_operation_ODD1_middle_DatO_reg_29_ ( .D(1'b1), .RN(
Sgf_operation_ODD1_middle_N29), .CK(clk), .Q(
Sgf_operation_ODD1_Q_middle[29]) );
DFFTRX1TS Sgf_operation_ODD1_right_DatO_reg_44_ ( .D(1'b1), .RN(
Sgf_operation_ODD1_right_N44), .CK(clk), .Q(
Sgf_operation_ODD1_Q_right[44]), .QN(DP_OP_168J43_122_1342_n403) );
DFFTRX1TS Sgf_operation_ODD1_right_DatO_reg_32_ ( .D(1'b1), .RN(
Sgf_operation_ODD1_right_N32), .CK(clk), .Q(
Sgf_operation_ODD1_Q_right[32]), .QN(DP_OP_168J43_122_1342_n415) );
DFFTRX1TS Sgf_operation_ODD1_left_DatO_reg_32_ ( .D(1'b1), .RN(
Sgf_operation_ODD1_left_N32), .CK(clk), .Q(
Sgf_operation_ODD1_Q_left[32]), .QN(DP_OP_168J43_122_1342_n467) );
DFFTRX1TS Sgf_operation_ODD1_left_DatO_reg_42_ ( .D(1'b1), .RN(
Sgf_operation_ODD1_left_N42), .CK(clk), .Q(
Sgf_operation_ODD1_Q_left[42]), .QN(DP_OP_168J43_122_1342_n457) );
DFFTRX1TS Sgf_operation_ODD1_left_DatO_reg_25_ ( .D(1'b1), .RN(
Sgf_operation_ODD1_left_N25), .CK(clk), .Q(
Sgf_operation_ODD1_Q_left[25]), .QN(DP_OP_168J43_122_1342_n474) );
DFFTRX1TS Sgf_operation_ODD1_right_DatO_reg_24_ ( .D(1'b1), .RN(
Sgf_operation_ODD1_right_N24), .CK(clk), .Q(Sgf_operation_Result[24]),
.QN(DP_OP_168J43_122_1342_n423) );
DFFTRX1TS Sgf_operation_ODD1_middle_DatO_reg_23_ ( .D(1'b1), .RN(
Sgf_operation_ODD1_middle_N23), .CK(clk), .Q(
Sgf_operation_ODD1_Q_middle[23]) );
DFFTRX1TS Sgf_operation_ODD1_middle_DatO_reg_24_ ( .D(1'b1), .RN(
Sgf_operation_ODD1_middle_N24), .CK(clk), .Q(
Sgf_operation_ODD1_Q_middle[24]) );
DFFTRX1TS Sgf_operation_ODD1_right_DatO_reg_34_ ( .D(1'b1), .RN(
Sgf_operation_ODD1_right_N34), .CK(clk), .Q(
Sgf_operation_ODD1_Q_right[34]), .QN(DP_OP_168J43_122_1342_n413) );
DFFTRX1TS Sgf_operation_ODD1_left_DatO_reg_29_ ( .D(1'b1), .RN(
Sgf_operation_ODD1_left_N29), .CK(clk), .Q(
Sgf_operation_ODD1_Q_left[29]), .QN(DP_OP_168J43_122_1342_n470) );
DFFTRX1TS Sgf_operation_ODD1_middle_DatO_reg_25_ ( .D(1'b1), .RN(
Sgf_operation_ODD1_middle_N25), .CK(clk), .Q(
Sgf_operation_ODD1_Q_middle[25]) );
DFFTRX1TS Sgf_operation_ODD1_right_DatO_reg_40_ ( .D(1'b1), .RN(
Sgf_operation_ODD1_right_N40), .CK(clk), .Q(
Sgf_operation_ODD1_Q_right[40]), .QN(DP_OP_168J43_122_1342_n407) );
DFFTRX1TS Sgf_operation_ODD1_right_DatO_reg_31_ ( .D(1'b1), .RN(
Sgf_operation_ODD1_right_N31), .CK(clk), .Q(
Sgf_operation_ODD1_Q_right[31]), .QN(DP_OP_168J43_122_1342_n416) );
DFFTRX1TS Sgf_operation_ODD1_middle_DatO_reg_21_ ( .D(1'b1), .RN(
Sgf_operation_ODD1_middle_N21), .CK(clk), .Q(
Sgf_operation_ODD1_Q_middle[21]) );
DFFTRX1TS Sgf_operation_ODD1_middle_DatO_reg_20_ ( .D(1'b1), .RN(
Sgf_operation_ODD1_middle_N20), .CK(clk), .Q(
Sgf_operation_ODD1_Q_middle[20]) );
DFFTRX1TS Sgf_operation_ODD1_right_DatO_reg_43_ ( .D(1'b1), .RN(
Sgf_operation_ODD1_right_N43), .CK(clk), .Q(
Sgf_operation_ODD1_Q_right[43]), .QN(DP_OP_168J43_122_1342_n404) );
DFFTRX1TS Sgf_operation_ODD1_left_DatO_reg_28_ ( .D(1'b1), .RN(
Sgf_operation_ODD1_left_N28), .CK(clk), .Q(
Sgf_operation_ODD1_Q_left[28]), .QN(DP_OP_168J43_122_1342_n471) );
DFFTRX1TS Sgf_operation_ODD1_right_DatO_reg_28_ ( .D(1'b1), .RN(
Sgf_operation_ODD1_right_N28), .CK(clk), .Q(
Sgf_operation_ODD1_Q_right[28]), .QN(DP_OP_168J43_122_1342_n419) );
DFFTRX1TS Sgf_operation_ODD1_right_DatO_reg_23_ ( .D(1'b1), .RN(
Sgf_operation_ODD1_right_N23), .CK(clk), .Q(Sgf_operation_Result[23]),
.QN(DP_OP_168J43_122_1342_n424) );
DFFTRX1TS Sgf_operation_ODD1_left_DatO_reg_24_ ( .D(1'b1), .RN(
Sgf_operation_ODD1_left_N24), .CK(clk), .Q(
Sgf_operation_ODD1_Q_left[24]), .QN(DP_OP_168J43_122_1342_n475) );
DFFTRX1TS Sgf_operation_ODD1_middle_DatO_reg_22_ ( .D(1'b1), .RN(
Sgf_operation_ODD1_middle_N22), .CK(clk), .Q(
Sgf_operation_ODD1_Q_middle[22]) );
DFFTRX1TS Sgf_operation_ODD1_right_DatO_reg_30_ ( .D(1'b1), .RN(
Sgf_operation_ODD1_right_N30), .CK(clk), .Q(
Sgf_operation_ODD1_Q_right[30]), .QN(DP_OP_168J43_122_1342_n417) );
DFFTRX1TS Sgf_operation_ODD1_right_DatO_reg_26_ ( .D(1'b1), .RN(
Sgf_operation_ODD1_right_N26), .CK(clk), .Q(Sgf_operation_Result[26]),
.QN(DP_OP_168J43_122_1342_n421) );
DFFTRX1TS Sgf_operation_ODD1_right_DatO_reg_27_ ( .D(1'b1), .RN(
Sgf_operation_ODD1_right_N27), .CK(clk), .Q(
Sgf_operation_ODD1_Q_right[27]), .QN(DP_OP_168J43_122_1342_n420) );
DFFTRX1TS Sgf_operation_ODD1_left_DatO_reg_27_ ( .D(1'b1), .RN(
Sgf_operation_ODD1_left_N27), .CK(clk), .Q(
Sgf_operation_ODD1_Q_left[27]), .QN(DP_OP_168J43_122_1342_n472) );
DFFTRX1TS Sgf_operation_ODD1_middle_DatO_reg_19_ ( .D(1'b1), .RN(
Sgf_operation_ODD1_middle_N19), .CK(clk), .Q(
Sgf_operation_ODD1_Q_middle[19]) );
DFFTRX1TS Sgf_operation_ODD1_right_DatO_reg_22_ ( .D(1'b1), .RN(
Sgf_operation_ODD1_right_N22), .CK(clk), .Q(Sgf_operation_Result[22]),
.QN(DP_OP_168J43_122_1342_n425) );
DFFTRX1TS Sgf_operation_ODD1_right_DatO_reg_25_ ( .D(1'b1), .RN(
Sgf_operation_ODD1_right_N25), .CK(clk), .Q(Sgf_operation_Result[25]),
.QN(DP_OP_168J43_122_1342_n422) );
DFFTRX1TS Sgf_operation_ODD1_left_DatO_reg_22_ ( .D(1'b1), .RN(
Sgf_operation_ODD1_left_N22), .CK(clk), .Q(
Sgf_operation_ODD1_Q_left[22]), .QN(DP_OP_168J43_122_1342_n477) );
DFFTRX1TS Sgf_operation_ODD1_left_DatO_reg_23_ ( .D(1'b1), .RN(
Sgf_operation_ODD1_left_N23), .CK(clk), .Q(
Sgf_operation_ODD1_Q_left[23]), .QN(DP_OP_168J43_122_1342_n476) );
DFFTRX1TS Sgf_operation_ODD1_left_DatO_reg_18_ ( .D(1'b1), .RN(
Sgf_operation_ODD1_left_N18), .CK(clk), .Q(
Sgf_operation_ODD1_Q_left[18]), .QN(DP_OP_168J43_122_1342_n481) );
DFFTRX1TS Sgf_operation_ODD1_left_DatO_reg_19_ ( .D(1'b1), .RN(
Sgf_operation_ODD1_left_N19), .CK(clk), .Q(
Sgf_operation_ODD1_Q_left[19]), .QN(DP_OP_168J43_122_1342_n480) );
DFFTRX1TS Sgf_operation_ODD1_middle_DatO_reg_17_ ( .D(1'b1), .RN(
Sgf_operation_ODD1_middle_N17), .CK(clk), .Q(
Sgf_operation_ODD1_Q_middle[17]) );
DFFTRX1TS Sgf_operation_ODD1_middle_DatO_reg_18_ ( .D(1'b1), .RN(
Sgf_operation_ODD1_middle_N18), .CK(clk), .Q(
Sgf_operation_ODD1_Q_middle[18]) );
DFFTRX1TS Sgf_operation_ODD1_left_DatO_reg_20_ ( .D(1'b1), .RN(
Sgf_operation_ODD1_left_N20), .CK(clk), .Q(
Sgf_operation_ODD1_Q_left[20]), .QN(DP_OP_168J43_122_1342_n479) );
DFFTRX1TS Sgf_operation_ODD1_right_DatO_reg_21_ ( .D(1'b1), .RN(
Sgf_operation_ODD1_right_N21), .CK(clk), .Q(Sgf_operation_Result[21]),
.QN(DP_OP_168J43_122_1342_n426) );
DFFTRX1TS Sgf_operation_ODD1_right_DatO_reg_20_ ( .D(1'b1), .RN(
Sgf_operation_ODD1_right_N20), .CK(clk), .Q(Sgf_operation_Result[20]),
.QN(DP_OP_168J43_122_1342_n427) );
DFFTRX1TS Sgf_operation_ODD1_right_DatO_reg_18_ ( .D(1'b1), .RN(
Sgf_operation_ODD1_right_N18), .CK(clk), .Q(Sgf_operation_Result[18]),
.QN(DP_OP_168J43_122_1342_n429) );
DFFTRX1TS Sgf_operation_ODD1_left_DatO_reg_17_ ( .D(1'b1), .RN(
Sgf_operation_ODD1_left_N17), .CK(clk), .Q(
Sgf_operation_ODD1_Q_left[17]), .QN(DP_OP_168J43_122_1342_n482) );
DFFTRX1TS Sgf_operation_ODD1_middle_DatO_reg_16_ ( .D(1'b1), .RN(
Sgf_operation_ODD1_middle_N16), .CK(clk), .Q(
Sgf_operation_ODD1_Q_middle[16]) );
DFFTRX1TS Sgf_operation_ODD1_left_DatO_reg_16_ ( .D(1'b1), .RN(
Sgf_operation_ODD1_left_N16), .CK(clk), .Q(
Sgf_operation_ODD1_Q_left[16]), .QN(DP_OP_168J43_122_1342_n483) );
DFFTRX1TS Sgf_operation_ODD1_right_DatO_reg_19_ ( .D(1'b1), .RN(
Sgf_operation_ODD1_right_N19), .CK(clk), .Q(Sgf_operation_Result[19]),
.QN(DP_OP_168J43_122_1342_n428) );
DFFTRX1TS Sgf_operation_ODD1_left_DatO_reg_14_ ( .D(1'b1), .RN(
Sgf_operation_ODD1_left_N14), .CK(clk), .Q(
Sgf_operation_ODD1_Q_left[14]), .QN(DP_OP_168J43_122_1342_n485) );
DFFTRX1TS Sgf_operation_ODD1_right_DatO_reg_17_ ( .D(1'b1), .RN(
Sgf_operation_ODD1_right_N17), .CK(clk), .Q(Sgf_operation_Result[17]),
.QN(DP_OP_168J43_122_1342_n430) );
DFFTRX1TS Sgf_operation_ODD1_left_DatO_reg_15_ ( .D(1'b1), .RN(
Sgf_operation_ODD1_left_N15), .CK(clk), .Q(
Sgf_operation_ODD1_Q_left[15]), .QN(DP_OP_168J43_122_1342_n484) );
DFFTRX1TS Sgf_operation_ODD1_middle_DatO_reg_14_ ( .D(1'b1), .RN(
Sgf_operation_ODD1_middle_N14), .CK(clk), .Q(
Sgf_operation_ODD1_Q_middle[14]) );
DFFTRX1TS Sgf_operation_ODD1_middle_DatO_reg_13_ ( .D(1'b1), .RN(
Sgf_operation_ODD1_middle_N13), .CK(clk), .Q(
Sgf_operation_ODD1_Q_middle[13]) );
DFFTRX1TS Sgf_operation_ODD1_left_DatO_reg_13_ ( .D(1'b1), .RN(
Sgf_operation_ODD1_left_N13), .CK(clk), .Q(
Sgf_operation_ODD1_Q_left[13]), .QN(DP_OP_168J43_122_1342_n486) );
DFFTRX1TS Sgf_operation_ODD1_left_DatO_reg_12_ ( .D(1'b1), .RN(
Sgf_operation_ODD1_left_N12), .CK(clk), .Q(
Sgf_operation_ODD1_Q_left[12]), .QN(DP_OP_168J43_122_1342_n487) );
DFFTRX1TS Sgf_operation_ODD1_right_DatO_reg_16_ ( .D(1'b1), .RN(
Sgf_operation_ODD1_right_N16), .CK(clk), .Q(Sgf_operation_Result[16]),
.QN(DP_OP_168J43_122_1342_n431) );
DFFTRX1TS Sgf_operation_ODD1_right_DatO_reg_15_ ( .D(1'b1), .RN(
Sgf_operation_ODD1_right_N15), .CK(clk), .Q(Sgf_operation_Result[15]),
.QN(DP_OP_168J43_122_1342_n432) );
DFFTRX1TS Sgf_operation_ODD1_middle_DatO_reg_11_ ( .D(1'b1), .RN(
Sgf_operation_ODD1_middle_N11), .CK(clk), .Q(
Sgf_operation_ODD1_Q_middle[11]) );
DFFTRX1TS Sgf_operation_ODD1_left_DatO_reg_10_ ( .D(1'b1), .RN(
Sgf_operation_ODD1_left_N10), .CK(clk), .Q(
Sgf_operation_ODD1_Q_left[10]), .QN(DP_OP_168J43_122_1342_n489) );
DFFTRX1TS Sgf_operation_ODD1_right_DatO_reg_13_ ( .D(1'b1), .RN(
Sgf_operation_ODD1_right_N13), .CK(clk), .Q(Sgf_operation_Result[13]),
.QN(DP_OP_168J43_122_1342_n434) );
DFFTRX1TS Sgf_operation_ODD1_middle_DatO_reg_9_ ( .D(1'b1), .RN(
Sgf_operation_ODD1_middle_N9), .CK(clk), .Q(
Sgf_operation_ODD1_Q_middle[9]) );
DFFTRX1TS Sgf_operation_ODD1_middle_DatO_reg_12_ ( .D(1'b1), .RN(
Sgf_operation_ODD1_middle_N12), .CK(clk), .Q(
Sgf_operation_ODD1_Q_middle[12]) );
DFFTRX1TS Sgf_operation_ODD1_right_DatO_reg_14_ ( .D(1'b1), .RN(
Sgf_operation_ODD1_right_N14), .CK(clk), .Q(Sgf_operation_Result[14]),
.QN(DP_OP_168J43_122_1342_n433) );
DFFTRX1TS Sgf_operation_ODD1_middle_DatO_reg_10_ ( .D(1'b1), .RN(
Sgf_operation_ODD1_middle_N10), .CK(clk), .Q(
Sgf_operation_ODD1_Q_middle[10]) );
DFFTRX1TS Sgf_operation_ODD1_left_DatO_reg_9_ ( .D(1'b1), .RN(
Sgf_operation_ODD1_left_N9), .CK(clk), .Q(Sgf_operation_ODD1_Q_left[9]), .QN(DP_OP_168J43_122_1342_n490) );
DFFTRX1TS Sgf_operation_ODD1_right_DatO_reg_12_ ( .D(1'b1), .RN(
Sgf_operation_ODD1_right_N12), .CK(clk), .Q(Sgf_operation_Result[12]),
.QN(DP_OP_168J43_122_1342_n435) );
DFFTRX1TS Sgf_operation_ODD1_middle_DatO_reg_8_ ( .D(1'b1), .RN(
Sgf_operation_ODD1_middle_N8), .CK(clk), .Q(
Sgf_operation_ODD1_Q_middle[8]) );
DFFTRX1TS Sgf_operation_ODD1_right_DatO_reg_9_ ( .D(1'b1), .RN(
Sgf_operation_ODD1_right_N9), .CK(clk), .Q(Sgf_operation_Result[9]),
.QN(DP_OP_168J43_122_1342_n438) );
DFFTRX1TS Sgf_operation_ODD1_right_DatO_reg_11_ ( .D(1'b1), .RN(
Sgf_operation_ODD1_right_N11), .CK(clk), .Q(Sgf_operation_Result[11]),
.QN(DP_OP_168J43_122_1342_n436) );
DFFTRX1TS Sgf_operation_ODD1_middle_DatO_reg_7_ ( .D(1'b1), .RN(
Sgf_operation_ODD1_middle_N7), .CK(clk), .Q(
Sgf_operation_ODD1_Q_middle[7]) );
DFFTRX1TS Sgf_operation_ODD1_right_DatO_reg_10_ ( .D(1'b1), .RN(
Sgf_operation_ODD1_right_N10), .CK(clk), .Q(Sgf_operation_Result[10]),
.QN(DP_OP_168J43_122_1342_n437) );
DFFTRX1TS Sgf_operation_ODD1_left_DatO_reg_8_ ( .D(1'b1), .RN(
Sgf_operation_ODD1_left_N8), .CK(clk), .Q(Sgf_operation_ODD1_Q_left[8]), .QN(DP_OP_168J43_122_1342_n491) );
DFFTRX1TS Sgf_operation_ODD1_right_DatO_reg_8_ ( .D(1'b1), .RN(
Sgf_operation_ODD1_right_N8), .CK(clk), .Q(Sgf_operation_Result[8]),
.QN(DP_OP_168J43_122_1342_n439) );
DFFTRX1TS Sgf_operation_ODD1_middle_DatO_reg_6_ ( .D(1'b1), .RN(
Sgf_operation_ODD1_middle_N6), .CK(clk), .Q(
Sgf_operation_ODD1_Q_middle[6]) );
DFFTRX1TS Sgf_operation_ODD1_left_DatO_reg_7_ ( .D(1'b1), .RN(
Sgf_operation_ODD1_left_N7), .CK(clk), .Q(Sgf_operation_ODD1_Q_left[7]), .QN(DP_OP_168J43_122_1342_n492) );
DFFTRX1TS Sgf_operation_ODD1_middle_DatO_reg_5_ ( .D(1'b1), .RN(
Sgf_operation_ODD1_middle_N5), .CK(clk), .Q(
Sgf_operation_ODD1_Q_middle[5]) );
DFFTRX1TS Sgf_operation_ODD1_right_DatO_reg_6_ ( .D(1'b1), .RN(
Sgf_operation_ODD1_right_N6), .CK(clk), .Q(Sgf_operation_Result[6]),
.QN(DP_OP_168J43_122_1342_n441) );
DFFTRX1TS Sgf_operation_ODD1_middle_DatO_reg_4_ ( .D(1'b1), .RN(
Sgf_operation_ODD1_middle_N4), .CK(clk), .Q(
Sgf_operation_ODD1_Q_middle[4]) );
DFFTRX1TS Sgf_operation_ODD1_right_DatO_reg_7_ ( .D(1'b1), .RN(
Sgf_operation_ODD1_right_N7), .CK(clk), .Q(Sgf_operation_Result[7]),
.QN(DP_OP_168J43_122_1342_n440) );
DFFTRX1TS Sgf_operation_ODD1_right_DatO_reg_5_ ( .D(1'b1), .RN(
Sgf_operation_ODD1_right_N5), .CK(clk), .Q(Sgf_operation_Result[5]),
.QN(DP_OP_168J43_122_1342_n442) );
DFFTRX1TS Sgf_operation_ODD1_left_DatO_reg_5_ ( .D(1'b1), .RN(
Sgf_operation_ODD1_left_N5), .CK(clk), .Q(Sgf_operation_ODD1_Q_left[5]), .QN(DP_OP_168J43_122_1342_n494) );
DFFTRX1TS Sgf_operation_ODD1_middle_DatO_reg_3_ ( .D(1'b1), .RN(
Sgf_operation_ODD1_middle_N3), .CK(clk), .Q(
Sgf_operation_ODD1_Q_middle[3]) );
DFFTRX1TS Sgf_operation_ODD1_left_DatO_reg_4_ ( .D(1'b1), .RN(
Sgf_operation_ODD1_left_N4), .CK(clk), .Q(Sgf_operation_ODD1_Q_left[4]), .QN(DP_OP_168J43_122_1342_n495) );
DFFTRX1TS Sgf_operation_ODD1_right_DatO_reg_4_ ( .D(1'b1), .RN(
Sgf_operation_ODD1_right_N4), .CK(clk), .Q(Sgf_operation_Result[4]),
.QN(DP_OP_168J43_122_1342_n443) );
DFFTRX1TS Sgf_operation_ODD1_left_DatO_reg_3_ ( .D(1'b1), .RN(
Sgf_operation_ODD1_left_N3), .CK(clk), .Q(Sgf_operation_ODD1_Q_left[3]), .QN(DP_OP_168J43_122_1342_n496) );
DFFTRX1TS Sgf_operation_ODD1_middle_DatO_reg_2_ ( .D(1'b1), .RN(
Sgf_operation_ODD1_middle_N2), .CK(clk), .Q(
Sgf_operation_ODD1_Q_middle[2]) );
DFFTRX1TS Sgf_operation_ODD1_right_DatO_reg_3_ ( .D(1'b1), .RN(
Sgf_operation_ODD1_right_N3), .CK(clk), .Q(Sgf_operation_Result[3]),
.QN(DP_OP_168J43_122_1342_n444) );
DFFTRX1TS Sgf_operation_ODD1_left_DatO_reg_2_ ( .D(1'b1), .RN(
Sgf_operation_ODD1_left_N2), .CK(clk), .Q(Sgf_operation_ODD1_Q_left[2]), .QN(DP_OP_168J43_122_1342_n497) );
DFFTRX1TS Sgf_operation_ODD1_right_DatO_reg_2_ ( .D(1'b1), .RN(
Sgf_operation_ODD1_right_N2), .CK(clk), .Q(Sgf_operation_Result[2]),
.QN(DP_OP_168J43_122_1342_n445) );
DFFTRX1TS Sgf_operation_ODD1_left_DatO_reg_1_ ( .D(1'b1), .RN(
Sgf_operation_ODD1_left_N1), .CK(clk), .Q(Sgf_operation_ODD1_Q_left[1]), .QN(DP_OP_168J43_122_1342_n498) );
DFFTRX1TS Sgf_operation_ODD1_right_DatO_reg_0_ ( .D(1'b1), .RN(
mult_x_24_n2066), .CK(clk), .Q(Sgf_operation_Result[0]), .QN(
DP_OP_168J43_122_1342_n447) );
DFFTRX1TS Sgf_operation_ODD1_middle_DatO_reg_39_ ( .D(1'b1), .RN(
Sgf_operation_ODD1_middle_N39), .CK(clk), .Q(
Sgf_operation_ODD1_Q_middle[39]) );
DFFTRX1TS Sgf_operation_ODD1_middle_DatO_reg_32_ ( .D(1'b1), .RN(
Sgf_operation_ODD1_middle_N32), .CK(clk), .Q(
Sgf_operation_ODD1_Q_middle[32]) );
DFFTRX1TS Sgf_operation_ODD1_middle_DatO_reg_38_ ( .D(1'b1), .RN(
Sgf_operation_ODD1_middle_N38), .CK(clk), .Q(
Sgf_operation_ODD1_Q_middle[38]) );
CMPR42X1TS mult_x_24_U666 ( .A(mult_x_24_n730), .B(mult_x_24_n1462), .C(
mult_x_24_n1435), .D(mult_x_24_n1516), .ICI(mult_x_24_n731), .S(
mult_x_24_n717), .ICO(mult_x_24_n715), .CO(mult_x_24_n716) );
DFFTRX1TS Sgf_operation_ODD1_left_DatO_reg_41_ ( .D(1'b1), .RN(
Sgf_operation_ODD1_left_N41), .CK(clk), .QN(DP_OP_168J43_122_1342_n458) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_5_ ( .D(n651), .CK(clk), .RN(
n6619), .Q(Op_MX[5]) );
DFFRX2TS Operands_load_reg_YMRegister_Q_reg_2_ ( .D(n584), .CK(clk), .RN(
n6622), .Q(Op_MY[2]), .QN(n6551) );
DFFRX4TS Operands_load_reg_XMRegister_Q_reg_0_ ( .D(n646), .CK(clk), .RN(
n6609), .Q(Op_MX[0]), .QN(n6547) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_27_ ( .D(n609), .CK(clk), .RN(
n6624), .Q(Op_MY[27]), .QN(n6546) );
DFFRX2TS Operands_load_reg_YMRegister_Q_reg_26_ ( .D(n608), .CK(clk), .RN(
n6616), .Q(Op_MY[26]), .QN(n6545) );
DFFRX4TS Operands_load_reg_XMRegister_Q_reg_26_ ( .D(n672), .CK(clk), .RN(
n796), .Q(Op_MX[26]), .QN(n6548) );
DFFRX4TS Operands_load_reg_XMRegister_Q_reg_38_ ( .D(n684), .CK(clk), .RN(
n6621), .Q(n6588), .QN(n6556) );
DFFRX4TS Operands_load_reg_XMRegister_Q_reg_44_ ( .D(n690), .CK(clk), .RN(
n6621), .Q(n6587), .QN(n6560) );
DFFRX4TS Operands_load_reg_XMRegister_Q_reg_50_ ( .D(n696), .CK(clk), .RN(
n1630), .Q(n6586), .QN(n6566) );
CMPR42X1TS mult_x_24_U703 ( .A(mult_x_24_n1525), .B(mult_x_24_n832), .C(
mult_x_24_n833), .D(mult_x_24_n823), .ICI(mult_x_24_n829), .S(
mult_x_24_n820), .ICO(mult_x_24_n818), .CO(mult_x_24_n819) );
CMPR42X1TS mult_x_24_U631 ( .A(mult_x_24_n633), .B(mult_x_24_n629), .C(
mult_x_24_n634), .D(mult_x_24_n626), .ICI(mult_x_24_n630), .S(
mult_x_24_n623), .ICO(mult_x_24_n621), .CO(mult_x_24_n622) );
CMPR42X1TS mult_x_24_U680 ( .A(mult_x_24_n777), .B(mult_x_24_n765), .C(
mult_x_24_n774), .D(mult_x_24_n762), .ICI(mult_x_24_n770), .S(
mult_x_24_n759), .ICO(mult_x_24_n757), .CO(mult_x_24_n758) );
DFFRX4TS Sel_A_Q_reg_0_ ( .D(n710), .CK(clk), .RN(n6617), .Q(FSM_selector_A),
.QN(n6574) );
CLKMX2X2TS U746 ( .A(P_Sgf[88]), .B(n5773), .S0(n5792), .Y(n509) );
ADDHXLTS U747 ( .A(Sgf_normalized_result[50]), .B(n5642), .CO(n5633), .S(
n5643) );
ADDHXLTS U748 ( .A(Sgf_normalized_result[49]), .B(n5647), .CO(n5642), .S(
n5648) );
NOR2X1TS U749 ( .A(n5813), .B(n5825), .Y(n1417) );
OAI21X1TS U750 ( .A0(n5813), .A1(n5826), .B0(n5814), .Y(n1416) );
ADDHXLTS U751 ( .A(Sgf_normalized_result[47]), .B(n5665), .CO(n5653), .S(
n5666) );
NAND2X1TS U752 ( .A(n1414), .B(Sgf_operation_ODD1_Q_left[28]), .Y(n5826) );
NAND2X1TS U753 ( .A(n1415), .B(Sgf_operation_ODD1_Q_left[29]), .Y(n5814) );
XOR2X1TS U754 ( .A(n1036), .B(Sgf_operation_ODD1_Q_middle[55]), .Y(n1414) );
ADDHXLTS U755 ( .A(Sgf_normalized_result[46]), .B(n5677), .CO(n5665), .S(
n5678) );
INVX1TS U756 ( .A(n1035), .Y(n1415) );
NAND2X1TS U757 ( .A(n1411), .B(Sgf_operation_ODD1_Q_left[26]), .Y(n5848) );
ADDHXLTS U758 ( .A(Sgf_normalized_result[45]), .B(n5686), .CO(n5677), .S(
n5687) );
ADDHXLTS U759 ( .A(Sgf_normalized_result[44]), .B(n5695), .CO(n5686), .S(
n5696) );
ADDHXLTS U760 ( .A(Sgf_normalized_result[43]), .B(n5703), .CO(n5695), .S(
n5704) );
AOI21X1TS U761 ( .A0(n2519), .A1(n2525), .B0(n2518), .Y(n4662) );
CMPR32X2TS U762 ( .A(Sgf_operation_ODD1_Q_middle[51]), .B(n922), .C(n921),
.CO(n1409), .S(n1043) );
NOR2X1TS U763 ( .A(n2528), .B(n2530), .Y(n2519) );
NAND2X1TS U764 ( .A(DP_OP_169J43_123_4229_n929), .B(
DP_OP_169J43_123_4229_n946), .Y(n2631) );
NAND2X1TS U765 ( .A(DP_OP_169J43_123_4229_n1009), .B(
DP_OP_169J43_123_4229_n1029), .Y(n4814) );
NOR2X1TS U766 ( .A(DP_OP_169J43_123_4229_n929), .B(
DP_OP_169J43_123_4229_n946), .Y(n2629) );
CMPR32X2TS U767 ( .A(Sgf_operation_ODD1_Q_middle[50]), .B(n924), .C(n923),
.CO(n1044), .S(n1402) );
AOI21X2TS U768 ( .A0(n2547), .A1(n3939), .B0(n2546), .Y(n3910) );
CMPR32X2TS U769 ( .A(Sgf_operation_ODD1_Q_middle[49]), .B(n926), .C(n925),
.CO(n1403), .S(n1047) );
OAI21X2TS U770 ( .A0(n2969), .A1(n2435), .B0(n2434), .Y(n3150) );
NAND2X1TS U771 ( .A(mult_x_23_n568), .B(mult_x_23_n575), .Y(n3093) );
NOR2X1TS U772 ( .A(mult_x_23_n713), .B(mult_x_23_n723), .Y(n3139) );
CMPR32X2TS U773 ( .A(Sgf_operation_ODD1_Q_middle[48]), .B(n928), .C(n927),
.CO(n1046), .S(n1396) );
NAND2X1TS U774 ( .A(mult_x_23_n586), .B(mult_x_23_n595), .Y(n3104) );
AOI21X1TS U775 ( .A0(n2499), .A1(n2498), .B0(n2497), .Y(n4893) );
CMPR32X2TS U776 ( .A(Sgf_operation_ODD1_Q_middle[47]), .B(n930), .C(n929),
.CO(n1397), .S(n1050) );
CMPR32X2TS U777 ( .A(Sgf_operation_ODD1_Q_middle[46]), .B(
DP_OP_168J43_122_1342_n401), .C(n5657), .CO(n1049), .S(n1390) );
CMPR42X1TS U778 ( .A(mult_x_23_n605), .B(mult_x_23_n601), .C(mult_x_23_n606),
.D(mult_x_23_n599), .ICI(mult_x_23_n602), .S(mult_x_23_n596), .ICO(
mult_x_23_n594), .CO(mult_x_23_n595) );
CMPR42X1TS U779 ( .A(mult_x_23_n600), .B(mult_x_23_n597), .C(mult_x_23_n589),
.D(mult_x_23_n598), .ICI(mult_x_23_n594), .S(mult_x_23_n586), .ICO(
mult_x_23_n584), .CO(mult_x_23_n585) );
AOI21X1TS U780 ( .A0(n2412), .A1(n2411), .B0(n2410), .Y(n3188) );
CMPR32X2TS U781 ( .A(Sgf_operation_ODD1_Q_middle[45]), .B(
DP_OP_168J43_122_1342_n454), .C(DP_OP_168J43_122_1342_n402), .CO(n1391), .S(n1053) );
CMPR32X2TS U782 ( .A(Sgf_operation_ODD1_Q_middle[44]), .B(
DP_OP_168J43_122_1342_n403), .C(DP_OP_168J43_122_1342_n455), .CO(n1052), .S(n1384) );
CMPR42X1TS U783 ( .A(mult_x_24_n653), .B(mult_x_24_n648), .C(mult_x_24_n654),
.D(mult_x_24_n645), .ICI(mult_x_24_n650), .S(mult_x_24_n642), .ICO(
mult_x_24_n640), .CO(mult_x_24_n641) );
CMPR32X2TS U784 ( .A(Sgf_operation_ODD1_Q_middle[43]), .B(
DP_OP_168J43_122_1342_n456), .C(DP_OP_168J43_122_1342_n404), .CO(n1385), .S(n1380) );
CMPR32X2TS U785 ( .A(Sgf_operation_ODD1_Q_middle[42]), .B(
DP_OP_168J43_122_1342_n405), .C(DP_OP_168J43_122_1342_n457), .CO(n1379), .S(n1375) );
INVX2TS U786 ( .A(n1786), .Y(n3680) );
CMPR32X2TS U787 ( .A(Sgf_operation_ODD1_Q_middle[41]), .B(
DP_OP_168J43_122_1342_n458), .C(DP_OP_168J43_122_1342_n406), .CO(n1376), .S(n1371) );
CMPR32X2TS U788 ( .A(n2335), .B(n2334), .C(n2333), .CO(n2394), .S(n2393) );
INVX2TS U789 ( .A(n2714), .Y(n3668) );
NOR2X1TS U790 ( .A(n1967), .B(n4964), .Y(n4954) );
NOR2XLTS U791 ( .A(n2827), .B(n4971), .Y(n2828) );
INVX2TS U792 ( .A(n1888), .Y(n3701) );
CMPR32X2TS U793 ( .A(Sgf_operation_ODD1_Q_middle[40]), .B(
DP_OP_168J43_122_1342_n407), .C(DP_OP_168J43_122_1342_n459), .CO(n1370), .S(n1055) );
NOR2X1TS U794 ( .A(n1938), .B(n4971), .Y(DP_OP_169J43_123_4229_n889) );
INVX2TS U795 ( .A(n1607), .Y(n3723) );
CMPR32X2TS U796 ( .A(Sgf_operation_ODD1_Q_middle[39]), .B(
DP_OP_168J43_122_1342_n460), .C(n931), .CO(n1056), .S(n1059) );
ADDHXLTS U797 ( .A(n3330), .B(n3329), .CO(n3341), .S(mult_x_23_n789) );
BUFX4TS U798 ( .A(n1532), .Y(n5577) );
OAI21X1TS U799 ( .A0(n2713), .A1(n1771), .B0(n1773), .Y(n1794) );
CMPR32X2TS U800 ( .A(Sgf_operation_ODD1_Q_middle[38]), .B(n932), .C(
DP_OP_168J43_122_1342_n461), .CO(n1058), .S(n1360) );
INVX2TS U801 ( .A(n1614), .Y(n3652) );
INVX4TS U802 ( .A(n4685), .Y(n4684) );
CMPR32X2TS U803 ( .A(Sgf_operation_ODD1_Q_middle[37]), .B(
DP_OP_168J43_122_1342_n462), .C(DP_OP_168J43_122_1342_n410), .CO(n1361), .S(n1357) );
INVX2TS U804 ( .A(n2256), .Y(n3590) );
INVX2TS U805 ( .A(n2207), .Y(n3585) );
BUFX4TS U806 ( .A(n1459), .Y(n2741) );
OAI21X1TS U807 ( .A0(n2653), .A1(n2486), .B0(n2485), .Y(n2705) );
CMPR32X2TS U808 ( .A(Sgf_operation_ODD1_Q_middle[36]), .B(
DP_OP_168J43_122_1342_n411), .C(DP_OP_168J43_122_1342_n463), .CO(n1356), .S(n1330) );
NOR2X1TS U809 ( .A(n2486), .B(n1713), .Y(n1715) );
BUFX3TS U810 ( .A(n1787), .Y(n3407) );
NAND2X1TS U811 ( .A(n3412), .B(n3312), .Y(n2858) );
INVX4TS U812 ( .A(n1608), .Y(n1609) );
CMPR32X2TS U813 ( .A(Sgf_operation_ODD1_Q_middle[35]), .B(
DP_OP_168J43_122_1342_n464), .C(DP_OP_168J43_122_1342_n412), .CO(n1331), .S(n1334) );
NAND2X1TS U814 ( .A(n1463), .B(n2679), .Y(n1465) );
NOR2X1TS U815 ( .A(n1688), .B(n2881), .Y(n1690) );
NOR2BX1TS U816 ( .AN(n2776), .B(n2775), .Y(n2774) );
NOR2BX1TS U817 ( .AN(n1745), .B(n1744), .Y(n1788) );
NAND2BX1TS U818 ( .AN(n1745), .B(n5000), .Y(n1787) );
NOR2X1TS U819 ( .A(n2777), .B(n2776), .Y(n2786) );
CLKINVX6TS U820 ( .A(DP_OP_169J43_123_4229_n2318), .Y(n5548) );
NAND2X1TS U821 ( .A(n3703), .B(n3698), .Y(n1915) );
NAND3X1TS U822 ( .A(n2718), .B(n2717), .C(n2716), .Y(n2719) );
NAND2X1TS U823 ( .A(n867), .B(n866), .Y(n1994) );
NOR2X1TS U824 ( .A(n1559), .B(n1571), .Y(n1461) );
NAND2X1TS U825 ( .A(n1317), .B(Sgf_operation_ODD1_Q_left[4]), .Y(n6108) );
NOR2BX1TS U826 ( .AN(n2754), .B(n2753), .Y(n2780) );
NOR2BX1TS U827 ( .AN(n1840), .B(n1839), .Y(n1872) );
AOI21X1TS U828 ( .A0(n1663), .A1(n1982), .B0(n1662), .Y(n2005) );
NAND2BX4TS U829 ( .AN(n2317), .B(n2318), .Y(n2307) );
NOR2X1TS U830 ( .A(n2755), .B(n2754), .Y(n2867) );
NAND2X1TS U831 ( .A(n3748), .B(n3742), .Y(n2573) );
NOR2X1TS U832 ( .A(n3737), .B(n3731), .Y(n2654) );
NOR2X1TS U833 ( .A(n3742), .B(n3737), .Y(n2575) );
NAND2X1TS U834 ( .A(n3742), .B(n3737), .Y(n2576) );
NOR2X1TS U835 ( .A(n1480), .B(n1518), .Y(n1452) );
INVX4TS U836 ( .A(n771), .Y(n729) );
CMPR32X2TS U837 ( .A(Sgf_operation_ODD1_Q_middle[34]), .B(
DP_OP_168J43_122_1342_n413), .C(DP_OP_168J43_122_1342_n465), .CO(n1333), .S(n1032) );
CLKBUFX2TS U838 ( .A(n6586), .Y(n786) );
NOR2BX1TS U839 ( .AN(n2209), .B(n2208), .Y(n2226) );
NOR2X1TS U840 ( .A(n2210), .B(n2209), .Y(n2222) );
CMPR32X2TS U841 ( .A(Sgf_operation_ODD1_Q_middle[32]), .B(
DP_OP_168J43_122_1342_n415), .C(DP_OP_168J43_122_1342_n467), .CO(n1028), .S(n1026) );
CMPR32X2TS U842 ( .A(Sgf_operation_ODD1_Q_middle[33]), .B(
DP_OP_168J43_122_1342_n466), .C(DP_OP_168J43_122_1342_n414), .CO(n1031), .S(n1027) );
BUFX4TS U843 ( .A(Op_MY[30]), .Y(n3582) );
BUFX4TS U844 ( .A(Op_MY[33]), .Y(n3650) );
NOR2X1TS U845 ( .A(n1286), .B(n1281), .Y(n1269) );
BUFX4TS U846 ( .A(n789), .Y(n4639) );
BUFX4TS U847 ( .A(n794), .Y(n4632) );
BUFX4TS U848 ( .A(n795), .Y(n4536) );
CMPR32X2TS U849 ( .A(Sgf_operation_ODD1_Q_middle[28]), .B(
DP_OP_168J43_122_1342_n471), .C(DP_OP_168J43_122_1342_n419), .CO(n1011), .S(n1010) );
CMPR32X2TS U850 ( .A(Sgf_operation_ODD1_Q_middle[30]), .B(
DP_OP_168J43_122_1342_n417), .C(DP_OP_168J43_122_1342_n469), .CO(n1015), .S(n1014) );
CMPR32X2TS U851 ( .A(Sgf_operation_ODD1_Q_middle[31]), .B(
DP_OP_168J43_122_1342_n416), .C(DP_OP_168J43_122_1342_n468), .CO(n1025), .S(n1016) );
CMPR32X2TS U852 ( .A(Sgf_operation_ODD1_Q_middle[29]), .B(
DP_OP_168J43_122_1342_n470), .C(DP_OP_168J43_122_1342_n418), .CO(n1013), .S(n1012) );
NOR2X1TS U853 ( .A(n1302), .B(n1297), .Y(n1255) );
NOR2X1TS U854 ( .A(n1061), .B(n998), .Y(n1252) );
CMPR32X2TS U855 ( .A(Sgf_operation_ODD1_Q_middle[27]), .B(
DP_OP_168J43_122_1342_n472), .C(DP_OP_168J43_122_1342_n420), .CO(n1009), .S(n1006) );
CMPR32X2TS U856 ( .A(Sgf_operation_ODD1_Q_middle[26]), .B(
DP_OP_168J43_122_1342_n421), .C(DP_OP_168J43_122_1342_n473), .CO(n1005), .S(n1004) );
CMPR32X2TS U857 ( .A(Sgf_operation_ODD1_Q_middle[24]), .B(
DP_OP_168J43_122_1342_n423), .C(DP_OP_168J43_122_1342_n475), .CO(n1001), .S(n1000) );
CMPR32X2TS U858 ( .A(Sgf_operation_ODD1_Q_middle[25]), .B(
DP_OP_168J43_122_1342_n422), .C(DP_OP_168J43_122_1342_n474), .CO(n1003), .S(n1002) );
NOR2X1TS U859 ( .A(n1216), .B(n1218), .Y(n1205) );
NAND2X1TS U860 ( .A(n982), .B(n981), .Y(n1212) );
NAND2X1TS U861 ( .A(n988), .B(n987), .Y(n1076) );
NAND2X1TS U862 ( .A(n984), .B(n983), .Y(n1207) );
NAND2X1TS U863 ( .A(n990), .B(n989), .Y(n1071) );
NAND2X1TS U864 ( .A(n980), .B(n979), .Y(n1219) );
NOR2X2TS U865 ( .A(n980), .B(n979), .Y(n1218) );
CMPR32X2TS U866 ( .A(Sgf_operation_ODD1_Q_middle[17]), .B(
DP_OP_168J43_122_1342_n430), .C(DP_OP_168J43_122_1342_n482), .CO(n981),
.S(n980) );
CMPR32X2TS U867 ( .A(Sgf_operation_ODD1_Q_middle[18]), .B(
DP_OP_168J43_122_1342_n429), .C(DP_OP_168J43_122_1342_n481), .CO(n983),
.S(n982) );
CMPR32X2TS U868 ( .A(Sgf_operation_ODD1_Q_middle[19]), .B(
DP_OP_168J43_122_1342_n428), .C(DP_OP_168J43_122_1342_n480), .CO(n987),
.S(n984) );
CMPR32X2TS U869 ( .A(Sgf_operation_ODD1_Q_middle[23]), .B(
DP_OP_168J43_122_1342_n424), .C(DP_OP_168J43_122_1342_n476), .CO(n999),
.S(n994) );
CMPR32X2TS U870 ( .A(Sgf_operation_ODD1_Q_middle[16]), .B(
DP_OP_168J43_122_1342_n431), .C(DP_OP_168J43_122_1342_n483), .CO(n979),
.S(n978) );
CMPR32X2TS U871 ( .A(Sgf_operation_ODD1_Q_middle[22]), .B(
DP_OP_168J43_122_1342_n425), .C(DP_OP_168J43_122_1342_n477), .CO(n993),
.S(n992) );
CMPR32X2TS U872 ( .A(Sgf_operation_ODD1_Q_middle[21]), .B(
DP_OP_168J43_122_1342_n426), .C(DP_OP_168J43_122_1342_n478), .CO(n991),
.S(n990) );
CMPR32X2TS U873 ( .A(Sgf_operation_ODD1_Q_middle[20]), .B(
DP_OP_168J43_122_1342_n427), .C(DP_OP_168J43_122_1342_n479), .CO(n989),
.S(n988) );
NOR2X1TS U874 ( .A(n1089), .B(n1092), .Y(n1083) );
NAND2X1TS U875 ( .A(n956), .B(n955), .Y(n1125) );
NAND2X1TS U876 ( .A(n968), .B(n967), .Y(n1195) );
NAND2X1TS U877 ( .A(n946), .B(n945), .Y(n1172) );
NAND2X1TS U878 ( .A(n958), .B(n957), .Y(n1108) );
NOR2X1TS U879 ( .A(n968), .B(n967), .Y(n1087) );
CMPR32X2TS U880 ( .A(Sgf_operation_ODD1_Q_middle[14]), .B(
DP_OP_168J43_122_1342_n433), .C(DP_OP_168J43_122_1342_n485), .CO(n969),
.S(n968) );
CMPR32X2TS U881 ( .A(Sgf_operation_ODD1_Q_middle[7]), .B(
DP_OP_168J43_122_1342_n440), .C(DP_OP_168J43_122_1342_n492), .CO(n953),
.S(n948) );
CMPR32X2TS U882 ( .A(Sgf_operation_ODD1_Q_middle[3]), .B(
DP_OP_168J43_122_1342_n444), .C(DP_OP_168J43_122_1342_n496), .CO(n941),
.S(n938) );
CMPR32X2TS U883 ( .A(Sgf_operation_ODD1_Q_middle[9]), .B(
DP_OP_168J43_122_1342_n438), .C(DP_OP_168J43_122_1342_n490), .CO(n957),
.S(n956) );
CMPR32X2TS U884 ( .A(Sgf_operation_ODD1_Q_middle[5]), .B(
DP_OP_168J43_122_1342_n442), .C(DP_OP_168J43_122_1342_n494), .CO(n945),
.S(n944) );
CMPR32X2TS U885 ( .A(Sgf_operation_ODD1_Q_middle[8]), .B(
DP_OP_168J43_122_1342_n439), .C(DP_OP_168J43_122_1342_n491), .CO(n955),
.S(n954) );
CMPR32X2TS U886 ( .A(Sgf_operation_ODD1_Q_middle[11]), .B(
DP_OP_168J43_122_1342_n436), .C(DP_OP_168J43_122_1342_n488), .CO(n963),
.S(n960) );
CMPR32X2TS U887 ( .A(Sgf_operation_ODD1_Q_middle[6]), .B(
DP_OP_168J43_122_1342_n441), .C(DP_OP_168J43_122_1342_n493), .CO(n947),
.S(n946) );
CMPR32X2TS U888 ( .A(Sgf_operation_ODD1_Q_middle[13]), .B(
DP_OP_168J43_122_1342_n434), .C(DP_OP_168J43_122_1342_n486), .CO(n967),
.S(n966) );
CMPR32X2TS U889 ( .A(Sgf_operation_ODD1_Q_middle[12]), .B(
DP_OP_168J43_122_1342_n435), .C(DP_OP_168J43_122_1342_n487), .CO(n965),
.S(n964) );
CMPR32X2TS U890 ( .A(Sgf_operation_ODD1_Q_middle[10]), .B(
DP_OP_168J43_122_1342_n437), .C(DP_OP_168J43_122_1342_n489), .CO(n959),
.S(n958) );
CMPR32X2TS U891 ( .A(Sgf_operation_ODD1_Q_middle[15]), .B(
DP_OP_168J43_122_1342_n432), .C(DP_OP_168J43_122_1342_n484), .CO(n977),
.S(n970) );
OAI21XLTS U892 ( .A0(n2610), .A1(n2602), .B0(n2611), .Y(n1453) );
NOR2XLTS U893 ( .A(n1983), .B(n1659), .Y(n1660) );
OAI21XLTS U894 ( .A0(n1270), .A1(n1276), .B0(n1271), .Y(n1017) );
NOR2XLTS U895 ( .A(n1666), .B(n1665), .Y(n1667) );
OAI21XLTS U896 ( .A0(n1256), .A1(n1292), .B0(n1257), .Y(n1007) );
NOR2X1TS U897 ( .A(n2591), .B(n1840), .Y(n2834) );
OAI21XLTS U898 ( .A0(Op_MX[14]), .A1(Op_MX[41]), .B0(Op_MX[13]), .Y(n2596)
);
NOR2XLTS U899 ( .A(n2592), .B(n2591), .Y(n2593) );
OAI21XLTS U900 ( .A0(n2890), .A1(n2889), .B0(n2888), .Y(n2891) );
OAI21XLTS U901 ( .A0(Op_MX[4]), .A1(Op_MX[31]), .B0(Op_MX[3]), .Y(n1953) );
OAI21XLTS U902 ( .A0(n4082), .A1(n4081), .B0(n4080), .Y(n4083) );
OR2X1TS U903 ( .A(n4626), .B(n4621), .Y(n741) );
OR2X1TS U904 ( .A(n4607), .B(n4615), .Y(n866) );
NOR2XLTS U905 ( .A(n1994), .B(n1996), .Y(n1999) );
OAI21XLTS U906 ( .A0(n1970), .A1(n1969), .B0(n1968), .Y(n1975) );
NOR2X1TS U907 ( .A(n1171), .B(n1119), .Y(n950) );
OAI21XLTS U908 ( .A0(n2741), .A1(n2740), .B0(n2739), .Y(n2742) );
NOR2XLTS U909 ( .A(n793), .B(n807), .Y(n1547) );
OR2X1TS U910 ( .A(n4573), .B(n4578), .Y(n859) );
NOR2XLTS U911 ( .A(n3782), .B(n3787), .Y(n3790) );
NOR2X1TS U912 ( .A(n3703), .B(n3698), .Y(n1908) );
INVX2TS U913 ( .A(n2005), .Y(n4085) );
OAI21XLTS U914 ( .A0(n2946), .A1(n4381), .B0(n844), .Y(n2926) );
BUFX4TS U915 ( .A(Op_MY[37]), .Y(n3731) );
OAI21XLTS U916 ( .A0(n4650), .A1(n4323), .B0(n4314), .Y(n4315) );
OAI21XLTS U917 ( .A0(n4551), .A1(n4269), .B0(n4260), .Y(n4261) );
OAI21XLTS U918 ( .A0(n4650), .A1(n4269), .B0(n4254), .Y(n4255) );
NOR2XLTS U919 ( .A(n4958), .B(n4964), .Y(n4959) );
OAI21XLTS U920 ( .A0(n2741), .A1(n2731), .B0(n2730), .Y(n2732) );
OAI21XLTS U921 ( .A0(n4551), .A1(n4381), .B0(n4370), .Y(n4371) );
OAI21XLTS U922 ( .A0(n3585), .A1(n3510), .B0(n3502), .Y(n3503) );
OAI21XLTS U923 ( .A0(n4611), .A1(n4435), .B0(n4406), .Y(n4407) );
OAI21XLTS U924 ( .A0(n3690), .A1(n1900), .B0(n1927), .Y(n1928) );
OAI21XLTS U925 ( .A0(n4650), .A1(n4381), .B0(n4364), .Y(n4365) );
OAI21XLTS U926 ( .A0(n4611), .A1(n4496), .B0(n4460), .Y(n4461) );
OAI21XLTS U927 ( .A0(n4605), .A1(n2927), .B0(n4346), .Y(n4347) );
OAI21XLTS U928 ( .A0(n4565), .A1(n2345), .B0(n4504), .Y(n4505) );
OAI21XLTS U929 ( .A0(n3735), .A1(n3510), .B0(n3489), .Y(n3490) );
OAI21XLTS U930 ( .A0(n4565), .A1(n2307), .B0(n4442), .Y(n4443) );
OAI21XLTS U931 ( .A0(n4585), .A1(n2927), .B0(n4338), .Y(n4339) );
OAI21XLTS U932 ( .A0(n4634), .A1(n4092), .B0(n2081), .Y(n2082) );
OAI21XLTS U933 ( .A0(n4595), .A1(n1853), .B0(n1816), .Y(n1817) );
NAND2X1TS U934 ( .A(n992), .B(n991), .Y(n1243) );
OR2X1TS U935 ( .A(n1028), .B(n1027), .Y(n905) );
OAI21XLTS U936 ( .A0(n3701), .A1(n1877), .B0(n1913), .Y(n1914) );
OAI21XLTS U937 ( .A0(n2714), .A1(n3510), .B0(n2783), .Y(n2784) );
OAI21XLTS U938 ( .A0(n3696), .A1(n3453), .B0(n2801), .Y(n2802) );
OAI21XLTS U939 ( .A0(n3701), .A1(n3407), .B0(n1895), .Y(n1896) );
OAI21X1TS U940 ( .A0(n1218), .A1(n1223), .B0(n1219), .Y(n1204) );
OAI21XLTS U941 ( .A0(n4555), .A1(n4424), .B0(n4388), .Y(n4389) );
NAND2X2TS U942 ( .A(n3360), .B(n3312), .Y(n2214) );
OAI21XLTS U943 ( .A0(n4543), .A1(n4550), .B0(n4542), .Y(n4544) );
OAI21XLTS U944 ( .A0(n4629), .A1(n4550), .B0(n4528), .Y(n4529) );
OAI21XLTS U945 ( .A0(n3723), .A1(n3728), .B0(n3722), .Y(n3724) );
OAI21XLTS U946 ( .A0(n4617), .A1(n4550), .B0(n4521), .Y(n4523) );
ADDHXLTS U947 ( .A(n3309), .B(n3308), .CO(n3322), .S(mult_x_23_n732) );
OAI21XLTS U948 ( .A0(n3680), .A1(n3728), .B0(n3679), .Y(n3681) );
OAI21XLTS U949 ( .A0(n3878), .A1(n3764), .B0(n3763), .Y(n3765) );
OAI21XLTS U950 ( .A0(n4656), .A1(n4800), .B0(n4655), .Y(n4657) );
OAI21XLTS U951 ( .A0(n1245), .A1(n1244), .B0(n1243), .Y(n1250) );
NAND2BX1TS U952 ( .AN(Sgf_operation_ODD1_Q_middle[55]), .B(n1036), .Y(n1035)
);
OAI21XLTS U953 ( .A0(n1280), .A1(n1286), .B0(n1287), .Y(n1285) );
OAI21XLTS U954 ( .A0(n3623), .A1(n2785), .B0(n2778), .Y(n2779) );
OAI21XLTS U955 ( .A0(n847), .A1(n1877), .B0(n1842), .Y(n1843) );
OAI21XLTS U956 ( .A0(n1215), .A1(n1211), .B0(n1212), .Y(n1210) );
OAI21XLTS U957 ( .A0(n4555), .A1(n1544), .B0(n4169), .Y(n4170) );
OAI21XLTS U958 ( .A0(n847), .A1(n3402), .B0(n3372), .Y(n3373) );
OAI21XLTS U959 ( .A0(n873), .A1(n2236), .B0(n2284), .Y(n2285) );
OAI21XLTS U960 ( .A0(n3129), .A1(n3135), .B0(n3130), .Y(n2440) );
OAI21XLTS U961 ( .A0(n4821), .A1(n4827), .B0(n4822), .Y(n2514) );
OAI21XLTS U962 ( .A0(n3896), .A1(n2565), .B0(n2566), .Y(n2553) );
NAND2X1TS U963 ( .A(n4653), .B(n4658), .Y(n4661) );
NOR2XLTS U964 ( .A(n6197), .B(n6196), .Y(n1242) );
OAI21XLTS U965 ( .A0(n2456), .A1(n3112), .B0(n2457), .Y(n2444) );
ADDHXLTS U966 ( .A(n3349), .B(n3348), .CO(n3364), .S(mult_x_23_n828) );
INVX2TS U967 ( .A(n4763), .Y(n4671) );
OAI21XLTS U968 ( .A0(n4921), .A1(n4918), .B0(n4922), .Y(n2402) );
OAI21X1TS U969 ( .A0(n4808), .A1(n4814), .B0(n4809), .Y(n2525) );
INVX2TS U970 ( .A(n5825), .Y(n5827) );
OR2X1TS U971 ( .A(n1365), .B(Sgf_operation_ODD1_Q_left[13]), .Y(n816) );
CMPR42X1TS U972 ( .A(mult_x_23_n767), .B(mult_x_23_n1349), .C(mult_x_23_n768), .D(mult_x_23_n759), .ICI(mult_x_23_n764), .S(mult_x_23_n756), .ICO(
mult_x_23_n754), .CO(mult_x_23_n755) );
NOR2XLTS U973 ( .A(n2981), .B(n2974), .Y(n2984) );
OAI21XLTS U974 ( .A0(n5629), .A1(n6568), .B0(n5628), .Y(n5630) );
CMPR42X1TS U975 ( .A(mult_x_24_n643), .B(mult_x_24_n638), .C(mult_x_24_n644),
.D(mult_x_24_n635), .ICI(mult_x_24_n640), .S(mult_x_24_n632), .ICO(
mult_x_24_n630), .CO(mult_x_24_n631) );
NOR2X1TS U976 ( .A(n4789), .B(n4791), .Y(n4778) );
OAI21XLTS U977 ( .A0(n4024), .A1(n4030), .B0(n4025), .Y(n2383) );
OR2X1TS U978 ( .A(DP_OP_169J43_123_4229_n1274), .B(
DP_OP_169J43_123_4229_n1281), .Y(n890) );
OR2X1TS U979 ( .A(mult_x_23_n800), .B(mult_x_23_n806), .Y(n902) );
OR2X1TS U980 ( .A(DP_OP_169J43_123_4229_n1212), .B(
DP_OP_169J43_123_4229_n1224), .Y(n753) );
OR2X1TS U981 ( .A(mult_x_24_n759), .B(mult_x_24_n771), .Y(n881) );
OR2X1TS U982 ( .A(DP_OP_169J43_123_4229_n1156), .B(
DP_OP_169J43_123_4229_n1171), .Y(n4863) );
OR2X1TS U983 ( .A(DP_OP_169J43_123_4229_n1124), .B(
DP_OP_169J43_123_4229_n1140), .Y(n4852) );
OR2X1TS U984 ( .A(mult_x_24_n642), .B(mult_x_24_n651), .Y(n3891) );
AOI21X2TS U985 ( .A0(n818), .A1(n5870), .B0(n1406), .Y(n5861) );
NOR2XLTS U986 ( .A(n5806), .B(n5763), .Y(n5764) );
NOR2XLTS U987 ( .A(n809), .B(n5656), .Y(n5658) );
OAI21XLTS U988 ( .A0(n6146), .A1(n6092), .B0(n6091), .Y(n6097) );
NOR2XLTS U989 ( .A(n5806), .B(n1438), .Y(n1439) );
NOR2XLTS U990 ( .A(n809), .B(n1539), .Y(n1540) );
AOI21X1TS U991 ( .A0(n2985), .A1(n2984), .B0(n2983), .Y(n3069) );
OAI21XLTS U992 ( .A0(n6222), .A1(n6261), .B0(n6262), .Y(n6220) );
OR2X1TS U993 ( .A(DP_OP_169J43_123_4229_n721), .B(DP_OP_169J43_123_4229_n717), .Y(n4716) );
OAI21X1TS U994 ( .A0(n4755), .A1(n4673), .B0(n4672), .Y(n4748) );
OR2X1TS U995 ( .A(mult_x_24_n548), .B(n3796), .Y(n3821) );
OR2X1TS U996 ( .A(mult_x_24_n560), .B(mult_x_24_n564), .Y(n3839) );
OR2X1TS U997 ( .A(n3013), .B(n3012), .Y(n3030) );
OAI21XLTS U998 ( .A0(n4017), .A1(n4013), .B0(n4014), .Y(n4012) );
OAI21XLTS U999 ( .A0(n3993), .A1(n3992), .B0(n3991), .Y(n3998) );
OAI21XLTS U1000 ( .A0(n4904), .A1(n4903), .B0(n4902), .Y(n4909) );
OAI21XLTS U1001 ( .A0(n3967), .A1(n3966), .B0(n3965), .Y(n3972) );
OAI21XLTS U1002 ( .A0(n3165), .A1(n3152), .B0(n3151), .Y(n3157) );
OAI21XLTS U1003 ( .A0(n3125), .A1(n3121), .B0(n3122), .Y(n3120) );
OAI21XLTS U1004 ( .A0(n4858), .A1(n4844), .B0(n4843), .Y(n4849) );
OAI21XLTS U1005 ( .A0(n4817), .A1(n4813), .B0(n4814), .Y(n4812) );
ADDHXLTS U1006 ( .A(Sgf_normalized_result[48]), .B(n5653), .CO(n5647), .S(
n5654) );
OAI21XLTS U1007 ( .A0(n3230), .A1(n3227), .B0(n3228), .Y(n3226) );
OAI21XLTS U1008 ( .A0(n4705), .A1(n4701), .B0(n4702), .Y(n4700) );
OAI21XLTS U1009 ( .A0(n4766), .A1(n4758), .B0(n4763), .Y(n4762) );
OAI21XLTS U1010 ( .A0(n3819), .A1(n3815), .B0(n3816), .Y(n3814) );
OR2X1TS U1011 ( .A(exp_oper_result[11]), .B(Exp_module_Overflow_flag_A), .Y(
overflow_flag) );
BUFX12TS U1012 ( .A(n5806), .Y(n809) );
CLKMX2X2TS U1013 ( .A(n6188), .B(FSM_add_overflow_flag), .S0(n6187), .Y(n526) );
CLKMX2X2TS U1014 ( .A(n5634), .B(Add_result[51]), .S0(n6394), .Y(n528) );
CLKMX2X2TS U1015 ( .A(n5643), .B(Add_result[50]), .S0(n6394), .Y(n529) );
CLKMX2X2TS U1016 ( .A(n5648), .B(Add_result[49]), .S0(n6394), .Y(n530) );
CLKMX2X2TS U1017 ( .A(n5654), .B(Add_result[48]), .S0(n6394), .Y(n531) );
CLKMX2X2TS U1018 ( .A(P_Sgf[77]), .B(n5883), .S0(n5944), .Y(n498) );
CLKMX2X2TS U1019 ( .A(n5666), .B(Add_result[47]), .S0(n6394), .Y(n532) );
CLKMX2X2TS U1020 ( .A(P_Sgf[76]), .B(n5892), .S0(n5944), .Y(n497) );
CLKMX2X2TS U1021 ( .A(P_Sgf[75]), .B(n5904), .S0(n5944), .Y(n496) );
XNOR2X1TS U1022 ( .A(n3023), .B(n3022), .Y(Sgf_operation_ODD1_left_N51) );
CLKMX2X2TS U1023 ( .A(n5678), .B(Add_result[46]), .S0(n6394), .Y(n533) );
CLKMX2X2TS U1024 ( .A(P_Sgf[74]), .B(n5913), .S0(n5944), .Y(n495) );
OAI21X2TS U1025 ( .A0(n3028), .A1(n3024), .B0(n3025), .Y(n3023) );
XOR2X1TS U1026 ( .A(n3028), .B(n3027), .Y(Sgf_operation_ODD1_left_N50) );
NAND2XLTS U1027 ( .A(n5815), .B(n5814), .Y(n5818) );
CLKMX2X2TS U1028 ( .A(P_Sgf[73]), .B(n5924), .S0(n5944), .Y(n494) );
CLKMX2X2TS U1029 ( .A(P_Sgf[72]), .B(n5933), .S0(n5944), .Y(n493) );
CLKINVX1TS U1030 ( .A(n5813), .Y(n5815) );
OAI21X2TS U1031 ( .A0(n4714), .A1(n4710), .B0(n4711), .Y(n4709) );
INVX1TS U1032 ( .A(n5837), .Y(n5839) );
AOI21X2TS U1033 ( .A0(n3050), .A1(n3048), .B0(n2993), .Y(n3046) );
CLKMX2X2TS U1034 ( .A(P_Sgf[57]), .B(n6125), .S0(n6136), .Y(n478) );
CLKMX2X2TS U1035 ( .A(P_Sgf[59]), .B(n6098), .S0(n6136), .Y(n480) );
CLKMX2X2TS U1036 ( .A(P_Sgf[58]), .B(n6111), .S0(n6136), .Y(n479) );
CLKMX2X2TS U1037 ( .A(P_Sgf[55]), .B(n6147), .S0(n6339), .Y(n476) );
CLKMX2X2TS U1038 ( .A(P_Sgf[56]), .B(n6137), .S0(n6136), .Y(n477) );
OAI21X1TS U1039 ( .A0(n4662), .A1(n4661), .B0(n4660), .Y(n4663) );
OR2X2TS U1040 ( .A(n1393), .B(Sgf_operation_ODD1_Q_left[20]), .Y(n820) );
OAI21X1TS U1041 ( .A0(n6087), .A1(n1324), .B0(n1323), .Y(n1325) );
OR2X2TS U1042 ( .A(n1387), .B(Sgf_operation_ODD1_Q_left[18]), .Y(n821) );
INVX1TS U1043 ( .A(n4719), .Y(n4721) );
XOR2X1TS U1044 ( .A(n4003), .B(n4002), .Y(Sgf_operation_ODD1_right_N11) );
XOR2X1TS U1045 ( .A(n3209), .B(n3208), .Y(Sgf_operation_ODD1_left_N10) );
INVX1TS U1046 ( .A(n3833), .Y(n3835) );
INVX1TS U1047 ( .A(n3060), .Y(n3062) );
INVX1TS U1048 ( .A(n3851), .Y(n3853) );
INVX1TS U1049 ( .A(n3842), .Y(n3844) );
INVX1TS U1050 ( .A(n3051), .Y(n3053) );
XOR2X1TS U1051 ( .A(n4920), .B(n2182), .Y(Sgf_operation_ODD1_middle_N8) );
INVX1TS U1052 ( .A(n3042), .Y(n3044) );
OR2X2TS U1053 ( .A(DP_OP_169J43_123_4229_n1247), .B(
DP_OP_169J43_123_4229_n1255), .Y(n898) );
NOR2X2TS U1054 ( .A(n6120), .B(n6119), .Y(n6104) );
AOI21X1TS U1055 ( .A0(n836), .A1(n6162), .B0(n1311), .Y(n6087) );
OR2X2TS U1056 ( .A(mult_x_23_n807), .B(mult_x_23_n813), .Y(n901) );
OR2X2TS U1057 ( .A(n1307), .B(Sgf_operation_ODD1_Q_right[50]), .Y(n875) );
OR2X2TS U1058 ( .A(n1314), .B(Sgf_operation_ODD1_Q_left[2]), .Y(n813) );
OAI21X1TS U1059 ( .A0(n3222), .A1(n3228), .B0(n3223), .Y(n2267) );
OR2X2TS U1060 ( .A(n1310), .B(Sgf_operation_ODD1_Q_right[53]), .Y(n836) );
OAI21X1TS U1061 ( .A0(n3729), .A1(n3728), .B0(n3727), .Y(n3730) );
OAI21X1TS U1062 ( .A0(n3729), .A1(n3599), .B0(n3567), .Y(n3568) );
OAI21X1TS U1063 ( .A0(n3706), .A1(n3636), .B0(n3627), .Y(n3628) );
INVX1TS U1064 ( .A(n5547), .Y(n4691) );
OAI21X1TS U1065 ( .A0(n3745), .A1(n3599), .B0(n3574), .Y(n3575) );
OAI21X1TS U1066 ( .A0(n3711), .A1(n3728), .B0(n3710), .Y(n3712) );
OAI21X1TS U1067 ( .A0(n847), .A1(n3562), .B0(n3516), .Y(n3517) );
OAI21X1TS U1068 ( .A0(n3611), .A1(n2715), .B0(n3518), .Y(n3519) );
OAI21X1TS U1069 ( .A0(n3723), .A1(n3636), .B0(n3635), .Y(n3638) );
OAI21X1TS U1070 ( .A0(n3717), .A1(n3636), .B0(n3632), .Y(n3633) );
OAI21X1TS U1071 ( .A0(n3755), .A1(n3562), .B0(n3552), .Y(n3553) );
OAI21X1TS U1072 ( .A0(n3717), .A1(n1900), .B0(n1949), .Y(n1950) );
OAI21X1TS U1073 ( .A0(n3717), .A1(n2715), .B0(n3537), .Y(n3538) );
OAI21X1TS U1074 ( .A0(n3723), .A1(n2715), .B0(n3540), .Y(n3542) );
OAI21X1TS U1075 ( .A0(n3755), .A1(n2236), .B0(n3754), .Y(n3757) );
OAI21X1TS U1076 ( .A0(n3740), .A1(n2236), .B0(n3739), .Y(n3741) );
OAI21X1TS U1077 ( .A0(n3755), .A1(n3510), .B0(n3495), .Y(n3496) );
OAI21X1TS U1078 ( .A0(n4629), .A1(n4496), .B0(n4470), .Y(n4471) );
INVX2TS U1079 ( .A(n1924), .Y(n3706) );
OAI21X1TS U1080 ( .A0(n4629), .A1(n2945), .B0(n4248), .Y(n4249) );
OAI21X1TS U1081 ( .A0(n3740), .A1(n1609), .B0(n3263), .Y(n3265) );
INVX2TS U1082 ( .A(n1800), .Y(n3690) );
OAI21X1TS U1083 ( .A0(n4650), .A1(n4496), .B0(n4477), .Y(n4478) );
OAI21X1TS U1084 ( .A0(n4551), .A1(n4550), .B0(n4549), .Y(n4552) );
OAI21X1TS U1085 ( .A0(n3696), .A1(n1877), .B0(n1873), .Y(n1874) );
OAI21X1TS U1086 ( .A0(n4642), .A1(n4269), .B0(n4252), .Y(n4253) );
OAI21X1TS U1087 ( .A0(n3585), .A1(n3428), .B0(n3420), .Y(n3421) );
OAI21X1TS U1088 ( .A0(n3585), .A1(n3728), .B0(n2237), .Y(n2238) );
BUFX4TS U1089 ( .A(n1882), .Y(n5569) );
OAI21X1TS U1090 ( .A0(n4650), .A1(n4214), .B0(n4205), .Y(n4206) );
OAI21X1TS U1091 ( .A0(n3666), .A1(n2236), .B0(n2234), .Y(n2235) );
OAI21X1TS U1092 ( .A0(n3668), .A1(n3599), .B0(n763), .Y(n3564) );
OAI21X1TS U1093 ( .A0(n4642), .A1(n4641), .B0(n4640), .Y(n4643) );
OAI21X1TS U1094 ( .A0(n4543), .A1(n4323), .B0(n4318), .Y(n4319) );
OAI21X1TS U1095 ( .A0(n4642), .A1(n2927), .B0(n4362), .Y(n4363) );
OAI21X1TS U1096 ( .A0(n4538), .A1(n4435), .B0(n4428), .Y(n4429) );
OAI21X1TS U1097 ( .A0(n4551), .A1(n4435), .B0(n4434), .Y(n4436) );
OAI21X1TS U1098 ( .A0(n3735), .A1(n3665), .B0(n3642), .Y(n3643) );
OAI21X1TS U1099 ( .A0(n4642), .A1(n4214), .B0(n4203), .Y(n4204) );
OAI21X1TS U1100 ( .A0(n4551), .A1(n4214), .B0(n4213), .Y(n4215) );
OAI21X1TS U1101 ( .A0(n3652), .A1(n3510), .B0(n2864), .Y(n2865) );
OAI21X1TS U1102 ( .A0(n4543), .A1(n4435), .B0(n4430), .Y(n4431) );
OAI21X1TS U1103 ( .A0(n3585), .A1(n3475), .B0(n2868), .Y(n2869) );
OAI21X1TS U1104 ( .A0(n4551), .A1(n2327), .B0(n2358), .Y(n2359) );
OAI21X1TS U1105 ( .A0(n4543), .A1(n4092), .B0(n2033), .Y(n2034) );
OAI21X1TS U1106 ( .A0(n4538), .A1(n4214), .B0(n4207), .Y(n4208) );
OAI21X1TS U1107 ( .A0(n3735), .A1(n2236), .B0(n3734), .Y(n3736) );
OAI21X1TS U1108 ( .A0(n4650), .A1(n2327), .B0(n4649), .Y(n4651) );
OAI21X1TS U1109 ( .A0(n873), .A1(n3475), .B0(n3469), .Y(n3470) );
OAI21X1TS U1110 ( .A0(n4543), .A1(n4214), .B0(n4209), .Y(n4210) );
OAI21X1TS U1111 ( .A0(n3666), .A1(n3475), .B0(n3474), .Y(n3476) );
OAI21X1TS U1112 ( .A0(n873), .A1(n3665), .B0(n3656), .Y(n3657) );
OAI21X1TS U1113 ( .A0(n4551), .A1(n4323), .B0(n4322), .Y(n4324) );
OAI21X1TS U1114 ( .A0(n3590), .A1(n3475), .B0(n3335), .Y(n3336) );
OAI21X1TS U1115 ( .A0(n3590), .A1(n3510), .B0(n3504), .Y(n3505) );
OAI21X1TS U1116 ( .A0(n2714), .A1(n3599), .B0(n3565), .Y(n3566) );
OAI21X1TS U1117 ( .A0(n4374), .A1(n4092), .B0(n1990), .Y(n1991) );
OAI21X1TS U1118 ( .A0(n3590), .A1(n1609), .B0(n3283), .Y(n3287) );
OAI21X1TS U1119 ( .A0(n3590), .A1(n3428), .B0(n3422), .Y(n3423) );
OAI21X1TS U1120 ( .A0(n3590), .A1(n3665), .B0(n2271), .Y(n2272) );
OAI21X1TS U1121 ( .A0(n3590), .A1(n2236), .B0(n2257), .Y(n2258) );
OAI21X1TS U1122 ( .A0(n2946), .A1(n4214), .B0(n863), .Y(n1545) );
OAI21X1TS U1123 ( .A0(n4141), .A1(n4214), .B0(n4099), .Y(n4100) );
OAI21X1TS U1124 ( .A0(n4497), .A1(n4214), .B0(n4107), .Y(n4108) );
OAI21X1TS U1125 ( .A0(n4497), .A1(n4550), .B0(n2341), .Y(n2342) );
OAI21X1TS U1126 ( .A0(n1133), .A1(n1129), .B0(n1130), .Y(n1128) );
INVX3TS U1127 ( .A(n1060), .Y(n1253) );
OAI21X1TS U1128 ( .A0(n1175), .A1(n1171), .B0(n1172), .Y(n1123) );
OAI21X1TS U1129 ( .A0(n2946), .A1(n4496), .B0(n841), .Y(n2306) );
OAI21X1TS U1130 ( .A0(n2946), .A1(n4435), .B0(n839), .Y(n917) );
OAI21X1TS U1131 ( .A0(n2946), .A1(n4269), .B0(n845), .Y(n2947) );
OAI21X1TS U1132 ( .A0(n2945), .A1(n6547), .B0(n2948), .Y(n2950) );
OAI21X1TS U1133 ( .A0(n4141), .A1(n4435), .B0(n4140), .Y(n4142) );
OAI21X1TS U1134 ( .A0(n4141), .A1(n4496), .B0(n2319), .Y(n2320) );
OAI21X1TS U1135 ( .A0(n4141), .A1(n4269), .B0(n2953), .Y(n2954) );
OAI21X1TS U1136 ( .A0(n2946), .A1(n4323), .B0(n840), .Y(n1427) );
OAI21X1TS U1137 ( .A0(n1428), .A1(n6547), .B0(n1429), .Y(n1430) );
OAI21X1TS U1138 ( .A0(n4141), .A1(n4323), .B0(n4120), .Y(n4121) );
OAI21X1TS U1139 ( .A0(n3353), .A1(n3510), .B0(n2835), .Y(n2836) );
AOI21X2TS U1140 ( .A0(n1080), .A1(n976), .B0(n975), .Y(n1060) );
OAI21X1TS U1141 ( .A0(n831), .A1(n3510), .B0(n3509), .Y(n3512) );
AND2X2TS U1142 ( .A(n3248), .B(n3687), .Y(n1720) );
OAI21X1TS U1143 ( .A0(n2927), .A1(n6547), .B0(n2928), .Y(n2929) );
OAI21X1TS U1144 ( .A0(n2307), .A1(n6547), .B0(n2308), .Y(n2309) );
NOR2X1TS U1145 ( .A(n4965), .B(n4964), .Y(n4968) );
OAI21X1TS U1146 ( .A0(n4141), .A1(n4381), .B0(n2931), .Y(n2932) );
NOR2X1TS U1147 ( .A(n4961), .B(n4964), .Y(n4963) );
OAI21X1TS U1148 ( .A0(n831), .A1(n3428), .B0(n3427), .Y(n3430) );
OAI21X1TS U1149 ( .A0(n3314), .A1(n1877), .B0(n852), .Y(n2831) );
OAI21X1TS U1150 ( .A0(n3353), .A1(n3562), .B0(n3352), .Y(n3354) );
OAI21X1TS U1151 ( .A0(n3314), .A1(n2715), .B0(n853), .Y(n1542) );
OAI21X1TS U1152 ( .A0(n831), .A1(n3402), .B0(n3319), .Y(n3320) );
OAI21X1TS U1153 ( .A0(n3353), .A1(n3402), .B0(n3310), .Y(n3311) );
OAI21X1TS U1154 ( .A0(n6546), .A1(n1900), .B0(n2184), .Y(n2185) );
INVX3TS U1155 ( .A(n899), .Y(n3501) );
OAI21X1TS U1156 ( .A0(n1081), .A1(n974), .B0(n973), .Y(n975) );
CLKAND2X2TS U1157 ( .A(n2092), .B(n6585), .Y(n5635) );
INVX3TS U1158 ( .A(n763), .Y(n3583) );
INVX3TS U1159 ( .A(n2756), .Y(n3471) );
NAND2XLTS U1160 ( .A(n1339), .B(n1338), .Y(n1340) );
AOI21X1TS U1161 ( .A0(n1117), .A1(n950), .B0(n949), .Y(n951) );
NAND2X4TS U1162 ( .A(n1627), .B(n5548), .Y(n1628) );
NAND2X1TS U1163 ( .A(n1118), .B(n950), .Y(n952) );
INVX3TS U1164 ( .A(n894), .Y(n3659) );
AND2X2TS U1165 ( .A(n4106), .B(n4598), .Y(n4047) );
OR2X2TS U1166 ( .A(n4603), .B(n4609), .Y(n864) );
OR2X2TS U1167 ( .A(n4632), .B(n4639), .Y(n868) );
NOR2X1TS U1168 ( .A(n1608), .B(n1502), .Y(n1503) );
OR2X2TS U1169 ( .A(n4540), .B(n4536), .Y(n740) );
OR2X2TS U1170 ( .A(n4563), .B(n4568), .Y(n858) );
OR2X2TS U1171 ( .A(n4598), .B(n4593), .Y(n862) );
INVX1TS U1172 ( .A(n1337), .Y(n1339) );
CLKXOR2X2TS U1173 ( .A(n786), .B(n6584), .Y(n1608) );
OR2X2TS U1174 ( .A(n4372), .B(n4545), .Y(n865) );
OR2X2TS U1175 ( .A(n4588), .B(n4583), .Y(n860) );
AND2X2TS U1176 ( .A(n908), .B(n1624), .Y(n6538) );
NOR2X1TS U1177 ( .A(Sgf_normalized_result[4]), .B(Sgf_normalized_result[5]),
.Y(n5624) );
CLKMX2X2TS U1178 ( .A(P_Sgf[90]), .B(n5756), .S0(n5792), .Y(n511) );
CLKMX2X2TS U1179 ( .A(P_Sgf[94]), .B(n5718), .S0(n5792), .Y(n515) );
CLKMX2X2TS U1180 ( .A(P_Sgf[86]), .B(n5793), .S0(n5792), .Y(n507) );
CLKMX2X2TS U1181 ( .A(P_Sgf[100]), .B(n5660), .S0(n5792), .Y(n522) );
CLKMX2X2TS U1182 ( .A(P_Sgf[105]), .B(n1444), .S0(n6339), .Y(n420) );
CLKMX2X2TS U1183 ( .A(P_Sgf[87]), .B(n5784), .S0(n5792), .Y(n508) );
CLKMX2X2TS U1184 ( .A(P_Sgf[98]), .B(n5682), .S0(n5792), .Y(n519) );
CLKMX2X2TS U1185 ( .A(P_Sgf[96]), .B(n5699), .S0(n5792), .Y(n517) );
CLKMX2X2TS U1186 ( .A(P_Sgf[84]), .B(n5807), .S0(n5944), .Y(n505) );
CLKMX2X2TS U1187 ( .A(P_Sgf[95]), .B(n5709), .S0(n5792), .Y(n516) );
CLKMX2X2TS U1188 ( .A(P_Sgf[83]), .B(n5819), .S0(n5944), .Y(n504) );
CLKMX2X2TS U1189 ( .A(P_Sgf[85]), .B(n5800), .S0(n5944), .Y(n506) );
CLKMX2X2TS U1190 ( .A(P_Sgf[103]), .B(n1440), .S0(n6202), .Y(n525) );
CLKMX2X2TS U1191 ( .A(P_Sgf[89]), .B(n5765), .S0(n5792), .Y(n510) );
CLKMX2X2TS U1192 ( .A(P_Sgf[93]), .B(n5727), .S0(n5792), .Y(n514) );
CLKMX2X2TS U1193 ( .A(P_Sgf[97]), .B(n5691), .S0(n5792), .Y(n518) );
CLKMX2X2TS U1194 ( .A(P_Sgf[91]), .B(n5746), .S0(n5792), .Y(n512) );
CLKMX2X2TS U1195 ( .A(P_Sgf[92]), .B(n5735), .S0(n5792), .Y(n513) );
CLKMX2X2TS U1196 ( .A(P_Sgf[99]), .B(n5673), .S0(n5792), .Y(n521) );
NOR2X1TS U1197 ( .A(n809), .B(n5771), .Y(n5772) );
CLKMX2X2TS U1198 ( .A(P_Sgf[82]), .B(n5830), .S0(n5944), .Y(n503) );
NOR2X1TS U1199 ( .A(n809), .B(n1435), .Y(n1436) );
NOR2X1TS U1200 ( .A(n809), .B(n1434), .Y(n1422) );
NOR2X1TS U1201 ( .A(n809), .B(n764), .Y(n1443) );
NOR2X1TS U1202 ( .A(n809), .B(n5716), .Y(n5717) );
NOR2X1TS U1203 ( .A(n809), .B(n5697), .Y(n5698) );
NOR2X1TS U1204 ( .A(n809), .B(n5680), .Y(n5681) );
NOR2X1TS U1205 ( .A(n809), .B(n5790), .Y(n5791) );
NOR2X1TS U1206 ( .A(n809), .B(n5782), .Y(n5783) );
NOR2X1TS U1207 ( .A(n809), .B(n5754), .Y(n5755) );
NOR2X1TS U1208 ( .A(n5806), .B(n5744), .Y(n5745) );
OAI21X1TS U1209 ( .A0(n5828), .A1(n5825), .B0(n5826), .Y(n5817) );
NOR2X1TS U1210 ( .A(n5806), .B(n5689), .Y(n5690) );
NOR2X1TS U1211 ( .A(n5806), .B(n5707), .Y(n5708) );
NOR2X1TS U1212 ( .A(n5806), .B(n5733), .Y(n5734) );
NOR2X1TS U1213 ( .A(n5806), .B(n5725), .Y(n5726) );
NOR2X1TS U1214 ( .A(n5806), .B(n5671), .Y(n5672) );
NOR2X1TS U1215 ( .A(n5806), .B(DP_OP_168J43_122_1342_n469), .Y(n5799) );
CLKMX2X2TS U1216 ( .A(n5627), .B(Add_result[52]), .S0(n6187), .Y(n527) );
CLKMX2X2TS U1217 ( .A(P_Sgf[81]), .B(n5842), .S0(n5944), .Y(n502) );
CLKMX2X2TS U1218 ( .A(P_Sgf[80]), .B(n5851), .S0(n5944), .Y(n501) );
CLKMX2X2TS U1219 ( .A(P_Sgf[79]), .B(n5863), .S0(n5944), .Y(n500) );
CLKMX2X2TS U1220 ( .A(P_Sgf[78]), .B(n5872), .S0(n5944), .Y(n499) );
XOR2X1TS U1221 ( .A(n3819), .B(n3818), .Y(Sgf_operation_ODD1_right_N52) );
XOR2X1TS U1222 ( .A(n4705), .B(n4704), .Y(Sgf_operation_ODD1_middle_N54) );
XOR2X1TS U1223 ( .A(n3828), .B(n3827), .Y(Sgf_operation_ODD1_right_N50) );
XOR2X1TS U1224 ( .A(n3037), .B(n3036), .Y(Sgf_operation_ODD1_left_N48) );
XOR2X1TS U1225 ( .A(n4714), .B(n4713), .Y(Sgf_operation_ODD1_middle_N52) );
XOR2X1TS U1226 ( .A(n3885), .B(n3884), .Y(Sgf_operation_ODD1_right_N39) );
XOR2X1TS U1227 ( .A(n3837), .B(n3836), .Y(Sgf_operation_ODD1_right_N48) );
XOR2X1TS U1228 ( .A(n3046), .B(n3045), .Y(Sgf_operation_ODD1_left_N46) );
XOR2X1TS U1229 ( .A(n4723), .B(n4722), .Y(Sgf_operation_ODD1_middle_N50) );
XOR2X1TS U1230 ( .A(n2639), .B(n2638), .Y(Sgf_operation_ODD1_middle_N36) );
XOR2X1TS U1231 ( .A(n4753), .B(n4752), .Y(Sgf_operation_ODD1_middle_N45) );
XOR2X1TS U1232 ( .A(n3880), .B(n2648), .Y(Sgf_operation_ODD1_right_N36) );
NAND2X2TS U1233 ( .A(n1413), .B(Sgf_operation_ODD1_Q_left[27]), .Y(n5838) );
XOR2X1TS U1234 ( .A(n3846), .B(n3845), .Y(Sgf_operation_ODD1_right_N46) );
XOR2X1TS U1235 ( .A(n3895), .B(n3894), .Y(Sgf_operation_ODD1_right_N37) );
XOR2X1TS U1236 ( .A(n4766), .B(n4765), .Y(Sgf_operation_ODD1_middle_N43) );
XOR2X1TS U1237 ( .A(n2484), .B(n2483), .Y(Sgf_operation_ODD1_left_N34) );
OR2X2TS U1238 ( .A(n1411), .B(Sgf_operation_ODD1_Q_left[26]), .Y(n817) );
XOR2X1TS U1239 ( .A(n3055), .B(n3054), .Y(Sgf_operation_ODD1_left_N44) );
OAI21X1TS U1240 ( .A0(n4788), .A1(n4784), .B0(n4785), .Y(n4783) );
XOR2X1TS U1241 ( .A(n4743), .B(n4742), .Y(Sgf_operation_ODD1_middle_N46) );
XOR2X1TS U1242 ( .A(n4795), .B(n4794), .Y(Sgf_operation_ODD1_middle_N38) );
OAI21X1TS U1243 ( .A0(n4768), .A1(n4767), .B0(n4773), .Y(n4772) );
XOR2X1TS U1244 ( .A(n4732), .B(n4731), .Y(Sgf_operation_ODD1_middle_N48) );
XOR2X1TS U1245 ( .A(n2534), .B(n2533), .Y(Sgf_operation_ODD1_middle_N32) );
XOR2X1TS U1246 ( .A(n4788), .B(n4787), .Y(Sgf_operation_ODD1_middle_N39) );
XOR2X1TS U1247 ( .A(n2558), .B(n2557), .Y(Sgf_operation_ODD1_right_N35) );
XOR2X1TS U1248 ( .A(n3855), .B(n3854), .Y(Sgf_operation_ODD1_right_N44) );
OAI21X2TS U1249 ( .A0(n3855), .A1(n3851), .B0(n3852), .Y(n3850) );
XOR2X1TS U1250 ( .A(n2647), .B(n2585), .Y(Sgf_operation_ODD1_right_N34) );
XOR2X1TS U1251 ( .A(n3866), .B(n3865), .Y(Sgf_operation_ODD1_right_N42) );
XOR2X1TS U1252 ( .A(n2635), .B(n2572), .Y(Sgf_operation_ODD1_middle_N33) );
XOR2X1TS U1253 ( .A(n3873), .B(n3872), .Y(Sgf_operation_ODD1_right_N41) );
XOR2X1TS U1254 ( .A(n2523), .B(n2522), .Y(Sgf_operation_ODD1_middle_N34) );
XOR2X1TS U1255 ( .A(n2569), .B(n2568), .Y(Sgf_operation_ODD1_right_N33) );
XOR2X1TS U1256 ( .A(n3096), .B(n3095), .Y(Sgf_operation_ODD1_left_N37) );
OAI21X1TS U1257 ( .A0(n3096), .A1(n3092), .B0(n3093), .Y(n3091) );
XOR2X1TS U1258 ( .A(n3084), .B(n3083), .Y(Sgf_operation_ODD1_left_N39) );
XOR2X1TS U1259 ( .A(n2480), .B(n2463), .Y(Sgf_operation_ODD1_left_N31) );
AOI21X2TS U1260 ( .A0(n4736), .A1(n4734), .B0(n4680), .Y(n4732) );
OR2X2TS U1261 ( .A(n1405), .B(Sgf_operation_ODD1_Q_left[24]), .Y(n818) );
XOR2X1TS U1262 ( .A(n2460), .B(n2459), .Y(Sgf_operation_ODD1_left_N30) );
XOR2X1TS U1263 ( .A(n3103), .B(n3102), .Y(Sgf_operation_ODD1_left_N36) );
XOR2X1TS U1264 ( .A(n3075), .B(n3074), .Y(Sgf_operation_ODD1_left_N40) );
XOR2X1TS U1265 ( .A(n2449), .B(n2448), .Y(Sgf_operation_ODD1_left_N32) );
AOI21X2TS U1266 ( .A0(n3859), .A1(n3857), .B0(n3777), .Y(n3855) );
XOR2X1TS U1267 ( .A(n3064), .B(n3063), .Y(Sgf_operation_ODD1_left_N42) );
OAI21X2TS U1268 ( .A0(n3860), .A1(n3776), .B0(n3775), .Y(n3859) );
XOR2X1TS U1269 ( .A(n3931), .B(n3930), .Y(Sgf_operation_ODD1_right_N27) );
OAI21X1TS U1270 ( .A0(n3909), .A1(n3905), .B0(n3906), .Y(n3904) );
XOR2X1TS U1271 ( .A(n3922), .B(n3921), .Y(Sgf_operation_ODD1_right_N28) );
XOR2X1TS U1272 ( .A(n3909), .B(n3908), .Y(Sgf_operation_ODD1_right_N30) );
XOR2X1TS U1273 ( .A(n3935), .B(n3934), .Y(Sgf_operation_ODD1_right_N26) );
XOR2X1TS U1274 ( .A(n4830), .B(n4829), .Y(Sgf_operation_ODD1_middle_N27) );
AOI21X2TS U1275 ( .A0(n3068), .A1(n3066), .B0(n2991), .Y(n3064) );
XOR2X1TS U1276 ( .A(n4837), .B(n4836), .Y(Sgf_operation_ODD1_middle_N26) );
XOR2X1TS U1277 ( .A(n3945), .B(n3944), .Y(Sgf_operation_ODD1_right_N24) );
OAI21X1TS U1278 ( .A0(n3922), .A1(n3918), .B0(n3919), .Y(n3917) );
OAI21X2TS U1279 ( .A0(n4737), .A1(n4679), .B0(n4678), .Y(n4736) );
XOR2X1TS U1280 ( .A(n4817), .B(n4816), .Y(Sgf_operation_ODD1_middle_N29) );
OAI21X1TS U1281 ( .A0(n4830), .A1(n4826), .B0(n4827), .Y(n4825) );
AOI21X2TS U1282 ( .A0(n4738), .A1(n4741), .B0(n4677), .Y(n4678) );
OAI21X1TS U1283 ( .A0(n3138), .A1(n3134), .B0(n3135), .Y(n3133) );
OAI21X1TS U1284 ( .A0(n6077), .A1(n6034), .B0(n6033), .Y(n6039) );
XOR2X1TS U1285 ( .A(n3138), .B(n3137), .Y(Sgf_operation_ODD1_left_N25) );
NAND2X1TS U1286 ( .A(n4739), .B(n4741), .Y(n4679) );
AOI21X2TS U1287 ( .A0(n4665), .A1(n4664), .B0(n4663), .Y(n4737) );
OAI21X1TS U1288 ( .A0(n6077), .A1(n6050), .B0(n6049), .Y(n6053) );
OAI21X1TS U1289 ( .A0(n6146), .A1(n6119), .B0(n6118), .Y(n6124) );
OAI21X1TS U1290 ( .A0(n6146), .A1(n6107), .B0(n6106), .Y(n6110) );
XOR2X1TS U1291 ( .A(n3145), .B(n3144), .Y(Sgf_operation_ODD1_left_N24) );
XOR2X1TS U1292 ( .A(n3125), .B(n3124), .Y(Sgf_operation_ODD1_left_N27) );
OR2X2TS U1293 ( .A(n1399), .B(Sgf_operation_ODD1_Q_left[22]), .Y(n819) );
OAI21X1TS U1294 ( .A0(n6077), .A1(n6073), .B0(n6074), .Y(n6066) );
XOR2X1TS U1295 ( .A(n3961), .B(n3960), .Y(Sgf_operation_ODD1_right_N20) );
OAI21X1TS U1296 ( .A0(n4858), .A1(n4850), .B0(n4855), .Y(n4854) );
XOR2X1TS U1297 ( .A(n3956), .B(n3955), .Y(Sgf_operation_ODD1_right_N21) );
AOI21X2TS U1298 ( .A0(n6032), .A1(n1354), .B0(n1353), .Y(n6023) );
OAI21X1TS U1299 ( .A0(n3956), .A1(n3949), .B0(n3953), .Y(n3952) );
OAI21X2TS U1300 ( .A0(n4818), .A1(n2517), .B0(n2516), .Y(n4665) );
XOR2X1TS U1301 ( .A(n4865), .B(n4864), .Y(Sgf_operation_ODD1_middle_N21) );
XOR2X1TS U1302 ( .A(n4872), .B(n4871), .Y(Sgf_operation_ODD1_middle_N20) );
XOR2X1TS U1303 ( .A(n4858), .B(n4857), .Y(Sgf_operation_ODD1_middle_N22) );
XOR2X1TS U1304 ( .A(n3170), .B(n3169), .Y(Sgf_operation_ODD1_left_N19) );
XOR2X1TS U1305 ( .A(n3165), .B(n3164), .Y(Sgf_operation_ODD1_left_N20) );
NOR2X1TS U1306 ( .A(n4661), .B(n4654), .Y(n4664) );
OAI21X1TS U1307 ( .A0(n3165), .A1(n3158), .B0(n3162), .Y(n3161) );
XOR2X1TS U1308 ( .A(n3179), .B(n3178), .Y(Sgf_operation_ODD1_left_N18) );
AOI21X2TS U1309 ( .A0(n4842), .A1(n2513), .B0(n2512), .Y(n4818) );
NOR2X1TS U1310 ( .A(n3759), .B(n3769), .Y(n3772) );
NAND2X1TS U1311 ( .A(n3071), .B(n3073), .Y(n2990) );
XOR2X1TS U1312 ( .A(n3986), .B(n3985), .Y(Sgf_operation_ODD1_right_N15) );
AOI21X2TS U1313 ( .A0(n1326), .A1(n6085), .B0(n1325), .Y(n1327) );
XOR2X1TS U1314 ( .A(n3979), .B(n3978), .Y(Sgf_operation_ODD1_right_N16) );
XOR2X1TS U1315 ( .A(n3967), .B(n2427), .Y(Sgf_operation_ODD1_right_N17) );
AOI21X2TS U1316 ( .A0(n3150), .A1(n2439), .B0(n2438), .Y(n3126) );
NAND2X1TS U1317 ( .A(n2550), .B(n3912), .Y(n2552) );
AOI21X1TS U1318 ( .A0(n2560), .A1(n2554), .B0(n2553), .Y(n3770) );
OAI21X1TS U1319 ( .A0(n3182), .A1(n3181), .B0(n3180), .Y(n3187) );
XOR2X1TS U1320 ( .A(n4898), .B(n4897), .Y(Sgf_operation_ODD1_middle_N15) );
OAI21X1TS U1321 ( .A0(n4892), .A1(n4885), .B0(n4889), .Y(n4888) );
AOI21X1TS U1322 ( .A0(n2515), .A1(n4819), .B0(n2514), .Y(n2516) );
OAI21X1TS U1323 ( .A0(n4892), .A1(n4879), .B0(n4878), .Y(n4884) );
OAI21X1TS U1324 ( .A0(n4779), .A1(n4785), .B0(n4780), .Y(n4666) );
OAI21X1TS U1325 ( .A0(n6172), .A1(n6208), .B0(n6209), .Y(n6177) );
OAI21X1TS U1326 ( .A0(n2982), .A1(n2981), .B0(n2980), .Y(n2983) );
AOI21X2TS U1327 ( .A0(n4877), .A1(n2506), .B0(n2505), .Y(n4859) );
XOR2X1TS U1328 ( .A(n3182), .B(n2417), .Y(Sgf_operation_ODD1_left_N15) );
XOR2X1TS U1329 ( .A(n4892), .B(n4891), .Y(Sgf_operation_ODD1_middle_N16) );
NOR2X1TS U1330 ( .A(n4844), .B(n4845), .Y(n2513) );
XOR2X1TS U1331 ( .A(n3192), .B(n3191), .Y(Sgf_operation_ODD1_left_N14) );
OAI21X1TS U1332 ( .A0(n3913), .A1(n3919), .B0(n3914), .Y(n2549) );
NOR2X1TS U1333 ( .A(n4879), .B(n4880), .Y(n2506) );
XOR2X1TS U1334 ( .A(n3993), .B(n2401), .Y(Sgf_operation_ODD1_right_N12) );
NAND2X1TS U1335 ( .A(n2973), .B(n2979), .Y(n2981) );
NOR2X1TS U1336 ( .A(n3152), .B(n3153), .Y(n2439) );
OR2X2TS U1337 ( .A(mult_x_24_n785), .B(mult_x_24_n797), .Y(n883) );
OR2X2TS U1338 ( .A(DP_OP_169J43_123_4229_n761), .B(
DP_OP_169J43_123_4229_n769), .Y(n4751) );
NAND2X1TS U1339 ( .A(n3891), .B(n751), .Y(n3879) );
OAI21X1TS U1340 ( .A0(n3093), .A1(n3087), .B0(n3088), .Y(n2986) );
OAI21X1TS U1341 ( .A0(n6242), .A1(n6196), .B0(n6195), .Y(n6201) );
OR2X2TS U1342 ( .A(DP_OP_169J43_123_4229_n804), .B(
DP_OP_169J43_123_4229_n792), .Y(n4770) );
XOR2X1TS U1343 ( .A(n4914), .B(n4913), .Y(Sgf_operation_ODD1_middle_N11) );
XOR2X1TS U1344 ( .A(n4904), .B(n2409), .Y(Sgf_operation_ODD1_middle_N12) );
OAI21X1TS U1345 ( .A0(n6242), .A1(n6190), .B0(n6239), .Y(n6193) );
OR2X2TS U1346 ( .A(DP_OP_169J43_123_4229_n780), .B(
DP_OP_169J43_123_4229_n770), .Y(n4760) );
XOR2X1TS U1347 ( .A(n3198), .B(n2302), .Y(Sgf_operation_ODD1_left_N11) );
OR2X2TS U1348 ( .A(mult_x_24_n772), .B(mult_x_24_n784), .Y(n882) );
NAND3BX1TS U1349 ( .AN(Exp_module_Data_S[10]), .B(n6392), .C(n6343), .Y(
n6344) );
OAI21X1TS U1350 ( .A0(n2976), .A1(n3108), .B0(n2975), .Y(n2977) );
OAI21X1TS U1351 ( .A0(n3104), .A1(n3099), .B0(n3100), .Y(n3085) );
OR2X2TS U1352 ( .A(DP_OP_169J43_123_4229_n751), .B(
DP_OP_169J43_123_4229_n760), .Y(n4741) );
OAI21X1TS U1353 ( .A0(n3198), .A1(n3197), .B0(n3196), .Y(n3203) );
OAI21X2TS U1354 ( .A0(n4893), .A1(n2502), .B0(n2501), .Y(n4877) );
OR2X2TS U1355 ( .A(mult_x_24_n614), .B(mult_x_24_n622), .Y(n3883) );
OR2X2TS U1356 ( .A(DP_OP_169J43_123_4229_n729), .B(
DP_OP_169J43_123_4229_n734), .Y(n4725) );
NOR2X2TS U1357 ( .A(n6093), .B(n6092), .Y(n1321) );
OR2X2TS U1358 ( .A(mult_x_24_n632), .B(mult_x_24_n641), .Y(n751) );
OR2X2TS U1359 ( .A(mult_x_24_n809), .B(mult_x_24_n819), .Y(n885) );
OR2X2TS U1360 ( .A(DP_OP_169J43_123_4229_n743), .B(
DP_OP_169J43_123_4229_n750), .Y(n4734) );
OR2X2TS U1361 ( .A(mult_x_24_n583), .B(mult_x_24_n589), .Y(n3857) );
NAND2X1TS U1362 ( .A(n3167), .B(n904), .Y(n2435) );
OR2X2TS U1363 ( .A(mult_x_24_n831), .B(mult_x_24_n840), .Y(n886) );
OR2X2TS U1364 ( .A(mult_x_24_n590), .B(mult_x_24_n596), .Y(n3864) );
AOI21X2TS U1365 ( .A0(n814), .A1(n6105), .B0(n1318), .Y(n6091) );
OR2X2TS U1366 ( .A(mult_x_24_n798), .B(mult_x_24_n808), .Y(n884) );
OR2X2TS U1367 ( .A(mult_x_24_n571), .B(mult_x_24_n576), .Y(n3848) );
OR2X2TS U1368 ( .A(mult_x_23_n547), .B(mult_x_23_n541), .Y(n3066) );
OR2X2TS U1369 ( .A(mult_x_23_n735), .B(mult_x_23_n745), .Y(n903) );
OR2X2TS U1370 ( .A(mult_x_23_n756), .B(mult_x_23_n765), .Y(n904) );
OR2X2TS U1371 ( .A(mult_x_23_n529), .B(mult_x_23_n533), .Y(n3057) );
OR2X2TS U1372 ( .A(mult_x_24_n552), .B(mult_x_24_n555), .Y(n3830) );
OAI21X1TS U1373 ( .A0(n4920), .A1(n4919), .B0(n4918), .Y(n4925) );
OR2X2TS U1374 ( .A(mult_x_23_n548), .B(mult_x_23_n552), .Y(n3073) );
NAND2X2TS U1375 ( .A(n814), .B(n6104), .Y(n6092) );
OR2X2TS U1376 ( .A(DP_OP_169J43_123_4229_n709), .B(
DP_OP_169J43_123_4229_n711), .Y(n4707) );
OR2X2TS U1377 ( .A(mult_x_24_n869), .B(mult_x_24_n876), .Y(n3977) );
OAI21X2TS U1378 ( .A0(n6214), .A1(n1235), .B0(n1234), .Y(n6189) );
OAI21X1TS U1379 ( .A0(n6250), .A1(n6249), .B0(n6248), .Y(n6255) );
OR2X2TS U1380 ( .A(mult_x_24_n841), .B(mult_x_24_n850), .Y(n887) );
OAI21X1TS U1381 ( .A0(n3994), .A1(n3991), .B0(n3995), .Y(n2420) );
NOR2X1TS U1382 ( .A(n3994), .B(n3992), .Y(n2421) );
OR2X2TS U1383 ( .A(mult_x_23_n524), .B(mult_x_23_n520), .Y(n3048) );
OR2X2TS U1384 ( .A(DP_OP_169J43_123_4229_n1236), .B(
DP_OP_169J43_123_4229_n1246), .Y(n4896) );
INVX1TS U1385 ( .A(n6152), .Y(n1322) );
OAI21X1TS U1386 ( .A0(n6197), .A1(n6195), .B0(n6198), .Y(n1241) );
OAI21X1TS U1387 ( .A0(n4032), .A1(n4029), .B0(n4030), .Y(n4028) );
OAI21X1TS U1388 ( .A0(n6033), .A1(n6035), .B0(n6036), .Y(n1353) );
NOR2X1TS U1389 ( .A(n6035), .B(n6034), .Y(n1354) );
OR2X2TS U1390 ( .A(mult_x_23_n516), .B(n2998), .Y(n3039) );
OAI21X1TS U1391 ( .A0(n4926), .A1(n4929), .B0(n4927), .Y(n2403) );
OAI21X1TS U1392 ( .A0(n4008), .A1(n4014), .B0(n4009), .Y(n2395) );
OAI21X1TS U1393 ( .A0(n6230), .A1(n6233), .B0(n6234), .Y(n1232) );
NOR2X1TS U1394 ( .A(n4008), .B(n4013), .Y(n2396) );
OAI21X1TS U1395 ( .A0(n1279), .A1(n1275), .B0(n1276), .Y(n1274) );
NOR2X1TS U1396 ( .A(n4921), .B(n4919), .Y(n2404) );
NOR2X1TS U1397 ( .A(n1577), .B(n4964), .Y(n1578) );
AOI21X2TS U1398 ( .A0(n1290), .A1(n1269), .B0(n1268), .Y(n1279) );
NOR2X1TS U1399 ( .A(n2697), .B(n2847), .Y(n2698) );
OAI21X2TS U1400 ( .A0(n6297), .A1(n6293), .B0(n6294), .Y(n6299) );
OAI21X1TS U1401 ( .A0(n4575), .A1(n2345), .B0(n4508), .Y(n4509) );
OAI21X1TS U1402 ( .A0(n4570), .A1(n1544), .B0(n2768), .Y(n2769) );
OAI21X1TS U1403 ( .A0(n4617), .A1(n4381), .B0(n4351), .Y(n4353) );
OAI21X1TS U1404 ( .A0(n4590), .A1(n2307), .B0(n4452), .Y(n4453) );
OAI21X1TS U1405 ( .A0(n4560), .A1(n2945), .B0(n4219), .Y(n4220) );
OAI21X1TS U1406 ( .A0(n4590), .A1(n1853), .B0(n1808), .Y(n1809) );
OAI21X1TS U1407 ( .A0(n4575), .A1(n1544), .B0(n4173), .Y(n4174) );
OAI21X1TS U1408 ( .A0(n4385), .A1(n4323), .B0(n4271), .Y(n4272) );
OAI21X1TS U1409 ( .A0(n4580), .A1(n1544), .B0(n4175), .Y(n4176) );
OAI21X1TS U1410 ( .A0(n4570), .A1(n2345), .B0(n4506), .Y(n4507) );
OAI21X1TS U1411 ( .A0(n4555), .A1(n4641), .B0(n4554), .Y(n4556) );
OAI21X1TS U1412 ( .A0(n4585), .A1(n2307), .B0(n4450), .Y(n4451) );
OAI21X1TS U1413 ( .A0(n3706), .A1(n3453), .B0(n3444), .Y(n3445) );
OAI21X1TS U1414 ( .A0(n4617), .A1(n2327), .B0(n4616), .Y(n4618) );
OAI21X1TS U1415 ( .A0(n3680), .A1(n2715), .B0(n3520), .Y(n3521) );
OAI21X1TS U1416 ( .A0(n4412), .A1(n4381), .B0(n2914), .Y(n2915) );
AOI21X2TS U1417 ( .A0(n6291), .A1(n874), .B0(n1170), .Y(n6297) );
OAI21X1TS U1418 ( .A0(n4605), .A1(n4641), .B0(n4604), .Y(n4606) );
OAI21X1TS U1419 ( .A0(n4600), .A1(n1544), .B0(n4183), .Y(n4184) );
OAI21X1TS U1420 ( .A0(n4617), .A1(n4092), .B0(n2044), .Y(n2045) );
OAI21X1TS U1421 ( .A0(n4560), .A1(n4641), .B0(n4559), .Y(n4561) );
OAI21X1TS U1422 ( .A0(n4611), .A1(n4269), .B0(n4235), .Y(n4236) );
OAI21X1TS U1423 ( .A0(n4555), .A1(n2927), .B0(n4326), .Y(n4327) );
OAI21X1TS U1424 ( .A0(n4570), .A1(n1428), .B0(n4280), .Y(n4281) );
OAI21X1TS U1425 ( .A0(n3623), .A1(n3636), .B0(n3622), .Y(n3624) );
OAI21X1TS U1426 ( .A0(n4595), .A1(n2307), .B0(n4454), .Y(n4455) );
OAI21X1TS U1427 ( .A0(n3690), .A1(n1877), .B0(n1906), .Y(n1907) );
OAI21X1TS U1428 ( .A0(n3729), .A1(n3475), .B0(n3456), .Y(n3457) );
OAI21X1TS U1429 ( .A0(n4595), .A1(n1428), .B0(n4290), .Y(n4291) );
OAI21X1TS U1430 ( .A0(n4580), .A1(n1853), .B0(n1769), .Y(n1770) );
OAI21X1TS U1431 ( .A0(n3706), .A1(n1877), .B0(n1933), .Y(n1934) );
OAI21X1TS U1432 ( .A0(n4412), .A1(n2327), .B0(n2935), .Y(n2936) );
OAI21X1TS U1433 ( .A0(n3690), .A1(n2715), .B0(n3524), .Y(n3525) );
OAI21X1TS U1434 ( .A0(n4565), .A1(n1544), .B0(n2749), .Y(n2750) );
OAI21X1TS U1435 ( .A0(n4385), .A1(n4269), .B0(n4048), .Y(n4049) );
OAI21X1TS U1436 ( .A0(n4600), .A1(n4641), .B0(n4599), .Y(n4601) );
OAI21X1TS U1437 ( .A0(n3690), .A1(n3728), .B0(n3689), .Y(n3691) );
OAI21X1TS U1438 ( .A0(n4585), .A1(n1853), .B0(n4052), .Y(n4053) );
OAI21X1TS U1439 ( .A0(n4555), .A1(n2945), .B0(n4217), .Y(n4218) );
OAI21X1TS U1440 ( .A0(n3680), .A1(n3453), .B0(n2781), .Y(n2782) );
OAI21X1TS U1441 ( .A0(n3690), .A1(n3407), .B0(n1801), .Y(n1802) );
OAI21X1TS U1442 ( .A0(n4575), .A1(n2307), .B0(n4446), .Y(n4447) );
OAI21X1TS U1443 ( .A0(n4560), .A1(n2345), .B0(n4502), .Y(n4503) );
OAI21X1TS U1444 ( .A0(n4611), .A1(n4092), .B0(n1854), .Y(n1855) );
OAI21X1TS U1445 ( .A0(n4565), .A1(n1853), .B0(n1732), .Y(n1733) );
OAI21X1TS U1446 ( .A0(n3680), .A1(n3407), .B0(n1789), .Y(n1790) );
OAI21X1TS U1447 ( .A0(n4605), .A1(n1428), .B0(n4294), .Y(n4295) );
OAI21X1TS U1448 ( .A0(n4385), .A1(n4214), .B0(n4166), .Y(n4167) );
OAI21X1TS U1449 ( .A0(n4412), .A1(n4269), .B0(n4241), .Y(n4243) );
OAI21X1TS U1450 ( .A0(n4555), .A1(n2345), .B0(n4500), .Y(n4501) );
OAI21X1TS U1451 ( .A0(n4560), .A1(n2307), .B0(n4440), .Y(n4441) );
OAI21X1TS U1452 ( .A0(n4590), .A1(n2927), .B0(n4340), .Y(n4341) );
OAI21X1TS U1453 ( .A0(n4385), .A1(n4550), .B0(n2855), .Y(n2856) );
OAI21X1TS U1454 ( .A0(n4611), .A1(n4323), .B0(n4296), .Y(n4297) );
OAI21X1TS U1455 ( .A0(n4570), .A1(n1853), .B0(n4163), .Y(n4165) );
OAI21X1TS U1456 ( .A0(n3706), .A1(n3728), .B0(n3705), .Y(n3707) );
XNOR2X1TS U1457 ( .A(n5565), .B(n5396), .Y(n5385) );
OAI21X1TS U1458 ( .A0(n4570), .A1(n2307), .B0(n4444), .Y(n4445) );
OAI21X1TS U1459 ( .A0(n4617), .A1(n4323), .B0(n4299), .Y(n4300) );
OAI21X1TS U1460 ( .A0(n4600), .A1(n2927), .B0(n4344), .Y(n4345) );
OAI21X1TS U1461 ( .A0(n4412), .A1(n4323), .B0(n4301), .Y(n4303) );
OAI21X1TS U1462 ( .A0(n4575), .A1(n1853), .B0(n1761), .Y(n1762) );
OAI21X1TS U1463 ( .A0(n4560), .A1(n1544), .B0(n4171), .Y(n4172) );
OAI21X1TS U1464 ( .A0(n4595), .A1(n2927), .B0(n4342), .Y(n4343) );
NOR2X1TS U1465 ( .A(n2616), .B(n4964), .Y(n2617) );
OAI21X1TS U1466 ( .A0(n4565), .A1(n2945), .B0(n4221), .Y(n4222) );
OAI21X1TS U1467 ( .A0(n3623), .A1(n3728), .B0(n2803), .Y(n2804) );
OAI21X1TS U1468 ( .A0(n4580), .A1(n2307), .B0(n4448), .Y(n4449) );
OAI21X1TS U1469 ( .A0(n4585), .A1(n1544), .B0(n4177), .Y(n4178) );
OAI21X1TS U1470 ( .A0(n4600), .A1(n1853), .B0(n1945), .Y(n1946) );
OAI21X1TS U1471 ( .A0(n4555), .A1(n1428), .B0(n4274), .Y(n4275) );
OAI21X1TS U1472 ( .A0(n3729), .A1(n3428), .B0(n3410), .Y(n3411) );
OAI21X1TS U1473 ( .A0(n3706), .A1(n2715), .B0(n3532), .Y(n3533) );
OAI21X1TS U1474 ( .A0(n3706), .A1(n2785), .B0(n3384), .Y(n3385) );
OAI21X1TS U1475 ( .A0(n4570), .A1(n2945), .B0(n4223), .Y(n4224) );
OAI21X1TS U1476 ( .A0(n4605), .A1(n1853), .B0(n2003), .Y(n2004) );
OAI21X1TS U1477 ( .A0(n4590), .A1(n1544), .B0(n4179), .Y(n4180) );
OAI21X1TS U1478 ( .A0(n3623), .A1(n1877), .B0(n1931), .Y(n1932) );
OAI21X1TS U1479 ( .A0(n4580), .A1(n2927), .B0(n4336), .Y(n4337) );
OAI21X1TS U1480 ( .A0(n3680), .A1(n3636), .B0(n3613), .Y(n3614) );
OAI21X1TS U1481 ( .A0(n4600), .A1(n1428), .B0(n4292), .Y(n4293) );
OAI21X1TS U1482 ( .A0(n4617), .A1(n4269), .B0(n4238), .Y(n4239) );
OAI21X1TS U1483 ( .A0(n4555), .A1(n2307), .B0(n4438), .Y(n4439) );
OAI21X1TS U1484 ( .A0(n4385), .A1(n4381), .B0(n4058), .Y(n4059) );
OAI21X1TS U1485 ( .A0(n4560), .A1(n1428), .B0(n4276), .Y(n4277) );
OAI21X1TS U1486 ( .A0(n1295), .A1(n1291), .B0(n1292), .Y(n1260) );
OAI21X1TS U1487 ( .A0(n3623), .A1(n2715), .B0(n3528), .Y(n3529) );
OAI21X1TS U1488 ( .A0(n4385), .A1(n4092), .B0(n3799), .Y(n3800) );
OAI21X1TS U1489 ( .A0(n4575), .A1(n2945), .B0(n4225), .Y(n4226) );
OAI21X1TS U1490 ( .A0(n4385), .A1(n4435), .B0(n4384), .Y(n4386) );
OAI21X1TS U1491 ( .A0(n4595), .A1(n1544), .B0(n4181), .Y(n4182) );
OAI21X1TS U1492 ( .A0(n4595), .A1(n2945), .B0(n4229), .Y(n4230) );
OAI21X1TS U1493 ( .A0(n4580), .A1(n2945), .B0(n2810), .Y(n2811) );
OAI21X1TS U1494 ( .A0(n4580), .A1(n1428), .B0(n4284), .Y(n4285) );
OAI21X1TS U1495 ( .A0(n4565), .A1(n1428), .B0(n4278), .Y(n4279) );
OAI21X1TS U1496 ( .A0(n4555), .A1(n1853), .B0(n3794), .Y(n3795) );
OAI21X1TS U1497 ( .A0(n4611), .A1(n4214), .B0(n4187), .Y(n4188) );
OAI21X1TS U1498 ( .A0(n4565), .A1(n2927), .B0(n4330), .Y(n4331) );
OAI21X1TS U1499 ( .A0(n4611), .A1(n4381), .B0(n4348), .Y(n4349) );
OAI21X1TS U1500 ( .A0(n4560), .A1(n1853), .B0(n1705), .Y(n1706) );
OAI21X1TS U1501 ( .A0(n4385), .A1(n2327), .B0(n2898), .Y(n2899) );
OAI21X1TS U1502 ( .A0(n3690), .A1(n2785), .B0(n3378), .Y(n3379) );
OAI21X1TS U1503 ( .A0(n3729), .A1(n3665), .B0(n3639), .Y(n3640) );
OAI21X1TS U1504 ( .A0(n3680), .A1(n1900), .B0(n1904), .Y(n1905) );
OAI21X1TS U1505 ( .A0(n4575), .A1(n4641), .B0(n4574), .Y(n4576) );
OAI21X1TS U1506 ( .A0(n4585), .A1(n1428), .B0(n4286), .Y(n4287) );
OAI21X1TS U1507 ( .A0(n4580), .A1(n4641), .B0(n4579), .Y(n4581) );
OAI21X1TS U1508 ( .A0(n4595), .A1(n2345), .B0(n4516), .Y(n4517) );
OAI21X1TS U1509 ( .A0(n4611), .A1(n4550), .B0(n2812), .Y(n2813) );
OAI21X1TS U1510 ( .A0(n4412), .A1(n4496), .B0(n2957), .Y(n2958) );
OAI21X1TS U1511 ( .A0(n3706), .A1(n1900), .B0(n1947), .Y(n1948) );
OAI21X1TS U1512 ( .A0(n4595), .A1(n4641), .B0(n4594), .Y(n4596) );
OAI21X1TS U1513 ( .A0(n4617), .A1(n4214), .B0(n4190), .Y(n4191) );
OAI21X1TS U1514 ( .A0(n4617), .A1(n4496), .B0(n4463), .Y(n4465) );
OAI21X1TS U1515 ( .A0(n3690), .A1(n3453), .B0(n3438), .Y(n3439) );
OAI21X1TS U1516 ( .A0(n3680), .A1(n1877), .B0(n3478), .Y(n3479) );
OAI21X1TS U1517 ( .A0(n4575), .A1(n2927), .B0(n4334), .Y(n4335) );
OAI21X1TS U1518 ( .A0(n3690), .A1(n3636), .B0(n3617), .Y(n3618) );
OAI21X1TS U1519 ( .A0(n4611), .A1(n2327), .B0(n4610), .Y(n4612) );
OAI21X1TS U1520 ( .A0(n3623), .A1(n1900), .B0(n1846), .Y(n1847) );
OAI21X1TS U1521 ( .A0(n4585), .A1(n4641), .B0(n4584), .Y(n4586) );
OAI21X1TS U1522 ( .A0(n4605), .A1(n2945), .B0(n4233), .Y(n4234) );
OAI21X1TS U1523 ( .A0(n4590), .A1(n1428), .B0(n4288), .Y(n4289) );
OAI21X1TS U1524 ( .A0(n3623), .A1(n3453), .B0(n3440), .Y(n3441) );
OAI21X1TS U1525 ( .A0(n4600), .A1(n2945), .B0(n4231), .Y(n4232) );
OAI21X1TS U1526 ( .A0(n4570), .A1(n2927), .B0(n4332), .Y(n4333) );
OAI21X1TS U1527 ( .A0(n4412), .A1(n4214), .B0(n4192), .Y(n4194) );
OAI21X1TS U1528 ( .A0(n4605), .A1(n2345), .B0(n2814), .Y(n2815) );
OAI21X1TS U1529 ( .A0(n3729), .A1(n3402), .B0(n3391), .Y(n3392) );
OAI21X1TS U1530 ( .A0(n3729), .A1(n3510), .B0(n3486), .Y(n3487) );
OAI21X1TS U1531 ( .A0(n4590), .A1(n4641), .B0(n4589), .Y(n4591) );
OAI21X1TS U1532 ( .A0(n4412), .A1(n4092), .B0(n2038), .Y(n2039) );
OAI21X1TS U1533 ( .A0(n4617), .A1(n4435), .B0(n4409), .Y(n4410) );
OAI21X1TS U1534 ( .A0(n4412), .A1(n4550), .B0(n2902), .Y(n2903) );
OAI21X1TS U1535 ( .A0(n4560), .A1(n2927), .B0(n4328), .Y(n4329) );
OAI21X1TS U1536 ( .A0(n4590), .A1(n2345), .B0(n4514), .Y(n4515) );
OAI21X1TS U1537 ( .A0(n4585), .A1(n2345), .B0(n4512), .Y(n4513) );
OAI21X1TS U1538 ( .A0(n4590), .A1(n2945), .B0(n4227), .Y(n4228) );
OAI21X1TS U1539 ( .A0(n4575), .A1(n1428), .B0(n4282), .Y(n4283) );
OAI21X1TS U1540 ( .A0(n4570), .A1(n4641), .B0(n4569), .Y(n4571) );
OAI21X1TS U1541 ( .A0(n4600), .A1(n2307), .B0(n4456), .Y(n4457) );
OAI21X1TS U1542 ( .A0(n3729), .A1(n3562), .B0(n3543), .Y(n3544) );
OAI21X1TS U1543 ( .A0(n4605), .A1(n1544), .B0(n4185), .Y(n4186) );
OAI21X1TS U1544 ( .A0(n4385), .A1(n4496), .B0(n2900), .Y(n2901) );
OAI21X1TS U1545 ( .A0(n4412), .A1(n4435), .B0(n4411), .Y(n4414) );
OAI21X1TS U1546 ( .A0(n4585), .A1(n2945), .B0(n4062), .Y(n4063) );
OAI21X1TS U1547 ( .A0(n4580), .A1(n2345), .B0(n4510), .Y(n4511) );
OAI21X1TS U1548 ( .A0(n4565), .A1(n4641), .B0(n4564), .Y(n4566) );
OAI21X1TS U1549 ( .A0(n3680), .A1(n2785), .B0(n3376), .Y(n3377) );
OAI21X1TS U1550 ( .A0(n4605), .A1(n2307), .B0(n4458), .Y(n4459) );
OAI21X1TS U1551 ( .A0(n3623), .A1(n3407), .B0(n1837), .Y(n1838) );
OAI21X1TS U1552 ( .A0(n4623), .A1(n2307), .B0(n4467), .Y(n4468) );
XNOR2X1TS U1553 ( .A(n1347), .B(n1346), .Y(n1348) );
OAI21X1TS U1554 ( .A0(n4634), .A1(n4381), .B0(n4360), .Y(n4361) );
OAI21X1TS U1555 ( .A0(n4623), .A1(n1544), .B0(n4196), .Y(n4197) );
OAI21X1TS U1556 ( .A0(n3723), .A1(n2785), .B0(n3260), .Y(n3261) );
OAI21X1TS U1557 ( .A0(n3717), .A1(n2785), .B0(n3388), .Y(n3390) );
OAI21X1TS U1558 ( .A0(n3717), .A1(n3407), .B0(n1870), .Y(n1871) );
OAI21X1TS U1559 ( .A0(n4634), .A1(n4641), .B0(n4633), .Y(n4636) );
OAI21X1TS U1560 ( .A0(n4623), .A1(n2927), .B0(n4355), .Y(n4356) );
OAI21X1TS U1561 ( .A0(n3711), .A1(n1877), .B0(n1980), .Y(n1981) );
OAI21X1TS U1562 ( .A0(n3711), .A1(n3407), .B0(n1911), .Y(n1912) );
OAI21X1TS U1563 ( .A0(n3611), .A1(n3665), .B0(n3610), .Y(n3612) );
OAI21X1TS U1564 ( .A0(n3755), .A1(n3475), .B0(n3465), .Y(n3466) );
OAI21X1TS U1565 ( .A0(n4623), .A1(n2345), .B0(n4525), .Y(n4526) );
OAI21X1TS U1566 ( .A0(n3723), .A1(n1877), .B0(n3483), .Y(n3485) );
OAI21X1TS U1567 ( .A0(n3685), .A1(n1877), .B0(n3480), .Y(n3481) );
OAI21X1TS U1568 ( .A0(n3668), .A1(n2785), .B0(n757), .Y(n3004) );
OAI21X1TS U1569 ( .A0(n4629), .A1(n1853), .B0(n2066), .Y(n2067) );
OAI21X1TS U1570 ( .A0(n3685), .A1(n2785), .B0(n3244), .Y(n3245) );
OAI21X1TS U1571 ( .A0(n3740), .A1(n3510), .B0(n3491), .Y(n3492) );
OAI21X1TS U1572 ( .A0(n847), .A1(n3728), .B0(n3675), .Y(n3676) );
OAI21X1TS U1573 ( .A0(n3701), .A1(n3453), .B0(n3442), .Y(n3443) );
OAI21X1TS U1574 ( .A0(n3685), .A1(n1900), .B0(n1929), .Y(n1930) );
OAI21X1TS U1575 ( .A0(n3717), .A1(n1877), .B0(n1875), .Y(n1876) );
OAI21X1TS U1576 ( .A0(n3668), .A1(n2236), .B0(n758), .Y(n3669) );
OAI21X1TS U1577 ( .A0(n3745), .A1(n3510), .B0(n3493), .Y(n3494) );
OAI21X1TS U1578 ( .A0(n4629), .A1(n2327), .B0(n4628), .Y(n4630) );
OAI21X1TS U1579 ( .A0(n4629), .A1(n4435), .B0(n4419), .Y(n4420) );
OAI21X1TS U1580 ( .A0(n3701), .A1(n2715), .B0(n3530), .Y(n3531) );
OAI21X1TS U1581 ( .A0(n4623), .A1(n4424), .B0(n4416), .Y(n4417) );
OAI21X1TS U1582 ( .A0(n3701), .A1(n1900), .B0(n1889), .Y(n1890) );
OAI21X1TS U1583 ( .A0(n3711), .A1(n1900), .B0(n1992), .Y(n1993) );
OAI21X1TS U1584 ( .A0(n4634), .A1(n4435), .B0(n4421), .Y(n4422) );
OAI21X1TS U1585 ( .A0(n3685), .A1(n3728), .B0(n3684), .Y(n3686) );
OAI21X1TS U1586 ( .A0(n847), .A1(n3636), .B0(n3607), .Y(n3608) );
OAI21X1TS U1587 ( .A0(n3611), .A1(n3728), .B0(n2805), .Y(n2806) );
OAI21X1TS U1588 ( .A0(n3723), .A1(n3407), .B0(n3406), .Y(n3409) );
OAI21X1TS U1589 ( .A0(n3611), .A1(n3428), .B0(n1753), .Y(n1754) );
OAI21X1TS U1590 ( .A0(n3668), .A1(n3665), .B0(n894), .Y(n3602) );
OAI21X1TS U1591 ( .A0(n3745), .A1(n3402), .B0(n3401), .Y(n3403) );
OAI21X1TS U1592 ( .A0(n3711), .A1(n2715), .B0(n3534), .Y(n3535) );
XNOR2X1TS U1593 ( .A(n1301), .B(n1300), .Y(n1309) );
OAI21X1TS U1594 ( .A0(n3611), .A1(n1900), .B0(n1898), .Y(n1899) );
OAI21X1TS U1595 ( .A0(n4623), .A1(n2945), .B0(n4245), .Y(n4246) );
OAI21X1TS U1596 ( .A0(n3740), .A1(n3402), .B0(n3396), .Y(n3397) );
OAI21X1TS U1597 ( .A0(n4623), .A1(n4641), .B0(n4622), .Y(n4624) );
OAI21X1TS U1598 ( .A0(n3711), .A1(n3636), .B0(n3629), .Y(n3630) );
OAI21X1TS U1599 ( .A0(n3668), .A1(n3428), .B0(n893), .Y(n3404) );
OAI21X1TS U1600 ( .A0(n3740), .A1(n3562), .B0(n3548), .Y(n3549) );
OAI21X1TS U1601 ( .A0(n3717), .A1(n3728), .B0(n3716), .Y(n3718) );
OAI21X1TS U1602 ( .A0(n3685), .A1(n3407), .B0(n1823), .Y(n1824) );
OAI21X1TS U1603 ( .A0(n3685), .A1(n2715), .B0(n3522), .Y(n3523) );
OAI21X1TS U1604 ( .A0(n3740), .A1(n3475), .B0(n3461), .Y(n3462) );
OAI21X1TS U1605 ( .A0(n3717), .A1(n3453), .B0(n3449), .Y(n3450) );
OAI21X1TS U1606 ( .A0(n3755), .A1(n3428), .B0(n3293), .Y(n3294) );
OAI21X1TS U1607 ( .A0(n3755), .A1(n3665), .B0(n3648), .Y(n3649) );
OAI21X1TS U1608 ( .A0(n847), .A1(n3599), .B0(n1902), .Y(n1903) );
OAI21X1TS U1609 ( .A0(n4629), .A1(n1428), .B0(n4308), .Y(n4309) );
XNOR2X1TS U1610 ( .A(n1306), .B(n1305), .Y(n1308) );
OAI21X1TS U1611 ( .A0(n3685), .A1(n3453), .B0(n3436), .Y(n3437) );
OAI21X1TS U1612 ( .A0(n4634), .A1(n1544), .B0(n4201), .Y(n4202) );
OAI21X1TS U1613 ( .A0(n3745), .A1(n3665), .B0(n3646), .Y(n3647) );
OAI21X1TS U1614 ( .A0(n4623), .A1(n1428), .B0(n4305), .Y(n4306) );
OAI21X1TS U1615 ( .A0(n3740), .A1(n3665), .B0(n3644), .Y(n3645) );
OAI21X1TS U1616 ( .A0(n4634), .A1(n4550), .B0(n4530), .Y(n4531) );
OAI21X1TS U1617 ( .A0(n3711), .A1(n2785), .B0(n3256), .Y(n3257) );
OAI21X1TS U1618 ( .A0(n4629), .A1(n4214), .B0(n4199), .Y(n4200) );
OAI21X1TS U1619 ( .A0(n3685), .A1(n3636), .B0(n3615), .Y(n3616) );
OAI21X1TS U1620 ( .A0(n4623), .A1(n1853), .B0(n2056), .Y(n2057) );
OAI21X1TS U1621 ( .A0(n3701), .A1(n3728), .B0(n3700), .Y(n3702) );
OAI21X1TS U1622 ( .A0(n3701), .A1(n3636), .B0(n3625), .Y(n3626) );
OAI21X1TS U1623 ( .A0(n3745), .A1(n3475), .B0(n3463), .Y(n3464) );
OAI21X1TS U1624 ( .A0(n3740), .A1(n3428), .B0(n2799), .Y(n2800) );
OAI21X1TS U1625 ( .A0(n847), .A1(n3475), .B0(n3432), .Y(n3433) );
OAI21X1TS U1626 ( .A0(n3723), .A1(n1900), .B0(n2013), .Y(n2014) );
OAI21X1TS U1627 ( .A0(n3668), .A1(n3562), .B0(n2719), .Y(n2720) );
OAI21X1TS U1628 ( .A0(n4634), .A1(n2307), .B0(n4472), .Y(n4474) );
OAI21X1TS U1629 ( .A0(n3701), .A1(n2785), .B0(n3382), .Y(n3383) );
OAI21X1TS U1630 ( .A0(n4634), .A1(n4269), .B0(n4250), .Y(n4251) );
OAI21X1TS U1631 ( .A0(n3668), .A1(n3510), .B0(n899), .Y(n3477) );
OAI21X1TS U1632 ( .A0(n3668), .A1(n3453), .B0(n2756), .Y(n2757) );
OAI21X1TS U1633 ( .A0(n3723), .A1(n3453), .B0(n3452), .Y(n3455) );
OAI21X1TS U1634 ( .A0(n3611), .A1(n3402), .B0(n3374), .Y(n3375) );
OAI21X1TS U1635 ( .A0(n3755), .A1(n3599), .B0(n3576), .Y(n3577) );
OAI21X1TS U1636 ( .A0(n3740), .A1(n3599), .B0(n3572), .Y(n3573) );
OAI21X1TS U1637 ( .A0(n847), .A1(n3428), .B0(n1747), .Y(n1748) );
OAI21X1TS U1638 ( .A0(n3745), .A1(n3562), .B0(n3550), .Y(n3551) );
OAI21X1TS U1639 ( .A0(n3745), .A1(n2236), .B0(n3744), .Y(n3747) );
OAI21X1TS U1640 ( .A0(n3611), .A1(n3475), .B0(n3434), .Y(n3435) );
OAI21X1TS U1641 ( .A0(n4634), .A1(n4323), .B0(n4310), .Y(n4311) );
XNOR2X1TS U1642 ( .A(n1079), .B(n1078), .Y(n1236) );
OAI21X1TS U1643 ( .A0(n3585), .A1(n3402), .B0(n3303), .Y(n3304) );
OAI21X1TS U1644 ( .A0(n3666), .A1(n3402), .B0(n3291), .Y(n3292) );
OAI21X1TS U1645 ( .A0(n3652), .A1(n3428), .B0(n3301), .Y(n3302) );
OAI21X1TS U1646 ( .A0(n3652), .A1(n3402), .B0(n3278), .Y(n3279) );
OAI21X1TS U1647 ( .A0(n873), .A1(n3562), .B0(n3556), .Y(n3557) );
OAI21X1TS U1648 ( .A0(n4538), .A1(n4496), .B0(n4479), .Y(n4480) );
INVX2TS U1649 ( .A(n1296), .Y(n1306) );
OAI21X1TS U1650 ( .A0(n3735), .A1(n3475), .B0(n3459), .Y(n3460) );
OAI21X1TS U1651 ( .A0(n3696), .A1(n1900), .B0(n1891), .Y(n1892) );
OAI21X1TS U1652 ( .A0(n3696), .A1(n3407), .B0(n1893), .Y(n1894) );
OAI21X1TS U1653 ( .A0(n3735), .A1(n3428), .B0(n3413), .Y(n3414) );
OAI21X1TS U1654 ( .A0(n873), .A1(n3428), .B0(n3415), .Y(n3416) );
OAI21X1TS U1655 ( .A0(n4551), .A1(n4092), .B0(n2071), .Y(n2072) );
OAI21X1TS U1656 ( .A0(n4538), .A1(n4092), .B0(n2011), .Y(n2012) );
OAI21X1TS U1657 ( .A0(n2714), .A1(n3728), .B0(n3671), .Y(n3672) );
OAI21X1TS U1658 ( .A0(n3652), .A1(n3599), .B0(n2839), .Y(n2840) );
OAI21X1TS U1659 ( .A0(n3585), .A1(n3562), .B0(n2842), .Y(n2843) );
OAI21X1TS U1660 ( .A0(n1069), .A1(n1075), .B0(n1076), .Y(n1074) );
OAI21X1TS U1661 ( .A0(n3696), .A1(n3636), .B0(n3619), .Y(n3620) );
OAI21X1TS U1662 ( .A0(n4543), .A1(n2327), .B0(n2388), .Y(n2389) );
OAI21X1TS U1663 ( .A0(n873), .A1(n3402), .B0(n2787), .Y(n2788) );
OAI21X1TS U1664 ( .A0(n4538), .A1(n4323), .B0(n4316), .Y(n4317) );
OAI21X1TS U1665 ( .A0(n3735), .A1(n3562), .B0(n3546), .Y(n3547) );
OAI21X1TS U1666 ( .A0(n4538), .A1(n2327), .B0(n2331), .Y(n2332) );
OAI21X1TS U1667 ( .A0(n4538), .A1(n4381), .B0(n4366), .Y(n4367) );
OAI21X1TS U1668 ( .A0(n4642), .A1(n4323), .B0(n4312), .Y(n4313) );
OAI21X1TS U1669 ( .A0(n4543), .A1(n4269), .B0(n4258), .Y(n4259) );
OAI21X1TS U1670 ( .A0(n3696), .A1(n2715), .B0(n3526), .Y(n3527) );
OAI21X1TS U1671 ( .A0(n2714), .A1(n3407), .B0(n2724), .Y(n2725) );
OAI21X1TS U1672 ( .A0(n3696), .A1(n3728), .B0(n3695), .Y(n3697) );
OAI21X1TS U1673 ( .A0(n2714), .A1(n3665), .B0(n3603), .Y(n3605) );
OAI21X1TS U1674 ( .A0(n3652), .A1(n3475), .B0(n3467), .Y(n3468) );
OAI21X1TS U1675 ( .A0(n4543), .A1(n4381), .B0(n4368), .Y(n4369) );
OAI21X1TS U1676 ( .A0(n4538), .A1(n4269), .B0(n4256), .Y(n4257) );
OAI21X1TS U1677 ( .A0(n4642), .A1(n4424), .B0(n4423), .Y(n4425) );
OAI21X1TS U1678 ( .A0(n3666), .A1(n3428), .B0(n3417), .Y(n3418) );
OAI21X1TS U1679 ( .A0(n873), .A1(n3510), .B0(n3497), .Y(n3498) );
OAI21X1TS U1680 ( .A0(n4538), .A1(n4550), .B0(n4537), .Y(n4539) );
OAI21X1TS U1681 ( .A0(n3666), .A1(n3510), .B0(n3499), .Y(n3500) );
OAI21X1TS U1682 ( .A0(n4650), .A1(n4435), .B0(n4426), .Y(n4427) );
OAI21X1TS U1683 ( .A0(n3735), .A1(n3599), .B0(n3570), .Y(n3571) );
OAI21X1TS U1684 ( .A0(n4650), .A1(n4550), .B0(n4534), .Y(n4535) );
OAI21X1TS U1685 ( .A0(n3652), .A1(n3562), .B0(n3554), .Y(n3555) );
OAI21X1TS U1686 ( .A0(n4551), .A1(n4496), .B0(n4483), .Y(n4484) );
NOR2X1TS U1687 ( .A(n1977), .B(n4964), .Y(n1978) );
OAI21X1TS U1688 ( .A0(n2714), .A1(n3475), .B0(n3251), .Y(n3252) );
OAI21X1TS U1689 ( .A0(n4543), .A1(n4496), .B0(n4481), .Y(n4482) );
OAI21X1TS U1690 ( .A0(n3696), .A1(n2785), .B0(n3380), .Y(n3381) );
OAI21X1TS U1691 ( .A0(n4642), .A1(n2345), .B0(n4532), .Y(n4533) );
OAI21X1TS U1692 ( .A0(n2714), .A1(n3562), .B0(n3513), .Y(n3514) );
OAI21X1TS U1693 ( .A0(n4650), .A1(n4092), .B0(n4091), .Y(n4094) );
OAI21X1TS U1694 ( .A0(n3585), .A1(n3599), .B0(n3584), .Y(n3586) );
OAI21X1TS U1695 ( .A0(n3652), .A1(n2236), .B0(n2197), .Y(n2198) );
OAI21X1TS U1696 ( .A0(n3652), .A1(n3665), .B0(n3651), .Y(n3653) );
OAI21X1TS U1697 ( .A0(n4642), .A1(n4092), .B0(n4074), .Y(n4076) );
OAI21X1TS U1698 ( .A0(n3585), .A1(n3665), .B0(n2211), .Y(n2212) );
OAI21X1TS U1699 ( .A0(n3735), .A1(n3402), .B0(n3394), .Y(n3395) );
OAI21X1TS U1700 ( .A0(n873), .A1(n3599), .B0(n3578), .Y(n3579) );
OAI21X1TS U1701 ( .A0(n3666), .A1(n3599), .B0(n3580), .Y(n3581) );
OAI21X1TS U1702 ( .A0(n2714), .A1(n3402), .B0(n2994), .Y(n2995) );
OAI21X1TS U1703 ( .A0(n1344), .A1(n1336), .B0(n1335), .Y(n1341) );
OAI21X1TS U1704 ( .A0(n4374), .A1(n4550), .B0(n2325), .Y(n2326) );
OAI21XLTS U1705 ( .A0(n3353), .A1(n1609), .B0(n3300), .Y(n3307) );
OAI21X1TS U1706 ( .A0(n2741), .A1(n1467), .B0(n1466), .Y(n1469) );
OAI21X1TS U1707 ( .A0(n3590), .A1(n3402), .B0(n3315), .Y(n3316) );
OAI21X1TS U1708 ( .A0(n2741), .A1(n1580), .B0(n1581), .Y(n1474) );
OAI21X1TS U1709 ( .A0(n2741), .A1(n2690), .B0(n2689), .Y(n2695) );
XNOR2X1TS U1710 ( .A(n1253), .B(n1225), .Y(n1227) );
OAI21X1TS U1711 ( .A0(n2741), .A1(n1570), .B0(n1569), .Y(n1575) );
OAI21X1TS U1712 ( .A0(n4374), .A1(n4435), .B0(n2940), .Y(n2941) );
OAI21X1TS U1713 ( .A0(n3590), .A1(n3599), .B0(n3589), .Y(n3591) );
OAI21X1TS U1714 ( .A0(n4374), .A1(n4496), .B0(n2874), .Y(n2875) );
OAI21X1TS U1715 ( .A0(n4374), .A1(n4381), .B0(n4373), .Y(n4375) );
OAI21X1TS U1716 ( .A0(n3590), .A1(n3562), .B0(n3357), .Y(n3358) );
OAI21X1TS U1717 ( .A0(n2741), .A1(n2465), .B0(n2464), .Y(n2470) );
OAI21XLTS U1718 ( .A0(n831), .A1(n1609), .B0(n3290), .Y(n3297) );
OAI21X1TS U1719 ( .A0(n4374), .A1(n4269), .B0(n4262), .Y(n4263) );
OAI21X1TS U1720 ( .A0(n2741), .A1(n1586), .B0(n1585), .Y(n1591) );
OAI21X1TS U1721 ( .A0(n2741), .A1(n2740), .B0(n2098), .Y(n2099) );
OAI21X1TS U1722 ( .A0(n2741), .A1(n2673), .B0(n2672), .Y(n2676) );
OAI21X1TS U1723 ( .A0(n4374), .A1(n4214), .B0(n2919), .Y(n2920) );
OAI21X1TS U1724 ( .A0(n4374), .A1(n2327), .B0(n2351), .Y(n2352) );
OAI21X1TS U1725 ( .A0(n4374), .A1(n4323), .B0(n2964), .Y(n2965) );
OAI21X1TS U1726 ( .A0(n4488), .A1(n4381), .B0(n4376), .Y(n4377) );
NOR2X1TS U1727 ( .A(n3782), .B(n1726), .Y(n1728) );
NOR2X1TS U1728 ( .A(n2883), .B(n2889), .Y(n2892) );
OAI21X1TS U1729 ( .A0(n2621), .A1(n2609), .B0(n2608), .Y(n2614) );
OAI21X1TS U1730 ( .A0(n3788), .A1(n1726), .B0(n1725), .Y(n1727) );
OAI21X1TS U1731 ( .A0(n4497), .A1(n4381), .B0(n4380), .Y(n4382) );
OAI21X1TS U1732 ( .A0(n4497), .A1(n4435), .B0(n4148), .Y(n4149) );
OAI21X4TS U1733 ( .A0(n2713), .A1(n2712), .B0(n2711), .Y(n2714) );
OAI21X1TS U1734 ( .A0(n4488), .A1(n4214), .B0(n4103), .Y(n4104) );
OAI21X1TS U1735 ( .A0(n4488), .A1(n4435), .B0(n4145), .Y(n4146) );
NOR2X1TS U1736 ( .A(n2883), .B(n1810), .Y(n1812) );
NOR2X1TS U1737 ( .A(n2073), .B(n2050), .Y(n2052) );
OAI21X1TS U1738 ( .A0(n1544), .A1(n6547), .B0(n1432), .Y(n1433) );
NOR2X1TS U1739 ( .A(n2851), .B(n3782), .Y(n2853) );
OAI21X1TS U1740 ( .A0(n3788), .A1(n2851), .B0(n2850), .Y(n2852) );
CLKAND2X2TS U1741 ( .A(n2365), .B(n6598), .Y(n2366) );
OAI21X1TS U1742 ( .A0(n4488), .A1(n2327), .B0(n2373), .Y(n2374) );
OAI21X1TS U1743 ( .A0(n4497), .A1(n4092), .B0(n2027), .Y(n2028) );
OAI21X1TS U1744 ( .A0(n4488), .A1(n4092), .B0(n2019), .Y(n2020) );
OAI21X1TS U1745 ( .A0(n4488), .A1(n4550), .B0(n2338), .Y(n2339) );
OAI21X1TS U1746 ( .A0(n4497), .A1(n4269), .B0(n4268), .Y(n4270) );
OAI21X1TS U1747 ( .A0(n4488), .A1(n4269), .B0(n4264), .Y(n4265) );
OAI21X1TS U1748 ( .A0(n4488), .A1(n4323), .B0(n4124), .Y(n4125) );
OAI21X1TS U1749 ( .A0(n4497), .A1(n4323), .B0(n4127), .Y(n4128) );
OAI21X1TS U1750 ( .A0(n4497), .A1(n4496), .B0(n4495), .Y(n4498) );
OAI21X1TS U1751 ( .A0(n4488), .A1(n4496), .B0(n4487), .Y(n4489) );
OAI21X1TS U1752 ( .A0(n2621), .A1(n1488), .B0(n1487), .Y(n1493) );
OAI21X1TS U1753 ( .A0(n3788), .A1(n3787), .B0(n3786), .Y(n3789) );
AO21XLTS U1754 ( .A0(n5470), .A1(n5474), .B0(n812), .Y(n1979) );
OAI21X1TS U1755 ( .A0(n2653), .A1(n2574), .B0(n2573), .Y(n2579) );
NOR2X1TS U1756 ( .A(n3782), .B(n2761), .Y(n2763) );
NOR2X1TS U1757 ( .A(n2883), .B(n2881), .Y(n1804) );
OAI21X1TS U1758 ( .A0(n3788), .A1(n1755), .B0(n1765), .Y(n1756) );
NOR2X1TS U1759 ( .A(n3782), .B(n1755), .Y(n1757) );
AO21XLTS U1760 ( .A0(n5389), .A1(n5407), .B0(n889), .Y(n2830) );
OAI21X1TS U1761 ( .A0(n3788), .A1(n1697), .B0(n1696), .Y(n1698) );
OAI21XLTS U1762 ( .A0(n3314), .A1(n1609), .B0(n760), .Y(n3325) );
NOR2X1TS U1763 ( .A(n3782), .B(n1697), .Y(n1699) );
OAI21X1TS U1764 ( .A0(n2075), .A1(n2059), .B0(n2058), .Y(n2060) );
OAI21X1TS U1765 ( .A0(n4424), .A1(n6547), .B0(n911), .Y(n912) );
NOR2X1TS U1766 ( .A(n2073), .B(n2059), .Y(n2061) );
OAI21X1TS U1767 ( .A0(n2946), .A1(n4092), .B0(n861), .Y(n2904) );
OAI21X1TS U1768 ( .A0(n1853), .A1(n6547), .B0(n2905), .Y(n2906) );
OAI21X1TS U1769 ( .A0(n4141), .A1(n4092), .B0(n2907), .Y(n2908) );
NOR2X1TS U1770 ( .A(n2073), .B(n2074), .Y(n2077) );
OAI21X1TS U1771 ( .A0(n2621), .A1(n1479), .B0(n1478), .Y(n1482) );
OAI21X1TS U1772 ( .A0(n2621), .A1(n1517), .B0(n1516), .Y(n1522) );
OAI21X1TS U1773 ( .A0(n2621), .A1(n2620), .B0(n2619), .Y(n2626) );
AO21XLTS U1774 ( .A0(n5543), .A1(n5512), .B0(n756), .Y(n4960) );
INVX3TS U1775 ( .A(n3020), .Y(n3289) );
BUFX4TS U1776 ( .A(n5541), .Y(n5529) );
AOI222X1TS U1777 ( .A0(n3488), .A1(n6590), .B0(n3507), .B1(n3678), .C0(n3506), .C1(n3609), .Y(n1878) );
OR3X4TS U1778 ( .A(n6401), .B(underflow_flag), .C(overflow_flag), .Y(n6404)
);
NOR2X1TS U1779 ( .A(n1527), .B(n1456), .Y(n1458) );
OAI21X1TS U1780 ( .A0(n1526), .A1(n1456), .B0(n1455), .Y(n1457) );
AOI222X1TS U1781 ( .A0(n3412), .A1(n3709), .B0(n3405), .B1(n3715), .C0(n3424), .C1(n3708), .Y(n1911) );
BUFX3TS U1782 ( .A(n1615), .Y(n3313) );
OAI21X1TS U1783 ( .A0(n2685), .A1(n2684), .B0(n2683), .Y(n2686) );
OAI31X1TS U1784 ( .A0(n6585), .A1(n2723), .A2(n5629), .B0(n6541), .Y(n709)
);
OAI21X2TS U1785 ( .A0(n952), .A1(n1116), .B0(n951), .Y(n1080) );
OAI21X1TS U1786 ( .A0(n2058), .A1(n1673), .B0(n1672), .Y(n1674) );
NOR2X6TS U1787 ( .A(n6541), .B(n5636), .Y(n5637) );
OAI21X1TS U1788 ( .A0(n2485), .A1(n1713), .B0(n1712), .Y(n1714) );
AND3X4TS U1789 ( .A(n2748), .B(n774), .C(n2747), .Y(n2918) );
NOR2X1TS U1790 ( .A(n1681), .B(n1680), .Y(n1682) );
NAND2BX4TS U1791 ( .AN(n774), .B(n2748), .Y(n1544) );
OAI21X1TS U1792 ( .A0(n1997), .A1(n1996), .B0(n1995), .Y(n1998) );
NOR2X1TS U1793 ( .A(n1723), .B(n1693), .Y(n1694) );
AOI222X1TS U1794 ( .A0(n3641), .A1(n3709), .B0(n3634), .B1(n3715), .C0(n3631), .C1(n3708), .Y(n3629) );
NOR2X1TS U1795 ( .A(n2047), .B(n1671), .Y(n1672) );
NOR2X1TS U1796 ( .A(n6546), .B(n3317), .Y(n3328) );
OAI21X1TS U1797 ( .A0(n1335), .A1(n1337), .B0(n1338), .Y(n1033) );
NOR2X1TS U1798 ( .A(n1336), .B(n1337), .Y(n1034) );
INVX2TS U1799 ( .A(n5655), .Y(n5656) );
INVX3TS U1800 ( .A(n2719), .Y(n3558) );
INVX3TS U1801 ( .A(n893), .Y(n3419) );
INVX3TS U1802 ( .A(n771), .Y(n772) );
AOI21X2TS U1803 ( .A0(n940), .A1(n1134), .B0(n939), .Y(n1116) );
BUFX3TS U1804 ( .A(n916), .Y(n4424) );
NAND2BX1TS U1805 ( .AN(n2876), .B(n2878), .Y(n916) );
AND3X4TS U1806 ( .A(n2878), .B(n2877), .C(n2876), .Y(n2939) );
BUFX4TS U1807 ( .A(n2841), .Y(n3545) );
AND3X4TS U1808 ( .A(n2809), .B(n2808), .C(n2807), .Y(n4240) );
AND3X4TS U1809 ( .A(n2913), .B(n2912), .C(n2911), .Y(n2930) );
NAND2BX4TS U1810 ( .AN(n2912), .B(n2913), .Y(n2927) );
NAND2BX4TS U1811 ( .AN(n1840), .B(n2591), .Y(n1877) );
OAI21X1TS U1812 ( .A0(n2604), .A1(n2603), .B0(n2602), .Y(n2605) );
OAI21X1TS U1813 ( .A0(n2133), .A1(n2132), .B0(n2131), .Y(n2138) );
NAND2BX4TS U1814 ( .AN(n2808), .B(n2809), .Y(n2945) );
NOR2X1TS U1815 ( .A(n2885), .B(n1686), .Y(n1687) );
NAND2BX4TS U1816 ( .AN(n1703), .B(n1704), .Y(n1853) );
NAND2X1TS U1817 ( .A(n1736), .B(n1775), .Y(n1738) );
INVX3TS U1818 ( .A(n757), .Y(n3398) );
AND3X4TS U1819 ( .A(n1704), .B(n1703), .C(n1702), .Y(n1989) );
AND3X4TS U1820 ( .A(n2318), .B(n2317), .C(n2316), .Y(n2873) );
BUFX4TS U1821 ( .A(n2786), .Y(n3393) );
NAND2BX4TS U1822 ( .AN(n2961), .B(n2963), .Y(n1428) );
AND3X4TS U1823 ( .A(n2963), .B(n2962), .C(n2961), .Y(n4119) );
BUFX3TS U1824 ( .A(n5659), .Y(n6202) );
NAND2BX4TS U1825 ( .AN(n1845), .B(n5086), .Y(n1900) );
NOR2X1TS U1826 ( .A(n1957), .B(n1956), .Y(n1958) );
NOR2X1TS U1827 ( .A(n2822), .B(n2821), .Y(n2823) );
AND3X4TS U1828 ( .A(n2330), .B(n2329), .C(n6537), .Y(n2360) );
OAI21X1TS U1829 ( .A0(n1206), .A1(n1212), .B0(n1207), .Y(n985) );
NAND2BX4TS U1830 ( .AN(n6537), .B(n2330), .Y(n2327) );
NAND2BX4TS U1831 ( .AN(n2776), .B(n2777), .Y(n2785) );
OAI21X1TS U1832 ( .A0(n1199), .A1(n1195), .B0(n1200), .Y(n971) );
NOR2X1TS U1833 ( .A(n5031), .B(n5030), .Y(n5033) );
OAI21X1TS U1834 ( .A0(n1281), .A1(n1287), .B0(n1282), .Y(n1268) );
NAND2BX1TS U1835 ( .AN(n2754), .B(n2755), .Y(n2866) );
OAI21X1TS U1836 ( .A0(n1135), .A1(n1141), .B0(n1136), .Y(n939) );
NAND3X1TS U1837 ( .A(n2755), .B(n2754), .C(n2753), .Y(n2756) );
OAI21X1TS U1838 ( .A0(n1297), .A1(n1303), .B0(n1298), .Y(n1254) );
NAND2BX4TS U1839 ( .AN(n2323), .B(n2324), .Y(n2345) );
AND3X4TS U1840 ( .A(n2324), .B(n2323), .C(n2322), .Y(n2348) );
OAI21X1TS U1841 ( .A0(n1246), .A1(n1243), .B0(n1247), .Y(n995) );
NOR2X1TS U1842 ( .A(n5059), .B(n5058), .Y(n5061) );
NOR2X1TS U1843 ( .A(n2667), .B(n2666), .Y(n2668) );
NOR2X1TS U1844 ( .A(n5628), .B(n6585), .Y(n1620) );
NAND2X1TS U1845 ( .A(n1549), .B(n1548), .Y(n5024) );
NOR2X1TS U1846 ( .A(n1743), .B(n1552), .Y(n1553) );
NAND2BX4TS U1847 ( .AN(n2717), .B(n2718), .Y(n2715) );
OR2X2TS U1848 ( .A(n4573), .B(n4568), .Y(n2765) );
NOR2X2TS U1849 ( .A(n960), .B(n959), .Y(n1103) );
OAI21X1TS U1850 ( .A0(n792), .A1(Op_MX[49]), .B0(Op_MX[21]), .Y(n1499) );
OAI21X1TS U1851 ( .A0(n795), .A1(Op_MX[33]), .B0(Op_MX[5]), .Y(n1961) );
NOR2X1TS U1852 ( .A(n786), .B(Op_MX[23]), .Y(n1497) );
OAI21X1TS U1853 ( .A0(n791), .A1(Op_MX[45]), .B0(n793), .Y(n1556) );
OR2X2TS U1854 ( .A(n4607), .B(n4621), .Y(n867) );
NOR2X1TS U1855 ( .A(n2111), .B(n2110), .Y(n2113) );
NOR2X1TS U1856 ( .A(n5001), .B(n5000), .Y(n5002) );
NOR2X2TS U1857 ( .A(n958), .B(n957), .Y(n1101) );
NOR2X1TS U1858 ( .A(n2132), .B(n2134), .Y(n1446) );
OAI21X1TS U1859 ( .A0(n2134), .A1(n2131), .B0(n2135), .Y(n1445) );
INVX3TS U1860 ( .A(n6546), .Y(n3351) );
OAI21X1TS U1861 ( .A0(Op_MX[12]), .A1(Op_MX[39]), .B0(n794), .Y(n2588) );
NOR2X1TS U1862 ( .A(n794), .B(n805), .Y(n5053) );
BUFX3TS U1863 ( .A(Op_MX[26]), .Y(n5133) );
INVX1TS U1864 ( .A(n2090), .Y(n2091) );
OAI21X1TS U1865 ( .A0(n789), .A1(Op_MX[37]), .B0(Op_MX[9]), .Y(n2826) );
OAI21X1TS U1866 ( .A0(n1971), .A1(n1968), .B0(n1972), .Y(n1447) );
NOR2X1TS U1867 ( .A(n2141), .B(n2196), .Y(n2142) );
NOR2X1TS U1868 ( .A(n6059), .B(n5623), .Y(n5625) );
NOR2X1TS U1869 ( .A(n5971), .B(n6542), .Y(n5622) );
OR2X2TS U1870 ( .A(n4588), .B(n4593), .Y(n2886) );
NOR2X2TS U1871 ( .A(n956), .B(n955), .Y(n1124) );
OAI21X1TS U1872 ( .A0(n2691), .A1(n2683), .B0(n2692), .Y(n1462) );
CLKAND2X4TS U1873 ( .A(n5611), .B(n6567), .Y(n5613) );
NAND2BX4TS U1874 ( .AN(mult_x_23_n1930), .B(n2196), .Y(n2236) );
NOR2X2TS U1875 ( .A(n992), .B(n991), .Y(n1244) );
AND2X2TS U1876 ( .A(n5611), .B(FS_Module_state_reg[3]), .Y(n1634) );
OR2X2TS U1877 ( .A(n919), .B(Sgf_operation_ODD1_Q_middle[53]), .Y(n1038) );
NOR2X2TS U1878 ( .A(n994), .B(n993), .Y(n1246) );
OR2X2TS U1879 ( .A(n920), .B(Sgf_operation_ODD1_Q_middle[52]), .Y(n1041) );
NOR2X2TS U1880 ( .A(n966), .B(n965), .Y(n1092) );
OAI21X1TS U1881 ( .A0(n6584), .A1(n788), .B0(Op_MX[23]), .Y(n1496) );
INVX2TS U1882 ( .A(n2465), .Y(n1880) );
NOR2X1TS U1883 ( .A(n5087), .B(n5086), .Y(n5088) );
OR2X2TS U1884 ( .A(n3670), .B(n3674), .Y(n2709) );
NOR2X2TS U1885 ( .A(n990), .B(n989), .Y(n1070) );
NOR2X2TS U1886 ( .A(n988), .B(n987), .Y(n1075) );
XOR2X1TS U1887 ( .A(n805), .B(Op_MX[39]), .Y(n5059) );
NOR2X2TS U1888 ( .A(n984), .B(n983), .Y(n1206) );
OAI21X1TS U1889 ( .A0(Op_MX[8]), .A1(Op_MX[35]), .B0(Op_MX[7]), .Y(n2818) );
XNOR2X1TS U1890 ( .A(Op_MX[39]), .B(Op_MX[40]), .Y(n1839) );
BUFX4TS U1891 ( .A(Op_MY[35]), .Y(n3742) );
NOR2X1TS U1892 ( .A(Op_MX[9]), .B(Op_MX[36]), .Y(n2816) );
NOR2X1TS U1893 ( .A(Op_MX[3]), .B(Op_MX[30]), .Y(n2105) );
XNOR2X1TS U1894 ( .A(Op_MX[45]), .B(Op_MX[46]), .Y(n1744) );
BUFX4TS U1895 ( .A(Op_MY[39]), .Y(n3719) );
OAI21X1TS U1896 ( .A0(Op_MX[20]), .A1(Op_MX[47]), .B0(Op_MX[19]), .Y(n2663)
);
NOR2X1TS U1897 ( .A(Op_MX[19]), .B(Op_MX[46]), .Y(n4995) );
NOR2X1TS U1898 ( .A(Op_MX[21]), .B(Op_MX[48]), .Y(n2661) );
XNOR2X1TS U1899 ( .A(Op_MX[43]), .B(Op_MX[42]), .Y(n2753) );
NOR2X1TS U1900 ( .A(Op_MX[15]), .B(Op_MX[42]), .Y(n5025) );
NOR2X1TS U1901 ( .A(Op_MX[7]), .B(Op_MX[34]), .Y(n5081) );
NOR2X1TS U1902 ( .A(Op_MX[13]), .B(Op_MX[40]), .Y(n2586) );
NOR2X1TS U1903 ( .A(Op_MX[5]), .B(n6589), .Y(n1951) );
OAI21X1TS U1904 ( .A0(Op_MX[29]), .A1(Op_MX[2]), .B0(Op_MX[1]), .Y(n2107) );
NOR2X1TS U1905 ( .A(Op_MX[28]), .B(Op_MX[1]), .Y(n2123) );
OAI21X2TS U1906 ( .A0(n6023), .A1(n6019), .B0(n6020), .Y(n6011) );
OAI21X1TS U1907 ( .A0(n6091), .A1(n6093), .B0(n6094), .Y(n1320) );
OAI21X2TS U1908 ( .A0(n1124), .A1(n1130), .B0(n1125), .Y(n1098) );
OAI21X4TS U1909 ( .A0(n3828), .A1(n3824), .B0(n3825), .Y(n3823) );
OAI21X1TS U1910 ( .A0(n2005), .A1(n1677), .B0(n1676), .Y(n1678) );
AOI21X4TS U1911 ( .A0(n3041), .A1(n3039), .B0(n2999), .Y(n3037) );
OAI21X1TS U1912 ( .A0(n6546), .A1(n3407), .B0(n2858), .Y(n2859) );
AOI21X2TS U1913 ( .A0(n4709), .A1(n4707), .B0(n4683), .Y(n4705) );
OAI21X1TS U1914 ( .A0(n2741), .A1(n1558), .B0(n1557), .Y(n1561) );
AOI21X2TS U1915 ( .A0(n4718), .A1(n4716), .B0(n4682), .Y(n4714) );
OAI21X1TS U1916 ( .A0(n2530), .A1(n4804), .B0(n2531), .Y(n2518) );
OAI21X4TS U1917 ( .A0(n5963), .A1(n5960), .B0(n5961), .Y(n5952) );
NOR2X1TS U1918 ( .A(n934), .B(DP_OP_168J43_122_1342_n498), .Y(n1145) );
XNOR2X1TS U1919 ( .A(DP_OP_168J43_122_1342_n446), .B(
Sgf_operation_ODD1_Q_middle[1]), .Y(n934) );
AOI21X4TS U1920 ( .A0(n3032), .A1(n3030), .B0(n3014), .Y(n3028) );
INVX2TS U1921 ( .A(n5579), .Y(n2827) );
AOI21X4TS U1922 ( .A0(n4727), .A1(n4725), .B0(n4681), .Y(n4723) );
OAI21X4TS U1923 ( .A0(n4732), .A1(n4728), .B0(n4729), .Y(n4727) );
NOR2X1TS U1924 ( .A(n2963), .B(n2961), .Y(n2959) );
NOR2X1TS U1925 ( .A(n2913), .B(n2912), .Y(n2925) );
NOR2BX1TS U1926 ( .AN(n2912), .B(n2911), .Y(n2924) );
INVX2TS U1927 ( .A(n4068), .Y(n2075) );
INVX2TS U1928 ( .A(n2068), .Y(n2029) );
BUFX4TS U1929 ( .A(n791), .Y(n4598) );
BUFX4TS U1930 ( .A(n793), .Y(n4603) );
INVX2TS U1931 ( .A(n2074), .Y(n4071) );
OR2X2TS U1932 ( .A(n4632), .B(n4626), .Y(n2063) );
NOR2BX1TS U1933 ( .AN(n2317), .B(n2316), .Y(n2315) );
ADDHXLTS U1934 ( .A(n4102), .B(n4101), .CO(n2910), .S(n4113) );
BUFX3TS U1935 ( .A(n2867), .Y(n3473) );
NAND2X1TS U1936 ( .A(n742), .B(n4086), .Y(n4087) );
AOI21X1TS U1937 ( .A0(n4085), .A1(n4084), .B0(n4083), .Y(n4088) );
ADDHXLTS U1938 ( .A(n4144), .B(n4143), .CO(n2934), .S(n4154) );
NAND2X1TS U1939 ( .A(n868), .B(n2078), .Y(n2079) );
AOI21X1TS U1940 ( .A0(n4085), .A1(n2077), .B0(n2076), .Y(n2080) );
NOR2X1TS U1941 ( .A(n2809), .B(n2808), .Y(n2951) );
NAND2X1TS U1942 ( .A(n862), .B(n1813), .Y(n1814) );
AOI21X1TS U1943 ( .A0(n3791), .A1(n1812), .B0(n1811), .Y(n1815) );
NOR2X2TS U1944 ( .A(n1994), .B(n1683), .Y(n1940) );
NAND2X1TS U1945 ( .A(n4158), .B(n4159), .Y(n2311) );
ADDHXLTS U1946 ( .A(n4151), .B(n4150), .CO(n4155), .S(mult_x_24_n908) );
BUFX4TS U1947 ( .A(Op_MX[21]), .Y(n4583) );
BUFX4TS U1948 ( .A(n792), .Y(n4578) );
NOR2X1TS U1949 ( .A(n2545), .B(n3941), .Y(n2547) );
NAND2X1TS U1950 ( .A(n883), .B(n884), .Y(n2545) );
NAND2X1TS U1951 ( .A(n4632), .B(n4626), .Y(n2062) );
NAND2X2TS U1952 ( .A(n868), .B(n4071), .Y(n2059) );
OAI21X1TS U1953 ( .A0(n2025), .A1(n2021), .B0(n2022), .Y(n2018) );
NAND2X1TS U1954 ( .A(n4071), .B(n4070), .Y(n4072) );
AOI21X1TS U1955 ( .A0(n4085), .A1(n4069), .B0(n4068), .Y(n4073) );
ADDHXLTS U1956 ( .A(n3511), .B(n3359), .CO(n3355), .S(n3370) );
INVX4TS U1957 ( .A(n2719), .Y(n3536) );
BUFX4TS U1958 ( .A(Op_MX[9]), .Y(n4647) );
OAI21XLTS U1959 ( .A0(n831), .A1(n3475), .B0(n3338), .Y(n3339) );
OAI21XLTS U1960 ( .A0(n3314), .A1(n2785), .B0(n832), .Y(n1618) );
NAND2X1TS U1961 ( .A(n2886), .B(n1805), .Y(n1806) );
AOI21X1TS U1962 ( .A0(n3791), .A1(n1804), .B0(n1803), .Y(n1807) );
NAND2X1TS U1963 ( .A(n4563), .B(n4568), .Y(n1729) );
CLKAND2X2TS U1964 ( .A(n4485), .B(n4106), .Y(mult_x_24_n961) );
CLKAND2X2TS U1965 ( .A(n3248), .B(n3713), .Y(n1610) );
NOR2X1TS U1966 ( .A(n1704), .B(n1703), .Y(n1987) );
CLKAND2X2TS U1967 ( .A(n4164), .B(n4621), .Y(n4061) );
NOR2X1TS U1968 ( .A(n2748), .B(n774), .Y(n2916) );
CMPR42X1TS U1969 ( .A(n6598), .B(mult_x_24_n960), .C(mult_x_24_n1327), .D(
mult_x_24_n1354), .ICI(mult_x_24_n1381), .S(mult_x_24_n720), .ICO(
mult_x_24_n718), .CO(mult_x_24_n719) );
CLKAND2X2TS U1970 ( .A(n4164), .B(n4372), .Y(mult_x_24_n960) );
NOR2X2TS U1971 ( .A(n1082), .B(n974), .Y(n976) );
NAND2X2TS U1972 ( .A(n1083), .B(n972), .Y(n974) );
NAND2X1TS U1973 ( .A(n4588), .B(n4583), .Y(n2893) );
AOI21X2TS U1974 ( .A0(n1826), .A1(n1718), .B0(n1717), .Y(n1773) );
OAI21XLTS U1975 ( .A0(n3314), .A1(n1900), .B0(n854), .Y(n2183) );
NAND2X1TS U1976 ( .A(n2008), .B(n4080), .Y(n2009) );
AOI21X1TS U1977 ( .A0(n4085), .A1(n2007), .B0(n2006), .Y(n2010) );
NAND2X1TS U1978 ( .A(n741), .B(n2053), .Y(n2054) );
AOI21X1TS U1979 ( .A0(n4085), .A1(n2052), .B0(n2051), .Y(n2055) );
BUFX4TS U1980 ( .A(n790), .Y(n4609) );
OAI21XLTS U1981 ( .A0(n4575), .A1(n4424), .B0(n4394), .Y(n4395) );
NAND2X1TS U1982 ( .A(n2765), .B(n2764), .Y(n2766) );
AOI21X1TS U1983 ( .A0(n3791), .A1(n2763), .B0(n2762), .Y(n2767) );
OAI21X1TS U1984 ( .A0(n1133), .A1(n1082), .B0(n1081), .Y(n1091) );
NAND2X1TS U1985 ( .A(n966), .B(n965), .Y(n1093) );
AOI21X1TS U1986 ( .A0(n3791), .A1(n1764), .B0(n1763), .Y(n1768) );
AOI21X2TS U1987 ( .A0(n6011), .A1(n815), .B0(n1363), .Y(n5985) );
OAI21XLTS U1988 ( .A0(n4141), .A1(n4550), .B0(n2349), .Y(n2350) );
CMPR42X1TS U1989 ( .A(mult_x_24_n1554), .B(mult_x_24_n1527), .C(
mult_x_24_n853), .D(mult_x_24_n844), .ICI(mult_x_24_n849), .S(
mult_x_24_n841), .ICO(mult_x_24_n839), .CO(mult_x_24_n840) );
NOR2X1TS U1990 ( .A(n3918), .B(n3913), .Y(n2550) );
NAND2X1TS U1991 ( .A(n1393), .B(Sgf_operation_ODD1_Q_left[20]), .Y(n5910) );
INVX2TS U1992 ( .A(n5889), .Y(n1400) );
NOR2X1TS U1993 ( .A(n1404), .B(Sgf_operation_ODD1_Q_left[23]), .Y(n5878) );
NAND2X1TS U1994 ( .A(n1405), .B(Sgf_operation_ODD1_Q_left[24]), .Y(n5869) );
INVX2TS U1995 ( .A(n5848), .Y(n1412) );
NOR2X2TS U1996 ( .A(n1413), .B(Sgf_operation_ODD1_Q_left[27]), .Y(n5837) );
NOR2X2TS U1997 ( .A(n1414), .B(Sgf_operation_ODD1_Q_left[28]), .Y(n5825) );
INVX2TS U1998 ( .A(n2461), .Y(n2480) );
OAI21X2TS U1999 ( .A0(n3069), .A1(n2990), .B0(n2989), .Y(n3068) );
OAI21X1TS U2000 ( .A0(n3909), .A1(n3759), .B0(n3770), .Y(n2583) );
INVX2TS U2001 ( .A(n4737), .Y(n4799) );
INVX2TS U2002 ( .A(n2570), .Y(n2635) );
OAI21X2TS U2003 ( .A0(n3037), .A1(n3033), .B0(n3034), .Y(n3032) );
OAI21X2TS U2004 ( .A0(n3046), .A1(n3042), .B0(n3043), .Y(n3041) );
OAI21X1TS U2005 ( .A0(n1621), .A1(n1624), .B0(n1622), .Y(n2118) );
NAND2X1TS U2006 ( .A(n2826), .B(n2825), .Y(n5054) );
NAND2BXLTS U2007 ( .AN(n5098), .B(n5163), .Y(n4979) );
INVX2TS U2008 ( .A(n2134), .Y(n2136) );
INVX2TS U2009 ( .A(n1971), .Y(n1973) );
XOR2X1TS U2010 ( .A(n6589), .B(Op_MX[33]), .Y(n1957) );
AOI21X1TS U2011 ( .A0(n2166), .A1(n1963), .B0(n1962), .Y(n1970) );
NAND2X1TS U2012 ( .A(n4607), .B(n4621), .Y(n2035) );
NAND2X1TS U2013 ( .A(n2588), .B(n2587), .Y(n5052) );
NOR2X1TS U2014 ( .A(n3698), .B(n3621), .Y(n1919) );
ADDHXLTS U2015 ( .A(n3429), .B(n3337), .CO(n3333), .S(n3347) );
INVX4TS U2016 ( .A(n761), .Y(n5437) );
BUFX4TS U2017 ( .A(n1494), .Y(n5575) );
INVX4TS U2018 ( .A(n889), .Y(n5401) );
CLKAND2X2TS U2019 ( .A(n3313), .B(n3658), .Y(n3276) );
BUFX3TS U2020 ( .A(n2786), .Y(n3400) );
NOR2X2TS U2021 ( .A(n4603), .B(n4598), .Y(n1810) );
NOR2X1TS U2022 ( .A(n2603), .B(n2610), .Y(n1454) );
AOI21X1TS U2023 ( .A0(n2118), .A1(n1446), .B0(n1445), .Y(n1856) );
OAI21X1TS U2024 ( .A0(n2167), .A1(n2163), .B0(n2168), .Y(n1962) );
INVX4TS U2025 ( .A(n900), .Y(n5202) );
NOR2X1TS U2026 ( .A(n2597), .B(n4964), .Y(n4950) );
BUFX4TS U2027 ( .A(n2615), .Y(n5571) );
NOR2X1TS U2028 ( .A(n2015), .B(n4964), .Y(DP_OP_169J43_123_4229_n827) );
NAND2X1TS U2029 ( .A(n5206), .B(n2669), .Y(n2733) );
NOR2X1TS U2030 ( .A(n1860), .B(n4964), .Y(DP_OP_169J43_123_4229_n963) );
INVX4TS U2031 ( .A(n897), .Y(n5363) );
NAND2X1TS U2032 ( .A(n5308), .B(n5034), .Y(n5036) );
NAND2X1TS U2033 ( .A(n5374), .B(n5062), .Y(n5064) );
NAND2X1TS U2034 ( .A(n5273), .B(n1554), .Y(n5010) );
BUFX4TS U2035 ( .A(n1562), .Y(n5565) );
NAND2X1TS U2036 ( .A(n5441), .B(n5089), .Y(n5412) );
BUFX4TS U2037 ( .A(n2471), .Y(n5567) );
NAND2X1TS U2038 ( .A(n5405), .B(n2824), .Y(n5067) );
NAND2X1TS U2039 ( .A(n2765), .B(n858), .Y(n1695) );
NAND2X1TS U2040 ( .A(n4588), .B(n4593), .Y(n1805) );
NAND2X1TS U2041 ( .A(n864), .B(n1850), .Y(n1683) );
NAND2X2TS U2042 ( .A(n1942), .B(n862), .Y(n2881) );
NAND2X1TS U2043 ( .A(n4637), .B(n4647), .Y(n4086) );
NAND2X1TS U2044 ( .A(n2008), .B(n742), .Y(n1668) );
NAND2X1TS U2045 ( .A(n2063), .B(n741), .Y(n1673) );
NOR2X1TS U2046 ( .A(n1908), .B(n1919), .Y(n1825) );
NOR2X1TS U2047 ( .A(n2574), .B(n2575), .Y(n2649) );
NOR2X1TS U2048 ( .A(n2654), .B(n2793), .Y(n1602) );
NAND2BXLTS U2049 ( .AN(n5098), .B(n5495), .Y(n2115) );
NAND2X1TS U2050 ( .A(n4637), .B(n4644), .Y(n4080) );
INVX2TS U2051 ( .A(n4081), .Y(n2008) );
NAND2X1TS U2052 ( .A(n2063), .B(n2062), .Y(n2064) );
AOI21X1TS U2053 ( .A0(n4085), .A1(n2061), .B0(n2060), .Y(n2065) );
BUFX4TS U2054 ( .A(n1937), .Y(n5586) );
BUFX4TS U2055 ( .A(n1523), .Y(n5579) );
BUFX4TS U2056 ( .A(n1483), .Y(n5581) );
NAND2X1TS U2057 ( .A(n4626), .B(n4621), .Y(n2053) );
NAND2X1TS U2058 ( .A(n4607), .B(n4615), .Y(n2041) );
INVX2TS U2059 ( .A(n2035), .Y(n2040) );
ADDHXLTS U2060 ( .A(n4130), .B(n4129), .CO(n4134), .S(mult_x_24_n866) );
NOR2X1TS U2061 ( .A(n3731), .B(n3725), .Y(n2793) );
OAI21XLTS U2062 ( .A0(n3353), .A1(n3475), .B0(n3331), .Y(n3332) );
NAND2X1TS U2063 ( .A(n4603), .B(n4598), .Y(n1941) );
INVX2TS U2064 ( .A(n1810), .Y(n1942) );
NAND2X1TS U2065 ( .A(n4603), .B(n4609), .Y(n2000) );
NOR2X2TS U2066 ( .A(n4615), .B(n4609), .Y(n1996) );
CLKAND2X2TS U2067 ( .A(n3313), .B(n3650), .Y(n3267) );
OAI21XLTS U2068 ( .A0(n4605), .A1(n4424), .B0(n4404), .Y(n4405) );
OAI21XLTS U2069 ( .A0(n4600), .A1(n4424), .B0(n4402), .Y(n4403) );
CLKAND2X2TS U2070 ( .A(n4164), .B(n4158), .Y(mult_x_24_n962) );
OAI21XLTS U2071 ( .A0(n4595), .A1(n4424), .B0(n4400), .Y(n4401) );
BUFX4TS U2072 ( .A(Op_MY[41]), .Y(n3708) );
INVX2TS U2073 ( .A(n1910), .Y(n3711) );
INVX2TS U2074 ( .A(n1996), .Y(n1850) );
NAND2X1TS U2075 ( .A(n4615), .B(n4609), .Y(n1995) );
BUFX4TS U2076 ( .A(n1475), .Y(n5561) );
BUFX4TS U2077 ( .A(n1592), .Y(n5559) );
INVX2TS U2078 ( .A(n2656), .Y(n3745) );
CLKAND2X2TS U2079 ( .A(n3313), .B(n3748), .Y(n1616) );
OAI21XLTS U2080 ( .A0(n4580), .A1(n4424), .B0(n4396), .Y(n4397) );
CLKAND2X2TS U2081 ( .A(n4164), .B(n4545), .Y(mult_x_24_n959) );
CLKAND2X2TS U2082 ( .A(n4466), .B(n4558), .Y(n4437) );
OAI21XLTS U2083 ( .A0(n4570), .A1(n4424), .B0(n2879), .Y(n2880) );
CLKAND2X2TS U2084 ( .A(n4164), .B(n4644), .Y(n4078) );
NAND2X1TS U2085 ( .A(n4573), .B(n4568), .Y(n2764) );
CLKAND2X2TS U2086 ( .A(n3313), .B(n3725), .Y(n2706) );
INVX2TS U2087 ( .A(n2494), .Y(n3729) );
AOI21X2TS U2088 ( .A0(n1515), .A1(n1452), .B0(n1451), .Y(n1526) );
NAND2X1TS U2089 ( .A(n1511), .B(n1452), .Y(n1527) );
NAND2X1TS U2090 ( .A(n2598), .B(n1454), .Y(n1456) );
OAI21X1TS U2091 ( .A0(n1856), .A1(n1450), .B0(n1449), .Y(n1477) );
AOI21X1TS U2092 ( .A0(n1962), .A1(n1448), .B0(n1447), .Y(n1449) );
NAND2X1TS U2093 ( .A(n1963), .B(n1448), .Y(n1450) );
NAND2X1TS U2094 ( .A(n1499), .B(n1498), .Y(n2670) );
CLKXOR2X2TS U2095 ( .A(n2665), .B(n2664), .Y(n5208) );
BUFX4TS U2096 ( .A(n2100), .Y(n5551) );
INVX4TS U2097 ( .A(n5143), .Y(n5171) );
NAND2X1TS U2098 ( .A(n5032), .B(n5024), .Y(n1550) );
CLKXOR2X2TS U2099 ( .A(n4997), .B(n4996), .Y(n5008) );
INVX4TS U2100 ( .A(n5143), .Y(n5163) );
BUFX4TS U2101 ( .A(n1470), .Y(n5553) );
NAND2X1TS U2102 ( .A(n5175), .B(n1504), .Y(n2735) );
BUFX4TS U2103 ( .A(n2677), .Y(n5557) );
BUFX4TS U2104 ( .A(n2696), .Y(n5555) );
NOR2X1TS U2105 ( .A(n1883), .B(n4971), .Y(DP_OP_169J43_123_4229_n777) );
BUFX4TS U2106 ( .A(n5275), .Y(n5273) );
BUFX4TS U2107 ( .A(n2735), .Y(n5173) );
BUFX4TS U2108 ( .A(n5208), .Y(n5206) );
NAND2X1TS U2109 ( .A(n2886), .B(n860), .Y(n1688) );
NAND2X1TS U2110 ( .A(n860), .B(n2893), .Y(n2894) );
AOI21X1TS U2111 ( .A0(n3791), .A1(n2892), .B0(n2891), .Y(n2895) );
NOR2X1TS U2112 ( .A(n1781), .B(n1779), .Y(n1736) );
INVX2TS U2113 ( .A(n1752), .Y(n3611) );
NAND2X1TS U2114 ( .A(n3677), .B(n3609), .Y(n1818) );
OAI21X1TS U2115 ( .A0(n2713), .A1(n1778), .B0(n1777), .Y(n1821) );
NAND2X1TS U2116 ( .A(n938), .B(n937), .Y(n1136) );
NOR2X2TS U2117 ( .A(n948), .B(n947), .Y(n1119) );
NOR2X2TS U2118 ( .A(n946), .B(n945), .Y(n1171) );
NAND2X1TS U2119 ( .A(n948), .B(n947), .Y(n1120) );
AOI21X1TS U2120 ( .A0(n1163), .A1(n1118), .B0(n1117), .Y(n1175) );
NAND2X1TS U2121 ( .A(n960), .B(n959), .Y(n1104) );
NAND2X1TS U2122 ( .A(n994), .B(n993), .Y(n1247) );
NAND2X1TS U2123 ( .A(n1006), .B(n1005), .Y(n1257) );
NOR2X2TS U2124 ( .A(n1006), .B(n1005), .Y(n1256) );
OAI21X1TS U2125 ( .A0(n1133), .A1(n1100), .B0(n1099), .Y(n1111) );
AOI21X1TS U2126 ( .A0(n1079), .A1(n1066), .B0(n1065), .Y(n1245) );
NOR2X2TS U2127 ( .A(n1012), .B(n1011), .Y(n1281) );
NAND2X1TS U2128 ( .A(n1012), .B(n1011), .Y(n1282) );
AOI21X1TS U2129 ( .A0(n1253), .A1(n1064), .B0(n1063), .Y(n1069) );
OAI21X1TS U2130 ( .A0(n1060), .A1(n1024), .B0(n1023), .Y(n1261) );
NAND2X1TS U2131 ( .A(n1022), .B(n1252), .Y(n1024) );
AOI21X1TS U2132 ( .A0(n1251), .A1(n1022), .B0(n1021), .Y(n1023) );
NOR2X1TS U2133 ( .A(n1020), .B(n1264), .Y(n1022) );
AOI21X1TS U2134 ( .A0(n905), .A1(n1030), .B0(n1029), .Y(n1335) );
INVX2TS U2135 ( .A(n1345), .Y(n1029) );
INVX2TS U2136 ( .A(n1342), .Y(n1030) );
NAND2X1TS U2137 ( .A(n1262), .B(n905), .Y(n1336) );
NAND2X1TS U2138 ( .A(n1026), .B(n1025), .Y(n1342) );
NOR2X2TS U2139 ( .A(n1016), .B(n1015), .Y(n1270) );
NOR2X2TS U2140 ( .A(n1014), .B(n1013), .Y(n1275) );
NAND2X1TS U2141 ( .A(n1014), .B(n1013), .Y(n1276) );
NAND2X1TS U2142 ( .A(n1016), .B(n1015), .Y(n1271) );
NAND2X1TS U2143 ( .A(n1010), .B(n1009), .Y(n1287) );
NOR2X2TS U2144 ( .A(n1010), .B(n1009), .Y(n1286) );
AOI21X1TS U2145 ( .A0(n1306), .A1(n1255), .B0(n1254), .Y(n1295) );
NOR2X2TS U2146 ( .A(n1004), .B(n1003), .Y(n1291) );
NAND2X1TS U2147 ( .A(n1004), .B(n1003), .Y(n1292) );
INVX2TS U2148 ( .A(n2233), .Y(n3666) );
NAND2X1TS U2149 ( .A(n4485), .B(n4158), .Y(n2310) );
NAND2X1TS U2150 ( .A(n755), .B(n2030), .Y(n2031) );
AOI21X1TS U2151 ( .A0(n4085), .A1(n740), .B0(n2029), .Y(n2032) );
INVX2TS U2152 ( .A(n2070), .Y(n4551) );
INVX2TS U2153 ( .A(n2026), .Y(n4497) );
NAND2X2TS U2154 ( .A(n5545), .B(n2143), .Y(n5541) );
BUFX4TS U2155 ( .A(n5476), .Y(n5510) );
BUFX3TS U2156 ( .A(n5541), .Y(n5543) );
BUFX4TS U2157 ( .A(n5474), .Y(n5472) );
BUFX4TS U2158 ( .A(n5095), .Y(n5470) );
BUFX4TS U2159 ( .A(n5512), .Y(n5545) );
INVX2TS U2160 ( .A(n2580), .Y(n3755) );
BUFX3TS U2161 ( .A(n2221), .Y(n3636) );
AOI21X1TS U2162 ( .A0(n3791), .A1(n1728), .B0(n1727), .Y(n1731) );
NOR2X1TS U2163 ( .A(n2976), .B(n2972), .Y(n2979) );
INVX2TS U2164 ( .A(mult_x_23_n544), .Y(n3254) );
CLKAND2X2TS U2165 ( .A(n4106), .B(n4609), .Y(mult_x_24_n947) );
CMPR42X1TS U2166 ( .A(mult_x_24_n1350), .B(mult_x_24_n1485), .C(
mult_x_24_n1377), .D(mult_x_24_n1431), .ICI(mult_x_24_n679), .S(
mult_x_24_n669), .ICO(mult_x_24_n667), .CO(mult_x_24_n668) );
CMPR42X1TS U2167 ( .A(mult_x_23_n1255), .B(mult_x_23_n1203), .C(
mult_x_23_n1177), .D(mult_x_23_n591), .ICI(mult_x_23_n1229), .S(
mult_x_23_n589), .ICO(mult_x_23_n587), .CO(mult_x_23_n588) );
OAI21X1TS U2168 ( .A0(n1115), .A1(n1086), .B0(n1085), .Y(n1198) );
AOI21X1TS U2169 ( .A0(n1253), .A1(n1205), .B0(n1204), .Y(n1215) );
NOR2X2TS U2170 ( .A(n982), .B(n981), .Y(n1211) );
NAND2X1TS U2171 ( .A(n1524), .B(n6583), .Y(n1525) );
BUFX4TS U2172 ( .A(n2743), .Y(n5549) );
CLKXOR2X2TS U2173 ( .A(n1524), .B(n6583), .Y(n5143) );
BUFX4TS U2174 ( .A(n788), .Y(n4568) );
AOI21X1TS U2175 ( .A0(n3791), .A1(n1699), .B0(n1698), .Y(n1701) );
AOI21X1TS U2176 ( .A0(n3791), .A1(n3790), .B0(n3789), .Y(n3792) );
NAND2X1TS U2177 ( .A(n859), .B(n1758), .Y(n1759) );
AOI21X1TS U2178 ( .A0(n3791), .A1(n1757), .B0(n1756), .Y(n1760) );
NAND2X1TS U2179 ( .A(n836), .B(n6163), .Y(n6086) );
XNOR2X1TS U2180 ( .A(n920), .B(Sgf_operation_ODD1_Q_middle[52]), .Y(n1408)
);
NAND2X1TS U2181 ( .A(n6129), .B(n5624), .Y(n6058) );
OR2X1TS U2182 ( .A(n3360), .B(n3312), .Y(n1536) );
OAI21XLTS U2183 ( .A0(n2946), .A1(n4550), .B0(n842), .Y(n2344) );
OAI21XLTS U2184 ( .A0(n3353), .A1(n3665), .B0(n2227), .Y(n2228) );
CMPR42X1TS U2185 ( .A(mult_x_24_n908), .B(mult_x_24_n1508), .C(
mult_x_24_n1535), .D(mult_x_24_n1562), .ICI(mult_x_24_n909), .S(
mult_x_24_n906), .ICO(mult_x_24_n904), .CO(mult_x_24_n905) );
AOI21X1TS U2186 ( .A0(n2404), .A1(n2403), .B0(n2402), .Y(n4910) );
OAI21X1TS U2187 ( .A0(n2300), .A1(n3204), .B0(n2299), .Y(n2412) );
CMPR42X1TS U2188 ( .A(DP_OP_169J43_123_4229_n1237), .B(
DP_OP_169J43_123_4229_n1231), .C(DP_OP_169J43_123_4229_n1238), .D(
DP_OP_169J43_123_4229_n1228), .ICI(DP_OP_169J43_123_4229_n1234), .S(
DP_OP_169J43_123_4229_n1225), .ICO(DP_OP_169J43_123_4229_n1223), .CO(
DP_OP_169J43_123_4229_n1224) );
AOI21X2TS U2189 ( .A0(n2432), .A1(n2431), .B0(n2430), .Y(n2969) );
CMPR42X1TS U2190 ( .A(mult_x_24_n1553), .B(mult_x_24_n1526), .C(
mult_x_24_n843), .D(mult_x_24_n834), .ICI(mult_x_24_n839), .S(
mult_x_24_n831), .ICO(mult_x_24_n829), .CO(mult_x_24_n830) );
OAI21X2TS U2191 ( .A0(n3126), .A1(n2443), .B0(n2442), .Y(n2985) );
NOR2X1TS U2192 ( .A(n3134), .B(n3129), .Y(n2441) );
CMPR42X1TS U2193 ( .A(DP_OP_169J43_123_4229_n1191), .B(
DP_OP_169J43_123_4229_n1178), .C(DP_OP_169J43_123_4229_n1188), .D(
DP_OP_169J43_123_4229_n1175), .ICI(DP_OP_169J43_123_4229_n1184), .S(
DP_OP_169J43_123_4229_n1172), .ICO(DP_OP_169J43_123_4229_n1170), .CO(
DP_OP_169J43_123_4229_n1171) );
CMPR42X1TS U2194 ( .A(DP_OP_169J43_123_4229_n1125), .B(
DP_OP_169J43_123_4229_n1113), .C(DP_OP_169J43_123_4229_n1126), .D(
DP_OP_169J43_123_4229_n1110), .ICI(DP_OP_169J43_123_4229_n1122), .S(
DP_OP_169J43_123_4229_n1107), .ICO(DP_OP_169J43_123_4229_n1105), .CO(
DP_OP_169J43_123_4229_n1106) );
CMPR42X1TS U2195 ( .A(DP_OP_169J43_123_4229_n1150), .B(
DP_OP_169J43_123_4229_n1147), .C(DP_OP_169J43_123_4229_n1158), .D(
DP_OP_169J43_123_4229_n1154), .ICI(DP_OP_169J43_123_4229_n1144), .S(
DP_OP_169J43_123_4229_n1141), .ICO(DP_OP_169J43_123_4229_n1139), .CO(
DP_OP_169J43_123_4229_n1140) );
CMPR42X1TS U2196 ( .A(DP_OP_169J43_123_4229_n1142), .B(
DP_OP_169J43_123_4229_n1130), .C(DP_OP_169J43_123_4229_n1143), .D(
DP_OP_169J43_123_4229_n1139), .ICI(DP_OP_169J43_123_4229_n1127), .S(
DP_OP_169J43_123_4229_n1124), .ICO(DP_OP_169J43_123_4229_n1122), .CO(
DP_OP_169J43_123_4229_n1123) );
OAI21X2TS U2197 ( .A0(n4859), .A1(n2509), .B0(n2508), .Y(n4842) );
NAND2X1TS U2198 ( .A(n4861), .B(n4863), .Y(n2509) );
NAND2X1TS U2199 ( .A(n885), .B(n3954), .Y(n3941) );
AOI21X1TS U2200 ( .A0(n2451), .A1(n2445), .B0(n2444), .Y(n2982) );
CMPR42X1TS U2201 ( .A(mult_x_24_n764), .B(mult_x_24_n753), .C(mult_x_24_n761), .D(mult_x_24_n750), .ICI(mult_x_24_n757), .S(mult_x_24_n747), .ICO(
mult_x_24_n745), .CO(mult_x_24_n746) );
CMPR42X1TS U2202 ( .A(mult_x_24_n669), .B(mult_x_24_n680), .C(mult_x_24_n666), .D(mult_x_24_n677), .ICI(mult_x_24_n673), .S(mult_x_24_n663), .ICO(
mult_x_24_n661), .CO(mult_x_24_n662) );
AOI21X2TS U2203 ( .A0(n3773), .A1(n3772), .B0(n3771), .Y(n3860) );
NOR2X1TS U2204 ( .A(DP_OP_169J43_123_4229_n967), .B(
DP_OP_169J43_123_4229_n986), .Y(n2528) );
NOR2X1TS U2205 ( .A(DP_OP_169J43_123_4229_n861), .B(
DP_OP_169J43_123_4229_n875), .Y(n4789) );
NOR2X1TS U2206 ( .A(mult_x_24_n687), .B(mult_x_24_n698), .Y(n2563) );
CMPR42X1TS U2207 ( .A(mult_x_24_n692), .B(mult_x_24_n681), .C(mult_x_24_n678), .D(mult_x_24_n689), .ICI(mult_x_24_n685), .S(mult_x_24_n675), .ICO(
mult_x_24_n673), .CO(mult_x_24_n674) );
CMPR42X1TS U2208 ( .A(mult_x_24_n668), .B(mult_x_24_n658), .C(mult_x_24_n665), .D(mult_x_24_n655), .ICI(mult_x_24_n661), .S(mult_x_24_n652), .ICO(
mult_x_24_n650), .CO(mult_x_24_n651) );
NAND2X1TS U2209 ( .A(n2519), .B(n2524), .Y(n4654) );
CMPR42X1TS U2210 ( .A(DP_OP_169J43_123_4229_n952), .B(
DP_OP_169J43_123_4229_n935), .C(DP_OP_169J43_123_4229_n949), .D(
DP_OP_169J43_123_4229_n932), .ICI(DP_OP_169J43_123_4229_n945), .S(
DP_OP_169J43_123_4229_n929), .ICO(DP_OP_169J43_123_4229_n927), .CO(
DP_OP_169J43_123_4229_n928) );
AOI21X2TS U2211 ( .A0(n1184), .A1(n6299), .B0(n1183), .Y(n6315) );
NOR2X1TS U2212 ( .A(n6304), .B(n1182), .Y(n1184) );
OAI21X1TS U2213 ( .A0(n6303), .A1(n1182), .B0(n1181), .Y(n1183) );
NAND2X1TS U2214 ( .A(n827), .B(n828), .Y(n1182) );
NAND2X1TS U2215 ( .A(n826), .B(n1233), .Y(n1235) );
AOI21X1TS U2216 ( .A0(n6215), .A1(n1233), .B0(n1232), .Y(n1234) );
NOR2X1TS U2217 ( .A(n6233), .B(n6229), .Y(n1233) );
BUFX4TS U2218 ( .A(n2732), .Y(n5547) );
CMPR42X1TS U2219 ( .A(DP_OP_169J43_123_4229_n811), .B(
DP_OP_169J43_123_4229_n818), .C(DP_OP_169J43_123_4229_n808), .D(
DP_OP_169J43_123_4229_n819), .ICI(DP_OP_169J43_123_4229_n815), .S(
DP_OP_169J43_123_4229_n805), .ICO(DP_OP_169J43_123_4229_n803), .CO(
DP_OP_169J43_123_4229_n804) );
CMPR42X1TS U2220 ( .A(DP_OP_169J43_123_4229_n823), .B(
DP_OP_169J43_123_4229_n832), .C(DP_OP_169J43_123_4229_n833), .D(
DP_OP_169J43_123_4229_n820), .ICI(DP_OP_169J43_123_4229_n829), .S(
DP_OP_169J43_123_4229_n817), .ICO(DP_OP_169J43_123_4229_n815), .CO(
DP_OP_169J43_123_4229_n816) );
NOR2X1TS U2221 ( .A(DP_OP_169J43_123_4229_n893), .B(
DP_OP_169J43_123_4229_n909), .Y(n4652) );
CMPR42X1TS U2222 ( .A(DP_OP_169J43_123_4229_n1089), .B(
DP_OP_169J43_123_4229_n1076), .C(DP_OP_169J43_123_4229_n1090), .D(
DP_OP_169J43_123_4229_n1073), .ICI(DP_OP_169J43_123_4229_n1086), .S(
DP_OP_169J43_123_4229_n1070), .ICO(DP_OP_169J43_123_4229_n1068), .CO(
DP_OP_169J43_123_4229_n1069) );
CMPR42X1TS U2223 ( .A(DP_OP_169J43_123_4229_n1039), .B(
DP_OP_169J43_123_4229_n1036), .C(DP_OP_169J43_123_4229_n1052), .D(
DP_OP_169J43_123_4229_n1033), .ICI(DP_OP_169J43_123_4229_n1048), .S(
DP_OP_169J43_123_4229_n1030), .ICO(DP_OP_169J43_123_4229_n1028), .CO(
DP_OP_169J43_123_4229_n1029) );
CMPR42X1TS U2224 ( .A(DP_OP_169J43_123_4229_n1059), .B(
DP_OP_169J43_123_4229_n1056), .C(DP_OP_169J43_123_4229_n1072), .D(
DP_OP_169J43_123_4229_n1053), .ICI(DP_OP_169J43_123_4229_n1068), .S(
DP_OP_169J43_123_4229_n1050), .ICO(DP_OP_169J43_123_4229_n1048), .CO(
DP_OP_169J43_123_4229_n1049) );
NOR2X1TS U2225 ( .A(n4833), .B(n4831), .Y(n4820) );
BUFX3TS U2226 ( .A(n2854), .Y(n4385) );
AO21XLTS U2227 ( .A0(n880), .A1(n6277), .B0(n1154), .Y(n759) );
NOR2X1TS U2228 ( .A(n1377), .B(Sgf_operation_ODD1_Q_left[15]), .Y(n5960) );
NAND2X1TS U2229 ( .A(n1377), .B(Sgf_operation_ODD1_Q_left[15]), .Y(n5961) );
NAND2X1TS U2230 ( .A(n1381), .B(Sgf_operation_ODD1_Q_left[16]), .Y(n5951) );
NOR2X1TS U2231 ( .A(n1386), .B(Sgf_operation_ODD1_Q_left[17]), .Y(n5939) );
NAND2X1TS U2232 ( .A(n1386), .B(Sgf_operation_ODD1_Q_left[17]), .Y(n5940) );
NAND2X1TS U2233 ( .A(n1387), .B(Sgf_operation_ODD1_Q_left[18]), .Y(n5930) );
NOR2X1TS U2234 ( .A(n1392), .B(Sgf_operation_ODD1_Q_left[19]), .Y(n5919) );
NAND2X1TS U2235 ( .A(n1392), .B(Sgf_operation_ODD1_Q_left[19]), .Y(n5920) );
INVX2TS U2236 ( .A(n5910), .Y(n1394) );
NOR2X1TS U2237 ( .A(n1398), .B(Sgf_operation_ODD1_Q_left[21]), .Y(n5899) );
NAND2X1TS U2238 ( .A(n1398), .B(Sgf_operation_ODD1_Q_left[21]), .Y(n5900) );
NAND2X1TS U2239 ( .A(n1399), .B(Sgf_operation_ODD1_Q_left[22]), .Y(n5889) );
NAND2X1TS U2240 ( .A(n1404), .B(Sgf_operation_ODD1_Q_left[23]), .Y(n5879) );
INVX2TS U2241 ( .A(n5869), .Y(n1406) );
NOR2X1TS U2242 ( .A(n1410), .B(Sgf_operation_ODD1_Q_left[25]), .Y(n5858) );
NAND2X1TS U2243 ( .A(n1410), .B(Sgf_operation_ODD1_Q_left[25]), .Y(n5859) );
INVX2TS U2244 ( .A(n5816), .Y(n5828) );
AOI21X1TS U2245 ( .A0(n834), .A1(n1239), .B0(n1238), .Y(n6195) );
NAND2X1TS U2246 ( .A(n834), .B(n6240), .Y(n6196) );
NAND2X1TS U2247 ( .A(n1240), .B(Sgf_operation_ODD1_Q_right[49]), .Y(n6198)
);
AOI21X2TS U2248 ( .A0(n813), .A1(n6131), .B0(n1315), .Y(n6118) );
NAND2X1TS U2249 ( .A(n1316), .B(Sgf_operation_ODD1_Q_left[3]), .Y(n6121) );
NOR2X1TS U2250 ( .A(n1236), .B(Sgf_operation_ODD1_Q_right[47]), .Y(n6190) );
OR2X1TS U2251 ( .A(n1237), .B(Sgf_operation_ODD1_Q_right[48]), .Y(n834) );
OAI21X1TS U2252 ( .A0(n6287), .A1(n6283), .B0(n6284), .Y(n6291) );
AOI21X1TS U2253 ( .A0(n825), .A1(n6048), .B0(n1351), .Y(n6033) );
NAND2X1TS U2254 ( .A(n825), .B(n6047), .Y(n6034) );
NAND2X1TS U2255 ( .A(n1348), .B(Sgf_operation_ODD1_Q_left[6]), .Y(n6074) );
NAND2X1TS U2256 ( .A(n1319), .B(Sgf_operation_ODD1_Q_left[5]), .Y(n6094) );
NAND2X1TS U2257 ( .A(n1372), .B(Sgf_operation_ODD1_Q_left[14]), .Y(n5975) );
AOI21X1TS U2258 ( .A0(n816), .A1(n5986), .B0(n1366), .Y(n1367) );
NAND2X1TS U2259 ( .A(n1365), .B(Sgf_operation_ODD1_Q_left[13]), .Y(n5987) );
NAND2X1TS U2260 ( .A(n1364), .B(Sgf_operation_ODD1_Q_left[12]), .Y(n5998) );
OR2X1TS U2261 ( .A(n1364), .B(Sgf_operation_ODD1_Q_left[12]), .Y(n824) );
OR2X1TS U2262 ( .A(n2371), .B(n2370), .Y(n4040) );
NOR2X1TS U2263 ( .A(n754), .B(n3241), .Y(n3239) );
OR2X1TS U2264 ( .A(n2250), .B(n2249), .Y(n3238) );
OR2X1TS U2265 ( .A(mult_x_23_n826), .B(mult_x_23_n830), .Y(n3207) );
NAND2X1TS U2266 ( .A(n903), .B(n3163), .Y(n3152) );
NAND2X1TS U2267 ( .A(mult_x_23_n669), .B(mult_x_23_n679), .Y(n3122) );
INVX2TS U2268 ( .A(n2985), .Y(n3125) );
NOR2X1TS U2269 ( .A(n4868), .B(n4866), .Y(n4861) );
INVX2TS U2270 ( .A(n3773), .Y(n3909) );
NAND2X1TS U2271 ( .A(DP_OP_169J43_123_4229_n1088), .B(
DP_OP_169J43_123_4229_n1106), .Y(n4838) );
NAND2X1TS U2272 ( .A(n4852), .B(n4856), .Y(n4844) );
OAI21X1TS U2273 ( .A0(n3125), .A1(n2974), .B0(n2982), .Y(n2461) );
NOR2X1TS U2274 ( .A(n3076), .B(n3080), .Y(n3071) );
INVX2TS U2275 ( .A(n3069), .Y(n3107) );
OAI21X1TS U2276 ( .A0(n3064), .A1(n3060), .B0(n3061), .Y(n3059) );
NAND2X1TS U2277 ( .A(DP_OP_169J43_123_4229_n861), .B(
DP_OP_169J43_123_4229_n875), .Y(n4796) );
INVX2TS U2278 ( .A(n4665), .Y(n4817) );
OAI21X1TS U2279 ( .A0(n2480), .A1(n2479), .B0(n2478), .Y(n3111) );
OAI21X1TS U2280 ( .A0(n2647), .A1(n2646), .B0(n2645), .Y(n3892) );
NAND2X1TS U2281 ( .A(n1227), .B(Sgf_operation_ODD1_Q_right[43]), .Y(n6262)
);
NOR2X2TS U2282 ( .A(n1227), .B(Sgf_operation_ODD1_Q_right[43]), .Y(n6261) );
NAND2X1TS U2283 ( .A(n1228), .B(Sgf_operation_ODD1_Q_right[44]), .Y(n6217)
);
NAND2X1TS U2284 ( .A(n1236), .B(Sgf_operation_ODD1_Q_right[47]), .Y(n6239)
);
NAND2X1TS U2285 ( .A(n1308), .B(Sgf_operation_ODD1_Q_right[51]), .Y(n6209)
);
NAND2X1TS U2286 ( .A(n1309), .B(Sgf_operation_ODD1_Q_right[52]), .Y(n6174)
);
NOR2X1TS U2287 ( .A(n4754), .B(n4673), .Y(n4749) );
AOI21X1TS U2288 ( .A0(n4776), .A1(n4757), .B0(n4756), .Y(n4766) );
AOI21X1TS U2289 ( .A0(n4799), .A1(n4747), .B0(n4746), .Y(n4768) );
INVX2TS U2290 ( .A(n4768), .Y(n4776) );
OAI21X1TS U2291 ( .A0(n2635), .A1(n2634), .B0(n2633), .Y(n4803) );
NAND2X1TS U2292 ( .A(DP_OP_169J43_123_4229_n1050), .B(
DP_OP_169J43_123_4229_n1069), .Y(n4827) );
NAND2BXLTS U2293 ( .AN(n5475), .B(n5296), .Y(n5035) );
NAND2BXLTS U2294 ( .AN(n5098), .B(n5263), .Y(n5009) );
INVX2TS U2295 ( .A(n2603), .Y(n1507) );
INVX2TS U2296 ( .A(n1528), .Y(n1486) );
INVX2TS U2297 ( .A(n5059), .Y(n1840) );
INVX2TS U2298 ( .A(n2610), .Y(n2612) );
INVX2TS U2299 ( .A(n2466), .Y(n2468) );
INVX2TS U2300 ( .A(n1939), .Y(n2890) );
NOR2X1TS U2301 ( .A(n3725), .B(n3719), .Y(n2487) );
NOR2X1TS U2302 ( .A(n3719), .B(n3713), .Y(n2489) );
XOR2X1TS U2303 ( .A(n807), .B(Op_MX[45]), .Y(n1743) );
NOR2X1TS U2304 ( .A(n1211), .B(n1206), .Y(n986) );
NOR2X1TS U2305 ( .A(n1256), .B(n1291), .Y(n1008) );
NOR2X1TS U2306 ( .A(n1275), .B(n1270), .Y(n1018) );
NAND2X1TS U2307 ( .A(n1961), .B(n1960), .Y(n5082) );
NAND2X1TS U2308 ( .A(n4647), .B(n4639), .Y(n4070) );
NOR2X1TS U2309 ( .A(n3582), .B(n3658), .Y(n2200) );
NOR2X1TS U2310 ( .A(n3658), .B(n3654), .Y(n2202) );
INVX2TS U2311 ( .A(n2167), .Y(n2169) );
INVX2TS U2312 ( .A(n2163), .Y(n2164) );
INVX2TS U2313 ( .A(n1856), .Y(n2166) );
NOR2X2TS U2314 ( .A(n4637), .B(n4644), .Y(n4081) );
NAND2X1TS U2315 ( .A(n2818), .B(n2817), .Y(n5091) );
INVX2TS U2316 ( .A(n2622), .Y(n2624) );
INVX2TS U2317 ( .A(n1512), .Y(n1513) );
INVX2TS U2318 ( .A(n1518), .Y(n1520) );
INVX2TS U2319 ( .A(n1477), .Y(n2621) );
NOR2X2TS U2320 ( .A(n4647), .B(n4639), .Y(n2074) );
NAND2X1TS U2321 ( .A(n4632), .B(n4639), .Y(n2078) );
INVX4TS U2322 ( .A(n876), .Y(n5335) );
INVX4TS U2323 ( .A(n897), .Y(n5370) );
NAND2BXLTS U2324 ( .AN(n5098), .B(n5195), .Y(n4981) );
ADDHXLTS U2325 ( .A(n5013), .B(n5012), .CO(DP_OP_169J43_123_4229_n1168), .S(
n5020) );
NAND2BXLTS U2326 ( .AN(n5098), .B(n5231), .Y(n5006) );
OAI21XLTS U2327 ( .A0(n4629), .A1(n4381), .B0(n4358), .Y(n4359) );
CLKAND2X2TS U2328 ( .A(n3313), .B(n3360), .Y(n3298) );
INVX2TS U2329 ( .A(n1957), .Y(n1845) );
CLKAND2X2TS U2330 ( .A(n3313), .B(n3587), .Y(n3288) );
CLKAND2X2TS U2331 ( .A(n3313), .B(n3582), .Y(n3282) );
CLKAND2X2TS U2332 ( .A(n3313), .B(n3654), .Y(n3270) );
INVX2TS U2333 ( .A(n1582), .Y(n1583) );
CLKAND2X2TS U2334 ( .A(n4164), .B(n4536), .Y(n4067) );
XNOR2X1TS U2335 ( .A(Op_MX[37]), .B(Op_MX[36]), .Y(n2716) );
NOR2X1TS U2336 ( .A(n3621), .B(n3692), .Y(n1829) );
NOR2X1TS U2337 ( .A(n3692), .B(n3687), .Y(n1831) );
CLKAND2X2TS U2338 ( .A(n3313), .B(n3731), .Y(n3262) );
OAI21X1TS U2339 ( .A0(n1119), .A1(n1172), .B0(n1120), .Y(n949) );
NOR2X1TS U2340 ( .A(n1101), .B(n1103), .Y(n962) );
NOR2X2TS U2341 ( .A(n1087), .B(n1199), .Y(n972) );
AOI21X1TS U2342 ( .A0(n1084), .A1(n972), .B0(n971), .Y(n973) );
NOR2X1TS U2343 ( .A(n1244), .B(n1246), .Y(n996) );
INVX2TS U2344 ( .A(n2727), .Y(n2097) );
INVX2TS U2345 ( .A(n1565), .Y(n1566) );
INVX2TS U2346 ( .A(n1571), .Y(n1573) );
INVX2TS U2347 ( .A(n2684), .Y(n2674) );
INVX4TS U2348 ( .A(n762), .Y(n5238) );
NAND2X1TS U2349 ( .A(n2663), .B(n2662), .Y(n5005) );
NAND2X1TS U2350 ( .A(n1556), .B(n1555), .Y(n4996) );
NAND2X1TS U2351 ( .A(n2596), .B(n2595), .Y(n5027) );
INVX4TS U2352 ( .A(n811), .Y(n5304) );
NAND2X1TS U2353 ( .A(n5242), .B(n5003), .Y(n5213) );
INVX4TS U2354 ( .A(n5008), .Y(n5269) );
OAI21XLTS U2355 ( .A0(n4684), .A1(n4971), .B0(n4969), .Y(n4975) );
NAND2BXLTS U2356 ( .AN(n5098), .B(n5133), .Y(n4969) );
ADDHXLTS U2357 ( .A(n4984), .B(n4983), .CO(DP_OP_169J43_123_4229_n1103), .S(
n4991) );
INVX4TS U2358 ( .A(n761), .Y(n5430) );
NAND2X1TS U2359 ( .A(n4598), .B(n4593), .Y(n1813) );
NAND2X1TS U2360 ( .A(n740), .B(n755), .Y(n4079) );
NAND2X1TS U2361 ( .A(n743), .B(n865), .Y(n1661) );
CLKAND2X2TS U2362 ( .A(n4106), .B(n4626), .Y(n4057) );
INVX2TS U2363 ( .A(n1940), .Y(n2883) );
NAND2X1TS U2364 ( .A(n2882), .B(n2886), .Y(n2889) );
NOR2X1TS U2365 ( .A(n3713), .B(n3708), .Y(n1707) );
NOR2X1TS U2366 ( .A(n3708), .B(n3703), .Y(n1865) );
NAND2X1TS U2367 ( .A(n3725), .B(n3719), .Y(n2702) );
NAND2X1TS U2368 ( .A(n3713), .B(n3708), .Y(n1861) );
NOR2X2TS U2369 ( .A(n2487), .B(n2489), .Y(n1708) );
NOR2X1TS U2370 ( .A(n2200), .B(n2202), .Y(n2230) );
AOI21X1TS U2371 ( .A0(n872), .A1(n1595), .B0(n1594), .Y(n2199) );
INVX2TS U2372 ( .A(n1743), .Y(n1745) );
NOR2X1TS U2373 ( .A(n3687), .B(n3682), .Y(n1734) );
NOR2X1TS U2374 ( .A(n3682), .B(n3677), .Y(n1795) );
NOR2X1TS U2375 ( .A(n3677), .B(n3609), .Y(n1779) );
OR2X1TS U2376 ( .A(DP_OP_168J43_122_1342_n446), .B(
Sgf_operation_ODD1_Q_middle[1]), .Y(n935) );
ADDFX2TS U2377 ( .A(Sgf_operation_ODD1_Q_middle[2]), .B(
DP_OP_168J43_122_1342_n445), .CI(DP_OP_168J43_122_1342_n497), .CO(n937), .S(n936) );
NOR2X1TS U2378 ( .A(n1157), .B(n1164), .Y(n1118) );
NOR2X1TS U2379 ( .A(n1129), .B(n1124), .Y(n1097) );
NOR2X1TS U2380 ( .A(n1075), .B(n1070), .Y(n1066) );
OAI21X1TS U2381 ( .A0(n1070), .A1(n1076), .B0(n1071), .Y(n1065) );
AOI21X1TS U2382 ( .A0(n1008), .A1(n1254), .B0(n1007), .Y(n1265) );
AOI21X1TS U2383 ( .A0(n1204), .A1(n986), .B0(n985), .Y(n1062) );
NAND2X1TS U2384 ( .A(n1205), .B(n986), .Y(n1061) );
NAND2X1TS U2385 ( .A(n1269), .B(n1018), .Y(n1020) );
NAND2X1TS U2386 ( .A(n1008), .B(n1255), .Y(n1264) );
OAI21X1TS U2387 ( .A0(n1265), .A1(n1020), .B0(n1019), .Y(n1021) );
AOI21X1TS U2388 ( .A0(n1268), .A1(n1018), .B0(n1017), .Y(n1019) );
NAND2X1TS U2389 ( .A(n3587), .B(n3582), .Y(n2216) );
NAND2X1TS U2390 ( .A(n4536), .B(n4644), .Y(n2030) );
NAND2X1TS U2391 ( .A(n2107), .B(n2106), .Y(n2145) );
NAND2X1TS U2392 ( .A(n4540), .B(n4536), .Y(n2068) );
NOR2X2TS U2393 ( .A(n4485), .B(n4372), .Y(n2021) );
NAND2X1TS U2394 ( .A(n4485), .B(n4372), .Y(n2022) );
NAND2X1TS U2395 ( .A(n3582), .B(n3658), .Y(n2252) );
NAND2X1TS U2396 ( .A(n1953), .B(n1952), .Y(n2104) );
NAND2X1TS U2397 ( .A(n4372), .B(n4545), .Y(n2016) );
NAND2X1TS U2398 ( .A(n4540), .B(n4545), .Y(n1984) );
BUFX4TS U2399 ( .A(n2121), .Y(n5505) );
INVX2TS U2400 ( .A(n2132), .Y(n2119) );
NAND2BXLTS U2401 ( .AN(n5098), .B(n5461), .Y(n5096) );
BUFX4TS U2402 ( .A(n2139), .Y(n5502) );
NAND2X1TS U2403 ( .A(n3658), .B(n3654), .Y(n2203) );
NAND2BXLTS U2404 ( .AN(n5098), .B(n5437), .Y(n5092) );
NAND2X1TS U2405 ( .A(n5510), .B(n2114), .Y(n2116) );
INVX4TS U2406 ( .A(n4957), .Y(n5585) );
ADDHXLTS U2407 ( .A(n5074), .B(n5073), .CO(n5078), .S(
DP_OP_169J43_123_4229_n1279) );
NAND2BXLTS U2408 ( .AN(n5098), .B(n5396), .Y(n5066) );
BUFX4TS U2409 ( .A(n1976), .Y(n5589) );
NAND2X1TS U2410 ( .A(n5472), .B(n1959), .Y(n5095) );
BUFX4TS U2411 ( .A(n1966), .Y(n5592) );
INVX2TS U2412 ( .A(n1969), .Y(n1964) );
INVX4TS U2413 ( .A(n812), .Y(n5468) );
NOR2X1TS U2414 ( .A(n3650), .B(n3748), .Y(n2279) );
NAND2X1TS U2415 ( .A(n3654), .B(n3650), .Y(n2276) );
INVX2TS U2416 ( .A(n4069), .Y(n2073) );
NAND2X1TS U2417 ( .A(n2046), .B(n2063), .Y(n2050) );
OAI21XLTS U2418 ( .A0(n4642), .A1(n4496), .B0(n4475), .Y(n4476) );
NOR2BX1TS U2419 ( .AN(n2717), .B(n2716), .Y(n3350) );
NOR2X1TS U2420 ( .A(n2718), .B(n2717), .Y(n2841) );
OAI21X1TS U2421 ( .A0(n2653), .A1(n2652), .B0(n2651), .Y(n2792) );
ADDHXLTS U2422 ( .A(n5045), .B(n5044), .CO(n5049), .S(
DP_OP_169J43_123_4229_n1244) );
NAND2BXLTS U2423 ( .AN(n5098), .B(n5330), .Y(n5038) );
ADDHXLTS U2424 ( .A(n5070), .B(n5069), .CO(DP_OP_169J43_123_4229_n1262), .S(
n5077) );
NAND2BXLTS U2425 ( .AN(n5098), .B(n5363), .Y(n5063) );
OAI21XLTS U2426 ( .A0(n3314), .A1(n3453), .B0(n851), .Y(n1537) );
INVX2TS U2427 ( .A(n2713), .Y(n1918) );
NAND2X1TS U2428 ( .A(n3621), .B(n3692), .Y(n1884) );
NAND2BX1TS U2429 ( .AN(n2209), .B(n2210), .Y(n2221) );
OAI21XLTS U2430 ( .A0(n6546), .A1(n2785), .B0(n909), .Y(n910) );
NAND2X1TS U2431 ( .A(n3687), .B(n3682), .Y(n1791) );
AO21XLTS U2432 ( .A0(n3595), .A1(n767), .B0(n3569), .Y(n1901) );
OAI21XLTS U2433 ( .A0(n4585), .A1(n4424), .B0(n2896), .Y(n2897) );
CLKAND2X2TS U2434 ( .A(n772), .B(n4558), .Y(n4499) );
NAND2X1TS U2435 ( .A(n1722), .B(n2765), .Y(n1726) );
OAI21XLTS U2436 ( .A0(n4590), .A1(n4424), .B0(n4398), .Y(n4399) );
CLKAND2X2TS U2437 ( .A(n4620), .B(n4558), .Y(n4553) );
CLKAND2X2TS U2438 ( .A(n3248), .B(n3703), .Y(n2428) );
CLKAND2X2TS U2439 ( .A(n3248), .B(n3708), .Y(n2700) );
CLKAND2X2TS U2440 ( .A(n3248), .B(n3698), .Y(n3249) );
NOR2BX1TS U2441 ( .AN(n1845), .B(n1844), .Y(n1897) );
AO21XLTS U2442 ( .A0(n3751), .A1(n767), .B0(n3733), .Y(n3673) );
CLKAND2X2TS U2443 ( .A(n4304), .B(n4383), .Y(n4273) );
CLKAND2X2TS U2444 ( .A(n4164), .B(n4607), .Y(n4056) );
AO21XLTS U2445 ( .A0(n3661), .A1(n3670), .B0(n3641), .Y(n3606) );
BUFX4TS U2446 ( .A(n5408), .Y(n5441) );
CLKAND2X2TS U2447 ( .A(n3313), .B(n3742), .Y(n2581) );
AO21XLTS U2448 ( .A0(n3559), .A1(n3670), .B0(n3545), .Y(n3515) );
CLKAND2X2TS U2449 ( .A(n3313), .B(n3737), .Y(n2657) );
CLKAND2X2TS U2450 ( .A(n4164), .B(n4540), .Y(mult_x_24_n958) );
CLKAND2X2TS U2451 ( .A(n4164), .B(n4637), .Y(n4066) );
CLKAND2X2TS U2452 ( .A(n4106), .B(n4615), .Y(mult_x_24_n948) );
NAND2X2TS U2453 ( .A(n859), .B(n1766), .Y(n2761) );
CLKAND2X2TS U2454 ( .A(n3248), .B(n3621), .Y(n2751) );
OAI21X1TS U2455 ( .A0(n2713), .A1(n1828), .B0(n1827), .Y(n1887) );
CLKAND2X2TS U2456 ( .A(n3313), .B(n3719), .Y(n2495) );
CLKAND2X2TS U2457 ( .A(Op_MX[27]), .B(Op_MX[0]), .Y(n2124) );
NOR2X1TS U2458 ( .A(n942), .B(n941), .Y(n1157) );
ADDFX2TS U2459 ( .A(Sgf_operation_ODD1_Q_middle[4]), .B(
DP_OP_168J43_122_1342_n443), .CI(DP_OP_168J43_122_1342_n495), .CO(n943), .S(n942) );
AOI21X2TS U2460 ( .A0(n1098), .A1(n962), .B0(n961), .Y(n1081) );
OAI21X1TS U2461 ( .A0(n1103), .A1(n1108), .B0(n1104), .Y(n961) );
NAND2X1TS U2462 ( .A(n1097), .B(n962), .Y(n1082) );
NOR2X1TS U2463 ( .A(n964), .B(n963), .Y(n1089) );
OAI21X2TS U2464 ( .A0(n1092), .A1(n1112), .B0(n1093), .Y(n1084) );
NOR2X1TS U2465 ( .A(n978), .B(n977), .Y(n1216) );
OAI21X1TS U2466 ( .A0(n1062), .A1(n998), .B0(n997), .Y(n1251) );
AOI21X1TS U2467 ( .A0(n1065), .A1(n996), .B0(n995), .Y(n997) );
NAND2X1TS U2468 ( .A(n1564), .B(n1461), .Y(n1580) );
NAND2X1TS U2469 ( .A(n2726), .B(n2737), .Y(n2740) );
BUFX4TS U2470 ( .A(n5209), .Y(n5242) );
AO21XLTS U2471 ( .A0(n5337), .A1(n5341), .B0(n876), .Y(n2618) );
AO21XLTS U2472 ( .A0(n5372), .A1(n5343), .B0(n897), .Y(
DP_OP_169J43_123_4229_n1554) );
AO21XLTS U2473 ( .A0(n5423), .A1(n5408), .B0(n761), .Y(
DP_OP_169J43_123_4229_n1614) );
BUFX4TS U2474 ( .A(n5341), .Y(n5339) );
BUFX4TS U2475 ( .A(n5277), .Y(n5308) );
AO21XLTS U2476 ( .A0(n5508), .A1(n5476), .B0(n896), .Y(
DP_OP_169J43_123_4229_n1674) );
BUFX4TS U2477 ( .A(n5067), .Y(n5389) );
BUFX4TS U2478 ( .A(n5343), .Y(n5374) );
BUFX4TS U2479 ( .A(n5010), .Y(n5271) );
BUFX4TS U2480 ( .A(n5412), .Y(n5423) );
BUFX4TS U2481 ( .A(n5407), .Y(n5405) );
NOR2X2TS U2482 ( .A(n2761), .B(n1695), .Y(n3781) );
NOR2X2TS U2483 ( .A(n1668), .B(n4079), .Y(n4069) );
NOR2X1TS U2484 ( .A(n2059), .B(n1673), .Y(n1675) );
OAI21X1TS U2485 ( .A0(n1661), .A1(n2022), .B0(n1660), .Y(n1662) );
NOR2X1TS U2486 ( .A(n1661), .B(n2021), .Y(n1663) );
NAND2X1TS U2487 ( .A(n3781), .B(n3784), .Y(n3787) );
NAND2X1TS U2488 ( .A(n4583), .B(n4578), .Y(n1765) );
NAND2X1TS U2489 ( .A(n4573), .B(n4578), .Y(n1758) );
CLKAND2X2TS U2490 ( .A(n4354), .B(n4558), .Y(n4325) );
CLKAND2X2TS U2491 ( .A(n4164), .B(n4647), .Y(mult_x_24_n954) );
CLKAND2X2TS U2492 ( .A(n4415), .B(n4558), .Y(n4387) );
NAND2X1TS U2493 ( .A(n1825), .B(n1718), .Y(n1771) );
NAND2X1TS U2494 ( .A(n2649), .B(n1602), .Y(n2486) );
NAND2X1TS U2495 ( .A(n1708), .B(n1710), .Y(n1713) );
AOI21X2TS U2496 ( .A0(n2650), .A1(n1602), .B0(n1601), .Y(n2485) );
OAI21X2TS U2497 ( .A0(n2199), .A1(n1599), .B0(n1598), .Y(n1716) );
NAND2X1TS U2498 ( .A(n2230), .B(n1597), .Y(n1599) );
AOI21X1TS U2499 ( .A0(n2229), .A1(n1597), .B0(n1596), .Y(n1598) );
NOR2X1TS U2500 ( .A(n2277), .B(n2279), .Y(n1597) );
INVX2TS U2501 ( .A(Sgf_operation_ODD1_Q_right[47]), .Y(n929) );
INVX2TS U2502 ( .A(Sgf_operation_ODD1_Q_right[48]), .Y(n928) );
INVX2TS U2503 ( .A(Sgf_operation_ODD1_Q_right[49]), .Y(n925) );
INVX2TS U2504 ( .A(Sgf_operation_ODD1_Q_right[50]), .Y(n923) );
INVX2TS U2505 ( .A(Sgf_operation_ODD1_Q_right[52]), .Y(n920) );
INVX2TS U2506 ( .A(Sgf_operation_ODD1_Q_right[53]), .Y(n919) );
NAND2X1TS U2507 ( .A(n944), .B(n943), .Y(n1165) );
AOI21X1TS U2508 ( .A0(DP_OP_168J43_122_1342_n499), .A1(n888), .B0(n933), .Y(
n1148) );
NAND2X1TS U2509 ( .A(n1032), .B(n1031), .Y(n1338) );
NOR2X2TS U2510 ( .A(n1032), .B(n1031), .Y(n1337) );
NAND2X1TS U2511 ( .A(n6153), .B(n1321), .Y(n1324) );
AOI21X1TS U2512 ( .A0(n1322), .A1(n1321), .B0(n1320), .Y(n1323) );
NOR2X2TS U2513 ( .A(n1324), .B(n6086), .Y(n1326) );
NOR2X1TS U2514 ( .A(n1026), .B(n1025), .Y(n1343) );
NAND2X1TS U2515 ( .A(n1028), .B(n1027), .Y(n1345) );
INVX2TS U2516 ( .A(n1343), .Y(n1262) );
INVX2TS U2517 ( .A(Sgf_operation_ODD1_Q_right[39]), .Y(n931) );
NAND2X1TS U2518 ( .A(n3360), .B(n3587), .Y(n2215) );
ADDHXLTS U2519 ( .A(n2158), .B(n2157), .CO(DP_OP_169J43_123_4229_n1308), .S(
n2178) );
OAI21XLTS U2520 ( .A0(n3666), .A1(n3665), .B0(n3664), .Y(n3667) );
OAI21XLTS U2521 ( .A0(n831), .A1(n3599), .B0(n3598), .Y(n3601) );
OAI21XLTS U2522 ( .A0(n3353), .A1(n3599), .B0(n2190), .Y(n2192) );
OAI21XLTS U2523 ( .A0(n6546), .A1(n2715), .B0(n913), .Y(n914) );
AOI21X1TS U2524 ( .A0(n3791), .A1(n867), .B0(n2040), .Y(n2043) );
CMPR42X1TS U2525 ( .A(mult_x_24_n866), .B(mult_x_24_n1529), .C(
mult_x_24_n1448), .D(mult_x_24_n1475), .ICI(mult_x_24_n870), .S(
mult_x_24_n864), .ICO(mult_x_24_n862), .CO(mult_x_24_n863) );
BUFX3TS U2526 ( .A(n2841), .Y(n3560) );
NAND2X1TS U2527 ( .A(n1942), .B(n1941), .Y(n1943) );
AOI21X1TS U2528 ( .A0(n3791), .A1(n1940), .B0(n1939), .Y(n1944) );
NAND2X1TS U2529 ( .A(n864), .B(n2000), .Y(n2001) );
AOI21X1TS U2530 ( .A0(n3791), .A1(n1999), .B0(n1998), .Y(n2002) );
CMPR42X1TS U2531 ( .A(DP_OP_169J43_123_4229_n1686), .B(
DP_OP_169J43_123_4229_n1714), .C(DP_OP_169J43_123_4229_n1173), .D(
DP_OP_169J43_123_4229_n1180), .ICI(DP_OP_169J43_123_4229_n1165), .S(
DP_OP_169J43_123_4229_n1159), .ICO(DP_OP_169J43_123_4229_n1157), .CO(
DP_OP_169J43_123_4229_n1158) );
NOR2X1TS U2532 ( .A(n2454), .B(n2456), .Y(n2445) );
NOR2X1TS U2533 ( .A(n3092), .B(n3087), .Y(n2987) );
AO21XLTS U2534 ( .A0(n3472), .A1(n767), .B0(n3458), .Y(n3431) );
NOR2X1TS U2535 ( .A(n2563), .B(n2565), .Y(n2554) );
NAND2X1TS U2536 ( .A(n1850), .B(n1995), .Y(n1851) );
AOI21X1TS U2537 ( .A0(n3791), .A1(n1849), .B0(n1848), .Y(n1852) );
NOR2X1TS U2538 ( .A(n3879), .B(n3764), .Y(n3767) );
NOR2X1TS U2539 ( .A(n4821), .B(n4826), .Y(n2515) );
CMPR42X1TS U2540 ( .A(DP_OP_169J43_123_4229_n1020), .B(
DP_OP_169J43_123_4229_n999), .C(DP_OP_169J43_123_4229_n996), .D(
DP_OP_169J43_123_4229_n1017), .ICI(DP_OP_169J43_123_4229_n993), .S(
DP_OP_169J43_123_4229_n990), .ICO(DP_OP_169J43_123_4229_n988), .CO(
DP_OP_169J43_123_4229_n989) );
CMPR42X1TS U2541 ( .A(DP_OP_169J43_123_4229_n1041), .B(
DP_OP_169J43_123_4229_n1021), .C(DP_OP_169J43_123_4229_n1038), .D(
DP_OP_169J43_123_4229_n1035), .ICI(DP_OP_169J43_123_4229_n1031), .S(
DP_OP_169J43_123_4229_n1012), .ICO(DP_OP_169J43_123_4229_n1010), .CO(
DP_OP_169J43_123_4229_n1011) );
NOR2X1TS U2542 ( .A(n4652), .B(n4656), .Y(n4658) );
CMPR42X1TS U2543 ( .A(mult_x_24_n1380), .B(mult_x_24_n1515), .C(
mult_x_24_n1407), .D(mult_x_24_n1461), .ICI(mult_x_24_n719), .S(
mult_x_24_n705), .ICO(mult_x_24_n703), .CO(mult_x_24_n704) );
CMPR42X1TS U2544 ( .A(mult_x_24_n1486), .B(mult_x_24_n1459), .C(
mult_x_24_n683), .D(mult_x_24_n695), .ICI(mult_x_24_n688), .S(
mult_x_24_n678), .ICO(mult_x_24_n676), .CO(mult_x_24_n677) );
OAI21XLTS U2545 ( .A0(n4565), .A1(n4424), .B0(n4392), .Y(n4393) );
OAI21XLTS U2546 ( .A0(n4560), .A1(n4424), .B0(n4390), .Y(n4391) );
CLKAND2X2TS U2547 ( .A(n3248), .B(n3692), .Y(n2418) );
AO21XLTS U2548 ( .A0(n3425), .A1(n767), .B0(n3412), .Y(n1746) );
CLKAND2X2TS U2549 ( .A(n4106), .B(n4603), .Y(mult_x_24_n946) );
CLKAND2X2TS U2550 ( .A(n4244), .B(n4383), .Y(n4216) );
CMPR42X1TS U2551 ( .A(DP_OP_169J43_123_4229_n978), .B(
DP_OP_169J43_123_4229_n959), .C(DP_OP_169J43_123_4229_n975), .D(
DP_OP_169J43_123_4229_n972), .ICI(DP_OP_169J43_123_4229_n953), .S(
DP_OP_169J43_123_4229_n950), .ICO(DP_OP_169J43_123_4229_n948), .CO(
DP_OP_169J43_123_4229_n949) );
BUFX4TS U2552 ( .A(n2867), .Y(n3458) );
INVX4TS U2553 ( .A(n2756), .Y(n3448) );
BUFX3TS U2554 ( .A(n2780), .Y(n3451) );
BUFX3TS U2555 ( .A(n2866), .Y(n3453) );
CMPR42X1TS U2556 ( .A(mult_x_23_n1176), .B(mult_x_23_n1228), .C(
mult_x_23_n1150), .D(mult_x_23_n590), .ICI(mult_x_23_n587), .S(
mult_x_23_n579), .ICO(mult_x_23_n577), .CO(mult_x_23_n578) );
AO21XLTS U2557 ( .A0(n3507), .A1(n767), .B0(n3488), .Y(n1841) );
BUFX4TS U2558 ( .A(n1626), .Y(n5097) );
INVX2TS U2559 ( .A(n1621), .Y(n1623) );
AOI21X1TS U2560 ( .A0(n827), .A1(n6309), .B0(n1180), .Y(n1181) );
NAND2X1TS U2561 ( .A(n964), .B(n963), .Y(n1112) );
NAND2X1TS U2562 ( .A(n970), .B(n969), .Y(n1200) );
NOR2X2TS U2563 ( .A(n970), .B(n969), .Y(n1199) );
NOR2X2TS U2564 ( .A(n1002), .B(n1001), .Y(n1297) );
AOI21X1TS U2565 ( .A0(n1253), .A1(n1252), .B0(n1251), .Y(n1296) );
NOR2X2TS U2566 ( .A(n1000), .B(n999), .Y(n1302) );
NAND2X1TS U2567 ( .A(n1002), .B(n1001), .Y(n1298) );
OAI21X2TS U2568 ( .A0(n1581), .A1(n1465), .B0(n1464), .Y(n2738) );
CLKAND2X2TS U2569 ( .A(n2736), .B(Op_MY[26]), .Y(n2728) );
CLKAND2X2TS U2570 ( .A(n2737), .B(Op_MY[26]), .Y(n2729) );
AO21XLTS U2571 ( .A0(n5204), .A1(n5208), .B0(n900), .Y(n2699) );
AO21XLTS U2572 ( .A0(n5257), .A1(n5275), .B0(n5008), .Y(n1579) );
BUFX4TS U2573 ( .A(n5142), .Y(n5175) );
AO21XLTS U2574 ( .A0(n5224), .A1(n5209), .B0(n762), .Y(
DP_OP_169J43_123_4229_n1434) );
AO21XLTS U2575 ( .A0(n5290), .A1(n5277), .B0(n811), .Y(
DP_OP_169J43_123_4229_n1494) );
NOR2X1TS U2576 ( .A(n4784), .B(n4779), .Y(n4667) );
CMPR42X1TS U2577 ( .A(DP_OP_169J43_123_4229_n1061), .B(
DP_OP_169J43_123_4229_n1042), .C(DP_OP_169J43_123_4229_n1058), .D(
DP_OP_169J43_123_4229_n1055), .ICI(DP_OP_169J43_123_4229_n1051), .S(
DP_OP_169J43_123_4229_n1033), .ICO(DP_OP_169J43_123_4229_n1031), .CO(
DP_OP_169J43_123_4229_n1032) );
NAND2X2TS U2578 ( .A(n1940), .B(n1690), .Y(n3782) );
BUFX4TS U2579 ( .A(n1678), .Y(n3791) );
NAND2X1TS U2580 ( .A(n4069), .B(n1675), .Y(n1677) );
AOI21X1TS U2581 ( .A0(n4068), .A1(n1675), .B0(n1674), .Y(n1676) );
CLKAND2X2TS U2582 ( .A(n4161), .B(n4383), .Y(n3793) );
CLKAND2X2TS U2583 ( .A(n4106), .B(n4583), .Y(mult_x_24_n942) );
CLKAND2X2TS U2584 ( .A(n4195), .B(n4383), .Y(n4168) );
CLKAND2X2TS U2585 ( .A(n4164), .B(n4593), .Y(n4051) );
CLKAND2X2TS U2586 ( .A(n4106), .B(n4588), .Y(n4046) );
CMPR42X1TS U2587 ( .A(n6555), .B(mult_x_24_n954), .C(mult_x_24_n952), .D(
mult_x_24_n1319), .ICI(mult_x_24_n1373), .S(mult_x_24_n629), .ICO(
mult_x_24_n627), .CO(mult_x_24_n628) );
CLKAND2X2TS U2588 ( .A(n4164), .B(n4632), .Y(mult_x_24_n952) );
CMPR42X1TS U2589 ( .A(mult_x_24_n953), .B(mult_x_24_n649), .C(
mult_x_24_n1320), .D(mult_x_24_n1455), .ICI(mult_x_24_n1374), .S(
mult_x_24_n638), .ICO(mult_x_24_n636), .CO(mult_x_24_n637) );
CLKAND2X2TS U2590 ( .A(n4164), .B(n4639), .Y(mult_x_24_n953) );
NOR2X1TS U2591 ( .A(n1738), .B(n1771), .Y(n2708) );
OAI21X1TS U2592 ( .A0(n1773), .A1(n1738), .B0(n1737), .Y(n2710) );
CLKAND2X2TS U2593 ( .A(n3248), .B(n3674), .Y(n3002) );
CLKAND2X2TS U2594 ( .A(n3248), .B(n3609), .Y(n2996) );
CLKAND2X2TS U2595 ( .A(n3248), .B(n3682), .Y(n2303) );
CLKAND2X2TS U2596 ( .A(n3248), .B(n3677), .Y(n2102) );
AO21XLTS U2597 ( .A0(n3399), .A1(n767), .B0(n3393), .Y(n3371) );
INVX2TS U2598 ( .A(n1822), .Y(n3685) );
XNOR2X1TS U2599 ( .A(n1139), .B(n1138), .Y(n1155) );
OAI21XLTS U2600 ( .A0(n1144), .A1(n1140), .B0(n1141), .Y(n1139) );
XNOR2X1TS U2601 ( .A(n1123), .B(n1122), .Y(n1177) );
XOR2X1TS U2602 ( .A(n1107), .B(n1106), .Y(n1186) );
AOI21X1TS U2603 ( .A0(n1111), .A1(n1109), .B0(n1102), .Y(n1107) );
XNOR2X1TS U2604 ( .A(n1250), .B(n1249), .Y(n1307) );
AOI21X1TS U2605 ( .A0(n1242), .A1(n6189), .B0(n1241), .Y(n6084) );
XNOR2X1TS U2606 ( .A(n1260), .B(n1259), .Y(n1312) );
XNOR2X1TS U2607 ( .A(n1111), .B(n1110), .Y(n1185) );
XOR2X1TS U2608 ( .A(n1245), .B(n1068), .Y(n1240) );
NOR2X2TS U2609 ( .A(n1240), .B(Sgf_operation_ODD1_Q_right[49]), .Y(n6197) );
NOR2X1TS U2610 ( .A(n1312), .B(Sgf_operation_ODD1_Q_left[0]), .Y(n6090) );
XNOR2X1TS U2611 ( .A(n1285), .B(n1284), .Y(n1314) );
XOR2X1TS U2612 ( .A(n1279), .B(n1278), .Y(n1316) );
NOR2X2TS U2613 ( .A(n1316), .B(Sgf_operation_ODD1_Q_left[3]), .Y(n6120) );
XNOR2X1TS U2614 ( .A(n1074), .B(n1073), .Y(n1237) );
XNOR2X1TS U2615 ( .A(n1128), .B(n1127), .Y(n1179) );
NOR2X2TS U2616 ( .A(n1352), .B(Sgf_operation_ODD1_Q_left[9]), .Y(n6035) );
OAI21X1TS U2617 ( .A0(n6062), .A1(n6074), .B0(n6063), .Y(n6048) );
NOR2X1TS U2618 ( .A(n6062), .B(n6073), .Y(n6047) );
AOI21X1TS U2619 ( .A0(n1261), .A1(n1034), .B0(n1033), .Y(n1332) );
XNOR2X1TS U2620 ( .A(n1341), .B(n1340), .Y(n1349) );
NOR2X2TS U2621 ( .A(n1349), .B(Sgf_operation_ODD1_Q_left[7]), .Y(n6062) );
XOR2X1TS U2622 ( .A(n1344), .B(n1263), .Y(n1319) );
NOR2X2TS U2623 ( .A(n1319), .B(Sgf_operation_ODD1_Q_left[5]), .Y(n6093) );
OAI21X2TS U2624 ( .A0(n6118), .A1(n6120), .B0(n6121), .Y(n6105) );
XNOR2X1TS U2625 ( .A(n1274), .B(n1273), .Y(n1317) );
XNOR2X1TS U2626 ( .A(n1290), .B(n1289), .Y(n1313) );
NOR2X2TS U2627 ( .A(n1415), .B(Sgf_operation_ODD1_Q_left[29]), .Y(n5813) );
OR2X1TS U2628 ( .A(n4158), .B(n4159), .Y(n915) );
INVX2TS U2629 ( .A(n2313), .Y(n4141) );
BUFX4TS U2630 ( .A(Op_MX[2]), .Y(n4485) );
OAI21XLTS U2631 ( .A0(n4497), .A1(n2327), .B0(n2367), .Y(n2368) );
OAI21XLTS U2632 ( .A0(n2345), .A1(n6547), .B0(n2346), .Y(n2347) );
OAI21XLTS U2633 ( .A0(n831), .A1(n2236), .B0(n2246), .Y(n2247) );
OAI21XLTS U2634 ( .A0(n3314), .A1(n3636), .B0(n855), .Y(n2223) );
NAND2BXLTS U2635 ( .AN(n5098), .B(n5533), .Y(n2146) );
CMPR42X1TS U2636 ( .A(DP_OP_169J43_123_4229_n1289), .B(
DP_OP_169J43_123_4229_n1725), .C(DP_OP_169J43_123_4229_n1752), .D(
DP_OP_169J43_123_4229_n1285), .ICI(DP_OP_169J43_123_4229_n1286), .S(
DP_OP_169J43_123_4229_n1282), .ICO(DP_OP_169J43_123_4229_n1280), .CO(
DP_OP_169J43_123_4229_n1281) );
CMPR42X1TS U2637 ( .A(DP_OP_169J43_123_4229_n1724), .B(
DP_OP_169J43_123_4229_n1696), .C(DP_OP_169J43_123_4229_n1284), .D(
DP_OP_169J43_123_4229_n1280), .ICI(DP_OP_169J43_123_4229_n1277), .S(
DP_OP_169J43_123_4229_n1274), .ICO(DP_OP_169J43_123_4229_n1272), .CO(
DP_OP_169J43_123_4229_n1273) );
OAI21X1TS U2638 ( .A0(n4910), .A1(n2407), .B0(n2406), .Y(n2498) );
CMPR42X1TS U2639 ( .A(DP_OP_169J43_123_4229_n1666), .B(
DP_OP_169J43_123_4229_n1722), .C(DP_OP_169J43_123_4229_n1268), .D(
DP_OP_169J43_123_4229_n1264), .ICI(DP_OP_169J43_123_4229_n1259), .S(
DP_OP_169J43_123_4229_n1256), .ICO(DP_OP_169J43_123_4229_n1254), .CO(
DP_OP_169J43_123_4229_n1255) );
CMPR42X1TS U2640 ( .A(DP_OP_169J43_123_4229_n1217), .B(
DP_OP_169J43_123_4229_n1214), .C(DP_OP_169J43_123_4229_n1206), .D(
DP_OP_169J43_123_4229_n1203), .ICI(DP_OP_169J43_123_4229_n1210), .S(
DP_OP_169J43_123_4229_n1200), .ICO(DP_OP_169J43_123_4229_n1198), .CO(
DP_OP_169J43_123_4229_n1199) );
CMPR42X1TS U2641 ( .A(mult_x_23_n1345), .B(mult_x_23_n725), .C(
mult_x_23_n726), .D(mult_x_23_n722), .ICI(mult_x_23_n716), .S(
mult_x_23_n713), .ICO(mult_x_23_n711), .CO(mult_x_23_n712) );
NAND2X1TS U2642 ( .A(n2450), .B(n2445), .Y(n2974) );
NAND2X1TS U2643 ( .A(n3086), .B(n2987), .Y(n3076) );
NOR2X1TS U2644 ( .A(mult_x_23_n647), .B(mult_x_23_n657), .Y(n2454) );
NOR2X1TS U2645 ( .A(n3116), .B(n3121), .Y(n2450) );
NOR2X1TS U2646 ( .A(n4813), .B(n4808), .Y(n2524) );
NOR2X1TS U2647 ( .A(n2474), .B(n2477), .Y(n2973) );
CMPR42X1TS U2648 ( .A(mult_x_24_n704), .B(mult_x_24_n693), .C(mult_x_24_n701), .D(mult_x_24_n690), .ICI(mult_x_24_n697), .S(mult_x_24_n687), .ICO(
mult_x_24_n685), .CO(mult_x_24_n686) );
NOR2X1TS U2649 ( .A(n3900), .B(n3905), .Y(n2559) );
NOR2X1TS U2650 ( .A(n2644), .B(n2641), .Y(n3758) );
XNOR2X1TS U2651 ( .A(n1163), .B(n1158), .Y(n1159) );
NOR2X1TS U2652 ( .A(n1185), .B(Sgf_operation_ODD1_Q_right[37]), .Y(n6316) );
XOR2X1TS U2653 ( .A(n1096), .B(n1095), .Y(n1191) );
XNOR2X1TS U2654 ( .A(n1198), .B(n1088), .Y(n1192) );
NOR2X2TS U2655 ( .A(n1192), .B(Sgf_operation_ODD1_Q_right[41]), .Y(n6251) );
OAI21X1TS U2656 ( .A0(n1190), .A1(n6315), .B0(n1189), .Y(n6244) );
NAND2X1TS U2657 ( .A(n6330), .B(n835), .Y(n1190) );
AOI21X1TS U2658 ( .A0(n6328), .A1(n835), .B0(n1188), .Y(n1189) );
AOI21X2TS U2659 ( .A0(n1194), .A1(n6244), .B0(n1193), .Y(n6214) );
NOR2X1TS U2660 ( .A(n6251), .B(n6249), .Y(n1194) );
OAI21X1TS U2661 ( .A0(n6251), .A1(n6248), .B0(n6252), .Y(n1193) );
XOR2X1TS U2662 ( .A(n1222), .B(n1221), .Y(n1228) );
AOI21X1TS U2663 ( .A0(n1253), .A1(n1224), .B0(n1217), .Y(n1222) );
NOR2X2TS U2664 ( .A(n1228), .B(Sgf_operation_ODD1_Q_right[44]), .Y(n6216) );
AOI21X1TS U2665 ( .A0(n810), .A1(n6223), .B0(n1230), .Y(n6230) );
NAND2X1TS U2666 ( .A(n810), .B(n6224), .Y(n6229) );
XNOR2X1TS U2667 ( .A(n1210), .B(n1209), .Y(n1231) );
NOR2X2TS U2668 ( .A(n1231), .B(Sgf_operation_ODD1_Q_right[46]), .Y(n6233) );
NOR2X2TS U2669 ( .A(n1309), .B(Sgf_operation_ODD1_Q_right[52]), .Y(n6173) );
AO21XLTS U2670 ( .A0(n5157), .A1(n5142), .B0(n5143), .Y(
DP_OP_169J43_123_4229_n1374) );
NOR2X1TS U2671 ( .A(n2629), .B(n2632), .Y(n4653) );
CLKAND2X2TS U2672 ( .A(n3248), .B(n3670), .Y(n3007) );
NAND2X1TS U2673 ( .A(n1153), .B(Sgf_operation_ODD1_Q_right[29]), .Y(n6276)
);
NOR2X1TS U2674 ( .A(n1176), .B(Sgf_operation_ODD1_Q_right[33]), .Y(n6293) );
NAND2X1TS U2675 ( .A(n1176), .B(Sgf_operation_ODD1_Q_right[33]), .Y(n6294)
);
NAND2X1TS U2676 ( .A(n1177), .B(Sgf_operation_ODD1_Q_right[34]), .Y(n6303)
);
NAND2X1TS U2677 ( .A(n1307), .B(Sgf_operation_ODD1_Q_right[50]), .Y(n6204)
);
NAND2X1TS U2678 ( .A(n1312), .B(Sgf_operation_ODD1_Q_left[0]), .Y(n6152) );
AOI21X1TS U2679 ( .A0(n6212), .A1(n6089), .B0(n6088), .Y(n6155) );
NAND2X1TS U2680 ( .A(Sgf_operation_ODD1_Q_left[31]), .B(
Sgf_operation_ODD1_Q_left[30]), .Y(n5790) );
NAND2X1TS U2681 ( .A(n5724), .B(n5668), .Y(n5697) );
INVX2TS U2682 ( .A(n5667), .Y(n5668) );
NAND2X1TS U2683 ( .A(n5655), .B(Sgf_operation_ODD1_Q_left[46]), .Y(n1434) );
MX2X1TS U2684 ( .A(Op_MX[55]), .B(exp_oper_result[3]), .S0(FSM_selector_A),
.Y(S_Oper_A_exp[3]) );
MX2X1TS U2685 ( .A(Op_MX[54]), .B(exp_oper_result[2]), .S0(FSM_selector_A),
.Y(S_Oper_A_exp[2]) );
NAND2X1TS U2686 ( .A(n1185), .B(Sgf_operation_ODD1_Q_right[37]), .Y(n6319)
);
INVX2TS U2687 ( .A(n6144), .Y(n6131) );
OAI21X1TS U2688 ( .A0(n6155), .A1(n6090), .B0(n6152), .Y(n6132) );
NAND2X1TS U2689 ( .A(n1314), .B(Sgf_operation_ODD1_Q_left[2]), .Y(n6133) );
NOR2X1TS U2690 ( .A(n5626), .B(n5969), .Y(n5958) );
OR2X1TS U2691 ( .A(n1179), .B(Sgf_operation_ODD1_Q_right[36]), .Y(n827) );
NAND2X1TS U2692 ( .A(n1179), .B(Sgf_operation_ODD1_Q_right[36]), .Y(n6311)
);
NAND2X1TS U2693 ( .A(n1169), .B(Sgf_operation_ODD1_Q_right[32]), .Y(n6289)
);
NOR2X1TS U2694 ( .A(n1152), .B(Sgf_operation_ODD1_Q_right[28]), .Y(n6270) );
MX2X1TS U2695 ( .A(Op_MX[52]), .B(exp_oper_result[0]), .S0(FSM_selector_A),
.Y(S_Oper_A_exp[0]) );
MX2X1TS U2696 ( .A(Op_MX[53]), .B(exp_oper_result[1]), .S0(FSM_selector_A),
.Y(S_Oper_A_exp[1]) );
NOR2X1TS U2697 ( .A(n1358), .B(Sgf_operation_ODD1_Q_left[10]), .Y(n6019) );
NAND2X1TS U2698 ( .A(n1358), .B(Sgf_operation_ODD1_Q_left[10]), .Y(n6020) );
OR2X1TS U2699 ( .A(n1350), .B(Sgf_operation_ODD1_Q_left[8]), .Y(n825) );
NAND2X1TS U2700 ( .A(n1313), .B(Sgf_operation_ODD1_Q_left[1]), .Y(n6144) );
NOR2X1TS U2701 ( .A(n6173), .B(n6208), .Y(n6163) );
OAI21X1TS U2702 ( .A0(n6173), .A1(n6209), .B0(n6174), .Y(n6162) );
INVX2TS U2703 ( .A(n6058), .Y(n6102) );
NAND2X1TS U2704 ( .A(n1442), .B(n1441), .Y(n1539) );
OAI21XLTS U2705 ( .A0(n3314), .A1(n2236), .B0(n857), .Y(n2244) );
OAI21X1TS U2706 ( .A0(n3220), .A1(n3216), .B0(n3217), .Y(n3215) );
NAND2BXLTS U2707 ( .AN(n5098), .B(n5591), .Y(n1629) );
BUFX3TS U2708 ( .A(n5649), .Y(n6179) );
AOI21X1TS U2709 ( .A0(n877), .A1(n759), .B0(n1156), .Y(n6287) );
NOR2X1TS U2710 ( .A(n1159), .B(Sgf_operation_ODD1_Q_right[31]), .Y(n6283) );
OR2X1TS U2711 ( .A(n1178), .B(Sgf_operation_ODD1_Q_right[35]), .Y(n828) );
OAI21X1TS U2712 ( .A0(n6322), .A1(n6319), .B0(n6323), .Y(n6328) );
NOR2X1TS U2713 ( .A(n6322), .B(n6316), .Y(n6330) );
OR2X1TS U2714 ( .A(n1187), .B(Sgf_operation_ODD1_Q_right[39]), .Y(n835) );
NAND2X1TS U2715 ( .A(n1191), .B(Sgf_operation_ODD1_Q_right[40]), .Y(n6248)
);
NOR2X2TS U2716 ( .A(n1191), .B(Sgf_operation_ODD1_Q_right[40]), .Y(n6249) );
NAND2X1TS U2717 ( .A(n1192), .B(Sgf_operation_ODD1_Q_right[41]), .Y(n6252)
);
NAND2X1TS U2718 ( .A(n1226), .B(Sgf_operation_ODD1_Q_right[42]), .Y(n6257)
);
OR2X1TS U2719 ( .A(n1226), .B(Sgf_operation_ODD1_Q_right[42]), .Y(n826) );
OAI21X1TS U2720 ( .A0(n6216), .A1(n6262), .B0(n6217), .Y(n6223) );
NOR2X1TS U2721 ( .A(n6216), .B(n6261), .Y(n6224) );
OR2X1TS U2722 ( .A(n1229), .B(Sgf_operation_ODD1_Q_right[45]), .Y(n810) );
NAND2X1TS U2723 ( .A(n1229), .B(Sgf_operation_ODD1_Q_right[45]), .Y(n6225)
);
NAND2X1TS U2724 ( .A(n1231), .B(Sgf_operation_ODD1_Q_right[46]), .Y(n6234)
);
XOR3X1TS U2725 ( .A(n4694), .B(n4693), .C(n4692), .Y(n4695) );
MX2X1TS U2726 ( .A(P_Sgf[69]), .B(n5965), .S0(n6136), .Y(n490) );
XOR2X1TS U2727 ( .A(n5964), .B(n5963), .Y(n5965) );
MX2X1TS U2728 ( .A(P_Sgf[70]), .B(n5954), .S0(n6136), .Y(n491) );
MX2X1TS U2729 ( .A(P_Sgf[71]), .B(n5945), .S0(n5944), .Y(n492) );
XOR2X1TS U2730 ( .A(n5943), .B(n5942), .Y(n5945) );
XOR2X1TS U2731 ( .A(n5923), .B(n5922), .Y(n5924) );
XOR2X1TS U2732 ( .A(n5903), .B(n5902), .Y(n5904) );
XOR2X1TS U2733 ( .A(n5882), .B(n5881), .Y(n5883) );
XOR2X1TS U2734 ( .A(n5862), .B(n5861), .Y(n5863) );
XNOR2X1TS U2735 ( .A(n5850), .B(n5849), .Y(n5851) );
NAND2X1TS U2736 ( .A(n817), .B(n5848), .Y(n5850) );
XOR2X1TS U2737 ( .A(n5841), .B(n5840), .Y(n5842) );
NAND2X1TS U2738 ( .A(n5839), .B(n5838), .Y(n5841) );
XOR2X1TS U2739 ( .A(n5829), .B(n5828), .Y(n5830) );
NAND2X1TS U2740 ( .A(n5827), .B(n5826), .Y(n5829) );
XNOR2X1TS U2741 ( .A(n5818), .B(n5817), .Y(n5819) );
XNOR2X1TS U2742 ( .A(n5799), .B(DP_OP_168J43_122_1342_n468), .Y(n5800) );
XNOR2X1TS U2743 ( .A(n5791), .B(DP_OP_168J43_122_1342_n467), .Y(n5793) );
XNOR2X1TS U2744 ( .A(n5783), .B(DP_OP_168J43_122_1342_n466), .Y(n5784) );
NAND2X1TS U2745 ( .A(n5781), .B(Sgf_operation_ODD1_Q_left[32]), .Y(n5782) );
XNOR2X1TS U2746 ( .A(n5772), .B(DP_OP_168J43_122_1342_n465), .Y(n5773) );
XNOR2X1TS U2747 ( .A(n5764), .B(DP_OP_168J43_122_1342_n464), .Y(n5765) );
NAND2X1TS U2748 ( .A(n5762), .B(Sgf_operation_ODD1_Q_left[34]), .Y(n5763) );
XNOR2X1TS U2749 ( .A(n5755), .B(DP_OP_168J43_122_1342_n463), .Y(n5756) );
INVX2TS U2750 ( .A(n5753), .Y(n5754) );
XNOR2X1TS U2751 ( .A(n5745), .B(DP_OP_168J43_122_1342_n462), .Y(n5746) );
NAND2X1TS U2752 ( .A(n5753), .B(Sgf_operation_ODD1_Q_left[36]), .Y(n5744) );
XNOR2X1TS U2753 ( .A(n5726), .B(DP_OP_168J43_122_1342_n460), .Y(n5727) );
NAND2X1TS U2754 ( .A(n5724), .B(Sgf_operation_ODD1_Q_left[38]), .Y(n5725) );
XNOR2X1TS U2755 ( .A(n5717), .B(DP_OP_168J43_122_1342_n459), .Y(n5718) );
INVX2TS U2756 ( .A(n5715), .Y(n5716) );
XNOR2X1TS U2757 ( .A(n5708), .B(DP_OP_168J43_122_1342_n458), .Y(n5709) );
NAND2X1TS U2758 ( .A(n5715), .B(Sgf_operation_ODD1_Q_left[40]), .Y(n5707) );
XNOR2X1TS U2759 ( .A(n5698), .B(DP_OP_168J43_122_1342_n457), .Y(n5699) );
XNOR2X1TS U2760 ( .A(n5690), .B(DP_OP_168J43_122_1342_n456), .Y(n5691) );
NAND2X1TS U2761 ( .A(n5688), .B(Sgf_operation_ODD1_Q_left[42]), .Y(n5689) );
XNOR2X1TS U2762 ( .A(n5681), .B(DP_OP_168J43_122_1342_n455), .Y(n5682) );
INVX2TS U2763 ( .A(n5679), .Y(n5680) );
XNOR2X1TS U2764 ( .A(n5672), .B(DP_OP_168J43_122_1342_n454), .Y(n5673) );
NAND2X1TS U2765 ( .A(n5679), .B(Sgf_operation_ODD1_Q_left[44]), .Y(n5671) );
CLKMX2X2TS U2766 ( .A(P_Sgf[101]), .B(n1424), .S0(n6202), .Y(n523) );
XNOR2X1TS U2767 ( .A(n1422), .B(n930), .Y(n1424) );
MX2X1TS U2768 ( .A(Exp_module_Data_S[8]), .B(exp_oper_result[8]), .S0(n6338),
.Y(n409) );
MX2X1TS U2769 ( .A(Exp_module_Data_S[7]), .B(exp_oper_result[7]), .S0(n6338),
.Y(n410) );
MX2X1TS U2770 ( .A(Exp_module_Data_S[9]), .B(exp_oper_result[9]), .S0(n6338),
.Y(n408) );
MX2X1TS U2771 ( .A(Exp_module_Data_S[10]), .B(exp_oper_result[10]), .S0(
n6338), .Y(n407) );
MX2X1TS U2772 ( .A(n5687), .B(Add_result[45]), .S0(n6394), .Y(n534) );
MX2X1TS U2773 ( .A(n5696), .B(Add_result[44]), .S0(n6394), .Y(n535) );
MX2X1TS U2774 ( .A(n5704), .B(Add_result[43]), .S0(n5835), .Y(n536) );
MX2X1TS U2775 ( .A(n5714), .B(Add_result[42]), .S0(n5835), .Y(n537) );
MX2X1TS U2776 ( .A(n5723), .B(Add_result[41]), .S0(n5835), .Y(n538) );
MX2X1TS U2777 ( .A(n5732), .B(Add_result[40]), .S0(n5835), .Y(n539) );
MX2X1TS U2778 ( .A(n5741), .B(Add_result[39]), .S0(n5835), .Y(n540) );
MX2X1TS U2779 ( .A(n5752), .B(Add_result[38]), .S0(n5835), .Y(n541) );
MX2X1TS U2780 ( .A(n5761), .B(Add_result[37]), .S0(n5835), .Y(n542) );
MX2X1TS U2781 ( .A(n5770), .B(Add_result[36]), .S0(n5835), .Y(n543) );
MX2X1TS U2782 ( .A(n5780), .B(Add_result[35]), .S0(n5835), .Y(n544) );
MX2X1TS U2783 ( .A(n5789), .B(Add_result[34]), .S0(n5835), .Y(n545) );
MX2X1TS U2784 ( .A(n5798), .B(Add_result[33]), .S0(n5835), .Y(n546) );
INVX2TS U2785 ( .A(n6129), .Y(n6115) );
XNOR2X1TS U2786 ( .A(n5658), .B(n5657), .Y(n5660) );
CLKMX2X2TS U2787 ( .A(P_Sgf[102]), .B(n1437), .S0(n6202), .Y(n524) );
XNOR2X1TS U2788 ( .A(n1436), .B(n927), .Y(n1437) );
INVX2TS U2789 ( .A(n1442), .Y(n1435) );
AO22XLTS U2790 ( .A0(n5613), .A1(Data_MX[63]), .B0(n5615), .B1(Op_MX[63]),
.Y(n645) );
MX2X1TS U2791 ( .A(P_Sgf[68]), .B(n5978), .S0(n6136), .Y(n489) );
MX2X1TS U2792 ( .A(P_Sgf[67]), .B(n5990), .S0(n6136), .Y(n488) );
MX2X1TS U2793 ( .A(P_Sgf[66]), .B(n6001), .S0(n6136), .Y(n487) );
NAND2X1TS U2794 ( .A(n1442), .B(Sgf_operation_ODD1_Q_left[48]), .Y(n1438) );
XNOR2X1TS U2795 ( .A(n1443), .B(n922), .Y(n1444) );
CLKMX2X2TS U2796 ( .A(P_Sgf[104]), .B(n1541), .S0(n6336), .Y(n520) );
XNOR2X1TS U2797 ( .A(n1540), .B(n924), .Y(n1541) );
XOR2XLTS U2798 ( .A(n4038), .B(n4037), .Y(Sgf_operation_ODD1_right_N4) );
XOR2XLTS U2799 ( .A(n3236), .B(n3235), .Y(Sgf_operation_ODD1_left_N4) );
XOR2XLTS U2800 ( .A(n4946), .B(n4945), .Y(Sgf_operation_ODD1_middle_N3) );
XOR2XLTS U2801 ( .A(n3231), .B(n3230), .Y(Sgf_operation_ODD1_left_N5) );
XOR2XLTS U2802 ( .A(n4033), .B(n4032), .Y(Sgf_operation_ODD1_right_N5) );
XOR2XLTS U2803 ( .A(n4022), .B(n4021), .Y(Sgf_operation_ODD1_right_N7) );
XOR2XLTS U2804 ( .A(n4938), .B(n4937), .Y(Sgf_operation_ODD1_middle_N5) );
XOR2XLTS U2805 ( .A(n3220), .B(n3219), .Y(Sgf_operation_ODD1_left_N7) );
XOR2XLTS U2806 ( .A(n4017), .B(n4016), .Y(Sgf_operation_ODD1_right_N8) );
XOR2XLTS U2807 ( .A(n4930), .B(n4929), .Y(Sgf_operation_ODD1_middle_N7) );
INVX2TS U2808 ( .A(n3153), .Y(n3155) );
INVX2TS U2809 ( .A(n3116), .Y(n3118) );
MX2X1TS U2810 ( .A(Exp_module_Data_S[11]), .B(exp_oper_result[11]), .S0(
n6338), .Y(n406) );
MX2X1TS U2811 ( .A(Exp_module_Overflow_flag_A), .B(n6340), .S0(n6339), .Y(
n405) );
NAND4BXLTS U2812 ( .AN(n6342), .B(Exp_module_Data_S[9]), .C(
Exp_module_Data_S[8]), .D(Exp_module_Data_S[7]), .Y(n6343) );
INVX2TS U2813 ( .A(n4821), .Y(n4823) );
OR2X1TS U2814 ( .A(n4637), .B(n4647), .Y(n742) );
OR2X1TS U2815 ( .A(n4540), .B(n4545), .Y(n743) );
BUFX3TS U2816 ( .A(n1620), .Y(n6582) );
XOR2X1TS U2817 ( .A(Op_MY[21]), .B(n769), .Y(n750) );
OR2X1TS U2818 ( .A(n1313), .B(Sgf_operation_ODD1_Q_left[1]), .Y(n752) );
XNOR2X1TS U2819 ( .A(n2243), .B(n3746), .Y(n754) );
OR2X1TS U2820 ( .A(n4536), .B(n4644), .Y(n755) );
CLKXOR2X2TS U2821 ( .A(n2145), .B(n2144), .Y(n756) );
NAND3X1TS U2822 ( .A(n2777), .B(n2776), .C(n2775), .Y(n757) );
NAND3X1TS U2823 ( .A(n2196), .B(n2195), .C(mult_x_23_n1930), .Y(n758) );
NAND2X1TS U2824 ( .A(n3313), .B(n3312), .Y(n760) );
CLKXOR2X2TS U2825 ( .A(n5091), .B(n5090), .Y(n761) );
CLKXOR2X2TS U2826 ( .A(n5005), .B(n5004), .Y(n762) );
NAND3X1TS U2827 ( .A(n5086), .B(n1845), .C(n1844), .Y(n763) );
OR2X1TS U2828 ( .A(n1539), .B(n924), .Y(n764) );
NOR2X1TS U2829 ( .A(n1593), .B(n6548), .Y(DP_OP_169J43_123_4229_n1331) );
CLKINVX3TS U2830 ( .A(n758), .Y(n3749) );
INVX2TS U2831 ( .A(n2691), .Y(n2693) );
NOR2X2TS U2832 ( .A(Op_MY[50]), .B(n6591), .Y(n2691) );
NAND3X2TS U2833 ( .A(n2087), .B(n6567), .C(n6536), .Y(n1630) );
NOR2X2TS U2834 ( .A(n2393), .B(n2392), .Y(n4013) );
NOR4X1TS U2835 ( .A(Op_MY[12]), .B(Op_MY[6]), .C(Op_MY[4]), .D(Op_MY[1]),
.Y(n6354) );
NOR4X1TS U2836 ( .A(Op_MX[13]), .B(Op_MX[7]), .C(n795), .D(Op_MX[5]), .Y(
n6378) );
NOR4X1TS U2837 ( .A(Op_MY[44]), .B(Op_MY[41]), .C(Op_MY[40]), .D(Op_MY[39]),
.Y(n6359) );
NOR4X1TS U2838 ( .A(n793), .B(Op_MX[15]), .C(Op_MX[12]), .D(Op_MX[8]), .Y(
n6379) );
NOR2X4TS U2839 ( .A(FS_Module_state_reg[3]), .B(n6347), .Y(n6392) );
NOR3XLTS U2840 ( .A(Op_MX[34]), .B(Op_MX[53]), .C(Op_MX[52]), .Y(n6381) );
INVX2TS U2841 ( .A(n6582), .Y(n765) );
INVX2TS U2842 ( .A(n765), .Y(n766) );
INVX4TS U2843 ( .A(n6544), .Y(n767) );
INVX2TS U2844 ( .A(n6592), .Y(n768) );
INVX2TS U2845 ( .A(n768), .Y(n769) );
INVX4TS U2846 ( .A(n768), .Y(n770) );
INVX2TS U2847 ( .A(n2321), .Y(n771) );
OR2X4TS U2848 ( .A(FSM_selector_B[1]), .B(n6559), .Y(n5608) );
BUFX3TS U2849 ( .A(n5992), .Y(n6180) );
BUFX3TS U2850 ( .A(n5992), .Y(n6168) );
BUFX3TS U2851 ( .A(n5992), .Y(n6157) );
BUFX3TS U2852 ( .A(n5992), .Y(n6138) );
NOR4X1TS U2853 ( .A(n794), .B(Op_MX[9]), .C(Op_MX[4]), .D(Op_MX[3]), .Y(
n6377) );
NAND2X1TS U2854 ( .A(n4690), .B(n3781), .Y(n2851) );
NOR2X2TS U2855 ( .A(n2848), .B(n2847), .Y(n4690) );
AOI222X1TS U2856 ( .A0(n3458), .A1(n3709), .B0(n3451), .B1(n3715), .C0(n3448), .C1(n3708), .Y(n3446) );
AOI222X1TS U2857 ( .A0(n3393), .A1(n3709), .B0(n3387), .B1(n3715), .C0(n3386), .C1(n3708), .Y(n3256) );
BUFX4TS U2858 ( .A(Op_MY[43]), .Y(n3709) );
INVX2TS U2859 ( .A(n739), .Y(n773) );
INVX2TS U2860 ( .A(n750), .Y(n774) );
INVX4TS U2861 ( .A(n6558), .Y(n4352) );
INVX4TS U2862 ( .A(n6560), .Y(n3454) );
INVX4TS U2863 ( .A(n6556), .Y(n3541) );
INVX2TS U2864 ( .A(n1587), .Y(n1589) );
NOR2X2TS U2865 ( .A(Op_MY[48]), .B(Op_MY[21]), .Y(n1587) );
INVX2TS U2866 ( .A(n6595), .Y(n775) );
INVX2TS U2867 ( .A(n775), .Y(n776) );
INVX4TS U2868 ( .A(n775), .Y(n777) );
NOR4X1TS U2869 ( .A(n6583), .B(n788), .C(n6588), .D(n3604), .Y(n6372) );
XNOR2X2TS U2870 ( .A(Op_MX[5]), .B(n6589), .Y(n2112) );
INVX2TS U2871 ( .A(n6593), .Y(n778) );
INVX2TS U2872 ( .A(n778), .Y(n779) );
INVX4TS U2873 ( .A(n778), .Y(n780) );
NOR4X1TS U2874 ( .A(Op_MX[47]), .B(n6587), .C(Op_MX[41]), .D(Op_MX[35]), .Y(
n6369) );
INVX2TS U2875 ( .A(n6596), .Y(n781) );
INVX2TS U2876 ( .A(n781), .Y(n782) );
INVX4TS U2877 ( .A(n781), .Y(n783) );
NOR4X1TS U2878 ( .A(Op_MX[19]), .B(Op_MX[14]), .C(n789), .D(Op_MX[1]), .Y(
n6380) );
NOR4X1TS U2879 ( .A(n783), .B(n803), .C(n767), .D(Op_MY[50]), .Y(n6352) );
BUFX3TS U2880 ( .A(n6631), .Y(n784) );
INVX3TS U2881 ( .A(rst), .Y(n6631) );
BUFX3TS U2882 ( .A(n1630), .Y(n1633) );
BUFX4TS U2883 ( .A(n1630), .Y(n6620) );
BUFX4TS U2884 ( .A(n1630), .Y(n6617) );
BUFX4TS U2885 ( .A(n6622), .Y(n6613) );
BUFX4TS U2886 ( .A(n6625), .Y(n6621) );
BUFX3TS U2887 ( .A(n6611), .Y(n785) );
BUFX3TS U2888 ( .A(n6625), .Y(n1632) );
BUFX4TS U2889 ( .A(n5649), .Y(n6013) );
BUFX4TS U2890 ( .A(n5649), .Y(n6041) );
BUFX4TS U2891 ( .A(n5649), .Y(n5774) );
XNOR2X2TS U2892 ( .A(n786), .B(Op_MX[23]), .Y(n2671) );
CLKXOR2X2TS U2893 ( .A(n786), .B(Op_MX[49]), .Y(n2777) );
NOR3XLTS U2894 ( .A(Op_MY[25]), .B(Op_MY[52]), .C(Op_MY[53]), .Y(n6361) );
NOR4X1TS U2895 ( .A(Op_MX[61]), .B(Op_MX[60]), .C(Op_MX[59]), .D(Op_MX[58]),
.Y(n6383) );
NOR2X2TS U2896 ( .A(n1485), .B(n1489), .Y(n2598) );
BUFX4TS U2897 ( .A(Op_MY[42]), .Y(n3715) );
NOR2X1TS U2898 ( .A(Op_MY[39]), .B(Op_MY[12]), .Y(n1485) );
BUFX4TS U2899 ( .A(Op_MX[3]), .Y(n4372) );
XNOR2X2TS U2900 ( .A(Op_MX[3]), .B(Op_MX[30]), .Y(n2144) );
XNOR2X2TS U2901 ( .A(Op_MX[13]), .B(Op_MX[40]), .Y(n5060) );
NOR4X1TS U2902 ( .A(Op_MX[46]), .B(Op_MX[40]), .C(Op_MX[28]), .D(Op_MX[30]),
.Y(n6374) );
NOR2X1TS U2903 ( .A(Op_MY[45]), .B(Op_MY[18]), .Y(n1559) );
XNOR2X2TS U2904 ( .A(Op_MY[18]), .B(n779), .Y(n2808) );
NOR4X1TS U2905 ( .A(Op_MY[18]), .B(Op_MY[15]), .C(Op_MY[9]), .D(Op_MY[7]),
.Y(n6355) );
XNOR2X2TS U2906 ( .A(Op_MX[28]), .B(Op_MX[1]), .Y(n2125) );
XNOR2X2TS U2907 ( .A(Op_MX[19]), .B(Op_MX[46]), .Y(n4997) );
CLKXOR2X2TS U2908 ( .A(Op_MY[10]), .B(n776), .Y(n2878) );
NOR4X1TS U2909 ( .A(Op_MY[21]), .B(Op_MY[19]), .C(Op_MY[13]), .D(Op_MY[10]),
.Y(n6356) );
BUFX4TS U2910 ( .A(Op_MY[45]), .Y(n3699) );
NOR4X1TS U2911 ( .A(Op_MY[46]), .B(Op_MY[45]), .C(Op_MY[43]), .D(Op_MY[42]),
.Y(n6358) );
NOR2X2TS U2912 ( .A(Op_MY[36]), .B(Op_MY[9]), .Y(n2622) );
BUFX4TS U2913 ( .A(Op_MY[31]), .Y(n3588) );
NOR4X1TS U2914 ( .A(Op_MY[36]), .B(Op_MY[35]), .C(Op_MY[32]), .D(Op_MY[31]),
.Y(n6350) );
BUFX4TS U2915 ( .A(Op_MY[47]), .Y(n3694) );
NOR4X1TS U2916 ( .A(Op_MY[0]), .B(Op_MY[49]), .C(Op_MY[48]), .D(Op_MY[47]),
.Y(n6357) );
OR2X2TS U2917 ( .A(n6590), .B(Op_MY[24]), .Y(n2737) );
NOR4X1TS U2918 ( .A(Op_MY[24]), .B(Op_MY[22]), .C(Op_MY[16]), .D(Op_MY[3]),
.Y(n6353) );
NOR2X2TS U2919 ( .A(Op_MY[40]), .B(Op_MY[13]), .Y(n1489) );
NOR2X2TS U2920 ( .A(Op_MY[49]), .B(Op_MY[22]), .Y(n2684) );
BUFX4TS U2921 ( .A(Op_MY[28]), .Y(n3360) );
NOR4X1TS U2922 ( .A(Op_MY[30]), .B(Op_MY[29]), .C(Op_MY[28]), .D(Op_MY[27]),
.Y(n6351) );
BUFX4TS U2923 ( .A(Op_MY[32]), .Y(n3654) );
BUFX4TS U2924 ( .A(Op_MY[32]), .Y(n3660) );
BUFX4TS U2925 ( .A(Op_MY[34]), .Y(n3748) );
BUFX4TS U2926 ( .A(Op_MY[34]), .Y(n3655) );
NOR4X1TS U2927 ( .A(Op_MY[38]), .B(Op_MY[37]), .C(Op_MY[34]), .D(Op_MY[33]),
.Y(n6360) );
NOR4X1TS U2928 ( .A(Op_MX[23]), .B(n792), .C(n791), .D(Op_MX[2]), .Y(n6371)
);
NOR4X1TS U2929 ( .A(Op_MX[49]), .B(Op_MX[43]), .C(Op_MX[37]), .D(Op_MX[33]),
.Y(n6376) );
NOR4X1TS U2930 ( .A(Op_MX[21]), .B(Op_MX[20]), .C(n790), .D(Op_MX[0]), .Y(
n6370) );
NOR4X1TS U2931 ( .A(Op_MX[48]), .B(Op_MX[42]), .C(Op_MX[36]), .D(Op_MX[31]),
.Y(n6375) );
OAI21X1TS U2932 ( .A0(n790), .A1(Op_MX[43]), .B0(Op_MX[15]), .Y(n1549) );
BUFX4TS U2933 ( .A(Op_MX[7]), .Y(n4644) );
XNOR2X2TS U2934 ( .A(Op_MX[7]), .B(Op_MX[34]), .Y(n5083) );
XNOR2X2TS U2935 ( .A(Op_MX[15]), .B(Op_MX[42]), .Y(n5026) );
BUFX4TS U2936 ( .A(Op_MX[15]), .Y(n4615) );
INVX2TS U2937 ( .A(n735), .Y(n788) );
INVX2TS U2938 ( .A(n748), .Y(n789) );
INVX2TS U2939 ( .A(n747), .Y(n790) );
INVX2TS U2940 ( .A(n738), .Y(n791) );
BUFX4TS U2941 ( .A(Op_MX[14]), .Y(n4607) );
INVX2TS U2942 ( .A(n749), .Y(n792) );
INVX2TS U2943 ( .A(n736), .Y(n793) );
BUFX4TS U2944 ( .A(Op_MX[19]), .Y(n4593) );
INVX2TS U2945 ( .A(n746), .Y(n794) );
BUFX4TS U2946 ( .A(Op_MX[13]), .Y(n4621) );
INVX2TS U2947 ( .A(n745), .Y(n795) );
NOR2X2TS U2948 ( .A(Op_MY[38]), .B(n776), .Y(n1518) );
XNOR2X2TS U2949 ( .A(Op_MY[12]), .B(n776), .Y(n2912) );
CLKXOR2X2TS U2950 ( .A(Op_MY[16]), .B(n779), .Y(n2963) );
AOI21X1TS U2951 ( .A0(n2396), .A1(n4007), .B0(n2395), .Y(n3999) );
AOI21X2TS U2952 ( .A0(n2537), .A1(n2536), .B0(n2535), .Y(n3957) );
AOI21X1TS U2953 ( .A0(n4932), .A1(n869), .B0(n2180), .Y(n4929) );
OAI31X1TS U2954 ( .A0(n6585), .A1(n2088), .A2(n6535), .B0(n1658), .Y(n712)
);
INVX2TS U2955 ( .A(n5969), .Y(n6045) );
NAND2X1TS U2956 ( .A(n5625), .B(n6058), .Y(n5969) );
NOR4X1TS U2957 ( .A(Op_MX[45]), .B(Op_MX[39]), .C(Op_MX[27]), .D(n6584), .Y(
n6373) );
BUFX3TS U2958 ( .A(n6627), .Y(n796) );
BUFX3TS U2959 ( .A(n6627), .Y(n797) );
BUFX3TS U2960 ( .A(n6617), .Y(n1631) );
NOR2X2TS U2961 ( .A(DP_OP_169J43_123_4229_n1295), .B(
DP_OP_169J43_123_4229_n1299), .Y(n4919) );
NOR2X2TS U2962 ( .A(Op_MY[42]), .B(Op_MY[15]), .Y(n2610) );
BUFX4TS U2963 ( .A(n6538), .Y(n5098) );
NAND2X1TS U2964 ( .A(n1186), .B(Sgf_operation_ODD1_Q_right[38]), .Y(n6323)
);
INVX2TS U2965 ( .A(Sgf_operation_ODD1_Q_right[38]), .Y(n932) );
NOR2X2TS U2966 ( .A(n2264), .B(n2263), .Y(n3227) );
NOR2X2TS U2967 ( .A(mult_x_24_n899), .B(mult_x_24_n905), .Y(n3992) );
OAI22X2TS U2968 ( .A0(beg_FSM), .A1(n6625), .B0(ack_FSM), .B1(n2094), .Y(
n6345) );
BUFX4TS U2969 ( .A(n6610), .Y(n6630) );
NOR2X2TS U2970 ( .A(Op_MY[46]), .B(Op_MY[19]), .Y(n1571) );
NOR2X2TS U2971 ( .A(n1685), .B(n1684), .Y(n2884) );
INVX2TS U2972 ( .A(n2620), .Y(n1935) );
NOR2X2TS U2973 ( .A(Op_MY[35]), .B(n782), .Y(n2620) );
NOR2X2TS U2974 ( .A(Op_MY[43]), .B(Op_MY[16]), .Y(n2465) );
NOR2XLTS U2975 ( .A(n4029), .B(n4024), .Y(n2384) );
NOR2X2TS U2976 ( .A(n2380), .B(n2379), .Y(n4029) );
NOR2X2TS U2977 ( .A(mult_x_24_n916), .B(n2394), .Y(n4008) );
NOR2XLTS U2978 ( .A(n3222), .B(n3227), .Y(n2268) );
NOR2X2TS U2979 ( .A(n2266), .B(n2265), .Y(n3222) );
OAI21XLTS U2980 ( .A0(n4141), .A1(n2327), .B0(n2361), .Y(n2362) );
OAI21XLTS U2981 ( .A0(n2946), .A1(n2327), .B0(n843), .Y(n2364) );
NOR2X2TS U2982 ( .A(n1692), .B(n1691), .Y(n2760) );
NOR2X2TS U2983 ( .A(n1670), .B(n1669), .Y(n2058) );
XNOR2X2TS U2984 ( .A(Op_MX[9]), .B(Op_MX[36]), .Y(n5090) );
XNOR2X2TS U2985 ( .A(Op_MX[21]), .B(Op_MX[48]), .Y(n5004) );
OAI21X2TS U2986 ( .A0(n1997), .A1(n1683), .B0(n1682), .Y(n1939) );
NOR2X2TS U2987 ( .A(n2040), .B(n1679), .Y(n1997) );
OAI21X2TS U2988 ( .A0(n4082), .A1(n1668), .B0(n1667), .Y(n4068) );
NOR2X2TS U2989 ( .A(n2029), .B(n1664), .Y(n4082) );
NOR4X1TS U2990 ( .A(Op_MX[26]), .B(n6586), .C(Op_MX[29]), .D(Op_MX[62]), .Y(
n6382) );
NOR2XLTS U2991 ( .A(FSM_selector_B[1]), .B(Op_MY[52]), .Y(n5609) );
BUFX4TS U2992 ( .A(n1609), .Y(n3317) );
NOR2X6TS U2993 ( .A(n6336), .B(n6392), .Y(n6338) );
NOR2X2TS U2994 ( .A(n5638), .B(FSM_selector_C), .Y(n5661) );
NAND2X2TS U2995 ( .A(n5630), .B(n6585), .Y(n5638) );
BUFX4TS U2996 ( .A(n5637), .Y(n6184) );
BUFX4TS U2997 ( .A(n6583), .Y(n4557) );
BUFX4TS U2998 ( .A(Op_MY[50]), .Y(n3678) );
BUFX4TS U2999 ( .A(Op_MY[37]), .Y(n3743) );
BUFX4TS U3000 ( .A(Op_MY[35]), .Y(n3750) );
BUFX4TS U3001 ( .A(Op_MY[39]), .Y(n3732) );
BUFX4TS U3002 ( .A(Op_MY[48]), .Y(n3688) );
BUFX4TS U3003 ( .A(Op_MY[44]), .Y(n3704) );
BUFX4TS U3004 ( .A(Op_MY[41]), .Y(n3721) );
BUFX4TS U3005 ( .A(Op_MY[33]), .Y(n3662) );
BUFX4TS U3006 ( .A(Op_MY[30]), .Y(n3596) );
INVX3TS U3007 ( .A(n1634), .Y(n6394) );
INVX4TS U3008 ( .A(n6545), .Y(n4164) );
INVX4TS U3009 ( .A(n6564), .Y(n4242) );
INVX4TS U3010 ( .A(n6553), .Y(n3637) );
INVX4TS U3011 ( .A(n6554), .Y(n4464) );
INVX4TS U3012 ( .A(n6566), .Y(n3389) );
BUFX4TS U3013 ( .A(Op_MY[46]), .Y(n3693) );
BUFX4TS U3014 ( .A(Op_MY[49]), .Y(n3683) );
BUFX4TS U3015 ( .A(Op_MY[40]), .Y(n3713) );
BUFX4TS U3016 ( .A(Op_MY[40]), .Y(n3726) );
BUFX4TS U3017 ( .A(Op_MY[38]), .Y(n3725) );
BUFX4TS U3018 ( .A(Op_MY[38]), .Y(n3738) );
BUFX4TS U3019 ( .A(Op_MY[36]), .Y(n3737) );
BUFX4TS U3020 ( .A(Op_MY[36]), .Y(n3752) );
BUFX4TS U3021 ( .A(Op_MY[29]), .Y(n3587) );
INVX2TS U3022 ( .A(n6565), .Y(n798) );
CLKBUFX2TS U3023 ( .A(n6594), .Y(n799) );
BUFX4TS U3024 ( .A(n6594), .Y(n800) );
CLKBUFX2TS U3025 ( .A(n6597), .Y(n801) );
CLKBUFX2TS U3026 ( .A(n6597), .Y(n802) );
CLKBUFX2TS U3027 ( .A(n6597), .Y(n803) );
CLKBUFX2TS U3028 ( .A(n6597), .Y(n804) );
CLKBUFX2TS U3029 ( .A(n6588), .Y(n805) );
CLKBUFX2TS U3030 ( .A(n6587), .Y(n807) );
BUFX4TS U3031 ( .A(Op_MX[20]), .Y(n4588) );
BUFX4TS U3032 ( .A(Op_MX[23]), .Y(n4573) );
BUFX4TS U3033 ( .A(Op_MX[4]), .Y(n4545) );
BUFX4TS U3034 ( .A(Op_MX[8]), .Y(n4637) );
BUFX4TS U3035 ( .A(Op_MX[5]), .Y(n4540) );
BUFX4TS U3036 ( .A(Op_MX[1]), .Y(n4158) );
XOR2X1TS U3037 ( .A(n809), .B(DP_OP_168J43_122_1342_n469), .Y(n5807) );
CLKXOR2X2TS U3038 ( .A(n5032), .B(n5024), .Y(n811) );
CLKXOR2X2TS U3039 ( .A(n5083), .B(n5082), .Y(n812) );
INVX2TS U3040 ( .A(Sgf_operation_ODD1_Q_left[46]), .Y(n5657) );
OR2X2TS U3041 ( .A(n1317), .B(Sgf_operation_ODD1_Q_left[4]), .Y(n814) );
OR2X1TS U3042 ( .A(n1362), .B(Sgf_operation_ODD1_Q_left[11]), .Y(n815) );
OR2X1TS U3043 ( .A(n1381), .B(Sgf_operation_ODD1_Q_left[16]), .Y(n822) );
OR2X1TS U3044 ( .A(n1372), .B(Sgf_operation_ODD1_Q_left[14]), .Y(n823) );
CLKAND2X2TS U3045 ( .A(n5742), .B(n1421), .Y(n829) );
OR2X1TS U3046 ( .A(n3360), .B(n3587), .Y(n830) );
CLKXOR2X4TS U3047 ( .A(n2218), .B(n2217), .Y(n831) );
AOI22X1TS U3048 ( .A0(n3393), .A1(n3360), .B0(n3399), .B1(n3312), .Y(n832)
);
CLKAND2X2TS U3049 ( .A(n856), .B(n3756), .Y(n833) );
OR2X1TS U3050 ( .A(n2129), .B(n2128), .Y(n837) );
INVX2TS U3051 ( .A(Sgf_operation_ODD1_Q_left[50]), .Y(n924) );
INVX2TS U3052 ( .A(Sgf_operation_ODD1_Q_left[48]), .Y(n927) );
INVX2TS U3053 ( .A(Sgf_operation_ODD1_Q_left[51]), .Y(n922) );
OR2X1TS U3054 ( .A(n4485), .B(n4158), .Y(n838) );
AOI22X1TS U3055 ( .A0(n4415), .A1(n4159), .B0(n4418), .B1(n4158), .Y(n839)
);
AOI22X1TS U3056 ( .A0(n4304), .A1(n4139), .B0(n4307), .B1(n4158), .Y(n840)
);
AOI22X1TS U3057 ( .A0(n4466), .A1(n4159), .B0(n4469), .B1(n4158), .Y(n841)
);
AOI22X1TS U3058 ( .A0(n729), .A1(n4159), .B0(n4527), .B1(n4158), .Y(n842) );
AOI22X1TS U3059 ( .A0(n4627), .A1(n4158), .B0(n4620), .B1(n4139), .Y(n843)
);
AOI22X1TS U3060 ( .A0(n4354), .A1(n4139), .B0(n4357), .B1(n4158), .Y(n844)
);
AOI22X1TS U3061 ( .A0(n4244), .A1(n4139), .B0(n4247), .B1(n4158), .Y(n845)
);
INVX2TS U3062 ( .A(Sgf_operation_ODD1_Q_left[47]), .Y(n930) );
OR2X1TS U3063 ( .A(n5667), .B(n1420), .Y(n846) );
XNOR2X4TS U3064 ( .A(n1742), .B(n3670), .Y(n847) );
XNOR2X1TS U3065 ( .A(n2362), .B(n4635), .Y(n848) );
AOI22X1TS U3066 ( .A0(n3412), .A1(n3360), .B0(n3425), .B1(n3351), .Y(n849)
);
OR2X1TS U3067 ( .A(DP_OP_168J43_122_1342_n466), .B(
DP_OP_168J43_122_1342_n467), .Y(n850) );
AOI22X1TS U3068 ( .A0(n3458), .A1(n3360), .B0(n3472), .B1(n3312), .Y(n851)
);
AOI22X1TS U3069 ( .A0(n3488), .A1(n3360), .B0(n3507), .B1(n3351), .Y(n852)
);
AOI22X1TS U3070 ( .A0(n3545), .A1(n3360), .B0(n3559), .B1(n3351), .Y(n853)
);
AOI22X1TS U3071 ( .A0(n3569), .A1(n3360), .B0(n3595), .B1(n3351), .Y(n854)
);
AOI22X1TS U3072 ( .A0(n3661), .A1(n3312), .B0(n3641), .B1(n3360), .Y(n855)
);
OA21XLTS U3073 ( .A0(n2236), .A1(n6546), .B0(n892), .Y(n856) );
AOI22X1TS U3074 ( .A0(n3733), .A1(n3360), .B0(n3751), .B1(n3351), .Y(n857)
);
AOI22X1TS U3075 ( .A0(n4161), .A1(n4139), .B0(n4162), .B1(n4158), .Y(n861)
);
AOI22X1TS U3076 ( .A0(n4195), .A1(n4139), .B0(n4198), .B1(n4158), .Y(n863)
);
OR2X1TS U3077 ( .A(DP_OP_169J43_123_4229_n1305), .B(n2179), .Y(n869) );
OR2X1TS U3078 ( .A(n6269), .B(Sgf_operation_ODD1_Q_right[27]), .Y(n870) );
CLKAND2X2TS U3079 ( .A(n870), .B(n6273), .Y(n871) );
OR2X1TS U3080 ( .A(n3587), .B(n3582), .Y(n872) );
CLKXOR2X4TS U3081 ( .A(n2283), .B(n2282), .Y(n873) );
OR2X1TS U3082 ( .A(n1169), .B(Sgf_operation_ODD1_Q_right[32]), .Y(n874) );
CLKXOR2X2TS U3083 ( .A(n5027), .B(n5026), .Y(n876) );
OR2X1TS U3084 ( .A(n1155), .B(Sgf_operation_ODD1_Q_right[30]), .Y(n877) );
OR2X1TS U3085 ( .A(mult_x_24_n911), .B(mult_x_24_n915), .Y(n878) );
OR2X1TS U3086 ( .A(mult_x_24_n906), .B(mult_x_24_n910), .Y(n879) );
OR2X1TS U3087 ( .A(n1153), .B(Sgf_operation_ODD1_Q_right[29]), .Y(n880) );
OR2X1TS U3088 ( .A(Sgf_operation_ODD1_Q_middle[0]), .B(
DP_OP_168J43_122_1342_n447), .Y(n888) );
CLKXOR2X2TS U3089 ( .A(n5055), .B(n5054), .Y(n889) );
OR2X1TS U3090 ( .A(DP_OP_169J43_123_4229_n1282), .B(
DP_OP_169J43_123_4229_n1287), .Y(n891) );
NAND2X1TS U3091 ( .A(n2245), .B(n3312), .Y(n892) );
NAND3X1TS U3092 ( .A(n5000), .B(n1745), .C(n1744), .Y(n893) );
NAND3X1TS U3093 ( .A(n2210), .B(n2209), .C(n2208), .Y(n894) );
OR2X1TS U3094 ( .A(n2155), .B(n2154), .Y(n895) );
CLKXOR2X2TS U3095 ( .A(n2112), .B(n2104), .Y(n896) );
CLKXOR2X2TS U3096 ( .A(n5060), .B(n5052), .Y(n897) );
NAND3X1TS U3097 ( .A(n2591), .B(n1840), .C(n1839), .Y(n899) );
CLKXOR2X2TS U3098 ( .A(n2671), .B(n2670), .Y(n900) );
OR2X1TS U3099 ( .A(n2295), .B(n2294), .Y(n906) );
OR2X1TS U3100 ( .A(mult_x_23_n831), .B(n2297), .Y(n907) );
NOR2X1TS U3101 ( .A(n1969), .B(n1971), .Y(n1448) );
INVX2TS U3102 ( .A(n1489), .Y(n1491) );
NOR2X1TS U3103 ( .A(n1857), .B(n2167), .Y(n1963) );
NOR2X1TS U3104 ( .A(n2878), .B(n2876), .Y(n2937) );
AOI21X1TS U3105 ( .A0(n1477), .A1(n1458), .B0(n1457), .Y(n1459) );
NOR2X2TS U3106 ( .A(n4583), .B(n4578), .Y(n1755) );
NAND2X1TS U3107 ( .A(n3737), .B(n3731), .Y(n2789) );
NOR2X1TS U3108 ( .A(n3674), .B(n3609), .Y(n1781) );
INVX2TS U3109 ( .A(n1857), .Y(n2165) );
NOR2X1TS U3110 ( .A(n2318), .B(n2317), .Y(n2314) );
OAI21X1TS U3111 ( .A0(n2653), .A1(n1605), .B0(n1604), .Y(n1864) );
NOR2X1TS U3112 ( .A(n5086), .B(n1845), .Y(n2188) );
INVX2TS U3113 ( .A(n1716), .Y(n2653) );
NAND2X1TS U3114 ( .A(n1066), .B(n996), .Y(n998) );
NOR2X1TS U3115 ( .A(n1707), .B(n1865), .Y(n1710) );
NAND2X1TS U3116 ( .A(n3670), .B(n3674), .Y(n1749) );
NOR2X1TS U3117 ( .A(n1829), .B(n1831), .Y(n1718) );
AOI21X1TS U3118 ( .A0(n2255), .A1(n2230), .B0(n2229), .Y(n2278) );
BUFX4TS U3119 ( .A(n1510), .Y(n5573) );
BUFX4TS U3120 ( .A(Op_MY[42]), .Y(n3703) );
NAND2X1TS U3121 ( .A(n5339), .B(n2594), .Y(n4951) );
INVX4TS U3122 ( .A(n5008), .Y(n5263) );
BUFX4TS U3123 ( .A(n1576), .Y(n5563) );
NAND2X1TS U3124 ( .A(n858), .B(n1729), .Y(n1730) );
BUFX4TS U3125 ( .A(Op_MX[12]), .Y(n4626) );
OAI21X1TS U3126 ( .A0(n2713), .A1(n1740), .B0(n1739), .Y(n1751) );
BUFX4TS U3127 ( .A(Op_MY[31]), .Y(n3658) );
OAI21XLTS U3128 ( .A0(n831), .A1(n3562), .B0(n3361), .Y(n3362) );
BUFX4TS U3129 ( .A(n2627), .Y(n5583) );
OAI21XLTS U3130 ( .A0(n3666), .A1(n3562), .B0(n3561), .Y(n3563) );
ADDHXLTS U3131 ( .A(n5041), .B(n5040), .CO(DP_OP_169J43_123_4229_n1221), .S(
n5048) );
ADDHXLTS U3132 ( .A(n4988), .B(n4987), .CO(n4992), .S(
DP_OP_169J43_123_4229_n1138) );
INVX2TS U3133 ( .A(n1140), .Y(n1142) );
INVX2TS U3134 ( .A(n1129), .Y(n1131) );
INVX2TS U3135 ( .A(n1103), .Y(n1105) );
INVX2TS U3136 ( .A(n1087), .Y(n1197) );
INVX2TS U3137 ( .A(n1070), .Y(n1072) );
NAND2X1TS U3138 ( .A(n1000), .B(n999), .Y(n1303) );
AOI21X2TS U3139 ( .A0(n1306), .A1(n1267), .B0(n1266), .Y(n1280) );
INVX2TS U3140 ( .A(Sgf_operation_ODD1_Q_left[49]), .Y(n926) );
NAND2X1TS U3141 ( .A(n1496), .B(n1495), .Y(n1524) );
BUFX4TS U3142 ( .A(n2733), .Y(n5204) );
CMPR42X1TS U3143 ( .A(DP_OP_169J43_123_4229_n1481), .B(
DP_OP_169J43_123_4229_n1705), .C(DP_OP_169J43_123_4229_n1537), .D(
DP_OP_169J43_123_4229_n1022), .ICI(DP_OP_169J43_123_4229_n1016), .S(
DP_OP_169J43_123_4229_n999), .ICO(DP_OP_169J43_123_4229_n997), .CO(
DP_OP_169J43_123_4229_n998) );
INVX2TS U3144 ( .A(n1836), .Y(n3623) );
INVX2TS U3145 ( .A(n1116), .Y(n1163) );
NAND2X1TS U3146 ( .A(n1113), .B(n1112), .Y(n1114) );
NAND2X1TS U3147 ( .A(n1208), .B(n1207), .Y(n1209) );
NAND2X1TS U3148 ( .A(n1304), .B(n1303), .Y(n1305) );
NAND2X1TS U3149 ( .A(n1262), .B(n1342), .Y(n1263) );
CMPR42X1TS U3150 ( .A(DP_OP_169J43_123_4229_n1101), .B(
DP_OP_169J43_123_4229_n1541), .C(DP_OP_169J43_123_4229_n1513), .D(
DP_OP_169J43_123_4229_n1597), .ICI(DP_OP_169J43_123_4229_n1092), .S(
DP_OP_169J43_123_4229_n1082), .ICO(DP_OP_169J43_123_4229_n1080), .CO(
DP_OP_169J43_123_4229_n1081) );
INVX2TS U3151 ( .A(n2187), .Y(n3353) );
ADDHXLTS U3152 ( .A(n5105), .B(n5104), .CO(n5109), .S(
DP_OP_169J43_123_4229_n1302) );
NAND2X1TS U3153 ( .A(n3767), .B(n3758), .Y(n3769) );
CMPR42X1TS U3154 ( .A(mult_x_24_n1410), .B(mult_x_24_n1545), .C(
mult_x_24_n1437), .D(mult_x_24_n1491), .ICI(mult_x_24_n751), .S(
mult_x_24_n741), .ICO(mult_x_24_n739), .CO(mult_x_24_n740) );
CMPR42X1TS U3155 ( .A(DP_OP_169J43_123_4229_n1043), .B(
DP_OP_169J43_123_4229_n1650), .C(DP_OP_169J43_123_4229_n1594), .D(
DP_OP_169J43_123_4229_n1622), .ICI(DP_OP_169J43_123_4229_n1024), .S(
DP_OP_169J43_123_4229_n1018), .ICO(DP_OP_169J43_123_4229_n1016), .CO(
DP_OP_169J43_123_4229_n1017) );
CMPR42X1TS U3156 ( .A(mult_x_24_n1352), .B(mult_x_24_n706), .C(
mult_x_24_n1406), .D(mult_x_24_n1433), .ICI(mult_x_24_n703), .S(
mult_x_24_n693), .ICO(mult_x_24_n691), .CO(mult_x_24_n692) );
XOR2X1TS U3157 ( .A(n1175), .B(n1174), .Y(n1176) );
NOR2X2TS U3158 ( .A(n1186), .B(Sgf_operation_ODD1_Q_right[38]), .Y(n6322) );
CMPR42X1TS U3159 ( .A(DP_OP_169J43_123_4229_n1472), .B(
DP_OP_169J43_123_4229_n1444), .C(DP_OP_169J43_123_4229_n853), .D(
DP_OP_169J43_123_4229_n840), .ICI(DP_OP_169J43_123_4229_n850), .S(
DP_OP_169J43_123_4229_n834), .ICO(DP_OP_169J43_123_4229_n832), .CO(
DP_OP_169J43_123_4229_n833) );
CMPR42X1TS U3160 ( .A(DP_OP_169J43_123_4229_n1081), .B(
DP_OP_169J43_123_4229_n1062), .C(DP_OP_169J43_123_4229_n1078), .D(
DP_OP_169J43_123_4229_n1075), .ICI(DP_OP_169J43_123_4229_n1071), .S(
DP_OP_169J43_123_4229_n1053), .ICO(DP_OP_169J43_123_4229_n1051), .CO(
DP_OP_169J43_123_4229_n1052) );
AOI21X1TS U3161 ( .A0(n4777), .A1(n4667), .B0(n4666), .Y(n4745) );
NAND2X1TS U3162 ( .A(n4778), .B(n4667), .Y(n4744) );
OAI21XLTS U3163 ( .A0(n3353), .A1(n2236), .B0(n2242), .Y(n2243) );
NAND2X1TS U3164 ( .A(n2441), .B(n3128), .Y(n2443) );
NAND2X1TS U3165 ( .A(n2515), .B(n4820), .Y(n2517) );
NAND2X1TS U3166 ( .A(n2559), .B(n2554), .Y(n3759) );
NOR2X1TS U3167 ( .A(DP_OP_169J43_123_4229_n1088), .B(
DP_OP_169J43_123_4229_n1106), .Y(n4831) );
OAI21XLTS U3168 ( .A0(FSM_selector_B[0]), .A1(n5609), .B0(n5608), .Y(n5610)
);
INVX2TS U3169 ( .A(n6270), .Y(n6272) );
INVX2TS U3170 ( .A(n6289), .Y(n1170) );
INVX2TS U3171 ( .A(n6319), .Y(n6320) );
INVX2TS U3172 ( .A(n6261), .Y(n6263) );
NAND2X1TS U3173 ( .A(n1349), .B(Sgf_operation_ODD1_Q_left[7]), .Y(n6063) );
OAI21X2TS U3174 ( .A0(n6084), .A1(n1328), .B0(n1327), .Y(n6032) );
NAND2X1TS U3175 ( .A(n4764), .B(n4760), .Y(n4673) );
CMPR42X1TS U3176 ( .A(mult_x_24_n628), .B(mult_x_24_n619), .C(mult_x_24_n625), .D(mult_x_24_n617), .ICI(mult_x_24_n621), .S(mult_x_24_n614), .ICO(
mult_x_24_n612), .CO(mult_x_24_n613) );
NOR2X1TS U3177 ( .A(n4744), .B(n4676), .Y(n4739) );
AOI21X1TS U3178 ( .A0(n2422), .A1(n2421), .B0(n2420), .Y(n3973) );
NAND2X1TS U3179 ( .A(n753), .B(n4890), .Y(n4879) );
NOR2X1TS U3180 ( .A(n3923), .B(n3927), .Y(n3912) );
INVX2TS U3181 ( .A(n4845), .Y(n4847) );
NOR2X1TS U3182 ( .A(n3141), .B(n3139), .Y(n3128) );
INVX2TS U3183 ( .A(n3129), .Y(n3131) );
NAND2X1TS U3184 ( .A(DP_OP_169J43_123_4229_n967), .B(
DP_OP_169J43_123_4229_n986), .Y(n4804) );
INVX2TS U3185 ( .A(n4808), .Y(n4810) );
OAI21X1TS U3186 ( .A0(n4817), .A1(n4654), .B0(n4662), .Y(n2570) );
NOR2XLTS U3187 ( .A(n6346), .B(P_Sgf[105]), .Y(n2086) );
NAND2X1TS U3188 ( .A(n6245), .B(n6248), .Y(n6246) );
INVX2TS U3189 ( .A(n6189), .Y(n6242) );
NAND2X1TS U3190 ( .A(n752), .B(n6144), .Y(n6145) );
NAND2X1TS U3191 ( .A(n5880), .B(n5879), .Y(n5882) );
NOR2XLTS U3192 ( .A(n6102), .B(n6572), .Y(n6082) );
AOI21X1TS U3193 ( .A0(n4799), .A1(n4778), .B0(n4777), .Y(n4788) );
AOI21X1TS U3194 ( .A0(n4940), .A1(n895), .B0(n2156), .Y(n4937) );
INVX2TS U3195 ( .A(n2583), .Y(n2647) );
OAI21X1TS U3196 ( .A0(n4817), .A1(n2527), .B0(n2526), .Y(n4807) );
AOI21X2TS U3197 ( .A0(n3059), .A1(n3057), .B0(n2992), .Y(n3055) );
NOR2XLTS U3198 ( .A(n2084), .B(underflow_flag), .Y(n2085) );
XOR2XLTS U3199 ( .A(n6313), .B(n6312), .Y(n6314) );
XOR2X1TS U3200 ( .A(n6023), .B(n6022), .Y(n6024) );
XNOR2X1TS U3201 ( .A(n5871), .B(n5870), .Y(n5872) );
XNOR2X1TS U3202 ( .A(n5734), .B(DP_OP_168J43_122_1342_n461), .Y(n5735) );
XNOR2X1TS U3203 ( .A(n1439), .B(n926), .Y(n1440) );
ADDHXLTS U3204 ( .A(Sgf_normalized_result[51]), .B(n5633), .CO(n6186), .S(
n5634) );
OR2X1TS U3334 ( .A(Op_MY[27]), .B(Op_MY[0]), .Y(n908) );
NAND2X1TS U3335 ( .A(Op_MY[27]), .B(Op_MY[0]), .Y(n1624) );
INVX4TS U3336 ( .A(n6563), .Y(n3429) );
XNOR2X2TS U3337 ( .A(n3429), .B(Op_MX[48]), .Y(n2776) );
INVX4TS U3338 ( .A(n6546), .Y(n3312) );
NAND2X1TS U3339 ( .A(n3393), .B(n3312), .Y(n909) );
XOR2X1TS U3340 ( .A(n910), .B(n3389), .Y(n1619) );
XNOR2X2TS U3341 ( .A(Op_MY[9]), .B(n782), .Y(n2876) );
BUFX4TS U3342 ( .A(n2937), .Y(n4418) );
INVX4TS U3343 ( .A(n6547), .Y(n4159) );
NAND2X1TS U3344 ( .A(n4418), .B(n4159), .Y(n911) );
INVX4TS U3345 ( .A(n6555), .Y(n4413) );
XOR2X1TS U3346 ( .A(n912), .B(n4413), .Y(n918) );
INVX4TS U3347 ( .A(n6550), .Y(n3600) );
XNOR2X2TS U3348 ( .A(n3600), .B(Op_MX[36]), .Y(n2717) );
CLKXOR2X2TS U3349 ( .A(n805), .B(Op_MX[37]), .Y(n2718) );
NAND2X1TS U3350 ( .A(n3545), .B(n3312), .Y(n913) );
XOR2X1TS U3351 ( .A(n914), .B(n3541), .Y(n1543) );
NAND2X2TS U3352 ( .A(n915), .B(n2311), .Y(n2946) );
BUFX4TS U3353 ( .A(n916), .Y(n4435) );
XNOR2X1TS U3354 ( .A(Op_MY[9]), .B(Op_MY[10]), .Y(n2877) );
NOR2BX1TS U3355 ( .AN(n2876), .B(n2877), .Y(n2938) );
BUFX4TS U3356 ( .A(n2938), .Y(n4415) );
XOR2X1TS U3357 ( .A(n917), .B(n4413), .Y(n4138) );
ADDHXLTS U3358 ( .A(n777), .B(n918), .CO(n4137), .S(mult_x_24_n918) );
XOR2X1TS U3359 ( .A(Op_MX[27]), .B(Op_MX[0]), .Y(DP_OP_169J43_123_4229_n2318) );
XNOR2X1TS U3360 ( .A(n919), .B(Sgf_operation_ODD1_Q_middle[53]), .Y(n1040)
);
INVX2TS U3361 ( .A(Sgf_operation_ODD1_Q_right[51]), .Y(n921) );
NOR2X2TS U3362 ( .A(n944), .B(n943), .Y(n1164) );
NOR2X2TS U3363 ( .A(n936), .B(n935), .Y(n1140) );
NOR2X2TS U3364 ( .A(n938), .B(n937), .Y(n1135) );
NOR2X1TS U3365 ( .A(n1140), .B(n1135), .Y(n940) );
NAND2X1TS U3366 ( .A(Sgf_operation_ODD1_Q_middle[0]), .B(
DP_OP_168J43_122_1342_n447), .Y(n1150) );
INVX2TS U3367 ( .A(n1150), .Y(n933) );
NAND2X1TS U3368 ( .A(n934), .B(DP_OP_168J43_122_1342_n498), .Y(n1146) );
OAI21X2TS U3369 ( .A0(n1148), .A1(n1145), .B0(n1146), .Y(n1134) );
NAND2X1TS U3370 ( .A(n936), .B(n935), .Y(n1141) );
NAND2X1TS U3371 ( .A(n942), .B(n941), .Y(n1160) );
OAI21X2TS U3372 ( .A0(n1164), .A1(n1160), .B0(n1165), .Y(n1117) );
NOR2X2TS U3373 ( .A(n954), .B(n953), .Y(n1129) );
NAND2X1TS U3374 ( .A(n954), .B(n953), .Y(n1130) );
NAND2X1TS U3375 ( .A(n978), .B(n977), .Y(n1223) );
AFHCONX2TS U3376 ( .A(Sgf_operation_ODD1_Q_middle[54]), .B(n1038), .CI(n1037), .CON(n1036), .S(n1413) );
AFHCINX2TS U3377 ( .CIN(n1039), .B(n1040), .A(n1041), .S(n1411), .CO(n1037)
);
AFHCINX2TS U3378 ( .CIN(n1042), .B(n1043), .A(n1044), .S(n1405), .CO(n1407)
);
AFHCINX2TS U3379 ( .CIN(n1045), .B(n1046), .A(n1047), .S(n1399), .CO(n1401)
);
AFHCINX2TS U3380 ( .CIN(n1048), .B(n1049), .A(n1050), .S(n1393), .CO(n1395)
);
AFHCINX2TS U3381 ( .CIN(n1051), .B(n1052), .A(n1053), .S(n1387), .CO(n1389)
);
AFHCONX2TS U3382 ( .A(n1056), .B(n1055), .CI(n1054), .CON(n1369), .S(n1365)
);
AFHCINX2TS U3383 ( .CIN(n1057), .B(n1058), .A(n1059), .S(n1364), .CO(n1054)
);
NAND2X1TS U3384 ( .A(n816), .B(n824), .Y(n1368) );
INVX2TS U3385 ( .A(n1061), .Y(n1064) );
INVX2TS U3386 ( .A(n1062), .Y(n1063) );
INVX2TS U3387 ( .A(n1069), .Y(n1079) );
INVX2TS U3388 ( .A(n1244), .Y(n1067) );
NAND2X1TS U3389 ( .A(n1067), .B(n1243), .Y(n1068) );
NAND2X1TS U3390 ( .A(n1072), .B(n1071), .Y(n1073) );
INVX2TS U3391 ( .A(n1075), .Y(n1077) );
NAND2X1TS U3392 ( .A(n1077), .B(n1076), .Y(n1078) );
INVX2TS U3393 ( .A(n6190), .Y(n6240) );
INVX2TS U3394 ( .A(n1080), .Y(n1133) );
INVX2TS U3395 ( .A(n1091), .Y(n1115) );
INVX2TS U3396 ( .A(n1083), .Y(n1086) );
INVX2TS U3397 ( .A(n1084), .Y(n1085) );
NAND2X1TS U3398 ( .A(n1197), .B(n1195), .Y(n1088) );
INVX2TS U3399 ( .A(n1089), .Y(n1113) );
INVX2TS U3400 ( .A(n1112), .Y(n1090) );
AOI21X1TS U3401 ( .A0(n1091), .A1(n1113), .B0(n1090), .Y(n1096) );
INVX2TS U3402 ( .A(n1092), .Y(n1094) );
NAND2X1TS U3403 ( .A(n1094), .B(n1093), .Y(n1095) );
INVX2TS U3404 ( .A(n1097), .Y(n1100) );
INVX2TS U3405 ( .A(n1098), .Y(n1099) );
INVX2TS U3406 ( .A(n1101), .Y(n1109) );
INVX2TS U3407 ( .A(n1108), .Y(n1102) );
NAND2X1TS U3408 ( .A(n1105), .B(n1104), .Y(n1106) );
NAND2X1TS U3409 ( .A(n1109), .B(n1108), .Y(n1110) );
XOR2X1TS U3410 ( .A(n1115), .B(n1114), .Y(n1187) );
INVX2TS U3411 ( .A(n1119), .Y(n1121) );
NAND2X1TS U3412 ( .A(n1121), .B(n1120), .Y(n1122) );
NOR2X2TS U3413 ( .A(n1177), .B(Sgf_operation_ODD1_Q_right[34]), .Y(n6304) );
INVX2TS U3414 ( .A(n1124), .Y(n1126) );
NAND2X1TS U3415 ( .A(n1126), .B(n1125), .Y(n1127) );
NAND2X1TS U3416 ( .A(n1131), .B(n1130), .Y(n1132) );
XOR2X1TS U3417 ( .A(n1133), .B(n1132), .Y(n1178) );
INVX2TS U3418 ( .A(n1134), .Y(n1144) );
INVX2TS U3419 ( .A(n1135), .Y(n1137) );
NAND2X1TS U3420 ( .A(n1137), .B(n1136), .Y(n1138) );
NAND2X1TS U3421 ( .A(n1142), .B(n1141), .Y(n1143) );
XOR2X1TS U3422 ( .A(n1144), .B(n1143), .Y(n1153) );
INVX2TS U3423 ( .A(n1145), .Y(n1147) );
NAND2X1TS U3424 ( .A(n1147), .B(n1146), .Y(n1149) );
XOR2X1TS U3425 ( .A(n1149), .B(n1148), .Y(n1152) );
NAND2X1TS U3426 ( .A(n888), .B(n1150), .Y(n1151) );
XNOR2X1TS U3427 ( .A(DP_OP_168J43_122_1342_n499), .B(n1151), .Y(n6269) );
NAND2X1TS U3428 ( .A(n6269), .B(Sgf_operation_ODD1_Q_right[27]), .Y(n6273)
);
NAND2X1TS U3429 ( .A(n1152), .B(Sgf_operation_ODD1_Q_right[28]), .Y(n6271)
);
OAI21X2TS U3430 ( .A0(n6270), .A1(n6273), .B0(n6271), .Y(n6277) );
INVX2TS U3431 ( .A(n6276), .Y(n1154) );
NAND2X1TS U3432 ( .A(n1155), .B(Sgf_operation_ODD1_Q_right[30]), .Y(n6280)
);
INVX2TS U3433 ( .A(n6280), .Y(n1156) );
INVX2TS U3434 ( .A(n1157), .Y(n1162) );
NAND2X1TS U3435 ( .A(n1162), .B(n1160), .Y(n1158) );
NAND2X1TS U3436 ( .A(n1159), .B(Sgf_operation_ODD1_Q_right[31]), .Y(n6284)
);
INVX2TS U3437 ( .A(n1160), .Y(n1161) );
AOI21X1TS U3438 ( .A0(n1163), .A1(n1162), .B0(n1161), .Y(n1168) );
INVX2TS U3439 ( .A(n1164), .Y(n1166) );
NAND2X1TS U3440 ( .A(n1166), .B(n1165), .Y(n1167) );
XOR2X1TS U3441 ( .A(n1168), .B(n1167), .Y(n1169) );
INVX2TS U3442 ( .A(n1171), .Y(n1173) );
NAND2X1TS U3443 ( .A(n1173), .B(n1172), .Y(n1174) );
NAND2X1TS U3444 ( .A(n1178), .B(Sgf_operation_ODD1_Q_right[35]), .Y(n6306)
);
INVX2TS U3445 ( .A(n6306), .Y(n6309) );
INVX2TS U3446 ( .A(n6311), .Y(n1180) );
NAND2X1TS U3447 ( .A(n1187), .B(Sgf_operation_ODD1_Q_right[39]), .Y(n6331)
);
INVX2TS U3448 ( .A(n6331), .Y(n1188) );
INVX2TS U3449 ( .A(n1195), .Y(n1196) );
AOI21X1TS U3450 ( .A0(n1198), .A1(n1197), .B0(n1196), .Y(n1203) );
INVX2TS U3451 ( .A(n1199), .Y(n1201) );
NAND2X1TS U3452 ( .A(n1201), .B(n1200), .Y(n1202) );
XOR2X1TS U3453 ( .A(n1203), .B(n1202), .Y(n1226) );
INVX2TS U3454 ( .A(n1206), .Y(n1208) );
INVX2TS U3455 ( .A(n1211), .Y(n1213) );
NAND2X1TS U3456 ( .A(n1213), .B(n1212), .Y(n1214) );
XOR2X1TS U3457 ( .A(n1215), .B(n1214), .Y(n1229) );
INVX2TS U3458 ( .A(n1216), .Y(n1224) );
INVX2TS U3459 ( .A(n1223), .Y(n1217) );
INVX2TS U3460 ( .A(n1218), .Y(n1220) );
NAND2X1TS U3461 ( .A(n1220), .B(n1219), .Y(n1221) );
NAND2X1TS U3462 ( .A(n1224), .B(n1223), .Y(n1225) );
INVX2TS U3463 ( .A(n6257), .Y(n6215) );
INVX2TS U3464 ( .A(n6225), .Y(n1230) );
INVX2TS U3465 ( .A(n6239), .Y(n1239) );
NAND2X1TS U3466 ( .A(n1237), .B(Sgf_operation_ODD1_Q_right[48]), .Y(n6191)
);
INVX2TS U3467 ( .A(n6191), .Y(n1238) );
INVX2TS U3468 ( .A(n1246), .Y(n1248) );
NAND2X1TS U3469 ( .A(n1248), .B(n1247), .Y(n1249) );
INVX2TS U3470 ( .A(n1256), .Y(n1258) );
NAND2X1TS U3471 ( .A(n1258), .B(n1257), .Y(n1259) );
INVX2TS U3472 ( .A(n6090), .Y(n6153) );
INVX2TS U3473 ( .A(n1261), .Y(n1344) );
INVX2TS U3474 ( .A(n1264), .Y(n1267) );
INVX2TS U3475 ( .A(n1265), .Y(n1266) );
INVX2TS U3476 ( .A(n1280), .Y(n1290) );
INVX2TS U3477 ( .A(n1270), .Y(n1272) );
NAND2X1TS U3478 ( .A(n1272), .B(n1271), .Y(n1273) );
INVX2TS U3479 ( .A(n1275), .Y(n1277) );
NAND2X1TS U3480 ( .A(n1277), .B(n1276), .Y(n1278) );
INVX2TS U3481 ( .A(n1281), .Y(n1283) );
NAND2X1TS U3482 ( .A(n1283), .B(n1282), .Y(n1284) );
INVX2TS U3483 ( .A(n1286), .Y(n1288) );
NAND2X1TS U3484 ( .A(n1288), .B(n1287), .Y(n1289) );
NAND2X2TS U3485 ( .A(n813), .B(n752), .Y(n6119) );
INVX2TS U3486 ( .A(n1291), .Y(n1293) );
NAND2X1TS U3487 ( .A(n1293), .B(n1292), .Y(n1294) );
XOR2X1TS U3488 ( .A(n1295), .B(n1294), .Y(n1310) );
OAI21X1TS U3489 ( .A0(n1296), .A1(n1302), .B0(n1303), .Y(n1301) );
INVX2TS U3490 ( .A(n1297), .Y(n1299) );
NAND2X1TS U3491 ( .A(n1299), .B(n1298), .Y(n1300) );
INVX2TS U3492 ( .A(n1302), .Y(n1304) );
NOR2X2TS U3493 ( .A(n1308), .B(Sgf_operation_ODD1_Q_right[51]), .Y(n6208) );
NAND2X2TS U3494 ( .A(n875), .B(n1326), .Y(n1328) );
INVX2TS U3495 ( .A(n6204), .Y(n6085) );
NAND2X1TS U3496 ( .A(n1310), .B(Sgf_operation_ODD1_Q_right[53]), .Y(n6164)
);
INVX2TS U3497 ( .A(n6164), .Y(n1311) );
INVX2TS U3498 ( .A(n6133), .Y(n1315) );
INVX2TS U3499 ( .A(n6108), .Y(n1318) );
AFHCONX2TS U3500 ( .A(n1331), .B(n1330), .CI(n1329), .CON(n1355), .S(n1352)
);
AFHCINX2TS U3501 ( .CIN(n1332), .B(n1333), .A(n1334), .S(n1350), .CO(n1329)
);
OAI21X1TS U3502 ( .A0(n1344), .A1(n1343), .B0(n1342), .Y(n1347) );
NAND2X1TS U3503 ( .A(n905), .B(n1345), .Y(n1346) );
NOR2X2TS U3504 ( .A(n1348), .B(Sgf_operation_ODD1_Q_left[6]), .Y(n6073) );
NAND2X1TS U3505 ( .A(n1350), .B(Sgf_operation_ODD1_Q_left[8]), .Y(n6051) );
INVX2TS U3506 ( .A(n6051), .Y(n1351) );
NAND2X1TS U3507 ( .A(n1352), .B(Sgf_operation_ODD1_Q_left[9]), .Y(n6036) );
AFHCINX2TS U3508 ( .CIN(n1355), .B(n1356), .A(n1357), .S(n1358), .CO(n1359)
);
AFHCONX2TS U3509 ( .A(n1361), .B(n1360), .CI(n1359), .CON(n1057), .S(n1362)
);
NAND2X1TS U3510 ( .A(n1362), .B(Sgf_operation_ODD1_Q_left[11]), .Y(n6009) );
INVX2TS U3511 ( .A(n6009), .Y(n1363) );
INVX2TS U3512 ( .A(n5998), .Y(n5986) );
INVX2TS U3513 ( .A(n5987), .Y(n1366) );
OAI21X4TS U3514 ( .A0(n1368), .A1(n5985), .B0(n1367), .Y(n5976) );
AFHCINX2TS U3515 ( .CIN(n1369), .B(n1370), .A(n1371), .S(n1372), .CO(n1374)
);
INVX2TS U3516 ( .A(n5975), .Y(n1373) );
AOI21X4TS U3517 ( .A0(n5976), .A1(n823), .B0(n1373), .Y(n5963) );
AFHCONX2TS U3518 ( .A(n1376), .B(n1375), .CI(n1374), .CON(n1378), .S(n1377)
);
AFHCINX2TS U3519 ( .CIN(n1378), .B(n1379), .A(n1380), .S(n1381), .CO(n1383)
);
INVX2TS U3520 ( .A(n5951), .Y(n1382) );
AOI21X4TS U3521 ( .A0(n5952), .A1(n822), .B0(n1382), .Y(n5942) );
AFHCONX2TS U3522 ( .A(n1385), .B(n1384), .CI(n1383), .CON(n1051), .S(n1386)
);
OAI21X4TS U3523 ( .A0(n5942), .A1(n5939), .B0(n5940), .Y(n5931) );
INVX2TS U3524 ( .A(n5930), .Y(n1388) );
AOI21X4TS U3525 ( .A0(n821), .A1(n5931), .B0(n1388), .Y(n5922) );
AFHCONX2TS U3526 ( .A(n1391), .B(n1390), .CI(n1389), .CON(n1048), .S(n1392)
);
OAI21X4TS U3527 ( .A0(n5922), .A1(n5919), .B0(n5920), .Y(n5911) );
AOI21X4TS U3528 ( .A0(n820), .A1(n5911), .B0(n1394), .Y(n5902) );
AFHCONX2TS U3529 ( .A(n1397), .B(n1396), .CI(n1395), .CON(n1045), .S(n1398)
);
OAI21X4TS U3530 ( .A0(n5902), .A1(n5899), .B0(n5900), .Y(n5890) );
AOI21X4TS U3531 ( .A0(n819), .A1(n5890), .B0(n1400), .Y(n5881) );
AFHCONX2TS U3532 ( .A(n1403), .B(n1402), .CI(n1401), .CON(n1042), .S(n1404)
);
OAI21X4TS U3533 ( .A0(n5881), .A1(n5878), .B0(n5879), .Y(n5870) );
AFHCONX2TS U3534 ( .A(n1409), .B(n1408), .CI(n1407), .CON(n1039), .S(n1410)
);
OAI21X4TS U3535 ( .A0(n5861), .A1(n5858), .B0(n5859), .Y(n5849) );
AOI21X4TS U3536 ( .A0(n817), .A1(n5849), .B0(n1412), .Y(n5840) );
OAI21X4TS U3537 ( .A0(n5837), .A1(n5840), .B0(n5838), .Y(n5816) );
AOI21X4TS U3538 ( .A0(n1417), .A1(n5816), .B0(n1416), .Y(n5806) );
NOR2X1TS U3539 ( .A(DP_OP_168J43_122_1342_n460), .B(
DP_OP_168J43_122_1342_n461), .Y(n5705) );
NOR2XLTS U3540 ( .A(DP_OP_168J43_122_1342_n458), .B(
DP_OP_168J43_122_1342_n459), .Y(n1418) );
NAND2X1TS U3541 ( .A(n5705), .B(n1418), .Y(n5667) );
NOR2X1TS U3542 ( .A(DP_OP_168J43_122_1342_n456), .B(
DP_OP_168J43_122_1342_n457), .Y(n5669) );
NOR2XLTS U3543 ( .A(DP_OP_168J43_122_1342_n454), .B(
DP_OP_168J43_122_1342_n455), .Y(n1419) );
NAND2X1TS U3544 ( .A(n5669), .B(n1419), .Y(n1420) );
NOR2X2TS U3545 ( .A(n850), .B(n5790), .Y(n5762) );
NOR2X1TS U3546 ( .A(DP_OP_168J43_122_1342_n464), .B(
DP_OP_168J43_122_1342_n465), .Y(n5742) );
NOR2XLTS U3547 ( .A(DP_OP_168J43_122_1342_n462), .B(
DP_OP_168J43_122_1342_n463), .Y(n1421) );
NAND2X2TS U3548 ( .A(n5762), .B(n829), .Y(n5733) );
NOR2X1TS U3549 ( .A(n846), .B(n5733), .Y(n5655) );
NOR2X2TS U3550 ( .A(FS_Module_state_reg[0]), .B(FS_Module_state_reg[2]), .Y(
n2087) );
NAND2X1TS U3551 ( .A(n2087), .B(FS_Module_state_reg[3]), .Y(n5629) );
NAND2X1TS U3552 ( .A(n6585), .B(FSM_add_overflow_flag), .Y(n1423) );
NOR2X1TS U3553 ( .A(n6540), .B(FS_Module_state_reg[3]), .Y(n2090) );
NAND2X1TS U3554 ( .A(n2090), .B(n6535), .Y(n5628) );
OAI21X1TS U3555 ( .A0(n5629), .A1(n1423), .B0(n5628), .Y(n5659) );
INVX4TS U3556 ( .A(n6557), .Y(n3511) );
XNOR2X2TS U3557 ( .A(n3511), .B(Op_MX[42]), .Y(n2754) );
CLKXOR2X2TS U3558 ( .A(n807), .B(Op_MX[43]), .Y(n2755) );
NAND2X1TS U3559 ( .A(n3458), .B(n3312), .Y(n1425) );
OAI21X1TS U3560 ( .A0(n6546), .A1(n3453), .B0(n1425), .Y(n1426) );
XOR2X1TS U3561 ( .A(n1426), .B(n3454), .Y(n1538) );
XNOR2X2TS U3562 ( .A(Op_MY[15]), .B(n799), .Y(n2961) );
BUFX4TS U3563 ( .A(n1428), .Y(n4323) );
XNOR2X1TS U3564 ( .A(Op_MY[15]), .B(Op_MY[16]), .Y(n2962) );
NOR2BX1TS U3565 ( .AN(n2961), .B(n2962), .Y(n2960) );
BUFX4TS U3566 ( .A(n2960), .Y(n4304) );
INVX4TS U3567 ( .A(n6547), .Y(n4139) );
BUFX4TS U3568 ( .A(n2959), .Y(n4307) );
INVX4TS U3569 ( .A(n6561), .Y(n4302) );
XOR2X1TS U3570 ( .A(n1427), .B(n4302), .Y(n4118) );
NAND2X1TS U3571 ( .A(n4307), .B(n4159), .Y(n1429) );
XOR2X1TS U3572 ( .A(n1430), .B(n4302), .Y(n1431) );
ADDHXLTS U3573 ( .A(n780), .B(n1431), .CO(n4117), .S(mult_x_24_n882) );
CLKXOR2X2TS U3574 ( .A(Op_MY[22]), .B(n6591), .Y(n2748) );
BUFX4TS U3575 ( .A(n2916), .Y(n4198) );
NAND2X1TS U3576 ( .A(n4198), .B(n4159), .Y(n1432) );
INVX4TS U3577 ( .A(n6565), .Y(n4193) );
XOR2X1TS U3578 ( .A(n1433), .B(n4193), .Y(n1546) );
INVX4TS U3579 ( .A(n6551), .Y(n6598) );
NOR2X2TS U3580 ( .A(n1434), .B(n930), .Y(n1442) );
NOR2XLTS U3581 ( .A(n927), .B(n926), .Y(n1441) );
BUFX4TS U3582 ( .A(n6202), .Y(n6339) );
NOR2X1TS U3583 ( .A(Op_MY[28]), .B(Op_MY[1]), .Y(n1621) );
NAND2X1TS U3584 ( .A(Op_MY[28]), .B(Op_MY[1]), .Y(n1622) );
NOR2X2TS U3585 ( .A(Op_MY[29]), .B(Op_MY[2]), .Y(n2132) );
NOR2X2TS U3586 ( .A(Op_MY[30]), .B(Op_MY[3]), .Y(n2134) );
NAND2X1TS U3587 ( .A(Op_MY[29]), .B(Op_MY[2]), .Y(n2131) );
NAND2X1TS U3588 ( .A(Op_MY[30]), .B(Op_MY[3]), .Y(n2135) );
NOR2X1TS U3589 ( .A(Op_MY[31]), .B(Op_MY[4]), .Y(n1857) );
NOR2X2TS U3590 ( .A(Op_MY[32]), .B(n804), .Y(n2167) );
NOR2X2TS U3591 ( .A(Op_MY[33]), .B(Op_MY[6]), .Y(n1969) );
NOR2X2TS U3592 ( .A(Op_MY[34]), .B(Op_MY[7]), .Y(n1971) );
NAND2X1TS U3593 ( .A(Op_MY[31]), .B(Op_MY[4]), .Y(n2163) );
NAND2X1TS U3594 ( .A(Op_MY[32]), .B(n803), .Y(n2168) );
NAND2X1TS U3595 ( .A(Op_MY[33]), .B(Op_MY[6]), .Y(n1968) );
NAND2X1TS U3596 ( .A(Op_MY[34]), .B(Op_MY[7]), .Y(n1972) );
NOR2X2TS U3597 ( .A(n2620), .B(n2622), .Y(n1511) );
NOR2X1TS U3598 ( .A(Op_MY[37]), .B(Op_MY[10]), .Y(n1480) );
NOR2X2TS U3599 ( .A(Op_MY[41]), .B(n799), .Y(n2603) );
NAND2X1TS U3600 ( .A(Op_MY[35]), .B(n782), .Y(n2619) );
NAND2X1TS U3601 ( .A(Op_MY[36]), .B(Op_MY[9]), .Y(n2623) );
OAI21X2TS U3602 ( .A0(n2622), .A1(n2619), .B0(n2623), .Y(n1515) );
NAND2X1TS U3603 ( .A(Op_MY[37]), .B(Op_MY[10]), .Y(n1512) );
NAND2X1TS U3604 ( .A(Op_MY[38]), .B(n776), .Y(n1519) );
OAI21X1TS U3605 ( .A0(n1518), .A1(n1512), .B0(n1519), .Y(n1451) );
NAND2X1TS U3606 ( .A(Op_MY[39]), .B(Op_MY[12]), .Y(n1528) );
NAND2X1TS U3607 ( .A(Op_MY[40]), .B(Op_MY[13]), .Y(n1490) );
OAI21X2TS U3608 ( .A0(n1489), .A1(n1528), .B0(n1490), .Y(n2601) );
NAND2X1TS U3609 ( .A(Op_MY[41]), .B(n799), .Y(n2602) );
NAND2X1TS U3610 ( .A(Op_MY[42]), .B(Op_MY[15]), .Y(n2611) );
AOI21X1TS U3611 ( .A0(n2601), .A1(n1454), .B0(n1453), .Y(n1455) );
NOR2X1TS U3612 ( .A(n2691), .B(n2684), .Y(n1463) );
NOR2X1TS U3613 ( .A(Op_MY[47]), .B(n769), .Y(n1472) );
NOR2X2TS U3614 ( .A(n1472), .B(n1587), .Y(n2679) );
NOR2X2TS U3615 ( .A(Op_MY[44]), .B(n779), .Y(n2466) );
NOR2X2TS U3616 ( .A(n2465), .B(n2466), .Y(n1564) );
NOR2X2TS U3617 ( .A(n1465), .B(n1580), .Y(n2726) );
INVX2TS U3618 ( .A(n2726), .Y(n1467) );
NAND2X1TS U3619 ( .A(Op_MY[43]), .B(Op_MY[16]), .Y(n2464) );
NAND2X1TS U3620 ( .A(Op_MY[44]), .B(n779), .Y(n2467) );
OAI21X2TS U3621 ( .A0(n2466), .A1(n2464), .B0(n2467), .Y(n1568) );
NAND2X1TS U3622 ( .A(Op_MY[45]), .B(Op_MY[18]), .Y(n1565) );
NAND2X1TS U3623 ( .A(Op_MY[46]), .B(Op_MY[19]), .Y(n1572) );
OAI21X1TS U3624 ( .A0(n1571), .A1(n1565), .B0(n1572), .Y(n1460) );
AOI21X2TS U3625 ( .A0(n1568), .A1(n1461), .B0(n1460), .Y(n1581) );
NAND2X1TS U3626 ( .A(Op_MY[47]), .B(n769), .Y(n1582) );
NAND2X1TS U3627 ( .A(Op_MY[48]), .B(Op_MY[21]), .Y(n1588) );
OAI21X2TS U3628 ( .A0(n1587), .A1(n1582), .B0(n1588), .Y(n2682) );
NAND2X1TS U3629 ( .A(Op_MY[49]), .B(Op_MY[22]), .Y(n2683) );
NAND2X1TS U3630 ( .A(Op_MY[50]), .B(n6591), .Y(n2692) );
AOI21X1TS U3631 ( .A0(n1463), .A1(n2682), .B0(n1462), .Y(n1464) );
INVX2TS U3632 ( .A(n2738), .Y(n1466) );
NAND2X1TS U3633 ( .A(n6590), .B(Op_MY[24]), .Y(n2727) );
NAND2X1TS U3634 ( .A(n2737), .B(n2727), .Y(n1468) );
XNOR2X1TS U3635 ( .A(n1469), .B(n1468), .Y(n1470) );
INVX2TS U3636 ( .A(n5553), .Y(n1471) );
INVX4TS U3637 ( .A(n5122), .Y(n4964) );
CLKBUFX2TS U3638 ( .A(n4964), .Y(n2847) );
NOR2X1TS U3639 ( .A(n1471), .B(n2847), .Y(DP_OP_169J43_123_4229_n713) );
INVX2TS U3640 ( .A(n1472), .Y(n1584) );
NAND2X1TS U3641 ( .A(n1584), .B(n1582), .Y(n1473) );
XNOR2X1TS U3642 ( .A(n1474), .B(n1473), .Y(n1475) );
INVX2TS U3643 ( .A(n5561), .Y(n1476) );
NOR2X1TS U3644 ( .A(n1476), .B(n4964), .Y(DP_OP_169J43_123_4229_n739) );
INVX2TS U3645 ( .A(n1511), .Y(n1479) );
INVX2TS U3646 ( .A(n1515), .Y(n1478) );
INVX2TS U3647 ( .A(n1480), .Y(n1514) );
NAND2X1TS U3648 ( .A(n1514), .B(n1512), .Y(n1481) );
XNOR2X1TS U3649 ( .A(n1482), .B(n1481), .Y(n1483) );
INVX2TS U3650 ( .A(n5581), .Y(n1484) );
INVX4TS U3651 ( .A(n5133), .Y(n4971) );
NOR2X2TS U3652 ( .A(n1484), .B(n4971), .Y(n2829) );
INVX2TS U3653 ( .A(n2829), .Y(n1535) );
INVX2TS U3654 ( .A(n1527), .Y(n2600) );
INVX2TS U3655 ( .A(n1485), .Y(n1529) );
NAND2X1TS U3656 ( .A(n2600), .B(n1529), .Y(n1488) );
INVX2TS U3657 ( .A(n1526), .Y(n2607) );
AOI21X1TS U3658 ( .A0(n2607), .A1(n1529), .B0(n1486), .Y(n1487) );
NAND2X1TS U3659 ( .A(n1491), .B(n1490), .Y(n1492) );
XNOR2X1TS U3660 ( .A(n1493), .B(n1492), .Y(n1494) );
NAND2X1TS U3661 ( .A(n6584), .B(n788), .Y(n1495) );
XNOR2X1TS U3662 ( .A(n5575), .B(n5171), .Y(n5159) );
XOR2X1TS U3663 ( .A(n6584), .B(n788), .Y(n1502) );
XNOR2X1TS U3664 ( .A(n1502), .B(n1497), .Y(n1501) );
NAND2X1TS U3665 ( .A(n792), .B(Op_MX[49]), .Y(n1498) );
NAND2X1TS U3666 ( .A(n2671), .B(n2670), .Y(n1500) );
CLKXOR2X2TS U3667 ( .A(n1501), .B(n1500), .Y(n5142) );
XOR2X1TS U3668 ( .A(n1503), .B(n6583), .Y(n1504) );
NAND2X1TS U3669 ( .A(n2600), .B(n2598), .Y(n1506) );
AOI21X1TS U3670 ( .A0(n2607), .A1(n2598), .B0(n2601), .Y(n1505) );
OAI21X1TS U3671 ( .A0(n2621), .A1(n1506), .B0(n1505), .Y(n1509) );
NAND2X1TS U3672 ( .A(n1507), .B(n2602), .Y(n1508) );
XNOR2X1TS U3673 ( .A(n1509), .B(n1508), .Y(n1510) );
XNOR2X1TS U3674 ( .A(n5573), .B(n5171), .Y(n5158) );
OAI22X1TS U3675 ( .A0(n5159), .A1(n5173), .B0(n5158), .B1(n5175), .Y(n1534)
);
NAND2X1TS U3676 ( .A(n1511), .B(n1514), .Y(n1517) );
AOI21X1TS U3677 ( .A0(n1515), .A1(n1514), .B0(n1513), .Y(n1516) );
NAND2X1TS U3678 ( .A(n1520), .B(n1519), .Y(n1521) );
XNOR2X1TS U3679 ( .A(n1522), .B(n1521), .Y(n1523) );
BUFX3TS U3680 ( .A(Op_MX[26]), .Y(n5122) );
XNOR2X1TS U3681 ( .A(n5579), .B(n5122), .Y(n5129) );
CLKXOR2X2TS U3682 ( .A(n1525), .B(n4971), .Y(n4685) );
BUFX4TS U3683 ( .A(n4684), .Y(n5138) );
OAI21X1TS U3684 ( .A0(n2621), .A1(n1527), .B0(n1526), .Y(n1531) );
NAND2X1TS U3685 ( .A(n1529), .B(n1528), .Y(n1530) );
XNOR2X1TS U3686 ( .A(n1531), .B(n1530), .Y(n1532) );
XNOR2X1TS U3687 ( .A(n5577), .B(n5133), .Y(n5128) );
BUFX4TS U3688 ( .A(n4685), .Y(n5136) );
OAI22X1TS U3689 ( .A0(n5129), .A1(n5138), .B0(n5128), .B1(n5136), .Y(n1533)
);
CMPR32X2TS U3690 ( .A(n1535), .B(n1534), .C(n1533), .CO(
DP_OP_169J43_123_4229_n855), .S(DP_OP_169J43_123_4229_n856) );
NAND2X2TS U3691 ( .A(n1536), .B(n2214), .Y(n3314) );
BUFX4TS U3692 ( .A(n2780), .Y(n3472) );
XOR2X1TS U3693 ( .A(n1537), .B(n3454), .Y(n3330) );
ADDHXLTS U3694 ( .A(n807), .B(n1538), .CO(n3329), .S(mult_x_23_n797) );
BUFX4TS U3695 ( .A(n6202), .Y(n6336) );
BUFX4TS U3696 ( .A(n3350), .Y(n3559) );
XOR2X1TS U3697 ( .A(n1542), .B(n3541), .Y(n3349) );
ADDHXLTS U3698 ( .A(n805), .B(n1543), .CO(n3348), .S(mult_x_23_n833) );
BUFX4TS U3699 ( .A(n1544), .Y(n4214) );
XNOR2X1TS U3700 ( .A(Op_MY[21]), .B(Op_MY[22]), .Y(n2747) );
NOR2BX1TS U3701 ( .AN(n774), .B(n2747), .Y(n2917) );
BUFX4TS U3702 ( .A(n2917), .Y(n4195) );
XOR2X1TS U3703 ( .A(n1545), .B(n4193), .Y(n4098) );
ADDHXLTS U3704 ( .A(n6591), .B(n1546), .CO(n4097), .S(mult_x_24_n828) );
XOR2X1TS U3705 ( .A(n791), .B(Op_MX[45]), .Y(n1552) );
XNOR2X1TS U3706 ( .A(n1552), .B(n1547), .Y(n1551) );
XNOR2X2TS U3707 ( .A(n793), .B(n807), .Y(n5032) );
NAND2X1TS U3708 ( .A(n790), .B(Op_MX[43]), .Y(n1548) );
CLKXOR2X2TS U3709 ( .A(n1551), .B(n1550), .Y(n5275) );
XOR2X1TS U3710 ( .A(n1553), .B(n4997), .Y(n1554) );
BUFX4TS U3711 ( .A(n5010), .Y(n5257) );
NAND2X1TS U3712 ( .A(n791), .B(Op_MX[45]), .Y(n1555) );
INVX2TS U3713 ( .A(n1564), .Y(n1558) );
INVX2TS U3714 ( .A(n1568), .Y(n1557) );
INVX2TS U3715 ( .A(n1559), .Y(n1567) );
NAND2X1TS U3716 ( .A(n1567), .B(n1565), .Y(n1560) );
XNOR2X1TS U3717 ( .A(n1561), .B(n1560), .Y(n1562) );
INVX2TS U3718 ( .A(n5565), .Y(n1563) );
NOR2X1TS U3719 ( .A(n1563), .B(n6548), .Y(n2770) );
NAND2X1TS U3720 ( .A(n1564), .B(n1567), .Y(n1570) );
AOI21X1TS U3721 ( .A0(n1568), .A1(n1567), .B0(n1566), .Y(n1569) );
NAND2X1TS U3722 ( .A(n1573), .B(n1572), .Y(n1574) );
XNOR2X1TS U3723 ( .A(n1575), .B(n1574), .Y(n1576) );
INVX2TS U3724 ( .A(n5563), .Y(n1577) );
CMPR32X2TS U3725 ( .A(n1579), .B(n2770), .C(n1578), .CO(
DP_OP_169J43_123_4229_n747), .S(DP_OP_169J43_123_4229_n748) );
INVX2TS U3726 ( .A(n1580), .Y(n2681) );
NAND2X1TS U3727 ( .A(n2681), .B(n1584), .Y(n1586) );
INVX2TS U3728 ( .A(n1581), .Y(n2688) );
AOI21X1TS U3729 ( .A0(n2688), .A1(n1584), .B0(n1583), .Y(n1585) );
NAND2X1TS U3730 ( .A(n1589), .B(n1588), .Y(n1590) );
XNOR2X1TS U3731 ( .A(n1591), .B(n1590), .Y(n1592) );
INVX2TS U3732 ( .A(n5559), .Y(n1593) );
INVX2TS U3733 ( .A(n2214), .Y(n1595) );
NAND2X1TS U3734 ( .A(n2216), .B(n2215), .Y(n1594) );
NOR2X2TS U3735 ( .A(n3654), .B(n3650), .Y(n2277) );
NAND2X1TS U3736 ( .A(n2203), .B(n2252), .Y(n2229) );
NAND2X1TS U3737 ( .A(n3650), .B(n3748), .Y(n2280) );
NAND2X1TS U3738 ( .A(n2280), .B(n2276), .Y(n1596) );
NOR2X2TS U3739 ( .A(n3748), .B(n3742), .Y(n2574) );
INVX2TS U3740 ( .A(n2486), .Y(n1600) );
NAND2X1TS U3741 ( .A(n1600), .B(n1708), .Y(n1605) );
NAND2X1TS U3742 ( .A(n2576), .B(n2573), .Y(n2650) );
NAND2X1TS U3743 ( .A(n3731), .B(n3725), .Y(n2794) );
NAND2X1TS U3744 ( .A(n2794), .B(n2789), .Y(n1601) );
INVX2TS U3745 ( .A(n2485), .Y(n1603) );
NAND2X1TS U3746 ( .A(n3719), .B(n3713), .Y(n2490) );
NAND2X1TS U3747 ( .A(n2490), .B(n2702), .Y(n1711) );
AOI21X1TS U3748 ( .A0(n1603), .A1(n1708), .B0(n1711), .Y(n1604) );
INVX2TS U3749 ( .A(n1707), .Y(n1863) );
NAND2X1TS U3750 ( .A(n1863), .B(n1861), .Y(n1606) );
XNOR2X1TS U3751 ( .A(n1864), .B(n1606), .Y(n1607) );
NAND2X1TS U3752 ( .A(n1609), .B(n6584), .Y(n3020) );
NOR2BX1TS U3753 ( .AN(n1609), .B(n6584), .Y(n1615) );
BUFX3TS U3754 ( .A(n1615), .Y(n3248) );
AOI21X1TS U3755 ( .A0(n3289), .A1(n3719), .B0(n1610), .Y(n1611) );
OAI21X1TS U3756 ( .A0(n3723), .A1(n3317), .B0(n1611), .Y(mult_x_23_n557) );
INVX2TS U3757 ( .A(n2574), .Y(n1612) );
NAND2X1TS U3758 ( .A(n1612), .B(n2573), .Y(n1613) );
XOR2X1TS U3759 ( .A(n2653), .B(n1613), .Y(n1614) );
AOI21X1TS U3760 ( .A0(n3289), .A1(n3650), .B0(n1616), .Y(n1617) );
OAI21X1TS U3761 ( .A0(n3652), .A1(n1609), .B0(n1617), .Y(mult_x_23_n611) );
XNOR2X1TS U3762 ( .A(Op_MX[49]), .B(Op_MX[48]), .Y(n2775) );
BUFX4TS U3763 ( .A(n2774), .Y(n3399) );
XOR2X1TS U3764 ( .A(n1618), .B(n3389), .Y(n3309) );
ADDHXLTS U3765 ( .A(n786), .B(n1619), .CO(n3308), .S(mult_x_23_n743) );
INVX4TS U3766 ( .A(n6545), .Y(n4106) );
NAND2X1TS U3767 ( .A(n1623), .B(n1622), .Y(n1625) );
XOR2X1TS U3768 ( .A(n1625), .B(n1624), .Y(n1626) );
CLKXOR2X2TS U3769 ( .A(n2125), .B(n2124), .Y(n4957) );
INVX4TS U3770 ( .A(n4957), .Y(n5591) );
XNOR2X1TS U3771 ( .A(n5097), .B(n5591), .Y(n2122) );
BUFX3TS U3772 ( .A(n6538), .Y(n5093) );
XOR2X1TS U3773 ( .A(mult_x_23_n1930), .B(n2125), .Y(n1627) );
OAI22X1TS U3774 ( .A0(n2122), .A1(n5548), .B0(n5093), .B1(n1628), .Y(n2096)
);
BUFX4TS U3775 ( .A(n1628), .Y(n5587) );
NAND2X1TS U3776 ( .A(n5587), .B(n1629), .Y(n2095) );
NAND2X1TS U3777 ( .A(n2096), .B(n2095), .Y(DP_OP_169J43_123_4229_n646) );
BUFX3TS U3778 ( .A(n6626), .Y(n6623) );
BUFX3TS U3779 ( .A(n6631), .Y(n6604) );
BUFX3TS U3780 ( .A(n6627), .Y(n6622) );
BUFX3TS U3781 ( .A(n6627), .Y(n6629) );
BUFX3TS U3782 ( .A(n6620), .Y(n6628) );
BUFX3TS U3783 ( .A(n1633), .Y(n6627) );
BUFX3TS U3784 ( .A(n6628), .Y(n6608) );
BUFX3TS U3785 ( .A(n6631), .Y(n6607) );
BUFX3TS U3786 ( .A(n6627), .Y(n6626) );
BUFX3TS U3787 ( .A(n6631), .Y(n6606) );
BUFX3TS U3788 ( .A(n6627), .Y(n6625) );
BUFX3TS U3789 ( .A(n6631), .Y(n6605) );
BUFX3TS U3790 ( .A(n6627), .Y(n6624) );
BUFX3TS U3791 ( .A(n6631), .Y(n6601) );
BUFX3TS U3792 ( .A(n6631), .Y(n6600) );
BUFX3TS U3793 ( .A(n6631), .Y(n6602) );
BUFX3TS U3794 ( .A(n1632), .Y(n6618) );
BUFX3TS U3795 ( .A(n6627), .Y(n6609) );
BUFX3TS U3796 ( .A(n6617), .Y(n6610) );
BUFX3TS U3797 ( .A(n6631), .Y(n6603) );
BUFX3TS U3798 ( .A(n1631), .Y(n6614) );
BUFX3TS U3799 ( .A(n6631), .Y(n6599) );
BUFX3TS U3800 ( .A(n6627), .Y(n6619) );
BUFX3TS U3801 ( .A(n6627), .Y(n6612) );
BUFX3TS U3802 ( .A(n6627), .Y(n6616) );
BUFX3TS U3803 ( .A(n6627), .Y(n6615) );
BUFX3TS U3804 ( .A(n6620), .Y(n6611) );
NOR3X1TS U3805 ( .A(n6535), .B(FS_Module_state_reg[2]), .C(n6585), .Y(n5611)
);
INVX4TS U3806 ( .A(n1634), .Y(n6187) );
NAND2X1TS U3807 ( .A(n6187), .B(Add_result[2]), .Y(n1635) );
OAI21XLTS U3808 ( .A0(n6187), .A1(Sgf_normalized_result[2]), .B0(n1635), .Y(
n577) );
NOR2XLTS U3809 ( .A(n6535), .B(FS_Module_state_reg[3]), .Y(n1637) );
NOR2XLTS U3810 ( .A(n6540), .B(n6585), .Y(n1636) );
NAND2X1TS U3811 ( .A(n1637), .B(n1636), .Y(n6346) );
NAND2BXLTS U3812 ( .AN(n6346), .B(P_Sgf[105]), .Y(n2083) );
NAND3X1TS U3813 ( .A(FS_Module_state_reg[0]), .B(n6585), .C(n6540), .Y(n6347) );
INVX2TS U3814 ( .A(n6392), .Y(n6389) );
NAND2X1TS U3815 ( .A(n6389), .B(n6394), .Y(n1638) );
AO21XLTS U3816 ( .A0(n2083), .A1(FSM_selector_B[0]), .B0(n1638), .Y(n419) );
INVX2TS U3817 ( .A(n6347), .Y(n1639) );
AND2X2TS U3818 ( .A(FS_Module_state_reg[3]), .B(n1639), .Y(n6403) );
BUFX3TS U3819 ( .A(n6403), .Y(n6405) );
INVX4TS U3820 ( .A(n6405), .Y(n6401) );
OA22X1TS U3821 ( .A0(n6403), .A1(final_result_ieee[55]), .B0(
exp_oper_result[3]), .B1(n6404), .Y(n296) );
OA22X1TS U3822 ( .A0(n6403), .A1(final_result_ieee[54]), .B0(
exp_oper_result[2]), .B1(n6404), .Y(n297) );
OA22X1TS U3823 ( .A0(n6403), .A1(final_result_ieee[62]), .B0(
exp_oper_result[10]), .B1(n6404), .Y(n289) );
OA22X1TS U3824 ( .A0(n6403), .A1(final_result_ieee[53]), .B0(
exp_oper_result[1]), .B1(n6404), .Y(n298) );
NOR2X1TS U3825 ( .A(n6567), .B(n6540), .Y(n2088) );
CLKXOR2X2TS U3826 ( .A(Op_MX[63]), .B(Op_MY[63]), .Y(n2084) );
NOR4X1TS U3827 ( .A(P_Sgf[0]), .B(P_Sgf[1]), .C(P_Sgf[2]), .D(P_Sgf[3]), .Y(
n1655) );
NOR4X1TS U3828 ( .A(P_Sgf[4]), .B(P_Sgf[5]), .C(P_Sgf[6]), .D(P_Sgf[7]), .Y(
n1654) );
NOR4X1TS U3829 ( .A(P_Sgf[48]), .B(P_Sgf[49]), .C(P_Sgf[50]), .D(P_Sgf[51]),
.Y(n1653) );
OR4X2TS U3830 ( .A(P_Sgf[44]), .B(P_Sgf[45]), .C(P_Sgf[46]), .D(P_Sgf[47]),
.Y(n1651) );
OR4X2TS U3831 ( .A(P_Sgf[40]), .B(P_Sgf[41]), .C(P_Sgf[42]), .D(P_Sgf[43]),
.Y(n1650) );
NOR4X1TS U3832 ( .A(P_Sgf[8]), .B(P_Sgf[9]), .C(P_Sgf[10]), .D(P_Sgf[11]),
.Y(n1643) );
NOR4X1TS U3833 ( .A(P_Sgf[12]), .B(P_Sgf[13]), .C(P_Sgf[14]), .D(P_Sgf[15]),
.Y(n1642) );
NOR4X1TS U3834 ( .A(P_Sgf[16]), .B(P_Sgf[17]), .C(P_Sgf[18]), .D(P_Sgf[19]),
.Y(n1641) );
NOR4X1TS U3835 ( .A(P_Sgf[20]), .B(P_Sgf[21]), .C(P_Sgf[22]), .D(P_Sgf[23]),
.Y(n1640) );
NAND4XLTS U3836 ( .A(n1643), .B(n1642), .C(n1641), .D(n1640), .Y(n1649) );
NOR4X1TS U3837 ( .A(P_Sgf[24]), .B(P_Sgf[25]), .C(P_Sgf[26]), .D(P_Sgf[27]),
.Y(n1647) );
NOR4X1TS U3838 ( .A(P_Sgf[28]), .B(P_Sgf[29]), .C(P_Sgf[30]), .D(P_Sgf[31]),
.Y(n1646) );
NOR4X1TS U3839 ( .A(P_Sgf[32]), .B(P_Sgf[33]), .C(P_Sgf[34]), .D(P_Sgf[35]),
.Y(n1645) );
NOR4X1TS U3840 ( .A(P_Sgf[36]), .B(P_Sgf[37]), .C(P_Sgf[38]), .D(P_Sgf[39]),
.Y(n1644) );
NAND4XLTS U3841 ( .A(n1647), .B(n1646), .C(n1645), .D(n1644), .Y(n1648) );
NOR4X1TS U3842 ( .A(n1651), .B(n1650), .C(n1649), .D(n1648), .Y(n1652) );
NAND4XLTS U3843 ( .A(n1655), .B(n1654), .C(n1653), .D(n1652), .Y(n1657) );
MXI2X1TS U3844 ( .A(n2084), .B(round_mode[1]), .S0(round_mode[0]), .Y(n1656)
);
OAI211X1TS U3845 ( .A0(n2084), .A1(round_mode[1]), .B0(n1657), .C0(n1656),
.Y(n2723) );
AOI32X1TS U3846 ( .A0(FS_Module_state_reg[3]), .A1(n2087), .A2(n2723), .B0(
n6585), .B1(n2087), .Y(n1658) );
CLKAND2X2TS U3847 ( .A(n4106), .B(n4573), .Y(mult_x_24_n940) );
CLKAND2X2TS U3848 ( .A(n4106), .B(n4578), .Y(mult_x_24_n941) );
NAND2X1TS U3849 ( .A(n2310), .B(n2311), .Y(n1982) );
INVX2TS U3850 ( .A(n2016), .Y(n1983) );
INVX2TS U3851 ( .A(n1984), .Y(n1659) );
INVX2TS U3852 ( .A(n2030), .Y(n1664) );
INVX2TS U3853 ( .A(n4080), .Y(n1666) );
INVX2TS U3854 ( .A(n4086), .Y(n1665) );
INVX2TS U3855 ( .A(n4070), .Y(n1670) );
INVX2TS U3856 ( .A(n2078), .Y(n1669) );
INVX2TS U3857 ( .A(n2062), .Y(n2047) );
INVX2TS U3858 ( .A(n2053), .Y(n1671) );
INVX2TS U3859 ( .A(n1755), .Y(n1766) );
BUFX4TS U3860 ( .A(n6583), .Y(n4563) );
INVX2TS U3861 ( .A(n3781), .Y(n1697) );
INVX2TS U3862 ( .A(n2041), .Y(n1679) );
INVX2TS U3863 ( .A(n1995), .Y(n1681) );
INVX2TS U3864 ( .A(n2000), .Y(n1680) );
INVX2TS U3865 ( .A(n1941), .Y(n1685) );
INVX2TS U3866 ( .A(n1813), .Y(n1684) );
INVX2TS U3867 ( .A(n1805), .Y(n2885) );
INVX2TS U3868 ( .A(n2893), .Y(n1686) );
OAI21X1TS U3869 ( .A0(n2884), .A1(n1688), .B0(n1687), .Y(n1689) );
AOI21X4TS U3870 ( .A0(n1939), .A1(n1690), .B0(n1689), .Y(n3788) );
INVX2TS U3871 ( .A(n1765), .Y(n1692) );
INVX2TS U3872 ( .A(n1758), .Y(n1691) );
INVX2TS U3873 ( .A(n2764), .Y(n1723) );
INVX2TS U3874 ( .A(n1729), .Y(n1693) );
OAI21X2TS U3875 ( .A0(n2760), .A1(n1695), .B0(n1694), .Y(n3785) );
INVX2TS U3876 ( .A(n3785), .Y(n1696) );
INVX4TS U3877 ( .A(n6548), .Y(n4383) );
NOR2X1TS U3878 ( .A(n4383), .B(n4563), .Y(n2848) );
INVX2TS U3879 ( .A(n2848), .Y(n3784) );
NAND2X1TS U3880 ( .A(n4383), .B(n4563), .Y(n2849) );
NAND2X1TS U3881 ( .A(n3784), .B(n2849), .Y(n1700) );
XNOR2X4TS U3882 ( .A(n1701), .B(n1700), .Y(n4560) );
XNOR2X2TS U3883 ( .A(Op_MY[24]), .B(n6591), .Y(n1703) );
CLKXOR2X2TS U3884 ( .A(n4106), .B(Op_MY[25]), .Y(n1704) );
BUFX4TS U3885 ( .A(n1987), .Y(n4162) );
INVX4TS U3886 ( .A(n4971), .Y(n4558) );
XNOR2X1TS U3887 ( .A(Op_MY[24]), .B(Op_MY[25]), .Y(n1702) );
NOR2BX1TS U3888 ( .AN(n1703), .B(n1702), .Y(n1988) );
BUFX4TS U3889 ( .A(n1988), .Y(n4161) );
BUFX4TS U3890 ( .A(n1989), .Y(n4160) );
AOI222X1TS U3891 ( .A0(n4162), .A1(n4558), .B0(n4161), .B1(n6583), .C0(n4160), .C1(n4568), .Y(n1705) );
INVX4TS U3892 ( .A(n6545), .Y(n4075) );
XOR2X1TS U3893 ( .A(n1706), .B(n4075), .Y(mult_x_24_n1307) );
NAND2X1TS U3894 ( .A(n3708), .B(n3703), .Y(n1866) );
NAND2X1TS U3895 ( .A(n1866), .B(n1861), .Y(n1709) );
AOI21X1TS U3896 ( .A0(n1711), .A1(n1710), .B0(n1709), .Y(n1712) );
AOI21X4TS U3897 ( .A0(n1716), .A1(n1715), .B0(n1714), .Y(n2713) );
BUFX4TS U3898 ( .A(Op_MY[43]), .Y(n3698) );
BUFX4TS U3899 ( .A(Op_MY[44]), .Y(n3621) );
BUFX4TS U3900 ( .A(Op_MY[45]), .Y(n3692) );
BUFX4TS U3901 ( .A(Op_MY[46]), .Y(n3687) );
NAND2X1TS U3902 ( .A(n3698), .B(n3621), .Y(n1920) );
NAND2X1TS U3903 ( .A(n1920), .B(n1915), .Y(n1826) );
NAND2X1TS U3904 ( .A(n3692), .B(n3687), .Y(n1832) );
NAND2X1TS U3905 ( .A(n1832), .B(n1884), .Y(n1717) );
BUFX4TS U3906 ( .A(Op_MY[47]), .Y(n3682) );
INVX2TS U3907 ( .A(n1734), .Y(n1793) );
NAND2X1TS U3908 ( .A(n1793), .B(n1791), .Y(n1719) );
CLKXOR2X4TS U3909 ( .A(n1794), .B(n1719), .Y(n3696) );
INVX4TS U3910 ( .A(n3020), .Y(n3299) );
AOI21X1TS U3911 ( .A0(n3299), .A1(n3692), .B0(n1720), .Y(n1721) );
OAI21X1TS U3912 ( .A0(n3696), .A1(n3317), .B0(n1721), .Y(mult_x_23_n521) );
INVX2TS U3913 ( .A(n2761), .Y(n1722) );
INVX2TS U3914 ( .A(n2760), .Y(n1724) );
AOI21X1TS U3915 ( .A0(n1724), .A1(n2765), .B0(n1723), .Y(n1725) );
XNOR2X4TS U3916 ( .A(n1731), .B(n1730), .Y(n4565) );
AOI222X1TS U3917 ( .A0(n4162), .A1(n4557), .B0(n4161), .B1(n788), .C0(n4160),
.C1(n4573), .Y(n1732) );
INVX4TS U3918 ( .A(n6545), .Y(n4093) );
XOR2X1TS U3919 ( .A(n1733), .B(n4093), .Y(mult_x_24_n1308) );
BUFX4TS U3920 ( .A(Op_MY[50]), .Y(n3674) );
BUFX4TS U3921 ( .A(Op_MY[49]), .Y(n3609) );
BUFX4TS U3922 ( .A(Op_MY[48]), .Y(n3677) );
NOR2X2TS U3923 ( .A(n1734), .B(n1795), .Y(n1775) );
INVX2TS U3924 ( .A(n2708), .Y(n1740) );
NAND2X1TS U3925 ( .A(n3682), .B(n3677), .Y(n1796) );
NAND2X1TS U3926 ( .A(n1796), .B(n1791), .Y(n1774) );
NAND2X1TS U3927 ( .A(n3674), .B(n3609), .Y(n1782) );
NAND2X1TS U3928 ( .A(n1782), .B(n1818), .Y(n1735) );
AOI21X1TS U3929 ( .A0(n1736), .A1(n1774), .B0(n1735), .Y(n1737) );
INVX2TS U3930 ( .A(n2710), .Y(n1739) );
INVX4TS U3931 ( .A(n6544), .Y(n3670) );
INVX2TS U3932 ( .A(n1749), .Y(n1741) );
AOI21X1TS U3933 ( .A0(n1751), .A1(n2709), .B0(n1741), .Y(n1742) );
CLKXOR2X2TS U3934 ( .A(Op_MX[47]), .B(Op_MX[46]), .Y(n5000) );
BUFX4TS U3935 ( .A(n1787), .Y(n3428) );
INVX4TS U3936 ( .A(n893), .Y(n3424) );
BUFX4TS U3937 ( .A(n1788), .Y(n3425) );
NOR2X2TS U3938 ( .A(n5000), .B(n1745), .Y(n2798) );
BUFX4TS U3939 ( .A(n2798), .Y(n3412) );
AOI21X1TS U3940 ( .A0(n3424), .A1(n3674), .B0(n1746), .Y(n1747) );
INVX4TS U3941 ( .A(n6563), .Y(n3408) );
XOR2X1TS U3942 ( .A(n1748), .B(n3408), .Y(mult_x_23_n1169) );
NAND2X1TS U3943 ( .A(n2709), .B(n1749), .Y(n1750) );
XNOR2X1TS U3944 ( .A(n1751), .B(n1750), .Y(n1752) );
AOI222X1TS U3945 ( .A0(n3412), .A1(n767), .B0(n3425), .B1(n3678), .C0(n3424),
.C1(n3609), .Y(n1753) );
XOR2X1TS U3946 ( .A(n1754), .B(n3408), .Y(mult_x_23_n1170) );
XNOR2X4TS U3947 ( .A(n1760), .B(n1759), .Y(n4575) );
BUFX4TS U3948 ( .A(Op_MX[23]), .Y(n4567) );
AOI222X1TS U3949 ( .A0(n4162), .A1(n4567), .B0(n4161), .B1(n792), .C0(n4160),
.C1(n4583), .Y(n1761) );
XOR2X1TS U3950 ( .A(n1762), .B(n4093), .Y(mult_x_24_n1310) );
INVX2TS U3951 ( .A(n3782), .Y(n1764) );
INVX2TS U3952 ( .A(n3788), .Y(n1763) );
NAND2X1TS U3953 ( .A(n1766), .B(n1765), .Y(n1767) );
XNOR2X4TS U3954 ( .A(n1768), .B(n1767), .Y(n4580) );
BUFX4TS U3955 ( .A(n792), .Y(n4572) );
AOI222X1TS U3956 ( .A0(n4162), .A1(n4572), .B0(n4161), .B1(Op_MX[21]), .C0(
n4160), .C1(n4588), .Y(n1769) );
XOR2X1TS U3957 ( .A(n1770), .B(n4075), .Y(mult_x_24_n1311) );
INVX2TS U3958 ( .A(n1771), .Y(n1772) );
NAND2X1TS U3959 ( .A(n1772), .B(n1775), .Y(n1778) );
INVX2TS U3960 ( .A(n1773), .Y(n1776) );
AOI21X1TS U3961 ( .A0(n1776), .A1(n1775), .B0(n1774), .Y(n1777) );
INVX2TS U3962 ( .A(n1779), .Y(n1819) );
INVX2TS U3963 ( .A(n1818), .Y(n1780) );
AOI21X1TS U3964 ( .A0(n1821), .A1(n1819), .B0(n1780), .Y(n1785) );
INVX2TS U3965 ( .A(n1781), .Y(n1783) );
NAND2X1TS U3966 ( .A(n1783), .B(n1782), .Y(n1784) );
XOR2X1TS U3967 ( .A(n1785), .B(n1784), .Y(n1786) );
BUFX3TS U3968 ( .A(n1788), .Y(n3405) );
AOI222X1TS U3969 ( .A0(n3412), .A1(n3678), .B0(n3405), .B1(n3683), .C0(n3424), .C1(n3677), .Y(n1789) );
XOR2X1TS U3970 ( .A(n1790), .B(n3408), .Y(mult_x_23_n1171) );
INVX2TS U3971 ( .A(n1791), .Y(n1792) );
AOI21X1TS U3972 ( .A0(n1794), .A1(n1793), .B0(n1792), .Y(n1799) );
INVX2TS U3973 ( .A(n1795), .Y(n1797) );
NAND2X1TS U3974 ( .A(n1797), .B(n1796), .Y(n1798) );
XOR2X1TS U3975 ( .A(n1799), .B(n1798), .Y(n1800) );
AOI222X1TS U3976 ( .A0(n3412), .A1(n3688), .B0(n3405), .B1(n3694), .C0(n3424), .C1(n3687), .Y(n1801) );
XOR2X1TS U3977 ( .A(n1802), .B(n3408), .Y(mult_x_23_n1173) );
OAI21X1TS U3978 ( .A0(n2890), .A1(n2881), .B0(n2884), .Y(n1803) );
XNOR2X4TS U3979 ( .A(n1807), .B(n1806), .Y(n4590) );
BUFX4TS U3980 ( .A(Op_MX[20]), .Y(n4582) );
AOI222X1TS U3981 ( .A0(n4162), .A1(n4582), .B0(n4161), .B1(Op_MX[19]), .C0(
n4160), .C1(n4598), .Y(n1808) );
XOR2X1TS U3982 ( .A(n1809), .B(n4093), .Y(mult_x_24_n1313) );
OAI21X1TS U3983 ( .A0(n2890), .A1(n1810), .B0(n1941), .Y(n1811) );
XNOR2X4TS U3984 ( .A(n1815), .B(n1814), .Y(n4595) );
BUFX4TS U3985 ( .A(Op_MX[19]), .Y(n4587) );
AOI222X1TS U3986 ( .A0(n4162), .A1(n4587), .B0(n4161), .B1(n791), .C0(n4160),
.C1(n4603), .Y(n1816) );
XOR2X1TS U3987 ( .A(n1817), .B(n4093), .Y(mult_x_24_n1314) );
NAND2X1TS U3988 ( .A(n1819), .B(n1818), .Y(n1820) );
XNOR2X1TS U3989 ( .A(n1821), .B(n1820), .Y(n1822) );
AOI222X1TS U3990 ( .A0(n3412), .A1(n3683), .B0(n3405), .B1(n3688), .C0(n3424), .C1(n3682), .Y(n1823) );
XOR2X1TS U3991 ( .A(n1824), .B(n3408), .Y(mult_x_23_n1172) );
INVX2TS U3992 ( .A(n1825), .Y(n1828) );
INVX2TS U3993 ( .A(n1826), .Y(n1827) );
INVX2TS U3994 ( .A(n1829), .Y(n1885) );
INVX2TS U3995 ( .A(n1884), .Y(n1830) );
AOI21X1TS U3996 ( .A0(n1887), .A1(n1885), .B0(n1830), .Y(n1835) );
INVX2TS U3997 ( .A(n1831), .Y(n1833) );
NAND2X1TS U3998 ( .A(n1833), .B(n1832), .Y(n1834) );
XOR2X1TS U3999 ( .A(n1835), .B(n1834), .Y(n1836) );
AOI222X1TS U4000 ( .A0(n3412), .A1(n3693), .B0(n3405), .B1(n3699), .C0(n3424), .C1(n3621), .Y(n1837) );
XOR2X1TS U4001 ( .A(n1838), .B(n3408), .Y(mult_x_23_n1175) );
CLKXOR2X2TS U4002 ( .A(Op_MX[41]), .B(Op_MX[40]), .Y(n2591) );
INVX4TS U4003 ( .A(n899), .Y(n3506) );
BUFX4TS U4004 ( .A(n1872), .Y(n3507) );
BUFX4TS U4005 ( .A(n2834), .Y(n3488) );
AOI21X1TS U4006 ( .A0(n3506), .A1(n3674), .B0(n1841), .Y(n1842) );
INVX4TS U4007 ( .A(n6557), .Y(n3484) );
XOR2X1TS U4008 ( .A(n1843), .B(n3484), .Y(mult_x_23_n1227) );
CLKXOR2X2TS U4009 ( .A(Op_MX[35]), .B(Op_MX[34]), .Y(n5086) );
BUFX4TS U4010 ( .A(n2188), .Y(n3569) );
XNOR2X1TS U4011 ( .A(Op_MX[33]), .B(Op_MX[34]), .Y(n1844) );
BUFX3TS U4012 ( .A(n1897), .Y(n2189) );
INVX4TS U4013 ( .A(n763), .Y(n3593) );
AOI222X1TS U4014 ( .A0(n3569), .A1(n3693), .B0(n2189), .B1(n3699), .C0(n3593), .C1(n3621), .Y(n1846) );
INVX4TS U4015 ( .A(n6550), .Y(n2191) );
XOR2X1TS U4016 ( .A(n1847), .B(n2191), .Y(mult_x_23_n1291) );
INVX2TS U4017 ( .A(n1994), .Y(n1849) );
INVX2TS U4018 ( .A(n1997), .Y(n1848) );
XNOR2X4TS U4019 ( .A(n1852), .B(n1851), .Y(n4611) );
BUFX4TS U4020 ( .A(n1853), .Y(n4092) );
BUFX4TS U4021 ( .A(n790), .Y(n4602) );
AOI222X1TS U4022 ( .A0(n4162), .A1(n4602), .B0(n4161), .B1(Op_MX[15]), .C0(
n4160), .C1(n4607), .Y(n1854) );
XOR2X1TS U4023 ( .A(n1855), .B(n4093), .Y(mult_x_24_n1317) );
NAND2X1TS U4024 ( .A(n2165), .B(n2163), .Y(n1858) );
XNOR2X1TS U4025 ( .A(n2166), .B(n1858), .Y(n1859) );
BUFX4TS U4026 ( .A(n1859), .Y(n5540) );
INVX2TS U4027 ( .A(n5540), .Y(n1860) );
INVX2TS U4028 ( .A(n1861), .Y(n1862) );
AOI21X1TS U4029 ( .A0(n1864), .A1(n1863), .B0(n1862), .Y(n1869) );
INVX2TS U4030 ( .A(n1865), .Y(n1867) );
NAND2X1TS U4031 ( .A(n1867), .B(n1866), .Y(n1868) );
XNOR2X4TS U4032 ( .A(n1869), .B(n1868), .Y(n3717) );
AOI222X1TS U4033 ( .A0(n3412), .A1(n3715), .B0(n3405), .B1(n3721), .C0(n3424), .C1(n3713), .Y(n1870) );
XOR2X1TS U4034 ( .A(n1871), .B(n3408), .Y(mult_x_23_n1179) );
BUFX3TS U4035 ( .A(n1872), .Y(n3482) );
AOI222X1TS U4036 ( .A0(n3488), .A1(n3682), .B0(n3482), .B1(n3693), .C0(n3506), .C1(n3692), .Y(n1873) );
XOR2X1TS U4037 ( .A(n1874), .B(n3484), .Y(mult_x_23_n1232) );
AOI222X1TS U4038 ( .A0(n3488), .A1(n3703), .B0(n3482), .B1(n3721), .C0(n3506), .C1(n3713), .Y(n1875) );
XOR2X1TS U4039 ( .A(n1876), .B(n3484), .Y(mult_x_23_n1237) );
BUFX4TS U4040 ( .A(n1877), .Y(n3510) );
OAI21X1TS U4041 ( .A0(n3611), .A1(n3510), .B0(n1878), .Y(n1879) );
XOR2X1TS U4042 ( .A(n1879), .B(n3484), .Y(mult_x_23_n1228) );
NAND2X1TS U4043 ( .A(n1880), .B(n2464), .Y(n1881) );
XOR2X1TS U4044 ( .A(n2741), .B(n1881), .Y(n1882) );
INVX2TS U4045 ( .A(n5569), .Y(n1883) );
NAND2X1TS U4046 ( .A(n1885), .B(n1884), .Y(n1886) );
XNOR2X1TS U4047 ( .A(n1887), .B(n1886), .Y(n1888) );
AOI222X1TS U4048 ( .A0(n3569), .A1(n3699), .B0(n2189), .B1(n3704), .C0(n3593), .C1(n3698), .Y(n1889) );
XOR2X1TS U4049 ( .A(n1890), .B(n2191), .Y(mult_x_23_n1292) );
AOI222X1TS U4050 ( .A0(n3569), .A1(n3694), .B0(n2189), .B1(n3693), .C0(n3593), .C1(n3692), .Y(n1891) );
XOR2X1TS U4051 ( .A(n1892), .B(n2191), .Y(mult_x_23_n1290) );
AOI222X1TS U4052 ( .A0(n3412), .A1(n3694), .B0(n3405), .B1(n3693), .C0(n3424), .C1(n3692), .Y(n1893) );
XOR2X1TS U4053 ( .A(n1894), .B(n3408), .Y(mult_x_23_n1174) );
AOI222X1TS U4054 ( .A0(n3412), .A1(n3699), .B0(n3405), .B1(n3704), .C0(n3424), .C1(n3698), .Y(n1895) );
XOR2X1TS U4055 ( .A(n1896), .B(n3408), .Y(mult_x_23_n1176) );
BUFX4TS U4056 ( .A(n1897), .Y(n3595) );
AOI222X1TS U4057 ( .A0(n3569), .A1(n767), .B0(n3595), .B1(n3678), .C0(n3593),
.C1(n3609), .Y(n1898) );
XOR2X1TS U4058 ( .A(n1899), .B(n2191), .Y(mult_x_23_n1286) );
BUFX4TS U4059 ( .A(n1900), .Y(n3599) );
AOI21X1TS U4060 ( .A0(n3593), .A1(n3674), .B0(n1901), .Y(n1902) );
XOR2X1TS U4061 ( .A(n1903), .B(n2191), .Y(mult_x_23_n1285) );
AOI222X1TS U4062 ( .A0(n3569), .A1(n3678), .B0(n2189), .B1(n3683), .C0(n3593), .C1(n3677), .Y(n1904) );
XOR2X1TS U4063 ( .A(n1905), .B(n2191), .Y(mult_x_23_n1287) );
AOI222X1TS U4064 ( .A0(n3488), .A1(n3677), .B0(n3482), .B1(n3694), .C0(n3506), .C1(n3687), .Y(n1906) );
XOR2X1TS U4065 ( .A(n1907), .B(n3484), .Y(mult_x_23_n1231) );
INVX2TS U4066 ( .A(n1908), .Y(n1917) );
NAND2X1TS U4067 ( .A(n1917), .B(n1915), .Y(n1909) );
XNOR2X1TS U4068 ( .A(n1918), .B(n1909), .Y(n1910) );
XOR2X1TS U4069 ( .A(n1912), .B(n3408), .Y(mult_x_23_n1178) );
AOI222X1TS U4070 ( .A0(n3488), .A1(n3692), .B0(n3482), .B1(n3704), .C0(n3506), .C1(n3698), .Y(n1913) );
XOR2X1TS U4071 ( .A(n1914), .B(n3484), .Y(mult_x_23_n1234) );
INVX2TS U4072 ( .A(n1915), .Y(n1916) );
AOI21X1TS U4073 ( .A0(n1918), .A1(n1917), .B0(n1916), .Y(n1923) );
INVX2TS U4074 ( .A(n1919), .Y(n1921) );
NAND2X1TS U4075 ( .A(n1921), .B(n1920), .Y(n1922) );
XOR2X1TS U4076 ( .A(n1923), .B(n1922), .Y(n1924) );
AOI222X1TS U4077 ( .A0(n3412), .A1(n3704), .B0(n3405), .B1(n3709), .C0(n3424), .C1(n3703), .Y(n1925) );
OAI21X1TS U4078 ( .A0(n3706), .A1(n3407), .B0(n1925), .Y(n1926) );
XOR2X1TS U4079 ( .A(n1926), .B(n3408), .Y(mult_x_23_n1177) );
AOI222X1TS U4080 ( .A0(n3569), .A1(n3688), .B0(n2189), .B1(n3694), .C0(n3593), .C1(n3687), .Y(n1927) );
XOR2X1TS U4081 ( .A(n1928), .B(n2191), .Y(mult_x_23_n1289) );
AOI222X1TS U4082 ( .A0(n3569), .A1(n3683), .B0(n2189), .B1(n3688), .C0(n3593), .C1(n3682), .Y(n1929) );
XOR2X1TS U4083 ( .A(n1930), .B(n2191), .Y(mult_x_23_n1288) );
AOI222X1TS U4084 ( .A0(n3488), .A1(n3687), .B0(n3482), .B1(n3699), .C0(n3506), .C1(n3621), .Y(n1931) );
XOR2X1TS U4085 ( .A(n1932), .B(n3484), .Y(mult_x_23_n1233) );
AOI222X1TS U4086 ( .A0(n3488), .A1(n3621), .B0(n3482), .B1(n3709), .C0(n3506), .C1(n3703), .Y(n1933) );
XOR2X1TS U4087 ( .A(n1934), .B(n3484), .Y(mult_x_23_n1235) );
NAND2X1TS U4088 ( .A(n1935), .B(n2619), .Y(n1936) );
XOR2X1TS U4089 ( .A(n2621), .B(n1936), .Y(n1937) );
INVX2TS U4090 ( .A(n5586), .Y(n1938) );
XNOR2X4TS U4091 ( .A(n1944), .B(n1943), .Y(n4600) );
BUFX4TS U4092 ( .A(n791), .Y(n4592) );
AOI222X1TS U4093 ( .A0(n4162), .A1(n4592), .B0(n4161), .B1(n793), .C0(n4160),
.C1(n4609), .Y(n1945) );
XOR2X1TS U4094 ( .A(n1946), .B(n4075), .Y(mult_x_24_n1315) );
AOI222X1TS U4095 ( .A0(n3569), .A1(n3704), .B0(n2189), .B1(n3709), .C0(n3593), .C1(n3703), .Y(n1947) );
XOR2X1TS U4096 ( .A(n1948), .B(n2191), .Y(mult_x_23_n1293) );
AOI222X1TS U4097 ( .A0(n3569), .A1(n3715), .B0(n2189), .B1(n3721), .C0(n3593), .C1(n3713), .Y(n1949) );
XOR2X1TS U4098 ( .A(n1950), .B(n2191), .Y(mult_x_23_n1295) );
XOR2X1TS U4099 ( .A(n795), .B(Op_MX[33]), .Y(n1956) );
XNOR2X1TS U4100 ( .A(n1956), .B(n1951), .Y(n1955) );
NAND2X1TS U4101 ( .A(Op_MX[4]), .B(Op_MX[31]), .Y(n1952) );
NAND2X1TS U4102 ( .A(n2112), .B(n2104), .Y(n1954) );
CLKXOR2X2TS U4103 ( .A(n1955), .B(n1954), .Y(n5474) );
XOR2X1TS U4104 ( .A(n1958), .B(n5083), .Y(n1959) );
NAND2X1TS U4105 ( .A(n795), .B(Op_MX[33]), .Y(n1960) );
NAND2X1TS U4106 ( .A(n1964), .B(n1968), .Y(n1965) );
XOR2X1TS U4107 ( .A(n1970), .B(n1965), .Y(n1966) );
INVX2TS U4108 ( .A(n5592), .Y(n1967) );
NAND2X1TS U4109 ( .A(n1973), .B(n1972), .Y(n1974) );
XNOR2X1TS U4110 ( .A(n1975), .B(n1974), .Y(n1976) );
INVX2TS U4111 ( .A(n5589), .Y(n1977) );
CMPR32X2TS U4112 ( .A(n1979), .B(n4954), .C(n1978), .CO(
DP_OP_169J43_123_4229_n906), .S(DP_OP_169J43_123_4229_n907) );
AOI222X1TS U4113 ( .A0(n3488), .A1(n3698), .B0(n3482), .B1(n3715), .C0(n3506), .C1(n3708), .Y(n1980) );
XOR2X1TS U4114 ( .A(n1981), .B(n3484), .Y(mult_x_23_n1236) );
INVX2TS U4115 ( .A(n1982), .Y(n2025) );
AOI21X1TS U4116 ( .A0(n2018), .A1(n865), .B0(n1983), .Y(n1986) );
NAND2X1TS U4117 ( .A(n743), .B(n1984), .Y(n1985) );
XNOR2X4TS U4118 ( .A(n1986), .B(n1985), .Y(n4374) );
BUFX3TS U4119 ( .A(n1987), .Y(n4090) );
BUFX4TS U4120 ( .A(Op_MX[5]), .Y(n4546) );
BUFX3TS U4121 ( .A(n1988), .Y(n4089) );
AOI222X1TS U4122 ( .A0(n4090), .A1(n4546), .B0(n4089), .B1(Op_MX[4]), .C0(
n1989), .C1(n4372), .Y(n1990) );
XOR2X1TS U4123 ( .A(n1991), .B(n4093), .Y(mult_x_24_n1328) );
AOI222X1TS U4124 ( .A0(n3569), .A1(n3709), .B0(n2189), .B1(n3715), .C0(n3593), .C1(n3708), .Y(n1992) );
XOR2X1TS U4125 ( .A(n1993), .B(n2191), .Y(mult_x_23_n1294) );
XNOR2X4TS U4126 ( .A(n2002), .B(n2001), .Y(n4605) );
BUFX4TS U4127 ( .A(n793), .Y(n4597) );
AOI222X1TS U4128 ( .A0(n4162), .A1(n4597), .B0(n4161), .B1(n790), .C0(n4160),
.C1(n4615), .Y(n2003) );
XOR2X1TS U4129 ( .A(n2004), .B(n4093), .Y(mult_x_24_n1316) );
INVX2TS U4130 ( .A(n4079), .Y(n2007) );
INVX2TS U4131 ( .A(n4082), .Y(n2006) );
XNOR2X4TS U4132 ( .A(n2010), .B(n2009), .Y(n4538) );
BUFX4TS U4133 ( .A(Op_MX[8]), .Y(n4645) );
AOI222X1TS U4134 ( .A0(n4090), .A1(n4645), .B0(n4089), .B1(Op_MX[7]), .C0(
n1989), .C1(n4536), .Y(n2011) );
XOR2X1TS U4135 ( .A(n2012), .B(n4093), .Y(mult_x_24_n1325) );
AOI222X1TS U4136 ( .A0(n3569), .A1(n3721), .B0(n2189), .B1(n3726), .C0(n3583), .C1(n3719), .Y(n2013) );
XOR2X1TS U4137 ( .A(n2014), .B(n2191), .Y(mult_x_23_n1296) );
INVX2TS U4138 ( .A(n5577), .Y(n2015) );
NAND2X1TS U4139 ( .A(n865), .B(n2016), .Y(n2017) );
CLKXOR2X4TS U4140 ( .A(n2018), .B(n2017), .Y(n4488) );
BUFX4TS U4141 ( .A(Op_MX[4]), .Y(n4486) );
AOI222X1TS U4142 ( .A0(n4090), .A1(n4486), .B0(n4089), .B1(Op_MX[3]), .C0(
n1989), .C1(n4485), .Y(n2019) );
XOR2X1TS U4143 ( .A(n2020), .B(n4075), .Y(mult_x_24_n1329) );
INVX2TS U4144 ( .A(n2021), .Y(n2023) );
NAND2X1TS U4145 ( .A(n2023), .B(n2022), .Y(n2024) );
XOR2X1TS U4146 ( .A(n2025), .B(n2024), .Y(n2026) );
BUFX4TS U4147 ( .A(Op_MX[3]), .Y(n4493) );
AOI222X1TS U4148 ( .A0(n4090), .A1(n4493), .B0(n4089), .B1(Op_MX[2]), .C0(
n1989), .C1(n4158), .Y(n2027) );
XOR2X1TS U4149 ( .A(n2028), .B(n4093), .Y(mult_x_24_n1330) );
XNOR2X4TS U4150 ( .A(n2032), .B(n2031), .Y(n4543) );
BUFX4TS U4151 ( .A(Op_MX[7]), .Y(n4541) );
AOI222X1TS U4152 ( .A0(n4090), .A1(n4541), .B0(n4089), .B1(n731), .C0(n1989),
.C1(n4540), .Y(n2033) );
XOR2X1TS U4153 ( .A(n2034), .B(n4075), .Y(mult_x_24_n1326) );
NAND2X1TS U4154 ( .A(n867), .B(n2035), .Y(n2036) );
XNOR2X1TS U4155 ( .A(n3791), .B(n2036), .Y(n2037) );
INVX4TS U4156 ( .A(n2037), .Y(n4412) );
BUFX4TS U4157 ( .A(Op_MX[14]), .Y(n4614) );
AOI222X1TS U4158 ( .A0(n4090), .A1(n4614), .B0(n4089), .B1(Op_MX[13]), .C0(
n1989), .C1(n4626), .Y(n2038) );
XOR2X1TS U4159 ( .A(n2039), .B(n4075), .Y(mult_x_24_n1319) );
NAND2X1TS U4160 ( .A(n866), .B(n2041), .Y(n2042) );
XNOR2X4TS U4161 ( .A(n2043), .B(n2042), .Y(n4617) );
BUFX4TS U4162 ( .A(Op_MX[15]), .Y(n4608) );
AOI222X1TS U4163 ( .A0(n4162), .A1(n4608), .B0(n4161), .B1(Op_MX[14]), .C0(
n4160), .C1(n4621), .Y(n2044) );
XOR2X1TS U4164 ( .A(n2045), .B(n4093), .Y(mult_x_24_n1318) );
INVX2TS U4165 ( .A(n2059), .Y(n2046) );
INVX2TS U4166 ( .A(n2058), .Y(n2048) );
AOI21X1TS U4167 ( .A0(n2048), .A1(n2063), .B0(n2047), .Y(n2049) );
OAI21X1TS U4168 ( .A0(n2075), .A1(n2050), .B0(n2049), .Y(n2051) );
XNOR2X4TS U4169 ( .A(n2055), .B(n2054), .Y(n4623) );
BUFX4TS U4170 ( .A(Op_MX[13]), .Y(n4524) );
AOI222X1TS U4171 ( .A0(n4090), .A1(n4524), .B0(n4161), .B1(Op_MX[12]), .C0(
n1989), .C1(n4632), .Y(n2056) );
XOR2X1TS U4172 ( .A(n2057), .B(n4075), .Y(mult_x_24_n1320) );
XNOR2X4TS U4173 ( .A(n2065), .B(n2064), .Y(n4629) );
BUFX4TS U4174 ( .A(Op_MX[12]), .Y(n4619) );
AOI222X1TS U4175 ( .A0(n4162), .A1(n4619), .B0(n4089), .B1(n794), .C0(n1989),
.C1(n4639), .Y(n2066) );
XOR2X1TS U4176 ( .A(n2067), .B(n4075), .Y(mult_x_24_n1321) );
NAND2X1TS U4177 ( .A(n740), .B(n2068), .Y(n2069) );
XNOR2X1TS U4178 ( .A(n4085), .B(n2069), .Y(n2070) );
BUFX4TS U4179 ( .A(n795), .Y(n4547) );
AOI222X1TS U4180 ( .A0(n4090), .A1(n4547), .B0(n4089), .B1(Op_MX[5]), .C0(
n1989), .C1(n4545), .Y(n2071) );
XOR2X1TS U4181 ( .A(n2072), .B(n4093), .Y(mult_x_24_n1327) );
OAI21X1TS U4182 ( .A0(n2075), .A1(n2074), .B0(n4070), .Y(n2076) );
XNOR2X4TS U4183 ( .A(n2080), .B(n2079), .Y(n4634) );
BUFX4TS U4184 ( .A(n794), .Y(n4625) );
AOI222X1TS U4185 ( .A0(n4090), .A1(n4625), .B0(n4089), .B1(n744), .C0(n1989),
.C1(n4647), .Y(n2081) );
XOR2X1TS U4186 ( .A(n2082), .B(n4075), .Y(mult_x_24_n1322) );
OAI31X1TS U4187 ( .A0(n1634), .A1(n6392), .A2(n6539), .B0(n2083), .Y(n418)
);
OAI32X1TS U4188 ( .A0(n6401), .A1(n2085), .A2(overflow_flag), .B0(n6405),
.B1(n6580), .Y(n287) );
INVX2TS U4189 ( .A(zero_flag), .Y(n6390) );
AOI211XLTS U4190 ( .A0(n6582), .A1(n6390), .B0(n2087), .C0(n2086), .Y(n2089)
);
NAND3X1TS U4191 ( .A(n2088), .B(n6535), .C(n6536), .Y(n2094) );
NOR2XLTS U4192 ( .A(n2089), .B(n6345), .Y(n713) );
OAI21XLTS U4193 ( .A0(n6540), .A1(n6345), .B0(FS_Module_state_reg[3]), .Y(
n2093) );
NAND2X1TS U4194 ( .A(n5629), .B(n2091), .Y(n2092) );
INVX2TS U4195 ( .A(n5635), .Y(n5649) );
OAI211XLTS U4196 ( .A0(n765), .A1(n6390), .B0(n2093), .C0(n5774), .Y(n714)
);
INVX2TS U4197 ( .A(n2094), .Y(ready) );
OR2X1TS U4198 ( .A(n2096), .B(n2095), .Y(n6562) );
INVX2TS U4199 ( .A(mult_x_24_n942), .Y(mult_x_24_n557) );
AOI21X1TS U4200 ( .A0(n2738), .A1(n2737), .B0(n2097), .Y(n2098) );
XNOR2X1TS U4201 ( .A(n2099), .B(Op_MY[25]), .Y(n2100) );
INVX2TS U4202 ( .A(n5551), .Y(n2101) );
NOR2X1TS U4203 ( .A(n2101), .B(n2847), .Y(DP_OP_169J43_123_4229_n1329) );
INVX2TS U4204 ( .A(DP_OP_169J43_123_4229_n713), .Y(
DP_OP_169J43_123_4229_n714) );
AOI21X1TS U4205 ( .A0(n3299), .A1(n3682), .B0(n2102), .Y(n2103) );
OAI21X1TS U4206 ( .A0(n3685), .A1(n3317), .B0(n2103), .Y(mult_x_23_n1120) );
INVX4TS U4207 ( .A(n896), .Y(n5495) );
XOR2X1TS U4208 ( .A(Op_MX[4]), .B(Op_MX[31]), .Y(n2110) );
XNOR2X1TS U4209 ( .A(n2110), .B(n2105), .Y(n2109) );
NAND2X1TS U4210 ( .A(Op_MX[29]), .B(Op_MX[2]), .Y(n2106) );
NAND2X1TS U4211 ( .A(n2145), .B(n2144), .Y(n2108) );
CLKXOR2X2TS U4212 ( .A(n2109), .B(n2108), .Y(n5476) );
XOR2X1TS U4213 ( .A(Op_MX[30]), .B(Op_MX[31]), .Y(n2111) );
XOR2X1TS U4214 ( .A(n2113), .B(n2112), .Y(n2114) );
BUFX4TS U4215 ( .A(n2116), .Y(n5506) );
OAI22X1TS U4216 ( .A0(n2115), .A1(n5510), .B0(n5506), .B1(n896), .Y(n2158)
);
INVX4TS U4217 ( .A(n896), .Y(n5504) );
XNOR2X1TS U4218 ( .A(n5097), .B(n5504), .Y(n5509) );
XNOR2X1TS U4219 ( .A(n5093), .B(n5504), .Y(n2117) );
BUFX4TS U4220 ( .A(n2116), .Y(n5508) );
OAI22X1TS U4221 ( .A0(n5509), .A1(n5510), .B0(n2117), .B1(n5508), .Y(n2157)
);
NOR2X1TS U4222 ( .A(DP_OP_169J43_123_4229_n1300), .B(
DP_OP_169J43_123_4229_n1304), .Y(n4926) );
INVX2TS U4223 ( .A(n2118), .Y(n2133) );
NAND2X1TS U4224 ( .A(n2119), .B(n2131), .Y(n2120) );
XOR2X1TS U4225 ( .A(n2133), .B(n2120), .Y(n2121) );
XNOR2X1TS U4226 ( .A(n5505), .B(n5591), .Y(n2140) );
OAI22X1TS U4227 ( .A0(n2140), .A1(n5548), .B0(n2122), .B1(n1628), .Y(n2129)
);
BUFX3TS U4228 ( .A(n6538), .Y(n5475) );
XOR2X1TS U4229 ( .A(Op_MX[29]), .B(Op_MX[2]), .Y(n2141) );
XNOR2X1TS U4230 ( .A(n2141), .B(n2123), .Y(n2127) );
NAND2X1TS U4231 ( .A(n2125), .B(n2124), .Y(n2126) );
CLKXOR2X2TS U4232 ( .A(n2127), .B(n2126), .Y(n5512) );
NOR2BX1TS U4233 ( .AN(n5475), .B(n5512), .Y(n2128) );
INVX2TS U4234 ( .A(DP_OP_169J43_123_4229_n646), .Y(n4948) );
NAND2X1TS U4235 ( .A(n2129), .B(n2128), .Y(n4947) );
INVX2TS U4236 ( .A(n4947), .Y(n2130) );
AOI21X1TS U4237 ( .A0(n837), .A1(n4948), .B0(n2130), .Y(n4946) );
NAND2X1TS U4238 ( .A(n2136), .B(n2135), .Y(n2137) );
XNOR2X1TS U4239 ( .A(n2138), .B(n2137), .Y(n2139) );
XNOR2X1TS U4240 ( .A(n5502), .B(n5591), .Y(n2153) );
OAI22X1TS U4241 ( .A0(n2153), .A1(n5548), .B0(n2140), .B1(n5587), .Y(n2149)
);
CLKXOR2X2TS U4242 ( .A(Op_MX[29]), .B(Op_MX[28]), .Y(n2196) );
XOR2X1TS U4243 ( .A(n2142), .B(n2144), .Y(n2143) );
INVX4TS U4244 ( .A(n756), .Y(n5533) );
OAI22X1TS U4245 ( .A0(n5529), .A1(n756), .B0(n2146), .B1(n5545), .Y(n2152)
);
INVX4TS U4246 ( .A(n756), .Y(n5539) );
XNOR2X1TS U4247 ( .A(n5097), .B(n5539), .Y(n2150) );
XNOR2X1TS U4248 ( .A(n5098), .B(n5539), .Y(n2147) );
OAI22X1TS U4249 ( .A0(n2150), .A1(n5545), .B0(n5529), .B1(n2147), .Y(n2151)
);
NOR2X1TS U4250 ( .A(n2149), .B(n2148), .Y(n4942) );
NAND2X1TS U4251 ( .A(n2149), .B(n2148), .Y(n4943) );
OAI21X1TS U4252 ( .A0(n4946), .A1(n4942), .B0(n4943), .Y(n4940) );
NOR2BX1TS U4253 ( .AN(n5475), .B(n5476), .Y(n2162) );
XNOR2X1TS U4254 ( .A(n5505), .B(n5539), .Y(n2159) );
OAI22X1TS U4255 ( .A0(n2159), .A1(n5545), .B0(n2150), .B1(n5543), .Y(n2161)
);
ADDHX1TS U4256 ( .A(n2152), .B(n2151), .CO(n2160), .S(n2148) );
XNOR2X1TS U4257 ( .A(n5540), .B(n5591), .Y(n2173) );
OAI22X1TS U4258 ( .A0(n2173), .A1(n5548), .B0(n2153), .B1(n1628), .Y(n2154)
);
NAND2X1TS U4259 ( .A(n2155), .B(n2154), .Y(n4939) );
INVX2TS U4260 ( .A(n4939), .Y(n2156) );
XNOR2X1TS U4261 ( .A(n5502), .B(n5539), .Y(n5544) );
OAI22X1TS U4262 ( .A0(n5544), .A1(n5545), .B0(n2159), .B1(n5543), .Y(n2177)
);
CMPR32X2TS U4263 ( .A(n2162), .B(n2161), .C(n2160), .CO(n2176), .S(n2155) );
AOI21X1TS U4264 ( .A0(n2166), .A1(n2165), .B0(n2164), .Y(n2171) );
NAND2X1TS U4265 ( .A(n2169), .B(n2168), .Y(n2170) );
XOR2X1TS U4266 ( .A(n2171), .B(n2170), .Y(n2172) );
BUFX4TS U4267 ( .A(n2172), .Y(n5536) );
XNOR2X1TS U4268 ( .A(n5536), .B(n5591), .Y(n5597) );
OAI22X1TS U4269 ( .A0(n5597), .A1(n5548), .B0(n2173), .B1(n1628), .Y(n2174)
);
NOR2X1TS U4270 ( .A(n2175), .B(n2174), .Y(n4934) );
NAND2X1TS U4271 ( .A(n2175), .B(n2174), .Y(n4935) );
OAI21X1TS U4272 ( .A0(n4937), .A1(n4934), .B0(n4935), .Y(n4932) );
CMPR32X2TS U4273 ( .A(n2178), .B(n2177), .C(n2176), .CO(n2179), .S(n2175) );
NAND2X1TS U4274 ( .A(DP_OP_169J43_123_4229_n1305), .B(n2179), .Y(n4931) );
INVX2TS U4275 ( .A(n4931), .Y(n2180) );
NAND2X1TS U4276 ( .A(DP_OP_169J43_123_4229_n1300), .B(
DP_OP_169J43_123_4229_n1304), .Y(n4927) );
INVX2TS U4277 ( .A(n2403), .Y(n4920) );
INVX2TS U4278 ( .A(n4919), .Y(n2181) );
NAND2X1TS U4279 ( .A(DP_OP_169J43_123_4229_n1295), .B(
DP_OP_169J43_123_4229_n1299), .Y(n4918) );
NAND2X1TS U4280 ( .A(n2181), .B(n4918), .Y(n2182) );
XOR2X1TS U4281 ( .A(n2183), .B(n2191), .Y(n2270) );
NAND2X1TS U4282 ( .A(n3569), .B(n3312), .Y(n2184) );
XOR2X1TS U4283 ( .A(n2185), .B(n2191), .Y(n2213) );
NAND2X1TS U4284 ( .A(n830), .B(n2215), .Y(n2186) );
XOR2X1TS U4285 ( .A(n2186), .B(n2214), .Y(n2187) );
BUFX3TS U4286 ( .A(n2188), .Y(n3597) );
BUFX4TS U4287 ( .A(Op_MY[29]), .Y(n3594) );
BUFX4TS U4288 ( .A(Op_MY[28]), .Y(n3592) );
AOI222X1TS U4289 ( .A0(n3597), .A1(n3594), .B0(n2189), .B1(n3592), .C0(n3593), .C1(n3351), .Y(n2190) );
XOR2X1TS U4290 ( .A(n2192), .B(n2191), .Y(n2193) );
ADDHXLTS U4291 ( .A(n2194), .B(n2193), .CO(mult_x_23_n836), .S(n2290) );
NOR2X1TS U4292 ( .A(n2196), .B(mult_x_23_n1930), .Y(n2245) );
BUFX4TS U4293 ( .A(n2245), .Y(n3733) );
BUFX3TS U4294 ( .A(n3733), .Y(n3753) );
XNOR2X1TS U4295 ( .A(Op_MX[27]), .B(Op_MX[28]), .Y(n2195) );
NOR2BX1TS U4296 ( .AN(mult_x_23_n1930), .B(n2195), .Y(n2241) );
BUFX4TS U4297 ( .A(n2241), .Y(n3751) );
AOI222X1TS U4298 ( .A0(n3753), .A1(n3750), .B0(n3751), .B1(n3655), .C0(n3749), .C1(n3650), .Y(n2197) );
INVX4TS U4299 ( .A(n6552), .Y(n3746) );
XOR2X1TS U4300 ( .A(n2198), .B(n3746), .Y(n2289) );
INVX2TS U4301 ( .A(n2199), .Y(n2255) );
INVX2TS U4302 ( .A(n2200), .Y(n2253) );
INVX2TS U4303 ( .A(n2252), .Y(n2201) );
AOI21X1TS U4304 ( .A0(n2255), .A1(n2253), .B0(n2201), .Y(n2206) );
INVX2TS U4305 ( .A(n2202), .Y(n2204) );
NAND2X1TS U4306 ( .A(n2204), .B(n2203), .Y(n2205) );
XOR2X1TS U4307 ( .A(n2206), .B(n2205), .Y(n2207) );
INVX4TS U4308 ( .A(n6552), .Y(n3756) );
XNOR2X2TS U4309 ( .A(n3756), .B(Op_MX[30]), .Y(n2209) );
CLKXOR2X2TS U4310 ( .A(n6589), .B(Op_MX[31]), .Y(n2210) );
BUFX4TS U4311 ( .A(n2221), .Y(n3665) );
BUFX3TS U4312 ( .A(n2222), .Y(n3663) );
XNOR2X1TS U4313 ( .A(Op_MX[31]), .B(Op_MX[30]), .Y(n2208) );
BUFX4TS U4314 ( .A(n2226), .Y(n3661) );
AOI222X1TS U4315 ( .A0(n3663), .A1(n3660), .B0(n3661), .B1(n3588), .C0(n3659), .C1(n3582), .Y(n2211) );
XOR2X1TS U4316 ( .A(n2212), .B(n6589), .Y(n2288) );
NAND2X1TS U4317 ( .A(n3207), .B(n907), .Y(n2300) );
ADDHXLTS U4318 ( .A(n3600), .B(n2213), .CO(n2269), .S(n2275) );
NAND2X1TS U4319 ( .A(n2215), .B(n2214), .Y(n2218) );
NAND2X1TS U4320 ( .A(n872), .B(n2216), .Y(n2217) );
INVX4TS U4321 ( .A(n894), .Y(n3631) );
AOI222X1TS U4322 ( .A0(n3663), .A1(n3596), .B0(n3661), .B1(n3594), .C0(n3631), .C1(n3592), .Y(n2219) );
OAI21X1TS U4323 ( .A0(n831), .A1(n3665), .B0(n2219), .Y(n2220) );
XOR2X1TS U4324 ( .A(n2220), .B(n6589), .Y(n2274) );
BUFX4TS U4325 ( .A(n2222), .Y(n3641) );
XOR2X1TS U4326 ( .A(n2223), .B(n3637), .Y(n2260) );
NAND2X1TS U4327 ( .A(n3641), .B(n3312), .Y(n2224) );
OAI21X1TS U4328 ( .A0(n6546), .A1(n3636), .B0(n2224), .Y(n2225) );
XOR2X1TS U4329 ( .A(n2225), .B(n3637), .Y(n2248) );
BUFX3TS U4330 ( .A(n2226), .Y(n3634) );
AOI222X1TS U4331 ( .A0(n3663), .A1(n3594), .B0(n3634), .B1(n3592), .C0(n3631), .C1(n3351), .Y(n2227) );
XOR2X1TS U4332 ( .A(n2228), .B(n3637), .Y(n2239) );
INVX2TS U4333 ( .A(n2277), .Y(n2231) );
NAND2X1TS U4334 ( .A(n2231), .B(n2276), .Y(n2232) );
XOR2X1TS U4335 ( .A(n2278), .B(n2232), .Y(n2233) );
AOI222X1TS U4336 ( .A0(n3753), .A1(n3662), .B0(n3751), .B1(n3660), .C0(n3749), .C1(n3658), .Y(n2234) );
XOR2X1TS U4337 ( .A(n2235), .B(n3746), .Y(n2265) );
BUFX4TS U4338 ( .A(n2236), .Y(n3728) );
AOI222X1TS U4339 ( .A0(n3753), .A1(n3660), .B0(n3751), .B1(n3588), .C0(n3749), .C1(n3582), .Y(n2237) );
XOR2X1TS U4340 ( .A(n2238), .B(n3746), .Y(n2264) );
ADDHX1TS U4341 ( .A(n2240), .B(n2239), .CO(n2273), .S(n2263) );
BUFX3TS U4342 ( .A(n2241), .Y(n3720) );
INVX4TS U4343 ( .A(n758), .Y(n3714) );
AOI222X1TS U4344 ( .A0(n3753), .A1(n3594), .B0(n3720), .B1(n3592), .C0(n3714), .C1(n3351), .Y(n2242) );
XOR2X1TS U4345 ( .A(n2244), .B(n3746), .Y(n3242) );
NAND2X1TS U4346 ( .A(n3242), .B(n833), .Y(n3241) );
AOI222X1TS U4347 ( .A0(n3753), .A1(n3596), .B0(n3751), .B1(n3594), .C0(n3714), .C1(n3592), .Y(n2246) );
XOR2X1TS U4348 ( .A(n2247), .B(n3746), .Y(n2250) );
ADDHX1TS U4349 ( .A(n6589), .B(n2248), .CO(n2259), .S(n2249) );
NAND2X1TS U4350 ( .A(n2250), .B(n2249), .Y(n3237) );
INVX2TS U4351 ( .A(n3237), .Y(n2251) );
AOI21X1TS U4352 ( .A0(n3239), .A1(n3238), .B0(n2251), .Y(n3236) );
NAND2X1TS U4353 ( .A(n2253), .B(n2252), .Y(n2254) );
XNOR2X1TS U4354 ( .A(n2255), .B(n2254), .Y(n2256) );
AOI222X1TS U4355 ( .A0(n3753), .A1(n3588), .B0(n3751), .B1(n3596), .C0(n3714), .C1(n3587), .Y(n2257) );
XOR2X1TS U4356 ( .A(n2258), .B(n3746), .Y(n2262) );
ADDHX1TS U4357 ( .A(n2260), .B(n2259), .CO(n2240), .S(n2261) );
NOR2X1TS U4358 ( .A(n2262), .B(n2261), .Y(n3232) );
NAND2X1TS U4359 ( .A(n2262), .B(n2261), .Y(n3233) );
OAI21X1TS U4360 ( .A0(n3236), .A1(n3232), .B0(n3233), .Y(n3221) );
NAND2X1TS U4361 ( .A(n2264), .B(n2263), .Y(n3228) );
NAND2X1TS U4362 ( .A(n2266), .B(n2265), .Y(n3223) );
AOI21X1TS U4363 ( .A0(n2268), .A1(n3221), .B0(n2267), .Y(n3220) );
ADDHXLTS U4364 ( .A(n2270), .B(n2269), .CO(n2194), .S(n2293) );
AOI222X1TS U4365 ( .A0(n3663), .A1(n3588), .B0(n3661), .B1(n3596), .C0(n3631), .C1(n3587), .Y(n2271) );
XOR2X1TS U4366 ( .A(n2272), .B(n6589), .Y(n2292) );
CMPR32X2TS U4367 ( .A(n2275), .B(n2274), .C(n2273), .CO(n2291), .S(n2266) );
OAI21X1TS U4368 ( .A0(n2278), .A1(n2277), .B0(n2276), .Y(n2283) );
INVX2TS U4369 ( .A(n2279), .Y(n2281) );
NAND2X1TS U4370 ( .A(n2281), .B(n2280), .Y(n2282) );
AOI222X1TS U4371 ( .A0(n3753), .A1(n3655), .B0(n3751), .B1(n3662), .C0(n3749), .C1(n3654), .Y(n2284) );
XOR2X1TS U4372 ( .A(n2285), .B(n3746), .Y(n2286) );
NOR2X1TS U4373 ( .A(n2287), .B(n2286), .Y(n3216) );
NAND2X1TS U4374 ( .A(n2287), .B(n2286), .Y(n3217) );
CMPR32X2TS U4375 ( .A(n2290), .B(n2289), .C(n2288), .CO(n2297), .S(n2295) );
CMPR32X2TS U4376 ( .A(n2293), .B(n2292), .C(n2291), .CO(n2294), .S(n2287) );
NAND2X1TS U4377 ( .A(n2295), .B(n2294), .Y(n3213) );
INVX2TS U4378 ( .A(n3213), .Y(n2296) );
AOI21X1TS U4379 ( .A0(n3215), .A1(n906), .B0(n2296), .Y(n3204) );
NAND2X1TS U4380 ( .A(mult_x_23_n831), .B(n2297), .Y(n3210) );
INVX2TS U4381 ( .A(n3210), .Y(n3205) );
NAND2X1TS U4382 ( .A(mult_x_23_n826), .B(mult_x_23_n830), .Y(n3206) );
INVX2TS U4383 ( .A(n3206), .Y(n2298) );
AOI21X1TS U4384 ( .A0(n3207), .A1(n3205), .B0(n2298), .Y(n2299) );
INVX2TS U4385 ( .A(n2412), .Y(n3198) );
NOR2X2TS U4386 ( .A(mult_x_23_n821), .B(mult_x_23_n825), .Y(n3197) );
INVX2TS U4387 ( .A(n3197), .Y(n2301) );
NAND2X1TS U4388 ( .A(mult_x_23_n821), .B(mult_x_23_n825), .Y(n3196) );
NAND2X1TS U4389 ( .A(n2301), .B(n3196), .Y(n2302) );
AOI21X1TS U4390 ( .A0(n3299), .A1(n3687), .B0(n2303), .Y(n2304) );
OAI21X1TS U4391 ( .A0(n3690), .A1(n3317), .B0(n2304), .Y(mult_x_23_n1121) );
INVX4TS U4392 ( .A(n6551), .Y(n4635) );
CLKXOR2X2TS U4393 ( .A(Op_MY[1]), .B(n4635), .Y(n2330) );
BUFX4TS U4394 ( .A(n2327), .Y(n4641) );
NOR2X1TS U4395 ( .A(n2330), .B(n6537), .Y(n2328) );
BUFX4TS U4396 ( .A(n2328), .Y(n4627) );
NAND2X1TS U4397 ( .A(n4627), .B(n4159), .Y(n2305) );
OAI21X1TS U4398 ( .A0(n4641), .A1(n6547), .B0(n2305), .Y(mult_x_24_n2066) );
NAND2X1TS U4399 ( .A(n879), .B(n878), .Y(n2399) );
XNOR2X2TS U4400 ( .A(Op_MY[6]), .B(n802), .Y(n2317) );
CLKXOR2X2TS U4401 ( .A(Op_MY[7]), .B(n782), .Y(n2318) );
BUFX4TS U4402 ( .A(n2307), .Y(n4496) );
XNOR2X1TS U4403 ( .A(Op_MY[6]), .B(Op_MY[7]), .Y(n2316) );
BUFX4TS U4404 ( .A(n2315), .Y(n4466) );
BUFX4TS U4405 ( .A(n2314), .Y(n4469) );
XOR2X1TS U4406 ( .A(n2306), .B(n4464), .Y(n2337) );
NAND2X1TS U4407 ( .A(n4469), .B(n4159), .Y(n2308) );
XOR2X1TS U4408 ( .A(n2309), .B(n4464), .Y(n2340) );
NAND2X1TS U4409 ( .A(n838), .B(n2310), .Y(n2312) );
XOR2X1TS U4410 ( .A(n2312), .B(n2311), .Y(n2313) );
BUFX3TS U4411 ( .A(n2314), .Y(n4494) );
BUFX4TS U4412 ( .A(Op_MX[2]), .Y(n4491) );
BUFX3TS U4413 ( .A(n2315), .Y(n4492) );
BUFX4TS U4414 ( .A(Op_MX[1]), .Y(n4490) );
BUFX4TS U4415 ( .A(n2873), .Y(n4462) );
AOI222X1TS U4416 ( .A0(n4494), .A1(n4491), .B0(n4492), .B1(n4490), .C0(n4462), .C1(n4139), .Y(n2319) );
XOR2X1TS U4417 ( .A(n2320), .B(n783), .Y(n2659) );
XNOR2X2TS U4418 ( .A(n6598), .B(Op_MY[3]), .Y(n2323) );
CLKXOR2X2TS U4419 ( .A(Op_MY[4]), .B(n801), .Y(n2324) );
BUFX4TS U4420 ( .A(n2345), .Y(n4550) );
NOR2X1TS U4421 ( .A(n2324), .B(n2323), .Y(n2343) );
BUFX3TS U4422 ( .A(n2343), .Y(n4548) );
XNOR2X1TS U4423 ( .A(Op_MY[3]), .B(Op_MY[4]), .Y(n2322) );
NOR2BX1TS U4424 ( .AN(n2323), .B(n2322), .Y(n2321) );
AOI222X1TS U4425 ( .A0(n4548), .A1(n4546), .B0(n729), .B1(n4486), .C0(n2348),
.C1(n4372), .Y(n2325) );
XOR2X1TS U4426 ( .A(n2326), .B(n803), .Y(n2334) );
BUFX3TS U4427 ( .A(n2328), .Y(n4648) );
XNOR2X1TS U4428 ( .A(Op_MY[1]), .B(Op_MY[0]), .Y(n2329) );
NOR2BX1TS U4429 ( .AN(n6537), .B(n2329), .Y(n2363) );
BUFX3TS U4430 ( .A(n2363), .Y(n4646) );
AOI222X1TS U4431 ( .A0(n4648), .A1(n4637), .B0(n4646), .B1(n4541), .C0(n2360), .C1(n4536), .Y(n2331) );
XOR2X1TS U4432 ( .A(n2332), .B(Op_MY[2]), .Y(n2333) );
ADDHXLTS U4433 ( .A(n2337), .B(n2336), .CO(n2660), .S(n2387) );
AOI222X1TS U4434 ( .A0(n4548), .A1(n4486), .B0(n772), .B1(n4493), .C0(n2348),
.C1(n4485), .Y(n2338) );
XOR2X1TS U4435 ( .A(n2339), .B(n802), .Y(n2386) );
ADDHXLTS U4436 ( .A(n783), .B(n2340), .CO(n2336), .S(n2357) );
AOI222X1TS U4437 ( .A0(n4548), .A1(n4493), .B0(n729), .B1(n4491), .C0(n2348),
.C1(n4490), .Y(n2341) );
XOR2X1TS U4438 ( .A(n2342), .B(n803), .Y(n2356) );
BUFX4TS U4439 ( .A(n2343), .Y(n4527) );
INVX4TS U4440 ( .A(n6549), .Y(n4522) );
XOR2X1TS U4441 ( .A(n2344), .B(n4522), .Y(n2376) );
NAND2X1TS U4442 ( .A(n4527), .B(n4159), .Y(n2346) );
XOR2X1TS U4443 ( .A(n2347), .B(n4522), .Y(n2369) );
BUFX4TS U4444 ( .A(n2348), .Y(n4520) );
AOI222X1TS U4445 ( .A0(n4548), .A1(n4491), .B0(n729), .B1(n4490), .C0(n4520),
.C1(n4139), .Y(n2349) );
XOR2X1TS U4446 ( .A(n2350), .B(n802), .Y(n2353) );
AOI222X1TS U4447 ( .A0(n4648), .A1(n4540), .B0(n4646), .B1(n4486), .C0(n2360), .C1(n4372), .Y(n2351) );
XOR2X1TS U4448 ( .A(n2352), .B(Op_MY[2]), .Y(n2380) );
ADDHX1TS U4449 ( .A(n2354), .B(n2353), .CO(n2355), .S(n2379) );
CMPR32X2TS U4450 ( .A(n2357), .B(n2356), .C(n2355), .CO(n2385), .S(n2382) );
AOI222X1TS U4451 ( .A0(n4648), .A1(n4536), .B0(n4646), .B1(n4546), .C0(n2360), .C1(n4545), .Y(n2358) );
XOR2X1TS U4452 ( .A(n2359), .B(Op_MY[2]), .Y(n2381) );
NOR2X2TS U4453 ( .A(n2382), .B(n2381), .Y(n4024) );
BUFX4TS U4454 ( .A(n2360), .Y(n4613) );
AOI222X1TS U4455 ( .A0(n4648), .A1(n4485), .B0(n4646), .B1(n4490), .C0(n4613), .C1(n4139), .Y(n2361) );
BUFX4TS U4456 ( .A(n2363), .Y(n4620) );
XOR2X1TS U4457 ( .A(n2364), .B(n4635), .Y(n4044) );
INVX2TS U4458 ( .A(mult_x_24_n2066), .Y(n2365) );
NAND2X1TS U4459 ( .A(n4044), .B(n2366), .Y(n4043) );
NOR2X1TS U4460 ( .A(n848), .B(n4043), .Y(n4041) );
AOI222X1TS U4461 ( .A0(n4648), .A1(n4372), .B0(n4646), .B1(n4491), .C0(n2360), .C1(n4490), .Y(n2367) );
XOR2X1TS U4462 ( .A(n2368), .B(n4635), .Y(n2371) );
ADDHX1TS U4463 ( .A(n804), .B(n2369), .CO(n2375), .S(n2370) );
NAND2X1TS U4464 ( .A(n2371), .B(n2370), .Y(n4039) );
INVX2TS U4465 ( .A(n4039), .Y(n2372) );
AOI21X1TS U4466 ( .A0(n4041), .A1(n4040), .B0(n2372), .Y(n4038) );
AOI222X1TS U4467 ( .A0(n4648), .A1(n4545), .B0(n4646), .B1(n4493), .C0(n2360), .C1(n4485), .Y(n2373) );
XOR2X1TS U4468 ( .A(n2374), .B(Op_MY[2]), .Y(n2378) );
ADDHX1TS U4469 ( .A(n2376), .B(n2375), .CO(n2354), .S(n2377) );
NOR2X1TS U4470 ( .A(n2378), .B(n2377), .Y(n4034) );
NAND2X1TS U4471 ( .A(n2378), .B(n2377), .Y(n4035) );
OAI21X1TS U4472 ( .A0(n4038), .A1(n4034), .B0(n4035), .Y(n4023) );
NAND2X1TS U4473 ( .A(n2380), .B(n2379), .Y(n4030) );
NAND2X1TS U4474 ( .A(n2382), .B(n2381), .Y(n4025) );
AOI21X1TS U4475 ( .A0(n2384), .A1(n4023), .B0(n2383), .Y(n4022) );
CMPR32X2TS U4476 ( .A(n2387), .B(n2386), .C(n2385), .CO(n2392), .S(n2391) );
AOI222X1TS U4477 ( .A0(n4648), .A1(n4644), .B0(n4646), .B1(n4547), .C0(n2360), .C1(n4540), .Y(n2388) );
XOR2X1TS U4478 ( .A(n2389), .B(n6598), .Y(n2390) );
NOR2X1TS U4479 ( .A(n2391), .B(n2390), .Y(n4018) );
NAND2X1TS U4480 ( .A(n2391), .B(n2390), .Y(n4019) );
OAI21X1TS U4481 ( .A0(n4022), .A1(n4018), .B0(n4019), .Y(n4007) );
NAND2X1TS U4482 ( .A(n2393), .B(n2392), .Y(n4014) );
NAND2X1TS U4483 ( .A(mult_x_24_n916), .B(n2394), .Y(n4009) );
NAND2X1TS U4484 ( .A(mult_x_24_n911), .B(mult_x_24_n915), .Y(n4004) );
INVX2TS U4485 ( .A(n4004), .Y(n4000) );
NAND2X1TS U4486 ( .A(mult_x_24_n906), .B(mult_x_24_n910), .Y(n4001) );
INVX2TS U4487 ( .A(n4001), .Y(n2397) );
AOI21X1TS U4488 ( .A0(n879), .A1(n4000), .B0(n2397), .Y(n2398) );
OAI21X1TS U4489 ( .A0(n2399), .A1(n3999), .B0(n2398), .Y(n2422) );
INVX2TS U4490 ( .A(n2422), .Y(n3993) );
INVX2TS U4491 ( .A(n3992), .Y(n2400) );
NAND2X1TS U4492 ( .A(mult_x_24_n899), .B(mult_x_24_n905), .Y(n3991) );
NAND2X1TS U4493 ( .A(n2400), .B(n3991), .Y(n2401) );
NOR2X2TS U4494 ( .A(DP_OP_169J43_123_4229_n1288), .B(
DP_OP_169J43_123_4229_n1294), .Y(n4921) );
NAND2X1TS U4495 ( .A(DP_OP_169J43_123_4229_n1288), .B(
DP_OP_169J43_123_4229_n1294), .Y(n4922) );
NAND2X1TS U4496 ( .A(n890), .B(n891), .Y(n2407) );
NAND2X1TS U4497 ( .A(DP_OP_169J43_123_4229_n1282), .B(
DP_OP_169J43_123_4229_n1287), .Y(n4915) );
INVX2TS U4498 ( .A(n4915), .Y(n4911) );
NAND2X1TS U4499 ( .A(DP_OP_169J43_123_4229_n1274), .B(
DP_OP_169J43_123_4229_n1281), .Y(n4912) );
INVX2TS U4500 ( .A(n4912), .Y(n2405) );
AOI21X1TS U4501 ( .A0(n890), .A1(n4911), .B0(n2405), .Y(n2406) );
INVX2TS U4502 ( .A(n2498), .Y(n4904) );
NOR2X2TS U4503 ( .A(DP_OP_169J43_123_4229_n1266), .B(
DP_OP_169J43_123_4229_n1273), .Y(n4903) );
INVX2TS U4504 ( .A(n4903), .Y(n2408) );
NAND2X1TS U4505 ( .A(DP_OP_169J43_123_4229_n1266), .B(
DP_OP_169J43_123_4229_n1273), .Y(n4902) );
NAND2X1TS U4506 ( .A(n2408), .B(n4902), .Y(n2409) );
INVX2TS U4507 ( .A(mult_x_23_n521), .Y(mult_x_23_n526) );
NOR2X2TS U4508 ( .A(mult_x_23_n814), .B(mult_x_23_n820), .Y(n3199) );
NOR2X1TS U4509 ( .A(n3197), .B(n3199), .Y(n2411) );
NAND2X1TS U4510 ( .A(mult_x_23_n814), .B(mult_x_23_n820), .Y(n3200) );
OAI21X1TS U4511 ( .A0(n3199), .A1(n3196), .B0(n3200), .Y(n2410) );
NAND2X1TS U4512 ( .A(n902), .B(n901), .Y(n2415) );
NAND2X1TS U4513 ( .A(mult_x_23_n807), .B(mult_x_23_n813), .Y(n3193) );
INVX2TS U4514 ( .A(n3193), .Y(n3189) );
NAND2X1TS U4515 ( .A(mult_x_23_n800), .B(mult_x_23_n806), .Y(n3190) );
INVX2TS U4516 ( .A(n3190), .Y(n2413) );
AOI21X1TS U4517 ( .A0(n902), .A1(n3189), .B0(n2413), .Y(n2414) );
OAI21X2TS U4518 ( .A0(n3188), .A1(n2415), .B0(n2414), .Y(n2432) );
INVX2TS U4519 ( .A(n2432), .Y(n3182) );
NOR2X2TS U4520 ( .A(mult_x_23_n792), .B(mult_x_23_n799), .Y(n3181) );
INVX2TS U4521 ( .A(n3181), .Y(n2416) );
NAND2X1TS U4522 ( .A(mult_x_23_n792), .B(mult_x_23_n799), .Y(n3180) );
NAND2X1TS U4523 ( .A(n2416), .B(n3180), .Y(n2417) );
INVX2TS U4524 ( .A(mult_x_24_n948), .Y(mult_x_24_n594) );
AOI21X1TS U4525 ( .A0(n3299), .A1(n3621), .B0(n2418), .Y(n2419) );
OAI21X1TS U4526 ( .A0(n3623), .A1(n3317), .B0(n2419), .Y(mult_x_23_n1122) );
INVX2TS U4527 ( .A(DP_OP_169J43_123_4229_n739), .Y(
DP_OP_169J43_123_4229_n740) );
NOR2X2TS U4528 ( .A(mult_x_24_n892), .B(mult_x_24_n898), .Y(n3994) );
NAND2X1TS U4529 ( .A(mult_x_24_n892), .B(mult_x_24_n898), .Y(n3995) );
NOR2X2TS U4530 ( .A(mult_x_24_n877), .B(mult_x_24_n884), .Y(n3982) );
NOR2X1TS U4531 ( .A(mult_x_24_n885), .B(mult_x_24_n891), .Y(n3980) );
NOR2X1TS U4532 ( .A(n3982), .B(n3980), .Y(n3975) );
NAND2X1TS U4533 ( .A(n3975), .B(n3977), .Y(n2425) );
NAND2X1TS U4534 ( .A(mult_x_24_n885), .B(mult_x_24_n891), .Y(n3987) );
NAND2X1TS U4535 ( .A(mult_x_24_n877), .B(mult_x_24_n884), .Y(n3983) );
OAI21X1TS U4536 ( .A0(n3982), .A1(n3987), .B0(n3983), .Y(n3974) );
NAND2X1TS U4537 ( .A(mult_x_24_n869), .B(mult_x_24_n876), .Y(n3976) );
INVX2TS U4538 ( .A(n3976), .Y(n2423) );
AOI21X1TS U4539 ( .A0(n3974), .A1(n3977), .B0(n2423), .Y(n2424) );
OAI21X1TS U4540 ( .A0(n3973), .A1(n2425), .B0(n2424), .Y(n2536) );
INVX2TS U4541 ( .A(n2536), .Y(n3967) );
NOR2X2TS U4542 ( .A(mult_x_24_n861), .B(mult_x_24_n868), .Y(n3966) );
INVX2TS U4543 ( .A(n3966), .Y(n2426) );
NAND2X1TS U4544 ( .A(mult_x_24_n861), .B(mult_x_24_n868), .Y(n3965) );
NAND2X1TS U4545 ( .A(n2426), .B(n3965), .Y(n2427) );
INVX2TS U4546 ( .A(mult_x_24_n954), .Y(mult_x_24_n649) );
AOI21X1TS U4547 ( .A0(n3299), .A1(n3708), .B0(n2428), .Y(n2429) );
OAI21X1TS U4548 ( .A0(n3711), .A1(n3317), .B0(n2429), .Y(mult_x_23_n1124) );
NOR2X2TS U4549 ( .A(mult_x_23_n784), .B(mult_x_23_n791), .Y(n3183) );
NOR2X1TS U4550 ( .A(n3183), .B(n3181), .Y(n2431) );
NAND2X1TS U4551 ( .A(mult_x_23_n784), .B(mult_x_23_n791), .Y(n3184) );
OAI21X1TS U4552 ( .A0(n3183), .A1(n3180), .B0(n3184), .Y(n2430) );
NOR2X2TS U4553 ( .A(mult_x_23_n766), .B(mult_x_23_n775), .Y(n3175) );
NOR2X1TS U4554 ( .A(mult_x_23_n776), .B(mult_x_23_n783), .Y(n2970) );
NOR2X1TS U4555 ( .A(n3175), .B(n2970), .Y(n3167) );
NAND2X1TS U4556 ( .A(mult_x_23_n776), .B(mult_x_23_n783), .Y(n3171) );
NAND2X1TS U4557 ( .A(mult_x_23_n766), .B(mult_x_23_n775), .Y(n3176) );
OAI21X1TS U4558 ( .A0(n3175), .A1(n3171), .B0(n3176), .Y(n3166) );
NAND2X1TS U4559 ( .A(mult_x_23_n756), .B(mult_x_23_n765), .Y(n3168) );
INVX2TS U4560 ( .A(n3168), .Y(n2433) );
AOI21X1TS U4561 ( .A0(n3166), .A1(n904), .B0(n2433), .Y(n2434) );
NOR2X1TS U4562 ( .A(mult_x_23_n746), .B(mult_x_23_n755), .Y(n3158) );
INVX2TS U4563 ( .A(n3158), .Y(n3163) );
NOR2X2TS U4564 ( .A(mult_x_23_n724), .B(mult_x_23_n734), .Y(n3153) );
NAND2X1TS U4565 ( .A(mult_x_23_n746), .B(mult_x_23_n755), .Y(n3162) );
INVX2TS U4566 ( .A(n3162), .Y(n2437) );
NAND2X1TS U4567 ( .A(mult_x_23_n735), .B(mult_x_23_n745), .Y(n3159) );
INVX2TS U4568 ( .A(n3159), .Y(n2436) );
AOI21X1TS U4569 ( .A0(n903), .A1(n2437), .B0(n2436), .Y(n3151) );
NAND2X1TS U4570 ( .A(mult_x_23_n724), .B(mult_x_23_n734), .Y(n3154) );
OAI21X1TS U4571 ( .A0(n3151), .A1(n3153), .B0(n3154), .Y(n2438) );
NOR2X2TS U4572 ( .A(mult_x_23_n691), .B(mult_x_23_n701), .Y(n3134) );
NOR2X2TS U4573 ( .A(mult_x_23_n680), .B(mult_x_23_n690), .Y(n3129) );
NOR2X2TS U4574 ( .A(mult_x_23_n702), .B(mult_x_23_n712), .Y(n3141) );
NAND2X1TS U4575 ( .A(mult_x_23_n713), .B(mult_x_23_n723), .Y(n3146) );
NAND2X1TS U4576 ( .A(mult_x_23_n702), .B(mult_x_23_n712), .Y(n3142) );
OAI21X1TS U4577 ( .A0(n3141), .A1(n3146), .B0(n3142), .Y(n3127) );
NAND2X1TS U4578 ( .A(mult_x_23_n691), .B(mult_x_23_n701), .Y(n3135) );
NAND2X1TS U4579 ( .A(mult_x_23_n680), .B(mult_x_23_n690), .Y(n3130) );
AOI21X1TS U4580 ( .A0(n3127), .A1(n2441), .B0(n2440), .Y(n2442) );
NOR2X2TS U4581 ( .A(mult_x_23_n658), .B(mult_x_23_n668), .Y(n3116) );
NOR2X2TS U4582 ( .A(mult_x_23_n669), .B(mult_x_23_n679), .Y(n3121) );
NOR2X2TS U4583 ( .A(mult_x_23_n636), .B(mult_x_23_n646), .Y(n2456) );
NAND2X1TS U4584 ( .A(mult_x_23_n658), .B(mult_x_23_n668), .Y(n3117) );
OAI21X1TS U4585 ( .A0(n3116), .A1(n3122), .B0(n3117), .Y(n2451) );
NAND2X1TS U4586 ( .A(mult_x_23_n647), .B(mult_x_23_n657), .Y(n3112) );
NAND2X1TS U4587 ( .A(mult_x_23_n636), .B(mult_x_23_n646), .Y(n2457) );
NOR2X1TS U4588 ( .A(mult_x_23_n625), .B(mult_x_23_n635), .Y(n2474) );
INVX2TS U4589 ( .A(n2474), .Y(n2462) );
NAND2X1TS U4590 ( .A(mult_x_23_n625), .B(mult_x_23_n635), .Y(n2476) );
INVX2TS U4591 ( .A(n2476), .Y(n2446) );
AOI21X1TS U4592 ( .A0(n2461), .A1(n2462), .B0(n2446), .Y(n2449) );
NOR2X2TS U4593 ( .A(mult_x_23_n615), .B(mult_x_23_n624), .Y(n2477) );
INVX2TS U4594 ( .A(n2477), .Y(n2447) );
NAND2X1TS U4595 ( .A(mult_x_23_n615), .B(mult_x_23_n624), .Y(n2475) );
NAND2X1TS U4596 ( .A(n2447), .B(n2475), .Y(n2448) );
INVX2TS U4597 ( .A(n2450), .Y(n2453) );
INVX2TS U4598 ( .A(n2451), .Y(n2452) );
OAI21X1TS U4599 ( .A0(n3125), .A1(n2453), .B0(n2452), .Y(n3115) );
INVX2TS U4600 ( .A(n2454), .Y(n3113) );
INVX2TS U4601 ( .A(n3112), .Y(n2455) );
AOI21X1TS U4602 ( .A0(n3115), .A1(n3113), .B0(n2455), .Y(n2460) );
INVX2TS U4603 ( .A(n2456), .Y(n2458) );
NAND2X1TS U4604 ( .A(n2458), .B(n2457), .Y(n2459) );
NAND2X1TS U4605 ( .A(n2462), .B(n2476), .Y(n2463) );
NAND2X1TS U4606 ( .A(n2468), .B(n2467), .Y(n2469) );
XNOR2X1TS U4607 ( .A(n2470), .B(n2469), .Y(n2471) );
INVX2TS U4608 ( .A(n5567), .Y(n2472) );
NOR2X1TS U4609 ( .A(n2472), .B(n4971), .Y(DP_OP_169J43_123_4229_n1333) );
INVX2TS U4610 ( .A(n5536), .Y(n2473) );
NOR2X1TS U4611 ( .A(n2473), .B(n4964), .Y(DP_OP_169J43_123_4229_n1339) );
INVX2TS U4612 ( .A(DP_OP_169J43_123_4229_n963), .Y(
DP_OP_169J43_123_4229_n964) );
INVX2TS U4613 ( .A(n2973), .Y(n2479) );
OAI21X1TS U4614 ( .A0(n2477), .A1(n2476), .B0(n2475), .Y(n2978) );
INVX2TS U4615 ( .A(n2978), .Y(n2478) );
NOR2X1TS U4616 ( .A(mult_x_23_n604), .B(mult_x_23_n614), .Y(n2972) );
INVX2TS U4617 ( .A(n2972), .Y(n3109) );
NAND2X1TS U4618 ( .A(mult_x_23_n604), .B(mult_x_23_n614), .Y(n3108) );
INVX2TS U4619 ( .A(n3108), .Y(n2481) );
AOI21X1TS U4620 ( .A0(n3111), .A1(n3109), .B0(n2481), .Y(n2484) );
NOR2X2TS U4621 ( .A(mult_x_23_n596), .B(mult_x_23_n603), .Y(n2976) );
INVX2TS U4622 ( .A(n2976), .Y(n2482) );
NAND2X1TS U4623 ( .A(mult_x_23_n596), .B(mult_x_23_n603), .Y(n2975) );
NAND2X1TS U4624 ( .A(n2482), .B(n2975), .Y(n2483) );
INVX2TS U4625 ( .A(n2487), .Y(n2703) );
INVX2TS U4626 ( .A(n2702), .Y(n2488) );
AOI21X1TS U4627 ( .A0(n2705), .A1(n2703), .B0(n2488), .Y(n2493) );
INVX2TS U4628 ( .A(n2489), .Y(n2491) );
NAND2X1TS U4629 ( .A(n2491), .B(n2490), .Y(n2492) );
XOR2X1TS U4630 ( .A(n2493), .B(n2492), .Y(n2494) );
AOI21X1TS U4631 ( .A0(n3289), .A1(n3725), .B0(n2495), .Y(n2496) );
OAI21X1TS U4632 ( .A0(n3729), .A1(n3317), .B0(n2496), .Y(mult_x_23_n1126) );
NOR2X2TS U4633 ( .A(DP_OP_169J43_123_4229_n1256), .B(
DP_OP_169J43_123_4229_n1265), .Y(n4905) );
NOR2X1TS U4634 ( .A(n4905), .B(n4903), .Y(n2499) );
NAND2X1TS U4635 ( .A(DP_OP_169J43_123_4229_n1256), .B(
DP_OP_169J43_123_4229_n1265), .Y(n4906) );
OAI21X1TS U4636 ( .A0(n4905), .A1(n4902), .B0(n4906), .Y(n2497) );
NAND2X1TS U4637 ( .A(n4896), .B(n898), .Y(n2502) );
NAND2X1TS U4638 ( .A(DP_OP_169J43_123_4229_n1247), .B(
DP_OP_169J43_123_4229_n1255), .Y(n4899) );
INVX2TS U4639 ( .A(n4899), .Y(n4894) );
NAND2X1TS U4640 ( .A(DP_OP_169J43_123_4229_n1236), .B(
DP_OP_169J43_123_4229_n1246), .Y(n4895) );
INVX2TS U4641 ( .A(n4895), .Y(n2500) );
AOI21X1TS U4642 ( .A0(n4896), .A1(n4894), .B0(n2500), .Y(n2501) );
NOR2X1TS U4643 ( .A(DP_OP_169J43_123_4229_n1225), .B(
DP_OP_169J43_123_4229_n1235), .Y(n4885) );
INVX2TS U4644 ( .A(n4885), .Y(n4890) );
NOR2X2TS U4645 ( .A(DP_OP_169J43_123_4229_n1200), .B(
DP_OP_169J43_123_4229_n1211), .Y(n4880) );
NAND2X1TS U4646 ( .A(DP_OP_169J43_123_4229_n1225), .B(
DP_OP_169J43_123_4229_n1235), .Y(n4889) );
INVX2TS U4647 ( .A(n4889), .Y(n2504) );
NAND2X1TS U4648 ( .A(DP_OP_169J43_123_4229_n1212), .B(
DP_OP_169J43_123_4229_n1224), .Y(n4886) );
INVX2TS U4649 ( .A(n4886), .Y(n2503) );
AOI21X1TS U4650 ( .A0(n753), .A1(n2504), .B0(n2503), .Y(n4878) );
NAND2X1TS U4651 ( .A(DP_OP_169J43_123_4229_n1200), .B(
DP_OP_169J43_123_4229_n1211), .Y(n4881) );
OAI21X1TS U4652 ( .A0(n4878), .A1(n4880), .B0(n4881), .Y(n2505) );
NOR2X2TS U4653 ( .A(DP_OP_169J43_123_4229_n1172), .B(
DP_OP_169J43_123_4229_n1185), .Y(n4868) );
NOR2X1TS U4654 ( .A(DP_OP_169J43_123_4229_n1186), .B(
DP_OP_169J43_123_4229_n1199), .Y(n4866) );
NAND2X1TS U4655 ( .A(DP_OP_169J43_123_4229_n1186), .B(
DP_OP_169J43_123_4229_n1199), .Y(n4873) );
NAND2X1TS U4656 ( .A(DP_OP_169J43_123_4229_n1172), .B(
DP_OP_169J43_123_4229_n1185), .Y(n4869) );
OAI21X1TS U4657 ( .A0(n4868), .A1(n4873), .B0(n4869), .Y(n4860) );
NAND2X1TS U4658 ( .A(DP_OP_169J43_123_4229_n1156), .B(
DP_OP_169J43_123_4229_n1171), .Y(n4862) );
INVX2TS U4659 ( .A(n4862), .Y(n2507) );
AOI21X1TS U4660 ( .A0(n4860), .A1(n4863), .B0(n2507), .Y(n2508) );
NOR2X1TS U4661 ( .A(DP_OP_169J43_123_4229_n1141), .B(
DP_OP_169J43_123_4229_n1155), .Y(n4850) );
INVX2TS U4662 ( .A(n4850), .Y(n4856) );
NOR2X2TS U4663 ( .A(DP_OP_169J43_123_4229_n1107), .B(
DP_OP_169J43_123_4229_n1123), .Y(n4845) );
NAND2X1TS U4664 ( .A(DP_OP_169J43_123_4229_n1141), .B(
DP_OP_169J43_123_4229_n1155), .Y(n4855) );
INVX2TS U4665 ( .A(n4855), .Y(n2511) );
NAND2X1TS U4666 ( .A(DP_OP_169J43_123_4229_n1124), .B(
DP_OP_169J43_123_4229_n1140), .Y(n4851) );
INVX2TS U4667 ( .A(n4851), .Y(n2510) );
AOI21X1TS U4668 ( .A0(n4852), .A1(n2511), .B0(n2510), .Y(n4843) );
NAND2X1TS U4669 ( .A(DP_OP_169J43_123_4229_n1107), .B(
DP_OP_169J43_123_4229_n1123), .Y(n4846) );
OAI21X1TS U4670 ( .A0(n4843), .A1(n4845), .B0(n4846), .Y(n2512) );
NOR2X2TS U4671 ( .A(DP_OP_169J43_123_4229_n1030), .B(
DP_OP_169J43_123_4229_n1049), .Y(n4821) );
NOR2X2TS U4672 ( .A(DP_OP_169J43_123_4229_n1050), .B(
DP_OP_169J43_123_4229_n1069), .Y(n4826) );
NOR2X2TS U4673 ( .A(DP_OP_169J43_123_4229_n1070), .B(
DP_OP_169J43_123_4229_n1087), .Y(n4833) );
NAND2X1TS U4674 ( .A(DP_OP_169J43_123_4229_n1070), .B(
DP_OP_169J43_123_4229_n1087), .Y(n4834) );
OAI21X1TS U4675 ( .A0(n4833), .A1(n4838), .B0(n4834), .Y(n4819) );
NAND2X1TS U4676 ( .A(DP_OP_169J43_123_4229_n1030), .B(
DP_OP_169J43_123_4229_n1049), .Y(n4822) );
NOR2X2TS U4677 ( .A(DP_OP_169J43_123_4229_n947), .B(
DP_OP_169J43_123_4229_n966), .Y(n2530) );
NOR2X2TS U4678 ( .A(DP_OP_169J43_123_4229_n1009), .B(
DP_OP_169J43_123_4229_n1029), .Y(n4813) );
NOR2X2TS U4679 ( .A(DP_OP_169J43_123_4229_n987), .B(
DP_OP_169J43_123_4229_n1008), .Y(n4808) );
NAND2X1TS U4680 ( .A(DP_OP_169J43_123_4229_n987), .B(
DP_OP_169J43_123_4229_n1008), .Y(n4809) );
NAND2X1TS U4681 ( .A(DP_OP_169J43_123_4229_n947), .B(
DP_OP_169J43_123_4229_n966), .Y(n2531) );
INVX2TS U4682 ( .A(n2629), .Y(n2571) );
INVX2TS U4683 ( .A(n2631), .Y(n2520) );
AOI21X1TS U4684 ( .A0(n2570), .A1(n2571), .B0(n2520), .Y(n2523) );
NOR2X2TS U4685 ( .A(DP_OP_169J43_123_4229_n910), .B(
DP_OP_169J43_123_4229_n928), .Y(n2632) );
INVX2TS U4686 ( .A(n2632), .Y(n2521) );
NAND2X1TS U4687 ( .A(DP_OP_169J43_123_4229_n910), .B(
DP_OP_169J43_123_4229_n928), .Y(n2630) );
NAND2X1TS U4688 ( .A(n2521), .B(n2630), .Y(n2522) );
INVX2TS U4689 ( .A(mult_x_23_n611), .Y(mult_x_23_n622) );
INVX2TS U4690 ( .A(n2524), .Y(n2527) );
INVX2TS U4691 ( .A(n2525), .Y(n2526) );
INVX2TS U4692 ( .A(n2528), .Y(n4805) );
INVX2TS U4693 ( .A(n4804), .Y(n2529) );
AOI21X1TS U4694 ( .A0(n4807), .A1(n4805), .B0(n2529), .Y(n2534) );
INVX2TS U4695 ( .A(n2530), .Y(n2532) );
NAND2X1TS U4696 ( .A(n2532), .B(n2531), .Y(n2533) );
INVX2TS U4697 ( .A(DP_OP_169J43_123_4229_n777), .Y(
DP_OP_169J43_123_4229_n778) );
INVX2TS U4698 ( .A(mult_x_23_n557), .Y(mult_x_23_n565) );
NOR2X1TS U4699 ( .A(mult_x_24_n820), .B(mult_x_24_n830), .Y(n3949) );
INVX2TS U4700 ( .A(n3949), .Y(n3954) );
NOR2X2TS U4701 ( .A(mult_x_24_n851), .B(mult_x_24_n860), .Y(n3968) );
NOR2X1TS U4702 ( .A(n3968), .B(n3966), .Y(n2537) );
NAND2X1TS U4703 ( .A(mult_x_24_n851), .B(mult_x_24_n860), .Y(n3969) );
OAI21X1TS U4704 ( .A0(n3968), .A1(n3965), .B0(n3969), .Y(n2535) );
NAND2X1TS U4705 ( .A(n886), .B(n887), .Y(n2540) );
NAND2X1TS U4706 ( .A(mult_x_24_n841), .B(mult_x_24_n850), .Y(n3962) );
INVX2TS U4707 ( .A(n3962), .Y(n3958) );
NAND2X1TS U4708 ( .A(mult_x_24_n831), .B(mult_x_24_n840), .Y(n3959) );
INVX2TS U4709 ( .A(n3959), .Y(n2538) );
AOI21X1TS U4710 ( .A0(n886), .A1(n3958), .B0(n2538), .Y(n2539) );
OAI21X4TS U4711 ( .A0(n3957), .A1(n2540), .B0(n2539), .Y(n3939) );
NAND2X1TS U4712 ( .A(mult_x_24_n820), .B(mult_x_24_n830), .Y(n3953) );
INVX2TS U4713 ( .A(n3953), .Y(n2542) );
NAND2X1TS U4714 ( .A(mult_x_24_n809), .B(mult_x_24_n819), .Y(n3950) );
INVX2TS U4715 ( .A(n3950), .Y(n2541) );
AOI21X1TS U4716 ( .A0(n885), .A1(n2542), .B0(n2541), .Y(n3940) );
NAND2X1TS U4717 ( .A(mult_x_24_n798), .B(mult_x_24_n808), .Y(n3946) );
INVX2TS U4718 ( .A(n3946), .Y(n3942) );
NAND2X1TS U4719 ( .A(mult_x_24_n785), .B(mult_x_24_n797), .Y(n3943) );
INVX2TS U4720 ( .A(n3943), .Y(n2543) );
AOI21X1TS U4721 ( .A0(n883), .A1(n3942), .B0(n2543), .Y(n2544) );
OAI21X1TS U4722 ( .A0(n3940), .A1(n2545), .B0(n2544), .Y(n2546) );
NOR2X2TS U4723 ( .A(mult_x_24_n735), .B(mult_x_24_n746), .Y(n3918) );
NOR2X2TS U4724 ( .A(mult_x_24_n723), .B(mult_x_24_n734), .Y(n3913) );
NAND2X1TS U4725 ( .A(n882), .B(n881), .Y(n3923) );
NOR2X2TS U4726 ( .A(mult_x_24_n747), .B(mult_x_24_n758), .Y(n3927) );
NAND2X1TS U4727 ( .A(mult_x_24_n772), .B(mult_x_24_n784), .Y(n3936) );
INVX2TS U4728 ( .A(n3936), .Y(n3932) );
NAND2X1TS U4729 ( .A(mult_x_24_n759), .B(mult_x_24_n771), .Y(n3933) );
INVX2TS U4730 ( .A(n3933), .Y(n2548) );
AOI21X1TS U4731 ( .A0(n881), .A1(n3932), .B0(n2548), .Y(n3924) );
NAND2X1TS U4732 ( .A(mult_x_24_n747), .B(mult_x_24_n758), .Y(n3928) );
OAI21X1TS U4733 ( .A0(n3924), .A1(n3927), .B0(n3928), .Y(n3911) );
NAND2X1TS U4734 ( .A(mult_x_24_n735), .B(mult_x_24_n746), .Y(n3919) );
NAND2X1TS U4735 ( .A(mult_x_24_n723), .B(mult_x_24_n734), .Y(n3914) );
AOI21X1TS U4736 ( .A0(n3911), .A1(n2550), .B0(n2549), .Y(n2551) );
OAI21X4TS U4737 ( .A0(n3910), .A1(n2552), .B0(n2551), .Y(n3773) );
NOR2X2TS U4738 ( .A(mult_x_24_n699), .B(mult_x_24_n710), .Y(n3900) );
NOR2X2TS U4739 ( .A(mult_x_24_n711), .B(mult_x_24_n722), .Y(n3905) );
NOR2X2TS U4740 ( .A(mult_x_24_n675), .B(mult_x_24_n686), .Y(n2565) );
NAND2X1TS U4741 ( .A(mult_x_24_n711), .B(mult_x_24_n722), .Y(n3906) );
NAND2X1TS U4742 ( .A(mult_x_24_n699), .B(mult_x_24_n710), .Y(n3901) );
OAI21X1TS U4743 ( .A0(n3900), .A1(n3906), .B0(n3901), .Y(n2560) );
NAND2X1TS U4744 ( .A(mult_x_24_n687), .B(mult_x_24_n698), .Y(n3896) );
NAND2X1TS U4745 ( .A(mult_x_24_n675), .B(mult_x_24_n686), .Y(n2566) );
NOR2X1TS U4746 ( .A(mult_x_24_n663), .B(mult_x_24_n674), .Y(n2641) );
INVX2TS U4747 ( .A(n2641), .Y(n2584) );
NAND2X1TS U4748 ( .A(mult_x_24_n663), .B(mult_x_24_n674), .Y(n2643) );
INVX2TS U4749 ( .A(n2643), .Y(n2555) );
AOI21X1TS U4750 ( .A0(n2583), .A1(n2584), .B0(n2555), .Y(n2558) );
NOR2X2TS U4751 ( .A(mult_x_24_n652), .B(mult_x_24_n662), .Y(n2644) );
INVX2TS U4752 ( .A(n2644), .Y(n2556) );
NAND2X1TS U4753 ( .A(mult_x_24_n652), .B(mult_x_24_n662), .Y(n2642) );
NAND2X1TS U4754 ( .A(n2556), .B(n2642), .Y(n2557) );
INVX2TS U4755 ( .A(n2559), .Y(n2562) );
INVX2TS U4756 ( .A(n2560), .Y(n2561) );
OAI21X1TS U4757 ( .A0(n3909), .A1(n2562), .B0(n2561), .Y(n3899) );
INVX2TS U4758 ( .A(n2563), .Y(n3897) );
INVX2TS U4759 ( .A(n3896), .Y(n2564) );
AOI21X1TS U4760 ( .A0(n3899), .A1(n3897), .B0(n2564), .Y(n2569) );
INVX2TS U4761 ( .A(n2565), .Y(n2567) );
NAND2X1TS U4762 ( .A(n2567), .B(n2566), .Y(n2568) );
NAND2X1TS U4763 ( .A(n2571), .B(n2631), .Y(n2572) );
INVX2TS U4764 ( .A(n2575), .Y(n2577) );
NAND2X1TS U4765 ( .A(n2577), .B(n2576), .Y(n2578) );
XNOR2X1TS U4766 ( .A(n2579), .B(n2578), .Y(n2580) );
AOI21X1TS U4767 ( .A0(n3289), .A1(n3748), .B0(n2581), .Y(n2582) );
OAI21X1TS U4768 ( .A0(n3755), .A1(n1609), .B0(n2582), .Y(mult_x_23_n1129) );
NAND2X1TS U4769 ( .A(n2584), .B(n2643), .Y(n2585) );
XOR2X1TS U4770 ( .A(Op_MX[14]), .B(Op_MX[41]), .Y(n2592) );
XNOR2X1TS U4771 ( .A(n2592), .B(n2586), .Y(n2590) );
NAND2X1TS U4772 ( .A(Op_MX[12]), .B(Op_MX[39]), .Y(n2587) );
NAND2X1TS U4773 ( .A(n5060), .B(n5052), .Y(n2589) );
CLKXOR2X2TS U4774 ( .A(n2590), .B(n2589), .Y(n5341) );
XOR2X1TS U4775 ( .A(n2593), .B(n5026), .Y(n2594) );
BUFX4TS U4776 ( .A(n4951), .Y(n5337) );
NAND2X1TS U4777 ( .A(Op_MX[14]), .B(Op_MX[41]), .Y(n2595) );
INVX2TS U4778 ( .A(n5573), .Y(n2597) );
INVX2TS U4779 ( .A(n2598), .Y(n2599) );
NOR2X1TS U4780 ( .A(n2599), .B(n2603), .Y(n2606) );
NAND2X1TS U4781 ( .A(n2606), .B(n2600), .Y(n2609) );
INVX2TS U4782 ( .A(n2601), .Y(n2604) );
AOI21X1TS U4783 ( .A0(n2607), .A1(n2606), .B0(n2605), .Y(n2608) );
NAND2X1TS U4784 ( .A(n2612), .B(n2611), .Y(n2613) );
XNOR2X1TS U4785 ( .A(n2614), .B(n2613), .Y(n2615) );
INVX2TS U4786 ( .A(n5571), .Y(n2616) );
CMPR32X2TS U4787 ( .A(n2618), .B(n4950), .C(n2617), .CO(
DP_OP_169J43_123_4229_n788), .S(DP_OP_169J43_123_4229_n789) );
INVX2TS U4788 ( .A(DP_OP_169J43_123_4229_n889), .Y(
DP_OP_169J43_123_4229_n890) );
INVX2TS U4789 ( .A(DP_OP_169J43_123_4229_n827), .Y(
DP_OP_169J43_123_4229_n828) );
NAND2X1TS U4790 ( .A(n2624), .B(n2623), .Y(n2625) );
XNOR2X1TS U4791 ( .A(n2626), .B(n2625), .Y(n2627) );
INVX2TS U4792 ( .A(n5583), .Y(n2628) );
NOR2X1TS U4793 ( .A(n2628), .B(n4964), .Y(DP_OP_169J43_123_4229_n1337) );
INVX2TS U4794 ( .A(n4653), .Y(n2634) );
OAI21X1TS U4795 ( .A0(n2632), .A1(n2631), .B0(n2630), .Y(n4659) );
INVX2TS U4796 ( .A(n4659), .Y(n2633) );
INVX2TS U4797 ( .A(n4652), .Y(n4801) );
NAND2X1TS U4798 ( .A(DP_OP_169J43_123_4229_n893), .B(
DP_OP_169J43_123_4229_n909), .Y(n4800) );
INVX2TS U4799 ( .A(n4800), .Y(n2636) );
AOI21X1TS U4800 ( .A0(n4803), .A1(n4801), .B0(n2636), .Y(n2639) );
NOR2X2TS U4801 ( .A(DP_OP_169J43_123_4229_n876), .B(
DP_OP_169J43_123_4229_n892), .Y(n4656) );
INVX2TS U4802 ( .A(n4656), .Y(n2637) );
NAND2X1TS U4803 ( .A(DP_OP_169J43_123_4229_n876), .B(
DP_OP_169J43_123_4229_n892), .Y(n4655) );
NAND2X1TS U4804 ( .A(n2637), .B(n4655), .Y(n2638) );
INVX2TS U4805 ( .A(n5575), .Y(n2640) );
NOR2X1TS U4806 ( .A(n2640), .B(n4971), .Y(DP_OP_169J43_123_4229_n1335) );
INVX2TS U4807 ( .A(n3758), .Y(n2646) );
OAI21X1TS U4808 ( .A0(n2644), .A1(n2643), .B0(n2642), .Y(n3766) );
INVX2TS U4809 ( .A(n3766), .Y(n2645) );
INVX2TS U4810 ( .A(n3892), .Y(n3880) );
NAND2X1TS U4811 ( .A(mult_x_24_n642), .B(mult_x_24_n651), .Y(n3760) );
NAND2X1TS U4812 ( .A(n3891), .B(n3760), .Y(n2648) );
INVX2TS U4813 ( .A(n2649), .Y(n2652) );
INVX2TS U4814 ( .A(n2650), .Y(n2651) );
INVX2TS U4815 ( .A(n2654), .Y(n2791) );
NAND2X1TS U4816 ( .A(n2791), .B(n2789), .Y(n2655) );
XNOR2X1TS U4817 ( .A(n2792), .B(n2655), .Y(n2656) );
AOI21X1TS U4818 ( .A0(n3289), .A1(n3742), .B0(n2657), .Y(n2658) );
OAI21X1TS U4819 ( .A0(n3745), .A1(n1609), .B0(n2658), .Y(mult_x_23_n1128) );
ADDHXLTS U4820 ( .A(n2660), .B(n2659), .CO(mult_x_24_n921), .S(n2335) );
XOR2X1TS U4821 ( .A(n792), .B(Op_MX[49]), .Y(n2666) );
XNOR2X1TS U4822 ( .A(n2666), .B(n2661), .Y(n2665) );
NAND2X1TS U4823 ( .A(Op_MX[20]), .B(Op_MX[47]), .Y(n2662) );
NAND2X1TS U4824 ( .A(n5005), .B(n5004), .Y(n2664) );
XOR2X1TS U4825 ( .A(Op_MX[48]), .B(Op_MX[49]), .Y(n2667) );
XOR2X1TS U4826 ( .A(n2668), .B(n2671), .Y(n2669) );
NAND2X1TS U4827 ( .A(n2681), .B(n2679), .Y(n2673) );
AOI21X1TS U4828 ( .A0(n2688), .A1(n2679), .B0(n2682), .Y(n2672) );
NAND2X1TS U4829 ( .A(n2674), .B(n2683), .Y(n2675) );
XNOR2X1TS U4830 ( .A(n2676), .B(n2675), .Y(n2677) );
INVX2TS U4831 ( .A(n5557), .Y(n2678) );
NOR2X1TS U4832 ( .A(n2678), .B(n2847), .Y(n2734) );
INVX2TS U4833 ( .A(n2679), .Y(n2680) );
NOR2X1TS U4834 ( .A(n2680), .B(n2684), .Y(n2687) );
NAND2X1TS U4835 ( .A(n2687), .B(n2681), .Y(n2690) );
INVX2TS U4836 ( .A(n2682), .Y(n2685) );
AOI21X1TS U4837 ( .A0(n2688), .A1(n2687), .B0(n2686), .Y(n2689) );
NAND2X1TS U4838 ( .A(n2693), .B(n2692), .Y(n2694) );
XNOR2X1TS U4839 ( .A(n2695), .B(n2694), .Y(n2696) );
INVX2TS U4840 ( .A(n5555), .Y(n2697) );
CMPR32X2TS U4841 ( .A(n2699), .B(n2734), .C(n2698), .CO(
DP_OP_169J43_123_4229_n718), .S(DP_OP_169J43_123_4229_n719) );
AOI21X1TS U4842 ( .A0(n3299), .A1(n3713), .B0(n2700), .Y(n2701) );
OAI21X1TS U4843 ( .A0(n3717), .A1(n3317), .B0(n2701), .Y(mult_x_23_n1125) );
NAND2X1TS U4844 ( .A(n2703), .B(n2702), .Y(n2704) );
CLKXOR2X4TS U4845 ( .A(n2705), .B(n2704), .Y(n3735) );
AOI21X1TS U4846 ( .A0(n3289), .A1(n3731), .B0(n2706), .Y(n2707) );
OAI21X1TS U4847 ( .A0(n3735), .A1(n1609), .B0(n2707), .Y(n3259) );
INVX2TS U4848 ( .A(n3259), .Y(n2722) );
NAND2X1TS U4849 ( .A(n2708), .B(n2709), .Y(n2712) );
AOI21X1TS U4850 ( .A0(n2710), .A1(n2709), .B0(n6590), .Y(n2711) );
BUFX4TS U4851 ( .A(n2715), .Y(n3562) );
XOR2X1TS U4852 ( .A(n2720), .B(n805), .Y(n2721) );
CMPR32X2TS U4853 ( .A(n2722), .B(mult_x_23_n592), .C(n2721), .CO(
mult_x_23_n580), .S(mult_x_23_n581) );
MX2X1TS U4854 ( .A(P_Sgf[3]), .B(Sgf_operation_Result[3]), .S0(n6339), .Y(
n424) );
AOI21X1TS U4855 ( .A0(n3424), .A1(n3670), .B0(n3425), .Y(n2724) );
XOR2X1TS U4856 ( .A(n2725), .B(n3429), .Y(mult_x_23_n1168) );
NAND2X1TS U4857 ( .A(n2726), .B(n2729), .Y(n2731) );
NAND2X1TS U4858 ( .A(n2727), .B(n6543), .Y(n2736) );
AOI21X1TS U4859 ( .A0(n2738), .A1(n2729), .B0(n2728), .Y(n2730) );
XNOR2X1TS U4860 ( .A(n5547), .B(n5202), .Y(n5177) );
BUFX4TS U4861 ( .A(n2733), .Y(n5196) );
OAI22X1TS U4862 ( .A0(n5177), .A1(n5196), .B0(n5206), .B1(n900), .Y(n2746)
);
INVX2TS U4863 ( .A(n2734), .Y(n2745) );
XNOR2X1TS U4864 ( .A(n5551), .B(n5163), .Y(n5146) );
BUFX4TS U4865 ( .A(n2735), .Y(n5157) );
AOI21X1TS U4866 ( .A0(n2738), .A1(n2737), .B0(n2736), .Y(n2739) );
XNOR2X1TS U4867 ( .A(n2742), .B(n6545), .Y(n2743) );
XNOR2X1TS U4868 ( .A(n5549), .B(n5163), .Y(n5145) );
BUFX4TS U4869 ( .A(n5142), .Y(n5167) );
OAI22X1TS U4870 ( .A0(n5146), .A1(n5157), .B0(n5145), .B1(n5167), .Y(n2744)
);
CMPR32X2TS U4871 ( .A(n2746), .B(n2745), .C(n2744), .CO(
DP_OP_169J43_123_4229_n723), .S(DP_OP_169J43_123_4229_n724) );
BUFX4TS U4872 ( .A(n788), .Y(n4562) );
BUFX4TS U4873 ( .A(n2918), .Y(n4189) );
AOI222X1TS U4874 ( .A0(n4198), .A1(n4557), .B0(n4195), .B1(n4562), .C0(n4189), .C1(n4573), .Y(n2749) );
XOR2X1TS U4875 ( .A(n2750), .B(n4193), .Y(mult_x_24_n1338) );
AOI21X1TS U4876 ( .A0(n3299), .A1(n3698), .B0(n2751), .Y(n2752) );
OAI21X1TS U4877 ( .A0(n3701), .A1(n3317), .B0(n2752), .Y(n3247) );
INVX2TS U4878 ( .A(n3247), .Y(n2759) );
XOR2X1TS U4879 ( .A(n2757), .B(n6587), .Y(n2758) );
CMPR32X2TS U4880 ( .A(mult_x_23_n544), .B(n2759), .C(n2758), .CO(
mult_x_23_n535), .S(mult_x_23_n536) );
OAI21X1TS U4881 ( .A0(n3788), .A1(n2761), .B0(n2760), .Y(n2762) );
XNOR2X4TS U4882 ( .A(n2767), .B(n2766), .Y(n4570) );
AOI222X1TS U4883 ( .A0(n4198), .A1(n4562), .B0(n4195), .B1(n4567), .C0(n4189), .C1(n4578), .Y(n2768) );
XOR2X1TS U4884 ( .A(n2769), .B(n4193), .Y(mult_x_24_n1339) );
XNOR2X1TS U4885 ( .A(n5547), .B(n5269), .Y(n5244) );
OAI22X1TS U4886 ( .A0(n5244), .A1(n5257), .B0(n5273), .B1(n5008), .Y(n2773)
);
INVX2TS U4887 ( .A(n2770), .Y(n2772) );
XNOR2X1TS U4888 ( .A(n5559), .B(n5163), .Y(n5150) );
XNOR2X1TS U4889 ( .A(n5557), .B(n5163), .Y(n5149) );
OAI22X1TS U4890 ( .A0(n5150), .A1(n5157), .B0(n5149), .B1(n5167), .Y(n2771)
);
CMPR32X2TS U4891 ( .A(n2773), .B(n2772), .C(n2771), .CO(
DP_OP_169J43_123_4229_n755), .S(DP_OP_169J43_123_4229_n756) );
BUFX3TS U4892 ( .A(n2774), .Y(n3387) );
INVX4TS U4893 ( .A(n757), .Y(n3386) );
AOI222X1TS U4894 ( .A0(n3393), .A1(n3693), .B0(n3387), .B1(n3699), .C0(n3386), .C1(n3621), .Y(n2778) );
XOR2X1TS U4895 ( .A(n2779), .B(n3389), .Y(mult_x_23_n1146) );
AOI222X1TS U4896 ( .A0(n3458), .A1(n3678), .B0(n3451), .B1(n3683), .C0(n3448), .C1(n3677), .Y(n2781) );
XOR2X1TS U4897 ( .A(n2782), .B(n3454), .Y(mult_x_23_n1200) );
AOI21X1TS U4898 ( .A0(n3506), .A1(n3670), .B0(n3507), .Y(n2783) );
XOR2X1TS U4899 ( .A(n2784), .B(n3511), .Y(mult_x_23_n1226) );
BUFX4TS U4900 ( .A(n2785), .Y(n3402) );
AOI222X1TS U4901 ( .A0(n3400), .A1(n3655), .B0(n3399), .B1(n3662), .C0(n3398), .C1(n3654), .Y(n2787) );
XOR2X1TS U4902 ( .A(n2788), .B(n6586), .Y(mult_x_23_n1158) );
INVX2TS U4903 ( .A(n2789), .Y(n2790) );
AOI21X1TS U4904 ( .A0(n2792), .A1(n2791), .B0(n2790), .Y(n2797) );
INVX2TS U4905 ( .A(n2793), .Y(n2795) );
NAND2X1TS U4906 ( .A(n2795), .B(n2794), .Y(n2796) );
XNOR2X4TS U4907 ( .A(n2797), .B(n2796), .Y(n3740) );
BUFX3TS U4908 ( .A(n2798), .Y(n3426) );
AOI222X1TS U4909 ( .A0(n3426), .A1(n3738), .B0(n3425), .B1(n3743), .C0(n3419), .C1(n3737), .Y(n2799) );
XOR2X1TS U4910 ( .A(n2800), .B(n3429), .Y(mult_x_23_n1183) );
AOI222X1TS U4911 ( .A0(n3458), .A1(n3694), .B0(n3451), .B1(n3693), .C0(n3448), .C1(n3692), .Y(n2801) );
XOR2X1TS U4912 ( .A(n2802), .B(n3454), .Y(mult_x_23_n1203) );
AOI222X1TS U4913 ( .A0(n3733), .A1(n3693), .B0(n3720), .B1(n3699), .C0(n3714), .C1(n3621), .Y(n2803) );
XOR2X1TS U4914 ( .A(n2804), .B(n3756), .Y(mult_x_23_n1349) );
AOI222X1TS U4915 ( .A0(n3733), .A1(n767), .B0(n3751), .B1(n3678), .C0(n3714),
.C1(n3609), .Y(n2805) );
XOR2X1TS U4916 ( .A(n2806), .B(n3756), .Y(mult_x_23_n1344) );
CLKXOR2X2TS U4917 ( .A(Op_MY[19]), .B(n769), .Y(n2809) );
BUFX4TS U4918 ( .A(n2951), .Y(n4247) );
XNOR2X1TS U4919 ( .A(Op_MY[18]), .B(Op_MY[19]), .Y(n2807) );
NOR2BX1TS U4920 ( .AN(n2808), .B(n2807), .Y(n2952) );
BUFX4TS U4921 ( .A(n2952), .Y(n4244) );
BUFX4TS U4922 ( .A(Op_MX[21]), .Y(n4577) );
BUFX4TS U4923 ( .A(n4240), .Y(n4237) );
AOI222X1TS U4924 ( .A0(n4247), .A1(n4572), .B0(n4244), .B1(n4577), .C0(n4237), .C1(n4588), .Y(n2810) );
XOR2X1TS U4925 ( .A(n2811), .B(n4242), .Y(mult_x_24_n1371) );
AOI222X1TS U4926 ( .A0(n4527), .A1(n4602), .B0(n772), .B1(n4608), .C0(n4520),
.C1(n4607), .Y(n2812) );
XOR2X1TS U4927 ( .A(n2813), .B(n4522), .Y(mult_x_24_n1527) );
AOI222X1TS U4928 ( .A0(n4527), .A1(n4597), .B0(n772), .B1(n4602), .C0(n4520),
.C1(n4615), .Y(n2814) );
XOR2X1TS U4929 ( .A(n2815), .B(n4522), .Y(mult_x_24_n1526) );
XOR2X1TS U4930 ( .A(n789), .B(Op_MX[37]), .Y(n2821) );
XNOR2X1TS U4931 ( .A(n2821), .B(n2816), .Y(n2820) );
NAND2X1TS U4932 ( .A(Op_MX[8]), .B(Op_MX[35]), .Y(n2817) );
NAND2X1TS U4933 ( .A(n5091), .B(n5090), .Y(n2819) );
CLKXOR2X2TS U4934 ( .A(n2820), .B(n2819), .Y(n5407) );
XOR2X1TS U4935 ( .A(Op_MX[36]), .B(Op_MX[37]), .Y(n2822) );
XNOR2X2TS U4936 ( .A(n794), .B(n805), .Y(n5055) );
XOR2X1TS U4937 ( .A(n2823), .B(n5055), .Y(n2824) );
NAND2X1TS U4938 ( .A(n789), .B(Op_MX[37]), .Y(n2825) );
CMPR32X2TS U4939 ( .A(n2830), .B(n2829), .C(n2828), .CO(
DP_OP_169J43_123_4229_n841), .S(DP_OP_169J43_123_4229_n842) );
XOR2X1TS U4940 ( .A(n2831), .B(n3484), .Y(n3356) );
NAND2X1TS U4941 ( .A(n3488), .B(n3312), .Y(n2832) );
OAI21X1TS U4942 ( .A0(n6546), .A1(n1877), .B0(n2832), .Y(n2833) );
XOR2X1TS U4943 ( .A(n2833), .B(n3484), .Y(n3359) );
BUFX3TS U4944 ( .A(n2834), .Y(n3508) );
AOI222X1TS U4945 ( .A0(n3508), .A1(n3587), .B0(n3482), .B1(n3592), .C0(n3506), .C1(n3351), .Y(n2835) );
XOR2X1TS U4946 ( .A(n2836), .B(n3484), .Y(n2837) );
ADDHXLTS U4947 ( .A(n2838), .B(n2837), .CO(mult_x_23_n803), .S(n2846) );
AOI222X1TS U4948 ( .A0(n3597), .A1(n3750), .B0(n3595), .B1(n3655), .C0(n3583), .C1(n3650), .Y(n2839) );
XOR2X1TS U4949 ( .A(n2840), .B(n3600), .Y(n2845) );
AOI222X1TS U4950 ( .A0(n3560), .A1(n3654), .B0(n3559), .B1(n3588), .C0(n3558), .C1(n3582), .Y(n2842) );
XOR2X1TS U4951 ( .A(n2843), .B(n6588), .Y(n2844) );
CMPR32X2TS U4952 ( .A(n2846), .B(n2845), .C(n2844), .CO(mult_x_23_n801), .S(
mult_x_23_n802) );
INVX2TS U4953 ( .A(n2849), .Y(n3783) );
AOI21X1TS U4954 ( .A0(n4690), .A1(n3785), .B0(n3783), .Y(n2850) );
AOI21X1TS U4955 ( .A0(n2853), .A1(n3791), .B0(n2852), .Y(n2854) );
NAND2X1TS U4956 ( .A(n4520), .B(n4383), .Y(n2855) );
XOR2X1TS U4957 ( .A(n2856), .B(n801), .Y(mult_x_24_n1515) );
OAI21X1TS U4958 ( .A0(n3314), .A1(n3407), .B0(n849), .Y(n2857) );
XOR2X1TS U4959 ( .A(n2857), .B(n3408), .Y(n3334) );
XOR2X1TS U4960 ( .A(n2859), .B(n3408), .Y(n3337) );
AOI222X1TS U4961 ( .A0(n3426), .A1(n3594), .B0(n3405), .B1(n3592), .C0(n3424), .C1(n3351), .Y(n2860) );
OAI21X1TS U4962 ( .A0(n3353), .A1(n3428), .B0(n2860), .Y(n2861) );
XOR2X1TS U4963 ( .A(n2861), .B(n3408), .Y(n2862) );
ADDHXLTS U4964 ( .A(n2863), .B(n2862), .CO(mult_x_23_n752), .S(n2872) );
AOI222X1TS U4965 ( .A0(n3508), .A1(n3742), .B0(n3507), .B1(n3655), .C0(n3501), .C1(n3650), .Y(n2864) );
XOR2X1TS U4966 ( .A(n2865), .B(n3511), .Y(n2871) );
BUFX4TS U4967 ( .A(n2866), .Y(n3475) );
AOI222X1TS U4968 ( .A0(n3473), .A1(n3660), .B0(n3472), .B1(n3588), .C0(n3471), .C1(n3582), .Y(n2868) );
XOR2X1TS U4969 ( .A(n2869), .B(n6587), .Y(n2870) );
CMPR32X2TS U4970 ( .A(n2872), .B(n2871), .C(n2870), .CO(mult_x_23_n750), .S(
mult_x_23_n751) );
AOI222X1TS U4971 ( .A0(n4494), .A1(n4546), .B0(n4492), .B1(n4486), .C0(n2873), .C1(n4372), .Y(n2874) );
XOR2X1TS U4972 ( .A(n2875), .B(n783), .Y(mult_x_24_n1508) );
BUFX4TS U4973 ( .A(n2939), .Y(n4408) );
AOI222X1TS U4974 ( .A0(n4418), .A1(n4562), .B0(n4415), .B1(n4567), .C0(n4408), .C1(n4578), .Y(n2879) );
XOR2X1TS U4975 ( .A(n2880), .B(n4413), .Y(mult_x_24_n1459) );
INVX2TS U4976 ( .A(n2881), .Y(n2882) );
INVX2TS U4977 ( .A(n2884), .Y(n2887) );
AOI21X1TS U4978 ( .A0(n2887), .A1(n2886), .B0(n2885), .Y(n2888) );
XNOR2X4TS U4979 ( .A(n2895), .B(n2894), .Y(n4585) );
AOI222X1TS U4980 ( .A0(n4418), .A1(n4577), .B0(n4415), .B1(n4582), .C0(n4408), .C1(n4593), .Y(n2896) );
XOR2X1TS U4981 ( .A(n2897), .B(n4413), .Y(mult_x_24_n1462) );
NAND2X1TS U4982 ( .A(n4613), .B(n4383), .Y(n2898) );
XOR2X1TS U4983 ( .A(n2899), .B(n4635), .Y(mult_x_24_n1545) );
NAND2X1TS U4984 ( .A(n4462), .B(n4383), .Y(n2900) );
XOR2X1TS U4985 ( .A(n2901), .B(n6596), .Y(mult_x_24_n1485) );
AOI222X1TS U4986 ( .A0(n4548), .A1(n4614), .B0(n772), .B1(n4524), .C0(n2348),
.C1(n4626), .Y(n2902) );
XOR2X1TS U4987 ( .A(n2903), .B(n4522), .Y(mult_x_24_n1529) );
XOR2X1TS U4988 ( .A(n2904), .B(n4075), .Y(n4102) );
NAND2X1TS U4989 ( .A(n4162), .B(n4159), .Y(n2905) );
XOR2X1TS U4990 ( .A(n2906), .B(n4093), .Y(n4105) );
AOI222X1TS U4991 ( .A0(n4090), .A1(n4491), .B0(n4089), .B1(Op_MX[1]), .C0(
n4160), .C1(n4139), .Y(n2907) );
XOR2X1TS U4992 ( .A(n2908), .B(n4093), .Y(n2909) );
ADDHXLTS U4993 ( .A(n2910), .B(n2909), .CO(mult_x_24_n768), .S(n2923) );
CLKXOR2X2TS U4994 ( .A(Op_MY[13]), .B(n799), .Y(n2913) );
BUFX4TS U4995 ( .A(n2927), .Y(n4381) );
BUFX3TS U4996 ( .A(n2925), .Y(n4379) );
XNOR2X1TS U4997 ( .A(Op_MY[12]), .B(Op_MY[13]), .Y(n2911) );
BUFX3TS U4998 ( .A(n2924), .Y(n4378) );
AOI222X1TS U4999 ( .A0(n4379), .A1(n4614), .B0(n4378), .B1(Op_MX[13]), .C0(
n2930), .C1(n4626), .Y(n2914) );
XOR2X1TS U5000 ( .A(n2915), .B(n4352), .Y(n2922) );
BUFX3TS U5001 ( .A(n2916), .Y(n4212) );
BUFX3TS U5002 ( .A(n2917), .Y(n4211) );
AOI222X1TS U5003 ( .A0(n4212), .A1(n4546), .B0(n4211), .B1(n4486), .C0(n2918), .C1(n4372), .Y(n2919) );
XOR2X1TS U5004 ( .A(n2920), .B(n6591), .Y(n2921) );
CMPR32X2TS U5005 ( .A(n2923), .B(n2922), .C(n2921), .CO(mult_x_24_n766), .S(
mult_x_24_n767) );
BUFX4TS U5006 ( .A(n2924), .Y(n4354) );
BUFX4TS U5007 ( .A(n2925), .Y(n4357) );
XOR2X1TS U5008 ( .A(n2926), .B(n4352), .Y(n4144) );
NAND2X1TS U5009 ( .A(n4357), .B(n4159), .Y(n2928) );
XOR2X1TS U5010 ( .A(n2929), .B(n4352), .Y(n4147) );
BUFX4TS U5011 ( .A(n2930), .Y(n4350) );
AOI222X1TS U5012 ( .A0(n4379), .A1(n4491), .B0(n4378), .B1(n4490), .C0(n4350), .C1(n4139), .Y(n2931) );
XOR2X1TS U5013 ( .A(n2932), .B(n799), .Y(n2933) );
ADDHXLTS U5014 ( .A(n2934), .B(n2933), .CO(mult_x_24_n888), .S(n2944) );
AOI222X1TS U5015 ( .A0(n4648), .A1(n4607), .B0(n4646), .B1(n4524), .C0(n2360), .C1(n4626), .Y(n2935) );
XOR2X1TS U5016 ( .A(n2936), .B(n4635), .Y(n2943) );
BUFX3TS U5017 ( .A(n2937), .Y(n4433) );
BUFX3TS U5018 ( .A(n2938), .Y(n4432) );
AOI222X1TS U5019 ( .A0(n4433), .A1(n4546), .B0(n4432), .B1(n4486), .C0(n2939), .C1(n4372), .Y(n2940) );
XOR2X1TS U5020 ( .A(n2941), .B(n777), .Y(n2942) );
CMPR32X2TS U5021 ( .A(n2944), .B(n2943), .C(n2942), .CO(mult_x_24_n886), .S(
mult_x_24_n887) );
BUFX4TS U5022 ( .A(n2945), .Y(n4269) );
XOR2X1TS U5023 ( .A(n2947), .B(n4242), .Y(n4123) );
NAND2X1TS U5024 ( .A(n4247), .B(n4159), .Y(n2948) );
XOR2X1TS U5025 ( .A(n2950), .B(n4242), .Y(n4126) );
BUFX3TS U5026 ( .A(n2951), .Y(n4267) );
BUFX3TS U5027 ( .A(n2952), .Y(n4266) );
AOI222X1TS U5028 ( .A0(n4267), .A1(n4491), .B0(n4266), .B1(n4490), .C0(n4237), .C1(n4139), .Y(n2953) );
XOR2X1TS U5029 ( .A(n2954), .B(n770), .Y(n2955) );
ADDHXLTS U5030 ( .A(n2956), .B(n2955), .CO(mult_x_24_n837), .S(n2968) );
AOI222X1TS U5031 ( .A0(n4494), .A1(n4614), .B0(n4492), .B1(n4524), .C0(n2873), .C1(n4626), .Y(n2957) );
XOR2X1TS U5032 ( .A(n2958), .B(n4464), .Y(n2967) );
BUFX3TS U5033 ( .A(n2959), .Y(n4321) );
BUFX3TS U5034 ( .A(n2960), .Y(n4320) );
AOI222X1TS U5035 ( .A0(n4321), .A1(n4546), .B0(n4320), .B1(n4486), .C0(n4119), .C1(n4372), .Y(n2964) );
XOR2X1TS U5036 ( .A(n2965), .B(n780), .Y(n2966) );
CMPR32X2TS U5037 ( .A(n2968), .B(n2967), .C(n2966), .CO(mult_x_24_n835), .S(
mult_x_24_n836) );
INVX2TS U5038 ( .A(n2969), .Y(n3174) );
INVX2TS U5039 ( .A(n2970), .Y(n3173) );
NAND2X1TS U5040 ( .A(n3173), .B(n3171), .Y(n2971) );
XNOR2X1TS U5041 ( .A(n3174), .B(n2971), .Y(Sgf_operation_ODD1_left_N17) );
AOI21X1TS U5042 ( .A0(n2979), .A1(n2978), .B0(n2977), .Y(n2980) );
NOR2X1TS U5043 ( .A(mult_x_23_n586), .B(mult_x_23_n595), .Y(n3097) );
NOR2X2TS U5044 ( .A(mult_x_23_n576), .B(mult_x_23_n585), .Y(n3099) );
NOR2X1TS U5045 ( .A(n3097), .B(n3099), .Y(n3086) );
NOR2X2TS U5046 ( .A(mult_x_23_n568), .B(mult_x_23_n575), .Y(n3092) );
NOR2X2TS U5047 ( .A(mult_x_23_n561), .B(mult_x_23_n567), .Y(n3087) );
NOR2X2TS U5048 ( .A(mult_x_23_n553), .B(mult_x_23_n560), .Y(n3080) );
NAND2X1TS U5049 ( .A(mult_x_23_n576), .B(mult_x_23_n585), .Y(n3100) );
NAND2X1TS U5050 ( .A(mult_x_23_n561), .B(mult_x_23_n567), .Y(n3088) );
AOI21X1TS U5051 ( .A0(n3085), .A1(n2987), .B0(n2986), .Y(n3077) );
NAND2X1TS U5052 ( .A(mult_x_23_n553), .B(mult_x_23_n560), .Y(n3081) );
OAI21X1TS U5053 ( .A0(n3077), .A1(n3080), .B0(n3081), .Y(n3070) );
NAND2X1TS U5054 ( .A(mult_x_23_n548), .B(mult_x_23_n552), .Y(n3072) );
INVX2TS U5055 ( .A(n3072), .Y(n2988) );
AOI21X1TS U5056 ( .A0(n3070), .A1(n3073), .B0(n2988), .Y(n2989) );
NAND2X1TS U5057 ( .A(mult_x_23_n547), .B(mult_x_23_n541), .Y(n3065) );
INVX2TS U5058 ( .A(n3065), .Y(n2991) );
NOR2X1TS U5059 ( .A(mult_x_23_n540), .B(mult_x_23_n534), .Y(n3060) );
NAND2X1TS U5060 ( .A(mult_x_23_n540), .B(mult_x_23_n534), .Y(n3061) );
NAND2X1TS U5061 ( .A(mult_x_23_n529), .B(mult_x_23_n533), .Y(n3056) );
INVX2TS U5062 ( .A(n3056), .Y(n2992) );
NOR2X1TS U5063 ( .A(mult_x_23_n525), .B(mult_x_23_n528), .Y(n3051) );
NAND2X1TS U5064 ( .A(mult_x_23_n525), .B(mult_x_23_n528), .Y(n3052) );
OAI21X4TS U5065 ( .A0(n3055), .A1(n3051), .B0(n3052), .Y(n3050) );
NAND2X1TS U5066 ( .A(mult_x_23_n524), .B(mult_x_23_n520), .Y(n3047) );
INVX2TS U5067 ( .A(n3047), .Y(n2993) );
NOR2X1TS U5068 ( .A(mult_x_23_n517), .B(mult_x_23_n519), .Y(n3042) );
NAND2X1TS U5069 ( .A(mult_x_23_n517), .B(mult_x_23_n519), .Y(n3043) );
AOI21X1TS U5070 ( .A0(n3386), .A1(n3670), .B0(n3399), .Y(n2994) );
XOR2X1TS U5071 ( .A(n2995), .B(n6586), .Y(n3010) );
INVX2TS U5072 ( .A(n3010), .Y(n3001) );
AOI21X1TS U5073 ( .A0(n3299), .A1(n3677), .B0(n2996), .Y(n2997) );
OAI21X1TS U5074 ( .A0(n3680), .A1(n3317), .B0(n2997), .Y(n3000) );
NAND2X1TS U5075 ( .A(mult_x_23_n516), .B(n2998), .Y(n3038) );
INVX2TS U5076 ( .A(n3038), .Y(n2999) );
CMPR32X2TS U5077 ( .A(n3001), .B(mult_x_23_n515), .C(n3000), .CO(n3006), .S(
n2998) );
AOI21X1TS U5078 ( .A0(n3299), .A1(n3609), .B0(n3002), .Y(n3003) );
OAI21X1TS U5079 ( .A0(n3611), .A1(n3317), .B0(n3003), .Y(n3016) );
INVX2TS U5080 ( .A(n3016), .Y(n3011) );
XOR2X1TS U5081 ( .A(n3004), .B(n6586), .Y(n3009) );
NOR2X1TS U5082 ( .A(n3006), .B(n3005), .Y(n3033) );
NAND2X1TS U5083 ( .A(n3006), .B(n3005), .Y(n3034) );
AOI21X1TS U5084 ( .A0(n3299), .A1(n3674), .B0(n3007), .Y(n3008) );
OAI21X1TS U5085 ( .A0(n847), .A1(n3317), .B0(n3008), .Y(n3015) );
CMPR32X2TS U5086 ( .A(n3011), .B(n3010), .C(n3009), .CO(n3012), .S(n3005) );
NAND2X1TS U5087 ( .A(n3013), .B(n3012), .Y(n3029) );
INVX2TS U5088 ( .A(n3029), .Y(n3014) );
CMPR32X2TS U5089 ( .A(n6566), .B(n3016), .C(n3015), .CO(n3019), .S(n3013) );
AOI21X1TS U5090 ( .A0(n3299), .A1(n3670), .B0(n3313), .Y(n3017) );
OAI21X1TS U5091 ( .A0(n2714), .A1(n3317), .B0(n3017), .Y(n3021) );
INVX2TS U5092 ( .A(n3021), .Y(n3018) );
NOR2X1TS U5093 ( .A(n3019), .B(n3018), .Y(n3024) );
NAND2X1TS U5094 ( .A(n3019), .B(n3018), .Y(n3025) );
NAND2X1TS U5095 ( .A(n3299), .B(n3021), .Y(n3022) );
INVX2TS U5096 ( .A(n3024), .Y(n3026) );
NAND2X1TS U5097 ( .A(n3026), .B(n3025), .Y(n3027) );
NAND2X1TS U5098 ( .A(n3030), .B(n3029), .Y(n3031) );
XNOR2X1TS U5099 ( .A(n3032), .B(n3031), .Y(Sgf_operation_ODD1_left_N49) );
INVX2TS U5100 ( .A(n3033), .Y(n3035) );
NAND2X1TS U5101 ( .A(n3035), .B(n3034), .Y(n3036) );
NAND2X1TS U5102 ( .A(n3039), .B(n3038), .Y(n3040) );
XNOR2X1TS U5103 ( .A(n3041), .B(n3040), .Y(Sgf_operation_ODD1_left_N47) );
NAND2X1TS U5104 ( .A(n3044), .B(n3043), .Y(n3045) );
NAND2X1TS U5105 ( .A(n3048), .B(n3047), .Y(n3049) );
XNOR2X1TS U5106 ( .A(n3050), .B(n3049), .Y(Sgf_operation_ODD1_left_N45) );
NAND2X1TS U5107 ( .A(n3053), .B(n3052), .Y(n3054) );
NAND2X1TS U5108 ( .A(n3057), .B(n3056), .Y(n3058) );
XNOR2X1TS U5109 ( .A(n3059), .B(n3058), .Y(Sgf_operation_ODD1_left_N43) );
NAND2X1TS U5110 ( .A(n3062), .B(n3061), .Y(n3063) );
NAND2X1TS U5111 ( .A(n3066), .B(n3065), .Y(n3067) );
XNOR2X1TS U5112 ( .A(n3068), .B(n3067), .Y(Sgf_operation_ODD1_left_N41) );
AOI21X1TS U5113 ( .A0(n3107), .A1(n3071), .B0(n3070), .Y(n3075) );
NAND2X1TS U5114 ( .A(n3073), .B(n3072), .Y(n3074) );
INVX2TS U5115 ( .A(n3076), .Y(n3079) );
INVX2TS U5116 ( .A(n3077), .Y(n3078) );
AOI21X1TS U5117 ( .A0(n3107), .A1(n3079), .B0(n3078), .Y(n3084) );
INVX2TS U5118 ( .A(n3080), .Y(n3082) );
NAND2X1TS U5119 ( .A(n3082), .B(n3081), .Y(n3083) );
AOI21X1TS U5120 ( .A0(n3107), .A1(n3086), .B0(n3085), .Y(n3096) );
INVX2TS U5121 ( .A(n3087), .Y(n3089) );
NAND2X1TS U5122 ( .A(n3089), .B(n3088), .Y(n3090) );
XNOR2X1TS U5123 ( .A(n3091), .B(n3090), .Y(Sgf_operation_ODD1_left_N38) );
INVX2TS U5124 ( .A(n3092), .Y(n3094) );
NAND2X1TS U5125 ( .A(n3094), .B(n3093), .Y(n3095) );
INVX2TS U5126 ( .A(n3097), .Y(n3105) );
INVX2TS U5127 ( .A(n3104), .Y(n3098) );
AOI21X1TS U5128 ( .A0(n3107), .A1(n3105), .B0(n3098), .Y(n3103) );
INVX2TS U5129 ( .A(n3099), .Y(n3101) );
NAND2X1TS U5130 ( .A(n3101), .B(n3100), .Y(n3102) );
NAND2X1TS U5131 ( .A(n3105), .B(n3104), .Y(n3106) );
XNOR2X1TS U5132 ( .A(n3107), .B(n3106), .Y(Sgf_operation_ODD1_left_N35) );
NAND2X1TS U5133 ( .A(n3109), .B(n3108), .Y(n3110) );
XNOR2X1TS U5134 ( .A(n3111), .B(n3110), .Y(Sgf_operation_ODD1_left_N33) );
NAND2X1TS U5135 ( .A(n3113), .B(n3112), .Y(n3114) );
XNOR2X1TS U5136 ( .A(n3115), .B(n3114), .Y(Sgf_operation_ODD1_left_N29) );
NAND2X1TS U5137 ( .A(n3118), .B(n3117), .Y(n3119) );
XNOR2X1TS U5138 ( .A(n3120), .B(n3119), .Y(Sgf_operation_ODD1_left_N28) );
INVX2TS U5139 ( .A(n3121), .Y(n3123) );
NAND2X1TS U5140 ( .A(n3123), .B(n3122), .Y(n3124) );
INVX2TS U5141 ( .A(n3126), .Y(n3149) );
AOI21X1TS U5142 ( .A0(n3149), .A1(n3128), .B0(n3127), .Y(n3138) );
NAND2X1TS U5143 ( .A(n3131), .B(n3130), .Y(n3132) );
XNOR2X1TS U5144 ( .A(n3133), .B(n3132), .Y(Sgf_operation_ODD1_left_N26) );
INVX2TS U5145 ( .A(n3134), .Y(n3136) );
NAND2X1TS U5146 ( .A(n3136), .B(n3135), .Y(n3137) );
INVX2TS U5147 ( .A(n3139), .Y(n3147) );
INVX2TS U5148 ( .A(n3146), .Y(n3140) );
AOI21X1TS U5149 ( .A0(n3149), .A1(n3147), .B0(n3140), .Y(n3145) );
INVX2TS U5150 ( .A(n3141), .Y(n3143) );
NAND2X1TS U5151 ( .A(n3143), .B(n3142), .Y(n3144) );
NAND2X1TS U5152 ( .A(n3147), .B(n3146), .Y(n3148) );
XNOR2X1TS U5153 ( .A(n3149), .B(n3148), .Y(Sgf_operation_ODD1_left_N23) );
INVX2TS U5154 ( .A(n3150), .Y(n3165) );
NAND2X1TS U5155 ( .A(n3155), .B(n3154), .Y(n3156) );
XNOR2X1TS U5156 ( .A(n3157), .B(n3156), .Y(Sgf_operation_ODD1_left_N22) );
NAND2X1TS U5157 ( .A(n903), .B(n3159), .Y(n3160) );
XNOR2X1TS U5158 ( .A(n3161), .B(n3160), .Y(Sgf_operation_ODD1_left_N21) );
NAND2X1TS U5159 ( .A(n3163), .B(n3162), .Y(n3164) );
AOI21X1TS U5160 ( .A0(n3174), .A1(n3167), .B0(n3166), .Y(n3170) );
NAND2X1TS U5161 ( .A(n904), .B(n3168), .Y(n3169) );
INVX2TS U5162 ( .A(n3171), .Y(n3172) );
AOI21X1TS U5163 ( .A0(n3174), .A1(n3173), .B0(n3172), .Y(n3179) );
INVX2TS U5164 ( .A(n3175), .Y(n3177) );
NAND2X1TS U5165 ( .A(n3177), .B(n3176), .Y(n3178) );
INVX2TS U5166 ( .A(n3183), .Y(n3185) );
NAND2X1TS U5167 ( .A(n3185), .B(n3184), .Y(n3186) );
XNOR2X1TS U5168 ( .A(n3187), .B(n3186), .Y(Sgf_operation_ODD1_left_N16) );
INVX2TS U5169 ( .A(n3188), .Y(n3195) );
AOI21X1TS U5170 ( .A0(n3195), .A1(n901), .B0(n3189), .Y(n3192) );
NAND2X1TS U5171 ( .A(n902), .B(n3190), .Y(n3191) );
NAND2X1TS U5172 ( .A(n901), .B(n3193), .Y(n3194) );
XNOR2X1TS U5173 ( .A(n3195), .B(n3194), .Y(Sgf_operation_ODD1_left_N13) );
INVX2TS U5174 ( .A(n3199), .Y(n3201) );
NAND2X1TS U5175 ( .A(n3201), .B(n3200), .Y(n3202) );
XNOR2X1TS U5176 ( .A(n3203), .B(n3202), .Y(Sgf_operation_ODD1_left_N12) );
INVX2TS U5177 ( .A(n3204), .Y(n3212) );
AOI21X1TS U5178 ( .A0(n3212), .A1(n907), .B0(n3205), .Y(n3209) );
NAND2X1TS U5179 ( .A(n3207), .B(n3206), .Y(n3208) );
NAND2X1TS U5180 ( .A(n907), .B(n3210), .Y(n3211) );
XNOR2X1TS U5181 ( .A(n3212), .B(n3211), .Y(Sgf_operation_ODD1_left_N9) );
NAND2X1TS U5182 ( .A(n906), .B(n3213), .Y(n3214) );
XNOR2X1TS U5183 ( .A(n3215), .B(n3214), .Y(Sgf_operation_ODD1_left_N8) );
INVX2TS U5184 ( .A(n3216), .Y(n3218) );
NAND2X1TS U5185 ( .A(n3218), .B(n3217), .Y(n3219) );
INVX2TS U5186 ( .A(n3221), .Y(n3230) );
INVX2TS U5187 ( .A(n3222), .Y(n3224) );
NAND2X1TS U5188 ( .A(n3224), .B(n3223), .Y(n3225) );
XNOR2X1TS U5189 ( .A(n3226), .B(n3225), .Y(Sgf_operation_ODD1_left_N6) );
INVX2TS U5190 ( .A(n3227), .Y(n3229) );
NAND2X1TS U5191 ( .A(n3229), .B(n3228), .Y(n3231) );
INVX2TS U5192 ( .A(n3232), .Y(n3234) );
NAND2X1TS U5193 ( .A(n3234), .B(n3233), .Y(n3235) );
NAND2X1TS U5194 ( .A(n3238), .B(n3237), .Y(n3240) );
XNOR2X1TS U5195 ( .A(n3240), .B(n3239), .Y(Sgf_operation_ODD1_left_N3) );
XOR2XLTS U5196 ( .A(n754), .B(n3241), .Y(Sgf_operation_ODD1_left_N2) );
INVX2TS U5197 ( .A(n3242), .Y(n3243) );
XNOR2X1TS U5198 ( .A(n3243), .B(n833), .Y(Sgf_operation_ODD1_left_N1) );
AOI222X1TS U5199 ( .A0(n3393), .A1(n3683), .B0(n3387), .B1(n3688), .C0(n3386), .C1(n3682), .Y(n3244) );
XOR2X1TS U5200 ( .A(n3245), .B(n3389), .Y(n3246) );
CMPR32X2TS U5201 ( .A(n6560), .B(n3247), .C(n3246), .CO(mult_x_23_n530), .S(
mult_x_23_n531) );
AOI21X1TS U5202 ( .A0(n3299), .A1(n3703), .B0(n3249), .Y(n3250) );
OAI21X1TS U5203 ( .A0(n3706), .A1(n3317), .B0(n3250), .Y(n3255) );
AOI21X1TS U5204 ( .A0(n3448), .A1(n3670), .B0(n3472), .Y(n3251) );
XOR2X1TS U5205 ( .A(n3252), .B(n6587), .Y(n3253) );
CMPR32X2TS U5206 ( .A(n3255), .B(n3254), .C(n3253), .CO(mult_x_23_n542), .S(
mult_x_23_n543) );
XOR2X1TS U5207 ( .A(n3257), .B(n3389), .Y(n3258) );
CMPR32X2TS U5208 ( .A(n6556), .B(n3259), .C(n3258), .CO(mult_x_23_n572), .S(
mult_x_23_n573) );
AOI222X1TS U5209 ( .A0(n3393), .A1(n3721), .B0(n3387), .B1(n3726), .C0(n3398), .C1(n3719), .Y(n3260) );
XOR2X1TS U5210 ( .A(n3261), .B(n3389), .Y(n3266) );
AOI21X1TS U5211 ( .A0(n3289), .A1(n3737), .B0(n3262), .Y(n3263) );
INVX2TS U5212 ( .A(mult_x_23_n592), .Y(n3264) );
CMPR32X2TS U5213 ( .A(n3266), .B(n3265), .C(n3264), .CO(mult_x_23_n590), .S(
mult_x_23_n591) );
AOI21X1TS U5214 ( .A0(n3289), .A1(n3654), .B0(n3267), .Y(n3268) );
OAI21X1TS U5215 ( .A0(n873), .A1(n1609), .B0(n3268), .Y(n3269) );
CMPR32X2TS U5216 ( .A(n6553), .B(n6552), .C(n3269), .CO(mult_x_23_n632), .S(
mult_x_23_n633) );
AOI21X1TS U5217 ( .A0(n3289), .A1(n3658), .B0(n3270), .Y(n3271) );
OAI21X1TS U5218 ( .A0(n3666), .A1(n1609), .B0(n3271), .Y(n3275) );
AOI222X1TS U5219 ( .A0(n3400), .A1(n3752), .B0(n3399), .B1(n3750), .C0(n3398), .C1(n3748), .Y(n3272) );
OAI21X1TS U5220 ( .A0(n3755), .A1(n3402), .B0(n3272), .Y(n3273) );
XOR2X1TS U5221 ( .A(n3273), .B(n6586), .Y(n3274) );
CMPR32X2TS U5222 ( .A(n3756), .B(n3275), .C(n3274), .CO(mult_x_23_n643), .S(
mult_x_23_n644) );
AOI21X1TS U5223 ( .A0(n3289), .A1(n3582), .B0(n3276), .Y(n3277) );
OAI21X1TS U5224 ( .A0(n3585), .A1(n1609), .B0(n3277), .Y(n3281) );
AOI222X1TS U5225 ( .A0(n3400), .A1(n3750), .B0(n3399), .B1(n3655), .C0(n3398), .C1(n3650), .Y(n3278) );
XOR2X1TS U5226 ( .A(n3279), .B(n6586), .Y(n3280) );
CMPR32X2TS U5227 ( .A(n3756), .B(n3281), .C(n3280), .CO(mult_x_23_n654), .S(
mult_x_23_n655) );
AOI21X1TS U5228 ( .A0(n3289), .A1(n3587), .B0(n3282), .Y(n3283) );
AOI222X1TS U5229 ( .A0(n3426), .A1(n3743), .B0(n3425), .B1(n3752), .C0(n3419), .C1(n3742), .Y(n3284) );
OAI21X1TS U5230 ( .A0(n3745), .A1(n3428), .B0(n3284), .Y(n3285) );
XOR2X1TS U5231 ( .A(n3285), .B(n3429), .Y(n3286) );
CMPR32X2TS U5232 ( .A(n3756), .B(n3287), .C(n3286), .CO(mult_x_23_n665), .S(
mult_x_23_n666) );
AOI21X1TS U5233 ( .A0(n3289), .A1(n3360), .B0(n3288), .Y(n3290) );
AOI222X1TS U5234 ( .A0(n3400), .A1(n3662), .B0(n3399), .B1(n3660), .C0(n3398), .C1(n3658), .Y(n3291) );
XOR2X1TS U5235 ( .A(n3292), .B(n6586), .Y(n3296) );
AOI222X1TS U5236 ( .A0(n3426), .A1(n3752), .B0(n3425), .B1(n3750), .C0(n3419), .C1(n3748), .Y(n3293) );
XOR2X1TS U5237 ( .A(n3294), .B(n3429), .Y(n3295) );
CMPR32X2TS U5238 ( .A(n3297), .B(n3296), .C(n3295), .CO(mult_x_23_n676), .S(
mult_x_23_n677) );
AOI21X1TS U5239 ( .A0(n3299), .A1(n3312), .B0(n3298), .Y(n3300) );
AOI222X1TS U5240 ( .A0(n3426), .A1(n3750), .B0(n3425), .B1(n3655), .C0(n3419), .C1(n3650), .Y(n3301) );
XOR2X1TS U5241 ( .A(n3302), .B(n3429), .Y(n3306) );
AOI222X1TS U5242 ( .A0(n3400), .A1(n3660), .B0(n3399), .B1(n3588), .C0(n3398), .C1(n3582), .Y(n3303) );
XOR2X1TS U5243 ( .A(n3304), .B(n6586), .Y(n3305) );
CMPR32X2TS U5244 ( .A(n3307), .B(n3306), .C(n3305), .CO(mult_x_23_n687), .S(
mult_x_23_n688) );
AOI222X1TS U5245 ( .A0(n3400), .A1(n3594), .B0(n3387), .B1(n3592), .C0(n3386), .C1(n3351), .Y(n3310) );
XOR2X1TS U5246 ( .A(n3311), .B(n3389), .Y(n3321) );
AOI222X1TS U5247 ( .A0(n3400), .A1(n3588), .B0(n3399), .B1(n3596), .C0(n3386), .C1(n3587), .Y(n3315) );
XOR2X1TS U5248 ( .A(n3316), .B(n6586), .Y(n3324) );
AOI222X1TS U5249 ( .A0(n3400), .A1(n3596), .B0(n3399), .B1(n3594), .C0(n3386), .C1(n3592), .Y(n3319) );
XOR2X1TS U5250 ( .A(n3320), .B(n786), .Y(n3327) );
ADDHXLTS U5251 ( .A(n3322), .B(n3321), .CO(n3326), .S(mult_x_23_n721) );
CMPR32X2TS U5252 ( .A(n3325), .B(n3324), .C(n3323), .CO(mult_x_23_n698), .S(
mult_x_23_n699) );
CMPR32X2TS U5253 ( .A(n3328), .B(n3327), .C(n3326), .CO(n3323), .S(
mult_x_23_n710) );
AOI222X1TS U5254 ( .A0(n3473), .A1(n3594), .B0(n3451), .B1(n3592), .C0(n3448), .C1(n3351), .Y(n3331) );
XOR2X1TS U5255 ( .A(n3332), .B(n3454), .Y(n3340) );
ADDHXLTS U5256 ( .A(n3334), .B(n3333), .CO(n2863), .S(n3344) );
AOI222X1TS U5257 ( .A0(n3473), .A1(n3588), .B0(n3472), .B1(n3596), .C0(n3448), .C1(n3587), .Y(n3335) );
XOR2X1TS U5258 ( .A(n3336), .B(n6587), .Y(n3343) );
AOI222X1TS U5259 ( .A0(n3473), .A1(n3596), .B0(n3472), .B1(n3594), .C0(n3448), .C1(n3592), .Y(n3338) );
XOR2X1TS U5260 ( .A(n3339), .B(n807), .Y(n3346) );
ADDHXLTS U5261 ( .A(n3341), .B(n3340), .CO(n3345), .S(mult_x_23_n781) );
CMPR32X2TS U5262 ( .A(n3344), .B(n3343), .C(n3342), .CO(mult_x_23_n760), .S(
mult_x_23_n761) );
CMPR32X2TS U5263 ( .A(n3347), .B(n3346), .C(n3345), .CO(n3342), .S(
mult_x_23_n771) );
BUFX3TS U5264 ( .A(n3350), .Y(n3539) );
AOI222X1TS U5265 ( .A0(n3560), .A1(n3594), .B0(n3539), .B1(n3592), .C0(n3536), .C1(n3351), .Y(n3352) );
XOR2X1TS U5266 ( .A(n3354), .B(n3541), .Y(n3363) );
ADDHXLTS U5267 ( .A(n3356), .B(n3355), .CO(n2838), .S(n3367) );
AOI222X1TS U5268 ( .A0(n3560), .A1(n3588), .B0(n3559), .B1(n3596), .C0(n3536), .C1(n3587), .Y(n3357) );
XOR2X1TS U5269 ( .A(n3358), .B(n6588), .Y(n3366) );
AOI222X1TS U5270 ( .A0(n3560), .A1(n3596), .B0(n3559), .B1(n3594), .C0(n3536), .C1(n3360), .Y(n3361) );
XOR2X1TS U5271 ( .A(n3362), .B(n6588), .Y(n3369) );
ADDHXLTS U5272 ( .A(n3364), .B(n3363), .CO(n3368), .S(mult_x_23_n823) );
CMPR32X2TS U5273 ( .A(n3367), .B(n3366), .C(n3365), .CO(mult_x_23_n808), .S(
mult_x_23_n809) );
CMPR32X2TS U5274 ( .A(n3370), .B(n3369), .C(n3368), .CO(n3365), .S(
mult_x_23_n816) );
AOI21X1TS U5275 ( .A0(n3386), .A1(n3674), .B0(n3371), .Y(n3372) );
XOR2X1TS U5276 ( .A(n3373), .B(n3389), .Y(mult_x_23_n1140) );
AOI222X1TS U5277 ( .A0(n3393), .A1(n767), .B0(n3399), .B1(n3678), .C0(n3386),
.C1(n3609), .Y(n3374) );
XOR2X1TS U5278 ( .A(n3375), .B(n3389), .Y(mult_x_23_n1141) );
AOI222X1TS U5279 ( .A0(n3393), .A1(n3678), .B0(n3387), .B1(n3683), .C0(n3386), .C1(n3677), .Y(n3376) );
XOR2X1TS U5280 ( .A(n3377), .B(n3389), .Y(mult_x_23_n1142) );
AOI222X1TS U5281 ( .A0(n3393), .A1(n3688), .B0(n3387), .B1(n3694), .C0(n3386), .C1(n3687), .Y(n3378) );
XOR2X1TS U5282 ( .A(n3379), .B(n3389), .Y(mult_x_23_n1144) );
AOI222X1TS U5283 ( .A0(n3393), .A1(n3694), .B0(n3387), .B1(n3693), .C0(n3386), .C1(n3692), .Y(n3380) );
XOR2X1TS U5284 ( .A(n3381), .B(n3389), .Y(mult_x_23_n1145) );
AOI222X1TS U5285 ( .A0(n3393), .A1(n3699), .B0(n3387), .B1(n3704), .C0(n3386), .C1(n3698), .Y(n3382) );
XOR2X1TS U5286 ( .A(n3383), .B(n3389), .Y(mult_x_23_n1147) );
AOI222X1TS U5287 ( .A0(n3393), .A1(n3704), .B0(n3387), .B1(n3709), .C0(n3386), .C1(n3703), .Y(n3384) );
XOR2X1TS U5288 ( .A(n3385), .B(n3389), .Y(mult_x_23_n1148) );
AOI222X1TS U5289 ( .A0(n3393), .A1(n3715), .B0(n3387), .B1(n3721), .C0(n3386), .C1(n3713), .Y(n3388) );
XOR2X1TS U5290 ( .A(n3390), .B(n3389), .Y(mult_x_23_n1150) );
AOI222X1TS U5291 ( .A0(n3400), .A1(n3726), .B0(n3399), .B1(n3732), .C0(n3398), .C1(n3725), .Y(n3391) );
XOR2X1TS U5292 ( .A(n3392), .B(n6586), .Y(mult_x_23_n1152) );
AOI222X1TS U5293 ( .A0(n3393), .A1(n3732), .B0(n3399), .B1(n3738), .C0(n3398), .C1(n3731), .Y(n3394) );
XOR2X1TS U5294 ( .A(n3395), .B(n6586), .Y(mult_x_23_n1153) );
AOI222X1TS U5295 ( .A0(n3400), .A1(n3738), .B0(n3399), .B1(n3743), .C0(n3398), .C1(n3737), .Y(n3396) );
XOR2X1TS U5296 ( .A(n3397), .B(n6586), .Y(mult_x_23_n1154) );
AOI222X1TS U5297 ( .A0(n3400), .A1(n3743), .B0(n3399), .B1(n3752), .C0(n3398), .C1(n3742), .Y(n3401) );
XOR2X1TS U5298 ( .A(n3403), .B(n6586), .Y(mult_x_23_n1155) );
XOR2X1TS U5299 ( .A(n3404), .B(n3429), .Y(mult_x_23_n1167) );
AOI222X1TS U5300 ( .A0(n3412), .A1(n3721), .B0(n3405), .B1(n3726), .C0(n3419), .C1(n3719), .Y(n3406) );
XOR2X1TS U5301 ( .A(n3409), .B(n3408), .Y(mult_x_23_n1180) );
AOI222X1TS U5302 ( .A0(n3426), .A1(n3726), .B0(n3425), .B1(n3732), .C0(n3419), .C1(n3725), .Y(n3410) );
XOR2X1TS U5303 ( .A(n3411), .B(n3429), .Y(mult_x_23_n1181) );
AOI222X1TS U5304 ( .A0(n3412), .A1(n3732), .B0(n3425), .B1(n3738), .C0(n3419), .C1(n3731), .Y(n3413) );
XOR2X1TS U5305 ( .A(n3414), .B(n3429), .Y(mult_x_23_n1182) );
AOI222X1TS U5306 ( .A0(n3426), .A1(n3655), .B0(n3425), .B1(n3662), .C0(n3419), .C1(n3654), .Y(n3415) );
XOR2X1TS U5307 ( .A(n3416), .B(n3429), .Y(mult_x_23_n1187) );
AOI222X1TS U5308 ( .A0(n3426), .A1(n3662), .B0(n3425), .B1(n3660), .C0(n3419), .C1(n3658), .Y(n3417) );
XOR2X1TS U5309 ( .A(n3418), .B(n3429), .Y(mult_x_23_n1188) );
AOI222X1TS U5310 ( .A0(n3426), .A1(n3660), .B0(n3425), .B1(n3588), .C0(n3419), .C1(n3582), .Y(n3420) );
XOR2X1TS U5311 ( .A(n3421), .B(n3429), .Y(mult_x_23_n1189) );
AOI222X1TS U5312 ( .A0(n3426), .A1(n3588), .B0(n3425), .B1(n3596), .C0(n3424), .C1(n3587), .Y(n3422) );
XOR2X1TS U5313 ( .A(n3423), .B(n3429), .Y(mult_x_23_n1190) );
AOI222X1TS U5314 ( .A0(n3426), .A1(n3596), .B0(n3425), .B1(n3594), .C0(n3424), .C1(n3592), .Y(n3427) );
XOR2X1TS U5315 ( .A(n3430), .B(n3429), .Y(mult_x_23_n1191) );
AOI21X1TS U5316 ( .A0(n3448), .A1(n3674), .B0(n3431), .Y(n3432) );
XOR2X1TS U5317 ( .A(n3433), .B(n3454), .Y(mult_x_23_n1198) );
AOI222X1TS U5318 ( .A0(n3458), .A1(n767), .B0(n3472), .B1(n3678), .C0(n3448),
.C1(n3609), .Y(n3434) );
XOR2X1TS U5319 ( .A(n3435), .B(n3454), .Y(mult_x_23_n1199) );
AOI222X1TS U5320 ( .A0(n3458), .A1(n3683), .B0(n3451), .B1(n3688), .C0(n3448), .C1(n3682), .Y(n3436) );
XOR2X1TS U5321 ( .A(n3437), .B(n3454), .Y(mult_x_23_n1201) );
AOI222X1TS U5322 ( .A0(n3458), .A1(n3688), .B0(n3451), .B1(n3694), .C0(n3448), .C1(n3687), .Y(n3438) );
XOR2X1TS U5323 ( .A(n3439), .B(n3454), .Y(mult_x_23_n1202) );
AOI222X1TS U5324 ( .A0(n3458), .A1(n3693), .B0(n3451), .B1(n3699), .C0(n3448), .C1(n3621), .Y(n3440) );
XOR2X1TS U5325 ( .A(n3441), .B(n3454), .Y(mult_x_23_n1204) );
AOI222X1TS U5326 ( .A0(n3458), .A1(n3699), .B0(n3451), .B1(n3704), .C0(n3448), .C1(n3698), .Y(n3442) );
XOR2X1TS U5327 ( .A(n3443), .B(n3454), .Y(mult_x_23_n1205) );
AOI222X1TS U5328 ( .A0(n3458), .A1(n3704), .B0(n3451), .B1(n3709), .C0(n3448), .C1(n3703), .Y(n3444) );
XOR2X1TS U5329 ( .A(n3445), .B(n3454), .Y(mult_x_23_n1206) );
OAI21X1TS U5330 ( .A0(n3711), .A1(n3453), .B0(n3446), .Y(n3447) );
XOR2X1TS U5331 ( .A(n3447), .B(n3454), .Y(mult_x_23_n1207) );
AOI222X1TS U5332 ( .A0(n3458), .A1(n3715), .B0(n3451), .B1(n3721), .C0(n3448), .C1(n3713), .Y(n3449) );
XOR2X1TS U5333 ( .A(n3450), .B(n3454), .Y(mult_x_23_n1208) );
AOI222X1TS U5334 ( .A0(n3458), .A1(n3721), .B0(n3451), .B1(n3726), .C0(n3471), .C1(n3719), .Y(n3452) );
XOR2X1TS U5335 ( .A(n3455), .B(n3454), .Y(mult_x_23_n1209) );
AOI222X1TS U5336 ( .A0(n3473), .A1(n3726), .B0(n3472), .B1(n3732), .C0(n3471), .C1(n3725), .Y(n3456) );
XOR2X1TS U5337 ( .A(n3457), .B(n6587), .Y(mult_x_23_n1210) );
AOI222X1TS U5338 ( .A0(n3458), .A1(n3732), .B0(n3472), .B1(n3738), .C0(n3471), .C1(n3731), .Y(n3459) );
XOR2X1TS U5339 ( .A(n3460), .B(n6587), .Y(mult_x_23_n1211) );
AOI222X1TS U5340 ( .A0(n3473), .A1(n3738), .B0(n3472), .B1(n3743), .C0(n3471), .C1(n3737), .Y(n3461) );
XOR2X1TS U5341 ( .A(n3462), .B(n6587), .Y(mult_x_23_n1212) );
AOI222X1TS U5342 ( .A0(n3473), .A1(n3743), .B0(n3472), .B1(n3752), .C0(n3471), .C1(n3742), .Y(n3463) );
XOR2X1TS U5343 ( .A(n3464), .B(n6587), .Y(mult_x_23_n1213) );
AOI222X1TS U5344 ( .A0(n3473), .A1(n3752), .B0(n3472), .B1(n3750), .C0(n3471), .C1(n3748), .Y(n3465) );
XOR2X1TS U5345 ( .A(n3466), .B(n6587), .Y(mult_x_23_n1214) );
AOI222X1TS U5346 ( .A0(n3473), .A1(n3750), .B0(n3472), .B1(n3655), .C0(n3471), .C1(n3650), .Y(n3467) );
XOR2X1TS U5347 ( .A(n3468), .B(n6587), .Y(mult_x_23_n1215) );
AOI222X1TS U5348 ( .A0(n3473), .A1(n3655), .B0(n3472), .B1(n3662), .C0(n3471), .C1(n3654), .Y(n3469) );
XOR2X1TS U5349 ( .A(n3470), .B(n6587), .Y(mult_x_23_n1216) );
AOI222X1TS U5350 ( .A0(n3473), .A1(n3662), .B0(n3472), .B1(n3660), .C0(n3471), .C1(n3658), .Y(n3474) );
XOR2X1TS U5351 ( .A(n3476), .B(n6587), .Y(mult_x_23_n1217) );
XOR2X1TS U5352 ( .A(n3477), .B(n3511), .Y(mult_x_23_n1225) );
AOI222X1TS U5353 ( .A0(n3488), .A1(n3674), .B0(n3482), .B1(n3683), .C0(n3506), .C1(n3677), .Y(n3478) );
XOR2X1TS U5354 ( .A(n3479), .B(n3484), .Y(mult_x_23_n1229) );
AOI222X1TS U5355 ( .A0(n3488), .A1(n3609), .B0(n3482), .B1(n3688), .C0(n3506), .C1(n3682), .Y(n3480) );
XOR2X1TS U5356 ( .A(n3481), .B(n3484), .Y(mult_x_23_n1230) );
AOI222X1TS U5357 ( .A0(n3488), .A1(n3708), .B0(n3482), .B1(n3726), .C0(n3501), .C1(n3719), .Y(n3483) );
XOR2X1TS U5358 ( .A(n3485), .B(n3484), .Y(mult_x_23_n1238) );
AOI222X1TS U5359 ( .A0(n3508), .A1(n3713), .B0(n3507), .B1(n3732), .C0(n3501), .C1(n3725), .Y(n3486) );
XOR2X1TS U5360 ( .A(n3487), .B(n3511), .Y(mult_x_23_n1239) );
AOI222X1TS U5361 ( .A0(n3488), .A1(n3719), .B0(n3507), .B1(n3738), .C0(n3501), .C1(n3731), .Y(n3489) );
XOR2X1TS U5362 ( .A(n3490), .B(n3511), .Y(mult_x_23_n1240) );
AOI222X1TS U5363 ( .A0(n3508), .A1(n3725), .B0(n3507), .B1(n3743), .C0(n3501), .C1(n3737), .Y(n3491) );
XOR2X1TS U5364 ( .A(n3492), .B(n3511), .Y(mult_x_23_n1241) );
AOI222X1TS U5365 ( .A0(n3508), .A1(n3731), .B0(n3507), .B1(n3752), .C0(n3501), .C1(n3742), .Y(n3493) );
XOR2X1TS U5366 ( .A(n3494), .B(n3511), .Y(mult_x_23_n1242) );
AOI222X1TS U5367 ( .A0(n3508), .A1(n3737), .B0(n3507), .B1(n3750), .C0(n3501), .C1(n3748), .Y(n3495) );
XOR2X1TS U5368 ( .A(n3496), .B(n3511), .Y(mult_x_23_n1243) );
AOI222X1TS U5369 ( .A0(n3508), .A1(n3748), .B0(n3507), .B1(n3662), .C0(n3501), .C1(n3654), .Y(n3497) );
XOR2X1TS U5370 ( .A(n3498), .B(n3511), .Y(mult_x_23_n1245) );
AOI222X1TS U5371 ( .A0(n3508), .A1(n3650), .B0(n3507), .B1(n3660), .C0(n3501), .C1(n3658), .Y(n3499) );
XOR2X1TS U5372 ( .A(n3500), .B(n3511), .Y(mult_x_23_n1246) );
AOI222X1TS U5373 ( .A0(n3508), .A1(n3660), .B0(n3507), .B1(n3588), .C0(n3501), .C1(n3582), .Y(n3502) );
XOR2X1TS U5374 ( .A(n3503), .B(n3511), .Y(mult_x_23_n1247) );
AOI222X1TS U5375 ( .A0(n3508), .A1(n3658), .B0(n3507), .B1(n3596), .C0(n3506), .C1(n3587), .Y(n3504) );
XOR2X1TS U5376 ( .A(n3505), .B(n3511), .Y(mult_x_23_n1248) );
AOI222X1TS U5377 ( .A0(n3508), .A1(n3582), .B0(n3507), .B1(n3594), .C0(n3506), .C1(n3592), .Y(n3509) );
XOR2X1TS U5378 ( .A(n3512), .B(n3511), .Y(mult_x_23_n1249) );
AOI21X1TS U5379 ( .A0(n3536), .A1(n3670), .B0(n3559), .Y(n3513) );
XOR2X1TS U5380 ( .A(n3514), .B(n6588), .Y(mult_x_23_n1255) );
AOI21X1TS U5381 ( .A0(n3536), .A1(n3674), .B0(n3515), .Y(n3516) );
XOR2X1TS U5382 ( .A(n3517), .B(n3541), .Y(mult_x_23_n1256) );
AOI222X1TS U5383 ( .A0(n3545), .A1(n767), .B0(n3559), .B1(n3678), .C0(n3536),
.C1(n3609), .Y(n3518) );
XOR2X1TS U5384 ( .A(n3519), .B(n3541), .Y(mult_x_23_n1257) );
AOI222X1TS U5385 ( .A0(n3545), .A1(n3678), .B0(n3539), .B1(n3683), .C0(n3536), .C1(n3677), .Y(n3520) );
XOR2X1TS U5386 ( .A(n3521), .B(n3541), .Y(mult_x_23_n1258) );
AOI222X1TS U5387 ( .A0(n3545), .A1(n3683), .B0(n3539), .B1(n3688), .C0(n3536), .C1(n3682), .Y(n3522) );
XOR2X1TS U5388 ( .A(n3523), .B(n3541), .Y(mult_x_23_n1259) );
AOI222X1TS U5389 ( .A0(n3545), .A1(n3688), .B0(n3539), .B1(n3694), .C0(n3536), .C1(n3687), .Y(n3524) );
XOR2X1TS U5390 ( .A(n3525), .B(n3541), .Y(mult_x_23_n1260) );
AOI222X1TS U5391 ( .A0(n3545), .A1(n3694), .B0(n3539), .B1(n3693), .C0(n3536), .C1(n3692), .Y(n3526) );
XOR2X1TS U5392 ( .A(n3527), .B(n3541), .Y(mult_x_23_n1261) );
AOI222X1TS U5393 ( .A0(n3545), .A1(n3693), .B0(n3539), .B1(n3699), .C0(n3536), .C1(n3621), .Y(n3528) );
XOR2X1TS U5394 ( .A(n3529), .B(n3541), .Y(mult_x_23_n1262) );
AOI222X1TS U5395 ( .A0(n3545), .A1(n3699), .B0(n3539), .B1(n3704), .C0(n3536), .C1(n3698), .Y(n3530) );
XOR2X1TS U5396 ( .A(n3531), .B(n3541), .Y(mult_x_23_n1263) );
AOI222X1TS U5397 ( .A0(n3545), .A1(n3704), .B0(n3539), .B1(n3709), .C0(n3536), .C1(n3703), .Y(n3532) );
XOR2X1TS U5398 ( .A(n3533), .B(n3541), .Y(mult_x_23_n1264) );
AOI222X1TS U5399 ( .A0(n3545), .A1(n3709), .B0(n3539), .B1(n3715), .C0(n3536), .C1(n3708), .Y(n3534) );
XOR2X1TS U5400 ( .A(n3535), .B(n3541), .Y(mult_x_23_n1265) );
AOI222X1TS U5401 ( .A0(n3545), .A1(n3715), .B0(n3539), .B1(n3721), .C0(n3536), .C1(n3713), .Y(n3537) );
XOR2X1TS U5402 ( .A(n3538), .B(n3541), .Y(mult_x_23_n1266) );
AOI222X1TS U5403 ( .A0(n3545), .A1(n3721), .B0(n3539), .B1(n3726), .C0(n3558), .C1(n3719), .Y(n3540) );
XOR2X1TS U5404 ( .A(n3542), .B(n3541), .Y(mult_x_23_n1267) );
AOI222X1TS U5405 ( .A0(n3560), .A1(n3726), .B0(n3559), .B1(n3732), .C0(n3558), .C1(n3725), .Y(n3543) );
XOR2X1TS U5406 ( .A(n3544), .B(n6588), .Y(mult_x_23_n1268) );
AOI222X1TS U5407 ( .A0(n3545), .A1(n3732), .B0(n3559), .B1(n3738), .C0(n3558), .C1(n3731), .Y(n3546) );
XOR2X1TS U5408 ( .A(n3547), .B(n6588), .Y(mult_x_23_n1269) );
AOI222X1TS U5409 ( .A0(n3560), .A1(n3738), .B0(n3559), .B1(n3743), .C0(n3558), .C1(n3737), .Y(n3548) );
XOR2X1TS U5410 ( .A(n3549), .B(n6588), .Y(mult_x_23_n1270) );
AOI222X1TS U5411 ( .A0(n3560), .A1(n3743), .B0(n3559), .B1(n3752), .C0(n3558), .C1(n3742), .Y(n3550) );
XOR2X1TS U5412 ( .A(n3551), .B(n6588), .Y(mult_x_23_n1271) );
AOI222X1TS U5413 ( .A0(n3560), .A1(n3752), .B0(n3559), .B1(n3750), .C0(n3558), .C1(n3748), .Y(n3552) );
XOR2X1TS U5414 ( .A(n3553), .B(n6588), .Y(mult_x_23_n1272) );
AOI222X1TS U5415 ( .A0(n3560), .A1(n3750), .B0(n3559), .B1(n3655), .C0(n3558), .C1(n3650), .Y(n3554) );
XOR2X1TS U5416 ( .A(n3555), .B(n6588), .Y(mult_x_23_n1273) );
AOI222X1TS U5417 ( .A0(n3560), .A1(n3655), .B0(n3559), .B1(n3662), .C0(n3558), .C1(n3654), .Y(n3556) );
XOR2X1TS U5418 ( .A(n3557), .B(n6588), .Y(mult_x_23_n1274) );
AOI222X1TS U5419 ( .A0(n3560), .A1(n3662), .B0(n3559), .B1(n3660), .C0(n3558), .C1(n3658), .Y(n3561) );
XOR2X1TS U5420 ( .A(n3563), .B(n6588), .Y(mult_x_23_n1275) );
XOR2X1TS U5421 ( .A(n3564), .B(n3600), .Y(mult_x_23_n1283) );
AOI21X1TS U5422 ( .A0(n3593), .A1(n3670), .B0(n3595), .Y(n3565) );
XOR2X1TS U5423 ( .A(n3566), .B(n3600), .Y(mult_x_23_n1284) );
AOI222X1TS U5424 ( .A0(n3597), .A1(n3726), .B0(n3595), .B1(n3732), .C0(n3583), .C1(n3725), .Y(n3567) );
XOR2X1TS U5425 ( .A(n3568), .B(n3600), .Y(mult_x_23_n1297) );
AOI222X1TS U5426 ( .A0(n3569), .A1(n3732), .B0(n3595), .B1(n3738), .C0(n3583), .C1(n3731), .Y(n3570) );
XOR2X1TS U5427 ( .A(n3571), .B(n3600), .Y(mult_x_23_n1298) );
AOI222X1TS U5428 ( .A0(n3597), .A1(n3738), .B0(n3595), .B1(n3743), .C0(n3583), .C1(n3737), .Y(n3572) );
XOR2X1TS U5429 ( .A(n3573), .B(n3600), .Y(mult_x_23_n1299) );
AOI222X1TS U5430 ( .A0(n3597), .A1(n3743), .B0(n3595), .B1(n3752), .C0(n3583), .C1(n3742), .Y(n3574) );
XOR2X1TS U5431 ( .A(n3575), .B(n3600), .Y(mult_x_23_n1300) );
AOI222X1TS U5432 ( .A0(n3597), .A1(n3752), .B0(n3595), .B1(n3750), .C0(n3583), .C1(n3748), .Y(n3576) );
XOR2X1TS U5433 ( .A(n3577), .B(n3600), .Y(mult_x_23_n1301) );
AOI222X1TS U5434 ( .A0(n3597), .A1(n3655), .B0(n3595), .B1(n3662), .C0(n3583), .C1(n3654), .Y(n3578) );
XOR2X1TS U5435 ( .A(n3579), .B(n3600), .Y(mult_x_23_n1303) );
AOI222X1TS U5436 ( .A0(n3597), .A1(n3662), .B0(n3595), .B1(n3660), .C0(n3583), .C1(n3658), .Y(n3580) );
XOR2X1TS U5437 ( .A(n3581), .B(n3600), .Y(mult_x_23_n1304) );
AOI222X1TS U5438 ( .A0(n3597), .A1(n3660), .B0(n3595), .B1(n3588), .C0(n3583), .C1(n3582), .Y(n3584) );
XOR2X1TS U5439 ( .A(n3586), .B(n3600), .Y(mult_x_23_n1305) );
AOI222X1TS U5440 ( .A0(n3597), .A1(n3588), .B0(n3595), .B1(n3596), .C0(n3593), .C1(n3587), .Y(n3589) );
XOR2X1TS U5441 ( .A(n3591), .B(n3600), .Y(mult_x_23_n1306) );
AOI222X1TS U5442 ( .A0(n3597), .A1(n3596), .B0(n3595), .B1(n3594), .C0(n3593), .C1(n3592), .Y(n3598) );
XOR2X1TS U5443 ( .A(n3601), .B(n3600), .Y(mult_x_23_n1307) );
XOR2X1TS U5444 ( .A(n3602), .B(n6589), .Y(mult_x_23_n1312) );
AOI21X1TS U5445 ( .A0(n3631), .A1(n3670), .B0(n3661), .Y(n3603) );
INVX2TS U5446 ( .A(n6553), .Y(n3604) );
XOR2X1TS U5447 ( .A(n3605), .B(n3604), .Y(mult_x_23_n1313) );
AOI21X1TS U5448 ( .A0(n3631), .A1(n3674), .B0(n3606), .Y(n3607) );
XOR2X1TS U5449 ( .A(n3608), .B(n3637), .Y(mult_x_23_n1314) );
AOI222X1TS U5450 ( .A0(n3641), .A1(n767), .B0(n3661), .B1(n3678), .C0(n3631),
.C1(n3609), .Y(n3610) );
XOR2X1TS U5451 ( .A(n3612), .B(n3637), .Y(mult_x_23_n1315) );
AOI222X1TS U5452 ( .A0(n3641), .A1(n3678), .B0(n3634), .B1(n3683), .C0(n3631), .C1(n3677), .Y(n3613) );
XOR2X1TS U5453 ( .A(n3614), .B(n3637), .Y(mult_x_23_n1316) );
AOI222X1TS U5454 ( .A0(n3641), .A1(n3683), .B0(n3634), .B1(n3688), .C0(n3631), .C1(n3682), .Y(n3615) );
XOR2X1TS U5455 ( .A(n3616), .B(n3637), .Y(mult_x_23_n1317) );
AOI222X1TS U5456 ( .A0(n3641), .A1(n3688), .B0(n3634), .B1(n3694), .C0(n3631), .C1(n3687), .Y(n3617) );
XOR2X1TS U5457 ( .A(n3618), .B(n3637), .Y(mult_x_23_n1318) );
AOI222X1TS U5458 ( .A0(n3641), .A1(n3694), .B0(n3634), .B1(n3693), .C0(n3631), .C1(n3692), .Y(n3619) );
XOR2X1TS U5459 ( .A(n3620), .B(n3637), .Y(mult_x_23_n1319) );
AOI222X1TS U5460 ( .A0(n3641), .A1(n3693), .B0(n3634), .B1(n3699), .C0(n3631), .C1(n3621), .Y(n3622) );
XOR2X1TS U5461 ( .A(n3624), .B(n3637), .Y(mult_x_23_n1320) );
AOI222X1TS U5462 ( .A0(n3641), .A1(n3699), .B0(n3634), .B1(n3704), .C0(n3631), .C1(n3698), .Y(n3625) );
XOR2X1TS U5463 ( .A(n3626), .B(n3637), .Y(mult_x_23_n1321) );
AOI222X1TS U5464 ( .A0(n3641), .A1(n3704), .B0(n3634), .B1(n3709), .C0(n3631), .C1(n3703), .Y(n3627) );
XOR2X1TS U5465 ( .A(n3628), .B(n3637), .Y(mult_x_23_n1322) );
XOR2X1TS U5466 ( .A(n3630), .B(n3637), .Y(mult_x_23_n1323) );
AOI222X1TS U5467 ( .A0(n3641), .A1(n3715), .B0(n3634), .B1(n3721), .C0(n3631), .C1(n3713), .Y(n3632) );
XOR2X1TS U5468 ( .A(n3633), .B(n3637), .Y(mult_x_23_n1324) );
AOI222X1TS U5469 ( .A0(n3641), .A1(n3721), .B0(n3634), .B1(n3726), .C0(n3659), .C1(n3719), .Y(n3635) );
XOR2X1TS U5470 ( .A(n3638), .B(n3637), .Y(mult_x_23_n1325) );
AOI222X1TS U5471 ( .A0(n3663), .A1(n3726), .B0(n3661), .B1(n3732), .C0(n3659), .C1(n3725), .Y(n3639) );
XOR2X1TS U5472 ( .A(n3640), .B(n6589), .Y(mult_x_23_n1326) );
AOI222X1TS U5473 ( .A0(n3641), .A1(n3732), .B0(n3661), .B1(n3738), .C0(n3659), .C1(n3731), .Y(n3642) );
XOR2X1TS U5474 ( .A(n3643), .B(n6589), .Y(mult_x_23_n1327) );
AOI222X1TS U5475 ( .A0(n3663), .A1(n3738), .B0(n3661), .B1(n3743), .C0(n3659), .C1(n3737), .Y(n3644) );
XOR2X1TS U5476 ( .A(n3645), .B(n3604), .Y(mult_x_23_n1328) );
AOI222X1TS U5477 ( .A0(n3663), .A1(n3743), .B0(n3661), .B1(n3752), .C0(n3659), .C1(n3742), .Y(n3646) );
XOR2X1TS U5478 ( .A(n3647), .B(n6589), .Y(mult_x_23_n1329) );
AOI222X1TS U5479 ( .A0(n3663), .A1(n3752), .B0(n3661), .B1(n3750), .C0(n3659), .C1(n3748), .Y(n3648) );
XOR2X1TS U5480 ( .A(n3649), .B(n6589), .Y(mult_x_23_n1330) );
AOI222X1TS U5481 ( .A0(n3663), .A1(n3750), .B0(n3661), .B1(n3655), .C0(n3659), .C1(n3650), .Y(n3651) );
XOR2X1TS U5482 ( .A(n3653), .B(n6589), .Y(mult_x_23_n1331) );
AOI222X1TS U5483 ( .A0(n3663), .A1(n3655), .B0(n3661), .B1(n3662), .C0(n3659), .C1(n3654), .Y(n3656) );
XOR2X1TS U5484 ( .A(n3657), .B(n3604), .Y(mult_x_23_n1332) );
AOI222X1TS U5485 ( .A0(n3663), .A1(n3662), .B0(n3661), .B1(n3660), .C0(n3659), .C1(n3658), .Y(n3664) );
XOR2X1TS U5486 ( .A(n3667), .B(n6589), .Y(mult_x_23_n1333) );
XOR2X1TS U5487 ( .A(n3669), .B(n3756), .Y(mult_x_23_n1341) );
AOI21X1TS U5488 ( .A0(n3714), .A1(n3670), .B0(n3751), .Y(n3671) );
XOR2X1TS U5489 ( .A(n3672), .B(n3756), .Y(mult_x_23_n1342) );
AOI21X1TS U5490 ( .A0(n3714), .A1(n3674), .B0(n3673), .Y(n3675) );
XOR2X1TS U5491 ( .A(n3676), .B(n3756), .Y(mult_x_23_n1343) );
AOI222X1TS U5492 ( .A0(n3733), .A1(n3678), .B0(n3720), .B1(n3683), .C0(n3714), .C1(n3677), .Y(n3679) );
XOR2X1TS U5493 ( .A(n3681), .B(n3756), .Y(mult_x_23_n1345) );
AOI222X1TS U5494 ( .A0(n3733), .A1(n3683), .B0(n3720), .B1(n3688), .C0(n3714), .C1(n3682), .Y(n3684) );
XOR2X1TS U5495 ( .A(n3686), .B(n3756), .Y(mult_x_23_n1346) );
AOI222X1TS U5496 ( .A0(n3733), .A1(n3688), .B0(n3720), .B1(n3694), .C0(n3714), .C1(n3687), .Y(n3689) );
XOR2X1TS U5497 ( .A(n3691), .B(n3746), .Y(mult_x_23_n1347) );
AOI222X1TS U5498 ( .A0(n3733), .A1(n3694), .B0(n3720), .B1(n3693), .C0(n3714), .C1(n3692), .Y(n3695) );
XOR2X1TS U5499 ( .A(n3697), .B(n3756), .Y(mult_x_23_n1348) );
AOI222X1TS U5500 ( .A0(n3733), .A1(n3699), .B0(n3720), .B1(n3704), .C0(n3714), .C1(n3698), .Y(n3700) );
XOR2X1TS U5501 ( .A(n3702), .B(Op_MX[29]), .Y(mult_x_23_n1350) );
AOI222X1TS U5502 ( .A0(n3733), .A1(n3704), .B0(n3720), .B1(n3709), .C0(n3714), .C1(n3703), .Y(n3705) );
XOR2X1TS U5503 ( .A(n3707), .B(Op_MX[29]), .Y(mult_x_23_n1351) );
AOI222X1TS U5504 ( .A0(n3733), .A1(n3709), .B0(n3720), .B1(n3715), .C0(n3714), .C1(n3708), .Y(n3710) );
XOR2X1TS U5505 ( .A(n3712), .B(n3746), .Y(mult_x_23_n1352) );
AOI222X1TS U5506 ( .A0(n3733), .A1(n3715), .B0(n3720), .B1(n3721), .C0(n3714), .C1(n3713), .Y(n3716) );
XOR2X1TS U5507 ( .A(n3718), .B(Op_MX[29]), .Y(mult_x_23_n1353) );
AOI222X1TS U5508 ( .A0(n3733), .A1(n3721), .B0(n3720), .B1(n3726), .C0(n3749), .C1(n3719), .Y(n3722) );
XOR2X1TS U5509 ( .A(n3724), .B(n3746), .Y(mult_x_23_n1354) );
AOI222X1TS U5510 ( .A0(n3753), .A1(n3726), .B0(n3751), .B1(n3732), .C0(n3749), .C1(n3725), .Y(n3727) );
XOR2X1TS U5511 ( .A(n3730), .B(n3746), .Y(mult_x_23_n1355) );
AOI222X1TS U5512 ( .A0(n3733), .A1(n3732), .B0(n3751), .B1(n3738), .C0(n3749), .C1(n3731), .Y(n3734) );
XOR2X1TS U5513 ( .A(n3736), .B(n3746), .Y(mult_x_23_n1356) );
AOI222X1TS U5514 ( .A0(n3753), .A1(n3738), .B0(n3751), .B1(n3743), .C0(n3749), .C1(n3737), .Y(n3739) );
XOR2X1TS U5515 ( .A(n3741), .B(n3746), .Y(mult_x_23_n1357) );
AOI222X1TS U5516 ( .A0(n3753), .A1(n3743), .B0(n3751), .B1(n3752), .C0(n3749), .C1(n3742), .Y(n3744) );
XOR2X1TS U5517 ( .A(n3747), .B(n3746), .Y(mult_x_23_n1358) );
AOI222X1TS U5518 ( .A0(n3753), .A1(n3752), .B0(n3751), .B1(n3750), .C0(n3749), .C1(n3748), .Y(n3754) );
XOR2X1TS U5519 ( .A(n3757), .B(n3756), .Y(mult_x_23_n1359) );
OR2X2TS U5520 ( .A(mult_x_24_n623), .B(mult_x_24_n631), .Y(n3887) );
NAND2X1TS U5521 ( .A(n3887), .B(n3883), .Y(n3764) );
INVX2TS U5522 ( .A(n3760), .Y(n3890) );
NAND2X1TS U5523 ( .A(mult_x_24_n632), .B(mult_x_24_n641), .Y(n3893) );
INVX2TS U5524 ( .A(n3893), .Y(n3761) );
AOI21X1TS U5525 ( .A0(n751), .A1(n3890), .B0(n3761), .Y(n3878) );
NAND2X1TS U5526 ( .A(mult_x_24_n623), .B(mult_x_24_n631), .Y(n3886) );
INVX2TS U5527 ( .A(n3886), .Y(n3881) );
NAND2X1TS U5528 ( .A(mult_x_24_n614), .B(mult_x_24_n622), .Y(n3882) );
INVX2TS U5529 ( .A(n3882), .Y(n3762) );
AOI21X1TS U5530 ( .A0(n3883), .A1(n3881), .B0(n3762), .Y(n3763) );
AOI21X1TS U5531 ( .A0(n3767), .A1(n3766), .B0(n3765), .Y(n3768) );
OAI21X1TS U5532 ( .A0(n3770), .A1(n3769), .B0(n3768), .Y(n3771) );
NOR2X1TS U5533 ( .A(mult_x_24_n605), .B(mult_x_24_n613), .Y(n3867) );
NOR2X2TS U5534 ( .A(mult_x_24_n597), .B(mult_x_24_n604), .Y(n3869) );
NOR2X1TS U5535 ( .A(n3867), .B(n3869), .Y(n3862) );
NAND2X1TS U5536 ( .A(n3862), .B(n3864), .Y(n3776) );
NAND2X1TS U5537 ( .A(mult_x_24_n605), .B(mult_x_24_n613), .Y(n3874) );
NAND2X1TS U5538 ( .A(mult_x_24_n597), .B(mult_x_24_n604), .Y(n3870) );
OAI21X1TS U5539 ( .A0(n3869), .A1(n3874), .B0(n3870), .Y(n3861) );
NAND2X1TS U5540 ( .A(mult_x_24_n590), .B(mult_x_24_n596), .Y(n3863) );
INVX2TS U5541 ( .A(n3863), .Y(n3774) );
AOI21X1TS U5542 ( .A0(n3861), .A1(n3864), .B0(n3774), .Y(n3775) );
NAND2X1TS U5543 ( .A(mult_x_24_n583), .B(mult_x_24_n589), .Y(n3856) );
INVX2TS U5544 ( .A(n3856), .Y(n3777) );
NOR2X1TS U5545 ( .A(mult_x_24_n577), .B(mult_x_24_n582), .Y(n3851) );
NAND2X1TS U5546 ( .A(mult_x_24_n577), .B(mult_x_24_n582), .Y(n3852) );
NAND2X1TS U5547 ( .A(mult_x_24_n571), .B(mult_x_24_n576), .Y(n3847) );
INVX2TS U5548 ( .A(n3847), .Y(n3778) );
AOI21X4TS U5549 ( .A0(n3850), .A1(n3848), .B0(n3778), .Y(n3846) );
NOR2X1TS U5550 ( .A(mult_x_24_n570), .B(mult_x_24_n565), .Y(n3842) );
NAND2X1TS U5551 ( .A(mult_x_24_n570), .B(mult_x_24_n565), .Y(n3843) );
OAI21X4TS U5552 ( .A0(n3846), .A1(n3842), .B0(n3843), .Y(n3841) );
NAND2X1TS U5553 ( .A(mult_x_24_n560), .B(mult_x_24_n564), .Y(n3838) );
INVX2TS U5554 ( .A(n3838), .Y(n3779) );
AOI21X4TS U5555 ( .A0(n3841), .A1(n3839), .B0(n3779), .Y(n3837) );
NOR2X1TS U5556 ( .A(mult_x_24_n559), .B(mult_x_24_n556), .Y(n3833) );
NAND2X1TS U5557 ( .A(mult_x_24_n559), .B(mult_x_24_n556), .Y(n3834) );
OAI21X4TS U5558 ( .A0(n3837), .A1(n3833), .B0(n3834), .Y(n3832) );
NAND2X1TS U5559 ( .A(mult_x_24_n552), .B(mult_x_24_n555), .Y(n3829) );
INVX2TS U5560 ( .A(n3829), .Y(n3780) );
AOI21X4TS U5561 ( .A0(n3832), .A1(n3830), .B0(n3780), .Y(n3828) );
NOR2X1TS U5562 ( .A(mult_x_24_n549), .B(mult_x_24_n551), .Y(n3824) );
NAND2X1TS U5563 ( .A(mult_x_24_n549), .B(mult_x_24_n551), .Y(n3825) );
CLKAND2X2TS U5564 ( .A(n4106), .B(n4568), .Y(n3807) );
INVX2TS U5565 ( .A(n3807), .Y(n3804) );
AOI21X1TS U5566 ( .A0(n3785), .A1(n3784), .B0(n3783), .Y(n3786) );
XNOR2X4TS U5567 ( .A(n3792), .B(n4971), .Y(n4555) );
AOI21X1TS U5568 ( .A0(n4160), .A1(n4563), .B0(n3793), .Y(n3794) );
XOR2X1TS U5569 ( .A(n3795), .B(n4075), .Y(n3798) );
NAND2X1TS U5570 ( .A(mult_x_24_n548), .B(n3796), .Y(n3820) );
INVX2TS U5571 ( .A(n3820), .Y(n3797) );
AOI21X4TS U5572 ( .A0(n3823), .A1(n3821), .B0(n3797), .Y(n3819) );
CMPR32X2TS U5573 ( .A(n3804), .B(mult_x_24_n547), .C(n3798), .CO(n3802), .S(
n3796) );
CLKAND2X2TS U5574 ( .A(n4106), .B(n4563), .Y(n3805) );
NAND2X1TS U5575 ( .A(n4160), .B(n4383), .Y(n3799) );
XOR2X1TS U5576 ( .A(n3800), .B(n4075), .Y(n3803) );
NOR2X1TS U5577 ( .A(n3802), .B(n3801), .Y(n3815) );
NAND2X1TS U5578 ( .A(n3802), .B(n3801), .Y(n3816) );
CMPR32X2TS U5579 ( .A(n3805), .B(n3804), .C(n3803), .CO(n3810), .S(n3801) );
CLKAND2X2TS U5580 ( .A(n4558), .B(n4106), .Y(n3806) );
XOR3X1TS U5581 ( .A(n6545), .B(n3807), .C(n3806), .Y(n3809) );
OR2X1TS U5582 ( .A(n3810), .B(n3809), .Y(n3812) );
NAND2X1TS U5583 ( .A(n3810), .B(n3809), .Y(n3811) );
NAND2X1TS U5584 ( .A(n3812), .B(n3811), .Y(n3813) );
XNOR2X1TS U5585 ( .A(n3814), .B(n3813), .Y(Sgf_operation_ODD1_right_N53) );
INVX2TS U5586 ( .A(n3815), .Y(n3817) );
NAND2X1TS U5587 ( .A(n3817), .B(n3816), .Y(n3818) );
NAND2X1TS U5588 ( .A(n3821), .B(n3820), .Y(n3822) );
XNOR2X1TS U5589 ( .A(n3823), .B(n3822), .Y(Sgf_operation_ODD1_right_N51) );
INVX2TS U5590 ( .A(n3824), .Y(n3826) );
NAND2X1TS U5591 ( .A(n3826), .B(n3825), .Y(n3827) );
NAND2X1TS U5592 ( .A(n3830), .B(n3829), .Y(n3831) );
XNOR2X1TS U5593 ( .A(n3832), .B(n3831), .Y(Sgf_operation_ODD1_right_N49) );
NAND2X1TS U5594 ( .A(n3835), .B(n3834), .Y(n3836) );
NAND2X1TS U5595 ( .A(n3839), .B(n3838), .Y(n3840) );
XNOR2X1TS U5596 ( .A(n3841), .B(n3840), .Y(Sgf_operation_ODD1_right_N47) );
NAND2X1TS U5597 ( .A(n3844), .B(n3843), .Y(n3845) );
NAND2X1TS U5598 ( .A(n3848), .B(n3847), .Y(n3849) );
XNOR2X1TS U5599 ( .A(n3850), .B(n3849), .Y(Sgf_operation_ODD1_right_N45) );
NAND2X1TS U5600 ( .A(n3853), .B(n3852), .Y(n3854) );
NAND2X1TS U5601 ( .A(n3857), .B(n3856), .Y(n3858) );
XNOR2X1TS U5602 ( .A(n3859), .B(n3858), .Y(Sgf_operation_ODD1_right_N43) );
INVX2TS U5603 ( .A(n3860), .Y(n3877) );
AOI21X1TS U5604 ( .A0(n3877), .A1(n3862), .B0(n3861), .Y(n3866) );
NAND2X1TS U5605 ( .A(n3864), .B(n3863), .Y(n3865) );
INVX2TS U5606 ( .A(n3867), .Y(n3875) );
INVX2TS U5607 ( .A(n3874), .Y(n3868) );
AOI21X1TS U5608 ( .A0(n3877), .A1(n3875), .B0(n3868), .Y(n3873) );
INVX2TS U5609 ( .A(n3869), .Y(n3871) );
NAND2X1TS U5610 ( .A(n3871), .B(n3870), .Y(n3872) );
NAND2X1TS U5611 ( .A(n3875), .B(n3874), .Y(n3876) );
XNOR2X1TS U5612 ( .A(n3877), .B(n3876), .Y(Sgf_operation_ODD1_right_N40) );
OAI21X1TS U5613 ( .A0(n3880), .A1(n3879), .B0(n3878), .Y(n3889) );
AOI21X1TS U5614 ( .A0(n3889), .A1(n3887), .B0(n3881), .Y(n3885) );
NAND2X1TS U5615 ( .A(n3883), .B(n3882), .Y(n3884) );
NAND2X1TS U5616 ( .A(n3887), .B(n3886), .Y(n3888) );
XNOR2X1TS U5617 ( .A(n3889), .B(n3888), .Y(Sgf_operation_ODD1_right_N38) );
AOI21X1TS U5618 ( .A0(n3892), .A1(n3891), .B0(n3890), .Y(n3895) );
NAND2X1TS U5619 ( .A(n751), .B(n3893), .Y(n3894) );
NAND2X1TS U5620 ( .A(n3897), .B(n3896), .Y(n3898) );
XNOR2X1TS U5621 ( .A(n3899), .B(n3898), .Y(Sgf_operation_ODD1_right_N32) );
INVX2TS U5622 ( .A(n3900), .Y(n3902) );
NAND2X1TS U5623 ( .A(n3902), .B(n3901), .Y(n3903) );
XNOR2X1TS U5624 ( .A(n3904), .B(n3903), .Y(Sgf_operation_ODD1_right_N31) );
INVX2TS U5625 ( .A(n3905), .Y(n3907) );
NAND2X1TS U5626 ( .A(n3907), .B(n3906), .Y(n3908) );
INVX2TS U5627 ( .A(n3910), .Y(n3938) );
AOI21X1TS U5628 ( .A0(n3938), .A1(n3912), .B0(n3911), .Y(n3922) );
INVX2TS U5629 ( .A(n3913), .Y(n3915) );
NAND2X1TS U5630 ( .A(n3915), .B(n3914), .Y(n3916) );
XNOR2X1TS U5631 ( .A(n3917), .B(n3916), .Y(Sgf_operation_ODD1_right_N29) );
INVX2TS U5632 ( .A(n3918), .Y(n3920) );
NAND2X1TS U5633 ( .A(n3920), .B(n3919), .Y(n3921) );
INVX2TS U5634 ( .A(n3923), .Y(n3926) );
INVX2TS U5635 ( .A(n3924), .Y(n3925) );
AOI21X1TS U5636 ( .A0(n3938), .A1(n3926), .B0(n3925), .Y(n3931) );
INVX2TS U5637 ( .A(n3927), .Y(n3929) );
NAND2X1TS U5638 ( .A(n3929), .B(n3928), .Y(n3930) );
AOI21X1TS U5639 ( .A0(n3938), .A1(n882), .B0(n3932), .Y(n3935) );
NAND2X1TS U5640 ( .A(n881), .B(n3933), .Y(n3934) );
NAND2X1TS U5641 ( .A(n882), .B(n3936), .Y(n3937) );
XNOR2X1TS U5642 ( .A(n3938), .B(n3937), .Y(Sgf_operation_ODD1_right_N25) );
INVX2TS U5643 ( .A(n3939), .Y(n3956) );
OAI21X1TS U5644 ( .A0(n3956), .A1(n3941), .B0(n3940), .Y(n3948) );
AOI21X1TS U5645 ( .A0(n3948), .A1(n884), .B0(n3942), .Y(n3945) );
NAND2X1TS U5646 ( .A(n883), .B(n3943), .Y(n3944) );
NAND2X1TS U5647 ( .A(n884), .B(n3946), .Y(n3947) );
XNOR2X1TS U5648 ( .A(n3948), .B(n3947), .Y(Sgf_operation_ODD1_right_N23) );
NAND2X1TS U5649 ( .A(n885), .B(n3950), .Y(n3951) );
XNOR2X1TS U5650 ( .A(n3952), .B(n3951), .Y(Sgf_operation_ODD1_right_N22) );
NAND2X1TS U5651 ( .A(n3954), .B(n3953), .Y(n3955) );
INVX2TS U5652 ( .A(n3957), .Y(n3964) );
AOI21X1TS U5653 ( .A0(n3964), .A1(n887), .B0(n3958), .Y(n3961) );
NAND2X1TS U5654 ( .A(n886), .B(n3959), .Y(n3960) );
NAND2X1TS U5655 ( .A(n887), .B(n3962), .Y(n3963) );
XNOR2X1TS U5656 ( .A(n3964), .B(n3963), .Y(Sgf_operation_ODD1_right_N19) );
INVX2TS U5657 ( .A(n3968), .Y(n3970) );
NAND2X1TS U5658 ( .A(n3970), .B(n3969), .Y(n3971) );
XNOR2X1TS U5659 ( .A(n3972), .B(n3971), .Y(Sgf_operation_ODD1_right_N18) );
INVX2TS U5660 ( .A(n3973), .Y(n3990) );
AOI21X1TS U5661 ( .A0(n3990), .A1(n3975), .B0(n3974), .Y(n3979) );
NAND2X1TS U5662 ( .A(n3977), .B(n3976), .Y(n3978) );
INVX2TS U5663 ( .A(n3980), .Y(n3988) );
INVX2TS U5664 ( .A(n3987), .Y(n3981) );
AOI21X1TS U5665 ( .A0(n3990), .A1(n3988), .B0(n3981), .Y(n3986) );
INVX2TS U5666 ( .A(n3982), .Y(n3984) );
NAND2X1TS U5667 ( .A(n3984), .B(n3983), .Y(n3985) );
NAND2X1TS U5668 ( .A(n3988), .B(n3987), .Y(n3989) );
XNOR2X1TS U5669 ( .A(n3990), .B(n3989), .Y(Sgf_operation_ODD1_right_N14) );
INVX2TS U5670 ( .A(n3994), .Y(n3996) );
NAND2X1TS U5671 ( .A(n3996), .B(n3995), .Y(n3997) );
XNOR2X1TS U5672 ( .A(n3998), .B(n3997), .Y(Sgf_operation_ODD1_right_N13) );
INVX2TS U5673 ( .A(n3999), .Y(n4005) );
AOI21X1TS U5674 ( .A0(n4005), .A1(n878), .B0(n4000), .Y(n4003) );
NAND2X1TS U5675 ( .A(n879), .B(n4001), .Y(n4002) );
NAND2X1TS U5676 ( .A(n878), .B(n4004), .Y(n4006) );
XNOR2X1TS U5677 ( .A(n4006), .B(n4005), .Y(Sgf_operation_ODD1_right_N10) );
INVX2TS U5678 ( .A(n4007), .Y(n4017) );
INVX2TS U5679 ( .A(n4008), .Y(n4010) );
NAND2X1TS U5680 ( .A(n4010), .B(n4009), .Y(n4011) );
XNOR2X1TS U5681 ( .A(n4012), .B(n4011), .Y(Sgf_operation_ODD1_right_N9) );
INVX2TS U5682 ( .A(n4013), .Y(n4015) );
NAND2X1TS U5683 ( .A(n4015), .B(n4014), .Y(n4016) );
INVX2TS U5684 ( .A(n4018), .Y(n4020) );
NAND2X1TS U5685 ( .A(n4020), .B(n4019), .Y(n4021) );
INVX2TS U5686 ( .A(n4023), .Y(n4032) );
INVX2TS U5687 ( .A(n4024), .Y(n4026) );
NAND2X1TS U5688 ( .A(n4026), .B(n4025), .Y(n4027) );
XNOR2X1TS U5689 ( .A(n4028), .B(n4027), .Y(Sgf_operation_ODD1_right_N6) );
INVX2TS U5690 ( .A(n4029), .Y(n4031) );
NAND2X1TS U5691 ( .A(n4031), .B(n4030), .Y(n4033) );
INVX2TS U5692 ( .A(n4034), .Y(n4036) );
NAND2X1TS U5693 ( .A(n4036), .B(n4035), .Y(n4037) );
NAND2X1TS U5694 ( .A(n4040), .B(n4039), .Y(n4042) );
XNOR2X1TS U5695 ( .A(n4042), .B(n4041), .Y(Sgf_operation_ODD1_right_N3) );
XOR2XLTS U5696 ( .A(n848), .B(n4043), .Y(Sgf_operation_ODD1_right_N2) );
INVX2TS U5697 ( .A(n4044), .Y(n4045) );
XNOR2X1TS U5698 ( .A(n4045), .B(n2366), .Y(Sgf_operation_ODD1_right_N1) );
CMPR32X2TS U5699 ( .A(n6564), .B(n4047), .C(n4046), .CO(mult_x_24_n561), .S(
mult_x_24_n562) );
INVX2TS U5700 ( .A(n4047), .Y(n4055) );
NAND2X1TS U5701 ( .A(n4237), .B(n4383), .Y(n4048) );
XOR2X1TS U5702 ( .A(n4049), .B(n6592), .Y(n4050) );
CMPR32X2TS U5703 ( .A(n4051), .B(n4055), .C(n4050), .CO(mult_x_24_n566), .S(
mult_x_24_n567) );
AOI222X1TS U5704 ( .A0(n4162), .A1(n4577), .B0(n4161), .B1(Op_MX[20]), .C0(
n4160), .C1(n4593), .Y(n4052) );
XOR2X1TS U5705 ( .A(n4053), .B(n4093), .Y(n4054) );
CMPR32X2TS U5706 ( .A(n4055), .B(mult_x_24_n578), .C(n4054), .CO(
mult_x_24_n572), .S(mult_x_24_n573) );
CMPR32X2TS U5707 ( .A(n6558), .B(n4056), .C(n4057), .CO(mult_x_24_n601), .S(
mult_x_24_n602) );
INVX2TS U5708 ( .A(n4057), .Y(n4065) );
NAND2X1TS U5709 ( .A(n4350), .B(n4383), .Y(n4058) );
XOR2X1TS U5710 ( .A(n4059), .B(n4352), .Y(n4060) );
CMPR32X2TS U5711 ( .A(n4061), .B(n4065), .C(n4060), .CO(mult_x_24_n609), .S(
mult_x_24_n610) );
AOI222X1TS U5712 ( .A0(n4247), .A1(n4577), .B0(n4244), .B1(n4582), .C0(n4237), .C1(n4593), .Y(n4062) );
XOR2X1TS U5713 ( .A(n4063), .B(n4242), .Y(n4064) );
CMPR32X2TS U5714 ( .A(n4065), .B(mult_x_24_n627), .C(n4064), .CO(
mult_x_24_n618), .S(mult_x_24_n619) );
CMPR32X2TS U5715 ( .A(n6554), .B(n4066), .C(n4067), .CO(mult_x_24_n659), .S(
mult_x_24_n660) );
INVX2TS U5716 ( .A(n4067), .Y(n4096) );
XNOR2X4TS U5717 ( .A(n4073), .B(n4072), .Y(n4642) );
BUFX4TS U5718 ( .A(n789), .Y(n4631) );
AOI222X1TS U5719 ( .A0(n4090), .A1(n4631), .B0(n4089), .B1(Op_MX[9]), .C0(
n1989), .C1(n4637), .Y(n4074) );
XOR2X1TS U5720 ( .A(n4076), .B(n4075), .Y(n4077) );
CMPR32X2TS U5721 ( .A(n4078), .B(n4096), .C(n4077), .CO(mult_x_24_n670), .S(
mult_x_24_n671) );
NOR2X1TS U5722 ( .A(n4079), .B(n4081), .Y(n4084) );
XNOR2X4TS U5723 ( .A(n4088), .B(n4087), .Y(n4650) );
BUFX4TS U5724 ( .A(Op_MX[9]), .Y(n4638) );
AOI222X1TS U5725 ( .A0(n4090), .A1(n4638), .B0(n4089), .B1(Op_MX[8]), .C0(
n1989), .C1(n4644), .Y(n4091) );
XOR2X1TS U5726 ( .A(n4094), .B(n4093), .Y(n4095) );
CMPR32X2TS U5727 ( .A(n4096), .B(mult_x_24_n694), .C(n4095), .CO(
mult_x_24_n682), .S(mult_x_24_n683) );
ADDHXLTS U5728 ( .A(n4098), .B(n4097), .CO(n4110), .S(mult_x_24_n817) );
AOI222X1TS U5729 ( .A0(n4212), .A1(n4491), .B0(n4211), .B1(Op_MX[1]), .C0(
n4189), .C1(n4139), .Y(n4099) );
XOR2X1TS U5730 ( .A(n4100), .B(n6591), .Y(n4109) );
AOI222X1TS U5731 ( .A0(n4212), .A1(n4486), .B0(n4211), .B1(n4493), .C0(n2918), .C1(n4485), .Y(n4103) );
XOR2X1TS U5732 ( .A(n4104), .B(n6591), .Y(n4112) );
ADDHXLTS U5733 ( .A(n4106), .B(n4105), .CO(n4101), .S(n4116) );
AOI222X1TS U5734 ( .A0(n4212), .A1(n4493), .B0(n4211), .B1(n4491), .C0(n2918), .C1(n4490), .Y(n4107) );
XOR2X1TS U5735 ( .A(n4108), .B(n6591), .Y(n4115) );
ADDHXLTS U5736 ( .A(n4110), .B(n4109), .CO(n4114), .S(mult_x_24_n806) );
CMPR32X2TS U5737 ( .A(n4113), .B(n4112), .C(n4111), .CO(mult_x_24_n779), .S(
mult_x_24_n780) );
CMPR32X2TS U5738 ( .A(n4116), .B(n4115), .C(n4114), .CO(n4111), .S(
mult_x_24_n793) );
ADDHXLTS U5739 ( .A(n4118), .B(n4117), .CO(n4130), .S(mult_x_24_n874) );
BUFX4TS U5740 ( .A(n4119), .Y(n4298) );
AOI222X1TS U5741 ( .A0(n4321), .A1(n4491), .B0(n4320), .B1(n4490), .C0(n4298), .C1(n4139), .Y(n4120) );
XOR2X1TS U5742 ( .A(n4121), .B(n780), .Y(n4129) );
ADDHXLTS U5743 ( .A(n4123), .B(n4122), .CO(n2956), .S(n4133) );
AOI222X1TS U5744 ( .A0(n4321), .A1(n4486), .B0(n4320), .B1(n4493), .C0(n4119), .C1(n4485), .Y(n4124) );
XOR2X1TS U5745 ( .A(n4125), .B(n780), .Y(n4132) );
ADDHXLTS U5746 ( .A(n770), .B(n4126), .CO(n4122), .S(n4136) );
AOI222X1TS U5747 ( .A0(n4321), .A1(n4493), .B0(n4320), .B1(n4491), .C0(n4119), .C1(n4490), .Y(n4127) );
XOR2X1TS U5748 ( .A(n4128), .B(n780), .Y(n4135) );
CMPR32X2TS U5749 ( .A(n4133), .B(n4132), .C(n4131), .CO(mult_x_24_n845), .S(
mult_x_24_n846) );
CMPR32X2TS U5750 ( .A(n4136), .B(n4135), .C(n4134), .CO(n4131), .S(
mult_x_24_n856) );
ADDHXLTS U5751 ( .A(n4138), .B(n4137), .CO(n4151), .S(mult_x_24_n913) );
AOI222X1TS U5752 ( .A0(n4433), .A1(n4491), .B0(n4432), .B1(n4490), .C0(n4408), .C1(n4139), .Y(n4140) );
XOR2X1TS U5753 ( .A(n4142), .B(n777), .Y(n4150) );
AOI222X1TS U5754 ( .A0(n4433), .A1(n4486), .B0(n4432), .B1(n4493), .C0(n2939), .C1(n4485), .Y(n4145) );
XOR2X1TS U5755 ( .A(n4146), .B(n777), .Y(n4153) );
ADDHXLTS U5756 ( .A(n799), .B(n4147), .CO(n4143), .S(n4157) );
AOI222X1TS U5757 ( .A0(n4433), .A1(n4493), .B0(n4432), .B1(n4491), .C0(n2939), .C1(n4490), .Y(n4148) );
XOR2X1TS U5758 ( .A(n4149), .B(n777), .Y(n4156) );
CMPR32X2TS U5759 ( .A(n4154), .B(n4153), .C(n4152), .CO(mult_x_24_n893), .S(
mult_x_24_n894) );
CMPR32X2TS U5760 ( .A(n4157), .B(n4156), .C(n4155), .CO(n4152), .S(
mult_x_24_n901) );
CLKAND2X2TS U5761 ( .A(n4164), .B(n4159), .Y(mult_x_24_n963) );
AOI222X1TS U5762 ( .A0(n4162), .A1(n4562), .B0(n4161), .B1(Op_MX[23]), .C0(
n4160), .C1(n4578), .Y(n4163) );
XOR2X1TS U5763 ( .A(n4165), .B(n4164), .Y(mult_x_24_n1309) );
NAND2X1TS U5764 ( .A(n4189), .B(n4383), .Y(n4166) );
XOR2X1TS U5765 ( .A(n4167), .B(n798), .Y(mult_x_24_n1335) );
AOI21X1TS U5766 ( .A0(n4189), .A1(n4563), .B0(n4168), .Y(n4169) );
XOR2X1TS U5767 ( .A(n4170), .B(n798), .Y(mult_x_24_n1336) );
AOI222X1TS U5768 ( .A0(n4198), .A1(n4558), .B0(n4195), .B1(n4557), .C0(n4189), .C1(n4568), .Y(n4171) );
XOR2X1TS U5769 ( .A(n4172), .B(n4193), .Y(mult_x_24_n1337) );
AOI222X1TS U5770 ( .A0(n4198), .A1(n4567), .B0(n4195), .B1(n4572), .C0(n4189), .C1(n4583), .Y(n4173) );
XOR2X1TS U5771 ( .A(n4174), .B(n4193), .Y(mult_x_24_n1340) );
AOI222X1TS U5772 ( .A0(n4198), .A1(n4572), .B0(n4195), .B1(n4577), .C0(n4189), .C1(n4588), .Y(n4175) );
XOR2X1TS U5773 ( .A(n4176), .B(n4193), .Y(mult_x_24_n1341) );
AOI222X1TS U5774 ( .A0(n4198), .A1(n4577), .B0(n4195), .B1(n4582), .C0(n4189), .C1(n4593), .Y(n4177) );
XOR2X1TS U5775 ( .A(n4178), .B(n4193), .Y(mult_x_24_n1342) );
AOI222X1TS U5776 ( .A0(n4198), .A1(n4582), .B0(n4195), .B1(n4587), .C0(n4189), .C1(n4598), .Y(n4179) );
XOR2X1TS U5777 ( .A(n4180), .B(n4193), .Y(mult_x_24_n1343) );
AOI222X1TS U5778 ( .A0(n4198), .A1(n4587), .B0(n4195), .B1(n4592), .C0(n4189), .C1(n4603), .Y(n4181) );
XOR2X1TS U5779 ( .A(n4182), .B(n4193), .Y(mult_x_24_n1344) );
AOI222X1TS U5780 ( .A0(n4198), .A1(n4592), .B0(n4195), .B1(n4597), .C0(n4189), .C1(n4609), .Y(n4183) );
XOR2X1TS U5781 ( .A(n4184), .B(n4193), .Y(mult_x_24_n1345) );
AOI222X1TS U5782 ( .A0(n4198), .A1(n4597), .B0(n4195), .B1(n4602), .C0(n4189), .C1(n4615), .Y(n4185) );
XOR2X1TS U5783 ( .A(n4186), .B(n4193), .Y(mult_x_24_n1346) );
AOI222X1TS U5784 ( .A0(n4198), .A1(n4602), .B0(n4195), .B1(n4608), .C0(n4189), .C1(n4607), .Y(n4187) );
XOR2X1TS U5785 ( .A(n4188), .B(n4193), .Y(mult_x_24_n1347) );
AOI222X1TS U5786 ( .A0(n4198), .A1(n4608), .B0(n4195), .B1(n4614), .C0(n4189), .C1(n4621), .Y(n4190) );
XOR2X1TS U5787 ( .A(n4191), .B(n4193), .Y(mult_x_24_n1348) );
AOI222X1TS U5788 ( .A0(n4212), .A1(n4614), .B0(n4211), .B1(n4524), .C0(n2918), .C1(n4626), .Y(n4192) );
XOR2X1TS U5789 ( .A(n4194), .B(n4193), .Y(mult_x_24_n1349) );
AOI222X1TS U5790 ( .A0(n4212), .A1(n4524), .B0(n4195), .B1(n4619), .C0(n2918), .C1(n4632), .Y(n4196) );
XOR2X1TS U5791 ( .A(n4197), .B(n6591), .Y(mult_x_24_n1350) );
AOI222X1TS U5792 ( .A0(n4198), .A1(n4619), .B0(n4211), .B1(n4625), .C0(n2918), .C1(n4639), .Y(n4199) );
XOR2X1TS U5793 ( .A(n4200), .B(n798), .Y(mult_x_24_n1351) );
AOI222X1TS U5794 ( .A0(n4212), .A1(n4625), .B0(n4211), .B1(n4631), .C0(n2918), .C1(n4647), .Y(n4201) );
XOR2X1TS U5795 ( .A(n4202), .B(n798), .Y(mult_x_24_n1352) );
AOI222X1TS U5796 ( .A0(n4212), .A1(n4631), .B0(n4211), .B1(n4638), .C0(n2918), .C1(n4637), .Y(n4203) );
XOR2X1TS U5797 ( .A(n4204), .B(n6591), .Y(mult_x_24_n1353) );
AOI222X1TS U5798 ( .A0(n4212), .A1(n4638), .B0(n4211), .B1(n4645), .C0(n2918), .C1(n4644), .Y(n4205) );
XOR2X1TS U5799 ( .A(n4206), .B(n6591), .Y(mult_x_24_n1354) );
AOI222X1TS U5800 ( .A0(n4212), .A1(n4645), .B0(n4211), .B1(n4541), .C0(n2918), .C1(n4536), .Y(n4207) );
XOR2X1TS U5801 ( .A(n4208), .B(n6591), .Y(mult_x_24_n1355) );
AOI222X1TS U5802 ( .A0(n4212), .A1(n4541), .B0(n4211), .B1(n4547), .C0(n2918), .C1(n4540), .Y(n4209) );
XOR2X1TS U5803 ( .A(n4210), .B(n6591), .Y(mult_x_24_n1356) );
AOI222X1TS U5804 ( .A0(n4212), .A1(n4547), .B0(n4211), .B1(n4546), .C0(n2918), .C1(n4545), .Y(n4213) );
XOR2X1TS U5805 ( .A(n4215), .B(n6591), .Y(mult_x_24_n1357) );
AOI21X1TS U5806 ( .A0(n4237), .A1(n4563), .B0(n4216), .Y(n4217) );
XOR2X1TS U5807 ( .A(n4218), .B(n6592), .Y(mult_x_24_n1366) );
AOI222X1TS U5808 ( .A0(n4247), .A1(n4558), .B0(n4244), .B1(n4557), .C0(n4237), .C1(n4568), .Y(n4219) );
XOR2X1TS U5809 ( .A(n4220), .B(n4242), .Y(mult_x_24_n1367) );
AOI222X1TS U5810 ( .A0(n4247), .A1(n4557), .B0(n4244), .B1(n4562), .C0(n4237), .C1(n4573), .Y(n4221) );
XOR2X1TS U5811 ( .A(n4222), .B(n4242), .Y(mult_x_24_n1368) );
AOI222X1TS U5812 ( .A0(n4247), .A1(n4562), .B0(n4244), .B1(n4567), .C0(n4237), .C1(n4578), .Y(n4223) );
XOR2X1TS U5813 ( .A(n4224), .B(n4242), .Y(mult_x_24_n1369) );
AOI222X1TS U5814 ( .A0(n4247), .A1(n4567), .B0(n4244), .B1(n4572), .C0(n4237), .C1(n4583), .Y(n4225) );
XOR2X1TS U5815 ( .A(n4226), .B(n4242), .Y(mult_x_24_n1370) );
AOI222X1TS U5816 ( .A0(n4247), .A1(n4582), .B0(n4244), .B1(n4587), .C0(n4237), .C1(n4598), .Y(n4227) );
XOR2X1TS U5817 ( .A(n4228), .B(n4242), .Y(mult_x_24_n1373) );
AOI222X1TS U5818 ( .A0(n4247), .A1(n4587), .B0(n4244), .B1(n4592), .C0(n4237), .C1(n4603), .Y(n4229) );
XOR2X1TS U5819 ( .A(n4230), .B(n4242), .Y(mult_x_24_n1374) );
AOI222X1TS U5820 ( .A0(n4247), .A1(n4592), .B0(n4244), .B1(n4597), .C0(n4237), .C1(n4609), .Y(n4231) );
XOR2X1TS U5821 ( .A(n4232), .B(n4242), .Y(mult_x_24_n1375) );
AOI222X1TS U5822 ( .A0(n4247), .A1(n4597), .B0(n4244), .B1(n4602), .C0(n4237), .C1(n4615), .Y(n4233) );
XOR2X1TS U5823 ( .A(n4234), .B(n4242), .Y(mult_x_24_n1376) );
AOI222X1TS U5824 ( .A0(n4247), .A1(n4602), .B0(n4244), .B1(n4608), .C0(n4237), .C1(n4607), .Y(n4235) );
XOR2X1TS U5825 ( .A(n4236), .B(n4242), .Y(mult_x_24_n1377) );
AOI222X1TS U5826 ( .A0(n4247), .A1(n4608), .B0(n4244), .B1(n4614), .C0(n4237), .C1(n4621), .Y(n4238) );
XOR2X1TS U5827 ( .A(n4239), .B(n4242), .Y(mult_x_24_n1378) );
AOI222X1TS U5828 ( .A0(n4267), .A1(n4614), .B0(n4266), .B1(n4524), .C0(n4240), .C1(n4626), .Y(n4241) );
XOR2X1TS U5829 ( .A(n4243), .B(n4242), .Y(mult_x_24_n1379) );
AOI222X1TS U5830 ( .A0(n4267), .A1(n4524), .B0(n4244), .B1(n4619), .C0(n4240), .C1(n4632), .Y(n4245) );
XOR2X1TS U5831 ( .A(n4246), .B(n770), .Y(mult_x_24_n1380) );
AOI222X1TS U5832 ( .A0(n4247), .A1(n4619), .B0(n4266), .B1(n4625), .C0(n4240), .C1(n4639), .Y(n4248) );
XOR2X1TS U5833 ( .A(n4249), .B(n770), .Y(mult_x_24_n1381) );
AOI222X1TS U5834 ( .A0(n4267), .A1(n4625), .B0(n4266), .B1(n4631), .C0(n4240), .C1(n4647), .Y(n4250) );
XOR2X1TS U5835 ( .A(n4251), .B(n770), .Y(mult_x_24_n1382) );
AOI222X1TS U5836 ( .A0(n4267), .A1(n4631), .B0(n4266), .B1(n4638), .C0(n4240), .C1(n4637), .Y(n4252) );
XOR2X1TS U5837 ( .A(n4253), .B(n770), .Y(mult_x_24_n1383) );
AOI222X1TS U5838 ( .A0(n4267), .A1(n4638), .B0(n4266), .B1(n4645), .C0(n4240), .C1(n4644), .Y(n4254) );
XOR2X1TS U5839 ( .A(n4255), .B(n770), .Y(mult_x_24_n1384) );
AOI222X1TS U5840 ( .A0(n4267), .A1(n4645), .B0(n4266), .B1(n4541), .C0(n4240), .C1(n4536), .Y(n4256) );
XOR2X1TS U5841 ( .A(n4257), .B(n770), .Y(mult_x_24_n1385) );
AOI222X1TS U5842 ( .A0(n4267), .A1(n4541), .B0(n4266), .B1(n4547), .C0(n4240), .C1(n4540), .Y(n4258) );
XOR2X1TS U5843 ( .A(n4259), .B(n770), .Y(mult_x_24_n1386) );
AOI222X1TS U5844 ( .A0(n4267), .A1(n4547), .B0(n4266), .B1(n4546), .C0(n4240), .C1(n4545), .Y(n4260) );
XOR2X1TS U5845 ( .A(n4261), .B(n770), .Y(mult_x_24_n1387) );
AOI222X1TS U5846 ( .A0(n4267), .A1(n4546), .B0(n4266), .B1(n4486), .C0(n4240), .C1(n4372), .Y(n4262) );
XOR2X1TS U5847 ( .A(n4263), .B(n770), .Y(mult_x_24_n1388) );
AOI222X1TS U5848 ( .A0(n4267), .A1(n4486), .B0(n4266), .B1(n4493), .C0(n4240), .C1(n4485), .Y(n4264) );
XOR2X1TS U5849 ( .A(n4265), .B(n770), .Y(mult_x_24_n1389) );
AOI222X1TS U5850 ( .A0(n4267), .A1(n4493), .B0(n4266), .B1(n4491), .C0(n4240), .C1(n4490), .Y(n4268) );
XOR2X1TS U5851 ( .A(n4270), .B(n770), .Y(mult_x_24_n1390) );
NAND2X1TS U5852 ( .A(n4298), .B(n4383), .Y(n4271) );
XOR2X1TS U5853 ( .A(n4272), .B(n6593), .Y(mult_x_24_n1395) );
AOI21X1TS U5854 ( .A0(n4298), .A1(n4563), .B0(n4273), .Y(n4274) );
XOR2X1TS U5855 ( .A(n4275), .B(n6593), .Y(mult_x_24_n1396) );
AOI222X1TS U5856 ( .A0(n4307), .A1(n4558), .B0(n4304), .B1(n4557), .C0(n4298), .C1(n4568), .Y(n4276) );
XOR2X1TS U5857 ( .A(n4277), .B(n4302), .Y(mult_x_24_n1397) );
AOI222X1TS U5858 ( .A0(n4307), .A1(n4557), .B0(n4304), .B1(n4562), .C0(n4298), .C1(n4573), .Y(n4278) );
XOR2X1TS U5859 ( .A(n4279), .B(n4302), .Y(mult_x_24_n1398) );
AOI222X1TS U5860 ( .A0(n4307), .A1(n4562), .B0(n4304), .B1(n4567), .C0(n4298), .C1(n4578), .Y(n4280) );
XOR2X1TS U5861 ( .A(n4281), .B(n4302), .Y(mult_x_24_n1399) );
AOI222X1TS U5862 ( .A0(n4307), .A1(n4567), .B0(n4304), .B1(n4572), .C0(n4298), .C1(n4583), .Y(n4282) );
XOR2X1TS U5863 ( .A(n4283), .B(n4302), .Y(mult_x_24_n1400) );
AOI222X1TS U5864 ( .A0(n4307), .A1(n4572), .B0(n4304), .B1(n4577), .C0(n4298), .C1(n4588), .Y(n4284) );
XOR2X1TS U5865 ( .A(n4285), .B(n4302), .Y(mult_x_24_n1401) );
AOI222X1TS U5866 ( .A0(n4307), .A1(n4577), .B0(n4304), .B1(n4582), .C0(n4298), .C1(n4593), .Y(n4286) );
XOR2X1TS U5867 ( .A(n4287), .B(n4302), .Y(mult_x_24_n1402) );
AOI222X1TS U5868 ( .A0(n4307), .A1(n4582), .B0(n4304), .B1(n4587), .C0(n4298), .C1(n4598), .Y(n4288) );
XOR2X1TS U5869 ( .A(n4289), .B(n4302), .Y(mult_x_24_n1403) );
AOI222X1TS U5870 ( .A0(n4307), .A1(n4587), .B0(n4304), .B1(n4592), .C0(n4298), .C1(n4603), .Y(n4290) );
XOR2X1TS U5871 ( .A(n4291), .B(n4302), .Y(mult_x_24_n1404) );
AOI222X1TS U5872 ( .A0(n4307), .A1(n4592), .B0(n4304), .B1(n4597), .C0(n4298), .C1(n4609), .Y(n4292) );
XOR2X1TS U5873 ( .A(n4293), .B(n4302), .Y(mult_x_24_n1405) );
AOI222X1TS U5874 ( .A0(n4307), .A1(n4597), .B0(n4304), .B1(n4602), .C0(n4298), .C1(n4615), .Y(n4294) );
XOR2X1TS U5875 ( .A(n4295), .B(n4302), .Y(mult_x_24_n1406) );
AOI222X1TS U5876 ( .A0(n4307), .A1(n4602), .B0(n4304), .B1(n4608), .C0(n4298), .C1(n4607), .Y(n4296) );
XOR2X1TS U5877 ( .A(n4297), .B(n4302), .Y(mult_x_24_n1407) );
AOI222X1TS U5878 ( .A0(n4307), .A1(n4608), .B0(n4304), .B1(n4614), .C0(n4298), .C1(n4621), .Y(n4299) );
XOR2X1TS U5879 ( .A(n4300), .B(n4302), .Y(mult_x_24_n1408) );
AOI222X1TS U5880 ( .A0(n4321), .A1(n4614), .B0(n4320), .B1(n4524), .C0(n4119), .C1(n4626), .Y(n4301) );
XOR2X1TS U5881 ( .A(n4303), .B(n4302), .Y(mult_x_24_n1409) );
AOI222X1TS U5882 ( .A0(n4321), .A1(n4524), .B0(n4304), .B1(n4619), .C0(n4119), .C1(n4632), .Y(n4305) );
XOR2X1TS U5883 ( .A(n4306), .B(n780), .Y(mult_x_24_n1410) );
AOI222X1TS U5884 ( .A0(n4307), .A1(n4619), .B0(n4320), .B1(n4625), .C0(n4119), .C1(n4639), .Y(n4308) );
XOR2X1TS U5885 ( .A(n4309), .B(n780), .Y(mult_x_24_n1411) );
AOI222X1TS U5886 ( .A0(n4321), .A1(n4625), .B0(n4320), .B1(n4631), .C0(n4119), .C1(n4647), .Y(n4310) );
XOR2X1TS U5887 ( .A(n4311), .B(n780), .Y(mult_x_24_n1412) );
AOI222X1TS U5888 ( .A0(n4321), .A1(n4631), .B0(n4320), .B1(n4638), .C0(n4119), .C1(n4637), .Y(n4312) );
XOR2X1TS U5889 ( .A(n4313), .B(n780), .Y(mult_x_24_n1413) );
AOI222X1TS U5890 ( .A0(n4321), .A1(n4638), .B0(n4320), .B1(n4645), .C0(n4119), .C1(n4644), .Y(n4314) );
XOR2X1TS U5891 ( .A(n4315), .B(n780), .Y(mult_x_24_n1414) );
AOI222X1TS U5892 ( .A0(n4321), .A1(n4645), .B0(n4320), .B1(n4541), .C0(n4119), .C1(n4536), .Y(n4316) );
XOR2X1TS U5893 ( .A(n4317), .B(n780), .Y(mult_x_24_n1415) );
AOI222X1TS U5894 ( .A0(n4321), .A1(n4541), .B0(n4320), .B1(n4547), .C0(n4119), .C1(n4540), .Y(n4318) );
XOR2X1TS U5895 ( .A(n4319), .B(n780), .Y(mult_x_24_n1416) );
AOI222X1TS U5896 ( .A0(n4321), .A1(n4547), .B0(n4320), .B1(n4546), .C0(n4119), .C1(n4545), .Y(n4322) );
XOR2X1TS U5897 ( .A(n4324), .B(n780), .Y(mult_x_24_n1417) );
AOI21X1TS U5898 ( .A0(n4350), .A1(n4563), .B0(n4325), .Y(n4326) );
XOR2X1TS U5899 ( .A(n4327), .B(n800), .Y(mult_x_24_n1426) );
AOI222X1TS U5900 ( .A0(n4357), .A1(n4558), .B0(n4354), .B1(n6583), .C0(n4350), .C1(n4568), .Y(n4328) );
XOR2X1TS U5901 ( .A(n4329), .B(n4352), .Y(mult_x_24_n1427) );
AOI222X1TS U5902 ( .A0(n4357), .A1(n4557), .B0(n4354), .B1(n788), .C0(n4350),
.C1(n4573), .Y(n4330) );
XOR2X1TS U5903 ( .A(n4331), .B(n4352), .Y(mult_x_24_n1428) );
AOI222X1TS U5904 ( .A0(n4357), .A1(n4562), .B0(n4354), .B1(Op_MX[23]), .C0(
n4350), .C1(n4578), .Y(n4332) );
XOR2X1TS U5905 ( .A(n4333), .B(n4352), .Y(mult_x_24_n1429) );
AOI222X1TS U5906 ( .A0(n4357), .A1(n4567), .B0(n4354), .B1(n733), .C0(n4350),
.C1(n4583), .Y(n4334) );
XOR2X1TS U5907 ( .A(n4335), .B(n4352), .Y(mult_x_24_n1430) );
AOI222X1TS U5908 ( .A0(n4357), .A1(n4572), .B0(n4354), .B1(Op_MX[21]), .C0(
n4350), .C1(n4588), .Y(n4336) );
XOR2X1TS U5909 ( .A(n4337), .B(n800), .Y(mult_x_24_n1431) );
AOI222X1TS U5910 ( .A0(n4357), .A1(n4577), .B0(n4354), .B1(Op_MX[20]), .C0(
n4350), .C1(n4593), .Y(n4338) );
XOR2X1TS U5911 ( .A(n4339), .B(n4352), .Y(mult_x_24_n1432) );
AOI222X1TS U5912 ( .A0(n4357), .A1(n4582), .B0(n4354), .B1(Op_MX[19]), .C0(
n4350), .C1(n4598), .Y(n4340) );
XOR2X1TS U5913 ( .A(n4341), .B(n4352), .Y(mult_x_24_n1433) );
AOI222X1TS U5914 ( .A0(n4357), .A1(n4587), .B0(n4354), .B1(n737), .C0(n4350),
.C1(n4603), .Y(n4342) );
XOR2X1TS U5915 ( .A(n4343), .B(n4352), .Y(mult_x_24_n1434) );
AOI222X1TS U5916 ( .A0(n4357), .A1(n4592), .B0(n4354), .B1(n734), .C0(n4350),
.C1(n4609), .Y(n4344) );
XOR2X1TS U5917 ( .A(n4345), .B(n4352), .Y(mult_x_24_n1435) );
AOI222X1TS U5918 ( .A0(n4357), .A1(n4597), .B0(n4354), .B1(n730), .C0(n4350),
.C1(n4615), .Y(n4346) );
XOR2X1TS U5919 ( .A(n4347), .B(n4352), .Y(mult_x_24_n1436) );
AOI222X1TS U5920 ( .A0(n4357), .A1(n4602), .B0(n4354), .B1(Op_MX[15]), .C0(
n4350), .C1(n4607), .Y(n4348) );
XOR2X1TS U5921 ( .A(n4349), .B(n4352), .Y(mult_x_24_n1437) );
AOI222X1TS U5922 ( .A0(n4357), .A1(n4608), .B0(n4354), .B1(Op_MX[14]), .C0(
n4350), .C1(n4621), .Y(n4351) );
XOR2X1TS U5923 ( .A(n4353), .B(n4352), .Y(mult_x_24_n1438) );
AOI222X1TS U5924 ( .A0(n4379), .A1(n4524), .B0(n4354), .B1(Op_MX[12]), .C0(
n2930), .C1(n4632), .Y(n4355) );
XOR2X1TS U5925 ( .A(n4356), .B(n800), .Y(mult_x_24_n1440) );
AOI222X1TS U5926 ( .A0(n4357), .A1(n4619), .B0(n4378), .B1(n732), .C0(n2930),
.C1(n4639), .Y(n4358) );
XOR2X1TS U5927 ( .A(n4359), .B(n800), .Y(mult_x_24_n1441) );
AOI222X1TS U5928 ( .A0(n4379), .A1(n4625), .B0(n4378), .B1(n789), .C0(n2930),
.C1(n4647), .Y(n4360) );
XOR2X1TS U5929 ( .A(n4361), .B(n800), .Y(mult_x_24_n1442) );
AOI222X1TS U5930 ( .A0(n4379), .A1(n4631), .B0(n4378), .B1(Op_MX[9]), .C0(
n2930), .C1(n4637), .Y(n4362) );
XOR2X1TS U5931 ( .A(n4363), .B(n800), .Y(mult_x_24_n1443) );
AOI222X1TS U5932 ( .A0(n4379), .A1(n4638), .B0(n4378), .B1(Op_MX[8]), .C0(
n2930), .C1(n4644), .Y(n4364) );
XOR2X1TS U5933 ( .A(n4365), .B(n800), .Y(mult_x_24_n1444) );
AOI222X1TS U5934 ( .A0(n4379), .A1(n4645), .B0(n4378), .B1(Op_MX[7]), .C0(
n2930), .C1(n4536), .Y(n4366) );
XOR2X1TS U5935 ( .A(n4367), .B(n800), .Y(mult_x_24_n1445) );
AOI222X1TS U5936 ( .A0(n4379), .A1(n4541), .B0(n4378), .B1(n795), .C0(n2930),
.C1(n4540), .Y(n4368) );
XOR2X1TS U5937 ( .A(n4369), .B(n800), .Y(mult_x_24_n1446) );
AOI222X1TS U5938 ( .A0(n4379), .A1(n4547), .B0(n4378), .B1(Op_MX[5]), .C0(
n2930), .C1(n4545), .Y(n4370) );
XOR2X1TS U5939 ( .A(n4371), .B(n800), .Y(mult_x_24_n1447) );
AOI222X1TS U5940 ( .A0(n4379), .A1(n4546), .B0(n4378), .B1(Op_MX[4]), .C0(
n2930), .C1(n4372), .Y(n4373) );
XOR2X1TS U5941 ( .A(n4375), .B(n800), .Y(mult_x_24_n1448) );
AOI222X1TS U5942 ( .A0(n4379), .A1(n4486), .B0(n4378), .B1(Op_MX[3]), .C0(
n2930), .C1(n4485), .Y(n4376) );
XOR2X1TS U5943 ( .A(n4377), .B(n800), .Y(mult_x_24_n1449) );
AOI222X1TS U5944 ( .A0(n4379), .A1(n4493), .B0(n4378), .B1(Op_MX[2]), .C0(
n2930), .C1(n4490), .Y(n4380) );
XOR2X1TS U5945 ( .A(n4382), .B(n800), .Y(mult_x_24_n1450) );
NAND2X1TS U5946 ( .A(n4408), .B(n4383), .Y(n4384) );
XOR2X1TS U5947 ( .A(n4386), .B(n6595), .Y(mult_x_24_n1455) );
AOI21X1TS U5948 ( .A0(n4408), .A1(n4563), .B0(n4387), .Y(n4388) );
XOR2X1TS U5949 ( .A(n4389), .B(n6595), .Y(mult_x_24_n1456) );
AOI222X1TS U5950 ( .A0(n4418), .A1(n4558), .B0(n4415), .B1(n4557), .C0(n4408), .C1(n4568), .Y(n4390) );
XOR2X1TS U5951 ( .A(n4391), .B(n4413), .Y(mult_x_24_n1457) );
AOI222X1TS U5952 ( .A0(n4418), .A1(n4557), .B0(n4415), .B1(n4562), .C0(n4408), .C1(n4573), .Y(n4392) );
XOR2X1TS U5953 ( .A(n4393), .B(n4413), .Y(mult_x_24_n1458) );
AOI222X1TS U5954 ( .A0(n4418), .A1(n4567), .B0(n4415), .B1(n4572), .C0(n4408), .C1(n4583), .Y(n4394) );
XOR2X1TS U5955 ( .A(n4395), .B(n4413), .Y(mult_x_24_n1460) );
AOI222X1TS U5956 ( .A0(n4418), .A1(n4572), .B0(n4415), .B1(n4577), .C0(n4408), .C1(n4588), .Y(n4396) );
XOR2X1TS U5957 ( .A(n4397), .B(n4413), .Y(mult_x_24_n1461) );
AOI222X1TS U5958 ( .A0(n4418), .A1(n4582), .B0(n4415), .B1(n4587), .C0(n4408), .C1(n4598), .Y(n4398) );
XOR2X1TS U5959 ( .A(n4399), .B(n4413), .Y(mult_x_24_n1463) );
AOI222X1TS U5960 ( .A0(n4418), .A1(n4587), .B0(n4415), .B1(n4592), .C0(n4408), .C1(n4603), .Y(n4400) );
XOR2X1TS U5961 ( .A(n4401), .B(n4413), .Y(mult_x_24_n1464) );
AOI222X1TS U5962 ( .A0(n4418), .A1(n4592), .B0(n4415), .B1(n4597), .C0(n4408), .C1(n4609), .Y(n4402) );
XOR2X1TS U5963 ( .A(n4403), .B(n4413), .Y(mult_x_24_n1465) );
AOI222X1TS U5964 ( .A0(n4418), .A1(n4597), .B0(n4415), .B1(n4602), .C0(n4408), .C1(n4615), .Y(n4404) );
XOR2X1TS U5965 ( .A(n4405), .B(n4413), .Y(mult_x_24_n1466) );
AOI222X1TS U5966 ( .A0(n4418), .A1(n4602), .B0(n4415), .B1(n4608), .C0(n4408), .C1(n4607), .Y(n4406) );
XOR2X1TS U5967 ( .A(n4407), .B(n4413), .Y(mult_x_24_n1467) );
AOI222X1TS U5968 ( .A0(n4418), .A1(n4608), .B0(n4415), .B1(n4614), .C0(n4408), .C1(n4621), .Y(n4409) );
XOR2X1TS U5969 ( .A(n4410), .B(n4413), .Y(mult_x_24_n1468) );
AOI222X1TS U5970 ( .A0(n4433), .A1(n4614), .B0(n4432), .B1(n4524), .C0(n2939), .C1(n4626), .Y(n4411) );
XOR2X1TS U5971 ( .A(n4414), .B(n4413), .Y(mult_x_24_n1469) );
AOI222X1TS U5972 ( .A0(n4433), .A1(n4524), .B0(n4415), .B1(n4619), .C0(n2939), .C1(n4632), .Y(n4416) );
XOR2X1TS U5973 ( .A(n4417), .B(n777), .Y(mult_x_24_n1470) );
AOI222X1TS U5974 ( .A0(n4418), .A1(n4619), .B0(n4432), .B1(n4625), .C0(n2939), .C1(n4639), .Y(n4419) );
XOR2X1TS U5975 ( .A(n4420), .B(n777), .Y(mult_x_24_n1471) );
AOI222X1TS U5976 ( .A0(n4433), .A1(n4625), .B0(n4432), .B1(n4631), .C0(n2939), .C1(n4647), .Y(n4421) );
XOR2X1TS U5977 ( .A(n4422), .B(n777), .Y(mult_x_24_n1472) );
AOI222X1TS U5978 ( .A0(n4433), .A1(n4631), .B0(n4432), .B1(n4638), .C0(n2939), .C1(n4637), .Y(n4423) );
XOR2X1TS U5979 ( .A(n4425), .B(n777), .Y(mult_x_24_n1473) );
AOI222X1TS U5980 ( .A0(n4433), .A1(n4638), .B0(n4432), .B1(n4645), .C0(n2939), .C1(n4644), .Y(n4426) );
XOR2X1TS U5981 ( .A(n4427), .B(n777), .Y(mult_x_24_n1474) );
AOI222X1TS U5982 ( .A0(n4433), .A1(n4645), .B0(n4432), .B1(n4541), .C0(n2939), .C1(n4536), .Y(n4428) );
XOR2X1TS U5983 ( .A(n4429), .B(n777), .Y(mult_x_24_n1475) );
AOI222X1TS U5984 ( .A0(n4433), .A1(n4541), .B0(n4432), .B1(n4547), .C0(n2939), .C1(n4540), .Y(n4430) );
XOR2X1TS U5985 ( .A(n4431), .B(n777), .Y(mult_x_24_n1476) );
AOI222X1TS U5986 ( .A0(n4433), .A1(n4547), .B0(n4432), .B1(n4546), .C0(n2939), .C1(n4545), .Y(n4434) );
XOR2X1TS U5987 ( .A(n4436), .B(n777), .Y(mult_x_24_n1477) );
AOI21X1TS U5988 ( .A0(n4462), .A1(n4563), .B0(n4437), .Y(n4438) );
XOR2X1TS U5989 ( .A(n4439), .B(n6596), .Y(mult_x_24_n1486) );
AOI222X1TS U5990 ( .A0(n4469), .A1(n4558), .B0(n4466), .B1(n4557), .C0(n4462), .C1(n4568), .Y(n4440) );
XOR2X1TS U5991 ( .A(n4441), .B(n4464), .Y(mult_x_24_n1487) );
AOI222X1TS U5992 ( .A0(n4469), .A1(n4557), .B0(n4466), .B1(n4562), .C0(n4462), .C1(n4573), .Y(n4442) );
XOR2X1TS U5993 ( .A(n4443), .B(n4464), .Y(mult_x_24_n1488) );
AOI222X1TS U5994 ( .A0(n4469), .A1(n4562), .B0(n4466), .B1(n4567), .C0(n4462), .C1(n4578), .Y(n4444) );
XOR2X1TS U5995 ( .A(n4445), .B(n4464), .Y(mult_x_24_n1489) );
AOI222X1TS U5996 ( .A0(n4469), .A1(n4567), .B0(n4466), .B1(n4572), .C0(n4462), .C1(n4583), .Y(n4446) );
XOR2X1TS U5997 ( .A(n4447), .B(n4464), .Y(mult_x_24_n1490) );
AOI222X1TS U5998 ( .A0(n4469), .A1(n4572), .B0(n4466), .B1(n4577), .C0(n4462), .C1(n4588), .Y(n4448) );
XOR2X1TS U5999 ( .A(n4449), .B(n4464), .Y(mult_x_24_n1491) );
AOI222X1TS U6000 ( .A0(n4469), .A1(n4577), .B0(n4466), .B1(n4582), .C0(n4462), .C1(n4593), .Y(n4450) );
XOR2X1TS U6001 ( .A(n4451), .B(n4464), .Y(mult_x_24_n1492) );
AOI222X1TS U6002 ( .A0(n4469), .A1(n4582), .B0(n4466), .B1(n4587), .C0(n4462), .C1(n4598), .Y(n4452) );
XOR2X1TS U6003 ( .A(n4453), .B(n4464), .Y(mult_x_24_n1493) );
AOI222X1TS U6004 ( .A0(n4469), .A1(n4587), .B0(n4466), .B1(n4592), .C0(n4462), .C1(n4603), .Y(n4454) );
XOR2X1TS U6005 ( .A(n4455), .B(n4464), .Y(mult_x_24_n1494) );
AOI222X1TS U6006 ( .A0(n4469), .A1(n4592), .B0(n4466), .B1(n4597), .C0(n4462), .C1(n4609), .Y(n4456) );
XOR2X1TS U6007 ( .A(n4457), .B(n4464), .Y(mult_x_24_n1495) );
AOI222X1TS U6008 ( .A0(n4469), .A1(n4597), .B0(n4466), .B1(n4602), .C0(n4462), .C1(n4615), .Y(n4458) );
XOR2X1TS U6009 ( .A(n4459), .B(n4464), .Y(mult_x_24_n1496) );
AOI222X1TS U6010 ( .A0(n4469), .A1(n4602), .B0(n4466), .B1(n4608), .C0(n4462), .C1(n4607), .Y(n4460) );
XOR2X1TS U6011 ( .A(n4461), .B(n4464), .Y(mult_x_24_n1497) );
AOI222X1TS U6012 ( .A0(n4469), .A1(n4608), .B0(n4466), .B1(n4614), .C0(n4462), .C1(n4621), .Y(n4463) );
XOR2X1TS U6013 ( .A(n4465), .B(n4464), .Y(mult_x_24_n1498) );
AOI222X1TS U6014 ( .A0(n4494), .A1(n4524), .B0(n4466), .B1(n4619), .C0(n2873), .C1(n4632), .Y(n4467) );
XOR2X1TS U6015 ( .A(n4468), .B(n783), .Y(mult_x_24_n1500) );
AOI222X1TS U6016 ( .A0(n4469), .A1(n4619), .B0(n4492), .B1(n4625), .C0(n2873), .C1(n4639), .Y(n4470) );
XOR2X1TS U6017 ( .A(n4471), .B(n783), .Y(mult_x_24_n1501) );
AOI222X1TS U6018 ( .A0(n4494), .A1(n4625), .B0(n4492), .B1(n4631), .C0(n2873), .C1(n4647), .Y(n4472) );
XOR2X1TS U6019 ( .A(n4474), .B(n783), .Y(mult_x_24_n1502) );
AOI222X1TS U6020 ( .A0(n4494), .A1(n4631), .B0(n4492), .B1(n4638), .C0(n2873), .C1(n4637), .Y(n4475) );
XOR2X1TS U6021 ( .A(n4476), .B(n783), .Y(mult_x_24_n1503) );
AOI222X1TS U6022 ( .A0(n4494), .A1(n4638), .B0(n4492), .B1(n4645), .C0(n2873), .C1(n4644), .Y(n4477) );
XOR2X1TS U6023 ( .A(n4478), .B(n783), .Y(mult_x_24_n1504) );
AOI222X1TS U6024 ( .A0(n4494), .A1(n4645), .B0(n4492), .B1(n4541), .C0(n2873), .C1(n4536), .Y(n4479) );
XOR2X1TS U6025 ( .A(n4480), .B(n783), .Y(mult_x_24_n1505) );
AOI222X1TS U6026 ( .A0(n4494), .A1(n4541), .B0(n4492), .B1(n4547), .C0(n2873), .C1(n4540), .Y(n4481) );
XOR2X1TS U6027 ( .A(n4482), .B(n783), .Y(mult_x_24_n1506) );
AOI222X1TS U6028 ( .A0(n4494), .A1(n4547), .B0(n4492), .B1(n4546), .C0(n2873), .C1(n4545), .Y(n4483) );
XOR2X1TS U6029 ( .A(n4484), .B(n783), .Y(mult_x_24_n1507) );
AOI222X1TS U6030 ( .A0(n4494), .A1(n4486), .B0(n4492), .B1(n4493), .C0(n2873), .C1(n4485), .Y(n4487) );
XOR2X1TS U6031 ( .A(n4489), .B(n783), .Y(mult_x_24_n1509) );
AOI222X1TS U6032 ( .A0(n4494), .A1(n4493), .B0(n4492), .B1(n4491), .C0(n2873), .C1(n4490), .Y(n4495) );
XOR2X1TS U6033 ( .A(n4498), .B(n783), .Y(mult_x_24_n1510) );
AOI21X1TS U6034 ( .A0(n4520), .A1(n4563), .B0(n4499), .Y(n4500) );
XOR2X1TS U6035 ( .A(n4501), .B(n801), .Y(mult_x_24_n1516) );
AOI222X1TS U6036 ( .A0(n4527), .A1(n4558), .B0(n772), .B1(n4557), .C0(n4520),
.C1(n4568), .Y(n4502) );
XOR2X1TS U6037 ( .A(n4503), .B(n4522), .Y(mult_x_24_n1517) );
AOI222X1TS U6038 ( .A0(n4527), .A1(n4557), .B0(n729), .B1(n4562), .C0(n4520),
.C1(n4573), .Y(n4504) );
XOR2X1TS U6039 ( .A(n4505), .B(n4522), .Y(mult_x_24_n1518) );
AOI222X1TS U6040 ( .A0(n4527), .A1(n4562), .B0(n772), .B1(n4567), .C0(n4520),
.C1(n4578), .Y(n4506) );
XOR2X1TS U6041 ( .A(n4507), .B(n4522), .Y(mult_x_24_n1519) );
AOI222X1TS U6042 ( .A0(n4527), .A1(n4567), .B0(n729), .B1(n4572), .C0(n4520),
.C1(n4583), .Y(n4508) );
XOR2X1TS U6043 ( .A(n4509), .B(n4522), .Y(mult_x_24_n1520) );
AOI222X1TS U6044 ( .A0(n4527), .A1(n4572), .B0(n772), .B1(n4577), .C0(n4520),
.C1(n4588), .Y(n4510) );
XOR2X1TS U6045 ( .A(n4511), .B(n4522), .Y(mult_x_24_n1521) );
AOI222X1TS U6046 ( .A0(n4527), .A1(n4577), .B0(n729), .B1(n4582), .C0(n4520),
.C1(n4593), .Y(n4512) );
XOR2X1TS U6047 ( .A(n4513), .B(n4522), .Y(mult_x_24_n1522) );
AOI222X1TS U6048 ( .A0(n4527), .A1(n4582), .B0(n772), .B1(n4587), .C0(n4520),
.C1(n4598), .Y(n4514) );
XOR2X1TS U6049 ( .A(n4515), .B(n4522), .Y(mult_x_24_n1523) );
AOI222X1TS U6050 ( .A0(n4527), .A1(n4587), .B0(n729), .B1(n4592), .C0(n4520),
.C1(n4603), .Y(n4516) );
XOR2X1TS U6051 ( .A(n4517), .B(n4522), .Y(mult_x_24_n1524) );
AOI222X1TS U6052 ( .A0(n4527), .A1(n4592), .B0(n729), .B1(n4597), .C0(n4520),
.C1(n4609), .Y(n4518) );
OAI21X1TS U6053 ( .A0(n4600), .A1(n2345), .B0(n4518), .Y(n4519) );
XOR2X1TS U6054 ( .A(n4519), .B(n4522), .Y(mult_x_24_n1525) );
AOI222X1TS U6055 ( .A0(n4527), .A1(n4608), .B0(n729), .B1(n4614), .C0(n4520),
.C1(n4621), .Y(n4521) );
XOR2X1TS U6056 ( .A(n4523), .B(n4522), .Y(mult_x_24_n1528) );
AOI222X1TS U6057 ( .A0(n4548), .A1(n4524), .B0(n729), .B1(n4619), .C0(n2348),
.C1(n4632), .Y(n4525) );
XOR2X1TS U6058 ( .A(n4526), .B(n804), .Y(mult_x_24_n1530) );
AOI222X1TS U6059 ( .A0(n4527), .A1(n4619), .B0(n772), .B1(n4625), .C0(n2348),
.C1(n4639), .Y(n4528) );
XOR2X1TS U6060 ( .A(n4529), .B(n803), .Y(mult_x_24_n1531) );
AOI222X1TS U6061 ( .A0(n4548), .A1(n4625), .B0(n729), .B1(n4631), .C0(n2348),
.C1(n4647), .Y(n4530) );
XOR2X1TS U6062 ( .A(n4531), .B(n804), .Y(mult_x_24_n1532) );
AOI222X1TS U6063 ( .A0(n4548), .A1(n4631), .B0(n772), .B1(n4638), .C0(n2348),
.C1(n4637), .Y(n4532) );
XOR2X1TS U6064 ( .A(n4533), .B(n802), .Y(mult_x_24_n1533) );
AOI222X1TS U6065 ( .A0(n4548), .A1(n4638), .B0(n729), .B1(n4645), .C0(n2348),
.C1(n4644), .Y(n4534) );
XOR2X1TS U6066 ( .A(n4535), .B(n802), .Y(mult_x_24_n1534) );
AOI222X1TS U6067 ( .A0(n4548), .A1(n4645), .B0(n729), .B1(n4541), .C0(n2348),
.C1(n4536), .Y(n4537) );
XOR2X1TS U6068 ( .A(n4539), .B(n804), .Y(mult_x_24_n1535) );
AOI222X1TS U6069 ( .A0(n4548), .A1(n4541), .B0(n772), .B1(n4547), .C0(n2348),
.C1(n4540), .Y(n4542) );
XOR2X1TS U6070 ( .A(n4544), .B(n803), .Y(mult_x_24_n1536) );
AOI222X1TS U6071 ( .A0(n4548), .A1(n4547), .B0(n729), .B1(n4546), .C0(n2348),
.C1(n4545), .Y(n4549) );
XOR2X1TS U6072 ( .A(n4552), .B(n804), .Y(mult_x_24_n1537) );
AOI21X1TS U6073 ( .A0(n4613), .A1(n4563), .B0(n4553), .Y(n4554) );
XOR2X1TS U6074 ( .A(n4556), .B(n4635), .Y(mult_x_24_n1546) );
AOI222X1TS U6075 ( .A0(n4627), .A1(n4558), .B0(n4620), .B1(n4557), .C0(n4613), .C1(n4568), .Y(n4559) );
XOR2X1TS U6076 ( .A(n4561), .B(n4635), .Y(mult_x_24_n1547) );
AOI222X1TS U6077 ( .A0(n4627), .A1(n4563), .B0(n4620), .B1(n4562), .C0(n4613), .C1(n4573), .Y(n4564) );
XOR2X1TS U6078 ( .A(n4566), .B(n4635), .Y(mult_x_24_n1548) );
AOI222X1TS U6079 ( .A0(n4627), .A1(n4568), .B0(n4620), .B1(n4567), .C0(n4613), .C1(n4578), .Y(n4569) );
XOR2X1TS U6080 ( .A(n4571), .B(n4635), .Y(mult_x_24_n1549) );
AOI222X1TS U6081 ( .A0(n4627), .A1(n4573), .B0(n4620), .B1(n4572), .C0(n4613), .C1(n4583), .Y(n4574) );
XOR2X1TS U6082 ( .A(n4576), .B(n4635), .Y(mult_x_24_n1550) );
AOI222X1TS U6083 ( .A0(n4627), .A1(n4578), .B0(n4620), .B1(n4577), .C0(n4613), .C1(n4588), .Y(n4579) );
XOR2X1TS U6084 ( .A(n4581), .B(n4635), .Y(mult_x_24_n1551) );
AOI222X1TS U6085 ( .A0(n4627), .A1(n4583), .B0(n4620), .B1(n4582), .C0(n4613), .C1(n4593), .Y(n4584) );
XOR2X1TS U6086 ( .A(n4586), .B(n6598), .Y(mult_x_24_n1552) );
AOI222X1TS U6087 ( .A0(n4627), .A1(n4588), .B0(n4620), .B1(n4587), .C0(n4613), .C1(n4598), .Y(n4589) );
XOR2X1TS U6088 ( .A(n4591), .B(n6598), .Y(mult_x_24_n1553) );
AOI222X1TS U6089 ( .A0(n4627), .A1(n4593), .B0(n4620), .B1(n4592), .C0(n4613), .C1(n4603), .Y(n4594) );
XOR2X1TS U6090 ( .A(n4596), .B(n6598), .Y(mult_x_24_n1554) );
AOI222X1TS U6091 ( .A0(n4627), .A1(n4598), .B0(n4620), .B1(n4597), .C0(n4613), .C1(n4609), .Y(n4599) );
XOR2X1TS U6092 ( .A(n4601), .B(n6598), .Y(mult_x_24_n1555) );
AOI222X1TS U6093 ( .A0(n4627), .A1(n4603), .B0(n4620), .B1(n4602), .C0(n4613), .C1(n4615), .Y(n4604) );
XOR2X1TS U6094 ( .A(n4606), .B(n6598), .Y(mult_x_24_n1556) );
AOI222X1TS U6095 ( .A0(n4627), .A1(n4609), .B0(n4620), .B1(n4608), .C0(n4613), .C1(n4607), .Y(n4610) );
XOR2X1TS U6096 ( .A(n4612), .B(n6598), .Y(mult_x_24_n1557) );
AOI222X1TS U6097 ( .A0(n4627), .A1(n4615), .B0(n4620), .B1(n4614), .C0(n4613), .C1(n4621), .Y(n4616) );
XOR2X1TS U6098 ( .A(n4618), .B(n6598), .Y(mult_x_24_n1558) );
AOI222X1TS U6099 ( .A0(n4648), .A1(n4621), .B0(n4620), .B1(n4619), .C0(n2360), .C1(n4632), .Y(n4622) );
XOR2X1TS U6100 ( .A(n4624), .B(n6598), .Y(mult_x_24_n1560) );
AOI222X1TS U6101 ( .A0(n4627), .A1(n4626), .B0(n4646), .B1(n4625), .C0(n2360), .C1(n4639), .Y(n4628) );
XOR2X1TS U6102 ( .A(n4630), .B(n4635), .Y(mult_x_24_n1561) );
AOI222X1TS U6103 ( .A0(n4648), .A1(n4632), .B0(n4646), .B1(n4631), .C0(n2360), .C1(n4647), .Y(n4633) );
XOR2X1TS U6104 ( .A(n4636), .B(n4635), .Y(mult_x_24_n1562) );
AOI222X1TS U6105 ( .A0(n4648), .A1(n4639), .B0(n4646), .B1(n4638), .C0(n2360), .C1(n4637), .Y(n4640) );
XOR2X1TS U6106 ( .A(n4643), .B(n6598), .Y(mult_x_24_n1563) );
AOI222X1TS U6107 ( .A0(n4648), .A1(n4647), .B0(n4646), .B1(n4645), .C0(n2360), .C1(n4644), .Y(n4649) );
XOR2X1TS U6108 ( .A(n4651), .B(Op_MY[2]), .Y(mult_x_24_n1564) );
AOI21X1TS U6109 ( .A0(n4659), .A1(n4658), .B0(n4657), .Y(n4660) );
NOR2X2TS U6110 ( .A(DP_OP_169J43_123_4229_n845), .B(
DP_OP_169J43_123_4229_n860), .Y(n4791) );
NOR2X2TS U6111 ( .A(DP_OP_169J43_123_4229_n831), .B(
DP_OP_169J43_123_4229_n844), .Y(n4784) );
NOR2X2TS U6112 ( .A(DP_OP_169J43_123_4229_n817), .B(
DP_OP_169J43_123_4229_n830), .Y(n4779) );
NOR2X1TS U6113 ( .A(DP_OP_169J43_123_4229_n805), .B(
DP_OP_169J43_123_4229_n816), .Y(n4767) );
INVX2TS U6114 ( .A(n4767), .Y(n4774) );
NAND2X2TS U6115 ( .A(n4774), .B(n4770), .Y(n4754) );
NOR2X1TS U6116 ( .A(DP_OP_169J43_123_4229_n791), .B(
DP_OP_169J43_123_4229_n781), .Y(n4758) );
INVX2TS U6117 ( .A(n4758), .Y(n4764) );
NAND2X2TS U6118 ( .A(n4749), .B(n4751), .Y(n4676) );
NAND2X1TS U6119 ( .A(DP_OP_169J43_123_4229_n845), .B(
DP_OP_169J43_123_4229_n860), .Y(n4792) );
OAI21X1TS U6120 ( .A0(n4791), .A1(n4796), .B0(n4792), .Y(n4777) );
NAND2X1TS U6121 ( .A(DP_OP_169J43_123_4229_n831), .B(
DP_OP_169J43_123_4229_n844), .Y(n4785) );
NAND2X1TS U6122 ( .A(DP_OP_169J43_123_4229_n817), .B(
DP_OP_169J43_123_4229_n830), .Y(n4780) );
NAND2X1TS U6123 ( .A(DP_OP_169J43_123_4229_n805), .B(
DP_OP_169J43_123_4229_n816), .Y(n4773) );
INVX2TS U6124 ( .A(n4773), .Y(n4669) );
NAND2X1TS U6125 ( .A(DP_OP_169J43_123_4229_n804), .B(
DP_OP_169J43_123_4229_n792), .Y(n4769) );
INVX2TS U6126 ( .A(n4769), .Y(n4668) );
AOI21X1TS U6127 ( .A0(n4669), .A1(n4770), .B0(n4668), .Y(n4755) );
NAND2X1TS U6128 ( .A(DP_OP_169J43_123_4229_n791), .B(
DP_OP_169J43_123_4229_n781), .Y(n4763) );
NAND2X1TS U6129 ( .A(DP_OP_169J43_123_4229_n780), .B(
DP_OP_169J43_123_4229_n770), .Y(n4759) );
INVX2TS U6130 ( .A(n4759), .Y(n4670) );
AOI21X1TS U6131 ( .A0(n4671), .A1(n4760), .B0(n4670), .Y(n4672) );
NAND2X1TS U6132 ( .A(DP_OP_169J43_123_4229_n761), .B(
DP_OP_169J43_123_4229_n769), .Y(n4750) );
INVX2TS U6133 ( .A(n4750), .Y(n4674) );
AOI21X1TS U6134 ( .A0(n4748), .A1(n4751), .B0(n4674), .Y(n4675) );
OAI21X2TS U6135 ( .A0(n4745), .A1(n4676), .B0(n4675), .Y(n4738) );
NAND2X1TS U6136 ( .A(DP_OP_169J43_123_4229_n751), .B(
DP_OP_169J43_123_4229_n760), .Y(n4740) );
INVX2TS U6137 ( .A(n4740), .Y(n4677) );
NAND2X1TS U6138 ( .A(DP_OP_169J43_123_4229_n743), .B(
DP_OP_169J43_123_4229_n750), .Y(n4733) );
INVX2TS U6139 ( .A(n4733), .Y(n4680) );
NOR2X1TS U6140 ( .A(DP_OP_169J43_123_4229_n735), .B(
DP_OP_169J43_123_4229_n742), .Y(n4728) );
NAND2X1TS U6141 ( .A(DP_OP_169J43_123_4229_n735), .B(
DP_OP_169J43_123_4229_n742), .Y(n4729) );
NAND2X1TS U6142 ( .A(DP_OP_169J43_123_4229_n729), .B(
DP_OP_169J43_123_4229_n734), .Y(n4724) );
INVX2TS U6143 ( .A(n4724), .Y(n4681) );
NOR2X1TS U6144 ( .A(DP_OP_169J43_123_4229_n728), .B(
DP_OP_169J43_123_4229_n722), .Y(n4719) );
NAND2X1TS U6145 ( .A(DP_OP_169J43_123_4229_n728), .B(
DP_OP_169J43_123_4229_n722), .Y(n4720) );
OAI21X4TS U6146 ( .A0(n4723), .A1(n4719), .B0(n4720), .Y(n4718) );
NAND2X1TS U6147 ( .A(DP_OP_169J43_123_4229_n721), .B(
DP_OP_169J43_123_4229_n717), .Y(n4715) );
INVX2TS U6148 ( .A(n4715), .Y(n4682) );
NOR2X1TS U6149 ( .A(DP_OP_169J43_123_4229_n712), .B(
DP_OP_169J43_123_4229_n716), .Y(n4710) );
NAND2X1TS U6150 ( .A(DP_OP_169J43_123_4229_n712), .B(
DP_OP_169J43_123_4229_n716), .Y(n4711) );
NAND2X1TS U6151 ( .A(DP_OP_169J43_123_4229_n709), .B(
DP_OP_169J43_123_4229_n711), .Y(n4706) );
INVX2TS U6152 ( .A(n4706), .Y(n4683) );
XNOR2X1TS U6153 ( .A(n5547), .B(Op_MX[26]), .Y(n5112) );
BUFX4TS U6154 ( .A(n4685), .Y(n5141) );
OAI22X1TS U6155 ( .A0(n5112), .A1(n4684), .B0(n5141), .B1(n4971), .Y(n4689)
);
INVX2TS U6156 ( .A(n5549), .Y(n4686) );
NOR2X1TS U6157 ( .A(n4686), .B(n4971), .Y(n4692) );
INVX2TS U6158 ( .A(n4692), .Y(n4688) );
NOR2X1TS U6159 ( .A(DP_OP_169J43_123_4229_n708), .B(n4687), .Y(n4701) );
NAND2X1TS U6160 ( .A(DP_OP_169J43_123_4229_n708), .B(n4687), .Y(n4702) );
CMPR32X2TS U6161 ( .A(n4689), .B(n4688), .C(DP_OP_169J43_123_4229_n707),
.CO(n4696), .S(n4687) );
INVX2TS U6162 ( .A(n4690), .Y(n4694) );
NOR2X1TS U6163 ( .A(n4691), .B(n4964), .Y(n4693) );
OR2X1TS U6164 ( .A(n4696), .B(n4695), .Y(n4698) );
NAND2X1TS U6165 ( .A(n4696), .B(n4695), .Y(n4697) );
NAND2X1TS U6166 ( .A(n4698), .B(n4697), .Y(n4699) );
XNOR2X1TS U6167 ( .A(n4700), .B(n4699), .Y(Sgf_operation_ODD1_middle_N55) );
INVX2TS U6168 ( .A(n4701), .Y(n4703) );
NAND2X1TS U6169 ( .A(n4703), .B(n4702), .Y(n4704) );
NAND2X1TS U6170 ( .A(n4707), .B(n4706), .Y(n4708) );
XNOR2X1TS U6171 ( .A(n4709), .B(n4708), .Y(Sgf_operation_ODD1_middle_N53) );
INVX2TS U6172 ( .A(n4710), .Y(n4712) );
NAND2X1TS U6173 ( .A(n4712), .B(n4711), .Y(n4713) );
NAND2X1TS U6174 ( .A(n4716), .B(n4715), .Y(n4717) );
XNOR2X1TS U6175 ( .A(n4718), .B(n4717), .Y(Sgf_operation_ODD1_middle_N51) );
NAND2X1TS U6176 ( .A(n4721), .B(n4720), .Y(n4722) );
NAND2X1TS U6177 ( .A(n4725), .B(n4724), .Y(n4726) );
XNOR2X1TS U6178 ( .A(n4727), .B(n4726), .Y(Sgf_operation_ODD1_middle_N49) );
INVX2TS U6179 ( .A(n4728), .Y(n4730) );
NAND2X1TS U6180 ( .A(n4730), .B(n4729), .Y(n4731) );
NAND2X1TS U6181 ( .A(n4734), .B(n4733), .Y(n4735) );
XNOR2X1TS U6182 ( .A(n4736), .B(n4735), .Y(Sgf_operation_ODD1_middle_N47) );
AOI21X1TS U6183 ( .A0(n4799), .A1(n4739), .B0(n4738), .Y(n4743) );
NAND2X1TS U6184 ( .A(n4741), .B(n4740), .Y(n4742) );
INVX2TS U6185 ( .A(n4744), .Y(n4747) );
INVX2TS U6186 ( .A(n4745), .Y(n4746) );
AOI21X1TS U6187 ( .A0(n4776), .A1(n4749), .B0(n4748), .Y(n4753) );
NAND2X1TS U6188 ( .A(n4751), .B(n4750), .Y(n4752) );
INVX2TS U6189 ( .A(n4754), .Y(n4757) );
INVX2TS U6190 ( .A(n4755), .Y(n4756) );
NAND2X1TS U6191 ( .A(n4760), .B(n4759), .Y(n4761) );
XNOR2X1TS U6192 ( .A(n4762), .B(n4761), .Y(Sgf_operation_ODD1_middle_N44) );
NAND2X1TS U6193 ( .A(n4764), .B(n4763), .Y(n4765) );
NAND2X1TS U6194 ( .A(n4770), .B(n4769), .Y(n4771) );
XNOR2X1TS U6195 ( .A(n4772), .B(n4771), .Y(Sgf_operation_ODD1_middle_N42) );
NAND2X1TS U6196 ( .A(n4774), .B(n4773), .Y(n4775) );
XNOR2X1TS U6197 ( .A(n4776), .B(n4775), .Y(Sgf_operation_ODD1_middle_N41) );
INVX2TS U6198 ( .A(n4779), .Y(n4781) );
NAND2X1TS U6199 ( .A(n4781), .B(n4780), .Y(n4782) );
XNOR2X1TS U6200 ( .A(n4783), .B(n4782), .Y(Sgf_operation_ODD1_middle_N40) );
INVX2TS U6201 ( .A(n4784), .Y(n4786) );
NAND2X1TS U6202 ( .A(n4786), .B(n4785), .Y(n4787) );
INVX2TS U6203 ( .A(n4789), .Y(n4797) );
INVX2TS U6204 ( .A(n4796), .Y(n4790) );
AOI21X1TS U6205 ( .A0(n4799), .A1(n4797), .B0(n4790), .Y(n4795) );
INVX2TS U6206 ( .A(n4791), .Y(n4793) );
NAND2X1TS U6207 ( .A(n4793), .B(n4792), .Y(n4794) );
NAND2X1TS U6208 ( .A(n4797), .B(n4796), .Y(n4798) );
XNOR2X1TS U6209 ( .A(n4799), .B(n4798), .Y(Sgf_operation_ODD1_middle_N37) );
NAND2X1TS U6210 ( .A(n4801), .B(n4800), .Y(n4802) );
XNOR2X1TS U6211 ( .A(n4803), .B(n4802), .Y(Sgf_operation_ODD1_middle_N35) );
NAND2X1TS U6212 ( .A(n4805), .B(n4804), .Y(n4806) );
XNOR2X1TS U6213 ( .A(n4807), .B(n4806), .Y(Sgf_operation_ODD1_middle_N31) );
NAND2X1TS U6214 ( .A(n4810), .B(n4809), .Y(n4811) );
XNOR2X1TS U6215 ( .A(n4812), .B(n4811), .Y(Sgf_operation_ODD1_middle_N30) );
INVX2TS U6216 ( .A(n4813), .Y(n4815) );
NAND2X1TS U6217 ( .A(n4815), .B(n4814), .Y(n4816) );
INVX2TS U6218 ( .A(n4818), .Y(n4841) );
AOI21X1TS U6219 ( .A0(n4841), .A1(n4820), .B0(n4819), .Y(n4830) );
NAND2X1TS U6220 ( .A(n4823), .B(n4822), .Y(n4824) );
XNOR2X1TS U6221 ( .A(n4825), .B(n4824), .Y(Sgf_operation_ODD1_middle_N28) );
INVX2TS U6222 ( .A(n4826), .Y(n4828) );
NAND2X1TS U6223 ( .A(n4828), .B(n4827), .Y(n4829) );
INVX2TS U6224 ( .A(n4831), .Y(n4839) );
INVX2TS U6225 ( .A(n4838), .Y(n4832) );
AOI21X1TS U6226 ( .A0(n4841), .A1(n4839), .B0(n4832), .Y(n4837) );
INVX2TS U6227 ( .A(n4833), .Y(n4835) );
NAND2X1TS U6228 ( .A(n4835), .B(n4834), .Y(n4836) );
NAND2X1TS U6229 ( .A(n4839), .B(n4838), .Y(n4840) );
XNOR2X1TS U6230 ( .A(n4841), .B(n4840), .Y(Sgf_operation_ODD1_middle_N25) );
INVX2TS U6231 ( .A(n4842), .Y(n4858) );
NAND2X1TS U6232 ( .A(n4847), .B(n4846), .Y(n4848) );
XNOR2X1TS U6233 ( .A(n4849), .B(n4848), .Y(Sgf_operation_ODD1_middle_N24) );
NAND2X1TS U6234 ( .A(n4852), .B(n4851), .Y(n4853) );
XNOR2X1TS U6235 ( .A(n4854), .B(n4853), .Y(Sgf_operation_ODD1_middle_N23) );
NAND2X1TS U6236 ( .A(n4856), .B(n4855), .Y(n4857) );
INVX2TS U6237 ( .A(n4859), .Y(n4876) );
AOI21X1TS U6238 ( .A0(n4876), .A1(n4861), .B0(n4860), .Y(n4865) );
NAND2X1TS U6239 ( .A(n4863), .B(n4862), .Y(n4864) );
INVX2TS U6240 ( .A(n4866), .Y(n4874) );
INVX2TS U6241 ( .A(n4873), .Y(n4867) );
AOI21X1TS U6242 ( .A0(n4876), .A1(n4874), .B0(n4867), .Y(n4872) );
INVX2TS U6243 ( .A(n4868), .Y(n4870) );
NAND2X1TS U6244 ( .A(n4870), .B(n4869), .Y(n4871) );
NAND2X1TS U6245 ( .A(n4874), .B(n4873), .Y(n4875) );
XNOR2X1TS U6246 ( .A(n4876), .B(n4875), .Y(Sgf_operation_ODD1_middle_N19) );
INVX2TS U6247 ( .A(n4877), .Y(n4892) );
INVX2TS U6248 ( .A(n4880), .Y(n4882) );
NAND2X1TS U6249 ( .A(n4882), .B(n4881), .Y(n4883) );
XNOR2X1TS U6250 ( .A(n4884), .B(n4883), .Y(Sgf_operation_ODD1_middle_N18) );
NAND2X1TS U6251 ( .A(n753), .B(n4886), .Y(n4887) );
XNOR2X1TS U6252 ( .A(n4888), .B(n4887), .Y(Sgf_operation_ODD1_middle_N17) );
NAND2X1TS U6253 ( .A(n4890), .B(n4889), .Y(n4891) );
INVX2TS U6254 ( .A(n4893), .Y(n4901) );
AOI21X1TS U6255 ( .A0(n4901), .A1(n898), .B0(n4894), .Y(n4898) );
NAND2X1TS U6256 ( .A(n4896), .B(n4895), .Y(n4897) );
NAND2X1TS U6257 ( .A(n898), .B(n4899), .Y(n4900) );
XNOR2X1TS U6258 ( .A(n4901), .B(n4900), .Y(Sgf_operation_ODD1_middle_N14) );
INVX2TS U6259 ( .A(n4905), .Y(n4907) );
NAND2X1TS U6260 ( .A(n4907), .B(n4906), .Y(n4908) );
XNOR2X1TS U6261 ( .A(n4909), .B(n4908), .Y(Sgf_operation_ODD1_middle_N13) );
INVX2TS U6262 ( .A(n4910), .Y(n4917) );
AOI21X1TS U6263 ( .A0(n4917), .A1(n891), .B0(n4911), .Y(n4914) );
NAND2X1TS U6264 ( .A(n890), .B(n4912), .Y(n4913) );
NAND2X1TS U6265 ( .A(n891), .B(n4915), .Y(n4916) );
XNOR2X1TS U6266 ( .A(n4917), .B(n4916), .Y(Sgf_operation_ODD1_middle_N10) );
INVX2TS U6267 ( .A(n4921), .Y(n4923) );
NAND2X1TS U6268 ( .A(n4923), .B(n4922), .Y(n4924) );
XNOR2X1TS U6269 ( .A(n4925), .B(n4924), .Y(Sgf_operation_ODD1_middle_N9) );
INVX2TS U6270 ( .A(n4926), .Y(n4928) );
NAND2X1TS U6271 ( .A(n4928), .B(n4927), .Y(n4930) );
NAND2X1TS U6272 ( .A(n869), .B(n4931), .Y(n4933) );
XNOR2X1TS U6273 ( .A(n4933), .B(n4932), .Y(Sgf_operation_ODD1_middle_N6) );
INVX2TS U6274 ( .A(n4934), .Y(n4936) );
NAND2X1TS U6275 ( .A(n4936), .B(n4935), .Y(n4938) );
NAND2X1TS U6276 ( .A(n895), .B(n4939), .Y(n4941) );
XNOR2X1TS U6277 ( .A(n4941), .B(n4940), .Y(Sgf_operation_ODD1_middle_N4) );
INVX2TS U6278 ( .A(n4942), .Y(n4944) );
NAND2X1TS U6279 ( .A(n4944), .B(n4943), .Y(n4945) );
NAND2X1TS U6280 ( .A(n837), .B(n4947), .Y(n4949) );
XNOR2X1TS U6281 ( .A(n4949), .B(n4948), .Y(Sgf_operation_ODD1_middle_N2) );
INVX2TS U6282 ( .A(n4950), .Y(n4953) );
XNOR2X1TS U6283 ( .A(n5547), .B(n5335), .Y(n5310) );
BUFX4TS U6284 ( .A(n4951), .Y(n5328) );
OAI22X1TS U6285 ( .A0(n5310), .A1(n5328), .B0(n5339), .B1(n876), .Y(n4952)
);
CMPR32X2TS U6286 ( .A(n4953), .B(n4952), .C(DP_OP_169J43_123_4229_n812),
.CO(DP_OP_169J43_123_4229_n799), .S(DP_OP_169J43_123_4229_n800) );
INVX2TS U6287 ( .A(n4954), .Y(n4956) );
XNOR2X1TS U6288 ( .A(n5589), .B(n5133), .Y(n5134) );
XNOR2X1TS U6289 ( .A(n5586), .B(n5133), .Y(n5131) );
OAI22X1TS U6290 ( .A0(n5134), .A1(n5138), .B0(n5131), .B1(n5136), .Y(n4955)
);
CMPR32X2TS U6291 ( .A(n4956), .B(n4955), .C(DP_OP_169J43_123_4229_n942),
.CO(DP_OP_169J43_123_4229_n923), .S(DP_OP_169J43_123_4229_n924) );
INVX2TS U6292 ( .A(n5502), .Y(n4958) );
CMPR32X2TS U6293 ( .A(n4957), .B(n4960), .C(n4959), .CO(
DP_OP_169J43_123_4229_n983), .S(DP_OP_169J43_123_4229_n984) );
INVX2TS U6294 ( .A(n5505), .Y(n4961) );
XNOR2X1TS U6295 ( .A(n5540), .B(n5133), .Y(n5139) );
XNOR2X1TS U6296 ( .A(n5502), .B(n5122), .Y(n4966) );
OAI22X1TS U6297 ( .A0(n5139), .A1(n5141), .B0(n4966), .B1(n5138), .Y(n4962)
);
CMPR32X2TS U6298 ( .A(n5591), .B(n4963), .C(n4962), .CO(
DP_OP_169J43_123_4229_n1003), .S(DP_OP_169J43_123_4229_n1004) );
INVX2TS U6299 ( .A(n5097), .Y(n4965) );
XNOR2X1TS U6300 ( .A(n5505), .B(n5122), .Y(n4973) );
OAI22X1TS U6301 ( .A0(n4966), .A1(n5141), .B0(n4973), .B1(n5138), .Y(n4967)
);
CMPR32X2TS U6302 ( .A(n5591), .B(n4968), .C(n4967), .CO(
DP_OP_169J43_123_4229_n1025), .S(DP_OP_169J43_123_4229_n1026) );
XNOR2X1TS U6303 ( .A(n5097), .B(n5122), .Y(n4972) );
XNOR2X1TS U6304 ( .A(n5093), .B(n5133), .Y(n4970) );
OAI22X1TS U6305 ( .A0(n4972), .A1(n5141), .B0(n4970), .B1(n5138), .Y(n4974)
);
NOR2BX1TS U6306 ( .AN(n5475), .B(n4971), .Y(n4978) );
OAI22X1TS U6307 ( .A0(n4973), .A1(n5141), .B0(n4972), .B1(n5138), .Y(n4977)
);
ADDHXLTS U6308 ( .A(n4975), .B(n4974), .CO(n4976), .S(
DP_OP_169J43_123_4229_n1067) );
CMPR32X2TS U6309 ( .A(n4978), .B(n4977), .C(n4976), .CO(
DP_OP_169J43_123_4229_n1046), .S(DP_OP_169J43_123_4229_n1047) );
OAI22X1TS U6310 ( .A0(n4979), .A1(n5175), .B0(n5157), .B1(n5143), .Y(n4984)
);
XNOR2X1TS U6311 ( .A(n5097), .B(n5171), .Y(n5174) );
XNOR2X1TS U6312 ( .A(n5093), .B(n5171), .Y(n4980) );
OAI22X1TS U6313 ( .A0(n5174), .A1(n5175), .B0(n4980), .B1(n5173), .Y(n4983)
);
INVX4TS U6314 ( .A(n900), .Y(n5195) );
OAI22X1TS U6315 ( .A0(n4981), .A1(n5206), .B0(n5196), .B1(n900), .Y(n4988)
);
XNOR2X1TS U6316 ( .A(n5097), .B(n5202), .Y(n4985) );
XNOR2X1TS U6317 ( .A(n5093), .B(n5202), .Y(n4982) );
OAI22X1TS U6318 ( .A0(n4985), .A1(n5206), .B0(n4982), .B1(n5204), .Y(n4987)
);
XNOR2X1TS U6319 ( .A(n5502), .B(n5202), .Y(n5205) );
XNOR2X1TS U6320 ( .A(n5505), .B(n5202), .Y(n4986) );
OAI22X1TS U6321 ( .A0(n5205), .A1(n5206), .B0(n4986), .B1(n5196), .Y(n4990)
);
NOR2BX1TS U6322 ( .AN(n5475), .B(n5142), .Y(n4994) );
OAI22X1TS U6323 ( .A0(n4986), .A1(n5206), .B0(n4985), .B1(n5204), .Y(n4993)
);
CMPR32X2TS U6324 ( .A(n4991), .B(n4990), .C(n4989), .CO(
DP_OP_169J43_123_4229_n1101), .S(DP_OP_169J43_123_4229_n1102) );
CMPR32X2TS U6325 ( .A(n4994), .B(n4993), .C(n4992), .CO(n4989), .S(
DP_OP_169J43_123_4229_n1121) );
XOR2X1TS U6326 ( .A(Op_MX[20]), .B(Op_MX[47]), .Y(n5001) );
XNOR2X1TS U6327 ( .A(n5001), .B(n4995), .Y(n4999) );
NAND2X1TS U6328 ( .A(n4997), .B(n4996), .Y(n4998) );
CLKXOR2X2TS U6329 ( .A(n4999), .B(n4998), .Y(n5209) );
XOR2X1TS U6330 ( .A(n5002), .B(n5004), .Y(n5003) );
BUFX4TS U6331 ( .A(n5213), .Y(n5224) );
INVX4TS U6332 ( .A(n762), .Y(n5231) );
BUFX4TS U6333 ( .A(n5209), .Y(n5234) );
OAI22X1TS U6334 ( .A0(n5224), .A1(n762), .B0(n5006), .B1(n5234), .Y(n5013)
);
XNOR2X1TS U6335 ( .A(n5097), .B(n5238), .Y(n5241) );
XNOR2X1TS U6336 ( .A(n5093), .B(n5238), .Y(n5007) );
OAI22X1TS U6337 ( .A0(n5241), .A1(n5242), .B0(n5224), .B1(n5007), .Y(n5012)
);
OAI22X1TS U6338 ( .A0(n5009), .A1(n5273), .B0(n5257), .B1(n5008), .Y(n5017)
);
XNOR2X1TS U6339 ( .A(n5097), .B(n5269), .Y(n5014) );
XNOR2X1TS U6340 ( .A(n5093), .B(n5269), .Y(n5011) );
OAI22X1TS U6341 ( .A0(n5014), .A1(n5273), .B0(n5011), .B1(n5271), .Y(n5016)
);
XNOR2X1TS U6342 ( .A(n5502), .B(n5269), .Y(n5272) );
XNOR2X1TS U6343 ( .A(n5505), .B(n5269), .Y(n5015) );
OAI22X1TS U6344 ( .A0(n5272), .A1(n5273), .B0(n5015), .B1(n5271), .Y(n5019)
);
NOR2BX1TS U6345 ( .AN(n5475), .B(n5209), .Y(n5023) );
OAI22X1TS U6346 ( .A0(n5015), .A1(n5273), .B0(n5014), .B1(n5271), .Y(n5022)
);
ADDHXLTS U6347 ( .A(n5017), .B(n5016), .CO(n5021), .S(
DP_OP_169J43_123_4229_n1197) );
CMPR32X2TS U6348 ( .A(n5020), .B(n5019), .C(n5018), .CO(
DP_OP_169J43_123_4229_n1166), .S(DP_OP_169J43_123_4229_n1167) );
CMPR32X2TS U6349 ( .A(n5023), .B(n5022), .C(n5021), .CO(n5018), .S(
DP_OP_169J43_123_4229_n1183) );
INVX4TS U6350 ( .A(n811), .Y(n5296) );
XOR2X1TS U6351 ( .A(n790), .B(Op_MX[43]), .Y(n5030) );
XNOR2X1TS U6352 ( .A(n5030), .B(n5025), .Y(n5029) );
NAND2X1TS U6353 ( .A(n5027), .B(n5026), .Y(n5028) );
CLKXOR2X2TS U6354 ( .A(n5029), .B(n5028), .Y(n5277) );
XOR2X1TS U6355 ( .A(Op_MX[42]), .B(Op_MX[43]), .Y(n5031) );
XOR2X1TS U6356 ( .A(n5033), .B(n5032), .Y(n5034) );
BUFX4TS U6357 ( .A(n5036), .Y(n5290) );
OAI22X1TS U6358 ( .A0(n5035), .A1(n5308), .B0(n5290), .B1(n811), .Y(n5041)
);
XNOR2X1TS U6359 ( .A(n5097), .B(n5304), .Y(n5307) );
XNOR2X1TS U6360 ( .A(n5093), .B(n5304), .Y(n5037) );
BUFX4TS U6361 ( .A(n5036), .Y(n5306) );
OAI22X1TS U6362 ( .A0(n5307), .A1(n5308), .B0(n5037), .B1(n5306), .Y(n5040)
);
INVX4TS U6363 ( .A(n876), .Y(n5330) );
BUFX4TS U6364 ( .A(n5341), .Y(n5333) );
OAI22X1TS U6365 ( .A0(n5328), .A1(n876), .B0(n5038), .B1(n5333), .Y(n5045)
);
XNOR2X1TS U6366 ( .A(n5097), .B(n5335), .Y(n5042) );
XNOR2X1TS U6367 ( .A(n5093), .B(n5335), .Y(n5039) );
OAI22X1TS U6368 ( .A0(n5042), .A1(n5339), .B0(n5328), .B1(n5039), .Y(n5044)
);
XNOR2X1TS U6369 ( .A(n5502), .B(n5335), .Y(n5338) );
XNOR2X1TS U6370 ( .A(n5505), .B(n5335), .Y(n5043) );
OAI22X1TS U6371 ( .A0(n5338), .A1(n5339), .B0(n5043), .B1(n5337), .Y(n5047)
);
NOR2BX1TS U6372 ( .AN(n5093), .B(n5277), .Y(n5051) );
OAI22X1TS U6373 ( .A0(n5043), .A1(n5339), .B0(n5042), .B1(n5337), .Y(n5050)
);
CMPR32X2TS U6374 ( .A(n5048), .B(n5047), .C(n5046), .CO(
DP_OP_169J43_123_4229_n1219), .S(DP_OP_169J43_123_4229_n1220) );
CMPR32X2TS U6375 ( .A(n5051), .B(n5050), .C(n5049), .CO(n5046), .S(
DP_OP_169J43_123_4229_n1233) );
XOR2X1TS U6376 ( .A(Op_MX[12]), .B(Op_MX[39]), .Y(n5058) );
XNOR2X1TS U6377 ( .A(n5058), .B(n5053), .Y(n5057) );
NAND2X1TS U6378 ( .A(n5055), .B(n5054), .Y(n5056) );
CLKXOR2X2TS U6379 ( .A(n5057), .B(n5056), .Y(n5343) );
XOR2X1TS U6380 ( .A(n5061), .B(n5060), .Y(n5062) );
BUFX4TS U6381 ( .A(n5064), .Y(n5361) );
OAI22X1TS U6382 ( .A0(n5063), .A1(n5374), .B0(n5361), .B1(n897), .Y(n5070)
);
XNOR2X1TS U6383 ( .A(n5097), .B(n5370), .Y(n5373) );
XNOR2X1TS U6384 ( .A(n5093), .B(n5370), .Y(n5065) );
BUFX4TS U6385 ( .A(n5064), .Y(n5372) );
OAI22X1TS U6386 ( .A0(n5373), .A1(n5374), .B0(n5065), .B1(n5372), .Y(n5069)
);
INVX4TS U6387 ( .A(n889), .Y(n5396) );
OAI22X1TS U6388 ( .A0(n5066), .A1(n5405), .B0(n5389), .B1(n889), .Y(n5074)
);
XNOR2X1TS U6389 ( .A(n5097), .B(n5401), .Y(n5071) );
XNOR2X1TS U6390 ( .A(n5093), .B(n5401), .Y(n5068) );
BUFX4TS U6391 ( .A(n5067), .Y(n5403) );
OAI22X1TS U6392 ( .A0(n5071), .A1(n5405), .B0(n5068), .B1(n5403), .Y(n5073)
);
XNOR2X1TS U6393 ( .A(n5502), .B(n5401), .Y(n5404) );
XNOR2X1TS U6394 ( .A(n5505), .B(n5401), .Y(n5072) );
OAI22X1TS U6395 ( .A0(n5404), .A1(n5405), .B0(n5072), .B1(n5389), .Y(n5076)
);
NOR2BX1TS U6396 ( .AN(n5475), .B(n5343), .Y(n5080) );
OAI22X1TS U6397 ( .A0(n5072), .A1(n5405), .B0(n5071), .B1(n5403), .Y(n5079)
);
CMPR32X2TS U6398 ( .A(n5077), .B(n5076), .C(n5075), .CO(
DP_OP_169J43_123_4229_n1260), .S(DP_OP_169J43_123_4229_n1261) );
CMPR32X2TS U6399 ( .A(n5080), .B(n5079), .C(n5078), .CO(n5075), .S(
DP_OP_169J43_123_4229_n1271) );
XOR2X1TS U6400 ( .A(Op_MX[8]), .B(Op_MX[35]), .Y(n5087) );
XNOR2X1TS U6401 ( .A(n5087), .B(n5081), .Y(n5085) );
NAND2X1TS U6402 ( .A(n5083), .B(n5082), .Y(n5084) );
CLKXOR2X2TS U6403 ( .A(n5085), .B(n5084), .Y(n5408) );
XOR2X1TS U6404 ( .A(n5088), .B(n5090), .Y(n5089) );
BUFX4TS U6405 ( .A(n5408), .Y(n5433) );
OAI22X1TS U6406 ( .A0(n5423), .A1(n761), .B0(n5092), .B1(n5433), .Y(n5101)
);
XNOR2X1TS U6407 ( .A(n5097), .B(n5437), .Y(n5440) );
XNOR2X1TS U6408 ( .A(n5093), .B(n5437), .Y(n5094) );
OAI22X1TS U6409 ( .A0(n5440), .A1(n5441), .B0(n5423), .B1(n5094), .Y(n5100)
);
INVX4TS U6410 ( .A(n812), .Y(n5461) );
BUFX4TS U6411 ( .A(n5095), .Y(n5462) );
OAI22X1TS U6412 ( .A0(n5096), .A1(n5472), .B0(n5462), .B1(n812), .Y(n5105)
);
XNOR2X1TS U6413 ( .A(n5097), .B(n5468), .Y(n5102) );
XNOR2X1TS U6414 ( .A(n5098), .B(n5468), .Y(n5099) );
OAI22X1TS U6415 ( .A0(n5102), .A1(n5472), .B0(n5099), .B1(n5470), .Y(n5104)
);
ADDHXLTS U6416 ( .A(n5101), .B(n5100), .CO(DP_OP_169J43_123_4229_n1291), .S(
n5108) );
XNOR2X1TS U6417 ( .A(n5502), .B(n5468), .Y(n5471) );
XNOR2X1TS U6418 ( .A(n5505), .B(n5468), .Y(n5103) );
OAI22X1TS U6419 ( .A0(n5471), .A1(n5472), .B0(n5103), .B1(n5462), .Y(n5107)
);
NOR2BX1TS U6420 ( .AN(n5475), .B(n5408), .Y(n5111) );
OAI22X1TS U6421 ( .A0(n5103), .A1(n5472), .B0(n5102), .B1(n5470), .Y(n5110)
);
CMPR32X2TS U6422 ( .A(n5108), .B(n5107), .C(n5106), .CO(
DP_OP_169J43_123_4229_n1289), .S(DP_OP_169J43_123_4229_n1290) );
CMPR32X2TS U6423 ( .A(n5111), .B(n5110), .C(n5109), .CO(n5106), .S(
DP_OP_169J43_123_4229_n1297) );
XNOR2X1TS U6424 ( .A(n5549), .B(n5133), .Y(n5113) );
OAI22X1TS U6425 ( .A0(n5113), .A1(n4684), .B0(n5112), .B1(n5141), .Y(
DP_OP_169J43_123_4229_n1346) );
XNOR2X1TS U6426 ( .A(n5551), .B(n5133), .Y(n5114) );
OAI22X1TS U6427 ( .A0(n5114), .A1(n4684), .B0(n5113), .B1(n5136), .Y(
DP_OP_169J43_123_4229_n1347) );
XNOR2X1TS U6428 ( .A(n5553), .B(n5133), .Y(n5115) );
OAI22X1TS U6429 ( .A0(n5115), .A1(n4684), .B0(n5114), .B1(n5136), .Y(
DP_OP_169J43_123_4229_n1348) );
XNOR2X1TS U6430 ( .A(n5555), .B(n5133), .Y(n5116) );
OAI22X1TS U6431 ( .A0(n5116), .A1(n4684), .B0(n5115), .B1(n5141), .Y(
DP_OP_169J43_123_4229_n1349) );
XNOR2X1TS U6432 ( .A(n5557), .B(n5122), .Y(n5117) );
OAI22X1TS U6433 ( .A0(n5117), .A1(n4684), .B0(n5116), .B1(n5136), .Y(
DP_OP_169J43_123_4229_n1350) );
XNOR2X1TS U6434 ( .A(n5559), .B(n5122), .Y(n5118) );
OAI22X1TS U6435 ( .A0(n5118), .A1(n4684), .B0(n5117), .B1(n5136), .Y(
DP_OP_169J43_123_4229_n1351) );
XNOR2X1TS U6436 ( .A(n5561), .B(Op_MX[26]), .Y(n5119) );
OAI22X1TS U6437 ( .A0(n5119), .A1(n4684), .B0(n5118), .B1(n5136), .Y(
DP_OP_169J43_123_4229_n1352) );
XNOR2X1TS U6438 ( .A(n5563), .B(n5122), .Y(n5120) );
OAI22X1TS U6439 ( .A0(n5120), .A1(n4684), .B0(n5119), .B1(n5136), .Y(
DP_OP_169J43_123_4229_n1353) );
XNOR2X1TS U6440 ( .A(n5565), .B(n5122), .Y(n5121) );
OAI22X1TS U6441 ( .A0(n5121), .A1(n4684), .B0(n5120), .B1(n5136), .Y(
DP_OP_169J43_123_4229_n1354) );
XNOR2X1TS U6442 ( .A(n5567), .B(n5122), .Y(n5123) );
OAI22X1TS U6443 ( .A0(n5123), .A1(n4684), .B0(n5121), .B1(n5136), .Y(
DP_OP_169J43_123_4229_n1355) );
XNOR2X1TS U6444 ( .A(n5569), .B(n5122), .Y(n5124) );
OAI22X1TS U6445 ( .A0(n5123), .A1(n5141), .B0(n5124), .B1(n5138), .Y(
DP_OP_169J43_123_4229_n1356) );
XNOR2X1TS U6446 ( .A(n5571), .B(Op_MX[26]), .Y(n5125) );
OAI22X1TS U6447 ( .A0(n5124), .A1(n5141), .B0(n5125), .B1(n4684), .Y(
DP_OP_169J43_123_4229_n1357) );
XNOR2X1TS U6448 ( .A(n5573), .B(Op_MX[26]), .Y(n5126) );
OAI22X1TS U6449 ( .A0(n5126), .A1(n4684), .B0(n5125), .B1(n5136), .Y(
DP_OP_169J43_123_4229_n1358) );
XNOR2X1TS U6450 ( .A(n5575), .B(Op_MX[26]), .Y(n5127) );
OAI22X1TS U6451 ( .A0(n5127), .A1(n5138), .B0(n5126), .B1(n5141), .Y(
DP_OP_169J43_123_4229_n1359) );
OAI22X1TS U6452 ( .A0(n5128), .A1(n5138), .B0(n5127), .B1(n5136), .Y(
DP_OP_169J43_123_4229_n1360) );
XNOR2X1TS U6453 ( .A(n5581), .B(Op_MX[26]), .Y(n5130) );
OAI22X1TS U6454 ( .A0(n5130), .A1(n5138), .B0(n5129), .B1(n5136), .Y(
DP_OP_169J43_123_4229_n1362) );
XNOR2X1TS U6455 ( .A(n5583), .B(n5133), .Y(n5132) );
OAI22X1TS U6456 ( .A0(n5132), .A1(n5138), .B0(n5130), .B1(n5136), .Y(
DP_OP_169J43_123_4229_n1363) );
OAI22X1TS U6457 ( .A0(n5132), .A1(n5141), .B0(n5131), .B1(n5138), .Y(
DP_OP_169J43_123_4229_n1364) );
XNOR2X1TS U6458 ( .A(n5592), .B(n5133), .Y(n5137) );
OAI22X1TS U6459 ( .A0(n5134), .A1(n5141), .B0(n5137), .B1(n5138), .Y(
DP_OP_169J43_123_4229_n1366) );
XNOR2X1TS U6460 ( .A(n5536), .B(Op_MX[26]), .Y(n5140) );
OAI22X1TS U6461 ( .A0(n5140), .A1(n5138), .B0(n5137), .B1(n5136), .Y(
DP_OP_169J43_123_4229_n1367) );
OAI22X1TS U6462 ( .A0(n5140), .A1(n5141), .B0(n5139), .B1(n5138), .Y(
DP_OP_169J43_123_4229_n1368) );
NOR2BX1TS U6463 ( .AN(n5475), .B(n5141), .Y(DP_OP_169J43_123_4229_n1373) );
XNOR2X1TS U6464 ( .A(n5547), .B(n5171), .Y(n5144) );
OAI22X1TS U6465 ( .A0(n5144), .A1(n5157), .B0(n5175), .B1(n5143), .Y(
DP_OP_169J43_123_4229_n1375) );
OAI22X1TS U6466 ( .A0(n5145), .A1(n5157), .B0(n5144), .B1(n5175), .Y(
DP_OP_169J43_123_4229_n1376) );
XNOR2X1TS U6467 ( .A(n5553), .B(n5163), .Y(n5147) );
OAI22X1TS U6468 ( .A0(n5147), .A1(n5157), .B0(n5146), .B1(n5167), .Y(
DP_OP_169J43_123_4229_n1378) );
XNOR2X1TS U6469 ( .A(n5555), .B(n5163), .Y(n5148) );
OAI22X1TS U6470 ( .A0(n5148), .A1(n5157), .B0(n5147), .B1(n5175), .Y(
DP_OP_169J43_123_4229_n1379) );
OAI22X1TS U6471 ( .A0(n5149), .A1(n5157), .B0(n5148), .B1(n5167), .Y(
DP_OP_169J43_123_4229_n1380) );
XNOR2X1TS U6472 ( .A(n5561), .B(n5163), .Y(n5151) );
OAI22X1TS U6473 ( .A0(n5151), .A1(n5157), .B0(n5150), .B1(n5167), .Y(
DP_OP_169J43_123_4229_n1382) );
XNOR2X1TS U6474 ( .A(n5563), .B(n5163), .Y(n5152) );
OAI22X1TS U6475 ( .A0(n5152), .A1(n5157), .B0(n5151), .B1(n5167), .Y(
DP_OP_169J43_123_4229_n1383) );
XNOR2X1TS U6476 ( .A(n5565), .B(n5163), .Y(n5153) );
OAI22X1TS U6477 ( .A0(n5153), .A1(n5157), .B0(n5152), .B1(n5167), .Y(
DP_OP_169J43_123_4229_n1384) );
XNOR2X1TS U6478 ( .A(n5567), .B(n5163), .Y(n5154) );
OAI22X1TS U6479 ( .A0(n5154), .A1(n5157), .B0(n5153), .B1(n5167), .Y(
DP_OP_169J43_123_4229_n1385) );
XNOR2X1TS U6480 ( .A(n5569), .B(n5163), .Y(n5155) );
OAI22X1TS U6481 ( .A0(n5154), .A1(n5175), .B0(n5155), .B1(n5173), .Y(
DP_OP_169J43_123_4229_n1386) );
XNOR2X1TS U6482 ( .A(n5571), .B(n5171), .Y(n5156) );
OAI22X1TS U6483 ( .A0(n5155), .A1(n5175), .B0(n5156), .B1(n5157), .Y(
DP_OP_169J43_123_4229_n1387) );
OAI22X1TS U6484 ( .A0(n5158), .A1(n5157), .B0(n5156), .B1(n5167), .Y(
DP_OP_169J43_123_4229_n1388) );
XNOR2X1TS U6485 ( .A(n5577), .B(n5163), .Y(n5160) );
OAI22X1TS U6486 ( .A0(n5160), .A1(n5173), .B0(n5159), .B1(n5167), .Y(
DP_OP_169J43_123_4229_n1390) );
XNOR2X1TS U6487 ( .A(n5579), .B(n5171), .Y(n5161) );
OAI22X1TS U6488 ( .A0(n5161), .A1(n5173), .B0(n5160), .B1(n5167), .Y(
DP_OP_169J43_123_4229_n1391) );
XNOR2X1TS U6489 ( .A(n5581), .B(n5171), .Y(n5162) );
OAI22X1TS U6490 ( .A0(n5162), .A1(n5173), .B0(n5161), .B1(n5167), .Y(
DP_OP_169J43_123_4229_n1392) );
XNOR2X1TS U6491 ( .A(n5583), .B(n5163), .Y(n5164) );
OAI22X1TS U6492 ( .A0(n5164), .A1(n5173), .B0(n5162), .B1(n5167), .Y(
DP_OP_169J43_123_4229_n1393) );
XNOR2X1TS U6493 ( .A(n5586), .B(n5163), .Y(n5165) );
OAI22X1TS U6494 ( .A0(n5164), .A1(n5175), .B0(n5165), .B1(n5173), .Y(
DP_OP_169J43_123_4229_n1394) );
XNOR2X1TS U6495 ( .A(n5589), .B(n5171), .Y(n5166) );
OAI22X1TS U6496 ( .A0(n5166), .A1(n5173), .B0(n5165), .B1(n5167), .Y(
DP_OP_169J43_123_4229_n1395) );
XNOR2X1TS U6497 ( .A(n5592), .B(n5171), .Y(n5168) );
OAI22X1TS U6498 ( .A0(n5166), .A1(n5175), .B0(n5168), .B1(n5173), .Y(
DP_OP_169J43_123_4229_n1396) );
XNOR2X1TS U6499 ( .A(n5536), .B(n5171), .Y(n5169) );
OAI22X1TS U6500 ( .A0(n5169), .A1(n5173), .B0(n5168), .B1(n5167), .Y(
DP_OP_169J43_123_4229_n1397) );
XNOR2X1TS U6501 ( .A(n5540), .B(n5171), .Y(n5170) );
OAI22X1TS U6502 ( .A0(n5169), .A1(n5175), .B0(n5170), .B1(n5173), .Y(
DP_OP_169J43_123_4229_n1398) );
XNOR2X1TS U6503 ( .A(n5502), .B(n5171), .Y(n5172) );
OAI22X1TS U6504 ( .A0(n5170), .A1(n5175), .B0(n5172), .B1(n5173), .Y(
DP_OP_169J43_123_4229_n1399) );
XNOR2X1TS U6505 ( .A(n5505), .B(n5171), .Y(n5176) );
OAI22X1TS U6506 ( .A0(n5172), .A1(n5175), .B0(n5176), .B1(n5173), .Y(
DP_OP_169J43_123_4229_n1400) );
OAI22X1TS U6507 ( .A0(n5176), .A1(n5175), .B0(n5174), .B1(n5173), .Y(
DP_OP_169J43_123_4229_n1401) );
XNOR2X1TS U6508 ( .A(n5549), .B(n5195), .Y(n5178) );
OAI22X1TS U6509 ( .A0(n5178), .A1(n5196), .B0(n5177), .B1(n5206), .Y(
DP_OP_169J43_123_4229_n1406) );
XNOR2X1TS U6510 ( .A(n5551), .B(n5195), .Y(n5179) );
BUFX4TS U6511 ( .A(n5208), .Y(n5200) );
OAI22X1TS U6512 ( .A0(n5179), .A1(n5196), .B0(n5178), .B1(n5200), .Y(
DP_OP_169J43_123_4229_n1407) );
XNOR2X1TS U6513 ( .A(n5553), .B(n5195), .Y(n5180) );
OAI22X1TS U6514 ( .A0(n5180), .A1(n5196), .B0(n5179), .B1(n5200), .Y(
DP_OP_169J43_123_4229_n1408) );
XNOR2X1TS U6515 ( .A(n5555), .B(n5195), .Y(n5181) );
OAI22X1TS U6516 ( .A0(n5181), .A1(n5196), .B0(n5180), .B1(n5206), .Y(
DP_OP_169J43_123_4229_n1409) );
XNOR2X1TS U6517 ( .A(n5557), .B(n5195), .Y(n5182) );
OAI22X1TS U6518 ( .A0(n5182), .A1(n5196), .B0(n5181), .B1(n5200), .Y(
DP_OP_169J43_123_4229_n1410) );
XNOR2X1TS U6519 ( .A(n5559), .B(n5195), .Y(n5183) );
OAI22X1TS U6520 ( .A0(n5183), .A1(n5196), .B0(n5182), .B1(n5200), .Y(
DP_OP_169J43_123_4229_n1411) );
XNOR2X1TS U6521 ( .A(n5561), .B(n5195), .Y(n5184) );
OAI22X1TS U6522 ( .A0(n5184), .A1(n5196), .B0(n5183), .B1(n5200), .Y(
DP_OP_169J43_123_4229_n1412) );
XNOR2X1TS U6523 ( .A(n5563), .B(n5195), .Y(n5185) );
OAI22X1TS U6524 ( .A0(n5185), .A1(n5196), .B0(n5184), .B1(n5200), .Y(
DP_OP_169J43_123_4229_n1413) );
XNOR2X1TS U6525 ( .A(n5565), .B(n5195), .Y(n5186) );
OAI22X1TS U6526 ( .A0(n5186), .A1(n5196), .B0(n5185), .B1(n5200), .Y(
DP_OP_169J43_123_4229_n1414) );
XNOR2X1TS U6527 ( .A(n5567), .B(n5195), .Y(n5187) );
OAI22X1TS U6528 ( .A0(n5187), .A1(n5196), .B0(n5186), .B1(n5200), .Y(
DP_OP_169J43_123_4229_n1415) );
XNOR2X1TS U6529 ( .A(n5569), .B(n5195), .Y(n5188) );
OAI22X1TS U6530 ( .A0(n5187), .A1(n5206), .B0(n5188), .B1(n5204), .Y(
DP_OP_169J43_123_4229_n1416) );
XNOR2X1TS U6531 ( .A(n5571), .B(n5202), .Y(n5189) );
OAI22X1TS U6532 ( .A0(n5188), .A1(n5206), .B0(n5189), .B1(n5204), .Y(
DP_OP_169J43_123_4229_n1417) );
XNOR2X1TS U6533 ( .A(n5573), .B(n5202), .Y(n5190) );
OAI22X1TS U6534 ( .A0(n5190), .A1(n5196), .B0(n5189), .B1(n5200), .Y(
DP_OP_169J43_123_4229_n1418) );
XNOR2X1TS U6535 ( .A(n5575), .B(n5202), .Y(n5191) );
OAI22X1TS U6536 ( .A0(n5191), .A1(n5204), .B0(n5190), .B1(n5206), .Y(
DP_OP_169J43_123_4229_n1419) );
XNOR2X1TS U6537 ( .A(n5577), .B(n5195), .Y(n5192) );
OAI22X1TS U6538 ( .A0(n5192), .A1(n5204), .B0(n5191), .B1(n5200), .Y(
DP_OP_169J43_123_4229_n1420) );
XNOR2X1TS U6539 ( .A(n5579), .B(n5202), .Y(n5193) );
OAI22X1TS U6540 ( .A0(n5193), .A1(n5204), .B0(n5192), .B1(n5200), .Y(
DP_OP_169J43_123_4229_n1421) );
XNOR2X1TS U6541 ( .A(n5581), .B(n5202), .Y(n5194) );
OAI22X1TS U6542 ( .A0(n5194), .A1(n5204), .B0(n5193), .B1(n5200), .Y(
DP_OP_169J43_123_4229_n1422) );
XNOR2X1TS U6543 ( .A(n5583), .B(n5195), .Y(n5197) );
OAI22X1TS U6544 ( .A0(n5197), .A1(n5204), .B0(n5194), .B1(n5200), .Y(
DP_OP_169J43_123_4229_n1423) );
XNOR2X1TS U6545 ( .A(n5586), .B(n5195), .Y(n5198) );
OAI22X1TS U6546 ( .A0(n5197), .A1(n5206), .B0(n5198), .B1(n5196), .Y(
DP_OP_169J43_123_4229_n1424) );
XNOR2X1TS U6547 ( .A(n5589), .B(n5202), .Y(n5199) );
OAI22X1TS U6548 ( .A0(n5199), .A1(n5204), .B0(n5198), .B1(n5200), .Y(
DP_OP_169J43_123_4229_n1425) );
XNOR2X1TS U6549 ( .A(n5592), .B(n5202), .Y(n5201) );
OAI22X1TS U6550 ( .A0(n5199), .A1(n5206), .B0(n5201), .B1(n5204), .Y(
DP_OP_169J43_123_4229_n1426) );
XNOR2X1TS U6551 ( .A(n5536), .B(n5202), .Y(n5203) );
OAI22X1TS U6552 ( .A0(n5203), .A1(n5204), .B0(n5201), .B1(n5200), .Y(
DP_OP_169J43_123_4229_n1427) );
XNOR2X1TS U6553 ( .A(n5540), .B(n5202), .Y(n5207) );
OAI22X1TS U6554 ( .A0(n5203), .A1(n5206), .B0(n5207), .B1(n5204), .Y(
DP_OP_169J43_123_4229_n1428) );
OAI22X1TS U6555 ( .A0(n5207), .A1(n5206), .B0(n5205), .B1(n5204), .Y(
DP_OP_169J43_123_4229_n1429) );
NOR2BX1TS U6556 ( .AN(n5475), .B(n5208), .Y(DP_OP_169J43_123_4229_n1433) );
XNOR2X1TS U6557 ( .A(n5547), .B(n5238), .Y(n5210) );
OAI22X1TS U6558 ( .A0(n5210), .A1(n5224), .B0(n5242), .B1(n762), .Y(
DP_OP_169J43_123_4229_n1435) );
XNOR2X1TS U6559 ( .A(n5549), .B(n5231), .Y(n5211) );
OAI22X1TS U6560 ( .A0(n5211), .A1(n5224), .B0(n5210), .B1(n5242), .Y(
DP_OP_169J43_123_4229_n1436) );
XNOR2X1TS U6561 ( .A(n5551), .B(n5231), .Y(n5212) );
OAI22X1TS U6562 ( .A0(n5212), .A1(n5224), .B0(n5211), .B1(n5234), .Y(
DP_OP_169J43_123_4229_n1437) );
XNOR2X1TS U6563 ( .A(n5553), .B(n5231), .Y(n5214) );
OAI22X1TS U6564 ( .A0(n5214), .A1(n5224), .B0(n5212), .B1(n5234), .Y(
DP_OP_169J43_123_4229_n1438) );
XNOR2X1TS U6565 ( .A(n5555), .B(n5231), .Y(n5215) );
BUFX4TS U6566 ( .A(n5213), .Y(n5240) );
OAI22X1TS U6567 ( .A0(n5215), .A1(n5240), .B0(n5214), .B1(n5242), .Y(
DP_OP_169J43_123_4229_n1439) );
XNOR2X1TS U6568 ( .A(n5557), .B(n5231), .Y(n5216) );
OAI22X1TS U6569 ( .A0(n5216), .A1(n5224), .B0(n5215), .B1(n5242), .Y(
DP_OP_169J43_123_4229_n1440) );
XNOR2X1TS U6570 ( .A(n5559), .B(n5231), .Y(n5217) );
OAI22X1TS U6571 ( .A0(n5217), .A1(n5224), .B0(n5216), .B1(n5234), .Y(
DP_OP_169J43_123_4229_n1441) );
XNOR2X1TS U6572 ( .A(n5561), .B(n5231), .Y(n5218) );
OAI22X1TS U6573 ( .A0(n5218), .A1(n5224), .B0(n5217), .B1(n5234), .Y(
DP_OP_169J43_123_4229_n1442) );
XNOR2X1TS U6574 ( .A(n5563), .B(n5231), .Y(n5219) );
OAI22X1TS U6575 ( .A0(n5219), .A1(n5224), .B0(n5218), .B1(n5234), .Y(
DP_OP_169J43_123_4229_n1443) );
XNOR2X1TS U6576 ( .A(n5565), .B(n5231), .Y(n5220) );
OAI22X1TS U6577 ( .A0(n5220), .A1(n5224), .B0(n5219), .B1(n5234), .Y(
DP_OP_169J43_123_4229_n1444) );
XNOR2X1TS U6578 ( .A(n5567), .B(n5231), .Y(n5221) );
OAI22X1TS U6579 ( .A0(n5221), .A1(n5224), .B0(n5220), .B1(n5234), .Y(
DP_OP_169J43_123_4229_n1445) );
XNOR2X1TS U6580 ( .A(n5569), .B(n5231), .Y(n5222) );
OAI22X1TS U6581 ( .A0(n5221), .A1(n5242), .B0(n5222), .B1(n5240), .Y(
DP_OP_169J43_123_4229_n1446) );
XNOR2X1TS U6582 ( .A(n5571), .B(n5238), .Y(n5223) );
OAI22X1TS U6583 ( .A0(n5222), .A1(n5242), .B0(n5223), .B1(n5224), .Y(
DP_OP_169J43_123_4229_n1447) );
XNOR2X1TS U6584 ( .A(n5573), .B(n5238), .Y(n5225) );
OAI22X1TS U6585 ( .A0(n5225), .A1(n5224), .B0(n5223), .B1(n5234), .Y(
DP_OP_169J43_123_4229_n1448) );
XNOR2X1TS U6586 ( .A(n5575), .B(n5238), .Y(n5226) );
OAI22X1TS U6587 ( .A0(n5226), .A1(n5240), .B0(n5225), .B1(n5242), .Y(
DP_OP_169J43_123_4229_n1449) );
XNOR2X1TS U6588 ( .A(n5577), .B(n5231), .Y(n5227) );
OAI22X1TS U6589 ( .A0(n5227), .A1(n5240), .B0(n5226), .B1(n5234), .Y(
DP_OP_169J43_123_4229_n1450) );
XNOR2X1TS U6590 ( .A(n5579), .B(n5238), .Y(n5228) );
OAI22X1TS U6591 ( .A0(n5228), .A1(n5240), .B0(n5227), .B1(n5234), .Y(
DP_OP_169J43_123_4229_n1451) );
XNOR2X1TS U6592 ( .A(n5581), .B(n5238), .Y(n5229) );
OAI22X1TS U6593 ( .A0(n5229), .A1(n5240), .B0(n5228), .B1(n5234), .Y(
DP_OP_169J43_123_4229_n1452) );
XNOR2X1TS U6594 ( .A(n5583), .B(n5238), .Y(n5230) );
OAI22X1TS U6595 ( .A0(n5230), .A1(n5240), .B0(n5229), .B1(n5234), .Y(
DP_OP_169J43_123_4229_n1453) );
XNOR2X1TS U6596 ( .A(n5586), .B(n5231), .Y(n5232) );
OAI22X1TS U6597 ( .A0(n5230), .A1(n5242), .B0(n5232), .B1(n5240), .Y(
DP_OP_169J43_123_4229_n1454) );
XNOR2X1TS U6598 ( .A(n5589), .B(n5231), .Y(n5233) );
OAI22X1TS U6599 ( .A0(n5233), .A1(n5240), .B0(n5232), .B1(n5234), .Y(
DP_OP_169J43_123_4229_n1455) );
XNOR2X1TS U6600 ( .A(n5592), .B(n5238), .Y(n5235) );
OAI22X1TS U6601 ( .A0(n5233), .A1(n5242), .B0(n5235), .B1(n5240), .Y(
DP_OP_169J43_123_4229_n1456) );
XNOR2X1TS U6602 ( .A(n5536), .B(n5238), .Y(n5236) );
OAI22X1TS U6603 ( .A0(n5236), .A1(n5240), .B0(n5235), .B1(n5234), .Y(
DP_OP_169J43_123_4229_n1457) );
XNOR2X1TS U6604 ( .A(n5540), .B(n5238), .Y(n5237) );
OAI22X1TS U6605 ( .A0(n5236), .A1(n5242), .B0(n5237), .B1(n5240), .Y(
DP_OP_169J43_123_4229_n1458) );
XNOR2X1TS U6606 ( .A(n5502), .B(n5238), .Y(n5239) );
OAI22X1TS U6607 ( .A0(n5237), .A1(n5242), .B0(n5239), .B1(n5240), .Y(
DP_OP_169J43_123_4229_n1459) );
XNOR2X1TS U6608 ( .A(n5505), .B(n5238), .Y(n5243) );
OAI22X1TS U6609 ( .A0(n5239), .A1(n5242), .B0(n5243), .B1(n5240), .Y(
DP_OP_169J43_123_4229_n1460) );
OAI22X1TS U6610 ( .A0(n5243), .A1(n5242), .B0(n5241), .B1(n5240), .Y(
DP_OP_169J43_123_4229_n1461) );
XNOR2X1TS U6611 ( .A(n5549), .B(n5263), .Y(n5245) );
OAI22X1TS U6612 ( .A0(n5245), .A1(n5257), .B0(n5244), .B1(n5273), .Y(
DP_OP_169J43_123_4229_n1466) );
XNOR2X1TS U6613 ( .A(n5551), .B(n5263), .Y(n5246) );
BUFX4TS U6614 ( .A(n5275), .Y(n5267) );
OAI22X1TS U6615 ( .A0(n5246), .A1(n5257), .B0(n5245), .B1(n5267), .Y(
DP_OP_169J43_123_4229_n1467) );
XNOR2X1TS U6616 ( .A(n5553), .B(n5263), .Y(n5247) );
OAI22X1TS U6617 ( .A0(n5247), .A1(n5257), .B0(n5246), .B1(n5267), .Y(
DP_OP_169J43_123_4229_n1468) );
XNOR2X1TS U6618 ( .A(n5555), .B(n5263), .Y(n5248) );
OAI22X1TS U6619 ( .A0(n5248), .A1(n5257), .B0(n5247), .B1(n5273), .Y(
DP_OP_169J43_123_4229_n1469) );
XNOR2X1TS U6620 ( .A(n5557), .B(n5263), .Y(n5249) );
OAI22X1TS U6621 ( .A0(n5249), .A1(n5257), .B0(n5248), .B1(n5267), .Y(
DP_OP_169J43_123_4229_n1470) );
XNOR2X1TS U6622 ( .A(n5559), .B(n5263), .Y(n5250) );
OAI22X1TS U6623 ( .A0(n5250), .A1(n5257), .B0(n5249), .B1(n5267), .Y(
DP_OP_169J43_123_4229_n1471) );
XNOR2X1TS U6624 ( .A(n5561), .B(n5263), .Y(n5251) );
OAI22X1TS U6625 ( .A0(n5251), .A1(n5257), .B0(n5250), .B1(n5267), .Y(
DP_OP_169J43_123_4229_n1472) );
XNOR2X1TS U6626 ( .A(n5563), .B(n5263), .Y(n5252) );
OAI22X1TS U6627 ( .A0(n5252), .A1(n5257), .B0(n5251), .B1(n5267), .Y(
DP_OP_169J43_123_4229_n1473) );
XNOR2X1TS U6628 ( .A(n5565), .B(n5263), .Y(n5253) );
OAI22X1TS U6629 ( .A0(n5253), .A1(n5257), .B0(n5252), .B1(n5267), .Y(
DP_OP_169J43_123_4229_n1474) );
XNOR2X1TS U6630 ( .A(n5567), .B(n5263), .Y(n5254) );
OAI22X1TS U6631 ( .A0(n5254), .A1(n5257), .B0(n5253), .B1(n5267), .Y(
DP_OP_169J43_123_4229_n1475) );
XNOR2X1TS U6632 ( .A(n5569), .B(n5263), .Y(n5255) );
OAI22X1TS U6633 ( .A0(n5254), .A1(n5273), .B0(n5255), .B1(n5271), .Y(
DP_OP_169J43_123_4229_n1476) );
XNOR2X1TS U6634 ( .A(n5571), .B(n5269), .Y(n5256) );
OAI22X1TS U6635 ( .A0(n5255), .A1(n5273), .B0(n5256), .B1(n5257), .Y(
DP_OP_169J43_123_4229_n1477) );
XNOR2X1TS U6636 ( .A(n5573), .B(n5269), .Y(n5258) );
OAI22X1TS U6637 ( .A0(n5258), .A1(n5257), .B0(n5256), .B1(n5267), .Y(
DP_OP_169J43_123_4229_n1478) );
XNOR2X1TS U6638 ( .A(n5575), .B(n5269), .Y(n5259) );
OAI22X1TS U6639 ( .A0(n5259), .A1(n5271), .B0(n5258), .B1(n5273), .Y(
DP_OP_169J43_123_4229_n1479) );
XNOR2X1TS U6640 ( .A(n5577), .B(n5263), .Y(n5260) );
OAI22X1TS U6641 ( .A0(n5260), .A1(n5271), .B0(n5259), .B1(n5267), .Y(
DP_OP_169J43_123_4229_n1480) );
XNOR2X1TS U6642 ( .A(n5579), .B(n5269), .Y(n5261) );
OAI22X1TS U6643 ( .A0(n5261), .A1(n5271), .B0(n5260), .B1(n5267), .Y(
DP_OP_169J43_123_4229_n1481) );
XNOR2X1TS U6644 ( .A(n5581), .B(n5269), .Y(n5262) );
OAI22X1TS U6645 ( .A0(n5262), .A1(n5271), .B0(n5261), .B1(n5267), .Y(
DP_OP_169J43_123_4229_n1482) );
XNOR2X1TS U6646 ( .A(n5583), .B(n5263), .Y(n5264) );
OAI22X1TS U6647 ( .A0(n5264), .A1(n5271), .B0(n5262), .B1(n5267), .Y(
DP_OP_169J43_123_4229_n1483) );
XNOR2X1TS U6648 ( .A(n5586), .B(n5263), .Y(n5265) );
OAI22X1TS U6649 ( .A0(n5264), .A1(n5273), .B0(n5265), .B1(n5271), .Y(
DP_OP_169J43_123_4229_n1484) );
XNOR2X1TS U6650 ( .A(n5589), .B(n5269), .Y(n5266) );
OAI22X1TS U6651 ( .A0(n5266), .A1(n5271), .B0(n5265), .B1(n5267), .Y(
DP_OP_169J43_123_4229_n1485) );
XNOR2X1TS U6652 ( .A(n5592), .B(n5269), .Y(n5268) );
OAI22X1TS U6653 ( .A0(n5266), .A1(n5273), .B0(n5268), .B1(n5271), .Y(
DP_OP_169J43_123_4229_n1486) );
XNOR2X1TS U6654 ( .A(n5536), .B(n5269), .Y(n5270) );
OAI22X1TS U6655 ( .A0(n5270), .A1(n5271), .B0(n5268), .B1(n5267), .Y(
DP_OP_169J43_123_4229_n1487) );
XNOR2X1TS U6656 ( .A(n5540), .B(n5269), .Y(n5274) );
OAI22X1TS U6657 ( .A0(n5270), .A1(n5273), .B0(n5274), .B1(n5271), .Y(
DP_OP_169J43_123_4229_n1488) );
OAI22X1TS U6658 ( .A0(n5274), .A1(n5273), .B0(n5272), .B1(n5271), .Y(
DP_OP_169J43_123_4229_n1489) );
NOR2BX1TS U6659 ( .AN(n5475), .B(n5275), .Y(DP_OP_169J43_123_4229_n1493) );
XNOR2X1TS U6660 ( .A(n5547), .B(n5304), .Y(n5276) );
OAI22X1TS U6661 ( .A0(n5276), .A1(n5290), .B0(n5308), .B1(n811), .Y(
DP_OP_169J43_123_4229_n1495) );
XNOR2X1TS U6662 ( .A(n5549), .B(n5296), .Y(n5278) );
OAI22X1TS U6663 ( .A0(n5278), .A1(n5290), .B0(n5276), .B1(n5308), .Y(
DP_OP_169J43_123_4229_n1496) );
XNOR2X1TS U6664 ( .A(n5551), .B(n5296), .Y(n5279) );
BUFX4TS U6665 ( .A(n5277), .Y(n5300) );
OAI22X1TS U6666 ( .A0(n5279), .A1(n5290), .B0(n5278), .B1(n5300), .Y(
DP_OP_169J43_123_4229_n1497) );
XNOR2X1TS U6667 ( .A(n5553), .B(n5296), .Y(n5280) );
OAI22X1TS U6668 ( .A0(n5280), .A1(n5290), .B0(n5279), .B1(n5300), .Y(
DP_OP_169J43_123_4229_n1498) );
XNOR2X1TS U6669 ( .A(n5555), .B(n5296), .Y(n5281) );
OAI22X1TS U6670 ( .A0(n5281), .A1(n5290), .B0(n5280), .B1(n5308), .Y(
DP_OP_169J43_123_4229_n1499) );
XNOR2X1TS U6671 ( .A(n5557), .B(n5296), .Y(n5282) );
OAI22X1TS U6672 ( .A0(n5282), .A1(n5290), .B0(n5281), .B1(n5300), .Y(
DP_OP_169J43_123_4229_n1500) );
XNOR2X1TS U6673 ( .A(n5559), .B(n5296), .Y(n5283) );
OAI22X1TS U6674 ( .A0(n5283), .A1(n5290), .B0(n5282), .B1(n5300), .Y(
DP_OP_169J43_123_4229_n1501) );
XNOR2X1TS U6675 ( .A(n5561), .B(n5296), .Y(n5284) );
OAI22X1TS U6676 ( .A0(n5284), .A1(n5290), .B0(n5283), .B1(n5300), .Y(
DP_OP_169J43_123_4229_n1502) );
XNOR2X1TS U6677 ( .A(n5563), .B(n5296), .Y(n5285) );
OAI22X1TS U6678 ( .A0(n5285), .A1(n5290), .B0(n5284), .B1(n5300), .Y(
DP_OP_169J43_123_4229_n1503) );
XNOR2X1TS U6679 ( .A(n5565), .B(n5296), .Y(n5286) );
OAI22X1TS U6680 ( .A0(n5286), .A1(n5290), .B0(n5285), .B1(n5300), .Y(
DP_OP_169J43_123_4229_n1504) );
XNOR2X1TS U6681 ( .A(n5567), .B(n5296), .Y(n5287) );
OAI22X1TS U6682 ( .A0(n5287), .A1(n5290), .B0(n5286), .B1(n5300), .Y(
DP_OP_169J43_123_4229_n1505) );
XNOR2X1TS U6683 ( .A(n5569), .B(n5296), .Y(n5288) );
OAI22X1TS U6684 ( .A0(n5287), .A1(n5308), .B0(n5288), .B1(n5306), .Y(
DP_OP_169J43_123_4229_n1506) );
XNOR2X1TS U6685 ( .A(n5571), .B(n5304), .Y(n5289) );
OAI22X1TS U6686 ( .A0(n5288), .A1(n5308), .B0(n5289), .B1(n5290), .Y(
DP_OP_169J43_123_4229_n1507) );
XNOR2X1TS U6687 ( .A(n5573), .B(n5304), .Y(n5291) );
OAI22X1TS U6688 ( .A0(n5291), .A1(n5290), .B0(n5289), .B1(n5300), .Y(
DP_OP_169J43_123_4229_n1508) );
XNOR2X1TS U6689 ( .A(n5575), .B(n5304), .Y(n5292) );
OAI22X1TS U6690 ( .A0(n5292), .A1(n5306), .B0(n5291), .B1(n5308), .Y(
DP_OP_169J43_123_4229_n1509) );
XNOR2X1TS U6691 ( .A(n5577), .B(n5296), .Y(n5293) );
OAI22X1TS U6692 ( .A0(n5293), .A1(n5306), .B0(n5292), .B1(n5300), .Y(
DP_OP_169J43_123_4229_n1510) );
XNOR2X1TS U6693 ( .A(n5579), .B(n5304), .Y(n5294) );
OAI22X1TS U6694 ( .A0(n5294), .A1(n5306), .B0(n5293), .B1(n5300), .Y(
DP_OP_169J43_123_4229_n1511) );
XNOR2X1TS U6695 ( .A(n5581), .B(n5304), .Y(n5295) );
OAI22X1TS U6696 ( .A0(n5295), .A1(n5306), .B0(n5294), .B1(n5300), .Y(
DP_OP_169J43_123_4229_n1512) );
XNOR2X1TS U6697 ( .A(n5583), .B(n5296), .Y(n5297) );
OAI22X1TS U6698 ( .A0(n5297), .A1(n5306), .B0(n5295), .B1(n5300), .Y(
DP_OP_169J43_123_4229_n1513) );
XNOR2X1TS U6699 ( .A(n5586), .B(n5296), .Y(n5298) );
OAI22X1TS U6700 ( .A0(n5297), .A1(n5308), .B0(n5298), .B1(n5306), .Y(
DP_OP_169J43_123_4229_n1514) );
XNOR2X1TS U6701 ( .A(n5589), .B(n5304), .Y(n5299) );
OAI22X1TS U6702 ( .A0(n5299), .A1(n5306), .B0(n5298), .B1(n5300), .Y(
DP_OP_169J43_123_4229_n1515) );
XNOR2X1TS U6703 ( .A(n5592), .B(n5304), .Y(n5301) );
OAI22X1TS U6704 ( .A0(n5299), .A1(n5308), .B0(n5301), .B1(n5306), .Y(
DP_OP_169J43_123_4229_n1516) );
XNOR2X1TS U6705 ( .A(n5536), .B(n5304), .Y(n5302) );
OAI22X1TS U6706 ( .A0(n5302), .A1(n5306), .B0(n5301), .B1(n5300), .Y(
DP_OP_169J43_123_4229_n1517) );
XNOR2X1TS U6707 ( .A(n5540), .B(n5304), .Y(n5303) );
OAI22X1TS U6708 ( .A0(n5302), .A1(n5308), .B0(n5303), .B1(n5306), .Y(
DP_OP_169J43_123_4229_n1518) );
XNOR2X1TS U6709 ( .A(n5502), .B(n5304), .Y(n5305) );
OAI22X1TS U6710 ( .A0(n5303), .A1(n5308), .B0(n5305), .B1(n5306), .Y(
DP_OP_169J43_123_4229_n1519) );
XNOR2X1TS U6711 ( .A(n5505), .B(n5304), .Y(n5309) );
OAI22X1TS U6712 ( .A0(n5305), .A1(n5308), .B0(n5309), .B1(n5306), .Y(
DP_OP_169J43_123_4229_n1520) );
OAI22X1TS U6713 ( .A0(n5309), .A1(n5308), .B0(n5307), .B1(n5306), .Y(
DP_OP_169J43_123_4229_n1521) );
XNOR2X1TS U6714 ( .A(n5549), .B(n5330), .Y(n5311) );
OAI22X1TS U6715 ( .A0(n5311), .A1(n5328), .B0(n5310), .B1(n5339), .Y(
DP_OP_169J43_123_4229_n1526) );
XNOR2X1TS U6716 ( .A(n5551), .B(n5330), .Y(n5312) );
OAI22X1TS U6717 ( .A0(n5312), .A1(n5328), .B0(n5311), .B1(n5333), .Y(
DP_OP_169J43_123_4229_n1527) );
XNOR2X1TS U6718 ( .A(n5553), .B(n5330), .Y(n5313) );
OAI22X1TS U6719 ( .A0(n5313), .A1(n5328), .B0(n5312), .B1(n5333), .Y(
DP_OP_169J43_123_4229_n1528) );
XNOR2X1TS U6720 ( .A(n5555), .B(n5330), .Y(n5314) );
OAI22X1TS U6721 ( .A0(n5314), .A1(n5337), .B0(n5313), .B1(n5339), .Y(
DP_OP_169J43_123_4229_n1529) );
XNOR2X1TS U6722 ( .A(n5557), .B(n5330), .Y(n5315) );
OAI22X1TS U6723 ( .A0(n5315), .A1(n5328), .B0(n5314), .B1(n5339), .Y(
DP_OP_169J43_123_4229_n1530) );
XNOR2X1TS U6724 ( .A(n5559), .B(n5330), .Y(n5316) );
OAI22X1TS U6725 ( .A0(n5316), .A1(n5328), .B0(n5315), .B1(n5333), .Y(
DP_OP_169J43_123_4229_n1531) );
XNOR2X1TS U6726 ( .A(n5561), .B(n5330), .Y(n5317) );
OAI22X1TS U6727 ( .A0(n5317), .A1(n5328), .B0(n5316), .B1(n5333), .Y(
DP_OP_169J43_123_4229_n1532) );
XNOR2X1TS U6728 ( .A(n5563), .B(n5330), .Y(n5318) );
OAI22X1TS U6729 ( .A0(n5318), .A1(n5328), .B0(n5317), .B1(n5333), .Y(
DP_OP_169J43_123_4229_n1533) );
XNOR2X1TS U6730 ( .A(n5565), .B(n5330), .Y(n5319) );
OAI22X1TS U6731 ( .A0(n5319), .A1(n5328), .B0(n5318), .B1(n5333), .Y(
DP_OP_169J43_123_4229_n1534) );
XNOR2X1TS U6732 ( .A(n5567), .B(n5330), .Y(n5320) );
OAI22X1TS U6733 ( .A0(n5320), .A1(n5328), .B0(n5319), .B1(n5333), .Y(
DP_OP_169J43_123_4229_n1535) );
XNOR2X1TS U6734 ( .A(n5569), .B(n5330), .Y(n5321) );
OAI22X1TS U6735 ( .A0(n5320), .A1(n5339), .B0(n5321), .B1(n5337), .Y(
DP_OP_169J43_123_4229_n1536) );
XNOR2X1TS U6736 ( .A(n5571), .B(n5335), .Y(n5322) );
OAI22X1TS U6737 ( .A0(n5321), .A1(n5339), .B0(n5322), .B1(n5328), .Y(
DP_OP_169J43_123_4229_n1537) );
XNOR2X1TS U6738 ( .A(n5573), .B(n5335), .Y(n5323) );
OAI22X1TS U6739 ( .A0(n5323), .A1(n5328), .B0(n5322), .B1(n5333), .Y(
DP_OP_169J43_123_4229_n1538) );
XNOR2X1TS U6740 ( .A(n5575), .B(n5335), .Y(n5324) );
OAI22X1TS U6741 ( .A0(n5324), .A1(n5337), .B0(n5323), .B1(n5339), .Y(
DP_OP_169J43_123_4229_n1539) );
XNOR2X1TS U6742 ( .A(n5577), .B(n5330), .Y(n5325) );
OAI22X1TS U6743 ( .A0(n5325), .A1(n5337), .B0(n5324), .B1(n5333), .Y(
DP_OP_169J43_123_4229_n1540) );
XNOR2X1TS U6744 ( .A(n5579), .B(n5335), .Y(n5326) );
OAI22X1TS U6745 ( .A0(n5326), .A1(n5337), .B0(n5325), .B1(n5333), .Y(
DP_OP_169J43_123_4229_n1541) );
XNOR2X1TS U6746 ( .A(n5581), .B(n5335), .Y(n5327) );
OAI22X1TS U6747 ( .A0(n5327), .A1(n5337), .B0(n5326), .B1(n5333), .Y(
DP_OP_169J43_123_4229_n1542) );
XNOR2X1TS U6748 ( .A(n5583), .B(n5335), .Y(n5329) );
OAI22X1TS U6749 ( .A0(n5329), .A1(n5337), .B0(n5327), .B1(n5333), .Y(
DP_OP_169J43_123_4229_n1543) );
XNOR2X1TS U6750 ( .A(n5586), .B(n5330), .Y(n5331) );
OAI22X1TS U6751 ( .A0(n5329), .A1(n5339), .B0(n5331), .B1(n5328), .Y(
DP_OP_169J43_123_4229_n1544) );
XNOR2X1TS U6752 ( .A(n5589), .B(n5330), .Y(n5332) );
OAI22X1TS U6753 ( .A0(n5332), .A1(n5337), .B0(n5331), .B1(n5333), .Y(
DP_OP_169J43_123_4229_n1545) );
XNOR2X1TS U6754 ( .A(n5592), .B(n5335), .Y(n5334) );
OAI22X1TS U6755 ( .A0(n5332), .A1(n5339), .B0(n5334), .B1(n5337), .Y(
DP_OP_169J43_123_4229_n1546) );
XNOR2X1TS U6756 ( .A(n5536), .B(n5335), .Y(n5336) );
OAI22X1TS U6757 ( .A0(n5336), .A1(n5337), .B0(n5334), .B1(n5333), .Y(
DP_OP_169J43_123_4229_n1547) );
XNOR2X1TS U6758 ( .A(n5540), .B(n5335), .Y(n5340) );
OAI22X1TS U6759 ( .A0(n5336), .A1(n5339), .B0(n5340), .B1(n5337), .Y(
DP_OP_169J43_123_4229_n1548) );
OAI22X1TS U6760 ( .A0(n5340), .A1(n5339), .B0(n5338), .B1(n5337), .Y(
DP_OP_169J43_123_4229_n1549) );
NOR2BX1TS U6761 ( .AN(n5475), .B(n5341), .Y(DP_OP_169J43_123_4229_n1553) );
XNOR2X1TS U6762 ( .A(n5547), .B(n5370), .Y(n5342) );
OAI22X1TS U6763 ( .A0(n5342), .A1(n5361), .B0(n5374), .B1(n897), .Y(
DP_OP_169J43_123_4229_n1555) );
XNOR2X1TS U6764 ( .A(n5549), .B(n5363), .Y(n5344) );
OAI22X1TS U6765 ( .A0(n5344), .A1(n5361), .B0(n5342), .B1(n5374), .Y(
DP_OP_169J43_123_4229_n1556) );
XNOR2X1TS U6766 ( .A(n5551), .B(n5363), .Y(n5345) );
BUFX4TS U6767 ( .A(n5343), .Y(n5366) );
OAI22X1TS U6768 ( .A0(n5345), .A1(n5361), .B0(n5344), .B1(n5366), .Y(
DP_OP_169J43_123_4229_n1557) );
XNOR2X1TS U6769 ( .A(n5553), .B(n5363), .Y(n5346) );
OAI22X1TS U6770 ( .A0(n5346), .A1(n5361), .B0(n5345), .B1(n5366), .Y(
DP_OP_169J43_123_4229_n1558) );
XNOR2X1TS U6771 ( .A(n5555), .B(n5363), .Y(n5347) );
OAI22X1TS U6772 ( .A0(n5347), .A1(n5361), .B0(n5346), .B1(n5374), .Y(
DP_OP_169J43_123_4229_n1559) );
XNOR2X1TS U6773 ( .A(n5557), .B(n5363), .Y(n5348) );
OAI22X1TS U6774 ( .A0(n5348), .A1(n5361), .B0(n5347), .B1(n5366), .Y(
DP_OP_169J43_123_4229_n1560) );
XNOR2X1TS U6775 ( .A(n5559), .B(n5363), .Y(n5349) );
OAI22X1TS U6776 ( .A0(n5349), .A1(n5361), .B0(n5348), .B1(n5366), .Y(
DP_OP_169J43_123_4229_n1561) );
XNOR2X1TS U6777 ( .A(n5561), .B(n5363), .Y(n5350) );
OAI22X1TS U6778 ( .A0(n5350), .A1(n5361), .B0(n5349), .B1(n5366), .Y(
DP_OP_169J43_123_4229_n1562) );
XNOR2X1TS U6779 ( .A(n5563), .B(n5363), .Y(n5351) );
OAI22X1TS U6780 ( .A0(n5351), .A1(n5361), .B0(n5350), .B1(n5366), .Y(
DP_OP_169J43_123_4229_n1563) );
XNOR2X1TS U6781 ( .A(n5565), .B(n5363), .Y(n5352) );
OAI22X1TS U6782 ( .A0(n5352), .A1(n5361), .B0(n5351), .B1(n5366), .Y(
DP_OP_169J43_123_4229_n1564) );
XNOR2X1TS U6783 ( .A(n5567), .B(n5363), .Y(n5353) );
OAI22X1TS U6784 ( .A0(n5353), .A1(n5361), .B0(n5352), .B1(n5366), .Y(
DP_OP_169J43_123_4229_n1565) );
XNOR2X1TS U6785 ( .A(n5569), .B(n5363), .Y(n5354) );
OAI22X1TS U6786 ( .A0(n5353), .A1(n5374), .B0(n5354), .B1(n5372), .Y(
DP_OP_169J43_123_4229_n1566) );
XNOR2X1TS U6787 ( .A(n5571), .B(n5370), .Y(n5355) );
OAI22X1TS U6788 ( .A0(n5354), .A1(n5374), .B0(n5355), .B1(n5361), .Y(
DP_OP_169J43_123_4229_n1567) );
XNOR2X1TS U6789 ( .A(n5573), .B(n5370), .Y(n5356) );
OAI22X1TS U6790 ( .A0(n5356), .A1(n5361), .B0(n5355), .B1(n5366), .Y(
DP_OP_169J43_123_4229_n1568) );
XNOR2X1TS U6791 ( .A(n5575), .B(n5370), .Y(n5357) );
OAI22X1TS U6792 ( .A0(n5357), .A1(n5372), .B0(n5356), .B1(n5374), .Y(
DP_OP_169J43_123_4229_n1569) );
XNOR2X1TS U6793 ( .A(n5577), .B(n5363), .Y(n5358) );
OAI22X1TS U6794 ( .A0(n5358), .A1(n5372), .B0(n5357), .B1(n5366), .Y(
DP_OP_169J43_123_4229_n1570) );
XNOR2X1TS U6795 ( .A(n5579), .B(n5370), .Y(n5359) );
OAI22X1TS U6796 ( .A0(n5359), .A1(n5372), .B0(n5358), .B1(n5366), .Y(
DP_OP_169J43_123_4229_n1571) );
XNOR2X1TS U6797 ( .A(n5581), .B(n5370), .Y(n5360) );
OAI22X1TS U6798 ( .A0(n5360), .A1(n5372), .B0(n5359), .B1(n5366), .Y(
DP_OP_169J43_123_4229_n1572) );
XNOR2X1TS U6799 ( .A(n5583), .B(n5370), .Y(n5362) );
OAI22X1TS U6800 ( .A0(n5362), .A1(n5372), .B0(n5360), .B1(n5366), .Y(
DP_OP_169J43_123_4229_n1573) );
XNOR2X1TS U6801 ( .A(n5586), .B(n5363), .Y(n5364) );
OAI22X1TS U6802 ( .A0(n5362), .A1(n5374), .B0(n5364), .B1(n5361), .Y(
DP_OP_169J43_123_4229_n1574) );
XNOR2X1TS U6803 ( .A(n5589), .B(n5363), .Y(n5365) );
OAI22X1TS U6804 ( .A0(n5365), .A1(n5372), .B0(n5364), .B1(n5366), .Y(
DP_OP_169J43_123_4229_n1575) );
XNOR2X1TS U6805 ( .A(n5592), .B(n5370), .Y(n5367) );
OAI22X1TS U6806 ( .A0(n5365), .A1(n5374), .B0(n5367), .B1(n5372), .Y(
DP_OP_169J43_123_4229_n1576) );
XNOR2X1TS U6807 ( .A(n5536), .B(n5370), .Y(n5368) );
OAI22X1TS U6808 ( .A0(n5368), .A1(n5372), .B0(n5367), .B1(n5366), .Y(
DP_OP_169J43_123_4229_n1577) );
XNOR2X1TS U6809 ( .A(n5540), .B(n5370), .Y(n5369) );
OAI22X1TS U6810 ( .A0(n5368), .A1(n5374), .B0(n5369), .B1(n5372), .Y(
DP_OP_169J43_123_4229_n1578) );
XNOR2X1TS U6811 ( .A(n5502), .B(n5370), .Y(n5371) );
OAI22X1TS U6812 ( .A0(n5369), .A1(n5374), .B0(n5371), .B1(n5372), .Y(
DP_OP_169J43_123_4229_n1579) );
XNOR2X1TS U6813 ( .A(n5505), .B(n5370), .Y(n5375) );
OAI22X1TS U6814 ( .A0(n5371), .A1(n5374), .B0(n5375), .B1(n5372), .Y(
DP_OP_169J43_123_4229_n1580) );
OAI22X1TS U6815 ( .A0(n5375), .A1(n5374), .B0(n5373), .B1(n5372), .Y(
DP_OP_169J43_123_4229_n1581) );
XNOR2X1TS U6816 ( .A(n5547), .B(n5401), .Y(n5376) );
OAI22X1TS U6817 ( .A0(n5376), .A1(n5389), .B0(n5405), .B1(n889), .Y(
DP_OP_169J43_123_4229_n1585) );
XNOR2X1TS U6818 ( .A(n5549), .B(n5396), .Y(n5377) );
OAI22X1TS U6819 ( .A0(n5377), .A1(n5389), .B0(n5376), .B1(n5405), .Y(
DP_OP_169J43_123_4229_n1586) );
XNOR2X1TS U6820 ( .A(n5551), .B(n5396), .Y(n5378) );
BUFX4TS U6821 ( .A(n5407), .Y(n5399) );
OAI22X1TS U6822 ( .A0(n5378), .A1(n5389), .B0(n5377), .B1(n5399), .Y(
DP_OP_169J43_123_4229_n1587) );
XNOR2X1TS U6823 ( .A(n5553), .B(n5396), .Y(n5379) );
OAI22X1TS U6824 ( .A0(n5379), .A1(n5389), .B0(n5378), .B1(n5399), .Y(
DP_OP_169J43_123_4229_n1588) );
XNOR2X1TS U6825 ( .A(n5555), .B(n5396), .Y(n5380) );
OAI22X1TS U6826 ( .A0(n5380), .A1(n5389), .B0(n5379), .B1(n5405), .Y(
DP_OP_169J43_123_4229_n1589) );
XNOR2X1TS U6827 ( .A(n5557), .B(n5396), .Y(n5381) );
OAI22X1TS U6828 ( .A0(n5381), .A1(n5389), .B0(n5380), .B1(n5399), .Y(
DP_OP_169J43_123_4229_n1590) );
XNOR2X1TS U6829 ( .A(n5559), .B(n5396), .Y(n5382) );
OAI22X1TS U6830 ( .A0(n5382), .A1(n5389), .B0(n5381), .B1(n5399), .Y(
DP_OP_169J43_123_4229_n1591) );
XNOR2X1TS U6831 ( .A(n5561), .B(n5396), .Y(n5383) );
OAI22X1TS U6832 ( .A0(n5383), .A1(n5389), .B0(n5382), .B1(n5399), .Y(
DP_OP_169J43_123_4229_n1592) );
XNOR2X1TS U6833 ( .A(n5563), .B(n5396), .Y(n5384) );
OAI22X1TS U6834 ( .A0(n5384), .A1(n5389), .B0(n5383), .B1(n5399), .Y(
DP_OP_169J43_123_4229_n1593) );
OAI22X1TS U6835 ( .A0(n5385), .A1(n5389), .B0(n5384), .B1(n5399), .Y(
DP_OP_169J43_123_4229_n1594) );
XNOR2X1TS U6836 ( .A(n5567), .B(n5396), .Y(n5386) );
OAI22X1TS U6837 ( .A0(n5386), .A1(n5389), .B0(n5385), .B1(n5399), .Y(
DP_OP_169J43_123_4229_n1595) );
XNOR2X1TS U6838 ( .A(n5569), .B(n5396), .Y(n5387) );
OAI22X1TS U6839 ( .A0(n5386), .A1(n5405), .B0(n5387), .B1(n5403), .Y(
DP_OP_169J43_123_4229_n1596) );
XNOR2X1TS U6840 ( .A(n5571), .B(n5401), .Y(n5388) );
OAI22X1TS U6841 ( .A0(n5387), .A1(n5405), .B0(n5388), .B1(n5403), .Y(
DP_OP_169J43_123_4229_n1597) );
XNOR2X1TS U6842 ( .A(n5573), .B(n5401), .Y(n5390) );
OAI22X1TS U6843 ( .A0(n5390), .A1(n5389), .B0(n5388), .B1(n5399), .Y(
DP_OP_169J43_123_4229_n1598) );
XNOR2X1TS U6844 ( .A(n5575), .B(n5401), .Y(n5391) );
OAI22X1TS U6845 ( .A0(n5391), .A1(n5403), .B0(n5390), .B1(n5405), .Y(
DP_OP_169J43_123_4229_n1599) );
XNOR2X1TS U6846 ( .A(n5577), .B(n5396), .Y(n5392) );
OAI22X1TS U6847 ( .A0(n5392), .A1(n5403), .B0(n5391), .B1(n5399), .Y(
DP_OP_169J43_123_4229_n1600) );
XNOR2X1TS U6848 ( .A(n5579), .B(n5401), .Y(n5393) );
OAI22X1TS U6849 ( .A0(n5393), .A1(n5403), .B0(n5392), .B1(n5399), .Y(
DP_OP_169J43_123_4229_n1601) );
XNOR2X1TS U6850 ( .A(n5581), .B(n5401), .Y(n5394) );
OAI22X1TS U6851 ( .A0(n5394), .A1(n5403), .B0(n5393), .B1(n5399), .Y(
DP_OP_169J43_123_4229_n1602) );
XNOR2X1TS U6852 ( .A(n5583), .B(n5401), .Y(n5395) );
OAI22X1TS U6853 ( .A0(n5395), .A1(n5403), .B0(n5394), .B1(n5399), .Y(
DP_OP_169J43_123_4229_n1603) );
XNOR2X1TS U6854 ( .A(n5586), .B(n5396), .Y(n5397) );
OAI22X1TS U6855 ( .A0(n5395), .A1(n5405), .B0(n5397), .B1(n5403), .Y(
DP_OP_169J43_123_4229_n1604) );
XNOR2X1TS U6856 ( .A(n5589), .B(n5396), .Y(n5398) );
OAI22X1TS U6857 ( .A0(n5398), .A1(n5403), .B0(n5397), .B1(n5399), .Y(
DP_OP_169J43_123_4229_n1605) );
XNOR2X1TS U6858 ( .A(n5592), .B(n5401), .Y(n5400) );
OAI22X1TS U6859 ( .A0(n5398), .A1(n5405), .B0(n5400), .B1(n5403), .Y(
DP_OP_169J43_123_4229_n1606) );
XNOR2X1TS U6860 ( .A(n5536), .B(n5401), .Y(n5402) );
OAI22X1TS U6861 ( .A0(n5402), .A1(n5403), .B0(n5400), .B1(n5399), .Y(
DP_OP_169J43_123_4229_n1607) );
XNOR2X1TS U6862 ( .A(n5540), .B(n5401), .Y(n5406) );
OAI22X1TS U6863 ( .A0(n5402), .A1(n5405), .B0(n5406), .B1(n5403), .Y(
DP_OP_169J43_123_4229_n1608) );
OAI22X1TS U6864 ( .A0(n5406), .A1(n5405), .B0(n5404), .B1(n5403), .Y(
DP_OP_169J43_123_4229_n1609) );
NOR2BX1TS U6865 ( .AN(n5475), .B(n5407), .Y(DP_OP_169J43_123_4229_n1613) );
XNOR2X1TS U6866 ( .A(n5547), .B(n5437), .Y(n5409) );
OAI22X1TS U6867 ( .A0(n5409), .A1(n5423), .B0(n5441), .B1(n761), .Y(
DP_OP_169J43_123_4229_n1615) );
XNOR2X1TS U6868 ( .A(n5549), .B(n5430), .Y(n5410) );
OAI22X1TS U6869 ( .A0(n5410), .A1(n5423), .B0(n5409), .B1(n5441), .Y(
DP_OP_169J43_123_4229_n1616) );
XNOR2X1TS U6870 ( .A(n5551), .B(n5430), .Y(n5411) );
OAI22X1TS U6871 ( .A0(n5411), .A1(n5423), .B0(n5410), .B1(n5433), .Y(
DP_OP_169J43_123_4229_n1617) );
XNOR2X1TS U6872 ( .A(n5553), .B(n5430), .Y(n5413) );
OAI22X1TS U6873 ( .A0(n5413), .A1(n5423), .B0(n5411), .B1(n5433), .Y(
DP_OP_169J43_123_4229_n1618) );
XNOR2X1TS U6874 ( .A(n5555), .B(n5430), .Y(n5414) );
BUFX4TS U6875 ( .A(n5412), .Y(n5439) );
OAI22X1TS U6876 ( .A0(n5414), .A1(n5439), .B0(n5413), .B1(n5441), .Y(
DP_OP_169J43_123_4229_n1619) );
XNOR2X1TS U6877 ( .A(n5557), .B(n5430), .Y(n5415) );
OAI22X1TS U6878 ( .A0(n5415), .A1(n5423), .B0(n5414), .B1(n5441), .Y(
DP_OP_169J43_123_4229_n1620) );
XNOR2X1TS U6879 ( .A(n5559), .B(n5430), .Y(n5416) );
OAI22X1TS U6880 ( .A0(n5416), .A1(n5423), .B0(n5415), .B1(n5433), .Y(
DP_OP_169J43_123_4229_n1621) );
XNOR2X1TS U6881 ( .A(n5561), .B(n5430), .Y(n5417) );
OAI22X1TS U6882 ( .A0(n5417), .A1(n5423), .B0(n5416), .B1(n5433), .Y(
DP_OP_169J43_123_4229_n1622) );
XNOR2X1TS U6883 ( .A(n5563), .B(n5430), .Y(n5418) );
OAI22X1TS U6884 ( .A0(n5418), .A1(n5423), .B0(n5417), .B1(n5433), .Y(
DP_OP_169J43_123_4229_n1623) );
XNOR2X1TS U6885 ( .A(n5565), .B(n5430), .Y(n5419) );
OAI22X1TS U6886 ( .A0(n5419), .A1(n5423), .B0(n5418), .B1(n5433), .Y(
DP_OP_169J43_123_4229_n1624) );
XNOR2X1TS U6887 ( .A(n5567), .B(n5430), .Y(n5420) );
OAI22X1TS U6888 ( .A0(n5420), .A1(n5423), .B0(n5419), .B1(n5433), .Y(
DP_OP_169J43_123_4229_n1625) );
XNOR2X1TS U6889 ( .A(n5569), .B(n5430), .Y(n5421) );
OAI22X1TS U6890 ( .A0(n5420), .A1(n5441), .B0(n5421), .B1(n5439), .Y(
DP_OP_169J43_123_4229_n1626) );
XNOR2X1TS U6891 ( .A(n5571), .B(n5437), .Y(n5422) );
OAI22X1TS U6892 ( .A0(n5421), .A1(n5441), .B0(n5422), .B1(n5423), .Y(
DP_OP_169J43_123_4229_n1627) );
XNOR2X1TS U6893 ( .A(n5573), .B(n5437), .Y(n5424) );
OAI22X1TS U6894 ( .A0(n5424), .A1(n5423), .B0(n5422), .B1(n5433), .Y(
DP_OP_169J43_123_4229_n1628) );
XNOR2X1TS U6895 ( .A(n5575), .B(n5437), .Y(n5425) );
OAI22X1TS U6896 ( .A0(n5425), .A1(n5439), .B0(n5424), .B1(n5441), .Y(
DP_OP_169J43_123_4229_n1629) );
XNOR2X1TS U6897 ( .A(n5577), .B(n5430), .Y(n5426) );
OAI22X1TS U6898 ( .A0(n5426), .A1(n5439), .B0(n5425), .B1(n5433), .Y(
DP_OP_169J43_123_4229_n1630) );
XNOR2X1TS U6899 ( .A(n5579), .B(n5437), .Y(n5427) );
OAI22X1TS U6900 ( .A0(n5427), .A1(n5439), .B0(n5426), .B1(n5433), .Y(
DP_OP_169J43_123_4229_n1631) );
XNOR2X1TS U6901 ( .A(n5581), .B(n5437), .Y(n5428) );
OAI22X1TS U6902 ( .A0(n5428), .A1(n5439), .B0(n5427), .B1(n5433), .Y(
DP_OP_169J43_123_4229_n1632) );
XNOR2X1TS U6903 ( .A(n5583), .B(n5430), .Y(n5429) );
OAI22X1TS U6904 ( .A0(n5429), .A1(n5439), .B0(n5428), .B1(n5433), .Y(
DP_OP_169J43_123_4229_n1633) );
XNOR2X1TS U6905 ( .A(n5586), .B(n5430), .Y(n5431) );
OAI22X1TS U6906 ( .A0(n5429), .A1(n5441), .B0(n5431), .B1(n5439), .Y(
DP_OP_169J43_123_4229_n1634) );
XNOR2X1TS U6907 ( .A(n5589), .B(n5430), .Y(n5432) );
OAI22X1TS U6908 ( .A0(n5432), .A1(n5439), .B0(n5431), .B1(n5433), .Y(
DP_OP_169J43_123_4229_n1635) );
XNOR2X1TS U6909 ( .A(n5592), .B(n5437), .Y(n5434) );
OAI22X1TS U6910 ( .A0(n5432), .A1(n5441), .B0(n5434), .B1(n5439), .Y(
DP_OP_169J43_123_4229_n1636) );
XNOR2X1TS U6911 ( .A(n5536), .B(n5437), .Y(n5435) );
OAI22X1TS U6912 ( .A0(n5435), .A1(n5439), .B0(n5434), .B1(n5433), .Y(
DP_OP_169J43_123_4229_n1637) );
XNOR2X1TS U6913 ( .A(n5540), .B(n5437), .Y(n5436) );
OAI22X1TS U6914 ( .A0(n5435), .A1(n5441), .B0(n5436), .B1(n5439), .Y(
DP_OP_169J43_123_4229_n1638) );
XNOR2X1TS U6915 ( .A(n5502), .B(n5437), .Y(n5438) );
OAI22X1TS U6916 ( .A0(n5436), .A1(n5441), .B0(n5438), .B1(n5439), .Y(
DP_OP_169J43_123_4229_n1639) );
XNOR2X1TS U6917 ( .A(n5505), .B(n5437), .Y(n5442) );
OAI22X1TS U6918 ( .A0(n5438), .A1(n5441), .B0(n5442), .B1(n5439), .Y(
DP_OP_169J43_123_4229_n1640) );
OAI22X1TS U6919 ( .A0(n5442), .A1(n5441), .B0(n5440), .B1(n5439), .Y(
DP_OP_169J43_123_4229_n1641) );
XNOR2X1TS U6920 ( .A(n5547), .B(n5468), .Y(n5443) );
OAI22X1TS U6921 ( .A0(n5443), .A1(n5462), .B0(n5472), .B1(n812), .Y(
DP_OP_169J43_123_4229_n1645) );
XNOR2X1TS U6922 ( .A(n5549), .B(n5461), .Y(n5444) );
BUFX4TS U6923 ( .A(n5474), .Y(n5466) );
OAI22X1TS U6924 ( .A0(n5444), .A1(n5462), .B0(n5443), .B1(n5466), .Y(
DP_OP_169J43_123_4229_n1646) );
XNOR2X1TS U6925 ( .A(n5551), .B(n5461), .Y(n5445) );
OAI22X1TS U6926 ( .A0(n5445), .A1(n5462), .B0(n5444), .B1(n5466), .Y(
DP_OP_169J43_123_4229_n1647) );
XNOR2X1TS U6927 ( .A(n5553), .B(n5461), .Y(n5446) );
OAI22X1TS U6928 ( .A0(n5446), .A1(n5462), .B0(n5445), .B1(n5472), .Y(
DP_OP_169J43_123_4229_n1648) );
XNOR2X1TS U6929 ( .A(n5555), .B(n5461), .Y(n5447) );
OAI22X1TS U6930 ( .A0(n5447), .A1(n5462), .B0(n5446), .B1(n5466), .Y(
DP_OP_169J43_123_4229_n1649) );
XNOR2X1TS U6931 ( .A(n5557), .B(n5461), .Y(n5448) );
OAI22X1TS U6932 ( .A0(n5448), .A1(n5462), .B0(n5447), .B1(n5472), .Y(
DP_OP_169J43_123_4229_n1650) );
XNOR2X1TS U6933 ( .A(n5559), .B(n5461), .Y(n5449) );
OAI22X1TS U6934 ( .A0(n5449), .A1(n5462), .B0(n5448), .B1(n5466), .Y(
DP_OP_169J43_123_4229_n1651) );
XNOR2X1TS U6935 ( .A(n5561), .B(n5461), .Y(n5450) );
OAI22X1TS U6936 ( .A0(n5450), .A1(n5462), .B0(n5449), .B1(n5466), .Y(
DP_OP_169J43_123_4229_n1652) );
XNOR2X1TS U6937 ( .A(n5563), .B(n5461), .Y(n5451) );
OAI22X1TS U6938 ( .A0(n5451), .A1(n5462), .B0(n5450), .B1(n5466), .Y(
DP_OP_169J43_123_4229_n1653) );
XNOR2X1TS U6939 ( .A(n5565), .B(n5461), .Y(n5452) );
OAI22X1TS U6940 ( .A0(n5452), .A1(n5462), .B0(n5451), .B1(n5466), .Y(
DP_OP_169J43_123_4229_n1654) );
XNOR2X1TS U6941 ( .A(n5567), .B(n5461), .Y(n5453) );
OAI22X1TS U6942 ( .A0(n5453), .A1(n5462), .B0(n5452), .B1(n5466), .Y(
DP_OP_169J43_123_4229_n1655) );
XNOR2X1TS U6943 ( .A(n5569), .B(n5461), .Y(n5454) );
OAI22X1TS U6944 ( .A0(n5453), .A1(n5472), .B0(n5454), .B1(n5470), .Y(
DP_OP_169J43_123_4229_n1656) );
XNOR2X1TS U6945 ( .A(n5571), .B(n5468), .Y(n5455) );
OAI22X1TS U6946 ( .A0(n5454), .A1(n5472), .B0(n5455), .B1(n5470), .Y(
DP_OP_169J43_123_4229_n1657) );
XNOR2X1TS U6947 ( .A(n5573), .B(n5468), .Y(n5456) );
OAI22X1TS U6948 ( .A0(n5456), .A1(n5462), .B0(n5455), .B1(n5466), .Y(
DP_OP_169J43_123_4229_n1658) );
XNOR2X1TS U6949 ( .A(n5575), .B(n5468), .Y(n5457) );
OAI22X1TS U6950 ( .A0(n5457), .A1(n5470), .B0(n5456), .B1(n5472), .Y(
DP_OP_169J43_123_4229_n1659) );
XNOR2X1TS U6951 ( .A(n5577), .B(n5461), .Y(n5458) );
OAI22X1TS U6952 ( .A0(n5458), .A1(n5470), .B0(n5457), .B1(n5466), .Y(
DP_OP_169J43_123_4229_n1660) );
XNOR2X1TS U6953 ( .A(n5579), .B(n5468), .Y(n5459) );
OAI22X1TS U6954 ( .A0(n5459), .A1(n5470), .B0(n5458), .B1(n5466), .Y(
DP_OP_169J43_123_4229_n1661) );
XNOR2X1TS U6955 ( .A(n5581), .B(n5468), .Y(n5460) );
OAI22X1TS U6956 ( .A0(n5460), .A1(n5470), .B0(n5459), .B1(n5466), .Y(
DP_OP_169J43_123_4229_n1662) );
XNOR2X1TS U6957 ( .A(n5583), .B(n5461), .Y(n5463) );
OAI22X1TS U6958 ( .A0(n5463), .A1(n5470), .B0(n5460), .B1(n5466), .Y(
DP_OP_169J43_123_4229_n1663) );
XNOR2X1TS U6959 ( .A(n5586), .B(n5461), .Y(n5464) );
OAI22X1TS U6960 ( .A0(n5463), .A1(n5472), .B0(n5464), .B1(n5462), .Y(
DP_OP_169J43_123_4229_n1664) );
XNOR2X1TS U6961 ( .A(n5589), .B(n5468), .Y(n5465) );
OAI22X1TS U6962 ( .A0(n5465), .A1(n5470), .B0(n5464), .B1(n5466), .Y(
DP_OP_169J43_123_4229_n1665) );
XNOR2X1TS U6963 ( .A(n5592), .B(n5468), .Y(n5467) );
OAI22X1TS U6964 ( .A0(n5465), .A1(n5472), .B0(n5467), .B1(n5470), .Y(
DP_OP_169J43_123_4229_n1666) );
XNOR2X1TS U6965 ( .A(n5536), .B(n5468), .Y(n5469) );
OAI22X1TS U6966 ( .A0(n5469), .A1(n5470), .B0(n5467), .B1(n5466), .Y(
DP_OP_169J43_123_4229_n1667) );
XNOR2X1TS U6967 ( .A(n5540), .B(n5468), .Y(n5473) );
OAI22X1TS U6968 ( .A0(n5469), .A1(n5472), .B0(n5473), .B1(n5470), .Y(
DP_OP_169J43_123_4229_n1668) );
OAI22X1TS U6969 ( .A0(n5473), .A1(n5472), .B0(n5471), .B1(n5470), .Y(
DP_OP_169J43_123_4229_n1669) );
NOR2BX1TS U6970 ( .AN(n5475), .B(n5474), .Y(DP_OP_169J43_123_4229_n1673) );
XNOR2X1TS U6971 ( .A(n5547), .B(n5504), .Y(n5477) );
OAI22X1TS U6972 ( .A0(n5477), .A1(n5506), .B0(n5510), .B1(n896), .Y(
DP_OP_169J43_123_4229_n1675) );
XNOR2X1TS U6973 ( .A(n5549), .B(n5495), .Y(n5478) );
BUFX4TS U6974 ( .A(n5476), .Y(n5499) );
OAI22X1TS U6975 ( .A0(n5478), .A1(n5506), .B0(n5477), .B1(n5499), .Y(
DP_OP_169J43_123_4229_n1676) );
XNOR2X1TS U6976 ( .A(n5551), .B(n5495), .Y(n5479) );
OAI22X1TS U6977 ( .A0(n5479), .A1(n5506), .B0(n5478), .B1(n5499), .Y(
DP_OP_169J43_123_4229_n1677) );
XNOR2X1TS U6978 ( .A(n5553), .B(n5495), .Y(n5480) );
OAI22X1TS U6979 ( .A0(n5480), .A1(n5506), .B0(n5479), .B1(n5510), .Y(
DP_OP_169J43_123_4229_n1678) );
XNOR2X1TS U6980 ( .A(n5555), .B(n5495), .Y(n5481) );
OAI22X1TS U6981 ( .A0(n5481), .A1(n5506), .B0(n5480), .B1(n5499), .Y(
DP_OP_169J43_123_4229_n1679) );
XNOR2X1TS U6982 ( .A(n5557), .B(n5495), .Y(n5482) );
OAI22X1TS U6983 ( .A0(n5482), .A1(n5506), .B0(n5481), .B1(n5510), .Y(
DP_OP_169J43_123_4229_n1680) );
XNOR2X1TS U6984 ( .A(n5559), .B(n5495), .Y(n5483) );
OAI22X1TS U6985 ( .A0(n5483), .A1(n5506), .B0(n5482), .B1(n5499), .Y(
DP_OP_169J43_123_4229_n1681) );
XNOR2X1TS U6986 ( .A(n5561), .B(n5495), .Y(n5484) );
OAI22X1TS U6987 ( .A0(n5484), .A1(n5506), .B0(n5483), .B1(n5499), .Y(
DP_OP_169J43_123_4229_n1682) );
XNOR2X1TS U6988 ( .A(n5563), .B(n5495), .Y(n5485) );
OAI22X1TS U6989 ( .A0(n5485), .A1(n5506), .B0(n5484), .B1(n5499), .Y(
DP_OP_169J43_123_4229_n1683) );
XNOR2X1TS U6990 ( .A(n5565), .B(n5495), .Y(n5486) );
OAI22X1TS U6991 ( .A0(n5486), .A1(n5506), .B0(n5485), .B1(n5499), .Y(
DP_OP_169J43_123_4229_n1684) );
XNOR2X1TS U6992 ( .A(n5567), .B(n5495), .Y(n5487) );
OAI22X1TS U6993 ( .A0(n5487), .A1(n5506), .B0(n5486), .B1(n5499), .Y(
DP_OP_169J43_123_4229_n1685) );
XNOR2X1TS U6994 ( .A(n5569), .B(n5495), .Y(n5488) );
OAI22X1TS U6995 ( .A0(n5487), .A1(n5510), .B0(n5488), .B1(n5508), .Y(
DP_OP_169J43_123_4229_n1686) );
XNOR2X1TS U6996 ( .A(n5571), .B(n5504), .Y(n5489) );
OAI22X1TS U6997 ( .A0(n5488), .A1(n5510), .B0(n5489), .B1(n5508), .Y(
DP_OP_169J43_123_4229_n1687) );
XNOR2X1TS U6998 ( .A(n5573), .B(n5504), .Y(n5490) );
OAI22X1TS U6999 ( .A0(n5490), .A1(n5506), .B0(n5489), .B1(n5499), .Y(
DP_OP_169J43_123_4229_n1688) );
XNOR2X1TS U7000 ( .A(n5575), .B(n5504), .Y(n5491) );
OAI22X1TS U7001 ( .A0(n5491), .A1(n5508), .B0(n5490), .B1(n5510), .Y(
DP_OP_169J43_123_4229_n1689) );
XNOR2X1TS U7002 ( .A(n5577), .B(n5495), .Y(n5492) );
OAI22X1TS U7003 ( .A0(n5492), .A1(n5508), .B0(n5491), .B1(n5499), .Y(
DP_OP_169J43_123_4229_n1690) );
XNOR2X1TS U7004 ( .A(n5579), .B(n5504), .Y(n5493) );
OAI22X1TS U7005 ( .A0(n5493), .A1(n5508), .B0(n5492), .B1(n5499), .Y(
DP_OP_169J43_123_4229_n1691) );
XNOR2X1TS U7006 ( .A(n5581), .B(n5504), .Y(n5494) );
OAI22X1TS U7007 ( .A0(n5494), .A1(n5508), .B0(n5493), .B1(n5499), .Y(
DP_OP_169J43_123_4229_n1692) );
XNOR2X1TS U7008 ( .A(n5583), .B(n5495), .Y(n5496) );
OAI22X1TS U7009 ( .A0(n5496), .A1(n5508), .B0(n5494), .B1(n5499), .Y(
DP_OP_169J43_123_4229_n1693) );
XNOR2X1TS U7010 ( .A(n5586), .B(n5495), .Y(n5497) );
OAI22X1TS U7011 ( .A0(n5496), .A1(n5510), .B0(n5497), .B1(n5506), .Y(
DP_OP_169J43_123_4229_n1694) );
XNOR2X1TS U7012 ( .A(n5589), .B(n5504), .Y(n5498) );
OAI22X1TS U7013 ( .A0(n5498), .A1(n5508), .B0(n5497), .B1(n5499), .Y(
DP_OP_169J43_123_4229_n1695) );
XNOR2X1TS U7014 ( .A(n5592), .B(n5504), .Y(n5500) );
OAI22X1TS U7015 ( .A0(n5498), .A1(n5510), .B0(n5500), .B1(n5508), .Y(
DP_OP_169J43_123_4229_n1696) );
XNOR2X1TS U7016 ( .A(n5536), .B(n5504), .Y(n5501) );
OAI22X1TS U7017 ( .A0(n5501), .A1(n5508), .B0(n5500), .B1(n5499), .Y(
DP_OP_169J43_123_4229_n1697) );
XNOR2X1TS U7018 ( .A(n5540), .B(n5504), .Y(n5503) );
OAI22X1TS U7019 ( .A0(n5501), .A1(n5510), .B0(n5503), .B1(n5508), .Y(
DP_OP_169J43_123_4229_n1698) );
XNOR2X1TS U7020 ( .A(n5502), .B(n5504), .Y(n5507) );
OAI22X1TS U7021 ( .A0(n5503), .A1(n5510), .B0(n5507), .B1(n5508), .Y(
DP_OP_169J43_123_4229_n1699) );
XNOR2X1TS U7022 ( .A(n5505), .B(n5504), .Y(n5511) );
OAI22X1TS U7023 ( .A0(n5507), .A1(n5510), .B0(n5511), .B1(n5506), .Y(
DP_OP_169J43_123_4229_n1700) );
OAI22X1TS U7024 ( .A0(n5511), .A1(n5510), .B0(n5509), .B1(n5508), .Y(
DP_OP_169J43_123_4229_n1701) );
XNOR2X1TS U7025 ( .A(n5547), .B(n5539), .Y(n5513) );
OAI22X1TS U7026 ( .A0(n5513), .A1(n5529), .B0(n5545), .B1(n756), .Y(
DP_OP_169J43_123_4229_n1705) );
XNOR2X1TS U7027 ( .A(n5549), .B(n5533), .Y(n5514) );
BUFX4TS U7028 ( .A(n5512), .Y(n5537) );
OAI22X1TS U7029 ( .A0(n5514), .A1(n5529), .B0(n5513), .B1(n5537), .Y(
DP_OP_169J43_123_4229_n1706) );
XNOR2X1TS U7030 ( .A(n5551), .B(n5533), .Y(n5515) );
OAI22X1TS U7031 ( .A0(n5515), .A1(n5529), .B0(n5514), .B1(n5537), .Y(
DP_OP_169J43_123_4229_n1707) );
XNOR2X1TS U7032 ( .A(n5553), .B(n5533), .Y(n5516) );
OAI22X1TS U7033 ( .A0(n5516), .A1(n5529), .B0(n5515), .B1(n5537), .Y(
DP_OP_169J43_123_4229_n1708) );
XNOR2X1TS U7034 ( .A(n5555), .B(n5533), .Y(n5517) );
OAI22X1TS U7035 ( .A0(n5517), .A1(n5543), .B0(n5516), .B1(n5537), .Y(
DP_OP_169J43_123_4229_n1709) );
XNOR2X1TS U7036 ( .A(n5557), .B(n5533), .Y(n5518) );
OAI22X1TS U7037 ( .A0(n5518), .A1(n5529), .B0(n5517), .B1(n5537), .Y(
DP_OP_169J43_123_4229_n1710) );
XNOR2X1TS U7038 ( .A(n5559), .B(n5533), .Y(n5519) );
OAI22X1TS U7039 ( .A0(n5519), .A1(n5529), .B0(n5518), .B1(n5537), .Y(
DP_OP_169J43_123_4229_n1711) );
XNOR2X1TS U7040 ( .A(n5561), .B(n5533), .Y(n5520) );
OAI22X1TS U7041 ( .A0(n5520), .A1(n5529), .B0(n5519), .B1(n5537), .Y(
DP_OP_169J43_123_4229_n1712) );
XNOR2X1TS U7042 ( .A(n5563), .B(n5533), .Y(n5521) );
OAI22X1TS U7043 ( .A0(n5521), .A1(n5529), .B0(n5520), .B1(n5537), .Y(
DP_OP_169J43_123_4229_n1713) );
XNOR2X1TS U7044 ( .A(n5565), .B(n5533), .Y(n5522) );
OAI22X1TS U7045 ( .A0(n5522), .A1(n5529), .B0(n5521), .B1(n5537), .Y(
DP_OP_169J43_123_4229_n1714) );
XNOR2X1TS U7046 ( .A(n5567), .B(n5533), .Y(n5523) );
OAI22X1TS U7047 ( .A0(n5523), .A1(n5529), .B0(n5522), .B1(n5537), .Y(
DP_OP_169J43_123_4229_n1715) );
XNOR2X1TS U7048 ( .A(n5569), .B(n5533), .Y(n5524) );
OAI22X1TS U7049 ( .A0(n5523), .A1(n5545), .B0(n5524), .B1(n5541), .Y(
DP_OP_169J43_123_4229_n1716) );
XNOR2X1TS U7050 ( .A(n5571), .B(n5539), .Y(n5525) );
OAI22X1TS U7051 ( .A0(n5524), .A1(n5545), .B0(n5525), .B1(n5543), .Y(
DP_OP_169J43_123_4229_n1717) );
XNOR2X1TS U7052 ( .A(n5573), .B(n5539), .Y(n5526) );
OAI22X1TS U7053 ( .A0(n5526), .A1(n5529), .B0(n5525), .B1(n5537), .Y(
DP_OP_169J43_123_4229_n1718) );
XNOR2X1TS U7054 ( .A(n5575), .B(n5539), .Y(n5527) );
OAI22X1TS U7055 ( .A0(n5527), .A1(n5529), .B0(n5526), .B1(n5537), .Y(
DP_OP_169J43_123_4229_n1719) );
XNOR2X1TS U7056 ( .A(n5577), .B(n5533), .Y(n5528) );
OAI22X1TS U7057 ( .A0(n5528), .A1(n5541), .B0(n5527), .B1(n5545), .Y(
DP_OP_169J43_123_4229_n1720) );
XNOR2X1TS U7058 ( .A(n5579), .B(n5539), .Y(n5530) );
OAI22X1TS U7059 ( .A0(n5530), .A1(n5529), .B0(n5528), .B1(n5537), .Y(
DP_OP_169J43_123_4229_n1721) );
XNOR2X1TS U7060 ( .A(n5581), .B(n5539), .Y(n5531) );
OAI22X1TS U7061 ( .A0(n5531), .A1(n5543), .B0(n5530), .B1(n5545), .Y(
DP_OP_169J43_123_4229_n1722) );
XNOR2X1TS U7062 ( .A(n5583), .B(n5533), .Y(n5532) );
OAI22X1TS U7063 ( .A0(n5532), .A1(n5543), .B0(n5531), .B1(n5537), .Y(
DP_OP_169J43_123_4229_n1723) );
XNOR2X1TS U7064 ( .A(n5586), .B(n5539), .Y(n5534) );
OAI22X1TS U7065 ( .A0(n5532), .A1(n5545), .B0(n5534), .B1(n5543), .Y(
DP_OP_169J43_123_4229_n1724) );
XNOR2X1TS U7066 ( .A(n5589), .B(n5533), .Y(n5535) );
OAI22X1TS U7067 ( .A0(n5535), .A1(n5541), .B0(n5534), .B1(n5545), .Y(
DP_OP_169J43_123_4229_n1725) );
XNOR2X1TS U7068 ( .A(n5592), .B(n5539), .Y(n5538) );
OAI22X1TS U7069 ( .A0(n5535), .A1(n5545), .B0(n5538), .B1(n5541), .Y(
DP_OP_169J43_123_4229_n1726) );
XNOR2X1TS U7070 ( .A(n5536), .B(n5539), .Y(n5542) );
OAI22X1TS U7071 ( .A0(n5542), .A1(n5541), .B0(n5538), .B1(n5537), .Y(
DP_OP_169J43_123_4229_n1727) );
XNOR2X1TS U7072 ( .A(n5540), .B(n5539), .Y(n5546) );
OAI22X1TS U7073 ( .A0(n5542), .A1(n5545), .B0(n5546), .B1(n5541), .Y(
DP_OP_169J43_123_4229_n1728) );
OAI22X1TS U7074 ( .A0(n5546), .A1(n5545), .B0(n5544), .B1(n5543), .Y(
DP_OP_169J43_123_4229_n1729) );
XNOR2X1TS U7075 ( .A(n5547), .B(n5591), .Y(n5550) );
BUFX4TS U7076 ( .A(n5548), .Y(n5595) );
OAI22X1TS U7077 ( .A0(n5550), .A1(n5587), .B0(n4957), .B1(n5595), .Y(
DP_OP_169J43_123_4229_n1734) );
XNOR2X1TS U7078 ( .A(n5549), .B(n5585), .Y(n5552) );
OAI22X1TS U7079 ( .A0(n5552), .A1(n5587), .B0(n5550), .B1(n5548), .Y(
DP_OP_169J43_123_4229_n1735) );
XNOR2X1TS U7080 ( .A(n5551), .B(n5585), .Y(n5554) );
OAI22X1TS U7081 ( .A0(n5554), .A1(n5587), .B0(n5552), .B1(n5595), .Y(
DP_OP_169J43_123_4229_n1736) );
XNOR2X1TS U7082 ( .A(n5553), .B(n5585), .Y(n5556) );
OAI22X1TS U7083 ( .A0(n5556), .A1(n5587), .B0(n5554), .B1(n5595), .Y(
DP_OP_169J43_123_4229_n1737) );
XNOR2X1TS U7084 ( .A(n5555), .B(n5585), .Y(n5558) );
OAI22X1TS U7085 ( .A0(n5558), .A1(n5587), .B0(n5556), .B1(n5548), .Y(
DP_OP_169J43_123_4229_n1738) );
XNOR2X1TS U7086 ( .A(n5557), .B(n5585), .Y(n5560) );
OAI22X1TS U7087 ( .A0(n5560), .A1(n5587), .B0(n5558), .B1(n5548), .Y(
DP_OP_169J43_123_4229_n1739) );
XNOR2X1TS U7088 ( .A(n5559), .B(n5585), .Y(n5562) );
OAI22X1TS U7089 ( .A0(n5562), .A1(n5587), .B0(n5560), .B1(n5595), .Y(
DP_OP_169J43_123_4229_n1740) );
XNOR2X1TS U7090 ( .A(n5561), .B(n5585), .Y(n5564) );
OAI22X1TS U7091 ( .A0(n5564), .A1(n5587), .B0(n5562), .B1(n5595), .Y(
DP_OP_169J43_123_4229_n1741) );
XNOR2X1TS U7092 ( .A(n5563), .B(n5585), .Y(n5566) );
OAI22X1TS U7093 ( .A0(n5566), .A1(n5587), .B0(n5564), .B1(n5595), .Y(
DP_OP_169J43_123_4229_n1742) );
XNOR2X1TS U7094 ( .A(n5565), .B(n5585), .Y(n5568) );
OAI22X1TS U7095 ( .A0(n5568), .A1(n5587), .B0(n5566), .B1(n5595), .Y(
DP_OP_169J43_123_4229_n1743) );
XNOR2X1TS U7096 ( .A(n5567), .B(n5585), .Y(n5570) );
OAI22X1TS U7097 ( .A0(n5570), .A1(n5587), .B0(n5568), .B1(n5595), .Y(
DP_OP_169J43_123_4229_n1744) );
XNOR2X1TS U7098 ( .A(n5569), .B(n5585), .Y(n5572) );
OAI22X1TS U7099 ( .A0(n5570), .A1(n5548), .B0(n5572), .B1(n1628), .Y(
DP_OP_169J43_123_4229_n1745) );
XNOR2X1TS U7100 ( .A(n5571), .B(n5591), .Y(n5574) );
OAI22X1TS U7101 ( .A0(n5572), .A1(n5548), .B0(n5574), .B1(n1628), .Y(
DP_OP_169J43_123_4229_n1746) );
XNOR2X1TS U7102 ( .A(n5573), .B(n5591), .Y(n5576) );
OAI22X1TS U7103 ( .A0(n5576), .A1(n5587), .B0(n5574), .B1(n5595), .Y(
DP_OP_169J43_123_4229_n1747) );
XNOR2X1TS U7104 ( .A(n5575), .B(n5591), .Y(n5578) );
OAI22X1TS U7105 ( .A0(n5578), .A1(n1628), .B0(n5576), .B1(n5548), .Y(
DP_OP_169J43_123_4229_n1748) );
XNOR2X1TS U7106 ( .A(n5577), .B(n5585), .Y(n5580) );
OAI22X1TS U7107 ( .A0(n5580), .A1(n1628), .B0(n5578), .B1(n5595), .Y(
DP_OP_169J43_123_4229_n1749) );
XNOR2X1TS U7108 ( .A(n5579), .B(n5591), .Y(n5582) );
OAI22X1TS U7109 ( .A0(n5582), .A1(n1628), .B0(n5580), .B1(n5595), .Y(
DP_OP_169J43_123_4229_n1750) );
XNOR2X1TS U7110 ( .A(n5581), .B(n5585), .Y(n5584) );
OAI22X1TS U7111 ( .A0(n5584), .A1(n1628), .B0(n5582), .B1(n5595), .Y(
DP_OP_169J43_123_4229_n1751) );
XNOR2X1TS U7112 ( .A(n5583), .B(n5585), .Y(n5588) );
OAI22X1TS U7113 ( .A0(n5588), .A1(n1628), .B0(n5584), .B1(n5595), .Y(
DP_OP_169J43_123_4229_n1752) );
XNOR2X1TS U7114 ( .A(n5586), .B(n5585), .Y(n5590) );
OAI22X1TS U7115 ( .A0(n5588), .A1(n5548), .B0(n5590), .B1(n5587), .Y(
DP_OP_169J43_123_4229_n1753) );
XNOR2X1TS U7116 ( .A(n5589), .B(n5591), .Y(n5594) );
OAI22X1TS U7117 ( .A0(n5594), .A1(n1628), .B0(n5590), .B1(n5595), .Y(
DP_OP_169J43_123_4229_n1754) );
XNOR2X1TS U7118 ( .A(n5592), .B(n5591), .Y(n5596) );
OAI22X1TS U7119 ( .A0(n5594), .A1(n5548), .B0(n5596), .B1(n1628), .Y(
DP_OP_169J43_123_4229_n1755) );
OAI22X1TS U7120 ( .A0(n5597), .A1(n1628), .B0(n5596), .B1(n5595), .Y(
DP_OP_169J43_123_4229_n1756) );
NOR3BX1TS U7121 ( .AN(Op_MY[62]), .B(FSM_selector_B[1]), .C(
FSM_selector_B[0]), .Y(n5598) );
XOR2X1TS U7122 ( .A(n6582), .B(n5598), .Y(DP_OP_36J43_124_1029_n18) );
OAI2BB1X1TS U7123 ( .A0N(Op_MY[61]), .A1N(n6539), .B0(n5608), .Y(n5599) );
XOR2X1TS U7124 ( .A(n6582), .B(n5599), .Y(DP_OP_36J43_124_1029_n19) );
OAI2BB1X1TS U7125 ( .A0N(Op_MY[60]), .A1N(n6539), .B0(n5608), .Y(n5600) );
XOR2X1TS U7126 ( .A(n6582), .B(n5600), .Y(DP_OP_36J43_124_1029_n20) );
OAI2BB1X1TS U7127 ( .A0N(Op_MY[59]), .A1N(n6539), .B0(n5608), .Y(n5601) );
XOR2X1TS U7128 ( .A(n6582), .B(n5601), .Y(DP_OP_36J43_124_1029_n21) );
OAI2BB1X1TS U7129 ( .A0N(Op_MY[58]), .A1N(n6539), .B0(n5608), .Y(n5602) );
XOR2X1TS U7130 ( .A(n6582), .B(n5602), .Y(DP_OP_36J43_124_1029_n22) );
OAI2BB1X1TS U7131 ( .A0N(Op_MY[57]), .A1N(n6539), .B0(n5608), .Y(n5603) );
XOR2X1TS U7132 ( .A(n6582), .B(n5603), .Y(DP_OP_36J43_124_1029_n23) );
OAI2BB1X1TS U7133 ( .A0N(Op_MY[56]), .A1N(n6539), .B0(n5608), .Y(n5604) );
XOR2X1TS U7134 ( .A(n6582), .B(n5604), .Y(DP_OP_36J43_124_1029_n24) );
OAI2BB1X1TS U7135 ( .A0N(Op_MY[55]), .A1N(n6539), .B0(n5608), .Y(n5605) );
XOR2X1TS U7136 ( .A(n6582), .B(n5605), .Y(DP_OP_36J43_124_1029_n25) );
OAI2BB1X1TS U7137 ( .A0N(Op_MY[54]), .A1N(n6539), .B0(n5608), .Y(n5606) );
XOR2X1TS U7138 ( .A(n766), .B(n5606), .Y(DP_OP_36J43_124_1029_n26) );
OAI2BB1X1TS U7139 ( .A0N(Op_MY[53]), .A1N(n6539), .B0(n5608), .Y(n5607) );
XOR2X1TS U7140 ( .A(n766), .B(n5607), .Y(DP_OP_36J43_124_1029_n27) );
XOR2X1TS U7141 ( .A(n766), .B(n5610), .Y(DP_OP_36J43_124_1029_n28) );
INVX4TS U7142 ( .A(n5613), .Y(n5612) );
MX2X1TS U7143 ( .A(Data_MX[26]), .B(Op_MX[26]), .S0(n5612), .Y(n672) );
MX2X1TS U7144 ( .A(Data_MX[25]), .B(n6583), .S0(n5612), .Y(n671) );
MX2X1TS U7145 ( .A(Data_MX[24]), .B(n788), .S0(n5612), .Y(n670) );
MX2X1TS U7146 ( .A(Data_MX[23]), .B(Op_MX[23]), .S0(n5612), .Y(n669) );
MX2X1TS U7147 ( .A(Data_MX[22]), .B(n792), .S0(n5612), .Y(n668) );
MX2X1TS U7148 ( .A(Data_MX[21]), .B(Op_MX[21]), .S0(n5612), .Y(n667) );
MX2X1TS U7149 ( .A(Data_MX[20]), .B(Op_MX[20]), .S0(n5612), .Y(n666) );
MX2X1TS U7150 ( .A(Data_MX[19]), .B(Op_MX[19]), .S0(n5612), .Y(n665) );
MX2X1TS U7151 ( .A(Data_MX[18]), .B(n791), .S0(n5612), .Y(n664) );
MX2X1TS U7152 ( .A(Data_MX[17]), .B(n793), .S0(n5612), .Y(n663) );
MX2X1TS U7153 ( .A(Data_MX[16]), .B(n790), .S0(n5612), .Y(n662) );
MX2X1TS U7154 ( .A(Data_MX[15]), .B(Op_MX[15]), .S0(n5612), .Y(n661) );
MX2X1TS U7155 ( .A(Data_MX[14]), .B(Op_MX[14]), .S0(n5612), .Y(n660) );
INVX4TS U7156 ( .A(n5613), .Y(n5614) );
MX2X1TS U7157 ( .A(Data_MX[13]), .B(Op_MX[13]), .S0(n5614), .Y(n659) );
MX2X1TS U7158 ( .A(Data_MX[12]), .B(Op_MX[12]), .S0(n5614), .Y(n658) );
MX2X1TS U7159 ( .A(Data_MX[11]), .B(n794), .S0(n5614), .Y(n657) );
MX2X1TS U7160 ( .A(Data_MX[10]), .B(n789), .S0(n5614), .Y(n656) );
MX2X1TS U7161 ( .A(Data_MX[9]), .B(Op_MX[9]), .S0(n5614), .Y(n655) );
MX2X1TS U7162 ( .A(Data_MX[8]), .B(Op_MX[8]), .S0(n5614), .Y(n654) );
MX2X1TS U7163 ( .A(Data_MX[7]), .B(Op_MX[7]), .S0(n5614), .Y(n653) );
MX2X1TS U7164 ( .A(Data_MX[6]), .B(n795), .S0(n5614), .Y(n652) );
MX2X1TS U7165 ( .A(Data_MX[5]), .B(Op_MX[5]), .S0(n5614), .Y(n651) );
MX2X1TS U7166 ( .A(Data_MX[4]), .B(Op_MX[4]), .S0(n5614), .Y(n650) );
MX2X1TS U7167 ( .A(Data_MX[3]), .B(Op_MX[3]), .S0(n5614), .Y(n649) );
MX2X1TS U7168 ( .A(Data_MX[2]), .B(Op_MX[2]), .S0(n5614), .Y(n648) );
MX2X1TS U7169 ( .A(Data_MX[1]), .B(Op_MX[1]), .S0(n5614), .Y(n647) );
INVX4TS U7170 ( .A(n5613), .Y(n5615) );
MX2X1TS U7171 ( .A(Data_MX[0]), .B(Op_MX[0]), .S0(n5615), .Y(n646) );
MX2X1TS U7172 ( .A(Data_MX[51]), .B(n6584), .S0(n5615), .Y(n697) );
MX2X1TS U7173 ( .A(Data_MX[50]), .B(n6586), .S0(n5615), .Y(n696) );
MX2X1TS U7174 ( .A(Data_MX[49]), .B(Op_MX[49]), .S0(n5615), .Y(n695) );
MX2X1TS U7175 ( .A(Data_MX[48]), .B(Op_MX[48]), .S0(n5615), .Y(n694) );
MX2X1TS U7176 ( .A(Data_MX[47]), .B(Op_MX[47]), .S0(n5615), .Y(n693) );
MX2X1TS U7177 ( .A(Data_MX[46]), .B(Op_MX[46]), .S0(n5615), .Y(n692) );
MX2X1TS U7178 ( .A(Data_MX[45]), .B(Op_MX[45]), .S0(n5615), .Y(n691) );
MX2X1TS U7179 ( .A(Data_MX[44]), .B(n6587), .S0(n5615), .Y(n690) );
MX2X1TS U7180 ( .A(Data_MX[43]), .B(Op_MX[43]), .S0(n5615), .Y(n689) );
MX2X1TS U7181 ( .A(Data_MX[42]), .B(Op_MX[42]), .S0(n5615), .Y(n688) );
MX2X1TS U7182 ( .A(Data_MX[41]), .B(Op_MX[41]), .S0(n5615), .Y(n687) );
MX2X1TS U7183 ( .A(Data_MX[40]), .B(Op_MX[40]), .S0(n5615), .Y(n686) );
INVX4TS U7184 ( .A(n5613), .Y(n5616) );
MX2X1TS U7185 ( .A(Data_MX[39]), .B(Op_MX[39]), .S0(n5616), .Y(n685) );
MX2X1TS U7186 ( .A(Data_MX[38]), .B(n6588), .S0(n5616), .Y(n684) );
MX2X1TS U7187 ( .A(Data_MX[37]), .B(Op_MX[37]), .S0(n5616), .Y(n683) );
MX2X1TS U7188 ( .A(Data_MX[36]), .B(Op_MX[36]), .S0(n5616), .Y(n682) );
MX2X1TS U7189 ( .A(Data_MX[35]), .B(Op_MX[35]), .S0(n5616), .Y(n681) );
MX2X1TS U7190 ( .A(Data_MX[34]), .B(Op_MX[34]), .S0(n5616), .Y(n680) );
MX2X1TS U7191 ( .A(Data_MX[33]), .B(Op_MX[33]), .S0(n5616), .Y(n679) );
MX2X1TS U7192 ( .A(Data_MX[32]), .B(n3604), .S0(n5616), .Y(n678) );
MX2X1TS U7193 ( .A(Data_MX[31]), .B(Op_MX[31]), .S0(n5616), .Y(n677) );
MX2X1TS U7194 ( .A(Data_MX[30]), .B(Op_MX[30]), .S0(n5616), .Y(n676) );
MX2X1TS U7195 ( .A(Data_MX[29]), .B(Op_MX[29]), .S0(n5616), .Y(n675) );
MX2X1TS U7196 ( .A(Data_MX[28]), .B(Op_MX[28]), .S0(n5616), .Y(n674) );
MX2X1TS U7197 ( .A(Data_MX[27]), .B(Op_MX[27]), .S0(n5616), .Y(n673) );
INVX4TS U7198 ( .A(n5613), .Y(n5617) );
MX2X1TS U7199 ( .A(Data_MY[26]), .B(Op_MY[26]), .S0(n5617), .Y(n608) );
MX2X1TS U7200 ( .A(Data_MY[25]), .B(Op_MY[25]), .S0(n5617), .Y(n607) );
MX2X1TS U7201 ( .A(Data_MY[24]), .B(Op_MY[24]), .S0(n5617), .Y(n606) );
MX2X1TS U7202 ( .A(Data_MY[23]), .B(n798), .S0(n5617), .Y(n605) );
MX2X1TS U7203 ( .A(Data_MY[22]), .B(Op_MY[22]), .S0(n5617), .Y(n604) );
MX2X1TS U7204 ( .A(Data_MY[21]), .B(Op_MY[21]), .S0(n5617), .Y(n603) );
MX2X1TS U7205 ( .A(Data_MY[20]), .B(n770), .S0(n5617), .Y(n602) );
MX2X1TS U7206 ( .A(Data_MY[19]), .B(Op_MY[19]), .S0(n5617), .Y(n601) );
MX2X1TS U7207 ( .A(Data_MY[18]), .B(Op_MY[18]), .S0(n5617), .Y(n600) );
MX2X1TS U7208 ( .A(Data_MY[17]), .B(n780), .S0(n5617), .Y(n599) );
MX2X1TS U7209 ( .A(Data_MY[16]), .B(Op_MY[16]), .S0(n5617), .Y(n598) );
MX2X1TS U7210 ( .A(Data_MY[15]), .B(Op_MY[15]), .S0(n5617), .Y(n597) );
MX2X1TS U7211 ( .A(Data_MY[14]), .B(n800), .S0(n5617), .Y(n596) );
INVX4TS U7212 ( .A(n5613), .Y(n5618) );
MX2X1TS U7213 ( .A(Data_MY[13]), .B(Op_MY[13]), .S0(n5618), .Y(n595) );
MX2X1TS U7214 ( .A(Data_MY[12]), .B(Op_MY[12]), .S0(n5618), .Y(n594) );
MX2X1TS U7215 ( .A(Data_MY[11]), .B(n777), .S0(n5618), .Y(n593) );
MX2X1TS U7216 ( .A(Data_MY[10]), .B(Op_MY[10]), .S0(n5618), .Y(n592) );
MX2X1TS U7217 ( .A(Data_MY[9]), .B(Op_MY[9]), .S0(n5618), .Y(n591) );
MX2X1TS U7218 ( .A(Data_MY[8]), .B(n783), .S0(n5618), .Y(n590) );
MX2X1TS U7219 ( .A(Data_MY[7]), .B(Op_MY[7]), .S0(n5618), .Y(n589) );
MX2X1TS U7220 ( .A(Data_MY[6]), .B(Op_MY[6]), .S0(n5618), .Y(n588) );
MX2X1TS U7221 ( .A(Data_MY[5]), .B(n802), .S0(n5618), .Y(n587) );
MX2X1TS U7222 ( .A(Data_MY[4]), .B(Op_MY[4]), .S0(n5618), .Y(n586) );
MX2X1TS U7223 ( .A(Data_MY[3]), .B(Op_MY[3]), .S0(n5618), .Y(n585) );
MX2X1TS U7224 ( .A(Data_MY[2]), .B(Op_MY[2]), .S0(n5618), .Y(n584) );
MX2X1TS U7225 ( .A(Data_MY[1]), .B(Op_MY[1]), .S0(n5618), .Y(n583) );
INVX4TS U7226 ( .A(n5613), .Y(n5619) );
MX2X1TS U7227 ( .A(Data_MY[0]), .B(Op_MY[0]), .S0(n5619), .Y(n582) );
MX2X1TS U7228 ( .A(Data_MY[51]), .B(n767), .S0(n5619), .Y(n633) );
MX2X1TS U7229 ( .A(Data_MY[50]), .B(Op_MY[50]), .S0(n5619), .Y(n632) );
MX2X1TS U7230 ( .A(Data_MY[49]), .B(Op_MY[49]), .S0(n5619), .Y(n631) );
MX2X1TS U7231 ( .A(Data_MY[48]), .B(Op_MY[48]), .S0(n5619), .Y(n630) );
MX2X1TS U7232 ( .A(Data_MY[47]), .B(Op_MY[47]), .S0(n5619), .Y(n629) );
MX2X1TS U7233 ( .A(Data_MY[46]), .B(Op_MY[46]), .S0(n5619), .Y(n628) );
MX2X1TS U7234 ( .A(Data_MY[45]), .B(Op_MY[45]), .S0(n5619), .Y(n627) );
MX2X1TS U7235 ( .A(Data_MY[44]), .B(Op_MY[44]), .S0(n5619), .Y(n626) );
MX2X1TS U7236 ( .A(Data_MY[43]), .B(Op_MY[43]), .S0(n5619), .Y(n625) );
MX2X1TS U7237 ( .A(Data_MY[42]), .B(Op_MY[42]), .S0(n5619), .Y(n624) );
MX2X1TS U7238 ( .A(Data_MY[41]), .B(Op_MY[41]), .S0(n5619), .Y(n623) );
MX2X1TS U7239 ( .A(Data_MY[40]), .B(Op_MY[40]), .S0(n5619), .Y(n622) );
INVX4TS U7240 ( .A(n5613), .Y(n5620) );
MX2X1TS U7241 ( .A(Data_MY[39]), .B(Op_MY[39]), .S0(n5620), .Y(n621) );
MX2X1TS U7242 ( .A(Data_MY[38]), .B(Op_MY[38]), .S0(n5620), .Y(n620) );
MX2X1TS U7243 ( .A(Data_MY[37]), .B(Op_MY[37]), .S0(n5620), .Y(n619) );
MX2X1TS U7244 ( .A(Data_MY[36]), .B(Op_MY[36]), .S0(n5620), .Y(n618) );
MX2X1TS U7245 ( .A(Data_MY[35]), .B(Op_MY[35]), .S0(n5620), .Y(n617) );
MX2X1TS U7246 ( .A(Data_MY[34]), .B(Op_MY[34]), .S0(n5620), .Y(n616) );
MX2X1TS U7247 ( .A(Data_MY[33]), .B(Op_MY[33]), .S0(n5620), .Y(n615) );
MX2X1TS U7248 ( .A(Data_MY[32]), .B(Op_MY[32]), .S0(n5620), .Y(n614) );
MX2X1TS U7249 ( .A(Data_MY[31]), .B(Op_MY[31]), .S0(n5620), .Y(n613) );
MX2X1TS U7250 ( .A(Data_MY[30]), .B(Op_MY[30]), .S0(n5620), .Y(n612) );
MX2X1TS U7251 ( .A(Data_MY[29]), .B(Op_MY[29]), .S0(n5620), .Y(n611) );
MX2X1TS U7252 ( .A(Data_MY[28]), .B(Op_MY[28]), .S0(n5620), .Y(n610) );
MX2X1TS U7253 ( .A(Data_MY[27]), .B(Op_MY[27]), .S0(n5620), .Y(n609) );
NAND2X1TS U7254 ( .A(Sgf_normalized_result[10]), .B(
Sgf_normalized_result[11]), .Y(n6005) );
NAND2X1TS U7255 ( .A(Sgf_normalized_result[12]), .B(
Sgf_normalized_result[13]), .Y(n5621) );
NOR2X1TS U7256 ( .A(n6005), .B(n5621), .Y(n5970) );
NAND2X1TS U7257 ( .A(Sgf_normalized_result[14]), .B(
Sgf_normalized_result[15]), .Y(n5971) );
NAND2X1TS U7258 ( .A(n5970), .B(n5622), .Y(n5626) );
NAND2X1TS U7259 ( .A(Sgf_normalized_result[6]), .B(Sgf_normalized_result[7]),
.Y(n6059) );
NAND2X1TS U7260 ( .A(Sgf_normalized_result[8]), .B(Sgf_normalized_result[9]),
.Y(n5623) );
MXI2X1TS U7261 ( .A(P_Sgf[104]), .B(Add_result[52]), .S0(FSM_selector_C),
.Y(n5631) );
AOI21X1TS U7262 ( .A0(n5631), .A1(n5638), .B0(n6013), .Y(n5632) );
AO21XLTS U7263 ( .A0(Sgf_normalized_result[52]), .A1(n6041), .B0(n5632), .Y(
n580) );
NAND2X1TS U7264 ( .A(n5635), .B(n5638), .Y(n5636) );
NOR2X1TS U7265 ( .A(FSM_selector_C), .B(n5636), .Y(n5747) );
BUFX3TS U7266 ( .A(n5747), .Y(n5739) );
BUFX3TS U7267 ( .A(n5637), .Y(n6160) );
BUFX3TS U7268 ( .A(n5661), .Y(n5894) );
NOR2X2TS U7269 ( .A(n5638), .B(n6541), .Y(n5992) );
AOI22X1TS U7270 ( .A0(n6168), .A1(Add_result[52]), .B0(
Sgf_normalized_result[51]), .B1(n6179), .Y(n5639) );
OAI2BB1X1TS U7271 ( .A0N(P_Sgf[104]), .A1N(n5894), .B0(n5639), .Y(n5640) );
AOI21X1TS U7272 ( .A0(n6160), .A1(Add_result[51]), .B0(n5640), .Y(n5641) );
OAI2BB1X1TS U7273 ( .A0N(n5739), .A1N(P_Sgf[103]), .B0(n5641), .Y(n404) );
BUFX3TS U7274 ( .A(n5661), .Y(n6182) );
AOI22X1TS U7275 ( .A0(n6138), .A1(Add_result[51]), .B0(
Sgf_normalized_result[50]), .B1(n6179), .Y(n5644) );
OAI2BB1X1TS U7276 ( .A0N(P_Sgf[103]), .A1N(n6182), .B0(n5644), .Y(n5645) );
AOI21X1TS U7277 ( .A0(n6160), .A1(Add_result[50]), .B0(n5645), .Y(n5646) );
OAI2BB1X1TS U7278 ( .A0N(n5739), .A1N(P_Sgf[102]), .B0(n5646), .Y(n403) );
BUFX3TS U7279 ( .A(n5661), .Y(n6026) );
AOI22X1TS U7280 ( .A0(n6168), .A1(Add_result[50]), .B0(
Sgf_normalized_result[49]), .B1(n6013), .Y(n5650) );
OAI2BB1X1TS U7281 ( .A0N(n6026), .A1N(P_Sgf[102]), .B0(n5650), .Y(n5651) );
AOI21X1TS U7282 ( .A0(n6160), .A1(Add_result[49]), .B0(n5651), .Y(n5652) );
OAI2BB1X1TS U7283 ( .A0N(n5739), .A1N(P_Sgf[101]), .B0(n5652), .Y(n402) );
BUFX4TS U7284 ( .A(n5659), .Y(n5792) );
BUFX3TS U7285 ( .A(n5661), .Y(n5776) );
AOI22X1TS U7286 ( .A0(n6157), .A1(Add_result[49]), .B0(
Sgf_normalized_result[48]), .B1(n6179), .Y(n5662) );
OAI2BB1X1TS U7287 ( .A0N(n5776), .A1N(P_Sgf[101]), .B0(n5662), .Y(n5663) );
AOI21X1TS U7288 ( .A0(n6160), .A1(Add_result[48]), .B0(n5663), .Y(n5664) );
OAI2BB1X1TS U7289 ( .A0N(n5739), .A1N(P_Sgf[100]), .B0(n5664), .Y(n401) );
INVX2TS U7290 ( .A(n5733), .Y(n5724) );
INVX2TS U7291 ( .A(n5669), .Y(n5670) );
NOR2X1TS U7292 ( .A(n5697), .B(n5670), .Y(n5679) );
AOI22X1TS U7293 ( .A0(n6157), .A1(Add_result[48]), .B0(
Sgf_normalized_result[47]), .B1(n5774), .Y(n5674) );
OAI2BB1X1TS U7294 ( .A0N(n5776), .A1N(P_Sgf[100]), .B0(n5674), .Y(n5675) );
AOI21X1TS U7295 ( .A0(n6160), .A1(Add_result[47]), .B0(n5675), .Y(n5676) );
OAI2BB1X1TS U7296 ( .A0N(n5739), .A1N(P_Sgf[99]), .B0(n5676), .Y(n400) );
AOI22X1TS U7297 ( .A0(n6168), .A1(Add_result[47]), .B0(
Sgf_normalized_result[46]), .B1(n6041), .Y(n5683) );
OAI2BB1X1TS U7298 ( .A0N(n5776), .A1N(P_Sgf[99]), .B0(n5683), .Y(n5684) );
AOI21X1TS U7299 ( .A0(n6160), .A1(Add_result[46]), .B0(n5684), .Y(n5685) );
OAI2BB1X1TS U7300 ( .A0N(n5739), .A1N(P_Sgf[98]), .B0(n5685), .Y(n399) );
INVX2TS U7301 ( .A(n5697), .Y(n5688) );
AOI22X1TS U7302 ( .A0(n6138), .A1(Add_result[46]), .B0(
Sgf_normalized_result[45]), .B1(n6013), .Y(n5692) );
OAI2BB1X1TS U7303 ( .A0N(n5776), .A1N(P_Sgf[98]), .B0(n5692), .Y(n5693) );
AOI21X1TS U7304 ( .A0(n6160), .A1(Add_result[45]), .B0(n5693), .Y(n5694) );
OAI2BB1X1TS U7305 ( .A0N(n5739), .A1N(P_Sgf[97]), .B0(n5694), .Y(n398) );
AOI22X1TS U7306 ( .A0(n6157), .A1(Add_result[45]), .B0(
Sgf_normalized_result[44]), .B1(n5774), .Y(n5700) );
OAI2BB1X1TS U7307 ( .A0N(n5776), .A1N(P_Sgf[97]), .B0(n5700), .Y(n5701) );
AOI21X1TS U7308 ( .A0(n6160), .A1(Add_result[44]), .B0(n5701), .Y(n5702) );
OAI2BB1X1TS U7309 ( .A0N(n5739), .A1N(P_Sgf[96]), .B0(n5702), .Y(n397) );
INVX4TS U7310 ( .A(n1634), .Y(n5835) );
INVX2TS U7311 ( .A(n5705), .Y(n5706) );
NOR2X1TS U7312 ( .A(n5733), .B(n5706), .Y(n5715) );
AOI22X1TS U7313 ( .A0(n6168), .A1(Add_result[44]), .B0(
Sgf_normalized_result[43]), .B1(n6041), .Y(n5710) );
OAI2BB1X1TS U7314 ( .A0N(n5776), .A1N(P_Sgf[96]), .B0(n5710), .Y(n5711) );
AOI21X1TS U7315 ( .A0(n6160), .A1(Add_result[43]), .B0(n5711), .Y(n5712) );
OAI2BB1X1TS U7316 ( .A0N(n5739), .A1N(P_Sgf[95]), .B0(n5712), .Y(n396) );
AHHCINX2TS U7317 ( .A(Sgf_normalized_result[42]), .CIN(n5713), .S(n5714),
.CO(n5703) );
AOI22X1TS U7318 ( .A0(n6138), .A1(Add_result[43]), .B0(
Sgf_normalized_result[42]), .B1(n6013), .Y(n5719) );
OAI2BB1X1TS U7319 ( .A0N(n5776), .A1N(P_Sgf[95]), .B0(n5719), .Y(n5720) );
AOI21X1TS U7320 ( .A0(n6160), .A1(Add_result[42]), .B0(n5720), .Y(n5721) );
OAI2BB1X1TS U7321 ( .A0N(n5739), .A1N(P_Sgf[94]), .B0(n5721), .Y(n395) );
AHHCONX2TS U7322 ( .A(Sgf_normalized_result[41]), .CI(n5722), .CON(n5713),
.S(n5723) );
AOI22X1TS U7323 ( .A0(n6157), .A1(Add_result[42]), .B0(
Sgf_normalized_result[41]), .B1(n5774), .Y(n5728) );
OAI2BB1X1TS U7324 ( .A0N(n5776), .A1N(P_Sgf[94]), .B0(n5728), .Y(n5729) );
AOI21X1TS U7325 ( .A0(n6160), .A1(Add_result[41]), .B0(n5729), .Y(n5730) );
OAI2BB1X1TS U7326 ( .A0N(n5739), .A1N(P_Sgf[93]), .B0(n5730), .Y(n394) );
AHHCINX2TS U7327 ( .A(Sgf_normalized_result[40]), .CIN(n5731), .S(n5732),
.CO(n5722) );
AOI22X1TS U7328 ( .A0(n6168), .A1(Add_result[41]), .B0(
Sgf_normalized_result[40]), .B1(n6041), .Y(n5736) );
OAI2BB1X1TS U7329 ( .A0N(n5776), .A1N(P_Sgf[93]), .B0(n5736), .Y(n5737) );
AOI21X1TS U7330 ( .A0(n6160), .A1(Add_result[40]), .B0(n5737), .Y(n5738) );
OAI2BB1X1TS U7331 ( .A0N(n5739), .A1N(P_Sgf[92]), .B0(n5738), .Y(n393) );
AHHCONX2TS U7332 ( .A(Sgf_normalized_result[39]), .CI(n5740), .CON(n5731),
.S(n5741) );
INVX2TS U7333 ( .A(n5762), .Y(n5771) );
INVX2TS U7334 ( .A(n5742), .Y(n5743) );
NOR2X1TS U7335 ( .A(n5771), .B(n5743), .Y(n5753) );
BUFX3TS U7336 ( .A(n5747), .Y(n5991) );
CLKBUFX3TS U7337 ( .A(n5739), .Y(n5855) );
BUFX3TS U7338 ( .A(n5637), .Y(n6150) );
AOI22X1TS U7339 ( .A0(n6157), .A1(Add_result[40]), .B0(
Sgf_normalized_result[39]), .B1(n6041), .Y(n5748) );
OAI2BB1X1TS U7340 ( .A0N(n5776), .A1N(P_Sgf[92]), .B0(n5748), .Y(n5749) );
AOI21X1TS U7341 ( .A0(n6150), .A1(Add_result[39]), .B0(n5749), .Y(n5750) );
OAI2BB1X1TS U7342 ( .A0N(n5855), .A1N(P_Sgf[91]), .B0(n5750), .Y(n392) );
AHHCINX2TS U7343 ( .A(Sgf_normalized_result[38]), .CIN(n5751), .S(n5752),
.CO(n5740) );
AOI22X1TS U7344 ( .A0(n6168), .A1(Add_result[39]), .B0(
Sgf_normalized_result[38]), .B1(n6013), .Y(n5757) );
OAI2BB1X1TS U7345 ( .A0N(n5776), .A1N(P_Sgf[91]), .B0(n5757), .Y(n5758) );
AOI21X1TS U7346 ( .A0(n6150), .A1(Add_result[38]), .B0(n5758), .Y(n5759) );
OAI2BB1X1TS U7347 ( .A0N(n5855), .A1N(P_Sgf[90]), .B0(n5759), .Y(n391) );
AHHCONX2TS U7348 ( .A(Sgf_normalized_result[37]), .CI(n5760), .CON(n5751),
.S(n5761) );
AOI22X1TS U7349 ( .A0(n6138), .A1(Add_result[38]), .B0(
Sgf_normalized_result[37]), .B1(n5774), .Y(n5766) );
OAI2BB1X1TS U7350 ( .A0N(n5776), .A1N(P_Sgf[90]), .B0(n5766), .Y(n5767) );
AOI21X1TS U7351 ( .A0(n6150), .A1(Add_result[37]), .B0(n5767), .Y(n5768) );
OAI2BB1X1TS U7352 ( .A0N(n5855), .A1N(P_Sgf[89]), .B0(n5768), .Y(n390) );
AHHCINX2TS U7353 ( .A(Sgf_normalized_result[36]), .CIN(n5769), .S(n5770),
.CO(n5760) );
AOI22X1TS U7354 ( .A0(n6157), .A1(Add_result[37]), .B0(
Sgf_normalized_result[36]), .B1(n6041), .Y(n5775) );
OAI2BB1X1TS U7355 ( .A0N(n5776), .A1N(P_Sgf[89]), .B0(n5775), .Y(n5777) );
AOI21X1TS U7356 ( .A0(n6150), .A1(Add_result[36]), .B0(n5777), .Y(n5778) );
OAI2BB1X1TS U7357 ( .A0N(n5855), .A1N(P_Sgf[88]), .B0(n5778), .Y(n389) );
AHHCONX2TS U7358 ( .A(Sgf_normalized_result[35]), .CI(n5779), .CON(n5769),
.S(n5780) );
INVX2TS U7359 ( .A(n5790), .Y(n5781) );
AOI22X1TS U7360 ( .A0(n6168), .A1(Add_result[36]), .B0(
Sgf_normalized_result[35]), .B1(n6041), .Y(n5785) );
OAI2BB1X1TS U7361 ( .A0N(n5894), .A1N(P_Sgf[88]), .B0(n5785), .Y(n5786) );
AOI21X1TS U7362 ( .A0(n6150), .A1(Add_result[35]), .B0(n5786), .Y(n5787) );
OAI2BB1X1TS U7363 ( .A0N(n5855), .A1N(P_Sgf[87]), .B0(n5787), .Y(n388) );
AHHCINX2TS U7364 ( .A(Sgf_normalized_result[34]), .CIN(n5788), .S(n5789),
.CO(n5779) );
AOI22X1TS U7365 ( .A0(n6138), .A1(Add_result[35]), .B0(
Sgf_normalized_result[34]), .B1(n6013), .Y(n5794) );
OAI2BB1X1TS U7366 ( .A0N(n5894), .A1N(P_Sgf[87]), .B0(n5794), .Y(n5795) );
AOI21X1TS U7367 ( .A0(n6150), .A1(Add_result[34]), .B0(n5795), .Y(n5796) );
OAI2BB1X1TS U7368 ( .A0N(n5855), .A1N(P_Sgf[86]), .B0(n5796), .Y(n387) );
AHHCONX2TS U7369 ( .A(Sgf_normalized_result[33]), .CI(n5797), .CON(n5788),
.S(n5798) );
BUFX4TS U7370 ( .A(n6202), .Y(n5944) );
AOI22X1TS U7371 ( .A0(n6157), .A1(Add_result[34]), .B0(
Sgf_normalized_result[33]), .B1(n5774), .Y(n5801) );
OAI2BB1X1TS U7372 ( .A0N(n5894), .A1N(P_Sgf[86]), .B0(n5801), .Y(n5802) );
AOI21X1TS U7373 ( .A0(n6150), .A1(Add_result[33]), .B0(n5802), .Y(n5803) );
OAI2BB1X1TS U7374 ( .A0N(n5855), .A1N(P_Sgf[85]), .B0(n5803), .Y(n386) );
AHHCINX2TS U7375 ( .A(Sgf_normalized_result[32]), .CIN(n5804), .S(n5805),
.CO(n5797) );
MX2X1TS U7376 ( .A(n5805), .B(Add_result[32]), .S0(n5835), .Y(n547) );
AOI22X1TS U7377 ( .A0(n6168), .A1(Add_result[33]), .B0(
Sgf_normalized_result[32]), .B1(n6041), .Y(n5808) );
OAI2BB1X1TS U7378 ( .A0N(n5894), .A1N(P_Sgf[85]), .B0(n5808), .Y(n5809) );
AOI21X1TS U7379 ( .A0(n6150), .A1(Add_result[32]), .B0(n5809), .Y(n5810) );
OAI2BB1X1TS U7380 ( .A0N(n5855), .A1N(P_Sgf[84]), .B0(n5810), .Y(n385) );
AHHCONX2TS U7381 ( .A(Sgf_normalized_result[31]), .CI(n5811), .CON(n5804),
.S(n5812) );
MX2X1TS U7382 ( .A(n5812), .B(Add_result[31]), .S0(n5835), .Y(n548) );
AOI22X1TS U7383 ( .A0(n6138), .A1(Add_result[32]), .B0(
Sgf_normalized_result[31]), .B1(n6013), .Y(n5820) );
OAI2BB1X1TS U7384 ( .A0N(n5894), .A1N(P_Sgf[84]), .B0(n5820), .Y(n5821) );
AOI21X1TS U7385 ( .A0(n6150), .A1(Add_result[31]), .B0(n5821), .Y(n5822) );
OAI2BB1X1TS U7386 ( .A0N(n5855), .A1N(P_Sgf[83]), .B0(n5822), .Y(n384) );
AHHCINX2TS U7387 ( .A(Sgf_normalized_result[30]), .CIN(n5823), .S(n5824),
.CO(n5811) );
MX2X1TS U7388 ( .A(n5824), .B(Add_result[30]), .S0(n5835), .Y(n549) );
AOI22X1TS U7389 ( .A0(n6157), .A1(Add_result[31]), .B0(
Sgf_normalized_result[30]), .B1(n5774), .Y(n5831) );
OAI2BB1X1TS U7390 ( .A0N(n5894), .A1N(P_Sgf[83]), .B0(n5831), .Y(n5832) );
AOI21X1TS U7391 ( .A0(n6150), .A1(Add_result[30]), .B0(n5832), .Y(n5833) );
OAI2BB1X1TS U7392 ( .A0N(n5855), .A1N(P_Sgf[82]), .B0(n5833), .Y(n383) );
AHHCONX2TS U7393 ( .A(Sgf_normalized_result[29]), .CI(n5834), .CON(n5823),
.S(n5836) );
MX2X1TS U7394 ( .A(n5836), .B(Add_result[29]), .S0(n5835), .Y(n550) );
AOI22X1TS U7395 ( .A0(n6168), .A1(Add_result[30]), .B0(
Sgf_normalized_result[29]), .B1(n6041), .Y(n5843) );
OAI2BB1X1TS U7396 ( .A0N(n5894), .A1N(P_Sgf[82]), .B0(n5843), .Y(n5844) );
AOI21X1TS U7397 ( .A0(n6150), .A1(Add_result[29]), .B0(n5844), .Y(n5845) );
OAI2BB1X1TS U7398 ( .A0N(n5855), .A1N(P_Sgf[81]), .B0(n5845), .Y(n382) );
AHHCINX2TS U7399 ( .A(Sgf_normalized_result[28]), .CIN(n5846), .S(n5847),
.CO(n5834) );
INVX4TS U7400 ( .A(n1634), .Y(n6030) );
MX2X1TS U7401 ( .A(n5847), .B(Add_result[28]), .S0(n6030), .Y(n551) );
AOI22X1TS U7402 ( .A0(n6138), .A1(Add_result[29]), .B0(
Sgf_normalized_result[28]), .B1(n6013), .Y(n5852) );
OAI2BB1X1TS U7403 ( .A0N(n5894), .A1N(P_Sgf[81]), .B0(n5852), .Y(n5853) );
AOI21X1TS U7404 ( .A0(n6150), .A1(Add_result[28]), .B0(n5853), .Y(n5854) );
OAI2BB1X1TS U7405 ( .A0N(n5855), .A1N(P_Sgf[80]), .B0(n5854), .Y(n381) );
AHHCONX2TS U7406 ( .A(Sgf_normalized_result[27]), .CI(n5856), .CON(n5846),
.S(n5857) );
MX2X1TS U7407 ( .A(n5857), .B(Add_result[27]), .S0(n6030), .Y(n552) );
INVX2TS U7408 ( .A(n5858), .Y(n5860) );
NAND2X1TS U7409 ( .A(n5860), .B(n5859), .Y(n5862) );
AOI22X1TS U7410 ( .A0(n6180), .A1(Add_result[28]), .B0(
Sgf_normalized_result[27]), .B1(n5774), .Y(n5864) );
OAI2BB1X1TS U7411 ( .A0N(n5894), .A1N(P_Sgf[80]), .B0(n5864), .Y(n5865) );
AOI21X1TS U7412 ( .A0(n5637), .A1(Add_result[27]), .B0(n5865), .Y(n5866) );
OAI2BB1X1TS U7413 ( .A0N(n5991), .A1N(P_Sgf[79]), .B0(n5866), .Y(n380) );
AHHCINX2TS U7414 ( .A(Sgf_normalized_result[26]), .CIN(n5867), .S(n5868),
.CO(n5856) );
MX2X1TS U7415 ( .A(n5868), .B(Add_result[26]), .S0(n6030), .Y(n553) );
NAND2X1TS U7416 ( .A(n818), .B(n5869), .Y(n5871) );
AOI22X1TS U7417 ( .A0(n6180), .A1(Add_result[27]), .B0(
Sgf_normalized_result[26]), .B1(n6041), .Y(n5873) );
OAI2BB1X1TS U7418 ( .A0N(n5894), .A1N(P_Sgf[79]), .B0(n5873), .Y(n5874) );
AOI21X1TS U7419 ( .A0(n5637), .A1(Add_result[26]), .B0(n5874), .Y(n5875) );
OAI2BB1X1TS U7420 ( .A0N(n5991), .A1N(P_Sgf[78]), .B0(n5875), .Y(n379) );
AHHCONX2TS U7421 ( .A(Sgf_normalized_result[25]), .CI(n5876), .CON(n5867),
.S(n5877) );
MX2X1TS U7422 ( .A(n5877), .B(Add_result[25]), .S0(n6030), .Y(n554) );
INVX2TS U7423 ( .A(n5878), .Y(n5880) );
AOI22X1TS U7424 ( .A0(n6180), .A1(Add_result[26]), .B0(
Sgf_normalized_result[25]), .B1(n6013), .Y(n5884) );
OAI2BB1X1TS U7425 ( .A0N(n5894), .A1N(P_Sgf[78]), .B0(n5884), .Y(n5885) );
AOI21X1TS U7426 ( .A0(n5637), .A1(Add_result[25]), .B0(n5885), .Y(n5886) );
OAI2BB1X1TS U7427 ( .A0N(n5991), .A1N(P_Sgf[77]), .B0(n5886), .Y(n378) );
AHHCINX2TS U7428 ( .A(Sgf_normalized_result[24]), .CIN(n5887), .S(n5888),
.CO(n5876) );
MX2X1TS U7429 ( .A(n5888), .B(Add_result[24]), .S0(n6030), .Y(n555) );
NAND2X1TS U7430 ( .A(n819), .B(n5889), .Y(n5891) );
XNOR2X1TS U7431 ( .A(n5891), .B(n5890), .Y(n5892) );
AOI22X1TS U7432 ( .A0(n6180), .A1(Add_result[25]), .B0(
Sgf_normalized_result[24]), .B1(n6179), .Y(n5893) );
OAI2BB1X1TS U7433 ( .A0N(n5894), .A1N(P_Sgf[77]), .B0(n5893), .Y(n5895) );
AOI21X1TS U7434 ( .A0(n5637), .A1(Add_result[24]), .B0(n5895), .Y(n5896) );
OAI2BB1X1TS U7435 ( .A0N(n5991), .A1N(P_Sgf[76]), .B0(n5896), .Y(n377) );
AHHCONX2TS U7436 ( .A(Sgf_normalized_result[23]), .CI(n5897), .CON(n5887),
.S(n5898) );
MX2X1TS U7437 ( .A(n5898), .B(Add_result[23]), .S0(n6030), .Y(n556) );
INVX2TS U7438 ( .A(n5899), .Y(n5901) );
NAND2X1TS U7439 ( .A(n5901), .B(n5900), .Y(n5903) );
AOI22X1TS U7440 ( .A0(n6180), .A1(Add_result[24]), .B0(
Sgf_normalized_result[23]), .B1(n6179), .Y(n5905) );
OAI2BB1X1TS U7441 ( .A0N(n6026), .A1N(P_Sgf[76]), .B0(n5905), .Y(n5906) );
AOI21X1TS U7442 ( .A0(n5637), .A1(Add_result[23]), .B0(n5906), .Y(n5907) );
OAI2BB1X1TS U7443 ( .A0N(n5991), .A1N(P_Sgf[75]), .B0(n5907), .Y(n376) );
AHHCINX2TS U7444 ( .A(Sgf_normalized_result[22]), .CIN(n5908), .S(n5909),
.CO(n5897) );
MX2X1TS U7445 ( .A(n5909), .B(Add_result[22]), .S0(n6030), .Y(n557) );
NAND2X1TS U7446 ( .A(n820), .B(n5910), .Y(n5912) );
XNOR2X1TS U7447 ( .A(n5912), .B(n5911), .Y(n5913) );
AOI22X1TS U7448 ( .A0(n6180), .A1(Add_result[23]), .B0(
Sgf_normalized_result[22]), .B1(n6179), .Y(n5914) );
OAI2BB1X1TS U7449 ( .A0N(n6026), .A1N(P_Sgf[75]), .B0(n5914), .Y(n5915) );
AOI21X1TS U7450 ( .A0(n5637), .A1(Add_result[22]), .B0(n5915), .Y(n5916) );
OAI2BB1X1TS U7451 ( .A0N(n5991), .A1N(P_Sgf[74]), .B0(n5916), .Y(n375) );
AHHCONX2TS U7452 ( .A(Sgf_normalized_result[21]), .CI(n5917), .CON(n5908),
.S(n5918) );
MX2X1TS U7453 ( .A(n5918), .B(Add_result[21]), .S0(n6030), .Y(n558) );
INVX2TS U7454 ( .A(n5919), .Y(n5921) );
NAND2X1TS U7455 ( .A(n5921), .B(n5920), .Y(n5923) );
AOI22X1TS U7456 ( .A0(n6180), .A1(Add_result[22]), .B0(
Sgf_normalized_result[21]), .B1(n6179), .Y(n5925) );
OAI2BB1X1TS U7457 ( .A0N(n6026), .A1N(P_Sgf[74]), .B0(n5925), .Y(n5926) );
AOI21X1TS U7458 ( .A0(n5637), .A1(Add_result[21]), .B0(n5926), .Y(n5927) );
OAI2BB1X1TS U7459 ( .A0N(n5991), .A1N(P_Sgf[73]), .B0(n5927), .Y(n374) );
AHHCINX2TS U7460 ( .A(Sgf_normalized_result[20]), .CIN(n5928), .S(n5929),
.CO(n5917) );
MX2X1TS U7461 ( .A(n5929), .B(Add_result[20]), .S0(n6030), .Y(n559) );
NAND2X1TS U7462 ( .A(n821), .B(n5930), .Y(n5932) );
XNOR2X1TS U7463 ( .A(n5932), .B(n5931), .Y(n5933) );
AOI22X1TS U7464 ( .A0(n6180), .A1(Add_result[21]), .B0(
Sgf_normalized_result[20]), .B1(n6013), .Y(n5934) );
OAI2BB1X1TS U7465 ( .A0N(n6026), .A1N(P_Sgf[73]), .B0(n5934), .Y(n5935) );
AOI21X1TS U7466 ( .A0(n5637), .A1(Add_result[20]), .B0(n5935), .Y(n5936) );
OAI2BB1X1TS U7467 ( .A0N(n5991), .A1N(P_Sgf[72]), .B0(n5936), .Y(n373) );
AHHCONX2TS U7468 ( .A(Sgf_normalized_result[19]), .CI(n5937), .CON(n5928),
.S(n5938) );
MX2X1TS U7469 ( .A(n5938), .B(Add_result[19]), .S0(n6030), .Y(n560) );
INVX2TS U7470 ( .A(n5939), .Y(n5941) );
NAND2X1TS U7471 ( .A(n5941), .B(n5940), .Y(n5943) );
AOI22X1TS U7472 ( .A0(n6180), .A1(Add_result[20]), .B0(
Sgf_normalized_result[19]), .B1(n5774), .Y(n5946) );
OAI2BB1X1TS U7473 ( .A0N(n6026), .A1N(P_Sgf[72]), .B0(n5946), .Y(n5947) );
AOI21X1TS U7474 ( .A0(n5637), .A1(Add_result[19]), .B0(n5947), .Y(n5948) );
OAI2BB1X1TS U7475 ( .A0N(n5991), .A1N(P_Sgf[71]), .B0(n5948), .Y(n372) );
AHHCINX2TS U7476 ( .A(Sgf_normalized_result[18]), .CIN(n5949), .S(n5950),
.CO(n5937) );
MX2X1TS U7477 ( .A(n5950), .B(Add_result[18]), .S0(n6030), .Y(n561) );
NAND2X1TS U7478 ( .A(n822), .B(n5951), .Y(n5953) );
XNOR2X1TS U7479 ( .A(n5953), .B(n5952), .Y(n5954) );
BUFX4TS U7480 ( .A(n6202), .Y(n6136) );
AOI22X1TS U7481 ( .A0(n6180), .A1(Add_result[19]), .B0(
Sgf_normalized_result[18]), .B1(n6041), .Y(n5955) );
OAI2BB1X1TS U7482 ( .A0N(n6026), .A1N(P_Sgf[71]), .B0(n5955), .Y(n5956) );
AOI21X1TS U7483 ( .A0(n5637), .A1(Add_result[18]), .B0(n5956), .Y(n5957) );
OAI2BB1X1TS U7484 ( .A0N(n5991), .A1N(P_Sgf[70]), .B0(n5957), .Y(n371) );
AHHCONX2TS U7485 ( .A(Sgf_normalized_result[17]), .CI(n5958), .CON(n5949),
.S(n5959) );
MX2X1TS U7486 ( .A(n5959), .B(Add_result[17]), .S0(n6030), .Y(n562) );
INVX2TS U7487 ( .A(n5960), .Y(n5962) );
NAND2X1TS U7488 ( .A(n5962), .B(n5961), .Y(n5964) );
AOI22X1TS U7489 ( .A0(n6138), .A1(Add_result[18]), .B0(
Sgf_normalized_result[17]), .B1(n6013), .Y(n5966) );
OAI2BB1X1TS U7490 ( .A0N(n6026), .A1N(P_Sgf[70]), .B0(n5966), .Y(n5967) );
AOI21X1TS U7491 ( .A0(n5637), .A1(Add_result[17]), .B0(n5967), .Y(n5968) );
OAI2BB1X1TS U7492 ( .A0N(n5991), .A1N(P_Sgf[69]), .B0(n5968), .Y(n370) );
NAND2X1TS U7493 ( .A(n6045), .B(n5970), .Y(n5982) );
INVX2TS U7494 ( .A(n5982), .Y(n5996) );
INVX2TS U7495 ( .A(n5971), .Y(n5972) );
NAND2X1TS U7496 ( .A(n5996), .B(n5972), .Y(n5973) );
XOR2XLTS U7497 ( .A(n5973), .B(n6542), .Y(n5974) );
MX2X1TS U7498 ( .A(n5974), .B(Add_result[16]), .S0(n6030), .Y(n563) );
NAND2X1TS U7499 ( .A(n823), .B(n5975), .Y(n5977) );
XNOR2X1TS U7500 ( .A(n5977), .B(n5976), .Y(n5978) );
AOI22X1TS U7501 ( .A0(n6157), .A1(Add_result[17]), .B0(
Sgf_normalized_result[16]), .B1(n5774), .Y(n5979) );
OAI2BB1X1TS U7502 ( .A0N(n6026), .A1N(P_Sgf[69]), .B0(n5979), .Y(n5980) );
AOI21X1TS U7503 ( .A0(n5637), .A1(Add_result[16]), .B0(n5980), .Y(n5981) );
OAI2BB1X1TS U7504 ( .A0N(n5991), .A1N(P_Sgf[68]), .B0(n5981), .Y(n369) );
NOR2XLTS U7505 ( .A(n5982), .B(n6573), .Y(n5983) );
XNOR2X1TS U7506 ( .A(n5983), .B(n6577), .Y(n5984) );
MX2X1TS U7507 ( .A(n5984), .B(Add_result[15]), .S0(n6030), .Y(n564) );
INVX2TS U7508 ( .A(n5985), .Y(n5999) );
AOI21X1TS U7509 ( .A0(n5999), .A1(n824), .B0(n5986), .Y(n5989) );
NAND2X1TS U7510 ( .A(n816), .B(n5987), .Y(n5988) );
XOR2X1TS U7511 ( .A(n5989), .B(n5988), .Y(n5990) );
BUFX3TS U7512 ( .A(n5991), .Y(n6142) );
AOI22X1TS U7513 ( .A0(n6168), .A1(Add_result[16]), .B0(
Sgf_normalized_result[15]), .B1(n5774), .Y(n5993) );
OAI2BB1X1TS U7514 ( .A0N(n6026), .A1N(P_Sgf[68]), .B0(n5993), .Y(n5994) );
AOI21X1TS U7515 ( .A0(n6184), .A1(Add_result[15]), .B0(n5994), .Y(n5995) );
OAI2BB1X1TS U7516 ( .A0N(n6142), .A1N(P_Sgf[67]), .B0(n5995), .Y(n368) );
XNOR2X1TS U7517 ( .A(n5996), .B(n6573), .Y(n5997) );
MX2X1TS U7518 ( .A(n5997), .B(Add_result[14]), .S0(n6187), .Y(n565) );
NAND2X1TS U7519 ( .A(n824), .B(n5998), .Y(n6000) );
XNOR2X1TS U7520 ( .A(n6000), .B(n5999), .Y(n6001) );
AOI22X1TS U7521 ( .A0(n6157), .A1(Add_result[15]), .B0(
Sgf_normalized_result[14]), .B1(n6041), .Y(n6002) );
OAI2BB1X1TS U7522 ( .A0N(n6026), .A1N(P_Sgf[67]), .B0(n6002), .Y(n6003) );
AOI21X1TS U7523 ( .A0(n6184), .A1(Add_result[14]), .B0(n6003), .Y(n6004) );
OAI2BB1X1TS U7524 ( .A0N(n6142), .A1N(P_Sgf[66]), .B0(n6004), .Y(n367) );
INVX2TS U7525 ( .A(n6005), .Y(n6006) );
NAND2X1TS U7526 ( .A(n6045), .B(n6006), .Y(n6017) );
NOR2XLTS U7527 ( .A(n6017), .B(n6571), .Y(n6007) );
XNOR2X1TS U7528 ( .A(n6007), .B(n6578), .Y(n6008) );
MX2X1TS U7529 ( .A(n6008), .B(Add_result[13]), .S0(n6187), .Y(n566) );
NAND2X1TS U7530 ( .A(n815), .B(n6009), .Y(n6010) );
XNOR2X1TS U7531 ( .A(n6011), .B(n6010), .Y(n6012) );
MX2X1TS U7532 ( .A(P_Sgf[65]), .B(n6012), .S0(n6136), .Y(n486) );
AOI22X1TS U7533 ( .A0(n6138), .A1(Add_result[14]), .B0(
Sgf_normalized_result[13]), .B1(n6013), .Y(n6014) );
OAI2BB1X1TS U7534 ( .A0N(n6026), .A1N(P_Sgf[66]), .B0(n6014), .Y(n6015) );
AOI21X1TS U7535 ( .A0(n6184), .A1(Add_result[13]), .B0(n6015), .Y(n6016) );
OAI2BB1X1TS U7536 ( .A0N(n6142), .A1N(P_Sgf[65]), .B0(n6016), .Y(n366) );
XOR2XLTS U7537 ( .A(n6017), .B(n6571), .Y(n6018) );
MX2X1TS U7538 ( .A(n6018), .B(Add_result[12]), .S0(n6187), .Y(n567) );
INVX2TS U7539 ( .A(n6019), .Y(n6021) );
NAND2X1TS U7540 ( .A(n6021), .B(n6020), .Y(n6022) );
MX2X1TS U7541 ( .A(P_Sgf[64]), .B(n6024), .S0(n6136), .Y(n485) );
AOI22X1TS U7542 ( .A0(n6168), .A1(Add_result[13]), .B0(
Sgf_normalized_result[12]), .B1(n6013), .Y(n6025) );
OAI2BB1X1TS U7543 ( .A0N(n6026), .A1N(P_Sgf[65]), .B0(n6025), .Y(n6027) );
AOI21X1TS U7544 ( .A0(n6184), .A1(Add_result[12]), .B0(n6027), .Y(n6028) );
OAI2BB1X1TS U7545 ( .A0N(n6142), .A1N(P_Sgf[64]), .B0(n6028), .Y(n365) );
NAND2X1TS U7546 ( .A(n6045), .B(Sgf_normalized_result[10]), .Y(n6029) );
XOR2XLTS U7547 ( .A(n6029), .B(n6575), .Y(n6031) );
MX2X1TS U7548 ( .A(n6031), .B(Add_result[11]), .S0(n6030), .Y(n568) );
INVX2TS U7549 ( .A(n6032), .Y(n6077) );
INVX2TS U7550 ( .A(n6035), .Y(n6037) );
NAND2X1TS U7551 ( .A(n6037), .B(n6036), .Y(n6038) );
XNOR2X1TS U7552 ( .A(n6039), .B(n6038), .Y(n6040) );
MX2X1TS U7553 ( .A(P_Sgf[63]), .B(n6040), .S0(n6136), .Y(n484) );
AOI22X1TS U7554 ( .A0(n6157), .A1(Add_result[12]), .B0(
Sgf_normalized_result[11]), .B1(n5774), .Y(n6042) );
OAI2BB1X1TS U7555 ( .A0N(n6182), .A1N(P_Sgf[64]), .B0(n6042), .Y(n6043) );
AOI21X1TS U7556 ( .A0(n6184), .A1(Add_result[11]), .B0(n6043), .Y(n6044) );
OAI2BB1X1TS U7557 ( .A0N(n6142), .A1N(P_Sgf[63]), .B0(n6044), .Y(n364) );
XNOR2X1TS U7558 ( .A(n6045), .B(n6569), .Y(n6046) );
MX2X1TS U7559 ( .A(n6046), .B(Add_result[10]), .S0(n6187), .Y(n569) );
INVX2TS U7560 ( .A(n6047), .Y(n6050) );
INVX2TS U7561 ( .A(n6048), .Y(n6049) );
NAND2X1TS U7562 ( .A(n825), .B(n6051), .Y(n6052) );
XNOR2X1TS U7563 ( .A(n6053), .B(n6052), .Y(n6054) );
MX2X1TS U7564 ( .A(P_Sgf[62]), .B(n6054), .S0(n6136), .Y(n483) );
AOI22X1TS U7565 ( .A0(n6138), .A1(Add_result[11]), .B0(
Sgf_normalized_result[10]), .B1(n5774), .Y(n6055) );
OAI2BB1X1TS U7566 ( .A0N(n6182), .A1N(P_Sgf[63]), .B0(n6055), .Y(n6056) );
AOI21X1TS U7567 ( .A0(n6184), .A1(Add_result[10]), .B0(n6056), .Y(n6057) );
OAI2BB1X1TS U7568 ( .A0N(n6142), .A1N(P_Sgf[62]), .B0(n6057), .Y(n363) );
NOR2X1TS U7569 ( .A(n6102), .B(n6059), .Y(n6071) );
NAND2X1TS U7570 ( .A(n6071), .B(Sgf_normalized_result[8]), .Y(n6060) );
XOR2XLTS U7571 ( .A(n6060), .B(n6576), .Y(n6061) );
MX2X1TS U7572 ( .A(n6061), .B(Add_result[9]), .S0(n6187), .Y(n570) );
INVX2TS U7573 ( .A(n6062), .Y(n6064) );
NAND2X1TS U7574 ( .A(n6064), .B(n6063), .Y(n6065) );
XNOR2X1TS U7575 ( .A(n6066), .B(n6065), .Y(n6067) );
MX2X1TS U7576 ( .A(P_Sgf[61]), .B(n6067), .S0(n6136), .Y(n482) );
AOI22X1TS U7577 ( .A0(n6157), .A1(Add_result[10]), .B0(
Sgf_normalized_result[9]), .B1(n6041), .Y(n6068) );
OAI2BB1X1TS U7578 ( .A0N(n6182), .A1N(P_Sgf[62]), .B0(n6068), .Y(n6069) );
AOI21X1TS U7579 ( .A0(n6184), .A1(Add_result[9]), .B0(n6069), .Y(n6070) );
OAI2BB1X1TS U7580 ( .A0N(n6142), .A1N(P_Sgf[61]), .B0(n6070), .Y(n362) );
XNOR2X1TS U7581 ( .A(n6071), .B(n6570), .Y(n6072) );
MX2X1TS U7582 ( .A(n6072), .B(Add_result[8]), .S0(n6187), .Y(n571) );
INVX2TS U7583 ( .A(n6073), .Y(n6075) );
NAND2X1TS U7584 ( .A(n6075), .B(n6074), .Y(n6076) );
XOR2X1TS U7585 ( .A(n6077), .B(n6076), .Y(n6078) );
MX2X1TS U7586 ( .A(P_Sgf[60]), .B(n6078), .S0(n6136), .Y(n481) );
AOI22X1TS U7587 ( .A0(n6168), .A1(Add_result[9]), .B0(
Sgf_normalized_result[8]), .B1(n6013), .Y(n6079) );
OAI2BB1X1TS U7588 ( .A0N(n6182), .A1N(P_Sgf[61]), .B0(n6079), .Y(n6080) );
AOI21X1TS U7589 ( .A0(n6184), .A1(Add_result[8]), .B0(n6080), .Y(n6081) );
OAI2BB1X1TS U7590 ( .A0N(n6142), .A1N(P_Sgf[60]), .B0(n6081), .Y(n361) );
XNOR2X1TS U7591 ( .A(n6082), .B(n6579), .Y(n6083) );
MX2X1TS U7592 ( .A(n6083), .B(Add_result[7]), .S0(n6187), .Y(n572) );
INVX2TS U7593 ( .A(n6084), .Y(n6206) );
AOI21X1TS U7594 ( .A0(n6206), .A1(n875), .B0(n6085), .Y(n6172) );
INVX2TS U7595 ( .A(n6172), .Y(n6212) );
INVX2TS U7596 ( .A(n6086), .Y(n6089) );
INVX2TS U7597 ( .A(n6087), .Y(n6088) );
INVX2TS U7598 ( .A(n6132), .Y(n6146) );
INVX2TS U7599 ( .A(n6093), .Y(n6095) );
NAND2X1TS U7600 ( .A(n6095), .B(n6094), .Y(n6096) );
XNOR2X1TS U7601 ( .A(n6097), .B(n6096), .Y(n6098) );
AOI22X1TS U7602 ( .A0(n6138), .A1(Add_result[8]), .B0(
Sgf_normalized_result[7]), .B1(n5774), .Y(n6099) );
OAI2BB1X1TS U7603 ( .A0N(n6182), .A1N(P_Sgf[60]), .B0(n6099), .Y(n6100) );
AOI21X1TS U7604 ( .A0(n6184), .A1(Add_result[7]), .B0(n6100), .Y(n6101) );
OAI2BB1X1TS U7605 ( .A0N(n6142), .A1N(P_Sgf[59]), .B0(n6101), .Y(n360) );
XOR2XLTS U7606 ( .A(n6102), .B(n6572), .Y(n6103) );
MX2X1TS U7607 ( .A(n6103), .B(Add_result[6]), .S0(n6187), .Y(n573) );
INVX2TS U7608 ( .A(n6104), .Y(n6107) );
INVX2TS U7609 ( .A(n6105), .Y(n6106) );
NAND2X1TS U7610 ( .A(n814), .B(n6108), .Y(n6109) );
XNOR2X1TS U7611 ( .A(n6110), .B(n6109), .Y(n6111) );
AOI22X1TS U7612 ( .A0(n6157), .A1(Add_result[7]), .B0(
Sgf_normalized_result[6]), .B1(n6041), .Y(n6112) );
OAI2BB1X1TS U7613 ( .A0N(n6182), .A1N(P_Sgf[59]), .B0(n6112), .Y(n6113) );
AOI21X1TS U7614 ( .A0(n6184), .A1(Add_result[6]), .B0(n6113), .Y(n6114) );
OAI2BB1X1TS U7615 ( .A0N(n6142), .A1N(P_Sgf[58]), .B0(n6114), .Y(n359) );
NOR2XLTS U7616 ( .A(n6115), .B(Sgf_normalized_result[4]), .Y(n6116) );
XOR2XLTS U7617 ( .A(n6116), .B(Sgf_normalized_result[5]), .Y(n6117) );
MX2X1TS U7618 ( .A(n6117), .B(Add_result[5]), .S0(n6187), .Y(n574) );
INVX2TS U7619 ( .A(n6120), .Y(n6122) );
NAND2X1TS U7620 ( .A(n6122), .B(n6121), .Y(n6123) );
XNOR2X1TS U7621 ( .A(n6124), .B(n6123), .Y(n6125) );
AOI22X1TS U7622 ( .A0(n6168), .A1(Add_result[6]), .B0(
Sgf_normalized_result[5]), .B1(n6179), .Y(n6126) );
OAI2BB1X1TS U7623 ( .A0N(n6182), .A1N(P_Sgf[58]), .B0(n6126), .Y(n6127) );
AOI21X1TS U7624 ( .A0(n6184), .A1(Add_result[5]), .B0(n6127), .Y(n6128) );
OAI2BB1X1TS U7625 ( .A0N(n6142), .A1N(P_Sgf[57]), .B0(n6128), .Y(n358) );
XOR2XLTS U7626 ( .A(n6129), .B(Sgf_normalized_result[4]), .Y(n6130) );
MX2X1TS U7627 ( .A(n6130), .B(Add_result[4]), .S0(n6187), .Y(n575) );
AOI21X1TS U7628 ( .A0(n6132), .A1(n752), .B0(n6131), .Y(n6135) );
NAND2X1TS U7629 ( .A(n813), .B(n6133), .Y(n6134) );
XOR2X1TS U7630 ( .A(n6135), .B(n6134), .Y(n6137) );
AOI22X1TS U7631 ( .A0(n6138), .A1(Add_result[5]), .B0(
Sgf_normalized_result[4]), .B1(n6179), .Y(n6139) );
OAI2BB1X1TS U7632 ( .A0N(n6182), .A1N(P_Sgf[57]), .B0(n6139), .Y(n6140) );
AOI21X1TS U7633 ( .A0(n6184), .A1(Add_result[4]), .B0(n6140), .Y(n6141) );
OAI2BB1X1TS U7634 ( .A0N(n6142), .A1N(P_Sgf[56]), .B0(n6141), .Y(n357) );
AHHCONX2TS U7635 ( .A(n773), .CI(Sgf_normalized_result[2]), .CON(n6129), .S(
n6143) );
MX2X1TS U7636 ( .A(n6143), .B(Add_result[3]), .S0(n6187), .Y(n576) );
XOR2X1TS U7637 ( .A(n6146), .B(n6145), .Y(n6147) );
AOI22X1TS U7638 ( .A0(n6180), .A1(Add_result[4]), .B0(n773), .B1(n6179), .Y(
n6148) );
OAI2BB1X1TS U7639 ( .A0N(n6182), .A1N(P_Sgf[56]), .B0(n6148), .Y(n6149) );
AOI21X1TS U7640 ( .A0(n6150), .A1(Add_result[3]), .B0(n6149), .Y(n6151) );
OAI2BB1X1TS U7641 ( .A0N(n5739), .A1N(P_Sgf[55]), .B0(n6151), .Y(n356) );
NAND2X1TS U7642 ( .A(n6153), .B(n6152), .Y(n6154) );
XOR2X1TS U7643 ( .A(n6155), .B(n6154), .Y(n6156) );
MX2X1TS U7644 ( .A(P_Sgf[54]), .B(n6156), .S0(n6339), .Y(n475) );
AOI22X1TS U7645 ( .A0(n6180), .A1(Add_result[3]), .B0(
Sgf_normalized_result[2]), .B1(n6179), .Y(n6158) );
OAI2BB1X1TS U7646 ( .A0N(n6182), .A1N(P_Sgf[55]), .B0(n6158), .Y(n6159) );
AOI21X1TS U7647 ( .A0(n6160), .A1(Add_result[2]), .B0(n6159), .Y(n6161) );
OAI2BB1X1TS U7648 ( .A0N(n5739), .A1N(P_Sgf[54]), .B0(n6161), .Y(n355) );
AOI21X1TS U7649 ( .A0(n6212), .A1(n6163), .B0(n6162), .Y(n6166) );
NAND2X1TS U7650 ( .A(n836), .B(n6164), .Y(n6165) );
XOR2X1TS U7651 ( .A(n6166), .B(n6165), .Y(n6167) );
MX2X1TS U7652 ( .A(P_Sgf[53]), .B(n6167), .S0(n6339), .Y(n474) );
AOI22X1TS U7653 ( .A0(n6138), .A1(Add_result[2]), .B0(
Sgf_normalized_result[1]), .B1(n6179), .Y(n6169) );
OAI2BB1X1TS U7654 ( .A0N(n6182), .A1N(P_Sgf[54]), .B0(n6169), .Y(n6170) );
AOI21X1TS U7655 ( .A0(n6184), .A1(Add_result[1]), .B0(n6170), .Y(n6171) );
OAI2BB1X1TS U7656 ( .A0N(n6142), .A1N(P_Sgf[53]), .B0(n6171), .Y(n354) );
INVX2TS U7657 ( .A(n6173), .Y(n6175) );
NAND2X1TS U7658 ( .A(n6175), .B(n6174), .Y(n6176) );
XNOR2X1TS U7659 ( .A(n6177), .B(n6176), .Y(n6178) );
MX2X1TS U7660 ( .A(P_Sgf[52]), .B(n6178), .S0(n6339), .Y(n473) );
AOI22X1TS U7661 ( .A0(n6180), .A1(Add_result[1]), .B0(
Sgf_normalized_result[0]), .B1(n6179), .Y(n6181) );
OAI2BB1X1TS U7662 ( .A0N(n6182), .A1N(P_Sgf[53]), .B0(n6181), .Y(n6183) );
AOI21X1TS U7663 ( .A0(n6184), .A1(Add_result[0]), .B0(n6183), .Y(n6185) );
OAI2BB1X1TS U7664 ( .A0N(P_Sgf[52]), .A1N(n5991), .B0(n6185), .Y(n353) );
ADDHXLTS U7665 ( .A(Sgf_normalized_result[52]), .B(n6186), .CO(n6188), .S(
n5627) );
MX2X1TS U7666 ( .A(P_Sgf[0]), .B(Sgf_operation_Result[0]), .S0(n6339), .Y(
n421) );
MX2X1TS U7667 ( .A(P_Sgf[1]), .B(Sgf_operation_Result[1]), .S0(n6339), .Y(
n422) );
MX2X1TS U7668 ( .A(P_Sgf[2]), .B(Sgf_operation_Result[2]), .S0(n6339), .Y(
n423) );
MX2X1TS U7669 ( .A(P_Sgf[4]), .B(Sgf_operation_Result[4]), .S0(n6339), .Y(
n425) );
MX2X1TS U7670 ( .A(P_Sgf[5]), .B(Sgf_operation_Result[5]), .S0(n6339), .Y(
n426) );
MX2X1TS U7671 ( .A(P_Sgf[6]), .B(Sgf_operation_Result[6]), .S0(n6339), .Y(
n427) );
MX2X1TS U7672 ( .A(P_Sgf[7]), .B(Sgf_operation_Result[7]), .S0(n6339), .Y(
n428) );
NAND2X1TS U7673 ( .A(n834), .B(n6191), .Y(n6192) );
XNOR2X1TS U7674 ( .A(n6193), .B(n6192), .Y(n6194) );
MX2X1TS U7675 ( .A(P_Sgf[48]), .B(n6194), .S0(n6339), .Y(n469) );
INVX2TS U7676 ( .A(n6197), .Y(n6199) );
NAND2X1TS U7677 ( .A(n6199), .B(n6198), .Y(n6200) );
XNOR2X1TS U7678 ( .A(n6201), .B(n6200), .Y(n6203) );
BUFX4TS U7679 ( .A(n6202), .Y(n6267) );
MX2X1TS U7680 ( .A(P_Sgf[49]), .B(n6203), .S0(n6267), .Y(n470) );
NAND2X1TS U7681 ( .A(n875), .B(n6204), .Y(n6205) );
XNOR2X1TS U7682 ( .A(n6206), .B(n6205), .Y(n6207) );
MX2X1TS U7683 ( .A(P_Sgf[50]), .B(n6207), .S0(n6267), .Y(n471) );
INVX2TS U7684 ( .A(n6208), .Y(n6210) );
NAND2X1TS U7685 ( .A(n6210), .B(n6209), .Y(n6211) );
XNOR2X1TS U7686 ( .A(n6212), .B(n6211), .Y(n6213) );
MX2X1TS U7687 ( .A(P_Sgf[51]), .B(n6213), .S0(n6267), .Y(n472) );
INVX2TS U7688 ( .A(n6214), .Y(n6259) );
AOI21X1TS U7689 ( .A0(n6259), .A1(n826), .B0(n6215), .Y(n6222) );
INVX2TS U7690 ( .A(n6216), .Y(n6218) );
NAND2X1TS U7691 ( .A(n6218), .B(n6217), .Y(n6219) );
XNOR2X1TS U7692 ( .A(n6220), .B(n6219), .Y(n6221) );
MX2X1TS U7693 ( .A(P_Sgf[44]), .B(n6221), .S0(n6267), .Y(n465) );
INVX2TS U7694 ( .A(n6222), .Y(n6265) );
AOI21X1TS U7695 ( .A0(n6265), .A1(n6224), .B0(n6223), .Y(n6227) );
NAND2X1TS U7696 ( .A(n810), .B(n6225), .Y(n6226) );
XOR2X1TS U7697 ( .A(n6227), .B(n6226), .Y(n6228) );
MX2X1TS U7698 ( .A(P_Sgf[45]), .B(n6228), .S0(n6267), .Y(n466) );
INVX2TS U7699 ( .A(n6229), .Y(n6232) );
INVX2TS U7700 ( .A(n6230), .Y(n6231) );
AOI21X1TS U7701 ( .A0(n6265), .A1(n6232), .B0(n6231), .Y(n6237) );
INVX2TS U7702 ( .A(n6233), .Y(n6235) );
NAND2X1TS U7703 ( .A(n6235), .B(n6234), .Y(n6236) );
XOR2X1TS U7704 ( .A(n6237), .B(n6236), .Y(n6238) );
MX2X1TS U7705 ( .A(P_Sgf[46]), .B(n6238), .S0(n6267), .Y(n467) );
NAND2X1TS U7706 ( .A(n6240), .B(n6239), .Y(n6241) );
XOR2XLTS U7707 ( .A(n6242), .B(n6241), .Y(n6243) );
MX2X1TS U7708 ( .A(P_Sgf[47]), .B(n6243), .S0(n6267), .Y(n468) );
INVX2TS U7709 ( .A(n6244), .Y(n6250) );
INVX2TS U7710 ( .A(n6249), .Y(n6245) );
XOR2XLTS U7711 ( .A(n6250), .B(n6246), .Y(n6247) );
MX2X1TS U7712 ( .A(P_Sgf[40]), .B(n6247), .S0(n6267), .Y(n461) );
INVX2TS U7713 ( .A(n6251), .Y(n6253) );
NAND2X1TS U7714 ( .A(n6253), .B(n6252), .Y(n6254) );
XNOR2X1TS U7715 ( .A(n6255), .B(n6254), .Y(n6256) );
MX2X1TS U7716 ( .A(P_Sgf[41]), .B(n6256), .S0(n6267), .Y(n462) );
NAND2X1TS U7717 ( .A(n826), .B(n6257), .Y(n6258) );
XNOR2X1TS U7718 ( .A(n6259), .B(n6258), .Y(n6260) );
MX2X1TS U7719 ( .A(P_Sgf[42]), .B(n6260), .S0(n6267), .Y(n463) );
NAND2X1TS U7720 ( .A(n6263), .B(n6262), .Y(n6264) );
XNOR2X1TS U7721 ( .A(n6265), .B(n6264), .Y(n6266) );
MX2X1TS U7722 ( .A(P_Sgf[43]), .B(n6266), .S0(n6267), .Y(n464) );
MX2X1TS U7723 ( .A(P_Sgf[8]), .B(Sgf_operation_Result[8]), .S0(n6267), .Y(
n429) );
MX2X1TS U7724 ( .A(P_Sgf[9]), .B(Sgf_operation_Result[9]), .S0(n6267), .Y(
n430) );
MX2X1TS U7725 ( .A(P_Sgf[10]), .B(Sgf_operation_Result[10]), .S0(n6267), .Y(
n431) );
MX2X1TS U7726 ( .A(P_Sgf[11]), .B(Sgf_operation_Result[11]), .S0(n6267), .Y(
n432) );
BUFX4TS U7727 ( .A(n6202), .Y(n6268) );
MX2X1TS U7728 ( .A(P_Sgf[12]), .B(Sgf_operation_Result[12]), .S0(n6268), .Y(
n433) );
MX2X1TS U7729 ( .A(P_Sgf[13]), .B(Sgf_operation_Result[13]), .S0(n6268), .Y(
n434) );
MX2X1TS U7730 ( .A(P_Sgf[14]), .B(Sgf_operation_Result[14]), .S0(n6268), .Y(
n435) );
MX2X1TS U7731 ( .A(P_Sgf[15]), .B(Sgf_operation_Result[15]), .S0(n6268), .Y(
n436) );
MX2X1TS U7732 ( .A(P_Sgf[16]), .B(Sgf_operation_Result[16]), .S0(n6268), .Y(
n437) );
MX2X1TS U7733 ( .A(P_Sgf[17]), .B(Sgf_operation_Result[17]), .S0(n6268), .Y(
n438) );
MX2X1TS U7734 ( .A(P_Sgf[18]), .B(Sgf_operation_Result[18]), .S0(n6268), .Y(
n439) );
MX2X1TS U7735 ( .A(P_Sgf[19]), .B(Sgf_operation_Result[19]), .S0(n6268), .Y(
n440) );
MX2X1TS U7736 ( .A(P_Sgf[20]), .B(Sgf_operation_Result[20]), .S0(n6268), .Y(
n441) );
MX2X1TS U7737 ( .A(P_Sgf[21]), .B(Sgf_operation_Result[21]), .S0(n6268), .Y(
n442) );
MX2X1TS U7738 ( .A(P_Sgf[22]), .B(Sgf_operation_Result[22]), .S0(n6268), .Y(
n443) );
MX2X1TS U7739 ( .A(P_Sgf[23]), .B(Sgf_operation_Result[23]), .S0(n6268), .Y(
n444) );
MX2X1TS U7740 ( .A(P_Sgf[24]), .B(Sgf_operation_Result[24]), .S0(n6268), .Y(
n445) );
MX2X1TS U7741 ( .A(P_Sgf[25]), .B(Sgf_operation_Result[25]), .S0(n6268), .Y(
n446) );
MX2X1TS U7742 ( .A(P_Sgf[26]), .B(Sgf_operation_Result[26]), .S0(n6268), .Y(
n447) );
MX2X1TS U7743 ( .A(P_Sgf[27]), .B(n871), .S0(n6336), .Y(n448) );
NAND2X1TS U7744 ( .A(n6272), .B(n6271), .Y(n6274) );
XOR2XLTS U7745 ( .A(n6274), .B(n6273), .Y(n6275) );
MX2X1TS U7746 ( .A(P_Sgf[28]), .B(n6275), .S0(n6336), .Y(n449) );
NAND2X1TS U7747 ( .A(n880), .B(n6276), .Y(n6278) );
XNOR2X1TS U7748 ( .A(n6278), .B(n6277), .Y(n6279) );
MX2X1TS U7749 ( .A(P_Sgf[29]), .B(n6279), .S0(n6336), .Y(n450) );
NAND2X1TS U7750 ( .A(n877), .B(n6280), .Y(n6281) );
XNOR2X1TS U7751 ( .A(n6281), .B(n759), .Y(n6282) );
MX2X1TS U7752 ( .A(P_Sgf[30]), .B(n6282), .S0(n6336), .Y(n451) );
INVX2TS U7753 ( .A(n6283), .Y(n6285) );
NAND2X1TS U7754 ( .A(n6285), .B(n6284), .Y(n6286) );
XOR2XLTS U7755 ( .A(n6287), .B(n6286), .Y(n6288) );
MX2X1TS U7756 ( .A(P_Sgf[31]), .B(n6288), .S0(n6336), .Y(n452) );
NAND2X1TS U7757 ( .A(n874), .B(n6289), .Y(n6290) );
XNOR2X1TS U7758 ( .A(n6291), .B(n6290), .Y(n6292) );
MX2X1TS U7759 ( .A(P_Sgf[32]), .B(n6292), .S0(n6336), .Y(n453) );
INVX2TS U7760 ( .A(n6293), .Y(n6295) );
NAND2X1TS U7761 ( .A(n6295), .B(n6294), .Y(n6296) );
XOR2XLTS U7762 ( .A(n6297), .B(n6296), .Y(n6298) );
MX2X1TS U7763 ( .A(P_Sgf[33]), .B(n6298), .S0(n6336), .Y(n454) );
INVX2TS U7764 ( .A(n6299), .Y(n6305) );
INVX2TS U7765 ( .A(n6304), .Y(n6300) );
NAND2X1TS U7766 ( .A(n6300), .B(n6303), .Y(n6301) );
XOR2XLTS U7767 ( .A(n6305), .B(n6301), .Y(n6302) );
MX2X1TS U7768 ( .A(P_Sgf[34]), .B(n6302), .S0(n6336), .Y(n455) );
OAI21X1TS U7769 ( .A0(n6305), .A1(n6304), .B0(n6303), .Y(n6310) );
NAND2X1TS U7770 ( .A(n828), .B(n6306), .Y(n6307) );
XNOR2X1TS U7771 ( .A(n6310), .B(n6307), .Y(n6308) );
MX2X1TS U7772 ( .A(P_Sgf[35]), .B(n6308), .S0(n6336), .Y(n456) );
AOI21X1TS U7773 ( .A0(n6310), .A1(n828), .B0(n6309), .Y(n6313) );
NAND2X1TS U7774 ( .A(n827), .B(n6311), .Y(n6312) );
MX2X1TS U7775 ( .A(P_Sgf[36]), .B(n6314), .S0(n6336), .Y(n457) );
INVX2TS U7776 ( .A(n6315), .Y(n6329) );
INVX2TS U7777 ( .A(n6316), .Y(n6321) );
NAND2X1TS U7778 ( .A(n6321), .B(n6319), .Y(n6317) );
XNOR2X1TS U7779 ( .A(n6329), .B(n6317), .Y(n6318) );
MX2X1TS U7780 ( .A(P_Sgf[37]), .B(n6318), .S0(n6336), .Y(n458) );
AOI21X1TS U7781 ( .A0(n6329), .A1(n6321), .B0(n6320), .Y(n6326) );
INVX2TS U7782 ( .A(n6322), .Y(n6324) );
NAND2X1TS U7783 ( .A(n6324), .B(n6323), .Y(n6325) );
XOR2XLTS U7784 ( .A(n6326), .B(n6325), .Y(n6327) );
MX2X1TS U7785 ( .A(P_Sgf[38]), .B(n6327), .S0(n6336), .Y(n459) );
AOI21X1TS U7786 ( .A0(n6330), .A1(n6329), .B0(n6328), .Y(n6333) );
NAND2X1TS U7787 ( .A(n835), .B(n6331), .Y(n6332) );
XOR2XLTS U7788 ( .A(n6333), .B(n6332), .Y(n6334) );
MX2X1TS U7789 ( .A(P_Sgf[39]), .B(n6334), .S0(n6336), .Y(n460) );
INVX4TS U7790 ( .A(n5613), .Y(n6335) );
MX2X1TS U7791 ( .A(Data_MY[52]), .B(Op_MY[52]), .S0(n6335), .Y(n634) );
MX2X1TS U7792 ( .A(Data_MY[62]), .B(Op_MY[62]), .S0(n6335), .Y(n644) );
MX2X1TS U7793 ( .A(Data_MY[61]), .B(Op_MY[61]), .S0(n6335), .Y(n643) );
MX2X1TS U7794 ( .A(Data_MY[60]), .B(Op_MY[60]), .S0(n6335), .Y(n642) );
MX2X1TS U7795 ( .A(Data_MY[59]), .B(Op_MY[59]), .S0(n6335), .Y(n641) );
MX2X1TS U7796 ( .A(Data_MY[58]), .B(Op_MY[58]), .S0(n6335), .Y(n640) );
MX2X1TS U7797 ( .A(Data_MY[57]), .B(Op_MY[57]), .S0(n6335), .Y(n639) );
MX2X1TS U7798 ( .A(Data_MY[56]), .B(Op_MY[56]), .S0(n6335), .Y(n638) );
MX2X1TS U7799 ( .A(Data_MY[55]), .B(Op_MY[55]), .S0(n6335), .Y(n637) );
MX2X1TS U7800 ( .A(Data_MY[54]), .B(Op_MY[54]), .S0(n6335), .Y(n636) );
MX2X1TS U7801 ( .A(Data_MY[53]), .B(Op_MY[53]), .S0(n6335), .Y(n635) );
MX2X1TS U7802 ( .A(Data_MX[62]), .B(Op_MX[62]), .S0(n6335), .Y(n708) );
MX2X1TS U7803 ( .A(Data_MX[61]), .B(Op_MX[61]), .S0(n6335), .Y(n707) );
MX2X1TS U7804 ( .A(Data_MX[60]), .B(Op_MX[60]), .S0(n5614), .Y(n706) );
MX2X1TS U7805 ( .A(Data_MX[59]), .B(Op_MX[59]), .S0(n6335), .Y(n705) );
MX2X1TS U7806 ( .A(Data_MX[58]), .B(Op_MX[58]), .S0(n5617), .Y(n704) );
MX2X1TS U7807 ( .A(Data_MX[57]), .B(Op_MX[57]), .S0(n5612), .Y(n703) );
MX2X1TS U7808 ( .A(Data_MX[56]), .B(Op_MX[56]), .S0(n5619), .Y(n702) );
MX2X1TS U7809 ( .A(Data_MX[55]), .B(Op_MX[55]), .S0(n5620), .Y(n701) );
MX2X1TS U7810 ( .A(Data_MX[54]), .B(Op_MX[54]), .S0(n5616), .Y(n700) );
MX2X1TS U7811 ( .A(Data_MX[53]), .B(Op_MX[53]), .S0(n5615), .Y(n699) );
MX2X1TS U7812 ( .A(Data_MX[52]), .B(Op_MX[52]), .S0(n5618), .Y(n698) );
NAND2X1TS U7813 ( .A(n6389), .B(n6574), .Y(n710) );
NOR2BX1TS U7814 ( .AN(exp_oper_result[11]), .B(n6574), .Y(S_Oper_A_exp[11])
);
MX2X1TS U7815 ( .A(Op_MX[62]), .B(exp_oper_result[10]), .S0(FSM_selector_A),
.Y(S_Oper_A_exp[10]) );
MX2X1TS U7816 ( .A(Op_MX[61]), .B(exp_oper_result[9]), .S0(FSM_selector_A),
.Y(S_Oper_A_exp[9]) );
MX2X1TS U7817 ( .A(Op_MX[60]), .B(exp_oper_result[8]), .S0(FSM_selector_A),
.Y(S_Oper_A_exp[8]) );
MX2X1TS U7818 ( .A(Op_MX[59]), .B(exp_oper_result[7]), .S0(FSM_selector_A),
.Y(S_Oper_A_exp[7]) );
MX2X1TS U7819 ( .A(Exp_module_Data_S[6]), .B(exp_oper_result[6]), .S0(n6338),
.Y(n411) );
MX2X1TS U7820 ( .A(Op_MX[58]), .B(exp_oper_result[6]), .S0(FSM_selector_A),
.Y(S_Oper_A_exp[6]) );
MX2X1TS U7821 ( .A(Exp_module_Data_S[5]), .B(exp_oper_result[5]), .S0(n6338),
.Y(n412) );
MX2X1TS U7822 ( .A(Op_MX[57]), .B(exp_oper_result[5]), .S0(FSM_selector_A),
.Y(S_Oper_A_exp[5]) );
MX2X1TS U7823 ( .A(Exp_module_Data_S[4]), .B(exp_oper_result[4]), .S0(n6338),
.Y(n413) );
MX2X1TS U7824 ( .A(Op_MX[56]), .B(exp_oper_result[4]), .S0(FSM_selector_A),
.Y(S_Oper_A_exp[4]) );
MX2X1TS U7825 ( .A(Exp_module_Data_S[3]), .B(exp_oper_result[3]), .S0(n6338),
.Y(n414) );
MX2X1TS U7826 ( .A(Exp_module_Data_S[2]), .B(exp_oper_result[2]), .S0(n6338),
.Y(n415) );
MX2X1TS U7827 ( .A(Exp_module_Data_S[1]), .B(exp_oper_result[1]), .S0(n6338),
.Y(n416) );
MX2X1TS U7828 ( .A(Exp_module_Data_S[0]), .B(exp_oper_result[0]), .S0(n6338),
.Y(n417) );
XNOR2X1TS U7829 ( .A(DP_OP_36J43_124_1029_n1), .B(n765), .Y(n6340) );
NAND4XLTS U7830 ( .A(Exp_module_Data_S[3]), .B(Exp_module_Data_S[2]), .C(
Exp_module_Data_S[1]), .D(Exp_module_Data_S[0]), .Y(n6341) );
NAND4BXLTS U7831 ( .AN(n6341), .B(Exp_module_Data_S[6]), .C(
Exp_module_Data_S[5]), .D(Exp_module_Data_S[4]), .Y(n6342) );
OAI22X1TS U7832 ( .A0(Exp_module_Data_S[11]), .A1(n6344), .B0(n6392), .B1(
n6581), .Y(n352) );
INVX4TS U7833 ( .A(n6404), .Y(n6402) );
AO22XLTS U7834 ( .A0(n6402), .A1(Sgf_normalized_result[2]), .B0(
final_result_ieee[2]), .B1(n6401), .Y(n349) );
AO22XLTS U7835 ( .A0(n6402), .A1(n773), .B0(final_result_ieee[3]), .B1(n6401), .Y(n348) );
AO22XLTS U7836 ( .A0(n5613), .A1(Data_MY[63]), .B0(n5618), .B1(Op_MY[63]),
.Y(n715) );
AOI21X1TS U7837 ( .A0(FS_Module_state_reg[2]), .A1(n6345), .B0(n6582), .Y(
n6348) );
NAND3XLTS U7838 ( .A(n6348), .B(n6347), .C(n6346), .Y(n711) );
NOR4X1TS U7839 ( .A(n770), .B(n780), .C(n800), .D(n777), .Y(n6349) );
NAND4XLTS U7840 ( .A(n6352), .B(n6351), .C(n6350), .D(n6349), .Y(n6368) );
NAND4XLTS U7841 ( .A(n6356), .B(n6355), .C(n6354), .D(n6353), .Y(n6367) );
NAND4XLTS U7842 ( .A(n6360), .B(n6359), .C(n6358), .D(n6357), .Y(n6366) );
NOR4X1TS U7843 ( .A(Op_MY[57]), .B(Op_MY[56]), .C(Op_MY[55]), .D(Op_MY[54]),
.Y(n6364) );
NOR4X1TS U7844 ( .A(Op_MY[61]), .B(Op_MY[60]), .C(Op_MY[59]), .D(Op_MY[58]),
.Y(n6363) );
NOR4X1TS U7845 ( .A(Op_MY[26]), .B(n798), .C(Op_MY[2]), .D(Op_MY[62]), .Y(
n6362) );
NAND4XLTS U7846 ( .A(n6364), .B(n6363), .C(n6362), .D(n6361), .Y(n6365) );
OR4X2TS U7847 ( .A(n6368), .B(n6367), .C(n6366), .D(n6365), .Y(n6393) );
NAND4XLTS U7848 ( .A(n6372), .B(n6371), .C(n6370), .D(n6369), .Y(n6388) );
NAND4XLTS U7849 ( .A(n6376), .B(n6375), .C(n6374), .D(n6373), .Y(n6387) );
NAND4XLTS U7850 ( .A(n6380), .B(n6379), .C(n6378), .D(n6377), .Y(n6386) );
NOR4X1TS U7851 ( .A(Op_MX[57]), .B(Op_MX[56]), .C(Op_MX[55]), .D(Op_MX[54]),
.Y(n6384) );
NAND4XLTS U7852 ( .A(n6384), .B(n6383), .C(n6382), .D(n6381), .Y(n6385) );
OR4X2TS U7853 ( .A(n6388), .B(n6387), .C(n6386), .D(n6385), .Y(n6391) );
AOI32X1TS U7854 ( .A0(n6393), .A1(n6392), .A2(n6391), .B0(n6390), .B1(n6389),
.Y(n581) );
AO22XLTS U7855 ( .A0(n1634), .A1(Sgf_normalized_result[0]), .B0(n6394), .B1(
Add_result[0]), .Y(n579) );
AO22XLTS U7856 ( .A0(n1634), .A1(Sgf_normalized_result[1]), .B0(n6394), .B1(
Add_result[1]), .Y(n578) );
INVX2TS U7857 ( .A(n6404), .Y(n6395) );
INVX4TS U7858 ( .A(n6405), .Y(n6400) );
AO22XLTS U7859 ( .A0(Sgf_normalized_result[0]), .A1(n6395), .B0(
final_result_ieee[0]), .B1(n6400), .Y(n351) );
INVX2TS U7860 ( .A(n6403), .Y(n6396) );
AO22XLTS U7861 ( .A0(Sgf_normalized_result[1]), .A1(n6395), .B0(
final_result_ieee[1]), .B1(n6396), .Y(n350) );
AO22XLTS U7862 ( .A0(Sgf_normalized_result[4]), .A1(n6395), .B0(
final_result_ieee[4]), .B1(n6396), .Y(n347) );
AO22XLTS U7863 ( .A0(Sgf_normalized_result[5]), .A1(n6395), .B0(
final_result_ieee[5]), .B1(n6396), .Y(n346) );
AO22XLTS U7864 ( .A0(Sgf_normalized_result[6]), .A1(n6395), .B0(
final_result_ieee[6]), .B1(n6396), .Y(n345) );
AO22XLTS U7865 ( .A0(Sgf_normalized_result[7]), .A1(n6395), .B0(
final_result_ieee[7]), .B1(n6396), .Y(n344) );
AO22XLTS U7866 ( .A0(Sgf_normalized_result[8]), .A1(n6395), .B0(
final_result_ieee[8]), .B1(n6396), .Y(n343) );
INVX4TS U7867 ( .A(n6404), .Y(n6397) );
AO22XLTS U7868 ( .A0(Sgf_normalized_result[9]), .A1(n6397), .B0(
final_result_ieee[9]), .B1(n6396), .Y(n342) );
AO22XLTS U7869 ( .A0(Sgf_normalized_result[10]), .A1(n6397), .B0(
final_result_ieee[10]), .B1(n6396), .Y(n341) );
AO22XLTS U7870 ( .A0(Sgf_normalized_result[11]), .A1(n6397), .B0(
final_result_ieee[11]), .B1(n6396), .Y(n340) );
INVX4TS U7871 ( .A(n6403), .Y(n6398) );
AO22XLTS U7872 ( .A0(Sgf_normalized_result[12]), .A1(n6397), .B0(
final_result_ieee[12]), .B1(n6398), .Y(n339) );
AO22XLTS U7873 ( .A0(Sgf_normalized_result[13]), .A1(n6397), .B0(
final_result_ieee[13]), .B1(n6398), .Y(n338) );
AO22XLTS U7874 ( .A0(Sgf_normalized_result[14]), .A1(n6397), .B0(
final_result_ieee[14]), .B1(n6398), .Y(n337) );
AO22XLTS U7875 ( .A0(Sgf_normalized_result[15]), .A1(n6397), .B0(
final_result_ieee[15]), .B1(n6398), .Y(n336) );
AO22XLTS U7876 ( .A0(Sgf_normalized_result[16]), .A1(n6397), .B0(
final_result_ieee[16]), .B1(n6398), .Y(n335) );
AO22XLTS U7877 ( .A0(Sgf_normalized_result[17]), .A1(n6397), .B0(
final_result_ieee[17]), .B1(n6398), .Y(n334) );
AO22XLTS U7878 ( .A0(Sgf_normalized_result[18]), .A1(n6397), .B0(
final_result_ieee[18]), .B1(n6398), .Y(n333) );
AO22XLTS U7879 ( .A0(Sgf_normalized_result[19]), .A1(n6397), .B0(
final_result_ieee[19]), .B1(n6398), .Y(n332) );
AO22XLTS U7880 ( .A0(Sgf_normalized_result[20]), .A1(n6397), .B0(
final_result_ieee[20]), .B1(n6398), .Y(n331) );
AO22XLTS U7881 ( .A0(Sgf_normalized_result[21]), .A1(n6397), .B0(
final_result_ieee[21]), .B1(n6398), .Y(n330) );
AO22XLTS U7882 ( .A0(Sgf_normalized_result[22]), .A1(n6397), .B0(
final_result_ieee[22]), .B1(n6398), .Y(n329) );
AO22XLTS U7883 ( .A0(Sgf_normalized_result[23]), .A1(n6397), .B0(
final_result_ieee[23]), .B1(n6398), .Y(n328) );
INVX4TS U7884 ( .A(n6404), .Y(n6399) );
AO22XLTS U7885 ( .A0(Sgf_normalized_result[24]), .A1(n6399), .B0(
final_result_ieee[24]), .B1(n6398), .Y(n327) );
AO22XLTS U7886 ( .A0(Sgf_normalized_result[25]), .A1(n6399), .B0(
final_result_ieee[25]), .B1(n6398), .Y(n326) );
AO22XLTS U7887 ( .A0(Sgf_normalized_result[26]), .A1(n6399), .B0(
final_result_ieee[26]), .B1(n6398), .Y(n325) );
AO22XLTS U7888 ( .A0(Sgf_normalized_result[27]), .A1(n6399), .B0(
final_result_ieee[27]), .B1(n6400), .Y(n324) );
AO22XLTS U7889 ( .A0(Sgf_normalized_result[28]), .A1(n6399), .B0(
final_result_ieee[28]), .B1(n6400), .Y(n323) );
AO22XLTS U7890 ( .A0(Sgf_normalized_result[29]), .A1(n6399), .B0(
final_result_ieee[29]), .B1(n6400), .Y(n322) );
AO22XLTS U7891 ( .A0(Sgf_normalized_result[30]), .A1(n6399), .B0(
final_result_ieee[30]), .B1(n6400), .Y(n321) );
AO22XLTS U7892 ( .A0(Sgf_normalized_result[31]), .A1(n6399), .B0(
final_result_ieee[31]), .B1(n6400), .Y(n320) );
AO22XLTS U7893 ( .A0(Sgf_normalized_result[32]), .A1(n6399), .B0(
final_result_ieee[32]), .B1(n6400), .Y(n319) );
AO22XLTS U7894 ( .A0(Sgf_normalized_result[33]), .A1(n6399), .B0(
final_result_ieee[33]), .B1(n6400), .Y(n318) );
AO22XLTS U7895 ( .A0(Sgf_normalized_result[34]), .A1(n6399), .B0(
final_result_ieee[34]), .B1(n6400), .Y(n317) );
AO22XLTS U7896 ( .A0(Sgf_normalized_result[35]), .A1(n6399), .B0(
final_result_ieee[35]), .B1(n6400), .Y(n316) );
AO22XLTS U7897 ( .A0(Sgf_normalized_result[36]), .A1(n6399), .B0(
final_result_ieee[36]), .B1(n6400), .Y(n315) );
AO22XLTS U7898 ( .A0(Sgf_normalized_result[37]), .A1(n6399), .B0(
final_result_ieee[37]), .B1(n6400), .Y(n314) );
AO22XLTS U7899 ( .A0(Sgf_normalized_result[38]), .A1(n6399), .B0(
final_result_ieee[38]), .B1(n6400), .Y(n313) );
AO22XLTS U7900 ( .A0(Sgf_normalized_result[39]), .A1(n6402), .B0(
final_result_ieee[39]), .B1(n6400), .Y(n312) );
AO22XLTS U7901 ( .A0(Sgf_normalized_result[40]), .A1(n6402), .B0(
final_result_ieee[40]), .B1(n6400), .Y(n311) );
AO22XLTS U7902 ( .A0(Sgf_normalized_result[41]), .A1(n6402), .B0(
final_result_ieee[41]), .B1(n6401), .Y(n310) );
AO22XLTS U7903 ( .A0(Sgf_normalized_result[42]), .A1(n6402), .B0(
final_result_ieee[42]), .B1(n6401), .Y(n309) );
AO22XLTS U7904 ( .A0(Sgf_normalized_result[43]), .A1(n6402), .B0(
final_result_ieee[43]), .B1(n6401), .Y(n308) );
AO22XLTS U7905 ( .A0(Sgf_normalized_result[44]), .A1(n6402), .B0(
final_result_ieee[44]), .B1(n6401), .Y(n307) );
AO22XLTS U7906 ( .A0(Sgf_normalized_result[45]), .A1(n6402), .B0(
final_result_ieee[45]), .B1(n6401), .Y(n306) );
AO22XLTS U7907 ( .A0(Sgf_normalized_result[46]), .A1(n6402), .B0(
final_result_ieee[46]), .B1(n6401), .Y(n305) );
AO22XLTS U7908 ( .A0(Sgf_normalized_result[47]), .A1(n6402), .B0(
final_result_ieee[47]), .B1(n6401), .Y(n304) );
AO22XLTS U7909 ( .A0(Sgf_normalized_result[48]), .A1(n6402), .B0(
final_result_ieee[48]), .B1(n6401), .Y(n303) );
AO22XLTS U7910 ( .A0(Sgf_normalized_result[49]), .A1(n6402), .B0(
final_result_ieee[49]), .B1(n6401), .Y(n302) );
AO22XLTS U7911 ( .A0(Sgf_normalized_result[50]), .A1(n6402), .B0(
final_result_ieee[50]), .B1(n6401), .Y(n301) );
AO22XLTS U7912 ( .A0(Sgf_normalized_result[51]), .A1(n6402), .B0(
final_result_ieee[51]), .B1(n6401), .Y(n300) );
OA22X1TS U7913 ( .A0(n6403), .A1(final_result_ieee[52]), .B0(
exp_oper_result[0]), .B1(n6404), .Y(n299) );
OA22X1TS U7914 ( .A0(n6405), .A1(final_result_ieee[56]), .B0(
exp_oper_result[4]), .B1(n6404), .Y(n295) );
OA22X1TS U7915 ( .A0(n6405), .A1(final_result_ieee[57]), .B0(
exp_oper_result[5]), .B1(n6404), .Y(n294) );
OA22X1TS U7916 ( .A0(n6405), .A1(final_result_ieee[58]), .B0(
exp_oper_result[6]), .B1(n6404), .Y(n293) );
OA22X1TS U7917 ( .A0(n6405), .A1(final_result_ieee[59]), .B0(
exp_oper_result[7]), .B1(n6404), .Y(n292) );
OA22X1TS U7918 ( .A0(n6405), .A1(final_result_ieee[60]), .B0(
exp_oper_result[8]), .B1(n6404), .Y(n291) );
OA22X1TS U7919 ( .A0(n6405), .A1(final_result_ieee[61]), .B0(
exp_oper_result[9]), .B1(n6404), .Y(n290) );
CMPR42X1TS U7920 ( .A(mult_x_23_n1227), .B(mult_x_23_n1175), .C(
mult_x_23_n578), .D(mult_x_23_n571), .ICI(mult_x_23_n574), .S(
mult_x_23_n568), .ICO(mult_x_23_n566), .CO(mult_x_23_n567) );
CMPR42X1TS U7921 ( .A(mult_x_23_n1291), .B(mult_x_23_n697), .C(
mult_x_23_n704), .D(mult_x_23_n694), .ICI(mult_x_23_n700), .S(
mult_x_23_n691), .ICO(mult_x_23_n689), .CO(mult_x_23_n690) );
CMPR42X1TS U7922 ( .A(mult_x_23_n569), .B(mult_x_23_n1200), .C(
mult_x_23_n564), .D(mult_x_23_n570), .ICI(mult_x_23_n566), .S(
mult_x_23_n561), .ICO(mult_x_23_n559), .CO(mult_x_23_n560) );
CMPR42X1TS U7923 ( .A(mult_x_23_n621), .B(mult_x_23_n630), .C(mult_x_23_n627), .D(mult_x_23_n618), .ICI(mult_x_23_n623), .S(mult_x_23_n615), .ICO(
mult_x_23_n613), .CO(mult_x_23_n614) );
CMPR42X1TS U7924 ( .A(mult_x_23_n652), .B(mult_x_23_n642), .C(mult_x_23_n649), .D(mult_x_23_n639), .ICI(mult_x_23_n645), .S(mult_x_23_n636), .ICO(
mult_x_23_n634), .CO(mult_x_23_n635) );
CMPR42X1TS U7925 ( .A(DP_OP_169J43_123_4229_n898), .B(
DP_OP_169J43_123_4229_n882), .C(DP_OP_169J43_123_4229_n895), .D(
DP_OP_169J43_123_4229_n879), .ICI(DP_OP_169J43_123_4229_n891), .S(
DP_OP_169J43_123_4229_n876), .ICO(DP_OP_169J43_123_4229_n874), .CO(
DP_OP_169J43_123_4229_n875) );
CMPR42X1TS U7926 ( .A(DP_OP_169J43_123_4229_n776), .B(
DP_OP_169J43_123_4229_n786), .C(DP_OP_169J43_123_4229_n783), .D(
DP_OP_169J43_123_4229_n773), .ICI(DP_OP_169J43_123_4229_n779), .S(
DP_OP_169J43_123_4229_n770), .ICO(DP_OP_169J43_123_4229_n768), .CO(
DP_OP_169J43_123_4229_n769) );
CMPR42X1TS U7927 ( .A(DP_OP_169J43_123_4229_n1426), .B(
DP_OP_169J43_123_4229_n1538), .C(DP_OP_169J43_123_4229_n1510), .D(
DP_OP_169J43_123_4229_n1482), .ICI(DP_OP_169J43_123_4229_n1037), .S(
DP_OP_169J43_123_4229_n1021), .ICO(DP_OP_169J43_123_4229_n1019), .CO(
DP_OP_169J43_123_4229_n1020) );
CMPR42X1TS U7928 ( .A(mult_x_23_n622), .B(mult_x_23_n632), .C(
mult_x_23_n1180), .D(mult_x_23_n1284), .ICI(mult_x_23_n1232), .S(
mult_x_23_n621), .ICO(mult_x_23_n619), .CO(mult_x_23_n620) );
CMPR42X1TS U7929 ( .A(mult_x_23_n565), .B(mult_x_23_n1226), .C(
mult_x_23_n1174), .D(mult_x_23_n572), .ICI(mult_x_23_n1148), .S(
mult_x_23_n564), .ICO(mult_x_23_n562), .CO(mult_x_23_n563) );
CMPR42X1TS U7930 ( .A(DP_OP_169J43_123_4229_n1470), .B(
DP_OP_169J43_123_4229_n1442), .C(DP_OP_169J43_123_4229_n821), .D(
DP_OP_169J43_123_4229_n825), .ICI(DP_OP_169J43_123_4229_n822), .S(
DP_OP_169J43_123_4229_n808), .ICO(DP_OP_169J43_123_4229_n806), .CO(
DP_OP_169J43_123_4229_n807) );
CMPR42X1TS U7931 ( .A(DP_OP_169J43_123_4229_n1421), .B(
DP_OP_169J43_123_4229_n1393), .C(DP_OP_169J43_123_4229_n1645), .D(
DP_OP_169J43_123_4229_n1477), .ICI(DP_OP_169J43_123_4229_n936), .S(
DP_OP_169J43_123_4229_n922), .ICO(DP_OP_169J43_123_4229_n920), .CO(
DP_OP_169J43_123_4229_n921) );
CMPR42X1TS U7932 ( .A(DP_OP_169J43_123_4229_n1396), .B(
DP_OP_169J43_123_4229_n1508), .C(DP_OP_169J43_123_4229_n1480), .D(
DP_OP_169J43_123_4229_n1452), .ICI(DP_OP_169J43_123_4229_n991), .S(
DP_OP_169J43_123_4229_n979), .ICO(DP_OP_169J43_123_4229_n977), .CO(
DP_OP_169J43_123_4229_n978) );
CMPR42X1TS U7933 ( .A(mult_x_23_n1236), .B(mult_x_23_n1158), .C(
mult_x_23_n1288), .D(mult_x_23_n676), .ICI(mult_x_23_n673), .S(
mult_x_23_n664), .ICO(mult_x_23_n662), .CO(mult_x_23_n663) );
CMPR42X1TS U7934 ( .A(mult_x_23_n1261), .B(mult_x_23_n1183), .C(
mult_x_23_n1235), .D(mult_x_23_n1287), .ICI(mult_x_23_n659), .S(
mult_x_23_n650), .ICO(mult_x_23_n648), .CO(mult_x_23_n649) );
CMPR42X1TS U7935 ( .A(DP_OP_169J43_123_4229_n1676), .B(
DP_OP_169J43_123_4229_n1648), .C(DP_OP_169J43_123_4229_n997), .D(
DP_OP_169J43_123_4229_n994), .ICI(DP_OP_169J43_123_4229_n1001), .S(
DP_OP_169J43_123_4229_n973), .ICO(DP_OP_169J43_123_4229_n971), .CO(
DP_OP_169J43_123_4229_n972) );
CMPR42X1TS U7936 ( .A(mult_x_23_n1182), .B(mult_x_23_n654), .C(
mult_x_23_n1312), .D(mult_x_23_n1286), .ICI(mult_x_23_n651), .S(
mult_x_23_n642), .ICO(mult_x_23_n640), .CO(mult_x_23_n641) );
CMPR42X1TS U7937 ( .A(DP_OP_169J43_123_4229_n1357), .B(
DP_OP_169J43_123_4229_n1413), .C(DP_OP_169J43_123_4229_n1497), .D(
DP_OP_169J43_123_4229_n1469), .ICI(DP_OP_169J43_123_4229_n813), .S(
DP_OP_169J43_123_4229_n798), .ICO(DP_OP_169J43_123_4229_n796), .CO(
DP_OP_169J43_123_4229_n797) );
CMPR42X1TS U7938 ( .A(mult_x_24_n1344), .B(mult_x_24_n1371), .C(
mult_x_24_n1398), .D(mult_x_24_n610), .ICI(mult_x_24_n615), .S(
mult_x_24_n608), .ICO(mult_x_24_n606), .CO(mult_x_24_n607) );
CMPR42X1TS U7939 ( .A(DP_OP_169J43_123_4229_n1506), .B(
DP_OP_169J43_123_4229_n1590), .C(DP_OP_169J43_123_4229_n1618), .D(
DP_OP_169J43_123_4229_n957), .ICI(DP_OP_169J43_123_4229_n944), .S(
DP_OP_169J43_123_4229_n938), .ICO(DP_OP_169J43_123_4229_n936), .CO(
DP_OP_169J43_123_4229_n937) );
CMPR42X1TS U7940 ( .A(mult_x_23_n1205), .B(mult_x_23_n619), .C(
mult_x_23_n1179), .D(mult_x_23_n1231), .ICI(mult_x_23_n620), .S(
mult_x_23_n607), .ICO(mult_x_23_n605), .CO(mult_x_23_n606) );
CMPR42X1TS U7941 ( .A(mult_x_23_n1234), .B(mult_x_23_n644), .C(
mult_x_23_n1208), .D(mult_x_23_n1260), .ICI(mult_x_23_n648), .S(
mult_x_23_n639), .ICO(mult_x_23_n637), .CO(mult_x_23_n638) );
CMPR42X1TS U7942 ( .A(mult_x_23_n1263), .B(mult_x_23_n677), .C(
mult_x_23_n1237), .D(mult_x_23_n1289), .ICI(mult_x_23_n681), .S(
mult_x_23_n672), .ICO(mult_x_23_n670), .CO(mult_x_23_n671) );
CMPR42X1TS U7943 ( .A(DP_OP_169J43_123_4229_n837), .B(
DP_OP_169J43_123_4229_n846), .C(DP_OP_169J43_123_4229_n847), .D(
DP_OP_169J43_123_4229_n834), .ICI(DP_OP_169J43_123_4229_n843), .S(
DP_OP_169J43_123_4229_n831), .ICO(DP_OP_169J43_123_4229_n829), .CO(
DP_OP_169J43_123_4229_n830) );
CMPR42X1TS U7944 ( .A(mult_x_23_n717), .B(mult_x_23_n1344), .C(
mult_x_23_n1292), .D(mult_x_23_n1318), .ICI(mult_x_23_n718), .S(
mult_x_23_n705), .ICO(mult_x_23_n703), .CO(mult_x_23_n704) );
CMPR42X1TS U7945 ( .A(DP_OP_169J43_123_4229_n1557), .B(
DP_OP_169J43_123_4229_n1473), .C(DP_OP_169J43_123_4229_n1529), .D(
DP_OP_169J43_123_4229_n856), .ICI(DP_OP_169J43_123_4229_n872), .S(
DP_OP_169J43_123_4229_n851), .ICO(DP_OP_169J43_123_4229_n849), .CO(
DP_OP_169J43_123_4229_n850) );
CMPR42X1TS U7946 ( .A(DP_OP_169J43_123_4229_n1587), .B(
DP_OP_169J43_123_4229_n1503), .C(DP_OP_169J43_123_4229_n1531), .D(
DP_OP_169J43_123_4229_n1559), .ICI(DP_OP_169J43_123_4229_n900), .S(
DP_OP_169J43_123_4229_n882), .ICO(DP_OP_169J43_123_4229_n880), .CO(
DP_OP_169J43_123_4229_n881) );
CMPR42X1TS U7947 ( .A(DP_OP_169J43_123_4229_n1588), .B(
DP_OP_169J43_123_4229_n1504), .C(DP_OP_169J43_123_4229_n1532), .D(
DP_OP_169J43_123_4229_n920), .ICI(DP_OP_169J43_123_4229_n914), .S(
DP_OP_169J43_123_4229_n899), .ICO(DP_OP_169J43_123_4229_n897), .CO(
DP_OP_169J43_123_4229_n898) );
CMPR42X1TS U7948 ( .A(mult_x_23_n616), .B(mult_x_23_n610), .C(mult_x_23_n617), .D(mult_x_23_n607), .ICI(mult_x_23_n613), .S(mult_x_23_n604), .ICO(
mult_x_23_n602), .CO(mult_x_23_n603) );
CMPR42X1TS U7949 ( .A(mult_x_24_n1317), .B(mult_x_24_n618), .C(
mult_x_24_n616), .D(mult_x_24_n608), .ICI(mult_x_24_n612), .S(
mult_x_24_n605), .ICO(mult_x_24_n603), .CO(mult_x_24_n604) );
CMPR42X1TS U7950 ( .A(mult_x_23_n1198), .B(mult_x_23_n1146), .C(
mult_x_23_n555), .D(mult_x_23_n550), .ICI(mult_x_23_n551), .S(
mult_x_23_n548), .ICO(mult_x_23_n546), .CO(mult_x_23_n547) );
CMPR42X1TS U7951 ( .A(mult_x_24_n1368), .B(mult_x_24_n591), .C(
mult_x_24_n592), .D(mult_x_24_n586), .ICI(mult_x_24_n588), .S(
mult_x_24_n583), .ICO(mult_x_24_n581), .CO(mult_x_24_n582) );
CMPR42X1TS U7952 ( .A(DP_OP_169J43_123_4229_n775), .B(
DP_OP_169J43_123_4229_n767), .C(DP_OP_169J43_123_4229_n772), .D(
DP_OP_169J43_123_4229_n764), .ICI(DP_OP_169J43_123_4229_n768), .S(
DP_OP_169J43_123_4229_n761), .ICO(DP_OP_169J43_123_4229_n759), .CO(
DP_OP_169J43_123_4229_n760) );
CMPR42X1TS U7953 ( .A(mult_x_24_n947), .B(mult_x_24_n594), .C(
mult_x_24_n1395), .D(mult_x_24_n1341), .ICI(mult_x_24_n1314), .S(
mult_x_24_n586), .ICO(mult_x_24_n584), .CO(mult_x_24_n585) );
CMPR42X1TS U7954 ( .A(DP_OP_169J43_123_4229_n1383), .B(
DP_OP_169J43_123_4229_n1439), .C(DP_OP_169J43_123_4229_n1355), .D(
DP_OP_169J43_123_4229_n1411), .ICI(DP_OP_169J43_123_4229_n785), .S(
DP_OP_169J43_123_4229_n773), .ICO(DP_OP_169J43_123_4229_n771), .CO(
DP_OP_169J43_123_4229_n772) );
CMPR42X1TS U7955 ( .A(mult_x_24_n1340), .B(mult_x_24_n584), .C(
mult_x_24_n585), .D(mult_x_24_n580), .ICI(mult_x_24_n581), .S(
mult_x_24_n577), .ICO(mult_x_24_n575), .CO(mult_x_24_n576) );
CMPR42X1TS U7956 ( .A(mult_x_24_n1366), .B(mult_x_24_n1339), .C(
mult_x_24_n573), .D(mult_x_24_n579), .ICI(mult_x_24_n575), .S(
mult_x_24_n571), .ICO(mult_x_24_n569), .CO(mult_x_24_n570) );
CMPR42X1TS U7957 ( .A(n6557), .B(mult_x_23_n557), .C(mult_x_23_n1124), .D(
mult_x_23_n1172), .ICI(mult_x_23_n554), .S(mult_x_23_n550), .ICO(
mult_x_23_n544), .CO(mult_x_23_n549) );
CMPR42X1TS U7958 ( .A(mult_x_23_n1170), .B(mult_x_23_n542), .C(
mult_x_23_n536), .D(mult_x_23_n1144), .ICI(mult_x_23_n539), .S(
mult_x_23_n534), .ICO(mult_x_23_n532), .CO(mult_x_23_n533) );
CMPR42X1TS U7959 ( .A(mult_x_24_n1311), .B(mult_x_24_n1338), .C(
mult_x_24_n567), .D(mult_x_24_n572), .ICI(mult_x_24_n569), .S(
mult_x_24_n565), .ICO(mult_x_24_n563), .CO(mult_x_24_n564) );
CMPR42X1TS U7960 ( .A(mult_x_24_n562), .B(mult_x_24_n566), .C(
mult_x_24_n1337), .D(mult_x_24_n1310), .ICI(mult_x_24_n563), .S(
mult_x_24_n560), .ICO(mult_x_24_n558), .CO(mult_x_24_n559) );
CMPR42X1TS U7961 ( .A(DP_OP_169J43_123_4229_n1436), .B(
DP_OP_169J43_123_4229_n1408), .C(DP_OP_169J43_123_4229_n1380), .D(
DP_OP_169J43_123_4229_n748), .ICI(DP_OP_169J43_123_4229_n752), .S(
DP_OP_169J43_123_4229_n746), .ICO(DP_OP_169J43_123_4229_n744), .CO(
DP_OP_169J43_123_4229_n745) );
CMPR42X1TS U7962 ( .A(mult_x_23_n526), .B(mult_x_23_n1168), .C(
mult_x_23_n530), .D(mult_x_23_n1142), .ICI(mult_x_23_n527), .S(
mult_x_23_n525), .ICO(mult_x_23_n523), .CO(mult_x_23_n524) );
CMPR42X1TS U7963 ( .A(DP_OP_169J43_123_4229_n1434), .B(
DP_OP_169J43_123_4229_n739), .C(DP_OP_169J43_123_4229_n1331), .D(
DP_OP_169J43_123_4229_n1406), .ICI(DP_OP_169J43_123_4229_n1378), .S(
DP_OP_169J43_123_4229_n732), .ICO(DP_OP_169J43_123_4229_n730), .CO(
DP_OP_169J43_123_4229_n731) );
CMPR42X1TS U7964 ( .A(mult_x_24_n941), .B(mult_x_24_n557), .C(
mult_x_24_n1335), .D(mult_x_24_n1308), .ICI(mult_x_24_n554), .S(
mult_x_24_n552), .ICO(mult_x_24_n550), .CO(mult_x_24_n551) );
CMPR42X1TS U7965 ( .A(DP_OP_169J43_123_4229_n1376), .B(
DP_OP_169J43_123_4229_n1348), .C(DP_OP_169J43_123_4229_n719), .D(
DP_OP_169J43_123_4229_n723), .ICI(DP_OP_169J43_123_4229_n720), .S(
DP_OP_169J43_123_4229_n717), .ICO(DP_OP_169J43_123_4229_n715), .CO(
DP_OP_169J43_123_4229_n716) );
CMPR42X1TS U7966 ( .A(DP_OP_169J43_123_4229_n1375), .B(
DP_OP_169J43_123_4229_n714), .C(DP_OP_169J43_123_4229_n1347), .D(
DP_OP_169J43_123_4229_n718), .ICI(DP_OP_169J43_123_4229_n715), .S(
DP_OP_169J43_123_4229_n712), .ICO(DP_OP_169J43_123_4229_n710), .CO(
DP_OP_169J43_123_4229_n711) );
CMPR42X1TS U7967 ( .A(DP_OP_169J43_123_4229_n1374), .B(
DP_OP_169J43_123_4229_n713), .C(DP_OP_169J43_123_4229_n1329), .D(
DP_OP_169J43_123_4229_n1346), .ICI(DP_OP_169J43_123_4229_n710), .S(
DP_OP_169J43_123_4229_n709), .ICO(DP_OP_169J43_123_4229_n707), .CO(
DP_OP_169J43_123_4229_n708) );
initial $sdf_annotate("FPU_Multiplication_Function_ASIC_fpu_syn_constraints_clk20.tcl_KOA_2STAGE_syn.sdf");
endmodule
|
module sky130_fd_sc_ms__ha_2 (
COUT,
SUM ,
A ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
output COUT;
output SUM ;
input A ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ms__ha base (
.COUT(COUT),
.SUM(SUM),
.A(A),
.B(B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
|
module sky130_fd_sc_ms__ha_2 (
COUT,
SUM ,
A ,
B
);
output COUT;
output SUM ;
input A ;
input B ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__ha base (
.COUT(COUT),
.SUM(SUM),
.A(A),
.B(B)
);
endmodule
|
module sky130_fd_sc_ms__dlymetal6s6s (
//# {{data|Data Signals}}
input A ,
output X ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
|
module sky130_fd_sc_hs__a2bb2o (
VPWR,
VGND,
X ,
A1_N,
A2_N,
B1 ,
B2
);
// Module ports
input VPWR;
input VGND;
output X ;
input A1_N;
input A2_N;
input B1 ;
input B2 ;
// Local signals
wire B2 and0_out ;
wire B2 nor0_out ;
wire or0_out_X ;
wire u_vpwr_vgnd0_out_X;
// Name Output Other arguments
and and0 (and0_out , B1, B2 );
nor nor0 (nor0_out , A1_N, A2_N );
or or0 (or0_out_X , nor0_out, and0_out );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_X, or0_out_X, VPWR, VGND);
buf buf0 (X , u_vpwr_vgnd0_out_X );
endmodule
|
module top(CLCK, SCL, SDA, CNT1A, CNT1B, CNT2A,CNT2B, CNT3A, CNT3B, CNT4A, CNT4B);
input CLCK;
input SCL;
inout SDA;
input CNT1A;
input CNT1B;
input CNT2A;
input CNT2B;
input CNT3A;
input CNT3B;
input CNT4A;
input CNT4B;
wire[15:0] CNTR1;
wire[15:0] CNTR2;
wire[15:0] CNTR3;
wire[15:0] CNTR4;
wire[7:0] CMD;
wire[1:0] TEND;
quad counter1(.clk (CLCK),
.quadA (CNT1A),
.quadB (CNT1B),
.count (CNTR1),
.CMD (CMD),
.TEND (TEND));
quad counter2(.clk (CLCK),
.quadA (CNT2A),
.quadB (CNT2B),
.count (CNTR2),
.CMD (CMD),
.TEND (TEND));
quad counter3(.clk (CLCK),
.quadA (CNT3A),
.quadB (CNT3B),
.count (CNTR3),
.CMD (CMD),
.TEND (TEND));
quad counter4(.clk (CLCK),
.quadA (CNT4A),
.quadB (CNT4B),
.count (CNTR4),
.CMD (CMD),
.TEND (TEND));
I2CSlave(.CLCK (CLCK),
.SCL (SCL),
.SDA (SDA),
.CNTR1 (CNTR1),
.CNTR2 (CNTR2),
.CNTR3 (CNTR3),
.CNTR4 (CNTR4),
.CMD (CMD),
.TEND (TEND));
endmodule
|
module sky130_fd_sc_ls__o2bb2a_2 (
X ,
A1_N,
A2_N,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1_N;
input A2_N;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__o2bb2a base (
.X(X),
.A1_N(A1_N),
.A2_N(A2_N),
.B1(B1),
.B2(B2),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
|
module sky130_fd_sc_ls__o2bb2a_2 (
X ,
A1_N,
A2_N,
B1 ,
B2
);
output X ;
input A1_N;
input A2_N;
input B1 ;
input B2 ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__o2bb2a base (
.X(X),
.A1_N(A1_N),
.A2_N(A2_N),
.B1(B1),
.B2(B2)
);
endmodule
|
module adders_io (
ap_clk,
ap_rst,
ap_start,
ap_done,
ap_idle,
ap_ready,
in1,
in1_ap_vld,
in2,
in2_ap_ack,
in_out1_i,
in_out1_i_ap_vld,
in_out1_i_ap_ack,
in_out1_o,
in_out1_o_ap_vld,
in_out1_o_ap_ack
);
parameter ap_ST_fsm_state1 = 2'd1;
parameter ap_ST_fsm_state2 = 2'd2;
input ap_clk;
input ap_rst;
input ap_start;
output ap_done;
output ap_idle;
output ap_ready;
input [31:0] in1;
input in1_ap_vld;
input [31:0] in2;
output in2_ap_ack;
input [31:0] in_out1_i;
input in_out1_i_ap_vld;
output in_out1_i_ap_ack;
output [31:0] in_out1_o;
output in_out1_o_ap_vld;
input in_out1_o_ap_ack;
reg ap_done;
reg ap_idle;
reg ap_ready;
reg in2_ap_ack;
reg in_out1_i_ap_ack;
reg in_out1_o_ap_vld;
(* fsm_encoding = "none" *) reg [1:0] ap_CS_fsm;
wire ap_CS_fsm_state1;
reg [31:0] in1_preg;
reg [31:0] in1_in_sig;
reg in1_ap_vld_preg;
reg in1_ap_vld_in_sig;
reg in1_blk_n;
reg in_out1_i_blk_n;
reg in_out1_o_blk_n;
wire ap_CS_fsm_state2;
reg [31:0] in_out1_read_reg_68;
reg ap_block_state1;
wire [31:0] tmp1_fu_57_p2;
reg [31:0] tmp1_reg_73;
reg ap_reg_ioackin_in_out1_o_ap_ack;
reg ap_sig_ioackin_in_out1_o_ap_ack;
reg [1:0] ap_NS_fsm;
// power-on initialization
initial begin
#0 ap_CS_fsm = 2'd1;
#0 in1_preg = 32'd0;
#0 in1_ap_vld_preg = 1'b0;
#0 ap_reg_ioackin_in_out1_o_ap_ack = 1'b0;
end
always @ (posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_CS_fsm <= ap_ST_fsm_state1;
end else begin
ap_CS_fsm <= ap_NS_fsm;
end
end
always @ (posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_reg_ioackin_in_out1_o_ap_ack <= 1'b0;
end else begin
if ((1'b1 == ap_CS_fsm_state2)) begin
if ((ap_sig_ioackin_in_out1_o_ap_ack == 1'b1)) begin
ap_reg_ioackin_in_out1_o_ap_ack <= 1'b0;
end else if ((1'b1 == in_out1_o_ap_ack)) begin
ap_reg_ioackin_in_out1_o_ap_ack <= 1'b1;
end
end
end
end
always @ (posedge ap_clk) begin
if (ap_rst == 1'b1) begin
in1_ap_vld_preg <= 1'b0;
end else begin
if (((1'b1 == ap_CS_fsm_state2) & (ap_sig_ioackin_in_out1_o_ap_ack == 1'b1))) begin
in1_ap_vld_preg <= 1'b0;
end else if (((1'b1 == in1_ap_vld) & ~((1'b0 == ap_start) & (1'b1 == ap_CS_fsm_state1)))) begin
in1_ap_vld_preg <= in1_ap_vld;
end
end
end
always @ (posedge ap_clk) begin
if (ap_rst == 1'b1) begin
in1_preg <= 32'd0;
end else begin
if (((1'b1 == in1_ap_vld) & ~((1'b0 == ap_start) & (1'b1 == ap_CS_fsm_state1)))) begin
in1_preg <= in1;
end
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_state1) & ~((1'b0 == ap_start) | (1'b0 == in1_ap_vld_in_sig) | (1'b0 == in_out1_i_ap_vld)))) begin
in_out1_read_reg_68 <= in_out1_i;
tmp1_reg_73 <= tmp1_fu_57_p2;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_state2) & (ap_sig_ioackin_in_out1_o_ap_ack == 1'b1))) begin
ap_done = 1'b1;
end else begin
ap_done = 1'b0;
end
end
always @ (*) begin
if (((1'b0 == ap_start) & (1'b1 == ap_CS_fsm_state1))) begin
ap_idle = 1'b1;
end else begin
ap_idle = 1'b0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_state2) & (ap_sig_ioackin_in_out1_o_ap_ack == 1'b1))) begin
ap_ready = 1'b1;
end else begin
ap_ready = 1'b0;
end
end
always @ (*) begin
if ((1'b0 == ap_reg_ioackin_in_out1_o_ap_ack)) begin
ap_sig_ioackin_in_out1_o_ap_ack = in_out1_o_ap_ack;
end else begin
ap_sig_ioackin_in_out1_o_ap_ack = 1'b1;
end
end
always @ (*) begin
if ((1'b1 == in1_ap_vld)) begin
in1_ap_vld_in_sig = in1_ap_vld;
end else begin
in1_ap_vld_in_sig = in1_ap_vld_preg;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_state1) & (ap_start == 1'b1))) begin
in1_blk_n = in1_ap_vld;
end else begin
in1_blk_n = 1'b1;
end
end
always @ (*) begin
if ((1'b1 == in1_ap_vld)) begin
in1_in_sig = in1;
end else begin
in1_in_sig = in1_preg;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_state1) & ~((1'b0 == ap_start) | (1'b0 == in1_ap_vld_in_sig) | (1'b0 == in_out1_i_ap_vld)))) begin
in2_ap_ack = 1'b1;
end else begin
in2_ap_ack = 1'b0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_state1) & ~((1'b0 == ap_start) | (1'b0 == in1_ap_vld_in_sig) | (1'b0 == in_out1_i_ap_vld)))) begin
in_out1_i_ap_ack = 1'b1;
end else begin
in_out1_i_ap_ack = 1'b0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_state1) & (ap_start == 1'b1))) begin
in_out1_i_blk_n = in_out1_i_ap_vld;
end else begin
in_out1_i_blk_n = 1'b1;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_state2) & (1'b0 == ap_reg_ioackin_in_out1_o_ap_ack))) begin
in_out1_o_ap_vld = 1'b1;
end else begin
in_out1_o_ap_vld = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == ap_CS_fsm_state2)) begin
in_out1_o_blk_n = in_out1_o_ap_ack;
end else begin
in_out1_o_blk_n = 1'b1;
end
end
always @ (*) begin
case (ap_CS_fsm)
ap_ST_fsm_state1 : begin
if (((1'b1 == ap_CS_fsm_state1) & ~((1'b0 == ap_start) | (1'b0 == in1_ap_vld_in_sig) | (1'b0 == in_out1_i_ap_vld)))) begin
ap_NS_fsm = ap_ST_fsm_state2;
end else begin
ap_NS_fsm = ap_ST_fsm_state1;
end
end
ap_ST_fsm_state2 : begin
if (((1'b1 == ap_CS_fsm_state2) & (ap_sig_ioackin_in_out1_o_ap_ack == 1'b1))) begin
ap_NS_fsm = ap_ST_fsm_state1;
end else begin
ap_NS_fsm = ap_ST_fsm_state2;
end
end
default : begin
ap_NS_fsm = 'bx;
end
endcase
end
assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0];
assign ap_CS_fsm_state2 = ap_CS_fsm[32'd1];
always @ (*) begin
ap_block_state1 = ((1'b0 == ap_start) | (1'b0 == in1_ap_vld_in_sig) | (1'b0 == in_out1_i_ap_vld));
end
assign in_out1_o = (tmp1_reg_73 + in_out1_read_reg_68);
assign tmp1_fu_57_p2 = (in2 + in1_in_sig);
endmodule
|
module sky130_fd_sc_hd__o2bb2ai (
//# {{data|Data Signals}}
input A1_N,
input A2_N,
input B1 ,
input B2 ,
output Y ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
|
module sprite_ram_4Kx16 (
address_a,
address_b,
byteena_a,
clock_a,
clock_b,
data_a,
data_b,
wren_a,
wren_b,
q_a,
q_b);
input [11:0] address_a;
input [8:0] address_b;
input [1:0] byteena_a;
input clock_a;
input clock_b;
input [15:0] data_a;
input [127:0] data_b;
input wren_a;
input wren_b;
output [15:0] q_a;
output [127:0] q_b;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 [1:0] byteena_a;
tri1 clock_a;
tri0 wren_a;
tri0 wren_b;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [15:0] sub_wire0;
wire [127:0] sub_wire1;
wire [15:0] q_a = sub_wire0[15:0];
wire [127:0] q_b = sub_wire1[127:0];
altsyncram altsyncram_component (
.byteena_a (byteena_a),
.clock0 (clock_a),
.wren_a (wren_a),
.address_b (address_b),
.clock1 (clock_b),
.data_b (data_b),
.wren_b (wren_b),
.address_a (address_a),
.data_a (data_a),
.q_a (sub_wire0),
.q_b (sub_wire1),
.aclr0 (1'b0),
.aclr1 (1'b0),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_b (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.eccstatus (),
.rden_a (1'b1),
.rden_b (1'b1));
defparam
altsyncram_component.address_reg_b = "CLOCK1",
altsyncram_component.byte_size = 8,
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_input_b = "BYPASS",
altsyncram_component.clock_enable_output_a = "BYPASS",
altsyncram_component.clock_enable_output_b = "BYPASS",
altsyncram_component.indata_reg_b = "CLOCK1",
altsyncram_component.intended_device_family = "Cyclone IV E",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 4096,
altsyncram_component.numwords_b = 512,
altsyncram_component.operation_mode = "BIDIR_DUAL_PORT",
altsyncram_component.outdata_aclr_a = "NONE",
altsyncram_component.outdata_aclr_b = "NONE",
altsyncram_component.outdata_reg_a = "UNREGISTERED",
altsyncram_component.outdata_reg_b = "UNREGISTERED",
altsyncram_component.power_up_uninitialized = "FALSE",
altsyncram_component.read_during_write_mode_port_a = "NEW_DATA_NO_NBE_READ",
altsyncram_component.read_during_write_mode_port_b = "NEW_DATA_NO_NBE_READ",
altsyncram_component.widthad_a = 12,
altsyncram_component.widthad_b = 9,
altsyncram_component.width_a = 16,
altsyncram_component.width_b = 128,
altsyncram_component.width_byteena_a = 2,
altsyncram_component.width_byteena_b = 1,
altsyncram_component.wrcontrol_wraddress_reg_b = "CLOCK1";
endmodule
|
module axi_read_slave #(
parameter DATA_WIDTH = 32,
parameter READ_ACCEPTANCE = 4,
parameter MIN_LATENCY = 48,
parameter MAX_LATENCY = 48
) (
input clk,
input reset,
input arvalid,
output arready,
input [31:0] araddr,
input [7:0] arlen,
input [2:0] arsize,
input [1:0] arburst,
input [2:0] arprot,
input [3:0] arcache,
output rvalid,
input rready,
output [DATA_WIDTH-1:0] rdata,
output [1:0] rresp,
output rlast
);
reg [DATA_WIDTH-1:0] data = 'h00;
assign rresp = 2'b00;
//assign rdata = data;
always @(posedge clk) begin
if (reset == 1'b1) begin
data <= 'h00;
end else if (rvalid == 1'b1 && rready == 1'b1) begin
data <= data + 1'b1;
end
end
axi_slave #(
.ACCEPTANCE(READ_ACCEPTANCE),
.MIN_LATENCY(MIN_LATENCY),
.MAX_LATENCY(MAX_LATENCY)
) i_axi_slave (
.clk(clk),
.reset(reset),
.valid(arvalid),
.ready(arready),
.addr(araddr),
.len(arlen),
.size(arsize),
.burst(arburst),
.prot(arprot),
.cache(arcache),
.beat_stb(rvalid),
.beat_ack(rvalid & rready),
.beat_last(rlast),
.beat_addr(rdata)
);
endmodule
|
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.