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module tx_engine
#(parameter C_DATA_WIDTH = 128,
parameter C_DEPTH_PACKETS = 10,
parameter C_PIPELINE_INPUT = 1,
parameter C_PIPELINE_OUTPUT = 0,
parameter C_FORMATTER_DELAY = 1,
parameter C_MAX_HDR_WIDTH = 128,
parameter C_MAX_PAYLOAD_DWORDS = 64,
parameter C_VENDOR = "ALTERA"
)
(
// Interface: Clocks
input CLK,
// Interface: Reset
input RST_IN,
// Interface: TX HDR
input TX_HDR_VALID,
input [C_MAX_HDR_WIDTH-1:0] TX_HDR,
input [`SIG_LEN_W-1:0] TX_HDR_PAYLOAD_LEN,
input [`SIG_NONPAY_W-1:0] TX_HDR_NONPAY_LEN,
input [`SIG_PACKETLEN_W-1:0] TX_HDR_PACKET_LEN,
input TX_HDR_NOPAYLOAD,
output TX_HDR_READY,
// Interface: TX_DATA
input TX_DATA_VALID,
input [C_DATA_WIDTH-1:0] TX_DATA,
input TX_DATA_START_FLAG,
input [clog2s(C_DATA_WIDTH/32)-1:0] TX_DATA_START_OFFSET,
input TX_DATA_END_FLAG,
input [clog2s(C_DATA_WIDTH/32)-1:0] TX_DATA_END_OFFSET,
output TX_DATA_READY,
// Interface: TX_PKT
input TX_PKT_READY,
output [C_DATA_WIDTH-1:0] TX_PKT,
output TX_PKT_START_FLAG,
output [clog2s(C_DATA_WIDTH/32)-1:0] TX_PKT_START_OFFSET,
output TX_PKT_END_FLAG,
output [clog2s(C_DATA_WIDTH/32)-1:0] TX_PKT_END_OFFSET,
output TX_PKT_VALID
);
`include "functions.vh"
localparam C_PIPELINE_HDR_FIFO_INPUT = C_PIPELINE_INPUT;
localparam C_PIPELINE_HDR_FIFO_OUTPUT = C_PIPELINE_OUTPUT;
localparam C_PIPELINE_HDR_INPUT = C_PIPELINE_INPUT;
localparam C_ACTUAL_HDR_FIFO_DEPTH = (1<<clog2s(C_DEPTH_PACKETS));
localparam C_USE_COMPUTE_REG = 1;
localparam C_USE_READY_REG = 1;
localparam C_USE_FWFT_HDR_FIFO = 1;
localparam C_DATA_FIFO_DEPTH = C_ACTUAL_HDR_FIFO_DEPTH + C_FORMATTER_DELAY +
C_PIPELINE_HDR_FIFO_INPUT + C_PIPELINE_HDR_FIFO_OUTPUT + C_USE_FWFT_HDR_FIFO + // Header Fifo
C_PIPELINE_HDR_INPUT + C_USE_COMPUTE_REG + C_USE_READY_REG + C_PIPELINE_OUTPUT;
wire wTxHdrReady;
wire wTxHdrValid;
wire [C_MAX_HDR_WIDTH-1:0] wTxHdr;
wire [`SIG_NONPAY_W-1:0] wTxHdrNonpayLen;
wire [`SIG_PACKETLEN_W-1:0] wTxHdrPacketLen;
wire [`SIG_LEN_W-1:0] wTxHdrPayloadLen;
wire wTxHdrNoPayload;
wire wTxDataReady;
wire [C_DATA_WIDTH-1:0] wTxData;
wire [clog2s(C_DATA_WIDTH/32)-1:0] wTxDataEndOffset;
wire wTxDataStartFlag;
wire wTxDataPacketValid;
wire [(C_DATA_WIDTH/32)-1:0] wTxDataEndFlags;
wire [(C_DATA_WIDTH/32)-1:0] wTxDataWordValid;
wire [(C_DATA_WIDTH/32)-1:0] wTxDataWordReady;
tx_data_pipeline
#(.C_DEPTH_PACKETS (C_DATA_FIFO_DEPTH),
/*AUTOINSTPARAM*/
// Parameters
.C_DATA_WIDTH (C_DATA_WIDTH),
.C_PIPELINE_INPUT (C_PIPELINE_INPUT),
.C_PIPELINE_OUTPUT (C_PIPELINE_OUTPUT),
.C_MAX_PAYLOAD_DWORDS (C_MAX_PAYLOAD_DWORDS),
.C_VENDOR (C_VENDOR))
tx_data_pipeline_inst
(// Outputs
.RD_TX_DATA (wTxData[C_DATA_WIDTH-1:0]),
.RD_TX_DATA_WORD_VALID (wTxDataWordValid[(C_DATA_WIDTH/32)-1:0]),
.RD_TX_DATA_START_FLAG (wTxDataStartFlag),
.RD_TX_DATA_END_FLAGS (wTxDataEndFlags[(C_DATA_WIDTH/32)-1:0]),
.RD_TX_DATA_PACKET_VALID (wTxDataPacketValid),
.WR_TX_DATA_READY (TX_DATA_READY),
// Inputs
.RD_TX_DATA_WORD_READY (wTxDataWordReady[(C_DATA_WIDTH/32)-1:0]),
.WR_TX_DATA (TX_DATA),
.WR_TX_DATA_VALID (TX_DATA_VALID),
.WR_TX_DATA_START_FLAG (TX_DATA_START_FLAG),
.WR_TX_DATA_START_OFFSET (TX_DATA_START_OFFSET[clog2s(C_DATA_WIDTH/32)-1:0]),
.WR_TX_DATA_END_FLAG (TX_DATA_END_FLAG),
.WR_TX_DATA_END_OFFSET (TX_DATA_END_OFFSET[clog2s(C_DATA_WIDTH/32)-1:0]),
/*AUTOINST*/
// Inputs
.CLK (CLK),
.RST_IN (RST_IN));
// TX Header Fifo
tx_hdr_fifo
#(.C_PIPELINE_OUTPUT (C_PIPELINE_HDR_FIFO_OUTPUT),
.C_PIPELINE_INPUT (C_PIPELINE_HDR_FIFO_INPUT),
/*AUTOINSTPARAM*/
// Parameters
.C_DEPTH_PACKETS (C_DEPTH_PACKETS),
.C_MAX_HDR_WIDTH (C_MAX_HDR_WIDTH),
.C_VENDOR (C_VENDOR))
txhf_inst
(// Outputs
.WR_TX_HDR_READY (TX_HDR_READY),
.RD_TX_HDR (wTxHdr[C_MAX_HDR_WIDTH-1:0]),
.RD_TX_HDR_VALID (wTxHdrValid),
.RD_TX_HDR_NOPAYLOAD (wTxHdrNoPayload),
.RD_TX_HDR_PAYLOAD_LEN (wTxHdrPayloadLen[`SIG_LEN_W-1:0]),
.RD_TX_HDR_NONPAY_LEN (wTxHdrNonpayLen[`SIG_NONPAY_W-1:0]),
.RD_TX_HDR_PACKET_LEN (wTxHdrPacketLen[`SIG_PACKETLEN_W-1:0]),
// Inputs
.WR_TX_HDR (TX_HDR[C_MAX_HDR_WIDTH-1:0]),
.WR_TX_HDR_VALID (TX_HDR_VALID),
.WR_TX_HDR_NOPAYLOAD (TX_HDR_NOPAYLOAD),
.WR_TX_HDR_PAYLOAD_LEN (TX_HDR_PAYLOAD_LEN[`SIG_LEN_W-1:0]),
.WR_TX_HDR_NONPAY_LEN (TX_HDR_NONPAY_LEN[`SIG_NONPAY_W-1:0]),
.WR_TX_HDR_PACKET_LEN (TX_HDR_PACKET_LEN[`SIG_PACKETLEN_W-1:0]),
.RD_TX_HDR_READY (wTxHdrReady),
/*AUTOINST*/
// Inputs
.CLK (CLK),
.RST_IN (RST_IN));
// TX Header Fifo
tx_alignment_pipeline
#(// Parameters
.C_PIPELINE_OUTPUT (1),
.C_PIPELINE_DATA_INPUT (1),
.C_PIPELINE_HDR_INPUT (C_PIPELINE_HDR_INPUT),
.C_DATA_WIDTH (C_DATA_WIDTH),
// Parameters
/*AUTOINSTPARAM*/
// Parameters
.C_USE_COMPUTE_REG (C_USE_COMPUTE_REG),
.C_USE_READY_REG (C_USE_READY_REG),
.C_MAX_HDR_WIDTH (C_MAX_HDR_WIDTH),
.C_VENDOR (C_VENDOR))
tx_alignment_inst
(// Outputs
.TX_DATA_WORD_READY (wTxDataWordReady[(C_DATA_WIDTH/32)-1:0]),
.TX_HDR_READY (wTxHdrReady),
// Inputs
.TX_DATA_START_FLAG (wTxDataStartFlag),
.TX_DATA_END_FLAGS (wTxDataEndFlags),
.TX_DATA_WORD_VALID (wTxDataWordValid[(C_DATA_WIDTH/32)-1:0]),
.TX_DATA_PACKET_VALID (wTxDataPacketValid),
.TX_DATA (wTxData[C_DATA_WIDTH-1:0]),
.TX_HDR (wTxHdr[C_MAX_HDR_WIDTH-1:0]),
.TX_HDR_VALID (wTxHdrValid),
.TX_HDR_NOPAYLOAD (wTxHdrNoPayload),
.TX_HDR_PAYLOAD_LEN (wTxHdrPayloadLen[`SIG_LEN_W-1:0]),
.TX_HDR_NONPAY_LEN (wTxHdrNonpayLen[`SIG_NONPAY_W-1:0]),
.TX_HDR_PACKET_LEN (wTxHdrPacketLen[`SIG_PACKETLEN_W-1:0]),
/*AUTOINST*/
// Outputs
.TX_PKT (TX_PKT[C_DATA_WIDTH-1:0]),
.TX_PKT_START_FLAG (TX_PKT_START_FLAG),
.TX_PKT_START_OFFSET (TX_PKT_START_OFFSET[clog2s(C_DATA_WIDTH/32)-1:0]),
.TX_PKT_END_FLAG (TX_PKT_END_FLAG),
.TX_PKT_END_OFFSET (TX_PKT_END_OFFSET[clog2s(C_DATA_WIDTH/32)-1:0]),
.TX_PKT_VALID (TX_PKT_VALID),
// Inputs
.CLK (CLK),
.RST_IN (RST_IN),
.TX_PKT_READY (TX_PKT_READY));
endmodule
|
module user_design(clk, rst, exception, input_timer, input_rs232_rx, input_ps2, input_i2c, input_switches, input_eth_rx, input_buttons, input_timer_stb, input_rs232_rx_stb, input_ps2_stb, input_i2c_stb, input_switches_stb, input_eth_rx_stb, input_buttons_stb, input_timer_ack, input_rs232_rx_ack, input_ps2_ack, input_i2c_ack, input_switches_ack, input_eth_rx_ack, input_buttons_ack, output_seven_segment_annode, output_eth_tx, output_rs232_tx, output_leds, output_audio, output_led_g, output_seven_segment_cathode, output_led_b, output_i2c, output_vga, output_led_r, output_seven_segment_annode_stb, output_eth_tx_stb, output_rs232_tx_stb, output_leds_stb, output_audio_stb, output_led_g_stb, output_seven_segment_cathode_stb, output_led_b_stb, output_i2c_stb, output_vga_stb, output_led_r_stb, output_seven_segment_annode_ack, output_eth_tx_ack, output_rs232_tx_ack, output_leds_ack, output_audio_ack, output_led_g_ack, output_seven_segment_cathode_ack, output_led_b_ack, output_i2c_ack, output_vga_ack, output_led_r_ack);
input clk;
input rst;
output exception;
input [31:0] input_timer;
input input_timer_stb;
output input_timer_ack;
input [31:0] input_rs232_rx;
input input_rs232_rx_stb;
output input_rs232_rx_ack;
input [31:0] input_ps2;
input input_ps2_stb;
output input_ps2_ack;
input [31:0] input_i2c;
input input_i2c_stb;
output input_i2c_ack;
input [31:0] input_switches;
input input_switches_stb;
output input_switches_ack;
input [31:0] input_eth_rx;
input input_eth_rx_stb;
output input_eth_rx_ack;
input [31:0] input_buttons;
input input_buttons_stb;
output input_buttons_ack;
output [31:0] output_seven_segment_annode;
output output_seven_segment_annode_stb;
input output_seven_segment_annode_ack;
output [31:0] output_eth_tx;
output output_eth_tx_stb;
input output_eth_tx_ack;
output [31:0] output_rs232_tx;
output output_rs232_tx_stb;
input output_rs232_tx_ack;
output [31:0] output_leds;
output output_leds_stb;
input output_leds_ack;
output [31:0] output_audio;
output output_audio_stb;
input output_audio_ack;
output [31:0] output_led_g;
output output_led_g_stb;
input output_led_g_ack;
output [31:0] output_seven_segment_cathode;
output output_seven_segment_cathode_stb;
input output_seven_segment_cathode_ack;
output [31:0] output_led_b;
output output_led_b_stb;
input output_led_b_ack;
output [31:0] output_i2c;
output output_i2c_stb;
input output_i2c_ack;
output [31:0] output_vga;
output output_vga_stb;
input output_vga_ack;
output [31:0] output_led_r;
output output_led_r_stb;
input output_led_r_ack;
wire [31:0] wire_139931276046560;
wire wire_139931276046560_stb;
wire wire_139931276046560_ack;
wire exception_139931282298208;
wire exception_139931279302312;
wire exception_139931282298568;
wire exception_139931276022632;
wire exception_139931284594768;
wire exception_139931283933808;
wire exception_139931274793904;
wire exception_139931280104840;
wire exception_139931276181376;
wire exception_139931279234472;
wire exception_139931282558560;
wire exception_139931284812000;
wire exception_139931278184392;
wire exception_139931274909024;
wire exception_139931275225496;
wire exception_139931277018680;
wire exception_139931277927848;
wire exception_139931279974624;
main_0 main_0_139931282298208(
.clk(clk),
.rst(rst),
.exception(exception_139931282298208),
.output_value(wire_139931276046560),
.output_value_stb(wire_139931276046560_stb),
.output_value_ack(wire_139931276046560_ack));
main_1 main_1_139931279302312(
.clk(clk),
.rst(rst),
.exception(exception_139931279302312),
.input_value(wire_139931276046560),
.input_value_stb(wire_139931276046560_stb),
.input_value_ack(wire_139931276046560_ack),
.output_annode(output_seven_segment_annode),
.output_annode_stb(output_seven_segment_annode_stb),
.output_annode_ack(output_seven_segment_annode_ack),
.output_cathode(output_seven_segment_cathode),
.output_cathode_stb(output_seven_segment_cathode_stb),
.output_cathode_ack(output_seven_segment_cathode_ack));
main_2 main_2_139931282298568(
.clk(clk),
.rst(rst),
.exception(exception_139931282298568),
.input_in(input_timer),
.input_in_stb(input_timer_stb),
.input_in_ack(input_timer_ack));
main_3 main_3_139931276022632(
.clk(clk),
.rst(rst),
.exception(exception_139931276022632),
.input_in(input_rs232_rx),
.input_in_stb(input_rs232_rx_stb),
.input_in_ack(input_rs232_rx_ack));
main_4 main_4_139931284594768(
.clk(clk),
.rst(rst),
.exception(exception_139931284594768),
.input_in(input_ps2),
.input_in_stb(input_ps2_stb),
.input_in_ack(input_ps2_ack));
main_5 main_5_139931283933808(
.clk(clk),
.rst(rst),
.exception(exception_139931283933808),
.input_in(input_i2c),
.input_in_stb(input_i2c_stb),
.input_in_ack(input_i2c_ack));
main_6 main_6_139931274793904(
.clk(clk),
.rst(rst),
.exception(exception_139931274793904),
.input_in(input_switches),
.input_in_stb(input_switches_stb),
.input_in_ack(input_switches_ack));
main_7 main_7_139931280104840(
.clk(clk),
.rst(rst),
.exception(exception_139931280104840),
.input_in(input_eth_rx),
.input_in_stb(input_eth_rx_stb),
.input_in_ack(input_eth_rx_ack));
main_8 main_8_139931276181376(
.clk(clk),
.rst(rst),
.exception(exception_139931276181376),
.input_in(input_buttons),
.input_in_stb(input_buttons_stb),
.input_in_ack(input_buttons_ack));
main_9 main_9_139931279234472(
.clk(clk),
.rst(rst),
.exception(exception_139931279234472),
.output_out(output_eth_tx),
.output_out_stb(output_eth_tx_stb),
.output_out_ack(output_eth_tx_ack));
main_10 main_10_139931282558560(
.clk(clk),
.rst(rst),
.exception(exception_139931282558560),
.output_out(output_rs232_tx),
.output_out_stb(output_rs232_tx_stb),
.output_out_ack(output_rs232_tx_ack));
main_11 main_11_139931284812000(
.clk(clk),
.rst(rst),
.exception(exception_139931284812000),
.output_out(output_leds),
.output_out_stb(output_leds_stb),
.output_out_ack(output_leds_ack));
main_12 main_12_139931278184392(
.clk(clk),
.rst(rst),
.exception(exception_139931278184392),
.output_out(output_audio),
.output_out_stb(output_audio_stb),
.output_out_ack(output_audio_ack));
main_13 main_13_139931274909024(
.clk(clk),
.rst(rst),
.exception(exception_139931274909024),
.output_out(output_led_g),
.output_out_stb(output_led_g_stb),
.output_out_ack(output_led_g_ack));
main_14 main_14_139931275225496(
.clk(clk),
.rst(rst),
.exception(exception_139931275225496),
.output_out(output_led_b),
.output_out_stb(output_led_b_stb),
.output_out_ack(output_led_b_ack));
main_15 main_15_139931277018680(
.clk(clk),
.rst(rst),
.exception(exception_139931277018680),
.output_out(output_i2c),
.output_out_stb(output_i2c_stb),
.output_out_ack(output_i2c_ack));
main_16 main_16_139931277927848(
.clk(clk),
.rst(rst),
.exception(exception_139931277927848),
.output_out(output_vga),
.output_out_stb(output_vga_stb),
.output_out_ack(output_vga_ack));
main_17 main_17_139931279974624(
.clk(clk),
.rst(rst),
.exception(exception_139931279974624),
.output_out(output_led_r),
.output_out_stb(output_led_r_stb),
.output_out_ack(output_led_r_ack));
assign exception = exception_139931282298208 || exception_139931279302312 || exception_139931282298568 || exception_139931276022632 || exception_139931284594768 || exception_139931283933808 || exception_139931274793904 || exception_139931280104840 || exception_139931276181376 || exception_139931279234472 || exception_139931282558560 || exception_139931284812000 || exception_139931278184392 || exception_139931274909024 || exception_139931275225496 || exception_139931277018680 || exception_139931277927848 || exception_139931279974624;
endmodule
|
module col_mach #
(
parameter TCQ = 100,
parameter BANK_WIDTH = 3,
parameter BURST_MODE = "8",
parameter COL_WIDTH = 12,
parameter CS_WIDTH = 4,
parameter DATA_BUF_ADDR_WIDTH = 8,
parameter DATA_BUF_OFFSET_WIDTH = 1,
parameter DELAY_WR_DATA_CNTRL = 0,
parameter DQS_WIDTH = 8,
parameter DRAM_TYPE = "DDR3",
parameter EARLY_WR_DATA_ADDR = "OFF",
parameter ECC = "OFF",
parameter MC_ERR_ADDR_WIDTH = 31,
parameter nCK_PER_CLK = 2,
parameter nPHY_WRLAT = 0,
parameter nRD_EN2CNFG_WR = 6,
parameter nWR_EN2CNFG_RD = 4,
parameter nWR_EN2CNFG_WR = 4,
parameter RANK_WIDTH = 2,
parameter ROW_WIDTH = 16
)
(/*AUTOARG*/
// Outputs
dq_busy_data, wr_data_offset, mc_wrdata_en, wr_data_en,
wr_data_addr, inhbt_wr_config, inhbt_rd_config,
rd_rmw, ecc_err_addr, ecc_status_valid, wr_ecc_buf, rd_data_end,
rd_data_addr, rd_data_offset, rd_data_en,
// Inputs
clk, rst, sent_col, col_size, io_config, col_wr_data_buf_addr,
phy_rddata_valid, col_periodic_rd, col_data_buf_addr, col_rmw,
col_rd_wr, col_ra, col_ba, col_row, col_a
);
input clk;
input rst;
input sent_col;
input col_rd_wr;
output reg dq_busy_data = 1'b0;
// The following generates a column command disable based mostly on the type
// of DRAM and the fabric to DRAM CK ratio.
generate
if ((nCK_PER_CLK == 1) && ((BURST_MODE == "8") || (DRAM_TYPE == "DDR3")))
begin : three_bumps
reg [1:0] granted_col_d_r;
wire [1:0] granted_col_d_ns = {sent_col, granted_col_d_r[1]};
always @(posedge clk) granted_col_d_r <= #TCQ granted_col_d_ns;
always @(/*AS*/granted_col_d_r or sent_col)
dq_busy_data = sent_col || |granted_col_d_r;
end
if (((nCK_PER_CLK == 2) && ((BURST_MODE == "8") || (DRAM_TYPE == "DDR3")))
|| ((nCK_PER_CLK == 1) && ((BURST_MODE == "4") || (DRAM_TYPE == "DDR2"))))
begin : one_bump
always @(/*AS*/sent_col) dq_busy_data = sent_col;
end
endgenerate
// This generates a data offset based on fabric clock to DRAM CK ratio and
// the size bit. Note that this is different that the dq_busy_data signal
// generated above.
reg [1:0] offset_r = 2'b0;
reg [1:0] offset_ns = 2'b0;
input col_size;
wire data_end;
generate
if(nCK_PER_CLK == 4) begin : data_valid_4_1
always @ (rst)
if(rst) begin
offset_ns = 2'b0;
offset_r = 2'b0;
end
assign data_end = 1'b1;
end
else begin
if(DATA_BUF_OFFSET_WIDTH == 2) begin : data_valid_1_1
always @(col_size or offset_r or rst or sent_col) begin
if (rst) offset_ns = 2'b0;
else begin
offset_ns = offset_r;
if (sent_col) offset_ns = 2'b1;
else if (|offset_r && (offset_r != {col_size, 1'b1}))
offset_ns = offset_r + 2'b1;
else offset_ns = 2'b0;
end
end
always @(posedge clk) offset_r <= #TCQ offset_ns;
assign data_end = col_size ? (offset_r == 2'b11) : offset_r[0];
end
else begin : data_valid_2_1
always @(col_size or rst or sent_col)
offset_ns[0] = rst ? 1'b0 : sent_col && col_size;
always @(posedge clk) offset_r[0] <= #TCQ offset_ns[0];
assign data_end = col_size ? offset_r[0] : 1'b1;
end
end
endgenerate
reg [DATA_BUF_OFFSET_WIDTH-1:0] offset_r1 = {DATA_BUF_OFFSET_WIDTH{1'b0}};
reg [DATA_BUF_OFFSET_WIDTH-1:0] offset_r2 = {DATA_BUF_OFFSET_WIDTH{1'b0}};
reg col_rd_wr_r1;
reg col_rd_wr_r2;
generate
if ((nPHY_WRLAT == 1) || (DELAY_WR_DATA_CNTRL == 1)) begin : offset_pipe_0
always @(posedge clk) offset_r1 <=
#TCQ offset_r[DATA_BUF_OFFSET_WIDTH-1:0];
always @(posedge clk) col_rd_wr_r1 <= #TCQ col_rd_wr;
end
if(nPHY_WRLAT == 2) begin : offset_pipe_1
always @(posedge clk) offset_r2 <=
#TCQ offset_r1[DATA_BUF_OFFSET_WIDTH-1:0];
always @(posedge clk) col_rd_wr_r2 <= #TCQ col_rd_wr_r1;
end
endgenerate
output wire [DATA_BUF_OFFSET_WIDTH-1:0] wr_data_offset;
assign wr_data_offset = (DELAY_WR_DATA_CNTRL == 1)
? offset_r1[DATA_BUF_OFFSET_WIDTH-1:0]
: (EARLY_WR_DATA_ADDR == "OFF")
? offset_r[DATA_BUF_OFFSET_WIDTH-1:0]
: offset_ns[DATA_BUF_OFFSET_WIDTH-1:0];
input [RANK_WIDTH:0] io_config;
reg sent_col_r1;
reg sent_col_r2;
always @(posedge clk) sent_col_r1 <= #TCQ sent_col;
always @(posedge clk) sent_col_r2 <= #TCQ sent_col_r1;
wire wrdata_en = (nPHY_WRLAT == 0) ?
(sent_col & ~col_rd_wr) || |offset_r :
(nPHY_WRLAT == 1) ?
(sent_col_r1 & ~col_rd_wr_r1) || |offset_r1 :
//(nPHY_WRLAT >= 2) ?
(sent_col_r2 & ~col_rd_wr_r2) || |offset_r2;
output wire [DQS_WIDTH-1:0] mc_wrdata_en;
assign mc_wrdata_en = {DQS_WIDTH{wrdata_en}};
output wire wr_data_en;
assign wr_data_en = (DELAY_WR_DATA_CNTRL == 1)
? ((sent_col_r1 || |offset_r1) && io_config[RANK_WIDTH])
: ((sent_col || |offset_r) && io_config[RANK_WIDTH]);
input [DATA_BUF_ADDR_WIDTH-1:0] col_wr_data_buf_addr;
output wire [DATA_BUF_ADDR_WIDTH-1:0] wr_data_addr;
generate
if (DELAY_WR_DATA_CNTRL == 1) begin : delay_wr_data_cntrl_eq_1
reg [DATA_BUF_ADDR_WIDTH-1:0] col_wr_data_buf_addr_r;
always @(posedge clk) col_wr_data_buf_addr_r <=
#TCQ col_wr_data_buf_addr;
assign wr_data_addr = col_wr_data_buf_addr_r;
end
else begin : delay_wr_data_cntrl_ne_1
assign wr_data_addr = col_wr_data_buf_addr;
end
endgenerate
// CAS-RD to mc_rddata_en
wire read_data_valid = (sent_col || |offset_r) && ~io_config[RANK_WIDTH];
function integer clogb2 (input integer size); // ceiling logb2
begin
size = size - 1;
for (clogb2=1; size>1; clogb2=clogb2+1)
size = size >> 1;
end
endfunction // clogb2
localparam ONE = 1;
localparam nRD_EN2CNFG_WR_LOCAL = nRD_EN2CNFG_WR - 2;
localparam nWR_EN2CNFG_WR_LOCAL = nWR_EN2CNFG_WR - 2;
localparam WR_WAIT_CNT_WIDTH = clogb2(nRD_EN2CNFG_WR_LOCAL + 1);
reg [WR_WAIT_CNT_WIDTH-1:0] cnfg_wr_wait_r;
reg [WR_WAIT_CNT_WIDTH-1:0] cnfg_wr_wait_ns;
always @(/*AS*/cnfg_wr_wait_r or read_data_valid or rst or wrdata_en) begin
if (rst) cnfg_wr_wait_ns = {WR_WAIT_CNT_WIDTH{1'b0}};
else begin
cnfg_wr_wait_ns = cnfg_wr_wait_r;
if (wrdata_en)
cnfg_wr_wait_ns = nWR_EN2CNFG_WR_LOCAL[WR_WAIT_CNT_WIDTH-1:0];
else
if (read_data_valid)
cnfg_wr_wait_ns = nRD_EN2CNFG_WR_LOCAL[WR_WAIT_CNT_WIDTH-1:0];
else
if (|cnfg_wr_wait_r)
cnfg_wr_wait_ns = cnfg_wr_wait_r - ONE[WR_WAIT_CNT_WIDTH-1:0];
end // else: !if(rst)
end
always @(posedge clk) cnfg_wr_wait_r <= #TCQ cnfg_wr_wait_ns;
localparam nWR_EN2CNFG_RD_LOCAL = nWR_EN2CNFG_RD - 2;
localparam RD_WAIT_CNT_WIDTH = clogb2(nWR_EN2CNFG_RD_LOCAL + 1);
reg [RD_WAIT_CNT_WIDTH-1:0] cnfg_rd_wait_r;
reg [RD_WAIT_CNT_WIDTH-1:0] cnfg_rd_wait_ns;
always @(/*AS*/cnfg_rd_wait_r or rst or wrdata_en) begin
if (rst) cnfg_rd_wait_ns = {RD_WAIT_CNT_WIDTH{1'b0}};
else begin
cnfg_rd_wait_ns = cnfg_rd_wait_r;
if (wrdata_en)
cnfg_rd_wait_ns = nWR_EN2CNFG_RD_LOCAL[RD_WAIT_CNT_WIDTH-1:0];
else
if (|cnfg_rd_wait_r)
cnfg_rd_wait_ns = cnfg_rd_wait_r - ONE[RD_WAIT_CNT_WIDTH-1:0];
end
end
always @(posedge clk) cnfg_rd_wait_r <= #TCQ cnfg_rd_wait_ns;
// Finally, generate the inhbit signals. Do it in a way to help timing.
wire inhbt_wr_config_ns = (cnfg_wr_wait_ns != {WR_WAIT_CNT_WIDTH{1'b0}});
reg inhbt_wr_config_r;
always @(posedge clk) inhbt_wr_config_r <= #TCQ inhbt_wr_config_ns;
output wire inhbt_wr_config;
assign inhbt_wr_config = sent_col || wrdata_en || inhbt_wr_config_r;
wire inhbt_rd_config_ns = (cnfg_rd_wait_ns != {RD_WAIT_CNT_WIDTH{1'b0}});
reg inhbt_rd_config_r;
always @(posedge clk) inhbt_rd_config_r <= #TCQ inhbt_rd_config_ns;
output wire inhbt_rd_config;
assign inhbt_rd_config = sent_col || wrdata_en || inhbt_rd_config_r;
// Implement FIFO that records reads as they are sent to the DRAM.
// When phy_rddata_valid is returned some unknown time later, the
// FIFO output is used to control how the data is interpreted.
input phy_rddata_valid;
output wire rd_rmw;
output reg [MC_ERR_ADDR_WIDTH-1:0] ecc_err_addr;
output reg ecc_status_valid;
output reg wr_ecc_buf;
output reg rd_data_end;
output reg [DATA_BUF_ADDR_WIDTH-1:0] rd_data_addr;
output reg [DATA_BUF_OFFSET_WIDTH-1:0] rd_data_offset;
output reg rd_data_en;
input col_periodic_rd;
input [DATA_BUF_ADDR_WIDTH-1:0] col_data_buf_addr;
input col_rmw;
input [RANK_WIDTH-1:0] col_ra;
input [BANK_WIDTH-1:0] col_ba;
input [ROW_WIDTH-1:0] col_row;
input [ROW_WIDTH-1:0] col_a;
wire [11:0] col_a_full = {col_a[13], col_a[11], col_a[9:0]};
wire [COL_WIDTH-1:0] col_a_extracted = col_a_full[COL_WIDTH-1:0];
localparam MC_ERR_LINE_WIDTH = MC_ERR_ADDR_WIDTH-DATA_BUF_OFFSET_WIDTH;
localparam FIFO_WIDTH = 1 /*data_end*/ +
1 /*periodic_rd*/ +
DATA_BUF_ADDR_WIDTH +
DATA_BUF_OFFSET_WIDTH +
((ECC == "OFF") ? 0 : 1+MC_ERR_LINE_WIDTH);
localparam FULL_RAM_CNT = (FIFO_WIDTH/6);
localparam REMAINDER = FIFO_WIDTH % 6;
localparam RAM_CNT = FULL_RAM_CNT + ((REMAINDER == 0 ) ? 0 : 1);
localparam RAM_WIDTH = (RAM_CNT*6);
generate
begin : read_fifo
wire [MC_ERR_LINE_WIDTH:0] ecc_line;
if (CS_WIDTH == 1)
assign ecc_line = {col_rmw, col_ba, col_row, col_a_extracted};
else
assign ecc_line = {col_rmw,
col_ra,
col_ba,
col_row,
col_a_extracted};
wire [FIFO_WIDTH-1:0] real_fifo_data;
if (ECC == "OFF")
assign real_fifo_data = {data_end,
col_periodic_rd,
col_data_buf_addr,
offset_r[DATA_BUF_OFFSET_WIDTH-1:0]};
else
assign real_fifo_data = {data_end,
col_periodic_rd,
col_data_buf_addr,
offset_r[DATA_BUF_OFFSET_WIDTH-1:0],
ecc_line};
wire [RAM_WIDTH-1:0] fifo_in_data;
if (REMAINDER == 0)
assign fifo_in_data = real_fifo_data;
else
assign fifo_in_data = {{6-REMAINDER{1'b0}}, real_fifo_data};
wire [RAM_WIDTH-1:0] fifo_out_data_ns;
reg [4:0] head_r;
wire [4:0] head_ns = rst ? 5'b0 : read_data_valid
? (head_r + 5'b1)
: head_r;
always @(posedge clk) head_r <= #TCQ head_ns;
reg [4:0] tail_r;
wire [4:0] tail_ns = rst ? 5'b0 : phy_rddata_valid
? (tail_r + 5'b1)
: tail_r;
always @(posedge clk) tail_r <= #TCQ tail_ns;
genvar i;
for (i=0; i<RAM_CNT; i=i+1) begin : fifo_ram
RAM32M
#(.INIT_A(64'h0000000000000000),
.INIT_B(64'h0000000000000000),
.INIT_C(64'h0000000000000000),
.INIT_D(64'h0000000000000000)
) RAM32M0 (
.DOA(fifo_out_data_ns[((i*6)+4)+:2]),
.DOB(fifo_out_data_ns[((i*6)+2)+:2]),
.DOC(fifo_out_data_ns[((i*6)+0)+:2]),
.DOD(),
.DIA(fifo_in_data[((i*6)+4)+:2]),
.DIB(fifo_in_data[((i*6)+2)+:2]),
.DIC(fifo_in_data[((i*6)+0)+:2]),
.DID(2'b0),
.ADDRA(tail_ns),
.ADDRB(tail_ns),
.ADDRC(tail_ns),
.ADDRD(head_r),
.WE(1'b1),
.WCLK(clk)
);
end // block: fifo_ram
reg [RAM_WIDTH-1:0] fifo_out_data_r;
always @(posedge clk) fifo_out_data_r <= #TCQ fifo_out_data_ns;
// When ECC is ON, most of the FIFO output is delayed
// by one state.
if (ECC == "OFF") begin
reg periodic_rd;
always @(/*AS*/phy_rddata_valid or fifo_out_data_r) begin
{rd_data_end,
periodic_rd,
rd_data_addr,
rd_data_offset} = fifo_out_data_r[FIFO_WIDTH-1:0];
ecc_err_addr = {MC_ERR_ADDR_WIDTH{1'b0}};
rd_data_en = phy_rddata_valid && ~periodic_rd;
ecc_status_valid = 1'b0;
wr_ecc_buf = 1'b0;
end
assign rd_rmw = 1'b0;
end
else begin
wire rd_data_end_ns;
wire periodic_rd;
wire [DATA_BUF_ADDR_WIDTH-1:0] rd_data_addr_ns;
wire [DATA_BUF_OFFSET_WIDTH-1:0] rd_data_offset_ns;
wire [MC_ERR_ADDR_WIDTH-1:0] ecc_err_addr_ns;
assign {rd_data_end_ns,
periodic_rd,
rd_data_addr_ns,
rd_data_offset_ns,
rd_rmw,
ecc_err_addr_ns[DATA_BUF_OFFSET_WIDTH+:MC_ERR_LINE_WIDTH]} =
{fifo_out_data_r[FIFO_WIDTH-1:0]};
assign ecc_err_addr_ns[0+:DATA_BUF_OFFSET_WIDTH] = rd_data_offset_ns;
always @(posedge clk) rd_data_end <= #TCQ rd_data_end_ns;
always @(posedge clk) rd_data_addr <= #TCQ rd_data_addr_ns;
always @(posedge clk) rd_data_offset <= #TCQ rd_data_offset_ns;
always @(posedge clk) ecc_err_addr <= #TCQ ecc_err_addr_ns;
wire rd_data_en_ns = phy_rddata_valid && ~(periodic_rd || rd_rmw);
always @(posedge clk) rd_data_en <= rd_data_en_ns;
wire ecc_status_valid_ns = phy_rddata_valid && ~periodic_rd;
always @(posedge clk) ecc_status_valid <= #TCQ ecc_status_valid_ns;
wire wr_ecc_buf_ns = phy_rddata_valid && ~periodic_rd && rd_rmw;
always @(posedge clk) wr_ecc_buf <= #TCQ wr_ecc_buf_ns;
end
end
endgenerate
endmodule
|
module or1200_spram_2048x32(
`ifdef OR1200_BIST
// RAM BIST
mbist_si_i, mbist_so_o, mbist_ctrl_i,
`endif
// Generic synchronous single-port RAM interface
clk, rst, ce, we, oe, addr, di, doq
);
//
// Default address and data buses width
//
parameter aw = 11;
parameter dw = 32;
`ifdef OR1200_BIST
//
// RAM BIST
//
input mbist_si_i;
input [`OR1200_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i;
output mbist_so_o;
`endif
//
// Generic synchronous single-port RAM interface
//
input clk; // Clock
input rst; // Reset
input ce; // Chip enable input
input we; // Write enable input
input oe; // Output enable input
input [aw-1:0] addr; // address bus inputs
input [dw-1:0] di; // input data bus
output [dw-1:0] doq; // output data bus
//
// Internal wires and registers
//
`ifdef OR1200_ARTISAN_SSP
`else
`ifdef OR1200_VIRTUALSILICON_SSP
`else
`ifdef OR1200_BIST
assign mbist_so_o = mbist_si_i;
`endif
`endif
`endif
`ifdef OR1200_ARTISAN_SSP
//
// Instantiation of ASIC memory:
//
// Artisan Synchronous Single-Port RAM (ra1sh)
//
`ifdef UNUSED
art_hdsp_2048x32 #(dw, 1<<aw, aw) artisan_ssp(
`else
`ifdef OR1200_BIST
art_hssp_2048x32_bist artisan_ssp(
`else
art_hssp_2048x32 artisan_ssp(
`endif
`endif
`ifdef OR1200_BIST
// RAM BIST
.mbist_si_i(mbist_si_i),
.mbist_so_o(mbist_so_o),
.mbist_ctrl_i(mbist_ctrl_i),
`endif
.CLK(clk),
.CEN(~ce),
.WEN(~we),
.A(addr),
.D(di),
.OEN(~oe),
.Q(doq)
);
`else
`ifdef OR1200_AVANT_ATP
//
// Instantiation of ASIC memory:
//
// Avant! Asynchronous Two-Port RAM
//
avant_atp avant_atp(
.web(~we),
.reb(),
.oeb(~oe),
.rcsb(),
.wcsb(),
.ra(addr),
.wa(addr),
.di(di),
.doq(doq)
);
`else
`ifdef OR1200_VIRAGE_SSP
//
// Instantiation of ASIC memory:
//
// Virage Synchronous 1-port R/W RAM
//
virage_ssp virage_ssp(
.clk(clk),
.adr(addr),
.d(di),
.we(we),
.oe(oe),
.me(ce),
.q(doq)
);
`else
`ifdef OR1200_VIRTUALSILICON_SSP
//
// Instantiation of ASIC memory:
//
// Virtual Silicon Single-Port Synchronous SRAM
//
`ifdef UNUSED
vs_hdsp_2048x32 #(1<<aw, aw-1, dw-1) vs_ssp(
`else
`ifdef OR1200_BIST
vs_hdsp_2048x32_bist vs_ssp(
`else
vs_hdsp_2048x32 vs_ssp(
`endif
`endif
`ifdef OR1200_BIST
// RAM BIST
.mbist_si_i(mbist_si_i),
.mbist_so_o(mbist_so_o),
.mbist_ctrl_i(mbist_ctrl_i),
`endif
.CK(clk),
.ADR(addr),
.DI(di),
.WEN(~we),
.CEN(~ce),
.OEN(~oe),
.DOUT(doq)
);
`else
`ifdef OR1200_XILINX_RAMB4
//
// Instantiation of FPGA memory:
//
// Virtex/Spartan2
//
//
// Block 0
//
RAMB4_S2 ramb4_s2_0(
.CLK(clk),
.RST(rst),
.ADDR(addr),
.DI(di[1:0]),
.EN(ce),
.WE(we),
.DO(doq[1:0])
);
//
// Block 1
//
RAMB4_S2 ramb4_s2_1(
.CLK(clk),
.RST(rst),
.ADDR(addr),
.DI(di[3:2]),
.EN(ce),
.WE(we),
.DO(doq[3:2])
);
//
// Block 2
//
RAMB4_S2 ramb4_s2_2(
.CLK(clk),
.RST(rst),
.ADDR(addr),
.DI(di[5:4]),
.EN(ce),
.WE(we),
.DO(doq[5:4])
);
//
// Block 3
//
RAMB4_S2 ramb4_s2_3(
.CLK(clk),
.RST(rst),
.ADDR(addr),
.DI(di[7:6]),
.EN(ce),
.WE(we),
.DO(doq[7:6])
);
//
// Block 4
//
RAMB4_S2 ramb4_s2_4(
.CLK(clk),
.RST(rst),
.ADDR(addr),
.DI(di[9:8]),
.EN(ce),
.WE(we),
.DO(doq[9:8])
);
//
// Block 5
//
RAMB4_S2 ramb4_s2_5(
.CLK(clk),
.RST(rst),
.ADDR(addr),
.DI(di[11:10]),
.EN(ce),
.WE(we),
.DO(doq[11:10])
);
//
// Block 6
//
RAMB4_S2 ramb4_s2_6(
.CLK(clk),
.RST(rst),
.ADDR(addr),
.DI(di[13:12]),
.EN(ce),
.WE(we),
.DO(doq[13:12])
);
//
// Block 7
//
RAMB4_S2 ramb4_s2_7(
.CLK(clk),
.RST(rst),
.ADDR(addr),
.DI(di[15:14]),
.EN(ce),
.WE(we),
.DO(doq[15:14])
);
//
// Block 8
//
RAMB4_S2 ramb4_s2_8(
.CLK(clk),
.RST(rst),
.ADDR(addr),
.DI(di[17:16]),
.EN(ce),
.WE(we),
.DO(doq[17:16])
);
//
// Block 9
//
RAMB4_S2 ramb4_s2_9(
.CLK(clk),
.RST(rst),
.ADDR(addr),
.DI(di[19:18]),
.EN(ce),
.WE(we),
.DO(doq[19:18])
);
//
// Block 10
//
RAMB4_S2 ramb4_s2_10(
.CLK(clk),
.RST(rst),
.ADDR(addr),
.DI(di[21:20]),
.EN(ce),
.WE(we),
.DO(doq[21:20])
);
//
// Block 11
//
RAMB4_S2 ramb4_s2_11(
.CLK(clk),
.RST(rst),
.ADDR(addr),
.DI(di[23:22]),
.EN(ce),
.WE(we),
.DO(doq[23:22])
);
//
// Block 12
//
RAMB4_S2 ramb4_s2_12(
.CLK(clk),
.RST(rst),
.ADDR(addr),
.DI(di[25:24]),
.EN(ce),
.WE(we),
.DO(doq[25:24])
);
//
// Block 13
//
RAMB4_S2 ramb4_s2_13(
.CLK(clk),
.RST(rst),
.ADDR(addr),
.DI(di[27:26]),
.EN(ce),
.WE(we),
.DO(doq[27:26])
);
//
// Block 14
//
RAMB4_S2 ramb4_s2_14(
.CLK(clk),
.RST(rst),
.ADDR(addr),
.DI(di[29:28]),
.EN(ce),
.WE(we),
.DO(doq[29:28])
);
//
// Block 15
//
RAMB4_S2 ramb4_s2_15(
.CLK(clk),
.RST(rst),
.ADDR(addr),
.DI(di[31:30]),
.EN(ce),
.WE(we),
.DO(doq[31:30])
);
`else
`ifdef OR1200_XILINX_RAMB16
//
// Instantiation of FPGA memory:
//
// Virtex4/Spartan3E
//
// Added By Nir Mor
//
//
// Block 0
//
RAMB16_S9 ramb16_s9_0(
.CLK(clk),
.SSR(rst),
.ADDR(addr),
.DI(di[7:0]),
.DIP(1'b0),
.EN(ce),
.WE(we),
.DO(doq[7:0]),
.DOP()
);
//
// Block 1
//
RAMB16_S9 ramb16_s9_1(
.CLK(clk),
.SSR(rst),
.ADDR(addr),
.DI(di[15:8]),
.DIP(1'b0),
.EN(ce),
.WE(we),
.DO(doq[15:8]),
.DOP()
);
//
// Block 2
//
RAMB16_S9 ramb16_s9_2(
.CLK(clk),
.SSR(rst),
.ADDR(addr),
.DI(di[23:16]),
.DIP(1'b0),
.EN(ce),
.WE(we),
.DO(doq[23:16]),
.DOP()
);
//
// Block 3
//
RAMB16_S9 ramb16_s9_3(
.CLK(clk),
.SSR(rst),
.ADDR(addr),
.DI(di[31:24]),
.DIP(1'b0),
.EN(ce),
.WE(we),
.DO(doq[31:24]),
.DOP()
);
`else
`ifdef OR1200_ALTERA_LPM
//
// Instantiation of FPGA memory:
//
// Altera LPM
//
// Added By Jamil Khatib
//
wire wr;
assign wr = ce & we;
initial $display("Using Altera LPM.");
lpm_ram_dq lpm_ram_dq_component (
.address(addr),
.inclock(clk),
.outclock(clk),
.data(di),
.we(wr),
.q(doq)
);
defparam lpm_ram_dq_component.lpm_width = dw,
lpm_ram_dq_component.lpm_widthad = aw,
lpm_ram_dq_component.lpm_indata = "REGISTERED",
lpm_ram_dq_component.lpm_address_control = "REGISTERED",
lpm_ram_dq_component.lpm_outdata = "UNREGISTERED",
lpm_ram_dq_component.lpm_hint = "USE_EAB=ON";
// examplar attribute lpm_ram_dq_component NOOPT TRUE
`else
//
// Generic single-port synchronous RAM model
//
//
// Generic RAM's registers and wires
//
reg [dw-1:0] mem [(1<<aw)-1:0]; // RAM content
reg [aw-1:0] addr_reg; // RAM address register
//
// Data output drivers
//
assign doq = (oe) ? mem[addr_reg] : {dw{1'b0}};
//
// RAM address register
//
always @(posedge clk or posedge rst)
if (rst)
addr_reg <= #1 {aw{1'b0}};
else if (ce)
addr_reg <= #1 addr;
//
// RAM write
//
always @(posedge clk)
if (ce && we)
mem[addr] <= #1 di;
`endif // !OR1200_ALTERA_LPM
`endif // !OR1200_XILINX_RAMB16
`endif // !OR1200_XILINX_RAMB4
`endif // !OR1200_VIRTUALSILICON_SSP
`endif // !OR1200_VIRAGE_SSP
`endif // !OR1200_AVANT_ATP
`endif // !OR1200_ARTISAN_SSP
endmodule
|
module outputs)
wire [7:0] dout_o; // From uart_ of sasc_top.v
wire empty_o; // From uart_ of sasc_top.v
wire full_o; // From uart_ of sasc_top.v
wire sio_ce; // From baud_ of sasc_brg.v
wire sio_ce_x4; // From baud_ of sasc_brg.v
// End of automatics
wire cmdRd;
wire cmdMem;
reg re_i;
reg we_i;
sasc_top uart_ (// Outputs
.txd_o (uart_tx),
.rts_o (),
// Inputs
.rxd_i (uart_rx),
.cts_i (1'b0),
.rst_n (arst_n),
/*AUTOINST*/
// Outputs
.dout_o (dout_o[7:0]),
.full_o (full_o),
.empty_o (empty_o),
// Inputs
.clk (clk),
.sio_ce (sio_ce),
.sio_ce_x4 (sio_ce_x4),
.din_i (din_i[7:0]),
.re_i (re_i),
.we_i (we_i));
sasc_brg baud_ (/*AUTOINST*/
// Outputs
.sio_ce (sio_ce),
.sio_ce_x4 (sio_ce_x4),
// Inputs
.clk (clk),
.arst_n (arst_n));
always @ (posedge clk or negedge arst_n)
if (~arst_n)
state <= stIdle;
else
case (state)
stIdle : if (~empty_o) state <= stCmd1;
stCmd1 : if (~empty_o) state <= stCmd2;
stCmd2 : if (cmdRd) state <= stRd; // read
else if (~empty_o) state <= stData1; // write
stData1: if (cmdRd) state <= stData2; // read
else if (~empty_o) state <= stData2; // write
stData2: if (cmdRd) state <= stData3; // read
else if (~empty_o) state <= stData3; // write
stData3: if (cmdRd) state <= stData4; // read done
else if (~empty_o) state <= stData4; // write
stData4: if (cmdRd) state <= stIdle;
else state <= stWr; // write commit
stWr: state <= stIdle;
stRd: state <= stData1;
endcase // case(state)
// --------------- Command Word Capture ----------------- //
always @ (posedge clk or negedge arst_n)
if (~arst_n) cmd <= 0;
else
begin
if (state==stIdle) cmd[15:8] <= dout_o[7:0];
if (state==stCmd1) cmd[7:0] <= dout_o[7:0];
end
assign cmdRd = ~cmd[15];
assign cmdMem = cmd[14];
assign uart_addr = cmd[13:0];
// --------------- Write Command ----------------- //
always @ (posedge clk or negedge arst_n)
if (~arst_n)
uart_dout <= 0;
else
begin
if (state==stCmd2 & ~cmdRd) uart_dout[31:24] <= dout_o[7:0];
if (state==stData1 & ~cmdRd) uart_dout[23:16] <= dout_o[7:0];
if (state==stData2 & ~cmdRd) uart_dout[15:8] <= dout_o[7:0];
if (state==stData3 & ~cmdRd) uart_dout[7:0] <= dout_o[7:0];
end
always @ (/*AS*/cmdRd or empty_o or state)
case (state)
stIdle : re_i = ~empty_o;
stCmd1 : re_i = ~empty_o;
stCmd2 : re_i = ~empty_o & ~cmdRd;
stData1: re_i = ~empty_o & ~cmdRd;
stData2: re_i = ~empty_o & ~cmdRd;
stData3: re_i = ~empty_o & ~cmdRd;
default: re_i = 0;
endcase // case(state)
assign uart_mem_we = (state==stWr) & cmdMem;
assign reg_we = (state==stWr) & ~cmdMem;
// --------------- Read Command ----------------- //
always @ (/*AS*/cmdMem or state or uart_mem_i or uart_reg_i)
case (state)
stData2: din_i[7:0] = cmdMem ? uart_mem_i[23:16] : uart_reg_i[23:16];
stData3: din_i[7:0] = cmdMem ? uart_mem_i[15:8] : uart_reg_i[15:8];
stData4: din_i[7:0] = cmdMem ? uart_mem_i[7:0] : uart_reg_i[7:0];
default: din_i[7:0] = cmdMem ? 0 : 0;
endcase // case(state)
always @ (/*AS*/cmdRd or state)
case (state)
stData1: we_i = cmdRd;
stData2: we_i = cmdRd;
stData3: we_i = cmdRd;
stData4: we_i = cmdRd;
default: we_i = 0;
endcase // case(state)
assign uart_mem_re = (state==stRd);
endmodule
|
module test;
reg [3:0] s;
reg i15, i14, i13, i12, i11, i10, i9, i8, i7, i6, i5, i4, i3, i2, i1, i0;
wire z;
mux_16to1 mux(
.s (s ),
.i15(i15),
.i14(i14),
.i13(i13),
.i12(i12),
.i11(i11),
.i10(i10),
.i9 (i9 ),
.i8 (i8 ),
.i7 (i7 ),
.i6 (i6 ),
.i5 (i5 ),
.i4 (i4 ),
.i3 (i3 ),
.i2 (i2 ),
.i1 (i1 ),
.i0 (i0 ),
.z (z ));
initial begin
$monitor($time, ": %b %b %b %b %b %b %b %b %b %b %b %b %b %b %b %b | %b %b %b %b | %b",
i15, i14, i13, i12,i11,i10,i9, i8,i7, i6, i5, i4, i3, i2, i1, i0,s[3], s[2],s[1],s[0],z);
#5 i15 = 0; i14 = 0; i13 = 0; i12 = 0; i11 = 0; i10 = 0; i9 = 0; i8 = 0;
i7 = 0; i6 = 0; i5 = 0; i4 = 0; i3 = 0; i2 = 0; i1 = 0; i0 = 0;
s[3] = 0; s[2] = 0; s[1] = 0; s[0] = 0;
#5 i4 = 1; i5 = 1; i2 = 1; s[1] = 1; // 010 select i2
#5 s[0] = 1; // 0011 select i3
#5 s[2] = 1; // 0111 select i7
#5 i7 = 0;
#5 s[1] = 0; // 0101 select i5
#5 i15 = 1; s[1] = 1; s[3] = 1; //1111 select i15
#5 i10 = 1; s[0] = 0; s[2] = 0; // 1010 select i10
end
// 0000 0
// 0001 1
// 0010 2
// 0011 3
// 0100 4
// 0101 5
// 0110 6
// 0111 7
// 1000 8
// 1001 9
// 1010 10
// 1011 11
// 1100 12
// 1101 13
// 1110 14
// 1111 15
endmodule
|
module fpga_core #
(
parameter TARGET = "XILINX"
)
(
/*
* Clock: 390.625 MHz
* Synchronous reset
*/
input wire clk,
input wire rst,
/*
* GPIO
*/
output wire [1:0] user_led_g,
output wire user_led_r,
output wire [1:0] front_led,
input wire [1:0] user_sw,
/*
* Ethernet: QSFP28
*/
input wire qsfp_0_tx_clk_0,
input wire qsfp_0_tx_rst_0,
output wire [63:0] qsfp_0_txd_0,
output wire [7:0] qsfp_0_txc_0,
input wire qsfp_0_rx_clk_0,
input wire qsfp_0_rx_rst_0,
input wire [63:0] qsfp_0_rxd_0,
input wire [7:0] qsfp_0_rxc_0,
input wire qsfp_0_tx_clk_1,
input wire qsfp_0_tx_rst_1,
output wire [63:0] qsfp_0_txd_1,
output wire [7:0] qsfp_0_txc_1,
input wire qsfp_0_rx_clk_1,
input wire qsfp_0_rx_rst_1,
input wire [63:0] qsfp_0_rxd_1,
input wire [7:0] qsfp_0_rxc_1,
input wire qsfp_0_tx_clk_2,
input wire qsfp_0_tx_rst_2,
output wire [63:0] qsfp_0_txd_2,
output wire [7:0] qsfp_0_txc_2,
input wire qsfp_0_rx_clk_2,
input wire qsfp_0_rx_rst_2,
input wire [63:0] qsfp_0_rxd_2,
input wire [7:0] qsfp_0_rxc_2,
input wire qsfp_0_tx_clk_3,
input wire qsfp_0_tx_rst_3,
output wire [63:0] qsfp_0_txd_3,
output wire [7:0] qsfp_0_txc_3,
input wire qsfp_0_rx_clk_3,
input wire qsfp_0_rx_rst_3,
input wire [63:0] qsfp_0_rxd_3,
input wire [7:0] qsfp_0_rxc_3,
input wire qsfp_1_tx_clk_0,
input wire qsfp_1_tx_rst_0,
output wire [63:0] qsfp_1_txd_0,
output wire [7:0] qsfp_1_txc_0,
input wire qsfp_1_rx_clk_0,
input wire qsfp_1_rx_rst_0,
input wire [63:0] qsfp_1_rxd_0,
input wire [7:0] qsfp_1_rxc_0,
input wire qsfp_1_tx_clk_1,
input wire qsfp_1_tx_rst_1,
output wire [63:0] qsfp_1_txd_1,
output wire [7:0] qsfp_1_txc_1,
input wire qsfp_1_rx_clk_1,
input wire qsfp_1_rx_rst_1,
input wire [63:0] qsfp_1_rxd_1,
input wire [7:0] qsfp_1_rxc_1,
input wire qsfp_1_tx_clk_2,
input wire qsfp_1_tx_rst_2,
output wire [63:0] qsfp_1_txd_2,
output wire [7:0] qsfp_1_txc_2,
input wire qsfp_1_rx_clk_2,
input wire qsfp_1_rx_rst_2,
input wire [63:0] qsfp_1_rxd_2,
input wire [7:0] qsfp_1_rxc_2,
input wire qsfp_1_tx_clk_3,
input wire qsfp_1_tx_rst_3,
output wire [63:0] qsfp_1_txd_3,
output wire [7:0] qsfp_1_txc_3,
input wire qsfp_1_rx_clk_3,
input wire qsfp_1_rx_rst_3,
input wire [63:0] qsfp_1_rxd_3,
input wire [7:0] qsfp_1_rxc_3
);
// AXI between MAC and Ethernet modules
wire [63:0] rx_axis_tdata;
wire [7:0] rx_axis_tkeep;
wire rx_axis_tvalid;
wire rx_axis_tready;
wire rx_axis_tlast;
wire rx_axis_tuser;
wire [63:0] tx_axis_tdata;
wire [7:0] tx_axis_tkeep;
wire tx_axis_tvalid;
wire tx_axis_tready;
wire tx_axis_tlast;
wire tx_axis_tuser;
// Ethernet frame between Ethernet modules and UDP stack
wire rx_eth_hdr_ready;
wire rx_eth_hdr_valid;
wire [47:0] rx_eth_dest_mac;
wire [47:0] rx_eth_src_mac;
wire [15:0] rx_eth_type;
wire [63:0] rx_eth_payload_axis_tdata;
wire [7:0] rx_eth_payload_axis_tkeep;
wire rx_eth_payload_axis_tvalid;
wire rx_eth_payload_axis_tready;
wire rx_eth_payload_axis_tlast;
wire rx_eth_payload_axis_tuser;
wire tx_eth_hdr_ready;
wire tx_eth_hdr_valid;
wire [47:0] tx_eth_dest_mac;
wire [47:0] tx_eth_src_mac;
wire [15:0] tx_eth_type;
wire [63:0] tx_eth_payload_axis_tdata;
wire [7:0] tx_eth_payload_axis_tkeep;
wire tx_eth_payload_axis_tvalid;
wire tx_eth_payload_axis_tready;
wire tx_eth_payload_axis_tlast;
wire tx_eth_payload_axis_tuser;
// IP frame connections
wire rx_ip_hdr_valid;
wire rx_ip_hdr_ready;
wire [47:0] rx_ip_eth_dest_mac;
wire [47:0] rx_ip_eth_src_mac;
wire [15:0] rx_ip_eth_type;
wire [3:0] rx_ip_version;
wire [3:0] rx_ip_ihl;
wire [5:0] rx_ip_dscp;
wire [1:0] rx_ip_ecn;
wire [15:0] rx_ip_length;
wire [15:0] rx_ip_identification;
wire [2:0] rx_ip_flags;
wire [12:0] rx_ip_fragment_offset;
wire [7:0] rx_ip_ttl;
wire [7:0] rx_ip_protocol;
wire [15:0] rx_ip_header_checksum;
wire [31:0] rx_ip_source_ip;
wire [31:0] rx_ip_dest_ip;
wire [63:0] rx_ip_payload_axis_tdata;
wire [7:0] rx_ip_payload_axis_tkeep;
wire rx_ip_payload_axis_tvalid;
wire rx_ip_payload_axis_tready;
wire rx_ip_payload_axis_tlast;
wire rx_ip_payload_axis_tuser;
wire tx_ip_hdr_valid;
wire tx_ip_hdr_ready;
wire [5:0] tx_ip_dscp;
wire [1:0] tx_ip_ecn;
wire [15:0] tx_ip_length;
wire [7:0] tx_ip_ttl;
wire [7:0] tx_ip_protocol;
wire [31:0] tx_ip_source_ip;
wire [31:0] tx_ip_dest_ip;
wire [63:0] tx_ip_payload_axis_tdata;
wire [7:0] tx_ip_payload_axis_tkeep;
wire tx_ip_payload_axis_tvalid;
wire tx_ip_payload_axis_tready;
wire tx_ip_payload_axis_tlast;
wire tx_ip_payload_axis_tuser;
// UDP frame connections
wire rx_udp_hdr_valid;
wire rx_udp_hdr_ready;
wire [47:0] rx_udp_eth_dest_mac;
wire [47:0] rx_udp_eth_src_mac;
wire [15:0] rx_udp_eth_type;
wire [3:0] rx_udp_ip_version;
wire [3:0] rx_udp_ip_ihl;
wire [5:0] rx_udp_ip_dscp;
wire [1:0] rx_udp_ip_ecn;
wire [15:0] rx_udp_ip_length;
wire [15:0] rx_udp_ip_identification;
wire [2:0] rx_udp_ip_flags;
wire [12:0] rx_udp_ip_fragment_offset;
wire [7:0] rx_udp_ip_ttl;
wire [7:0] rx_udp_ip_protocol;
wire [15:0] rx_udp_ip_header_checksum;
wire [31:0] rx_udp_ip_source_ip;
wire [31:0] rx_udp_ip_dest_ip;
wire [15:0] rx_udp_source_port;
wire [15:0] rx_udp_dest_port;
wire [15:0] rx_udp_length;
wire [15:0] rx_udp_checksum;
wire [63:0] rx_udp_payload_axis_tdata;
wire [7:0] rx_udp_payload_axis_tkeep;
wire rx_udp_payload_axis_tvalid;
wire rx_udp_payload_axis_tready;
wire rx_udp_payload_axis_tlast;
wire rx_udp_payload_axis_tuser;
wire tx_udp_hdr_valid;
wire tx_udp_hdr_ready;
wire [5:0] tx_udp_ip_dscp;
wire [1:0] tx_udp_ip_ecn;
wire [7:0] tx_udp_ip_ttl;
wire [31:0] tx_udp_ip_source_ip;
wire [31:0] tx_udp_ip_dest_ip;
wire [15:0] tx_udp_source_port;
wire [15:0] tx_udp_dest_port;
wire [15:0] tx_udp_length;
wire [15:0] tx_udp_checksum;
wire [63:0] tx_udp_payload_axis_tdata;
wire [7:0] tx_udp_payload_axis_tkeep;
wire tx_udp_payload_axis_tvalid;
wire tx_udp_payload_axis_tready;
wire tx_udp_payload_axis_tlast;
wire tx_udp_payload_axis_tuser;
wire [63:0] rx_fifo_udp_payload_axis_tdata;
wire [7:0] rx_fifo_udp_payload_axis_tkeep;
wire rx_fifo_udp_payload_axis_tvalid;
wire rx_fifo_udp_payload_axis_tready;
wire rx_fifo_udp_payload_axis_tlast;
wire rx_fifo_udp_payload_axis_tuser;
wire [63:0] tx_fifo_udp_payload_axis_tdata;
wire [7:0] tx_fifo_udp_payload_axis_tkeep;
wire tx_fifo_udp_payload_axis_tvalid;
wire tx_fifo_udp_payload_axis_tready;
wire tx_fifo_udp_payload_axis_tlast;
wire tx_fifo_udp_payload_axis_tuser;
// Configuration
wire [47:0] local_mac = 48'h02_00_00_00_00_00;
wire [31:0] local_ip = {8'd192, 8'd168, 8'd1, 8'd128};
wire [31:0] gateway_ip = {8'd192, 8'd168, 8'd1, 8'd1};
wire [31:0] subnet_mask = {8'd255, 8'd255, 8'd255, 8'd0};
// IP ports not used
assign rx_ip_hdr_ready = 1;
assign rx_ip_payload_axis_tready = 1;
assign tx_ip_hdr_valid = 0;
assign tx_ip_dscp = 0;
assign tx_ip_ecn = 0;
assign tx_ip_length = 0;
assign tx_ip_ttl = 0;
assign tx_ip_protocol = 0;
assign tx_ip_source_ip = 0;
assign tx_ip_dest_ip = 0;
assign tx_ip_payload_axis_tdata = 0;
assign tx_ip_payload_axis_tkeep = 0;
assign tx_ip_payload_axis_tvalid = 0;
assign tx_ip_payload_axis_tlast = 0;
assign tx_ip_payload_axis_tuser = 0;
// Loop back UDP
wire match_cond = rx_udp_dest_port == 1234;
wire no_match = !match_cond;
reg match_cond_reg = 0;
reg no_match_reg = 0;
always @(posedge clk) begin
if (rst) begin
match_cond_reg <= 0;
no_match_reg <= 0;
end else begin
if (rx_udp_payload_axis_tvalid) begin
if ((!match_cond_reg && !no_match_reg) ||
(rx_udp_payload_axis_tvalid && rx_udp_payload_axis_tready && rx_udp_payload_axis_tlast)) begin
match_cond_reg <= match_cond;
no_match_reg <= no_match;
end
end else begin
match_cond_reg <= 0;
no_match_reg <= 0;
end
end
end
assign tx_udp_hdr_valid = rx_udp_hdr_valid && match_cond;
assign rx_udp_hdr_ready = (tx_eth_hdr_ready && match_cond) || no_match;
assign tx_udp_ip_dscp = 0;
assign tx_udp_ip_ecn = 0;
assign tx_udp_ip_ttl = 64;
assign tx_udp_ip_source_ip = local_ip;
assign tx_udp_ip_dest_ip = rx_udp_ip_source_ip;
assign tx_udp_source_port = rx_udp_dest_port;
assign tx_udp_dest_port = rx_udp_source_port;
assign tx_udp_length = rx_udp_length;
assign tx_udp_checksum = 0;
assign tx_udp_payload_axis_tdata = tx_fifo_udp_payload_axis_tdata;
assign tx_udp_payload_axis_tkeep = tx_fifo_udp_payload_axis_tkeep;
assign tx_udp_payload_axis_tvalid = tx_fifo_udp_payload_axis_tvalid;
assign tx_fifo_udp_payload_axis_tready = tx_udp_payload_axis_tready;
assign tx_udp_payload_axis_tlast = tx_fifo_udp_payload_axis_tlast;
assign tx_udp_payload_axis_tuser = tx_fifo_udp_payload_axis_tuser;
assign rx_fifo_udp_payload_axis_tdata = rx_udp_payload_axis_tdata;
assign rx_fifo_udp_payload_axis_tkeep = rx_udp_payload_axis_tkeep;
assign rx_fifo_udp_payload_axis_tvalid = rx_udp_payload_axis_tvalid && match_cond_reg;
assign rx_udp_payload_axis_tready = (rx_fifo_udp_payload_axis_tready && match_cond_reg) || no_match_reg;
assign rx_fifo_udp_payload_axis_tlast = rx_udp_payload_axis_tlast;
assign rx_fifo_udp_payload_axis_tuser = rx_udp_payload_axis_tuser;
// Place first payload byte onto LEDs
reg valid_last = 0;
reg [7:0] led_reg = 0;
always @(posedge clk) begin
if (rst) begin
led_reg <= 0;
end else begin
valid_last <= tx_udp_payload_axis_tvalid;
if (tx_udp_payload_axis_tvalid && !valid_last) begin
led_reg <= tx_udp_payload_axis_tdata;
end
end
end
assign user_led_g = ~led_reg[1:0];
assign user_led_r = 1'b1;
assign front_led = 2'b00;
assign phy_reset_n = !rst;
assign qsfp_0_txd_1 = 64'h0707070707070707;
assign qsfp_0_txc_1 = 8'hff;
assign qsfp_0_txd_2 = 64'h0707070707070707;
assign qsfp_0_txc_2 = 8'hff;
assign qsfp_0_txd_3 = 64'h0707070707070707;
assign qsfp_0_txc_3 = 8'hff;
assign qsfp_1_txd_0 = 64'h0707070707070707;
assign qsfp_1_txc_0 = 8'hff;
assign qsfp_1_txd_1 = 64'h0707070707070707;
assign qsfp_1_txc_1 = 8'hff;
assign qsfp_1_txd_2 = 64'h0707070707070707;
assign qsfp_1_txc_2 = 8'hff;
assign qsfp_1_txd_3 = 64'h0707070707070707;
assign qsfp_1_txc_3 = 8'hff;
eth_mac_10g_fifo #(
.ENABLE_PADDING(1),
.ENABLE_DIC(1),
.MIN_FRAME_LENGTH(64),
.TX_FIFO_DEPTH(4096),
.TX_FRAME_FIFO(1),
.RX_FIFO_DEPTH(4096),
.RX_FRAME_FIFO(1)
)
eth_mac_10g_fifo_inst (
.rx_clk(qsfp_0_rx_clk_0),
.rx_rst(qsfp_0_rx_rst_0),
.tx_clk(qsfp_0_tx_clk_0),
.tx_rst(qsfp_0_tx_rst_0),
.logic_clk(clk),
.logic_rst(rst),
.tx_axis_tdata(tx_axis_tdata),
.tx_axis_tkeep(tx_axis_tkeep),
.tx_axis_tvalid(tx_axis_tvalid),
.tx_axis_tready(tx_axis_tready),
.tx_axis_tlast(tx_axis_tlast),
.tx_axis_tuser(tx_axis_tuser),
.rx_axis_tdata(rx_axis_tdata),
.rx_axis_tkeep(rx_axis_tkeep),
.rx_axis_tvalid(rx_axis_tvalid),
.rx_axis_tready(rx_axis_tready),
.rx_axis_tlast(rx_axis_tlast),
.rx_axis_tuser(rx_axis_tuser),
.xgmii_rxd(qsfp_0_rxd_0),
.xgmii_rxc(qsfp_0_rxc_0),
.xgmii_txd(qsfp_0_txd_0),
.xgmii_txc(qsfp_0_txc_0),
.tx_fifo_overflow(),
.tx_fifo_bad_frame(),
.tx_fifo_good_frame(),
.rx_error_bad_frame(),
.rx_error_bad_fcs(),
.rx_fifo_overflow(),
.rx_fifo_bad_frame(),
.rx_fifo_good_frame(),
.ifg_delay(8'd12)
);
eth_axis_rx #(
.DATA_WIDTH(64)
)
eth_axis_rx_inst (
.clk(clk),
.rst(rst),
// AXI input
.s_axis_tdata(rx_axis_tdata),
.s_axis_tkeep(rx_axis_tkeep),
.s_axis_tvalid(rx_axis_tvalid),
.s_axis_tready(rx_axis_tready),
.s_axis_tlast(rx_axis_tlast),
.s_axis_tuser(rx_axis_tuser),
// Ethernet frame output
.m_eth_hdr_valid(rx_eth_hdr_valid),
.m_eth_hdr_ready(rx_eth_hdr_ready),
.m_eth_dest_mac(rx_eth_dest_mac),
.m_eth_src_mac(rx_eth_src_mac),
.m_eth_type(rx_eth_type),
.m_eth_payload_axis_tdata(rx_eth_payload_axis_tdata),
.m_eth_payload_axis_tkeep(rx_eth_payload_axis_tkeep),
.m_eth_payload_axis_tvalid(rx_eth_payload_axis_tvalid),
.m_eth_payload_axis_tready(rx_eth_payload_axis_tready),
.m_eth_payload_axis_tlast(rx_eth_payload_axis_tlast),
.m_eth_payload_axis_tuser(rx_eth_payload_axis_tuser),
// Status signals
.busy(),
.error_header_early_termination()
);
eth_axis_tx #(
.DATA_WIDTH(64)
)
eth_axis_tx_inst (
.clk(clk),
.rst(rst),
// Ethernet frame input
.s_eth_hdr_valid(tx_eth_hdr_valid),
.s_eth_hdr_ready(tx_eth_hdr_ready),
.s_eth_dest_mac(tx_eth_dest_mac),
.s_eth_src_mac(tx_eth_src_mac),
.s_eth_type(tx_eth_type),
.s_eth_payload_axis_tdata(tx_eth_payload_axis_tdata),
.s_eth_payload_axis_tkeep(tx_eth_payload_axis_tkeep),
.s_eth_payload_axis_tvalid(tx_eth_payload_axis_tvalid),
.s_eth_payload_axis_tready(tx_eth_payload_axis_tready),
.s_eth_payload_axis_tlast(tx_eth_payload_axis_tlast),
.s_eth_payload_axis_tuser(tx_eth_payload_axis_tuser),
// AXI output
.m_axis_tdata(tx_axis_tdata),
.m_axis_tkeep(tx_axis_tkeep),
.m_axis_tvalid(tx_axis_tvalid),
.m_axis_tready(tx_axis_tready),
.m_axis_tlast(tx_axis_tlast),
.m_axis_tuser(tx_axis_tuser),
// Status signals
.busy()
);
udp_complete_64
udp_complete_inst (
.clk(clk),
.rst(rst),
// Ethernet frame input
.s_eth_hdr_valid(rx_eth_hdr_valid),
.s_eth_hdr_ready(rx_eth_hdr_ready),
.s_eth_dest_mac(rx_eth_dest_mac),
.s_eth_src_mac(rx_eth_src_mac),
.s_eth_type(rx_eth_type),
.s_eth_payload_axis_tdata(rx_eth_payload_axis_tdata),
.s_eth_payload_axis_tkeep(rx_eth_payload_axis_tkeep),
.s_eth_payload_axis_tvalid(rx_eth_payload_axis_tvalid),
.s_eth_payload_axis_tready(rx_eth_payload_axis_tready),
.s_eth_payload_axis_tlast(rx_eth_payload_axis_tlast),
.s_eth_payload_axis_tuser(rx_eth_payload_axis_tuser),
// Ethernet frame output
.m_eth_hdr_valid(tx_eth_hdr_valid),
.m_eth_hdr_ready(tx_eth_hdr_ready),
.m_eth_dest_mac(tx_eth_dest_mac),
.m_eth_src_mac(tx_eth_src_mac),
.m_eth_type(tx_eth_type),
.m_eth_payload_axis_tdata(tx_eth_payload_axis_tdata),
.m_eth_payload_axis_tkeep(tx_eth_payload_axis_tkeep),
.m_eth_payload_axis_tvalid(tx_eth_payload_axis_tvalid),
.m_eth_payload_axis_tready(tx_eth_payload_axis_tready),
.m_eth_payload_axis_tlast(tx_eth_payload_axis_tlast),
.m_eth_payload_axis_tuser(tx_eth_payload_axis_tuser),
// IP frame input
.s_ip_hdr_valid(tx_ip_hdr_valid),
.s_ip_hdr_ready(tx_ip_hdr_ready),
.s_ip_dscp(tx_ip_dscp),
.s_ip_ecn(tx_ip_ecn),
.s_ip_length(tx_ip_length),
.s_ip_ttl(tx_ip_ttl),
.s_ip_protocol(tx_ip_protocol),
.s_ip_source_ip(tx_ip_source_ip),
.s_ip_dest_ip(tx_ip_dest_ip),
.s_ip_payload_axis_tdata(tx_ip_payload_axis_tdata),
.s_ip_payload_axis_tkeep(tx_ip_payload_axis_tkeep),
.s_ip_payload_axis_tvalid(tx_ip_payload_axis_tvalid),
.s_ip_payload_axis_tready(tx_ip_payload_axis_tready),
.s_ip_payload_axis_tlast(tx_ip_payload_axis_tlast),
.s_ip_payload_axis_tuser(tx_ip_payload_axis_tuser),
// IP frame output
.m_ip_hdr_valid(rx_ip_hdr_valid),
.m_ip_hdr_ready(rx_ip_hdr_ready),
.m_ip_eth_dest_mac(rx_ip_eth_dest_mac),
.m_ip_eth_src_mac(rx_ip_eth_src_mac),
.m_ip_eth_type(rx_ip_eth_type),
.m_ip_version(rx_ip_version),
.m_ip_ihl(rx_ip_ihl),
.m_ip_dscp(rx_ip_dscp),
.m_ip_ecn(rx_ip_ecn),
.m_ip_length(rx_ip_length),
.m_ip_identification(rx_ip_identification),
.m_ip_flags(rx_ip_flags),
.m_ip_fragment_offset(rx_ip_fragment_offset),
.m_ip_ttl(rx_ip_ttl),
.m_ip_protocol(rx_ip_protocol),
.m_ip_header_checksum(rx_ip_header_checksum),
.m_ip_source_ip(rx_ip_source_ip),
.m_ip_dest_ip(rx_ip_dest_ip),
.m_ip_payload_axis_tdata(rx_ip_payload_axis_tdata),
.m_ip_payload_axis_tkeep(rx_ip_payload_axis_tkeep),
.m_ip_payload_axis_tvalid(rx_ip_payload_axis_tvalid),
.m_ip_payload_axis_tready(rx_ip_payload_axis_tready),
.m_ip_payload_axis_tlast(rx_ip_payload_axis_tlast),
.m_ip_payload_axis_tuser(rx_ip_payload_axis_tuser),
// UDP frame input
.s_udp_hdr_valid(tx_udp_hdr_valid),
.s_udp_hdr_ready(tx_udp_hdr_ready),
.s_udp_ip_dscp(tx_udp_ip_dscp),
.s_udp_ip_ecn(tx_udp_ip_ecn),
.s_udp_ip_ttl(tx_udp_ip_ttl),
.s_udp_ip_source_ip(tx_udp_ip_source_ip),
.s_udp_ip_dest_ip(tx_udp_ip_dest_ip),
.s_udp_source_port(tx_udp_source_port),
.s_udp_dest_port(tx_udp_dest_port),
.s_udp_length(tx_udp_length),
.s_udp_checksum(tx_udp_checksum),
.s_udp_payload_axis_tdata(tx_udp_payload_axis_tdata),
.s_udp_payload_axis_tkeep(tx_udp_payload_axis_tkeep),
.s_udp_payload_axis_tvalid(tx_udp_payload_axis_tvalid),
.s_udp_payload_axis_tready(tx_udp_payload_axis_tready),
.s_udp_payload_axis_tlast(tx_udp_payload_axis_tlast),
.s_udp_payload_axis_tuser(tx_udp_payload_axis_tuser),
// UDP frame output
.m_udp_hdr_valid(rx_udp_hdr_valid),
.m_udp_hdr_ready(rx_udp_hdr_ready),
.m_udp_eth_dest_mac(rx_udp_eth_dest_mac),
.m_udp_eth_src_mac(rx_udp_eth_src_mac),
.m_udp_eth_type(rx_udp_eth_type),
.m_udp_ip_version(rx_udp_ip_version),
.m_udp_ip_ihl(rx_udp_ip_ihl),
.m_udp_ip_dscp(rx_udp_ip_dscp),
.m_udp_ip_ecn(rx_udp_ip_ecn),
.m_udp_ip_length(rx_udp_ip_length),
.m_udp_ip_identification(rx_udp_ip_identification),
.m_udp_ip_flags(rx_udp_ip_flags),
.m_udp_ip_fragment_offset(rx_udp_ip_fragment_offset),
.m_udp_ip_ttl(rx_udp_ip_ttl),
.m_udp_ip_protocol(rx_udp_ip_protocol),
.m_udp_ip_header_checksum(rx_udp_ip_header_checksum),
.m_udp_ip_source_ip(rx_udp_ip_source_ip),
.m_udp_ip_dest_ip(rx_udp_ip_dest_ip),
.m_udp_source_port(rx_udp_source_port),
.m_udp_dest_port(rx_udp_dest_port),
.m_udp_length(rx_udp_length),
.m_udp_checksum(rx_udp_checksum),
.m_udp_payload_axis_tdata(rx_udp_payload_axis_tdata),
.m_udp_payload_axis_tkeep(rx_udp_payload_axis_tkeep),
.m_udp_payload_axis_tvalid(rx_udp_payload_axis_tvalid),
.m_udp_payload_axis_tready(rx_udp_payload_axis_tready),
.m_udp_payload_axis_tlast(rx_udp_payload_axis_tlast),
.m_udp_payload_axis_tuser(rx_udp_payload_axis_tuser),
// Status signals
.ip_rx_busy(),
.ip_tx_busy(),
.udp_rx_busy(),
.udp_tx_busy(),
.ip_rx_error_header_early_termination(),
.ip_rx_error_payload_early_termination(),
.ip_rx_error_invalid_header(),
.ip_rx_error_invalid_checksum(),
.ip_tx_error_payload_early_termination(),
.ip_tx_error_arp_failed(),
.udp_rx_error_header_early_termination(),
.udp_rx_error_payload_early_termination(),
.udp_tx_error_payload_early_termination(),
// Configuration
.local_mac(local_mac),
.local_ip(local_ip),
.gateway_ip(gateway_ip),
.subnet_mask(subnet_mask),
.clear_arp_cache(1'b0)
);
axis_fifo #(
.DEPTH(8192),
.DATA_WIDTH(64),
.KEEP_ENABLE(1),
.KEEP_WIDTH(8),
.ID_ENABLE(0),
.DEST_ENABLE(0),
.USER_ENABLE(1),
.USER_WIDTH(1),
.FRAME_FIFO(0)
)
udp_payload_fifo (
.clk(clk),
.rst(rst),
// AXI input
.s_axis_tdata(rx_fifo_udp_payload_axis_tdata),
.s_axis_tkeep(rx_fifo_udp_payload_axis_tkeep),
.s_axis_tvalid(rx_fifo_udp_payload_axis_tvalid),
.s_axis_tready(rx_fifo_udp_payload_axis_tready),
.s_axis_tlast(rx_fifo_udp_payload_axis_tlast),
.s_axis_tid(0),
.s_axis_tdest(0),
.s_axis_tuser(rx_fifo_udp_payload_axis_tuser),
// AXI output
.m_axis_tdata(tx_fifo_udp_payload_axis_tdata),
.m_axis_tkeep(tx_fifo_udp_payload_axis_tkeep),
.m_axis_tvalid(tx_fifo_udp_payload_axis_tvalid),
.m_axis_tready(tx_fifo_udp_payload_axis_tready),
.m_axis_tlast(tx_fifo_udp_payload_axis_tlast),
.m_axis_tid(),
.m_axis_tdest(),
.m_axis_tuser(tx_fifo_udp_payload_axis_tuser),
// Status
.status_overflow(),
.status_bad_frame(),
.status_good_frame()
);
endmodule
|
module dmac_request_generator (
input req_aclk,
input req_aresetn,
output [C_ID_WIDTH-1:0] request_id,
input [C_ID_WIDTH-1:0] response_id,
input req_valid,
output reg req_ready,
input [C_BURSTS_PER_TRANSFER_WIDTH-1:0] req_burst_count,
input enable,
input pause,
output eot
);
parameter C_ID_WIDTH = 3;
parameter C_BURSTS_PER_TRANSFER_WIDTH = 17;
`include "inc_id.h"
/*
* Here we only need to count the number of bursts, which means we can ignore
* the lower bits of the byte count. The last last burst may not contain the
* maximum number of bytes, but the address_generator and data_mover will take
* care that only the requested ammount of bytes is transfered.
*/
reg [C_BURSTS_PER_TRANSFER_WIDTH-1:0] burst_count = 'h00;
reg [C_ID_WIDTH-1:0] id;
wire [C_ID_WIDTH-1:0] id_next = inc_id(id);
assign eot = burst_count == 'h00;
assign request_id = id;
always @(posedge req_aclk)
begin
if (req_aresetn == 1'b0) begin
burst_count <= 'h00;
id <= 'h0;
req_ready <= 1'b1;
end else if (enable == 1'b0) begin
req_ready <= 1'b1;
end else begin
if (req_ready) begin
if (req_valid && enable) begin
burst_count <= req_burst_count;
req_ready <= 1'b0;
end
end else if (response_id != id_next && ~pause) begin
if (eot)
req_ready <= 1'b1;
burst_count <= burst_count - 1'b1;
id <= id_next;
end
end
end
endmodule
|
module sky130_fd_sc_hd__a31o_2 (
X ,
A1 ,
A2 ,
A3 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__a31o base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
|
module sky130_fd_sc_hd__a31o_2 (
X ,
A1,
A2,
A3,
B1
);
output X ;
input A1;
input A2;
input A3;
input B1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__a31o base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1)
);
endmodule
|
module sky130_fd_sc_hs__o221a (
VPWR,
VGND,
X ,
A1 ,
A2 ,
B1 ,
B2 ,
C1
);
// Module ports
input VPWR;
input VGND;
output X ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input C1 ;
// Local signals
wire B2 or0_out ;
wire B2 or1_out ;
wire and0_out_X ;
wire u_vpwr_vgnd0_out_X;
// Name Output Other arguments
or or0 (or0_out , B2, B1 );
or or1 (or1_out , A2, A1 );
and and0 (and0_out_X , or0_out, or1_out, C1 );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_X, and0_out_X, VPWR, VGND);
buf buf0 (X , u_vpwr_vgnd0_out_X );
endmodule
|
module nios_mem_if_ddr2_emif_0_p0_addr_cmd_datapath(
clk,
reset_n,
afi_address,
afi_bank,
afi_cs_n,
afi_cke,
afi_odt,
afi_ras_n,
afi_cas_n,
afi_we_n,
phy_ddio_address,
phy_ddio_bank,
phy_ddio_cs_n,
phy_ddio_cke,
phy_ddio_we_n,
phy_ddio_ras_n,
phy_ddio_cas_n,
phy_ddio_odt
);
parameter MEM_ADDRESS_WIDTH = "";
parameter MEM_BANK_WIDTH = "";
parameter MEM_CHIP_SELECT_WIDTH = "";
parameter MEM_CLK_EN_WIDTH = "";
parameter MEM_ODT_WIDTH = "";
parameter MEM_DM_WIDTH = "";
parameter MEM_CONTROL_WIDTH = "";
parameter MEM_DQ_WIDTH = "";
parameter MEM_READ_DQS_WIDTH = "";
parameter MEM_WRITE_DQS_WIDTH = "";
parameter AFI_ADDRESS_WIDTH = "";
parameter AFI_BANK_WIDTH = "";
parameter AFI_CHIP_SELECT_WIDTH = "";
parameter AFI_CLK_EN_WIDTH = "";
parameter AFI_ODT_WIDTH = "";
parameter AFI_DATA_MASK_WIDTH = "";
parameter AFI_CONTROL_WIDTH = "";
parameter AFI_DATA_WIDTH = "";
parameter NUM_AC_FR_CYCLE_SHIFTS = "";
localparam RATE_MULT = 2;
input reset_n;
input clk;
input [AFI_ADDRESS_WIDTH-1:0] afi_address;
input [AFI_BANK_WIDTH-1:0] afi_bank;
input [AFI_CHIP_SELECT_WIDTH-1:0] afi_cs_n;
input [AFI_CLK_EN_WIDTH-1:0] afi_cke;
input [AFI_ODT_WIDTH-1:0] afi_odt;
input [AFI_CONTROL_WIDTH-1:0] afi_ras_n;
input [AFI_CONTROL_WIDTH-1:0] afi_cas_n;
input [AFI_CONTROL_WIDTH-1:0] afi_we_n;
output [AFI_ADDRESS_WIDTH-1:0] phy_ddio_address;
output [AFI_BANK_WIDTH-1:0] phy_ddio_bank;
output [AFI_CHIP_SELECT_WIDTH-1:0] phy_ddio_cs_n;
output [AFI_CLK_EN_WIDTH-1:0] phy_ddio_cke;
output [AFI_ODT_WIDTH-1:0] phy_ddio_odt;
output [AFI_CONTROL_WIDTH-1:0] phy_ddio_ras_n;
output [AFI_CONTROL_WIDTH-1:0] phy_ddio_cas_n;
output [AFI_CONTROL_WIDTH-1:0] phy_ddio_we_n;
wire [AFI_ADDRESS_WIDTH-1:0] afi_address_r = afi_address;
wire [AFI_BANK_WIDTH-1:0] afi_bank_r = afi_bank;
wire [AFI_CHIP_SELECT_WIDTH-1:0] afi_cs_n_r = afi_cs_n;
wire [AFI_CLK_EN_WIDTH-1:0] afi_cke_r = afi_cke;
wire [AFI_ODT_WIDTH-1:0] afi_odt_r = afi_odt;
wire [AFI_CONTROL_WIDTH-1:0] afi_ras_n_r = afi_ras_n;
wire [AFI_CONTROL_WIDTH-1:0] afi_cas_n_r = afi_cas_n;
wire [AFI_CONTROL_WIDTH-1:0] afi_we_n_r = afi_we_n;
wire [1:0] shift_fr_cycle =
(NUM_AC_FR_CYCLE_SHIFTS == 0) ? 2'b00 : (
(NUM_AC_FR_CYCLE_SHIFTS == 1) ? 2'b01 : (
(NUM_AC_FR_CYCLE_SHIFTS == 2) ? 2'b10 : (
2'b11 )));
nios_mem_if_ddr2_emif_0_p0_fr_cycle_shifter uaddr_cmd_shift_address(
.clk (clk),
.reset_n (reset_n),
.shift_by (shift_fr_cycle),
.datain (afi_address_r),
.dataout (phy_ddio_address)
);
defparam uaddr_cmd_shift_address.DATA_WIDTH = MEM_ADDRESS_WIDTH;
defparam uaddr_cmd_shift_address.REG_POST_RESET_HIGH = "false";
nios_mem_if_ddr2_emif_0_p0_fr_cycle_shifter uaddr_cmd_shift_bank(
.clk (clk),
.reset_n (reset_n),
.shift_by (shift_fr_cycle),
.datain (afi_bank_r),
.dataout (phy_ddio_bank)
);
defparam uaddr_cmd_shift_bank.DATA_WIDTH = MEM_BANK_WIDTH;
defparam uaddr_cmd_shift_bank.REG_POST_RESET_HIGH = "false";
nios_mem_if_ddr2_emif_0_p0_fr_cycle_shifter uaddr_cmd_shift_cke(
.clk (clk),
.reset_n (reset_n),
.shift_by (shift_fr_cycle),
.datain (afi_cke_r),
.dataout (phy_ddio_cke)
);
defparam uaddr_cmd_shift_cke.DATA_WIDTH = MEM_CLK_EN_WIDTH;
defparam uaddr_cmd_shift_cke.REG_POST_RESET_HIGH = "false";
nios_mem_if_ddr2_emif_0_p0_fr_cycle_shifter uaddr_cmd_shift_cs_n(
.clk (clk),
.reset_n (reset_n),
.shift_by (shift_fr_cycle),
.datain (afi_cs_n_r),
.dataout (phy_ddio_cs_n)
);
defparam uaddr_cmd_shift_cs_n.DATA_WIDTH = MEM_CHIP_SELECT_WIDTH;
defparam uaddr_cmd_shift_cs_n.REG_POST_RESET_HIGH = "true";
nios_mem_if_ddr2_emif_0_p0_fr_cycle_shifter uaddr_cmd_shift_odt(
.clk (clk),
.reset_n (reset_n),
.shift_by (shift_fr_cycle),
.datain (afi_odt_r),
.dataout (phy_ddio_odt)
);
defparam uaddr_cmd_shift_odt.DATA_WIDTH = MEM_ODT_WIDTH;
defparam uaddr_cmd_shift_odt.REG_POST_RESET_HIGH = "false";
nios_mem_if_ddr2_emif_0_p0_fr_cycle_shifter uaddr_cmd_shift_ras_n(
.clk (clk),
.reset_n (reset_n),
.shift_by (shift_fr_cycle),
.datain (afi_ras_n_r),
.dataout (phy_ddio_ras_n)
);
defparam uaddr_cmd_shift_ras_n.DATA_WIDTH = MEM_CONTROL_WIDTH;
defparam uaddr_cmd_shift_ras_n.REG_POST_RESET_HIGH = "true";
nios_mem_if_ddr2_emif_0_p0_fr_cycle_shifter uaddr_cmd_shift_cas_n(
.clk (clk),
.reset_n (reset_n),
.shift_by (shift_fr_cycle),
.datain (afi_cas_n_r),
.dataout (phy_ddio_cas_n)
);
defparam uaddr_cmd_shift_cas_n.DATA_WIDTH = MEM_CONTROL_WIDTH;
defparam uaddr_cmd_shift_cas_n.REG_POST_RESET_HIGH = "true";
nios_mem_if_ddr2_emif_0_p0_fr_cycle_shifter uaddr_cmd_shift_we_n(
.clk (clk),
.reset_n (reset_n),
.shift_by (shift_fr_cycle),
.datain (afi_we_n_r),
.dataout (phy_ddio_we_n)
);
defparam uaddr_cmd_shift_we_n.DATA_WIDTH = MEM_CONTROL_WIDTH;
defparam uaddr_cmd_shift_we_n.REG_POST_RESET_HIGH = "true";
endmodule
|
module sky130_fd_sc_hd__o311a (
//# {{data|Data Signals}}
input A1,
input A2,
input A3,
input B1,
input C1,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
|
module Board_Nexys4DDR (nreset,
clk100Mhz,
extInt,
leds,
rgbLeds,
segments_a,
segments_b,
segments_c,
segments_d,
segments_e,
segments_f,
segments_g,
dot,
selector,
pmodA,
sSwitches,
pButtons,
tck,
tms,
tdi,
tdo,
rx,
tx);
// Input ports
input nreset;
input clk100Mhz;
input [0:0] extInt;
input [15:0] sSwitches;
input [4:0] pButtons;
input tck;
input tms;
input tdi;
input rx;
// Output ports
output [15:0] leds;
output [5:0] rgbLeds;
output tdo;
output tx;
output segments_a;
output segments_b;
output segments_c;
output segments_d;
output segments_e;
output segments_f;
output segments_g;
output dot;
output [7:0] selector;
// Bidirectional port
inout [7:0] pmodA;
// Internal reset
wire reset;
// Clock generation
wire boardClk;
wire boardClkLocked;
// Internal wiring
wire [7:0] pmodA_read;
wire [7:0] pmodA_write;
wire [7:0] pmodA_writeEnable;
// Instantiate a PLL/MMCM (makes a 80Mhz clock)
PLL makeClk (.clkIn (clk100Mhz),
.clkOut (boardClk),
.isLocked (boardClkLocked));
// Instantiate the J1SoC core generated by Spinal
J1Nexys4X core (.reset (reset),
.boardClk (boardClk),
.boardClkLocked (boardClkLocked),
.extInt (extInt),
.leds (leds),
.rgbLeds (rgbLeds),
.segments_a (segments_a),
.segments_b (segments_b),
.segments_c (segments_c),
.segments_d (segments_d),
.segments_e (segments_e),
.segments_f (segments_f),
.segments_g (segments_g),
.dot (dot),
.selector (selector),
.pmodA_read (pmodA_read),
.pmodA_write (pmodA_write),
.pmodA_writeEnable (pmodA_writeEnable),
.sSwitches (sSwitches),
.pButtons (pButtons),
.tck (tck),
.tms (tms),
.tdi (tdi),
.tdo (tdo),
.rx (rx),
.tx (tx));
// Make the reset high active
assign reset = !nreset;
// Connect the pmodA read port
assign pmodA_read = pmodA;
// Generate the write port and equip it with tristate functionality
genvar i;
generate
for (i = 0; i < 8; i = i + 1) begin
assign pmodA[i] = pmodA_writeEnable[i] ? pmodA_write[i] : 1'bZ;
end
endgenerate
endmodule
|
module sky130_fd_sc_lp__o2111a (
//# {{data|Data Signals}}
input A1,
input A2,
input B1,
input C1,
input D1,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
|
module sram_ctrl (
input clk,
input rst_n,
input clk_proc,
input wr_en,
input rd_en,
input [31:0] wr_data,
input [20:0] addr,
output reg [31:0] rd_data,
output sram_ub_n,
output sram_lb_n,
output reg sram_ce_n,
output reg sram_we_n,
output reg sram_oe_n,
output reg [19:0] sram_addr,
output reg [15:0] sram_wr_data,
input [15:0] sram_rd_data
);
parameter ST_IDLE = 0;
parameter ST_WRITE_0 = 1;
parameter ST_WRITE_1 = 2;
parameter ST_READ_0 = 3;
parameter ST_READ_1 = 4;
parameter ST_READ_2 = 5;
reg [2:0] state;
reg [2:0] next_state;
reg [2:0] counter;
reg [31:0] rd_data_reg;
wire [20:0] addr_plus2;
reg wr_data_dly;
reg rd_data_dly;
reg wr_detc;
//wire rd_detc;
reg clk_proc_pulse;
reg clk_proc_dly;
//wire [31:0] rd_data_concat;
assign sram_ub_n = 1'b0;
assign sram_lb_n = 1'b0;
assign addr_plus2 = addr+2;
//assign rd_data_concat = {sram_rd_data,rd_data_reg[15:0]};
always@(posedge clk, negedge rst_n)begin
if(!rst_n)begin
rd_data <= 0;
end
else begin
if(state == ST_IDLE)begin
rd_data <= rd_data_reg;
end
end
end
always@(posedge clk, negedge rst_n)begin
if(!rst_n)begin
wr_data_dly <= 1'b0;
clk_proc_dly <= 1'b0;
wr_detc <= 1'b0;
clk_proc_pulse <= 1'b0;
end
else begin
wr_data_dly <= wr_en;
wr_detc <= wr_en & !wr_data_dly;
clk_proc_dly <= clk_proc;
clk_proc_pulse <= clk_proc & !clk_proc_dly;
end
end
always@(posedge clk, negedge rst_n)begin
if(!rst_n)begin
rd_data_reg <= 32'd0;
sram_ce_n = 1'b0;
sram_we_n = 1'b0;
sram_oe_n = 1'b1;
sram_wr_data = 0;
sram_addr = 0;
end
else begin
case(state)
ST_IDLE: begin
if(wr_detc)begin //write
sram_ce_n <= 1'b0;
sram_we_n <= 1'b0;
sram_oe_n <= 1'b1;
sram_wr_data <= wr_data[15:0];
sram_addr <= addr[20:1];
end
else if (rd_en && clk_proc_pulse) begin//read
sram_ce_n <= 1'b0;
sram_we_n <= 1'b1;
sram_oe_n <= 1'b0;
sram_addr <= addr[20:1];
end
else begin
sram_ce_n <= 1'b1;
sram_we_n <= 1'b1;
sram_oe_n <= 1'b1;
sram_addr <= 20'd0;
sram_wr_data <= 16'd0;
end
end
ST_WRITE_0: begin
sram_ce_n <= 1'b1;
sram_we_n <= 1'b1;
sram_oe_n <= 1'b1;
sram_wr_data <= 0;
sram_addr <= 0;
end
ST_WRITE_1: begin
sram_ce_n <= 1'b0;
sram_we_n <= 1'b0;
sram_oe_n <= 1'b1;
sram_wr_data <= wr_data[31:16];
sram_addr <= addr_plus2[20:1];
end
ST_READ_0: begin
sram_ce_n <= 1'b1;
sram_we_n <= 1'b1;
sram_oe_n <= 1'b0;
sram_addr <= 0;
end
ST_READ_1: begin
sram_ce_n <= 1'b0;
sram_we_n <= 1'b1;
sram_oe_n <= 1'b0;
sram_addr <= addr_plus2[20:1];
rd_data_reg[15:0] <= sram_rd_data;
end
ST_READ_2: begin
sram_ce_n <= 1'b1;
sram_we_n <= 1'b1;
sram_oe_n <= 1'b0;
sram_addr <= addr_plus2[20:1];
rd_data_reg[31:16] <= sram_rd_data;
end
default: begin
sram_ce_n <= 1'b1;
sram_we_n <= 1'b1;
sram_oe_n <= 1'b1;
rd_data_reg <= rd_data_reg;
end
endcase
end
end
always@(posedge clk, negedge rst_n)begin
if(!rst_n)begin
state <= ST_IDLE;
end
else begin
state <= next_state;
end
end
always@(*)begin
case (state)
ST_IDLE: begin
if(wr_detc)
next_state = ST_WRITE_0;
else if(rd_en && clk_proc_pulse)
next_state = ST_READ_0;
else
next_state = ST_IDLE;
end
ST_WRITE_0: begin
next_state = ST_WRITE_1;
end
ST_WRITE_1: begin
next_state = ST_IDLE;
end
ST_READ_0: begin
next_state = ST_READ_1;
end
ST_READ_1: begin
next_state = ST_READ_2;
end
ST_READ_2: begin
next_state = ST_IDLE;
end
default:begin
next_state = ST_IDLE;
end
endcase
end
endmodule
|
module sky130_fd_sc_lp__o21ai (
//# {{data|Data Signals}}
input A1,
input A2,
input B1,
output Y
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
|
module CLS_PWM_DutyCycle_Timer
#(
parameter CLK_RATE_HZ = 50000000, // Hz
parameter DUTY_RATE_HZ = 1000, // Hz
parameter DUTY_PERCENT = 50 // Cycle On-time %
)
(
// Input Signals
input PWM_INTERVAL_TICK,
// Output Signals
output reg PWM_OUT,
// System Signals
input CLK
);
// Include Standard Functions header file (needed for bit_index())
`include "StdFunctions.vh"
// Initial register settings
initial
begin
PWM_OUT = 1'b0;
end
//!! Add Implementation Here !!
localparam PWM_INV_TICKS = CLK_RATE_HZ / DUTY_RATE_HZ;
localparam PWM_REG_WIDTH = bit_index(PWM_INV_TICKS);
// Compute the PWM Duty Cycle Counter Parameters
localparam integer PDC_OFF_TICKS = PWM_INV_TICKS * (100.0-DUTY_PERCENT) / 100;
localparam [PWM_REG_WIDTH:0] PDC_LOADVAL = {1'b1, {PWM_REG_WIDTH{1'b0}}} - PDC_OFF_TICKS[PWM_REG_WIDTH:0];
reg [PWM_REG_WIDTH:0] pdc_count_reg;
// Initialize Registers
initial
begin
pdc_count_reg = PDC_LOADVAL;
end
// PWM Duty Cycle Counter
always @(posedge CLK)
begin
if (PWM_INTERVAL_TICK)
pdc_count_reg <= PDC_LOADVAL;
else
pdc_count_reg <= pdc_count_reg + 1'b1;
end
// PWM Output Register
always @(posedge CLK)
begin
PWM_OUT <= pdc_count_reg[PWM_REG_WIDTH];
end
endmodule
|
module sky130_fd_sc_ls__sdfbbn (
//# {{data|Data Signals}}
input D ,
output Q ,
output Q_N ,
//# {{control|Control Signals}}
input RESET_B,
input SET_B ,
//# {{scanchain|Scan Chain}}
input SCD ,
input SCE ,
//# {{clocks|Clocking}}
input CLK_N
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
|
module sky130_fd_sc_ls__sdfrtn (
Q ,
CLK_N ,
D ,
SCD ,
SCE ,
RESET_B
);
output Q ;
input CLK_N ;
input D ;
input SCD ;
input SCE ;
input RESET_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
|
module mem(
input wire clk_i, // clock
output reg kpu_wait_o, // Stop kpu execution if needed
input wire [`N-1:0] i_addr_i, // instruction memory address
output reg [`N-1:0] i_data_o, // instruction data output
input wire [`N-1:0] d_addr_i, // data memory address
input wire [3:0] d_sel_i, // data byte select
input wire [`N-1:0] d_data_i, // data input
output reg [`N-1:0] d_data_o, // data output
input wire [`N-1:0] d_gp_i, // general purpose input
output reg [`N-1:0] d_gp_o, // general purpose output
input wire [`N-1:0] io_int_num_i, // interrupt number input
output reg int_ctrl_rst_o, // rst int ctrl line
// Wishbone handler lines
output reg wb_ready_o,
output reg [31:0] wb_command_o = 0,
output reg [31:0] wb_addr_o = 0,
output reg [31:0] wb_data_o = 0,
output reg [27:0] wb_data_count_o = 0,
input wire [31:0] wb_status_i,
input wire [31:0] wb_data_i,
input wire [27:0] wb_data_count_i,
input wire wb_o_en_i,
// External SRAM interface
output wire [`SRAM_ADDR_W-1:0] sram_addr_o,
inout wire [`SRAM_DATA_W-1:0] sram_data_io,
output wire sram_cs_o,
output wire sram_we_o,
output wire sram_oe_o,
output wire sram_hb_o,
output wire sram_lb_o
);
reg [`N-1:0] ram [0:`RAM_SIZE - 1] /* synthesis syn_ramstyle=no_rw_check */;
reg [`N-1:0] rom [0:`ROM_SIZE - 1] /* synthesis syn_ramstyle=no_rw_check */;
reg [3:0] wb_interface_state;
reg wb_write_start = 1'b0;
reg wb_read_start = 1'b0;
reg [1:0] wb_byte_count_read, wb_data_count_tmp;
reg [31:0] wb_data_write, wb_reg_write, wb_reg_read;
reg wb_was_read, wb_readed_data_ready;
reg [31:0] wb_readed_data;
wire kcache_wait;
// WB write states
localparam WB_IDLE = 0;
localparam WB_READ_ONGOING = 1;
localparam WB_WRITE_ONGOING = 2;
localparam WB_READ_WAIT = 3;
localparam WB_WRITE_WAIT = 4;
initial
begin
`ifdef ROM_IMAGE
$readmemh(`ROM_IMAGE, rom);
`else
$readmemh("rom/rom.hex", rom);
`endif
d_gp_o = `N'h0;
kpu_wait_o = `N'h0;
wb_interface_state = 3'b0;
wb_ready_o = 1'b0;
end // initial begin
kcache kcache_i(
.clk_i(clk_i),
.wait_o(kcache_wait),
.flush_i(1'b0), // TODO to be populated with correct mem mapped reg
.i_addr_i(0),
.i_data_o(),
.d_addr_i(0),
.d_sel_wr_i(4'b0),
.d_data_i(0),
.d_data_o(),
// SRAM wires
.sram_addr_o(sram_addr_o),
.sram_data_io(sram_data_io),
.sram_cs_o(sram_cs_o),
.sram_we_o(sram_we_o),
.sram_oe_o(sram_oe_o),
.sram_hb_o(sram_hb_o),
.sram_lb_o(sram_lb_o)
);
always @(ram[i_addr_i] or i_addr_i) begin
if ((i_addr_i << 2) & `ROM_ADDR)
i_data_o = rom[i_addr_i & ~(`ROM_ADDR >> 2)];
else
i_data_o = ram[i_addr_i];
end
always @(*)
kpu_wait_o = wb_interface_state != WB_IDLE ||
wb_write_start || wb_read_start || kcache_wait;
// read
always @(ram[d_addr_i] or d_addr_i or d_gp_i or d_sel_i
or io_int_num_i or wb_interface_state or wb_readed_data
or wb_readed_data_ready) begin
wb_read_start = 1'b0;
wb_byte_count_read = 2'd3;
wb_reg_read = 32'b0;
d_data_o = `N'h0;
if (wb_readed_data_ready)
d_data_o = wb_readed_data;
else if (d_sel_i == 4'b0000)
case (d_addr_i << 2)
`IO_INT_NUM_MAP: begin // Raised IO interrupt number
d_data_o = io_int_num_i;
end
`GP_IN_MAP: begin // General purpose input read
d_data_o = d_gp_i;
end
`UART_CONTROL_REG_MAP: begin
if (wb_interface_state == WB_IDLE) begin
wb_read_start = 1'b1;
wb_reg_read = `UART_REG_CONTROL;
end
end
`UART_STATUS_REG_MAP: begin
if (wb_interface_state == WB_IDLE) begin
wb_read_start = 1'b1;
wb_reg_read = `UART_REG_STATUS;
end
end
`UART_PRESCALER_REG_MAP: begin
if (wb_interface_state == WB_IDLE) begin
wb_read_start = 1'b1;
wb_reg_read = `UART_REG_PRESCALER;
end
end
`UART_CLOCK_DIV_REG_MAP: begin
if (wb_interface_state == WB_IDLE) begin
wb_read_start = 1'b1;
wb_reg_read = `UART_REG_CLOCK_DIV;
end
end
`UART_WRITE_COUNT_REG_MAP: begin
if (wb_interface_state == WB_IDLE) begin
wb_read_start = 1'b1;
wb_reg_read = `UART_REG_WRITE_COUNT;
end
end
`UART_WRITE_REG_MAP: begin
if (wb_interface_state == WB_IDLE) begin
wb_read_start = 1'b1;
wb_reg_read = `UART_REG_WRITE;
end
end
`UART_READ_COUNT_REG_MAP: begin
if (wb_interface_state == WB_IDLE) begin
wb_read_start = 1'b1;
wb_reg_read = `UART_REG_READ_COUNT;
end
end
`UART_READ_REG_MAP: begin
if (wb_interface_state == WB_IDLE) begin
wb_byte_count_read = 2'd1;
wb_read_start = 1'b1;
wb_reg_read = `UART_REG_READ;
end
end
default: begin // Normal memory read
if ((d_addr_i << 2) & `ROM_ADDR)
d_data_o = rom[d_addr_i & ~(`ROM_ADDR >> 2)];
else
d_data_o = ram[d_addr_i];
end
endcase
end
// write
always @(posedge clk_i) begin
wb_write_start <= #1 1'b0;
casex (d_addr_i << 2)
`GP_OUT_MAP: begin // General purpose output write
if (d_sel_i[0])
d_gp_o[7:0] <= #1 d_data_i[7:0];
if (d_sel_i[1])
d_gp_o[15:8] <= #1 d_data_i[15:8];
if (d_sel_i[2])
d_gp_o[23:16] <= #1 d_data_i[23:16];
if (d_sel_i[3])
d_gp_o[31:24] <= #1 d_data_i[31:24];
end
`UART_CONTROL_REG_MAP: begin
// Start wishbone write procedure
if (d_sel_i) begin
if (wb_interface_state == WB_IDLE) begin
wb_write_start <= #1 1'b1;
wb_data_write <= #1 d_data_i;
wb_reg_write <= #1 `UART_REG_CONTROL;
end
else begin
wb_write_start <= #1 1'b0;
end
end
end
`UART_CLOCK_DIV_REG_MAP: begin
// Start wishbone write procedure
if (d_sel_i) begin
if (wb_interface_state == WB_IDLE) begin
wb_write_start <= #1 1'b1;
wb_data_write <= #1 d_data_i;
wb_reg_write <= #1 `UART_REG_CLOCK_DIV;
end
else begin
wb_write_start <= #1 1'b0;
end
end
end
`UART_WRITE_REG_MAP: begin
// Start wishbone write procedure
if (d_sel_i) begin
if (wb_interface_state == WB_IDLE) begin
wb_write_start <= #1 1'b1;
wb_data_write <= #1 (1 << 16) | (d_data_i[7:0] << 8);
wb_reg_write <= #1 `UART_REG_WRITE;
end
else begin
wb_write_start <= #1 1'b0;
end
end
end
default: begin // Normal memory write
if (d_sel_i[0])
ram[d_addr_i][7:0] <= #1 d_data_i[7:0];
if (d_sel_i[1])
ram[d_addr_i][15:8] <= #1 d_data_i[15:8];
if (d_sel_i[2])
ram[d_addr_i][23:16] <= #1 d_data_i[23:16];
if (d_sel_i[3])
ram[d_addr_i][31:24] <= #1 d_data_i[31:24];
end
endcase // case (wb_interface_state)
end
////////////////////////////////
// WISHBONE READ/WRITE //
////////////////////////////////
always @(posedge clk_i) begin
case (wb_interface_state )
WB_IDLE: begin
wb_readed_data_ready <= #1 1'b0;
if (wb_write_start) begin
wb_interface_state <= #1 WB_WRITE_ONGOING;
wb_command_o <= #1 `COMMAND_WRITE;
wb_addr_o <= #1 wb_reg_write;
wb_data_o <= #1 wb_data_write;
wb_data_count_o <= #1 28'h0;
wb_ready_o <= #1 1'b1;
end
else if (wb_read_start) begin
wb_interface_state <= #1 WB_READ_ONGOING;
wb_command_o <= #1 `COMMAND_READ;
wb_addr_o <= #1 wb_reg_read;
wb_data_count_o <= #1 28'h0;
wb_ready_o <= #1 1'b1;
wb_data_count_tmp <= #1 wb_byte_count_read;
end
end
WB_READ_ONGOING: begin
if (wb_status_i == ~wb_command_o &&
(wb_data_count_i == 28'h0)) begin
wb_ready_o <= #1 1'b0;
wb_interface_state <= #1 WB_READ_WAIT;
end
end
WB_WRITE_ONGOING: begin
if (wb_status_i == ~wb_command_o) begin
wb_ready_o <= #1 1'b0;
wb_interface_state <= #1 WB_WRITE_WAIT;
end
end
WB_READ_WAIT: begin
if (wb_o_en_i) begin
wb_ready_o <= #1 1'b0;
wb_interface_state <= #1 WB_IDLE;
wb_readed_data_ready <= #1 1'b1;
if (wb_data_count_tmp == 2'd1)
wb_readed_data <= #1 {24'b0, wb_data_i[31:24]};
else
wb_readed_data <= #1 wb_data_i;
end
end
WB_WRITE_WAIT: begin
if (wb_o_en_i) begin
wb_ready_o <= #1 1'b0;
wb_interface_state <= #1 WB_IDLE;
end
end
endcase
end
// Reset interrupt controller
always @(posedge clk_i) begin
if (d_addr_i << 2 == `IO_INT_NUM_MAP && d_sel_i != 4'b0000)
int_ctrl_rst_o <= 1'b1;
else
int_ctrl_rst_o <= 1'b0;
end
endmodule
|
module sky130_fd_sc_ms__dlxbn_1 (
Q ,
Q_N ,
D ,
GATE_N,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
output Q_N ;
input D ;
input GATE_N;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
sky130_fd_sc_ms__dlxbn base (
.Q(Q),
.Q_N(Q_N),
.D(D),
.GATE_N(GATE_N),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
|
module sky130_fd_sc_ms__dlxbn_1 (
Q ,
Q_N ,
D ,
GATE_N
);
output Q ;
output Q_N ;
input D ;
input GATE_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__dlxbn base (
.Q(Q),
.Q_N(Q_N),
.D(D),
.GATE_N(GATE_N)
);
endmodule
|
module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outreadylatency_check ( .error(1'b1) );
end
endgenerate
nios_mem_if_ddr2_emif_0_s0_mm_interconnect_0_avalon_st_adapter_error_adapter_0 error_adapter_0 (
.clk (in_clk_0_clk), // clk.clk
.reset_n (~in_rst_0_reset), // reset.reset_n
.in_data (in_0_data), // in.data
.in_valid (in_0_valid), // .valid
.in_ready (in_0_ready), // .ready
.out_data (out_0_data), // out.data
.out_valid (out_0_valid), // .valid
.out_ready (out_0_ready), // .ready
.out_error (out_0_error) // .error
);
endmodule
|
module edgedetect (
input iCLK ,
input iRST ,
input iSIG ,
output wire oRE ,
output wire oFE ,
output wire oRFE
);
parameter registered = "FALSE";
reg delay;
wire re;
wire fe;
wire rfe;
always @(posedge iCLK)
begin
if (iRST)
begin
delay <= 1'b0;
end
else
begin
delay <= iSIG;
end
end
// Edge detect logic
assign re = (iSIG && !delay) ? 1'b1 : 1'b0;
assign fe = (!iSIG && delay) ? 1'b1 : 1'b0;
assign rfe = ((iSIG && !delay) || (!iSIG && delay)) ? 1'b1 : 1'b0;
// Register edge detect pulses
reg re_reg, fe_reg, rfe_reg;
always @(posedge iCLK)
begin
if (iRST)
begin
re_reg <= 1'b0;
fe_reg <= 1'b0;
rfe_reg <= 1'b0;
end
else
begin
re_reg <= re;
fe_reg <= fe;
rfe_reg <= rfe;
end
end
// MUX either the combination or registered edge detect pulses to the outputs
assign oRE = (registered == "TRUE") ? re_reg : re ;
assign oFE = (registered == "TRUE") ? fe_reg : fe ;
assign oRFE = (registered == "TRUE") ? rfe_reg : rfe;
endmodule
|
module FIFO_image_filter_img_2_rows_V_shiftReg (
clk,
data,
ce,
a,
q);
parameter DATA_WIDTH = 32'd12;
parameter ADDR_WIDTH = 32'd2;
parameter DEPTH = 32'd3;
input clk;
input [DATA_WIDTH-1:0] data;
input ce;
input [ADDR_WIDTH-1:0] a;
output [DATA_WIDTH-1:0] q;
reg[DATA_WIDTH-1:0] SRL_SIG [0:DEPTH-1];
integer i;
always @ (posedge clk)
begin
if (ce)
begin
for (i=0;i<DEPTH-1;i=i+1)
SRL_SIG[i+1] <= SRL_SIG[i];
SRL_SIG[0] <= data;
end
end
assign q = SRL_SIG[a];
endmodule
|
module FIFO_image_filter_img_2_rows_V (
clk,
reset,
if_empty_n,
if_read_ce,
if_read,
if_dout,
if_full_n,
if_write_ce,
if_write,
if_din);
parameter MEM_STYLE = "shiftreg";
parameter DATA_WIDTH = 32'd12;
parameter ADDR_WIDTH = 32'd2;
parameter DEPTH = 32'd3;
input clk;
input reset;
output if_empty_n;
input if_read_ce;
input if_read;
output[DATA_WIDTH - 1:0] if_dout;
output if_full_n;
input if_write_ce;
input if_write;
input[DATA_WIDTH - 1:0] if_din;
wire[ADDR_WIDTH - 1:0] shiftReg_addr ;
wire[DATA_WIDTH - 1:0] shiftReg_data, shiftReg_q;
reg[ADDR_WIDTH:0] mOutPtr = {(ADDR_WIDTH+1){1'b1}};
reg internal_empty_n = 0, internal_full_n = 1;
assign if_empty_n = internal_empty_n;
assign if_full_n = internal_full_n;
assign shiftReg_data = if_din;
assign if_dout = shiftReg_q;
always @ (posedge clk) begin
if (reset == 1'b1)
begin
mOutPtr <= ~{ADDR_WIDTH+1{1'b0}};
internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end
else begin
if (((if_read & if_read_ce) == 1 & internal_empty_n == 1) &&
((if_write & if_write_ce) == 0 | internal_full_n == 0))
begin
mOutPtr <= mOutPtr -1;
if (mOutPtr == 0)
internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end
else if (((if_read & if_read_ce) == 0 | internal_empty_n == 0) &&
((if_write & if_write_ce) == 1 & internal_full_n == 1))
begin
mOutPtr <= mOutPtr +1;
internal_empty_n <= 1'b1;
if (mOutPtr == DEPTH-2)
internal_full_n <= 1'b0;
end
end
end
assign shiftReg_addr = mOutPtr[ADDR_WIDTH] == 1'b0 ? mOutPtr[ADDR_WIDTH-1:0]:{ADDR_WIDTH{1'b0}};
assign shiftReg_ce = (if_write & if_write_ce) & internal_full_n;
FIFO_image_filter_img_2_rows_V_shiftReg
#(
.DATA_WIDTH(DATA_WIDTH),
.ADDR_WIDTH(ADDR_WIDTH),
.DEPTH(DEPTH))
U_FIFO_image_filter_img_2_rows_V_ram (
.clk(clk),
.data(shiftReg_data),
.ce(shiftReg_ce),
.a(shiftReg_addr),
.q(shiftReg_q));
endmodule
|
module du(clk, rst, deposit, select, price, ldRdeposit, ldRselect, ldRprice,
ldA, ldRproduct, ldRchange, ldRpurchase, ldMprice, ldMquantity,
clrRdeposit, clrRselect, clrRprice, clrA, clrRproduct, clrRchange,
clrRpurchase, purchase, refund, product, change);
input clk, rst;
input [9:0] deposit, price;
input [4:0] select;
input ldRdeposit, ldRselect, ldRprice, ldA, ldRproduct, ldRchange;
input ldRpurchase, ldMprice, ldMquantity, clrRdeposit, clrRselect;
input clrRprice, clrA, clrRproduct, clrRchange, clrRpurchase;
output reg purchase, refund;
output reg [4:0] product;
output reg [9:0] change;
reg [9:0] Rdeposit, Rprice, Adeposit;
reg [4:0] Rselect;
reg [15:0] mem [0:31];
integer i;
initial begin
for (i=0;i<32;i=i+1) begin
mem[i] = 16'h2864;
end
mem[0] = 16'b0000_0000_0011_0010; // quantity=0, price=50(RM5)
mem[1] = 16'b0010_1001_1001_0000; // quantity=10, price=400(RM40)
end
//initial begin $readmemh("default.dat", mem); end
// Register deposit
always @ (negedge rst or posedge clk) begin
if (rst == 0) Rdeposit <= 0;
else if (ldRdeposit) Rdeposit <= deposit;
else if (clrRdeposit) Rdeposit <= 0;
end
// Register select
always @ (negedge rst or posedge clk) begin
if (rst == 0) Rselect <= 0;
else if (ldRselect) Rselect <= select;
else if (clrRselect) Rselect <= 0;
end
// Register price
always @ (negedge rst or posedge clk) begin
if (rst == 0) Rprice <= 0;
else if (ldRprice) Rprice <= price;
else if (clrRprice) Rprice <= 0;
end
// Accumulator accumulate deposit, and restore previous if exceed threshold
always @ (negedge rst or posedge clk) begin
if (rst == 0) Adeposit <= 0;
else if (ldA) Adeposit <= Adeposit + Rdeposit;
else if (clrA) Adeposit <= 0;
else if (refund) Adeposit <= Adeposit - Rdeposit;
end
// Comparator Adeposit > maximum accepted deposit
always @ (Adeposit) begin
if (Adeposit > 500) refund = 1;
else refund = 0;
end
// Comparator Adeposit >= price, quantity > 0
always @ (Adeposit) begin
for (i=0; i<32;i=i+1) begin
if (0 < mem[i][13:10] && Adeposit >= mem[i][9:0])
mem[i][15] = 1;
else mem[i][15] = 0;
end
end
// Logic to indicate purchase
always @ (negedge rst or posedge clk) begin
if (rst == 0) purchase <= 0;
else if (ldRpurchase)
if (mem[Rselect][15]) purchase <= 1;
else purchase <= 0;
else if (clrRpurchase) purchase <= 0;
end
// Substractor calculate change
always @ (negedge rst or posedge clk) begin
if (rst == 0) change <= 0;
else if (ldRchange) change <= Adeposit - mem[Rselect][9:0];
else if (clrRchange) change <= 0;
end
// Register selected product
always @ (negedge rst or posedge clk) begin
if (rst == 0) product <= 0;
else if (ldRproduct) product <= Rselect;
else if (clrRproduct) product <= 0;
end
// Register array update price or reduce quantity by 1
always @ (posedge clk) begin
if (ldMquantity) mem[Rselect][13:10] <= mem[Rselect][13:10] - 1'b1;
if (ldMprice) mem[Rselect][9:0] <= Rprice;
end
endmodule
|
module sync_ptr
#(
parameter ASIZE = 4
)(
input wire dest_clk,
input wire dest_rst_n,
input wire [ASIZE:0] src_ptr,
output reg [ASIZE:0] dest_ptr
);
reg [ASIZE:0] ptr_x;
always @(posedge dest_clk or negedge dest_rst_n) begin
if (!dest_rst_n)
{dest_ptr,ptr_x} <= 0;
else
{dest_ptr,ptr_x} <= {ptr_x,src_ptr};
end
endmodule
|
module simuart(input wire clk,
input wire cs,
input wire [31:0] bus_addr,
input wire [31:0] bus_wr_val,
input wire [3:0] bus_bytesel,
output reg bus_ack,
output reg [31:0] bus_data,
output reg inter,
input wire intack
);
reg [8:0] uart_buf;
reg ff;
reg ffold;
initial begin
bus_ack = 1'b0;
bus_data = 32'b0;
inter = 1'b0;
init_socket();
end
final begin
close_socket();
end
always @(posedge clk) begin
bus_data <= 32'b0;
ff <= 1'b0;
ffold <= 1'b0;
if (~uart_buf[8] && ~cs)
uart_buf <= recuart();
ff<=ffold;
if (uart_buf[8] && (uart_buf[7:0]==8'h3)) begin
if(intack==1'b0) begin
inter <=1'b1;
end else begin
uart_buf[8]<=1'b0;
end
end else begin
if (cs && bus_bytesel[3:0] == 4'b0001) begin
if (bus_addr[3:0] == 4'b0000) begin
senduart(bus_wr_val[7:0]);
end
if (bus_addr[3:0] == 4'b1000) begin
inter<=1'b0;
end
if (bus_addr[3:0] == 4'b1100) begin
inter<=1'b1;
end
end else if (cs) begin
if (bus_addr[3:0] == 4'b0000) begin
bus_data <= {24'b0, uart_buf[7:0]};
ff <= 1'b1;
if (ff && ~ffold) uart_buf[8] <= 1'b0;
end else if (bus_addr[3:0] == 4'b0100) begin
/* Status register read. */
bus_data <= (uart_buf[8] ? 32'b10 : 32'b0);
end
end
end
bus_ack <= cs;
end
endmodule
|
module de1_soc_proc(
///////// CLOCK2 /////////
input CLOCK2_50,
input CLOCK3_50,
input CLOCK4_50,
input CLOCK_50,
///////// GPIO /////////
inout [35:0] GPIO_0,
///////// HEX0 /////////
output [6:0] HEX0,
output [6:0] HEX1,
output [6:0] HEX2,
output [6:0] HEX3,
output [6:0] HEX4,
output [6:0] HEX5,
///////// KEY /////////
input [3:0] KEY,
///////// LEDR /////////
output [9:0] LEDR,
///////// SW /////////
input [9:0] SW
);
reg rCPU_CLK = 1;
integer dCPU_CLK_CNTR = 0;
assign LEDR[8] = rCPU_CLK;
always@(posedge CLOCK2_50)
begin
if(dCPU_CLK_CNTR == 250000) begin
dCPU_CLK_CNTR <= 0;
rCPU_CLK <= ~rCPU_CLK;
end
else begin
dCPU_CLK_CNTR <= dCPU_CLK_CNTR + 1;
end
end
core core(
.iCLK(rCPU_CLK),
.iGPI(SW[7:0]),
.oGPO(LEDR[7:0])
);
endmodule
|
module header
// Internal signals
//
// Generated Signal List
//
//
// End of Generated Signal List
//
// %COMPILER_OPTS%
//
// Generated Signal Assignments
//
//
// Generated Instances and Port Mappings
//
// Generated Instance Port Map for inst_eaa
inst_eaa_e inst_eaa (
);
// End of Generated Instance Port Map for inst_eaa
// Generated Instance Port Map for inst_eab
inst_eab_e inst_eab (
);
// End of Generated Instance Port Map for inst_eab
// Generated Instance Port Map for inst_eac
inst_eac_e inst_eac (
);
// End of Generated Instance Port Map for inst_eac
endmodule
|
module decodes the signal by timing the initial HIGH pulse to determine tau_w, and then averaging a portion of the input sequence in each time bin of the recorded length, tau_w.
Ted Golfinopoulos, 9 Aug 2012
*/
parameter NUM_SIZE=7;
parameter TIMER_SIZE=13; //Number of bits in timer for measuring duration of ON/OFF pulses in clock cycles. For 10E6 Hz clock and 2E3 Hz maximum input signal, ON/OFF pulses are 1/2E3 Hz = 500 us, so register has to be able to count to at least 10E6/2E3 = 5E3 < 2^13 = 8192.
parameter THRESHOLD_TIME=127; //Number of consecutive clock cycles that the signal must hold its value before the state is accepted as genuine.
input clk, sig;
output wire [NUM_SIZE-1:0] numOut;
reg [NUM_SIZE-1:0] newNum, lastNum;
reg [3:0] numIndex; //Number to indicate where to index into encoded binary number.
reg sigLast; //Bit holding last value of input state.
//Timers and pulse width registers.
reg [TIMER_SIZE-1:0] sigTimer, sequenceTimer, tau_w;
reg [1:0] stageInSequence; //Number representing the stage in searching for and parsing numbers from serial bit sequences - see below.
reg numLock; //When this bit is high, don't allow changes to bits in decoded number.
assign numOut=lastNum; //Assign wire output to lastNum register.
initial begin
lastNum=1'b0; //Initialize output.
newNum=1'b0;
sigTimer=1'b0;
sequenceTimer=1'b0;
tau_w=1'b1;
sigLast=1'b0;
stageInSequence=1'b0;
numIndex=1'b0;
numLock=1'b0;
end
always @(posedge clk) begin
//STAGES IN SEQUENCE:
//0 => waiting for a new sequence.
//1 => timing initial on pulse.
//2 => waiting for off time that separates initial arm pulse from number pulse.
//3 => parsing number pulse
//TIME HOW LONG SIG HAS BEEN IN CURRENT STATE
if(sig==sigLast) begin
//Note - this timer will overflow.
sigTimer=sigTimer+1'b1;
end else begin
//$display("State change");
if(stageInSequence==1'b1) begin
tau_w=sigTimer; //If we are timing the pulse length, record time.
stageInSequence=2'b10; //Advance to next stage - wait for off pulse to finish.
sequenceTimer=1'b0; //Reset sequence timer.
sigTimer=1'b0; //Reset signal timer.
//$display("stageInSequence=%b, sig=%b, tau_w=%d",stageInSequence,sig,tau_w);
end
sigTimer=1'b0; //Reset signal timer.
sigLast=sig; //Update register holding last value of sig.
end
//Look for arm pulses - if found, time the arm pulse to calibrate the length of pulses in the sequence.
if(sigLast && sigTimer>THRESHOLD_TIME && stageInSequence==1'b0) begin
stageInSequence=1'b1; //Time initial on pulse to calibrate tau_w.
//$display("stageInSequence=%b, sig=%b",stageInSequence,sig);
end
//SEQUENCE TIMER
if(sequenceTimer<tau_w && stageInSequence>2'b01) begin
sequenceTimer=sequenceTimer+1'b1; //Increment timer
end else begin //Reset timer and increment index into parsed number.
if(stageInSequence==2'b10) begin
//Initial off period between arm pulse and number pulse is complete - advance stage in sequence.
stageInSequence=2'b11;
numIndex=1'b0;
numLock=1'b0; //Turn off lock for changing bit values.
//$display("stageInSequence=%b, sig=%b",stageInSequence,sig);
end else if(stageInSequence==2'b11) begin
numIndex=numIndex+1'b1; //Increment index in parsed number.
numLock=1'b0; //Turn off lock on bit value for current number in sequence.
end
sequenceTimer=1'b0;
//Reset signal timer - otherwise, can have repeated bits which are immediately
//accepted as valid because they have been on for over the threshold time.
if(stageInSequence>2'b01) begin sigTimer=1'b0; end
end
//STAGE 3 - PARSE NUMBERS FROM INPUT SEQUENCE.
if(stageInSequence==2'b11) begin
if(numIndex>=NUM_SIZE) begin
lastNum=newNum; //Update stored number.
stageInSequence=1'b0; //Number has been parsed - sequence is done.
//$display("stageInSequence=%b, sig=%b",stageInSequence,sig);
end else if(sigTimer>THRESHOLD_TIME && !numLock) begin
newNum[NUM_SIZE-1-numIndex]=sigLast; //Update bit in new number.
numLock=1'b1; //Don't allow any more changes for this bit in the number.
//$display("Recorded bit, %b, which has held for %d cycles", sigLast,sigTimer);
end
end
end
endmodule
|
module VGA_text
(
input [7:0] estado,
input [3:0]RG1_Dec,
input [3:0]RG2_Dec,
input [3:0]RG3_Dec,
input [3:0]RG1_Unit,
input [3:0]RG2_Unit,
input [3:0]RG3_Unit,
input escribiendo,
input en_out,
input wire CLK, off_alarma, on_alarma, //preguntar al profe cual es clk ???
input wire [3:0] dig0_Dec, dig1_Unit, direccion,
input wire [9:0] pix_x, pix_y,
output wire [8:0] text_on,
output reg [2:0] text_rgb,
output [7:0] seg_Ti,
output [7:0] min_Ti,
output [7:0] hor_Ti
);
wire [10:0] rom_addr;
reg [6:0] char_addr, char_addr_H, char_addr_F,
char_addr_C, char_addr_EN1, char_addr_EN2, char_addr_EN3, char_addr_EN4, char_addr_TF, char_addr_sep;
reg [3:0] row_addr;
wire [3:0] row_addr_H, row_addr_F, row_addr_C, row_addr_EN1, row_addr_EN2, row_addr_EN3, row_addr_EN4, row_addr_TF, row_addr_sep;
reg [2:0] bit_addr;
wire [2:0] bit_addr_H, bit_addr_F,bit_addr_C, bit_addr_EN1, bit_addr_EN2, bit_addr_EN3, bit_addr_EN4, bit_addr_TF, bit_addr_sep;
wire [7:0] font_word;
wire font_bit, HORA_on, FECHA_on, CRONOMETRO_on, TCRONOFIN_on, ENCABEZADO1_on, ENCABEZADO2_on, ENCABEZADO3_on, ENCABEZADO4_on,separa_on;
wire [3:0] dig_Dec_Ho, dig_Dec_min, dig_Dec_seg, dig_Dec_mes, dig_Dec_dia, dig_Dec_an, dig_Dec_Ho_Ti, dig_Dec_min_Ti, dig_Dec_seg_Ti;
wire [3:0] dig_Unit_Ho, dig_Unit_min, dig_Unit_seg, dig_Unit_mes, dig_Unit_dia, dig_Unit_an, dig_Unit_Ho_Ti, dig_Unit_min_Ti, dig_Unit_seg_Ti;
assign pix_x [0]=0;
assign seg_Ti= {dig_Dec_seg_Ti,dig_Unit_seg_Ti};
assign min_Ti= {dig_Dec_min_Ti,dig_Unit_min_Ti};
assign hor_Ti= {dig_Dec_Ho_Ti,dig_Unit_Ho_Ti};
// Instanciación de la ROM
font_rom font_unit
(.Clk(CLK), .addr(rom_addr), .data(font_word));
// instantiate control de digitos
control_digitos_1 digitos_1_unit
(
.estado(estado),
.RG1_Dec(RG1_Dec),
.RG2_Dec(RG2_Dec),
.RG3_Dec(RG3_Dec),
.escribiendo(escribiendo),
.en_out(en_out),
.clk(CLK),
.dig0_Dec(dig0_Dec),
.direccion(direccion),
.dig_Dec_Ho (dig_Dec_Ho), .dig_Dec_min (dig_Dec_min), .dig_Dec_seg (dig_Dec_seg),
.dig_Dec_mes (dig_Dec_mes), .dig_Dec_dia(dig_Dec_dia), .dig_Dec_an (dig_Dec_an),
.dig_Dec_Ho_Ti (dig_Dec_Ho_Ti), .dig_Dec_min_Ti (dig_Dec_min_Ti), .dig_Dec_seg_Ti (dig_Dec_seg_Ti)
);
// instantiate control de digitos 2
control_digitos_2 digitos_2_unit
(
.estado(estado),
.RG1_Unit(RG1_Unit),
.RG2_Unit(RG2_Unit),
.RG3_Unit(RG3_Unit),
.escribiendo(escribiendo),
.en_out(en_out),
.clk(CLK),
.dig1_Unit(dig1_Unit),
.direccion (direccion),
.dig_Unit_Ho (dig_Unit_Ho), .dig_Unit_min (dig_Unit_min), .dig_Unit_seg (dig_Unit_seg),
.dig_Unit_mes (dig_Unit_mes), .dig_Unit_dia (dig_Unit_dia), .dig_Unit_an (dig_Unit_an),
.dig_Unit_Ho_Ti (dig_Unit_Ho_Ti), .dig_Unit_min_Ti (dig_Unit_min_Ti), .dig_Unit_seg_Ti (dig_Unit_seg_Ti)
);
//-------------------------------------------
// Region de Encabezado1
// - escala 16(x)-a-16(y) de fuente, 640x480=40x15
// - line 1, 35 caracteres: "Instituto Tecnologico de Costa Rica"
//-------------------------------------------
assign ENCABEZADO1_on = (pix_y[9:4]==0) && (2<=pix_x[9:4]<=36);//los bits sobrantes son lo que tienen que dar 2^5=32
assign row_addr_EN1 = pix_y[3:0];
assign bit_addr_EN1 = pix_x[3:1];
always @*
case (pix_x[9:4])// 6 bits 2^6=64, tengo que poner un default para los extra
6'h2: char_addr_EN1 = 7'h49; // I
6'h3: char_addr_EN1 = 7'h6e; // n
6'h4: char_addr_EN1 = 7'h73; // s
6'h5: char_addr_EN1 = 7'h74; // t
6'h6: char_addr_EN1 = 7'h69; // i
6'h7: char_addr_EN1 = 7'h74; // t
6'h8: char_addr_EN1 = 7'h75; // u
6'h9: char_addr_EN1 = 7'h74; // t
6'ha: char_addr_EN1 = 7'h6f; // o
6'hb: char_addr_EN1 = 7'h00; //
6'hc: char_addr_EN1 = 7'h54; // T
6'hd: char_addr_EN1 = 7'h65; // e
6'he: char_addr_EN1 = 7'h63; // c
6'hf: char_addr_EN1 = 7'h6e; // n
6'h10: char_addr_EN1 = 7'h6f; // o
6'h11: char_addr_EN1 = 7'h6c; // l
6'h12: char_addr_EN1 = 7'h6f; // o
6'h13: char_addr_EN1 = 7'h67; // g
6'h14: char_addr_EN1 = 7'h69; // i
6'h15: char_addr_EN1 = 7'h63; // c
6'h16: char_addr_EN1 = 7'h6f; // o
6'h17: char_addr_EN1 = 7'h00; //
6'h18: char_addr_EN1 = 7'h64; // d
6'h19: char_addr_EN1 = 7'h65; // e
6'h1a: char_addr_EN1 = 7'h00; //
6'h1b: char_addr_EN1 = 7'h43; // C
6'h1c: char_addr_EN1 = 7'h6f; // o
6'h1d: char_addr_EN1 = 7'h73; // s
6'h1e: char_addr_EN1 = 7'h74; // t
6'h1f: char_addr_EN1 = 7'h61; // a
6'h20: char_addr_EN1 = 7'h00; //
6'h21: char_addr_EN1 = 7'h52; // R
6'h22: char_addr_EN1 = 7'h69; // i
6'h23: char_addr_EN1 = 7'h63; // c
6'h24: char_addr_EN1 = 7'h61; // a
default: char_addr_EN1 = 7'h00; //
endcase
//-------------------------------------------
// Region de Encabezado2
// - escala 16(x)-a-16(y) de fuente, 640x480=40x15
// - line 2, 36 caracteres: "Escuela de Ingenieria en Electronica"
//-------------------------------------------
assign ENCABEZADO2_on = (pix_y[9:4]==1) && (2<=pix_x[9:4]<=37);//los bits sobrantes son lo que tienen que dar 2^5=32
assign row_addr_EN2 = pix_y[3:0];
assign bit_addr_EN2 = pix_x[3:1];
always @*
case (pix_x[9:4])// 6 bits 2^6=64, tengo que poner un default para los extra
6'h2: char_addr_EN2 = 7'h45; // E
6'h3: char_addr_EN2 = 7'h73; // s
6'h4: char_addr_EN2 = 7'h63; // c
6'h5: char_addr_EN2 = 7'h75; // u
6'h6: char_addr_EN2 = 7'h65; // e
6'h7: char_addr_EN2 = 7'h6c; // l
6'h8: char_addr_EN2 = 7'h61; // a
6'h9: char_addr_EN2 = 7'h00; //
6'ha: char_addr_EN2 = 7'h64; // d
6'hb: char_addr_EN2 = 7'h65; // e
6'hc: char_addr_EN2 = 7'h00; //
6'hd: char_addr_EN2 = 7'h49; // I
6'he: char_addr_EN2 = 7'h6e; // n
6'hf: char_addr_EN2 = 7'h67; // g
6'h10: char_addr_EN2 = 7'h65; // e
6'h11: char_addr_EN2 = 7'h6e; // n
6'h12: char_addr_EN2 = 7'h69; // i
6'h13: char_addr_EN2 = 7'h65; // e
6'h14: char_addr_EN2 = 7'h72; // r
6'h15: char_addr_EN2 = 7'h69; // i
6'h16: char_addr_EN2 = 7'h61; // a
6'h17: char_addr_EN2 = 7'h00; //
6'h18: char_addr_EN2 = 7'h65; // e
6'h19: char_addr_EN2 = 7'h6e; // n
6'h1a: char_addr_EN2 = 7'h00; //
6'h1b: char_addr_EN2 = 7'h45; // E
6'h1c: char_addr_EN2 = 7'h6c; // l
6'h1d: char_addr_EN2 = 7'h65; // e
6'h1e: char_addr_EN2 = 7'h63; // c
6'h1f: char_addr_EN2 = 7'h74; // t
6'h20: char_addr_EN2 = 7'h72; // r
6'h21: char_addr_EN2 = 7'h6f; // o
6'h22: char_addr_EN2 = 7'h6e; // n
6'h23: char_addr_EN2 = 7'h69; // i
6'h24: char_addr_EN2 = 7'h63; // c
6'h25: char_addr_EN2 = 7'h61; // a
default: char_addr_EN2 = 7'h00; //
endcase
//-------------------------------------------
// Region de Encabezado3
// - escala 16(x)-a-16(y) de fuente, 640x480=40x15
// - line 3, 36 caracteres: "Lab. de Diseno de Sistemas Digitales"
//-------------------------------------------
assign ENCABEZADO3_on = (pix_y[9:4]==2) && (2<=pix_x[9:4]<=37);//los bits sobrantes son lo que tienen que dar 2^5=32
assign row_addr_EN3 = pix_y[3:0];
assign bit_addr_EN3 = pix_x[3:1];
always @*
case (pix_x[9:4])// 6 bits 2^6=64, tengo que poner un default para los extra
6'h2: char_addr_EN3 = 7'h4c; // L
6'h3: char_addr_EN3 = 7'h61; // a
6'h4: char_addr_EN3 = 7'h62; // b
6'h5: char_addr_EN3 = 7'h2e; // .
6'h6: char_addr_EN3 = 7'h00; //
6'h7: char_addr_EN3 = 7'h64; // d
6'h8: char_addr_EN3 = 7'h65; // e
6'h9: char_addr_EN3 = 7'h00; //
6'ha: char_addr_EN3 = 7'h44; // D
6'hb: char_addr_EN3 = 7'h69; // i
6'hc: char_addr_EN3 = 7'h73; // s
6'hd: char_addr_EN3 = 7'h65; // e
6'he: char_addr_EN3 = 7'h6e; // n
6'hf: char_addr_EN3 = 7'h6f; // o
6'h10: char_addr_EN3 = 7'h00; //
6'h11: char_addr_EN3 = 7'h64; // d
6'h12: char_addr_EN3 = 7'h65; // e
6'h13: char_addr_EN3 = 7'h00; //
6'h14: char_addr_EN3 = 7'h53; // S
6'h15: char_addr_EN3 = 7'h69; // i
6'h16: char_addr_EN3 = 7'h73; // s
6'h17: char_addr_EN3 = 7'h74; // t
6'h18: char_addr_EN3 = 7'h65; // e
6'h19: char_addr_EN3 = 7'h6d; // m
6'h1a: char_addr_EN3 = 7'h61; // a
6'h1b: char_addr_EN3 = 7'h73; // s
6'h1c: char_addr_EN3 = 7'h00; //
6'h1d: char_addr_EN3 = 7'h44; // D
6'h1e: char_addr_EN3 = 7'h69; // i
6'h1f: char_addr_EN3 = 7'h67; // g
6'h20: char_addr_EN3 = 7'h69; // i
6'h21: char_addr_EN3 = 7'h74; // t
6'h22: char_addr_EN3 = 7'h61; // a
6'h23: char_addr_EN3 = 7'h6c; // l
6'h24: char_addr_EN3 = 7'h65; // e
6'h25: char_addr_EN3 = 7'h73; // s
default: char_addr_EN3 = 7'h00; //
endcase
//-------------------------------------------
// Region de Encabezado4
// - escala 16(x)-a-16(y) de fuente, 640x480=40x15
// - line 15, 8 caracteres: ">Alarma<"
//-------------------------------------------
assign ENCABEZADO4_on = (pix_y[9:4]==14) && (17<=pix_x[9:4]<=24);//los bits sobrantes son lo que tienen que dar 2^5=32
assign row_addr_EN4 = pix_y[3:0];
assign bit_addr_EN4 = pix_x[3:1];
always @*
case (pix_x[8:4])// 5 bits 2^5=32, tengo que poner un default para los extra
5'h11: char_addr_EN4 = 7'h10; // >
5'h12: char_addr_EN4 = 7'h41; // A
5'h13: char_addr_EN4 = 7'h6c; // l
5'h14: char_addr_EN4 = 7'h61; // a
5'h15: char_addr_EN4 = 7'h72; // r
5'h16: char_addr_EN4 = 7'h6d; // m
5'h17: char_addr_EN4 = 7'h61; // a
5'h18: char_addr_EN4 = 7'h11; // <
default: char_addr_EN4 = 7'h00; //
endcase
//-------------------------------------------
// Region de separacion
// - escala 16(x)-a-16(y) de fuente, 640x480=10x3.75~4
// - line 6, 40 caracteres: "----------"
//-------------------------------------------
assign separa_on = (pix_y[9:4]==5) && (0<=pix_x[9:4]<=39);//los bits sobrantes son lo que tienen que dar 2^7=128
assign row_addr_sep = pix_y[3:0];//4b
assign bit_addr_sep = pix_x[3:1];//3b
always @*
case (pix_x[7:4])// 4 bits 2^4=16, y ocupo 10, tengo que poner un default para los extra
4'h0: char_addr_sep = 7'h2d; // -
4'h1: char_addr_sep = 7'h0f; //*
4'h2: char_addr_sep = 7'h2d; // -
4'h3: char_addr_sep = 7'h0f; //*
4'h4: char_addr_sep = 7'h2d; // -
4'h5: char_addr_sep = 7'h0f; //*
4'h6: char_addr_sep = 7'h2d; // -
4'h7: char_addr_sep = 7'h0f; //*
4'h8: char_addr_sep = 7'h2d; // -
4'h9: char_addr_sep = 7'h0f; //*
4'ha: char_addr_sep = 7'h2d; // -
4'hb: char_addr_sep = 7'h0f; //*
4'hc: char_addr_sep = 7'h2d; // -
4'hd: char_addr_sep = 7'h0f; //*
4'he: char_addr_sep = 7'h2d; // -
4'hf: char_addr_sep = 7'h0f; //*
4'h10: char_addr_sep = 7'h2d; // -
4'h11: char_addr_sep = 7'h0f; //*
4'h12: char_addr_sep = 7'h2d; // -
4'h13: char_addr_sep = 7'h0f; //*
4'h14: char_addr_sep = 7'h2d; // -
4'h15: char_addr_sep = 7'h0f; //*
4'h16: char_addr_sep = 7'h2d; // -
4'h17: char_addr_sep = 7'h0f; //*
4'h18: char_addr_sep = 7'h2d; // -
4'h19: char_addr_sep = 7'h0f; //*
4'h1a: char_addr_sep = 7'h2d; // -
4'h1b: char_addr_sep = 7'h0f; //*
4'h1c: char_addr_sep = 7'h2d; // -
4'h1d: char_addr_sep = 7'h0f; //*
4'h1e: char_addr_sep = 7'h2d; // -
4'h1f: char_addr_sep = 7'h0f; //*
4'h20: char_addr_sep = 7'h2d; // -
4'h21: char_addr_sep = 7'h0f; //*
4'h22: char_addr_sep = 7'h2d; // -
4'h23: char_addr_sep = 7'h0f; //*
4'h24: char_addr_sep = 7'h2d; // -
4'h25: char_addr_sep = 7'h0f; //*
4'h26: char_addr_sep = 7'h2d; // -
4'h27: char_addr_sep = 7'h0f; //*
default: char_addr_sep = 7'h0f; //*
endcase
//-------------------------------------------
// Region de Fecha
// - escala 16(x)-a-16(y) de fuente, 640x480=40x7.5~8
// - line 8, 17 chars: ">Fecha:DD/DD/20DD"
//-------------------------------------------
assign FECHA_on = (pix_y[9:4]==7) && (1<=pix_x[9:4]) && (pix_x[9:4]<=17);//los bits sobrantes son lo que tienen que dar 2^4=16
assign row_addr_F = pix_y[3:0];
assign bit_addr_F = pix_x[3:1];
always @*
case (pix_x[8:4])//UTILIZO 5 BITS PARA GENERAR LAS 17 COMBINACIONES
5'h1: char_addr_F = 7'h00; // >
5'h2: char_addr_F = 7'h00; // F
5'h3: char_addr_F = 7'h00; // e
5'h4: char_addr_F = 7'h00; // c
5'h5: char_addr_F = 7'h00; // h
5'h6: char_addr_F = 7'h00; // a
5'h7: char_addr_F = 7'h00; // :
5'h8: char_addr_F = {3'b011, dig_Dec_dia}; // dia
5'h9: char_addr_F = {3'b011,dig_Unit_dia}; // dia
5'ha: char_addr_F = 7'h2f; // /
5'hb: char_addr_F = {3'b011, dig_Dec_mes}; // mes
5'hc: char_addr_F = {3'b011, dig_Unit_mes}; // mes
5'hd: char_addr_F = 7'h2f; // /
5'he: char_addr_F = 7'h32; // 2
5'hf: char_addr_F = 7'h30; // 0
5'h10: char_addr_F = {3'b011, dig_Dec_an}; // año
default char_addr_F = {3'b011, dig_Unit_an}; // año
endcase
//-------------------------------------------
// Region de Cronometro
// - escala 16(x)-a-64(y) de fuente, 640x480=40x7.5~8
// - line 10, 20 chars: ">Cronometro:DD/DD/DD"
//-------------------------------------------
assign CRONOMETRO_on = (pix_y[9:4]==24) && (1<=pix_x[9:4]) && (pix_x[9:4]<=17);//los bits sobrantes son lo que tienen que dar 2^4=16
assign row_addr_C = pix_y[3:0];
assign bit_addr_C = pix_x[3:1];
always @*
case (pix_x[8:4])//UTILIZO 5 BITS PARA GENERAR LAS 20 COMBINACIONES
5'h1: char_addr_C = 7'h00;// >
5'h2: char_addr_C = 7'h00; // C
5'h3: char_addr_C = 7'h00; // r
5'h4: char_addr_C = 7'h00; // o
5'h5: char_addr_C = 7'h00; // n
5'h6: char_addr_C = 7'h00; // o
5'h7: char_addr_C = 7'h00; // m
5'h8: char_addr_C = 7'h00; // e
5'h9: char_addr_C = {3'b011, dig_Dec_Ho_Ti}; //Horas
5'ha: char_addr_C = {3'b011, dig_Unit_Ho_Ti}; // Horas
5'hb: char_addr_C = 7'h3a; // :
5'hc: char_addr_C = {3'b011, dig_Dec_min_Ti}; // minutos
5'hd: char_addr_C = {3'b011, dig_Unit_min_Ti}; // minutos
5'he: char_addr_C = 7'h3a; // :
5'hf: char_addr_C = {3'b011, dig_Dec_seg_Ti}; //segundos
5'h10: char_addr_C = {3'b011, dig_Unit_seg_Ti}; // segundos
default: char_addr_C = 7'h00; // e
endcase
//-------------------------------------------
// Region de Hora
// - escala 16(x)-a-16(y) de fuente, 640x480=40x7.5~8
// - line 12, 14 chars: ">Hora:DD/DD/DD"
//-------------------------------------------
assign HORA_on = (pix_y[9:4]==15) && (1<=pix_x[9:4]) && (pix_x[9:4]<=17);//los bits sobrantes son lo que tienen que dar 2^4=16
assign row_addr_H = pix_y[3:0];
assign bit_addr_H = pix_x[3:1];
always @*
case (pix_x[7:4])//UTILIZO 4 BITS PARA GENERAR LAS 14 COMBINACIONES
4'h1: char_addr_H = 7'h00; // >
4'h2: char_addr_H = 7'h00; // H
4'h3: char_addr_H = 7'h00; // o
4'h4: char_addr_H = 7'h00; // r
4'h5: char_addr_H = 7'h00; // a
4'h6: char_addr_H = 7'h00; // :
4'h7: char_addr_H = 7'h00; // a
4'h8: char_addr_H = 7'h00; // :
4'h9: char_addr_H = {3'b011, dig_Dec_Ho}; // Horas
4'ha: char_addr_H = {3'b011, dig_Unit_Ho}; // Horas
4'hb: char_addr_H = 7'h3a; // :
4'hc: char_addr_H = {3'b011, dig_Dec_min}; // minutos
4'hd: char_addr_H = {3'b011, dig_Unit_min}; // minutos
4'he: char_addr_H = 7'h3a; // :
4'hf: char_addr_H = {3'b011, dig_Dec_seg}; // segundos
4'h10: char_addr_H = {3'b011, dig_Unit_seg}; // segundos
default: char_addr_H = 7'h00; // :
endcase
//-------------------------------------------
// Region de separacion
// - escala 64(x)-a-128(y) de fuente, 640x480=10x3.75~4
// - line 3, 10 caracter:
//
//
// ******
// ********
// ** ** **
// ********
// ********
// ** **
// *** ***
// ********
// ********
// ******
//
//
//
//
//-------------------------------------------
assign TCRONOFIN_on= (pix_y[9:7]==2) && ((2<=pix_x[9:6])&& (pix_x[9:6]<=8));//los bits sobrantes son lo que tienen que dar 2^7=128
assign row_addr_TF = pix_y[6:3];//4b
assign bit_addr_TF = pix_x[5:3];//3b
always @*
case (pix_x[8:6])// 4 bits 2^4=16, y ocupo 10, tengo que poner un default para los extra
3'h2: char_addr_TF = 7'h00; //
3'h3: char_addr_TF = 7'h02; //
3'h4: char_addr_TF = 7'h00; //
3'h5: char_addr_TF = 7'h02; //
3'h6: char_addr_TF = 7'h00; //
3'h7: char_addr_TF = 7'h02; //
3'h8: char_addr_TF = 7'h00; //
default: char_addr_TF = 7'h0f; //*
endcase
//-------------------------------------------
// Direccion de fuente en ROM y rgb
//-------------------------------------------
always @*
begin
text_rgb = 3'b000; // fondo, negro
if (ENCABEZADO1_on)
begin
char_addr = char_addr_EN1;
row_addr = row_addr_EN1;
bit_addr = bit_addr_EN1;
if (font_bit)
text_rgb = 3'b001;
else
text_rgb = 3'b111;
end
else if (ENCABEZADO2_on)
begin
char_addr = char_addr_EN2;
row_addr = row_addr_EN2;
bit_addr = bit_addr_EN2;
if (font_bit)
text_rgb = 3'b001;
else
text_rgb = 3'b111;
end
else if (ENCABEZADO3_on)
begin
char_addr = char_addr_EN3;
row_addr = row_addr_EN3;
bit_addr = bit_addr_EN3;
if (font_bit)
text_rgb = 3'b001;
else
text_rgb = 3'b111;
end
else if (separa_on)
begin
char_addr = char_addr_sep;
row_addr = row_addr_sep;
bit_addr = bit_addr_sep;
if (font_bit)
text_rgb = 3'b010;
else
text_rgb = 3'b111;
end
else if (HORA_on )
begin
char_addr = char_addr_H;
row_addr = row_addr_H;
bit_addr = bit_addr_H;
if (font_bit)
text_rgb = 3'b111;
else
text_rgb = 3'b000;
end
else if (CRONOMETRO_on)
begin
char_addr = char_addr_C;
row_addr = row_addr_C;
bit_addr = bit_addr_C;
if (font_bit)
text_rgb = 3'b111;
else
text_rgb = 3'b000;
end
else if (FECHA_on)
begin
char_addr = char_addr_F;
row_addr = row_addr_F;
bit_addr = bit_addr_F;
if (font_bit)
text_rgb = 3'b111;
else
text_rgb = 3'b000;
end
else if (ENCABEZADO4_on)
begin
char_addr = char_addr_EN4;
row_addr = row_addr_EN4;
bit_addr = bit_addr_EN4;
if (font_bit)
text_rgb = 3'b010;
else
text_rgb = 3'b111;
end
else //TCRONOFIN_on))
begin
char_addr = char_addr_TF;
row_addr = row_addr_TF;
bit_addr = bit_addr_TF;
if ((font_bit)&&(off_alarma))
text_rgb = 3'b010;
else if ((font_bit)&&(on_alarma))
text_rgb = 3'b100;
else
text_rgb = 3'b000;
end
end
assign text_on = {ENCABEZADO1_on, ENCABEZADO2_on, ENCABEZADO3_on, separa_on, HORA_on, CRONOMETRO_on, FECHA_on, ENCABEZADO4_on,TCRONOFIN_on};
//-------------------------------------------
// font rom interface
//-------------------------------------------
assign rom_addr = {char_addr, row_addr};
assign font_bit = font_word[~bit_addr];
endmodule
|
module NW_vc_fc_out (flit, flit_valid,
channel_cntrl_in,
vc_status, // vc_status[vc]=1 if blocked (fifo is full)
// only when using credit-based flow control
vc_empty, // vc_empty[vc]=1 if VC fifo is empty (credits=init_credits)
vc_credits,
clk, rst_n);
`include "NW_functions.v"
parameter num_vcs = 4;
parameter init_credits = 4;
parameter optimized_credit_counter = 1;
// +1 as has to hold 'init_credits' value
parameter counter_bits = clogb2(init_credits+1);
input flit_t flit;
input flit_valid;
input chan_cntrl_t channel_cntrl_in;
output vc_t vc_status;
output [num_vcs-1:0] vc_empty;
output [num_vcs-1:0][counter_bits-1:0] vc_credits;
input clk, rst_n;
logic [num_vcs-1:0][counter_bits-1:0] counter;
logic [num_vcs-1:0] inc, dec;
// buffer credit and flit vc id.'s so we can move counter in credit counter optimization
logic last_credit_valid, last_flit_valid;
logic [num_vcs-1:0] last_flit_vc_id;
// logic [counter_bits-1:0] last_credit;
vc_index_t last_credit;
logic [num_vcs-1:0][counter_bits-1:0] counter_current;
logic [num_vcs-1:0] vc_empty;
genvar i;
// fsm states
parameter stop=1'b0, go=1'b1;
logic [num_vcs-1:0] current_state, next_state;
// *************************************
// Stop/Go Flow Control
// *************************************
`ifdef NEARLY_FULL_FLOW_CONTROL
generate
for (i=0; i<num_vcs; i++) begin:pervc
always@(posedge clk) begin
if (!rst_n)
current_state[i]<=go;
else
current_state[i]<=next_state[i];
end
always_comb begin
case (current_state[i])
stop:
if (channel_cntrl_in.nearly_full[i])
begin
next_state[i]<=go;
end
else
begin
next_state[i]<=stop;
end
go:
// nearly full and flit sent
if (channel_cntrl_in.nearly_full[i] && flit_valid && (oh2bin(flit.control.vc_id)==i))
begin
next_state[i]<=stop;
end
else
begin
next_state[i]<=go;
end
endcase
end // always_comb begin
assign vc_status[i]=(current_state[i]==stop);
end // block: pervc
endgenerate
`endif
// *************************************
// Credit-based Flow Control
// *************************************
`ifdef CREDIT_FLOW_CONTROL
generate
if (optimized_credit_counter) begin
// ***********************************
// optimized credit-counter (moves counter logic off critical path)
// ***********************************
always@(posedge clk) begin
last_credit_valid <= channel_cntrl_in.credit_valid;
last_credit <= channel_cntrl_in.credit;
last_flit_valid <= flit_valid;
last_flit_vc_id <= flit.control.vc_id;
// $display ("empty=%b", vc_empty);
end
assign vc_credits = counter_current;
for (i=0; i<num_vcs; i++) begin:pervc1
always_comb begin:addsub
if (inc[i] && !dec[i])
counter_current[i]=counter[i]+1;
else if (dec[i] && !inc[i])
counter_current[i]=counter[i]-1;
else
counter_current[i]=counter[i];
end
always@(posedge clk) begin
if (!rst_n) begin
counter[i]<=init_credits;
vc_empty[i]<='1;
end else begin
counter[i]<=counter_current[i];
if ((counter_current[i]==0) ||
((counter_current[i]==1) && flit_valid && (oh2bin(flit.control.vc_id)==i)) &&
!(channel_cntrl_in.credit_valid && (channel_cntrl_in.credit==i))) begin
vc_status[i] <= 1'b1;
vc_empty[i] <= 1'b0;
end else begin
vc_status[i] <= 1'b0;
vc_empty[i] <= (counter_current[i]==init_credits);
end
end // else: !if(!rst_n)
end // always@ (posedge clk)
assign inc[i]=(last_credit_valid) && (last_credit==i);
assign dec[i]=(last_flit_valid) && (oh2bin(last_flit_vc_id)==i);
end
end else begin
assign vc_credits = counter;
// ***********************************
// unoptimized credit-counter
// ***********************************
for (i=0; i<num_vcs; i++) begin:pervc
always@(posedge clk) begin
if (!rst_n) begin
counter[i]<=init_credits;
end else begin
if (inc[i] && !dec[i]) begin
assert (counter[i]!=init_credits) else $fatal;
counter[i]<=counter[i]+1;
end
if (dec[i] && !inc[i]) begin
assert (counter[i]!=0) else $fatal;
counter[i]<=counter[i]-1;
end
end // else: !if(!rst_n)
end
// received credit for VC i?
assign inc[i]=(channel_cntrl_in.credit_valid) && (channel_cntrl_in.credit==i);
// flit sent, one less credit
assign dec[i]=(flit_valid) && (oh2bin(flit.control.vc_id)==i);
// if counter==0, VC is blocked
assign vc_status[i]=(counter[i]==0);
// if counter==init_credits, VC buffer is empty
assign vc_empty[i]=(counter[i]==init_credits);
end // block: pervc
end
endgenerate
`endif
endmodule
|
module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
s2f_width_check ( .error(1'b1) );
end
endgenerate
system_acl_iface_hps_fpga_interfaces fpga_interfaces (
.h2f_rst_n (h2f_rst_n), // h2f_reset.reset_n
.h2f_lw_axi_clk (h2f_lw_axi_clk), // h2f_lw_axi_clock.clk
.h2f_lw_AWID (h2f_lw_AWID), // h2f_lw_axi_master.awid
.h2f_lw_AWADDR (h2f_lw_AWADDR), // .awaddr
.h2f_lw_AWLEN (h2f_lw_AWLEN), // .awlen
.h2f_lw_AWSIZE (h2f_lw_AWSIZE), // .awsize
.h2f_lw_AWBURST (h2f_lw_AWBURST), // .awburst
.h2f_lw_AWLOCK (h2f_lw_AWLOCK), // .awlock
.h2f_lw_AWCACHE (h2f_lw_AWCACHE), // .awcache
.h2f_lw_AWPROT (h2f_lw_AWPROT), // .awprot
.h2f_lw_AWVALID (h2f_lw_AWVALID), // .awvalid
.h2f_lw_AWREADY (h2f_lw_AWREADY), // .awready
.h2f_lw_WID (h2f_lw_WID), // .wid
.h2f_lw_WDATA (h2f_lw_WDATA), // .wdata
.h2f_lw_WSTRB (h2f_lw_WSTRB), // .wstrb
.h2f_lw_WLAST (h2f_lw_WLAST), // .wlast
.h2f_lw_WVALID (h2f_lw_WVALID), // .wvalid
.h2f_lw_WREADY (h2f_lw_WREADY), // .wready
.h2f_lw_BID (h2f_lw_BID), // .bid
.h2f_lw_BRESP (h2f_lw_BRESP), // .bresp
.h2f_lw_BVALID (h2f_lw_BVALID), // .bvalid
.h2f_lw_BREADY (h2f_lw_BREADY), // .bready
.h2f_lw_ARID (h2f_lw_ARID), // .arid
.h2f_lw_ARADDR (h2f_lw_ARADDR), // .araddr
.h2f_lw_ARLEN (h2f_lw_ARLEN), // .arlen
.h2f_lw_ARSIZE (h2f_lw_ARSIZE), // .arsize
.h2f_lw_ARBURST (h2f_lw_ARBURST), // .arburst
.h2f_lw_ARLOCK (h2f_lw_ARLOCK), // .arlock
.h2f_lw_ARCACHE (h2f_lw_ARCACHE), // .arcache
.h2f_lw_ARPROT (h2f_lw_ARPROT), // .arprot
.h2f_lw_ARVALID (h2f_lw_ARVALID), // .arvalid
.h2f_lw_ARREADY (h2f_lw_ARREADY), // .arready
.h2f_lw_RID (h2f_lw_RID), // .rid
.h2f_lw_RDATA (h2f_lw_RDATA), // .rdata
.h2f_lw_RRESP (h2f_lw_RRESP), // .rresp
.h2f_lw_RLAST (h2f_lw_RLAST), // .rlast
.h2f_lw_RVALID (h2f_lw_RVALID), // .rvalid
.h2f_lw_RREADY (h2f_lw_RREADY), // .rready
.f2h_sdram0_ADDRESS (f2h_sdram0_ADDRESS), // f2h_sdram0_data.address
.f2h_sdram0_BURSTCOUNT (f2h_sdram0_BURSTCOUNT), // .burstcount
.f2h_sdram0_WAITREQUEST (f2h_sdram0_WAITREQUEST), // .waitrequest
.f2h_sdram0_READDATA (f2h_sdram0_READDATA), // .readdata
.f2h_sdram0_READDATAVALID (f2h_sdram0_READDATAVALID), // .readdatavalid
.f2h_sdram0_READ (f2h_sdram0_READ), // .read
.f2h_sdram0_WRITEDATA (f2h_sdram0_WRITEDATA), // .writedata
.f2h_sdram0_BYTEENABLE (f2h_sdram0_BYTEENABLE), // .byteenable
.f2h_sdram0_WRITE (f2h_sdram0_WRITE), // .write
.f2h_sdram0_clk (f2h_sdram0_clk), // f2h_sdram0_clock.clk
.f2h_irq_p0 (f2h_irq_p0), // f2h_irq0.irq
.f2h_irq_p1 (f2h_irq_p1) // f2h_irq1.irq
);
system_acl_iface_hps_hps_io hps_io (
.mem_a (mem_a), // memory.mem_a
.mem_ba (mem_ba), // .mem_ba
.mem_ck (mem_ck), // .mem_ck
.mem_ck_n (mem_ck_n), // .mem_ck_n
.mem_cke (mem_cke), // .mem_cke
.mem_cs_n (mem_cs_n), // .mem_cs_n
.mem_ras_n (mem_ras_n), // .mem_ras_n
.mem_cas_n (mem_cas_n), // .mem_cas_n
.mem_we_n (mem_we_n), // .mem_we_n
.mem_reset_n (mem_reset_n), // .mem_reset_n
.mem_dq (mem_dq), // .mem_dq
.mem_dqs (mem_dqs), // .mem_dqs
.mem_dqs_n (mem_dqs_n), // .mem_dqs_n
.mem_odt (mem_odt), // .mem_odt
.mem_dm (mem_dm), // .mem_dm
.oct_rzqin (oct_rzqin), // .oct_rzqin
.hps_io_emac1_inst_TX_CLK (hps_io_emac1_inst_TX_CLK), // hps_io.hps_io_emac1_inst_TX_CLK
.hps_io_emac1_inst_TXD0 (hps_io_emac1_inst_TXD0), // .hps_io_emac1_inst_TXD0
.hps_io_emac1_inst_TXD1 (hps_io_emac1_inst_TXD1), // .hps_io_emac1_inst_TXD1
.hps_io_emac1_inst_TXD2 (hps_io_emac1_inst_TXD2), // .hps_io_emac1_inst_TXD2
.hps_io_emac1_inst_TXD3 (hps_io_emac1_inst_TXD3), // .hps_io_emac1_inst_TXD3
.hps_io_emac1_inst_RXD0 (hps_io_emac1_inst_RXD0), // .hps_io_emac1_inst_RXD0
.hps_io_emac1_inst_MDIO (hps_io_emac1_inst_MDIO), // .hps_io_emac1_inst_MDIO
.hps_io_emac1_inst_MDC (hps_io_emac1_inst_MDC), // .hps_io_emac1_inst_MDC
.hps_io_emac1_inst_RX_CTL (hps_io_emac1_inst_RX_CTL), // .hps_io_emac1_inst_RX_CTL
.hps_io_emac1_inst_TX_CTL (hps_io_emac1_inst_TX_CTL), // .hps_io_emac1_inst_TX_CTL
.hps_io_emac1_inst_RX_CLK (hps_io_emac1_inst_RX_CLK), // .hps_io_emac1_inst_RX_CLK
.hps_io_emac1_inst_RXD1 (hps_io_emac1_inst_RXD1), // .hps_io_emac1_inst_RXD1
.hps_io_emac1_inst_RXD2 (hps_io_emac1_inst_RXD2), // .hps_io_emac1_inst_RXD2
.hps_io_emac1_inst_RXD3 (hps_io_emac1_inst_RXD3), // .hps_io_emac1_inst_RXD3
.hps_io_sdio_inst_CMD (hps_io_sdio_inst_CMD), // .hps_io_sdio_inst_CMD
.hps_io_sdio_inst_D0 (hps_io_sdio_inst_D0), // .hps_io_sdio_inst_D0
.hps_io_sdio_inst_D1 (hps_io_sdio_inst_D1), // .hps_io_sdio_inst_D1
.hps_io_sdio_inst_CLK (hps_io_sdio_inst_CLK), // .hps_io_sdio_inst_CLK
.hps_io_sdio_inst_D2 (hps_io_sdio_inst_D2), // .hps_io_sdio_inst_D2
.hps_io_sdio_inst_D3 (hps_io_sdio_inst_D3), // .hps_io_sdio_inst_D3
.hps_io_uart0_inst_RX (hps_io_uart0_inst_RX), // .hps_io_uart0_inst_RX
.hps_io_uart0_inst_TX (hps_io_uart0_inst_TX), // .hps_io_uart0_inst_TX
.hps_io_i2c1_inst_SDA (hps_io_i2c1_inst_SDA), // .hps_io_i2c1_inst_SDA
.hps_io_i2c1_inst_SCL (hps_io_i2c1_inst_SCL), // .hps_io_i2c1_inst_SCL
.hps_io_gpio_inst_GPIO53 (hps_io_gpio_inst_GPIO53) // .hps_io_gpio_inst_GPIO53
);
endmodule
|
module header
// Internal signals
//
// Generated Signal List
//
//
// End of Generated Signal List
//
// %COMPILER_OPTS%
//
// Generated Signal Assignments
//
//
// Generated Instances and Port Mappings
//
endmodule
|
module EP_MEM (
clk,
a_rd_a_i_0, // [8:0] Port A Read Address Bank 0
a_rd_d_o_0, // [31:0] Port A Read Data Bank 0
a_rd_en_i_0, // Port A Read Enable Bank 0
b_wr_a_i_0, // [8:0] Port B Write Address Bank 0
b_wr_d_i_0, // [31:0] Port B Write Data Bank 0
b_wr_en_i_0, // Port B Write Enable Bank 0
b_rd_d_o_0, // [31:0] Port B Read Data Bank 0
b_rd_en_i_0, // Port B Read Enable Bank 0
a_rd_a_i_1, // [8:0] Port A Read Address Bank 1
a_rd_d_o_1, // [31:0] Port A Read Data Bank 1
a_rd_en_i_1,
b_wr_a_i_1, // [8:0] Port B Write Address Bank 1
b_wr_d_i_1, // [31:0] Port B Write Data Bank 1
b_wr_en_i_1, // Port B Write Enable Bank 1
b_rd_d_o_1, // [31:0] Port B Read Data Bank 1
b_rd_en_i_1, // Port B Read Enable Bank 1
a_rd_a_i_2, // [8:0] Port A Read Address Bank 2
a_rd_d_o_2, // [31:0] Port A Read Data Bank 2
a_rd_en_i_2,
b_wr_a_i_2, // [8:0] Port B Write Address Bank 2
b_wr_d_i_2, // [31:0] Port B Write Data Bank 2
b_wr_en_i_2, // Port B Write Enable Bank 2
b_rd_d_o_2, // [31:0] Port B Read Data Bank 2
b_rd_en_i_2, // Port B Read Enable Bank 2
a_rd_a_i_3, // [8:0] Port A Read Address Bank 3
a_rd_d_o_3, // [31:0] Port A Read Data Bank 3
a_rd_en_i_3,
b_wr_a_i_3, // [8:0] Port B Write Address Bank 3
b_wr_d_i_3, // [31:0] Port B Write Data Bank 3
b_wr_en_i_3, // Port B Write Enable Bank 3
b_rd_d_o_3, // [31:0] Port B Read Data Bank 3
b_rd_en_i_3 // Port B Read Enable Bank 3
);
input clk;
input [08:00] a_rd_a_i_0;
output [31:00] a_rd_d_o_0;
input a_rd_en_i_0;
input [08:00] b_wr_a_i_0;
input [31:00] b_wr_d_i_0;
input b_wr_en_i_0;
output [31:00] b_rd_d_o_0;
input b_rd_en_i_0;
input [08:00] a_rd_a_i_1;
output [31:00] a_rd_d_o_1;
input a_rd_en_i_1;
input [08:00] b_wr_a_i_1;
input [31:00] b_wr_d_i_1;
input b_wr_en_i_1;
output [31:00] b_rd_d_o_1;
input b_rd_en_i_1;
input [08:00] a_rd_a_i_2;
output [31:00] a_rd_d_o_2;
input a_rd_en_i_2;
input [08:00] b_wr_a_i_2;
input [31:00] b_wr_d_i_2;
input b_wr_en_i_2;
output [31:00] b_rd_d_o_2;
input b_rd_en_i_2;
input [08:00] a_rd_a_i_3;
output [31:00] a_rd_d_o_3;
input a_rd_en_i_3;
input [08:00] b_wr_a_i_3;
input [31:00] b_wr_d_i_3;
input b_wr_en_i_3;
output [31:00] b_rd_d_o_3;
input b_rd_en_i_3;
//----------------------------------------------------------------
//
// 4 x 512 DWs Buffer Banks (512 x 32 bits + 512 x 4 bits)
// 1 each for IO, Mem32, Mem64 and EROM
//----------------------------------------------------------------
RAMB36 #(
.DOA_REG(1), // Optional output registers on A port (0 or 1)
.DOB_REG(1), // Optional output registers on B port (0 or 1)
.INIT_A(36'h000000000), // Initial values on A output port
.INIT_B(36'h000000000), // Initial values on B output port
.RAM_EXTENSION_A("NONE"), // "UPPER", "LOWER" or "NONE" when cascaded
.RAM_EXTENSION_B("NONE"), // "UPPER", "LOWER" or "NONE" when cascaded
.READ_WIDTH_A(36), // Valid values are 1, 2, 4, 9, 18, or 36
.READ_WIDTH_B(36), // Valid values are 1, 2, 4, 9, 18, or 36
.SIM_COLLISION_CHECK("ALL"), // Collision check enable "ALL", "WARNING_ONLY",
// "GENERATE_X_ONLY" or "NONE
.SRVAL_A(36'h000000000), // Set/Reset value for A port output
.SRVAL_B(36'h000000000), // Set/Reset value for B port output
.WRITE_MODE_A("WRITE_FIRST"), // "WRITE_FIRST", "READ_FIRST", or "NO_CHANGE
.WRITE_MODE_B("WRITE_FIRST"), // "WRITE_FIRST", "READ_FIRST", or "NO_CHANGE
.WRITE_WIDTH_A(36), // Valid values are 1, 2, 4, 9, 18, or 36
.WRITE_WIDTH_B(36), // Valid values are 1, 2, 4, 9, 18, or 36
// The following INIT_xx declarations specify the initial contents of the RAM
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
// The next set of INITP_xx are for the parity bits
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000)
) ep_io_mem_inst (
.DOA(a_rd_d_o_0[31:0]), // 32-bit A port data output
.DOB(b_rd_d_o_0[31:0]), // 32-bit B port data output
.DOPA(), // 4-bit A port parity data output
.DOPB(), // 4-bit B port parity data output
.ADDRA({1'b0,a_rd_a_i_0[8:0],6'b0}), // 16-bit A port address input
.ADDRB({1'b0,b_wr_a_i_0[8:0],6'b0}), // 16-bit B port address input
.CLKA(clk), // 1-bit A port clock input
.CLKB(clk), // 1-bit B port clock input
.DIA(32'b0), // 32-bit A port data input
.DIB(b_wr_d_i_0[31:0]), // 32-bit B port data input
.DIPA(4'b0000), // 4-bit A port parity data input
.DIPB(4'b0), // 4-bit B port parity data input
.ENA(a_rd_en_i_0), // 1-bit A port enable input
.ENB(b_rd_en_i_0), // 1-bit B port enable input
.REGCEA(1'b1), // 1-bit A port register enable input
.REGCEB(1'b1), // 1-bit B port register enable input
.SSRA(1'b0), // 1-bit A port set/reset input
.SSRB(1'b0), // 1-bit B port set/reset input
.WEA(4'b0), // 4-bit A port write enable input
.WEB({b_wr_en_i_0, b_wr_en_i_0, b_wr_en_i_0, b_wr_en_i_0}), // 4-bit B port write enable input
.CASCADEINLATA (1'b0),
.CASCADEINREGA (1'b0),
.CASCADEOUTLATA (),
.CASCADEOUTREGA (),
.CASCADEINLATB (1'b0),
.CASCADEINREGB (1'b0),
.CASCADEOUTLATB (),
.CASCADEOUTREGB ()
);
RAMB36 #(
.DOA_REG(1), // Optional output registers on A port (0 or 1)
.DOB_REG(1), // Optional output registers on B port (0 or 1)
.INIT_A(36'h000000000), // Initial values on A output port
.INIT_B(36'h000000000), // Initial values on B output port
.RAM_EXTENSION_A("NONE"), // "UPPER", "LOWER" or "NONE" when cascaded
.RAM_EXTENSION_B("NONE"), // "UPPER", "LOWER" or "NONE" when cascaded
.READ_WIDTH_A(36), // Valid values are 1, 2, 4, 9, 18, or 36
.READ_WIDTH_B(36), // Valid values are 1, 2, 4, 9, 18, or 36
.SIM_COLLISION_CHECK("ALL"), // Collision check enable "ALL", "WARNING_ONLY",
// "GENERATE_X_ONLY" or "NONE
.SRVAL_A(36'h000000000), // Set/Reset value for A port output
.SRVAL_B(36'h000000000), // Set/Reset value for B port output
.WRITE_MODE_A("WRITE_FIRST"), // "WRITE_FIRST", "READ_FIRST", or "NO_CHANGE
.WRITE_MODE_B("WRITE_FIRST"), // "WRITE_FIRST", "READ_FIRST", or "NO_CHANGE
.WRITE_WIDTH_A(36), // Valid values are 1, 2, 4, 9, 18, or 36
.WRITE_WIDTH_B(36), // Valid values are 1, 2, 4, 9, 18, or 36
// The following INIT_xx declarations specify the initial contents of the RAM
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
// The next set of INITP_xx are for the parity bits
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000)
) ep_mem32_inst (
.DOA(a_rd_d_o_1[31:0]), // 32-bit A port data output
.DOB(b_rd_d_o_1[31:0]), // 32-bit B port data output
.DOPA(), // 4-bit A port parity data output
.DOPB(), // 4-bit B port parity data output
.ADDRA({1'b0,a_rd_a_i_1[8:0],6'b0}), // 16-bit A port address input
.ADDRB({1'b0,b_wr_a_i_1[8:0],6'b0}), // 16-bit B port address input
.CLKA(clk), // 1-bit A port clock input
.CLKB(clk), // 1-bit B port clock input
.DIA(32'b0), // 32-bit A port data input
.DIB(b_wr_d_i_1[31:0]), // 32-bit B port data input
.DIPA(4'b0000), // 4-bit A port parity data input
.DIPB(4'b0), // 4-bit B port parity data input
.ENA(a_rd_en_i_1), // 1-bit A port enable input
.ENB(b_rd_en_i_1), // 1-bit B port enable input
.REGCEA(1'b1), // 1-bit A port register enable input
.REGCEB(1'b1), // 1-bit B port register enable input
.SSRA(1'b0), // 1-bit A port set/reset input
.SSRB(1'b0), // 1-bit B port set/reset input
.WEA(4'b0), // 4-bit A port write enable input
.WEB({b_wr_en_i_1, b_wr_en_i_1, b_wr_en_i_1, b_wr_en_i_1}), // 4-bit B port write enable input
.CASCADEINLATA (1'b0),
.CASCADEINREGA (1'b0),
.CASCADEOUTLATA (),
.CASCADEOUTREGA (),
.CASCADEINLATB (1'b0),
.CASCADEINREGB (1'b0),
.CASCADEOUTLATB (),
.CASCADEOUTREGB ()
);
RAMB36 #(
.DOA_REG(1), // Optional output registers on A port (0 or 1)
.DOB_REG(1), // Optional output registers on B port (0 or 1)
.INIT_A(36'h000000000), // Initial values on A output port
.INIT_B(36'h000000000), // Initial values on B output port
.RAM_EXTENSION_A("NONE"), // "UPPER", "LOWER" or "NONE" when cascaded
.RAM_EXTENSION_B("NONE"), // "UPPER", "LOWER" or "NONE" when cascaded
.READ_WIDTH_A(36), // Valid values are 1, 2, 4, 9, 18, or 36
.READ_WIDTH_B(36), // Valid values are 1, 2, 4, 9, 18, or 36
.SIM_COLLISION_CHECK("ALL"), // Collision check enable "ALL", "WARNING_ONLY",
// "GENERATE_X_ONLY" or "NONE
.SRVAL_A(36'h000000000), // Set/Reset value for A port output
.SRVAL_B(36'h000000000), // Set/Reset value for B port output
.WRITE_MODE_A("WRITE_FIRST"), // "WRITE_FIRST", "READ_FIRST", or "NO_CHANGE
.WRITE_MODE_B("WRITE_FIRST"), // "WRITE_FIRST", "READ_FIRST", or "NO_CHANGE
.WRITE_WIDTH_A(36), // Valid values are 1, 2, 4, 9, 18, or 36
.WRITE_WIDTH_B(36), // Valid values are 1, 2, 4, 9, 18, or 36
// The following INIT_xx declarations specify the initial contents of the RAM
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
// The next set of INITP_xx are for the parity bits
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000)
) ep_mem64_inst (
.DOA(a_rd_d_o_2[31:0]), // 32-bit A port data output
.DOB(b_rd_d_o_2[31:0]), // 32-bit B port data output
.DOPA(), // 4-bit A port parity data output
.DOPB(), // 4-bit B port parity data output
.ADDRA({1'b0,a_rd_a_i_2[8:0],6'b0}), // 16-bit A port address input
.ADDRB({1'b0,b_wr_a_i_2[8:0],6'b0}), // 16-bit B port address input
.CLKA(clk), // 1-bit A port clock input
.CLKB(clk), // 1-bit B port clock input
.DIA(32'b0), // 32-bit A port data input
.DIB(b_wr_d_i_2[31:0]), // 32-bit B port data input
.DIPA(4'b0000), // 4-bit A port parity data input
.DIPB(4'b0), // 4-bit B port parity data input
.ENA(a_rd_en_i_2), // 1-bit A port enable input
.ENB(b_rd_en_i_2), // 1-bit B port enable input
.REGCEA(1'b1), // 1-bit A port register enable input
.REGCEB(1'b1), // 1-bit B port register enable input
.SSRA(1'b0), // 1-bit A port set/reset input
.SSRB(1'b0), // 1-bit B port set/reset input
.WEA(4'b0), // 4-bit A port write enable input
.WEB({b_wr_en_i_2, b_wr_en_i_2, b_wr_en_i_2, b_wr_en_i_2}), // 4-bit B port write enable input
.CASCADEINLATA (1'b0),
.CASCADEINREGA (1'b0),
.CASCADEOUTLATA (),
.CASCADEOUTREGA (),
.CASCADEINLATB (1'b0),
.CASCADEINREGB (1'b0),
.CASCADEOUTLATB (),
.CASCADEOUTREGB ()
);
RAMB36 #(
.DOA_REG(1), // Optional output registers on A port (0 or 1)
.DOB_REG(1), // Optional output registers on B port (0 or 1)
.INIT_A(36'h000000000), // Initial values on A output port
.INIT_B(36'h000000000), // Initial values on B output port
.RAM_EXTENSION_A("NONE"), // "UPPER", "LOWER" or "NONE" when cascaded
.RAM_EXTENSION_B("NONE"), // "UPPER", "LOWER" or "NONE" when cascaded
.READ_WIDTH_A(36), // Valid values are 1, 2, 4, 9, 18, or 36
.READ_WIDTH_B(36), // Valid values are 1, 2, 4, 9, 18, or 36
.SIM_COLLISION_CHECK("ALL"), // Collision check enable "ALL", "WARNING_ONLY",
// "GENERATE_X_ONLY" or "NONE
.SRVAL_A(36'h000000000), // Set/Reset value for A port output
.SRVAL_B(36'h000000000), // Set/Reset value for B port output
.WRITE_MODE_A("WRITE_FIRST"), // "WRITE_FIRST", "READ_FIRST", or "NO_CHANGE
.WRITE_MODE_B("WRITE_FIRST"), // "WRITE_FIRST", "READ_FIRST", or "NO_CHANGE
.WRITE_WIDTH_A(36), // Valid values are 1, 2, 4, 9, 18, or 36
.WRITE_WIDTH_B(36), // Valid values are 1, 2, 4, 9, 18, or 36
// The following INIT_xx declarations specify the initial contents of the RAM
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
// The next set of INITP_xx are for the parity bits
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000)
) ep_mem_erom_inst (
.DOA(a_rd_d_o_3[31:0]), // 32-bit A port data output
.DOB(b_rd_d_o_3[31:0]), // 32-bit B port data output
.DOPA(), // 4-bit A port parity data output
.DOPB(), // 4-bit B port parity data output
.ADDRA({1'b0,a_rd_a_i_3[8:0],6'b0}), // 16-bit A port address input
.ADDRB({1'b0,b_wr_a_i_3[8:0],6'b0}), // 16-bit B port address input
.CLKA(clk), // 1-bit A port clock input
.CLKB(clk), // 1-bit B port clock input
.DIA(32'b0), // 32-bit A port data input
.DIB(b_wr_d_i_3[31:0]), // 32-bit B port data input
.DIPA(4'b0000), // 4-bit A port parity data input
.DIPB(4'b0), // 4-bit B port parity data input
.ENA(a_rd_en_i_3), // 1-bit A port enable input
.ENB(b_rd_en_i_3), // 1-bit B port enable input
.REGCEA(1'b1), // 1-bit A port register enable input
.REGCEB(1'b1), // 1-bit B port register enable input
.SSRA(1'b0), // 1-bit A port set/reset input
.SSRB(1'b0), // 1-bit B port set/reset input
.WEA(4'b0), // 4-bit A port write enable input
.WEB({b_wr_en_i_3, b_wr_en_i_3, b_wr_en_i_3, b_wr_en_i_3}), // 4-bit B port write enable input
.CASCADEINLATA (1'b0),
.CASCADEINREGA (1'b0),
.CASCADEOUTLATA (),
.CASCADEOUTREGA (),
.CASCADEINLATB (1'b0),
.CASCADEINREGB (1'b0),
.CASCADEOUTLATB (),
.CASCADEOUTREGB ()
);
endmodule
|
module m_port_ultra_processor_array (
input clk,
input reset_n,
input processorEnable,
input [8191:0] convexCloud,
output [4095:0] convexHull1,
output [4095:0] convexHull2,
output [7:0] convexHullSize1,
output [7:0] convexHullSize2
);
// Wires -- processor inputs
wire [4095:0] processorConvexCloud1;
wire [4095:0] processorConvexCloud2;
wire [8:0] processorConvexCloudSize1;
wire [8:0] processorConvexCloudSize2;
// Declare processor unit 1
m_port_ultra_quickhull quickhullProcessor1 (
.clk (clk),
.reset_n (reset_n),
.processorEnable (processorEnable),
.points (processorConvexCloud1),
.size (processorConvexCloudSize1),
.convexPointsOutput (convexHull1),
.convexSetSizeOutput (convexHullSize1)
);
// Declare processor unit 2
m_port_ultra_quickhull quickhullProcessor2 (
.clk (clk),
.reset_n (reset_n),
.processorEnable (processorEnable),
.points (processorConvexCloud2),
.size (processorConvexCloudSize2),
.convexPointsOutput (convexHull2),
.convexSetSizeOutput (convexHullSize2)
);
endmodule
|
module axis_async_frame_fifo_64 #
(
parameter ADDR_WIDTH = 12,
parameter DATA_WIDTH = 64,
parameter KEEP_WIDTH = (DATA_WIDTH/8),
parameter DROP_WHEN_FULL = 0
)
(
/*
* AXI input
*/
input wire input_clk,
input wire input_rst,
input wire [DATA_WIDTH-1:0] input_axis_tdata,
input wire [KEEP_WIDTH-1:0] input_axis_tkeep,
input wire input_axis_tvalid,
output wire input_axis_tready,
input wire input_axis_tlast,
input wire input_axis_tuser,
/*
* AXI output
*/
input wire output_clk,
input wire output_rst,
output wire [DATA_WIDTH-1:0] output_axis_tdata,
output wire [KEEP_WIDTH-1:0] output_axis_tkeep,
output wire output_axis_tvalid,
input wire output_axis_tready,
output wire output_axis_tlast
);
reg [ADDR_WIDTH:0] wr_ptr = {ADDR_WIDTH+1{1'b0}}, wr_ptr_next;
reg [ADDR_WIDTH:0] wr_ptr_cur = {ADDR_WIDTH+1{1'b0}};
reg [ADDR_WIDTH:0] wr_ptr_gray = {ADDR_WIDTH+1{1'b0}};
reg [ADDR_WIDTH:0] rd_ptr = {ADDR_WIDTH+1{1'b0}}, rd_ptr_next;
reg [ADDR_WIDTH:0] rd_ptr_gray = {ADDR_WIDTH+1{1'b0}};
reg [ADDR_WIDTH:0] wr_ptr_gray_sync1 = {ADDR_WIDTH+1{1'b0}};
reg [ADDR_WIDTH:0] wr_ptr_gray_sync2 = {ADDR_WIDTH+1{1'b0}};
reg [ADDR_WIDTH:0] rd_ptr_gray_sync1 = {ADDR_WIDTH+1{1'b0}};
reg [ADDR_WIDTH:0] rd_ptr_gray_sync2 = {ADDR_WIDTH+1{1'b0}};
reg input_rst_sync1 = 1;
reg input_rst_sync2 = 1;
reg output_rst_sync1 = 1;
reg output_rst_sync2 = 1;
reg drop_frame = 1'b0;
reg [DATA_WIDTH+KEEP_WIDTH+2-1:0] data_out_reg = {1'b0, {KEEP_WIDTH{1'b0}}, {DATA_WIDTH{1'b0}}};
//(* RAM_STYLE="BLOCK" *)
reg [DATA_WIDTH+KEEP_WIDTH+2-1:0] mem[(2**ADDR_WIDTH)-1:0];
reg output_read = 1'b0;
reg output_axis_tvalid_reg = 1'b0;
wire [DATA_WIDTH+KEEP_WIDTH+2-1:0] data_in = {input_axis_tlast, input_axis_tkeep, input_axis_tdata};
// full when first TWO MSBs do NOT match, but rest matches
// (gray code equivalent of first MSB different but rest same)
wire full = ((wr_ptr_gray[ADDR_WIDTH] != rd_ptr_gray_sync2[ADDR_WIDTH]) &&
(wr_ptr_gray[ADDR_WIDTH-1] != rd_ptr_gray_sync2[ADDR_WIDTH-1]) &&
(wr_ptr_gray[ADDR_WIDTH-2:0] == rd_ptr_gray_sync2[ADDR_WIDTH-2:0]));
// empty when pointers match exactly
wire empty = rd_ptr_gray == wr_ptr_gray_sync2;
// overflow in single packet
wire full_cur = ((wr_ptr[ADDR_WIDTH] != wr_ptr_cur[ADDR_WIDTH]) &&
(wr_ptr[ADDR_WIDTH-1:0] == wr_ptr_cur[ADDR_WIDTH-1:0]));
wire write = input_axis_tvalid & (~full | DROP_WHEN_FULL);
wire read = (output_axis_tready | ~output_axis_tvalid_reg) & ~empty;
assign {output_axis_tlast, output_axis_tkeep, output_axis_tdata} = data_out_reg;
assign input_axis_tready = (~full | DROP_WHEN_FULL);
assign output_axis_tvalid = output_axis_tvalid_reg;
// reset synchronization
always @(posedge input_clk or posedge input_rst or posedge output_rst) begin
if (input_rst | output_rst) begin
input_rst_sync1 <= 1;
input_rst_sync2 <= 1;
end else begin
input_rst_sync1 <= 0;
input_rst_sync2 <= input_rst_sync1;
end
end
always @(posedge output_clk or posedge input_rst or posedge output_rst) begin
if (input_rst | output_rst) begin
output_rst_sync1 <= 1;
output_rst_sync2 <= 1;
end else begin
output_rst_sync1 <= 0;
output_rst_sync2 <= output_rst_sync1;
end
end
// write
always @(posedge input_clk or posedge input_rst_sync2) begin
if (input_rst_sync2) begin
wr_ptr <= 0;
wr_ptr_cur <= 0;
wr_ptr_gray <= 0;
drop_frame <= 0;
end else if (write) begin
if (full | full_cur | drop_frame) begin
// buffer full, hold current pointer, drop packet at end
drop_frame <= 1;
if (input_axis_tlast) begin
wr_ptr_cur <= wr_ptr;
drop_frame <= 0;
end
end else begin
mem[wr_ptr_cur[ADDR_WIDTH-1:0]] <= data_in;
wr_ptr_cur <= wr_ptr_cur + 1;
if (input_axis_tlast) begin
if (input_axis_tuser) begin
// bad packet, reset write pointer
wr_ptr_cur <= wr_ptr;
end else begin
// good packet, push new write pointer
wr_ptr_next = wr_ptr_cur + 1;
wr_ptr <= wr_ptr_next;
wr_ptr_gray <= wr_ptr_next ^ (wr_ptr_next >> 1);
end
end
end
end
end
// pointer synchronization
always @(posedge input_clk or posedge input_rst_sync2) begin
if (input_rst_sync2) begin
rd_ptr_gray_sync1 <= 0;
rd_ptr_gray_sync2 <= 0;
end else begin
rd_ptr_gray_sync1 <= rd_ptr_gray;
rd_ptr_gray_sync2 <= rd_ptr_gray_sync1;
end
end
// read
always @(posedge output_clk or posedge output_rst_sync2) begin
if (output_rst_sync2) begin
rd_ptr <= 0;
rd_ptr_gray <= 0;
end else if (read) begin
data_out_reg <= mem[rd_ptr[ADDR_WIDTH-1:0]];
rd_ptr_next = rd_ptr + 1;
rd_ptr <= rd_ptr_next;
rd_ptr_gray <= rd_ptr_next ^ (rd_ptr_next >> 1);
end
end
// pointer synchronization
always @(posedge output_clk or posedge output_rst_sync2) begin
if (output_rst_sync2) begin
wr_ptr_gray_sync1 <= 0;
wr_ptr_gray_sync2 <= 0;
end else begin
wr_ptr_gray_sync1 <= wr_ptr_gray;
wr_ptr_gray_sync2 <= wr_ptr_gray_sync1;
end
end
// source ready output
always @(posedge output_clk or posedge output_rst_sync2) begin
if (output_rst_sync2) begin
output_axis_tvalid_reg <= 1'b0;
end else if (output_axis_tready | ~output_axis_tvalid_reg) begin
output_axis_tvalid_reg <= ~empty;
end else begin
output_axis_tvalid_reg <= output_axis_tvalid_reg;
end
end
endmodule
|
module ptp_tag_insert #
(
parameter DATA_WIDTH = 64,
parameter KEEP_WIDTH = DATA_WIDTH/8,
parameter TAG_WIDTH = 16,
parameter TAG_OFFSET = 1,
parameter USER_WIDTH = TAG_WIDTH+TAG_OFFSET
)
(
input wire clk,
input wire rst,
/*
* AXI input
*/
input wire [DATA_WIDTH-1:0] s_axis_tdata,
input wire [KEEP_WIDTH-1:0] s_axis_tkeep,
input wire s_axis_tvalid,
output wire s_axis_tready,
input wire s_axis_tlast,
input wire [USER_WIDTH-1:0] s_axis_tuser,
/*
* AXI output
*/
output wire [DATA_WIDTH-1:0] m_axis_tdata,
output wire [KEEP_WIDTH-1:0] m_axis_tkeep,
output wire m_axis_tvalid,
input wire m_axis_tready,
output wire m_axis_tlast,
output wire [USER_WIDTH-1:0] m_axis_tuser,
/*
* Tag input
*/
input wire [TAG_WIDTH-1:0] s_axis_tag,
input wire s_axis_tag_valid,
output wire s_axis_tag_ready
);
reg [TAG_WIDTH-1:0] tag_reg = {TAG_WIDTH{1'b0}};
reg tag_valid_reg = 1'b0;
reg [USER_WIDTH-1:0] user;
assign s_axis_tready = m_axis_tready && tag_valid_reg;
assign m_axis_tdata = s_axis_tdata;
assign m_axis_tkeep = s_axis_tkeep;
assign m_axis_tvalid = s_axis_tvalid && tag_valid_reg;
assign m_axis_tlast = s_axis_tlast;
assign m_axis_tuser = user;
assign s_axis_tag_ready = !tag_valid_reg;
always @* begin
user = s_axis_tuser;
user[TAG_OFFSET +: TAG_WIDTH] = tag_reg;
end
always @(posedge clk) begin
if (tag_valid_reg) begin
if (s_axis_tvalid && s_axis_tready && s_axis_tlast) begin
tag_valid_reg <= 1'b0;
end
end else begin
tag_reg <= s_axis_tag;
tag_valid_reg <= s_axis_tag_valid;
end
if (rst) begin
tag_valid_reg <= 1'b0;
end
end
endmodule
|
module jtag_lm32 (
input JTCK,
input JTDI,
output JTDO2,
input JSHIFT,
input JUPDATE,
input JRSTN,
input JCE2,
input JTAGREG_ENABLE,
input CONTROL_DATAN,
output REG_UPDATE,
input [7:0] REG_D,
input [2:0] REG_ADDR_D,
output [7:0] REG_Q,
output [2:0] REG_ADDR_Q
);
/////////////////////////////////////////////////////
// Internal nets and registers
/////////////////////////////////////////////////////
wire [9:0] tdibus;
/////////////////////////////////////////////////////
// Instantiations
/////////////////////////////////////////////////////
TYPEA DATA_BIT0 (
.CLK(JTCK),
.RESET_N(JRSTN),
.CLKEN(clk_enable),
.TDI(JTDI),
.TDO(tdibus[0]),
.DATA_OUT(REG_Q[0]),
.DATA_IN(REG_D[0]),
.CAPTURE_DR(captureDr),
.UPDATE_DR(JUPDATE)
);
TYPEA DATA_BIT1 (
.CLK(JTCK),
.RESET_N(JRSTN),
.CLKEN(clk_enable),
.TDI(tdibus[0]),
.TDO(tdibus[1]),
.DATA_OUT(REG_Q[1]),
.DATA_IN(REG_D[1]),
.CAPTURE_DR(captureDr),
.UPDATE_DR(JUPDATE)
);
TYPEA DATA_BIT2 (
.CLK(JTCK),
.RESET_N(JRSTN),
.CLKEN(clk_enable),
.TDI(tdibus[1]),
.TDO(tdibus[2]),
.DATA_OUT(REG_Q[2]),
.DATA_IN(REG_D[2]),
.CAPTURE_DR(captureDr),
.UPDATE_DR(JUPDATE)
);
TYPEA DATA_BIT3 (
.CLK(JTCK),
.RESET_N(JRSTN),
.CLKEN(clk_enable),
.TDI(tdibus[2]),
.TDO(tdibus[3]),
.DATA_OUT(REG_Q[3]),
.DATA_IN(REG_D[3]),
.CAPTURE_DR(captureDr),
.UPDATE_DR(JUPDATE)
);
TYPEA DATA_BIT4 (
.CLK(JTCK),
.RESET_N(JRSTN),
.CLKEN(clk_enable),
.TDI(tdibus[3]),
.TDO(tdibus[4]),
.DATA_OUT(REG_Q[4]),
.DATA_IN(REG_D[4]),
.CAPTURE_DR(captureDr),
.UPDATE_DR(JUPDATE)
);
TYPEA DATA_BIT5 (
.CLK(JTCK),
.RESET_N(JRSTN),
.CLKEN(clk_enable),
.TDI(tdibus[4]),
.TDO(tdibus[5]),
.DATA_OUT(REG_Q[5]),
.DATA_IN(REG_D[5]),
.CAPTURE_DR(captureDr),
.UPDATE_DR(JUPDATE)
);
TYPEA DATA_BIT6 (
.CLK(JTCK),
.RESET_N(JRSTN),
.CLKEN(clk_enable),
.TDI(tdibus[5]),
.TDO(tdibus[6]),
.DATA_OUT(REG_Q[6]),
.DATA_IN(REG_D[6]),
.CAPTURE_DR(captureDr),
.UPDATE_DR(JUPDATE)
);
TYPEA DATA_BIT7 (
.CLK(JTCK),
.RESET_N(JRSTN),
.CLKEN(clk_enable),
.TDI(tdibus[6]),
.TDO(tdibus[7]),
.DATA_OUT(REG_Q[7]),
.DATA_IN(REG_D[7]),
.CAPTURE_DR(captureDr),
.UPDATE_DR(JUPDATE)
);
TYPEA ADDR_BIT0 (
.CLK(JTCK),
.RESET_N(JRSTN),
.CLKEN(clk_enable),
.TDI(tdibus[7]),
.TDO(tdibus[8]),
.DATA_OUT(REG_ADDR_Q[0]),
.DATA_IN(REG_ADDR_D[0]),
.CAPTURE_DR(captureDr),
.UPDATE_DR(JUPDATE)
);
TYPEA ADDR_BIT1 (
.CLK(JTCK),
.RESET_N(JRSTN),
.CLKEN(clk_enable),
.TDI(tdibus[8]),
.TDO(tdibus[9]),
.DATA_OUT(REG_ADDR_Q[1]),
.DATA_IN(REG_ADDR_D[1]),
.CAPTURE_DR(captureDr),
.UPDATE_DR(JUPDATE)
);
TYPEA ADDR_BIT2 (
.CLK(JTCK),
.RESET_N(JRSTN),
.CLKEN(clk_enable),
.TDI(tdibus[9]),
.TDO(JTDO2),
.DATA_OUT(REG_ADDR_Q[2]),
.DATA_IN(REG_ADDR_D[2]),
.CAPTURE_DR(captureDr),
.UPDATE_DR(JUPDATE)
);
/////////////////////////////////////////////////////
// Combinational logic
/////////////////////////////////////////////////////
assign clk_enable = JTAGREG_ENABLE & JCE2;
assign captureDr = !JSHIFT & JCE2;
// JCE2 is only active during shift
assign REG_UPDATE = JTAGREG_ENABLE & JUPDATE;
endmodule
|
module axis_bayer_extractor #
(
parameter integer C_PIXEL_WIDTH = 8,
parameter integer C_BYPASS = 0,
parameter integer C_COL_ODD = 0,
parameter integer C_ROW_ODD = 0
) (
input wire clk,
input wire resetn,
input wire s_axis_tvalid,
input wire [C_PIXEL_WIDTH-1:0] s_axis_tdata,
input wire s_axis_tuser,
input wire s_axis_tlast,
output wire s_axis_tready,
output wire m_axis_tvalid,
output wire [C_PIXEL_WIDTH-1:0] m_axis_tdata,
output wire m_axis_tuser,
output wire m_axis_tlast,
input wire m_axis_tready
);
generate
if (C_BYPASS == 1) begin: direct_connect
assign m_axis_tvalid = s_axis_tvalid;
assign m_axis_tdata[C_PIXEL_WIDTH-1:0] = s_axis_tdata[C_PIXEL_WIDTH-1:0];
assign m_axis_tuser = s_axis_tuser;
assign m_axis_tlast = s_axis_tlast;
assign s_axis_tready = m_axis_tready;
end
else begin: extract_quater
reg r_m_axis_tvalid;
assign m_axis_tvalid = r_m_axis_tvalid;
reg [C_PIXEL_WIDTH-1:0] r_m_axis_tdata;
assign m_axis_tdata[C_PIXEL_WIDTH-1:0] = r_m_axis_tdata;
reg r_m_axis_tuser;
assign m_axis_tuser = r_m_axis_tuser;
reg r_m_axis_tlast;
assign m_axis_tlast = r_m_axis_tlast;
wire snext;
assign snext = s_axis_tvalid && s_axis_tready;
wire mnext;
assign mnext = m_axis_tvalid && m_axis_tready;
reg sline_lsb;
reg spixel_lsb;
always @ (posedge clk) begin
if (resetn == 1'b0)
sline_lsb <= 0;
else if (snext && s_axis_tlast)
sline_lsb <= ~sline_lsb;
end
always @ (posedge clk) begin
if (resetn == 1'b0)
spixel_lsb <= 0;
else if (snext)
spixel_lsb <= ~spixel_lsb;
end
always @ (posedge clk) begin
if (resetn == 1'b0)
r_m_axis_tdata <= 0;
else if (snext
&& (spixel_lsb == C_COL_ODD)
&& (sline_lsb == C_ROW_ODD))
r_m_axis_tdata <= s_axis_tdata;
end
always @ (posedge clk) begin
if (resetn == 1'b0)
r_m_axis_tvalid <= 0;
else if (snext
&& (spixel_lsb == 1)
&& (sline_lsb == C_ROW_ODD))
r_m_axis_tvalid <= 1;
else if (m_axis_tready)
r_m_axis_tvalid <= 0;
end
always @ (posedge clk) begin
if (resetn == 1'b0)
r_m_axis_tlast <= 0;
else if (snext
&& (spixel_lsb == 1)
&& (sline_lsb == C_ROW_ODD))
r_m_axis_tlast <= s_axis_tlast;
end
always @ (posedge clk) begin
if (resetn == 1'b0)
r_m_axis_tuser <= 0;
else if (snext
&& s_axis_tuser)
r_m_axis_tuser <= 1;
else if (mnext)
r_m_axis_tuser <= 0;
end
assign s_axis_tready = (~m_axis_tvalid || m_axis_tready);
end
endgenerate
endmodule
|
module forp(
reset,
sysclk
);
input reset, sysclk;
wire reset;
wire sysclk;
reg selection;
reg [6:0] egg_timer;
always @(posedge reset or posedge sysclk) begin : P1
reg [31:0] timer_var = 0;
reg [31:0] a, i, j, k;
reg [31:0] zz5;
reg [511:0] zz;
if(reset == 1'b 1) begin
selection <= 1'b 1;
timer_var = 2;
egg_timer <= {7{1'b0}};
end else begin
// pulse only lasts for once cycle
selection <= 1'b 0;
egg_timer <= {7{1'b1}};
for (i=0; i <= j * k; i = i + 1) begin
a = a + i;
for (k=a - 9; k >= -14; k = k - 1) begin
zz5 = zz[31 + k:k];
end
// k
end
// i
end
end
endmodule
|
module alu( input [31:0] A, B,
input [2:0] F,
output reg [31:0] Y, output Zero);
always @ ( * )
case (F[2:0])
3'b000: Y <= A & B;
3'b001: Y <= A | B;
3'b010: Y <= A + B;
//3'b011: Y <= 0; // not used
3'b011: Y <= A & ~B;
3'b101: Y <= A + ~B;
3'b110: Y <= A - B;
3'b111: Y <= A < B ? 1:0;
default: Y <= 0; //default to 0, should not happen
endcase
assign Zero = (Y == 32'b0);
endmodule
|
module regfile(input clk,
input we3,
input [4:0] ra1, ra2, wa3,
input [31:0] wd3,
output [31:0] rd1, rd2);
reg [31:0] rf[31:0];
// three ported register file
// read two ports combinationally
// write third port on rising edge of clock
// register 0 hardwired to 0
always @(posedge clk)
if (we3) rf[wa3] <= wd3;
assign rd1 = (ra1 != 0) ? rf[ra1] : 0;
assign rd2 = (ra2 != 0) ? rf[ra2] : 0;
endmodule
|
module sl2(input [31:0] a,
output [31:0] y);
// shift left by 2
assign y = {a[29:0], 2'b00};
endmodule
|
module signext(input [15:0] a,
output [31:0] y);
assign y = {{16{a[15]}}, a};
endmodule
|
module flopr #(parameter WIDTH = 8)
(input clk, reset,
input [WIDTH-1:0] d,
output reg [WIDTH-1:0] q);
always @(posedge clk, posedge reset)
if (reset) q <= 0;
else q <= d;
endmodule
|
module flopenr #(parameter WIDTH = 8)
(input clk, reset,
input en,
input [WIDTH-1:0] d,
output reg [WIDTH-1:0] q);
always @(posedge clk, posedge reset)
if (reset) q <= 0;
else if (en) q <= d;
endmodule
|
module mux2 #(parameter WIDTH = 8)
(input [WIDTH-1:0] d0, d1,
input s,
output [WIDTH-1:0] y);
assign y = s ? d1 : d0;
endmodule
|
module mux3 #(parameter WIDTH = 8)
(input [WIDTH-1:0] d0, d1, d2,
input [1:0] s,
output [WIDTH-1:0] y);
assign #1 y = s[1] ? d2 : (s[0] ? d1 : d0);
endmodule
|
module mux4 #(parameter WIDTH = 8)
(input [WIDTH-1:0] d0, d1, d2, d3,
input [1:0] s,
output reg [WIDTH-1:0] y);
always @( * )
case(s)
2'b00: y <= d0;
2'b01: y <= d1;
2'b10: y <= d2;
2'b11: y <= d3;
endcase
endmodule
|
module outputs)
wire elink_access_inb; // From ewrapper_link_top of ewrapper_link_top.v
wire elink_access_outb; // From axi_elink_if of axi_elink_if.v
wire elink_cclk_enb; // From axi_elink_if of axi_elink_if.v
wire [1:0] elink_clk_div; // From axi_elink_if of axi_elink_if.v
wire [3:0] elink_ctrlmode_inb; // From ewrapper_link_top of ewrapper_link_top.v
wire [3:0] elink_ctrlmode_outb; // From axi_elink_if of axi_elink_if.v
wire [31:0] elink_data_inb; // From ewrapper_link_top of ewrapper_link_top.v
wire [31:0] elink_data_outb; // From axi_elink_if of axi_elink_if.v
wire [1:0] elink_datamode_inb; // From ewrapper_link_top of ewrapper_link_top.v
wire [1:0] elink_datamode_outb; // From axi_elink_if of axi_elink_if.v
wire elink_disable; // From axi_elink_if of axi_elink_if.v
wire [31:0] elink_dstaddr_outb; // From axi_elink_if of axi_elink_if.v
wire elink_rd_wait_inb; // From ewrapper_link_top of ewrapper_link_top.v
wire elink_rd_wait_outb; // From axi_elink_if of axi_elink_if.v
wire [31:0] elink_srcaddr_inb; // From ewrapper_link_top of ewrapper_link_top.v
wire [31:0] elink_srcaddr_outb; // From axi_elink_if of axi_elink_if.v
wire elink_wr_wait_inb; // From ewrapper_link_top of ewrapper_link_top.v
wire elink_wr_wait_outb; // From axi_elink_if of axi_elink_if.v
wire elink_write_inb; // From ewrapper_link_top of ewrapper_link_top.v
wire elink_write_outb; // From axi_elink_if of axi_elink_if.v
wire emaxi_access_inb; // From axi_master of axi_master.v
wire emaxi_access_outb; // From axi_elink_if of axi_elink_if.v
wire [3:0] emaxi_ctrlmode_inb; // From axi_master of axi_master.v
wire [3:0] emaxi_ctrlmode_outb; // From axi_elink_if of axi_elink_if.v
wire [31:0] emaxi_data_inb; // From axi_master of axi_master.v
wire [31:0] emaxi_data_outb; // From axi_elink_if of axi_elink_if.v
wire [1:0] emaxi_datamode_inb; // From axi_master of axi_master.v
wire [1:0] emaxi_datamode_outb; // From axi_elink_if of axi_elink_if.v
wire [31:0] emaxi_dstaddr_inb; // From axi_master of axi_master.v
wire [31:0] emaxi_dstaddr_outb; // From axi_elink_if of axi_elink_if.v
wire emaxi_rd_wait_inb; // From axi_master of axi_master.v
wire [31:0] emaxi_srcaddr_inb; // From axi_master of axi_master.v
wire [31:0] emaxi_srcaddr_outb; // From axi_elink_if of axi_elink_if.v
wire emaxi_wr_wait_inb; // From axi_master of axi_master.v
wire emaxi_wr_wait_outb; // From axi_elink_if of axi_elink_if.v
wire emaxi_write_inb; // From axi_master of axi_master.v
wire emaxi_write_outb; // From axi_elink_if of axi_elink_if.v
wire esaxi_access_inb; // From axi_slave of axi_slave.v
wire esaxi_access_outb; // From axi_elink_if of axi_elink_if.v
wire [3:0] esaxi_ctrlmode_inb; // From axi_slave of axi_slave.v
wire [3:0] esaxi_ctrlmode_outb; // From axi_elink_if of axi_elink_if.v
wire [31:0] esaxi_data_inb; // From axi_slave of axi_slave.v
wire [31:0] esaxi_data_outb; // From axi_elink_if of axi_elink_if.v
wire [1:0] esaxi_datamode_inb; // From axi_slave of axi_slave.v
wire [1:0] esaxi_datamode_outb; // From axi_elink_if of axi_elink_if.v
wire [31:0] esaxi_dstaddr_inb; // From axi_slave of axi_slave.v
wire [31:0] esaxi_dstaddr_outb; // From axi_elink_if of axi_elink_if.v
wire esaxi_rd_wait_inb; // From axi_slave of axi_slave.v
wire esaxi_rd_wait_outb; // From axi_elink_if of axi_elink_if.v
wire [31:0] esaxi_srcaddr_inb; // From axi_slave of axi_slave.v
wire [31:0] esaxi_srcaddr_outb; // From axi_elink_if of axi_elink_if.v
wire esaxi_wr_wait_inb; // From axi_slave of axi_slave.v
wire esaxi_wr_wait_outb; // From axi_elink_if of axi_elink_if.v
wire esaxi_write_inb; // From axi_slave of axi_slave.v
wire esaxi_write_outb; // From axi_elink_if of axi_elink_if.v
// End of automatics
//#########
//# Regs
//#########
//#########
//# Wires
//#########
wire emaxi_reset;
wire esaxi_reset;
wire rxi_eclk;
wire [31:0] elink_dstaddr_inb;
wire [31:0] elink_dstaddr_tmp;
wire ext_mem_access;
//#################
//# global signals
//#################
assign emaxi_reset = ~emaxi_aresetn;
assign esaxi_reset = ~esaxi_aresetn;
//##################################
//# AXI Slave Port Instantiation
//##################################
/*axi_slave AUTO_TEMPLATE(.eclk (rxi_eclk),
.reset (esaxi_reset),
.aclk (esaxi_aclk),
.aw\(.*\) (esaxi_aw\1[]),
.w\(.*\) (esaxi_w\1[]),
.b\(.*\) (esaxi_b\1[]),
.ar\(.*\) (esaxi_ar\1[]),
.r\(.*\) (esaxi_r\1[]),
.emesh_\(.*\) (esaxi_\1[]),
);
*/
axi_slave axi_slave(/*AUTOINST*/
// Outputs
.csysack (csysack),
.cactive (cactive),
.awready (esaxi_awready), // Templated
.wready (esaxi_wready), // Templated
.bid (esaxi_bid[SIDW-1:0]), // Templated
.bresp (esaxi_bresp[1:0]), // Templated
.bvalid (esaxi_bvalid), // Templated
.arready (esaxi_arready), // Templated
.rid (esaxi_rid[SIDW-1:0]), // Templated
.rdata (esaxi_rdata[SDW-1:0]), // Templated
.rresp (esaxi_rresp[1:0]), // Templated
.rlast (esaxi_rlast), // Templated
.rvalid (esaxi_rvalid), // Templated
.emesh_access_inb(esaxi_access_inb), // Templated
.emesh_write_inb (esaxi_write_inb), // Templated
.emesh_datamode_inb(esaxi_datamode_inb[1:0]), // Templated
.emesh_ctrlmode_inb(esaxi_ctrlmode_inb[3:0]), // Templated
.emesh_dstaddr_inb(esaxi_dstaddr_inb[31:0]), // Templated
.emesh_srcaddr_inb(esaxi_srcaddr_inb[31:0]), // Templated
.emesh_data_inb (esaxi_data_inb[31:0]), // Templated
.emesh_wr_wait_inb(esaxi_wr_wait_inb), // Templated
.emesh_rd_wait_inb(esaxi_rd_wait_inb), // Templated
// Inputs
.aclk (esaxi_aclk), // Templated
.eclk (rxi_eclk), // Templated
.reset (esaxi_reset), // Templated
.csysreq (csysreq),
.awid (esaxi_awid[SIDW-1:0]), // Templated
.awaddr (esaxi_awaddr[SAW-1:0]), // Templated
.awlen (esaxi_awlen[3:0]), // Templated
.awsize (esaxi_awsize[2:0]), // Templated
.awburst (esaxi_awburst[1:0]), // Templated
.awlock (esaxi_awlock[1:0]), // Templated
.awcache (esaxi_awcache[3:0]), // Templated
.awprot (esaxi_awprot[2:0]), // Templated
.awvalid (esaxi_awvalid), // Templated
.wid (esaxi_wid[SIDW-1:0]), // Templated
.wdata (esaxi_wdata[SDW-1:0]), // Templated
.wstrb (esaxi_wstrb[3:0]), // Templated
.wlast (esaxi_wlast), // Templated
.wvalid (esaxi_wvalid), // Templated
.bready (esaxi_bready), // Templated
.arid (esaxi_arid[SIDW-1:0]), // Templated
.araddr (esaxi_araddr[SAW-1:0]), // Templated
.arlen (esaxi_arlen[3:0]), // Templated
.arsize (esaxi_arsize[2:0]), // Templated
.arburst (esaxi_arburst[1:0]), // Templated
.arlock (esaxi_arlock[1:0]), // Templated
.arcache (esaxi_arcache[3:0]), // Templated
.arprot (esaxi_arprot[2:0]), // Templated
.arvalid (esaxi_arvalid), // Templated
.rready (esaxi_rready), // Templated
.emesh_access_outb(esaxi_access_outb), // Templated
.emesh_write_outb(esaxi_write_outb), // Templated
.emesh_datamode_outb(esaxi_datamode_outb[1:0]), // Templated
.emesh_ctrlmode_outb(esaxi_ctrlmode_outb[3:0]), // Templated
.emesh_dstaddr_outb(esaxi_dstaddr_outb[31:0]), // Templated
.emesh_srcaddr_outb(esaxi_srcaddr_outb[31:0]), // Templated
.emesh_data_outb (esaxi_data_outb[31:0]), // Templated
.emesh_wr_wait_outb(esaxi_wr_wait_outb), // Templated
.emesh_rd_wait_outb(esaxi_rd_wait_outb), // Templated
.awqos (esaxi_awqos[3:0]), // Templated
.arqos (esaxi_arqos[3:0])); // Templated
//##################################
//# AXI Master Port Instantiation
//##################################
/*axi_master AUTO_TEMPLATE(.eclk (rxi_eclk),
.reset (emaxi_reset),
.aclk (emaxi_aclk),
.aw\(.*\) (emaxi_aw\1[]),
.w\(.*\) (emaxi_w\1[]),
.b\(.*\) (emaxi_b\1[]),
.ar\(.*\) (emaxi_ar\1[]),
.r\(.*\) (emaxi_r\1[]),
.emesh_\(.*\) (emaxi_\1[]),
);
*/
axi_master axi_master(/*AUTOINST*/
// Outputs
.awid (emaxi_awid[MIDW-1:0]), // Templated
.awaddr (emaxi_awaddr[MAW-1:0]), // Templated
.awlen (emaxi_awlen[3:0]), // Templated
.awsize (emaxi_awsize[2:0]), // Templated
.awburst (emaxi_awburst[1:0]), // Templated
.awlock (emaxi_awlock[1:0]), // Templated
.awcache (emaxi_awcache[3:0]), // Templated
.awprot (emaxi_awprot[2:0]), // Templated
.awvalid (emaxi_awvalid), // Templated
.wid (emaxi_wid[MIDW-1:0]), // Templated
.wdata (emaxi_wdata[MDW-1:0]), // Templated
.wstrb (emaxi_wstrb[STW-1:0]), // Templated
.wlast (emaxi_wlast), // Templated
.wvalid (emaxi_wvalid), // Templated
.bready (emaxi_bready), // Templated
.arid (emaxi_arid[MIDW-1:0]), // Templated
.araddr (emaxi_araddr[MAW-1:0]), // Templated
.arlen (emaxi_arlen[3:0]), // Templated
.arsize (emaxi_arsize[2:0]), // Templated
.arburst (emaxi_arburst[1:0]), // Templated
.arlock (emaxi_arlock[1:0]), // Templated
.arcache (emaxi_arcache[3:0]), // Templated
.arprot (emaxi_arprot[2:0]), // Templated
.arvalid (emaxi_arvalid), // Templated
.rready (emaxi_rready), // Templated
.emesh_access_inb (emaxi_access_inb), // Templated
.emesh_write_inb (emaxi_write_inb), // Templated
.emesh_datamode_inb (emaxi_datamode_inb[1:0]), // Templated
.emesh_ctrlmode_inb (emaxi_ctrlmode_inb[3:0]), // Templated
.emesh_dstaddr_inb (emaxi_dstaddr_inb[31:0]), // Templated
.emesh_srcaddr_inb (emaxi_srcaddr_inb[31:0]), // Templated
.emesh_data_inb (emaxi_data_inb[31:0]), // Templated
.emesh_wr_wait_inb (emaxi_wr_wait_inb), // Templated
.emesh_rd_wait_inb (emaxi_rd_wait_inb), // Templated
.awqos (emaxi_awqos[3:0]), // Templated
.arqos (emaxi_arqos[3:0]), // Templated
// Inputs
.aclk (emaxi_aclk), // Templated
.eclk (rxi_eclk), // Templated
.reset (emaxi_reset), // Templated
.awready (emaxi_awready), // Templated
.wready (emaxi_wready), // Templated
.bid (emaxi_bid[MIDW-1:0]), // Templated
.bresp (emaxi_bresp[1:0]), // Templated
.bvalid (emaxi_bvalid), // Templated
.arready (emaxi_arready), // Templated
.rid (emaxi_rid[MIDW-1:0]), // Templated
.rdata (emaxi_rdata[MDW-1:0]), // Templated
.rresp (emaxi_rresp[1:0]), // Templated
.rlast (emaxi_rlast), // Templated
.rvalid (emaxi_rvalid), // Templated
.emesh_access_outb (emaxi_access_outb), // Templated
.emesh_write_outb (emaxi_write_outb), // Templated
.emesh_datamode_outb (emaxi_datamode_outb[1:0]), // Templated
.emesh_ctrlmode_outb (emaxi_ctrlmode_outb[3:0]), // Templated
.emesh_dstaddr_outb (emaxi_dstaddr_outb[31:0]), // Templated
.emesh_srcaddr_outb (emaxi_srcaddr_outb[31:0]), // Templated
.emesh_data_outb (emaxi_data_outb[31:0]), // Templated
.emesh_wr_wait_outb (emaxi_wr_wait_outb)); // Templated
//#####################################
//# ELINK (CHIP Port) Instantiation
//#####################################
//# "manual remapping" of external memory address seen by the chips
assign ext_mem_access = (elink_dstaddr_tmp[31:28] == `VIRT_EXT_MEM) &
~(elink_dstaddr_tmp[31:20] == `AXI_COORD);
assign elink_dstaddr_inb[31:28] = ext_mem_access ? `PHYS_EXT_MEM :
elink_dstaddr_tmp[31:28];
assign elink_dstaddr_inb[27:0] = elink_dstaddr_tmp[27:0];
/*ewrapper_link_top AUTO_TEMPLATE(.emesh_clk_inb (rxi_eclk),
.burst_en (1'b1),
.emesh_dstaddr_inb(elink_dstaddr_tmp[31:0]),
.emesh_\(.*\) (elink_\1[]),
);
*/
ewrapper_link_top ewrapper_link_top
(/*AUTOINST*/
// Outputs
.emesh_clk_inb (rxi_eclk), // Templated
.emesh_access_inb (elink_access_inb), // Templated
.emesh_write_inb (elink_write_inb), // Templated
.emesh_datamode_inb (elink_datamode_inb[1:0]), // Templated
.emesh_ctrlmode_inb (elink_ctrlmode_inb[3:0]), // Templated
.emesh_dstaddr_inb (elink_dstaddr_tmp[31:0]), // Templated
.emesh_srcaddr_inb (elink_srcaddr_inb[31:0]), // Templated
.emesh_data_inb (elink_data_inb[31:0]), // Templated
.emesh_wr_wait_inb (elink_wr_wait_inb), // Templated
.emesh_rd_wait_inb (elink_rd_wait_inb), // Templated
.txo_data_p (txo_data_p[7:0]),
.txo_data_n (txo_data_n[7:0]),
.txo_frame_p (txo_frame_p),
.txo_frame_n (txo_frame_n),
.txo_lclk_p (txo_lclk_p),
.txo_lclk_n (txo_lclk_n),
.rxo_wr_wait_p (rxo_wr_wait_p),
.rxo_wr_wait_n (rxo_wr_wait_n),
.rxo_rd_wait_p (rxo_rd_wait_p),
.rxo_rd_wait_n (rxo_rd_wait_n),
.rxi_cclk_p (rxi_cclk_p),
.rxi_cclk_n (rxi_cclk_n),
// Inputs
.reset (reset),
.clkin_100 (clkin_100),
.elink_disable (elink_disable),
.elink_cclk_enb (elink_cclk_enb),
.elink_clk_div (elink_clk_div[1:0]),
.emesh_access_outb (elink_access_outb), // Templated
.emesh_write_outb (elink_write_outb), // Templated
.emesh_datamode_outb (elink_datamode_outb[1:0]), // Templated
.emesh_ctrlmode_outb (elink_ctrlmode_outb[3:0]), // Templated
.emesh_dstaddr_outb (elink_dstaddr_outb[31:0]), // Templated
.emesh_srcaddr_outb (elink_srcaddr_outb[31:0]), // Templated
.emesh_data_outb (elink_data_outb[31:0]), // Templated
.emesh_wr_wait_outb (elink_wr_wait_outb), // Templated
.emesh_rd_wait_outb (elink_rd_wait_outb), // Templated
.rxi_data_p (rxi_data_p[7:0]),
.rxi_data_n (rxi_data_n[7:0]),
.rxi_frame_p (rxi_frame_p),
.rxi_frame_n (rxi_frame_n),
.rxi_lclk_p (rxi_lclk_p),
.rxi_lclk_n (rxi_lclk_n),
.txi_wr_wait_p (txi_wr_wait_p),
.txi_wr_wait_n (txi_wr_wait_n),
.txi_rd_wait_p (txi_rd_wait_p),
.txi_rd_wait_n (txi_rd_wait_n),
.burst_en (1'b1)); // Templated
//####################################
//# AXI-ELINK Interface Instantiation
//####################################
/*axi_elink_if AUTO_TEMPLATE(.eclk (rxi_eclk),
.aclk (esaxi_aclk),
);
*/
axi_elink_if axi_elink_if
(/*AUTOINST*/
// Outputs
.reset_chip (reset_chip),
.reset_fpga (reset_fpga),
.emaxi_access_outb (emaxi_access_outb),
.emaxi_write_outb (emaxi_write_outb),
.emaxi_datamode_outb (emaxi_datamode_outb[1:0]),
.emaxi_ctrlmode_outb (emaxi_ctrlmode_outb[3:0]),
.emaxi_dstaddr_outb (emaxi_dstaddr_outb[31:0]),
.emaxi_srcaddr_outb (emaxi_srcaddr_outb[31:0]),
.emaxi_data_outb (emaxi_data_outb[31:0]),
.emaxi_wr_wait_outb (emaxi_wr_wait_outb),
.esaxi_access_outb (esaxi_access_outb),
.esaxi_write_outb (esaxi_write_outb),
.esaxi_datamode_outb (esaxi_datamode_outb[1:0]),
.esaxi_ctrlmode_outb (esaxi_ctrlmode_outb[3:0]),
.esaxi_dstaddr_outb (esaxi_dstaddr_outb[31:0]),
.esaxi_srcaddr_outb (esaxi_srcaddr_outb[31:0]),
.esaxi_data_outb (esaxi_data_outb[31:0]),
.esaxi_wr_wait_outb (esaxi_wr_wait_outb),
.esaxi_rd_wait_outb (esaxi_rd_wait_outb),
.elink_access_outb (elink_access_outb),
.elink_write_outb (elink_write_outb),
.elink_datamode_outb (elink_datamode_outb[1:0]),
.elink_ctrlmode_outb (elink_ctrlmode_outb[3:0]),
.elink_dstaddr_outb (elink_dstaddr_outb[31:0]),
.elink_srcaddr_outb (elink_srcaddr_outb[31:0]),
.elink_data_outb (elink_data_outb[31:0]),
.elink_wr_wait_outb (elink_wr_wait_outb),
.elink_rd_wait_outb (elink_rd_wait_outb),
.elink_disable (elink_disable),
.elink_cclk_enb (elink_cclk_enb),
.elink_clk_div (elink_clk_div[1:0]),
// Inputs
.eclk (rxi_eclk), // Templated
.aclk (esaxi_aclk), // Templated
.reset (reset),
.emaxi_access_inb (emaxi_access_inb),
.emaxi_write_inb (emaxi_write_inb),
.emaxi_datamode_inb (emaxi_datamode_inb[1:0]),
.emaxi_ctrlmode_inb (emaxi_ctrlmode_inb[3:0]),
.emaxi_dstaddr_inb (emaxi_dstaddr_inb[31:0]),
.emaxi_srcaddr_inb (emaxi_srcaddr_inb[31:0]),
.emaxi_data_inb (emaxi_data_inb[31:0]),
.emaxi_wr_wait_inb (emaxi_wr_wait_inb),
.emaxi_rd_wait_inb (emaxi_rd_wait_inb),
.esaxi_access_inb (esaxi_access_inb),
.esaxi_write_inb (esaxi_write_inb),
.esaxi_datamode_inb (esaxi_datamode_inb[1:0]),
.esaxi_ctrlmode_inb (esaxi_ctrlmode_inb[3:0]),
.esaxi_dstaddr_inb (esaxi_dstaddr_inb[31:0]),
.esaxi_srcaddr_inb (esaxi_srcaddr_inb[31:0]),
.esaxi_data_inb (esaxi_data_inb[31:0]),
.esaxi_wr_wait_inb (esaxi_wr_wait_inb),
.esaxi_rd_wait_inb (esaxi_rd_wait_inb),
.elink_access_inb (elink_access_inb),
.elink_write_inb (elink_write_inb),
.elink_datamode_inb (elink_datamode_inb[1:0]),
.elink_ctrlmode_inb (elink_ctrlmode_inb[3:0]),
.elink_dstaddr_inb (elink_dstaddr_inb[31:0]),
.elink_srcaddr_inb (elink_srcaddr_inb[31:0]),
.elink_data_inb (elink_data_inb[31:0]),
.elink_wr_wait_inb (elink_wr_wait_inb),
.elink_rd_wait_inb (elink_rd_wait_inb));
endmodule
|
module Clk_Wizard
(VGA_clock,
Main_clock,
resetn,
locked,
Clock_Board);
output VGA_clock;
output Main_clock;
input resetn;
output locked;
input Clock_Board;
(* IBUF_LOW_PWR *) wire Clock_Board;
wire Main_clock;
wire VGA_clock;
wire locked;
wire resetn;
Clk_Wizard_Clk_Wizard_clk_wiz inst
(.Clock_Board(Clock_Board),
.Main_clock(Main_clock),
.VGA_clock(VGA_clock),
.locked(locked),
.resetn(resetn));
endmodule
|
module Clk_Wizard_Clk_Wizard_clk_wiz
(VGA_clock,
Main_clock,
resetn,
locked,
Clock_Board);
output VGA_clock;
output Main_clock;
input resetn;
output locked;
input Clock_Board;
wire Clock_Board;
wire Clock_Board_Clk_Wizard;
wire Main_clock;
wire Main_clock_Clk_Wizard;
wire VGA_clock;
wire VGA_clock_Clk_Wizard;
wire clkfbout_Clk_Wizard;
wire locked;
wire reset_high;
wire resetn;
wire NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT2_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT3_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED;
wire NLW_mmcm_adv_inst_DRDY_UNCONNECTED;
wire NLW_mmcm_adv_inst_PSDONE_UNCONNECTED;
wire [15:0]NLW_mmcm_adv_inst_DO_UNCONNECTED;
(* BOX_TYPE = "PRIMITIVE" *)
(* CAPACITANCE = "DONT_CARE" *)
(* IBUF_DELAY_VALUE = "0" *)
(* IFD_DELAY_VALUE = "AUTO" *)
IBUF #(
.IOSTANDARD("DEFAULT"))
clkin1_ibufg
(.I(Clock_Board),
.O(Clock_Board_Clk_Wizard));
(* BOX_TYPE = "PRIMITIVE" *)
BUFG clkout1_buf
(.I(VGA_clock_Clk_Wizard),
.O(VGA_clock));
(* BOX_TYPE = "PRIMITIVE" *)
BUFG clkout2_buf
(.I(Main_clock_Clk_Wizard),
.O(Main_clock));
(* BOX_TYPE = "PRIMITIVE" *)
MMCME2_ADV #(
.BANDWIDTH("OPTIMIZED"),
.CLKFBOUT_MULT_F(21.875000),
.CLKFBOUT_PHASE(0.000000),
.CLKFBOUT_USE_FINE_PS("FALSE"),
.CLKIN1_PERIOD(10.000000),
.CLKIN2_PERIOD(0.000000),
.CLKOUT0_DIVIDE_F(10.125000),
.CLKOUT0_DUTY_CYCLE(0.500000),
.CLKOUT0_PHASE(0.000000),
.CLKOUT0_USE_FINE_PS("FALSE"),
.CLKOUT1_DIVIDE(11),
.CLKOUT1_DUTY_CYCLE(0.500000),
.CLKOUT1_PHASE(0.000000),
.CLKOUT1_USE_FINE_PS("FALSE"),
.CLKOUT2_DIVIDE(1),
.CLKOUT2_DUTY_CYCLE(0.500000),
.CLKOUT2_PHASE(0.000000),
.CLKOUT2_USE_FINE_PS("FALSE"),
.CLKOUT3_DIVIDE(1),
.CLKOUT3_DUTY_CYCLE(0.500000),
.CLKOUT3_PHASE(0.000000),
.CLKOUT3_USE_FINE_PS("FALSE"),
.CLKOUT4_CASCADE("FALSE"),
.CLKOUT4_DIVIDE(1),
.CLKOUT4_DUTY_CYCLE(0.500000),
.CLKOUT4_PHASE(0.000000),
.CLKOUT4_USE_FINE_PS("FALSE"),
.CLKOUT5_DIVIDE(1),
.CLKOUT5_DUTY_CYCLE(0.500000),
.CLKOUT5_PHASE(0.000000),
.CLKOUT5_USE_FINE_PS("FALSE"),
.CLKOUT6_DIVIDE(1),
.CLKOUT6_DUTY_CYCLE(0.500000),
.CLKOUT6_PHASE(0.000000),
.CLKOUT6_USE_FINE_PS("FALSE"),
.COMPENSATION("INTERNAL"),
.DIVCLK_DIVIDE(2),
.IS_CLKINSEL_INVERTED(1'b0),
.IS_PSEN_INVERTED(1'b0),
.IS_PSINCDEC_INVERTED(1'b0),
.IS_PWRDWN_INVERTED(1'b0),
.IS_RST_INVERTED(1'b0),
.REF_JITTER1(0.010000),
.REF_JITTER2(0.010000),
.SS_EN("FALSE"),
.SS_MODE("CENTER_HIGH"),
.SS_MOD_PERIOD(10000),
.STARTUP_WAIT("FALSE"))
mmcm_adv_inst
(.CLKFBIN(clkfbout_Clk_Wizard),
.CLKFBOUT(clkfbout_Clk_Wizard),
.CLKFBOUTB(NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED),
.CLKFBSTOPPED(NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED),
.CLKIN1(Clock_Board_Clk_Wizard),
.CLKIN2(1'b0),
.CLKINSEL(1'b1),
.CLKINSTOPPED(NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED),
.CLKOUT0(VGA_clock_Clk_Wizard),
.CLKOUT0B(NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED),
.CLKOUT1(Main_clock_Clk_Wizard),
.CLKOUT1B(NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED),
.CLKOUT2(NLW_mmcm_adv_inst_CLKOUT2_UNCONNECTED),
.CLKOUT2B(NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED),
.CLKOUT3(NLW_mmcm_adv_inst_CLKOUT3_UNCONNECTED),
.CLKOUT3B(NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED),
.CLKOUT4(NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED),
.CLKOUT5(NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED),
.CLKOUT6(NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED),
.DADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DCLK(1'b0),
.DEN(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DO(NLW_mmcm_adv_inst_DO_UNCONNECTED[15:0]),
.DRDY(NLW_mmcm_adv_inst_DRDY_UNCONNECTED),
.DWE(1'b0),
.LOCKED(locked),
.PSCLK(1'b0),
.PSDONE(NLW_mmcm_adv_inst_PSDONE_UNCONNECTED),
.PSEN(1'b0),
.PSINCDEC(1'b0),
.PWRDWN(1'b0),
.RST(reset_high));
LUT1 #(
.INIT(2'h1))
mmcm_adv_inst_i_1
(.I0(resetn),
.O(reset_high));
endmodule
|
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
|
module cpu_tb();
reg clk = 0;
//
// ROM
//
localparam MEM_ADDR = 4;
localparam MEM_EXTRA = 4;
reg [ MEM_ADDR :0] mem_addr;
reg [ MEM_EXTRA-1:0] mem_extra;
reg [ MEM_ADDR :0] rom_lower_bound = 0;
reg [ MEM_ADDR :0] rom_upper_bound = ~0;
wire [2**MEM_EXTRA*8-1:0] mem_data;
wire mem_error;
genrom #(
.ROMFILE("i32.sub.hex"),
.AW(MEM_ADDR),
.DW(8),
.EXTRA(MEM_EXTRA)
)
ROM (
.clk(clk),
.addr(mem_addr),
.extra(mem_extra),
.lower_bound(rom_lower_bound),
.upper_bound(rom_upper_bound),
.data(mem_data),
.error(mem_error)
);
//
// CPU
//
parameter HAS_FPU = 1;
parameter USE_64B = 1;
reg reset = 0;
wire [63:0] result;
wire [ 1:0] result_type;
wire result_empty;
wire [ 3:0] trap;
cpu #(
.HAS_FPU(HAS_FPU),
.USE_64B(USE_64B),
.MEM_DEPTH(MEM_ADDR)
)
dut
(
.clk(clk),
.reset(reset),
.result(result),
.result_type(result_type),
.result_empty(result_empty),
.trap(trap),
.mem_addr(mem_addr),
.mem_extra(mem_extra),
.mem_data(mem_data),
.mem_error(mem_error)
);
always #1 clk = ~clk;
initial begin
$dumpfile("i32.sub_tb.vcd");
$dumpvars(0, cpu_tb);
#24
`assert(result, 1);
`assert(result_type, `i32);
`assert(result_empty, 0);
$finish;
end
endmodule
|
module sky130_fd_sc_ls__sdfrbp (
Q ,
Q_N ,
CLK ,
D ,
SCD ,
SCE ,
RESET_B
);
// Module ports
output Q ;
output Q_N ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input RESET_B;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire buf_Q ;
wire RESET ;
wire mux_out ;
reg notifier ;
wire D_delayed ;
wire SCD_delayed ;
wire SCE_delayed ;
wire RESET_B_delayed;
wire CLK_delayed ;
wire awake ;
wire cond0 ;
wire cond1 ;
wire cond2 ;
wire cond3 ;
wire cond4 ;
// Name Output Other arguments
not not0 (RESET , RESET_B_delayed );
sky130_fd_sc_ls__udp_mux_2to1 mux_2to10 (mux_out, D_delayed, SCD_delayed, SCE_delayed );
sky130_fd_sc_ls__udp_dff$PR_pp$PG$N dff0 (buf_Q , mux_out, CLK_delayed, RESET, notifier, VPWR, VGND);
assign awake = ( VPWR === 1'b1 );
assign cond0 = ( ( RESET_B_delayed === 1'b1 ) && awake );
assign cond1 = ( ( SCE_delayed === 1'b0 ) && cond0 );
assign cond2 = ( ( SCE_delayed === 1'b1 ) && cond0 );
assign cond3 = ( ( D_delayed !== SCD_delayed ) && cond0 );
assign cond4 = ( ( RESET_B === 1'b1 ) && awake );
buf buf0 (Q , buf_Q );
not not1 (Q_N , buf_Q );
endmodule
|
module system_ov7670_controller_1_0_i2c_sender
(E,
sioc,
p_0_in,
\busy_sr_reg[1]_0 ,
siod,
\busy_sr_reg[31]_0 ,
clk,
p_1_in,
DOADO,
\busy_sr_reg[31]_1 );
output [0:0]E;
output sioc;
output p_0_in;
output \busy_sr_reg[1]_0 ;
output siod;
input \busy_sr_reg[31]_0 ;
input clk;
input [0:0]p_1_in;
input [15:0]DOADO;
input [0:0]\busy_sr_reg[31]_1 ;
wire [15:0]DOADO;
wire [0:0]E;
wire busy_sr0;
wire \busy_sr[0]_i_3_n_0 ;
wire \busy_sr[0]_i_5_n_0 ;
wire \busy_sr[10]_i_1_n_0 ;
wire \busy_sr[11]_i_1_n_0 ;
wire \busy_sr[12]_i_1_n_0 ;
wire \busy_sr[13]_i_1_n_0 ;
wire \busy_sr[14]_i_1_n_0 ;
wire \busy_sr[15]_i_1_n_0 ;
wire \busy_sr[16]_i_1_n_0 ;
wire \busy_sr[17]_i_1_n_0 ;
wire \busy_sr[18]_i_1_n_0 ;
wire \busy_sr[19]_i_1_n_0 ;
wire \busy_sr[1]_i_1_n_0 ;
wire \busy_sr[20]_i_1_n_0 ;
wire \busy_sr[21]_i_1_n_0 ;
wire \busy_sr[22]_i_1_n_0 ;
wire \busy_sr[23]_i_1_n_0 ;
wire \busy_sr[24]_i_1_n_0 ;
wire \busy_sr[25]_i_1_n_0 ;
wire \busy_sr[26]_i_1_n_0 ;
wire \busy_sr[27]_i_1_n_0 ;
wire \busy_sr[28]_i_1_n_0 ;
wire \busy_sr[29]_i_1_n_0 ;
wire \busy_sr[2]_i_1_n_0 ;
wire \busy_sr[30]_i_1_n_0 ;
wire \busy_sr[31]_i_1_n_0 ;
wire \busy_sr[31]_i_2_n_0 ;
wire \busy_sr[3]_i_1_n_0 ;
wire \busy_sr[4]_i_1_n_0 ;
wire \busy_sr[5]_i_1_n_0 ;
wire \busy_sr[6]_i_1_n_0 ;
wire \busy_sr[7]_i_1_n_0 ;
wire \busy_sr[8]_i_1_n_0 ;
wire \busy_sr[9]_i_1_n_0 ;
wire \busy_sr_reg[1]_0 ;
wire \busy_sr_reg[31]_0 ;
wire [0:0]\busy_sr_reg[31]_1 ;
wire \busy_sr_reg_n_0_[0] ;
wire \busy_sr_reg_n_0_[10] ;
wire \busy_sr_reg_n_0_[11] ;
wire \busy_sr_reg_n_0_[12] ;
wire \busy_sr_reg_n_0_[13] ;
wire \busy_sr_reg_n_0_[14] ;
wire \busy_sr_reg_n_0_[15] ;
wire \busy_sr_reg_n_0_[16] ;
wire \busy_sr_reg_n_0_[17] ;
wire \busy_sr_reg_n_0_[18] ;
wire \busy_sr_reg_n_0_[1] ;
wire \busy_sr_reg_n_0_[21] ;
wire \busy_sr_reg_n_0_[22] ;
wire \busy_sr_reg_n_0_[23] ;
wire \busy_sr_reg_n_0_[24] ;
wire \busy_sr_reg_n_0_[25] ;
wire \busy_sr_reg_n_0_[26] ;
wire \busy_sr_reg_n_0_[27] ;
wire \busy_sr_reg_n_0_[28] ;
wire \busy_sr_reg_n_0_[29] ;
wire \busy_sr_reg_n_0_[2] ;
wire \busy_sr_reg_n_0_[30] ;
wire \busy_sr_reg_n_0_[3] ;
wire \busy_sr_reg_n_0_[4] ;
wire \busy_sr_reg_n_0_[5] ;
wire \busy_sr_reg_n_0_[6] ;
wire \busy_sr_reg_n_0_[7] ;
wire \busy_sr_reg_n_0_[8] ;
wire \busy_sr_reg_n_0_[9] ;
wire clk;
wire \data_sr[10]_i_1_n_0 ;
wire \data_sr[12]_i_1_n_0 ;
wire \data_sr[13]_i_1_n_0 ;
wire \data_sr[14]_i_1_n_0 ;
wire \data_sr[15]_i_1_n_0 ;
wire \data_sr[16]_i_1_n_0 ;
wire \data_sr[17]_i_1_n_0 ;
wire \data_sr[18]_i_1_n_0 ;
wire \data_sr[19]_i_1_n_0 ;
wire \data_sr[22]_i_1_n_0 ;
wire \data_sr[27]_i_1_n_0 ;
wire \data_sr[30]_i_1_n_0 ;
wire \data_sr[31]_i_1_n_0 ;
wire \data_sr[31]_i_2_n_0 ;
wire \data_sr[3]_i_1_n_0 ;
wire \data_sr[4]_i_1_n_0 ;
wire \data_sr[5]_i_1_n_0 ;
wire \data_sr[6]_i_1_n_0 ;
wire \data_sr[7]_i_1_n_0 ;
wire \data_sr[8]_i_1_n_0 ;
wire \data_sr[9]_i_1_n_0 ;
wire \data_sr_reg_n_0_[10] ;
wire \data_sr_reg_n_0_[11] ;
wire \data_sr_reg_n_0_[12] ;
wire \data_sr_reg_n_0_[13] ;
wire \data_sr_reg_n_0_[14] ;
wire \data_sr_reg_n_0_[15] ;
wire \data_sr_reg_n_0_[16] ;
wire \data_sr_reg_n_0_[17] ;
wire \data_sr_reg_n_0_[18] ;
wire \data_sr_reg_n_0_[19] ;
wire \data_sr_reg_n_0_[1] ;
wire \data_sr_reg_n_0_[20] ;
wire \data_sr_reg_n_0_[21] ;
wire \data_sr_reg_n_0_[22] ;
wire \data_sr_reg_n_0_[23] ;
wire \data_sr_reg_n_0_[24] ;
wire \data_sr_reg_n_0_[25] ;
wire \data_sr_reg_n_0_[26] ;
wire \data_sr_reg_n_0_[27] ;
wire \data_sr_reg_n_0_[28] ;
wire \data_sr_reg_n_0_[29] ;
wire \data_sr_reg_n_0_[2] ;
wire \data_sr_reg_n_0_[30] ;
wire \data_sr_reg_n_0_[31] ;
wire \data_sr_reg_n_0_[3] ;
wire \data_sr_reg_n_0_[4] ;
wire \data_sr_reg_n_0_[5] ;
wire \data_sr_reg_n_0_[6] ;
wire \data_sr_reg_n_0_[7] ;
wire \data_sr_reg_n_0_[8] ;
wire \data_sr_reg_n_0_[9] ;
wire [7:6]divider_reg__0;
wire [5:0]divider_reg__1;
wire p_0_in;
wire [7:0]p_0_in__0;
wire [0:0]p_1_in;
wire [1:0]p_1_in_0;
wire sioc;
wire sioc_i_1_n_0;
wire sioc_i_2_n_0;
wire sioc_i_3_n_0;
wire sioc_i_4_n_0;
wire sioc_i_5_n_0;
wire siod;
wire siod_INST_0_i_1_n_0;
LUT6 #(
.INIT(64'h4000FFFF40004000))
\busy_sr[0]_i_1
(.I0(\busy_sr[0]_i_3_n_0 ),
.I1(divider_reg__0[6]),
.I2(divider_reg__0[7]),
.I3(p_0_in),
.I4(\busy_sr_reg[1]_0 ),
.I5(p_1_in),
.O(busy_sr0));
LUT6 #(
.INIT(64'h7FFFFFFFFFFFFFFF))
\busy_sr[0]_i_3
(.I0(divider_reg__1[4]),
.I1(divider_reg__1[2]),
.I2(divider_reg__1[0]),
.I3(divider_reg__1[1]),
.I4(divider_reg__1[3]),
.I5(divider_reg__1[5]),
.O(\busy_sr[0]_i_3_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT5 #(
.INIT(32'hFFFFFFFE))
\busy_sr[0]_i_4
(.I0(divider_reg__1[2]),
.I1(divider_reg__1[3]),
.I2(divider_reg__1[0]),
.I3(divider_reg__1[1]),
.I4(\busy_sr[0]_i_5_n_0 ),
.O(\busy_sr_reg[1]_0 ));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT4 #(
.INIT(16'hFFFE))
\busy_sr[0]_i_5
(.I0(divider_reg__1[5]),
.I1(divider_reg__1[4]),
.I2(divider_reg__0[7]),
.I3(divider_reg__0[6]),
.O(\busy_sr[0]_i_5_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair18" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[10]_i_1
(.I0(\busy_sr_reg_n_0_[9] ),
.I1(p_0_in),
.O(\busy_sr[10]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair15" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[11]_i_1
(.I0(\busy_sr_reg_n_0_[10] ),
.I1(p_0_in),
.O(\busy_sr[11]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair29" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[12]_i_1
(.I0(\busy_sr_reg_n_0_[11] ),
.I1(p_0_in),
.O(\busy_sr[12]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair28" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[13]_i_1
(.I0(\busy_sr_reg_n_0_[12] ),
.I1(p_0_in),
.O(\busy_sr[13]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair27" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[14]_i_1
(.I0(\busy_sr_reg_n_0_[13] ),
.I1(p_0_in),
.O(\busy_sr[14]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair14" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[15]_i_1
(.I0(\busy_sr_reg_n_0_[14] ),
.I1(p_0_in),
.O(\busy_sr[15]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair21" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[16]_i_1
(.I0(\busy_sr_reg_n_0_[15] ),
.I1(p_0_in),
.O(\busy_sr[16]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair28" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[17]_i_1
(.I0(\busy_sr_reg_n_0_[16] ),
.I1(p_0_in),
.O(\busy_sr[17]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair27" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[18]_i_1
(.I0(\busy_sr_reg_n_0_[17] ),
.I1(p_0_in),
.O(\busy_sr[18]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair26" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[19]_i_1
(.I0(\busy_sr_reg_n_0_[18] ),
.I1(p_0_in),
.O(\busy_sr[19]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[1]_i_1
(.I0(\busy_sr_reg_n_0_[0] ),
.I1(p_0_in),
.O(\busy_sr[1]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair25" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[20]_i_1
(.I0(p_1_in_0[0]),
.I1(p_0_in),
.O(\busy_sr[20]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair24" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[21]_i_1
(.I0(p_1_in_0[1]),
.I1(p_0_in),
.O(\busy_sr[21]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair23" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[22]_i_1
(.I0(\busy_sr_reg_n_0_[21] ),
.I1(p_0_in),
.O(\busy_sr[22]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair22" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[23]_i_1
(.I0(\busy_sr_reg_n_0_[22] ),
.I1(p_0_in),
.O(\busy_sr[23]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair21" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[24]_i_1
(.I0(\busy_sr_reg_n_0_[23] ),
.I1(p_0_in),
.O(\busy_sr[24]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair20" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[25]_i_1
(.I0(\busy_sr_reg_n_0_[24] ),
.I1(p_0_in),
.O(\busy_sr[25]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair19" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[26]_i_1
(.I0(\busy_sr_reg_n_0_[25] ),
.I1(p_0_in),
.O(\busy_sr[26]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair18" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[27]_i_1
(.I0(\busy_sr_reg_n_0_[26] ),
.I1(p_0_in),
.O(\busy_sr[27]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair15" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[28]_i_1
(.I0(\busy_sr_reg_n_0_[27] ),
.I1(p_0_in),
.O(\busy_sr[28]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair14" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[29]_i_1
(.I0(\busy_sr_reg_n_0_[28] ),
.I1(p_0_in),
.O(\busy_sr[29]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair26" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[2]_i_1
(.I0(\busy_sr_reg_n_0_[1] ),
.I1(p_0_in),
.O(\busy_sr[2]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair5" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[30]_i_1
(.I0(\busy_sr_reg_n_0_[29] ),
.I1(p_0_in),
.O(\busy_sr[30]_i_1_n_0 ));
LUT6 #(
.INIT(64'h22222222A2222222))
\busy_sr[31]_i_1
(.I0(p_1_in),
.I1(\busy_sr_reg[1]_0 ),
.I2(p_0_in),
.I3(divider_reg__0[7]),
.I4(divider_reg__0[6]),
.I5(\busy_sr[0]_i_3_n_0 ),
.O(\busy_sr[31]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair4" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[31]_i_2
(.I0(p_0_in),
.I1(\busy_sr_reg_n_0_[30] ),
.O(\busy_sr[31]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair25" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[3]_i_1
(.I0(\busy_sr_reg_n_0_[2] ),
.I1(p_0_in),
.O(\busy_sr[3]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair24" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[4]_i_1
(.I0(\busy_sr_reg_n_0_[3] ),
.I1(p_0_in),
.O(\busy_sr[4]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair23" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[5]_i_1
(.I0(\busy_sr_reg_n_0_[4] ),
.I1(p_0_in),
.O(\busy_sr[5]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair29" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[6]_i_1
(.I0(\busy_sr_reg_n_0_[5] ),
.I1(p_0_in),
.O(\busy_sr[6]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair22" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[7]_i_1
(.I0(\busy_sr_reg_n_0_[6] ),
.I1(p_0_in),
.O(\busy_sr[7]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair20" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[8]_i_1
(.I0(\busy_sr_reg_n_0_[7] ),
.I1(p_0_in),
.O(\busy_sr[8]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair19" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[9]_i_1
(.I0(\busy_sr_reg_n_0_[8] ),
.I1(p_0_in),
.O(\busy_sr[9]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\busy_sr_reg[0]
(.C(clk),
.CE(busy_sr0),
.D(p_1_in),
.Q(\busy_sr_reg_n_0_[0] ),
.R(1'b0));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[10]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[10]_i_1_n_0 ),
.Q(\busy_sr_reg_n_0_[10] ),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[11]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[11]_i_1_n_0 ),
.Q(\busy_sr_reg_n_0_[11] ),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[12]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[12]_i_1_n_0 ),
.Q(\busy_sr_reg_n_0_[12] ),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[13]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[13]_i_1_n_0 ),
.Q(\busy_sr_reg_n_0_[13] ),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[14]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[14]_i_1_n_0 ),
.Q(\busy_sr_reg_n_0_[14] ),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[15]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[15]_i_1_n_0 ),
.Q(\busy_sr_reg_n_0_[15] ),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[16]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[16]_i_1_n_0 ),
.Q(\busy_sr_reg_n_0_[16] ),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[17]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[17]_i_1_n_0 ),
.Q(\busy_sr_reg_n_0_[17] ),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[18]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[18]_i_1_n_0 ),
.Q(\busy_sr_reg_n_0_[18] ),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[19]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[19]_i_1_n_0 ),
.Q(p_1_in_0[0]),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[1]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[1]_i_1_n_0 ),
.Q(\busy_sr_reg_n_0_[1] ),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[20]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[20]_i_1_n_0 ),
.Q(p_1_in_0[1]),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[21]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[21]_i_1_n_0 ),
.Q(\busy_sr_reg_n_0_[21] ),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[22]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[22]_i_1_n_0 ),
.Q(\busy_sr_reg_n_0_[22] ),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[23]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[23]_i_1_n_0 ),
.Q(\busy_sr_reg_n_0_[23] ),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[24]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[24]_i_1_n_0 ),
.Q(\busy_sr_reg_n_0_[24] ),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[25]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[25]_i_1_n_0 ),
.Q(\busy_sr_reg_n_0_[25] ),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[26]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[26]_i_1_n_0 ),
.Q(\busy_sr_reg_n_0_[26] ),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[27]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[27]_i_1_n_0 ),
.Q(\busy_sr_reg_n_0_[27] ),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[28]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[28]_i_1_n_0 ),
.Q(\busy_sr_reg_n_0_[28] ),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[29]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[29]_i_1_n_0 ),
.Q(\busy_sr_reg_n_0_[29] ),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[2]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[2]_i_1_n_0 ),
.Q(\busy_sr_reg_n_0_[2] ),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[30]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[30]_i_1_n_0 ),
.Q(\busy_sr_reg_n_0_[30] ),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[31]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[31]_i_2_n_0 ),
.Q(p_0_in),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[3]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[3]_i_1_n_0 ),
.Q(\busy_sr_reg_n_0_[3] ),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[4]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[4]_i_1_n_0 ),
.Q(\busy_sr_reg_n_0_[4] ),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[5]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[5]_i_1_n_0 ),
.Q(\busy_sr_reg_n_0_[5] ),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[6]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[6]_i_1_n_0 ),
.Q(\busy_sr_reg_n_0_[6] ),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[7]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[7]_i_1_n_0 ),
.Q(\busy_sr_reg_n_0_[7] ),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[8]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[8]_i_1_n_0 ),
.Q(\busy_sr_reg_n_0_[8] ),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[9]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[9]_i_1_n_0 ),
.Q(\busy_sr_reg_n_0_[9] ),
.S(\busy_sr[31]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair12" *)
LUT3 #(
.INIT(8'hB8))
\data_sr[10]_i_1
(.I0(\data_sr_reg_n_0_[9] ),
.I1(p_0_in),
.I2(DOADO[7]),
.O(\data_sr[10]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair13" *)
LUT3 #(
.INIT(8'hB8))
\data_sr[12]_i_1
(.I0(\data_sr_reg_n_0_[11] ),
.I1(p_0_in),
.I2(DOADO[8]),
.O(\data_sr[12]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair12" *)
LUT3 #(
.INIT(8'hB8))
\data_sr[13]_i_1
(.I0(\data_sr_reg_n_0_[12] ),
.I1(p_0_in),
.I2(DOADO[9]),
.O(\data_sr[13]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair11" *)
LUT3 #(
.INIT(8'hB8))
\data_sr[14]_i_1
(.I0(\data_sr_reg_n_0_[13] ),
.I1(p_0_in),
.I2(DOADO[10]),
.O(\data_sr[14]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair10" *)
LUT3 #(
.INIT(8'hB8))
\data_sr[15]_i_1
(.I0(\data_sr_reg_n_0_[14] ),
.I1(p_0_in),
.I2(DOADO[11]),
.O(\data_sr[15]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair9" *)
LUT3 #(
.INIT(8'hB8))
\data_sr[16]_i_1
(.I0(\data_sr_reg_n_0_[15] ),
.I1(p_0_in),
.I2(DOADO[12]),
.O(\data_sr[16]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair8" *)
LUT3 #(
.INIT(8'hB8))
\data_sr[17]_i_1
(.I0(\data_sr_reg_n_0_[16] ),
.I1(p_0_in),
.I2(DOADO[13]),
.O(\data_sr[17]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair7" *)
LUT3 #(
.INIT(8'hB8))
\data_sr[18]_i_1
(.I0(\data_sr_reg_n_0_[17] ),
.I1(p_0_in),
.I2(DOADO[14]),
.O(\data_sr[18]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair6" *)
LUT3 #(
.INIT(8'hB8))
\data_sr[19]_i_1
(.I0(\data_sr_reg_n_0_[18] ),
.I1(p_0_in),
.I2(DOADO[15]),
.O(\data_sr[19]_i_1_n_0 ));
LUT6 #(
.INIT(64'hCFCFCFCFAACAAAAA))
\data_sr[22]_i_1
(.I0(\data_sr_reg_n_0_[22] ),
.I1(\data_sr_reg_n_0_[21] ),
.I2(p_0_in),
.I3(\data_sr[31]_i_2_n_0 ),
.I4(divider_reg__0[7]),
.I5(\busy_sr_reg[31]_0 ),
.O(\data_sr[22]_i_1_n_0 ));
LUT6 #(
.INIT(64'hCFCFCFCFAACAAAAA))
\data_sr[27]_i_1
(.I0(\data_sr_reg_n_0_[27] ),
.I1(\data_sr_reg_n_0_[26] ),
.I2(p_0_in),
.I3(\data_sr[31]_i_2_n_0 ),
.I4(divider_reg__0[7]),
.I5(\busy_sr_reg[31]_0 ),
.O(\data_sr[27]_i_1_n_0 ));
LUT3 #(
.INIT(8'h02))
\data_sr[30]_i_1
(.I0(p_1_in),
.I1(\busy_sr_reg[1]_0 ),
.I2(p_0_in),
.O(\data_sr[30]_i_1_n_0 ));
LUT6 #(
.INIT(64'hCFCFCFCFAACAAAAA))
\data_sr[31]_i_1
(.I0(\data_sr_reg_n_0_[31] ),
.I1(\data_sr_reg_n_0_[30] ),
.I2(p_0_in),
.I3(\data_sr[31]_i_2_n_0 ),
.I4(divider_reg__0[7]),
.I5(\busy_sr_reg[31]_0 ),
.O(\data_sr[31]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair17" *)
LUT2 #(
.INIT(4'hB))
\data_sr[31]_i_2
(.I0(\busy_sr[0]_i_3_n_0 ),
.I1(divider_reg__0[6]),
.O(\data_sr[31]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair6" *)
LUT3 #(
.INIT(8'hB8))
\data_sr[3]_i_1
(.I0(\data_sr_reg_n_0_[2] ),
.I1(p_0_in),
.I2(DOADO[0]),
.O(\data_sr[3]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair13" *)
LUT3 #(
.INIT(8'hB8))
\data_sr[4]_i_1
(.I0(\data_sr_reg_n_0_[3] ),
.I1(p_0_in),
.I2(DOADO[1]),
.O(\data_sr[4]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair7" *)
LUT3 #(
.INIT(8'hB8))
\data_sr[5]_i_1
(.I0(\data_sr_reg_n_0_[4] ),
.I1(p_0_in),
.I2(DOADO[2]),
.O(\data_sr[5]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair8" *)
LUT3 #(
.INIT(8'hB8))
\data_sr[6]_i_1
(.I0(\data_sr_reg_n_0_[5] ),
.I1(p_0_in),
.I2(DOADO[3]),
.O(\data_sr[6]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair9" *)
LUT3 #(
.INIT(8'hB8))
\data_sr[7]_i_1
(.I0(\data_sr_reg_n_0_[6] ),
.I1(p_0_in),
.I2(DOADO[4]),
.O(\data_sr[7]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair10" *)
LUT3 #(
.INIT(8'hB8))
\data_sr[8]_i_1
(.I0(\data_sr_reg_n_0_[7] ),
.I1(p_0_in),
.I2(DOADO[5]),
.O(\data_sr[8]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair11" *)
LUT3 #(
.INIT(8'hB8))
\data_sr[9]_i_1
(.I0(\data_sr_reg_n_0_[8] ),
.I1(p_0_in),
.I2(DOADO[6]),
.O(\data_sr[9]_i_1_n_0 ));
FDRE #(
.INIT(1'b1))
\data_sr_reg[10]
(.C(clk),
.CE(busy_sr0),
.D(\data_sr[10]_i_1_n_0 ),
.Q(\data_sr_reg_n_0_[10] ),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\data_sr_reg[11]
(.C(clk),
.CE(busy_sr0),
.D(\data_sr_reg_n_0_[10] ),
.Q(\data_sr_reg_n_0_[11] ),
.R(\data_sr[30]_i_1_n_0 ));
FDRE #(
.INIT(1'b1))
\data_sr_reg[12]
(.C(clk),
.CE(busy_sr0),
.D(\data_sr[12]_i_1_n_0 ),
.Q(\data_sr_reg_n_0_[12] ),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\data_sr_reg[13]
(.C(clk),
.CE(busy_sr0),
.D(\data_sr[13]_i_1_n_0 ),
.Q(\data_sr_reg_n_0_[13] ),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\data_sr_reg[14]
(.C(clk),
.CE(busy_sr0),
.D(\data_sr[14]_i_1_n_0 ),
.Q(\data_sr_reg_n_0_[14] ),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\data_sr_reg[15]
(.C(clk),
.CE(busy_sr0),
.D(\data_sr[15]_i_1_n_0 ),
.Q(\data_sr_reg_n_0_[15] ),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\data_sr_reg[16]
(.C(clk),
.CE(busy_sr0),
.D(\data_sr[16]_i_1_n_0 ),
.Q(\data_sr_reg_n_0_[16] ),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\data_sr_reg[17]
(.C(clk),
.CE(busy_sr0),
.D(\data_sr[17]_i_1_n_0 ),
.Q(\data_sr_reg_n_0_[17] ),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\data_sr_reg[18]
(.C(clk),
.CE(busy_sr0),
.D(\data_sr[18]_i_1_n_0 ),
.Q(\data_sr_reg_n_0_[18] ),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\data_sr_reg[19]
(.C(clk),
.CE(busy_sr0),
.D(\data_sr[19]_i_1_n_0 ),
.Q(\data_sr_reg_n_0_[19] ),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\data_sr_reg[1]
(.C(clk),
.CE(busy_sr0),
.D(p_0_in),
.Q(\data_sr_reg_n_0_[1] ),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\data_sr_reg[20]
(.C(clk),
.CE(busy_sr0),
.D(\data_sr_reg_n_0_[19] ),
.Q(\data_sr_reg_n_0_[20] ),
.R(\data_sr[30]_i_1_n_0 ));
FDRE #(
.INIT(1'b1))
\data_sr_reg[21]
(.C(clk),
.CE(busy_sr0),
.D(\data_sr_reg_n_0_[20] ),
.Q(\data_sr_reg_n_0_[21] ),
.R(\data_sr[30]_i_1_n_0 ));
FDRE #(
.INIT(1'b1))
\data_sr_reg[22]
(.C(clk),
.CE(1'b1),
.D(\data_sr[22]_i_1_n_0 ),
.Q(\data_sr_reg_n_0_[22] ),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\data_sr_reg[23]
(.C(clk),
.CE(busy_sr0),
.D(\data_sr_reg_n_0_[22] ),
.Q(\data_sr_reg_n_0_[23] ),
.R(\data_sr[30]_i_1_n_0 ));
FDRE #(
.INIT(1'b1))
\data_sr_reg[24]
(.C(clk),
.CE(busy_sr0),
.D(\data_sr_reg_n_0_[23] ),
.Q(\data_sr_reg_n_0_[24] ),
.R(\data_sr[30]_i_1_n_0 ));
FDRE #(
.INIT(1'b1))
\data_sr_reg[25]
(.C(clk),
.CE(busy_sr0),
.D(\data_sr_reg_n_0_[24] ),
.Q(\data_sr_reg_n_0_[25] ),
.R(\data_sr[30]_i_1_n_0 ));
FDRE #(
.INIT(1'b1))
\data_sr_reg[26]
(.C(clk),
.CE(busy_sr0),
.D(\data_sr_reg_n_0_[25] ),
.Q(\data_sr_reg_n_0_[26] ),
.R(\data_sr[30]_i_1_n_0 ));
FDRE #(
.INIT(1'b1))
\data_sr_reg[27]
(.C(clk),
.CE(1'b1),
.D(\data_sr[27]_i_1_n_0 ),
.Q(\data_sr_reg_n_0_[27] ),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\data_sr_reg[28]
(.C(clk),
.CE(busy_sr0),
.D(\data_sr_reg_n_0_[27] ),
.Q(\data_sr_reg_n_0_[28] ),
.R(\data_sr[30]_i_1_n_0 ));
FDRE #(
.INIT(1'b1))
\data_sr_reg[29]
(.C(clk),
.CE(busy_sr0),
.D(\data_sr_reg_n_0_[28] ),
.Q(\data_sr_reg_n_0_[29] ),
.R(\data_sr[30]_i_1_n_0 ));
FDRE #(
.INIT(1'b1))
\data_sr_reg[2]
(.C(clk),
.CE(busy_sr0),
.D(\data_sr_reg_n_0_[1] ),
.Q(\data_sr_reg_n_0_[2] ),
.R(\data_sr[30]_i_1_n_0 ));
FDRE #(
.INIT(1'b1))
\data_sr_reg[30]
(.C(clk),
.CE(busy_sr0),
.D(\data_sr_reg_n_0_[29] ),
.Q(\data_sr_reg_n_0_[30] ),
.R(\data_sr[30]_i_1_n_0 ));
FDRE #(
.INIT(1'b1))
\data_sr_reg[31]
(.C(clk),
.CE(1'b1),
.D(\data_sr[31]_i_1_n_0 ),
.Q(\data_sr_reg_n_0_[31] ),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\data_sr_reg[3]
(.C(clk),
.CE(busy_sr0),
.D(\data_sr[3]_i_1_n_0 ),
.Q(\data_sr_reg_n_0_[3] ),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\data_sr_reg[4]
(.C(clk),
.CE(busy_sr0),
.D(\data_sr[4]_i_1_n_0 ),
.Q(\data_sr_reg_n_0_[4] ),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\data_sr_reg[5]
(.C(clk),
.CE(busy_sr0),
.D(\data_sr[5]_i_1_n_0 ),
.Q(\data_sr_reg_n_0_[5] ),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\data_sr_reg[6]
(.C(clk),
.CE(busy_sr0),
.D(\data_sr[6]_i_1_n_0 ),
.Q(\data_sr_reg_n_0_[6] ),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\data_sr_reg[7]
(.C(clk),
.CE(busy_sr0),
.D(\data_sr[7]_i_1_n_0 ),
.Q(\data_sr_reg_n_0_[7] ),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\data_sr_reg[8]
(.C(clk),
.CE(busy_sr0),
.D(\data_sr[8]_i_1_n_0 ),
.Q(\data_sr_reg_n_0_[8] ),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\data_sr_reg[9]
(.C(clk),
.CE(busy_sr0),
.D(\data_sr[9]_i_1_n_0 ),
.Q(\data_sr_reg_n_0_[9] ),
.R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair16" *)
LUT1 #(
.INIT(2'h1))
\divider[0]_i_1
(.I0(divider_reg__1[0]),
.O(p_0_in__0[0]));
(* SOFT_HLUTNM = "soft_lutpair16" *)
LUT2 #(
.INIT(4'h6))
\divider[1]_i_1
(.I0(divider_reg__1[0]),
.I1(divider_reg__1[1]),
.O(p_0_in__0[1]));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT3 #(
.INIT(8'h78))
\divider[2]_i_1
(.I0(divider_reg__1[1]),
.I1(divider_reg__1[0]),
.I2(divider_reg__1[2]),
.O(p_0_in__0[2]));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT4 #(
.INIT(16'h7F80))
\divider[3]_i_1
(.I0(divider_reg__1[2]),
.I1(divider_reg__1[0]),
.I2(divider_reg__1[1]),
.I3(divider_reg__1[3]),
.O(p_0_in__0[3]));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT5 #(
.INIT(32'h7FFF8000))
\divider[4]_i_1
(.I0(divider_reg__1[3]),
.I1(divider_reg__1[1]),
.I2(divider_reg__1[0]),
.I3(divider_reg__1[2]),
.I4(divider_reg__1[4]),
.O(p_0_in__0[4]));
LUT6 #(
.INIT(64'h7FFFFFFF80000000))
\divider[5]_i_1
(.I0(divider_reg__1[4]),
.I1(divider_reg__1[2]),
.I2(divider_reg__1[0]),
.I3(divider_reg__1[1]),
.I4(divider_reg__1[3]),
.I5(divider_reg__1[5]),
.O(p_0_in__0[5]));
(* SOFT_HLUTNM = "soft_lutpair17" *)
LUT2 #(
.INIT(4'h9))
\divider[6]_i_1
(.I0(\busy_sr[0]_i_3_n_0 ),
.I1(divider_reg__0[6]),
.O(p_0_in__0[6]));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT3 #(
.INIT(8'hD2))
\divider[7]_i_2
(.I0(divider_reg__0[6]),
.I1(\busy_sr[0]_i_3_n_0 ),
.I2(divider_reg__0[7]),
.O(p_0_in__0[7]));
FDRE #(
.INIT(1'b1))
\divider_reg[0]
(.C(clk),
.CE(\busy_sr_reg[31]_1 ),
.D(p_0_in__0[0]),
.Q(divider_reg__1[0]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\divider_reg[1]
(.C(clk),
.CE(\busy_sr_reg[31]_1 ),
.D(p_0_in__0[1]),
.Q(divider_reg__1[1]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\divider_reg[2]
(.C(clk),
.CE(\busy_sr_reg[31]_1 ),
.D(p_0_in__0[2]),
.Q(divider_reg__1[2]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\divider_reg[3]
(.C(clk),
.CE(\busy_sr_reg[31]_1 ),
.D(p_0_in__0[3]),
.Q(divider_reg__1[3]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\divider_reg[4]
(.C(clk),
.CE(\busy_sr_reg[31]_1 ),
.D(p_0_in__0[4]),
.Q(divider_reg__1[4]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\divider_reg[5]
(.C(clk),
.CE(\busy_sr_reg[31]_1 ),
.D(p_0_in__0[5]),
.Q(divider_reg__1[5]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\divider_reg[6]
(.C(clk),
.CE(\busy_sr_reg[31]_1 ),
.D(p_0_in__0[6]),
.Q(divider_reg__0[6]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\divider_reg[7]
(.C(clk),
.CE(\busy_sr_reg[31]_1 ),
.D(p_0_in__0[7]),
.Q(divider_reg__0[7]),
.R(1'b0));
LUT6 #(
.INIT(64'hFCFCFFF8FFFFFFFF))
sioc_i_1
(.I0(\busy_sr_reg_n_0_[0] ),
.I1(sioc_i_2_n_0),
.I2(sioc_i_3_n_0),
.I3(\busy_sr_reg_n_0_[1] ),
.I4(sioc_i_4_n_0),
.I5(p_0_in),
.O(sioc_i_1_n_0));
LUT2 #(
.INIT(4'h6))
sioc_i_2
(.I0(divider_reg__0[6]),
.I1(divider_reg__0[7]),
.O(sioc_i_2_n_0));
(* SOFT_HLUTNM = "soft_lutpair4" *)
LUT4 #(
.INIT(16'hA222))
sioc_i_3
(.I0(sioc_i_5_n_0),
.I1(\busy_sr_reg_n_0_[30] ),
.I2(divider_reg__0[6]),
.I3(p_0_in),
.O(sioc_i_3_n_0));
(* SOFT_HLUTNM = "soft_lutpair5" *)
LUT4 #(
.INIT(16'h7FFF))
sioc_i_4
(.I0(\busy_sr_reg_n_0_[29] ),
.I1(\busy_sr_reg_n_0_[2] ),
.I2(p_0_in),
.I3(\busy_sr_reg_n_0_[30] ),
.O(sioc_i_4_n_0));
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT4 #(
.INIT(16'h0001))
sioc_i_5
(.I0(\busy_sr_reg_n_0_[0] ),
.I1(\busy_sr_reg_n_0_[1] ),
.I2(\busy_sr_reg_n_0_[29] ),
.I3(\busy_sr_reg_n_0_[2] ),
.O(sioc_i_5_n_0));
FDRE sioc_reg
(.C(clk),
.CE(1'b1),
.D(sioc_i_1_n_0),
.Q(sioc),
.R(1'b0));
LUT2 #(
.INIT(4'h8))
siod_INST_0
(.I0(\data_sr_reg_n_0_[31] ),
.I1(siod_INST_0_i_1_n_0),
.O(siod));
LUT6 #(
.INIT(64'hB0BBB0BB0000B0BB))
siod_INST_0_i_1
(.I0(\busy_sr_reg_n_0_[28] ),
.I1(\busy_sr_reg_n_0_[29] ),
.I2(p_1_in_0[0]),
.I3(p_1_in_0[1]),
.I4(\busy_sr_reg_n_0_[11] ),
.I5(\busy_sr_reg_n_0_[10] ),
.O(siod_INST_0_i_1_n_0));
FDRE taken_reg
(.C(clk),
.CE(1'b1),
.D(\busy_sr_reg[31]_0 ),
.Q(E),
.R(1'b0));
endmodule
|
module system_ov7670_controller_1_0_ov7670_controller
(config_finished,
siod,
sioc,
resend,
clk);
output config_finished;
output siod;
output sioc;
input resend;
input clk;
wire Inst_i2c_sender_n_3;
wire Inst_ov7670_registers_n_16;
wire Inst_ov7670_registers_n_18;
wire clk;
wire config_finished;
wire p_0_in;
wire [0:0]p_1_in;
wire resend;
wire sioc;
wire siod;
wire [15:0]sreg_reg;
wire taken;
system_ov7670_controller_1_0_i2c_sender Inst_i2c_sender
(.DOADO(sreg_reg),
.E(taken),
.\busy_sr_reg[1]_0 (Inst_i2c_sender_n_3),
.\busy_sr_reg[31]_0 (Inst_ov7670_registers_n_18),
.\busy_sr_reg[31]_1 (Inst_ov7670_registers_n_16),
.clk(clk),
.p_0_in(p_0_in),
.p_1_in(p_1_in),
.sioc(sioc),
.siod(siod));
system_ov7670_controller_1_0_ov7670_registers Inst_ov7670_registers
(.DOADO(sreg_reg),
.E(taken),
.clk(clk),
.config_finished(config_finished),
.\divider_reg[2] (Inst_i2c_sender_n_3),
.\divider_reg[7] (Inst_ov7670_registers_n_16),
.p_0_in(p_0_in),
.p_1_in(p_1_in),
.resend(resend),
.taken_reg(Inst_ov7670_registers_n_18));
endmodule
|
module system_ov7670_controller_1_0_ov7670_registers
(DOADO,
\divider_reg[7] ,
config_finished,
taken_reg,
p_1_in,
clk,
\divider_reg[2] ,
p_0_in,
resend,
E);
output [15:0]DOADO;
output [0:0]\divider_reg[7] ;
output config_finished;
output taken_reg;
output [0:0]p_1_in;
input clk;
input \divider_reg[2] ;
input p_0_in;
input resend;
input [0:0]E;
wire [15:0]DOADO;
wire [0:0]E;
wire [7:0]address;
wire [7:0]address_reg__0;
wire \address_rep[0]_i_1_n_0 ;
wire \address_rep[1]_i_1_n_0 ;
wire \address_rep[2]_i_1_n_0 ;
wire \address_rep[3]_i_1_n_0 ;
wire \address_rep[4]_i_1_n_0 ;
wire \address_rep[5]_i_1_n_0 ;
wire \address_rep[6]_i_1_n_0 ;
wire \address_rep[7]_i_1_n_0 ;
wire \address_rep[7]_i_2_n_0 ;
wire clk;
wire config_finished;
wire config_finished_INST_0_i_1_n_0;
wire config_finished_INST_0_i_2_n_0;
wire config_finished_INST_0_i_3_n_0;
wire config_finished_INST_0_i_4_n_0;
wire \divider_reg[2] ;
wire [0:0]\divider_reg[7] ;
wire p_0_in;
wire [0:0]p_1_in;
wire resend;
wire taken_reg;
wire [15:0]NLW_sreg_reg_DOBDO_UNCONNECTED;
wire [1:0]NLW_sreg_reg_DOPADOP_UNCONNECTED;
wire [1:0]NLW_sreg_reg_DOPBDOP_UNCONNECTED;
(* equivalent_register_removal = "no" *)
FDRE #(
.INIT(1'b0))
\address_reg[0]
(.C(clk),
.CE(E),
.D(\address_rep[0]_i_1_n_0 ),
.Q(address_reg__0[0]),
.R(resend));
(* equivalent_register_removal = "no" *)
FDRE #(
.INIT(1'b0))
\address_reg[1]
(.C(clk),
.CE(E),
.D(\address_rep[1]_i_1_n_0 ),
.Q(address_reg__0[1]),
.R(resend));
(* equivalent_register_removal = "no" *)
FDRE #(
.INIT(1'b0))
\address_reg[2]
(.C(clk),
.CE(E),
.D(\address_rep[2]_i_1_n_0 ),
.Q(address_reg__0[2]),
.R(resend));
(* equivalent_register_removal = "no" *)
FDRE #(
.INIT(1'b0))
\address_reg[3]
(.C(clk),
.CE(E),
.D(\address_rep[3]_i_1_n_0 ),
.Q(address_reg__0[3]),
.R(resend));
(* equivalent_register_removal = "no" *)
FDRE #(
.INIT(1'b0))
\address_reg[4]
(.C(clk),
.CE(E),
.D(\address_rep[4]_i_1_n_0 ),
.Q(address_reg__0[4]),
.R(resend));
(* equivalent_register_removal = "no" *)
FDRE #(
.INIT(1'b0))
\address_reg[5]
(.C(clk),
.CE(E),
.D(\address_rep[5]_i_1_n_0 ),
.Q(address_reg__0[5]),
.R(resend));
(* equivalent_register_removal = "no" *)
FDRE #(
.INIT(1'b0))
\address_reg[6]
(.C(clk),
.CE(E),
.D(\address_rep[6]_i_1_n_0 ),
.Q(address_reg__0[6]),
.R(resend));
(* equivalent_register_removal = "no" *)
FDRE #(
.INIT(1'b0))
\address_reg[7]
(.C(clk),
.CE(E),
.D(\address_rep[7]_i_1_n_0 ),
.Q(address_reg__0[7]),
.R(resend));
(* equivalent_register_removal = "no" *)
FDRE #(
.INIT(1'b0))
\address_reg_rep[0]
(.C(clk),
.CE(E),
.D(\address_rep[0]_i_1_n_0 ),
.Q(address[0]),
.R(resend));
(* equivalent_register_removal = "no" *)
FDRE #(
.INIT(1'b0))
\address_reg_rep[1]
(.C(clk),
.CE(E),
.D(\address_rep[1]_i_1_n_0 ),
.Q(address[1]),
.R(resend));
(* equivalent_register_removal = "no" *)
FDRE #(
.INIT(1'b0))
\address_reg_rep[2]
(.C(clk),
.CE(E),
.D(\address_rep[2]_i_1_n_0 ),
.Q(address[2]),
.R(resend));
(* equivalent_register_removal = "no" *)
FDRE #(
.INIT(1'b0))
\address_reg_rep[3]
(.C(clk),
.CE(E),
.D(\address_rep[3]_i_1_n_0 ),
.Q(address[3]),
.R(resend));
(* equivalent_register_removal = "no" *)
FDRE #(
.INIT(1'b0))
\address_reg_rep[4]
(.C(clk),
.CE(E),
.D(\address_rep[4]_i_1_n_0 ),
.Q(address[4]),
.R(resend));
(* equivalent_register_removal = "no" *)
FDRE #(
.INIT(1'b0))
\address_reg_rep[5]
(.C(clk),
.CE(E),
.D(\address_rep[5]_i_1_n_0 ),
.Q(address[5]),
.R(resend));
(* equivalent_register_removal = "no" *)
FDRE #(
.INIT(1'b0))
\address_reg_rep[6]
(.C(clk),
.CE(E),
.D(\address_rep[6]_i_1_n_0 ),
.Q(address[6]),
.R(resend));
(* equivalent_register_removal = "no" *)
FDRE #(
.INIT(1'b0))
\address_reg_rep[7]
(.C(clk),
.CE(E),
.D(\address_rep[7]_i_1_n_0 ),
.Q(address[7]),
.R(resend));
LUT1 #(
.INIT(2'h1))
\address_rep[0]_i_1
(.I0(address_reg__0[0]),
.O(\address_rep[0]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair32" *)
LUT2 #(
.INIT(4'h6))
\address_rep[1]_i_1
(.I0(address_reg__0[0]),
.I1(address_reg__0[1]),
.O(\address_rep[1]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair32" *)
LUT3 #(
.INIT(8'h78))
\address_rep[2]_i_1
(.I0(address_reg__0[1]),
.I1(address_reg__0[0]),
.I2(address_reg__0[2]),
.O(\address_rep[2]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair31" *)
LUT4 #(
.INIT(16'h7F80))
\address_rep[3]_i_1
(.I0(address_reg__0[2]),
.I1(address_reg__0[0]),
.I2(address_reg__0[1]),
.I3(address_reg__0[3]),
.O(\address_rep[3]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair31" *)
LUT5 #(
.INIT(32'h7FFF8000))
\address_rep[4]_i_1
(.I0(address_reg__0[3]),
.I1(address_reg__0[1]),
.I2(address_reg__0[0]),
.I3(address_reg__0[2]),
.I4(address_reg__0[4]),
.O(\address_rep[4]_i_1_n_0 ));
LUT6 #(
.INIT(64'h7FFFFFFF80000000))
\address_rep[5]_i_1
(.I0(address_reg__0[4]),
.I1(address_reg__0[2]),
.I2(address_reg__0[0]),
.I3(address_reg__0[1]),
.I4(address_reg__0[3]),
.I5(address_reg__0[5]),
.O(\address_rep[5]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair33" *)
LUT2 #(
.INIT(4'h9))
\address_rep[6]_i_1
(.I0(\address_rep[7]_i_2_n_0 ),
.I1(address_reg__0[6]),
.O(\address_rep[6]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair33" *)
LUT3 #(
.INIT(8'hD2))
\address_rep[7]_i_1
(.I0(address_reg__0[6]),
.I1(\address_rep[7]_i_2_n_0 ),
.I2(address_reg__0[7]),
.O(\address_rep[7]_i_1_n_0 ));
LUT6 #(
.INIT(64'h7FFFFFFFFFFFFFFF))
\address_rep[7]_i_2
(.I0(address_reg__0[4]),
.I1(address_reg__0[2]),
.I2(address_reg__0[0]),
.I3(address_reg__0[1]),
.I4(address_reg__0[3]),
.I5(address_reg__0[5]),
.O(\address_rep[7]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair30" *)
LUT5 #(
.INIT(32'h0000FFFE))
\busy_sr[0]_i_2
(.I0(config_finished_INST_0_i_4_n_0),
.I1(config_finished_INST_0_i_3_n_0),
.I2(config_finished_INST_0_i_2_n_0),
.I3(config_finished_INST_0_i_1_n_0),
.I4(p_0_in),
.O(p_1_in));
(* SOFT_HLUTNM = "soft_lutpair30" *)
LUT4 #(
.INIT(16'h0001))
config_finished_INST_0
(.I0(config_finished_INST_0_i_1_n_0),
.I1(config_finished_INST_0_i_2_n_0),
.I2(config_finished_INST_0_i_3_n_0),
.I3(config_finished_INST_0_i_4_n_0),
.O(config_finished));
LUT4 #(
.INIT(16'h7FFF))
config_finished_INST_0_i_1
(.I0(DOADO[5]),
.I1(DOADO[4]),
.I2(DOADO[7]),
.I3(DOADO[6]),
.O(config_finished_INST_0_i_1_n_0));
LUT4 #(
.INIT(16'h7FFF))
config_finished_INST_0_i_2
(.I0(DOADO[1]),
.I1(DOADO[0]),
.I2(DOADO[3]),
.I3(DOADO[2]),
.O(config_finished_INST_0_i_2_n_0));
LUT4 #(
.INIT(16'h7FFF))
config_finished_INST_0_i_3
(.I0(DOADO[13]),
.I1(DOADO[12]),
.I2(DOADO[15]),
.I3(DOADO[14]),
.O(config_finished_INST_0_i_3_n_0));
LUT4 #(
.INIT(16'h7FFF))
config_finished_INST_0_i_4
(.I0(DOADO[9]),
.I1(DOADO[8]),
.I2(DOADO[11]),
.I3(DOADO[10]),
.O(config_finished_INST_0_i_4_n_0));
LUT6 #(
.INIT(64'hFFFFFFFFFFFE0000))
\divider[7]_i_1
(.I0(config_finished_INST_0_i_1_n_0),
.I1(config_finished_INST_0_i_2_n_0),
.I2(config_finished_INST_0_i_3_n_0),
.I3(config_finished_INST_0_i_4_n_0),
.I4(\divider_reg[2] ),
.I5(p_0_in),
.O(\divider_reg[7] ));
(* CLOCK_DOMAINS = "INDEPENDENT" *)
(* \MEM.PORTA.DATA_BIT_LAYOUT = "p0_d16" *)
(* METHODOLOGY_DRC_VIOS = "{SYNTH-6 {cell *THIS*}}" *)
(* RTL_RAM_BITS = "4096" *)
(* RTL_RAM_NAME = "U0/Inst_ov7670_registers/sreg" *)
(* bram_addr_begin = "0" *)
(* bram_addr_end = "1023" *)
(* bram_slice_begin = "0" *)
(* bram_slice_end = "15" *)
RAMB18E1 #(
.DOA_REG(0),
.DOB_REG(0),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h53295217510C50344F4014383A04401004008C003E000C001100120412801280),
.INIT_01(256'h229121021E3716020F4B0E61030A1A7B190332A41861171111003DC0581E5440),
.INIT_02(256'h90008F008E008D4F74106B4A69004E204D403C78392A3871371D350B330B2907),
.INIT_03(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFB80AB382B20EB10CB0849A0096009100),
.INIT_04(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_05(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_06(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_07(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_08(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_09(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_0A(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_0B(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_0C(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_0D(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_0E(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_0F(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(18'h00000),
.INIT_B(18'h00000),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("PERFORMANCE"),
.READ_WIDTH_A(18),
.READ_WIDTH_B(0),
.RSTREG_PRIORITY_A("RSTREG"),
.RSTREG_PRIORITY_B("RSTREG"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(18'h00000),
.SRVAL_B(18'h00000),
.WRITE_MODE_A("WRITE_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(18),
.WRITE_WIDTH_B(0))
sreg_reg
(.ADDRARDADDR({1'b0,1'b0,address,1'b0,1'b0,1'b0,1'b0}),
.ADDRBWRADDR({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
.CLKARDCLK(clk),
.CLKBWRCLK(1'b0),
.DIADI({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
.DIBDI({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
.DIPADIP({1'b0,1'b0}),
.DIPBDIP({1'b1,1'b1}),
.DOADO(DOADO),
.DOBDO(NLW_sreg_reg_DOBDO_UNCONNECTED[15:0]),
.DOPADOP(NLW_sreg_reg_DOPADOP_UNCONNECTED[1:0]),
.DOPBDOP(NLW_sreg_reg_DOPBDOP_UNCONNECTED[1:0]),
.ENARDEN(1'b1),
.ENBWREN(1'b0),
.REGCEAREGCE(1'b0),
.REGCEB(1'b0),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.WEA({1'b0,1'b0}),
.WEBWE({1'b0,1'b0,1'b0,1'b0}));
LUT6 #(
.INIT(64'h0000000055555554))
taken_i_1
(.I0(p_0_in),
.I1(config_finished_INST_0_i_1_n_0),
.I2(config_finished_INST_0_i_2_n_0),
.I3(config_finished_INST_0_i_3_n_0),
.I4(config_finished_INST_0_i_4_n_0),
.I5(\divider_reg[2] ),
.O(taken_reg));
endmodule
|
module system_ov7670_controller_1_0
(clk,
resend,
config_finished,
sioc,
siod,
reset,
pwdn,
xclk);
(* x_interface_info = "xilinx.com:signal:clock:1.0 clk CLK" *) input clk;
input resend;
output config_finished;
output sioc;
inout siod;
(* x_interface_info = "xilinx.com:signal:reset:1.0 reset RST" *) output reset;
output pwdn;
output xclk;
wire \<const0> ;
wire \<const1> ;
wire clk;
wire config_finished;
wire resend;
wire sioc;
wire siod;
assign pwdn = \<const0> ;
assign reset = \<const1> ;
GND GND
(.G(\<const0> ));
system_ov7670_controller_1_0_ov7670_controller U0
(.clk(clk),
.config_finished(config_finished),
.resend(resend),
.sioc(sioc),
.siod(siod));
VCC VCC
(.P(\<const1> ));
endmodule
|
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
|
module game_engine (
RESET,
SYSTEM_CLOCK,
VGA_CLOCK,
PADDLE_A_POSITION,
PADDLE_B_POSITION,
PIXEL_H,
PIXEL_V,
BALL_H,
BALL_V,
PIXEL
);
input RESET;
input SYSTEM_CLOCK;
input VGA_CLOCK;
input [7:0] PADDLE_A_POSITION;
input [7:0] PADDLE_B_POSITION;
input [10:0] PIXEL_H;
input [10:0] PIXEL_V;
output [10:0] BALL_H;
output [10:0] BALL_V;
output [2:0] PIXEL; // 1 red, 1 green, 1 blue
reg [2:0] pixel;
reg [10:0] paddle_a_pos;
reg [10:0] paddle_b_pos;
reg [10:0] ball_h;
reg [10:0] ball_v;
wire [10:0] ball_h_wire;
wire [10:0] ball_v_wire;
wire border = (PIXEL_V <= 4 || PIXEL_V >= 474 || PIXEL_H <= 4 || PIXEL_H >= 774);
wire net = (PIXEL_V[4] == 1 && (PIXEL_H == 389 || PIXEL_H == 390));
wire paddle_a = (PIXEL_H >= 10 && PIXEL_H <= 20 && PIXEL_V >= paddle_a_pos && PIXEL_V <= (paddle_a_pos + 75));
wire paddle_b = (PIXEL_H >= 760 && PIXEL_H <= 770 && PIXEL_V >= paddle_b_pos && PIXEL_V <= (paddle_b_pos + 75));
wire ball = PIXEL_H >= ball_h && PIXEL_H <= (ball_h + 16) && PIXEL_V >= ball_v && PIXEL_V <= (ball_v + 16);
wire [2:0] score_rgb;
reg [7:0] score_player_one;
reg [7:0] score_player_two;
score score_1(
.clk(SYSTEM_CLOCK),
.PIXEL_H(PIXEL_H),
.PIXEL_V(PIXEL_V),
.PLAYER_ONE(score_player_one),
.PLAYER_TWO(score_player_two),
.PIXEL(score_rgb)
);
always @ (posedge VGA_CLOCK) begin
// Max incomming postion is 255
// so double to get to 510 which is a bit bigger than wanted.
paddle_a_pos <= PADDLE_A_POSITION << 1;
paddle_b_pos <= PADDLE_B_POSITION << 1;
end
// Ball
reg [16:0] ball_timer;
reg [27:0] ball_timer_delay;
reg ball_h_direction;
reg ball_v_direction;
always @ (posedge VGA_CLOCK or posedge RESET) begin
if (RESET) begin
ball_h <= 382;
ball_v <= 200;
ball_h_direction <= 0;
ball_v_direction <= 0;
ball_timer <= 0;
ball_timer_delay <= 28'd67108863;
score_player_one <= 0;
score_player_two <= 0;
end else begin
if (ball_timer_delay > 0) begin
ball_timer_delay <= ball_timer_delay -1;
end
else begin
ball_timer <= ball_timer + 1;
end
// Only move the ball when timer says so.
if (ball_timer == 17'd91071) begin
ball_timer <= 0;
// Move the ball
if (ball_h_direction) begin
ball_h <= ball_h + 1;
// Paddle B detection (right side)
if (ball_h > 755) begin
if (ball_v >= paddle_b_pos && ball_v < (paddle_b_pos + 75)) begin
// Hit the paddle
ball_h_direction <= 0;
end
else begin
// Missed the paddle - new serve
ball_h <= 382;
ball_h_direction <= 1;
ball_timer_delay <= 28'd67108863;
score_player_one <= score_player_one + 1'd1;
end
end
end
else begin
ball_h <= ball_h - 1;
// Paddle A detection (left side)
if (ball_h < 20) begin
if (ball_v >= paddle_a_pos && ball_v < (paddle_a_pos + 75)) begin
// Hit the paddle
ball_h_direction <= 1;
end
else begin
// Missed the paddle - new serve
ball_h <= 382;
ball_h_direction <= 0;
ball_timer_delay <= 28'd67108863;
score_player_two <= score_player_two + 1'd1;
end
end
end
if (ball_v_direction) begin
ball_v <= ball_v + 1;
// Bottom border collision
if (ball_v > 470) ball_v_direction <= 0;
end
else begin
ball_v <= ball_v - 1;
// Top border collision
if (ball_v < 4) ball_v_direction <= 1;
end
end
end
end
// Draw the pixel for the requested vga location.
always @ (posedge VGA_CLOCK) begin
if (paddle_a) begin
pixel <= 3'b111; // white paddle
end
else if (paddle_b) begin
pixel <= 3'b111; // white paddle
end
else if (border) begin
pixel <= 3'b100; // red border
end
else if (ball && ball_timer_delay == 0) begin
pixel <= 3'b001; // blue ball
end
else if (score_rgb) begin
pixel <= score_rgb;
end
else if (net) begin
pixel <= 3'b110; // yellow net
end
else begin
pixel <= 3'b000; // black
end
end
assign PIXEL = pixel;
assign BALL_H = ball_h;
assign BALL_V = ball_v;
endmodule
|
module top();
// Inputs are registered
reg A_N;
reg B_N;
reg C;
reg D;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Y;
initial
begin
// Initial state is x for all inputs.
A_N = 1'bX;
B_N = 1'bX;
C = 1'bX;
D = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A_N = 1'b0;
#40 B_N = 1'b0;
#60 C = 1'b0;
#80 D = 1'b0;
#100 VGND = 1'b0;
#120 VNB = 1'b0;
#140 VPB = 1'b0;
#160 VPWR = 1'b0;
#180 A_N = 1'b1;
#200 B_N = 1'b1;
#220 C = 1'b1;
#240 D = 1'b1;
#260 VGND = 1'b1;
#280 VNB = 1'b1;
#300 VPB = 1'b1;
#320 VPWR = 1'b1;
#340 A_N = 1'b0;
#360 B_N = 1'b0;
#380 C = 1'b0;
#400 D = 1'b0;
#420 VGND = 1'b0;
#440 VNB = 1'b0;
#460 VPB = 1'b0;
#480 VPWR = 1'b0;
#500 VPWR = 1'b1;
#520 VPB = 1'b1;
#540 VNB = 1'b1;
#560 VGND = 1'b1;
#580 D = 1'b1;
#600 C = 1'b1;
#620 B_N = 1'b1;
#640 A_N = 1'b1;
#660 VPWR = 1'bx;
#680 VPB = 1'bx;
#700 VNB = 1'bx;
#720 VGND = 1'bx;
#740 D = 1'bx;
#760 C = 1'bx;
#780 B_N = 1'bx;
#800 A_N = 1'bx;
end
sky130_fd_sc_hdll__nand4bb dut (.A_N(A_N), .B_N(B_N), .C(C), .D(D), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Y(Y));
endmodule
|
module under test
master_updateable_megarom dut(
.D(D),
.bbc_A(bbc_A),
.flash_A(flash_A),
.flash_nOE(flash_nOE),
.flash_nWE(flash_nWE),
.cpld_SCK_in(spi_sck),
.cpld_MOSI(spi_mosi),
.cpld_SS(spi_ss),
.cpld_MISO(spi_miso),
.cpld_JP(cpld_JP)
);
// clock driver
initial begin
clk = 1'b0;
forever #9 clk = ~clk;
end
// spi process
always @(posedge clk) begin
if (spi_start == 1'b1) begin
$display("- start SPI transaction");
spi_ss <= 1'b0;
spi_count <= 6'd32;
spi_mosi <= spi_d[31]; // first bit
spi_shift <= {spi_d[30:0], 1'b0};
spi_sck <= 1'b0;
end else if (spi_ss == 1'b0) begin
if (spi_count == 0) begin
$display("- end SPI transaction with spi_shift=%x (A %x, rnw %x, wdata %x, rdata %x)",
spi_shift, spi_shift[31:13], spi_shift[12], spi_shift[11:4], spi_shift[7:0]);
spi_ss <= 1'b1; // end of transaction
end else if (spi_sck == 1'b0) begin
spi_sck <= 1'b1;
end else begin
// mid-transaction
spi_mosi <= spi_shift[31];
spi_shift <= {spi_shift[30:0], spi_miso};
spi_count <= spi_count - 1;
spi_sck <= 1'b0;
end;
end
end
always @(negedge dut.allowing_bbc_access) begin
$display("disallowing bbc access");
end
always @(posedge dut.allowing_bbc_access) begin
$display("allowing bbc access");
end
always @(negedge flash_nOE) begin
$display("flash_nOE low with flash_A=%x", flash_A);
end
// flash fixture always reads 0x42
assign D = (flash_nOE == 1'b0) ? 8'h42 : 8'hZZ;
always @(posedge flash_nOE) begin
$display("flash_nOE high with flash_A=%x", flash_A);
end
always @(negedge flash_nWE) begin
$display("flash_nWE low with flash_A=%x and D=%x", flash_A, D);
end
always @(posedge flash_nWE) begin
$display("flash_nWE high with flash_A=%x and D=%x", flash_A, D);
end
initial begin
$display("running master_updateable_megarom_tb");
$dumpfile("master_updateable_megarom_tb.vcd");
$dumpvars(0, master_updateable_megarom_tb);
$display("start");
repeat(10) @(posedge clk);
// check that we start out letting the BBC control the flash
`assert(dut.allowing_bbc_access == 1'b1, "FAIL: not allowing bbc access initially");
$display("\nSetting bbc_A to 12345");
bbc_A <= 17'h12345;
$display("\nTEST that ffffff00 disables BBC access");
spi_d <= 32'hffffff00;
spi_start <= 1;
@(posedge clk);
#1 spi_start <= 0;
@(posedge spi_ss);
@(posedge clk);
`assert(dut.allowing_bbc_access == 1'b0, "FAIL: ffffff00 didn't disable bbc access");
$display("\nTEST that ffffffff reenables BBC access");
spi_d <= 32'hffffffff;
spi_start <= 1;
@(posedge clk);
#1 spi_start <= 0;
@(posedge spi_ss);
@(posedge clk);
`assert(dut.allowing_bbc_access == 1'b1, "FAIL: 32 1's didn't reenable bbc access");
$display("\nTEST that we can write to the flash (51234)");
// message format for a WRITE: 17 address bits, rnw, 8 data bits, 6 zeros (32 bits total)
// with the write happening during the six zeros
spi_d <= {19'b1010001001000110100, 1'b0, 8'b10001001, 4'b0000};
spi_start <= 1;
@(posedge clk);
#1 spi_start <= 0;
@(posedge spi_ss);
`assert(dut.allowing_bbc_access == 1'b0, "FAIL: write operation unlocked bbc access");
$display("\nTEST that we can read from the flash (70f0f)");
// message format for a READ: 17 address bits, rnw, 14 zeros (32 bits total)
// with the data byte returned in the final 8 bits
spi_d <= {19'b1110000111100001111, 1'b1, 12'b0};
spi_start <= 1;
@(posedge clk);
#1 spi_start <= 0;
@(posedge spi_ss);
`assert(dut.allowing_bbc_access == 1'b0, "FAIL: write operation unlocked bbc access");
$display("\nTEST that the unlock process appears correct");
spi_d <= {19'h5555, 1'b0, 8'hAA, 4'b0};
spi_start <= 1;
@(posedge clk);
#1 spi_start <= 0;
@(posedge spi_ss);
spi_d <= {19'h2AAA, 1'b0, 8'h55, 4'b0};
spi_start <= 1;
@(posedge clk);
#1 spi_start <= 0;
@(posedge spi_ss);
spi_d <= {19'h5555, 1'b0, 8'h90, 4'b0};
spi_start <= 1;
@(posedge clk);
#1 spi_start <= 0;
@(posedge spi_ss);
spi_d <= {19'h0, 1'b1, 12'b0};
spi_start <= 1;
@(posedge clk);
#1 spi_start <= 0;
@(posedge spi_ss);
spi_d <= {19'h1, 1'b1, 12'b0};
spi_start <= 1;
@(posedge clk);
#1 spi_start <= 0;
@(posedge spi_ss);
spi_d <= {19'h5555, 1'b0, 8'hF0, 4'b0};
spi_start <= 1;
@(posedge clk);
#1 spi_start <= 0;
@(posedge spi_ss);
$display("^^^ expect write 5555, write 2AAA, write 5555, read 0, read 1, write 5555");
// finish off
$display("running out the clock");
repeat(1000) @(posedge clk);
$display("PASS");
$finish;
end
endmodule
|
module sky130_fd_sc_ms__decap_4 (
VPWR,
VGND,
VPB ,
VNB
);
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ms__decap base (
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
|
module sky130_fd_sc_ms__decap_4 ();
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__decap base ();
endmodule
|
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(s_axi_aclk, s_axi_aresetn, s_axi_awaddr,
s_axi_awvalid, s_axi_awready, s_axi_wdata, s_axi_wstrb, s_axi_wvalid, s_axi_wready,
s_axi_bresp, s_axi_bvalid, s_axi_bready, s_axi_araddr, s_axi_arvalid, s_axi_arready,
s_axi_rdata, s_axi_rresp, s_axi_rvalid, s_axi_rready, gpio_io_i, gpio_io_o, gpio_io_t)
/* synthesis syn_black_box black_box_pad_pin="s_axi_aclk,s_axi_aresetn,s_axi_awaddr[8:0],s_axi_awvalid,s_axi_awready,s_axi_wdata[31:0],s_axi_wstrb[3:0],s_axi_wvalid,s_axi_wready,s_axi_bresp[1:0],s_axi_bvalid,s_axi_bready,s_axi_araddr[8:0],s_axi_arvalid,s_axi_arready,s_axi_rdata[31:0],s_axi_rresp[1:0],s_axi_rvalid,s_axi_rready,gpio_io_i[3:0],gpio_io_o[3:0],gpio_io_t[3:0]" */;
input s_axi_aclk;
input s_axi_aresetn;
input [8:0]s_axi_awaddr;
input s_axi_awvalid;
output s_axi_awready;
input [31:0]s_axi_wdata;
input [3:0]s_axi_wstrb;
input s_axi_wvalid;
output s_axi_wready;
output [1:0]s_axi_bresp;
output s_axi_bvalid;
input s_axi_bready;
input [8:0]s_axi_araddr;
input s_axi_arvalid;
output s_axi_arready;
output [31:0]s_axi_rdata;
output [1:0]s_axi_rresp;
output s_axi_rvalid;
input s_axi_rready;
input [3:0]gpio_io_i;
output [3:0]gpio_io_o;
output [3:0]gpio_io_t;
endmodule
|
module sky130_fd_sc_lp__a31o (
//# {{data|Data Signals}}
input A1,
input A2,
input A3,
input B1,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
|
module WcaReadDwordReg
(
input wire reset, //Active Hi
input wire clock, //System clock, should be synchronous with WcaRegbus
input wire enableIn, //Allows input if specified.
input wire [31:0] in,
//Internal Interface.
input wire [11:0] rbusCtrl, // Address and control lines(12 total) { addr[7:0], readEnable, writeEnable, dataStrobe, clkbus}
inout wire [7:0] rbusData // Tri-state I/O data.
);
parameter my_addr = 0;
wire [7:0] Q0;
wire [7:0] Q1;
wire [7:0] Q2;
wire [7:0] Q3;
wire addrValid = (my_addr == rbusCtrl[11:4]);
wire read = addrValid & rbusCtrl[3];
wire enable = enableIn & ~addrValid; //Latch if address is us.
//Count register for 4 pulse read.
reg [1:0] select;
always @(posedge rbusCtrl[0])
begin
if( reset | ~addrValid)
select <= 2'h0;
else if(rbusCtrl[1] & addrValid)
select <= select + 2'h1;
end
// Only allow latching when addres is not valid. If preparing for a read, everything must be stable.
WcaRegCore8 sr3( .Data(in[31:24]), .Enable( enable ), .Aclr(reset), .Clock(clock), .Q(Q3));
WcaRegCore8 sr2( .Data(in[23:16]), .Enable( enable ), .Aclr(reset), .Clock(clock), .Q(Q2));
WcaRegCore8 sr1( .Data(in[15:8]), .Enable( enable ), .Aclr(reset), .Clock(clock), .Q(Q1));
WcaRegCore8 sr0( .Data(in[7:0]), .Enable( enable ), .Aclr(reset), .Clock(clock), .Q(Q0));
//Place data on the buss if reading.
assign rbusData = (read & select == 2'h3) ? Q3 : 8'bz;
assign rbusData = (read & select == 2'h2) ? Q2 : 8'bz;
assign rbusData = (read & select == 2'h1) ? Q1 : 8'bz;
assign rbusData = (read & select == 2'h0) ? Q0 : 8'bz;
endmodule
|
module sky130_fd_sc_hs__buf (
VPWR,
VGND,
X ,
A
);
// Module ports
input VPWR;
input VGND;
output X ;
input A ;
// Local signals
wire buf0_out_X ;
wire u_vpwr_vgnd0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X , A );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_X, buf0_out_X, VPWR, VGND);
buf buf1 (X , u_vpwr_vgnd0_out_X );
endmodule
|
module sky130_fd_sc_hs__inv (
VPWR,
VGND,
Y ,
A
);
// Module ports
input VPWR;
input VGND;
output Y ;
input A ;
// Local signals
wire not0_out_Y ;
wire u_vpwr_vgnd0_out_Y;
// Name Output Other arguments
not not0 (not0_out_Y , A );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_Y, not0_out_Y, VPWR, VGND);
buf buf0 (Y , u_vpwr_vgnd0_out_Y );
endmodule
|
module serial # (
parameter TRUE = 1'b1,
parameter FALSE = 1'b0,
parameter CLOCK_PER_BAUD_RATE = 5208,
parameter SERIAL_STATE_LAST = 8,
parameter SERIAL_STATE_SENT = 9,
parameter SERIAL_STATE_WAIT = 10
)(
input CLOCK_50M,
// input RX,
output TX,
input [63:0] send_buffer_in,
input [2:0] send_buffer_count_in,
// output [63:0] send_buffer_out,
output [2:0] send_buffer_count_out,
output LED1,
output LED2
);
reg [63:0] send_buffer;
reg [2:0] send_buffer_count;
assign send_buffer_out = send_buffer;
assign send_buffer_count_out = send_buffer_count;
/*
* CLOCK GENERATOR
*/
reg CLOCK = FALSE;
reg [15:0] clock_counter;
always @(posedge CLOCK_50M) begin
if (clock_counter < CLOCK_PER_BAUD_RATE) begin
CLOCK <= FALSE;
clock_counter <= clock_counter + 1;
end
else begin
CLOCK <= TRUE;
clock_counter <= 0;
end
end
/*
* TRANSMIT DATA
*/
// reg serial_state = SERIAL_STATE_WAIT;
reg [7:0] tx_buffer = "A";
reg [3:0] tx_counter = SERIAL_STATE_WAIT; // 0->start bit sent,1=>first bit sent,...8=>wight bit sent,9=>sent, 10=>not send yet
reg tx_state = TRUE;
assign TX = tx_state;
assign LED1 = tx_state;
assign LED2 = TRUE;
// wire send_buffer_input;
// wire send_buffer_count_input;
// assign send_buffer_input = send_buffer;
// assign send_buffer_count_input = send_buffer_count;
always @(posedge CLOCK) begin
if (tx_counter == SERIAL_STATE_WAIT) begin
tx_state <= FALSE;
tx_counter <= 0;
end
else if (tx_counter == SERIAL_STATE_LAST) begin
tx_state <= TRUE;
tx_counter <= SERIAL_STATE_SENT;
end
else if (tx_counter == SERIAL_STATE_SENT && send_buffer_count_in > 0) begin
tx_buffer <= send_buffer_in[7:0];
send_buffer <= send_buffer_in >> 8;
send_buffer_count <= send_buffer_count_in - 1;
end
else begin
tx_state <= tx_buffer[tx_counter];
tx_counter <= tx_counter + 1;
end
end
// function send (
// input dummy
// );
// begin
// tx_buffer = "A";
// tx_counter = SERIAL_STATE_WAIT;
// end
// endfunction
/*
* RECEIVE DATA
*/
// always @(posedge CLOCK) begin
// end
endmodule
|
module bw_r_l2d_rep_bot (/*AUTOARG*/
// Outputs
fuse_l2d_rden_buf, fuse_l2d_wren_buf, si_buf, arst_l_buf, se_buf,
sehold_buf, fuse_l2d_rid_buf, fuse_read_data_in_buf,
fuse_l2d_data_in_buf, word_en_l, col_offset_l, set_l, wr_en_l,
way_sel_l, decc_in_l, scbuf_scdata_fbdecc_top_buf,
scbuf_scdata_fbdecc_bot_buf, sbdt_l, sbdb_l, fuse_clk1_buf,
fuse_clk2_buf, mem_write_disable_buf,
// Inputs
fuse_l2d_rden, fuse_l2d_wren, si, arst_l, se, sehold,
fuse_l2d_rid, fuse_read_data_in, fuse_l2d_data_in, word_en,
col_offset, set, wr_en, way_sel, decc_in, fbdt_l, fbdb_l,
scdata_scbuf_decc_top, scdata_scbuf_decc_bot,
efc_scdata_fuse_clk1, efc_scdata_fuse_clk2, mem_write_disable
);
input fuse_l2d_rden;
input [5:0] fuse_l2d_wren;
input si;
input arst_l;
input se;
input sehold;
input [2:0] fuse_l2d_rid;
input fuse_read_data_in;
input fuse_l2d_data_in;
input [3:0] word_en;
input col_offset;
input [9:0] set;
input wr_en;
input [11:0] way_sel;
input [155:0] decc_in;
input [155:0] fbdt_l;
input [155:0] fbdb_l;
input [155:0] scdata_scbuf_decc_top;
input [155:0] scdata_scbuf_decc_bot;
input efc_scdata_fuse_clk1;
input efc_scdata_fuse_clk2;
input mem_write_disable;
output fuse_l2d_rden_buf;
output [5:0] fuse_l2d_wren_buf;
output si_buf;
output arst_l_buf;
output se_buf;
output sehold_buf;
output [2:0] fuse_l2d_rid_buf;
output fuse_read_data_in_buf;
output fuse_l2d_data_in_buf;
output [3:0] word_en_l;
output col_offset_l;
output [9:0] set_l;
output wr_en_l;
output [11:0] way_sel_l;
output [155:0] decc_in_l;
output [155:0] scbuf_scdata_fbdecc_top_buf;
output [155:0] scbuf_scdata_fbdecc_bot_buf;
output [155:0] sbdt_l;
output [155:0] sbdb_l;
output fuse_clk1_buf;
output fuse_clk2_buf;
output mem_write_disable_buf;
///////////////////////////////////////////////////////////////////////
// Non-inverting Buffers
///////////////////////////////////////////////////////////////////////
assign fuse_l2d_rden_buf = fuse_l2d_rden;
assign fuse_l2d_wren_buf[5:0] = fuse_l2d_wren[5:0];
assign si_buf = si;
assign arst_l_buf = arst_l;
assign se_buf = se;
assign sehold_buf = sehold;
assign fuse_l2d_rid_buf[2:0] = fuse_l2d_rid[2:0];
assign fuse_read_data_in_buf = fuse_read_data_in;
assign fuse_l2d_data_in_buf = fuse_l2d_data_in;
assign fuse_clk1_buf = efc_scdata_fuse_clk1;
assign fuse_clk2_buf = efc_scdata_fuse_clk2;
assign mem_write_disable_buf = mem_write_disable;
///////////////////////////////////////////////////////////////////////
// Inverting Buffers
///////////////////////////////////////////////////////////////////////
assign word_en_l[3:0] = ~word_en[3:0];
assign col_offset_l = ~col_offset;
assign set_l[9:0] = ~set[9:0];
assign wr_en_l = ~wr_en;
assign way_sel_l = ~way_sel;
assign decc_in_l[155:0] = ~decc_in[155:0];
assign scbuf_scdata_fbdecc_top_buf[155:0] = ~fbdt_l[155:0];
assign scbuf_scdata_fbdecc_bot_buf[155:0] = ~fbdb_l[155:0];
assign sbdt_l[155:0] = ~scdata_scbuf_decc_top[155:0];
assign sbdb_l[155:0] = ~scdata_scbuf_decc_bot[155:0];
endmodule
|
module eth_mac_phy_10g_fifo #
(
parameter DATA_WIDTH = 64,
parameter HDR_WIDTH = (DATA_WIDTH/32),
parameter AXIS_DATA_WIDTH = DATA_WIDTH,
parameter AXIS_KEEP_ENABLE = (AXIS_DATA_WIDTH>8),
parameter AXIS_KEEP_WIDTH = (AXIS_DATA_WIDTH/8),
parameter ENABLE_PADDING = 1,
parameter ENABLE_DIC = 1,
parameter MIN_FRAME_LENGTH = 64,
parameter BIT_REVERSE = 0,
parameter SCRAMBLER_DISABLE = 0,
parameter PRBS31_ENABLE = 0,
parameter TX_SERDES_PIPELINE = 0,
parameter RX_SERDES_PIPELINE = 0,
parameter BITSLIP_HIGH_CYCLES = 1,
parameter BITSLIP_LOW_CYCLES = 8,
parameter COUNT_125US = 125000/6.4,
parameter TX_FIFO_DEPTH = 4096,
parameter TX_FIFO_PIPELINE_OUTPUT = 2,
parameter TX_FRAME_FIFO = 1,
parameter TX_DROP_OVERSIZE_FRAME = TX_FRAME_FIFO,
parameter TX_DROP_BAD_FRAME = TX_DROP_OVERSIZE_FRAME,
parameter TX_DROP_WHEN_FULL = 0,
parameter RX_FIFO_DEPTH = 4096,
parameter RX_FIFO_PIPELINE_OUTPUT = 2,
parameter RX_FRAME_FIFO = 1,
parameter RX_DROP_OVERSIZE_FRAME = RX_FRAME_FIFO,
parameter RX_DROP_BAD_FRAME = RX_DROP_OVERSIZE_FRAME,
parameter RX_DROP_WHEN_FULL = RX_DROP_OVERSIZE_FRAME,
parameter PTP_PERIOD_NS = 4'h6,
parameter PTP_PERIOD_FNS = 16'h6666,
parameter PTP_USE_SAMPLE_CLOCK = 0,
parameter TX_PTP_TS_ENABLE = 0,
parameter RX_PTP_TS_ENABLE = 0,
parameter TX_PTP_TS_FIFO_DEPTH = 64,
parameter PTP_TS_WIDTH = 96,
parameter TX_PTP_TAG_ENABLE = 0,
parameter PTP_TAG_WIDTH = 16,
parameter TX_USER_WIDTH = (TX_PTP_TS_ENABLE && TX_PTP_TAG_ENABLE ? PTP_TAG_WIDTH : 0) + 1,
parameter RX_USER_WIDTH = (RX_PTP_TS_ENABLE ? PTP_TS_WIDTH : 0) + 1
)
(
input wire rx_clk,
input wire rx_rst,
input wire tx_clk,
input wire tx_rst,
input wire logic_clk,
input wire logic_rst,
input wire ptp_sample_clk,
/*
* AXI input
*/
input wire [AXIS_DATA_WIDTH-1:0] tx_axis_tdata,
input wire [AXIS_KEEP_WIDTH-1:0] tx_axis_tkeep,
input wire tx_axis_tvalid,
output wire tx_axis_tready,
input wire tx_axis_tlast,
input wire [TX_USER_WIDTH-1:0] tx_axis_tuser,
/*
* Transmit timestamp output
*/
output wire [PTP_TS_WIDTH-1:0] m_axis_tx_ptp_ts_96,
output wire [PTP_TAG_WIDTH-1:0] m_axis_tx_ptp_ts_tag,
output wire m_axis_tx_ptp_ts_valid,
input wire m_axis_tx_ptp_ts_ready,
/*
* AXI output
*/
output wire [AXIS_DATA_WIDTH-1:0] rx_axis_tdata,
output wire [AXIS_KEEP_WIDTH-1:0] rx_axis_tkeep,
output wire rx_axis_tvalid,
input wire rx_axis_tready,
output wire rx_axis_tlast,
output wire [RX_USER_WIDTH-1:0] rx_axis_tuser,
/*
* SERDES interface
*/
output wire [DATA_WIDTH-1:0] serdes_tx_data,
output wire [HDR_WIDTH-1:0] serdes_tx_hdr,
input wire [DATA_WIDTH-1:0] serdes_rx_data,
input wire [HDR_WIDTH-1:0] serdes_rx_hdr,
output wire serdes_rx_bitslip,
/*
* Status
*/
output wire tx_error_underflow,
output wire tx_fifo_overflow,
output wire tx_fifo_bad_frame,
output wire tx_fifo_good_frame,
output wire rx_error_bad_frame,
output wire rx_error_bad_fcs,
output wire rx_bad_block,
output wire rx_block_lock,
output wire rx_high_ber,
output wire rx_fifo_overflow,
output wire rx_fifo_bad_frame,
output wire rx_fifo_good_frame,
/*
* PTP clock
*/
input wire [PTP_TS_WIDTH-1:0] ptp_ts_96,
input wire ptp_ts_step,
/*
* Configuration
*/
input wire [7:0] ifg_delay,
input wire tx_prbs31_enable,
input wire rx_prbs31_enable
);
parameter KEEP_WIDTH = DATA_WIDTH/8;
wire [DATA_WIDTH-1:0] tx_fifo_axis_tdata;
wire [KEEP_WIDTH-1:0] tx_fifo_axis_tkeep;
wire tx_fifo_axis_tvalid;
wire tx_fifo_axis_tready;
wire tx_fifo_axis_tlast;
wire [TX_USER_WIDTH-1:0] tx_fifo_axis_tuser;
wire [DATA_WIDTH-1:0] rx_fifo_axis_tdata;
wire [KEEP_WIDTH-1:0] rx_fifo_axis_tkeep;
wire rx_fifo_axis_tvalid;
wire rx_fifo_axis_tlast;
wire [RX_USER_WIDTH-1:0] rx_fifo_axis_tuser;
wire [PTP_TS_WIDTH-1:0] tx_ptp_ts_96;
wire [PTP_TS_WIDTH-1:0] rx_ptp_ts_96;
wire [PTP_TS_WIDTH-1:0] tx_axis_ptp_ts_96;
wire [PTP_TAG_WIDTH-1:0] tx_axis_ptp_ts_tag;
wire tx_axis_ptp_ts_valid;
// synchronize MAC status signals into logic clock domain
wire tx_error_underflow_int;
reg [0:0] tx_sync_reg_1 = 1'b0;
reg [0:0] tx_sync_reg_2 = 1'b0;
reg [0:0] tx_sync_reg_3 = 1'b0;
reg [0:0] tx_sync_reg_4 = 1'b0;
assign tx_error_underflow = tx_sync_reg_3[0] ^ tx_sync_reg_4[0];
always @(posedge tx_clk or posedge tx_rst) begin
if (tx_rst) begin
tx_sync_reg_1 <= 1'b0;
end else begin
tx_sync_reg_1 <= tx_sync_reg_1 ^ {tx_error_underflow_int};
end
end
always @(posedge logic_clk or posedge logic_rst) begin
if (logic_rst) begin
tx_sync_reg_2 <= 1'b0;
tx_sync_reg_3 <= 1'b0;
tx_sync_reg_4 <= 1'b0;
end else begin
tx_sync_reg_2 <= tx_sync_reg_1;
tx_sync_reg_3 <= tx_sync_reg_2;
tx_sync_reg_4 <= tx_sync_reg_3;
end
end
wire rx_error_bad_frame_int;
wire rx_error_bad_fcs_int;
wire rx_bad_block_int;
wire rx_block_lock_int;
wire rx_high_ber_int;
reg [4:0] rx_sync_reg_1 = 5'd0;
reg [4:0] rx_sync_reg_2 = 5'd0;
reg [4:0] rx_sync_reg_3 = 5'd0;
reg [4:0] rx_sync_reg_4 = 5'd0;
assign rx_error_bad_frame = rx_sync_reg_3[0] ^ rx_sync_reg_4[0];
assign rx_error_bad_fcs = rx_sync_reg_3[1] ^ rx_sync_reg_4[1];
assign rx_bad_block = rx_sync_reg_3[2] ^ rx_sync_reg_4[2];
assign rx_block_lock = rx_sync_reg_3[3] ^ rx_sync_reg_4[3];
assign rx_high_ber = rx_sync_reg_3[4] ^ rx_sync_reg_4[4];
always @(posedge rx_clk or posedge rx_rst) begin
if (rx_rst) begin
rx_sync_reg_1 <= 5'd0;
end else begin
rx_sync_reg_1 <= rx_sync_reg_1 ^ {rx_high_ber_int, rx_block_lock_int, rx_bad_block_int, rx_error_bad_fcs_int, rx_error_bad_frame_int};
end
end
always @(posedge logic_clk or posedge logic_rst) begin
if (logic_rst) begin
rx_sync_reg_2 <= 5'd0;
rx_sync_reg_3 <= 5'd0;
rx_sync_reg_4 <= 5'd0;
end else begin
rx_sync_reg_2 <= rx_sync_reg_1;
rx_sync_reg_3 <= rx_sync_reg_2;
rx_sync_reg_4 <= rx_sync_reg_3;
end
end
// PTP timestamping
generate
if (TX_PTP_TS_ENABLE) begin
ptp_clock_cdc #(
.TS_WIDTH(PTP_TS_WIDTH),
.NS_WIDTH(4),
.FNS_WIDTH(16),
.USE_SAMPLE_CLOCK(PTP_USE_SAMPLE_CLOCK)
)
tx_ptp_cdc (
.input_clk(logic_clk),
.input_rst(logic_rst),
.output_clk(tx_clk),
.output_rst(tx_rst),
.sample_clk(ptp_sample_clk),
.input_ts(ptp_ts_96),
.input_ts_step(ptp_ts_step),
.output_ts(tx_ptp_ts_96),
.output_ts_step(),
.output_pps(),
.locked()
);
axis_async_fifo #(
.DEPTH(TX_PTP_TS_FIFO_DEPTH),
.DATA_WIDTH(PTP_TS_WIDTH),
.KEEP_ENABLE(0),
.LAST_ENABLE(0),
.ID_ENABLE(TX_PTP_TAG_ENABLE),
.ID_WIDTH(PTP_TAG_WIDTH),
.DEST_ENABLE(0),
.USER_ENABLE(0),
.FRAME_FIFO(0)
)
tx_ptp_ts_fifo (
.async_rst(logic_rst | tx_rst),
// AXI input
.s_clk(tx_clk),
.s_axis_tdata(tx_axis_ptp_ts_96),
.s_axis_tkeep(0),
.s_axis_tvalid(tx_axis_ptp_ts_valid),
.s_axis_tready(),
.s_axis_tlast(0),
.s_axis_tid(tx_axis_ptp_ts_tag),
.s_axis_tdest(0),
.s_axis_tuser(0),
// AXI output
.m_clk(logic_clk),
.m_axis_tdata(m_axis_tx_ptp_ts_96),
.m_axis_tkeep(),
.m_axis_tvalid(m_axis_tx_ptp_ts_valid),
.m_axis_tready(m_axis_tx_ptp_ts_ready),
.m_axis_tlast(),
.m_axis_tid(m_axis_tx_ptp_ts_tag),
.m_axis_tdest(),
.m_axis_tuser(),
// Status
.s_status_overflow(),
.s_status_bad_frame(),
.s_status_good_frame(),
.m_status_overflow(),
.m_status_bad_frame(),
.m_status_good_frame()
);
end else begin
assign m_axis_tx_ptp_ts_96 = {PTP_TS_WIDTH{1'b0}};
assign m_axis_tx_ptp_ts_tag = {PTP_TAG_WIDTH{1'b0}};
assign m_axis_tx_ptp_ts_valid = 1'b0;
assign tx_ptp_ts_96 = {PTP_TS_WIDTH{1'b0}};
end
if (RX_PTP_TS_ENABLE) begin
ptp_clock_cdc #(
.TS_WIDTH(PTP_TS_WIDTH),
.NS_WIDTH(4),
.FNS_WIDTH(16),
.USE_SAMPLE_CLOCK(PTP_USE_SAMPLE_CLOCK)
)
rx_ptp_cdc (
.input_clk(logic_clk),
.input_rst(logic_rst),
.output_clk(rx_clk),
.output_rst(rx_rst),
.sample_clk(ptp_sample_clk),
.input_ts(ptp_ts_96),
.input_ts_step(ptp_ts_step),
.output_ts(rx_ptp_ts_96),
.output_ts_step(),
.output_pps(),
.locked()
);
end else begin
assign rx_ptp_ts_96 = {PTP_TS_WIDTH{1'b0}};
end
endgenerate
eth_mac_phy_10g #(
.DATA_WIDTH(DATA_WIDTH),
.KEEP_WIDTH(KEEP_WIDTH),
.HDR_WIDTH(HDR_WIDTH),
.ENABLE_PADDING(ENABLE_PADDING),
.ENABLE_DIC(ENABLE_DIC),
.MIN_FRAME_LENGTH(MIN_FRAME_LENGTH),
.PTP_PERIOD_NS(PTP_PERIOD_NS),
.PTP_PERIOD_FNS(PTP_PERIOD_FNS),
.TX_PTP_TS_ENABLE(TX_PTP_TS_ENABLE),
.TX_PTP_TS_WIDTH(PTP_TS_WIDTH),
.TX_PTP_TAG_ENABLE(TX_PTP_TAG_ENABLE),
.TX_PTP_TAG_WIDTH(PTP_TAG_WIDTH),
.RX_PTP_TS_ENABLE(RX_PTP_TS_ENABLE),
.RX_PTP_TS_WIDTH(PTP_TS_WIDTH),
.TX_USER_WIDTH(TX_USER_WIDTH),
.RX_USER_WIDTH(RX_USER_WIDTH),
.BIT_REVERSE(BIT_REVERSE),
.SCRAMBLER_DISABLE(SCRAMBLER_DISABLE),
.PRBS31_ENABLE(PRBS31_ENABLE),
.TX_SERDES_PIPELINE(TX_SERDES_PIPELINE),
.RX_SERDES_PIPELINE(RX_SERDES_PIPELINE),
.BITSLIP_HIGH_CYCLES(BITSLIP_HIGH_CYCLES),
.BITSLIP_LOW_CYCLES(BITSLIP_LOW_CYCLES),
.COUNT_125US(COUNT_125US)
)
eth_mac_phy_10g_inst (
.tx_clk(tx_clk),
.tx_rst(tx_rst),
.rx_clk(rx_clk),
.rx_rst(rx_rst),
.tx_axis_tdata(tx_fifo_axis_tdata),
.tx_axis_tkeep(tx_fifo_axis_tkeep),
.tx_axis_tvalid(tx_fifo_axis_tvalid),
.tx_axis_tready(tx_fifo_axis_tready),
.tx_axis_tlast(tx_fifo_axis_tlast),
.tx_axis_tuser(tx_fifo_axis_tuser),
.rx_axis_tdata(rx_fifo_axis_tdata),
.rx_axis_tkeep(rx_fifo_axis_tkeep),
.rx_axis_tvalid(rx_fifo_axis_tvalid),
.rx_axis_tlast(rx_fifo_axis_tlast),
.rx_axis_tuser(rx_fifo_axis_tuser),
.serdes_tx_data(serdes_tx_data),
.serdes_tx_hdr(serdes_tx_hdr),
.serdes_rx_data(serdes_rx_data),
.serdes_rx_hdr(serdes_rx_hdr),
.serdes_rx_bitslip(serdes_rx_bitslip),
.tx_ptp_ts(tx_ptp_ts_96),
.rx_ptp_ts(rx_ptp_ts_96),
.tx_axis_ptp_ts(tx_axis_ptp_ts_96),
.tx_axis_ptp_ts_tag(tx_axis_ptp_ts_tag),
.tx_axis_ptp_ts_valid(tx_axis_ptp_ts_valid),
.tx_error_underflow(tx_error_underflow_int),
.rx_error_bad_frame(rx_error_bad_frame_int),
.rx_error_bad_fcs(rx_error_bad_fcs_int),
.rx_bad_block(rx_bad_block_int),
.rx_block_lock(rx_block_lock_int),
.rx_high_ber(rx_high_ber_int),
.ifg_delay(ifg_delay),
.tx_prbs31_enable(tx_prbs31_enable),
.rx_prbs31_enable(rx_prbs31_enable)
);
axis_async_fifo_adapter #(
.DEPTH(TX_FIFO_DEPTH),
.S_DATA_WIDTH(AXIS_DATA_WIDTH),
.S_KEEP_ENABLE(AXIS_KEEP_ENABLE),
.S_KEEP_WIDTH(AXIS_KEEP_WIDTH),
.M_DATA_WIDTH(DATA_WIDTH),
.M_KEEP_ENABLE(1),
.M_KEEP_WIDTH(KEEP_WIDTH),
.ID_ENABLE(0),
.DEST_ENABLE(0),
.USER_ENABLE(1),
.USER_WIDTH(TX_USER_WIDTH),
.PIPELINE_OUTPUT(TX_FIFO_PIPELINE_OUTPUT),
.FRAME_FIFO(TX_FRAME_FIFO),
.USER_BAD_FRAME_VALUE(1'b1),
.USER_BAD_FRAME_MASK(1'b1),
.DROP_OVERSIZE_FRAME(TX_DROP_OVERSIZE_FRAME),
.DROP_BAD_FRAME(TX_DROP_BAD_FRAME),
.DROP_WHEN_FULL(TX_DROP_WHEN_FULL)
)
tx_fifo (
// AXI input
.s_clk(logic_clk),
.s_rst(logic_rst),
.s_axis_tdata(tx_axis_tdata),
.s_axis_tkeep(tx_axis_tkeep),
.s_axis_tvalid(tx_axis_tvalid),
.s_axis_tready(tx_axis_tready),
.s_axis_tlast(tx_axis_tlast),
.s_axis_tid(0),
.s_axis_tdest(0),
.s_axis_tuser(tx_axis_tuser),
// AXI output
.m_clk(tx_clk),
.m_rst(tx_rst),
.m_axis_tdata(tx_fifo_axis_tdata),
.m_axis_tkeep(tx_fifo_axis_tkeep),
.m_axis_tvalid(tx_fifo_axis_tvalid),
.m_axis_tready(tx_fifo_axis_tready),
.m_axis_tlast(tx_fifo_axis_tlast),
.m_axis_tid(),
.m_axis_tdest(),
.m_axis_tuser(tx_fifo_axis_tuser),
// Status
.s_status_overflow(tx_fifo_overflow),
.s_status_bad_frame(tx_fifo_bad_frame),
.s_status_good_frame(tx_fifo_good_frame),
.m_status_overflow(),
.m_status_bad_frame(),
.m_status_good_frame()
);
axis_async_fifo_adapter #(
.DEPTH(RX_FIFO_DEPTH),
.S_DATA_WIDTH(DATA_WIDTH),
.S_KEEP_ENABLE(1),
.S_KEEP_WIDTH(KEEP_WIDTH),
.M_DATA_WIDTH(AXIS_DATA_WIDTH),
.M_KEEP_ENABLE(AXIS_KEEP_ENABLE),
.M_KEEP_WIDTH(AXIS_KEEP_WIDTH),
.ID_ENABLE(0),
.DEST_ENABLE(0),
.USER_ENABLE(1),
.USER_WIDTH(RX_USER_WIDTH),
.PIPELINE_OUTPUT(RX_FIFO_PIPELINE_OUTPUT),
.FRAME_FIFO(RX_FRAME_FIFO),
.USER_BAD_FRAME_VALUE(1'b1),
.USER_BAD_FRAME_MASK(1'b1),
.DROP_OVERSIZE_FRAME(RX_DROP_OVERSIZE_FRAME),
.DROP_BAD_FRAME(RX_DROP_BAD_FRAME),
.DROP_WHEN_FULL(RX_DROP_WHEN_FULL)
)
rx_fifo (
// AXI input
.s_clk(rx_clk),
.s_rst(rx_rst),
.s_axis_tdata(rx_fifo_axis_tdata),
.s_axis_tkeep(rx_fifo_axis_tkeep),
.s_axis_tvalid(rx_fifo_axis_tvalid),
.s_axis_tready(),
.s_axis_tlast(rx_fifo_axis_tlast),
.s_axis_tid(0),
.s_axis_tdest(0),
.s_axis_tuser(rx_fifo_axis_tuser),
// AXI output
.m_clk(logic_clk),
.m_rst(logic_rst),
.m_axis_tdata(rx_axis_tdata),
.m_axis_tkeep(rx_axis_tkeep),
.m_axis_tvalid(rx_axis_tvalid),
.m_axis_tready(rx_axis_tready),
.m_axis_tlast(rx_axis_tlast),
.m_axis_tid(),
.m_axis_tdest(),
.m_axis_tuser(rx_axis_tuser),
// Status
.s_status_overflow(),
.s_status_bad_frame(),
.s_status_good_frame(),
.m_status_overflow(rx_fifo_overflow),
.m_status_bad_frame(rx_fifo_bad_frame),
.m_status_good_frame(rx_fifo_good_frame)
);
endmodule
|
module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
fifo_depths_check ( .error(1'b1) );
end
endgenerate
altera_avalon_st_jtag_interface #(
.PURPOSE (1),
.UPSTREAM_FIFO_SIZE (0),
.DOWNSTREAM_FIFO_SIZE (64),
.MGMT_CHANNEL_WIDTH (-1),
.EXPORT_JTAG (0),
.USE_PLI (0),
.PLI_PORT (50000)
) jtag_phy_embedded_in_jtag_master (
.clk (clk_clk), // input, width = 1, clock.clk
.reset_n (~rst_controller_reset_out_reset), // input, width = 1, clock_reset.reset_n
.source_data (jtag_phy_embedded_in_jtag_master_src_data), // output, width = 8, src.data
.source_valid (jtag_phy_embedded_in_jtag_master_src_valid), // output, width = 1, .valid
.sink_data (p2b_out_bytes_stream_data), // input, width = 8, sink.data
.sink_valid (p2b_out_bytes_stream_valid), // input, width = 1, .valid
.sink_ready (p2b_out_bytes_stream_ready), // output, width = 1, .ready
.resetrequest (master_reset_reset), // output, width = 1, resetrequest.reset
.source_ready (1'b1), // (terminated),
.mgmt_valid (), // (terminated),
.mgmt_channel (), // (terminated),
.mgmt_data (), // (terminated),
.jtag_tck (1'b0), // (terminated),
.jtag_tms (1'b0), // (terminated),
.jtag_tdi (1'b0), // (terminated),
.jtag_tdo (), // (terminated),
.jtag_ena (1'b0), // (terminated),
.jtag_usr1 (1'b0), // (terminated),
.jtag_clr (1'b0), // (terminated),
.jtag_clrn (1'b0), // (terminated),
.jtag_state_tlr (1'b0), // (terminated),
.jtag_state_rti (1'b0), // (terminated),
.jtag_state_sdrs (1'b0), // (terminated),
.jtag_state_cdr (1'b0), // (terminated),
.jtag_state_sdr (1'b0), // (terminated),
.jtag_state_e1dr (1'b0), // (terminated),
.jtag_state_pdr (1'b0), // (terminated),
.jtag_state_e2dr (1'b0), // (terminated),
.jtag_state_udr (1'b0), // (terminated),
.jtag_state_sirs (1'b0), // (terminated),
.jtag_state_cir (1'b0), // (terminated),
.jtag_state_sir (1'b0), // (terminated),
.jtag_state_e1ir (1'b0), // (terminated),
.jtag_state_pir (1'b0), // (terminated),
.jtag_state_e2ir (1'b0), // (terminated),
.jtag_state_uir (1'b0), // (terminated),
.jtag_ir_in (3'b000), // (terminated),
.jtag_irq (), // (terminated),
.jtag_ir_out () // (terminated),
);
ghrd_10as066n2_hps_m_timing_adapter_171_xf5weri timing_adt (
.clk (clk_clk), // input, width = 1, clk.clk
.reset_n (~rst_controller_reset_out_reset), // input, width = 1, reset.reset_n
.in_data (jtag_phy_embedded_in_jtag_master_src_data), // input, width = 8, in.data
.in_valid (jtag_phy_embedded_in_jtag_master_src_valid), // input, width = 1, .valid
.out_data (timing_adt_out_data), // output, width = 8, out.data
.out_valid (timing_adt_out_valid), // output, width = 1, .valid
.out_ready (timing_adt_out_ready) // input, width = 1, .ready
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (8),
.FIFO_DEPTH (64),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (0),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (3),
.USE_MEMORY_BLOCKS (1),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) fifo (
.clk (clk_clk), // input, width = 1, clk.clk
.reset (rst_controller_reset_out_reset), // input, width = 1, clk_reset.reset
.in_data (timing_adt_out_data), // input, width = 8, in.data
.in_valid (timing_adt_out_valid), // input, width = 1, .valid
.in_ready (timing_adt_out_ready), // output, width = 1, .ready
.out_data (fifo_out_data), // output, width = 8, out.data
.out_valid (fifo_out_valid), // output, width = 1, .valid
.out_ready (fifo_out_ready), // input, width = 1, .ready
.csr_address (2'b00), // (terminated),
.csr_read (1'b0), // (terminated),
.csr_write (1'b0), // (terminated),
.csr_readdata (), // (terminated),
.csr_writedata (32'b00000000000000000000000000000000), // (terminated),
.almost_full_data (), // (terminated),
.almost_empty_data (), // (terminated),
.in_startofpacket (1'b0), // (terminated),
.in_endofpacket (1'b0), // (terminated),
.out_startofpacket (), // (terminated),
.out_endofpacket (), // (terminated),
.in_empty (1'b0), // (terminated),
.out_empty (), // (terminated),
.in_error (1'b0), // (terminated),
.out_error (), // (terminated),
.in_channel (1'b0), // (terminated),
.out_channel () // (terminated),
);
altera_avalon_st_bytes_to_packets #(
.CHANNEL_WIDTH (8),
.ENCODING (0)
) b2p (
.clk (clk_clk), // input, width = 1, clk.clk
.reset_n (~rst_controller_reset_out_reset), // input, width = 1, clk_reset.reset_n
.out_channel (b2p_out_packets_stream_channel), // output, width = 8, out_packets_stream.channel
.out_ready (b2p_out_packets_stream_ready), // input, width = 1, .ready
.out_valid (b2p_out_packets_stream_valid), // output, width = 1, .valid
.out_data (b2p_out_packets_stream_data), // output, width = 8, .data
.out_startofpacket (b2p_out_packets_stream_startofpacket), // output, width = 1, .startofpacket
.out_endofpacket (b2p_out_packets_stream_endofpacket), // output, width = 1, .endofpacket
.in_ready (fifo_out_ready), // output, width = 1, in_bytes_stream.ready
.in_valid (fifo_out_valid), // input, width = 1, .valid
.in_data (fifo_out_data) // input, width = 8, .data
);
altera_avalon_st_packets_to_bytes #(
.CHANNEL_WIDTH (8),
.ENCODING (0)
) p2b (
.clk (clk_clk), // input, width = 1, clk.clk
.reset_n (~rst_controller_reset_out_reset), // input, width = 1, clk_reset.reset_n
.in_ready (p2b_adapter_out_ready), // output, width = 1, in_packets_stream.ready
.in_valid (p2b_adapter_out_valid), // input, width = 1, .valid
.in_data (p2b_adapter_out_data), // input, width = 8, .data
.in_channel (p2b_adapter_out_channel), // input, width = 8, .channel
.in_startofpacket (p2b_adapter_out_startofpacket), // input, width = 1, .startofpacket
.in_endofpacket (p2b_adapter_out_endofpacket), // input, width = 1, .endofpacket
.out_ready (p2b_out_bytes_stream_ready), // input, width = 1, out_bytes_stream.ready
.out_valid (p2b_out_bytes_stream_valid), // output, width = 1, .valid
.out_data (p2b_out_bytes_stream_data) // output, width = 8, .data
);
altera_avalon_packets_to_master #(
.FAST_VER (0),
.FIFO_DEPTHS (2),
.FIFO_WIDTHU (1)
) transacto (
.clk (clk_clk), // input, width = 1, clk.clk
.reset_n (~rst_controller_reset_out_reset), // input, width = 1, clk_reset.reset_n
.out_ready (transacto_out_stream_ready), // input, width = 1, out_stream.ready
.out_valid (transacto_out_stream_valid), // output, width = 1, .valid
.out_data (transacto_out_stream_data), // output, width = 8, .data
.out_startofpacket (transacto_out_stream_startofpacket), // output, width = 1, .startofpacket
.out_endofpacket (transacto_out_stream_endofpacket), // output, width = 1, .endofpacket
.in_ready (b2p_adapter_out_ready), // output, width = 1, in_stream.ready
.in_valid (b2p_adapter_out_valid), // input, width = 1, .valid
.in_data (b2p_adapter_out_data), // input, width = 8, .data
.in_startofpacket (b2p_adapter_out_startofpacket), // input, width = 1, .startofpacket
.in_endofpacket (b2p_adapter_out_endofpacket), // input, width = 1, .endofpacket
.address (master_address), // output, width = 32, avalon_master.address
.readdata (master_readdata), // input, width = 32, .readdata
.read (master_read), // output, width = 1, .read
.write (master_write), // output, width = 1, .write
.writedata (master_writedata), // output, width = 32, .writedata
.waitrequest (master_waitrequest), // input, width = 1, .waitrequest
.readdatavalid (master_readdatavalid), // input, width = 1, .readdatavalid
.byteenable (master_byteenable) // output, width = 4, .byteenable
);
ghrd_10as066n2_hps_m_channel_adapter_171_2swajja b2p_adapter (
.clk (clk_clk), // input, width = 1, clk.clk
.reset_n (~rst_controller_reset_out_reset), // input, width = 1, reset.reset_n
.in_data (b2p_out_packets_stream_data), // input, width = 8, in.data
.in_valid (b2p_out_packets_stream_valid), // input, width = 1, .valid
.in_ready (b2p_out_packets_stream_ready), // output, width = 1, .ready
.in_startofpacket (b2p_out_packets_stream_startofpacket), // input, width = 1, .startofpacket
.in_endofpacket (b2p_out_packets_stream_endofpacket), // input, width = 1, .endofpacket
.in_channel (b2p_out_packets_stream_channel), // input, width = 8, .channel
.out_data (b2p_adapter_out_data), // output, width = 8, out.data
.out_valid (b2p_adapter_out_valid), // output, width = 1, .valid
.out_ready (b2p_adapter_out_ready), // input, width = 1, .ready
.out_startofpacket (b2p_adapter_out_startofpacket), // output, width = 1, .startofpacket
.out_endofpacket (b2p_adapter_out_endofpacket) // output, width = 1, .endofpacket
);
ghrd_10as066n2_hps_m_channel_adapter_171_vh2yu6y p2b_adapter (
.clk (clk_clk), // input, width = 1, clk.clk
.reset_n (~rst_controller_reset_out_reset), // input, width = 1, reset.reset_n
.in_data (transacto_out_stream_data), // input, width = 8, in.data
.in_valid (transacto_out_stream_valid), // input, width = 1, .valid
.in_ready (transacto_out_stream_ready), // output, width = 1, .ready
.in_startofpacket (transacto_out_stream_startofpacket), // input, width = 1, .startofpacket
.in_endofpacket (transacto_out_stream_endofpacket), // input, width = 1, .endofpacket
.out_data (p2b_adapter_out_data), // output, width = 8, out.data
.out_valid (p2b_adapter_out_valid), // output, width = 1, .valid
.out_ready (p2b_adapter_out_ready), // input, width = 1, .ready
.out_startofpacket (p2b_adapter_out_startofpacket), // output, width = 1, .startofpacket
.out_endofpacket (p2b_adapter_out_endofpacket), // output, width = 1, .endofpacket
.out_channel (p2b_adapter_out_channel) // output, width = 8, .channel
);
altera_reset_controller #(
.NUM_RESET_INPUTS (1),
.OUTPUT_RESET_SYNC_EDGES ("deassert"),
.SYNC_DEPTH (2),
.RESET_REQUEST_PRESENT (0),
.RESET_REQ_WAIT_TIME (1),
.MIN_RST_ASSERTION_TIME (3),
.RESET_REQ_EARLY_DSRT_TIME (1),
.USE_RESET_REQUEST_IN0 (0),
.USE_RESET_REQUEST_IN1 (0),
.USE_RESET_REQUEST_IN2 (0),
.USE_RESET_REQUEST_IN3 (0),
.USE_RESET_REQUEST_IN4 (0),
.USE_RESET_REQUEST_IN5 (0),
.USE_RESET_REQUEST_IN6 (0),
.USE_RESET_REQUEST_IN7 (0),
.USE_RESET_REQUEST_IN8 (0),
.USE_RESET_REQUEST_IN9 (0),
.USE_RESET_REQUEST_IN10 (0),
.USE_RESET_REQUEST_IN11 (0),
.USE_RESET_REQUEST_IN12 (0),
.USE_RESET_REQUEST_IN13 (0),
.USE_RESET_REQUEST_IN14 (0),
.USE_RESET_REQUEST_IN15 (0),
.ADAPT_RESET_REQUEST (0)
) rst_controller (
.reset_in0 (clk_reset_reset), // input, width = 1, reset_in0.reset
.clk (clk_clk), // input, width = 1, clk.clk
.reset_out (rst_controller_reset_out_reset), // output, width = 1, reset_out.reset
.reset_req (), // (terminated),
.reset_req_in0 (1'b0), // (terminated),
.reset_in1 (1'b0), // (terminated),
.reset_req_in1 (1'b0), // (terminated),
.reset_in2 (1'b0), // (terminated),
.reset_req_in2 (1'b0), // (terminated),
.reset_in3 (1'b0), // (terminated),
.reset_req_in3 (1'b0), // (terminated),
.reset_in4 (1'b0), // (terminated),
.reset_req_in4 (1'b0), // (terminated),
.reset_in5 (1'b0), // (terminated),
.reset_req_in5 (1'b0), // (terminated),
.reset_in6 (1'b0), // (terminated),
.reset_req_in6 (1'b0), // (terminated),
.reset_in7 (1'b0), // (terminated),
.reset_req_in7 (1'b0), // (terminated),
.reset_in8 (1'b0), // (terminated),
.reset_req_in8 (1'b0), // (terminated),
.reset_in9 (1'b0), // (terminated),
.reset_req_in9 (1'b0), // (terminated),
.reset_in10 (1'b0), // (terminated),
.reset_req_in10 (1'b0), // (terminated),
.reset_in11 (1'b0), // (terminated),
.reset_req_in11 (1'b0), // (terminated),
.reset_in12 (1'b0), // (terminated),
.reset_req_in12 (1'b0), // (terminated),
.reset_in13 (1'b0), // (terminated),
.reset_req_in13 (1'b0), // (terminated),
.reset_in14 (1'b0), // (terminated),
.reset_req_in14 (1'b0), // (terminated),
.reset_in15 (1'b0), // (terminated),
.reset_req_in15 (1'b0) // (terminated),
);
endmodule
|
module altera_onchip_flash_avmm_data_controller (
// To/From System
clock,
reset_n,
// To/From Flash IP interface
flash_busy,
flash_se_pass,
flash_sp_pass,
flash_osc,
flash_drdout,
flash_xe_ye,
flash_se,
flash_arclk,
flash_arshft,
flash_drclk,
flash_drshft,
flash_drdin,
flash_nprogram,
flash_nerase,
flash_ardin,
// To/From Avalon_MM data slave interface
avmm_read,
avmm_write,
avmm_addr,
avmm_writedata,
avmm_burstcount,
avmm_waitrequest,
avmm_readdatavalid,
avmm_readdata,
// To/From Avalon_MM csr slave interface
csr_control,
csr_status
);
parameter READ_AND_WRITE_MODE = 0;
parameter WRAPPING_BURST_MODE = 0;
parameter DATA_WIDTH = 32;
parameter AVMM_DATA_ADDR_WIDTH = 20;
parameter AVMM_DATA_BURSTCOUNT_WIDTH = 4;
parameter FLASH_ADDR_WIDTH = 23;
parameter FLASH_SEQ_READ_DATA_COUNT = 2; //number of 32-bit data per sequential read
parameter FLASH_READ_CYCLE_MAX_INDEX = 3; //period to for each sequential read
parameter FLASH_ADDR_ALIGNMENT_BITS = 1; //number of last addr bits for alignment
parameter FLASH_RESET_CYCLE_MAX_INDEX = 28; //period that required by flash before back to idle for erase and program operation
parameter FLASH_BUSY_TIMEOUT_CYCLE_MAX_INDEX = 112; //flash busy timeout period (1200ns)
parameter FLASH_ERASE_TIMEOUT_CYCLE_MAX_INDEX = 40603248; //erase timeout period (350ms)
parameter FLASH_WRITE_TIMEOUT_CYCLE_MAX_INDEX = 35382; //write timeout period (305us)
parameter MIN_VALID_ADDR = 1;
parameter MAX_VALID_ADDR = 1;
parameter SECTOR1_START_ADDR = 1;
parameter SECTOR1_END_ADDR = 1;
parameter SECTOR2_START_ADDR = 1;
parameter SECTOR2_END_ADDR = 1;
parameter SECTOR3_START_ADDR = 1;
parameter SECTOR3_END_ADDR = 1;
parameter SECTOR4_START_ADDR = 1;
parameter SECTOR4_END_ADDR = 1;
parameter SECTOR5_START_ADDR = 1;
parameter SECTOR5_END_ADDR = 1;
parameter SECTOR_READ_PROTECTION_MODE = 5'b11111;
parameter SECTOR1_MAP = 1;
parameter SECTOR2_MAP = 1;
parameter SECTOR3_MAP = 1;
parameter SECTOR4_MAP = 1;
parameter SECTOR5_MAP = 1;
parameter ADDR_RANGE1_END_ADDR = 1;
parameter ADDR_RANGE2_END_ADDR = 1;
parameter ADDR_RANGE1_OFFSET = 1;
parameter ADDR_RANGE2_OFFSET = 1;
parameter ADDR_RANGE3_OFFSET = 1;
localparam [1:0] ERASE_ST_IDLE = 0,
ERASE_ST_PENDING = 1,
ERASE_ST_BUSY = 2;
localparam [1:0] STATUS_IDLE = 0,
STATUS_BUSY_ERASE = 1,
STATUS_BUSY_WRITE = 2,
STATUS_BUSY_READ = 3;
localparam [2:0] WRITE_STATE_IDLE = 0,
WRITE_STATE_ADDR = 1,
WRITE_STATE_WRITE = 2,
WRITE_STATE_WAIT_BUSY = 3,
WRITE_STATE_WAIT_DONE = 4,
WRITE_STATE_RESET = 5,
WRITE_STATE_ERROR = 6;
localparam [2:0] ERASE_STATE_IDLE = 0,
ERASE_STATE_ADDR = 1,
ERASE_STATE_WAIT_BUSY = 2,
ERASE_STATE_WAIT_DONE = 3,
ERASE_STATE_RESET = 4,
ERASE_STATE_ERROR = 5;
localparam [2:0] READ_STATE_IDLE = 0,
READ_STATE_ADDR = 1,
READ_STATE_READ = 2,
READ_STATE_SETUP = 2,
READ_STATE_DUMMY = 3,
READ_STATE_READY = 4,
READ_STATE_FINAL = 5,
READ_STATE_CLEAR = 6,
READ_STATE_PULSE_SE = 7;
localparam [0:0] READ_SETUP = 0,
READ_RECV_DATA = 1;
localparam [1:0] READ_VALID_IDLE = 0,
READ_VALID_READING = 1,
READ_VALID_PRE_READING = 2;
// To/From System
input clock;
input reset_n;
// To/From Flash IP interface
input flash_busy;
input flash_se_pass;
input flash_sp_pass;
input flash_osc;
input [DATA_WIDTH-1:0] flash_drdout;
output flash_xe_ye;
output flash_se;
output flash_arclk;
output flash_arshft;
output flash_drclk;
output flash_drshft;
output flash_drdin;
output flash_nprogram;
output flash_nerase;
output [FLASH_ADDR_WIDTH-1:0] flash_ardin;
// To/From Avalon_MM data slave interface
input avmm_read;
input avmm_write;
input [AVMM_DATA_ADDR_WIDTH-1:0] avmm_addr;
input [DATA_WIDTH-1:0] avmm_writedata;
input [AVMM_DATA_BURSTCOUNT_WIDTH-1:0] avmm_burstcount;
output avmm_waitrequest;
output avmm_readdatavalid;
output reg [DATA_WIDTH-1:0] avmm_readdata;
// To/From Avalon_MM csr slave interface
input [31:0] csr_control;
output [9:0] csr_status;
reg reset_n_reg1;
reg reset_n_reg2;
reg [1:0] csr_status_busy;
reg csr_status_e_pass;
reg csr_status_w_pass;
reg csr_status_r_pass;
reg [2:0] erase_state;
reg [2:0] write_state;
reg [2:0] read_state;
reg avmm_read_state;
reg [1:0] avmm_read_valid_state;
reg avmm_readdatavalid_reg;
reg avmm_readdata_ready;
reg [2:0] flash_sector_addr;
reg [FLASH_ADDR_WIDTH-1:0] flash_page_addr;
reg [FLASH_ADDR_WIDTH-1:0] flash_seq_read_ardin;
reg [FLASH_ADDR_WIDTH-1:0] flash_addr_wire_neg_reg;
reg [FLASH_ADDR_ALIGNMENT_BITS-1:0] flash_ardin_align_reg;
reg [FLASH_ADDR_ALIGNMENT_BITS-1:0] flash_ardin_align_backup_reg;
reg [AVMM_DATA_BURSTCOUNT_WIDTH-1:0] avmm_burstcount_input_reg;
reg [AVMM_DATA_BURSTCOUNT_WIDTH-1:0] avmm_burstcount_reg;
reg write_drclk_en;
reg read_drclk_en;
reg enable_arclk_sync_reg;
reg enable_arclk_neg_reg;
reg enable_arclk_neg_pos_reg;
reg enable_drclk_neg_reg;
reg enable_drclk_neg_pos_reg;
reg enable_drclk_neg_pos_write_reg;
reg flash_drdin_neg_reg;
reg [15:0] write_count;
reg [25:0] erase_count;
reg [2:0] read_count;
reg [2:0] read_ctrl_count;
reg [2:0] data_count;
reg write_timeout;
reg write_wait;
reg write_wait_neg;
reg erase_timeout;
reg read_wait;
reg read_wait_neg;
reg flash_drshft_reg;
reg flash_drshft_neg_reg;
reg flash_se_neg_reg;
reg flash_se_pass_reg;
reg flash_sp_pass_reg;
reg flash_busy_reg;
reg flash_busy_clear_reg;
reg erase_busy_scan;
reg write_busy_scan;
reg is_sector1_writable_reg;
reg is_sector2_writable_reg;
reg is_sector3_writable_reg;
reg is_sector4_writable_reg;
reg is_sector5_writable_reg;
wire reset_n_w;
wire is_addr_within_valid_range;
wire is_addr_writable;
wire is_sector_writable;
wire is_erase_addr_writable;
wire [2:0] cur_e_addr;
wire [FLASH_ADDR_WIDTH-1:0] cur_a_addr;
wire [FLASH_ADDR_WIDTH-1:0] cur_read_addr;
wire [FLASH_ADDR_WIDTH-1:0] flash_addr_wire;
wire [FLASH_ADDR_WIDTH-1:0] flash_page_addr_wire;
wire [2:0] flash_sector_wire;
wire is_valid_write_burst_count;
wire is_erase_busy;
wire is_write_busy;
wire is_read_busy;
wire [FLASH_ADDR_WIDTH-1:0] flash_read_addr;
wire [FLASH_ADDR_WIDTH-1:0] next_flash_read_ardin;
wire [19:0] csr_page_erase_addr;
wire [2:0] csr_sector_erase_addr;
wire valid_csr_sector_erase_addr;
wire [1:0] csr_erase_state;
wire [4:0] csr_write_protection_mode;
wire valid_csr_erase;
wire valid_command;
wire flash_drdin_w;
wire flash_arclk_arshft_en_w;
wire flash_se_w;
wire is_busy;
wire write_wait_w;
wire read_wait_w;
wire flash_busy_sync;
wire flash_busy_clear_sync;
generate // generate combi based on read and write mode
if (READ_AND_WRITE_MODE == 1) begin
assign is_erase_busy = (erase_state != ERASE_STATE_IDLE);
assign is_write_busy = (write_state != WRITE_STATE_IDLE);
assign is_read_busy = (read_state != READ_STATE_IDLE);
assign is_busy = is_erase_busy || is_write_busy || is_read_busy;
assign flash_drdin = flash_drdin_neg_reg;
assign write_wait_w = (write_wait || write_wait_neg);
assign is_erase_addr_writable =
(valid_csr_erase && valid_csr_sector_erase_addr) ? is_sector_writable : is_addr_writable;
assign csr_write_protection_mode = csr_control[27:23];
assign is_valid_write_burst_count = (avmm_burstcount == 1);
always @ (negedge clock) begin
if (~reset_n_w) begin
flash_addr_wire_neg_reg <= 0;
end
else if (valid_csr_erase && valid_csr_sector_erase_addr) begin
flash_addr_wire_neg_reg <= { flash_sector_addr, 1'b0, {(19){1'b1}}};
end
else begin
flash_addr_wire_neg_reg <= flash_page_addr;
end
end
end
else begin
assign is_erase_busy = 1'b0;
assign is_write_busy = 1'b0;
assign is_read_busy = (read_state != READ_STATE_IDLE);
assign is_busy = is_read_busy;
assign flash_drdin = 1'b1;
assign write_wait_w = 1'b0;
always @ (negedge clock) begin
if (~reset_n_w) begin
flash_addr_wire_neg_reg <= 0;
end
else begin
flash_addr_wire_neg_reg <= flash_page_addr;
end
end
end
endgenerate
assign csr_status = { SECTOR_READ_PROTECTION_MODE[4:0], csr_status_e_pass, csr_status_w_pass, csr_status_r_pass, csr_status_busy};
assign csr_page_erase_addr = csr_control[19:0];
assign csr_sector_erase_addr = csr_control[22:20];
assign csr_erase_state = csr_control[31:30];
assign valid_csr_sector_erase_addr = (csr_sector_erase_addr != {(3){1'b1}});
assign valid_csr_erase = (csr_erase_state == ERASE_ST_PENDING);
assign valid_command = (valid_csr_erase == 1) || (avmm_write == 1);
assign cur_read_addr = avmm_addr;
assign read_wait_w = (read_wait || read_wait_neg);
generate // generate combi based on read burst mode
if (WRAPPING_BURST_MODE == 0) begin
// incrementing read
assign flash_read_addr = (is_read_busy) ? flash_seq_read_ardin : avmm_addr;
assign cur_e_addr = csr_sector_erase_addr;
assign cur_a_addr = (valid_csr_erase) ? csr_page_erase_addr : flash_read_addr;
assign flash_arclk_arshft_en_w = (~is_erase_busy && ~is_write_busy && ~is_read_busy && valid_command) || (is_read_busy && (read_state == READ_STATE_FINAL || read_state == READ_STATE_ADDR));
assign flash_se_w = (read_state == READ_STATE_SETUP);
assign avmm_waitrequest = ~reset_n || ((~is_write_busy && avmm_write) || write_wait_w || (~is_read_busy && avmm_read) || (avmm_read && read_wait_w));
assign next_flash_read_ardin = {flash_seq_read_ardin[FLASH_ADDR_WIDTH-1:FLASH_ADDR_ALIGNMENT_BITS], {(FLASH_ADDR_ALIGNMENT_BITS){1'b0}}} + FLASH_SEQ_READ_DATA_COUNT[22:0];
end
else begin
// wrapping read
assign cur_e_addr = csr_sector_erase_addr;
assign cur_a_addr = (valid_csr_erase) ? csr_page_erase_addr : avmm_addr;
assign flash_arclk_arshft_en_w = (~is_erase_busy && ~is_write_busy && ~is_read_busy && valid_command) || (read_wait && read_ctrl_count <= 1 && avmm_read);
assign flash_se_w = (read_state == READ_STATE_READ && read_ctrl_count==FLASH_READ_CYCLE_MAX_INDEX+1);
assign avmm_waitrequest = ~reset_n || ((~is_write_busy && avmm_write) || write_wait_w || (~is_read_busy && avmm_read) || (avmm_read && read_wait_w));
end
endgenerate
assign flash_arshft = 1'b1;
assign flash_drshft = flash_drshft_neg_reg;
assign flash_arclk = (~enable_arclk_neg_reg || clock || enable_arclk_neg_pos_reg);
assign flash_drclk = (~enable_drclk_neg_reg || clock || enable_drclk_neg_pos_reg || enable_drclk_neg_pos_write_reg);
assign flash_nerase = ~(erase_state == ERASE_STATE_WAIT_BUSY || erase_state == ERASE_STATE_WAIT_DONE);
assign flash_nprogram = ~(write_state == WRITE_STATE_WAIT_BUSY || write_state == WRITE_STATE_WAIT_DONE);
assign flash_xe_ye = ((~is_busy && avmm_read) || is_read_busy);
assign flash_se = flash_se_neg_reg;
assign flash_ardin = flash_addr_wire_neg_reg;
assign avmm_readdatavalid = avmm_readdatavalid_reg;
always @(posedge clock) begin
if (~reset_n_w | ~csr_status_r_pass) begin
avmm_readdata <= 32'hffffffff;
end
else begin
avmm_readdata <= flash_drdout;
end
end
// avoid async reset removal issue
assign reset_n_w = reset_n_reg2;
// initial register
initial begin
csr_status_busy = STATUS_IDLE;
csr_status_e_pass = 0;
csr_status_w_pass = 0;
csr_status_r_pass = 0;
avmm_burstcount_input_reg = {(AVMM_DATA_BURSTCOUNT_WIDTH){1'b0}};
avmm_burstcount_reg = {(AVMM_DATA_BURSTCOUNT_WIDTH){1'b0}};
erase_state = ERASE_STATE_IDLE;
write_state = WRITE_STATE_IDLE;
read_state = READ_STATE_IDLE;
avmm_read_state = READ_SETUP;
avmm_read_valid_state = READ_VALID_IDLE;
avmm_readdatavalid_reg = 0;
avmm_readdata_ready = 0;
flash_sector_addr = 0;
flash_page_addr = 0;
flash_ardin_align_reg = {(FLASH_ADDR_ALIGNMENT_BITS){1'b0}};
flash_ardin_align_backup_reg = {(FLASH_ADDR_ALIGNMENT_BITS){1'b0}};
write_drclk_en = 0;
read_drclk_en = 0;
flash_drshft_reg = 1;
flash_drshft_neg_reg = 1;
flash_busy_reg = 0;
flash_busy_clear_reg = 0;
flash_se_neg_reg = 0;
flash_se_pass_reg = 0;
flash_sp_pass_reg = 0;
erase_busy_scan = 0;
write_busy_scan = 0;
flash_seq_read_ardin = 0;
enable_arclk_neg_reg = 0;
enable_arclk_neg_pos_reg = 0;
enable_drclk_neg_reg = 0;
enable_drclk_neg_pos_reg = 0;
enable_drclk_neg_pos_write_reg = 0;
flash_drdin_neg_reg = 0;
write_count = 0;
erase_count = 0;
read_ctrl_count = 0;
data_count = 0;
write_timeout = 0;
erase_timeout = 0;
write_wait = 0;
write_wait_neg = 0;
reset_n_reg1 = 0;
reset_n_reg2 = 0;
read_wait = 0;
read_wait_neg = 0;
read_count = 0;
is_sector1_writable_reg = 0;
is_sector2_writable_reg = 0;
is_sector3_writable_reg = 0;
is_sector4_writable_reg = 0;
is_sector5_writable_reg = 0;
end
// -------------------------------------------------------------------
// Avoid async reset removal issue
// -------------------------------------------------------------------
always @ (negedge reset_n or posedge clock) begin
if (~reset_n) begin
{reset_n_reg2, reset_n_reg1} <= 2'b0;
end
else begin
{reset_n_reg2, reset_n_reg1} <= {reset_n_reg1, 1'b1};
end
end
// -------------------------------------------------------------------
// Sync combinational output before feeding into flash
// -------------------------------------------------------------------
always @ (posedge clock) begin
if (~reset_n_w) begin
enable_arclk_sync_reg <= 0;
end
else begin
enable_arclk_sync_reg <= flash_arclk_arshft_en_w;
end
end
// -------------------------------------------------------------------
// Get rid of the race condition between different dynamic clock. Trigger clock enable in early half cycle.
// -------------------------------------------------------------------
always @ (negedge clock) begin
if (~reset_n_w) begin
enable_arclk_neg_reg <= 0;
enable_drclk_neg_reg <= 0;
flash_drshft_neg_reg <= 1;
flash_se_neg_reg <= 0;
write_wait_neg <= 0;
read_wait_neg <= 0;
end
else begin
enable_arclk_neg_reg <= enable_arclk_sync_reg;
enable_drclk_neg_reg <= (write_drclk_en || read_drclk_en);
flash_drshft_neg_reg <= flash_drshft_reg;
flash_se_neg_reg <= flash_se_w;
write_wait_neg <= write_wait;
read_wait_neg <= read_wait;
end
end
// -------------------------------------------------------------------
// Get rid of glitch for pos clock
// -------------------------------------------------------------------
always @ (posedge clock) begin
if (~reset_n_w) begin
enable_arclk_neg_pos_reg <= 0;
end
else begin
enable_arclk_neg_pos_reg <= enable_arclk_neg_reg;
end
end
// -------------------------------------------------------------------
// Pine line page address path
// -------------------------------------------------------------------
always @ (posedge clock) begin
if (~reset_n_w) begin
flash_page_addr <= 0;
end
else begin
flash_page_addr <= flash_page_addr_wire;
end
end
generate // generate always block based on read and write mode. Write and erase operation is unnecessary in read only mode.
if (READ_AND_WRITE_MODE == 1) begin
// -------------------------------------------------------------------
// Pine line sector address path
// -------------------------------------------------------------------
always @ (posedge clock) begin
if (~reset_n_w) begin
flash_sector_addr <= 0;
end
else begin
flash_sector_addr <= flash_sector_wire;
end
end
// -------------------------------------------------------------------
// Minitor flash pass signal and update CSR busy status
// -------------------------------------------------------------------
always @ (posedge clock) begin
if (~reset_n_w) begin
flash_se_pass_reg <= 0;
flash_sp_pass_reg <= 0;
csr_status_busy <= STATUS_IDLE;
end
else begin
flash_se_pass_reg <= flash_se_pass;
flash_sp_pass_reg <= flash_sp_pass;
if (is_erase_busy) begin
csr_status_busy <= STATUS_BUSY_ERASE;
end
else if (is_write_busy) begin
csr_status_busy <= STATUS_BUSY_WRITE;
end
else if (is_read_busy) begin
csr_status_busy <= STATUS_BUSY_READ;
end
else begin
csr_status_busy <= STATUS_IDLE;
end
end
end
// -------------------------------------------------------------------
// Monitor and store flash busy signal, it may faster then the clock
// -------------------------------------------------------------------
wire busy_scan;
assign busy_scan = (erase_busy_scan || write_busy_scan);
always @ (negedge reset_n or negedge busy_scan or posedge flash_osc) begin
if (~reset_n || ~busy_scan) begin
flash_busy_reg <= 0;
flash_busy_clear_reg <= 0;
end
else if (flash_busy_reg) begin
flash_busy_reg <= flash_busy_reg;
flash_busy_clear_reg <= ~flash_busy;
end
else begin
flash_busy_reg <= flash_busy;
flash_busy_clear_reg <= 0;
end
end
altera_std_synchronizer #(
.depth (2)
) stdsync_busy (
.clk(clock), // clock
.din(flash_busy_reg), // busy signal
.dout(flash_busy_sync), // busy signal which reg to clock
.reset_n(reset_n) // active low reset
);
altera_std_synchronizer #(
.depth (2)
) stdsync_busy_clear (
.clk(clock), // clock
.din(flash_busy_clear_reg), // busy signal
.dout(flash_busy_clear_sync), // busy signal which reg to clock
.reset_n(reset_n) // active low reset
);
// -------------------------------------------------------------------
// Get rid of the race condition of shftreg signal (drdin), add half cycle delay to the data
// -------------------------------------------------------------------
always @ (negedge clock) begin
if (~reset_n_w) begin
flash_drdin_neg_reg <= 1;
end
else begin
flash_drdin_neg_reg <= flash_drdin_w;
end
end
// -------------------------------------------------------------------
// Avalon_MM data interface fsm - communicate between Avalon_MM and Flash IP (Write Operation)
// -------------------------------------------------------------------
always @ (posedge clock) begin
if (~reset_n_w) begin
write_state <= WRITE_STATE_IDLE;
write_wait <= 0;
end
else begin
case (write_state)
WRITE_STATE_IDLE: begin
// reset all register
write_count <= 0;
write_timeout <= 1'b0;
write_busy_scan <= 1'b0;
enable_drclk_neg_pos_write_reg <= 0;
// check command
if (avmm_write) begin
if (~valid_csr_erase && ~is_erase_busy && ~is_read_busy) begin
write_state <= WRITE_STATE_ADDR;
write_wait <= 1;
end
end
end
WRITE_STATE_ADDR: begin
if (is_addr_writable && is_valid_write_burst_count) begin
write_count <= DATA_WIDTH[5:0];
write_state <= WRITE_STATE_WRITE;
end
else begin
write_wait <= 0;
write_count <= 2;
write_state <= WRITE_STATE_ERROR;
end
end
WRITE_STATE_WRITE: begin
if (write_count != 0) begin
write_drclk_en <= 1;
write_count <= write_count - 16'd1;
end
else begin
enable_drclk_neg_pos_write_reg <= 1;
write_drclk_en <= 0;
write_busy_scan <= 1'b1;
write_count <= FLASH_BUSY_TIMEOUT_CYCLE_MAX_INDEX[15:0];
write_state <= WRITE_STATE_WAIT_BUSY;
end
end
WRITE_STATE_WAIT_BUSY: begin
if (flash_busy_sync) begin
write_count <= FLASH_WRITE_TIMEOUT_CYCLE_MAX_INDEX[15:0];
write_state <= WRITE_STATE_WAIT_DONE;
end
else begin
if (write_count != 0)
write_count <= write_count - 16'd1;
else begin
write_timeout <= 1'b1;
write_count <= FLASH_RESET_CYCLE_MAX_INDEX[15:0];
write_state <= WRITE_STATE_RESET;
end
end
end
WRITE_STATE_WAIT_DONE: begin
if (flash_busy_clear_sync) begin
write_count <= FLASH_RESET_CYCLE_MAX_INDEX[15:0];
write_state <= WRITE_STATE_RESET;
end
else begin
if (write_count != 0) begin
write_count <= write_count - 16'd1;
end
else begin
write_timeout <= 1'b1;
write_count <= FLASH_RESET_CYCLE_MAX_INDEX[15:0];
write_state <= WRITE_STATE_RESET;
end
end
end
WRITE_STATE_RESET: begin
write_busy_scan <= 1'b0;
if (write_timeout) begin
csr_status_w_pass <= 1'b0;
end
else begin
csr_status_w_pass <= flash_sp_pass_reg;
end
if (write_count == 1) begin
write_wait <= 0;
end
if (write_count != 0) begin
write_count <= write_count - 16'd1;
end
else begin
write_state <= WRITE_STATE_IDLE;
end
end
WRITE_STATE_ERROR: begin
csr_status_w_pass <= 1'b0;
if (write_count == 1) begin
write_wait <= 0;
end
if (write_count != 0) begin
write_count <= write_count - 16'd1;
end
else begin
write_state <= WRITE_STATE_IDLE;
end
end
default: begin
write_state <= WRITE_STATE_IDLE;
end
endcase
end
end
// -------------------------------------------------------------------
// Avalon_MM data interface fsm - communicate between Avalon_MM and Flash IP (Erase Operation)
// -------------------------------------------------------------------
always @ (posedge clock) begin
if (~reset_n_w) begin
erase_state <= ERASE_STATE_IDLE;
end
else begin
case (erase_state)
ERASE_STATE_IDLE: begin
// reset all register
erase_count <= 0;
erase_timeout <= 1'b0;
erase_busy_scan <= 1'b0;
// check command
if (valid_csr_erase && ~is_write_busy && ~is_read_busy) begin
erase_state <= ERASE_STATE_ADDR;
end
end
ERASE_STATE_ADDR: begin
if (is_erase_addr_writable) begin
erase_busy_scan <= 1'b1;
erase_count <= FLASH_BUSY_TIMEOUT_CYCLE_MAX_INDEX[25:0];
erase_state <= ERASE_STATE_WAIT_BUSY;
end
else begin
erase_count <= 2;
erase_state <= ERASE_STATE_ERROR;
end
end
ERASE_STATE_WAIT_BUSY: begin
if (flash_busy_sync) begin
erase_count <= FLASH_ERASE_TIMEOUT_CYCLE_MAX_INDEX[25:0];
erase_state <= ERASE_STATE_WAIT_DONE;
end
else begin
if (erase_count != 0)
erase_count <= erase_count - 26'd1;
else begin
erase_timeout <= 1'b1;
erase_count <= FLASH_RESET_CYCLE_MAX_INDEX[25:0];
erase_state <= ERASE_STATE_RESET;
end
end
end
ERASE_STATE_WAIT_DONE: begin
if (flash_busy_clear_sync) begin
erase_count <= FLASH_RESET_CYCLE_MAX_INDEX[25:0];
erase_state <= ERASE_STATE_RESET;
end
else begin
if (erase_count != 0) begin
erase_count <= erase_count - 26'd1;
end
else begin
erase_timeout <= 1'b1;
erase_count <= FLASH_RESET_CYCLE_MAX_INDEX[25:0];
erase_state <= ERASE_STATE_RESET;
end
end
end
ERASE_STATE_RESET: begin
erase_busy_scan <= 1'b0;
if (erase_timeout) begin
csr_status_e_pass <= 1'b0;
end
else begin
csr_status_e_pass <= flash_se_pass_reg;
end
if (erase_count != 0) begin
erase_count <= erase_count - 26'd1;
end
else begin
erase_state <= ERASE_STATE_IDLE;
end
end
ERASE_STATE_ERROR: begin
csr_status_e_pass <= 1'b0;
if (erase_count != 0) begin
erase_count <= erase_count - 26'd1;
end
else begin
erase_state <= ERASE_STATE_IDLE;
end
end
default: begin
erase_state <= ERASE_STATE_IDLE;
end
endcase
end
end
end
endgenerate
generate // generate always block for read operation based on read burst mode.
if (WRAPPING_BURST_MODE == 0) begin
// -------------------------------------------------------------------
// Avalon_MM data interface fsm - communicate between Avalon_MM and Flash IP (Increamenting Burst Read Operation)
// -------------------------------------------------------------------
always @ (posedge clock) begin
if (~reset_n_w) begin
read_state <= READ_STATE_IDLE;
read_wait <= 0;
end
else begin
case (read_state)
READ_STATE_IDLE: begin
// reset all register
avmm_read_state <= READ_SETUP;
avmm_readdata_ready <= 0;
flash_ardin_align_reg <= 0;
read_ctrl_count <= 0;
avmm_burstcount_input_reg <= 0;
enable_drclk_neg_pos_reg <= 0;
read_drclk_en <= 0;
flash_drshft_reg <= 1;
// check command
if (avmm_read) begin
if (~valid_csr_erase && ~is_erase_busy && ~is_write_busy) begin
read_wait <= 1;
read_state <= READ_STATE_ADDR;
flash_seq_read_ardin <= avmm_addr;
avmm_burstcount_input_reg <= avmm_burstcount;
end
end
end
READ_STATE_ADDR: begin
if (is_addr_within_valid_range) begin
csr_status_r_pass <= 1;
end
else begin
csr_status_r_pass <= 0;
end
read_wait <= 0;
read_state <= READ_STATE_PULSE_SE;
end
READ_STATE_PULSE_SE: begin
read_wait <= 1;
read_state <= READ_STATE_SETUP;
end
// incrementing read
READ_STATE_SETUP: begin
if (next_flash_read_ardin > MAX_VALID_ADDR) begin
flash_seq_read_ardin <= MIN_VALID_ADDR[FLASH_ADDR_WIDTH-1:0];
end
else begin
flash_seq_read_ardin <= next_flash_read_ardin;
end
flash_ardin_align_reg <= flash_seq_read_ardin[FLASH_ADDR_ALIGNMENT_BITS-1:0];
if (FLASH_READ_CYCLE_MAX_INDEX[2:0] > 2) begin
read_ctrl_count <= FLASH_READ_CYCLE_MAX_INDEX[2:0] - 3'd2;
read_state <= READ_STATE_DUMMY;
end
else begin
read_state <= READ_STATE_READY;
end
end
READ_STATE_DUMMY: begin
if (read_ctrl_count > 1) begin
read_ctrl_count <= read_ctrl_count - 3'd1;
end
else begin
read_state <= READ_STATE_READY;
end
end
READ_STATE_READY: begin
if (avmm_read_state == READ_SETUP) begin
avmm_readdata_ready <= 1;
end
read_drclk_en <= 1;
flash_drshft_reg <= 0;
read_state <= READ_STATE_FINAL;
end
READ_STATE_FINAL: begin
flash_drshft_reg <= 1;
avmm_readdata_ready <= 0;
avmm_read_state <= READ_RECV_DATA;
if ((avmm_read_state == READ_RECV_DATA) && (avmm_burstcount_reg == 0)) begin
read_state <= READ_STATE_CLEAR;
read_drclk_en <= 0;
enable_drclk_neg_pos_reg <= 1;
end
else begin
read_state <= READ_STATE_PULSE_SE;
end
end
// Dummy state to clear arclk glitch
READ_STATE_CLEAR: begin
read_wait <= 0;
read_state <= READ_STATE_IDLE;
end
default: begin
read_state <= READ_STATE_IDLE;
end
endcase
end
end
end
else begin
// -------------------------------------------------------------------
// Avalon_MM data interface fsm - communicate between Avalon_MM and Flash IP (Wrapping Burst Read Operation)
// -------------------------------------------------------------------
always @ (posedge clock) begin
if (~reset_n_w) begin
read_state <= READ_STATE_IDLE;
read_wait <= 0;
end
else begin
case (read_state)
READ_STATE_IDLE: begin
// reset all register
avmm_readdata_ready <= 0;
flash_ardin_align_reg <= 0;
read_ctrl_count <= 0;
enable_drclk_neg_pos_reg <= 0;
flash_drshft_reg <= 1;
read_drclk_en <= 0;
avmm_burstcount_input_reg <= 0;
// check command
if (avmm_read) begin
if (~valid_csr_erase && ~is_erase_busy && ~is_write_busy) begin
read_wait <= 1;
read_state <= READ_STATE_ADDR;
avmm_burstcount_input_reg <= avmm_burstcount;
end
end
end
READ_STATE_ADDR: begin
read_wait <= 0;
if (is_addr_within_valid_range) begin
csr_status_r_pass <= 1;
end
else begin
csr_status_r_pass <= 0;
end
read_state <= READ_STATE_PULSE_SE;
read_ctrl_count <= FLASH_READ_CYCLE_MAX_INDEX[2:0] + 3'd1;
end
READ_STATE_PULSE_SE: begin
read_wait <= 1;
read_state <= READ_STATE_READ;
end
// wrapping read
READ_STATE_READ: begin
// read control signal
if (read_ctrl_count > 0) begin
read_ctrl_count <= read_ctrl_count - 3'd1;
end
if (read_ctrl_count == 2) begin
avmm_readdata_ready <= 1;
read_drclk_en <= 1;
flash_drshft_reg <= 0;
end
else begin
flash_drshft_reg <= 1;
end
if (avmm_read && ~read_wait) begin
read_wait <= 1;
end
if (avmm_readdata_ready || read_ctrl_count == 0) begin
avmm_readdata_ready <= 0;
if (avmm_read) begin
avmm_burstcount_input_reg <= avmm_burstcount;
read_state <= READ_STATE_ADDR;
end
end
// read data signal
if (read_count > 0) begin
read_count <= read_count - 3'd1;
end
else begin
if (avmm_readdata_ready) begin
read_count <= FLASH_SEQ_READ_DATA_COUNT[2:0] - 3'd1;
end
end
// back to idle if both control and read cycle are finished
if (read_ctrl_count == 0 && read_count == 0 && ~avmm_read) begin
read_state <= READ_STATE_IDLE;
read_drclk_en <= 0;
read_wait <= 0;
enable_drclk_neg_pos_reg <= 1;
end
end
default: begin
read_state <= READ_STATE_IDLE;
end
endcase
end
end
end
endgenerate
generate // generate readdatavalid control signal always block based on read burst mode.
if (WRAPPING_BURST_MODE == 0) begin
// -------------------------------------------------------------------
// Control readdatavalid signal - incrementing read
// -------------------------------------------------------------------
always @ (posedge clock) begin
if (~reset_n_w) begin
avmm_read_valid_state <= READ_VALID_IDLE;
avmm_burstcount_reg <= 0;
avmm_readdatavalid_reg <= 0;
flash_ardin_align_backup_reg <= 0;
data_count <= 0;
end
else begin
case (avmm_read_valid_state)
READ_VALID_IDLE: begin
if (avmm_readdata_ready) begin
data_count <= FLASH_READ_CYCLE_MAX_INDEX[2:0];
avmm_read_valid_state <= READ_VALID_PRE_READING;
avmm_burstcount_reg <= avmm_burstcount_input_reg - {{(AVMM_DATA_BURSTCOUNT_WIDTH-1){1'b0}}, 1'b1};
flash_ardin_align_backup_reg <= flash_ardin_align_reg;
end
end
READ_VALID_PRE_READING: begin
avmm_readdatavalid_reg <= 1;
avmm_read_valid_state <= READ_VALID_READING;
end
READ_VALID_READING: begin
if (avmm_burstcount_reg == 0) begin
avmm_read_valid_state <= READ_VALID_IDLE;
avmm_readdatavalid_reg <= 0;
end
else begin
if (data_count > 0) begin
if ((FLASH_READ_CYCLE_MAX_INDEX - data_count + 1 + flash_ardin_align_backup_reg) < FLASH_SEQ_READ_DATA_COUNT) begin
avmm_readdatavalid_reg <= 1;
avmm_burstcount_reg <= avmm_burstcount_reg - {{(AVMM_DATA_BURSTCOUNT_WIDTH-1){1'b0}}, 1'b1};
end
else begin
avmm_readdatavalid_reg <= 0;
end
data_count <= data_count - 3'd1;
end
else begin
flash_ardin_align_backup_reg <= 0;
data_count <= FLASH_READ_CYCLE_MAX_INDEX[2:0];
avmm_read_valid_state <= READ_VALID_PRE_READING;
avmm_burstcount_reg <= avmm_burstcount_reg - {{(AVMM_DATA_BURSTCOUNT_WIDTH-1){1'b0}}, 1'b1};
end
end
end
default: begin
avmm_read_valid_state <= READ_VALID_IDLE;
avmm_burstcount_reg <= 0;
avmm_readdatavalid_reg <= 0;
flash_ardin_align_backup_reg <= 0;
data_count <= 0;
end
endcase
end
end
end
else begin
// -------------------------------------------------------------------
// Control readdatavalid signal - wrapping read with fixed burst count
// Burst count
// 1~2 - ZB8
// 1~4 - all other devices
// -------------------------------------------------------------------
always @ (posedge clock) begin
if (~reset_n_w) begin
avmm_read_valid_state <= READ_VALID_IDLE;
avmm_readdatavalid_reg <= 0;
end
else begin
case (avmm_read_valid_state)
READ_VALID_IDLE: begin
data_count <= 0;
if (avmm_readdata_ready) begin
data_count <= avmm_burstcount_input_reg - 3'd1;
avmm_read_valid_state <= READ_VALID_PRE_READING;
end
end
READ_VALID_PRE_READING: begin
avmm_readdatavalid_reg <= 1;
avmm_read_valid_state <= READ_VALID_READING;
end
READ_VALID_READING: begin
if (data_count > 0) begin
data_count <= data_count - 3'd1;
end
else begin
if (avmm_readdata_ready) begin
data_count <= avmm_burstcount_input_reg - 3'd1;
end
else begin
avmm_read_valid_state <= READ_VALID_IDLE;
avmm_readdatavalid_reg <= 0;
end
end
end
default: begin
avmm_read_valid_state <= READ_VALID_IDLE;
end
endcase
end
end
end
endgenerate
generate // generate shiftreg based on read and write mode. Unnecessary in read only mode.
if (READ_AND_WRITE_MODE == 1) begin
// -------------------------------------------------------------------
// Instantiate a shift register to send the data to UFM serially (load parallel)
// -------------------------------------------------------------------
lpm_shiftreg # (
.lpm_type ("LPM_SHIFTREG"),
.lpm_width (DATA_WIDTH),
.lpm_direction ("LEFT")
) ufm_data_shiftreg (
.data(avmm_writedata),
.clock(clock),
.enable(write_state == WRITE_STATE_WRITE),
.load(write_count == DATA_WIDTH),
.shiftout(flash_drdin_w),
.aclr(write_state == WRITE_STATE_IDLE)
);
end
endgenerate
altera_onchip_flash_address_range_check # (
.MIN_VALID_ADDR(MIN_VALID_ADDR),
.MAX_VALID_ADDR(MAX_VALID_ADDR)
) address_range_checker (
.address(cur_read_addr),
.is_addr_within_valid_range(is_addr_within_valid_range)
);
altera_onchip_flash_convert_address # (
.ADDR_RANGE1_END_ADDR(ADDR_RANGE1_END_ADDR),
.ADDR_RANGE2_END_ADDR(ADDR_RANGE2_END_ADDR),
.ADDR_RANGE1_OFFSET(ADDR_RANGE1_OFFSET),
.ADDR_RANGE2_OFFSET(ADDR_RANGE2_OFFSET),
.ADDR_RANGE3_OFFSET(ADDR_RANGE3_OFFSET)
) address_convertor (
.address(cur_a_addr),
.flash_addr(flash_page_addr_wire)
);
generate // sector address convertsion is unnecessary in read only mode
if (READ_AND_WRITE_MODE == 1) begin
// pipe line addr legality check logic
always @ (posedge clock) begin
if (~reset_n_w) begin
is_sector1_writable_reg <= 1'b0;
is_sector2_writable_reg <= 1'b0;
is_sector3_writable_reg <= 1'b0;
is_sector4_writable_reg <= 1'b0;
is_sector5_writable_reg <= 1'b0;
end
else begin
is_sector1_writable_reg <= ~(csr_write_protection_mode[0] || SECTOR_READ_PROTECTION_MODE[0]);
is_sector2_writable_reg <= ~(csr_write_protection_mode[1] || SECTOR_READ_PROTECTION_MODE[1]);
is_sector3_writable_reg <= ~(csr_write_protection_mode[2] || SECTOR_READ_PROTECTION_MODE[2]);
is_sector4_writable_reg <= ~(csr_write_protection_mode[3] || SECTOR_READ_PROTECTION_MODE[3]);
is_sector5_writable_reg <= ~(csr_write_protection_mode[4] || SECTOR_READ_PROTECTION_MODE[4]);
end
end
altera_onchip_flash_a_address_write_protection_check # (
.SECTOR1_START_ADDR(SECTOR1_START_ADDR),
.SECTOR1_END_ADDR(SECTOR1_END_ADDR),
.SECTOR2_START_ADDR(SECTOR2_START_ADDR),
.SECTOR2_END_ADDR(SECTOR2_END_ADDR),
.SECTOR3_START_ADDR(SECTOR3_START_ADDR),
.SECTOR3_END_ADDR(SECTOR3_END_ADDR),
.SECTOR4_START_ADDR(SECTOR4_START_ADDR),
.SECTOR4_END_ADDR(SECTOR4_END_ADDR),
.SECTOR5_START_ADDR(SECTOR5_START_ADDR),
.SECTOR5_END_ADDR(SECTOR5_END_ADDR)
) access_address_write_protection_checker (
.address(cur_a_addr),
.is_sector1_writable(is_sector1_writable_reg),
.is_sector2_writable(is_sector2_writable_reg),
.is_sector3_writable(is_sector3_writable_reg),
.is_sector4_writable(is_sector4_writable_reg),
.is_sector5_writable(is_sector5_writable_reg),
.is_addr_writable(is_addr_writable)
);
altera_onchip_flash_s_address_write_protection_check sector_address_write_protection_checker (
.address(cur_e_addr[2:0]),
.is_sector1_writable(is_sector1_writable_reg),
.is_sector2_writable(is_sector2_writable_reg),
.is_sector3_writable(is_sector3_writable_reg),
.is_sector4_writable(is_sector4_writable_reg),
.is_sector5_writable(is_sector5_writable_reg),
.is_addr_writable(is_sector_writable)
);
altera_onchip_flash_convert_sector # (
.SECTOR1_MAP(SECTOR1_MAP),
.SECTOR2_MAP(SECTOR2_MAP),
.SECTOR3_MAP(SECTOR3_MAP),
.SECTOR4_MAP(SECTOR4_MAP),
.SECTOR5_MAP(SECTOR5_MAP)
) sector_convertor (
.sector(cur_e_addr[2:0]),
.flash_sector(flash_sector_wire)
);
end
endgenerate
endmodule
|
module bsg_comm_link
#(parameter `BSG_INV_PARAM(channel_width_p )
, parameter `BSG_INV_PARAM(core_channels_p )
, parameter `BSG_INV_PARAM(link_channels_p )
, parameter `BSG_INV_PARAM(nodes_p ) // how many nodes on the FSB
, parameter `BSG_INV_PARAM(master_p ) // 1=FPGA,0=ASIC
// e.g if you have four channels, and you wanted any
// subset of them to be supported, you would
// provide 1111. if you only want all four channels
// to be supported, then you provide 1000.
//
// any combination of channels
, parameter channel_mask_p=(1 << (link_channels_p))-1
// NB: master_ parameters only apply to the master
// this is the maximum ratio between master io frequency
// and the min of: slave io frequency
// slave core frequency
// master core frequency
//
// that we want to support.
// Used only by master.
, parameter master_to_slave_speedup_p = 100
// have this node enabled at startup (typ. 0 for ASIC; 1 for FPGA)
, parameter enabled_at_start_vec_p = (nodes_p) ' (0)
// * PARAMETERS
// * below here mostly can be left alone
// *
// *
// *
// enable this if comm_link appears on the critical path
// adds one core cycle of latency in or out
// and two channel_width_p*link_channels fifos.
, parameter sbox_pipeline_in_p = 1'b1
, parameter sbox_pipeline_out_p = 1'b1
// made this node see all packets (typ. 0 for ASIC and FPGA)
, parameter snoop_vec_p = (nodes_p) ' (0)
// in testing, use this to disable tests
, parameter master_bypass_test_p = 5'b00000
// for DDR at 500 mbps, we make token go at / 8 = 66 mbps
// this will keep the token clock nice and slow
// careful: values other than 3 have not been tested.
, parameter lg_credit_to_token_decimation_p = 3
// lg of how many cycles to wait to assert token reset
// also how many cycles to assert it for
// keep these at 5; bigger is not necessarilybetter.
// bigger is not necessarily better for token_width
// keep these at 5, unless token_decimation
// increases.
, parameter master_lg_token_width_p = lg_credit_to_token_decimation_p+2
, parameter slave_lg_token_width_p = lg_credit_to_token_decimation_p+2
// time after reset to start calibration process
, parameter master_lg_wait_after_reset_p = $clog2(1+master_to_slave_speedup_p*128)
// time to assert reset before calibration code
, parameter master_calib_prepare_cycles_p
= master_to_slave_speedup_p
* 2 * (2**(master_lg_token_width_p+1)+2**(slave_lg_token_width_p+1))
// time to hold calibration code after reset
// see derivation in master_master
, parameter master_lg_out_prepare_hold_cycles_p
= $clog2(5*master_to_slave_speedup_p+10)
// fixme: derive value better (we reduced this to 25 from 5000 for simulation)
// 25 might actually be okay
, parameter master_calib_timeout_cycles_p = master_to_slave_speedup_p * 25
)
(input core_clk_i
, input async_reset_i
, input io_master_clk_i
// into nodes (control)
, output [nodes_p-1:0] core_node_reset_r_o
, output [nodes_p-1:0] core_node_en_r_o
// into nodes (fsb interface)
, output [nodes_p-1:0] core_node_v_o
, output [core_channels_p*channel_width_p-1:0] core_node_data_o [nodes_p-1:0]
, input [nodes_p-1:0] core_node_ready_i
// out of nodes (fsb interface)
, input [nodes_p-1:0] core_node_v_i
, input [core_channels_p*channel_width_p-1:0] core_node_data_i [nodes_p-1:0]
, output [nodes_p-1:0] core_node_yumi_o
// use this as a reset signal if you want to wakeup
// after the comm link has woken up.
, output core_calib_reset_r_o
// in from i/o
, input [link_channels_p-1:0] io_valid_tline_i
, input [channel_width_p-1:0] io_data_tline_i [link_channels_p-1:0]
, input [link_channels_p-1:0] io_clk_tline_i // clk
, output [link_channels_p-1:0] io_token_clk_tline_o // clk
// out to i/o
, output [link_channels_p-1:0] im_valid_tline_o
, output [channel_width_p-1:0] im_data_tline_o [link_channels_p-1:0]
, output [link_channels_p-1:0] im_clk_tline_o // clk
// note: generate by the master (FPGA) and sent to the slave (ASIC)
// not used by slave (ASIC).
, output reg im_slave_reset_tline_r_o
, input [link_channels_p-1:0] token_clk_tline_i // clk
// note: this is almost never the right reset to use
// as it occurs before the channels come up
// safest thing is to not connect it
, output core_async_reset_danger_o
);
// if we have more than 2X the number of core channels than link channels
// we should use a channel narrow gadget to simplify the circuit
// higher multiples are possible but TBD.
localparam bao_narrow_lp = (
((core_channels_p / 2) >= link_channels_p)
& (core_channels_p % 2) == 0
) ? 2 : 1;
// across all frequency combinations, we need a little over 20 fifo slots
// so we round up to 32, to allow for delay in the FPGA
localparam lg_input_fifo_depth_lp = 5;
// synchronized resets for incoming i/o channels
wire [link_channels_p-1:0] io_reset;
wire [link_channels_p-1:0] io_calib_done;
wire im_reset;
wire [link_channels_p-1:0] im_clk_init;
wire im_slave_reset_tline_n;
wire core_reset_i;
assign core_async_reset_danger_o = core_reset_i;
// synchronize core and im resets
bsg_sync_sync #(.width_p(1)) core_reset_ss
(.oclk_i(core_clk_i)
, .iclk_data_i(async_reset_i)
, .oclk_data_o(core_reset_i)
);
bsg_sync_sync #(.width_p(1)) im_reset_ss
(.oclk_i(io_master_clk_i)
, .iclk_data_i(async_reset_i)
, .oclk_data_o(im_reset)
);
// register true output signals
always @(posedge io_master_clk_i)
im_slave_reset_tline_r_o <= im_slave_reset_tline_n;
wire [link_channels_p-1:0] core_asm_to_sso_valid;
wire [channel_width_p-1:0] core_asm_to_sso_data [link_channels_p-1:0];
wire [link_channels_p-1:0] core_asm_to_sso_ready;
wire [link_channels_p-1:0] core_ssi_to_asm_valid;
wire [channel_width_p-1:0] core_ssi_to_asm_data [link_channels_p-1:0];
wire [link_channels_p-1:0] core_ssi_to_asm_yumi;
wire [link_channels_p-1:0] core_asm_to_sso_valid_sbox
, core_ssi_to_asm_valid_sbox;
wire [channel_width_p-1:0] core_asm_to_sso_data_sbox [link_channels_p-1:0];
wire [channel_width_p-1:0] core_ssi_to_asm_data_sbox [link_channels_p-1:0];
wire [link_channels_p-1:0] core_asm_to_sso_ready_sbox
, core_ssi_to_asm_yumi_sbox;
// synchronous to im clock
wire [link_channels_p-1:0] im_override_en;
wire [channel_width_p+1-1:0] im_override_valid_data [link_channels_p-1:0];
wire [link_channels_p-1:0] im_override_is_posedge, im_infinite_credits_en;
// synchronous to io clocks
wire [channel_width_p+1-1:0] io_snoop_valid_data_pos [link_channels_p-1:0];
wire [channel_width_p+1-1:0] io_snoop_valid_data_neg [link_channels_p-1:0];
wire [link_channels_p-1:0] io_trigger_mode_en, io_trigger_mode_alt_en;
wire [link_channels_p-1:0] core_loopback_en;
wire [link_channels_p-1:0] core_channel_active, im_channel_active;
// computed from channel_active signals
logic [`BSG_MAX(0,$clog2(link_channels_p)-1):0] core_top_active_channel_bao_r, core_top_active_channel_bai_r, core_top_active_channel_n;
logic [`BSG_MAX(0,$clog2(link_channels_p+1)-1):0] active_channel_count;
bsg_popcount #(.width_p(link_channels_p)) pop (.i(core_channel_active)
,.o(active_channel_count) );
// how many channels are alive?
assign core_top_active_channel_n = (| core_channel_active) ? (active_channel_count - 1) : '0;
// clone this register to keep it off critical paths
bsg_dff #(.harden_p(1)
,.strength_p(4)
,.width_p(`BSG_MAX(1,$clog2(link_channels_p)))
) core_top_active_channel_bai_r_reg
(.clock_i(core_clk_i)
,.data_i(core_top_active_channel_n)
,.data_o(core_top_active_channel_bai_r)
);
bsg_dff #(.harden_p(1)
,.strength_p(4)
,.width_p(`BSG_MAX(1,$clog2(link_channels_p)))
) core_top_active_channel_bao_r_reg
(.clock_i(core_clk_i)
,.data_i(core_top_active_channel_n)
,.data_o(core_top_active_channel_bao_r)
);
localparam tests_p = 5;
wire im_calib_done, im_calib_done_r;
wire core_calib_done_prefanout_r;
bsg_launch_sync_sync #(.width_p(1)) out_to_core_sync_calib_done
(.iclk_i(io_master_clk_i)
,.iclk_reset_i(1'b0)
,.oclk_i(core_clk_i)
,.iclk_data_i(im_calib_done)
,.iclk_data_o(im_calib_done_r)
// ,.oclk_data_o(core_calib_done_r)
,.oclk_data_o(core_calib_done_prefanout_r)
);
// generate pipelined reset tree
wire [5:0] core_calib_done_vec_r;
assign core_calib_reset_r_o = ~core_calib_done_vec_r[0];
genvar k;
for (k = 0; k < 6; k=k+1)
begin: cr
bsg_dff #(.harden_p(1)
,.strength_p(4)
,.width_p(1)
) core_calib_reset_fanout_reg
(.clock_i(core_clk_i)
,.data_i(core_calib_done_prefanout_r)
,.data_o(core_calib_done_vec_r[k])
);
end
if (master_p)
begin : mstr
// counter intuitive; organized by tests then by channel
wire [tests_p+1-1:0][link_channels_p-1:0] im_test_scoreboard;
wire [$clog2(tests_p+1)-1:0] im_test_index; // + 1; for the "final test"
wire im_prepare;
// assert the tline
assign im_slave_reset_tline_n = im_prepare;
logic im_start_calibration_n, im_start_calibration_r;
// wait a certain number of cycles after global reset to start
// global calibration
bsg_wait_after_reset #(.lg_wait_cycles_p(master_lg_wait_after_reset_p)) bwar
(.clk_i(io_master_clk_i)
,.reset_i (im_reset)
,.ready_r_o(im_start_calibration_n)
);
always_ff @(posedge io_master_clk_i)
im_start_calibration_r <= im_start_calibration_n;
bsg_source_sync_channel_control_master_master
#(.link_channels_p(link_channels_p)
,.tests_p(tests_p)
,.prepare_cycles_p(master_calib_prepare_cycles_p)
,.timeout_cycles_p(master_calib_timeout_cycles_p)
) master_master
(.clk_i(io_master_clk_i)
,.reset_i (im_reset)
,.start_i (~im_start_calibration_r & im_start_calibration_n )
,.test_scoreboard_i(im_test_scoreboard)
,.test_index_r_o (im_test_index )
,.prepare_o (im_prepare )
,.done_o (im_calib_done )
);
always_ff @(negedge io_master_clk_i)
if (im_calib_done & ~im_calib_done_r)
$display("###### Master calibration COMPLETED with active channels: (%b)."
, im_channel_active);
end // block: mstr
else // slave
begin
// the slave is done calibrating if any of the channels are
// active. since activation goes high only when im_reset goes
// low, all channels will all activate at the same time.
//
// no waiting for differences in channel clocks is necessary.
//
assign im_calib_done = (|im_channel_active);
assign im_slave_reset_tline_n = 1'b0;
end
wire im_channel_reset, core_channel_reset;
genvar i,j;
logic im_reset_r;
if (master_p)
begin : rreg
always @(posedge io_master_clk_i)
im_reset_r <= im_reset;
end
// create all of the input and output channels
for (i = 0; i < link_channels_p; i=i+1)
begin: ch
bsg_launch_sync_sync #(.width_p(1)) blss_channel_active
(.iclk_i (io_master_clk_i)
,.iclk_reset_i(im_reset)
,.oclk_i (core_clk_i)
,.iclk_data_i (im_channel_active[i])
,.iclk_data_o()
,.oclk_data_o (core_channel_active[i])
);
if (master_p)
begin :m
wire [tests_p+1-1:0] im_tests_gather;
for (j = 0; j < tests_p+1; j=j+1)
begin : mpa
assign mstr.im_test_scoreboard[j][i] = im_tests_gather[j];
end
bsg_source_sync_channel_control_master
#(.width_p(channel_width_p)
,.lg_token_width_p(master_lg_token_width_p)
,.lg_out_prepare_hold_cycles_p(master_lg_out_prepare_hold_cycles_p)
,.bypass_test_p(master_bypass_test_p)
,.tests_lp(tests_p)
) control_master
(
.out_clk_i (io_master_clk_i)
,.out_reset_i (im_reset)
,.out_calibration_state_i (mstr.im_test_index)
,.out_calib_prepare_i (mstr.im_prepare)
,.out_channel_blessed_i (im_channel_active[i])
,.out_override_en_o (im_override_en [i])
,.out_override_valid_data_o (im_override_valid_data [i])
,.out_override_is_posedge_i (im_override_is_posedge [i])
,.in_clk_i (io_clk_tline_i [i])
// reset synchronized to io_clk_tline_i
,.in_reset_i (io_reset [i])
,.in_snoop_valid_data_neg_i(io_snoop_valid_data_neg [i])
,.in_snoop_valid_data_pos_i(io_snoop_valid_data_pos [i])
// AWC fixme: incorrect name should be output clocked, not in clocked
// i.e. should be:
,.out_infinite_credits_o (im_infinite_credits_en[i])
//,.in_infinite_credits_o (io_infinite_credits_en [i])
,.out_test_pass_r_o ( im_tests_gather )
);
assign im_channel_reset = mstr.im_prepare;
bsg_launch_sync_sync #(.width_p(1)) io_reset_lss
(.iclk_i (io_master_clk_i)
,.iclk_reset_i(1'b0)
,.oclk_i (io_clk_tline_i[i])
,.iclk_data_i (im_channel_reset)
,.iclk_data_o()
,.oclk_data_o (io_reset[i])
);
// generate core_channel reset from im_channel reset
bsg_launch_sync_sync #(.width_p(1)) bssi_reset
(.iclk_i(io_master_clk_i)
,.iclk_reset_i(1'b0)
,.oclk_i(core_clk_i)
,.iclk_data_i(im_channel_reset)
,.iclk_data_o()
,.oclk_data_o(core_channel_reset)
);
assign io_trigger_mode_en [i] = 1'b0;
assign io_trigger_mode_alt_en [i] = 1'b0;
assign core_loopback_en [i] = 1'b0;
`ifndef SYNTHESIS
// activate the channel if all of the "real" tests passed
// MBT: we use triple equals because this handles the X case in simulation
// DC of course does not like ===
assign im_channel_active[i] = (im_tests_gather[tests_p-1:0] === { tests_p {1'b1} });
`else
assign im_channel_active[i] = (im_tests_gather[tests_p-1:0] == { tests_p {1'b1} });
`endif
assign im_clk_init [i] = im_reset & ~im_reset_r;
end
else
begin : s
// no launch flop necessary here
// and we synchronize directly from
// the async reset for speed
bsg_sync_sync #(.width_p(1)) io_reset_ss
(.oclk_i(io_clk_tline_i[i])
, .iclk_data_i(async_reset_i)
, .oclk_data_o(io_reset[i])
);
assign core_channel_reset = core_reset_i;
assign im_channel_reset = im_reset;
bsg_source_sync_channel_control_slave
#(.width_p(channel_width_p)
,.lg_token_width_p(slave_lg_token_width_p)
)
control_slave
(// output channel
.out_clk_i (io_master_clk_i)
,.out_reset_i (im_reset)
,.out_clk_init_r_o (im_clk_init [i])
,.out_override_en_o (im_override_en [i])
,.out_override_valid_data_o (im_override_valid_data [i])
// whether the channel is available for I/O assembler, post reset
,.out_channel_active_o (im_channel_active [i])
// for input channel
,.in_clk_i (io_clk_tline_i [i])
,.in_snoop_valid_data_i (io_snoop_valid_data_pos [i])
,.in_trigger_mode_en_o (io_trigger_mode_en [i])
,.in_trigger_mode_alt_en_o (io_trigger_mode_alt_en [i])
// AWC fixme: incorrect name should be output clocked, not in clocked
// i.e. should be:
,.out_infinite_credits_o (im_infinite_credits_en[i])
//,.in_infinite_credits_o (io_infinite_credits_en [i])
// for core control
,.core_clk_i (core_clk_i )
,.core_loopback_en_o (core_loopback_en [i])
);
end
// The token reset strategy for metastability is different,
// because clocking the token clock increments a counter. Introducing
// a synchronizer for the reset requires for us to control the token reset
// precisely relative to the token clock, which cannot easily be done
// from another clock domain.
//
// Instead, we tie the token reset to the im reset, and avoid
// metastability by requiring the master reset be asserted for many cycles
// before going low.
//
// During that reset period, we toggle the token clock to clear out state.
// The token clock should only be toggled again (in normal use) a safe
// number of cycles after reset goes low.
wire token_reset = im_channel_reset;
bsg_source_sync_output
#(.lg_start_credits_p(lg_input_fifo_depth_lp)
,.lg_credit_to_token_decimation_p(lg_credit_to_token_decimation_p)
,.channel_width_p(channel_width_p)
) sso
(.core_clk_i(core_clk_i)
,.core_reset_i(core_channel_reset)
,.core_data_i (core_loopback_en[i]
? core_ssi_to_asm_data [i]
: core_asm_to_sso_data_sbox [i])
,.core_valid_i(core_loopback_en[i]
? core_ssi_to_asm_valid[i]
: core_asm_to_sso_valid_sbox[i])
// fixme: any special treatment required for loopback?
,.core_ready_o(core_asm_to_sso_ready [i])
,.io_master_clk_i(io_master_clk_i)
,.io_reset_i (im_channel_reset)
,.io_clk_init_i (im_clk_init[i])
,.io_override_en_i (im_override_en[i] )
,.io_override_valid_data_i(im_override_valid_data[i])
,.io_override_is_posedge_o(im_override_is_posedge[i])
,.io_clk_r_o( im_clk_tline_o [i])
,.io_data_r_o( im_data_tline_o [i])
,.io_valid_r_o(im_valid_tline_o [i])
// AWC fixme: incorrect name should be output clocked, not in clocked
// i.e. should be:
,.io_infinite_credits_i (im_infinite_credits_en[i])
//,.io_infinite_credits_i (io_infinite_credits_en[i])
,.token_clk_i (token_clk_tline_i [i])
,.token_reset_i(token_reset )
);
bsg_launch_sync_sync #(.width_p(1)) im_to_io_calib_done
(.iclk_i (io_master_clk_i)
,.iclk_reset_i(1'b0)
,.oclk_i (io_clk_tline_i[i])
,.iclk_data_i (im_calib_done)
,.iclk_data_o()
,.oclk_data_o (io_calib_done[i])
);
bsg_source_sync_input
#(.lg_fifo_depth_p(lg_input_fifo_depth_lp)
,.lg_credit_to_token_decimation_p(lg_credit_to_token_decimation_p)
,.channel_width_p(channel_width_p)
) ssi
// starts on reset lo->hi xition
(.io_clk_i (io_clk_tline_i [i])
,.io_data_i (io_data_tline_i [i])
,.io_valid_i (io_valid_tline_i [i])
,.io_token_r_o(io_token_clk_tline_o [i])
// note a small quirk: for the master, we tie reset of the
// input channel to the calibration being done rather
// than the channel reset. this is because for the most
// part the input channel is not used during calibration.
// for the master, we keep this unit quiet until calibration is done
// for the slave, we need to use this unit, but we reset it for each
// phase of calibration
,.io_reset_i(master_p ? ~io_calib_done[i] : io_reset[i])
// for both master and slave, prepare/reset mode enables token bypass
// i.e.; we reset the token on every Phase.
//
,.io_token_bypass_i(io_reset[i])
,.io_edge_i(2'b11) // latch on both edges; could change on the fly
,.io_snoop_pos_r_o(io_snoop_valid_data_pos[i]) // snoop input channel
// for establishing calib.
// state on reset
,.io_snoop_neg_r_o(io_snoop_valid_data_neg[i])
// enable loop-back trigger mode
,.io_trigger_mode_en_i (io_trigger_mode_en [i])
// enable loop-back trigger mode: alternate trigger
,.io_trigger_mode_alt_en_i(io_trigger_mode_alt_en[i])
,.core_clk_i (core_clk_i)
,.core_reset_i(core_channel_reset)
// core 1 side logical signals
,.core_data_o (core_ssi_to_asm_data [i] )
,.core_valid_o(core_ssi_to_asm_valid [i] )
,.core_yumi_i (core_loopback_en[i]
? (core_asm_to_sso_ready[i] & core_ssi_to_asm_valid[i])
: core_ssi_to_asm_yumi_sbox[i])
);
// only used by master; ignore for slave
// wire ignore = | io_snoop_valid_data_neg[i];
end // block: channel
//***************************************************
//
// SBOX, ASSEMBLER AND FRONT SIDE BUS
//
//
// fixme: the code after this point
// could be factored into another file
//
//***************************************************
bsg_sbox #(.num_channels_p(link_channels_p)
,.channel_width_p(channel_width_p)
,.pipeline_indir_p(sbox_pipeline_in_p)
,.pipeline_outdir_p(sbox_pipeline_out_p)
) sbox
(.clk_i(core_clk_i)
,.reset_i(core_reset_i)
,.calibration_done_i(core_calib_done_vec_r[1])
,.channel_active_i(core_channel_active)
,.in_v_i (core_ssi_to_asm_valid)
,.in_data_i(core_ssi_to_asm_data )
,.in_yumi_o(core_ssi_to_asm_yumi_sbox )
,.in_v_o (core_ssi_to_asm_valid_sbox )
,.in_data_o(core_ssi_to_asm_data_sbox )
,.in_yumi_i(core_ssi_to_asm_yumi )
,.out_me_v_i (core_asm_to_sso_valid )
,.out_me_data_i (core_asm_to_sso_data )
,.out_me_ready_o(core_asm_to_sso_ready_sbox )
,.out_me_v_o (core_asm_to_sso_valid_sbox )
,.out_me_data_o (core_asm_to_sso_data_sbox )
,.out_me_ready_i(core_asm_to_sso_ready )
);
// outgoing from fsb to nrw
wire core_nrw_valid_li;
wire [core_channels_p*channel_width_p-1:0] core_nrw_data_li;
wire core_nrw_ready_lo;
// outgoing from nrw to asm
wire core_asm_valid_li;
wire [core_channels_p*channel_width_p/bao_narrow_lp-1:0] core_asm_data_li;
wire core_asm_ready_lo;
// out to core
wire core_asm_valid_lo;
wire [core_channels_p*channel_width_p-1:0] core_asm_data_lo;
wire core_asm_yumi_li;
typedef logic [`BSG_MAX($clog2(core_channels_p/bao_narrow_lp),1)-1:0] bsg_comm_link_active_out_vec_t;
typedef logic [`BSG_MAX($clog2(core_channels_p),1)-1:0] bsg_comm_link_active_in_vec_t;
// de-bond channel into multiple individual channels
bsg_assembler_out #(.width_p(channel_width_p)
,.num_in_p(core_channels_p/bao_narrow_lp)
,.num_out_p(link_channels_p)
,.out_channel_count_mask_p(channel_mask_p)
) bao
(.clk (core_clk_i )
,.reset (core_channel_reset)
,.calibration_done_i(core_calib_done_vec_r[2])
,.valid_i(core_asm_valid_li)
,.data_i (core_asm_data_li )
,.ready_o(core_asm_ready_lo)
// typesafe equivalent to core_channels_p-1
,.in_top_channel_i( (bsg_comm_link_active_out_vec_t ' (core_channels_p/bao_narrow_lp))
- 1'b1
)
,.out_top_channel_i(core_top_active_channel_bao_r)
,.valid_o(core_asm_to_sso_valid)
,.data_o( core_asm_to_sso_data )
,.ready_i(core_asm_to_sso_ready_sbox)
);
// we will not say that data is available unless
// calibration is done; keeps interface clean.
wire core_valid_tmp;
assign core_asm_valid_lo = core_valid_tmp & core_calib_done_vec_r[2];
// merge them into one bonded channel
bsg_assembler_in #(.width_p(channel_width_p)
,.num_in_p(link_channels_p)
,.num_out_p(core_channels_p)
,.in_channel_count_mask_p(channel_mask_p)
) bai
(.clk (core_clk_i )
,.reset (core_channel_reset)
,.calibration_done_i (core_calib_done_vec_r[3] )
,.valid_i(core_ssi_to_asm_valid_sbox)
,.data_i (core_ssi_to_asm_data_sbox )
,.yumi_o (core_ssi_to_asm_yumi )
,.in_top_channel_i(core_top_active_channel_bai_r)
// typesafe equivalent to core_channels_p-1
,.out_top_channel_i((bsg_comm_link_active_in_vec_t ' (core_channels_p)) - 1'b1)
,.valid_o(core_valid_tmp)
,.data_o (core_asm_data_lo )
,.yumi_i (core_asm_yumi_li )
);
if (bao_narrow_lp == 2)
begin: nrw
bsg_fifo_1r1w_narrowed #(.width_p(channel_width_p*core_channels_p)
,.els_p(2)
,.width_out_p(channel_width_p*core_channels_p/bao_narrow_lp)
) nrw
(.clk_i(core_clk_i)
,.reset_i(~core_calib_done_vec_r[4])
// from FSB
,.v_i (core_nrw_valid_li)
,.data_i (core_nrw_data_li )
,.ready_o(core_nrw_ready_lo)
// to assembler
,.v_o (core_asm_valid_li)
,.data_o(core_asm_data_li)
,.yumi_i(core_asm_ready_lo & core_asm_valid_li)
);
end // block: nrw
else
begin : not_nrw
assign core_asm_valid_li = core_nrw_valid_li;
assign core_asm_data_li = core_nrw_data_li;
assign core_nrw_ready_lo = core_asm_ready_lo;
end
bsg_fsb #(.width_p(channel_width_p*core_channels_p)
,.nodes_p(nodes_p)
,.enabled_at_start_vec_p(enabled_at_start_vec_p)
,.snoop_vec_p(snoop_vec_p)
) fsb
(.clk_i (core_clk_i)
,.reset_i(~core_calib_done_vec_r[5])
// from assembler
,.asm_v_i (core_asm_valid_lo)
,.asm_data_i(core_asm_data_lo )
,.asm_yumi_o(core_asm_yumi_li )
// to assembler
,.asm_v_o (core_nrw_valid_li)
,.asm_data_o (core_nrw_data_li )
,.asm_ready_i(core_nrw_ready_lo)
// into nodes
,.node_v_o (core_node_v_o )
,.node_data_o (core_node_data_o )
,.node_ready_i (core_node_ready_i )
,.node_en_r_o (core_node_en_r_o )
,.node_reset_r_o(core_node_reset_r_o)
// out of nodes
,.node_v_i (core_node_v_i )
,.node_data_i(core_node_data_i)
,.node_yumi_o(core_node_yumi_o)
);
endmodule
|
module
.rdp_rdy_i (rd_rdy),// (rd_rdy),
.rdp_valid_o (rd_valid),
.rd_addr_o (rd_addr),
.rd_bl_o (rd_bl)
);
/* afifo #
(
.TCQ (TCQ),
.DSIZE (DWIDTH),
.FIFO_DEPTH (32),
.ASIZE (5),
.SYNC (1) // set the SYNC to 1 because rd_clk = wr_clk to reduce latency
)
rd_mdata_fifo
(
.wr_clk (clk_i),
.rst (rst_rb[0]),
.wr_en (!memc_rd_empty_i),
.wr_data (memc_rd_data_i),
.rd_en (memc_rd_en_o),
.rd_clk (clk_i),
.rd_data (rd_v6_mdata),
.full (),
.almost_full (rd_mdata_fifo_afull),
.empty (rd_mdata_fifo_empty)
);
*/
wire cmd_rd_en;
assign cmd_rd_en = memc_cmd_en_o;
assign rdpath_data_valid_i =!memc_rd_empty_i ;
assign rdpath_rd_data_i = memc_rd_data_i ;
generate
if (PORT_MODE == "RD_MODE" || PORT_MODE == "BI_MODE")
begin : RD_PATH
read_data_path
#(
.TCQ (TCQ),
.FAMILY (FAMILY) ,
.MEM_TYPE (MEM_TYPE),
.BL_WIDTH (BL_WIDTH),
.nCK_PER_CLK (nCK_PER_CLK),
.MEM_BURST_LEN (MEM_BURST_LEN),
.START_ADDR (PRBS_SADDR),
.CMP_DATA_PIPE_STAGES (CMP_DATA_PIPE_STAGES),
.ADDR_WIDTH (ADDR_WIDTH),
.SEL_VICTIM_LINE (SEL_VICTIM_LINE),
.DATA_PATTERN (DATA_PATTERN),
.DWIDTH (DWIDTH),
.NUM_DQ_PINS (NUM_DQ_PINS),
.MEM_COL_WIDTH (MEM_COL_WIDTH)
)
read_data_path
(
.clk_i (clk_i),
.rst_i (rst_rb),
.manual_clear_error (manual_clear_error),
.cmd_rdy_o (rd_rdy),
.cmd_valid_i (rd_valid),
.memc_cmd_full_i (memc_cmd_full_i),
.prbs_fseed_i (data_seed_i),
.cmd_sent (memc_cmd_instr_o),
.bl_sent (memc_bl_o[5:0]),
.cmd_en_i (cmd_rd_en),
.data_mode_i (data_mode_r_b),
.fixed_data_i (fixed_data_i),
.simple_data0 (simple_data0),
.simple_data1 (simple_data1),
.simple_data2 (simple_data2),
.simple_data3 (simple_data3),
.simple_data4 (simple_data4),
.simple_data5 (simple_data5),
.simple_data6 (simple_data6),
.simple_data7 (simple_data7),
.mode_load_i (mode_load_i),
.addr_i (rd_addr),
.bl_i (rd_bl),
.data_rdy_o (memc_rd_en_o),
.data_valid_i (rdpath_data_valid_i),
.data_i (rdpath_rd_data_i),
.data_error_o (cmp_error),
.cmp_data_valid (cmp_data_valid),
.cmp_data_o (cmp_data),
.rd_mdata_o (mem_rd_data ),
.cmp_addr_o (cmp_addr),
.cmp_bl_o (cmp_bl),
.dq_error_bytelane_cmp (dq_error_bytelane_cmp),
//****************************************************
.cumlative_dq_lane_error_r (cumlative_dq_lane_error),
.cumlative_dq_r0_bit_error_r (cumlative_dq_r0_bit_error),
.cumlative_dq_f0_bit_error_r (cumlative_dq_f0_bit_error),
.cumlative_dq_r1_bit_error_r (cumlative_dq_r1_bit_error),
.cumlative_dq_f1_bit_error_r (cumlative_dq_f1_bit_error),
.dq_r0_bit_error_r (dq_r0_bit_error_r),
.dq_f0_bit_error_r (dq_f0_bit_error_r),
.dq_r1_bit_error_r (dq_r1_bit_error_r),
.dq_f1_bit_error_r (dq_f1_bit_error_r),
.dq_r0_read_bit_r (dq_r0_read_bit),
.dq_f0_read_bit_r (dq_f0_read_bit),
.dq_r1_read_bit_r (dq_r1_read_bit),
.dq_f1_read_bit_r (dq_f1_read_bit),
.dq_r0_expect_bit_r (dq_r0_expect_bit),
.dq_f0_expect_bit_r (dq_f0_expect_bit ),
.dq_r1_expect_bit_r (dq_r1_expect_bit),
.dq_f1_expect_bit_r (dq_f1_expect_bit ),
.error_addr_o (error_addr)
);
end
else
begin
assign cmp_error = 1'b0;
assign cmp_data_valid = 1'b0;
assign cmp_data ='b0;
end
endgenerate
assign wr_path_data_rdy_i = !(memc_wr_full_i );
generate
if (PORT_MODE == "WR_MODE" || PORT_MODE == "BI_MODE")
begin : WR_PATH
write_data_path
#(
.TCQ (TCQ),
.FAMILY (FAMILY),
.nCK_PER_CLK (nCK_PER_CLK),
.MEM_TYPE (MEM_TYPE),
.START_ADDR (PRBS_SADDR),
.BL_WIDTH (BL_WIDTH),
.MEM_BURST_LEN (MEM_BURST_LEN),
.ADDR_WIDTH (ADDR_WIDTH),
.DATA_PATTERN (DATA_PATTERN),
.DWIDTH (DWIDTH),
.NUM_DQ_PINS (NUM_DQ_PINS),
.SEL_VICTIM_LINE (SEL_VICTIM_LINE),
.MEM_COL_WIDTH (MEM_COL_WIDTH),
.EYE_TEST (EYE_TEST)
)
write_data_path
(
.clk_i(clk_i),
.rst_i (rst_rb),
.cmd_rdy_o (wr_rdy),
.cmd_valid_i (wr_valid),
.cmd_validB_i (wr_validB),
.cmd_validC_i (wr_validC),
.prbs_fseed_i (data_seed_i),
.mode_load_i (mode_load_i),
.wr_data_mask_gen_i (wr_data_mask_gen_i),
.mem_init_done_i (mem_init_done),
.data_mode_i (data_mode_r_c),
.last_word_wr_o (last_word_wr),
.fixed_data_i (fixed_data_i),
.simple_data0 (simple_data0),
.simple_data1 (simple_data1),
.simple_data2 (simple_data2),
.simple_data3 (simple_data3),
.simple_data4 (simple_data4),
.simple_data5 (simple_data5),
.simple_data6 (simple_data6),
.simple_data7 (simple_data7),
.addr_i (wr_addr),
.bl_i (wr_bl),
.data_rdy_i (wr_path_data_rdy_i),
.data_valid_o (memc_wr_en),
.data_o (memc_wr_data),
.data_mask_o (memc_wr_mask_o),
.data_wr_end_o (memc_wr_data_end)
);
end
else
begin
assign memc_wr_en = 1'b0;
assign memc_wr_data = 'b0;
assign memc_wr_mask_o = 'b0;
end
endgenerate
generate
if (MEM_TYPE != "QDR2PLUS" && (FAMILY == "VIRTEX6" || FAMILY == "SPARTAN6" ))
begin: nonQDR_WR
assign memc_wr_en_o = memc_wr_en;
assign memc_wr_data_o = memc_wr_data ;
assign memc_wr_data_end_o = (nCK_PER_CLK == 4) ? memc_wr_data_end: memc_wr_data_end;
end
// QDR
else
begin: QDR_WR
always @ (posedge clk_i)
memc_wr_data_r <= memc_wr_data;
assign memc_wr_en_o = memc_wr_en;
assign memc_wr_data_o = memc_wr_data_r ;
assign memc_wr_data_end_o = memc_wr_data_end;
end
endgenerate
//QDR
always @ (posedge clk_i)
begin
if (memc_wr_full_i)
begin
memc_wr_en_r <= 1'b0;
end
else
begin
memc_wr_en_r <= memc_wr_en;
end
end
tg_status
#(
.TCQ (TCQ),
.DWIDTH (DWIDTH)
)
tg_status
(
.clk_i (clk_i),
.rst_i (rst_ra[2]),
.manual_clear_error (manual_clear_error),
.data_error_i (cmp_error),
.cmp_data_i (cmp_data),
.rd_data_i (mem_rd_data ),
.cmp_addr_i (cmp_addr),
.cmp_bl_i (cmp_bl),
.mcb_cmd_full_i (memc_cmd_full_i),
.mcb_wr_full_i (memc_wr_full_i),
.mcb_rd_empty_i (memc_rd_empty_i),
.error_status (error_status),
.error (error)
);
endmodule
|
module sky130_fd_sc_hd__and2 (
X,
A,
B
);
// Module ports
output X;
input A;
input B;
// Local signals
wire and0_out_X;
// Name Output Other arguments
and and0 (and0_out_X, A, B );
buf buf0 (X , and0_out_X );
endmodule
|
module sky130_fd_sc_ls__o22a (
//# {{data|Data Signals}}
input A1 ,
input A2 ,
input B1 ,
input B2 ,
output X ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
|
module control_o (reset, rxd, StringReady, CharReady, parity, ready, error, WriteChar, WriteString, PossibleStart, clk_2, check);
input rxd;
input StringReady;
input CharReady;
input parity;
input clk_2;
input check;
input reset;
output reg ready;
output reg error;
output reg WriteChar;
output reg WriteString;
output reg PossibleStart;
reg [2:0] current_state;
reg [2:0] next_state;
// se les ponen nombres a los estados para que en el case se pueda entender y manejar mejor
parameter IDLE = 3'b000;
parameter POSSIBLESTART = 3'b001;
parameter READ = 3'b010;
parameter ERROR = 3'b011;
parameter WRITE = 3'b100;
parameter STOP = 3'b101;
always @(current_state or rxd or check or CharReady or StringReady or reset or parity) begin
if (reset==1'b1) begin
next_state <= 3'b000;
ready =1'b0;
error = 1'b0;
WriteString = 1'b0;
WriteChar = 1'b0;
PossibleStart = 1'b0;
end
else begin
case (current_state)
IDLE: begin
if (rxd==1)
next_state<=IDLE;
else
next_state<=POSSIBLESTART;
ready=1'b0;
error=1'b0;
WriteChar=1'b0;
WriteString=1'b0;
PossibleStart=1'b0;
end // case: IDLE
POSSIBLESTART: begin
if (check == 1) begin
if (rxd == 0) begin
next_state<=READ;
end
else
next_state<=IDLE;
end
else
next_state<=POSSIBLESTART;
ready=1'b0;
error=1'b0;
WriteChar=1'b0;
WriteString=1'b0;
PossibleStart=1'b1;
end // case: POSSIBLESTART
READ: begin
if (CharReady==0)
next_state<=READ;
else
next_state<=ERROR;
ready=1'b0;
error=1'b0;
WriteChar=1'b1;
WriteString=1'b0;
PossibleStart=1'b0;
end // case: READ
ERROR: begin
next_state<=WRITE;
if (parity==1)
error=1'b1;
else
error=1'b0;
ready=1'b0;
WriteChar=1'b0;
WriteString=1'b0;
PossibleStart=1'b0;
end // case: ERROR
WRITE: begin
if (StringReady==0)
next_state<=IDLE;
else
next_state<=STOP;
ready=1'b0;
error=1'b0;
WriteChar=1'b0;
WriteString=1'b1;
PossibleStart=1'b0;
end // case: WRITE
STOP: begin
next_state<=IDLE;
ready=1'b1;
error=1'b0;
WriteChar=1'b0;
WriteString=1'b0;
PossibleStart=1'b0;
end // case: STOP
default: begin
next_state<=IDLE;
ready=1'b0;
error=1'b0;
WriteChar=1'b0;
WriteString=1'b0;
PossibleStart=1'b0;
end
endcase // case (current_state)
end // else: !if(reset==1'b1)
end // always @ (posedge clk_2)
always @(negedge clk_2 or posedge reset) begin
if (reset == 1'b1) begin
current_state<=IDLE;
end
else begin
current_state<=next_state;
end
end
endmodule
|
module testcase_TENC();
localparam X_WIDTH = 5;
localparam Y_WIDTH = 5;
localparam PROC_CYCLES = 16;
localparam TOTAL_PAQUETES = 100000;
localparam TRAFFIC = 10;
//
localparam NODOS_INYECCION = X_WIDTH + X_WIDTH;
localparam STEP = TOTAL_PAQUETES / NODOS_INYECCION;
// -- Instancia de harnes de pruebas ----------------------------- >>>>>
/*
-- Descripcion: Instancia de Nucleo de la red + los modulos source y
sink para la captura y emicion de paquetes de
prueba.
Este arnes incluye deflectores en los puertos del
cuadrante 'x+' y 'y-'.
-- Parametros:
-- X_WIDTH: Numero de nodos en la dimension X de la red.
En otras palabra el numero de nodos por fila
de la red.
-- Y_WIDTH: Numero de nodos en la dimension Y de la red.
En otras palabra el numero de nodos por
columna de la red.
-- PROC_CYCLES: Numero de ciclos de procesamiento que
ejecutara el modulo 'test_engine' de
cada nodo de la red.
*/
harness_TENC
#(
.X_WIDTH (X_WIDTH),
.Y_WIDTH (Y_WIDTH),
.PROC_CYCLES (PROC_CYCLES)
)
arnes
();
// -- variables de simulacion ------------------------------------ >>>>>
integer sum = 0;
/*
-- Descripcion: La variable 'x_deflector' almacena las direcciones
'x' de todos los deflectores de la red. La variable
'y_deflector' lleva a cabo la misma tarea pero con
las direcciones en 'y'.
Las variables 'x_gate' y 'y_gate' cumplen la misma
tarea que las variables anteriormente mencionadas
pero para las 'gate' de salida de la red.
*/
integer x_deflectors [0:NODOS_INYECCION - 1] = {
1,
5,
2,
4,
3,
3,
4,
2,
5,
1
};
integer y_deflectors [0:NODOS_INYECCION - 1] = {
0,
6,
0,
6,
0,
6,
0,
6,
0,
6
};
integer x_gates [0:NODOS_INYECCION - 1] = {
1,
5,
1,
5,
1,
5,
1,
5,
1,
5
};
integer y_gates [0:NODOS_INYECCION - 1] = {
1,
5,
2,
4,
3,
3,
4,
2,
5,
1
};
// -- Generadores de trafico ------------------------------------- >>>>>
genvar index_y;
// -- Generadores de puertos en X- --------------------------- >>>>>
generate
for(index_y = 0; index_y < Y_WIDTH; index_y = index_y + 1)
begin: XNEG_generator
// -- Bloque de inyector para puertos XNEG ----------- >>>>>
initial
begin: xneg_injectors
integer packet_count;
integer dest;
integer gate;
integer traffic_arbiter;
integer seed;
integer packet_serial;
// -- Inicializar Variables ------------------ >>>>>
seed = $stime + (((-1)^(index_y + 2)) * ((Y_WIDTH * STEP) + (index_y * STEP)));
//traffic_arbiter = ({$random(seed)}) % 10;
traffic_arbiter = $urandom(seed) % 10;
//dest = ({$random(seed)}) % NODOS_INYECCION;
//gate = (dest * STEP) % NODOS_INYECCION;
dest = index_y;
gate = index_y;
//packet_serial = 0;
packet_serial = index_y * STEP;
// -- Habilitacion de observador ------------- >>>>>
arnes.xneg_ports[index_y].source.open_observer();
// -- Espera de Reset de la red -------------- >>>>>
@(negedge arnes.reset);
// -- Inicio de ciclo de envio de paquetes --- >>>>>
for (packet_count = (index_y * STEP); packet_count < ((index_y * STEP) + STEP); packet_count = packet_count + 1)
begin
@(posedge arnes.clk)
#(arnes.Thold)
if (traffic_arbiter < TRAFFIC)
begin
arnes.xneg_ports[index_y].packet_generator.network_directed_packet(x_deflectors[dest], y_deflectors[dest], x_gates[gate], y_gates[gate], packet_serial);
arnes.xneg_ports[index_y].source.send_packet(arnes.xneg_ports[index_y].packet_generator.packet);
packet_serial = packet_serial + 1;
end
else
begin
packet_count = packet_count - 1;
end
//traffic_arbiter = (traffic_arbiter + 1) % 10;
traffic_arbiter = $urandom(seed) % 10;
dest = (dest + 1) % NODOS_INYECCION;
gate = (gate + 1) % NODOS_INYECCION;
end
sum = sum + 1;
#(10);
arnes.xneg_ports[index_y].source.close_observer();
end
// -- Observador de salida --------------------------- >>>>>
initial
begin
arnes.xneg_ports[index_y].sink.open_observer();
@(negedge arnes.reset);
@(posedge arnes.clk & sum == (NODOS_INYECCION));
repeat(400)
@(negedge arnes.clk);
arnes.xneg_ports[index_y].sink.close_observer();
end
end
endgenerate
// -- Generadores de puertos en Y+ --------------------------- >>>>>
generate
for(index_y = 0; index_y < Y_WIDTH; index_y = index_y + 1)
begin: XPOS_generator
// -- Bloque de inyector para puertos YPOS ----------- >>>>>
initial
begin: xpos_injectors
integer packet_count;
integer dest;
integer gate;
integer traffic_arbiter;
integer seed;
integer packet_serial;
// -- Inicializar Variables ------------------ >>>>>
seed = $stime + (((-1)^(index_y + 2)) * ((X_WIDTH * STEP) + (index_y * STEP)));
//traffic_arbiter = ({$random(seed)}) % 10;
traffic_arbiter = $urandom(seed) % 10;
//dest = ({$random(seed)}) % NODOS_INYECCION;
//gate = (dest * STEP) % NODOS_INYECCION;
dest = index_y + 5;
gate = index_y + 5;
//packet_serial = 0;
packet_serial = ((Y_WIDTH * STEP) + (index_y * STEP));
// -- Habilitacion de observador ------------- >>>>>
arnes.xpos_ports[index_y].source.open_observer();
// -- Espera de Reset de la red -------------- >>>>>
@(negedge arnes.reset);
// -- Inicio de ciclo de envio de paquetes --- >>>>>
for (packet_count = ((Y_WIDTH * STEP) + (index_y * STEP)); packet_count < ((Y_WIDTH * STEP) + ((index_y + 1) * STEP)); packet_count = packet_count + 1)
begin
@(posedge arnes.clk)
#(arnes.Thold)
if (traffic_arbiter < TRAFFIC)
begin
arnes.xpos_ports[index_y].packet_generator.network_directed_packet(x_deflectors[dest], y_deflectors[dest], x_gates[gate], y_gates[gate], packet_serial);
arnes.xpos_ports[index_y].source.send_packet(arnes.xpos_ports[index_y].packet_generator.packet);
packet_serial = packet_serial + 1;
end
else
begin
packet_count = packet_count - 1;
end
//traffic_arbiter = (traffic_arbiter + 1) % 10;
traffic_arbiter = $urandom(seed) % 10;
dest = (dest + 1) % NODOS_INYECCION;
gate = (gate + 1) % NODOS_INYECCION;
end
sum = sum + 1;
#(10);
arnes.xpos_ports[index_y].source.close_observer();
end
// -- Observador de salida --------------------------- >>>>>
initial
begin
arnes.xpos_ports[index_y].sink.open_observer();
@(negedge arnes.reset);
@(posedge arnes.clk & sum == (NODOS_INYECCION));
repeat(400)
@(negedge arnes.clk);
arnes.xpos_ports[index_y].sink.close_observer();
end
end
endgenerate
initial
begin : ciclo_principal
integer total_recepcion;
integer fp;
arnes.sync_reset();
@(posedge arnes.clk & sum == (NODOS_INYECCION))
// DBG: $display("suma: ", sum);
repeat(800)
@(negedge arnes.clk);
fp = $fopen("reception_resume.dat", "w");
if(!fp)
$display("Could not open reception_resume.dat");
else
$display("Success opening reception_resume.dat");
total_recepcion = arnes.xpos_ports[0].sink.packet_count +
arnes.xpos_ports[1].sink.packet_count +
arnes.xpos_ports[2].sink.packet_count +
arnes.xpos_ports[3].sink.packet_count +
arnes.xpos_ports[4].sink.packet_count +
arnes.xneg_ports[0].sink.packet_count +
arnes.xneg_ports[1].sink.packet_count +
arnes.xneg_ports[2].sink.packet_count +
arnes.xneg_ports[3].sink.packet_count +
arnes.xneg_ports[4].sink.packet_count;
$fdisplay(fp, "%d", arnes.xneg_ports[0].sink.packet_count);
$fdisplay(fp, "%d", arnes.xneg_ports[1].sink.packet_count);
$fdisplay(fp, "%d", arnes.xneg_ports[2].sink.packet_count);
$fdisplay(fp, "%d", arnes.xneg_ports[3].sink.packet_count);
$fdisplay(fp, "%d", arnes.xneg_ports[4].sink.packet_count);
$fdisplay(fp, "%d", arnes.xpos_ports[0].sink.packet_count);
$fdisplay(fp, "%d", arnes.xpos_ports[1].sink.packet_count);
$fdisplay(fp, "%d", arnes.xpos_ports[2].sink.packet_count);
$fdisplay(fp, "%d", arnes.xpos_ports[3].sink.packet_count);
$fdisplay(fp, "%d", arnes.xpos_ports[4].sink.packet_count);
$fclose(fp);
$display("reception_resume.dat se cerro de manera exitosa");
$display("",);
$display("Total de paquetes enviados 'xpos(1,6)': ", arnes.xpos_ports[0].source.packet_count);
$display("",);
$display("Total de paquetes enviados 'xpos(2,6)': ", arnes.xpos_ports[1].source.packet_count);
$display("",);
$display("Total de paquetes enviados 'xpos(3,6)': ", arnes.xpos_ports[2].source.packet_count);
$display("",);
$display("Total de paquetes enviados 'xpos(4,6)': ", arnes.xpos_ports[3].source.packet_count);
$display("",);
$display("Total de paquetes enviados 'xpos(5,6)': ", arnes.xpos_ports[4].source.packet_count);
$display("",);
$display("Total de paquetes enviados 'xneg(1,0)': ", arnes.xneg_ports[0].source.packet_count);
$display("",);
$display("Total de paquetes enviados 'xneg(2,0)': ", arnes.xneg_ports[1].source.packet_count);
$display("",);
$display("Total de paquetes enviados 'xneg(3,0)': ", arnes.xneg_ports[2].source.packet_count);
$display("",);
$display("Total de paquetes enviados 'xneg(4,0)': ", arnes.xneg_ports[3].source.packet_count);
$display("",);
$display("Total de paquetes enviados 'xneg(5,0)': ", arnes.xneg_ports[4].source.packet_count);
$display("",);
$display("",);
$display("",);
$display("",);
$display("",);
$display("Total de paquetes recibidos 'xpos(1,6)': ", arnes.xpos_ports[0].sink.packet_count);
$display("",);
$display("Total de paquetes recibidos 'xpos(2,6)': ", arnes.xpos_ports[1].sink.packet_count);
$display("",);
$display("Total de paquetes recibidos 'xpos(3,6)': ", arnes.xpos_ports[2].sink.packet_count);
$display("",);
$display("Total de paquetes recibidos 'xpos(4,6)': ", arnes.xpos_ports[3].sink.packet_count);
$display("",);
$display("Total de paquetes recibidos 'xpos(5,6)': ", arnes.xpos_ports[4].sink.packet_count);
$display("",);
$display("Total de paquetes recibidos 'xneg(1,0)': ", arnes.xneg_ports[0].sink.packet_count);
$display("",);
$display("Total de paquetes recibidos 'xneg(2,0)': ", arnes.xneg_ports[1].sink.packet_count);
$display("",);
$display("Total de paquetes recibidos 'xneg(3,0)': ", arnes.xneg_ports[2].sink.packet_count);
$display("",);
$display("Total de paquetes recibidos 'xneg(4,0)': ", arnes.xneg_ports[3].sink.packet_count);
$display("",);
$display("Total de paquetes recibidos 'xneg(5,0)': ", arnes.xneg_ports[4].sink.packet_count);
$display("",);
$display("Total de paquetes recibidos 'testcase': ", total_recepcion);
#(10);
$stop;
$finish;
end
endmodule
|
module sky130_fd_sc_lp__mux4 (
X ,
A0 ,
A1 ,
A2 ,
A3 ,
S0 ,
S1 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A0 ;
input A1 ;
input A2 ;
input A3 ;
input S0 ;
input S1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire mux_4to20_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
sky130_fd_sc_lp__udp_mux_4to2 mux_4to20 (mux_4to20_out_X , A0, A1, A2, A3, S0, S1 );
sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, mux_4to20_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
|
module cf_add (
// data_p = data_1 + data_2 + data_3 + data_4 (all the inputs are signed)
clk,
data_1,
data_2,
data_3,
data_4,
data_p,
// ddata_out is internal pipe-line matched for ddata_in
ddata_in,
ddata_out);
// delayed data bus width
parameter DELAY_DATA_WIDTH = 16;
parameter DW = DELAY_DATA_WIDTH - 1;
input clk;
input [24:0] data_1;
input [24:0] data_2;
input [24:0] data_3;
input [24:0] data_4;
output [ 7:0] data_p;
input [DW:0] ddata_in;
output [DW:0] ddata_out;
reg [DW:0] p1_ddata = 'd0;
reg [24:0] p1_data_1 = 'd0;
reg [24:0] p1_data_2 = 'd0;
reg [24:0] p1_data_3 = 'd0;
reg [24:0] p1_data_4 = 'd0;
reg [DW:0] p2_ddata = 'd0;
reg [24:0] p2_data_0 = 'd0;
reg [24:0] p2_data_1 = 'd0;
reg [DW:0] p3_ddata = 'd0;
reg [24:0] p3_data = 'd0;
reg [DW:0] ddata_out = 'd0;
reg [ 7:0] data_p = 'd0;
wire [24:0] p1_data_1_p_s;
wire [24:0] p1_data_1_n_s;
wire [24:0] p1_data_1_s;
wire [24:0] p1_data_2_p_s;
wire [24:0] p1_data_2_n_s;
wire [24:0] p1_data_2_s;
wire [24:0] p1_data_3_p_s;
wire [24:0] p1_data_3_n_s;
wire [24:0] p1_data_3_s;
wire [24:0] p1_data_4_p_s;
wire [24:0] p1_data_4_n_s;
wire [24:0] p1_data_4_s;
// pipe line stage 1, get the two's complement versions
assign p1_data_1_p_s = {1'b0, data_1[23:0]};
assign p1_data_1_n_s = ~p1_data_1_p_s + 1'b1;
assign p1_data_1_s = (data_1[24] == 1'b1) ? p1_data_1_n_s : p1_data_1_p_s;
assign p1_data_2_p_s = {1'b0, data_2[23:0]};
assign p1_data_2_n_s = ~p1_data_2_p_s + 1'b1;
assign p1_data_2_s = (data_2[24] == 1'b1) ? p1_data_2_n_s : p1_data_2_p_s;
assign p1_data_3_p_s = {1'b0, data_3[23:0]};
assign p1_data_3_n_s = ~p1_data_3_p_s + 1'b1;
assign p1_data_3_s = (data_3[24] == 1'b1) ? p1_data_3_n_s : p1_data_3_p_s;
assign p1_data_4_p_s = {1'b0, data_4[23:0]};
assign p1_data_4_n_s = ~p1_data_4_p_s + 1'b1;
assign p1_data_4_s = (data_4[24] == 1'b1) ? p1_data_4_n_s : p1_data_4_p_s;
always @(posedge clk) begin
p1_ddata <= ddata_in;
p1_data_1 <= p1_data_1_s;
p1_data_2 <= p1_data_2_s;
p1_data_3 <= p1_data_3_s;
p1_data_4 <= p1_data_4_s;
end
// pipe line stage 2, get the sum (intermediate, 4->2)
always @(posedge clk) begin
p2_ddata <= p1_ddata;
p2_data_0 <= p1_data_1 + p1_data_2;
p2_data_1 <= p1_data_3 + p1_data_4;
end
// pipe line stage 3, get the sum (final, 2->1)
always @(posedge clk) begin
p3_ddata <= p2_ddata;
p3_data <= p2_data_0 + p2_data_1;
end
// output registers, output is unsigned (0 if sum is < 0) and saturated.
// the inputs are expected to be 1.4.20 format (output is 8bits).
always @(posedge clk) begin
ddata_out <= p3_ddata;
if (p3_data[24] == 1'b1) begin
data_p <= 8'h00;
end else if (p3_data[23:20] == 'd0) begin
data_p <= p3_data[19:12];
end else begin
data_p <= 8'hff;
end
end
endmodule
|
module lsu
(/*AUTOARG*/
// Outputs
issue_ready,
vgpr_source1_rd_en, vgpr_source2_rd_en,
sgpr_source1_rd_en, sgpr_source2_rd_en,
mem_gm_or_lds, tracemon_gm_or_lds,
vgpr_dest_wr_en,
mem_rd_en, mem_wr_en,
sgpr_dest_wr_en,
exec_rd_wfid,
mem_tag_req,
sgpr_source1_addr, sgpr_source2_addr, sgpr_dest_addr,
vgpr_source1_addr, vgpr_source2_addr, vgpr_dest_addr,
vgpr_dest_wr_mask, mem_wr_mask,
sgpr_dest_data,
mem_addr,
vgpr_dest_data, mem_wr_data, rfa_dest_wr_req,
lsu_done, lsu_done_wfid,
sgpr_instr_done, sgpr_instr_done_wfid,
vgpr_instr_done, vgpr_instr_done_wfid,
tracemon_retire_pc, tracemon_mem_addr, tracemon_idle,
// Inputs
clk, rst, issue_lsu_select, mem_ack, issue_wfid, mem_tag_resp,
issue_source_reg1, issue_source_reg2, issue_source_reg3,
issue_dest_reg, issue_mem_sgpr, issue_imm_value0, issue_lds_base,
issue_imm_value1, issue_opcode, sgpr_source2_data,
exec_rd_m0_value, issue_instr_pc, exec_exec_value,
sgpr_source1_data, vgpr_source2_data, vgpr_source1_data,
mem_rd_data, lsu_stall
);
parameter MEMORY_BUS_WIDTH = 32;
parameter MEM_SLOTS = 1;
input clk;
input rst;
input issue_lsu_select, mem_ack;
input [5:0] issue_wfid;
input [6:0] mem_tag_resp;
input [11:0] issue_source_reg1, issue_source_reg2, issue_source_reg3,
issue_dest_reg, issue_mem_sgpr;
input [15:0] issue_imm_value0, issue_lds_base;
input [31:0] issue_imm_value1, issue_opcode, sgpr_source2_data, exec_rd_m0_value,
issue_instr_pc;
input [63:0] exec_exec_value;
input [127:0] sgpr_source1_data;
input [2047:0] vgpr_source1_data;
input [2047:0] vgpr_source2_data;
input [MEMORY_BUS_WIDTH-1:0] mem_rd_data;
input lsu_stall;
output issue_ready, vgpr_source1_rd_en, vgpr_source2_rd_en,
sgpr_source1_rd_en, sgpr_source2_rd_en, mem_gm_or_lds,
tracemon_gm_or_lds;
output vgpr_dest_wr_en, mem_rd_en, mem_wr_en;
output [3:0] sgpr_dest_wr_en;
output [5:0] exec_rd_wfid;
output [6:0] mem_tag_req;
output [8:0] sgpr_source1_addr, sgpr_source2_addr, sgpr_dest_addr;
output [9:0] vgpr_source1_addr, vgpr_source2_addr, vgpr_dest_addr;
output [63:0] vgpr_dest_wr_mask, mem_wr_mask;
output [127:0] sgpr_dest_data;
output [31:0] mem_addr;
output [2047:0] vgpr_dest_data;
output [MEMORY_BUS_WIDTH-1:0] mem_wr_data;
output rfa_dest_wr_req;
output lsu_done;
output sgpr_instr_done;
output vgpr_instr_done;
output [5:0] lsu_done_wfid;
output [5:0] sgpr_instr_done_wfid;
output [5:0] vgpr_instr_done_wfid;
output [31:0] tracemon_retire_pc;
output [2047:0] tracemon_mem_addr;
output tracemon_idle;
assign exec_rd_wfid = issue_wfid;
reg [31:0] issue_opcode_flopped;
reg [15:0] issue_lds_base_flopped;
reg [15:0] issue_imm_value0_flopped;
wire [2047:0] calc_mem_addr;
wire gm_or_lds;
wire decoded_sgpr_source1_rd_en;
wire decoded_sgpr_source2_rd_en;
wire [8:0] decoded_sgpr_source1_addr;
wire [8:0] decoded_sgpr_source2_addr;
//wire decoded_vgpr_source1_rd_en;
wire decoded_vgpr_source2_rd_en;
wire [9:0] decoded_vgpr_source1_addr;
wire [9:0] decoded_vgpr_source2_addr;
wire [5:0] mem_op_cnt;
wire mem_op_rd;
wire mem_op_wr;
wire mem_gpr;
wire [3:0] sgpr_wr_mask;
wire [1:0] gpr_op_depth;
always@(posedge clk) begin
if(rst) begin
issue_opcode_flopped <= 32'd0;
issue_lds_base_flopped <= 16'd0;
issue_imm_value0_flopped <= 16'd0;
end
else begin
issue_opcode_flopped <= issue_opcode;
issue_lds_base_flopped <= issue_lds_base;
issue_imm_value0_flopped <= issue_imm_value0;
end
end
// The decoder requires two cycles to receive the entire opcode. On the second
// cycle it generates register read operations for getting addres values from
// the GPRs.
lsu_opcode_decoder lsu_opcode_decoder0(
.lsu_selected(issue_lsu_select),
.lsu_opcode(issue_opcode),
.issue_source_reg1(issue_source_reg1),
.issue_source_reg2(issue_source_reg2),
.issue_source_reg3(issue_source_reg3),
.issue_mem_sgpr(issue_mem_sgpr),
//.issue_dest_reg(issue_dest_reg_flopped),
.sgpr_source1_rd_en(decoded_sgpr_source1_rd_en),
.sgpr_source2_rd_en(decoded_sgpr_source2_rd_en),
.sgpr_source1_addr(decoded_sgpr_source1_addr),
.sgpr_source2_addr(decoded_sgpr_source2_addr),
.vgpr_source2_rd_en(decoded_vgpr_source2_rd_en),
.vgpr_source1_addr(decoded_vgpr_source1_addr),
.vgpr_source2_addr(decoded_vgpr_source2_addr),
// Signals to indicate a new memory request
.mem_op_cnt(mem_op_cnt),
.mem_op_rd(mem_op_rd),
.mem_op_wr(mem_op_wr),
.mem_gpr(mem_gpr),
.sgpr_wr_mask(sgpr_wr_mask),
.gpr_op_depth(gpr_op_depth)
);
lsu_op_manager lsu_op_manager0(
.lsu_wfid(issue_wfid),
.instr_pc(issue_instr_pc),
// Signals to indicate a new memory request
.mem_op_cnt(mem_op_cnt),
.mem_op_rd(mem_op_rd),
.mem_op_wr(mem_op_wr),
.mem_gpr(mem_gpr),
.gm_or_lds(gm_or_lds),
.sgpr_wr_mask(sgpr_wr_mask),
.gpr_op_depth(gpr_op_depth),
.exec_mask(exec_exec_value),
.mem_in_addr(calc_mem_addr),
.mem_ack(mem_ack),
.mem_rd_data(mem_rd_data),
.vgpr_source1_data(vgpr_source1_data),
.free_mem_slots(1'b0),
.decoded_sgpr_source1_rd_en(decoded_sgpr_source1_rd_en),
.decoded_sgpr_source2_rd_en(decoded_sgpr_source2_rd_en),
.decoded_sgpr_source1_addr(decoded_sgpr_source1_addr),
.decoded_sgpr_source2_addr(decoded_sgpr_source2_addr),
//decoded_vgpr_source1_rd_en,
.decoded_vgpr_source2_rd_en(decoded_vgpr_source2_rd_en),
.decoded_vgpr_source1_addr(decoded_vgpr_source1_addr),
.decoded_vgpr_source2_addr(decoded_vgpr_source2_addr),
.decoded_dest_addr(issue_dest_reg),
.sgpr_dest_data(sgpr_dest_data),
.sgpr_dest_wr_en(sgpr_dest_wr_en),
.sgpr_dest_addr(sgpr_dest_addr),
.vgpr_dest_data(vgpr_dest_data),
.vgpr_dest_wr_en(vgpr_dest_wr_en),
.vgpr_wr_mask(vgpr_dest_wr_mask),
.vgpr_dest_addr(vgpr_dest_addr),
.lsu_rdy(issue_ready),
.lsu_done(lsu_done),
.sgpr_instr_done(sgpr_instr_done),
.vgpr_instr_done(vgpr_instr_done),
.lsu_done_wfid(lsu_done_wfid),
.sgpr_instr_done_wfid(sgpr_instr_done_wfid),
.vgpr_instr_done_wfid(vgpr_instr_done_wfid),
.retire_pc(tracemon_retire_pc),
.retire_gm_or_lds(tracemon_gm_or_lds),
.tracemon_mem_addr(tracemon_mem_addr),
.mem_rd_en(mem_rd_en),
.mem_wr_en(mem_wr_en),
.mem_out_addr(mem_addr),
.mem_wr_data(mem_wr_data),
.mem_tag_req(mem_tag_req),
.mem_gm_or_lds(mem_gm_or_lds),
.sgpr_source1_rd_en(sgpr_source1_rd_en),
.sgpr_source2_rd_en(sgpr_source2_rd_en),
.sgpr_source1_addr(sgpr_source1_addr),
.sgpr_source2_addr(sgpr_source2_addr),
.vgpr_source1_rd_en(vgpr_source1_rd_en),
.vgpr_source2_rd_en(vgpr_source2_rd_en),
.vgpr_source1_addr(vgpr_source1_addr),
.vgpr_source2_addr(vgpr_source2_addr),
.clk(clk),
.rst(rst)
);
// Because the register read operations for the address values will take one
// cycle to complete the opcode needs to be flopped so that the opcode being
// used by the address calculator is properly aligned.
lsu_addr_calculator addr_calc(
.in_vector_source_b(vgpr_source2_data),
.in_scalar_source_a(sgpr_source1_data),
.in_scalar_source_b(sgpr_source2_data),
.in_opcode(issue_opcode_flopped),
.in_lds_base(issue_lds_base_flopped),
.in_imm_value0(issue_imm_value0_flopped),
.out_ld_st_addr(calc_mem_addr),
.out_gm_or_lds(gm_or_lds)
);
assign rfa_dest_wr_req = (|sgpr_dest_wr_en) | vgpr_dest_wr_en;
// Something of a hack, at this point it's not actually needed
assign mem_wr_mask = vgpr_dest_wr_mask;
assign tracemon_idle = issue_ready;
endmodule
|
module ad_data_in #(
// parameters
parameter SINGLE_ENDED = 0,
parameter DEVICE_TYPE = 0,
parameter IODELAY_ENABLE = 1,
parameter IODELAY_CTRL = 0,
parameter IODELAY_GROUP = "dev_if_delay_group") (
// data interface
input rx_clk,
input rx_data_in_p,
input rx_data_in_n,
output rx_data_p,
output rx_data_n,
// delay-data interface
input up_clk,
input up_dld,
input [ 4:0] up_dwdata,
output [ 4:0] up_drdata,
// delay-cntrl interface
input delay_clk,
input delay_rst,
output delay_locked);
// internal parameters
localparam NONE = -1;
localparam VIRTEX7 = 0;
localparam ULTRASCALE_PLUS = 2;
localparam ULTRASCALE = 3;
localparam IODELAY_CTRL_ENABLED = (IODELAY_ENABLE == 1) ? IODELAY_CTRL : 0;
localparam IODELAY_CTRL_SIM_DEVICE = (DEVICE_TYPE == ULTRASCALE_PLUS) ? "ULTRASCALE" :
(DEVICE_TYPE == ULTRASCALE) ? "ULTRASCALE" : "7SERIES";
localparam IODELAY_DEVICE_TYPE = (IODELAY_ENABLE == 1) ? DEVICE_TYPE : NONE;
localparam IODELAY_SIM_DEVICE = (DEVICE_TYPE == ULTRASCALE_PLUS) ? "ULTRASCALE_PLUS" :
(DEVICE_TYPE == ULTRASCALE) ? "ULTRASCALE" : "7SERIES";
// internal signals
wire rx_data_ibuf_s;
wire rx_data_idelay_s;
wire [ 8:0] up_drdata_s;
// delay controller
generate
if (IODELAY_CTRL_ENABLED == 0) begin
assign delay_locked = 1'b1;
end else begin
(* IODELAY_GROUP = IODELAY_GROUP *)
IDELAYCTRL #(.SIM_DEVICE (IODELAY_CTRL_SIM_DEVICE)) i_delay_ctrl (
.RST (delay_rst),
.REFCLK (delay_clk),
.RDY (delay_locked));
end
endgenerate
// receive data interface, ibuf -> idelay -> iddr
generate
if (SINGLE_ENDED == 1) begin
IBUF i_rx_data_ibuf (
.I (rx_data_in_p),
.O (rx_data_ibuf_s));
end else begin
IBUFDS i_rx_data_ibuf (
.I (rx_data_in_p),
.IB (rx_data_in_n),
.O (rx_data_ibuf_s));
end
endgenerate
// idelay
generate
if (IODELAY_DEVICE_TYPE == VIRTEX7) begin
(* IODELAY_GROUP = IODELAY_GROUP *)
IDELAYE2 #(
.CINVCTRL_SEL ("FALSE"),
.DELAY_SRC ("IDATAIN"),
.HIGH_PERFORMANCE_MODE ("FALSE"),
.IDELAY_TYPE ("VAR_LOAD"),
.IDELAY_VALUE (0),
.REFCLK_FREQUENCY (200.0),
.PIPE_SEL ("FALSE"),
.SIGNAL_PATTERN ("DATA"))
i_rx_data_idelay (
.CE (1'b0),
.INC (1'b0),
.DATAIN (1'b0),
.LDPIPEEN (1'b0),
.CINVCTRL (1'b0),
.REGRST (1'b0),
.C (up_clk),
.IDATAIN (rx_data_ibuf_s),
.DATAOUT (rx_data_idelay_s),
.LD (up_dld),
.CNTVALUEIN (up_dwdata),
.CNTVALUEOUT (up_drdata));
end
endgenerate
generate
if ((IODELAY_DEVICE_TYPE == ULTRASCALE) || (IODELAY_DEVICE_TYPE == ULTRASCALE_PLUS)) begin
assign up_drdata = up_drdata_s[8:4];
(* IODELAY_GROUP = IODELAY_GROUP *)
IDELAYE3 #(
.SIM_DEVICE (IODELAY_SIM_DEVICE),
.DELAY_SRC ("IDATAIN"),
.DELAY_TYPE ("VAR_LOAD"),
.REFCLK_FREQUENCY (200.0),
.DELAY_FORMAT ("COUNT"))
i_rx_data_idelay (
.CASC_RETURN (1'b0),
.CASC_IN (1'b0),
.CASC_OUT (),
.CE (1'b0),
.CLK (up_clk),
.INC (1'b0),
.LOAD (up_dld),
.CNTVALUEIN ({up_dwdata, 4'd0}),
.CNTVALUEOUT (up_drdata_s),
.DATAIN (1'b0),
.IDATAIN (rx_data_ibuf_s),
.DATAOUT (rx_data_idelay_s),
.RST (1'b0),
.EN_VTC (~up_dld));
end
endgenerate
generate
if (IODELAY_DEVICE_TYPE == NONE) begin
assign rx_data_idelay_s = rx_data_ibuf_s;
assign up_drdata = 5'd0;
end
endgenerate
// iddr
generate
if ((DEVICE_TYPE == ULTRASCALE) || (DEVICE_TYPE == ULTRASCALE_PLUS)) begin
IDDRE1 #(.DDR_CLK_EDGE ("SAME_EDGE")) i_rx_data_iddr (
.R (1'b0),
.C (rx_clk),
.CB (~rx_clk),
.D (rx_data_idelay_s),
.Q1 (rx_data_p),
.Q2 (rx_data_n));
end
endgenerate
generate
if (DEVICE_TYPE == VIRTEX7) begin
IDDR #(.DDR_CLK_EDGE ("SAME_EDGE")) i_rx_data_iddr (
.CE (1'b1),
.R (1'b0),
.S (1'b0),
.C (rx_clk),
.D (rx_data_idelay_s),
.Q1 (rx_data_p),
.Q2 (rx_data_n));
end
endgenerate
endmodule
|
module top();
// Inputs are registered
reg A;
reg B;
reg VPWR;
reg VGND;
// Outputs are wires
wire COUT;
wire SUM;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
B = 1'bX;
VGND = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 B = 1'b0;
#60 VGND = 1'b0;
#80 VPWR = 1'b0;
#100 A = 1'b1;
#120 B = 1'b1;
#140 VGND = 1'b1;
#160 VPWR = 1'b1;
#180 A = 1'b0;
#200 B = 1'b0;
#220 VGND = 1'b0;
#240 VPWR = 1'b0;
#260 VPWR = 1'b1;
#280 VGND = 1'b1;
#300 B = 1'b1;
#320 A = 1'b1;
#340 VPWR = 1'bx;
#360 VGND = 1'bx;
#380 B = 1'bx;
#400 A = 1'bx;
end
sky130_fd_sc_hs__ha dut (.A(A), .B(B), .VPWR(VPWR), .VGND(VGND), .COUT(COUT), .SUM(SUM));
endmodule
|
module aur1_SYM_GEN
(
// TX_LL Interface
GEN_SCP,
GEN_ECP,
GEN_PAD,
TX_PE_DATA,
TX_PE_DATA_V,
GEN_CC,
// Global Logic Interface
GEN_A,
GEN_K,
GEN_R,
GEN_V,
// Lane Init SM Interface
GEN_K_FSM,
GEN_SP_DATA,
GEN_SPA_DATA,
// GTP Interface
TX_CHAR_IS_K,
TX_DATA,
// System Interface
USER_CLK,
RESET
);
`define DLY #1
//***********************************Port Declarations*******************************
// TX_LL Interface // See description for info about GEN_PAD and TX_PE_DATA_V.
input GEN_SCP; // Generate SCP.
input GEN_ECP; // Generate ECP.
input GEN_PAD; // Replace LSB with Pad character.
input [0:15] TX_PE_DATA; // Data. Transmitted when TX_PE_DATA_V is asserted.
input TX_PE_DATA_V; // Transmit data.
input GEN_CC; // Generate Clock Correction symbols.
// Global Logic Interface // See description for info about GEN_K,GEN_R and GEN_A.
input GEN_A; // Generate A character for MSBYTE
input [0:1] GEN_K; // Generate K character for selected bytes.
input [0:1] GEN_R; // Generate R character for selected bytes.
input [0:1] GEN_V; // Generate Ver data character on selected bytes.
// Lane Init SM Interface
input GEN_K_FSM; // Generate K character on byte 0.
input [0:1] GEN_SP_DATA; // Generate SP data character on selected bytes.
input [0:1] GEN_SPA_DATA; // Generate SPA data character on selected bytes.
// GTP Interface
output [1:0] TX_CHAR_IS_K; // Transmit TX_DATA as a control character.
output [15:0] TX_DATA; // Data to GTP for transmission to channel partner.
// System Interface
input USER_CLK; // Clock for all non-GTP Aurora Logic.
input RESET; // RESET signal to drive TX_CHAR_IS_K to known value
//**************************External Register Declarations****************************
reg [15:0] TX_DATA;
reg [1:0] TX_CHAR_IS_K;
//**************************Internal Register Declarations****************************
// Slack registers. Allow slack for routing delay and automatic retiming.
reg gen_scp_r;
reg gen_ecp_r;
reg gen_pad_r;
reg [0:15] tx_pe_data_r;
reg tx_pe_data_v_r;
reg gen_cc_r;
reg gen_a_r;
reg [0:1] gen_k_r;
reg [0:1] gen_r_r;
reg [0:1] gen_v_r;
reg gen_k_fsm_r;
reg [0:1] gen_sp_data_r;
reg [0:1] gen_spa_data_r;
//*********************************Wire Declarations**********************************
wire [0:1] idle_c;
//*********************************Main Body of Code**********************************
// Register all inputs with the slack registers.
always @(posedge USER_CLK)
begin
gen_scp_r <= `DLY GEN_SCP;
gen_ecp_r <= `DLY GEN_ECP;
gen_pad_r <= `DLY GEN_PAD;
tx_pe_data_r <= `DLY TX_PE_DATA;
tx_pe_data_v_r <= `DLY TX_PE_DATA_V;
gen_cc_r <= `DLY GEN_CC;
gen_a_r <= `DLY GEN_A;
gen_k_r <= `DLY GEN_K;
gen_r_r <= `DLY GEN_R;
gen_v_r <= `DLY GEN_V;
gen_k_fsm_r <= `DLY GEN_K_FSM;
gen_sp_data_r <= `DLY GEN_SP_DATA;
gen_spa_data_r <= `DLY GEN_SPA_DATA;
end
// When none of the msb non_idle inputs are asserted, allow idle characters.
assign idle_c[0] = !( gen_scp_r |
gen_ecp_r |
tx_pe_data_v_r |
gen_cc_r |
gen_k_fsm_r |
gen_sp_data_r[0] |
gen_spa_data_r[0] |
gen_v_r[0]
);
// Generate data for MSB. Note that all inputs must be asserted exclusively, except
// for the GEN_A, GEN_K and GEN_R inputs which are ignored when other characters
// are asserted.
always @ (posedge USER_CLK)
begin
if(gen_scp_r) TX_DATA[15:8] <= `DLY 8'h5c; // K28.2(SCP)
if(gen_ecp_r) TX_DATA[15:8] <= `DLY 8'hfd; // K29.7(ECP)
if(tx_pe_data_v_r) TX_DATA[15:8] <= `DLY tx_pe_data_r[0:7]; // DATA
if(gen_cc_r) TX_DATA[15:8] <= `DLY 8'hf7; // K23.7(CC)
if(idle_c[0] & gen_a_r) TX_DATA[15:8] <= `DLY 8'h7c; // K28.3(A)
if(idle_c[0] & gen_k_r[0]) TX_DATA[15:8] <= `DLY 8'hbc; // K28.5(K)
if(idle_c[0] & gen_r_r[0]) TX_DATA[15:8] <= `DLY 8'h1c; // K28.0(R)
if(gen_k_fsm_r) TX_DATA[15:8] <= `DLY 8'hbc; // K28.5(K)
if(gen_sp_data_r[0]) TX_DATA[15:8] <= `DLY 8'h4a; // D10.2(SP data)
if(gen_spa_data_r[0]) TX_DATA[15:8] <= `DLY 8'h2c; // D12.1(SPA data)
if(gen_v_r[0]) TX_DATA[15:8] <= `DLY 8'he8; // D8.7(Ver data)
end
// Generate control signal for MSB.
always @(posedge USER_CLK)
begin
if(RESET)
TX_CHAR_IS_K[1] <= `DLY 1'b0;
else
TX_CHAR_IS_K[1] <= `DLY !( tx_pe_data_v_r |
gen_sp_data_r[0] |
gen_spa_data_r[0] |
gen_v_r[0]
);
end
// When none of the msb non_idle inputs are asserted, allow idle characters. Note that
// because gen_pad is only valid with the data valid signal, we only look at the data
// valid signal.
assign idle_c[1] = !( gen_scp_r |
gen_ecp_r |
tx_pe_data_v_r |
gen_cc_r |
gen_sp_data_r[1] |
gen_spa_data_r[1] |
gen_v_r[1]
);
// Generate data for LSB. Note that all inputs must be asserted exclusively except for
// the GEN_PAD signal and the GEN_K and GEN_R set. GEN_PAD can be asserted
// at the same time as TX_DATA_VALID. This will override TX_DATA and replace the
// lsb user data with a PAD character. The GEN_K and GEN_R inputs are ignored
// if any other input is asserted.
always @ (posedge USER_CLK)
begin
if(gen_scp_r) TX_DATA[7:0] <= `DLY 8'hfb; // K27.7(SCP)
if(gen_ecp_r) TX_DATA[7:0] <= `DLY 8'hfe; // K30.7(ECP)
if(tx_pe_data_v_r & gen_pad_r) TX_DATA[7:0] <= `DLY 8'h9c; // K28.4(PAD)
if(tx_pe_data_v_r & !gen_pad_r) TX_DATA[7:0] <= `DLY tx_pe_data_r[8:15]; // DATA
if(gen_cc_r) TX_DATA[7:0] <= `DLY 8'hf7; // K23.7(CC)
if(idle_c[1] & gen_k_r[1]) TX_DATA[7:0] <= `DLY 8'hbc; // K28.5(K)
if(idle_c[1] & gen_r_r[1]) TX_DATA[7:0] <= `DLY 8'h1c; // K28.0(R)
if(gen_sp_data_r[1]) TX_DATA[7:0] <= `DLY 8'h4a; // D10.2(SP data)
if(gen_spa_data_r[1]) TX_DATA[7:0] <= `DLY 8'h2c; // D12.1(SPA data)
if(gen_v_r[1]) TX_DATA[7:0] <= `DLY 8'he8; // D8.7(Ver data)
end
// Generate control signal for LSB.
always @(posedge USER_CLK)
begin
if(RESET)
TX_CHAR_IS_K[0] <= `DLY 1'b0;
else
TX_CHAR_IS_K[0] <= `DLY !( tx_pe_data_v_r & !gen_pad_r |
gen_sp_data_r[1] |
gen_spa_data_r[1] |
gen_v_r[1]
);
end
endmodule
|
module sky130_fd_sc_lp__clkdlybuf4s15 (
X,
A
);
// Module ports
output X;
input A;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire buf0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X, A );
buf buf1 (X , buf0_out_X );
endmodule
|
module sky130_fd_sc_hs__sdfsbp_2 (
CLK ,
D ,
Q ,
Q_N ,
SCD ,
SCE ,
SET_B,
VPWR ,
VGND
);
input CLK ;
input D ;
output Q ;
output Q_N ;
input SCD ;
input SCE ;
input SET_B;
input VPWR ;
input VGND ;
sky130_fd_sc_hs__sdfsbp base (
.CLK(CLK),
.D(D),
.Q(Q),
.Q_N(Q_N),
.SCD(SCD),
.SCE(SCE),
.SET_B(SET_B),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
|
module sky130_fd_sc_hs__sdfsbp_2 (
CLK ,
D ,
Q ,
Q_N ,
SCD ,
SCE ,
SET_B
);
input CLK ;
input D ;
output Q ;
output Q_N ;
input SCD ;
input SCE ;
input SET_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__sdfsbp base (
.CLK(CLK),
.D(D),
.Q(Q),
.Q_N(Q_N),
.SCD(SCD),
.SCE(SCE),
.SET_B(SET_B)
);
endmodule
|
module ad_iqcor #(
// select i/q if disabled
parameter Q_OR_I_N = 0,
parameter SCALE_ONLY = 0,
parameter DISABLE = 0) (
// data interface
input clk,
input valid,
input [15:0] data_in,
input [15:0] data_iq,
output valid_out,
output [15:0] data_out,
// control interface
input iqcor_enable,
input [15:0] iqcor_coeff_1,
input [15:0] iqcor_coeff_2);
// internal registers
reg p1_valid = 'd0;
reg [33:0] p1_data_p = 'd0;
reg valid_int = 'd0;
reg [15:0] data_int = 'd0;
reg [15:0] iqcor_coeff_1_r = 'd0;
reg [15:0] iqcor_coeff_2_r = 'd0;
// internal signals
wire [15:0] data_i_s;
wire [15:0] data_q_s;
wire [33:0] p1_data_p_i_s;
wire p1_valid_s;
wire [15:0] p1_data_i_s;
wire [33:0] p1_data_p_q_s;
wire [15:0] p1_data_q_s;
wire [15:0] p1_data_i_int;
wire [15:0] p1_data_q_int;
// data-path disable
generate
if (DISABLE == 1) begin
assign valid_out = valid;
assign data_out = data_in;
end else begin
assign valid_out = valid_int;
assign data_out = data_int;
end
endgenerate
// swap i & q
assign data_i_s = (Q_OR_I_N == 1 && SCALE_ONLY == 1'b0) ? data_iq : data_in;
assign data_q_s = (Q_OR_I_N == 1) ? data_in : data_iq;
// coefficients are flopped to remove warnings from vivado
always @(posedge clk) begin
iqcor_coeff_1_r <= iqcor_coeff_1;
iqcor_coeff_2_r <= iqcor_coeff_2;
end
// scaling functions - i
ad_mul #(.DELAY_DATA_WIDTH(17)) i_mul_i (
.clk (clk),
.data_a ({data_i_s[15], data_i_s}),
.data_b ({iqcor_coeff_1_r[15], iqcor_coeff_1_r}),
.data_p (p1_data_p_i_s),
.ddata_in ({valid, data_i_s}),
.ddata_out ({p1_valid_s, p1_data_i_s}));
generate
if (SCALE_ONLY == 0) begin
// scaling functions - q
ad_mul #(.DELAY_DATA_WIDTH(16)) i_mul_q (
.clk (clk),
.data_a ({data_q_s[15], data_q_s}),
.data_b ({iqcor_coeff_2_r[15], iqcor_coeff_2_r}),
.data_p (p1_data_p_q_s),
.ddata_in (data_q_s),
.ddata_out (p1_data_q_s));
// sum
end else begin
assign p1_data_p_q_s = 34'h0;
assign p1_data_q_s = 16'h0;
end
endgenerate
generate
if (Q_OR_I_N == 1 && SCALE_ONLY == 0) begin
reg [15:0] p1_data_q = 'd0;
always @(posedge clk) begin
p1_data_q <= p1_data_q_s;
end
assign p1_data_i_int = 16'h0;
assign p1_data_q_int = p1_data_q;
// sum
end else begin
reg [15:0] p1_data_i = 'd0;
always @(posedge clk) begin
p1_data_i <= p1_data_i_s;
end
assign p1_data_i_int = p1_data_i;
assign p1_data_q_int = 16'h0;
end
endgenerate
always @(posedge clk) begin
p1_valid <= p1_valid_s;
p1_data_p <= p1_data_p_i_s + p1_data_p_q_s;
end
// output registers
always @(posedge clk) begin
valid_int <= p1_valid;
if (iqcor_enable == 1'b1) begin
data_int <= p1_data_p[29:14];
end else if (Q_OR_I_N == 1 && SCALE_ONLY == 0) begin
data_int <= p1_data_q_int;
end else begin
data_int <= p1_data_i_int;
end
end
endmodule
|
module hi_flite(
pck0, ck_1356meg, ck_1356megb,
pwr_lo, pwr_hi, pwr_oe1, pwr_oe2, pwr_oe3, pwr_oe4,
adc_d, adc_clk,
ssp_frame, ssp_din, ssp_dout, ssp_clk,
cross_hi, cross_lo,
dbg,
mod_type // used
);
input pck0, ck_1356meg, ck_1356megb;
output pwr_lo, pwr_hi, pwr_oe1, pwr_oe2, pwr_oe3, pwr_oe4;
input [7:0] adc_d;
output adc_clk;
input ssp_dout;
output ssp_frame, ssp_din, ssp_clk;
input cross_hi, cross_lo;
output dbg;
input [2:0] mod_type; // used.
assign dbg=0;
wire power= mod_type[2];
wire speed= mod_type[1];
wire disabl= mod_type[0];
// Most off, oe4 for modulation;
// Trying reader emulation (would presumably just require switching power on, but I am not sure)
//;// 1'b0;
assign pwr_lo = 1'b0;
//512x64/fc -wait before ts0, 32768 ticks
//tslot: 256*64/fc
assign adc_clk = ck_1356meg;
///heuristic values for initial thresholds. seem to work OK
`define imin 70//(13'd256)
`define imax 180//(-13'd256)
`define ithrmin 91//-13'd8
`define ithrmax 160// 13'd8
`define min_bitdelay_212 8
//minimum values and corresponding thresholds
reg [8:0] curmin=`imin;
reg [8:0] curminthres=`ithrmin;
reg [8:0] curmaxthres=`ithrmax;
reg [8:0] curmax=`imax;
//signal state, 1-not modulated, 0 -modulated
reg after_hysteresis = 1'b1;
//state machine for envelope tracking
reg [1:0] state=1'd0;
//lower edge detected, trying to detect first bit of SYNC (b24d, 1011001001001101)
reg try_sync=1'b0;
//detected first sync bit, phase frozen
reg did_sync=0;
`define bithalf_212 32 //half-bit length for 212 kbit
`define bitmlen_212 63 //bit transition edge
`define bithalf_424 16 //half-bit length for 212 kbit
`define bitmlen_424 31 //bit transition edge
wire [7:0]bithalf= speed ? `bithalf_424 : `bithalf_212;
wire [7:0]bitmlen= speed ? `bitmlen_424 : `bitmlen_212;
//ssp clock and current values
reg ssp_clk;
reg ssp_frame;
reg curbit=1'b0;
reg [7:0] fccount=8'd0; // in-bit tick counter. Counts carrier cycles from the first lower edge detected, reset on every manchester bit detected
reg [7:0] tsinceedge=8'd0;// ticks from last edge, desync if the valye is too large
reg zero=1'b0; // Manchester first halfbit low second high corresponds to this value. It has been known to change. SYNC is used to set it
//ssp counter for transfer and framing
reg [8:0] ssp_cnt=9'd0;
always @(posedge adc_clk)
ssp_cnt <= (ssp_cnt + 1);
//maybe change it so that ARM sends preamble as well.
//then: ready bits sent to ARM, 8 bits sent from ARM (all ones), then preamble (all zeros, presumably) - which starts modulation
always @(negedge adc_clk)
begin
//count fc/64 - transfer bits to ARM at the rate they are received
if( ((~speed) && (ssp_cnt[5:0] == 6'b000000)) || (speed &&(ssp_cnt[4:0] == 5'b00000)))
begin
ssp_clk <= 1'b1;
// if(mod_type[2])
// begin
// ssp_din<=outp[0];//after_hysteresis;
//outp<={1'b0,outp[7:1]};
// end
// else
ssp_din <= curbit;
//sample ssp_dout
end
if( ( (~speed) && (ssp_cnt[5:0] == 6'b100000)) ||(speed && ssp_cnt[4:0] == 5'b10000))
ssp_clk <= 1'b0;
//create frame pulses. TBH, I still don't know what they do exactly, but they are crucial for ARM->FPGA transfer. If the frame is in the beginning of the byte, transfer slows to a crawl for some reason
// took me a day to figure THAT out.
if(( (~speed) && (ssp_cnt[8:0] == 9'd31))||(speed && ssp_cnt[7:0] == 8'd15))
begin
ssp_frame <= 1'b1;
end
if(( (~speed) && (ssp_cnt[8:0] == 9'b1011111))||(speed &&ssp_cnt[7:0] == 8'b101111) )
begin
ssp_frame <= 1'b0;
end
end
//send current bit (detected in SNIFF mode or the one being modulated in MOD mode, 0 otherwise)
reg ssp_din;//= outp[0];
//previous signal value, mostly to detect SYNC
reg prv =1'b1;
reg[7:0] mid=8'd128; //for simple error correction in mod/demod detection, use maximum of modded/demodded in given interval. Maybe 1 bit is extra? but better safe than sorry.
// set TAGSIM__MODULATE on ARM if we want to write... (frame would get lost if done mid-frame...)
// start sending over 1s on ssp->arm when we start sending preamble
reg counting_desync=1'b0; // are we counting bits since last frame?
reg sending=1'b0; // are we actively modulating?
reg [11:0] bit_counts=12'd0;///for timeslots... only support ts=0 for now, at 212 speed -512 fullbits from end of frame. One hopes. might remove those?
//reg [2:0]old_mod;
//always @(mod_type) //when moving from modulate_mode
//begin
//if (mod_type[2]==1&&old_mod[2]==0)
// bit_counts=0;
//old_mod=mod_type;
//end
//we need some way to flush bit_counts triggers on mod_type changes don't compile
reg dlay;
always @(negedge adc_clk) //every data ping?
begin
//envelope follow code...
////////////
//move the counter to the outside...
// if (adc_d>=curminthres||try_sync)
if(fccount==bitmlen)
begin
if((~try_sync)&&(adc_d<curminthres)&&disabl )
begin
fccount<=1;
end
else
begin
fccount<=0;
end
// if (counting_desync)
// begin
dlay<=ssp_dout;
if(bit_counts>768) // should be over ts0 now, without ARM interference... stop counting...
begin
bit_counts<=0;
// counting_desync<=0;
end
else
if((power))
bit_counts<=0;
else
bit_counts<=bit_counts+1;
// end
end
else
begin
if((~try_sync)&&(adc_d<curminthres) &&disabl)
begin
fccount<=1;
end
else
begin
fccount<=fccount+1;
end
end
if (adc_d>curmaxthres) //rising edge
begin
case (state)
0: begin
curmax <= adc_d>`imax? adc_d :`imax;
state <= 2;
end
1: begin
curminthres <= ( (curmin>>1)+(curmin>>2)+(curmin>>4)+(curmax>>3)+(curmax>>4)); //threshold: 0.1875 max + 0.8125 min
curmaxthres <= ( (curmax>>1)+(curmax>>2)+(curmax>>4)+(curmin>>3)+(curmin>>4));
curmax <= adc_d>155? adc_d :155; // to hopefully prevent overflow from spikes going up to 255
state <= 2;
end
2: begin
if (adc_d>curmax)
curmax <= adc_d;
end
default:
begin
end
endcase
after_hysteresis <=1'b1;
if(try_sync)
tsinceedge<=0;
end
else if (adc_d<curminthres) //falling edge
begin
case (state)
0: begin
curmin <=adc_d<`imin? adc_d :`imin;
state <=1;
end
1: begin
if (adc_d<curmin)
curmin <= adc_d;
end
2: begin
curminthres <= ( (curmin>>1)+(curmin>>2)+(curmin>>4)+(curmax>>3)+(curmax>>4));
curmaxthres <= ( (curmax>>1)+(curmax>>2)+(curmax>>4)+(curmin>>3)+(curmin>>4));
curmin <=adc_d<`imin? adc_d :`imin;
state <=1;
end
default:
begin
end
endcase
after_hysteresis <=0;
if (~try_sync ) //begin modulation, lower edge...
begin
try_sync <=1;
//counting_desync<=1'b0;
fccount <= 1;
did_sync<=0;
curbit<=0;
mid <=8'd127;
tsinceedge<=0;
prv <=1;
end
else
begin
tsinceedge<=0;
end
end
else //stable state, low or high
begin
curminthres <= ( (curmin>>1)+(curmin>>2)+(curmin>>4)+(curmax>>3)+(curmax>>4));
curmaxthres <= ( (curmax>>1)+(curmax>>2)+(curmax>>4)+(curmin>>3)+(curmin>>4));
state <=0;
if (try_sync )
begin
if (tsinceedge>=(128))
begin
//we might need to start counting... assuming ARM wants to reply to the frame.
// counting_desync<=1'b1;
bit_counts<=1;// i think? 128 is about 2 bits passed... but 1 also works
try_sync<=0;
did_sync<=0;//desync
curmin <=`imin; //reset envelope
curmax <=`imax;
curminthres <=`ithrmin;
curmaxthres <=`ithrmax;
prv <=1;
tsinceedge <=0;
after_hysteresis <=1'b1;
curbit <=0;
mid <=8'd128;
end
else
tsinceedge<=(tsinceedge+1);
end
end
if (try_sync && tsinceedge<128)
begin
//detect bits in their middle ssp sampling is in sync, so it would sample all bits in order
if (fccount==bithalf)
begin
if ((~did_sync) && ((prv==1&&(mid>128))||(prv==0&&(mid<=128))))
begin
//sync the Zero, and set curbit roperly
did_sync <=1'b1;
zero <= ~prv;// 1-prv
curbit <=1;
end
else
curbit <= (mid>128) ? (~zero):zero;
prv <=(mid>128) ?1:0;
if(adc_d>curmaxthres)
mid <=8'd129;
else if (adc_d<curminthres)
mid <=8'd127;
else
begin
if (after_hysteresis)
begin
mid <=8'd129;
end
else
begin
mid<=8'd127;
end
end
end
else
begin
if (fccount==bitmlen)
begin
// fccount <=0;
prv <=(mid>128)?1:0;
mid <=128;
end
else
begin
// minimum-maximum calc
if(adc_d>curmaxthres)
mid <=mid+1;
else if (adc_d<curminthres)
mid <=mid-1;
else
begin
if (after_hysteresis)
begin
mid <=mid+1;
end
else
begin
mid<=mid-1;
end
end
end
end
end
else
begin
end
sending <=0;
end
//put modulation here to maintain the correct clock. Seems that some readers are sensitive to that
reg pwr_hi;
reg pwr_oe1;
reg pwr_oe2;
reg pwr_oe3;
reg pwr_oe4;
wire mod=((fccount>=bithalf)^dlay)&(~disabl);
always @(ck_1356megb or ssp_dout or power or disabl or mod)
begin
if (power)
begin
pwr_hi <= ck_1356megb;
pwr_oe1 <= 1'b0;//mod;
pwr_oe2 <= 1'b0;//mod;
pwr_oe3 <= 1'b0;//mod;
pwr_oe4 <= mod;//1'b0;
end
else
begin
pwr_hi <= 1'b0;
pwr_oe1 <= 1'b0;
pwr_oe2 <= 1'b0;
pwr_oe3 <= 1'b0;
pwr_oe4 <= mod;
end
end
//assign pwr_oe4 = 1'b0;// mod_sig_coil & (modulate_mode)&sending & (~mod_type[2]);
//try shallow mod for reader?
//assign pwr_hi= (mod_type[2]) & ck_1356megb;
//assign pwr_oe1= 1'b0; //mod_sig_coil & (modulate_mode)&sending & (mod_type[2]);
//assign pwr_oe2 = 1'b0;// mod_sig_coil & (modulate_mode)&sending & (mod_type[2]);
//assign pwr_oe3 = 1'b0; //mod_sig_coil & (modulate_mode)&sending & (mod_type[2]);
endmodule
|
module hps_sdram (
input wire pll_ref_clk, // pll_ref_clk.clk
input wire global_reset_n, // global_reset.reset_n
input wire soft_reset_n, // soft_reset.reset_n
output wire [14:0] mem_a, // memory.mem_a
output wire [2:0] mem_ba, // .mem_ba
output wire [0:0] mem_ck, // .mem_ck
output wire [0:0] mem_ck_n, // .mem_ck_n
output wire [0:0] mem_cke, // .mem_cke
output wire [0:0] mem_cs_n, // .mem_cs_n
output wire [3:0] mem_dm, // .mem_dm
output wire [0:0] mem_ras_n, // .mem_ras_n
output wire [0:0] mem_cas_n, // .mem_cas_n
output wire [0:0] mem_we_n, // .mem_we_n
output wire mem_reset_n, // .mem_reset_n
inout wire [31:0] mem_dq, // .mem_dq
inout wire [3:0] mem_dqs, // .mem_dqs
inout wire [3:0] mem_dqs_n, // .mem_dqs_n
output wire [0:0] mem_odt, // .mem_odt
input wire oct_rzqin // oct.rzqin
);
wire pll_afi_clk_clk; // pll:afi_clk -> [c0:afi_clk, p0:afi_clk]
wire pll_afi_half_clk_clk; // pll:afi_half_clk -> [c0:afi_half_clk, p0:afi_half_clk]
wire [4:0] p0_afi_afi_rlat; // p0:afi_rlat -> c0:afi_rlat
wire p0_afi_afi_cal_success; // p0:afi_cal_success -> c0:afi_cal_success
wire [79:0] p0_afi_afi_rdata; // p0:afi_rdata -> c0:afi_rdata
wire [3:0] p0_afi_afi_wlat; // p0:afi_wlat -> c0:afi_wlat
wire p0_afi_afi_cal_fail; // p0:afi_cal_fail -> c0:afi_cal_fail
wire [0:0] p0_afi_afi_rdata_valid; // p0:afi_rdata_valid -> c0:afi_rdata_valid
wire p0_afi_reset_reset; // p0:afi_reset_n -> c0:afi_reset_n
wire [4:0] c0_afi_afi_rdata_en_full; // c0:afi_rdata_en_full -> p0:afi_rdata_en_full
wire [0:0] c0_afi_afi_rst_n; // c0:afi_rst_n -> p0:afi_rst_n
wire [4:0] c0_afi_afi_dqs_burst; // c0:afi_dqs_burst -> p0:afi_dqs_burst
wire [19:0] c0_afi_afi_addr; // c0:afi_addr -> p0:afi_addr
wire [9:0] c0_afi_afi_dm; // c0:afi_dm -> p0:afi_dm
wire [0:0] c0_afi_afi_mem_clk_disable; // c0:afi_mem_clk_disable -> p0:afi_mem_clk_disable
wire [0:0] c0_afi_afi_we_n; // c0:afi_we_n -> p0:afi_we_n
wire [4:0] c0_afi_afi_rdata_en; // c0:afi_rdata_en -> p0:afi_rdata_en
wire [1:0] c0_afi_afi_odt; // c0:afi_odt -> p0:afi_odt
wire [0:0] c0_afi_afi_ras_n; // c0:afi_ras_n -> p0:afi_ras_n
wire [1:0] c0_afi_afi_cke; // c0:afi_cke -> p0:afi_cke
wire [4:0] c0_afi_afi_wdata_valid; // c0:afi_wdata_valid -> p0:afi_wdata_valid
wire [79:0] c0_afi_afi_wdata; // c0:afi_wdata -> p0:afi_wdata
wire [2:0] c0_afi_afi_ba; // c0:afi_ba -> p0:afi_ba
wire [0:0] c0_afi_afi_cas_n; // c0:afi_cas_n -> p0:afi_cas_n
wire [1:0] c0_afi_afi_cs_n; // c0:afi_cs_n -> p0:afi_cs_n
wire [7:0] c0_hard_phy_cfg_cfg_tmrd; // c0:cfg_tmrd -> p0:cfg_tmrd
wire [23:0] c0_hard_phy_cfg_cfg_dramconfig; // c0:cfg_dramconfig -> p0:cfg_dramconfig
wire [7:0] c0_hard_phy_cfg_cfg_rowaddrwidth; // c0:cfg_rowaddrwidth -> p0:cfg_rowaddrwidth
wire [7:0] c0_hard_phy_cfg_cfg_devicewidth; // c0:cfg_devicewidth -> p0:cfg_devicewidth
wire [15:0] c0_hard_phy_cfg_cfg_trefi; // c0:cfg_trefi -> p0:cfg_trefi
wire [7:0] c0_hard_phy_cfg_cfg_tcl; // c0:cfg_tcl -> p0:cfg_tcl
wire [7:0] c0_hard_phy_cfg_cfg_csaddrwidth; // c0:cfg_csaddrwidth -> p0:cfg_csaddrwidth
wire [7:0] c0_hard_phy_cfg_cfg_coladdrwidth; // c0:cfg_coladdrwidth -> p0:cfg_coladdrwidth
wire [7:0] c0_hard_phy_cfg_cfg_trfc; // c0:cfg_trfc -> p0:cfg_trfc
wire [7:0] c0_hard_phy_cfg_cfg_addlat; // c0:cfg_addlat -> p0:cfg_addlat
wire [7:0] c0_hard_phy_cfg_cfg_bankaddrwidth; // c0:cfg_bankaddrwidth -> p0:cfg_bankaddrwidth
wire [7:0] c0_hard_phy_cfg_cfg_interfacewidth; // c0:cfg_interfacewidth -> p0:cfg_interfacewidth
wire [7:0] c0_hard_phy_cfg_cfg_twr; // c0:cfg_twr -> p0:cfg_twr
wire [7:0] c0_hard_phy_cfg_cfg_caswrlat; // c0:cfg_caswrlat -> p0:cfg_caswrlat
wire p0_ctl_clk_clk; // p0:ctl_clk -> c0:ctl_clk
wire p0_ctl_reset_reset; // p0:ctl_reset_n -> c0:ctl_reset_n
wire p0_io_int_io_intaficalfail; // p0:io_intaficalfail -> c0:io_intaficalfail
wire p0_io_int_io_intaficalsuccess; // p0:io_intaficalsuccess -> c0:io_intaficalsuccess
wire [15:0] oct_oct_sharing_parallelterminationcontrol; // oct:parallelterminationcontrol -> p0:parallelterminationcontrol
wire [15:0] oct_oct_sharing_seriesterminationcontrol; // oct:seriesterminationcontrol -> p0:seriesterminationcontrol
wire pll_pll_sharing_pll_write_clk; // pll:pll_write_clk -> p0:pll_write_clk
wire pll_pll_sharing_pll_avl_clk; // pll:pll_avl_clk -> p0:pll_avl_clk
wire pll_pll_sharing_pll_write_clk_pre_phy_clk; // pll:pll_write_clk_pre_phy_clk -> p0:pll_write_clk_pre_phy_clk
wire pll_pll_sharing_pll_addr_cmd_clk; // pll:pll_addr_cmd_clk -> p0:pll_addr_cmd_clk
wire pll_pll_sharing_pll_config_clk; // pll:pll_config_clk -> p0:pll_config_clk
wire pll_pll_sharing_pll_avl_phy_clk; // pll:pll_avl_phy_clk -> p0:pll_avl_phy_clk
wire pll_pll_sharing_afi_phy_clk; // pll:afi_phy_clk -> p0:afi_phy_clk
wire pll_pll_sharing_pll_mem_clk; // pll:pll_mem_clk -> p0:pll_mem_clk
wire pll_pll_sharing_pll_locked; // pll:pll_locked -> p0:pll_locked
wire pll_pll_sharing_pll_mem_phy_clk; // pll:pll_mem_phy_clk -> p0:pll_mem_phy_clk
wire p0_dll_clk_clk; // p0:dll_clk -> dll:clk
wire p0_dll_sharing_dll_pll_locked; // p0:dll_pll_locked -> dll:dll_pll_locked
wire [6:0] dll_dll_sharing_dll_delayctrl; // dll:dll_delayctrl -> p0:dll_delayctrl
hps_sdram_pll pll (
.global_reset_n (global_reset_n), // global_reset.reset_n
.pll_ref_clk (pll_ref_clk), // pll_ref_clk.clk
.afi_clk (pll_afi_clk_clk), // afi_clk.clk
.afi_half_clk (pll_afi_half_clk_clk), // afi_half_clk.clk
.pll_mem_clk (pll_pll_sharing_pll_mem_clk), // pll_sharing.pll_mem_clk
.pll_write_clk (pll_pll_sharing_pll_write_clk), // .pll_write_clk
.pll_locked (pll_pll_sharing_pll_locked), // .pll_locked
.pll_write_clk_pre_phy_clk (pll_pll_sharing_pll_write_clk_pre_phy_clk), // .pll_write_clk_pre_phy_clk
.pll_addr_cmd_clk (pll_pll_sharing_pll_addr_cmd_clk), // .pll_addr_cmd_clk
.pll_avl_clk (pll_pll_sharing_pll_avl_clk), // .pll_avl_clk
.pll_config_clk (pll_pll_sharing_pll_config_clk), // .pll_config_clk
.pll_mem_phy_clk (pll_pll_sharing_pll_mem_phy_clk), // .pll_mem_phy_clk
.afi_phy_clk (pll_pll_sharing_afi_phy_clk), // .afi_phy_clk
.pll_avl_phy_clk (pll_pll_sharing_pll_avl_phy_clk) // .pll_avl_phy_clk
);
hps_sdram_p0 p0 (
.global_reset_n (global_reset_n), // global_reset.reset_n
.soft_reset_n (soft_reset_n), // soft_reset.reset_n
.afi_reset_n (p0_afi_reset_reset), // afi_reset.reset_n
.afi_reset_export_n (), // afi_reset_export.reset_n
.ctl_reset_n (p0_ctl_reset_reset), // ctl_reset.reset_n
.afi_clk (pll_afi_clk_clk), // afi_clk.clk
.afi_half_clk (pll_afi_half_clk_clk), // afi_half_clk.clk
.ctl_clk (p0_ctl_clk_clk), // ctl_clk.clk
.avl_clk (), // avl_clk.clk
.avl_reset_n (), // avl_reset.reset_n
.scc_clk (), // scc_clk.clk
.scc_reset_n (), // scc_reset.reset_n
.avl_address (), // avl.address
.avl_write (), // .write
.avl_writedata (), // .writedata
.avl_read (), // .read
.avl_readdata (), // .readdata
.avl_waitrequest (), // .waitrequest
.dll_clk (p0_dll_clk_clk), // dll_clk.clk
.afi_addr (c0_afi_afi_addr), // afi.afi_addr
.afi_ba (c0_afi_afi_ba), // .afi_ba
.afi_cke (c0_afi_afi_cke), // .afi_cke
.afi_cs_n (c0_afi_afi_cs_n), // .afi_cs_n
.afi_ras_n (c0_afi_afi_ras_n), // .afi_ras_n
.afi_we_n (c0_afi_afi_we_n), // .afi_we_n
.afi_cas_n (c0_afi_afi_cas_n), // .afi_cas_n
.afi_rst_n (c0_afi_afi_rst_n), // .afi_rst_n
.afi_odt (c0_afi_afi_odt), // .afi_odt
.afi_dqs_burst (c0_afi_afi_dqs_burst), // .afi_dqs_burst
.afi_wdata_valid (c0_afi_afi_wdata_valid), // .afi_wdata_valid
.afi_wdata (c0_afi_afi_wdata), // .afi_wdata
.afi_dm (c0_afi_afi_dm), // .afi_dm
.afi_rdata (p0_afi_afi_rdata), // .afi_rdata
.afi_rdata_en (c0_afi_afi_rdata_en), // .afi_rdata_en
.afi_rdata_en_full (c0_afi_afi_rdata_en_full), // .afi_rdata_en_full
.afi_rdata_valid (p0_afi_afi_rdata_valid), // .afi_rdata_valid
.afi_wlat (p0_afi_afi_wlat), // .afi_wlat
.afi_rlat (p0_afi_afi_rlat), // .afi_rlat
.afi_cal_success (p0_afi_afi_cal_success), // .afi_cal_success
.afi_cal_fail (p0_afi_afi_cal_fail), // .afi_cal_fail
.scc_data (), // scc.scc_data
.scc_dqs_ena (), // .scc_dqs_ena
.scc_dqs_io_ena (), // .scc_dqs_io_ena
.scc_dq_ena (), // .scc_dq_ena
.scc_dm_ena (), // .scc_dm_ena
.capture_strobe_tracking (), // .capture_strobe_tracking
.scc_upd (), // .scc_upd
.cfg_addlat (c0_hard_phy_cfg_cfg_addlat), // hard_phy_cfg.cfg_addlat
.cfg_bankaddrwidth (c0_hard_phy_cfg_cfg_bankaddrwidth), // .cfg_bankaddrwidth
.cfg_caswrlat (c0_hard_phy_cfg_cfg_caswrlat), // .cfg_caswrlat
.cfg_coladdrwidth (c0_hard_phy_cfg_cfg_coladdrwidth), // .cfg_coladdrwidth
.cfg_csaddrwidth (c0_hard_phy_cfg_cfg_csaddrwidth), // .cfg_csaddrwidth
.cfg_devicewidth (c0_hard_phy_cfg_cfg_devicewidth), // .cfg_devicewidth
.cfg_dramconfig (c0_hard_phy_cfg_cfg_dramconfig), // .cfg_dramconfig
.cfg_interfacewidth (c0_hard_phy_cfg_cfg_interfacewidth), // .cfg_interfacewidth
.cfg_rowaddrwidth (c0_hard_phy_cfg_cfg_rowaddrwidth), // .cfg_rowaddrwidth
.cfg_tcl (c0_hard_phy_cfg_cfg_tcl), // .cfg_tcl
.cfg_tmrd (c0_hard_phy_cfg_cfg_tmrd), // .cfg_tmrd
.cfg_trefi (c0_hard_phy_cfg_cfg_trefi), // .cfg_trefi
.cfg_trfc (c0_hard_phy_cfg_cfg_trfc), // .cfg_trfc
.cfg_twr (c0_hard_phy_cfg_cfg_twr), // .cfg_twr
.afi_mem_clk_disable (c0_afi_afi_mem_clk_disable), // afi_mem_clk_disable.afi_mem_clk_disable
.pll_mem_clk (pll_pll_sharing_pll_mem_clk), // pll_sharing.pll_mem_clk
.pll_write_clk (pll_pll_sharing_pll_write_clk), // .pll_write_clk
.pll_locked (pll_pll_sharing_pll_locked), // .pll_locked
.pll_write_clk_pre_phy_clk (pll_pll_sharing_pll_write_clk_pre_phy_clk), // .pll_write_clk_pre_phy_clk
.pll_addr_cmd_clk (pll_pll_sharing_pll_addr_cmd_clk), // .pll_addr_cmd_clk
.pll_avl_clk (pll_pll_sharing_pll_avl_clk), // .pll_avl_clk
.pll_config_clk (pll_pll_sharing_pll_config_clk), // .pll_config_clk
.pll_mem_phy_clk (pll_pll_sharing_pll_mem_phy_clk), // .pll_mem_phy_clk
.afi_phy_clk (pll_pll_sharing_afi_phy_clk), // .afi_phy_clk
.pll_avl_phy_clk (pll_pll_sharing_pll_avl_phy_clk), // .pll_avl_phy_clk
.dll_pll_locked (p0_dll_sharing_dll_pll_locked), // dll_sharing.dll_pll_locked
.dll_delayctrl (dll_dll_sharing_dll_delayctrl), // .dll_delayctrl
.seriesterminationcontrol (oct_oct_sharing_seriesterminationcontrol), // oct_sharing.seriesterminationcontrol
.parallelterminationcontrol (oct_oct_sharing_parallelterminationcontrol), // .parallelterminationcontrol
.mem_a (mem_a), // memory.mem_a
.mem_ba (mem_ba), // .mem_ba
.mem_ck (mem_ck), // .mem_ck
.mem_ck_n (mem_ck_n), // .mem_ck_n
.mem_cke (mem_cke), // .mem_cke
.mem_cs_n (mem_cs_n), // .mem_cs_n
.mem_dm (mem_dm), // .mem_dm
.mem_ras_n (mem_ras_n), // .mem_ras_n
.mem_cas_n (mem_cas_n), // .mem_cas_n
.mem_we_n (mem_we_n), // .mem_we_n
.mem_reset_n (mem_reset_n), // .mem_reset_n
.mem_dq (mem_dq), // .mem_dq
.mem_dqs (mem_dqs), // .mem_dqs
.mem_dqs_n (mem_dqs_n), // .mem_dqs_n
.mem_odt (mem_odt), // .mem_odt
.io_intaficalfail (p0_io_int_io_intaficalfail), // io_int.io_intaficalfail
.io_intaficalsuccess (p0_io_int_io_intaficalsuccess), // .io_intaficalsuccess
.csr_soft_reset_req (1'b0), // (terminated)
.io_intaddrdout (64'b0000000000000000000000000000000000000000000000000000000000000000), // (terminated)
.io_intbadout (12'b000000000000), // (terminated)
.io_intcasndout (4'b0000), // (terminated)
.io_intckdout (4'b0000), // (terminated)
.io_intckedout (8'b00000000), // (terminated)
.io_intckndout (4'b0000), // (terminated)
.io_intcsndout (8'b00000000), // (terminated)
.io_intdmdout (20'b00000000000000000000), // (terminated)
.io_intdqdin (), // (terminated)
.io_intdqdout (180'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000), // (terminated)
.io_intdqoe (90'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000), // (terminated)
.io_intdqsbdout (20'b00000000000000000000), // (terminated)
.io_intdqsboe (10'b0000000000), // (terminated)
.io_intdqsdout (20'b00000000000000000000), // (terminated)
.io_intdqslogicdqsena (10'b0000000000), // (terminated)
.io_intdqslogicfiforeset (5'b00000), // (terminated)
.io_intdqslogicincrdataen (10'b0000000000), // (terminated)
.io_intdqslogicincwrptr (10'b0000000000), // (terminated)
.io_intdqslogicoct (10'b0000000000), // (terminated)
.io_intdqslogicrdatavalid (), // (terminated)
.io_intdqslogicreadlatency (25'b0000000000000000000000000), // (terminated)
.io_intdqsoe (10'b0000000000), // (terminated)
.io_intodtdout (8'b00000000), // (terminated)
.io_intrasndout (4'b0000), // (terminated)
.io_intresetndout (4'b0000), // (terminated)
.io_intwendout (4'b0000), // (terminated)
.io_intafirlat (), // (terminated)
.io_intafiwlat () // (terminated)
);
altera_mem_if_hhp_qseq_synth_top #(
.MEM_IF_DM_WIDTH (4),
.MEM_IF_DQS_WIDTH (4),
.MEM_IF_CS_WIDTH (1),
.MEM_IF_DQ_WIDTH (32)
) seq (
);
altera_mem_if_hard_memory_controller_top_cyclonev #(
.MEM_IF_DQS_WIDTH (4),
.MEM_IF_CS_WIDTH (1),
.MEM_IF_CHIP_BITS (1),
.MEM_IF_CLK_PAIR_COUNT (1),
.CSR_ADDR_WIDTH (10),
.CSR_DATA_WIDTH (8),
.CSR_BE_WIDTH (1),
.AVL_ADDR_WIDTH (27),
.AVL_DATA_WIDTH (64),
.AVL_SIZE_WIDTH (3),
.AVL_DATA_WIDTH_PORT_0 (1),
.AVL_ADDR_WIDTH_PORT_0 (1),
.AVL_NUM_SYMBOLS_PORT_0 (1),
.LSB_WFIFO_PORT_0 (5),
.MSB_WFIFO_PORT_0 (5),
.LSB_RFIFO_PORT_0 (5),
.MSB_RFIFO_PORT_0 (5),
.AVL_DATA_WIDTH_PORT_1 (1),
.AVL_ADDR_WIDTH_PORT_1 (1),
.AVL_NUM_SYMBOLS_PORT_1 (1),
.LSB_WFIFO_PORT_1 (5),
.MSB_WFIFO_PORT_1 (5),
.LSB_RFIFO_PORT_1 (5),
.MSB_RFIFO_PORT_1 (5),
.AVL_DATA_WIDTH_PORT_2 (1),
.AVL_ADDR_WIDTH_PORT_2 (1),
.AVL_NUM_SYMBOLS_PORT_2 (1),
.LSB_WFIFO_PORT_2 (5),
.MSB_WFIFO_PORT_2 (5),
.LSB_RFIFO_PORT_2 (5),
.MSB_RFIFO_PORT_2 (5),
.AVL_DATA_WIDTH_PORT_3 (1),
.AVL_ADDR_WIDTH_PORT_3 (1),
.AVL_NUM_SYMBOLS_PORT_3 (1),
.LSB_WFIFO_PORT_3 (5),
.MSB_WFIFO_PORT_3 (5),
.LSB_RFIFO_PORT_3 (5),
.MSB_RFIFO_PORT_3 (5),
.AVL_DATA_WIDTH_PORT_4 (1),
.AVL_ADDR_WIDTH_PORT_4 (1),
.AVL_NUM_SYMBOLS_PORT_4 (1),
.LSB_WFIFO_PORT_4 (5),
.MSB_WFIFO_PORT_4 (5),
.LSB_RFIFO_PORT_4 (5),
.MSB_RFIFO_PORT_4 (5),
.AVL_DATA_WIDTH_PORT_5 (1),
.AVL_ADDR_WIDTH_PORT_5 (1),
.AVL_NUM_SYMBOLS_PORT_5 (1),
.LSB_WFIFO_PORT_5 (5),
.MSB_WFIFO_PORT_5 (5),
.LSB_RFIFO_PORT_5 (5),
.MSB_RFIFO_PORT_5 (5),
.ENUM_ATTR_COUNTER_ONE_RESET ("DISABLED"),
.ENUM_ATTR_COUNTER_ZERO_RESET ("DISABLED"),
.ENUM_ATTR_STATIC_CONFIG_VALID ("DISABLED"),
.ENUM_AUTO_PCH_ENABLE_0 ("DISABLED"),
.ENUM_AUTO_PCH_ENABLE_1 ("DISABLED"),
.ENUM_AUTO_PCH_ENABLE_2 ("DISABLED"),
.ENUM_AUTO_PCH_ENABLE_3 ("DISABLED"),
.ENUM_AUTO_PCH_ENABLE_4 ("DISABLED"),
.ENUM_AUTO_PCH_ENABLE_5 ("DISABLED"),
.ENUM_CAL_REQ ("DISABLED"),
.ENUM_CFG_BURST_LENGTH ("BL_8"),
.ENUM_CFG_INTERFACE_WIDTH ("DWIDTH_32"),
.ENUM_CFG_SELF_RFSH_EXIT_CYCLES ("SELF_RFSH_EXIT_CYCLES_512"),
.ENUM_CFG_STARVE_LIMIT ("STARVE_LIMIT_10"),
.ENUM_CFG_TYPE ("DDR3"),
.ENUM_CLOCK_OFF_0 ("DISABLED"),
.ENUM_CLOCK_OFF_1 ("DISABLED"),
.ENUM_CLOCK_OFF_2 ("DISABLED"),
.ENUM_CLOCK_OFF_3 ("DISABLED"),
.ENUM_CLOCK_OFF_4 ("DISABLED"),
.ENUM_CLOCK_OFF_5 ("DISABLED"),
.ENUM_CLR_INTR ("NO_CLR_INTR"),
.ENUM_CMD_PORT_IN_USE_0 ("FALSE"),
.ENUM_CMD_PORT_IN_USE_1 ("FALSE"),
.ENUM_CMD_PORT_IN_USE_2 ("FALSE"),
.ENUM_CMD_PORT_IN_USE_3 ("FALSE"),
.ENUM_CMD_PORT_IN_USE_4 ("FALSE"),
.ENUM_CMD_PORT_IN_USE_5 ("FALSE"),
.ENUM_CPORT0_RDY_ALMOST_FULL ("NOT_FULL"),
.ENUM_CPORT0_RFIFO_MAP ("FIFO_0"),
.ENUM_CPORT0_TYPE ("DISABLE"),
.ENUM_CPORT0_WFIFO_MAP ("FIFO_0"),
.ENUM_CPORT1_RDY_ALMOST_FULL ("NOT_FULL"),
.ENUM_CPORT1_RFIFO_MAP ("FIFO_0"),
.ENUM_CPORT1_TYPE ("DISABLE"),
.ENUM_CPORT1_WFIFO_MAP ("FIFO_0"),
.ENUM_CPORT2_RDY_ALMOST_FULL ("NOT_FULL"),
.ENUM_CPORT2_RFIFO_MAP ("FIFO_0"),
.ENUM_CPORT2_TYPE ("DISABLE"),
.ENUM_CPORT2_WFIFO_MAP ("FIFO_0"),
.ENUM_CPORT3_RDY_ALMOST_FULL ("NOT_FULL"),
.ENUM_CPORT3_RFIFO_MAP ("FIFO_0"),
.ENUM_CPORT3_TYPE ("DISABLE"),
.ENUM_CPORT3_WFIFO_MAP ("FIFO_0"),
.ENUM_CPORT4_RDY_ALMOST_FULL ("NOT_FULL"),
.ENUM_CPORT4_RFIFO_MAP ("FIFO_0"),
.ENUM_CPORT4_TYPE ("DISABLE"),
.ENUM_CPORT4_WFIFO_MAP ("FIFO_0"),
.ENUM_CPORT5_RDY_ALMOST_FULL ("NOT_FULL"),
.ENUM_CPORT5_RFIFO_MAP ("FIFO_0"),
.ENUM_CPORT5_TYPE ("DISABLE"),
.ENUM_CPORT5_WFIFO_MAP ("FIFO_0"),
.ENUM_CTL_ADDR_ORDER ("CHIP_ROW_BANK_COL"),
.ENUM_CTL_ECC_ENABLED ("CTL_ECC_DISABLED"),
.ENUM_CTL_ECC_RMW_ENABLED ("CTL_ECC_RMW_DISABLED"),
.ENUM_CTL_REGDIMM_ENABLED ("REGDIMM_DISABLED"),
.ENUM_CTL_USR_REFRESH ("CTL_USR_REFRESH_DISABLED"),
.ENUM_CTRL_WIDTH ("DATA_WIDTH_64_BIT"),
.ENUM_DELAY_BONDING ("BONDING_LATENCY_0"),
.ENUM_DFX_BYPASS_ENABLE ("DFX_BYPASS_DISABLED"),
.ENUM_DISABLE_MERGING ("MERGING_ENABLED"),
.ENUM_ECC_DQ_WIDTH ("ECC_DQ_WIDTH_0"),
.ENUM_ENABLE_ATPG ("DISABLED"),
.ENUM_ENABLE_BONDING_0 ("DISABLED"),
.ENUM_ENABLE_BONDING_1 ("DISABLED"),
.ENUM_ENABLE_BONDING_2 ("DISABLED"),
.ENUM_ENABLE_BONDING_3 ("DISABLED"),
.ENUM_ENABLE_BONDING_4 ("DISABLED"),
.ENUM_ENABLE_BONDING_5 ("DISABLED"),
.ENUM_ENABLE_BONDING_WRAPBACK ("DISABLED"),
.ENUM_ENABLE_DQS_TRACKING ("ENABLED"),
.ENUM_ENABLE_ECC_CODE_OVERWRITES ("DISABLED"),
.ENUM_ENABLE_FAST_EXIT_PPD ("DISABLED"),
.ENUM_ENABLE_INTR ("DISABLED"),
.ENUM_ENABLE_NO_DM ("DISABLED"),
.ENUM_ENABLE_PIPELINEGLOBAL ("DISABLED"),
.ENUM_GANGED_ARF ("DISABLED"),
.ENUM_GEN_DBE ("GEN_DBE_DISABLED"),
.ENUM_GEN_SBE ("GEN_SBE_DISABLED"),
.ENUM_INC_SYNC ("FIFO_SET_2"),
.ENUM_LOCAL_IF_CS_WIDTH ("ADDR_WIDTH_0"),
.ENUM_MASK_CORR_DROPPED_INTR ("DISABLED"),
.ENUM_MASK_DBE_INTR ("DISABLED"),
.ENUM_MASK_SBE_INTR ("DISABLED"),
.ENUM_MEM_IF_AL ("AL_0"),
.ENUM_MEM_IF_BANKADDR_WIDTH ("ADDR_WIDTH_3"),
.ENUM_MEM_IF_BURSTLENGTH ("MEM_IF_BURSTLENGTH_8"),
.ENUM_MEM_IF_COLADDR_WIDTH ("ADDR_WIDTH_10"),
.ENUM_MEM_IF_CS_PER_RANK ("MEM_IF_CS_PER_RANK_1"),
.ENUM_MEM_IF_CS_WIDTH ("MEM_IF_CS_WIDTH_1"),
.ENUM_MEM_IF_DQ_PER_CHIP ("MEM_IF_DQ_PER_CHIP_8"),
.ENUM_MEM_IF_DQS_WIDTH ("DQS_WIDTH_4"),
.ENUM_MEM_IF_DWIDTH ("MEM_IF_DWIDTH_32"),
.ENUM_MEM_IF_MEMTYPE ("DDR3_SDRAM"),
.ENUM_MEM_IF_ROWADDR_WIDTH ("ADDR_WIDTH_15"),
.ENUM_MEM_IF_SPEEDBIN ("DDR3_1600_8_8_8"),
.ENUM_MEM_IF_TCCD ("TCCD_4"),
.ENUM_MEM_IF_TCL ("TCL_7"),
.ENUM_MEM_IF_TCWL ("TCWL_7"),
.ENUM_MEM_IF_TFAW ("TFAW_15"),
.ENUM_MEM_IF_TMRD ("TMRD_4"),
.ENUM_MEM_IF_TRAS ("TRAS_14"),
.ENUM_MEM_IF_TRC ("TRC_20"),
.ENUM_MEM_IF_TRCD ("TRCD_6"),
.ENUM_MEM_IF_TRP ("TRP_6"),
.ENUM_MEM_IF_TRRD ("TRRD_3"),
.ENUM_MEM_IF_TRTP ("TRTP_3"),
.ENUM_MEM_IF_TWR ("TWR_6"),
.ENUM_MEM_IF_TWTR ("TWTR_4"),
.ENUM_MMR_CFG_MEM_BL ("MP_BL_8"),
.ENUM_OUTPUT_REGD ("DISABLED"),
.ENUM_PDN_EXIT_CYCLES ("SLOW_EXIT"),
.ENUM_PORT0_WIDTH ("PORT_32_BIT"),
.ENUM_PORT1_WIDTH ("PORT_32_BIT"),
.ENUM_PORT2_WIDTH ("PORT_32_BIT"),
.ENUM_PORT3_WIDTH ("PORT_32_BIT"),
.ENUM_PORT4_WIDTH ("PORT_32_BIT"),
.ENUM_PORT5_WIDTH ("PORT_32_BIT"),
.ENUM_PRIORITY_0_0 ("WEIGHT_0"),
.ENUM_PRIORITY_0_1 ("WEIGHT_0"),
.ENUM_PRIORITY_0_2 ("WEIGHT_0"),
.ENUM_PRIORITY_0_3 ("WEIGHT_0"),
.ENUM_PRIORITY_0_4 ("WEIGHT_0"),
.ENUM_PRIORITY_0_5 ("WEIGHT_0"),
.ENUM_PRIORITY_1_0 ("WEIGHT_0"),
.ENUM_PRIORITY_1_1 ("WEIGHT_0"),
.ENUM_PRIORITY_1_2 ("WEIGHT_0"),
.ENUM_PRIORITY_1_3 ("WEIGHT_0"),
.ENUM_PRIORITY_1_4 ("WEIGHT_0"),
.ENUM_PRIORITY_1_5 ("WEIGHT_0"),
.ENUM_PRIORITY_2_0 ("WEIGHT_0"),
.ENUM_PRIORITY_2_1 ("WEIGHT_0"),
.ENUM_PRIORITY_2_2 ("WEIGHT_0"),
.ENUM_PRIORITY_2_3 ("WEIGHT_0"),
.ENUM_PRIORITY_2_4 ("WEIGHT_0"),
.ENUM_PRIORITY_2_5 ("WEIGHT_0"),
.ENUM_PRIORITY_3_0 ("WEIGHT_0"),
.ENUM_PRIORITY_3_1 ("WEIGHT_0"),
.ENUM_PRIORITY_3_2 ("WEIGHT_0"),
.ENUM_PRIORITY_3_3 ("WEIGHT_0"),
.ENUM_PRIORITY_3_4 ("WEIGHT_0"),
.ENUM_PRIORITY_3_5 ("WEIGHT_0"),
.ENUM_PRIORITY_4_0 ("WEIGHT_0"),
.ENUM_PRIORITY_4_1 ("WEIGHT_0"),
.ENUM_PRIORITY_4_2 ("WEIGHT_0"),
.ENUM_PRIORITY_4_3 ("WEIGHT_0"),
.ENUM_PRIORITY_4_4 ("WEIGHT_0"),
.ENUM_PRIORITY_4_5 ("WEIGHT_0"),
.ENUM_PRIORITY_5_0 ("WEIGHT_0"),
.ENUM_PRIORITY_5_1 ("WEIGHT_0"),
.ENUM_PRIORITY_5_2 ("WEIGHT_0"),
.ENUM_PRIORITY_5_3 ("WEIGHT_0"),
.ENUM_PRIORITY_5_4 ("WEIGHT_0"),
.ENUM_PRIORITY_5_5 ("WEIGHT_0"),
.ENUM_PRIORITY_6_0 ("WEIGHT_0"),
.ENUM_PRIORITY_6_1 ("WEIGHT_0"),
.ENUM_PRIORITY_6_2 ("WEIGHT_0"),
.ENUM_PRIORITY_6_3 ("WEIGHT_0"),
.ENUM_PRIORITY_6_4 ("WEIGHT_0"),
.ENUM_PRIORITY_6_5 ("WEIGHT_0"),
.ENUM_PRIORITY_7_0 ("WEIGHT_0"),
.ENUM_PRIORITY_7_1 ("WEIGHT_0"),
.ENUM_PRIORITY_7_2 ("WEIGHT_0"),
.ENUM_PRIORITY_7_3 ("WEIGHT_0"),
.ENUM_PRIORITY_7_4 ("WEIGHT_0"),
.ENUM_PRIORITY_7_5 ("WEIGHT_0"),
.ENUM_RCFG_STATIC_WEIGHT_0 ("WEIGHT_0"),
.ENUM_RCFG_STATIC_WEIGHT_1 ("WEIGHT_0"),
.ENUM_RCFG_STATIC_WEIGHT_2 ("WEIGHT_0"),
.ENUM_RCFG_STATIC_WEIGHT_3 ("WEIGHT_0"),
.ENUM_RCFG_STATIC_WEIGHT_4 ("WEIGHT_0"),
.ENUM_RCFG_STATIC_WEIGHT_5 ("WEIGHT_0"),
.ENUM_RCFG_USER_PRIORITY_0 ("PRIORITY_1"),
.ENUM_RCFG_USER_PRIORITY_1 ("PRIORITY_1"),
.ENUM_RCFG_USER_PRIORITY_2 ("PRIORITY_1"),
.ENUM_RCFG_USER_PRIORITY_3 ("PRIORITY_1"),
.ENUM_RCFG_USER_PRIORITY_4 ("PRIORITY_1"),
.ENUM_RCFG_USER_PRIORITY_5 ("PRIORITY_1"),
.ENUM_RD_DWIDTH_0 ("DWIDTH_0"),
.ENUM_RD_DWIDTH_1 ("DWIDTH_0"),
.ENUM_RD_DWIDTH_2 ("DWIDTH_0"),
.ENUM_RD_DWIDTH_3 ("DWIDTH_0"),
.ENUM_RD_DWIDTH_4 ("DWIDTH_0"),
.ENUM_RD_DWIDTH_5 ("DWIDTH_0"),
.ENUM_RD_FIFO_IN_USE_0 ("FALSE"),
.ENUM_RD_FIFO_IN_USE_1 ("FALSE"),
.ENUM_RD_FIFO_IN_USE_2 ("FALSE"),
.ENUM_RD_FIFO_IN_USE_3 ("FALSE"),
.ENUM_RD_PORT_INFO_0 ("USE_NO"),
.ENUM_RD_PORT_INFO_1 ("USE_NO"),
.ENUM_RD_PORT_INFO_2 ("USE_NO"),
.ENUM_RD_PORT_INFO_3 ("USE_NO"),
.ENUM_RD_PORT_INFO_4 ("USE_NO"),
.ENUM_RD_PORT_INFO_5 ("USE_NO"),
.ENUM_READ_ODT_CHIP ("ODT_DISABLED"),
.ENUM_REORDER_DATA ("DATA_REORDERING"),
.ENUM_RFIFO0_CPORT_MAP ("CMD_PORT_0"),
.ENUM_RFIFO1_CPORT_MAP ("CMD_PORT_0"),
.ENUM_RFIFO2_CPORT_MAP ("CMD_PORT_0"),
.ENUM_RFIFO3_CPORT_MAP ("CMD_PORT_0"),
.ENUM_SINGLE_READY_0 ("CONCATENATE_RDY"),
.ENUM_SINGLE_READY_1 ("CONCATENATE_RDY"),
.ENUM_SINGLE_READY_2 ("CONCATENATE_RDY"),
.ENUM_SINGLE_READY_3 ("CONCATENATE_RDY"),
.ENUM_STATIC_WEIGHT_0 ("WEIGHT_0"),
.ENUM_STATIC_WEIGHT_1 ("WEIGHT_0"),
.ENUM_STATIC_WEIGHT_2 ("WEIGHT_0"),
.ENUM_STATIC_WEIGHT_3 ("WEIGHT_0"),
.ENUM_STATIC_WEIGHT_4 ("WEIGHT_0"),
.ENUM_STATIC_WEIGHT_5 ("WEIGHT_0"),
.ENUM_SYNC_MODE_0 ("ASYNCHRONOUS"),
.ENUM_SYNC_MODE_1 ("ASYNCHRONOUS"),
.ENUM_SYNC_MODE_2 ("ASYNCHRONOUS"),
.ENUM_SYNC_MODE_3 ("ASYNCHRONOUS"),
.ENUM_SYNC_MODE_4 ("ASYNCHRONOUS"),
.ENUM_SYNC_MODE_5 ("ASYNCHRONOUS"),
.ENUM_TEST_MODE ("NORMAL_MODE"),
.ENUM_THLD_JAR1_0 ("THRESHOLD_32"),
.ENUM_THLD_JAR1_1 ("THRESHOLD_32"),
.ENUM_THLD_JAR1_2 ("THRESHOLD_32"),
.ENUM_THLD_JAR1_3 ("THRESHOLD_32"),
.ENUM_THLD_JAR1_4 ("THRESHOLD_32"),
.ENUM_THLD_JAR1_5 ("THRESHOLD_32"),
.ENUM_THLD_JAR2_0 ("THRESHOLD_16"),
.ENUM_THLD_JAR2_1 ("THRESHOLD_16"),
.ENUM_THLD_JAR2_2 ("THRESHOLD_16"),
.ENUM_THLD_JAR2_3 ("THRESHOLD_16"),
.ENUM_THLD_JAR2_4 ("THRESHOLD_16"),
.ENUM_THLD_JAR2_5 ("THRESHOLD_16"),
.ENUM_USE_ALMOST_EMPTY_0 ("EMPTY"),
.ENUM_USE_ALMOST_EMPTY_1 ("EMPTY"),
.ENUM_USE_ALMOST_EMPTY_2 ("EMPTY"),
.ENUM_USE_ALMOST_EMPTY_3 ("EMPTY"),
.ENUM_USER_ECC_EN ("DISABLE"),
.ENUM_USER_PRIORITY_0 ("PRIORITY_1"),
.ENUM_USER_PRIORITY_1 ("PRIORITY_1"),
.ENUM_USER_PRIORITY_2 ("PRIORITY_1"),
.ENUM_USER_PRIORITY_3 ("PRIORITY_1"),
.ENUM_USER_PRIORITY_4 ("PRIORITY_1"),
.ENUM_USER_PRIORITY_5 ("PRIORITY_1"),
.ENUM_WFIFO0_CPORT_MAP ("CMD_PORT_0"),
.ENUM_WFIFO0_RDY_ALMOST_FULL ("NOT_FULL"),
.ENUM_WFIFO1_CPORT_MAP ("CMD_PORT_0"),
.ENUM_WFIFO1_RDY_ALMOST_FULL ("NOT_FULL"),
.ENUM_WFIFO2_CPORT_MAP ("CMD_PORT_0"),
.ENUM_WFIFO2_RDY_ALMOST_FULL ("NOT_FULL"),
.ENUM_WFIFO3_CPORT_MAP ("CMD_PORT_0"),
.ENUM_WFIFO3_RDY_ALMOST_FULL ("NOT_FULL"),
.ENUM_WR_DWIDTH_0 ("DWIDTH_0"),
.ENUM_WR_DWIDTH_1 ("DWIDTH_0"),
.ENUM_WR_DWIDTH_2 ("DWIDTH_0"),
.ENUM_WR_DWIDTH_3 ("DWIDTH_0"),
.ENUM_WR_DWIDTH_4 ("DWIDTH_0"),
.ENUM_WR_DWIDTH_5 ("DWIDTH_0"),
.ENUM_WR_FIFO_IN_USE_0 ("FALSE"),
.ENUM_WR_FIFO_IN_USE_1 ("FALSE"),
.ENUM_WR_FIFO_IN_USE_2 ("FALSE"),
.ENUM_WR_FIFO_IN_USE_3 ("FALSE"),
.ENUM_WR_PORT_INFO_0 ("USE_NO"),
.ENUM_WR_PORT_INFO_1 ("USE_NO"),
.ENUM_WR_PORT_INFO_2 ("USE_NO"),
.ENUM_WR_PORT_INFO_3 ("USE_NO"),
.ENUM_WR_PORT_INFO_4 ("USE_NO"),
.ENUM_WR_PORT_INFO_5 ("USE_NO"),
.ENUM_WRITE_ODT_CHIP ("WRITE_CHIP0_ODT0_CHIP1"),
.INTG_MEM_AUTO_PD_CYCLES (0),
.INTG_CYC_TO_RLD_JARS_0 (1),
.INTG_CYC_TO_RLD_JARS_1 (1),
.INTG_CYC_TO_RLD_JARS_2 (1),
.INTG_CYC_TO_RLD_JARS_3 (1),
.INTG_CYC_TO_RLD_JARS_4 (1),
.INTG_CYC_TO_RLD_JARS_5 (1),
.INTG_EXTRA_CTL_CLK_ACT_TO_ACT (0),
.INTG_EXTRA_CTL_CLK_ACT_TO_ACT_DIFF_BANK (0),
.INTG_EXTRA_CTL_CLK_ACT_TO_PCH (0),
.INTG_EXTRA_CTL_CLK_ACT_TO_RDWR (0),
.INTG_EXTRA_CTL_CLK_ARF_PERIOD (0),
.INTG_EXTRA_CTL_CLK_ARF_TO_VALID (0),
.INTG_EXTRA_CTL_CLK_FOUR_ACT_TO_ACT (0),
.INTG_EXTRA_CTL_CLK_PCH_ALL_TO_VALID (0),
.INTG_EXTRA_CTL_CLK_PCH_TO_VALID (0),
.INTG_EXTRA_CTL_CLK_PDN_PERIOD (0),
.INTG_EXTRA_CTL_CLK_PDN_TO_VALID (0),
.INTG_EXTRA_CTL_CLK_RD_AP_TO_VALID (0),
.INTG_EXTRA_CTL_CLK_RD_TO_PCH (0),
.INTG_EXTRA_CTL_CLK_RD_TO_RD (0),
.INTG_EXTRA_CTL_CLK_RD_TO_RD_DIFF_CHIP (0),
.INTG_EXTRA_CTL_CLK_RD_TO_WR (2),
.INTG_EXTRA_CTL_CLK_RD_TO_WR_BC (2),
.INTG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP (2),
.INTG_EXTRA_CTL_CLK_SRF_TO_VALID (0),
.INTG_EXTRA_CTL_CLK_SRF_TO_ZQ_CAL (0),
.INTG_EXTRA_CTL_CLK_WR_AP_TO_VALID (0),
.INTG_EXTRA_CTL_CLK_WR_TO_PCH (0),
.INTG_EXTRA_CTL_CLK_WR_TO_RD (3),
.INTG_EXTRA_CTL_CLK_WR_TO_RD_BC (3),
.INTG_EXTRA_CTL_CLK_WR_TO_RD_DIFF_CHIP (3),
.INTG_EXTRA_CTL_CLK_WR_TO_WR (0),
.INTG_EXTRA_CTL_CLK_WR_TO_WR_DIFF_CHIP (0),
.INTG_MEM_IF_TREFI (3120),
.INTG_MEM_IF_TRFC (120),
.INTG_RCFG_SUM_WT_PRIORITY_0 (0),
.INTG_RCFG_SUM_WT_PRIORITY_1 (0),
.INTG_RCFG_SUM_WT_PRIORITY_2 (0),
.INTG_RCFG_SUM_WT_PRIORITY_3 (0),
.INTG_RCFG_SUM_WT_PRIORITY_4 (0),
.INTG_RCFG_SUM_WT_PRIORITY_5 (0),
.INTG_RCFG_SUM_WT_PRIORITY_6 (0),
.INTG_RCFG_SUM_WT_PRIORITY_7 (0),
.INTG_SUM_WT_PRIORITY_0 (0),
.INTG_SUM_WT_PRIORITY_1 (0),
.INTG_SUM_WT_PRIORITY_2 (0),
.INTG_SUM_WT_PRIORITY_3 (0),
.INTG_SUM_WT_PRIORITY_4 (0),
.INTG_SUM_WT_PRIORITY_5 (0),
.INTG_SUM_WT_PRIORITY_6 (0),
.INTG_SUM_WT_PRIORITY_7 (0),
.INTG_POWER_SAVING_EXIT_CYCLES (5),
.INTG_MEM_CLK_ENTRY_CYCLES (10),
.ENUM_ENABLE_BURST_INTERRUPT ("DISABLED"),
.ENUM_ENABLE_BURST_TERMINATE ("DISABLED"),
.AFI_RATE_RATIO (1),
.AFI_ADDR_WIDTH (15),
.AFI_BANKADDR_WIDTH (3),
.AFI_CONTROL_WIDTH (1),
.AFI_CS_WIDTH (1),
.AFI_DM_WIDTH (8),
.AFI_DQ_WIDTH (64),
.AFI_ODT_WIDTH (1),
.AFI_WRITE_DQS_WIDTH (4),
.AFI_RLAT_WIDTH (6),
.AFI_WLAT_WIDTH (6),
.HARD_PHY (1)
) c0 (
.afi_clk (pll_afi_clk_clk), // afi_clk.clk
.afi_reset_n (p0_afi_reset_reset), // afi_reset.reset_n
.ctl_reset_n (p0_ctl_reset_reset), // ctl_reset.reset_n
.afi_half_clk (pll_afi_half_clk_clk), // afi_half_clk.clk
.ctl_clk (p0_ctl_clk_clk), // ctl_clk.clk
.local_init_done (), // status.local_init_done
.local_cal_success (), // .local_cal_success
.local_cal_fail (), // .local_cal_fail
.afi_addr (c0_afi_afi_addr), // afi.afi_addr
.afi_ba (c0_afi_afi_ba), // .afi_ba
.afi_cke (c0_afi_afi_cke), // .afi_cke
.afi_cs_n (c0_afi_afi_cs_n), // .afi_cs_n
.afi_ras_n (c0_afi_afi_ras_n), // .afi_ras_n
.afi_we_n (c0_afi_afi_we_n), // .afi_we_n
.afi_cas_n (c0_afi_afi_cas_n), // .afi_cas_n
.afi_rst_n (c0_afi_afi_rst_n), // .afi_rst_n
.afi_odt (c0_afi_afi_odt), // .afi_odt
.afi_mem_clk_disable (c0_afi_afi_mem_clk_disable), // .afi_mem_clk_disable
.afi_init_req (), // .afi_init_req
.afi_cal_req (), // .afi_cal_req
.afi_seq_busy (), // .afi_seq_busy
.afi_ctl_refresh_done (), // .afi_ctl_refresh_done
.afi_ctl_long_idle (), // .afi_ctl_long_idle
.afi_dqs_burst (c0_afi_afi_dqs_burst), // .afi_dqs_burst
.afi_wdata_valid (c0_afi_afi_wdata_valid), // .afi_wdata_valid
.afi_wdata (c0_afi_afi_wdata), // .afi_wdata
.afi_dm (c0_afi_afi_dm), // .afi_dm
.afi_rdata (p0_afi_afi_rdata), // .afi_rdata
.afi_rdata_en (c0_afi_afi_rdata_en), // .afi_rdata_en
.afi_rdata_en_full (c0_afi_afi_rdata_en_full), // .afi_rdata_en_full
.afi_rdata_valid (p0_afi_afi_rdata_valid), // .afi_rdata_valid
.afi_wlat (p0_afi_afi_wlat), // .afi_wlat
.afi_rlat (p0_afi_afi_rlat), // .afi_rlat
.afi_cal_success (p0_afi_afi_cal_success), // .afi_cal_success
.afi_cal_fail (p0_afi_afi_cal_fail), // .afi_cal_fail
.cfg_addlat (c0_hard_phy_cfg_cfg_addlat), // hard_phy_cfg.cfg_addlat
.cfg_bankaddrwidth (c0_hard_phy_cfg_cfg_bankaddrwidth), // .cfg_bankaddrwidth
.cfg_caswrlat (c0_hard_phy_cfg_cfg_caswrlat), // .cfg_caswrlat
.cfg_coladdrwidth (c0_hard_phy_cfg_cfg_coladdrwidth), // .cfg_coladdrwidth
.cfg_csaddrwidth (c0_hard_phy_cfg_cfg_csaddrwidth), // .cfg_csaddrwidth
.cfg_devicewidth (c0_hard_phy_cfg_cfg_devicewidth), // .cfg_devicewidth
.cfg_dramconfig (c0_hard_phy_cfg_cfg_dramconfig), // .cfg_dramconfig
.cfg_interfacewidth (c0_hard_phy_cfg_cfg_interfacewidth), // .cfg_interfacewidth
.cfg_rowaddrwidth (c0_hard_phy_cfg_cfg_rowaddrwidth), // .cfg_rowaddrwidth
.cfg_tcl (c0_hard_phy_cfg_cfg_tcl), // .cfg_tcl
.cfg_tmrd (c0_hard_phy_cfg_cfg_tmrd), // .cfg_tmrd
.cfg_trefi (c0_hard_phy_cfg_cfg_trefi), // .cfg_trefi
.cfg_trfc (c0_hard_phy_cfg_cfg_trfc), // .cfg_trfc
.cfg_twr (c0_hard_phy_cfg_cfg_twr), // .cfg_twr
.io_intaficalfail (p0_io_int_io_intaficalfail), // io_int.io_intaficalfail
.io_intaficalsuccess (p0_io_int_io_intaficalsuccess), // .io_intaficalsuccess
.mp_cmd_clk_0 (1'b0), // (terminated)
.mp_cmd_reset_n_0 (1'b1), // (terminated)
.mp_cmd_clk_1 (1'b0), // (terminated)
.mp_cmd_reset_n_1 (1'b1), // (terminated)
.mp_cmd_clk_2 (1'b0), // (terminated)
.mp_cmd_reset_n_2 (1'b1), // (terminated)
.mp_cmd_clk_3 (1'b0), // (terminated)
.mp_cmd_reset_n_3 (1'b1), // (terminated)
.mp_cmd_clk_4 (1'b0), // (terminated)
.mp_cmd_reset_n_4 (1'b1), // (terminated)
.mp_cmd_clk_5 (1'b0), // (terminated)
.mp_cmd_reset_n_5 (1'b1), // (terminated)
.mp_rfifo_clk_0 (1'b0), // (terminated)
.mp_rfifo_reset_n_0 (1'b1), // (terminated)
.mp_wfifo_clk_0 (1'b0), // (terminated)
.mp_wfifo_reset_n_0 (1'b1), // (terminated)
.mp_rfifo_clk_1 (1'b0), // (terminated)
.mp_rfifo_reset_n_1 (1'b1), // (terminated)
.mp_wfifo_clk_1 (1'b0), // (terminated)
.mp_wfifo_reset_n_1 (1'b1), // (terminated)
.mp_rfifo_clk_2 (1'b0), // (terminated)
.mp_rfifo_reset_n_2 (1'b1), // (terminated)
.mp_wfifo_clk_2 (1'b0), // (terminated)
.mp_wfifo_reset_n_2 (1'b1), // (terminated)
.mp_rfifo_clk_3 (1'b0), // (terminated)
.mp_rfifo_reset_n_3 (1'b1), // (terminated)
.mp_wfifo_clk_3 (1'b0), // (terminated)
.mp_wfifo_reset_n_3 (1'b1), // (terminated)
.csr_clk (1'b0), // (terminated)
.csr_reset_n (1'b1), // (terminated)
.avl_ready_0 (), // (terminated)
.avl_burstbegin_0 (1'b0), // (terminated)
.avl_addr_0 (1'b0), // (terminated)
.avl_rdata_valid_0 (), // (terminated)
.avl_rdata_0 (), // (terminated)
.avl_wdata_0 (1'b0), // (terminated)
.avl_be_0 (1'b0), // (terminated)
.avl_read_req_0 (1'b0), // (terminated)
.avl_write_req_0 (1'b0), // (terminated)
.avl_size_0 (3'b000), // (terminated)
.avl_ready_1 (), // (terminated)
.avl_burstbegin_1 (1'b0), // (terminated)
.avl_addr_1 (1'b0), // (terminated)
.avl_rdata_valid_1 (), // (terminated)
.avl_rdata_1 (), // (terminated)
.avl_wdata_1 (1'b0), // (terminated)
.avl_be_1 (1'b0), // (terminated)
.avl_read_req_1 (1'b0), // (terminated)
.avl_write_req_1 (1'b0), // (terminated)
.avl_size_1 (3'b000), // (terminated)
.avl_ready_2 (), // (terminated)
.avl_burstbegin_2 (1'b0), // (terminated)
.avl_addr_2 (1'b0), // (terminated)
.avl_rdata_valid_2 (), // (terminated)
.avl_rdata_2 (), // (terminated)
.avl_wdata_2 (1'b0), // (terminated)
.avl_be_2 (1'b0), // (terminated)
.avl_read_req_2 (1'b0), // (terminated)
.avl_write_req_2 (1'b0), // (terminated)
.avl_size_2 (3'b000), // (terminated)
.avl_ready_3 (), // (terminated)
.avl_burstbegin_3 (1'b0), // (terminated)
.avl_addr_3 (1'b0), // (terminated)
.avl_rdata_valid_3 (), // (terminated)
.avl_rdata_3 (), // (terminated)
.avl_wdata_3 (1'b0), // (terminated)
.avl_be_3 (1'b0), // (terminated)
.avl_read_req_3 (1'b0), // (terminated)
.avl_write_req_3 (1'b0), // (terminated)
.avl_size_3 (3'b000), // (terminated)
.avl_ready_4 (), // (terminated)
.avl_burstbegin_4 (1'b0), // (terminated)
.avl_addr_4 (1'b0), // (terminated)
.avl_rdata_valid_4 (), // (terminated)
.avl_rdata_4 (), // (terminated)
.avl_wdata_4 (1'b0), // (terminated)
.avl_be_4 (1'b0), // (terminated)
.avl_read_req_4 (1'b0), // (terminated)
.avl_write_req_4 (1'b0), // (terminated)
.avl_size_4 (3'b000), // (terminated)
.avl_ready_5 (), // (terminated)
.avl_burstbegin_5 (1'b0), // (terminated)
.avl_addr_5 (1'b0), // (terminated)
.avl_rdata_valid_5 (), // (terminated)
.avl_rdata_5 (), // (terminated)
.avl_wdata_5 (1'b0), // (terminated)
.avl_be_5 (1'b0), // (terminated)
.avl_read_req_5 (1'b0), // (terminated)
.avl_write_req_5 (1'b0), // (terminated)
.avl_size_5 (3'b000), // (terminated)
.csr_write_req (1'b0), // (terminated)
.csr_read_req (1'b0), // (terminated)
.csr_waitrequest (), // (terminated)
.csr_addr (10'b0000000000), // (terminated)
.csr_be (1'b0), // (terminated)
.csr_wdata (8'b00000000), // (terminated)
.csr_rdata (), // (terminated)
.csr_rdata_valid (), // (terminated)
.local_multicast (1'b0), // (terminated)
.local_refresh_req (1'b0), // (terminated)
.local_refresh_chip (1'b0), // (terminated)
.local_refresh_ack (), // (terminated)
.local_self_rfsh_req (1'b0), // (terminated)
.local_self_rfsh_chip (1'b0), // (terminated)
.local_self_rfsh_ack (), // (terminated)
.local_deep_powerdn_req (1'b0), // (terminated)
.local_deep_powerdn_chip (1'b0), // (terminated)
.local_deep_powerdn_ack (), // (terminated)
.local_powerdn_ack (), // (terminated)
.local_priority (1'b0), // (terminated)
.bonding_in_1 (4'b0000), // (terminated)
.bonding_in_2 (6'b000000), // (terminated)
.bonding_in_3 (6'b000000), // (terminated)
.bonding_out_1 (), // (terminated)
.bonding_out_2 (), // (terminated)
.bonding_out_3 () // (terminated)
);
altera_mem_if_oct_cyclonev #(
.OCT_TERM_CONTROL_WIDTH (16)
) oct (
.oct_rzqin (oct_rzqin), // oct.rzqin
.seriesterminationcontrol (oct_oct_sharing_seriesterminationcontrol), // oct_sharing.seriesterminationcontrol
.parallelterminationcontrol (oct_oct_sharing_parallelterminationcontrol) // .parallelterminationcontrol
);
altera_mem_if_dll_cyclonev #(
.DLL_DELAY_CTRL_WIDTH (7),
.DLL_OFFSET_CTRL_WIDTH (6),
.DELAY_BUFFER_MODE ("HIGH"),
.DELAY_CHAIN_LENGTH (8),
.DLL_INPUT_FREQUENCY_PS_STR ("2500 ps")
) dll (
.clk (p0_dll_clk_clk), // clk.clk
.dll_pll_locked (p0_dll_sharing_dll_pll_locked), // dll_sharing.dll_pll_locked
.dll_delayctrl (dll_dll_sharing_dll_delayctrl) // .dll_delayctrl
);
endmodule
|
module sky130_fd_sc_ms__sdlclkp (
GCLK,
SCE ,
GATE,
CLK
);
// Module ports
output GCLK;
input SCE ;
input GATE;
input CLK ;
// Local signals
wire m0 ;
wire m0n ;
wire clkn ;
wire SCE_GATE;
// Name Output Other arguments
not not0 (m0n , m0 );
not not1 (clkn , CLK );
nor nor0 (SCE_GATE, GATE, SCE );
sky130_fd_sc_ms__udp_dlatch$P dlatch0 (m0 , SCE_GATE, clkn );
and and0 (GCLK , m0n, CLK );
endmodule
|
module sky130_fd_sc_hs__tapvgnd2_1 (
VPWR,
VGND
);
input VPWR;
input VGND;
sky130_fd_sc_hs__tapvgnd2 base (
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
|
module sky130_fd_sc_hs__tapvgnd2_1 ();
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__tapvgnd2 base ();
endmodule
|
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