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module limbus_nios2_qsys_0_nios2_oci_itrace (
// inputs:
clk,
dbrk_traceoff,
dbrk_traceon,
jdo,
jrst_n,
take_action_tracectrl,
trc_enb,
xbrk_traceoff,
xbrk_traceon,
xbrk_wrap_traceoff,
// outputs:
dct_buffer,
dct_count,
itm,
trc_ctrl,
trc_on
)
;
output [ 29: 0] dct_buffer;
output [ 3: 0] dct_count;
output [ 35: 0] itm;
output [ 15: 0] trc_ctrl;
output trc_on;
input clk;
input dbrk_traceoff;
input dbrk_traceon;
input [ 15: 0] jdo;
input jrst_n;
input take_action_tracectrl;
input trc_enb;
input xbrk_traceoff;
input xbrk_traceon;
input xbrk_wrap_traceoff;
wire advanced_exc_occured;
wire curr_pid;
reg [ 29: 0] dct_buffer /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
wire [ 1: 0] dct_code;
reg [ 3: 0] dct_count /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
wire dct_is_taken;
wire [ 31: 0] eic_addr;
wire [ 31: 0] exc_addr;
wire instr_retired;
wire is_cond_dct;
wire is_dct;
wire is_exception_no_break;
wire is_external_interrupt;
wire is_fast_tlb_miss_exception;
wire is_idct;
reg [ 35: 0] itm /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
wire not_in_debug_mode;
reg pending_curr_pid /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
reg pending_exc /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
reg [ 31: 0] pending_exc_addr /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
reg [ 31: 0] pending_exc_handler /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
reg pending_exc_record_handler /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
reg [ 3: 0] pending_frametype /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
reg pending_prev_pid /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
reg prev_pid /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
reg prev_pid_valid /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
wire record_dct_outcome_in_sync;
wire record_itrace;
wire [ 31: 0] retired_pcb;
reg snapped_curr_pid /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
reg snapped_pid /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
reg snapped_prev_pid /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
wire [ 1: 0] sync_code;
wire [ 6: 0] sync_interval;
reg [ 6: 0] sync_timer /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
wire [ 6: 0] sync_timer_next;
wire sync_timer_reached_zero;
reg trc_clear /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=D101" */;
wire [ 15: 0] trc_ctrl;
reg [ 10: 0] trc_ctrl_reg /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */;
wire trc_on;
assign is_cond_dct = 1'b0;
assign is_dct = 1'b0;
assign dct_is_taken = 1'b0;
assign is_idct = 1'b0;
assign retired_pcb = 32'b0;
assign not_in_debug_mode = 1'b0;
assign instr_retired = 1'b0;
assign advanced_exc_occured = 1'b0;
assign is_exception_no_break = 1'b0;
assign is_external_interrupt = 1'b0;
assign is_fast_tlb_miss_exception = 1'b0;
assign curr_pid = 1'b0;
assign exc_addr = 32'b0;
assign eic_addr = 32'b0;
assign sync_code = trc_ctrl[3 : 2];
assign sync_interval = { sync_code[1] & sync_code[0], 1'b0, sync_code[1] & ~sync_code[0], 1'b0, ~sync_code[1] & sync_code[0], 2'b00 };
assign sync_timer_reached_zero = sync_timer == 0;
assign record_dct_outcome_in_sync = dct_is_taken & sync_timer_reached_zero;
assign sync_timer_next = sync_timer_reached_zero ? sync_timer : (sync_timer - 1);
assign record_itrace = trc_on & trc_ctrl[4];
assign dct_code = {is_cond_dct, dct_is_taken};
always @(posedge clk or negedge jrst_n)
begin
if (jrst_n == 0)
trc_clear <= 0;
else
trc_clear <= ~trc_enb &
take_action_tracectrl & jdo[4];
end
always @(posedge clk or negedge jrst_n)
begin
if (jrst_n == 0)
begin
itm <= 0;
dct_buffer <= 0;
dct_count <= 0;
sync_timer <= 0;
pending_frametype <= 4'b0000;
pending_exc <= 0;
pending_exc_addr <= 0;
pending_exc_handler <= 0;
pending_exc_record_handler <= 0;
prev_pid <= 0;
prev_pid_valid <= 0;
snapped_pid <= 0;
snapped_curr_pid <= 0;
snapped_prev_pid <= 0;
pending_curr_pid <= 0;
pending_prev_pid <= 0;
end
else if (trc_clear || (!0 && !0))
begin
itm <= 0;
dct_buffer <= 0;
dct_count <= 0;
sync_timer <= 0;
pending_frametype <= 4'b0000;
pending_exc <= 0;
pending_exc_addr <= 0;
pending_exc_handler <= 0;
pending_exc_record_handler <= 0;
prev_pid <= 0;
prev_pid_valid <= 0;
snapped_pid <= 0;
snapped_curr_pid <= 0;
snapped_prev_pid <= 0;
pending_curr_pid <= 0;
pending_prev_pid <= 0;
end
else
begin
if (!prev_pid_valid)
begin
prev_pid <= curr_pid;
prev_pid_valid <= 1;
end
if ((curr_pid != prev_pid) & prev_pid_valid & !snapped_pid)
begin
snapped_pid <= 1;
snapped_curr_pid <= curr_pid;
snapped_prev_pid <= prev_pid;
prev_pid <= curr_pid;
prev_pid_valid <= 1;
end
if (instr_retired | advanced_exc_occured)
begin
if (~record_itrace)
pending_frametype <= 4'b1010;
else if (is_exception_no_break)
begin
pending_exc <= 1;
pending_exc_addr <= exc_addr;
pending_exc_record_handler <= 0;
if (is_external_interrupt)
pending_exc_handler <= eic_addr;
else if (is_fast_tlb_miss_exception)
pending_exc_handler <= 32'h0;
else
pending_exc_handler <= 32'h10000020;
pending_frametype <= 4'b0000;
end
else if (is_idct)
pending_frametype <= 4'b1001;
else if (record_dct_outcome_in_sync)
pending_frametype <= 4'b1000;
else if (!is_dct & snapped_pid)
begin
pending_frametype <= 4'b0011;
pending_curr_pid <= snapped_curr_pid;
pending_prev_pid <= snapped_prev_pid;
snapped_pid <= 0;
end
else
pending_frametype <= 4'b0000;
if ((dct_count != 0) &
(~record_itrace |
is_exception_no_break |
is_idct |
record_dct_outcome_in_sync |
(!is_dct & snapped_pid)))
begin
itm <= {4'b0001, dct_buffer, 2'b00};
dct_buffer <= 0;
dct_count <= 0;
sync_timer <= sync_timer_next;
end
else
begin
if (record_itrace & (is_dct & (dct_count != 4'd15)) & ~record_dct_outcome_in_sync & ~advanced_exc_occured)
begin
dct_buffer <= {dct_code, dct_buffer[29 : 2]};
dct_count <= dct_count + 1;
end
if (record_itrace & (
(pending_frametype == 4'b1000) |
(pending_frametype == 4'b1010) |
(pending_frametype == 4'b1001)))
begin
itm <= {pending_frametype, retired_pcb};
sync_timer <= sync_interval;
if (0 &
((pending_frametype == 4'b1000) | (pending_frametype == 4'b1010)) &
!snapped_pid & prev_pid_valid)
begin
snapped_pid <= 1;
snapped_curr_pid <= curr_pid;
snapped_prev_pid <= prev_pid;
end
end
else if (record_itrace &
0 & (pending_frametype == 4'b0011))
itm <= {4'b0011, 2'b00, pending_prev_pid, 2'b00, pending_curr_pid};
else if (record_itrace & is_dct)
begin
if (dct_count == 4'd15)
begin
itm <= {4'b0001, dct_code, dct_buffer};
dct_buffer <= 0;
dct_count <= 0;
sync_timer <= sync_timer_next;
end
else
itm <= 4'b0000;
end
else
itm <= {4'b0000, 32'b0};
end
end
else if (record_itrace & pending_exc)
begin
if (pending_exc_record_handler)
begin
itm <= {4'b0010, pending_exc_handler[31 : 1], 1'b1};
pending_exc <= 1'b0;
pending_exc_record_handler <= 1'b0;
end
else
begin
itm <= {4'b0010, pending_exc_addr[31 : 1], 1'b0};
pending_exc_record_handler <= 1'b1;
end
end
else
itm <= {4'b0000, 32'b0};
end
end
always @(posedge clk or negedge jrst_n)
begin
if (jrst_n == 0)
begin
trc_ctrl_reg[0] <= 1'b0;
trc_ctrl_reg[1] <= 1'b0;
trc_ctrl_reg[3 : 2] <= 2'b00;
trc_ctrl_reg[4] <= 1'b0;
trc_ctrl_reg[7 : 5] <= 3'b000;
trc_ctrl_reg[8] <= 0;
trc_ctrl_reg[9] <= 1'b0;
trc_ctrl_reg[10] <= 1'b0;
end
else if (take_action_tracectrl)
begin
trc_ctrl_reg[0] <= jdo[5];
trc_ctrl_reg[1] <= jdo[6];
trc_ctrl_reg[3 : 2] <= jdo[8 : 7];
trc_ctrl_reg[4] <= jdo[9];
trc_ctrl_reg[9] <= jdo[14];
trc_ctrl_reg[10] <= jdo[2];
if (0)
trc_ctrl_reg[7 : 5] <= jdo[12 : 10];
if (0 & 0)
trc_ctrl_reg[8] <= jdo[13];
end
else if (xbrk_wrap_traceoff)
begin
trc_ctrl_reg[1] <= 0;
trc_ctrl_reg[0] <= 0;
end
else if (dbrk_traceoff | xbrk_traceoff)
trc_ctrl_reg[1] <= 0;
else if (trc_ctrl_reg[0] &
(dbrk_traceon | xbrk_traceon))
trc_ctrl_reg[1] <= 1;
end
assign trc_ctrl = (0 || 0) ? {6'b000000, trc_ctrl_reg} : 0;
assign trc_on = trc_ctrl[1] & (trc_ctrl[9] | not_in_debug_mode);
endmodule
|
module limbus_nios2_qsys_0_nios2_oci_td_mode (
// inputs:
ctrl,
// outputs:
td_mode
)
;
output [ 3: 0] td_mode;
input [ 8: 0] ctrl;
wire [ 2: 0] ctrl_bits_for_mux;
reg [ 3: 0] td_mode;
assign ctrl_bits_for_mux = ctrl[7 : 5];
always @(ctrl_bits_for_mux)
begin
case (ctrl_bits_for_mux)
3'b000: begin
td_mode = 4'b0000;
end // 3'b000
3'b001: begin
td_mode = 4'b1000;
end // 3'b001
3'b010: begin
td_mode = 4'b0100;
end // 3'b010
3'b011: begin
td_mode = 4'b1100;
end // 3'b011
3'b100: begin
td_mode = 4'b0010;
end // 3'b100
3'b101: begin
td_mode = 4'b1010;
end // 3'b101
3'b110: begin
td_mode = 4'b0101;
end // 3'b110
3'b111: begin
td_mode = 4'b1111;
end // 3'b111
endcase // ctrl_bits_for_mux
end
endmodule
|
module limbus_nios2_qsys_0_nios2_oci_dtrace (
// inputs:
clk,
cpu_d_address,
cpu_d_read,
cpu_d_readdata,
cpu_d_wait,
cpu_d_write,
cpu_d_writedata,
jrst_n,
trc_ctrl,
// outputs:
atm,
dtm
)
;
output [ 35: 0] atm;
output [ 35: 0] dtm;
input clk;
input [ 28: 0] cpu_d_address;
input cpu_d_read;
input [ 31: 0] cpu_d_readdata;
input cpu_d_wait;
input cpu_d_write;
input [ 31: 0] cpu_d_writedata;
input jrst_n;
input [ 15: 0] trc_ctrl;
reg [ 35: 0] atm /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
wire [ 31: 0] cpu_d_address_0_padded;
wire [ 31: 0] cpu_d_readdata_0_padded;
wire [ 31: 0] cpu_d_writedata_0_padded;
reg [ 35: 0] dtm /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
wire record_load_addr;
wire record_load_data;
wire record_store_addr;
wire record_store_data;
wire [ 3: 0] td_mode_trc_ctrl;
assign cpu_d_writedata_0_padded = cpu_d_writedata | 32'b0;
assign cpu_d_readdata_0_padded = cpu_d_readdata | 32'b0;
assign cpu_d_address_0_padded = cpu_d_address | 32'b0;
//limbus_nios2_qsys_0_nios2_oci_trc_ctrl_td_mode, which is an e_instance
limbus_nios2_qsys_0_nios2_oci_td_mode limbus_nios2_qsys_0_nios2_oci_trc_ctrl_td_mode
(
.ctrl (trc_ctrl[8 : 0]),
.td_mode (td_mode_trc_ctrl)
);
assign {record_load_addr, record_store_addr,
record_load_data, record_store_data} = td_mode_trc_ctrl;
always @(posedge clk or negedge jrst_n)
begin
if (jrst_n == 0)
begin
atm <= 0;
dtm <= 0;
end
else if (0)
begin
if (cpu_d_write & ~cpu_d_wait & record_store_addr)
atm <= {4'b0101, cpu_d_address_0_padded};
else if (cpu_d_read & ~cpu_d_wait & record_load_addr)
atm <= {4'b0100, cpu_d_address_0_padded};
else
atm <= {4'b0000, cpu_d_address_0_padded};
if (cpu_d_write & ~cpu_d_wait & record_store_data)
dtm <= {4'b0111, cpu_d_writedata_0_padded};
else if (cpu_d_read & ~cpu_d_wait & record_load_data)
dtm <= {4'b0110, cpu_d_readdata_0_padded};
else
dtm <= {4'b0000, cpu_d_readdata_0_padded};
end
else
begin
atm <= 0;
dtm <= 0;
end
end
endmodule
|
module limbus_nios2_qsys_0_nios2_oci_compute_input_tm_cnt (
// inputs:
atm_valid,
dtm_valid,
itm_valid,
// outputs:
compute_input_tm_cnt
)
;
output [ 1: 0] compute_input_tm_cnt;
input atm_valid;
input dtm_valid;
input itm_valid;
reg [ 1: 0] compute_input_tm_cnt;
wire [ 2: 0] switch_for_mux;
assign switch_for_mux = {itm_valid, atm_valid, dtm_valid};
always @(switch_for_mux)
begin
case (switch_for_mux)
3'b000: begin
compute_input_tm_cnt = 0;
end // 3'b000
3'b001: begin
compute_input_tm_cnt = 1;
end // 3'b001
3'b010: begin
compute_input_tm_cnt = 1;
end // 3'b010
3'b011: begin
compute_input_tm_cnt = 2;
end // 3'b011
3'b100: begin
compute_input_tm_cnt = 1;
end // 3'b100
3'b101: begin
compute_input_tm_cnt = 2;
end // 3'b101
3'b110: begin
compute_input_tm_cnt = 2;
end // 3'b110
3'b111: begin
compute_input_tm_cnt = 3;
end // 3'b111
endcase // switch_for_mux
end
endmodule
|
module limbus_nios2_qsys_0_nios2_oci_fifo_wrptr_inc (
// inputs:
ge2_free,
ge3_free,
input_tm_cnt,
// outputs:
fifo_wrptr_inc
)
;
output [ 3: 0] fifo_wrptr_inc;
input ge2_free;
input ge3_free;
input [ 1: 0] input_tm_cnt;
reg [ 3: 0] fifo_wrptr_inc;
always @(ge2_free or ge3_free or input_tm_cnt)
begin
if (ge3_free & (input_tm_cnt == 3))
fifo_wrptr_inc = 3;
else if (ge2_free & (input_tm_cnt >= 2))
fifo_wrptr_inc = 2;
else if (input_tm_cnt >= 1)
fifo_wrptr_inc = 1;
else
fifo_wrptr_inc = 0;
end
endmodule
|
module limbus_nios2_qsys_0_nios2_oci_fifo_cnt_inc (
// inputs:
empty,
ge2_free,
ge3_free,
input_tm_cnt,
// outputs:
fifo_cnt_inc
)
;
output [ 4: 0] fifo_cnt_inc;
input empty;
input ge2_free;
input ge3_free;
input [ 1: 0] input_tm_cnt;
reg [ 4: 0] fifo_cnt_inc;
always @(empty or ge2_free or ge3_free or input_tm_cnt)
begin
if (empty)
fifo_cnt_inc = input_tm_cnt[1 : 0];
else if (ge3_free & (input_tm_cnt == 3))
fifo_cnt_inc = 2;
else if (ge2_free & (input_tm_cnt >= 2))
fifo_cnt_inc = 1;
else if (input_tm_cnt >= 1)
fifo_cnt_inc = 0;
else
fifo_cnt_inc = {5{1'b1}};
end
endmodule
|
module limbus_nios2_qsys_0_nios2_oci_fifo (
// inputs:
atm,
clk,
dbrk_traceme,
dbrk_traceoff,
dbrk_traceon,
dct_buffer,
dct_count,
dtm,
itm,
jrst_n,
reset_n,
test_ending,
test_has_ended,
trc_on,
// outputs:
tw
)
;
output [ 35: 0] tw;
input [ 35: 0] atm;
input clk;
input dbrk_traceme;
input dbrk_traceoff;
input dbrk_traceon;
input [ 29: 0] dct_buffer;
input [ 3: 0] dct_count;
input [ 35: 0] dtm;
input [ 35: 0] itm;
input jrst_n;
input reset_n;
input test_ending;
input test_has_ended;
input trc_on;
wire atm_valid;
wire [ 1: 0] compute_input_tm_cnt;
wire dtm_valid;
wire empty;
reg [ 35: 0] fifo_0;
wire fifo_0_enable;
wire [ 35: 0] fifo_0_mux;
reg [ 35: 0] fifo_1;
reg [ 35: 0] fifo_10;
wire fifo_10_enable;
wire [ 35: 0] fifo_10_mux;
reg [ 35: 0] fifo_11;
wire fifo_11_enable;
wire [ 35: 0] fifo_11_mux;
reg [ 35: 0] fifo_12;
wire fifo_12_enable;
wire [ 35: 0] fifo_12_mux;
reg [ 35: 0] fifo_13;
wire fifo_13_enable;
wire [ 35: 0] fifo_13_mux;
reg [ 35: 0] fifo_14;
wire fifo_14_enable;
wire [ 35: 0] fifo_14_mux;
reg [ 35: 0] fifo_15;
wire fifo_15_enable;
wire [ 35: 0] fifo_15_mux;
wire fifo_1_enable;
wire [ 35: 0] fifo_1_mux;
reg [ 35: 0] fifo_2;
wire fifo_2_enable;
wire [ 35: 0] fifo_2_mux;
reg [ 35: 0] fifo_3;
wire fifo_3_enable;
wire [ 35: 0] fifo_3_mux;
reg [ 35: 0] fifo_4;
wire fifo_4_enable;
wire [ 35: 0] fifo_4_mux;
reg [ 35: 0] fifo_5;
wire fifo_5_enable;
wire [ 35: 0] fifo_5_mux;
reg [ 35: 0] fifo_6;
wire fifo_6_enable;
wire [ 35: 0] fifo_6_mux;
reg [ 35: 0] fifo_7;
wire fifo_7_enable;
wire [ 35: 0] fifo_7_mux;
reg [ 35: 0] fifo_8;
wire fifo_8_enable;
wire [ 35: 0] fifo_8_mux;
reg [ 35: 0] fifo_9;
wire fifo_9_enable;
wire [ 35: 0] fifo_9_mux;
reg [ 4: 0] fifo_cnt /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
wire [ 4: 0] fifo_cnt_inc;
wire [ 35: 0] fifo_head;
reg [ 3: 0] fifo_rdptr /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
wire [ 35: 0] fifo_read_mux;
reg [ 3: 0] fifo_wrptr /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
wire [ 3: 0] fifo_wrptr_inc;
wire [ 3: 0] fifo_wrptr_plus1;
wire [ 3: 0] fifo_wrptr_plus2;
wire ge2_free;
wire ge3_free;
wire input_ge1;
wire input_ge2;
wire input_ge3;
wire [ 1: 0] input_tm_cnt;
wire itm_valid;
reg overflow_pending /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
wire [ 35: 0] overflow_pending_atm;
wire [ 35: 0] overflow_pending_dtm;
wire trc_this;
wire [ 35: 0] tw;
assign trc_this = trc_on | (dbrk_traceon & ~dbrk_traceoff) | dbrk_traceme;
assign itm_valid = |itm[35 : 32];
assign atm_valid = |atm[35 : 32] & trc_this;
assign dtm_valid = |dtm[35 : 32] & trc_this;
assign ge2_free = ~fifo_cnt[4];
assign ge3_free = ge2_free & ~&fifo_cnt[3 : 0];
assign empty = ~|fifo_cnt;
assign fifo_wrptr_plus1 = fifo_wrptr + 1;
assign fifo_wrptr_plus2 = fifo_wrptr + 2;
limbus_nios2_qsys_0_nios2_oci_compute_input_tm_cnt the_limbus_nios2_qsys_0_nios2_oci_compute_input_tm_cnt
(
.atm_valid (atm_valid),
.compute_input_tm_cnt (compute_input_tm_cnt),
.dtm_valid (dtm_valid),
.itm_valid (itm_valid)
);
assign input_tm_cnt = compute_input_tm_cnt;
limbus_nios2_qsys_0_nios2_oci_fifo_wrptr_inc the_limbus_nios2_qsys_0_nios2_oci_fifo_wrptr_inc
(
.fifo_wrptr_inc (fifo_wrptr_inc),
.ge2_free (ge2_free),
.ge3_free (ge3_free),
.input_tm_cnt (input_tm_cnt)
);
limbus_nios2_qsys_0_nios2_oci_fifo_cnt_inc the_limbus_nios2_qsys_0_nios2_oci_fifo_cnt_inc
(
.empty (empty),
.fifo_cnt_inc (fifo_cnt_inc),
.ge2_free (ge2_free),
.ge3_free (ge3_free),
.input_tm_cnt (input_tm_cnt)
);
limbus_nios2_qsys_0_oci_test_bench the_limbus_nios2_qsys_0_oci_test_bench
(
.dct_buffer (dct_buffer),
.dct_count (dct_count),
.test_ending (test_ending),
.test_has_ended (test_has_ended)
);
always @(posedge clk or negedge jrst_n)
begin
if (jrst_n == 0)
begin
fifo_rdptr <= 0;
fifo_wrptr <= 0;
fifo_cnt <= 0;
overflow_pending <= 1;
end
else
begin
fifo_wrptr <= fifo_wrptr + fifo_wrptr_inc;
fifo_cnt <= fifo_cnt + fifo_cnt_inc;
if (~empty)
fifo_rdptr <= fifo_rdptr + 1;
if (~trc_this || (~ge2_free & input_ge2) || (~ge3_free & input_ge3))
overflow_pending <= 1;
else if (atm_valid | dtm_valid)
overflow_pending <= 0;
end
end
assign fifo_head = fifo_read_mux;
assign tw = 0 ? { (empty ? 4'h0 : fifo_head[35 : 32]), fifo_head[31 : 0]} : itm;
assign fifo_0_enable = ((fifo_wrptr == 4'd0) && input_ge1) || (ge2_free && (fifo_wrptr_plus1== 4'd0) && input_ge2) ||(ge3_free && (fifo_wrptr_plus2== 4'd0) && input_ge3);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
fifo_0 <= 0;
else if (fifo_0_enable)
fifo_0 <= fifo_0_mux;
end
assign fifo_0_mux = (((fifo_wrptr == 4'd0) && itm_valid))? itm :
(((fifo_wrptr == 4'd0) && atm_valid))? overflow_pending_atm :
(((fifo_wrptr == 4'd0) && dtm_valid))? overflow_pending_dtm :
(((fifo_wrptr_plus1 == 4'd0) && (ge2_free & itm_valid & atm_valid)))? overflow_pending_atm :
(((fifo_wrptr_plus1 == 4'd0) && (ge2_free & itm_valid & dtm_valid)))? overflow_pending_dtm :
(((fifo_wrptr_plus1 == 4'd0) && (ge2_free & atm_valid & dtm_valid)))? overflow_pending_dtm :
overflow_pending_dtm;
assign fifo_1_enable = ((fifo_wrptr == 4'd1) && input_ge1) || (ge2_free && (fifo_wrptr_plus1== 4'd1) && input_ge2) ||(ge3_free && (fifo_wrptr_plus2== 4'd1) && input_ge3);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
fifo_1 <= 0;
else if (fifo_1_enable)
fifo_1 <= fifo_1_mux;
end
assign fifo_1_mux = (((fifo_wrptr == 4'd1) && itm_valid))? itm :
(((fifo_wrptr == 4'd1) && atm_valid))? overflow_pending_atm :
(((fifo_wrptr == 4'd1) && dtm_valid))? overflow_pending_dtm :
(((fifo_wrptr_plus1 == 4'd1) && (ge2_free & itm_valid & atm_valid)))? overflow_pending_atm :
(((fifo_wrptr_plus1 == 4'd1) && (ge2_free & itm_valid & dtm_valid)))? overflow_pending_dtm :
(((fifo_wrptr_plus1 == 4'd1) && (ge2_free & atm_valid & dtm_valid)))? overflow_pending_dtm :
overflow_pending_dtm;
assign fifo_2_enable = ((fifo_wrptr == 4'd2) && input_ge1) || (ge2_free && (fifo_wrptr_plus1== 4'd2) && input_ge2) ||(ge3_free && (fifo_wrptr_plus2== 4'd2) && input_ge3);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
fifo_2 <= 0;
else if (fifo_2_enable)
fifo_2 <= fifo_2_mux;
end
assign fifo_2_mux = (((fifo_wrptr == 4'd2) && itm_valid))? itm :
(((fifo_wrptr == 4'd2) && atm_valid))? overflow_pending_atm :
(((fifo_wrptr == 4'd2) && dtm_valid))? overflow_pending_dtm :
(((fifo_wrptr_plus1 == 4'd2) && (ge2_free & itm_valid & atm_valid)))? overflow_pending_atm :
(((fifo_wrptr_plus1 == 4'd2) && (ge2_free & itm_valid & dtm_valid)))? overflow_pending_dtm :
(((fifo_wrptr_plus1 == 4'd2) && (ge2_free & atm_valid & dtm_valid)))? overflow_pending_dtm :
overflow_pending_dtm;
assign fifo_3_enable = ((fifo_wrptr == 4'd3) && input_ge1) || (ge2_free && (fifo_wrptr_plus1== 4'd3) && input_ge2) ||(ge3_free && (fifo_wrptr_plus2== 4'd3) && input_ge3);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
fifo_3 <= 0;
else if (fifo_3_enable)
fifo_3 <= fifo_3_mux;
end
assign fifo_3_mux = (((fifo_wrptr == 4'd3) && itm_valid))? itm :
(((fifo_wrptr == 4'd3) && atm_valid))? overflow_pending_atm :
(((fifo_wrptr == 4'd3) && dtm_valid))? overflow_pending_dtm :
(((fifo_wrptr_plus1 == 4'd3) && (ge2_free & itm_valid & atm_valid)))? overflow_pending_atm :
(((fifo_wrptr_plus1 == 4'd3) && (ge2_free & itm_valid & dtm_valid)))? overflow_pending_dtm :
(((fifo_wrptr_plus1 == 4'd3) && (ge2_free & atm_valid & dtm_valid)))? overflow_pending_dtm :
overflow_pending_dtm;
assign fifo_4_enable = ((fifo_wrptr == 4'd4) && input_ge1) || (ge2_free && (fifo_wrptr_plus1== 4'd4) && input_ge2) ||(ge3_free && (fifo_wrptr_plus2== 4'd4) && input_ge3);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
fifo_4 <= 0;
else if (fifo_4_enable)
fifo_4 <= fifo_4_mux;
end
assign fifo_4_mux = (((fifo_wrptr == 4'd4) && itm_valid))? itm :
(((fifo_wrptr == 4'd4) && atm_valid))? overflow_pending_atm :
(((fifo_wrptr == 4'd4) && dtm_valid))? overflow_pending_dtm :
(((fifo_wrptr_plus1 == 4'd4) && (ge2_free & itm_valid & atm_valid)))? overflow_pending_atm :
(((fifo_wrptr_plus1 == 4'd4) && (ge2_free & itm_valid & dtm_valid)))? overflow_pending_dtm :
(((fifo_wrptr_plus1 == 4'd4) && (ge2_free & atm_valid & dtm_valid)))? overflow_pending_dtm :
overflow_pending_dtm;
assign fifo_5_enable = ((fifo_wrptr == 4'd5) && input_ge1) || (ge2_free && (fifo_wrptr_plus1== 4'd5) && input_ge2) ||(ge3_free && (fifo_wrptr_plus2== 4'd5) && input_ge3);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
fifo_5 <= 0;
else if (fifo_5_enable)
fifo_5 <= fifo_5_mux;
end
assign fifo_5_mux = (((fifo_wrptr == 4'd5) && itm_valid))? itm :
(((fifo_wrptr == 4'd5) && atm_valid))? overflow_pending_atm :
(((fifo_wrptr == 4'd5) && dtm_valid))? overflow_pending_dtm :
(((fifo_wrptr_plus1 == 4'd5) && (ge2_free & itm_valid & atm_valid)))? overflow_pending_atm :
(((fifo_wrptr_plus1 == 4'd5) && (ge2_free & itm_valid & dtm_valid)))? overflow_pending_dtm :
(((fifo_wrptr_plus1 == 4'd5) && (ge2_free & atm_valid & dtm_valid)))? overflow_pending_dtm :
overflow_pending_dtm;
assign fifo_6_enable = ((fifo_wrptr == 4'd6) && input_ge1) || (ge2_free && (fifo_wrptr_plus1== 4'd6) && input_ge2) ||(ge3_free && (fifo_wrptr_plus2== 4'd6) && input_ge3);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
fifo_6 <= 0;
else if (fifo_6_enable)
fifo_6 <= fifo_6_mux;
end
assign fifo_6_mux = (((fifo_wrptr == 4'd6) && itm_valid))? itm :
(((fifo_wrptr == 4'd6) && atm_valid))? overflow_pending_atm :
(((fifo_wrptr == 4'd6) && dtm_valid))? overflow_pending_dtm :
(((fifo_wrptr_plus1 == 4'd6) && (ge2_free & itm_valid & atm_valid)))? overflow_pending_atm :
(((fifo_wrptr_plus1 == 4'd6) && (ge2_free & itm_valid & dtm_valid)))? overflow_pending_dtm :
(((fifo_wrptr_plus1 == 4'd6) && (ge2_free & atm_valid & dtm_valid)))? overflow_pending_dtm :
overflow_pending_dtm;
assign fifo_7_enable = ((fifo_wrptr == 4'd7) && input_ge1) || (ge2_free && (fifo_wrptr_plus1== 4'd7) && input_ge2) ||(ge3_free && (fifo_wrptr_plus2== 4'd7) && input_ge3);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
fifo_7 <= 0;
else if (fifo_7_enable)
fifo_7 <= fifo_7_mux;
end
assign fifo_7_mux = (((fifo_wrptr == 4'd7) && itm_valid))? itm :
(((fifo_wrptr == 4'd7) && atm_valid))? overflow_pending_atm :
(((fifo_wrptr == 4'd7) && dtm_valid))? overflow_pending_dtm :
(((fifo_wrptr_plus1 == 4'd7) && (ge2_free & itm_valid & atm_valid)))? overflow_pending_atm :
(((fifo_wrptr_plus1 == 4'd7) && (ge2_free & itm_valid & dtm_valid)))? overflow_pending_dtm :
(((fifo_wrptr_plus1 == 4'd7) && (ge2_free & atm_valid & dtm_valid)))? overflow_pending_dtm :
overflow_pending_dtm;
assign fifo_8_enable = ((fifo_wrptr == 4'd8) && input_ge1) || (ge2_free && (fifo_wrptr_plus1== 4'd8) && input_ge2) ||(ge3_free && (fifo_wrptr_plus2== 4'd8) && input_ge3);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
fifo_8 <= 0;
else if (fifo_8_enable)
fifo_8 <= fifo_8_mux;
end
assign fifo_8_mux = (((fifo_wrptr == 4'd8) && itm_valid))? itm :
(((fifo_wrptr == 4'd8) && atm_valid))? overflow_pending_atm :
(((fifo_wrptr == 4'd8) && dtm_valid))? overflow_pending_dtm :
(((fifo_wrptr_plus1 == 4'd8) && (ge2_free & itm_valid & atm_valid)))? overflow_pending_atm :
(((fifo_wrptr_plus1 == 4'd8) && (ge2_free & itm_valid & dtm_valid)))? overflow_pending_dtm :
(((fifo_wrptr_plus1 == 4'd8) && (ge2_free & atm_valid & dtm_valid)))? overflow_pending_dtm :
overflow_pending_dtm;
assign fifo_9_enable = ((fifo_wrptr == 4'd9) && input_ge1) || (ge2_free && (fifo_wrptr_plus1== 4'd9) && input_ge2) ||(ge3_free && (fifo_wrptr_plus2== 4'd9) && input_ge3);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
fifo_9 <= 0;
else if (fifo_9_enable)
fifo_9 <= fifo_9_mux;
end
assign fifo_9_mux = (((fifo_wrptr == 4'd9) && itm_valid))? itm :
(((fifo_wrptr == 4'd9) && atm_valid))? overflow_pending_atm :
(((fifo_wrptr == 4'd9) && dtm_valid))? overflow_pending_dtm :
(((fifo_wrptr_plus1 == 4'd9) && (ge2_free & itm_valid & atm_valid)))? overflow_pending_atm :
(((fifo_wrptr_plus1 == 4'd9) && (ge2_free & itm_valid & dtm_valid)))? overflow_pending_dtm :
(((fifo_wrptr_plus1 == 4'd9) && (ge2_free & atm_valid & dtm_valid)))? overflow_pending_dtm :
overflow_pending_dtm;
assign fifo_10_enable = ((fifo_wrptr == 4'd10) && input_ge1) || (ge2_free && (fifo_wrptr_plus1== 4'd10) && input_ge2) ||(ge3_free && (fifo_wrptr_plus2== 4'd10) && input_ge3);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
fifo_10 <= 0;
else if (fifo_10_enable)
fifo_10 <= fifo_10_mux;
end
assign fifo_10_mux = (((fifo_wrptr == 4'd10) && itm_valid))? itm :
(((fifo_wrptr == 4'd10) && atm_valid))? overflow_pending_atm :
(((fifo_wrptr == 4'd10) && dtm_valid))? overflow_pending_dtm :
(((fifo_wrptr_plus1 == 4'd10) && (ge2_free & itm_valid & atm_valid)))? overflow_pending_atm :
(((fifo_wrptr_plus1 == 4'd10) && (ge2_free & itm_valid & dtm_valid)))? overflow_pending_dtm :
(((fifo_wrptr_plus1 == 4'd10) && (ge2_free & atm_valid & dtm_valid)))? overflow_pending_dtm :
overflow_pending_dtm;
assign fifo_11_enable = ((fifo_wrptr == 4'd11) && input_ge1) || (ge2_free && (fifo_wrptr_plus1== 4'd11) && input_ge2) ||(ge3_free && (fifo_wrptr_plus2== 4'd11) && input_ge3);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
fifo_11 <= 0;
else if (fifo_11_enable)
fifo_11 <= fifo_11_mux;
end
assign fifo_11_mux = (((fifo_wrptr == 4'd11) && itm_valid))? itm :
(((fifo_wrptr == 4'd11) && atm_valid))? overflow_pending_atm :
(((fifo_wrptr == 4'd11) && dtm_valid))? overflow_pending_dtm :
(((fifo_wrptr_plus1 == 4'd11) && (ge2_free & itm_valid & atm_valid)))? overflow_pending_atm :
(((fifo_wrptr_plus1 == 4'd11) && (ge2_free & itm_valid & dtm_valid)))? overflow_pending_dtm :
(((fifo_wrptr_plus1 == 4'd11) && (ge2_free & atm_valid & dtm_valid)))? overflow_pending_dtm :
overflow_pending_dtm;
assign fifo_12_enable = ((fifo_wrptr == 4'd12) && input_ge1) || (ge2_free && (fifo_wrptr_plus1== 4'd12) && input_ge2) ||(ge3_free && (fifo_wrptr_plus2== 4'd12) && input_ge3);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
fifo_12 <= 0;
else if (fifo_12_enable)
fifo_12 <= fifo_12_mux;
end
assign fifo_12_mux = (((fifo_wrptr == 4'd12) && itm_valid))? itm :
(((fifo_wrptr == 4'd12) && atm_valid))? overflow_pending_atm :
(((fifo_wrptr == 4'd12) && dtm_valid))? overflow_pending_dtm :
(((fifo_wrptr_plus1 == 4'd12) && (ge2_free & itm_valid & atm_valid)))? overflow_pending_atm :
(((fifo_wrptr_plus1 == 4'd12) && (ge2_free & itm_valid & dtm_valid)))? overflow_pending_dtm :
(((fifo_wrptr_plus1 == 4'd12) && (ge2_free & atm_valid & dtm_valid)))? overflow_pending_dtm :
overflow_pending_dtm;
assign fifo_13_enable = ((fifo_wrptr == 4'd13) && input_ge1) || (ge2_free && (fifo_wrptr_plus1== 4'd13) && input_ge2) ||(ge3_free && (fifo_wrptr_plus2== 4'd13) && input_ge3);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
fifo_13 <= 0;
else if (fifo_13_enable)
fifo_13 <= fifo_13_mux;
end
assign fifo_13_mux = (((fifo_wrptr == 4'd13) && itm_valid))? itm :
(((fifo_wrptr == 4'd13) && atm_valid))? overflow_pending_atm :
(((fifo_wrptr == 4'd13) && dtm_valid))? overflow_pending_dtm :
(((fifo_wrptr_plus1 == 4'd13) && (ge2_free & itm_valid & atm_valid)))? overflow_pending_atm :
(((fifo_wrptr_plus1 == 4'd13) && (ge2_free & itm_valid & dtm_valid)))? overflow_pending_dtm :
(((fifo_wrptr_plus1 == 4'd13) && (ge2_free & atm_valid & dtm_valid)))? overflow_pending_dtm :
overflow_pending_dtm;
assign fifo_14_enable = ((fifo_wrptr == 4'd14) && input_ge1) || (ge2_free && (fifo_wrptr_plus1== 4'd14) && input_ge2) ||(ge3_free && (fifo_wrptr_plus2== 4'd14) && input_ge3);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
fifo_14 <= 0;
else if (fifo_14_enable)
fifo_14 <= fifo_14_mux;
end
assign fifo_14_mux = (((fifo_wrptr == 4'd14) && itm_valid))? itm :
(((fifo_wrptr == 4'd14) && atm_valid))? overflow_pending_atm :
(((fifo_wrptr == 4'd14) && dtm_valid))? overflow_pending_dtm :
(((fifo_wrptr_plus1 == 4'd14) && (ge2_free & itm_valid & atm_valid)))? overflow_pending_atm :
(((fifo_wrptr_plus1 == 4'd14) && (ge2_free & itm_valid & dtm_valid)))? overflow_pending_dtm :
(((fifo_wrptr_plus1 == 4'd14) && (ge2_free & atm_valid & dtm_valid)))? overflow_pending_dtm :
overflow_pending_dtm;
assign fifo_15_enable = ((fifo_wrptr == 4'd15) && input_ge1) || (ge2_free && (fifo_wrptr_plus1== 4'd15) && input_ge2) ||(ge3_free && (fifo_wrptr_plus2== 4'd15) && input_ge3);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
fifo_15 <= 0;
else if (fifo_15_enable)
fifo_15 <= fifo_15_mux;
end
assign fifo_15_mux = (((fifo_wrptr == 4'd15) && itm_valid))? itm :
(((fifo_wrptr == 4'd15) && atm_valid))? overflow_pending_atm :
(((fifo_wrptr == 4'd15) && dtm_valid))? overflow_pending_dtm :
(((fifo_wrptr_plus1 == 4'd15) && (ge2_free & itm_valid & atm_valid)))? overflow_pending_atm :
(((fifo_wrptr_plus1 == 4'd15) && (ge2_free & itm_valid & dtm_valid)))? overflow_pending_dtm :
(((fifo_wrptr_plus1 == 4'd15) && (ge2_free & atm_valid & dtm_valid)))? overflow_pending_dtm :
overflow_pending_dtm;
assign input_ge1 = |input_tm_cnt;
assign input_ge2 = input_tm_cnt[1];
assign input_ge3 = &input_tm_cnt;
assign overflow_pending_atm = {overflow_pending, atm[34 : 0]};
assign overflow_pending_dtm = {overflow_pending, dtm[34 : 0]};
assign fifo_read_mux = (fifo_rdptr == 4'd0)? fifo_0 :
(fifo_rdptr == 4'd1)? fifo_1 :
(fifo_rdptr == 4'd2)? fifo_2 :
(fifo_rdptr == 4'd3)? fifo_3 :
(fifo_rdptr == 4'd4)? fifo_4 :
(fifo_rdptr == 4'd5)? fifo_5 :
(fifo_rdptr == 4'd6)? fifo_6 :
(fifo_rdptr == 4'd7)? fifo_7 :
(fifo_rdptr == 4'd8)? fifo_8 :
(fifo_rdptr == 4'd9)? fifo_9 :
(fifo_rdptr == 4'd10)? fifo_10 :
(fifo_rdptr == 4'd11)? fifo_11 :
(fifo_rdptr == 4'd12)? fifo_12 :
(fifo_rdptr == 4'd13)? fifo_13 :
(fifo_rdptr == 4'd14)? fifo_14 :
fifo_15;
endmodule
|
module limbus_nios2_qsys_0_nios2_oci_pib (
// inputs:
clk,
clkx2,
jrst_n,
tw,
// outputs:
tr_clk,
tr_data
)
;
output tr_clk;
output [ 17: 0] tr_data;
input clk;
input clkx2;
input jrst_n;
input [ 35: 0] tw;
wire phase;
wire tr_clk;
reg tr_clk_reg /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
wire [ 17: 0] tr_data;
reg [ 17: 0] tr_data_reg /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
reg x1 /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
reg x2 /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
assign phase = x1^x2;
always @(posedge clk or negedge jrst_n)
begin
if (jrst_n == 0)
x1 <= 0;
else
x1 <= ~x1;
end
always @(posedge clkx2 or negedge jrst_n)
begin
if (jrst_n == 0)
begin
x2 <= 0;
tr_clk_reg <= 0;
tr_data_reg <= 0;
end
else
begin
x2 <= x1;
tr_clk_reg <= ~phase;
tr_data_reg <= phase ? tw[17 : 0] : tw[35 : 18];
end
end
assign tr_clk = 0 ? tr_clk_reg : 0;
assign tr_data = 0 ? tr_data_reg : 0;
endmodule
|
module limbus_nios2_qsys_0_nios2_oci_im (
// inputs:
clk,
jdo,
jrst_n,
reset_n,
take_action_tracectrl,
take_action_tracemem_a,
take_action_tracemem_b,
take_no_action_tracemem_a,
trc_ctrl,
tw,
// outputs:
tracemem_on,
tracemem_trcdata,
tracemem_tw,
trc_enb,
trc_im_addr,
trc_wrap,
xbrk_wrap_traceoff
)
;
output tracemem_on;
output [ 35: 0] tracemem_trcdata;
output tracemem_tw;
output trc_enb;
output [ 6: 0] trc_im_addr;
output trc_wrap;
output xbrk_wrap_traceoff;
input clk;
input [ 37: 0] jdo;
input jrst_n;
input reset_n;
input take_action_tracectrl;
input take_action_tracemem_a;
input take_action_tracemem_b;
input take_no_action_tracemem_a;
input [ 15: 0] trc_ctrl;
input [ 35: 0] tw;
wire tracemem_on;
wire [ 35: 0] tracemem_trcdata;
wire tracemem_tw;
wire trc_enb;
reg [ 6: 0] trc_im_addr /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */;
wire [ 35: 0] trc_im_data;
reg [ 16: 0] trc_jtag_addr /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=D101" */;
wire trc_on_chip;
reg trc_wrap /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */;
wire tw_valid;
wire xbrk_wrap_traceoff;
assign trc_im_data = tw;
always @(posedge clk or negedge jrst_n)
begin
if (jrst_n == 0)
begin
trc_im_addr <= 0;
trc_wrap <= 0;
end
else if (!0)
begin
trc_im_addr <= 0;
trc_wrap <= 0;
end
else if (take_action_tracectrl &&
(jdo[4] | jdo[3]))
begin
if (jdo[4])
trc_im_addr <= 0;
if (jdo[3])
trc_wrap <= 0;
end
else if (trc_enb & trc_on_chip & tw_valid)
begin
trc_im_addr <= trc_im_addr+1;
if (&trc_im_addr)
trc_wrap <= 1;
end
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
trc_jtag_addr <= 0;
else if (take_action_tracemem_a ||
take_no_action_tracemem_a ||
take_action_tracemem_b)
trc_jtag_addr <= take_action_tracemem_a ?
jdo[35 : 19] :
trc_jtag_addr + 1;
end
assign trc_enb = trc_ctrl[0];
assign trc_on_chip = ~trc_ctrl[8];
assign tw_valid = |trc_im_data[35 : 32];
assign xbrk_wrap_traceoff = trc_ctrl[10] & trc_wrap;
assign tracemem_tw = trc_wrap;
assign tracemem_on = trc_enb;
assign tracemem_trcdata = 0;
endmodule
|
module limbus_nios2_qsys_0_nios2_performance_monitors
;
endmodule
|
module limbus_nios2_qsys_0_nios2_oci (
// inputs:
D_valid,
E_st_data,
E_valid,
F_pc,
address_nxt,
av_ld_data_aligned_filtered,
byteenable_nxt,
clk,
d_address,
d_read,
d_waitrequest,
d_write,
debugaccess_nxt,
hbreak_enabled,
read_nxt,
reset,
reset_n,
reset_req,
test_ending,
test_has_ended,
write_nxt,
writedata_nxt,
// outputs:
jtag_debug_module_debugaccess_to_roms,
oci_hbreak_req,
oci_ienable,
oci_single_step_mode,
readdata,
resetrequest,
waitrequest
)
;
output jtag_debug_module_debugaccess_to_roms;
output oci_hbreak_req;
output [ 31: 0] oci_ienable;
output oci_single_step_mode;
output [ 31: 0] readdata;
output resetrequest;
output waitrequest;
input D_valid;
input [ 31: 0] E_st_data;
input E_valid;
input [ 26: 0] F_pc;
input [ 8: 0] address_nxt;
input [ 31: 0] av_ld_data_aligned_filtered;
input [ 3: 0] byteenable_nxt;
input clk;
input [ 28: 0] d_address;
input d_read;
input d_waitrequest;
input d_write;
input debugaccess_nxt;
input hbreak_enabled;
input read_nxt;
input reset;
input reset_n;
input reset_req;
input test_ending;
input test_has_ended;
input write_nxt;
input [ 31: 0] writedata_nxt;
wire [ 31: 0] MonDReg;
reg [ 8: 0] address;
wire [ 35: 0] atm;
wire [ 31: 0] break_readreg;
reg [ 3: 0] byteenable;
wire clkx2;
wire [ 28: 0] cpu_d_address;
wire cpu_d_read;
wire [ 31: 0] cpu_d_readdata;
wire cpu_d_wait;
wire cpu_d_write;
wire [ 31: 0] cpu_d_writedata;
wire dbrk_break;
wire dbrk_goto0;
wire dbrk_goto1;
wire dbrk_hit0_latch;
wire dbrk_hit1_latch;
wire dbrk_hit2_latch;
wire dbrk_hit3_latch;
wire dbrk_traceme;
wire dbrk_traceoff;
wire dbrk_traceon;
wire dbrk_trigout;
wire [ 29: 0] dct_buffer;
wire [ 3: 0] dct_count;
reg debugaccess;
wire debugack;
wire debugreq;
wire [ 35: 0] dtm;
wire dummy_sink;
wire [ 35: 0] itm;
wire [ 37: 0] jdo;
wire jrst_n;
wire jtag_debug_module_debugaccess_to_roms;
wire monitor_error;
wire monitor_go;
wire monitor_ready;
wire oci_hbreak_req;
wire [ 31: 0] oci_ienable;
wire [ 31: 0] oci_reg_readdata;
wire oci_single_step_mode;
wire [ 31: 0] ociram_readdata;
wire ocireg_ers;
wire ocireg_mrs;
reg read;
reg [ 31: 0] readdata;
wire resetlatch;
wire resetrequest;
wire st_ready_test_idle;
wire take_action_break_a;
wire take_action_break_b;
wire take_action_break_c;
wire take_action_ocimem_a;
wire take_action_ocimem_b;
wire take_action_ocireg;
wire take_action_tracectrl;
wire take_action_tracemem_a;
wire take_action_tracemem_b;
wire take_no_action_break_a;
wire take_no_action_break_b;
wire take_no_action_break_c;
wire take_no_action_ocimem_a;
wire take_no_action_tracemem_a;
wire tr_clk;
wire [ 17: 0] tr_data;
wire tracemem_on;
wire [ 35: 0] tracemem_trcdata;
wire tracemem_tw;
wire [ 15: 0] trc_ctrl;
wire trc_enb;
wire [ 6: 0] trc_im_addr;
wire trc_on;
wire trc_wrap;
wire trigbrktype;
wire trigger_state_0;
wire trigger_state_1;
wire trigout;
wire [ 35: 0] tw;
wire waitrequest;
reg write;
reg [ 31: 0] writedata;
wire xbrk_break;
wire [ 7: 0] xbrk_ctrl0;
wire [ 7: 0] xbrk_ctrl1;
wire [ 7: 0] xbrk_ctrl2;
wire [ 7: 0] xbrk_ctrl3;
wire xbrk_goto0;
wire xbrk_goto1;
wire xbrk_traceoff;
wire xbrk_traceon;
wire xbrk_trigout;
wire xbrk_wrap_traceoff;
limbus_nios2_qsys_0_nios2_oci_debug the_limbus_nios2_qsys_0_nios2_oci_debug
(
.clk (clk),
.dbrk_break (dbrk_break),
.debugack (debugack),
.debugreq (debugreq),
.hbreak_enabled (hbreak_enabled),
.jdo (jdo),
.jrst_n (jrst_n),
.monitor_error (monitor_error),
.monitor_go (monitor_go),
.monitor_ready (monitor_ready),
.oci_hbreak_req (oci_hbreak_req),
.ocireg_ers (ocireg_ers),
.ocireg_mrs (ocireg_mrs),
.reset (reset),
.resetlatch (resetlatch),
.resetrequest (resetrequest),
.st_ready_test_idle (st_ready_test_idle),
.take_action_ocimem_a (take_action_ocimem_a),
.take_action_ocireg (take_action_ocireg),
.xbrk_break (xbrk_break)
);
limbus_nios2_qsys_0_nios2_ocimem the_limbus_nios2_qsys_0_nios2_ocimem
(
.MonDReg (MonDReg),
.address (address),
.byteenable (byteenable),
.clk (clk),
.debugaccess (debugaccess),
.jdo (jdo),
.jrst_n (jrst_n),
.ociram_readdata (ociram_readdata),
.read (read),
.reset_req (reset_req),
.take_action_ocimem_a (take_action_ocimem_a),
.take_action_ocimem_b (take_action_ocimem_b),
.take_no_action_ocimem_a (take_no_action_ocimem_a),
.waitrequest (waitrequest),
.write (write),
.writedata (writedata)
);
limbus_nios2_qsys_0_nios2_avalon_reg the_limbus_nios2_qsys_0_nios2_avalon_reg
(
.address (address),
.clk (clk),
.debugaccess (debugaccess),
.monitor_error (monitor_error),
.monitor_go (monitor_go),
.monitor_ready (monitor_ready),
.oci_ienable (oci_ienable),
.oci_reg_readdata (oci_reg_readdata),
.oci_single_step_mode (oci_single_step_mode),
.ocireg_ers (ocireg_ers),
.ocireg_mrs (ocireg_mrs),
.reset_n (reset_n),
.take_action_ocireg (take_action_ocireg),
.write (write),
.writedata (writedata)
);
limbus_nios2_qsys_0_nios2_oci_break the_limbus_nios2_qsys_0_nios2_oci_break
(
.break_readreg (break_readreg),
.clk (clk),
.dbrk_break (dbrk_break),
.dbrk_goto0 (dbrk_goto0),
.dbrk_goto1 (dbrk_goto1),
.dbrk_hit0_latch (dbrk_hit0_latch),
.dbrk_hit1_latch (dbrk_hit1_latch),
.dbrk_hit2_latch (dbrk_hit2_latch),
.dbrk_hit3_latch (dbrk_hit3_latch),
.jdo (jdo),
.jrst_n (jrst_n),
.reset_n (reset_n),
.take_action_break_a (take_action_break_a),
.take_action_break_b (take_action_break_b),
.take_action_break_c (take_action_break_c),
.take_no_action_break_a (take_no_action_break_a),
.take_no_action_break_b (take_no_action_break_b),
.take_no_action_break_c (take_no_action_break_c),
.trigbrktype (trigbrktype),
.trigger_state_0 (trigger_state_0),
.trigger_state_1 (trigger_state_1),
.xbrk_ctrl0 (xbrk_ctrl0),
.xbrk_ctrl1 (xbrk_ctrl1),
.xbrk_ctrl2 (xbrk_ctrl2),
.xbrk_ctrl3 (xbrk_ctrl3),
.xbrk_goto0 (xbrk_goto0),
.xbrk_goto1 (xbrk_goto1)
);
limbus_nios2_qsys_0_nios2_oci_xbrk the_limbus_nios2_qsys_0_nios2_oci_xbrk
(
.D_valid (D_valid),
.E_valid (E_valid),
.F_pc (F_pc),
.clk (clk),
.reset_n (reset_n),
.trigger_state_0 (trigger_state_0),
.trigger_state_1 (trigger_state_1),
.xbrk_break (xbrk_break),
.xbrk_ctrl0 (xbrk_ctrl0),
.xbrk_ctrl1 (xbrk_ctrl1),
.xbrk_ctrl2 (xbrk_ctrl2),
.xbrk_ctrl3 (xbrk_ctrl3),
.xbrk_goto0 (xbrk_goto0),
.xbrk_goto1 (xbrk_goto1),
.xbrk_traceoff (xbrk_traceoff),
.xbrk_traceon (xbrk_traceon),
.xbrk_trigout (xbrk_trigout)
);
limbus_nios2_qsys_0_nios2_oci_dbrk the_limbus_nios2_qsys_0_nios2_oci_dbrk
(
.E_st_data (E_st_data),
.av_ld_data_aligned_filtered (av_ld_data_aligned_filtered),
.clk (clk),
.cpu_d_address (cpu_d_address),
.cpu_d_read (cpu_d_read),
.cpu_d_readdata (cpu_d_readdata),
.cpu_d_wait (cpu_d_wait),
.cpu_d_write (cpu_d_write),
.cpu_d_writedata (cpu_d_writedata),
.d_address (d_address),
.d_read (d_read),
.d_waitrequest (d_waitrequest),
.d_write (d_write),
.dbrk_break (dbrk_break),
.dbrk_goto0 (dbrk_goto0),
.dbrk_goto1 (dbrk_goto1),
.dbrk_traceme (dbrk_traceme),
.dbrk_traceoff (dbrk_traceoff),
.dbrk_traceon (dbrk_traceon),
.dbrk_trigout (dbrk_trigout),
.debugack (debugack),
.reset_n (reset_n)
);
limbus_nios2_qsys_0_nios2_oci_itrace the_limbus_nios2_qsys_0_nios2_oci_itrace
(
.clk (clk),
.dbrk_traceoff (dbrk_traceoff),
.dbrk_traceon (dbrk_traceon),
.dct_buffer (dct_buffer),
.dct_count (dct_count),
.itm (itm),
.jdo (jdo),
.jrst_n (jrst_n),
.take_action_tracectrl (take_action_tracectrl),
.trc_ctrl (trc_ctrl),
.trc_enb (trc_enb),
.trc_on (trc_on),
.xbrk_traceoff (xbrk_traceoff),
.xbrk_traceon (xbrk_traceon),
.xbrk_wrap_traceoff (xbrk_wrap_traceoff)
);
limbus_nios2_qsys_0_nios2_oci_dtrace the_limbus_nios2_qsys_0_nios2_oci_dtrace
(
.atm (atm),
.clk (clk),
.cpu_d_address (cpu_d_address),
.cpu_d_read (cpu_d_read),
.cpu_d_readdata (cpu_d_readdata),
.cpu_d_wait (cpu_d_wait),
.cpu_d_write (cpu_d_write),
.cpu_d_writedata (cpu_d_writedata),
.dtm (dtm),
.jrst_n (jrst_n),
.trc_ctrl (trc_ctrl)
);
limbus_nios2_qsys_0_nios2_oci_fifo the_limbus_nios2_qsys_0_nios2_oci_fifo
(
.atm (atm),
.clk (clk),
.dbrk_traceme (dbrk_traceme),
.dbrk_traceoff (dbrk_traceoff),
.dbrk_traceon (dbrk_traceon),
.dct_buffer (dct_buffer),
.dct_count (dct_count),
.dtm (dtm),
.itm (itm),
.jrst_n (jrst_n),
.reset_n (reset_n),
.test_ending (test_ending),
.test_has_ended (test_has_ended),
.trc_on (trc_on),
.tw (tw)
);
limbus_nios2_qsys_0_nios2_oci_pib the_limbus_nios2_qsys_0_nios2_oci_pib
(
.clk (clk),
.clkx2 (clkx2),
.jrst_n (jrst_n),
.tr_clk (tr_clk),
.tr_data (tr_data),
.tw (tw)
);
limbus_nios2_qsys_0_nios2_oci_im the_limbus_nios2_qsys_0_nios2_oci_im
(
.clk (clk),
.jdo (jdo),
.jrst_n (jrst_n),
.reset_n (reset_n),
.take_action_tracectrl (take_action_tracectrl),
.take_action_tracemem_a (take_action_tracemem_a),
.take_action_tracemem_b (take_action_tracemem_b),
.take_no_action_tracemem_a (take_no_action_tracemem_a),
.tracemem_on (tracemem_on),
.tracemem_trcdata (tracemem_trcdata),
.tracemem_tw (tracemem_tw),
.trc_ctrl (trc_ctrl),
.trc_enb (trc_enb),
.trc_im_addr (trc_im_addr),
.trc_wrap (trc_wrap),
.tw (tw),
.xbrk_wrap_traceoff (xbrk_wrap_traceoff)
);
assign trigout = dbrk_trigout | xbrk_trigout;
assign jtag_debug_module_debugaccess_to_roms = debugack;
always @(posedge clk or negedge jrst_n)
begin
if (jrst_n == 0)
address <= 0;
else
address <= address_nxt;
end
always @(posedge clk or negedge jrst_n)
begin
if (jrst_n == 0)
byteenable <= 0;
else
byteenable <= byteenable_nxt;
end
always @(posedge clk or negedge jrst_n)
begin
if (jrst_n == 0)
writedata <= 0;
else
writedata <= writedata_nxt;
end
always @(posedge clk or negedge jrst_n)
begin
if (jrst_n == 0)
debugaccess <= 0;
else
debugaccess <= debugaccess_nxt;
end
always @(posedge clk or negedge jrst_n)
begin
if (jrst_n == 0)
read <= 0;
else
read <= read ? waitrequest : read_nxt;
end
always @(posedge clk or negedge jrst_n)
begin
if (jrst_n == 0)
write <= 0;
else
write <= write ? waitrequest : write_nxt;
end
always @(posedge clk or negedge jrst_n)
begin
if (jrst_n == 0)
readdata <= 0;
else
readdata <= address[8] ? oci_reg_readdata : ociram_readdata;
end
limbus_nios2_qsys_0_jtag_debug_module_wrapper the_limbus_nios2_qsys_0_jtag_debug_module_wrapper
(
.MonDReg (MonDReg),
.break_readreg (break_readreg),
.clk (clk),
.dbrk_hit0_latch (dbrk_hit0_latch),
.dbrk_hit1_latch (dbrk_hit1_latch),
.dbrk_hit2_latch (dbrk_hit2_latch),
.dbrk_hit3_latch (dbrk_hit3_latch),
.debugack (debugack),
.jdo (jdo),
.jrst_n (jrst_n),
.monitor_error (monitor_error),
.monitor_ready (monitor_ready),
.reset_n (reset_n),
.resetlatch (resetlatch),
.st_ready_test_idle (st_ready_test_idle),
.take_action_break_a (take_action_break_a),
.take_action_break_b (take_action_break_b),
.take_action_break_c (take_action_break_c),
.take_action_ocimem_a (take_action_ocimem_a),
.take_action_ocimem_b (take_action_ocimem_b),
.take_action_tracectrl (take_action_tracectrl),
.take_action_tracemem_a (take_action_tracemem_a),
.take_action_tracemem_b (take_action_tracemem_b),
.take_no_action_break_a (take_no_action_break_a),
.take_no_action_break_b (take_no_action_break_b),
.take_no_action_break_c (take_no_action_break_c),
.take_no_action_ocimem_a (take_no_action_ocimem_a),
.take_no_action_tracemem_a (take_no_action_tracemem_a),
.tracemem_on (tracemem_on),
.tracemem_trcdata (tracemem_trcdata),
.tracemem_tw (tracemem_tw),
.trc_im_addr (trc_im_addr),
.trc_on (trc_on),
.trc_wrap (trc_wrap),
.trigbrktype (trigbrktype),
.trigger_state_1 (trigger_state_1)
);
//dummy sink, which is an e_mux
assign dummy_sink = tr_clk |
tr_data |
trigout |
debugack;
assign debugreq = 0;
assign clkx2 = 0;
endmodule
|
module limbus_nios2_qsys_0 (
// inputs:
clk,
d_irq,
d_readdata,
d_waitrequest,
i_readdata,
i_waitrequest,
jtag_debug_module_address,
jtag_debug_module_byteenable,
jtag_debug_module_debugaccess,
jtag_debug_module_read,
jtag_debug_module_write,
jtag_debug_module_writedata,
reset_n,
reset_req,
// outputs:
d_address,
d_byteenable,
d_read,
d_write,
d_writedata,
i_address,
i_read,
jtag_debug_module_debugaccess_to_roms,
jtag_debug_module_readdata,
jtag_debug_module_resetrequest,
jtag_debug_module_waitrequest,
no_ci_readra
)
;
output [ 28: 0] d_address;
output [ 3: 0] d_byteenable;
output d_read;
output d_write;
output [ 31: 0] d_writedata;
output [ 28: 0] i_address;
output i_read;
output jtag_debug_module_debugaccess_to_roms;
output [ 31: 0] jtag_debug_module_readdata;
output jtag_debug_module_resetrequest;
output jtag_debug_module_waitrequest;
output no_ci_readra;
input clk;
input [ 31: 0] d_irq;
input [ 31: 0] d_readdata;
input d_waitrequest;
input [ 31: 0] i_readdata;
input i_waitrequest;
input [ 8: 0] jtag_debug_module_address;
input [ 3: 0] jtag_debug_module_byteenable;
input jtag_debug_module_debugaccess;
input jtag_debug_module_read;
input jtag_debug_module_write;
input [ 31: 0] jtag_debug_module_writedata;
input reset_n;
input reset_req;
wire [ 1: 0] D_compare_op;
wire D_ctrl_alu_force_xor;
wire D_ctrl_alu_signed_comparison;
wire D_ctrl_alu_subtract;
wire D_ctrl_b_is_dst;
wire D_ctrl_br;
wire D_ctrl_br_cmp;
wire D_ctrl_br_uncond;
wire D_ctrl_break;
wire D_ctrl_crst;
wire D_ctrl_custom;
wire D_ctrl_custom_multi;
wire D_ctrl_exception;
wire D_ctrl_force_src2_zero;
wire D_ctrl_hi_imm16;
wire D_ctrl_ignore_dst;
wire D_ctrl_implicit_dst_eretaddr;
wire D_ctrl_implicit_dst_retaddr;
wire D_ctrl_jmp_direct;
wire D_ctrl_jmp_indirect;
wire D_ctrl_ld;
wire D_ctrl_ld_io;
wire D_ctrl_ld_non_io;
wire D_ctrl_ld_signed;
wire D_ctrl_logic;
wire D_ctrl_rdctl_inst;
wire D_ctrl_retaddr;
wire D_ctrl_rot_right;
wire D_ctrl_shift_logical;
wire D_ctrl_shift_right_arith;
wire D_ctrl_shift_rot;
wire D_ctrl_shift_rot_right;
wire D_ctrl_src2_choose_imm;
wire D_ctrl_st;
wire D_ctrl_uncond_cti_non_br;
wire D_ctrl_unsigned_lo_imm16;
wire D_ctrl_wrctl_inst;
wire [ 4: 0] D_dst_regnum;
wire [ 55: 0] D_inst;
reg [ 31: 0] D_iw /* synthesis ALTERA_IP_DEBUG_VISIBLE = 1 */;
wire [ 4: 0] D_iw_a;
wire [ 4: 0] D_iw_b;
wire [ 4: 0] D_iw_c;
wire [ 2: 0] D_iw_control_regnum;
wire [ 7: 0] D_iw_custom_n;
wire D_iw_custom_readra;
wire D_iw_custom_readrb;
wire D_iw_custom_writerc;
wire [ 15: 0] D_iw_imm16;
wire [ 25: 0] D_iw_imm26;
wire [ 4: 0] D_iw_imm5;
wire [ 1: 0] D_iw_memsz;
wire [ 5: 0] D_iw_op;
wire [ 5: 0] D_iw_opx;
wire [ 4: 0] D_iw_shift_imm5;
wire [ 4: 0] D_iw_trap_break_imm5;
wire [ 26: 0] D_jmp_direct_target_waddr;
wire [ 1: 0] D_logic_op;
wire [ 1: 0] D_logic_op_raw;
wire D_mem16;
wire D_mem32;
wire D_mem8;
wire D_op_add;
wire D_op_addi;
wire D_op_and;
wire D_op_andhi;
wire D_op_andi;
wire D_op_beq;
wire D_op_bge;
wire D_op_bgeu;
wire D_op_blt;
wire D_op_bltu;
wire D_op_bne;
wire D_op_br;
wire D_op_break;
wire D_op_bret;
wire D_op_call;
wire D_op_callr;
wire D_op_cmpeq;
wire D_op_cmpeqi;
wire D_op_cmpge;
wire D_op_cmpgei;
wire D_op_cmpgeu;
wire D_op_cmpgeui;
wire D_op_cmplt;
wire D_op_cmplti;
wire D_op_cmpltu;
wire D_op_cmpltui;
wire D_op_cmpne;
wire D_op_cmpnei;
wire D_op_crst;
wire D_op_custom;
wire D_op_div;
wire D_op_divu;
wire D_op_eret;
wire D_op_flushd;
wire D_op_flushda;
wire D_op_flushi;
wire D_op_flushp;
wire D_op_hbreak;
wire D_op_initd;
wire D_op_initda;
wire D_op_initi;
wire D_op_intr;
wire D_op_jmp;
wire D_op_jmpi;
wire D_op_ldb;
wire D_op_ldbio;
wire D_op_ldbu;
wire D_op_ldbuio;
wire D_op_ldh;
wire D_op_ldhio;
wire D_op_ldhu;
wire D_op_ldhuio;
wire D_op_ldl;
wire D_op_ldw;
wire D_op_ldwio;
wire D_op_mul;
wire D_op_muli;
wire D_op_mulxss;
wire D_op_mulxsu;
wire D_op_mulxuu;
wire D_op_nextpc;
wire D_op_nor;
wire D_op_opx;
wire D_op_or;
wire D_op_orhi;
wire D_op_ori;
wire D_op_rdctl;
wire D_op_rdprs;
wire D_op_ret;
wire D_op_rol;
wire D_op_roli;
wire D_op_ror;
wire D_op_rsv02;
wire D_op_rsv09;
wire D_op_rsv10;
wire D_op_rsv17;
wire D_op_rsv18;
wire D_op_rsv25;
wire D_op_rsv26;
wire D_op_rsv33;
wire D_op_rsv34;
wire D_op_rsv41;
wire D_op_rsv42;
wire D_op_rsv49;
wire D_op_rsv57;
wire D_op_rsv61;
wire D_op_rsv62;
wire D_op_rsv63;
wire D_op_rsvx00;
wire D_op_rsvx10;
wire D_op_rsvx15;
wire D_op_rsvx17;
wire D_op_rsvx21;
wire D_op_rsvx25;
wire D_op_rsvx33;
wire D_op_rsvx34;
wire D_op_rsvx35;
wire D_op_rsvx42;
wire D_op_rsvx43;
wire D_op_rsvx44;
wire D_op_rsvx47;
wire D_op_rsvx50;
wire D_op_rsvx51;
wire D_op_rsvx55;
wire D_op_rsvx56;
wire D_op_rsvx60;
wire D_op_rsvx63;
wire D_op_sll;
wire D_op_slli;
wire D_op_sra;
wire D_op_srai;
wire D_op_srl;
wire D_op_srli;
wire D_op_stb;
wire D_op_stbio;
wire D_op_stc;
wire D_op_sth;
wire D_op_sthio;
wire D_op_stw;
wire D_op_stwio;
wire D_op_sub;
wire D_op_sync;
wire D_op_trap;
wire D_op_wrctl;
wire D_op_wrprs;
wire D_op_xor;
wire D_op_xorhi;
wire D_op_xori;
reg D_valid;
wire [ 55: 0] D_vinst;
wire D_wr_dst_reg;
wire [ 31: 0] E_alu_result;
reg E_alu_sub;
wire [ 32: 0] E_arith_result;
wire [ 31: 0] E_arith_src1;
wire [ 31: 0] E_arith_src2;
wire E_ci_multi_stall;
wire [ 31: 0] E_ci_result;
wire E_cmp_result;
wire [ 31: 0] E_control_rd_data;
wire E_eq;
reg E_invert_arith_src_msb;
wire E_ld_stall;
wire [ 31: 0] E_logic_result;
wire E_logic_result_is_0;
wire E_lt;
wire [ 28: 0] E_mem_baddr;
wire [ 3: 0] E_mem_byte_en;
reg E_new_inst;
reg [ 4: 0] E_shift_rot_cnt;
wire [ 4: 0] E_shift_rot_cnt_nxt;
wire E_shift_rot_done;
wire E_shift_rot_fill_bit;
reg [ 31: 0] E_shift_rot_result;
wire [ 31: 0] E_shift_rot_result_nxt;
wire E_shift_rot_stall;
reg [ 31: 0] E_src1;
reg [ 31: 0] E_src2;
wire [ 31: 0] E_st_data;
wire E_st_stall;
wire E_stall;
reg E_valid;
wire [ 55: 0] E_vinst;
wire E_wrctl_bstatus;
wire E_wrctl_estatus;
wire E_wrctl_ienable;
wire E_wrctl_status;
wire [ 31: 0] F_av_iw;
wire [ 4: 0] F_av_iw_a;
wire [ 4: 0] F_av_iw_b;
wire [ 4: 0] F_av_iw_c;
wire [ 2: 0] F_av_iw_control_regnum;
wire [ 7: 0] F_av_iw_custom_n;
wire F_av_iw_custom_readra;
wire F_av_iw_custom_readrb;
wire F_av_iw_custom_writerc;
wire [ 15: 0] F_av_iw_imm16;
wire [ 25: 0] F_av_iw_imm26;
wire [ 4: 0] F_av_iw_imm5;
wire [ 1: 0] F_av_iw_memsz;
wire [ 5: 0] F_av_iw_op;
wire [ 5: 0] F_av_iw_opx;
wire [ 4: 0] F_av_iw_shift_imm5;
wire [ 4: 0] F_av_iw_trap_break_imm5;
wire F_av_mem16;
wire F_av_mem32;
wire F_av_mem8;
wire [ 55: 0] F_inst;
wire [ 31: 0] F_iw;
wire [ 4: 0] F_iw_a;
wire [ 4: 0] F_iw_b;
wire [ 4: 0] F_iw_c;
wire [ 2: 0] F_iw_control_regnum;
wire [ 7: 0] F_iw_custom_n;
wire F_iw_custom_readra;
wire F_iw_custom_readrb;
wire F_iw_custom_writerc;
wire [ 15: 0] F_iw_imm16;
wire [ 25: 0] F_iw_imm26;
wire [ 4: 0] F_iw_imm5;
wire [ 1: 0] F_iw_memsz;
wire [ 5: 0] F_iw_op;
wire [ 5: 0] F_iw_opx;
wire [ 4: 0] F_iw_shift_imm5;
wire [ 4: 0] F_iw_trap_break_imm5;
wire F_jmp_direct_pc_hi;
wire F_mem16;
wire F_mem32;
wire F_mem8;
wire F_op_add;
wire F_op_addi;
wire F_op_and;
wire F_op_andhi;
wire F_op_andi;
wire F_op_beq;
wire F_op_bge;
wire F_op_bgeu;
wire F_op_blt;
wire F_op_bltu;
wire F_op_bne;
wire F_op_br;
wire F_op_break;
wire F_op_bret;
wire F_op_call;
wire F_op_callr;
wire F_op_cmpeq;
wire F_op_cmpeqi;
wire F_op_cmpge;
wire F_op_cmpgei;
wire F_op_cmpgeu;
wire F_op_cmpgeui;
wire F_op_cmplt;
wire F_op_cmplti;
wire F_op_cmpltu;
wire F_op_cmpltui;
wire F_op_cmpne;
wire F_op_cmpnei;
wire F_op_crst;
wire F_op_custom;
wire F_op_div;
wire F_op_divu;
wire F_op_eret;
wire F_op_flushd;
wire F_op_flushda;
wire F_op_flushi;
wire F_op_flushp;
wire F_op_hbreak;
wire F_op_initd;
wire F_op_initda;
wire F_op_initi;
wire F_op_intr;
wire F_op_jmp;
wire F_op_jmpi;
wire F_op_ldb;
wire F_op_ldbio;
wire F_op_ldbu;
wire F_op_ldbuio;
wire F_op_ldh;
wire F_op_ldhio;
wire F_op_ldhu;
wire F_op_ldhuio;
wire F_op_ldl;
wire F_op_ldw;
wire F_op_ldwio;
wire F_op_mul;
wire F_op_muli;
wire F_op_mulxss;
wire F_op_mulxsu;
wire F_op_mulxuu;
wire F_op_nextpc;
wire F_op_nor;
wire F_op_opx;
wire F_op_or;
wire F_op_orhi;
wire F_op_ori;
wire F_op_rdctl;
wire F_op_rdprs;
wire F_op_ret;
wire F_op_rol;
wire F_op_roli;
wire F_op_ror;
wire F_op_rsv02;
wire F_op_rsv09;
wire F_op_rsv10;
wire F_op_rsv17;
wire F_op_rsv18;
wire F_op_rsv25;
wire F_op_rsv26;
wire F_op_rsv33;
wire F_op_rsv34;
wire F_op_rsv41;
wire F_op_rsv42;
wire F_op_rsv49;
wire F_op_rsv57;
wire F_op_rsv61;
wire F_op_rsv62;
wire F_op_rsv63;
wire F_op_rsvx00;
wire F_op_rsvx10;
wire F_op_rsvx15;
wire F_op_rsvx17;
wire F_op_rsvx21;
wire F_op_rsvx25;
wire F_op_rsvx33;
wire F_op_rsvx34;
wire F_op_rsvx35;
wire F_op_rsvx42;
wire F_op_rsvx43;
wire F_op_rsvx44;
wire F_op_rsvx47;
wire F_op_rsvx50;
wire F_op_rsvx51;
wire F_op_rsvx55;
wire F_op_rsvx56;
wire F_op_rsvx60;
wire F_op_rsvx63;
wire F_op_sll;
wire F_op_slli;
wire F_op_sra;
wire F_op_srai;
wire F_op_srl;
wire F_op_srli;
wire F_op_stb;
wire F_op_stbio;
wire F_op_stc;
wire F_op_sth;
wire F_op_sthio;
wire F_op_stw;
wire F_op_stwio;
wire F_op_sub;
wire F_op_sync;
wire F_op_trap;
wire F_op_wrctl;
wire F_op_wrprs;
wire F_op_xor;
wire F_op_xorhi;
wire F_op_xori;
reg [ 26: 0] F_pc /* synthesis ALTERA_IP_DEBUG_VISIBLE = 1 */;
wire F_pc_en;
wire [ 26: 0] F_pc_no_crst_nxt;
wire [ 26: 0] F_pc_nxt;
wire [ 26: 0] F_pc_plus_one;
wire [ 1: 0] F_pc_sel_nxt;
wire [ 28: 0] F_pcb;
wire [ 28: 0] F_pcb_nxt;
wire [ 28: 0] F_pcb_plus_four;
wire F_valid;
wire [ 55: 0] F_vinst;
reg [ 1: 0] R_compare_op;
reg R_ctrl_alu_force_xor;
wire R_ctrl_alu_force_xor_nxt;
reg R_ctrl_alu_signed_comparison;
wire R_ctrl_alu_signed_comparison_nxt;
reg R_ctrl_alu_subtract;
wire R_ctrl_alu_subtract_nxt;
reg R_ctrl_b_is_dst;
wire R_ctrl_b_is_dst_nxt;
reg R_ctrl_br;
reg R_ctrl_br_cmp;
wire R_ctrl_br_cmp_nxt;
wire R_ctrl_br_nxt;
reg R_ctrl_br_uncond;
wire R_ctrl_br_uncond_nxt;
reg R_ctrl_break;
wire R_ctrl_break_nxt;
reg R_ctrl_crst;
wire R_ctrl_crst_nxt;
reg R_ctrl_custom;
reg R_ctrl_custom_multi;
wire R_ctrl_custom_multi_nxt;
wire R_ctrl_custom_nxt;
reg R_ctrl_exception;
wire R_ctrl_exception_nxt;
reg R_ctrl_force_src2_zero;
wire R_ctrl_force_src2_zero_nxt;
reg R_ctrl_hi_imm16;
wire R_ctrl_hi_imm16_nxt;
reg R_ctrl_ignore_dst;
wire R_ctrl_ignore_dst_nxt;
reg R_ctrl_implicit_dst_eretaddr;
wire R_ctrl_implicit_dst_eretaddr_nxt;
reg R_ctrl_implicit_dst_retaddr;
wire R_ctrl_implicit_dst_retaddr_nxt;
reg R_ctrl_jmp_direct;
wire R_ctrl_jmp_direct_nxt;
reg R_ctrl_jmp_indirect;
wire R_ctrl_jmp_indirect_nxt;
reg R_ctrl_ld;
reg R_ctrl_ld_io;
wire R_ctrl_ld_io_nxt;
reg R_ctrl_ld_non_io;
wire R_ctrl_ld_non_io_nxt;
wire R_ctrl_ld_nxt;
reg R_ctrl_ld_signed;
wire R_ctrl_ld_signed_nxt;
reg R_ctrl_logic;
wire R_ctrl_logic_nxt;
reg R_ctrl_rdctl_inst;
wire R_ctrl_rdctl_inst_nxt;
reg R_ctrl_retaddr;
wire R_ctrl_retaddr_nxt;
reg R_ctrl_rot_right;
wire R_ctrl_rot_right_nxt;
reg R_ctrl_shift_logical;
wire R_ctrl_shift_logical_nxt;
reg R_ctrl_shift_right_arith;
wire R_ctrl_shift_right_arith_nxt;
reg R_ctrl_shift_rot;
wire R_ctrl_shift_rot_nxt;
reg R_ctrl_shift_rot_right;
wire R_ctrl_shift_rot_right_nxt;
reg R_ctrl_src2_choose_imm;
wire R_ctrl_src2_choose_imm_nxt;
reg R_ctrl_st;
wire R_ctrl_st_nxt;
reg R_ctrl_uncond_cti_non_br;
wire R_ctrl_uncond_cti_non_br_nxt;
reg R_ctrl_unsigned_lo_imm16;
wire R_ctrl_unsigned_lo_imm16_nxt;
reg R_ctrl_wrctl_inst;
wire R_ctrl_wrctl_inst_nxt;
reg [ 4: 0] R_dst_regnum /* synthesis ALTERA_IP_DEBUG_VISIBLE = 1 */;
wire R_en;
reg [ 1: 0] R_logic_op;
wire [ 31: 0] R_rf_a;
wire [ 31: 0] R_rf_b;
wire [ 31: 0] R_src1;
wire [ 31: 0] R_src2;
wire [ 15: 0] R_src2_hi;
wire [ 15: 0] R_src2_lo;
reg R_src2_use_imm;
wire [ 7: 0] R_stb_data;
wire [ 15: 0] R_sth_data;
reg R_valid;
wire [ 55: 0] R_vinst;
reg R_wr_dst_reg;
reg [ 31: 0] W_alu_result;
wire W_br_taken;
reg W_bstatus_reg;
wire W_bstatus_reg_inst_nxt;
wire W_bstatus_reg_nxt;
reg W_cmp_result;
reg [ 31: 0] W_control_rd_data;
wire [ 31: 0] W_cpuid_reg;
reg W_estatus_reg;
wire W_estatus_reg_inst_nxt;
wire W_estatus_reg_nxt;
reg [ 31: 0] W_ienable_reg;
wire [ 31: 0] W_ienable_reg_nxt;
reg [ 31: 0] W_ipending_reg;
wire [ 31: 0] W_ipending_reg_nxt;
wire [ 28: 0] W_mem_baddr;
wire [ 31: 0] W_rf_wr_data;
wire W_rf_wren;
wire W_status_reg;
reg W_status_reg_pie;
wire W_status_reg_pie_inst_nxt;
wire W_status_reg_pie_nxt;
reg W_valid /* synthesis ALTERA_IP_DEBUG_VISIBLE = 1 */;
wire [ 55: 0] W_vinst;
wire [ 31: 0] W_wr_data;
wire [ 31: 0] W_wr_data_non_zero;
wire av_fill_bit;
reg [ 1: 0] av_ld_align_cycle;
wire [ 1: 0] av_ld_align_cycle_nxt;
wire av_ld_align_one_more_cycle;
reg av_ld_aligning_data;
wire av_ld_aligning_data_nxt;
reg [ 7: 0] av_ld_byte0_data;
wire [ 7: 0] av_ld_byte0_data_nxt;
reg [ 7: 0] av_ld_byte1_data;
wire av_ld_byte1_data_en;
wire [ 7: 0] av_ld_byte1_data_nxt;
reg [ 7: 0] av_ld_byte2_data;
wire [ 7: 0] av_ld_byte2_data_nxt;
reg [ 7: 0] av_ld_byte3_data;
wire [ 7: 0] av_ld_byte3_data_nxt;
wire [ 31: 0] av_ld_data_aligned_filtered;
wire [ 31: 0] av_ld_data_aligned_unfiltered;
wire av_ld_done;
wire av_ld_extend;
wire av_ld_getting_data;
wire av_ld_rshift8;
reg av_ld_waiting_for_data;
wire av_ld_waiting_for_data_nxt;
wire av_sign_bit;
wire [ 28: 0] d_address;
reg [ 3: 0] d_byteenable;
reg d_read;
wire d_read_nxt;
reg d_write;
wire d_write_nxt;
reg [ 31: 0] d_writedata;
reg hbreak_enabled;
reg hbreak_pending;
wire hbreak_pending_nxt;
wire hbreak_req;
wire [ 28: 0] i_address;
reg i_read;
wire i_read_nxt;
wire [ 31: 0] iactive;
wire intr_req;
wire jtag_debug_module_clk;
wire jtag_debug_module_debugaccess_to_roms;
wire [ 31: 0] jtag_debug_module_readdata;
wire jtag_debug_module_reset;
wire jtag_debug_module_resetrequest;
wire jtag_debug_module_waitrequest;
wire no_ci_readra;
wire oci_hbreak_req;
wire [ 31: 0] oci_ienable;
wire oci_single_step_mode;
wire oci_tb_hbreak_req;
wire test_ending;
wire test_has_ended;
reg wait_for_one_post_bret_inst;
//the_limbus_nios2_qsys_0_test_bench, which is an e_instance
limbus_nios2_qsys_0_test_bench the_limbus_nios2_qsys_0_test_bench
(
.D_iw (D_iw),
.D_iw_op (D_iw_op),
.D_iw_opx (D_iw_opx),
.D_valid (D_valid),
.E_valid (E_valid),
.F_pcb (F_pcb),
.F_valid (F_valid),
.R_ctrl_ld (R_ctrl_ld),
.R_ctrl_ld_non_io (R_ctrl_ld_non_io),
.R_dst_regnum (R_dst_regnum),
.R_wr_dst_reg (R_wr_dst_reg),
.W_valid (W_valid),
.W_vinst (W_vinst),
.W_wr_data (W_wr_data),
.av_ld_data_aligned_filtered (av_ld_data_aligned_filtered),
.av_ld_data_aligned_unfiltered (av_ld_data_aligned_unfiltered),
.clk (clk),
.d_address (d_address),
.d_byteenable (d_byteenable),
.d_read (d_read),
.d_write (d_write),
.i_address (i_address),
.i_read (i_read),
.i_readdata (i_readdata),
.i_waitrequest (i_waitrequest),
.reset_n (reset_n),
.test_has_ended (test_has_ended)
);
assign F_av_iw_a = F_av_iw[31 : 27];
assign F_av_iw_b = F_av_iw[26 : 22];
assign F_av_iw_c = F_av_iw[21 : 17];
assign F_av_iw_custom_n = F_av_iw[13 : 6];
assign F_av_iw_custom_readra = F_av_iw[16];
assign F_av_iw_custom_readrb = F_av_iw[15];
assign F_av_iw_custom_writerc = F_av_iw[14];
assign F_av_iw_opx = F_av_iw[16 : 11];
assign F_av_iw_op = F_av_iw[5 : 0];
assign F_av_iw_shift_imm5 = F_av_iw[10 : 6];
assign F_av_iw_trap_break_imm5 = F_av_iw[10 : 6];
assign F_av_iw_imm5 = F_av_iw[10 : 6];
assign F_av_iw_imm16 = F_av_iw[21 : 6];
assign F_av_iw_imm26 = F_av_iw[31 : 6];
assign F_av_iw_memsz = F_av_iw[4 : 3];
assign F_av_iw_control_regnum = F_av_iw[8 : 6];
assign F_av_mem8 = F_av_iw_memsz == 2'b00;
assign F_av_mem16 = F_av_iw_memsz == 2'b01;
assign F_av_mem32 = F_av_iw_memsz[1] == 1'b1;
assign F_iw_a = F_iw[31 : 27];
assign F_iw_b = F_iw[26 : 22];
assign F_iw_c = F_iw[21 : 17];
assign F_iw_custom_n = F_iw[13 : 6];
assign F_iw_custom_readra = F_iw[16];
assign F_iw_custom_readrb = F_iw[15];
assign F_iw_custom_writerc = F_iw[14];
assign F_iw_opx = F_iw[16 : 11];
assign F_iw_op = F_iw[5 : 0];
assign F_iw_shift_imm5 = F_iw[10 : 6];
assign F_iw_trap_break_imm5 = F_iw[10 : 6];
assign F_iw_imm5 = F_iw[10 : 6];
assign F_iw_imm16 = F_iw[21 : 6];
assign F_iw_imm26 = F_iw[31 : 6];
assign F_iw_memsz = F_iw[4 : 3];
assign F_iw_control_regnum = F_iw[8 : 6];
assign F_mem8 = F_iw_memsz == 2'b00;
assign F_mem16 = F_iw_memsz == 2'b01;
assign F_mem32 = F_iw_memsz[1] == 1'b1;
assign D_iw_a = D_iw[31 : 27];
assign D_iw_b = D_iw[26 : 22];
assign D_iw_c = D_iw[21 : 17];
assign D_iw_custom_n = D_iw[13 : 6];
assign D_iw_custom_readra = D_iw[16];
assign D_iw_custom_readrb = D_iw[15];
assign D_iw_custom_writerc = D_iw[14];
assign D_iw_opx = D_iw[16 : 11];
assign D_iw_op = D_iw[5 : 0];
assign D_iw_shift_imm5 = D_iw[10 : 6];
assign D_iw_trap_break_imm5 = D_iw[10 : 6];
assign D_iw_imm5 = D_iw[10 : 6];
assign D_iw_imm16 = D_iw[21 : 6];
assign D_iw_imm26 = D_iw[31 : 6];
assign D_iw_memsz = D_iw[4 : 3];
assign D_iw_control_regnum = D_iw[8 : 6];
assign D_mem8 = D_iw_memsz == 2'b00;
assign D_mem16 = D_iw_memsz == 2'b01;
assign D_mem32 = D_iw_memsz[1] == 1'b1;
assign F_op_call = F_iw_op == 0;
assign F_op_jmpi = F_iw_op == 1;
assign F_op_ldbu = F_iw_op == 3;
assign F_op_addi = F_iw_op == 4;
assign F_op_stb = F_iw_op == 5;
assign F_op_br = F_iw_op == 6;
assign F_op_ldb = F_iw_op == 7;
assign F_op_cmpgei = F_iw_op == 8;
assign F_op_ldhu = F_iw_op == 11;
assign F_op_andi = F_iw_op == 12;
assign F_op_sth = F_iw_op == 13;
assign F_op_bge = F_iw_op == 14;
assign F_op_ldh = F_iw_op == 15;
assign F_op_cmplti = F_iw_op == 16;
assign F_op_initda = F_iw_op == 19;
assign F_op_ori = F_iw_op == 20;
assign F_op_stw = F_iw_op == 21;
assign F_op_blt = F_iw_op == 22;
assign F_op_ldw = F_iw_op == 23;
assign F_op_cmpnei = F_iw_op == 24;
assign F_op_flushda = F_iw_op == 27;
assign F_op_xori = F_iw_op == 28;
assign F_op_stc = F_iw_op == 29;
assign F_op_bne = F_iw_op == 30;
assign F_op_ldl = F_iw_op == 31;
assign F_op_cmpeqi = F_iw_op == 32;
assign F_op_ldbuio = F_iw_op == 35;
assign F_op_muli = F_iw_op == 36;
assign F_op_stbio = F_iw_op == 37;
assign F_op_beq = F_iw_op == 38;
assign F_op_ldbio = F_iw_op == 39;
assign F_op_cmpgeui = F_iw_op == 40;
assign F_op_ldhuio = F_iw_op == 43;
assign F_op_andhi = F_iw_op == 44;
assign F_op_sthio = F_iw_op == 45;
assign F_op_bgeu = F_iw_op == 46;
assign F_op_ldhio = F_iw_op == 47;
assign F_op_cmpltui = F_iw_op == 48;
assign F_op_initd = F_iw_op == 51;
assign F_op_orhi = F_iw_op == 52;
assign F_op_stwio = F_iw_op == 53;
assign F_op_bltu = F_iw_op == 54;
assign F_op_ldwio = F_iw_op == 55;
assign F_op_rdprs = F_iw_op == 56;
assign F_op_flushd = F_iw_op == 59;
assign F_op_xorhi = F_iw_op == 60;
assign F_op_rsv02 = F_iw_op == 2;
assign F_op_rsv09 = F_iw_op == 9;
assign F_op_rsv10 = F_iw_op == 10;
assign F_op_rsv17 = F_iw_op == 17;
assign F_op_rsv18 = F_iw_op == 18;
assign F_op_rsv25 = F_iw_op == 25;
assign F_op_rsv26 = F_iw_op == 26;
assign F_op_rsv33 = F_iw_op == 33;
assign F_op_rsv34 = F_iw_op == 34;
assign F_op_rsv41 = F_iw_op == 41;
assign F_op_rsv42 = F_iw_op == 42;
assign F_op_rsv49 = F_iw_op == 49;
assign F_op_rsv57 = F_iw_op == 57;
assign F_op_rsv61 = F_iw_op == 61;
assign F_op_rsv62 = F_iw_op == 62;
assign F_op_rsv63 = F_iw_op == 63;
assign F_op_eret = F_op_opx & (F_iw_opx == 1);
assign F_op_roli = F_op_opx & (F_iw_opx == 2);
assign F_op_rol = F_op_opx & (F_iw_opx == 3);
assign F_op_flushp = F_op_opx & (F_iw_opx == 4);
assign F_op_ret = F_op_opx & (F_iw_opx == 5);
assign F_op_nor = F_op_opx & (F_iw_opx == 6);
assign F_op_mulxuu = F_op_opx & (F_iw_opx == 7);
assign F_op_cmpge = F_op_opx & (F_iw_opx == 8);
assign F_op_bret = F_op_opx & (F_iw_opx == 9);
assign F_op_ror = F_op_opx & (F_iw_opx == 11);
assign F_op_flushi = F_op_opx & (F_iw_opx == 12);
assign F_op_jmp = F_op_opx & (F_iw_opx == 13);
assign F_op_and = F_op_opx & (F_iw_opx == 14);
assign F_op_cmplt = F_op_opx & (F_iw_opx == 16);
assign F_op_slli = F_op_opx & (F_iw_opx == 18);
assign F_op_sll = F_op_opx & (F_iw_opx == 19);
assign F_op_wrprs = F_op_opx & (F_iw_opx == 20);
assign F_op_or = F_op_opx & (F_iw_opx == 22);
assign F_op_mulxsu = F_op_opx & (F_iw_opx == 23);
assign F_op_cmpne = F_op_opx & (F_iw_opx == 24);
assign F_op_srli = F_op_opx & (F_iw_opx == 26);
assign F_op_srl = F_op_opx & (F_iw_opx == 27);
assign F_op_nextpc = F_op_opx & (F_iw_opx == 28);
assign F_op_callr = F_op_opx & (F_iw_opx == 29);
assign F_op_xor = F_op_opx & (F_iw_opx == 30);
assign F_op_mulxss = F_op_opx & (F_iw_opx == 31);
assign F_op_cmpeq = F_op_opx & (F_iw_opx == 32);
assign F_op_divu = F_op_opx & (F_iw_opx == 36);
assign F_op_div = F_op_opx & (F_iw_opx == 37);
assign F_op_rdctl = F_op_opx & (F_iw_opx == 38);
assign F_op_mul = F_op_opx & (F_iw_opx == 39);
assign F_op_cmpgeu = F_op_opx & (F_iw_opx == 40);
assign F_op_initi = F_op_opx & (F_iw_opx == 41);
assign F_op_trap = F_op_opx & (F_iw_opx == 45);
assign F_op_wrctl = F_op_opx & (F_iw_opx == 46);
assign F_op_cmpltu = F_op_opx & (F_iw_opx == 48);
assign F_op_add = F_op_opx & (F_iw_opx == 49);
assign F_op_break = F_op_opx & (F_iw_opx == 52);
assign F_op_hbreak = F_op_opx & (F_iw_opx == 53);
assign F_op_sync = F_op_opx & (F_iw_opx == 54);
assign F_op_sub = F_op_opx & (F_iw_opx == 57);
assign F_op_srai = F_op_opx & (F_iw_opx == 58);
assign F_op_sra = F_op_opx & (F_iw_opx == 59);
assign F_op_intr = F_op_opx & (F_iw_opx == 61);
assign F_op_crst = F_op_opx & (F_iw_opx == 62);
assign F_op_rsvx00 = F_op_opx & (F_iw_opx == 0);
assign F_op_rsvx10 = F_op_opx & (F_iw_opx == 10);
assign F_op_rsvx15 = F_op_opx & (F_iw_opx == 15);
assign F_op_rsvx17 = F_op_opx & (F_iw_opx == 17);
assign F_op_rsvx21 = F_op_opx & (F_iw_opx == 21);
assign F_op_rsvx25 = F_op_opx & (F_iw_opx == 25);
assign F_op_rsvx33 = F_op_opx & (F_iw_opx == 33);
assign F_op_rsvx34 = F_op_opx & (F_iw_opx == 34);
assign F_op_rsvx35 = F_op_opx & (F_iw_opx == 35);
assign F_op_rsvx42 = F_op_opx & (F_iw_opx == 42);
assign F_op_rsvx43 = F_op_opx & (F_iw_opx == 43);
assign F_op_rsvx44 = F_op_opx & (F_iw_opx == 44);
assign F_op_rsvx47 = F_op_opx & (F_iw_opx == 47);
assign F_op_rsvx50 = F_op_opx & (F_iw_opx == 50);
assign F_op_rsvx51 = F_op_opx & (F_iw_opx == 51);
assign F_op_rsvx55 = F_op_opx & (F_iw_opx == 55);
assign F_op_rsvx56 = F_op_opx & (F_iw_opx == 56);
assign F_op_rsvx60 = F_op_opx & (F_iw_opx == 60);
assign F_op_rsvx63 = F_op_opx & (F_iw_opx == 63);
assign F_op_opx = F_iw_op == 58;
assign F_op_custom = F_iw_op == 50;
assign D_op_call = D_iw_op == 0;
assign D_op_jmpi = D_iw_op == 1;
assign D_op_ldbu = D_iw_op == 3;
assign D_op_addi = D_iw_op == 4;
assign D_op_stb = D_iw_op == 5;
assign D_op_br = D_iw_op == 6;
assign D_op_ldb = D_iw_op == 7;
assign D_op_cmpgei = D_iw_op == 8;
assign D_op_ldhu = D_iw_op == 11;
assign D_op_andi = D_iw_op == 12;
assign D_op_sth = D_iw_op == 13;
assign D_op_bge = D_iw_op == 14;
assign D_op_ldh = D_iw_op == 15;
assign D_op_cmplti = D_iw_op == 16;
assign D_op_initda = D_iw_op == 19;
assign D_op_ori = D_iw_op == 20;
assign D_op_stw = D_iw_op == 21;
assign D_op_blt = D_iw_op == 22;
assign D_op_ldw = D_iw_op == 23;
assign D_op_cmpnei = D_iw_op == 24;
assign D_op_flushda = D_iw_op == 27;
assign D_op_xori = D_iw_op == 28;
assign D_op_stc = D_iw_op == 29;
assign D_op_bne = D_iw_op == 30;
assign D_op_ldl = D_iw_op == 31;
assign D_op_cmpeqi = D_iw_op == 32;
assign D_op_ldbuio = D_iw_op == 35;
assign D_op_muli = D_iw_op == 36;
assign D_op_stbio = D_iw_op == 37;
assign D_op_beq = D_iw_op == 38;
assign D_op_ldbio = D_iw_op == 39;
assign D_op_cmpgeui = D_iw_op == 40;
assign D_op_ldhuio = D_iw_op == 43;
assign D_op_andhi = D_iw_op == 44;
assign D_op_sthio = D_iw_op == 45;
assign D_op_bgeu = D_iw_op == 46;
assign D_op_ldhio = D_iw_op == 47;
assign D_op_cmpltui = D_iw_op == 48;
assign D_op_initd = D_iw_op == 51;
assign D_op_orhi = D_iw_op == 52;
assign D_op_stwio = D_iw_op == 53;
assign D_op_bltu = D_iw_op == 54;
assign D_op_ldwio = D_iw_op == 55;
assign D_op_rdprs = D_iw_op == 56;
assign D_op_flushd = D_iw_op == 59;
assign D_op_xorhi = D_iw_op == 60;
assign D_op_rsv02 = D_iw_op == 2;
assign D_op_rsv09 = D_iw_op == 9;
assign D_op_rsv10 = D_iw_op == 10;
assign D_op_rsv17 = D_iw_op == 17;
assign D_op_rsv18 = D_iw_op == 18;
assign D_op_rsv25 = D_iw_op == 25;
assign D_op_rsv26 = D_iw_op == 26;
assign D_op_rsv33 = D_iw_op == 33;
assign D_op_rsv34 = D_iw_op == 34;
assign D_op_rsv41 = D_iw_op == 41;
assign D_op_rsv42 = D_iw_op == 42;
assign D_op_rsv49 = D_iw_op == 49;
assign D_op_rsv57 = D_iw_op == 57;
assign D_op_rsv61 = D_iw_op == 61;
assign D_op_rsv62 = D_iw_op == 62;
assign D_op_rsv63 = D_iw_op == 63;
assign D_op_eret = D_op_opx & (D_iw_opx == 1);
assign D_op_roli = D_op_opx & (D_iw_opx == 2);
assign D_op_rol = D_op_opx & (D_iw_opx == 3);
assign D_op_flushp = D_op_opx & (D_iw_opx == 4);
assign D_op_ret = D_op_opx & (D_iw_opx == 5);
assign D_op_nor = D_op_opx & (D_iw_opx == 6);
assign D_op_mulxuu = D_op_opx & (D_iw_opx == 7);
assign D_op_cmpge = D_op_opx & (D_iw_opx == 8);
assign D_op_bret = D_op_opx & (D_iw_opx == 9);
assign D_op_ror = D_op_opx & (D_iw_opx == 11);
assign D_op_flushi = D_op_opx & (D_iw_opx == 12);
assign D_op_jmp = D_op_opx & (D_iw_opx == 13);
assign D_op_and = D_op_opx & (D_iw_opx == 14);
assign D_op_cmplt = D_op_opx & (D_iw_opx == 16);
assign D_op_slli = D_op_opx & (D_iw_opx == 18);
assign D_op_sll = D_op_opx & (D_iw_opx == 19);
assign D_op_wrprs = D_op_opx & (D_iw_opx == 20);
assign D_op_or = D_op_opx & (D_iw_opx == 22);
assign D_op_mulxsu = D_op_opx & (D_iw_opx == 23);
assign D_op_cmpne = D_op_opx & (D_iw_opx == 24);
assign D_op_srli = D_op_opx & (D_iw_opx == 26);
assign D_op_srl = D_op_opx & (D_iw_opx == 27);
assign D_op_nextpc = D_op_opx & (D_iw_opx == 28);
assign D_op_callr = D_op_opx & (D_iw_opx == 29);
assign D_op_xor = D_op_opx & (D_iw_opx == 30);
assign D_op_mulxss = D_op_opx & (D_iw_opx == 31);
assign D_op_cmpeq = D_op_opx & (D_iw_opx == 32);
assign D_op_divu = D_op_opx & (D_iw_opx == 36);
assign D_op_div = D_op_opx & (D_iw_opx == 37);
assign D_op_rdctl = D_op_opx & (D_iw_opx == 38);
assign D_op_mul = D_op_opx & (D_iw_opx == 39);
assign D_op_cmpgeu = D_op_opx & (D_iw_opx == 40);
assign D_op_initi = D_op_opx & (D_iw_opx == 41);
assign D_op_trap = D_op_opx & (D_iw_opx == 45);
assign D_op_wrctl = D_op_opx & (D_iw_opx == 46);
assign D_op_cmpltu = D_op_opx & (D_iw_opx == 48);
assign D_op_add = D_op_opx & (D_iw_opx == 49);
assign D_op_break = D_op_opx & (D_iw_opx == 52);
assign D_op_hbreak = D_op_opx & (D_iw_opx == 53);
assign D_op_sync = D_op_opx & (D_iw_opx == 54);
assign D_op_sub = D_op_opx & (D_iw_opx == 57);
assign D_op_srai = D_op_opx & (D_iw_opx == 58);
assign D_op_sra = D_op_opx & (D_iw_opx == 59);
assign D_op_intr = D_op_opx & (D_iw_opx == 61);
assign D_op_crst = D_op_opx & (D_iw_opx == 62);
assign D_op_rsvx00 = D_op_opx & (D_iw_opx == 0);
assign D_op_rsvx10 = D_op_opx & (D_iw_opx == 10);
assign D_op_rsvx15 = D_op_opx & (D_iw_opx == 15);
assign D_op_rsvx17 = D_op_opx & (D_iw_opx == 17);
assign D_op_rsvx21 = D_op_opx & (D_iw_opx == 21);
assign D_op_rsvx25 = D_op_opx & (D_iw_opx == 25);
assign D_op_rsvx33 = D_op_opx & (D_iw_opx == 33);
assign D_op_rsvx34 = D_op_opx & (D_iw_opx == 34);
assign D_op_rsvx35 = D_op_opx & (D_iw_opx == 35);
assign D_op_rsvx42 = D_op_opx & (D_iw_opx == 42);
assign D_op_rsvx43 = D_op_opx & (D_iw_opx == 43);
assign D_op_rsvx44 = D_op_opx & (D_iw_opx == 44);
assign D_op_rsvx47 = D_op_opx & (D_iw_opx == 47);
assign D_op_rsvx50 = D_op_opx & (D_iw_opx == 50);
assign D_op_rsvx51 = D_op_opx & (D_iw_opx == 51);
assign D_op_rsvx55 = D_op_opx & (D_iw_opx == 55);
assign D_op_rsvx56 = D_op_opx & (D_iw_opx == 56);
assign D_op_rsvx60 = D_op_opx & (D_iw_opx == 60);
assign D_op_rsvx63 = D_op_opx & (D_iw_opx == 63);
assign D_op_opx = D_iw_op == 58;
assign D_op_custom = D_iw_op == 50;
assign R_en = 1'b1;
assign E_ci_result = 0;
//custom_instruction_master, which is an e_custom_instruction_master
assign no_ci_readra = 1'b0;
assign E_ci_multi_stall = 1'b0;
assign iactive = d_irq[31 : 0] & 32'b00000000000000000000000000000001;
assign F_pc_sel_nxt = R_ctrl_exception ? 2'b00 :
R_ctrl_break ? 2'b01 :
(W_br_taken | R_ctrl_uncond_cti_non_br) ? 2'b10 :
2'b11;
assign F_pc_no_crst_nxt = (F_pc_sel_nxt == 2'b00)? 67108872 :
(F_pc_sel_nxt == 2'b01)? 67240456 :
(F_pc_sel_nxt == 2'b10)? E_arith_result[28 : 2] :
F_pc_plus_one;
assign F_pc_nxt = F_pc_no_crst_nxt;
assign F_pcb_nxt = {F_pc_nxt, 2'b00};
assign F_pc_en = W_valid;
assign F_pc_plus_one = F_pc + 1;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
F_pc <= 67108864;
else if (F_pc_en)
F_pc <= F_pc_nxt;
end
assign F_pcb = {F_pc, 2'b00};
assign F_pcb_plus_four = {F_pc_plus_one, 2'b00};
assign F_valid = i_read & ~i_waitrequest;
assign i_read_nxt = W_valid | (i_read & i_waitrequest);
assign i_address = {F_pc, 2'b00};
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
i_read <= 1'b1;
else
i_read <= i_read_nxt;
end
assign oci_tb_hbreak_req = oci_hbreak_req;
assign hbreak_req = (oci_tb_hbreak_req | hbreak_pending) & hbreak_enabled & ~(wait_for_one_post_bret_inst & ~W_valid);
assign hbreak_pending_nxt = hbreak_pending ? hbreak_enabled
: hbreak_req;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
wait_for_one_post_bret_inst <= 1'b0;
else
wait_for_one_post_bret_inst <= (~hbreak_enabled & oci_single_step_mode) ? 1'b1 : (F_valid | ~oci_single_step_mode) ? 1'b0 : wait_for_one_post_bret_inst;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
hbreak_pending <= 1'b0;
else
hbreak_pending <= hbreak_pending_nxt;
end
assign intr_req = W_status_reg_pie & (W_ipending_reg != 0);
assign F_av_iw = i_readdata;
assign F_iw = hbreak_req ? 4040762 :
1'b0 ? 127034 :
intr_req ? 3926074 :
F_av_iw;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
D_iw <= 0;
else if (F_valid)
D_iw <= F_iw;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
D_valid <= 0;
else
D_valid <= F_valid;
end
assign D_dst_regnum = D_ctrl_implicit_dst_retaddr ? 5'd31 :
D_ctrl_implicit_dst_eretaddr ? 5'd29 :
D_ctrl_b_is_dst ? D_iw_b :
D_iw_c;
assign D_wr_dst_reg = (D_dst_regnum != 0) & ~D_ctrl_ignore_dst;
assign D_logic_op_raw = D_op_opx ? D_iw_opx[4 : 3] :
D_iw_op[4 : 3];
assign D_logic_op = D_ctrl_alu_force_xor ? 2'b11 : D_logic_op_raw;
assign D_compare_op = D_op_opx ? D_iw_opx[4 : 3] :
D_iw_op[4 : 3];
assign F_jmp_direct_pc_hi = F_pc[26];
assign D_jmp_direct_target_waddr = {F_jmp_direct_pc_hi, D_iw[31 : 6]};
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_valid <= 0;
else
R_valid <= D_valid;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_wr_dst_reg <= 0;
else
R_wr_dst_reg <= D_wr_dst_reg;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_dst_regnum <= 0;
else
R_dst_regnum <= D_dst_regnum;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_logic_op <= 0;
else
R_logic_op <= D_logic_op;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_compare_op <= 0;
else
R_compare_op <= D_compare_op;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_src2_use_imm <= 0;
else
R_src2_use_imm <= D_ctrl_src2_choose_imm | (D_ctrl_br & R_valid);
end
assign W_rf_wren = (R_wr_dst_reg & W_valid) | ~reset_n;
assign W_rf_wr_data = R_ctrl_ld ? av_ld_data_aligned_filtered : W_wr_data;
//limbus_nios2_qsys_0_register_bank_a, which is an nios_sdp_ram
limbus_nios2_qsys_0_register_bank_a_module limbus_nios2_qsys_0_register_bank_a
(
.clock (clk),
.data (W_rf_wr_data),
.q (R_rf_a),
.rdaddress (D_iw_a),
.wraddress (R_dst_regnum),
.wren (W_rf_wren)
);
//synthesis translate_off
`ifdef NO_PLI
defparam limbus_nios2_qsys_0_register_bank_a.lpm_file = "limbus_nios2_qsys_0_rf_ram_a.dat";
`else
defparam limbus_nios2_qsys_0_register_bank_a.lpm_file = "limbus_nios2_qsys_0_rf_ram_a.hex";
`endif
//synthesis translate_on
//synthesis read_comments_as_HDL on
//defparam limbus_nios2_qsys_0_register_bank_a.lpm_file = "limbus_nios2_qsys_0_rf_ram_a.mif";
//synthesis read_comments_as_HDL off
//limbus_nios2_qsys_0_register_bank_b, which is an nios_sdp_ram
limbus_nios2_qsys_0_register_bank_b_module limbus_nios2_qsys_0_register_bank_b
(
.clock (clk),
.data (W_rf_wr_data),
.q (R_rf_b),
.rdaddress (D_iw_b),
.wraddress (R_dst_regnum),
.wren (W_rf_wren)
);
//synthesis translate_off
`ifdef NO_PLI
defparam limbus_nios2_qsys_0_register_bank_b.lpm_file = "limbus_nios2_qsys_0_rf_ram_b.dat";
`else
defparam limbus_nios2_qsys_0_register_bank_b.lpm_file = "limbus_nios2_qsys_0_rf_ram_b.hex";
`endif
//synthesis translate_on
//synthesis read_comments_as_HDL on
//defparam limbus_nios2_qsys_0_register_bank_b.lpm_file = "limbus_nios2_qsys_0_rf_ram_b.mif";
//synthesis read_comments_as_HDL off
assign R_src1 = (((R_ctrl_br & E_valid) | (R_ctrl_retaddr & R_valid)))? {F_pc_plus_one, 2'b00} :
((R_ctrl_jmp_direct & E_valid))? {D_jmp_direct_target_waddr, 2'b00} :
R_rf_a;
assign R_src2_lo = ((R_ctrl_force_src2_zero|R_ctrl_hi_imm16))? 16'b0 :
(R_src2_use_imm)? D_iw_imm16 :
R_rf_b[15 : 0];
assign R_src2_hi = ((R_ctrl_force_src2_zero|R_ctrl_unsigned_lo_imm16))? 16'b0 :
(R_ctrl_hi_imm16)? D_iw_imm16 :
(R_src2_use_imm)? {16 {D_iw_imm16[15]}} :
R_rf_b[31 : 16];
assign R_src2 = {R_src2_hi, R_src2_lo};
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
E_valid <= 0;
else
E_valid <= R_valid | E_stall;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
E_new_inst <= 0;
else
E_new_inst <= R_valid;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
E_src1 <= 0;
else
E_src1 <= R_src1;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
E_src2 <= 0;
else
E_src2 <= R_src2;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
E_invert_arith_src_msb <= 0;
else
E_invert_arith_src_msb <= D_ctrl_alu_signed_comparison & R_valid;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
E_alu_sub <= 0;
else
E_alu_sub <= D_ctrl_alu_subtract & R_valid;
end
assign E_stall = E_shift_rot_stall | E_ld_stall | E_st_stall | E_ci_multi_stall;
assign E_arith_src1 = { E_src1[31] ^ E_invert_arith_src_msb,
E_src1[30 : 0]};
assign E_arith_src2 = { E_src2[31] ^ E_invert_arith_src_msb,
E_src2[30 : 0]};
assign E_arith_result = E_alu_sub ?
E_arith_src1 - E_arith_src2 :
E_arith_src1 + E_arith_src2;
assign E_mem_baddr = E_arith_result[28 : 0];
assign E_logic_result = (R_logic_op == 2'b00)? (~(E_src1 | E_src2)) :
(R_logic_op == 2'b01)? (E_src1 & E_src2) :
(R_logic_op == 2'b10)? (E_src1 | E_src2) :
(E_src1 ^ E_src2);
assign E_logic_result_is_0 = E_logic_result == 0;
assign E_eq = E_logic_result_is_0;
assign E_lt = E_arith_result[32];
assign E_cmp_result = (R_compare_op == 2'b00)? E_eq :
(R_compare_op == 2'b01)? ~E_lt :
(R_compare_op == 2'b10)? E_lt :
~E_eq;
assign E_shift_rot_cnt_nxt = E_new_inst ? E_src2[4 : 0] : E_shift_rot_cnt-1;
assign E_shift_rot_done = (E_shift_rot_cnt == 0) & ~E_new_inst;
assign E_shift_rot_stall = R_ctrl_shift_rot & E_valid & ~E_shift_rot_done;
assign E_shift_rot_fill_bit = R_ctrl_shift_logical ? 1'b0 :
(R_ctrl_rot_right ? E_shift_rot_result[0] :
E_shift_rot_result[31]);
assign E_shift_rot_result_nxt = (E_new_inst)? E_src1 :
(R_ctrl_shift_rot_right)? {E_shift_rot_fill_bit, E_shift_rot_result[31 : 1]} :
{E_shift_rot_result[30 : 0], E_shift_rot_fill_bit};
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
E_shift_rot_result <= 0;
else
E_shift_rot_result <= E_shift_rot_result_nxt;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
E_shift_rot_cnt <= 0;
else
E_shift_rot_cnt <= E_shift_rot_cnt_nxt;
end
assign E_control_rd_data = (D_iw_control_regnum == 3'd0)? W_status_reg :
(D_iw_control_regnum == 3'd1)? W_estatus_reg :
(D_iw_control_regnum == 3'd2)? W_bstatus_reg :
(D_iw_control_regnum == 3'd3)? W_ienable_reg :
(D_iw_control_regnum == 3'd4)? W_ipending_reg :
W_cpuid_reg;
assign E_alu_result = ((R_ctrl_br_cmp | R_ctrl_rdctl_inst))? 0 :
(R_ctrl_shift_rot)? E_shift_rot_result :
(R_ctrl_logic)? E_logic_result :
(R_ctrl_custom)? E_ci_result :
E_arith_result;
assign R_stb_data = R_rf_b[7 : 0];
assign R_sth_data = R_rf_b[15 : 0];
assign E_st_data = (D_mem8)? {R_stb_data, R_stb_data, R_stb_data, R_stb_data} :
(D_mem16)? {R_sth_data, R_sth_data} :
R_rf_b;
assign E_mem_byte_en = ({D_iw_memsz, E_mem_baddr[1 : 0]} == {2'b00, 2'b00})? 4'b0001 :
({D_iw_memsz, E_mem_baddr[1 : 0]} == {2'b00, 2'b01})? 4'b0010 :
({D_iw_memsz, E_mem_baddr[1 : 0]} == {2'b00, 2'b10})? 4'b0100 :
({D_iw_memsz, E_mem_baddr[1 : 0]} == {2'b00, 2'b11})? 4'b1000 :
({D_iw_memsz, E_mem_baddr[1 : 0]} == {2'b01, 2'b00})? 4'b0011 :
({D_iw_memsz, E_mem_baddr[1 : 0]} == {2'b01, 2'b01})? 4'b0011 :
({D_iw_memsz, E_mem_baddr[1 : 0]} == {2'b01, 2'b10})? 4'b1100 :
({D_iw_memsz, E_mem_baddr[1 : 0]} == {2'b01, 2'b11})? 4'b1100 :
4'b1111;
assign d_read_nxt = (R_ctrl_ld & E_new_inst) | (d_read & d_waitrequest);
assign E_ld_stall = R_ctrl_ld & ((E_valid & ~av_ld_done) | E_new_inst);
assign d_write_nxt = (R_ctrl_st & E_new_inst) | (d_write & d_waitrequest);
assign E_st_stall = d_write_nxt;
assign d_address = W_mem_baddr;
assign av_ld_getting_data = d_read & ~d_waitrequest;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
d_read <= 0;
else
d_read <= d_read_nxt;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
d_writedata <= 0;
else
d_writedata <= E_st_data;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
d_byteenable <= 0;
else
d_byteenable <= E_mem_byte_en;
end
assign av_ld_align_cycle_nxt = av_ld_getting_data ? 0 : (av_ld_align_cycle+1);
assign av_ld_align_one_more_cycle = av_ld_align_cycle == (D_mem16 ? 2 : 3);
assign av_ld_aligning_data_nxt = av_ld_aligning_data ?
~av_ld_align_one_more_cycle :
(~D_mem32 & av_ld_getting_data);
assign av_ld_waiting_for_data_nxt = av_ld_waiting_for_data ?
~av_ld_getting_data :
(R_ctrl_ld & E_new_inst);
assign av_ld_done = ~av_ld_waiting_for_data_nxt & (D_mem32 | ~av_ld_aligning_data_nxt);
assign av_ld_rshift8 = av_ld_aligning_data &
(av_ld_align_cycle < (W_mem_baddr[1 : 0]));
assign av_ld_extend = av_ld_aligning_data;
assign av_ld_byte0_data_nxt = av_ld_rshift8 ? av_ld_byte1_data :
av_ld_extend ? av_ld_byte0_data :
d_readdata[7 : 0];
assign av_ld_byte1_data_nxt = av_ld_rshift8 ? av_ld_byte2_data :
av_ld_extend ? {8 {av_fill_bit}} :
d_readdata[15 : 8];
assign av_ld_byte2_data_nxt = av_ld_rshift8 ? av_ld_byte3_data :
av_ld_extend ? {8 {av_fill_bit}} :
d_readdata[23 : 16];
assign av_ld_byte3_data_nxt = av_ld_rshift8 ? av_ld_byte3_data :
av_ld_extend ? {8 {av_fill_bit}} :
d_readdata[31 : 24];
assign av_ld_byte1_data_en = ~(av_ld_extend & D_mem16 & ~av_ld_rshift8);
assign av_ld_data_aligned_unfiltered = {av_ld_byte3_data, av_ld_byte2_data,
av_ld_byte1_data, av_ld_byte0_data};
assign av_sign_bit = D_mem16 ? av_ld_byte1_data[7] : av_ld_byte0_data[7];
assign av_fill_bit = av_sign_bit & R_ctrl_ld_signed;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
av_ld_align_cycle <= 0;
else
av_ld_align_cycle <= av_ld_align_cycle_nxt;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
av_ld_waiting_for_data <= 0;
else
av_ld_waiting_for_data <= av_ld_waiting_for_data_nxt;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
av_ld_aligning_data <= 0;
else
av_ld_aligning_data <= av_ld_aligning_data_nxt;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
av_ld_byte0_data <= 0;
else
av_ld_byte0_data <= av_ld_byte0_data_nxt;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
av_ld_byte1_data <= 0;
else if (av_ld_byte1_data_en)
av_ld_byte1_data <= av_ld_byte1_data_nxt;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
av_ld_byte2_data <= 0;
else
av_ld_byte2_data <= av_ld_byte2_data_nxt;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
av_ld_byte3_data <= 0;
else
av_ld_byte3_data <= av_ld_byte3_data_nxt;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
W_valid <= 0;
else
W_valid <= E_valid & ~E_stall;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
W_control_rd_data <= 0;
else
W_control_rd_data <= E_control_rd_data;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
W_cmp_result <= 0;
else
W_cmp_result <= E_cmp_result;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
W_alu_result <= 0;
else
W_alu_result <= E_alu_result;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
W_status_reg_pie <= 0;
else
W_status_reg_pie <= W_status_reg_pie_nxt;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
W_estatus_reg <= 0;
else
W_estatus_reg <= W_estatus_reg_nxt;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
W_bstatus_reg <= 0;
else
W_bstatus_reg <= W_bstatus_reg_nxt;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
W_ienable_reg <= 0;
else
W_ienable_reg <= W_ienable_reg_nxt;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
W_ipending_reg <= 0;
else
W_ipending_reg <= W_ipending_reg_nxt;
end
assign W_cpuid_reg = 0;
assign W_wr_data_non_zero = R_ctrl_br_cmp ? W_cmp_result :
R_ctrl_rdctl_inst ? W_control_rd_data :
W_alu_result[31 : 0];
assign W_wr_data = W_wr_data_non_zero;
assign W_br_taken = R_ctrl_br & W_cmp_result;
assign W_mem_baddr = W_alu_result[28 : 0];
assign W_status_reg = W_status_reg_pie;
assign E_wrctl_status = R_ctrl_wrctl_inst &
(D_iw_control_regnum == 3'd0);
assign E_wrctl_estatus = R_ctrl_wrctl_inst &
(D_iw_control_regnum == 3'd1);
assign E_wrctl_bstatus = R_ctrl_wrctl_inst &
(D_iw_control_regnum == 3'd2);
assign E_wrctl_ienable = R_ctrl_wrctl_inst &
(D_iw_control_regnum == 3'd3);
assign W_status_reg_pie_inst_nxt = (R_ctrl_exception | R_ctrl_break | R_ctrl_crst) ? 1'b0 :
(D_op_eret) ? W_estatus_reg :
(D_op_bret) ? W_bstatus_reg :
(E_wrctl_status) ? E_src1[0] :
W_status_reg_pie;
assign W_status_reg_pie_nxt = E_valid ? W_status_reg_pie_inst_nxt : W_status_reg_pie;
assign W_estatus_reg_inst_nxt = (R_ctrl_crst) ? 0 :
(R_ctrl_exception) ? W_status_reg :
(E_wrctl_estatus) ? E_src1[0] :
W_estatus_reg;
assign W_estatus_reg_nxt = E_valid ? W_estatus_reg_inst_nxt : W_estatus_reg;
assign W_bstatus_reg_inst_nxt = (R_ctrl_break) ? W_status_reg :
(E_wrctl_bstatus) ? E_src1[0] :
W_bstatus_reg;
assign W_bstatus_reg_nxt = E_valid ? W_bstatus_reg_inst_nxt : W_bstatus_reg;
assign W_ienable_reg_nxt = ((E_wrctl_ienable & E_valid) ?
E_src1[31 : 0] : W_ienable_reg) & 32'b00000000000000000000000000000001;
assign W_ipending_reg_nxt = iactive & W_ienable_reg & oci_ienable & 32'b00000000000000000000000000000001;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
hbreak_enabled <= 1'b1;
else if (E_valid)
hbreak_enabled <= R_ctrl_break ? 1'b0 : D_op_bret ? 1'b1 : hbreak_enabled;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
d_write <= 0;
else
d_write <= d_write_nxt;
end
limbus_nios2_qsys_0_nios2_oci the_limbus_nios2_qsys_0_nios2_oci
(
.D_valid (D_valid),
.E_st_data (E_st_data),
.E_valid (E_valid),
.F_pc (F_pc),
.address_nxt (jtag_debug_module_address),
.av_ld_data_aligned_filtered (av_ld_data_aligned_filtered),
.byteenable_nxt (jtag_debug_module_byteenable),
.clk (jtag_debug_module_clk),
.d_address (d_address),
.d_read (d_read),
.d_waitrequest (d_waitrequest),
.d_write (d_write),
.debugaccess_nxt (jtag_debug_module_debugaccess),
.hbreak_enabled (hbreak_enabled),
.jtag_debug_module_debugaccess_to_roms (jtag_debug_module_debugaccess_to_roms),
.oci_hbreak_req (oci_hbreak_req),
.oci_ienable (oci_ienable),
.oci_single_step_mode (oci_single_step_mode),
.read_nxt (jtag_debug_module_read),
.readdata (jtag_debug_module_readdata),
.reset (jtag_debug_module_reset),
.reset_n (reset_n),
.reset_req (reset_req),
.resetrequest (jtag_debug_module_resetrequest),
.test_ending (test_ending),
.test_has_ended (test_has_ended),
.waitrequest (jtag_debug_module_waitrequest),
.write_nxt (jtag_debug_module_write),
.writedata_nxt (jtag_debug_module_writedata)
);
//jtag_debug_module, which is an e_avalon_slave
assign jtag_debug_module_clk = clk;
assign jtag_debug_module_reset = ~reset_n;
assign D_ctrl_custom = 1'b0;
assign R_ctrl_custom_nxt = D_ctrl_custom;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_custom <= 0;
else if (R_en)
R_ctrl_custom <= R_ctrl_custom_nxt;
end
assign D_ctrl_custom_multi = 1'b0;
assign R_ctrl_custom_multi_nxt = D_ctrl_custom_multi;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_custom_multi <= 0;
else if (R_en)
R_ctrl_custom_multi <= R_ctrl_custom_multi_nxt;
end
assign D_ctrl_jmp_indirect = D_op_eret|
D_op_bret|
D_op_rsvx17|
D_op_rsvx25|
D_op_ret|
D_op_jmp|
D_op_rsvx21|
D_op_callr;
assign R_ctrl_jmp_indirect_nxt = D_ctrl_jmp_indirect;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_jmp_indirect <= 0;
else if (R_en)
R_ctrl_jmp_indirect <= R_ctrl_jmp_indirect_nxt;
end
assign D_ctrl_jmp_direct = D_op_call|D_op_jmpi;
assign R_ctrl_jmp_direct_nxt = D_ctrl_jmp_direct;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_jmp_direct <= 0;
else if (R_en)
R_ctrl_jmp_direct <= R_ctrl_jmp_direct_nxt;
end
assign D_ctrl_implicit_dst_retaddr = D_op_call|D_op_rsv02;
assign R_ctrl_implicit_dst_retaddr_nxt = D_ctrl_implicit_dst_retaddr;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_implicit_dst_retaddr <= 0;
else if (R_en)
R_ctrl_implicit_dst_retaddr <= R_ctrl_implicit_dst_retaddr_nxt;
end
assign D_ctrl_implicit_dst_eretaddr = D_op_div|D_op_divu|D_op_mul|D_op_muli|D_op_mulxss|D_op_mulxsu|D_op_mulxuu;
assign R_ctrl_implicit_dst_eretaddr_nxt = D_ctrl_implicit_dst_eretaddr;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_implicit_dst_eretaddr <= 0;
else if (R_en)
R_ctrl_implicit_dst_eretaddr <= R_ctrl_implicit_dst_eretaddr_nxt;
end
assign D_ctrl_exception = D_op_trap|
D_op_rsvx44|
D_op_div|
D_op_divu|
D_op_mul|
D_op_muli|
D_op_mulxss|
D_op_mulxsu|
D_op_mulxuu|
D_op_intr|
D_op_rsvx60;
assign R_ctrl_exception_nxt = D_ctrl_exception;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_exception <= 0;
else if (R_en)
R_ctrl_exception <= R_ctrl_exception_nxt;
end
assign D_ctrl_break = D_op_break|D_op_hbreak;
assign R_ctrl_break_nxt = D_ctrl_break;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_break <= 0;
else if (R_en)
R_ctrl_break <= R_ctrl_break_nxt;
end
assign D_ctrl_crst = D_op_crst|D_op_rsvx63;
assign R_ctrl_crst_nxt = D_ctrl_crst;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_crst <= 0;
else if (R_en)
R_ctrl_crst <= R_ctrl_crst_nxt;
end
assign D_ctrl_uncond_cti_non_br = D_op_call|
D_op_jmpi|
D_op_eret|
D_op_bret|
D_op_rsvx17|
D_op_rsvx25|
D_op_ret|
D_op_jmp|
D_op_rsvx21|
D_op_callr;
assign R_ctrl_uncond_cti_non_br_nxt = D_ctrl_uncond_cti_non_br;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_uncond_cti_non_br <= 0;
else if (R_en)
R_ctrl_uncond_cti_non_br <= R_ctrl_uncond_cti_non_br_nxt;
end
assign D_ctrl_retaddr = D_op_call|
D_op_rsv02|
D_op_nextpc|
D_op_callr|
D_op_trap|
D_op_rsvx44|
D_op_div|
D_op_divu|
D_op_mul|
D_op_muli|
D_op_mulxss|
D_op_mulxsu|
D_op_mulxuu|
D_op_intr|
D_op_rsvx60|
D_op_break|
D_op_hbreak;
assign R_ctrl_retaddr_nxt = D_ctrl_retaddr;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_retaddr <= 0;
else if (R_en)
R_ctrl_retaddr <= R_ctrl_retaddr_nxt;
end
assign D_ctrl_shift_logical = D_op_slli|D_op_sll|D_op_srli|D_op_srl;
assign R_ctrl_shift_logical_nxt = D_ctrl_shift_logical;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_shift_logical <= 0;
else if (R_en)
R_ctrl_shift_logical <= R_ctrl_shift_logical_nxt;
end
assign D_ctrl_shift_right_arith = D_op_srai|D_op_sra;
assign R_ctrl_shift_right_arith_nxt = D_ctrl_shift_right_arith;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_shift_right_arith <= 0;
else if (R_en)
R_ctrl_shift_right_arith <= R_ctrl_shift_right_arith_nxt;
end
assign D_ctrl_rot_right = D_op_rsvx10|D_op_ror|D_op_rsvx42|D_op_rsvx43;
assign R_ctrl_rot_right_nxt = D_ctrl_rot_right;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_rot_right <= 0;
else if (R_en)
R_ctrl_rot_right <= R_ctrl_rot_right_nxt;
end
assign D_ctrl_shift_rot_right = D_op_srli|
D_op_srl|
D_op_srai|
D_op_sra|
D_op_rsvx10|
D_op_ror|
D_op_rsvx42|
D_op_rsvx43;
assign R_ctrl_shift_rot_right_nxt = D_ctrl_shift_rot_right;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_shift_rot_right <= 0;
else if (R_en)
R_ctrl_shift_rot_right <= R_ctrl_shift_rot_right_nxt;
end
assign D_ctrl_shift_rot = D_op_slli|
D_op_rsvx50|
D_op_sll|
D_op_rsvx51|
D_op_roli|
D_op_rsvx34|
D_op_rol|
D_op_rsvx35|
D_op_srli|
D_op_srl|
D_op_srai|
D_op_sra|
D_op_rsvx10|
D_op_ror|
D_op_rsvx42|
D_op_rsvx43;
assign R_ctrl_shift_rot_nxt = D_ctrl_shift_rot;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_shift_rot <= 0;
else if (R_en)
R_ctrl_shift_rot <= R_ctrl_shift_rot_nxt;
end
assign D_ctrl_logic = D_op_and|
D_op_or|
D_op_xor|
D_op_nor|
D_op_andhi|
D_op_orhi|
D_op_xorhi|
D_op_andi|
D_op_ori|
D_op_xori;
assign R_ctrl_logic_nxt = D_ctrl_logic;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_logic <= 0;
else if (R_en)
R_ctrl_logic <= R_ctrl_logic_nxt;
end
assign D_ctrl_hi_imm16 = D_op_andhi|D_op_orhi|D_op_xorhi;
assign R_ctrl_hi_imm16_nxt = D_ctrl_hi_imm16;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_hi_imm16 <= 0;
else if (R_en)
R_ctrl_hi_imm16 <= R_ctrl_hi_imm16_nxt;
end
assign D_ctrl_unsigned_lo_imm16 = D_op_cmpgeui|
D_op_cmpltui|
D_op_andi|
D_op_ori|
D_op_xori|
D_op_roli|
D_op_rsvx10|
D_op_slli|
D_op_srli|
D_op_rsvx34|
D_op_rsvx42|
D_op_rsvx50|
D_op_srai;
assign R_ctrl_unsigned_lo_imm16_nxt = D_ctrl_unsigned_lo_imm16;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_unsigned_lo_imm16 <= 0;
else if (R_en)
R_ctrl_unsigned_lo_imm16 <= R_ctrl_unsigned_lo_imm16_nxt;
end
assign D_ctrl_br_uncond = D_op_br|D_op_rsv02;
assign R_ctrl_br_uncond_nxt = D_ctrl_br_uncond;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_br_uncond <= 0;
else if (R_en)
R_ctrl_br_uncond <= R_ctrl_br_uncond_nxt;
end
assign D_ctrl_br = D_op_br|
D_op_bge|
D_op_blt|
D_op_bne|
D_op_beq|
D_op_bgeu|
D_op_bltu|
D_op_rsv62;
assign R_ctrl_br_nxt = D_ctrl_br;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_br <= 0;
else if (R_en)
R_ctrl_br <= R_ctrl_br_nxt;
end
assign D_ctrl_alu_subtract = D_op_sub|
D_op_rsvx25|
D_op_cmplti|
D_op_cmpltui|
D_op_cmplt|
D_op_cmpltu|
D_op_blt|
D_op_bltu|
D_op_cmpgei|
D_op_cmpgeui|
D_op_cmpge|
D_op_cmpgeu|
D_op_bge|
D_op_rsv10|
D_op_bgeu|
D_op_rsv42;
assign R_ctrl_alu_subtract_nxt = D_ctrl_alu_subtract;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_alu_subtract <= 0;
else if (R_en)
R_ctrl_alu_subtract <= R_ctrl_alu_subtract_nxt;
end
assign D_ctrl_alu_signed_comparison = D_op_cmpge|D_op_cmpgei|D_op_cmplt|D_op_cmplti|D_op_bge|D_op_blt;
assign R_ctrl_alu_signed_comparison_nxt = D_ctrl_alu_signed_comparison;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_alu_signed_comparison <= 0;
else if (R_en)
R_ctrl_alu_signed_comparison <= R_ctrl_alu_signed_comparison_nxt;
end
assign D_ctrl_br_cmp = D_op_br|
D_op_bge|
D_op_blt|
D_op_bne|
D_op_beq|
D_op_bgeu|
D_op_bltu|
D_op_rsv62|
D_op_cmpgei|
D_op_cmplti|
D_op_cmpnei|
D_op_cmpgeui|
D_op_cmpltui|
D_op_cmpeqi|
D_op_rsvx00|
D_op_cmpge|
D_op_cmplt|
D_op_cmpne|
D_op_cmpgeu|
D_op_cmpltu|
D_op_cmpeq|
D_op_rsvx56;
assign R_ctrl_br_cmp_nxt = D_ctrl_br_cmp;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_br_cmp <= 0;
else if (R_en)
R_ctrl_br_cmp <= R_ctrl_br_cmp_nxt;
end
assign D_ctrl_ld_signed = D_op_ldb|
D_op_ldh|
D_op_ldl|
D_op_ldw|
D_op_ldbio|
D_op_ldhio|
D_op_ldwio|
D_op_rsv63;
assign R_ctrl_ld_signed_nxt = D_ctrl_ld_signed;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_ld_signed <= 0;
else if (R_en)
R_ctrl_ld_signed <= R_ctrl_ld_signed_nxt;
end
assign D_ctrl_ld = D_op_ldb|
D_op_ldh|
D_op_ldl|
D_op_ldw|
D_op_ldbio|
D_op_ldhio|
D_op_ldwio|
D_op_rsv63|
D_op_ldbu|
D_op_ldhu|
D_op_ldbuio|
D_op_ldhuio;
assign R_ctrl_ld_nxt = D_ctrl_ld;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_ld <= 0;
else if (R_en)
R_ctrl_ld <= R_ctrl_ld_nxt;
end
assign D_ctrl_ld_non_io = D_op_ldbu|D_op_ldhu|D_op_ldb|D_op_ldh|D_op_ldw|D_op_ldl;
assign R_ctrl_ld_non_io_nxt = D_ctrl_ld_non_io;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_ld_non_io <= 0;
else if (R_en)
R_ctrl_ld_non_io <= R_ctrl_ld_non_io_nxt;
end
assign D_ctrl_st = D_op_stb|
D_op_sth|
D_op_stw|
D_op_stc|
D_op_stbio|
D_op_sthio|
D_op_stwio|
D_op_rsv61;
assign R_ctrl_st_nxt = D_ctrl_st;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_st <= 0;
else if (R_en)
R_ctrl_st <= R_ctrl_st_nxt;
end
assign D_ctrl_ld_io = D_op_ldbuio|D_op_ldhuio|D_op_ldbio|D_op_ldhio|D_op_ldwio|D_op_rsv63;
assign R_ctrl_ld_io_nxt = D_ctrl_ld_io;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_ld_io <= 0;
else if (R_en)
R_ctrl_ld_io <= R_ctrl_ld_io_nxt;
end
assign D_ctrl_b_is_dst = D_op_addi|
D_op_andhi|
D_op_orhi|
D_op_xorhi|
D_op_andi|
D_op_ori|
D_op_xori|
D_op_call|
D_op_rdprs|
D_op_cmpgei|
D_op_cmplti|
D_op_cmpnei|
D_op_cmpgeui|
D_op_cmpltui|
D_op_cmpeqi|
D_op_jmpi|
D_op_rsv09|
D_op_rsv17|
D_op_rsv25|
D_op_rsv33|
D_op_rsv41|
D_op_rsv49|
D_op_rsv57|
D_op_ldb|
D_op_ldh|
D_op_ldl|
D_op_ldw|
D_op_ldbio|
D_op_ldhio|
D_op_ldwio|
D_op_rsv63|
D_op_ldbu|
D_op_ldhu|
D_op_ldbuio|
D_op_ldhuio|
D_op_initd|
D_op_initda|
D_op_flushd|
D_op_flushda;
assign R_ctrl_b_is_dst_nxt = D_ctrl_b_is_dst;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_b_is_dst <= 0;
else if (R_en)
R_ctrl_b_is_dst <= R_ctrl_b_is_dst_nxt;
end
assign D_ctrl_ignore_dst = D_op_br|
D_op_bge|
D_op_blt|
D_op_bne|
D_op_beq|
D_op_bgeu|
D_op_bltu|
D_op_rsv62|
D_op_stb|
D_op_sth|
D_op_stw|
D_op_stc|
D_op_stbio|
D_op_sthio|
D_op_stwio|
D_op_rsv61|
D_op_jmpi|
D_op_rsv09|
D_op_rsv17|
D_op_rsv25|
D_op_rsv33|
D_op_rsv41|
D_op_rsv49|
D_op_rsv57;
assign R_ctrl_ignore_dst_nxt = D_ctrl_ignore_dst;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_ignore_dst <= 0;
else if (R_en)
R_ctrl_ignore_dst <= R_ctrl_ignore_dst_nxt;
end
assign D_ctrl_src2_choose_imm = D_op_addi|
D_op_andhi|
D_op_orhi|
D_op_xorhi|
D_op_andi|
D_op_ori|
D_op_xori|
D_op_call|
D_op_rdprs|
D_op_cmpgei|
D_op_cmplti|
D_op_cmpnei|
D_op_cmpgeui|
D_op_cmpltui|
D_op_cmpeqi|
D_op_jmpi|
D_op_rsv09|
D_op_rsv17|
D_op_rsv25|
D_op_rsv33|
D_op_rsv41|
D_op_rsv49|
D_op_rsv57|
D_op_ldb|
D_op_ldh|
D_op_ldl|
D_op_ldw|
D_op_ldbio|
D_op_ldhio|
D_op_ldwio|
D_op_rsv63|
D_op_ldbu|
D_op_ldhu|
D_op_ldbuio|
D_op_ldhuio|
D_op_initd|
D_op_initda|
D_op_flushd|
D_op_flushda|
D_op_stb|
D_op_sth|
D_op_stw|
D_op_stc|
D_op_stbio|
D_op_sthio|
D_op_stwio|
D_op_rsv61|
D_op_roli|
D_op_rsvx10|
D_op_slli|
D_op_srli|
D_op_rsvx34|
D_op_rsvx42|
D_op_rsvx50|
D_op_srai;
assign R_ctrl_src2_choose_imm_nxt = D_ctrl_src2_choose_imm;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_src2_choose_imm <= 0;
else if (R_en)
R_ctrl_src2_choose_imm <= R_ctrl_src2_choose_imm_nxt;
end
assign D_ctrl_wrctl_inst = D_op_wrctl;
assign R_ctrl_wrctl_inst_nxt = D_ctrl_wrctl_inst;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_wrctl_inst <= 0;
else if (R_en)
R_ctrl_wrctl_inst <= R_ctrl_wrctl_inst_nxt;
end
assign D_ctrl_rdctl_inst = D_op_rdctl;
assign R_ctrl_rdctl_inst_nxt = D_ctrl_rdctl_inst;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_rdctl_inst <= 0;
else if (R_en)
R_ctrl_rdctl_inst <= R_ctrl_rdctl_inst_nxt;
end
assign D_ctrl_force_src2_zero = D_op_call|
D_op_rsv02|
D_op_nextpc|
D_op_callr|
D_op_trap|
D_op_rsvx44|
D_op_intr|
D_op_rsvx60|
D_op_break|
D_op_hbreak|
D_op_eret|
D_op_bret|
D_op_rsvx17|
D_op_rsvx25|
D_op_ret|
D_op_jmp|
D_op_rsvx21|
D_op_jmpi;
assign R_ctrl_force_src2_zero_nxt = D_ctrl_force_src2_zero;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_force_src2_zero <= 0;
else if (R_en)
R_ctrl_force_src2_zero <= R_ctrl_force_src2_zero_nxt;
end
assign D_ctrl_alu_force_xor = D_op_cmpgei|
D_op_cmpgeui|
D_op_cmpeqi|
D_op_cmpge|
D_op_cmpgeu|
D_op_cmpeq|
D_op_cmpnei|
D_op_cmpne|
D_op_bge|
D_op_rsv10|
D_op_bgeu|
D_op_rsv42|
D_op_beq|
D_op_rsv34|
D_op_bne|
D_op_rsv62|
D_op_br|
D_op_rsv02;
assign R_ctrl_alu_force_xor_nxt = D_ctrl_alu_force_xor;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_alu_force_xor <= 0;
else if (R_en)
R_ctrl_alu_force_xor <= R_ctrl_alu_force_xor_nxt;
end
//data_master, which is an e_avalon_master
//instruction_master, which is an e_avalon_master
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
assign F_inst = (F_op_call)? 56'h20202063616c6c :
(F_op_jmpi)? 56'h2020206a6d7069 :
(F_op_ldbu)? 56'h2020206c646275 :
(F_op_addi)? 56'h20202061646469 :
(F_op_stb)? 56'h20202020737462 :
(F_op_br)? 56'h20202020206272 :
(F_op_ldb)? 56'h202020206c6462 :
(F_op_cmpgei)? 56'h20636d70676569 :
(F_op_ldhu)? 56'h2020206c646875 :
(F_op_andi)? 56'h202020616e6469 :
(F_op_sth)? 56'h20202020737468 :
(F_op_bge)? 56'h20202020626765 :
(F_op_ldh)? 56'h202020206c6468 :
(F_op_cmplti)? 56'h20636d706c7469 :
(F_op_initda)? 56'h20696e69746461 :
(F_op_ori)? 56'h202020206f7269 :
(F_op_stw)? 56'h20202020737477 :
(F_op_blt)? 56'h20202020626c74 :
(F_op_ldw)? 56'h202020206c6477 :
(F_op_cmpnei)? 56'h20636d706e6569 :
(F_op_flushda)? 56'h666c7573686461 :
(F_op_xori)? 56'h202020786f7269 :
(F_op_bne)? 56'h20202020626e65 :
(F_op_cmpeqi)? 56'h20636d70657169 :
(F_op_ldbuio)? 56'h206c646275696f :
(F_op_muli)? 56'h2020206d756c69 :
(F_op_stbio)? 56'h2020737462696f :
(F_op_beq)? 56'h20202020626571 :
(F_op_ldbio)? 56'h20206c6462696f :
(F_op_cmpgeui)? 56'h636d7067657569 :
(F_op_ldhuio)? 56'h206c646875696f :
(F_op_andhi)? 56'h2020616e646869 :
(F_op_sthio)? 56'h2020737468696f :
(F_op_bgeu)? 56'h20202062676575 :
(F_op_ldhio)? 56'h20206c6468696f :
(F_op_cmpltui)? 56'h636d706c747569 :
(F_op_initd)? 56'h2020696e697464 :
(F_op_orhi)? 56'h2020206f726869 :
(F_op_stwio)? 56'h2020737477696f :
(F_op_bltu)? 56'h202020626c7475 :
(F_op_ldwio)? 56'h20206c6477696f :
(F_op_flushd)? 56'h20666c75736864 :
(F_op_xorhi)? 56'h2020786f726869 :
(F_op_eret)? 56'h20202065726574 :
(F_op_roli)? 56'h202020726f6c69 :
(F_op_rol)? 56'h20202020726f6c :
(F_op_flushp)? 56'h20666c75736870 :
(F_op_ret)? 56'h20202020726574 :
(F_op_nor)? 56'h202020206e6f72 :
(F_op_mulxuu)? 56'h206d756c787575 :
(F_op_cmpge)? 56'h2020636d706765 :
(F_op_bret)? 56'h20202062726574 :
(F_op_ror)? 56'h20202020726f72 :
(F_op_flushi)? 56'h20666c75736869 :
(F_op_jmp)? 56'h202020206a6d70 :
(F_op_and)? 56'h20202020616e64 :
(F_op_cmplt)? 56'h2020636d706c74 :
(F_op_slli)? 56'h202020736c6c69 :
(F_op_sll)? 56'h20202020736c6c :
(F_op_or)? 56'h20202020206f72 :
(F_op_mulxsu)? 56'h206d756c787375 :
(F_op_cmpne)? 56'h2020636d706e65 :
(F_op_srli)? 56'h20202073726c69 :
(F_op_srl)? 56'h2020202073726c :
(F_op_nextpc)? 56'h206e6578747063 :
(F_op_callr)? 56'h202063616c6c72 :
(F_op_xor)? 56'h20202020786f72 :
(F_op_mulxss)? 56'h206d756c787373 :
(F_op_cmpeq)? 56'h2020636d706571 :
(F_op_divu)? 56'h20202064697675 :
(F_op_div)? 56'h20202020646976 :
(F_op_rdctl)? 56'h2020726463746c :
(F_op_mul)? 56'h202020206d756c :
(F_op_cmpgeu)? 56'h20636d70676575 :
(F_op_initi)? 56'h2020696e697469 :
(F_op_trap)? 56'h20202074726170 :
(F_op_wrctl)? 56'h2020777263746c :
(F_op_cmpltu)? 56'h20636d706c7475 :
(F_op_add)? 56'h20202020616464 :
(F_op_break)? 56'h2020627265616b :
(F_op_hbreak)? 56'h2068627265616b :
(F_op_sync)? 56'h20202073796e63 :
(F_op_sub)? 56'h20202020737562 :
(F_op_srai)? 56'h20202073726169 :
(F_op_sra)? 56'h20202020737261 :
(F_op_intr)? 56'h202020696e7472 :
56'h20202020424144;
assign D_inst = (D_op_call)? 56'h20202063616c6c :
(D_op_jmpi)? 56'h2020206a6d7069 :
(D_op_ldbu)? 56'h2020206c646275 :
(D_op_addi)? 56'h20202061646469 :
(D_op_stb)? 56'h20202020737462 :
(D_op_br)? 56'h20202020206272 :
(D_op_ldb)? 56'h202020206c6462 :
(D_op_cmpgei)? 56'h20636d70676569 :
(D_op_ldhu)? 56'h2020206c646875 :
(D_op_andi)? 56'h202020616e6469 :
(D_op_sth)? 56'h20202020737468 :
(D_op_bge)? 56'h20202020626765 :
(D_op_ldh)? 56'h202020206c6468 :
(D_op_cmplti)? 56'h20636d706c7469 :
(D_op_initda)? 56'h20696e69746461 :
(D_op_ori)? 56'h202020206f7269 :
(D_op_stw)? 56'h20202020737477 :
(D_op_blt)? 56'h20202020626c74 :
(D_op_ldw)? 56'h202020206c6477 :
(D_op_cmpnei)? 56'h20636d706e6569 :
(D_op_flushda)? 56'h666c7573686461 :
(D_op_xori)? 56'h202020786f7269 :
(D_op_bne)? 56'h20202020626e65 :
(D_op_cmpeqi)? 56'h20636d70657169 :
(D_op_ldbuio)? 56'h206c646275696f :
(D_op_muli)? 56'h2020206d756c69 :
(D_op_stbio)? 56'h2020737462696f :
(D_op_beq)? 56'h20202020626571 :
(D_op_ldbio)? 56'h20206c6462696f :
(D_op_cmpgeui)? 56'h636d7067657569 :
(D_op_ldhuio)? 56'h206c646875696f :
(D_op_andhi)? 56'h2020616e646869 :
(D_op_sthio)? 56'h2020737468696f :
(D_op_bgeu)? 56'h20202062676575 :
(D_op_ldhio)? 56'h20206c6468696f :
(D_op_cmpltui)? 56'h636d706c747569 :
(D_op_initd)? 56'h2020696e697464 :
(D_op_orhi)? 56'h2020206f726869 :
(D_op_stwio)? 56'h2020737477696f :
(D_op_bltu)? 56'h202020626c7475 :
(D_op_ldwio)? 56'h20206c6477696f :
(D_op_flushd)? 56'h20666c75736864 :
(D_op_xorhi)? 56'h2020786f726869 :
(D_op_eret)? 56'h20202065726574 :
(D_op_roli)? 56'h202020726f6c69 :
(D_op_rol)? 56'h20202020726f6c :
(D_op_flushp)? 56'h20666c75736870 :
(D_op_ret)? 56'h20202020726574 :
(D_op_nor)? 56'h202020206e6f72 :
(D_op_mulxuu)? 56'h206d756c787575 :
(D_op_cmpge)? 56'h2020636d706765 :
(D_op_bret)? 56'h20202062726574 :
(D_op_ror)? 56'h20202020726f72 :
(D_op_flushi)? 56'h20666c75736869 :
(D_op_jmp)? 56'h202020206a6d70 :
(D_op_and)? 56'h20202020616e64 :
(D_op_cmplt)? 56'h2020636d706c74 :
(D_op_slli)? 56'h202020736c6c69 :
(D_op_sll)? 56'h20202020736c6c :
(D_op_or)? 56'h20202020206f72 :
(D_op_mulxsu)? 56'h206d756c787375 :
(D_op_cmpne)? 56'h2020636d706e65 :
(D_op_srli)? 56'h20202073726c69 :
(D_op_srl)? 56'h2020202073726c :
(D_op_nextpc)? 56'h206e6578747063 :
(D_op_callr)? 56'h202063616c6c72 :
(D_op_xor)? 56'h20202020786f72 :
(D_op_mulxss)? 56'h206d756c787373 :
(D_op_cmpeq)? 56'h2020636d706571 :
(D_op_divu)? 56'h20202064697675 :
(D_op_div)? 56'h20202020646976 :
(D_op_rdctl)? 56'h2020726463746c :
(D_op_mul)? 56'h202020206d756c :
(D_op_cmpgeu)? 56'h20636d70676575 :
(D_op_initi)? 56'h2020696e697469 :
(D_op_trap)? 56'h20202074726170 :
(D_op_wrctl)? 56'h2020777263746c :
(D_op_cmpltu)? 56'h20636d706c7475 :
(D_op_add)? 56'h20202020616464 :
(D_op_break)? 56'h2020627265616b :
(D_op_hbreak)? 56'h2068627265616b :
(D_op_sync)? 56'h20202073796e63 :
(D_op_sub)? 56'h20202020737562 :
(D_op_srai)? 56'h20202073726169 :
(D_op_sra)? 56'h20202020737261 :
(D_op_intr)? 56'h202020696e7472 :
56'h20202020424144;
assign F_vinst = F_valid ? F_inst : {7{8'h2d}};
assign D_vinst = D_valid ? D_inst : {7{8'h2d}};
assign R_vinst = R_valid ? D_inst : {7{8'h2d}};
assign E_vinst = E_valid ? D_inst : {7{8'h2d}};
assign W_vinst = W_valid ? D_inst : {7{8'h2d}};
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
endmodule
|
module sky130_fd_sc_lp__nand3_m (
Y ,
A ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__nand3 base (
.Y(Y),
.A(A),
.B(B),
.C(C),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
|
module sky130_fd_sc_lp__nand3_m (
Y,
A,
B,
C
);
output Y;
input A;
input B;
input C;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__nand3 base (
.Y(Y),
.A(A),
.B(B),
.C(C)
);
endmodule
|
module ddr3 (
rst_n,
ck,
ck_n,
cke,
cs_n,
ras_n,
cas_n,
we_n,
dm_tdqs,
ba,
addr,
dq,
dqs,
dqs_n,
tdqs_n,
odt
);
`define x1Gb
`define sg187E
`define x16
/* `include "ddr3_model_parameters.vh" */
/****************************************************************************************
*
* Disclaimer This software code and all associated documentation, comments or other
* of Warranty: information (collectively "Software") is provided "AS IS" without
* warranty of any kind. MICRON TECHNOLOGY, INC. ("MTI") EXPRESSLY
* DISCLAIMS ALL WARRANTIES EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED
* TO, NONINFRINGEMENT OF THIRD PARTY RIGHTS, AND ANY IMPLIED WARRANTIES
* OF MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. MTI DOES NOT
* WARRANT THAT THE SOFTWARE WILL MEET YOUR REQUIREMENTS, OR THAT THE
* OPERATION OF THE SOFTWARE WILL BE UNINTERRUPTED OR ERROR-FREE.
* FURTHERMORE, MTI DOES NOT MAKE ANY REPRESENTATIONS REGARDING THE USE OR
* THE RESULTS OF THE USE OF THE SOFTWARE IN TERMS OF ITS CORRECTNESS,
* ACCURACY, RELIABILITY, OR OTHERWISE. THE ENTIRE RISK ARISING OUT OF USE
* OR PERFORMANCE OF THE SOFTWARE REMAINS WITH YOU. IN NO EVENT SHALL MTI,
* ITS AFFILIATED COMPANIES OR THEIR SUPPLIERS BE LIABLE FOR ANY DIRECT,
* INDIRECT, CONSEQUENTIAL, INCIDENTAL, OR SPECIAL DAMAGES (INCLUDING,
* WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS INTERRUPTION,
* OR LOSS OF INFORMATION) ARISING OUT OF YOUR USE OF OR INABILITY TO USE
* THE SOFTWARE, EVEN IF MTI HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH
* DAMAGES. Because some jurisdictions prohibit the exclusion or
* limitation of liability for consequential or incidental damages, the
* above limitation may not apply to you.
*
* Copyright 2003 Micron Technology, Inc. All rights reserved.
*
****************************************************************************************/
// Parameters current with 1Gb and 2Gb datasheet rev D
// Timing parameters based on Speed Grade
// SYMBOL UNITS DESCRIPTION
// ------ ----- -----------
`ifdef x1Gb // 1Gb parameters
`ifdef sg094E // sg094E is equivalent to the JEDEC DDR3-2133 (13-13-13) speed bin
parameter TCK_MIN = 937.5; // tCK ps Minimum Clock Cycle Time
parameter TJIT_PER = 50; // tJIT(per) ps Period JItter
parameter TJIT_CC = 100; // tJIT(cc) ps Cycle to Cycle jitter
parameter TERR_2PER = 73; // tERR(2per) ps Accumulated Error (2-cycle)
parameter TERR_3PER = 85; // tERR(3per) ps Accumulated Error (3-cycle)
parameter TERR_4PER = 98; // tERR(4per) ps Accumulated Error (4-cycle)
parameter TERR_5PER = 105; // tERR(5per) ps Accumulated Error (5-cycle)
parameter TERR_6PER = 111; // tERR(6per) ps Accumulated Error (6-cycle)
parameter TERR_7PER = 117; // tERR(7per) ps Accumulated Error (7-cycle)
parameter TERR_8PER = 121; // tERR(8per) ps Accumulated Error (8-cycle)
parameter TERR_9PER = 125; // tERR(9per) ps Accumulated Error (9-cycle)
parameter TERR_10PER = 128; // tERR(10per)ps Accumulated Error (10-cycle)
parameter TERR_11PER = 132; // tERR(11per)ps Accumulated Error (11-cycle)
parameter TERR_12PER = 134; // tERR(12per)ps Accumulated Error (12-cycle)
parameter TDS = 5; // tDS ps DQ and DM input setup time relative to DQS
parameter TDH = 20; // tDH ps DQ and DM input hold time relative to DQS
parameter TDQSQ = 70; // tDQSQ ps DQS-DQ skew, DQS to last DQ valid, per group, per access
parameter TDQSS = 0.27; // tDQSS tCK Rising clock edge to DQS/DQS# latching transition
parameter TDSS = 0.18; // tDSS tCK DQS falling edge to CLK rising (setup time)
parameter TDSH = 0.18; // tDSH tCK DQS falling edge from CLK rising (hold time)
parameter TDQSCK = 175; // tDQSCK ps DQS output access time from CK/CK#
parameter TQSH = 0.40; // tQSH tCK DQS Output High Pulse Width
parameter TQSL = 0.40; // tQSL tCK DQS Output Low Pulse Width
parameter TDIPW = 275; // tDIPW ps DQ and DM input Pulse Width
parameter TIPW = 455; // tIPW ps Control and Address input Pulse Width
parameter TIS = 35; // tIS ps Input Setup Time
parameter TIH = 75; // tIH ps Input Hold Time
parameter TRAS_MIN = 35000; // tRAS ps Minimum Active to Precharge command time
parameter TRC = 46250; // tRC ps Active to Active/Auto Refresh command time
parameter TRCD = 12187; // tRCD ps Active to Read/Write command time
parameter TRP = 12187; // tRP ps Precharge command period
parameter TXP = 6000; // tXP ps Exit power down to a valid command
parameter TCKE = 5000; // tCKE ps CKE minimum high or low pulse width
parameter TAON = 180; // tAON ps RTT turn-on from ODTLon reference
parameter TWLS = 122; // tWLS ps Setup time for tDQS flop
parameter TWLH = 122; // tWLH ps Hold time of tDQS flop
parameter TWLO = 7500; // tWLO ps Write levelization output delay
parameter TAA_MIN = 12187; // TAA ps Internal READ command to first data
parameter CL_TIME = 12187; // CL ps Minimum CAS Latency
`else `ifdef sg094 // sg094 is equivalent to the JEDEC DDR3-2133 (14-14-14) speed bin
parameter TCK_MIN = 937.5; // tCK ps Minimum Clock Cycle Time
parameter TJIT_PER = 50; // tJIT(per) ps Period JItter
parameter TJIT_CC = 100; // tJIT(cc) ps Cycle to Cycle jitter
parameter TERR_2PER = 73; // tERR(2per) ps Accumulated Error (2-cycle)
parameter TERR_3PER = 85; // tERR(3per) ps Accumulated Error (3-cycle)
parameter TERR_4PER = 98; // tERR(4per) ps Accumulated Error (4-cycle)
parameter TERR_5PER = 105; // tERR(5per) ps Accumulated Error (5-cycle)
parameter TERR_6PER = 111; // tERR(6per) ps Accumulated Error (6-cycle)
parameter TERR_7PER = 117; // tERR(7per) ps Accumulated Error (7-cycle)
parameter TERR_8PER = 121; // tERR(8per) ps Accumulated Error (8-cycle)
parameter TERR_9PER = 125; // tERR(9per) ps Accumulated Error (9-cycle)
parameter TERR_10PER = 128; // tERR(10per)ps Accumulated Error (10-cycle)
parameter TERR_11PER = 132; // tERR(11per)ps Accumulated Error (11-cycle)
parameter TERR_12PER = 134; // tERR(12per)ps Accumulated Error (12-cycle)
parameter TDS = 5; // tDS ps DQ and DM input setup time relative to DQS
parameter TDH = 20; // tDH ps DQ and DM input hold time relative to DQS
parameter TDQSQ = 70; // tDQSQ ps DQS-DQ skew, DQS to last DQ valid, per group, per access
parameter TDQSS = 0.27; // tDQSS tCK Rising clock edge to DQS/DQS# latching transition
parameter TDSS = 0.18; // tDSS tCK DQS falling edge to CLK rising (setup time)
parameter TDSH = 0.18; // tDSH tCK DQS falling edge from CLK rising (hold time)
parameter TDQSCK = 175; // tDQSCK ps DQS output access time from CK/CK#
parameter TQSH = 0.40; // tQSH tCK DQS Output High Pulse Width
parameter TQSL = 0.40; // tQSL tCK DQS Output Low Pulse Width
parameter TDIPW = 275; // tDIPW ps DQ and DM input Pulse Width
parameter TIPW = 455; // tIPW ps Control and Address input Pulse Width
parameter TIS = 35; // tIS ps Input Setup Time
parameter TIH = 75; // tIH ps Input Hold Time
parameter TRAS_MIN = 35000; // tRAS ps Minimum Active to Precharge command time
parameter TRC = 46250; // tRC ps Active to Active/Auto Refresh command time
parameter TRCD = 13125; // tRCD ps Active to Read/Write command time
parameter TRP = 13125; // tRP ps Precharge command period
parameter TXP = 6000; // tXP ps Exit power down to a valid command
parameter TCKE = 5000; // tCKE ps CKE minimum high or low pulse width
parameter TAON = 180; // tAON ps RTT turn-on from ODTLon reference
parameter TWLS = 122; // tWLS ps Setup time for tDQS flop
parameter TWLH = 122; // tWLH ps Hold time of tDQS flop
parameter TWLO = 7500; // tWLO ps Write levelization output delay
parameter TAA_MIN = 13125; // TAA ps Internal READ command to first data
parameter CL_TIME = 13125; // CL ps Minimum CAS Latency
`else `ifdef sg107F // sg107F is equivalent to the JEDEC DDR3-1866 (12-12-12) speed bin
parameter TCK_MIN = 15e3/14; // tCK ps Minimum Clock Cycle Time
parameter TJIT_PER = 60; // tJIT(per) ps Period JItter
parameter TJIT_CC = 120; // tJIT(cc) ps Cycle to Cycle jitter
parameter TERR_2PER = 88; // tERR(2per) ps Accumulated Error (2-cycle)
parameter TERR_3PER = 103; // tERR(3per) ps Accumulated Error (3-cycle)
parameter TERR_4PER = 117; // tERR(4per) ps Accumulated Error (4-cycle)
parameter TERR_5PER = 126; // tERR(5per) ps Accumulated Error (5-cycle)
parameter TERR_6PER = 133; // tERR(6per) ps Accumulated Error (6-cycle)
parameter TERR_7PER = 140; // tERR(7per) ps Accumulated Error (7-cycle)
parameter TERR_8PER = 145; // tERR(8per) ps Accumulated Error (8-cycle)
parameter TERR_9PER = 150; // tERR(9per) ps Accumulated Error (9-cycle)
parameter TERR_10PER = 154; // tERR(10per)ps Accumulated Error (10-cycle)
parameter TERR_11PER = 158; // tERR(11per)ps Accumulated Error (11-cycle)
parameter TERR_12PER = 161; // tERR(12per)ps Accumulated Error (12-cycle)
parameter TDS = 10; // tDS ps DQ and DM input setup time relative to DQS
parameter TDH = 20; // tDH ps DQ and DM input hold time relative to DQS
parameter TDQSQ = 80; // tDQSQ ps DQS-DQ skew, DQS to last DQ valid, per group, per access
parameter TDQSS = 0.27; // tDQSS tCK Rising clock edge to DQS/DQS# latching transition
parameter TDSS = 0.18; // tDSS tCK DQS falling edge to CLK rising (setup time)
parameter TDSH = 0.18; // tDSH tCK DQS falling edge from CLK rising (hold time)
parameter TDQSCK = 200; // tDQSCK ps DQS output access time from CK/CK#
parameter TQSH = 0.40; // tQSH tCK DQS Output High Pulse Width
parameter TQSL = 0.40; // tQSL tCK DQS Output Low Pulse Width
parameter TDIPW = 300; // tDIPW ps DQ and DM input Pulse Width
parameter TIPW = 505; // tIPW ps Control and Address input Pulse Width
parameter TIS = 50; // tIS ps Input Setup Time
parameter TIH = 100; // tIH ps Input Hold Time
parameter TRAS_MIN = 35000; // tRAS ps Minimum Active to Precharge command time
parameter TRC = 46250; // tRC ps Active to Active/Auto Refresh command time
parameter TRCD = 12857; // tRCD ps Active to Read/Write command time
parameter TRP = 12857; // tRP ps Precharge command period
parameter TXP = 6000; // tXP ps Exit power down to a valid command
parameter TCKE = 5000; // tCKE ps CKE minimum high or low pulse width
parameter TAON = 200; // tAON ps RTT turn-on from ODTLon reference
parameter TWLS = 140; // tWLS ps Setup time for tDQS flop
parameter TWLH = 140; // tWLH ps Hold time of tDQS flop
parameter TWLO = 7500; // tWLO ps Write levelization output delay
parameter TAA_MIN = 12857; // TAA ps Internal READ command to first data
parameter CL_TIME = 12857; // CL ps Minimum CAS Latency
`else `ifdef sg107E // sg107E is equivalent to the JEDEC DDR3-1866 (13-13-13) speed bin
parameter TCK_MIN = 15e3/14; // tCK ps Minimum Clock Cycle Time
parameter TJIT_PER = 60; // tJIT(per) ps Period JItter
parameter TJIT_CC = 120; // tJIT(cc) ps Cycle to Cycle jitter
parameter TERR_2PER = 88; // tERR(2per) ps Accumulated Error (2-cycle)
parameter TERR_3PER = 103; // tERR(3per) ps Accumulated Error (3-cycle)
parameter TERR_4PER = 117; // tERR(4per) ps Accumulated Error (4-cycle)
parameter TERR_5PER = 126; // tERR(5per) ps Accumulated Error (5-cycle)
parameter TERR_6PER = 133; // tERR(6per) ps Accumulated Error (6-cycle)
parameter TERR_7PER = 140; // tERR(7per) ps Accumulated Error (7-cycle)
parameter TERR_8PER = 145; // tERR(8per) ps Accumulated Error (8-cycle)
parameter TERR_9PER = 150; // tERR(9per) ps Accumulated Error (9-cycle)
parameter TERR_10PER = 154; // tERR(10per)ps Accumulated Error (10-cycle)
parameter TERR_11PER = 158; // tERR(11per)ps Accumulated Error (11-cycle)
parameter TERR_12PER = 161; // tERR(12per)ps Accumulated Error (12-cycle)
parameter TDS = 10; // tDS ps DQ and DM input setup time relative to DQS
parameter TDH = 20; // tDH ps DQ and DM input hold time relative to DQS
parameter TDQSQ = 80; // tDQSQ ps DQS-DQ skew, DQS to last DQ valid, per group, per access
parameter TDQSS = 0.27; // tDQSS tCK Rising clock edge to DQS/DQS# latching transition
parameter TDSS = 0.18; // tDSS tCK DQS falling edge to CLK rising (setup time)
parameter TDSH = 0.18; // tDSH tCK DQS falling edge from CLK rising (hold time)
parameter TDQSCK = 200; // tDQSCK ps DQS output access time from CK/CK#
parameter TQSH = 0.40; // tQSH tCK DQS Output High Pulse Width
parameter TQSL = 0.40; // tQSL tCK DQS Output Low Pulse Width
parameter TDIPW = 300; // tDIPW ps DQ and DM input Pulse Width
parameter TIPW = 505; // tIPW ps Control and Address input Pulse Width
parameter TIS = 50; // tIS ps Input Setup Time
parameter TIH = 100; // tIH ps Input Hold Time
parameter TRAS_MIN = 35000; // tRAS ps Minimum Active to Precharge command time
parameter TRC = 46250; // tRC ps Active to Active/Auto Refresh command time
parameter TRCD = 13928; // tRCD ps Active to Read/Write command time
parameter TRP = 13928; // tRP ps Precharge command period
parameter TXP = 6000; // tXP ps Exit power down to a valid command
parameter TCKE = 5000; // tCKE ps CKE minimum high or low pulse width
parameter TAON = 200; // tAON ps RTT turn-on from ODTLon reference
parameter TWLS = 140; // tWLS ps Setup time for tDQS flop
parameter TWLH = 140; // tWLH ps Hold time of tDQS flop
parameter TWLO = 7500; // tWLO ps Write levelization output delay
parameter TAA_MIN = 13928; // TAA ps Internal READ command to first data
parameter CL_TIME = 13928; // CL ps Minimum CAS Latency
`else `ifdef sg107 // sg107 is equivalent to the JEDEC DDR3-1866 (14-14-14) speed bin
parameter TCK_MIN = 15e3/14; // tCK ps Minimum Clock Cycle Time
parameter TJIT_PER = 60; // tJIT(per) ps Period JItter
parameter TJIT_CC = 120; // tJIT(cc) ps Cycle to Cycle jitter
parameter TERR_2PER = 88; // tERR(2per) ps Accumulated Error (2-cycle)
parameter TERR_3PER = 103; // tERR(3per) ps Accumulated Error (3-cycle)
parameter TERR_4PER = 117; // tERR(4per) ps Accumulated Error (4-cycle)
parameter TERR_5PER = 126; // tERR(5per) ps Accumulated Error (5-cycle)
parameter TERR_6PER = 133; // tERR(6per) ps Accumulated Error (6-cycle)
parameter TERR_7PER = 140; // tERR(7per) ps Accumulated Error (7-cycle)
parameter TERR_8PER = 145; // tERR(8per) ps Accumulated Error (8-cycle)
parameter TERR_9PER = 150; // tERR(9per) ps Accumulated Error (9-cycle)
parameter TERR_10PER = 154; // tERR(10per)ps Accumulated Error (10-cycle)
parameter TERR_11PER = 158; // tERR(11per)ps Accumulated Error (11-cycle)
parameter TERR_12PER = 161; // tERR(12per)ps Accumulated Error (12-cycle)
parameter TDS = 10; // tDS ps DQ and DM input setup time relative to DQS
parameter TDH = 20; // tDH ps DQ and DM input hold time relative to DQS
parameter TDQSQ = 80; // tDQSQ ps DQS-DQ skew, DQS to last DQ valid, per group, per access
parameter TDQSS = 0.27; // tDQSS tCK Rising clock edge to DQS/DQS# latching transition
parameter TDSS = 0.18; // tDSS tCK DQS falling edge to CLK rising (setup time)
parameter TDSH = 0.18; // tDSH tCK DQS falling edge from CLK rising (hold time)
parameter TDQSCK = 200; // tDQSCK ps DQS output access time from CK/CK#
parameter TQSH = 0.40; // tQSH tCK DQS Output High Pulse Width
parameter TQSL = 0.40; // tQSL tCK DQS Output Low Pulse Width
parameter TDIPW = 300; // tDIPW ps DQ and DM input Pulse Width
parameter TIPW = 505; // tIPW ps Control and Address input Pulse Width
parameter TIS = 50; // tIS ps Input Setup Time
parameter TIH = 100; // tIH ps Input Hold Time
parameter TRAS_MIN = 35000; // tRAS ps Minimum Active to Precharge command time
parameter TRC = 46250; // tRC ps Active to Active/Auto Refresh command time
parameter TRCD = 15000; // tRCD ps Active to Read/Write command time
parameter TRP = 15000; // tRP ps Precharge command period
parameter TXP = 6000; // tXP ps Exit power down to a valid command
parameter TCKE = 5000; // tCKE ps CKE minimum high or low pulse width
parameter TAON = 200; // tAON ps RTT turn-on from ODTLon reference
parameter TWLS = 140; // tWLS ps Setup time for tDQS flop
parameter TWLH = 140; // tWLH ps Hold time of tDQS flop
parameter TWLO = 7500; // tWLO ps Write levelization output delay
parameter TAA_MIN = 15000; // TAA ps Internal READ command to first data
parameter CL_TIME = 15000; // CL ps Minimum CAS Latency
`else `ifdef sg125F // sg125F is equivalent to the JEDEC DDR3-1600 (9-9-9) speed bin
parameter TCK_MIN = 1250; // tCK ps Minimum Clock Cycle Time
parameter TJIT_PER = 70; // tJIT(per) ps Period JItter
parameter TJIT_CC = 140; // tJIT(cc) ps Cycle to Cycle jitter
parameter TERR_2PER = 103; // tERR(2per) ps Accumulated Error (2-cycle)
parameter TERR_3PER = 122; // tERR(3per) ps Accumulated Error (3-cycle)
parameter TERR_4PER = 136; // tERR(4per) ps Accumulated Error (4-cycle)
parameter TERR_5PER = 147; // tERR(5per) ps Accumulated Error (5-cycle)
parameter TERR_6PER = 155; // tERR(6per) ps Accumulated Error (6-cycle)
parameter TERR_7PER = 163; // tERR(7per) ps Accumulated Error (7-cycle)
parameter TERR_8PER = 169; // tERR(8per) ps Accumulated Error (8-cycle)
parameter TERR_9PER = 175; // tERR(9per) ps Accumulated Error (9-cycle)
parameter TERR_10PER = 180; // tERR(10per)ps Accumulated Error (10-cycle)
parameter TERR_11PER = 184; // tERR(11per)ps Accumulated Error (11-cycle)
parameter TERR_12PER = 188; // tERR(12per)ps Accumulated Error (12-cycle)
parameter TDS = 10; // tDS ps DQ and DM input setup time relative to DQS
parameter TDH = 45; // tDH ps DQ and DM input hold time relative to DQS
parameter TDQSQ = 100; // tDQSQ ps DQS-DQ skew, DQS to last DQ valid, per group, per access
parameter TDQSS = 0.27; // tDQSS tCK Rising clock edge to DQS/DQS# latching transition
parameter TDSS = 0.18; // tDSS tCK DQS falling edge to CLK rising (setup time)
parameter TDSH = 0.18; // tDSH tCK DQS falling edge from CLK rising (hold time)
parameter TDQSCK = 225; // tDQSCK ps DQS output access time from CK/CK#
parameter TQSH = 0.40; // tQSH tCK DQS Output High Pulse Width
parameter TQSL = 0.40; // tQSL tCK DQS Output Low Pulse Width
parameter TDIPW = 360; // tDIPW ps DQ and DM input Pulse Width
parameter TIPW = 560; // tIPW ps Control and Address input Pulse Width
parameter TIS = 170; // tIS ps Input Setup Time
parameter TIH = 120; // tIH ps Input Hold Time
parameter TRAS_MIN = 35000; // tRAS ps Minimum Active to Precharge command time
parameter TRC = 46250; // tRC ps Active to Active/Auto Refresh command time
parameter TRCD = 11250; // tRCD ps Active to Read/Write command time
parameter TRP = 11250; // tRP ps Precharge command period
parameter TXP = 6000; // tXP ps Exit power down to a valid command
parameter TCKE = 5000; // tCKE ps CKE minimum high or low pulse width
parameter TAON = 250; // tAON ps RTT turn-on from ODTLon reference
parameter TWLS = 165; // tWLS ps Setup time for tDQS flop
parameter TWLH = 165; // tWLH ps Hold time of tDQS flop
parameter TWLO = 7500; // tWLO ps Write levelization output delay
parameter TAA_MIN = 11250; // TAA ps Internal READ command to first data
parameter CL_TIME = 11250; // CL ps Minimum CAS Latency
`else `ifdef sg125E // sg125E is equivalent to the JEDEC DDR3-1600 (10-10-10) speed bin
parameter TCK_MIN = 1250; // tCK ps Minimum Clock Cycle Time
parameter TJIT_PER = 70; // tJIT(per) ps Period JItter
parameter TJIT_CC = 140; // tJIT(cc) ps Cycle to Cycle jitter
parameter TERR_2PER = 103; // tERR(2per) ps Accumulated Error (2-cycle)
parameter TERR_3PER = 122; // tERR(3per) ps Accumulated Error (3-cycle)
parameter TERR_4PER = 136; // tERR(4per) ps Accumulated Error (4-cycle)
parameter TERR_5PER = 147; // tERR(5per) ps Accumulated Error (5-cycle)
parameter TERR_6PER = 155; // tERR(6per) ps Accumulated Error (6-cycle)
parameter TERR_7PER = 163; // tERR(7per) ps Accumulated Error (7-cycle)
parameter TERR_8PER = 169; // tERR(8per) ps Accumulated Error (8-cycle)
parameter TERR_9PER = 175; // tERR(9per) ps Accumulated Error (9-cycle)
parameter TERR_10PER = 180; // tERR(10per)ps Accumulated Error (10-cycle)
parameter TERR_11PER = 184; // tERR(11per)ps Accumulated Error (11-cycle)
parameter TERR_12PER = 188; // tERR(12per)ps Accumulated Error (12-cycle)
parameter TDS = 10; // tDS ps DQ and DM input setup time relative to DQS
parameter TDH = 45; // tDH ps DQ and DM input hold time relative to DQS
parameter TDQSQ = 100; // tDQSQ ps DQS-DQ skew, DQS to last DQ valid, per group, per access
parameter TDQSS = 0.27; // tDQSS tCK Rising clock edge to DQS/DQS# latching transition
parameter TDSS = 0.18; // tDSS tCK DQS falling edge to CLK rising (setup time)
parameter TDSH = 0.18; // tDSH tCK DQS falling edge from CLK rising (hold time)
parameter TDQSCK = 225; // tDQSCK ps DQS output access time from CK/CK#
parameter TQSH = 0.40; // tQSH tCK DQS Output High Pulse Width
parameter TQSL = 0.40; // tQSL tCK DQS Output Low Pulse Width
parameter TDIPW = 360; // tDIPW ps DQ and DM input Pulse Width
parameter TIPW = 560; // tIPW ps Control and Address input Pulse Width
parameter TIS = 170; // tIS ps Input Setup Time
parameter TIH = 120; // tIH ps Input Hold Time
parameter TRAS_MIN = 35000; // tRAS ps Minimum Active to Precharge command time
parameter TRC = 47500; // tRC ps Active to Active/Auto Refresh command time
parameter TRCD = 12500; // tRCD ps Active to Read/Write command time
parameter TRP = 12500; // tRP ps Precharge command period
parameter TXP = 6000; // tXP ps Exit power down to a valid command
parameter TCKE = 5000; // tCKE ps CKE minimum high or low pulse width
parameter TAON = 250; // tAON ps RTT turn-on from ODTLon reference
parameter TWLS = 165; // tWLS ps Setup time for tDQS flop
parameter TWLH = 165; // tWLH ps Hold time of tDQS flop
parameter TWLO = 7500; // tWLO ps Write levelization output delay
parameter TAA_MIN = 12500; // TAA ps Internal READ command to first data
parameter CL_TIME = 12500; // CL ps Minimum CAS Latency
`else `ifdef sg125 // sg125 is equivalent to the JEDEC DDR3-1600 (11-11-11) speed bin
parameter TCK_MIN = 1250; // tCK ps Minimum Clock Cycle Time
parameter TJIT_PER = 70; // tJIT(per) ps Period JItter
parameter TJIT_CC = 140; // tJIT(cc) ps Cycle to Cycle jitter
parameter TERR_2PER = 103; // tERR(2per) ps Accumulated Error (2-cycle)
parameter TERR_3PER = 122; // tERR(3per) ps Accumulated Error (3-cycle)
parameter TERR_4PER = 136; // tERR(4per) ps Accumulated Error (4-cycle)
parameter TERR_5PER = 147; // tERR(5per) ps Accumulated Error (5-cycle)
parameter TERR_6PER = 155; // tERR(6per) ps Accumulated Error (6-cycle)
parameter TERR_7PER = 163; // tERR(7per) ps Accumulated Error (7-cycle)
parameter TERR_8PER = 169; // tERR(8per) ps Accumulated Error (8-cycle)
parameter TERR_9PER = 175; // tERR(9per) ps Accumulated Error (9-cycle)
parameter TERR_10PER = 180; // tERR(10per)ps Accumulated Error (10-cycle)
parameter TERR_11PER = 184; // tERR(11per)ps Accumulated Error (11-cycle)
parameter TERR_12PER = 188; // tERR(12per)ps Accumulated Error (12-cycle)
parameter TDS = 10; // tDS ps DQ and DM input setup time relative to DQS
parameter TDH = 45; // tDH ps DQ and DM input hold time relative to DQS
parameter TDQSQ = 100; // tDQSQ ps DQS-DQ skew, DQS to last DQ valid, per group, per access
parameter TDQSS = 0.27; // tDQSS tCK Rising clock edge to DQS/DQS# latching transition
parameter TDSS = 0.18; // tDSS tCK DQS falling edge to CLK rising (setup time)
parameter TDSH = 0.18; // tDSH tCK DQS falling edge from CLK rising (hold time)
parameter TDQSCK = 225; // tDQSCK ps DQS output access time from CK/CK#
parameter TQSH = 0.40; // tQSH tCK DQS Output High Pulse Width
parameter TQSL = 0.40; // tQSL tCK DQS Output Low Pulse Width
parameter TDIPW = 360; // tDIPW ps DQ and DM input Pulse Width
parameter TIPW = 560; // tIPW ps Control and Address input Pulse Width
parameter TIS = 170; // tIS ps Input Setup Time
parameter TIH = 120; // tIH ps Input Hold Time
parameter TRAS_MIN = 35000; // tRAS ps Minimum Active to Precharge command time
parameter TRC = 48750; // tRC ps Active to Active/Auto Refresh command time
parameter TRCD = 13125; // tRCD ps Active to Read/Write command time
parameter TRP = 13125; // tRP ps Precharge command period
parameter TXP = 6000; // tXP ps Exit power down to a valid command
parameter TCKE = 5000; // tCKE ps CKE minimum high or low pulse width
parameter TAON = 250; // tAON ps RTT turn-on from ODTLon reference
parameter TWLS = 165; // tWLS ps Setup time for tDQS flop
parameter TWLH = 165; // tWLH ps Hold time of tDQS flop
parameter TWLO = 7500; // tWLO ps Write levelization output delay
parameter TAA_MIN = 13125; // TAA ps Internal READ command to first data
parameter CL_TIME = 13125; // CL ps Minimum CAS Latency
`else `ifdef sg15E // sg15E is equivalent to the JEDEC DDR3-1333H (9-9-9) speed bin
parameter TCK_MIN = 1500; // tCK ps Minimum Clock Cycle Time
parameter TJIT_PER = 80; // tJIT(per) ps Period JItter
parameter TJIT_CC = 160; // tJIT(cc) ps Cycle to Cycle jitter
parameter TERR_2PER = 118; // tERR(2per) ps Accumulated Error (2-cycle)
parameter TERR_3PER = 140; // tERR(3per) ps Accumulated Error (3-cycle)
parameter TERR_4PER = 155; // tERR(4per) ps Accumulated Error (4-cycle)
parameter TERR_5PER = 168; // tERR(5per) ps Accumulated Error (5-cycle)
parameter TERR_6PER = 177; // tERR(6per) ps Accumulated Error (6-cycle)
parameter TERR_7PER = 186; // tERR(7per) ps Accumulated Error (7-cycle)
parameter TERR_8PER = 193; // tERR(8per) ps Accumulated Error (8-cycle)
parameter TERR_9PER = 200; // tERR(9per) ps Accumulated Error (9-cycle)
parameter TERR_10PER = 205; // tERR(10per)ps Accumulated Error (10-cycle)
parameter TERR_11PER = 210; // tERR(11per)ps Accumulated Error (11-cycle)
parameter TERR_12PER = 215; // tERR(12per)ps Accumulated Error (12-cycle)
parameter TDS = 30; // tDS ps DQ and DM input setup time relative to DQS
parameter TDH = 65; // tDH ps DQ and DM input hold time relative to DQS
parameter TDQSQ = 125; // tDQSQ ps DQS-DQ skew, DQS to last DQ valid, per group, per access
parameter TDQSS = 0.25; // tDQSS tCK Rising clock edge to DQS/DQS# latching transition
parameter TDSS = 0.20; // tDSS tCK DQS falling edge to CLK rising (setup time)
parameter TDSH = 0.20; // tDSH tCK DQS falling edge from CLK rising (hold time)
parameter TDQSCK = 255; // tDQSCK ps DQS output access time from CK/CK#
parameter TQSH = 0.40; // tQSH tCK DQS Output High Pulse Width
parameter TQSL = 0.40; // tQSL tCK DQS Output Low Pulse Width
parameter TDIPW = 400; // tDIPW ps DQ and DM input Pulse Width
parameter TIPW = 620; // tIPW ps Control and Address input Pulse Width
parameter TIS = 190; // tIS ps Input Setup Time
parameter TIH = 140; // tIH ps Input Hold Time
parameter TRAS_MIN = 36000; // tRAS ps Minimum Active to Precharge command time
parameter TRC = 49500; // tRC ps Active to Active/Auto Refresh command time
parameter TRCD = 13125; // tRCD ps Active to Read/Write command time
parameter TRP = 13125; // tRP ps Precharge command period
parameter TXP = 6000; // tXP ps Exit power down to a valid command
parameter TCKE = 5625; // tCKE ps CKE minimum high or low pulse width
parameter TAON = 250; // tAON ps RTT turn-on from ODTLon reference
parameter TWLS = 195; // tWLS ps Setup time for tDQS flop
parameter TWLH = 195; // tWLH ps Hold time of tDQS flop
parameter TWLO = 9000; // tWLO ps Write levelization output delay
parameter TAA_MIN = 13125; // TAA ps Internal READ command to first data
parameter CL_TIME = 13125; // CL ps Minimum CAS Latency
`else `ifdef sg15 // sg15 is equivalent to the JEDEC DDR3-1333J (10-10-10) speed bin
parameter TCK_MIN = 1500; // tCK ps Minimum Clock Cycle Time
parameter TJIT_PER = 80; // tJIT(per) ps Period JItter
parameter TJIT_CC = 160; // tJIT(cc) ps Cycle to Cycle jitter
parameter TERR_2PER = 118; // tERR(2per) ps Accumulated Error (2-cycle)
parameter TERR_3PER = 140; // tERR(3per) ps Accumulated Error (3-cycle)
parameter TERR_4PER = 155; // tERR(4per) ps Accumulated Error (4-cycle)
parameter TERR_5PER = 168; // tERR(5per) ps Accumulated Error (5-cycle)
parameter TERR_6PER = 177; // tERR(6per) ps Accumulated Error (6-cycle)
parameter TERR_7PER = 186; // tERR(7per) ps Accumulated Error (7-cycle)
parameter TERR_8PER = 193; // tERR(8per) ps Accumulated Error (8-cycle)
parameter TERR_9PER = 200; // tERR(9per) ps Accumulated Error (9-cycle)
parameter TERR_10PER = 205; // tERR(10per)ps Accumulated Error (10-cycle)
parameter TERR_11PER = 210; // tERR(11per)ps Accumulated Error (11-cycle)
parameter TERR_12PER = 215; // tERR(12per)ps Accumulated Error (12-cycle)
parameter TDS = 30; // tDS ps DQ and DM input setup time relative to DQS
parameter TDH = 65; // tDH ps DQ and DM input hold time relative to DQS
parameter TDQSQ = 125; // tDQSQ ps DQS-DQ skew, DQS to last DQ valid, per group, per access
parameter TDQSS = 0.25; // tDQSS tCK Rising clock edge to DQS/DQS# latching transition
parameter TDSS = 0.20; // tDSS tCK DQS falling edge to CLK rising (setup time)
parameter TDSH = 0.20; // tDSH tCK DQS falling edge from CLK rising (hold time)
parameter TDQSCK = 255; // tDQSCK ps DQS output access time from CK/CK#
parameter TQSH = 0.40; // tQSH tCK DQS Output High Pulse Width
parameter TQSL = 0.40; // tQSL tCK DQS Output Low Pulse Width
parameter TDIPW = 400; // tDIPW ps DQ and DM input Pulse Width
parameter TIPW = 620; // tIPW ps Control and Address input Pulse Width
parameter TIS = 190; // tIS ps Input Setup Time
parameter TIH = 140; // tIH ps Input Hold Time
parameter TRAS_MIN = 36000; // tRAS ps Minimum Active to Precharge command time
parameter TRC = 51000; // tRC ps Active to Active/Auto Refresh command time
parameter TRCD = 15000; // tRCD ps Active to Read/Write command time
parameter TRP = 15000; // tRP ps Precharge command period
parameter TXP = 6000; // tXP ps Exit power down to a valid command
parameter TCKE = 5625; // tCKE ps CKE minimum high or low pulse width
parameter TAON = 250; // tAON ps RTT turn-on from ODTLon reference
parameter TWLS = 195; // tWLS ps Setup time for tDQS flop
parameter TWLH = 195; // tWLH ps Hold time of tDQS flop
parameter TWLO = 9000; // tWLO ps Write levelization output delay
parameter TAA_MIN = 15000; // TAA ps Internal READ command to first data
parameter CL_TIME = 15000; // CL ps Minimum CAS Latency
`else `ifdef sg187E // sg187E is equivalent to the JEDEC DDR3-1066F (7-7-7) speed bin
parameter TCK_MIN = 1875; // tCK ps Minimum Clock Cycle Time
parameter TJIT_PER = 90; // tJIT(per) ps Period JItter
parameter TJIT_CC = 180; // tJIT(cc) ps Cycle to Cycle jitter
parameter TERR_2PER = 132; // tERR(2per) ps Accumulated Error (2-cycle)
parameter TERR_3PER = 157; // tERR(3per) ps Accumulated Error (3-cycle)
parameter TERR_4PER = 175; // tERR(4per) ps Accumulated Error (4-cycle)
parameter TERR_5PER = 188; // tERR(5per) ps Accumulated Error (5-cycle)
parameter TERR_6PER = 200; // tERR(6per) ps Accumulated Error (6-cycle)
parameter TERR_7PER = 209; // tERR(7per) ps Accumulated Error (7-cycle)
parameter TERR_8PER = 217; // tERR(8per) ps Accumulated Error (8-cycle)
parameter TERR_9PER = 224; // tERR(9per) ps Accumulated Error (9-cycle)
parameter TERR_10PER = 231; // tERR(10per)ps Accumulated Error (10-cycle)
parameter TERR_11PER = 237; // tERR(11per)ps Accumulated Error (11-cycle)
parameter TERR_12PER = 242; // tERR(12per)ps Accumulated Error (12-cycle)
parameter TDS = 75; // tDS ps DQ and DM input setup time relative to DQS
parameter TDH = 100; // tDH ps DQ and DM input hold time relative to DQS
parameter TDQSQ = 150; // tDQSQ ps DQS-DQ skew, DQS to last DQ valid, per group, per access
parameter TDQSS = 0.25; // tDQSS tCK Rising clock edge to DQS/DQS# latching transition
parameter TDSS = 0.20; // tDSS tCK DQS falling edge to CLK rising (setup time)
parameter TDSH = 0.20; // tDSH tCK DQS falling edge from CLK rising (hold time)
parameter TDQSCK = 300; // tDQSCK ps DQS output access time from CK/CK#
parameter TQSH = 0.38; // tQSH tCK DQS Output High Pulse Width
parameter TQSL = 0.38; // tQSL tCK DQS Output Low Pulse Width
parameter TDIPW = 490; // tDIPW ps DQ and DM input Pulse Width
parameter TIPW = 780; // tIPW ps Control and Address input Pulse Width
parameter TIS = 275; // tIS ps Input Setup Time
parameter TIH = 200; // tIH ps Input Hold Time
parameter TRAS_MIN = 37500; // tRAS ps Minimum Active to Precharge command time
parameter TRC = 50625; // tRC ps Active to Active/Auto Refresh command time
parameter TRCD = 13125; // tRCD ps Active to Read/Write command time
parameter TRP = 13125; // tRP ps Precharge command period
parameter TXP = 7500; // tXP ps Exit power down to a valid command
parameter TCKE = 5625; // tCKE ps CKE minimum high or low pulse width
parameter TAON = 300; // tAON ps RTT turn-on from ODTLon reference
parameter TWLS = 245; // tWLS ps Setup time for tDQS flop
parameter TWLH = 245; // tWLH ps Hold time of tDQS flop
parameter TWLO = 9000; // tWLO ps Write levelization output delay
parameter TAA_MIN = 13125; // TAA ps Internal READ command to first data
parameter CL_TIME = 13125; // CL ps Minimum CAS Latency
`else `ifdef sg187 // sg187 is equivalent to the JEDEC DDR3-1066G (8-8-8) speed bin
parameter TCK_MIN = 1875; // tCK ps Minimum Clock Cycle Time
parameter TJIT_PER = 90; // tJIT(per) ps Period JItter
parameter TJIT_CC = 180; // tJIT(cc) ps Cycle to Cycle jitter
parameter TERR_2PER = 132; // tERR(2per) ps Accumulated Error (2-cycle)
parameter TERR_3PER = 157; // tERR(3per) ps Accumulated Error (3-cycle)
parameter TERR_4PER = 175; // tERR(4per) ps Accumulated Error (4-cycle)
parameter TERR_5PER = 188; // tERR(5per) ps Accumulated Error (5-cycle)
parameter TERR_6PER = 200; // tERR(6per) ps Accumulated Error (6-cycle)
parameter TERR_7PER = 209; // tERR(7per) ps Accumulated Error (7-cycle)
parameter TERR_8PER = 217; // tERR(8per) ps Accumulated Error (8-cycle)
parameter TERR_9PER = 224; // tERR(9per) ps Accumulated Error (9-cycle)
parameter TERR_10PER = 231; // tERR(10per)ps Accumulated Error (10-cycle)
parameter TERR_11PER = 237; // tERR(11per)ps Accumulated Error (11-cycle)
parameter TERR_12PER = 242; // tERR(12per)ps Accumulated Error (12-cycle)
parameter TDS = 75; // tDS ps DQ and DM input setup time relative to DQS
parameter TDH = 100; // tDH ps DQ and DM input hold time relative to DQS
parameter TDQSQ = 150; // tDQSQ ps DQS-DQ skew, DQS to last DQ valid, per group, per access
parameter TDQSS = 0.25; // tDQSS tCK Rising clock edge to DQS/DQS# latching transition
parameter TDSS = 0.20; // tDSS tCK DQS falling edge to CLK rising (setup time)
parameter TDSH = 0.20; // tDSH tCK DQS falling edge from CLK rising (hold time)
parameter TDQSCK = 300; // tDQSCK ps DQS output access time from CK/CK#
parameter TQSH = 0.38; // tQSH tCK DQS Output High Pulse Width
parameter TQSL = 0.38; // tQSL tCK DQS Output Low Pulse Width
parameter TDIPW = 490; // tDIPW ps DQ and DM input Pulse Width
parameter TIPW = 780; // tIPW ps Control and Address input Pulse Width
parameter TIS = 275; // tIS ps Input Setup Time
parameter TIH = 200; // tIH ps Input Hold Time
parameter TRAS_MIN = 37500; // tRAS ps Minimum Active to Precharge command time
parameter TRC = 52500; // tRC ps Active to Active/Auto Refresh command time
parameter TRCD = 15000; // tRCD ps Active to Read/Write command time
parameter TRP = 15000; // tRP ps Precharge command period
parameter TXP = 7500; // tXP ps Exit power down to a valid command
parameter TCKE = 5625; // tCKE ps CKE minimum high or low pulse width
parameter TAON = 300; // tAON ps RTT turn-on from ODTLon reference
parameter TWLS = 245; // tWLS ps Setup time for tDQS flop
parameter TWLH = 245; // tWLH ps Hold time of tDQS flop
parameter TWLO = 9000; // tWLO ps Write levelization output delay
parameter TAA_MIN = 15000; // TAA ps Internal READ command to first data
parameter CL_TIME = 15000; // CL ps Minimum CAS Latency
`else `ifdef sg25E // sg25E is equivalent to the JEDEC DDR3-800D (5-5-5) speed bin
parameter TCK_MIN = 2500; // tCK ps Minimum Clock Cycle Time
parameter TJIT_PER = 100; // tJIT(per) ps Period JItter
parameter TJIT_CC = 200; // tJIT(cc) ps Cycle to Cycle jitter
parameter TERR_2PER = 147; // tERR(2per) ps Accumulated Error (2-cycle)
parameter TERR_3PER = 175; // tERR(3per) ps Accumulated Error (3-cycle)
parameter TERR_4PER = 194; // tERR(4per) ps Accumulated Error (4-cycle)
parameter TERR_5PER = 209; // tERR(5per) ps Accumulated Error (5-cycle)
parameter TERR_6PER = 222; // tERR(6per) ps Accumulated Error (6-cycle)
parameter TERR_7PER = 232; // tERR(7per) ps Accumulated Error (7-cycle)
parameter TERR_8PER = 241; // tERR(8per) ps Accumulated Error (8-cycle)
parameter TERR_9PER = 249; // tERR(9per) ps Accumulated Error (9-cycle)
parameter TERR_10PER = 257; // tERR(10per)ps Accumulated Error (10-cycle)
parameter TERR_11PER = 263; // tERR(11per)ps Accumulated Error (11-cycle)
parameter TERR_12PER = 269; // tERR(12per)ps Accumulated Error (12-cycle)
parameter TDS = 125; // tDS ps DQ and DM input setup time relative to DQS
parameter TDH = 150; // tDH ps DQ and DM input hold time relative to DQS
parameter TDQSQ = 200; // tDQSQ ps DQS-DQ skew, DQS to last DQ valid, per group, per access
parameter TDQSS = 0.25; // tDQSS tCK Rising clock edge to DQS/DQS# latching transition
parameter TDSS = 0.20; // tDSS tCK DQS falling edge to CLK rising (setup time)
parameter TDSH = 0.20; // tDSH tCK DQS falling edge from CLK rising (hold time)
parameter TDQSCK = 400; // tDQSCK ps DQS output access time from CK/CK#
parameter TQSH = 0.38; // tQSH tCK DQS Output High Pulse Width
parameter TQSL = 0.38; // tQSL tCK DQS Output Low Pulse Width
parameter TDIPW = 600; // tDIPW ps DQ and DM input Pulse Width
parameter TIPW = 900; // tIPW ps Control and Address input Pulse Width
parameter TIS = 350; // tIS ps Input Setup Time
parameter TIH = 275; // tIH ps Input Hold Time
parameter TRAS_MIN = 37500; // tRAS ps Minimum Active to Precharge command time
parameter TRC = 50000; // tRC ps Active to Active/Auto Refresh command time
parameter TRCD = 12500; // tRCD ps Active to Read/Write command time
parameter TRP = 12500; // tRP ps Precharge command period
parameter TXP = 7500; // tXP ps Exit power down to a valid command
parameter TCKE = 7500; // tCKE ps CKE minimum high or low pulse width
parameter TAON = 400; // tAON ps RTT turn-on from ODTLon reference
parameter TWLS = 325; // tWLS ps Setup time for tDQS flop
parameter TWLH = 325; // tWLH ps Hold time of tDQS flop
parameter TWLO = 9000; // tWLO ps Write levelization output delay
parameter TAA_MIN = 12500; // TAA ps Internal READ command to first data
parameter CL_TIME = 12500; // CL ps Minimum CAS Latency
`else
`define sg25 // sg25 is equivalent to the JEDEC DDR3-800E (6-6-6) speed bin
parameter TCK_MIN = 2500; // tCK ps Minimum Clock Cycle Time
parameter TJIT_PER = 100; // tJIT(per) ps Period JItter
parameter TJIT_CC = 200; // tJIT(cc) ps Cycle to Cycle jitter
parameter TERR_2PER = 147; // tERR(2per) ps Accumulated Error (2-cycle)
parameter TERR_3PER = 175; // tERR(3per) ps Accumulated Error (3-cycle)
parameter TERR_4PER = 194; // tERR(4per) ps Accumulated Error (4-cycle)
parameter TERR_5PER = 209; // tERR(5per) ps Accumulated Error (5-cycle)
parameter TERR_6PER = 222; // tERR(6per) ps Accumulated Error (6-cycle)
parameter TERR_7PER = 232; // tERR(7per) ps Accumulated Error (7-cycle)
parameter TERR_8PER = 241; // tERR(8per) ps Accumulated Error (8-cycle)
parameter TERR_9PER = 249; // tERR(9per) ps Accumulated Error (9-cycle)
parameter TERR_10PER = 257; // tERR(10per)ps Accumulated Error (10-cycle)
parameter TERR_11PER = 263; // tERR(11per)ps Accumulated Error (11-cycle)
parameter TERR_12PER = 269; // tERR(12per)ps Accumulated Error (12-cycle)
parameter TDS = 125; // tDS ps DQ and DM input setup time relative to DQS
parameter TDH = 150; // tDH ps DQ and DM input hold time relative to DQS
parameter TDQSQ = 200; // tDQSQ ps DQS-DQ skew, DQS to last DQ valid, per group, per access
parameter TDQSS = 0.25; // tDQSS tCK Rising clock edge to DQS/DQS# latching transition
parameter TDSS = 0.20; // tDSS tCK DQS falling edge to CLK rising (setup time)
parameter TDSH = 0.20; // tDSH tCK DQS falling edge from CLK rising (hold time)
parameter TDQSCK = 400; // tDQSCK ps DQS output access time from CK/CK#
parameter TQSH = 0.38; // tQSH tCK DQS Output High Pulse Width
parameter TQSL = 0.38; // tQSL tCK DQS Output Low Pulse Width
parameter TDIPW = 600; // tDIPW ps DQ and DM input Pulse Width
parameter TIPW = 900; // tIPW ps Control and Address input Pulse Width
parameter TIS = 350; // tIS ps Input Setup Time
parameter TIH = 275; // tIH ps Input Hold Time
parameter TRAS_MIN = 37500; // tRAS ps Minimum Active to Precharge command time
parameter TRC = 52500; // tRC ps Active to Active/Auto Refresh command time
parameter TRCD = 15000; // tRCD ps Active to Read/Write command time
parameter TRP = 15000; // tRP ps Precharge command period
parameter TXP = 7500; // tXP ps Exit power down to a valid command
parameter TCKE = 7500; // tCKE ps CKE minimum high or low pulse width
parameter TAON = 400; // tAON ps RTT turn-on from ODTLon reference
parameter TWLS = 325; // tWLS ps Setup time for tDQS flop
parameter TWLH = 325; // tWLH ps Hold time of tDQS flop
parameter TWLO = 9000; // tWLO ps Write levelization output delay
parameter TAA_MIN = 15000; // TAA ps Internal READ command to first data
parameter CL_TIME = 15000; // CL ps Minimum CAS Latency
`endif `endif `endif `endif `endif `endif `endif `endif `endif `endif `endif `endif `endif
`ifdef x16
`ifdef sg094E
parameter TRRD = 7500; // tRRD ps (2KB page size) Active bank a to Active bank b command time
parameter TFAW = 30000; // tFAW ps (2KB page size) Four Bank Activate window
`else `ifdef sg094
parameter TRRD = 7500; // tRRD ps (2KB page size) Active bank a to Active bank b command time
parameter TFAW = 30000; // tFAW ps (2KB page size) Four Bank Activate window
`else `ifdef sg107F
parameter TRRD = 7500; // tRRD ps (2KB page size) Active bank a to Active bank b command time
parameter TFAW = 35000; // tFAW ps (2KB page size) Four Bank Activate window
`else `ifdef sg107E
parameter TRRD = 7500; // tRRD ps (2KB page size) Active bank a to Active bank b command time
parameter TFAW = 35000; // tFAW ps (2KB page size) Four Bank Activate window
`else `ifdef sg107
parameter TRRD = 7500; // tRRD ps (2KB page size) Active bank a to Active bank b command time
parameter TFAW = 35000; // tFAW ps (2KB page size) Four Bank Activate window
`else `ifdef sg125F
parameter TRRD = 7500; // tRRD ps (2KB page size) Active bank a to Active bank b command time
parameter TFAW = 40000; // tFAW ps (2KB page size) Four Bank Activate window
`else `ifdef sg125E
parameter TRRD = 7500; // tRRD ps (2KB page size) Active bank a to Active bank b command time
parameter TFAW = 40000; // tFAW ps (2KB page size) Four Bank Activate window
`else `ifdef sg125
parameter TRRD = 7500; // tRRD ps (2KB page size) Active bank a to Active bank b command time
parameter TFAW = 40000; // tFAW ps (2KB page size) Four Bank Activate window
`else `ifdef sg15E
parameter TRRD = 7500; // tRRD ps (2KB page size) Active bank a to Active bank b command time
parameter TFAW = 45000; // tFAW ps (2KB page size) Four Bank Activate window
`else `ifdef sg15
parameter TRRD = 7500; // tRRD ps (2KB page size) Active bank a to Active bank b command time
parameter TFAW = 45000; // tFAW ps (2KB page size) Four Bank Activate window
`else // sg187E, sg187, sg25, sg25E
parameter TRRD = 10000; // tRRD ps (2KB page size) Active bank a to Active bank b command time
parameter TFAW = 50000; // tFAW ps (2KB page size) Four Bank Activate window
`endif `endif `endif `endif `endif `endif `endif `endif `endif `endif
`else // x4, x8
`ifdef sg094E
parameter TRRD = 6000; // tRRD ps (1KB page size) Active bank a to Active bank b command time
parameter TFAW = 25000; // tFAW ps (1KB page size) Four Bank Activate window
`else `ifdef sg094
parameter TRRD = 6000; // tRRD ps (1KB page size) Active bank a to Active bank b command time
parameter TFAW = 25000; // tFAW ps (1KB page size) Four Bank Activate window
`else `ifdef sg107F
parameter TRRD = 6000; // tRRD ps (1KB page size) Active bank a to Active bank b command time
parameter TFAW = 25000; // tFAW ps (1KB page size) Four Bank Activate window
`else `ifdef sg107E
parameter TRRD = 6000; // tRRD ps (1KB page size) Active bank a to Active bank b command time
parameter TFAW = 25000; // tFAW ps (1KB page size) Four Bank Activate window
`else `ifdef sg107
parameter TRRD = 6000; // tRRD ps (1KB page size) Active bank a to Active bank b command time
parameter TFAW = 25000; // tFAW ps (1KB page size) Four Bank Activate window
`else `ifdef sg125F
parameter TRRD = 6000; // tRRD ps (1KB page size) Active bank a to Active bank b command time
parameter TFAW = 30000; // tFAW ps (1KB page size) Four Bank Activate window
`else `ifdef sg125E
parameter TRRD = 6000; // tRRD ps (1KB page size) Active bank a to Active bank b command time
parameter TFAW = 30000; // tFAW ps (1KB page size) Four Bank Activate window
`else `ifdef sg125
parameter TRRD = 6000; // tRRD ps (1KB page size) Active bank a to Active bank b command time
parameter TFAW = 30000; // tFAW ps (1KB page size) Four Bank Activate window
`else `ifdef sg15E
parameter TRRD = 6000; // tRRD ps (1KB page size) Active bank a to Active bank b command time
parameter TFAW = 30000; // tFAW ps (1KB page size) Four Bank Activate window
`else `ifdef sg15
parameter TRRD = 6000; // tRRD ps (1KB page size) Active bank a to Active bank b command time
parameter TFAW = 30000; // tFAW ps (1KB page size) Four Bank Activate window
`else `ifdef sg187E
parameter TRRD = 7500; // tRRD ps (1KB page size) Active bank a to Active bank b command time
parameter TFAW = 37500; // tFAW ps (1KB page size) Four Bank Activate window
`else `ifdef sg187
parameter TRRD = 7500; // tRRD ps (1KB page size) Active bank a to Active bank b command time
parameter TFAW = 37500; // tFAW ps (1KB page size) Four Bank Activate window
`else // sg25, sg25E
parameter TRRD = 10000; // tRRD ps (1KB page size) Active bank a to Active bank b command time
parameter TFAW = 40000; // tFAW ps (1KB page size) Four Bank Activate window
`endif `endif `endif `endif `endif `endif `endif `endif `endif `endif `endif `endif
`endif
// Timing Parameters
// Mode Register
parameter CL_MIN = 5; // CL tCK Minimum CAS Latency
parameter CL_MAX = 14; // CL tCK Maximum CAS Latency
parameter AL_MIN = 0; // AL tCK Minimum Additive Latency
parameter AL_MAX = 2; // AL tCK Maximum Additive Latency
parameter WR_MIN = 5; // WR tCK Minimum Write Recovery
parameter WR_MAX = 16; // WR tCK Maximum Write Recovery
parameter BL_MIN = 4; // BL tCK Minimum Burst Length
parameter BL_MAX = 8; // BL tCK Minimum Burst Length
parameter CWL_MIN = 5; // CWL tCK Minimum CAS Write Latency
parameter CWL_MAX = 10; // CWL tCK Maximum CAS Write Latency
// Clock
parameter TCK_MAX = 3300; // tCK ps Maximum Clock Cycle Time
parameter TCH_AVG_MIN = 0.47; // tCH tCK Minimum Clock High-Level Pulse Width
parameter TCL_AVG_MIN = 0.47; // tCL tCK Minimum Clock Low-Level Pulse Width
parameter TCH_AVG_MAX = 0.53; // tCH tCK Maximum Clock High-Level Pulse Width
parameter TCL_AVG_MAX = 0.53; // tCL tCK Maximum Clock Low-Level Pulse Width
parameter TCH_ABS_MIN = 0.43; // tCH tCK Minimum Clock High-Level Pulse Width
parameter TCL_ABS_MIN = 0.43; // tCL tCK Maximum Clock Low-Level Pulse Width
parameter TCKE_TCK = 3; // tCKE tCK CKE minimum high or low pulse width
parameter TAA_MAX = 20000; // TAA ps Internal READ command to first data
// Data OUT
parameter TQH = 0.38; // tQH ps DQ output hold time from DQS, DQS#
// Data Strobe OUT
parameter TRPRE = 0.90; // tRPRE tCK DQS Read Preamble
parameter TRPST = 0.30; // tRPST tCK DQS Read Postamble
// Data Strobe IN
parameter TDQSH = 0.45; // tDQSH tCK DQS input High Pulse Width
parameter TDQSL = 0.45; // tDQSL tCK DQS input Low Pulse Width
parameter TWPRE = 0.90; // tWPRE tCK DQS Write Preamble
parameter TWPST = 0.30; // tWPST tCK DQS Write Postamble
// Command and Address
parameter TZQCS = 64; // tZQCS tCK ZQ Cal (Short) time
parameter TZQINIT = 512; // tZQinit tCK ZQ Cal (Long) time
parameter TZQOPER = 256; // tZQoper tCK ZQ Cal (Long) time
parameter TCCD = 4; // tCCD tCK Cas to Cas command delay
parameter TCCD_DG = 2; // tCCD_DG tCK Cas to Cas command delay to different group
parameter TRAS_MAX = 60e9; // tRAS ps Maximum Active to Precharge command time
parameter TWR = 15000; // tWR ps Write recovery time
parameter TMRD = 4; // tMRD tCK Load Mode Register command cycle time
parameter TMOD = 15000; // tMOD ps LOAD MODE to non-LOAD MODE command cycle time
parameter TMOD_TCK = 12; // tMOD tCK LOAD MODE to non-LOAD MODE command cycle time
parameter TRRD_TCK = 4; // tRRD tCK Active bank a to Active bank b command time
parameter TRRD_DG = 3000; // tRRD_DG ps Active bank a to Active bank b command time to different group
parameter TRRD_DG_TCK = 2; // tRRD_DG tCK Active bank a to Active bank b command time to different group
parameter TRTP = 7500; // tRTP ps Read to Precharge command delay
parameter TRTP_TCK = 4; // tRTP tCK Read to Precharge command delay
parameter TWTR = 7500; // tWTR ps Write to Read command delay
parameter TWTR_DG = 3750; // tWTR_DG ps Write to Read command delay to different group
parameter TWTR_TCK = 4; // tWTR tCK Write to Read command delay
parameter TWTR_DG_TCK = 2; // tWTR_DG tCK Write to Read command delay to different group
parameter TDLLK = 512; // tDLLK tCK DLL locking time
// Refresh - 1Gb
parameter TRFC_MIN = 110000; // tRFC ps Refresh to Refresh Command interval minimum value
parameter TRFC_MAX =70312500; // tRFC ps Refresh to Refresh Command Interval maximum value
// Power Down
parameter TXP_TCK = 3; // tXP tCK Exit power down to a valid command
parameter TXPDLL = 24000; // tXPDLL ps Exit precharge power down to READ or WRITE command (DLL-off mode)
parameter TXPDLL_TCK = 10; // tXPDLL tCK Exit precharge power down to READ or WRITE command (DLL-off mode)
parameter TACTPDEN = 1; // tACTPDEN tCK Timing of last ACT command to power down entry
parameter TPRPDEN = 1; // tPREPDEN tCK Timing of last PRE command to power down entry
parameter TREFPDEN = 1; // tARPDEN tCK Timing of last REFRESH command to power down entry
parameter TCPDED = 1; // tCPDED tCK Command pass disable/enable delay
parameter TPD_MAX =TRFC_MAX; // tPD ps Power-down entry-to-exit timing
parameter TXPR = 120000; // tXPR ps Exit Reset from CKE assertion to a valid command
parameter TXPR_TCK = 5; // tXPR tCK Exit Reset from CKE assertion to a valid command
// Self Refresh
parameter TXS = 120000; // tXS ps Exit self refesh to a non-read or write command
parameter TXS_TCK = 5; // tXS tCK Exit self refesh to a non-read or write command
parameter TXSDLL = TDLLK; // tXSRD tCK Exit self refresh to a read or write command
parameter TISXR = TIS; // tISXR ps CKE setup time during self refresh exit.
parameter TCKSRE = 10000; // tCKSRE ps Valid Clock requirement after self refresh entry (SRE)
parameter TCKSRE_TCK = 5; // tCKSRE tCK Valid Clock requirement after self refresh entry (SRE)
parameter TCKSRX = 10000; // tCKSRX ps Valid Clock requirement prior to self refresh exit (SRX)
parameter TCKSRX_TCK = 5; // tCKSRX tCK Valid Clock requirement prior to self refresh exit (SRX)
parameter TCKESR_TCK = 4; // tCKESR tCK Minimum CKE low width for Self Refresh entry to exit timing
// ODT
parameter TAOF = 0.7; // tAOF tCK RTT turn-off from ODTLoff reference
parameter TAONPD = 8500; // tAONPD ps Asynchronous RTT turn-on delay (Power-Down with DLL frozen)
parameter TAOFPD = 8500; // tAONPD ps Asynchronous RTT turn-off delay (Power-Down with DLL frozen)
parameter ODTH4 = 4; // ODTH4 tCK ODT minimum HIGH time after ODT assertion or write (BL4)
parameter ODTH8 = 6; // ODTH8 tCK ODT minimum HIGH time after write (BL8)
parameter TADC = 0.7; // tADC tCK RTT dynamic change skew
// Write Levelization
parameter TWLMRD = 40; // tWLMRD tCK First DQS pulse rising edge after tDQSS margining mode is programmed
parameter TWLDQSEN = 25; // tWLDQSEN tCK DQS/DQS delay after tDQSS margining mode is programmed
parameter TWLOE = 2000; // tWLOE ps Write levelization output error
// Size Parameters based on Part Width
`ifdef x4
parameter DM_BITS = 1; // Set this parameter to control how many Data Mask bits are used
parameter ADDR_BITS = 14; // MAX Address Bits
parameter ROW_BITS = 14; // Set this parameter to control how many Address bits are used
parameter COL_BITS = 11; // Set this parameter to control how many Column bits are used
parameter DQ_BITS = 4; // Set this parameter to control how many Data bits are used **Same as part bit width**
parameter DQS_BITS = 1; // Set this parameter to control how many Dqs bits are used
`else `ifdef x8
parameter DM_BITS = 1; // Set this parameter to control how many Data Mask bits are used
parameter ADDR_BITS = 14; // MAX Address Bits
parameter ROW_BITS = 14; // Set this parameter to control how many Address bits are used
parameter COL_BITS = 10; // Set this parameter to control how many Column bits are used
parameter DQ_BITS = 8; // Set this parameter to control how many Data bits are used **Same as part bit width**
parameter DQS_BITS = 1; // Set this parameter to control how many Dqs bits are used
`else
`define x16
parameter DM_BITS = 2; // Set this parameter to control how many Data Mask bits are used
parameter ADDR_BITS = 13; // MAX Address Bits
parameter ROW_BITS = 13; // Set this parameter to control how many Address bits are used
parameter COL_BITS = 10; // Set this parameter to control how many Column bits are used
parameter DQ_BITS = 16; // Set this parameter to control how many Data bits are used **Same as part bit width**
parameter DQS_BITS = 2; // Set this parameter to control how many Dqs bits are used
`endif `endif
// Size Parameters
parameter BA_BITS = 3; // Set this parmaeter to control how many Bank Address bits are used
parameter MEM_BITS = 15; // Set this parameter to control how many write data bursts can be stored in memory. The default is 2^10=1024.
parameter AP = 10; // the address bit that controls auto-precharge and precharge-all
parameter BC = 12; // the address bit that controls burst chop
parameter BL_BITS = 3; // the number of bits required to count to BL_MAX
parameter BO_BITS = 2; // the number of Burst Order Bits
`ifdef QUAD_RANK
`define DUAL_RANK // also define DUAL_RANK
parameter CS_BITS = 4; // Number of Chip Select Bits
parameter RANKS = 4; // Number of Chip Selects
`else `ifdef DUAL_RANK
parameter CS_BITS = 2; // Number of Chip Select Bits
parameter RANKS = 2; // Number of Chip Selects
`else
parameter CS_BITS = 2; // Number of Chip Select Bits
parameter RANKS = 1; // Number of Chip Selects
`endif `endif
// Simulation parameters
parameter RZQ = 240; // termination resistance
parameter PRE_DEF_PAT = 8'hAA; // value returned during mpr pre-defined pattern readout
parameter STOP_ON_ERROR = 1; // If set to 1, the model will halt on command sequence/major errors
parameter DEBUG = 0; // Turn on Debug messages
parameter BUS_DELAY = 0; // delay in nanoseconds
parameter RANDOM_OUT_DELAY = 0; // If set to 1, the model will put a random amount of delay on DQ/DQS during reads
parameter RANDOM_SEED = 711689044; //seed value for random generator.
parameter RDQSEN_PRE = 2; // DQS driving time prior to first read strobe
parameter RDQSEN_PST = 1; // DQS driving time after last read strobe
parameter RDQS_PRE = 2; // DQS low time prior to first read strobe
parameter RDQS_PST = 1; // DQS low time after last read strobe
parameter RDQEN_PRE = 0; // DQ/DM driving time prior to first read data
parameter RDQEN_PST = 0; // DQ/DM driving time after last read data
parameter WDQS_PRE = 2; // DQS half clock periods prior to first write strobe
parameter WDQS_PST = 1; // DQS half clock periods after last write strobe
// check for legal cas latency based on the cas write latency
function valid_cl;
input [3:0] cl;
input [3:0] cwl;
case ({cwl, cl})
`ifdef sg094E
{4'd5, 4'd5 },
{4'd5, 4'd6 },
{4'd6, 4'd7 },
{4'd6, 4'd8 },
{4'd7, 4'd9 },
{4'd7, 4'd10},
{4'd8, 4'd10},
{4'd8, 4'd11},
{4'd8, 4'd12},
{4'd9, 4'd12},
{4'd9, 4'd13},
{4'd9, 4'd14},
{4'd10, 4'd13},
{4'd10, 4'd14}: valid_cl = 1;
`else `ifdef sg094
{4'd5, 4'd6 },
{4'd6, 4'd7 },
{4'd6, 4'd8 },
{4'd7, 4'd10},
{4'd8, 4'd11},
{4'd8, 4'd12},
{4'd9, 4'd13},
{4'd9, 4'd14},
{4'd10, 4'd14}: valid_cl = 1;
`else `ifdef sg107F
{4'd5, 4'd6 },
{4'd6, 4'd7 },
{4'd6, 4'd8 },
{4'd7, 4'd9 },
{4'd7, 4'd10},
{4'd8, 4'd11},
{4'd8, 4'd12},
{4'd9, 4'd12},
{4'd9, 4'd13},
{4'd9, 4'd14}: valid_cl = 1;
`else `ifdef sg107E
{4'd5, 4'd6 },
{4'd6, 4'd8 },
{4'd7, 4'd10},
{4'd8, 4'd12},
{4'd9, 4'd13},
{4'd9, 4'd14}: valid_cl = 1;
`else `ifdef sg107
{4'd5, 4'd6 },
{4'd6, 4'd8 },
{4'd7, 4'd10},
{4'd8, 4'd12},
{4'd9, 4'd14}: valid_cl = 1;
`else `ifdef sg125F
{4'd5, 4'd5 },
{4'd5, 4'd6 },
{4'd6, 4'd7 },
{4'd6, 4'd8 },
{4'd7, 4'd8 },
{4'd7, 4'd9 },
{4'd7, 4'd10},
{4'd8, 4'd9 },
{4'd8, 4'd10},
{4'd8, 4'd11}: valid_cl = 1;
`else `ifdef sg125E
{4'd5, 4'd5 },
{4'd5, 4'd6 },
{4'd6, 4'd7 },
{4'd6, 4'd8 },
{4'd7, 4'd9 },
{4'd7, 4'd10},
{4'd8, 4'd10},
{4'd8, 4'd11}: valid_cl = 1;
`else `ifdef sg125
{4'd5, 4'd6 },
{4'd6, 4'd7 },
{4'd6, 4'd8 },
{4'd7, 4'd9 },
{4'd7, 4'd10},
{4'd8, 4'd11}: valid_cl = 1;
`else `ifdef sg15E
{4'd5, 4'd6 },
{4'd6, 4'd7 },
{4'd6, 4'd8 },
{4'd7, 4'd9 },
{4'd7, 4'd10}: valid_cl = 1;
`else `ifdef sg15
{4'd5, 4'd6 },
{4'd6, 4'd8 },
{4'd7, 4'd10}: valid_cl = 1;
`else `ifdef sg187E
{4'd5, 4'd6 },
{4'd6, 4'd7 },
{4'd6, 4'd8 }: valid_cl = 1;
`else `ifdef sg187
{4'd5, 4'd6 },
{4'd6, 4'd8 }: valid_cl = 1;
`else `ifdef sg25E
{4'd5, 4'd5 },
{4'd5, 4'd6 }: valid_cl = 1;
`else `ifdef sg25
{4'd5, 4'd6 }: valid_cl = 1;
`endif `endif `endif `endif `endif `endif `endif `endif `endif `endif `endif `endif `endif `endif
default : valid_cl = 0;
endcase
endfunction
// find the minimum valid cas write latency
function [3:0] min_cwl;
input period;
real period;
min_cwl = (period >= 2500.0) ? 5:
(period >= 1875.0) ? 6:
(period >= 1500.0) ? 7:
(period >= 1250.0) ? 8:
(period >= 15e3/14) ? 9:
10; // (period >= 937.5)
endfunction
// find the minimum valid cas latency
function [3:0] min_cl;
input period;
real period;
reg [3:0] cwl;
reg [3:0] cl;
begin
cwl = min_cwl(period);
for (cl=CL_MAX; cl>=CL_MIN; cl=cl-1) begin
if (valid_cl(cl, cwl)) begin
min_cl = cl;
end
end
end
endfunction
`elsif x2Gb // 2Gb parts
// SYMBOL UNITS DESCRIPTION
// ------ ----- -----------
`ifdef sg15E // sg15E is equivelant to the JEDEC DDR3-1333H (9-9-9) speed bin
parameter TCK_MIN = 1500; // tCK ps Minimum Clock Cycle Time
parameter TJIT_PER = 80; // tJIT(per) ps Period JItter
parameter TJIT_CC = 160; // tJIT(cc) ps Cycle to Cycle jitter
parameter TERR_2PER = 118; // tERR(2per) ps Accumulated Error (2-cycle)
parameter TERR_3PER = 140; // tERR(3per) ps Accumulated Error (3-cycle)
parameter TERR_4PER = 155; // tERR(4per) ps Accumulated Error (4-cycle)
parameter TERR_5PER = 168; // tERR(5per) ps Accumulated Error (5-cycle)
parameter TERR_6PER = 177; // tERR(6per) ps Accumulated Error (6-cycle)
parameter TERR_7PER = 186; // tERR(7per) ps Accumulated Error (7-cycle)
parameter TERR_8PER = 193; // tERR(8per) ps Accumulated Error (8-cycle)
parameter TERR_9PER = 200; // tERR(9per) ps Accumulated Error (9-cycle)
parameter TERR_10PER = 205; // tERR(10per)ps Accumulated Error (10-cycle)
parameter TERR_11PER = 210; // tERR(11per)ps Accumulated Error (11-cycle)
parameter TERR_12PER = 215; // tERR(12per)ps Accumulated Error (12-cycle)
parameter TDS = 30; // tDS ps DQ and DM input setup time relative to DQS
parameter TDH = 65; // tDH ps DQ and DM input hold time relative to DQS
parameter TDQSQ = 125; // tDQSQ ps DQS-DQ skew, DQS to last DQ valid, per group, per access
parameter TDQSS = 0.25; // tDQSS tCK Rising clock edge to DQS/DQS# latching transition
parameter TDSS = 0.20; // tDSS tCK DQS falling edge to CLK rising (setup time)
parameter TDSH = 0.20; // tDSH tCK DQS falling edge from CLK rising (hold time)
parameter TDQSCK = 255; // tDQSCK ps DQS output access time from CK/CK#
parameter TQSH = 0.40; // tQSH tCK DQS Output High Pulse Width
parameter TQSL = 0.40; // tQSL tCK DQS Output Low Pulse Width
parameter TDIPW = 400; // tDIPW ps DQ and DM input Pulse Width
parameter TIPW = 620; // tIPW ps Control and Address input Pulse Width
parameter TIS = 190; // tIS ps Input Setup Time
parameter TIH = 140; // tIH ps Input Hold Time
parameter TRAS_MIN = 36000; // tRAS ps Minimum Active to Precharge command time
parameter TRC = 49500; // tRC ps Active to Active/Auto Refresh command time
parameter TRCD = 13500; // tRCD ps Active to Read/Write command time
parameter TRP = 13500; // tRP ps Precharge command period
parameter TXP = 6000; // tXP ps Exit power down to a valid command
parameter TCKE = 5625; // tCKE ps CKE minimum high or low pulse width
parameter TAON = 250; // tAON ps RTT turn-on from ODTLon reference
parameter TWLS = 195; // tWLS ps Setup time for tDQS flop
parameter TWLH = 195; // tWLH ps Hold time of tDQS flop
parameter TWLO = 9000; // tWLO ps Write levelization output delay
parameter TAA_MIN = 13500; // TAA ps Internal READ command to first data
parameter CL_TIME = 13500; // CL ps Minimum CAS Latency
`else `ifdef sg15 // sg15 is equivelant to the JEDEC DDR3-1333J (10-10-10) speed bin
parameter TCK_MIN = 1500; // tCK ps Minimum Clock Cycle Time
parameter TJIT_PER = 80; // tJIT(per) ps Period JItter
parameter TJIT_CC = 160; // tJIT(cc) ps Cycle to Cycle jitter
parameter TERR_2PER = 118; // tERR(2per) ps Accumulated Error (2-cycle)
parameter TERR_3PER = 140; // tERR(3per) ps Accumulated Error (3-cycle)
parameter TERR_4PER = 155; // tERR(4per) ps Accumulated Error (4-cycle)
parameter TERR_5PER = 168; // tERR(5per) ps Accumulated Error (5-cycle)
parameter TERR_6PER = 177; // tERR(6per) ps Accumulated Error (6-cycle)
parameter TERR_7PER = 186; // tERR(7per) ps Accumulated Error (7-cycle)
parameter TERR_8PER = 193; // tERR(8per) ps Accumulated Error (8-cycle)
parameter TERR_9PER = 200; // tERR(9per) ps Accumulated Error (9-cycle)
parameter TERR_10PER = 205; // tERR(10per)ps Accumulated Error (10-cycle)
parameter TERR_11PER = 210; // tERR(11per)ps Accumulated Error (11-cycle)
parameter TERR_12PER = 215; // tERR(12per)ps Accumulated Error (12-cycle)
parameter TDS = 30; // tDS ps DQ and DM input setup time relative to DQS
parameter TDH = 65; // tDH ps DQ and DM input hold time relative to DQS
parameter TDQSQ = 125; // tDQSQ ps DQS-DQ skew, DQS to last DQ valid, per group, per access
parameter TDQSS = 0.25; // tDQSS tCK Rising clock edge to DQS/DQS# latching transition
parameter TDSS = 0.20; // tDSS tCK DQS falling edge to CLK rising (setup time)
parameter TDSH = 0.20; // tDSH tCK DQS falling edge from CLK rising (hold time)
parameter TDQSCK = 255; // tDQSCK ps DQS output access time from CK/CK#
parameter TQSH = 0.40; // tQSH tCK DQS Output High Pulse Width
parameter TQSL = 0.40; // tQSL tCK DQS Output Low Pulse Width
parameter TDIPW = 400; // tDIPW ps DQ and DM input Pulse Width
parameter TIPW = 620; // tIPW ps Control and Address input Pulse Width
parameter TIS = 190; // tIS ps Input Setup Time
parameter TIH = 140; // tIH ps Input Hold Time
parameter TRAS_MIN = 36000; // tRAS ps Minimum Active to Precharge command time
parameter TRC = 51000; // tRC ps Active to Active/Auto Refresh command time
parameter TRCD = 15000; // tRCD ps Active to Read/Write command time
parameter TRP = 15000; // tRP ps Precharge command period
parameter TXP = 6000; // tXP ps Exit power down to a valid command
parameter TCKE = 5625; // tCKE ps CKE minimum high or low pulse width
parameter TAON = 250; // tAON ps RTT turn-on from ODTLon reference
parameter TWLS = 195; // tWLS ps Setup time for tDQS flop
parameter TWLH = 195; // tWLH ps Hold time of tDQS flop
parameter TWLO = 9000; // tWLO ps Write levelization output delay
parameter TAA_MIN = 15000; // TAA ps Internal READ command to first data
parameter CL_TIME = 15000; // CL ps Minimum CAS Latency
`else `ifdef sg187E // sg187E is equivelant to the JEDEC DDR3-1066F (7-7-7) speed bin
parameter TCK_MIN = 1875; // tCK ps Minimum Clock Cycle Time
parameter TJIT_PER = 90; // tJIT(per) ps Period JItter
parameter TJIT_CC = 180; // tJIT(cc) ps Cycle to Cycle jitter
parameter TERR_2PER = 132; // tERR(2per) ps Accumulated Error (2-cycle)
parameter TERR_3PER = 157; // tERR(3per) ps Accumulated Error (3-cycle)
parameter TERR_4PER = 175; // tERR(4per) ps Accumulated Error (4-cycle)
parameter TERR_5PER = 188; // tERR(5per) ps Accumulated Error (5-cycle)
parameter TERR_6PER = 200; // tERR(6per) ps Accumulated Error (6-cycle)
parameter TERR_7PER = 209; // tERR(7per) ps Accumulated Error (7-cycle)
parameter TERR_8PER = 217; // tERR(8per) ps Accumulated Error (8-cycle)
parameter TERR_9PER = 224; // tERR(9per) ps Accumulated Error (9-cycle)
parameter TERR_10PER = 231; // tERR(10per)ps Accumulated Error (10-cycle)
parameter TERR_11PER = 237; // tERR(11per)ps Accumulated Error (11-cycle)
parameter TERR_12PER = 242; // tERR(12per)ps Accumulated Error (12-cycle)
parameter TDS = 25; // tDS ps DQ and DM input setup time relative to DQS
parameter TDH = 100; // tDH ps DQ and DM input hold time relative to DQS
parameter TDQSQ = 150; // tDQSQ ps DQS-DQ skew, DQS to last DQ valid, per group, per access
parameter TDQSS = 0.25; // tDQSS tCK Rising clock edge to DQS/DQS# latching transition
parameter TDSS = 0.20; // tDSS tCK DQS falling edge to CLK rising (setup time)
parameter TDSH = 0.20; // tDSH tCK DQS falling edge from CLK rising (hold time)
parameter TDQSCK = 300; // tDQSCK ps DQS output access time from CK/CK#
parameter TQSH = 0.38; // tQSH tCK DQS Output High Pulse Width
parameter TQSL = 0.38; // tQSL tCK DQS Output Low Pulse Width
parameter TDIPW = 490; // tDIPW ps DQ and DM input Pulse Width
parameter TIPW = 780; // tIPW ps Control and Address input Pulse Width
parameter TIS = 125; // tIS ps Input Setup Time
parameter TIH = 200; // tIH ps Input Hold Time
parameter TRAS_MIN = 37500; // tRAS ps Minimum Active to Precharge command time
parameter TRC = 50625; // tRC ps Active to Active/Auto Refresh command time
parameter TRCD = 13125; // tRCD ps Active to Read/Write command time
parameter TRP = 13125; // tRP ps Precharge command period
parameter TXP = 7500; // tXP ps Exit power down to a valid command
parameter TCKE = 5625; // tCKE ps CKE minimum high or low pulse width
parameter TAON = 300; // tAON ps RTT turn-on from ODTLon reference
parameter TWLS = 245; // tWLS ps Setup time for tDQS flop
parameter TWLH = 245; // tWLH ps Hold time of tDQS flop
parameter TWLO = 9000; // tWLO ps Write levelization output delay
parameter TAA_MIN = 13125; // TAA ps Internal READ command to first data
parameter CL_TIME = 13125; // CL ps Minimum CAS Latency
`else `ifdef sg187 // sg187 is equivelant to the JEDEC DDR3-1066G (8-8-8) speed bin
parameter TCK_MIN = 1875; // tCK ps Minimum Clock Cycle Time
parameter TJIT_PER = 90; // tJIT(per) ps Period JItter
parameter TJIT_CC = 180; // tJIT(cc) ps Cycle to Cycle jitter
parameter TERR_2PER = 132; // tERR(2per) ps Accumulated Error (2-cycle)
parameter TERR_3PER = 157; // tERR(3per) ps Accumulated Error (3-cycle)
parameter TERR_4PER = 175; // tERR(4per) ps Accumulated Error (4-cycle)
parameter TERR_5PER = 188; // tERR(5per) ps Accumulated Error (5-cycle)
parameter TERR_6PER = 200; // tERR(6per) ps Accumulated Error (6-cycle)
parameter TERR_7PER = 209; // tERR(7per) ps Accumulated Error (7-cycle)
parameter TERR_8PER = 217; // tERR(8per) ps Accumulated Error (8-cycle)
parameter TERR_9PER = 224; // tERR(9per) ps Accumulated Error (9-cycle)
parameter TERR_10PER = 231; // tERR(10per)ps Accumulated Error (10-cycle)
parameter TERR_11PER = 237; // tERR(11per)ps Accumulated Error (11-cycle)
parameter TERR_12PER = 242; // tERR(12per)ps Accumulated Error (12-cycle)
parameter TDS = 25; // tDS ps DQ and DM input setup time relative to DQS
parameter TDH = 100; // tDH ps DQ and DM input hold time relative to DQS
parameter TDQSQ = 150; // tDQSQ ps DQS-DQ skew, DQS to last DQ valid, per group, per access
parameter TDQSS = 0.25; // tDQSS tCK Rising clock edge to DQS/DQS# latching transition
parameter TDSS = 0.20; // tDSS tCK DQS falling edge to CLK rising (setup time)
parameter TDSH = 0.20; // tDSH tCK DQS falling edge from CLK rising (hold time)
parameter TDQSCK = 300; // tDQSCK ps DQS output access time from CK/CK#
parameter TQSH = 0.38; // tQSH tCK DQS Output High Pulse Width
parameter TQSL = 0.38; // tQSL tCK DQS Output Low Pulse Width
parameter TDIPW = 490; // tDIPW ps DQ and DM input Pulse Width
parameter TIPW = 780; // tIPW ps Control and Address input Pulse Width
parameter TIS = 125; // tIS ps Input Setup Time
parameter TIH = 200; // tIH ps Input Hold Time
parameter TRAS_MIN = 37500; // tRAS ps Minimum Active to Precharge command time
parameter TRC = 52500; // tRC ps Active to Active/Auto Refresh command time
parameter TRCD = 15000; // tRCD ps Active to Read/Write command time
parameter TRP = 15000; // tRP ps Precharge command period
parameter TXP = 7500; // tXP ps Exit power down to a valid command
parameter TCKE = 5625; // tCKE ps CKE minimum high or low pulse width
parameter TAON = 300; // tAON ps RTT turn-on from ODTLon reference
parameter TWLS = 245; // tWLS ps Setup time for tDQS flop
parameter TWLH = 245; // tWLH ps Hold time of tDQS flop
parameter TWLO = 9000; // tWLO ps Write levelization output delay
parameter TAA_MIN = 15000; // TAA ps Internal READ command to first data
parameter CL_TIME = 15000; // CL ps Minimum CAS Latency
`else `ifdef sg25E // sg25E is equivelant to the JEDEC DDR3-800D (5-5-5) speed bin
parameter TCK_MIN = 2500; // tCK ps Minimum Clock Cycle Time
parameter TJIT_PER = 100; // tJIT(per) ps Period JItter
parameter TJIT_CC = 200; // tJIT(cc) ps Cycle to Cycle jitter
parameter TERR_2PER = 147; // tERR(2per) ps Accumulated Error (2-cycle)
parameter TERR_3PER = 175; // tERR(3per) ps Accumulated Error (3-cycle)
parameter TERR_4PER = 194; // tERR(4per) ps Accumulated Error (4-cycle)
parameter TERR_5PER = 209; // tERR(5per) ps Accumulated Error (5-cycle)
parameter TERR_6PER = 222; // tERR(6per) ps Accumulated Error (6-cycle)
parameter TERR_7PER = 232; // tERR(7per) ps Accumulated Error (7-cycle)
parameter TERR_8PER = 241; // tERR(8per) ps Accumulated Error (8-cycle)
parameter TERR_9PER = 249; // tERR(9per) ps Accumulated Error (9-cycle)
parameter TERR_10PER = 257; // tERR(10per)ps Accumulated Error (10-cycle)
parameter TERR_11PER = 263; // tERR(11per)ps Accumulated Error (11-cycle)
parameter TERR_12PER = 269; // tERR(12per)ps Accumulated Error (12-cycle)
parameter TDS = 75; // tDS ps DQ and DM input setup time relative to DQS
parameter TDH = 150; // tDH ps DQ and DM input hold time relative to DQS
parameter TDQSQ = 200; // tDQSQ ps DQS-DQ skew, DQS to last DQ valid, per group, per access
parameter TDQSS = 0.25; // tDQSS tCK Rising clock edge to DQS/DQS# latching transition
parameter TDSS = 0.20; // tDSS tCK DQS falling edge to CLK rising (setup time)
parameter TDSH = 0.20; // tDSH tCK DQS falling edge from CLK rising (hold time)
parameter TDQSCK = 400; // tDQSCK ps DQS output access time from CK/CK#
parameter TQSH = 0.38; // tQSH tCK DQS Output High Pulse Width
parameter TQSL = 0.38; // tQSL tCK DQS Output Low Pulse Width
parameter TDIPW = 600; // tDIPW ps DQ and DM input Pulse Width
parameter TIPW = 900; // tIPW ps Control and Address input Pulse Width
parameter TIS = 200; // tIS ps Input Setup Time
parameter TIH = 275; // tIH ps Input Hold Time
parameter TRAS_MIN = 37500; // tRAS ps Minimum Active to Precharge command time
parameter TRC = 50000; // tRC ps Active to Active/Auto Refresh command time
parameter TRCD = 12500; // tRCD ps Active to Read/Write command time
parameter TRP = 12500; // tRP ps Precharge command period
parameter TXP = 7500; // tXP ps Exit power down to a valid command
parameter TCKE = 7500; // tCKE ps CKE minimum high or low pulse width
parameter TAON = 400; // tAON ps RTT turn-on from ODTLon reference
parameter TWLS = 325; // tWLS ps Setup time for tDQS flop
parameter TWLH = 325; // tWLH ps Hold time of tDQS flop
parameter TWLO = 9000; // tWLO ps Write levelization output delay
parameter TAA_MIN = 12500; // TAA ps Internal READ command to first data
parameter CL_TIME = 12500; // CL ps Minimum CAS Latency
`else
`define sg25 // sg25 is equivelant to the JEDEC DDR3-800E (6-6-6) speed bin
parameter TCK_MIN = 2500; // tCK ps Minimum Clock Cycle Time
parameter TJIT_PER = 100; // tJIT(per) ps Period JItter
parameter TJIT_CC = 200; // tJIT(cc) ps Cycle to Cycle jitter
parameter TERR_2PER = 147; // tERR(2per) ps Accumulated Error (2-cycle)
parameter TERR_3PER = 175; // tERR(3per) ps Accumulated Error (3-cycle)
parameter TERR_4PER = 194; // tERR(4per) ps Accumulated Error (4-cycle)
parameter TERR_5PER = 209; // tERR(5per) ps Accumulated Error (5-cycle)
parameter TERR_6PER = 222; // tERR(6per) ps Accumulated Error (6-cycle)
parameter TERR_7PER = 232; // tERR(7per) ps Accumulated Error (7-cycle)
parameter TERR_8PER = 241; // tERR(8per) ps Accumulated Error (8-cycle)
parameter TERR_9PER = 249; // tERR(9per) ps Accumulated Error (9-cycle)
parameter TERR_10PER = 257; // tERR(10per)ps Accumulated Error (10-cycle)
parameter TERR_11PER = 263; // tERR(11per)ps Accumulated Error (11-cycle)
parameter TERR_12PER = 269; // tERR(12per)ps Accumulated Error (12-cycle)
parameter TDS = 75; // tDS ps DQ and DM input setup time relative to DQS
parameter TDH = 150; // tDH ps DQ and DM input hold time relative to DQS
parameter TDQSQ = 200; // tDQSQ ps DQS-DQ skew, DQS to last DQ valid, per group, per access
parameter TDQSS = 0.25; // tDQSS tCK Rising clock edge to DQS/DQS# latching transition
parameter TDSS = 0.20; // tDSS tCK DQS falling edge to CLK rising (setup time)
parameter TDSH = 0.20; // tDSH tCK DQS falling edge from CLK rising (hold time)
parameter TDQSCK = 400; // tDQSCK ps DQS output access time from CK/CK#
parameter TQSH = 0.38; // tQSH tCK DQS Output High Pulse Width
parameter TQSL = 0.38; // tQSL tCK DQS Output Low Pulse Width
parameter TDIPW = 600; // tDIPW ps DQ and DM input Pulse Width
parameter TIPW = 900; // tIPW ps Control and Address input Pulse Width
parameter TIS = 200; // tIS ps Input Setup Time
parameter TIH = 275; // tIH ps Input Hold Time
parameter TRAS_MIN = 37500; // tRAS ps Minimum Active to Precharge command time
parameter TRC = 52500; // tRC ps Active to Active/Auto Refresh command time
parameter TRCD = 15000; // tRCD ps Active to Read/Write command time
parameter TRP = 15000; // tRP ps Precharge command period
parameter TXP = 7500; // tXP ps Exit power down to a valid command
parameter TCKE = 7500; // tCKE ps CKE minimum high or low pulse width
parameter TAON = 400; // tAON ps RTT turn-on from ODTLon reference
parameter TWLS = 325; // tWLS ps Setup time for tDQS flop
parameter TWLH = 325; // tWLH ps Hold time of tDQS flop
parameter TWLO = 9000; // tWLO ps Write levelization output delay
parameter TAA_MIN = 15000; // TAA ps Internal READ command to first data
parameter CL_TIME = 15000; // CL ps Minimum CAS Latency
`endif `endif `endif `endif `endif
`ifdef x16
`ifdef sg15E
parameter TRRD = 7500; // tRRD ps (2KB page size) Active bank a to Active bank b command time
parameter TFAW = 45000; // tFAW ps (2KB page size) Four Bank Activate window
`else `ifdef sg15
parameter TRRD = 7500; // tRRD ps (2KB page size) Active bank a to Active bank b command time
parameter TFAW = 45000; // tFAW ps (2KB page size) Four Bank Activate window
`else // sg187E, sg187, sg25, sg25E
parameter TRRD = 10000; // tRRD ps (2KB page size) Active bank a to Active bank b command time
parameter TFAW = 50000; // tFAW ps (2KB page size) Four Bank Activate window
`endif `endif
`else // x4, x8
`ifdef sg15E
parameter TRRD = 6000; // tRRD ps (1KB page size) Active bank a to Active bank b command time
parameter TFAW = 30000; // tFAW ps (1KB page size) Four Bank Activate window
`else `ifdef sg15
parameter TRRD = 6000; // tRRD ps (1KB page size) Active bank a to Active bank b command time
parameter TFAW = 30000; // tFAW ps (1KB page size) Four Bank Activate window
`else `ifdef sg187E
parameter TRRD = 7500; // tRRD ps (1KB page size) Active bank a to Active bank b command time
parameter TFAW = 37500; // tFAW ps (1KB page size) Four Bank Activate window
`else `ifdef sg187
parameter TRRD = 7500; // tRRD ps (1KB page size) Active bank a to Active bank b command time
parameter TFAW = 37500; // tFAW ps (1KB page size) Four Bank Activate window
`else // sg25, sg25E
parameter TRRD = 10000; // tRRD ps (1KB page size) Active bank a to Active bank b command time
parameter TFAW = 40000; // tFAW ps (1KB page size) Four Bank Activate window
`endif `endif `endif `endif
`endif
// Timing Parameters
// Mode Register
parameter CL_MIN = 5; // CL tCK Minimum CAS Latency
parameter CL_MAX = 11; // CL tCK Maximum CAS Latency
parameter AL_MIN = 0; // AL tCK Minimum Additive Latency
parameter AL_MAX = 2; // AL tCK Maximum Additive Latency
parameter WR_MIN = 5; // WR tCK Minimum Write Recovery
parameter WR_MAX = 12; // WR tCK Maximum Write Recovery
parameter BL_MIN = 4; // BL tCK Minimum Burst Length
parameter BL_MAX = 8; // BL tCK Minimum Burst Length
parameter CWL_MIN = 5; // CWL tCK Minimum CAS Write Latency
parameter CWL_MAX = 8; // CWL tCK Maximum CAS Write Latency
// Clock
parameter TCK_MAX = 3300; // tCK ps Maximum Clock Cycle Time
parameter TCH_AVG_MIN = 0.47; // tCH tCK Minimum Clock High-Level Pulse Width
parameter TCL_AVG_MIN = 0.47; // tCL tCK Minimum Clock Low-Level Pulse Width
parameter TCH_AVG_MAX = 0.53; // tCH tCK Maximum Clock High-Level Pulse Width
parameter TCL_AVG_MAX = 0.53; // tCL tCK Maximum Clock Low-Level Pulse Width
parameter TCH_ABS_MIN = 0.43; // tCH tCK Minimum Clock High-Level Pulse Width
parameter TCL_ABS_MIN = 0.43; // tCL tCK Maximum Clock Low-Level Pulse Width
parameter TCKE_TCK = 3; // tCKE tCK CKE minimum high or low pulse width
parameter TAA_MAX = 20000; // TAA ps Internal READ command to first data
// Data OUT
parameter TQH = 0.38; // tQH ps DQ output hold time from DQS, DQS#
// Data Strobe OUT
parameter TRPRE = 0.90; // tRPRE tCK DQS Read Preamble
parameter TRPST = 0.30; // tRPST tCK DQS Read Postamble
// Data Strobe IN
parameter TDQSH = 0.45; // tDQSH tCK DQS input High Pulse Width
parameter TDQSL = 0.45; // tDQSL tCK DQS input Low Pulse Width
parameter TWPRE = 0.90; // tWPRE tCK DQS Write Preamble
parameter TWPST = 0.30; // tWPST tCK DQS Write Postamble
// Command and Address
parameter TZQCS = 64; // tZQCS tCK ZQ Cal (Short) time
parameter TZQINIT = 512; // tZQinit tCK ZQ Cal (Long) time
parameter TZQOPER = 256; // tZQoper tCK ZQ Cal (Long) time
parameter TCCD = 4; // tCCD tCK Cas to Cas command delay
parameter TCCD_DG = 2; // tCCD_DG tCK Cas to Cas command delay to different group
parameter TRAS_MAX =70312500; // tRAS ps Maximum Active to Precharge command time
parameter TWR = 15000; // tWR ps Write recovery time
parameter TMRD = 4; // tMRD tCK Load Mode Register command cycle time
parameter TMOD = 15000; // tMOD ps LOAD MODE to non-LOAD MODE command cycle time
parameter TMOD_TCK = 12; // tMOD tCK LOAD MODE to non-LOAD MODE command cycle time
parameter TRRD_TCK = 4; // tRRD tCK Active bank a to Active bank b command time
parameter TRRD_DG = 3000; // tRRD_DG ps Active bank a to Active bank b command time to different group
parameter TRRD_DG_TCK = 2; // tRRD_DG tCK Active bank a to Active bank b command time to different group
parameter TRTP = 7500; // tRTP ps Read to Precharge command delay
parameter TRTP_TCK = 4; // tRTP tCK Read to Precharge command delay
parameter TWTR = 7500; // tWTR ps Write to Read command delay
parameter TWTR_DG = 3750; // tWTR_DG ps Write to Read command delay to different group
parameter TWTR_TCK = 4; // tWTR tCK Write to Read command delay
parameter TWTR_DG_TCK = 2; // tWTR_DG tCK Write to Read command delay to different group
parameter TDLLK = 512; // tDLLK tCK DLL locking time
// Refresh - 2Gb
parameter TRFC_MIN = 160000; // tRFC ps Refresh to Refresh Command interval minimum value
parameter TRFC_MAX =70312500; // tRFC ps Refresh to Refresh Command Interval maximum value
// Power Down
parameter TXP_TCK = 3; // tXP tCK Exit power down to a valid command
parameter TXPDLL = 24000; // tXPDLL ps Exit precharge power down to READ or WRITE command (DLL-off mode)
parameter TXPDLL_TCK = 10; // tXPDLL tCK Exit precharge power down to READ or WRITE command (DLL-off mode)
parameter TACTPDEN = 1; // tACTPDEN tCK Timing of last ACT command to power down entry
parameter TPRPDEN = 1; // tPREPDEN tCK Timing of last PRE command to power down entry
parameter TREFPDEN = 1; // tARPDEN tCK Timing of last REFRESH command to power down entry
parameter TCPDED = 1; // tCPDED tCK Command pass disable/enable delay
parameter TPD_MAX =TRFC_MAX; // tPD ps Power-down entry-to-exit timing
parameter TXPR = 170000; // tXPR ps Exit Reset from CKE assertion to a valid command
parameter TXPR_TCK = 5; // tXPR tCK Exit Reset from CKE assertion to a valid command
// Self Refresh
parameter TXS = 170000; // tXS ps Exit self refesh to a non-read or write command
parameter TXS_TCK = 5; // tXS tCK Exit self refesh to a non-read or write command
parameter TXSDLL = TDLLK; // tXSRD tCK Exit self refresh to a read or write command
parameter TISXR = TIS; // tISXR ps CKE setup time during self refresh exit.
parameter TCKSRE = 10000; // tCKSRE ps Valid Clock requirement after self refresh entry (SRE)
parameter TCKSRE_TCK = 5; // tCKSRE tCK Valid Clock requirement after self refresh entry (SRE)
parameter TCKSRX = 10000; // tCKSRX ps Valid Clock requirement prior to self refresh exit (SRX)
parameter TCKSRX_TCK = 5; // tCKSRX tCK Valid Clock requirement prior to self refresh exit (SRX)
parameter TCKESR_TCK = 4; // tCKESR tCK Minimum CKE low width for Self Refresh entry to exit timing
// ODT
parameter TAOF = 0.7; // tAOF tCK RTT turn-off from ODTLoff reference
parameter TAONPD = 9000; // tAONPD ps Asynchronous RTT turn-on delay (Power-Down with DLL frozen)
parameter TAOFPD = 9000; // tAONPD ps Asynchronous RTT turn-off delay (Power-Down with DLL frozen)
parameter ODTH4 = 4; // ODTH4 tCK ODT minimum HIGH time after ODT assertion or write (BL4)
parameter ODTH8 = 6; // ODTH8 tCK ODT minimum HIGH time after write (BL8)
parameter TADC = 0.7; // tADC tCK RTT dynamic change skew
// Write Levelization
parameter TWLMRD = 40; // tWLMRD tCK First DQS pulse rising edge after tDQSS margining mode is programmed
parameter TWLDQSEN = 25; // tWLDQSEN tCK DQS/DQS delay after tDQSS margining mode is programmed
parameter TWLOE = 2000; // tWLOE ps Write levelization output error
// Size Parameters based on Part Width
`ifdef x4
parameter DM_BITS = 1; // Set this parameter to control how many Data Mask bits are used
parameter ADDR_BITS = 15; // MAX Address Bits
parameter ROW_BITS = 15; // Set this parameter to control how many Address bits are used
parameter COL_BITS = 11; // Set this parameter to control how many Column bits are used
parameter DQ_BITS = 4; // Set this parameter to control how many Data bits are used **Same as part bit width**
parameter DQS_BITS = 1; // Set this parameter to control how many Dqs bits are used
`else `ifdef x8
parameter DM_BITS = 1; // Set this parameter to control how many Data Mask bits are used
parameter ADDR_BITS = 15; // MAX Address Bits
parameter ROW_BITS = 15; // Set this parameter to control how many Address bits are used
parameter COL_BITS = 10; // Set this parameter to control how many Column bits are used
parameter DQ_BITS = 8; // Set this parameter to control how many Data bits are used **Same as part bit width**
parameter DQS_BITS = 1; // Set this parameter to control how many Dqs bits are used
`else
`define x16
parameter DM_BITS = 2; // Set this parameter to control how many Data Mask bits are used
parameter ADDR_BITS = 14; // MAX Address Bits
parameter ROW_BITS = 14; // Set this parameter to control how many Address bits are used
parameter COL_BITS = 10; // Set this parameter to control how many Column bits are used
parameter DQ_BITS = 16; // Set this parameter to control how many Data bits are used **Same as part bit width**
parameter DQS_BITS = 2; // Set this parameter to control how many Dqs bits are used
`endif `endif
// Size Parameters
parameter BA_BITS = 3; // Set this parmaeter to control how many Bank Address bits are used
parameter MEM_BITS = 15; // Set this parameter to control how many write data bursts can be stored in memory. The default is 2^10=1024.
parameter AP = 10; // the address bit that controls auto-precharge and precharge-all
parameter BC = 12; // the address bit that controls burst chop
parameter BL_BITS = 3; // the number of bits required to count to BL_MAX
parameter BO_BITS = 2; // the number of Burst Order Bits
`ifdef QUAD_RANK
`define DUAL_RANK // also define DUAL_RANK
parameter CS_BITS = 4; // Number of Chip Select Bits
parameter RANKS = 4; // Number of Chip Selects
`else `ifdef DUAL_RANK
parameter CS_BITS = 2; // Number of Chip Select Bits
parameter RANKS = 2; // Number of Chip Selects
`else
parameter CS_BITS = 2; // Number of Chip Select Bits
parameter RANKS = 1; // Number of Chip Selects
`endif `endif
// Simulation parameters
parameter RZQ = 240; // termination resistance
parameter PRE_DEF_PAT = 8'hAA; // value returned during mpr pre-defined pattern readout
parameter STOP_ON_ERROR = 1; // If set to 1, the model will halt on command sequence/major errors
parameter DEBUG = 0; // Turn on Debug messages
parameter BUS_DELAY = 0; // delay in nanoseconds
parameter RANDOM_OUT_DELAY = 0; // If set to 1, the model will put a random amount of delay on DQ/DQS during reads
parameter RANDOM_SEED = 711689044; //seed value for random generator.
parameter RDQSEN_PRE = 2; // DQS driving time prior to first read strobe
parameter RDQSEN_PST = 1; // DQS driving time after last read strobe
parameter RDQS_PRE = 2; // DQS low time prior to first read strobe
parameter RDQS_PST = 1; // DQS low time after last read strobe
parameter RDQEN_PRE = 0; // DQ/DM driving time prior to first read data
parameter RDQEN_PST = 0; // DQ/DM driving time after last read data
parameter WDQS_PRE = 2; // DQS half clock periods prior to first write strobe
parameter WDQS_PST = 1; // DQS half clock periods after last write strobe
// check for legal cas latency based on the cas write latency
function valid_cl;
input [3:0] cl;
input [3:0] cwl;
case ({cwl, cl})
`ifdef sg15E
{4'd5, 4'd6 },
{4'd6, 4'd8 },
{4'd7, 4'd9 },
{4'd7, 4'd10}: valid_cl = 1;
`else `ifdef sg15
{4'd5, 4'd6 },
{4'd6, 4'd8 },
{4'd7, 4'd10}: valid_cl = 1;
`else `ifdef sg187E
{4'd5, 4'd6 },
{4'd6, 4'd7 },
{4'd6, 4'd8 }: valid_cl = 1;
`else `ifdef sg187
{4'd5, 4'd6 },
{4'd6, 4'd8 }: valid_cl = 1;
`else `ifdef sg25E
{4'd5, 4'd5 },
{4'd5, 4'd6 }: valid_cl = 1;
`else `ifdef sg25
{4'd5, 4'd6 }: valid_cl = 1;
`endif `endif `endif `endif `endif `endif
default : valid_cl = 0;
endcase
endfunction
// find the minimum valid cas write latency
function [3:0] min_cwl;
input period;
real period;
min_cwl = (period >= 2500.0) ? 5:
(period >= 1875.0) ? 6:
(period >= 1500.0) ? 7:
8; //(period >= 1250.0)
endfunction
// find the minimum valid cas latency
function [3:0] min_cl;
input period;
real period;
reg [3:0] cwl;
reg [3:0] cl;
begin
cwl = min_cwl(period);
for (cl=CL_MAX; cl>=CL_MIN; cl=cl-1) begin
if (valid_cl(cl, cwl)) begin
min_cl = cl;
end
end
end
endfunction
`endif
parameter check_strict_mrbits = 1;
parameter check_strict_timing = 1;
parameter feature_pasr = 1;
parameter feature_truebl4 = 0;
// text macros
`define DQ_PER_DQS DQ_BITS/DQS_BITS
`define BANKS (1<<BA_BITS)
`define MAX_BITS (BA_BITS+ROW_BITS+COL_BITS-BL_BITS)
`define MAX_SIZE (1<<(BA_BITS+ROW_BITS+COL_BITS-BL_BITS))
`define MEM_SIZE (1<<MEM_BITS)
`define MAX_PIPE 4*CL_MAX
// Declare Ports
input rst_n;
input ck;
input ck_n;
input cke;
input cs_n;
input ras_n;
input cas_n;
input we_n;
inout [DM_BITS-1:0] dm_tdqs;
input [BA_BITS-1:0] ba;
input [ADDR_BITS-1:0] addr;
inout [DQ_BITS-1:0] dq;
inout [DQS_BITS-1:0] dqs;
inout [DQS_BITS-1:0] dqs_n;
output [DQS_BITS-1:0] tdqs_n;
input odt;
// clock jitter
real tck_avg;
time tck_sample [TDLLK-1:0];
time tch_sample [TDLLK-1:0];
time tcl_sample [TDLLK-1:0];
time tck_i;
time tch_i;
time tcl_i;
real tch_avg;
real tcl_avg;
time tm_ck_pos;
time tm_ck_neg;
real tjit_per_rtime;
integer tjit_cc_time;
real terr_nper_rtime;
//DDR3 clock jitter variables
real tjit_ch_rtime;
real duty_cycle;
// clock skew
real out_delay;
integer dqsck [DQS_BITS-1:0];
integer dqsck_min;
integer dqsck_max;
integer dqsq_min;
integer dqsq_max;
integer seed;
// Mode Registers
reg [ADDR_BITS-1:0] mode_reg [`BANKS-1:0];
reg burst_order;
reg [BL_BITS:0] burst_length;
reg blotf;
reg truebl4;
integer cas_latency;
reg dll_reset;
reg dll_locked;
integer write_recovery;
reg low_power;
reg dll_en;
reg [2:0] odt_rtt_nom;
reg [1:0] odt_rtt_wr;
reg odt_en;
reg dyn_odt_en;
reg [1:0] al;
integer additive_latency;
reg write_levelization;
reg duty_cycle_corrector;
reg tdqs_en;
reg out_en;
reg [2:0] pasr;
integer cas_write_latency;
reg asr; // auto self refresh
reg srt; // self refresh temperature range
reg [1:0] mpr_select;
reg mpr_en;
reg odts_readout;
integer read_latency;
integer write_latency;
// cmd encoding
parameter // {cs, ras, cas, we}
LOAD_MODE = 4'b0000,
REFRESH = 4'b0001,
PRECHARGE = 4'b0010,
ACTIVATE = 4'b0011,
WRITE = 4'b0100,
READ = 4'b0101,
ZQ = 4'b0110,
NOP = 4'b0111,
// DESEL = 4'b1xxx,
PWR_DOWN = 4'b1000,
SELF_REF = 4'b1001
;
reg [8*9-1:0] cmd_string [9:0];
initial begin
cmd_string[LOAD_MODE] = "Load Mode";
cmd_string[REFRESH ] = "Refresh ";
cmd_string[PRECHARGE] = "Precharge";
cmd_string[ACTIVATE ] = "Activate ";
cmd_string[WRITE ] = "Write ";
cmd_string[READ ] = "Read ";
cmd_string[ZQ ] = "ZQ ";
cmd_string[NOP ] = "No Op ";
cmd_string[PWR_DOWN ] = "Pwr Down ";
cmd_string[SELF_REF ] = "Self Ref ";
end
// command state
reg [`BANKS-1:0] active_bank;
reg [`BANKS-1:0] auto_precharge_bank;
reg [`BANKS-1:0] write_precharge_bank;
reg [`BANKS-1:0] read_precharge_bank;
reg [ROW_BITS-1:0] active_row [`BANKS-1:0];
reg in_power_down;
reg in_self_refresh;
reg [3:0] init_mode_reg;
reg init_dll_reset;
reg init_done;
integer init_step;
reg zq_set;
reg er_trfc_max;
reg odt_state;
reg odt_state_dly;
reg dyn_odt_state;
reg dyn_odt_state_dly;
reg prev_odt;
wire [7:0] calibration_pattern = 8'b10101010; // value returned during mpr pre-defined pattern readout
wire [7:0] temp_sensor = 8'h01; // value returned during mpr temp sensor readout
reg [1:0] mr_chk;
reg rd_bc;
integer banki;
// cmd timers/counters
integer ref_cntr;
integer odt_cntr;
integer ck_cntr;
integer ck_txpr;
integer ck_load_mode;
integer ck_refresh;
integer ck_precharge;
integer ck_activate;
integer ck_write;
integer ck_read;
integer ck_zqinit;
integer ck_zqoper;
integer ck_zqcs;
integer ck_power_down;
integer ck_slow_exit_pd;
integer ck_self_refresh;
integer ck_freq_change;
integer ck_odt;
integer ck_odth8;
integer ck_dll_reset;
integer ck_cke_cmd;
integer ck_bank_write [`BANKS-1:0];
integer ck_bank_read [`BANKS-1:0];
integer ck_group_activate [1:0];
integer ck_group_write [1:0];
integer ck_group_read [1:0];
time tm_txpr;
time tm_load_mode;
time tm_refresh;
time tm_precharge;
time tm_activate;
time tm_write_end;
time tm_power_down;
time tm_slow_exit_pd;
time tm_self_refresh;
time tm_freq_change;
time tm_cke_cmd;
time tm_ttsinit;
time tm_bank_precharge [`BANKS-1:0];
time tm_bank_activate [`BANKS-1:0];
time tm_bank_write_end [`BANKS-1:0];
time tm_bank_read_end [`BANKS-1:0];
time tm_group_activate [1:0];
time tm_group_write_end [1:0];
// pipelines
reg [`MAX_PIPE:0] al_pipeline;
reg [`MAX_PIPE:0] wr_pipeline;
reg [`MAX_PIPE:0] rd_pipeline;
reg [`MAX_PIPE:0] odt_pipeline;
reg [`MAX_PIPE:0] dyn_odt_pipeline;
reg [BL_BITS:0] bl_pipeline [`MAX_PIPE:0];
reg [BA_BITS-1:0] ba_pipeline [`MAX_PIPE:0];
reg [ROW_BITS-1:0] row_pipeline [`MAX_PIPE:0];
reg [COL_BITS-1:0] col_pipeline [`MAX_PIPE:0];
reg prev_cke;
// data state
reg [BL_MAX*DQ_BITS-1:0] memory_data;
reg [BL_MAX*DQ_BITS-1:0] bit_mask;
reg [BL_BITS-1:0] burst_position;
reg [BL_BITS:0] burst_cntr;
reg [DQ_BITS-1:0] dq_temp;
reg [31:0] check_write_postamble;
reg [31:0] check_write_preamble;
reg [31:0] check_write_dqs_high;
reg [31:0] check_write_dqs_low;
reg [15:0] check_dm_tdipw;
reg [63:0] check_dq_tdipw;
// data timers/counters
time tm_rst_n;
time tm_cke;
time tm_odt;
time tm_tdqss;
time tm_dm [15:0];
time tm_dqs [15:0];
time tm_dqs_pos [31:0];
time tm_dqss_pos [31:0];
time tm_dqs_neg [31:0];
time tm_dq [63:0];
time tm_cmd_addr [22:0];
reg [8*7-1:0] cmd_addr_string [22:0];
initial begin
cmd_addr_string[ 0] = "CS_N ";
cmd_addr_string[ 1] = "RAS_N ";
cmd_addr_string[ 2] = "CAS_N ";
cmd_addr_string[ 3] = "WE_N ";
cmd_addr_string[ 4] = "BA 0 ";
cmd_addr_string[ 5] = "BA 1 ";
cmd_addr_string[ 6] = "BA 2 ";
cmd_addr_string[ 7] = "ADDR 0";
cmd_addr_string[ 8] = "ADDR 1";
cmd_addr_string[ 9] = "ADDR 2";
cmd_addr_string[10] = "ADDR 3";
cmd_addr_string[11] = "ADDR 4";
cmd_addr_string[12] = "ADDR 5";
cmd_addr_string[13] = "ADDR 6";
cmd_addr_string[14] = "ADDR 7";
cmd_addr_string[15] = "ADDR 8";
cmd_addr_string[16] = "ADDR 9";
cmd_addr_string[17] = "ADDR 10";
cmd_addr_string[18] = "ADDR 11";
cmd_addr_string[19] = "ADDR 12";
cmd_addr_string[20] = "ADDR 13";
cmd_addr_string[21] = "ADDR 14";
cmd_addr_string[22] = "ADDR 15";
end
reg [8*5-1:0] dqs_string [1:0];
initial begin
dqs_string[0] = "DQS ";
dqs_string[1] = "DQS_N";
end
// Memory Storage
`ifdef MAX_MEM
parameter RFF_BITS = DQ_BITS*BL_MAX;
// %z format uses 8 bytes for every 32 bits or less.
parameter RFF_CHUNK = 8 * (RFF_BITS/32 + (RFF_BITS%32 ? 1 : 0));
reg [1024:1] tmp_model_dir;
integer memfd[`BANKS-1:0];
initial
begin : file_io_open
integer bank;
if (!$value$plusargs("model_data+%s", tmp_model_dir))
begin
tmp_model_dir = "/tmp";
$display(
"%m: at time %t WARNING: no +model_data option specified, using /tmp.",
$time
);
end
for (bank = 0; bank < `BANKS; bank = bank + 1)
memfd[bank] = open_bank_file(bank);
end
`else
reg [BL_MAX*DQ_BITS-1:0] memory [0:`MEM_SIZE-1];
reg [`MAX_BITS-1:0] address [0:`MEM_SIZE-1];
reg [MEM_BITS:0] memory_index;
reg [MEM_BITS:0] memory_used = 0;
`endif
// receive
reg rst_n_in;
reg ck_in;
reg ck_n_in;
reg cke_in;
reg cs_n_in;
reg ras_n_in;
reg cas_n_in;
reg we_n_in;
reg [15:0] dm_in;
reg [2:0] ba_in;
reg [15:0] addr_in;
reg [63:0] dq_in;
reg [31:0] dqs_in;
reg odt_in;
reg [15:0] dm_in_pos;
reg [15:0] dm_in_neg;
reg [63:0] dq_in_pos;
reg [63:0] dq_in_neg;
reg dq_in_valid;
reg dqs_in_valid;
integer wdqs_cntr;
integer wdq_cntr;
integer wdqs_pos_cntr [31:0];
reg b2b_write;
reg [BL_BITS:0] wr_burst_length;
reg [31:0] prev_dqs_in;
reg diff_ck;
always @(rst_n ) rst_n_in <= #BUS_DELAY rst_n;
always @(ck ) ck_in <= #BUS_DELAY ck;
always @(ck_n ) ck_n_in <= #BUS_DELAY ck_n;
always @(cke ) cke_in <= #BUS_DELAY cke;
always @(cs_n ) cs_n_in <= #BUS_DELAY cs_n;
always @(ras_n ) ras_n_in <= #BUS_DELAY ras_n;
always @(cas_n ) cas_n_in <= #BUS_DELAY cas_n;
always @(we_n ) we_n_in <= #BUS_DELAY we_n;
always @(dm_tdqs) dm_in <= #BUS_DELAY dm_tdqs;
always @(ba ) ba_in <= #BUS_DELAY ba;
always @(addr ) addr_in <= #BUS_DELAY addr;
always @(dq ) dq_in <= #BUS_DELAY dq;
always @(dqs or dqs_n) dqs_in <= #BUS_DELAY (dqs_n<<16) | dqs;
always @(odt ) odt_in <= #BUS_DELAY odt;
// create internal clock
always @(posedge ck_in) diff_ck <= ck_in;
always @(posedge ck_n_in) diff_ck <= ~ck_n_in;
wire [15:0] dqs_even = dqs_in[15:0];
wire [15:0] dqs_odd = dqs_in[31:16];
wire [3:0] cmd_n_in = !cs_n_in ? {ras_n_in, cas_n_in, we_n_in} : NOP; //deselect = nop
// transmit
reg dqs_out_en;
reg [DQS_BITS-1:0] dqs_out_en_dly;
reg dqs_out;
reg [DQS_BITS-1:0] dqs_out_dly;
reg dq_out_en;
reg [DQ_BITS-1:0] dq_out_en_dly;
reg [DQ_BITS-1:0] dq_out;
reg [DQ_BITS-1:0] dq_out_dly;
integer rdqsen_cntr;
integer rdqs_cntr;
integer rdqen_cntr;
integer rdq_cntr;
bufif1 buf_dqs [DQS_BITS-1:0] (dqs, dqs_out_dly, dqs_out_en_dly & {DQS_BITS{out_en}});
bufif1 buf_dqs_n [DQS_BITS-1:0] (dqs_n, ~dqs_out_dly, dqs_out_en_dly & {DQS_BITS{out_en}});
bufif1 buf_dq [DQ_BITS-1:0] (dq, dq_out_dly, dq_out_en_dly & {DQ_BITS {out_en}});
assign tdqs_n = {DQS_BITS{1'bz}};
initial begin
if (BL_MAX < 2)
$display("%m ERROR: BL_MAX parameter must be >= 2. \nBL_MAX = %d", BL_MAX);
if ((1<<BO_BITS) > BL_MAX)
$display("%m ERROR: 2^BO_BITS cannot be greater than BL_MAX parameter.");
$timeformat (-12, 1, " ps", 1);
seed = RANDOM_SEED;
ck_cntr = 0;
end
function integer get_rtt_wr;
input [1:0] rtt;
begin
get_rtt_wr = RZQ/{rtt[0], rtt[1], 1'b0};
end
endfunction
function integer get_rtt_nom;
input [2:0] rtt;
begin
case (rtt)
1: get_rtt_nom = RZQ/4;
2: get_rtt_nom = RZQ/2;
3: get_rtt_nom = RZQ/6;
4: get_rtt_nom = RZQ/12;
5: get_rtt_nom = RZQ/8;
default : get_rtt_nom = 0;
endcase
end
endfunction
// calculate the absolute value of a real number
function real abs_value;
input arg;
real arg;
begin
if (arg < 0.0)
abs_value = -1.0 * arg;
else
abs_value = arg;
end
endfunction
function integer ceil;
input number;
real number;
// LMR 4.1.7
// When either operand of a relational expression is a real operand then the other operand shall be converted
// to an equivalent real value, and the expression shall be interpreted as a comparison between two real values.
if (number > $rtoi(number))
ceil = $rtoi(number) + 1;
else
ceil = number;
endfunction
function integer floor;
input number;
real number;
// LMR 4.1.7
// When either operand of a relational expression is a real operand then the other operand shall be converted
// to an equivalent real value, and the expression shall be interpreted as a comparison between two real values.
if (number < $rtoi(number))
floor = $rtoi(number) - 1;
else
floor = number;
endfunction
`ifdef MAX_MEM
function integer open_bank_file( input integer bank );
integer fd;
reg [2048:1] filename;
begin
$sformat( filename, "%0s/%m.%0d", tmp_model_dir, bank );
fd = $fopen(filename, "w+");
if (fd == 0)
begin
$display("%m: at time %0t ERROR: failed to open %0s.", $time, filename);
$finish;
end
else
begin
if (DEBUG) $display("%m: at time %0t INFO: opening %0s.", $time, filename);
open_bank_file = fd;
end
end
endfunction
function [RFF_BITS:1] read_from_file(
input integer fd,
input integer index
);
integer code;
integer offset;
reg [1024:1] msg;
reg [RFF_BITS:1] read_value;
begin
offset = index * RFF_CHUNK;
code = $fseek( fd, offset, 0 );
// $fseek returns 0 on success, -1 on failure
if (code != 0)
begin
$display("%m: at time %t ERROR: fseek to %d failed", $time, offset);
$finish;
end
code = $fscanf(fd, "%z", read_value);
// $fscanf returns number of items read
if (code != 1)
begin
if ($ferror(fd,msg) != 0)
begin
$display("%m: at time %t ERROR: fscanf failed at %d", $time, index);
$display(msg);
$finish;
end
else
read_value = 'hx;
end
/* when reading from unwritten portions of the file, 0 will be returned.
* Use 0 in bit 1 as indicator that invalid data has been read.
* A true 0 is encoded as Z.
*/
if (read_value[1] === 1'bz)
// true 0 encoded as Z, data is valid
read_value[1] = 1'b0;
else if (read_value[1] === 1'b0)
// read from file section that has not been written
read_value = 'hx;
read_from_file = read_value;
end
endfunction
task write_to_file(
input integer fd,
input integer index,
input [RFF_BITS:1] data
);
integer code;
integer offset;
begin
offset = index * RFF_CHUNK;
code = $fseek( fd, offset, 0 );
if (code != 0)
begin
$display("%m: at time %t ERROR: fseek to %d failed", $time, offset);
$finish;
end
// encode a valid data
if (data[1] === 1'bz)
data[1] = 1'bx;
else if (data[1] === 1'b0)
data[1] = 1'bz;
$fwrite( fd, "%z", data );
end
endtask
`else
function get_index;
input [`MAX_BITS-1:0] addr;
begin : index
get_index = 0;
for (memory_index=0; memory_index<memory_used; memory_index=memory_index+1) begin
if (address[memory_index] == addr) begin
get_index = 1;
disable index;
end
end
end
endfunction
`endif
task memory_write;
input [BA_BITS-1:0] bank;
input [ROW_BITS-1:0] row;
input [COL_BITS-1:0] col;
input [BL_MAX*DQ_BITS-1:0] data;
reg [`MAX_BITS-1:0] addr;
begin
`ifdef MAX_MEM
addr = {row, col}/BL_MAX;
write_to_file( memfd[bank], addr, data );
`else
// chop off the lowest address bits
addr = {bank, row, col}/BL_MAX;
if (get_index(addr)) begin
address[memory_index] = addr;
memory[memory_index] = data;
end else if (memory_used == `MEM_SIZE) begin
$display ("%m: at time %t ERROR: Memory overflow. Write to Address %h with Data %h will be lost.\nYou must increase the MEM_BITS parameter or define MAX_MEM.", $time, addr, data);
if (STOP_ON_ERROR) $stop(0);
end else begin
address[memory_used] = addr;
memory[memory_used] = data;
memory_used = memory_used + 1;
end
`endif
end
endtask
task memory_read;
input [BA_BITS-1:0] bank;
input [ROW_BITS-1:0] row;
input [COL_BITS-1:0] col;
output [BL_MAX*DQ_BITS-1:0] data;
reg [`MAX_BITS-1:0] addr;
begin
`ifdef MAX_MEM
addr = {row, col}/BL_MAX;
data = read_from_file( memfd[bank], addr );
`else
// chop off the lowest address bits
addr = {bank, row, col}/BL_MAX;
if (get_index(addr)) begin
data = memory[memory_index];
end else begin
data = {BL_MAX*DQ_BITS{1'bx}};
end
`endif
end
endtask
task set_latency;
begin
if (al == 0) begin
additive_latency = 0;
end else begin
additive_latency = cas_latency - al;
end
read_latency = cas_latency + additive_latency;
write_latency = cas_write_latency + additive_latency;
end
endtask
// this task will erase the contents of 0 or more banks
task erase_banks;
input [`BANKS-1:0] banks; //one select bit per bank
reg [BA_BITS-1:0] ba;
reg [`MAX_BITS-1:0] i;
integer bank;
begin
`ifdef MAX_MEM
for (bank = 0; bank < `BANKS; bank = bank + 1)
if (banks[bank] === 1'b1) begin
$fclose(memfd[bank]);
memfd[bank] = open_bank_file(bank);
end
`else
memory_index = 0;
i = 0;
// remove the selected banks
for (memory_index=0; memory_index<memory_used; memory_index=memory_index+1) begin
ba = (address[memory_index]>>(ROW_BITS+COL_BITS-BL_BITS));
if (!banks[ba]) begin //bank is selected to keep
address[i] = address[memory_index];
memory[i] = memory[memory_index];
i = i + 1;
end
end
// clean up the unused banks
for (memory_index=i; memory_index<memory_used; memory_index=memory_index+1) begin
address[memory_index] = 'bx;
memory[memory_index] = {8*DQ_BITS{1'bx}};
end
memory_used = i;
`endif
end
endtask
// Before this task runs, the model must be in a valid state for precharge power down and out of reset.
// After this task runs, NOP commands must be issued until TZQINIT has been met
task initialize;
input [ADDR_BITS-1:0] mode_reg0;
input [ADDR_BITS-1:0] mode_reg1;
input [ADDR_BITS-1:0] mode_reg2;
input [ADDR_BITS-1:0] mode_reg3;
begin
if (DEBUG) $display ("%m: at time %t INFO: Performing Initialization Sequence", $time);
cmd_task(1, NOP, 'bx, 'bx);
cmd_task(1, ZQ, 'bx, 'h400); //ZQCL
cmd_task(1, LOAD_MODE, 3, mode_reg3);
cmd_task(1, LOAD_MODE, 2, mode_reg2);
cmd_task(1, LOAD_MODE, 1, mode_reg1);
cmd_task(1, LOAD_MODE, 0, mode_reg0 | 'h100); // DLL Reset
cmd_task(0, NOP, 'bx, 'bx);
end
endtask
task reset_task;
integer i;
begin
// disable inputs
dq_in_valid = 0;
dqs_in_valid <= 0;
wdqs_cntr = 0;
wdq_cntr = 0;
for (i=0; i<31; i=i+1) begin
wdqs_pos_cntr[i] <= 0;
end
b2b_write <= 0;
// disable outputs
out_en = 0;
dq_out_en = 0;
rdq_cntr = 0;
dqs_out_en = 0;
rdqs_cntr = 0;
// disable ODT
odt_en = 0;
dyn_odt_en = 0;
odt_state = 0;
dyn_odt_state = 0;
// reset bank state
active_bank = 0;
auto_precharge_bank = 0;
read_precharge_bank = 0;
write_precharge_bank = 0;
// require initialization sequence
init_done = 0;
mpr_en = 0;
init_step = 0;
init_mode_reg = 0;
init_dll_reset = 0;
zq_set = 0;
// reset DLL
dll_en = 0;
dll_reset = 0;
dll_locked = 0;
// exit power down and self refresh
prev_cke = 1'bx;
in_power_down = 0;
in_self_refresh = 0;
// clear pipelines
al_pipeline = 0;
wr_pipeline = 0;
rd_pipeline = 0;
odt_pipeline = 0;
dyn_odt_pipeline = 0;
end
endtask
parameter SAME_BANK = 2'd0; // same bank, same group
parameter DIFF_BANK = 2'd1; // different bank, same group
parameter DIFF_GROUP = 2'd2; // different bank, different group
task chk_err;
input [1:0] relationship;
input [BA_BITS-1:0] bank;
input [3:0] fromcmd;
input [3:0] cmd;
reg err;
begin
// $display ("truebl4 = %d, relationship = %d, fromcmd = %h, cmd = %h", truebl4, relationship, fromcmd, cmd);
casex ({truebl4, relationship, fromcmd, cmd})
// load mode
{1'bx, DIFF_BANK , LOAD_MODE, LOAD_MODE} : begin if (ck_cntr - ck_load_mode < TMRD) $display ("%m: at time %t ERROR: tMRD violation during %s", $time, cmd_string[cmd]); end
{1'bx, DIFF_BANK , LOAD_MODE, READ } : begin if (($time - tm_load_mode < TMOD) || (ck_cntr - ck_load_mode < TMOD_TCK)) $display ("%m: at time %t ERROR: tMOD violation during %s", $time, cmd_string[cmd]); end
{1'bx, DIFF_BANK , LOAD_MODE, REFRESH } ,
{1'bx, DIFF_BANK , LOAD_MODE, PRECHARGE} ,
{1'bx, DIFF_BANK , LOAD_MODE, ACTIVATE } ,
{1'bx, DIFF_BANK , LOAD_MODE, ZQ } ,
{1'bx, DIFF_BANK , LOAD_MODE, PWR_DOWN } ,
{1'bx, DIFF_BANK , LOAD_MODE, SELF_REF } : begin if (($time - tm_load_mode < TMOD) || (ck_cntr - ck_load_mode < TMOD_TCK)) $display ("%m: at time %t ERROR: tMOD violation during %s", $time, cmd_string[cmd]); end
// refresh
{1'bx, DIFF_BANK , REFRESH , LOAD_MODE} ,
{1'bx, DIFF_BANK , REFRESH , REFRESH } ,
{1'bx, DIFF_BANK , REFRESH , PRECHARGE} ,
{1'bx, DIFF_BANK , REFRESH , ACTIVATE } ,
{1'bx, DIFF_BANK , REFRESH , ZQ } ,
{1'bx, DIFF_BANK , REFRESH , SELF_REF } : begin if ($time - tm_refresh < TRFC_MIN) $display ("%m: at time %t ERROR: tRFC violation during %s", $time, cmd_string[cmd]); end
{1'bx, DIFF_BANK , REFRESH , PWR_DOWN } : begin if (ck_cntr - ck_refresh < TREFPDEN) $display ("%m: at time %t ERROR: tREFPDEN violation during %s", $time, cmd_string[cmd]); end
// precharge
{1'bx, SAME_BANK , PRECHARGE, ACTIVATE } : begin if ($time - tm_bank_precharge[bank] < TRP) $display ("%m: at time %t ERROR: tRP violation during %s to bank %d", $time, cmd_string[cmd], bank); end
{1'bx, DIFF_BANK , PRECHARGE, LOAD_MODE} ,
{1'bx, DIFF_BANK , PRECHARGE, REFRESH } ,
{1'bx, DIFF_BANK , PRECHARGE, ZQ } ,
{1'bx, DIFF_BANK , PRECHARGE, SELF_REF } : begin if ($time - tm_precharge < TRP) $display ("%m: at time %t ERROR: tRP violation during %s", $time, cmd_string[cmd]); end
{1'bx, DIFF_BANK , PRECHARGE, PWR_DOWN } : ; //tPREPDEN = 1 tCK, can be concurrent with auto precharge
// activate
{1'bx, SAME_BANK , ACTIVATE , PRECHARGE} : begin if ($time - tm_bank_activate[bank] > TRAS_MAX) $display ("%m: at time %t ERROR: tRAS maximum violation during %s to bank %d", $time, cmd_string[cmd], bank);
if ($time - tm_bank_activate[bank] < TRAS_MIN) $display ("%m: at time %t ERROR: tRAS minimum violation during %s to bank %d", $time, cmd_string[cmd], bank);end
{1'bx, SAME_BANK , ACTIVATE , ACTIVATE } : begin if ($time - tm_bank_activate[bank] < TRC) $display ("%m: at time %t ERROR: tRC violation during %s to bank %d", $time, cmd_string[cmd], bank); end
{1'bx, SAME_BANK , ACTIVATE , WRITE } ,
{1'bx, SAME_BANK , ACTIVATE , READ } : ; // tRCD is checked outside this task
{1'b0, DIFF_BANK , ACTIVATE , ACTIVATE } : begin if (($time - tm_activate < TRRD) || (ck_cntr - ck_activate < TRRD_TCK)) $display ("%m: at time %t ERROR: tRRD violation during %s to bank %d", $time, cmd_string[cmd], bank); end
{1'b1, DIFF_BANK , ACTIVATE , ACTIVATE } : begin if (($time - tm_group_activate[bank[1]] < TRRD) || (ck_cntr - ck_group_activate[bank[1]] < TRRD_TCK)) $display ("%m: at time %t ERROR: tRRD violation during %s to bank %d", $time, cmd_string[cmd], bank); end
{1'b1, DIFF_GROUP, ACTIVATE , ACTIVATE } : begin if (($time - tm_activate < TRRD_DG) || (ck_cntr - ck_activate < TRRD_DG_TCK)) $display ("%m: at time %t ERROR: tRRD_DG violation during %s to bank %d", $time, cmd_string[cmd], bank); end
{1'bx, DIFF_BANK , ACTIVATE , REFRESH } : begin if ($time - tm_activate < TRC) $display ("%m: at time %t ERROR: tRC violation during %s", $time, cmd_string[cmd]); end
{1'bx, DIFF_BANK , ACTIVATE , PWR_DOWN } : begin if (ck_cntr - ck_activate < TACTPDEN) $display ("%m: at time %t ERROR: tACTPDEN violation during %s", $time, cmd_string[cmd]); end
// write
{1'bx, SAME_BANK , WRITE , PRECHARGE} : begin if (($time - tm_bank_write_end[bank] < TWR) || (ck_cntr - ck_bank_write[bank] <= write_latency + burst_length/2)) $display ("%m: at time %t ERROR: tWR violation during %s to bank %d", $time, cmd_string[cmd], bank); end
{1'b0, DIFF_BANK , WRITE , WRITE } : begin if (ck_cntr - ck_write < TCCD) $display ("%m: at time %t ERROR: tCCD violation during %s to bank %d", $time, cmd_string[cmd], bank); end
{1'b1, DIFF_BANK , WRITE , WRITE } : begin if (ck_cntr - ck_group_write[bank[1]] < TCCD) $display ("%m: at time %t ERROR: tCCD violation during %s to bank %d", $time, cmd_string[cmd], bank); end
{1'b0, DIFF_BANK , WRITE , READ } : begin if (ck_cntr - ck_write < write_latency + burst_length/2 + TWTR_TCK - additive_latency) $display ("%m: at time %t ERROR: tWTR violation during %s to bank %d", $time, cmd_string[cmd], bank); end
{1'b1, DIFF_BANK , WRITE , READ } : begin if (ck_cntr - ck_group_write[bank[1]] < write_latency + burst_length/2 + TWTR_TCK - additive_latency) $display ("%m: at time %t ERROR: tWTR violation during %s to bank %d", $time, cmd_string[cmd], bank); end
{1'b1, DIFF_GROUP, WRITE , WRITE } : begin if (ck_cntr - ck_write < TCCD_DG) $display ("%m: at time %t ERROR: tCCD_DG violation during %s to bank %d", $time, cmd_string[cmd], bank); end
{1'b1, DIFF_GROUP, WRITE , READ } : begin if (ck_cntr - ck_write < write_latency + burst_length/2 + TWTR_DG_TCK - additive_latency) $display ("%m: at time %t ERROR: tWTR_DG violation during %s to bank %d", $time, cmd_string[cmd], bank); end
{1'bx, DIFF_BANK , WRITE , PWR_DOWN } : begin if (($time - tm_write_end < TWR) || (ck_cntr - ck_write < write_latency + burst_length/2)) $display ("%m: at time %t ERROR: tWRPDEN violation during %s", $time, cmd_string[cmd]); end
// read
{1'bx, SAME_BANK , READ , PRECHARGE} : begin if (($time - tm_bank_read_end[bank] < TRTP) || (ck_cntr - ck_bank_read[bank] < additive_latency + TRTP_TCK)) $display ("%m: at time %t ERROR: tRTP violation during %s to bank %d", $time, cmd_string[cmd], bank); end
{1'b0, DIFF_BANK , READ , WRITE } : ; // tRTW is checked outside this task
{1'b1, DIFF_BANK , READ , WRITE } : ; // tRTW is checked outside this task
{1'b0, DIFF_BANK , READ , READ } : begin if (ck_cntr - ck_read < TCCD) $display ("%m: at time %t ERROR: tCCD violation during %s to bank %d", $time, cmd_string[cmd], bank); end
{1'b1, DIFF_BANK , READ , READ } : begin if (ck_cntr - ck_group_read[bank[1]] < TCCD) $display ("%m: at time %t ERROR: tCCD violation during %s to bank %d", $time, cmd_string[cmd], bank); end
{1'b1, DIFF_GROUP, READ , WRITE } : ; // tRTW is checked outside this task
{1'b1, DIFF_GROUP, READ , READ } : begin if (ck_cntr - ck_read < TCCD_DG) $display ("%m: at time %t ERROR: tCCD_DG violation during %s to bank %d", $time, cmd_string[cmd], bank); end
{1'bx, DIFF_BANK , READ , PWR_DOWN } : begin if (ck_cntr - ck_read < read_latency + 5) $display ("%m: at time %t ERROR: tRDPDEN violation during %s", $time, cmd_string[cmd]); end
// zq
{1'bx, DIFF_BANK , ZQ , LOAD_MODE} : ; // 1 tCK
{1'bx, DIFF_BANK , ZQ , REFRESH } ,
{1'bx, DIFF_BANK , ZQ , PRECHARGE} ,
{1'bx, DIFF_BANK , ZQ , ACTIVATE } ,
{1'bx, DIFF_BANK , ZQ , ZQ } ,
{1'bx, DIFF_BANK , ZQ , PWR_DOWN } ,
{1'bx, DIFF_BANK , ZQ , SELF_REF } : begin if (ck_cntr - ck_zqinit < TZQINIT) $display ("%m: at time %t ERROR: tZQinit violation during %s", $time, cmd_string[cmd]);
if (ck_cntr - ck_zqoper < TZQOPER) $display ("%m: at time %t ERROR: tZQoper violation during %s", $time, cmd_string[cmd]);
if (ck_cntr - ck_zqcs < TZQCS) $display ("%m: at time %t ERROR: tZQCS violation during %s", $time, cmd_string[cmd]); end
// power down
{1'bx, DIFF_BANK , PWR_DOWN , LOAD_MODE} ,
{1'bx, DIFF_BANK , PWR_DOWN , REFRESH } ,
{1'bx, DIFF_BANK , PWR_DOWN , PRECHARGE} ,
{1'bx, DIFF_BANK , PWR_DOWN , ACTIVATE } ,
{1'bx, DIFF_BANK , PWR_DOWN , WRITE } ,
{1'bx, DIFF_BANK , PWR_DOWN , ZQ } : begin if (($time - tm_power_down < TXP) || (ck_cntr - ck_power_down < TXP_TCK)) $display ("%m: at time %t ERROR: tXP violation during %s", $time, cmd_string[cmd]); end
{1'bx, DIFF_BANK , PWR_DOWN , READ } : begin if (($time - tm_power_down < TXP) || (ck_cntr - ck_power_down < TXP_TCK)) $display ("%m: at time %t ERROR: tXP violation during %s", $time, cmd_string[cmd]);
else if (($time - tm_slow_exit_pd < TXPDLL) || (ck_cntr - ck_slow_exit_pd < TXPDLL_TCK)) $display ("%m: at time %t ERROR: tXPDLL violation during %s", $time, cmd_string[cmd]); end
{1'bx, DIFF_BANK , PWR_DOWN , PWR_DOWN } ,
{1'bx, DIFF_BANK , PWR_DOWN , SELF_REF } : begin if (($time - tm_power_down < TXP) || (ck_cntr - ck_power_down < TXP_TCK)) $display ("%m: at time %t ERROR: tXP violation during %s", $time, cmd_string[cmd]);
if ((tm_power_down > tm_refresh) && ($time - tm_refresh < TRFC_MIN)) $display ("%m: at time %t ERROR: tRFC violation during %s", $time, cmd_string[cmd]);
if ((tm_refresh > tm_power_down) && (($time - tm_power_down < TXPDLL) || (ck_cntr - ck_power_down < TXPDLL_TCK))) $display ("%m: at time %t ERROR: tXPDLL violation during %s", $time, cmd_string[cmd]);
if (($time - tm_cke_cmd < TCKE) || (ck_cntr - ck_cke_cmd < TCKE_TCK)) $display ("%m: at time %t ERROR: tCKE violation on CKE", $time); end
// self refresh
{1'bx, DIFF_BANK , SELF_REF , LOAD_MODE} ,
{1'bx, DIFF_BANK , SELF_REF , REFRESH } ,
{1'bx, DIFF_BANK , SELF_REF , PRECHARGE} ,
{1'bx, DIFF_BANK , SELF_REF , ACTIVATE } ,
{1'bx, DIFF_BANK , SELF_REF , WRITE } ,
{1'bx, DIFF_BANK , SELF_REF , ZQ } : begin if (($time - tm_self_refresh < TXS) || (ck_cntr - ck_self_refresh < TXS_TCK)) $display ("%m: at time %t ERROR: tXS violation during %s", $time, cmd_string[cmd]); end
{1'bx, DIFF_BANK , SELF_REF , READ } : begin if (ck_cntr - ck_self_refresh < TXSDLL) $display ("%m: at time %t ERROR: tXSDLL violation during %s", $time, cmd_string[cmd]); end
{1'bx, DIFF_BANK , SELF_REF , PWR_DOWN } ,
{1'bx, DIFF_BANK , SELF_REF , SELF_REF } : begin if (($time - tm_self_refresh < TXS) || (ck_cntr - ck_self_refresh < TXS_TCK)) $display ("%m: at time %t ERROR: tXS violation during %s", $time, cmd_string[cmd]);
if (($time - tm_cke_cmd < TCKE) || (ck_cntr - ck_cke_cmd < TCKE_TCK)) $display ("%m: at time %t ERROR: tCKE violation on CKE", $time); end
endcase
end
endtask
task cmd_task;
input cke;
input [2:0] cmd;
input [BA_BITS-1:0] bank;
input [ADDR_BITS-1:0] addr;
reg [`BANKS:0] i;
integer j;
reg [`BANKS:0] tfaw_cntr;
reg [COL_BITS-1:0] col;
reg group;
begin
// tRFC max check
if (!er_trfc_max && !in_self_refresh) begin
if ($time - tm_refresh > TRFC_MAX && check_strict_timing) begin
$display ("%m: at time %t ERROR: tRFC maximum violation during %s", $time, cmd_string[cmd]);
er_trfc_max = 1;
end
end
if (cke) begin
if ((cmd < NOP) && (cmd != PRECHARGE)) begin
if (($time - tm_txpr < TXPR) || (ck_cntr - ck_txpr < TXPR_TCK))
$display ("%m: at time %t ERROR: tXPR violation during %s", $time, cmd_string[cmd]);
for (j=0; j<=SELF_REF; j=j+1) begin
chk_err(SAME_BANK , bank, j, cmd);
chk_err(DIFF_BANK , bank, j, cmd);
chk_err(DIFF_GROUP, bank, j, cmd);
end
end
case (cmd)
LOAD_MODE : begin
if (|odt_pipeline)
$display ("%m: at time %t ERROR: ODTL violation during %s", $time, cmd_string[cmd]);
if (odt_state)
$display ("%m: at time %t ERROR: ODT must be off prior to %s", $time, cmd_string[cmd]);
if (|active_bank) begin
$display ("%m: at time %t ERROR: %s Failure. All banks must be Precharged.", $time, cmd_string[cmd]);
if (STOP_ON_ERROR) $stop(0);
end else begin
if (DEBUG) $display ("%m: at time %t INFO: %s %d", $time, cmd_string[cmd], bank);
if (bank>>2) begin
$display ("%m: at time %t ERROR: %s %d Illegal value. Reserved bank bits must be programmed to zero", $time, cmd_string[cmd], bank);
end
case (bank)
0 : begin
// Burst Length
if (addr[1:0] == 2'b00) begin
burst_length = 8;
blotf = 0;
truebl4 = 0;
if (DEBUG) $display ("%m: at time %t INFO: %s %d Burst Length = %d", $time, cmd_string[cmd], bank, burst_length);
end else if (addr[1:0] == 2'b01) begin
burst_length = 8;
blotf = 1;
truebl4 = 0;
if (DEBUG) $display ("%m: at time %t INFO: %s %d Burst Length = Select via A12", $time, cmd_string[cmd], bank);
end else if (addr[1:0] == 2'b10) begin
burst_length = 4;
blotf = 0;
truebl4 = 0;
if (DEBUG) $display ("%m: at time %t INFO: %s %d Burst Length = Fixed %d (chop)", $time, cmd_string[cmd], bank, burst_length);
end else if (feature_truebl4 && (addr[1:0] == 2'b11)) begin
burst_length = 4;
blotf = 0;
truebl4 = 1;
if (DEBUG) $display ("%m: at time %t INFO: %s %d Burst Length = True %d", $time, cmd_string[cmd], bank, burst_length);
end else begin
$display ("%m: at time %t ERROR: %s %d Illegal Burst Length = %d", $time, cmd_string[cmd], bank, addr[1:0]);
end
// Burst Order
burst_order = addr[3];
if (!burst_order) begin
if (DEBUG) $display ("%m: at time %t INFO: %s %d Burst Order = Sequential", $time, cmd_string[cmd], bank);
end else if (burst_order) begin
if (DEBUG) $display ("%m: at time %t INFO: %s %d Burst Order = Interleaved", $time, cmd_string[cmd], bank);
end else begin
$display ("%m: at time %t ERROR: %s %d Illegal Burst Order = %d", $time, cmd_string[cmd], bank, burst_order);
end
// CAS Latency
cas_latency = {addr[2],addr[6:4]} + 4;
set_latency;
if ((cas_latency >= CL_MIN) && (cas_latency <= CL_MAX)) begin
if (DEBUG) $display ("%m: at time %t INFO: %s %d CAS Latency = %d", $time, cmd_string[cmd], bank, cas_latency);
end else begin
$display ("%m: at time %t ERROR: %s %d Illegal CAS Latency = %d", $time, cmd_string[cmd], bank, cas_latency);
end
// Reserved
if (addr[7] !== 0 && check_strict_mrbits) begin
$display ("%m: at time %t ERROR: %s %d Illegal value. Reserved address bits must be programmed to zero", $time, cmd_string[cmd], bank);
end
// DLL Reset
dll_reset = addr[8];
if (!dll_reset) begin
if (DEBUG) $display ("%m: at time %t INFO: %s %d DLL Reset = Normal", $time, cmd_string[cmd], bank);
end else if (dll_reset) begin
if (DEBUG) $display ("%m: at time %t INFO: %s %d DLL Reset = Reset DLL", $time, cmd_string[cmd], bank);
dll_locked = 0;
init_dll_reset = 1;
ck_dll_reset <= ck_cntr;
end else begin
$display ("%m: at time %t ERROR: %s %d Illegal DLL Reset = %d", $time, cmd_string[cmd], bank, dll_reset);
end
// Write Recovery
if (addr[11:9] == 0) begin
write_recovery = 16;
end else if (addr[11:9] < 4) begin
write_recovery = addr[11:9] + 4;
end else begin
write_recovery = 2*addr[11:9];
end
if ((write_recovery >= WR_MIN) && (write_recovery <= WR_MAX)) begin
if (DEBUG) $display ("%m: at time %t INFO: %s %d Write Recovery = %d", $time, cmd_string[cmd], bank, write_recovery);
end else begin
$display ("%m: at time %t ERROR: %s %d Illegal Write Recovery = %d", $time, cmd_string[cmd], bank, write_recovery);
end
// Power Down Mode
low_power = !addr[12];
if (!low_power) begin
if (DEBUG) $display ("%m: at time %t INFO: %s %d Power Down Mode = DLL on", $time, cmd_string[cmd], bank);
end else if (low_power) begin
if (DEBUG) $display ("%m: at time %t INFO: %s %d Power Down Mode = DLL off", $time, cmd_string[cmd], bank);
end else begin
$display ("%m: at time %t ERROR: %s %d Illegal Power Down Mode = %d", $time, cmd_string[cmd], bank, low_power);
end
// Reserved
if (ADDR_BITS>13 && addr[13] !== 0 && check_strict_mrbits) begin
$display ("%m: at time %t ERROR: %s %d Illegal value. Reserved address bits must be programmed to zero", $time, cmd_string[cmd], bank);
end
end
1 : begin
// DLL Enable
dll_en = !addr[0];
if (!dll_en) begin
if (DEBUG) $display ("%m: at time %t INFO: %s %d DLL Enable = Disabled", $time, cmd_string[cmd], bank);
if (check_strict_mrbits) $display ("%m: at time %t WARNING: %s %d DLL off mode is not modeled", $time, cmd_string[cmd], bank);
end else if (dll_en) begin
if (DEBUG) $display ("%m: at time %t INFO: %s %d DLL Enable = Enabled", $time, cmd_string[cmd], bank);
end else begin
$display ("%m: at time %t ERROR: %s %d Illegal DLL Enable = %d", $time, cmd_string[cmd], bank, dll_en);
end
// Output Drive Strength
if ({addr[5], addr[1]} == 2'b00) begin
if (DEBUG) $display ("%m: at time %t INFO: %s %d Output Drive Strength = %d Ohm", $time, cmd_string[cmd], bank, RZQ/6);
end else if ({addr[5], addr[1]} == 2'b01) begin
if (DEBUG) $display ("%m: at time %t INFO: %s %d Output Drive Strength = %d Ohm", $time, cmd_string[cmd], bank, RZQ/7);
end else if ({addr[5], addr[1]} == 2'b11) begin
if (DEBUG) $display ("%m: at time %t INFO: %s %d Output Drive Strength = %d Ohm", $time, cmd_string[cmd], bank, RZQ/5);
end else begin
$display ("%m: at time %t ERROR: %s %d Illegal Output Drive Strength = %d", $time, cmd_string[cmd], bank, {addr[5], addr[1]});
end
// ODT Rtt (Rtt_NOM)
odt_rtt_nom = {addr[9], addr[6], addr[2]};
if (odt_rtt_nom == 3'b000) begin
if (DEBUG) $display ("%m: at time %t INFO: %s %d ODT Rtt = Disabled", $time, cmd_string[cmd], bank);
odt_en = 0;
end else if ((odt_rtt_nom < 4) || ((!addr[7] || (addr[7] && addr[12])) && (odt_rtt_nom < 6))) begin
if (DEBUG) $display ("%m: at time %t INFO: %s %d ODT Rtt = %d Ohm", $time, cmd_string[cmd], bank, get_rtt_nom(odt_rtt_nom));
odt_en = 1;
end else begin
$display ("%m: at time %t ERROR: %s %d Illegal ODT Rtt = %d", $time, cmd_string[cmd], bank, odt_rtt_nom);
odt_en = 0;
end
// Report the additive latency value
al = addr[4:3];
set_latency;
if (al == 0) begin
if (DEBUG) $display ("%m: at time %t INFO: %s %d Additive Latency = %d", $time, cmd_string[cmd], bank, al);
end else if ((al >= AL_MIN) && (al <= AL_MAX)) begin
if (DEBUG) $display ("%m: at time %t INFO: %s %d Additive Latency = CL - %d", $time, cmd_string[cmd], bank, al);
end else begin
$display ("%m: at time %t ERROR: %s %d Illegal Additive Latency = %d", $time, cmd_string[cmd], bank, al);
end
// Write Levelization
write_levelization = addr[7];
if (!write_levelization) begin
if (DEBUG) $display ("%m: at time %t INFO: %s %d Write Levelization = Disabled", $time, cmd_string[cmd], bank);
end else if (write_levelization) begin
if (DEBUG) $display ("%m: at time %t INFO: %s %d Write Levelization = Enabled", $time, cmd_string[cmd], bank);
end else begin
$display ("%m: at time %t ERROR: %s %d Illegal Write Levelization = %d", $time, cmd_string[cmd], bank, write_levelization);
end
// Reserved
if (addr[8] !== 0 && check_strict_mrbits) begin
$display ("%m: at time %t ERROR: %s %d Illegal value. Reserved address bits must be programmed to zero", $time, cmd_string[cmd], bank);
end
// Reserved
if (addr[10] !== 0 && check_strict_mrbits) begin
$display ("%m: at time %t ERROR: %s %d Illegal value. Reserved address bits must be programmed to zero", $time, cmd_string[cmd], bank);
end
// TDQS Enable
tdqs_en = addr[11];
if (!tdqs_en) begin
if (DEBUG) $display ("%m: at time %t INFO: %s %d TDQS Enable = Disabled", $time, cmd_string[cmd], bank);
end else if (tdqs_en) begin
if (8 == DQ_BITS) begin
if (DEBUG) $display ("%m: at time %t INFO: %s %d TDQS Enable = Enabled", $time, cmd_string[cmd], bank);
end
else begin
$display ("%m: at time %t WARNING: %s %d Illegal TDQS Enable. TDQS only exists on a x8 part", $time, cmd_string[cmd], bank);
tdqs_en = 0;
end
end else begin
$display ("%m: at time %t ERROR: %s %d Illegal TDQS Enable = %d", $time, cmd_string[cmd], bank, tdqs_en);
end
// Output Enable
out_en = !addr[12];
if (!out_en) begin
if (DEBUG) $display ("%m: at time %t INFO: %s %d Qoff = Disabled", $time, cmd_string[cmd], bank);
end else if (out_en) begin
if (DEBUG) $display ("%m: at time %t INFO: %s %d Qoff = Enabled", $time, cmd_string[cmd], bank);
end else begin
$display ("%m: at time %t ERROR: %s %d Illegal Qoff = %d", $time, cmd_string[cmd], bank, out_en);
end
// Reserved
if (ADDR_BITS>13 && addr[13] !== 0 && check_strict_mrbits) begin
$display ("%m: at time %t ERROR: %s %d Illegal value. Reserved address bits must be programmed to zero", $time, cmd_string[cmd], bank);
end
end
2 : begin
if (feature_pasr) begin
// Partial Array Self Refresh
pasr = addr[2:0];
case (pasr)
3'b000 : if (DEBUG) $display ("%m: at time %t INFO: %s %d Partial Array Self Refresh = Bank 0-7", $time, cmd_string[cmd], bank);
3'b001 : if (DEBUG) $display ("%m: at time %t INFO: %s %d Partial Array Self Refresh = Bank 0-3", $time, cmd_string[cmd], bank);
3'b010 : if (DEBUG) $display ("%m: at time %t INFO: %s %d Partial Array Self Refresh = Bank 0-1", $time, cmd_string[cmd], bank);
3'b011 : if (DEBUG) $display ("%m: at time %t INFO: %s %d Partial Array Self Refresh = Bank 0", $time, cmd_string[cmd], bank);
3'b100 : if (DEBUG) $display ("%m: at time %t INFO: %s %d Partial Array Self Refresh = Bank 2-7", $time, cmd_string[cmd], bank);
3'b101 : if (DEBUG) $display ("%m: at time %t INFO: %s %d Partial Array Self Refresh = Bank 4-7", $time, cmd_string[cmd], bank);
3'b110 : if (DEBUG) $display ("%m: at time %t INFO: %s %d Partial Array Self Refresh = Bank 6-7", $time, cmd_string[cmd], bank);
3'b111 : if (DEBUG) $display ("%m: at time %t INFO: %s %d Partial Array Self Refresh = Bank 7", $time, cmd_string[cmd], bank);
default : $display ("%m: at time %t ERROR: %s %d Illegal Partial Array Self Refresh = %d", $time, cmd_string[cmd], bank, pasr);
endcase
end
else
if (addr[2:0] !== 0 && check_strict_mrbits) begin
$display ("%m: at time %t ERROR: %s %d Illegal value. Reserved address bits must be programmed to zero", $time, cmd_string[cmd], bank);
end
// CAS Write Latency
cas_write_latency = addr[5:3]+5;
set_latency;
if ((cas_write_latency >= CWL_MIN) && (cas_write_latency <= CWL_MAX)) begin
if (DEBUG) $display ("%m: at time %t INFO: %s %d CAS Write Latency = %d", $time, cmd_string[cmd], bank, cas_write_latency);
end else begin
$display ("%m: at time %t ERROR: %s %d Illegal CAS Write Latency = %d", $time, cmd_string[cmd], bank, cas_write_latency);
end
// Auto Self Refresh Method
asr = addr[6];
if (!asr) begin
if (DEBUG) $display ("%m: at time %t INFO: %s %d Auto Self Refresh = Disabled", $time, cmd_string[cmd], bank);
end else if (asr) begin
if (DEBUG) $display ("%m: at time %t INFO: %s %d Auto Self Refresh = Enabled", $time, cmd_string[cmd], bank);
if (check_strict_mrbits) $display ("%m: at time %t WARNING: %s %d Auto Self Refresh is not modeled", $time, cmd_string[cmd], bank);
end else begin
$display ("%m: at time %t ERROR: %s %d Illegal Auto Self Refresh = %d", $time, cmd_string[cmd], bank, asr);
end
// Self Refresh Temperature
srt = addr[7];
if (!srt) begin
if (DEBUG) $display ("%m: at time %t INFO: %s %d Self Refresh Temperature = Normal", $time, cmd_string[cmd], bank);
end else if (srt) begin
if (DEBUG) $display ("%m: at time %t INFO: %s %d Self Refresh Temperature = Extended", $time, cmd_string[cmd], bank);
if (check_strict_mrbits) $display ("%m: at time %t WARNING: %s %d Self Refresh Temperature is not modeled", $time, cmd_string[cmd], bank);
end else begin
$display ("%m: at time %t ERROR: %s %d Illegal Self Refresh Temperature = %d", $time, cmd_string[cmd], bank, srt);
end
if (asr && srt)
$display ("%m: at time %t ERROR: %s %d SRT must be set to 0 when ASR is enabled.", $time, cmd_string[cmd], bank);
// Reserved
if (addr[8] !== 0 && check_strict_mrbits) begin
$display ("%m: at time %t ERROR: %s %d Illegal value. Reserved address bits must be programmed to zero", $time, cmd_string[cmd], bank);
end
// Dynamic ODT (Rtt_WR)
odt_rtt_wr = addr[10:9];
if (odt_rtt_wr == 2'b00) begin
if (DEBUG) $display ("%m: at time %t INFO: %s %d Dynamic ODT = Disabled", $time, cmd_string[cmd], bank);
dyn_odt_en = 0;
end else if ((odt_rtt_wr > 0) && (odt_rtt_wr < 3)) begin
if (DEBUG) $display ("%m: at time %t INFO: %s %d Dynamic ODT Rtt = %d Ohm", $time, cmd_string[cmd], bank, get_rtt_wr(odt_rtt_wr));
dyn_odt_en = 1;
end else begin
$display ("%m: at time %t ERROR: %s %d Illegal Dynamic ODT = %d", $time, cmd_string[cmd], bank, odt_rtt_wr);
dyn_odt_en = 0;
end
// Reserved
if (ADDR_BITS>13 && addr[13:11] !== 0 && check_strict_mrbits) begin
$display ("%m: at time %t ERROR: %s %d Illegal value. Reserved address bits must be programmed to zero", $time, cmd_string[cmd], bank);
end
end
3 : begin
mpr_select = addr[1:0];
// MultiPurpose Register Select
if (mpr_select == 2'b00) begin
if (DEBUG) $display ("%m: at time %t INFO: %s %d MultiPurpose Register Select = Pre-defined pattern", $time, cmd_string[cmd], bank);
end else begin
if (check_strict_mrbits) $display ("%m: at time %t ERROR: %s %d Illegal MultiPurpose Register Select = %d", $time, cmd_string[cmd], bank, mpr_select);
end
// MultiPurpose Register Enable
mpr_en = addr[2];
if (!mpr_en) begin
if (DEBUG) $display ("%m: at time %t INFO: %s %d MultiPurpose Register Enable = Disabled", $time, cmd_string[cmd], bank);
end else if (mpr_en) begin
if (DEBUG) $display ("%m: at time %t INFO: %s %d MultiPurpose Register Enable = Enabled", $time, cmd_string[cmd], bank);
end else begin
$display ("%m: at time %t ERROR: %s %d Illegal MultiPurpose Register Enable = %d", $time, cmd_string[cmd], bank, mpr_en);
end
// Reserved
if (ADDR_BITS>13 && addr[13:3] !== 0 && check_strict_mrbits) begin
$display ("%m: at time %t ERROR: %s %d Illegal value. Reserved address bits must be programmed to zero", $time, cmd_string[cmd], bank);
end
end
endcase
if (dyn_odt_en && write_levelization)
$display ("%m: at time %t ERROR: Dynamic ODT is not available during Write Leveling mode.", $time);
init_mode_reg[bank] = 1;
mode_reg[bank] = addr;
tm_load_mode <= $time;
ck_load_mode <= ck_cntr;
end
end
REFRESH : begin
if (mpr_en) begin
$display ("%m: at time %t ERROR: %s Failure. Multipurpose Register must be disabled.", $time, cmd_string[cmd]);
if (STOP_ON_ERROR) $stop(0);
end else if (|active_bank) begin
$display ("%m: at time %t ERROR: %s Failure. All banks must be Precharged.", $time, cmd_string[cmd]);
if (STOP_ON_ERROR) $stop(0);
end else begin
if (DEBUG) $display ("%m: at time %t INFO: %s", $time, cmd_string[cmd]);
er_trfc_max = 0;
ref_cntr = ref_cntr + 1;
tm_refresh <= $time;
ck_refresh <= ck_cntr;
end
end
PRECHARGE : begin
if (addr[AP]) begin
if (DEBUG) $display ("%m: at time %t INFO: %s All", $time, cmd_string[cmd]);
end
// PRECHARGE command will be treated as a NOP if there is no open row in that bank (idle state),
// or if the previously open row is already in the process of precharging
if (|active_bank) begin
if (($time - tm_txpr < TXPR) || (ck_cntr - ck_txpr < TXPR_TCK))
$display ("%m: at time %t ERROR: tXPR violation during %s", $time, cmd_string[cmd]);
if (mpr_en) begin
$display ("%m: at time %t ERROR: %s Failure. Multipurpose Register must be disabled.", $time, cmd_string[cmd]);
if (STOP_ON_ERROR) $stop(0);
end else begin
for (i=0; i<`BANKS; i=i+1) begin
if (active_bank[i]) begin
if (addr[AP] || (i == bank)) begin
for (j=0; j<=SELF_REF; j=j+1) begin
chk_err(SAME_BANK, i, j, cmd);
chk_err(DIFF_BANK, i, j, cmd);
end
if (auto_precharge_bank[i]) begin
$display ("%m: at time %t ERROR: %s Failure. Auto Precharge is scheduled to bank %d.", $time, cmd_string[cmd], i);
if (STOP_ON_ERROR) $stop(0);
end else begin
if (DEBUG) $display ("%m: at time %t INFO: %s bank %d", $time, cmd_string[cmd], i);
active_bank[i] = 1'b0;
tm_bank_precharge[i] <= $time;
tm_precharge <= $time;
ck_precharge <= ck_cntr;
end
end
end
end
end
end
end
ACTIVATE : begin
tfaw_cntr = 0;
for (i=0; i<`BANKS; i=i+1) begin
if ($time - tm_bank_activate[i] < TFAW) begin
tfaw_cntr = tfaw_cntr + 1;
end
end
if (tfaw_cntr > 3) begin
$display ("%m: at time %t ERROR: tFAW violation during %s to bank %d", $time, cmd_string[cmd], bank);
end
if (mpr_en) begin
$display ("%m: at time %t ERROR: %s Failure. Multipurpose Register must be disabled.", $time, cmd_string[cmd]);
if (STOP_ON_ERROR) $stop(0);
end else if (!init_done) begin
$display ("%m: at time %t ERROR: %s Failure. Initialization sequence is not complete.", $time, cmd_string[cmd]);
if (STOP_ON_ERROR) $stop(0);
end else if (active_bank[bank]) begin
$display ("%m: at time %t ERROR: %s Failure. Bank %d must be Precharged.", $time, cmd_string[cmd], bank);
if (STOP_ON_ERROR) $stop(0);
end else begin
if (addr >= 1<<ROW_BITS) begin
$display ("%m: at time %t WARNING: row = %h does not exist. Maximum row = %h", $time, addr, (1<<ROW_BITS)-1);
end
if (DEBUG) $display ("%m: at time %t INFO: %s bank %d row %h", $time, cmd_string[cmd], bank, addr);
active_bank[bank] = 1'b1;
active_row[bank] = addr;
tm_group_activate[bank[1]] <= $time;
tm_activate <= $time;
tm_bank_activate[bank] <= $time;
ck_group_activate[bank[1]] <= ck_cntr;
ck_activate <= ck_cntr;
end
end
WRITE : begin
if ((!rd_bc && blotf) || (burst_length == 4)) begin // BL=4
if (truebl4) begin
if (ck_cntr - ck_group_read[bank[1]] < read_latency + TCCD/2 + 2 - write_latency)
$display ("%m: at time %t ERROR: tRTW violation during %s to bank %d", $time, cmd_string[cmd], bank);
if (ck_cntr - ck_read < read_latency + TCCD_DG/2 + 2 - write_latency)
$display ("%m: at time %t ERROR: tRTW_DG violation during %s to bank %d", $time, cmd_string[cmd], bank);
end else begin
if (ck_cntr - ck_read < read_latency + TCCD/2 + 2 - write_latency)
$display ("%m: at time %t ERROR: tRTW violation during %s to bank %d", $time, cmd_string[cmd], bank);
end
end else begin // BL=8
if (ck_cntr - ck_read < read_latency + TCCD + 2 - write_latency)
$display ("%m: at time %t ERROR: tRTW violation during %s to bank %d", $time, cmd_string[cmd], bank);
end
if (mpr_en) begin
$display ("%m: at time %t ERROR: %s Failure. Multipurpose Register must be disabled.", $time, cmd_string[cmd]);
if (STOP_ON_ERROR) $stop(0);
end else if (!init_done) begin
$display ("%m: at time %t ERROR: %s Failure. Initialization sequence is not complete.", $time, cmd_string[cmd]);
if (STOP_ON_ERROR) $stop(0);
end else if (!active_bank[bank]) begin
if (check_strict_timing) $display ("%m: at time %t ERROR: %s Failure. Bank %d must be Activated.", $time, cmd_string[cmd], bank);
if (STOP_ON_ERROR) $stop(0);
end else if (auto_precharge_bank[bank]) begin
$display ("%m: at time %t ERROR: %s Failure. Auto Precharge is scheduled to bank %d.", $time, cmd_string[cmd], bank);
if (STOP_ON_ERROR) $stop(0);
end else if (ck_cntr - ck_write < burst_length/2) begin
$display ("%m: at time %t ERROR: %s Failure. Illegal burst interruption.", $time, cmd_string[cmd]);
if (STOP_ON_ERROR) $stop(0);
end else begin
if (addr[AP]) begin
auto_precharge_bank[bank] = 1'b1;
write_precharge_bank[bank] = 1'b1;
end
col = {addr[BC-1:AP+1], addr[AP-1:0]}; // assume BC > AP
if (col >= 1<<COL_BITS) begin
$display ("%m: at time %t WARNING: col = %h does not exist. Maximum col = %h", $time, col, (1<<COL_BITS)-1);
end
if ((!addr[BC] && blotf) || (burst_length == 4)) begin // BL=4
col = col & -4;
end else begin // BL=8
col = col & -8;
end
if (DEBUG) $display ("%m: at time %t INFO: %s bank %d col %h, auto precharge %d", $time, cmd_string[cmd], bank, col, addr[AP]);
wr_pipeline[2*write_latency + 1] = 1;
ba_pipeline[2*write_latency + 1] = bank;
row_pipeline[2*write_latency + 1] = active_row[bank];
col_pipeline[2*write_latency + 1] = col;
if ((!addr[BC] && blotf) || (burst_length == 4)) begin // BL=4
bl_pipeline[2*write_latency + 1] = 4;
if (mpr_en && col%4) begin
$display ("%m: at time %t WARNING: col[1:0] must be set to 2'b00 during a BL4 Multipurpose Register read", $time);
end
end else begin // BL=8
bl_pipeline[2*write_latency + 1] = 8;
if (odt_in) begin
ck_odth8 <= ck_cntr;
end
end
for (j=0; j<(burst_length + 4); j=j+1) begin
dyn_odt_pipeline[2*(write_latency - 2) + j] = 1'b1; // ODTLcnw = WL - 2, ODTLcwn = BL/2 + 2
end
ck_bank_write[bank] <= ck_cntr;
ck_group_write[bank[1]] <= ck_cntr;
ck_write <= ck_cntr;
end
end
READ : begin
if (!dll_locked)
$display ("%m: at time %t WARNING: tDLLK violation during %s.", $time, cmd_string[cmd]);
if (mpr_en && (addr[1:0] != 2'b00)) begin
$display ("%m: at time %t ERROR: %s Failure. addr[1:0] must be zero during Multipurpose Register Read.", $time, cmd_string[cmd]);
if (STOP_ON_ERROR) $stop(0);
end else if (!init_done) begin
$display ("%m: at time %t ERROR: %s Failure. Initialization sequence is not complete.", $time, cmd_string[cmd]);
if (STOP_ON_ERROR) $stop(0);
end else if (!active_bank[bank] && !mpr_en) begin
if (check_strict_timing) $display ("%m: at time %t ERROR: %s Failure. Bank %d must be Activated.", $time, cmd_string[cmd], bank);
if (STOP_ON_ERROR) $stop(0);
end else if (auto_precharge_bank[bank]) begin
$display ("%m: at time %t ERROR: %s Failure. Auto Precharge is scheduled to bank %d.", $time, cmd_string[cmd], bank);
if (STOP_ON_ERROR) $stop(0);
end else if (ck_cntr - ck_read < burst_length/2) begin
$display ("%m: at time %t ERROR: %s Failure. Illegal burst interruption.", $time, cmd_string[cmd]);
if (STOP_ON_ERROR) $stop(0);
end else begin
if (addr[AP] && !mpr_en) begin
auto_precharge_bank[bank] = 1'b1;
read_precharge_bank[bank] = 1'b1;
end
col = {addr[BC-1:AP+1], addr[AP-1:0]}; // assume BC > AP
if (col >= 1<<COL_BITS) begin
$display ("%m: at time %t WARNING: col = %h does not exist. Maximum col = %h", $time, col, (1<<COL_BITS)-1);
end
if (DEBUG) $display ("%m: at time %t INFO: %s bank %d col %h, auto precharge %d", $time, cmd_string[cmd], bank, col, addr[AP]);
rd_pipeline[2*read_latency - 1] = 1;
ba_pipeline[2*read_latency - 1] = bank;
row_pipeline[2*read_latency - 1] = active_row[bank];
col_pipeline[2*read_latency - 1] = col;
if ((!addr[BC] && blotf) || (burst_length == 4)) begin // BL=4
bl_pipeline[2*read_latency - 1] = 4;
if (mpr_en && col%4) begin
$display ("%m: at time %t WARNING: col[1:0] must be set to 2'b00 during a BL4 Multipurpose Register read", $time);
end
end else begin // BL=8
bl_pipeline[2*read_latency - 1] = 8;
if (mpr_en && col%8) begin
$display ("%m: at time %t WARNING: col[2:0] must be set to 3'b000 during a BL8 Multipurpose Register read", $time);
end
end
rd_bc = addr[BC];
ck_bank_read[bank] <= ck_cntr;
ck_group_read[bank[1]] <= ck_cntr;
ck_read <= ck_cntr;
end
end
ZQ : begin
if (mpr_en) begin
$display ("%m: at time %t ERROR: %s Failure. Multipurpose Register must be disabled.", $time, cmd_string[cmd]);
if (STOP_ON_ERROR) $stop(0);
end else if (|active_bank) begin
$display ("%m: at time %t ERROR: %s Failure. All banks must be Precharged.", $time, cmd_string[cmd]);
if (STOP_ON_ERROR) $stop(0);
end else begin
if (DEBUG) $display ("%m: at time %t INFO: %s long = %d", $time, cmd_string[cmd], addr[AP]);
if (addr[AP]) begin
zq_set = 1;
if (init_done) begin
ck_zqoper <= ck_cntr;
end else begin
ck_zqinit <= ck_cntr;
end
end else begin
ck_zqcs <= ck_cntr;
end
end
end
NOP: begin
if (in_power_down) begin
if (($time - tm_freq_change < TCKSRX) || (ck_cntr - ck_freq_change < TCKSRX_TCK))
$display ("%m: at time %t ERROR: tCKSRX violation during Power Down Exit", $time);
if ($time - tm_cke_cmd > TPD_MAX)
$display ("%m: at time %t ERROR: tPD maximum violation during Power Down Exit", $time);
if (DEBUG) $display ("%m: at time %t INFO: Power Down Exit", $time);
in_power_down = 0;
if ((active_bank == 0) && low_power) begin // precharge power down with dll off
if (ck_cntr - ck_odt < write_latency - 1)
$display ("%m: at time %t WARNING: tANPD violation during Power Down Exit. Synchronous or asynchronous change in termination resistance is possible.", $time);
tm_slow_exit_pd <= $time;
ck_slow_exit_pd <= ck_cntr;
end
tm_power_down <= $time;
ck_power_down <= ck_cntr;
end
if (in_self_refresh) begin
if (($time - tm_freq_change < TCKSRX) || (ck_cntr - ck_freq_change < TCKSRX_TCK))
$display ("%m: at time %t ERROR: tCKSRX violation during Self Refresh Exit", $time);
if (ck_cntr - ck_cke_cmd < TCKESR_TCK)
$display ("%m: at time %t ERROR: tCKESR violation during Self Refresh Exit", $time);
if ($time - tm_cke < TISXR)
$display ("%m: at time %t ERROR: tISXR violation during Self Refresh Exit", $time);
if (DEBUG) $display ("%m: at time %t INFO: Self Refresh Exit", $time);
in_self_refresh = 0;
ck_dll_reset <= ck_cntr;
ck_self_refresh <= ck_cntr;
tm_self_refresh <= $time;
tm_refresh <= $time;
end
end
endcase
if ((prev_cke !== 1) && (cmd !== NOP)) begin
$display ("%m: at time %t ERROR: NOP or Deselect is required when CKE goes active.", $time);
end
if (!init_done) begin
case (init_step)
0 : begin
if ($time - tm_rst_n < 500000000 && check_strict_timing)
$display ("%m at time %t WARNING: 500 us is required after RST_N goes inactive before CKE goes active.", $time);
tm_txpr <= $time;
ck_txpr <= ck_cntr;
init_step = init_step + 1;
end
1 : if (dll_en) init_step = init_step + 1;
2 : begin
if (&init_mode_reg && init_dll_reset && zq_set) begin
if (DEBUG) $display ("%m: at time %t INFO: Initialization Sequence is complete", $time);
init_done = 1;
end
end
endcase
end
end else if (prev_cke) begin
if ((!init_done) && (init_step > 1)) begin
$display ("%m: at time %t ERROR: CKE must remain active until the initialization sequence is complete.", $time);
if (STOP_ON_ERROR) $stop(0);
end
case (cmd)
REFRESH : begin
if ($time - tm_txpr < TXPR)
$display ("%m: at time %t ERROR: tXPR violation during %s", $time, cmd_string[SELF_REF]);
for (j=0; j<=SELF_REF; j=j+1) begin
chk_err(DIFF_BANK, bank, j, SELF_REF);
end
if (mpr_en) begin
$display ("%m: at time %t ERROR: Self Refresh Failure. Multipurpose Register must be disabled.", $time);
if (STOP_ON_ERROR) $stop(0);
end else if (|active_bank) begin
$display ("%m: at time %t ERROR: Self Refresh Failure. All banks must be Precharged.", $time);
if (STOP_ON_ERROR) $stop(0);
end else if (odt_state) begin
$display ("%m: at time %t ERROR: Self Refresh Failure. ODT must be off prior to entering Self Refresh", $time);
if (STOP_ON_ERROR) $stop(0);
end else if (!init_done) begin
$display ("%m: at time %t ERROR: Self Refresh Failure. Initialization sequence is not complete.", $time);
if (STOP_ON_ERROR) $stop(0);
end else begin
if (DEBUG) $display ("%m: at time %t INFO: Self Refresh Enter", $time);
if (feature_pasr)
// Partial Array Self Refresh
case (pasr)
3'b000 : ;//keep Bank 0-7
3'b001 : begin if (DEBUG) $display("%m: at time %t INFO: Banks 4-7 will be lost due to Partial Array Self Refresh", $time); erase_banks(8'hF0); end
3'b010 : begin if (DEBUG) $display("%m: at time %t INFO: Banks 2-7 will be lost due to Partial Array Self Refresh", $time); erase_banks(8'hFC); end
3'b011 : begin if (DEBUG) $display("%m: at time %t INFO: Banks 1-7 will be lost due to Partial Array Self Refresh", $time); erase_banks(8'hFE); end
3'b100 : begin if (DEBUG) $display("%m: at time %t INFO: Banks 0-1 will be lost due to Partial Array Self Refresh", $time); erase_banks(8'h03); end
3'b101 : begin if (DEBUG) $display("%m: at time %t INFO: Banks 0-3 will be lost due to Partial Array Self Refresh", $time); erase_banks(8'h0F); end
3'b110 : begin if (DEBUG) $display("%m: at time %t INFO: Banks 0-5 will be lost due to Partial Array Self Refresh", $time); erase_banks(8'h3F); end
3'b111 : begin if (DEBUG) $display("%m: at time %t INFO: Banks 0-6 will be lost due to Partial Array Self Refresh", $time); erase_banks(8'h7F); end
endcase
in_self_refresh = 1;
dll_locked = 0;
end
end
NOP : begin
// entering precharge power down with dll off and tANPD has not been satisfied
if (low_power && (active_bank == 0) && |odt_pipeline)
$display ("%m: at time %t WARNING: tANPD violation during %s. Synchronous or asynchronous change in termination resistance is possible.", $time, cmd_string[PWR_DOWN]);
if ($time - tm_txpr < TXPR)
$display ("%m: at time %t ERROR: tXPR violation during %s", $time, cmd_string[PWR_DOWN]);
for (j=0; j<=SELF_REF; j=j+1) begin
chk_err(DIFF_BANK, bank, j, PWR_DOWN);
end
if (mpr_en) begin
$display ("%m: at time %t ERROR: Power Down Failure. Multipurpose Register must be disabled.", $time);
if (STOP_ON_ERROR) $stop(0);
end else if (!init_done) begin
$display ("%m: at time %t ERROR: Power Down Failure. Initialization sequence is not complete.", $time);
if (STOP_ON_ERROR) $stop(0);
end else begin
if (DEBUG) begin
if (|active_bank) begin
$display ("%m: at time %t INFO: Active Power Down Enter", $time);
end else begin
$display ("%m: at time %t INFO: Precharge Power Down Enter", $time);
end
end
in_power_down = 1;
end
end
default : begin
$display ("%m: at time %t ERROR: NOP, Deselect, or Refresh is required when CKE goes inactive.", $time);
end
endcase
end else if (in_self_refresh || in_power_down) begin
if ((ck_cntr - ck_cke_cmd <= TCPDED) && (cmd !== NOP))
$display ("%m: at time %t ERROR: tCPDED violation during Power Down or Self Refresh Entry. NOP or Deselect is required.", $time);
end
prev_cke = cke;
end
endtask
task data_task;
reg [BA_BITS-1:0] bank;
reg [ROW_BITS-1:0] row;
reg [COL_BITS-1:0] col;
integer i;
integer j;
begin
if (diff_ck) begin
for (i=0; i<32; i=i+1) begin
if (dq_in_valid && dll_locked && ($time - tm_dqs_neg[i] < $rtoi(TDSS*tck_avg)))
$display ("%m: at time %t ERROR: tDSS violation on %s bit %d", $time, dqs_string[i/16], i%16);
if (check_write_dqs_high[i])
$display ("%m: at time %t ERROR: %s bit %d latching edge required during the preceding clock period.", $time, dqs_string[i/16], i%16);
end
check_write_dqs_high <= 0;
end else begin
for (i=0; i<32; i=i+1) begin
if (dll_locked && dq_in_valid) begin
tm_tdqss = abs_value(1.0*tm_ck_pos - tm_dqss_pos[i]);
if ((tm_tdqss < tck_avg/2.0) && (tm_tdqss > TDQSS*tck_avg))
$display ("%m: at time %t ERROR: tDQSS violation on %s bit %d", $time, dqs_string[i/16], i%16);
end
if (check_write_dqs_low[i])
$display ("%m: at time %t ERROR: %s bit %d latching edge required during the preceding clock period", $time, dqs_string[i/16], i%16);
end
check_write_preamble <= 0;
check_write_postamble <= 0;
check_write_dqs_low <= 0;
end
if (wr_pipeline[0] || rd_pipeline[0]) begin
bank = ba_pipeline[0];
row = row_pipeline[0];
col = col_pipeline[0];
burst_cntr = 0;
memory_read(bank, row, col, memory_data);
end
// burst counter
if (burst_cntr < burst_length) begin
burst_position = col ^ burst_cntr;
if (!burst_order) begin
burst_position[BO_BITS-1:0] = col + burst_cntr;
end
burst_cntr = burst_cntr + 1;
end
// write dqs counter
if (wr_pipeline[WDQS_PRE + 1]) begin
wdqs_cntr = WDQS_PRE + bl_pipeline[WDQS_PRE + 1] + WDQS_PST - 1;
end
// write dqs
if ((wr_pipeline[2]) && (wdq_cntr == 0)) begin //write preamble
check_write_preamble <= ({DQS_BITS{1'b1}}<<16) | {DQS_BITS{1'b1}};
end
if (wdqs_cntr > 1) begin // write data
if ((wdqs_cntr - WDQS_PST)%2) begin
check_write_dqs_high <= ({DQS_BITS{1'b1}}<<16) | {DQS_BITS{1'b1}};
end else begin
check_write_dqs_low <= ({DQS_BITS{1'b1}}<<16) | {DQS_BITS{1'b1}};
end
end
if (wdqs_cntr == WDQS_PST) begin // write postamble
check_write_postamble <= ({DQS_BITS{1'b1}}<<16) | {DQS_BITS{1'b1}};
end
if (wdqs_cntr > 0) begin
wdqs_cntr = wdqs_cntr - 1;
end
// write dq
if (dq_in_valid) begin // write data
bit_mask = 0;
if (diff_ck) begin
for (i=0; i<DM_BITS; i=i+1) begin
bit_mask = bit_mask | ({`DQ_PER_DQS{~dm_in_neg[i]}}<<(burst_position*DQ_BITS + i*`DQ_PER_DQS));
end
memory_data = (dq_in_neg<<(burst_position*DQ_BITS) & bit_mask) | (memory_data & ~bit_mask);
end else begin
for (i=0; i<DM_BITS; i=i+1) begin
bit_mask = bit_mask | ({`DQ_PER_DQS{~dm_in_pos[i]}}<<(burst_position*DQ_BITS + i*`DQ_PER_DQS));
end
memory_data = (dq_in_pos<<(burst_position*DQ_BITS) & bit_mask) | (memory_data & ~bit_mask);
end
dq_temp = memory_data>>(burst_position*DQ_BITS);
if (DEBUG) $display ("%m: at time %t INFO: WRITE @ DQS= bank = %h row = %h col = %h data = %h",$time, bank, row, (-1*BL_MAX & col) + burst_position, dq_temp);
if (burst_cntr%BL_MIN == 0) begin
memory_write(bank, row, col, memory_data);
end
end
if (wr_pipeline[1]) begin
wdq_cntr = bl_pipeline[1];
end
if (wdq_cntr > 0) begin
wdq_cntr = wdq_cntr - 1;
dq_in_valid = 1'b1;
end else begin
dq_in_valid = 1'b0;
dqs_in_valid <= 1'b0;
for (i=0; i<31; i=i+1) begin
wdqs_pos_cntr[i] <= 0;
end
end
if (wr_pipeline[0]) begin
b2b_write <= 1'b0;
end
if (wr_pipeline[2]) begin
if (dqs_in_valid) begin
b2b_write <= 1'b1;
end
dqs_in_valid <= 1'b1;
wr_burst_length = bl_pipeline[2];
end
// read dqs enable counter
if (rd_pipeline[RDQSEN_PRE]) begin
rdqsen_cntr = RDQSEN_PRE + bl_pipeline[RDQSEN_PRE] + RDQSEN_PST - 1;
end
if (rdqsen_cntr > 0) begin
rdqsen_cntr = rdqsen_cntr - 1;
dqs_out_en = 1'b1;
end else begin
dqs_out_en = 1'b0;
end
// read dqs counter
if (rd_pipeline[RDQS_PRE]) begin
rdqs_cntr = RDQS_PRE + bl_pipeline[RDQS_PRE] + RDQS_PST - 1;
end
// read dqs
if (((rd_pipeline>>1 & {RDQS_PRE{1'b1}}) > 0) && (rdq_cntr == 0)) begin //read preamble
dqs_out = 1'b0;
end else if (rdqs_cntr > RDQS_PST) begin // read data
dqs_out = rdqs_cntr - RDQS_PST;
end else if (rdqs_cntr > 0) begin // read postamble
dqs_out = 1'b0;
end else begin
dqs_out = 1'b1;
end
if (rdqs_cntr > 0) begin
rdqs_cntr = rdqs_cntr - 1;
end
// read dq enable counter
if (rd_pipeline[RDQEN_PRE]) begin
rdqen_cntr = RDQEN_PRE + bl_pipeline[RDQEN_PRE] + RDQEN_PST;
end
if (rdqen_cntr > 0) begin
rdqen_cntr = rdqen_cntr - 1;
dq_out_en = 1'b1;
end else begin
dq_out_en = 1'b0;
end
// read dq
if (rd_pipeline[0]) begin
rdq_cntr = bl_pipeline[0];
end
if (rdq_cntr > 0) begin // read data
if (mpr_en) begin
`ifdef MPR_DQ0 // DQ0 output MPR data, other DQ low
if (mpr_select == 2'b00) begin // Calibration Pattern
dq_temp = {DQS_BITS{{`DQ_PER_DQS-1{1'b0}}, calibration_pattern[burst_position]}};
end else if (odts_readout && (mpr_select == 2'b11)) begin // Temp Sensor (ODTS)
dq_temp = {DQS_BITS{{`DQ_PER_DQS-1{1'b0}}, temp_sensor[burst_position]}};
end else begin // Reserved
dq_temp = {DQS_BITS{{`DQ_PER_DQS-1{1'b0}}, 1'bx}};
end
`else // all DQ output MPR data
if (mpr_select == 2'b00) begin // Calibration Pattern
dq_temp = {DQS_BITS{{`DQ_PER_DQS{calibration_pattern[burst_position]}}}};
end else if (odts_readout && (mpr_select == 2'b11)) begin // Temp Sensor (ODTS)
dq_temp = {DQS_BITS{{`DQ_PER_DQS{temp_sensor[burst_position]}}}};
end else begin // Reserved
dq_temp = {DQS_BITS{{`DQ_PER_DQS{1'bx}}}};
end
`endif
if (DEBUG) $display ("%m: at time %t READ @ DQS MultiPurpose Register %d, col = %d, data = %b", $time, mpr_select, burst_position, dq_temp[0]);
end else begin
dq_temp = memory_data>>(burst_position*DQ_BITS);
if (DEBUG) $display ("%m: at time %t INFO: READ @ DQS= bank = %h row = %h col = %h data = %h",$time, bank, row, (-1*BL_MAX & col) + burst_position, dq_temp);
end
dq_out = dq_temp;
rdq_cntr = rdq_cntr - 1;
end else begin
dq_out = {DQ_BITS{1'b1}};
end
// delay signals prior to output
if (RANDOM_OUT_DELAY && (dqs_out_en || (|dqs_out_en_dly) || dq_out_en || (|dq_out_en_dly))) begin
for (i=0; i<DQS_BITS; i=i+1) begin
// DQSCK requirements
// 1.) less than tDQSCK
// 2.) greater than -tDQSCK
// 3.) cannot change more than tQH + tDQSQ from previous DQS edge
dqsck_max = TDQSCK;
if (dqsck_max > dqsck[i] + TQH*tck_avg + TDQSQ) begin
dqsck_max = dqsck[i] + TQH*tck_avg + TDQSQ;
end
dqsck_min = -1*TDQSCK;
if (dqsck_min < dqsck[i] - TQH*tck_avg - TDQSQ) begin
dqsck_min = dqsck[i] - TQH*tck_avg - TDQSQ;
end
// DQSQ requirements
// 1.) less than tDQSQ
// 2.) greater than 0
// 3.) greater than tQH from the previous DQS edge
dqsq_min = 0;
if (dqsq_min < dqsck[i] - TQH*tck_avg) begin
dqsq_min = dqsck[i] - TQH*tck_avg;
end
if (dqsck_min == dqsck_max) begin
dqsck[i] = dqsck_min;
end else begin
dqsck[i] = $dist_uniform(seed, dqsck_min, dqsck_max);
end
dqsq_max = TDQSQ + dqsck[i];
dqs_out_en_dly[i] <= #(tck_avg/2) dqs_out_en;
dqs_out_dly[i] <= #(tck_avg/2 + dqsck[i]) dqs_out;
if (!write_levelization) begin
for (j=0; j<`DQ_PER_DQS; j=j+1) begin
dq_out_en_dly[i*`DQ_PER_DQS + j] <= #(tck_avg/2) dq_out_en;
if (dqsq_min == dqsq_max) begin
dq_out_dly [i*`DQ_PER_DQS + j] <= #(tck_avg/2 + dqsq_min) dq_out[i*`DQ_PER_DQS + j];
end else begin
dq_out_dly [i*`DQ_PER_DQS + j] <= #(tck_avg/2 + $dist_uniform(seed, dqsq_min, dqsq_max)) dq_out[i*`DQ_PER_DQS + j];
end
end
end
end
end else begin
out_delay = tck_avg/2;
dqs_out_en_dly <= #(out_delay) {DQS_BITS{dqs_out_en}};
dqs_out_dly <= #(out_delay) {DQS_BITS{dqs_out }};
if (write_levelization !== 1'b1) begin
dq_out_en_dly <= #(out_delay) {DQ_BITS {dq_out_en }};
dq_out_dly <= #(out_delay) {DQ_BITS {dq_out }};
end
end
end
endtask
always @ (posedge rst_n_in) begin : reset
integer i;
if (rst_n_in) begin
if ($time < 200000000 && check_strict_timing)
$display ("%m at time %t WARNING: 200 us is required before RST_N goes inactive.", $time);
if (cke_in !== 1'b0)
$display ("%m: at time %t ERROR: CKE must be inactive when RST_N goes inactive.", $time);
if ($time - tm_cke < 10000)
$display ("%m: at time %t ERROR: CKE must be maintained inactive for 10 ns before RST_N goes inactive.", $time);
// clear memory
`ifdef MAX_MEM
// verification group does not erase memory
// for (banki = 0; banki < `BANKS; banki = banki + 1) begin
// $fclose(memfd[banki]);
// memfd[banki] = open_bank_file(banki);
// end
`else
memory_used <= 0; //erase memory
`endif
end
end
always @(negedge rst_n_in or posedge diff_ck or negedge diff_ck) begin : main
integer i;
if (!rst_n_in) begin
reset_task;
end else begin
if (!in_self_refresh && (diff_ck !== 1'b0) && (diff_ck !== 1'b1))
$display ("%m: at time %t ERROR: CK and CK_N are not allowed to go to an unknown state.", $time);
data_task;
// Clock Frequency Change is legal:
// 1.) During Self Refresh
// 2.) During Precharge Power Down (DLL on or off)
if (in_self_refresh || (in_power_down && (active_bank == 0))) begin
if (diff_ck) begin
tjit_per_rtime = $time - tm_ck_pos - tck_avg;
end else begin
tjit_per_rtime = $time - tm_ck_neg - tck_avg;
end
if (dll_locked && (abs_value(tjit_per_rtime) > TJIT_PER)) begin
if ((tm_ck_pos - tm_cke_cmd < TCKSRE) || (ck_cntr - ck_cke_cmd < TCKSRE_TCK))
$display ("%m: at time %t ERROR: tCKSRE violation during Self Refresh or Precharge Power Down Entry", $time);
if (odt_state) begin
$display ("%m: at time %t ERROR: Clock Frequency Change Failure. ODT must be off prior to Clock Frequency Change.", $time);
if (STOP_ON_ERROR) $stop(0);
end else begin
if (DEBUG) $display ("%m: at time %t INFO: Clock Frequency Change detected. DLL Reset is Required.", $time);
tm_freq_change <= $time;
ck_freq_change <= ck_cntr;
dll_locked = 0;
end
end
end
if (diff_ck) begin
// check setup of command signals
if ($time > TIS) begin
if ($time - tm_cke < TIS)
$display ("%m: at time %t ERROR: tIS violation on CKE by %t", $time, tm_cke + TIS - $time);
if (cke_in) begin
for (i=0; i<22; i=i+1) begin
if ($time - tm_cmd_addr[i] < TIS)
$display ("%m: at time %t ERROR: tIS violation on %s by %t", $time, cmd_addr_string[i], tm_cmd_addr[i] + TIS - $time);
end
end
end
// update current state
if (dll_locked) begin
if (mr_chk == 0) begin
mr_chk = 1;
end else if (init_mode_reg[0] && (mr_chk == 1)) begin
// check CL value against the clock frequency
if (cas_latency*tck_avg < CL_TIME && check_strict_timing)
$display ("%m: at time %t ERROR: CAS Latency = %d is illegal @tCK(avg) = %f", $time, cas_latency, tck_avg);
// check WR value against the clock frequency
if (ceil(write_recovery*tck_avg) < TWR)
$display ("%m: at time %t ERROR: Write Recovery = %d is illegal @tCK(avg) = %f", $time, write_recovery, tck_avg);
// check the CWL value against the clock frequency
if (check_strict_timing) begin
case (cas_write_latency)
5 : if (tck_avg < 2500.0) $display ("%m: at time %t ERROR: CWL = %d is illegal @tCK(avg) = %f", $time, cas_write_latency, tck_avg);
6 : if ((tck_avg < 1875.0) || (tck_avg >= 2500.0)) $display ("%m: at time %t ERROR: CWL = %d is illegal @tCK(avg) = %f", $time, cas_write_latency, tck_avg);
7 : if ((tck_avg < 1500.0) || (tck_avg >= 1875.0)) $display ("%m: at time %t ERROR: CWL = %d is illegal @tCK(avg) = %f", $time, cas_write_latency, tck_avg);
8 : if ((tck_avg < 1250.0) || (tck_avg >= 1500.0)) $display ("%m: at time %t ERROR: CWL = %d is illegal @tCK(avg) = %f", $time, cas_write_latency, tck_avg);
9 : if ((tck_avg < 15e3/14) || (tck_avg >= 1250.0)) $display ("%m: at time %t ERROR: CWL = %d is illegal @tCK(avg) = %f", $time, cas_write_latency, tck_avg);
10: if ((tck_avg < 937.5) || (tck_avg >= 15e3/14)) $display ("%m: at time %t ERROR: CWL = %d is illegal @tCK(avg) = %f", $time, cas_write_latency, tck_avg);
default : $display ("%m: at time %t ERROR: CWL = %d is illegal @tCK(avg) = %f", $time, cas_write_latency, tck_avg);
endcase
// check the CL value against the clock frequency
if (!valid_cl(cas_latency, cas_write_latency))
$display ("%m: at time %t ERROR: CAS Latency = %d is not valid when CAS Write Latency = %d", $time, cas_latency, cas_write_latency);
end
mr_chk = 2;
end
end else if (!in_self_refresh) begin
mr_chk = 0;
if (ck_cntr - ck_dll_reset == TDLLK) begin
dll_locked = 1;
end
end
if (|auto_precharge_bank) begin
for (i=0; i<`BANKS; i=i+1) begin
// Write with Auto Precharge Calculation
// 1. Meet minimum tRAS requirement
// 2. Write Latency PLUS BL/2 cycles PLUS WR after Write command
if (write_precharge_bank[i]) begin
if ($time - tm_bank_activate[i] >= TRAS_MIN) begin
if (ck_cntr - ck_bank_write[i] >= write_latency + burst_length/2 + write_recovery) begin
if (DEBUG) $display ("%m: at time %t INFO: Auto Precharge bank %d", $time, i);
write_precharge_bank[i] = 0;
active_bank[i] = 0;
auto_precharge_bank[i] = 0;
tm_bank_precharge[i] = $time;
tm_precharge = $time;
ck_precharge = ck_cntr;
end
end
end
// Read with Auto Precharge Calculation
// 1. Meet minimum tRAS requirement
// 2. Additive Latency plus 4 cycles after Read command
// 3. tRTP after the last 8-bit prefetch
if (read_precharge_bank[i]) begin
if (($time - tm_bank_activate[i] >= TRAS_MIN) && (ck_cntr - ck_bank_read[i] >= additive_latency + TRTP_TCK)) begin
read_precharge_bank[i] = 0;
// In case the internal precharge is pushed out by tRTP, tRP starts at the point where
// the internal precharge happens (not at the next rising clock edge after this event).
if ($time - tm_bank_read_end[i] < TRTP) begin
if (DEBUG) $display ("%m: at time %t INFO: Auto Precharge bank %d", tm_bank_read_end[i] + TRTP, i);
active_bank[i] <= #(tm_bank_read_end[i] + TRTP - $time) 0;
auto_precharge_bank[i] <= #(tm_bank_read_end[i] + TRTP - $time) 0;
tm_bank_precharge[i] <= #(tm_bank_read_end[i] + TRTP - $time) tm_bank_read_end[i] + TRTP;
tm_precharge <= #(tm_bank_read_end[i] + TRTP - $time) tm_bank_read_end[i] + TRTP;
ck_precharge = ck_cntr;
end else begin
if (DEBUG) $display ("%m: at time %t INFO: Auto Precharge bank %d", $time, i);
active_bank[i] = 0;
auto_precharge_bank[i] = 0;
tm_bank_precharge[i] = $time;
tm_precharge = $time;
ck_precharge = ck_cntr;
end
end
end
end
end
// respond to incoming command
if (cke_in ^ prev_cke) begin
tm_cke_cmd <= $time;
ck_cke_cmd <= ck_cntr;
end
cmd_task(cke_in, cmd_n_in, ba_in, addr_in);
if ((cmd_n_in == WRITE) || (cmd_n_in == READ)) begin
al_pipeline[2*additive_latency] = 1'b1;
end
if (al_pipeline[0]) begin
// check tRCD after additive latency
if ((rd_pipeline[2*cas_latency - 1]) && ($time - tm_bank_activate[ba_pipeline[2*cas_latency - 1]] < TRCD))
$display ("%m: at time %t ERROR: tRCD violation during %s", $time, cmd_string[READ]);
if ((wr_pipeline[2*cas_write_latency + 1]) && ($time - tm_bank_activate[ba_pipeline[2*cas_write_latency + 1]] < TRCD))
$display ("%m: at time %t ERROR: tRCD violation during %s", $time, cmd_string[WRITE]);
// check tWTR after additive latency
if (rd_pipeline[2*cas_latency - 1]) begin //{
if (truebl4) begin //{
i = ba_pipeline[2*cas_latency - 1];
if ($time - tm_group_write_end[i[1]] < TWTR)
$display ("%m: at time %t ERROR: tWTR violation during %s", $time, cmd_string[READ]);
if ($time - tm_write_end < TWTR_DG)
$display ("%m: at time %t ERROR: tWTR_DG violation during %s", $time, cmd_string[READ]);
end else begin
if ($time - tm_write_end < TWTR)
$display ("%m: at time %t ERROR: tWTR violation during %s", $time, cmd_string[READ]);
end
end
end
if (rd_pipeline) begin
if (rd_pipeline[2*cas_latency - 1]) begin
tm_bank_read_end[ba_pipeline[2*cas_latency - 1]] <= $time;
end
end
for (i=0; i<`BANKS; i=i+1) begin
if ((ck_cntr - ck_bank_write[i] > write_latency) && (ck_cntr - ck_bank_write[i] <= write_latency + burst_length/2)) begin
tm_bank_write_end[i] <= $time;
tm_group_write_end[i[1]] <= $time;
tm_write_end <= $time;
end
end
// clk pin is disabled during self refresh
if (!in_self_refresh && tm_ck_pos ) begin
tjit_cc_time = $time - tm_ck_pos - tck_i;
tck_i = $time - tm_ck_pos;
tck_avg = tck_avg - tck_sample[ck_cntr%TDLLK]/$itor(TDLLK);
tck_avg = tck_avg + tck_i/$itor(TDLLK);
tck_sample[ck_cntr%TDLLK] = tck_i;
tjit_per_rtime = tck_i - tck_avg;
if (dll_locked && check_strict_timing) begin
// check accumulated error
terr_nper_rtime = 0;
for (i=0; i<12; i=i+1) begin
terr_nper_rtime = terr_nper_rtime + tck_sample[i] - tck_avg;
terr_nper_rtime = abs_value(terr_nper_rtime);
case (i)
0 :;
1 : if (terr_nper_rtime - TERR_2PER >= 1.0) $display ("%m: at time %t ERROR: tERR(2per) violation by %f ps.", $time, terr_nper_rtime - TERR_2PER);
2 : if (terr_nper_rtime - TERR_3PER >= 1.0) $display ("%m: at time %t ERROR: tERR(3per) violation by %f ps.", $time, terr_nper_rtime - TERR_3PER);
3 : if (terr_nper_rtime - TERR_4PER >= 1.0) $display ("%m: at time %t ERROR: tERR(4per) violation by %f ps.", $time, terr_nper_rtime - TERR_4PER);
4 : if (terr_nper_rtime - TERR_5PER >= 1.0) $display ("%m: at time %t ERROR: tERR(5per) violation by %f ps.", $time, terr_nper_rtime - TERR_5PER);
5 : if (terr_nper_rtime - TERR_6PER >= 1.0) $display ("%m: at time %t ERROR: tERR(6per) violation by %f ps.", $time, terr_nper_rtime - TERR_6PER);
6 : if (terr_nper_rtime - TERR_7PER >= 1.0) $display ("%m: at time %t ERROR: tERR(7per) violation by %f ps.", $time, terr_nper_rtime - TERR_7PER);
7 : if (terr_nper_rtime - TERR_8PER >= 1.0) $display ("%m: at time %t ERROR: tERR(8per) violation by %f ps.", $time, terr_nper_rtime - TERR_8PER);
8 : if (terr_nper_rtime - TERR_9PER >= 1.0) $display ("%m: at time %t ERROR: tERR(9per) violation by %f ps.", $time, terr_nper_rtime - TERR_9PER);
9 : if (terr_nper_rtime - TERR_10PER >= 1.0) $display ("%m: at time %t ERROR: tERR(10per) violation by %f ps.", $time, terr_nper_rtime - TERR_10PER);
10 : if (terr_nper_rtime - TERR_11PER >= 1.0) $display ("%m: at time %t ERROR: tERR(11per) violation by %f ps.", $time, terr_nper_rtime - TERR_11PER);
11 : if (terr_nper_rtime - TERR_12PER >= 1.0) $display ("%m: at time %t ERROR: tERR(12per) violation by %f ps.", $time, terr_nper_rtime - TERR_12PER);
endcase
end
// check tCK min/max/jitter
if (abs_value(tjit_per_rtime) - TJIT_PER >= 1.0)
$display ("%m: at time %t ERROR: tJIT(per) violation by %f ps.", $time, abs_value(tjit_per_rtime) - TJIT_PER);
if (abs_value(tjit_cc_time) - TJIT_CC >= 1.0)
$display ("%m: at time %t ERROR: tJIT(cc) violation by %f ps.", $time, abs_value(tjit_cc_time) - TJIT_CC);
if (TCK_MIN - tck_avg >= 1.0)
$display ("%m: at time %t ERROR: tCK(avg) minimum violation by %f ps.", $time, TCK_MIN - tck_avg);
if (tck_avg - TCK_MAX >= 1.0)
$display ("%m: at time %t ERROR: tCK(avg) maximum violation by %f ps.", $time, tck_avg - TCK_MAX);
// check tCL
if (tm_ck_neg - $time < TCL_ABS_MIN*tck_avg)
$display ("%m: at time %t ERROR: tCL(abs) minimum violation on CLK by %t", $time, TCL_ABS_MIN*tck_avg - tm_ck_neg + $time);
if (tcl_avg < TCL_AVG_MIN*tck_avg)
$display ("%m: at time %t ERROR: tCL(avg) minimum violation on CLK by %t", $time, TCL_AVG_MIN*tck_avg - tcl_avg);
if (tcl_avg > TCL_AVG_MAX*tck_avg)
$display ("%m: at time %t ERROR: tCL(avg) maximum violation on CLK by %t", $time, tcl_avg - TCL_AVG_MAX*tck_avg);
end
// calculate the tch avg jitter
tch_avg = tch_avg - tch_sample[ck_cntr%TDLLK]/$itor(TDLLK);
tch_avg = tch_avg + tch_i/$itor(TDLLK);
tch_sample[ck_cntr%TDLLK] = tch_i;
tjit_ch_rtime = tch_i - tch_avg;
duty_cycle = tch_avg/tck_avg;
// update timers/counters
tcl_i <= $time - tm_ck_neg;
end
prev_odt <= odt_in;
// update timers/counters
ck_cntr <= ck_cntr + 1;
tm_ck_pos = $time;
end else begin
// clk pin is disabled during self refresh
if (!in_self_refresh) begin
if (dll_locked && check_strict_timing) begin
if ($time - tm_ck_pos < TCH_ABS_MIN*tck_avg)
$display ("%m: at time %t ERROR: tCH(abs) minimum violation on CLK by %t", $time, TCH_ABS_MIN*tck_avg - $time + tm_ck_pos);
if (tch_avg < TCH_AVG_MIN*tck_avg)
$display ("%m: at time %t ERROR: tCH(avg) minimum violation on CLK by %t", $time, TCH_AVG_MIN*tck_avg - tch_avg);
if (tch_avg > TCH_AVG_MAX*tck_avg)
$display ("%m: at time %t ERROR: tCH(avg) maximum violation on CLK by %t", $time, tch_avg - TCH_AVG_MAX*tck_avg);
end
// calculate the tcl avg jitter
tcl_avg = tcl_avg - tcl_sample[ck_cntr%TDLLK]/$itor(TDLLK);
tcl_avg = tcl_avg + tcl_i/$itor(TDLLK);
tcl_sample[ck_cntr%TDLLK] = tcl_i;
// update timers/counters
tch_i <= $time - tm_ck_pos;
end
tm_ck_neg = $time;
end
// on die termination
if (odt_en || dyn_odt_en) begin
// odt pin is disabled during self refresh
if (!in_self_refresh && diff_ck) begin
if ($time - tm_odt < TIS)
$display ("%m: at time %t ERROR: tIS violation on ODT by %t", $time, tm_odt + TIS - $time);
if (prev_odt ^ odt_in) begin
if (!dll_locked)
$display ("%m: at time %t WARNING: tDLLK violation during ODT transition.", $time);
if (($time - tm_load_mode < TMOD) || (ck_cntr - ck_load_mode < TMOD_TCK))
$display ("%m: at time %t ERROR: tMOD violation during ODT transition", $time);
if (ck_cntr - ck_zqinit < TZQINIT)
$display ("%m: at time %t ERROR: TZQinit violation during ODT transition", $time);
if (ck_cntr - ck_zqoper < TZQOPER)
$display ("%m: at time %t ERROR: TZQoper violation during ODT transition", $time);
if (ck_cntr - ck_zqcs < TZQCS)
$display ("%m: at time %t ERROR: tZQcs violation during ODT transition", $time);
// if (($time - tm_slow_exit_pd < TXPDLL) || (ck_cntr - ck_slow_exit_pd < TXPDLL_TCK))
// $display ("%m: at time %t ERROR: tXPDLL violation during ODT transition", $time);
if (ck_cntr - ck_self_refresh < TXSDLL)
$display ("%m: at time %t ERROR: tXSDLL violation during ODT transition", $time);
if (in_self_refresh)
$display ("%m: at time %t ERROR: Illegal ODT transition during Self Refresh.", $time);
if (!odt_in && (ck_cntr - ck_odt < ODTH4))
$display ("%m: at time %t ERROR: ODTH4 violation during ODT transition", $time);
if (!odt_in && (ck_cntr - ck_odth8 < ODTH8))
$display ("%m: at time %t ERROR: ODTH8 violation during ODT transition", $time);
if (($time - tm_slow_exit_pd < TXPDLL) || (ck_cntr - ck_slow_exit_pd < TXPDLL_TCK))
$display ("%m: at time %t WARNING: tXPDLL during ODT transition. Synchronous or asynchronous change in termination resistance is possible.", $time);
// async ODT mode applies:
// 1.) during precharge power down with DLL off
// 2.) if tANPD has not been satisfied
// 3.) until tXPDLL has been satisfied
if ((in_power_down && low_power && (active_bank == 0)) || ($time - tm_slow_exit_pd < TXPDLL) || (ck_cntr - ck_slow_exit_pd < TXPDLL_TCK)) begin
odt_state = odt_in;
if (DEBUG && odt_en) $display ("%m: at time %t INFO: Async On Die Termination Rtt_NOM = %d Ohm", $time, {32{odt_state}} & get_rtt_nom(odt_rtt_nom));
if (odt_state) begin
odt_state_dly <= #(TAONPD) odt_state;
end else begin
odt_state_dly <= #(TAOFPD) odt_state;
end
// sync ODT mode applies:
// 1.) during normal operation
// 2.) during active power down
// 3.) during precharge power down with DLL on
end else begin
odt_pipeline[2*(write_latency - 2)] = 1'b1; // ODTLon, ODTLoff
end
ck_odt <= ck_cntr;
end
end
if (odt_pipeline[0]) begin
odt_state = ~odt_state;
if (DEBUG && odt_en) $display ("%m: at time %t INFO: Sync On Die Termination Rtt_NOM = %d Ohm", $time, {32{odt_state}} & get_rtt_nom(odt_rtt_nom));
if (odt_state) begin
odt_state_dly <= #(TAON) odt_state;
end else begin
odt_state_dly <= #(TAOF*tck_avg) odt_state;
end
end
if (rd_pipeline[RDQSEN_PRE]) begin
odt_cntr = 1 + RDQSEN_PRE + bl_pipeline[RDQSEN_PRE] + RDQSEN_PST - 1;
end
if (odt_cntr > 0) begin
if (odt_state) begin
$display ("%m: at time %t ERROR: On Die Termination must be OFF during Read data transfer.", $time);
end
odt_cntr = odt_cntr - 1;
end
if (dyn_odt_en && odt_state) begin
if (DEBUG && (dyn_odt_state ^ dyn_odt_pipeline[0]))
$display ("%m: at time %t INFO: Sync On Die Termination Rtt_WR = %d Ohm", $time, {32{dyn_odt_pipeline[0]}} & get_rtt_wr(odt_rtt_wr));
dyn_odt_state = dyn_odt_pipeline[0];
end
dyn_odt_state_dly <= #(TADC*tck_avg) dyn_odt_state;
end
/*
if (cke_in && write_levelization) begin
for (i=0; i<DQS_BITS; i=i+1) begin
if ($time - tm_dqs_pos[i] < TWLH)
$display ("%m: at time %t WARNING: tWLH violation on DQS bit %d positive edge. Indeterminate CK capture is possible.", $time, i);
end
end
*/
// shift pipelines
if (|wr_pipeline || |rd_pipeline || |al_pipeline) begin
al_pipeline = al_pipeline>>1;
wr_pipeline = wr_pipeline>>1;
rd_pipeline = rd_pipeline>>1;
for (i=0; i<`MAX_PIPE; i=i+1) begin
bl_pipeline[i] = bl_pipeline[i+1];
ba_pipeline[i] = ba_pipeline[i+1];
row_pipeline[i] = row_pipeline[i+1];
col_pipeline[i] = col_pipeline[i+1];
end
end
if (|odt_pipeline || |dyn_odt_pipeline) begin
odt_pipeline = odt_pipeline>>1;
dyn_odt_pipeline = dyn_odt_pipeline>>1;
end
end
end
// receiver(s)
task dqs_even_receiver;
input [3:0] i;
reg [63:0] bit_mask;
begin
bit_mask = {`DQ_PER_DQS{1'b1}}<<(i*`DQ_PER_DQS);
if (dqs_even[i]) begin
if (tdqs_en) begin // tdqs disables dm
dm_in_pos[i] = 1'b0;
end else begin
dm_in_pos[i] = dm_in[i];
end
dq_in_pos = (dq_in & bit_mask) | (dq_in_pos & ~bit_mask);
end
end
endtask
always @(posedge dqs_even[ 0]) dqs_even_receiver( 0);
always @(posedge dqs_even[ 1]) dqs_even_receiver( 1);
always @(posedge dqs_even[ 2]) dqs_even_receiver( 2);
always @(posedge dqs_even[ 3]) dqs_even_receiver( 3);
always @(posedge dqs_even[ 4]) dqs_even_receiver( 4);
always @(posedge dqs_even[ 5]) dqs_even_receiver( 5);
always @(posedge dqs_even[ 6]) dqs_even_receiver( 6);
always @(posedge dqs_even[ 7]) dqs_even_receiver( 7);
always @(posedge dqs_even[ 8]) dqs_even_receiver( 8);
always @(posedge dqs_even[ 9]) dqs_even_receiver( 9);
always @(posedge dqs_even[10]) dqs_even_receiver(10);
always @(posedge dqs_even[11]) dqs_even_receiver(11);
always @(posedge dqs_even[12]) dqs_even_receiver(12);
always @(posedge dqs_even[13]) dqs_even_receiver(13);
always @(posedge dqs_even[14]) dqs_even_receiver(14);
always @(posedge dqs_even[15]) dqs_even_receiver(15);
task dqs_odd_receiver;
input [3:0] i;
reg [63:0] bit_mask;
begin
bit_mask = {`DQ_PER_DQS{1'b1}}<<(i*`DQ_PER_DQS);
if (dqs_odd[i]) begin
if (tdqs_en) begin // tdqs disables dm
dm_in_neg[i] = 1'b0;
end else begin
dm_in_neg[i] = dm_in[i];
end
dq_in_neg = (dq_in & bit_mask) | (dq_in_neg & ~bit_mask);
end
end
endtask
always @(posedge dqs_odd[ 0]) dqs_odd_receiver( 0);
always @(posedge dqs_odd[ 1]) dqs_odd_receiver( 1);
always @(posedge dqs_odd[ 2]) dqs_odd_receiver( 2);
always @(posedge dqs_odd[ 3]) dqs_odd_receiver( 3);
always @(posedge dqs_odd[ 4]) dqs_odd_receiver( 4);
always @(posedge dqs_odd[ 5]) dqs_odd_receiver( 5);
always @(posedge dqs_odd[ 6]) dqs_odd_receiver( 6);
always @(posedge dqs_odd[ 7]) dqs_odd_receiver( 7);
always @(posedge dqs_odd[ 8]) dqs_odd_receiver( 8);
always @(posedge dqs_odd[ 9]) dqs_odd_receiver( 9);
always @(posedge dqs_odd[10]) dqs_odd_receiver(10);
always @(posedge dqs_odd[11]) dqs_odd_receiver(11);
always @(posedge dqs_odd[12]) dqs_odd_receiver(12);
always @(posedge dqs_odd[13]) dqs_odd_receiver(13);
always @(posedge dqs_odd[14]) dqs_odd_receiver(14);
always @(posedge dqs_odd[15]) dqs_odd_receiver(15);
// Processes to check hold and pulse width of control signals
always @(posedge rst_n_in) begin
if ($time > 100000) begin
if (tm_rst_n + 100000 > $time)
$display ("%m: at time %t ERROR: RST_N pulse width violation by %t", $time, tm_rst_n + 100000 - $time);
end
tm_rst_n = $time;
end
always @(cke_in) begin
if (rst_n_in) begin
if ($time > TIH) begin
if ($time - tm_ck_pos < TIH)
$display ("%m: at time %t ERROR: tIH violation on CKE by %t", $time, tm_ck_pos + TIH - $time);
end
if ($time - tm_cke < TIPW)
$display ("%m: at time %t ERROR: tIPW violation on CKE by %t", $time, tm_cke + TIPW - $time);
end
tm_cke = $time;
end
always @(odt_in) begin
if (rst_n_in && odt_en && !in_self_refresh) begin
if ($time - tm_ck_pos < TIH)
$display ("%m: at time %t ERROR: tIH violation on ODT by %t", $time, tm_ck_pos + TIH - $time);
if ($time - tm_odt < TIPW)
$display ("%m: at time %t ERROR: tIPW violation on ODT by %t", $time, tm_odt + TIPW - $time);
end
tm_odt = $time;
end
task cmd_addr_timing_check;
input i;
reg [4:0] i;
begin
if (rst_n_in && prev_cke) begin
if ($time - tm_ck_pos < TIH)
$display ("%m: at time %t ERROR: tIH violation on %s by %t", $time, cmd_addr_string[i], tm_ck_pos + TIH - $time);
if ($time - tm_cmd_addr[i] < TIPW)
$display ("%m: at time %t ERROR: tIPW violation on %s by %t", $time, cmd_addr_string[i], tm_cmd_addr[i] + TIPW - $time);
end
tm_cmd_addr[i] = $time;
end
endtask
always @(cs_n_in ) cmd_addr_timing_check( 0);
always @(ras_n_in ) cmd_addr_timing_check( 1);
always @(cas_n_in ) cmd_addr_timing_check( 2);
always @(we_n_in ) cmd_addr_timing_check( 3);
always @(ba_in [ 0]) cmd_addr_timing_check( 4);
always @(ba_in [ 1]) cmd_addr_timing_check( 5);
always @(ba_in [ 2]) cmd_addr_timing_check( 6);
always @(addr_in[ 0]) cmd_addr_timing_check( 7);
always @(addr_in[ 1]) cmd_addr_timing_check( 8);
always @(addr_in[ 2]) cmd_addr_timing_check( 9);
always @(addr_in[ 3]) cmd_addr_timing_check(10);
always @(addr_in[ 4]) cmd_addr_timing_check(11);
always @(addr_in[ 5]) cmd_addr_timing_check(12);
always @(addr_in[ 6]) cmd_addr_timing_check(13);
always @(addr_in[ 7]) cmd_addr_timing_check(14);
always @(addr_in[ 8]) cmd_addr_timing_check(15);
always @(addr_in[ 9]) cmd_addr_timing_check(16);
always @(addr_in[10]) cmd_addr_timing_check(17);
always @(addr_in[11]) cmd_addr_timing_check(18);
always @(addr_in[12]) cmd_addr_timing_check(19);
always @(addr_in[13]) cmd_addr_timing_check(20);
always @(addr_in[14]) cmd_addr_timing_check(21);
always @(addr_in[15]) cmd_addr_timing_check(22);
// Processes to check setup and hold of data signals
task dm_timing_check;
input i;
reg [3:0] i;
begin
if (dqs_in_valid) begin
if ($time - tm_dqs[i] < TDH)
$display ("%m: at time %t ERROR: tDH violation on DM bit %d by %t", $time, i, tm_dqs[i] + TDH - $time);
if (check_dm_tdipw[i]) begin
if ($time - tm_dm[i] < TDIPW)
$display ("%m: at time %t ERROR: tDIPW violation on DM bit %d by %t", $time, i, tm_dm[i] + TDIPW - $time);
end
end
check_dm_tdipw[i] <= 1'b0;
tm_dm[i] = $time;
end
endtask
always @(dm_in[ 0]) dm_timing_check( 0);
always @(dm_in[ 1]) dm_timing_check( 1);
always @(dm_in[ 2]) dm_timing_check( 2);
always @(dm_in[ 3]) dm_timing_check( 3);
always @(dm_in[ 4]) dm_timing_check( 4);
always @(dm_in[ 5]) dm_timing_check( 5);
always @(dm_in[ 6]) dm_timing_check( 6);
always @(dm_in[ 7]) dm_timing_check( 7);
always @(dm_in[ 8]) dm_timing_check( 8);
always @(dm_in[ 9]) dm_timing_check( 9);
always @(dm_in[10]) dm_timing_check(10);
always @(dm_in[11]) dm_timing_check(11);
always @(dm_in[12]) dm_timing_check(12);
always @(dm_in[13]) dm_timing_check(13);
always @(dm_in[14]) dm_timing_check(14);
always @(dm_in[15]) dm_timing_check(15);
task dq_timing_check;
input i;
reg [5:0] i;
begin
if (dqs_in_valid) begin
if ($time - tm_dqs[i/`DQ_PER_DQS] < TDH)
$display ("%m: at time %t ERROR: tDH violation on DQ bit %d by %t", $time, i, tm_dqs[i/`DQ_PER_DQS] + TDH - $time);
if (check_dq_tdipw[i]) begin
if ($time - tm_dq[i] < TDIPW)
$display ("%m: at time %t ERROR: tDIPW violation on DQ bit %d by %t", $time, i, tm_dq[i] + TDIPW - $time);
end
end
check_dq_tdipw[i] <= 1'b0;
tm_dq[i] = $time;
end
endtask
always @(dq_in[ 0]) dq_timing_check( 0);
always @(dq_in[ 1]) dq_timing_check( 1);
always @(dq_in[ 2]) dq_timing_check( 2);
always @(dq_in[ 3]) dq_timing_check( 3);
always @(dq_in[ 4]) dq_timing_check( 4);
always @(dq_in[ 5]) dq_timing_check( 5);
always @(dq_in[ 6]) dq_timing_check( 6);
always @(dq_in[ 7]) dq_timing_check( 7);
always @(dq_in[ 8]) dq_timing_check( 8);
always @(dq_in[ 9]) dq_timing_check( 9);
always @(dq_in[10]) dq_timing_check(10);
always @(dq_in[11]) dq_timing_check(11);
always @(dq_in[12]) dq_timing_check(12);
always @(dq_in[13]) dq_timing_check(13);
always @(dq_in[14]) dq_timing_check(14);
always @(dq_in[15]) dq_timing_check(15);
always @(dq_in[16]) dq_timing_check(16);
always @(dq_in[17]) dq_timing_check(17);
always @(dq_in[18]) dq_timing_check(18);
always @(dq_in[19]) dq_timing_check(19);
always @(dq_in[20]) dq_timing_check(20);
always @(dq_in[21]) dq_timing_check(21);
always @(dq_in[22]) dq_timing_check(22);
always @(dq_in[23]) dq_timing_check(23);
always @(dq_in[24]) dq_timing_check(24);
always @(dq_in[25]) dq_timing_check(25);
always @(dq_in[26]) dq_timing_check(26);
always @(dq_in[27]) dq_timing_check(27);
always @(dq_in[28]) dq_timing_check(28);
always @(dq_in[29]) dq_timing_check(29);
always @(dq_in[30]) dq_timing_check(30);
always @(dq_in[31]) dq_timing_check(31);
always @(dq_in[32]) dq_timing_check(32);
always @(dq_in[33]) dq_timing_check(33);
always @(dq_in[34]) dq_timing_check(34);
always @(dq_in[35]) dq_timing_check(35);
always @(dq_in[36]) dq_timing_check(36);
always @(dq_in[37]) dq_timing_check(37);
always @(dq_in[38]) dq_timing_check(38);
always @(dq_in[39]) dq_timing_check(39);
always @(dq_in[40]) dq_timing_check(40);
always @(dq_in[41]) dq_timing_check(41);
always @(dq_in[42]) dq_timing_check(42);
always @(dq_in[43]) dq_timing_check(43);
always @(dq_in[44]) dq_timing_check(44);
always @(dq_in[45]) dq_timing_check(45);
always @(dq_in[46]) dq_timing_check(46);
always @(dq_in[47]) dq_timing_check(47);
always @(dq_in[48]) dq_timing_check(48);
always @(dq_in[49]) dq_timing_check(49);
always @(dq_in[50]) dq_timing_check(50);
always @(dq_in[51]) dq_timing_check(51);
always @(dq_in[52]) dq_timing_check(52);
always @(dq_in[53]) dq_timing_check(53);
always @(dq_in[54]) dq_timing_check(54);
always @(dq_in[55]) dq_timing_check(55);
always @(dq_in[56]) dq_timing_check(56);
always @(dq_in[57]) dq_timing_check(57);
always @(dq_in[58]) dq_timing_check(58);
always @(dq_in[59]) dq_timing_check(59);
always @(dq_in[60]) dq_timing_check(60);
always @(dq_in[61]) dq_timing_check(61);
always @(dq_in[62]) dq_timing_check(62);
always @(dq_in[63]) dq_timing_check(63);
task dqs_pos_timing_check;
input i;
reg [4:0] i;
reg [3:0] j;
begin
if (write_levelization && i<16) begin
if (ck_cntr - ck_load_mode < TWLMRD)
$display ("%m: at time %t ERROR: tWLMRD violation on DQS bit %d positive edge.", $time, i);
/*
if (($time - tm_ck_pos < TWLS) || ($time - tm_ck_neg < TWLS))
$display ("%m: at time %t WARNING: tWLS violation on DQS bit %d positive edge. Indeterminate CK capture is possible.", $time, i);
*/
if (DEBUG)
$display ("%m: at time %t Write Leveling @ DQS ck = %b", $time, diff_ck);
dq_out_en_dly[i*`DQ_PER_DQS] <= #(TWLO) 1'b1;
dq_out_dly[i*`DQ_PER_DQS] <= #(TWLO) diff_ck;
for (j=1; j<`DQ_PER_DQS; j=j+1) begin
dq_out_en_dly[i*`DQ_PER_DQS+j] <= #(TWLO + TWLOE) 1'b1;
dq_out_dly[i*`DQ_PER_DQS+j] <= #(TWLO + TWLOE) 1'b0;
end
end
if (dqs_in_valid && ((wdqs_pos_cntr[i] < wr_burst_length/2) || b2b_write)) begin
if (dqs_in[i] ^ prev_dqs_in[i]) begin
if (dll_locked) begin
if (check_write_preamble[i]) begin
if ($time - tm_dqs_pos[i] < $rtoi(TWPRE*tck_avg))
$display ("%m: at time %t ERROR: tWPRE violation on &s bit %d", $time, dqs_string[i/16], i%16);
end else if (check_write_postamble[i]) begin
if ($time - tm_dqs_neg[i] < $rtoi(TWPST*tck_avg))
$display ("%m: at time %t ERROR: tWPST violation on %s bit %d", $time, dqs_string[i/16], i%16);
end else begin
if ($time - tm_dqs_neg[i] < $rtoi(TDQSL*tck_avg))
$display ("%m: at time %t ERROR: tDQSL violation on %s bit %d", $time, dqs_string[i/16], i%16);
end
end
if ($time - tm_dm[i%16] < TDS)
$display ("%m: at time %t ERROR: tDS violation on DM bit %d by %t", $time, i, tm_dm[i%16] + TDS - $time);
if (!dq_out_en) begin
for (j=0; j<`DQ_PER_DQS; j=j+1) begin
if ($time - tm_dq[(i%16)*`DQ_PER_DQS+j] < TDS)
$display ("%m: at time %t ERROR: tDS violation on DQ bit %d by %t", $time, i*`DQ_PER_DQS+j, tm_dq[(i%16)*`DQ_PER_DQS+j] + TDS - $time);
check_dq_tdipw[(i%16)*`DQ_PER_DQS+j] <= 1'b1;
end
end
if ((wdqs_pos_cntr[i] < wr_burst_length/2) && !b2b_write) begin
wdqs_pos_cntr[i] <= wdqs_pos_cntr[i] + 1;
end else begin
wdqs_pos_cntr[i] <= 1;
end
check_dm_tdipw[i%16] <= 1'b1;
check_write_preamble[i] <= 1'b0;
check_write_postamble[i] <= 1'b0;
check_write_dqs_low[i] <= 1'b0;
tm_dqs[i%16] <= $time;
end else begin
$display ("%m: at time %t ERROR: Invalid latching edge on %s bit %d", $time, dqs_string[i/16], i%16);
end
end
tm_dqss_pos[i] <= $time;
tm_dqs_pos[i] = $time;
prev_dqs_in[i] <= dqs_in[i];
end
endtask
always @(posedge dqs_in[ 0]) dqs_pos_timing_check( 0);
always @(posedge dqs_in[ 1]) dqs_pos_timing_check( 1);
always @(posedge dqs_in[ 2]) dqs_pos_timing_check( 2);
always @(posedge dqs_in[ 3]) dqs_pos_timing_check( 3);
always @(posedge dqs_in[ 4]) dqs_pos_timing_check( 4);
always @(posedge dqs_in[ 5]) dqs_pos_timing_check( 5);
always @(posedge dqs_in[ 6]) dqs_pos_timing_check( 6);
always @(posedge dqs_in[ 7]) dqs_pos_timing_check( 7);
always @(posedge dqs_in[ 8]) dqs_pos_timing_check( 8);
always @(posedge dqs_in[ 9]) dqs_pos_timing_check( 9);
always @(posedge dqs_in[10]) dqs_pos_timing_check(10);
always @(posedge dqs_in[11]) dqs_pos_timing_check(11);
always @(posedge dqs_in[12]) dqs_pos_timing_check(12);
always @(posedge dqs_in[13]) dqs_pos_timing_check(13);
always @(posedge dqs_in[14]) dqs_pos_timing_check(14);
always @(posedge dqs_in[15]) dqs_pos_timing_check(15);
always @(negedge dqs_in[16]) dqs_pos_timing_check(16);
always @(negedge dqs_in[17]) dqs_pos_timing_check(17);
always @(negedge dqs_in[18]) dqs_pos_timing_check(18);
always @(negedge dqs_in[19]) dqs_pos_timing_check(19);
always @(negedge dqs_in[20]) dqs_pos_timing_check(20);
always @(negedge dqs_in[21]) dqs_pos_timing_check(21);
always @(negedge dqs_in[22]) dqs_pos_timing_check(22);
always @(negedge dqs_in[23]) dqs_pos_timing_check(23);
always @(negedge dqs_in[24]) dqs_pos_timing_check(24);
always @(negedge dqs_in[25]) dqs_pos_timing_check(25);
always @(negedge dqs_in[26]) dqs_pos_timing_check(26);
always @(negedge dqs_in[27]) dqs_pos_timing_check(27);
always @(negedge dqs_in[28]) dqs_pos_timing_check(28);
always @(negedge dqs_in[29]) dqs_pos_timing_check(29);
always @(negedge dqs_in[30]) dqs_pos_timing_check(30);
always @(negedge dqs_in[31]) dqs_pos_timing_check(31);
task dqs_neg_timing_check;
input i;
reg [4:0] i;
reg [3:0] j;
begin
if (write_levelization && i<16) begin
if (ck_cntr - ck_load_mode < TWLDQSEN)
$display ("%m: at time %t ERROR: tWLDQSEN violation on DQS bit %d.", $time, i);
if ($time - tm_dqs_pos[i] < $rtoi(TDQSH*tck_avg))
$display ("%m: at time %t ERROR: tDQSH violation on DQS bit %d by %t", $time, i, tm_dqs_pos[i] + TDQSH*tck_avg - $time);
end
if (dqs_in_valid && (wdqs_pos_cntr[i] > 0) && check_write_dqs_high[i]) begin
if (dqs_in[i] ^ prev_dqs_in[i]) begin
if (dll_locked) begin
if ($time - tm_dqs_pos[i] < $rtoi(TDQSH*tck_avg))
$display ("%m: at time %t ERROR: tDQSH violation on %s bit %d", $time, dqs_string[i/16], i%16);
if ($time - tm_ck_pos < $rtoi(TDSH*tck_avg))
$display ("%m: at time %t ERROR: tDSH violation on %s bit %d", $time, dqs_string[i/16], i%16);
end
if ($time - tm_dm[i%16] < TDS)
$display ("%m: at time %t ERROR: tDS violation on DM bit %d by %t", $time, i, tm_dm[i%16] + TDS - $time);
if (!dq_out_en) begin
for (j=0; j<`DQ_PER_DQS; j=j+1) begin
if ($time - tm_dq[(i%16)*`DQ_PER_DQS+j] < TDS)
$display ("%m: at time %t ERROR: tDS violation on DQ bit %d by %t", $time, i*`DQ_PER_DQS+j, tm_dq[(i%16)*`DQ_PER_DQS+j] + TDS - $time);
check_dq_tdipw[(i%16)*`DQ_PER_DQS+j] <= 1'b1;
end
end
check_dm_tdipw[i%16] <= 1'b1;
tm_dqs[i%16] <= $time;
end else begin
$display ("%m: at time %t ERROR: Invalid latching edge on %s bit %d", $time, dqs_string[i/16], i%16);
end
end
check_write_dqs_high[i] <= 1'b0;
tm_dqs_neg[i] = $time;
prev_dqs_in[i] <= dqs_in[i];
end
endtask
always @(negedge dqs_in[ 0]) dqs_neg_timing_check( 0);
always @(negedge dqs_in[ 1]) dqs_neg_timing_check( 1);
always @(negedge dqs_in[ 2]) dqs_neg_timing_check( 2);
always @(negedge dqs_in[ 3]) dqs_neg_timing_check( 3);
always @(negedge dqs_in[ 4]) dqs_neg_timing_check( 4);
always @(negedge dqs_in[ 5]) dqs_neg_timing_check( 5);
always @(negedge dqs_in[ 6]) dqs_neg_timing_check( 6);
always @(negedge dqs_in[ 7]) dqs_neg_timing_check( 7);
always @(negedge dqs_in[ 8]) dqs_neg_timing_check( 8);
always @(negedge dqs_in[ 9]) dqs_neg_timing_check( 9);
always @(negedge dqs_in[10]) dqs_neg_timing_check(10);
always @(negedge dqs_in[11]) dqs_neg_timing_check(11);
always @(negedge dqs_in[12]) dqs_neg_timing_check(12);
always @(negedge dqs_in[13]) dqs_neg_timing_check(13);
always @(negedge dqs_in[14]) dqs_neg_timing_check(14);
always @(negedge dqs_in[15]) dqs_neg_timing_check(15);
always @(posedge dqs_in[16]) dqs_neg_timing_check(16);
always @(posedge dqs_in[17]) dqs_neg_timing_check(17);
always @(posedge dqs_in[18]) dqs_neg_timing_check(18);
always @(posedge dqs_in[19]) dqs_neg_timing_check(19);
always @(posedge dqs_in[20]) dqs_neg_timing_check(20);
always @(posedge dqs_in[21]) dqs_neg_timing_check(21);
always @(posedge dqs_in[22]) dqs_neg_timing_check(22);
always @(posedge dqs_in[23]) dqs_neg_timing_check(23);
always @(posedge dqs_in[24]) dqs_neg_timing_check(24);
always @(posedge dqs_in[25]) dqs_neg_timing_check(25);
always @(posedge dqs_in[26]) dqs_neg_timing_check(26);
always @(posedge dqs_in[27]) dqs_neg_timing_check(27);
always @(posedge dqs_in[28]) dqs_neg_timing_check(28);
always @(posedge dqs_in[29]) dqs_neg_timing_check(29);
always @(posedge dqs_in[30]) dqs_neg_timing_check(30);
always @(posedge dqs_in[31]) dqs_neg_timing_check(31);
endmodule
|
module sky130_fd_sc_hs__nor2b (
Y ,
A ,
B_N ,
VPWR,
VGND
);
// Module ports
output Y ;
input A ;
input B_N ;
input VPWR;
input VGND;
// Local signals
wire Y not0_out ;
wire and0_out_Y ;
wire u_vpwr_vgnd0_out_Y;
// Name Output Other arguments
not not0 (not0_out , A );
and and0 (and0_out_Y , not0_out, B_N );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_Y, and0_out_Y, VPWR, VGND);
buf buf0 (Y , u_vpwr_vgnd0_out_Y );
endmodule
|
module is done
input h_hrd_hwr_n, // 1 - read, 0 - write
input h_mem_io_n, // 1 - Mem, 0 - IO.
input m_cpurd_state1, // To reset svga_sel_ff (mem)
input g_cpult_state1, // To reset svga_sel_ff (graph)
input g_lt_hwr_cmd, // cpu_wr cycle sm is idle
output h_iord, // The current IO cycle is read
output h_iowr, // The current IO cycle is write
output h_t_ready_n, // Done, Ready for next cycle
output reg host_cycle,
output io_cycle,
output h_svga_sel,
output wrbus_io_cycle
);
parameter idle_s = 2'b00,
dxfer_s0 = 2'b01,
dxfer_s1 = 2'b10,
turn_ar_s = 2'b11;
reg [1:0] current_state_ff;
reg [1:0] next_state;
reg svga_sel_ff;
reg svga_sel_reset; // to reset svga_sel_ff
reg io_ready_n;
reg io_cycle_bus;
wire svga_sel_ff_din;
wire int_ready_n;
wire tmp_int_ready_n;
wire comb_ready_n;
wire mem_write;
reg [4:0] tmo_cnt;
wire timer_ready_n;
wire dummy_out_0;
assign tmp_int_ready_n = a_ready_n & c_ready_n & g_ready_n &
m_ready_n;
assign int_ready_n = tmp_int_ready_n & timer_ready_n;
always @(posedge h_hclk, negedge h_reset_n)
if(~h_reset_n) current_state_ff <= idle_s;
else current_state_ff <= next_state;
always @* begin
host_cycle = 1'b0;
io_ready_n = 1'b1;
svga_sel_reset = 1'b0;
io_cycle_bus = 1'b0;
case(current_state_ff) // synopsys parallel_case full_case
idle_s: begin
if(h_svga_sel & g_lt_hwr_cmd & (~h_mem_io_n) )
next_state = dxfer_s0;
else
next_state = idle_s;
end
dxfer_s0: begin
host_cycle = 1'b1;
io_cycle_bus = 1'b1;
svga_sel_reset = 1'b1;
if(~int_ready_n) next_state = dxfer_s1;
else next_state = dxfer_s0;
end
dxfer_s1: begin
host_cycle = 1'b1;
io_cycle_bus = 1'b1;
next_state = turn_ar_s;
end
turn_ar_s: begin
io_ready_n = 1'b0;
io_cycle_bus = 1'b1;
next_state = idle_s;
end
endcase
end
assign io_cycle = host_cycle & (~h_mem_io_n);
assign wrbus_io_cycle = io_cycle_bus & (~h_mem_io_n);
assign h_iord = io_cycle & h_hrd_hwr_n;
assign h_iowr = io_cycle & (~h_hrd_hwr_n);
assign comb_ready_n = io_ready_n & g_mem_ready_n;
assign mem_write = h_mem_io_n & (~h_hrd_hwr_n);
// Generating timer_ready_n signal incase ready_n is not coming from any
// of the modules. If ready_n does not get generated from any of the modules
// for 25 h_hclk's then timer_ready_n gets generated.
always @(posedge h_hclk, negedge h_reset_n)
if (!h_reset_n) tmo_cnt <= 5'b0;
else if (t_svga_sel) tmo_cnt <= 5'b0;
else tmo_cnt <= tmo_cnt + io_cycle;
assign timer_ready_n = ~(tmo_cnt == 5'h19);
assign h_t_ready_n = comb_ready_n;
assign svga_sel_ff_din = ( ((~(m_cpurd_state1 | g_cpult_state1 |
svga_sel_reset)) &
(svga_sel_ff)) ) | ( t_svga_sel );
// Latching t_svga_sel and converting level to pulse
always @(posedge h_hclk, negedge h_reset_n)
if(~h_reset_n) svga_sel_ff <= 1'b0;
else svga_sel_ff <= #1 svga_sel_ff_din;
assign h_svga_sel = svga_sel_ff | t_svga_sel;
endmodule
|
module sky130_fd_sc_hd__lpflow_inputiso0n (
//# {{data|Data Signals}}
input A ,
output X ,
//# {{power|Power}}
input SLEEP_B
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
|
module tb_arbiter_IN_node();
//input
reg clk;
reg rst;
reg in_req_rdy;
reg in_rep_rdy;
reg [1:0] req_ctrl_in;
reg [1:0] rep_ctrl_in;
reg [15:0] req_flit_in;
reg [15:0] rep_flit_in;
reg [1:0] ic_download_state_in;
reg [1:0] dc_download_state_in;
reg [1:0] mem_download_state_in;
//output
wire ack_req;
wire ack_rep;
wire v_ic;
wire [15:0] flit_ic;
wire [1:0] ctrl_ic;
wire v_dc;
wire [15:0] flit_dc;
wire [1:0] ctrl_dc;
wire v_mem;
wire [15:0] flit_mem;
wire [1:0] ctrl_mem;
//instante the design unit
arbiter_IN_node uut (//input
.clk(clk),
.rst(rst),
.in_req_rdy(in_req_rdy),
.in_rep_rdy(in_rep_rdy),
.req_ctrl_in(req_ctrl_in),
.rep_ctrl_in(rep_ctrl_in),
.req_flit_in(req_flit_in),
.rep_flit_in(rep_flit_in),
.ic_download_state_in(ic_download_state_in),
.dc_download_state_in(dc_download_state_in),
.mem_download_state_in(mem_download_state_in),
//output
.ack_req(ack_req),
.ack_rep(ack_rep),
.v_ic(v_ic),
.flit_ic(flit_ic),
.ctrl_ic(ctrl_ic),
.v_dc(v_dc),
.flit_dc(flit_dc),
.ctrl_dc(ctrl_dc),
.v_mem(v_mem),
.flit_mem(flit_mem),
.ctrl_mem(ctrl_mem)
);
integer log_file;
//initial inputs
initial
begin
clk=1'b0;
rst=1'b1;
in_req_rdy=1'b0;
in_rep_rdy=1'b0;
req_ctrl_in=2'b00;
rep_ctrl_in=2'b00;
req_flit_in=16'h0000;
rep_flit_in=16'h0000;
ic_download_state_in=2'b00;//ic_idle
dc_download_state_in=2'b00;//dc_idle
mem_download_state_in=2'b00;//mem_idle
log_file=$fopen("log_arbiter_IN_node");
end
`define clk_step #14;
always #7 clk=~clk;
/////////////////////////////////////////////////////////////////
/////////////BEGIN TEST!/////////////////////////////////////////
initial begin
`clk_step
$display("BEGIN TEST!");
$fdisplay(log_file,"BEGIN TEST!");
rst=1'b0;
/////////////////////////////////////////////////////////////
///////////first case : ic rep flit and dc req come////////
////first flit come anad both ic_download and dc_download are ready
`clk_step
in_req_rdy=1'b1;
in_rep_rdy=1'b1;
req_ctrl_in=2'b01;
rep_ctrl_in=2'b01;
req_flit_in=16'hc0de;
rep_flit_in=16'hc280;
ic_download_state_in=2'b00;//ic_idle
dc_download_state_in=2'b00;//dc_idle
mem_download_state_in=2'b00;//mem_idle
///second flits ,both ready
`clk_step
in_req_rdy=1'b1;
in_rep_rdy=1'b1;
req_ctrl_in=2'b10;
rep_ctrl_in=2'b10;
req_flit_in=16'hc1de;
rep_flit_in=16'hc380;
ic_download_state_in=2'b01;//ic_busy
dc_download_state_in=2'b01;//dc_busy
mem_download_state_in=2'b00;//mem_idle
///3rd flits ,both ready
`clk_step
in_req_rdy=1'b1;
in_rep_rdy=1'b1;
req_ctrl_in=2'b10;
rep_ctrl_in=2'b10;
req_flit_in=16'hc2de;
rep_flit_in=16'hc480;
ic_download_state_in=2'b01;//ic_busy
dc_download_state_in=2'b01;//dc_busy
mem_download_state_in=2'b00;//mem_idle
////after a while ,last flits both come
`clk_step
in_req_rdy=1'b1;
in_rep_rdy=1'b1;
req_ctrl_in=2'b11;
rep_ctrl_in=2'b11;
req_flit_in=16'hc3de;
rep_flit_in=16'hc580;
ic_download_state_in=2'b01;//ic_busy
dc_download_state_in=2'b01;//dc_busy
mem_download_state_in=2'b00;//mem_idle
///this time make ic busy for a moment
`clk_step
in_req_rdy=1'b1;
in_rep_rdy=1'b1;
req_ctrl_in=2'b01;
rep_ctrl_in=2'b01;
req_flit_in=16'hc0de;
rep_flit_in=16'hc280;
ic_download_state_in=2'b10;//ic_busy
dc_download_state_in=2'b00;
mem_download_state_in=2'b00;
`clk_step
in_req_rdy=1'b1;
in_rep_rdy=1'b1;
req_ctrl_in=2'b10;
rep_ctrl_in=2'b01;
req_flit_in=16'hc1de;
rep_flit_in=16'hc280;
ic_download_state_in=2'b10;//ic_busy
dc_download_state_in=2'b01;
mem_download_state_in=2'b00;
`clk_step
in_req_rdy=1'b1;
in_rep_rdy=1'b1;
req_ctrl_in=2'b10;
rep_ctrl_in=2'b01;
req_flit_in=16'hc2de;
rep_flit_in=16'hc280;
ic_download_state_in=2'b10;//ic_busy
dc_download_state_in=2'b01;
mem_download_state_in=2'b00;
////now ic_donwload is idle
`clk_step
in_req_rdy=1'b1;
in_rep_rdy=1'b1;
req_ctrl_in=2'b11;
rep_ctrl_in=2'b01;
req_flit_in=16'hc3de;
rep_flit_in=16'hc280;
ic_download_state_in=2'b00;//ic_idle
dc_download_state_in=2'b01;
mem_download_state_in=2'b00;
`clk_step
in_req_rdy=1'b1;
in_rep_rdy=1'b1;
req_ctrl_in=2'b01;
rep_ctrl_in=2'b10;
req_flit_in=16'hc0df;
rep_flit_in=16'hc0de;
ic_download_state_in=2'b01;//ic_busy
dc_download_state_in=2'b10;//dc_rdy
mem_download_state_in=2'b00;
`clk_step
in_req_rdy=1'b1;
in_rep_rdy=1'b1;
req_ctrl_in=2'b01;
rep_ctrl_in=2'b10;
req_flit_in=16'hc0df;
rep_flit_in=16'hc1de;
ic_download_state_in=2'b01;//ic_busy
dc_download_state_in=2'b10;//dc_rdy
mem_download_state_in=2'b00;
`clk_step
in_req_rdy=1'b1;
in_rep_rdy=1'b1;
req_ctrl_in=2'b01;
rep_ctrl_in=2'b11;
req_flit_in=16'hc0df;
rep_flit_in=16'hc2de;
ic_download_state_in=2'b01;//ic_busy
dc_download_state_in=2'b10;//dc_rdy
mem_download_state_in=2'b00;
`clk_step
////////////////////////////////////////////////////////////
////////////second case :ic rep flit and mem req come ///////
///both mem and ic idle
`clk_step
in_req_rdy=1'b1;
in_rep_rdy=1'b1;
req_ctrl_in=2'b01;
rep_ctrl_in=2'b01;
req_flit_in=16'hfed0;
rep_flit_in=16'hc280;
ic_download_state_in=2'b00;//ic_idle
dc_download_state_in=2'b00;//dc_idle
mem_download_state_in=2'b00;//mem_idle
///second flits ,both ready
`clk_step
in_req_rdy=1'b1;
in_rep_rdy=1'b1;
req_ctrl_in=2'b10;
rep_ctrl_in=2'b10;
req_flit_in=16'h1234;
rep_flit_in=16'hc380;
ic_download_state_in=2'b01;//ic_busy
dc_download_state_in=2'b01;//dc_busy
mem_download_state_in=2'b00;//mem_idle
///3rd flits ,both ready
`clk_step
in_req_rdy=1'b1;
in_rep_rdy=1'b1;
req_ctrl_in=2'b10;
rep_ctrl_in=2'b10;
req_flit_in=16'habcd;
rep_flit_in=16'hc480;
ic_download_state_in=2'b01;//ic_busy
dc_download_state_in=2'b01;//dc_busy
mem_download_state_in=2'b00;//mem_idle
////after a while ,last flits both come
`clk_step
in_req_rdy=1'b1;
in_rep_rdy=1'b1;
req_ctrl_in=2'b11;
rep_ctrl_in=2'b11;
req_flit_in=16'hfed8;
rep_flit_in=16'hc580;
ic_download_state_in=2'b01;//ic_busy
dc_download_state_in=2'b01;//dc_busy
mem_download_state_in=2'b00;//mem_idle
///this time make mem rdy for a moment
//first flit to ic and mem download is ready for mem now
`clk_step
in_req_rdy=1'b1;
in_rep_rdy=1'b1;
req_ctrl_in=2'b01;
rep_ctrl_in=2'b01;
req_flit_in=16'hfed0;
rep_flit_in=16'hc280;
ic_download_state_in=2'b00;//ic_idle
dc_download_state_in=2'b00;//dc_idle
mem_download_state_in=2'b10;//mem_rdy
//second flit to ic and mem is still rdy for m_dl
`clk_step
in_req_rdy=1'b1;
in_rep_rdy=1'b1;
req_ctrl_in=2'b01;
rep_ctrl_in=2'b10;
req_flit_in=16'hfed0;
rep_flit_in=16'hc380;
ic_download_state_in=2'b01;//ic_busy
dc_download_state_in=2'b00;//dc_idle
mem_download_state_in=2'b10;//mem_rdy
//third flit to ic and first flit to mem
`clk_step
in_req_rdy=1'b1;
in_rep_rdy=1'b1;
req_ctrl_in=2'b01;
rep_ctrl_in=2'b10;
req_flit_in=16'hfed0;
rep_flit_in=16'hc480;
ic_download_state_in=2'b01;//ic_busy
dc_download_state_in=2'b00;//dc_idle
mem_download_state_in=2'b00;//mem_idle
//4th to ic and 2nd to mem
`clk_step
in_req_rdy=1'b1;
in_rep_rdy=1'b1;
req_ctrl_in=2'b10;
rep_ctrl_in=2'b10;
req_flit_in=16'h1234;
rep_flit_in=16'hc580;
ic_download_state_in=2'b01;//ic_busy
dc_download_state_in=2'b00;//dc_idle
mem_download_state_in=2'b01;//mem_busy
//last to ic and 7th to mem
`clk_step
in_req_rdy=1'b1;
in_rep_rdy=1'b1;
req_ctrl_in=2'b10;
rep_ctrl_in=2'b11;
req_flit_in=16'habcd;
rep_flit_in=16'hc980;
ic_download_state_in=2'b01;//ic_busy
dc_download_state_in=2'b00;//dc_idle
mem_download_state_in=2'b01;//mem_busy
//no flit to ic and last to mem
`clk_step
in_req_rdy=1'b1;
in_rep_rdy=1'b0;
req_ctrl_in=2'b11;
rep_ctrl_in=2'b00;
req_flit_in=16'h1357;
rep_flit_in=16'hc980;
ic_download_state_in=2'b10;//ic_rdy
dc_download_state_in=2'b00;//dc_idle
mem_download_state_in=2'b01;//mem_busy
////////////////////////////////////////////////////////////
///////////third case: only ic comes !//////////////////////
`clk_step
in_req_rdy=1'b0;
in_rep_rdy=1'b1;
req_ctrl_in=2'b00;
rep_ctrl_in=2'b01;
req_flit_in=16'h1234;
rep_flit_in=16'hc280;
ic_download_state_in=2'b00;//ic_idle
dc_download_state_in=2'b00;//dc_idle
mem_download_state_in=2'b00;//mem_idle
`clk_step
in_req_rdy=1'b0;
in_rep_rdy=1'b1;
req_ctrl_in=2'b00;
rep_ctrl_in=2'b10;
req_flit_in=16'h1234;
rep_flit_in=16'hc380;
ic_download_state_in=2'b01;//ic_idle
dc_download_state_in=2'b00;//dc_idle
mem_download_state_in=2'b00;//mem_idle
`clk_step
in_req_rdy=1'b0;
in_rep_rdy=1'b1;
req_ctrl_in=2'b00;
rep_ctrl_in=2'b10;
req_flit_in=16'h1234;
rep_flit_in=16'hc480;
ic_download_state_in=2'b01;//ic_idle
dc_download_state_in=2'b00;//dc_idle
mem_download_state_in=2'b00;//mem_idle
`clk_step
in_req_rdy=1'b0;
in_rep_rdy=1'b1;
req_ctrl_in=2'b00;
rep_ctrl_in=2'b11;
req_flit_in=16'h1234;
rep_flit_in=16'hc580;
ic_download_state_in=2'b01;//ic_idle
dc_download_state_in=2'b00;//dc_idle
mem_download_state_in=2'b00;//mem_idle
////////////////////////////////////////////////////////////
///////////4th case: dc rep and mem req come////////////////
`clk_step
in_req_rdy=1'b1;
in_rep_rdy=1'b1;
req_ctrl_in=2'b01;
rep_ctrl_in=2'b01;
req_flit_in=16'hfed0;
rep_flit_in=16'hc0de;
ic_download_state_in=2'b00;//ic_idle
dc_download_state_in=2'b00;//dc_idle
mem_download_state_in=2'b00;//mem_idle
`clk_step
in_req_rdy=1'b1;
in_rep_rdy=1'b1;
req_ctrl_in=2'b10;
rep_ctrl_in=2'b10;
req_flit_in=16'hfed1;
rep_flit_in=16'hc1de;
ic_download_state_in=2'b00;//ic_idle
dc_download_state_in=2'b01;//dc_busy
mem_download_state_in=2'b01;//mem_busy
`clk_step
in_req_rdy=1'b1;
in_rep_rdy=1'b1;
req_ctrl_in=2'b10;
rep_ctrl_in=2'b10;
req_flit_in=16'hfed2;
rep_flit_in=16'hc2de;
ic_download_state_in=2'b00;//ic_idle
dc_download_state_in=2'b01;//dc_busy
mem_download_state_in=2'b01;//mem_busy
`clk_step
in_req_rdy=1'b1;
in_rep_rdy=1'b1;
req_ctrl_in=2'b10;
rep_ctrl_in=2'b10;
req_flit_in=16'hfed3;
rep_flit_in=16'hc3de;
ic_download_state_in=2'b00;//ic_idle
dc_download_state_in=2'b01;//dc_busy
mem_download_state_in=2'b01;//mem_busy
`clk_step
in_req_rdy=1'b1;
in_rep_rdy=1'b1;
req_ctrl_in=2'b10;
rep_ctrl_in=2'b11;
req_flit_in=16'hfed4;
rep_flit_in=16'hc4de;
ic_download_state_in=2'b00;//ic_idle
dc_download_state_in=2'b01;//dc_busy
mem_download_state_in=2'b01;//mem_busy
`clk_step
in_req_rdy=1'b1;
in_rep_rdy=1'b1;
req_ctrl_in=2'b10;
rep_ctrl_in=2'b01;
req_flit_in=16'hfed5;
rep_flit_in=16'hc5de;
ic_download_state_in=2'b00;//ic_idle
dc_download_state_in=2'b10;//dc_rdy
mem_download_state_in=2'b01;//mem_busy
`clk_step
in_req_rdy=1'b1;
in_rep_rdy=1'b1;
req_ctrl_in=2'b11;
rep_ctrl_in=2'b01;
req_flit_in=16'hfed4;
rep_flit_in=16'hc4de;
ic_download_state_in=2'b00;//ic_idle
dc_download_state_in=2'b10;//dc_rdy
mem_download_state_in=2'b01;//mem_busy
////////////////////////////////////////////////////////////
///////////5th case: mem rep and dc req come/////////////////
`clk_step
in_req_rdy=1'b1;
in_rep_rdy=1'b1;
req_ctrl_in=2'b01;
rep_ctrl_in=2'b01;
req_flit_in=16'hc0de;
rep_flit_in=16'hfed0;
ic_download_state_in=2'b00;//ic_idle
dc_download_state_in=2'b00;//dc_idle
mem_download_state_in=2'b00;//mem_idle
`clk_step
in_req_rdy=1'b1;
in_rep_rdy=1'b1;
req_ctrl_in=2'b10;
rep_ctrl_in=2'b10;
req_flit_in=16'hc1de;
rep_flit_in=16'hfed1;
ic_download_state_in=2'b00;//ic_idle
dc_download_state_in=2'b01;//dc_busy
mem_download_state_in=2'b01;//mem_busy
`clk_step
in_req_rdy=1'b1;
in_rep_rdy=1'b1;
req_ctrl_in=2'b10;
rep_ctrl_in=2'b10;
req_flit_in=16'hc2de;
rep_flit_in=16'hfed2;
ic_download_state_in=2'b00;//ic_idle
dc_download_state_in=2'b01;//dc_busy
mem_download_state_in=2'b01;//mem_busy
`clk_step
in_req_rdy=1'b1;
in_rep_rdy=1'b1;
req_ctrl_in=2'b11;
rep_ctrl_in=2'b10;
req_flit_in=16'hc3de;
rep_flit_in=16'hfed3;
ic_download_state_in=2'b00;//ic_idle
dc_download_state_in=2'b01;//dc_busy
mem_download_state_in=2'b01;//mem_busy
`clk_step
in_req_rdy=1'b1;
in_rep_rdy=1'b1;
req_ctrl_in=2'b01;
rep_ctrl_in=2'b11;
req_flit_in=16'hc0de;
rep_flit_in=16'hfed4;
ic_download_state_in=2'b00;//ic_idle
dc_download_state_in=2'b10;//dc_rdy
mem_download_state_in=2'b01;//mem_busy
////////////////////////////////////////////////////////////
///////////6th case:dc rep and dc req come!/////////////////
// both come and dc rep win
`clk_step
in_req_rdy=1'b1;
in_rep_rdy=1'b1;
req_ctrl_in=2'b01;
rep_ctrl_in=2'b01;
req_flit_in=16'hc0de;
rep_flit_in=16'hc0ef;
ic_download_state_in=2'b00;//ic_idle
dc_download_state_in=2'b00;//dc_idle
mem_download_state_in=2'b00;//mem_idle
`clk_step
in_req_rdy=1'b1;
in_rep_rdy=1'b1;
req_ctrl_in=2'b01;
rep_ctrl_in=2'b10;
req_flit_in=16'hc0de;
rep_flit_in=16'hc1ef;
ic_download_state_in=2'b00;//ic_idle
dc_download_state_in=2'b01;//dc_busy
mem_download_state_in=2'b01;//mem_idle
`clk_step
in_req_rdy=1'b1;
in_rep_rdy=1'b1;
req_ctrl_in=2'b01;
rep_ctrl_in=2'b10;
req_flit_in=16'hc0de;
rep_flit_in=16'hc2ef;
ic_download_state_in=2'b00;//ic_idle
dc_download_state_in=2'b01;//dc_busy
mem_download_state_in=2'b01;//mem_idle
`clk_step
in_req_rdy=1'b1;
in_rep_rdy=1'b1;
req_ctrl_in=2'b01;
rep_ctrl_in=2'b11;
req_flit_in=16'hc0de;
rep_flit_in=16'hc3ef;
ic_download_state_in=2'b00;//ic_idle
dc_download_state_in=2'b01;//dc_busy
mem_download_state_in=2'b01;//mem_idle
`clk_step
`clk_step
`clk_step
`clk_step
/////////////////////////////
//it's turn of dc req////////
in_req_rdy=1'b1;
in_rep_rdy=1'b0;
req_ctrl_in=2'b01;
rep_ctrl_in=2'b01;
req_flit_in=16'hc0de;
rep_flit_in=16'hc3ef;
ic_download_state_in=2'b00;//ic_idle
dc_download_state_in=2'b00;//dc_idle
mem_download_state_in=2'b00;//mem_idle
`clk_step
in_req_rdy=1'b1;
in_rep_rdy=1'b0;
req_ctrl_in=2'b10;
rep_ctrl_in=2'b01;
req_flit_in=16'hc1de;
rep_flit_in=16'hc3ef;
ic_download_state_in=2'b00;//ic_idle
dc_download_state_in=2'b01;//dc_busy
mem_download_state_in=2'b01;//mem_idle
`clk_step
in_req_rdy=1'b1;
in_rep_rdy=1'b0;
req_ctrl_in=2'b10;
rep_ctrl_in=2'b01;
req_flit_in=16'hc2de;
rep_flit_in=16'hc3ef;
ic_download_state_in=2'b00;//ic_idle
dc_download_state_in=2'b01;//dc_busy
mem_download_state_in=2'b01;//mem_idle
`clk_step
in_req_rdy=1'b1;
in_rep_rdy=1'b0;
req_ctrl_in=2'b11;
rep_ctrl_in=2'b01;
req_flit_in=16'hc2de;
rep_flit_in=16'hc4ef;
ic_download_state_in=2'b00;//ic_idle
dc_download_state_in=2'b01;//dc_busy
mem_download_state_in=2'b01;//mem_idle
//next cycle dc_rdy
////////////////////////////////////////////////////////////
///////////7th case:mem rep and mem req come////////////////
// both come and mem rep win
`clk_step
in_req_rdy=1'b1;
in_rep_rdy=1'b1;
req_ctrl_in=2'b01;
rep_ctrl_in=2'b01;
req_flit_in=16'hfed0;
rep_flit_in=16'hfeb0;
ic_download_state_in=2'b00;//ic_idle
dc_download_state_in=2'b00;//dc_idle
mem_download_state_in=2'b00;//mem_idle
`clk_step
in_req_rdy=1'b1;
in_rep_rdy=1'b1;
req_ctrl_in=2'b01;
rep_ctrl_in=2'b10;
req_flit_in=16'hfed0;
rep_flit_in=16'hfeb1;
ic_download_state_in=2'b00;//ic_idle
dc_download_state_in=2'b00;//dc_busy
mem_download_state_in=2'b01;//mem_idle
`clk_step
in_req_rdy=1'b1;
in_rep_rdy=1'b1;
req_ctrl_in=2'b01;
rep_ctrl_in=2'b10;
req_flit_in=16'hfed0;
rep_flit_in=16'hfeb2;
ic_download_state_in=2'b00;//ic_idle
dc_download_state_in=2'b00;//dc_busy
mem_download_state_in=2'b01;//mem_idle
`clk_step
in_req_rdy=1'b1;
in_rep_rdy=1'b1;
req_ctrl_in=2'b01;
rep_ctrl_in=2'b11;
req_flit_in=16'hfed0;
rep_flit_in=16'hfeb3;
ic_download_state_in=2'b00;//ic_idle
dc_download_state_in=2'b00;//dc_idle
mem_download_state_in=2'b01;//mem_busy
`clk_step
in_req_rdy=1'b1;
in_rep_rdy=1'b1;
req_ctrl_in=2'b01;
rep_ctrl_in=2'b01;
req_flit_in=16'hfed0;
rep_flit_in=16'hfeb3;
ic_download_state_in=2'b00;//ic_idle
dc_download_state_in=2'b00;//dc_idle
mem_download_state_in=2'b01;//mem_busy
`clk_step
`clk_step
`clk_step
/////////////////////////////
//it's turn of dc req////////
in_req_rdy=1'b1;
in_rep_rdy=1'b0;
req_ctrl_in=2'b01;
rep_ctrl_in=2'b01;
req_flit_in=16'hfed0;
rep_flit_in=16'hfeb3;
ic_download_state_in=2'b00;//ic_idle
dc_download_state_in=2'b00;//dc_idle
mem_download_state_in=2'b00;//mem_idle
`clk_step
in_req_rdy=1'b1;
in_rep_rdy=1'b0;
req_ctrl_in=2'b10;
rep_ctrl_in=2'b01;
req_flit_in=16'hfed1;
rep_flit_in=16'hfeb3;
ic_download_state_in=2'b00;//ic_idle
dc_download_state_in=2'b00;//dc_idle
mem_download_state_in=2'b01;//mem_busy
`clk_step
in_req_rdy=1'b1;
in_rep_rdy=1'b0;
req_ctrl_in=2'b10;
rep_ctrl_in=2'b01;
req_flit_in=16'hfed2;
rep_flit_in=16'hfeb3;
ic_download_state_in=2'b00;//ic_idle
dc_download_state_in=2'b01;//dc_idle
mem_download_state_in=2'b01;//mem_busy
`clk_step
in_req_rdy=1'b1;
in_rep_rdy=1'b0;
req_ctrl_in=2'b11;
rep_ctrl_in=2'b01;
req_flit_in=16'hfed3;
rep_flit_in=16'hfeb0;
ic_download_state_in=2'b00;//ic_idle
dc_download_state_in=2'b00;//dc_busy
mem_download_state_in=2'b01;//mem_busy
//mem will reject coming flit whatever kind
////////////////////////////////////////////////////////////
//////////8th case:only dc rep comes////////////////////////
`clk_step
in_req_rdy=1'b0;
in_rep_rdy=1'b1;
req_ctrl_in=2'b01;
rep_ctrl_in=2'b01;
req_flit_in=16'hc0de;
rep_flit_in=16'hc0ef;
ic_download_state_in=2'b00;//ic_idle
dc_download_state_in=2'b00;//dc_idle
mem_download_state_in=2'b00;//mem_idle
`clk_step
in_req_rdy=1'b0;
in_rep_rdy=1'b1;
req_ctrl_in=2'b01;
rep_ctrl_in=2'b10;
req_flit_in=16'hc0de;
rep_flit_in=16'hc1ef;
ic_download_state_in=2'b00;//ic_idle
dc_download_state_in=2'b01;//dc_busy
mem_download_state_in=2'b01;//mem_idle
`clk_step
in_req_rdy=1'b0;
in_rep_rdy=1'b1;
req_ctrl_in=2'b01;
rep_ctrl_in=2'b10;
req_flit_in=16'hc0de;
rep_flit_in=16'hc2ef;
ic_download_state_in=2'b00;//ic_idle
dc_download_state_in=2'b01;//dc_busy
mem_download_state_in=2'b01;//mem_idle
`clk_step
in_req_rdy=1'b0;
in_rep_rdy=1'b1;
req_ctrl_in=2'b01;
rep_ctrl_in=2'b11;
req_flit_in=16'hc0de;
rep_flit_in=16'hc3ef;
ic_download_state_in=2'b00;//ic_idle
dc_download_state_in=2'b01;//dc_busy
mem_download_state_in=2'b01;//mem_idle
////////////////////////////////////////////////////////////
///////////9th case:only dc req come////////////////////////
`clk_step
in_req_rdy=1'b1;
in_rep_rdy=1'b0;
req_ctrl_in=2'b01;
rep_ctrl_in=2'b01;
req_flit_in=16'hc0de;
rep_flit_in=16'hc0ef;
ic_download_state_in=2'b00;//ic_idle
dc_download_state_in=2'b00;//dc_idle
mem_download_state_in=2'b00;//mem_idle
`clk_step
in_req_rdy=1'b1;
in_rep_rdy=1'b0;
req_ctrl_in=2'b01;
rep_ctrl_in=2'b10;
req_flit_in=16'hc0de;
rep_flit_in=16'hc1ef;
ic_download_state_in=2'b00;//ic_idle
dc_download_state_in=2'b01;//dc_busy
mem_download_state_in=2'b01;//mem_idle
`clk_step
in_req_rdy=1'b1;
in_rep_rdy=1'b0;
req_ctrl_in=2'b01;
rep_ctrl_in=2'b10;
req_flit_in=16'hc0de;
rep_flit_in=16'hc2ef;
ic_download_state_in=2'b00;//ic_idle
dc_download_state_in=2'b01;//dc_busy
mem_download_state_in=2'b01;//mem_idle
`clk_step
in_req_rdy=1'b1;
in_rep_rdy=1'b0;
req_ctrl_in=2'b01;
rep_ctrl_in=2'b11;
req_flit_in=16'hc0de;
rep_flit_in=16'hc3ef;
ic_download_state_in=2'b00;//ic_idle
dc_download_state_in=2'b01;//dc_busy
mem_download_state_in=2'b01;//mem_idle
////////////////////////////////////////////////////////////
///////////10th case:only mem rep comes/////////////////////
`clk_step
in_req_rdy=1'b0;
in_rep_rdy=1'b1;
req_ctrl_in=2'b01;
rep_ctrl_in=2'b01;
req_flit_in=16'hfed0;
rep_flit_in=16'hfeb0;
ic_download_state_in=2'b00;//ic_idle
dc_download_state_in=2'b00;//dc_idle
mem_download_state_in=2'b00;//mem_idle
`clk_step
in_req_rdy=1'b0;
in_rep_rdy=1'b1;
req_ctrl_in=2'b01;
rep_ctrl_in=2'b10;
req_flit_in=16'hfed0;
rep_flit_in=16'hfeb1;
ic_download_state_in=2'b00;//ic_idle
dc_download_state_in=2'b00;//dc_busy
mem_download_state_in=2'b01;//mem_idle
`clk_step
in_req_rdy=1'b0;
in_rep_rdy=1'b1;
req_ctrl_in=2'b01;
rep_ctrl_in=2'b10;
req_flit_in=16'hfed0;
rep_flit_in=16'hfeb2;
ic_download_state_in=2'b00;//ic_idle
dc_download_state_in=2'b00;//dc_busy
mem_download_state_in=2'b01;//mem_idle
`clk_step
in_req_rdy=1'b0;
in_rep_rdy=1'b1;
req_ctrl_in=2'b01;
rep_ctrl_in=2'b11;
req_flit_in=16'hfed0;
rep_flit_in=16'hfeb3;
ic_download_state_in=2'b00;//ic_idle
dc_download_state_in=2'b00;//dc_idle
mem_download_state_in=2'b01;//mem_busy
`clk_step
in_req_rdy=1'b0;
in_rep_rdy=1'b1;
req_ctrl_in=2'b01;
rep_ctrl_in=2'b01;
req_flit_in=16'hfed0;
rep_flit_in=16'hfeb3;
ic_download_state_in=2'b00;//ic_idle
dc_download_state_in=2'b00;//dc_idle
mem_download_state_in=2'b01;//mem_busy
////////////////////////////////////////////////////////////
////////////11th case: only mem req comes //////////////////
`clk_step
in_req_rdy=1'b1;
in_rep_rdy=1'b0;
req_ctrl_in=2'b01;
rep_ctrl_in=2'b01;
req_flit_in=16'hfed0;
rep_flit_in=16'hfeb0;
ic_download_state_in=2'b00;//ic_idle
dc_download_state_in=2'b00;//dc_idle
mem_download_state_in=2'b00;//mem_idle
`clk_step
in_req_rdy=1'b1;
in_rep_rdy=1'b0;
req_ctrl_in=2'b01;
rep_ctrl_in=2'b10;
req_flit_in=16'hfed0;
rep_flit_in=16'hfeb1;
ic_download_state_in=2'b00;//ic_idle
dc_download_state_in=2'b00;//dc_busy
mem_download_state_in=2'b01;//mem_idle
`clk_step
in_req_rdy=1'b1;
in_rep_rdy=1'b0;
req_ctrl_in=2'b01;
rep_ctrl_in=2'b10;
req_flit_in=16'hfed0;
rep_flit_in=16'hfeb2;
ic_download_state_in=2'b00;//ic_idle
dc_download_state_in=2'b00;//dc_busy
mem_download_state_in=2'b01;//mem_idle
`clk_step
in_req_rdy=1'b1;
in_rep_rdy=1'b0;
req_ctrl_in=2'b01;
rep_ctrl_in=2'b11;
req_flit_in=16'hfed0;
rep_flit_in=16'hfeb3;
ic_download_state_in=2'b00;//ic_idle
dc_download_state_in=2'b00;//dc_idle
mem_download_state_in=2'b01;//mem_busy
`clk_step
in_req_rdy=1'b1;
in_rep_rdy=1'b0;
req_ctrl_in=2'b01;
rep_ctrl_in=2'b01;
req_flit_in=16'hfed0;
rep_flit_in=16'hfeb3;
ic_download_state_in=2'b00;//ic_idle
dc_download_state_in=2'b00;//dc_idle
mem_download_state_in=2'b01;//mem_busy
////////////////////////////////////////////////////////////
/////////////12th case: nothing comes///////////////////////
`clk_step
in_req_rdy=1'b0;
in_rep_rdy=1'b0;
req_ctrl_in=2'b01;
rep_ctrl_in=2'b01;
req_flit_in=16'hfed0;
rep_flit_in=16'hfeb0;
ic_download_state_in=2'b00;//ic_idle
dc_download_state_in=2'b00;//dc_idle
mem_download_state_in=2'b00;//mem_idle
`clk_step
in_req_rdy=1'b0;
in_rep_rdy=1'b0;
req_ctrl_in=2'b01;
rep_ctrl_in=2'b10;
req_flit_in=16'hfed0;
rep_flit_in=16'hfeb1;
ic_download_state_in=2'b00;//ic_idle
dc_download_state_in=2'b00;//dc_busy
mem_download_state_in=2'b01;//mem_idle
`clk_step
in_req_rdy=1'b0;
in_rep_rdy=1'b0;
req_ctrl_in=2'b01;
rep_ctrl_in=2'b10;
req_flit_in=16'hfed0;
rep_flit_in=16'hfeb2;
ic_download_state_in=2'b00;//ic_idle
dc_download_state_in=2'b00;//dc_busy
mem_download_state_in=2'b01;//mem_idle
`clk_step
in_req_rdy=1'b0;
in_rep_rdy=1'b0;
req_ctrl_in=2'b01;
rep_ctrl_in=2'b11;
req_flit_in=16'hfed0;
rep_flit_in=16'hfeb3;
ic_download_state_in=2'b00;//ic_idle
dc_download_state_in=2'b00;//dc_idle
mem_download_state_in=2'b01;//mem_busy
`clk_step
in_req_rdy=1'b0;
in_rep_rdy=1'b0;
req_ctrl_in=2'b01;
rep_ctrl_in=2'b01;
req_flit_in=16'hfed0;
rep_flit_in=16'hfeb3;
ic_download_state_in=2'b00;//ic_idle
dc_download_state_in=2'b00;//dc_idle
mem_download_state_in=2'b01;//mem_busy
`clk_step
$display("FINISH TEST!");
$fdisplay(log_file,"FINISH TEST!");
$stop;
end
endmodule
|
module agnus_blitter
(
input clk, // bus clock
input clk7_en,
input reset, // reset
input ecs, // enable ECS extensions
input clkena, // enables blitter operation (used to slow it down)
input enadma, // no other dma channel is granted the bus
output reqdma, // blitter requests dma cycle
input ackdma, // agnus dma priority logic grants dma cycle
output we, // write enable (blitter writes to memory)
output reg zero, // blitter zero status
output reg busy, // blitter busy status
output int3, // blitter finish interrupt request
input [15:0] data_in, // bus data in
output [15:0] data_out, // bus data out
input [8:1] reg_address_in, // register address inputs
output [20:1] address_out, // chip address outputs
output reg [8:1] reg_address_out // register address outputs
);
//register names and adresses
parameter BLTCON0 = 9'h040;
parameter BLTCON0L = 9'h05A;
parameter BLTCON1 = 9'h042;
parameter BLTAFWM = 9'h044;
parameter BLTALWM = 9'h046;
parameter BLTADAT = 9'h074;
parameter BLTBDAT = 9'h072;
parameter BLTCDAT = 9'h070;
parameter BLTDDAT = 9'h000;
parameter BLTSIZE = 9'h058;
parameter BLTSIZH = 9'h05E;
parameter BLTSIZV = 9'h05C;
//channel select codes
parameter CHA = 2'b10; // channel A
parameter CHB = 2'b01; // channel B
parameter CHC = 2'b00; // channel C
parameter CHD = 2'b11; // channel D
parameter BLT_IDLE = 5'b00000;
parameter BLT_INIT = 5'b00001;
parameter BLT_A = 5'b01001;
parameter BLT_B = 5'b01011;
parameter BLT_C = 5'b01010;
parameter BLT_D = 5'b01000;
parameter BLT_E = 5'b01100;
parameter BLT_F = 5'b00100;
parameter BLT_L1 = 5'b11001;
parameter BLT_L2 = 5'b11011;
parameter BLT_L3 = 5'b11010;
parameter BLT_L4 = 5'b11000;
//local signals
reg [15:0] bltcon0; // blitter control register 0
wire [3:0] ash; // bltcon0 aliases
wire usea;
wire useb;
wire usec;
wire used;
reg enad; // do not disable D channel
reg [15:0] bltcon1; // blitter control register 1
wire [3:0] bsh; // bltcon1 aliases
wire desc; // enable descending mode (and not line mode)
wire line; // enable line mode
wire ife; // enable inclusive fill mode
wire efe; // enable exclusive fill mode
reg [15:0] bltafwm; // blitter first word mask for source A
reg [15:0] bltalwm; // blitter last word mask for source A
reg [15:0] bltadat; // blitter source A data register
reg [15:0] bltbdat; // blitter source B data register
reg [15:0] bltcdat; // blitter source C data register
reg [15:0] bltaold; // blitter source A 'old' data
reg [15:0] bltbold; // blitter source B 'old' data
reg [15:0] bltahold; // A holding register
reg [15:0] bltbhold; // B holding register
reg [15:0] bltdhold; // D holding register
reg [10:0] width; // blitsize number of words (width)
reg [14:0] height; // blitsize number of lines (height)
reg [4:0] blt_state; // blitter state
reg [4:0] blt_next; // blitter next state
wire enable; // blit cycle enable signal
reg [1:0] chsel; // channel selection - affects register bus address during DMA transactions
reg [1:0] ptrsel; // pointer selection - DMA memory bus address
reg [1:0] modsel; // modulo selection (blitter is a little bit weird in line mode0
reg enaptr; // enable selected pointer
reg incptr; // increment selected pointer
reg decptr; // decrement selected pointer
reg addmod; // add selected modulo
reg submod; // substract selected modulo
wire incash; // increment ASH (line mode)
wire decash; // decrement ASH (line mode)
wire decbsh; // decrement BSH (line mode)
wire sign_out; // new accumulator sign calculated by address generator (line mode)
reg sign; // current sign of accumulator (line mode)
reg sign_del;
reg first_pixel; // first pixel in a horizontal segment (used in one-dot line mode)
reg first_line_pixel; // first pixel of line (use D pointer)
reg start; // busy delayed by one blitter cycle (for cycle exact compatibility)
wire init; // blitter initialization cycle
wire next_word; // indicates last cycle of a single sequence
reg store_result; // updates D hold register
reg pipeline_full; // indicated update of D holding register
wire first_word; // first word of a line
reg first_word_del; // delayed signal for use in fill mode (initial fill carry selection)
wire last_word; // last word of a line
reg last_word_del; // delayed signal for adding modulo to D channel pointer register
wire last_line; // last line of the blit
wire done; // indicates the end of the blit (clears busy)
wire [15:0] minterm_out; // minterm generator output
wire [15:0] fill_out; // fill logic output
wire fci; // fill carry in
wire fco; // fill carry out
reg fcy; // fill carry latch (for the next word)
reg [10:0] width_cnt; // blitter width counter (in words)
wire width_cnt_dec; // decrement width counter
wire width_cnt_rld; // reload width counter
reg [14:0] height_cnt; // blitter height counter (in lines)
reg [15:0] bltamask;
wire [15:0] shiftaout;
wire [15:0] shiftbout;
reg dma_req;
wire dma_ack;
//--------------------------------------------------------------------------------------
//bltcon0: ASH part
always @(posedge clk)
if (clk7_en) begin
if (reset)
bltcon0[15:12] <= 0;
else if (enable && incash) // increment ash (line mode)
bltcon0[15:12] <= bltcon0[15:12] + 4'b0001;
else if (enable && decash) // decrement ash (line mode)
bltcon0[15:12] <= bltcon0[15:12] - 4'b0001;
else if (reg_address_in[8:1]==BLTCON0[8:1])
bltcon0[15:12] <= data_in[15:12];
end
assign ash[3:0] = bltcon0[15:12];
//bltcon0: USE part
always @(posedge clk)
if (clk7_en) begin
if (reset)
bltcon0[11:8] <= 0;
else if (reg_address_in[8:1]==BLTCON0[8:1])
bltcon0[11:8] <= data_in[11:8];
end
// writing blitcon0 while a blit is active disables D channel (not always but it's very likely)
always @(posedge clk)
if (clk7_en) begin
if (init)
enad <= 1'b1;
else if (reg_address_in[8:1]==BLTCON0[8:1] && busy)
enad <= 1'b0;
end
assign {usea, useb, usec, used} = {bltcon0[11:9], bltcon0[8] & enad}; // DMA channels enable
//bltcon0: LF part
always @(posedge clk)
if (clk7_en) begin
if (reset)
bltcon0[7:0] <= 0;
else if (reg_address_in[8:1]==BLTCON0[8:1] || reg_address_in[8:1]==BLTCON0L[8:1] && ecs)
bltcon0[7:0] <= data_in[7:0];
end
//bltcon1: BSH part
always @(posedge clk)
if (clk7_en) begin
if (reset)
bltcon1[15:12] <= 0;
else if (enable && decbsh) // decrement bsh (line mode - texturing)
bltcon1[15:12] <= bltcon1[15:12] - 4'b0001;
else if (reg_address_in[8:1]==BLTCON1[8:1])
bltcon1[15:12] <= data_in[15:12];
end
assign bsh[3:0] = bltcon1[15:12];
//bltcon1: the rest
always @(posedge clk)
if (clk7_en) begin
if (reset)
bltcon1[11:0] <= 0;
else if (reg_address_in[8:1]==BLTCON1[8:1])
bltcon1[11:0] <= data_in[11:0];
end
assign line = bltcon1[0]; // line mode
assign desc = ~line & bltcon1[1]; // descending blit mode
assign efe = ~line & bltcon1[4]; // exclusive fill mode
assign ife = ~line & bltcon1[3]; // inclusive fill mode
//--------------------------------------------------------------------------------------
//bltafwm register (first word mask for channel A)
always @(posedge clk)
if (clk7_en) begin
if (reset)
bltafwm[15:0] <= 0;
else if (reg_address_in[8:1]==BLTAFWM[8:1])
bltafwm[15:0] <= data_in[15:0];
end
//bltalwm register (last word mask for channel A)
always @(posedge clk)
if (clk7_en) begin
if (reset)
bltalwm[15:0] <= 0;
else if (reg_address_in[8:1]==BLTALWM[8:1])
bltalwm[15:0] <= data_in[15:0];
end
//channel A mask select
always @(*)
if (first_word && last_word)
bltamask[15:0] = bltafwm[15:0] & bltalwm[15:0];
else if (first_word)
bltamask[15:0] = bltafwm[15:0];
else if (last_word)
bltamask[15:0] = bltalwm[15:0];
else
bltamask[15:0] = 16'hFF_FF;
//bltadat register
always @(posedge clk)
if (clk7_en) begin
if (reset)
bltadat[15:0] <= 0;
else if (reg_address_in[8:1]==BLTADAT[8:1])
bltadat[15:0] <= data_in[15:0];
end
//channel A 'old' register
always @(posedge clk)
if (clk7_en) begin
if (enable)
if (init)
bltaold[15:0] <= 0;
else if (next_word && !line) // in line mode this register is equal zero all the time
bltaold[15:0] <= bltadat[15:0] & bltamask[15:0];
end
//channel A barrel shifter
agnus_blitter_barrelshifter barrel_shifter_A
(
.desc(desc),
.shift(ash),
.new_val(bltadat & bltamask),
.old_val(bltaold),
.out(shiftaout)
);
//channel A holding register
always @(posedge clk)
if (clk7_en) begin
if (enable)
bltahold[15:0] <= shiftaout[15:0];
end
//--------------------------------------------------------------------------------------
//bltbdat register
always @(posedge clk)
if (clk7_en) begin
if (reset)
bltbdat[15:0] <= 0;
else if (reg_address_in[8:1]==BLTBDAT[8:1])
bltbdat[15:0] <= data_in[15:0];
end
reg bltbold_init;
always @(posedge clk)
if (clk7_en) begin
if (reset || done)
bltbold_init <= 1'b1;
else if (reg_address_in[8:1]==BLTBDAT[8:1])
bltbold_init <= 1'b0;
end
//channel B 'old' register
always @(posedge clk)
if (clk7_en) begin
if (reg_address_in[8:1]==BLTBDAT[8:1])
if (bltbold_init)
bltbold[15:0] <= 0;
else
bltbold[15:0] <= bltbdat[15:0];
end
reg bltbdat_wrtn;
always @(posedge clk)
if (clk7_en) begin
if (reg_address_in[8:1]==BLTBDAT[8:1])
bltbdat_wrtn <= 1'b1;
else
bltbdat_wrtn <= 1'b0;
end
//channel B barrel shifter
agnus_blitter_barrelshifter barrel_shifter_B
(
.desc(desc),
.shift(bsh),
.new_val(bltbdat),
.old_val(bltbold),
.out(shiftbout)
);
//channel B holding register
always @(posedge clk)
if (clk7_en) begin
if (line)
bltbhold[15:0] <= {16{shiftbout[0]}}; // in line mode only one selected bit of BLTBDAT register (LSB) is used for texturing
else if (bltbdat_wrtn)
bltbhold[15:0] <= shiftbout[15:0];
end
//--------------------------------------------------------------------------------------
//bltcdat register
always @(posedge clk)
if (clk7_en) begin
if (reg_address_in[8:1]==BLTCDAT[8:1])
bltcdat[15:0] <= data_in[15:0];
end
//--------------------------------------------------------------------------------------
always @(posedge clk)
if (clk7_en) begin
if (next_word && enable)
last_word_del <= last_word;
end
always @(posedge clk)
if (clk7_en) begin
if (next_word && enable)
first_word_del <= first_word; // used in fill mode for selecting initial fci state
end
//--------------------------------------------------------------------------------------
//minterm generator instantation
agnus_blitter_minterm bltmt1
(
.lf(bltcon0[7:0]),
.ain(bltahold[15:0]),
.bin(bltbhold[15:0]),
.cin(bltcdat[15:0]),
.out(minterm_out[15:0])
);
//fill logic instantiation
agnus_blitter_fill bltfl1
(
.ife(ife),
.efe(efe),
.fci(fci),
.fco(fco),
.in(minterm_out[15:0]),
.out(fill_out[15:0])
);
//fill carry input
assign fci = first_word_del ? bltcon1[2] : fcy;
// carry out latch (updated at the same time as channel D holding register)
always @(posedge clk)
if (clk7_en) begin
if (store_result)
fcy <= fco;
end
// channel D holding register (updated one cycle later after a write to other holding registers)
always @(posedge clk)
if (clk7_en) begin
if (store_result)
bltdhold[15:0] <= fill_out[15:0];
end
// channel D 'zero' flag
always @(posedge clk)
if (clk7_en) begin
if (reset)
zero <= 1;
else if (enable && init)
zero <= 1;
else if (store_result && |fill_out[15:0])
zero <= 0;
end
//channel D data output
assign data_out[15:0] = ackdma && chsel[1:0]==CHD ? bltdhold[15:0] : 16'h00_00;
assign we = ackdma && chsel[1:0]==CHD ? 1'b1 : 1'b0;
//--------------------------------------------------------------------------------------
// 'busy' flag control
always @(posedge clk)
if (clk7_en) begin
if (reset)
busy <= 0;
else if (reg_address_in[8:1]==BLTSIZE[8:1] || reg_address_in[8:1]==BLTSIZH[8:1] && ecs) // set immediately after a write to BLTSIZE or BLTSIZH (ECS)
busy <= 1;
else if (done) // cleared when the blit is done
busy <= 0;
end
// blitter finish interrupt request
assign int3 = done;
// FSM start control (one bus clock cycle delay for cycle exact compatibility)
always @(posedge clk)
if (clk7_en) begin
if (reset || done)
start <= 0;
else if (clkena && busy)
start <= 1;
end
// blit width register (backup)
always @(posedge clk)
if (clk7_en) begin
if (reg_address_in[8:1]==BLTSIZE[8:1]) // OCS
width[10:0] <= {4'b0000, ~|data_in[5:0], data_in[5:0]};
else if (reg_address_in[8:1]==BLTSIZH[8:1] && ecs) // ECS
width[10:0] <= data_in[10:0];
end
assign width_cnt_dec = enable & next_word;
assign width_cnt_rld = enable & next_word & last_word | init & enable;
// blit width counter
always @(posedge clk)
if (clk7_en) begin
if (width_cnt_rld) // reload counter
width_cnt[10:0] <= width[10:0];
else if (width_cnt_dec) // decrement counter
width_cnt[10:0] <= width_cnt[10:0] - 1'b1;
end
assign last_word = width_cnt[10:0]==1 ? 1'b1 : 1'b0;
assign first_word = width_cnt[10:0]==width[10:0] ? 1'b1 : 1'b0;
assign last_line = height_cnt[14:0]==1 ? 1'b1 : 1'b0;
// ECS large blit height holding register
always @(posedge clk)
if (clk7_en) begin
if (reset)
height[14:0] <= 0;
else if (reg_address_in[8:1]==BLTSIZV[8:1]) // ECS BLTSIZV register
height[14:0] <= data_in[14:0];
end
// blit height counter
always @(posedge clk)
if (clk7_en) begin
if (reg_address_in[8:1]==BLTSIZE[8:1]) // OCS
height_cnt[14:0] <= {4'b0000, ~|data_in[15:6], data_in[15:6]};
else if (reg_address_in[8:1]==BLTSIZH[8:1] && ecs) // ECS
height_cnt[14:0] <= height[14:0];
else if (enable && next_word && last_word) // decrement height counter
height_cnt[14:0] <= height_cnt[14:0] - 1'b1;
end
// pipeline is full (first set of sources has been fetched)
always @(posedge clk)
if (clk7_en) begin
if (enable)
if (init)
pipeline_full <= 0;
else if (next_word)
pipeline_full <= 1;
end
//--------------------------------------------------------------------------------------
// instantiate address generation unit
agnus_blitter_adrgen address_generator_1
(
.clk(clk),
.clk7_en(clk7_en),
.reset(reset),
.first_line_pixel(line && first_line_pixel),
.ptrsel(ptrsel),
.modsel(modsel),
.enaptr(enaptr),
.incptr(incptr),
.decptr(decptr),
.addmod(addmod),
.submod(submod),
.sign_out(sign_out),
.data_in(data_in),
.reg_address_in(reg_address_in),
.address_out(address_out)
);
// custom register address output
always @(*)
case (chsel)
CHA : reg_address_out = BLTADAT[8:1];
CHB : reg_address_out = BLTBDAT[8:1];
CHC : reg_address_out = BLTCDAT[8:1];
CHD : reg_address_out = BLTDDAT[8:1];
endcase
//--------------------------------------------------------------------------------------
assign enable = enadma & clkena;
assign reqdma = dma_req & enable;
assign dma_ack = ackdma;
// blitter FSM
always @(posedge clk)
if (clk7_en) begin
if (reset)
blt_state <= BLT_IDLE;
else
blt_state <= blt_next;
end
always @(*)
case (blt_state)
BLT_IDLE:
begin
chsel = 2'bXX;
ptrsel = 2'bXX;
modsel = 2'bXX;
enaptr = 1'b0;
incptr = 1'bX;
decptr = 1'bX;
addmod = 1'bX;
submod = 1'bX;
dma_req = 1'b0;
if (enable)
if (start)
blt_next = BLT_INIT;
else
blt_next = BLT_IDLE;
else
blt_next = BLT_IDLE;
end
BLT_INIT:
begin
chsel = 2'bXX;
ptrsel = 2'bXX;
modsel = 2'bXX;
enaptr = 1'b0;
incptr = 1'bX;
decptr = 1'bX;
addmod = 1'bX;
submod = 1'bX;
dma_req = 1'b0;
if (enable)
if (line)
blt_next = BLT_L1; // go to first line draw cycle
else
blt_next = BLT_A;
else
blt_next = BLT_INIT;
end
BLT_A: // first blit cycle (channel A source data fetch or empty cycle)
begin
chsel = CHA;
ptrsel = CHA;
modsel = CHA;
enaptr = dma_ack;
incptr = ~desc;
decptr = desc;
addmod = ~desc & last_word; // add or substract modulo when last word in a line is fetched
submod = desc & last_word;
dma_req = usea; // empty cycle if channel A is not enabled
if (enable)
if (useb)
blt_next = BLT_B;
else if (usec || ife || efe) // in fill modes channel C cycle is always used (might be empty if channel C is not enabled)
blt_next = BLT_C;
else
blt_next = BLT_D;
else
blt_next = BLT_A;
end
BLT_B: // second blit cycle (always channel B fetch - if channel B is not enabled this cycle is skipped)
begin
chsel = CHB;
ptrsel = CHB;
modsel = CHB;
enaptr = dma_ack;
incptr = ~desc;
decptr = desc;
addmod = ~desc & last_word;
submod = desc & last_word;
dma_req = 1'b1; // we can only reach this state if channel B is enabled (USEB is set)
if (enable)
if (usec || ife || efe) // in fill modes channel C cycle is always used (might be empty if channel C is not enabled)
blt_next = BLT_C;
else
blt_next = BLT_D;
else
blt_next = BLT_B;
end
BLT_C:
begin
chsel = CHC;
ptrsel = CHC;
modsel = CHC;
enaptr = dma_ack;
incptr = ~desc;
decptr = desc;
addmod = ~desc & last_word;
submod = desc & last_word;
dma_req = usec; // channel C is enabled when USEC is set - in fill mode empty cycle if not enabled
if (enable)
if (used)
blt_next = BLT_D;
else if (last_word && last_line)
blt_next = BLT_IDLE;
else
blt_next = BLT_A;
else
blt_next = BLT_C;
end
BLT_D:
begin
chsel = CHD;
ptrsel = CHD;
modsel = CHD;
enaptr = dma_ack;
incptr = ~desc;
decptr = desc;
addmod = ~desc & last_word_del;
submod = desc & last_word_del;
dma_req = used & pipeline_full; // request DMA cycle if channel D holding register is full
if (enable)
if (last_word && last_line)
if (used)
blt_next = BLT_E; // if last data store cycle go to the first pipeline flush state
else
blt_next = BLT_IDLE; // if D channel is not used go to IDLE state
else
blt_next = BLT_A;
else
blt_next = BLT_D;
end
BLT_E: // empty cycle to allow data propagation through D hold register
begin
chsel = 2'bXX;
ptrsel = 2'bXX;
modsel = 2'bXX;
enaptr = 1'b0;
incptr = 1'bX;
decptr = 1'bX;
addmod = 1'bX;
submod = 1'bX;
dma_req = 1'b0;
if (clkena)
blt_next = BLT_F; // go to the last D hold register store cycle
else
blt_next = BLT_E;
end
BLT_F: // flush pipeline (store the last D hold register value)
begin
chsel = CHD;
ptrsel = CHD;
modsel = CHD;
enaptr = dma_ack;
incptr = ~desc;
decptr = desc;
addmod = ~desc & last_word_del;
submod = desc & last_word_del;
dma_req = 1'b1; // request DMA cycle (D holding register is full)
if (enable)
blt_next = BLT_IDLE; // it's the last cycle so go to IDLE state
else
blt_next = BLT_F;
end
BLT_L1: // update error accumulator
begin
chsel = CHA;
ptrsel = CHA;
modsel = sign ? CHB : CHA;
enaptr = enable;
incptr = 0;
decptr = 0;
addmod = 1;//pipeline_full; // update error accumulator
submod = 0;
dma_req = 0; // internal cycle - no DMA access
if (enable)
blt_next = BLT_L2;
else
blt_next = BLT_L1;
end
BLT_L2: // fetch source data from channel C
begin
chsel = CHC;
ptrsel = CHC;
modsel = CHC;
enaptr = enable; // no pointer increment
incptr = 0;
decptr = 0;
addmod = 0;
submod = 0;
dma_req = usec;
if (enable)
blt_next = BLT_L3;
else
blt_next = BLT_L2;
end
BLT_L3: // free cycle (data propagates from source holding registers to channel D hold register - no pipelining)
begin
chsel = CHA;
ptrsel = CHA;
modsel = CHA;
enaptr = 0;
incptr = 0;
decptr = 0;
addmod = 0;
submod = 0;
dma_req = 0;
if (enable)
blt_next = BLT_L4;
else
blt_next = BLT_L3;
end
BLT_L4: // store cycle - initial write @ D ptr, all succesive @ C ptr, always modulo C used
begin
chsel = CHD;
ptrsel = CHC;
modsel = CHC;
enaptr = enable;
incptr = (bltcon1[4] && !bltcon1[2] || !bltcon1[4] && !bltcon1[3] && !sign_del) && ash==4'b1111 ? 1'b1 : 1'b0;
decptr = (bltcon1[4] && bltcon1[2] || !bltcon1[4] && bltcon1[3] && !sign_del) && ash==4'b0000 ? 1'b1 : 1'b0;
addmod = !bltcon1[4] && !bltcon1[2] || bltcon1[4] && !bltcon1[3] && !sign_del ? 1'b1 : 1'b0;
submod = !bltcon1[4] && bltcon1[2] || bltcon1[4] && bltcon1[3] && !sign_del ? 1'b1 : 1'b0;
// in 'one dot' mode this might be a free bus cycle
dma_req = usec & (~bltcon1[1] | ~bltcon1[4] | first_pixel); // request DMA cycle
if (enable)
if (last_line) // if last data store go to idle state
blt_next = BLT_IDLE;
else
blt_next = BLT_L1;
else
blt_next = BLT_L4;
end
default:
begin
chsel = CHA;
ptrsel = 2'bXX;
modsel = 2'bXX;
enaptr = 0;
incptr = 0;
decptr = 0;
addmod = 0;
submod = 0;
dma_req = 0;
blt_next = BLT_IDLE;
end
endcase
// init blitter pipeline (reload height counter)
assign init = blt_state==BLT_INIT ? 1'b1 : 1'b0;
// indicates last cycle of a single sequence
assign next_word = blt_state==BLT_C && !used || blt_state==BLT_D || blt_state==BLT_L2 || blt_state==BLT_L4 ? 1'b1 : 1'b0;
// stores a new value to D hold register
always @(posedge clk)
if (clk7_en) begin
if (reset)
store_result <= 0;
else
store_result <= enable && next_word;
end
// blitter busy flag is cleared immediately after last source data is fetched (if D channel is not enabled) or the last but one result is stored
// signal 'done' is used to clear the 'busy' and 'start' flags
//assign done = (blt_state==BLT_C && !used || blt_state==BLT_D) && last_word && last_line || blt_state==BLT_L4 && last_line ? enable : 1'b0;
// This is temporary solution. Needs further investigation. With heavy display load and 060 CPU an ISR could run before the last pipelined data write.
assign done = (blt_state==BLT_C || blt_state==BLT_D) && !used && last_word && last_line || blt_state==BLT_F || blt_state==BLT_L4 && last_line ? enable : 1'b0;
always @(posedge clk)
if (clk7_en) begin
if (enable)
if (blt_state==BLT_INIT)
first_pixel <= 1'b1;
else if (blt_state==BLT_L4)
first_pixel <= ~sign_del;
end
always @ (posedge clk) begin
if (clk7_en) begin
if (reset) begin
first_line_pixel <= #1 1'b0;
end else if (enable) begin
if (blt_state == BLT_INIT)
first_line_pixel <= #1 1'b1;
else if (blt_state == BLT_L4)
first_line_pixel <= #1 1'b0;
end
end
end
always @(posedge clk)
if (clk7_en) begin
if (reg_address_in[8:1]==BLTCON1[8:1])
sign <= data_in[6]; // initial sign value
else if (enable && blt_state==BLT_L1)
sign <= sign_out; // latch sign output from error accumulator
end
always @(posedge clk)
if (clk7_en) begin
if (enable && blt_state==BLT_L1)
sign_del <= sign;
end
assign incash = enable && blt_state==BLT_L4 && (bltcon1[4] && !bltcon1[2] || !bltcon1[4] && !bltcon1[3] && !sign_del) ? 1'b1 : 1'b0;
assign decash = enable && blt_state==BLT_L4 && (bltcon1[4] && bltcon1[2] || !bltcon1[4] && bltcon1[3] && !sign_del) ? 1'b1 : 1'b0;
assign decbsh = enable && blt_state==BLT_L4 ? 1'b1 : 1'b0;
//--------------------------------------------------------------------------------------
endmodule
|
module pc2(
input [0:55] cd,
output [0:47] k
);
assign k = {cd[13], cd[16], cd[10], cd[23], cd[0], cd[4], cd[2], cd[27], cd[14], cd[5], cd[20], cd[9], cd[22], cd[18], cd[11], cd[3], cd[25], cd[7], cd[15], cd[6], cd[26], cd[19], cd[12], cd[1], cd[40], cd[51], cd[30], cd[36], cd[46], cd[54], cd[29], cd[39], cd[50], cd[44], cd[32], cd[47], cd[43], cd[48], cd[38], cd[55], cd[33], cd[52], cd[45], cd[41], cd[49], cd[35], cd[28], cd[31]};
endmodule
|
module header
// Internal signals
//
// Generated Signal List
//
wire sig_01;
wire sig_03;
wire sig_04;
wire [3:0] sig_05;
wire [3:0] sig_06;
wire [5:0] sig_07;
wire [8:2] sig_08;
wire [4:0] sig_13;
//
// End of Generated Signal List
//
// %COMPILER_OPTS%
// Generated Signal Assignments
//
// Generated Instances
// wiring ...
// Generated Instances and Port Mappings
// Generated Instance Port Map for inst_a
ent_a inst_a (
.p_mix_sig_01_go(sig_01), // Use internally test1Will create p_mix_sig_1_go port
.p_mix_sig_03_go(sig_03), // Interhierachy link, will create p_mix_sig_3_go
.p_mix_sig_04_gi(sig_04), // Interhierachy link, will create p_mix_sig_4_gi
.p_mix_sig_05_2_1_go(sig_05[2:1]), // Bus, single bits go to outsideBus, single bits go to outside, will create p_mix_sig_5_2_2_goBu...
.p_mix_sig_06_gi(sig_06), // Conflicting definition (X2)
.p_mix_sig_i_ae_gi(sig_i_ae), // Input Bus
.p_mix_sig_o_ae_go(sig_o_ae), // Output Bus
.port_i_a(sig_i_a), // Input Port
.port_o_a(sig_o_a), // Output Port
.sig_07(sig_07), // Conflicting definition, IN false!
.sig_08(sig_08), // VHDL intermediate needed (port name)
.sig_13(sig_13), // Create internal signal name
.sig_i_a2(sig_i_a2), // Input Port
.sig_o_a2(sig_o_a2) // Output Port
);
// End of Generated Instance Port Map for inst_a
// Generated Instance Port Map for inst_b
ent_b inst_b (
.port_b_1(sig_01), // Use internally test1Will create p_mix_sig_1_go port
.port_b_3(sig_03), // Interhierachy link, will create p_mix_sig_3_go
.port_b_4(sig_04), // Interhierachy link, will create p_mix_sig_4_gi
.port_b_5_1(sig_05[2]), // Bus, single bits go to outsideBus, single bits go to outside, will create p_mix_sig_5_2_2_goBu...
.port_b_5_2(sig_05[1]), // Bus, single bits go to outsideBus, single bits go to outside, will create p_mix_sig_5_2_2_goBu...
.port_b_6i(sig_06), // Conflicting definition (X2)
.port_b_6o(sig_06), // Conflicting definition (X2)
.sig_07(sig_07), // Conflicting definition, IN false!
.sig_08(sig_08) // VHDL intermediate needed (port name)
);
// End of Generated Instance Port Map for inst_b
endmodule
|
module sky130_fd_sc_lp__o21bai (
Y ,
A1 ,
A2 ,
B1_N,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A1 ;
input A2 ;
input B1_N;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire b ;
wire or0_out ;
wire nand0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
not not0 (b , B1_N );
or or0 (or0_out , A2, A1 );
nand nand0 (nand0_out_Y , b, or0_out );
sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nand0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
|
module pmsm (npm0, npm1, npm2, npm3, pm0, pm1, pm2, pm3, clk, reset);
// outputs
output [3:0] pm0, pm1, pm2, pm3;
// inputs
input clk, reset;
input [3:0] npm0, npm1, npm2, npm3;
reg [3:0] pm0, pm1, pm2, pm3;
reg [3:0] npm0norm, npm1norm, npm2norm, npm3norm;
// Defining constants: parameter [name_of_constant] = value;
parameter saturating_value = 4'd15;
always @ (npm0 or npm1 or npm2 or npm3)
begin
if ((npm0 <= npm1)&&(npm0 <= npm2)&&(npm0 <= npm3))
begin
npm0norm <= 0;
npm1norm <= npm1-npm0;
npm2norm <= npm2-npm0;
npm3norm <= npm3-npm0;
end
else if ((npm1 <= npm0)&&(npm1 <= npm2)&&(npm1 <= npm3))
begin
npm0norm <= npm0-npm1;
npm1norm <= 0;
npm2norm <= npm2-npm1;
npm3norm <= npm3-npm1;
end
else if ((npm2 <= npm0)&&(npm2 <= npm1)&&(npm2 <= npm3))
begin
npm0norm <= npm0-npm2;
npm1norm <= npm1-npm2;
npm2norm <= 0;
npm3norm <= npm3-npm2;
end
else if ((npm3 <= npm0)&&(npm3 <= npm1)&&(npm3 <= npm2))
begin
npm0norm <= npm0-npm3;
npm1norm <= npm1-npm3;
npm2norm <= npm2-npm3;
npm3norm <= 0;
end
end // always @ (npm0 or npm1 or npm2 or npm3)
/**
* @modified by Zhiyang Ong, November 1, 2007
* Note that the first register is reset to zero,
* and the rest are reset to infinity, which is
* represented by the saturating value of 15
* = 2^n - 1 = 2^4 - 1.
*
* This prevents the solution from arriving at a
* set of false/incorrect set of equivalent
* paths in the Trellis diagram. Multiple paths
* with zero costs indicate no unique solution.
* Also, these infinite/saturated values will be
* "removed"/diminished in 2 clock cycles.
*/
always @ (posedge clk)
begin
if (reset)
begin
pm0 <= 4'd0;
pm1 <= saturating_value;
pm2 <= saturating_value;
pm3 <= saturating_value;
end
else
begin
pm0 <= npm0norm;
pm1 <= npm1norm;
pm2 <= npm2norm;
pm3 <= npm3norm;
end
end // always @ (posedge clk)
endmodule
|
module clk_200_400_tb ();
// Clock to Q delay of 100ps
localparam TCQ = 100;
// timescale is 1ps/1ps
localparam ONE_NS = 1000;
localparam PHASE_ERR_MARGIN = 100; // 100ps
// how many cycles to run
localparam COUNT_PHASE = 1024;
// we'll be using the period in many locations
localparam time PER1 = 5.000*ONE_NS;
localparam time PER1_1 = PER1/2;
localparam time PER1_2 = PER1 - PER1/2;
// Declare the input clock signals
reg CLK_IN1 = 1;
// The high bit of the sampling counter
wire COUNT;
// Status and control signals
reg RESET = 0;
wire LOCKED;
reg COUNTER_RESET = 0;
// Input clock generation
//------------------------------------
always begin
CLK_IN1 = #PER1_1 ~CLK_IN1;
CLK_IN1 = #PER1_2 ~CLK_IN1;
end
// Test sequence
reg [15*8-1:0] test_phase = "";
initial begin
// Set up any display statements using time to be readable
$timeformat(-12, 2, "ps", 10);
COUNTER_RESET = 0;
test_phase = "reset";
RESET = 1;
#(PER1*6);
RESET = 0;
test_phase = "wait lock";
`wait_lock;
#(PER1*6);
COUNTER_RESET = 1;
#(PER1*20)
COUNTER_RESET = 0;
test_phase = "counting";
#(PER1*COUNT_PHASE);
$display("SIMULATION PASSED");
$display("SYSTEM_CLOCK_COUNTER : %0d\n",$time/PER1);
$finish;
end
// Instantiation of the example design containing the clock
// network and sampling counters
//---------------------------------------------------------
clk_200_400_exdes
#(
.TCQ (TCQ)
) dut
(// Clock in ports
.CLK_IN1 (CLK_IN1),
// Reset for logic in example design
.COUNTER_RESET (COUNTER_RESET),
// High bits of the counters
.COUNT (COUNT),
// Status and control signals
.RESET (RESET),
.LOCKED (LOCKED));
endmodule
|
module tb_top;
reg clk, rst;
wire [31:0] addr;
wire write_en;
wire [31:0] wdata;
wire [31:0] rdata;
initial begin
clk <= 0;
rst <= 1;
#105
rst <= 0;
#1000
$finish;
end
always begin
#10 clk = ~clk;
end
`ifndef NO_DEBUG
// always @(posedge clk) begin
// $display("time %t, %d %d", $time, rst, dut.top_main_inst.cur_st);
// end
`endif
top dut(.clk(clk), .rst(rst)
`ifndef NO_MEMORY
,
.sram_addr(addr), .sram_wdata_en(write_en),
.sram_wdata(wdata), .sram_rdata(rdata)
`endif
);
`ifndef NO_MEMORY
mem16k mem(.clk_i(clk), .rst_i(rst),
.addr_i(addr[31:2]), .write_en_i(write_en),
.wdata_i(wdata), .rdata_o(rdata));
`endif
endmodule
|
module mem16k(clk_i, rst_i, addr_i, write_en_i, wdata_i, rdata_o);
input clk_i, rst_i;
input [29:0] addr_i;
input write_en_i;
input [31:0] wdata_i;
output [31:0] rdata_o;
reg [31:0] storage[0:4095];
integer i;
initial begin
`ifndef NO_DEBUG
$display("mem16k init");
`endif
for (i = 0; i < 4096; i = i + 1) begin
storage[i] = 0;
end
end
always @(posedge clk_i) begin
if (rst_i) begin
end else begin
// $display("%t mem:read addr=%x,data=%x", $time, addr_i<<2, storage[addr_i[11:0]]);
if (write_en_i) begin
// $display("%t mem:write addr=%x,data=%x\n", $time, addr_i<<2, wdata_i);
storage[addr_i[11:0]] <= wdata_i;
end
end
end
assign rdata_o = storage[addr_i[11:0]];
endmodule
|
module CORDIC_Arch3v1_W64_EW11_SW52_SWR55_EWR6 ( clk, rst, beg_fsm_cordic,
ack_cordic, operation, data_in, shift_region_flag, ready_cordic,
data_output, beg_add_subt, add_subt_dataA, add_subt_dataB,
result_add_subt, op_add_subt, ready_add_subt, enab_cont_iter );
input [63:0] data_in;
input [1:0] shift_region_flag;
output [63:0] data_output;
output [63:0] add_subt_dataA;
output [63:0] add_subt_dataB;
input [63:0] result_add_subt;
input clk, rst, beg_fsm_cordic, ack_cordic, operation, ready_add_subt;
output ready_cordic, beg_add_subt, op_add_subt, enab_cont_iter;
wire d_ff1_operation_out, d_ff3_sign_out, n1181, n1182, n1183, n1184,
n1185, n1186, n1187, n1188, n1189, n1190, n1191, n1192, n1193, n1194,
n1195, n1196, n1197, n1198, n1199, n1200, n1201, n1202, n1203, n1204,
n1205, n1206, n1207, n1208, n1209, n1210, n1211, n1212, n1213, n1214,
n1215, n1216, n1217, n1218, n1219, n1220, n1221, n1222, n1223, n1224,
n1225, n1226, n1227, n1228, n1229, n1230, n1231, n1232, n1233, n1234,
n1235, n1236, n1237, n1238, n1239, n1240, n1241, n1242, n1243, n1244,
n1245, n1246, n1247, n1248, n1249, n1250, n1251, n1252, n1253, n1254,
n1255, n1256, n1257, n1258, n1259, n1260, n1261, n1262, n1263, n1264,
n1265, n1266, n1267, n1268, n1269, n1270, n1271, n1272, n1273, n1274,
n1275, n1276, n1277, n1278, n1279, n1280, n1281, n1282, n1283, n1284,
n1285, n1286, n1287, n1288, n1289, n1290, n1291, n1292, n1293, n1294,
n1295, n1296, n1297, n1298, n1299, n1300, n1301, n1302, n1303, n1304,
n1305, n1306, n1307, n1308, n1309, n1310, n1311, n1312, n1313, n1314,
n1315, n1316, n1317, n1318, n1319, n1320, n1321, n1322, n1323, n1324,
n1325, n1326, n1327, n1328, n1329, n1330, n1331, n1332, n1333, n1334,
n1335, n1336, n1337, n1338, n1339, n1340, n1341, n1342, n1343, n1344,
n1345, n1346, n1347, n1348, n1349, n1350, n1351, n1352, n1353, n1354,
n1355, n1356, n1357, n1358, n1359, n1360, n1361, n1362, n1363, n1364,
n1365, n1366, n1367, n1368, n1369, n1370, n1371, n1372, n1373, n1374,
n1375, n1376, n1377, n1378, n1379, n1380, n1381, n1382, n1383, n1384,
n1385, n1386, n1387, n1388, n1389, n1390, n1391, n1392, n1393, n1394,
n1395, n1396, n1397, n1398, n1399, n1400, n1401, n1402, n1403, n1404,
n1405, n1406, n1407, n1408, n1409, n1410, n1411, n1412, n1413, n1414,
n1415, n1416, n1417, n1418, n1419, n1420, n1421, n1422, n1423, n1424,
n1425, n1426, n1427, n1428, n1429, n1430, n1431, n1432, n1433, n1434,
n1435, n1436, n1437, n1438, n1439, n1440, n1441, n1442, n1443, n1444,
n1445, n1446, n1447, n1448, n1449, n1450, n1451, n1452, n1453, n1454,
n1455, n1456, n1457, n1458, n1459, n1460, n1461, n1462, n1463, n1464,
n1465, n1466, n1467, n1468, n1469, n1470, n1471, n1472, n1473, n1474,
n1475, n1476, n1477, n1478, n1479, n1480, n1481, n1482, n1483, n1484,
n1485, n1486, n1487, n1488, n1489, n1490, n1491, n1492, n1493, n1494,
n1495, n1496, n1497, n1498, n1499, n1500, n1501, n1502, n1503, n1504,
n1505, n1506, n1507, n1508, n1509, n1510, n1511, n1512, n1513, n1514,
n1515, n1516, n1517, n1518, n1519, n1520, n1521, n1522, n1523, n1524,
n1525, n1526, n1527, n1528, n1529, n1530, n1531, n1532, n1533, n1534,
n1535, n1536, n1537, n1538, n1539, n1540, n1541, n1542, n1543, n1544,
n1545, n1546, n1547, n1548, n1549, n1550, n1551, n1552, n1553, n1554,
n1555, n1556, n1557, n1558, n1559, n1560, n1561, n1562, n1563, n1564,
n1565, n1566, n1567, n1568, n1569, n1570, n1571, n1572, n1573, n1574,
n1575, n1576, n1577, n1578, n1579, n1580, n1581, n1582, n1583, n1584,
n1585, n1586, n1587, n1588, n1589, n1590, n1591, n1592, n1593, n1594,
n1595, n1596, n1597, n1598, n1599, n1600, n1601, n1602, n1603, n1604,
n1605, n1606, n1607, n1608, n1609, n1610, n1611, n1612, n1613, n1614,
n1615, n1616, n1617, n1618, n1619, n1620, n1621, n1622, n1623, n1624,
n1625, n1626, n1627, n1628, n1629, n1630, n1631, n1632, n1633, n1634,
n1635, n1636, n1637, n1638, n1639, n1640, n1641, n1642, n1643, n1644,
n1645, n1646, n1647, n1648, n1649, n1650, n1651, n1652, n1653, n1654,
n1655, n1656, n1657, n1658, n1659, n1660, n1661, n1662, n1663, n1664,
n1665, n1666, n1667, n1668, n1669, n1670, n1671, n1672, n1673, n1674,
n1675, n1676, n1677, n1678, n1679, n1680, n1681, n1682, n1683, n1684,
n1685, n1686, n1687, n1688, n1689, n1690, n1691, n1692, n1693, n1694,
n1695, n1696, n1697, n1698, n1699, n1700, n1701, n1702, n1703, n1704,
n1705, n1706, n1707, n1708, n1709, n1710, n1711, n1712, n1713, n1714,
n1715, n1716, n1717, n1718, n1719, n1720, n1721, n1722, n1723, n1724,
n1725, n1726, n1727, n1728, n1729, n1730, n1731, n1732, n1733, n1734,
n1735, n1736, n1737, n1738, n1739, n1740, n1741, n1742, n1743, n1744,
n1745, n1746, n1747, n1748, n1749, n1750, n1751, n1752, n1753, n1754,
n1755, n1756, n1757, n1758, n1759, n1760, n1761, n1762, n1763, n1764,
n1765, n1766, n1767, n1768, n1769, n1770, n1771, n1772, n1773, n1774,
n1775, n1776, n1777, n1778, n1779, n1780, n1781, n1782, n1783, n1784,
n1785, n1786, n1787, n1788, n1789, n1790, n1791, n1792, n1793, n1794,
n1795, n1796, n1797, n1798, n1799, n1800, n1801, n1802, n1803, n1804,
n1805, n1806, n1807, n1808, n1809, n1810, n1811, n1812, n1813, n1814,
n1815, n1816, n1817, n1818, n1819, n1820, n1821, n1822, n1823, n1824,
n1825, n1826, n1827, n1828, n1829, n1830, n1831, n1832, n1833, n1834,
n1835, n1836, n1837, n1838, n1839, n1840, n1841, n1842, n1843, n1844,
n1845, n1846, n1847, n1848, n1849, n1850, n1851, n1852, n1853, n1854,
n1855, n1856, n1857, n1858, n1859, n1860, n1861, n1862, n1863, n1864,
n1865, n1866, n1867, n1868, n1869, n1870, n1871, n1872, n1873, n1874,
n1875, n1876, n1877, n1878, n2009, n2010, n2011, n2012, n2013, n2014,
n2015, n2016, n2017, n2018, n2019, n2020, n2021, n2022, n2023, n2024,
n2025, n2026, n2027, n2028, n2029, n2030, n2031, n2032, n2033, n2035,
n2036, n2037, n2038, n2039, n2040, n2041, n2042, n2043, n2044, n2045,
n2046, n2047, n2048, n2049, n2050, n2051, n2052, n2053, n2054, n2055,
n2056, n2057, n2058, n2059, n2060, n2061, n2062, n2063, n2064, n2065,
n2066, n2067, n2068, n2069, n2070, n2071, n2072, n2073, n2074, n2075,
n2076, n2077, n2078, n2079, n2080, n2081, n2082, n2083, n2084, n2085,
n2086, n2087, n2088, n2089, n2090, n2091, n2092, n2093, n2094, n2095,
n2096, n2097, n2098, n2099, n2100, n2101, n2102, n2103, n2104, n2105,
n2106, n2107, n2108, n2109, n2110, n2111, n2112, n2113, n2114, n2115,
n2116, n2117, n2118, n2119, n2120, n2121, n2122, n2123, n2124, n2125,
n2126, n2127, n2128, n2129, n2130, n2131, n2132, n2133, n2134, n2135,
n2136, n2137, n2138, n2139, n2140, n2141, n2142, n2143, n2144, n2145,
n2146, n2147, n2148, n2149, n2150, n2151, n2152, n2153, n2154, n2155,
n2156, n2157, n2158, n2159, n2160, n2161, n2162, n2163, n2164, n2165,
n2166, n2167, n2168, n2169, n2170, n2171, n2172, n2173, n2174, n2175,
n2176, n2177, n2178, n2179, n2180, n2181, n2182, n2183, n2184, n2185,
n2186, n2187, n2188, n2189, n2190, n2191, n2192, n2193, n2194, n2195,
n2196, n2197, n2198, n2199, n2200, n2201, n2202, n2203, n2204, n2205,
n2206, n2207, n2208, n2209, n2210, n2211, n2212, n2213, n2214, n2215,
n2216, n2217, n2218, n2219, n2220, n2221, n2222, n2223, n2224, n2225,
n2226, n2227, n2228, n2229, n2230, n2231, n2232, n2233, n2234, n2235,
n2236, n2237, n2238, n2239, n2240, n2241, n2242, n2243, n2244, n2245,
n2246, n2247, n2248, n2249, n2250, n2251, n2252, n2253, n2254, n2255,
n2256, n2257, n2258, n2259, n2260, n2261, n2262, n2263, n2264, n2265,
n2266, n2267, n2268, n2269, n2270, n2271, n2272, n2273, n2274, n2275,
n2276, n2277, n2278, n2279, n2280, n2281, n2282, n2283, n2284, n2285,
n2286, n2287, n2288, n2289, n2290, n2291, n2292, n2293, n2294, n2295,
n2296, n2297, n2298, n2299, n2300, n2301, n2302, n2303, n2304, n2305,
n2306, n2307, n2308, n2309, n2310, n2311, n2312, n2313, n2314, n2315,
n2316, n2317, n2318, n2319, n2320, n2321, n2322, n2323, n2324, n2325,
n2326, n2327, n2328, n2329, n2330, n2331, n2332, n2333, n2334, n2335,
n2336, n2337, n2338, n2339, n2340, n2341, n2342, n2343, n2344, n2345,
n2346, n2347, n2348, n2349, n2350, n2351, n2352, n2353, n2354, n2355,
n2356, n2357, n2358, n2359, n2360, n2361, n2362, n2363, n2364, n2365,
n2366, n2367, n2368, n2369, n2370, n2371, n2372, n2373, n2374, n2375,
n2376, n2377, n2378, n2379, n2380, n2381, n2382, n2383, n2384, n2385,
n2386, n2387, n2388, n2389, n2390, n2391, n2392, n2393, n2394, n2395,
n2396, n2397, n2398, n2399, n2400, n2401, n2402, n2403, n2404, n2405,
n2406, n2407, n2408, n2409, n2410, n2411, n2412, n2413, n2414, n2415,
n2416, n2417, n2418, n2419, n2420, n2421, n2422, n2423, n2424, n2425,
n2426, n2427, n2428, n2429, n2430, n2431, n2432, n2433, n2434, n2435,
n2436, n2437, n2438, n2439, n2440, n2441, n2442, n2443, n2444, n2445,
n2446, n2447, n2448, n2449, n2450, n2451, n2452, n2453, n2454, n2455,
n2456, n2457, n2458, n2459, n2460, n2461, n2462, n2463, n2464, n2465,
n2466, n2467, n2468, n2469, n2470, n2471, n2472, n2473, n2474, n2475,
n2476, n2477, n2478, n2479, n2480, n2481, n2482, n2483, n2484, n2485,
n2486, n2487, n2488, n2489, n2490, n2491, n2492, n2493, n2494, n2495,
n2496, n2497, n2498, n2499, n2500, n2501, n2502, n2503, n2504, n2505,
n2506, n2507, n2508, n2509, n2510, n2511, n2512, n2513, n2514, n2515,
n2516, n2517, n2518, n2519, n2520, n2521, n2522, n2523, n2524, n2525,
n2526, n2527, n2528, n2529, n2530, n2531, n2532, n2533, n2534, n2535,
n2536, n2537, n2538, n2539, n2540, n2541, n2542, n2543, n2544, n2545,
n2546, n2547, n2548, n2549, n2550, n2551, n2552, n2553, n2554, n2555,
n2556, n2557, n2558, n2559, n2560, n2561, n2562, n2563, n2564, n2565,
n2566, n2567, n2568, n2569, n2570, n2571, n2572, n2573, n2574, n2575,
n2576, n2577, n2578, n2579, n2580, n2581, n2582, n2583, n2584, n2585,
n2586, n2587, n2588, n2589, n2590, n2591, n2592, n2593, n2594, n2595,
n2596, n2597, n2598, n2599, n2600, n2601, n2602, n2603, n2604, n2605,
n2606, n2607, n2608, n2609, n2610, n2611, n2612, n2613, n2614, n2615,
n2616, n2617, n2618, n2619, n2620, n2621, n2622, n2623, n2624, n2625,
n2626, n2627, n2628, n2629, n2630, n2631, n2632, n2633, n2634, n2635,
n2636, n2637, n2638, n2639, n2640, n2641, n2642, n2643, n2644, n2645,
n2646, n2647, n2648, n2649, n2650, n2651, n2652, n2653, n2654, n2655,
n2656, n2657, n2658, n2659, n2660, n2661, n2662, n2663, n2664, n2665,
n2666, n2667, n2668, n2669, n2670, n2671, n2672, n2673, n2674, n2675,
n2676, n2677, n2678, n2679, n2680, n2681, n2682, n2683, n2684, n2685,
n2686, n2687, n2688, n2689, n2690, n2691, n2692, n2693, n2694, n2695,
n2696, n2697, n2698, n2699, n2700, n2701, n2702, n2703, n2704, n2705,
n2706, n2707, n2708, n2709, n2710, n2711, n2712, n2713, n2714, n2715,
n2716, n2717, n2718, n2719, n2720, n2721, n2722, n2723, n2724, n2725,
n2726, n2727, n2728, n2729, n2730, n2731, n2732, n2733, n2734, n2735,
n2736, n2737, n2738, n2739, n2740, n2741, n2742, n2743, n2744, n2745,
n2746, n2747, n2748, n2749, n2750, n2751, n2752, n2753, n2754, n2755,
n2756, n2757, n2758, n2759, n2760, n2761, n2762, n2763, n2764, n2765,
n2766, n2767, n2768, n2769, n2770, n2771, n2772, n2773, n2774, n2775,
n2776, n2777, n2778, n2779, n2780, n2781, n2782, n2783, n2784, n2785,
n2786, n2787, n2788, n2789, n2790, n2791, n2792, n2793, n2794, n2795,
n2796, n2797, n2798, n2799, n2800, n2801, n2802, n2803, n2804, n2805,
n2806, n2807, n2808, n2809, n2810, n2811, n2812, n2813, n2814, n2815,
n2816, n2817, n2818, n2819, n2820, n2821, n2822, n2823, n2824, n2825,
n2826, n2827, n2828, n2829, n2830, n2831, n2832, n2833, n2834, n2835,
n2836, n2837, n2838, n2839, n2840, n2841, n2842, n2843, n2844, n2845,
n2846, n2847, n2848, n2849, n2850, n2851, n2852, n2853, n2854, n2855,
n2856, n2857, n2858, n2859, n2860, n2861, n2862;
wire [3:0] cont_iter_out;
wire [1:0] cont_var_out;
wire [1:0] d_ff1_shift_region_flag_out;
wire [63:0] d_ff1_Z;
wire [63:0] d_ff_Xn;
wire [63:0] d_ff_Yn;
wire [63:0] d_ff_Zn;
wire [63:0] d_ff2_X;
wire [63:0] d_ff2_Y;
wire [63:0] d_ff2_Z;
wire [63:0] d_ff3_sh_x_out;
wire [63:0] d_ff3_sh_y_out;
wire [55:0] d_ff3_LUT_out;
wire [7:0] inst_CORDIC_FSM_v3_state_next;
wire [7:0] inst_CORDIC_FSM_v3_state_reg;
DFFRXLTS reg_LUT_Q_reg_53_ ( .D(n1505), .CK(n2833), .RN(n2747), .QN(n2715)
);
DFFRXLTS reg_LUT_Q_reg_45_ ( .D(n1509), .CK(n2859), .RN(n2747), .QN(n2714)
);
DFFRXLTS reg_LUT_Q_reg_41_ ( .D(n1512), .CK(n2835), .RN(n2748), .QN(n2713)
);
DFFRXLTS reg_LUT_Q_reg_22_ ( .D(n1527), .CK(n2832), .RN(n2749), .QN(n2712)
);
DFFRXLTS reg_LUT_Q_reg_20_ ( .D(n1529), .CK(n2839), .RN(n2749), .QN(n2711)
);
DFFRXLTS reg_LUT_Q_reg_35_ ( .D(n1515), .CK(n2830), .RN(n2748), .QN(n2710)
);
DFFRXLTS reg_LUT_Q_reg_31_ ( .D(n1519), .CK(n2840), .RN(n2748), .QN(n2709)
);
DFFRXLTS reg_LUT_Q_reg_24_ ( .D(n1525), .CK(n2838), .RN(n2749), .QN(n2708)
);
DFFRXLTS reg_LUT_Q_reg_16_ ( .D(n1533), .CK(n2830), .RN(n2750), .QN(n2707)
);
DFFRXLTS reg_LUT_Q_reg_12_ ( .D(n1537), .CK(n2826), .RN(n2750), .QN(n2706)
);
DFFRX1TS reg_val_muxY_2stage_Q_reg_52_ ( .D(n1332), .CK(n2849), .RN(n2728),
.Q(d_ff2_Y[52]), .QN(n2704) );
DFFRXLTS reg_LUT_Q_reg_50_ ( .D(n1507), .CK(n2836), .RN(n2747), .QN(n2703)
);
DFFRX1TS reg_shift_y_Q_reg_61_ ( .D(n1312), .CK(n2841), .RN(n2759), .QN(
n2702) );
DFFRX1TS reg_LUT_Q_reg_56_ ( .D(n1502), .CK(n2839), .RN(n2747), .QN(n2701)
);
DFFRX1TS reg_val_muxX_2stage_Q_reg_57_ ( .D(n1199), .CK(n2854), .RN(n2718),
.Q(d_ff2_X[57]), .QN(n2700) );
DFFRX1TS reg_LUT_Q_reg_32_ ( .D(n1518), .CK(n2829), .RN(n2748), .QN(n2699)
);
DFFRX1TS reg_LUT_Q_reg_4_ ( .D(n1545), .CK(n2820), .RN(n2751), .QN(n2698) );
DFFRX1TS inst_CORDIC_FSM_v3_state_reg_reg_7_ ( .D(
inst_CORDIC_FSM_v3_state_next[7]), .CK(n2798), .RN(n2780), .Q(
inst_CORDIC_FSM_v3_state_reg[7]), .QN(n2697) );
DFFRX1TS reg_LUT_Q_reg_34_ ( .D(n1516), .CK(n2053), .RN(n2748), .QN(n2696)
);
DFFRX1TS reg_val_muxY_2stage_Q_reg_60_ ( .D(n1324), .CK(n2850), .RN(n2728),
.Q(d_ff2_Y[60]), .QN(n2695) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_58_ ( .D(n1326), .CK(n2850), .RN(n2728),
.Q(d_ff2_Y[58]), .QN(n2694) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_60_ ( .D(n1196), .CK(n2857), .RN(n2718),
.Q(d_ff2_X[60]), .QN(n2693) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_58_ ( .D(n1198), .CK(n2852), .RN(n2718),
.Q(d_ff2_X[58]), .QN(n2692) );
DFFRX1TS reg_LUT_Q_reg_28_ ( .D(n1521), .CK(n2832), .RN(n2749), .QN(n2691)
);
DFFRX1TS reg_val_muxX_2stage_Q_reg_52_ ( .D(n1204), .CK(n2049), .RN(n2782),
.QN(n2690) );
DFFRX2TS VAR_CONT_temp_reg_0_ ( .D(n1873), .CK(n2798), .RN(n2780), .Q(
cont_var_out[0]), .QN(n2689) );
DFFRX2TS reg_val_muxY_2stage_Q_reg_53_ ( .D(n1331), .CK(n2849), .RN(n2728),
.QN(n2688) );
DFFRX1TS inst_CORDIC_FSM_v3_state_reg_reg_6_ ( .D(
inst_CORDIC_FSM_v3_state_next[6]), .CK(n2845), .RN(n2781), .Q(
inst_CORDIC_FSM_v3_state_reg[6]), .QN(n2685) );
DFFRX1TS reg_region_flag_Q_reg_0_ ( .D(n1871), .CK(n2795), .RN(n2780), .Q(
d_ff1_shift_region_flag_out[0]), .QN(n2684) );
DFFRX2TS ITER_CONT_temp_reg_1_ ( .D(n1876), .CK(n2028), .RN(n2781), .Q(
cont_iter_out[1]), .QN(n2683) );
DFFRX1TS reg_shift_y_Q_reg_56_ ( .D(n1317), .CK(n2838), .RN(n2038), .QN(
n2682) );
DFFRX1TS reg_region_flag_Q_reg_1_ ( .D(n1870), .CK(n2795), .RN(n2719), .Q(
d_ff1_shift_region_flag_out[1]), .QN(n2681) );
DFFRX1TS reg_shift_x_Q_reg_56_ ( .D(n1189), .CK(n2831), .RN(n2792), .QN(
n2680) );
DFFRXLTS d_ff5_data_out_Q_reg_0_ ( .D(n1613), .CK(n2811), .RN(n2762), .Q(
data_output[0]) );
DFFRXLTS d_ff5_data_out_Q_reg_1_ ( .D(n1612), .CK(n2815), .RN(n2762), .Q(
data_output[1]) );
DFFRXLTS d_ff5_data_out_Q_reg_2_ ( .D(n1611), .CK(n2815), .RN(n2762), .Q(
data_output[2]) );
DFFRXLTS d_ff5_data_out_Q_reg_3_ ( .D(n1610), .CK(n2815), .RN(n2761), .Q(
data_output[3]) );
DFFRXLTS d_ff5_data_out_Q_reg_4_ ( .D(n1609), .CK(n2815), .RN(n2761), .Q(
data_output[4]) );
DFFRXLTS d_ff5_data_out_Q_reg_5_ ( .D(n1608), .CK(n2815), .RN(n2761), .Q(
data_output[5]) );
DFFRXLTS d_ff5_data_out_Q_reg_6_ ( .D(n1607), .CK(n2820), .RN(n2761), .Q(
data_output[6]) );
DFFRXLTS d_ff5_data_out_Q_reg_7_ ( .D(n1606), .CK(n2853), .RN(n2761), .Q(
data_output[7]) );
DFFRXLTS d_ff5_data_out_Q_reg_8_ ( .D(n1605), .CK(n2024), .RN(n2760), .Q(
data_output[8]) );
DFFRXLTS d_ff5_data_out_Q_reg_9_ ( .D(n1604), .CK(n2826), .RN(n2760), .Q(
data_output[9]) );
DFFRXLTS d_ff5_data_out_Q_reg_11_ ( .D(n1602), .CK(n2817), .RN(n2760), .Q(
data_output[11]) );
DFFRXLTS d_ff5_data_out_Q_reg_12_ ( .D(n1601), .CK(n2817), .RN(n2760), .Q(
data_output[12]) );
DFFRXLTS d_ff5_data_out_Q_reg_13_ ( .D(n1600), .CK(n2817), .RN(n2719), .Q(
data_output[13]) );
DFFRXLTS d_ff5_data_out_Q_reg_14_ ( .D(n1599), .CK(n2817), .RN(n2753), .Q(
data_output[14]) );
DFFRXLTS d_ff5_data_out_Q_reg_15_ ( .D(n1598), .CK(n2817), .RN(n2038), .Q(
data_output[15]) );
DFFRXLTS d_ff5_data_out_Q_reg_16_ ( .D(n1597), .CK(n2818), .RN(n2792), .Q(
data_output[16]) );
DFFRXLTS d_ff5_data_out_Q_reg_17_ ( .D(n1596), .CK(n2818), .RN(n2790), .Q(
data_output[17]) );
DFFRXLTS d_ff5_data_out_Q_reg_18_ ( .D(n1595), .CK(n2818), .RN(n2759), .Q(
data_output[18]) );
DFFRXLTS d_ff5_data_out_Q_reg_19_ ( .D(n1594), .CK(n2818), .RN(n2038), .Q(
data_output[19]) );
DFFRXLTS d_ff5_data_out_Q_reg_20_ ( .D(n1593), .CK(n2818), .RN(n2759), .Q(
data_output[20]) );
DFFRXLTS d_ff5_data_out_Q_reg_21_ ( .D(n1592), .CK(n2819), .RN(n2038), .Q(
data_output[21]) );
DFFRXLTS d_ff5_data_out_Q_reg_22_ ( .D(n1591), .CK(n2819), .RN(n2759), .Q(
data_output[22]) );
DFFRXLTS d_ff5_data_out_Q_reg_23_ ( .D(n1590), .CK(n2819), .RN(n2758), .Q(
data_output[23]) );
DFFRXLTS d_ff5_data_out_Q_reg_24_ ( .D(n1589), .CK(n2819), .RN(n2758), .Q(
data_output[24]) );
DFFRXLTS d_ff5_data_out_Q_reg_25_ ( .D(n1588), .CK(n2819), .RN(n2758), .Q(
data_output[25]) );
DFFRXLTS d_ff5_data_out_Q_reg_26_ ( .D(n1587), .CK(n2827), .RN(n2758), .Q(
data_output[26]) );
DFFRXLTS d_ff5_data_out_Q_reg_27_ ( .D(n1586), .CK(n2828), .RN(n2758), .Q(
data_output[27]) );
DFFRXLTS d_ff5_data_out_Q_reg_28_ ( .D(n1585), .CK(n2853), .RN(n2786), .Q(
data_output[28]) );
DFFRXLTS d_ff5_data_out_Q_reg_29_ ( .D(n1584), .CK(n2820), .RN(n2037), .Q(
data_output[29]) );
DFFRXLTS d_ff5_data_out_Q_reg_30_ ( .D(n1583), .CK(n2024), .RN(n2035), .Q(
data_output[30]) );
DFFRXLTS d_ff5_data_out_Q_reg_31_ ( .D(n1582), .CK(n2814), .RN(n2786), .Q(
data_output[31]) );
DFFRXLTS d_ff5_data_out_Q_reg_32_ ( .D(n1581), .CK(n2027), .RN(n2035), .Q(
data_output[32]) );
DFFRXLTS d_ff5_data_out_Q_reg_33_ ( .D(n1580), .CK(n2814), .RN(n2757), .Q(
data_output[33]) );
DFFRXLTS d_ff5_data_out_Q_reg_34_ ( .D(n1579), .CK(n2811), .RN(n2757), .Q(
data_output[34]) );
DFFRXLTS d_ff5_data_out_Q_reg_35_ ( .D(n1578), .CK(n2823), .RN(n2757), .Q(
data_output[35]) );
DFFRXLTS d_ff5_data_out_Q_reg_36_ ( .D(n1577), .CK(n2823), .RN(n2757), .Q(
data_output[36]) );
DFFRXLTS d_ff5_data_out_Q_reg_37_ ( .D(n1576), .CK(n2812), .RN(n2757), .Q(
data_output[37]) );
DFFRXLTS d_ff5_data_out_Q_reg_38_ ( .D(n1575), .CK(n2050), .RN(n2756), .Q(
data_output[38]) );
DFFRXLTS d_ff5_data_out_Q_reg_39_ ( .D(n1574), .CK(n2821), .RN(n2756), .Q(
data_output[39]) );
DFFRXLTS d_ff5_data_out_Q_reg_40_ ( .D(n1573), .CK(n2050), .RN(n2756), .Q(
data_output[40]) );
DFFRXLTS d_ff5_data_out_Q_reg_41_ ( .D(n1572), .CK(n2812), .RN(n2756), .Q(
data_output[41]) );
DFFRXLTS d_ff5_data_out_Q_reg_42_ ( .D(n1571), .CK(n2822), .RN(n2756), .Q(
data_output[42]) );
DFFRXLTS d_ff5_data_out_Q_reg_43_ ( .D(n1570), .CK(n2822), .RN(n2755), .Q(
data_output[43]) );
DFFRXLTS d_ff5_data_out_Q_reg_44_ ( .D(n1569), .CK(n2811), .RN(n2755), .Q(
data_output[44]) );
DFFRXLTS d_ff5_data_out_Q_reg_45_ ( .D(n1568), .CK(n2812), .RN(n2755), .Q(
data_output[45]) );
DFFRXLTS d_ff5_data_out_Q_reg_46_ ( .D(n1567), .CK(n2796), .RN(n2755), .Q(
data_output[46]) );
DFFRXLTS d_ff5_data_out_Q_reg_47_ ( .D(n1566), .CK(n2858), .RN(n2755), .Q(
data_output[47]) );
DFFRXLTS d_ff5_data_out_Q_reg_48_ ( .D(n1565), .CK(n2824), .RN(n2754), .Q(
data_output[48]) );
DFFRXLTS d_ff5_data_out_Q_reg_49_ ( .D(n1564), .CK(n2853), .RN(n2754), .Q(
data_output[49]) );
DFFRXLTS d_ff5_data_out_Q_reg_50_ ( .D(n1563), .CK(n2050), .RN(n2754), .Q(
data_output[50]) );
DFFRXLTS d_ff5_data_out_Q_reg_51_ ( .D(n1562), .CK(n2051), .RN(n2754), .Q(
data_output[51]) );
DFFRXLTS d_ff5_data_out_Q_reg_52_ ( .D(n1561), .CK(n2051), .RN(n2754), .Q(
data_output[52]) );
DFFRXLTS d_ff5_data_out_Q_reg_53_ ( .D(n1560), .CK(n2051), .RN(n2782), .Q(
data_output[53]) );
DFFRXLTS d_ff5_data_out_Q_reg_54_ ( .D(n1559), .CK(n2051), .RN(n2787), .Q(
data_output[54]) );
DFFRXLTS d_ff5_data_out_Q_reg_55_ ( .D(n1558), .CK(n2825), .RN(n2779), .Q(
data_output[55]) );
DFFRXLTS d_ff5_data_out_Q_reg_56_ ( .D(n1557), .CK(n2826), .RN(n2719), .Q(
data_output[56]) );
DFFRXLTS d_ff5_data_out_Q_reg_57_ ( .D(n1556), .CK(n2826), .RN(n2753), .Q(
data_output[57]) );
DFFRXLTS d_ff5_data_out_Q_reg_58_ ( .D(n1555), .CK(n2826), .RN(n2752), .Q(
data_output[58]) );
DFFRXLTS d_ff5_data_out_Q_reg_59_ ( .D(n1554), .CK(n2826), .RN(n2752), .Q(
data_output[59]) );
DFFRXLTS d_ff5_data_out_Q_reg_60_ ( .D(n1553), .CK(n2826), .RN(n2752), .Q(
data_output[60]) );
DFFRXLTS d_ff5_data_out_Q_reg_61_ ( .D(n1552), .CK(n2827), .RN(n2752), .Q(
data_output[61]) );
DFFRXLTS d_ff5_data_out_Q_reg_62_ ( .D(n1551), .CK(n2820), .RN(n2752), .Q(
data_output[62]) );
DFFRXLTS reg_shift_y_Q_reg_63_ ( .D(n1309), .CK(n2850), .RN(n2727), .Q(
d_ff3_sh_y_out[63]) );
DFFRXLTS reg_shift_x_Q_reg_63_ ( .D(n1181), .CK(n2858), .RN(n2718), .Q(
d_ff3_sh_x_out[63]) );
DFFRXLTS reg_shift_x_Q_reg_62_ ( .D(n1183), .CK(n2834), .RN(n2744), .Q(
d_ff3_sh_x_out[62]) );
DFFRXLTS reg_shift_y_Q_reg_62_ ( .D(n1311), .CK(n2835), .RN(n2744), .Q(
d_ff3_sh_y_out[62]) );
DFFRXLTS d_ff5_data_out_Q_reg_63_ ( .D(n1550), .CK(n2826), .RN(n2751), .Q(
data_output[63]) );
DFFRXLTS reg_LUT_Q_reg_52_ ( .D(n1506), .CK(n2831), .RN(n2747), .Q(
d_ff3_LUT_out[52]) );
DFFRXLTS reg_LUT_Q_reg_44_ ( .D(n1510), .CK(n2841), .RN(n2747), .Q(
d_ff3_LUT_out[44]) );
DFFRXLTS d_ff4_Zn_Q_reg_0_ ( .D(n1805), .CK(n2804), .RN(n2774), .Q(
d_ff_Zn[0]) );
DFFRXLTS reg_shift_y_Q_reg_54_ ( .D(n1319), .CK(n2829), .RN(n2745), .Q(
d_ff3_sh_y_out[54]) );
DFFRXLTS reg_shift_y_Q_reg_55_ ( .D(n1318), .CK(n2053), .RN(n2737), .Q(
d_ff3_sh_y_out[55]) );
DFFRXLTS reg_shift_y_Q_reg_0_ ( .D(n1435), .CK(n2829), .RN(n2738), .Q(
d_ff3_sh_y_out[0]) );
DFFRXLTS reg_shift_y_Q_reg_1_ ( .D(n1433), .CK(n2053), .RN(n2738), .Q(
d_ff3_sh_y_out[1]) );
DFFRXLTS reg_shift_y_Q_reg_2_ ( .D(n1431), .CK(n2839), .RN(n2744), .Q(
d_ff3_sh_y_out[2]) );
DFFRXLTS reg_shift_y_Q_reg_3_ ( .D(n1429), .CK(n2838), .RN(n2745), .Q(
d_ff3_sh_y_out[3]) );
DFFRXLTS reg_shift_y_Q_reg_5_ ( .D(n1425), .CK(n2030), .RN(n2792), .Q(
d_ff3_sh_y_out[5]) );
DFFRXLTS reg_shift_y_Q_reg_6_ ( .D(n1423), .CK(n2030), .RN(n2737), .Q(
d_ff3_sh_y_out[6]) );
DFFRXLTS reg_shift_y_Q_reg_7_ ( .D(n1421), .CK(n2030), .RN(n2736), .Q(
d_ff3_sh_y_out[7]) );
DFFRXLTS reg_shift_y_Q_reg_8_ ( .D(n1419), .CK(n2030), .RN(n2736), .Q(
d_ff3_sh_y_out[8]) );
DFFRXLTS reg_shift_y_Q_reg_9_ ( .D(n1417), .CK(n2030), .RN(n2736), .Q(
d_ff3_sh_y_out[9]) );
DFFRXLTS reg_shift_y_Q_reg_10_ ( .D(n1415), .CK(n2835), .RN(n2736), .Q(
d_ff3_sh_y_out[10]) );
DFFRXLTS reg_shift_y_Q_reg_11_ ( .D(n1413), .CK(n2836), .RN(n2736), .Q(
d_ff3_sh_y_out[11]) );
DFFRXLTS reg_shift_y_Q_reg_13_ ( .D(n1409), .CK(n2824), .RN(n2735), .Q(
d_ff3_sh_y_out[13]) );
DFFRXLTS reg_shift_y_Q_reg_14_ ( .D(n1407), .CK(n2047), .RN(n2735), .Q(
d_ff3_sh_y_out[14]) );
DFFRXLTS reg_shift_y_Q_reg_15_ ( .D(n1405), .CK(n2842), .RN(n2735), .Q(
d_ff3_sh_y_out[15]) );
DFFRXLTS reg_shift_y_Q_reg_17_ ( .D(n1401), .CK(n2842), .RN(n2746), .Q(
d_ff3_sh_y_out[17]) );
DFFRXLTS reg_shift_y_Q_reg_18_ ( .D(n1399), .CK(n2842), .RN(n2037), .Q(
d_ff3_sh_y_out[18]) );
DFFRXLTS reg_shift_y_Q_reg_19_ ( .D(n1397), .CK(n2842), .RN(n2791), .Q(
d_ff3_sh_y_out[19]) );
DFFRXLTS reg_shift_y_Q_reg_21_ ( .D(n1393), .CK(n2843), .RN(n2791), .Q(
d_ff3_sh_y_out[21]) );
DFFRXLTS reg_shift_y_Q_reg_23_ ( .D(n1389), .CK(n2843), .RN(n2734), .Q(
d_ff3_sh_y_out[23]) );
DFFRXLTS reg_shift_y_Q_reg_25_ ( .D(n1385), .CK(n2844), .RN(n2734), .Q(
d_ff3_sh_y_out[25]) );
DFFRXLTS reg_shift_y_Q_reg_26_ ( .D(n1383), .CK(n2844), .RN(n2734), .Q(
d_ff3_sh_y_out[26]) );
DFFRXLTS reg_shift_y_Q_reg_27_ ( .D(n1381), .CK(n2844), .RN(n2733), .Q(
d_ff3_sh_y_out[27]) );
DFFRXLTS reg_shift_y_Q_reg_29_ ( .D(n1377), .CK(n2844), .RN(n2733), .Q(
d_ff3_sh_y_out[29]) );
DFFRXLTS reg_shift_y_Q_reg_33_ ( .D(n1369), .CK(n2797), .RN(n2732), .Q(
d_ff3_sh_y_out[33]) );
DFFRXLTS reg_shift_y_Q_reg_37_ ( .D(n1361), .CK(n2797), .RN(n2731), .Q(
d_ff3_sh_y_out[37]) );
DFFRXLTS reg_shift_y_Q_reg_39_ ( .D(n1357), .CK(n2798), .RN(n2731), .Q(
d_ff3_sh_y_out[39]) );
DFFRXLTS d_ff4_Zn_Q_reg_1_ ( .D(n1804), .CK(n2801), .RN(n2774), .Q(
d_ff_Zn[1]) );
DFFRXLTS d_ff4_Zn_Q_reg_2_ ( .D(n1803), .CK(n2799), .RN(n2774), .Q(
d_ff_Zn[2]) );
DFFRXLTS d_ff4_Zn_Q_reg_3_ ( .D(n1802), .CK(n2801), .RN(n2774), .Q(
d_ff_Zn[3]) );
DFFRXLTS d_ff4_Zn_Q_reg_4_ ( .D(n1801), .CK(n2804), .RN(n2774), .Q(
d_ff_Zn[4]) );
DFFRXLTS d_ff4_Zn_Q_reg_5_ ( .D(n1800), .CK(n2025), .RN(n2773), .Q(
d_ff_Zn[5]) );
DFFRXLTS d_ff4_Zn_Q_reg_6_ ( .D(n1799), .CK(n2804), .RN(n2773), .Q(
d_ff_Zn[6]) );
DFFRXLTS d_ff4_Zn_Q_reg_7_ ( .D(n1798), .CK(n2799), .RN(n2773), .Q(
d_ff_Zn[7]) );
DFFRXLTS d_ff4_Zn_Q_reg_8_ ( .D(n1797), .CK(n2799), .RN(n2773), .Q(
d_ff_Zn[8]) );
DFFRXLTS d_ff4_Zn_Q_reg_9_ ( .D(n1796), .CK(n2801), .RN(n2773), .Q(
d_ff_Zn[9]) );
DFFRXLTS d_ff4_Zn_Q_reg_10_ ( .D(n1795), .CK(n2025), .RN(n2773), .Q(
d_ff_Zn[10]) );
DFFRXLTS d_ff4_Zn_Q_reg_11_ ( .D(n1794), .CK(n2804), .RN(n2773), .Q(
d_ff_Zn[11]) );
DFFRXLTS d_ff4_Zn_Q_reg_12_ ( .D(n1793), .CK(n2803), .RN(n2773), .Q(
d_ff_Zn[12]) );
DFFRXLTS d_ff4_Zn_Q_reg_13_ ( .D(n1792), .CK(n2800), .RN(n2773), .Q(
d_ff_Zn[13]) );
DFFRXLTS d_ff4_Zn_Q_reg_14_ ( .D(n1791), .CK(n2800), .RN(n2773), .Q(
d_ff_Zn[14]) );
DFFRXLTS d_ff4_Zn_Q_reg_15_ ( .D(n1790), .CK(n2025), .RN(n2772), .Q(
d_ff_Zn[15]) );
DFFRXLTS d_ff4_Zn_Q_reg_16_ ( .D(n1789), .CK(n2799), .RN(n2772), .Q(
d_ff_Zn[16]) );
DFFRXLTS d_ff4_Zn_Q_reg_17_ ( .D(n1788), .CK(n2803), .RN(n2772), .Q(
d_ff_Zn[17]) );
DFFRXLTS d_ff4_Zn_Q_reg_18_ ( .D(n1787), .CK(n2803), .RN(n2772), .Q(
d_ff_Zn[18]) );
DFFRXLTS d_ff4_Zn_Q_reg_19_ ( .D(n1786), .CK(n2800), .RN(n2772), .Q(
d_ff_Zn[19]) );
DFFRXLTS d_ff4_Zn_Q_reg_20_ ( .D(n1785), .CK(n2025), .RN(n2772), .Q(
d_ff_Zn[20]) );
DFFRXLTS d_ff4_Zn_Q_reg_21_ ( .D(n1784), .CK(n2803), .RN(n2772), .Q(
d_ff_Zn[21]) );
DFFRXLTS d_ff4_Zn_Q_reg_22_ ( .D(n1783), .CK(n2800), .RN(n2772), .Q(
d_ff_Zn[22]) );
DFFRXLTS d_ff4_Zn_Q_reg_23_ ( .D(n1782), .CK(n2800), .RN(n2772), .Q(
d_ff_Zn[23]) );
DFFRXLTS d_ff4_Zn_Q_reg_24_ ( .D(n1781), .CK(n2802), .RN(n2772), .Q(
d_ff_Zn[24]) );
DFFRXLTS d_ff4_Zn_Q_reg_25_ ( .D(n1780), .CK(n2025), .RN(n2771), .Q(
d_ff_Zn[25]) );
DFFRXLTS d_ff4_Zn_Q_reg_26_ ( .D(n1779), .CK(n2801), .RN(n2771), .Q(
d_ff_Zn[26]) );
DFFRXLTS d_ff4_Zn_Q_reg_27_ ( .D(n1778), .CK(n2803), .RN(n2771), .Q(
d_ff_Zn[27]) );
DFFRXLTS d_ff4_Zn_Q_reg_28_ ( .D(n1777), .CK(n2799), .RN(n2771), .Q(
d_ff_Zn[28]) );
DFFRXLTS d_ff4_Zn_Q_reg_29_ ( .D(n1776), .CK(n2802), .RN(n2771), .Q(
d_ff_Zn[29]) );
DFFRXLTS d_ff4_Zn_Q_reg_30_ ( .D(n1775), .CK(n2025), .RN(n2771), .Q(
d_ff_Zn[30]) );
DFFRXLTS d_ff4_Zn_Q_reg_31_ ( .D(n1774), .CK(n2807), .RN(n2771), .Q(
d_ff_Zn[31]) );
DFFRXLTS d_ff4_Zn_Q_reg_32_ ( .D(n1773), .CK(n2808), .RN(n2771), .Q(
d_ff_Zn[32]) );
DFFRXLTS d_ff4_Zn_Q_reg_33_ ( .D(n1772), .CK(n2808), .RN(n2771), .Q(
d_ff_Zn[33]) );
DFFRXLTS d_ff4_Zn_Q_reg_34_ ( .D(n1771), .CK(n2809), .RN(n2771), .Q(
d_ff_Zn[34]) );
DFFRXLTS d_ff4_Zn_Q_reg_35_ ( .D(n1770), .CK(n2806), .RN(n2770), .Q(
d_ff_Zn[35]) );
DFFRXLTS d_ff4_Zn_Q_reg_36_ ( .D(n1769), .CK(n2808), .RN(n2770), .Q(
d_ff_Zn[36]) );
DFFRXLTS d_ff4_Zn_Q_reg_37_ ( .D(n1768), .CK(n2808), .RN(n2770), .Q(
d_ff_Zn[37]) );
DFFRXLTS d_ff4_Zn_Q_reg_38_ ( .D(n1767), .CK(n2806), .RN(n2770), .Q(
d_ff_Zn[38]) );
DFFRXLTS d_ff4_Zn_Q_reg_39_ ( .D(n1766), .CK(n2805), .RN(n2770), .Q(
d_ff_Zn[39]) );
DFFRXLTS d_ff4_Zn_Q_reg_40_ ( .D(n1765), .CK(n2807), .RN(n2770), .Q(
d_ff_Zn[40]) );
DFFRXLTS d_ff4_Zn_Q_reg_41_ ( .D(n1764), .CK(n2808), .RN(n2770), .Q(
d_ff_Zn[41]) );
DFFRXLTS d_ff4_Zn_Q_reg_42_ ( .D(n1763), .CK(n2805), .RN(n2770), .Q(
d_ff_Zn[42]) );
DFFRXLTS d_ff4_Zn_Q_reg_43_ ( .D(n1762), .CK(n2808), .RN(n2770), .Q(
d_ff_Zn[43]) );
DFFRXLTS d_ff4_Zn_Q_reg_44_ ( .D(n1761), .CK(n2807), .RN(n2770), .Q(
d_ff_Zn[44]) );
DFFRXLTS d_ff4_Zn_Q_reg_45_ ( .D(n1760), .CK(n2805), .RN(n2769), .Q(
d_ff_Zn[45]) );
DFFRXLTS d_ff4_Zn_Q_reg_46_ ( .D(n1759), .CK(n2026), .RN(n2769), .Q(
d_ff_Zn[46]) );
DFFRXLTS d_ff4_Zn_Q_reg_47_ ( .D(n1758), .CK(n2808), .RN(n2769), .Q(
d_ff_Zn[47]) );
DFFRXLTS d_ff4_Zn_Q_reg_48_ ( .D(n1757), .CK(n2808), .RN(n2769), .Q(
d_ff_Zn[48]) );
DFFRXLTS d_ff4_Zn_Q_reg_49_ ( .D(n1756), .CK(n2806), .RN(n2769), .Q(
d_ff_Zn[49]) );
DFFRXLTS d_ff4_Zn_Q_reg_50_ ( .D(n1755), .CK(n2809), .RN(n2769), .Q(
d_ff_Zn[50]) );
DFFRXLTS d_ff4_Zn_Q_reg_51_ ( .D(n1754), .CK(n2806), .RN(n2769), .Q(
d_ff_Zn[51]) );
DFFRXLTS d_ff4_Zn_Q_reg_52_ ( .D(n1753), .CK(n2807), .RN(n2769), .Q(
d_ff_Zn[52]) );
DFFRXLTS d_ff4_Zn_Q_reg_53_ ( .D(n1752), .CK(n2809), .RN(n2769), .Q(
d_ff_Zn[53]) );
DFFRXLTS d_ff4_Zn_Q_reg_54_ ( .D(n1751), .CK(n2805), .RN(n2769), .Q(
d_ff_Zn[54]) );
DFFRXLTS d_ff4_Zn_Q_reg_55_ ( .D(n1750), .CK(n2806), .RN(n2768), .Q(
d_ff_Zn[55]) );
DFFRXLTS d_ff4_Zn_Q_reg_56_ ( .D(n1749), .CK(n2807), .RN(n2768), .Q(
d_ff_Zn[56]) );
DFFRXLTS d_ff4_Zn_Q_reg_57_ ( .D(n1748), .CK(n2026), .RN(n2768), .Q(
d_ff_Zn[57]) );
DFFRXLTS d_ff4_Zn_Q_reg_58_ ( .D(n1747), .CK(n2026), .RN(n2768), .Q(
d_ff_Zn[58]) );
DFFRXLTS d_ff4_Zn_Q_reg_59_ ( .D(n1746), .CK(n2026), .RN(n2768), .Q(
d_ff_Zn[59]) );
DFFRXLTS d_ff4_Zn_Q_reg_60_ ( .D(n1745), .CK(n2026), .RN(n2768), .Q(
d_ff_Zn[60]) );
DFFRXLTS d_ff4_Zn_Q_reg_61_ ( .D(n1744), .CK(n2808), .RN(n2768), .Q(
d_ff_Zn[61]) );
DFFRXLTS d_ff4_Zn_Q_reg_62_ ( .D(n1743), .CK(n2809), .RN(n2768), .Q(
d_ff_Zn[62]) );
DFFRXLTS d_ff4_Zn_Q_reg_63_ ( .D(n1742), .CK(n2808), .RN(n2768), .Q(
d_ff_Zn[63]) );
DFFRXLTS reg_Z0_Q_reg_5_ ( .D(n1864), .CK(n2846), .RN(n2782), .Q(d_ff1_Z[5])
);
DFFRXLTS reg_Z0_Q_reg_6_ ( .D(n1863), .CK(n2794), .RN(n2787), .Q(d_ff1_Z[6])
);
DFFRXLTS reg_Z0_Q_reg_7_ ( .D(n1862), .CK(n2798), .RN(n2779), .Q(d_ff1_Z[7])
);
DFFRXLTS reg_Z0_Q_reg_8_ ( .D(n1861), .CK(n2846), .RN(n2719), .Q(d_ff1_Z[8])
);
DFFRXLTS reg_Z0_Q_reg_9_ ( .D(n1860), .CK(n2845), .RN(n2789), .Q(d_ff1_Z[9])
);
DFFRXLTS reg_Z0_Q_reg_10_ ( .D(n1859), .CK(n2845), .RN(n2753), .Q(
d_ff1_Z[10]) );
DFFRXLTS reg_Z0_Q_reg_11_ ( .D(n1858), .CK(n2794), .RN(n2789), .Q(
d_ff1_Z[11]) );
DFFRXLTS reg_Z0_Q_reg_12_ ( .D(n1857), .CK(n2798), .RN(n2790), .Q(
d_ff1_Z[12]) );
DFFRXLTS reg_Z0_Q_reg_13_ ( .D(n1856), .CK(n2846), .RN(n2789), .Q(
d_ff1_Z[13]) );
DFFRXLTS reg_Z0_Q_reg_14_ ( .D(n1855), .CK(n2845), .RN(n2782), .Q(
d_ff1_Z[14]) );
DFFRXLTS reg_Z0_Q_reg_15_ ( .D(n1854), .CK(n2028), .RN(n2035), .Q(
d_ff1_Z[15]) );
DFFRXLTS reg_Z0_Q_reg_16_ ( .D(n1853), .CK(n2845), .RN(n2789), .Q(
d_ff1_Z[16]) );
DFFRXLTS reg_Z0_Q_reg_17_ ( .D(n1852), .CK(n2794), .RN(n2787), .Q(
d_ff1_Z[17]) );
DFFRXLTS reg_Z0_Q_reg_18_ ( .D(n1851), .CK(n2794), .RN(n2035), .Q(
d_ff1_Z[18]) );
DFFRXLTS reg_Z0_Q_reg_19_ ( .D(n1850), .CK(n2797), .RN(n2778), .Q(
d_ff1_Z[19]) );
DFFRXLTS reg_Z0_Q_reg_20_ ( .D(n1849), .CK(n2028), .RN(n2778), .Q(
d_ff1_Z[20]) );
DFFRXLTS reg_Z0_Q_reg_21_ ( .D(n1848), .CK(n2794), .RN(n2778), .Q(
d_ff1_Z[21]) );
DFFRXLTS reg_Z0_Q_reg_22_ ( .D(n1847), .CK(n2798), .RN(n2778), .Q(
d_ff1_Z[22]) );
DFFRXLTS reg_Z0_Q_reg_23_ ( .D(n1846), .CK(n2798), .RN(n2778), .Q(
d_ff1_Z[23]) );
DFFRXLTS reg_Z0_Q_reg_24_ ( .D(n1845), .CK(n2797), .RN(n2778), .Q(
d_ff1_Z[24]) );
DFFRXLTS reg_Z0_Q_reg_25_ ( .D(n1844), .CK(n2028), .RN(n2778), .Q(
d_ff1_Z[25]) );
DFFRXLTS reg_Z0_Q_reg_26_ ( .D(n1843), .CK(n2798), .RN(n2778), .Q(
d_ff1_Z[26]) );
DFFRXLTS reg_Z0_Q_reg_27_ ( .D(n1842), .CK(n2845), .RN(n2778), .Q(
d_ff1_Z[27]) );
DFFRXLTS reg_Z0_Q_reg_28_ ( .D(n1841), .CK(n2845), .RN(n2778), .Q(
d_ff1_Z[28]) );
DFFRXLTS reg_Z0_Q_reg_29_ ( .D(n1840), .CK(n2797), .RN(n2777), .Q(
d_ff1_Z[29]) );
DFFRXLTS reg_Z0_Q_reg_30_ ( .D(n1839), .CK(n2028), .RN(n2777), .Q(
d_ff1_Z[30]) );
DFFRXLTS reg_Z0_Q_reg_31_ ( .D(n1838), .CK(n2846), .RN(n2777), .Q(
d_ff1_Z[31]) );
DFFRXLTS reg_Z0_Q_reg_32_ ( .D(n1837), .CK(n2028), .RN(n2777), .Q(
d_ff1_Z[32]) );
DFFRXLTS reg_Z0_Q_reg_33_ ( .D(n1836), .CK(n2846), .RN(n2777), .Q(
d_ff1_Z[33]) );
DFFRXLTS reg_Z0_Q_reg_34_ ( .D(n1835), .CK(n2797), .RN(n2777), .Q(
d_ff1_Z[34]) );
DFFRXLTS reg_Z0_Q_reg_35_ ( .D(n1834), .CK(n2799), .RN(n2777), .Q(
d_ff1_Z[35]) );
DFFRXLTS reg_Z0_Q_reg_36_ ( .D(n1833), .CK(n2803), .RN(n2777), .Q(
d_ff1_Z[36]) );
DFFRXLTS reg_Z0_Q_reg_37_ ( .D(n1832), .CK(n2804), .RN(n2777), .Q(
d_ff1_Z[37]) );
DFFRXLTS reg_Z0_Q_reg_38_ ( .D(n1831), .CK(n2801), .RN(n2777), .Q(
d_ff1_Z[38]) );
DFFRXLTS reg_Z0_Q_reg_39_ ( .D(n1830), .CK(n2799), .RN(n2776), .Q(
d_ff1_Z[39]) );
DFFRXLTS reg_Z0_Q_reg_40_ ( .D(n1829), .CK(n2803), .RN(n2776), .Q(
d_ff1_Z[40]) );
DFFRXLTS reg_Z0_Q_reg_41_ ( .D(n1828), .CK(n2804), .RN(n2776), .Q(
d_ff1_Z[41]) );
DFFRXLTS reg_Z0_Q_reg_42_ ( .D(n1827), .CK(n2801), .RN(n2776), .Q(
d_ff1_Z[42]) );
DFFRXLTS reg_Z0_Q_reg_43_ ( .D(n1826), .CK(n2799), .RN(n2776), .Q(
d_ff1_Z[43]) );
DFFRXLTS reg_Z0_Q_reg_44_ ( .D(n1825), .CK(n2803), .RN(n2776), .Q(
d_ff1_Z[44]) );
DFFRXLTS reg_Z0_Q_reg_45_ ( .D(n1824), .CK(n2803), .RN(n2776), .Q(
d_ff1_Z[45]) );
DFFRXLTS reg_Z0_Q_reg_46_ ( .D(n1823), .CK(n2801), .RN(n2776), .Q(
d_ff1_Z[46]) );
DFFRXLTS reg_Z0_Q_reg_47_ ( .D(n1822), .CK(n2801), .RN(n2776), .Q(
d_ff1_Z[47]) );
DFFRXLTS reg_Z0_Q_reg_48_ ( .D(n1821), .CK(n2799), .RN(n2776), .Q(
d_ff1_Z[48]) );
DFFRXLTS reg_Z0_Q_reg_49_ ( .D(n1820), .CK(n2025), .RN(n2775), .Q(
d_ff1_Z[49]) );
DFFRXLTS reg_Z0_Q_reg_50_ ( .D(n1819), .CK(n2799), .RN(n2775), .Q(
d_ff1_Z[50]) );
DFFRXLTS reg_Z0_Q_reg_51_ ( .D(n1818), .CK(n2804), .RN(n2775), .Q(
d_ff1_Z[51]) );
DFFRXLTS reg_Z0_Q_reg_52_ ( .D(n1817), .CK(n2804), .RN(n2775), .Q(
d_ff1_Z[52]) );
DFFRXLTS reg_Z0_Q_reg_53_ ( .D(n1816), .CK(n2802), .RN(n2775), .Q(
d_ff1_Z[53]) );
DFFRXLTS reg_Z0_Q_reg_54_ ( .D(n1815), .CK(n2025), .RN(n2775), .Q(
d_ff1_Z[54]) );
DFFRXLTS reg_Z0_Q_reg_55_ ( .D(n1814), .CK(n2801), .RN(n2775), .Q(
d_ff1_Z[55]) );
DFFRXLTS reg_Z0_Q_reg_56_ ( .D(n1813), .CK(n2804), .RN(n2775), .Q(
d_ff1_Z[56]) );
DFFRXLTS reg_Z0_Q_reg_57_ ( .D(n1812), .CK(n2802), .RN(n2775), .Q(
d_ff1_Z[57]) );
DFFRXLTS reg_Z0_Q_reg_58_ ( .D(n1811), .CK(n2025), .RN(n2775), .Q(
d_ff1_Z[58]) );
DFFRXLTS reg_Z0_Q_reg_59_ ( .D(n1810), .CK(n2801), .RN(n2774), .Q(
d_ff1_Z[59]) );
DFFRXLTS reg_Z0_Q_reg_60_ ( .D(n1809), .CK(n2804), .RN(n2774), .Q(
d_ff1_Z[60]) );
DFFRXLTS reg_Z0_Q_reg_61_ ( .D(n1808), .CK(n2803), .RN(n2774), .Q(
d_ff1_Z[61]) );
DFFRXLTS reg_Z0_Q_reg_62_ ( .D(n1807), .CK(n2802), .RN(n2774), .Q(
d_ff1_Z[62]) );
DFFRXLTS reg_Z0_Q_reg_63_ ( .D(n1806), .CK(n2025), .RN(n2774), .Q(
d_ff1_Z[63]) );
DFFRXLTS reg_shift_x_Q_reg_52_ ( .D(n1193), .CK(n2836), .RN(n2792), .Q(
d_ff3_sh_x_out[52]) );
DFFRXLTS reg_shift_x_Q_reg_54_ ( .D(n1191), .CK(n2047), .RN(n2737), .Q(
d_ff3_sh_x_out[54]) );
DFFRXLTS reg_shift_x_Q_reg_55_ ( .D(n1190), .CK(n2796), .RN(n2746), .Q(
d_ff3_sh_x_out[55]) );
DFFRXLTS reg_shift_x_Q_reg_1_ ( .D(n1305), .CK(n2857), .RN(n2727), .Q(
d_ff3_sh_x_out[1]) );
DFFRXLTS reg_shift_x_Q_reg_2_ ( .D(n1303), .CK(n2861), .RN(n2727), .Q(
d_ff3_sh_x_out[2]) );
DFFRXLTS reg_shift_x_Q_reg_3_ ( .D(n1301), .CK(n2852), .RN(n2726), .Q(
d_ff3_sh_x_out[3]) );
DFFRXLTS reg_shift_x_Q_reg_5_ ( .D(n1297), .CK(n2049), .RN(n2726), .Q(
d_ff3_sh_x_out[5]) );
DFFRXLTS reg_shift_x_Q_reg_6_ ( .D(n1295), .CK(n2855), .RN(n2726), .Q(
d_ff3_sh_x_out[6]) );
DFFRXLTS reg_shift_x_Q_reg_7_ ( .D(n1293), .CK(n2854), .RN(n2726), .Q(
d_ff3_sh_x_out[7]) );
DFFRXLTS reg_shift_x_Q_reg_8_ ( .D(n1291), .CK(n2857), .RN(n2792), .Q(
d_ff3_sh_x_out[8]) );
DFFRXLTS reg_shift_x_Q_reg_9_ ( .D(n1289), .CK(n2861), .RN(n2791), .Q(
d_ff3_sh_x_out[9]) );
DFFRXLTS reg_shift_x_Q_reg_10_ ( .D(n1287), .CK(n2861), .RN(n2786), .Q(
d_ff3_sh_x_out[10]) );
DFFRXLTS reg_shift_x_Q_reg_11_ ( .D(n1285), .CK(n2826), .RN(n2789), .Q(
d_ff3_sh_x_out[11]) );
DFFRXLTS reg_shift_x_Q_reg_14_ ( .D(n1279), .CK(n2853), .RN(n2725), .Q(
d_ff3_sh_x_out[14]) );
DFFRXLTS reg_shift_x_Q_reg_15_ ( .D(n1277), .CK(n2828), .RN(n2725), .Q(
d_ff3_sh_x_out[15]) );
DFFRXLTS reg_shift_x_Q_reg_17_ ( .D(n1273), .CK(n2851), .RN(n2725), .Q(
d_ff3_sh_x_out[17]) );
DFFRXLTS reg_shift_x_Q_reg_18_ ( .D(n1271), .CK(n2855), .RN(n2724), .Q(
d_ff3_sh_x_out[18]) );
DFFRXLTS reg_shift_x_Q_reg_19_ ( .D(n1269), .CK(n2854), .RN(n2724), .Q(
d_ff3_sh_x_out[19]) );
DFFRXLTS reg_shift_x_Q_reg_21_ ( .D(n1265), .CK(n2852), .RN(n2724), .Q(
d_ff3_sh_x_out[21]) );
DFFRXLTS reg_shift_x_Q_reg_23_ ( .D(n1261), .CK(n2049), .RN(n2781), .Q(
d_ff3_sh_x_out[23]) );
DFFRXLTS reg_shift_x_Q_reg_25_ ( .D(n1257), .CK(n2851), .RN(n2792), .Q(
d_ff3_sh_x_out[25]) );
DFFRXLTS reg_shift_x_Q_reg_26_ ( .D(n1255), .CK(n2856), .RN(n2791), .Q(
d_ff3_sh_x_out[26]) );
DFFRXLTS reg_shift_x_Q_reg_27_ ( .D(n1253), .CK(n2856), .RN(n2786), .Q(
d_ff3_sh_x_out[27]) );
DFFRXLTS reg_shift_x_Q_reg_29_ ( .D(n1249), .CK(n2856), .RN(n2723), .Q(
d_ff3_sh_x_out[29]) );
DFFRXLTS reg_shift_x_Q_reg_33_ ( .D(n1241), .CK(n2851), .RN(n2722), .Q(
d_ff3_sh_x_out[33]) );
DFFRXLTS reg_shift_x_Q_reg_37_ ( .D(n1233), .CK(n2858), .RN(n2722), .Q(
d_ff3_sh_x_out[37]) );
DFFRXLTS reg_shift_x_Q_reg_39_ ( .D(n1229), .CK(n2858), .RN(n2721), .Q(
d_ff3_sh_x_out[39]) );
DFFRXLTS reg_LUT_Q_reg_21_ ( .D(n1528), .CK(n2840), .RN(n2749), .Q(
d_ff3_LUT_out[21]) );
DFFRXLTS reg_shift_x_Q_reg_61_ ( .D(n1184), .CK(n2834), .RN(n2744), .Q(
d_ff3_sh_x_out[61]) );
DFFRXLTS reg_LUT_Q_reg_37_ ( .D(n1514), .CK(n2833), .RN(n2748), .Q(
d_ff3_LUT_out[37]) );
DFFRXLTS reg_LUT_Q_reg_7_ ( .D(n1542), .CK(n2024), .RN(n2751), .Q(
d_ff3_LUT_out[7]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_7_ ( .D(n1494), .CK(n2841), .RN(n2745),
.Q(d_ff2_Z[7]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_10_ ( .D(n1491), .CK(n2833), .RN(n2743),
.Q(d_ff2_Z[10]) );
DFFRXLTS reg_shift_y_Q_reg_58_ ( .D(n1315), .CK(n2832), .RN(n2746), .Q(
d_ff3_sh_y_out[58]) );
DFFRXLTS reg_shift_y_Q_reg_60_ ( .D(n1313), .CK(n2831), .RN(n2744), .Q(
d_ff3_sh_y_out[60]) );
DFFRXLTS reg_shift_x_Q_reg_53_ ( .D(n1192), .CK(n2841), .RN(n2745), .Q(
d_ff3_sh_x_out[53]) );
DFFRXLTS reg_shift_y_Q_reg_4_ ( .D(n1427), .CK(n2832), .RN(n2746), .Q(
d_ff3_sh_y_out[4]) );
DFFRXLTS reg_shift_y_Q_reg_12_ ( .D(n1411), .CK(n2831), .RN(n2735), .Q(
d_ff3_sh_y_out[12]) );
DFFRXLTS reg_shift_y_Q_reg_16_ ( .D(n1403), .CK(n2842), .RN(n2735), .Q(
d_ff3_sh_y_out[16]) );
DFFRXLTS reg_shift_y_Q_reg_20_ ( .D(n1395), .CK(n2843), .RN(n2036), .Q(
d_ff3_sh_y_out[20]) );
DFFRXLTS reg_shift_y_Q_reg_22_ ( .D(n1391), .CK(n2843), .RN(n2734), .Q(
d_ff3_sh_y_out[22]) );
DFFRXLTS reg_shift_y_Q_reg_24_ ( .D(n1387), .CK(n2830), .RN(n2734), .Q(
d_ff3_sh_y_out[24]) );
DFFRXLTS reg_shift_y_Q_reg_28_ ( .D(n1379), .CK(n2844), .RN(n2733), .Q(
d_ff3_sh_y_out[28]) );
DFFRXLTS reg_shift_y_Q_reg_30_ ( .D(n1375), .CK(n2794), .RN(n2733), .Q(
d_ff3_sh_y_out[30]) );
DFFRXLTS reg_shift_y_Q_reg_31_ ( .D(n1373), .CK(n2846), .RN(n2733), .Q(
d_ff3_sh_y_out[31]) );
DFFRXLTS reg_shift_y_Q_reg_32_ ( .D(n1371), .CK(n2028), .RN(n2732), .Q(
d_ff3_sh_y_out[32]) );
DFFRXLTS reg_shift_y_Q_reg_34_ ( .D(n1367), .CK(n2797), .RN(n2732), .Q(
d_ff3_sh_y_out[34]) );
DFFRXLTS reg_shift_y_Q_reg_35_ ( .D(n1365), .CK(n2846), .RN(n2732), .Q(
d_ff3_sh_y_out[35]) );
DFFRXLTS reg_shift_y_Q_reg_36_ ( .D(n1363), .CK(n2845), .RN(n2732), .Q(
d_ff3_sh_y_out[36]) );
DFFRXLTS reg_shift_y_Q_reg_38_ ( .D(n1359), .CK(n2797), .RN(n2731), .Q(
d_ff3_sh_y_out[38]) );
DFFRXLTS reg_shift_y_Q_reg_40_ ( .D(n1355), .CK(n2847), .RN(n2731), .Q(
d_ff3_sh_y_out[40]) );
DFFRXLTS reg_shift_y_Q_reg_41_ ( .D(n1353), .CK(n2847), .RN(n2731), .Q(
d_ff3_sh_y_out[41]) );
DFFRXLTS reg_shift_y_Q_reg_42_ ( .D(n1351), .CK(n2847), .RN(n2730), .Q(
d_ff3_sh_y_out[42]) );
DFFRXLTS reg_shift_y_Q_reg_43_ ( .D(n1349), .CK(n2847), .RN(n2730), .Q(
d_ff3_sh_y_out[43]) );
DFFRXLTS reg_shift_y_Q_reg_44_ ( .D(n1347), .CK(n2847), .RN(n2730), .Q(
d_ff3_sh_y_out[44]) );
DFFRXLTS reg_shift_y_Q_reg_45_ ( .D(n1345), .CK(n2848), .RN(n2730), .Q(
d_ff3_sh_y_out[45]) );
DFFRXLTS reg_shift_y_Q_reg_46_ ( .D(n1343), .CK(n2848), .RN(n2730), .Q(
d_ff3_sh_y_out[46]) );
DFFRXLTS reg_shift_y_Q_reg_47_ ( .D(n1341), .CK(n2848), .RN(n2729), .Q(
d_ff3_sh_y_out[47]) );
DFFRXLTS reg_shift_y_Q_reg_48_ ( .D(n1339), .CK(n2848), .RN(n2729), .Q(
d_ff3_sh_y_out[48]) );
DFFRXLTS reg_shift_y_Q_reg_49_ ( .D(n1337), .CK(n2848), .RN(n2729), .Q(
d_ff3_sh_y_out[49]) );
DFFRXLTS reg_shift_y_Q_reg_50_ ( .D(n1335), .CK(n2849), .RN(n2729), .Q(
d_ff3_sh_y_out[50]) );
DFFRXLTS reg_shift_y_Q_reg_51_ ( .D(n1333), .CK(n2849), .RN(n2729), .Q(
d_ff3_sh_y_out[51]) );
DFFRXLTS reg_shift_y_Q_reg_57_ ( .D(n1316), .CK(n2839), .RN(n2745), .Q(
d_ff3_sh_y_out[57]) );
DFFRXLTS reg_shift_y_Q_reg_59_ ( .D(n1314), .CK(n2833), .RN(n2737), .Q(
d_ff3_sh_y_out[59]) );
DFFRXLTS reg_shift_x_Q_reg_58_ ( .D(n1187), .CK(n2834), .RN(n2792), .Q(
d_ff3_sh_x_out[58]) );
DFFRXLTS reg_shift_x_Q_reg_60_ ( .D(n1185), .CK(n2834), .RN(n2737), .Q(
d_ff3_sh_x_out[60]) );
DFFRXLTS reg_shift_x_Q_reg_4_ ( .D(n1299), .CK(n2851), .RN(n2726), .Q(
d_ff3_sh_x_out[4]) );
DFFRXLTS reg_shift_x_Q_reg_12_ ( .D(n1283), .CK(n2828), .RN(n2790), .Q(
d_ff3_sh_x_out[12]) );
DFFRXLTS reg_shift_x_Q_reg_16_ ( .D(n1275), .CK(n2857), .RN(n2725), .Q(
d_ff3_sh_x_out[16]) );
DFFRXLTS reg_shift_x_Q_reg_20_ ( .D(n1267), .CK(n2861), .RN(n2724), .Q(
d_ff3_sh_x_out[20]) );
DFFRXLTS reg_shift_x_Q_reg_22_ ( .D(n1263), .CK(n2855), .RN(n2724), .Q(
d_ff3_sh_x_out[22]) );
DFFRXLTS reg_shift_x_Q_reg_24_ ( .D(n1259), .CK(n2854), .RN(n2789), .Q(
d_ff3_sh_x_out[24]) );
DFFRXLTS reg_shift_x_Q_reg_28_ ( .D(n1251), .CK(n2856), .RN(n2723), .Q(
d_ff3_sh_x_out[28]) );
DFFRXLTS reg_shift_x_Q_reg_30_ ( .D(n1247), .CK(n2856), .RN(n2723), .Q(
d_ff3_sh_x_out[30]) );
DFFRXLTS reg_shift_x_Q_reg_31_ ( .D(n1245), .CK(n2855), .RN(n2723), .Q(
d_ff3_sh_x_out[31]) );
DFFRXLTS reg_shift_x_Q_reg_32_ ( .D(n1243), .CK(n2854), .RN(n2723), .Q(
d_ff3_sh_x_out[32]) );
DFFRXLTS reg_shift_x_Q_reg_34_ ( .D(n1239), .CK(n2857), .RN(n2722), .Q(
d_ff3_sh_x_out[34]) );
DFFRXLTS reg_shift_x_Q_reg_35_ ( .D(n1237), .CK(n2861), .RN(n2722), .Q(
d_ff3_sh_x_out[35]) );
DFFRXLTS reg_shift_x_Q_reg_36_ ( .D(n1235), .CK(n2858), .RN(n2722), .Q(
d_ff3_sh_x_out[36]) );
DFFRXLTS reg_shift_x_Q_reg_38_ ( .D(n1231), .CK(n2858), .RN(n2721), .Q(
d_ff3_sh_x_out[38]) );
DFFRXLTS reg_shift_x_Q_reg_40_ ( .D(n1227), .CK(n2858), .RN(n2721), .Q(
d_ff3_sh_x_out[40]) );
DFFRXLTS reg_shift_x_Q_reg_41_ ( .D(n1225), .CK(n2031), .RN(n2721), .Q(
d_ff3_sh_x_out[41]) );
DFFRXLTS reg_shift_x_Q_reg_42_ ( .D(n1223), .CK(n2031), .RN(n2721), .Q(
d_ff3_sh_x_out[42]) );
DFFRXLTS reg_shift_x_Q_reg_43_ ( .D(n1221), .CK(n2031), .RN(n2720), .Q(
d_ff3_sh_x_out[43]) );
DFFRXLTS reg_shift_x_Q_reg_44_ ( .D(n1219), .CK(n2031), .RN(n2720), .Q(
d_ff3_sh_x_out[44]) );
DFFRXLTS reg_shift_x_Q_reg_45_ ( .D(n1217), .CK(n2031), .RN(n2720), .Q(
d_ff3_sh_x_out[45]) );
DFFRXLTS reg_shift_x_Q_reg_46_ ( .D(n1215), .CK(n2860), .RN(n2720), .Q(
d_ff3_sh_x_out[46]) );
DFFRXLTS reg_shift_x_Q_reg_47_ ( .D(n1213), .CK(n2860), .RN(n2720), .Q(
d_ff3_sh_x_out[47]) );
DFFRXLTS reg_shift_x_Q_reg_48_ ( .D(n1211), .CK(n2860), .RN(n2779), .Q(
d_ff3_sh_x_out[48]) );
DFFRXLTS reg_shift_x_Q_reg_49_ ( .D(n1209), .CK(n2860), .RN(n2719), .Q(
d_ff3_sh_x_out[49]) );
DFFRXLTS reg_shift_x_Q_reg_50_ ( .D(n1207), .CK(n2860), .RN(n2753), .Q(
d_ff3_sh_x_out[50]) );
DFFRXLTS reg_shift_x_Q_reg_51_ ( .D(n1205), .CK(n2852), .RN(n2790), .Q(
d_ff3_sh_x_out[51]) );
DFFRXLTS reg_shift_y_Q_reg_53_ ( .D(n1320), .CK(n2838), .RN(n2746), .Q(
d_ff3_sh_y_out[53]) );
DFFRXLTS reg_shift_x_Q_reg_57_ ( .D(n1188), .CK(n2833), .RN(n2746), .Q(
d_ff3_sh_x_out[57]) );
DFFRX1TS reg_LUT_Q_reg_8_ ( .D(n1541), .CK(n2853), .RN(n2751), .Q(
d_ff3_LUT_out[8]) );
DFFRX1TS reg_shift_y_Q_reg_52_ ( .D(n1321), .CK(n2830), .RN(n2747), .Q(
d_ff3_sh_y_out[52]) );
DFFRX1TS reg_LUT_Q_reg_1_ ( .D(n1548), .CK(n2827), .RN(n2751), .Q(
d_ff3_LUT_out[1]) );
DFFRX1TS reg_LUT_Q_reg_2_ ( .D(n1547), .CK(n2827), .RN(n2751), .Q(
d_ff3_LUT_out[2]) );
DFFRX1TS reg_LUT_Q_reg_3_ ( .D(n1546), .CK(n2827), .RN(n2751), .Q(
d_ff3_LUT_out[3]) );
DFFRX1TS reg_LUT_Q_reg_5_ ( .D(n1544), .CK(n2828), .RN(n2751), .Q(
d_ff3_LUT_out[5]) );
DFFRX1TS reg_LUT_Q_reg_6_ ( .D(n1543), .CK(n2816), .RN(n2751), .Q(
d_ff3_LUT_out[6]) );
DFFRX1TS reg_LUT_Q_reg_9_ ( .D(n1540), .CK(n2024), .RN(n2750), .Q(
d_ff3_LUT_out[9]) );
DFFRX1TS reg_LUT_Q_reg_11_ ( .D(n1538), .CK(n2816), .RN(n2750), .Q(
d_ff3_LUT_out[11]) );
DFFRX1TS reg_LUT_Q_reg_14_ ( .D(n1535), .CK(n2828), .RN(n2750), .Q(
d_ff3_LUT_out[14]) );
DFFRX1TS reg_LUT_Q_reg_15_ ( .D(n1534), .CK(n2053), .RN(n2750), .Q(
d_ff3_LUT_out[15]) );
DFFRX1TS reg_LUT_Q_reg_17_ ( .D(n1532), .CK(n2832), .RN(n2750), .Q(
d_ff3_LUT_out[17]) );
DFFRX1TS reg_LUT_Q_reg_18_ ( .D(n1531), .CK(n2839), .RN(n2750), .Q(
d_ff3_LUT_out[18]) );
DFFRX1TS reg_LUT_Q_reg_19_ ( .D(n1530), .CK(n2838), .RN(n2749), .Q(
d_ff3_LUT_out[19]) );
DFFRX1TS reg_LUT_Q_reg_23_ ( .D(n1526), .CK(n2830), .RN(n2749), .Q(
d_ff3_LUT_out[23]) );
DFFRX1TS reg_LUT_Q_reg_25_ ( .D(n1524), .CK(n2839), .RN(n2749), .Q(
d_ff3_LUT_out[25]) );
DFFRX1TS reg_LUT_Q_reg_27_ ( .D(n1522), .CK(n2838), .RN(n2749), .Q(
d_ff3_LUT_out[27]) );
DFFRX1TS reg_LUT_Q_reg_29_ ( .D(n1520), .CK(n2053), .RN(n2748), .Q(
d_ff3_LUT_out[29]) );
DFFRX1TS reg_LUT_Q_reg_33_ ( .D(n1517), .CK(n2053), .RN(n2748), .Q(
d_ff3_LUT_out[33]) );
DFFRX1TS reg_LUT_Q_reg_39_ ( .D(n1513), .CK(n2831), .RN(n2748), .Q(
d_ff3_LUT_out[39]) );
DFFRX1TS reg_LUT_Q_reg_54_ ( .D(n1504), .CK(n2840), .RN(n2747), .Q(
d_ff3_LUT_out[54]) );
DFFRX1TS reg_LUT_Q_reg_55_ ( .D(n1503), .CK(n2829), .RN(n2747), .Q(
d_ff3_LUT_out[55]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_52_ ( .D(n1449), .CK(n2838), .RN(n2739),
.Q(d_ff2_Z[52]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_53_ ( .D(n1448), .CK(n2830), .RN(n2739),
.Q(d_ff2_Z[53]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_56_ ( .D(n1445), .CK(n2830), .RN(n2739),
.Q(d_ff2_Z[56]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_57_ ( .D(n1444), .CK(n2840), .RN(n2739),
.Q(d_ff2_Z[57]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_58_ ( .D(n1443), .CK(n2829), .RN(n2739),
.Q(d_ff2_Z[58]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_60_ ( .D(n1441), .CK(n2839), .RN(n2738),
.Q(d_ff2_Z[60]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_61_ ( .D(n1440), .CK(n2838), .RN(n2738),
.Q(d_ff2_Z[61]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_62_ ( .D(n1439), .CK(n2830), .RN(n2738),
.Q(d_ff2_Z[62]) );
DFFRX1TS reg_LUT_Q_reg_42_ ( .D(n1511), .CK(n2047), .RN(n2748), .Q(
d_ff3_LUT_out[42]) );
DFFRX1TS d_ff4_Xn_Q_reg_62_ ( .D(n1615), .CK(n2827), .RN(n2752), .Q(
d_ff_Xn[62]) );
DFFRX1TS d_ff4_Xn_Q_reg_1_ ( .D(n1676), .CK(n2823), .RN(n2762), .Q(
d_ff_Xn[1]) );
DFFRX1TS d_ff4_Xn_Q_reg_2_ ( .D(n1675), .CK(n2815), .RN(n2762), .Q(
d_ff_Xn[2]) );
DFFRX1TS d_ff4_Xn_Q_reg_4_ ( .D(n1673), .CK(n2815), .RN(n2761), .Q(
d_ff_Xn[4]) );
DFFRX1TS d_ff4_Xn_Q_reg_5_ ( .D(n1672), .CK(n2815), .RN(n2761), .Q(
d_ff_Xn[5]) );
DFFRX1TS d_ff4_Xn_Q_reg_10_ ( .D(n1667), .CK(n2820), .RN(n2760), .Q(
d_ff_Xn[10]) );
DFFRX1TS d_ff4_Xn_Q_reg_12_ ( .D(n1665), .CK(n2817), .RN(n2760), .Q(
d_ff_Xn[12]) );
DFFRX1TS d_ff4_Xn_Q_reg_15_ ( .D(n1662), .CK(n2817), .RN(n2035), .Q(
d_ff_Xn[15]) );
DFFRX1TS d_ff4_Xn_Q_reg_16_ ( .D(n1661), .CK(n2817), .RN(n2779), .Q(
d_ff_Xn[16]) );
DFFRX1TS d_ff4_Xn_Q_reg_17_ ( .D(n1660), .CK(n2818), .RN(n2783), .Q(
d_ff_Xn[17]) );
DFFRX1TS d_ff4_Xn_Q_reg_18_ ( .D(n1659), .CK(n2818), .RN(n2759), .Q(
d_ff_Xn[18]) );
DFFRX1TS d_ff4_Xn_Q_reg_20_ ( .D(n1657), .CK(n2818), .RN(n2759), .Q(
d_ff_Xn[20]) );
DFFRX1TS d_ff4_Xn_Q_reg_21_ ( .D(n1656), .CK(n2818), .RN(n2038), .Q(
d_ff_Xn[21]) );
DFFRX1TS d_ff4_Xn_Q_reg_22_ ( .D(n1655), .CK(n2819), .RN(n2759), .Q(
d_ff_Xn[22]) );
DFFRX1TS d_ff4_Xn_Q_reg_23_ ( .D(n1654), .CK(n2819), .RN(n2038), .Q(
d_ff_Xn[23]) );
DFFRX1TS d_ff4_Xn_Q_reg_25_ ( .D(n1652), .CK(n2819), .RN(n2758), .Q(
d_ff_Xn[25]) );
DFFRX1TS d_ff4_Xn_Q_reg_27_ ( .D(n1650), .CK(n2816), .RN(n2758), .Q(
d_ff_Xn[27]) );
DFFRX1TS d_ff4_Xn_Q_reg_30_ ( .D(n1647), .CK(n2816), .RN(n2786), .Q(
d_ff_Xn[30]) );
DFFRX1TS d_ff4_Xn_Q_reg_33_ ( .D(n1644), .CK(n2821), .RN(n2786), .Q(
d_ff_Xn[33]) );
DFFRX1TS d_ff4_Xn_Q_reg_37_ ( .D(n1640), .CK(n2823), .RN(n2757), .Q(
d_ff_Xn[37]) );
DFFRX1TS d_ff4_Xn_Q_reg_38_ ( .D(n1639), .CK(n2812), .RN(n2757), .Q(
d_ff_Xn[38]) );
DFFRX1TS d_ff4_Xn_Q_reg_40_ ( .D(n1637), .CK(n2811), .RN(n2756), .Q(
d_ff_Xn[40]) );
DFFRX1TS d_ff4_Xn_Q_reg_44_ ( .D(n1633), .CK(n2811), .RN(n2755), .Q(
d_ff_Xn[44]) );
DFFRX1TS d_ff4_Xn_Q_reg_47_ ( .D(n1630), .CK(n2828), .RN(n2755), .Q(
d_ff_Xn[47]) );
DFFRX1TS d_ff4_Xn_Q_reg_50_ ( .D(n1627), .CK(n2823), .RN(n2754), .Q(
d_ff_Xn[50]) );
DFFRX1TS d_ff4_Xn_Q_reg_51_ ( .D(n1626), .CK(n2800), .RN(n2754), .Q(
d_ff_Xn[51]) );
DFFRX1TS d_ff4_Yn_Q_reg_1_ ( .D(n1740), .CK(n2806), .RN(n2767), .Q(
d_ff_Yn[1]) );
DFFRX1TS d_ff4_Yn_Q_reg_2_ ( .D(n1739), .CK(n2809), .RN(n2767), .Q(
d_ff_Yn[2]) );
DFFRX1TS d_ff4_Yn_Q_reg_3_ ( .D(n1738), .CK(n2026), .RN(n2767), .Q(
d_ff_Yn[3]) );
DFFRX1TS d_ff4_Yn_Q_reg_4_ ( .D(n1737), .CK(n2806), .RN(n2767), .Q(
d_ff_Yn[4]) );
DFFRX1TS d_ff4_Yn_Q_reg_5_ ( .D(n1736), .CK(n2806), .RN(n2767), .Q(
d_ff_Yn[5]) );
DFFRX1TS d_ff4_Yn_Q_reg_6_ ( .D(n1735), .CK(n2805), .RN(n2767), .Q(
d_ff_Yn[6]) );
DFFRX1TS d_ff4_Yn_Q_reg_7_ ( .D(n1734), .CK(n2805), .RN(n2767), .Q(
d_ff_Yn[7]) );
DFFRX1TS d_ff4_Yn_Q_reg_8_ ( .D(n1733), .CK(n2809), .RN(n2767), .Q(
d_ff_Yn[8]) );
DFFRX1TS d_ff4_Yn_Q_reg_9_ ( .D(n1732), .CK(n2805), .RN(n2767), .Q(
d_ff_Yn[9]) );
DFFRX1TS d_ff4_Yn_Q_reg_10_ ( .D(n1731), .CK(n2809), .RN(n2767), .Q(
d_ff_Yn[10]) );
DFFRX1TS d_ff4_Yn_Q_reg_11_ ( .D(n1730), .CK(n2807), .RN(n2766), .Q(
d_ff_Yn[11]) );
DFFRX1TS d_ff4_Yn_Q_reg_12_ ( .D(n1729), .CK(n2809), .RN(n2766), .Q(
d_ff_Yn[12]) );
DFFRX1TS d_ff4_Yn_Q_reg_13_ ( .D(n1728), .CK(n2026), .RN(n2766), .Q(
d_ff_Yn[13]) );
DFFRX1TS d_ff4_Yn_Q_reg_14_ ( .D(n1727), .CK(n2026), .RN(n2766), .Q(
d_ff_Yn[14]) );
DFFRX1TS d_ff4_Yn_Q_reg_15_ ( .D(n1726), .CK(n2805), .RN(n2766), .Q(
d_ff_Yn[15]) );
DFFRX1TS d_ff4_Yn_Q_reg_16_ ( .D(n1725), .CK(n2809), .RN(n2766), .Q(
d_ff_Yn[16]) );
DFFRX1TS d_ff4_Yn_Q_reg_17_ ( .D(n1724), .CK(n2026), .RN(n2766), .Q(
d_ff_Yn[17]) );
DFFRX1TS d_ff4_Yn_Q_reg_18_ ( .D(n1723), .CK(n2806), .RN(n2766), .Q(
d_ff_Yn[18]) );
DFFRX1TS d_ff4_Yn_Q_reg_19_ ( .D(n1722), .CK(n2806), .RN(n2766), .Q(
d_ff_Yn[19]) );
DFFRX1TS d_ff4_Yn_Q_reg_20_ ( .D(n1721), .CK(n2809), .RN(n2766), .Q(
d_ff_Yn[20]) );
DFFRX1TS d_ff4_Yn_Q_reg_21_ ( .D(n1720), .CK(n2805), .RN(n2765), .Q(
d_ff_Yn[21]) );
DFFRX1TS d_ff4_Yn_Q_reg_22_ ( .D(n1719), .CK(n2807), .RN(n2765), .Q(
d_ff_Yn[22]) );
DFFRX1TS d_ff4_Yn_Q_reg_23_ ( .D(n1718), .CK(n2805), .RN(n2765), .Q(
d_ff_Yn[23]) );
DFFRX1TS d_ff4_Yn_Q_reg_24_ ( .D(n1717), .CK(n2807), .RN(n2765), .Q(
d_ff_Yn[24]) );
DFFRX1TS d_ff4_Yn_Q_reg_25_ ( .D(n1716), .CK(n2807), .RN(n2765), .Q(
d_ff_Yn[25]) );
DFFRX1TS d_ff4_Yn_Q_reg_26_ ( .D(n1715), .CK(n2026), .RN(n2765), .Q(
d_ff_Yn[26]) );
DFFRX1TS d_ff4_Yn_Q_reg_27_ ( .D(n1714), .CK(n2821), .RN(n2765), .Q(
d_ff_Yn[27]) );
DFFRX1TS d_ff4_Yn_Q_reg_28_ ( .D(n1713), .CK(n2821), .RN(n2765), .Q(
d_ff_Yn[28]) );
DFFRX1TS d_ff4_Yn_Q_reg_29_ ( .D(n1712), .CK(n2814), .RN(n2765), .Q(
d_ff_Yn[29]) );
DFFRX1TS d_ff4_Yn_Q_reg_30_ ( .D(n1711), .CK(n2027), .RN(n2765), .Q(
d_ff_Yn[30]) );
DFFRX1TS d_ff4_Yn_Q_reg_31_ ( .D(n1710), .CK(n2812), .RN(n2785), .Q(
d_ff_Yn[31]) );
DFFRX1TS d_ff4_Yn_Q_reg_32_ ( .D(n1709), .CK(n2027), .RN(n2784), .Q(
d_ff_Yn[32]) );
DFFRX1TS d_ff4_Yn_Q_reg_33_ ( .D(n1708), .CK(n2814), .RN(n2791), .Q(
d_ff_Yn[33]) );
DFFRX1TS d_ff4_Yn_Q_reg_34_ ( .D(n1707), .CK(n2050), .RN(n2785), .Q(
d_ff_Yn[34]) );
DFFRX1TS d_ff4_Yn_Q_reg_35_ ( .D(n1706), .CK(n2812), .RN(n2784), .Q(
d_ff_Yn[35]) );
DFFRX1TS d_ff4_Yn_Q_reg_36_ ( .D(n1705), .CK(n2027), .RN(n2038), .Q(
d_ff_Yn[36]) );
DFFRX1TS d_ff4_Yn_Q_reg_37_ ( .D(n1704), .CK(n2050), .RN(n2785), .Q(
d_ff_Yn[37]) );
DFFRX1TS d_ff4_Yn_Q_reg_38_ ( .D(n1703), .CK(n2821), .RN(n2784), .Q(
d_ff_Yn[38]) );
DFFRX1TS d_ff4_Yn_Q_reg_39_ ( .D(n1702), .CK(n2821), .RN(n2781), .Q(
d_ff_Yn[39]) );
DFFRX1TS d_ff4_Yn_Q_reg_40_ ( .D(n1701), .CK(n2821), .RN(n2785), .Q(
d_ff_Yn[40]) );
DFFRX1TS d_ff4_Yn_Q_reg_41_ ( .D(n1700), .CK(n2822), .RN(n2764), .Q(
d_ff_Yn[41]) );
DFFRX1TS d_ff4_Yn_Q_reg_42_ ( .D(n1699), .CK(n2814), .RN(n2764), .Q(
d_ff_Yn[42]) );
DFFRX1TS d_ff4_Yn_Q_reg_43_ ( .D(n1698), .CK(n2027), .RN(n2764), .Q(
d_ff_Yn[43]) );
DFFRX1TS d_ff4_Yn_Q_reg_44_ ( .D(n1697), .CK(n2823), .RN(n2764), .Q(
d_ff_Yn[44]) );
DFFRX1TS d_ff4_Yn_Q_reg_45_ ( .D(n1696), .CK(n2814), .RN(n2764), .Q(
d_ff_Yn[45]) );
DFFRX1TS d_ff4_Yn_Q_reg_46_ ( .D(n1695), .CK(n2027), .RN(n2764), .Q(
d_ff_Yn[46]) );
DFFRX1TS d_ff4_Yn_Q_reg_47_ ( .D(n1694), .CK(n2813), .RN(n2764), .Q(
d_ff_Yn[47]) );
DFFRX1TS d_ff4_Yn_Q_reg_48_ ( .D(n1693), .CK(n2813), .RN(n2764), .Q(
d_ff_Yn[48]) );
DFFRX1TS d_ff4_Yn_Q_reg_49_ ( .D(n1692), .CK(n2813), .RN(n2764), .Q(
d_ff_Yn[49]) );
DFFRX1TS d_ff4_Yn_Q_reg_50_ ( .D(n1691), .CK(n2813), .RN(n2764), .Q(
d_ff_Yn[50]) );
DFFRX1TS d_ff4_Yn_Q_reg_51_ ( .D(n1690), .CK(n2813), .RN(n2763), .Q(
d_ff_Yn[51]) );
DFFRX1TS d_ff4_Yn_Q_reg_54_ ( .D(n1687), .CK(n2813), .RN(n2763), .Q(
d_ff_Yn[54]) );
DFFRX1TS d_ff4_Yn_Q_reg_55_ ( .D(n1686), .CK(n2813), .RN(n2763), .Q(
d_ff_Yn[55]) );
DFFRX1TS d_ff4_Yn_Q_reg_56_ ( .D(n1685), .CK(n2813), .RN(n2763), .Q(
d_ff_Yn[56]) );
DFFRX1TS d_ff4_Yn_Q_reg_57_ ( .D(n1684), .CK(n2823), .RN(n2763), .Q(
d_ff_Yn[57]) );
DFFRX1TS d_ff4_Yn_Q_reg_59_ ( .D(n1682), .CK(n2027), .RN(n2763), .Q(
d_ff_Yn[59]) );
DFFRX1TS d_ff4_Yn_Q_reg_61_ ( .D(n1680), .CK(n2814), .RN(n2762), .Q(
d_ff_Yn[61]) );
DFFRX1TS d_ff4_Yn_Q_reg_62_ ( .D(n1679), .CK(n2050), .RN(n2762), .Q(
d_ff_Yn[62]) );
DFFRX1TS d_ff4_Xn_Q_reg_57_ ( .D(n1620), .CK(n2024), .RN(n2719), .Q(
d_ff_Xn[57]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_1_ ( .D(n1306), .CK(n2850), .RN(n2727),
.Q(d_ff2_X[1]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_2_ ( .D(n1304), .CK(n2861), .RN(n2727),
.Q(d_ff2_X[2]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_4_ ( .D(n1300), .CK(n2049), .RN(n2726),
.Q(d_ff2_X[4]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_5_ ( .D(n1298), .CK(n2049), .RN(n2726),
.Q(d_ff2_X[5]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_10_ ( .D(n1288), .CK(n2855), .RN(n2784),
.Q(d_ff2_X[10]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_12_ ( .D(n1284), .CK(n2853), .RN(n2037),
.Q(d_ff2_X[12]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_15_ ( .D(n1278), .CK(n2853), .RN(n2725),
.Q(d_ff2_X[15]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_16_ ( .D(n1276), .CK(n2024), .RN(n2725),
.Q(d_ff2_X[16]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_17_ ( .D(n1274), .CK(n2857), .RN(n2725),
.Q(d_ff2_X[17]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_18_ ( .D(n1272), .CK(n2852), .RN(n2725),
.Q(d_ff2_X[18]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_20_ ( .D(n1268), .CK(n2049), .RN(n2724),
.Q(d_ff2_X[20]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_21_ ( .D(n1266), .CK(n2861), .RN(n2724),
.Q(d_ff2_X[21]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_22_ ( .D(n1264), .CK(n2855), .RN(n2724),
.Q(d_ff2_X[22]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_23_ ( .D(n1262), .CK(n2854), .RN(n2724),
.Q(d_ff2_X[23]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_25_ ( .D(n1258), .CK(n2857), .RN(n2790),
.Q(d_ff2_X[25]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_27_ ( .D(n1254), .CK(n2856), .RN(n2784),
.Q(d_ff2_X[27]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_30_ ( .D(n1248), .CK(n2856), .RN(n2723),
.Q(d_ff2_X[30]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_33_ ( .D(n1242), .CK(n2852), .RN(n2723),
.Q(d_ff2_X[33]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_37_ ( .D(n1234), .CK(n2862), .RN(n2722),
.Q(d_ff2_X[37]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_38_ ( .D(n1232), .CK(n2862), .RN(n2722),
.Q(d_ff2_X[38]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_40_ ( .D(n1228), .CK(n2862), .RN(n2721),
.Q(d_ff2_X[40]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_44_ ( .D(n1220), .CK(n2031), .RN(n2720),
.Q(d_ff2_X[44]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_47_ ( .D(n1214), .CK(n2860), .RN(n2720),
.Q(d_ff2_X[47]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_50_ ( .D(n1208), .CK(n2860), .RN(n2779),
.Q(d_ff2_X[50]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_51_ ( .D(n1206), .CK(n2860), .RN(n2719),
.Q(d_ff2_X[51]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_63_ ( .D(n1182), .CK(n2862), .RN(n2718),
.Q(d_ff2_X[63]) );
DFFRX1TS d_ff4_Yn_Q_reg_0_ ( .D(n1741), .CK(n2807), .RN(n2768), .Q(
d_ff_Yn[0]) );
DFFRX1TS reg_sign_Q_reg_0_ ( .D(n1437), .CK(n2840), .RN(n2738), .Q(
d_ff3_sign_out) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_0_ ( .D(n1308), .CK(n2850), .RN(n2727),
.Q(d_ff2_X[0]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_3_ ( .D(n1302), .CK(n2049), .RN(n2727),
.Q(d_ff2_X[3]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_6_ ( .D(n1296), .CK(n2851), .RN(n2726),
.Q(d_ff2_X[6]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_7_ ( .D(n1294), .CK(n2854), .RN(n2726),
.Q(d_ff2_X[7]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_8_ ( .D(n1292), .CK(n2857), .RN(n2726),
.Q(d_ff2_X[8]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_9_ ( .D(n1290), .CK(n2852), .RN(n2792),
.Q(d_ff2_X[9]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_11_ ( .D(n1286), .CK(n2861), .RN(n2036),
.Q(d_ff2_X[11]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_13_ ( .D(n1282), .CK(n2828), .RN(n2792),
.Q(d_ff2_X[13]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_14_ ( .D(n1280), .CK(n2820), .RN(n2725),
.Q(d_ff2_X[14]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_19_ ( .D(n1270), .CK(n2851), .RN(n2724),
.Q(d_ff2_X[19]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_24_ ( .D(n1260), .CK(n2852), .RN(n2037),
.Q(d_ff2_X[24]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_26_ ( .D(n1256), .CK(n2049), .RN(n2781),
.Q(d_ff2_X[26]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_28_ ( .D(n1252), .CK(n2856), .RN(n2036),
.Q(d_ff2_X[28]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_29_ ( .D(n1250), .CK(n2856), .RN(n2723),
.Q(d_ff2_X[29]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_31_ ( .D(n1246), .CK(n2856), .RN(n2723),
.Q(d_ff2_X[31]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_32_ ( .D(n1244), .CK(n2049), .RN(n2723),
.Q(d_ff2_X[32]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_34_ ( .D(n1240), .CK(n2861), .RN(n2722),
.Q(d_ff2_X[34]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_35_ ( .D(n1238), .CK(n2851), .RN(n2722),
.Q(d_ff2_X[35]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_36_ ( .D(n1236), .CK(n2855), .RN(n2722),
.Q(d_ff2_X[36]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_39_ ( .D(n1230), .CK(n2862), .RN(n2721),
.Q(d_ff2_X[39]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_41_ ( .D(n1226), .CK(n2858), .RN(n2721),
.Q(d_ff2_X[41]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_42_ ( .D(n1224), .CK(n2031), .RN(n2721),
.Q(d_ff2_X[42]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_43_ ( .D(n1222), .CK(n2031), .RN(n2721),
.Q(d_ff2_X[43]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_45_ ( .D(n1218), .CK(n2031), .RN(n2720),
.Q(d_ff2_X[45]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_46_ ( .D(n1216), .CK(n2031), .RN(n2720),
.Q(d_ff2_X[46]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_48_ ( .D(n1212), .CK(n2860), .RN(n2720),
.Q(d_ff2_X[48]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_49_ ( .D(n1210), .CK(n2860), .RN(n2753),
.Q(d_ff2_X[49]) );
DFFRX1TS d_ff4_Xn_Q_reg_52_ ( .D(n1625), .CK(n2051), .RN(n2754), .Q(
d_ff_Xn[52]) );
DFFRX1TS d_ff4_Yn_Q_reg_52_ ( .D(n1689), .CK(n2813), .RN(n2763), .Q(
d_ff_Yn[52]) );
DFFRX1TS d_ff4_Yn_Q_reg_53_ ( .D(n1688), .CK(n2813), .RN(n2763), .Q(
d_ff_Yn[53]) );
DFFRX1TS d_ff4_Yn_Q_reg_58_ ( .D(n1683), .CK(n2822), .RN(n2763), .Q(
d_ff_Yn[58]) );
DFFRX1TS d_ff4_Yn_Q_reg_60_ ( .D(n1681), .CK(n2811), .RN(n2763), .Q(
d_ff_Yn[60]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_0_ ( .D(n1436), .CK(n2840), .RN(n2738),
.Q(d_ff2_Y[0]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_1_ ( .D(n1434), .CK(n2829), .RN(n2738),
.Q(d_ff2_Y[1]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_2_ ( .D(n1432), .CK(n2053), .RN(n2783),
.Q(d_ff2_Y[2]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_3_ ( .D(n1430), .CK(n2832), .RN(n2783),
.Q(d_ff2_Y[3]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_4_ ( .D(n1428), .CK(n2839), .RN(n2783),
.Q(d_ff2_Y[4]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_5_ ( .D(n1426), .CK(n2030), .RN(n2783),
.Q(d_ff2_Y[5]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_6_ ( .D(n1424), .CK(n2030), .RN(n2038),
.Q(d_ff2_Y[6]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_7_ ( .D(n1422), .CK(n2030), .RN(n2736),
.Q(d_ff2_Y[7]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_8_ ( .D(n1420), .CK(n2030), .RN(n2736),
.Q(d_ff2_Y[8]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_9_ ( .D(n1418), .CK(n2030), .RN(n2736),
.Q(d_ff2_Y[9]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_10_ ( .D(n1416), .CK(n2810), .RN(n2736),
.Q(d_ff2_Y[10]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_11_ ( .D(n1414), .CK(n2835), .RN(n2736),
.Q(d_ff2_Y[11]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_12_ ( .D(n1412), .CK(n2836), .RN(n2735),
.Q(d_ff2_Y[12]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_13_ ( .D(n1410), .CK(n2841), .RN(n2735),
.Q(d_ff2_Y[13]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_14_ ( .D(n1408), .CK(n2831), .RN(n2735),
.Q(d_ff2_Y[14]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_15_ ( .D(n1406), .CK(n2842), .RN(n2735),
.Q(d_ff2_Y[15]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_16_ ( .D(n1404), .CK(n2842), .RN(n2735),
.Q(d_ff2_Y[16]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_17_ ( .D(n1402), .CK(n2842), .RN(n2791),
.Q(d_ff2_Y[17]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_18_ ( .D(n1400), .CK(n2842), .RN(n2791),
.Q(d_ff2_Y[18]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_19_ ( .D(n1398), .CK(n2842), .RN(n2744),
.Q(d_ff2_Y[19]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_20_ ( .D(n1396), .CK(n2843), .RN(n2782),
.Q(d_ff2_Y[20]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_21_ ( .D(n1394), .CK(n2843), .RN(n2745),
.Q(d_ff2_Y[21]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_22_ ( .D(n1392), .CK(n2843), .RN(n2734),
.Q(d_ff2_Y[22]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_23_ ( .D(n1390), .CK(n2843), .RN(n2734),
.Q(d_ff2_Y[23]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_24_ ( .D(n1388), .CK(n2843), .RN(n2734),
.Q(d_ff2_Y[24]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_25_ ( .D(n1386), .CK(n2844), .RN(n2734),
.Q(d_ff2_Y[25]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_26_ ( .D(n1384), .CK(n2844), .RN(n2734),
.Q(d_ff2_Y[26]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_27_ ( .D(n1382), .CK(n2844), .RN(n2733),
.Q(d_ff2_Y[27]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_28_ ( .D(n1380), .CK(n2844), .RN(n2733),
.Q(d_ff2_Y[28]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_29_ ( .D(n1378), .CK(n2844), .RN(n2733),
.Q(d_ff2_Y[29]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_30_ ( .D(n1376), .CK(n2028), .RN(n2733),
.Q(d_ff2_Y[30]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_31_ ( .D(n1374), .CK(n2794), .RN(n2733),
.Q(d_ff2_Y[31]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_32_ ( .D(n1372), .CK(n2798), .RN(n2732),
.Q(d_ff2_Y[32]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_33_ ( .D(n1370), .CK(n2845), .RN(n2732),
.Q(d_ff2_Y[33]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_34_ ( .D(n1368), .CK(n2846), .RN(n2732),
.Q(d_ff2_Y[34]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_35_ ( .D(n1366), .CK(n2798), .RN(n2732),
.Q(d_ff2_Y[35]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_36_ ( .D(n1364), .CK(n2028), .RN(n2732),
.Q(d_ff2_Y[36]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_37_ ( .D(n1362), .CK(n2845), .RN(n2731),
.Q(d_ff2_Y[37]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_38_ ( .D(n1360), .CK(n2028), .RN(n2731),
.Q(d_ff2_Y[38]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_39_ ( .D(n1358), .CK(n2794), .RN(n2731),
.Q(d_ff2_Y[39]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_40_ ( .D(n1356), .CK(n2847), .RN(n2731),
.Q(d_ff2_Y[40]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_41_ ( .D(n1354), .CK(n2847), .RN(n2731),
.Q(d_ff2_Y[41]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_42_ ( .D(n1352), .CK(n2847), .RN(n2730),
.Q(d_ff2_Y[42]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_43_ ( .D(n1350), .CK(n2847), .RN(n2730),
.Q(d_ff2_Y[43]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_44_ ( .D(n1348), .CK(n2847), .RN(n2730),
.Q(d_ff2_Y[44]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_45_ ( .D(n1346), .CK(n2848), .RN(n2730),
.Q(d_ff2_Y[45]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_46_ ( .D(n1344), .CK(n2848), .RN(n2730),
.Q(d_ff2_Y[46]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_47_ ( .D(n1342), .CK(n2848), .RN(n2729),
.Q(d_ff2_Y[47]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_48_ ( .D(n1340), .CK(n2848), .RN(n2729),
.Q(d_ff2_Y[48]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_49_ ( .D(n1338), .CK(n2848), .RN(n2729),
.Q(d_ff2_Y[49]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_50_ ( .D(n1336), .CK(n2849), .RN(n2729),
.Q(d_ff2_Y[50]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_51_ ( .D(n1334), .CK(n2849), .RN(n2729),
.Q(d_ff2_Y[51]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_63_ ( .D(n1310), .CK(n2850), .RN(n2727),
.Q(d_ff2_Y[63]) );
DFFRX1TS d_ff4_Xn_Q_reg_56_ ( .D(n1621), .CK(n2051), .RN(n2753), .Q(
d_ff_Xn[56]) );
DFFRX1TS d_ff4_Xn_Q_reg_58_ ( .D(n1619), .CK(n2820), .RN(n2790), .Q(
d_ff_Xn[58]) );
DFFRX1TS d_ff4_Xn_Q_reg_59_ ( .D(n1618), .CK(n2816), .RN(n2752), .Q(
d_ff_Xn[59]) );
DFFRX1TS d_ff4_Xn_Q_reg_60_ ( .D(n1617), .CK(n2853), .RN(n2752), .Q(
d_ff_Xn[60]) );
DFFRX1TS d_ff4_Xn_Q_reg_61_ ( .D(n1616), .CK(n2828), .RN(n2752), .Q(
d_ff_Xn[61]) );
DFFRX1TS d_ff4_Xn_Q_reg_3_ ( .D(n1674), .CK(n2815), .RN(n2762), .Q(
d_ff_Xn[3]) );
DFFRX1TS d_ff4_Xn_Q_reg_6_ ( .D(n1671), .CK(n2815), .RN(n2761), .Q(
d_ff_Xn[6]) );
DFFRX1TS d_ff4_Xn_Q_reg_7_ ( .D(n1670), .CK(n2024), .RN(n2761), .Q(
d_ff_Xn[7]) );
DFFRX1TS d_ff4_Xn_Q_reg_8_ ( .D(n1669), .CK(n2024), .RN(n2761), .Q(
d_ff_Xn[8]) );
DFFRX1TS d_ff4_Xn_Q_reg_9_ ( .D(n1668), .CK(n2816), .RN(n2760), .Q(
d_ff_Xn[9]) );
DFFRX1TS d_ff4_Xn_Q_reg_11_ ( .D(n1666), .CK(n2853), .RN(n2760), .Q(
d_ff_Xn[11]) );
DFFRX1TS d_ff4_Xn_Q_reg_13_ ( .D(n1664), .CK(n2817), .RN(n2760), .Q(
d_ff_Xn[13]) );
DFFRX1TS d_ff4_Xn_Q_reg_14_ ( .D(n1663), .CK(n2817), .RN(n2783), .Q(
d_ff_Xn[14]) );
DFFRX1TS d_ff4_Xn_Q_reg_19_ ( .D(n1658), .CK(n2818), .RN(n2759), .Q(
d_ff_Xn[19]) );
DFFRX1TS d_ff4_Xn_Q_reg_24_ ( .D(n1653), .CK(n2819), .RN(n2758), .Q(
d_ff_Xn[24]) );
DFFRX1TS d_ff4_Xn_Q_reg_26_ ( .D(n1651), .CK(n2819), .RN(n2758), .Q(
d_ff_Xn[26]) );
DFFRX1TS d_ff4_Xn_Q_reg_28_ ( .D(n1649), .CK(n2820), .RN(n2758), .Q(
d_ff_Xn[28]) );
DFFRX1TS d_ff4_Xn_Q_reg_29_ ( .D(n1648), .CK(n2828), .RN(n2035), .Q(
d_ff_Xn[29]) );
DFFRX1TS d_ff4_Xn_Q_reg_31_ ( .D(n1646), .CK(n2827), .RN(n2035), .Q(
d_ff_Xn[31]) );
DFFRX1TS d_ff4_Xn_Q_reg_32_ ( .D(n1645), .CK(n2050), .RN(n2037), .Q(
d_ff_Xn[32]) );
DFFRX1TS d_ff4_Xn_Q_reg_34_ ( .D(n1643), .CK(n2812), .RN(n2757), .Q(
d_ff_Xn[34]) );
DFFRX1TS d_ff4_Xn_Q_reg_35_ ( .D(n1642), .CK(n2821), .RN(n2757), .Q(
d_ff_Xn[35]) );
DFFRX1TS d_ff4_Xn_Q_reg_36_ ( .D(n1641), .CK(n2823), .RN(n2757), .Q(
d_ff_Xn[36]) );
DFFRX1TS d_ff4_Xn_Q_reg_39_ ( .D(n1638), .CK(n2823), .RN(n2756), .Q(
d_ff_Xn[39]) );
DFFRX1TS d_ff4_Xn_Q_reg_41_ ( .D(n1636), .CK(n2812), .RN(n2756), .Q(
d_ff_Xn[41]) );
DFFRX1TS d_ff4_Xn_Q_reg_42_ ( .D(n1635), .CK(n2050), .RN(n2756), .Q(
d_ff_Xn[42]) );
DFFRX1TS d_ff4_Xn_Q_reg_43_ ( .D(n1634), .CK(n2814), .RN(n2756), .Q(
d_ff_Xn[43]) );
DFFRX1TS d_ff4_Xn_Q_reg_45_ ( .D(n1632), .CK(n2822), .RN(n2755), .Q(
d_ff_Xn[45]) );
DFFRX1TS d_ff4_Xn_Q_reg_46_ ( .D(n1631), .CK(n2050), .RN(n2755), .Q(
d_ff_Xn[46]) );
DFFRX1TS d_ff4_Xn_Q_reg_48_ ( .D(n1629), .CK(n2820), .RN(n2755), .Q(
d_ff_Xn[48]) );
DFFRX1TS d_ff4_Xn_Q_reg_49_ ( .D(n1628), .CK(n2862), .RN(n2754), .Q(
d_ff_Xn[49]) );
DFFRX1TS d_ff4_Xn_Q_reg_53_ ( .D(n1624), .CK(n2051), .RN(n2754), .Q(
d_ff_Xn[53]) );
DFFRX1TS d_ff4_Xn_Q_reg_54_ ( .D(n1623), .CK(n2051), .RN(n2785), .Q(
d_ff_Xn[54]) );
DFFRX1TS d_ff4_Xn_Q_reg_55_ ( .D(n1622), .CK(n2051), .RN(n2785), .Q(
d_ff_Xn[55]) );
DFFRX1TS d_ff4_Xn_Q_reg_0_ ( .D(n1677), .CK(n2027), .RN(n2762), .Q(
d_ff_Xn[0]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_62_ ( .D(n1194), .CK(n2862), .RN(n2718),
.Q(d_ff2_X[62]) );
DFFRX1TS d_ff4_Yn_Q_reg_63_ ( .D(n1678), .CK(n2812), .RN(n2762), .Q(
d_ff_Yn[63]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_63_ ( .D(n1438), .CK(n2829), .RN(n2738),
.Q(d_ff2_Z[63]) );
DFFRX1TS d_ff4_Xn_Q_reg_63_ ( .D(n1614), .CK(n2024), .RN(n2752), .Q(
d_ff_Xn[63]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_62_ ( .D(n1322), .CK(n2850), .RN(n2727),
.Q(d_ff2_Y[62]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_54_ ( .D(n1202), .CK(n2861), .RN(n2782),
.Q(d_ff2_X[54]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_55_ ( .D(n1201), .CK(n2851), .RN(n2718),
.Q(d_ff2_X[55]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_54_ ( .D(n1330), .CK(n2849), .RN(n2728),
.Q(d_ff2_Y[54]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_55_ ( .D(n1329), .CK(n2849), .RN(n2728),
.Q(d_ff2_Y[55]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_53_ ( .D(n1203), .CK(n2855), .RN(n2779),
.Q(d_ff2_X[53]) );
DFFRX1TS inst_CORDIC_FSM_v3_state_reg_reg_5_ ( .D(
inst_CORDIC_FSM_v3_state_next[5]), .CK(n2794), .RN(n2780), .Q(
inst_CORDIC_FSM_v3_state_reg[5]) );
DFFRX1TS inst_CORDIC_FSM_v3_state_reg_reg_4_ ( .D(
inst_CORDIC_FSM_v3_state_next[4]), .CK(n2846), .RN(n2781), .Q(
inst_CORDIC_FSM_v3_state_reg[4]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_59_ ( .D(n1197), .CK(n2854), .RN(n2718),
.Q(d_ff2_X[59]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_61_ ( .D(n1195), .CK(n2862), .RN(n2718),
.Q(d_ff2_X[61]) );
DFFRX1TS inst_CORDIC_FSM_v3_state_reg_reg_2_ ( .D(
inst_CORDIC_FSM_v3_state_next[2]), .CK(n2795), .RN(n2780), .Q(
inst_CORDIC_FSM_v3_state_reg[2]) );
DFFRX1TS inst_CORDIC_FSM_v3_state_reg_reg_1_ ( .D(
inst_CORDIC_FSM_v3_state_next[1]), .CK(n2846), .RN(n2780), .Q(
inst_CORDIC_FSM_v3_state_reg[1]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_59_ ( .D(n1325), .CK(n2850), .RN(n2728),
.Q(d_ff2_Y[59]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_61_ ( .D(n1323), .CK(n2850), .RN(n2728),
.Q(d_ff2_Y[61]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_57_ ( .D(n1327), .CK(n2849), .RN(n2728),
.Q(d_ff2_Y[57]) );
DFFRX2TS reg_val_muxX_2stage_Q_reg_56_ ( .D(n1200), .CK(n2852), .RN(n2718),
.Q(d_ff2_X[56]) );
DFFRX2TS VAR_CONT_temp_reg_1_ ( .D(n1878), .CK(n2858), .RN(n2781), .Q(
cont_var_out[1]) );
DFFRX2TS reg_val_muxY_2stage_Q_reg_56_ ( .D(n1328), .CK(n2849), .RN(n2728),
.Q(d_ff2_Y[56]) );
DFFRX1TS inst_CORDIC_FSM_v3_state_reg_reg_3_ ( .D(n2717), .CK(n2827), .RN(
n2780), .Q(inst_CORDIC_FSM_v3_state_reg[3]), .QN(n2716) );
DFFRX1TS reg_LUT_Q_reg_48_ ( .D(n1508), .CK(n2833), .RN(n2747), .Q(
d_ff3_LUT_out[48]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_55_ ( .D(n1446), .CK(n2832), .RN(n2739),
.Q(d_ff2_Z[55]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_54_ ( .D(n1447), .CK(n2840), .RN(n2739),
.Q(d_ff2_Z[54]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_51_ ( .D(n1450), .CK(n2829), .RN(n2739),
.Q(d_ff2_Z[51]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_50_ ( .D(n1451), .CK(n2053), .RN(n2739),
.Q(d_ff2_Z[50]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_49_ ( .D(n1452), .CK(n2832), .RN(n2739),
.Q(d_ff2_Z[49]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_48_ ( .D(n1453), .CK(n2839), .RN(n2740),
.Q(d_ff2_Z[48]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_47_ ( .D(n1454), .CK(n2838), .RN(n2740),
.Q(d_ff2_Z[47]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_46_ ( .D(n1455), .CK(n2830), .RN(n2740),
.Q(d_ff2_Z[46]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_45_ ( .D(n1456), .CK(n2840), .RN(n2740),
.Q(d_ff2_Z[45]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_44_ ( .D(n1457), .CK(n2837), .RN(n2740),
.Q(d_ff2_Z[44]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_43_ ( .D(n1458), .CK(n2837), .RN(n2740),
.Q(d_ff2_Z[43]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_42_ ( .D(n1459), .CK(n2837), .RN(n2740),
.Q(d_ff2_Z[42]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_41_ ( .D(n1460), .CK(n2837), .RN(n2740),
.Q(d_ff2_Z[41]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_40_ ( .D(n1461), .CK(n2837), .RN(n2740),
.Q(d_ff2_Z[40]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_39_ ( .D(n1462), .CK(n2837), .RN(n2740),
.Q(d_ff2_Z[39]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_38_ ( .D(n1463), .CK(n2837), .RN(n2741),
.Q(d_ff2_Z[38]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_37_ ( .D(n1464), .CK(n2837), .RN(n2741),
.Q(d_ff2_Z[37]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_36_ ( .D(n1465), .CK(n2837), .RN(n2741),
.Q(d_ff2_Z[36]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_34_ ( .D(n1467), .CK(n2047), .RN(n2741),
.Q(d_ff2_Z[34]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_33_ ( .D(n1468), .CK(n2833), .RN(n2741),
.Q(d_ff2_Z[33]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_32_ ( .D(n1469), .CK(n2810), .RN(n2741),
.Q(d_ff2_Z[32]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_31_ ( .D(n1470), .CK(n2835), .RN(n2741),
.Q(d_ff2_Z[31]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_30_ ( .D(n1471), .CK(n2836), .RN(n2741),
.Q(d_ff2_Z[30]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_29_ ( .D(n1472), .CK(n2841), .RN(n2741),
.Q(d_ff2_Z[29]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_28_ ( .D(n1473), .CK(n2831), .RN(n2742),
.Q(d_ff2_Z[28]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_27_ ( .D(n1474), .CK(n2047), .RN(n2742),
.Q(d_ff2_Z[27]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_26_ ( .D(n1475), .CK(n2833), .RN(n2742),
.Q(d_ff2_Z[26]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_25_ ( .D(n1476), .CK(n2859), .RN(n2742),
.Q(d_ff2_Z[25]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_24_ ( .D(n1477), .CK(n2835), .RN(n2742),
.Q(d_ff2_Z[24]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_23_ ( .D(n1478), .CK(n2836), .RN(n2742),
.Q(d_ff2_Z[23]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_22_ ( .D(n1479), .CK(n2841), .RN(n2742),
.Q(d_ff2_Z[22]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_21_ ( .D(n1480), .CK(n2831), .RN(n2742),
.Q(d_ff2_Z[21]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_20_ ( .D(n1481), .CK(n2047), .RN(n2742),
.Q(d_ff2_Z[20]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_19_ ( .D(n1482), .CK(n2833), .RN(n2742),
.Q(d_ff2_Z[19]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_18_ ( .D(n1483), .CK(n2047), .RN(n2743),
.Q(d_ff2_Z[18]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_17_ ( .D(n1484), .CK(n2047), .RN(n2743),
.Q(d_ff2_Z[17]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_16_ ( .D(n1485), .CK(n2047), .RN(n2743),
.Q(d_ff2_Z[16]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_15_ ( .D(n1486), .CK(n2824), .RN(n2743),
.Q(d_ff2_Z[15]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_14_ ( .D(n1487), .CK(n2835), .RN(n2743),
.Q(d_ff2_Z[14]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_13_ ( .D(n1488), .CK(n2836), .RN(n2743),
.Q(d_ff2_Z[13]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_12_ ( .D(n1489), .CK(n2841), .RN(n2743),
.Q(d_ff2_Z[12]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_11_ ( .D(n1490), .CK(n2831), .RN(n2743),
.Q(d_ff2_Z[11]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_9_ ( .D(n1492), .CK(n2833), .RN(n2743),
.Q(d_ff2_Z[9]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_8_ ( .D(n1493), .CK(n2835), .RN(n2737),
.Q(d_ff2_Z[8]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_6_ ( .D(n1495), .CK(n2796), .RN(n2746),
.Q(d_ff2_Z[6]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_5_ ( .D(n1496), .CK(n2836), .RN(n2744),
.Q(d_ff2_Z[5]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_4_ ( .D(n1497), .CK(n2834), .RN(n2745),
.Q(d_ff2_Z[4]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_3_ ( .D(n1498), .CK(n2834), .RN(n2737),
.Q(d_ff2_Z[3]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_2_ ( .D(n1499), .CK(n2834), .RN(n2746),
.Q(d_ff2_Z[2]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_1_ ( .D(n1500), .CK(n2834), .RN(n2744),
.Q(d_ff2_Z[1]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_0_ ( .D(n1501), .CK(n2834), .RN(n2745),
.Q(d_ff2_Z[0]) );
DFFRX1TS reg_LUT_Q_reg_10_ ( .D(n1539), .CK(n2827), .RN(n2750), .Q(
d_ff3_LUT_out[10]) );
DFFRX1TS reg_LUT_Q_reg_26_ ( .D(n1523), .CK(n2053), .RN(n2749), .Q(
d_ff3_LUT_out[26]) );
DFFRX4TS ITER_CONT_temp_reg_0_ ( .D(n1877), .CK(n2797), .RN(n2781), .Q(
cont_iter_out[0]), .QN(n2009) );
DFFRX1TS reg_LUT_Q_reg_13_ ( .D(n1536), .CK(n2853), .RN(n2750), .Q(
d_ff3_LUT_out[13]) );
DFFRX1TS reg_shift_x_Q_reg_13_ ( .D(n1281), .CK(n2820), .RN(n2725), .Q(
d_ff3_sh_x_out[13]) );
DFFRX1TS reg_shift_x_Q_reg_0_ ( .D(n1307), .CK(n2850), .RN(n2727), .Q(
d_ff3_sh_x_out[0]) );
DFFRX1TS reg_shift_x_Q_reg_59_ ( .D(n1186), .CK(n2834), .RN(n2792), .Q(
d_ff3_sh_x_out[59]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_35_ ( .D(n1466), .CK(n2837), .RN(n2741),
.Q(d_ff2_Z[35]) );
DFFRX4TS ITER_CONT_temp_reg_3_ ( .D(n1874), .CK(n2794), .RN(n2780), .Q(
cont_iter_out[3]), .QN(n2687) );
DFFRX2TS ITER_CONT_temp_reg_2_ ( .D(n1875), .CK(n2797), .RN(n2780), .Q(
cont_iter_out[2]), .QN(n2686) );
DFFRXLTS reg_operation_Q_reg_0_ ( .D(n1872), .CK(n2795), .RN(n2780), .Q(
d_ff1_operation_out), .QN(n2705) );
DFFSX1TS inst_CORDIC_FSM_v3_state_reg_reg_0_ ( .D(
inst_CORDIC_FSM_v3_state_next[0]), .CK(n2862), .SN(n2781), .Q(
inst_CORDIC_FSM_v3_state_reg[0]) );
DFFRXLTS reg_Z0_Q_reg_0_ ( .D(n1869), .CK(n2795), .RN(n2753), .Q(d_ff1_Z[0])
);
DFFRXLTS reg_Z0_Q_reg_1_ ( .D(n1868), .CK(n2795), .RN(n2719), .Q(d_ff1_Z[1])
);
DFFRXLTS reg_Z0_Q_reg_2_ ( .D(n1867), .CK(n2795), .RN(n2779), .Q(d_ff1_Z[2])
);
DFFRXLTS reg_Z0_Q_reg_3_ ( .D(n1866), .CK(n2795), .RN(n2782), .Q(d_ff1_Z[3])
);
DFFRXLTS reg_Z0_Q_reg_4_ ( .D(n1865), .CK(n2795), .RN(n2753), .Q(d_ff1_Z[4])
);
DFFRXLTS d_ff5_data_out_Q_reg_10_ ( .D(n1603), .CK(n2827), .RN(n2760), .Q(
data_output[10]) );
DFFRXLTS reg_LUT_Q_reg_0_ ( .D(n1549), .CK(n2828), .RN(n2751), .Q(
d_ff3_LUT_out[0]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_59_ ( .D(n1442), .CK(n2832), .RN(n2738),
.Q(d_ff2_Z[59]) );
NAND2X4TS U1310 ( .A(cont_var_out[1]), .B(cont_var_out[0]), .Y(n2616) );
CMPR32X2TS U1311 ( .A(n2687), .B(d_ff2_Y[55]), .C(n2440), .CO(n2656), .S(
n2441) );
NAND3XLTS U1312 ( .A(n2057), .B(n2697), .C(n2685), .Y(n2274) );
CLKINVX3TS U1313 ( .A(n2017), .Y(n2018) );
CLKINVX3TS U1314 ( .A(n2017), .Y(n2020) );
INVX2TS U1315 ( .A(n2674), .Y(n2151) );
AOI222X1TS U1316 ( .A0(n2362), .A1(d_ff2_Y[5]), .B0(n2317), .B1(d_ff2_X[5]),
.C0(d_ff2_Z[5]), .C1(n2366), .Y(n2294) );
AOI222X1TS U1317 ( .A0(n2362), .A1(d_ff2_Y[6]), .B0(n2636), .B1(d_ff2_X[6]),
.C0(d_ff2_Z[6]), .C1(n2316), .Y(n2295) );
AOI222X1TS U1318 ( .A0(n2362), .A1(d_ff2_Y[9]), .B0(n2361), .B1(d_ff2_X[9]),
.C0(d_ff2_Z[9]), .C1(n2366), .Y(n2298) );
AOI222X1TS U1319 ( .A0(n2362), .A1(d_ff2_Y[11]), .B0(n2636), .B1(d_ff2_X[11]), .C0(d_ff2_Z[11]), .C1(n2366), .Y(n2300) );
AOI222X1TS U1320 ( .A0(n2312), .A1(d_ff2_Y[12]), .B0(n2361), .B1(d_ff2_X[12]), .C0(d_ff2_Z[12]), .C1(n2366), .Y(n2301) );
AOI222X1TS U1321 ( .A0(n2362), .A1(d_ff2_Y[13]), .B0(n2317), .B1(d_ff2_X[13]), .C0(d_ff2_Z[13]), .C1(n2366), .Y(n2302) );
AOI222X1TS U1322 ( .A0(n2362), .A1(d_ff2_Y[15]), .B0(n2361), .B1(d_ff2_X[15]), .C0(d_ff2_Z[15]), .C1(n2316), .Y(n2304) );
AOI222X1TS U1323 ( .A0(n2312), .A1(d_ff2_Y[16]), .B0(n2317), .B1(d_ff2_X[16]), .C0(d_ff2_Z[16]), .C1(n2328), .Y(n2305) );
AOI222X1TS U1324 ( .A0(n2312), .A1(d_ff2_Y[17]), .B0(n2317), .B1(d_ff2_X[17]), .C0(d_ff2_Z[17]), .C1(n2316), .Y(n2306) );
AOI222X1TS U1325 ( .A0(n2312), .A1(d_ff2_Y[18]), .B0(n2636), .B1(d_ff2_X[18]), .C0(d_ff2_Z[18]), .C1(n2366), .Y(n2307) );
AOI222X1TS U1326 ( .A0(n2312), .A1(d_ff2_Y[19]), .B0(n2361), .B1(d_ff2_X[19]), .C0(d_ff2_Z[19]), .C1(n2328), .Y(n2308) );
AOI222X1TS U1327 ( .A0(n2312), .A1(d_ff2_Y[23]), .B0(n2317), .B1(d_ff2_X[23]), .C0(d_ff2_Z[23]), .C1(n2316), .Y(n2313) );
AOI222X1TS U1328 ( .A0(n2621), .A1(d_ff2_Y[24]), .B0(n2636), .B1(d_ff2_X[24]), .C0(d_ff2_Z[24]), .C1(n2328), .Y(n2314) );
AOI222X1TS U1329 ( .A0(n2324), .A1(d_ff2_Y[25]), .B0(n2361), .B1(d_ff2_X[25]), .C0(d_ff2_Z[25]), .C1(n2316), .Y(n2315) );
AOI222X1TS U1330 ( .A0(n2324), .A1(d_ff2_Y[26]), .B0(n2317), .B1(d_ff2_X[26]), .C0(d_ff2_Z[26]), .C1(n2316), .Y(n2318) );
AOI222X1TS U1331 ( .A0(n2324), .A1(d_ff2_Y[27]), .B0(n2344), .B1(d_ff2_X[27]), .C0(d_ff2_Z[27]), .C1(n2328), .Y(n2319) );
AOI222X1TS U1332 ( .A0(n2324), .A1(d_ff2_Y[28]), .B0(n2632), .B1(d_ff2_X[28]), .C0(d_ff2_Z[28]), .C1(n2328), .Y(n2320) );
AOI222X1TS U1333 ( .A0(n2324), .A1(d_ff2_Y[29]), .B0(n2344), .B1(d_ff2_X[29]), .C0(d_ff2_Z[29]), .C1(n2328), .Y(n2321) );
AOI222X1TS U1334 ( .A0(n2409), .A1(d_ff2_Y[30]), .B0(n2333), .B1(d_ff2_X[30]), .C0(d_ff2_Z[30]), .C1(n2328), .Y(n2322) );
AOI222X1TS U1335 ( .A0(n2324), .A1(d_ff2_Y[32]), .B0(n2632), .B1(d_ff2_X[32]), .C0(d_ff2_Z[32]), .C1(n2328), .Y(n2325) );
AOI222X1TS U1336 ( .A0(n2426), .A1(d_ff2_Y[33]), .B0(n2333), .B1(d_ff2_X[33]), .C0(d_ff2_Z[33]), .C1(n2328), .Y(n2329) );
AOI222X1TS U1337 ( .A0(n2634), .A1(d_ff2_Y[34]), .B0(n2344), .B1(d_ff2_X[34]), .C0(d_ff2_Z[34]), .C1(n2339), .Y(n2330) );
AOI222X1TS U1338 ( .A0(n2621), .A1(d_ff2_Y[37]), .B0(n2333), .B1(d_ff2_X[37]), .C0(d_ff2_Z[37]), .C1(n2339), .Y(n2334) );
AOI222X1TS U1339 ( .A0(n2409), .A1(d_ff2_Y[38]), .B0(n2632), .B1(d_ff2_X[38]), .C0(d_ff2_Z[38]), .C1(n2339), .Y(n2335) );
AOI222X1TS U1340 ( .A0(n2426), .A1(d_ff2_Y[39]), .B0(n2333), .B1(d_ff2_X[39]), .C0(d_ff2_Z[39]), .C1(n2339), .Y(n2336) );
AOI222X1TS U1341 ( .A0(n2634), .A1(d_ff2_Y[40]), .B0(n2344), .B1(d_ff2_X[40]), .C0(d_ff2_Z[40]), .C1(n2339), .Y(n2337) );
AOI222X1TS U1342 ( .A0(n2348), .A1(d_ff2_Y[44]), .B0(n2632), .B1(d_ff2_X[44]), .C0(d_ff2_Z[44]), .C1(n2354), .Y(n2342) );
AOI222X1TS U1343 ( .A0(n2348), .A1(d_ff2_Y[45]), .B0(n2333), .B1(d_ff2_X[45]), .C0(d_ff2_Z[45]), .C1(n2354), .Y(n2343) );
AOI222X1TS U1344 ( .A0(n2348), .A1(d_ff2_Y[46]), .B0(n2344), .B1(d_ff2_X[46]), .C0(d_ff2_Z[46]), .C1(n2354), .Y(n2345) );
AOI222X1TS U1345 ( .A0(n2348), .A1(d_ff2_Y[47]), .B0(n2421), .B1(d_ff2_X[47]), .C0(d_ff2_Z[47]), .C1(n2354), .Y(n2346) );
AOI222X1TS U1346 ( .A0(n2348), .A1(d_ff2_Y[48]), .B0(n2425), .B1(d_ff2_X[48]), .C0(d_ff2_Z[48]), .C1(n2354), .Y(n2347) );
AOI222X1TS U1347 ( .A0(n2348), .A1(d_ff2_Y[49]), .B0(n2421), .B1(d_ff2_X[49]), .C0(d_ff2_Z[49]), .C1(n2354), .Y(n2349) );
AOI222X1TS U1348 ( .A0(n2422), .A1(d_ff2_Y[50]), .B0(n2425), .B1(d_ff2_X[50]), .C0(d_ff2_Z[50]), .C1(n2354), .Y(n2350) );
AOI222X1TS U1349 ( .A0(n2634), .A1(d_ff2_Y[51]), .B0(n2421), .B1(d_ff2_X[51]), .C0(d_ff2_Z[51]), .C1(n2354), .Y(n2351) );
AOI222X1TS U1350 ( .A0(n2426), .A1(d_ff2_Y[54]), .B0(n2421), .B1(d_ff2_X[54]), .C0(d_ff2_Z[54]), .C1(n2354), .Y(n2355) );
AOI222X1TS U1351 ( .A0(n2422), .A1(d_ff2_Y[55]), .B0(n2425), .B1(d_ff2_X[55]), .C0(d_ff2_Z[55]), .C1(n2424), .Y(n2356) );
AO22XLTS U1352 ( .A0(n2562), .A1(d_ff_Yn[0]), .B0(d_ff2_Y[0]), .B1(n2158),
.Y(n1436) );
NAND2BXLTS U1353 ( .AN(n2499), .B(n2498), .Y(n1513) );
OAI2BB2XLTS U1354 ( .B0(ack_cordic), .B1(n2277), .A0N(enab_cont_iter), .A1N(
n2654), .Y(inst_CORDIC_FSM_v3_state_next[7]) );
CLKBUFX3TS U1355 ( .A(n2066), .Y(n2124) );
OR2X1TS U1356 ( .A(n2434), .B(n2683), .Y(n2010) );
CLKBUFX3TS U1357 ( .A(n2793), .Y(n2036) );
INVX2TS U1358 ( .A(n2017), .Y(n2019) );
CLKBUFX3TS U1359 ( .A(n2433), .Y(n2470) );
BUFX4TS U1360 ( .A(n2048), .Y(n2832) );
CLKBUFX2TS U1361 ( .A(clk), .Y(n2824) );
INVX2TS U1362 ( .A(n2686), .Y(n2011) );
INVX2TS U1363 ( .A(n2011), .Y(n2012) );
INVX2TS U1364 ( .A(cont_iter_out[0]), .Y(n2013) );
CLKINVX3TS U1365 ( .A(n2017), .Y(n2014) );
INVX2TS U1366 ( .A(n2017), .Y(n2015) );
INVX2TS U1367 ( .A(n2017), .Y(n2016) );
INVX2TS U1368 ( .A(n2124), .Y(n2017) );
CLKINVX3TS U1369 ( .A(rst), .Y(n2035) );
CLKINVX3TS U1370 ( .A(n2666), .Y(n2134) );
CLKINVX3TS U1371 ( .A(n2668), .Y(n2157) );
INVX2TS U1372 ( .A(n2665), .Y(n2523) );
CLKINVX3TS U1373 ( .A(n2365), .Y(n2494) );
CLKINVX3TS U1374 ( .A(n2365), .Y(n2361) );
CLKINVX3TS U1375 ( .A(n2365), .Y(n2317) );
CLKINVX3TS U1376 ( .A(n2365), .Y(n2636) );
CLKINVX3TS U1377 ( .A(n2668), .Y(n2254) );
CLKBUFX3TS U1378 ( .A(n2671), .Y(n2668) );
NAND2X1TS U1379 ( .A(n2644), .B(cont_iter_out[3]), .Y(n2268) );
CLKINVX3TS U1380 ( .A(n2538), .Y(n2644) );
CLKINVX3TS U1381 ( .A(n2717), .Y(n2113) );
INVX2TS U1382 ( .A(n2256), .Y(n2717) );
NOR2X2TS U1383 ( .A(n2638), .B(n2009), .Y(n2637) );
CLKINVX3TS U1384 ( .A(n2430), .Y(n2679) );
INVX2TS U1385 ( .A(n2430), .Y(n2144) );
INVX2TS U1386 ( .A(n2151), .Y(n2021) );
CLKINVX3TS U1387 ( .A(n2021), .Y(n2022) );
NOR2X2TS U1388 ( .A(d_ff2_X[59]), .B(n2581), .Y(n2580) );
NOR2X2TS U1389 ( .A(d_ff2_Y[59]), .B(n2535), .Y(n2574) );
CLKINVX3TS U1390 ( .A(n2669), .Y(n2279) );
INVX2TS U1391 ( .A(n2669), .Y(n2556) );
INVX2TS U1392 ( .A(n2669), .Y(n2146) );
INVX2TS U1393 ( .A(n2669), .Y(n2525) );
BUFX3TS U1394 ( .A(n2036), .Y(n2037) );
OAI21X2TS U1395 ( .A0(cont_iter_out[0]), .A1(cont_iter_out[2]), .B0(n2687),
.Y(n2497) );
AOI32X1TS U1396 ( .A0(n2648), .A1(n2662), .A2(n2683), .B0(n2703), .B1(n2430),
.Y(n1507) );
NOR2X2TS U1397 ( .A(n2141), .B(cont_iter_out[0]), .Y(n2648) );
CLKBUFX3TS U1398 ( .A(n2668), .Y(n2666) );
CLKBUFX3TS U1399 ( .A(n2668), .Y(n2665) );
CLKINVX3TS U1400 ( .A(n2605), .Y(n2620) );
CLKINVX3TS U1401 ( .A(n2605), .Y(n2623) );
CLKINVX3TS U1402 ( .A(n2605), .Y(n2401) );
BUFX3TS U1403 ( .A(n2782), .Y(n2784) );
INVX2TS U1404 ( .A(n2021), .Y(n2431) );
CLKINVX3TS U1405 ( .A(n2663), .Y(n2158) );
CLKBUFX3TS U1406 ( .A(n2460), .Y(n2449) );
AOI22X2TS U1407 ( .A0(cont_iter_out[0]), .A1(n2687), .B0(n2251), .B1(n2013),
.Y(n2452) );
CLKINVX3TS U1408 ( .A(n2399), .Y(n2405) );
CLKINVX3TS U1409 ( .A(n2399), .Y(n2425) );
CLKINVX3TS U1410 ( .A(n2399), .Y(n2421) );
BUFX3TS U1411 ( .A(n2788), .Y(n2790) );
BUFX3TS U1412 ( .A(n2753), .Y(n2789) );
BUFX3TS U1413 ( .A(n2737), .Y(n2791) );
BUFX3TS U1414 ( .A(n2746), .Y(n2786) );
CLKBUFX3TS U1415 ( .A(n2470), .Y(n2640) );
INVX2TS U1416 ( .A(n2010), .Y(n2023) );
BUFX3TS U1417 ( .A(n2793), .Y(n2781) );
NOR4BX2TS U1418 ( .AN(n2041), .B(inst_CORDIC_FSM_v3_state_reg[7]), .C(
inst_CORDIC_FSM_v3_state_reg[6]), .D(inst_CORDIC_FSM_v3_state_reg[3]),
.Y(n2267) );
NOR3X2TS U1419 ( .A(inst_CORDIC_FSM_v3_state_reg[4]), .B(
inst_CORDIC_FSM_v3_state_reg[5]), .C(inst_CORDIC_FSM_v3_state_reg[0]),
.Y(n2041) );
CLKBUFX3TS U1420 ( .A(n2674), .Y(n2664) );
CLKBUFX3TS U1421 ( .A(n2674), .Y(n2663) );
BUFX3TS U1422 ( .A(clk), .Y(n2048) );
AOI222X1TS U1423 ( .A0(n2599), .A1(d_ff3_sh_x_out[54]), .B0(n2361), .B1(
d_ff3_sh_y_out[54]), .C0(d_ff3_LUT_out[54]), .C1(n2626), .Y(n2368) );
AOI222X1TS U1424 ( .A0(n2599), .A1(d_ff3_sh_x_out[39]), .B0(n2636), .B1(
d_ff3_sh_y_out[39]), .C0(d_ff3_LUT_out[39]), .C1(n2626), .Y(n2376) );
AOI222X1TS U1425 ( .A0(n2397), .A1(d_ff3_sh_x_out[33]), .B0(n2317), .B1(
d_ff3_sh_y_out[33]), .C0(d_ff3_LUT_out[33]), .C1(n2626), .Y(n2382) );
AOI222X1TS U1426 ( .A0(n2397), .A1(d_ff3_sh_x_out[29]), .B0(n2421), .B1(
d_ff3_sh_y_out[29]), .C0(d_ff3_LUT_out[29]), .C1(n2626), .Y(n2386) );
AOI222X1TS U1427 ( .A0(n2397), .A1(d_ff3_sh_x_out[27]), .B0(n2361), .B1(
d_ff3_sh_y_out[27]), .C0(d_ff3_LUT_out[27]), .C1(n2626), .Y(n2388) );
CLKBUFX3TS U1428 ( .A(n2326), .Y(n2626) );
BUFX3TS U1429 ( .A(n2790), .Y(n2038) );
BUFX3TS U1430 ( .A(n2782), .Y(n2792) );
NAND2X2TS U1431 ( .A(n2687), .B(n2011), .Y(n2265) );
CLKBUFX3TS U1432 ( .A(n2630), .Y(n2621) );
CLKBUFX3TS U1433 ( .A(n2630), .Y(n2409) );
CLKBUFX3TS U1434 ( .A(n2630), .Y(n2634) );
CLKBUFX3TS U1435 ( .A(n2466), .Y(n2434) );
CLKBUFX3TS U1436 ( .A(n2466), .Y(n2460) );
BUFX6TS U1437 ( .A(n2836), .Y(n2837) );
BUFX6TS U1438 ( .A(n2027), .Y(n2815) );
BUFX6TS U1439 ( .A(n2821), .Y(n2819) );
BUFX6TS U1440 ( .A(n2841), .Y(n2847) );
BUFX6TS U1441 ( .A(n2835), .Y(n2834) );
BUFX6TS U1442 ( .A(n2822), .Y(n2818) );
BUFX6TS U1443 ( .A(n2852), .Y(n2850) );
BUFX6TS U1444 ( .A(n2050), .Y(n2813) );
BUFX4TS U1445 ( .A(n2814), .Y(n2825) );
BUFX4TS U1446 ( .A(n2814), .Y(n2051) );
BUFX6TS U1447 ( .A(n2049), .Y(n2860) );
BUFX4TS U1448 ( .A(n2857), .Y(n2858) );
BUFX4TS U1449 ( .A(n2857), .Y(n2862) );
BUFX6TS U1450 ( .A(n2831), .Y(n2842) );
BUFX6TS U1451 ( .A(n2047), .Y(n2844) );
BUFX6TS U1452 ( .A(n2823), .Y(n2817) );
BUFX4TS U1453 ( .A(n2825), .Y(n2024) );
BUFX4TS U1454 ( .A(n2825), .Y(n2826) );
BUFX6TS U1455 ( .A(n2825), .Y(n2820) );
BUFX6TS U1456 ( .A(n2825), .Y(n2853) );
BUFX6TS U1457 ( .A(n2825), .Y(n2828) );
BUFX6TS U1458 ( .A(n2825), .Y(n2827) );
BUFX6TS U1459 ( .A(n2855), .Y(n2849) );
BUFX4TS U1460 ( .A(n2048), .Y(n2855) );
BUFX4TS U1461 ( .A(n2859), .Y(n2843) );
BUFX6TS U1462 ( .A(n2048), .Y(n2830) );
BUFX6TS U1463 ( .A(n2854), .Y(n2848) );
BUFX4TS U1464 ( .A(n2055), .Y(n2854) );
BUFX6TS U1465 ( .A(n2851), .Y(n2856) );
BUFX4TS U1466 ( .A(n2048), .Y(n2851) );
BUFX3TS U1467 ( .A(n2052), .Y(n2800) );
CLKINVX6TS U1468 ( .A(n2029), .Y(n2025) );
BUFX6TS U1469 ( .A(n2052), .Y(n2799) );
BUFX6TS U1470 ( .A(n2052), .Y(n2801) );
BUFX6TS U1471 ( .A(n2052), .Y(n2804) );
BUFX6TS U1472 ( .A(n2052), .Y(n2803) );
CLKINVX6TS U1473 ( .A(n2029), .Y(n2026) );
CLKBUFX2TS U1474 ( .A(n2056), .Y(n2810) );
BUFX6TS U1475 ( .A(n2056), .Y(n2808) );
BUFX6TS U1476 ( .A(n2056), .Y(n2807) );
BUFX6TS U1477 ( .A(n2056), .Y(n2806) );
BUFX6TS U1478 ( .A(n2056), .Y(n2805) );
BUFX6TS U1479 ( .A(n2056), .Y(n2809) );
BUFX4TS U1480 ( .A(n2838), .Y(n2836) );
BUFX6TS U1481 ( .A(n2048), .Y(n2838) );
BUFX4TS U1482 ( .A(n2839), .Y(n2835) );
BUFX6TS U1483 ( .A(n2048), .Y(n2839) );
BUFX4TS U1484 ( .A(n2048), .Y(n2829) );
BUFX6TS U1485 ( .A(n2048), .Y(n2053) );
BUFX4TS U1486 ( .A(n2048), .Y(n2840) );
BUFX6TS U1487 ( .A(n2055), .Y(n2852) );
BUFX6TS U1488 ( .A(clk), .Y(n2857) );
BUFX6TS U1489 ( .A(n2048), .Y(n2861) );
BUFX6TS U1490 ( .A(n2802), .Y(n2049) );
BUFX4TS U1491 ( .A(n2055), .Y(n2027) );
BUFX4TS U1492 ( .A(n2055), .Y(n2812) );
BUFX3TS U1493 ( .A(clk), .Y(n2055) );
BUFX6TS U1494 ( .A(n2055), .Y(n2823) );
BUFX6TS U1495 ( .A(n2055), .Y(n2050) );
BUFX6TS U1496 ( .A(n2055), .Y(n2814) );
BUFX4TS U1497 ( .A(n2055), .Y(n2821) );
CLKINVX6TS U1498 ( .A(n2029), .Y(n2028) );
CLKBUFX2TS U1499 ( .A(n2054), .Y(n2796) );
BUFX6TS U1500 ( .A(n2830), .Y(n2833) );
BUFX6TS U1501 ( .A(n2840), .Y(n2831) );
BUFX4TS U1502 ( .A(n2053), .Y(n2841) );
BUFX6TS U1503 ( .A(n2829), .Y(n2047) );
INVX2TS U1504 ( .A(n2810), .Y(n2029) );
CLKINVX6TS U1505 ( .A(n2029), .Y(n2030) );
CLKINVX6TS U1506 ( .A(n2029), .Y(n2031) );
CLKBUFX2TS U1507 ( .A(clk), .Y(n2859) );
BUFX6TS U1508 ( .A(n2054), .Y(n2797) );
NOR3X4TS U1509 ( .A(n2683), .B(n2013), .C(n2643), .Y(n2654) );
NOR2X4TS U1510 ( .A(n2013), .B(n2588), .Y(n2288) );
OAI21X2TS U1511 ( .A0(n2013), .A1(n2141), .B0(n2023), .Y(n2155) );
BUFX6TS U1512 ( .A(n2054), .Y(n2794) );
BUFX6TS U1513 ( .A(n2054), .Y(n2846) );
BUFX6TS U1514 ( .A(n2054), .Y(n2845) );
BUFX6TS U1515 ( .A(n2054), .Y(n2798) );
XOR2XLTS U1516 ( .A(d_ff_Yn[63]), .B(n2164), .Y(n2165) );
OAI33X4TS U1517 ( .A0(d_ff1_shift_region_flag_out[1]), .A1(
d_ff1_operation_out), .A2(n2684), .B0(n2681), .B1(n2705), .B2(
d_ff1_shift_region_flag_out[0]), .Y(n2164) );
AOI222X1TS U1518 ( .A0(n2397), .A1(d_ff3_sh_x_out[26]), .B0(n2425), .B1(
d_ff3_sh_y_out[26]), .C0(d_ff3_LUT_out[26]), .C1(n2626), .Y(n2389) );
AOI222X1TS U1519 ( .A0(n2409), .A1(d_ff3_sh_x_out[10]), .B0(n2421), .B1(
d_ff3_sh_y_out[10]), .C0(d_ff3_LUT_out[10]), .C1(n2411), .Y(n2410) );
AOI222X1TS U1520 ( .A0(n2431), .A1(d_ff2_Z[0]), .B0(n2254), .B1(d_ff_Zn[0]),
.C0(n2019), .C1(d_ff1_Z[0]), .Y(n2100) );
AOI222X1TS U1521 ( .A0(n2362), .A1(d_ff2_Y[0]), .B0(n2494), .B1(d_ff2_X[0]),
.C0(d_ff2_Z[0]), .C1(n2339), .Y(n2327) );
AOI222X4TS U1522 ( .A0(n2504), .A1(d_ff2_Z[1]), .B0(n2016), .B1(d_ff1_Z[1]),
.C0(d_ff_Zn[1]), .C1(n2279), .Y(n2103) );
AOI222X1TS U1523 ( .A0(n2312), .A1(d_ff2_Y[1]), .B0(n2494), .B1(d_ff2_X[1]),
.C0(d_ff2_Z[1]), .C1(n2608), .Y(n2293) );
AOI222X1TS U1524 ( .A0(n2543), .A1(d_ff2_Z[2]), .B0(n2014), .B1(d_ff1_Z[2]),
.C0(d_ff_Zn[2]), .C1(n2157), .Y(n2107) );
AOI222X1TS U1525 ( .A0(n2312), .A1(d_ff2_Y[2]), .B0(n2494), .B1(d_ff2_X[2]),
.C0(d_ff2_Z[2]), .C1(n2366), .Y(n2291) );
AOI222X4TS U1526 ( .A0(n2504), .A1(d_ff2_Z[3]), .B0(n2018), .B1(d_ff1_Z[3]),
.C0(d_ff_Zn[3]), .C1(n2254), .Y(n2110) );
AOI222X1TS U1527 ( .A0(n2362), .A1(d_ff2_Y[3]), .B0(n2494), .B1(d_ff2_X[3]),
.C0(d_ff2_Z[3]), .C1(n2608), .Y(n2292) );
AOI222X1TS U1528 ( .A0(n2362), .A1(d_ff2_Y[4]), .B0(n2361), .B1(d_ff2_X[4]),
.C0(d_ff2_Z[4]), .C1(n2366), .Y(n2296) );
AOI222X4TS U1529 ( .A0(n2547), .A1(d_ff2_Z[5]), .B0(n2020), .B1(d_ff1_Z[5]),
.C0(d_ff_Zn[5]), .C1(n2254), .Y(n2115) );
AOI222X1TS U1530 ( .A0(n2158), .A1(d_ff2_Z[6]), .B0(n2015), .B1(d_ff1_Z[6]),
.C0(d_ff_Zn[6]), .C1(n2254), .Y(n2117) );
AOI222X4TS U1531 ( .A0(n2504), .A1(d_ff2_Z[8]), .B0(n2014), .B1(d_ff1_Z[8]),
.C0(d_ff_Zn[8]), .C1(n2157), .Y(n2120) );
AOI222X4TS U1532 ( .A0(n2547), .A1(d_ff2_Z[9]), .B0(n2020), .B1(d_ff1_Z[9]),
.C0(d_ff_Zn[9]), .C1(n2157), .Y(n2122) );
AOI222X1TS U1533 ( .A0(n2158), .A1(d_ff2_Z[11]), .B0(n2018), .B1(d_ff1_Z[11]), .C0(d_ff_Zn[11]), .C1(n2157), .Y(n2126) );
AOI222X1TS U1534 ( .A0(n2139), .A1(d_ff2_Z[12]), .B0(n2124), .B1(d_ff1_Z[12]), .C0(d_ff_Zn[12]), .C1(n2134), .Y(n2128) );
AOI222X1TS U1535 ( .A0(n2543), .A1(d_ff2_Z[13]), .B0(n2015), .B1(d_ff1_Z[13]), .C0(d_ff_Zn[13]), .C1(n2134), .Y(n2129) );
AOI222X4TS U1536 ( .A0(n2504), .A1(d_ff2_Z[14]), .B0(n2019), .B1(d_ff1_Z[14]), .C0(d_ff_Zn[14]), .C1(n2134), .Y(n2131) );
AOI222X4TS U1537 ( .A0(n2547), .A1(d_ff2_Z[15]), .B0(n2014), .B1(d_ff1_Z[15]), .C0(d_ff_Zn[15]), .C1(n2134), .Y(n2133) );
AOI222X1TS U1538 ( .A0(n2158), .A1(d_ff2_Z[16]), .B0(n2015), .B1(d_ff1_Z[16]), .C0(d_ff_Zn[16]), .C1(n2134), .Y(n2135) );
AOI222X1TS U1539 ( .A0(n2139), .A1(d_ff2_Z[17]), .B0(n2014), .B1(d_ff1_Z[17]), .C0(d_ff_Zn[17]), .C1(n2553), .Y(n2140) );
AOI222X4TS U1540 ( .A0(n2547), .A1(d_ff2_Z[18]), .B0(n2020), .B1(d_ff1_Z[18]), .C0(d_ff_Zn[18]), .C1(n2523), .Y(n2143) );
AOI222X1TS U1541 ( .A0(n2158), .A1(d_ff2_Z[19]), .B0(n2015), .B1(d_ff1_Z[19]), .C0(d_ff_Zn[19]), .C1(n2523), .Y(n2145) );
AOI222X1TS U1542 ( .A0(n2543), .A1(d_ff2_Z[20]), .B0(n2020), .B1(d_ff1_Z[20]), .C0(d_ff_Zn[20]), .C1(n2523), .Y(n2148) );
AOI222X1TS U1543 ( .A0(n2324), .A1(d_ff2_Y[20]), .B0(n2317), .B1(d_ff2_X[20]), .C0(d_ff2_Z[20]), .C1(n2316), .Y(n2309) );
AOI222X1TS U1544 ( .A0(n2139), .A1(d_ff2_Z[21]), .B0(n2018), .B1(d_ff1_Z[21]), .C0(d_ff_Zn[21]), .C1(n2523), .Y(n2150) );
AOI222X1TS U1545 ( .A0(n2324), .A1(d_ff2_Y[21]), .B0(n2636), .B1(d_ff2_X[21]), .C0(d_ff2_Z[21]), .C1(n2316), .Y(n2310) );
AOI222X1TS U1546 ( .A0(n2504), .A1(d_ff2_Z[22]), .B0(n2015), .B1(d_ff1_Z[22]), .C0(d_ff_Zn[22]), .C1(n2157), .Y(n2153) );
AOI222X1TS U1547 ( .A0(n2324), .A1(d_ff2_Y[22]), .B0(n2361), .B1(d_ff2_X[22]), .C0(d_ff2_Z[22]), .C1(n2316), .Y(n2311) );
AOI222X1TS U1548 ( .A0(n2547), .A1(d_ff2_Z[23]), .B0(n2018), .B1(d_ff1_Z[23]), .C0(d_ff_Zn[23]), .C1(n2157), .Y(n2156) );
AOI222X1TS U1549 ( .A0(n2158), .A1(d_ff2_Z[24]), .B0(n2124), .B1(d_ff1_Z[24]), .C0(d_ff_Zn[24]), .C1(n2157), .Y(n2159) );
AOI222X1TS U1550 ( .A0(n2022), .A1(d_ff2_Z[25]), .B0(n2015), .B1(d_ff1_Z[25]), .C0(d_ff_Zn[25]), .C1(n2157), .Y(n2152) );
AOI222X1TS U1551 ( .A0(n2139), .A1(d_ff2_Z[27]), .B0(n2124), .B1(d_ff1_Z[27]), .C0(d_ff_Zn[27]), .C1(n2519), .Y(n2147) );
AOI222X1TS U1552 ( .A0(n2022), .A1(d_ff2_Z[28]), .B0(n2014), .B1(d_ff1_Z[28]), .C0(d_ff_Zn[28]), .C1(n2525), .Y(n2142) );
AOI222X1TS U1553 ( .A0(n2022), .A1(d_ff2_Z[29]), .B0(n2015), .B1(d_ff1_Z[29]), .C0(d_ff_Zn[29]), .C1(n2146), .Y(n2136) );
AOI222X1TS U1554 ( .A0(n2022), .A1(d_ff2_Z[30]), .B0(n2014), .B1(d_ff1_Z[30]), .C0(d_ff_Zn[30]), .C1(n2556), .Y(n2132) );
AOI222X1TS U1555 ( .A0(n2348), .A1(d_ff2_Y[31]), .B0(n2344), .B1(d_ff2_X[31]), .C0(d_ff2_Z[31]), .C1(n2328), .Y(n2323) );
AOI222X1TS U1556 ( .A0(n2022), .A1(d_ff2_Z[36]), .B0(n2020), .B1(d_ff1_Z[36]), .C0(d_ff_Zn[36]), .C1(n2134), .Y(n2116) );
AOI222X1TS U1557 ( .A0(n2600), .A1(d_ff2_Y[36]), .B0(n2632), .B1(d_ff2_X[36]), .C0(d_ff2_Z[36]), .C1(n2339), .Y(n2332) );
AOI222X1TS U1558 ( .A0(n2113), .A1(d_ff2_Z[37]), .B0(n2015), .B1(d_ff1_Z[37]), .C0(d_ff_Zn[37]), .C1(n2134), .Y(n2114) );
AOI222X1TS U1559 ( .A0(n2113), .A1(d_ff2_Z[38]), .B0(n2018), .B1(d_ff1_Z[38]), .C0(d_ff_Zn[38]), .C1(n2134), .Y(n2111) );
AOI222X1TS U1560 ( .A0(n2113), .A1(d_ff2_Z[40]), .B0(n2018), .B1(d_ff1_Z[40]), .C0(d_ff_Zn[40]), .C1(n2134), .Y(n2099) );
AOI222X1TS U1561 ( .A0(n2113), .A1(d_ff2_Z[41]), .B0(n2015), .B1(d_ff1_Z[41]), .C0(d_ff_Zn[41]), .C1(n2553), .Y(n2095) );
AOI222X1TS U1562 ( .A0(n2348), .A1(d_ff2_Y[41]), .B0(n2632), .B1(d_ff2_X[41]), .C0(d_ff2_Z[41]), .C1(n2339), .Y(n2338) );
AOI222X1TS U1563 ( .A0(n2113), .A1(d_ff2_Z[42]), .B0(n2020), .B1(d_ff1_Z[42]), .C0(d_ff_Zn[42]), .C1(n2519), .Y(n2090) );
AOI222X1TS U1564 ( .A0(n2348), .A1(d_ff2_Y[42]), .B0(n2333), .B1(d_ff2_X[42]), .C0(d_ff2_Z[42]), .C1(n2339), .Y(n2340) );
AOI222X1TS U1565 ( .A0(n2348), .A1(d_ff2_Y[43]), .B0(n2344), .B1(d_ff2_X[43]), .C0(d_ff2_Z[43]), .C1(n2354), .Y(n2341) );
AOI222X1TS U1566 ( .A0(n2113), .A1(d_ff2_Z[44]), .B0(n2124), .B1(d_ff1_Z[44]), .C0(d_ff_Zn[44]), .C1(n2525), .Y(n2085) );
AOI222X1TS U1567 ( .A0(n2113), .A1(d_ff2_Z[45]), .B0(n2016), .B1(d_ff1_Z[45]), .C0(d_ff_Zn[45]), .C1(n2146), .Y(n2078) );
AOI222X1TS U1568 ( .A0(n2113), .A1(d_ff2_Z[46]), .B0(n2124), .B1(d_ff1_Z[46]), .C0(d_ff_Zn[46]), .C1(n2279), .Y(n2071) );
AOI222X1TS U1569 ( .A0(n2256), .A1(d_ff2_Z[47]), .B0(n2014), .B1(d_ff1_Z[47]), .C0(d_ff_Zn[47]), .C1(n2279), .Y(n2083) );
AOI222X1TS U1570 ( .A0(n2256), .A1(d_ff2_Z[48]), .B0(n2016), .B1(d_ff1_Z[48]), .C0(d_ff_Zn[48]), .C1(n2279), .Y(n2067) );
AOI222X1TS U1571 ( .A0(n2547), .A1(d_ff2_Z[49]), .B0(n2014), .B1(d_ff1_Z[49]), .C0(d_ff_Zn[49]), .C1(n2279), .Y(n2069) );
AOI222X1TS U1572 ( .A0(n2256), .A1(d_ff2_Z[50]), .B0(n2020), .B1(d_ff1_Z[50]), .C0(d_ff_Zn[50]), .C1(n2279), .Y(n2068) );
AOI222X1TS U1573 ( .A0(n2158), .A1(d_ff2_Z[51]), .B0(n2016), .B1(d_ff1_Z[51]), .C0(d_ff_Zn[51]), .C1(n2254), .Y(n2075) );
AOI222X1TS U1574 ( .A0(n2256), .A1(d_ff2_Z[54]), .B0(n2020), .B1(d_ff1_Z[54]), .C0(d_ff_Zn[54]), .C1(n2254), .Y(n2080) );
AOI222X1TS U1575 ( .A0(n2139), .A1(d_ff2_Z[55]), .B0(n2018), .B1(d_ff1_Z[55]), .C0(d_ff_Zn[55]), .C1(n2254), .Y(n2073) );
NOR2X2TS U1576 ( .A(n2285), .B(n2589), .Y(n2499) );
AOI221X4TS U1577 ( .A0(n2251), .A1(n2679), .B0(d_ff3_LUT_out[7]), .B1(n2538),
.C0(n2238), .Y(n2094) );
NOR2X2TS U1578 ( .A(n2287), .B(n2250), .Y(n2238) );
CLKBUFX3TS U1579 ( .A(n2508), .Y(n2507) );
CLKBUFX3TS U1580 ( .A(n2513), .Y(n2512) );
CLKBUFX3TS U1581 ( .A(n2455), .Y(n2459) );
CLKBUFX3TS U1582 ( .A(n2454), .Y(n2455) );
AOI222X1TS U1583 ( .A0(n2229), .A1(data_output[60]), .B0(n2228), .B1(
d_ff_Yn[60]), .C0(n2216), .C1(d_ff_Xn[60]), .Y(n2230) );
AOI222X1TS U1584 ( .A0(n2229), .A1(data_output[59]), .B0(n2228), .B1(
d_ff_Yn[59]), .C0(n2227), .C1(d_ff_Xn[59]), .Y(n2226) );
AOI222X1TS U1585 ( .A0(n2229), .A1(data_output[58]), .B0(n2228), .B1(
d_ff_Yn[58]), .C0(n2175), .C1(d_ff_Xn[58]), .Y(n2225) );
AOI222X1TS U1586 ( .A0(n2229), .A1(data_output[57]), .B0(n2228), .B1(
d_ff_Yn[57]), .C0(n2091), .C1(d_ff_Xn[57]), .Y(n2224) );
AOI222X1TS U1587 ( .A0(n2229), .A1(data_output[56]), .B0(n2228), .B1(
d_ff_Yn[56]), .C0(n2108), .C1(d_ff_Xn[56]), .Y(n2223) );
AOI222X1TS U1588 ( .A0(n2221), .A1(data_output[55]), .B0(n2228), .B1(
d_ff_Yn[55]), .C0(n2200), .C1(d_ff_Xn[55]), .Y(n2222) );
AOI222X1TS U1589 ( .A0(n2229), .A1(data_output[54]), .B0(n2228), .B1(
d_ff_Yn[54]), .C0(n2189), .C1(d_ff_Xn[54]), .Y(n2220) );
AOI222X1TS U1590 ( .A0(n2221), .A1(data_output[53]), .B0(n2218), .B1(
d_ff_Yn[53]), .C0(n2216), .C1(d_ff_Xn[53]), .Y(n2219) );
AOI222X1TS U1591 ( .A0(n2229), .A1(data_output[62]), .B0(n2228), .B1(
d_ff_Yn[62]), .C0(n2227), .C1(d_ff_Xn[62]), .Y(n2163) );
AOI222X1TS U1592 ( .A0(n2229), .A1(data_output[61]), .B0(n2228), .B1(
d_ff_Yn[61]), .C0(n2175), .C1(d_ff_Xn[61]), .Y(n2162) );
AOI222X4TS U1593 ( .A0(n2362), .A1(d_ff2_Y[7]), .B0(n2636), .B1(d_ff2_X[7]),
.C0(d_ff2_Z[7]), .C1(n2366), .Y(n2363) );
AOI222X1TS U1594 ( .A0(n2324), .A1(d_ff2_Y[14]), .B0(n2636), .B1(d_ff2_X[14]), .C0(d_ff2_Z[14]), .C1(n2316), .Y(n2303) );
AOI222X4TS U1595 ( .A0(n2312), .A1(d_ff2_Y[10]), .B0(n2317), .B1(d_ff2_X[10]), .C0(d_ff2_Z[10]), .C1(n2608), .Y(n2299) );
AOI222X1TS U1596 ( .A0(n2312), .A1(d_ff2_Y[8]), .B0(n2636), .B1(d_ff2_X[8]),
.C0(d_ff2_Z[8]), .C1(n2608), .Y(n2297) );
AOI222X4TS U1597 ( .A0(n2504), .A1(d_ff2_Z[59]), .B0(n2020), .B1(d_ff1_Z[59]), .C0(d_ff_Zn[59]), .C1(n2260), .Y(n2261) );
AOI222X4TS U1598 ( .A0(n2431), .A1(d_ff2_Z[58]), .B0(n2014), .B1(d_ff1_Z[58]), .C0(d_ff_Zn[58]), .C1(n2260), .Y(n2259) );
AOI222X4TS U1599 ( .A0(n2431), .A1(d_ff2_Z[57]), .B0(n2016), .B1(d_ff1_Z[57]), .C0(d_ff_Zn[57]), .C1(n2260), .Y(n2258) );
AOI222X4TS U1600 ( .A0(n2256), .A1(d_ff2_Z[56]), .B0(n2014), .B1(d_ff1_Z[56]), .C0(d_ff_Zn[56]), .C1(n2260), .Y(n2257) );
AOI222X4TS U1601 ( .A0(n2543), .A1(d_ff2_Z[26]), .B0(n2018), .B1(d_ff1_Z[26]), .C0(d_ff_Zn[26]), .C1(n2260), .Y(n2149) );
AOI222X4TS U1602 ( .A0(n2022), .A1(d_ff2_Z[31]), .B0(n2016), .B1(d_ff1_Z[31]), .C0(d_ff_Zn[31]), .C1(n2260), .Y(n2130) );
AOI222X4TS U1603 ( .A0(n2022), .A1(d_ff2_Z[32]), .B0(n2124), .B1(d_ff1_Z[32]), .C0(d_ff_Zn[32]), .C1(n2260), .Y(n2127) );
AOI222X4TS U1604 ( .A0(n2022), .A1(d_ff2_Z[33]), .B0(n2124), .B1(d_ff1_Z[33]), .C0(d_ff_Zn[33]), .C1(n2260), .Y(n2125) );
AOI222X4TS U1605 ( .A0(n2022), .A1(d_ff2_Z[34]), .B0(n2016), .B1(d_ff1_Z[34]), .C0(d_ff_Zn[34]), .C1(n2260), .Y(n2121) );
NOR3X2TS U1606 ( .A(d_ff2_X[57]), .B(d_ff2_X[56]), .C(n2676), .Y(n2583) );
NOR3X2TS U1607 ( .A(d_ff2_Y[57]), .B(d_ff2_Y[56]), .C(n2656), .Y(n2532) );
AOI222X4TS U1608 ( .A0(n2543), .A1(d_ff2_Z[10]), .B0(n2124), .B1(d_ff1_Z[10]), .C0(d_ff_Zn[10]), .C1(n2157), .Y(n2123) );
AOI222X4TS U1609 ( .A0(n2022), .A1(d_ff2_Z[35]), .B0(n2020), .B1(d_ff1_Z[35]), .C0(d_ff_Zn[35]), .C1(n2260), .Y(n2119) );
AOI222X4TS U1610 ( .A0(n2139), .A1(d_ff2_Z[7]), .B0(n2016), .B1(d_ff1_Z[7]),
.C0(d_ff_Zn[7]), .C1(n2157), .Y(n2118) );
AOI222X1TS U1611 ( .A0(n2543), .A1(d_ff2_Z[4]), .B0(n2018), .B1(d_ff1_Z[4]),
.C0(d_ff_Zn[4]), .C1(n2254), .Y(n2112) );
AOI222X1TS U1612 ( .A0(n2113), .A1(d_ff2_Z[39]), .B0(n2018), .B1(d_ff1_Z[39]), .C0(d_ff_Zn[39]), .C1(n2134), .Y(n2106) );
AOI222X1TS U1613 ( .A0(n2113), .A1(d_ff2_Z[43]), .B0(n2016), .B1(d_ff1_Z[43]), .C0(d_ff_Zn[43]), .C1(n2556), .Y(n2088) );
NOR3XLTS U1614 ( .A(cont_iter_out[1]), .B(n2431), .C(n2241), .Y(n2066) );
AOI222X1TS U1615 ( .A0(n2086), .A1(data_output[12]), .B0(n2101), .B1(
d_ff_Yn[12]), .C0(n2227), .C1(d_ff_Xn[12]), .Y(n2064) );
AOI222X1TS U1616 ( .A0(n2086), .A1(data_output[7]), .B0(n2101), .B1(
d_ff_Yn[7]), .C0(n2175), .C1(d_ff_Xn[7]), .Y(n2072) );
AOI222X1TS U1617 ( .A0(n2086), .A1(data_output[9]), .B0(n2101), .B1(
d_ff_Yn[9]), .C0(n2091), .C1(d_ff_Xn[9]), .Y(n2076) );
AOI222X1TS U1618 ( .A0(n2086), .A1(data_output[10]), .B0(n2101), .B1(
d_ff_Yn[10]), .C0(n2108), .C1(d_ff_Xn[10]), .Y(n2079) );
AOI222X1TS U1619 ( .A0(n2086), .A1(data_output[5]), .B0(n2101), .B1(
d_ff_Yn[5]), .C0(n2200), .C1(d_ff_Xn[5]), .Y(n2087) );
AOI222X1TS U1620 ( .A0(n2061), .A1(data_output[4]), .B0(n2101), .B1(
d_ff_Yn[4]), .C0(n2189), .C1(d_ff_Xn[4]), .Y(n2089) );
CLKBUFX3TS U1621 ( .A(n2179), .Y(n2101) );
AOI222X1TS U1622 ( .A0(n2426), .A1(d_ff3_sh_x_out[15]), .B0(n2421), .B1(
d_ff3_sh_y_out[15]), .C0(d_ff3_LUT_out[15]), .C1(n2411), .Y(n2403) );
AOI222X1TS U1623 ( .A0(n2426), .A1(d_ff3_sh_x_out[11]), .B0(n2425), .B1(
d_ff3_sh_y_out[11]), .C0(d_ff3_LUT_out[11]), .C1(n2411), .Y(n2408) );
AOI222X1TS U1624 ( .A0(n2426), .A1(d_ff3_sh_x_out[8]), .B0(n2421), .B1(
d_ff3_sh_y_out[8]), .C0(d_ff3_LUT_out[8]), .C1(n2424), .Y(n2413) );
AOI222X1TS U1625 ( .A0(n2426), .A1(d_ff3_sh_x_out[5]), .B0(n2425), .B1(
d_ff3_sh_y_out[5]), .C0(d_ff3_LUT_out[5]), .C1(n2424), .Y(n2416) );
AOI222X1TS U1626 ( .A0(n2426), .A1(d_ff3_sh_x_out[3]), .B0(n2425), .B1(
d_ff3_sh_y_out[3]), .C0(d_ff3_LUT_out[3]), .C1(n2424), .Y(n2419) );
CLKBUFX3TS U1627 ( .A(n2600), .Y(n2426) );
CLKBUFX3TS U1628 ( .A(n2433), .Y(n2480) );
CLKBUFX3TS U1629 ( .A(n2444), .Y(n2529) );
BUFX3TS U1630 ( .A(n2788), .Y(n2782) );
CLKBUFX3TS U1631 ( .A(n2035), .Y(n2793) );
CLKBUFX3TS U1632 ( .A(n2674), .Y(n2670) );
BUFX4TS U1633 ( .A(clk), .Y(n2795) );
NOR3X4TS U1634 ( .A(inst_CORDIC_FSM_v3_state_reg[7]), .B(n2685), .C(n2042),
.Y(enab_cont_iter) );
CLKBUFX2TS U1635 ( .A(n2616), .Y(n2032) );
CLKBUFX3TS U1636 ( .A(n2616), .Y(n2033) );
NOR3X4TS U1637 ( .A(n2430), .B(n2683), .C(n2013), .Y(n2489) );
CLKBUFX3TS U1638 ( .A(n2657), .Y(n2430) );
OAI21XLTS U1639 ( .A0(n2686), .A1(n2271), .B0(n2252), .Y(n1504) );
OAI211XLTS U1640 ( .A0(n2251), .A1(n2247), .B0(n2246), .C0(n2245), .Y(n1522)
);
OAI21XLTS U1641 ( .A0(n2704), .A1(n2465), .B0(n2286), .Y(n1321) );
OAI211XLTS U1642 ( .A0(n2646), .A1(n2451), .B0(n2097), .C0(n2096), .Y(n1539)
);
OAI21XLTS U1643 ( .A0(n2706), .A1(n2033), .B0(n2407), .Y(add_subt_dataB[12])
);
OAI21XLTS U1644 ( .A0(n2032), .A1(n2691), .B0(n2387), .Y(add_subt_dataB[28])
);
OAI21XLTS U1645 ( .A0(n2032), .A1(n2713), .B0(n2374), .Y(add_subt_dataB[41])
);
OAI211XLTS U1646 ( .A0(n2702), .A1(n2365), .B0(n2610), .C0(n2364), .Y(
add_subt_dataB[61]) );
OAI21XLTS U1647 ( .A0(n2627), .A1(n2690), .B0(n2352), .Y(add_subt_dataA[52])
);
NAND3BX2TS U1648 ( .AN(inst_CORDIC_FSM_v3_state_reg[1]), .B(
inst_CORDIC_FSM_v3_state_reg[2]), .C(n2267), .Y(n2256) );
CLKBUFX2TS U1649 ( .A(n2035), .Y(n2788) );
CLKBUFX2TS U1650 ( .A(n2788), .Y(n2785) );
BUFX3TS U1651 ( .A(n2784), .Y(n2765) );
BUFX3TS U1652 ( .A(n2784), .Y(n2766) );
BUFX3TS U1653 ( .A(n2719), .Y(n2778) );
BUFX3TS U1654 ( .A(n2784), .Y(n2767) );
BUFX3TS U1655 ( .A(n2779), .Y(n2777) );
CLKBUFX2TS U1656 ( .A(n2788), .Y(n2787) );
CLKBUFX2TS U1657 ( .A(n2790), .Y(n2783) );
BUFX3TS U1658 ( .A(n2038), .Y(n2772) );
BUFX3TS U1659 ( .A(n2759), .Y(n2771) );
BUFX3TS U1660 ( .A(n2784), .Y(n2770) );
BUFX3TS U1661 ( .A(n2787), .Y(n2769) );
BUFX3TS U1662 ( .A(n2779), .Y(n2764) );
BUFX3TS U1663 ( .A(n2793), .Y(n2768) );
BUFX3TS U1664 ( .A(n2781), .Y(n2776) );
BUFX3TS U1665 ( .A(n2036), .Y(n2743) );
BUFX3TS U1666 ( .A(n2036), .Y(n2742) );
BUFX3TS U1667 ( .A(n2036), .Y(n2741) );
BUFX3TS U1668 ( .A(n2791), .Y(n2740) );
BUFX3TS U1669 ( .A(n2793), .Y(n2775) );
BUFX3TS U1670 ( .A(n2791), .Y(n2739) );
BUFX3TS U1671 ( .A(n2753), .Y(n2744) );
BUFX3TS U1672 ( .A(n2788), .Y(n2779) );
BUFX3TS U1673 ( .A(n2719), .Y(n2745) );
BUFX3TS U1674 ( .A(n2793), .Y(n2755) );
BUFX3TS U1675 ( .A(n2793), .Y(n2756) );
BUFX3TS U1676 ( .A(n2036), .Y(n2757) );
BUFX3TS U1677 ( .A(n2035), .Y(n2730) );
BUFX3TS U1678 ( .A(n2036), .Y(n2729) );
BUFX3TS U1679 ( .A(n2788), .Y(n2753) );
BUFX3TS U1680 ( .A(n2782), .Y(n2758) );
BUFX3TS U1681 ( .A(n2789), .Y(n2752) );
BUFX3TS U1682 ( .A(n2790), .Y(n2759) );
BUFX3TS U1683 ( .A(n2037), .Y(n2722) );
BUFX3TS U1684 ( .A(n2745), .Y(n2734) );
BUFX3TS U1685 ( .A(n2784), .Y(n2732) );
BUFX3TS U1686 ( .A(n2037), .Y(n2721) );
BUFX3TS U1687 ( .A(n2789), .Y(n2750) );
BUFX3TS U1688 ( .A(n2793), .Y(n2749) );
BUFX3TS U1689 ( .A(n2037), .Y(n2720) );
BUFX3TS U1690 ( .A(n2036), .Y(n2735) );
BUFX3TS U1691 ( .A(n2790), .Y(n2731) );
BUFX3TS U1692 ( .A(n2793), .Y(n2754) );
BUFX3TS U1693 ( .A(n2745), .Y(n2724) );
BUFX3TS U1694 ( .A(n2744), .Y(n2723) );
BUFX3TS U1695 ( .A(n2746), .Y(n2726) );
BUFX3TS U1696 ( .A(n2787), .Y(n2763) );
BUFX3TS U1697 ( .A(n2793), .Y(n2747) );
BUFX3TS U1698 ( .A(n2737), .Y(n2725) );
BUFX3TS U1699 ( .A(n2788), .Y(n2719) );
BUFX3TS U1700 ( .A(n2737), .Y(n2774) );
BUFX3TS U1701 ( .A(n2037), .Y(n2718) );
BUFX3TS U1702 ( .A(n2789), .Y(n2728) );
BUFX3TS U1703 ( .A(n2744), .Y(n2733) );
BUFX3TS U1704 ( .A(n2038), .Y(n2773) );
BUFX3TS U1705 ( .A(n2793), .Y(n2736) );
BUFX3TS U1706 ( .A(n2037), .Y(n2748) );
BUFX3TS U1707 ( .A(n2759), .Y(n2780) );
BUFX3TS U1708 ( .A(n2789), .Y(n2751) );
BUFX3TS U1709 ( .A(n2779), .Y(n2737) );
BUFX3TS U1710 ( .A(n2791), .Y(n2738) );
BUFX3TS U1711 ( .A(n2787), .Y(n2746) );
BUFX3TS U1712 ( .A(n2786), .Y(n2727) );
NAND3XLTS U1713 ( .A(n2041), .B(n2697), .C(n2685), .Y(n2039) );
OR4X2TS U1714 ( .A(inst_CORDIC_FSM_v3_state_reg[1]), .B(
inst_CORDIC_FSM_v3_state_reg[2]), .C(n2716), .D(n2039), .Y(n2444) );
CLKBUFX2TS U1715 ( .A(n2444), .Y(n2466) );
CLKBUFX3TS U1716 ( .A(n2466), .Y(n2538) );
INVX2TS U1717 ( .A(n2265), .Y(n2491) );
CLKBUFX3TS U1718 ( .A(n2444), .Y(n2647) );
OAI2BB2XLTS U1719 ( .B0(n2430), .B1(n2491), .A0N(n2647), .A1N(
d_ff3_LUT_out[37]), .Y(n1514) );
CLKBUFX2TS U1720 ( .A(n2717), .Y(n2674) );
NOR2X1TS U1721 ( .A(n2011), .B(cont_iter_out[3]), .Y(n2272) );
INVX2TS U1722 ( .A(n2272), .Y(n2141) );
INVX2TS U1723 ( .A(n2648), .Y(n2241) );
OAI21XLTS U1724 ( .A0(n2241), .A1(cont_iter_out[1]), .B0(n2021), .Y(n2040)
);
CLKBUFX2TS U1725 ( .A(n2040), .Y(n2671) );
CLKBUFX2TS U1726 ( .A(n2668), .Y(n2669) );
OA22X1TS U1727 ( .A0(n2663), .A1(d_ff2_X[58]), .B0(d_ff_Xn[58]), .B1(n2673),
.Y(n1198) );
OA22X1TS U1728 ( .A0(n2670), .A1(d_ff2_X[60]), .B0(d_ff_Xn[60]), .B1(n2665),
.Y(n1196) );
NOR3X1TS U1729 ( .A(inst_CORDIC_FSM_v3_state_reg[1]), .B(
inst_CORDIC_FSM_v3_state_reg[2]), .C(inst_CORDIC_FSM_v3_state_reg[3]),
.Y(n2057) );
NAND2X1TS U1730 ( .A(n2057), .B(n2041), .Y(n2042) );
NOR3X2TS U1731 ( .A(inst_CORDIC_FSM_v3_state_reg[6]), .B(n2697), .C(n2042),
.Y(ready_cordic) );
INVX2TS U1732 ( .A(ready_cordic), .Y(n2277) );
NAND2X2TS U1733 ( .A(cont_iter_out[2]), .B(cont_iter_out[3]), .Y(n2643) );
NAND2X1TS U1734 ( .A(n2644), .B(cont_iter_out[0]), .Y(n2652) );
NOR2X4TS U1735 ( .A(n2434), .B(cont_iter_out[1]), .Y(n2642) );
NAND2X2TS U1736 ( .A(n2009), .B(n2642), .Y(n2250) );
INVX2TS U1737 ( .A(n2250), .Y(n2485) );
NOR2X2TS U1738 ( .A(n2687), .B(cont_iter_out[2]), .Y(n2251) );
INVX2TS U1739 ( .A(n2251), .Y(n2488) );
AOI22X1TS U1740 ( .A0(n2485), .A1(n2488), .B0(d_ff3_LUT_out[3]), .B1(n2538),
.Y(n2043) );
NAND2X1TS U1741 ( .A(n2009), .B(n2023), .Y(n2247) );
INVX2TS U1742 ( .A(n2247), .Y(n2232) );
NAND2X1TS U1743 ( .A(n2232), .B(n2643), .Y(n2093) );
OAI211XLTS U1744 ( .A0(n2011), .A1(n2652), .B0(n2043), .C0(n2093), .Y(n1546)
);
CLKBUFX3TS U1745 ( .A(n2670), .Y(n2046) );
OA22X1TS U1746 ( .A0(d_ff_Xn[46]), .A1(n2673), .B0(n2046), .B1(d_ff2_X[46]),
.Y(n1216) );
OA22X1TS U1747 ( .A0(d_ff_Xn[48]), .A1(n2673), .B0(n2046), .B1(d_ff2_X[48]),
.Y(n1212) );
OA22X1TS U1748 ( .A0(d_ff_Xn[49]), .A1(n2666), .B0(n2046), .B1(d_ff2_X[49]),
.Y(n1210) );
INVX2TS U1749 ( .A(n2023), .Y(n2589) );
CLKBUFX3TS U1750 ( .A(n2466), .Y(n2657) );
AOI22X1TS U1751 ( .A0(n2679), .A1(n2491), .B0(d_ff3_LUT_out[19]), .B1(n2657),
.Y(n2044) );
NAND2X2TS U1752 ( .A(n2643), .B(n2141), .Y(n2287) );
INVX2TS U1753 ( .A(n2238), .Y(n2289) );
OAI211XLTS U1754 ( .A0(cont_iter_out[3]), .A1(n2589), .B0(n2044), .C0(n2289),
.Y(n1530) );
INVX2TS U1755 ( .A(n2657), .Y(n2662) );
OAI21X1TS U1756 ( .A0(n2683), .A1(n2009), .B0(n2662), .Y(n2137) );
INVX2TS U1757 ( .A(n2137), .Y(n2490) );
CLKBUFX3TS U1758 ( .A(n2538), .Y(n2677) );
AOI22X1TS U1759 ( .A0(n2490), .A1(n2687), .B0(d_ff3_LUT_out[55]), .B1(n2677),
.Y(n2045) );
NAND2X1TS U1760 ( .A(n2489), .B(n2287), .Y(n2245) );
NAND2X1TS U1761 ( .A(n2045), .B(n2245), .Y(n1503) );
CLKBUFX3TS U1762 ( .A(n2668), .Y(n2673) );
OA22X1TS U1763 ( .A0(n2021), .A1(d_ff2_X[61]), .B0(d_ff_Xn[61]), .B1(n2673),
.Y(n1195) );
OA22X1TS U1764 ( .A0(n2664), .A1(d_ff2_X[59]), .B0(d_ff_Xn[59]), .B1(n2666),
.Y(n1197) );
OA22X1TS U1765 ( .A0(d_ff_Xn[53]), .A1(n2666), .B0(n2046), .B1(d_ff2_X[53]),
.Y(n1203) );
CLKBUFX2TS U1766 ( .A(n2671), .Y(n2667) );
OA22X1TS U1767 ( .A0(d_ff_Xn[55]), .A1(n2667), .B0(n2046), .B1(d_ff2_X[55]),
.Y(n1201) );
OA22X1TS U1768 ( .A0(d_ff_Xn[54]), .A1(n2665), .B0(n2046), .B1(d_ff2_X[54]),
.Y(n1202) );
OA22X1TS U1769 ( .A0(d_ff_Xn[31]), .A1(n2668), .B0(n2670), .B1(d_ff2_X[31]),
.Y(n1246) );
OA22X1TS U1770 ( .A0(d_ff_Xn[0]), .A1(n2666), .B0(n2046), .B1(d_ff2_X[0]),
.Y(n1308) );
OA22X1TS U1771 ( .A0(d_ff_Xn[19]), .A1(n2671), .B0(n2664), .B1(d_ff2_X[19]),
.Y(n1270) );
OA22X1TS U1772 ( .A0(d_ff_Xn[43]), .A1(n2668), .B0(n2021), .B1(d_ff2_X[43]),
.Y(n1222) );
OA22X1TS U1773 ( .A0(d_ff_Xn[41]), .A1(n2673), .B0(n2046), .B1(d_ff2_X[41]),
.Y(n1226) );
OA22X1TS U1774 ( .A0(d_ff_Xn[45]), .A1(n2665), .B0(n2046), .B1(d_ff2_X[45]),
.Y(n1218) );
OA22X1TS U1775 ( .A0(d_ff_Xn[42]), .A1(n2665), .B0(n2046), .B1(d_ff2_X[42]),
.Y(n1224) );
CLKBUFX2TS U1776 ( .A(clk), .Y(n2054) );
CLKBUFX2TS U1777 ( .A(clk), .Y(n2052) );
BUFX3TS U1778 ( .A(n2825), .Y(n2816) );
CLKBUFX2TS U1779 ( .A(clk), .Y(n2056) );
BUFX3TS U1780 ( .A(n2052), .Y(n2802) );
BUFX3TS U1781 ( .A(n2055), .Y(n2822) );
BUFX3TS U1782 ( .A(n2055), .Y(n2811) );
NOR2X1TS U1783 ( .A(inst_CORDIC_FSM_v3_state_reg[0]), .B(n2274), .Y(n2058)
);
NAND3BX1TS U1784 ( .AN(inst_CORDIC_FSM_v3_state_reg[5]), .B(n2058), .C(
inst_CORDIC_FSM_v3_state_reg[4]), .Y(n2617) );
NAND3BX1TS U1785 ( .AN(inst_CORDIC_FSM_v3_state_reg[4]), .B(
inst_CORDIC_FSM_v3_state_reg[5]), .C(n2058), .Y(n2618) );
NAND2X1TS U1786 ( .A(n2617), .B(n2618), .Y(beg_add_subt) );
BUFX3TS U1787 ( .A(n2786), .Y(n2762) );
BUFX3TS U1788 ( .A(n2786), .Y(n2760) );
BUFX3TS U1789 ( .A(n2786), .Y(n2761) );
NAND2X1TS U1790 ( .A(n2642), .B(n2265), .Y(n2059) );
OAI211XLTS U1791 ( .A0(n2144), .A1(n2712), .B0(n2268), .C0(n2059), .Y(n1527)
);
AOI21X1TS U1792 ( .A0(enab_cont_iter), .A1(n2654), .B0(ready_cordic), .Y(
n2062) );
CLKBUFX2TS U1793 ( .A(n2062), .Y(n2205) );
CLKBUFX2TS U1794 ( .A(n2205), .Y(n2061) );
CLKBUFX3TS U1795 ( .A(n2061), .Y(n2086) );
XOR2XLTS U1796 ( .A(n2681), .B(d_ff1_operation_out), .Y(n2060) );
XOR2X1TS U1797 ( .A(n2684), .B(n2060), .Y(n2063) );
NOR2BX1TS U1798 ( .AN(n2063), .B(n2061), .Y(n2160) );
CLKBUFX2TS U1799 ( .A(n2160), .Y(n2206) );
CLKBUFX3TS U1800 ( .A(n2206), .Y(n2179) );
CLKBUFX3TS U1801 ( .A(n2062), .Y(n2229) );
OR2X2TS U1802 ( .A(n2229), .B(n2063), .Y(n2167) );
INVX2TS U1803 ( .A(n2167), .Y(n2091) );
INVX2TS U1804 ( .A(n2064), .Y(n1601) );
AOI222X1TS U1805 ( .A0(n2086), .A1(data_output[8]), .B0(n2179), .B1(
d_ff_Yn[8]), .C0(n2216), .C1(d_ff_Xn[8]), .Y(n2065) );
INVX2TS U1806 ( .A(n2065), .Y(n1605) );
INVX2TS U1807 ( .A(n2067), .Y(n1453) );
INVX2TS U1808 ( .A(n2068), .Y(n1451) );
INVX2TS U1809 ( .A(n2664), .Y(n2504) );
INVX2TS U1810 ( .A(n2069), .Y(n1452) );
INVX2TS U1811 ( .A(n2167), .Y(n2175) );
AOI222X1TS U1812 ( .A0(n2086), .A1(data_output[13]), .B0(n2179), .B1(
d_ff_Yn[13]), .C0(n2091), .C1(d_ff_Xn[13]), .Y(n2070) );
INVX2TS U1813 ( .A(n2070), .Y(n1600) );
INVX2TS U1814 ( .A(n2071), .Y(n1455) );
NAND2X1TS U1815 ( .A(n2644), .B(n2141), .Y(n2138) );
INVX2TS U1816 ( .A(n2642), .Y(n2588) );
OAI211XLTS U1817 ( .A0(n2679), .A1(n2714), .B0(n2138), .C0(n2588), .Y(n1509)
);
INVX2TS U1818 ( .A(n2072), .Y(n1606) );
INVX2TS U1819 ( .A(n2073), .Y(n1446) );
CLKBUFX3TS U1820 ( .A(n2179), .Y(n2177) );
AOI222X1TS U1821 ( .A0(n2086), .A1(data_output[14]), .B0(n2177), .B1(
d_ff_Yn[14]), .C0(n2175), .C1(d_ff_Xn[14]), .Y(n2074) );
INVX2TS U1822 ( .A(n2074), .Y(n1599) );
NAND2X1TS U1823 ( .A(n2023), .B(n2141), .Y(n2105) );
OAI211XLTS U1824 ( .A0(n2144), .A1(n2711), .B0(n2268), .C0(n2105), .Y(n1529)
);
INVX2TS U1825 ( .A(n2075), .Y(n1450) );
INVX2TS U1826 ( .A(n2489), .Y(n2271) );
OAI211XLTS U1827 ( .A0(n2679), .A1(n2715), .B0(n2271), .C0(n2250), .Y(n1505)
);
INVX2TS U1828 ( .A(n2076), .Y(n1604) );
NAND2X1TS U1829 ( .A(n2642), .B(n2452), .Y(n2077) );
NOR2X2TS U1830 ( .A(cont_iter_out[0]), .B(cont_iter_out[3]), .Y(n2285) );
NAND2X1TS U1831 ( .A(n2499), .B(n2265), .Y(n2248) );
OAI211XLTS U1832 ( .A0(n2144), .A1(n2710), .B0(n2077), .C0(n2248), .Y(n1515)
);
INVX2TS U1833 ( .A(n2078), .Y(n1456) );
INVX2TS U1834 ( .A(n2079), .Y(n1603) );
INVX2TS U1835 ( .A(n2080), .Y(n1447) );
AOI222X1TS U1836 ( .A0(n2086), .A1(data_output[6]), .B0(n2179), .B1(
d_ff_Yn[6]), .C0(n2189), .C1(d_ff_Xn[6]), .Y(n2081) );
INVX2TS U1837 ( .A(n2081), .Y(n1607) );
AOI222X1TS U1838 ( .A0(n2086), .A1(data_output[11]), .B0(n2179), .B1(
d_ff_Yn[11]), .C0(n2200), .C1(d_ff_Xn[11]), .Y(n2082) );
INVX2TS U1839 ( .A(n2082), .Y(n1602) );
INVX2TS U1840 ( .A(n2083), .Y(n1454) );
CLKBUFX3TS U1841 ( .A(n2205), .Y(n2180) );
AOI222X1TS U1842 ( .A0(n2180), .A1(data_output[15]), .B0(n2177), .B1(
d_ff_Yn[15]), .C0(n2227), .C1(d_ff_Xn[15]), .Y(n2084) );
INVX2TS U1843 ( .A(n2084), .Y(n1598) );
INVX2TS U1844 ( .A(n2085), .Y(n1457) );
OAI211XLTS U1845 ( .A0(n2679), .A1(n2713), .B0(n2268), .C0(n2155), .Y(n1512)
);
INVX2TS U1846 ( .A(n2087), .Y(n1608) );
AOI22X1TS U1847 ( .A0(n2011), .A1(n2642), .B0(n2232), .B1(n2287), .Y(n2496)
);
NAND2X1TS U1848 ( .A(n2489), .B(n2265), .Y(n2097) );
OAI211XLTS U1849 ( .A0(n2144), .A1(n2709), .B0(n2496), .C0(n2097), .Y(n1519)
);
INVX2TS U1850 ( .A(n2088), .Y(n1458) );
INVX2TS U1851 ( .A(n2089), .Y(n1609) );
NAND2X1TS U1852 ( .A(n2642), .B(n2241), .Y(n2104) );
OAI211XLTS U1853 ( .A0(n2144), .A1(n2708), .B0(n2155), .C0(n2104), .Y(n1525)
);
INVX2TS U1854 ( .A(n2090), .Y(n1459) );
AOI222X1TS U1855 ( .A0(n2061), .A1(data_output[3]), .B0(n2101), .B1(
d_ff_Yn[3]), .C0(n2108), .C1(d_ff_Xn[3]), .Y(n2092) );
INVX2TS U1856 ( .A(n2092), .Y(n1610) );
OAI211XLTS U1857 ( .A0(n2287), .A1(n2271), .B0(n2094), .C0(n2093), .Y(n1542)
);
INVX2TS U1858 ( .A(n2095), .Y(n1460) );
NOR2X1TS U1859 ( .A(cont_iter_out[3]), .B(n2683), .Y(n2646) );
OAI21X1TS U1860 ( .A0(cont_iter_out[2]), .A1(n2285), .B0(n2644), .Y(n2451)
);
CLKBUFX3TS U1861 ( .A(n2657), .Y(n2649) );
NAND2X1TS U1862 ( .A(d_ff3_LUT_out[10]), .B(n2649), .Y(n2096) );
OR2X1TS U1863 ( .A(n2285), .B(n2588), .Y(n2154) );
OAI211XLTS U1864 ( .A0(n2144), .A1(n2707), .B0(n2105), .C0(n2154), .Y(n1533)
);
INVX2TS U1865 ( .A(n2167), .Y(n2108) );
AOI222X1TS U1866 ( .A0(n2061), .A1(data_output[2]), .B0(n2179), .B1(
d_ff_Yn[2]), .C0(n2091), .C1(d_ff_Xn[2]), .Y(n2098) );
INVX2TS U1867 ( .A(n2098), .Y(n1611) );
INVX2TS U1868 ( .A(n2099), .Y(n1461) );
INVX2TS U1869 ( .A(n2100), .Y(n1501) );
AOI222X1TS U1870 ( .A0(n2061), .A1(data_output[1]), .B0(n2101), .B1(
d_ff_Yn[1]), .C0(n2175), .C1(d_ff_Xn[1]), .Y(n2102) );
INVX2TS U1871 ( .A(n2102), .Y(n1612) );
INVX2TS U1872 ( .A(n2103), .Y(n1500) );
OAI211XLTS U1873 ( .A0(n2144), .A1(n2706), .B0(n2105), .C0(n2104), .Y(n1537)
);
INVX2TS U1874 ( .A(n2106), .Y(n1462) );
INVX2TS U1875 ( .A(n2021), .Y(n2547) );
INVX2TS U1876 ( .A(n2107), .Y(n1499) );
AOI222X1TS U1877 ( .A0(n2205), .A1(data_output[0]), .B0(d_ff_Yn[0]), .B1(
n2179), .C0(d_ff_Xn[0]), .C1(n2216), .Y(n2109) );
INVX2TS U1878 ( .A(n2109), .Y(n1613) );
INVX2TS U1879 ( .A(n2110), .Y(n1498) );
INVX2TS U1880 ( .A(n2111), .Y(n1463) );
INVX2TS U1881 ( .A(n2112), .Y(n1497) );
INVX2TS U1882 ( .A(n2114), .Y(n1464) );
INVX2TS U1883 ( .A(n2115), .Y(n1496) );
INVX2TS U1884 ( .A(n2116), .Y(n1465) );
INVX2TS U1885 ( .A(n2117), .Y(n1495) );
INVX2TS U1886 ( .A(n2118), .Y(n1494) );
INVX2TS U1887 ( .A(n2665), .Y(n2260) );
INVX2TS U1888 ( .A(n2119), .Y(n1466) );
INVX2TS U1889 ( .A(n2663), .Y(n2139) );
INVX2TS U1890 ( .A(n2120), .Y(n1493) );
INVX2TS U1891 ( .A(n2121), .Y(n1467) );
INVX2TS U1892 ( .A(n2122), .Y(n1492) );
INVX2TS U1893 ( .A(n2123), .Y(n1491) );
INVX2TS U1894 ( .A(n2125), .Y(n1468) );
INVX2TS U1895 ( .A(n2126), .Y(n1490) );
NAND2X1TS U1896 ( .A(n2689), .B(cont_var_out[1]), .Y(n2606) );
INVX2TS U1897 ( .A(n2606), .Y(n2600) );
CLKBUFX3TS U1898 ( .A(n2600), .Y(n2630) );
NAND2X1TS U1899 ( .A(n2634), .B(ready_add_subt), .Y(n2448) );
CLKBUFX2TS U1900 ( .A(n2448), .Y(n2454) );
NOR2XLTS U1901 ( .A(n2618), .B(n2459), .Y(inst_CORDIC_FSM_v3_state_next[6])
);
INVX2TS U1902 ( .A(n2127), .Y(n1469) );
INVX2TS U1903 ( .A(n2128), .Y(n1489) );
INVX2TS U1904 ( .A(n2129), .Y(n1488) );
INVX2TS U1905 ( .A(n2130), .Y(n1470) );
INVX2TS U1906 ( .A(n2131), .Y(n1487) );
INVX2TS U1907 ( .A(n2132), .Y(n1471) );
INVX2TS U1908 ( .A(n2133), .Y(n1486) );
INVX2TS U1909 ( .A(n2135), .Y(n1485) );
INVX2TS U1910 ( .A(n2136), .Y(n1472) );
OAI211XLTS U1911 ( .A0(n2144), .A1(n2699), .B0(n2138), .C0(n2137), .Y(n1518)
);
INVX2TS U1912 ( .A(n2140), .Y(n1484) );
OAI21X1TS U1913 ( .A0(cont_iter_out[1]), .A1(n2141), .B0(n2644), .Y(n2650)
);
NAND2X1TS U1914 ( .A(n2644), .B(n2009), .Y(n2465) );
OAI211XLTS U1915 ( .A0(n2144), .A1(n2691), .B0(n2650), .C0(n2465), .Y(n1521)
);
INVX2TS U1916 ( .A(n2142), .Y(n1473) );
INVX2TS U1917 ( .A(n2143), .Y(n1483) );
NAND2X1TS U1918 ( .A(n2644), .B(n2497), .Y(n2645) );
OAI211XLTS U1919 ( .A0(n2144), .A1(n2698), .B0(n2645), .C0(n2155), .Y(n1545)
);
INVX2TS U1920 ( .A(n2145), .Y(n1482) );
INVX2TS U1921 ( .A(n2147), .Y(n1474) );
INVX2TS U1922 ( .A(n2148), .Y(n1481) );
INVX2TS U1923 ( .A(n2149), .Y(n1475) );
INVX2TS U1924 ( .A(n2150), .Y(n1480) );
INVX2TS U1925 ( .A(n2152), .Y(n1476) );
INVX2TS U1926 ( .A(n2153), .Y(n1479) );
OAI211XLTS U1927 ( .A0(n2679), .A1(n2696), .B0(n2155), .C0(n2154), .Y(n1516)
);
INVX2TS U1928 ( .A(n2156), .Y(n1478) );
INVX2TS U1929 ( .A(n2159), .Y(n1477) );
CLKBUFX2TS U1930 ( .A(n2160), .Y(n2161) );
CLKBUFX3TS U1931 ( .A(n2161), .Y(n2228) );
INVX2TS U1932 ( .A(n2167), .Y(n2227) );
INVX2TS U1933 ( .A(n2162), .Y(n1552) );
INVX2TS U1934 ( .A(n2163), .Y(n1551) );
XNOR2X1TS U1935 ( .A(n2164), .B(d_ff_Xn[63]), .Y(n2168) );
AOI22X1TS U1936 ( .A0(n2229), .A1(data_output[63]), .B0(n2228), .B1(n2165),
.Y(n2166) );
OAI21XLTS U1937 ( .A0(n2168), .A1(n2167), .B0(n2166), .Y(n1550) );
AOI222X1TS U1938 ( .A0(n2180), .A1(data_output[16]), .B0(n2177), .B1(
d_ff_Yn[16]), .C0(n2216), .C1(d_ff_Xn[16]), .Y(n2169) );
INVX2TS U1939 ( .A(n2169), .Y(n1597) );
AOI222X1TS U1940 ( .A0(n2180), .A1(data_output[17]), .B0(n2177), .B1(
d_ff_Yn[17]), .C0(n2189), .C1(d_ff_Xn[17]), .Y(n2170) );
INVX2TS U1941 ( .A(n2170), .Y(n1596) );
AOI222X1TS U1942 ( .A0(n2180), .A1(data_output[18]), .B0(n2177), .B1(
d_ff_Yn[18]), .C0(n2200), .C1(d_ff_Xn[18]), .Y(n2171) );
INVX2TS U1943 ( .A(n2171), .Y(n1595) );
AOI222X1TS U1944 ( .A0(n2180), .A1(data_output[19]), .B0(n2177), .B1(
d_ff_Yn[19]), .C0(n2108), .C1(d_ff_Xn[19]), .Y(n2172) );
INVX2TS U1945 ( .A(n2172), .Y(n1594) );
AOI222X1TS U1946 ( .A0(n2180), .A1(data_output[20]), .B0(n2177), .B1(
d_ff_Yn[20]), .C0(n2091), .C1(d_ff_Xn[20]), .Y(n2173) );
INVX2TS U1947 ( .A(n2173), .Y(n1593) );
AOI222X1TS U1948 ( .A0(n2180), .A1(data_output[21]), .B0(n2177), .B1(
d_ff_Yn[21]), .C0(n2175), .C1(d_ff_Xn[21]), .Y(n2174) );
INVX2TS U1949 ( .A(n2174), .Y(n1592) );
AOI222X1TS U1950 ( .A0(n2180), .A1(data_output[22]), .B0(n2177), .B1(
d_ff_Yn[22]), .C0(n2227), .C1(d_ff_Xn[22]), .Y(n2176) );
INVX2TS U1951 ( .A(n2176), .Y(n1591) );
INVX2TS U1952 ( .A(n2167), .Y(n2189) );
AOI222X1TS U1953 ( .A0(n2180), .A1(data_output[23]), .B0(n2177), .B1(
d_ff_Yn[23]), .C0(n2200), .C1(d_ff_Xn[23]), .Y(n2178) );
INVX2TS U1954 ( .A(n2178), .Y(n1590) );
AOI222X1TS U1955 ( .A0(n2180), .A1(data_output[24]), .B0(n2161), .B1(
d_ff_Yn[24]), .C0(n2108), .C1(d_ff_Xn[24]), .Y(n2181) );
INVX2TS U1956 ( .A(n2181), .Y(n1589) );
CLKBUFX3TS U1957 ( .A(n2205), .Y(n2210) );
AOI222X1TS U1958 ( .A0(n2210), .A1(data_output[25]), .B0(n2161), .B1(
d_ff_Yn[25]), .C0(n2091), .C1(d_ff_Xn[25]), .Y(n2182) );
INVX2TS U1959 ( .A(n2182), .Y(n1588) );
AOI222X1TS U1960 ( .A0(n2210), .A1(data_output[26]), .B0(n2206), .B1(
d_ff_Yn[26]), .C0(n2175), .C1(d_ff_Xn[26]), .Y(n2183) );
INVX2TS U1961 ( .A(n2183), .Y(n1587) );
AOI222X1TS U1962 ( .A0(n2210), .A1(data_output[27]), .B0(n2161), .B1(
d_ff_Yn[27]), .C0(n2227), .C1(d_ff_Xn[27]), .Y(n2184) );
INVX2TS U1963 ( .A(n2184), .Y(n1586) );
AOI222X1TS U1964 ( .A0(n2210), .A1(data_output[28]), .B0(n2206), .B1(
d_ff_Yn[28]), .C0(n2216), .C1(d_ff_Xn[28]), .Y(n2185) );
INVX2TS U1965 ( .A(n2185), .Y(n1585) );
AOI222X1TS U1966 ( .A0(n2210), .A1(data_output[29]), .B0(n2161), .B1(
d_ff_Yn[29]), .C0(n2189), .C1(d_ff_Xn[29]), .Y(n2186) );
INVX2TS U1967 ( .A(n2186), .Y(n1584) );
AOI222X1TS U1968 ( .A0(n2210), .A1(data_output[30]), .B0(n2206), .B1(
d_ff_Yn[30]), .C0(n2200), .C1(d_ff_Xn[30]), .Y(n2187) );
INVX2TS U1969 ( .A(n2187), .Y(n1583) );
AOI222X1TS U1970 ( .A0(n2210), .A1(data_output[31]), .B0(n2161), .B1(
d_ff_Yn[31]), .C0(n2108), .C1(d_ff_Xn[31]), .Y(n2188) );
INVX2TS U1971 ( .A(n2188), .Y(n1582) );
AOI222X1TS U1972 ( .A0(n2210), .A1(data_output[32]), .B0(n2179), .B1(
d_ff_Yn[32]), .C0(n2091), .C1(d_ff_Xn[32]), .Y(n2190) );
INVX2TS U1973 ( .A(n2190), .Y(n1581) );
INVX2TS U1974 ( .A(n2167), .Y(n2200) );
AOI222X1TS U1975 ( .A0(n2210), .A1(data_output[33]), .B0(n2179), .B1(
d_ff_Yn[33]), .C0(n2227), .C1(d_ff_Xn[33]), .Y(n2191) );
INVX2TS U1976 ( .A(n2191), .Y(n1580) );
CLKBUFX3TS U1977 ( .A(n2205), .Y(n2203) );
CLKBUFX3TS U1978 ( .A(n2206), .Y(n2202) );
AOI222X1TS U1979 ( .A0(n2203), .A1(data_output[34]), .B0(n2202), .B1(
d_ff_Yn[34]), .C0(n2216), .C1(d_ff_Xn[34]), .Y(n2192) );
INVX2TS U1980 ( .A(n2192), .Y(n1579) );
AOI222X1TS U1981 ( .A0(n2203), .A1(data_output[35]), .B0(n2202), .B1(
d_ff_Yn[35]), .C0(n2189), .C1(d_ff_Xn[35]), .Y(n2193) );
INVX2TS U1982 ( .A(n2193), .Y(n1578) );
AOI222X1TS U1983 ( .A0(n2203), .A1(data_output[36]), .B0(n2202), .B1(
d_ff_Yn[36]), .C0(n2200), .C1(d_ff_Xn[36]), .Y(n2194) );
INVX2TS U1984 ( .A(n2194), .Y(n1577) );
AOI222X1TS U1985 ( .A0(n2203), .A1(data_output[37]), .B0(n2202), .B1(
d_ff_Yn[37]), .C0(n2108), .C1(d_ff_Xn[37]), .Y(n2195) );
INVX2TS U1986 ( .A(n2195), .Y(n1576) );
AOI222X1TS U1987 ( .A0(n2203), .A1(data_output[38]), .B0(n2202), .B1(
d_ff_Yn[38]), .C0(n2091), .C1(d_ff_Xn[38]), .Y(n2196) );
INVX2TS U1988 ( .A(n2196), .Y(n1575) );
AOI222X1TS U1989 ( .A0(n2203), .A1(data_output[39]), .B0(n2202), .B1(
d_ff_Yn[39]), .C0(n2175), .C1(d_ff_Xn[39]), .Y(n2197) );
INVX2TS U1990 ( .A(n2197), .Y(n1574) );
AOI222X1TS U1991 ( .A0(n2203), .A1(data_output[40]), .B0(n2202), .B1(
d_ff_Yn[40]), .C0(n2227), .C1(d_ff_Xn[40]), .Y(n2198) );
INVX2TS U1992 ( .A(n2198), .Y(n1573) );
AOI222X1TS U1993 ( .A0(n2203), .A1(data_output[41]), .B0(n2202), .B1(
d_ff_Yn[41]), .C0(n2216), .C1(d_ff_Xn[41]), .Y(n2199) );
INVX2TS U1994 ( .A(n2199), .Y(n1572) );
AOI222X1TS U1995 ( .A0(n2203), .A1(data_output[42]), .B0(n2202), .B1(
d_ff_Yn[42]), .C0(n2189), .C1(d_ff_Xn[42]), .Y(n2201) );
INVX2TS U1996 ( .A(n2201), .Y(n1571) );
INVX2TS U1997 ( .A(n2167), .Y(n2216) );
AOI222X1TS U1998 ( .A0(n2203), .A1(data_output[43]), .B0(n2202), .B1(
d_ff_Yn[43]), .C0(n2189), .C1(d_ff_Xn[43]), .Y(n2204) );
INVX2TS U1999 ( .A(n2204), .Y(n1570) );
CLKBUFX3TS U2000 ( .A(n2205), .Y(n2221) );
CLKBUFX3TS U2001 ( .A(n2206), .Y(n2218) );
AOI222X1TS U2002 ( .A0(n2221), .A1(data_output[44]), .B0(n2218), .B1(
d_ff_Yn[44]), .C0(n2200), .C1(d_ff_Xn[44]), .Y(n2207) );
INVX2TS U2003 ( .A(n2207), .Y(n1569) );
AOI222X1TS U2004 ( .A0(n2221), .A1(data_output[45]), .B0(n2218), .B1(
d_ff_Yn[45]), .C0(n2108), .C1(d_ff_Xn[45]), .Y(n2208) );
INVX2TS U2005 ( .A(n2208), .Y(n1568) );
AOI222X1TS U2006 ( .A0(n2221), .A1(data_output[46]), .B0(n2218), .B1(
d_ff_Yn[46]), .C0(n2091), .C1(d_ff_Xn[46]), .Y(n2209) );
INVX2TS U2007 ( .A(n2209), .Y(n1567) );
AOI222X1TS U2008 ( .A0(n2210), .A1(data_output[47]), .B0(n2218), .B1(
d_ff_Yn[47]), .C0(n2175), .C1(d_ff_Xn[47]), .Y(n2211) );
INVX2TS U2009 ( .A(n2211), .Y(n1566) );
AOI222X1TS U2010 ( .A0(n2221), .A1(data_output[48]), .B0(n2218), .B1(
d_ff_Yn[48]), .C0(n2227), .C1(d_ff_Xn[48]), .Y(n2212) );
INVX2TS U2011 ( .A(n2212), .Y(n1565) );
AOI222X1TS U2012 ( .A0(n2221), .A1(data_output[49]), .B0(n2218), .B1(
d_ff_Yn[49]), .C0(n2216), .C1(d_ff_Xn[49]), .Y(n2213) );
INVX2TS U2013 ( .A(n2213), .Y(n1564) );
AOI222X1TS U2014 ( .A0(n2221), .A1(data_output[50]), .B0(n2218), .B1(
d_ff_Yn[50]), .C0(n2189), .C1(d_ff_Xn[50]), .Y(n2214) );
INVX2TS U2015 ( .A(n2214), .Y(n1563) );
AOI222X1TS U2016 ( .A0(n2221), .A1(data_output[51]), .B0(n2218), .B1(
d_ff_Yn[51]), .C0(n2200), .C1(d_ff_Xn[51]), .Y(n2215) );
INVX2TS U2017 ( .A(n2215), .Y(n1562) );
AOI222X1TS U2018 ( .A0(n2221), .A1(data_output[52]), .B0(n2218), .B1(
d_ff_Yn[52]), .C0(n2108), .C1(d_ff_Xn[52]), .Y(n2217) );
INVX2TS U2019 ( .A(n2217), .Y(n1561) );
INVX2TS U2020 ( .A(n2219), .Y(n1560) );
INVX2TS U2021 ( .A(n2220), .Y(n1559) );
INVX2TS U2022 ( .A(n2222), .Y(n1558) );
INVX2TS U2023 ( .A(n2223), .Y(n1557) );
INVX2TS U2024 ( .A(n2224), .Y(n1556) );
INVX2TS U2025 ( .A(n2225), .Y(n1555) );
INVX2TS U2026 ( .A(n2226), .Y(n1554) );
INVX2TS U2027 ( .A(n2230), .Y(n1553) );
AOI22X1TS U2028 ( .A0(n2499), .A1(n2012), .B0(d_ff3_LUT_out[5]), .B1(n2657),
.Y(n2231) );
OAI21XLTS U2029 ( .A0(n2588), .A1(n2287), .B0(n2231), .Y(n1544) );
AOI22X1TS U2030 ( .A0(n2489), .A1(n2687), .B0(d_ff3_LUT_out[9]), .B1(n2538),
.Y(n2234) );
INVX2TS U2031 ( .A(n2287), .Y(n2486) );
AOI22X1TS U2032 ( .A0(n2232), .A1(n2486), .B0(n2288), .B1(n2643), .Y(n2233)
);
OAI211XLTS U2033 ( .A0(n2250), .A1(n2488), .B0(n2234), .C0(n2233), .Y(n1540)
);
AOI22X1TS U2034 ( .A0(n2489), .A1(n2687), .B0(d_ff3_LUT_out[11]), .B1(n2657),
.Y(n2236) );
AOI22X1TS U2035 ( .A0(n2485), .A1(n2643), .B0(n2288), .B1(n2012), .Y(n2235)
);
OAI211XLTS U2036 ( .A0(n2488), .A1(n2247), .B0(n2236), .C0(n2235), .Y(n1538)
);
AOI22X1TS U2037 ( .A0(n2490), .A1(n2011), .B0(d_ff3_LUT_out[14]), .B1(n2538),
.Y(n2237) );
OAI21XLTS U2038 ( .A0(n2687), .A1(n2589), .B0(n2237), .Y(n1535) );
AOI22X1TS U2039 ( .A0(n2489), .A1(n2491), .B0(d_ff3_LUT_out[15]), .B1(n2657),
.Y(n2240) );
AOI21X1TS U2040 ( .A0(n2288), .A1(n2686), .B0(n2238), .Y(n2239) );
OAI211XLTS U2041 ( .A0(n2589), .A1(n2241), .B0(n2240), .C0(n2239), .Y(n1534)
);
AOI22X1TS U2042 ( .A0(n2491), .A1(n2023), .B0(d_ff3_LUT_out[17]), .B1(n2430),
.Y(n2242) );
OAI21XLTS U2043 ( .A0(n2250), .A1(n2488), .B0(n2242), .Y(n1532) );
AOI22X1TS U2044 ( .A0(n2452), .A1(n2642), .B0(d_ff3_LUT_out[18]), .B1(n2460),
.Y(n2243) );
OAI21XLTS U2045 ( .A0(n2491), .A1(n2589), .B0(n2243), .Y(n1531) );
AOI22X1TS U2046 ( .A0(n2491), .A1(n2642), .B0(d_ff3_LUT_out[25]), .B1(n2538),
.Y(n2244) );
OAI211XLTS U2047 ( .A0(n2247), .A1(n2686), .B0(n2244), .C0(n2245), .Y(n1524)
);
AOI22X1TS U2048 ( .A0(n2288), .A1(cont_iter_out[2]), .B0(d_ff3_LUT_out[27]),
.B1(n2677), .Y(n2246) );
AOI22X1TS U2049 ( .A0(n2288), .A1(n2287), .B0(d_ff3_LUT_out[33]), .B1(n2677),
.Y(n2249) );
OAI211XLTS U2050 ( .A0(n2251), .A1(n2250), .B0(n2249), .C0(n2248), .Y(n1517)
);
AOI22X1TS U2051 ( .A0(n2490), .A1(n2012), .B0(d_ff3_LUT_out[54]), .B1(n2677),
.Y(n2252) );
AOI222X1TS U2052 ( .A0(n2256), .A1(d_ff2_Z[52]), .B0(n2019), .B1(d_ff1_Z[52]), .C0(d_ff_Zn[52]), .C1(n2254), .Y(n2253) );
INVX2TS U2053 ( .A(n2253), .Y(n1449) );
AOI222X1TS U2054 ( .A0(n2431), .A1(d_ff2_Z[53]), .B0(n2019), .B1(d_ff1_Z[53]), .C0(d_ff_Zn[53]), .C1(n2254), .Y(n2255) );
INVX2TS U2055 ( .A(n2255), .Y(n1448) );
INVX2TS U2056 ( .A(n2257), .Y(n1445) );
INVX2TS U2057 ( .A(n2258), .Y(n1444) );
INVX2TS U2058 ( .A(n2259), .Y(n1443) );
INVX2TS U2059 ( .A(n2261), .Y(n1442) );
AOI222X1TS U2060 ( .A0(n2431), .A1(d_ff2_Z[60]), .B0(n2019), .B1(d_ff1_Z[60]), .C0(d_ff_Zn[60]), .C1(n2279), .Y(n2262) );
INVX2TS U2061 ( .A(n2262), .Y(n1441) );
AOI222X1TS U2062 ( .A0(n2431), .A1(d_ff2_Z[61]), .B0(n2019), .B1(d_ff1_Z[61]), .C0(d_ff_Zn[61]), .C1(n2279), .Y(n2263) );
INVX2TS U2063 ( .A(n2263), .Y(n1440) );
AOI222X1TS U2064 ( .A0(n2431), .A1(d_ff2_Z[62]), .B0(n2019), .B1(d_ff1_Z[62]), .C0(d_ff_Zn[62]), .C1(n2279), .Y(n2264) );
INVX2TS U2065 ( .A(n2264), .Y(n1439) );
AOI22X1TS U2066 ( .A0(n2023), .A1(n2265), .B0(d_ff3_LUT_out[2]), .B1(n2460),
.Y(n2266) );
OAI211XLTS U2067 ( .A0(n2285), .A1(n2588), .B0(n2266), .C0(n2271), .Y(n1547)
);
INVX2TS U2068 ( .A(enab_cont_iter), .Y(n2638) );
NAND3BXLTS U2069 ( .AN(inst_CORDIC_FSM_v3_state_reg[2]), .B(
inst_CORDIC_FSM_v3_state_reg[1]), .C(n2267), .Y(n2275) );
OAI21XLTS U2070 ( .A0(n2654), .A1(n2638), .B0(n2275), .Y(
inst_CORDIC_FSM_v3_state_next[2]) );
INVX2TS U2071 ( .A(n2032), .Y(n2326) );
CLKBUFX3TS U2072 ( .A(n2326), .Y(n2633) );
OAI21XLTS U2073 ( .A0(n2633), .A1(n2617), .B0(n2649), .Y(
inst_CORDIC_FSM_v3_state_next[4]) );
INVX2TS U2074 ( .A(n2268), .Y(n2269) );
AOI21X1TS U2075 ( .A0(cont_iter_out[0]), .A1(n2491), .B0(n2588), .Y(n2283)
);
AOI211XLTS U2076 ( .A0(d_ff3_LUT_out[26]), .A1(n2466), .B0(n2269), .C0(n2283), .Y(n2270) );
OAI21XLTS U2077 ( .A0(n2272), .A1(n2271), .B0(n2270), .Y(n1523) );
NOR2XLTS U2078 ( .A(inst_CORDIC_FSM_v3_state_reg[4]), .B(
inst_CORDIC_FSM_v3_state_reg[5]), .Y(n2273) );
NAND3BX1TS U2079 ( .AN(n2274), .B(n2273), .C(inst_CORDIC_FSM_v3_state_reg[0]), .Y(n2615) );
NAND2X1TS U2080 ( .A(n2275), .B(n2615), .Y(n2433) );
INVX2TS U2081 ( .A(n2640), .Y(n2471) );
NOR4X1TS U2082 ( .A(n2664), .B(n2644), .C(enab_cont_iter), .D(beg_add_subt),
.Y(n2276) );
AOI32X1TS U2083 ( .A0(n2471), .A1(n2277), .A2(n2276), .B0(ready_cordic),
.B1(ack_cordic), .Y(n2278) );
OAI21XLTS U2084 ( .A0(beg_fsm_cordic), .A1(n2615), .B0(n2278), .Y(
inst_CORDIC_FSM_v3_state_next[0]) );
AOI222X1TS U2085 ( .A0(n2431), .A1(d_ff2_Z[63]), .B0(n2019), .B1(d_ff1_Z[63]), .C0(d_ff_Zn[63]), .C1(n2279), .Y(n2280) );
INVX2TS U2086 ( .A(n2280), .Y(n1438) );
NOR2XLTS U2087 ( .A(n2689), .B(cont_var_out[1]), .Y(n2281) );
INVX2TS U2088 ( .A(n2281), .Y(n2605) );
CLKBUFX2TS U2089 ( .A(n2605), .Y(n2399) );
NOR3BX2TS U2090 ( .AN(n2617), .B(enab_cont_iter), .C(ready_add_subt), .Y(
n2432) );
AOI21X1TS U2091 ( .A0(n2432), .A1(cont_var_out[1]), .B0(n2409), .Y(n2282) );
OAI21XLTS U2092 ( .A0(n2399), .A1(n2432), .B0(n2282), .Y(n1878) );
AOI21X1TS U2093 ( .A0(d_ff3_LUT_out[8]), .A1(n2649), .B0(n2283), .Y(n2284)
);
OAI31X1TS U2094 ( .A0(n2491), .A1(n2285), .A2(n2430), .B0(n2284), .Y(n1541)
);
NOR2X2TS U2095 ( .A(d_ff2_Y[52]), .B(n2009), .Y(n2586) );
AOI22X1TS U2096 ( .A0(n2679), .A1(n2586), .B0(d_ff3_sh_y_out[52]), .B1(n2677), .Y(n2286) );
AOI22X1TS U2097 ( .A0(n2288), .A1(n2287), .B0(d_ff3_LUT_out[1]), .B1(n2449),
.Y(n2290) );
OAI211XLTS U2098 ( .A0(n2497), .A1(n2589), .B0(n2290), .C0(n2289), .Y(n1548)
);
CLKBUFX3TS U2099 ( .A(n2426), .Y(n2422) );
CLKBUFX3TS U2100 ( .A(n2422), .Y(n2312) );
CLKBUFX2TS U2101 ( .A(n2605), .Y(n2365) );
CLKBUFX3TS U2102 ( .A(n2326), .Y(n2366) );
INVX2TS U2103 ( .A(n2291), .Y(add_subt_dataA[2]) );
CLKBUFX3TS U2104 ( .A(n2634), .Y(n2362) );
CLKBUFX3TS U2105 ( .A(n2326), .Y(n2608) );
INVX2TS U2106 ( .A(n2292), .Y(add_subt_dataA[3]) );
INVX2TS U2107 ( .A(n2293), .Y(add_subt_dataA[1]) );
INVX2TS U2108 ( .A(n2294), .Y(add_subt_dataA[5]) );
CLKBUFX3TS U2109 ( .A(n2326), .Y(n2316) );
INVX2TS U2110 ( .A(n2295), .Y(add_subt_dataA[6]) );
INVX2TS U2111 ( .A(n2296), .Y(add_subt_dataA[4]) );
INVX2TS U2112 ( .A(n2297), .Y(add_subt_dataA[8]) );
INVX2TS U2113 ( .A(n2298), .Y(add_subt_dataA[9]) );
INVX2TS U2114 ( .A(n2299), .Y(add_subt_dataA[10]) );
INVX2TS U2115 ( .A(n2300), .Y(add_subt_dataA[11]) );
INVX2TS U2116 ( .A(n2301), .Y(add_subt_dataA[12]) );
INVX2TS U2117 ( .A(n2302), .Y(add_subt_dataA[13]) );
CLKBUFX3TS U2118 ( .A(n2422), .Y(n2324) );
INVX2TS U2119 ( .A(n2303), .Y(add_subt_dataA[14]) );
INVX2TS U2120 ( .A(n2304), .Y(add_subt_dataA[15]) );
CLKBUFX3TS U2121 ( .A(n2326), .Y(n2328) );
INVX2TS U2122 ( .A(n2305), .Y(add_subt_dataA[16]) );
INVX2TS U2123 ( .A(n2306), .Y(add_subt_dataA[17]) );
INVX2TS U2124 ( .A(n2307), .Y(add_subt_dataA[18]) );
INVX2TS U2125 ( .A(n2308), .Y(add_subt_dataA[19]) );
INVX2TS U2126 ( .A(n2309), .Y(add_subt_dataA[20]) );
INVX2TS U2127 ( .A(n2310), .Y(add_subt_dataA[21]) );
INVX2TS U2128 ( .A(n2311), .Y(add_subt_dataA[22]) );
INVX2TS U2129 ( .A(n2313), .Y(add_subt_dataA[23]) );
CLKBUFX2TS U2130 ( .A(n2409), .Y(n2599) );
INVX2TS U2131 ( .A(n2314), .Y(add_subt_dataA[24]) );
INVX2TS U2132 ( .A(n2315), .Y(add_subt_dataA[25]) );
INVX2TS U2133 ( .A(n2318), .Y(add_subt_dataA[26]) );
CLKBUFX2TS U2134 ( .A(n2605), .Y(n2627) );
INVX2TS U2135 ( .A(n2627), .Y(n2333) );
INVX2TS U2136 ( .A(n2319), .Y(add_subt_dataA[27]) );
INVX2TS U2137 ( .A(n2320), .Y(add_subt_dataA[28]) );
INVX2TS U2138 ( .A(n2627), .Y(n2344) );
INVX2TS U2139 ( .A(n2321), .Y(add_subt_dataA[29]) );
INVX2TS U2140 ( .A(n2322), .Y(add_subt_dataA[30]) );
CLKBUFX3TS U2141 ( .A(n2599), .Y(n2348) );
INVX2TS U2142 ( .A(n2323), .Y(add_subt_dataA[31]) );
INVX2TS U2143 ( .A(n2325), .Y(add_subt_dataA[32]) );
CLKBUFX3TS U2144 ( .A(n2326), .Y(n2339) );
INVX2TS U2145 ( .A(n2327), .Y(add_subt_dataA[0]) );
INVX2TS U2146 ( .A(n2329), .Y(add_subt_dataA[33]) );
INVX2TS U2147 ( .A(n2330), .Y(add_subt_dataA[34]) );
AOI222X1TS U2148 ( .A0(n2634), .A1(d_ff2_Y[35]), .B0(n2333), .B1(d_ff2_X[35]), .C0(d_ff2_Z[35]), .C1(n2339), .Y(n2331) );
INVX2TS U2149 ( .A(n2331), .Y(add_subt_dataA[35]) );
INVX2TS U2150 ( .A(n2332), .Y(add_subt_dataA[36]) );
INVX2TS U2151 ( .A(n2334), .Y(add_subt_dataA[37]) );
INVX2TS U2152 ( .A(n2335), .Y(add_subt_dataA[38]) );
INVX2TS U2153 ( .A(n2336), .Y(add_subt_dataA[39]) );
INVX2TS U2154 ( .A(n2337), .Y(add_subt_dataA[40]) );
INVX2TS U2155 ( .A(n2338), .Y(add_subt_dataA[41]) );
INVX2TS U2156 ( .A(n2340), .Y(add_subt_dataA[42]) );
CLKBUFX3TS U2157 ( .A(n2326), .Y(n2354) );
INVX2TS U2158 ( .A(n2341), .Y(add_subt_dataA[43]) );
INVX2TS U2159 ( .A(n2342), .Y(add_subt_dataA[44]) );
INVX2TS U2160 ( .A(n2343), .Y(add_subt_dataA[45]) );
INVX2TS U2161 ( .A(n2345), .Y(add_subt_dataA[46]) );
INVX2TS U2162 ( .A(n2346), .Y(add_subt_dataA[47]) );
INVX2TS U2163 ( .A(n2347), .Y(add_subt_dataA[48]) );
INVX2TS U2164 ( .A(n2349), .Y(add_subt_dataA[49]) );
INVX2TS U2165 ( .A(n2350), .Y(add_subt_dataA[50]) );
INVX2TS U2166 ( .A(n2351), .Y(add_subt_dataA[51]) );
AOI22X1TS U2167 ( .A0(d_ff2_Y[52]), .A1(n2634), .B0(d_ff2_Z[52]), .B1(n2633),
.Y(n2352) );
AOI22X1TS U2168 ( .A0(n2620), .A1(d_ff2_X[53]), .B0(d_ff2_Z[53]), .B1(n2633),
.Y(n2353) );
OAI21XLTS U2169 ( .A0(n2688), .A1(n2606), .B0(n2353), .Y(add_subt_dataA[53])
);
INVX2TS U2170 ( .A(n2355), .Y(add_subt_dataA[54]) );
CLKBUFX3TS U2171 ( .A(n2326), .Y(n2424) );
INVX2TS U2172 ( .A(n2356), .Y(add_subt_dataA[55]) );
AOI22X1TS U2173 ( .A0(d_ff2_Y[57]), .A1(n2630), .B0(d_ff2_Z[57]), .B1(n2633),
.Y(n2357) );
OAI21XLTS U2174 ( .A0(n2700), .A1(n2605), .B0(n2357), .Y(add_subt_dataA[57])
);
AOI22X1TS U2175 ( .A0(d_ff2_Y[58]), .A1(n2630), .B0(d_ff2_Z[58]), .B1(n2633),
.Y(n2358) );
OAI21XLTS U2176 ( .A0(n2692), .A1(n2399), .B0(n2358), .Y(add_subt_dataA[58])
);
AOI22X1TS U2177 ( .A0(d_ff2_Y[60]), .A1(n2409), .B0(d_ff2_Z[60]), .B1(n2633),
.Y(n2359) );
OAI21XLTS U2178 ( .A0(n2693), .A1(n2627), .B0(n2359), .Y(add_subt_dataA[60])
);
AOI222X1TS U2179 ( .A0(n2600), .A1(d_ff2_Y[63]), .B0(n2425), .B1(d_ff2_X[63]), .C0(d_ff2_Z[63]), .C1(n2424), .Y(n2360) );
INVX2TS U2180 ( .A(n2360), .Y(add_subt_dataA[63]) );
INVX2TS U2181 ( .A(n2363), .Y(add_subt_dataA[7]) );
NAND2X2TS U2182 ( .A(n2608), .B(d_ff3_LUT_out[48]), .Y(n2610) );
NAND2X1TS U2183 ( .A(n2600), .B(d_ff3_sh_x_out[61]), .Y(n2364) );
AOI222X1TS U2184 ( .A0(n2599), .A1(d_ff3_sh_x_out[55]), .B0(n2494), .B1(
d_ff3_sh_y_out[55]), .C0(d_ff3_LUT_out[55]), .C1(n2366), .Y(n2367) );
INVX2TS U2185 ( .A(n2367), .Y(add_subt_dataB[55]) );
INVX2TS U2186 ( .A(n2368), .Y(add_subt_dataB[54]) );
AOI22X1TS U2187 ( .A0(d_ff3_sh_y_out[53]), .A1(n2620), .B0(n2630), .B1(
d_ff3_sh_x_out[53]), .Y(n2369) );
OAI21XLTS U2188 ( .A0(n2032), .A1(n2715), .B0(n2369), .Y(add_subt_dataB[53])
);
AOI222X1TS U2189 ( .A0(n2599), .A1(d_ff3_sh_x_out[52]), .B0(n2494), .B1(
d_ff3_sh_y_out[52]), .C0(n2608), .C1(d_ff3_LUT_out[52]), .Y(n2370) );
INVX2TS U2190 ( .A(n2370), .Y(add_subt_dataB[52]) );
AOI22X1TS U2191 ( .A0(n2621), .A1(d_ff3_sh_x_out[50]), .B0(n2401), .B1(
d_ff3_sh_y_out[50]), .Y(n2371) );
OAI21XLTS U2192 ( .A0(n2032), .A1(n2703), .B0(n2371), .Y(add_subt_dataB[50])
);
AOI22X1TS U2193 ( .A0(n2621), .A1(d_ff3_sh_x_out[45]), .B0(n2620), .B1(
d_ff3_sh_y_out[45]), .Y(n2372) );
OAI21XLTS U2194 ( .A0(n2616), .A1(n2714), .B0(n2372), .Y(add_subt_dataB[45])
);
CLKBUFX3TS U2195 ( .A(n2409), .Y(n2624) );
AOI22X1TS U2196 ( .A0(n2624), .A1(d_ff3_sh_x_out[43]), .B0(n2623), .B1(
d_ff3_sh_y_out[43]), .Y(n2373) );
OAI21XLTS U2197 ( .A0(n2696), .A1(n2616), .B0(n2373), .Y(add_subt_dataB[43])
);
AOI22X1TS U2198 ( .A0(n2624), .A1(d_ff3_sh_x_out[41]), .B0(n2401), .B1(
d_ff3_sh_y_out[41]), .Y(n2374) );
AOI22X1TS U2199 ( .A0(n2624), .A1(d_ff3_sh_x_out[40]), .B0(n2401), .B1(
d_ff3_sh_y_out[40]), .Y(n2375) );
OAI21XLTS U2200 ( .A0(n2033), .A1(n2691), .B0(n2375), .Y(add_subt_dataB[40])
);
INVX2TS U2201 ( .A(n2376), .Y(add_subt_dataB[39]) );
AOI22X1TS U2202 ( .A0(n2624), .A1(d_ff3_sh_x_out[38]), .B0(n2623), .B1(
d_ff3_sh_y_out[38]), .Y(n2377) );
OAI21XLTS U2203 ( .A0(n2616), .A1(n2699), .B0(n2377), .Y(add_subt_dataB[38])
);
CLKBUFX3TS U2204 ( .A(n2634), .Y(n2397) );
AOI222X1TS U2205 ( .A0(n2397), .A1(d_ff3_sh_x_out[37]), .B0(n2494), .B1(
d_ff3_sh_y_out[37]), .C0(n2608), .C1(d_ff3_LUT_out[37]), .Y(n2378) );
INVX2TS U2206 ( .A(n2378), .Y(add_subt_dataB[37]) );
CLKBUFX3TS U2207 ( .A(n2409), .Y(n2417) );
AOI22X1TS U2208 ( .A0(n2417), .A1(d_ff3_sh_x_out[36]), .B0(n2401), .B1(
d_ff3_sh_y_out[36]), .Y(n2379) );
OAI21XLTS U2209 ( .A0(n2033), .A1(n2691), .B0(n2379), .Y(add_subt_dataB[36])
);
AOI22X1TS U2210 ( .A0(n2624), .A1(d_ff3_sh_x_out[35]), .B0(n2623), .B1(
d_ff3_sh_y_out[35]), .Y(n2380) );
OAI21XLTS U2211 ( .A0(n2710), .A1(n2033), .B0(n2380), .Y(add_subt_dataB[35])
);
AOI22X1TS U2212 ( .A0(n2417), .A1(d_ff3_sh_x_out[34]), .B0(n2623), .B1(
d_ff3_sh_y_out[34]), .Y(n2381) );
OAI21XLTS U2213 ( .A0(n2696), .A1(n2616), .B0(n2381), .Y(add_subt_dataB[34])
);
INVX2TS U2214 ( .A(n2382), .Y(add_subt_dataB[33]) );
AOI22X1TS U2215 ( .A0(n2624), .A1(d_ff3_sh_x_out[32]), .B0(n2401), .B1(
d_ff3_sh_y_out[32]), .Y(n2383) );
OAI21XLTS U2216 ( .A0(n2616), .A1(n2699), .B0(n2383), .Y(add_subt_dataB[32])
);
AOI22X1TS U2217 ( .A0(n2417), .A1(d_ff3_sh_x_out[31]), .B0(n2401), .B1(
d_ff3_sh_y_out[31]), .Y(n2384) );
OAI21XLTS U2218 ( .A0(n2709), .A1(n2033), .B0(n2384), .Y(add_subt_dataB[31])
);
AOI22X1TS U2219 ( .A0(n2624), .A1(d_ff3_sh_x_out[30]), .B0(n2623), .B1(
d_ff3_sh_y_out[30]), .Y(n2385) );
OAI21XLTS U2220 ( .A0(n2033), .A1(n2698), .B0(n2385), .Y(add_subt_dataB[30])
);
INVX2TS U2221 ( .A(n2386), .Y(add_subt_dataB[29]) );
AOI22X1TS U2222 ( .A0(n2417), .A1(d_ff3_sh_x_out[28]), .B0(n2623), .B1(
d_ff3_sh_y_out[28]), .Y(n2387) );
INVX2TS U2223 ( .A(n2388), .Y(add_subt_dataB[27]) );
INVX2TS U2224 ( .A(n2389), .Y(add_subt_dataB[26]) );
CLKBUFX3TS U2225 ( .A(n2326), .Y(n2411) );
AOI222X1TS U2226 ( .A0(n2397), .A1(d_ff3_sh_x_out[25]), .B0(n2405), .B1(
d_ff3_sh_y_out[25]), .C0(d_ff3_LUT_out[25]), .C1(n2411), .Y(n2390) );
INVX2TS U2227 ( .A(n2390), .Y(add_subt_dataB[25]) );
AOI22X1TS U2228 ( .A0(n2417), .A1(d_ff3_sh_x_out[24]), .B0(n2401), .B1(
d_ff3_sh_y_out[24]), .Y(n2391) );
OAI21XLTS U2229 ( .A0(n2708), .A1(n2616), .B0(n2391), .Y(add_subt_dataB[24])
);
AOI222X1TS U2230 ( .A0(n2397), .A1(d_ff3_sh_x_out[23]), .B0(n2405), .B1(
d_ff3_sh_y_out[23]), .C0(d_ff3_LUT_out[23]), .C1(n2411), .Y(n2392) );
INVX2TS U2231 ( .A(n2392), .Y(add_subt_dataB[23]) );
AOI22X1TS U2232 ( .A0(n2417), .A1(d_ff3_sh_x_out[22]), .B0(n2623), .B1(
d_ff3_sh_y_out[22]), .Y(n2393) );
OAI21XLTS U2233 ( .A0(n2616), .A1(n2712), .B0(n2393), .Y(add_subt_dataB[22])
);
AOI222X1TS U2234 ( .A0(n2397), .A1(d_ff3_sh_x_out[21]), .B0(n2405), .B1(
d_ff3_sh_y_out[21]), .C0(n2608), .C1(d_ff3_LUT_out[21]), .Y(n2394) );
INVX2TS U2235 ( .A(n2394), .Y(add_subt_dataB[21]) );
AOI22X1TS U2236 ( .A0(n2417), .A1(d_ff3_sh_x_out[20]), .B0(n2401), .B1(
d_ff3_sh_y_out[20]), .Y(n2395) );
OAI21XLTS U2237 ( .A0(n2033), .A1(n2711), .B0(n2395), .Y(add_subt_dataB[20])
);
AOI222X1TS U2238 ( .A0(n2397), .A1(d_ff3_sh_x_out[19]), .B0(n2405), .B1(
d_ff3_sh_y_out[19]), .C0(d_ff3_LUT_out[19]), .C1(n2411), .Y(n2396) );
INVX2TS U2239 ( .A(n2396), .Y(add_subt_dataB[19]) );
AOI222X1TS U2240 ( .A0(n2397), .A1(d_ff3_sh_x_out[18]), .B0(n2405), .B1(
d_ff3_sh_y_out[18]), .C0(d_ff3_LUT_out[18]), .C1(n2411), .Y(n2398) );
INVX2TS U2241 ( .A(n2398), .Y(add_subt_dataB[18]) );
AOI222X1TS U2242 ( .A0(n2422), .A1(d_ff3_sh_x_out[17]), .B0(n2405), .B1(
d_ff3_sh_y_out[17]), .C0(d_ff3_LUT_out[17]), .C1(n2411), .Y(n2400) );
INVX2TS U2243 ( .A(n2400), .Y(add_subt_dataB[17]) );
AOI22X1TS U2244 ( .A0(n2417), .A1(d_ff3_sh_x_out[16]), .B0(n2623), .B1(
d_ff3_sh_y_out[16]), .Y(n2402) );
OAI21XLTS U2245 ( .A0(n2707), .A1(n2033), .B0(n2402), .Y(add_subt_dataB[16])
);
INVX2TS U2246 ( .A(n2403), .Y(add_subt_dataB[15]) );
AOI222X1TS U2247 ( .A0(n2600), .A1(d_ff3_sh_x_out[14]), .B0(n2405), .B1(
d_ff3_sh_y_out[14]), .C0(d_ff3_LUT_out[14]), .C1(n2411), .Y(n2404) );
INVX2TS U2248 ( .A(n2404), .Y(add_subt_dataB[14]) );
AOI222X1TS U2249 ( .A0(n2422), .A1(d_ff3_sh_x_out[13]), .B0(n2405), .B1(
d_ff3_sh_y_out[13]), .C0(n2608), .C1(d_ff3_LUT_out[13]), .Y(n2406) );
INVX2TS U2250 ( .A(n2406), .Y(add_subt_dataB[13]) );
AOI22X1TS U2251 ( .A0(n2417), .A1(d_ff3_sh_x_out[12]), .B0(n2494), .B1(
d_ff3_sh_y_out[12]), .Y(n2407) );
INVX2TS U2252 ( .A(n2408), .Y(add_subt_dataB[11]) );
INVX2TS U2253 ( .A(n2410), .Y(add_subt_dataB[10]) );
AOI222X1TS U2254 ( .A0(n2422), .A1(d_ff3_sh_x_out[9]), .B0(n2405), .B1(
d_ff3_sh_y_out[9]), .C0(d_ff3_LUT_out[9]), .C1(n2411), .Y(n2412) );
INVX2TS U2255 ( .A(n2412), .Y(add_subt_dataB[9]) );
INVX2TS U2256 ( .A(n2413), .Y(add_subt_dataB[8]) );
AOI222X1TS U2257 ( .A0(n2600), .A1(d_ff3_sh_x_out[7]), .B0(n2405), .B1(
d_ff3_sh_y_out[7]), .C0(d_ff3_LUT_out[7]), .C1(n2424), .Y(n2414) );
INVX2TS U2258 ( .A(n2414), .Y(add_subt_dataB[7]) );
AOI222X1TS U2259 ( .A0(n2422), .A1(d_ff3_sh_x_out[6]), .B0(n2425), .B1(
d_ff3_sh_y_out[6]), .C0(d_ff3_LUT_out[6]), .C1(n2424), .Y(n2415) );
INVX2TS U2260 ( .A(n2415), .Y(add_subt_dataB[6]) );
INVX2TS U2261 ( .A(n2416), .Y(add_subt_dataB[5]) );
AOI22X1TS U2262 ( .A0(n2417), .A1(d_ff3_sh_x_out[4]), .B0(n2494), .B1(
d_ff3_sh_y_out[4]), .Y(n2418) );
OAI21XLTS U2263 ( .A0(n2616), .A1(n2698), .B0(n2418), .Y(add_subt_dataB[4])
);
INVX2TS U2264 ( .A(n2419), .Y(add_subt_dataB[3]) );
AOI222X1TS U2265 ( .A0(n2600), .A1(d_ff3_sh_x_out[2]), .B0(n2421), .B1(
d_ff3_sh_y_out[2]), .C0(d_ff3_LUT_out[2]), .C1(n2424), .Y(n2420) );
INVX2TS U2266 ( .A(n2420), .Y(add_subt_dataB[2]) );
AOI222X1TS U2267 ( .A0(n2422), .A1(d_ff3_sh_x_out[1]), .B0(n2421), .B1(
d_ff3_sh_y_out[1]), .C0(d_ff3_LUT_out[1]), .C1(n2424), .Y(n2423) );
INVX2TS U2268 ( .A(n2423), .Y(add_subt_dataB[1]) );
AOI222X1TS U2269 ( .A0(n2426), .A1(d_ff3_sh_x_out[0]), .B0(n2425), .B1(
d_ff3_sh_y_out[0]), .C0(d_ff3_LUT_out[0]), .C1(n2424), .Y(n2427) );
INVX2TS U2270 ( .A(n2427), .Y(add_subt_dataB[0]) );
INVX2TS U2271 ( .A(n2434), .Y(n2548) );
AO22XLTS U2272 ( .A0(n2548), .A1(d_ff2_X[25]), .B0(n2434), .B1(
d_ff3_sh_x_out[25]), .Y(n1257) );
INVX2TS U2273 ( .A(n2449), .Y(n2545) );
AO22XLTS U2274 ( .A0(n2545), .A1(d_ff2_X[19]), .B0(n2460), .B1(
d_ff3_sh_x_out[19]), .Y(n1269) );
INVX2TS U2275 ( .A(n2434), .Y(n2559) );
CLKBUFX3TS U2276 ( .A(n2647), .Y(n2575) );
CLKBUFX3TS U2277 ( .A(n2575), .Y(n2566) );
AO22XLTS U2278 ( .A0(n2559), .A1(d_ff2_X[37]), .B0(n2566), .B1(
d_ff3_sh_x_out[37]), .Y(n1233) );
AO22XLTS U2279 ( .A0(n2559), .A1(d_ff2_X[26]), .B0(n2449), .B1(
d_ff3_sh_x_out[26]), .Y(n1255) );
CLKBUFX3TS U2280 ( .A(n2575), .Y(n2557) );
AO22XLTS U2281 ( .A0(n2559), .A1(d_ff2_X[27]), .B0(n2557), .B1(
d_ff3_sh_x_out[27]), .Y(n1253) );
AO22XLTS U2282 ( .A0(n2548), .A1(d_ff2_X[18]), .B0(n2434), .B1(
d_ff3_sh_x_out[18]), .Y(n1271) );
AO22XLTS U2283 ( .A0(n2548), .A1(d_ff2_X[23]), .B0(n2430), .B1(
d_ff3_sh_x_out[23]), .Y(n1261) );
AO22XLTS U2284 ( .A0(n2548), .A1(d_ff2_X[17]), .B0(n2460), .B1(
d_ff3_sh_x_out[17]), .Y(n1273) );
AO22XLTS U2285 ( .A0(n2559), .A1(d_ff2_X[29]), .B0(n2557), .B1(
d_ff3_sh_x_out[29]), .Y(n1249) );
CLKBUFX3TS U2286 ( .A(n2657), .Y(n2544) );
AO22XLTS U2287 ( .A0(n2548), .A1(d_ff2_X[15]), .B0(n2544), .B1(
d_ff3_sh_x_out[15]), .Y(n1277) );
INVX2TS U2288 ( .A(n2449), .Y(n2577) );
AOI222X1TS U2289 ( .A0(cont_iter_out[1]), .A1(n2586), .B0(cont_iter_out[1]),
.B1(n2688), .C0(n2586), .C1(n2688), .Y(n2438) );
NAND2X1TS U2290 ( .A(n2532), .B(n2694), .Y(n2535) );
OAI21XLTS U2291 ( .A0(n2532), .A1(n2694), .B0(n2535), .Y(n2428) );
AO22XLTS U2292 ( .A0(n2577), .A1(n2428), .B0(n2575), .B1(d_ff3_sh_y_out[58]),
.Y(n1315) );
AO22XLTS U2293 ( .A0(n2548), .A1(d_ff2_X[21]), .B0(n2449), .B1(
d_ff3_sh_x_out[21]), .Y(n1265) );
INVX2TS U2294 ( .A(n2434), .Y(n2579) );
AO22XLTS U2295 ( .A0(n2579), .A1(d_ff2_X[39]), .B0(n2566), .B1(
d_ff3_sh_x_out[39]), .Y(n1229) );
AO22XLTS U2296 ( .A0(n2559), .A1(d_ff2_X[33]), .B0(n2557), .B1(
d_ff3_sh_x_out[33]), .Y(n1241) );
NAND2X1TS U2297 ( .A(cont_iter_out[0]), .B(n2690), .Y(n2593) );
NAND2X1TS U2298 ( .A(n2583), .B(n2692), .Y(n2581) );
NAND2X1TS U2299 ( .A(n2580), .B(n2693), .Y(n2539) );
NOR2X1TS U2300 ( .A(d_ff2_X[61]), .B(n2539), .Y(n2435) );
AOI21X1TS U2301 ( .A0(d_ff2_X[61]), .A1(n2539), .B0(n2435), .Y(n2429) );
INVX2TS U2302 ( .A(n2449), .Y(n2651) );
AOI2BB2XLTS U2303 ( .B0(n2662), .B1(n2429), .A0N(d_ff3_sh_x_out[61]), .A1N(
n2651), .Y(n1184) );
INVX2TS U2304 ( .A(n2455), .Y(n2483) );
AO22XLTS U2305 ( .A0(n2483), .A1(result_add_subt[7]), .B0(n2459), .B1(
d_ff_Zn[7]), .Y(n1798) );
NAND2X1TS U2306 ( .A(cont_iter_out[1]), .B(n2637), .Y(n2567) );
OA21XLTS U2307 ( .A0(cont_iter_out[1]), .A1(n2637), .B0(n2567), .Y(n1876) );
AOI2BB2XLTS U2308 ( .B0(n2504), .B1(n2700), .A0N(d_ff_Xn[57]), .A1N(n2666),
.Y(n1199) );
AOI2BB2XLTS U2309 ( .B0(n2432), .B1(n2689), .A0N(n2689), .A1N(n2432), .Y(
n1873) );
AO22XLTS U2310 ( .A0(n2545), .A1(d_ff2_X[14]), .B0(n2544), .B1(
d_ff3_sh_x_out[14]), .Y(n1279) );
CLKBUFX2TS U2311 ( .A(n2470), .Y(n2472) );
INVX2TS U2312 ( .A(n2472), .Y(n2477) );
AO22XLTS U2313 ( .A0(n2477), .A1(d_ff1_Z[10]), .B0(n2480), .B1(data_in[10]),
.Y(n1859) );
AO22XLTS U2314 ( .A0(n2477), .A1(d_ff1_Z[9]), .B0(n2480), .B1(data_in[9]),
.Y(n1860) );
INVX2TS U2315 ( .A(n2472), .Y(n2478) );
AO22XLTS U2316 ( .A0(n2478), .A1(d_ff1_Z[8]), .B0(n2480), .B1(data_in[8]),
.Y(n1861) );
INVX2TS U2317 ( .A(n2449), .Y(n2541) );
AO22XLTS U2318 ( .A0(n2541), .A1(d_ff2_Y[63]), .B0(n2460), .B1(
d_ff3_sh_y_out[63]), .Y(n1309) );
AO22XLTS U2319 ( .A0(n2478), .A1(d_ff1_Z[7]), .B0(n2470), .B1(data_in[7]),
.Y(n1862) );
AO22XLTS U2320 ( .A0(n2541), .A1(d_ff2_X[63]), .B0(n2444), .B1(
d_ff3_sh_x_out[63]), .Y(n1181) );
CLKBUFX2TS U2321 ( .A(n2433), .Y(n2639) );
AO22XLTS U2322 ( .A0(n2478), .A1(d_ff1_Z[6]), .B0(n2639), .B1(data_in[6]),
.Y(n1863) );
AO22XLTS U2323 ( .A0(n2478), .A1(d_ff1_Z[5]), .B0(n2639), .B1(data_in[5]),
.Y(n1864) );
INVX2TS U2324 ( .A(n2538), .Y(n2596) );
XOR2XLTS U2325 ( .A(d_ff2_X[62]), .B(n2435), .Y(n2436) );
AO22XLTS U2326 ( .A0(n2596), .A1(n2436), .B0(n2449), .B1(d_ff3_sh_x_out[62]),
.Y(n1183) );
AO22XLTS U2327 ( .A0(n2478), .A1(d_ff1_Z[4]), .B0(n2640), .B1(data_in[4]),
.Y(n1865) );
NAND2X1TS U2328 ( .A(n2574), .B(n2695), .Y(n2660) );
NOR2X1TS U2329 ( .A(d_ff2_Y[61]), .B(n2660), .Y(n2659) );
XOR2XLTS U2330 ( .A(d_ff2_Y[62]), .B(n2659), .Y(n2437) );
AO22XLTS U2331 ( .A0(n2541), .A1(n2437), .B0(n2560), .B1(d_ff3_sh_y_out[62]),
.Y(n1311) );
INVX2TS U2332 ( .A(n2472), .Y(n2468) );
AO22XLTS U2333 ( .A0(n2468), .A1(d_ff1_Z[3]), .B0(n2639), .B1(data_in[3]),
.Y(n1866) );
AO22XLTS U2334 ( .A0(n2468), .A1(d_ff1_Z[2]), .B0(n2470), .B1(data_in[2]),
.Y(n1867) );
AO22XLTS U2335 ( .A0(n2468), .A1(d_ff1_Z[1]), .B0(n2639), .B1(data_in[1]),
.Y(n1868) );
AO22XLTS U2336 ( .A0(n2468), .A1(d_ff1_Z[0]), .B0(n2639), .B1(data_in[0]),
.Y(n1869) );
INVX2TS U2337 ( .A(n2459), .Y(n2619) );
AO22XLTS U2338 ( .A0(n2619), .A1(result_add_subt[63]), .B0(n2448), .B1(
d_ff_Zn[63]), .Y(n1742) );
AO22XLTS U2339 ( .A0(n2619), .A1(result_add_subt[62]), .B0(n2454), .B1(
d_ff_Zn[62]), .Y(n1743) );
INVX2TS U2340 ( .A(n2455), .Y(n2456) );
AO22XLTS U2341 ( .A0(n2456), .A1(result_add_subt[0]), .B0(n2455), .B1(
d_ff_Zn[0]), .Y(n1805) );
AO22XLTS U2342 ( .A0(n2619), .A1(result_add_subt[61]), .B0(n2455), .B1(
d_ff_Zn[61]), .Y(n1744) );
AO22XLTS U2343 ( .A0(n2619), .A1(result_add_subt[60]), .B0(n2459), .B1(
d_ff_Zn[60]), .Y(n1745) );
CMPR32X2TS U2344 ( .A(n2012), .B(d_ff2_Y[54]), .C(n2438), .CO(n2440), .S(
n2439) );
AO22XLTS U2345 ( .A0(n2577), .A1(n2439), .B0(n2560), .B1(d_ff3_sh_y_out[54]),
.Y(n1319) );
INVX2TS U2346 ( .A(n2455), .Y(n2458) );
AO22XLTS U2347 ( .A0(n2458), .A1(result_add_subt[59]), .B0(n2455), .B1(
d_ff_Zn[59]), .Y(n1746) );
AO22XLTS U2348 ( .A0(n2577), .A1(n2441), .B0(n2444), .B1(d_ff3_sh_y_out[55]),
.Y(n1318) );
AO22XLTS U2349 ( .A0(n2456), .A1(result_add_subt[58]), .B0(n2454), .B1(
d_ff_Zn[58]), .Y(n1747) );
CLKBUFX3TS U2350 ( .A(n2454), .Y(n2442) );
AO22XLTS U2351 ( .A0(n2456), .A1(result_add_subt[57]), .B0(n2442), .B1(
d_ff_Zn[57]), .Y(n1748) );
INVX2TS U2352 ( .A(n2466), .Y(n2584) );
AO22XLTS U2353 ( .A0(n2584), .A1(d_ff2_Y[0]), .B0(n2529), .B1(
d_ff3_sh_y_out[0]), .Y(n1435) );
AO22XLTS U2354 ( .A0(n2456), .A1(result_add_subt[56]), .B0(n2442), .B1(
d_ff_Zn[56]), .Y(n1749) );
AO22XLTS U2355 ( .A0(n2584), .A1(d_ff2_Y[1]), .B0(n2560), .B1(
d_ff3_sh_y_out[1]), .Y(n1433) );
AO22XLTS U2356 ( .A0(n2456), .A1(result_add_subt[55]), .B0(n2442), .B1(
d_ff_Zn[55]), .Y(n1750) );
AO22XLTS U2357 ( .A0(n2456), .A1(result_add_subt[54]), .B0(n2442), .B1(
d_ff_Zn[54]), .Y(n1751) );
AO22XLTS U2358 ( .A0(n2584), .A1(d_ff2_Y[2]), .B0(n2647), .B1(
d_ff3_sh_y_out[2]), .Y(n1431) );
AO22XLTS U2359 ( .A0(n2456), .A1(result_add_subt[53]), .B0(n2442), .B1(
d_ff_Zn[53]), .Y(n1752) );
AO22XLTS U2360 ( .A0(n2584), .A1(d_ff2_Y[3]), .B0(n2529), .B1(
d_ff3_sh_y_out[3]), .Y(n1429) );
AO22XLTS U2361 ( .A0(n2619), .A1(result_add_subt[52]), .B0(n2442), .B1(
d_ff_Zn[52]), .Y(n1753) );
AO22XLTS U2362 ( .A0(n2619), .A1(result_add_subt[51]), .B0(n2442), .B1(
d_ff_Zn[51]), .Y(n1754) );
AO22XLTS U2363 ( .A0(n2584), .A1(d_ff2_Y[5]), .B0(n2560), .B1(
d_ff3_sh_y_out[5]), .Y(n1425) );
AO22XLTS U2364 ( .A0(n2619), .A1(result_add_subt[50]), .B0(n2442), .B1(
d_ff_Zn[50]), .Y(n1755) );
INVX2TS U2365 ( .A(n2434), .Y(n2573) );
AO22XLTS U2366 ( .A0(n2573), .A1(d_ff2_Y[6]), .B0(n2444), .B1(
d_ff3_sh_y_out[6]), .Y(n1423) );
AO22XLTS U2367 ( .A0(n2619), .A1(result_add_subt[49]), .B0(n2442), .B1(
d_ff_Zn[49]), .Y(n1756) );
INVX2TS U2368 ( .A(n2448), .Y(n2446) );
AO22XLTS U2369 ( .A0(n2446), .A1(result_add_subt[48]), .B0(n2442), .B1(
d_ff_Zn[48]), .Y(n1757) );
AO22XLTS U2370 ( .A0(n2573), .A1(d_ff2_Y[7]), .B0(n2647), .B1(
d_ff3_sh_y_out[7]), .Y(n1421) );
CLKBUFX3TS U2371 ( .A(n2454), .Y(n2443) );
AO22XLTS U2372 ( .A0(n2446), .A1(result_add_subt[47]), .B0(n2443), .B1(
d_ff_Zn[47]), .Y(n1758) );
AO22XLTS U2373 ( .A0(n2573), .A1(d_ff2_Y[8]), .B0(n2647), .B1(
d_ff3_sh_y_out[8]), .Y(n1419) );
AO22XLTS U2374 ( .A0(n2446), .A1(result_add_subt[46]), .B0(n2443), .B1(
d_ff_Zn[46]), .Y(n1759) );
AO22XLTS U2375 ( .A0(n2446), .A1(result_add_subt[45]), .B0(n2443), .B1(
d_ff_Zn[45]), .Y(n1760) );
AO22XLTS U2376 ( .A0(n2573), .A1(d_ff2_Y[9]), .B0(n2444), .B1(
d_ff3_sh_y_out[9]), .Y(n1417) );
AO22XLTS U2377 ( .A0(n2446), .A1(result_add_subt[44]), .B0(n2443), .B1(
d_ff_Zn[44]), .Y(n1761) );
CLKBUFX2TS U2378 ( .A(n2529), .Y(n2653) );
AO22XLTS U2379 ( .A0(n2573), .A1(d_ff2_Y[10]), .B0(n2653), .B1(
d_ff3_sh_y_out[10]), .Y(n1415) );
AO22XLTS U2380 ( .A0(n2446), .A1(result_add_subt[43]), .B0(n2443), .B1(
d_ff_Zn[43]), .Y(n1762) );
INVX2TS U2381 ( .A(n2455), .Y(n2457) );
AO22XLTS U2382 ( .A0(n2457), .A1(result_add_subt[42]), .B0(n2443), .B1(
d_ff_Zn[42]), .Y(n1763) );
AO22XLTS U2383 ( .A0(n2573), .A1(d_ff2_Y[11]), .B0(n2529), .B1(
d_ff3_sh_y_out[11]), .Y(n1413) );
AO22XLTS U2384 ( .A0(n2477), .A1(d_ff1_Z[11]), .B0(n2480), .B1(data_in[11]),
.Y(n1858) );
AO22XLTS U2385 ( .A0(n2457), .A1(result_add_subt[41]), .B0(n2443), .B1(
d_ff_Zn[41]), .Y(n1764) );
AO22XLTS U2386 ( .A0(n2573), .A1(d_ff2_Y[13]), .B0(n2444), .B1(
d_ff3_sh_y_out[13]), .Y(n1409) );
AO22XLTS U2387 ( .A0(n2457), .A1(result_add_subt[40]), .B0(n2443), .B1(
d_ff_Zn[40]), .Y(n1765) );
AO22XLTS U2388 ( .A0(n2457), .A1(result_add_subt[39]), .B0(n2443), .B1(
d_ff_Zn[39]), .Y(n1766) );
AO22XLTS U2389 ( .A0(n2573), .A1(d_ff2_Y[14]), .B0(n2653), .B1(
d_ff3_sh_y_out[14]), .Y(n1407) );
AO22XLTS U2390 ( .A0(n2619), .A1(result_add_subt[38]), .B0(n2443), .B1(
d_ff_Zn[38]), .Y(n1767) );
AO22XLTS U2391 ( .A0(n2573), .A1(d_ff2_Y[15]), .B0(n2560), .B1(
d_ff3_sh_y_out[15]), .Y(n1405) );
INVX2TS U2392 ( .A(n2459), .Y(n2445) );
CLKBUFX3TS U2393 ( .A(n2454), .Y(n2447) );
AO22XLTS U2394 ( .A0(n2445), .A1(result_add_subt[37]), .B0(n2447), .B1(
d_ff_Zn[37]), .Y(n1768) );
AO22XLTS U2395 ( .A0(n2445), .A1(result_add_subt[36]), .B0(n2447), .B1(
d_ff_Zn[36]), .Y(n1769) );
INVX2TS U2396 ( .A(n2460), .Y(n2561) );
AO22XLTS U2397 ( .A0(n2561), .A1(d_ff2_Y[17]), .B0(n2444), .B1(
d_ff3_sh_y_out[17]), .Y(n1401) );
AO22XLTS U2398 ( .A0(n2445), .A1(result_add_subt[35]), .B0(n2447), .B1(
d_ff_Zn[35]), .Y(n1770) );
CLKBUFX3TS U2399 ( .A(n2444), .Y(n2560) );
AO22XLTS U2400 ( .A0(n2561), .A1(d_ff2_Y[18]), .B0(n2647), .B1(
d_ff3_sh_y_out[18]), .Y(n1399) );
AO22XLTS U2401 ( .A0(n2445), .A1(result_add_subt[34]), .B0(n2447), .B1(
d_ff_Zn[34]), .Y(n1771) );
AO22XLTS U2402 ( .A0(n2445), .A1(result_add_subt[33]), .B0(n2447), .B1(
d_ff_Zn[33]), .Y(n1772) );
AO22XLTS U2403 ( .A0(n2561), .A1(d_ff2_Y[19]), .B0(n2529), .B1(
d_ff3_sh_y_out[19]), .Y(n1397) );
AO22XLTS U2404 ( .A0(n2446), .A1(result_add_subt[32]), .B0(n2447), .B1(
d_ff_Zn[32]), .Y(n1773) );
AO22XLTS U2405 ( .A0(n2561), .A1(d_ff2_Y[21]), .B0(n2560), .B1(
d_ff3_sh_y_out[21]), .Y(n1393) );
AO22XLTS U2406 ( .A0(n2446), .A1(result_add_subt[31]), .B0(n2447), .B1(
d_ff_Zn[31]), .Y(n1774) );
AO22XLTS U2407 ( .A0(n2446), .A1(result_add_subt[30]), .B0(n2447), .B1(
d_ff_Zn[30]), .Y(n1775) );
AO22XLTS U2408 ( .A0(n2561), .A1(d_ff2_Y[23]), .B0(n2647), .B1(
d_ff3_sh_y_out[23]), .Y(n1389) );
AO22XLTS U2409 ( .A0(n2446), .A1(result_add_subt[29]), .B0(n2447), .B1(
d_ff_Zn[29]), .Y(n1776) );
AO22XLTS U2410 ( .A0(n2561), .A1(d_ff2_Y[25]), .B0(n2529), .B1(
d_ff3_sh_y_out[25]), .Y(n1385) );
AO22XLTS U2411 ( .A0(n2458), .A1(result_add_subt[28]), .B0(n2447), .B1(
d_ff_Zn[28]), .Y(n1777) );
CLKBUFX3TS U2412 ( .A(n2448), .Y(n2450) );
AO22XLTS U2413 ( .A0(n2458), .A1(result_add_subt[27]), .B0(n2450), .B1(
d_ff_Zn[27]), .Y(n1778) );
INVX2TS U2414 ( .A(n2449), .Y(n2551) );
CLKBUFX3TS U2415 ( .A(n2575), .Y(n2550) );
AO22XLTS U2416 ( .A0(n2551), .A1(d_ff2_Y[26]), .B0(n2550), .B1(
d_ff3_sh_y_out[26]), .Y(n1383) );
AO22XLTS U2417 ( .A0(n2458), .A1(result_add_subt[26]), .B0(n2450), .B1(
d_ff_Zn[26]), .Y(n1779) );
AO22XLTS U2418 ( .A0(n2551), .A1(d_ff2_Y[27]), .B0(n2560), .B1(
d_ff3_sh_y_out[27]), .Y(n1381) );
AO22XLTS U2419 ( .A0(n2458), .A1(result_add_subt[25]), .B0(n2450), .B1(
d_ff_Zn[25]), .Y(n1780) );
AO22XLTS U2420 ( .A0(n2458), .A1(result_add_subt[24]), .B0(n2450), .B1(
d_ff_Zn[24]), .Y(n1781) );
AO22XLTS U2421 ( .A0(n2551), .A1(d_ff2_Y[29]), .B0(n2550), .B1(
d_ff3_sh_y_out[29]), .Y(n1377) );
AO22XLTS U2422 ( .A0(n2483), .A1(result_add_subt[23]), .B0(n2450), .B1(
d_ff_Zn[23]), .Y(n1782) );
AO22XLTS U2423 ( .A0(n2551), .A1(d_ff2_Y[33]), .B0(n2550), .B1(
d_ff3_sh_y_out[33]), .Y(n1369) );
AO22XLTS U2424 ( .A0(n2483), .A1(result_add_subt[22]), .B0(n2450), .B1(
d_ff_Zn[22]), .Y(n1783) );
AO22XLTS U2425 ( .A0(n2483), .A1(result_add_subt[21]), .B0(n2450), .B1(
d_ff_Zn[21]), .Y(n1784) );
INVX2TS U2426 ( .A(n2460), .Y(n2528) );
AO22XLTS U2427 ( .A0(n2528), .A1(d_ff2_Y[37]), .B0(n2550), .B1(
d_ff3_sh_y_out[37]), .Y(n1361) );
AO22XLTS U2428 ( .A0(n2483), .A1(result_add_subt[20]), .B0(n2450), .B1(
d_ff_Zn[20]), .Y(n1785) );
CLKBUFX3TS U2429 ( .A(n2575), .Y(n2527) );
AO22XLTS U2430 ( .A0(n2528), .A1(d_ff2_Y[39]), .B0(n2527), .B1(
d_ff3_sh_y_out[39]), .Y(n1357) );
AO22XLTS U2431 ( .A0(n2483), .A1(result_add_subt[19]), .B0(n2450), .B1(
d_ff_Zn[19]), .Y(n1786) );
AO22XLTS U2432 ( .A0(n2457), .A1(result_add_subt[18]), .B0(n2450), .B1(
d_ff_Zn[18]), .Y(n1787) );
AOI22X1TS U2433 ( .A0(n2452), .A1(n2683), .B0(n2588), .B1(n2451), .Y(n2453)
);
AO21XLTS U2434 ( .A0(d_ff3_LUT_out[0]), .A1(n2653), .B0(n2453), .Y(n1549) );
CLKBUFX3TS U2435 ( .A(n2454), .Y(n2482) );
AO22XLTS U2436 ( .A0(n2457), .A1(result_add_subt[17]), .B0(n2482), .B1(
d_ff_Zn[17]), .Y(n1788) );
AO22XLTS U2437 ( .A0(n2456), .A1(result_add_subt[1]), .B0(n2455), .B1(
d_ff_Zn[1]), .Y(n1804) );
AO22XLTS U2438 ( .A0(n2457), .A1(result_add_subt[16]), .B0(n2482), .B1(
d_ff_Zn[16]), .Y(n1789) );
AO22XLTS U2439 ( .A0(n2457), .A1(result_add_subt[15]), .B0(n2482), .B1(
d_ff_Zn[15]), .Y(n1790) );
AO22XLTS U2440 ( .A0(n2456), .A1(result_add_subt[2]), .B0(n2459), .B1(
d_ff_Zn[2]), .Y(n1803) );
AO22XLTS U2441 ( .A0(n2457), .A1(result_add_subt[14]), .B0(n2482), .B1(
d_ff_Zn[14]), .Y(n1791) );
AO22XLTS U2442 ( .A0(n2456), .A1(result_add_subt[3]), .B0(n2459), .B1(
d_ff_Zn[3]), .Y(n1802) );
AO22XLTS U2443 ( .A0(n2457), .A1(result_add_subt[13]), .B0(n2482), .B1(
d_ff_Zn[13]), .Y(n1792) );
AO22XLTS U2444 ( .A0(n2458), .A1(result_add_subt[12]), .B0(n2482), .B1(
d_ff_Zn[12]), .Y(n1793) );
AO22XLTS U2445 ( .A0(n2483), .A1(result_add_subt[4]), .B0(n2459), .B1(
d_ff_Zn[4]), .Y(n1801) );
AO22XLTS U2446 ( .A0(n2458), .A1(result_add_subt[11]), .B0(n2482), .B1(
d_ff_Zn[11]), .Y(n1794) );
AO22XLTS U2447 ( .A0(n2483), .A1(result_add_subt[5]), .B0(n2459), .B1(
d_ff_Zn[5]), .Y(n1800) );
AO22XLTS U2448 ( .A0(n2458), .A1(result_add_subt[10]), .B0(n2482), .B1(
d_ff_Zn[10]), .Y(n1795) );
AO22XLTS U2449 ( .A0(n2458), .A1(result_add_subt[9]), .B0(n2482), .B1(
d_ff_Zn[9]), .Y(n1796) );
AO22XLTS U2450 ( .A0(n2483), .A1(result_add_subt[6]), .B0(n2459), .B1(
d_ff_Zn[6]), .Y(n1799) );
AO22XLTS U2451 ( .A0(n2477), .A1(d_ff1_Z[12]), .B0(n2480), .B1(data_in[12]),
.Y(n1857) );
AO22XLTS U2452 ( .A0(n2545), .A1(d_ff2_X[13]), .B0(n2544), .B1(
d_ff3_sh_x_out[13]), .Y(n1281) );
AO22XLTS U2453 ( .A0(n2545), .A1(d_ff2_X[11]), .B0(n2544), .B1(
d_ff3_sh_x_out[11]), .Y(n1285) );
AO22XLTS U2454 ( .A0(n2541), .A1(d_ff2_X[10]), .B0(n2544), .B1(
d_ff3_sh_x_out[10]), .Y(n1287) );
AO22XLTS U2455 ( .A0(n2545), .A1(d_ff2_X[9]), .B0(n2544), .B1(
d_ff3_sh_x_out[9]), .Y(n1289) );
AO22XLTS U2456 ( .A0(n2545), .A1(d_ff2_X[8]), .B0(n2544), .B1(
d_ff3_sh_x_out[8]), .Y(n1291) );
AO22XLTS U2457 ( .A0(n2545), .A1(d_ff2_X[7]), .B0(n2544), .B1(
d_ff3_sh_x_out[7]), .Y(n1293) );
AO22XLTS U2458 ( .A0(n2545), .A1(d_ff2_X[6]), .B0(n2649), .B1(
d_ff3_sh_x_out[6]), .Y(n1295) );
AO22XLTS U2459 ( .A0(n2541), .A1(d_ff2_X[5]), .B0(n2649), .B1(
d_ff3_sh_x_out[5]), .Y(n1297) );
AO22XLTS U2460 ( .A0(n2541), .A1(d_ff2_X[3]), .B0(n2649), .B1(
d_ff3_sh_x_out[3]), .Y(n1301) );
AO22XLTS U2461 ( .A0(n2541), .A1(d_ff2_X[2]), .B0(n2649), .B1(
d_ff3_sh_x_out[2]), .Y(n1303) );
AO22XLTS U2462 ( .A0(n2541), .A1(d_ff2_X[1]), .B0(n2649), .B1(
d_ff3_sh_x_out[1]), .Y(n1305) );
AO22XLTS U2463 ( .A0(n2541), .A1(d_ff2_X[0]), .B0(n2657), .B1(
d_ff3_sh_x_out[0]), .Y(n1307) );
CMPR32X2TS U2464 ( .A(d_ff2_X[55]), .B(n2687), .C(n2461), .CO(n2676), .S(
n2462) );
CLKBUFX3TS U2465 ( .A(n2575), .Y(n2594) );
AO22XLTS U2466 ( .A0(n2596), .A1(n2462), .B0(n2594), .B1(d_ff3_sh_x_out[55]),
.Y(n1190) );
CMPR32X2TS U2467 ( .A(d_ff2_X[54]), .B(n2012), .C(n2463), .CO(n2461), .S(
n2464) );
AO22XLTS U2468 ( .A0(n2596), .A1(n2464), .B0(n2594), .B1(d_ff3_sh_x_out[54]),
.Y(n1191) );
OAI22X1TS U2469 ( .A0(n2466), .A1(n2593), .B0(n2690), .B1(n2465), .Y(n2467)
);
AO21XLTS U2470 ( .A0(d_ff3_sh_x_out[52]), .A1(n2653), .B0(n2467), .Y(n1193)
);
CLKBUFX3TS U2471 ( .A(n2470), .Y(n2476) );
AO22XLTS U2472 ( .A0(n2471), .A1(d_ff1_Z[63]), .B0(n2476), .B1(data_in[63]),
.Y(n1806) );
AO22XLTS U2473 ( .A0(n2471), .A1(d_ff1_Z[62]), .B0(n2470), .B1(data_in[62]),
.Y(n1807) );
AO22XLTS U2474 ( .A0(n2471), .A1(d_ff1_Z[61]), .B0(n2640), .B1(data_in[61]),
.Y(n1808) );
AO22XLTS U2475 ( .A0(n2471), .A1(d_ff1_Z[60]), .B0(n2472), .B1(data_in[60]),
.Y(n1809) );
AO22XLTS U2476 ( .A0(n2477), .A1(d_ff1_Z[59]), .B0(n2640), .B1(data_in[59]),
.Y(n1810) );
AO22XLTS U2477 ( .A0(n2468), .A1(d_ff1_Z[58]), .B0(n2640), .B1(data_in[58]),
.Y(n1811) );
AO22XLTS U2478 ( .A0(n2468), .A1(d_ff1_Z[57]), .B0(n2640), .B1(data_in[57]),
.Y(n1812) );
CLKBUFX3TS U2479 ( .A(n2470), .Y(n2469) );
AO22XLTS U2480 ( .A0(n2468), .A1(d_ff1_Z[56]), .B0(n2469), .B1(data_in[56]),
.Y(n1813) );
AO22XLTS U2481 ( .A0(n2468), .A1(d_ff1_Z[55]), .B0(n2469), .B1(data_in[55]),
.Y(n1814) );
AO22XLTS U2482 ( .A0(n2468), .A1(d_ff1_Z[54]), .B0(n2469), .B1(data_in[54]),
.Y(n1815) );
AO22XLTS U2483 ( .A0(n2468), .A1(d_ff1_Z[53]), .B0(n2469), .B1(data_in[53]),
.Y(n1816) );
AO22XLTS U2484 ( .A0(n2471), .A1(d_ff1_Z[52]), .B0(n2469), .B1(data_in[52]),
.Y(n1817) );
AO22XLTS U2485 ( .A0(n2471), .A1(d_ff1_Z[51]), .B0(n2469), .B1(data_in[51]),
.Y(n1818) );
AO22XLTS U2486 ( .A0(n2471), .A1(d_ff1_Z[50]), .B0(n2469), .B1(data_in[50]),
.Y(n1819) );
AO22XLTS U2487 ( .A0(n2471), .A1(d_ff1_Z[49]), .B0(n2469), .B1(data_in[49]),
.Y(n1820) );
INVX2TS U2488 ( .A(n2470), .Y(n2475) );
AO22XLTS U2489 ( .A0(n2475), .A1(d_ff1_Z[48]), .B0(n2469), .B1(data_in[48]),
.Y(n1821) );
AO22XLTS U2490 ( .A0(n2475), .A1(d_ff1_Z[47]), .B0(n2469), .B1(data_in[47]),
.Y(n1822) );
CLKBUFX3TS U2491 ( .A(n2470), .Y(n2473) );
AO22XLTS U2492 ( .A0(n2475), .A1(d_ff1_Z[46]), .B0(n2473), .B1(data_in[46]),
.Y(n1823) );
AO22XLTS U2493 ( .A0(n2475), .A1(d_ff1_Z[45]), .B0(n2473), .B1(data_in[45]),
.Y(n1824) );
AO22XLTS U2494 ( .A0(n2475), .A1(d_ff1_Z[44]), .B0(n2473), .B1(data_in[44]),
.Y(n1825) );
AO22XLTS U2495 ( .A0(n2475), .A1(d_ff1_Z[43]), .B0(n2473), .B1(data_in[43]),
.Y(n1826) );
INVX2TS U2496 ( .A(n2472), .Y(n2481) );
AO22XLTS U2497 ( .A0(n2481), .A1(d_ff1_Z[42]), .B0(n2473), .B1(data_in[42]),
.Y(n1827) );
AO22XLTS U2498 ( .A0(n2481), .A1(d_ff1_Z[41]), .B0(n2473), .B1(data_in[41]),
.Y(n1828) );
AO22XLTS U2499 ( .A0(n2481), .A1(d_ff1_Z[40]), .B0(n2473), .B1(data_in[40]),
.Y(n1829) );
AO22XLTS U2500 ( .A0(n2481), .A1(d_ff1_Z[39]), .B0(n2473), .B1(data_in[39]),
.Y(n1830) );
AO22XLTS U2501 ( .A0(n2471), .A1(d_ff1_Z[38]), .B0(n2473), .B1(data_in[38]),
.Y(n1831) );
INVX2TS U2502 ( .A(n2472), .Y(n2474) );
AO22XLTS U2503 ( .A0(n2474), .A1(d_ff1_Z[37]), .B0(n2473), .B1(data_in[37]),
.Y(n1832) );
AO22XLTS U2504 ( .A0(n2474), .A1(d_ff1_Z[36]), .B0(n2476), .B1(data_in[36]),
.Y(n1833) );
AO22XLTS U2505 ( .A0(n2474), .A1(d_ff1_Z[35]), .B0(n2476), .B1(data_in[35]),
.Y(n1834) );
AO22XLTS U2506 ( .A0(n2474), .A1(d_ff1_Z[34]), .B0(n2476), .B1(data_in[34]),
.Y(n1835) );
AO22XLTS U2507 ( .A0(n2474), .A1(d_ff1_Z[33]), .B0(n2476), .B1(data_in[33]),
.Y(n1836) );
AO22XLTS U2508 ( .A0(n2475), .A1(d_ff1_Z[32]), .B0(n2476), .B1(data_in[32]),
.Y(n1837) );
AO22XLTS U2509 ( .A0(n2475), .A1(d_ff1_Z[31]), .B0(n2476), .B1(data_in[31]),
.Y(n1838) );
AO22XLTS U2510 ( .A0(n2475), .A1(d_ff1_Z[30]), .B0(n2476), .B1(data_in[30]),
.Y(n1839) );
AO22XLTS U2511 ( .A0(n2475), .A1(d_ff1_Z[29]), .B0(n2476), .B1(data_in[29]),
.Y(n1840) );
AO22XLTS U2512 ( .A0(n2477), .A1(d_ff1_Z[28]), .B0(n2476), .B1(data_in[28]),
.Y(n1841) );
CLKBUFX3TS U2513 ( .A(n2480), .Y(n2479) );
AO22XLTS U2514 ( .A0(n2477), .A1(d_ff1_Z[27]), .B0(n2479), .B1(data_in[27]),
.Y(n1842) );
AO22XLTS U2515 ( .A0(n2477), .A1(d_ff1_Z[26]), .B0(n2479), .B1(data_in[26]),
.Y(n1843) );
AO22XLTS U2516 ( .A0(n2477), .A1(d_ff1_Z[25]), .B0(n2479), .B1(data_in[25]),
.Y(n1844) );
AO22XLTS U2517 ( .A0(n2477), .A1(d_ff1_Z[24]), .B0(n2479), .B1(data_in[24]),
.Y(n1845) );
AO22XLTS U2518 ( .A0(n2478), .A1(d_ff1_Z[23]), .B0(n2479), .B1(data_in[23]),
.Y(n1846) );
AO22XLTS U2519 ( .A0(n2478), .A1(d_ff1_Z[22]), .B0(n2479), .B1(data_in[22]),
.Y(n1847) );
AO22XLTS U2520 ( .A0(n2478), .A1(d_ff1_Z[21]), .B0(n2479), .B1(data_in[21]),
.Y(n1848) );
AO22XLTS U2521 ( .A0(n2478), .A1(d_ff1_Z[20]), .B0(n2479), .B1(data_in[20]),
.Y(n1849) );
AO22XLTS U2522 ( .A0(n2478), .A1(d_ff1_Z[19]), .B0(n2479), .B1(data_in[19]),
.Y(n1850) );
AO22XLTS U2523 ( .A0(n2481), .A1(d_ff1_Z[18]), .B0(n2479), .B1(data_in[18]),
.Y(n1851) );
AO22XLTS U2524 ( .A0(n2481), .A1(d_ff1_Z[17]), .B0(n2480), .B1(data_in[17]),
.Y(n1852) );
AO22XLTS U2525 ( .A0(n2481), .A1(d_ff1_Z[16]), .B0(n2640), .B1(data_in[16]),
.Y(n1853) );
AO22XLTS U2526 ( .A0(n2481), .A1(d_ff1_Z[15]), .B0(n2480), .B1(data_in[15]),
.Y(n1854) );
AO22XLTS U2527 ( .A0(n2481), .A1(d_ff1_Z[14]), .B0(n2470), .B1(data_in[14]),
.Y(n1855) );
AO22XLTS U2528 ( .A0(n2481), .A1(d_ff1_Z[13]), .B0(n2480), .B1(data_in[13]),
.Y(n1856) );
AO22XLTS U2529 ( .A0(n2483), .A1(result_add_subt[8]), .B0(n2482), .B1(
d_ff_Zn[8]), .Y(n1797) );
INVX2TS U2530 ( .A(n2667), .Y(n2562) );
INVX2TS U2531 ( .A(n2717), .Y(n2524) );
AO22XLTS U2532 ( .A0(n2562), .A1(d_ff_Yn[20]), .B0(d_ff2_Y[20]), .B1(n2524),
.Y(n1396) );
INVX2TS U2533 ( .A(n2667), .Y(n2598) );
INVX2TS U2534 ( .A(n2670), .Y(n2597) );
AO22XLTS U2535 ( .A0(n2598), .A1(d_ff_Xn[5]), .B0(d_ff2_X[5]), .B1(n2597),
.Y(n1298) );
NAND3BXLTS U2536 ( .AN(cont_var_out[1]), .B(ready_add_subt), .C(n2689), .Y(
n2484) );
CLKBUFX2TS U2537 ( .A(n2484), .Y(n2565) );
CLKBUFX2TS U2538 ( .A(n2565), .Y(n2569) );
INVX2TS U2539 ( .A(n2569), .Y(n2526) );
CLKBUFX3TS U2540 ( .A(n2484), .Y(n2505) );
AO22XLTS U2541 ( .A0(n2526), .A1(result_add_subt[28]), .B0(n2505), .B1(
d_ff_Xn[28]), .Y(n1649) );
INVX2TS U2542 ( .A(n2670), .Y(n2563) );
AO22XLTS U2543 ( .A0(n2598), .A1(d_ff_Xn[4]), .B0(d_ff2_X[4]), .B1(n2563),
.Y(n1300) );
AO22XLTS U2544 ( .A0(n2526), .A1(result_add_subt[26]), .B0(n2505), .B1(
d_ff_Xn[26]), .Y(n1651) );
AOI22X1TS U2545 ( .A0(n2485), .A1(cont_iter_out[2]), .B0(d_ff3_LUT_out[6]),
.B1(n2657), .Y(n2487) );
AOI32X1TS U2546 ( .A0(n2589), .A1(n2487), .A2(n2652), .B0(n2486), .B1(n2487),
.Y(n1543) );
AO22XLTS U2547 ( .A0(n2526), .A1(result_add_subt[24]), .B0(n2505), .B1(
d_ff_Xn[24]), .Y(n1653) );
AO22XLTS U2548 ( .A0(n2598), .A1(d_ff_Xn[2]), .B0(d_ff2_X[2]), .B1(n2563),
.Y(n1304) );
INVX2TS U2549 ( .A(n2569), .Y(n2503) );
AO22XLTS U2550 ( .A0(n2503), .A1(result_add_subt[19]), .B0(n2505), .B1(
d_ff_Xn[19]), .Y(n1658) );
INVX2TS U2551 ( .A(n2671), .Y(n2511) );
AO22XLTS U2552 ( .A0(n2511), .A1(d_ff_Xn[1]), .B0(d_ff2_X[1]), .B1(n2563),
.Y(n1306) );
CLKBUFX2TS U2553 ( .A(n2565), .Y(n2508) );
CLKBUFX3TS U2554 ( .A(n2508), .Y(n2502) );
AO22XLTS U2555 ( .A0(n2503), .A1(result_add_subt[14]), .B0(n2502), .B1(
d_ff_Xn[14]), .Y(n1663) );
AO22XLTS U2556 ( .A0(n2503), .A1(result_add_subt[13]), .B0(n2502), .B1(
d_ff_Xn[13]), .Y(n1664) );
CLKBUFX2TS U2557 ( .A(n2565), .Y(n2568) );
INVX2TS U2558 ( .A(n2568), .Y(n2554) );
CLKBUFX3TS U2559 ( .A(n2508), .Y(n2558) );
AO22XLTS U2560 ( .A0(n2554), .A1(result_add_subt[57]), .B0(n2558), .B1(
d_ff_Xn[57]), .Y(n1620) );
AO22XLTS U2561 ( .A0(n2503), .A1(result_add_subt[11]), .B0(n2502), .B1(
d_ff_Xn[11]), .Y(n1666) );
AOI22X1TS U2562 ( .A0(n2489), .A1(n2488), .B0(d_ff3_LUT_out[23]), .B1(n2460),
.Y(n2493) );
OAI211XLTS U2563 ( .A0(cont_iter_out[1]), .A1(cont_iter_out[0]), .B0(n2491),
.C0(n2490), .Y(n2492) );
NAND2X1TS U2564 ( .A(n2493), .B(n2492), .Y(n1526) );
NAND2X1TS U2565 ( .A(n2494), .B(ready_add_subt), .Y(n2517) );
CLKBUFX2TS U2566 ( .A(n2517), .Y(n2506) );
CLKBUFX2TS U2567 ( .A(n2506), .Y(n2530) );
INVX2TS U2568 ( .A(n2530), .Y(n2546) );
CLKBUFX2TS U2569 ( .A(n2506), .Y(n2513) );
AO22XLTS U2570 ( .A0(n2546), .A1(result_add_subt[62]), .B0(n2517), .B1(
d_ff_Yn[62]), .Y(n1679) );
INVX2TS U2571 ( .A(n2568), .Y(n2549) );
AO22XLTS U2572 ( .A0(n2549), .A1(result_add_subt[9]), .B0(n2502), .B1(
d_ff_Xn[9]), .Y(n1668) );
AO22XLTS U2573 ( .A0(n2554), .A1(result_add_subt[52]), .B0(n2558), .B1(
d_ff_Xn[52]), .Y(n1625) );
AO22XLTS U2574 ( .A0(n2549), .A1(result_add_subt[8]), .B0(n2507), .B1(
d_ff_Xn[8]), .Y(n1669) );
AO22XLTS U2575 ( .A0(n2546), .A1(result_add_subt[61]), .B0(n2517), .B1(
d_ff_Yn[61]), .Y(n1680) );
AOI22X1TS U2576 ( .A0(n2679), .A1(n2654), .B0(d_ff3_LUT_out[29]), .B1(n2677),
.Y(n2495) );
NAND2X1TS U2577 ( .A(n2496), .B(n2495), .Y(n1520) );
AO22XLTS U2578 ( .A0(n2549), .A1(result_add_subt[7]), .B0(n2507), .B1(
d_ff_Xn[7]), .Y(n1670) );
INVX2TS U2579 ( .A(n2530), .Y(n2500) );
CLKBUFX3TS U2580 ( .A(n2513), .Y(n2501) );
AO22XLTS U2581 ( .A0(n2500), .A1(result_add_subt[52]), .B0(n2501), .B1(
d_ff_Yn[52]), .Y(n1689) );
AO22XLTS U2582 ( .A0(n2500), .A1(result_add_subt[59]), .B0(n2513), .B1(
d_ff_Yn[59]), .Y(n1682) );
AOI22X1TS U2583 ( .A0(n2497), .A1(n2642), .B0(d_ff3_LUT_out[39]), .B1(n2677),
.Y(n2498) );
AO22XLTS U2584 ( .A0(n2549), .A1(result_add_subt[6]), .B0(n2507), .B1(
d_ff_Xn[6]), .Y(n1671) );
AO22XLTS U2585 ( .A0(n2549), .A1(result_add_subt[3]), .B0(n2507), .B1(
d_ff_Xn[3]), .Y(n1674) );
AO22XLTS U2586 ( .A0(n2500), .A1(result_add_subt[57]), .B0(n2501), .B1(
d_ff_Yn[57]), .Y(n1684) );
AO22XLTS U2587 ( .A0(n2500), .A1(result_add_subt[53]), .B0(n2501), .B1(
d_ff_Yn[53]), .Y(n1688) );
INVX2TS U2588 ( .A(n2568), .Y(n2542) );
CLKBUFX2TS U2589 ( .A(n2508), .Y(n2578) );
AO22XLTS U2590 ( .A0(n2542), .A1(result_add_subt[61]), .B0(n2578), .B1(
d_ff_Xn[61]), .Y(n1616) );
AO22XLTS U2591 ( .A0(n2500), .A1(result_add_subt[56]), .B0(n2501), .B1(
d_ff_Yn[56]), .Y(n1685) );
AO22XLTS U2592 ( .A0(n2542), .A1(result_add_subt[60]), .B0(n2578), .B1(
d_ff_Xn[60]), .Y(n1617) );
AO22XLTS U2593 ( .A0(n2500), .A1(result_add_subt[58]), .B0(n2501), .B1(
d_ff_Yn[58]), .Y(n1683) );
AO22XLTS U2594 ( .A0(n2554), .A1(result_add_subt[59]), .B0(n2578), .B1(
d_ff_Xn[59]), .Y(n1618) );
AO22XLTS U2595 ( .A0(n2500), .A1(result_add_subt[55]), .B0(n2501), .B1(
d_ff_Yn[55]), .Y(n1686) );
AO22XLTS U2596 ( .A0(n2554), .A1(result_add_subt[58]), .B0(n2558), .B1(
d_ff_Xn[58]), .Y(n1619) );
AO22XLTS U2597 ( .A0(n2500), .A1(result_add_subt[54]), .B0(n2501), .B1(
d_ff_Yn[54]), .Y(n1687) );
AO22XLTS U2598 ( .A0(n2554), .A1(result_add_subt[56]), .B0(n2558), .B1(
d_ff_Xn[56]), .Y(n1621) );
AO22XLTS U2599 ( .A0(n2546), .A1(result_add_subt[60]), .B0(n2506), .B1(
d_ff_Yn[60]), .Y(n1681) );
INVX2TS U2600 ( .A(n2667), .Y(n2564) );
AO22XLTS U2601 ( .A0(n2564), .A1(d_ff_Yn[63]), .B0(d_ff2_Y[63]), .B1(n2563),
.Y(n1310) );
AO22XLTS U2602 ( .A0(n2500), .A1(result_add_subt[51]), .B0(n2501), .B1(
d_ff_Yn[51]), .Y(n1690) );
INVX2TS U2603 ( .A(n2664), .Y(n2543) );
AO22XLTS U2604 ( .A0(n2564), .A1(d_ff_Yn[51]), .B0(d_ff2_Y[51]), .B1(n2504),
.Y(n1334) );
AO22XLTS U2605 ( .A0(n2542), .A1(result_add_subt[62]), .B0(n2578), .B1(
d_ff_Xn[62]), .Y(n1615) );
AO22XLTS U2606 ( .A0(n2500), .A1(result_add_subt[50]), .B0(n2501), .B1(
d_ff_Yn[50]), .Y(n1691) );
AO22XLTS U2607 ( .A0(n2598), .A1(d_ff_Yn[50]), .B0(d_ff2_Y[50]), .B1(n2547),
.Y(n1336) );
AO22XLTS U2608 ( .A0(n2549), .A1(result_add_subt[1]), .B0(n2569), .B1(
d_ff_Xn[1]), .Y(n1676) );
AO22XLTS U2609 ( .A0(n2549), .A1(result_add_subt[2]), .B0(n2507), .B1(
d_ff_Xn[2]), .Y(n1675) );
INVX2TS U2610 ( .A(n2669), .Y(n2553) );
AO22XLTS U2611 ( .A0(n2553), .A1(d_ff_Yn[49]), .B0(d_ff2_Y[49]), .B1(n2158),
.Y(n1338) );
CLKBUFX2TS U2612 ( .A(n2506), .Y(n2520) );
INVX2TS U2613 ( .A(n2520), .Y(n2509) );
AO22XLTS U2614 ( .A0(n2509), .A1(result_add_subt[49]), .B0(n2501), .B1(
d_ff_Yn[49]), .Y(n1692) );
AO22XLTS U2615 ( .A0(n2549), .A1(result_add_subt[4]), .B0(n2507), .B1(
d_ff_Xn[4]), .Y(n1673) );
AO22XLTS U2616 ( .A0(n2553), .A1(d_ff_Yn[1]), .B0(d_ff2_Y[1]), .B1(n2158),
.Y(n1434) );
AO22XLTS U2617 ( .A0(n2519), .A1(d_ff_Yn[48]), .B0(d_ff2_Y[48]), .B1(n2543),
.Y(n1340) );
AO22XLTS U2618 ( .A0(n2549), .A1(result_add_subt[5]), .B0(n2507), .B1(
d_ff_Xn[5]), .Y(n1672) );
AO22XLTS U2619 ( .A0(n2509), .A1(result_add_subt[48]), .B0(n2506), .B1(
d_ff_Yn[48]), .Y(n1693) );
AO22XLTS U2620 ( .A0(n2503), .A1(result_add_subt[10]), .B0(n2502), .B1(
d_ff_Xn[10]), .Y(n1667) );
AO22XLTS U2621 ( .A0(n2525), .A1(d_ff_Yn[47]), .B0(d_ff2_Y[47]), .B1(n2139),
.Y(n1342) );
AO22XLTS U2622 ( .A0(n2503), .A1(result_add_subt[12]), .B0(n2502), .B1(
d_ff_Xn[12]), .Y(n1665) );
AO22XLTS U2623 ( .A0(n2519), .A1(d_ff_Yn[2]), .B0(d_ff2_Y[2]), .B1(n2543),
.Y(n1432) );
AO22XLTS U2624 ( .A0(n2146), .A1(d_ff_Yn[46]), .B0(d_ff2_Y[46]), .B1(n2158),
.Y(n1344) );
AO22XLTS U2625 ( .A0(n2503), .A1(result_add_subt[15]), .B0(n2502), .B1(
d_ff_Xn[15]), .Y(n1662) );
AO22XLTS U2626 ( .A0(n2509), .A1(result_add_subt[47]), .B0(n2506), .B1(
d_ff_Yn[47]), .Y(n1694) );
AO22XLTS U2627 ( .A0(n2503), .A1(result_add_subt[16]), .B0(n2502), .B1(
d_ff_Xn[16]), .Y(n1661) );
AO22XLTS U2628 ( .A0(n2556), .A1(d_ff_Yn[45]), .B0(d_ff2_Y[45]), .B1(n2504),
.Y(n1346) );
AO22XLTS U2629 ( .A0(n2503), .A1(result_add_subt[17]), .B0(n2502), .B1(
d_ff_Xn[17]), .Y(n1660) );
AO22XLTS U2630 ( .A0(n2509), .A1(result_add_subt[46]), .B0(n2530), .B1(
d_ff_Yn[46]), .Y(n1695) );
INVX2TS U2631 ( .A(n2021), .Y(n2552) );
AO22XLTS U2632 ( .A0(n2553), .A1(d_ff_Yn[44]), .B0(d_ff2_Y[44]), .B1(n2552),
.Y(n1348) );
AO22XLTS U2633 ( .A0(n2503), .A1(result_add_subt[18]), .B0(n2502), .B1(
d_ff_Xn[18]), .Y(n1659) );
INVX2TS U2634 ( .A(n2669), .Y(n2519) );
AO22XLTS U2635 ( .A0(n2553), .A1(d_ff_Yn[3]), .B0(d_ff2_Y[3]), .B1(n2139),
.Y(n1430) );
AO22XLTS U2636 ( .A0(n2526), .A1(result_add_subt[20]), .B0(n2505), .B1(
d_ff_Xn[20]), .Y(n1657) );
INVX2TS U2637 ( .A(n2664), .Y(n2510) );
AO22XLTS U2638 ( .A0(n2525), .A1(d_ff_Yn[43]), .B0(d_ff2_Y[43]), .B1(n2510),
.Y(n1350) );
AO22XLTS U2639 ( .A0(n2509), .A1(result_add_subt[45]), .B0(n2520), .B1(
d_ff_Yn[45]), .Y(n1696) );
AO22XLTS U2640 ( .A0(n2526), .A1(result_add_subt[21]), .B0(n2505), .B1(
d_ff_Xn[21]), .Y(n1656) );
AO22XLTS U2641 ( .A0(n2511), .A1(d_ff_Yn[42]), .B0(d_ff2_Y[42]), .B1(n2510),
.Y(n1352) );
AO22XLTS U2642 ( .A0(n2526), .A1(result_add_subt[22]), .B0(n2505), .B1(
d_ff_Xn[22]), .Y(n1655) );
INVX2TS U2643 ( .A(n2663), .Y(n2516) );
AO22XLTS U2644 ( .A0(n2556), .A1(d_ff_Yn[4]), .B0(d_ff2_Y[4]), .B1(n2516),
.Y(n1428) );
AO22XLTS U2645 ( .A0(n2509), .A1(result_add_subt[44]), .B0(n2513), .B1(
d_ff_Yn[44]), .Y(n1697) );
AO22XLTS U2646 ( .A0(n2526), .A1(result_add_subt[23]), .B0(n2505), .B1(
d_ff_Xn[23]), .Y(n1654) );
AO22XLTS U2647 ( .A0(n2523), .A1(d_ff_Yn[41]), .B0(d_ff2_Y[41]), .B1(n2510),
.Y(n1354) );
AO22XLTS U2648 ( .A0(n2526), .A1(result_add_subt[25]), .B0(n2505), .B1(
d_ff_Xn[25]), .Y(n1652) );
AO22XLTS U2649 ( .A0(n2511), .A1(d_ff_Yn[40]), .B0(d_ff2_Y[40]), .B1(n2510),
.Y(n1356) );
AO22XLTS U2650 ( .A0(n2526), .A1(result_add_subt[27]), .B0(n2505), .B1(
d_ff_Xn[27]), .Y(n1650) );
AO22XLTS U2651 ( .A0(n2509), .A1(result_add_subt[43]), .B0(n2506), .B1(
d_ff_Yn[43]), .Y(n1698) );
AO22XLTS U2652 ( .A0(n2519), .A1(d_ff_Yn[5]), .B0(d_ff2_Y[5]), .B1(n2516),
.Y(n1426) );
INVX2TS U2653 ( .A(n2507), .Y(n2592) );
CLKBUFX3TS U2654 ( .A(n2508), .Y(n2591) );
AO22XLTS U2655 ( .A0(n2592), .A1(result_add_subt[30]), .B0(n2591), .B1(
d_ff_Xn[30]), .Y(n1647) );
AO22XLTS U2656 ( .A0(n2511), .A1(d_ff_Yn[39]), .B0(d_ff2_Y[39]), .B1(n2510),
.Y(n1358) );
AO22XLTS U2657 ( .A0(n2592), .A1(result_add_subt[33]), .B0(n2591), .B1(
d_ff_Xn[33]), .Y(n1644) );
AO22XLTS U2658 ( .A0(n2509), .A1(result_add_subt[42]), .B0(n2530), .B1(
d_ff_Yn[42]), .Y(n1699) );
AO22XLTS U2659 ( .A0(n2511), .A1(d_ff_Yn[38]), .B0(d_ff2_Y[38]), .B1(n2510),
.Y(n1360) );
AO22XLTS U2660 ( .A0(n2592), .A1(result_add_subt[37]), .B0(n2591), .B1(
d_ff_Xn[37]), .Y(n1640) );
AO22XLTS U2661 ( .A0(n2146), .A1(d_ff_Yn[6]), .B0(d_ff2_Y[6]), .B1(n2516),
.Y(n1424) );
AO22XLTS U2662 ( .A0(n2592), .A1(result_add_subt[38]), .B0(n2591), .B1(
d_ff_Xn[38]), .Y(n1639) );
AO22XLTS U2663 ( .A0(n2511), .A1(d_ff_Yn[37]), .B0(d_ff2_Y[37]), .B1(n2510),
.Y(n1362) );
AO22XLTS U2664 ( .A0(n2509), .A1(result_add_subt[41]), .B0(n2520), .B1(
d_ff_Yn[41]), .Y(n1700) );
INVX2TS U2665 ( .A(n2569), .Y(n2570) );
AO22XLTS U2666 ( .A0(n2570), .A1(result_add_subt[40]), .B0(n2508), .B1(
d_ff_Xn[40]), .Y(n1637) );
AO22XLTS U2667 ( .A0(n2511), .A1(d_ff_Yn[36]), .B0(d_ff2_Y[36]), .B1(n2510),
.Y(n1364) );
AO22XLTS U2668 ( .A0(n2570), .A1(result_add_subt[44]), .B0(n2578), .B1(
d_ff_Xn[44]), .Y(n1633) );
AO22XLTS U2669 ( .A0(n2509), .A1(result_add_subt[40]), .B0(n2513), .B1(
d_ff_Yn[40]), .Y(n1701) );
AO22XLTS U2670 ( .A0(n2570), .A1(result_add_subt[47]), .B0(n2565), .B1(
d_ff_Xn[47]), .Y(n1630) );
AO22XLTS U2671 ( .A0(n2511), .A1(d_ff_Yn[35]), .B0(d_ff2_Y[35]), .B1(n2510),
.Y(n1366) );
AO22XLTS U2672 ( .A0(n2525), .A1(d_ff_Yn[7]), .B0(d_ff2_Y[7]), .B1(n2516),
.Y(n1422) );
AO22XLTS U2673 ( .A0(n2554), .A1(result_add_subt[50]), .B0(n2558), .B1(
d_ff_Xn[50]), .Y(n1627) );
AO22XLTS U2674 ( .A0(n2511), .A1(d_ff_Yn[34]), .B0(d_ff2_Y[34]), .B1(n2510),
.Y(n1368) );
AO22XLTS U2675 ( .A0(n2554), .A1(result_add_subt[51]), .B0(n2558), .B1(
d_ff_Xn[51]), .Y(n1626) );
INVX2TS U2676 ( .A(n2512), .Y(n2521) );
AO22XLTS U2677 ( .A0(n2521), .A1(result_add_subt[39]), .B0(n2512), .B1(
d_ff_Yn[39]), .Y(n1702) );
INVX2TS U2678 ( .A(n2530), .Y(n2531) );
AO22XLTS U2679 ( .A0(n2531), .A1(result_add_subt[1]), .B0(n2520), .B1(
d_ff_Yn[1]), .Y(n1740) );
INVX2TS U2680 ( .A(n2670), .Y(n2514) );
AO22XLTS U2681 ( .A0(n2519), .A1(d_ff_Yn[33]), .B0(d_ff2_Y[33]), .B1(n2514),
.Y(n1370) );
AO22XLTS U2682 ( .A0(n2556), .A1(d_ff_Yn[8]), .B0(d_ff2_Y[8]), .B1(n2516),
.Y(n1420) );
AO22XLTS U2683 ( .A0(n2531), .A1(result_add_subt[2]), .B0(n2512), .B1(
d_ff_Yn[2]), .Y(n1739) );
CLKBUFX3TS U2684 ( .A(n2513), .Y(n2522) );
AO22XLTS U2685 ( .A0(n2521), .A1(result_add_subt[38]), .B0(n2522), .B1(
d_ff_Yn[38]), .Y(n1703) );
AO22XLTS U2686 ( .A0(n2511), .A1(d_ff_Yn[32]), .B0(d_ff2_Y[32]), .B1(n2514),
.Y(n1372) );
AO22XLTS U2687 ( .A0(n2531), .A1(result_add_subt[3]), .B0(n2512), .B1(
d_ff_Yn[3]), .Y(n1738) );
AO22XLTS U2688 ( .A0(n2531), .A1(result_add_subt[4]), .B0(n2512), .B1(
d_ff_Yn[4]), .Y(n1737) );
AO22XLTS U2689 ( .A0(n2525), .A1(d_ff_Yn[31]), .B0(d_ff2_Y[31]), .B1(n2514),
.Y(n1374) );
AO22XLTS U2690 ( .A0(n2521), .A1(result_add_subt[37]), .B0(n2522), .B1(
d_ff_Yn[37]), .Y(n1704) );
AO22XLTS U2691 ( .A0(n2531), .A1(result_add_subt[5]), .B0(n2512), .B1(
d_ff_Yn[5]), .Y(n1736) );
AO22XLTS U2692 ( .A0(n2146), .A1(d_ff_Yn[9]), .B0(d_ff2_Y[9]), .B1(n2516),
.Y(n1418) );
AO22XLTS U2693 ( .A0(n2553), .A1(d_ff_Yn[30]), .B0(d_ff2_Y[30]), .B1(n2514),
.Y(n1376) );
AO22XLTS U2694 ( .A0(n2531), .A1(result_add_subt[6]), .B0(n2512), .B1(
d_ff_Yn[6]), .Y(n1735) );
AO22XLTS U2695 ( .A0(n2521), .A1(result_add_subt[36]), .B0(n2522), .B1(
d_ff_Yn[36]), .Y(n1705) );
AO22XLTS U2696 ( .A0(n2531), .A1(result_add_subt[7]), .B0(n2512), .B1(
d_ff_Yn[7]), .Y(n1734) );
AO22XLTS U2697 ( .A0(n2519), .A1(d_ff_Yn[29]), .B0(d_ff2_Y[29]), .B1(n2514),
.Y(n1378) );
AO22XLTS U2698 ( .A0(n2531), .A1(result_add_subt[8]), .B0(n2512), .B1(
d_ff_Yn[8]), .Y(n1733) );
AO22XLTS U2699 ( .A0(n2553), .A1(d_ff_Yn[10]), .B0(d_ff2_Y[10]), .B1(n2516),
.Y(n1416) );
AO22XLTS U2700 ( .A0(n2525), .A1(d_ff_Yn[28]), .B0(d_ff2_Y[28]), .B1(n2514),
.Y(n1380) );
CLKBUFX3TS U2701 ( .A(n2513), .Y(n2515) );
AO22XLTS U2702 ( .A0(n2531), .A1(result_add_subt[9]), .B0(n2515), .B1(
d_ff_Yn[9]), .Y(n1732) );
AO22XLTS U2703 ( .A0(n2521), .A1(result_add_subt[35]), .B0(n2522), .B1(
d_ff_Yn[35]), .Y(n1706) );
INVX2TS U2704 ( .A(n2520), .Y(n2518) );
AO22XLTS U2705 ( .A0(n2518), .A1(result_add_subt[10]), .B0(n2515), .B1(
d_ff_Yn[10]), .Y(n1731) );
AO22XLTS U2706 ( .A0(n2146), .A1(d_ff_Yn[27]), .B0(d_ff2_Y[27]), .B1(n2514),
.Y(n1382) );
AO22XLTS U2707 ( .A0(n2518), .A1(result_add_subt[11]), .B0(n2515), .B1(
d_ff_Yn[11]), .Y(n1730) );
AO22XLTS U2708 ( .A0(n2521), .A1(result_add_subt[34]), .B0(n2522), .B1(
d_ff_Yn[34]), .Y(n1707) );
AO22XLTS U2709 ( .A0(n2519), .A1(d_ff_Yn[26]), .B0(d_ff2_Y[26]), .B1(n2514),
.Y(n1384) );
AO22XLTS U2710 ( .A0(n2518), .A1(result_add_subt[12]), .B0(n2515), .B1(
d_ff_Yn[12]), .Y(n1729) );
AO22XLTS U2711 ( .A0(n2556), .A1(d_ff_Yn[11]), .B0(d_ff2_Y[11]), .B1(n2516),
.Y(n1414) );
AO22XLTS U2712 ( .A0(n2518), .A1(result_add_subt[13]), .B0(n2515), .B1(
d_ff_Yn[13]), .Y(n1728) );
AO22XLTS U2713 ( .A0(n2553), .A1(d_ff_Yn[25]), .B0(d_ff2_Y[25]), .B1(n2514),
.Y(n1386) );
AO22XLTS U2714 ( .A0(n2521), .A1(result_add_subt[33]), .B0(n2522), .B1(
d_ff_Yn[33]), .Y(n1708) );
AO22XLTS U2715 ( .A0(n2518), .A1(result_add_subt[14]), .B0(n2515), .B1(
d_ff_Yn[14]), .Y(n1727) );
AO22XLTS U2716 ( .A0(n2525), .A1(d_ff_Yn[24]), .B0(d_ff2_Y[24]), .B1(n2514),
.Y(n1388) );
AO22XLTS U2717 ( .A0(n2518), .A1(result_add_subt[15]), .B0(n2515), .B1(
d_ff_Yn[15]), .Y(n1726) );
AO22XLTS U2718 ( .A0(n2519), .A1(d_ff_Yn[12]), .B0(d_ff2_Y[12]), .B1(n2516),
.Y(n1412) );
AO22XLTS U2719 ( .A0(n2521), .A1(result_add_subt[32]), .B0(n2522), .B1(
d_ff_Yn[32]), .Y(n1709) );
AO22XLTS U2720 ( .A0(n2518), .A1(result_add_subt[16]), .B0(n2515), .B1(
d_ff_Yn[16]), .Y(n1725) );
AO22XLTS U2721 ( .A0(n2525), .A1(d_ff_Yn[23]), .B0(d_ff2_Y[23]), .B1(n2524),
.Y(n1390) );
AO22XLTS U2722 ( .A0(n2518), .A1(result_add_subt[17]), .B0(n2515), .B1(
d_ff_Yn[17]), .Y(n1724) );
AO22XLTS U2723 ( .A0(n2556), .A1(d_ff_Yn[22]), .B0(d_ff2_Y[22]), .B1(n2524),
.Y(n1392) );
AO22XLTS U2724 ( .A0(n2518), .A1(result_add_subt[18]), .B0(n2515), .B1(
d_ff_Yn[18]), .Y(n1723) );
AO22XLTS U2725 ( .A0(n2521), .A1(result_add_subt[31]), .B0(n2522), .B1(
d_ff_Yn[31]), .Y(n1710) );
AO22XLTS U2726 ( .A0(n2523), .A1(d_ff_Yn[13]), .B0(d_ff2_Y[13]), .B1(n2516),
.Y(n1410) );
CLKBUFX3TS U2727 ( .A(n2517), .Y(n2571) );
AO22XLTS U2728 ( .A0(n2518), .A1(result_add_subt[19]), .B0(n2571), .B1(
d_ff_Yn[19]), .Y(n1722) );
AO22XLTS U2729 ( .A0(n2146), .A1(d_ff_Yn[21]), .B0(d_ff2_Y[21]), .B1(n2524),
.Y(n1394) );
INVX2TS U2730 ( .A(n2520), .Y(n2572) );
AO22XLTS U2731 ( .A0(n2572), .A1(result_add_subt[20]), .B0(n2571), .B1(
d_ff_Yn[20]), .Y(n1721) );
AO22XLTS U2732 ( .A0(n2521), .A1(result_add_subt[30]), .B0(n2522), .B1(
d_ff_Yn[30]), .Y(n1711) );
AO22XLTS U2733 ( .A0(n2572), .A1(result_add_subt[21]), .B0(n2571), .B1(
d_ff_Yn[21]), .Y(n1720) );
AO22XLTS U2734 ( .A0(n2556), .A1(d_ff_Yn[14]), .B0(d_ff2_Y[14]), .B1(n2524),
.Y(n1408) );
AO22XLTS U2735 ( .A0(n2523), .A1(d_ff_Yn[19]), .B0(d_ff2_Y[19]), .B1(n2524),
.Y(n1398) );
AO22XLTS U2736 ( .A0(n2572), .A1(result_add_subt[22]), .B0(n2571), .B1(
d_ff_Yn[22]), .Y(n1719) );
AO22XLTS U2737 ( .A0(n2572), .A1(result_add_subt[29]), .B0(n2522), .B1(
d_ff_Yn[29]), .Y(n1712) );
AO22XLTS U2738 ( .A0(n2572), .A1(result_add_subt[23]), .B0(n2571), .B1(
d_ff_Yn[23]), .Y(n1718) );
AO22XLTS U2739 ( .A0(n2523), .A1(d_ff_Yn[18]), .B0(d_ff2_Y[18]), .B1(n2524),
.Y(n1400) );
AO22XLTS U2740 ( .A0(n2572), .A1(result_add_subt[24]), .B0(n2571), .B1(
d_ff_Yn[24]), .Y(n1717) );
AO22XLTS U2741 ( .A0(n2572), .A1(result_add_subt[28]), .B0(n2571), .B1(
d_ff_Yn[28]), .Y(n1713) );
AO22XLTS U2742 ( .A0(n2523), .A1(d_ff_Yn[17]), .B0(d_ff2_Y[17]), .B1(n2524),
.Y(n1402) );
AO22XLTS U2743 ( .A0(n2572), .A1(result_add_subt[25]), .B0(n2571), .B1(
d_ff_Yn[25]), .Y(n1716) );
AO22XLTS U2744 ( .A0(n2523), .A1(d_ff_Yn[15]), .B0(d_ff2_Y[15]), .B1(n2524),
.Y(n1406) );
AO22XLTS U2745 ( .A0(n2572), .A1(result_add_subt[26]), .B0(n2571), .B1(
d_ff_Yn[26]), .Y(n1715) );
AO22XLTS U2746 ( .A0(n2146), .A1(d_ff_Yn[16]), .B0(d_ff2_Y[16]), .B1(n2524),
.Y(n1404) );
AO22XLTS U2747 ( .A0(n2526), .A1(result_add_subt[29]), .B0(n2591), .B1(
d_ff_Xn[29]), .Y(n1648) );
AO22XLTS U2748 ( .A0(n2528), .A1(d_ff2_Y[41]), .B0(n2527), .B1(
d_ff3_sh_y_out[41]), .Y(n1353) );
AO22XLTS U2749 ( .A0(n2528), .A1(d_ff2_Y[40]), .B0(n2527), .B1(
d_ff3_sh_y_out[40]), .Y(n1355) );
AO22XLTS U2750 ( .A0(n2562), .A1(d_ff_Xn[51]), .B0(d_ff2_X[51]), .B1(n2504),
.Y(n1206) );
AO22XLTS U2751 ( .A0(n2528), .A1(d_ff2_Y[42]), .B0(n2527), .B1(
d_ff3_sh_y_out[42]), .Y(n1351) );
AO22XLTS U2752 ( .A0(n2598), .A1(d_ff_Xn[63]), .B0(d_ff2_X[63]), .B1(n2547),
.Y(n1182) );
AO22XLTS U2753 ( .A0(n2528), .A1(d_ff2_Y[43]), .B0(n2527), .B1(
d_ff3_sh_y_out[43]), .Y(n1349) );
AO22XLTS U2754 ( .A0(n2528), .A1(d_ff2_Y[44]), .B0(n2527), .B1(
d_ff3_sh_y_out[44]), .Y(n1347) );
AO22XLTS U2755 ( .A0(n2562), .A1(d_ff_Xn[50]), .B0(d_ff2_X[50]), .B1(n2547),
.Y(n1208) );
AO22XLTS U2756 ( .A0(n2528), .A1(d_ff2_Y[38]), .B0(n2527), .B1(
d_ff3_sh_y_out[38]), .Y(n1359) );
AO22XLTS U2757 ( .A0(n2528), .A1(d_ff2_Y[45]), .B0(n2527), .B1(
d_ff3_sh_y_out[45]), .Y(n1345) );
AO22XLTS U2758 ( .A0(n2577), .A1(d_ff2_Y[46]), .B0(n2647), .B1(
d_ff3_sh_y_out[46]), .Y(n1343) );
AO22XLTS U2759 ( .A0(n2562), .A1(d_ff_Xn[47]), .B0(d_ff2_X[47]), .B1(n2552),
.Y(n1214) );
AO22XLTS U2760 ( .A0(n2577), .A1(d_ff2_Y[47]), .B0(n2527), .B1(
d_ff3_sh_y_out[47]), .Y(n1341) );
AO22XLTS U2761 ( .A0(n2528), .A1(d_ff2_Y[36]), .B0(n2527), .B1(
d_ff3_sh_y_out[36]), .Y(n1363) );
AO22XLTS U2762 ( .A0(n2577), .A1(d_ff2_Y[48]), .B0(n2529), .B1(
d_ff3_sh_y_out[48]), .Y(n1339) );
AO22XLTS U2763 ( .A0(n2564), .A1(d_ff_Yn[55]), .B0(d_ff2_Y[55]), .B1(n2563),
.Y(n1329) );
AO22XLTS U2764 ( .A0(n2562), .A1(d_ff_Xn[44]), .B0(d_ff2_X[44]), .B1(n2552),
.Y(n1220) );
AO22XLTS U2765 ( .A0(n2577), .A1(d_ff2_Y[49]), .B0(n2560), .B1(
d_ff3_sh_y_out[49]), .Y(n1337) );
AO22XLTS U2766 ( .A0(n2531), .A1(result_add_subt[0]), .B0(n2530), .B1(
d_ff_Yn[0]), .Y(n1741) );
AO22XLTS U2767 ( .A0(n2564), .A1(d_ff_Yn[54]), .B0(d_ff2_Y[54]), .B1(n2543),
.Y(n1330) );
AO22XLTS U2768 ( .A0(n2577), .A1(d_ff2_Y[50]), .B0(n2653), .B1(
d_ff3_sh_y_out[50]), .Y(n1335) );
AO22XLTS U2769 ( .A0(n2564), .A1(d_ff_Xn[40]), .B0(d_ff2_X[40]), .B1(n2552),
.Y(n1228) );
AO22XLTS U2770 ( .A0(n2577), .A1(d_ff2_Y[51]), .B0(n2575), .B1(
d_ff3_sh_y_out[51]), .Y(n1333) );
AO22XLTS U2771 ( .A0(n2551), .A1(d_ff2_Y[35]), .B0(n2550), .B1(
d_ff3_sh_y_out[35]), .Y(n1365) );
NOR2X1TS U2772 ( .A(d_ff2_Y[56]), .B(n2656), .Y(n2655) );
INVX2TS U2773 ( .A(n2655), .Y(n2533) );
AOI21X1TS U2774 ( .A0(d_ff2_Y[57]), .A1(n2533), .B0(n2532), .Y(n2534) );
AOI2BB2XLTS U2775 ( .B0(n2662), .B1(n2534), .A0N(d_ff3_sh_y_out[57]), .A1N(
n2584), .Y(n1316) );
AO22XLTS U2776 ( .A0(n2564), .A1(d_ff_Yn[59]), .B0(d_ff2_Y[59]), .B1(n2563),
.Y(n1325) );
AO22XLTS U2777 ( .A0(n2553), .A1(d_ff_Xn[38]), .B0(d_ff2_X[38]), .B1(n2552),
.Y(n1232) );
AO22XLTS U2778 ( .A0(n2551), .A1(d_ff2_Y[34]), .B0(n2550), .B1(
d_ff3_sh_y_out[34]), .Y(n1367) );
AOI21X1TS U2779 ( .A0(d_ff2_Y[59]), .A1(n2535), .B0(n2574), .Y(n2536) );
AOI2BB2XLTS U2780 ( .B0(n2662), .B1(n2536), .A0N(d_ff3_sh_y_out[59]), .A1N(
n2584), .Y(n1314) );
AO22XLTS U2781 ( .A0(n2564), .A1(d_ff_Yn[62]), .B0(d_ff2_Y[62]), .B1(n2563),
.Y(n1322) );
OAI21XLTS U2782 ( .A0(n2583), .A1(n2692), .B0(n2581), .Y(n2537) );
AO22XLTS U2783 ( .A0(n2596), .A1(n2537), .B0(n2594), .B1(d_ff3_sh_x_out[58]),
.Y(n1187) );
AO22XLTS U2784 ( .A0(n2519), .A1(d_ff_Xn[37]), .B0(d_ff2_X[37]), .B1(n2552),
.Y(n1234) );
AO22XLTS U2785 ( .A0(n2538), .A1(d_ff3_sign_out), .B0(n2584), .B1(
d_ff2_Z[63]), .Y(n1437) );
OAI21XLTS U2786 ( .A0(n2580), .A1(n2693), .B0(n2539), .Y(n2540) );
AO22XLTS U2787 ( .A0(n2644), .A1(n2540), .B0(n2594), .B1(d_ff3_sh_x_out[60]),
.Y(n1185) );
AO22XLTS U2788 ( .A0(n2551), .A1(d_ff2_Y[32]), .B0(n2550), .B1(
d_ff3_sh_y_out[32]), .Y(n1371) );
AO22XLTS U2789 ( .A0(n2541), .A1(d_ff2_X[4]), .B0(n2649), .B1(
d_ff3_sh_x_out[4]), .Y(n1299) );
AO22XLTS U2790 ( .A0(n2542), .A1(result_add_subt[63]), .B0(n2578), .B1(
d_ff_Xn[63]), .Y(n1614) );
AO22XLTS U2791 ( .A0(n2525), .A1(d_ff_Xn[33]), .B0(d_ff2_X[33]), .B1(n2139),
.Y(n1242) );
AO22XLTS U2792 ( .A0(n2545), .A1(d_ff2_X[12]), .B0(n2544), .B1(
d_ff3_sh_x_out[12]), .Y(n1283) );
AO22XLTS U2793 ( .A0(n2564), .A1(d_ff_Yn[61]), .B0(d_ff2_Y[61]), .B1(n2563),
.Y(n1323) );
AO22XLTS U2794 ( .A0(n2545), .A1(d_ff2_X[16]), .B0(n2544), .B1(
d_ff3_sh_x_out[16]), .Y(n1275) );
AO22XLTS U2795 ( .A0(n2551), .A1(d_ff2_Y[31]), .B0(n2550), .B1(
d_ff3_sh_y_out[31]), .Y(n1373) );
AO22XLTS U2796 ( .A0(n2146), .A1(d_ff_Xn[30]), .B0(d_ff2_X[30]), .B1(n2552),
.Y(n1248) );
AO22XLTS U2797 ( .A0(n2548), .A1(d_ff2_X[20]), .B0(n2575), .B1(
d_ff3_sh_x_out[20]), .Y(n1267) );
AO22XLTS U2798 ( .A0(n2546), .A1(result_add_subt[63]), .B0(n2512), .B1(
d_ff_Yn[63]), .Y(n1678) );
AO22XLTS U2799 ( .A0(n2548), .A1(d_ff2_X[22]), .B0(n2434), .B1(
d_ff3_sh_x_out[22]), .Y(n1263) );
AO22XLTS U2800 ( .A0(n2564), .A1(d_ff_Yn[57]), .B0(d_ff2_Y[57]), .B1(n2563),
.Y(n1327) );
INVX2TS U2801 ( .A(n2667), .Y(n2672) );
AO22XLTS U2802 ( .A0(d_ff2_X[62]), .A1(n2547), .B0(n2672), .B1(d_ff_Xn[62]),
.Y(n1194) );
AO22XLTS U2803 ( .A0(n2551), .A1(d_ff2_Y[30]), .B0(n2550), .B1(
d_ff3_sh_y_out[30]), .Y(n1375) );
AO22XLTS U2804 ( .A0(n2548), .A1(d_ff2_X[24]), .B0(n2430), .B1(
d_ff3_sh_x_out[24]), .Y(n1259) );
AO22XLTS U2805 ( .A0(n2562), .A1(d_ff_Xn[27]), .B0(d_ff2_X[27]), .B1(n2552),
.Y(n1254) );
AO22XLTS U2806 ( .A0(n2548), .A1(d_ff2_X[28]), .B0(n2557), .B1(
d_ff3_sh_x_out[28]), .Y(n1251) );
AO22XLTS U2807 ( .A0(n2549), .A1(result_add_subt[0]), .B0(n2568), .B1(
d_ff_Xn[0]), .Y(n1677) );
AO22XLTS U2808 ( .A0(n2559), .A1(d_ff2_X[30]), .B0(n2557), .B1(
d_ff3_sh_x_out[30]), .Y(n1247) );
AO22XLTS U2809 ( .A0(n2551), .A1(d_ff2_Y[28]), .B0(n2550), .B1(
d_ff3_sh_y_out[28]), .Y(n1379) );
AO22XLTS U2810 ( .A0(n2556), .A1(d_ff_Xn[25]), .B0(d_ff2_X[25]), .B1(n2552),
.Y(n1258) );
AO22XLTS U2811 ( .A0(n2554), .A1(result_add_subt[55]), .B0(n2558), .B1(
d_ff_Xn[55]), .Y(n1622) );
AO22XLTS U2812 ( .A0(n2559), .A1(d_ff2_X[31]), .B0(n2557), .B1(
d_ff3_sh_x_out[31]), .Y(n1245) );
AO22XLTS U2813 ( .A0(n2559), .A1(d_ff2_X[32]), .B0(n2557), .B1(
d_ff3_sh_x_out[32]), .Y(n1243) );
AO22XLTS U2814 ( .A0(n2554), .A1(result_add_subt[54]), .B0(n2558), .B1(
d_ff_Xn[54]), .Y(n1623) );
AO22XLTS U2815 ( .A0(n2561), .A1(d_ff2_Y[16]), .B0(n2647), .B1(
d_ff3_sh_y_out[16]), .Y(n1403) );
AO22XLTS U2816 ( .A0(n2562), .A1(d_ff_Xn[23]), .B0(d_ff2_X[23]), .B1(n2552),
.Y(n1262) );
AO22XLTS U2817 ( .A0(n2579), .A1(d_ff2_X[46]), .B0(n2566), .B1(
d_ff3_sh_x_out[46]), .Y(n1215) );
AO22XLTS U2818 ( .A0(n2559), .A1(d_ff2_X[34]), .B0(n2557), .B1(
d_ff3_sh_x_out[34]), .Y(n1239) );
AO22XLTS U2819 ( .A0(n2556), .A1(d_ff_Xn[17]), .B0(d_ff2_X[17]), .B1(n2597),
.Y(n1274) );
AO22XLTS U2820 ( .A0(n2554), .A1(result_add_subt[53]), .B0(n2558), .B1(
d_ff_Xn[53]), .Y(n1624) );
AO22XLTS U2821 ( .A0(n2579), .A1(d_ff2_X[35]), .B0(n2557), .B1(
d_ff3_sh_x_out[35]), .Y(n1237) );
NOR2XLTS U2822 ( .A(n2686), .B(n2567), .Y(n2555) );
XOR2XLTS U2823 ( .A(n2555), .B(cont_iter_out[3]), .Y(n1874) );
AO22XLTS U2824 ( .A0(n2561), .A1(d_ff2_Y[24]), .B0(n2529), .B1(
d_ff3_sh_y_out[24]), .Y(n1387) );
AO22XLTS U2825 ( .A0(n2146), .A1(d_ff_Xn[22]), .B0(d_ff2_X[22]), .B1(n2597),
.Y(n1264) );
AO22XLTS U2826 ( .A0(n2579), .A1(d_ff2_X[36]), .B0(n2557), .B1(
d_ff3_sh_x_out[36]), .Y(n1235) );
AO22XLTS U2827 ( .A0(n2570), .A1(result_add_subt[49]), .B0(n2558), .B1(
d_ff_Xn[49]), .Y(n1628) );
AO22XLTS U2828 ( .A0(n2561), .A1(d_ff2_Y[22]), .B0(n2560), .B1(
d_ff3_sh_y_out[22]), .Y(n1391) );
AO22XLTS U2829 ( .A0(n2579), .A1(d_ff2_X[38]), .B0(n2566), .B1(
d_ff3_sh_x_out[38]), .Y(n1231) );
AO22XLTS U2830 ( .A0(n2570), .A1(result_add_subt[48]), .B0(n2565), .B1(
d_ff_Xn[48]), .Y(n1629) );
AO22XLTS U2831 ( .A0(n2559), .A1(d_ff2_X[40]), .B0(n2566), .B1(
d_ff3_sh_x_out[40]), .Y(n1227) );
AO22XLTS U2832 ( .A0(n2596), .A1(d_ff2_X[50]), .B0(n2594), .B1(
d_ff3_sh_x_out[50]), .Y(n1207) );
AO22XLTS U2833 ( .A0(n2562), .A1(d_ff_Xn[21]), .B0(d_ff2_X[21]), .B1(n2597),
.Y(n1266) );
AO22XLTS U2834 ( .A0(n2596), .A1(d_ff2_X[51]), .B0(n2594), .B1(
d_ff3_sh_x_out[51]), .Y(n1205) );
AO22XLTS U2835 ( .A0(n2579), .A1(d_ff2_X[41]), .B0(n2566), .B1(
d_ff3_sh_x_out[41]), .Y(n1225) );
AO22XLTS U2836 ( .A0(n2570), .A1(result_add_subt[46]), .B0(n2568), .B1(
d_ff_Xn[46]), .Y(n1631) );
AO22XLTS U2837 ( .A0(n2592), .A1(result_add_subt[35]), .B0(n2591), .B1(
d_ff_Xn[35]), .Y(n1642) );
AO22XLTS U2838 ( .A0(n2561), .A1(d_ff2_Y[20]), .B0(n2647), .B1(
d_ff3_sh_y_out[20]), .Y(n1395) );
AO22XLTS U2839 ( .A0(n2579), .A1(d_ff2_X[42]), .B0(n2566), .B1(
d_ff3_sh_x_out[42]), .Y(n1223) );
AO22XLTS U2840 ( .A0(n2562), .A1(d_ff_Xn[20]), .B0(d_ff2_X[20]), .B1(n2597),
.Y(n1268) );
AO22XLTS U2841 ( .A0(n2570), .A1(result_add_subt[45]), .B0(n2569), .B1(
d_ff_Xn[45]), .Y(n1632) );
AO22XLTS U2842 ( .A0(n2579), .A1(d_ff2_X[43]), .B0(n2566), .B1(
d_ff3_sh_x_out[43]), .Y(n1221) );
AO22XLTS U2843 ( .A0(n2564), .A1(d_ff_Yn[56]), .B0(d_ff2_Y[56]), .B1(n2563),
.Y(n1328) );
AO22XLTS U2844 ( .A0(n2598), .A1(d_ff_Xn[12]), .B0(d_ff2_X[12]), .B1(n2597),
.Y(n1284) );
AO22XLTS U2845 ( .A0(n2579), .A1(d_ff2_X[44]), .B0(n2566), .B1(
d_ff3_sh_x_out[44]), .Y(n1219) );
AO22XLTS U2846 ( .A0(n2570), .A1(result_add_subt[43]), .B0(n2565), .B1(
d_ff_Xn[43]), .Y(n1634) );
AO22XLTS U2847 ( .A0(n2598), .A1(d_ff_Xn[18]), .B0(d_ff2_X[18]), .B1(n2597),
.Y(n1272) );
AO22XLTS U2848 ( .A0(n2596), .A1(d_ff2_X[45]), .B0(n2566), .B1(
d_ff3_sh_x_out[45]), .Y(n1217) );
AOI2BB2XLTS U2849 ( .B0(n2567), .B1(n2686), .A0N(n2012), .A1N(n2567), .Y(
n1875) );
AO22XLTS U2850 ( .A0(n2570), .A1(result_add_subt[42]), .B0(n2568), .B1(
d_ff_Xn[42]), .Y(n1635) );
AO22XLTS U2851 ( .A0(n2596), .A1(d_ff2_X[48]), .B0(n2594), .B1(
d_ff3_sh_x_out[48]), .Y(n1211) );
AO22XLTS U2852 ( .A0(n2596), .A1(d_ff2_X[47]), .B0(n2594), .B1(
d_ff3_sh_x_out[47]), .Y(n1213) );
AO22XLTS U2853 ( .A0(n2570), .A1(result_add_subt[41]), .B0(n2569), .B1(
d_ff_Xn[41]), .Y(n1636) );
AO22XLTS U2854 ( .A0(n2598), .A1(d_ff_Xn[16]), .B0(d_ff2_X[16]), .B1(n2597),
.Y(n1276) );
AO22XLTS U2855 ( .A0(n2572), .A1(result_add_subt[27]), .B0(n2571), .B1(
d_ff_Yn[27]), .Y(n1714) );
AO22XLTS U2856 ( .A0(n2573), .A1(d_ff2_Y[12]), .B0(n2575), .B1(
d_ff3_sh_y_out[12]), .Y(n1411) );
OAI21XLTS U2857 ( .A0(n2574), .A1(n2695), .B0(n2660), .Y(n2576) );
AO22XLTS U2858 ( .A0(n2577), .A1(n2576), .B0(n2575), .B1(d_ff3_sh_y_out[60]),
.Y(n1313) );
AO22XLTS U2859 ( .A0(n2592), .A1(result_add_subt[39]), .B0(n2578), .B1(
d_ff_Xn[39]), .Y(n1638) );
AO22XLTS U2860 ( .A0(n2579), .A1(d_ff2_X[49]), .B0(n2594), .B1(
d_ff3_sh_x_out[49]), .Y(n1209) );
AO22XLTS U2861 ( .A0(n2598), .A1(d_ff_Xn[15]), .B0(d_ff2_X[15]), .B1(n2597),
.Y(n1278) );
AOI21X1TS U2862 ( .A0(d_ff2_X[59]), .A1(n2581), .B0(n2580), .Y(n2582) );
AOI2BB2XLTS U2863 ( .B0(n2662), .B1(n2582), .A0N(d_ff3_sh_x_out[59]), .A1N(
n2651), .Y(n1186) );
AO22XLTS U2864 ( .A0(n2592), .A1(result_add_subt[32]), .B0(n2591), .B1(
d_ff_Xn[32]), .Y(n1645) );
AO22XLTS U2865 ( .A0(n2592), .A1(result_add_subt[36]), .B0(n2591), .B1(
d_ff_Xn[36]), .Y(n1641) );
AO22XLTS U2866 ( .A0(n2584), .A1(d_ff2_Y[4]), .B0(n2529), .B1(
d_ff3_sh_y_out[4]), .Y(n1427) );
AO22XLTS U2867 ( .A0(n2592), .A1(result_add_subt[31]), .B0(n2591), .B1(
d_ff_Xn[31]), .Y(n1646) );
NOR2X1TS U2868 ( .A(d_ff2_X[56]), .B(n2676), .Y(n2675) );
AOI2BB1XLTS U2869 ( .A0N(n2700), .A1N(n2675), .B0(n2583), .Y(n2585) );
AOI2BB2XLTS U2870 ( .B0(n2662), .B1(n2585), .A0N(d_ff3_sh_x_out[57]), .A1N(
n2584), .Y(n1188) );
XNOR2X1TS U2871 ( .A(n2586), .B(n2688), .Y(n2587) );
MXI2X1TS U2872 ( .A(n2589), .B(n2588), .S0(n2587), .Y(n2590) );
AO21XLTS U2873 ( .A0(d_ff3_sh_y_out[53]), .A1(n2560), .B0(n2590), .Y(n1320)
);
AO22XLTS U2874 ( .A0(n2592), .A1(result_add_subt[34]), .B0(n2591), .B1(
d_ff_Xn[34]), .Y(n1643) );
CMPR32X2TS U2875 ( .A(d_ff2_X[53]), .B(n2683), .C(n2593), .CO(n2463), .S(
n2595) );
AO22XLTS U2876 ( .A0(n2596), .A1(n2595), .B0(n2594), .B1(d_ff3_sh_x_out[53]),
.Y(n1192) );
AO22XLTS U2877 ( .A0(n2598), .A1(d_ff_Xn[10]), .B0(d_ff2_X[10]), .B1(n2597),
.Y(n1288) );
AO22XLTS U2878 ( .A0(n2599), .A1(d_ff3_sh_x_out[63]), .B0(n2361), .B1(
d_ff3_sh_y_out[63]), .Y(add_subt_dataB[63]) );
AO22XLTS U2879 ( .A0(d_ff3_sh_y_out[62]), .A1(n2317), .B0(d_ff3_sh_x_out[62]), .B1(n2600), .Y(add_subt_dataB[62]) );
AOI22X1TS U2880 ( .A0(n2630), .A1(d_ff3_sh_x_out[60]), .B0(n2620), .B1(
d_ff3_sh_y_out[60]), .Y(n2601) );
NAND2X1TS U2881 ( .A(n2601), .B(n2610), .Y(add_subt_dataB[60]) );
AOI22X1TS U2882 ( .A0(n2621), .A1(d_ff3_sh_x_out[59]), .B0(n2620), .B1(
d_ff3_sh_y_out[59]), .Y(n2602) );
NAND2X1TS U2883 ( .A(n2602), .B(n2610), .Y(add_subt_dataB[59]) );
AOI22X1TS U2884 ( .A0(n2621), .A1(d_ff3_sh_x_out[58]), .B0(n2620), .B1(
d_ff3_sh_y_out[58]), .Y(n2603) );
NAND2X1TS U2885 ( .A(n2603), .B(n2610), .Y(add_subt_dataB[58]) );
AOI22X1TS U2886 ( .A0(n2630), .A1(d_ff3_sh_x_out[57]), .B0(n2620), .B1(
d_ff3_sh_y_out[57]), .Y(n2604) );
NAND2X1TS U2887 ( .A(n2604), .B(n2610), .Y(add_subt_dataB[57]) );
OAI222X1TS U2888 ( .A0(n2701), .A1(n2032), .B0(n2680), .B1(n2606), .C0(n2682), .C1(n2605), .Y(add_subt_dataB[56]) );
AOI22X1TS U2889 ( .A0(n2621), .A1(d_ff3_sh_x_out[51]), .B0(n2620), .B1(
d_ff3_sh_y_out[51]), .Y(n2607) );
NAND2X1TS U2890 ( .A(n2607), .B(n2610), .Y(add_subt_dataB[51]) );
AOI22X1TS U2891 ( .A0(n2621), .A1(d_ff3_sh_x_out[49]), .B0(n2620), .B1(
d_ff3_sh_y_out[49]), .Y(n2609) );
NAND2X1TS U2892 ( .A(n2608), .B(d_ff3_LUT_out[44]), .Y(n2613) );
NAND2X1TS U2893 ( .A(n2609), .B(n2613), .Y(add_subt_dataB[49]) );
AOI22X1TS U2894 ( .A0(n2624), .A1(d_ff3_sh_x_out[48]), .B0(n2401), .B1(
d_ff3_sh_y_out[48]), .Y(n2611) );
NAND2X1TS U2895 ( .A(n2611), .B(n2610), .Y(add_subt_dataB[48]) );
AOI22X1TS U2896 ( .A0(n2624), .A1(d_ff3_sh_x_out[46]), .B0(n2623), .B1(
d_ff3_sh_y_out[46]), .Y(n2612) );
NAND2X1TS U2897 ( .A(n2612), .B(n2613), .Y(add_subt_dataB[46]) );
AOI22X1TS U2898 ( .A0(n2621), .A1(d_ff3_sh_x_out[44]), .B0(n2401), .B1(
d_ff3_sh_y_out[44]), .Y(n2614) );
NAND2X1TS U2899 ( .A(n2614), .B(n2613), .Y(add_subt_dataB[44]) );
AOI2BB2XLTS U2900 ( .B0(cont_var_out[0]), .B1(d_ff3_sign_out), .A0N(
d_ff3_sign_out), .A1N(cont_var_out[0]), .Y(op_add_subt) );
NOR2BX1TS U2901 ( .AN(beg_fsm_cordic), .B(n2615), .Y(
inst_CORDIC_FSM_v3_state_next[1]) );
OAI22X1TS U2902 ( .A0(n2619), .A1(n2618), .B0(n2617), .B1(n2032), .Y(
inst_CORDIC_FSM_v3_state_next[5]) );
AOI22X1TS U2903 ( .A0(n2409), .A1(d_ff3_sh_x_out[47]), .B0(n2620), .B1(
d_ff3_sh_y_out[47]), .Y(n2622) );
OAI2BB1X1TS U2904 ( .A0N(n2626), .A1N(d_ff3_LUT_out[42]), .B0(n2622), .Y(
add_subt_dataB[47]) );
AOI22X1TS U2905 ( .A0(n2624), .A1(d_ff3_sh_x_out[42]), .B0(n2623), .B1(
d_ff3_sh_y_out[42]), .Y(n2625) );
OAI2BB1X1TS U2906 ( .A0N(n2626), .A1N(d_ff3_LUT_out[42]), .B0(n2625), .Y(
add_subt_dataB[42]) );
INVX2TS U2907 ( .A(n2627), .Y(n2632) );
AOI22X1TS U2908 ( .A0(d_ff2_Y[62]), .A1(n2634), .B0(d_ff2_Z[62]), .B1(n2633),
.Y(n2628) );
OAI2BB1X1TS U2909 ( .A0N(d_ff2_X[62]), .A1N(n2632), .B0(n2628), .Y(
add_subt_dataA[62]) );
AOI22X1TS U2910 ( .A0(d_ff2_Y[61]), .A1(n2409), .B0(d_ff2_Z[61]), .B1(n2633),
.Y(n2629) );
OAI2BB1X1TS U2911 ( .A0N(d_ff2_X[61]), .A1N(n2333), .B0(n2629), .Y(
add_subt_dataA[61]) );
AOI22X1TS U2912 ( .A0(d_ff2_Y[59]), .A1(n2630), .B0(d_ff2_Z[59]), .B1(n2633),
.Y(n2631) );
OAI2BB1X1TS U2913 ( .A0N(d_ff2_X[59]), .A1N(n2344), .B0(n2631), .Y(
add_subt_dataA[59]) );
AOI22X1TS U2914 ( .A0(d_ff2_Y[56]), .A1(n2634), .B0(d_ff2_Z[56]), .B1(n2633),
.Y(n2635) );
OAI2BB1X1TS U2915 ( .A0N(d_ff2_X[56]), .A1N(n2636), .B0(n2635), .Y(
add_subt_dataA[56]) );
AOI21X1TS U2916 ( .A0(n2638), .A1(n2009), .B0(n2637), .Y(n1877) );
OAI2BB2XLTS U2917 ( .B0(n2640), .B1(n2705), .A0N(n2639), .A1N(operation),
.Y(n1872) );
OAI2BB2XLTS U2918 ( .B0(n2640), .B1(n2684), .A0N(n2433), .A1N(
shift_region_flag[0]), .Y(n1871) );
OAI2BB2XLTS U2919 ( .B0(n2640), .B1(n2681), .A0N(n2639), .A1N(
shift_region_flag[1]), .Y(n1870) );
OAI21XLTS U2920 ( .A0(n2662), .A1(d_ff3_LUT_out[13]), .B0(n2645), .Y(n2641)
);
OAI2BB1X1TS U2921 ( .A0N(n2643), .A1N(n2642), .B0(n2641), .Y(n1536) );
OA22X1TS U2922 ( .A0(n2646), .A1(n2645), .B0(n2644), .B1(d_ff3_LUT_out[21]),
.Y(n1528) );
OAI2BB2XLTS U2923 ( .B0(n2649), .B1(n2648), .A0N(n2529), .A1N(
d_ff3_LUT_out[42]), .Y(n1511) );
OAI2BB1X1TS U2924 ( .A0N(d_ff3_LUT_out[44]), .A1N(n2653), .B0(n2650), .Y(
n1510) );
OR2X1TS U2925 ( .A(d_ff3_LUT_out[48]), .B(n2651), .Y(n1508) );
OAI2BB1X1TS U2926 ( .A0N(d_ff3_LUT_out[52]), .A1N(n2653), .B0(n2652), .Y(
n1506) );
AOI22X1TS U2927 ( .A0(n2679), .A1(n2654), .B0(n2701), .B1(n2677), .Y(n1502)
);
OAI2BB2XLTS U2928 ( .B0(n2704), .B1(n2663), .A0N(n2672), .A1N(d_ff_Yn[52]),
.Y(n1332) );
OAI2BB2XLTS U2929 ( .B0(n2688), .B1(n2664), .A0N(n2672), .A1N(d_ff_Yn[53]),
.Y(n1331) );
OAI2BB2XLTS U2930 ( .B0(n2694), .B1(n2670), .A0N(n2672), .A1N(d_ff_Yn[58]),
.Y(n1326) );
OAI2BB2XLTS U2931 ( .B0(n2695), .B1(n2021), .A0N(n2672), .A1N(d_ff_Yn[60]),
.Y(n1324) );
AOI21X1TS U2932 ( .A0(n2656), .A1(d_ff2_Y[56]), .B0(n2655), .Y(n2658) );
AOI22X1TS U2933 ( .A0(n2662), .A1(n2658), .B0(n2682), .B1(n2538), .Y(n1317)
);
AOI21X1TS U2934 ( .A0(d_ff2_Y[61]), .A1(n2660), .B0(n2659), .Y(n2661) );
AOI22X1TS U2935 ( .A0(n2662), .A1(n2661), .B0(n2702), .B1(n2677), .Y(n1312)
);
OA22X1TS U2936 ( .A0(d_ff_Xn[3]), .A1(n2673), .B0(n2717), .B1(d_ff2_X[3]),
.Y(n1302) );
OA22X1TS U2937 ( .A0(d_ff_Xn[6]), .A1(n2665), .B0(n2717), .B1(d_ff2_X[6]),
.Y(n1296) );
OA22X1TS U2938 ( .A0(d_ff_Xn[7]), .A1(n2666), .B0(n2021), .B1(d_ff2_X[7]),
.Y(n1294) );
OA22X1TS U2939 ( .A0(d_ff_Xn[8]), .A1(n2673), .B0(n2664), .B1(d_ff2_X[8]),
.Y(n1292) );
OA22X1TS U2940 ( .A0(d_ff_Xn[9]), .A1(n2665), .B0(n2663), .B1(d_ff2_X[9]),
.Y(n1290) );
OA22X1TS U2941 ( .A0(d_ff_Xn[11]), .A1(n2666), .B0(n2670), .B1(d_ff2_X[11]),
.Y(n1286) );
OA22X1TS U2942 ( .A0(d_ff_Xn[13]), .A1(n2673), .B0(n2717), .B1(d_ff2_X[13]),
.Y(n1282) );
OA22X1TS U2943 ( .A0(d_ff_Xn[14]), .A1(n2665), .B0(n2670), .B1(d_ff2_X[14]),
.Y(n1280) );
OA22X1TS U2944 ( .A0(d_ff_Xn[24]), .A1(n2671), .B0(n2717), .B1(d_ff2_X[24]),
.Y(n1260) );
OA22X1TS U2945 ( .A0(d_ff_Xn[26]), .A1(n2666), .B0(n2663), .B1(d_ff2_X[26]),
.Y(n1256) );
OA22X1TS U2946 ( .A0(d_ff_Xn[28]), .A1(n2666), .B0(n2664), .B1(d_ff2_X[28]),
.Y(n1252) );
OA22X1TS U2947 ( .A0(d_ff_Xn[29]), .A1(n2667), .B0(n2670), .B1(d_ff2_X[29]),
.Y(n1250) );
OA22X1TS U2948 ( .A0(d_ff_Xn[32]), .A1(n2673), .B0(n2674), .B1(d_ff2_X[32]),
.Y(n1244) );
OA22X1TS U2949 ( .A0(d_ff_Xn[34]), .A1(n2671), .B0(n2663), .B1(d_ff2_X[34]),
.Y(n1240) );
OA22X1TS U2950 ( .A0(d_ff_Xn[35]), .A1(n2668), .B0(n2717), .B1(d_ff2_X[35]),
.Y(n1238) );
OA22X1TS U2951 ( .A0(d_ff_Xn[36]), .A1(n2673), .B0(n2717), .B1(d_ff2_X[36]),
.Y(n1236) );
OA22X1TS U2952 ( .A0(d_ff_Xn[39]), .A1(n2671), .B0(n2664), .B1(d_ff2_X[39]),
.Y(n1230) );
OAI2BB2XLTS U2953 ( .B0(n2690), .B1(n2663), .A0N(n2672), .A1N(d_ff_Xn[52]),
.Y(n1204) );
OA22X1TS U2954 ( .A0(n2674), .A1(d_ff2_X[56]), .B0(d_ff_Xn[56]), .B1(n2665),
.Y(n1200) );
AOI21X1TS U2955 ( .A0(n2676), .A1(d_ff2_X[56]), .B0(n2675), .Y(n2678) );
AOI22X1TS U2956 ( .A0(n2679), .A1(n2678), .B0(n2680), .B1(n2677), .Y(n1189)
);
initial $sdf_annotate("CORDIC_Arch3v1_ASIC_fpu_syn_constraints_noclk.tcl_syn.sdf");
endmodule
|
module reg_grp #(parameter
REG_ADDR_BITS = 10,
NUM_OUTPUTS = 4
)
(
// Upstream register interface
input reg_req,
input reg_rd_wr_L,
input [REG_ADDR_BITS -1:0] reg_addr,
input [`CPCI_NF2_DATA_WIDTH -1:0] reg_wr_data,
output reg reg_ack,
output reg [`CPCI_NF2_DATA_WIDTH -1:0] reg_rd_data,
// Downstream register interface
output [NUM_OUTPUTS - 1 : 0] local_reg_req,
output [NUM_OUTPUTS - 1 : 0] local_reg_rd_wr_L,
output [NUM_OUTPUTS * (REG_ADDR_BITS - log2(NUM_OUTPUTS)) -1:0] local_reg_addr,
output [NUM_OUTPUTS * `CPCI_NF2_DATA_WIDTH -1:0] local_reg_wr_data,
input [NUM_OUTPUTS - 1 : 0] local_reg_ack,
input [NUM_OUTPUTS * `CPCI_NF2_DATA_WIDTH -1:0] local_reg_rd_data,
//-- misc
input clk,
input reset
);
// Log base 2 function
//
// Returns ceil(log2(X))
function integer log2;
input integer number;
begin
log2=0;
while(2**log2<number) begin
log2=log2+1;
end
end
endfunction // log2
// Register addresses
localparam SWITCH_ADDR_BITS = log2(NUM_OUTPUTS);
// ===========================================
// Local variables
wire [SWITCH_ADDR_BITS - 1 : 0] sel;
integer i;
// Internal register interface signals
reg int_reg_req[NUM_OUTPUTS - 1 : 0];
reg int_reg_rd_wr_L[NUM_OUTPUTS - 1 : 0];
reg [REG_ADDR_BITS -1:0] int_reg_addr[NUM_OUTPUTS - 1 : 0];
reg [`CPCI_NF2_DATA_WIDTH -1:0] int_reg_wr_data[NUM_OUTPUTS - 1 : 0];
wire int_reg_ack[NUM_OUTPUTS - 1 : 0];
wire [`CPCI_NF2_DATA_WIDTH -1:0] int_reg_rd_data[NUM_OUTPUTS - 1 : 0];
assign sel = reg_addr[REG_ADDR_BITS - 1 : REG_ADDR_BITS - SWITCH_ADDR_BITS];
// =====================================================
// Process register requests
always @(posedge clk)
begin
for (i = 0; i < NUM_OUTPUTS ; i = i + 1) begin
if (reset || sel != i) begin
int_reg_req[i] <= 1'b0;
int_reg_rd_wr_L[i] <= 1'b0;
int_reg_addr[i] <= 'h0;
int_reg_wr_data[i] <= 'h0;
end
else begin
int_reg_req[i] <= reg_req;
int_reg_rd_wr_L[i] <= reg_rd_wr_L;
int_reg_addr[i] <= reg_addr;
int_reg_wr_data[i] <= reg_wr_data;
end
end // for
end
always @(posedge clk)
begin
if (reset || sel >= NUM_OUTPUTS) begin
// Reset the outputs
reg_ack <= 1'b0;
reg_rd_data <= reset ? 'h0 : 'h dead_beef;
end
else begin
reg_ack <= int_reg_ack[sel];
reg_rd_data <= int_reg_rd_data[sel];
end
end
// =====================================================
// Logic to split/join inputs/outputs
genvar j;
generate
for (j = 0; j < NUM_OUTPUTS ; j = j + 1) begin : flatten
assign local_reg_req[j] = int_reg_req[j];
assign local_reg_rd_wr_L[j] = int_reg_rd_wr_L[j];
assign local_reg_addr[j * (REG_ADDR_BITS - SWITCH_ADDR_BITS) +: (REG_ADDR_BITS - SWITCH_ADDR_BITS)] = int_reg_addr[j];
assign local_reg_wr_data[j * `CPCI_NF2_DATA_WIDTH +: `CPCI_NF2_DATA_WIDTH] = int_reg_wr_data[j];
assign int_reg_ack[j] = local_reg_ack[j];
assign int_reg_rd_data[j] = local_reg_rd_data[j * `CPCI_NF2_DATA_WIDTH +: `CPCI_NF2_DATA_WIDTH];
end
endgenerate
// =====================================================
// Verify that ack is never high when the request signal is low
// synthesis translate_off
integer k;
always @(posedge clk) begin
if (reg_req === 1'b0)
for (k = 0; k < NUM_OUTPUTS ; k = k + 1)
if (int_reg_ack[k] === 1'b1)
$display($time, " %m: ERROR: int_reg_ack[%1d] is high when reg_req is low", k);
end
// synthesis translate_on
endmodule
|
module sky130_fd_sc_hd__sdfrbp (
Q ,
Q_N ,
CLK ,
D ,
SCD ,
SCE ,
RESET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
output Q_N ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input RESET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
endmodule
|
module sky130_fd_sc_lp__clkbuflp (
//# {{data|Data Signals}}
input A,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
|
module ctu_dft_jtag (/*AUTOARG*/
// Outputs
dft_tdo, io_tdo_en, jtag_creg_addr, jtag_creg_data, jtag_creg_rd_en,
jtag_creg_wr_en, jtag_creg_addr_en, jtag_creg_data_en,
jtag_creg_rdrtrn_complete, jtag_bist_serial, jtag_bist_parallel,
jtag_bist_active, jtag_bist_abort, dft_pll_div2, dft_pll_arst_l,
dft_pll_testmode, dft_pll_clamp_fltr, jtag_clsp_stop_id_vld,
jtag_clsp_stop_id, jtag_nstep_vld, jtag_nstep_domain,
jtag_nstep_count, dft_clsp_nstep_capture_l, jtag_clock_dr,
jtag_clsp_ignore_wrm_rst, jtag_clsp_sel_tck2,
jtag_clsp_force_cken_cmp, jtag_clsp_force_cken_dram,
jtag_clsp_force_cken_jbus, pll_bypass, ctu_sel_cpu, ctu_sel_dram,
ctu_sel_jbus, ctu_spc0_sscan_se, ctu_spc1_sscan_se,
ctu_spc2_sscan_se, ctu_spc3_sscan_se, ctu_spc4_sscan_se,
ctu_spc5_sscan_se, ctu_spc6_sscan_se, ctu_spc7_sscan_se,
ctu_spc0_tck, ctu_spc1_tck, ctu_spc2_tck, ctu_spc3_tck, ctu_spc4_tck,
ctu_spc5_tck, ctu_spc6_tck, ctu_spc7_tck, ctu_spc_sscan_tid,
ctu_pads_sscan_update, ctu_global_snap, ctu_ddr0_mode_ctl,
ctu_ddr0_hiz_l, ctu_ddr0_update_dr, ctu_ddr0_clock_dr,
ctu_ddr0_shift_dr, ctu_ddr1_mode_ctl, ctu_ddr1_hiz_l,
ctu_ddr1_update_dr, ctu_ddr1_clock_dr, ctu_ddr1_shift_dr,
ctu_ddr2_mode_ctl, ctu_ddr2_hiz_l, ctu_ddr2_update_dr,
ctu_ddr2_clock_dr, ctu_ddr2_shift_dr, ctu_ddr3_mode_ctl,
ctu_ddr3_hiz_l, ctu_ddr3_update_dr, ctu_ddr3_clock_dr,
ctu_ddr3_shift_dr, ctu_jbusl_mode_ctl, ctu_jbusl_hiz_l,
ctu_jbusl_update_dr, ctu_jbusl_clock_dr, ctu_jbusl_shift_dr,
ctu_jbusr_mode_ctl, ctu_jbusr_hiz_l, ctu_jbusr_update_dr,
ctu_jbusr_clock_dr, ctu_jbusr_shift_dr, ctu_debug_mode_ctl,
ctu_debug_hiz_l, ctu_debug_update_dr, ctu_debug_clock_dr,
ctu_debug_shift_dr, ctu_misc_mode_ctl, ctu_misc_hiz_l,
ctu_misc_update_dr, ctu_misc_clock_dr, ctu_misc_shift_dr,
ctu_pads_bso, global_shift_enable, global_scan_bypass_en,
dft_ctu_scan_disable, dft_pin_pscan_l, ctu_pads_so, ctu_fpu_so,
pscan_select, ctu_ddr_testmode_l, ctu_tst_scanmode,
ctu_tst_macrotest, ctu_tst_short_chain, ctu_tst_scan_disable,
ctu_efc_data_in, ctu_efc_updatedr, ctu_efc_shiftdr,
ctu_efc_capturedr, ctu_efc_tck, ctu_efc_rowaddr, ctu_efc_coladdr,
ctu_efc_read_en, ctu_efc_read_mode, ctu_efc_fuse_bypass,
ctu_efc_dest_sample, dft_rng_vctrl, dft_rng_rst_l, dft_tsr_div,
dft_tsr_tsel, dft_tsr_reset_l, testmode_l,
// Inputs
jbus_rst_l, io_tdi, io_tms, io_trst_l, io_tck, tck_l, jtag_id,
test_mode_pin, afi_rng_ctl, afi_tsr_div, afi_tsr_mode,
afi_pll_char_mode, afi_pll_div2, afi_pll_trst_l, afi_tsr_tsel,
afi_pll_clamp_fltr, creg_jtag_scratch_data, creg_jtag_rdrtrn_data,
creg_jtag_rdrtrn_vld, bist_jtag_result, bist_jtag_abort_done,
pll_bypass_pin, pll_reset_ref_l, spc0_ctu_sscan_out,
spc1_ctu_sscan_out, spc2_ctu_sscan_out, spc3_ctu_sscan_out,
spc4_ctu_sscan_out, spc5_ctu_sscan_out, spc6_ctu_sscan_out,
spc7_ctu_sscan_out, pads_ctu_bsi, pads_ctu_si,
sctag2_ctu_serial_scan_in, efc_ctu_data_out
);
//global interface
input jbus_rst_l;
//JTAG chip interface
input io_tdi;
input io_tms;
input io_trst_l;
input io_tck;
input tck_l;
output dft_tdo; //io_tdo;
output io_tdo_en;
// id info
input [3:0] jtag_id;
// test_mode pins
input test_mode_pin;
//input pscan_mode_pin;
//input shift_en_pin;
input [2:0] afi_rng_ctl;
input [9:1] afi_tsr_div;
input afi_tsr_mode;
input afi_pll_char_mode;
input [5:0] afi_pll_div2;
input afi_pll_trst_l;
input [7:0] afi_tsr_tsel;
input afi_pll_clamp_fltr;
//creg R/W interface
output [39:0] jtag_creg_addr; //address of internal register
output [63:0] jtag_creg_data; //data to load into internal register
output jtag_creg_rd_en;
output jtag_creg_wr_en;
output jtag_creg_addr_en;
output jtag_creg_data_en;
input [63:0] creg_jtag_scratch_data;
input [63:0] creg_jtag_rdrtrn_data;
input creg_jtag_rdrtrn_vld;
output jtag_creg_rdrtrn_complete;
// bist blk interface
//input bist_jtag_busy;
input [(`CTU_BIST_CNT*2)-1:0] bist_jtag_result;
input bist_jtag_abort_done;
output jtag_bist_serial;
output jtag_bist_parallel;
output [`CTU_BIST_CNT-1:0] jtag_bist_active;
output jtag_bist_abort;
// PLL and clock
input pll_bypass_pin;
input pll_reset_ref_l;
output [5:0] dft_pll_div2;
output dft_pll_arst_l;
output dft_pll_testmode;
output dft_pll_clamp_fltr;
output jtag_clsp_stop_id_vld;
output [5:0] jtag_clsp_stop_id;
output jtag_nstep_vld;
output [2:0] jtag_nstep_domain;
output [3:0] jtag_nstep_count;
output dft_clsp_nstep_capture_l;
output jtag_clock_dr;
output jtag_clsp_ignore_wrm_rst;
output jtag_clsp_sel_tck2;
//output jtag_clsp_force_cken;
output jtag_clsp_force_cken_cmp;
output jtag_clsp_force_cken_dram;
output jtag_clsp_force_cken_jbus;
//control interface
output pll_bypass;
output [2:0] ctu_sel_cpu;
output [2:0] ctu_sel_dram;
output [2:0] ctu_sel_jbus;
// shadow scan interface
input spc0_ctu_sscan_out;
input spc1_ctu_sscan_out;
input spc2_ctu_sscan_out;
input spc3_ctu_sscan_out;
input spc4_ctu_sscan_out;
input spc5_ctu_sscan_out;
input spc6_ctu_sscan_out;
input spc7_ctu_sscan_out;
output ctu_spc0_sscan_se;
output ctu_spc1_sscan_se;
output ctu_spc2_sscan_se;
output ctu_spc3_sscan_se;
output ctu_spc4_sscan_se;
output ctu_spc5_sscan_se;
output ctu_spc6_sscan_se;
output ctu_spc7_sscan_se;
output ctu_spc0_tck;
output ctu_spc1_tck;
output ctu_spc2_tck;
output ctu_spc3_tck;
output ctu_spc4_tck;
output ctu_spc5_tck;
output ctu_spc6_tck;
output ctu_spc7_tck;
output [3:0] ctu_spc_sscan_tid;
output ctu_pads_sscan_update;
output ctu_global_snap;
// Boundary Scan
output ctu_ddr0_mode_ctl;
output ctu_ddr0_hiz_l;
output ctu_ddr0_update_dr;
output ctu_ddr0_clock_dr;
output ctu_ddr0_shift_dr;
output ctu_ddr1_mode_ctl;
output ctu_ddr1_hiz_l;
output ctu_ddr1_update_dr;
output ctu_ddr1_clock_dr;
output ctu_ddr1_shift_dr;
output ctu_ddr2_mode_ctl;
output ctu_ddr2_hiz_l;
output ctu_ddr2_update_dr;
output ctu_ddr2_clock_dr;
output ctu_ddr2_shift_dr;
output ctu_ddr3_mode_ctl;
output ctu_ddr3_hiz_l;
output ctu_ddr3_update_dr;
output ctu_ddr3_clock_dr;
output ctu_ddr3_shift_dr;
output ctu_jbusl_mode_ctl;
output ctu_jbusl_hiz_l;
output ctu_jbusl_update_dr;
output ctu_jbusl_clock_dr;
output ctu_jbusl_shift_dr;
output ctu_jbusr_mode_ctl;
output ctu_jbusr_hiz_l;
output ctu_jbusr_update_dr;
output ctu_jbusr_clock_dr;
output ctu_jbusr_shift_dr;
output ctu_debug_mode_ctl;
output ctu_debug_hiz_l;
output ctu_debug_update_dr;
output ctu_debug_clock_dr;
output ctu_debug_shift_dr;
output ctu_misc_mode_ctl;
output ctu_misc_hiz_l;
output ctu_misc_update_dr;
output ctu_misc_clock_dr;
output ctu_misc_shift_dr;
output ctu_pads_bso;
input pads_ctu_bsi;
//scan signals
input pads_ctu_si;
input sctag2_ctu_serial_scan_in;
output global_shift_enable;
output global_scan_bypass_en;
output dft_ctu_scan_disable; //disable ctu cluster scan if not pin-based scan
output dft_pin_pscan_l; // select long chain is pin-based scan
output ctu_pads_so;
output ctu_fpu_so;
//pad connection for scan
output pscan_select;
// ctu and pad share scan chain
output ctu_ddr_testmode_l;
//cluster scanin
output ctu_tst_scanmode;
output ctu_tst_macrotest;
output ctu_tst_short_chain;
output ctu_tst_scan_disable;
// efuse shift interface (tck domain)
input efc_ctu_data_out; // Serial(scan) out from ctu
output ctu_efc_data_in; // Serial(scan) in to efc
output ctu_efc_updatedr;
output ctu_efc_shiftdr;
output ctu_efc_capturedr;
output ctu_efc_tck;
// efuse r/w interface
output [6:0] ctu_efc_rowaddr;
output [4:0] ctu_efc_coladdr;
output ctu_efc_read_en;
output [2:0] ctu_efc_read_mode;
output ctu_efc_fuse_bypass;
// efuse dest sample
output ctu_efc_dest_sample;
// random number generator
output [2:0] dft_rng_vctrl;
output dft_rng_rst_l;
// temperature sensor regulator
output [9:1] dft_tsr_div;
output [7:0] dft_tsr_tsel;
output dft_tsr_reset_l;
// CTU Internal scan
output testmode_l;
////////////////////////////////////////////////////////////////////////
// Interface signal type declarations
////////////////////////////////////////////////////////////////////////
reg [2:0] dft_rng_vctrl;
reg dft_rng_rst_l;
reg [9:1] dft_tsr_div;
reg [7:0] dft_tsr_tsel;
reg dft_tsr_reset_l;
reg [5:0] dft_pll_div2;
reg dft_pll_arst_l;
reg dft_pll_clamp_fltr;
reg ctu_pads_bso;
reg ctu_fpu_so;
reg [3:0] ctu_spc_sscan_tid;
////////////////////////////////////////////////////////////////////////
// Local signal declarations
////////////////////////////////////////////////////////////////////////
parameter TAP_CMD_LO = 0,
TAP_CMD_HI = `TAP_CMD_WIDTH - 1,
TAP_SSCAN_CFG_WIDTH = 8,
TAP_SSCAN_CFG_LO = TAP_CMD_HI + 1,
TAP_SSCAN_CFG_HI = TAP_SSCAN_CFG_LO + TAP_SSCAN_CFG_WIDTH - 1,
TAP_SSCAN_UPDATE = TAP_SSCAN_CFG_HI + 1,
TAP_MBIST_ACTIVE_WIDTH = `CTU_BIST_CNT,
TAP_MBIST_ACTIVE_LO = TAP_CMD_HI + 1,
TAP_MBIST_ACTIVE_HI = TAP_MBIST_ACTIVE_LO + TAP_MBIST_ACTIVE_WIDTH - 1,
TAP_CLK_STOP_ID_WIDTH = 6,
TAP_CLK_STOP_ID_LO = TAP_CMD_HI + 1,
TAP_CLK_STOP_ID_HI = TAP_CLK_STOP_ID_LO + TAP_CLK_STOP_ID_WIDTH - 1,
TAP_SUPPRESS_CAP_BIT = TAP_CMD_HI + 1,
TAP_CKEN_BIT = TAP_CMD_HI + 2,
TAP_SCAN_MODE_BIT = TAP_CMD_HI + 1,
TAP_SCAN_NSTEP_DOM_WIDTH = 3,
TAP_SCAN_NSTEP_CNT_WIDTH = 4,
TAP_SCAN_NSTEP_DOM_LO = TAP_CMD_HI + 1,
TAP_SCAN_NSTEP_DOM_HI = TAP_SCAN_NSTEP_DOM_LO + TAP_SCAN_NSTEP_DOM_WIDTH - 1,
TAP_SCAN_NSTEP_CNT_LO = TAP_SCAN_NSTEP_DOM_HI + 1,
TAP_SCAN_NSTEP_CNT_HI = TAP_SCAN_NSTEP_CNT_LO + TAP_SCAN_NSTEP_CNT_WIDTH - 1,
TAP_SCAN_CLK_SEL_WIDTH = 3,
TAP_SCAN_CLK_SEL_CPU_LO = TAP_CMD_HI + 1,
TAP_SCAN_CLK_SEL_CPU_HI = TAP_SCAN_CLK_SEL_CPU_LO + TAP_SCAN_CLK_SEL_WIDTH - 1,
TAP_SCAN_CLK_SEL_DRAM_LO = TAP_SCAN_CLK_SEL_CPU_HI + 1,
TAP_SCAN_CLK_SEL_DRAM_HI = TAP_SCAN_CLK_SEL_DRAM_LO + TAP_SCAN_CLK_SEL_WIDTH - 1,
TAP_SCAN_CLK_SEL_JBUS_LO = TAP_SCAN_CLK_SEL_DRAM_HI + 1,
TAP_SCAN_CLK_SEL_JBUS_HI = TAP_SCAN_CLK_SEL_JBUS_LO + TAP_SCAN_CLK_SEL_WIDTH - 1;
parameter TAP_SCAN_MODE_PARALLEL = 1'b1,
TAP_SCAN_MODE_SERIAL = 1'b0;
parameter JTAG_SDR_CNT_WIDTH = 4,
JTAG_CKEN_DRAM_WAIT = 4'd6,
JTAG_CKEN_JBUS_WAIT = 4'd6,
JTAG_CKEN_OTHER_WAIT = 4'd8;
wire [31:0] idcode;
wire [39:0] creg_addr;
wire [63:0] creg_wdata;
wire [64:0] creg_rdrtrn;
wire [63:0] scratch_reg;
wire instr_normal_scan;
wire instr_scan;
wire global_shift_enable_pre;
wire pscan_select_pre;
wire shadow_scan_instr;
wire [TAP_SSCAN_CFG_WIDTH-1:0] shadow_scan_config_reg;
wire [3:0] spc_sscan_tid;
wire suppress_capture_l;
wire pll_bypass_tap;
wire spc0_sscan_se_pre;
wire spc1_sscan_se_pre;
wire spc2_sscan_se_pre;
wire spc3_sscan_se_pre;
wire spc4_sscan_se_pre;
wire spc5_sscan_se_pre;
wire spc6_sscan_se_pre;
wire spc7_sscan_se_pre;
wire spc0_tck_pre;
wire spc1_tck_pre;
wire spc2_tck_pre;
wire spc3_tck_pre;
wire spc4_tck_pre;
wire spc5_tck_pre;
wire spc6_tck_pre;
wire spc7_tck_pre;
wire bscan_enable;
wire ddr0_clock_dr_pre;
wire ddr0_shift_dr_pre;
wire ddr1_clock_dr_pre;
wire ddr1_shift_dr_pre;
wire ddr2_clock_dr_pre;
wire ddr2_shift_dr_pre;
wire ddr3_clock_dr_pre;
wire ddr3_shift_dr_pre;
wire jbusl_clock_dr_pre;
wire jbusl_shift_dr_pre;
wire jbusr_clock_dr_pre;
wire jbusr_shift_dr_pre;
wire debug_clock_dr_pre;
wire debug_shift_dr_pre;
wire misc_clock_dr_pre;
wire misc_shift_dr_pre;
wire [6:0] efc_rowaddr;
wire [4:0] efc_coladdr;
wire [2:0] efc_read_mode;
wire efc_tck_pre;
wire [JTAG_SDR_CNT_WIDTH-1:0] scan_dump_shiftdr_cnt;
wire [JTAG_SDR_CNT_WIDTH-1:0] cken_dram_wait;
wire [JTAG_SDR_CNT_WIDTH-1:0] cken_jbus_wait;
wire [JTAG_SDR_CNT_WIDTH-1:0] cken_other_wait;
wire sel_tck2_pre;
wire nstep_mode;
reg [31:0] next_idcode;
reg [39:0] next_creg_addr;
reg [63:0] next_creg_wdata;
reg [64:0] next_creg_rdrtrn;
reg [63:0] next_scratch_reg;
wire next_instr_normal_scan;
wire next_instr_scan;
wire next_global_shift_enable_pre;
wire next_pscan_select_pre;
wire next_shadow_scan_instr;
wire [3:0] next_spc_sscan_tid;
reg [TAP_SSCAN_CFG_WIDTH-1:0] next_shadow_scan_config_reg;
wire next_pll_bypass_tap;
wire next_spc0_tck_pre;
wire next_spc1_tck_pre;
wire next_spc2_tck_pre;
wire next_spc3_tck_pre;
wire next_spc4_tck_pre;
wire next_spc5_tck_pre;
wire next_spc6_tck_pre;
wire next_spc7_tck_pre;
wire next_spc0_sscan_se_pre;
wire next_spc1_sscan_se_pre;
wire next_spc2_sscan_se_pre;
wire next_spc3_sscan_se_pre;
wire next_spc4_sscan_se_pre;
wire next_spc5_sscan_se_pre;
wire next_spc6_sscan_se_pre;
wire next_spc7_sscan_se_pre;
wire next_bscan_enable;
wire next_ddr0_clock_dr_pre;
wire next_ddr0_shift_dr_pre;
wire next_ddr1_clock_dr_pre;
wire next_ddr1_shift_dr_pre;
wire next_ddr2_clock_dr_pre;
wire next_ddr2_shift_dr_pre;
wire next_ddr3_clock_dr_pre;
wire next_ddr3_shift_dr_pre;
wire next_jbusl_clock_dr_pre;
wire next_jbusl_shift_dr_pre;
wire next_jbusr_clock_dr_pre;
wire next_jbusr_shift_dr_pre;
wire next_debug_clock_dr_pre;
wire next_debug_shift_dr_pre;
wire next_misc_clock_dr_pre;
wire next_misc_shift_dr_pre;
wire next_suppress_capture_l;
reg [6:0] next_efc_rowaddr;
reg [4:0] next_efc_coladdr;
reg [2:0] next_efc_read_mode;
wire next_efc_tck_pre;
reg next_nstep_mode;
reg [JTAG_SDR_CNT_WIDTH-1:0] next_scan_dump_shiftdr_cnt;
wire [JTAG_SDR_CNT_WIDTH-1:0] next_cken_dram_wait;
wire [JTAG_SDR_CNT_WIDTH-1:0] next_cken_jbus_wait;
wire [JTAG_SDR_CNT_WIDTH-1:0] next_cken_other_wait;
wire next_sel_tck2_pre;
wire creg_addr_shift;
wire creg_wdata_shift;
wire shadow_scan_config_reg_en;
reg [TAP_SSCAN_CFG_WIDTH-1:0] shadow_scan_config_mask;
reg shadow_scan_out;
wire pin_based_pscan_mode;
wire pin_based_shift_en;
wire pin_based_pll_bypass;
wire tap_rst_l;
wire tap_so;
wire tap_tdo_en;
wire tap_bypass_sel;
wire tap_clock_dr;
wire [`TAP_INSTR_WIDTH-1:0] tap_instructions;
wire [`TAP_INSTR_WIDTH-1:0] next_tap_instructions;
wire scratch_en_shift_dr;
wire scratch_reg_load;
wire instr_bypass;
wire instr_idcode;
wire instr_highz;
wire instr_clamp;
wire next_instr_highz;
wire next_instr_clamp;
wire next_instr_extest;
wire next_instr_sample_preload;
wire instr_creg_addr;
wire instr_creg_wdata;
wire instr_creg_rdata;
wire instr_creg_scratch;
wire instr_iob_wr;
wire instr_iob_rd;
wire instr_iob_rd_d1;
wire instr_iob_waddr;
wire instr_iob_wdata;
wire instr_iob_raddr;
wire instr_iob_raddr_d1;
wire instr_scan_parallel;
wire instr_scan_serial;
wire instr_scan_dump;
wire instr_scan_mtest;
wire next_instr_scan_parallel;
wire next_instr_scan_serial;
wire next_instr_scan_dump;
wire next_instr_scan_mtest_long;
wire next_instr_scan_mtest_short;
wire next_instr_scan_mtest;
wire next_instr_sscan_t0;
wire next_instr_sscan_t1;
wire next_instr_sscan_t2;
wire next_instr_sscan_t3;
wire instr_scan_bypass_en;
wire instr_scan_nstep;
wire instr_mbist_serial;
wire instr_mbist_parallel;
wire instr_mbist_result;
wire instr_mbist_abort;
wire next_instr_efc_read;
wire next_instr_efc_bypass_data;
wire next_instr_efc_bypass;
wire instr_efc_read;
wire instr_efc_bypass_data;
wire instr_efc_read_mode;
wire instr_efc_col_addr;
wire instr_efc_row_addr;
wire instr_efc_dest_sample;
wire instr_pll_bypass;
wire instr_clk_stop_id;
wire instr_clk_sel;
wire instr_efc_shift;
wire tap_capture_dr_state;
wire tap_shift_dr_state;
wire tap_shift_dr_state_d1;
wire tap_pause_dr_state;
wire tap_update_dr_state;
wire tap_shift_exit2_dr_state;
wire tap_update_ir_state;
wire creg_addr_instr;
wire creg_data_instr;
wire bist_result_reg_load;
wire bist_result_reg_shift;
wire [(`CTU_BIST_CNT*2)-1:0] bist_result_reg;
reg [(`CTU_BIST_CNT*2)-1:0] next_bist_result_reg;
wire toggle_pll_bypass_tap;
wire creg_rdrtrn_shift;
wire clear_creg_rdrtrn_vld;
wire creg_rdrtrn_vld;
wire next_creg_rdrtrn_vld;
wire creg_rdrtrn_out;
wire creg_rdrtrn_load;
wire creg_rdrtrn_load_d1;
wire creg_jtag_rdrtrn_vld_d;
wire creg_jtag_rdrtrn_vld_d2;
wire clock_dr_instr_scan_dump_capture;
wire [TAP_SCAN_CLK_SEL_WIDTH-1:0] clk_sel_cpu;
wire [TAP_SCAN_CLK_SEL_WIDTH-1:0] clk_sel_dram;
wire [TAP_SCAN_CLK_SEL_WIDTH-1:0] clk_sel_jbus;
wire [2:0] sel_cpu;
wire [2:0] sel_dram;
wire [2:0] sel_jbus;
wire [2:0] sel_cpu_ff;
wire [2:0] sel_dram_ff;
wire [2:0] sel_jbus_ff;
reg [2:0] next_sel_cpu_ff;
reg [2:0] next_sel_dram_ff;
reg [2:0] next_sel_jbus_ff;
wire next_jtag_bist_serial;
wire next_jtag_bist_parallel;
reg [TAP_MBIST_ACTIVE_WIDTH-1:0] next_jtag_bist_active;
wire efc_rowaddr_shift;
wire efc_coladdr_shift;
wire efc_read_mode_shift;
wire next_global_scan_bypass_en;
wire bscan_mode_ctl;
wire bscan_hiz_l;
wire bscan_update_dr;
wire bscan_clock_dr_pre;
wire bscan_shift_dr_pre;
wire next_ctu_ddr0_mode_ctl;
wire next_ctu_ddr0_hiz_l;
wire next_ctu_ddr0_update_dr;
wire next_ctu_ddr1_mode_ctl;
wire next_ctu_ddr1_hiz_l;
wire next_ctu_ddr1_update_dr;
wire next_ctu_ddr2_mode_ctl;
wire next_ctu_ddr2_hiz_l;
wire next_ctu_ddr2_update_dr;
wire next_ctu_ddr3_mode_ctl;
wire next_ctu_ddr3_hiz_l;
wire next_ctu_ddr3_update_dr;
wire next_ctu_jbusl_mode_ctl;
wire next_ctu_jbusl_hiz_l;
wire next_ctu_jbusl_update_dr;
wire next_ctu_jbusr_mode_ctl;
wire next_ctu_jbusr_hiz_l;
wire next_ctu_jbusr_update_dr;
wire next_ctu_debug_mode_ctl;
wire next_ctu_debug_hiz_l;
wire next_ctu_debug_update_dr;
wire next_ctu_misc_mode_ctl;
wire next_ctu_misc_hiz_l;
wire next_ctu_misc_update_dr;
wire pll_bypass;
wire dft_pin_pscan;
wire next_ctu_global_snap;
wire next_ctu_tst_macrotest;
wire next_ctu_tst_short_chain;
wire next_ctu_pads_sscan_update;
wire next_spc0_sscan;
wire next_spc1_sscan;
wire next_spc2_sscan;
wire next_spc3_sscan;
wire next_spc4_sscan;
wire next_spc5_sscan;
wire next_spc6_sscan;
wire next_spc7_sscan;
wire next_pads_sscan;
wire next_pads_sscan_se_pre;
wire next_pads_tck_pre;
wire next_ctu_efc_capturedr;
wire next_ctu_efc_shiftdr;
wire next_ctu_efc_updatedr;
wire next_ctu_efc_fuse_bypass;
wire next_ctu_efc_read_en;
wire next_ctu_efc_dest_sample;
wire [6:0] next_ctu_efc_rowaddr;
wire [4:0] next_ctu_efc_coladdr;
wire [2:0] next_ctu_efc_read_mode;
wire next_jtag_bist_abort;
wire next_jtag_creg_addr_en;
wire next_jtag_creg_wr_en;
wire next_jtag_creg_rd_en;
wire next_jtag_creg_data_en;
wire next_dft_clsp_nstep_capture_l;
wire next_jtag_clsp_force_cken_cmp;
wire next_jtag_clsp_force_cken_dram;
wire next_jtag_clsp_force_cken_jbus;
wire tap_update_ir_state_d1;
wire tap_update_ir_state_d2;
wire scan_dump_cken_cmp;
wire scan_dump_cken_dram;
wire scan_dump_cken_jbus;
wire scan_dump_cken_other;
wire normal_force_cken;
wire inc_scan_dump_shiftdr_cnt;
wire test_mode_pin_l;
wire trst;
wire global_scan_bypass_en_pre; // bug #5483
wire bypass_chain31; // bug #5581
reg pads_ctu_si_bypmux_out; // bug #5581
wire serial_scan; // bug #5695
wire pads_ctu_si_bypmux_out_ff; // bug #5696
//********************************************************************
// Pin-based operations
//********************************************************************
// use io_trst_l pin as pscan_mode_pin_l ans io_tms as shift_en_pin
// when test_mode_pin is asserted
//assign tap_rst_l = test_mode_pin | io_trst_l;
ctu_or2 u_or2_tap_rst_l (.a (test_mode_pin),
.b (io_trst_l),
.z (tap_rst_l)
);
//assign pin_based_pscan_mode = test_mode_pin & ~io_trst_l;
ctu_inv u_inv_test_mode_pin_l (.a (test_mode_pin),
.z (test_mode_pin_l)
);
ctu_nor2 u_nor2_pin_based_pscan_mode (.a(test_mode_pin_l),
.b(io_trst_l),
.z(pin_based_pscan_mode)
);
//assign pin_based_pll_bypass = test_mode_pin & pll_bypass_pin;
ctu_and2 u_and2_pin_based_pll_bypass (.a(test_mode_pin),
.b(pll_bypass_pin),
.z(pin_based_pll_bypass)
);
assign pin_based_shift_en = test_mode_pin & ~io_trst_l & io_tms;
//********************************************************************
// TAP Controller
//********************************************************************
ctu_dft_jtag_tap u_tap_controller (
// Inputs
.tck (io_tck),
.tck_l (tck_l),
.trst_n (tap_rst_l),
.tms (io_tms),
.tdi (io_tdi),
.so (tap_so),
.bypass_sel (tap_bypass_sel),
.dft_pin_pscan(dft_pin_pscan),
// Outputs
.capture_dr_state (tap_capture_dr_state),
.shift_dr_state (tap_shift_dr_state),
.pause_dr_state (tap_pause_dr_state),
.update_dr_state (tap_update_dr_state),
.shift_exit2_dr_state (tap_shift_exit2_dr_state),
.update_ir_state (tap_update_ir_state),
.clock_dr (tap_clock_dr),
.tdo (dft_tdo),
.tdo_en (tap_tdo_en),
.instructions (tap_instructions),
.next_instructions (next_tap_instructions)
);
//instruction decode
assign instr_bypass = tap_instructions[TAP_CMD_HI:TAP_CMD_LO] == {`TAP_CMD_WIDTH{1'b1}}
| (tap_instructions[TAP_CMD_HI:TAP_CMD_HI-3] == 4'b0001 // 0x05 thru 0x07
& (|tap_instructions[TAP_CMD_HI-4:TAP_CMD_LO]))
| (tap_instructions[TAP_CMD_HI:TAP_CMD_HI-3] == 4'b0100 // 0x11 thru 0x13
& (|tap_instructions[TAP_CMD_HI-4:TAP_CMD_LO]))
| tap_instructions[TAP_CMD_HI:TAP_CMD_LO] == 6'h19
| tap_instructions[TAP_CMD_HI:TAP_CMD_LO] == 6'h27
| tap_instructions[TAP_CMD_HI:TAP_CMD_LO] == 6'h2F
| tap_instructions[TAP_CMD_HI:TAP_CMD_HI-1] == 2'd3;
assign instr_idcode = tap_instructions[TAP_CMD_HI:TAP_CMD_LO] == `TAP_IDCODE;
assign instr_highz = tap_instructions[TAP_CMD_HI:TAP_CMD_LO] == `TAP_HIGHZ;
assign instr_clamp = tap_instructions[TAP_CMD_HI:TAP_CMD_LO] == `TAP_CLAMP;
assign next_instr_highz = next_tap_instructions[TAP_CMD_HI:TAP_CMD_LO] == `TAP_HIGHZ;
assign next_instr_clamp = next_tap_instructions[TAP_CMD_HI:TAP_CMD_LO] == `TAP_CLAMP;
assign next_instr_extest = next_tap_instructions[TAP_CMD_HI:TAP_CMD_LO] == `TAP_EXTEST;
assign next_instr_sample_preload = next_tap_instructions[TAP_CMD_HI:TAP_CMD_LO] == `TAP_SAMPLE_PRELOAD;
assign instr_creg_addr = tap_instructions[TAP_CMD_HI:TAP_CMD_LO] == `TAP_CREG_ADDR;
assign instr_creg_wdata = tap_instructions[TAP_CMD_HI:TAP_CMD_LO] == `TAP_CREG_WDATA;
assign instr_creg_rdata = tap_instructions[TAP_CMD_HI:TAP_CMD_LO] == `TAP_CREG_RDATA;
assign instr_creg_scratch = tap_instructions[TAP_CMD_HI:TAP_CMD_LO] == `TAP_CREG_SCRATCH;
assign instr_iob_wr = tap_instructions[TAP_CMD_HI:TAP_CMD_LO] == `TAP_IOB_WR;
assign instr_iob_rd = tap_instructions[TAP_CMD_HI:TAP_CMD_LO] == `TAP_IOB_RD;
assign instr_iob_waddr = tap_instructions[TAP_CMD_HI:TAP_CMD_LO] == `TAP_IOB_WADDR;
assign instr_iob_wdata = tap_instructions[TAP_CMD_HI:TAP_CMD_LO] == `TAP_IOB_WDATA;
assign instr_iob_raddr = tap_instructions[TAP_CMD_HI:TAP_CMD_LO] == `TAP_IOB_RADDR;
assign instr_scan_parallel = tap_instructions[TAP_CMD_HI:TAP_CMD_LO] == `TAP_SCAN_PARALLEL;
assign instr_scan_serial = tap_instructions[TAP_CMD_HI:TAP_CMD_LO] == `TAP_SCAN_SERIAL;
assign instr_scan_dump = tap_instructions[TAP_CMD_HI:TAP_CMD_LO] == `TAP_SCAN_DUMP;
assign next_instr_scan_parallel = next_tap_instructions[TAP_CMD_HI:TAP_CMD_LO] == `TAP_SCAN_PARALLEL;
assign next_instr_scan_serial = next_tap_instructions[TAP_CMD_HI:TAP_CMD_LO] == `TAP_SCAN_SERIAL;
assign next_instr_scan_mtest_long = next_tap_instructions[TAP_CMD_HI:TAP_CMD_LO] == `TAP_SCAN_MTEST_LONG;
assign next_instr_scan_mtest_short = next_tap_instructions[TAP_CMD_HI:TAP_CMD_LO] == `TAP_SCAN_MTEST_SHORT;
assign next_instr_scan_dump = next_tap_instructions[TAP_CMD_HI:TAP_CMD_LO] == `TAP_SCAN_DUMP;
assign next_instr_sscan_t0 = next_tap_instructions[TAP_CMD_HI:TAP_CMD_LO] == `TAP_SSCAN_T0;
assign next_instr_sscan_t1 = next_tap_instructions[TAP_CMD_HI:TAP_CMD_LO] == `TAP_SSCAN_T1;
assign next_instr_sscan_t2 = next_tap_instructions[TAP_CMD_HI:TAP_CMD_LO] == `TAP_SSCAN_T2;
assign next_instr_sscan_t3 = next_tap_instructions[TAP_CMD_HI:TAP_CMD_LO] == `TAP_SSCAN_T3;
assign instr_scan_bypass_en = tap_instructions[TAP_CMD_HI:TAP_CMD_LO] == `TAP_SCAN_BYPASS_EN;
assign instr_scan_nstep = tap_instructions[TAP_CMD_HI:TAP_CMD_LO] == `TAP_SCAN_NSTEP;
assign instr_mbist_serial = tap_instructions[TAP_CMD_HI:TAP_CMD_LO] == `TAP_MBIST_SERIAL;
assign instr_mbist_parallel = tap_instructions[TAP_CMD_HI:TAP_CMD_LO] == `TAP_MBIST_PARALLEL;
assign instr_mbist_result = tap_instructions[TAP_CMD_HI:TAP_CMD_LO] == `TAP_MBIST_RESULT;
assign instr_mbist_abort = tap_instructions[TAP_CMD_HI:TAP_CMD_LO] == `TAP_MBIST_ABORT;
assign next_instr_efc_read = next_tap_instructions[TAP_CMD_HI:TAP_CMD_LO] == `TAP_EFC_READ;
assign next_instr_efc_bypass_data = next_tap_instructions[TAP_CMD_HI:TAP_CMD_LO] == `TAP_EFC_BYPASS_DATA;
assign next_instr_efc_bypass = next_tap_instructions[TAP_CMD_HI:TAP_CMD_LO] == `TAP_EFC_BYPASS;
assign instr_efc_read = tap_instructions[TAP_CMD_HI:TAP_CMD_LO] == `TAP_EFC_READ;
assign instr_efc_bypass_data = tap_instructions[TAP_CMD_HI:TAP_CMD_LO] == `TAP_EFC_BYPASS_DATA;
assign instr_efc_read_mode = tap_instructions[TAP_CMD_HI:TAP_CMD_LO] == `TAP_EFC_READ_MODE;
assign instr_efc_col_addr = tap_instructions[TAP_CMD_HI:TAP_CMD_LO] == `TAP_EFC_COL_ADDR;
assign instr_efc_row_addr = tap_instructions[TAP_CMD_HI:TAP_CMD_LO] == `TAP_EFC_ROW_ADDR;
assign instr_efc_dest_sample = tap_instructions[TAP_CMD_HI:TAP_CMD_LO] == `TAP_EFC_DEST_SAMPLE;
assign instr_pll_bypass = tap_instructions[TAP_CMD_HI:TAP_CMD_LO] == `TAP_PLL_BYPASS;
assign instr_clk_stop_id = tap_instructions[TAP_CMD_HI:TAP_CMD_LO] == `TAP_CLK_STOP_ID;
assign instr_clk_sel = tap_instructions[TAP_CMD_HI:TAP_CMD_LO] == `TAP_CLK_SEL;
assign instr_scan_mtest = tap_instructions[TAP_CMD_HI:TAP_CMD_LO] == `TAP_SCAN_MTEST_LONG
| tap_instructions[TAP_CMD_HI:TAP_CMD_LO] == `TAP_SCAN_MTEST_SHORT;
assign next_instr_scan_mtest = next_instr_scan_mtest_long | next_instr_scan_mtest_short;
assign instr_efc_shift = instr_efc_bypass_data
| instr_efc_read;
//tap_bypass_sel generation
assign tap_bypass_sel = instr_highz | instr_clamp | instr_bypass;
assign tap_so = // (idcode[31] & instr_idcode)
(idcode[0] & instr_idcode) // bug #5497
| (pads_ctu_bsi & bscan_enable)
| (creg_addr[39] & instr_creg_addr)
| (creg_wdata[63] & instr_creg_wdata)
| (scratch_reg[63] & instr_creg_scratch)
| (creg_rdrtrn_out & instr_creg_rdata)
//| (pads_ctu_si & instr_scan)
//| (pads_ctu_si_bypmux_out & instr_scan) // bug # 5581
| (pads_ctu_si_bypmux_out_ff & instr_scan) // bug # 5581 & bug #5696
| (efc_ctu_data_out & instr_efc_shift)
| (shadow_scan_out & shadow_scan_instr)
| (bist_result_reg[(`CTU_BIST_CNT*2)-1] & instr_mbist_result);
assign io_tdo_en = tap_tdo_en
| instr_creg_rdata
| dft_pin_pscan;
//********************************************************************
// IDCODE
//********************************************************************
always @ ( /*AUTOSENSE*/idcode or instr_idcode or io_tdi or jtag_id
or tap_capture_dr_state or tap_shift_dr_state) begin
if (instr_idcode & tap_capture_dr_state)
next_idcode = { jtag_id[3:0], `CTU_PART_ID, `CTU_MANUFACTURE_ID, 1'b1 };
else begin
if (instr_idcode & tap_shift_dr_state)
// next_idcode = { idcode[30:0], io_tdi };
next_idcode = { io_tdi, idcode[31:1] }; // bug #5497
else
next_idcode = idcode[31:0];
end
end
//********************************************************************
// CREG
//********************************************************************
//-----------------------
// address shift register
//-----------------------
assign creg_addr_instr = instr_creg_addr
| instr_iob_waddr
| instr_iob_raddr;
assign creg_addr_shift = creg_addr_instr & tap_shift_dr_state;
always @ ( /*AUTOSENSE*/creg_addr or creg_addr_shift or io_tdi) begin
if (creg_addr_shift)
next_creg_addr = { creg_addr[38:0], io_tdi };
else
next_creg_addr = creg_addr;
end
assign jtag_creg_addr = creg_addr[39:0];
//-----------------------
// data shift register
//-----------------------
assign creg_data_instr = instr_creg_wdata | instr_iob_wdata ;
assign creg_wdata_shift = creg_data_instr
& tap_shift_dr_state;
always @ ( /*AUTOSENSE*/creg_wdata or creg_wdata_shift or io_tdi) begin
if (creg_wdata_shift)
next_creg_wdata[63:0] = { creg_wdata[62:0], io_tdi };
else
next_creg_wdata[63:0] = creg_wdata[63:0];
end
assign jtag_creg_data = creg_wdata[63:0];
//------------------------------
//generate enables to creg block
//------------------------------
assign next_jtag_creg_addr_en = tap_update_dr_state & creg_addr_instr;
assign next_jtag_creg_wr_en = instr_iob_wr
| ( tap_update_dr_state
& ( instr_iob_wdata
| instr_iob_waddr));
assign next_jtag_creg_rd_en = instr_iob_rd
| tap_update_dr_state & instr_iob_raddr;
assign next_jtag_creg_data_en = tap_update_dr_state & creg_data_instr;
//---------------------
// Read Return Register
//---------------------
// Handshake with creg
// - load_l is generated on rising edge on creg_jtag_rdrtrn_vld
// - load delayed by one provides the output handshake to ctu_creg
assign creg_rdrtrn_load = creg_jtag_rdrtrn_vld & ~creg_jtag_rdrtrn_vld_d2;
assign jtag_creg_rdrtrn_complete = creg_rdrtrn_load_d1;
// start shifting out read data once it is valid
assign creg_rdrtrn_shift = instr_creg_rdata & tap_shift_dr_state & creg_rdrtrn_vld;
always @ ( /*AUTOSENSE*/creg_jtag_rdrtrn_data or creg_rdrtrn
or creg_rdrtrn_load or creg_rdrtrn_shift or io_tdi) begin
if (creg_rdrtrn_load)
next_creg_rdrtrn[64:0] = { 1'b1, creg_jtag_rdrtrn_data };
else begin
if (creg_rdrtrn_shift)
next_creg_rdrtrn[64:0] = { creg_rdrtrn[63:0], io_tdi };
else
next_creg_rdrtrn[64:0] = creg_rdrtrn[64:0];
end
end
// set when load data into read-return_reg
assign clear_creg_rdrtrn_vld = (instr_iob_rd & ~instr_iob_rd_d1)
| (instr_iob_raddr & ~instr_iob_raddr_d1);
assign next_creg_rdrtrn_vld = creg_rdrtrn_load
| (creg_rdrtrn_vld & ~clear_creg_rdrtrn_vld);
assign creg_rdrtrn_out = creg_rdrtrn[64] & creg_rdrtrn_vld;
//---------------------
// Scratch Register
//---------------------
assign scratch_en_shift_dr = instr_creg_scratch & tap_shift_dr_state;
assign scratch_reg_load = instr_creg_scratch & tap_capture_dr_state;
always @ ( /*AUTOSENSE*/creg_jtag_scratch_data or io_tdi
or scratch_en_shift_dr or scratch_reg or scratch_reg_load) begin
if (scratch_reg_load)
next_scratch_reg[63:0] = creg_jtag_scratch_data;
else begin
if (scratch_en_shift_dr)
next_scratch_reg[63:0] = { scratch_reg[62:0], io_tdi };
else
next_scratch_reg[63:0] = scratch_reg[63:0];
end
end
//*******************************************************************
// Internal Scan
// - parallel and serial scan
// - macro test
//********************************************************************
// to test stub
// do precalc for timing
assign next_instr_normal_scan = next_instr_scan_parallel
| next_instr_scan_serial
| next_instr_scan_mtest_long
| next_instr_scan_mtest_short;
assign next_instr_scan = next_instr_normal_scan | next_instr_scan_dump;
assign next_global_shift_enable_pre = ( instr_normal_scan
| scan_dump_cken_cmp )
& ( tap_shift_exit2_dr_state
| tap_shift_dr_state_d1); //extend shift_en by 1 cycle to ensure deassert after clock_dr (SRAM)
assign global_shift_enable = (global_shift_enable_pre & ~pin_based_pscan_mode)
| pin_based_shift_en;
assign ctu_tst_scanmode = instr_scan
| pin_based_pscan_mode; //needs to be asserted during pin base scan
assign next_ctu_tst_macrotest = next_instr_scan_mtest_long
| next_instr_scan_mtest_short;
assign next_ctu_tst_short_chain = next_instr_scan_mtest_short;
// Reuse unused ctu_tst_scan_disable as "short_scan_disable"
assign ctu_tst_scan_disable = pin_based_pscan_mode;
// ctu and pads in same scan chain
assign ctu_ddr_testmode_l = ~ctu_tst_scanmode;
// boundary scan cell
// negedge
assign next_global_scan_bypass_en = global_scan_bypass_en
^ (instr_scan_bypass_en & tap_update_ir_state_d1); //toggle cmd
// bug #5483
assign global_scan_bypass_en = global_scan_bypass_en_pre
& ~pin_based_shift_en;
// to pad cluster scan multiplexers
assign next_pscan_select_pre = next_instr_scan_parallel
| ( (next_instr_scan_dump | next_instr_scan_mtest)
& next_tap_instructions[TAP_SCAN_MODE_BIT] == TAP_SCAN_MODE_PARALLEL);
assign pscan_select = pin_based_pscan_mode | pscan_select_pre;
// si to pad cluster internal scan
assign ctu_pads_so = io_tdi;
assign dft_pin_pscan = pin_based_pscan_mode;
assign dft_pin_pscan_l = ~pin_based_pscan_mode;
// for pin-based parallel scan, ctu scan chain is included
assign dft_ctu_scan_disable = ~dft_pin_pscan;
// hookup for short vs. long chain in test stub
// - long chain activated during pin-based parallel scan
// - long chain includes boundary scan and ctu
always @ ( /*AUTOSENSE*/dft_pin_pscan or io_tdi
or pads_ctu_si_bypmux_out) begin
if (dft_pin_pscan)
// ctu_pads_bso = pads_ctu_si; // feeds pad cluster internal scan so to boudary scan si
ctu_pads_bso = pads_ctu_si_bypmux_out; // bug #5581
else
ctu_pads_bso = io_tdi;
end
// bug #5581
assign bypass_chain31 = global_scan_bypass_en
& ~pin_based_shift_en
& tap_instructions[8];
always @ ( /*AUTOSENSE*/bypass_chain31 or ctu_fpu_so or pads_ctu_si) begin
if (bypass_chain31)
pads_ctu_si_bypmux_out = ctu_fpu_so;
else
pads_ctu_si_bypmux_out = pads_ctu_si;
end
// CTU internal testmode_l - really means "pin-based parallel scan mode"
// force on all clock enables
assign testmode_l = ~pin_based_pscan_mode;
assign jtag_clsp_ignore_wrm_rst = instr_scan;
// scan clock to be distributed during internal scan
assign next_suppress_capture_l = ~(tap_capture_dr_state
& (next_instr_scan_dump
| (next_tap_instructions[TAP_SUPPRESS_CAP_BIT]
& ~nstep_mode
& (next_instr_scan_parallel | next_instr_scan_serial))));
ctu_and2 u_and2_clock_dr_scan_dump_cap
( .a(tap_clock_dr),
.b(suppress_capture_l),
.z(clock_dr_instr_scan_dump_capture)
);
ctu_mux21 u_mux21_jtag_clock_dr
( .d0(clock_dr_instr_scan_dump_capture),
.d1(io_tck),
.s (pin_based_pscan_mode),
.z (jtag_clock_dr)
);
//always @ ( /*AUTOSENSE*/ )
// jtag_clock_dr = io_tck;
// else
// jtag_clock_dr = tap_clock_dr & suppress_capture_l;
//end
//********************************************************************
// Boundary Scan
// - because IO shadow scan chanin is part of boundary scan, need
// to assert some boundary scan signals during IO shadow scan
// (bscan_clock_dr_out and bscan_shift_dr_out)
// - negedge
//********************************************************************
assign next_bscan_enable = next_instr_extest
| next_instr_sample_preload;
assign bscan_mode_ctl = next_instr_extest
| next_instr_clamp
| next_instr_highz;
assign bscan_hiz_l = ~next_instr_highz;
assign bscan_update_dr = next_bscan_enable & tap_update_dr_state;
assign bscan_clock_dr_pre = (next_bscan_enable
& ( tap_capture_dr_state
| tap_shift_dr_state))
| next_pads_tck_pre;
assign bscan_shift_dr_pre = (next_bscan_enable & tap_shift_exit2_dr_state)
| next_pads_sscan_se_pre;
// to pad_ddr0
assign next_ctu_ddr0_mode_ctl = bscan_mode_ctl;
assign next_ctu_ddr0_hiz_l = bscan_hiz_l;
assign next_ctu_ddr0_update_dr = bscan_update_dr;
assign next_ddr0_clock_dr_pre = bscan_clock_dr_pre;
assign next_ddr0_shift_dr_pre = bscan_shift_dr_pre;
assign ctu_ddr0_clock_dr = (ddr0_clock_dr_pre | pin_based_pscan_mode) & io_tck;
assign ctu_ddr0_shift_dr = ddr0_shift_dr_pre | pin_based_shift_en;
// to pad_ddr1
assign next_ctu_ddr1_mode_ctl = bscan_mode_ctl;
assign next_ctu_ddr1_hiz_l = bscan_hiz_l;
assign next_ctu_ddr1_update_dr = bscan_update_dr;
assign next_ddr1_clock_dr_pre = bscan_clock_dr_pre;
assign next_ddr1_shift_dr_pre = bscan_shift_dr_pre;
assign ctu_ddr1_clock_dr = (ddr1_clock_dr_pre | pin_based_pscan_mode) & io_tck;
assign ctu_ddr1_shift_dr = ddr1_shift_dr_pre | pin_based_shift_en;
// to pad_ddr2
assign next_ctu_ddr2_mode_ctl = bscan_mode_ctl;
assign next_ctu_ddr2_hiz_l = bscan_hiz_l;
assign next_ctu_ddr2_update_dr = bscan_update_dr;
assign next_ddr2_clock_dr_pre = bscan_clock_dr_pre;
assign next_ddr2_shift_dr_pre = bscan_shift_dr_pre;
assign ctu_ddr2_clock_dr = (ddr2_clock_dr_pre | pin_based_pscan_mode) & io_tck;
assign ctu_ddr2_shift_dr = ddr2_shift_dr_pre | pin_based_shift_en;
// to pad_ddr3
assign next_ctu_ddr3_mode_ctl = bscan_mode_ctl;
assign next_ctu_ddr3_hiz_l = bscan_hiz_l;
assign next_ctu_ddr3_update_dr = bscan_update_dr;
assign next_ddr3_clock_dr_pre = bscan_clock_dr_pre;
assign next_ddr3_shift_dr_pre = bscan_shift_dr_pre;
assign ctu_ddr3_clock_dr = (ddr3_clock_dr_pre | pin_based_pscan_mode) & io_tck;
assign ctu_ddr3_shift_dr = ddr3_shift_dr_pre | pin_based_shift_en;
// to pad_jbusl
assign next_ctu_jbusl_mode_ctl = bscan_mode_ctl;
assign next_ctu_jbusl_hiz_l = bscan_hiz_l;
assign next_ctu_jbusl_update_dr = bscan_update_dr;
assign next_jbusl_clock_dr_pre = bscan_clock_dr_pre;
assign next_jbusl_shift_dr_pre = bscan_shift_dr_pre;
assign ctu_jbusl_clock_dr = (jbusl_clock_dr_pre | pin_based_pscan_mode) & io_tck;
assign ctu_jbusl_shift_dr = jbusl_shift_dr_pre | pin_based_shift_en;
// to pad_jbusr
assign next_ctu_jbusr_mode_ctl = bscan_mode_ctl;
assign next_ctu_jbusr_hiz_l = bscan_hiz_l;
assign next_ctu_jbusr_update_dr = bscan_update_dr;
assign next_jbusr_clock_dr_pre = bscan_clock_dr_pre;
assign next_jbusr_shift_dr_pre = bscan_shift_dr_pre;
assign ctu_jbusr_clock_dr = (jbusr_clock_dr_pre | pin_based_pscan_mode) & io_tck;
assign ctu_jbusr_shift_dr = jbusr_shift_dr_pre | pin_based_shift_en;
// to pad_debug
assign next_ctu_debug_mode_ctl = bscan_mode_ctl;
assign next_ctu_debug_hiz_l = bscan_hiz_l;
assign next_ctu_debug_update_dr = bscan_update_dr;
assign next_debug_clock_dr_pre = bscan_clock_dr_pre;
assign next_debug_shift_dr_pre = bscan_shift_dr_pre;
assign ctu_debug_clock_dr = (debug_clock_dr_pre | pin_based_pscan_mode) & io_tck;
assign ctu_debug_shift_dr = debug_shift_dr_pre | pin_based_shift_en;
// to pad_misc
assign next_ctu_misc_mode_ctl = bscan_mode_ctl;
assign next_ctu_misc_hiz_l = bscan_hiz_l;
assign next_ctu_misc_update_dr = bscan_update_dr;
assign next_misc_clock_dr_pre = bscan_clock_dr_pre;
assign next_misc_shift_dr_pre = bscan_shift_dr_pre;
assign ctu_misc_clock_dr = (misc_clock_dr_pre | pin_based_pscan_mode) & io_tck;
assign ctu_misc_shift_dr = misc_shift_dr_pre | pin_based_shift_en;
//********************************************************************
// Shadow Scan
//********************************************************************
assign next_shadow_scan_instr = next_instr_sscan_t0
| next_instr_sscan_t1
| next_instr_sscan_t2
| next_instr_sscan_t3;
// Always snap except in capture_dr state when tck toggles once to
// capture
assign next_ctu_global_snap = next_shadow_scan_instr & ~tap_capture_dr_state;
assign next_spc_sscan_tid[3:0] = { next_instr_sscan_t3,
next_instr_sscan_t2,
next_instr_sscan_t1,
( next_instr_sscan_t0 // always have at least one bit of tid asserted
| ~( next_instr_sscan_t1
| next_instr_sscan_t2
| next_instr_sscan_t3)) };
// ensure one-hot during scan
always @ ( /*AUTOSENSE*/global_shift_enable or spc_sscan_tid) begin
if (global_shift_enable)
ctu_spc_sscan_tid[3:0] = 4'b0001;
else
ctu_spc_sscan_tid[3:0] = spc_sscan_tid[3:0];
end
//----------------------------
// Shadow Scan Config Register
//----------------------------
assign shadow_scan_config_reg_en = shadow_scan_instr
& ( tap_update_ir_state
| tap_pause_dr_state);
always @ ( /*AUTOSENSE*/shadow_scan_config_mask
or shadow_scan_config_reg or shadow_scan_config_reg_en
or tap_instructions or tap_update_ir_state) begin
if (shadow_scan_config_reg_en) begin
if (tap_update_ir_state) // new shadow scan instr
next_shadow_scan_config_reg = tap_instructions[TAP_SSCAN_CFG_HI:TAP_SSCAN_CFG_LO];
else
next_shadow_scan_config_reg = shadow_scan_config_reg & shadow_scan_config_mask;
end
else
next_shadow_scan_config_reg = shadow_scan_config_reg;
end
always @ ( /*AUTOSENSE*/shadow_scan_config_reg) begin
casex (shadow_scan_config_reg[TAP_SSCAN_CFG_WIDTH-1:0])
8'b1???_????: shadow_scan_config_mask = { 1'b0, {TAP_SSCAN_CFG_WIDTH-1{1'b1}} };
8'b01??_????: shadow_scan_config_mask = { {2{1'b0}}, {TAP_SSCAN_CFG_WIDTH-2{1'b1}} };
8'b001?_????: shadow_scan_config_mask = { {3{1'b0}}, {TAP_SSCAN_CFG_WIDTH-3{1'b1}} };
8'b0001_????: shadow_scan_config_mask = { {4{1'b0}}, {TAP_SSCAN_CFG_WIDTH-4{1'b1}} };
8'b0000_1???: shadow_scan_config_mask = { {5{1'b0}}, {TAP_SSCAN_CFG_WIDTH-5{1'b1}} };
8'b0000_01??: shadow_scan_config_mask = { {6{1'b0}}, {TAP_SSCAN_CFG_WIDTH-6{1'b1}} };
8'b0000_001?: shadow_scan_config_mask = { {7{1'b0}}, 1'b1 };
default: shadow_scan_config_mask = {TAP_SSCAN_CFG_WIDTH{1'b0}};
endcase
end
//----------------------------
// shadow scan shift enable
//----------------------------
assign next_spc0_sscan = next_shadow_scan_config_reg[TAP_SSCAN_CFG_WIDTH-1] == 1'b1;
assign next_spc1_sscan = next_shadow_scan_config_reg[TAP_SSCAN_CFG_WIDTH-1:TAP_SSCAN_CFG_WIDTH-2] == 2'b01;
assign next_spc2_sscan = next_shadow_scan_config_reg[TAP_SSCAN_CFG_WIDTH-1:TAP_SSCAN_CFG_WIDTH-3] == 3'b001;
assign next_spc3_sscan = next_shadow_scan_config_reg[TAP_SSCAN_CFG_WIDTH-1:TAP_SSCAN_CFG_WIDTH-4] == 4'b0001;
assign next_spc4_sscan = next_shadow_scan_config_reg[TAP_SSCAN_CFG_WIDTH-1:TAP_SSCAN_CFG_WIDTH-5] == 5'b0000_1;
assign next_spc5_sscan = next_shadow_scan_config_reg[TAP_SSCAN_CFG_WIDTH-1:TAP_SSCAN_CFG_WIDTH-6] == 6'b0000_01;
assign next_spc6_sscan = next_shadow_scan_config_reg[TAP_SSCAN_CFG_WIDTH-1:TAP_SSCAN_CFG_WIDTH-7] == 7'b0000_001;
assign next_spc7_sscan = next_shadow_scan_config_reg[TAP_SSCAN_CFG_WIDTH-1: 0] == 8'b0000_0001;
assign next_pads_sscan = next_shadow_scan_config_reg[TAP_SSCAN_CFG_WIDTH-1: 0] == 8'b0000_0000;
//negedge
assign next_spc0_sscan_se_pre = tap_shift_exit2_dr_state
& (next_instr_scan
| (next_shadow_scan_instr & next_spc0_sscan));
assign next_spc1_sscan_se_pre = tap_shift_exit2_dr_state
& (next_instr_scan
| (next_shadow_scan_instr & next_spc1_sscan));
assign next_spc2_sscan_se_pre = tap_shift_exit2_dr_state
& (next_instr_scan
| (next_shadow_scan_instr & next_spc2_sscan));
assign next_spc3_sscan_se_pre = tap_shift_exit2_dr_state
& (next_instr_scan
| (next_shadow_scan_instr & next_spc3_sscan));
assign next_spc4_sscan_se_pre = tap_shift_exit2_dr_state
& (next_instr_scan
| (next_shadow_scan_instr & next_spc4_sscan));
assign next_spc5_sscan_se_pre = tap_shift_exit2_dr_state
& (next_instr_scan
| (next_shadow_scan_instr & next_spc5_sscan));
assign next_spc6_sscan_se_pre = tap_shift_exit2_dr_state
& (next_instr_scan
| (next_shadow_scan_instr & next_spc6_sscan));
assign next_spc7_sscan_se_pre = tap_shift_exit2_dr_state
& (next_instr_scan
| (next_shadow_scan_instr & next_spc7_sscan));
assign next_pads_sscan_se_pre = tap_shift_exit2_dr_state
& (next_instr_scan
| (next_shadow_scan_instr & next_pads_sscan));
assign ctu_spc0_sscan_se = spc0_sscan_se_pre | pin_based_shift_en;
assign ctu_spc1_sscan_se = spc1_sscan_se_pre | pin_based_shift_en;
assign ctu_spc2_sscan_se = spc2_sscan_se_pre | pin_based_shift_en;
assign ctu_spc3_sscan_se = spc3_sscan_se_pre | pin_based_shift_en;
assign ctu_spc4_sscan_se = spc4_sscan_se_pre | pin_based_shift_en;
assign ctu_spc5_sscan_se = spc5_sscan_se_pre | pin_based_shift_en;
assign ctu_spc6_sscan_se = spc6_sscan_se_pre | pin_based_shift_en;
assign ctu_spc7_sscan_se = spc7_sscan_se_pre | pin_based_shift_en;
//----------------------------
// shadow scan tck
//----------------------------
//negedge
assign next_spc0_tck_pre = ( tap_capture_dr_state
& next_shadow_scan_instr)
| ( tap_shift_dr_state
& (next_instr_normal_scan
| scan_dump_cken_other
| (next_shadow_scan_instr & next_spc0_sscan)) );
assign next_spc1_tck_pre = ( tap_capture_dr_state
& next_shadow_scan_instr)
| ( tap_shift_dr_state
& (next_instr_normal_scan
| scan_dump_cken_other
| (next_shadow_scan_instr & next_spc1_sscan)) );
assign next_spc2_tck_pre = ( tap_capture_dr_state
& next_shadow_scan_instr)
| ( tap_shift_dr_state
& (next_instr_normal_scan
| scan_dump_cken_other
| (next_shadow_scan_instr & next_spc2_sscan)) );
assign next_spc3_tck_pre = ( tap_capture_dr_state
& next_shadow_scan_instr)
| ( tap_shift_dr_state
& (next_instr_normal_scan
| scan_dump_cken_other
| (next_shadow_scan_instr & next_spc3_sscan)) );
assign next_spc4_tck_pre = ( tap_capture_dr_state
& next_shadow_scan_instr)
| ( tap_shift_dr_state
& (next_instr_normal_scan
| scan_dump_cken_other
| (next_shadow_scan_instr & next_spc4_sscan)) );
assign next_spc5_tck_pre = ( tap_capture_dr_state
& next_shadow_scan_instr)
| ( tap_shift_dr_state
& (next_instr_normal_scan
| scan_dump_cken_other
| (next_shadow_scan_instr & next_spc5_sscan)) );
assign next_spc6_tck_pre = ( tap_capture_dr_state
& next_shadow_scan_instr)
| ( tap_shift_dr_state
& (next_instr_normal_scan
| scan_dump_cken_other
| (next_shadow_scan_instr & next_spc6_sscan)) );
assign next_spc7_tck_pre = ( tap_capture_dr_state
& next_shadow_scan_instr)
| ( tap_shift_dr_state
& (next_instr_normal_scan
| scan_dump_cken_other
| (next_shadow_scan_instr & next_spc7_sscan)) );
assign next_pads_tck_pre = ( tap_capture_dr_state
& next_shadow_scan_instr)
| ( tap_shift_dr_state
& (next_instr_normal_scan
| scan_dump_cken_other
| (next_shadow_scan_instr & next_pads_sscan)) );
assign ctu_spc0_tck = io_tck & (spc0_tck_pre | pin_based_pscan_mode);
assign ctu_spc1_tck = io_tck & (spc1_tck_pre | pin_based_pscan_mode);
assign ctu_spc2_tck = io_tck & (spc2_tck_pre | pin_based_pscan_mode);
assign ctu_spc3_tck = io_tck & (spc3_tck_pre | pin_based_pscan_mode);
assign ctu_spc4_tck = io_tck & (spc4_tck_pre | pin_based_pscan_mode);
assign ctu_spc5_tck = io_tck & (spc5_tck_pre | pin_based_pscan_mode);
assign ctu_spc6_tck = io_tck & (spc6_tck_pre | pin_based_pscan_mode);
assign ctu_spc7_tck = io_tck & (spc7_tck_pre | pin_based_pscan_mode);
//----------------------------
// shadow scan out
//----------------------------
always @ ( /*AUTOSENSE*/pads_ctu_bsi or shadow_scan_config_reg
or spc0_ctu_sscan_out or spc1_ctu_sscan_out
or spc2_ctu_sscan_out or spc3_ctu_sscan_out
or spc4_ctu_sscan_out or spc5_ctu_sscan_out
or spc6_ctu_sscan_out or spc7_ctu_sscan_out) begin
casex (shadow_scan_config_reg[TAP_SSCAN_CFG_WIDTH-1:0])
8'b1???_????: shadow_scan_out = spc0_ctu_sscan_out;
8'b01??_????: shadow_scan_out = spc1_ctu_sscan_out;
8'b001?_????: shadow_scan_out = spc2_ctu_sscan_out;
8'b0001_????: shadow_scan_out = spc3_ctu_sscan_out;
8'b0000_1???: shadow_scan_out = spc4_ctu_sscan_out;
8'b0000_01??: shadow_scan_out = spc5_ctu_sscan_out;
8'b0000_001?: shadow_scan_out = spc6_ctu_sscan_out;
8'b0000_0001: shadow_scan_out = spc7_ctu_sscan_out;
default: shadow_scan_out = pads_ctu_bsi;
endcase
end
// Update-DR: the contents of the shadow chain are latched in the io registers
assign next_ctu_pads_sscan_update = next_shadow_scan_instr
& next_shadow_scan_config_reg == 8'd0
& (tap_update_dr_state
& next_tap_instructions[TAP_SSCAN_UPDATE]);
//********************************************************************
// MBIST
//********************************************************************
// Tell mbist control blk to start MBIST
// - once mbist is kicked off, does not stop until done, unless receive an abort
// - if bist sm has not completed previous bist, new bist instruction will be ignored
assign next_jtag_bist_serial = instr_mbist_serial
& (tap_update_ir_state_d1 | tap_update_ir_state_d2);
assign next_jtag_bist_parallel = instr_mbist_parallel
& (tap_update_ir_state_d1 | tap_update_ir_state_d2);
always @ ( /*AUTOSENSE*/instr_mbist_parallel or instr_mbist_serial
or jtag_bist_active or tap_instructions
or tap_update_ir_state_d1) begin
if ( (instr_mbist_serial & tap_update_ir_state_d1)
| (instr_mbist_parallel & tap_update_ir_state_d1) )
next_jtag_bist_active = tap_instructions[TAP_MBIST_ACTIVE_HI:TAP_MBIST_ACTIVE_LO];
else
next_jtag_bist_active = jtag_bist_active;
end
// MBIST Abort
assign next_jtag_bist_abort = (instr_mbist_abort & tap_update_ir_state_d1)
| (jtag_bist_abort & ~bist_jtag_abort_done);
// MBIST Result Register
assign bist_result_reg_load = instr_mbist_result & tap_capture_dr_state;
assign bist_result_reg_shift = instr_mbist_result & tap_shift_dr_state;
always @ ( /*AUTOSENSE*/bist_jtag_result or bist_result_reg
or bist_result_reg_load or bist_result_reg_shift or io_tdi) begin
if (bist_result_reg_load)
next_bist_result_reg = bist_jtag_result;
else begin
if (bist_result_reg_shift)
next_bist_result_reg = { bist_result_reg[(`CTU_BIST_CNT*2)-2:0], io_tdi };
else
next_bist_result_reg = bist_result_reg;
end
end
//********************************************************************
// Efuse
//********************************************************************
//------------------------
// Shift Interface
//------------------------
assign next_ctu_efc_capturedr = tap_capture_dr_state
& ( next_instr_efc_bypass_data
| next_instr_efc_bypass
| next_instr_efc_read);
assign next_ctu_efc_shiftdr = tap_shift_dr_state
& ( next_instr_efc_bypass_data
| next_instr_efc_read);
assign next_ctu_efc_updatedr = tap_update_dr_state
& ( next_instr_efc_bypass_data
| next_instr_efc_bypass
| next_instr_efc_read);
assign next_efc_tck_pre = next_ctu_efc_capturedr
| next_ctu_efc_shiftdr
| ( tap_shift_dr_state
& (next_instr_normal_scan | scan_dump_cken_other));
assign ctu_efc_tck = io_tck
& ( efc_tck_pre
| pin_based_pscan_mode);
assign ctu_efc_data_in = io_tdi;
//------------------------
// R/W Interface
//------------------------
assign next_ctu_efc_fuse_bypass = next_instr_efc_bypass;
assign next_ctu_efc_read_en = next_instr_efc_read;
// row address
assign efc_rowaddr_shift = instr_efc_row_addr & tap_shift_dr_state;
always @ ( /*AUTOSENSE*/efc_rowaddr or efc_rowaddr_shift or io_tdi) begin
if (efc_rowaddr_shift)
next_efc_rowaddr[6:0] = { efc_rowaddr[5:0], io_tdi };
else
next_efc_rowaddr[6:0] = efc_rowaddr[6:0];
end
assign next_ctu_efc_rowaddr = efc_rowaddr; //negedge
// column address
assign efc_coladdr_shift = instr_efc_col_addr & tap_shift_dr_state;
always @ ( /*AUTOSENSE*/efc_coladdr or efc_coladdr_shift or io_tdi) begin
if (efc_coladdr_shift)
next_efc_coladdr[4:0] = { efc_coladdr[3:0], io_tdi };
else
next_efc_coladdr[4:0] = efc_coladdr[4:0];
end
assign next_ctu_efc_coladdr = efc_coladdr; //negedge
// read mode
assign efc_read_mode_shift = instr_efc_read_mode & tap_shift_dr_state;
always @ ( /*AUTOSENSE*/efc_read_mode or efc_read_mode_shift or io_tdi) begin
if (efc_read_mode_shift)
next_efc_read_mode[2:0] = { efc_read_mode[1:0], io_tdi };
else
next_efc_read_mode[2:0] = efc_read_mode[2:0];
end
assign next_ctu_efc_read_mode = efc_read_mode; //negedge
//------------------------
// Destination Sample
//------------------------
// negedge
assign next_ctu_efc_dest_sample = instr_efc_dest_sample & tap_update_ir_state_d1;
//********************************************************************
// Clock Control
//********************************************************************
//------------------------
// clk_sel
//------------------------
//default value of ctu_sel_* at reset is 3'b111
// value of ctu_sel* is held until next (tap_instructions[4:0] == `TAP_CLK_SEL)
assign clk_sel_cpu = next_tap_instructions[TAP_SCAN_CLK_SEL_CPU_HI :TAP_SCAN_CLK_SEL_CPU_LO];
assign clk_sel_dram = next_tap_instructions[TAP_SCAN_CLK_SEL_DRAM_HI:TAP_SCAN_CLK_SEL_DRAM_LO];
assign clk_sel_jbus = next_tap_instructions[TAP_SCAN_CLK_SEL_JBUS_HI:TAP_SCAN_CLK_SEL_JBUS_LO];
assign sel_cpu[0] = clk_sel_cpu[0]; // normal
assign sel_cpu[1] = ~clk_sel_cpu[0] & clk_sel_cpu[1] & clk_sel_cpu[2]; // io_tck mode
assign sel_cpu[2] = ~clk_sel_cpu[0] & clk_sel_cpu[1] & ~clk_sel_cpu[2]; // pll_bypass
assign sel_dram[0] = clk_sel_dram[0]; // normal
assign sel_dram[1] = ~clk_sel_dram[0] & clk_sel_dram[1] & clk_sel_dram[2]; // io_tck mode
assign sel_dram[2] = ~clk_sel_dram[0] & clk_sel_dram[1] & ~clk_sel_dram[2]; // pll_bypass
assign sel_jbus[0] = clk_sel_jbus[0]; // normal
assign sel_jbus[1] = ~clk_sel_jbus[0] & clk_sel_jbus[1] & clk_sel_jbus[2]; // io_tck mode
assign sel_jbus[2] = ~clk_sel_jbus[0] & clk_sel_jbus[1] & ~clk_sel_jbus[2]; // pll_bypass
// negedge
always @ ( /*AUTOSENSE*/instr_clk_sel or instr_scan or pll_bypass_tap
or sel_cpu or sel_cpu_ff or sel_dram or sel_dram_ff
or sel_jbus or sel_jbus_ff or tap_update_ir_state_d1) begin
if (pll_bypass_tap) begin
next_sel_cpu_ff = 3'b100; // pll_bypass mode
next_sel_dram_ff = 3'b001; // normal
next_sel_jbus_ff = 3'b100; // pll_bypass mode
end
else if (tap_update_ir_state_d1 & instr_scan) begin // auto clock sel for internal scan instructions
next_sel_cpu_ff[2:0] = 3'b010; // tck mode
next_sel_dram_ff[2:0] = 3'b010;
next_sel_jbus_ff[2:0] = 3'b010;
end
else if (tap_update_ir_state_d1 & instr_clk_sel) begin // manual clock sel through tap
next_sel_cpu_ff[2:0] = sel_cpu[2:0];
next_sel_dram_ff[2:0] = sel_dram[2:0];
next_sel_jbus_ff[2:0] = sel_jbus[2:0];
end
else begin
next_sel_cpu_ff[2:0] = sel_cpu_ff[2:0];
next_sel_dram_ff[2:0] = sel_dram_ff[2:0];
next_sel_jbus_ff[2:0] = sel_jbus_ff[2:0];
end
end
//always @ ( /*AUTOSENSE*/pin_based_pll_bypass or pin_based_pscan_mode
// or sel_cpu_ff or sel_dram_ff or sel_jbus_ff) begin
// if (pin_based_pscan_mode) begin
// ctu_sel_cpu = 3'b010; // tck mode
// ctu_sel_dram = 3'b010;
// ctu_sel_jbus = 3'b010;
// end
// else if (pin_based_pll_bypass) begin
// ctu_sel_cpu = 3'b100; // pll_bypass mode
// ctu_sel_dram = 3'b001; // normal
// ctu_sel_jbus = 3'b100; // pll_bypass mode
// end
// else begin
// ctu_sel_cpu = sel_cpu_ff;
// ctu_sel_dram = sel_dram_ff;
// ctu_sel_jbus = sel_jbus_ff;
// end
//end
//
//assign ctu_sel_cpu[0] = ~( test_mode_pin // 0->0->ff
// & (~io_trst_l | pll_bypass_pin))
// & sel_cpu_ff[0];
//assign ctu_sel_cpu[1] = (test_mode_pin & ~io_trst_l) // 1->0->ff
// | ( ~(test_mode_pin & pll_bypass_pin)
// & sel_cpu_ff[1]);
//assign ctu_sel_cpu[2] = ~(test_mode_pin & ~io_trst_l) // 0->1->ff
// & ( (test_mode_pin & pll_bypass_pin)
// | sel_cpu_ff[2]);
//
//ctu_sel_dram[0] = 0->1->ff
//ctu_sel_dram[1] = 1->0->ff
//ctu_sel_dram[2] = 0->0->ff
//
//ctu_sel_jbus[0] = 0->0->ff
//ctu_sel_jbus[1] = 1->0->ff
//ctu_sel_jbus[2] = 0->1->ff
ctu_inv u_inv_trst(.z(trst), .a(io_trst_l));
/* ctu_jtag_clk_sel_0_0_ff AUTO_TEMPLATE (
.sel_clk (ctu_sel_cpu[@]),
.sel_ff(sel_cpu_ff[@]),); */
/* ctu_jtag_clk_sel_1_0_ff AUTO_TEMPLATE (
.sel_clk (ctu_sel_cpu[@]),
.sel_ff(sel_cpu_ff[@]),); */
/* ctu_jtag_clk_sel_0_1_ff AUTO_TEMPLATE (
.sel_clk (ctu_sel_cpu[@]),
.sel_ff(sel_cpu_ff[@]),); */
ctu_jtag_clk_sel_0_0_ff u_ctu_sel_cpu0 (/*AUTOINST*/
// Outputs
.sel_clk(ctu_sel_cpu[0]), // Templated
// Inputs
.test_mode_pin(test_mode_pin),
.trst(trst),
.pll_bypass_pin(pll_bypass_pin),
.sel_ff(sel_cpu_ff[0])); // Templated
ctu_jtag_clk_sel_1_0_ff u_ctu_sel_cpu1 (/*AUTOINST*/
// Outputs
.sel_clk(ctu_sel_cpu[1]), // Templated
// Inputs
.test_mode_pin(test_mode_pin),
.trst(trst),
.pll_bypass_pin(pll_bypass_pin),
.sel_ff(sel_cpu_ff[1])); // Templated
ctu_jtag_clk_sel_0_1_ff u_ctu_sel_cpu2 (/*AUTOINST*/
// Outputs
.sel_clk(ctu_sel_cpu[2]), // Templated
// Inputs
.test_mode_pin(test_mode_pin),
.trst(trst),
.pll_bypass_pin(pll_bypass_pin),
.sel_ff(sel_cpu_ff[2])); // Templated
/* ctu_jtag_clk_sel_0_0_ff AUTO_TEMPLATE (
.sel_clk (ctu_sel_dram[@]),
.sel_ff(sel_dram_ff[@]),); */
/* ctu_jtag_clk_sel_1_0_ff AUTO_TEMPLATE (
.sel_clk (ctu_sel_dram[@]),
.sel_ff(sel_dram_ff[@]),); */
/* ctu_jtag_clk_sel_0_1_ff AUTO_TEMPLATE (
.sel_clk (ctu_sel_dram[@]),
.sel_ff(sel_dram_ff[@]),); */
ctu_jtag_clk_sel_0_1_ff u_ctu_sel_dram0 (/*AUTOINST*/
// Outputs
.sel_clk(ctu_sel_dram[0]), // Templated
// Inputs
.test_mode_pin(test_mode_pin),
.trst(trst),
.pll_bypass_pin(pll_bypass_pin),
.sel_ff(sel_dram_ff[0])); // Templated
ctu_jtag_clk_sel_1_0_ff u_ctu_sel_dram1 (/*AUTOINST*/
// Outputs
.sel_clk(ctu_sel_dram[1]), // Templated
// Inputs
.test_mode_pin(test_mode_pin),
.trst(trst),
.pll_bypass_pin(pll_bypass_pin),
.sel_ff(sel_dram_ff[1])); // Templated
ctu_jtag_clk_sel_0_0_ff u_ctu_sel_dram2 (/*AUTOINST*/
// Outputs
.sel_clk(ctu_sel_dram[2]), // Templated
// Inputs
.test_mode_pin(test_mode_pin),
.trst(trst),
.pll_bypass_pin(pll_bypass_pin),
.sel_ff(sel_dram_ff[2])); // Templated
/* ctu_jtag_clk_sel_0_0_ff AUTO_TEMPLATE (
.sel_clk (ctu_sel_jbus[@]),
.sel_ff(sel_jbus_ff[@]),); */
/* ctu_jtag_clk_sel_1_0_ff AUTO_TEMPLATE (
.sel_clk (ctu_sel_jbus[@]),
.sel_ff(sel_jbus_ff[@]),); */
/* ctu_jtag_clk_sel_0_1_ff AUTO_TEMPLATE (
.sel_clk (ctu_sel_jbus[@]),
.sel_ff(sel_jbus_ff[@]),); */
ctu_jtag_clk_sel_0_0_ff u_ctu_sel_jbus0 (/*AUTOINST*/
// Outputs
.sel_clk(ctu_sel_jbus[0]), // Templated
// Inputs
.test_mode_pin(test_mode_pin),
.trst(trst),
.pll_bypass_pin(pll_bypass_pin),
.sel_ff(sel_jbus_ff[0])); // Templated
ctu_jtag_clk_sel_1_0_ff u_ctu_sel_jbus1 (/*AUTOINST*/
// Outputs
.sel_clk(ctu_sel_jbus[1]), // Templated
// Inputs
.test_mode_pin(test_mode_pin),
.trst(trst),
.pll_bypass_pin(pll_bypass_pin),
.sel_ff(sel_jbus_ff[1])); // Templated
ctu_jtag_clk_sel_0_1_ff u_ctu_sel_jbus2 (/*AUTOINST*/
// Outputs
.sel_clk(ctu_sel_jbus[2]), // Templated
// Inputs
.test_mode_pin(test_mode_pin),
.trst(trst),
.pll_bypass_pin(pll_bypass_pin),
.sel_ff(sel_jbus_ff[2])); // Templated
//------------------------
// scan dump
// - stagger cken and delay shift_enable to compensate for cken repeater fifo not
// balanced on top level &
//------------------------
assign next_cken_dram_wait = JTAG_CKEN_DRAM_WAIT;
assign next_cken_jbus_wait = JTAG_CKEN_JBUS_WAIT;
assign next_cken_other_wait = JTAG_CKEN_OTHER_WAIT;
assign scan_dump_cken_cmp = instr_scan_dump & ~nstep_mode;
assign scan_dump_cken_dram = scan_dump_cken_cmp & (scan_dump_shiftdr_cnt >= cken_dram_wait);
assign scan_dump_cken_jbus = scan_dump_cken_cmp & (scan_dump_shiftdr_cnt >= cken_jbus_wait);
assign scan_dump_cken_other = scan_dump_cken_cmp & (scan_dump_shiftdr_cnt >= cken_other_wait);
// negedge
assign inc_scan_dump_shiftdr_cnt = instr_scan_dump & tap_shift_dr_state;
always @ ( /*AUTOSENSE*/inc_scan_dump_shiftdr_cnt or instr_scan_dump
or scan_dump_shiftdr_cnt or tap_update_ir_state_d1) begin
if (tap_update_ir_state_d1 & instr_scan_dump)
next_scan_dump_shiftdr_cnt = {JTAG_SDR_CNT_WIDTH{1'b0}};
else begin
if (inc_scan_dump_shiftdr_cnt & (~&scan_dump_shiftdr_cnt)) // do not overflow counter
next_scan_dump_shiftdr_cnt = scan_dump_shiftdr_cnt +1'b1;
else
next_scan_dump_shiftdr_cnt = scan_dump_shiftdr_cnt;
end
end
//------------------------
// force_cken
//------------------------
assign normal_force_cken = ~nstep_mode
& ( tap_instructions[TAP_CKEN_BIT]
& ( instr_scan_parallel
| instr_scan_serial
| instr_scan_mtest ));
assign next_jtag_clsp_force_cken_cmp = normal_force_cken | scan_dump_cken_cmp;
assign next_jtag_clsp_force_cken_dram = normal_force_cken | scan_dump_cken_dram;
assign next_jtag_clsp_force_cken_jbus = normal_force_cken | scan_dump_cken_jbus;
//------------------------
// stop_id
//------------------------
// clock stop sequence
assign jtag_clsp_stop_id_vld = instr_clk_stop_id
& (tap_update_ir_state_d1 | tap_update_ir_state_d2); //sync to jbus
assign jtag_clsp_stop_id[5:0] = tap_instructions[TAP_CLK_STOP_ID_HI:TAP_CLK_STOP_ID_LO];
//------------------------
// nstep
//------------------------
assign jtag_nstep_vld = instr_scan_nstep
& (tap_update_ir_state_d1 | tap_update_ir_state_d2); //sync to
assign jtag_nstep_domain = tap_instructions[TAP_SCAN_NSTEP_DOM_HI:TAP_SCAN_NSTEP_DOM_LO];
assign jtag_nstep_count = tap_instructions[TAP_SCAN_NSTEP_CNT_HI:TAP_SCAN_NSTEP_CNT_LO];
// TAP_SCAN_NSTEP sets bit, and non-scan instruction clears bit
always @ ( /*AUTOSENSE*/instr_scan or instr_scan_bypass_en
or instr_scan_nstep or jtag_nstep_vld or nstep_mode) begin
if (jtag_nstep_vld)
next_nstep_mode = 1'b1;
else if (~instr_scan & ~instr_scan_nstep & ~instr_scan_bypass_en)
next_nstep_mode = 1'b0;
else
next_nstep_mode = nstep_mode;
end
assign next_dft_clsp_nstep_capture_l = ~(tap_capture_dr_state & next_nstep_mode);
//------------------------
// sel_tck2
//------------------------
assign next_sel_tck2_pre = ~nstep_mode
& ( instr_scan_parallel
| (instr_scan_mtest & tap_instructions[TAP_SCAN_MODE_BIT] == TAP_SCAN_MODE_PARALLEL));
assign jtag_clsp_sel_tck2 = sel_tck2_pre
| pin_based_pscan_mode;
//********************************************************************
// PLL Control
//********************************************************************
//-----------------------
// PLL_BYPASS
//-----------------------
assign toggle_pll_bypass_tap = instr_pll_bypass & tap_update_ir_state_d1;
assign next_pll_bypass_tap = toggle_pll_bypass_tap ^ pll_bypass_tap;
// pll_bypass_pin signal is gated by test_mode_pin
assign pll_bypass = pin_based_pll_bypass
| (~pin_based_pscan_mode & pll_bypass_tap)
| jtag_clsp_sel_tck2;
//*******************************************************************************
// Misc Muxes
// - muxes placed here for a lack of a better place
//*******************************************************************************
// Scan
// bug #5695
assign serial_scan = instr_scan_serial
| ( tap_instructions[TAP_SCAN_MODE_BIT] == TAP_SCAN_MODE_SERIAL
& ( tap_instructions[TAP_CMD_HI:TAP_CMD_LO] == `TAP_SCAN_DUMP // 6'h26
| tap_instructions[TAP_CMD_HI:TAP_CMD_LO] == `TAP_SCAN_MTEST_LONG // 6'h22
| tap_instructions[TAP_CMD_HI:TAP_CMD_LO] == `TAP_SCAN_MTEST_SHORT)); // 6'h23
always @ ( /*AUTOSENSE*/io_tdi or pin_based_pscan_mode
or sctag2_ctu_serial_scan_in or serial_scan) begin
// if (instr_scan_serial & ~pin_based_pscan_mode)
if (serial_scan & ~pin_based_pscan_mode) // bug #5695
ctu_fpu_so = sctag2_ctu_serial_scan_in;
else
ctu_fpu_so = io_tdi;
end
// Random Number Generator
always @ ( /*AUTOSENSE*/afi_rng_ctl or afi_tsr_mode or jbus_rst_l
or test_mode_pin) begin
if (test_mode_pin) begin
dft_rng_vctrl = afi_rng_ctl[2:0];
dft_rng_rst_l = afi_tsr_mode;
end
else begin
dft_rng_vctrl = 3'b111;
dft_rng_rst_l = jbus_rst_l;
end
end
// Temperature Sensor Regulator Divider
always @ ( /*AUTOSENSE*/afi_tsr_div or afi_tsr_mode or afi_tsr_tsel
or test_mode_pin) begin
if (test_mode_pin) begin
dft_tsr_div = afi_tsr_div[9:1];
dft_tsr_tsel = afi_tsr_tsel[7:0];
dft_tsr_reset_l = afi_tsr_mode;
end
else begin
dft_tsr_div = 9'b0_0001_1001;
dft_tsr_tsel = 8'd0;
dft_tsr_reset_l = 1'b0;
end
end
// PLL
always @ ( /*AUTOSENSE*/afi_pll_char_mode or afi_pll_clamp_fltr
or afi_pll_div2 or test_mode_pin) begin
if (test_mode_pin & afi_pll_char_mode) begin
dft_pll_div2 = afi_pll_div2[5:0];
dft_pll_clamp_fltr = afi_pll_clamp_fltr;
end
else begin
dft_pll_div2 = 6'd0;
dft_pll_clamp_fltr = 1'b0;
end
end
always @ ( /*AUTOSENSE*/afi_pll_char_mode or afi_pll_trst_l
or pin_based_pscan_mode or pll_reset_ref_l or test_mode_pin) begin
if (pin_based_pscan_mode)
dft_pll_arst_l = 1'b0;
else if (test_mode_pin & afi_pll_char_mode)
dft_pll_arst_l = afi_pll_trst_l;
else
dft_pll_arst_l = pll_reset_ref_l;
end
assign dft_pll_testmode = test_mode_pin & afi_pll_char_mode;
//*******************************************************************************
// Async Reset and Set DFFRL/DFFSL Instantiations
//*******************************************************************************
//--------------
// posedge flops
//--------------
dffrl_async_ns u_dffrl_async_creg_rdrtrn_vld
( .din (next_creg_rdrtrn_vld),
.clk (io_tck),
.rst_l (tap_rst_l),
.q (creg_rdrtrn_vld)
);
dffrl_async_ns #(64) u_dffrl_async_scratch_reg
(.din (next_scratch_reg),
.clk (io_tck),
.rst_l (tap_rst_l),
.q (scratch_reg)
);
dffrl_async_ns u_dffrl_async_jtag_bist_serial
( .din (next_jtag_bist_serial),
.rst_l (tap_rst_l),
.clk (io_tck),
.q (jtag_bist_serial)
);
dffrl_async_ns u_dffrl_async_jtag_bist_parallel
( .din (next_jtag_bist_parallel),
.rst_l (tap_rst_l),
.clk (io_tck),
.q (jtag_bist_parallel)
);
dffrl_async_ns u_dffrl_async_jtag_bist_abort
( .din (next_jtag_bist_abort),
.rst_l (tap_rst_l),
.clk (io_tck),
.q (jtag_bist_abort)
);
dffrl_async_ns #(TAP_MBIST_ACTIVE_WIDTH) u_dffrl_async_jtag_bist_active
( .din (next_jtag_bist_active),
.rst_l (tap_rst_l),
.clk (io_tck),
.q (jtag_bist_active)
);
dffrl_async_ns #(TAP_SSCAN_CFG_WIDTH) u_dffrl_async_shadow_scan_config_reg
( .din (next_shadow_scan_config_reg),
.clk (io_tck),
.rst_l (tap_rst_l),
.q (shadow_scan_config_reg)
);
dffrl_async_ns #(1) u_dffrl_async_jtag_creg_addr_en
( .din (next_jtag_creg_addr_en),
.clk (io_tck),
.rst_l (tap_rst_l),
.q (jtag_creg_addr_en)
);
dffrl_async_ns #(1) u_dffrl_async_jtag_creg_wr_en
( .din (next_jtag_creg_wr_en),
.clk (io_tck),
.rst_l (tap_rst_l),
.q (jtag_creg_wr_en)
);
dffrl_async_ns #(1) u_dffrl_async_jtag_creg_rd_en
( .din (next_jtag_creg_rd_en),
.clk (io_tck),
.rst_l (tap_rst_l),
.q (jtag_creg_rd_en)
);
dffrl_async_ns #(1) u_dffrl_async_jtag_creg_data_en
( .din (next_jtag_creg_data_en),
.clk (io_tck),
.rst_l (tap_rst_l),
.q (jtag_creg_data_en)
);
//--------------
// negedge flops
//--------------
dffrl_async_ns u_dffrl_async_global_scan_bypass_en
( .din (next_global_scan_bypass_en),
.clk (tck_l),
.rst_l (tap_rst_l),
// .q (global_scan_bypass_en));
.q (global_scan_bypass_en_pre)); // bug #5483
dffrl_async_ns u_dffrl_async_pscan_select_pre
( .din (next_pscan_select_pre),
.clk (tck_l),
.rst_l (tap_rst_l),
.q (pscan_select_pre));
// reset clocks in normal mode (bit 0 asserted)
dffsl_async_ns #(1) u_dffsl_async_sel_cpu_ff0
( .din (next_sel_cpu_ff[0]),
.clk (tck_l),
.set_l (tap_rst_l),
.q (sel_cpu_ff[0])
);
dffrl_async_ns #(2) u_dffrl_async_sel_cpu_ff_1to2
( .din (next_sel_cpu_ff[2:1]),
.clk (tck_l),
.rst_l (tap_rst_l),
.q (sel_cpu_ff[2:1])
);
dffsl_async_ns #(1) u_dffsl_async_sel_dram_ff0
( .din (next_sel_dram_ff[0]),
.clk (tck_l),
.set_l (tap_rst_l),
.q (sel_dram_ff[0])
);
dffrl_async_ns #(2) u_dffrl_async_sel_dram_ff_1to2
( .din (next_sel_dram_ff[2:1]),
.clk (tck_l),
.rst_l (tap_rst_l),
.q (sel_dram_ff[2:1])
);
dffsl_async_ns #(1) u_dffsl_async_sel_jbus_ff0
( .din (next_sel_jbus_ff[0]),
.clk (tck_l),
.set_l (tap_rst_l),
.q (sel_jbus_ff[0])
);
dffrl_async_ns #(2) u_dffrl_async_sel_jbus_ff_1to2
( .din (next_sel_jbus_ff[2:1]),
.clk (tck_l),
.rst_l (tap_rst_l),
.q (sel_jbus_ff[2:1])
);
// boundary scan
dffrl_async_ns #(1) u_dffrl_async_bscan_enable
( .din (next_bscan_enable),
.clk (tck_l),
.rst_l (tap_rst_l),
.q (bscan_enable)
);
dffrl_async_ns #(1) u_dffrl_async_ctu_ddr0_mode_ctl
( .din (next_ctu_ddr0_mode_ctl),
.clk (tck_l),
.rst_l (tap_rst_l),
.q (ctu_ddr0_mode_ctl)
);
dffrl_async_ns #(1) u_dffrl_async_ctu_ddr1_mode_ctl
( .din (next_ctu_ddr1_mode_ctl),
.clk (tck_l),
.rst_l (tap_rst_l),
.q (ctu_ddr1_mode_ctl)
);
dffrl_async_ns #(1) u_dffrl_async_ctu_ddr2_mode_ctl
( .din (next_ctu_ddr2_mode_ctl),
.clk (tck_l),
.rst_l (tap_rst_l),
.q (ctu_ddr2_mode_ctl)
);
dffrl_async_ns #(1) u_dffrl_async_ctu_ddr3_mode_ctl
( .din (next_ctu_ddr3_mode_ctl),
.clk (tck_l),
.rst_l (tap_rst_l),
.q (ctu_ddr3_mode_ctl)
);
dffrl_async_ns #(1) u_dffrl_async_ctu_jbusl_mode_ctl
( .din (next_ctu_jbusl_mode_ctl),
.clk (tck_l),
.rst_l (tap_rst_l),
.q (ctu_jbusl_mode_ctl)
);
dffrl_async_ns #(1) u_dffrl_async_ctu_jbusr_mode_ctl
( .din (next_ctu_jbusr_mode_ctl),
.clk (tck_l),
.rst_l (tap_rst_l),
.q (ctu_jbusr_mode_ctl)
);
dffrl_async_ns #(1) u_dffrl_async_ctu_debug_mode_ctl
( .din (next_ctu_debug_mode_ctl),
.clk (tck_l),
.rst_l (tap_rst_l),
.q (ctu_debug_mode_ctl)
);
dffrl_async_ns #(1) u_dffrl_async_ctu_misc_mode_ctl
( .din (next_ctu_misc_mode_ctl),
.clk (tck_l),
.rst_l (tap_rst_l),
.q (ctu_misc_mode_ctl)
);
dffsl_async_ns #(1) u_dffsl_async_ctu_ddr0_hiz_l
( .din (next_ctu_ddr0_hiz_l),
.clk (tck_l),
.set_l (tap_rst_l),
.q (ctu_ddr0_hiz_l)
);
dffsl_async_ns #(1) u_dffsl_async_ctu_ddr1_hiz_l
( .din (next_ctu_ddr1_hiz_l),
.clk (tck_l),
.set_l (tap_rst_l),
.q (ctu_ddr1_hiz_l)
);
dffsl_async_ns #(1) u_dffsl_async_ctu_ddr2_hiz_l
( .din (next_ctu_ddr2_hiz_l),
.clk (tck_l),
.set_l (tap_rst_l),
.q (ctu_ddr2_hiz_l)
);
dffsl_async_ns #(1) u_dffsl_async_ctu_ddr3_hiz_l
( .din (next_ctu_ddr3_hiz_l),
.clk (tck_l),
.set_l (tap_rst_l),
.q (ctu_ddr3_hiz_l)
);
dffsl_async_ns #(1) u_dffsl_async_ctu_jbusl_hiz_l
( .din (next_ctu_jbusl_hiz_l),
.clk (tck_l),
.set_l (tap_rst_l),
.q (ctu_jbusl_hiz_l)
);
dffsl_async_ns #(1) u_dffsl_async_ctu_jbusr_hiz_l
( .din (next_ctu_jbusr_hiz_l),
.clk (tck_l),
.set_l (tap_rst_l),
.q (ctu_jbusr_hiz_l)
);
dffsl_async_ns #(1) u_dffsl_async_ctu_debug_hiz_l
( .din (next_ctu_debug_hiz_l),
.clk (tck_l),
.set_l (tap_rst_l),
.q (ctu_debug_hiz_l)
);
dffsl_async_ns #(1) u_dffsl_async_ctu_misc_hiz_l
( .din (next_ctu_misc_hiz_l),
.clk (tck_l),
.set_l (tap_rst_l),
.q (ctu_misc_hiz_l)
);
dffrl_async_ns #(1) u_dffrl_async_ctu_ddr0_update_dr
( .din (next_ctu_ddr0_update_dr),
.clk (tck_l),
.rst_l (tap_rst_l),
.q (ctu_ddr0_update_dr)
);
dffrl_async_ns #(1) u_dffrl_async_ctu_ddr1_update_dr
( .din (next_ctu_ddr1_update_dr),
.clk (tck_l),
.rst_l (tap_rst_l),
.q (ctu_ddr1_update_dr)
);
dffrl_async_ns #(1) u_dffrl_async_ctu_ddr2_update_dr
( .din (next_ctu_ddr2_update_dr),
.clk (tck_l),
.rst_l (tap_rst_l),
.q (ctu_ddr2_update_dr)
);
dffrl_async_ns #(1) u_dffrl_async_ctu_ddr3_update_dr
( .din (next_ctu_ddr3_update_dr),
.clk (tck_l),
.rst_l (tap_rst_l),
.q (ctu_ddr3_update_dr)
);
dffrl_async_ns #(1) u_dffrl_async_ctu_jbusl_update_dr
( .din (next_ctu_jbusl_update_dr),
.clk (tck_l),
.rst_l (tap_rst_l),
.q (ctu_jbusl_update_dr)
);
dffrl_async_ns #(1) u_dffrl_async_ctu_jbusr_update_dr
( .din (next_ctu_jbusr_update_dr),
.clk (tck_l),
.rst_l (tap_rst_l),
.q (ctu_jbusr_update_dr)
);
dffrl_async_ns #(1) u_dffrl_async_ctu_debug_update_dr
( .din (next_ctu_debug_update_dr),
.clk (tck_l),
.rst_l (tap_rst_l),
.q (ctu_debug_update_dr)
);
dffrl_async_ns #(1) u_dffrl_async_ctu_misc_update_dr
( .din (next_ctu_misc_update_dr),
.clk (tck_l),
.rst_l (tap_rst_l),
.q (ctu_misc_update_dr)
);
dffrl_async_ns #(1) u_dffrl_async_ddr0_clock_dr_pre
( .din (next_ddr0_clock_dr_pre),
.clk (tck_l),
.rst_l (tap_rst_l),
.q (ddr0_clock_dr_pre)
);
dffrl_async_ns #(1) u_dffrl_async_ddr1_clock_dr_pre
( .din (next_ddr1_clock_dr_pre),
.clk (tck_l),
.rst_l (tap_rst_l),
.q (ddr1_clock_dr_pre)
);
dffrl_async_ns #(1) u_dffrl_async_ddr2_clock_dr_pre
( .din (next_ddr2_clock_dr_pre),
.clk (tck_l),
.rst_l (tap_rst_l),
.q (ddr2_clock_dr_pre)
);
dffrl_async_ns #(1) u_dffrl_async_ddr3_clock_dr_pre
( .din (next_ddr3_clock_dr_pre),
.clk (tck_l),
.rst_l (tap_rst_l),
.q (ddr3_clock_dr_pre)
);
dffrl_async_ns #(1) u_dffrl_async_jbusl_clock_dr_pre
( .din (next_jbusl_clock_dr_pre),
.clk (tck_l),
.rst_l (tap_rst_l),
.q (jbusl_clock_dr_pre)
);
dffrl_async_ns #(1) u_dffrl_async_jbusr_clock_dr_pre
( .din (next_jbusr_clock_dr_pre),
.clk (tck_l),
.rst_l (tap_rst_l),
.q (jbusr_clock_dr_pre)
);
dffrl_async_ns #(1) u_dffrl_async_debug_clock_dr_pre
( .din (next_debug_clock_dr_pre),
.clk (tck_l),
.rst_l (tap_rst_l),
.q (debug_clock_dr_pre)
);
dffrl_async_ns #(1) u_dffrl_async_misc_clock_dr_pre
( .din (next_misc_clock_dr_pre),
.clk (tck_l),
.rst_l (tap_rst_l),
.q (misc_clock_dr_pre)
);
dffrl_async_ns #(1) u_dffrl_async_ddr0_shift_dr_pre
( .din (next_ddr0_shift_dr_pre),
.clk (tck_l),
.rst_l (tap_rst_l),
.q (ddr0_shift_dr_pre)
);
dffrl_async_ns #(1) u_dffrl_async_ddr1_shift_dr_pre
( .din (next_ddr1_shift_dr_pre),
.clk (tck_l),
.rst_l (tap_rst_l),
.q (ddr1_shift_dr_pre)
);
dffrl_async_ns #(1) u_dffrl_async_ddr2_shift_dr_pre
( .din (next_ddr2_shift_dr_pre),
.clk (tck_l),
.rst_l (tap_rst_l),
.q (ddr2_shift_dr_pre)
);
dffrl_async_ns #(1) u_dffrl_async_ddr3_shift_dr_pre
( .din (next_ddr3_shift_dr_pre),
.clk (tck_l),
.rst_l (tap_rst_l),
.q (ddr3_shift_dr_pre)
);
dffrl_async_ns #(1) u_dffrl_async_jbusl_shift_dr_pre
( .din (next_jbusl_shift_dr_pre),
.clk (tck_l),
.rst_l (tap_rst_l),
.q (jbusl_shift_dr_pre)
);
dffrl_async_ns #(1) u_dffrl_async_jbusr_shift_dr_pre
( .din (next_jbusr_shift_dr_pre),
.clk (tck_l),
.rst_l (tap_rst_l),
.q (jbusr_shift_dr_pre)
);
dffrl_async_ns #(1) u_dffrl_async_debug_shift_dr_pre
( .din (next_debug_shift_dr_pre),
.clk (tck_l),
.rst_l (tap_rst_l),
.q (debug_shift_dr_pre)
);
dffrl_async_ns #(1) u_dffrl_async_misc_shift_dr_pre
( .din (next_misc_shift_dr_pre),
.clk (tck_l),
.rst_l (tap_rst_l),
.q (misc_shift_dr_pre)
);
// shadow scan
dffrl_async_ns #(1) u_dffrl_async_shadow_scan_instr
( .din (next_shadow_scan_instr),
.clk (tck_l),
.rst_l (tap_rst_l),
.q (shadow_scan_instr)
);
dffsl_async_ns #(1) u_dffsl_async_spc_sscan_tid0
( .din (next_spc_sscan_tid[0]),
.clk (tck_l),
.set_l (tap_rst_l),
.q (spc_sscan_tid[0])
);
dffrl_async_ns #(3) u_dffrl_async_spc_sscan_tid1to3
( .din (next_spc_sscan_tid[3:1]),
.clk (tck_l),
.rst_l (tap_rst_l),
.q (spc_sscan_tid[3:1])
);
dffrl_async_ns #(1) u_dffrl_async_ctu_pads_sscan_update
( .din (next_ctu_pads_sscan_update),
.clk (tck_l),
.rst_l (tap_rst_l),
.q (ctu_pads_sscan_update)
);
dffrl_async_ns #(1) u_dffrl_async_spc0_sscan_se_pre
( .din (next_spc0_sscan_se_pre),
.clk (tck_l),
.rst_l (tap_rst_l),
.q (spc0_sscan_se_pre)
);
dffrl_async_ns #(1) u_dffrl_async_spc1_sscan_se_pre
( .din (next_spc1_sscan_se_pre),
.clk (tck_l),
.rst_l (tap_rst_l),
.q (spc1_sscan_se_pre)
);
dffrl_async_ns #(1) u_dffrl_async_spc2_sscan_se_pre
( .din (next_spc2_sscan_se_pre),
.clk (tck_l),
.rst_l (tap_rst_l),
.q (spc2_sscan_se_pre)
);
dffrl_async_ns #(1) u_dffrl_async_spc3_sscan_se_pre
( .din (next_spc3_sscan_se_pre),
.clk (tck_l),
.rst_l (tap_rst_l),
.q (spc3_sscan_se_pre)
);
dffrl_async_ns #(1) u_dffrl_async_spc4_sscan_se_pre
( .din (next_spc4_sscan_se_pre),
.clk (tck_l),
.rst_l (tap_rst_l),
.q (spc4_sscan_se_pre)
);
dffrl_async_ns #(1) u_dffrl_async_spc5_sscan_se_pre
( .din (next_spc5_sscan_se_pre),
.clk (tck_l),
.rst_l (tap_rst_l),
.q (spc5_sscan_se_pre)
);
dffrl_async_ns #(1) u_dffrl_async_spc6_sscan_se_pre
( .din (next_spc6_sscan_se_pre),
.clk (tck_l),
.rst_l (tap_rst_l),
.q (spc6_sscan_se_pre)
);
dffrl_async_ns #(1) u_dffrl_async_spc7_sscan_se_pre
( .din (next_spc7_sscan_se_pre),
.clk (tck_l),
.rst_l (tap_rst_l),
.q (spc7_sscan_se_pre)
);
dffrl_async_ns #(1) u_dffrl_async_spc0_tck_pre
( .din (next_spc0_tck_pre),
.clk (tck_l),
.rst_l (tap_rst_l),
.q (spc0_tck_pre)
);
dffrl_async_ns #(1) u_dffrl_async_spc1_tck_pre
( .din (next_spc1_tck_pre),
.clk (tck_l),
.rst_l (tap_rst_l),
.q (spc1_tck_pre)
);
dffrl_async_ns #(1) u_dffrl_async_spc2_tck_pre
( .din (next_spc2_tck_pre),
.clk (tck_l),
.rst_l (tap_rst_l),
.q (spc2_tck_pre)
);
dffrl_async_ns #(1) u_dffrl_async_spc3_tck_pre
( .din (next_spc3_tck_pre),
.clk (tck_l),
.rst_l (tap_rst_l),
.q (spc3_tck_pre)
);
dffrl_async_ns #(1) u_dffrl_async_spc4_tck_pre
( .din (next_spc4_tck_pre),
.clk (tck_l),
.rst_l (tap_rst_l),
.q (spc4_tck_pre)
);
dffrl_async_ns #(1) u_dffrl_async_spc5_tck_pre
( .din (next_spc5_tck_pre),
.clk (tck_l),
.rst_l (tap_rst_l),
.q (spc5_tck_pre)
);
dffrl_async_ns #(1) u_dffrl_async_spc6_tck_pre
( .din (next_spc6_tck_pre),
.clk (tck_l),
.rst_l (tap_rst_l),
.q (spc6_tck_pre)
);
dffrl_async_ns #(1) u_dffrl_async_spc7_tck_pre
( .din (next_spc7_tck_pre),
.clk (tck_l),
.rst_l (tap_rst_l),
.q (spc7_tck_pre)
);
dffrl_async_ns #(1) u_dffrl_async_ctu_global_snap
( .din (next_ctu_global_snap),
.clk (tck_l),
.rst_l (tap_rst_l),
.q (ctu_global_snap)
);
// scan
dffrl_async_ns #(1) u_dffrl_async_instr_normal_scan
( .din (next_instr_normal_scan),
.clk (tck_l),
.rst_l (tap_rst_l),
.q (instr_normal_scan)
);
dffrl_async_ns #(1) u_dffrl_async_instr_scan
( .din (next_instr_scan),
.clk (tck_l),
.rst_l (tap_rst_l),
.q (instr_scan)
);
dffrl_async_ns #(1) u_dffrl_async_global_shift_enable_pre
( .din (next_global_shift_enable_pre),
.clk (tck_l),
.rst_l (tap_rst_l),
.q (global_shift_enable_pre)
);
dffrl_async_ns #(1) u_dffrl_async_ctu_tst_macrotest
( .din (next_ctu_tst_macrotest),
.clk (tck_l),
.rst_l (tap_rst_l),
.q (ctu_tst_macrotest)
);
dffrl_async_ns #(1) u_dffrl_async_ctu_tst_short_chain
( .din (next_ctu_tst_short_chain),
.clk (tck_l),
.rst_l (tap_rst_l),
.q (ctu_tst_short_chain)
);
dffrl_async_ns #(JTAG_SDR_CNT_WIDTH) u_dffrl_async_scan_dump_shiftdr_cnt
(.din (next_scan_dump_shiftdr_cnt),
.clk (tck_l),
.rst_l (tap_rst_l),
.q (scan_dump_shiftdr_cnt));
// efc
dffrl_async_ns #(1) u_dffrl_async_ctu_efc_capturedr
( .din (next_ctu_efc_capturedr),
.clk (tck_l),
.rst_l (tap_rst_l),
.q (ctu_efc_capturedr)
);
dffrl_async_ns #(1) u_dffrl_async_ctu_efc_shiftdr
( .din (next_ctu_efc_shiftdr),
.clk (tck_l),
.rst_l (tap_rst_l),
.q (ctu_efc_shiftdr)
);
dffrl_async_ns #(1) u_dffrl_async_ctu_efc_updatedr
( .din (next_ctu_efc_updatedr),
.clk (tck_l),
.rst_l (tap_rst_l),
.q (ctu_efc_updatedr)
);
dffrl_async_ns #(1) u_dffrl_async_efc_tck_pre
( .din (next_efc_tck_pre),
.clk (tck_l),
.rst_l (tap_rst_l),
.q (efc_tck_pre)
);
dffrl_async_ns #(1) u_dffrl_async_ctu_efc_fuse_bypass
( .din (next_ctu_efc_fuse_bypass),
.clk (tck_l),
.rst_l (tap_rst_l),
.q (ctu_efc_fuse_bypass)
);
dffrl_async_ns #(1) u_dffrl_async_ctu_efc_read_en
( .din (next_ctu_efc_read_en),
.clk (tck_l),
.rst_l (tap_rst_l),
.q (ctu_efc_read_en)
);
dffrl_async_ns #(1) u_dffrl_async_ctu_efc_dest_sample
( .din (next_ctu_efc_dest_sample),
.clk (tck_l),
.rst_l (tap_rst_l),
.q (ctu_efc_dest_sample)
);
dffsl_async_ns #(1) u_dffsl_async_suppress_capture_l
( .din (next_suppress_capture_l),
.clk (tck_l),
.set_l (tap_rst_l),
.q (suppress_capture_l)
);
dffrl_async_ns #(7) u_dffrl_async_ctu_efc_rowaddr
( .din (next_ctu_efc_rowaddr),
.clk (tck_l),
.rst_l (tap_rst_l),
.q (ctu_efc_rowaddr)
);
dffrl_async_ns #(5) u_dffrl_async_ctu_efc_coladdr
( .din (next_ctu_efc_coladdr),
.clk (tck_l),
.rst_l (tap_rst_l),
.q (ctu_efc_coladdr)
);
dffrl_async_ns #(3) u_dffrl_async_ctu_efc_read_mode
( .din (next_ctu_efc_read_mode),
.clk (tck_l),
.rst_l (tap_rst_l),
.q (ctu_efc_read_mode)
);
// nstep
dffrl_async_ns #(1) u_dffrl_async_nstep_mode
( .din (next_nstep_mode),
.clk (tck_l),
.rst_l (tap_rst_l),
.q (nstep_mode)
);
dffsl_async_ns #(1) u_dffsl_async_dft_clsp_nstep_capture_l
( .din (next_dft_clsp_nstep_capture_l),
.clk (tck_l),
.set_l (tap_rst_l),
.q (dft_clsp_nstep_capture_l)
);
// clock control
dffrl_async_ns u_dffrl_async_sel_tck2_pre
(.din (next_sel_tck2_pre),
.clk (tck_l),
.rst_l (tap_rst_l),
.q (sel_tck2_pre));
dffrl_async_ns u_dffrl_async_jtag_clsp_force_cken_cmp
(.din (next_jtag_clsp_force_cken_cmp),
.clk (tck_l),
.rst_l (tap_rst_l),
.q (jtag_clsp_force_cken_cmp));
dffrl_async_ns u_dffrl_async_jtag_clsp_force_cken_dram
(.din (next_jtag_clsp_force_cken_dram),
.clk (tck_l),
.rst_l (tap_rst_l),
.q (jtag_clsp_force_cken_dram));
dffrl_async_ns u_dffrl_async_jtag_clsp_force_cken_jbus
(.din (next_jtag_clsp_force_cken_jbus),
.clk (tck_l),
.rst_l (tap_rst_l),
.q (jtag_clsp_force_cken_jbus));
dffrl_async_ns u_dffrl_async_pll_bypass_tap
(.din (next_pll_bypass_tap),
.clk (tck_l),
.rst_l (tap_rst_l),
.q (pll_bypass_tap));
//*******************************************************************************
// DFF Instantiations
//*******************************************************************************
dff_ns u_dff_creg_rdrtrn_load_d1
( .din (creg_rdrtrn_load),
.clk (io_tck),
.q (creg_rdrtrn_load_d1)
);
dff_ns u_dff_creg_jtag_rdrtrn_vld_d
( .din (creg_jtag_rdrtrn_vld),
.clk (io_tck),
.q (creg_jtag_rdrtrn_vld_d)
);
dff_ns u_dff_creg_jtag_rdrtrn_vld_d2
( .din (creg_jtag_rdrtrn_vld_d),
.clk (io_tck),
.q (creg_jtag_rdrtrn_vld_d2)
);
dff_ns u_dff_tap_shift_dr_state_d1
(.din (tap_shift_dr_state),
.clk (io_tck),
.q (tap_shift_dr_state_d1)
);
dff_ns u_dff_tap_update_ir_state_d1
( .din (tap_update_ir_state),
.clk (io_tck),
.q (tap_update_ir_state_d1)
);
dff_ns u_dff_tap_update_ir_state_d2
( .din (tap_update_ir_state_d1),
.clk (io_tck),
.q (tap_update_ir_state_d2)
);
dff_ns u_dff_instr_iob_rd_d1
(.din (instr_iob_rd),
.clk (io_tck),
.q (instr_iob_rd_d1)
);
dff_ns u_dff_instr_iob_raddr_d1
(.din (instr_iob_raddr),
.clk (io_tck),
.q (instr_iob_raddr_d1)
);
dff_ns #(3) u_dff_efc_read_mode
(.din (next_efc_read_mode),
.clk (io_tck),
.q (efc_read_mode)
);
dff_ns #(5) u_dff_efc_coladdr
(.din (next_efc_coladdr),
.clk (io_tck),
.q (efc_coladdr)
);
dff_ns #(7) u_dff_efc_rowaddr
(.din (next_efc_rowaddr),
.clk (io_tck),
.q (efc_rowaddr)
);
dff_ns #(`CTU_BIST_CNT*2) u_dff_bist_result_reg
(.din (next_bist_result_reg),
.clk (io_tck),
.q (bist_result_reg)
);
dff_ns #(65) u_dff_creg_rdrtrn
(.din (next_creg_rdrtrn),
.clk (io_tck),
.q (creg_rdrtrn)
);
dff_ns #(64) u_dff_creg_wdata
(.din (next_creg_wdata),
.clk (io_tck),
.q (creg_wdata)
);
dff_ns #(40) u_dff_creg_addr
(.din (next_creg_addr),
.clk (io_tck),
.q (creg_addr)
);
dff_ns #(32) u_dff_idcode
(.din (next_idcode),
.clk (io_tck),
.q (idcode)
);
dff_ns #(JTAG_SDR_CNT_WIDTH) u_dff_cken_dram_wait
(.din (next_cken_dram_wait),
.clk (io_tck),
.q (cken_dram_wait)
);
dff_ns #(JTAG_SDR_CNT_WIDTH) u_dff_cken_jbus_wait
(.din (next_cken_jbus_wait),
.clk (io_tck),
.q (cken_jbus_wait)
);
dff_ns #(JTAG_SDR_CNT_WIDTH) u_dff_cken_other_wait
(.din (next_cken_other_wait),
.clk (io_tck),
.q (cken_other_wait)
);
// bug #5696
dff_ns #(1) u_dff_pads_ctu_si_bypmux_out_ff_nsr
(.din (pads_ctu_si_bypmux_out),
.clk (io_tck),
.q (pads_ctu_si_bypmux_out_ff)
);
endmodule
|
module zqynq_lab_1_design_axi_bram_ctrl_0_bram_0
(clka,
rsta,
ena,
wea,
addra,
dina,
douta,
clkb,
rstb,
enb,
web,
addrb,
dinb,
doutb);
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK" *) input clka;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA RST" *) input rsta;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA EN" *) input ena;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA WE" *) input [3:0]wea;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR" *) input [31:0]addra;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN" *) input [31:0]dina;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT" *) output [31:0]douta;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTB CLK" *) input clkb;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTB RST" *) input rstb;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTB EN" *) input enb;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTB WE" *) input [3:0]web;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTB ADDR" *) input [31:0]addrb;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTB DIN" *) input [31:0]dinb;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTB DOUT" *) output [31:0]doutb;
wire [31:0]addra;
wire [31:0]addrb;
wire clka;
wire clkb;
wire [31:0]dina;
wire [31:0]dinb;
wire [31:0]douta;
wire [31:0]doutb;
wire ena;
wire enb;
wire rsta;
wire rstb;
wire [3:0]wea;
wire [3:0]web;
wire NLW_U0_dbiterr_UNCONNECTED;
wire NLW_U0_rsta_busy_UNCONNECTED;
wire NLW_U0_rstb_busy_UNCONNECTED;
wire NLW_U0_s_axi_arready_UNCONNECTED;
wire NLW_U0_s_axi_awready_UNCONNECTED;
wire NLW_U0_s_axi_bvalid_UNCONNECTED;
wire NLW_U0_s_axi_dbiterr_UNCONNECTED;
wire NLW_U0_s_axi_rlast_UNCONNECTED;
wire NLW_U0_s_axi_rvalid_UNCONNECTED;
wire NLW_U0_s_axi_sbiterr_UNCONNECTED;
wire NLW_U0_s_axi_wready_UNCONNECTED;
wire NLW_U0_sbiterr_UNCONNECTED;
wire [31:0]NLW_U0_rdaddrecc_UNCONNECTED;
wire [3:0]NLW_U0_s_axi_bid_UNCONNECTED;
wire [1:0]NLW_U0_s_axi_bresp_UNCONNECTED;
wire [31:0]NLW_U0_s_axi_rdaddrecc_UNCONNECTED;
wire [31:0]NLW_U0_s_axi_rdata_UNCONNECTED;
wire [3:0]NLW_U0_s_axi_rid_UNCONNECTED;
wire [1:0]NLW_U0_s_axi_rresp_UNCONNECTED;
(* C_ADDRA_WIDTH = "32" *)
(* C_ADDRB_WIDTH = "32" *)
(* C_ALGORITHM = "1" *)
(* C_AXI_ID_WIDTH = "4" *)
(* C_AXI_SLAVE_TYPE = "0" *)
(* C_AXI_TYPE = "1" *)
(* C_BYTE_SIZE = "8" *)
(* C_COMMON_CLK = "0" *)
(* C_COUNT_18K_BRAM = "0" *)
(* C_COUNT_36K_BRAM = "16" *)
(* C_CTRL_ECC_ALGO = "NONE" *)
(* C_DEFAULT_DATA = "0" *)
(* C_DISABLE_WARN_BHV_COLL = "0" *)
(* C_DISABLE_WARN_BHV_RANGE = "0" *)
(* C_ELABORATION_DIR = "./" *)
(* C_ENABLE_32BIT_ADDRESS = "1" *)
(* C_EN_DEEPSLEEP_PIN = "0" *)
(* C_EN_ECC_PIPE = "0" *)
(* C_EN_RDADDRA_CHG = "0" *)
(* C_EN_RDADDRB_CHG = "0" *)
(* C_EN_SAFETY_CKT = "0" *)
(* C_EN_SHUTDOWN_PIN = "0" *)
(* C_EN_SLEEP_PIN = "0" *)
(* C_EST_POWER_SUMMARY = "Estimated Power for IP : 20.388 mW" *)
(* C_FAMILY = "zynq" *)
(* C_HAS_AXI_ID = "0" *)
(* C_HAS_ENA = "1" *)
(* C_HAS_ENB = "1" *)
(* C_HAS_INJECTERR = "0" *)
(* C_HAS_MEM_OUTPUT_REGS_A = "0" *)
(* C_HAS_MEM_OUTPUT_REGS_B = "0" *)
(* C_HAS_MUX_OUTPUT_REGS_A = "0" *)
(* C_HAS_MUX_OUTPUT_REGS_B = "0" *)
(* C_HAS_REGCEA = "0" *)
(* C_HAS_REGCEB = "0" *)
(* C_HAS_RSTA = "1" *)
(* C_HAS_RSTB = "1" *)
(* C_HAS_SOFTECC_INPUT_REGS_A = "0" *)
(* C_HAS_SOFTECC_OUTPUT_REGS_B = "0" *)
(* C_INITA_VAL = "0" *)
(* C_INITB_VAL = "0" *)
(* C_INIT_FILE = "NONE" *)
(* C_INIT_FILE_NAME = "no_coe_file_loaded" *)
(* C_INTERFACE_TYPE = "0" *)
(* C_LOAD_INIT_FILE = "0" *)
(* C_MEM_TYPE = "2" *)
(* C_MUX_PIPELINE_STAGES = "0" *)
(* C_PRIM_TYPE = "1" *)
(* C_READ_DEPTH_A = "16384" *)
(* C_READ_DEPTH_B = "16384" *)
(* C_READ_WIDTH_A = "32" *)
(* C_READ_WIDTH_B = "32" *)
(* C_RSTRAM_A = "0" *)
(* C_RSTRAM_B = "0" *)
(* C_RST_PRIORITY_A = "CE" *)
(* C_RST_PRIORITY_B = "CE" *)
(* C_SIM_COLLISION_CHECK = "ALL" *)
(* C_USE_BRAM_BLOCK = "1" *)
(* C_USE_BYTE_WEA = "1" *)
(* C_USE_BYTE_WEB = "1" *)
(* C_USE_DEFAULT_DATA = "0" *)
(* C_USE_ECC = "0" *)
(* C_USE_SOFTECC = "0" *)
(* C_USE_URAM = "0" *)
(* C_WEA_WIDTH = "4" *)
(* C_WEB_WIDTH = "4" *)
(* C_WRITE_DEPTH_A = "16384" *)
(* C_WRITE_DEPTH_B = "16384" *)
(* C_WRITE_MODE_A = "WRITE_FIRST" *)
(* C_WRITE_MODE_B = "WRITE_FIRST" *)
(* C_WRITE_WIDTH_A = "32" *)
(* C_WRITE_WIDTH_B = "32" *)
(* C_XDEVICEFAMILY = "zynq" *)
(* downgradeipidentifiedwarnings = "yes" *)
zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_v8_3_6 U0
(.addra(addra),
.addrb(addrb),
.clka(clka),
.clkb(clkb),
.dbiterr(NLW_U0_dbiterr_UNCONNECTED),
.deepsleep(1'b0),
.dina(dina),
.dinb(dinb),
.douta(douta),
.doutb(doutb),
.eccpipece(1'b0),
.ena(ena),
.enb(enb),
.injectdbiterr(1'b0),
.injectsbiterr(1'b0),
.rdaddrecc(NLW_U0_rdaddrecc_UNCONNECTED[31:0]),
.regcea(1'b0),
.regceb(1'b0),
.rsta(rsta),
.rsta_busy(NLW_U0_rsta_busy_UNCONNECTED),
.rstb(rstb),
.rstb_busy(NLW_U0_rstb_busy_UNCONNECTED),
.s_aclk(1'b0),
.s_aresetn(1'b0),
.s_axi_araddr({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_arburst({1'b0,1'b0}),
.s_axi_arid({1'b0,1'b0,1'b0,1'b0}),
.s_axi_arlen({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_arready(NLW_U0_s_axi_arready_UNCONNECTED),
.s_axi_arsize({1'b0,1'b0,1'b0}),
.s_axi_arvalid(1'b0),
.s_axi_awaddr({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_awburst({1'b0,1'b0}),
.s_axi_awid({1'b0,1'b0,1'b0,1'b0}),
.s_axi_awlen({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_awready(NLW_U0_s_axi_awready_UNCONNECTED),
.s_axi_awsize({1'b0,1'b0,1'b0}),
.s_axi_awvalid(1'b0),
.s_axi_bid(NLW_U0_s_axi_bid_UNCONNECTED[3:0]),
.s_axi_bready(1'b0),
.s_axi_bresp(NLW_U0_s_axi_bresp_UNCONNECTED[1:0]),
.s_axi_bvalid(NLW_U0_s_axi_bvalid_UNCONNECTED),
.s_axi_dbiterr(NLW_U0_s_axi_dbiterr_UNCONNECTED),
.s_axi_injectdbiterr(1'b0),
.s_axi_injectsbiterr(1'b0),
.s_axi_rdaddrecc(NLW_U0_s_axi_rdaddrecc_UNCONNECTED[31:0]),
.s_axi_rdata(NLW_U0_s_axi_rdata_UNCONNECTED[31:0]),
.s_axi_rid(NLW_U0_s_axi_rid_UNCONNECTED[3:0]),
.s_axi_rlast(NLW_U0_s_axi_rlast_UNCONNECTED),
.s_axi_rready(1'b0),
.s_axi_rresp(NLW_U0_s_axi_rresp_UNCONNECTED[1:0]),
.s_axi_rvalid(NLW_U0_s_axi_rvalid_UNCONNECTED),
.s_axi_sbiterr(NLW_U0_s_axi_sbiterr_UNCONNECTED),
.s_axi_wdata({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_wlast(1'b0),
.s_axi_wready(NLW_U0_s_axi_wready_UNCONNECTED),
.s_axi_wstrb({1'b0,1'b0,1'b0,1'b0}),
.s_axi_wvalid(1'b0),
.sbiterr(NLW_U0_sbiterr_UNCONNECTED),
.shutdown(1'b0),
.sleep(1'b0),
.wea(wea),
.web(web));
endmodule
|
module zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_generic_cstr
(douta,
doutb,
clka,
clkb,
ena,
enb,
rsta,
rstb,
addra,
addrb,
dina,
dinb,
wea,
web);
output [31:0]douta;
output [31:0]doutb;
input clka;
input clkb;
input ena;
input enb;
input rsta;
input rstb;
input [13:0]addra;
input [13:0]addrb;
input [31:0]dina;
input [31:0]dinb;
input [3:0]wea;
input [3:0]web;
wire [13:0]addra;
wire [13:0]addrb;
wire clka;
wire clkb;
wire [31:0]dina;
wire [31:0]dinb;
wire [31:0]douta;
wire [31:0]doutb;
wire ena;
wire enb;
wire rsta;
wire rstb;
wire [3:0]wea;
wire [3:0]web;
zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_width \ramloop[0].ram.r
(.addra(addra),
.addrb(addrb),
.clka(clka),
.clkb(clkb),
.dina(dina[1:0]),
.dinb(dinb[1:0]),
.douta(douta[1:0]),
.doutb(doutb[1:0]),
.ena(ena),
.enb(enb),
.rsta(rsta),
.rstb(rstb),
.wea(wea[0]),
.web(web[0]));
zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_width__parameterized9 \ramloop[10].ram.r
(.addra(addra),
.addrb(addrb),
.clka(clka),
.clkb(clkb),
.dina(dina[21:20]),
.dinb(dinb[21:20]),
.douta(douta[21:20]),
.doutb(doutb[21:20]),
.ena(ena),
.enb(enb),
.rsta(rsta),
.rstb(rstb),
.wea(wea[2]),
.web(web[2]));
zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_width__parameterized10 \ramloop[11].ram.r
(.addra(addra),
.addrb(addrb),
.clka(clka),
.clkb(clkb),
.dina(dina[23:22]),
.dinb(dinb[23:22]),
.douta(douta[23:22]),
.doutb(doutb[23:22]),
.ena(ena),
.enb(enb),
.rsta(rsta),
.rstb(rstb),
.wea(wea[2]),
.web(web[2]));
zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_width__parameterized11 \ramloop[12].ram.r
(.addra(addra),
.addrb(addrb),
.clka(clka),
.clkb(clkb),
.dina(dina[25:24]),
.dinb(dinb[25:24]),
.douta(douta[25:24]),
.doutb(doutb[25:24]),
.ena(ena),
.enb(enb),
.rsta(rsta),
.rstb(rstb),
.wea(wea[3]),
.web(web[3]));
zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_width__parameterized12 \ramloop[13].ram.r
(.addra(addra),
.addrb(addrb),
.clka(clka),
.clkb(clkb),
.dina(dina[27:26]),
.dinb(dinb[27:26]),
.douta(douta[27:26]),
.doutb(doutb[27:26]),
.ena(ena),
.enb(enb),
.rsta(rsta),
.rstb(rstb),
.wea(wea[3]),
.web(web[3]));
zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_width__parameterized13 \ramloop[14].ram.r
(.addra(addra),
.addrb(addrb),
.clka(clka),
.clkb(clkb),
.dina(dina[29:28]),
.dinb(dinb[29:28]),
.douta(douta[29:28]),
.doutb(doutb[29:28]),
.ena(ena),
.enb(enb),
.rsta(rsta),
.rstb(rstb),
.wea(wea[3]),
.web(web[3]));
zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_width__parameterized14 \ramloop[15].ram.r
(.addra(addra),
.addrb(addrb),
.clka(clka),
.clkb(clkb),
.dina(dina[31:30]),
.dinb(dinb[31:30]),
.douta(douta[31:30]),
.doutb(doutb[31:30]),
.ena(ena),
.enb(enb),
.rsta(rsta),
.rstb(rstb),
.wea(wea[3]),
.web(web[3]));
zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_width__parameterized0 \ramloop[1].ram.r
(.addra(addra),
.addrb(addrb),
.clka(clka),
.clkb(clkb),
.dina(dina[3:2]),
.dinb(dinb[3:2]),
.douta(douta[3:2]),
.doutb(doutb[3:2]),
.ena(ena),
.enb(enb),
.rsta(rsta),
.rstb(rstb),
.wea(wea[0]),
.web(web[0]));
zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_width__parameterized1 \ramloop[2].ram.r
(.addra(addra),
.addrb(addrb),
.clka(clka),
.clkb(clkb),
.dina(dina[5:4]),
.dinb(dinb[5:4]),
.douta(douta[5:4]),
.doutb(doutb[5:4]),
.ena(ena),
.enb(enb),
.rsta(rsta),
.rstb(rstb),
.wea(wea[0]),
.web(web[0]));
zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_width__parameterized2 \ramloop[3].ram.r
(.addra(addra),
.addrb(addrb),
.clka(clka),
.clkb(clkb),
.dina(dina[7:6]),
.dinb(dinb[7:6]),
.douta(douta[7:6]),
.doutb(doutb[7:6]),
.ena(ena),
.enb(enb),
.rsta(rsta),
.rstb(rstb),
.wea(wea[0]),
.web(web[0]));
zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_width__parameterized3 \ramloop[4].ram.r
(.addra(addra),
.addrb(addrb),
.clka(clka),
.clkb(clkb),
.dina(dina[9:8]),
.dinb(dinb[9:8]),
.douta(douta[9:8]),
.doutb(doutb[9:8]),
.ena(ena),
.enb(enb),
.rsta(rsta),
.rstb(rstb),
.wea(wea[1]),
.web(web[1]));
zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_width__parameterized4 \ramloop[5].ram.r
(.addra(addra),
.addrb(addrb),
.clka(clka),
.clkb(clkb),
.dina(dina[11:10]),
.dinb(dinb[11:10]),
.douta(douta[11:10]),
.doutb(doutb[11:10]),
.ena(ena),
.enb(enb),
.rsta(rsta),
.rstb(rstb),
.wea(wea[1]),
.web(web[1]));
zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_width__parameterized5 \ramloop[6].ram.r
(.addra(addra),
.addrb(addrb),
.clka(clka),
.clkb(clkb),
.dina(dina[13:12]),
.dinb(dinb[13:12]),
.douta(douta[13:12]),
.doutb(doutb[13:12]),
.ena(ena),
.enb(enb),
.rsta(rsta),
.rstb(rstb),
.wea(wea[1]),
.web(web[1]));
zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_width__parameterized6 \ramloop[7].ram.r
(.addra(addra),
.addrb(addrb),
.clka(clka),
.clkb(clkb),
.dina(dina[15:14]),
.dinb(dinb[15:14]),
.douta(douta[15:14]),
.doutb(doutb[15:14]),
.ena(ena),
.enb(enb),
.rsta(rsta),
.rstb(rstb),
.wea(wea[1]),
.web(web[1]));
zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_width__parameterized7 \ramloop[8].ram.r
(.addra(addra),
.addrb(addrb),
.clka(clka),
.clkb(clkb),
.dina(dina[17:16]),
.dinb(dinb[17:16]),
.douta(douta[17:16]),
.doutb(doutb[17:16]),
.ena(ena),
.enb(enb),
.rsta(rsta),
.rstb(rstb),
.wea(wea[2]),
.web(web[2]));
zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_width__parameterized8 \ramloop[9].ram.r
(.addra(addra),
.addrb(addrb),
.clka(clka),
.clkb(clkb),
.dina(dina[19:18]),
.dinb(dinb[19:18]),
.douta(douta[19:18]),
.doutb(doutb[19:18]),
.ena(ena),
.enb(enb),
.rsta(rsta),
.rstb(rstb),
.wea(wea[2]),
.web(web[2]));
endmodule
|
module zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_width
(douta,
doutb,
clka,
clkb,
ena,
enb,
rsta,
rstb,
addra,
addrb,
dina,
dinb,
wea,
web);
output [1:0]douta;
output [1:0]doutb;
input clka;
input clkb;
input ena;
input enb;
input rsta;
input rstb;
input [13:0]addra;
input [13:0]addrb;
input [1:0]dina;
input [1:0]dinb;
input [0:0]wea;
input [0:0]web;
wire [13:0]addra;
wire [13:0]addrb;
wire clka;
wire clkb;
wire [1:0]dina;
wire [1:0]dinb;
wire [1:0]douta;
wire [1:0]doutb;
wire ena;
wire enb;
wire rsta;
wire rstb;
wire [0:0]wea;
wire [0:0]web;
zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_wrapper \prim_noinit.ram
(.addra(addra),
.addrb(addrb),
.clka(clka),
.clkb(clkb),
.dina(dina),
.dinb(dinb),
.douta(douta),
.doutb(doutb),
.ena(ena),
.enb(enb),
.rsta(rsta),
.rstb(rstb),
.wea(wea),
.web(web));
endmodule
|
module zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_width__parameterized0
(douta,
doutb,
clka,
clkb,
ena,
enb,
rsta,
rstb,
addra,
addrb,
dina,
dinb,
wea,
web);
output [1:0]douta;
output [1:0]doutb;
input clka;
input clkb;
input ena;
input enb;
input rsta;
input rstb;
input [13:0]addra;
input [13:0]addrb;
input [1:0]dina;
input [1:0]dinb;
input [0:0]wea;
input [0:0]web;
wire [13:0]addra;
wire [13:0]addrb;
wire clka;
wire clkb;
wire [1:0]dina;
wire [1:0]dinb;
wire [1:0]douta;
wire [1:0]doutb;
wire ena;
wire enb;
wire rsta;
wire rstb;
wire [0:0]wea;
wire [0:0]web;
zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_wrapper__parameterized0 \prim_noinit.ram
(.addra(addra),
.addrb(addrb),
.clka(clka),
.clkb(clkb),
.dina(dina),
.dinb(dinb),
.douta(douta),
.doutb(doutb),
.ena(ena),
.enb(enb),
.rsta(rsta),
.rstb(rstb),
.wea(wea),
.web(web));
endmodule
|
module zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_width__parameterized1
(douta,
doutb,
clka,
clkb,
ena,
enb,
rsta,
rstb,
addra,
addrb,
dina,
dinb,
wea,
web);
output [1:0]douta;
output [1:0]doutb;
input clka;
input clkb;
input ena;
input enb;
input rsta;
input rstb;
input [13:0]addra;
input [13:0]addrb;
input [1:0]dina;
input [1:0]dinb;
input [0:0]wea;
input [0:0]web;
wire [13:0]addra;
wire [13:0]addrb;
wire clka;
wire clkb;
wire [1:0]dina;
wire [1:0]dinb;
wire [1:0]douta;
wire [1:0]doutb;
wire ena;
wire enb;
wire rsta;
wire rstb;
wire [0:0]wea;
wire [0:0]web;
zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_wrapper__parameterized1 \prim_noinit.ram
(.addra(addra),
.addrb(addrb),
.clka(clka),
.clkb(clkb),
.dina(dina),
.dinb(dinb),
.douta(douta),
.doutb(doutb),
.ena(ena),
.enb(enb),
.rsta(rsta),
.rstb(rstb),
.wea(wea),
.web(web));
endmodule
|
module zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_width__parameterized10
(douta,
doutb,
clka,
clkb,
ena,
enb,
rsta,
rstb,
addra,
addrb,
dina,
dinb,
wea,
web);
output [1:0]douta;
output [1:0]doutb;
input clka;
input clkb;
input ena;
input enb;
input rsta;
input rstb;
input [13:0]addra;
input [13:0]addrb;
input [1:0]dina;
input [1:0]dinb;
input [0:0]wea;
input [0:0]web;
wire [13:0]addra;
wire [13:0]addrb;
wire clka;
wire clkb;
wire [1:0]dina;
wire [1:0]dinb;
wire [1:0]douta;
wire [1:0]doutb;
wire ena;
wire enb;
wire rsta;
wire rstb;
wire [0:0]wea;
wire [0:0]web;
zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_wrapper__parameterized10 \prim_noinit.ram
(.addra(addra),
.addrb(addrb),
.clka(clka),
.clkb(clkb),
.dina(dina),
.dinb(dinb),
.douta(douta),
.doutb(doutb),
.ena(ena),
.enb(enb),
.rsta(rsta),
.rstb(rstb),
.wea(wea),
.web(web));
endmodule
|
module zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_width__parameterized11
(douta,
doutb,
clka,
clkb,
ena,
enb,
rsta,
rstb,
addra,
addrb,
dina,
dinb,
wea,
web);
output [1:0]douta;
output [1:0]doutb;
input clka;
input clkb;
input ena;
input enb;
input rsta;
input rstb;
input [13:0]addra;
input [13:0]addrb;
input [1:0]dina;
input [1:0]dinb;
input [0:0]wea;
input [0:0]web;
wire [13:0]addra;
wire [13:0]addrb;
wire clka;
wire clkb;
wire [1:0]dina;
wire [1:0]dinb;
wire [1:0]douta;
wire [1:0]doutb;
wire ena;
wire enb;
wire rsta;
wire rstb;
wire [0:0]wea;
wire [0:0]web;
zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_wrapper__parameterized11 \prim_noinit.ram
(.addra(addra),
.addrb(addrb),
.clka(clka),
.clkb(clkb),
.dina(dina),
.dinb(dinb),
.douta(douta),
.doutb(doutb),
.ena(ena),
.enb(enb),
.rsta(rsta),
.rstb(rstb),
.wea(wea),
.web(web));
endmodule
|
module zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_width__parameterized12
(douta,
doutb,
clka,
clkb,
ena,
enb,
rsta,
rstb,
addra,
addrb,
dina,
dinb,
wea,
web);
output [1:0]douta;
output [1:0]doutb;
input clka;
input clkb;
input ena;
input enb;
input rsta;
input rstb;
input [13:0]addra;
input [13:0]addrb;
input [1:0]dina;
input [1:0]dinb;
input [0:0]wea;
input [0:0]web;
wire [13:0]addra;
wire [13:0]addrb;
wire clka;
wire clkb;
wire [1:0]dina;
wire [1:0]dinb;
wire [1:0]douta;
wire [1:0]doutb;
wire ena;
wire enb;
wire rsta;
wire rstb;
wire [0:0]wea;
wire [0:0]web;
zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_wrapper__parameterized12 \prim_noinit.ram
(.addra(addra),
.addrb(addrb),
.clka(clka),
.clkb(clkb),
.dina(dina),
.dinb(dinb),
.douta(douta),
.doutb(doutb),
.ena(ena),
.enb(enb),
.rsta(rsta),
.rstb(rstb),
.wea(wea),
.web(web));
endmodule
|
module zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_width__parameterized13
(douta,
doutb,
clka,
clkb,
ena,
enb,
rsta,
rstb,
addra,
addrb,
dina,
dinb,
wea,
web);
output [1:0]douta;
output [1:0]doutb;
input clka;
input clkb;
input ena;
input enb;
input rsta;
input rstb;
input [13:0]addra;
input [13:0]addrb;
input [1:0]dina;
input [1:0]dinb;
input [0:0]wea;
input [0:0]web;
wire [13:0]addra;
wire [13:0]addrb;
wire clka;
wire clkb;
wire [1:0]dina;
wire [1:0]dinb;
wire [1:0]douta;
wire [1:0]doutb;
wire ena;
wire enb;
wire rsta;
wire rstb;
wire [0:0]wea;
wire [0:0]web;
zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_wrapper__parameterized13 \prim_noinit.ram
(.addra(addra),
.addrb(addrb),
.clka(clka),
.clkb(clkb),
.dina(dina),
.dinb(dinb),
.douta(douta),
.doutb(doutb),
.ena(ena),
.enb(enb),
.rsta(rsta),
.rstb(rstb),
.wea(wea),
.web(web));
endmodule
|
module zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_width__parameterized14
(douta,
doutb,
clka,
clkb,
ena,
enb,
rsta,
rstb,
addra,
addrb,
dina,
dinb,
wea,
web);
output [1:0]douta;
output [1:0]doutb;
input clka;
input clkb;
input ena;
input enb;
input rsta;
input rstb;
input [13:0]addra;
input [13:0]addrb;
input [1:0]dina;
input [1:0]dinb;
input [0:0]wea;
input [0:0]web;
wire [13:0]addra;
wire [13:0]addrb;
wire clka;
wire clkb;
wire [1:0]dina;
wire [1:0]dinb;
wire [1:0]douta;
wire [1:0]doutb;
wire ena;
wire enb;
wire rsta;
wire rstb;
wire [0:0]wea;
wire [0:0]web;
zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_wrapper__parameterized14 \prim_noinit.ram
(.addra(addra),
.addrb(addrb),
.clka(clka),
.clkb(clkb),
.dina(dina),
.dinb(dinb),
.douta(douta),
.doutb(doutb),
.ena(ena),
.enb(enb),
.rsta(rsta),
.rstb(rstb),
.wea(wea),
.web(web));
endmodule
|
module zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_width__parameterized2
(douta,
doutb,
clka,
clkb,
ena,
enb,
rsta,
rstb,
addra,
addrb,
dina,
dinb,
wea,
web);
output [1:0]douta;
output [1:0]doutb;
input clka;
input clkb;
input ena;
input enb;
input rsta;
input rstb;
input [13:0]addra;
input [13:0]addrb;
input [1:0]dina;
input [1:0]dinb;
input [0:0]wea;
input [0:0]web;
wire [13:0]addra;
wire [13:0]addrb;
wire clka;
wire clkb;
wire [1:0]dina;
wire [1:0]dinb;
wire [1:0]douta;
wire [1:0]doutb;
wire ena;
wire enb;
wire rsta;
wire rstb;
wire [0:0]wea;
wire [0:0]web;
zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_wrapper__parameterized2 \prim_noinit.ram
(.addra(addra),
.addrb(addrb),
.clka(clka),
.clkb(clkb),
.dina(dina),
.dinb(dinb),
.douta(douta),
.doutb(doutb),
.ena(ena),
.enb(enb),
.rsta(rsta),
.rstb(rstb),
.wea(wea),
.web(web));
endmodule
|
module zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_width__parameterized3
(douta,
doutb,
clka,
clkb,
ena,
enb,
rsta,
rstb,
addra,
addrb,
dina,
dinb,
wea,
web);
output [1:0]douta;
output [1:0]doutb;
input clka;
input clkb;
input ena;
input enb;
input rsta;
input rstb;
input [13:0]addra;
input [13:0]addrb;
input [1:0]dina;
input [1:0]dinb;
input [0:0]wea;
input [0:0]web;
wire [13:0]addra;
wire [13:0]addrb;
wire clka;
wire clkb;
wire [1:0]dina;
wire [1:0]dinb;
wire [1:0]douta;
wire [1:0]doutb;
wire ena;
wire enb;
wire rsta;
wire rstb;
wire [0:0]wea;
wire [0:0]web;
zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_wrapper__parameterized3 \prim_noinit.ram
(.addra(addra),
.addrb(addrb),
.clka(clka),
.clkb(clkb),
.dina(dina),
.dinb(dinb),
.douta(douta),
.doutb(doutb),
.ena(ena),
.enb(enb),
.rsta(rsta),
.rstb(rstb),
.wea(wea),
.web(web));
endmodule
|
module zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_width__parameterized4
(douta,
doutb,
clka,
clkb,
ena,
enb,
rsta,
rstb,
addra,
addrb,
dina,
dinb,
wea,
web);
output [1:0]douta;
output [1:0]doutb;
input clka;
input clkb;
input ena;
input enb;
input rsta;
input rstb;
input [13:0]addra;
input [13:0]addrb;
input [1:0]dina;
input [1:0]dinb;
input [0:0]wea;
input [0:0]web;
wire [13:0]addra;
wire [13:0]addrb;
wire clka;
wire clkb;
wire [1:0]dina;
wire [1:0]dinb;
wire [1:0]douta;
wire [1:0]doutb;
wire ena;
wire enb;
wire rsta;
wire rstb;
wire [0:0]wea;
wire [0:0]web;
zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_wrapper__parameterized4 \prim_noinit.ram
(.addra(addra),
.addrb(addrb),
.clka(clka),
.clkb(clkb),
.dina(dina),
.dinb(dinb),
.douta(douta),
.doutb(doutb),
.ena(ena),
.enb(enb),
.rsta(rsta),
.rstb(rstb),
.wea(wea),
.web(web));
endmodule
|
module zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_width__parameterized5
(douta,
doutb,
clka,
clkb,
ena,
enb,
rsta,
rstb,
addra,
addrb,
dina,
dinb,
wea,
web);
output [1:0]douta;
output [1:0]doutb;
input clka;
input clkb;
input ena;
input enb;
input rsta;
input rstb;
input [13:0]addra;
input [13:0]addrb;
input [1:0]dina;
input [1:0]dinb;
input [0:0]wea;
input [0:0]web;
wire [13:0]addra;
wire [13:0]addrb;
wire clka;
wire clkb;
wire [1:0]dina;
wire [1:0]dinb;
wire [1:0]douta;
wire [1:0]doutb;
wire ena;
wire enb;
wire rsta;
wire rstb;
wire [0:0]wea;
wire [0:0]web;
zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_wrapper__parameterized5 \prim_noinit.ram
(.addra(addra),
.addrb(addrb),
.clka(clka),
.clkb(clkb),
.dina(dina),
.dinb(dinb),
.douta(douta),
.doutb(doutb),
.ena(ena),
.enb(enb),
.rsta(rsta),
.rstb(rstb),
.wea(wea),
.web(web));
endmodule
|
module zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_width__parameterized6
(douta,
doutb,
clka,
clkb,
ena,
enb,
rsta,
rstb,
addra,
addrb,
dina,
dinb,
wea,
web);
output [1:0]douta;
output [1:0]doutb;
input clka;
input clkb;
input ena;
input enb;
input rsta;
input rstb;
input [13:0]addra;
input [13:0]addrb;
input [1:0]dina;
input [1:0]dinb;
input [0:0]wea;
input [0:0]web;
wire [13:0]addra;
wire [13:0]addrb;
wire clka;
wire clkb;
wire [1:0]dina;
wire [1:0]dinb;
wire [1:0]douta;
wire [1:0]doutb;
wire ena;
wire enb;
wire rsta;
wire rstb;
wire [0:0]wea;
wire [0:0]web;
zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_wrapper__parameterized6 \prim_noinit.ram
(.addra(addra),
.addrb(addrb),
.clka(clka),
.clkb(clkb),
.dina(dina),
.dinb(dinb),
.douta(douta),
.doutb(doutb),
.ena(ena),
.enb(enb),
.rsta(rsta),
.rstb(rstb),
.wea(wea),
.web(web));
endmodule
|
module zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_width__parameterized7
(douta,
doutb,
clka,
clkb,
ena,
enb,
rsta,
rstb,
addra,
addrb,
dina,
dinb,
wea,
web);
output [1:0]douta;
output [1:0]doutb;
input clka;
input clkb;
input ena;
input enb;
input rsta;
input rstb;
input [13:0]addra;
input [13:0]addrb;
input [1:0]dina;
input [1:0]dinb;
input [0:0]wea;
input [0:0]web;
wire [13:0]addra;
wire [13:0]addrb;
wire clka;
wire clkb;
wire [1:0]dina;
wire [1:0]dinb;
wire [1:0]douta;
wire [1:0]doutb;
wire ena;
wire enb;
wire rsta;
wire rstb;
wire [0:0]wea;
wire [0:0]web;
zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_wrapper__parameterized7 \prim_noinit.ram
(.addra(addra),
.addrb(addrb),
.clka(clka),
.clkb(clkb),
.dina(dina),
.dinb(dinb),
.douta(douta),
.doutb(doutb),
.ena(ena),
.enb(enb),
.rsta(rsta),
.rstb(rstb),
.wea(wea),
.web(web));
endmodule
|
module zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_width__parameterized8
(douta,
doutb,
clka,
clkb,
ena,
enb,
rsta,
rstb,
addra,
addrb,
dina,
dinb,
wea,
web);
output [1:0]douta;
output [1:0]doutb;
input clka;
input clkb;
input ena;
input enb;
input rsta;
input rstb;
input [13:0]addra;
input [13:0]addrb;
input [1:0]dina;
input [1:0]dinb;
input [0:0]wea;
input [0:0]web;
wire [13:0]addra;
wire [13:0]addrb;
wire clka;
wire clkb;
wire [1:0]dina;
wire [1:0]dinb;
wire [1:0]douta;
wire [1:0]doutb;
wire ena;
wire enb;
wire rsta;
wire rstb;
wire [0:0]wea;
wire [0:0]web;
zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_wrapper__parameterized8 \prim_noinit.ram
(.addra(addra),
.addrb(addrb),
.clka(clka),
.clkb(clkb),
.dina(dina),
.dinb(dinb),
.douta(douta),
.doutb(doutb),
.ena(ena),
.enb(enb),
.rsta(rsta),
.rstb(rstb),
.wea(wea),
.web(web));
endmodule
|
module zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_width__parameterized9
(douta,
doutb,
clka,
clkb,
ena,
enb,
rsta,
rstb,
addra,
addrb,
dina,
dinb,
wea,
web);
output [1:0]douta;
output [1:0]doutb;
input clka;
input clkb;
input ena;
input enb;
input rsta;
input rstb;
input [13:0]addra;
input [13:0]addrb;
input [1:0]dina;
input [1:0]dinb;
input [0:0]wea;
input [0:0]web;
wire [13:0]addra;
wire [13:0]addrb;
wire clka;
wire clkb;
wire [1:0]dina;
wire [1:0]dinb;
wire [1:0]douta;
wire [1:0]doutb;
wire ena;
wire enb;
wire rsta;
wire rstb;
wire [0:0]wea;
wire [0:0]web;
zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_wrapper__parameterized9 \prim_noinit.ram
(.addra(addra),
.addrb(addrb),
.clka(clka),
.clkb(clkb),
.dina(dina),
.dinb(dinb),
.douta(douta),
.doutb(doutb),
.ena(ena),
.enb(enb),
.rsta(rsta),
.rstb(rstb),
.wea(wea),
.web(web));
endmodule
|
module zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_wrapper
(douta,
doutb,
clka,
clkb,
ena,
enb,
rsta,
rstb,
addra,
addrb,
dina,
dinb,
wea,
web);
output [1:0]douta;
output [1:0]doutb;
input clka;
input clkb;
input ena;
input enb;
input rsta;
input rstb;
input [13:0]addra;
input [13:0]addrb;
input [1:0]dina;
input [1:0]dinb;
input [0:0]wea;
input [0:0]web;
wire [13:0]addra;
wire [13:0]addrb;
wire clka;
wire clkb;
wire [1:0]dina;
wire [1:0]dinb;
wire [1:0]douta;
wire [1:0]doutb;
wire ena;
wire enb;
wire rsta;
wire rstb;
wire [0:0]wea;
wire [0:0]web;
wire \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_SBITERR_UNCONNECTED ;
wire [31:2]\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOADO_UNCONNECTED ;
wire [31:2]\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOBDO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPADOP_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_RDADDRECC_UNCONNECTED ;
(* bmm_info_memory_device = "[1:0][0:16383]" *)
(* box_type = "PRIMITIVE" *)
RAMB36E1 #(
.DOA_REG(0),
.DOB_REG(0),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
.READ_WIDTH_A(2),
.READ_WIDTH_B(2),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("WRITE_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(2),
.WRITE_WIDTH_B(2))
\DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram
(.ADDRARDADDR({1'b1,addra,1'b1}),
.ADDRBWRADDR({1'b1,addrb,1'b1}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(clka),
.CLKBWRCLK(clkb),
.DBITERR(\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,dina}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,dinb}),
.DIPADIP({1'b0,1'b0,1'b0,1'b0}),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO({\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOADO_UNCONNECTED [31:2],douta}),
.DOBDO({\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOBDO_UNCONNECTED [31:2],doutb}),
.DOPADOP(\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPADOP_UNCONNECTED [3:0]),
.DOPBDOP(\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPBDOP_UNCONNECTED [3:0]),
.ECCPARITY(\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(ena),
.ENBWREN(enb),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b0),
.REGCEB(1'b0),
.RSTRAMARSTRAM(rsta),
.RSTRAMB(rstb),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_SBITERR_UNCONNECTED ),
.WEA({wea,wea,wea,wea}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,web,web,web,web}));
endmodule
|
module zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_wrapper__parameterized0
(douta,
doutb,
clka,
clkb,
ena,
enb,
rsta,
rstb,
addra,
addrb,
dina,
dinb,
wea,
web);
output [1:0]douta;
output [1:0]doutb;
input clka;
input clkb;
input ena;
input enb;
input rsta;
input rstb;
input [13:0]addra;
input [13:0]addrb;
input [1:0]dina;
input [1:0]dinb;
input [0:0]wea;
input [0:0]web;
wire [13:0]addra;
wire [13:0]addrb;
wire clka;
wire clkb;
wire [1:0]dina;
wire [1:0]dinb;
wire [1:0]douta;
wire [1:0]doutb;
wire ena;
wire enb;
wire rsta;
wire rstb;
wire [0:0]wea;
wire [0:0]web;
wire \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_SBITERR_UNCONNECTED ;
wire [31:2]\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOADO_UNCONNECTED ;
wire [31:2]\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOBDO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPADOP_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_RDADDRECC_UNCONNECTED ;
(* bmm_info_memory_device = "[3:2][0:16383]" *)
(* box_type = "PRIMITIVE" *)
RAMB36E1 #(
.DOA_REG(0),
.DOB_REG(0),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
.READ_WIDTH_A(2),
.READ_WIDTH_B(2),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("WRITE_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(2),
.WRITE_WIDTH_B(2))
\DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram
(.ADDRARDADDR({1'b1,addra,1'b1}),
.ADDRBWRADDR({1'b1,addrb,1'b1}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(clka),
.CLKBWRCLK(clkb),
.DBITERR(\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,dina}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,dinb}),
.DIPADIP({1'b0,1'b0,1'b0,1'b0}),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO({\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOADO_UNCONNECTED [31:2],douta}),
.DOBDO({\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOBDO_UNCONNECTED [31:2],doutb}),
.DOPADOP(\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPADOP_UNCONNECTED [3:0]),
.DOPBDOP(\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPBDOP_UNCONNECTED [3:0]),
.ECCPARITY(\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(ena),
.ENBWREN(enb),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b0),
.REGCEB(1'b0),
.RSTRAMARSTRAM(rsta),
.RSTRAMB(rstb),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_SBITERR_UNCONNECTED ),
.WEA({wea,wea,wea,wea}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,web,web,web,web}));
endmodule
|
module zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_wrapper__parameterized1
(douta,
doutb,
clka,
clkb,
ena,
enb,
rsta,
rstb,
addra,
addrb,
dina,
dinb,
wea,
web);
output [1:0]douta;
output [1:0]doutb;
input clka;
input clkb;
input ena;
input enb;
input rsta;
input rstb;
input [13:0]addra;
input [13:0]addrb;
input [1:0]dina;
input [1:0]dinb;
input [0:0]wea;
input [0:0]web;
wire [13:0]addra;
wire [13:0]addrb;
wire clka;
wire clkb;
wire [1:0]dina;
wire [1:0]dinb;
wire [1:0]douta;
wire [1:0]doutb;
wire ena;
wire enb;
wire rsta;
wire rstb;
wire [0:0]wea;
wire [0:0]web;
wire \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_SBITERR_UNCONNECTED ;
wire [31:2]\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOADO_UNCONNECTED ;
wire [31:2]\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOBDO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPADOP_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_RDADDRECC_UNCONNECTED ;
(* bmm_info_memory_device = "[5:4][0:16383]" *)
(* box_type = "PRIMITIVE" *)
RAMB36E1 #(
.DOA_REG(0),
.DOB_REG(0),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
.READ_WIDTH_A(2),
.READ_WIDTH_B(2),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("WRITE_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(2),
.WRITE_WIDTH_B(2))
\DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram
(.ADDRARDADDR({1'b1,addra,1'b1}),
.ADDRBWRADDR({1'b1,addrb,1'b1}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(clka),
.CLKBWRCLK(clkb),
.DBITERR(\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,dina}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,dinb}),
.DIPADIP({1'b0,1'b0,1'b0,1'b0}),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO({\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOADO_UNCONNECTED [31:2],douta}),
.DOBDO({\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOBDO_UNCONNECTED [31:2],doutb}),
.DOPADOP(\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPADOP_UNCONNECTED [3:0]),
.DOPBDOP(\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPBDOP_UNCONNECTED [3:0]),
.ECCPARITY(\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(ena),
.ENBWREN(enb),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b0),
.REGCEB(1'b0),
.RSTRAMARSTRAM(rsta),
.RSTRAMB(rstb),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_SBITERR_UNCONNECTED ),
.WEA({wea,wea,wea,wea}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,web,web,web,web}));
endmodule
|
module zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_wrapper__parameterized10
(douta,
doutb,
clka,
clkb,
ena,
enb,
rsta,
rstb,
addra,
addrb,
dina,
dinb,
wea,
web);
output [1:0]douta;
output [1:0]doutb;
input clka;
input clkb;
input ena;
input enb;
input rsta;
input rstb;
input [13:0]addra;
input [13:0]addrb;
input [1:0]dina;
input [1:0]dinb;
input [0:0]wea;
input [0:0]web;
wire [13:0]addra;
wire [13:0]addrb;
wire clka;
wire clkb;
wire [1:0]dina;
wire [1:0]dinb;
wire [1:0]douta;
wire [1:0]doutb;
wire ena;
wire enb;
wire rsta;
wire rstb;
wire [0:0]wea;
wire [0:0]web;
wire \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_SBITERR_UNCONNECTED ;
wire [31:2]\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOADO_UNCONNECTED ;
wire [31:2]\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOBDO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPADOP_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_RDADDRECC_UNCONNECTED ;
(* bmm_info_memory_device = "[23:22][0:16383]" *)
(* box_type = "PRIMITIVE" *)
RAMB36E1 #(
.DOA_REG(0),
.DOB_REG(0),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
.READ_WIDTH_A(2),
.READ_WIDTH_B(2),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("WRITE_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(2),
.WRITE_WIDTH_B(2))
\DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram
(.ADDRARDADDR({1'b1,addra,1'b1}),
.ADDRBWRADDR({1'b1,addrb,1'b1}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(clka),
.CLKBWRCLK(clkb),
.DBITERR(\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,dina}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,dinb}),
.DIPADIP({1'b0,1'b0,1'b0,1'b0}),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO({\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOADO_UNCONNECTED [31:2],douta}),
.DOBDO({\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOBDO_UNCONNECTED [31:2],doutb}),
.DOPADOP(\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPADOP_UNCONNECTED [3:0]),
.DOPBDOP(\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPBDOP_UNCONNECTED [3:0]),
.ECCPARITY(\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(ena),
.ENBWREN(enb),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b0),
.REGCEB(1'b0),
.RSTRAMARSTRAM(rsta),
.RSTRAMB(rstb),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_SBITERR_UNCONNECTED ),
.WEA({wea,wea,wea,wea}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,web,web,web,web}));
endmodule
|
module zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_wrapper__parameterized11
(douta,
doutb,
clka,
clkb,
ena,
enb,
rsta,
rstb,
addra,
addrb,
dina,
dinb,
wea,
web);
output [1:0]douta;
output [1:0]doutb;
input clka;
input clkb;
input ena;
input enb;
input rsta;
input rstb;
input [13:0]addra;
input [13:0]addrb;
input [1:0]dina;
input [1:0]dinb;
input [0:0]wea;
input [0:0]web;
wire [13:0]addra;
wire [13:0]addrb;
wire clka;
wire clkb;
wire [1:0]dina;
wire [1:0]dinb;
wire [1:0]douta;
wire [1:0]doutb;
wire ena;
wire enb;
wire rsta;
wire rstb;
wire [0:0]wea;
wire [0:0]web;
wire \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_SBITERR_UNCONNECTED ;
wire [31:2]\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOADO_UNCONNECTED ;
wire [31:2]\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOBDO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPADOP_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_RDADDRECC_UNCONNECTED ;
(* bmm_info_memory_device = "[25:24][0:16383]" *)
(* box_type = "PRIMITIVE" *)
RAMB36E1 #(
.DOA_REG(0),
.DOB_REG(0),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
.READ_WIDTH_A(2),
.READ_WIDTH_B(2),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("WRITE_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(2),
.WRITE_WIDTH_B(2))
\DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram
(.ADDRARDADDR({1'b1,addra,1'b1}),
.ADDRBWRADDR({1'b1,addrb,1'b1}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(clka),
.CLKBWRCLK(clkb),
.DBITERR(\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,dina}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,dinb}),
.DIPADIP({1'b0,1'b0,1'b0,1'b0}),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO({\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOADO_UNCONNECTED [31:2],douta}),
.DOBDO({\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOBDO_UNCONNECTED [31:2],doutb}),
.DOPADOP(\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPADOP_UNCONNECTED [3:0]),
.DOPBDOP(\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPBDOP_UNCONNECTED [3:0]),
.ECCPARITY(\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(ena),
.ENBWREN(enb),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b0),
.REGCEB(1'b0),
.RSTRAMARSTRAM(rsta),
.RSTRAMB(rstb),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_SBITERR_UNCONNECTED ),
.WEA({wea,wea,wea,wea}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,web,web,web,web}));
endmodule
|
module zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_wrapper__parameterized12
(douta,
doutb,
clka,
clkb,
ena,
enb,
rsta,
rstb,
addra,
addrb,
dina,
dinb,
wea,
web);
output [1:0]douta;
output [1:0]doutb;
input clka;
input clkb;
input ena;
input enb;
input rsta;
input rstb;
input [13:0]addra;
input [13:0]addrb;
input [1:0]dina;
input [1:0]dinb;
input [0:0]wea;
input [0:0]web;
wire [13:0]addra;
wire [13:0]addrb;
wire clka;
wire clkb;
wire [1:0]dina;
wire [1:0]dinb;
wire [1:0]douta;
wire [1:0]doutb;
wire ena;
wire enb;
wire rsta;
wire rstb;
wire [0:0]wea;
wire [0:0]web;
wire \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_SBITERR_UNCONNECTED ;
wire [31:2]\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOADO_UNCONNECTED ;
wire [31:2]\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOBDO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPADOP_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_RDADDRECC_UNCONNECTED ;
(* bmm_info_memory_device = "[27:26][0:16383]" *)
(* box_type = "PRIMITIVE" *)
RAMB36E1 #(
.DOA_REG(0),
.DOB_REG(0),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
.READ_WIDTH_A(2),
.READ_WIDTH_B(2),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("WRITE_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(2),
.WRITE_WIDTH_B(2))
\DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram
(.ADDRARDADDR({1'b1,addra,1'b1}),
.ADDRBWRADDR({1'b1,addrb,1'b1}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(clka),
.CLKBWRCLK(clkb),
.DBITERR(\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,dina}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,dinb}),
.DIPADIP({1'b0,1'b0,1'b0,1'b0}),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO({\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOADO_UNCONNECTED [31:2],douta}),
.DOBDO({\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOBDO_UNCONNECTED [31:2],doutb}),
.DOPADOP(\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPADOP_UNCONNECTED [3:0]),
.DOPBDOP(\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPBDOP_UNCONNECTED [3:0]),
.ECCPARITY(\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(ena),
.ENBWREN(enb),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b0),
.REGCEB(1'b0),
.RSTRAMARSTRAM(rsta),
.RSTRAMB(rstb),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_SBITERR_UNCONNECTED ),
.WEA({wea,wea,wea,wea}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,web,web,web,web}));
endmodule
|
module zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_wrapper__parameterized13
(douta,
doutb,
clka,
clkb,
ena,
enb,
rsta,
rstb,
addra,
addrb,
dina,
dinb,
wea,
web);
output [1:0]douta;
output [1:0]doutb;
input clka;
input clkb;
input ena;
input enb;
input rsta;
input rstb;
input [13:0]addra;
input [13:0]addrb;
input [1:0]dina;
input [1:0]dinb;
input [0:0]wea;
input [0:0]web;
wire [13:0]addra;
wire [13:0]addrb;
wire clka;
wire clkb;
wire [1:0]dina;
wire [1:0]dinb;
wire [1:0]douta;
wire [1:0]doutb;
wire ena;
wire enb;
wire rsta;
wire rstb;
wire [0:0]wea;
wire [0:0]web;
wire \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_SBITERR_UNCONNECTED ;
wire [31:2]\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOADO_UNCONNECTED ;
wire [31:2]\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOBDO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPADOP_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_RDADDRECC_UNCONNECTED ;
(* bmm_info_memory_device = "[29:28][0:16383]" *)
(* box_type = "PRIMITIVE" *)
RAMB36E1 #(
.DOA_REG(0),
.DOB_REG(0),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
.READ_WIDTH_A(2),
.READ_WIDTH_B(2),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("WRITE_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(2),
.WRITE_WIDTH_B(2))
\DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram
(.ADDRARDADDR({1'b1,addra,1'b1}),
.ADDRBWRADDR({1'b1,addrb,1'b1}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(clka),
.CLKBWRCLK(clkb),
.DBITERR(\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,dina}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,dinb}),
.DIPADIP({1'b0,1'b0,1'b0,1'b0}),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO({\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOADO_UNCONNECTED [31:2],douta}),
.DOBDO({\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOBDO_UNCONNECTED [31:2],doutb}),
.DOPADOP(\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPADOP_UNCONNECTED [3:0]),
.DOPBDOP(\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPBDOP_UNCONNECTED [3:0]),
.ECCPARITY(\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(ena),
.ENBWREN(enb),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b0),
.REGCEB(1'b0),
.RSTRAMARSTRAM(rsta),
.RSTRAMB(rstb),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_SBITERR_UNCONNECTED ),
.WEA({wea,wea,wea,wea}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,web,web,web,web}));
endmodule
|
module zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_wrapper__parameterized14
(douta,
doutb,
clka,
clkb,
ena,
enb,
rsta,
rstb,
addra,
addrb,
dina,
dinb,
wea,
web);
output [1:0]douta;
output [1:0]doutb;
input clka;
input clkb;
input ena;
input enb;
input rsta;
input rstb;
input [13:0]addra;
input [13:0]addrb;
input [1:0]dina;
input [1:0]dinb;
input [0:0]wea;
input [0:0]web;
wire [13:0]addra;
wire [13:0]addrb;
wire clka;
wire clkb;
wire [1:0]dina;
wire [1:0]dinb;
wire [1:0]douta;
wire [1:0]doutb;
wire ena;
wire enb;
wire rsta;
wire rstb;
wire [0:0]wea;
wire [0:0]web;
wire \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_SBITERR_UNCONNECTED ;
wire [31:2]\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOADO_UNCONNECTED ;
wire [31:2]\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOBDO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPADOP_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_RDADDRECC_UNCONNECTED ;
(* bmm_info_memory_device = "[31:30][0:16383]" *)
(* box_type = "PRIMITIVE" *)
RAMB36E1 #(
.DOA_REG(0),
.DOB_REG(0),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
.READ_WIDTH_A(2),
.READ_WIDTH_B(2),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("WRITE_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(2),
.WRITE_WIDTH_B(2))
\DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram
(.ADDRARDADDR({1'b1,addra,1'b1}),
.ADDRBWRADDR({1'b1,addrb,1'b1}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(clka),
.CLKBWRCLK(clkb),
.DBITERR(\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,dina}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,dinb}),
.DIPADIP({1'b0,1'b0,1'b0,1'b0}),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO({\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOADO_UNCONNECTED [31:2],douta}),
.DOBDO({\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOBDO_UNCONNECTED [31:2],doutb}),
.DOPADOP(\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPADOP_UNCONNECTED [3:0]),
.DOPBDOP(\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPBDOP_UNCONNECTED [3:0]),
.ECCPARITY(\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(ena),
.ENBWREN(enb),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b0),
.REGCEB(1'b0),
.RSTRAMARSTRAM(rsta),
.RSTRAMB(rstb),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_SBITERR_UNCONNECTED ),
.WEA({wea,wea,wea,wea}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,web,web,web,web}));
endmodule
|
module zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_wrapper__parameterized2
(douta,
doutb,
clka,
clkb,
ena,
enb,
rsta,
rstb,
addra,
addrb,
dina,
dinb,
wea,
web);
output [1:0]douta;
output [1:0]doutb;
input clka;
input clkb;
input ena;
input enb;
input rsta;
input rstb;
input [13:0]addra;
input [13:0]addrb;
input [1:0]dina;
input [1:0]dinb;
input [0:0]wea;
input [0:0]web;
wire [13:0]addra;
wire [13:0]addrb;
wire clka;
wire clkb;
wire [1:0]dina;
wire [1:0]dinb;
wire [1:0]douta;
wire [1:0]doutb;
wire ena;
wire enb;
wire rsta;
wire rstb;
wire [0:0]wea;
wire [0:0]web;
wire \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_SBITERR_UNCONNECTED ;
wire [31:2]\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOADO_UNCONNECTED ;
wire [31:2]\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOBDO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPADOP_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_RDADDRECC_UNCONNECTED ;
(* bmm_info_memory_device = "[7:6][0:16383]" *)
(* box_type = "PRIMITIVE" *)
RAMB36E1 #(
.DOA_REG(0),
.DOB_REG(0),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
.READ_WIDTH_A(2),
.READ_WIDTH_B(2),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("WRITE_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(2),
.WRITE_WIDTH_B(2))
\DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram
(.ADDRARDADDR({1'b1,addra,1'b1}),
.ADDRBWRADDR({1'b1,addrb,1'b1}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(clka),
.CLKBWRCLK(clkb),
.DBITERR(\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,dina}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,dinb}),
.DIPADIP({1'b0,1'b0,1'b0,1'b0}),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO({\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOADO_UNCONNECTED [31:2],douta}),
.DOBDO({\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOBDO_UNCONNECTED [31:2],doutb}),
.DOPADOP(\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPADOP_UNCONNECTED [3:0]),
.DOPBDOP(\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPBDOP_UNCONNECTED [3:0]),
.ECCPARITY(\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(ena),
.ENBWREN(enb),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b0),
.REGCEB(1'b0),
.RSTRAMARSTRAM(rsta),
.RSTRAMB(rstb),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_SBITERR_UNCONNECTED ),
.WEA({wea,wea,wea,wea}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,web,web,web,web}));
endmodule
|
module zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_wrapper__parameterized3
(douta,
doutb,
clka,
clkb,
ena,
enb,
rsta,
rstb,
addra,
addrb,
dina,
dinb,
wea,
web);
output [1:0]douta;
output [1:0]doutb;
input clka;
input clkb;
input ena;
input enb;
input rsta;
input rstb;
input [13:0]addra;
input [13:0]addrb;
input [1:0]dina;
input [1:0]dinb;
input [0:0]wea;
input [0:0]web;
wire [13:0]addra;
wire [13:0]addrb;
wire clka;
wire clkb;
wire [1:0]dina;
wire [1:0]dinb;
wire [1:0]douta;
wire [1:0]doutb;
wire ena;
wire enb;
wire rsta;
wire rstb;
wire [0:0]wea;
wire [0:0]web;
wire \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_SBITERR_UNCONNECTED ;
wire [31:2]\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOADO_UNCONNECTED ;
wire [31:2]\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOBDO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPADOP_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_RDADDRECC_UNCONNECTED ;
(* bmm_info_memory_device = "[9:8][0:16383]" *)
(* box_type = "PRIMITIVE" *)
RAMB36E1 #(
.DOA_REG(0),
.DOB_REG(0),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
.READ_WIDTH_A(2),
.READ_WIDTH_B(2),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("WRITE_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(2),
.WRITE_WIDTH_B(2))
\DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram
(.ADDRARDADDR({1'b1,addra,1'b1}),
.ADDRBWRADDR({1'b1,addrb,1'b1}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(clka),
.CLKBWRCLK(clkb),
.DBITERR(\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,dina}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,dinb}),
.DIPADIP({1'b0,1'b0,1'b0,1'b0}),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO({\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOADO_UNCONNECTED [31:2],douta}),
.DOBDO({\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOBDO_UNCONNECTED [31:2],doutb}),
.DOPADOP(\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPADOP_UNCONNECTED [3:0]),
.DOPBDOP(\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPBDOP_UNCONNECTED [3:0]),
.ECCPARITY(\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(ena),
.ENBWREN(enb),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b0),
.REGCEB(1'b0),
.RSTRAMARSTRAM(rsta),
.RSTRAMB(rstb),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_SBITERR_UNCONNECTED ),
.WEA({wea,wea,wea,wea}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,web,web,web,web}));
endmodule
|
module zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_wrapper__parameterized4
(douta,
doutb,
clka,
clkb,
ena,
enb,
rsta,
rstb,
addra,
addrb,
dina,
dinb,
wea,
web);
output [1:0]douta;
output [1:0]doutb;
input clka;
input clkb;
input ena;
input enb;
input rsta;
input rstb;
input [13:0]addra;
input [13:0]addrb;
input [1:0]dina;
input [1:0]dinb;
input [0:0]wea;
input [0:0]web;
wire [13:0]addra;
wire [13:0]addrb;
wire clka;
wire clkb;
wire [1:0]dina;
wire [1:0]dinb;
wire [1:0]douta;
wire [1:0]doutb;
wire ena;
wire enb;
wire rsta;
wire rstb;
wire [0:0]wea;
wire [0:0]web;
wire \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_SBITERR_UNCONNECTED ;
wire [31:2]\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOADO_UNCONNECTED ;
wire [31:2]\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOBDO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPADOP_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_RDADDRECC_UNCONNECTED ;
(* bmm_info_memory_device = "[11:10][0:16383]" *)
(* box_type = "PRIMITIVE" *)
RAMB36E1 #(
.DOA_REG(0),
.DOB_REG(0),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
.READ_WIDTH_A(2),
.READ_WIDTH_B(2),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("WRITE_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(2),
.WRITE_WIDTH_B(2))
\DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram
(.ADDRARDADDR({1'b1,addra,1'b1}),
.ADDRBWRADDR({1'b1,addrb,1'b1}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(clka),
.CLKBWRCLK(clkb),
.DBITERR(\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,dina}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,dinb}),
.DIPADIP({1'b0,1'b0,1'b0,1'b0}),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO({\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOADO_UNCONNECTED [31:2],douta}),
.DOBDO({\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOBDO_UNCONNECTED [31:2],doutb}),
.DOPADOP(\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPADOP_UNCONNECTED [3:0]),
.DOPBDOP(\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPBDOP_UNCONNECTED [3:0]),
.ECCPARITY(\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(ena),
.ENBWREN(enb),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b0),
.REGCEB(1'b0),
.RSTRAMARSTRAM(rsta),
.RSTRAMB(rstb),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_SBITERR_UNCONNECTED ),
.WEA({wea,wea,wea,wea}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,web,web,web,web}));
endmodule
|
module zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_wrapper__parameterized5
(douta,
doutb,
clka,
clkb,
ena,
enb,
rsta,
rstb,
addra,
addrb,
dina,
dinb,
wea,
web);
output [1:0]douta;
output [1:0]doutb;
input clka;
input clkb;
input ena;
input enb;
input rsta;
input rstb;
input [13:0]addra;
input [13:0]addrb;
input [1:0]dina;
input [1:0]dinb;
input [0:0]wea;
input [0:0]web;
wire [13:0]addra;
wire [13:0]addrb;
wire clka;
wire clkb;
wire [1:0]dina;
wire [1:0]dinb;
wire [1:0]douta;
wire [1:0]doutb;
wire ena;
wire enb;
wire rsta;
wire rstb;
wire [0:0]wea;
wire [0:0]web;
wire \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_SBITERR_UNCONNECTED ;
wire [31:2]\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOADO_UNCONNECTED ;
wire [31:2]\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOBDO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPADOP_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_RDADDRECC_UNCONNECTED ;
(* bmm_info_memory_device = "[13:12][0:16383]" *)
(* box_type = "PRIMITIVE" *)
RAMB36E1 #(
.DOA_REG(0),
.DOB_REG(0),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
.READ_WIDTH_A(2),
.READ_WIDTH_B(2),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("WRITE_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(2),
.WRITE_WIDTH_B(2))
\DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram
(.ADDRARDADDR({1'b1,addra,1'b1}),
.ADDRBWRADDR({1'b1,addrb,1'b1}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(clka),
.CLKBWRCLK(clkb),
.DBITERR(\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,dina}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,dinb}),
.DIPADIP({1'b0,1'b0,1'b0,1'b0}),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO({\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOADO_UNCONNECTED [31:2],douta}),
.DOBDO({\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOBDO_UNCONNECTED [31:2],doutb}),
.DOPADOP(\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPADOP_UNCONNECTED [3:0]),
.DOPBDOP(\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPBDOP_UNCONNECTED [3:0]),
.ECCPARITY(\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(ena),
.ENBWREN(enb),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b0),
.REGCEB(1'b0),
.RSTRAMARSTRAM(rsta),
.RSTRAMB(rstb),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_SBITERR_UNCONNECTED ),
.WEA({wea,wea,wea,wea}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,web,web,web,web}));
endmodule
|
module zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_wrapper__parameterized6
(douta,
doutb,
clka,
clkb,
ena,
enb,
rsta,
rstb,
addra,
addrb,
dina,
dinb,
wea,
web);
output [1:0]douta;
output [1:0]doutb;
input clka;
input clkb;
input ena;
input enb;
input rsta;
input rstb;
input [13:0]addra;
input [13:0]addrb;
input [1:0]dina;
input [1:0]dinb;
input [0:0]wea;
input [0:0]web;
wire [13:0]addra;
wire [13:0]addrb;
wire clka;
wire clkb;
wire [1:0]dina;
wire [1:0]dinb;
wire [1:0]douta;
wire [1:0]doutb;
wire ena;
wire enb;
wire rsta;
wire rstb;
wire [0:0]wea;
wire [0:0]web;
wire \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_SBITERR_UNCONNECTED ;
wire [31:2]\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOADO_UNCONNECTED ;
wire [31:2]\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOBDO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPADOP_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_RDADDRECC_UNCONNECTED ;
(* bmm_info_memory_device = "[15:14][0:16383]" *)
(* box_type = "PRIMITIVE" *)
RAMB36E1 #(
.DOA_REG(0),
.DOB_REG(0),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
.READ_WIDTH_A(2),
.READ_WIDTH_B(2),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("WRITE_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(2),
.WRITE_WIDTH_B(2))
\DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram
(.ADDRARDADDR({1'b1,addra,1'b1}),
.ADDRBWRADDR({1'b1,addrb,1'b1}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(clka),
.CLKBWRCLK(clkb),
.DBITERR(\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,dina}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,dinb}),
.DIPADIP({1'b0,1'b0,1'b0,1'b0}),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO({\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOADO_UNCONNECTED [31:2],douta}),
.DOBDO({\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOBDO_UNCONNECTED [31:2],doutb}),
.DOPADOP(\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPADOP_UNCONNECTED [3:0]),
.DOPBDOP(\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPBDOP_UNCONNECTED [3:0]),
.ECCPARITY(\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(ena),
.ENBWREN(enb),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b0),
.REGCEB(1'b0),
.RSTRAMARSTRAM(rsta),
.RSTRAMB(rstb),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_SBITERR_UNCONNECTED ),
.WEA({wea,wea,wea,wea}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,web,web,web,web}));
endmodule
|
module zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_wrapper__parameterized7
(douta,
doutb,
clka,
clkb,
ena,
enb,
rsta,
rstb,
addra,
addrb,
dina,
dinb,
wea,
web);
output [1:0]douta;
output [1:0]doutb;
input clka;
input clkb;
input ena;
input enb;
input rsta;
input rstb;
input [13:0]addra;
input [13:0]addrb;
input [1:0]dina;
input [1:0]dinb;
input [0:0]wea;
input [0:0]web;
wire [13:0]addra;
wire [13:0]addrb;
wire clka;
wire clkb;
wire [1:0]dina;
wire [1:0]dinb;
wire [1:0]douta;
wire [1:0]doutb;
wire ena;
wire enb;
wire rsta;
wire rstb;
wire [0:0]wea;
wire [0:0]web;
wire \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_SBITERR_UNCONNECTED ;
wire [31:2]\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOADO_UNCONNECTED ;
wire [31:2]\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOBDO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPADOP_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_RDADDRECC_UNCONNECTED ;
(* bmm_info_memory_device = "[17:16][0:16383]" *)
(* box_type = "PRIMITIVE" *)
RAMB36E1 #(
.DOA_REG(0),
.DOB_REG(0),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
.READ_WIDTH_A(2),
.READ_WIDTH_B(2),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("WRITE_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(2),
.WRITE_WIDTH_B(2))
\DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram
(.ADDRARDADDR({1'b1,addra,1'b1}),
.ADDRBWRADDR({1'b1,addrb,1'b1}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(clka),
.CLKBWRCLK(clkb),
.DBITERR(\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,dina}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,dinb}),
.DIPADIP({1'b0,1'b0,1'b0,1'b0}),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO({\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOADO_UNCONNECTED [31:2],douta}),
.DOBDO({\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOBDO_UNCONNECTED [31:2],doutb}),
.DOPADOP(\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPADOP_UNCONNECTED [3:0]),
.DOPBDOP(\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPBDOP_UNCONNECTED [3:0]),
.ECCPARITY(\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(ena),
.ENBWREN(enb),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b0),
.REGCEB(1'b0),
.RSTRAMARSTRAM(rsta),
.RSTRAMB(rstb),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_SBITERR_UNCONNECTED ),
.WEA({wea,wea,wea,wea}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,web,web,web,web}));
endmodule
|
module zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_wrapper__parameterized8
(douta,
doutb,
clka,
clkb,
ena,
enb,
rsta,
rstb,
addra,
addrb,
dina,
dinb,
wea,
web);
output [1:0]douta;
output [1:0]doutb;
input clka;
input clkb;
input ena;
input enb;
input rsta;
input rstb;
input [13:0]addra;
input [13:0]addrb;
input [1:0]dina;
input [1:0]dinb;
input [0:0]wea;
input [0:0]web;
wire [13:0]addra;
wire [13:0]addrb;
wire clka;
wire clkb;
wire [1:0]dina;
wire [1:0]dinb;
wire [1:0]douta;
wire [1:0]doutb;
wire ena;
wire enb;
wire rsta;
wire rstb;
wire [0:0]wea;
wire [0:0]web;
wire \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_SBITERR_UNCONNECTED ;
wire [31:2]\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOADO_UNCONNECTED ;
wire [31:2]\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOBDO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPADOP_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_RDADDRECC_UNCONNECTED ;
(* bmm_info_memory_device = "[19:18][0:16383]" *)
(* box_type = "PRIMITIVE" *)
RAMB36E1 #(
.DOA_REG(0),
.DOB_REG(0),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
.READ_WIDTH_A(2),
.READ_WIDTH_B(2),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("WRITE_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(2),
.WRITE_WIDTH_B(2))
\DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram
(.ADDRARDADDR({1'b1,addra,1'b1}),
.ADDRBWRADDR({1'b1,addrb,1'b1}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(clka),
.CLKBWRCLK(clkb),
.DBITERR(\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,dina}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,dinb}),
.DIPADIP({1'b0,1'b0,1'b0,1'b0}),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO({\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOADO_UNCONNECTED [31:2],douta}),
.DOBDO({\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOBDO_UNCONNECTED [31:2],doutb}),
.DOPADOP(\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPADOP_UNCONNECTED [3:0]),
.DOPBDOP(\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPBDOP_UNCONNECTED [3:0]),
.ECCPARITY(\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(ena),
.ENBWREN(enb),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b0),
.REGCEB(1'b0),
.RSTRAMARSTRAM(rsta),
.RSTRAMB(rstb),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_SBITERR_UNCONNECTED ),
.WEA({wea,wea,wea,wea}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,web,web,web,web}));
endmodule
|
module zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_wrapper__parameterized9
(douta,
doutb,
clka,
clkb,
ena,
enb,
rsta,
rstb,
addra,
addrb,
dina,
dinb,
wea,
web);
output [1:0]douta;
output [1:0]doutb;
input clka;
input clkb;
input ena;
input enb;
input rsta;
input rstb;
input [13:0]addra;
input [13:0]addrb;
input [1:0]dina;
input [1:0]dinb;
input [0:0]wea;
input [0:0]web;
wire [13:0]addra;
wire [13:0]addrb;
wire clka;
wire clkb;
wire [1:0]dina;
wire [1:0]dinb;
wire [1:0]douta;
wire [1:0]doutb;
wire ena;
wire enb;
wire rsta;
wire rstb;
wire [0:0]wea;
wire [0:0]web;
wire \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_SBITERR_UNCONNECTED ;
wire [31:2]\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOADO_UNCONNECTED ;
wire [31:2]\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOBDO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPADOP_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_RDADDRECC_UNCONNECTED ;
(* bmm_info_memory_device = "[21:20][0:16383]" *)
(* box_type = "PRIMITIVE" *)
RAMB36E1 #(
.DOA_REG(0),
.DOB_REG(0),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
.READ_WIDTH_A(2),
.READ_WIDTH_B(2),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("WRITE_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(2),
.WRITE_WIDTH_B(2))
\DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram
(.ADDRARDADDR({1'b1,addra,1'b1}),
.ADDRBWRADDR({1'b1,addrb,1'b1}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(clka),
.CLKBWRCLK(clkb),
.DBITERR(\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,dina}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,dinb}),
.DIPADIP({1'b0,1'b0,1'b0,1'b0}),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO({\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOADO_UNCONNECTED [31:2],douta}),
.DOBDO({\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOBDO_UNCONNECTED [31:2],doutb}),
.DOPADOP(\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPADOP_UNCONNECTED [3:0]),
.DOPBDOP(\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPBDOP_UNCONNECTED [3:0]),
.ECCPARITY(\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(ena),
.ENBWREN(enb),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b0),
.REGCEB(1'b0),
.RSTRAMARSTRAM(rsta),
.RSTRAMB(rstb),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_SBITERR_UNCONNECTED ),
.WEA({wea,wea,wea,wea}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,web,web,web,web}));
endmodule
|
module zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_top
(douta,
doutb,
clka,
clkb,
ena,
enb,
rsta,
rstb,
addra,
addrb,
dina,
dinb,
wea,
web);
output [31:0]douta;
output [31:0]doutb;
input clka;
input clkb;
input ena;
input enb;
input rsta;
input rstb;
input [13:0]addra;
input [13:0]addrb;
input [31:0]dina;
input [31:0]dinb;
input [3:0]wea;
input [3:0]web;
wire [13:0]addra;
wire [13:0]addrb;
wire clka;
wire clkb;
wire [31:0]dina;
wire [31:0]dinb;
wire [31:0]douta;
wire [31:0]doutb;
wire ena;
wire enb;
wire rsta;
wire rstb;
wire [3:0]wea;
wire [3:0]web;
zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_generic_cstr \valid.cstr
(.addra(addra),
.addrb(addrb),
.clka(clka),
.clkb(clkb),
.dina(dina),
.dinb(dinb),
.douta(douta),
.doutb(doutb),
.ena(ena),
.enb(enb),
.rsta(rsta),
.rstb(rstb),
.wea(wea),
.web(web));
endmodule
|
module zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_v8_3_6
(clka,
rsta,
ena,
regcea,
wea,
addra,
dina,
douta,
clkb,
rstb,
enb,
regceb,
web,
addrb,
dinb,
doutb,
injectsbiterr,
injectdbiterr,
eccpipece,
sbiterr,
dbiterr,
rdaddrecc,
sleep,
deepsleep,
shutdown,
rsta_busy,
rstb_busy,
s_aclk,
s_aresetn,
s_axi_awid,
s_axi_awaddr,
s_axi_awlen,
s_axi_awsize,
s_axi_awburst,
s_axi_awvalid,
s_axi_awready,
s_axi_wdata,
s_axi_wstrb,
s_axi_wlast,
s_axi_wvalid,
s_axi_wready,
s_axi_bid,
s_axi_bresp,
s_axi_bvalid,
s_axi_bready,
s_axi_arid,
s_axi_araddr,
s_axi_arlen,
s_axi_arsize,
s_axi_arburst,
s_axi_arvalid,
s_axi_arready,
s_axi_rid,
s_axi_rdata,
s_axi_rresp,
s_axi_rlast,
s_axi_rvalid,
s_axi_rready,
s_axi_injectsbiterr,
s_axi_injectdbiterr,
s_axi_sbiterr,
s_axi_dbiterr,
s_axi_rdaddrecc);
input clka;
input rsta;
input ena;
input regcea;
input [3:0]wea;
input [31:0]addra;
input [31:0]dina;
output [31:0]douta;
input clkb;
input rstb;
input enb;
input regceb;
input [3:0]web;
input [31:0]addrb;
input [31:0]dinb;
output [31:0]doutb;
input injectsbiterr;
input injectdbiterr;
input eccpipece;
output sbiterr;
output dbiterr;
output [31:0]rdaddrecc;
input sleep;
input deepsleep;
input shutdown;
output rsta_busy;
output rstb_busy;
input s_aclk;
input s_aresetn;
input [3:0]s_axi_awid;
input [31:0]s_axi_awaddr;
input [7:0]s_axi_awlen;
input [2:0]s_axi_awsize;
input [1:0]s_axi_awburst;
input s_axi_awvalid;
output s_axi_awready;
input [31:0]s_axi_wdata;
input [3:0]s_axi_wstrb;
input s_axi_wlast;
input s_axi_wvalid;
output s_axi_wready;
output [3:0]s_axi_bid;
output [1:0]s_axi_bresp;
output s_axi_bvalid;
input s_axi_bready;
input [3:0]s_axi_arid;
input [31:0]s_axi_araddr;
input [7:0]s_axi_arlen;
input [2:0]s_axi_arsize;
input [1:0]s_axi_arburst;
input s_axi_arvalid;
output s_axi_arready;
output [3:0]s_axi_rid;
output [31:0]s_axi_rdata;
output [1:0]s_axi_rresp;
output s_axi_rlast;
output s_axi_rvalid;
input s_axi_rready;
input s_axi_injectsbiterr;
input s_axi_injectdbiterr;
output s_axi_sbiterr;
output s_axi_dbiterr;
output [31:0]s_axi_rdaddrecc;
wire \<const0> ;
wire [31:0]addra;
wire [31:0]addrb;
wire clka;
wire clkb;
wire [31:0]dina;
wire [31:0]dinb;
wire [31:0]douta;
wire [31:0]doutb;
wire ena;
wire enb;
wire rsta;
wire rstb;
wire [3:0]wea;
wire [3:0]web;
assign dbiterr = \<const0> ;
assign rdaddrecc[31] = \<const0> ;
assign rdaddrecc[30] = \<const0> ;
assign rdaddrecc[29] = \<const0> ;
assign rdaddrecc[28] = \<const0> ;
assign rdaddrecc[27] = \<const0> ;
assign rdaddrecc[26] = \<const0> ;
assign rdaddrecc[25] = \<const0> ;
assign rdaddrecc[24] = \<const0> ;
assign rdaddrecc[23] = \<const0> ;
assign rdaddrecc[22] = \<const0> ;
assign rdaddrecc[21] = \<const0> ;
assign rdaddrecc[20] = \<const0> ;
assign rdaddrecc[19] = \<const0> ;
assign rdaddrecc[18] = \<const0> ;
assign rdaddrecc[17] = \<const0> ;
assign rdaddrecc[16] = \<const0> ;
assign rdaddrecc[15] = \<const0> ;
assign rdaddrecc[14] = \<const0> ;
assign rdaddrecc[13] = \<const0> ;
assign rdaddrecc[12] = \<const0> ;
assign rdaddrecc[11] = \<const0> ;
assign rdaddrecc[10] = \<const0> ;
assign rdaddrecc[9] = \<const0> ;
assign rdaddrecc[8] = \<const0> ;
assign rdaddrecc[7] = \<const0> ;
assign rdaddrecc[6] = \<const0> ;
assign rdaddrecc[5] = \<const0> ;
assign rdaddrecc[4] = \<const0> ;
assign rdaddrecc[3] = \<const0> ;
assign rdaddrecc[2] = \<const0> ;
assign rdaddrecc[1] = \<const0> ;
assign rdaddrecc[0] = \<const0> ;
assign rsta_busy = \<const0> ;
assign rstb_busy = \<const0> ;
assign s_axi_arready = \<const0> ;
assign s_axi_awready = \<const0> ;
assign s_axi_bid[3] = \<const0> ;
assign s_axi_bid[2] = \<const0> ;
assign s_axi_bid[1] = \<const0> ;
assign s_axi_bid[0] = \<const0> ;
assign s_axi_bresp[1] = \<const0> ;
assign s_axi_bresp[0] = \<const0> ;
assign s_axi_bvalid = \<const0> ;
assign s_axi_dbiterr = \<const0> ;
assign s_axi_rdaddrecc[31] = \<const0> ;
assign s_axi_rdaddrecc[30] = \<const0> ;
assign s_axi_rdaddrecc[29] = \<const0> ;
assign s_axi_rdaddrecc[28] = \<const0> ;
assign s_axi_rdaddrecc[27] = \<const0> ;
assign s_axi_rdaddrecc[26] = \<const0> ;
assign s_axi_rdaddrecc[25] = \<const0> ;
assign s_axi_rdaddrecc[24] = \<const0> ;
assign s_axi_rdaddrecc[23] = \<const0> ;
assign s_axi_rdaddrecc[22] = \<const0> ;
assign s_axi_rdaddrecc[21] = \<const0> ;
assign s_axi_rdaddrecc[20] = \<const0> ;
assign s_axi_rdaddrecc[19] = \<const0> ;
assign s_axi_rdaddrecc[18] = \<const0> ;
assign s_axi_rdaddrecc[17] = \<const0> ;
assign s_axi_rdaddrecc[16] = \<const0> ;
assign s_axi_rdaddrecc[15] = \<const0> ;
assign s_axi_rdaddrecc[14] = \<const0> ;
assign s_axi_rdaddrecc[13] = \<const0> ;
assign s_axi_rdaddrecc[12] = \<const0> ;
assign s_axi_rdaddrecc[11] = \<const0> ;
assign s_axi_rdaddrecc[10] = \<const0> ;
assign s_axi_rdaddrecc[9] = \<const0> ;
assign s_axi_rdaddrecc[8] = \<const0> ;
assign s_axi_rdaddrecc[7] = \<const0> ;
assign s_axi_rdaddrecc[6] = \<const0> ;
assign s_axi_rdaddrecc[5] = \<const0> ;
assign s_axi_rdaddrecc[4] = \<const0> ;
assign s_axi_rdaddrecc[3] = \<const0> ;
assign s_axi_rdaddrecc[2] = \<const0> ;
assign s_axi_rdaddrecc[1] = \<const0> ;
assign s_axi_rdaddrecc[0] = \<const0> ;
assign s_axi_rdata[31] = \<const0> ;
assign s_axi_rdata[30] = \<const0> ;
assign s_axi_rdata[29] = \<const0> ;
assign s_axi_rdata[28] = \<const0> ;
assign s_axi_rdata[27] = \<const0> ;
assign s_axi_rdata[26] = \<const0> ;
assign s_axi_rdata[25] = \<const0> ;
assign s_axi_rdata[24] = \<const0> ;
assign s_axi_rdata[23] = \<const0> ;
assign s_axi_rdata[22] = \<const0> ;
assign s_axi_rdata[21] = \<const0> ;
assign s_axi_rdata[20] = \<const0> ;
assign s_axi_rdata[19] = \<const0> ;
assign s_axi_rdata[18] = \<const0> ;
assign s_axi_rdata[17] = \<const0> ;
assign s_axi_rdata[16] = \<const0> ;
assign s_axi_rdata[15] = \<const0> ;
assign s_axi_rdata[14] = \<const0> ;
assign s_axi_rdata[13] = \<const0> ;
assign s_axi_rdata[12] = \<const0> ;
assign s_axi_rdata[11] = \<const0> ;
assign s_axi_rdata[10] = \<const0> ;
assign s_axi_rdata[9] = \<const0> ;
assign s_axi_rdata[8] = \<const0> ;
assign s_axi_rdata[7] = \<const0> ;
assign s_axi_rdata[6] = \<const0> ;
assign s_axi_rdata[5] = \<const0> ;
assign s_axi_rdata[4] = \<const0> ;
assign s_axi_rdata[3] = \<const0> ;
assign s_axi_rdata[2] = \<const0> ;
assign s_axi_rdata[1] = \<const0> ;
assign s_axi_rdata[0] = \<const0> ;
assign s_axi_rid[3] = \<const0> ;
assign s_axi_rid[2] = \<const0> ;
assign s_axi_rid[1] = \<const0> ;
assign s_axi_rid[0] = \<const0> ;
assign s_axi_rlast = \<const0> ;
assign s_axi_rresp[1] = \<const0> ;
assign s_axi_rresp[0] = \<const0> ;
assign s_axi_rvalid = \<const0> ;
assign s_axi_sbiterr = \<const0> ;
assign s_axi_wready = \<const0> ;
assign sbiterr = \<const0> ;
GND GND
(.G(\<const0> ));
zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_v8_3_6_synth inst_blk_mem_gen
(.addra(addra[15:2]),
.addrb(addrb[15:2]),
.clka(clka),
.clkb(clkb),
.dina(dina),
.dinb(dinb),
.douta(douta),
.doutb(doutb),
.ena(ena),
.enb(enb),
.rsta(rsta),
.rstb(rstb),
.wea(wea),
.web(web));
endmodule
|
module zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_v8_3_6_synth
(douta,
doutb,
clka,
clkb,
ena,
enb,
rsta,
rstb,
addra,
addrb,
dina,
dinb,
wea,
web);
output [31:0]douta;
output [31:0]doutb;
input clka;
input clkb;
input ena;
input enb;
input rsta;
input rstb;
input [13:0]addra;
input [13:0]addrb;
input [31:0]dina;
input [31:0]dinb;
input [3:0]wea;
input [3:0]web;
wire [13:0]addra;
wire [13:0]addrb;
wire clka;
wire clkb;
wire [31:0]dina;
wire [31:0]dinb;
wire [31:0]douta;
wire [31:0]doutb;
wire ena;
wire enb;
wire rsta;
wire rstb;
wire [3:0]wea;
wire [3:0]web;
zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_top \gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen
(.addra(addra),
.addrb(addrb),
.clka(clka),
.clkb(clkb),
.dina(dina),
.dinb(dinb),
.douta(douta),
.doutb(doutb),
.ena(ena),
.enb(enb),
.rsta(rsta),
.rstb(rstb),
.wea(wea),
.web(web));
endmodule
|
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (strong1, weak0) GSR = GSR_int;
assign (strong1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
|
module sky130_fd_sc_hdll__clkinvlp (
Y ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
|
module th22 ( y, a, b );
output y;
input a, b;
specify
specparam CDS_LIBNAME = "static";
specparam CDS_CELLNAME = "th22";
specparam CDS_VIEWNAME = "schematic";
endspecify
pfet_b P4 ( .b(cds_globals.vdd_), .g(a), .s(cds_globals.vdd_),
.d(net24));
pfet_b P3 ( .b(cds_globals.vdd_), .g(y), .s(net24), .d(net15));
pfet_b P2 ( .b(cds_globals.vdd_), .g(b), .s(cds_globals.vdd_),
.d(net24));
pfet_b P1 ( .b(cds_globals.vdd_), .g(b), .s(net35), .d(net15));
pfet_b P0 ( .b(cds_globals.vdd_), .g(a), .s(cds_globals.vdd_),
.d(net35));
nfet_b N4 ( .d(net22), .g(b), .s(cds_globals.gnd_),
.b(cds_globals.gnd_));
nfet_b N3 ( .d(net22), .g(a), .s(cds_globals.gnd_),
.b(cds_globals.gnd_));
nfet_b N2 ( .d(net15), .g(y), .s(net22), .b(cds_globals.gnd_));
nfet_b N1 ( .d(net34), .g(a), .s(cds_globals.gnd_),
.b(cds_globals.gnd_));
nfet_b N0 ( .d(net15), .g(b), .s(net34), .b(cds_globals.gnd_));
inv I8 ( y, net15);
endmodule
|
module sky130_fd_sc_hs__mux2i_4 (
Y ,
A0 ,
A1 ,
S ,
VPWR,
VGND
);
output Y ;
input A0 ;
input A1 ;
input S ;
input VPWR;
input VGND;
sky130_fd_sc_hs__mux2i base (
.Y(Y),
.A0(A0),
.A1(A1),
.S(S),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
|
module sky130_fd_sc_hs__mux2i_4 (
Y ,
A0,
A1,
S
);
output Y ;
input A0;
input A1;
input S ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__mux2i base (
.Y(Y),
.A0(A0),
.A1(A1),
.S(S)
);
endmodule
|
module sky130_fd_sc_hs__a222oi (
Y ,
A1 ,
A2 ,
B1 ,
B2 ,
C1 ,
C2 ,
VPWR,
VGND
);
// Module ports
output Y ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input C1 ;
input C2 ;
input VPWR;
input VGND;
// Local signals
wire B2 nand0_out ;
wire B2 nand1_out ;
wire B2 nand2_out ;
wire and0_out_Y ;
wire u_vpwr_vgnd0_out_Y;
// Name Output Other arguments
nand nand0 (nand0_out , A2, A1 );
nand nand1 (nand1_out , B2, B1 );
nand nand2 (nand2_out , C2, C1 );
and and0 (and0_out_Y , nand0_out, nand1_out, nand2_out);
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_Y, and0_out_Y, VPWR, VGND );
buf buf0 (Y , u_vpwr_vgnd0_out_Y );
endmodule
|
module sky130_fd_sc_hdll__nor3b (
Y ,
A ,
B ,
C_N ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A ;
input B ;
input C_N ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire nor0_out ;
wire and0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
nor nor0 (nor0_out , A, B );
and and0 (and0_out_Y , C_N, nor0_out );
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, and0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
|
module system_zed_hdmi_0_0(clk, clk_x2, clk_100, active, hsync, vsync, rgb888,
hdmi_clk, hdmi_hsync, hdmi_vsync, hdmi_d, hdmi_de, hdmi_scl, hdmi_sda)
/* synthesis syn_black_box black_box_pad_pin="clk,clk_x2,clk_100,active,hsync,vsync,rgb888[23:0],hdmi_clk,hdmi_hsync,hdmi_vsync,hdmi_d[15:0],hdmi_de,hdmi_scl,hdmi_sda" */;
input clk;
input clk_x2;
input clk_100;
input active;
input hsync;
input vsync;
input [23:0]rgb888;
output hdmi_clk;
output hdmi_hsync;
output hdmi_vsync;
output [15:0]hdmi_d;
output hdmi_de;
output hdmi_scl;
inout hdmi_sda;
endmodule
|
module tb_pLayer;
// Inputs
reg [263:0] state_in;
reg clk;
reg rst;
reg en;
// Outputs
wire [263:0] state_out;
wire out_rdy;
// Instantiate the Unit Under Test (UUT)
pLayer uut (
.state_in(state_in),
.state_out(state_out),
.clk(clk),
.rst(rst),
.en(en),
.out_rdy(out_rdy)
);
//integer i;
initial begin
// Initialize Inputs
state_in = 0;
clk = 0;
rst = 1;
// Wait 100 ns for global reset to finish
#100;
rst = 0;
// Add stimulus here
$display("[INITIALIZING]");
en = 1;
state_in = 264'h20d6d3dcd9d5d8dad7dfd4d1d2d0dbdddee6e3ece9e5e8eae7efe4e1e2e0ebed94;
$display("state in: %h", state_in);
repeat (66)
#5;
if (out_rdy) begin
$display("state out: %h", state_out);
end
rst = 1; en = 0;
#5;
en = 1; rst = 0;
state_in = 264'ha8365886353658867333568863335688ca2ed1e22f3856833e55353353dd2d22a5;
$display("state in: %h", state_in);
repeat (66)
#5;
if (out_rdy) begin
$display("state out: %h", state_out);
end
end
always begin
#5; clk = !clk;
end
endmodule
|
module hdr_fifo (
aclr,
clock,
data,
rdreq,
wrreq,
almost_full,
empty,
full,
q);
input aclr;
input clock;
input [71:0] data;
input rdreq;
input wrreq;
output almost_full;
output empty;
output full;
output [71:0] q;
endmodule
|
module sky130_fd_sc_hd__sdfsbp_1 (
Q ,
Q_N ,
CLK ,
D ,
SCD ,
SCE ,
SET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
output Q_N ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input SET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
sky130_fd_sc_hd__sdfsbp base (
.Q(Q),
.Q_N(Q_N),
.CLK(CLK),
.D(D),
.SCD(SCD),
.SCE(SCE),
.SET_B(SET_B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
|
module sky130_fd_sc_hd__sdfsbp_1 (
Q ,
Q_N ,
CLK ,
D ,
SCD ,
SCE ,
SET_B
);
output Q ;
output Q_N ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input SET_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__sdfsbp base (
.Q(Q),
.Q_N(Q_N),
.CLK(CLK),
.D(D),
.SCD(SCD),
.SCE(SCE),
.SET_B(SET_B)
);
endmodule
|
module test_wb_ram;
// Parameters
parameter DATA_WIDTH = 32;
parameter ADDR_WIDTH = 16;
parameter SELECT_WIDTH = 4;
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg [ADDR_WIDTH-1:0] adr_i = 0;
reg [DATA_WIDTH-1:0] dat_i = 0;
reg we_i = 0;
reg [SELECT_WIDTH-1:0] sel_i = 0;
reg stb_i = 0;
reg cyc_i = 0;
// Outputs
wire [DATA_WIDTH-1:0] dat_o;
wire ack_o;
initial begin
// myhdl integration
$from_myhdl(clk,
rst,
current_test,
adr_i,
dat_i,
we_i,
sel_i,
stb_i,
cyc_i);
$to_myhdl(dat_o,
ack_o);
// dump file
$dumpfile("test_wb_ram.lxt");
$dumpvars(0, test_wb_ram);
end
wb_ram #(
.DATA_WIDTH(DATA_WIDTH),
.ADDR_WIDTH(ADDR_WIDTH),
.SELECT_WIDTH(SELECT_WIDTH)
)
UUT (
.clk(clk),
.adr_i(adr_i),
.dat_i(dat_i),
.dat_o(dat_o),
.we_i(we_i),
.sel_i(sel_i),
.stb_i(stb_i),
.ack_o(ack_o),
.cyc_i(cyc_i)
);
endmodule
|
module sky130_fd_sc_lp__a31oi (
Y ,
A1,
A2,
A3,
B1
);
// Module ports
output Y ;
input A1;
input A2;
input A3;
input B1;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire and0_out ;
wire nor0_out_Y;
// Name Output Other arguments
and and0 (and0_out , A3, A1, A2 );
nor nor0 (nor0_out_Y, B1, and0_out );
buf buf0 (Y , nor0_out_Y );
endmodule
|
module top();
// Inputs are registered
reg A;
reg TE;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Z;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
TE = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 TE = 1'b0;
#60 VGND = 1'b0;
#80 VNB = 1'b0;
#100 VPB = 1'b0;
#120 VPWR = 1'b0;
#140 A = 1'b1;
#160 TE = 1'b1;
#180 VGND = 1'b1;
#200 VNB = 1'b1;
#220 VPB = 1'b1;
#240 VPWR = 1'b1;
#260 A = 1'b0;
#280 TE = 1'b0;
#300 VGND = 1'b0;
#320 VNB = 1'b0;
#340 VPB = 1'b0;
#360 VPWR = 1'b0;
#380 VPWR = 1'b1;
#400 VPB = 1'b1;
#420 VNB = 1'b1;
#440 VGND = 1'b1;
#460 TE = 1'b1;
#480 A = 1'b1;
#500 VPWR = 1'bx;
#520 VPB = 1'bx;
#540 VNB = 1'bx;
#560 VGND = 1'bx;
#580 TE = 1'bx;
#600 A = 1'bx;
end
sky130_fd_sc_hd__einvp dut (.A(A), .TE(TE), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Z(Z));
endmodule
|
module sky130_fd_sc_hvl__einvp (
Z ,
A ,
TE
);
// Module ports
output Z ;
input A ;
input TE;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Name Output Other arguments
notif1 notif10 (Z , A, TE );
endmodule
|
module mips32(/*AUTOARG*/
// Outputs
porta_out, portb_out,
// Inputs
rst, clk, porta_in, portb_in, interrupts
);
input rst;
input clk;
input porta_in;
input portb_in;
input [4:0] interrupts;
output porta_out;
output portb_out;
reg [31:0] PC;
reg [31:0] PCadd4;
wire [31:0] PCnext, PCout;
wire [31:0] HI;
wire [31:0] LO;
wire [31:0] inst;
wire [31:0] immediate;
wire [4:0] rs, rt, rd;
wire load, store, move, ssnop, nop,jump, branch,sign, regwrite,memtoreg,memread, memwrite;
wire [20:0] aluc;
wire [3:0] move_op;
wire [8:0] load_op;
wire [5:0] store_op;
wire [31:0] regrs_data, regrt_data;
wire [31:0] memaddr;
wire [31:0] memdata_in;
// IF stage
wire IF_stall;
wire IF_flush;
wire [31:0] IF_inst;
wire [31:0] IF_PC, IF_PCnext;
//wire [31:0] ID_inst;
//wire [31:0] ID_PCnext;
// ID stage
wire ID_stall;
wire ID_flush;
wire [31:0] ID_inst;
wire [31:0] ID_PCnext;
wire [4:0] ID_reg_dst;
wire [31:0] ID_data_a, ID_data_b, ID_data_c;
//wire [20:0] aluc;
wire ID_sign;
wire ID_memread, ID_memwrite;
wire [31:0] ID_memaddr;
wire [8:0] ID_load_op;
wire [5:0] ID_store_op;
wire ID_memtoreg, ID_regwrite;
wire [31:0] EX_data_a, EX_data_b, EX_data_c;
wire [20:0] EX_aluc;
wire EX_sign;
wire EX_memread, EX_memwrite;
wire [31:0] EX_memaddr;
wire [8:0] EX_load_op;
wire [5:0] EX_store_op;
wire EX_memtoreg, EX_regwrite;
// EXE stage:
wire EX_stall;
wire EX_flush;
wire [31:0] EX_alu_out;
wire [31:0] EX_alu_out_t;
wire [4:0] EX_rt_rd;
wire M_regwrite;
wire M_memtoreg;
wire M_memread;
wire M_memwrite;
wire [31:0] M_memaddr;
wire [8:0] M_load_op;
wire [5:0] M_store_op;
wire [31:0] M_alu_out;
wire [31:0] M_readdata;
wire [4:0] M_rt_rd;
wire M_flush;
wire M_stall;
wire WB_stall;
wire WB_regwrite;
wire WB_memtoreg;
wire [31:0] WB_readdata;
wire [31:0] WB_alu_out;
wire [4:0] WB_rtrd;
IF_stage IF_stage_0(/*AUTOINST*/
// Outputs
.ID_inst (ID_inst[31:0]),
.ID_PCnext (ID_PCnext[31:0]),
// Inputs
.clk (clk),
.rst (rst),
.IF_stall (IF_stall),
.IF_flush (IF_flush),
.ID_stall (ID_stall),
.IF_inst (IF_inst[31:0]),
.IF_PCnext (IF_PCnext[31:0]),
.IF_PC (IF_PC[31:0]));
always @(posedge clk) begin
if (rst)
PC <= 32'b0;
else begin
PC <= PCnext;
PCadd4 <= PC + 32'h0000_0004;
end
end
mux2 #(.WIDTH(32)) PC_mux(
.sel (jump|branch),
.in0 (PCadd4),
.in1 (PCout),
.out (PCnext)
);
rom rom_0(
.PC (PC),
.inst (IF_inst),
.clk (clk)
);
//wire [31:0] target_offset;
//wire [25:0] inst_idx;
//wire [4:0] regdst;
decode decode_0(
.clk (clk),
.inst_in (ID_inst),
.PCin (ID_PCnext),
.regrs_data (regrs_data),
.regrt_data (regrt_data),
//Outputs
.PCout (PCout),
.jump (jump),
.ssnop (ssnop),
.branch (branch),
.aluc (ID_aluc),
.sign (ID_sign),
//.base (base),
//.immediate (immediate),
.store (store),
.store_op (ID_store_op),
.op_a (ID_data_a),
.op_b (ID_data_b),
.op_sa (ID_data_c),
.move (move),
.move_op (move_op),
.rs (rs),
.rt (rt),
.rd (rd),
.nop (nop),
.load (load),
.load_op (ID_load_op),
//.target_offset(target_offset),
//.inst_idx (inst_idx),
.regwrite (ID_regwrite),
.memtoreg (ID_memtoreg),
.memread (ID_memread),
.regdst (ID_reg_dst),
.memwrite (ID_memwrite),
.memaddr (ID_memaddr)
);
ID_stage ID_stage_0(/*AUTOINST*/
// Outputs
.EX_data_a (EX_data_a[31:0]),
.EX_data_b (EX_data_b[31:0]),
.EX_data_c (EX_data_c[31:0]),
.EX_aluc (EX_aluc[20:0]),
.EX_sign (EX_sign),
.EX_memread (EX_memread),
.EX_memwrite (EX_memwrite),
.EX_memaddr (EX_memaddr),
.EX_load_op (EX_load_op[8:0]),
.EX_store_op (EX_store_op[5:0]),
.EX_memtoreg (EX_memtoreg),
.EX_regwrite (EX_regwrite),
// Inputs
.clk (clk),
.rst (rst),
.ID_stall (ID_stall),
.ID_flush (ID_flush),
.EX_stall (EX_stall),
.ID_reg_dst (ID_reg_dst[4:0]),
.ID_data_a (ID_data_a[31:0]),
.ID_data_b (ID_data_b[31:0]),
.ID_data_c (ID_data_c[31:0]),
.ID_aluc (ID_aluc),
.ID_sign (ID_sign),
.ID_memread (ID_memread),
.ID_memwrite (ID_memwrite),
.ID_memaddr (ID_memaddr),
.ID_load_op (ID_load_op[8:0]),
.ID_store_op (ID_store_op[5:0]),
.ID_memtoreg (ID_memtoreg),
.ID_regwrite (ID_regwrite));
alu alu_0(
//Inputs
//.data_c (ID_data_c),
.clk (clk),
.aluc (EX_aluc),
.sign (EX_sign),
.data_a (EX_data_a),
.data_b (EX_data_b),
.data_c (EX_data_c),
//Outputs
.data_out_t (EX_alu_out_t),
.overflow (overflow),
.ready (ready),
.data_out (EX_alu_out));
EX_stage EX_stage_0(
// Outputs
.M_regwrite (M_regwrite),
.M_memtoreg (M_memtoreg),
.M_memread (M_memread),
.M_memwrite (M_memwrite),
.M_memaddr (M_memaddr),
.M_load_op (M_load_op[8:0]),
.M_store_op (M_store_op[5:0]),
.M_alu_out (M_alu_out[31:0]),
.M_rt_rd (M_rt_rd[4:0]),
// Inputs
.clk (clk),
.rst (rst),
.EX_stall (EX_stall),
.EX_flush (EX_flush),
.M_stall (M_stall),
.EX_regwrite (EX_regwrite),
//.EX_reg_dst (ID_reg_dst),
.EX_memtoreg (EX_memtoreg),
.EX_memread (EX_memread),
.EX_memwrite (EX_memwrite),
.EX_memaddr (EX_memaddr),
.EX_load_op (EX_load_op[8:0]),
.EX_store_op (EX_store_op[5:0]),
.EX_alu_out (EX_alu_out[31:0]),
.EX_alu_out_t (EX_alu_out_t[31:0]),
.EX_rt_rd (ID_reg_dst));
reg [31:0] gpr_data_in;
always @* begin
case (WB_memtoreg)
1'b1: gpr_data_in <= WB_readdata;
1'b0: gpr_data_in <= WB_alu_out;
endcase
end
gpr gpr_0(
// Outputs
.reg_out1 (regrt_data),
.reg_out2 (regrs_data),
// Inputs
.clk (clk),
.regwrite (WB_regwrite),
.data_in (gpr_data_in),
.write_addr (WB_rtrd),
.reg_addr1 (rs),
.reg_addr2 (rt));
data_ram data_ram_0(
.clk (clk),
.rst (rst),
.m_read (M_memread),
.m_write (M_memwrite),
.m_addr (M_memaddr),
.m_din (memdata_in),
// Outputs
.m_dout (M_readdata)
);
MEM_stage MEM_stage_0(
// Outputs
.WB_regwrite (WB_regwrite),
.WB_memtoreg (WB_memtoreg),
.WB_readdata (WB_readdata),
.WB_alu_out (WB_alu_out[31:0]),
.WB_rt_rd (WB_rtrd),
// Inputs
.clk (clk),
.rst (rst),
.M_flush (M_flush),
.M_stall (M_stall),
.WB_stall (WB_stall),
.M_regwrite (M_regwrite),
.M_memtoreg (M_memtoreg),
.M_readdata (M_readdata),
.M_alu_out (M_alu_out[31:0]),
.M_rt_rd (M_rt_rd[4:0]));
endmodule
|
module sky130_fd_sc_ls__a211oi (
//# {{data|Data Signals}}
input A1,
input A2,
input B1,
input C1,
output Y
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
|
module sky130_fd_sc_ls__nand2b (
Y ,
A_N,
B
);
// Module ports
output Y ;
input A_N;
input B ;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire not0_out ;
wire or0_out_Y;
// Name Output Other arguments
not not0 (not0_out , B );
or or0 (or0_out_Y, not0_out, A_N );
buf buf0 (Y , or0_out_Y );
endmodule
|
module top_sim;
reg CLK, RST;
wire CLK100M = CLK;
wire d_busy;
wire d_w;
wire [`DRAMW-1:0] d_din;
wire [`DRAMW-1:0] d_dout;
wire d_douten;
wire [1:0] d_req; // DRAM access request (read/write)
wire [31:0] d_initadr; // dram initial address for the access
wire [31:0] d_blocks; // the number of blocks per one access(read/write)
wire initdone;
wire sortdone;
initial begin CLK=0; forever #50 CLK=~CLK; end
initial begin RST=1; #400 RST=0; end
reg [31:0] cnt;
always @(posedge CLK) cnt <= (RST) ? 0 : cnt + 1;
reg [31:0] lcnt;
always @(posedge CLK) lcnt <= (RST) ? 0 : (c.last_phase && c.initdone) ? lcnt + 1 : lcnt;
reg [31:0] cnt0_0, cnt1_0, cnt2_0, cnt3_0, cnt4_0, cnt5_0, cnt6_0, cnt7_0, cnt8_0;
always @(posedge CLK) cnt0_0 <= (RST) ? 0 : (c.phase_a==0 && c.initdone) ? cnt0_0 + 1 : cnt0_0;
always @(posedge CLK) cnt1_0 <= (RST) ? 0 : (c.phase_a==1 && c.initdone) ? cnt1_0 + 1 : cnt1_0;
always @(posedge CLK) cnt2_0 <= (RST) ? 0 : (c.phase_a==2 && c.initdone) ? cnt2_0 + 1 : cnt2_0;
always @(posedge CLK) cnt3_0 <= (RST) ? 0 : (c.phase_a==3 && c.initdone) ? cnt3_0 + 1 : cnt3_0;
always @(posedge CLK) cnt4_0 <= (RST) ? 0 : (c.phase_a==4 && c.initdone) ? cnt4_0 + 1 : cnt4_0;
always @(posedge CLK) cnt5_0 <= (RST) ? 0 : (c.phase_a==5 && c.initdone) ? cnt5_0 + 1 : cnt5_0;
always @(posedge CLK) cnt6_0 <= (RST) ? 0 : (c.phase_a==6 && c.initdone) ? cnt6_0 + 1 : cnt6_0;
always @(posedge CLK) cnt7_0 <= (RST) ? 0 : (c.phase_a==7 && c.initdone) ? cnt7_0 + 1 : cnt7_0;
always @(posedge CLK) cnt8_0 <= (RST) ? 0 : (c.phase_a==8 && c.initdone) ? cnt8_0 + 1 : cnt8_0;
reg [31:0] cnt0_1, cnt1_1, cnt2_1, cnt3_1, cnt4_1, cnt5_1, cnt6_1, cnt7_1, cnt8_1;
always @(posedge CLK) cnt0_1 <= (RST) ? 0 : (c.phase_b==0 && c.initdone) ? cnt0_1 + 1 : cnt0_1;
always @(posedge CLK) cnt1_1 <= (RST) ? 0 : (c.phase_b==1 && c.initdone) ? cnt1_1 + 1 : cnt1_1;
always @(posedge CLK) cnt2_1 <= (RST) ? 0 : (c.phase_b==2 && c.initdone) ? cnt2_1 + 1 : cnt2_1;
always @(posedge CLK) cnt3_1 <= (RST) ? 0 : (c.phase_b==3 && c.initdone) ? cnt3_1 + 1 : cnt3_1;
always @(posedge CLK) cnt4_1 <= (RST) ? 0 : (c.phase_b==4 && c.initdone) ? cnt4_1 + 1 : cnt4_1;
always @(posedge CLK) cnt5_1 <= (RST) ? 0 : (c.phase_b==5 && c.initdone) ? cnt5_1 + 1 : cnt5_1;
always @(posedge CLK) cnt6_1 <= (RST) ? 0 : (c.phase_b==6 && c.initdone) ? cnt6_1 + 1 : cnt6_1;
always @(posedge CLK) cnt7_1 <= (RST) ? 0 : (c.phase_b==7 && c.initdone) ? cnt7_1 + 1 : cnt7_1;
always @(posedge CLK) cnt8_1 <= (RST) ? 0 : (c.phase_b==8 && c.initdone) ? cnt8_1 + 1 : cnt8_1;
generate
if (`INITTYPE=="reverse" || `INITTYPE=="sorted") begin
always @(posedge CLK) begin /// note
if (c.initdone) begin
$write("%d|%d|state(%d)", cnt[19:0], c.last_phase, c.state);
$write("|");
if (c.F01_deq0) $write("%d", c.F01_dot0); else $write(" ");
if (c.F01_deq1) $write("%d", c.F01_dot1); else $write(" ");
$write("|");
if (d.app_wdf_wren) $write(" |M%d %d ", d_din[63:32], d_din[31:0]);
$write("\n");
$fflush();
end
end
always @(posedge CLK) begin
if (c.sortdone) begin : simulation_finish
$write("\nIt takes %d cycles\n", cnt);
$write("last(%1d): %d cycles\n", `LAST_PHASE, lcnt);
$write("phase0: %d %d cycles\n", cnt0_0, cnt0_1);
$write("phase1: %d %d cycles\n", cnt1_0, cnt1_1);
$write("phase2: %d %d cycles\n", cnt2_0, cnt2_1);
$write("phase3: %d %d cycles\n", cnt3_0, cnt3_1);
$write("phase4: %d %d cycles\n", cnt4_0, cnt4_1);
$write("phase5: %d %d cycles\n", cnt5_0, cnt5_1);
$write("phase6: %d %d cycles\n", cnt6_0, cnt6_1);
$write("phase7: %d %d cycles\n", cnt7_0, cnt7_1);
$write("phase8: %d %d cycles\n", cnt8_0, cnt8_1);
$write("Sorting finished!\n");
$finish();
end
end
end else if (`INITTYPE == "xorshift") begin
integer fp;
initial begin
fp = $fopen("test.txt", "w");
end
always @(posedge CLK) begin /// note
if (c.last_phase && c.F01_deq0) begin
$write("%08x ", c.F01_dot0);
$fwrite(fp, "%08x ", c.F01_dot0);
$fflush();
end
if (c.sortdone) begin
$fclose(fp);
$finish();
end
end
end
endgenerate
/***** DRAM Controller & DRAM Instantiation *****/
/**********************************************************************************************/
DRAM d(CLK, RST, d_req, d_initadr, d_blocks, d_din, d_w, d_dout, d_douten, d_busy);
wire ERROR;
/***** Core Module Instantiation *****/
/**********************************************************************************************/
CORE c(CLK100M, RST, initdone, sortdone,
d_busy, d_din, d_w, d_dout, d_douten, d_req, d_initadr, d_blocks, ERROR);
endmodule
|
module DRAM (input wire CLK, //
input wire RST, //
input wire [1:0] D_REQ, // dram request, load or store
input wire [31:0] D_INITADR, // dram request, initial address
input wire [31:0] D_ELEM, // dram request, the number of elements
input wire [`DRAMW-1:0] D_DIN, //
output wire D_W, //
output reg [`DRAMW-1:0] D_DOUT, //
output reg D_DOUTEN, //
output wire D_BUSY); //
/******* DRAM ******************************************************/
localparam M_REQ = 0;
localparam M_WRITE = 1;
localparam M_READ = 2;
///////////////////////////////////////////////////////////////////////////////////
reg [`DDR3_CMD] app_cmd;
reg app_en;
wire [`DRAMW-1:0] app_wdf_data;
reg app_wdf_wren;
wire app_wdf_end = app_wdf_wren;
// outputs of u_dram
wire [`DRAMW-1:0] app_rd_data;
wire app_rd_data_end;
wire app_rd_data_valid=1; // in simulation, always ready !!
wire app_rdy = 1; // in simulation, always ready !!
wire app_wdf_rdy = 1; // in simulation, always ready !!
wire ui_clk = CLK;
reg [1:0] mode;
reg [`DRAMW-1:0] app_wdf_data_buf;
reg [31:0] caddr; // check address
reg [31:0] remain, remain2; //
reg [7:0] req_state; //
///////////////////////////////////////////////////////////////////////////////////
reg [`DRAMW-1:0] mem [`DRAM_SIZE-1:0];
reg [31:0] app_addr;
reg [31:0] dram_addr;
always @(posedge CLK) dram_addr <= app_addr;
always @(posedge CLK) begin /***** DRAM WRITE *****/
if (RST) begin end
else if(app_wdf_wren) mem[dram_addr[27:3]] <= app_wdf_data;
end
assign app_rd_data = mem[app_addr[27:3]];
assign app_wdf_data = D_DIN;
assign D_BUSY = (mode!=M_REQ); // DRAM busy
assign D_W = (mode==M_WRITE && app_rdy && app_wdf_rdy); // store one element
///// READ & WRITE PORT CONTROL (begin) ////////////////////////////////////////////
always @(posedge ui_clk) begin
if (RST) begin
mode <= M_REQ;
{app_addr, app_cmd, app_en, app_wdf_wren} <= 0;
{D_DOUT, D_DOUTEN} <= 0;
{caddr, remain, remain2, req_state} <= 0;
end else begin
case (mode)
///////////////////////////////////////////////////////////////// request
M_REQ: begin
D_DOUTEN <= 0;
if(D_REQ==`DRAM_REQ_WRITE) begin ///// WRITE or STORE request
app_cmd <= `DRAM_CMD_WRITE;
mode <= M_WRITE;
app_wdf_wren <= 0;
app_en <= 1;
app_addr <= D_INITADR; // param, initial address
remain <= D_ELEM; // the number of blocks to be written
end
else if(D_REQ==`DRAM_REQ_READ) begin ///// READ or LOAD request
app_cmd <= `DRAM_CMD_READ;
mode <= M_READ;
app_wdf_wren <= 0;
app_en <= 1;
app_addr <= D_INITADR; // param, initial address
remain <= D_ELEM; // param, the number of blocks to be read
remain2 <= D_ELEM; // param, the number of blocks to be read
end
else begin
app_wdf_wren <= 0;
app_en <= 0;
end
end
//////////////////////////////////////////////////////////////////// read
M_READ: begin
if (app_rdy) begin // read request is accepted.
app_addr <= (app_addr==`MEM_LAST_ADDR) ? 0 : app_addr + 8;
remain2 <= remain2 - 1;
if(remain2==1) app_en <= 0;
end
D_DOUTEN <= app_rd_data_valid; // dram data_out enable
if (app_rd_data_valid) begin
D_DOUT <= app_rd_data;
caddr <= (caddr==`MEM_LAST_ADDR) ? 0 : caddr + 8;
remain <= remain - 1;
if(remain==1) begin
mode <= M_REQ;
end
end
end
/////////////////////////////////////////////////////////////////// write
M_WRITE: begin
if (app_rdy && app_wdf_rdy) begin
// app_wdf_data <= D_DIN;
app_wdf_wren <= 1;
app_addr <= (app_addr==`MEM_LAST_ADDR) ? 0 : app_addr + 8;
remain <= remain - 1;
if(remain==1) begin
mode <= M_REQ;
app_en <= 0;
end
end
else app_wdf_wren <= 0;
end
endcase
end
end
///// READ & WRITE PORT CONTROL (end) //////////////////////////////////////
endmodule
|
module nios_tester_nios2_gen2_0_cpu_debug_slave_wrapper (
// inputs:
MonDReg,
break_readreg,
clk,
dbrk_hit0_latch,
dbrk_hit1_latch,
dbrk_hit2_latch,
dbrk_hit3_latch,
debugack,
monitor_error,
monitor_ready,
reset_n,
resetlatch,
tracemem_on,
tracemem_trcdata,
tracemem_tw,
trc_im_addr,
trc_on,
trc_wrap,
trigbrktype,
trigger_state_1,
// outputs:
jdo,
jrst_n,
st_ready_test_idle,
take_action_break_a,
take_action_break_b,
take_action_break_c,
take_action_ocimem_a,
take_action_ocimem_b,
take_action_tracectrl,
take_no_action_break_a,
take_no_action_break_b,
take_no_action_break_c,
take_no_action_ocimem_a
)
;
output [ 37: 0] jdo;
output jrst_n;
output st_ready_test_idle;
output take_action_break_a;
output take_action_break_b;
output take_action_break_c;
output take_action_ocimem_a;
output take_action_ocimem_b;
output take_action_tracectrl;
output take_no_action_break_a;
output take_no_action_break_b;
output take_no_action_break_c;
output take_no_action_ocimem_a;
input [ 31: 0] MonDReg;
input [ 31: 0] break_readreg;
input clk;
input dbrk_hit0_latch;
input dbrk_hit1_latch;
input dbrk_hit2_latch;
input dbrk_hit3_latch;
input debugack;
input monitor_error;
input monitor_ready;
input reset_n;
input resetlatch;
input tracemem_on;
input [ 35: 0] tracemem_trcdata;
input tracemem_tw;
input [ 6: 0] trc_im_addr;
input trc_on;
input trc_wrap;
input trigbrktype;
input trigger_state_1;
wire [ 37: 0] jdo;
wire jrst_n;
wire [ 37: 0] sr;
wire st_ready_test_idle;
wire take_action_break_a;
wire take_action_break_b;
wire take_action_break_c;
wire take_action_ocimem_a;
wire take_action_ocimem_b;
wire take_action_tracectrl;
wire take_no_action_break_a;
wire take_no_action_break_b;
wire take_no_action_break_c;
wire take_no_action_ocimem_a;
wire vji_cdr;
wire [ 1: 0] vji_ir_in;
wire [ 1: 0] vji_ir_out;
wire vji_rti;
wire vji_sdr;
wire vji_tck;
wire vji_tdi;
wire vji_tdo;
wire vji_udr;
wire vji_uir;
//Change the sld_virtual_jtag_basic's defparams to
//switch between a regular Nios II or an internally embedded Nios II.
//For a regular Nios II, sld_mfg_id = 70, sld_type_id = 34.
//For an internally embedded Nios II, slf_mfg_id = 110, sld_type_id = 135.
nios_tester_nios2_gen2_0_cpu_debug_slave_tck the_nios_tester_nios2_gen2_0_cpu_debug_slave_tck
(
.MonDReg (MonDReg),
.break_readreg (break_readreg),
.dbrk_hit0_latch (dbrk_hit0_latch),
.dbrk_hit1_latch (dbrk_hit1_latch),
.dbrk_hit2_latch (dbrk_hit2_latch),
.dbrk_hit3_latch (dbrk_hit3_latch),
.debugack (debugack),
.ir_in (vji_ir_in),
.ir_out (vji_ir_out),
.jrst_n (jrst_n),
.jtag_state_rti (vji_rti),
.monitor_error (monitor_error),
.monitor_ready (monitor_ready),
.reset_n (reset_n),
.resetlatch (resetlatch),
.sr (sr),
.st_ready_test_idle (st_ready_test_idle),
.tck (vji_tck),
.tdi (vji_tdi),
.tdo (vji_tdo),
.tracemem_on (tracemem_on),
.tracemem_trcdata (tracemem_trcdata),
.tracemem_tw (tracemem_tw),
.trc_im_addr (trc_im_addr),
.trc_on (trc_on),
.trc_wrap (trc_wrap),
.trigbrktype (trigbrktype),
.trigger_state_1 (trigger_state_1),
.vs_cdr (vji_cdr),
.vs_sdr (vji_sdr),
.vs_uir (vji_uir)
);
nios_tester_nios2_gen2_0_cpu_debug_slave_sysclk the_nios_tester_nios2_gen2_0_cpu_debug_slave_sysclk
(
.clk (clk),
.ir_in (vji_ir_in),
.jdo (jdo),
.sr (sr),
.take_action_break_a (take_action_break_a),
.take_action_break_b (take_action_break_b),
.take_action_break_c (take_action_break_c),
.take_action_ocimem_a (take_action_ocimem_a),
.take_action_ocimem_b (take_action_ocimem_b),
.take_action_tracectrl (take_action_tracectrl),
.take_no_action_break_a (take_no_action_break_a),
.take_no_action_break_b (take_no_action_break_b),
.take_no_action_break_c (take_no_action_break_c),
.take_no_action_ocimem_a (take_no_action_ocimem_a),
.vs_udr (vji_udr),
.vs_uir (vji_uir)
);
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
assign vji_tck = 1'b0;
assign vji_tdi = 1'b0;
assign vji_sdr = 1'b0;
assign vji_cdr = 1'b0;
assign vji_rti = 1'b0;
assign vji_uir = 1'b0;
assign vji_udr = 1'b0;
assign vji_ir_in = 2'b0;
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
//synthesis read_comments_as_HDL on
// sld_virtual_jtag_basic nios_tester_nios2_gen2_0_cpu_debug_slave_phy
// (
// .ir_in (vji_ir_in),
// .ir_out (vji_ir_out),
// .jtag_state_rti (vji_rti),
// .tck (vji_tck),
// .tdi (vji_tdi),
// .tdo (vji_tdo),
// .virtual_state_cdr (vji_cdr),
// .virtual_state_sdr (vji_sdr),
// .virtual_state_udr (vji_udr),
// .virtual_state_uir (vji_uir)
// );
//
// defparam nios_tester_nios2_gen2_0_cpu_debug_slave_phy.sld_auto_instance_index = "YES",
// nios_tester_nios2_gen2_0_cpu_debug_slave_phy.sld_instance_index = 0,
// nios_tester_nios2_gen2_0_cpu_debug_slave_phy.sld_ir_width = 2,
// nios_tester_nios2_gen2_0_cpu_debug_slave_phy.sld_mfg_id = 70,
// nios_tester_nios2_gen2_0_cpu_debug_slave_phy.sld_sim_action = "",
// nios_tester_nios2_gen2_0_cpu_debug_slave_phy.sld_sim_n_scan = 0,
// nios_tester_nios2_gen2_0_cpu_debug_slave_phy.sld_sim_total_length = 0,
// nios_tester_nios2_gen2_0_cpu_debug_slave_phy.sld_type_id = 34,
// nios_tester_nios2_gen2_0_cpu_debug_slave_phy.sld_version = 3;
//
//synthesis read_comments_as_HDL off
endmodule
|
module Booth_Tester_2;
// Inputs
reg [3:0] multiplicand;
reg [3:0] multiplier;
// Outputs
wire [7:0] product;
// Instantiate the Unit Under Test (UUT)
Booth_Multiplier_II uut (
.product(product),
.multiplicand(multiplicand),
.multiplier(multiplier)
);
initial begin
// Initialize Inputs
multiplicand = 4'b1100;
multiplier = 4'b1011;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
end
endmodule
|
module body
//
// generate internal reset
wire rst_i = arst_i ^ ARST_LVL;
// generate wishbone signals
wire wb_wacc = wb_cyc_i & wb_stb_i & wb_we_i;
// generate acknowledge output signal
always @(posedge wb_clk_i)
wb_ack_o <= #1 wb_cyc_i & wb_stb_i & ~wb_ack_o; // because timing is always honored
// assign DAT_O
always @(posedge wb_clk_i)
begin
case (wb_adr_i) // synopsis parallel_case
3'b000: wb_dat_o <= #1 prer[ 7:0];
3'b001: wb_dat_o <= #1 prer[15:8];
3'b010: wb_dat_o <= #1 ctr;
3'b011: wb_dat_o <= #1 rxr; // write is transmit register (txr)
3'b100: wb_dat_o <= #1 sr; // write is command register (cr)
3'b101: wb_dat_o <= #1 txr;
3'b110: wb_dat_o <= #1 cr;
3'b111: wb_dat_o <= #1 0; // reserved
endcase
end
// generate registers
always @(posedge wb_clk_i or negedge rst_i)
if (!rst_i)
begin
prer <= #1 16'hffff;
ctr <= #1 8'h0;
txr <= #1 8'h0;
end
else if (wb_rst_i)
begin
prer <= #1 16'hffff;
ctr <= #1 8'h0;
txr <= #1 8'h0;
end
else
if (wb_wacc)
case (wb_adr_i) // synopsis parallel_case
3'b000 : prer [ 7:0] <= #1 wb_dat_i;
3'b001 : prer [15:8] <= #1 wb_dat_i;
3'b010 : ctr <= #1 wb_dat_i;
3'b011 : txr <= #1 wb_dat_i;
default: ;
endcase
// generate command register (special case)
always @(posedge wb_clk_i or negedge rst_i)
if (~rst_i)
cr <= #1 8'h0;
else if (wb_rst_i)
cr <= #1 8'h0;
else if (wb_wacc)
begin
if (core_en & (wb_adr_i == 3'b100) )
cr <= #1 wb_dat_i;
end
else
begin
if (done | i2c_al)
cr[7:4] <= #1 4'h0; // clear command bits when done
// or when aribitration lost
cr[2:1] <= #1 2'b0; // reserved bits
cr[0] <= #1 2'b0; // clear IRQ_ACK bit
end
// decode command register
wire sta = cr[7];
wire sto = cr[6];
wire rd = cr[5];
wire wr = cr[4];
wire ack = cr[3];
wire iack = cr[0];
// decode control register
assign core_en = ctr[7];
assign ien = ctr[6];
// hookup byte controller block
i2c_master_byte_ctrl byte_controller (
.clk ( wb_clk_i ),
.rst ( wb_rst_i ),
.nReset ( rst_i ),
.ena ( core_en ),
.clk_cnt ( prer ),
.start ( sta ),
.stop ( sto ),
.read ( rd ),
.write ( wr ),
.ack_in ( ack ),
.din ( txr ),
.cmd_ack ( done ),
.ack_out ( irxack ),
.dout ( rxr ),
.i2c_busy ( i2c_busy ),
.i2c_al ( i2c_al ),
.scl_i ( scl_pad_i ),
.scl_o ( scl_pad_o ),
.scl_oen ( scl_padoen_o ),
.sda_i ( sda_pad_i ),
.sda_o ( sda_pad_o ),
.sda_oen ( sda_padoen_o )
);
// status register block + interrupt request signal
always @(posedge wb_clk_i or negedge rst_i)
if (!rst_i)
begin
al <= #1 1'b0;
rxack <= #1 1'b0;
tip <= #1 1'b0;
irq_flag <= #1 1'b0;
end
else if (wb_rst_i)
begin
al <= #1 1'b0;
rxack <= #1 1'b0;
tip <= #1 1'b0;
irq_flag <= #1 1'b0;
end
else
begin
al <= #1 i2c_al | (al & ~sta);
rxack <= #1 irxack;
tip <= #1 (rd | wr);
irq_flag <= #1 (done | i2c_al | irq_flag) & ~iack; // interrupt request flag is always generated
end
// generate interrupt request signals
always @(posedge wb_clk_i or negedge rst_i)
if (!rst_i)
wb_inta_o <= #1 1'b0;
else if (wb_rst_i)
wb_inta_o <= #1 1'b0;
else
wb_inta_o <= #1 irq_flag && ien; // interrupt signal is only generated when IEN (interrupt enable bit is set)
// assign status register bits
assign sr[7] = rxack;
assign sr[6] = i2c_busy;
assign sr[5] = al;
assign sr[4:2] = 3'h0; // reserved
assign sr[1] = tip;
assign sr[0] = irq_flag;
endmodule
|
module VGA_Controller (
input wire Clock,
input wire Enable,
input wire Reset,
input wire[2:0] iPixel,
output wire oHorizontalSync,
output wire oVerticalSync,
output wire oRed,
output wire oGreen,
output wire oBlue,
output wire[9:0] oColumnCount,
output wire[9:0] oRowCount
);
wire[10:0] wColumnCount;
wire wColumnReset, wRowReset;
wire[9:0] wColumnCount_2, wRowCount;
assign wColumnCount_2 = {wColumnCount[10:1]};
assign wColumnReset = (wColumnCount == 11'd1599);
assign wRowReset = (wRowCount == 10'd524 && wColumnReset);
assign oColumnCount = wColumnCount_2;
assign oRowCount = wRowCount;
UPCOUNTER_POSEDGE # ( 11 ) COLUMN_COUNTER
(
.Clock( Clock ),
.Reset( wColumnReset | Reset ),
.Initial( 11'd0 ),
.Enable( 1'b1 ),
.Q( wColumnCount )
);
UPCOUNTER_POSEDGE # ( 10 ) ROW_COUNTER
(
.Clock( Clock ),
.Reset( wRowReset | Reset ),
.Initial( 10'd0 ),
.Enable( wColumnReset ),
.Q( wRowCount )
);
parameter H_VISIBLE_AREA = 640;
parameter H_FRONT_PORCH = 16;
parameter H_PULSE = 96;
parameter H_BACK_PORCH = 48;
parameter HORIZONTAL_LINE = 800;
parameter V_VISIBLE_AREA = 480;
parameter V_FRONT_PORCH = 10;
parameter V_PULSE = 2;
parameter V_BACK_PORCH = 33;
parameter VERTICAL_LINE = 525;
assign oHorizontalSync =
(
wColumnCount_2 >= (H_VISIBLE_AREA + H_FRONT_PORCH ) &&
wColumnCount_2 <= (H_VISIBLE_AREA + H_FRONT_PORCH + H_PULSE )
) ? 1'b0 : 1'b1;
assign oVerticalSync =
(
wRowCount >= (V_VISIBLE_AREA + V_FRONT_PORCH ) &&
wRowCount <= (V_VISIBLE_AREA + V_FRONT_PORCH + V_PULSE )
) ? 1'b0 : 1'b1;
assign {oRed,oGreen,oBlue} = (wColumnCount_2 < H_VISIBLE_AREA && wRowCount < V_VISIBLE_AREA) ?
{iPixel} : //display color
{`BLACK}; //black
endmodule
|
module sky130_fd_sc_lp__nand3b (
//# {{data|Data Signals}}
input A_N ,
input B ,
input C ,
output Y ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
|
module deserializer(
clk, //serialized data proper clock
enable, //suspend while enable on low
reset, //set output to zero and reset counter to 0 on high
framesize, //number of bits to be deserialized - 1
in, //serialized data
out, //deserialized data
complete //reset counter to 0 and hold out's data while high
);
parameter BITS = 136; //size of deserializer
parameter BITS_COUNTER = 8; //size of counter, must be at least log2(BITS)
parameter COUNTER_MAX = 8'hFF; //max possible value
input clk, enable, reset, in;
input [BITS_COUNTER-1:0] framesize;
output reg complete;
output reg [BITS-1:0] out;
reg [BITS_COUNTER-1:0] counter; //we need to know which array item (out) to write on
always@(posedge reset) begin
out = 0;
counter = framesize;
complete = 0;
end
always@(posedge clk) begin
if(enable) begin
if(~complete) begin //as long there's not any reset state, count
out[counter] <= in;
counter = counter - 1; //next item
end
end else begin
complete = 0;
end
end
always@(counter) begin
if(counter == COUNTER_MAX) begin //all bits have been read
complete = 1;
end
end
always@(complete) begin
counter = framesize; //this way there's no need to reset every time we start a transaction (resetting all out bits consumes power)
end
endmodule
|
module sky130_fd_sc_ms__dfxtp_4 (
Q ,
CLK ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
output Q ;
input CLK ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ms__dfxtp base (
.Q(Q),
.CLK(CLK),
.D(D),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
|
module sky130_fd_sc_ms__dfxtp_4 (
Q ,
CLK,
D
);
output Q ;
input CLK;
input D ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__dfxtp base (
.Q(Q),
.CLK(CLK),
.D(D)
);
endmodule
|
module top();
// Inputs are registered
reg A;
reg B;
reg C;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
B = 1'bX;
C = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 B = 1'b0;
#60 C = 1'b0;
#80 VGND = 1'b0;
#100 VNB = 1'b0;
#120 VPB = 1'b0;
#140 VPWR = 1'b0;
#160 A = 1'b1;
#180 B = 1'b1;
#200 C = 1'b1;
#220 VGND = 1'b1;
#240 VNB = 1'b1;
#260 VPB = 1'b1;
#280 VPWR = 1'b1;
#300 A = 1'b0;
#320 B = 1'b0;
#340 C = 1'b0;
#360 VGND = 1'b0;
#380 VNB = 1'b0;
#400 VPB = 1'b0;
#420 VPWR = 1'b0;
#440 VPWR = 1'b1;
#460 VPB = 1'b1;
#480 VNB = 1'b1;
#500 VGND = 1'b1;
#520 C = 1'b1;
#540 B = 1'b1;
#560 A = 1'b1;
#580 VPWR = 1'bx;
#600 VPB = 1'bx;
#620 VNB = 1'bx;
#640 VGND = 1'bx;
#660 C = 1'bx;
#680 B = 1'bx;
#700 A = 1'bx;
end
sky130_fd_sc_lp__maj3 dut (.A(A), .B(B), .C(C), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .X(X));
endmodule
|
module sky130_fd_sc_ms__clkdlyinv3sd3 (
Y,
A
);
// Module ports
output Y;
input A;
// Local signals
wire not0_out_Y;
// Name Output Other arguments
not not0 (not0_out_Y, A );
buf buf0 (Y , not0_out_Y );
endmodule
|
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