module_content
stringlengths 18
1.05M
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module sky130_fd_sc_hd__clkdlybuf4s25 (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire buf0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X , A );
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, buf0_out_X, VPWR, VGND);
buf buf1 (X , pwrgood_pp0_out_X );
endmodule
|
module ps2_controller (
input reset,
input clk,
input ps2_clock,
input ps2_data,
output scan_ready,
output [7:0] scan_code
);
reg [7:0] r_scan_code;
reg [3:0] state_reg = 4'd0;
reg ready;
reg [1:0] ps2_clock_edge_detect = 2'b00;
wire ps2_clock_negedge;
assign scan_code = r_scan_code;
assign scan_ready = ready;
assign ps2_clock_negedge = (ps2_clock_edge_detect == 2'b10);
// Sample the ps2_clock.
always @(posedge clk) begin
ps2_clock_edge_detect <= {ps2_clock_edge_detect[0], ps2_clock};
end
// ps2_clock is goes low 15us after the data is set.
always @(posedge clk or posedge reset) begin
if (reset) begin
state_reg <= 4'b0;
r_scan_code <= 8'b0;
end
else if (ready) begin
// Ensure ready flag is only one system clock.
ready <= 1'b0;
end
else if (ps2_clock_negedge) begin
case (state_reg)
4'd0: // 1 start bit. This is always 0.
begin
state_reg <= state_reg + 1'b1;
ready <= 1'b0;
end
4'd9: // 1 parity bit (odd parity).
begin
if (!ps2_data == ^r_scan_code) begin
ready <= 1'b1;
end else begin
ready <= 1'b0;
end
state_reg <= state_reg + 1'b1;
end
4'd10: // 1 stop bit. This is always 1.
begin
state_reg <= 4'b0;
ready <= 1'b0;
end
default: // 8 data bits, least significant bit first.
begin
r_scan_code[state_reg - 1] <= ps2_data;
state_reg <= state_reg + 1'b1;
ready <= 1'b0;
end
endcase
end
end
endmodule
|
module oh_memory_ram # (parameter DW = 104, //memory width
parameter DEPTH = 32, //memory depth
parameter AW = $clog2(DEPTH) // address width
)
(// read-port
input rd_clk,// rd clock
input rd_en, // memory access
input [AW-1:0] rd_addr, // address
output reg [DW-1:0] rd_dout, // data output
// write-port
input wr_clk,// wr clock
input wr_en, // memory access
input [AW-1:0] wr_addr, // address
input [DW-1:0] wr_wem, // write enable vector
input [DW-1:0] wr_din // data input
);
reg [DW-1:0] ram [DEPTH-1:0];
integer i;
//registered read port
always @ (posedge rd_clk)
if(rd_en)
rd_dout[DW-1:0] <= ram[rd_addr[AW-1:0]];
//write port with vector enable
always @(posedge wr_clk)
for (i=0;i<DW;i=i+1)
if (wr_en & wr_wem[i])
ram[wr_addr[AW-1:0]][i] <= wr_din[i];
endmodule
|
module ime_best_mv_above_16 (
// global
clk ,
rstn ,
// ctrl_i
start_i ,
val_i ,
qp_i ,
// update_i
update_wrk_i ,
update_cnt_i ,
update_cst_i ,
// sad_i
sad_16x16_00_i , sad_16x16_10_i , sad_16x16_20_i , sad_16x16_30_i ,
sad_16x16_01_i , sad_16x16_11_i , sad_16x16_21_i , sad_16x16_31_i ,
sad_16x16_02_i , sad_16x16_12_i , sad_16x16_22_i , sad_16x16_32_i ,
sad_16x16_03_i , sad_16x16_13_i , sad_16x16_23_i , sad_16x16_33_i ,
// mv_i
mv_x_16x16_i ,
mv_y_16x16_i ,
// cost_o
// cost_16x32
cost_16x32_00_o , cost_16x32_20_o ,
cost_16x32_01_o , cost_16x32_21_o ,
cost_16x32_02_o , cost_16x32_22_o ,
cost_16x32_03_o , cost_16x32_23_o ,
// cost_32x16
cost_32x16_00_o , cost_32x16_20_o ,
cost_32x16_10_o , cost_32x16_30_o ,
cost_32x16_02_o , cost_32x16_22_o ,
cost_32x16_12_o , cost_32x16_32_o ,
// cost_32x32
cost_32x32_00_o , cost_32x32_20_o ,
cost_32x32_02_o , cost_32x32_22_o ,
// cost_32x64
cost_32x64_00_o ,
cost_32x64_02_o ,
// cost_64x32
cost_64x32_00_o , cost_64x32_20_o ,
// cost_64x64
cost_64x64_00_o ,
// mv_x_o
// mv_x_16x32
mv_x_16x32_00_o , mv_x_16x32_20_o ,
mv_x_16x32_01_o , mv_x_16x32_21_o ,
mv_x_16x32_02_o , mv_x_16x32_22_o ,
mv_x_16x32_03_o , mv_x_16x32_23_o ,
// mv_x_32x16
mv_x_32x16_00_o , mv_x_32x16_20_o ,
mv_x_32x16_10_o , mv_x_32x16_30_o ,
mv_x_32x16_02_o , mv_x_32x16_22_o ,
mv_x_32x16_12_o , mv_x_32x16_32_o ,
// mv_x_32x32
mv_x_32x32_00_o , mv_x_32x32_20_o ,
mv_x_32x32_02_o , mv_x_32x32_22_o ,
// mv_x_32x64
mv_x_32x64_00_o ,
mv_x_32x64_02_o ,
// mv_x_64x32
mv_x_64x32_00_o , mv_x_64x32_20_o ,
// mv_x_64x64
mv_x_64x64_00_o ,
// mv_y_o
// mv_y_16x32
mv_y_16x32_00_o , mv_y_16x32_20_o ,
mv_y_16x32_01_o , mv_y_16x32_21_o ,
mv_y_16x32_02_o , mv_y_16x32_22_o ,
mv_y_16x32_03_o , mv_y_16x32_23_o ,
// mv_y_32x16
mv_y_32x16_00_o , mv_y_32x16_20_o ,
mv_y_32x16_10_o , mv_y_32x16_30_o ,
mv_y_32x16_02_o , mv_y_32x16_22_o ,
mv_y_32x16_12_o , mv_y_32x16_32_o ,
// mv_y_32x32
mv_y_32x32_00_o , mv_y_32x32_20_o ,
mv_y_32x32_02_o , mv_y_32x32_22_o ,
// mv_y_32x64
mv_y_32x64_00_o ,
mv_y_32x64_02_o ,
// mv_y_64x32
mv_y_64x32_00_o , mv_y_64x32_20_o ,
// mv_y_64x64
mv_y_64x64_00_o
);
//*** PARAMETER DECLARATION ****************************************************
//*** INPUT/OUTPUT DECLARATION *************************************************
// global
input clk ;
input rstn ;
// ctrl_i
input start_i ;
input val_i ;
input [5 : 0] qp_i ;
// update_i
input update_wrk_i ;
input [6 : 0] update_cnt_i ;
input [`COST_WIDTH-1 : 0] update_cst_i ;
// sad_i
input [`PIXEL_WIDTH+7 : 0] sad_16x16_00_i , sad_16x16_10_i , sad_16x16_20_i , sad_16x16_30_i ;
input [`PIXEL_WIDTH+7 : 0] sad_16x16_01_i , sad_16x16_11_i , sad_16x16_21_i , sad_16x16_31_i ;
input [`PIXEL_WIDTH+7 : 0] sad_16x16_02_i , sad_16x16_12_i , sad_16x16_22_i , sad_16x16_32_i ;
input [`PIXEL_WIDTH+7 : 0] sad_16x16_03_i , sad_16x16_13_i , sad_16x16_23_i , sad_16x16_33_i ;
// mv_i
input [`IMV_WIDTH-1 : 0] mv_x_16x16_i ;
input [`IMV_WIDTH-1 : 0] mv_y_16x16_i ;
// cost_o
// cost_16x32
output reg [`COST_WIDTH-1 : 0] cost_16x32_00_o , cost_16x32_20_o ;
output reg [`COST_WIDTH-1 : 0] cost_16x32_01_o , cost_16x32_21_o ;
output reg [`COST_WIDTH-1 : 0] cost_16x32_02_o , cost_16x32_22_o ;
output reg [`COST_WIDTH-1 : 0] cost_16x32_03_o , cost_16x32_23_o ;
// cost_32x16
output reg [`COST_WIDTH-1 : 0] cost_32x16_00_o , cost_32x16_20_o ;
output reg [`COST_WIDTH-1 : 0] cost_32x16_10_o , cost_32x16_30_o ;
output reg [`COST_WIDTH-1 : 0] cost_32x16_02_o , cost_32x16_22_o ;
output reg [`COST_WIDTH-1 : 0] cost_32x16_12_o , cost_32x16_32_o ;
// cost_32x32
output reg [`COST_WIDTH-1 : 0] cost_32x32_00_o , cost_32x32_20_o ;
output reg [`COST_WIDTH-1 : 0] cost_32x32_02_o , cost_32x32_22_o ;
// cost_32x64
output reg [`COST_WIDTH-1 : 0] cost_32x64_00_o ;
output reg [`COST_WIDTH-1 : 0] cost_32x64_02_o ;
// cost_64x32
output reg [`COST_WIDTH-1 : 0] cost_64x32_00_o , cost_64x32_20_o ;
// cost_64x64
output reg [`COST_WIDTH-1 : 0] cost_64x64_00_o ;
// mv_x_o
// mv_x_16x32
output reg [`IMV_WIDTH-1 : 0] mv_x_16x32_00_o , mv_x_16x32_20_o ;
output reg [`IMV_WIDTH-1 : 0] mv_x_16x32_01_o , mv_x_16x32_21_o ;
output reg [`IMV_WIDTH-1 : 0] mv_x_16x32_02_o , mv_x_16x32_22_o ;
output reg [`IMV_WIDTH-1 : 0] mv_x_16x32_03_o , mv_x_16x32_23_o ;
// mv_x_32x16
output reg [`IMV_WIDTH-1 : 0] mv_x_32x16_00_o , mv_x_32x16_20_o ;
output reg [`IMV_WIDTH-1 : 0] mv_x_32x16_10_o , mv_x_32x16_30_o ;
output reg [`IMV_WIDTH-1 : 0] mv_x_32x16_02_o , mv_x_32x16_22_o ;
output reg [`IMV_WIDTH-1 : 0] mv_x_32x16_12_o , mv_x_32x16_32_o ;
// mv_x_32x32
output reg [`IMV_WIDTH-1 : 0] mv_x_32x32_00_o , mv_x_32x32_20_o ;
output reg [`IMV_WIDTH-1 : 0] mv_x_32x32_02_o , mv_x_32x32_22_o ;
// mv_x_32x64
output reg [`IMV_WIDTH-1 : 0] mv_x_32x64_00_o ;
output reg [`IMV_WIDTH-1 : 0] mv_x_32x64_02_o ;
// mv_x_64x32
output reg [`IMV_WIDTH-1 : 0] mv_x_64x32_00_o , mv_x_64x32_20_o ;
// mv_x_64x64
output reg [`IMV_WIDTH-1 : 0] mv_x_64x64_00_o ;
// mv_y_o
// mv_y_16x32
output reg [`IMV_WIDTH-1 : 0] mv_y_16x32_00_o , mv_y_16x32_20_o ;
output reg [`IMV_WIDTH-1 : 0] mv_y_16x32_01_o , mv_y_16x32_21_o ;
output reg [`IMV_WIDTH-1 : 0] mv_y_16x32_02_o , mv_y_16x32_22_o ;
output reg [`IMV_WIDTH-1 : 0] mv_y_16x32_03_o , mv_y_16x32_23_o ;
// mv_y_32x16
output reg [`IMV_WIDTH-1 : 0] mv_y_32x16_00_o , mv_y_32x16_20_o ;
output reg [`IMV_WIDTH-1 : 0] mv_y_32x16_10_o , mv_y_32x16_30_o ;
output reg [`IMV_WIDTH-1 : 0] mv_y_32x16_02_o , mv_y_32x16_22_o ;
output reg [`IMV_WIDTH-1 : 0] mv_y_32x16_12_o , mv_y_32x16_32_o ;
// mv_y_32x32
output reg [`IMV_WIDTH-1 : 0] mv_y_32x32_00_o , mv_y_32x32_20_o ;
output reg [`IMV_WIDTH-1 : 0] mv_y_32x32_02_o , mv_y_32x32_22_o ;
// mv_y_32x64
output reg [`IMV_WIDTH-1 : 0] mv_y_32x64_00_o ;
output reg [`IMV_WIDTH-1 : 0] mv_y_32x64_02_o ;
// mv_y_64x32
output reg [`IMV_WIDTH-1 : 0] mv_y_64x32_00_o , mv_y_64x32_20_o ;
// mv_y_64x64
output reg [`IMV_WIDTH-1 : 0] mv_y_64x64_00_o ;
//*** WIRE & REG DECLARATION ***************************************************
// sad_w
// sad_16x32
wire [`PIXEL_WIDTH+8 : 0] sad_16x32_00_w , sad_16x32_20_w ;
wire [`PIXEL_WIDTH+8 : 0] sad_16x32_01_w , sad_16x32_21_w ;
wire [`PIXEL_WIDTH+8 : 0] sad_16x32_02_w , sad_16x32_22_w ;
wire [`PIXEL_WIDTH+8 : 0] sad_16x32_03_w , sad_16x32_23_w ;
// sad_32x16
wire [`PIXEL_WIDTH+8 : 0] sad_32x16_00_w , sad_32x16_20_w ;
wire [`PIXEL_WIDTH+8 : 0] sad_32x16_10_w , sad_32x16_30_w ;
wire [`PIXEL_WIDTH+8 : 0] sad_32x16_02_w , sad_32x16_22_w ;
wire [`PIXEL_WIDTH+8 : 0] sad_32x16_12_w , sad_32x16_32_w ;
// sad_32x32
wire [`PIXEL_WIDTH+9 : 0] sad_32x32_00_w , sad_32x32_20_w ;
wire [`PIXEL_WIDTH+9 : 0] sad_32x32_02_w , sad_32x32_22_w ;
// sad_32x64
wire [`PIXEL_WIDTH+10 : 0] sad_32x64_00_w ;
wire [`PIXEL_WIDTH+10 : 0] sad_32x64_02_w ;
// sad_64x32
wire [`PIXEL_WIDTH+10 : 0] sad_64x32_00_w , sad_64x32_20_w ;
// sad_64x64
wire [`PIXEL_WIDTH+11 : 0] sad_64x64_00_w ;
// mv_cost
wire [`FMV_WIDTH-1 : 0] mv_x_16x16_s_w ;
wire [`FMV_WIDTH-1 : 0] mv_y_16x16_s_w ;
wire [`FMV_WIDTH : 0] mv_x_16x16_c_w ;
wire [`FMV_WIDTH : 0] mv_y_16x16_c_w ;
reg [4 : 0] bitsnum_x_w ;
reg [4 : 0] bitsnum_y_w ;
reg [6 : 0] lambda_w ;
wire [12 : 0] mv_cost_w ;
// cost_w
// cost_16x32
wire [`COST_WIDTH-1 : 0] cost_16x32_00_w , cost_16x32_20_w ;
wire [`COST_WIDTH-1 : 0] cost_16x32_01_w , cost_16x32_21_w ;
wire [`COST_WIDTH-1 : 0] cost_16x32_02_w , cost_16x32_22_w ;
wire [`COST_WIDTH-1 : 0] cost_16x32_03_w , cost_16x32_23_w ;
// cost_32x16
wire [`COST_WIDTH-1 : 0] cost_32x16_00_w , cost_32x16_20_w ;
wire [`COST_WIDTH-1 : 0] cost_32x16_10_w , cost_32x16_30_w ;
wire [`COST_WIDTH-1 : 0] cost_32x16_02_w , cost_32x16_22_w ;
wire [`COST_WIDTH-1 : 0] cost_32x16_12_w , cost_32x16_32_w ;
// cost_32x32
wire [`COST_WIDTH-1 : 0] cost_32x32_00_w , cost_32x32_20_w ;
wire [`COST_WIDTH-1 : 0] cost_32x32_02_w , cost_32x32_22_w ;
// cost_32x64
wire [`COST_WIDTH-1 : 0] cost_32x64_00_w ;
wire [`COST_WIDTH-1 : 0] cost_32x64_02_w ;
// cost_64x32
wire [`COST_WIDTH-1 : 0] cost_64x32_00_w , cost_64x32_20_w ;
// cost_64x64
wire [`COST_WIDTH-1 : 0] cost_64x64_00_w ;
// cover_w
// cover_16x32
wire cover_16x32_00_w , cover_16x32_20_w ;
wire cover_16x32_01_w , cover_16x32_21_w ;
wire cover_16x32_02_w , cover_16x32_22_w ;
wire cover_16x32_03_w , cover_16x32_23_w ;
// cover_32x16
wire cover_32x16_00_w , cover_32x16_20_w ;
wire cover_32x16_10_w , cover_32x16_30_w ;
wire cover_32x16_02_w , cover_32x16_22_w ;
wire cover_32x16_12_w , cover_32x16_32_w ;
// cover_32x32
wire cover_32x32_00_w , cover_32x32_20_w ;
wire cover_32x32_02_w , cover_32x32_22_w ;
// cover_32x64
wire cover_32x64_00_w ;
wire cover_32x64_02_w ;
// cover_64x32
wire cover_64x32_00_w , cover_64x32_20_w ;
// cover_64x64
wire cover_64x64_00_w ;
//*** MAIN BODY ****************************************************************
// sad_w
// sad_16x32
assign sad_16x32_00_w = sad_16x16_00_i + sad_16x16_10_i ;
assign sad_16x32_01_w = sad_16x16_01_i + sad_16x16_11_i ;
assign sad_16x32_02_w = sad_16x16_02_i + sad_16x16_12_i ;
assign sad_16x32_03_w = sad_16x16_03_i + sad_16x16_13_i ;
assign sad_16x32_20_w = sad_16x16_20_i + sad_16x16_30_i ;
assign sad_16x32_21_w = sad_16x16_21_i + sad_16x16_31_i ;
assign sad_16x32_22_w = sad_16x16_22_i + sad_16x16_32_i ;
assign sad_16x32_23_w = sad_16x16_23_i + sad_16x16_33_i ;
// sad_32x16
assign sad_32x16_00_w = sad_16x16_00_i + sad_16x16_01_i ;
assign sad_32x16_10_w = sad_16x16_10_i + sad_16x16_11_i ;
assign sad_32x16_02_w = sad_16x16_02_i + sad_16x16_03_i ;
assign sad_32x16_12_w = sad_16x16_12_i + sad_16x16_13_i ;
assign sad_32x16_20_w = sad_16x16_20_i + sad_16x16_21_i ;
assign sad_32x16_30_w = sad_16x16_30_i + sad_16x16_31_i ;
assign sad_32x16_22_w = sad_16x16_22_i + sad_16x16_23_i ;
assign sad_32x16_32_w = sad_16x16_32_i + sad_16x16_33_i ;
// sad_32x32
assign sad_32x32_00_w = sad_16x32_00_w + sad_16x32_01_w ;
assign sad_32x32_02_w = sad_16x32_02_w + sad_16x32_03_w ;
assign sad_32x32_20_w = sad_16x32_20_w + sad_16x32_21_w ;
assign sad_32x32_22_w = sad_16x32_22_w + sad_16x32_23_w ;
// sad 32x64
assign sad_32x64_00_w = sad_32x32_00_w + sad_32x32_20_w ;
assign sad_32x64_02_w = sad_32x32_02_w + sad_32x32_22_w ;
// sad 64x32
assign sad_64x32_00_w = sad_32x32_00_w + sad_32x32_02_w ;
assign sad_64x32_20_w = sad_32x32_20_w + sad_32x32_22_w ;
// sad 64x64
assign sad_64x64_00_w = sad_32x64_00_w + sad_32x64_02_w ;
// mv_cost
assign mv_x_16x16_s_w = ( mv_x_16x16_i-12 ) * 4 ; //+ mv_x_base_i ;
assign mv_y_16x16_s_w = ( mv_y_16x16_i-12 ) * 4 ; //+ mv_y_base_i ;
assign mv_x_16x16_c_w = ( mv_x_16x16_s_w[`FMV_WIDTH-1] ) ? ( {1'b0,~mv_x_16x16_s_w[`FMV_WIDTH-2:0],1'b0} + 3 ) :
( (|mv_x_16x16_s_w[`FMV_WIDTH-2:0]) ? ( {1'b0, mv_x_16x16_s_w[`FMV_WIDTH-2:0],1'b0} )
: 1 );
assign mv_y_16x16_c_w = ( mv_y_16x16_s_w[`FMV_WIDTH-1] ) ? ( {1'b0,~mv_y_16x16_s_w[`FMV_WIDTH-2:0],1'b0} + 3 ) :
( (|mv_y_16x16_s_w[`FMV_WIDTH-2:0]) ? ( {1'b0, mv_y_16x16_s_w[`FMV_WIDTH-2:0],1'b0} )
: 1 );
always @(*) begin
casex( mv_x_16x16_c_w )
'b000_0000_0001 : bitsnum_x_w = 01 ;
'b000_0000_001x : bitsnum_x_w = 03 ;
'b000_0000_01xx : bitsnum_x_w = 05 ;
'b000_0000_1xxx : bitsnum_x_w = 07 ;
'b000_0001_xxxx : bitsnum_x_w = 09 ;
'b000_001x_xxxx : bitsnum_x_w = 11 ;
'b000_01xx_xxxx : bitsnum_x_w = 13 ;
'b000_1xxx_xxxx : bitsnum_x_w = 15 ;
'b001_xxxx_xxxx : bitsnum_x_w = 17 ;
'b01x_xxxx_xxxx : bitsnum_x_w = 19 ;
'b1xx_xxxx_xxxx : bitsnum_x_w = 21 ;
default : bitsnum_x_w = 21 ;
endcase
end
always @(*) begin
casex( mv_y_16x16_c_w )
'b000_0000_0001 : bitsnum_y_w = 01 ;
'b000_0000_001x : bitsnum_y_w = 03 ;
'b000_0000_01xx : bitsnum_y_w = 05 ;
'b000_0000_1xxx : bitsnum_y_w = 07 ;
'b000_0001_xxxx : bitsnum_y_w = 09 ;
'b000_001x_xxxx : bitsnum_y_w = 11 ;
'b000_01xx_xxxx : bitsnum_y_w = 13 ;
'b000_1xxx_xxxx : bitsnum_y_w = 15 ;
'b001_xxxx_xxxx : bitsnum_y_w = 17 ;
'b01x_xxxx_xxxx : bitsnum_y_w = 19 ;
'b1xx_xxxx_xxxx : bitsnum_y_w = 21 ;
default : bitsnum_y_w = 21 ;
endcase
end
always @(*) begin
case( qp_i )
0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15 : lambda_w = 01 ;
16,17,18,19 : lambda_w = 02 ;
20,21,22 : lambda_w = 03 ;
23,24,25 : lambda_w = 04 ;
26 : lambda_w = 05 ;
27,28 : lambda_w = 06 ;
29 : lambda_w = 07 ;
30 : lambda_w = 08 ;
31 : lambda_w = 09 ;
32 : lambda_w = 10 ;
33 : lambda_w = 11 ;
34 : lambda_w = 13 ;
35 : lambda_w = 14 ;
36 : lambda_w = 16 ;
37 : lambda_w = 18 ;
38 : lambda_w = 20 ;
39 : lambda_w = 23 ;
40 : lambda_w = 25 ;
41 : lambda_w = 29 ;
42 : lambda_w = 32 ;
43 : lambda_w = 36 ;
44 : lambda_w = 40 ;
45 : lambda_w = 45 ;
46 : lambda_w = 51 ;
47 : lambda_w = 57 ;
48 : lambda_w = 64 ;
49 : lambda_w = 72 ;
50 : lambda_w = 81 ;
51 : lambda_w = 91 ;
default : lambda_w = 00 ;
endcase
end
assign mv_cost_w = lambda_w * ( bitsnum_x_w + bitsnum_y_w );
// cost_w
// cost_16x32
assign cost_16x32_00_w = sad_16x32_00_w + mv_cost_w ;
assign cost_16x32_01_w = sad_16x32_01_w + mv_cost_w ;
assign cost_16x32_02_w = sad_16x32_02_w + mv_cost_w ;
assign cost_16x32_03_w = sad_16x32_03_w + mv_cost_w ;
assign cost_16x32_20_w = sad_16x32_20_w + mv_cost_w ;
assign cost_16x32_21_w = sad_16x32_21_w + mv_cost_w ;
assign cost_16x32_22_w = sad_16x32_22_w + mv_cost_w ;
assign cost_16x32_23_w = sad_16x32_23_w + mv_cost_w ;
// cost_32x16
assign cost_32x16_00_w = sad_32x16_00_w + mv_cost_w ;
assign cost_32x16_10_w = sad_32x16_10_w + mv_cost_w ;
assign cost_32x16_02_w = sad_32x16_02_w + mv_cost_w ;
assign cost_32x16_12_w = sad_32x16_12_w + mv_cost_w ;
assign cost_32x16_20_w = sad_32x16_20_w + mv_cost_w ;
assign cost_32x16_30_w = sad_32x16_30_w + mv_cost_w ;
assign cost_32x16_22_w = sad_32x16_22_w + mv_cost_w ;
assign cost_32x16_32_w = sad_32x16_32_w + mv_cost_w ;
// cost_32x32
assign cost_32x32_00_w = sad_32x32_00_w + mv_cost_w ;
assign cost_32x32_02_w = sad_32x32_02_w + mv_cost_w ;
assign cost_32x32_20_w = sad_32x32_20_w + mv_cost_w ;
assign cost_32x32_22_w = sad_32x32_22_w + mv_cost_w ;
// cost 32x64
assign cost_32x64_00_w = sad_32x64_00_w + mv_cost_w ;
assign cost_32x64_02_w = sad_32x64_02_w + mv_cost_w ;
// cost 64x32
assign cost_64x32_00_w = sad_64x32_00_w + mv_cost_w ;
assign cost_64x32_20_w = sad_64x32_20_w + mv_cost_w ;
// cost 64x64
assign cost_64x64_00_w = sad_64x64_00_w + mv_cost_w ;
// cover_w
// cover_16x32
assign cover_16x32_00_w = cost_16x32_00_w < cost_16x32_00_o ;
assign cover_16x32_01_w = cost_16x32_01_w < cost_16x32_01_o ;
assign cover_16x32_02_w = cost_16x32_02_w < cost_16x32_02_o ;
assign cover_16x32_03_w = cost_16x32_03_w < cost_16x32_03_o ;
assign cover_16x32_20_w = cost_16x32_20_w < cost_16x32_20_o ;
assign cover_16x32_21_w = cost_16x32_21_w < cost_16x32_21_o ;
assign cover_16x32_22_w = cost_16x32_22_w < cost_16x32_22_o ;
assign cover_16x32_23_w = cost_16x32_23_w < cost_16x32_23_o ;
// cover_32x16
assign cover_32x16_00_w = cost_32x16_00_w < cost_32x16_00_o ;
assign cover_32x16_10_w = cost_32x16_10_w < cost_32x16_10_o ;
assign cover_32x16_02_w = cost_32x16_02_w < cost_32x16_02_o ;
assign cover_32x16_12_w = cost_32x16_12_w < cost_32x16_12_o ;
assign cover_32x16_20_w = cost_32x16_20_w < cost_32x16_20_o ;
assign cover_32x16_30_w = cost_32x16_30_w < cost_32x16_30_o ;
assign cover_32x16_22_w = cost_32x16_22_w < cost_32x16_22_o ;
assign cover_32x16_32_w = cost_32x16_32_w < cost_32x16_32_o ;
// cover_32x32
assign cover_32x32_00_w = cost_32x32_00_w < cost_32x32_00_o ;
assign cover_32x32_02_w = cost_32x32_02_w < cost_32x32_02_o ;
assign cover_32x32_20_w = cost_32x32_20_w < cost_32x32_20_o ;
assign cover_32x32_22_w = cost_32x32_22_w < cost_32x32_22_o ;
// cover 32x64
assign cover_32x64_00_w = cost_32x64_00_w < cost_32x64_00_o ;
assign cover_32x64_02_w = cost_32x64_02_w < cost_32x64_02_o ;
// cover 64x32
assign cover_64x32_00_w = cost_64x32_00_w < cost_64x32_00_o ;
assign cover_64x32_20_w = cost_64x32_20_w < cost_64x32_20_o ;
// cover 64x64
assign cover_64x64_00_w = cost_64x64_00_w < cost_64x64_00_o ;
// cost_o
always @(posedge clk or negedge rstn ) begin
if( !rstn ) begin
// cost_16x32
cost_16x32_00_o <= -1 ;
cost_16x32_01_o <= -1 ;
cost_16x32_02_o <= -1 ;
cost_16x32_03_o <= -1 ;
cost_16x32_20_o <= -1 ;
cost_16x32_21_o <= -1 ;
cost_16x32_22_o <= -1 ;
cost_16x32_23_o <= -1 ;
// cost_32x16
cost_32x16_00_o <= -1 ;
cost_32x16_10_o <= -1 ;
cost_32x16_02_o <= -1 ;
cost_32x16_12_o <= -1 ;
// cost_32x16
cost_32x16_20_o <= -1 ;
cost_32x16_30_o <= -1 ;
cost_32x16_22_o <= -1 ;
cost_32x16_32_o <= -1 ;
// cost_32x32
cost_32x32_00_o <= -1 ;
cost_32x32_02_o <= -1 ;
// cost_32x32
cost_32x32_20_o <= -1 ;
cost_32x32_22_o <= -1 ;
// cost_32x64
cost_32x64_00_o <= -1 ;
cost_32x64_02_o <= -1 ;
// cost_64x32
cost_64x32_00_o <= -1 ;
cost_64x32_20_o <= -1 ;
// cost_64x64
cost_64x64_00_o <= -1 ;
end
else if( start_i ) begin
// cost_16x32
cost_16x32_00_o <= -1 ;
cost_16x32_01_o <= -1 ;
cost_16x32_02_o <= -1 ;
cost_16x32_03_o <= -1 ;
cost_16x32_20_o <= -1 ;
cost_16x32_21_o <= -1 ;
cost_16x32_22_o <= -1 ;
cost_16x32_23_o <= -1 ;
// cost_32x16
cost_32x16_00_o <= -1 ;
cost_32x16_10_o <= -1 ;
cost_32x16_02_o <= -1 ;
cost_32x16_12_o <= -1 ;
// cost_32x16
cost_32x16_20_o <= -1 ;
cost_32x16_30_o <= -1 ;
cost_32x16_22_o <= -1 ;
cost_32x16_32_o <= -1 ;
// cost_32x32
cost_32x32_00_o <= -1 ;
cost_32x32_02_o <= -1 ;
// cost_32x32
cost_32x32_20_o <= -1 ;
cost_32x32_22_o <= -1 ;
// cost_32x64
cost_32x64_00_o <= -1 ;
cost_32x64_02_o <= -1 ;
// cost_64x32
cost_64x32_00_o <= -1 ;
cost_64x32_20_o <= -1 ;
// cost_64x64
cost_64x64_00_o <= -1 ;
end
else if( val_i ) begin
// cover_16x32
if( cover_16x32_00_w ) cost_16x32_00_o <= cost_16x32_00_w ;
if( cover_16x32_01_w ) cost_16x32_01_o <= cost_16x32_01_w ;
if( cover_16x32_02_w ) cost_16x32_02_o <= cost_16x32_02_w ;
if( cover_16x32_03_w ) cost_16x32_03_o <= cost_16x32_03_w ;
if( cover_16x32_20_w ) cost_16x32_20_o <= cost_16x32_20_w ;
if( cover_16x32_21_w ) cost_16x32_21_o <= cost_16x32_21_w ;
if( cover_16x32_22_w ) cost_16x32_22_o <= cost_16x32_22_w ;
if( cover_16x32_23_w ) cost_16x32_23_o <= cost_16x32_23_w ;
// cover_32x16
if( cover_32x16_00_w ) cost_32x16_00_o <= cost_32x16_00_w ;
if( cover_32x16_10_w ) cost_32x16_10_o <= cost_32x16_10_w ;
if( cover_32x16_02_w ) cost_32x16_02_o <= cost_32x16_02_w ;
if( cover_32x16_12_w ) cost_32x16_12_o <= cost_32x16_12_w ;
// cover_32x16
if( cover_32x16_20_w ) cost_32x16_20_o <= cost_32x16_20_w ;
if( cover_32x16_30_w ) cost_32x16_30_o <= cost_32x16_30_w ;
if( cover_32x16_22_w ) cost_32x16_22_o <= cost_32x16_22_w ;
if( cover_32x16_32_w ) cost_32x16_32_o <= cost_32x16_32_w ;
// cover_32x32
if( cover_32x32_00_w ) cost_32x32_00_o <= cost_32x32_00_w ;
if( cover_32x32_02_w ) cost_32x32_02_o <= cost_32x32_02_w ;
// cover_32x32
if( cover_32x32_20_w ) cost_32x32_20_o <= cost_32x32_20_w ;
if( cover_32x32_22_w ) cost_32x32_22_o <= cost_32x32_22_w ;
// cover_32x64
if( cover_32x64_00_w ) cost_32x64_00_o <= cost_32x64_00_w ;
if( cover_32x64_02_w ) cost_32x64_02_o <= cost_32x64_02_w ;
// cover_64x32
if( cover_64x32_00_w ) cost_64x32_00_o <= cost_64x32_00_w ;
if( cover_64x32_20_w ) cost_64x32_20_o <= cost_64x32_20_w ;
// cover_64x64
if( cover_64x64_00_w ) cost_64x64_00_o <= cost_64x64_00_w ;
end
else if( update_wrk_i ) begin
case( update_cnt_i )
16 : cost_32x32_00_o <= update_cst_i ;
17 : cost_32x32_02_o <= update_cst_i ;
18 : cost_32x32_20_o <= update_cst_i ;
19 : cost_32x32_22_o <= update_cst_i ;
20 : cost_64x64_00_o <= update_cst_i ;
endcase
end
end
// mv_x_o
always @(posedge clk or negedge rstn ) begin
if( !rstn ) begin
// mv_x_16x32
mv_x_16x32_00_o <= -1 ;
mv_x_16x32_01_o <= -1 ;
mv_x_16x32_02_o <= -1 ;
mv_x_16x32_03_o <= -1 ;
mv_x_16x32_20_o <= -1 ;
mv_x_16x32_21_o <= -1 ;
mv_x_16x32_22_o <= -1 ;
mv_x_16x32_23_o <= -1 ;
// mv_x_32x16
mv_x_32x16_00_o <= -1 ;
mv_x_32x16_10_o <= -1 ;
mv_x_32x16_02_o <= -1 ;
mv_x_32x16_12_o <= -1 ;
// mv_x_32x16
mv_x_32x16_20_o <= -1 ;
mv_x_32x16_30_o <= -1 ;
mv_x_32x16_22_o <= -1 ;
mv_x_32x16_32_o <= -1 ;
// mv_x_32x32
mv_x_32x32_00_o <= -1 ;
mv_x_32x32_02_o <= -1 ;
// mv_x_32x32
mv_x_32x32_20_o <= -1 ;
mv_x_32x32_22_o <= -1 ;
// mv_x_32x64
mv_x_32x64_00_o <= -1 ;
mv_x_32x64_02_o <= -1 ;
// mv_x_64x32
mv_x_64x32_00_o <= -1 ;
mv_x_64x32_20_o <= -1 ;
// mv_x_64x64
mv_x_64x64_00_o <= -1 ;
end
else if( val_i ) begin
// cover_16x32
if( cover_16x32_00_w ) mv_x_16x32_00_o <= mv_x_16x16_i ;
if( cover_16x32_01_w ) mv_x_16x32_01_o <= mv_x_16x16_i ;
if( cover_16x32_02_w ) mv_x_16x32_02_o <= mv_x_16x16_i ;
if( cover_16x32_03_w ) mv_x_16x32_03_o <= mv_x_16x16_i ;
if( cover_16x32_20_w ) mv_x_16x32_20_o <= mv_x_16x16_i ;
if( cover_16x32_21_w ) mv_x_16x32_21_o <= mv_x_16x16_i ;
if( cover_16x32_22_w ) mv_x_16x32_22_o <= mv_x_16x16_i ;
if( cover_16x32_23_w ) mv_x_16x32_23_o <= mv_x_16x16_i ;
// cover_32x16
if( cover_32x16_00_w ) mv_x_32x16_00_o <= mv_x_16x16_i ;
if( cover_32x16_10_w ) mv_x_32x16_10_o <= mv_x_16x16_i ;
if( cover_32x16_02_w ) mv_x_32x16_02_o <= mv_x_16x16_i ;
if( cover_32x16_12_w ) mv_x_32x16_12_o <= mv_x_16x16_i ;
// cover_32x16
if( cover_32x16_20_w ) mv_x_32x16_20_o <= mv_x_16x16_i ;
if( cover_32x16_30_w ) mv_x_32x16_30_o <= mv_x_16x16_i ;
if( cover_32x16_22_w ) mv_x_32x16_22_o <= mv_x_16x16_i ;
if( cover_32x16_32_w ) mv_x_32x16_32_o <= mv_x_16x16_i ;
// cover_32x32
if( cover_32x32_00_w ) mv_x_32x32_00_o <= mv_x_16x16_i ;
if( cover_32x32_02_w ) mv_x_32x32_02_o <= mv_x_16x16_i ;
// cover_32x32
if( cover_32x32_20_w ) mv_x_32x32_20_o <= mv_x_16x16_i ;
if( cover_32x32_22_w ) mv_x_32x32_22_o <= mv_x_16x16_i ;
// cover_32x64
if( cover_32x64_00_w ) mv_x_32x64_00_o <= mv_x_16x16_i ;
if( cover_32x64_02_w ) mv_x_32x64_02_o <= mv_x_16x16_i ;
// cover_64x32
if( cover_64x32_00_w ) mv_x_64x32_00_o <= mv_x_16x16_i ;
if( cover_64x32_20_w ) mv_x_64x32_20_o <= mv_x_16x16_i ;
// cover_64x64
if( cover_64x64_00_w ) mv_x_64x64_00_o <= mv_x_16x16_i ;
end
end
// mv_y_o
always @(posedge clk or negedge rstn ) begin
if( !rstn ) begin
// mv_y_16x32
mv_y_16x32_00_o <= -1 ;
mv_y_16x32_01_o <= -1 ;
mv_y_16x32_02_o <= -1 ;
mv_y_16x32_03_o <= -1 ;
mv_y_16x32_20_o <= -1 ;
mv_y_16x32_21_o <= -1 ;
mv_y_16x32_22_o <= -1 ;
mv_y_16x32_23_o <= -1 ;
// mv_y_32x16
mv_y_32x16_00_o <= -1 ;
mv_y_32x16_10_o <= -1 ;
mv_y_32x16_02_o <= -1 ;
mv_y_32x16_12_o <= -1 ;
// mv_y_32x16
mv_y_32x16_20_o <= -1 ;
mv_y_32x16_30_o <= -1 ;
mv_y_32x16_22_o <= -1 ;
mv_y_32x16_32_o <= -1 ;
// mv_y_32x32
mv_y_32x32_00_o <= -1 ;
mv_y_32x32_02_o <= -1 ;
// mv_y_32x32
mv_y_32x32_20_o <= -1 ;
mv_y_32x32_22_o <= -1 ;
// mv_y_32x64
mv_y_32x64_00_o <= -1 ;
mv_y_32x64_02_o <= -1 ;
// mv_y_64x32
mv_y_64x32_00_o <= -1 ;
mv_y_64x32_20_o <= -1 ;
// mv_y_64x64
mv_y_64x64_00_o <= -1 ;
end
else if( val_i ) begin
// cover_16x32
if( cover_16x32_00_w ) mv_y_16x32_00_o <= mv_y_16x16_i ;
if( cover_16x32_01_w ) mv_y_16x32_01_o <= mv_y_16x16_i ;
if( cover_16x32_02_w ) mv_y_16x32_02_o <= mv_y_16x16_i ;
if( cover_16x32_03_w ) mv_y_16x32_03_o <= mv_y_16x16_i ;
if( cover_16x32_20_w ) mv_y_16x32_20_o <= mv_y_16x16_i ;
if( cover_16x32_21_w ) mv_y_16x32_21_o <= mv_y_16x16_i ;
if( cover_16x32_22_w ) mv_y_16x32_22_o <= mv_y_16x16_i ;
if( cover_16x32_23_w ) mv_y_16x32_23_o <= mv_y_16x16_i ;
// cover_32x16
if( cover_32x16_00_w ) mv_y_32x16_00_o <= mv_y_16x16_i ;
if( cover_32x16_10_w ) mv_y_32x16_10_o <= mv_y_16x16_i ;
if( cover_32x16_02_w ) mv_y_32x16_02_o <= mv_y_16x16_i ;
if( cover_32x16_12_w ) mv_y_32x16_12_o <= mv_y_16x16_i ;
// cover_32x16
if( cover_32x16_20_w ) mv_y_32x16_20_o <= mv_y_16x16_i ;
if( cover_32x16_30_w ) mv_y_32x16_30_o <= mv_y_16x16_i ;
if( cover_32x16_22_w ) mv_y_32x16_22_o <= mv_y_16x16_i ;
if( cover_32x16_32_w ) mv_y_32x16_32_o <= mv_y_16x16_i ;
// cover_32x32
if( cover_32x32_00_w ) mv_y_32x32_00_o <= mv_y_16x16_i ;
if( cover_32x32_02_w ) mv_y_32x32_02_o <= mv_y_16x16_i ;
// cover_32x32
if( cover_32x32_20_w ) mv_y_32x32_20_o <= mv_y_16x16_i ;
if( cover_32x32_22_w ) mv_y_32x32_22_o <= mv_y_16x16_i ;
// cover_32x64
if( cover_32x64_00_w ) mv_y_32x64_00_o <= mv_y_16x16_i ;
if( cover_32x64_02_w ) mv_y_32x64_02_o <= mv_y_16x16_i ;
// cover_64x32
if( cover_64x32_00_w ) mv_y_64x32_00_o <= mv_y_16x16_i ;
if( cover_64x32_20_w ) mv_y_64x32_20_o <= mv_y_16x16_i ;
// cover_64x64
if( cover_64x64_00_w ) mv_y_64x64_00_o <= mv_y_16x16_i ;
end
end
//*** DEBUG ********************************************************************
endmodule
|
module DE0Nano_Button(
//////////// CLOCK //////////
CLOCK_50,
//////////// LED //////////
LED,
//////////// KEY //////////
KEY
);
//=======================================================
// PARAMETER declarations
//=======================================================
parameter LED_SEQUENCE_0 =8'b10000000;
parameter LED_SEQUENCE_1 =8'b01000000;
parameter LED_SEQUENCE_2 =8'b00100000;
parameter LED_SEQUENCE_3 =8'b00010000;
parameter LED_SEQUENCE_4 =8'b00001000;
parameter LED_SEQUENCE_5 =8'b00000100;
parameter LED_SEQUENCE_6 =8'b00000010;
parameter LED_SEQUENCE_7 =8'b00000001;
//=======================================================
// PORT declarations
//=======================================================
//////////// CLOCK //////////
input CLOCK_50;
//////////// LED //////////
output [7:0] LED;
//////////// KEY //////////
input [1:0] KEY;
//=======================================================
// REG/WIRE declarations
//=======================================================
reg [7:0]LedsState=LED_SEQUENCE_0;
reg [7:0]LedsNextState;
wire Clock_Sequence;
reg SequenceControl=0;
wire Btn1_Signal;
wire Btn2_Signal;
//Frequency Divider Module
ClockDivider #(.Bits_counter (28)) DIVIDER_A
( .P_CLOCK(CLOCK_50),
.P_TIMER_OUT(Clock_Sequence),
.P_COMPARATOR(28'd16000000));
// Debounce circuir for Button1
DeBounce DebBtn1 (
.clk(CLOCK_50),
.n_reset(1'b1),
.button_in(KEY[0]),
.DB_out(Btn1_Signal)
);
// Debounce circuir for Button2
DeBounce DebBtn2 (
.clk(CLOCK_50),
.n_reset(1'b1),
.button_in(KEY[1]),
.DB_out(Btn2_Signal)
);
//=======================================================
// Structural coding
//=======================================================
// Leds Sequence control
always @(*)
begin
case (LedsState)
LED_SEQUENCE_0:
begin
if (SequenceControl==0)
LedsNextState=LED_SEQUENCE_1;
else
LedsNextState=LED_SEQUENCE_7;
end
LED_SEQUENCE_1:
begin
if (SequenceControl==0)
LedsNextState=LED_SEQUENCE_2;
else
LedsNextState=LED_SEQUENCE_0;
end
LED_SEQUENCE_2:
begin
if (SequenceControl==0)
LedsNextState=LED_SEQUENCE_3;
else
LedsNextState=LED_SEQUENCE_1;
end
LED_SEQUENCE_3:
begin
if (SequenceControl==0)
LedsNextState=LED_SEQUENCE_4;
else
LedsNextState=LED_SEQUENCE_2;
end
LED_SEQUENCE_4:
begin
if (SequenceControl==0)
LedsNextState=LED_SEQUENCE_5;
else
LedsNextState=LED_SEQUENCE_3;
end
LED_SEQUENCE_5:
begin
if (SequenceControl==0)
LedsNextState=LED_SEQUENCE_6;
else
LedsNextState=LED_SEQUENCE_4;
end
LED_SEQUENCE_6:
begin
if (SequenceControl==0)
LedsNextState=LED_SEQUENCE_7;
else
LedsNextState=LED_SEQUENCE_5;
end
LED_SEQUENCE_7:
begin
if (SequenceControl==0)
LedsNextState=LED_SEQUENCE_0;
else
LedsNextState=LED_SEQUENCE_6;
end
default:
LedsNextState=LED_SEQUENCE_0;
endcase
end
// Led direction control
always @ (posedge CLOCK_50)
begin
if (Btn1_Signal==0)
SequenceControl<=0;
else if (Btn2_Signal==0)
SequenceControl<=1;
else
SequenceControl<=SequenceControl;
end
// Leds sequence registers
always @ (posedge Clock_Sequence)
begin
LedsState<=LedsNextState;
end
//=======================================================
// Connections & assigns
//=======================================================
assign LED = LedsState;
endmodule
|
module sky130_fd_sc_ls__nor2_4 (
Y ,
A ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__nor2 base (
.Y(Y),
.A(A),
.B(B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
|
module sky130_fd_sc_ls__nor2_4 (
Y,
A,
B
);
output Y;
input A;
input B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__nor2 base (
.Y(Y),
.A(A),
.B(B)
);
endmodule
|
module sky130_fd_sc_lp__bushold (
//# {{data|Data Signals}}
inout X ,
//# {{control|Control Signals}}
input RESET,
//# {{power|Power}}
input VPB ,
input VPWR ,
input VGND ,
input VNB
);
endmodule
|
module system_vga_sync_ref_1_0(clk, rst, hsync, vsync, start, active, xaddr, yaddr)
/* synthesis syn_black_box black_box_pad_pin="clk,rst,hsync,vsync,start,active,xaddr[9:0],yaddr[9:0]" */;
input clk;
input rst;
input hsync;
input vsync;
output start;
output active;
output [9:0]xaddr;
output [9:0]yaddr;
endmodule
|
module ID_EX_Seg(
input Clk,
input stall,
input flush,
input [31:0]PC_Add,
input OverflowEn,
input[2:0] condition,
input Branch,
input[2:0] PC_write,//Unknown
input[3:0] Mem_Byte_Write,
input[3:0] Rd_Write_Byte_en,
input MemWBSrc,
input Jump,
input ALUShiftSrc,
input [2:0]MemDataSrc,
input ALUSrcA,ALUSrcB,
input [3:0] ALUOp,
input [1:0] RegDst,
input ShiftAmountSrc,
input [1:0] ShiftOp,
input [31:0] OperandA,OperandB,
input [4:0]Rs,Rt,Rd,
input [31:0] Immediate32,
input [4:0]Shamt,
input BranchSel,
input [1:0] RtRead,
output reg [31:0]PC_Add_out,
output reg OverflowEn_out,
output reg[2:0] condition_out,
output reg Branch_out,
output reg[2:0] PC_write_out,
output reg[3:0] Mem_Byte_Write_out,
output reg[3:0] Rd_Write_Byte_en_out,
output reg MemWBSrc_out,
output reg Jump_out,
output reg ALUShiftSrc_out,
output reg [2:0]MemDataSrc_out,
output reg ALUSrcA_out,ALUSrcB_out,
output reg [3:0] ALUOp_out,
output reg [1:0] RegDst_out,
output reg ShiftAmountSrc_out,
output reg [1:0] ShiftOp_out,
output reg [31:0] OperandA_out,OperandB_out,
output reg [4:0] Rs_out,Rt_out,Rd_out,
output reg [31:0] Immediate32_out,
output reg [4:0]Shamt_out,
output reg BranchSel_out,
output reg [1:0] RtRead_out
);
always@(posedge Clk)
begin
if(flush)begin
PC_Add_out <= 32'h0;
OverflowEn_out <= 1'b0;
condition_out <= 3'b0;
Branch_out <= 1'b0;
PC_write_out <= 3'b0;
Mem_Byte_Write_out <= 4'b0;
Rd_Write_Byte_en_out <= 4'b0;
MemWBSrc_out <= 1'b0;
Jump_out <= 1'b0;
ALUShiftSrc_out <= 1'b0;
MemDataSrc_out <= 3'b0;
ALUSrcA_out <= 1'b0;
ALUSrcB_out <= 1'b0;
ALUOp_out <= 4'b0;
RegDst_out <= 2'b0;
ShiftAmountSrc_out <= 1'b0;
ShiftOp_out <= 2'b0;//
OperandA_out <= 32'b0;
OperandB_out <= 32'b0;
Rs_out <= 5'b0;
Rt_out <= 5'b0;
Rd_out <= 5'b0;
Immediate32_out <= 32'b0;
Shamt_out <= 5'b0;
BranchSel_out <= 1'b0;
RtRead_out <= 1'b0;
end
else if(~stall)
begin
PC_Add_out <= PC_Add;
OverflowEn_out <= OverflowEn;
condition_out <= condition;
Branch_out <= Branch;
PC_write_out <= PC_write;
Mem_Byte_Write_out <= Mem_Byte_Write;
Rd_Write_Byte_en_out <= Rd_Write_Byte_en;
MemWBSrc_out <= MemWBSrc;
Jump_out <= Jump;
ALUShiftSrc_out <= ALUShiftSrc;
MemDataSrc_out <= MemDataSrc;
ALUSrcA_out <= ALUSrcA;
ALUSrcB_out <= ALUSrcB;
ALUOp_out <= ALUOp;
RegDst_out <= RegDst;
ShiftAmountSrc_out <= ShiftAmountSrc;
ShiftOp_out <= ShiftOp;
OperandA_out <= OperandA;
OperandB_out <= OperandB;
Rs_out <= Rs;
Rt_out <= Rt;
Rd_out <= Rd;
Immediate32_out <= Immediate32;
Shamt_out <= Shamt;
BranchSel_out <= BranchSel;
RtRead_out <= RtRead;
end
end
endmodule
|
module opl3_cpu_processing_system7_0_0 (
I2C0_SDA_I,
I2C0_SDA_O,
I2C0_SDA_T,
I2C0_SCL_I,
I2C0_SCL_O,
I2C0_SCL_T,
SDIO0_WP,
USB0_PORT_INDCTL,
USB0_VBUS_PWRSELECT,
USB0_VBUS_PWRFAULT,
M_AXI_GP0_ARVALID,
M_AXI_GP0_AWVALID,
M_AXI_GP0_BREADY,
M_AXI_GP0_RREADY,
M_AXI_GP0_WLAST,
M_AXI_GP0_WVALID,
M_AXI_GP0_ARID,
M_AXI_GP0_AWID,
M_AXI_GP0_WID,
M_AXI_GP0_ARBURST,
M_AXI_GP0_ARLOCK,
M_AXI_GP0_ARSIZE,
M_AXI_GP0_AWBURST,
M_AXI_GP0_AWLOCK,
M_AXI_GP0_AWSIZE,
M_AXI_GP0_ARPROT,
M_AXI_GP0_AWPROT,
M_AXI_GP0_ARADDR,
M_AXI_GP0_AWADDR,
M_AXI_GP0_WDATA,
M_AXI_GP0_ARCACHE,
M_AXI_GP0_ARLEN,
M_AXI_GP0_ARQOS,
M_AXI_GP0_AWCACHE,
M_AXI_GP0_AWLEN,
M_AXI_GP0_AWQOS,
M_AXI_GP0_WSTRB,
M_AXI_GP0_ACLK,
M_AXI_GP0_ARREADY,
M_AXI_GP0_AWREADY,
M_AXI_GP0_BVALID,
M_AXI_GP0_RLAST,
M_AXI_GP0_RVALID,
M_AXI_GP0_WREADY,
M_AXI_GP0_BID,
M_AXI_GP0_RID,
M_AXI_GP0_BRESP,
M_AXI_GP0_RRESP,
M_AXI_GP0_RDATA,
FCLK_RESET0_N,
MIO,
DDR_CAS_n,
DDR_CKE,
DDR_Clk_n,
DDR_Clk,
DDR_CS_n,
DDR_DRSTB,
DDR_ODT,
DDR_RAS_n,
DDR_WEB,
DDR_BankAddr,
DDR_Addr,
DDR_VRN,
DDR_VRP,
DDR_DM,
DDR_DQ,
DDR_DQS_n,
DDR_DQS,
PS_SRSTB,
PS_CLK,
PS_PORB
);
input I2C0_SDA_I;
output I2C0_SDA_O;
output I2C0_SDA_T;
input I2C0_SCL_I;
output I2C0_SCL_O;
output I2C0_SCL_T;
input SDIO0_WP;
output [1 : 0] USB0_PORT_INDCTL;
output USB0_VBUS_PWRSELECT;
input USB0_VBUS_PWRFAULT;
output M_AXI_GP0_ARVALID;
output M_AXI_GP0_AWVALID;
output M_AXI_GP0_BREADY;
output M_AXI_GP0_RREADY;
output M_AXI_GP0_WLAST;
output M_AXI_GP0_WVALID;
output [11 : 0] M_AXI_GP0_ARID;
output [11 : 0] M_AXI_GP0_AWID;
output [11 : 0] M_AXI_GP0_WID;
output [1 : 0] M_AXI_GP0_ARBURST;
output [1 : 0] M_AXI_GP0_ARLOCK;
output [2 : 0] M_AXI_GP0_ARSIZE;
output [1 : 0] M_AXI_GP0_AWBURST;
output [1 : 0] M_AXI_GP0_AWLOCK;
output [2 : 0] M_AXI_GP0_AWSIZE;
output [2 : 0] M_AXI_GP0_ARPROT;
output [2 : 0] M_AXI_GP0_AWPROT;
output [31 : 0] M_AXI_GP0_ARADDR;
output [31 : 0] M_AXI_GP0_AWADDR;
output [31 : 0] M_AXI_GP0_WDATA;
output [3 : 0] M_AXI_GP0_ARCACHE;
output [3 : 0] M_AXI_GP0_ARLEN;
output [3 : 0] M_AXI_GP0_ARQOS;
output [3 : 0] M_AXI_GP0_AWCACHE;
output [3 : 0] M_AXI_GP0_AWLEN;
output [3 : 0] M_AXI_GP0_AWQOS;
output [3 : 0] M_AXI_GP0_WSTRB;
input M_AXI_GP0_ACLK;
input M_AXI_GP0_ARREADY;
input M_AXI_GP0_AWREADY;
input M_AXI_GP0_BVALID;
input M_AXI_GP0_RLAST;
input M_AXI_GP0_RVALID;
input M_AXI_GP0_WREADY;
input [11 : 0] M_AXI_GP0_BID;
input [11 : 0] M_AXI_GP0_RID;
input [1 : 0] M_AXI_GP0_BRESP;
input [1 : 0] M_AXI_GP0_RRESP;
input [31 : 0] M_AXI_GP0_RDATA;
output FCLK_RESET0_N;
input [53 : 0] MIO;
input DDR_CAS_n;
input DDR_CKE;
input DDR_Clk_n;
input DDR_Clk;
input DDR_CS_n;
input DDR_DRSTB;
input DDR_ODT;
input DDR_RAS_n;
input DDR_WEB;
input [2 : 0] DDR_BankAddr;
input [14 : 0] DDR_Addr;
input DDR_VRN;
input DDR_VRP;
input [3 : 0] DDR_DM;
input [31 : 0] DDR_DQ;
input [3 : 0] DDR_DQS_n;
input [3 : 0] DDR_DQS;
input PS_SRSTB;
input PS_CLK;
input PS_PORB;
processing_system7_bfm_v2_0_5_processing_system7_bfm #(
.C_USE_M_AXI_GP0(1),
.C_USE_M_AXI_GP1(0),
.C_USE_S_AXI_ACP(0),
.C_USE_S_AXI_GP0(0),
.C_USE_S_AXI_GP1(0),
.C_USE_S_AXI_HP0(0),
.C_USE_S_AXI_HP1(0),
.C_USE_S_AXI_HP2(0),
.C_USE_S_AXI_HP3(0),
.C_S_AXI_HP0_DATA_WIDTH(64),
.C_S_AXI_HP1_DATA_WIDTH(64),
.C_S_AXI_HP2_DATA_WIDTH(64),
.C_S_AXI_HP3_DATA_WIDTH(64),
.C_HIGH_OCM_EN(0),
.C_FCLK_CLK0_FREQ(10.0),
.C_FCLK_CLK1_FREQ(10.0),
.C_FCLK_CLK2_FREQ(10.0),
.C_FCLK_CLK3_FREQ(10.0),
.C_M_AXI_GP0_ENABLE_STATIC_REMAP(0),
.C_M_AXI_GP1_ENABLE_STATIC_REMAP(0),
.C_M_AXI_GP0_THREAD_ID_WIDTH (12),
.C_M_AXI_GP1_THREAD_ID_WIDTH (12)
) inst (
.M_AXI_GP0_ARVALID(M_AXI_GP0_ARVALID),
.M_AXI_GP0_AWVALID(M_AXI_GP0_AWVALID),
.M_AXI_GP0_BREADY(M_AXI_GP0_BREADY),
.M_AXI_GP0_RREADY(M_AXI_GP0_RREADY),
.M_AXI_GP0_WLAST(M_AXI_GP0_WLAST),
.M_AXI_GP0_WVALID(M_AXI_GP0_WVALID),
.M_AXI_GP0_ARID(M_AXI_GP0_ARID),
.M_AXI_GP0_AWID(M_AXI_GP0_AWID),
.M_AXI_GP0_WID(M_AXI_GP0_WID),
.M_AXI_GP0_ARBURST(M_AXI_GP0_ARBURST),
.M_AXI_GP0_ARLOCK(M_AXI_GP0_ARLOCK),
.M_AXI_GP0_ARSIZE(M_AXI_GP0_ARSIZE),
.M_AXI_GP0_AWBURST(M_AXI_GP0_AWBURST),
.M_AXI_GP0_AWLOCK(M_AXI_GP0_AWLOCK),
.M_AXI_GP0_AWSIZE(M_AXI_GP0_AWSIZE),
.M_AXI_GP0_ARPROT(M_AXI_GP0_ARPROT),
.M_AXI_GP0_AWPROT(M_AXI_GP0_AWPROT),
.M_AXI_GP0_ARADDR(M_AXI_GP0_ARADDR),
.M_AXI_GP0_AWADDR(M_AXI_GP0_AWADDR),
.M_AXI_GP0_WDATA(M_AXI_GP0_WDATA),
.M_AXI_GP0_ARCACHE(M_AXI_GP0_ARCACHE),
.M_AXI_GP0_ARLEN(M_AXI_GP0_ARLEN),
.M_AXI_GP0_ARQOS(M_AXI_GP0_ARQOS),
.M_AXI_GP0_AWCACHE(M_AXI_GP0_AWCACHE),
.M_AXI_GP0_AWLEN(M_AXI_GP0_AWLEN),
.M_AXI_GP0_AWQOS(M_AXI_GP0_AWQOS),
.M_AXI_GP0_WSTRB(M_AXI_GP0_WSTRB),
.M_AXI_GP0_ACLK(M_AXI_GP0_ACLK),
.M_AXI_GP0_ARREADY(M_AXI_GP0_ARREADY),
.M_AXI_GP0_AWREADY(M_AXI_GP0_AWREADY),
.M_AXI_GP0_BVALID(M_AXI_GP0_BVALID),
.M_AXI_GP0_RLAST(M_AXI_GP0_RLAST),
.M_AXI_GP0_RVALID(M_AXI_GP0_RVALID),
.M_AXI_GP0_WREADY(M_AXI_GP0_WREADY),
.M_AXI_GP0_BID(M_AXI_GP0_BID),
.M_AXI_GP0_RID(M_AXI_GP0_RID),
.M_AXI_GP0_BRESP(M_AXI_GP0_BRESP),
.M_AXI_GP0_RRESP(M_AXI_GP0_RRESP),
.M_AXI_GP0_RDATA(M_AXI_GP0_RDATA),
.M_AXI_GP1_ARVALID(),
.M_AXI_GP1_AWVALID(),
.M_AXI_GP1_BREADY(),
.M_AXI_GP1_RREADY(),
.M_AXI_GP1_WLAST(),
.M_AXI_GP1_WVALID(),
.M_AXI_GP1_ARID(),
.M_AXI_GP1_AWID(),
.M_AXI_GP1_WID(),
.M_AXI_GP1_ARBURST(),
.M_AXI_GP1_ARLOCK(),
.M_AXI_GP1_ARSIZE(),
.M_AXI_GP1_AWBURST(),
.M_AXI_GP1_AWLOCK(),
.M_AXI_GP1_AWSIZE(),
.M_AXI_GP1_ARPROT(),
.M_AXI_GP1_AWPROT(),
.M_AXI_GP1_ARADDR(),
.M_AXI_GP1_AWADDR(),
.M_AXI_GP1_WDATA(),
.M_AXI_GP1_ARCACHE(),
.M_AXI_GP1_ARLEN(),
.M_AXI_GP1_ARQOS(),
.M_AXI_GP1_AWCACHE(),
.M_AXI_GP1_AWLEN(),
.M_AXI_GP1_AWQOS(),
.M_AXI_GP1_WSTRB(),
.M_AXI_GP1_ACLK(1'B0),
.M_AXI_GP1_ARREADY(1'B0),
.M_AXI_GP1_AWREADY(1'B0),
.M_AXI_GP1_BVALID(1'B0),
.M_AXI_GP1_RLAST(1'B0),
.M_AXI_GP1_RVALID(1'B0),
.M_AXI_GP1_WREADY(1'B0),
.M_AXI_GP1_BID(12'B0),
.M_AXI_GP1_RID(12'B0),
.M_AXI_GP1_BRESP(2'B0),
.M_AXI_GP1_RRESP(2'B0),
.M_AXI_GP1_RDATA(32'B0),
.S_AXI_GP0_ARREADY(),
.S_AXI_GP0_AWREADY(),
.S_AXI_GP0_BVALID(),
.S_AXI_GP0_RLAST(),
.S_AXI_GP0_RVALID(),
.S_AXI_GP0_WREADY(),
.S_AXI_GP0_BRESP(),
.S_AXI_GP0_RRESP(),
.S_AXI_GP0_RDATA(),
.S_AXI_GP0_BID(),
.S_AXI_GP0_RID(),
.S_AXI_GP0_ACLK(1'B0),
.S_AXI_GP0_ARVALID(1'B0),
.S_AXI_GP0_AWVALID(1'B0),
.S_AXI_GP0_BREADY(1'B0),
.S_AXI_GP0_RREADY(1'B0),
.S_AXI_GP0_WLAST(1'B0),
.S_AXI_GP0_WVALID(1'B0),
.S_AXI_GP0_ARBURST(2'B0),
.S_AXI_GP0_ARLOCK(2'B0),
.S_AXI_GP0_ARSIZE(3'B0),
.S_AXI_GP0_AWBURST(2'B0),
.S_AXI_GP0_AWLOCK(2'B0),
.S_AXI_GP0_AWSIZE(3'B0),
.S_AXI_GP0_ARPROT(3'B0),
.S_AXI_GP0_AWPROT(3'B0),
.S_AXI_GP0_ARADDR(32'B0),
.S_AXI_GP0_AWADDR(32'B0),
.S_AXI_GP0_WDATA(32'B0),
.S_AXI_GP0_ARCACHE(4'B0),
.S_AXI_GP0_ARLEN(4'B0),
.S_AXI_GP0_ARQOS(4'B0),
.S_AXI_GP0_AWCACHE(4'B0),
.S_AXI_GP0_AWLEN(4'B0),
.S_AXI_GP0_AWQOS(4'B0),
.S_AXI_GP0_WSTRB(4'B0),
.S_AXI_GP0_ARID(6'B0),
.S_AXI_GP0_AWID(6'B0),
.S_AXI_GP0_WID(6'B0),
.S_AXI_GP1_ARREADY(),
.S_AXI_GP1_AWREADY(),
.S_AXI_GP1_BVALID(),
.S_AXI_GP1_RLAST(),
.S_AXI_GP1_RVALID(),
.S_AXI_GP1_WREADY(),
.S_AXI_GP1_BRESP(),
.S_AXI_GP1_RRESP(),
.S_AXI_GP1_RDATA(),
.S_AXI_GP1_BID(),
.S_AXI_GP1_RID(),
.S_AXI_GP1_ACLK(1'B0),
.S_AXI_GP1_ARVALID(1'B0),
.S_AXI_GP1_AWVALID(1'B0),
.S_AXI_GP1_BREADY(1'B0),
.S_AXI_GP1_RREADY(1'B0),
.S_AXI_GP1_WLAST(1'B0),
.S_AXI_GP1_WVALID(1'B0),
.S_AXI_GP1_ARBURST(2'B0),
.S_AXI_GP1_ARLOCK(2'B0),
.S_AXI_GP1_ARSIZE(3'B0),
.S_AXI_GP1_AWBURST(2'B0),
.S_AXI_GP1_AWLOCK(2'B0),
.S_AXI_GP1_AWSIZE(3'B0),
.S_AXI_GP1_ARPROT(3'B0),
.S_AXI_GP1_AWPROT(3'B0),
.S_AXI_GP1_ARADDR(32'B0),
.S_AXI_GP1_AWADDR(32'B0),
.S_AXI_GP1_WDATA(32'B0),
.S_AXI_GP1_ARCACHE(4'B0),
.S_AXI_GP1_ARLEN(4'B0),
.S_AXI_GP1_ARQOS(4'B0),
.S_AXI_GP1_AWCACHE(4'B0),
.S_AXI_GP1_AWLEN(4'B0),
.S_AXI_GP1_AWQOS(4'B0),
.S_AXI_GP1_WSTRB(4'B0),
.S_AXI_GP1_ARID(6'B0),
.S_AXI_GP1_AWID(6'B0),
.S_AXI_GP1_WID(6'B0),
.S_AXI_ACP_ARREADY(),
.S_AXI_ACP_AWREADY(),
.S_AXI_ACP_BVALID(),
.S_AXI_ACP_RLAST(),
.S_AXI_ACP_RVALID(),
.S_AXI_ACP_WREADY(),
.S_AXI_ACP_BRESP(),
.S_AXI_ACP_RRESP(),
.S_AXI_ACP_BID(),
.S_AXI_ACP_RID(),
.S_AXI_ACP_RDATA(),
.S_AXI_ACP_ACLK(1'B0),
.S_AXI_ACP_ARVALID(1'B0),
.S_AXI_ACP_AWVALID(1'B0),
.S_AXI_ACP_BREADY(1'B0),
.S_AXI_ACP_RREADY(1'B0),
.S_AXI_ACP_WLAST(1'B0),
.S_AXI_ACP_WVALID(1'B0),
.S_AXI_ACP_ARID(3'B0),
.S_AXI_ACP_ARPROT(3'B0),
.S_AXI_ACP_AWID(3'B0),
.S_AXI_ACP_AWPROT(3'B0),
.S_AXI_ACP_WID(3'B0),
.S_AXI_ACP_ARADDR(32'B0),
.S_AXI_ACP_AWADDR(32'B0),
.S_AXI_ACP_ARCACHE(4'B0),
.S_AXI_ACP_ARLEN(4'B0),
.S_AXI_ACP_ARQOS(4'B0),
.S_AXI_ACP_AWCACHE(4'B0),
.S_AXI_ACP_AWLEN(4'B0),
.S_AXI_ACP_AWQOS(4'B0),
.S_AXI_ACP_ARBURST(2'B0),
.S_AXI_ACP_ARLOCK(2'B0),
.S_AXI_ACP_ARSIZE(3'B0),
.S_AXI_ACP_AWBURST(2'B0),
.S_AXI_ACP_AWLOCK(2'B0),
.S_AXI_ACP_AWSIZE(3'B0),
.S_AXI_ACP_ARUSER(5'B0),
.S_AXI_ACP_AWUSER(5'B0),
.S_AXI_ACP_WDATA(64'B0),
.S_AXI_ACP_WSTRB(8'B0),
.S_AXI_HP0_ARREADY(),
.S_AXI_HP0_AWREADY(),
.S_AXI_HP0_BVALID(),
.S_AXI_HP0_RLAST(),
.S_AXI_HP0_RVALID(),
.S_AXI_HP0_WREADY(),
.S_AXI_HP0_BRESP(),
.S_AXI_HP0_RRESP(),
.S_AXI_HP0_BID(),
.S_AXI_HP0_RID(),
.S_AXI_HP0_RDATA(),
.S_AXI_HP0_ACLK(1'B0),
.S_AXI_HP0_ARVALID(1'B0),
.S_AXI_HP0_AWVALID(1'B0),
.S_AXI_HP0_BREADY(1'B0),
.S_AXI_HP0_RREADY(1'B0),
.S_AXI_HP0_WLAST(1'B0),
.S_AXI_HP0_WVALID(1'B0),
.S_AXI_HP0_ARBURST(2'B0),
.S_AXI_HP0_ARLOCK(2'B0),
.S_AXI_HP0_ARSIZE(3'B0),
.S_AXI_HP0_AWBURST(2'B0),
.S_AXI_HP0_AWLOCK(2'B0),
.S_AXI_HP0_AWSIZE(3'B0),
.S_AXI_HP0_ARPROT(3'B0),
.S_AXI_HP0_AWPROT(3'B0),
.S_AXI_HP0_ARADDR(32'B0),
.S_AXI_HP0_AWADDR(32'B0),
.S_AXI_HP0_ARCACHE(4'B0),
.S_AXI_HP0_ARLEN(4'B0),
.S_AXI_HP0_ARQOS(4'B0),
.S_AXI_HP0_AWCACHE(4'B0),
.S_AXI_HP0_AWLEN(4'B0),
.S_AXI_HP0_AWQOS(4'B0),
.S_AXI_HP0_ARID(6'B0),
.S_AXI_HP0_AWID(6'B0),
.S_AXI_HP0_WID(6'B0),
.S_AXI_HP0_WDATA(64'B0),
.S_AXI_HP0_WSTRB(8'B0),
.S_AXI_HP1_ARREADY(),
.S_AXI_HP1_AWREADY(),
.S_AXI_HP1_BVALID(),
.S_AXI_HP1_RLAST(),
.S_AXI_HP1_RVALID(),
.S_AXI_HP1_WREADY(),
.S_AXI_HP1_BRESP(),
.S_AXI_HP1_RRESP(),
.S_AXI_HP1_BID(),
.S_AXI_HP1_RID(),
.S_AXI_HP1_RDATA(),
.S_AXI_HP1_ACLK(1'B0),
.S_AXI_HP1_ARVALID(1'B0),
.S_AXI_HP1_AWVALID(1'B0),
.S_AXI_HP1_BREADY(1'B0),
.S_AXI_HP1_RREADY(1'B0),
.S_AXI_HP1_WLAST(1'B0),
.S_AXI_HP1_WVALID(1'B0),
.S_AXI_HP1_ARBURST(2'B0),
.S_AXI_HP1_ARLOCK(2'B0),
.S_AXI_HP1_ARSIZE(3'B0),
.S_AXI_HP1_AWBURST(2'B0),
.S_AXI_HP1_AWLOCK(2'B0),
.S_AXI_HP1_AWSIZE(3'B0),
.S_AXI_HP1_ARPROT(3'B0),
.S_AXI_HP1_AWPROT(3'B0),
.S_AXI_HP1_ARADDR(32'B0),
.S_AXI_HP1_AWADDR(32'B0),
.S_AXI_HP1_ARCACHE(4'B0),
.S_AXI_HP1_ARLEN(4'B0),
.S_AXI_HP1_ARQOS(4'B0),
.S_AXI_HP1_AWCACHE(4'B0),
.S_AXI_HP1_AWLEN(4'B0),
.S_AXI_HP1_AWQOS(4'B0),
.S_AXI_HP1_ARID(6'B0),
.S_AXI_HP1_AWID(6'B0),
.S_AXI_HP1_WID(6'B0),
.S_AXI_HP1_WDATA(64'B0),
.S_AXI_HP1_WSTRB(8'B0),
.S_AXI_HP2_ARREADY(),
.S_AXI_HP2_AWREADY(),
.S_AXI_HP2_BVALID(),
.S_AXI_HP2_RLAST(),
.S_AXI_HP2_RVALID(),
.S_AXI_HP2_WREADY(),
.S_AXI_HP2_BRESP(),
.S_AXI_HP2_RRESP(),
.S_AXI_HP2_BID(),
.S_AXI_HP2_RID(),
.S_AXI_HP2_RDATA(),
.S_AXI_HP2_ACLK(1'B0),
.S_AXI_HP2_ARVALID(1'B0),
.S_AXI_HP2_AWVALID(1'B0),
.S_AXI_HP2_BREADY(1'B0),
.S_AXI_HP2_RREADY(1'B0),
.S_AXI_HP2_WLAST(1'B0),
.S_AXI_HP2_WVALID(1'B0),
.S_AXI_HP2_ARBURST(2'B0),
.S_AXI_HP2_ARLOCK(2'B0),
.S_AXI_HP2_ARSIZE(3'B0),
.S_AXI_HP2_AWBURST(2'B0),
.S_AXI_HP2_AWLOCK(2'B0),
.S_AXI_HP2_AWSIZE(3'B0),
.S_AXI_HP2_ARPROT(3'B0),
.S_AXI_HP2_AWPROT(3'B0),
.S_AXI_HP2_ARADDR(32'B0),
.S_AXI_HP2_AWADDR(32'B0),
.S_AXI_HP2_ARCACHE(4'B0),
.S_AXI_HP2_ARLEN(4'B0),
.S_AXI_HP2_ARQOS(4'B0),
.S_AXI_HP2_AWCACHE(4'B0),
.S_AXI_HP2_AWLEN(4'B0),
.S_AXI_HP2_AWQOS(4'B0),
.S_AXI_HP2_ARID(6'B0),
.S_AXI_HP2_AWID(6'B0),
.S_AXI_HP2_WID(6'B0),
.S_AXI_HP2_WDATA(64'B0),
.S_AXI_HP2_WSTRB(8'B0),
.S_AXI_HP3_ARREADY(),
.S_AXI_HP3_AWREADY(),
.S_AXI_HP3_BVALID(),
.S_AXI_HP3_RLAST(),
.S_AXI_HP3_RVALID(),
.S_AXI_HP3_WREADY(),
.S_AXI_HP3_BRESP(),
.S_AXI_HP3_RRESP(),
.S_AXI_HP3_BID(),
.S_AXI_HP3_RID(),
.S_AXI_HP3_RDATA(),
.S_AXI_HP3_ACLK(1'B0),
.S_AXI_HP3_ARVALID(1'B0),
.S_AXI_HP3_AWVALID(1'B0),
.S_AXI_HP3_BREADY(1'B0),
.S_AXI_HP3_RREADY(1'B0),
.S_AXI_HP3_WLAST(1'B0),
.S_AXI_HP3_WVALID(1'B0),
.S_AXI_HP3_ARBURST(2'B0),
.S_AXI_HP3_ARLOCK(2'B0),
.S_AXI_HP3_ARSIZE(3'B0),
.S_AXI_HP3_AWBURST(2'B0),
.S_AXI_HP3_AWLOCK(2'B0),
.S_AXI_HP3_AWSIZE(3'B0),
.S_AXI_HP3_ARPROT(3'B0),
.S_AXI_HP3_AWPROT(3'B0),
.S_AXI_HP3_ARADDR(32'B0),
.S_AXI_HP3_AWADDR(32'B0),
.S_AXI_HP3_ARCACHE(4'B0),
.S_AXI_HP3_ARLEN(4'B0),
.S_AXI_HP3_ARQOS(4'B0),
.S_AXI_HP3_AWCACHE(4'B0),
.S_AXI_HP3_AWLEN(4'B0),
.S_AXI_HP3_AWQOS(4'B0),
.S_AXI_HP3_ARID(6'B0),
.S_AXI_HP3_AWID(6'B0),
.S_AXI_HP3_WID(6'B0),
.S_AXI_HP3_WDATA(64'B0),
.S_AXI_HP3_WSTRB(8'B0),
.FCLK_CLK0(),
.FCLK_CLK1(),
.FCLK_CLK2(),
.FCLK_CLK3(),
.FCLK_RESET0_N(FCLK_RESET0_N),
.FCLK_RESET1_N(),
.FCLK_RESET2_N(),
.FCLK_RESET3_N(),
.IRQ_F2P(16'B0),
.PS_SRSTB(PS_SRSTB),
.PS_CLK(PS_CLK),
.PS_PORB(PS_PORB)
);
endmodule
|
module alu (
input [31:0] x,
input [15:0] y,
output [31:0] out,
input [ 2:0] t,
input [ 2:0] func,
input [15:0] iflags,
output [ 8:0] oflags,
input word_op,
input [15:0] seg,
input [15:0] off,
input clk,
output div_exc
);
// Net declarations
wire [15:0] add, log, shi, rot;
wire [8:0] othflags;
wire [19:0] oth;
wire [31:0] cnv, mul;
wire af_add, af_cnv;
wire cf_cnv, cf_add, cf_mul, cf_log, cf_shi, cf_rot;
wire of_cnv, of_add, of_mul, of_log, of_shi, of_rot;
wire ofi, sfi, zfi, afi, pfi, cfi;
wire ofo, sfo, zfo, afo, pfo, cfo;
wire flags_unchanged;
wire dexc;
// Module instances
addsub add1 (x[15:0], y, add, func, word_op, cfi, cf_add, af_add, of_add);
conv cnv2 (
.x (x[15:0]),
.func (func),
.out (cnv),
.iflags ({afi, cfi}),
.oflags ({af_cnv, of_cnv, cf_cnv})
);
muldiv mul3 (
.x (x),
.y (y),
.o (mul),
.f (func),
.word_op (word_op),
.cfo (cf_mul),
.ofo (of_mul),
.clk (clk),
.exc (dexc)
);
bitlog log4 (x[15:0], y, log, func, cf_log, of_log);
shifts shi5 (x[15:0], y[4:0], shi, func[1:0], word_op, cfi, ofi, cf_shi, of_shi);
rotate rot6 (x[15:0], y[4:0], func[1:0], cfi, word_op, rot, cf_rot, ofi, of_rot);
othop oth7 (x[15:0], y, seg, off, iflags, func, word_op, oth, othflags);
mux8_16 m0(t, {8'd0, y[7:0]}, add, cnv[15:0],
mul[15:0], log, shi, rot, oth[15:0], out[15:0]);
mux8_16 m1(t, 16'd0, 16'd0, cnv[31:16], mul[31:16],
16'd0, 16'd0, 16'd0, {12'b0,oth[19:16]}, out[31:16]);
mux8_1 a1(t, 1'b0, cf_add, cf_cnv, cf_mul, cf_log, cf_shi, cf_rot, 1'b0, cfo);
mux8_1 a2(t, 1'b0, af_add, af_cnv, 1'b0, 1'b0, 1'b0, afi, 1'b0, afo);
mux8_1 a3(t, 1'b0, of_add, of_cnv, of_mul, of_log, of_shi, of_rot, 1'b0, ofo);
// Flags
assign pfo = flags_unchanged ? pfi : ^~ out[7:0];
assign zfo = flags_unchanged ? zfi
: ((word_op && (t!=3'd2)) ? ~|out[15:0] : ~|out[7:0]);
assign sfo = flags_unchanged ? sfi
: ((word_op && (t!=3'd2)) ? out[15] : out[7]);
assign oflags = (t == 3'd7) ? othflags
: { ofo, iflags[10:8], sfo, zfo, afo, pfo, cfo };
assign ofi = iflags[11];
assign sfi = iflags[7];
assign zfi = iflags[6];
assign afi = iflags[4];
assign pfi = iflags[2];
assign cfi = iflags[0];
assign flags_unchanged = (t == 3'd4 && func == 3'd2
|| t == 3'd5 && y[4:0] == 5'h0
|| t == 3'd6);
assign div_exc = func[1] && (t==3'd3) && dexc;
endmodule
|
module addsub (
input [15:0] x,
input [15:0] y,
output [15:0] out,
input [ 2:0] f,
input word_op,
input cfi,
output cfo,
output afo,
output ofo
);
// Net declarations
wire [15:0] op2;
wire ci;
wire cfoadd;
wire xs, ys, os;
// Module instances
fulladd16 fa0 ( // We instantiate only one adder
.x (x), // to have less hardware
.y (op2),
.ci (ci),
.co (cfoadd),
.z (out),
.s (f[2])
);
// Assignments
assign op2 = f[2] ? ~y
: ((f[1:0]==2'b11) ? { 8'b0, y[7:0] } : y);
assign ci = f[2] & f[1] | f[2] & ~f[0] & ~cfi
| f[2] & f[0] | (f==3'b0) & cfi;
assign afo = f[1] ? (f[2] ? &out[3:0] : ~|out[3:0] )
: (x[4] ^ y[4] ^ out[4]);
assign cfo = f[1] ? cfi /* inc, dec */
: (word_op ? cfoadd : (x[8]^y[8]^out[8]));
assign xs = word_op ? x[15] : x[7];
assign ys = word_op ? y[15] : y[7];
assign os = word_op ? out[15] : out[7];
assign ofo = f[2] ? (~xs & ys & os | xs & ~ys & ~os)
: (~xs & ~ys & os | xs & ys & ~os);
endmodule
|
module conv (
input [15:0] x,
input [ 2:0] func,
output [31:0] out,
input [ 1:0] iflags, // afi, cfi
output [ 2:0] oflags // afo, ofo, cfo
);
// Net declarations
wire afi, cfi;
wire ofo, afo, cfo;
wire [15:0] aaa, aas;
wire [ 7:0] daa, tmpdaa, das, tmpdas;
wire [15:0] cbw, cwd;
wire acond, dcond;
wire tmpcf;
// Module instances
mux8_16 m0(func, cbw, aaa, aas, 16'd0,
cwd, {x[15:8], daa}, {x[15:8], das}, 16'd0, out[15:0]);
// Assignments
assign aaa = (acond ? (x + 16'h0106) : x) & 16'hff0f;
assign aas = (acond ? (x - 16'h0106) : x) & 16'hff0f;
assign tmpdaa = acond ? (x[7:0] + 8'h06) : x[7:0];
assign daa = dcond ? (tmpdaa + 8'h60) : tmpdaa;
assign tmpdas = acond ? (x[7:0] - 8'h06) : x[7:0];
assign das = dcond ? (tmpdas - 8'h60) : tmpdas;
assign cbw = { { 8{x[ 7]}}, x[7:0] };
assign { out[31:16], cwd } = { {16{x[15]}}, x };
assign acond = ((x[7:0] & 8'h0f) > 8'h09) | afi;
assign dcond = (x[7:0] > 8'h99) | cfi;
assign afi = iflags[1];
assign cfi = iflags[0];
assign afo = acond;
assign ofo = 1'b0;
assign tmpcf = (x[7:0] < 8'h06) | cfi;
assign cfo = func[2] ? (dcond ? 1'b1 : (acond & tmpcf))
: acond;
assign oflags = { afo, ofo, cfo };
endmodule
|
module muldiv (
input [31:0] x, // 16 MSb for division
input [15:0] y,
output [31:0] o,
input [ 2:0] f,
input word_op,
output cfo,
output ofo,
input clk,
output exc
);
// Net declarations
wire as, bs, cfs, cfu;
wire [16:0] a, b;
wire [33:0] p;
wire div0, over, ovf, mint;
wire [33:0] zi;
wire [16:0] di;
wire [17:0] q;
wire [17:0] s;
// Module instantiations
mult signmul17 (
.clk (clk),
.a (a),
.b (b),
.p (p)
);
div_su #(34) dut (
.clk (clk),
.ena (1'b1),
.z (zi),
.d (di),
.q (q),
.s (s),
.ovf (ovf),
.div0 (div0)
);
// Sign ext. for imul
assign as = f[0] & (word_op ? x[15] : x[7]);
assign bs = f[0] & (word_op ? y[15] : y[7]);
assign a = word_op ? { as, x[15:0] }
: { {9{as}}, x[7:0] };
assign b = word_op ? { bs, y } : { {9{bs}}, y[7:0] };
assign zi = f[2] ? { 26'h0, x[7:0] }
: (word_op ? (f[0] ? { {2{x[31]}}, x }
: { 2'b0, x })
: (f[0] ? { {18{x[15]}}, x[15:0] }
: { 18'b0, x[15:0] }));
assign di = word_op ? (f[0] ? { y[15], y } : { 1'b0, y })
: (f[0] ? { {9{y[7]}}, y[7:0] }
: { 9'h000, y[7:0] });
assign o = f[2] ? { 16'h0, q[7:0], s[7:0] }
: (f[1] ? ( word_op ? {s[15:0], q[15:0]}
: {16'h0, s[7:0], q[7:0]})
: p[31:0]);
assign ofo = f[1] ? 1'b0 : cfo;
assign cfo = f[1] ? 1'b0 : !(f[0] ? cfs : cfu);
assign cfu = word_op ? (o[31:16] == 16'h0)
: (o[15:8] == 8'h0);
assign cfs = word_op ? (o[31:16] == {16{o[15]}})
: (o[15:8] == {8{o[7]}});
// Exceptions
assign over = f[2] ? 1'b0
: (word_op ? (f[0] ? (q[17:16]!={2{q[15]}})
: (q[17:16]!=2'b0) )
: (f[0] ? (q[17:8]!={10{q[7]}})
: (q[17:8]!=10'h000)));
assign mint = f[0] & (word_op ? (x==32'h80000000)
: (x==16'h8000));
assign exc = div0 | (!f[2] & ovf) | over | mint;
endmodule
|
module bitlog(x, y, out, func, cfo, ofo);
// IO ports
input [15:0] x, y;
input [2:0] func;
output [15:0] out;
output cfo, ofo;
// Net declarations
wire [15:0] and_n, or_n, not_n, xor_n;
// Module instantiations
mux8_16 m0(func, and_n, or_n, not_n, xor_n, 16'd0, 16'd0, 16'd0, 16'd0, out);
// Assignments
assign and_n = x & y;
assign or_n = x | y;
assign not_n = ~x;
assign xor_n = x ^ y;
assign cfo = 1'b0;
assign ofo = 1'b0;
endmodule
|
module shifts(x, y, out, func, word_op, cfi, ofi, cfo, ofo);
// IO ports
input [15:0] x;
input [ 4:0] y;
input [1:0] func;
input word_op;
output [15:0] out;
output cfo, ofo;
input cfi, ofi;
// Net declarations
wire [15:0] sal, sar, shr, sal16, sar16, shr16;
wire [7:0] sal8, sar8, shr8;
wire ofo_shl, ofo_sar, ofo_shr;
wire cfo_sal8, cfo_sal16, cfo_sar8, cfo_sar16, cfo_shr8, cfo_shr16;
wire cfo16, cfo8;
wire unchanged;
// Module instantiations
mux4_16 m0(func, sal, sar, shr, 16'd0, out);
// Assignments
assign { cfo_sal16, sal16 } = x << y;
assign { sar16, cfo_sar16 } = (y > 5'd16) ? 17'h1ffff
: (({x,1'b0} >> y) | (x[15] ? (17'h1ffff << (17 - y))
: 17'h0));
assign { shr16, cfo_shr16 } = ({x,1'b0} >> y);
assign { cfo_sal8, sal8 } = x[7:0] << y;
assign { sar8, cfo_sar8 } = (y > 5'd8) ? 9'h1ff
: (({x[7:0],1'b0} >> y) | (x[7] ? (9'h1ff << (9 - y))
: 9'h0));
assign { shr8, cfo_shr8 } = ({x[7:0],1'b0} >> y);
assign sal = word_op ? sal16 : { 8'd0, sal8 };
assign shr = word_op ? shr16 : { 8'd0, shr8 };
assign sar = word_op ? sar16 : { {8{sar8[7]}}, sar8 };
assign ofo = unchanged ? ofi
: (func[1] ? ofo_shr : (func[0] ? ofo_sar : ofo_shl));
assign cfo16 = func[1] ? cfo_shr16
: (func[0] ? cfo_sar16 : cfo_sal16);
assign cfo8 = func[1] ? cfo_shr8
: (func[0] ? cfo_sar8 : cfo_sal8);
assign cfo = unchanged ? cfi : (word_op ? cfo16 : cfo8);
assign ofo_shl = word_op ? (out[15] != cfo) : (out[7] != cfo);
assign ofo_sar = 1'b0;
assign ofo_shr = word_op ? x[15] : x[7];
assign unchanged = word_op ? (y==5'b0) : (y[3:0]==4'b0);
endmodule
|
module othop (x, y, seg, off, iflags, func, word_op, out, oflags);
// IO ports
input [15:0] x, y, off, seg, iflags;
input [2:0] func;
input word_op;
output [19:0] out;
output [8:0] oflags;
// Net declarations
wire [15:0] deff, deff2, outf, clcm, setf, intf, strf;
wire [19:0] dcmp, dcmp2;
wire dfi;
// Module instantiations
mux8_16 m0(func, dcmp[15:0], dcmp2[15:0], deff, outf, clcm, setf,
intf, strf, out[15:0]);
assign out[19:16] = func ? dcmp2[19:16] : dcmp[19:16];
// Assignments
assign dcmp = (seg << 4) + deff;
assign dcmp2 = (seg << 4) + deff2;
assign deff = x + y + off;
assign deff2 = x + y + off + 16'd2;
assign outf = y;
assign clcm = y[2] ? (y[1] ? /* -1: clc */ {iflags[15:1], 1'b0}
: /* 4: cld */ {iflags[15:11], 1'b0, iflags[9:0]})
: (y[1] ? /* 2: cli */ {iflags[15:10], 1'b0, iflags[8:0]}
: /* 0: cmc */ {iflags[15:1], ~iflags[0]});
assign setf = y[2] ? (y[1] ? /* -1: stc */ {iflags[15:1], 1'b1}
: /* 4: std */ {iflags[15:11], 1'b1, iflags[9:0]})
: (y[1] ? /* 2: sti */ {iflags[15:10], 1'b1, iflags[8:0]}
: /* 0: outf */ iflags);
assign intf = {iflags[15:10], 2'b0, iflags[7:0]};
assign dfi = iflags[10];
assign strf = dfi ? (x - y) : (x + y);
assign oflags = word_op ? { out[11:6], out[4], out[2], out[0] }
: { iflags[11:8], out[7:6], out[4], out[2], out[0] };
endmodule
|
module master_clock_0002(
// interface 'refclk'
input wire refclk,
// interface 'reset'
input wire rst,
// interface 'outclk0'
output wire outclk_0,
// interface 'outclk1'
output wire outclk_1,
// interface 'locked'
output wire locked
);
altera_pll #(
.fractional_vco_multiplier("false"),
.reference_clock_frequency("50.0 MHz"),
.operation_mode("direct"),
.number_of_clocks(2),
.output_clock_frequency0("150.000000 MHz"),
.phase_shift0("0 ps"),
.duty_cycle0(50),
.output_clock_frequency1("40.000000 MHz"),
.phase_shift1("0 ps"),
.duty_cycle1(50),
.output_clock_frequency2("0 MHz"),
.phase_shift2("0 ps"),
.duty_cycle2(50),
.output_clock_frequency3("0 MHz"),
.phase_shift3("0 ps"),
.duty_cycle3(50),
.output_clock_frequency4("0 MHz"),
.phase_shift4("0 ps"),
.duty_cycle4(50),
.output_clock_frequency5("0 MHz"),
.phase_shift5("0 ps"),
.duty_cycle5(50),
.output_clock_frequency6("0 MHz"),
.phase_shift6("0 ps"),
.duty_cycle6(50),
.output_clock_frequency7("0 MHz"),
.phase_shift7("0 ps"),
.duty_cycle7(50),
.output_clock_frequency8("0 MHz"),
.phase_shift8("0 ps"),
.duty_cycle8(50),
.output_clock_frequency9("0 MHz"),
.phase_shift9("0 ps"),
.duty_cycle9(50),
.output_clock_frequency10("0 MHz"),
.phase_shift10("0 ps"),
.duty_cycle10(50),
.output_clock_frequency11("0 MHz"),
.phase_shift11("0 ps"),
.duty_cycle11(50),
.output_clock_frequency12("0 MHz"),
.phase_shift12("0 ps"),
.duty_cycle12(50),
.output_clock_frequency13("0 MHz"),
.phase_shift13("0 ps"),
.duty_cycle13(50),
.output_clock_frequency14("0 MHz"),
.phase_shift14("0 ps"),
.duty_cycle14(50),
.output_clock_frequency15("0 MHz"),
.phase_shift15("0 ps"),
.duty_cycle15(50),
.output_clock_frequency16("0 MHz"),
.phase_shift16("0 ps"),
.duty_cycle16(50),
.output_clock_frequency17("0 MHz"),
.phase_shift17("0 ps"),
.duty_cycle17(50),
.pll_type("General"),
.pll_subtype("General")
) altera_pll_i (
.rst (rst),
.outclk ({outclk_1, outclk_0}),
.locked (locked),
.fboutclk ( ),
.fbclk (1'b0),
.refclk (refclk)
);
endmodule
|
module
// and do not propogate out to other modules that may be attached, complicating
// timing assertions.
//
bsg_two_fifo
#(.width_p(channel_width_p)
) twofer
(.clk_i (core_clk_i)
,.reset_i(core_link_reset_i)
// we feed this into the local yumi, but only if it is valid
,.ready_o(core_async_fifo_ready_li)
,.data_i (core_async_fifo_data_lo)
,.v_i (core_async_fifo_valid_lo)
,.v_o (core_valid_o)
,.data_o (core_data_o)
,.yumi_i (core_yumi_i)
);
// a word was transferred to fifo if ...
assign core_async_fifo_deque = core_async_fifo_valid_lo & core_async_fifo_ready_li;
end
else
begin
// keep async_fifo isolated when reset is asserted
assign core_valid_o = (core_link_reset_i)? 1'b0 : core_async_fifo_valid_lo;
assign core_data_o = core_async_fifo_data_lo;
assign core_async_fifo_deque = core_yumi_i;
end
// **********************************************
// credit return
//
// these are credits coming from the receive end of the async fifo in the core clk
// domain and passing to the io clk domain and out of the chip.
//
logic [lg_credit_to_token_decimation_p+1-1:0] core_credits_sent_r;
// which bit of the core_credits_sent_r counter we use determines
// the value of the token line in credits
//
//
// this signal's register should be placed right next to the I/O pad:
// glitch sensitive.
assign core_token_r_o = core_credits_sent_r[lg_credit_to_token_decimation_p];
// Increase token counter when dequeue from async fifo
bsg_counter_clear_up
#(.max_val_p({(lg_credit_to_token_decimation_p+1){1'b1}})
,.init_val_p(0)
,.disable_overflow_warning_p(1) // Allow overflow for this counter
)
token_counter
(.clk_i (core_clk_i)
,.reset_i(core_link_reset_i)
,.clear_i(1'b0)
,.up_i (core_async_fifo_deque)
,.count_o(core_credits_sent_r)
);
endmodule
|
module RAT_Mux4x1_8_0_1
(A,
B,
C,
D,
SEL,
X);
input [7:0]A;
input [7:0]B;
input [7:0]C;
input [7:0]D;
input [1:0]SEL;
output [7:0]X;
wire [7:0]A;
wire [7:0]B;
wire [7:0]C;
wire [7:0]D;
wire [1:0]SEL;
wire [7:0]X;
RAT_Mux4x1_8_0_1_Mux4x1_8 U0
(.A(A),
.B(B),
.C(C),
.D(D),
.SEL(SEL),
.X(X));
endmodule
|
module RAT_Mux4x1_8_0_1_Mux4x1_8
(X,
D,
B,
C,
SEL,
A);
output [7:0]X;
input [7:0]D;
input [7:0]B;
input [7:0]C;
input [1:0]SEL;
input [7:0]A;
wire [7:0]A;
wire [7:0]B;
wire [7:0]C;
wire [7:0]D;
wire [1:0]SEL;
wire [7:0]X;
LUT6 #(
.INIT(64'hAACCAACCF0FFF000))
\X[0]_INST_0
(.I0(D[0]),
.I1(B[0]),
.I2(C[0]),
.I3(SEL[1]),
.I4(A[0]),
.I5(SEL[0]),
.O(X[0]));
LUT6 #(
.INIT(64'hAACCAACCF0FFF000))
\X[1]_INST_0
(.I0(D[1]),
.I1(B[1]),
.I2(C[1]),
.I3(SEL[1]),
.I4(A[1]),
.I5(SEL[0]),
.O(X[1]));
LUT6 #(
.INIT(64'hAACCAACCF0FFF000))
\X[2]_INST_0
(.I0(D[2]),
.I1(B[2]),
.I2(C[2]),
.I3(SEL[1]),
.I4(A[2]),
.I5(SEL[0]),
.O(X[2]));
LUT6 #(
.INIT(64'hAACCAACCF0FFF000))
\X[3]_INST_0
(.I0(D[3]),
.I1(B[3]),
.I2(C[3]),
.I3(SEL[1]),
.I4(A[3]),
.I5(SEL[0]),
.O(X[3]));
LUT6 #(
.INIT(64'hAACCAACCF0FFF000))
\X[4]_INST_0
(.I0(D[4]),
.I1(B[4]),
.I2(C[4]),
.I3(SEL[1]),
.I4(A[4]),
.I5(SEL[0]),
.O(X[4]));
LUT6 #(
.INIT(64'hAACCAACCF0FFF000))
\X[5]_INST_0
(.I0(D[5]),
.I1(B[5]),
.I2(C[5]),
.I3(SEL[1]),
.I4(A[5]),
.I5(SEL[0]),
.O(X[5]));
LUT6 #(
.INIT(64'hAACCAACCF0FFF000))
\X[6]_INST_0
(.I0(D[6]),
.I1(B[6]),
.I2(C[6]),
.I3(SEL[1]),
.I4(A[6]),
.I5(SEL[0]),
.O(X[6]));
LUT6 #(
.INIT(64'hAACCAACCF0FFF000))
\X[7]_INST_0
(.I0(D[7]),
.I1(B[7]),
.I2(C[7]),
.I3(SEL[1]),
.I4(A[7]),
.I5(SEL[0]),
.O(X[7]));
endmodule
|
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
|
module top();
// Inputs are registered
reg A_N;
reg B_N;
reg C;
reg D;
reg VPWR;
reg VGND;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A_N = 1'bX;
B_N = 1'bX;
C = 1'bX;
D = 1'bX;
VGND = 1'bX;
VPWR = 1'bX;
#20 A_N = 1'b0;
#40 B_N = 1'b0;
#60 C = 1'b0;
#80 D = 1'b0;
#100 VGND = 1'b0;
#120 VPWR = 1'b0;
#140 A_N = 1'b1;
#160 B_N = 1'b1;
#180 C = 1'b1;
#200 D = 1'b1;
#220 VGND = 1'b1;
#240 VPWR = 1'b1;
#260 A_N = 1'b0;
#280 B_N = 1'b0;
#300 C = 1'b0;
#320 D = 1'b0;
#340 VGND = 1'b0;
#360 VPWR = 1'b0;
#380 VPWR = 1'b1;
#400 VGND = 1'b1;
#420 D = 1'b1;
#440 C = 1'b1;
#460 B_N = 1'b1;
#480 A_N = 1'b1;
#500 VPWR = 1'bx;
#520 VGND = 1'bx;
#540 D = 1'bx;
#560 C = 1'bx;
#580 B_N = 1'bx;
#600 A_N = 1'bx;
end
sky130_fd_sc_hs__and4bb dut (.A_N(A_N), .B_N(B_N), .C(C), .D(D), .VPWR(VPWR), .VGND(VGND), .X(X));
endmodule
|
module ram_sync_nolatch_2r1w #(
parameter BRAM_ADDR_WIDTH = `ADDR_LEN,
parameter BRAM_DATA_WIDTH = `DATA_LEN,
parameter DATA_DEPTH = 32
)
(
input wire clk,
input wire [BRAM_ADDR_WIDTH-1:0] raddr1,
input wire [BRAM_ADDR_WIDTH-1:0] raddr2,
output wire [BRAM_DATA_WIDTH-1:0] rdata1,
output wire [BRAM_DATA_WIDTH-1:0] rdata2,
input wire [BRAM_ADDR_WIDTH-1:0] waddr,
input wire [BRAM_DATA_WIDTH-1:0] wdata,
input wire we
);
reg [BRAM_DATA_WIDTH-1:0] mem [0:DATA_DEPTH-1];
integer i;
assign rdata1 = mem[raddr1];
assign rdata2 = mem[raddr2];
always @ (posedge clk) begin
if (we)
mem[waddr] <= wdata;
end
endmodule
|
module ram_sync_nolatch_2r2w #(
parameter BRAM_ADDR_WIDTH = `ADDR_LEN,
parameter BRAM_DATA_WIDTH = `DATA_LEN,
parameter DATA_DEPTH = 32
)
(
input wire clk,
input wire [BRAM_ADDR_WIDTH-1:0] raddr1,
input wire [BRAM_ADDR_WIDTH-1:0] raddr2,
output wire [BRAM_DATA_WIDTH-1:0] rdata1,
output wire [BRAM_DATA_WIDTH-1:0] rdata2,
input wire [BRAM_ADDR_WIDTH-1:0] waddr1,
input wire [BRAM_ADDR_WIDTH-1:0] waddr2,
input wire [BRAM_DATA_WIDTH-1:0] wdata1,
input wire [BRAM_DATA_WIDTH-1:0] wdata2,
input wire we1,
input wire we2
);
reg [BRAM_DATA_WIDTH-1:0] mem [0:DATA_DEPTH-1];
assign rdata1 = mem[raddr1];
assign rdata2 = mem[raddr2];
always @ (posedge clk) begin
if (we1)
mem[waddr1] <= wdata1;
if (we2)
mem[waddr2] <= wdata2;
end
endmodule
|
module ram_sync_nolatch_4r1w(
input wire clk,
input wire [BRAM_ADDR_WIDTH-1:0] raddr1,
input wire [BRAM_ADDR_WIDTH-1:0] raddr2,
input wire [BRAM_ADDR_WIDTH-1:0] raddr3,
input wire [BRAM_ADDR_WIDTH-1:0] raddr4,
output wire [BRAM_DATA_WIDTH-1:0] rdata1,
output wire [BRAM_DATA_WIDTH-1:0] rdata2,
output wire [BRAM_DATA_WIDTH-1:0] rdata3,
output wire [BRAM_DATA_WIDTH-1:0] rdata4,
input wire [BRAM_ADDR_WIDTH-1:0] waddr,
input wire [BRAM_DATA_WIDTH-1:0] wdata,
input wire we
);
parameter BRAM_ADDR_WIDTH = `ADDR_LEN;
parameter BRAM_DATA_WIDTH = `DATA_LEN;
parameter DATA_DEPTH = 32;
ram_sync_nolatch_2r1w
#(BRAM_ADDR_WIDTH, BRAM_DATA_WIDTH, DATA_DEPTH)
mem0(
.clk(clk),
.raddr1(raddr1),
.raddr2(raddr2),
.rdata1(rdata1),
.rdata2(rdata2),
.waddr(waddr),
.wdata(wdata),
.we(we)
);
ram_sync_nolatch_2r1w
#(BRAM_ADDR_WIDTH, BRAM_DATA_WIDTH, DATA_DEPTH)
mem1(
.clk(clk),
.raddr1(raddr3),
.raddr2(raddr4),
.rdata1(rdata3),
.rdata2(rdata4),
.waddr(waddr),
.wdata(wdata),
.we(we)
);
endmodule
|
module ram_sync_nolatch_4r2w #(
parameter BRAM_ADDR_WIDTH = `ADDR_LEN,
parameter BRAM_DATA_WIDTH = `DATA_LEN,
parameter DATA_DEPTH = 32
)
(
input wire clk,
input wire [BRAM_ADDR_WIDTH-1:0] raddr1,
input wire [BRAM_ADDR_WIDTH-1:0] raddr2,
input wire [BRAM_ADDR_WIDTH-1:0] raddr3,
input wire [BRAM_ADDR_WIDTH-1:0] raddr4,
output wire [BRAM_DATA_WIDTH-1:0] rdata1,
output wire [BRAM_DATA_WIDTH-1:0] rdata2,
output wire [BRAM_DATA_WIDTH-1:0] rdata3,
output wire [BRAM_DATA_WIDTH-1:0] rdata4,
input wire [BRAM_ADDR_WIDTH-1:0] waddr1,
input wire [BRAM_ADDR_WIDTH-1:0] waddr2,
input wire [BRAM_DATA_WIDTH-1:0] wdata1,
input wire [BRAM_DATA_WIDTH-1:0] wdata2,
input wire we1,
input wire we2
);
reg [BRAM_DATA_WIDTH-1:0] mem [0:DATA_DEPTH-1];
assign rdata1 = mem[raddr1];
assign rdata2 = mem[raddr2];
assign rdata3 = mem[raddr3];
assign rdata4 = mem[raddr4];
always @ (posedge clk) begin
if (we1)
mem[waddr1] <= wdata1;
if (we2)
mem[waddr2] <= wdata2;
end
endmodule
|
module ram_sync_nolatch_6r2w(
input wire clk,
input wire [BRAM_ADDR_WIDTH-1:0] raddr1,
input wire [BRAM_ADDR_WIDTH-1:0] raddr2,
input wire [BRAM_ADDR_WIDTH-1:0] raddr3,
input wire [BRAM_ADDR_WIDTH-1:0] raddr4,
input wire [BRAM_ADDR_WIDTH-1:0] raddr5,
input wire [BRAM_ADDR_WIDTH-1:0] raddr6,
output wire [BRAM_DATA_WIDTH-1:0] rdata1,
output wire [BRAM_DATA_WIDTH-1:0] rdata2,
output wire [BRAM_DATA_WIDTH-1:0] rdata3,
output wire [BRAM_DATA_WIDTH-1:0] rdata4,
output wire [BRAM_DATA_WIDTH-1:0] rdata5,
output wire [BRAM_DATA_WIDTH-1:0] rdata6,
input wire [BRAM_ADDR_WIDTH-1:0] waddr1,
input wire [BRAM_ADDR_WIDTH-1:0] waddr2,
input wire [BRAM_DATA_WIDTH-1:0] wdata1,
input wire [BRAM_DATA_WIDTH-1:0] wdata2,
input wire we1,
input wire we2
);
parameter BRAM_ADDR_WIDTH = `ADDR_LEN;
parameter BRAM_DATA_WIDTH = `DATA_LEN;
parameter DATA_DEPTH = 32;
ram_sync_nolatch_2r2w
#(BRAM_ADDR_WIDTH, BRAM_DATA_WIDTH, DATA_DEPTH)
mem0(
.clk(clk),
.raddr1(raddr1),
.raddr2(raddr2),
.rdata1(rdata1),
.rdata2(rdata2),
.waddr1(waddr1),
.waddr2(waddr2),
.wdata1(wdata1),
.wdata2(wdata2),
.we1(we1),
.we2(we2)
);
ram_sync_nolatch_2r2w
#(BRAM_ADDR_WIDTH, BRAM_DATA_WIDTH, DATA_DEPTH)
mem1(
.clk(clk),
.raddr1(raddr3),
.raddr2(raddr4),
.rdata1(rdata3),
.rdata2(rdata4),
.waddr1(waddr1),
.waddr2(waddr2),
.wdata1(wdata1),
.wdata2(wdata2),
.we1(we1),
.we2(we2)
);
ram_sync_nolatch_2r2w
#(BRAM_ADDR_WIDTH, BRAM_DATA_WIDTH, DATA_DEPTH)
mem2(
.clk(clk),
.raddr1(raddr5),
.raddr2(raddr6),
.rdata1(rdata5),
.rdata2(rdata6),
.waddr1(waddr1),
.waddr2(waddr2),
.wdata1(wdata1),
.wdata2(wdata2),
.we1(we1),
.we2(we2)
);
endmodule
|
module Prescaler(ins_o,ins_i,icm_i,rst_i,clk_i);
output ins_o;
input ins_i;
input [2:0] icm_i;
input rst_i;
input clk_i;
reg ins_o;
reg next_ins_o_reg;
reg [4:0] threshold_reg;
reg [4:0] next_counter_reg;
reg [4:0] counter_reg;
//threshold:
always @(icm_i )
begin
case(icm_i )
'h1, 'h2, 'h3 :
begin
threshold_reg =('h1);
end
'h4, 'h6 :
begin
threshold_reg =('h4);
end
'h5, 'h7 :
begin
threshold_reg =('h10);
end
default:
begin
threshold_reg =('h0);
end
endcase
end
//on_change:
always @(threshold_reg or counter_reg or ins_i )
begin
if (counter_reg ==threshold_reg )
begin
next_ins_o_reg =(0);
next_counter_reg =(0);
end
else if (ins_i )
begin
next_ins_o_reg =(1);
next_counter_reg =(counter_reg +1);
end
end
//registers:
always @(posedge clk_i or posedge rst_i )
begin
if (!rst_i &&clk_i )
begin
counter_reg <=(next_counter_reg );
ins_o <=(next_ins_o_reg );
end
else
begin
counter_reg <=(0);
ins_o <=(0);
end
end
endmodule
|
module fibonacci (
clk, //clock
reset, //reset the Multiplier
n, //Fibonacci number to calculate
result, //result of fibonacci calculation
ready //signals if the result is ready
);
parameter inBits = 8; //No of bits for n
parameter outBits = 16; //No of bits of Fib number
//----Input Ports---
input clk;
input reset;
input [inBits-1:0] n;
//---Output Ports---
output reg [outBits-1:0] result;
output reg ready;
//---Internal Registers---
reg [outBits-1:0] last;
reg [inBits-1:0] no;
reg [inBits-1:0] count;
always @(posedge clk) begin
if (reset) begin
result <= 16'b0;
last <= 16'b0;
no <= n;
count <= 16'b0;
//0th fibonacci number is 0, need to generate 1 afterwards
end else begin
if (result == 0 && !ready) begin
result <= 1;
end else if (ready) begin
result <= result;
end else begin
result <= result + last;
end
last <= result;
count <= count + 1;
end
ready <= count >= no;
$display("reset %b, count %d, result %d, ready %b, no %d, last %d",reset, count, result, ready, no, last);
end
endmodule
|
module digit_select(
d1,
d2,
d3,
d4,
control,
digit
);
// ==============================================================================
// Port Declarations
// ==============================================================================
input [3:0] d1;
input [3:0] d2;
input [3:0] d3;
input [3:0] d4;
input [1:0] control;
output [3:0] digit;
// ==============================================================================
// Implementation
// ==============================================================================
// Assign digit to display on SSD cathodes
assign digit = (control == 2'b11) ? d1 :
(control == 2'b10) ? d2 :
(control == 2'b01) ? d3 :
d4;
endmodule
|
module sky130_fd_sc_lp__o32a_4 (
X ,
A1 ,
A2 ,
A3 ,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__o32a base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.B2(B2),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
|
module sky130_fd_sc_lp__o32a_4 (
X ,
A1,
A2,
A3,
B1,
B2
);
output X ;
input A1;
input A2;
input A3;
input B1;
input B2;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__o32a base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.B2(B2)
);
endmodule
|
module processing_system7_bfm_v2_0_processing_system7_bfm
(
CAN0_PHY_TX,
CAN0_PHY_RX,
CAN1_PHY_TX,
CAN1_PHY_RX,
ENET0_GMII_TX_EN,
ENET0_GMII_TX_ER,
ENET0_MDIO_MDC,
ENET0_MDIO_O,
ENET0_MDIO_T,
ENET0_PTP_DELAY_REQ_RX,
ENET0_PTP_DELAY_REQ_TX,
ENET0_PTP_PDELAY_REQ_RX,
ENET0_PTP_PDELAY_REQ_TX,
ENET0_PTP_PDELAY_RESP_RX,
ENET0_PTP_PDELAY_RESP_TX,
ENET0_PTP_SYNC_FRAME_RX,
ENET0_PTP_SYNC_FRAME_TX,
ENET0_SOF_RX,
ENET0_SOF_TX,
ENET0_GMII_TXD,
ENET0_GMII_COL,
ENET0_GMII_CRS,
ENET0_EXT_INTIN,
ENET0_GMII_RX_CLK,
ENET0_GMII_RX_DV,
ENET0_GMII_RX_ER,
ENET0_GMII_TX_CLK,
ENET0_MDIO_I,
ENET0_GMII_RXD,
ENET1_GMII_TX_EN,
ENET1_GMII_TX_ER,
ENET1_MDIO_MDC,
ENET1_MDIO_O,
ENET1_MDIO_T,
ENET1_PTP_DELAY_REQ_RX,
ENET1_PTP_DELAY_REQ_TX,
ENET1_PTP_PDELAY_REQ_RX,
ENET1_PTP_PDELAY_REQ_TX,
ENET1_PTP_PDELAY_RESP_RX,
ENET1_PTP_PDELAY_RESP_TX,
ENET1_PTP_SYNC_FRAME_RX,
ENET1_PTP_SYNC_FRAME_TX,
ENET1_SOF_RX,
ENET1_SOF_TX,
ENET1_GMII_TXD,
ENET1_GMII_COL,
ENET1_GMII_CRS,
ENET1_EXT_INTIN,
ENET1_GMII_RX_CLK,
ENET1_GMII_RX_DV,
ENET1_GMII_RX_ER,
ENET1_GMII_TX_CLK,
ENET1_MDIO_I,
ENET1_GMII_RXD,
GPIO_I,
GPIO_O,
GPIO_T,
I2C0_SDA_I,
I2C0_SDA_O,
I2C0_SDA_T,
I2C0_SCL_I,
I2C0_SCL_O,
I2C0_SCL_T,
I2C1_SDA_I,
I2C1_SDA_O,
I2C1_SDA_T,
I2C1_SCL_I,
I2C1_SCL_O,
I2C1_SCL_T,
PJTAG_TCK,
PJTAG_TMS,
PJTAG_TD_I,
PJTAG_TD_T,
PJTAG_TD_O,
SDIO0_CLK,
SDIO0_CLK_FB,
SDIO0_CMD_O,
SDIO0_CMD_I,
SDIO0_CMD_T,
SDIO0_DATA_I,
SDIO0_DATA_O,
SDIO0_DATA_T,
SDIO0_LED,
SDIO0_CDN,
SDIO0_WP,
SDIO0_BUSPOW,
SDIO0_BUSVOLT,
SDIO1_CLK,
SDIO1_CLK_FB,
SDIO1_CMD_O,
SDIO1_CMD_I,
SDIO1_CMD_T,
SDIO1_DATA_I,
SDIO1_DATA_O,
SDIO1_DATA_T,
SDIO1_LED,
SDIO1_CDN,
SDIO1_WP,
SDIO1_BUSPOW,
SDIO1_BUSVOLT,
SPI0_SCLK_I,
SPI0_SCLK_O,
SPI0_SCLK_T,
SPI0_MOSI_I,
SPI0_MOSI_O,
SPI0_MOSI_T,
SPI0_MISO_I,
SPI0_MISO_O,
SPI0_MISO_T,
SPI0_SS_I,
SPI0_SS_O,
SPI0_SS1_O,
SPI0_SS2_O,
SPI0_SS_T,
SPI1_SCLK_I,
SPI1_SCLK_O,
SPI1_SCLK_T,
SPI1_MOSI_I,
SPI1_MOSI_O,
SPI1_MOSI_T,
SPI1_MISO_I,
SPI1_MISO_O,
SPI1_MISO_T,
SPI1_SS_I,
SPI1_SS_O,
SPI1_SS1_O,
SPI1_SS2_O,
SPI1_SS_T,
UART0_DTRN,
UART0_RTSN,
UART0_TX,
UART0_CTSN,
UART0_DCDN,
UART0_DSRN,
UART0_RIN,
UART0_RX,
UART1_DTRN,
UART1_RTSN,
UART1_TX,
UART1_CTSN,
UART1_DCDN,
UART1_DSRN,
UART1_RIN,
UART1_RX,
TTC0_WAVE0_OUT,
TTC0_WAVE1_OUT,
TTC0_WAVE2_OUT,
TTC0_CLK0_IN,
TTC0_CLK1_IN,
TTC0_CLK2_IN,
TTC1_WAVE0_OUT,
TTC1_WAVE1_OUT,
TTC1_WAVE2_OUT,
TTC1_CLK0_IN,
TTC1_CLK1_IN,
TTC1_CLK2_IN,
WDT_CLK_IN,
WDT_RST_OUT,
TRACE_CLK,
TRACE_CTL,
TRACE_DATA,
USB0_PORT_INDCTL,
USB1_PORT_INDCTL,
USB0_VBUS_PWRSELECT,
USB1_VBUS_PWRSELECT,
USB0_VBUS_PWRFAULT,
USB1_VBUS_PWRFAULT,
SRAM_INTIN,
M_AXI_GP0_ARVALID,
M_AXI_GP0_AWVALID,
M_AXI_GP0_BREADY,
M_AXI_GP0_RREADY,
M_AXI_GP0_WLAST,
M_AXI_GP0_WVALID,
M_AXI_GP0_ARID,
M_AXI_GP0_AWID,
M_AXI_GP0_WID,
M_AXI_GP0_ARBURST,
M_AXI_GP0_ARLOCK,
M_AXI_GP0_ARSIZE,
M_AXI_GP0_AWBURST,
M_AXI_GP0_AWLOCK,
M_AXI_GP0_AWSIZE,
M_AXI_GP0_ARPROT,
M_AXI_GP0_AWPROT,
M_AXI_GP0_ARADDR,
M_AXI_GP0_AWADDR,
M_AXI_GP0_WDATA,
M_AXI_GP0_ARCACHE,
M_AXI_GP0_ARLEN,
M_AXI_GP0_ARQOS,
M_AXI_GP0_AWCACHE,
M_AXI_GP0_AWLEN,
M_AXI_GP0_AWQOS,
M_AXI_GP0_WSTRB,
M_AXI_GP0_ACLK,
M_AXI_GP0_ARREADY,
M_AXI_GP0_AWREADY,
M_AXI_GP0_BVALID,
M_AXI_GP0_RLAST,
M_AXI_GP0_RVALID,
M_AXI_GP0_WREADY,
M_AXI_GP0_BID,
M_AXI_GP0_RID,
M_AXI_GP0_BRESP,
M_AXI_GP0_RRESP,
M_AXI_GP0_RDATA,
M_AXI_GP1_ARVALID,
M_AXI_GP1_AWVALID,
M_AXI_GP1_BREADY,
M_AXI_GP1_RREADY,
M_AXI_GP1_WLAST,
M_AXI_GP1_WVALID,
M_AXI_GP1_ARID,
M_AXI_GP1_AWID,
M_AXI_GP1_WID,
M_AXI_GP1_ARBURST,
M_AXI_GP1_ARLOCK,
M_AXI_GP1_ARSIZE,
M_AXI_GP1_AWBURST,
M_AXI_GP1_AWLOCK,
M_AXI_GP1_AWSIZE,
M_AXI_GP1_ARPROT,
M_AXI_GP1_AWPROT,
M_AXI_GP1_ARADDR,
M_AXI_GP1_AWADDR,
M_AXI_GP1_WDATA,
M_AXI_GP1_ARCACHE,
M_AXI_GP1_ARLEN,
M_AXI_GP1_ARQOS,
M_AXI_GP1_AWCACHE,
M_AXI_GP1_AWLEN,
M_AXI_GP1_AWQOS,
M_AXI_GP1_WSTRB,
M_AXI_GP1_ACLK,
M_AXI_GP1_ARREADY,
M_AXI_GP1_AWREADY,
M_AXI_GP1_BVALID,
M_AXI_GP1_RLAST,
M_AXI_GP1_RVALID,
M_AXI_GP1_WREADY,
M_AXI_GP1_BID,
M_AXI_GP1_RID,
M_AXI_GP1_BRESP,
M_AXI_GP1_RRESP,
M_AXI_GP1_RDATA,
S_AXI_GP0_ARREADY,
S_AXI_GP0_AWREADY,
S_AXI_GP0_BVALID,
S_AXI_GP0_RLAST,
S_AXI_GP0_RVALID,
S_AXI_GP0_WREADY,
S_AXI_GP0_BRESP,
S_AXI_GP0_RRESP,
S_AXI_GP0_RDATA,
S_AXI_GP0_BID,
S_AXI_GP0_RID,
S_AXI_GP0_ACLK,
S_AXI_GP0_ARVALID,
S_AXI_GP0_AWVALID,
S_AXI_GP0_BREADY,
S_AXI_GP0_RREADY,
S_AXI_GP0_WLAST,
S_AXI_GP0_WVALID,
S_AXI_GP0_ARBURST,
S_AXI_GP0_ARLOCK,
S_AXI_GP0_ARSIZE,
S_AXI_GP0_AWBURST,
S_AXI_GP0_AWLOCK,
S_AXI_GP0_AWSIZE,
S_AXI_GP0_ARPROT,
S_AXI_GP0_AWPROT,
S_AXI_GP0_ARADDR,
S_AXI_GP0_AWADDR,
S_AXI_GP0_WDATA,
S_AXI_GP0_ARCACHE,
S_AXI_GP0_ARLEN,
S_AXI_GP0_ARQOS,
S_AXI_GP0_AWCACHE,
S_AXI_GP0_AWLEN,
S_AXI_GP0_AWQOS,
S_AXI_GP0_WSTRB,
S_AXI_GP0_ARID,
S_AXI_GP0_AWID,
S_AXI_GP0_WID,
S_AXI_GP1_ARREADY,
S_AXI_GP1_AWREADY,
S_AXI_GP1_BVALID,
S_AXI_GP1_RLAST,
S_AXI_GP1_RVALID,
S_AXI_GP1_WREADY,
S_AXI_GP1_BRESP,
S_AXI_GP1_RRESP,
S_AXI_GP1_RDATA,
S_AXI_GP1_BID,
S_AXI_GP1_RID,
S_AXI_GP1_ACLK,
S_AXI_GP1_ARVALID,
S_AXI_GP1_AWVALID,
S_AXI_GP1_BREADY,
S_AXI_GP1_RREADY,
S_AXI_GP1_WLAST,
S_AXI_GP1_WVALID,
S_AXI_GP1_ARBURST,
S_AXI_GP1_ARLOCK,
S_AXI_GP1_ARSIZE,
S_AXI_GP1_AWBURST,
S_AXI_GP1_AWLOCK,
S_AXI_GP1_AWSIZE,
S_AXI_GP1_ARPROT,
S_AXI_GP1_AWPROT,
S_AXI_GP1_ARADDR,
S_AXI_GP1_AWADDR,
S_AXI_GP1_WDATA,
S_AXI_GP1_ARCACHE,
S_AXI_GP1_ARLEN,
S_AXI_GP1_ARQOS,
S_AXI_GP1_AWCACHE,
S_AXI_GP1_AWLEN,
S_AXI_GP1_AWQOS,
S_AXI_GP1_WSTRB,
S_AXI_GP1_ARID,
S_AXI_GP1_AWID,
S_AXI_GP1_WID,
S_AXI_ACP_AWREADY,
S_AXI_ACP_ARREADY,
S_AXI_ACP_BVALID,
S_AXI_ACP_RLAST,
S_AXI_ACP_RVALID,
S_AXI_ACP_WREADY,
S_AXI_ACP_BRESP,
S_AXI_ACP_RRESP,
S_AXI_ACP_BID,
S_AXI_ACP_RID,
S_AXI_ACP_RDATA,
S_AXI_ACP_ACLK,
S_AXI_ACP_ARVALID,
S_AXI_ACP_AWVALID,
S_AXI_ACP_BREADY,
S_AXI_ACP_RREADY,
S_AXI_ACP_WLAST,
S_AXI_ACP_WVALID,
S_AXI_ACP_ARID,
S_AXI_ACP_ARPROT,
S_AXI_ACP_AWID,
S_AXI_ACP_AWPROT,
S_AXI_ACP_WID,
S_AXI_ACP_ARADDR,
S_AXI_ACP_AWADDR,
S_AXI_ACP_ARCACHE,
S_AXI_ACP_ARLEN,
S_AXI_ACP_ARQOS,
S_AXI_ACP_AWCACHE,
S_AXI_ACP_AWLEN,
S_AXI_ACP_AWQOS,
S_AXI_ACP_ARBURST,
S_AXI_ACP_ARLOCK,
S_AXI_ACP_ARSIZE,
S_AXI_ACP_AWBURST,
S_AXI_ACP_AWLOCK,
S_AXI_ACP_AWSIZE,
S_AXI_ACP_ARUSER,
S_AXI_ACP_AWUSER,
S_AXI_ACP_WDATA,
S_AXI_ACP_WSTRB,
S_AXI_HP0_ARREADY,
S_AXI_HP0_AWREADY,
S_AXI_HP0_BVALID,
S_AXI_HP0_RLAST,
S_AXI_HP0_RVALID,
S_AXI_HP0_WREADY,
S_AXI_HP0_BRESP,
S_AXI_HP0_RRESP,
S_AXI_HP0_BID,
S_AXI_HP0_RID,
S_AXI_HP0_RDATA,
S_AXI_HP0_RCOUNT,
S_AXI_HP0_WCOUNT,
S_AXI_HP0_RACOUNT,
S_AXI_HP0_WACOUNT,
S_AXI_HP0_ACLK,
S_AXI_HP0_ARVALID,
S_AXI_HP0_AWVALID,
S_AXI_HP0_BREADY,
S_AXI_HP0_RDISSUECAP1_EN,
S_AXI_HP0_RREADY,
S_AXI_HP0_WLAST,
S_AXI_HP0_WRISSUECAP1_EN,
S_AXI_HP0_WVALID,
S_AXI_HP0_ARBURST,
S_AXI_HP0_ARLOCK,
S_AXI_HP0_ARSIZE,
S_AXI_HP0_AWBURST,
S_AXI_HP0_AWLOCK,
S_AXI_HP0_AWSIZE,
S_AXI_HP0_ARPROT,
S_AXI_HP0_AWPROT,
S_AXI_HP0_ARADDR,
S_AXI_HP0_AWADDR,
S_AXI_HP0_ARCACHE,
S_AXI_HP0_ARLEN,
S_AXI_HP0_ARQOS,
S_AXI_HP0_AWCACHE,
S_AXI_HP0_AWLEN,
S_AXI_HP0_AWQOS,
S_AXI_HP0_ARID,
S_AXI_HP0_AWID,
S_AXI_HP0_WID,
S_AXI_HP0_WDATA,
S_AXI_HP0_WSTRB,
S_AXI_HP1_ARREADY,
S_AXI_HP1_AWREADY,
S_AXI_HP1_BVALID,
S_AXI_HP1_RLAST,
S_AXI_HP1_RVALID,
S_AXI_HP1_WREADY,
S_AXI_HP1_BRESP,
S_AXI_HP1_RRESP,
S_AXI_HP1_BID,
S_AXI_HP1_RID,
S_AXI_HP1_RDATA,
S_AXI_HP1_RCOUNT,
S_AXI_HP1_WCOUNT,
S_AXI_HP1_RACOUNT,
S_AXI_HP1_WACOUNT,
S_AXI_HP1_ACLK,
S_AXI_HP1_ARVALID,
S_AXI_HP1_AWVALID,
S_AXI_HP1_BREADY,
S_AXI_HP1_RDISSUECAP1_EN,
S_AXI_HP1_RREADY,
S_AXI_HP1_WLAST,
S_AXI_HP1_WRISSUECAP1_EN,
S_AXI_HP1_WVALID,
S_AXI_HP1_ARBURST,
S_AXI_HP1_ARLOCK,
S_AXI_HP1_ARSIZE,
S_AXI_HP1_AWBURST,
S_AXI_HP1_AWLOCK,
S_AXI_HP1_AWSIZE,
S_AXI_HP1_ARPROT,
S_AXI_HP1_AWPROT,
S_AXI_HP1_ARADDR,
S_AXI_HP1_AWADDR,
S_AXI_HP1_ARCACHE,
S_AXI_HP1_ARLEN,
S_AXI_HP1_ARQOS,
S_AXI_HP1_AWCACHE,
S_AXI_HP1_AWLEN,
S_AXI_HP1_AWQOS,
S_AXI_HP1_ARID,
S_AXI_HP1_AWID,
S_AXI_HP1_WID,
S_AXI_HP1_WDATA,
S_AXI_HP1_WSTRB,
S_AXI_HP2_ARREADY,
S_AXI_HP2_AWREADY,
S_AXI_HP2_BVALID,
S_AXI_HP2_RLAST,
S_AXI_HP2_RVALID,
S_AXI_HP2_WREADY,
S_AXI_HP2_BRESP,
S_AXI_HP2_RRESP,
S_AXI_HP2_BID,
S_AXI_HP2_RID,
S_AXI_HP2_RDATA,
S_AXI_HP2_RCOUNT,
S_AXI_HP2_WCOUNT,
S_AXI_HP2_RACOUNT,
S_AXI_HP2_WACOUNT,
S_AXI_HP2_ACLK,
S_AXI_HP2_ARVALID,
S_AXI_HP2_AWVALID,
S_AXI_HP2_BREADY,
S_AXI_HP2_RDISSUECAP1_EN,
S_AXI_HP2_RREADY,
S_AXI_HP2_WLAST,
S_AXI_HP2_WRISSUECAP1_EN,
S_AXI_HP2_WVALID,
S_AXI_HP2_ARBURST,
S_AXI_HP2_ARLOCK,
S_AXI_HP2_ARSIZE,
S_AXI_HP2_AWBURST,
S_AXI_HP2_AWLOCK,
S_AXI_HP2_AWSIZE,
S_AXI_HP2_ARPROT,
S_AXI_HP2_AWPROT,
S_AXI_HP2_ARADDR,
S_AXI_HP2_AWADDR,
S_AXI_HP2_ARCACHE,
S_AXI_HP2_ARLEN,
S_AXI_HP2_ARQOS,
S_AXI_HP2_AWCACHE,
S_AXI_HP2_AWLEN,
S_AXI_HP2_AWQOS,
S_AXI_HP2_ARID,
S_AXI_HP2_AWID,
S_AXI_HP2_WID,
S_AXI_HP2_WDATA,
S_AXI_HP2_WSTRB,
S_AXI_HP3_ARREADY,
S_AXI_HP3_AWREADY,
S_AXI_HP3_BVALID,
S_AXI_HP3_RLAST,
S_AXI_HP3_RVALID,
S_AXI_HP3_WREADY,
S_AXI_HP3_BRESP,
S_AXI_HP3_RRESP,
S_AXI_HP3_BID,
S_AXI_HP3_RID,
S_AXI_HP3_RDATA,
S_AXI_HP3_RCOUNT,
S_AXI_HP3_WCOUNT,
S_AXI_HP3_RACOUNT,
S_AXI_HP3_WACOUNT,
S_AXI_HP3_ACLK,
S_AXI_HP3_ARVALID,
S_AXI_HP3_AWVALID,
S_AXI_HP3_BREADY,
S_AXI_HP3_RDISSUECAP1_EN,
S_AXI_HP3_RREADY,
S_AXI_HP3_WLAST,
S_AXI_HP3_WRISSUECAP1_EN,
S_AXI_HP3_WVALID,
S_AXI_HP3_ARBURST,
S_AXI_HP3_ARLOCK,
S_AXI_HP3_ARSIZE,
S_AXI_HP3_AWBURST,
S_AXI_HP3_AWLOCK,
S_AXI_HP3_AWSIZE,
S_AXI_HP3_ARPROT,
S_AXI_HP3_AWPROT,
S_AXI_HP3_ARADDR,
S_AXI_HP3_AWADDR,
S_AXI_HP3_ARCACHE,
S_AXI_HP3_ARLEN,
S_AXI_HP3_ARQOS,
S_AXI_HP3_AWCACHE,
S_AXI_HP3_AWLEN,
S_AXI_HP3_AWQOS,
S_AXI_HP3_ARID,
S_AXI_HP3_AWID,
S_AXI_HP3_WID,
S_AXI_HP3_WDATA,
S_AXI_HP3_WSTRB,
DMA0_DATYPE,
DMA0_DAVALID,
DMA0_DRREADY,
DMA0_ACLK,
DMA0_DAREADY,
DMA0_DRLAST,
DMA0_DRVALID,
DMA0_DRTYPE,
DMA1_DATYPE,
DMA1_DAVALID,
DMA1_DRREADY,
DMA1_ACLK,
DMA1_DAREADY,
DMA1_DRLAST,
DMA1_DRVALID,
DMA1_DRTYPE,
DMA2_DATYPE,
DMA2_DAVALID,
DMA2_DRREADY,
DMA2_ACLK,
DMA2_DAREADY,
DMA2_DRLAST,
DMA2_DRVALID,
DMA3_DRVALID,
DMA3_DATYPE,
DMA3_DAVALID,
DMA3_DRREADY,
DMA3_ACLK,
DMA3_DAREADY,
DMA3_DRLAST,
DMA2_DRTYPE,
DMA3_DRTYPE,
FTMD_TRACEIN_DATA,
FTMD_TRACEIN_VALID,
FTMD_TRACEIN_CLK,
FTMD_TRACEIN_ATID,
FTMT_F2P_TRIG,
FTMT_F2P_TRIGACK,
FTMT_F2P_DEBUG,
FTMT_P2F_TRIGACK,
FTMT_P2F_TRIG,
FTMT_P2F_DEBUG,
FCLK_CLK3,
FCLK_CLK2,
FCLK_CLK1,
FCLK_CLK0,
FCLK_CLKTRIG3_N,
FCLK_CLKTRIG2_N,
FCLK_CLKTRIG1_N,
FCLK_CLKTRIG0_N,
FCLK_RESET3_N,
FCLK_RESET2_N,
FCLK_RESET1_N,
FCLK_RESET0_N,
FPGA_IDLE_N,
DDR_ARB,
IRQ_F2P,
Core0_nFIQ,
Core0_nIRQ,
Core1_nFIQ,
Core1_nIRQ,
EVENT_EVENTO,
EVENT_STANDBYWFE,
EVENT_STANDBYWFI,
EVENT_EVENTI,
MIO,
DDR_Clk,
DDR_Clk_n,
DDR_CKE,
DDR_CS_n,
DDR_RAS_n,
DDR_CAS_n,
DDR_WEB,
DDR_BankAddr,
DDR_Addr,
DDR_ODT,
DDR_DRSTB,
DDR_DQ,
DDR_DM,
DDR_DQS,
DDR_DQS_n,
DDR_VRN,
DDR_VRP,
PS_SRSTB,
PS_CLK,
PS_PORB,
IRQ_P2F_DMAC_ABORT,
IRQ_P2F_DMAC0,
IRQ_P2F_DMAC1,
IRQ_P2F_DMAC2,
IRQ_P2F_DMAC3,
IRQ_P2F_DMAC4,
IRQ_P2F_DMAC5,
IRQ_P2F_DMAC6,
IRQ_P2F_DMAC7,
IRQ_P2F_SMC,
IRQ_P2F_QSPI,
IRQ_P2F_CTI,
IRQ_P2F_GPIO,
IRQ_P2F_USB0,
IRQ_P2F_ENET0,
IRQ_P2F_ENET_WAKE0,
IRQ_P2F_SDIO0,
IRQ_P2F_I2C0,
IRQ_P2F_SPI0,
IRQ_P2F_UART0,
IRQ_P2F_CAN0,
IRQ_P2F_USB1,
IRQ_P2F_ENET1,
IRQ_P2F_ENET_WAKE1,
IRQ_P2F_SDIO1,
IRQ_P2F_I2C1,
IRQ_P2F_SPI1,
IRQ_P2F_UART1,
IRQ_P2F_CAN1
);
/* parameters for gen_clk */
parameter C_FCLK_CLK0_FREQ = 50;
parameter C_FCLK_CLK1_FREQ = 50;
parameter C_FCLK_CLK3_FREQ = 50;
parameter C_FCLK_CLK2_FREQ = 50;
parameter C_HIGH_OCM_EN = 0;
/* parameters for HP ports */
parameter C_USE_S_AXI_HP0 = 0;
parameter C_USE_S_AXI_HP1 = 0;
parameter C_USE_S_AXI_HP2 = 0;
parameter C_USE_S_AXI_HP3 = 0;
parameter C_S_AXI_HP0_DATA_WIDTH = 32;
parameter C_S_AXI_HP1_DATA_WIDTH = 32;
parameter C_S_AXI_HP2_DATA_WIDTH = 32;
parameter C_S_AXI_HP3_DATA_WIDTH = 32;
parameter C_M_AXI_GP0_THREAD_ID_WIDTH = 12;
parameter C_M_AXI_GP1_THREAD_ID_WIDTH = 12;
parameter C_M_AXI_GP0_ENABLE_STATIC_REMAP = 0;
parameter C_M_AXI_GP1_ENABLE_STATIC_REMAP = 0;
/* Do we need these
parameter C_S_AXI_HP0_ENABLE_HIGHOCM = 0;
parameter C_S_AXI_HP1_ENABLE_HIGHOCM = 0;
parameter C_S_AXI_HP2_ENABLE_HIGHOCM = 0;
parameter C_S_AXI_HP3_ENABLE_HIGHOCM = 0; */
parameter C_S_AXI_HP0_BASEADDR = 32'h0000_0000;
parameter C_S_AXI_HP1_BASEADDR = 32'h0000_0000;
parameter C_S_AXI_HP2_BASEADDR = 32'h0000_0000;
parameter C_S_AXI_HP3_BASEADDR = 32'h0000_0000;
parameter C_S_AXI_HP0_HIGHADDR = 32'hFFFF_FFFF;
parameter C_S_AXI_HP1_HIGHADDR = 32'hFFFF_FFFF;
parameter C_S_AXI_HP2_HIGHADDR = 32'hFFFF_FFFF;
parameter C_S_AXI_HP3_HIGHADDR = 32'hFFFF_FFFF;
/* parameters for GP and ACP ports */
parameter C_USE_M_AXI_GP0 = 0;
parameter C_USE_M_AXI_GP1 = 0;
parameter C_USE_S_AXI_GP0 = 1;
parameter C_USE_S_AXI_GP1 = 1;
/* Do we need this?
parameter C_M_AXI_GP0_ENABLE_HIGHOCM = 0;
parameter C_M_AXI_GP1_ENABLE_HIGHOCM = 0;
parameter C_S_AXI_GP0_ENABLE_HIGHOCM = 0;
parameter C_S_AXI_GP1_ENABLE_HIGHOCM = 0;
parameter C_S_AXI_ACP_ENABLE_HIGHOCM = 0;*/
parameter C_S_AXI_GP0_BASEADDR = 32'h0000_0000;
parameter C_S_AXI_GP1_BASEADDR = 32'h0000_0000;
parameter C_S_AXI_GP0_HIGHADDR = 32'hFFFF_FFFF;
parameter C_S_AXI_GP1_HIGHADDR = 32'hFFFF_FFFF;
parameter C_USE_S_AXI_ACP = 1;
parameter C_S_AXI_ACP_BASEADDR = 32'h0000_0000;
parameter C_S_AXI_ACP_HIGHADDR = 32'hFFFF_FFFF;
`include "processing_system7_bfm_v2_0_local_params.v"
output CAN0_PHY_TX;
input CAN0_PHY_RX;
output CAN1_PHY_TX;
input CAN1_PHY_RX;
output ENET0_GMII_TX_EN;
output ENET0_GMII_TX_ER;
output ENET0_MDIO_MDC;
output ENET0_MDIO_O;
output ENET0_MDIO_T;
output ENET0_PTP_DELAY_REQ_RX;
output ENET0_PTP_DELAY_REQ_TX;
output ENET0_PTP_PDELAY_REQ_RX;
output ENET0_PTP_PDELAY_REQ_TX;
output ENET0_PTP_PDELAY_RESP_RX;
output ENET0_PTP_PDELAY_RESP_TX;
output ENET0_PTP_SYNC_FRAME_RX;
output ENET0_PTP_SYNC_FRAME_TX;
output ENET0_SOF_RX;
output ENET0_SOF_TX;
output [7:0] ENET0_GMII_TXD;
input ENET0_GMII_COL;
input ENET0_GMII_CRS;
input ENET0_EXT_INTIN;
input ENET0_GMII_RX_CLK;
input ENET0_GMII_RX_DV;
input ENET0_GMII_RX_ER;
input ENET0_GMII_TX_CLK;
input ENET0_MDIO_I;
input [7:0] ENET0_GMII_RXD;
output ENET1_GMII_TX_EN;
output ENET1_GMII_TX_ER;
output ENET1_MDIO_MDC;
output ENET1_MDIO_O;
output ENET1_MDIO_T;
output ENET1_PTP_DELAY_REQ_RX;
output ENET1_PTP_DELAY_REQ_TX;
output ENET1_PTP_PDELAY_REQ_RX;
output ENET1_PTP_PDELAY_REQ_TX;
output ENET1_PTP_PDELAY_RESP_RX;
output ENET1_PTP_PDELAY_RESP_TX;
output ENET1_PTP_SYNC_FRAME_RX;
output ENET1_PTP_SYNC_FRAME_TX;
output ENET1_SOF_RX;
output ENET1_SOF_TX;
output [7:0] ENET1_GMII_TXD;
input ENET1_GMII_COL;
input ENET1_GMII_CRS;
input ENET1_EXT_INTIN;
input ENET1_GMII_RX_CLK;
input ENET1_GMII_RX_DV;
input ENET1_GMII_RX_ER;
input ENET1_GMII_TX_CLK;
input ENET1_MDIO_I;
input [7:0] ENET1_GMII_RXD;
input [63:0] GPIO_I;
output [63:0] GPIO_O;
output [63:0] GPIO_T;
input I2C0_SDA_I;
output I2C0_SDA_O;
output I2C0_SDA_T;
input I2C0_SCL_I;
output I2C0_SCL_O;
output I2C0_SCL_T;
input I2C1_SDA_I;
output I2C1_SDA_O;
output I2C1_SDA_T;
input I2C1_SCL_I;
output I2C1_SCL_O;
output I2C1_SCL_T;
input PJTAG_TCK;
input PJTAG_TMS;
input PJTAG_TD_I;
output PJTAG_TD_T;
output PJTAG_TD_O;
output SDIO0_CLK;
input SDIO0_CLK_FB;
output SDIO0_CMD_O;
input SDIO0_CMD_I;
output SDIO0_CMD_T;
input [3:0] SDIO0_DATA_I;
output [3:0] SDIO0_DATA_O;
output [3:0] SDIO0_DATA_T;
output SDIO0_LED;
input SDIO0_CDN;
input SDIO0_WP;
output SDIO0_BUSPOW;
output [2:0] SDIO0_BUSVOLT;
output SDIO1_CLK;
input SDIO1_CLK_FB;
output SDIO1_CMD_O;
input SDIO1_CMD_I;
output SDIO1_CMD_T;
input [3:0] SDIO1_DATA_I;
output [3:0] SDIO1_DATA_O;
output [3:0] SDIO1_DATA_T;
output SDIO1_LED;
input SDIO1_CDN;
input SDIO1_WP;
output SDIO1_BUSPOW;
output [2:0] SDIO1_BUSVOLT;
input SPI0_SCLK_I;
output SPI0_SCLK_O;
output SPI0_SCLK_T;
input SPI0_MOSI_I;
output SPI0_MOSI_O;
output SPI0_MOSI_T;
input SPI0_MISO_I;
output SPI0_MISO_O;
output SPI0_MISO_T;
input SPI0_SS_I;
output SPI0_SS_O;
output SPI0_SS1_O;
output SPI0_SS2_O;
output SPI0_SS_T;
input SPI1_SCLK_I;
output SPI1_SCLK_O;
output SPI1_SCLK_T;
input SPI1_MOSI_I;
output SPI1_MOSI_O;
output SPI1_MOSI_T;
input SPI1_MISO_I;
output SPI1_MISO_O;
output SPI1_MISO_T;
input SPI1_SS_I;
output SPI1_SS_O;
output SPI1_SS1_O;
output SPI1_SS2_O;
output SPI1_SS_T;
output UART0_DTRN;
output UART0_RTSN;
output UART0_TX;
input UART0_CTSN;
input UART0_DCDN;
input UART0_DSRN;
input UART0_RIN;
input UART0_RX;
output UART1_DTRN;
output UART1_RTSN;
output UART1_TX;
input UART1_CTSN;
input UART1_DCDN;
input UART1_DSRN;
input UART1_RIN;
input UART1_RX;
output TTC0_WAVE0_OUT;
output TTC0_WAVE1_OUT;
output TTC0_WAVE2_OUT;
input TTC0_CLK0_IN;
input TTC0_CLK1_IN;
input TTC0_CLK2_IN;
output TTC1_WAVE0_OUT;
output TTC1_WAVE1_OUT;
output TTC1_WAVE2_OUT;
input TTC1_CLK0_IN;
input TTC1_CLK1_IN;
input TTC1_CLK2_IN;
input WDT_CLK_IN;
output WDT_RST_OUT;
input TRACE_CLK;
output TRACE_CTL;
output [31:0] TRACE_DATA;
output [1:0] USB0_PORT_INDCTL;
output [1:0] USB1_PORT_INDCTL;
output USB0_VBUS_PWRSELECT;
output USB1_VBUS_PWRSELECT;
input USB0_VBUS_PWRFAULT;
input USB1_VBUS_PWRFAULT;
input SRAM_INTIN;
output M_AXI_GP0_ARVALID;
output M_AXI_GP0_AWVALID;
output M_AXI_GP0_BREADY;
output M_AXI_GP0_RREADY;
output M_AXI_GP0_WLAST;
output M_AXI_GP0_WVALID;
output [C_M_AXI_GP0_THREAD_ID_WIDTH-1:0] M_AXI_GP0_ARID;
output [C_M_AXI_GP0_THREAD_ID_WIDTH-1:0] M_AXI_GP0_AWID;
output [C_M_AXI_GP0_THREAD_ID_WIDTH-1:0] M_AXI_GP0_WID;
output [1:0] M_AXI_GP0_ARBURST;
output [1:0] M_AXI_GP0_ARLOCK;
output [2:0] M_AXI_GP0_ARSIZE;
output [1:0] M_AXI_GP0_AWBURST;
output [1:0] M_AXI_GP0_AWLOCK;
output [2:0] M_AXI_GP0_AWSIZE;
output [2:0] M_AXI_GP0_ARPROT;
output [2:0] M_AXI_GP0_AWPROT;
output [31:0] M_AXI_GP0_ARADDR;
output [31:0] M_AXI_GP0_AWADDR;
output [31:0] M_AXI_GP0_WDATA;
output [3:0] M_AXI_GP0_ARCACHE;
output [3:0] M_AXI_GP0_ARLEN;
output [3:0] M_AXI_GP0_ARQOS;
output [3:0] M_AXI_GP0_AWCACHE;
output [3:0] M_AXI_GP0_AWLEN;
output [3:0] M_AXI_GP0_AWQOS;
output [3:0] M_AXI_GP0_WSTRB;
input M_AXI_GP0_ACLK;
input M_AXI_GP0_ARREADY;
input M_AXI_GP0_AWREADY;
input M_AXI_GP0_BVALID;
input M_AXI_GP0_RLAST;
input M_AXI_GP0_RVALID;
input M_AXI_GP0_WREADY;
input [C_M_AXI_GP0_THREAD_ID_WIDTH-1:0] M_AXI_GP0_BID;
input [C_M_AXI_GP0_THREAD_ID_WIDTH-1:0] M_AXI_GP0_RID;
input [1:0] M_AXI_GP0_BRESP;
input [1:0] M_AXI_GP0_RRESP;
input [31:0] M_AXI_GP0_RDATA;
output M_AXI_GP1_ARVALID;
output M_AXI_GP1_AWVALID;
output M_AXI_GP1_BREADY;
output M_AXI_GP1_RREADY;
output M_AXI_GP1_WLAST;
output M_AXI_GP1_WVALID;
output [C_M_AXI_GP1_THREAD_ID_WIDTH-1:0] M_AXI_GP1_ARID;
output [C_M_AXI_GP1_THREAD_ID_WIDTH-1:0] M_AXI_GP1_AWID;
output [C_M_AXI_GP1_THREAD_ID_WIDTH-1:0] M_AXI_GP1_WID;
output [1:0] M_AXI_GP1_ARBURST;
output [1:0] M_AXI_GP1_ARLOCK;
output [2:0] M_AXI_GP1_ARSIZE;
output [1:0] M_AXI_GP1_AWBURST;
output [1:0] M_AXI_GP1_AWLOCK;
output [2:0] M_AXI_GP1_AWSIZE;
output [2:0] M_AXI_GP1_ARPROT;
output [2:0] M_AXI_GP1_AWPROT;
output [31:0] M_AXI_GP1_ARADDR;
output [31:0] M_AXI_GP1_AWADDR;
output [31:0] M_AXI_GP1_WDATA;
output [3:0] M_AXI_GP1_ARCACHE;
output [3:0] M_AXI_GP1_ARLEN;
output [3:0] M_AXI_GP1_ARQOS;
output [3:0] M_AXI_GP1_AWCACHE;
output [3:0] M_AXI_GP1_AWLEN;
output [3:0] M_AXI_GP1_AWQOS;
output [3:0] M_AXI_GP1_WSTRB;
input M_AXI_GP1_ACLK;
input M_AXI_GP1_ARREADY;
input M_AXI_GP1_AWREADY;
input M_AXI_GP1_BVALID;
input M_AXI_GP1_RLAST;
input M_AXI_GP1_RVALID;
input M_AXI_GP1_WREADY;
input [C_M_AXI_GP1_THREAD_ID_WIDTH-1:0] M_AXI_GP1_BID;
input [C_M_AXI_GP1_THREAD_ID_WIDTH-1:0] M_AXI_GP1_RID;
input [1:0] M_AXI_GP1_BRESP;
input [1:0] M_AXI_GP1_RRESP;
input [31:0] M_AXI_GP1_RDATA;
output S_AXI_GP0_ARREADY;
output S_AXI_GP0_AWREADY;
output S_AXI_GP0_BVALID;
output S_AXI_GP0_RLAST;
output S_AXI_GP0_RVALID;
output S_AXI_GP0_WREADY;
output [1:0] S_AXI_GP0_BRESP;
output [1:0] S_AXI_GP0_RRESP;
output [31:0] S_AXI_GP0_RDATA;
output [5:0] S_AXI_GP0_BID;
output [5:0] S_AXI_GP0_RID;
input S_AXI_GP0_ACLK;
input S_AXI_GP0_ARVALID;
input S_AXI_GP0_AWVALID;
input S_AXI_GP0_BREADY;
input S_AXI_GP0_RREADY;
input S_AXI_GP0_WLAST;
input S_AXI_GP0_WVALID;
input [1:0] S_AXI_GP0_ARBURST;
input [1:0] S_AXI_GP0_ARLOCK;
input [2:0] S_AXI_GP0_ARSIZE;
input [1:0] S_AXI_GP0_AWBURST;
input [1:0] S_AXI_GP0_AWLOCK;
input [2:0] S_AXI_GP0_AWSIZE;
input [2:0] S_AXI_GP0_ARPROT;
input [2:0] S_AXI_GP0_AWPROT;
input [31:0] S_AXI_GP0_ARADDR;
input [31:0] S_AXI_GP0_AWADDR;
input [31:0] S_AXI_GP0_WDATA;
input [3:0] S_AXI_GP0_ARCACHE;
input [3:0] S_AXI_GP0_ARLEN;
input [3:0] S_AXI_GP0_ARQOS;
input [3:0] S_AXI_GP0_AWCACHE;
input [3:0] S_AXI_GP0_AWLEN;
input [3:0] S_AXI_GP0_AWQOS;
input [3:0] S_AXI_GP0_WSTRB;
input [5:0] S_AXI_GP0_ARID;
input [5:0] S_AXI_GP0_AWID;
input [5:0] S_AXI_GP0_WID;
output S_AXI_GP1_ARREADY;
output S_AXI_GP1_AWREADY;
output S_AXI_GP1_BVALID;
output S_AXI_GP1_RLAST;
output S_AXI_GP1_RVALID;
output S_AXI_GP1_WREADY;
output [1:0] S_AXI_GP1_BRESP;
output [1:0] S_AXI_GP1_RRESP;
output [31:0] S_AXI_GP1_RDATA;
output [5:0] S_AXI_GP1_BID;
output [5:0] S_AXI_GP1_RID;
input S_AXI_GP1_ACLK;
input S_AXI_GP1_ARVALID;
input S_AXI_GP1_AWVALID;
input S_AXI_GP1_BREADY;
input S_AXI_GP1_RREADY;
input S_AXI_GP1_WLAST;
input S_AXI_GP1_WVALID;
input [1:0] S_AXI_GP1_ARBURST;
input [1:0] S_AXI_GP1_ARLOCK;
input [2:0] S_AXI_GP1_ARSIZE;
input [1:0] S_AXI_GP1_AWBURST;
input [1:0] S_AXI_GP1_AWLOCK;
input [2:0] S_AXI_GP1_AWSIZE;
input [2:0] S_AXI_GP1_ARPROT;
input [2:0] S_AXI_GP1_AWPROT;
input [31:0] S_AXI_GP1_ARADDR;
input [31:0] S_AXI_GP1_AWADDR;
input [31:0] S_AXI_GP1_WDATA;
input [3:0] S_AXI_GP1_ARCACHE;
input [3:0] S_AXI_GP1_ARLEN;
input [3:0] S_AXI_GP1_ARQOS;
input [3:0] S_AXI_GP1_AWCACHE;
input [3:0] S_AXI_GP1_AWLEN;
input [3:0] S_AXI_GP1_AWQOS;
input [3:0] S_AXI_GP1_WSTRB;
input [5:0] S_AXI_GP1_ARID;
input [5:0] S_AXI_GP1_AWID;
input [5:0] S_AXI_GP1_WID;
output S_AXI_ACP_AWREADY;
output S_AXI_ACP_ARREADY;
output S_AXI_ACP_BVALID;
output S_AXI_ACP_RLAST;
output S_AXI_ACP_RVALID;
output S_AXI_ACP_WREADY;
output [1:0] S_AXI_ACP_BRESP;
output [1:0] S_AXI_ACP_RRESP;
output [2:0] S_AXI_ACP_BID;
output [2:0] S_AXI_ACP_RID;
output [63:0] S_AXI_ACP_RDATA;
input S_AXI_ACP_ACLK;
input S_AXI_ACP_ARVALID;
input S_AXI_ACP_AWVALID;
input S_AXI_ACP_BREADY;
input S_AXI_ACP_RREADY;
input S_AXI_ACP_WLAST;
input S_AXI_ACP_WVALID;
input [2:0] S_AXI_ACP_ARID;
input [2:0] S_AXI_ACP_ARPROT;
input [2:0] S_AXI_ACP_AWID;
input [2:0] S_AXI_ACP_AWPROT;
input [2:0] S_AXI_ACP_WID;
input [31:0] S_AXI_ACP_ARADDR;
input [31:0] S_AXI_ACP_AWADDR;
input [3:0] S_AXI_ACP_ARCACHE;
input [3:0] S_AXI_ACP_ARLEN;
input [3:0] S_AXI_ACP_ARQOS;
input [3:0] S_AXI_ACP_AWCACHE;
input [3:0] S_AXI_ACP_AWLEN;
input [3:0] S_AXI_ACP_AWQOS;
input [1:0] S_AXI_ACP_ARBURST;
input [1:0] S_AXI_ACP_ARLOCK;
input [2:0] S_AXI_ACP_ARSIZE;
input [1:0] S_AXI_ACP_AWBURST;
input [1:0] S_AXI_ACP_AWLOCK;
input [2:0] S_AXI_ACP_AWSIZE;
input [4:0] S_AXI_ACP_ARUSER;
input [4:0] S_AXI_ACP_AWUSER;
input [63:0] S_AXI_ACP_WDATA;
input [7:0] S_AXI_ACP_WSTRB;
output S_AXI_HP0_ARREADY;
output S_AXI_HP0_AWREADY;
output S_AXI_HP0_BVALID;
output S_AXI_HP0_RLAST;
output S_AXI_HP0_RVALID;
output S_AXI_HP0_WREADY;
output [1:0] S_AXI_HP0_BRESP;
output [1:0] S_AXI_HP0_RRESP;
output [5:0] S_AXI_HP0_BID;
output [5:0] S_AXI_HP0_RID;
output [C_S_AXI_HP0_DATA_WIDTH-1:0] S_AXI_HP0_RDATA;
output [7:0] S_AXI_HP0_RCOUNT;
output [7:0] S_AXI_HP0_WCOUNT;
output [2:0] S_AXI_HP0_RACOUNT;
output [5:0] S_AXI_HP0_WACOUNT;
input S_AXI_HP0_ACLK;
input S_AXI_HP0_ARVALID;
input S_AXI_HP0_AWVALID;
input S_AXI_HP0_BREADY;
input S_AXI_HP0_RDISSUECAP1_EN;
input S_AXI_HP0_RREADY;
input S_AXI_HP0_WLAST;
input S_AXI_HP0_WRISSUECAP1_EN;
input S_AXI_HP0_WVALID;
input [1:0] S_AXI_HP0_ARBURST;
input [1:0] S_AXI_HP0_ARLOCK;
input [2:0] S_AXI_HP0_ARSIZE;
input [1:0] S_AXI_HP0_AWBURST;
input [1:0] S_AXI_HP0_AWLOCK;
input [2:0] S_AXI_HP0_AWSIZE;
input [2:0] S_AXI_HP0_ARPROT;
input [2:0] S_AXI_HP0_AWPROT;
input [31:0] S_AXI_HP0_ARADDR;
input [31:0] S_AXI_HP0_AWADDR;
input [3:0] S_AXI_HP0_ARCACHE;
input [3:0] S_AXI_HP0_ARLEN;
input [3:0] S_AXI_HP0_ARQOS;
input [3:0] S_AXI_HP0_AWCACHE;
input [3:0] S_AXI_HP0_AWLEN;
input [3:0] S_AXI_HP0_AWQOS;
input [5:0] S_AXI_HP0_ARID;
input [5:0] S_AXI_HP0_AWID;
input [5:0] S_AXI_HP0_WID;
input [C_S_AXI_HP0_DATA_WIDTH-1:0] S_AXI_HP0_WDATA;
input [C_S_AXI_HP0_DATA_WIDTH/8-1:0] S_AXI_HP0_WSTRB;
output S_AXI_HP1_ARREADY;
output S_AXI_HP1_AWREADY;
output S_AXI_HP1_BVALID;
output S_AXI_HP1_RLAST;
output S_AXI_HP1_RVALID;
output S_AXI_HP1_WREADY;
output [1:0] S_AXI_HP1_BRESP;
output [1:0] S_AXI_HP1_RRESP;
output [5:0] S_AXI_HP1_BID;
output [5:0] S_AXI_HP1_RID;
output [C_S_AXI_HP1_DATA_WIDTH-1:0] S_AXI_HP1_RDATA;
output [7:0] S_AXI_HP1_RCOUNT;
output [7:0] S_AXI_HP1_WCOUNT;
output [2:0] S_AXI_HP1_RACOUNT;
output [5:0] S_AXI_HP1_WACOUNT;
input S_AXI_HP1_ACLK;
input S_AXI_HP1_ARVALID;
input S_AXI_HP1_AWVALID;
input S_AXI_HP1_BREADY;
input S_AXI_HP1_RDISSUECAP1_EN;
input S_AXI_HP1_RREADY;
input S_AXI_HP1_WLAST;
input S_AXI_HP1_WRISSUECAP1_EN;
input S_AXI_HP1_WVALID;
input [1:0] S_AXI_HP1_ARBURST;
input [1:0] S_AXI_HP1_ARLOCK;
input [2:0] S_AXI_HP1_ARSIZE;
input [1:0] S_AXI_HP1_AWBURST;
input [1:0] S_AXI_HP1_AWLOCK;
input [2:0] S_AXI_HP1_AWSIZE;
input [2:0] S_AXI_HP1_ARPROT;
input [2:0] S_AXI_HP1_AWPROT;
input [31:0] S_AXI_HP1_ARADDR;
input [31:0] S_AXI_HP1_AWADDR;
input [3:0] S_AXI_HP1_ARCACHE;
input [3:0] S_AXI_HP1_ARLEN;
input [3:0] S_AXI_HP1_ARQOS;
input [3:0] S_AXI_HP1_AWCACHE;
input [3:0] S_AXI_HP1_AWLEN;
input [3:0] S_AXI_HP1_AWQOS;
input [5:0] S_AXI_HP1_ARID;
input [5:0] S_AXI_HP1_AWID;
input [5:0] S_AXI_HP1_WID;
input [C_S_AXI_HP1_DATA_WIDTH-1:0] S_AXI_HP1_WDATA;
input [C_S_AXI_HP1_DATA_WIDTH/8-1:0] S_AXI_HP1_WSTRB;
output S_AXI_HP2_ARREADY;
output S_AXI_HP2_AWREADY;
output S_AXI_HP2_BVALID;
output S_AXI_HP2_RLAST;
output S_AXI_HP2_RVALID;
output S_AXI_HP2_WREADY;
output [1:0] S_AXI_HP2_BRESP;
output [1:0] S_AXI_HP2_RRESP;
output [5:0] S_AXI_HP2_BID;
output [5:0] S_AXI_HP2_RID;
output [C_S_AXI_HP2_DATA_WIDTH-1:0] S_AXI_HP2_RDATA;
output [7:0] S_AXI_HP2_RCOUNT;
output [7:0] S_AXI_HP2_WCOUNT;
output [2:0] S_AXI_HP2_RACOUNT;
output [5:0] S_AXI_HP2_WACOUNT;
input S_AXI_HP2_ACLK;
input S_AXI_HP2_ARVALID;
input S_AXI_HP2_AWVALID;
input S_AXI_HP2_BREADY;
input S_AXI_HP2_RDISSUECAP1_EN;
input S_AXI_HP2_RREADY;
input S_AXI_HP2_WLAST;
input S_AXI_HP2_WRISSUECAP1_EN;
input S_AXI_HP2_WVALID;
input [1:0] S_AXI_HP2_ARBURST;
input [1:0] S_AXI_HP2_ARLOCK;
input [2:0] S_AXI_HP2_ARSIZE;
input [1:0] S_AXI_HP2_AWBURST;
input [1:0] S_AXI_HP2_AWLOCK;
input [2:0] S_AXI_HP2_AWSIZE;
input [2:0] S_AXI_HP2_ARPROT;
input [2:0] S_AXI_HP2_AWPROT;
input [31:0] S_AXI_HP2_ARADDR;
input [31:0] S_AXI_HP2_AWADDR;
input [3:0] S_AXI_HP2_ARCACHE;
input [3:0] S_AXI_HP2_ARLEN;
input [3:0] S_AXI_HP2_ARQOS;
input [3:0] S_AXI_HP2_AWCACHE;
input [3:0] S_AXI_HP2_AWLEN;
input [3:0] S_AXI_HP2_AWQOS;
input [5:0] S_AXI_HP2_ARID;
input [5:0] S_AXI_HP2_AWID;
input [5:0] S_AXI_HP2_WID;
input [C_S_AXI_HP2_DATA_WIDTH-1:0] S_AXI_HP2_WDATA;
input [C_S_AXI_HP2_DATA_WIDTH/8-1:0] S_AXI_HP2_WSTRB;
output S_AXI_HP3_ARREADY;
output S_AXI_HP3_AWREADY;
output S_AXI_HP3_BVALID;
output S_AXI_HP3_RLAST;
output S_AXI_HP3_RVALID;
output S_AXI_HP3_WREADY;
output [1:0] S_AXI_HP3_BRESP;
output [1:0] S_AXI_HP3_RRESP;
output [5:0] S_AXI_HP3_BID;
output [5:0] S_AXI_HP3_RID;
output [C_S_AXI_HP3_DATA_WIDTH-1:0] S_AXI_HP3_RDATA;
output [7:0] S_AXI_HP3_RCOUNT;
output [7:0] S_AXI_HP3_WCOUNT;
output [2:0] S_AXI_HP3_RACOUNT;
output [5:0] S_AXI_HP3_WACOUNT;
input S_AXI_HP3_ACLK;
input S_AXI_HP3_ARVALID;
input S_AXI_HP3_AWVALID;
input S_AXI_HP3_BREADY;
input S_AXI_HP3_RDISSUECAP1_EN;
input S_AXI_HP3_RREADY;
input S_AXI_HP3_WLAST;
input S_AXI_HP3_WRISSUECAP1_EN;
input S_AXI_HP3_WVALID;
input [1:0] S_AXI_HP3_ARBURST;
input [1:0] S_AXI_HP3_ARLOCK;
input [2:0] S_AXI_HP3_ARSIZE;
input [1:0] S_AXI_HP3_AWBURST;
input [1:0] S_AXI_HP3_AWLOCK;
input [2:0] S_AXI_HP3_AWSIZE;
input [2:0] S_AXI_HP3_ARPROT;
input [2:0] S_AXI_HP3_AWPROT;
input [31:0] S_AXI_HP3_ARADDR;
input [31:0] S_AXI_HP3_AWADDR;
input [3:0] S_AXI_HP3_ARCACHE;
input [3:0] S_AXI_HP3_ARLEN;
input [3:0] S_AXI_HP3_ARQOS;
input [3:0] S_AXI_HP3_AWCACHE;
input [3:0] S_AXI_HP3_AWLEN;
input [3:0] S_AXI_HP3_AWQOS;
input [5:0] S_AXI_HP3_ARID;
input [5:0] S_AXI_HP3_AWID;
input [5:0] S_AXI_HP3_WID;
input [C_S_AXI_HP3_DATA_WIDTH-1:0] S_AXI_HP3_WDATA;
input [C_S_AXI_HP3_DATA_WIDTH/8-1:0] S_AXI_HP3_WSTRB;
output [1:0] DMA0_DATYPE;
output DMA0_DAVALID;
output DMA0_DRREADY;
input DMA0_ACLK;
input DMA0_DAREADY;
input DMA0_DRLAST;
input DMA0_DRVALID;
input [1:0] DMA0_DRTYPE;
output [1:0] DMA1_DATYPE;
output DMA1_DAVALID;
output DMA1_DRREADY;
input DMA1_ACLK;
input DMA1_DAREADY;
input DMA1_DRLAST;
input DMA1_DRVALID;
input [1:0] DMA1_DRTYPE;
output [1:0] DMA2_DATYPE;
output DMA2_DAVALID;
output DMA2_DRREADY;
input DMA2_ACLK;
input DMA2_DAREADY;
input DMA2_DRLAST;
input DMA2_DRVALID;
input DMA3_DRVALID;
output [1:0] DMA3_DATYPE;
output DMA3_DAVALID;
output DMA3_DRREADY;
input DMA3_ACLK;
input DMA3_DAREADY;
input DMA3_DRLAST;
input [1:0] DMA2_DRTYPE;
input [1:0] DMA3_DRTYPE;
input [31:0] FTMD_TRACEIN_DATA;
input FTMD_TRACEIN_VALID;
input FTMD_TRACEIN_CLK;
input [3:0] FTMD_TRACEIN_ATID;
input [3:0] FTMT_F2P_TRIG;
output [3:0] FTMT_F2P_TRIGACK;
input [31:0] FTMT_F2P_DEBUG;
input [3:0] FTMT_P2F_TRIGACK;
output [3:0] FTMT_P2F_TRIG;
output [31:0] FTMT_P2F_DEBUG;
output FCLK_CLK3;
output FCLK_CLK2;
output FCLK_CLK1;
output FCLK_CLK0;
input FCLK_CLKTRIG3_N;
input FCLK_CLKTRIG2_N;
input FCLK_CLKTRIG1_N;
input FCLK_CLKTRIG0_N;
output FCLK_RESET3_N;
output FCLK_RESET2_N;
output FCLK_RESET1_N;
output FCLK_RESET0_N;
input FPGA_IDLE_N;
input [3:0] DDR_ARB;
input [irq_width-1:0] IRQ_F2P;
input Core0_nFIQ;
input Core0_nIRQ;
input Core1_nFIQ;
input Core1_nIRQ;
output EVENT_EVENTO;
output [1:0] EVENT_STANDBYWFE;
output [1:0] EVENT_STANDBYWFI;
input EVENT_EVENTI;
inout [53:0] MIO;
inout DDR_Clk;
inout DDR_Clk_n;
inout DDR_CKE;
inout DDR_CS_n;
inout DDR_RAS_n;
inout DDR_CAS_n;
output DDR_WEB;
inout [2:0] DDR_BankAddr;
inout [14:0] DDR_Addr;
inout DDR_ODT;
inout DDR_DRSTB;
inout [31:0] DDR_DQ;
inout [3:0] DDR_DM;
inout [3:0] DDR_DQS;
inout [3:0] DDR_DQS_n;
inout DDR_VRN;
inout DDR_VRP;
/* Reset Input & Clock Input */
input PS_SRSTB;
input PS_CLK;
input PS_PORB;
output IRQ_P2F_DMAC_ABORT;
output IRQ_P2F_DMAC0;
output IRQ_P2F_DMAC1;
output IRQ_P2F_DMAC2;
output IRQ_P2F_DMAC3;
output IRQ_P2F_DMAC4;
output IRQ_P2F_DMAC5;
output IRQ_P2F_DMAC6;
output IRQ_P2F_DMAC7;
output IRQ_P2F_SMC;
output IRQ_P2F_QSPI;
output IRQ_P2F_CTI;
output IRQ_P2F_GPIO;
output IRQ_P2F_USB0;
output IRQ_P2F_ENET0;
output IRQ_P2F_ENET_WAKE0;
output IRQ_P2F_SDIO0;
output IRQ_P2F_I2C0;
output IRQ_P2F_SPI0;
output IRQ_P2F_UART0;
output IRQ_P2F_CAN0;
output IRQ_P2F_USB1;
output IRQ_P2F_ENET1;
output IRQ_P2F_ENET_WAKE1;
output IRQ_P2F_SDIO1;
output IRQ_P2F_I2C1;
output IRQ_P2F_SPI1;
output IRQ_P2F_UART1;
output IRQ_P2F_CAN1;
/* Internal wires/nets used for connectivity */
wire net_rstn;
wire net_sw_clk;
wire net_ocm_clk;
wire net_arbiter_clk;
wire net_axi_mgp0_rstn;
wire net_axi_mgp1_rstn;
wire net_axi_gp0_rstn;
wire net_axi_gp1_rstn;
wire net_axi_hp0_rstn;
wire net_axi_hp1_rstn;
wire net_axi_hp2_rstn;
wire net_axi_hp3_rstn;
wire net_axi_acp_rstn;
wire [4:0] net_axi_acp_awuser;
wire [4:0] net_axi_acp_aruser;
/* Dummy */
assign net_axi_acp_awuser = S_AXI_ACP_AWUSER;
assign net_axi_acp_aruser = S_AXI_ACP_ARUSER;
/* Global variables */
reg DEBUG_INFO = 1;
reg STOP_ON_ERROR = 1;
/* local variable acting as semaphore for wait_mem_update and wait_reg_update task */
reg mem_update_key = 1;
reg reg_update_key_0 = 1;
reg reg_update_key_1 = 1;
/* assignments and semantic checks for unused ports */
`include "processing_system7_bfm_v2_0_unused_ports.v"
/* include api definition */
`include "processing_system7_bfm_v2_0_apis.v"
/* Reset Generator */
processing_system7_bfm_v2_0_gen_reset gen_rst(.por_rst_n(PS_PORB),
.sys_rst_n(PS_SRSTB),
.rst_out_n(net_rstn),
.m_axi_gp0_clk(M_AXI_GP0_ACLK),
.m_axi_gp1_clk(M_AXI_GP1_ACLK),
.s_axi_gp0_clk(S_AXI_GP0_ACLK),
.s_axi_gp1_clk(S_AXI_GP1_ACLK),
.s_axi_hp0_clk(S_AXI_HP0_ACLK),
.s_axi_hp1_clk(S_AXI_HP1_ACLK),
.s_axi_hp2_clk(S_AXI_HP2_ACLK),
.s_axi_hp3_clk(S_AXI_HP3_ACLK),
.s_axi_acp_clk(S_AXI_ACP_ACLK),
.m_axi_gp0_rstn(net_axi_mgp0_rstn),
.m_axi_gp1_rstn(net_axi_mgp1_rstn),
.s_axi_gp0_rstn(net_axi_gp0_rstn),
.s_axi_gp1_rstn(net_axi_gp1_rstn),
.s_axi_hp0_rstn(net_axi_hp0_rstn),
.s_axi_hp1_rstn(net_axi_hp1_rstn),
.s_axi_hp2_rstn(net_axi_hp2_rstn),
.s_axi_hp3_rstn(net_axi_hp3_rstn),
.s_axi_acp_rstn(net_axi_acp_rstn),
.fclk_reset3_n(FCLK_RESET3_N),
.fclk_reset2_n(FCLK_RESET2_N),
.fclk_reset1_n(FCLK_RESET1_N),
.fclk_reset0_n(FCLK_RESET0_N),
.fpga_acp_reset_n(), ////S_AXI_ACP_ARESETN), (These are removed from Zynq IP)
.fpga_gp_m0_reset_n(), ////M_AXI_GP0_ARESETN),
.fpga_gp_m1_reset_n(), ////M_AXI_GP1_ARESETN),
.fpga_gp_s0_reset_n(), ////S_AXI_GP0_ARESETN),
.fpga_gp_s1_reset_n(), ////S_AXI_GP1_ARESETN),
.fpga_hp_s0_reset_n(), ////S_AXI_HP0_ARESETN),
.fpga_hp_s1_reset_n(), ////S_AXI_HP1_ARESETN),
.fpga_hp_s2_reset_n(), ////S_AXI_HP2_ARESETN),
.fpga_hp_s3_reset_n() ////S_AXI_HP3_ARESETN)
);
/* Clock Generator */
processing_system7_bfm_v2_0_gen_clock #(C_FCLK_CLK3_FREQ, C_FCLK_CLK2_FREQ, C_FCLK_CLK1_FREQ, C_FCLK_CLK0_FREQ)
gen_clk(.ps_clk(PS_CLK),
.sw_clk(net_sw_clk),
.fclk_clk3(FCLK_CLK3),
.fclk_clk2(FCLK_CLK2),
.fclk_clk1(FCLK_CLK1),
.fclk_clk0(FCLK_CLK0)
);
wire net_wr_ack_ocm_gp0, net_wr_ack_ddr_gp0, net_wr_ack_ocm_gp1, net_wr_ack_ddr_gp1;
wire net_wr_dv_ocm_gp0, net_wr_dv_ddr_gp0, net_wr_dv_ocm_gp1, net_wr_dv_ddr_gp1;
wire [max_burst_bits-1:0] net_wr_data_gp0, net_wr_data_gp1;
wire [addr_width-1:0] net_wr_addr_gp0, net_wr_addr_gp1;
wire [max_burst_bytes_width:0] net_wr_bytes_gp0, net_wr_bytes_gp1;
wire [axi_qos_width-1:0] net_wr_qos_gp0, net_wr_qos_gp1;
wire net_rd_req_ddr_gp0, net_rd_req_ddr_gp1;
wire net_rd_req_ocm_gp0, net_rd_req_ocm_gp1;
wire net_rd_req_reg_gp0, net_rd_req_reg_gp1;
wire [addr_width-1:0] net_rd_addr_gp0, net_rd_addr_gp1;
wire [max_burst_bytes_width:0] net_rd_bytes_gp0, net_rd_bytes_gp1;
wire [max_burst_bits-1:0] net_rd_data_ddr_gp0, net_rd_data_ddr_gp1;
wire [max_burst_bits-1:0] net_rd_data_ocm_gp0, net_rd_data_ocm_gp1;
wire [max_burst_bits-1:0] net_rd_data_reg_gp0, net_rd_data_reg_gp1;
wire net_rd_dv_ddr_gp0, net_rd_dv_ddr_gp1;
wire net_rd_dv_ocm_gp0, net_rd_dv_ocm_gp1;
wire net_rd_dv_reg_gp0, net_rd_dv_reg_gp1;
wire [axi_qos_width-1:0] net_rd_qos_gp0, net_rd_qos_gp1;
wire net_wr_ack_ddr_hp0, net_wr_ack_ddr_hp1, net_wr_ack_ddr_hp2, net_wr_ack_ddr_hp3;
wire net_wr_ack_ocm_hp0, net_wr_ack_ocm_hp1, net_wr_ack_ocm_hp2, net_wr_ack_ocm_hp3;
wire net_wr_dv_ddr_hp0, net_wr_dv_ddr_hp1, net_wr_dv_ddr_hp2, net_wr_dv_ddr_hp3;
wire net_wr_dv_ocm_hp0, net_wr_dv_ocm_hp1, net_wr_dv_ocm_hp2, net_wr_dv_ocm_hp3;
wire [max_burst_bits-1:0] net_wr_data_hp0, net_wr_data_hp1, net_wr_data_hp2, net_wr_data_hp3;
wire [addr_width-1:0] net_wr_addr_hp0, net_wr_addr_hp1, net_wr_addr_hp2, net_wr_addr_hp3;
wire [max_burst_bytes_width:0] net_wr_bytes_hp0, net_wr_bytes_hp1, net_wr_bytes_hp2, net_wr_bytes_hp3;
wire [axi_qos_width-1:0] net_wr_qos_hp0, net_wr_qos_hp1, net_wr_qos_hp2, net_wr_qos_hp3;
wire net_rd_req_ddr_hp0, net_rd_req_ddr_hp1, net_rd_req_ddr_hp2, net_rd_req_ddr_hp3;
wire net_rd_req_ocm_hp0, net_rd_req_ocm_hp1, net_rd_req_ocm_hp2, net_rd_req_ocm_hp3;
wire [addr_width-1:0] net_rd_addr_hp0, net_rd_addr_hp1, net_rd_addr_hp2, net_rd_addr_hp3;
wire [max_burst_bytes_width:0] net_rd_bytes_hp0, net_rd_bytes_hp1, net_rd_bytes_hp2, net_rd_bytes_hp3;
wire [max_burst_bits-1:0] net_rd_data_ddr_hp0, net_rd_data_ddr_hp1, net_rd_data_ddr_hp2, net_rd_data_ddr_hp3;
wire [max_burst_bits-1:0] net_rd_data_ocm_hp0, net_rd_data_ocm_hp1, net_rd_data_ocm_hp2, net_rd_data_ocm_hp3;
wire net_rd_dv_ddr_hp0, net_rd_dv_ddr_hp1, net_rd_dv_ddr_hp2, net_rd_dv_ddr_hp3;
wire net_rd_dv_ocm_hp0, net_rd_dv_ocm_hp1, net_rd_dv_ocm_hp2, net_rd_dv_ocm_hp3;
wire [axi_qos_width-1:0] net_rd_qos_hp0, net_rd_qos_hp1, net_rd_qos_hp2, net_rd_qos_hp3;
wire net_wr_ack_ddr_acp,net_wr_ack_ocm_acp;
wire net_wr_dv_ddr_acp,net_wr_dv_ocm_acp;
wire [max_burst_bits-1:0] net_wr_data_acp;
wire [addr_width-1:0] net_wr_addr_acp;
wire [max_burst_bytes_width:0] net_wr_bytes_acp;
wire [axi_qos_width-1:0] net_wr_qos_acp;
wire net_rd_req_ddr_acp, net_rd_req_ocm_acp;
wire [addr_width-1:0] net_rd_addr_acp;
wire [max_burst_bytes_width:0] net_rd_bytes_acp;
wire [max_burst_bits-1:0] net_rd_data_ddr_acp;
wire [max_burst_bits-1:0] net_rd_data_ocm_acp;
wire net_rd_dv_ddr_acp,net_rd_dv_ocm_acp;
wire [axi_qos_width-1:0] net_rd_qos_acp;
wire ocm_wr_ack_port0;
wire ocm_wr_dv_port0;
wire ocm_rd_req_port0;
wire ocm_rd_dv_port0;
wire [addr_width-1:0] ocm_wr_addr_port0;
wire [max_burst_bits-1:0] ocm_wr_data_port0;
wire [max_burst_bytes_width:0] ocm_wr_bytes_port0;
wire [addr_width-1:0] ocm_rd_addr_port0;
wire [max_burst_bits-1:0] ocm_rd_data_port0;
wire [max_burst_bytes_width:0] ocm_rd_bytes_port0;
wire [axi_qos_width-1:0] ocm_wr_qos_port0;
wire [axi_qos_width-1:0] ocm_rd_qos_port0;
wire ocm_wr_ack_port1;
wire ocm_wr_dv_port1;
wire ocm_rd_req_port1;
wire ocm_rd_dv_port1;
wire [addr_width-1:0] ocm_wr_addr_port1;
wire [max_burst_bits-1:0] ocm_wr_data_port1;
wire [max_burst_bytes_width:0] ocm_wr_bytes_port1;
wire [addr_width-1:0] ocm_rd_addr_port1;
wire [max_burst_bits-1:0] ocm_rd_data_port1;
wire [max_burst_bytes_width:0] ocm_rd_bytes_port1;
wire [axi_qos_width-1:0] ocm_wr_qos_port1;
wire [axi_qos_width-1:0] ocm_rd_qos_port1;
wire ddr_wr_ack_port0;
wire ddr_wr_dv_port0;
wire ddr_rd_req_port0;
wire ddr_rd_dv_port0;
wire[addr_width-1:0] ddr_wr_addr_port0;
wire[max_burst_bits-1:0] ddr_wr_data_port0;
wire[max_burst_bytes_width:0] ddr_wr_bytes_port0;
wire[addr_width-1:0] ddr_rd_addr_port0;
wire[max_burst_bits-1:0] ddr_rd_data_port0;
wire[max_burst_bytes_width:0] ddr_rd_bytes_port0;
wire [axi_qos_width-1:0] ddr_wr_qos_port0;
wire [axi_qos_width-1:0] ddr_rd_qos_port0;
wire ddr_wr_ack_port1;
wire ddr_wr_dv_port1;
wire ddr_rd_req_port1;
wire ddr_rd_dv_port1;
wire[addr_width-1:0] ddr_wr_addr_port1;
wire[max_burst_bits-1:0] ddr_wr_data_port1;
wire[max_burst_bytes_width:0] ddr_wr_bytes_port1;
wire[addr_width-1:0] ddr_rd_addr_port1;
wire[max_burst_bits-1:0] ddr_rd_data_port1;
wire[max_burst_bytes_width:0] ddr_rd_bytes_port1;
wire[axi_qos_width-1:0] ddr_wr_qos_port1;
wire[axi_qos_width-1:0] ddr_rd_qos_port1;
wire ddr_wr_ack_port2;
wire ddr_wr_dv_port2;
wire ddr_rd_req_port2;
wire ddr_rd_dv_port2;
wire[addr_width-1:0] ddr_wr_addr_port2;
wire[max_burst_bits-1:0] ddr_wr_data_port2;
wire[max_burst_bytes_width:0] ddr_wr_bytes_port2;
wire[addr_width-1:0] ddr_rd_addr_port2;
wire[max_burst_bits-1:0] ddr_rd_data_port2;
wire[max_burst_bytes_width:0] ddr_rd_bytes_port2;
wire[axi_qos_width-1:0] ddr_wr_qos_port2;
wire[axi_qos_width-1:0] ddr_rd_qos_port2;
wire ddr_wr_ack_port3;
wire ddr_wr_dv_port3;
wire ddr_rd_req_port3;
wire ddr_rd_dv_port3;
wire[addr_width-1:0] ddr_wr_addr_port3;
wire[max_burst_bits-1:0] ddr_wr_data_port3;
wire[max_burst_bytes_width:0] ddr_wr_bytes_port3;
wire[addr_width-1:0] ddr_rd_addr_port3;
wire[max_burst_bits-1:0] ddr_rd_data_port3;
wire[max_burst_bytes_width:0] ddr_rd_bytes_port3;
wire[axi_qos_width-1:0] ddr_wr_qos_port3;
wire[axi_qos_width-1:0] ddr_rd_qos_port3;
wire reg_rd_req_port0;
wire reg_rd_dv_port0;
wire[addr_width-1:0] reg_rd_addr_port0;
wire[max_burst_bits-1:0] reg_rd_data_port0;
wire[max_burst_bytes_width:0] reg_rd_bytes_port0;
wire [axi_qos_width-1:0] reg_rd_qos_port0;
wire reg_rd_req_port1;
wire reg_rd_dv_port1;
wire[addr_width-1:0] reg_rd_addr_port1;
wire[max_burst_bits-1:0] reg_rd_data_port1;
wire[max_burst_bytes_width:0] reg_rd_bytes_port1;
wire [axi_qos_width-1:0] reg_rd_qos_port1;
wire [11:0] M_AXI_GP0_AWID_FULL;
wire [11:0] M_AXI_GP0_WID_FULL;
wire [11:0] M_AXI_GP0_ARID_FULL;
wire [11:0] M_AXI_GP0_BID_FULL;
wire [11:0] M_AXI_GP0_RID_FULL;
wire [11:0] M_AXI_GP1_AWID_FULL;
wire [11:0] M_AXI_GP1_WID_FULL;
wire [11:0] M_AXI_GP1_ARID_FULL;
wire [11:0] M_AXI_GP1_BID_FULL;
wire [11:0] M_AXI_GP1_RID_FULL;
function [5:0] compress_id;
input [11:0] id;
begin
compress_id = id[5:0];
end
endfunction
function [11:0] uncompress_id;
input [5:0] id;
begin
uncompress_id = {6'b110000, id[5:0]};
end
endfunction
assign M_AXI_GP0_AWID = (C_M_AXI_GP0_ENABLE_STATIC_REMAP == 1) ? compress_id(M_AXI_GP0_AWID_FULL) : M_AXI_GP0_AWID_FULL;
assign M_AXI_GP0_WID = (C_M_AXI_GP0_ENABLE_STATIC_REMAP == 1) ? compress_id(M_AXI_GP0_WID_FULL) : M_AXI_GP0_WID_FULL;
assign M_AXI_GP0_ARID = (C_M_AXI_GP0_ENABLE_STATIC_REMAP == 1) ? compress_id(M_AXI_GP0_ARID_FULL) : M_AXI_GP0_ARID_FULL;
assign M_AXI_GP0_BID_FULL = (C_M_AXI_GP0_ENABLE_STATIC_REMAP == 1) ? uncompress_id(M_AXI_GP0_BID) : M_AXI_GP0_BID;
assign M_AXI_GP0_RID_FULL = (C_M_AXI_GP0_ENABLE_STATIC_REMAP == 1) ? uncompress_id(M_AXI_GP0_RID) : M_AXI_GP0_RID;
assign M_AXI_GP1_AWID = (C_M_AXI_GP1_ENABLE_STATIC_REMAP == 1) ? compress_id(M_AXI_GP1_AWID_FULL) : M_AXI_GP1_AWID_FULL;
assign M_AXI_GP1_WID = (C_M_AXI_GP1_ENABLE_STATIC_REMAP == 1) ? compress_id(M_AXI_GP1_WID_FULL) : M_AXI_GP1_WID_FULL;
assign M_AXI_GP1_ARID = (C_M_AXI_GP1_ENABLE_STATIC_REMAP == 1) ? compress_id(M_AXI_GP1_ARID_FULL) : M_AXI_GP1_ARID_FULL;
assign M_AXI_GP1_BID_FULL = (C_M_AXI_GP1_ENABLE_STATIC_REMAP == 1) ? uncompress_id(M_AXI_GP1_BID) : M_AXI_GP1_BID;
assign M_AXI_GP1_RID_FULL = (C_M_AXI_GP1_ENABLE_STATIC_REMAP == 1) ? uncompress_id(M_AXI_GP1_RID) : M_AXI_GP1_RID;
processing_system7_bfm_v2_0_interconnect_model icm (
.rstn(net_rstn),
.sw_clk(net_sw_clk),
.w_qos_gp0(net_wr_qos_gp0),
.w_qos_gp1(net_wr_qos_gp1),
.w_qos_hp0(net_wr_qos_hp0),
.w_qos_hp1(net_wr_qos_hp1),
.w_qos_hp2(net_wr_qos_hp2),
.w_qos_hp3(net_wr_qos_hp3),
.r_qos_gp0(net_rd_qos_gp0),
.r_qos_gp1(net_rd_qos_gp1),
.r_qos_hp0(net_rd_qos_hp0),
.r_qos_hp1(net_rd_qos_hp1),
.r_qos_hp2(net_rd_qos_hp2),
.r_qos_hp3(net_rd_qos_hp3),
/* GP Slave ports access */
.wr_ack_ddr_gp0(net_wr_ack_ddr_gp0),
.wr_ack_ocm_gp0(net_wr_ack_ocm_gp0),
.wr_data_gp0(net_wr_data_gp0),
.wr_addr_gp0(net_wr_addr_gp0),
.wr_bytes_gp0(net_wr_bytes_gp0),
.wr_dv_ddr_gp0(net_wr_dv_ddr_gp0),
.wr_dv_ocm_gp0(net_wr_dv_ocm_gp0),
.rd_req_ddr_gp0(net_rd_req_ddr_gp0),
.rd_req_ocm_gp0(net_rd_req_ocm_gp0),
.rd_req_reg_gp0(net_rd_req_reg_gp0),
.rd_addr_gp0(net_rd_addr_gp0),
.rd_bytes_gp0(net_rd_bytes_gp0),
.rd_data_ddr_gp0(net_rd_data_ddr_gp0),
.rd_data_ocm_gp0(net_rd_data_ocm_gp0),
.rd_data_reg_gp0(net_rd_data_reg_gp0),
.rd_dv_ddr_gp0(net_rd_dv_ddr_gp0),
.rd_dv_ocm_gp0(net_rd_dv_ocm_gp0),
.rd_dv_reg_gp0(net_rd_dv_reg_gp0),
.wr_ack_ddr_gp1(net_wr_ack_ddr_gp1),
.wr_ack_ocm_gp1(net_wr_ack_ocm_gp1),
.wr_data_gp1(net_wr_data_gp1),
.wr_addr_gp1(net_wr_addr_gp1),
.wr_bytes_gp1(net_wr_bytes_gp1),
.wr_dv_ddr_gp1(net_wr_dv_ddr_gp1),
.wr_dv_ocm_gp1(net_wr_dv_ocm_gp1),
.rd_req_ddr_gp1(net_rd_req_ddr_gp1),
.rd_req_ocm_gp1(net_rd_req_ocm_gp1),
.rd_req_reg_gp1(net_rd_req_reg_gp1),
.rd_addr_gp1(net_rd_addr_gp1),
.rd_bytes_gp1(net_rd_bytes_gp1),
.rd_data_ddr_gp1(net_rd_data_ddr_gp1),
.rd_data_ocm_gp1(net_rd_data_ocm_gp1),
.rd_data_reg_gp1(net_rd_data_reg_gp1),
.rd_dv_ddr_gp1(net_rd_dv_ddr_gp1),
.rd_dv_ocm_gp1(net_rd_dv_ocm_gp1),
.rd_dv_reg_gp1(net_rd_dv_reg_gp1),
/* HP Slave ports access */
.wr_ack_ddr_hp0(net_wr_ack_ddr_hp0),
.wr_ack_ocm_hp0(net_wr_ack_ocm_hp0),
.wr_data_hp0(net_wr_data_hp0),
.wr_addr_hp0(net_wr_addr_hp0),
.wr_bytes_hp0(net_wr_bytes_hp0),
.wr_dv_ddr_hp0(net_wr_dv_ddr_hp0),
.wr_dv_ocm_hp0(net_wr_dv_ocm_hp0),
.rd_req_ddr_hp0(net_rd_req_ddr_hp0),
.rd_req_ocm_hp0(net_rd_req_ocm_hp0),
.rd_addr_hp0(net_rd_addr_hp0),
.rd_bytes_hp0(net_rd_bytes_hp0),
.rd_data_ddr_hp0(net_rd_data_ddr_hp0),
.rd_data_ocm_hp0(net_rd_data_ocm_hp0),
.rd_dv_ddr_hp0(net_rd_dv_ddr_hp0),
.rd_dv_ocm_hp0(net_rd_dv_ocm_hp0),
.wr_ack_ddr_hp1(net_wr_ack_ddr_hp1),
.wr_ack_ocm_hp1(net_wr_ack_ocm_hp1),
.wr_data_hp1(net_wr_data_hp1),
.wr_addr_hp1(net_wr_addr_hp1),
.wr_bytes_hp1(net_wr_bytes_hp1),
.wr_dv_ddr_hp1(net_wr_dv_ddr_hp1),
.wr_dv_ocm_hp1(net_wr_dv_ocm_hp1),
.rd_req_ddr_hp1(net_rd_req_ddr_hp1),
.rd_req_ocm_hp1(net_rd_req_ocm_hp1),
.rd_addr_hp1(net_rd_addr_hp1),
.rd_bytes_hp1(net_rd_bytes_hp1),
.rd_data_ddr_hp1(net_rd_data_ddr_hp1),
.rd_data_ocm_hp1(net_rd_data_ocm_hp1),
.rd_dv_ocm_hp1(net_rd_dv_ocm_hp1),
.rd_dv_ddr_hp1(net_rd_dv_ddr_hp1),
.wr_ack_ddr_hp2(net_wr_ack_ddr_hp2),
.wr_ack_ocm_hp2(net_wr_ack_ocm_hp2),
.wr_data_hp2(net_wr_data_hp2),
.wr_addr_hp2(net_wr_addr_hp2),
.wr_bytes_hp2(net_wr_bytes_hp2),
.wr_dv_ocm_hp2(net_wr_dv_ocm_hp2),
.wr_dv_ddr_hp2(net_wr_dv_ddr_hp2),
.rd_req_ddr_hp2(net_rd_req_ddr_hp2),
.rd_req_ocm_hp2(net_rd_req_ocm_hp2),
.rd_addr_hp2(net_rd_addr_hp2),
.rd_bytes_hp2(net_rd_bytes_hp2),
.rd_data_ddr_hp2(net_rd_data_ddr_hp2),
.rd_data_ocm_hp2(net_rd_data_ocm_hp2),
.rd_dv_ddr_hp2(net_rd_dv_ddr_hp2),
.rd_dv_ocm_hp2(net_rd_dv_ocm_hp2),
.wr_ack_ocm_hp3(net_wr_ack_ocm_hp3),
.wr_ack_ddr_hp3(net_wr_ack_ddr_hp3),
.wr_data_hp3(net_wr_data_hp3),
.wr_addr_hp3(net_wr_addr_hp3),
.wr_bytes_hp3(net_wr_bytes_hp3),
.wr_dv_ddr_hp3(net_wr_dv_ddr_hp3),
.wr_dv_ocm_hp3(net_wr_dv_ocm_hp3),
.rd_req_ddr_hp3(net_rd_req_ddr_hp3),
.rd_req_ocm_hp3(net_rd_req_ocm_hp3),
.rd_addr_hp3(net_rd_addr_hp3),
.rd_bytes_hp3(net_rd_bytes_hp3),
.rd_data_ddr_hp3(net_rd_data_ddr_hp3),
.rd_data_ocm_hp3(net_rd_data_ocm_hp3),
.rd_dv_ddr_hp3(net_rd_dv_ddr_hp3),
.rd_dv_ocm_hp3(net_rd_dv_ocm_hp3),
/* Goes to port 1 of DDR */
.ddr_wr_ack_port1(ddr_wr_ack_port1),
.ddr_wr_dv_port1(ddr_wr_dv_port1),
.ddr_rd_req_port1(ddr_rd_req_port1),
.ddr_rd_dv_port1 (ddr_rd_dv_port1),
.ddr_wr_addr_port1(ddr_wr_addr_port1),
.ddr_wr_data_port1(ddr_wr_data_port1),
.ddr_wr_bytes_port1(ddr_wr_bytes_port1),
.ddr_rd_addr_port1(ddr_rd_addr_port1),
.ddr_rd_data_port1(ddr_rd_data_port1),
.ddr_rd_bytes_port1(ddr_rd_bytes_port1),
.ddr_wr_qos_port1(ddr_wr_qos_port1),
.ddr_rd_qos_port1(ddr_rd_qos_port1),
/* Goes to port2 of DDR */
.ddr_wr_ack_port2 (ddr_wr_ack_port2),
.ddr_wr_dv_port2 (ddr_wr_dv_port2),
.ddr_rd_req_port2 (ddr_rd_req_port2),
.ddr_rd_dv_port2 (ddr_rd_dv_port2),
.ddr_wr_addr_port2(ddr_wr_addr_port2),
.ddr_wr_data_port2(ddr_wr_data_port2),
.ddr_wr_bytes_port2(ddr_wr_bytes_port2),
.ddr_rd_addr_port2(ddr_rd_addr_port2),
.ddr_rd_data_port2(ddr_rd_data_port2),
.ddr_rd_bytes_port2(ddr_rd_bytes_port2),
.ddr_wr_qos_port2 (ddr_wr_qos_port2),
.ddr_rd_qos_port2 (ddr_rd_qos_port2),
/* Goes to port3 of DDR */
.ddr_wr_ack_port3 (ddr_wr_ack_port3),
.ddr_wr_dv_port3 (ddr_wr_dv_port3),
.ddr_rd_req_port3 (ddr_rd_req_port3),
.ddr_rd_dv_port3 (ddr_rd_dv_port3),
.ddr_wr_addr_port3(ddr_wr_addr_port3),
.ddr_wr_data_port3(ddr_wr_data_port3),
.ddr_wr_bytes_port3(ddr_wr_bytes_port3),
.ddr_rd_addr_port3(ddr_rd_addr_port3),
.ddr_rd_data_port3(ddr_rd_data_port3),
.ddr_rd_bytes_port3(ddr_rd_bytes_port3),
.ddr_wr_qos_port3 (ddr_wr_qos_port3),
.ddr_rd_qos_port3 (ddr_rd_qos_port3),
/* Goes to port 0 of OCM */
.ocm_wr_ack_port1 (ocm_wr_ack_port1),
.ocm_wr_dv_port1 (ocm_wr_dv_port1),
.ocm_rd_req_port1 (ocm_rd_req_port1),
.ocm_rd_dv_port1 (ocm_rd_dv_port1),
.ocm_wr_addr_port1(ocm_wr_addr_port1),
.ocm_wr_data_port1(ocm_wr_data_port1),
.ocm_wr_bytes_port1(ocm_wr_bytes_port1),
.ocm_rd_addr_port1(ocm_rd_addr_port1),
.ocm_rd_data_port1(ocm_rd_data_port1),
.ocm_rd_bytes_port1(ocm_rd_bytes_port1),
.ocm_wr_qos_port1(ocm_wr_qos_port1),
.ocm_rd_qos_port1(ocm_rd_qos_port1),
/* Goes to port 0 of REG */
.reg_rd_qos_port1 (reg_rd_qos_port1) ,
.reg_rd_req_port1 (reg_rd_req_port1),
.reg_rd_dv_port1 (reg_rd_dv_port1),
.reg_rd_addr_port1(reg_rd_addr_port1),
.reg_rd_data_port1(reg_rd_data_port1),
.reg_rd_bytes_port1(reg_rd_bytes_port1)
);
processing_system7_bfm_v2_0_ddrc ddrc (
.rstn(net_rstn),
.sw_clk(net_sw_clk),
/* Goes to port 0 of DDR */
.ddr_wr_ack_port0 (ddr_wr_ack_port0),
.ddr_wr_dv_port0 (ddr_wr_dv_port0),
.ddr_rd_req_port0 (ddr_rd_req_port0),
.ddr_rd_dv_port0 (ddr_rd_dv_port0),
.ddr_wr_addr_port0(net_wr_addr_acp),
.ddr_wr_data_port0(net_wr_data_acp),
.ddr_wr_bytes_port0(net_wr_bytes_acp),
.ddr_rd_addr_port0(net_rd_addr_acp),
.ddr_rd_bytes_port0(net_rd_bytes_acp),
.ddr_rd_data_port0(ddr_rd_data_port0),
.ddr_wr_qos_port0 (net_wr_qos_acp),
.ddr_rd_qos_port0 (net_rd_qos_acp),
/* Goes to port 1 of DDR */
.ddr_wr_ack_port1 (ddr_wr_ack_port1),
.ddr_wr_dv_port1 (ddr_wr_dv_port1),
.ddr_rd_req_port1 (ddr_rd_req_port1),
.ddr_rd_dv_port1 (ddr_rd_dv_port1),
.ddr_wr_addr_port1(ddr_wr_addr_port1),
.ddr_wr_data_port1(ddr_wr_data_port1),
.ddr_wr_bytes_port1(ddr_wr_bytes_port1),
.ddr_rd_addr_port1(ddr_rd_addr_port1),
.ddr_rd_data_port1(ddr_rd_data_port1),
.ddr_rd_bytes_port1(ddr_rd_bytes_port1),
.ddr_wr_qos_port1 (ddr_wr_qos_port1),
.ddr_rd_qos_port1 (ddr_rd_qos_port1),
/* Goes to port2 of DDR */
.ddr_wr_ack_port2 (ddr_wr_ack_port2),
.ddr_wr_dv_port2 (ddr_wr_dv_port2),
.ddr_rd_req_port2 (ddr_rd_req_port2),
.ddr_rd_dv_port2 (ddr_rd_dv_port2),
.ddr_wr_addr_port2(ddr_wr_addr_port2),
.ddr_wr_data_port2(ddr_wr_data_port2),
.ddr_wr_bytes_port2(ddr_wr_bytes_port2),
.ddr_rd_addr_port2(ddr_rd_addr_port2),
.ddr_rd_data_port2(ddr_rd_data_port2),
.ddr_rd_bytes_port2(ddr_rd_bytes_port2),
.ddr_wr_qos_port2 (ddr_wr_qos_port2),
.ddr_rd_qos_port2 (ddr_rd_qos_port2),
/* Goes to port3 of DDR */
.ddr_wr_ack_port3 (ddr_wr_ack_port3),
.ddr_wr_dv_port3 (ddr_wr_dv_port3),
.ddr_rd_req_port3 (ddr_rd_req_port3),
.ddr_rd_dv_port3 (ddr_rd_dv_port3),
.ddr_wr_addr_port3(ddr_wr_addr_port3),
.ddr_wr_data_port3(ddr_wr_data_port3),
.ddr_wr_bytes_port3(ddr_wr_bytes_port3),
.ddr_rd_addr_port3(ddr_rd_addr_port3),
.ddr_rd_data_port3(ddr_rd_data_port3),
.ddr_rd_bytes_port3(ddr_rd_bytes_port3),
.ddr_wr_qos_port3 (ddr_wr_qos_port3),
.ddr_rd_qos_port3 (ddr_rd_qos_port3)
);
processing_system7_bfm_v2_0_ocmc ocmc (
.rstn(net_rstn),
.sw_clk(net_sw_clk),
/* Goes to port 0 of OCM */
.ocm_wr_ack_port0 (ocm_wr_ack_port0),
.ocm_wr_dv_port0 (ocm_wr_dv_port0),
.ocm_rd_req_port0 (ocm_rd_req_port0),
.ocm_rd_dv_port0 (ocm_rd_dv_port0),
.ocm_wr_addr_port0(net_wr_addr_acp),
.ocm_wr_data_port0(net_wr_data_acp),
.ocm_wr_bytes_port0(net_wr_bytes_acp),
.ocm_rd_addr_port0(net_rd_addr_acp),
.ocm_rd_bytes_port0(net_rd_bytes_acp),
.ocm_rd_data_port0(ocm_rd_data_port0),
.ocm_wr_qos_port0 (net_wr_qos_acp),
.ocm_rd_qos_port0 (net_rd_qos_acp),
/* Goes to port 1 of OCM */
.ocm_wr_ack_port1 (ocm_wr_ack_port1),
.ocm_wr_dv_port1 (ocm_wr_dv_port1),
.ocm_rd_req_port1 (ocm_rd_req_port1),
.ocm_rd_dv_port1 (ocm_rd_dv_port1),
.ocm_wr_addr_port1(ocm_wr_addr_port1),
.ocm_wr_data_port1(ocm_wr_data_port1),
.ocm_wr_bytes_port1(ocm_wr_bytes_port1),
.ocm_rd_addr_port1(ocm_rd_addr_port1),
.ocm_rd_data_port1(ocm_rd_data_port1),
.ocm_rd_bytes_port1(ocm_rd_bytes_port1),
.ocm_wr_qos_port1(ocm_wr_qos_port1),
.ocm_rd_qos_port1(ocm_rd_qos_port1)
);
processing_system7_bfm_v2_0_regc regc (
.rstn(net_rstn),
.sw_clk(net_sw_clk),
/* Goes to port 0 of REG */
.reg_rd_req_port0 (reg_rd_req_port0),
.reg_rd_dv_port0 (reg_rd_dv_port0),
.reg_rd_addr_port0(net_rd_addr_acp),
.reg_rd_bytes_port0(net_rd_bytes_acp),
.reg_rd_data_port0(reg_rd_data_port0),
.reg_rd_qos_port0 (net_rd_qos_acp),
/* Goes to port 1 of REG */
.reg_rd_req_port1 (reg_rd_req_port1),
.reg_rd_dv_port1 (reg_rd_dv_port1),
.reg_rd_addr_port1(reg_rd_addr_port1),
.reg_rd_data_port1(reg_rd_data_port1),
.reg_rd_bytes_port1(reg_rd_bytes_port1),
.reg_rd_qos_port1(reg_rd_qos_port1)
);
/* include axi_gp port instantiations */
`include "processing_system7_bfm_v2_0_axi_gp.v"
/* include axi_hp port instantiations */
`include "processing_system7_bfm_v2_0_axi_hp.v"
/* include axi_acp port instantiations */
`include "processing_system7_bfm_v2_0_axi_acp.v"
endmodule
|
module sky130_fd_sc_hs__sdfbbp (
//# {{data|Data Signals}}
input D ,
output Q ,
output Q_N ,
//# {{control|Control Signals}}
input RESET_B,
input SET_B ,
//# {{scanchain|Scan Chain}}
input SCD ,
input SCE ,
//# {{clocks|Clocking}}
input CLK
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
endmodule
|
module th22r ( y, a, b, rsb );
output y;
input a, b, rsb;
specify
specparam CDS_LIBNAME = "static";
specparam CDS_CELLNAME = "th22r";
specparam CDS_VIEWNAME = "schematic";
endspecify
pfet_b P7 ( .b(cds_globals.vdd_), .g(rsb), .s(cds_globals.vdd_),
.d(net15));
pfet_b P4 ( .b(cds_globals.vdd_), .g(a), .s(cds_globals.vdd_),
.d(net24));
pfet_b P3 ( .b(cds_globals.vdd_), .g(y), .s(net24), .d(net15));
pfet_b P2 ( .b(cds_globals.vdd_), .g(b), .s(cds_globals.vdd_),
.d(net24));
pfet_b P1 ( .b(cds_globals.vdd_), .g(b), .s(net35), .d(net15));
pfet_b P0 ( .b(cds_globals.vdd_), .g(a), .s(cds_globals.vdd_),
.d(net35));
nfet_b N7 ( .d(net023), .g(rsb), .s(cds_globals.gnd_),
.b(cds_globals.gnd_));
nfet_b N4 ( .d(net22), .g(b), .s(net023), .b(cds_globals.gnd_));
nfet_b N3 ( .d(net22), .g(a), .s(net023), .b(cds_globals.gnd_));
nfet_b N2 ( .d(net15), .g(y), .s(net22), .b(cds_globals.gnd_));
nfet_b N1 ( .d(net34), .g(a), .s(net023), .b(cds_globals.gnd_));
nfet_b N0 ( .d(net15), .g(b), .s(net34), .b(cds_globals.gnd_));
inv I2 ( y, net15);
endmodule
|
module lm32_instruction_unit (
// ----- Inputs -------
clk_i,
rst_i,
`ifdef CFG_DEBUG_ENABLED
`ifdef CFG_ALTERNATE_EBA
at_debug,
`endif
`endif
// From pipeline
stall_a,
stall_f,
stall_d,
stall_x,
stall_m,
valid_f,
valid_d,
kill_f,
branch_predict_taken_d,
branch_predict_address_d,
`ifdef CFG_FAST_UNCONDITIONAL_BRANCH
branch_taken_x,
branch_target_x,
`endif
exception_m,
branch_taken_m,
branch_mispredict_taken_m,
branch_target_m,
`ifdef CFG_ICACHE_ENABLED
iflush,
`endif
`ifdef CFG_DCACHE_ENABLED
dcache_restart_request,
dcache_refill_request,
dcache_refilling,
`endif
`ifdef CFG_IROM_ENABLED
irom_store_data_m,
irom_address_xm,
irom_we_xm,
`endif
`ifdef CFG_IWB_ENABLED
// From Wishbone
i_dat_i,
i_ack_i,
i_err_i,
`endif
`ifdef CFG_HW_DEBUG_ENABLED
jtag_read_enable,
jtag_write_enable,
jtag_write_data,
jtag_address,
`endif
// ----- Outputs -------
// To pipeline
pc_f,
pc_d,
pc_x,
pc_m,
pc_w,
`ifdef CFG_ICACHE_ENABLED
icache_stall_request,
icache_restart_request,
icache_refill_request,
icache_refilling,
`endif
`ifdef CFG_IROM_ENABLED
irom_data_m,
`endif
`ifdef CFG_IWB_ENABLED
// To Wishbone
i_dat_o,
i_adr_o,
i_cyc_o,
i_sel_o,
i_stb_o,
i_we_o,
i_cti_o,
i_lock_o,
i_bte_o,
`endif
`ifdef CFG_HW_DEBUG_ENABLED
jtag_read_data,
jtag_access_complete,
`endif
`ifdef CFG_BUS_ERRORS_ENABLED
bus_error_d,
`endif
`ifdef CFG_EBR_POSEDGE_REGISTER_FILE
instruction_f,
`endif
instruction_d
);
/////////////////////////////////////////////////////
// Parameters
/////////////////////////////////////////////////////
parameter associativity = 1; // Associativity of the cache (Number of ways)
parameter sets = 512; // Number of sets
parameter bytes_per_line = 16; // Number of bytes per cache line
parameter base_address = 0; // Base address of cachable memory
parameter limit = 0; // Limit (highest address) of cachable memory
// For bytes_per_line == 4, we set 1 so part-select range isn't reversed, even though not really used
localparam addr_offset_width = bytes_per_line == 4 ? 1 : clogb2(bytes_per_line)-1-2;
localparam addr_offset_lsb = 2;
localparam addr_offset_msb = (addr_offset_lsb+addr_offset_width-1);
/////////////////////////////////////////////////////
// Inputs
/////////////////////////////////////////////////////
input clk_i; // Clock
input rst_i; // Reset
`ifdef CFG_DEBUG_ENABLED
`ifdef CFG_ALTERNATE_EBA
input at_debug; // GPIO input that maps EBA to DEBA
`endif
`endif
input stall_a; // Stall A stage instruction
input stall_f; // Stall F stage instruction
input stall_d; // Stall D stage instruction
input stall_x; // Stall X stage instruction
input stall_m; // Stall M stage instruction
input valid_f; // Instruction in F stage is valid
input valid_d; // Instruction in D stage is valid
input kill_f; // Kill instruction in F stage
input branch_predict_taken_d; // Branch is predicted taken in D stage
input [`LM32_PC_RNG] branch_predict_address_d; // Branch target address
`ifdef CFG_FAST_UNCONDITIONAL_BRANCH
input branch_taken_x; // Branch instruction in X stage is taken
input [`LM32_PC_RNG] branch_target_x; // Target PC of X stage branch instruction
`endif
input exception_m;
input branch_taken_m; // Branch instruction in M stage is taken
input branch_mispredict_taken_m; // Branch instruction in M stage is mispredicted as taken
input [`LM32_PC_RNG] branch_target_m; // Target PC of M stage branch instruction
`ifdef CFG_ICACHE_ENABLED
input iflush; // Flush instruction cache
`endif
`ifdef CFG_DCACHE_ENABLED
input dcache_restart_request; // Restart instruction that caused a data cache miss
input dcache_refill_request; // Request to refill data cache
input dcache_refilling;
`endif
`ifdef CFG_IROM_ENABLED
input [`LM32_WORD_RNG] irom_store_data_m; // Data from load-store unit
input [`LM32_WORD_RNG] irom_address_xm; // Address from load-store unit
input irom_we_xm; // Indicates if memory operation is load or store
`endif
`ifdef CFG_IWB_ENABLED
input [`LM32_WORD_RNG] i_dat_i; // Instruction Wishbone interface read data
input i_ack_i; // Instruction Wishbone interface acknowledgement
input i_err_i; // Instruction Wishbone interface error
`endif
`ifdef CFG_HW_DEBUG_ENABLED
input jtag_read_enable; // JTAG read memory request
input jtag_write_enable; // JTAG write memory request
input [`LM32_BYTE_RNG] jtag_write_data; // JTAG wrirte data
input [`LM32_WORD_RNG] jtag_address; // JTAG read/write address
`endif
/////////////////////////////////////////////////////
// Outputs
/////////////////////////////////////////////////////
output [`LM32_PC_RNG] pc_f; // F stage PC
reg [`LM32_PC_RNG] pc_f;
output [`LM32_PC_RNG] pc_d; // D stage PC
reg [`LM32_PC_RNG] pc_d;
output [`LM32_PC_RNG] pc_x; // X stage PC
reg [`LM32_PC_RNG] pc_x;
output [`LM32_PC_RNG] pc_m; // M stage PC
reg [`LM32_PC_RNG] pc_m;
output [`LM32_PC_RNG] pc_w; // W stage PC
reg [`LM32_PC_RNG] pc_w;
`ifdef CFG_ICACHE_ENABLED
output icache_stall_request; // Instruction cache stall request
wire icache_stall_request;
output icache_restart_request; // Request to restart instruction that cached instruction cache miss
wire icache_restart_request;
output icache_refill_request; // Instruction cache refill request
wire icache_refill_request;
output icache_refilling; // Indicates the icache is refilling
wire icache_refilling;
`endif
`ifdef CFG_IROM_ENABLED
output [`LM32_WORD_RNG] irom_data_m; // Data to load-store unit on load
wire [`LM32_WORD_RNG] irom_data_m;
`endif
`ifdef CFG_IWB_ENABLED
output [`LM32_WORD_RNG] i_dat_o; // Instruction Wishbone interface write data
`ifdef CFG_HW_DEBUG_ENABLED
reg [`LM32_WORD_RNG] i_dat_o;
`else
wire [`LM32_WORD_RNG] i_dat_o;
`endif
output [`LM32_WORD_RNG] i_adr_o; // Instruction Wishbone interface address
reg [`LM32_WORD_RNG] i_adr_o;
output i_cyc_o; // Instruction Wishbone interface cycle
reg i_cyc_o;
output [`LM32_BYTE_SELECT_RNG] i_sel_o; // Instruction Wishbone interface byte select
`ifdef CFG_HW_DEBUG_ENABLED
reg [`LM32_BYTE_SELECT_RNG] i_sel_o;
`else
wire [`LM32_BYTE_SELECT_RNG] i_sel_o;
`endif
output i_stb_o; // Instruction Wishbone interface strobe
reg i_stb_o;
output i_we_o; // Instruction Wishbone interface write enable
`ifdef CFG_HW_DEBUG_ENABLED
reg i_we_o;
`else
wire i_we_o;
`endif
output [`LM32_CTYPE_RNG] i_cti_o; // Instruction Wishbone interface cycle type
reg [`LM32_CTYPE_RNG] i_cti_o;
output i_lock_o; // Instruction Wishbone interface lock bus
reg i_lock_o;
output [`LM32_BTYPE_RNG] i_bte_o; // Instruction Wishbone interface burst type
wire [`LM32_BTYPE_RNG] i_bte_o;
`endif
`ifdef CFG_HW_DEBUG_ENABLED
output [`LM32_BYTE_RNG] jtag_read_data; // Data read for JTAG interface
reg [`LM32_BYTE_RNG] jtag_read_data;
output jtag_access_complete; // Requested memory access by JTAG interface is complete
wire jtag_access_complete;
`endif
`ifdef CFG_BUS_ERRORS_ENABLED
output bus_error_d; // Indicates a bus error occured while fetching the instruction
reg bus_error_d;
`endif
`ifdef CFG_EBR_POSEDGE_REGISTER_FILE
output [`LM32_INSTRUCTION_RNG] instruction_f; // F stage instruction (only to have register indices extracted from)
wire [`LM32_INSTRUCTION_RNG] instruction_f;
`endif
output [`LM32_INSTRUCTION_RNG] instruction_d; // D stage instruction to be decoded
reg [`LM32_INSTRUCTION_RNG] instruction_d;
/////////////////////////////////////////////////////
// Internal nets and registers
/////////////////////////////////////////////////////
reg [`LM32_PC_RNG] pc_a; // A stage PC
`ifdef LM32_CACHE_ENABLED
reg [`LM32_PC_RNG] restart_address; // Address to restart from after a cache miss
`endif
`ifdef CFG_ICACHE_ENABLED
wire icache_read_enable_f; // Indicates if instruction cache miss is valid
wire [`LM32_PC_RNG] icache_refill_address; // Address that caused cache miss
reg icache_refill_ready; // Indicates when next word of refill data is ready to be written to cache
reg [`LM32_INSTRUCTION_RNG] icache_refill_data; // Next word of refill data, fetched from Wishbone
wire [`LM32_INSTRUCTION_RNG] icache_data_f; // Instruction fetched from instruction cache
wire [`LM32_CTYPE_RNG] first_cycle_type; // First Wishbone cycle type
wire [`LM32_CTYPE_RNG] next_cycle_type; // Next Wishbone cycle type
wire last_word; // Indicates if this is the last word in the cache line
wire [`LM32_PC_RNG] first_address; // First cache refill address
`else
`ifdef CFG_IWB_ENABLED
reg [`LM32_INSTRUCTION_RNG] wb_data_f; // Instruction fetched from Wishbone
`endif
`endif
`ifdef CFG_IROM_ENABLED
wire irom_select_a; // Indicates if A stage PC maps to a ROM address
reg irom_select_f; // Indicates if F stage PC maps to a ROM address
wire [`LM32_INSTRUCTION_RNG] irom_data_f; // Instruction fetched from ROM
`endif
`ifdef CFG_EBR_POSEDGE_REGISTER_FILE
`else
wire [`LM32_INSTRUCTION_RNG] instruction_f; // F stage instruction
`endif
`ifdef CFG_BUS_ERRORS_ENABLED
reg bus_error_f; // Indicates if a bus error occured while fetching the instruction in the F stage
`endif
`ifdef CFG_HW_DEBUG_ENABLED
reg jtag_access; // Indicates if a JTAG WB access is in progress
`endif
`ifdef CFG_ALTERNATE_EBA
reg alternate_eba_taken;
`endif
/////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////
`include "lm32_functions.v"
/////////////////////////////////////////////////////
// Instantiations
/////////////////////////////////////////////////////
// Instruction ROM
`ifdef CFG_IROM_ENABLED
pmi_ram_dp_true
#(
// ----- Parameters -------
.pmi_family (`LATTICE_FAMILY),
//.pmi_addr_depth_a (1 << (clogb2(`CFG_IROM_LIMIT/4-`CFG_IROM_BASE_ADDRESS/4+1)-1)),
//.pmi_addr_width_a ((clogb2(`CFG_IROM_LIMIT/4-`CFG_IROM_BASE_ADDRESS/4+1)-1)),
//.pmi_data_width_a (`LM32_WORD_WIDTH),
//.pmi_addr_depth_b (1 << (clogb2(`CFG_IROM_LIMIT/4-`CFG_IROM_BASE_ADDRESS/4+1)-1)),
//.pmi_addr_width_b ((clogb2(`CFG_IROM_LIMIT/4-`CFG_IROM_BASE_ADDRESS/4+1)-1)),
//.pmi_data_width_b (`LM32_WORD_WIDTH),
.pmi_addr_depth_a (`CFG_IROM_LIMIT/4-`CFG_IROM_BASE_ADDRESS/4+1),
.pmi_addr_width_a (clogb2_v1(`CFG_IROM_LIMIT/4-`CFG_IROM_BASE_ADDRESS/4+1)),
.pmi_data_width_a (`LM32_WORD_WIDTH),
.pmi_addr_depth_b (`CFG_IROM_LIMIT/4-`CFG_IROM_BASE_ADDRESS/4+1),
.pmi_addr_width_b (clogb2_v1(`CFG_IROM_LIMIT/4-`CFG_IROM_BASE_ADDRESS/4+1)),
.pmi_data_width_b (`LM32_WORD_WIDTH),
.pmi_regmode_a ("noreg"),
.pmi_regmode_b ("noreg"),
.pmi_gsr ("enable"),
.pmi_resetmode ("sync"),
.pmi_init_file (`CFG_IROM_INIT_FILE),
.pmi_init_file_format (`CFG_IROM_INIT_FILE_FORMAT),
.module_type ("pmi_ram_dp_true")
)
ram (
// ----- Inputs -------
.ClockA (clk_i),
.ClockB (clk_i),
.ResetA (rst_i),
.ResetB (rst_i),
.DataInA ({32{1'b0}}),
.DataInB (irom_store_data_m),
.AddressA (pc_a[clogb2_v1(`CFG_IROM_LIMIT/4-`CFG_IROM_BASE_ADDRESS/4+1)+2-1:2]),
.AddressB (irom_address_xm[clogb2_v1(`CFG_IROM_LIMIT/4-`CFG_IROM_BASE_ADDRESS/4+1)+2-1:2]),
.ClockEnA (!stall_a),
.ClockEnB (!stall_x || !stall_m),
.WrA (`FALSE),
.WrB (irom_we_xm),
// ----- Outputs -------
.QA (irom_data_f),
.QB (irom_data_m)
);
`endif
`ifdef CFG_ICACHE_ENABLED
// Instruction cache
lm32_icache #(
.associativity (associativity),
.sets (sets),
.bytes_per_line (bytes_per_line),
.base_address (base_address),
.limit (limit)
) icache (
// ----- Inputs -----
.clk_i (clk_i),
.rst_i (rst_i),
.stall_a (stall_a),
.stall_f (stall_f),
.branch_predict_taken_d (branch_predict_taken_d),
.valid_d (valid_d),
.address_a (pc_a),
.address_f (pc_f),
.read_enable_f (icache_read_enable_f),
.refill_ready (icache_refill_ready),
.refill_data (icache_refill_data),
.iflush (iflush),
// ----- Outputs -----
.stall_request (icache_stall_request),
.restart_request (icache_restart_request),
.refill_request (icache_refill_request),
.refill_address (icache_refill_address),
.refilling (icache_refilling),
.inst (icache_data_f)
);
`endif
/////////////////////////////////////////////////////
// Combinational Logic
/////////////////////////////////////////////////////
`ifdef CFG_ICACHE_ENABLED
// Generate signal that indicates when instruction cache misses are valid
assign icache_read_enable_f = (valid_f == `TRUE)
&& (kill_f == `FALSE)
`ifdef CFG_DCACHE_ENABLED
&& (dcache_restart_request == `FALSE)
`endif
`ifdef CFG_IROM_ENABLED
&& (irom_select_f == `FALSE)
`endif
;
`endif
// Compute address of next instruction to fetch
always @(*)
begin
// The request from the latest pipeline stage must take priority
`ifdef CFG_DCACHE_ENABLED
if (dcache_restart_request == `TRUE)
pc_a = restart_address;
else
`endif
if (branch_taken_m == `TRUE)
if ((branch_mispredict_taken_m == `TRUE) && (exception_m == `FALSE))
pc_a = pc_x;
else
pc_a = branch_target_m;
`ifdef CFG_FAST_UNCONDITIONAL_BRANCH
else if (branch_taken_x == `TRUE)
pc_a = branch_target_x;
`endif
else
if ( (valid_d == `TRUE) && (branch_predict_taken_d == `TRUE) )
pc_a = branch_predict_address_d;
else
`ifdef CFG_ICACHE_ENABLED
if (icache_restart_request == `TRUE)
pc_a = restart_address;
else
`endif
pc_a = pc_f + 1'b1;
end
// Select where instruction should be fetched from
`ifdef CFG_IROM_ENABLED
assign irom_select_a = ({pc_a, 2'b00} >= `CFG_IROM_BASE_ADDRESS) && ({pc_a, 2'b00} <= `CFG_IROM_LIMIT);
`endif
// Select instruction from selected source
`ifdef CFG_ICACHE_ENABLED
`ifdef CFG_IROM_ENABLED
assign instruction_f = irom_select_f == `TRUE ? irom_data_f : icache_data_f;
`else
assign instruction_f = icache_data_f;
`endif
`else
`ifdef CFG_IROM_ENABLED
`ifdef CFG_IWB_ENABLED
assign instruction_f = irom_select_f == `TRUE ? irom_data_f : wb_data_f;
`else
assign instruction_f = irom_data_f;
`endif
`else
assign instruction_f = wb_data_f;
`endif
`endif
// Unused/constant Wishbone signals
`ifdef CFG_IWB_ENABLED
`ifdef CFG_HW_DEBUG_ENABLED
`else
assign i_dat_o = 32'd0;
assign i_we_o = `FALSE;
assign i_sel_o = 4'b1111;
`endif
assign i_bte_o = `LM32_BTYPE_LINEAR;
`endif
`ifdef CFG_ICACHE_ENABLED
// Determine parameters for next cache refill Wishbone access
generate
case (bytes_per_line)
4:
begin
assign first_cycle_type = `LM32_CTYPE_END;
assign next_cycle_type = `LM32_CTYPE_END;
assign last_word = `TRUE;
assign first_address = icache_refill_address;
end
8:
begin
assign first_cycle_type = `LM32_CTYPE_INCREMENTING;
assign next_cycle_type = `LM32_CTYPE_END;
assign last_word = i_adr_o[addr_offset_msb:addr_offset_lsb] == 1'b1;
assign first_address = {icache_refill_address[`LM32_PC_WIDTH+2-1:addr_offset_msb+1], {addr_offset_width{1'b0}}};
end
16:
begin
assign first_cycle_type = `LM32_CTYPE_INCREMENTING;
assign next_cycle_type = i_adr_o[addr_offset_msb] == 1'b1 ? `LM32_CTYPE_END : `LM32_CTYPE_INCREMENTING;
assign last_word = i_adr_o[addr_offset_msb:addr_offset_lsb] == 2'b11;
assign first_address = {icache_refill_address[`LM32_PC_WIDTH+2-1:addr_offset_msb+1], {addr_offset_width{1'b0}}};
end
endcase
endgenerate
`endif
/////////////////////////////////////////////////////
// Sequential Logic
/////////////////////////////////////////////////////
// PC
always @(posedge clk_i `CFG_RESET_SENSITIVITY)
begin
if (rst_i == `TRUE)
begin
`ifdef CFG_DEBUG_ENABLED
`ifdef CFG_ALTERNATE_EBA
if (at_debug == `TRUE)
pc_f <= #1 (`CFG_DEBA_RESET-4)/4;
else
pc_f <= #1 (`CFG_EBA_RESET-4)/4;
`else
pc_f <= #1 (`CFG_EBA_RESET-4)/4;
`endif
`else
pc_f <= #1 (`CFG_EBA_RESET-4)/4;
`endif
pc_d <= #1 {`LM32_PC_WIDTH{1'b0}};
pc_x <= #1 {`LM32_PC_WIDTH{1'b0}};
pc_m <= #1 {`LM32_PC_WIDTH{1'b0}};
pc_w <= #1 {`LM32_PC_WIDTH{1'b0}};
end
else
begin
if (stall_f == `FALSE)
pc_f <= #1 pc_a;
if (stall_d == `FALSE)
pc_d <= #1 pc_f;
if (stall_x == `FALSE)
pc_x <= #1 pc_d;
if (stall_m == `FALSE)
pc_m <= #1 pc_x;
pc_w <= #1 pc_m;
end
end
`ifdef LM32_CACHE_ENABLED
// Address to restart from after a cache miss has been handled
always @(posedge clk_i `CFG_RESET_SENSITIVITY)
begin
if (rst_i == `TRUE)
restart_address <= #1 {`LM32_PC_WIDTH{1'b0}};
else
begin
`ifdef CFG_DCACHE_ENABLED
`ifdef CFG_ICACHE_ENABLED
// D-cache restart address must take priority, otherwise instructions will be lost
if (dcache_refill_request == `TRUE)
restart_address <= #1 pc_w;
else if ((icache_refill_request == `TRUE) && (!dcache_refilling) && (!dcache_restart_request))
restart_address <= #1 icache_refill_address;
`else
if (dcache_refill_request == `TRUE)
restart_address <= #1 pc_w;
`endif
`else
`ifdef CFG_ICACHE_ENABLED
if (icache_refill_request == `TRUE)
restart_address <= #1 icache_refill_address;
`endif
`endif
end
end
`endif
// Record where instruction was fetched from
`ifdef CFG_IROM_ENABLED
always @(posedge clk_i `CFG_RESET_SENSITIVITY)
begin
if (rst_i == `TRUE)
irom_select_f <= #1 `FALSE;
else
begin
if (stall_f == `FALSE)
irom_select_f <= #1 irom_select_a;
end
end
`endif
`ifdef CFG_HW_DEBUG_ENABLED
assign jtag_access_complete = (i_cyc_o == `TRUE) && ((i_ack_i == `TRUE) || (i_err_i == `TRUE)) && (jtag_access == `TRUE);
always @(*)
begin
case (jtag_address[1:0])
2'b00: jtag_read_data = i_dat_i[`LM32_BYTE_3_RNG];
2'b01: jtag_read_data = i_dat_i[`LM32_BYTE_2_RNG];
2'b10: jtag_read_data = i_dat_i[`LM32_BYTE_1_RNG];
2'b11: jtag_read_data = i_dat_i[`LM32_BYTE_0_RNG];
endcase
end
`endif
`ifdef CFG_IWB_ENABLED
// Instruction Wishbone interface
`ifdef CFG_ICACHE_ENABLED
always @(posedge clk_i `CFG_RESET_SENSITIVITY)
begin
if (rst_i == `TRUE)
begin
i_cyc_o <= #1 `FALSE;
i_stb_o <= #1 `FALSE;
i_adr_o <= #1 {`LM32_WORD_WIDTH{1'b0}};
i_cti_o <= #1 `LM32_CTYPE_END;
i_lock_o <= #1 `FALSE;
icache_refill_data <= #1 {`LM32_INSTRUCTION_WIDTH{1'b0}};
icache_refill_ready <= #1 `FALSE;
`ifdef CFG_BUS_ERRORS_ENABLED
bus_error_f <= #1 `FALSE;
`endif
`ifdef CFG_HW_DEBUG_ENABLED
i_we_o <= #1 `FALSE;
i_sel_o <= #1 4'b1111;
jtag_access <= #1 `FALSE;
`endif
end
else
begin
icache_refill_ready <= #1 `FALSE;
// Is a cycle in progress?
if (i_cyc_o == `TRUE)
begin
// Has cycle completed?
if ((i_ack_i == `TRUE) || (i_err_i == `TRUE))
begin
`ifdef CFG_HW_DEBUG_ENABLED
if (jtag_access == `TRUE)
begin
i_cyc_o <= #1 `FALSE;
i_stb_o <= #1 `FALSE;
i_we_o <= #1 `FALSE;
jtag_access <= #1 `FALSE;
end
else
`endif
begin
if (last_word == `TRUE)
begin
// Cache line fill complete
i_cyc_o <= #1 `FALSE;
i_stb_o <= #1 `FALSE;
i_lock_o <= #1 `FALSE;
end
// Fetch next word in cache line
i_adr_o[addr_offset_msb:addr_offset_lsb] <= #1 i_adr_o[addr_offset_msb:addr_offset_lsb] + 1'b1;
i_cti_o <= #1 next_cycle_type;
// Write fetched data into instruction cache
icache_refill_ready <= #1 `TRUE;
icache_refill_data <= #1 i_dat_i;
end
end
`ifdef CFG_BUS_ERRORS_ENABLED
if (i_err_i == `TRUE)
begin
bus_error_f <= #1 `TRUE;
$display ("Instruction bus error. Address: %x", i_adr_o);
end
`endif
end
else
begin
if ((icache_refill_request == `TRUE) && (icache_refill_ready == `FALSE))
begin
// Read first word of cache line
`ifdef CFG_HW_DEBUG_ENABLED
i_sel_o <= #1 4'b1111;
`endif
i_adr_o <= #1 {first_address, 2'b00};
i_cyc_o <= #1 `TRUE;
i_stb_o <= #1 `TRUE;
i_cti_o <= #1 first_cycle_type;
//i_lock_o <= #1 `TRUE;
`ifdef CFG_BUS_ERRORS_ENABLED
bus_error_f <= #1 `FALSE;
`endif
end
`ifdef CFG_HW_DEBUG_ENABLED
else
begin
if ((jtag_read_enable == `TRUE) || (jtag_write_enable == `TRUE))
begin
case (jtag_address[1:0])
2'b00: i_sel_o <= #1 4'b1000;
2'b01: i_sel_o <= #1 4'b0100;
2'b10: i_sel_o <= #1 4'b0010;
2'b11: i_sel_o <= #1 4'b0001;
endcase
i_adr_o <= #1 jtag_address;
i_dat_o <= #1 {4{jtag_write_data}};
i_cyc_o <= #1 `TRUE;
i_stb_o <= #1 `TRUE;
i_we_o <= #1 jtag_write_enable;
i_cti_o <= #1 `LM32_CTYPE_END;
jtag_access <= #1 `TRUE;
end
end
`endif
`ifdef CFG_BUS_ERRORS_ENABLED
// Clear bus error when exception taken, otherwise they would be
// continually generated if exception handler is cached
`ifdef CFG_FAST_UNCONDITIONAL_BRANCH
if (branch_taken_x == `TRUE)
bus_error_f <= #1 `FALSE;
`endif
if (branch_taken_m == `TRUE)
bus_error_f <= #1 `FALSE;
`endif
end
end
end
`else
always @(posedge clk_i `CFG_RESET_SENSITIVITY)
begin
if (rst_i == `TRUE)
begin
i_cyc_o <= #1 `FALSE;
i_stb_o <= #1 `FALSE;
i_adr_o <= #1 {`LM32_WORD_WIDTH{1'b0}};
i_cti_o <= #1 `LM32_CTYPE_END;
i_lock_o <= #1 `FALSE;
wb_data_f <= #1 {`LM32_INSTRUCTION_WIDTH{1'b0}};
`ifdef CFG_BUS_ERRORS_ENABLED
bus_error_f <= #1 `FALSE;
`endif
end
else
begin
// Is a cycle in progress?
if (i_cyc_o == `TRUE)
begin
// Has cycle completed?
if((i_ack_i == `TRUE) || (i_err_i == `TRUE))
begin
// Cycle complete
i_cyc_o <= #1 `FALSE;
i_stb_o <= #1 `FALSE;
// Register fetched instruction
wb_data_f <= #1 i_dat_i;
end
`ifdef CFG_BUS_ERRORS_ENABLED
if (i_err_i == `TRUE)
begin
bus_error_f <= #1 `TRUE;
$display ("Instruction bus error. Address: %x", i_adr_o);
end
`endif
end
else
begin
// Wait for an instruction fetch from an external address
if ( (stall_a == `FALSE)
`ifdef CFG_IROM_ENABLED
&& (irom_select_a == `FALSE)
`endif
)
begin
// Fetch instruction
`ifdef CFG_HW_DEBUG_ENABLED
i_sel_o <= #1 4'b1111;
`endif
i_adr_o <= #1 {pc_a, 2'b00};
i_cyc_o <= #1 `TRUE;
i_stb_o <= #1 `TRUE;
`ifdef CFG_BUS_ERRORS_ENABLED
bus_error_f <= #1 `FALSE;
`endif
end
else
begin
if ( (stall_a == `FALSE)
`ifdef CFG_IROM_ENABLED
&& (irom_select_a == `TRUE)
`endif
)
begin
`ifdef CFG_BUS_ERRORS_ENABLED
bus_error_f <= #1 `FALSE;
`endif
end
end
end
end
end
`endif
`endif
// Instruction register
always @(posedge clk_i `CFG_RESET_SENSITIVITY)
begin
if (rst_i == `TRUE)
begin
instruction_d <= #1 {`LM32_INSTRUCTION_WIDTH{1'b0}};
`ifdef CFG_BUS_ERRORS_ENABLED
bus_error_d <= #1 `FALSE;
`endif
end
else
begin
if (stall_d == `FALSE)
begin
instruction_d <= #1 instruction_f;
`ifdef CFG_BUS_ERRORS_ENABLED
bus_error_d <= #1 bus_error_f;
`endif
end
end
end
endmodule
|
module ps2_mouse_cmdout (
input clk,
input reset,
input [7:0] the_command,
input send_command,
input ps2_clk_posedge,
input ps2_clk_negedge,
inout ps2_clk,
inout ps2_dat,
output reg command_was_sent,
output reg error_communication_timed_out
);
// --------------------------------------------------------------------
// Parameter Declarations , 1/12.5mhz => 0.08us
// --------------------------------------------------------------------
parameter CLOCK_CYCLES_FOR_101US = 1262; // Timing info for initiating
parameter NUMBER_OF_BITS_FOR_101US = 13; // Host-to-Device communication
parameter COUNTER_INCREMENT_FOR_101US = 13'h0001; // when using a 12.5MHz system clock
parameter CLOCK_CYCLES_FOR_15MS = 187500; // Timing info for start of
parameter NUMBER_OF_BITS_FOR_15MS = 20; // transmission error when
parameter COUNTER_INCREMENT_FOR_15MS = 20'h00001; // using a 12.5MHz system clock
parameter CLOCK_CYCLES_FOR_2MS = 25000; // Timing info for sending
parameter NUMBER_OF_BITS_FOR_2MS = 17; // data error when
parameter COUNTER_INCREMENT_FOR_2MS = 17'h00001; // using a 12.5MHz system clock
// --------------------------------------------------------------------
// Constant Declarations
// --------------------------------------------------------------------
parameter PS2_STATE_0_IDLE = 3'h0,
PS2_STATE_1_INITIATE_COMMUNICATION = 3'h1,
PS2_STATE_2_WAIT_FOR_CLOCK = 3'h2,
PS2_STATE_3_TRANSMIT_DATA = 3'h3,
PS2_STATE_4_TRANSMIT_STOP_BIT = 3'h4,
PS2_STATE_5_RECEIVE_ACK_BIT = 3'h5,
PS2_STATE_6_COMMAND_WAS_SENT = 3'h6,
PS2_STATE_7_TRANSMISSION_ERROR = 3'h7;
// --------------------------------------------------------------------
// Internal wires and registers Declarations
// --------------------------------------------------------------------
reg [3:0] cur_bit; // Internal Registers
reg [8:0] ps2_command;
reg [NUMBER_OF_BITS_FOR_101US:1] command_initiate_counter;
reg [NUMBER_OF_BITS_FOR_15MS:1] waiting_counter;
reg [NUMBER_OF_BITS_FOR_2MS:1] transfer_counter;
reg [2:0] ns_ps2_transmitter; // State Machine Registers
reg [2:0] s_ps2_transmitter;
// --------------------------------------------------------------------
// Finite State Machine(s)
// --------------------------------------------------------------------
always @(posedge clk) begin
if(reset == 1'b1) s_ps2_transmitter <= PS2_STATE_0_IDLE;
else s_ps2_transmitter <= ns_ps2_transmitter;
end
always @(*) begin // Defaults
ns_ps2_transmitter = PS2_STATE_0_IDLE;
case (s_ps2_transmitter)
PS2_STATE_0_IDLE:
begin
if (send_command == 1'b1) ns_ps2_transmitter = PS2_STATE_1_INITIATE_COMMUNICATION;
else ns_ps2_transmitter = PS2_STATE_0_IDLE;
end
PS2_STATE_1_INITIATE_COMMUNICATION:
begin
if (command_initiate_counter == CLOCK_CYCLES_FOR_101US)
ns_ps2_transmitter = PS2_STATE_2_WAIT_FOR_CLOCK;
else
ns_ps2_transmitter = PS2_STATE_1_INITIATE_COMMUNICATION;
end
PS2_STATE_2_WAIT_FOR_CLOCK:
begin
if (ps2_clk_negedge == 1'b1)
ns_ps2_transmitter = PS2_STATE_3_TRANSMIT_DATA;
else if (waiting_counter == CLOCK_CYCLES_FOR_15MS)
ns_ps2_transmitter = PS2_STATE_7_TRANSMISSION_ERROR;
else
ns_ps2_transmitter = PS2_STATE_2_WAIT_FOR_CLOCK;
end
PS2_STATE_3_TRANSMIT_DATA:
begin
if ((cur_bit == 4'd8) && (ps2_clk_negedge == 1'b1))
ns_ps2_transmitter = PS2_STATE_4_TRANSMIT_STOP_BIT;
else if (transfer_counter == CLOCK_CYCLES_FOR_2MS)
ns_ps2_transmitter = PS2_STATE_7_TRANSMISSION_ERROR;
else
ns_ps2_transmitter = PS2_STATE_3_TRANSMIT_DATA;
end
PS2_STATE_4_TRANSMIT_STOP_BIT:
begin
if (ps2_clk_negedge == 1'b1)
ns_ps2_transmitter = PS2_STATE_5_RECEIVE_ACK_BIT;
else if (transfer_counter == CLOCK_CYCLES_FOR_2MS)
ns_ps2_transmitter = PS2_STATE_7_TRANSMISSION_ERROR;
else
ns_ps2_transmitter = PS2_STATE_4_TRANSMIT_STOP_BIT;
end
PS2_STATE_5_RECEIVE_ACK_BIT:
begin
if (ps2_clk_posedge == 1'b1)
ns_ps2_transmitter = PS2_STATE_6_COMMAND_WAS_SENT;
else if (transfer_counter == CLOCK_CYCLES_FOR_2MS)
ns_ps2_transmitter = PS2_STATE_7_TRANSMISSION_ERROR;
else
ns_ps2_transmitter = PS2_STATE_5_RECEIVE_ACK_BIT;
end
PS2_STATE_6_COMMAND_WAS_SENT:
begin
if (send_command == 1'b0)
ns_ps2_transmitter = PS2_STATE_0_IDLE;
else
ns_ps2_transmitter = PS2_STATE_6_COMMAND_WAS_SENT;
end
PS2_STATE_7_TRANSMISSION_ERROR:
begin
if (send_command == 1'b0)
ns_ps2_transmitter = PS2_STATE_0_IDLE;
else
ns_ps2_transmitter = PS2_STATE_7_TRANSMISSION_ERROR;
end
default:
begin
ns_ps2_transmitter = PS2_STATE_0_IDLE;
end
endcase
end
// --------------------------------------------------------------------
// Sequential logic
// --------------------------------------------------------------------
always @(posedge clk) begin
if(reset == 1'b1) ps2_command <= 9'h000;
else if(s_ps2_transmitter == PS2_STATE_0_IDLE)
ps2_command <= {(^the_command) ^ 1'b1, the_command};
end
always @(posedge clk) begin
if(reset == 1'b1) command_initiate_counter <= {NUMBER_OF_BITS_FOR_101US{1'b0}};
else if((s_ps2_transmitter == PS2_STATE_1_INITIATE_COMMUNICATION) &&
(command_initiate_counter != CLOCK_CYCLES_FOR_101US))
command_initiate_counter <=
command_initiate_counter + COUNTER_INCREMENT_FOR_101US;
else if(s_ps2_transmitter != PS2_STATE_1_INITIATE_COMMUNICATION)
command_initiate_counter <= {NUMBER_OF_BITS_FOR_101US{1'b0}};
end
always @(posedge clk) begin
if(reset == 1'b1) waiting_counter <= {NUMBER_OF_BITS_FOR_15MS{1'b0}};
else if((s_ps2_transmitter == PS2_STATE_2_WAIT_FOR_CLOCK) &&
(waiting_counter != CLOCK_CYCLES_FOR_15MS))
waiting_counter <= waiting_counter + COUNTER_INCREMENT_FOR_15MS;
else if(s_ps2_transmitter != PS2_STATE_2_WAIT_FOR_CLOCK)
waiting_counter <= {NUMBER_OF_BITS_FOR_15MS{1'b0}};
end
always @(posedge clk) begin
if(reset == 1'b1) transfer_counter <= {NUMBER_OF_BITS_FOR_2MS{1'b0}};
else begin
if((s_ps2_transmitter == PS2_STATE_3_TRANSMIT_DATA) ||
(s_ps2_transmitter == PS2_STATE_4_TRANSMIT_STOP_BIT) ||
(s_ps2_transmitter == PS2_STATE_5_RECEIVE_ACK_BIT))
begin
if(transfer_counter != CLOCK_CYCLES_FOR_2MS)
transfer_counter <= transfer_counter + COUNTER_INCREMENT_FOR_2MS;
end
else transfer_counter <= {NUMBER_OF_BITS_FOR_2MS{1'b0}};
end
end
always @(posedge clk) begin
if(reset == 1'b1) cur_bit <= 4'h0;
else if((s_ps2_transmitter == PS2_STATE_3_TRANSMIT_DATA) &&
(ps2_clk_negedge == 1'b1))
cur_bit <= cur_bit + 4'h1;
else if(s_ps2_transmitter != PS2_STATE_3_TRANSMIT_DATA)
cur_bit <= 4'h0;
end
always @(posedge clk) begin
if(reset == 1'b1) command_was_sent <= 1'b0;
else if(s_ps2_transmitter == PS2_STATE_6_COMMAND_WAS_SENT)
command_was_sent <= 1'b1;
else if(send_command == 1'b0) command_was_sent <= 1'b0;
end
always @(posedge clk) begin
if(reset == 1'b1) error_communication_timed_out <= 1'b0;
else if(s_ps2_transmitter == PS2_STATE_7_TRANSMISSION_ERROR)
error_communication_timed_out <= 1'b1;
else if(send_command == 1'b0)
error_communication_timed_out <= 1'b0;
end
// --------------------------------------------------------------------
// Combinational logic
// --------------------------------------------------------------------
assign ps2_clk = (s_ps2_transmitter == PS2_STATE_1_INITIATE_COMMUNICATION) ? 1'b0 : 1'bz;
assign ps2_dat = (s_ps2_transmitter == PS2_STATE_3_TRANSMIT_DATA) ? ps2_command[cur_bit] :
(s_ps2_transmitter == PS2_STATE_2_WAIT_FOR_CLOCK) ? 1'b0 :
((s_ps2_transmitter == PS2_STATE_1_INITIATE_COMMUNICATION) &&
(command_initiate_counter[NUMBER_OF_BITS_FOR_101US] == 1'b1)) ? 1'b0 : 1'bz;
endmodule
|
module SNPS_CLOCK_GATE_HIGH_Up_counter_COUNTER_WIDTH4_32 ( CLK, EN, ENCLK, TE
);
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("CORDIC_Arch3v1_ASIC_fpu_syn_constraints_clk20.tcl_GATED_syn.sdf");
endmodule
|
module SNPS_CLOCK_GATE_HIGH_d_ff_en_W32_0_21 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("CORDIC_Arch3v1_ASIC_fpu_syn_constraints_clk20.tcl_GATED_syn.sdf");
endmodule
|
module SNPS_CLOCK_GATE_HIGH_d_ff_en_W32_0_23 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("CORDIC_Arch3v1_ASIC_fpu_syn_constraints_clk20.tcl_GATED_syn.sdf");
endmodule
|
module SNPS_CLOCK_GATE_HIGH_d_ff_en_W32_0_24 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("CORDIC_Arch3v1_ASIC_fpu_syn_constraints_clk20.tcl_GATED_syn.sdf");
endmodule
|
module SNPS_CLOCK_GATE_HIGH_d_ff_en_W32_0_26 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("CORDIC_Arch3v1_ASIC_fpu_syn_constraints_clk20.tcl_GATED_syn.sdf");
endmodule
|
module SNPS_CLOCK_GATE_HIGH_d_ff_en_W32_0_27 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("CORDIC_Arch3v1_ASIC_fpu_syn_constraints_clk20.tcl_GATED_syn.sdf");
endmodule
|
module SNPS_CLOCK_GATE_HIGH_d_ff_en_W32_0_29 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("CORDIC_Arch3v1_ASIC_fpu_syn_constraints_clk20.tcl_GATED_syn.sdf");
endmodule
|
module SNPS_CLOCK_GATE_HIGH_d_ff_en_W32_0_32 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("CORDIC_Arch3v1_ASIC_fpu_syn_constraints_clk20.tcl_GATED_syn.sdf");
endmodule
|
module CORDIC_Arch3v1_W32_EW8_SW23_SWR26_EWR5 ( clk, rst, beg_fsm_cordic,
ack_cordic, operation, data_in, shift_region_flag, ready_cordic,
data_output, beg_add_subt, add_subt_dataA, add_subt_dataB,
result_add_subt, op_add_subt, ready_add_subt, enab_cont_iter );
input [31:0] data_in;
input [1:0] shift_region_flag;
output [31:0] data_output;
output [31:0] add_subt_dataA;
output [31:0] add_subt_dataB;
input [31:0] result_add_subt;
input clk, rst, beg_fsm_cordic, ack_cordic, operation, ready_add_subt;
output ready_cordic, beg_add_subt, op_add_subt, enab_cont_iter;
wire enab_d_ff4_Zn, enab_d_ff_RB1, enab_RB3, enab_d_ff5_data_out,
d_ff1_operation_out, d_ff1_shift_region_flag_out_0_, d_ff3_sign_out,
enab_d_ff4_Yn, enab_d_ff4_Xn, fmtted_Result_31_, ITER_CONT_net3608262,
ITER_CONT_N5, ITER_CONT_N4, ITER_CONT_N3, d_ff5_data_out_net3608226,
reg_Z0_net3608226, reg_val_muxZ_2stage_net3608226,
reg_shift_y_net3608226, d_ff4_Xn_net3608226, d_ff4_Yn_net3608226,
d_ff4_Zn_net3608226, n154, n518, n519, n520, n521, n522, n523, n524,
n525, n526, n527, n528, n529, n531, n532, n533, n534, n535, n536,
n537, intadd_421_CI, intadd_421_n3, intadd_421_n2, intadd_421_n1,
intadd_422_CI, intadd_422_n3, intadd_422_n2, intadd_422_n1, n604,
n605, n606, n607, n608, n609, n610, n611, n612, n613, n614, n615,
n616, n617, n618, n619, n620, n621, n622, n623, n624, n625, n626,
n627, n628, n629, n630, n631, n632, n633, n634, n635, n636, n637,
n638, n639, n640, n641, n642, n643, n644, n645, n646, n647, n648,
n649, n650, n651, n652, n653, n654, n655, n656, n657, n658, n659,
n660, n661, n662, n663, n664, n665, n666, n667, n668, n669, n670,
n671, n672, n673, n674, n675, n676, n677, n678, n679, n680, n681,
n682, n683, n684, n685, n686, n687, n688, n689, n690, n691, n692,
n693, n694, n695, n696, n697, n698, n699, n700, n701, n702, n703,
n704, n705, n706, n707, n708, n709, n710, n711, n712, n713, n714,
n715, n716, n717, n718, n719, n720, n721, n722, n723, n724, n725,
n726, n727, n728, n729, n730, n731, n732, n733, n734, n735, n736,
n737, n738, n739, n740, n741, n742, n743, n744, n745, n746, n747,
n748, n749, n750, n751, n752, n753, n754, n755, n756, n757, n758,
n759, n760, n761, n762, n763, n764, n765, n766, n767, n768, n769,
n770, n771, n772, n773, n774, n775, n776, n777, n778, n779, n780,
n781, n782, n783, n784, n785, n786, n787, n788, n789, n790, n791,
n792, n793, n794, n795;
wire [3:0] cont_iter_out;
wire [1:0] cont_var_out;
wire [31:0] d_ff1_Z;
wire [31:0] d_ff_Xn;
wire [31:0] first_mux_X;
wire [31:0] d_ff_Yn;
wire [31:0] first_mux_Y;
wire [31:0] d_ff_Zn;
wire [31:0] first_mux_Z;
wire [31:0] d_ff2_X;
wire [31:0] d_ff2_Y;
wire [31:0] d_ff2_Z;
wire [7:0] sh_exp_x;
wire [7:0] sh_exp_y;
wire [25:4] data_out_LUT;
wire [31:0] d_ff3_sh_x_out;
wire [31:0] d_ff3_sh_y_out;
wire [27:0] d_ff3_LUT_out;
wire [30:0] mux_sal;
wire [7:0] inst_CORDIC_FSM_v3_state_next;
wire [7:0] inst_CORDIC_FSM_v3_state_reg;
SNPS_CLOCK_GATE_HIGH_Up_counter_COUNTER_WIDTH4_32 ITER_CONT_clk_gate_temp_reg (
.CLK(clk), .EN(enab_cont_iter), .ENCLK(ITER_CONT_net3608262), .TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_d_ff_en_W32_0_21 d_ff5_data_out_clk_gate_Q_reg ( .CLK(
clk), .EN(enab_d_ff5_data_out), .ENCLK(d_ff5_data_out_net3608226),
.TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_d_ff_en_W32_0_32 reg_Z0_clk_gate_Q_reg ( .CLK(clk),
.EN(enab_d_ff_RB1), .ENCLK(reg_Z0_net3608226), .TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_d_ff_en_W32_0_29 reg_val_muxZ_2stage_clk_gate_Q_reg (
.CLK(clk), .EN(n612), .ENCLK(reg_val_muxZ_2stage_net3608226), .TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_d_ff_en_W32_0_27 reg_shift_y_clk_gate_Q_reg ( .CLK(clk),
.EN(enab_RB3), .ENCLK(reg_shift_y_net3608226), .TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_d_ff_en_W32_0_26 d_ff4_Xn_clk_gate_Q_reg ( .CLK(clk),
.EN(enab_d_ff4_Xn), .ENCLK(d_ff4_Xn_net3608226), .TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_d_ff_en_W32_0_24 d_ff4_Yn_clk_gate_Q_reg ( .CLK(clk),
.EN(enab_d_ff4_Yn), .ENCLK(d_ff4_Yn_net3608226), .TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_d_ff_en_W32_0_23 d_ff4_Zn_clk_gate_Q_reg ( .CLK(clk),
.EN(enab_d_ff4_Zn), .ENCLK(d_ff4_Zn_net3608226), .TE(1'b0) );
DFFRXLTS reg_region_flag_Q_reg_0_ ( .D(shift_region_flag[0]), .CK(
reg_Z0_net3608226), .RN(n793), .Q(d_ff1_shift_region_flag_out_0_),
.QN(n615) );
DFFRXLTS reg_region_flag_Q_reg_1_ ( .D(shift_region_flag[1]), .CK(
reg_Z0_net3608226), .RN(n793), .QN(n606) );
DFFRXLTS reg_LUT_Q_reg_0_ ( .D(n524), .CK(reg_shift_y_net3608226), .RN(n788),
.Q(d_ff3_LUT_out[0]) );
DFFRXLTS reg_LUT_Q_reg_1_ ( .D(n534), .CK(reg_shift_y_net3608226), .RN(n789),
.Q(d_ff3_LUT_out[1]) );
DFFRXLTS reg_LUT_Q_reg_2_ ( .D(n528), .CK(reg_shift_y_net3608226), .RN(n789),
.Q(d_ff3_LUT_out[2]) );
DFFRXLTS reg_LUT_Q_reg_3_ ( .D(n536), .CK(reg_shift_y_net3608226), .RN(n788),
.Q(d_ff3_LUT_out[3]) );
DFFRXLTS reg_LUT_Q_reg_4_ ( .D(data_out_LUT[4]), .CK(reg_shift_y_net3608226),
.RN(n793), .Q(d_ff3_LUT_out[4]) );
DFFRXLTS reg_LUT_Q_reg_5_ ( .D(n525), .CK(reg_shift_y_net3608226), .RN(n787),
.Q(d_ff3_LUT_out[5]) );
DFFRXLTS reg_LUT_Q_reg_6_ ( .D(n527), .CK(reg_shift_y_net3608226), .RN(n792),
.Q(d_ff3_LUT_out[6]) );
DFFRXLTS reg_LUT_Q_reg_7_ ( .D(n531), .CK(reg_shift_y_net3608226), .RN(n793),
.Q(d_ff3_LUT_out[7]) );
DFFRXLTS reg_LUT_Q_reg_8_ ( .D(n761), .CK(reg_shift_y_net3608226), .RN(n793),
.Q(d_ff3_LUT_out[8]) );
DFFRXLTS reg_LUT_Q_reg_9_ ( .D(n533), .CK(reg_shift_y_net3608226), .RN(n788),
.Q(d_ff3_LUT_out[9]) );
DFFRXLTS reg_LUT_Q_reg_10_ ( .D(n526), .CK(reg_shift_y_net3608226), .RN(n793), .Q(d_ff3_LUT_out[10]) );
DFFRXLTS reg_LUT_Q_reg_12_ ( .D(n532), .CK(reg_shift_y_net3608226), .RN(n787), .Q(d_ff3_LUT_out[12]) );
DFFRXLTS reg_LUT_Q_reg_13_ ( .D(n523), .CK(reg_shift_y_net3608226), .RN(n785), .Q(d_ff3_LUT_out[13]) );
DFFRXLTS reg_LUT_Q_reg_15_ ( .D(n535), .CK(reg_shift_y_net3608226), .RN(n792), .Q(d_ff3_LUT_out[15]) );
DFFRXLTS reg_LUT_Q_reg_19_ ( .D(n537), .CK(reg_shift_y_net3608226), .RN(n789), .Q(d_ff3_LUT_out[19]) );
DFFRXLTS reg_LUT_Q_reg_21_ ( .D(n522), .CK(reg_shift_y_net3608226), .RN(n789), .Q(d_ff3_LUT_out[21]) );
DFFRXLTS reg_LUT_Q_reg_23_ ( .D(n521), .CK(reg_shift_y_net3608226), .RN(n788), .Q(d_ff3_LUT_out[23]) );
DFFRXLTS reg_LUT_Q_reg_24_ ( .D(n520), .CK(reg_shift_y_net3608226), .RN(n789), .Q(d_ff3_LUT_out[24]) );
DFFRXLTS reg_LUT_Q_reg_25_ ( .D(data_out_LUT[25]), .CK(
reg_shift_y_net3608226), .RN(n622), .Q(d_ff3_LUT_out[25]) );
DFFRXLTS reg_LUT_Q_reg_26_ ( .D(n529), .CK(reg_shift_y_net3608226), .RN(n794), .Q(d_ff3_LUT_out[26]) );
DFFRXLTS reg_Z0_Q_reg_0_ ( .D(data_in[0]), .CK(reg_Z0_net3608226), .RN(n622),
.Q(d_ff1_Z[0]) );
DFFRXLTS reg_Z0_Q_reg_1_ ( .D(data_in[1]), .CK(reg_Z0_net3608226), .RN(n786),
.Q(d_ff1_Z[1]) );
DFFRXLTS reg_Z0_Q_reg_2_ ( .D(data_in[2]), .CK(reg_Z0_net3608226), .RN(n784),
.Q(d_ff1_Z[2]) );
DFFRXLTS reg_Z0_Q_reg_3_ ( .D(data_in[3]), .CK(reg_Z0_net3608226), .RN(n783),
.Q(d_ff1_Z[3]) );
DFFRXLTS reg_Z0_Q_reg_4_ ( .D(data_in[4]), .CK(reg_Z0_net3608226), .RN(n791),
.Q(d_ff1_Z[4]) );
DFFRXLTS reg_Z0_Q_reg_5_ ( .D(data_in[5]), .CK(reg_Z0_net3608226), .RN(n794),
.Q(d_ff1_Z[5]) );
DFFRXLTS reg_Z0_Q_reg_6_ ( .D(data_in[6]), .CK(reg_Z0_net3608226), .RN(n622),
.Q(d_ff1_Z[6]) );
DFFRXLTS reg_Z0_Q_reg_7_ ( .D(data_in[7]), .CK(reg_Z0_net3608226), .RN(n786),
.Q(d_ff1_Z[7]) );
DFFRXLTS reg_Z0_Q_reg_8_ ( .D(data_in[8]), .CK(reg_Z0_net3608226), .RN(n784),
.Q(d_ff1_Z[8]) );
DFFRXLTS reg_Z0_Q_reg_9_ ( .D(data_in[9]), .CK(reg_Z0_net3608226), .RN(n783),
.Q(d_ff1_Z[9]) );
DFFRXLTS reg_Z0_Q_reg_10_ ( .D(data_in[10]), .CK(reg_Z0_net3608226), .RN(
n790), .Q(d_ff1_Z[10]) );
DFFRXLTS reg_Z0_Q_reg_11_ ( .D(data_in[11]), .CK(reg_Z0_net3608226), .RN(
n788), .Q(d_ff1_Z[11]) );
DFFRXLTS reg_Z0_Q_reg_12_ ( .D(data_in[12]), .CK(reg_Z0_net3608226), .RN(
n789), .Q(d_ff1_Z[12]) );
DFFRXLTS reg_Z0_Q_reg_13_ ( .D(data_in[13]), .CK(reg_Z0_net3608226), .RN(
n787), .Q(d_ff1_Z[13]) );
DFFRXLTS reg_Z0_Q_reg_14_ ( .D(data_in[14]), .CK(reg_Z0_net3608226), .RN(
n785), .Q(d_ff1_Z[14]) );
DFFRXLTS reg_Z0_Q_reg_15_ ( .D(data_in[15]), .CK(reg_Z0_net3608226), .RN(
n792), .Q(d_ff1_Z[15]) );
DFFRXLTS reg_Z0_Q_reg_16_ ( .D(data_in[16]), .CK(reg_Z0_net3608226), .RN(
n790), .Q(d_ff1_Z[16]) );
DFFRXLTS reg_Z0_Q_reg_17_ ( .D(data_in[17]), .CK(reg_Z0_net3608226), .RN(
n789), .Q(d_ff1_Z[17]) );
DFFRXLTS reg_Z0_Q_reg_18_ ( .D(data_in[18]), .CK(reg_Z0_net3608226), .RN(
n788), .Q(d_ff1_Z[18]) );
DFFRXLTS reg_Z0_Q_reg_19_ ( .D(data_in[19]), .CK(reg_Z0_net3608226), .RN(
n790), .Q(d_ff1_Z[19]) );
DFFRXLTS reg_Z0_Q_reg_20_ ( .D(data_in[20]), .CK(reg_Z0_net3608226), .RN(
n787), .Q(d_ff1_Z[20]) );
DFFRXLTS reg_Z0_Q_reg_21_ ( .D(data_in[21]), .CK(reg_Z0_net3608226), .RN(
n785), .Q(d_ff1_Z[21]) );
DFFRXLTS reg_Z0_Q_reg_22_ ( .D(data_in[22]), .CK(reg_Z0_net3608226), .RN(
n790), .Q(d_ff1_Z[22]) );
DFFRXLTS reg_Z0_Q_reg_23_ ( .D(data_in[23]), .CK(reg_Z0_net3608226), .RN(
n787), .Q(d_ff1_Z[23]) );
DFFRXLTS reg_Z0_Q_reg_24_ ( .D(data_in[24]), .CK(reg_Z0_net3608226), .RN(
n785), .Q(d_ff1_Z[24]) );
DFFRXLTS reg_Z0_Q_reg_25_ ( .D(data_in[25]), .CK(reg_Z0_net3608226), .RN(
n792), .Q(d_ff1_Z[25]) );
DFFRXLTS reg_Z0_Q_reg_26_ ( .D(data_in[26]), .CK(reg_Z0_net3608226), .RN(
n789), .Q(d_ff1_Z[26]) );
DFFRXLTS reg_Z0_Q_reg_27_ ( .D(data_in[27]), .CK(reg_Z0_net3608226), .RN(
n790), .Q(d_ff1_Z[27]) );
DFFRXLTS reg_Z0_Q_reg_28_ ( .D(data_in[28]), .CK(reg_Z0_net3608226), .RN(
n788), .Q(d_ff1_Z[28]) );
DFFRXLTS reg_Z0_Q_reg_29_ ( .D(data_in[29]), .CK(reg_Z0_net3608226), .RN(
n793), .Q(d_ff1_Z[29]) );
DFFRXLTS reg_Z0_Q_reg_30_ ( .D(data_in[30]), .CK(reg_Z0_net3608226), .RN(
n787), .Q(d_ff1_Z[30]) );
DFFRXLTS reg_Z0_Q_reg_31_ ( .D(data_in[31]), .CK(reg_Z0_net3608226), .RN(
n785), .Q(d_ff1_Z[31]) );
DFFRXLTS reg_shift_x_Q_reg_23_ ( .D(sh_exp_x[0]), .CK(reg_shift_y_net3608226), .RN(n792), .Q(d_ff3_sh_x_out[23]) );
DFFRXLTS reg_shift_x_Q_reg_24_ ( .D(sh_exp_x[1]), .CK(reg_shift_y_net3608226), .RN(n790), .Q(d_ff3_sh_x_out[24]) );
DFFRXLTS reg_shift_x_Q_reg_25_ ( .D(sh_exp_x[2]), .CK(reg_shift_y_net3608226), .RN(n785), .Q(d_ff3_sh_x_out[25]) );
DFFRXLTS reg_shift_x_Q_reg_26_ ( .D(sh_exp_x[3]), .CK(reg_shift_y_net3608226), .RN(n792), .Q(d_ff3_sh_x_out[26]) );
DFFRXLTS reg_shift_x_Q_reg_27_ ( .D(sh_exp_x[4]), .CK(reg_shift_y_net3608226), .RN(n790), .Q(d_ff3_sh_x_out[27]) );
DFFRXLTS reg_shift_x_Q_reg_28_ ( .D(sh_exp_x[5]), .CK(reg_shift_y_net3608226), .RN(n790), .Q(d_ff3_sh_x_out[28]) );
DFFRXLTS reg_shift_x_Q_reg_29_ ( .D(sh_exp_x[6]), .CK(reg_shift_y_net3608226), .RN(n788), .Q(d_ff3_sh_x_out[29]) );
DFFRXLTS reg_shift_x_Q_reg_30_ ( .D(sh_exp_x[7]), .CK(reg_shift_y_net3608226), .RN(n789), .Q(d_ff3_sh_x_out[30]) );
DFFRXLTS reg_shift_y_Q_reg_23_ ( .D(sh_exp_y[0]), .CK(reg_shift_y_net3608226), .RN(n787), .Q(d_ff3_sh_y_out[23]) );
DFFRXLTS reg_shift_y_Q_reg_24_ ( .D(sh_exp_y[1]), .CK(reg_shift_y_net3608226), .RN(n785), .Q(d_ff3_sh_y_out[24]) );
DFFRXLTS reg_shift_y_Q_reg_25_ ( .D(sh_exp_y[2]), .CK(reg_shift_y_net3608226), .RN(n792), .Q(d_ff3_sh_y_out[25]) );
DFFRXLTS reg_shift_y_Q_reg_26_ ( .D(sh_exp_y[3]), .CK(reg_shift_y_net3608226), .RN(n793), .Q(d_ff3_sh_y_out[26]) );
DFFRXLTS reg_shift_y_Q_reg_27_ ( .D(sh_exp_y[4]), .CK(reg_shift_y_net3608226), .RN(n793), .Q(d_ff3_sh_y_out[27]) );
DFFRXLTS reg_shift_y_Q_reg_28_ ( .D(sh_exp_y[5]), .CK(reg_shift_y_net3608226), .RN(n793), .Q(d_ff3_sh_y_out[28]) );
DFFRXLTS reg_shift_y_Q_reg_29_ ( .D(sh_exp_y[6]), .CK(reg_shift_y_net3608226), .RN(n788), .Q(d_ff3_sh_y_out[29]) );
DFFRXLTS reg_shift_y_Q_reg_30_ ( .D(sh_exp_y[7]), .CK(reg_shift_y_net3608226), .RN(n793), .Q(d_ff3_sh_y_out[30]) );
DFFRXLTS d_ff4_Xn_Q_reg_0_ ( .D(result_add_subt[0]), .CK(d_ff4_Xn_net3608226), .RN(n787), .Q(d_ff_Xn[0]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_0_ ( .D(first_mux_X[0]), .CK(
reg_val_muxZ_2stage_net3608226), .RN(n785), .Q(d_ff2_X[0]) );
DFFRXLTS reg_shift_x_Q_reg_0_ ( .D(d_ff2_X[0]), .CK(reg_shift_y_net3608226),
.RN(n792), .Q(d_ff3_sh_x_out[0]) );
DFFRXLTS d_ff4_Xn_Q_reg_1_ ( .D(result_add_subt[1]), .CK(d_ff4_Xn_net3608226), .RN(n789), .Q(d_ff_Xn[1]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_1_ ( .D(first_mux_X[1]), .CK(
reg_val_muxZ_2stage_net3608226), .RN(n793), .Q(d_ff2_X[1]) );
DFFRXLTS reg_shift_x_Q_reg_1_ ( .D(d_ff2_X[1]), .CK(reg_shift_y_net3608226),
.RN(n788), .Q(d_ff3_sh_x_out[1]) );
DFFRXLTS d_ff4_Xn_Q_reg_2_ ( .D(result_add_subt[2]), .CK(d_ff4_Xn_net3608226), .RN(n789), .Q(d_ff_Xn[2]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_2_ ( .D(first_mux_X[2]), .CK(
reg_val_muxZ_2stage_net3608226), .RN(n787), .Q(d_ff2_X[2]) );
DFFRXLTS reg_shift_x_Q_reg_2_ ( .D(d_ff2_X[2]), .CK(reg_shift_y_net3608226),
.RN(n785), .Q(d_ff3_sh_x_out[2]) );
DFFRXLTS d_ff4_Xn_Q_reg_3_ ( .D(result_add_subt[3]), .CK(d_ff4_Xn_net3608226), .RN(n792), .Q(d_ff_Xn[3]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_3_ ( .D(first_mux_X[3]), .CK(
reg_val_muxZ_2stage_net3608226), .RN(n786), .Q(d_ff2_X[3]) );
DFFRXLTS reg_shift_x_Q_reg_3_ ( .D(d_ff2_X[3]), .CK(reg_shift_y_net3608226),
.RN(n784), .Q(d_ff3_sh_x_out[3]) );
DFFRXLTS d_ff4_Xn_Q_reg_4_ ( .D(result_add_subt[4]), .CK(d_ff4_Xn_net3608226), .RN(n783), .Q(d_ff_Xn[4]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_4_ ( .D(first_mux_X[4]), .CK(
reg_val_muxZ_2stage_net3608226), .RN(n791), .Q(d_ff2_X[4]) );
DFFRXLTS reg_shift_x_Q_reg_4_ ( .D(d_ff2_X[4]), .CK(reg_shift_y_net3608226),
.RN(n794), .Q(d_ff3_sh_x_out[4]) );
DFFRXLTS d_ff4_Xn_Q_reg_5_ ( .D(result_add_subt[5]), .CK(d_ff4_Xn_net3608226), .RN(n786), .Q(d_ff_Xn[5]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_5_ ( .D(first_mux_X[5]), .CK(
reg_val_muxZ_2stage_net3608226), .RN(n784), .Q(d_ff2_X[5]) );
DFFRXLTS reg_shift_x_Q_reg_5_ ( .D(d_ff2_X[5]), .CK(reg_shift_y_net3608226),
.RN(n783), .Q(d_ff3_sh_x_out[5]) );
DFFRXLTS d_ff4_Xn_Q_reg_6_ ( .D(result_add_subt[6]), .CK(d_ff4_Xn_net3608226), .RN(n791), .Q(d_ff_Xn[6]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_6_ ( .D(first_mux_X[6]), .CK(
reg_val_muxZ_2stage_net3608226), .RN(n794), .Q(d_ff2_X[6]) );
DFFRXLTS reg_shift_x_Q_reg_6_ ( .D(d_ff2_X[6]), .CK(reg_shift_y_net3608226),
.RN(n786), .Q(d_ff3_sh_x_out[6]) );
DFFRXLTS d_ff4_Xn_Q_reg_7_ ( .D(result_add_subt[7]), .CK(d_ff4_Xn_net3608226), .RN(n784), .Q(d_ff_Xn[7]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_7_ ( .D(first_mux_X[7]), .CK(
reg_val_muxZ_2stage_net3608226), .RN(n787), .Q(d_ff2_X[7]) );
DFFRXLTS reg_shift_x_Q_reg_7_ ( .D(d_ff2_X[7]), .CK(reg_shift_y_net3608226),
.RN(n785), .Q(d_ff3_sh_x_out[7]) );
DFFRXLTS d_ff4_Xn_Q_reg_8_ ( .D(result_add_subt[8]), .CK(d_ff4_Xn_net3608226), .RN(n792), .Q(d_ff_Xn[8]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_8_ ( .D(first_mux_X[8]), .CK(
reg_val_muxZ_2stage_net3608226), .RN(n790), .Q(d_ff2_X[8]) );
DFFRXLTS reg_shift_x_Q_reg_8_ ( .D(d_ff2_X[8]), .CK(reg_shift_y_net3608226),
.RN(n790), .Q(d_ff3_sh_x_out[8]) );
DFFRXLTS d_ff4_Xn_Q_reg_9_ ( .D(result_add_subt[9]), .CK(d_ff4_Xn_net3608226), .RN(n788), .Q(d_ff_Xn[9]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_9_ ( .D(first_mux_X[9]), .CK(
reg_val_muxZ_2stage_net3608226), .RN(n790), .Q(d_ff2_X[9]) );
DFFRXLTS reg_shift_x_Q_reg_9_ ( .D(d_ff2_X[9]), .CK(reg_shift_y_net3608226),
.RN(n787), .Q(d_ff3_sh_x_out[9]) );
DFFRXLTS d_ff4_Xn_Q_reg_10_ ( .D(result_add_subt[10]), .CK(
d_ff4_Xn_net3608226), .RN(n785), .Q(d_ff_Xn[10]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_10_ ( .D(first_mux_X[10]), .CK(
reg_val_muxZ_2stage_net3608226), .RN(n792), .Q(d_ff2_X[10]) );
DFFRXLTS reg_shift_x_Q_reg_10_ ( .D(d_ff2_X[10]), .CK(reg_shift_y_net3608226), .RN(n793), .Q(d_ff3_sh_x_out[10]) );
DFFRXLTS d_ff4_Xn_Q_reg_11_ ( .D(result_add_subt[11]), .CK(
d_ff4_Xn_net3608226), .RN(n793), .Q(d_ff_Xn[11]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_11_ ( .D(first_mux_X[11]), .CK(
reg_val_muxZ_2stage_net3608226), .RN(n791), .Q(d_ff2_X[11]) );
DFFRXLTS reg_shift_x_Q_reg_11_ ( .D(d_ff2_X[11]), .CK(reg_shift_y_net3608226), .RN(n794), .Q(d_ff3_sh_x_out[11]) );
DFFRXLTS d_ff4_Xn_Q_reg_12_ ( .D(result_add_subt[12]), .CK(
d_ff4_Xn_net3608226), .RN(n786), .Q(d_ff_Xn[12]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_12_ ( .D(first_mux_X[12]), .CK(
reg_val_muxZ_2stage_net3608226), .RN(n784), .Q(d_ff2_X[12]) );
DFFRXLTS reg_shift_x_Q_reg_12_ ( .D(d_ff2_X[12]), .CK(reg_shift_y_net3608226), .RN(n783), .Q(d_ff3_sh_x_out[12]) );
DFFRXLTS d_ff4_Xn_Q_reg_13_ ( .D(result_add_subt[13]), .CK(
d_ff4_Xn_net3608226), .RN(n791), .Q(d_ff_Xn[13]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_13_ ( .D(first_mux_X[13]), .CK(
reg_val_muxZ_2stage_net3608226), .RN(n794), .Q(d_ff2_X[13]) );
DFFRXLTS reg_shift_x_Q_reg_13_ ( .D(d_ff2_X[13]), .CK(reg_shift_y_net3608226), .RN(n786), .Q(d_ff3_sh_x_out[13]) );
DFFRXLTS d_ff4_Xn_Q_reg_14_ ( .D(result_add_subt[14]), .CK(
d_ff4_Xn_net3608226), .RN(n784), .Q(d_ff_Xn[14]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_14_ ( .D(first_mux_X[14]), .CK(
reg_val_muxZ_2stage_net3608226), .RN(n783), .Q(d_ff2_X[14]) );
DFFRXLTS reg_shift_x_Q_reg_14_ ( .D(d_ff2_X[14]), .CK(reg_shift_y_net3608226), .RN(n791), .Q(d_ff3_sh_x_out[14]) );
DFFRXLTS d_ff4_Xn_Q_reg_15_ ( .D(result_add_subt[15]), .CK(
d_ff4_Xn_net3608226), .RN(n794), .Q(d_ff_Xn[15]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_15_ ( .D(first_mux_X[15]), .CK(
reg_val_muxZ_2stage_net3608226), .RN(n791), .Q(d_ff2_X[15]) );
DFFRXLTS reg_shift_x_Q_reg_15_ ( .D(d_ff2_X[15]), .CK(reg_shift_y_net3608226), .RN(n794), .Q(d_ff3_sh_x_out[15]) );
DFFRXLTS d_ff4_Xn_Q_reg_16_ ( .D(result_add_subt[16]), .CK(
d_ff4_Xn_net3608226), .RN(n622), .Q(d_ff_Xn[16]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_16_ ( .D(first_mux_X[16]), .CK(
reg_val_muxZ_2stage_net3608226), .RN(n786), .Q(d_ff2_X[16]) );
DFFRXLTS reg_shift_x_Q_reg_16_ ( .D(d_ff2_X[16]), .CK(reg_shift_y_net3608226), .RN(n784), .Q(d_ff3_sh_x_out[16]) );
DFFRXLTS d_ff4_Xn_Q_reg_17_ ( .D(result_add_subt[17]), .CK(
d_ff4_Xn_net3608226), .RN(n783), .Q(d_ff_Xn[17]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_17_ ( .D(first_mux_X[17]), .CK(
reg_val_muxZ_2stage_net3608226), .RN(n791), .Q(d_ff2_X[17]) );
DFFRXLTS reg_shift_x_Q_reg_17_ ( .D(d_ff2_X[17]), .CK(reg_shift_y_net3608226), .RN(n794), .Q(d_ff3_sh_x_out[17]) );
DFFRXLTS d_ff4_Xn_Q_reg_18_ ( .D(result_add_subt[18]), .CK(
d_ff4_Xn_net3608226), .RN(n622), .Q(d_ff_Xn[18]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_18_ ( .D(first_mux_X[18]), .CK(
reg_val_muxZ_2stage_net3608226), .RN(n786), .Q(d_ff2_X[18]) );
DFFRXLTS reg_shift_x_Q_reg_18_ ( .D(d_ff2_X[18]), .CK(reg_shift_y_net3608226), .RN(n784), .Q(d_ff3_sh_x_out[18]) );
DFFRXLTS d_ff4_Xn_Q_reg_19_ ( .D(result_add_subt[19]), .CK(
d_ff4_Xn_net3608226), .RN(n783), .Q(d_ff_Xn[19]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_19_ ( .D(first_mux_X[19]), .CK(
reg_val_muxZ_2stage_net3608226), .RN(n622), .Q(d_ff2_X[19]) );
DFFRXLTS reg_shift_x_Q_reg_19_ ( .D(d_ff2_X[19]), .CK(reg_shift_y_net3608226), .RN(n775), .Q(d_ff3_sh_x_out[19]) );
DFFRXLTS d_ff4_Xn_Q_reg_20_ ( .D(result_add_subt[20]), .CK(
d_ff4_Xn_net3608226), .RN(n604), .Q(d_ff_Xn[20]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_20_ ( .D(first_mux_X[20]), .CK(
reg_val_muxZ_2stage_net3608226), .RN(n792), .Q(d_ff2_X[20]) );
DFFRXLTS reg_shift_x_Q_reg_20_ ( .D(d_ff2_X[20]), .CK(reg_shift_y_net3608226), .RN(n780), .Q(d_ff3_sh_x_out[20]) );
DFFRXLTS d_ff4_Xn_Q_reg_21_ ( .D(result_add_subt[21]), .CK(
d_ff4_Xn_net3608226), .RN(n779), .Q(d_ff_Xn[21]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_21_ ( .D(first_mux_X[21]), .CK(
reg_val_muxZ_2stage_net3608226), .RN(n775), .Q(d_ff2_X[21]) );
DFFRXLTS reg_shift_x_Q_reg_21_ ( .D(d_ff2_X[21]), .CK(reg_shift_y_net3608226), .RN(n604), .Q(d_ff3_sh_x_out[21]) );
DFFRXLTS d_ff4_Xn_Q_reg_22_ ( .D(result_add_subt[22]), .CK(
d_ff4_Xn_net3608226), .RN(n776), .Q(d_ff_Xn[22]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_22_ ( .D(first_mux_X[22]), .CK(
reg_val_muxZ_2stage_net3608226), .RN(n792), .Q(d_ff2_X[22]) );
DFFRXLTS reg_shift_x_Q_reg_22_ ( .D(d_ff2_X[22]), .CK(reg_shift_y_net3608226), .RN(n770), .Q(d_ff3_sh_x_out[22]) );
DFFRXLTS d_ff4_Xn_Q_reg_23_ ( .D(result_add_subt[23]), .CK(
d_ff4_Xn_net3608226), .RN(n775), .Q(d_ff_Xn[23]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_23_ ( .D(first_mux_X[23]), .CK(
reg_val_muxZ_2stage_net3608226), .RN(n777), .Q(d_ff2_X[23]), .QN(n616)
);
DFFRXLTS d_ff4_Xn_Q_reg_24_ ( .D(result_add_subt[24]), .CK(
d_ff4_Xn_net3608226), .RN(n780), .Q(d_ff_Xn[24]) );
DFFRXLTS d_ff4_Xn_Q_reg_25_ ( .D(result_add_subt[25]), .CK(
d_ff4_Xn_net3608226), .RN(n781), .Q(d_ff_Xn[25]) );
DFFRXLTS d_ff4_Xn_Q_reg_26_ ( .D(result_add_subt[26]), .CK(
d_ff4_Xn_net3608226), .RN(n776), .Q(d_ff_Xn[26]) );
DFFRXLTS d_ff4_Xn_Q_reg_27_ ( .D(result_add_subt[27]), .CK(
d_ff4_Xn_net3608226), .RN(n780), .Q(d_ff_Xn[27]) );
DFFRXLTS d_ff4_Xn_Q_reg_28_ ( .D(result_add_subt[28]), .CK(
d_ff4_Xn_net3608226), .RN(n781), .Q(d_ff_Xn[28]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_28_ ( .D(first_mux_X[28]), .CK(
reg_val_muxZ_2stage_net3608226), .RN(n777), .Q(d_ff2_X[28]), .QN(n768)
);
DFFRXLTS d_ff4_Xn_Q_reg_29_ ( .D(result_add_subt[29]), .CK(
d_ff4_Xn_net3608226), .RN(n777), .Q(d_ff_Xn[29]) );
DFFRXLTS d_ff4_Xn_Q_reg_30_ ( .D(result_add_subt[30]), .CK(
d_ff4_Xn_net3608226), .RN(n779), .Q(d_ff_Xn[30]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_30_ ( .D(first_mux_X[30]), .CK(
reg_val_muxZ_2stage_net3608226), .RN(n780), .Q(d_ff2_X[30]) );
DFFRXLTS d_ff4_Xn_Q_reg_31_ ( .D(result_add_subt[31]), .CK(
d_ff4_Xn_net3608226), .RN(n781), .Q(d_ff_Xn[31]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_31_ ( .D(first_mux_X[31]), .CK(
reg_val_muxZ_2stage_net3608226), .RN(n782), .Q(d_ff2_X[31]) );
DFFRXLTS reg_shift_x_Q_reg_31_ ( .D(d_ff2_X[31]), .CK(reg_shift_y_net3608226), .RN(n782), .Q(d_ff3_sh_x_out[31]) );
DFFRXLTS d_ff4_Yn_Q_reg_0_ ( .D(result_add_subt[0]), .CK(d_ff4_Yn_net3608226), .RN(n778), .Q(d_ff_Yn[0]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_0_ ( .D(first_mux_Y[0]), .CK(
reg_val_muxZ_2stage_net3608226), .RN(n776), .Q(d_ff2_Y[0]) );
DFFRXLTS reg_shift_y_Q_reg_0_ ( .D(d_ff2_Y[0]), .CK(reg_shift_y_net3608226),
.RN(n779), .Q(d_ff3_sh_y_out[0]) );
DFFRXLTS d_ff4_Yn_Q_reg_1_ ( .D(result_add_subt[1]), .CK(d_ff4_Yn_net3608226), .RN(n780), .Q(d_ff_Yn[1]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_1_ ( .D(first_mux_Y[1]), .CK(
reg_val_muxZ_2stage_net3608226), .RN(n781), .Q(d_ff2_Y[1]) );
DFFRXLTS reg_shift_y_Q_reg_1_ ( .D(d_ff2_Y[1]), .CK(reg_shift_y_net3608226),
.RN(n773), .Q(d_ff3_sh_y_out[1]) );
DFFRXLTS d_ff4_Yn_Q_reg_2_ ( .D(result_add_subt[2]), .CK(d_ff4_Yn_net3608226), .RN(n771), .Q(d_ff_Yn[2]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_2_ ( .D(first_mux_Y[2]), .CK(
reg_val_muxZ_2stage_net3608226), .RN(n621), .Q(d_ff2_Y[2]) );
DFFRXLTS reg_shift_y_Q_reg_2_ ( .D(d_ff2_Y[2]), .CK(reg_shift_y_net3608226),
.RN(n775), .Q(d_ff3_sh_y_out[2]) );
DFFRXLTS d_ff4_Yn_Q_reg_3_ ( .D(result_add_subt[3]), .CK(d_ff4_Yn_net3608226), .RN(n154), .Q(d_ff_Yn[3]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_3_ ( .D(first_mux_Y[3]), .CK(
reg_val_muxZ_2stage_net3608226), .RN(n774), .Q(d_ff2_Y[3]) );
DFFRXLTS reg_shift_y_Q_reg_3_ ( .D(d_ff2_Y[3]), .CK(reg_shift_y_net3608226),
.RN(n771), .Q(d_ff3_sh_y_out[3]) );
DFFRXLTS d_ff4_Yn_Q_reg_4_ ( .D(result_add_subt[4]), .CK(d_ff4_Yn_net3608226), .RN(n773), .Q(d_ff_Yn[4]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_4_ ( .D(first_mux_Y[4]), .CK(
reg_val_muxZ_2stage_net3608226), .RN(n621), .Q(d_ff2_Y[4]) );
DFFRXLTS reg_shift_y_Q_reg_4_ ( .D(d_ff2_Y[4]), .CK(reg_shift_y_net3608226),
.RN(n777), .Q(d_ff3_sh_y_out[4]) );
DFFRXLTS d_ff4_Yn_Q_reg_5_ ( .D(result_add_subt[5]), .CK(d_ff4_Yn_net3608226), .RN(n779), .Q(d_ff_Yn[5]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_5_ ( .D(first_mux_Y[5]), .CK(
reg_val_muxZ_2stage_net3608226), .RN(n780), .Q(d_ff2_Y[5]) );
DFFRXLTS reg_shift_y_Q_reg_5_ ( .D(d_ff2_Y[5]), .CK(reg_shift_y_net3608226),
.RN(n781), .Q(d_ff3_sh_y_out[5]) );
DFFRXLTS d_ff4_Yn_Q_reg_6_ ( .D(result_add_subt[6]), .CK(d_ff4_Yn_net3608226), .RN(n777), .Q(d_ff_Yn[6]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_6_ ( .D(first_mux_Y[6]), .CK(
reg_val_muxZ_2stage_net3608226), .RN(n777), .Q(d_ff2_Y[6]) );
DFFRXLTS reg_shift_y_Q_reg_6_ ( .D(d_ff2_Y[6]), .CK(reg_shift_y_net3608226),
.RN(n778), .Q(d_ff3_sh_y_out[6]) );
DFFRXLTS d_ff4_Yn_Q_reg_7_ ( .D(result_add_subt[7]), .CK(d_ff4_Yn_net3608226), .RN(n782), .Q(d_ff_Yn[7]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_7_ ( .D(first_mux_Y[7]), .CK(
reg_val_muxZ_2stage_net3608226), .RN(n779), .Q(d_ff2_Y[7]) );
DFFRXLTS reg_shift_y_Q_reg_7_ ( .D(d_ff2_Y[7]), .CK(reg_shift_y_net3608226),
.RN(n782), .Q(d_ff3_sh_y_out[7]) );
DFFRXLTS d_ff4_Yn_Q_reg_8_ ( .D(result_add_subt[8]), .CK(d_ff4_Yn_net3608226), .RN(n778), .Q(d_ff_Yn[8]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_8_ ( .D(first_mux_Y[8]), .CK(
reg_val_muxZ_2stage_net3608226), .RN(n777), .Q(d_ff2_Y[8]) );
DFFRXLTS reg_shift_y_Q_reg_8_ ( .D(d_ff2_Y[8]), .CK(reg_shift_y_net3608226),
.RN(n782), .Q(d_ff3_sh_y_out[8]) );
DFFRXLTS d_ff4_Yn_Q_reg_9_ ( .D(result_add_subt[9]), .CK(d_ff4_Yn_net3608226), .RN(n780), .Q(d_ff_Yn[9]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_9_ ( .D(first_mux_Y[9]), .CK(
reg_val_muxZ_2stage_net3608226), .RN(n781), .Q(d_ff2_Y[9]) );
DFFRXLTS reg_shift_y_Q_reg_9_ ( .D(d_ff2_Y[9]), .CK(reg_shift_y_net3608226),
.RN(n776), .Q(d_ff3_sh_y_out[9]) );
DFFRXLTS d_ff4_Yn_Q_reg_10_ ( .D(result_add_subt[10]), .CK(
d_ff4_Yn_net3608226), .RN(n776), .Q(d_ff_Yn[10]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_10_ ( .D(first_mux_Y[10]), .CK(
reg_val_muxZ_2stage_net3608226), .RN(n778), .Q(d_ff2_Y[10]) );
DFFRXLTS reg_shift_y_Q_reg_10_ ( .D(d_ff2_Y[10]), .CK(reg_shift_y_net3608226), .RN(n781), .Q(d_ff3_sh_y_out[10]) );
DFFRXLTS d_ff4_Yn_Q_reg_11_ ( .D(result_add_subt[11]), .CK(
d_ff4_Yn_net3608226), .RN(n777), .Q(d_ff_Yn[11]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_11_ ( .D(first_mux_Y[11]), .CK(
reg_val_muxZ_2stage_net3608226), .RN(n777), .Q(d_ff2_Y[11]) );
DFFRXLTS reg_shift_y_Q_reg_11_ ( .D(d_ff2_Y[11]), .CK(reg_shift_y_net3608226), .RN(n778), .Q(d_ff3_sh_y_out[11]) );
DFFRXLTS d_ff4_Yn_Q_reg_12_ ( .D(result_add_subt[12]), .CK(
d_ff4_Yn_net3608226), .RN(n777), .Q(d_ff_Yn[12]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_12_ ( .D(first_mux_Y[12]), .CK(
reg_val_muxZ_2stage_net3608226), .RN(n779), .Q(d_ff2_Y[12]) );
DFFRXLTS reg_shift_y_Q_reg_12_ ( .D(d_ff2_Y[12]), .CK(reg_shift_y_net3608226), .RN(n780), .Q(d_ff3_sh_y_out[12]) );
DFFRXLTS d_ff4_Yn_Q_reg_13_ ( .D(result_add_subt[13]), .CK(
d_ff4_Yn_net3608226), .RN(n781), .Q(d_ff_Yn[13]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_13_ ( .D(first_mux_Y[13]), .CK(
reg_val_muxZ_2stage_net3608226), .RN(n782), .Q(d_ff2_Y[13]) );
DFFRXLTS reg_shift_y_Q_reg_13_ ( .D(d_ff2_Y[13]), .CK(reg_shift_y_net3608226), .RN(n779), .Q(d_ff3_sh_y_out[13]) );
DFFRXLTS d_ff4_Yn_Q_reg_14_ ( .D(result_add_subt[14]), .CK(
d_ff4_Yn_net3608226), .RN(n780), .Q(d_ff_Yn[14]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_14_ ( .D(first_mux_Y[14]), .CK(
reg_val_muxZ_2stage_net3608226), .RN(n781), .Q(d_ff2_Y[14]) );
DFFRXLTS reg_shift_y_Q_reg_14_ ( .D(d_ff2_Y[14]), .CK(reg_shift_y_net3608226), .RN(n782), .Q(d_ff3_sh_y_out[14]) );
DFFRXLTS d_ff4_Yn_Q_reg_15_ ( .D(result_add_subt[15]), .CK(
d_ff4_Yn_net3608226), .RN(n782), .Q(d_ff_Yn[15]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_15_ ( .D(first_mux_Y[15]), .CK(
reg_val_muxZ_2stage_net3608226), .RN(n778), .Q(d_ff2_Y[15]) );
DFFRXLTS reg_shift_y_Q_reg_15_ ( .D(d_ff2_Y[15]), .CK(reg_shift_y_net3608226), .RN(n782), .Q(d_ff3_sh_y_out[15]) );
DFFRXLTS d_ff4_Yn_Q_reg_16_ ( .D(result_add_subt[16]), .CK(
d_ff4_Yn_net3608226), .RN(n779), .Q(d_ff_Yn[16]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_16_ ( .D(first_mux_Y[16]), .CK(
reg_val_muxZ_2stage_net3608226), .RN(n780), .Q(d_ff2_Y[16]) );
DFFRXLTS reg_shift_y_Q_reg_16_ ( .D(d_ff2_Y[16]), .CK(reg_shift_y_net3608226), .RN(n787), .Q(d_ff3_sh_y_out[16]) );
DFFRXLTS d_ff4_Yn_Q_reg_17_ ( .D(result_add_subt[17]), .CK(
d_ff4_Yn_net3608226), .RN(n774), .Q(d_ff_Yn[17]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_17_ ( .D(first_mux_Y[17]), .CK(
reg_val_muxZ_2stage_net3608226), .RN(n621), .Q(d_ff2_Y[17]) );
DFFRXLTS reg_shift_y_Q_reg_17_ ( .D(d_ff2_Y[17]), .CK(reg_shift_y_net3608226), .RN(n775), .Q(d_ff3_sh_y_out[17]) );
DFFRXLTS d_ff4_Yn_Q_reg_18_ ( .D(result_add_subt[18]), .CK(
d_ff4_Yn_net3608226), .RN(n621), .Q(d_ff_Yn[18]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_18_ ( .D(first_mux_Y[18]), .CK(
reg_val_muxZ_2stage_net3608226), .RN(n780), .Q(d_ff2_Y[18]) );
DFFRXLTS reg_shift_y_Q_reg_18_ ( .D(d_ff2_Y[18]), .CK(reg_shift_y_net3608226), .RN(n777), .Q(d_ff3_sh_y_out[18]) );
DFFRXLTS d_ff4_Yn_Q_reg_19_ ( .D(result_add_subt[19]), .CK(
d_ff4_Yn_net3608226), .RN(n781), .Q(d_ff_Yn[19]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_19_ ( .D(first_mux_Y[19]), .CK(
reg_val_muxZ_2stage_net3608226), .RN(n621), .Q(d_ff2_Y[19]) );
DFFRXLTS reg_shift_y_Q_reg_19_ ( .D(d_ff2_Y[19]), .CK(reg_shift_y_net3608226), .RN(n778), .Q(d_ff3_sh_y_out[19]) );
DFFRXLTS d_ff4_Yn_Q_reg_20_ ( .D(result_add_subt[20]), .CK(
d_ff4_Yn_net3608226), .RN(n782), .Q(d_ff_Yn[20]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_20_ ( .D(first_mux_Y[20]), .CK(
reg_val_muxZ_2stage_net3608226), .RN(n779), .Q(d_ff2_Y[20]) );
DFFRXLTS reg_shift_y_Q_reg_20_ ( .D(d_ff2_Y[20]), .CK(reg_shift_y_net3608226), .RN(n780), .Q(d_ff3_sh_y_out[20]) );
DFFRXLTS d_ff4_Yn_Q_reg_21_ ( .D(result_add_subt[21]), .CK(
d_ff4_Yn_net3608226), .RN(n781), .Q(d_ff_Yn[21]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_21_ ( .D(first_mux_Y[21]), .CK(
reg_val_muxZ_2stage_net3608226), .RN(n777), .Q(d_ff2_Y[21]) );
DFFRXLTS reg_shift_y_Q_reg_21_ ( .D(d_ff2_Y[21]), .CK(reg_shift_y_net3608226), .RN(n782), .Q(d_ff3_sh_y_out[21]) );
DFFRXLTS d_ff4_Yn_Q_reg_22_ ( .D(result_add_subt[22]), .CK(
d_ff4_Yn_net3608226), .RN(n778), .Q(d_ff_Yn[22]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_22_ ( .D(first_mux_Y[22]), .CK(
reg_val_muxZ_2stage_net3608226), .RN(n776), .Q(d_ff2_Y[22]) );
DFFRXLTS reg_shift_y_Q_reg_22_ ( .D(d_ff2_Y[22]), .CK(reg_shift_y_net3608226), .RN(n780), .Q(d_ff3_sh_y_out[22]) );
DFFRXLTS d_ff4_Yn_Q_reg_23_ ( .D(result_add_subt[23]), .CK(
d_ff4_Yn_net3608226), .RN(n621), .Q(d_ff_Yn[23]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_23_ ( .D(first_mux_Y[23]), .CK(
reg_val_muxZ_2stage_net3608226), .RN(n775), .Q(d_ff2_Y[23]), .QN(n767)
);
DFFRXLTS d_ff4_Yn_Q_reg_24_ ( .D(result_add_subt[24]), .CK(
d_ff4_Yn_net3608226), .RN(n782), .Q(d_ff_Yn[24]) );
DFFRXLTS d_ff4_Yn_Q_reg_25_ ( .D(result_add_subt[25]), .CK(
d_ff4_Yn_net3608226), .RN(n787), .Q(d_ff_Yn[25]) );
DFFRXLTS d_ff4_Yn_Q_reg_26_ ( .D(result_add_subt[26]), .CK(
d_ff4_Yn_net3608226), .RN(n781), .Q(d_ff_Yn[26]) );
DFFRXLTS d_ff4_Yn_Q_reg_27_ ( .D(result_add_subt[27]), .CK(
d_ff4_Yn_net3608226), .RN(n775), .Q(d_ff_Yn[27]) );
DFFRXLTS d_ff4_Yn_Q_reg_28_ ( .D(result_add_subt[28]), .CK(
d_ff4_Yn_net3608226), .RN(n778), .Q(d_ff_Yn[28]) );
DFFRXLTS d_ff4_Yn_Q_reg_29_ ( .D(result_add_subt[29]), .CK(
d_ff4_Yn_net3608226), .RN(n778), .Q(d_ff_Yn[29]) );
DFFRXLTS d_ff4_Yn_Q_reg_30_ ( .D(result_add_subt[30]), .CK(
d_ff4_Yn_net3608226), .RN(n787), .Q(d_ff_Yn[30]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_30_ ( .D(first_mux_Y[30]), .CK(
reg_val_muxZ_2stage_net3608226), .RN(n774), .Q(d_ff2_Y[30]) );
DFFRXLTS d_ff4_Yn_Q_reg_31_ ( .D(result_add_subt[31]), .CK(
d_ff4_Yn_net3608226), .RN(n774), .Q(d_ff_Yn[31]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_31_ ( .D(first_mux_Y[31]), .CK(
reg_val_muxZ_2stage_net3608226), .RN(n774), .Q(d_ff2_Y[31]) );
DFFRXLTS reg_shift_y_Q_reg_31_ ( .D(d_ff2_Y[31]), .CK(reg_shift_y_net3608226), .RN(n774), .Q(d_ff3_sh_y_out[31]) );
DFFRXLTS d_ff4_Zn_Q_reg_0_ ( .D(result_add_subt[0]), .CK(d_ff4_Zn_net3608226), .RN(n774), .Q(d_ff_Zn[0]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_0_ ( .D(first_mux_Z[0]), .CK(
reg_val_muxZ_2stage_net3608226), .RN(n774), .Q(d_ff2_Z[0]) );
DFFRXLTS d_ff4_Zn_Q_reg_1_ ( .D(result_add_subt[1]), .CK(d_ff4_Zn_net3608226), .RN(n774), .Q(d_ff_Zn[1]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_1_ ( .D(first_mux_Z[1]), .CK(
reg_val_muxZ_2stage_net3608226), .RN(n774), .Q(d_ff2_Z[1]) );
DFFRXLTS d_ff4_Zn_Q_reg_2_ ( .D(result_add_subt[2]), .CK(d_ff4_Zn_net3608226), .RN(n774), .Q(d_ff_Zn[2]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_2_ ( .D(first_mux_Z[2]), .CK(
reg_val_muxZ_2stage_net3608226), .RN(n774), .Q(d_ff2_Z[2]) );
DFFRXLTS d_ff4_Zn_Q_reg_3_ ( .D(result_add_subt[3]), .CK(d_ff4_Zn_net3608226), .RN(n773), .Q(d_ff_Zn[3]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_3_ ( .D(first_mux_Z[3]), .CK(
reg_val_muxZ_2stage_net3608226), .RN(n773), .Q(d_ff2_Z[3]) );
DFFRXLTS d_ff4_Zn_Q_reg_4_ ( .D(result_add_subt[4]), .CK(d_ff4_Zn_net3608226), .RN(n773), .Q(d_ff_Zn[4]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_4_ ( .D(first_mux_Z[4]), .CK(
reg_val_muxZ_2stage_net3608226), .RN(n773), .Q(d_ff2_Z[4]) );
DFFRXLTS d_ff4_Zn_Q_reg_5_ ( .D(result_add_subt[5]), .CK(d_ff4_Zn_net3608226), .RN(n773), .Q(d_ff_Zn[5]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_5_ ( .D(first_mux_Z[5]), .CK(
reg_val_muxZ_2stage_net3608226), .RN(n773), .Q(d_ff2_Z[5]) );
DFFRXLTS d_ff4_Zn_Q_reg_6_ ( .D(result_add_subt[6]), .CK(d_ff4_Zn_net3608226), .RN(n773), .Q(d_ff_Zn[6]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_6_ ( .D(first_mux_Z[6]), .CK(
reg_val_muxZ_2stage_net3608226), .RN(n773), .Q(d_ff2_Z[6]) );
DFFRXLTS d_ff4_Zn_Q_reg_7_ ( .D(result_add_subt[7]), .CK(d_ff4_Zn_net3608226), .RN(n773), .Q(d_ff_Zn[7]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_7_ ( .D(first_mux_Z[7]), .CK(
reg_val_muxZ_2stage_net3608226), .RN(n773), .Q(d_ff2_Z[7]) );
DFFRXLTS d_ff4_Zn_Q_reg_8_ ( .D(result_add_subt[8]), .CK(d_ff4_Zn_net3608226), .RN(n773), .Q(d_ff_Zn[8]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_8_ ( .D(first_mux_Z[8]), .CK(
reg_val_muxZ_2stage_net3608226), .RN(n773), .Q(d_ff2_Z[8]) );
DFFRXLTS d_ff4_Zn_Q_reg_9_ ( .D(result_add_subt[9]), .CK(d_ff4_Zn_net3608226), .RN(n772), .Q(d_ff_Zn[9]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_9_ ( .D(first_mux_Z[9]), .CK(
reg_val_muxZ_2stage_net3608226), .RN(n795), .Q(d_ff2_Z[9]) );
DFFRXLTS d_ff4_Zn_Q_reg_10_ ( .D(result_add_subt[10]), .CK(
d_ff4_Zn_net3608226), .RN(n770), .Q(d_ff_Zn[10]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_10_ ( .D(first_mux_Z[10]), .CK(
reg_val_muxZ_2stage_net3608226), .RN(n772), .Q(d_ff2_Z[10]) );
DFFRXLTS d_ff4_Zn_Q_reg_11_ ( .D(result_add_subt[11]), .CK(
d_ff4_Zn_net3608226), .RN(n795), .Q(d_ff_Zn[11]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_11_ ( .D(first_mux_Z[11]), .CK(
reg_val_muxZ_2stage_net3608226), .RN(n770), .Q(d_ff2_Z[11]) );
DFFRXLTS d_ff4_Zn_Q_reg_12_ ( .D(result_add_subt[12]), .CK(
d_ff4_Zn_net3608226), .RN(n772), .Q(d_ff_Zn[12]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_12_ ( .D(first_mux_Z[12]), .CK(
reg_val_muxZ_2stage_net3608226), .RN(n795), .Q(d_ff2_Z[12]) );
DFFRXLTS d_ff4_Zn_Q_reg_13_ ( .D(result_add_subt[13]), .CK(
d_ff4_Zn_net3608226), .RN(n770), .Q(d_ff_Zn[13]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_13_ ( .D(first_mux_Z[13]), .CK(
reg_val_muxZ_2stage_net3608226), .RN(n772), .Q(d_ff2_Z[13]) );
DFFRXLTS d_ff4_Zn_Q_reg_14_ ( .D(result_add_subt[14]), .CK(
d_ff4_Zn_net3608226), .RN(n795), .Q(d_ff_Zn[14]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_14_ ( .D(first_mux_Z[14]), .CK(
reg_val_muxZ_2stage_net3608226), .RN(n770), .Q(d_ff2_Z[14]) );
DFFRXLTS d_ff4_Zn_Q_reg_15_ ( .D(result_add_subt[15]), .CK(
d_ff4_Zn_net3608226), .RN(n771), .Q(d_ff_Zn[15]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_15_ ( .D(first_mux_Z[15]), .CK(
reg_val_muxZ_2stage_net3608226), .RN(n771), .Q(d_ff2_Z[15]) );
DFFRXLTS d_ff4_Zn_Q_reg_16_ ( .D(result_add_subt[16]), .CK(
d_ff4_Zn_net3608226), .RN(n771), .Q(d_ff_Zn[16]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_16_ ( .D(first_mux_Z[16]), .CK(
reg_val_muxZ_2stage_net3608226), .RN(n771), .Q(d_ff2_Z[16]) );
DFFRXLTS d_ff4_Zn_Q_reg_17_ ( .D(result_add_subt[17]), .CK(
d_ff4_Zn_net3608226), .RN(n771), .Q(d_ff_Zn[17]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_17_ ( .D(first_mux_Z[17]), .CK(
reg_val_muxZ_2stage_net3608226), .RN(n771), .Q(d_ff2_Z[17]) );
DFFRXLTS d_ff4_Zn_Q_reg_18_ ( .D(result_add_subt[18]), .CK(
d_ff4_Zn_net3608226), .RN(n771), .Q(d_ff_Zn[18]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_18_ ( .D(first_mux_Z[18]), .CK(
reg_val_muxZ_2stage_net3608226), .RN(n771), .Q(d_ff2_Z[18]) );
DFFRXLTS d_ff4_Zn_Q_reg_19_ ( .D(result_add_subt[19]), .CK(
d_ff4_Zn_net3608226), .RN(n771), .Q(d_ff_Zn[19]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_19_ ( .D(first_mux_Z[19]), .CK(
reg_val_muxZ_2stage_net3608226), .RN(n771), .Q(d_ff2_Z[19]) );
DFFRXLTS d_ff4_Zn_Q_reg_20_ ( .D(result_add_subt[20]), .CK(
d_ff4_Zn_net3608226), .RN(n771), .Q(d_ff_Zn[20]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_20_ ( .D(first_mux_Z[20]), .CK(
reg_val_muxZ_2stage_net3608226), .RN(n771), .Q(d_ff2_Z[20]) );
DFFRXLTS d_ff4_Zn_Q_reg_21_ ( .D(result_add_subt[21]), .CK(
d_ff4_Zn_net3608226), .RN(n772), .Q(d_ff_Zn[21]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_21_ ( .D(first_mux_Z[21]), .CK(
reg_val_muxZ_2stage_net3608226), .RN(n795), .Q(d_ff2_Z[21]) );
DFFRXLTS d_ff4_Zn_Q_reg_22_ ( .D(result_add_subt[22]), .CK(
d_ff4_Zn_net3608226), .RN(n770), .Q(d_ff_Zn[22]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_22_ ( .D(first_mux_Z[22]), .CK(
reg_val_muxZ_2stage_net3608226), .RN(n604), .Q(d_ff2_Z[22]) );
DFFRXLTS d_ff4_Zn_Q_reg_23_ ( .D(result_add_subt[23]), .CK(
d_ff4_Zn_net3608226), .RN(n154), .Q(d_ff_Zn[23]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_23_ ( .D(first_mux_Z[23]), .CK(
reg_val_muxZ_2stage_net3608226), .RN(n154), .Q(d_ff2_Z[23]) );
DFFRXLTS d_ff4_Zn_Q_reg_24_ ( .D(result_add_subt[24]), .CK(
d_ff4_Zn_net3608226), .RN(n154), .Q(d_ff_Zn[24]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_24_ ( .D(first_mux_Z[24]), .CK(
reg_val_muxZ_2stage_net3608226), .RN(n154), .Q(d_ff2_Z[24]) );
DFFRXLTS d_ff4_Zn_Q_reg_25_ ( .D(result_add_subt[25]), .CK(
d_ff4_Zn_net3608226), .RN(n154), .Q(d_ff_Zn[25]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_25_ ( .D(first_mux_Z[25]), .CK(
reg_val_muxZ_2stage_net3608226), .RN(n604), .Q(d_ff2_Z[25]) );
DFFRXLTS d_ff4_Zn_Q_reg_26_ ( .D(result_add_subt[26]), .CK(
d_ff4_Zn_net3608226), .RN(n604), .Q(d_ff_Zn[26]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_26_ ( .D(first_mux_Z[26]), .CK(
reg_val_muxZ_2stage_net3608226), .RN(n772), .Q(d_ff2_Z[26]) );
DFFRXLTS d_ff4_Zn_Q_reg_27_ ( .D(result_add_subt[27]), .CK(
d_ff4_Zn_net3608226), .RN(n795), .Q(d_ff_Zn[27]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_27_ ( .D(first_mux_Z[27]), .CK(
reg_val_muxZ_2stage_net3608226), .RN(n770), .Q(d_ff2_Z[27]) );
DFFRXLTS d_ff4_Zn_Q_reg_28_ ( .D(result_add_subt[28]), .CK(
d_ff4_Zn_net3608226), .RN(n772), .Q(d_ff_Zn[28]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_28_ ( .D(first_mux_Z[28]), .CK(
reg_val_muxZ_2stage_net3608226), .RN(n795), .Q(d_ff2_Z[28]) );
DFFRXLTS d_ff4_Zn_Q_reg_29_ ( .D(result_add_subt[29]), .CK(
d_ff4_Zn_net3608226), .RN(n770), .Q(d_ff_Zn[29]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_29_ ( .D(first_mux_Z[29]), .CK(
reg_val_muxZ_2stage_net3608226), .RN(n772), .Q(d_ff2_Z[29]) );
DFFRXLTS d_ff4_Zn_Q_reg_30_ ( .D(result_add_subt[30]), .CK(
d_ff4_Zn_net3608226), .RN(n795), .Q(d_ff_Zn[30]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_30_ ( .D(first_mux_Z[30]), .CK(
reg_val_muxZ_2stage_net3608226), .RN(n770), .Q(d_ff2_Z[30]) );
DFFRXLTS d_ff4_Zn_Q_reg_31_ ( .D(result_add_subt[31]), .CK(
d_ff4_Zn_net3608226), .RN(n772), .Q(d_ff_Zn[31]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_31_ ( .D(first_mux_Z[31]), .CK(
reg_val_muxZ_2stage_net3608226), .RN(n795), .Q(d_ff2_Z[31]) );
DFFRXLTS reg_LUT_Q_reg_27_ ( .D(1'b1), .CK(reg_shift_y_net3608226), .RN(n770), .Q(d_ff3_LUT_out[27]) );
DFFRX1TS VAR_CONT_temp_reg_1_ ( .D(n519), .CK(clk), .RN(n784), .Q(
cont_var_out[1]), .QN(n766) );
DFFRX2TS VAR_CONT_temp_reg_0_ ( .D(n518), .CK(clk), .RN(n622), .Q(
cont_var_out[0]), .QN(n765) );
DFFRX2TS ITER_CONT_temp_reg_0_ ( .D(n763), .CK(ITER_CONT_net3608262), .RN(
n784), .Q(cont_iter_out[0]), .QN(n763) );
DFFRX2TS ITER_CONT_temp_reg_3_ ( .D(ITER_CONT_N5), .CK(ITER_CONT_net3608262),
.RN(n791), .Q(cont_iter_out[3]), .QN(n762) );
DFFRX2TS ITER_CONT_temp_reg_2_ ( .D(ITER_CONT_N4), .CK(ITER_CONT_net3608262),
.RN(n783), .Q(cont_iter_out[2]), .QN(n761) );
DFFRXLTS d_ff5_data_out_Q_reg_0_ ( .D(mux_sal[0]), .CK(
d_ff5_data_out_net3608226), .RN(n778), .Q(data_output[0]) );
DFFRXLTS d_ff5_data_out_Q_reg_1_ ( .D(mux_sal[1]), .CK(
d_ff5_data_out_net3608226), .RN(n771), .Q(data_output[1]) );
DFFRXLTS d_ff5_data_out_Q_reg_2_ ( .D(mux_sal[2]), .CK(
d_ff5_data_out_net3608226), .RN(n604), .Q(data_output[2]) );
DFFRXLTS d_ff5_data_out_Q_reg_3_ ( .D(mux_sal[3]), .CK(
d_ff5_data_out_net3608226), .RN(n775), .Q(data_output[3]) );
DFFRXLTS d_ff5_data_out_Q_reg_4_ ( .D(mux_sal[4]), .CK(
d_ff5_data_out_net3608226), .RN(n778), .Q(data_output[4]) );
DFFRXLTS d_ff5_data_out_Q_reg_5_ ( .D(mux_sal[5]), .CK(
d_ff5_data_out_net3608226), .RN(n776), .Q(data_output[5]) );
DFFRXLTS d_ff5_data_out_Q_reg_6_ ( .D(mux_sal[6]), .CK(
d_ff5_data_out_net3608226), .RN(n776), .Q(data_output[6]) );
DFFRXLTS d_ff5_data_out_Q_reg_7_ ( .D(mux_sal[7]), .CK(
d_ff5_data_out_net3608226), .RN(n782), .Q(data_output[7]) );
DFFRXLTS d_ff5_data_out_Q_reg_8_ ( .D(mux_sal[8]), .CK(
d_ff5_data_out_net3608226), .RN(n781), .Q(data_output[8]) );
DFFRXLTS d_ff5_data_out_Q_reg_9_ ( .D(mux_sal[9]), .CK(
d_ff5_data_out_net3608226), .RN(n780), .Q(data_output[9]) );
DFFRXLTS d_ff5_data_out_Q_reg_10_ ( .D(mux_sal[10]), .CK(
d_ff5_data_out_net3608226), .RN(n780), .Q(data_output[10]) );
DFFRXLTS d_ff5_data_out_Q_reg_11_ ( .D(mux_sal[11]), .CK(
d_ff5_data_out_net3608226), .RN(n779), .Q(data_output[11]) );
DFFRXLTS d_ff5_data_out_Q_reg_12_ ( .D(mux_sal[12]), .CK(
d_ff5_data_out_net3608226), .RN(n776), .Q(data_output[12]) );
DFFRXLTS d_ff5_data_out_Q_reg_13_ ( .D(mux_sal[13]), .CK(
d_ff5_data_out_net3608226), .RN(n776), .Q(data_output[13]) );
DFFRXLTS d_ff5_data_out_Q_reg_14_ ( .D(mux_sal[14]), .CK(
d_ff5_data_out_net3608226), .RN(n778), .Q(data_output[14]) );
DFFRXLTS d_ff5_data_out_Q_reg_15_ ( .D(mux_sal[15]), .CK(
d_ff5_data_out_net3608226), .RN(n777), .Q(data_output[15]) );
DFFRXLTS d_ff5_data_out_Q_reg_16_ ( .D(mux_sal[16]), .CK(
d_ff5_data_out_net3608226), .RN(n781), .Q(data_output[16]) );
DFFRXLTS d_ff5_data_out_Q_reg_17_ ( .D(mux_sal[17]), .CK(
d_ff5_data_out_net3608226), .RN(n604), .Q(data_output[17]) );
DFFRXLTS d_ff5_data_out_Q_reg_18_ ( .D(mux_sal[18]), .CK(
d_ff5_data_out_net3608226), .RN(n775), .Q(data_output[18]) );
DFFRXLTS d_ff5_data_out_Q_reg_19_ ( .D(mux_sal[19]), .CK(
d_ff5_data_out_net3608226), .RN(n776), .Q(data_output[19]) );
DFFRXLTS d_ff5_data_out_Q_reg_20_ ( .D(mux_sal[20]), .CK(
d_ff5_data_out_net3608226), .RN(n776), .Q(data_output[20]) );
DFFRXLTS d_ff5_data_out_Q_reg_21_ ( .D(mux_sal[21]), .CK(
d_ff5_data_out_net3608226), .RN(n781), .Q(data_output[21]) );
DFFRXLTS d_ff5_data_out_Q_reg_22_ ( .D(mux_sal[22]), .CK(
d_ff5_data_out_net3608226), .RN(n774), .Q(data_output[22]) );
DFFRXLTS d_ff5_data_out_Q_reg_23_ ( .D(mux_sal[23]), .CK(
d_ff5_data_out_net3608226), .RN(n773), .Q(data_output[23]) );
DFFRXLTS d_ff5_data_out_Q_reg_24_ ( .D(mux_sal[24]), .CK(
d_ff5_data_out_net3608226), .RN(n776), .Q(data_output[24]) );
DFFRXLTS d_ff5_data_out_Q_reg_25_ ( .D(mux_sal[25]), .CK(
d_ff5_data_out_net3608226), .RN(n775), .Q(data_output[25]) );
DFFRXLTS d_ff5_data_out_Q_reg_26_ ( .D(mux_sal[26]), .CK(
d_ff5_data_out_net3608226), .RN(n795), .Q(data_output[26]) );
DFFRXLTS d_ff5_data_out_Q_reg_27_ ( .D(mux_sal[27]), .CK(
d_ff5_data_out_net3608226), .RN(n778), .Q(data_output[27]) );
DFFRXLTS d_ff5_data_out_Q_reg_28_ ( .D(mux_sal[28]), .CK(
d_ff5_data_out_net3608226), .RN(n785), .Q(data_output[28]) );
DFFRXLTS d_ff5_data_out_Q_reg_29_ ( .D(mux_sal[29]), .CK(
d_ff5_data_out_net3608226), .RN(n785), .Q(data_output[29]) );
DFFRXLTS d_ff5_data_out_Q_reg_30_ ( .D(mux_sal[30]), .CK(
d_ff5_data_out_net3608226), .RN(n774), .Q(data_output[30]) );
DFFRXLTS d_ff5_data_out_Q_reg_31_ ( .D(fmtted_Result_31_), .CK(
d_ff5_data_out_net3608226), .RN(n774), .Q(data_output[31]) );
DFFRX1TS inst_CORDIC_FSM_v3_state_reg_reg_3_ ( .D(n612), .CK(clk), .RN(n785),
.Q(inst_CORDIC_FSM_v3_state_reg[3]) );
DFFRX1TS inst_CORDIC_FSM_v3_state_reg_reg_6_ ( .D(
inst_CORDIC_FSM_v3_state_next[6]), .CK(clk), .RN(n791), .Q(
inst_CORDIC_FSM_v3_state_reg[6]) );
DFFRX1TS inst_CORDIC_FSM_v3_state_reg_reg_4_ ( .D(
inst_CORDIC_FSM_v3_state_next[4]), .CK(clk), .RN(n783), .Q(
inst_CORDIC_FSM_v3_state_reg[4]) );
DFFRX1TS inst_CORDIC_FSM_v3_state_reg_reg_5_ ( .D(
inst_CORDIC_FSM_v3_state_next[5]), .CK(clk), .RN(n786), .Q(
inst_CORDIC_FSM_v3_state_reg[5]) );
DFFRX1TS inst_CORDIC_FSM_v3_state_reg_reg_1_ ( .D(
inst_CORDIC_FSM_v3_state_next[1]), .CK(clk), .RN(n792), .Q(
inst_CORDIC_FSM_v3_state_reg[1]) );
DFFRXLTS reg_sign_Q_reg_0_ ( .D(d_ff2_Z[31]), .CK(reg_shift_y_net3608226),
.RN(n772), .Q(d_ff3_sign_out) );
DFFRX1TS inst_CORDIC_FSM_v3_state_reg_reg_2_ ( .D(
inst_CORDIC_FSM_v3_state_next[2]), .CK(clk), .RN(n787), .Q(
inst_CORDIC_FSM_v3_state_reg[2]) );
DFFSX1TS inst_CORDIC_FSM_v3_state_reg_reg_0_ ( .D(
inst_CORDIC_FSM_v3_state_next[0]), .CK(clk), .SN(n622), .Q(
inst_CORDIC_FSM_v3_state_reg[0]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_27_ ( .D(first_mux_X[27]), .CK(
reg_val_muxZ_2stage_net3608226), .RN(n778), .Q(d_ff2_X[27]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_27_ ( .D(first_mux_Y[27]), .CK(
reg_val_muxZ_2stage_net3608226), .RN(n621), .Q(d_ff2_Y[27]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_29_ ( .D(first_mux_X[29]), .CK(
reg_val_muxZ_2stage_net3608226), .RN(n782), .Q(d_ff2_X[29]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_29_ ( .D(first_mux_Y[29]), .CK(
reg_val_muxZ_2stage_net3608226), .RN(n779), .Q(d_ff2_Y[29]) );
DFFRX1TS reg_operation_Q_reg_0_ ( .D(operation), .CK(reg_Z0_net3608226),
.RN(n793), .Q(d_ff1_operation_out) );
DFFRX4TS ITER_CONT_temp_reg_1_ ( .D(ITER_CONT_N3), .CK(ITER_CONT_net3608262),
.RN(n794), .Q(cont_iter_out[1]), .QN(n764) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_24_ ( .D(first_mux_X[24]), .CK(
reg_val_muxZ_2stage_net3608226), .RN(n776), .Q(d_ff2_X[24]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_26_ ( .D(first_mux_X[26]), .CK(
reg_val_muxZ_2stage_net3608226), .RN(n776), .Q(d_ff2_X[26]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_25_ ( .D(first_mux_X[25]), .CK(
reg_val_muxZ_2stage_net3608226), .RN(n777), .Q(d_ff2_X[25]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_26_ ( .D(first_mux_Y[26]), .CK(
reg_val_muxZ_2stage_net3608226), .RN(n785), .Q(d_ff2_Y[26]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_25_ ( .D(first_mux_Y[25]), .CK(
reg_val_muxZ_2stage_net3608226), .RN(n777), .Q(d_ff2_Y[25]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_24_ ( .D(first_mux_Y[24]), .CK(
reg_val_muxZ_2stage_net3608226), .RN(n775), .Q(d_ff2_Y[24]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_28_ ( .D(first_mux_Y[28]), .CK(
reg_val_muxZ_2stage_net3608226), .RN(n782), .Q(d_ff2_Y[28]), .QN(n769)
);
DFFRX1TS inst_CORDIC_FSM_v3_state_reg_reg_7_ ( .D(
inst_CORDIC_FSM_v3_state_next[7]), .CK(clk), .RN(n786), .Q(
inst_CORDIC_FSM_v3_state_reg[7]) );
ADDFX1TS intadd_422_U4 ( .A(d_ff2_Y[24]), .B(n764), .CI(intadd_422_CI), .CO(
intadd_422_n3), .S(sh_exp_y[1]) );
ADDFX1TS intadd_421_U4 ( .A(n764), .B(d_ff2_X[24]), .CI(intadd_421_CI), .CO(
intadd_421_n3), .S(sh_exp_x[1]) );
ADDFX1TS intadd_422_U3 ( .A(d_ff2_Y[25]), .B(n761), .CI(intadd_422_n3), .CO(
intadd_422_n2), .S(sh_exp_y[2]) );
ADDFX1TS intadd_421_U3 ( .A(d_ff2_X[25]), .B(n761), .CI(intadd_421_n3), .CO(
intadd_421_n2), .S(sh_exp_x[2]) );
ADDFX1TS intadd_421_U2 ( .A(d_ff2_X[26]), .B(n762), .CI(intadd_421_n2), .CO(
intadd_421_n1), .S(sh_exp_x[3]) );
ADDFX1TS intadd_422_U2 ( .A(d_ff2_Y[26]), .B(n762), .CI(intadd_422_n2), .CO(
intadd_422_n1), .S(sh_exp_y[3]) );
AOI222X1TS U407 ( .A0(n685), .A1(d_ff2_X[30]), .B0(n668), .B1(d_ff2_Y[30]),
.C0(n731), .C1(d_ff2_Z[30]), .Y(n671) );
AOI222X1TS U408 ( .A0(n744), .A1(d_ff2_X[6]), .B0(n743), .B1(d_ff2_Y[6]),
.C0(n609), .C1(d_ff2_Z[6]), .Y(n673) );
AOI222X1TS U409 ( .A0(n744), .A1(d_ff2_X[5]), .B0(n739), .B1(d_ff2_Y[5]),
.C0(n609), .C1(d_ff2_Z[5]), .Y(n675) );
OAI21XLTS U410 ( .A0(d_ff1_operation_out), .A1(n613), .B0(n698), .Y(n696) );
BUFX3TS U411 ( .A(n709), .Y(n614) );
INVX4TS U412 ( .A(n716), .Y(n646) );
AOI222X1TS U413 ( .A0(n685), .A1(d_ff2_X[27]), .B0(n668), .B1(d_ff2_Y[27]),
.C0(n609), .C1(d_ff2_Z[27]), .Y(n652) );
AOI222X1TS U414 ( .A0(n685), .A1(d_ff2_X[25]), .B0(n743), .B1(d_ff2_Y[25]),
.C0(n609), .C1(d_ff2_Z[25]), .Y(n653) );
AOI222X1TS U415 ( .A0(n669), .A1(d_ff2_X[23]), .B0(n739), .B1(d_ff2_Y[23]),
.C0(n609), .C1(d_ff2_Z[23]), .Y(n647) );
AOI222X1TS U416 ( .A0(n669), .A1(d_ff2_X[15]), .B0(n684), .B1(d_ff2_Y[15]),
.C0(n609), .C1(d_ff2_Z[15]), .Y(n659) );
NAND3X1TS U417 ( .A(enab_cont_iter), .B(n747), .C(n720), .Y(n635) );
INVX3TS U418 ( .A(n703), .Y(n702) );
NAND3BX1TS U419 ( .AN(inst_CORDIC_FSM_v3_state_reg[6]), .B(n624), .C(
inst_CORDIC_FSM_v3_state_reg[4]), .Y(n717) );
INVX3TS U420 ( .A(n640), .Y(n740) );
INVX3TS U421 ( .A(n640), .Y(n722) );
INVX3TS U422 ( .A(n640), .Y(n744) );
OR2X4TS U423 ( .A(cont_iter_out[2]), .B(n695), .Y(n703) );
NAND4BXLTS U424 ( .AN(inst_CORDIC_FSM_v3_state_reg[1]), .B(
inst_CORDIC_FSM_v3_state_reg[3]), .C(n632), .D(n631), .Y(n636) );
OR2X2TS U425 ( .A(n765), .B(cont_var_out[1]), .Y(n640) );
OR2X2TS U426 ( .A(n766), .B(cont_var_out[0]), .Y(n620) );
BUFX3TS U427 ( .A(n154), .Y(n604) );
NAND2BXLTS U428 ( .AN(inst_CORDIC_FSM_v3_state_reg[3]), .B(n631), .Y(n619)
);
NAND3BXLTS U429 ( .AN(n619), .B(inst_CORDIC_FSM_v3_state_reg[1]), .C(n632),
.Y(n629) );
NAND3XLTS U430 ( .A(n717), .B(n641), .C(n694), .Y(n753) );
AOI222X1TS U431 ( .A0(n722), .A1(d_ff3_sh_y_out[6]), .B0(n721), .B1(
d_ff3_sh_x_out[6]), .C0(n746), .C1(d_ff3_LUT_out[6]), .Y(n683) );
AOI222X1TS U432 ( .A0(n722), .A1(d_ff3_sh_y_out[9]), .B0(n668), .B1(
d_ff3_sh_x_out[9]), .C0(n746), .C1(d_ff3_LUT_out[9]), .Y(n682) );
AOI222X1TS U433 ( .A0(n722), .A1(d_ff3_sh_y_out[10]), .B0(n684), .B1(
d_ff3_sh_x_out[10]), .C0(n746), .C1(d_ff3_LUT_out[10]), .Y(n687) );
AOI222X1TS U434 ( .A0(n722), .A1(d_ff3_sh_y_out[21]), .B0(n668), .B1(
d_ff3_sh_x_out[21]), .C0(n746), .C1(d_ff3_LUT_out[21]), .Y(n688) );
AOI222X1TS U435 ( .A0(n722), .A1(d_ff3_sh_y_out[23]), .B0(n668), .B1(
d_ff3_sh_x_out[23]), .C0(n746), .C1(d_ff3_LUT_out[23]), .Y(n693) );
AOI222X1TS U436 ( .A0(n722), .A1(d_ff3_sh_y_out[26]), .B0(n684), .B1(
d_ff3_sh_x_out[26]), .C0(n731), .C1(d_ff3_LUT_out[26]), .Y(n643) );
AOI222X1TS U437 ( .A0(n744), .A1(d_ff2_X[3]), .B0(n684), .B1(d_ff2_Y[3]),
.C0(n731), .C1(d_ff2_Z[3]), .Y(n674) );
AOI222X1TS U438 ( .A0(n669), .A1(d_ff2_X[12]), .B0(n739), .B1(d_ff2_Y[12]),
.C0(n731), .C1(d_ff2_Z[12]), .Y(n649) );
AOI222X1TS U439 ( .A0(n669), .A1(d_ff2_X[18]), .B0(n684), .B1(d_ff2_Y[18]),
.C0(n731), .C1(d_ff2_Z[18]), .Y(n662) );
AOI222X1TS U440 ( .A0(n685), .A1(d_ff2_X[24]), .B0(n743), .B1(d_ff2_Y[24]),
.C0(n608), .C1(d_ff2_Z[24]), .Y(n667) );
AOI222X1TS U441 ( .A0(n685), .A1(d_ff2_X[26]), .B0(n739), .B1(d_ff2_Y[26]),
.C0(n731), .C1(d_ff2_Z[26]), .Y(n651) );
AOI222X1TS U442 ( .A0(n685), .A1(d_ff2_X[29]), .B0(n721), .B1(d_ff2_Y[29]),
.C0(n731), .C1(d_ff2_Z[29]), .Y(n661) );
OR2X1TS U443 ( .A(d_ff_Xn[25]), .B(n633), .Y(first_mux_X[25]) );
OR2X1TS U444 ( .A(d_ff_Xn[26]), .B(n633), .Y(first_mux_X[26]) );
OR2X1TS U445 ( .A(d_ff_Xn[24]), .B(n633), .Y(first_mux_X[24]) );
NOR2XLTS U446 ( .A(n720), .B(n628), .Y(ITER_CONT_N3) );
OR2X1TS U447 ( .A(d_ff_Xn[29]), .B(n633), .Y(first_mux_X[29]) );
OR2X1TS U448 ( .A(d_ff_Xn[27]), .B(n633), .Y(first_mux_X[27]) );
OAI21XLTS U449 ( .A0(beg_fsm_cordic), .A1(n715), .B0(n639), .Y(
inst_CORDIC_FSM_v3_state_next[0]) );
OAI21XLTS U450 ( .A0(n630), .A1(n641), .B0(n629), .Y(
inst_CORDIC_FSM_v3_state_next[2]) );
AO22XLTS U451 ( .A0(n712), .A1(d_ff_Yn[30]), .B0(n711), .B1(d_ff_Xn[30]),
.Y(mux_sal[30]) );
AO22XLTS U452 ( .A0(n712), .A1(d_ff_Yn[29]), .B0(n711), .B1(d_ff_Xn[29]),
.Y(mux_sal[29]) );
AO22XLTS U453 ( .A0(n712), .A1(d_ff_Yn[28]), .B0(n711), .B1(d_ff_Xn[28]),
.Y(mux_sal[28]) );
AO22XLTS U454 ( .A0(n712), .A1(d_ff_Yn[27]), .B0(n711), .B1(d_ff_Xn[27]),
.Y(mux_sal[27]) );
AO22XLTS U455 ( .A0(n614), .A1(d_ff_Yn[26]), .B0(n711), .B1(d_ff_Xn[26]),
.Y(mux_sal[26]) );
AO22XLTS U456 ( .A0(n614), .A1(d_ff_Yn[25]), .B0(n711), .B1(d_ff_Xn[25]),
.Y(mux_sal[25]) );
AO22XLTS U457 ( .A0(n614), .A1(d_ff_Yn[24]), .B0(n711), .B1(d_ff_Xn[24]),
.Y(mux_sal[24]) );
AO22XLTS U458 ( .A0(n614), .A1(d_ff_Yn[23]), .B0(n711), .B1(d_ff_Xn[23]),
.Y(mux_sal[23]) );
AO22XLTS U459 ( .A0(n614), .A1(d_ff_Yn[22]), .B0(n711), .B1(d_ff_Xn[22]),
.Y(mux_sal[22]) );
AO22XLTS U460 ( .A0(n614), .A1(d_ff_Yn[21]), .B0(n711), .B1(d_ff_Xn[21]),
.Y(mux_sal[21]) );
AO22XLTS U461 ( .A0(n614), .A1(d_ff_Yn[20]), .B0(n711), .B1(d_ff_Xn[20]),
.Y(mux_sal[20]) );
AO22XLTS U462 ( .A0(n614), .A1(d_ff_Yn[19]), .B0(n711), .B1(d_ff_Xn[19]),
.Y(mux_sal[19]) );
AO22XLTS U463 ( .A0(n614), .A1(d_ff_Yn[18]), .B0(n708), .B1(d_ff_Xn[18]),
.Y(mux_sal[18]) );
AO22XLTS U464 ( .A0(n614), .A1(d_ff_Yn[17]), .B0(n710), .B1(d_ff_Xn[17]),
.Y(mux_sal[17]) );
AO22XLTS U465 ( .A0(n614), .A1(d_ff_Yn[16]), .B0(n710), .B1(d_ff_Xn[16]),
.Y(mux_sal[16]) );
AO22XLTS U466 ( .A0(n614), .A1(d_ff_Yn[15]), .B0(n710), .B1(d_ff_Xn[15]),
.Y(mux_sal[15]) );
AO22XLTS U467 ( .A0(n614), .A1(d_ff_Yn[14]), .B0(n710), .B1(d_ff_Xn[14]),
.Y(mux_sal[14]) );
AO22XLTS U468 ( .A0(n614), .A1(d_ff_Yn[13]), .B0(n710), .B1(d_ff_Xn[13]),
.Y(mux_sal[13]) );
AO22XLTS U469 ( .A0(n709), .A1(d_ff_Yn[12]), .B0(n710), .B1(d_ff_Xn[12]),
.Y(mux_sal[12]) );
AO22XLTS U470 ( .A0(n709), .A1(d_ff_Yn[11]), .B0(n710), .B1(d_ff_Xn[11]),
.Y(mux_sal[11]) );
AO22XLTS U471 ( .A0(n709), .A1(d_ff_Yn[10]), .B0(n708), .B1(d_ff_Xn[10]),
.Y(mux_sal[10]) );
AO22XLTS U472 ( .A0(n709), .A1(d_ff_Yn[9]), .B0(n708), .B1(d_ff_Xn[9]), .Y(
mux_sal[9]) );
AO22XLTS U473 ( .A0(n709), .A1(d_ff_Yn[8]), .B0(n708), .B1(d_ff_Xn[8]), .Y(
mux_sal[8]) );
AO22XLTS U474 ( .A0(n709), .A1(d_ff_Yn[7]), .B0(n708), .B1(d_ff_Xn[7]), .Y(
mux_sal[7]) );
AO22XLTS U475 ( .A0(n709), .A1(d_ff_Yn[6]), .B0(n708), .B1(d_ff_Xn[6]), .Y(
mux_sal[6]) );
AO22XLTS U476 ( .A0(n709), .A1(d_ff_Yn[5]), .B0(n708), .B1(d_ff_Xn[5]), .Y(
mux_sal[5]) );
AO22XLTS U477 ( .A0(n709), .A1(d_ff_Yn[4]), .B0(n708), .B1(d_ff_Xn[4]), .Y(
mux_sal[4]) );
AO22XLTS U478 ( .A0(n709), .A1(d_ff_Yn[3]), .B0(n708), .B1(d_ff_Xn[3]), .Y(
mux_sal[3]) );
AO22XLTS U479 ( .A0(n709), .A1(d_ff_Yn[2]), .B0(n708), .B1(d_ff_Xn[2]), .Y(
mux_sal[2]) );
AO22XLTS U480 ( .A0(n709), .A1(d_ff_Yn[1]), .B0(n708), .B1(d_ff_Xn[1]), .Y(
mux_sal[1]) );
AO22XLTS U481 ( .A0(n709), .A1(d_ff_Yn[0]), .B0(n711), .B1(d_ff_Xn[0]), .Y(
mux_sal[0]) );
NOR2XLTS U482 ( .A(n630), .B(n529), .Y(ITER_CONT_N5) );
OAI211XLTS U483 ( .A0(n754), .A1(n640), .B0(n620), .C0(n642), .Y(n519) );
AO22XLTS U484 ( .A0(n714), .A1(d_ff1_Z[31]), .B0(n707), .B1(d_ff_Zn[31]),
.Y(first_mux_Z[31]) );
AO22XLTS U485 ( .A0(n714), .A1(d_ff1_Z[30]), .B0(n705), .B1(d_ff_Zn[30]),
.Y(first_mux_Z[30]) );
AO22XLTS U486 ( .A0(n714), .A1(d_ff1_Z[29]), .B0(n705), .B1(d_ff_Zn[29]),
.Y(first_mux_Z[29]) );
AO22XLTS U487 ( .A0(n714), .A1(d_ff1_Z[28]), .B0(n705), .B1(d_ff_Zn[28]),
.Y(first_mux_Z[28]) );
AO22XLTS U488 ( .A0(n706), .A1(d_ff1_Z[27]), .B0(n705), .B1(d_ff_Zn[27]),
.Y(first_mux_Z[27]) );
AO22XLTS U489 ( .A0(n706), .A1(d_ff1_Z[26]), .B0(n705), .B1(d_ff_Zn[26]),
.Y(first_mux_Z[26]) );
AO22XLTS U490 ( .A0(n706), .A1(d_ff1_Z[25]), .B0(n705), .B1(d_ff_Zn[25]),
.Y(first_mux_Z[25]) );
AO22XLTS U491 ( .A0(n706), .A1(d_ff1_Z[24]), .B0(n705), .B1(d_ff_Zn[24]),
.Y(first_mux_Z[24]) );
AO22XLTS U492 ( .A0(n706), .A1(d_ff1_Z[23]), .B0(n705), .B1(d_ff_Zn[23]),
.Y(first_mux_Z[23]) );
AO22XLTS U493 ( .A0(n706), .A1(d_ff1_Z[22]), .B0(n705), .B1(d_ff_Zn[22]),
.Y(first_mux_Z[22]) );
AO22XLTS U494 ( .A0(n706), .A1(d_ff1_Z[21]), .B0(n705), .B1(d_ff_Zn[21]),
.Y(first_mux_Z[21]) );
AO22XLTS U495 ( .A0(n706), .A1(d_ff1_Z[20]), .B0(n705), .B1(d_ff_Zn[20]),
.Y(first_mux_Z[20]) );
AO22XLTS U496 ( .A0(n706), .A1(d_ff1_Z[19]), .B0(n705), .B1(d_ff_Zn[19]),
.Y(first_mux_Z[19]) );
AO22XLTS U497 ( .A0(n706), .A1(d_ff1_Z[18]), .B0(n705), .B1(d_ff_Zn[18]),
.Y(first_mux_Z[18]) );
AO22XLTS U498 ( .A0(n706), .A1(d_ff1_Z[17]), .B0(n705), .B1(d_ff_Zn[17]),
.Y(first_mux_Z[17]) );
AO22XLTS U499 ( .A0(n706), .A1(d_ff1_Z[16]), .B0(n707), .B1(d_ff_Zn[16]),
.Y(first_mux_Z[16]) );
AO22XLTS U500 ( .A0(n706), .A1(d_ff1_Z[15]), .B0(n707), .B1(d_ff_Zn[15]),
.Y(first_mux_Z[15]) );
AO22XLTS U501 ( .A0(n704), .A1(d_ff1_Z[14]), .B0(n707), .B1(d_ff_Zn[14]),
.Y(first_mux_Z[14]) );
AO22XLTS U502 ( .A0(n704), .A1(d_ff1_Z[13]), .B0(n707), .B1(d_ff_Zn[13]),
.Y(first_mux_Z[13]) );
AO22XLTS U503 ( .A0(n704), .A1(d_ff1_Z[12]), .B0(n707), .B1(d_ff_Zn[12]),
.Y(first_mux_Z[12]) );
AO22XLTS U504 ( .A0(n704), .A1(d_ff1_Z[11]), .B0(n707), .B1(d_ff_Zn[11]),
.Y(first_mux_Z[11]) );
AO22XLTS U505 ( .A0(n704), .A1(d_ff1_Z[10]), .B0(n707), .B1(d_ff_Zn[10]),
.Y(first_mux_Z[10]) );
AO22XLTS U506 ( .A0(n704), .A1(d_ff1_Z[9]), .B0(n707), .B1(d_ff_Zn[9]), .Y(
first_mux_Z[9]) );
AO22XLTS U507 ( .A0(n704), .A1(d_ff1_Z[8]), .B0(n707), .B1(d_ff_Zn[8]), .Y(
first_mux_Z[8]) );
AO22XLTS U508 ( .A0(n704), .A1(d_ff1_Z[7]), .B0(n707), .B1(d_ff_Zn[7]), .Y(
first_mux_Z[7]) );
AO22XLTS U509 ( .A0(n704), .A1(d_ff1_Z[6]), .B0(n707), .B1(d_ff_Zn[6]), .Y(
first_mux_Z[6]) );
AO22XLTS U510 ( .A0(n704), .A1(d_ff1_Z[5]), .B0(n707), .B1(d_ff_Zn[5]), .Y(
first_mux_Z[5]) );
AO22XLTS U511 ( .A0(n704), .A1(d_ff1_Z[4]), .B0(n707), .B1(d_ff_Zn[4]), .Y(
first_mux_Z[4]) );
AO22XLTS U512 ( .A0(n704), .A1(d_ff1_Z[3]), .B0(n703), .B1(d_ff_Zn[3]), .Y(
first_mux_Z[3]) );
AO22XLTS U513 ( .A0(n702), .A1(d_ff1_Z[2]), .B0(n703), .B1(d_ff_Zn[2]), .Y(
first_mux_Z[2]) );
AO22XLTS U514 ( .A0(n704), .A1(d_ff1_Z[1]), .B0(n703), .B1(d_ff_Zn[1]), .Y(
first_mux_Z[1]) );
AO22XLTS U515 ( .A0(n714), .A1(d_ff1_Z[0]), .B0(n703), .B1(d_ff_Zn[0]), .Y(
first_mux_Z[0]) );
OR2X1TS U516 ( .A(d_ff_Xn[28]), .B(n633), .Y(first_mux_X[28]) );
OR2X1TS U517 ( .A(d_ff_Xn[20]), .B(n702), .Y(first_mux_X[20]) );
OR2X1TS U518 ( .A(d_ff_Xn[19]), .B(n702), .Y(first_mux_X[19]) );
OR2X1TS U519 ( .A(d_ff_Xn[17]), .B(n702), .Y(first_mux_X[17]) );
OR2X1TS U520 ( .A(d_ff_Xn[14]), .B(n702), .Y(first_mux_X[14]) );
OR2X1TS U521 ( .A(d_ff_Xn[13]), .B(n633), .Y(first_mux_X[13]) );
OR2X1TS U522 ( .A(d_ff_Xn[7]), .B(n633), .Y(first_mux_X[7]) );
OR2X1TS U523 ( .A(d_ff_Xn[6]), .B(n702), .Y(first_mux_X[6]) );
OR2X1TS U524 ( .A(d_ff_Xn[5]), .B(n702), .Y(first_mux_X[5]) );
OR2X1TS U525 ( .A(d_ff_Xn[2]), .B(n702), .Y(first_mux_X[2]) );
XOR2XLTS U526 ( .A(d_ff2_Y[30]), .B(n755), .Y(sh_exp_y[7]) );
OAI21XLTS U527 ( .A0(n757), .A1(n769), .B0(n756), .Y(sh_exp_y[5]) );
XOR2XLTS U528 ( .A(d_ff2_X[30]), .B(n758), .Y(sh_exp_x[7]) );
OAI21XLTS U529 ( .A0(n760), .A1(n768), .B0(n759), .Y(sh_exp_x[5]) );
OAI21XLTS U530 ( .A0(ack_cordic), .A1(n637), .B0(n635), .Y(
inst_CORDIC_FSM_v3_state_next[7]) );
OR4X2TS U531 ( .A(inst_CORDIC_FSM_v3_state_reg[3]), .B(
inst_CORDIC_FSM_v3_state_reg[1]), .C(inst_CORDIC_FSM_v3_state_reg[0]),
.D(inst_CORDIC_FSM_v3_state_reg[5]), .Y(n605) );
BUFX4TS U532 ( .A(n646), .Y(n731) );
INVX2TS U533 ( .A(n697), .Y(n710) );
INVX2TS U534 ( .A(n731), .Y(n607) );
INVX2TS U535 ( .A(n607), .Y(n608) );
INVX2TS U536 ( .A(n607), .Y(n609) );
INVX2TS U537 ( .A(n620), .Y(n739) );
INVX4TS U538 ( .A(n620), .Y(n668) );
INVX2TS U539 ( .A(n605), .Y(n610) );
OAI21XLTS U540 ( .A0(cont_iter_out[0]), .A1(n537), .B0(n752), .Y(n521) );
INVX2TS U541 ( .A(n752), .Y(n751) );
OAI21XLTS U542 ( .A0(n609), .A1(n717), .B0(n636), .Y(
inst_CORDIC_FSM_v3_state_next[4]) );
NAND3X2TS U543 ( .A(n762), .B(n763), .C(n764), .Y(n695) );
BUFX4TS U544 ( .A(n772), .Y(n773) );
BUFX4TS U545 ( .A(n621), .Y(n781) );
BUFX4TS U546 ( .A(n621), .Y(n780) );
BUFX3TS U547 ( .A(n621), .Y(n622) );
BUFX3TS U548 ( .A(n604), .Y(n621) );
BUFX4TS U549 ( .A(n604), .Y(n775) );
BUFX4TS U550 ( .A(n775), .Y(n777) );
BUFX4TS U551 ( .A(n775), .Y(n782) );
BUFX4TS U552 ( .A(n775), .Y(n776) );
BUFX4TS U553 ( .A(n792), .Y(n778) );
BUFX4TS U554 ( .A(n622), .Y(n793) );
BUFX4TS U555 ( .A(n794), .Y(n787) );
BUFX4TS U556 ( .A(n791), .Y(n785) );
BUFX4TS U557 ( .A(n783), .Y(n792) );
NOR2X4TS U558 ( .A(n761), .B(n762), .Y(n747) );
AOI222X1TS U559 ( .A0(n722), .A1(d_ff3_sh_y_out[8]), .B0(n668), .B1(
d_ff3_sh_x_out[8]), .C0(n746), .C1(d_ff3_LUT_out[8]), .Y(n691) );
AOI222X1TS U560 ( .A0(n722), .A1(d_ff3_sh_y_out[12]), .B0(n668), .B1(
d_ff3_sh_x_out[12]), .C0(n746), .C1(d_ff3_LUT_out[12]), .Y(n692) );
AOI222X1TS U561 ( .A0(n722), .A1(d_ff3_sh_y_out[25]), .B0(n668), .B1(
d_ff3_sh_x_out[25]), .C0(n746), .C1(d_ff3_LUT_out[25]), .Y(n690) );
AOI222X1TS U562 ( .A0(n722), .A1(d_ff3_sh_y_out[24]), .B0(n743), .B1(
d_ff3_sh_x_out[24]), .C0(n746), .C1(d_ff3_LUT_out[24]), .Y(n689) );
BUFX4TS U563 ( .A(n646), .Y(n746) );
INVX2TS U564 ( .A(inst_CORDIC_FSM_v3_state_next[3]), .Y(n611) );
INVX2TS U565 ( .A(n611), .Y(n612) );
INVX2TS U566 ( .A(n606), .Y(n613) );
INVX4TS U567 ( .A(n620), .Y(n721) );
CLKINVX3TS U568 ( .A(n620), .Y(n684) );
INVX4TS U569 ( .A(n620), .Y(n743) );
NOR2X2TS U570 ( .A(n694), .B(n620), .Y(enab_d_ff4_Zn) );
NOR2X4TS U571 ( .A(n763), .B(n764), .Y(n720) );
BUFX4TS U572 ( .A(n770), .Y(n771) );
BUFX4TS U573 ( .A(n795), .Y(n774) );
BUFX3TS U574 ( .A(n604), .Y(n795) );
NOR3BX2TS U575 ( .AN(inst_CORDIC_FSM_v3_state_reg[7]), .B(
inst_CORDIC_FSM_v3_state_reg[2]), .C(n617), .Y(ready_cordic) );
OAI32X4TS U576 ( .A0(n615), .A1(d_ff1_operation_out), .A2(n613), .B0(
d_ff1_shift_region_flag_out_0_), .B1(n698), .Y(n699) );
OAI21XLTS U577 ( .A0(cont_iter_out[1]), .A1(n749), .B0(n634), .Y(n534) );
OAI21XLTS U578 ( .A0(n747), .A1(cont_iter_out[1]), .B0(n634), .Y(n536) );
AOI21X2TS U579 ( .A0(cont_iter_out[2]), .A1(n762), .B0(n623), .Y(n634) );
OR2X1TS U580 ( .A(d_ff_Xn[3]), .B(n702), .Y(first_mux_X[3]) );
OR2X1TS U581 ( .A(d_ff_Xn[12]), .B(n702), .Y(first_mux_X[12]) );
OR2X1TS U582 ( .A(d_ff_Xn[1]), .B(n702), .Y(first_mux_X[1]) );
INVX4TS U583 ( .A(n710), .Y(n709) );
NOR2XLTS U584 ( .A(n694), .B(n640), .Y(enab_d_ff4_Yn) );
OR2X1TS U585 ( .A(d_ff_Xn[16]), .B(n702), .Y(first_mux_X[16]) );
OR2X1TS U586 ( .A(d_ff_Xn[10]), .B(n702), .Y(first_mux_X[10]) );
OAI211XLTS U587 ( .A0(n628), .A1(n627), .B0(n626), .C0(n695), .Y(n527) );
NOR2X1TS U588 ( .A(inst_CORDIC_FSM_v3_state_reg[4]), .B(
inst_CORDIC_FSM_v3_state_reg[6]), .Y(n618) );
NAND2X1TS U589 ( .A(n610), .B(n618), .Y(n617) );
NOR3BX1TS U590 ( .AN(inst_CORDIC_FSM_v3_state_reg[2]), .B(
inst_CORDIC_FSM_v3_state_reg[7]), .C(n617), .Y(
inst_CORDIC_FSM_v3_state_next[3]) );
INVX2TS U591 ( .A(n747), .Y(n537) );
NAND2X1TS U592 ( .A(n761), .B(cont_iter_out[3]), .Y(n627) );
INVX2TS U593 ( .A(n627), .Y(n623) );
NAND2X1TS U594 ( .A(n537), .B(cont_iter_out[0]), .Y(n752) );
NOR2X1TS U595 ( .A(n623), .B(n751), .Y(n748) );
OAI211X1TS U596 ( .A0(cont_iter_out[3]), .A1(n763), .B0(n761), .C0(n764),
.Y(n750) );
OAI21XLTS U597 ( .A0(n748), .A1(n764), .B0(n750), .Y(n526) );
NAND2X1TS U598 ( .A(n720), .B(n761), .Y(n626) );
OAI31X1TS U599 ( .A0(cont_iter_out[3]), .A1(cont_iter_out[1]), .A2(n761),
.B0(n626), .Y(n528) );
OAI31X4TS U600 ( .A0(cont_iter_out[2]), .A1(cont_iter_out[3]), .A2(n763),
.B0(n537), .Y(n749) );
OAI21XLTS U601 ( .A0(n747), .A1(n764), .B0(n749), .Y(n531) );
OAI21XLTS U602 ( .A0(n764), .A1(n749), .B0(n627), .Y(n532) );
NOR3BX1TS U603 ( .AN(n618), .B(inst_CORDIC_FSM_v3_state_reg[7]), .C(
inst_CORDIC_FSM_v3_state_reg[2]), .Y(n631) );
NOR2X1TS U604 ( .A(inst_CORDIC_FSM_v3_state_reg[0]), .B(
inst_CORDIC_FSM_v3_state_reg[5]), .Y(n632) );
NOR2X1TS U605 ( .A(inst_CORDIC_FSM_v3_state_reg[1]), .B(n619), .Y(n625) );
NAND3BX1TS U606 ( .AN(inst_CORDIC_FSM_v3_state_reg[5]), .B(
inst_CORDIC_FSM_v3_state_reg[0]), .C(n625), .Y(n715) );
NAND2X1TS U607 ( .A(n629), .B(n715), .Y(enab_d_ff_RB1) );
INVX2TS U608 ( .A(ready_add_subt), .Y(n694) );
INVX2TS U609 ( .A(rst), .Y(n154) );
BUFX3TS U610 ( .A(n621), .Y(n786) );
BUFX3TS U611 ( .A(n621), .Y(n784) );
BUFX3TS U612 ( .A(n795), .Y(n783) );
BUFX3TS U613 ( .A(n770), .Y(n791) );
BUFX3TS U614 ( .A(n775), .Y(n779) );
BUFX3TS U615 ( .A(n622), .Y(n790) );
BUFX3TS U616 ( .A(n772), .Y(n794) );
BUFX3TS U617 ( .A(n604), .Y(n770) );
BUFX3TS U618 ( .A(n622), .Y(n789) );
BUFX3TS U619 ( .A(n604), .Y(n772) );
BUFX3TS U620 ( .A(n622), .Y(n788) );
NAND2X1TS U621 ( .A(n634), .B(n752), .Y(n523) );
NOR3BX1TS U622 ( .AN(n610), .B(inst_CORDIC_FSM_v3_state_reg[7]), .C(
inst_CORDIC_FSM_v3_state_reg[2]), .Y(n624) );
NAND3BX1TS U623 ( .AN(inst_CORDIC_FSM_v3_state_reg[4]), .B(
inst_CORDIC_FSM_v3_state_reg[6]), .C(n624), .Y(n641) );
INVX2TS U624 ( .A(n641), .Y(enab_cont_iter) );
INVX2TS U625 ( .A(ready_cordic), .Y(n637) );
NAND2X1TS U626 ( .A(n637), .B(n635), .Y(enab_d_ff5_data_out) );
NAND3BX1TS U627 ( .AN(inst_CORDIC_FSM_v3_state_reg[0]), .B(
inst_CORDIC_FSM_v3_state_reg[5]), .C(n625), .Y(n718) );
NAND2X1TS U628 ( .A(n717), .B(n718), .Y(beg_add_subt) );
NAND2X1TS U629 ( .A(n767), .B(cont_iter_out[0]), .Y(intadd_422_CI) );
OAI21XLTS U630 ( .A0(cont_iter_out[0]), .A1(n767), .B0(intadd_422_CI), .Y(
sh_exp_y[0]) );
NAND2X1TS U631 ( .A(n616), .B(cont_iter_out[0]), .Y(intadd_421_CI) );
OAI21XLTS U632 ( .A0(cont_iter_out[0]), .A1(n616), .B0(intadd_421_CI), .Y(
sh_exp_x[0]) );
NOR2X1TS U633 ( .A(cont_iter_out[0]), .B(cont_iter_out[1]), .Y(n628) );
NOR2X1TS U634 ( .A(d_ff2_X[27]), .B(intadd_421_n1), .Y(n760) );
OR3X1TS U635 ( .A(d_ff2_X[28]), .B(d_ff2_X[27]), .C(intadd_421_n1), .Y(n759)
);
NOR2X1TS U636 ( .A(d_ff2_Y[27]), .B(intadd_422_n1), .Y(n757) );
OR3X1TS U637 ( .A(d_ff2_Y[28]), .B(d_ff2_Y[27]), .C(intadd_422_n1), .Y(n756)
);
NAND2X1TS U638 ( .A(cont_iter_out[2]), .B(n720), .Y(n719) );
CLKAND2X2TS U639 ( .A(n719), .B(n762), .Y(n529) );
NOR2X1TS U640 ( .A(n762), .B(n719), .Y(n630) );
NAND2X1TS U641 ( .A(cont_var_out[0]), .B(cont_var_out[1]), .Y(n716) );
BUFX3TS U642 ( .A(n703), .Y(n705) );
INVX2TS U643 ( .A(n703), .Y(n633) );
OAI21X1TS U644 ( .A0(n747), .A1(n764), .B0(n634), .Y(n535) );
OR2X1TS U645 ( .A(n535), .B(n751), .Y(n522) );
INVX2TS U646 ( .A(n636), .Y(enab_RB3) );
NOR4X1TS U647 ( .A(enab_cont_iter), .B(enab_RB3), .C(enab_d_ff_RB1), .D(
beg_add_subt), .Y(n638) );
AOI32X1TS U648 ( .A0(n638), .A1(n637), .A2(n611), .B0(ready_cordic), .B1(
ack_cordic), .Y(n639) );
INVX2TS U649 ( .A(n753), .Y(n754) );
NAND2X1TS U650 ( .A(n754), .B(cont_var_out[1]), .Y(n642) );
INVX2TS U651 ( .A(n643), .Y(add_subt_dataB[26]) );
INVX4TS U652 ( .A(n640), .Y(n669) );
AOI222X1TS U653 ( .A0(n669), .A1(d_ff2_X[11]), .B0(n668), .B1(d_ff2_Y[11]),
.C0(n646), .C1(d_ff2_Z[11]), .Y(n644) );
INVX2TS U654 ( .A(n644), .Y(add_subt_dataA[11]) );
AOI222X1TS U655 ( .A0(n669), .A1(d_ff2_X[17]), .B0(n721), .B1(d_ff2_Y[17]),
.C0(n646), .C1(d_ff2_Z[17]), .Y(n645) );
INVX2TS U656 ( .A(n645), .Y(add_subt_dataA[17]) );
INVX2TS U657 ( .A(n647), .Y(add_subt_dataA[23]) );
AOI222X1TS U658 ( .A0(n669), .A1(d_ff2_X[19]), .B0(n668), .B1(d_ff2_Y[19]),
.C0(n646), .C1(d_ff2_Z[19]), .Y(n648) );
INVX2TS U659 ( .A(n648), .Y(add_subt_dataA[19]) );
INVX2TS U660 ( .A(n649), .Y(add_subt_dataA[12]) );
INVX4TS U661 ( .A(n640), .Y(n685) );
AOI222X1TS U662 ( .A0(n685), .A1(d_ff3_sh_y_out[2]), .B0(n743), .B1(
d_ff3_sh_x_out[2]), .C0(n608), .C1(d_ff3_LUT_out[2]), .Y(n650) );
INVX2TS U663 ( .A(n650), .Y(add_subt_dataB[2]) );
INVX2TS U664 ( .A(n651), .Y(add_subt_dataA[26]) );
INVX2TS U665 ( .A(n652), .Y(add_subt_dataA[27]) );
INVX2TS U666 ( .A(n653), .Y(add_subt_dataA[25]) );
AOI222X1TS U667 ( .A0(n669), .A1(d_ff2_X[14]), .B0(n668), .B1(d_ff2_Y[14]),
.C0(n646), .C1(d_ff2_Z[14]), .Y(n654) );
INVX2TS U668 ( .A(n654), .Y(add_subt_dataA[14]) );
AOI222X1TS U669 ( .A0(n685), .A1(d_ff2_X[0]), .B0(n684), .B1(d_ff2_Y[0]),
.C0(n608), .C1(d_ff2_Z[0]), .Y(n655) );
INVX2TS U670 ( .A(n655), .Y(add_subt_dataA[0]) );
AOI222X1TS U671 ( .A0(n669), .A1(d_ff2_X[21]), .B0(n684), .B1(d_ff2_Y[21]),
.C0(n646), .C1(d_ff2_Z[21]), .Y(n656) );
INVX2TS U672 ( .A(n656), .Y(add_subt_dataA[21]) );
AOI222X1TS U673 ( .A0(n685), .A1(d_ff3_sh_y_out[0]), .B0(n739), .B1(
d_ff3_sh_x_out[0]), .C0(n608), .C1(d_ff3_LUT_out[0]), .Y(n657) );
INVX2TS U674 ( .A(n657), .Y(add_subt_dataB[0]) );
AOI222X1TS U675 ( .A0(n685), .A1(d_ff3_sh_y_out[1]), .B0(n743), .B1(
d_ff3_sh_x_out[1]), .C0(n608), .C1(d_ff3_LUT_out[1]), .Y(n658) );
INVX2TS U676 ( .A(n658), .Y(add_subt_dataB[1]) );
INVX2TS U677 ( .A(n659), .Y(add_subt_dataA[15]) );
AOI222X1TS U678 ( .A0(n669), .A1(d_ff2_X[16]), .B0(n668), .B1(d_ff2_Y[16]),
.C0(n646), .C1(d_ff2_Z[16]), .Y(n660) );
INVX2TS U679 ( .A(n660), .Y(add_subt_dataA[16]) );
INVX2TS U680 ( .A(n661), .Y(add_subt_dataA[29]) );
INVX2TS U681 ( .A(n662), .Y(add_subt_dataA[18]) );
AOI222X1TS U682 ( .A0(n685), .A1(d_ff2_X[31]), .B0(n743), .B1(d_ff2_Y[31]),
.C0(n731), .C1(d_ff2_Z[31]), .Y(n663) );
INVX2TS U683 ( .A(n663), .Y(add_subt_dataA[31]) );
AOI222X1TS U684 ( .A0(n669), .A1(d_ff2_X[20]), .B0(n668), .B1(d_ff2_Y[20]),
.C0(n646), .C1(d_ff2_Z[20]), .Y(n664) );
INVX2TS U685 ( .A(n664), .Y(add_subt_dataA[20]) );
AOI222X1TS U686 ( .A0(n685), .A1(d_ff2_X[28]), .B0(n721), .B1(d_ff2_Y[28]),
.C0(n731), .C1(d_ff2_Z[28]), .Y(n665) );
INVX2TS U687 ( .A(n665), .Y(add_subt_dataA[28]) );
AOI222X1TS U688 ( .A0(n669), .A1(d_ff2_X[22]), .B0(n739), .B1(d_ff2_Y[22]),
.C0(n646), .C1(d_ff2_Z[22]), .Y(n666) );
INVX2TS U689 ( .A(n666), .Y(add_subt_dataA[22]) );
INVX2TS U690 ( .A(n667), .Y(add_subt_dataA[24]) );
AOI222X1TS U691 ( .A0(n669), .A1(d_ff2_X[13]), .B0(n668), .B1(d_ff2_Y[13]),
.C0(n646), .C1(d_ff2_Z[13]), .Y(n670) );
INVX2TS U692 ( .A(n670), .Y(add_subt_dataA[13]) );
INVX2TS U693 ( .A(n671), .Y(add_subt_dataA[30]) );
AOI222X1TS U694 ( .A0(n744), .A1(d_ff2_X[10]), .B0(n721), .B1(d_ff2_Y[10]),
.C0(n731), .C1(d_ff2_Z[10]), .Y(n672) );
INVX2TS U695 ( .A(n672), .Y(add_subt_dataA[10]) );
INVX2TS U696 ( .A(n673), .Y(add_subt_dataA[6]) );
INVX2TS U697 ( .A(n674), .Y(add_subt_dataA[3]) );
INVX2TS U698 ( .A(n675), .Y(add_subt_dataA[5]) );
AOI222X1TS U699 ( .A0(n744), .A1(d_ff2_X[2]), .B0(n743), .B1(d_ff2_Y[2]),
.C0(n608), .C1(d_ff2_Z[2]), .Y(n676) );
INVX2TS U700 ( .A(n676), .Y(add_subt_dataA[2]) );
AOI222X1TS U701 ( .A0(n744), .A1(d_ff2_X[8]), .B0(n721), .B1(d_ff2_Y[8]),
.C0(n608), .C1(d_ff2_Z[8]), .Y(n677) );
INVX2TS U702 ( .A(n677), .Y(add_subt_dataA[8]) );
AOI222X1TS U703 ( .A0(n744), .A1(d_ff2_X[4]), .B0(n743), .B1(d_ff2_Y[4]),
.C0(n731), .C1(d_ff2_Z[4]), .Y(n678) );
INVX2TS U704 ( .A(n678), .Y(add_subt_dataA[4]) );
AOI222X1TS U705 ( .A0(n744), .A1(d_ff2_X[9]), .B0(n739), .B1(d_ff2_Y[9]),
.C0(n608), .C1(d_ff2_Z[9]), .Y(n679) );
INVX2TS U706 ( .A(n679), .Y(add_subt_dataA[9]) );
AOI222X1TS U707 ( .A0(n744), .A1(d_ff2_X[1]), .B0(n684), .B1(d_ff2_Y[1]),
.C0(n731), .C1(d_ff2_Z[1]), .Y(n680) );
INVX2TS U708 ( .A(n680), .Y(add_subt_dataA[1]) );
AOI222X1TS U709 ( .A0(n744), .A1(d_ff2_X[7]), .B0(n721), .B1(d_ff2_Y[7]),
.C0(n608), .C1(d_ff2_Z[7]), .Y(n681) );
INVX2TS U710 ( .A(n681), .Y(add_subt_dataA[7]) );
INVX2TS U711 ( .A(n682), .Y(add_subt_dataB[9]) );
INVX2TS U712 ( .A(n683), .Y(add_subt_dataB[6]) );
AOI222X1TS U713 ( .A0(n685), .A1(d_ff3_sh_y_out[4]), .B0(n668), .B1(
d_ff3_sh_x_out[4]), .C0(n746), .C1(d_ff3_LUT_out[4]), .Y(n686) );
INVX2TS U714 ( .A(n686), .Y(add_subt_dataB[4]) );
INVX2TS U715 ( .A(n687), .Y(add_subt_dataB[10]) );
INVX2TS U716 ( .A(n688), .Y(add_subt_dataB[21]) );
INVX2TS U717 ( .A(n689), .Y(add_subt_dataB[24]) );
INVX2TS U718 ( .A(n690), .Y(add_subt_dataB[25]) );
INVX2TS U719 ( .A(n691), .Y(add_subt_dataB[8]) );
INVX2TS U720 ( .A(n692), .Y(add_subt_dataB[12]) );
INVX2TS U721 ( .A(n693), .Y(add_subt_dataB[23]) );
NOR3XLTS U722 ( .A(cont_var_out[0]), .B(cont_var_out[1]), .C(n694), .Y(
enab_d_ff4_Xn) );
AOI32X1TS U724 ( .A0(cont_iter_out[3]), .A1(n695), .A2(n764), .B0(
cont_iter_out[2]), .B1(n695), .Y(data_out_LUT[4]) );
OAI22X1TS U725 ( .A0(cont_iter_out[3]), .A1(n719), .B0(cont_iter_out[2]),
.B1(n720), .Y(data_out_LUT[25]) );
NAND2X1TS U726 ( .A(d_ff1_operation_out), .B(n613), .Y(n698) );
XOR2X1TS U727 ( .A(n615), .B(n696), .Y(n697) );
BUFX3TS U728 ( .A(n710), .Y(n708) );
AOI22X1TS U729 ( .A0(n709), .A1(d_ff_Yn[31]), .B0(d_ff_Xn[31]), .B1(n708),
.Y(n700) );
XNOR2X1TS U730 ( .A(n700), .B(n699), .Y(fmtted_Result_31_) );
INVX4TS U731 ( .A(n703), .Y(n704) );
NOR2BX1TS U732 ( .AN(d_ff_Yn[0]), .B(n704), .Y(first_mux_Y[0]) );
NOR2BX1TS U733 ( .AN(d_ff_Yn[1]), .B(n704), .Y(first_mux_Y[1]) );
INVX4TS U734 ( .A(n703), .Y(n714) );
NOR2BX1TS U735 ( .AN(d_ff_Yn[2]), .B(n714), .Y(first_mux_Y[2]) );
INVX4TS U736 ( .A(n703), .Y(n706) );
NOR2BX1TS U737 ( .AN(d_ff_Yn[3]), .B(n706), .Y(first_mux_Y[3]) );
NOR2BX1TS U738 ( .AN(d_ff_Yn[4]), .B(n714), .Y(first_mux_Y[4]) );
NOR2BX1TS U739 ( .AN(d_ff_Yn[5]), .B(n706), .Y(first_mux_Y[5]) );
INVX4TS U740 ( .A(n703), .Y(n713) );
NOR2BX1TS U741 ( .AN(d_ff_Yn[6]), .B(n713), .Y(first_mux_Y[6]) );
NOR2BX1TS U742 ( .AN(d_ff_Yn[7]), .B(n713), .Y(first_mux_Y[7]) );
NOR2BX1TS U743 ( .AN(d_ff_Yn[8]), .B(n713), .Y(first_mux_Y[8]) );
INVX4TS U744 ( .A(n703), .Y(n701) );
NOR2BX1TS U745 ( .AN(d_ff_Yn[9]), .B(n701), .Y(first_mux_Y[9]) );
NOR2BX1TS U746 ( .AN(d_ff_Yn[10]), .B(n701), .Y(first_mux_Y[10]) );
NOR2BX1TS U747 ( .AN(d_ff_Yn[11]), .B(n701), .Y(first_mux_Y[11]) );
NOR2BX1TS U748 ( .AN(d_ff_Yn[12]), .B(n701), .Y(first_mux_Y[12]) );
NOR2BX1TS U749 ( .AN(d_ff_Yn[13]), .B(n701), .Y(first_mux_Y[13]) );
NOR2BX1TS U750 ( .AN(d_ff_Yn[14]), .B(n701), .Y(first_mux_Y[14]) );
NOR2BX1TS U751 ( .AN(d_ff_Yn[15]), .B(n701), .Y(first_mux_Y[15]) );
NOR2BX1TS U752 ( .AN(d_ff_Yn[16]), .B(n701), .Y(first_mux_Y[16]) );
NOR2BX1TS U753 ( .AN(d_ff_Yn[17]), .B(n701), .Y(first_mux_Y[17]) );
NOR2BX1TS U754 ( .AN(d_ff_Yn[18]), .B(n701), .Y(first_mux_Y[18]) );
NOR2BX1TS U755 ( .AN(d_ff_Yn[19]), .B(n701), .Y(first_mux_Y[19]) );
NOR2BX1TS U756 ( .AN(d_ff_Yn[20]), .B(n701), .Y(first_mux_Y[20]) );
NOR2BX1TS U757 ( .AN(d_ff_Yn[21]), .B(n701), .Y(first_mux_Y[21]) );
NOR2BX1TS U758 ( .AN(d_ff_Yn[22]), .B(n701), .Y(first_mux_Y[22]) );
NOR2BX1TS U759 ( .AN(d_ff_Yn[23]), .B(n701), .Y(first_mux_Y[23]) );
NOR2BX1TS U760 ( .AN(d_ff_Yn[24]), .B(n713), .Y(first_mux_Y[24]) );
NOR2BX1TS U761 ( .AN(d_ff_Yn[25]), .B(n713), .Y(first_mux_Y[25]) );
NOR2BX1TS U762 ( .AN(d_ff_Yn[26]), .B(n713), .Y(first_mux_Y[26]) );
NOR2BX1TS U763 ( .AN(d_ff_Yn[27]), .B(n713), .Y(first_mux_Y[27]) );
NOR2BX1TS U764 ( .AN(d_ff_Yn[28]), .B(n713), .Y(first_mux_Y[28]) );
NOR2BX1TS U765 ( .AN(d_ff_Yn[29]), .B(n713), .Y(first_mux_Y[29]) );
NOR2BX1TS U766 ( .AN(d_ff_Yn[30]), .B(n713), .Y(first_mux_Y[30]) );
NOR2BX1TS U767 ( .AN(d_ff_Yn[31]), .B(n713), .Y(first_mux_Y[31]) );
BUFX3TS U768 ( .A(n703), .Y(n707) );
BUFX3TS U769 ( .A(n708), .Y(n711) );
INVX2TS U770 ( .A(n708), .Y(n712) );
NOR2BX1TS U771 ( .AN(d_ff_Xn[0]), .B(n714), .Y(first_mux_X[0]) );
NOR2BX1TS U772 ( .AN(d_ff_Xn[4]), .B(n714), .Y(first_mux_X[4]) );
NOR2BX1TS U773 ( .AN(d_ff_Xn[8]), .B(n714), .Y(first_mux_X[8]) );
NOR2BX1TS U774 ( .AN(d_ff_Xn[9]), .B(n714), .Y(first_mux_X[9]) );
NOR2BX1TS U775 ( .AN(d_ff_Xn[11]), .B(n714), .Y(first_mux_X[11]) );
NOR2BX1TS U776 ( .AN(d_ff_Xn[15]), .B(n714), .Y(first_mux_X[15]) );
NOR2BX1TS U777 ( .AN(d_ff_Xn[18]), .B(n714), .Y(first_mux_X[18]) );
NOR2BX1TS U778 ( .AN(d_ff_Xn[21]), .B(n713), .Y(first_mux_X[21]) );
NOR2BX1TS U779 ( .AN(d_ff_Xn[22]), .B(n713), .Y(first_mux_X[22]) );
NOR2BX1TS U780 ( .AN(d_ff_Xn[23]), .B(n713), .Y(first_mux_X[23]) );
NOR2BX1TS U781 ( .AN(d_ff_Xn[30]), .B(n713), .Y(first_mux_X[30]) );
NOR2BX1TS U782 ( .AN(d_ff_Xn[31]), .B(n714), .Y(first_mux_X[31]) );
NOR2BX1TS U783 ( .AN(beg_fsm_cordic), .B(n715), .Y(
inst_CORDIC_FSM_v3_state_next[1]) );
OAI22X1TS U784 ( .A0(enab_d_ff4_Zn), .A1(n718), .B0(n717), .B1(n716), .Y(
inst_CORDIC_FSM_v3_state_next[5]) );
NOR2BX1TS U785 ( .AN(enab_d_ff4_Zn), .B(n718), .Y(
inst_CORDIC_FSM_v3_state_next[6]) );
OA21XLTS U786 ( .A0(cont_iter_out[2]), .A1(n720), .B0(n719), .Y(ITER_CONT_N4) );
XOR2XLTS U787 ( .A(d_ff3_sign_out), .B(cont_var_out[0]), .Y(op_add_subt) );
AO22XLTS U788 ( .A0(n722), .A1(d_ff3_sh_y_out[31]), .B0(n721), .B1(
d_ff3_sh_x_out[31]), .Y(add_subt_dataB[31]) );
AO22XLTS U789 ( .A0(n722), .A1(d_ff3_sh_y_out[30]), .B0(n743), .B1(
d_ff3_sh_x_out[30]), .Y(add_subt_dataB[30]) );
AOI22X1TS U790 ( .A0(n740), .A1(d_ff3_sh_y_out[29]), .B0(n721), .B1(
d_ff3_sh_x_out[29]), .Y(n723) );
NAND2X1TS U791 ( .A(n646), .B(d_ff3_LUT_out[27]), .Y(n725) );
NAND2X1TS U792 ( .A(n723), .B(n725), .Y(add_subt_dataB[29]) );
AOI22X1TS U793 ( .A0(n740), .A1(d_ff3_sh_y_out[28]), .B0(n721), .B1(
d_ff3_sh_x_out[28]), .Y(n724) );
NAND2X1TS U794 ( .A(n724), .B(n725), .Y(add_subt_dataB[28]) );
AOI22X1TS U795 ( .A0(n740), .A1(d_ff3_sh_y_out[27]), .B0(n739), .B1(
d_ff3_sh_x_out[27]), .Y(n726) );
NAND2X1TS U796 ( .A(n726), .B(n725), .Y(add_subt_dataB[27]) );
AOI22X1TS U797 ( .A0(n740), .A1(d_ff3_sh_y_out[22]), .B0(n743), .B1(
d_ff3_sh_x_out[22]), .Y(n727) );
OAI2BB1X1TS U798 ( .A0N(n609), .A1N(d_ff3_LUT_out[19]), .B0(n727), .Y(
add_subt_dataB[22]) );
AOI22X1TS U799 ( .A0(n740), .A1(d_ff3_sh_y_out[20]), .B0(n721), .B1(
d_ff3_sh_x_out[20]), .Y(n728) );
NAND2X1TS U800 ( .A(n646), .B(d_ff3_LUT_out[15]), .Y(n734) );
NAND2X1TS U801 ( .A(n728), .B(n734), .Y(add_subt_dataB[20]) );
AOI22X1TS U802 ( .A0(n740), .A1(d_ff3_sh_y_out[19]), .B0(n721), .B1(
d_ff3_sh_x_out[19]), .Y(n729) );
OAI2BB1X1TS U803 ( .A0N(n746), .A1N(d_ff3_LUT_out[19]), .B0(n729), .Y(
add_subt_dataB[19]) );
AOI22X1TS U804 ( .A0(n740), .A1(d_ff3_sh_y_out[18]), .B0(n743), .B1(
d_ff3_sh_x_out[18]), .Y(n730) );
OAI2BB1X1TS U805 ( .A0N(n731), .A1N(d_ff3_LUT_out[13]), .B0(n730), .Y(
add_subt_dataB[18]) );
AOI22X1TS U806 ( .A0(n740), .A1(d_ff3_sh_y_out[17]), .B0(n684), .B1(
d_ff3_sh_x_out[17]), .Y(n732) );
NAND2X1TS U807 ( .A(n732), .B(n734), .Y(add_subt_dataB[17]) );
AOI22X1TS U808 ( .A0(n740), .A1(d_ff3_sh_y_out[16]), .B0(n743), .B1(
d_ff3_sh_x_out[16]), .Y(n733) );
OAI2BB1X1TS U809 ( .A0N(n746), .A1N(d_ff3_LUT_out[3]), .B0(n733), .Y(
add_subt_dataB[16]) );
AOI22X1TS U810 ( .A0(n740), .A1(d_ff3_sh_y_out[15]), .B0(n739), .B1(
d_ff3_sh_x_out[15]), .Y(n735) );
NAND2X1TS U811 ( .A(n735), .B(n734), .Y(add_subt_dataB[15]) );
AOI22X1TS U812 ( .A0(n740), .A1(d_ff3_sh_y_out[14]), .B0(n721), .B1(
d_ff3_sh_x_out[14]), .Y(n736) );
OAI2BB1X1TS U813 ( .A0N(n609), .A1N(d_ff3_LUT_out[5]), .B0(n736), .Y(
add_subt_dataB[14]) );
AOI22X1TS U814 ( .A0(n744), .A1(d_ff3_sh_y_out[13]), .B0(n684), .B1(
d_ff3_sh_x_out[13]), .Y(n737) );
OAI2BB1X1TS U815 ( .A0N(n609), .A1N(d_ff3_LUT_out[13]), .B0(n737), .Y(
add_subt_dataB[13]) );
AOI22X1TS U816 ( .A0(n740), .A1(d_ff3_sh_y_out[11]), .B0(n743), .B1(
d_ff3_sh_x_out[11]), .Y(n738) );
OAI2BB1X1TS U817 ( .A0N(n746), .A1N(d_ff3_LUT_out[7]), .B0(n738), .Y(
add_subt_dataB[11]) );
AOI22X1TS U818 ( .A0(n740), .A1(d_ff3_sh_y_out[7]), .B0(n721), .B1(
d_ff3_sh_x_out[7]), .Y(n741) );
OAI2BB1X1TS U819 ( .A0N(n731), .A1N(d_ff3_LUT_out[7]), .B0(n741), .Y(
add_subt_dataB[7]) );
AOI22X1TS U820 ( .A0(n744), .A1(d_ff3_sh_y_out[5]), .B0(n721), .B1(
d_ff3_sh_x_out[5]), .Y(n742) );
OAI2BB1X1TS U821 ( .A0N(n746), .A1N(d_ff3_LUT_out[5]), .B0(n742), .Y(
add_subt_dataB[5]) );
AOI22X1TS U822 ( .A0(n744), .A1(d_ff3_sh_y_out[3]), .B0(n743), .B1(
d_ff3_sh_x_out[3]), .Y(n745) );
OAI2BB1X1TS U823 ( .A0N(n746), .A1N(d_ff3_LUT_out[3]), .B0(n745), .Y(
add_subt_dataB[3]) );
AOI22X1TS U824 ( .A0(cont_iter_out[1]), .A1(n749), .B0(n747), .B1(n764), .Y(
n533) );
AOI22X1TS U825 ( .A0(cont_iter_out[1]), .A1(n749), .B0(n748), .B1(n764), .Y(
n525) );
OAI2BB1X1TS U826 ( .A0N(cont_iter_out[1]), .A1N(n523), .B0(n750), .Y(n524)
);
AOI22X1TS U827 ( .A0(cont_iter_out[1]), .A1(n752), .B0(n751), .B1(n764), .Y(
n520) );
AOI22X1TS U828 ( .A0(n754), .A1(n765), .B0(cont_var_out[0]), .B1(n753), .Y(
n518) );
NOR2XLTS U830 ( .A(d_ff2_Y[29]), .B(n756), .Y(n755) );
XNOR2X1TS U831 ( .A(d_ff2_Y[29]), .B(n756), .Y(sh_exp_y[6]) );
AO21XLTS U832 ( .A0(intadd_422_n1), .A1(d_ff2_Y[27]), .B0(n757), .Y(
sh_exp_y[4]) );
NOR2XLTS U833 ( .A(d_ff2_X[29]), .B(n759), .Y(n758) );
XNOR2X1TS U834 ( .A(d_ff2_X[29]), .B(n759), .Y(sh_exp_x[6]) );
AO21XLTS U835 ( .A0(intadd_421_n1), .A1(d_ff2_X[27]), .B0(n760), .Y(
sh_exp_x[4]) );
initial $sdf_annotate("CORDIC_Arch3v1_ASIC_fpu_syn_constraints_clk20.tcl_GATED_syn.sdf");
endmodule
|
module sky130_fd_sc_hvl__inv (
//# {{data|Data Signals}}
input A ,
output Y ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
|
module cheat(
input clk,
input [7:0] SNES_PA,
input [23:0] SNES_ADDR,
input [7:0] SNES_DATA,
input SNES_wr_strobe,
input SNES_rd_strobe,
input SNES_reset_strobe,
input snescmd_enable,
input nmicmd_enable,
input return_vector_enable,
input branch1_enable,
input branch2_enable,
input branch3_enable,
input pad_latch,
input snes_ajr,
input SNES_cycle_start,
input [2:0] pgm_idx,
input pgm_we,
input [31:0] pgm_in,
output [7:0] data_out,
output cheat_hit,
output snescmd_unlock
);
//`define IRQ_HOOK_ENABLE
wire snescmd_wr_strobe = snescmd_enable & SNES_wr_strobe;
reg cheat_enable = 0;
reg nmi_enable = 0;
reg irq_enable = 0;
reg holdoff_enable = 0; // temp disable hooks after reset
reg buttons_enable = 0;
reg wram_present = 0;
wire branch_wram = cheat_enable & wram_present;
reg auto_nmi_enable = 1;
reg auto_nmi_enable_sync = 0;
`ifdef IRQ_HOOK_ENABLE
reg auto_irq_enable = 0;
reg auto_irq_enable_sync = 0;
`endif
reg hook_enable_sync = 0;
reg [1:0] sync_delay = 2'b10;
reg [4:0] nmi_usage = 5'h00;
`ifdef IRQ_HOOK_ENABLE
reg [4:0] irq_usage = 5'h00;
`endif
reg [20:0] usage_count = 21'h1fffff;
reg [29:0] hook_enable_count = 0;
reg hook_disable = 0;
reg [1:0] vector_unlock_r = 0;
wire vector_unlock = |vector_unlock_r;
reg [1:0] reset_unlock_r = 2'b10;
wire reset_unlock = |reset_unlock_r;
reg [23:0] cheat_addr[5:0];
reg [7:0] cheat_data[5:0];
reg [5:0] cheat_enable_mask;
reg snescmd_unlock_r = 0;
assign snescmd_unlock = snescmd_unlock_r;
reg [7:0] nmicmd = 0;
reg [7:0] return_vector = 8'hea;
reg [7:0] branch1_offset = 8'h00;
reg [7:0] branch2_offset = 8'h00;
reg [7:0] branch3_offset = 8'h04;
reg [15:0] pad_data = 0;
wire [5:0] cheat_match_bits ={(cheat_enable_mask[5] & (SNES_ADDR == cheat_addr[5])),
(cheat_enable_mask[4] & (SNES_ADDR == cheat_addr[4])),
(cheat_enable_mask[3] & (SNES_ADDR == cheat_addr[3])),
(cheat_enable_mask[2] & (SNES_ADDR == cheat_addr[2])),
(cheat_enable_mask[1] & (SNES_ADDR == cheat_addr[1])),
(cheat_enable_mask[0] & (SNES_ADDR == cheat_addr[0]))};
wire cheat_addr_match = |cheat_match_bits;
wire [1:0] nmi_match_bits = {SNES_ADDR == 24'h00FFEA, SNES_ADDR == 24'h00FFEB};
`ifdef IRQ_HOOK_ENABLE
wire [1:0] irq_match_bits = {SNES_ADDR == 24'h00FFEE, SNES_ADDR == 24'h00FFEF};
`endif
wire [1:0] rst_match_bits = {SNES_ADDR == 24'h00FFFC, SNES_ADDR == 24'h00FFFD};
wire nmi_addr_match = |nmi_match_bits;
`ifdef IRQ_HOOK_ENABLE
wire irq_addr_match = |irq_match_bits;
`endif
wire rst_addr_match = |rst_match_bits;
wire hook_enable = ~|hook_enable_count;
assign data_out = cheat_match_bits[0] ? cheat_data[0]
: cheat_match_bits[1] ? cheat_data[1]
: cheat_match_bits[2] ? cheat_data[2]
: cheat_match_bits[3] ? cheat_data[3]
: cheat_match_bits[4] ? cheat_data[4]
: cheat_match_bits[5] ? cheat_data[5]
: nmi_match_bits[1] ? 8'h10
`ifdef IRQ_HOOK_ENABLE
: irq_match_bits[1] ? 8'h10
`endif
: rst_match_bits[1] ? 8'h7D
: nmicmd_enable ? nmicmd
: return_vector_enable ? return_vector
: branch1_enable ? branch1_offset
: branch2_enable ? branch2_offset
: branch3_enable ? branch3_offset
: 8'h2a;
assign cheat_hit = (snescmd_unlock & hook_enable_sync & (nmicmd_enable | return_vector_enable | branch1_enable | branch2_enable | branch3_enable))
| (reset_unlock & rst_addr_match)
| (cheat_enable & cheat_addr_match)
| (hook_enable_sync & (((auto_nmi_enable_sync & nmi_enable) & nmi_addr_match & vector_unlock)
`ifdef IRQ_HOOK_ENABLE
|((auto_irq_enable_sync & irq_enable) & irq_addr_match & vector_unlock)
`endif
));
// irq/nmi detect based on CPU access pattern
// 4 writes (mirrored to B bus) signify that the CPU pushes PB, PC and
// SR to the stack and is going to read the vector address in the next
// two cycles.
// B bus mirror is used (combined with A BUS /WR!) so the write pattern
// cannot be confused with backwards DMA transfers.
reg [7:0] next_pa_addr = 0;
reg [2:0] cpu_push_cnt = 0;
always @(posedge clk) begin
if(SNES_reset_strobe) begin
cpu_push_cnt <= 0;
end else if(SNES_wr_strobe) begin
cpu_push_cnt <= cpu_push_cnt + 1;
if(cpu_push_cnt == 3'b0) begin
next_pa_addr <= SNES_PA - 1;
end else begin
if(SNES_PA == next_pa_addr) begin
next_pa_addr <= next_pa_addr - 1;
end else begin
cpu_push_cnt <= 3'b0;
end
end
end else if(SNES_rd_strobe) begin
cpu_push_cnt <= 3'b0;
end
end
// make patched vectors visible for last cycles of NMI/IRQ handling only
always @(posedge clk) begin
if(SNES_reset_strobe) begin
vector_unlock_r <= 2'b00;
end else if(SNES_rd_strobe) begin
if(hook_enable_sync
& ((auto_nmi_enable_sync & nmi_enable & nmi_match_bits[1])
`ifdef IRQ_HOOK_ENABLE
|(auto_irq_enable_sync & irq_enable & irq_match_bits[1])
`endif
)
& cpu_push_cnt == 4) begin
vector_unlock_r <= 2'b11;
end else if(|vector_unlock_r) begin
vector_unlock_r <= vector_unlock_r - 1;
end
end
end
// make patched reset vector visible for first fetch only
// (including masked read by Ultra16)
always @(posedge clk) begin
if(SNES_reset_strobe) begin
reset_unlock_r <= 2'b11;
end else if(SNES_cycle_start) begin
if(rst_addr_match & |reset_unlock_r) begin
reset_unlock_r <= reset_unlock_r - 1;
end
end
end
reg snescmd_unlock_disable_strobe = 1'b0;
reg [6:0] snescmd_unlock_disable_countdown = 0;
reg snescmd_unlock_disable = 0;
always @(posedge clk) begin
if(SNES_reset_strobe) begin
snescmd_unlock_r <= 0;
snescmd_unlock_disable <= 0;
end else begin
if(SNES_rd_strobe) begin
// *** GAME -> INGAME HOOK ***
if(hook_enable_sync
& ((auto_nmi_enable_sync & nmi_enable & nmi_match_bits[1])
`ifdef IRQ_HOOK_ENABLE
|(auto_irq_enable_sync & irq_enable & irq_match_bits[1])
`endif
)
& cpu_push_cnt == 4) begin
// remember where we came from (IRQ/NMI) for hook exit
return_vector <= SNES_ADDR[7:0];
snescmd_unlock_r <= 1;
end
if(rst_match_bits[1] & |reset_unlock_r) begin
snescmd_unlock_r <= 1;
end
end
// give some time to exit snescmd memory and jump to original vector
// sta @NMI_VECT_DISABLE 1-2 (after effective write)
// jmp ($ffxx) 3 (excluding address fetch)
// *** (INGAME HOOK -> GAME) ***
if(SNES_cycle_start) begin
if(snescmd_unlock_disable) begin
if(|snescmd_unlock_disable_countdown) begin
snescmd_unlock_disable_countdown <= snescmd_unlock_disable_countdown - 1;
end else if(snescmd_unlock_disable_countdown == 0) begin
snescmd_unlock_r <= 0;
snescmd_unlock_disable <= 0;
end
end
end
if(snescmd_unlock_disable_strobe) begin
snescmd_unlock_disable_countdown <= 7'd6;
snescmd_unlock_disable <= 1;
end
end
end
always @(posedge clk) usage_count <= usage_count - 1;
// Try and autoselect NMI or IRQ hook
always @(posedge clk) begin
if(usage_count == 21'b0) begin
nmi_usage <= SNES_cycle_start & nmi_match_bits[1];
`ifdef IRQ_HOOK_ENABLE
irq_usage <= SNES_cycle_start & irq_match_bits[1];
`endif
`ifdef IRQ_HOOK_ENABLE
if(|nmi_usage & |irq_usage) begin
auto_nmi_enable <= 1'b1;
auto_irq_enable <= 1'b0;
end else if(irq_usage == 5'b0) begin
auto_nmi_enable <= 1'b1;
auto_irq_enable <= 1'b0;
end else if(nmi_usage == 5'b0) begin
auto_nmi_enable <= 1'b0;
auto_irq_enable <= 1'b1;
end
`else
auto_nmi_enable <= |nmi_usage;
`endif
end else begin
if(SNES_cycle_start & nmi_match_bits[0]) nmi_usage <= nmi_usage + 1;
`ifdef IRQ_HOOK_ENABLE
if(SNES_cycle_start & irq_match_bits[0]) irq_usage <= irq_usage + 1;
`endif
end
end
// Do not change vectors while they are being read
always @(posedge clk) begin
if(SNES_cycle_start) begin
if(nmi_addr_match
`ifdef IRQ_HOOK_ENABLE
| irq_addr_match
`endif
) sync_delay <= 2'b10;
else begin
if (|sync_delay) sync_delay <= sync_delay - 1;
if (sync_delay == 2'b00) begin
auto_nmi_enable_sync <= auto_nmi_enable;
`ifdef IRQ_HOOK_ENABLE
auto_irq_enable_sync <= auto_irq_enable;
`endif
hook_enable_sync <= hook_enable;
end
end
end
end
// CMD 0x85: disable hooks for 10 seconds
always @(posedge clk) begin
if((snescmd_unlock & snescmd_wr_strobe & ~|SNES_ADDR[8:0] & (SNES_DATA == 8'h85))
| (holdoff_enable & SNES_reset_strobe)) begin
hook_enable_count <= 30'd960000000;
end else if (|hook_enable_count) begin
hook_enable_count <= hook_enable_count - 1;
end
end
always @(posedge clk) begin
if(SNES_reset_strobe) begin
snescmd_unlock_disable_strobe <= 1'b0;
end else begin
snescmd_unlock_disable_strobe <= 1'b0;
if(snescmd_unlock & snescmd_wr_strobe) begin
if(~|SNES_ADDR[8:0]) begin
case(SNES_DATA)
8'h82: cheat_enable <= 1;
8'h83: cheat_enable <= 0;
8'h84: {nmi_enable, irq_enable} <= 2'b00;
endcase
end else if(SNES_ADDR[8:0] == 9'h1fd) begin
snescmd_unlock_disable_strobe <= 1'b1;
end
end else if(pgm_we) begin
if(pgm_idx < 6) begin
cheat_addr[pgm_idx] <= pgm_in[31:8];
cheat_data[pgm_idx] <= pgm_in[7:0];
end else if(pgm_idx == 6) begin // set rom patch enable
cheat_enable_mask <= pgm_in[5:0];
end else if(pgm_idx == 7) begin // set/reset global enable / hooks
// pgm_in[13:8] are reset bit flags
// pgm_in[5:0] are set bit flags
{wram_present, buttons_enable, holdoff_enable, irq_enable, nmi_enable, cheat_enable}
<= ({wram_present, buttons_enable, holdoff_enable, irq_enable, nmi_enable, cheat_enable}
& ~pgm_in[13:8])
| pgm_in[5:0];
end
end
end
end
// map controller input to cmd output
// check button combinations
// L+R+Start+Select : $3030
// L+R+Select+X : $2070
// L+R+Start+A : $10b0
// L+R+Start+B : $9030
// L+R+Start+Y : $5030
// L+R+Start+X : $1070
always @(posedge clk) begin
if(snescmd_wr_strobe) begin
if(SNES_ADDR[8:0] == 9'h1f0) begin
pad_data[7:0] <= SNES_DATA;
end else if(SNES_ADDR[8:0] == 9'h1f1) begin
pad_data[15:8] <= SNES_DATA;
end
end
end
always @* begin
case(pad_data)
16'h3030: nmicmd = 8'h80;
16'h2070: nmicmd = 8'h81;
16'h10b0: nmicmd = 8'h82;
16'h9030: nmicmd = 8'h83;
16'h5030: nmicmd = 8'h84;
16'h1070: nmicmd = 8'h85;
default: nmicmd = 8'h00;
endcase
end
always @* begin
if(buttons_enable) begin
if(snes_ajr) begin
if(nmicmd) begin
branch1_offset = 8'h30; // nmi_echocmd
end else begin
if(branch_wram) begin
branch1_offset = 8'h3a; // nmi_patches
end else begin
branch1_offset = 8'h43; // nmi_exit
end
end
end else begin
if(pad_latch) begin
if(branch_wram) begin
branch1_offset = 8'h3a; // nmi_patches
end else begin
branch1_offset = 8'h43; // nmi_exit
end
end else begin
branch1_offset = 8'h00; // continue with MJR
end
end
end else begin
if(branch_wram) begin
branch1_offset = 8'h3a; // nmi_patches
end else begin
branch1_offset = 8'h43; // nmi_exit
end
end
end
always @* begin
if(nmicmd == 8'h81) begin
branch2_offset = 8'h14; // nmi_stop
end else if(branch_wram) begin
branch2_offset = 8'h00; // nmi_patches
end else begin
branch2_offset = 8'h09; // nmi_exit
end
end
endmodule
|
module ad_gt_es (
// drp interface
up_rstn,
up_clk,
up_es_drp_sel,
up_es_drp_wr,
up_es_drp_addr,
up_es_drp_wdata,
up_es_drp_rdata,
up_es_drp_ready,
// axi4 interface
axi_awvalid,
axi_awaddr,
axi_awprot,
axi_awready,
axi_wvalid,
axi_wdata,
axi_wstrb,
axi_wready,
axi_bvalid,
axi_bresp,
axi_bready,
axi_arvalid,
axi_araddr,
axi_arprot,
axi_arready,
axi_rvalid,
axi_rresp,
axi_rdata,
axi_rready,
// processor interface
up_lpm_dfe_n,
up_es_start,
up_es_stop,
up_es_init,
up_es_sdata0,
up_es_sdata1,
up_es_sdata2,
up_es_sdata3,
up_es_sdata4,
up_es_qdata0,
up_es_qdata1,
up_es_qdata2,
up_es_qdata3,
up_es_qdata4,
up_es_prescale,
up_es_hoffset_min,
up_es_hoffset_max,
up_es_hoffset_step,
up_es_voffset_min,
up_es_voffset_max,
up_es_voffset_step,
up_es_voffset_range,
up_es_start_addr,
up_es_dmaerr,
up_es_status);
// parameters
parameter GTH_GTX_N = 0;
// gt address
localparam ES_DRP_CTRL_ADDR = (GTH_GTX_N == 1) ? 12'h03c : 12'h03d; // GTH-7 12'h03d
localparam ES_DRP_SDATA0_ADDR = (GTH_GTX_N == 1) ? 12'h049 : 12'h036; // GTH-7 12'h036
localparam ES_DRP_SDATA1_ADDR = (GTH_GTX_N == 1) ? 12'h04a : 12'h037; // GTH-7 12'h037
localparam ES_DRP_SDATA2_ADDR = (GTH_GTX_N == 1) ? 12'h04b : 12'h038; // GTH-7 12'h038
localparam ES_DRP_SDATA3_ADDR = (GTH_GTX_N == 1) ? 12'h04c : 12'h039; // GTH-7 12'h039
localparam ES_DRP_SDATA4_ADDR = (GTH_GTX_N == 1) ? 12'h04d : 12'h03a; // GTH-7 12'h03a
localparam ES_DRP_QDATA0_ADDR = (GTH_GTX_N == 1) ? 12'h044 : 12'h031; // GTH-7 12'h031
localparam ES_DRP_QDATA1_ADDR = (GTH_GTX_N == 1) ? 12'h045 : 12'h032; // GTH-7 12'h032
localparam ES_DRP_QDATA2_ADDR = (GTH_GTX_N == 1) ? 12'h046 : 12'h033; // GTH-7 12'h033
localparam ES_DRP_QDATA3_ADDR = (GTH_GTX_N == 1) ? 12'h047 : 12'h034; // GTH-7 12'h034
localparam ES_DRP_QDATA4_ADDR = (GTH_GTX_N == 1) ? 12'h048 : 12'h035; // GTH-7 12'h035
localparam ES_DRP_HOFFSET_ADDR = (GTH_GTX_N == 1) ? 12'h04f : 12'h03c; // GTH-7 12'h03c
localparam ES_DRP_VOFFSET_ADDR = (GTH_GTX_N == 1) ? 12'h097 : 12'h03b; // GTH-7 12'h03b
localparam ES_DRP_STATUS_ADDR = (GTH_GTX_N == 1) ? 12'h153 : 12'h151; // GTH-7 12'h153
localparam ES_DRP_SCNT_ADDR = (GTH_GTX_N == 1) ? 12'h152 : 12'h150; // GTH-7 12'h152
localparam ES_DRP_ECNT_ADDR = (GTH_GTX_N == 1) ? 12'h151 : 12'h14f; // GTH-7 12'h151
// state machine
localparam ES_FSM_IDLE = 6'h00;
localparam ES_FSM_STATUS = 6'h01;
localparam ES_FSM_INIT = 6'h02;
localparam ES_FSM_CTRLINIT_READ = 6'h03;
localparam ES_FSM_CTRLINIT_RRDY = 6'h04;
localparam ES_FSM_CTRLINIT_WRITE = 6'h05;
localparam ES_FSM_CTRLINIT_WRDY = 6'h06;
localparam ES_FSM_SDATA0_WRITE = 6'h07;
localparam ES_FSM_SDATA0_WRDY = 6'h08;
localparam ES_FSM_SDATA1_WRITE = 6'h09;
localparam ES_FSM_SDATA1_WRDY = 6'h0a;
localparam ES_FSM_SDATA2_WRITE = 6'h0b;
localparam ES_FSM_SDATA2_WRDY = 6'h0c;
localparam ES_FSM_SDATA3_WRITE = 6'h0d;
localparam ES_FSM_SDATA3_WRDY = 6'h0e;
localparam ES_FSM_SDATA4_WRITE = 6'h0f;
localparam ES_FSM_SDATA4_WRDY = 6'h10;
localparam ES_FSM_QDATA0_WRITE = 6'h11;
localparam ES_FSM_QDATA0_WRDY = 6'h12;
localparam ES_FSM_QDATA1_WRITE = 6'h13;
localparam ES_FSM_QDATA1_WRDY = 6'h14;
localparam ES_FSM_QDATA2_WRITE = 6'h15;
localparam ES_FSM_QDATA2_WRDY = 6'h16;
localparam ES_FSM_QDATA3_WRITE = 6'h17;
localparam ES_FSM_QDATA3_WRDY = 6'h18;
localparam ES_FSM_QDATA4_WRITE = 6'h19;
localparam ES_FSM_QDATA4_WRDY = 6'h1a;
localparam ES_FSM_HOFFSET_READ = 6'h1b;
localparam ES_FSM_HOFFSET_RRDY = 6'h1c;
localparam ES_FSM_HOFFSET_WRITE = 6'h1d;
localparam ES_FSM_HOFFSET_WRDY = 6'h1e;
localparam ES_FSM_VOFFSET_READ = 6'h1f;
localparam ES_FSM_VOFFSET_RRDY = 6'h20;
localparam ES_FSM_VOFFSET_WRITE = 6'h21;
localparam ES_FSM_VOFFSET_WRDY = 6'h22;
localparam ES_FSM_CTRLSTART_READ = 6'h23;
localparam ES_FSM_CTRLSTART_RRDY = 6'h24;
localparam ES_FSM_CTRLSTART_WRITE = 6'h25;
localparam ES_FSM_CTRLSTART_WRDY = 6'h26;
localparam ES_FSM_STATUS_READ = 6'h27;
localparam ES_FSM_STATUS_RRDY = 6'h28;
localparam ES_FSM_CTRLSTOP_READ = 6'h29;
localparam ES_FSM_CTRLSTOP_RRDY = 6'h2a;
localparam ES_FSM_CTRLSTOP_WRITE = 6'h2b;
localparam ES_FSM_CTRLSTOP_WRDY = 6'h2c;
localparam ES_FSM_SCNT_READ = 6'h2d;
localparam ES_FSM_SCNT_RRDY = 6'h2e;
localparam ES_FSM_ECNT_READ = 6'h2f;
localparam ES_FSM_ECNT_RRDY = 6'h30;
localparam ES_FSM_DMA_WRITE = 6'h31;
localparam ES_FSM_DMA_READY = 6'h32;
localparam ES_FSM_UPDATE = 6'h33;
// drp interface
input up_rstn;
input up_clk;
output up_es_drp_sel;
output up_es_drp_wr;
output [11:0] up_es_drp_addr;
output [15:0] up_es_drp_wdata;
input [15:0] up_es_drp_rdata;
input up_es_drp_ready;
// axi4 interface
output axi_awvalid;
output [31:0] axi_awaddr;
output [ 2:0] axi_awprot;
input axi_awready;
output axi_wvalid;
output [31:0] axi_wdata;
output [ 3:0] axi_wstrb;
input axi_wready;
input axi_bvalid;
input [ 1:0] axi_bresp;
output axi_bready;
output axi_arvalid;
output [31:0] axi_araddr;
output [ 2:0] axi_arprot;
input axi_arready;
input axi_rvalid;
input [31:0] axi_rdata;
input [ 1:0] axi_rresp;
output axi_rready;
// processor interface
input up_lpm_dfe_n;
input up_es_start;
input up_es_stop;
input up_es_init;
input [15:0] up_es_sdata0;
input [15:0] up_es_sdata1;
input [15:0] up_es_sdata2;
input [15:0] up_es_sdata3;
input [15:0] up_es_sdata4;
input [15:0] up_es_qdata0;
input [15:0] up_es_qdata1;
input [15:0] up_es_qdata2;
input [15:0] up_es_qdata3;
input [15:0] up_es_qdata4;
input [ 4:0] up_es_prescale;
input [11:0] up_es_hoffset_min;
input [11:0] up_es_hoffset_max;
input [11:0] up_es_hoffset_step;
input [ 7:0] up_es_voffset_min;
input [ 7:0] up_es_voffset_max;
input [ 7:0] up_es_voffset_step;
input [ 1:0] up_es_voffset_range;
input [31:0] up_es_start_addr;
output up_es_dmaerr;
output up_es_status;
// internal registers
reg axi_awvalid = 'd0;
reg [31:0] axi_awaddr = 'd0;
reg axi_wvalid = 'd0;
reg [31:0] axi_wdata = 'd0;
reg up_es_dmaerr = 'd0;
reg up_es_status = 'd0;
reg up_es_ut = 'd0;
reg [31:0] up_es_dma_addr = 'd0;
reg [11:0] up_es_hoffset = 'd0;
reg [ 7:0] up_es_voffset = 'd0;
reg [15:0] up_es_hoffset_rdata = 'd0;
reg [15:0] up_es_voffset_rdata = 'd0;
reg [15:0] up_es_ctrl_rdata = 'd0;
reg [15:0] up_es_scnt_rdata = 'd0;
reg [15:0] up_es_ecnt_rdata = 'd0;
reg [ 5:0] up_es_fsm = 'd0;
reg up_es_drp_sel = 'd0;
reg up_es_drp_wr = 'd0;
reg [11:0] up_es_drp_addr = 'd0;
reg [15:0] up_es_drp_wdata = 'd0;
// internal signals
wire up_es_heos_s;
wire up_es_eos_s;
wire up_es_ut_s;
wire [ 7:0] up_es_voffset_2_s;
wire [ 7:0] up_es_voffset_n_s;
wire [ 7:0] up_es_voffset_s;
// axi write interface
assign axi_awprot = 3'd0;
assign axi_wstrb = 4'hf;
assign axi_bready = 1'd1;
assign axi_arvalid = 1'd0;
assign axi_araddr = 32'd0;
assign axi_arprot = 3'd0;
assign axi_rready = 1'd1;
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin
axi_awvalid <= 'b0;
axi_awaddr <= 'd0;
axi_wvalid <= 'b0;
axi_wdata <= 'd0;
end else begin
if ((axi_awvalid == 1'b1) && (axi_awready == 1'b1)) begin
axi_awvalid <= 1'b0;
axi_awaddr <= 32'd0;
end else if (up_es_fsm == ES_FSM_DMA_WRITE) begin
axi_awvalid <= 1'b1;
axi_awaddr <= up_es_dma_addr;
end
if ((axi_wvalid == 1'b1) && (axi_wready == 1'b1)) begin
axi_wvalid <= 1'b0;
axi_wdata <= 32'd0;
end else if (up_es_fsm == ES_FSM_DMA_WRITE) begin
axi_wvalid <= 1'b1;
axi_wdata <= {up_es_scnt_rdata, up_es_ecnt_rdata};
end
end
end
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 1'b0) begin
up_es_dmaerr <= 'd0;
end else begin
if (axi_bvalid == 1'b1) begin
up_es_dmaerr <= axi_bresp[1] | axi_bresp[0];
end
end
end
// prescale, horizontal and vertical offsets
assign up_es_heos_s = (up_es_hoffset == up_es_hoffset_max) ? up_es_ut : 1'b0;
assign up_es_eos_s = (up_es_voffset == up_es_voffset_max) ? up_es_heos_s : 1'b0;
assign up_es_ut_s = up_es_ut & ~up_lpm_dfe_n;
assign up_es_voffset_2_s = ~up_es_voffset + 1'b1;
assign up_es_voffset_n_s = {1'b1, up_es_voffset_2_s[6:0]};
assign up_es_voffset_s = (up_es_voffset[7] == 1'b1) ? up_es_voffset_n_s : up_es_voffset;
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 1'b0) begin
up_es_status <= 1'b0;
up_es_ut <= 'd0;
up_es_dma_addr <= 'd0;
up_es_hoffset <= 'd0;
up_es_voffset <= 'd0;
end else begin
if (up_es_fsm == ES_FSM_IDLE) begin
up_es_status <= 1'b0;
end else begin
up_es_status <= 1'b1;
end
if (up_es_fsm == ES_FSM_IDLE) begin
up_es_ut <= up_lpm_dfe_n;
up_es_dma_addr <= up_es_start_addr;
up_es_hoffset <= up_es_hoffset_min;
up_es_voffset <= up_es_voffset_min;
end else if (up_es_fsm == ES_FSM_UPDATE) begin
up_es_ut <= ~up_es_ut | up_lpm_dfe_n;
up_es_dma_addr <= up_es_dma_addr + 3'd4;
if (up_es_heos_s == 1'b1) begin
up_es_hoffset <= up_es_hoffset_min;
end else if (up_es_ut == 1'b1) begin
up_es_hoffset <= up_es_hoffset + up_es_hoffset_step;
end
if (up_es_heos_s == 1'b1) begin
up_es_voffset <= up_es_voffset + up_es_voffset_step;
end
end
end
end
// read-modify-write parameters (gt's are full of mixed up controls)
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 1'b0) begin
up_es_hoffset_rdata <= 'd0;
up_es_voffset_rdata <= 'd0;
up_es_ctrl_rdata <= 'd0;
up_es_scnt_rdata <= 'd0;
up_es_ecnt_rdata <= 'd0;
end else begin
if ((up_es_fsm == ES_FSM_HOFFSET_RRDY) && (up_es_drp_ready == 1'b1)) begin
up_es_hoffset_rdata <= up_es_drp_rdata;
end
if ((up_es_fsm == ES_FSM_VOFFSET_RRDY) && (up_es_drp_ready == 1'b1)) begin
up_es_voffset_rdata <= up_es_drp_rdata;
end
if (((up_es_fsm == ES_FSM_CTRLINIT_RRDY) || (up_es_fsm == ES_FSM_CTRLSTART_RRDY) ||
(up_es_fsm == ES_FSM_CTRLSTOP_RRDY)) && (up_es_drp_ready == 1'b1)) begin
up_es_ctrl_rdata <= up_es_drp_rdata;
end
if ((up_es_fsm == ES_FSM_SCNT_RRDY) && (up_es_drp_ready == 1'b1)) begin
up_es_scnt_rdata <= up_es_drp_rdata;
end
if ((up_es_fsm == ES_FSM_ECNT_RRDY) && (up_es_drp_ready == 1'b1)) begin
up_es_ecnt_rdata <= up_es_drp_rdata;
end
end
end
// eye scan state machine- write vertical and horizontal offsets
// and read back sample and error counters
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 1'b0) begin
up_es_fsm <= ES_FSM_IDLE;
end else begin
if (up_es_stop == 1'b1) begin
up_es_fsm <= ES_FSM_IDLE;
end else begin
case (up_es_fsm)
ES_FSM_IDLE: begin // idle
if (up_es_start == 1'b1) begin
up_es_fsm <= ES_FSM_STATUS;
end else begin
up_es_fsm <= ES_FSM_IDLE;
end
end
ES_FSM_STATUS: begin // set status
up_es_fsm <= ES_FSM_INIT;
end
ES_FSM_INIT: begin // initialize
if (up_es_init == 1'b1) begin
up_es_fsm <= ES_FSM_CTRLINIT_READ;
end else begin
up_es_fsm <= ES_FSM_HOFFSET_READ;
end
end
ES_FSM_CTRLINIT_READ: begin // control read
up_es_fsm <= ES_FSM_CTRLINIT_RRDY;
end
ES_FSM_CTRLINIT_RRDY: begin // control ready
if (up_es_drp_ready == 1'b1) begin
up_es_fsm <= ES_FSM_CTRLINIT_WRITE;
end else begin
up_es_fsm <= ES_FSM_CTRLINIT_RRDY;
end
end
ES_FSM_CTRLINIT_WRITE: begin // control write
up_es_fsm <= ES_FSM_CTRLINIT_WRDY;
end
ES_FSM_CTRLINIT_WRDY: begin // control ready
if (up_es_drp_ready == 1'b1) begin
up_es_fsm <= ES_FSM_SDATA0_WRITE;
end else begin
up_es_fsm <= ES_FSM_CTRLINIT_WRDY;
end
end
ES_FSM_SDATA0_WRITE: begin // sdata write
up_es_fsm <= ES_FSM_SDATA0_WRDY;
end
ES_FSM_SDATA0_WRDY: begin // sdata ready
if (up_es_drp_ready == 1'b1) begin
up_es_fsm <= ES_FSM_SDATA1_WRITE;
end else begin
up_es_fsm <= ES_FSM_SDATA0_WRDY;
end
end
ES_FSM_SDATA1_WRITE: begin // sdata write
up_es_fsm <= ES_FSM_SDATA1_WRDY;
end
ES_FSM_SDATA1_WRDY: begin // sdata ready
if (up_es_drp_ready == 1'b1) begin
up_es_fsm <= ES_FSM_SDATA2_WRITE;
end else begin
up_es_fsm <= ES_FSM_SDATA1_WRDY;
end
end
ES_FSM_SDATA2_WRITE: begin // sdata write
up_es_fsm <= ES_FSM_SDATA2_WRDY;
end
ES_FSM_SDATA2_WRDY: begin // sdata ready
if (up_es_drp_ready == 1'b1) begin
up_es_fsm <= ES_FSM_SDATA3_WRITE;
end else begin
up_es_fsm <= ES_FSM_SDATA2_WRDY;
end
end
ES_FSM_SDATA3_WRITE: begin // sdata write
up_es_fsm <= ES_FSM_SDATA3_WRDY;
end
ES_FSM_SDATA3_WRDY: begin // sdata ready
if (up_es_drp_ready == 1'b1) begin
up_es_fsm <= ES_FSM_SDATA4_WRITE;
end else begin
up_es_fsm <= ES_FSM_SDATA3_WRDY;
end
end
ES_FSM_SDATA4_WRITE: begin // sdata write
up_es_fsm <= ES_FSM_SDATA4_WRDY;
end
ES_FSM_SDATA4_WRDY: begin // sdata ready
if (up_es_drp_ready == 1'b1) begin
up_es_fsm <= ES_FSM_QDATA0_WRITE;
end else begin
up_es_fsm <= ES_FSM_SDATA4_WRDY;
end
end
ES_FSM_QDATA0_WRITE: begin // qdata write
up_es_fsm <= ES_FSM_QDATA0_WRDY;
end
ES_FSM_QDATA0_WRDY: begin // qdata ready
if (up_es_drp_ready == 1'b1) begin
up_es_fsm <= ES_FSM_QDATA1_WRITE;
end else begin
up_es_fsm <= ES_FSM_QDATA0_WRDY;
end
end
ES_FSM_QDATA1_WRITE: begin // qdata write
up_es_fsm <= ES_FSM_QDATA1_WRDY;
end
ES_FSM_QDATA1_WRDY: begin // qdata ready
if (up_es_drp_ready == 1'b1) begin
up_es_fsm <= ES_FSM_QDATA2_WRITE;
end else begin
up_es_fsm <= ES_FSM_QDATA1_WRDY;
end
end
ES_FSM_QDATA2_WRITE: begin // qdata write
up_es_fsm <= ES_FSM_QDATA2_WRDY;
end
ES_FSM_QDATA2_WRDY: begin // qdata ready
if (up_es_drp_ready == 1'b1) begin
up_es_fsm <= ES_FSM_QDATA3_WRITE;
end else begin
up_es_fsm <= ES_FSM_QDATA2_WRDY;
end
end
ES_FSM_QDATA3_WRITE: begin // qdata write
up_es_fsm <= ES_FSM_QDATA3_WRDY;
end
ES_FSM_QDATA3_WRDY: begin // qdata ready
if (up_es_drp_ready == 1'b1) begin
up_es_fsm <= ES_FSM_QDATA4_WRITE;
end else begin
up_es_fsm <= ES_FSM_QDATA3_WRDY;
end
end
ES_FSM_QDATA4_WRITE: begin // qdata write
up_es_fsm <= ES_FSM_QDATA4_WRDY;
end
ES_FSM_QDATA4_WRDY: begin // qdata ready
if (up_es_drp_ready == 1'b1) begin
up_es_fsm <= ES_FSM_HOFFSET_READ;
end else begin
up_es_fsm <= ES_FSM_QDATA4_WRDY;
end
end
ES_FSM_HOFFSET_READ: begin // horizontal offset read
up_es_fsm <= ES_FSM_HOFFSET_RRDY;
end
ES_FSM_HOFFSET_RRDY: begin // horizontal offset ready
if (up_es_drp_ready == 1'b1) begin
up_es_fsm <= ES_FSM_HOFFSET_WRITE;
end else begin
up_es_fsm <= ES_FSM_HOFFSET_RRDY;
end
end
ES_FSM_HOFFSET_WRITE: begin // horizontal offset write
up_es_fsm <= ES_FSM_HOFFSET_WRDY;
end
ES_FSM_HOFFSET_WRDY: begin // horizontal offset ready
if (up_es_drp_ready == 1'b1) begin
up_es_fsm <= ES_FSM_VOFFSET_READ;
end else begin
up_es_fsm <= ES_FSM_HOFFSET_WRDY;
end
end
ES_FSM_VOFFSET_READ: begin // vertical offset read
up_es_fsm <= ES_FSM_VOFFSET_RRDY;
end
ES_FSM_VOFFSET_RRDY: begin // vertical offset ready
if (up_es_drp_ready == 1'b1) begin
up_es_fsm <= ES_FSM_VOFFSET_WRITE;
end else begin
up_es_fsm <= ES_FSM_VOFFSET_RRDY;
end
end
ES_FSM_VOFFSET_WRITE: begin // vertical offset write
up_es_fsm <= ES_FSM_VOFFSET_WRDY;
end
ES_FSM_VOFFSET_WRDY: begin // vertical offset ready
if (up_es_drp_ready == 1'b1) begin
up_es_fsm <= ES_FSM_CTRLSTART_READ;
end else begin
up_es_fsm <= ES_FSM_VOFFSET_WRDY;
end
end
ES_FSM_CTRLSTART_READ: begin // control read
up_es_fsm <= ES_FSM_CTRLSTART_RRDY;
end
ES_FSM_CTRLSTART_RRDY: begin // control ready
if (up_es_drp_ready == 1'b1) begin
up_es_fsm <= ES_FSM_CTRLSTART_WRITE;
end else begin
up_es_fsm <= ES_FSM_CTRLSTART_RRDY;
end
end
ES_FSM_CTRLSTART_WRITE: begin // control write
up_es_fsm <= ES_FSM_CTRLSTART_WRDY;
end
ES_FSM_CTRLSTART_WRDY: begin // control ready
if (up_es_drp_ready == 1'b1) begin
up_es_fsm <= ES_FSM_STATUS_READ;
end else begin
up_es_fsm <= ES_FSM_CTRLSTART_WRDY;
end
end
ES_FSM_STATUS_READ: begin // status read
up_es_fsm <= ES_FSM_STATUS_RRDY;
end
ES_FSM_STATUS_RRDY: begin // status ready
if (up_es_drp_ready == 1'b0) begin
up_es_fsm <= ES_FSM_STATUS_RRDY;
end else if (up_es_drp_rdata[3:0] == 4'b0101) begin
up_es_fsm <= ES_FSM_CTRLSTOP_READ;
end else begin
up_es_fsm <= ES_FSM_STATUS_READ;
end
end
ES_FSM_CTRLSTOP_READ: begin // control read
up_es_fsm <= ES_FSM_CTRLSTOP_RRDY;
end
ES_FSM_CTRLSTOP_RRDY: begin // control ready
if (up_es_drp_ready == 1'b1) begin
up_es_fsm <= ES_FSM_CTRLSTOP_WRITE;
end else begin
up_es_fsm <= ES_FSM_CTRLSTOP_RRDY;
end
end
ES_FSM_CTRLSTOP_WRITE: begin // control write
up_es_fsm <= ES_FSM_CTRLSTOP_WRDY;
end
ES_FSM_CTRLSTOP_WRDY: begin // control ready
if (up_es_drp_ready == 1'b1) begin
up_es_fsm <= ES_FSM_SCNT_READ;
end else begin
up_es_fsm <= ES_FSM_CTRLSTOP_WRDY;
end
end
ES_FSM_SCNT_READ: begin // read sample count
up_es_fsm <= ES_FSM_SCNT_RRDY;
end
ES_FSM_SCNT_RRDY: begin // sample count ready
if (up_es_drp_ready == 1'b1) begin
up_es_fsm <= ES_FSM_ECNT_READ;
end else begin
up_es_fsm <= ES_FSM_SCNT_RRDY;
end
end
ES_FSM_ECNT_READ: begin // read error count
up_es_fsm <= ES_FSM_ECNT_RRDY;
end
ES_FSM_ECNT_RRDY: begin // error count ready
if (up_es_drp_ready == 1'b1) begin
up_es_fsm <= ES_FSM_DMA_WRITE;
end else begin
up_es_fsm <= ES_FSM_ECNT_RRDY;
end
end
ES_FSM_DMA_WRITE: begin // dma write
up_es_fsm <= ES_FSM_DMA_READY;
end
ES_FSM_DMA_READY: begin // dma ack
if (axi_bvalid == 1'b1) begin
up_es_fsm <= ES_FSM_UPDATE;
end else begin
up_es_fsm <= ES_FSM_DMA_READY;
end
end
ES_FSM_UPDATE: begin // update
if (up_es_eos_s == 1'b1) begin
up_es_fsm <= ES_FSM_IDLE;
end else if (up_es_ut == 1'b1) begin
up_es_fsm <= ES_FSM_HOFFSET_READ;
end else begin
up_es_fsm <= ES_FSM_VOFFSET_READ;
end
end
default: begin
up_es_fsm <= ES_FSM_IDLE;
end
endcase
end
end
end
// drp signals controlled by the fsm
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 1'b0) begin
up_es_drp_sel <= 'd0;
up_es_drp_wr <= 'd0;
up_es_drp_addr <= 'd0;
up_es_drp_wdata <= 'd0;
end else begin
case (up_es_fsm)
ES_FSM_CTRLINIT_READ: begin
up_es_drp_sel <= 1'b1;
up_es_drp_wr <= 1'b0;
up_es_drp_addr <= ES_DRP_CTRL_ADDR;
up_es_drp_wdata <= 16'h0000;
end
ES_FSM_CTRLINIT_WRITE: begin
up_es_drp_sel <= 1'b1;
up_es_drp_wr <= 1'b1;
up_es_drp_addr <= ES_DRP_CTRL_ADDR;
if (GTH_GTX_N == 1) begin
up_es_drp_wdata <= {up_es_ctrl_rdata[15:10], 2'b11, up_es_ctrl_rdata[7:5], up_es_prescale};
end else begin
up_es_drp_wdata <= {up_es_ctrl_rdata[15:10], 2'b11, up_es_ctrl_rdata[7:0]};
end
end
ES_FSM_SDATA0_WRITE: begin
up_es_drp_sel <= 1'b1;
up_es_drp_wr <= 1'b1;
up_es_drp_addr <= ES_DRP_SDATA0_ADDR;
up_es_drp_wdata <= up_es_sdata0;
end
ES_FSM_SDATA1_WRITE: begin
up_es_drp_sel <= 1'b1;
up_es_drp_wr <= 1'b1;
up_es_drp_addr <= ES_DRP_SDATA1_ADDR;
up_es_drp_wdata <= up_es_sdata1;
end
ES_FSM_SDATA2_WRITE: begin
up_es_drp_sel <= 1'b1;
up_es_drp_wr <= 1'b1;
up_es_drp_addr <= ES_DRP_SDATA2_ADDR;
up_es_drp_wdata <= up_es_sdata2;
end
ES_FSM_SDATA3_WRITE: begin
up_es_drp_sel <= 1'b1;
up_es_drp_wr <= 1'b1;
up_es_drp_addr <= ES_DRP_SDATA3_ADDR;
up_es_drp_wdata <= up_es_sdata3;
end
ES_FSM_SDATA4_WRITE: begin
up_es_drp_sel <= 1'b1;
up_es_drp_wr <= 1'b1;
up_es_drp_addr <= ES_DRP_SDATA4_ADDR;
up_es_drp_wdata <= up_es_sdata4;
end
ES_FSM_QDATA0_WRITE: begin
up_es_drp_sel <= 1'b1;
up_es_drp_wr <= 1'b1;
up_es_drp_addr <= ES_DRP_QDATA0_ADDR;
up_es_drp_wdata <= up_es_qdata0;
end
ES_FSM_QDATA1_WRITE: begin
up_es_drp_sel <= 1'b1;
up_es_drp_wr <= 1'b1;
up_es_drp_addr <= ES_DRP_QDATA1_ADDR;
up_es_drp_wdata <= up_es_qdata1;
end
ES_FSM_QDATA2_WRITE: begin
up_es_drp_sel <= 1'b1;
up_es_drp_wr <= 1'b1;
up_es_drp_addr <= ES_DRP_QDATA2_ADDR;
up_es_drp_wdata <= up_es_qdata2;
end
ES_FSM_QDATA3_WRITE: begin
up_es_drp_sel <= 1'b1;
up_es_drp_wr <= 1'b1;
up_es_drp_addr <= ES_DRP_QDATA3_ADDR;
up_es_drp_wdata <= up_es_qdata3;
end
ES_FSM_QDATA4_WRITE: begin
up_es_drp_sel <= 1'b1;
up_es_drp_wr <= 1'b1;
up_es_drp_addr <= ES_DRP_QDATA4_ADDR;
up_es_drp_wdata <= up_es_qdata4;
end
ES_FSM_HOFFSET_READ: begin
up_es_drp_sel <= 1'b1;
up_es_drp_wr <= 1'b0;
up_es_drp_addr <= ES_DRP_HOFFSET_ADDR;
up_es_drp_wdata <= 16'h0000;
end
ES_FSM_HOFFSET_WRITE: begin
up_es_drp_sel <= 1'b1;
up_es_drp_wr <= 1'b1;
up_es_drp_addr <= ES_DRP_HOFFSET_ADDR;
if (GTH_GTX_N == 1) begin
up_es_drp_wdata <= {up_es_hoffset, up_es_hoffset_rdata[3:0]};
end else begin
up_es_drp_wdata <= {up_es_hoffset_rdata[15:12], up_es_hoffset};
end
end
ES_FSM_VOFFSET_READ: begin
up_es_drp_sel <= 1'b1;
up_es_drp_wr <= 1'b0;
up_es_drp_addr <= ES_DRP_VOFFSET_ADDR;
up_es_drp_wdata <= 16'h0000;
end
ES_FSM_VOFFSET_WRITE: begin
up_es_drp_sel <= 1'b1;
up_es_drp_wr <= 1'b1;
up_es_drp_addr <= ES_DRP_VOFFSET_ADDR;
if (GTH_GTX_N == 1) begin
up_es_drp_wdata <= {up_es_voffset_rdata[15:11], up_es_voffset_s[7], up_es_ut_s, up_es_voffset_s[6:0], up_es_voffset_range};
end else begin
up_es_drp_wdata <= {up_es_prescale, up_es_voffset_rdata[10:9], up_es_ut_s, up_es_voffset_s};
end
end
ES_FSM_CTRLSTART_READ: begin
up_es_drp_sel <= 1'b1;
up_es_drp_wr <= 1'b0;
up_es_drp_addr <= ES_DRP_CTRL_ADDR;
up_es_drp_wdata <= 16'h0000;
end
ES_FSM_CTRLSTART_WRITE: begin
up_es_drp_sel <= 1'b1;
up_es_drp_wr <= 1'b1;
up_es_drp_addr <= ES_DRP_CTRL_ADDR;
if (GTH_GTX_N == 1) begin
up_es_drp_wdata <= {6'd1, up_es_ctrl_rdata[9:0]};
end else begin
up_es_drp_wdata <= {up_es_ctrl_rdata[15:6], 6'd1};
end
end
ES_FSM_STATUS_READ: begin
up_es_drp_sel <= 1'b1;
up_es_drp_wr <= 1'b0;
up_es_drp_addr <= ES_DRP_STATUS_ADDR;
up_es_drp_wdata <= 16'h0000;
end
ES_FSM_CTRLSTOP_READ: begin
up_es_drp_sel <= 1'b1;
up_es_drp_wr <= 1'b0;
up_es_drp_addr <= ES_DRP_CTRL_ADDR;
up_es_drp_wdata <= 16'h0000;
end
ES_FSM_CTRLSTOP_WRITE: begin
up_es_drp_sel <= 1'b1;
up_es_drp_wr <= 1'b1;
up_es_drp_addr <= ES_DRP_CTRL_ADDR;
if (GTH_GTX_N == 1) begin
up_es_drp_wdata <= {6'd0, up_es_ctrl_rdata[9:0]};
end else begin
up_es_drp_wdata <= {up_es_ctrl_rdata[15:6], 6'd0};
end
end
ES_FSM_SCNT_READ: begin
up_es_drp_sel <= 1'b1;
up_es_drp_wr <= 1'b0;
up_es_drp_addr <= ES_DRP_SCNT_ADDR;
up_es_drp_wdata <= 16'h0000;
end
ES_FSM_ECNT_READ: begin
up_es_drp_sel <= 1'b1;
up_es_drp_wr <= 1'b0;
up_es_drp_addr <= ES_DRP_ECNT_ADDR;
up_es_drp_wdata <= 16'h0000;
end
default: begin
up_es_drp_sel <= 1'b0;
up_es_drp_wr <= 1'b0;
up_es_drp_addr <= 9'h000;
up_es_drp_wdata <= 16'h0000;
end
endcase
end
end
endmodule
|
module axi_hdmi_tx_vdma (
// hdmi interface
hdmi_fs_toggle,
hdmi_raddr_g,
// vdma interface
vdma_clk,
vdma_rst,
vdma_fs,
vdma_fs_ret,
vdma_valid,
vdma_data,
vdma_ready,
vdma_wr,
vdma_waddr,
vdma_wdata,
vdma_fs_ret_toggle,
vdma_fs_waddr,
vdma_tpm_oos,
vdma_ovf,
vdma_unf);
// parameters
localparam BUF_THRESHOLD_LO = 9'd3;
localparam BUF_THRESHOLD_HI = 9'd509;
localparam RDY_THRESHOLD_LO = 9'd450;
localparam RDY_THRESHOLD_HI = 9'd500;
// hdmi interface
input hdmi_fs_toggle;
input [ 8:0] hdmi_raddr_g;
// vdma interface
input vdma_clk;
input vdma_rst;
output vdma_fs;
input vdma_fs_ret;
input vdma_valid;
input [63:0] vdma_data;
output vdma_ready;
output vdma_wr;
output [ 8:0] vdma_waddr;
output [47:0] vdma_wdata;
output vdma_fs_ret_toggle;
output [ 8:0] vdma_fs_waddr;
output vdma_tpm_oos;
output vdma_ovf;
output vdma_unf;
// internal registers
reg vdma_fs_toggle_m1 = 'd0;
reg vdma_fs_toggle_m2 = 'd0;
reg vdma_fs_toggle_m3 = 'd0;
reg vdma_fs = 'd0;
reg [ 8:0] vdma_fs_waddr = 'd0;
reg vdma_fs_ret_toggle = 'd0;
reg vdma_wr = 'd0;
reg [ 8:0] vdma_waddr = 'd0;
reg [47:0] vdma_wdata = 'd0;
reg [22:0] vdma_tpm_data = 'd0;
reg vdma_tpm_oos = 'd0;
reg [ 8:0] vdma_raddr_g_m1 = 'd0;
reg [ 8:0] vdma_raddr_g_m2 = 'd0;
reg [ 8:0] vdma_raddr = 'd0;
reg [ 8:0] vdma_addr_diff = 'd0;
reg vdma_ready = 'd0;
reg vdma_almost_full = 'd0;
reg vdma_almost_empty = 'd0;
reg vdma_ovf = 'd0;
reg vdma_unf = 'd0;
// internal wires
wire [47:0] vdma_tpm_data_s;
wire vdma_tpm_oos_s;
wire [ 9:0] vdma_addr_diff_s;
wire vdma_ovf_s;
wire vdma_unf_s;
// grey to binary conversion
function [8:0] g2b;
input [8:0] g;
reg [8:0] b;
begin
b[8] = g[8];
b[7] = b[8] ^ g[7];
b[6] = b[7] ^ g[6];
b[5] = b[6] ^ g[5];
b[4] = b[5] ^ g[4];
b[3] = b[4] ^ g[3];
b[2] = b[3] ^ g[2];
b[1] = b[2] ^ g[1];
b[0] = b[1] ^ g[0];
g2b = b;
end
endfunction
// get fs from hdmi side, return fs and sof write address back
always @(posedge vdma_clk or posedge vdma_rst) begin
if (vdma_rst == 1'b1) begin
vdma_fs_toggle_m1 <= 'd0;
vdma_fs_toggle_m2 <= 'd0;
vdma_fs_toggle_m3 <= 'd0;
end else begin
vdma_fs_toggle_m1 <= hdmi_fs_toggle;
vdma_fs_toggle_m2 <= vdma_fs_toggle_m1;
vdma_fs_toggle_m3 <= vdma_fs_toggle_m2;
end
end
always @(posedge vdma_clk) begin
vdma_fs <= vdma_fs_toggle_m2 ^ vdma_fs_toggle_m3;
if (vdma_fs_ret == 1'b1) begin
vdma_fs_waddr <= vdma_waddr;
vdma_fs_ret_toggle <= ~vdma_fs_ret_toggle;
end
end
// vdma write
always @(posedge vdma_clk) begin
vdma_wr <= vdma_valid & vdma_ready;
if (vdma_rst == 1'b1) begin
vdma_waddr <= 9'd0;
end else if (vdma_wr == 1'b1) begin
vdma_waddr <= vdma_waddr + 1'b1;
end
vdma_wdata <= {vdma_data[55:32], vdma_data[23:0]};
end
// test error conditions
assign vdma_tpm_data_s = {vdma_tpm_data, 1'b1, vdma_tpm_data, 1'b0};
assign vdma_tpm_oos_s = (vdma_wdata == vdma_tpm_data_s) ? 1'b0 : vdma_wr;
always @(posedge vdma_clk) begin
if ((vdma_rst == 1'b1) || (vdma_fs_ret == 1'b1)) begin
vdma_tpm_data <= 23'd0;
vdma_tpm_oos <= 1'd0;
end else if (vdma_wr == 1'b1) begin
vdma_tpm_data <= vdma_tpm_data + 1'b1;
vdma_tpm_oos <= vdma_tpm_oos_s;
end
end
// overflow or underflow status
assign vdma_addr_diff_s = {1'b1, vdma_waddr} - vdma_raddr;
assign vdma_ovf_s = (vdma_addr_diff < BUF_THRESHOLD_LO) ? vdma_almost_full : 1'b0;
assign vdma_unf_s = (vdma_addr_diff > BUF_THRESHOLD_HI) ? vdma_almost_empty : 1'b0;
always @(posedge vdma_clk or posedge vdma_rst) begin
if (vdma_rst == 1'b1) begin
vdma_raddr_g_m1 <= 9'd0;
vdma_raddr_g_m2 <= 9'd0;
end else begin
vdma_raddr_g_m1 <= hdmi_raddr_g;
vdma_raddr_g_m2 <= vdma_raddr_g_m1;
end
end
always @(posedge vdma_clk) begin
vdma_raddr <= g2b(vdma_raddr_g_m2);
vdma_addr_diff <= vdma_addr_diff_s[8:0];
if (vdma_addr_diff >= RDY_THRESHOLD_HI) begin
vdma_ready <= 1'b0;
end else if (vdma_addr_diff <= RDY_THRESHOLD_LO) begin
vdma_ready <= 1'b1;
end
if (vdma_addr_diff > BUF_THRESHOLD_HI) begin
vdma_almost_full <= 1'b1;
end else begin
vdma_almost_full <= 1'b0;
end
if (vdma_addr_diff < BUF_THRESHOLD_LO) begin
vdma_almost_empty <= 1'b1;
end else begin
vdma_almost_empty <= 1'b0;
end
vdma_ovf <= vdma_ovf_s;
vdma_unf <= vdma_unf_s;
end
endmodule
|
module sky130_fd_sc_hdll__xor3_2 (
X ,
A ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hdll__xor3 base (
.X(X),
.A(A),
.B(B),
.C(C),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
|
module sky130_fd_sc_hdll__xor3_2 (
X,
A,
B,
C
);
output X;
input A;
input B;
input C;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hdll__xor3 base (
.X(X),
.A(A),
.B(B),
.C(C)
);
endmodule
|
module top();
// Inputs are registered
reg A1;
reg A2;
reg B1_N;
reg VPWR;
reg VGND;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A1 = 1'bX;
A2 = 1'bX;
B1_N = 1'bX;
VGND = 1'bX;
VPWR = 1'bX;
#20 A1 = 1'b0;
#40 A2 = 1'b0;
#60 B1_N = 1'b0;
#80 VGND = 1'b0;
#100 VPWR = 1'b0;
#120 A1 = 1'b1;
#140 A2 = 1'b1;
#160 B1_N = 1'b1;
#180 VGND = 1'b1;
#200 VPWR = 1'b1;
#220 A1 = 1'b0;
#240 A2 = 1'b0;
#260 B1_N = 1'b0;
#280 VGND = 1'b0;
#300 VPWR = 1'b0;
#320 VPWR = 1'b1;
#340 VGND = 1'b1;
#360 B1_N = 1'b1;
#380 A2 = 1'b1;
#400 A1 = 1'b1;
#420 VPWR = 1'bx;
#440 VGND = 1'bx;
#460 B1_N = 1'bx;
#480 A2 = 1'bx;
#500 A1 = 1'bx;
end
sky130_fd_sc_hs__a21bo dut (.A1(A1), .A2(A2), .B1_N(B1_N), .VPWR(VPWR), .VGND(VGND), .X(X));
endmodule
|
module system_debounce_0_0(clk, signal_in, signal_out)
/* synthesis syn_black_box black_box_pad_pin="clk,signal_in,signal_out" */;
input clk;
input signal_in;
output signal_out;
endmodule
|
module sky130_fd_sc_hdll__einvp (
Z ,
A ,
TE
);
output Z ;
input A ;
input TE;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
|
module ALU_Cell_1bit(
A,
B,
A_from_next_bit,
C_in,
FS,
F,
C_out
);
input wire A;
input wire B;
input wire A_from_next_bit;
input wire C_in;
input wire [4:0] FS;
output wire F;
output wire C_out;
wire [1:0] logic_S;
wire SYNTHESIZED_WIRE_0;
wire SYNTHESIZED_WIRE_1;
wire SYNTHESIZED_WIRE_2;
wire SYNTHESIZED_WIRE_3;
wire SYNTHESIZED_WIRE_4;
wire SYNTHESIZED_WIRE_5;
wire SYNTHESIZED_WIRE_6;
wire SYNTHESIZED_WIRE_7;
wire SYNTHESIZED_WIRE_8;
wire SYNTHESIZED_WIRE_9;
wire SYNTHESIZED_WIRE_10;
assign SYNTHESIZED_WIRE_6 = 0;
assign SYNTHESIZED_WIRE_7 = 1;
Mux_4_to_1 b2v_inst(
.I1(FS[0]),
.I2(FS[1]),
.I3(FS[2]),
.I4(FS[3]),
.S(logic_S),
.OUT(SYNTHESIZED_WIRE_2));
Mux_2_to_1 b2v_inst11(
.S(FS[3]),
.I1(SYNTHESIZED_WIRE_0),
.I2(SYNTHESIZED_WIRE_1),
.OUT(SYNTHESIZED_WIRE_3));
Mux_2_to_1 b2v_inst13(
.S(FS[4]),
.I1(SYNTHESIZED_WIRE_2),
.I2(SYNTHESIZED_WIRE_3),
.OUT(F));
Mux_2_to_1 b2v_inst14(
.S(FS[3]),
.I1(SYNTHESIZED_WIRE_4),
.I2(logic_S[1]),
.OUT(C_out));
Mux_2_to_1 b2v_inst2(
.S(FS[0]),
.I1(logic_S[1]),
.I2(SYNTHESIZED_WIRE_5),
.OUT(SYNTHESIZED_WIRE_9));
assign SYNTHESIZED_WIRE_5 = ~logic_S[1];
Mux_4_to_1 b2v_inst4(
.I1(SYNTHESIZED_WIRE_6),
.I2(SYNTHESIZED_WIRE_7),
.I3(logic_S[0]),
.I4(SYNTHESIZED_WIRE_8),
.S(FS[2:1]),
.OUT(SYNTHESIZED_WIRE_10));
assign SYNTHESIZED_WIRE_8 = ~logic_S[0];
Mux_2_to_1 b2v_inst8(
.S(FS[0]),
.I1(C_in),
.I2(A_from_next_bit),
.OUT(SYNTHESIZED_WIRE_1));
Full_adder b2v_inst9(
.B(SYNTHESIZED_WIRE_9),
.A(SYNTHESIZED_WIRE_10),
.C_in(C_in),
.S(SYNTHESIZED_WIRE_0),
.C_out(SYNTHESIZED_WIRE_4));
assign logic_S[0] = B;
assign logic_S[1] = A;
endmodule
|
module sky130_fd_sc_hs__o22a (
X ,
A1 ,
A2 ,
B1 ,
B2 ,
VPWR,
VGND
);
// Module ports
output X ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input VPWR;
input VGND;
// Local signals
wire B2 or0_out ;
wire B2 or1_out ;
wire and0_out_X ;
wire u_vpwr_vgnd0_out_X;
// Name Output Other arguments
or or0 (or0_out , A2, A1 );
or or1 (or1_out , B2, B1 );
and and0 (and0_out_X , or0_out, or1_out );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_X, and0_out_X, VPWR, VGND);
buf buf0 (X , u_vpwr_vgnd0_out_X );
endmodule
|
module user_io #(parameter STRLEN=0) (
input [(8*STRLEN)-1:0] conf_str,
input SPI_CLK,
input SPI_SS_IO,
output reg SPI_MISO,
input SPI_MOSI,
output reg [7:0] joystick_0,
output reg [7:0] joystick_1,
output reg [15:0] joystick_analog_0,
output reg [15:0] joystick_analog_1,
output [1:0] buttons,
output [1:0] switches,
output scandoubler_disable,
output reg [7:0] status,
// connection to sd card emulation
input [31:0] sd_lba,
input sd_rd,
input sd_wr,
output reg sd_ack,
input sd_conf,
input sd_sdhc,
output [7:0] sd_dout, // valid on rising edge of sd_dout_strobe
output reg sd_dout_strobe,
input [7:0] sd_din,
output reg sd_din_strobe,
output reg sd_change,
// ps2 keyboard emulation
input ps2_clk, // 12-16khz provided by core
output ps2_kbd_clk,
output reg ps2_kbd_data,
output ps2_mouse_clk,
output reg ps2_mouse_data,
// serial com port
input [7:0] serial_data,
input serial_strobe
);
reg [6:0] sbuf;
reg [7:0] cmd;
reg [2:0] bit_cnt; // counts bits 0-7 0-7 ...
reg [7:0] byte_cnt; // counts bytes
reg [5:0] joystick0;
reg [5:0] joystick1;
reg [7:0] but_sw;
reg [2:0] stick_idx;
assign buttons = but_sw[1:0];
assign switches = but_sw[3:2];
assign scandoubler_disable = but_sw[4];
assign sd_dout = { sbuf, SPI_MOSI};
// this variant of user_io is for 8 bit cores (type == a4) only
wire [7:0] core_type = 8'ha4;
// command byte read by the io controller
wire [7:0] sd_cmd = { 4'h5, sd_conf, sd_sdhc, sd_wr, sd_rd };
// filter spi clock. the 8 bit gate delay is ~2.5ns in total
wire [7:0] spi_sck_D = { spi_sck_D[6:0], SPI_CLK } /* synthesis keep */;
wire spi_sck = (spi_sck && spi_sck_D != 8'h00) || (!spi_sck && spi_sck_D == 8'hff);
// drive MISO only when transmitting core id
always@(negedge spi_sck or posedge SPI_SS_IO) begin
if(SPI_SS_IO == 1) begin
SPI_MISO <= 1'bZ;
end else begin
// first byte returned is always core type, further bytes are
// command dependent
if(byte_cnt == 0) begin
SPI_MISO <= core_type[~bit_cnt];
end else begin
// reading serial fifo
if(cmd == 8'h1b) begin
// send alternating flag byte and data
if(byte_cnt[0]) SPI_MISO <= serial_out_status[~bit_cnt];
else SPI_MISO <= serial_out_byte[~bit_cnt];
end
// reading config string
else if(cmd == 8'h14) begin
// returning a byte from string
if(byte_cnt < STRLEN + 1)
SPI_MISO <= conf_str[{STRLEN - byte_cnt,~bit_cnt}];
else
SPI_MISO <= 1'b0;
end
// reading sd card status
else if(cmd == 8'h16) begin
if(byte_cnt == 1)
SPI_MISO <= sd_cmd[~bit_cnt];
else if((byte_cnt >= 2) && (byte_cnt < 6))
SPI_MISO <= sd_lba[{5-byte_cnt, ~bit_cnt}];
else
SPI_MISO <= 1'b0;
end
// reading sd card write data
else if(cmd == 8'h18)
SPI_MISO <= sd_din[~bit_cnt];
else
SPI_MISO <= 1'b0;
end
end
end
// ---------------- PS2 ---------------------
// 8 byte fifos to store ps2 bytes
localparam PS2_FIFO_BITS = 3;
// keyboard
reg [7:0] ps2_kbd_fifo [(2**PS2_FIFO_BITS)-1:0];
reg [PS2_FIFO_BITS-1:0] ps2_kbd_wptr;
reg [PS2_FIFO_BITS-1:0] ps2_kbd_rptr;
// ps2 transmitter state machine
reg [3:0] ps2_kbd_tx_state;
reg [7:0] ps2_kbd_tx_byte;
reg ps2_kbd_parity;
assign ps2_kbd_clk = ps2_clk || (ps2_kbd_tx_state == 0);
// ps2 transmitter
// Takes a byte from the FIFO and sends it in a ps2 compliant serial format.
reg ps2_kbd_r_inc;
always@(posedge ps2_clk) begin
ps2_kbd_r_inc <= 1'b0;
if(ps2_kbd_r_inc)
ps2_kbd_rptr <= ps2_kbd_rptr + 1;
// transmitter is idle?
if(ps2_kbd_tx_state == 0) begin
// data in fifo present?
if(ps2_kbd_wptr != ps2_kbd_rptr) begin
// load tx register from fifo
ps2_kbd_tx_byte <= ps2_kbd_fifo[ps2_kbd_rptr];
ps2_kbd_r_inc <= 1'b1;
// reset parity
ps2_kbd_parity <= 1'b1;
// start transmitter
ps2_kbd_tx_state <= 4'd1;
// put start bit on data line
ps2_kbd_data <= 1'b0; // start bit is 0
end
end else begin
// transmission of 8 data bits
if((ps2_kbd_tx_state >= 1)&&(ps2_kbd_tx_state < 9)) begin
ps2_kbd_data <= ps2_kbd_tx_byte[0]; // data bits
ps2_kbd_tx_byte[6:0] <= ps2_kbd_tx_byte[7:1]; // shift down
if(ps2_kbd_tx_byte[0])
ps2_kbd_parity <= !ps2_kbd_parity;
end
// transmission of parity
if(ps2_kbd_tx_state == 9)
ps2_kbd_data <= ps2_kbd_parity;
// transmission of stop bit
if(ps2_kbd_tx_state == 10)
ps2_kbd_data <= 1'b1; // stop bit is 1
// advance state machine
if(ps2_kbd_tx_state < 11)
ps2_kbd_tx_state <= ps2_kbd_tx_state + 4'd1;
else
ps2_kbd_tx_state <= 4'd0;
end
end
// mouse
reg [7:0] ps2_mouse_fifo [(2**PS2_FIFO_BITS)-1:0];
reg [PS2_FIFO_BITS-1:0] ps2_mouse_wptr;
reg [PS2_FIFO_BITS-1:0] ps2_mouse_rptr;
// ps2 transmitter state machine
reg [3:0] ps2_mouse_tx_state;
reg [7:0] ps2_mouse_tx_byte;
reg ps2_mouse_parity;
assign ps2_mouse_clk = ps2_clk || (ps2_mouse_tx_state == 0);
// ps2 transmitter
// Takes a byte from the FIFO and sends it in a ps2 compliant serial format.
reg ps2_mouse_r_inc;
always@(posedge ps2_clk) begin
ps2_mouse_r_inc <= 1'b0;
if(ps2_mouse_r_inc)
ps2_mouse_rptr <= ps2_mouse_rptr + 1;
// transmitter is idle?
if(ps2_mouse_tx_state == 0) begin
// data in fifo present?
if(ps2_mouse_wptr != ps2_mouse_rptr) begin
// load tx register from fifo
ps2_mouse_tx_byte <= ps2_mouse_fifo[ps2_mouse_rptr];
ps2_mouse_r_inc <= 1'b1;
// reset parity
ps2_mouse_parity <= 1'b1;
// start transmitter
ps2_mouse_tx_state <= 4'd1;
// put start bit on data line
ps2_mouse_data <= 1'b0; // start bit is 0
end
end else begin
// transmission of 8 data bits
if((ps2_mouse_tx_state >= 1)&&(ps2_mouse_tx_state < 9)) begin
ps2_mouse_data <= ps2_mouse_tx_byte[0]; // data bits
ps2_mouse_tx_byte[6:0] <= ps2_mouse_tx_byte[7:1]; // shift down
if(ps2_mouse_tx_byte[0])
ps2_mouse_parity <= !ps2_mouse_parity;
end
// transmission of parity
if(ps2_mouse_tx_state == 9)
ps2_mouse_data <= ps2_mouse_parity;
// transmission of stop bit
if(ps2_mouse_tx_state == 10)
ps2_mouse_data <= 1'b1; // stop bit is 1
// advance state machine
if(ps2_mouse_tx_state < 11)
ps2_mouse_tx_state <= ps2_mouse_tx_state + 4'd1;
else
ps2_mouse_tx_state <= 4'd0;
end
end
// fifo to receive serial data from core to be forwarded to io controller
// 16 byte fifo to store serial bytes
localparam SERIAL_OUT_FIFO_BITS = 6;
reg [7:0] serial_out_fifo [(2**SERIAL_OUT_FIFO_BITS)-1:0];
reg [SERIAL_OUT_FIFO_BITS-1:0] serial_out_wptr;
reg [SERIAL_OUT_FIFO_BITS-1:0] serial_out_rptr;
wire serial_out_data_available = serial_out_wptr != serial_out_rptr;
wire [7:0] serial_out_byte = serial_out_fifo[serial_out_rptr] /* synthesis keep */;
wire [7:0] serial_out_status = { 7'b1000000, serial_out_data_available};
// status[0] is reset signal from io controller and is thus used to flush
// the fifo
always @(posedge serial_strobe or posedge status[0]) begin
if(status[0] == 1) begin
serial_out_wptr <= 0;
end else begin
serial_out_fifo[serial_out_wptr] <= serial_data;
serial_out_wptr <= serial_out_wptr + 1;
end
end
always@(negedge spi_sck or posedge status[0]) begin
if(status[0] == 1) begin
serial_out_rptr <= 0;
end else begin
if((byte_cnt != 0) && (cmd == 8'h1b)) begin
// read last bit -> advance read pointer
if((bit_cnt == 7) && !byte_cnt[0] && serial_out_data_available)
serial_out_rptr <= serial_out_rptr + 1;
end
end
end
// SPI receiver
always@(posedge spi_sck or posedge SPI_SS_IO) begin
if(SPI_SS_IO == 1) begin
bit_cnt <= 3'd0;
byte_cnt <= 8'd0;
sd_ack <= 1'b0;
sd_dout_strobe <= 1'b0;
sd_din_strobe <= 1'b0;
sd_change <= 1'b0;
end else begin
sd_dout_strobe <= 1'b0;
sd_din_strobe <= 1'b0;
if(bit_cnt != 7)
sbuf[6:0] <= { sbuf[5:0], SPI_MOSI };
bit_cnt <= bit_cnt + 3'd1;
if((bit_cnt == 7)&&(byte_cnt != 8'd255))
byte_cnt <= byte_cnt + 8'd1;
// finished reading command byte
if(bit_cnt == 7) begin
if(byte_cnt == 0) begin
cmd <= { sbuf, SPI_MOSI};
// fetch first byte when sectore FPGA->IO command has been seen
if({ sbuf, SPI_MOSI} == 8'h18)
sd_din_strobe <= 1'b1;
if(({ sbuf, SPI_MOSI} == 8'h17) || ({ sbuf, SPI_MOSI} == 8'h18))
sd_ack <= 1'b1;
end else begin
// buttons and switches
if(cmd == 8'h01)
but_sw <= { sbuf, SPI_MOSI };
if(cmd == 8'h02)
joystick_0 <= { sbuf, SPI_MOSI };
if(cmd == 8'h03)
joystick_1 <= { sbuf, SPI_MOSI };
if(cmd == 8'h04) begin
// store incoming ps2 mouse bytes
ps2_mouse_fifo[ps2_mouse_wptr] <= { sbuf, SPI_MOSI };
ps2_mouse_wptr <= ps2_mouse_wptr + 1;
end
if(cmd == 8'h05) begin
// store incoming ps2 keyboard bytes
ps2_kbd_fifo[ps2_kbd_wptr] <= { sbuf, SPI_MOSI };
ps2_kbd_wptr <= ps2_kbd_wptr + 1;
end
if(cmd == 8'h15)
status <= { sbuf[6:0], SPI_MOSI };
// send sector IO -> FPGA
if(cmd == 8'h17) begin
// flag that download begins
sd_dout_strobe <= 1'b1;
end
// send sector FPGA -> IO
if(cmd == 8'h18)
sd_din_strobe <= 1'b1;
// send SD config IO -> FPGA
if(cmd == 8'h19) begin
// flag that download begins
// sd card knows data is config if sd_dout_strobe is asserted
// with sd_ack still being inactive (low)
sd_dout_strobe <= 1'b1;
end
// joystick analog
if(cmd == 8'h1a) begin
// first byte is joystick indes
if(byte_cnt == 1)
stick_idx <= { sbuf[1:0], SPI_MOSI };
else if(byte_cnt == 2) begin
// second byte is x axis
if(stick_idx == 0)
joystick_analog_0[15:8] <= { sbuf, SPI_MOSI };
else if(stick_idx == 1)
joystick_analog_1[15:8] <= { sbuf, SPI_MOSI };
end else if(byte_cnt == 3) begin
// third byte is y axis
if(stick_idx == 0)
joystick_analog_0[7:0] <= { sbuf, SPI_MOSI };
else if(stick_idx == 1)
joystick_analog_1[7:0] <= { sbuf, SPI_MOSI };
end
end
// set sd card status. The fact that this register is being
// set by the arm controller indicates a possible disk change
if(cmd == 8'h1c)
sd_change <= 1'b1;
end
end
end
end
endmodule
|
module red_pitaya_filter_block
#(
parameter STAGES = 1, //max. 4 stages
parameter SHIFTBITS = 4, //shift can be from 0 to 15 bits
parameter SIGNALBITS = 14, //bit width of the signals
parameter MINBW = 10
)
(
input clk_i,
input rstn_i ,
input [32-1:0] set_filter,
input signed [SIGNALBITS-1:0] dat_i,
output signed [SIGNALBITS-1:0] dat_o
);
//-----------------------------
// cascaded set of FILTERSTAGES low- or high-pass filters
wire signed [SIGNALBITS-1:0] filter_in[STAGES-1:0];
wire signed [SIGNALBITS-1:0] filter_out[STAGES-1:0];
assign filter_in[0] = dat_i;
assign dat_o = filter_out[STAGES-1];
genvar j;
generate for (j = 0; j < STAGES-1; j = j+1) begin
assign filter_in[j+1] = filter_out[j];
end endgenerate
generate for (j = 0; j < STAGES; j = j+1)
red_pitaya_lpf_block #(
.SHIFTBITS(SHIFTBITS),
.SIGNALBITS(SIGNALBITS),
.MINBW(MINBW)
)
lpf
(
.clk_i(clk_i),
.rstn_i(rstn_i),
.shift(set_filter[j*8+SHIFTBITS-1:j*8]),
.filter_on(set_filter[j*8+7]),
.highpass(set_filter[j*8+6]),
.signal_i(filter_in[j]),
.signal_o(filter_out[j])
);
endgenerate
endmodule
|
module sky130_fd_sc_ls__dfrbp_2 (
Q ,
Q_N ,
CLK ,
D ,
RESET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
output Q_N ;
input CLK ;
input D ;
input RESET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
sky130_fd_sc_ls__dfrbp base (
.Q(Q),
.Q_N(Q_N),
.CLK(CLK),
.D(D),
.RESET_B(RESET_B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
|
module sky130_fd_sc_ls__dfrbp_2 (
Q ,
Q_N ,
CLK ,
D ,
RESET_B
);
output Q ;
output Q_N ;
input CLK ;
input D ;
input RESET_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__dfrbp base (
.Q(Q),
.Q_N(Q_N),
.CLK(CLK),
.D(D),
.RESET_B(RESET_B)
);
endmodule
|
module mips_cop0 (
input clk,
input rst,
input[4:0] rd_addr,
output[31:0] rd_data,
output[31:0] rd_epc,
output rd_int,
output rd_status_exl,
input[4:0] wr_addr,
input wr_en,
input[31:0] wr_data,
input wr_status_exl_reset,
input wr_status_exl_set,
input wr_cause_en,
input wr_cause_bd,
input[5:0] wr_cause_int,
input[3:0] wr_cause_excode,
input wr_badvaddr_en,
input[31:0] wr_badvaddr_data
);
reg[31:0] epc;
reg[31:0] badvaddr;
reg cause_bd;
reg[5:0] cause_ip;
reg[3:0] cause_excode;
reg[5:0] status_im;
reg status_exl;
reg status_ie;
assign rd_epc= epc;
assign rd_status_exl= status_exl;
assign rd_data= rd_addr==5'd14 ? epc :
rd_addr==5'd13 ? {cause_bd,15'd0,
cause_ip,4'd0,
cause_excode,2'd0} :
rd_addr==5'd8 ? badvaddr :
{16'd0,
status_im,
8'd0,
status_exl,
status_ie};
assign rd_int= |(cause_ip & status_im) & status_ie & !status_exl;
always @(posedge clk)
if(rst)
begin
epc<= 32'd0;
cause_bd<= 1'b0;
cause_ip<= 6'd0;
cause_excode<= 4'd0;
status_im<= 6'd0;
status_exl<= 1'b1;
status_ie<= 1'b0;
badvaddr<= 32'd0;
end
else
begin
epc<= wr_en & wr_addr==5'd14 ? wr_data : epc;
cause_bd<= wr_cause_en ? wr_cause_bd : cause_bd;//31
cause_ip<= wr_cause_int;//15:10
cause_excode<= wr_cause_en ? wr_cause_excode :
cause_excode;//6:2
status_im<= wr_en & wr_addr==5'd12 ? wr_data[15:10] : status_im;
status_exl<= wr_status_exl_reset ? 1'b0 :
wr_status_exl_set ? 1'b1 :
wr_en & wr_addr==5'd12 ? wr_data[1] : status_exl;
status_ie<= wr_en & wr_addr==5'd12 ? wr_data[0] : status_ie;
badvaddr<= wr_badvaddr_en ? wr_badvaddr_data : badvaddr;
end
endmodule
|
module Computer_System_mm_interconnect_5 (
input wire System_PLL_sys_clk_clk, // System_PLL_sys_clk.clk
input wire Expansion_JP2_reset_reset_bridge_in_reset_reset, // Expansion_JP2_reset_reset_bridge_in_reset.reset
input wire Video_In_Subsystem_sys_reset_reset_bridge_in_reset_reset, // Video_In_Subsystem_sys_reset_reset_bridge_in_reset.reset
input wire [3:0] Video_In_Subsystem_top_io_gpi2_streamin_address, // Video_In_Subsystem_top_io_gpi2_streamin.address
input wire Video_In_Subsystem_top_io_gpi2_streamin_chipselect, // .chipselect
input wire Video_In_Subsystem_top_io_gpi2_streamin_read, // .read
output wire [31:0] Video_In_Subsystem_top_io_gpi2_streamin_readdata, // .readdata
input wire [3:0] Video_In_Subsystem_top_io_gpo2_streamout_address, // Video_In_Subsystem_top_io_gpo2_streamout.address
input wire Video_In_Subsystem_top_io_gpo2_streamout_chipselect, // .chipselect
input wire Video_In_Subsystem_top_io_gpo2_streamout_write, // .write
input wire [31:0] Video_In_Subsystem_top_io_gpo2_streamout_writedata, // .writedata
output wire [1:0] Expansion_JP2_s1_address, // Expansion_JP2_s1.address
output wire Expansion_JP2_s1_write, // .write
input wire [31:0] Expansion_JP2_s1_readdata, // .readdata
output wire [31:0] Expansion_JP2_s1_writedata, // .writedata
output wire Expansion_JP2_s1_chipselect // .chipselect
);
wire video_in_subsystem_top_io_gpi2_streamin_translator_avalon_universal_master_0_waitrequest; // Video_In_Subsystem_top_io_gpi2_streamin_agent:av_waitrequest -> Video_In_Subsystem_top_io_gpi2_streamin_translator:uav_waitrequest
wire [31:0] video_in_subsystem_top_io_gpi2_streamin_translator_avalon_universal_master_0_readdata; // Video_In_Subsystem_top_io_gpi2_streamin_agent:av_readdata -> Video_In_Subsystem_top_io_gpi2_streamin_translator:uav_readdata
wire video_in_subsystem_top_io_gpi2_streamin_translator_avalon_universal_master_0_debugaccess; // Video_In_Subsystem_top_io_gpi2_streamin_translator:uav_debugaccess -> Video_In_Subsystem_top_io_gpi2_streamin_agent:av_debugaccess
wire [3:0] video_in_subsystem_top_io_gpi2_streamin_translator_avalon_universal_master_0_address; // Video_In_Subsystem_top_io_gpi2_streamin_translator:uav_address -> Video_In_Subsystem_top_io_gpi2_streamin_agent:av_address
wire video_in_subsystem_top_io_gpi2_streamin_translator_avalon_universal_master_0_read; // Video_In_Subsystem_top_io_gpi2_streamin_translator:uav_read -> Video_In_Subsystem_top_io_gpi2_streamin_agent:av_read
wire [3:0] video_in_subsystem_top_io_gpi2_streamin_translator_avalon_universal_master_0_byteenable; // Video_In_Subsystem_top_io_gpi2_streamin_translator:uav_byteenable -> Video_In_Subsystem_top_io_gpi2_streamin_agent:av_byteenable
wire video_in_subsystem_top_io_gpi2_streamin_translator_avalon_universal_master_0_readdatavalid; // Video_In_Subsystem_top_io_gpi2_streamin_agent:av_readdatavalid -> Video_In_Subsystem_top_io_gpi2_streamin_translator:uav_readdatavalid
wire video_in_subsystem_top_io_gpi2_streamin_translator_avalon_universal_master_0_lock; // Video_In_Subsystem_top_io_gpi2_streamin_translator:uav_lock -> Video_In_Subsystem_top_io_gpi2_streamin_agent:av_lock
wire video_in_subsystem_top_io_gpi2_streamin_translator_avalon_universal_master_0_write; // Video_In_Subsystem_top_io_gpi2_streamin_translator:uav_write -> Video_In_Subsystem_top_io_gpi2_streamin_agent:av_write
wire [31:0] video_in_subsystem_top_io_gpi2_streamin_translator_avalon_universal_master_0_writedata; // Video_In_Subsystem_top_io_gpi2_streamin_translator:uav_writedata -> Video_In_Subsystem_top_io_gpi2_streamin_agent:av_writedata
wire [2:0] video_in_subsystem_top_io_gpi2_streamin_translator_avalon_universal_master_0_burstcount; // Video_In_Subsystem_top_io_gpi2_streamin_translator:uav_burstcount -> Video_In_Subsystem_top_io_gpi2_streamin_agent:av_burstcount
wire rsp_mux_src_valid; // rsp_mux:src_valid -> Video_In_Subsystem_top_io_gpi2_streamin_agent:rp_valid
wire [73:0] rsp_mux_src_data; // rsp_mux:src_data -> Video_In_Subsystem_top_io_gpi2_streamin_agent:rp_data
wire rsp_mux_src_ready; // Video_In_Subsystem_top_io_gpi2_streamin_agent:rp_ready -> rsp_mux:src_ready
wire [1:0] rsp_mux_src_channel; // rsp_mux:src_channel -> Video_In_Subsystem_top_io_gpi2_streamin_agent:rp_channel
wire rsp_mux_src_startofpacket; // rsp_mux:src_startofpacket -> Video_In_Subsystem_top_io_gpi2_streamin_agent:rp_startofpacket
wire rsp_mux_src_endofpacket; // rsp_mux:src_endofpacket -> Video_In_Subsystem_top_io_gpi2_streamin_agent:rp_endofpacket
wire video_in_subsystem_top_io_gpo2_streamout_translator_avalon_universal_master_0_waitrequest; // Video_In_Subsystem_top_io_gpo2_streamout_agent:av_waitrequest -> Video_In_Subsystem_top_io_gpo2_streamout_translator:uav_waitrequest
wire [31:0] video_in_subsystem_top_io_gpo2_streamout_translator_avalon_universal_master_0_readdata; // Video_In_Subsystem_top_io_gpo2_streamout_agent:av_readdata -> Video_In_Subsystem_top_io_gpo2_streamout_translator:uav_readdata
wire video_in_subsystem_top_io_gpo2_streamout_translator_avalon_universal_master_0_debugaccess; // Video_In_Subsystem_top_io_gpo2_streamout_translator:uav_debugaccess -> Video_In_Subsystem_top_io_gpo2_streamout_agent:av_debugaccess
wire [3:0] video_in_subsystem_top_io_gpo2_streamout_translator_avalon_universal_master_0_address; // Video_In_Subsystem_top_io_gpo2_streamout_translator:uav_address -> Video_In_Subsystem_top_io_gpo2_streamout_agent:av_address
wire video_in_subsystem_top_io_gpo2_streamout_translator_avalon_universal_master_0_read; // Video_In_Subsystem_top_io_gpo2_streamout_translator:uav_read -> Video_In_Subsystem_top_io_gpo2_streamout_agent:av_read
wire [3:0] video_in_subsystem_top_io_gpo2_streamout_translator_avalon_universal_master_0_byteenable; // Video_In_Subsystem_top_io_gpo2_streamout_translator:uav_byteenable -> Video_In_Subsystem_top_io_gpo2_streamout_agent:av_byteenable
wire video_in_subsystem_top_io_gpo2_streamout_translator_avalon_universal_master_0_readdatavalid; // Video_In_Subsystem_top_io_gpo2_streamout_agent:av_readdatavalid -> Video_In_Subsystem_top_io_gpo2_streamout_translator:uav_readdatavalid
wire video_in_subsystem_top_io_gpo2_streamout_translator_avalon_universal_master_0_lock; // Video_In_Subsystem_top_io_gpo2_streamout_translator:uav_lock -> Video_In_Subsystem_top_io_gpo2_streamout_agent:av_lock
wire video_in_subsystem_top_io_gpo2_streamout_translator_avalon_universal_master_0_write; // Video_In_Subsystem_top_io_gpo2_streamout_translator:uav_write -> Video_In_Subsystem_top_io_gpo2_streamout_agent:av_write
wire [31:0] video_in_subsystem_top_io_gpo2_streamout_translator_avalon_universal_master_0_writedata; // Video_In_Subsystem_top_io_gpo2_streamout_translator:uav_writedata -> Video_In_Subsystem_top_io_gpo2_streamout_agent:av_writedata
wire [2:0] video_in_subsystem_top_io_gpo2_streamout_translator_avalon_universal_master_0_burstcount; // Video_In_Subsystem_top_io_gpo2_streamout_translator:uav_burstcount -> Video_In_Subsystem_top_io_gpo2_streamout_agent:av_burstcount
wire rsp_mux_001_src_valid; // rsp_mux_001:src_valid -> Video_In_Subsystem_top_io_gpo2_streamout_agent:rp_valid
wire [73:0] rsp_mux_001_src_data; // rsp_mux_001:src_data -> Video_In_Subsystem_top_io_gpo2_streamout_agent:rp_data
wire rsp_mux_001_src_ready; // Video_In_Subsystem_top_io_gpo2_streamout_agent:rp_ready -> rsp_mux_001:src_ready
wire [1:0] rsp_mux_001_src_channel; // rsp_mux_001:src_channel -> Video_In_Subsystem_top_io_gpo2_streamout_agent:rp_channel
wire rsp_mux_001_src_startofpacket; // rsp_mux_001:src_startofpacket -> Video_In_Subsystem_top_io_gpo2_streamout_agent:rp_startofpacket
wire rsp_mux_001_src_endofpacket; // rsp_mux_001:src_endofpacket -> Video_In_Subsystem_top_io_gpo2_streamout_agent:rp_endofpacket
wire [31:0] expansion_jp2_s1_agent_m0_readdata; // Expansion_JP2_s1_translator:uav_readdata -> Expansion_JP2_s1_agent:m0_readdata
wire expansion_jp2_s1_agent_m0_waitrequest; // Expansion_JP2_s1_translator:uav_waitrequest -> Expansion_JP2_s1_agent:m0_waitrequest
wire expansion_jp2_s1_agent_m0_debugaccess; // Expansion_JP2_s1_agent:m0_debugaccess -> Expansion_JP2_s1_translator:uav_debugaccess
wire [3:0] expansion_jp2_s1_agent_m0_address; // Expansion_JP2_s1_agent:m0_address -> Expansion_JP2_s1_translator:uav_address
wire [3:0] expansion_jp2_s1_agent_m0_byteenable; // Expansion_JP2_s1_agent:m0_byteenable -> Expansion_JP2_s1_translator:uav_byteenable
wire expansion_jp2_s1_agent_m0_read; // Expansion_JP2_s1_agent:m0_read -> Expansion_JP2_s1_translator:uav_read
wire expansion_jp2_s1_agent_m0_readdatavalid; // Expansion_JP2_s1_translator:uav_readdatavalid -> Expansion_JP2_s1_agent:m0_readdatavalid
wire expansion_jp2_s1_agent_m0_lock; // Expansion_JP2_s1_agent:m0_lock -> Expansion_JP2_s1_translator:uav_lock
wire [31:0] expansion_jp2_s1_agent_m0_writedata; // Expansion_JP2_s1_agent:m0_writedata -> Expansion_JP2_s1_translator:uav_writedata
wire expansion_jp2_s1_agent_m0_write; // Expansion_JP2_s1_agent:m0_write -> Expansion_JP2_s1_translator:uav_write
wire [2:0] expansion_jp2_s1_agent_m0_burstcount; // Expansion_JP2_s1_agent:m0_burstcount -> Expansion_JP2_s1_translator:uav_burstcount
wire expansion_jp2_s1_agent_rf_source_valid; // Expansion_JP2_s1_agent:rf_source_valid -> Expansion_JP2_s1_agent_rsp_fifo:in_valid
wire [74:0] expansion_jp2_s1_agent_rf_source_data; // Expansion_JP2_s1_agent:rf_source_data -> Expansion_JP2_s1_agent_rsp_fifo:in_data
wire expansion_jp2_s1_agent_rf_source_ready; // Expansion_JP2_s1_agent_rsp_fifo:in_ready -> Expansion_JP2_s1_agent:rf_source_ready
wire expansion_jp2_s1_agent_rf_source_startofpacket; // Expansion_JP2_s1_agent:rf_source_startofpacket -> Expansion_JP2_s1_agent_rsp_fifo:in_startofpacket
wire expansion_jp2_s1_agent_rf_source_endofpacket; // Expansion_JP2_s1_agent:rf_source_endofpacket -> Expansion_JP2_s1_agent_rsp_fifo:in_endofpacket
wire expansion_jp2_s1_agent_rsp_fifo_out_valid; // Expansion_JP2_s1_agent_rsp_fifo:out_valid -> Expansion_JP2_s1_agent:rf_sink_valid
wire [74:0] expansion_jp2_s1_agent_rsp_fifo_out_data; // Expansion_JP2_s1_agent_rsp_fifo:out_data -> Expansion_JP2_s1_agent:rf_sink_data
wire expansion_jp2_s1_agent_rsp_fifo_out_ready; // Expansion_JP2_s1_agent:rf_sink_ready -> Expansion_JP2_s1_agent_rsp_fifo:out_ready
wire expansion_jp2_s1_agent_rsp_fifo_out_startofpacket; // Expansion_JP2_s1_agent_rsp_fifo:out_startofpacket -> Expansion_JP2_s1_agent:rf_sink_startofpacket
wire expansion_jp2_s1_agent_rsp_fifo_out_endofpacket; // Expansion_JP2_s1_agent_rsp_fifo:out_endofpacket -> Expansion_JP2_s1_agent:rf_sink_endofpacket
wire cmd_mux_src_valid; // cmd_mux:src_valid -> Expansion_JP2_s1_agent:cp_valid
wire [73:0] cmd_mux_src_data; // cmd_mux:src_data -> Expansion_JP2_s1_agent:cp_data
wire cmd_mux_src_ready; // Expansion_JP2_s1_agent:cp_ready -> cmd_mux:src_ready
wire [1:0] cmd_mux_src_channel; // cmd_mux:src_channel -> Expansion_JP2_s1_agent:cp_channel
wire cmd_mux_src_startofpacket; // cmd_mux:src_startofpacket -> Expansion_JP2_s1_agent:cp_startofpacket
wire cmd_mux_src_endofpacket; // cmd_mux:src_endofpacket -> Expansion_JP2_s1_agent:cp_endofpacket
wire video_in_subsystem_top_io_gpi2_streamin_agent_cp_valid; // Video_In_Subsystem_top_io_gpi2_streamin_agent:cp_valid -> router:sink_valid
wire [73:0] video_in_subsystem_top_io_gpi2_streamin_agent_cp_data; // Video_In_Subsystem_top_io_gpi2_streamin_agent:cp_data -> router:sink_data
wire video_in_subsystem_top_io_gpi2_streamin_agent_cp_ready; // router:sink_ready -> Video_In_Subsystem_top_io_gpi2_streamin_agent:cp_ready
wire video_in_subsystem_top_io_gpi2_streamin_agent_cp_startofpacket; // Video_In_Subsystem_top_io_gpi2_streamin_agent:cp_startofpacket -> router:sink_startofpacket
wire video_in_subsystem_top_io_gpi2_streamin_agent_cp_endofpacket; // Video_In_Subsystem_top_io_gpi2_streamin_agent:cp_endofpacket -> router:sink_endofpacket
wire router_src_valid; // router:src_valid -> cmd_demux:sink_valid
wire [73:0] router_src_data; // router:src_data -> cmd_demux:sink_data
wire router_src_ready; // cmd_demux:sink_ready -> router:src_ready
wire [1:0] router_src_channel; // router:src_channel -> cmd_demux:sink_channel
wire router_src_startofpacket; // router:src_startofpacket -> cmd_demux:sink_startofpacket
wire router_src_endofpacket; // router:src_endofpacket -> cmd_demux:sink_endofpacket
wire video_in_subsystem_top_io_gpo2_streamout_agent_cp_valid; // Video_In_Subsystem_top_io_gpo2_streamout_agent:cp_valid -> router_001:sink_valid
wire [73:0] video_in_subsystem_top_io_gpo2_streamout_agent_cp_data; // Video_In_Subsystem_top_io_gpo2_streamout_agent:cp_data -> router_001:sink_data
wire video_in_subsystem_top_io_gpo2_streamout_agent_cp_ready; // router_001:sink_ready -> Video_In_Subsystem_top_io_gpo2_streamout_agent:cp_ready
wire video_in_subsystem_top_io_gpo2_streamout_agent_cp_startofpacket; // Video_In_Subsystem_top_io_gpo2_streamout_agent:cp_startofpacket -> router_001:sink_startofpacket
wire video_in_subsystem_top_io_gpo2_streamout_agent_cp_endofpacket; // Video_In_Subsystem_top_io_gpo2_streamout_agent:cp_endofpacket -> router_001:sink_endofpacket
wire router_001_src_valid; // router_001:src_valid -> cmd_demux_001:sink_valid
wire [73:0] router_001_src_data; // router_001:src_data -> cmd_demux_001:sink_data
wire router_001_src_ready; // cmd_demux_001:sink_ready -> router_001:src_ready
wire [1:0] router_001_src_channel; // router_001:src_channel -> cmd_demux_001:sink_channel
wire router_001_src_startofpacket; // router_001:src_startofpacket -> cmd_demux_001:sink_startofpacket
wire router_001_src_endofpacket; // router_001:src_endofpacket -> cmd_demux_001:sink_endofpacket
wire expansion_jp2_s1_agent_rp_valid; // Expansion_JP2_s1_agent:rp_valid -> router_002:sink_valid
wire [73:0] expansion_jp2_s1_agent_rp_data; // Expansion_JP2_s1_agent:rp_data -> router_002:sink_data
wire expansion_jp2_s1_agent_rp_ready; // router_002:sink_ready -> Expansion_JP2_s1_agent:rp_ready
wire expansion_jp2_s1_agent_rp_startofpacket; // Expansion_JP2_s1_agent:rp_startofpacket -> router_002:sink_startofpacket
wire expansion_jp2_s1_agent_rp_endofpacket; // Expansion_JP2_s1_agent:rp_endofpacket -> router_002:sink_endofpacket
wire router_002_src_valid; // router_002:src_valid -> rsp_demux:sink_valid
wire [73:0] router_002_src_data; // router_002:src_data -> rsp_demux:sink_data
wire router_002_src_ready; // rsp_demux:sink_ready -> router_002:src_ready
wire [1:0] router_002_src_channel; // router_002:src_channel -> rsp_demux:sink_channel
wire router_002_src_startofpacket; // router_002:src_startofpacket -> rsp_demux:sink_startofpacket
wire router_002_src_endofpacket; // router_002:src_endofpacket -> rsp_demux:sink_endofpacket
wire cmd_demux_src0_valid; // cmd_demux:src0_valid -> cmd_mux:sink0_valid
wire [73:0] cmd_demux_src0_data; // cmd_demux:src0_data -> cmd_mux:sink0_data
wire cmd_demux_src0_ready; // cmd_mux:sink0_ready -> cmd_demux:src0_ready
wire [1:0] cmd_demux_src0_channel; // cmd_demux:src0_channel -> cmd_mux:sink0_channel
wire cmd_demux_src0_startofpacket; // cmd_demux:src0_startofpacket -> cmd_mux:sink0_startofpacket
wire cmd_demux_src0_endofpacket; // cmd_demux:src0_endofpacket -> cmd_mux:sink0_endofpacket
wire cmd_demux_001_src0_valid; // cmd_demux_001:src0_valid -> cmd_mux:sink1_valid
wire [73:0] cmd_demux_001_src0_data; // cmd_demux_001:src0_data -> cmd_mux:sink1_data
wire cmd_demux_001_src0_ready; // cmd_mux:sink1_ready -> cmd_demux_001:src0_ready
wire [1:0] cmd_demux_001_src0_channel; // cmd_demux_001:src0_channel -> cmd_mux:sink1_channel
wire cmd_demux_001_src0_startofpacket; // cmd_demux_001:src0_startofpacket -> cmd_mux:sink1_startofpacket
wire cmd_demux_001_src0_endofpacket; // cmd_demux_001:src0_endofpacket -> cmd_mux:sink1_endofpacket
wire rsp_demux_src0_valid; // rsp_demux:src0_valid -> rsp_mux:sink0_valid
wire [73:0] rsp_demux_src0_data; // rsp_demux:src0_data -> rsp_mux:sink0_data
wire rsp_demux_src0_ready; // rsp_mux:sink0_ready -> rsp_demux:src0_ready
wire [1:0] rsp_demux_src0_channel; // rsp_demux:src0_channel -> rsp_mux:sink0_channel
wire rsp_demux_src0_startofpacket; // rsp_demux:src0_startofpacket -> rsp_mux:sink0_startofpacket
wire rsp_demux_src0_endofpacket; // rsp_demux:src0_endofpacket -> rsp_mux:sink0_endofpacket
wire rsp_demux_src1_valid; // rsp_demux:src1_valid -> rsp_mux_001:sink0_valid
wire [73:0] rsp_demux_src1_data; // rsp_demux:src1_data -> rsp_mux_001:sink0_data
wire rsp_demux_src1_ready; // rsp_mux_001:sink0_ready -> rsp_demux:src1_ready
wire [1:0] rsp_demux_src1_channel; // rsp_demux:src1_channel -> rsp_mux_001:sink0_channel
wire rsp_demux_src1_startofpacket; // rsp_demux:src1_startofpacket -> rsp_mux_001:sink0_startofpacket
wire rsp_demux_src1_endofpacket; // rsp_demux:src1_endofpacket -> rsp_mux_001:sink0_endofpacket
wire expansion_jp2_s1_agent_rdata_fifo_src_valid; // Expansion_JP2_s1_agent:rdata_fifo_src_valid -> avalon_st_adapter:in_0_valid
wire [33:0] expansion_jp2_s1_agent_rdata_fifo_src_data; // Expansion_JP2_s1_agent:rdata_fifo_src_data -> avalon_st_adapter:in_0_data
wire expansion_jp2_s1_agent_rdata_fifo_src_ready; // avalon_st_adapter:in_0_ready -> Expansion_JP2_s1_agent:rdata_fifo_src_ready
wire avalon_st_adapter_out_0_valid; // avalon_st_adapter:out_0_valid -> Expansion_JP2_s1_agent:rdata_fifo_sink_valid
wire [33:0] avalon_st_adapter_out_0_data; // avalon_st_adapter:out_0_data -> Expansion_JP2_s1_agent:rdata_fifo_sink_data
wire avalon_st_adapter_out_0_ready; // Expansion_JP2_s1_agent:rdata_fifo_sink_ready -> avalon_st_adapter:out_0_ready
wire [0:0] avalon_st_adapter_out_0_error; // avalon_st_adapter:out_0_error -> Expansion_JP2_s1_agent:rdata_fifo_sink_error
altera_merlin_master_translator #(
.AV_ADDRESS_W (4),
.AV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (4),
.UAV_BURSTCOUNT_W (3),
.USE_READ (1),
.USE_WRITE (0),
.USE_BEGINBURSTTRANSFER (0),
.USE_BEGINTRANSFER (0),
.USE_CHIPSELECT (1),
.USE_BURSTCOUNT (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (1),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_LINEWRAPBURSTS (0),
.AV_REGISTERINCOMINGSIGNALS (0)
) video_in_subsystem_top_io_gpi2_streamin_translator (
.clk (System_PLL_sys_clk_clk), // clk.clk
.reset (Expansion_JP2_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (video_in_subsystem_top_io_gpi2_streamin_translator_avalon_universal_master_0_address), // avalon_universal_master_0.address
.uav_burstcount (video_in_subsystem_top_io_gpi2_streamin_translator_avalon_universal_master_0_burstcount), // .burstcount
.uav_read (video_in_subsystem_top_io_gpi2_streamin_translator_avalon_universal_master_0_read), // .read
.uav_write (video_in_subsystem_top_io_gpi2_streamin_translator_avalon_universal_master_0_write), // .write
.uav_waitrequest (video_in_subsystem_top_io_gpi2_streamin_translator_avalon_universal_master_0_waitrequest), // .waitrequest
.uav_readdatavalid (video_in_subsystem_top_io_gpi2_streamin_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
.uav_byteenable (video_in_subsystem_top_io_gpi2_streamin_translator_avalon_universal_master_0_byteenable), // .byteenable
.uav_readdata (video_in_subsystem_top_io_gpi2_streamin_translator_avalon_universal_master_0_readdata), // .readdata
.uav_writedata (video_in_subsystem_top_io_gpi2_streamin_translator_avalon_universal_master_0_writedata), // .writedata
.uav_lock (video_in_subsystem_top_io_gpi2_streamin_translator_avalon_universal_master_0_lock), // .lock
.uav_debugaccess (video_in_subsystem_top_io_gpi2_streamin_translator_avalon_universal_master_0_debugaccess), // .debugaccess
.av_address (Video_In_Subsystem_top_io_gpi2_streamin_address), // avalon_anti_master_0.address
.av_chipselect (Video_In_Subsystem_top_io_gpi2_streamin_chipselect), // .chipselect
.av_read (Video_In_Subsystem_top_io_gpi2_streamin_read), // .read
.av_readdata (Video_In_Subsystem_top_io_gpi2_streamin_readdata), // .readdata
.av_waitrequest (), // (terminated)
.av_burstcount (1'b1), // (terminated)
.av_byteenable (4'b1111), // (terminated)
.av_beginbursttransfer (1'b0), // (terminated)
.av_begintransfer (1'b0), // (terminated)
.av_readdatavalid (), // (terminated)
.av_write (1'b0), // (terminated)
.av_writedata (32'b00000000000000000000000000000000), // (terminated)
.av_lock (1'b0), // (terminated)
.av_debugaccess (1'b0), // (terminated)
.uav_clken (), // (terminated)
.av_clken (1'b1), // (terminated)
.uav_response (2'b00), // (terminated)
.av_response (), // (terminated)
.uav_writeresponsevalid (1'b0), // (terminated)
.av_writeresponsevalid () // (terminated)
);
altera_merlin_master_translator #(
.AV_ADDRESS_W (4),
.AV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (4),
.UAV_BURSTCOUNT_W (3),
.USE_READ (0),
.USE_WRITE (1),
.USE_BEGINBURSTTRANSFER (0),
.USE_BEGINTRANSFER (0),
.USE_CHIPSELECT (1),
.USE_BURSTCOUNT (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (1),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_LINEWRAPBURSTS (0),
.AV_REGISTERINCOMINGSIGNALS (0)
) video_in_subsystem_top_io_gpo2_streamout_translator (
.clk (System_PLL_sys_clk_clk), // clk.clk
.reset (Expansion_JP2_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (video_in_subsystem_top_io_gpo2_streamout_translator_avalon_universal_master_0_address), // avalon_universal_master_0.address
.uav_burstcount (video_in_subsystem_top_io_gpo2_streamout_translator_avalon_universal_master_0_burstcount), // .burstcount
.uav_read (video_in_subsystem_top_io_gpo2_streamout_translator_avalon_universal_master_0_read), // .read
.uav_write (video_in_subsystem_top_io_gpo2_streamout_translator_avalon_universal_master_0_write), // .write
.uav_waitrequest (video_in_subsystem_top_io_gpo2_streamout_translator_avalon_universal_master_0_waitrequest), // .waitrequest
.uav_readdatavalid (video_in_subsystem_top_io_gpo2_streamout_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
.uav_byteenable (video_in_subsystem_top_io_gpo2_streamout_translator_avalon_universal_master_0_byteenable), // .byteenable
.uav_readdata (video_in_subsystem_top_io_gpo2_streamout_translator_avalon_universal_master_0_readdata), // .readdata
.uav_writedata (video_in_subsystem_top_io_gpo2_streamout_translator_avalon_universal_master_0_writedata), // .writedata
.uav_lock (video_in_subsystem_top_io_gpo2_streamout_translator_avalon_universal_master_0_lock), // .lock
.uav_debugaccess (video_in_subsystem_top_io_gpo2_streamout_translator_avalon_universal_master_0_debugaccess), // .debugaccess
.av_address (Video_In_Subsystem_top_io_gpo2_streamout_address), // avalon_anti_master_0.address
.av_chipselect (Video_In_Subsystem_top_io_gpo2_streamout_chipselect), // .chipselect
.av_write (Video_In_Subsystem_top_io_gpo2_streamout_write), // .write
.av_writedata (Video_In_Subsystem_top_io_gpo2_streamout_writedata), // .writedata
.av_waitrequest (), // (terminated)
.av_burstcount (1'b1), // (terminated)
.av_byteenable (4'b1111), // (terminated)
.av_beginbursttransfer (1'b0), // (terminated)
.av_begintransfer (1'b0), // (terminated)
.av_read (1'b0), // (terminated)
.av_readdata (), // (terminated)
.av_readdatavalid (), // (terminated)
.av_lock (1'b0), // (terminated)
.av_debugaccess (1'b0), // (terminated)
.uav_clken (), // (terminated)
.av_clken (1'b1), // (terminated)
.uav_response (2'b00), // (terminated)
.av_response (), // (terminated)
.uav_writeresponsevalid (1'b0), // (terminated)
.av_writeresponsevalid () // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (2),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (1),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (4),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (0),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) expansion_jp2_s1_translator (
.clk (System_PLL_sys_clk_clk), // clk.clk
.reset (Expansion_JP2_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (expansion_jp2_s1_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (expansion_jp2_s1_agent_m0_burstcount), // .burstcount
.uav_read (expansion_jp2_s1_agent_m0_read), // .read
.uav_write (expansion_jp2_s1_agent_m0_write), // .write
.uav_waitrequest (expansion_jp2_s1_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (expansion_jp2_s1_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (expansion_jp2_s1_agent_m0_byteenable), // .byteenable
.uav_readdata (expansion_jp2_s1_agent_m0_readdata), // .readdata
.uav_writedata (expansion_jp2_s1_agent_m0_writedata), // .writedata
.uav_lock (expansion_jp2_s1_agent_m0_lock), // .lock
.uav_debugaccess (expansion_jp2_s1_agent_m0_debugaccess), // .debugaccess
.av_address (Expansion_JP2_s1_address), // avalon_anti_slave_0.address
.av_write (Expansion_JP2_s1_write), // .write
.av_readdata (Expansion_JP2_s1_readdata), // .readdata
.av_writedata (Expansion_JP2_s1_writedata), // .writedata
.av_chipselect (Expansion_JP2_s1_chipselect), // .chipselect
.av_read (), // (terminated)
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_byteenable (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_waitrequest (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_master_agent #(
.PKT_ORI_BURST_SIZE_H (73),
.PKT_ORI_BURST_SIZE_L (71),
.PKT_RESPONSE_STATUS_H (70),
.PKT_RESPONSE_STATUS_L (69),
.PKT_QOS_H (58),
.PKT_QOS_L (58),
.PKT_DATA_SIDEBAND_H (56),
.PKT_DATA_SIDEBAND_L (56),
.PKT_ADDR_SIDEBAND_H (55),
.PKT_ADDR_SIDEBAND_L (55),
.PKT_BURST_TYPE_H (54),
.PKT_BURST_TYPE_L (53),
.PKT_CACHE_H (68),
.PKT_CACHE_L (65),
.PKT_THREAD_ID_H (61),
.PKT_THREAD_ID_L (61),
.PKT_BURST_SIZE_H (52),
.PKT_BURST_SIZE_L (50),
.PKT_TRANS_EXCLUSIVE (45),
.PKT_TRANS_LOCK (44),
.PKT_BEGIN_BURST (57),
.PKT_PROTECTION_H (64),
.PKT_PROTECTION_L (62),
.PKT_BURSTWRAP_H (49),
.PKT_BURSTWRAP_L (49),
.PKT_BYTE_CNT_H (48),
.PKT_BYTE_CNT_L (46),
.PKT_ADDR_H (39),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (40),
.PKT_TRANS_POSTED (41),
.PKT_TRANS_WRITE (42),
.PKT_TRANS_READ (43),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (59),
.PKT_SRC_ID_L (59),
.PKT_DEST_ID_H (60),
.PKT_DEST_ID_L (60),
.ST_DATA_W (74),
.ST_CHANNEL_W (2),
.AV_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_RSP (0),
.ID (0),
.BURSTWRAP_VALUE (1),
.CACHE_VALUE (0),
.SECURE_ACCESS_BIT (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) video_in_subsystem_top_io_gpi2_streamin_agent (
.clk (System_PLL_sys_clk_clk), // clk.clk
.reset (Expansion_JP2_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.av_address (video_in_subsystem_top_io_gpi2_streamin_translator_avalon_universal_master_0_address), // av.address
.av_write (video_in_subsystem_top_io_gpi2_streamin_translator_avalon_universal_master_0_write), // .write
.av_read (video_in_subsystem_top_io_gpi2_streamin_translator_avalon_universal_master_0_read), // .read
.av_writedata (video_in_subsystem_top_io_gpi2_streamin_translator_avalon_universal_master_0_writedata), // .writedata
.av_readdata (video_in_subsystem_top_io_gpi2_streamin_translator_avalon_universal_master_0_readdata), // .readdata
.av_waitrequest (video_in_subsystem_top_io_gpi2_streamin_translator_avalon_universal_master_0_waitrequest), // .waitrequest
.av_readdatavalid (video_in_subsystem_top_io_gpi2_streamin_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
.av_byteenable (video_in_subsystem_top_io_gpi2_streamin_translator_avalon_universal_master_0_byteenable), // .byteenable
.av_burstcount (video_in_subsystem_top_io_gpi2_streamin_translator_avalon_universal_master_0_burstcount), // .burstcount
.av_debugaccess (video_in_subsystem_top_io_gpi2_streamin_translator_avalon_universal_master_0_debugaccess), // .debugaccess
.av_lock (video_in_subsystem_top_io_gpi2_streamin_translator_avalon_universal_master_0_lock), // .lock
.cp_valid (video_in_subsystem_top_io_gpi2_streamin_agent_cp_valid), // cp.valid
.cp_data (video_in_subsystem_top_io_gpi2_streamin_agent_cp_data), // .data
.cp_startofpacket (video_in_subsystem_top_io_gpi2_streamin_agent_cp_startofpacket), // .startofpacket
.cp_endofpacket (video_in_subsystem_top_io_gpi2_streamin_agent_cp_endofpacket), // .endofpacket
.cp_ready (video_in_subsystem_top_io_gpi2_streamin_agent_cp_ready), // .ready
.rp_valid (rsp_mux_src_valid), // rp.valid
.rp_data (rsp_mux_src_data), // .data
.rp_channel (rsp_mux_src_channel), // .channel
.rp_startofpacket (rsp_mux_src_startofpacket), // .startofpacket
.rp_endofpacket (rsp_mux_src_endofpacket), // .endofpacket
.rp_ready (rsp_mux_src_ready), // .ready
.av_response (), // (terminated)
.av_writeresponsevalid () // (terminated)
);
altera_merlin_master_agent #(
.PKT_ORI_BURST_SIZE_H (73),
.PKT_ORI_BURST_SIZE_L (71),
.PKT_RESPONSE_STATUS_H (70),
.PKT_RESPONSE_STATUS_L (69),
.PKT_QOS_H (58),
.PKT_QOS_L (58),
.PKT_DATA_SIDEBAND_H (56),
.PKT_DATA_SIDEBAND_L (56),
.PKT_ADDR_SIDEBAND_H (55),
.PKT_ADDR_SIDEBAND_L (55),
.PKT_BURST_TYPE_H (54),
.PKT_BURST_TYPE_L (53),
.PKT_CACHE_H (68),
.PKT_CACHE_L (65),
.PKT_THREAD_ID_H (61),
.PKT_THREAD_ID_L (61),
.PKT_BURST_SIZE_H (52),
.PKT_BURST_SIZE_L (50),
.PKT_TRANS_EXCLUSIVE (45),
.PKT_TRANS_LOCK (44),
.PKT_BEGIN_BURST (57),
.PKT_PROTECTION_H (64),
.PKT_PROTECTION_L (62),
.PKT_BURSTWRAP_H (49),
.PKT_BURSTWRAP_L (49),
.PKT_BYTE_CNT_H (48),
.PKT_BYTE_CNT_L (46),
.PKT_ADDR_H (39),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (40),
.PKT_TRANS_POSTED (41),
.PKT_TRANS_WRITE (42),
.PKT_TRANS_READ (43),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (59),
.PKT_SRC_ID_L (59),
.PKT_DEST_ID_H (60),
.PKT_DEST_ID_L (60),
.ST_DATA_W (74),
.ST_CHANNEL_W (2),
.AV_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_RSP (0),
.ID (1),
.BURSTWRAP_VALUE (1),
.CACHE_VALUE (0),
.SECURE_ACCESS_BIT (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) video_in_subsystem_top_io_gpo2_streamout_agent (
.clk (System_PLL_sys_clk_clk), // clk.clk
.reset (Expansion_JP2_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.av_address (video_in_subsystem_top_io_gpo2_streamout_translator_avalon_universal_master_0_address), // av.address
.av_write (video_in_subsystem_top_io_gpo2_streamout_translator_avalon_universal_master_0_write), // .write
.av_read (video_in_subsystem_top_io_gpo2_streamout_translator_avalon_universal_master_0_read), // .read
.av_writedata (video_in_subsystem_top_io_gpo2_streamout_translator_avalon_universal_master_0_writedata), // .writedata
.av_readdata (video_in_subsystem_top_io_gpo2_streamout_translator_avalon_universal_master_0_readdata), // .readdata
.av_waitrequest (video_in_subsystem_top_io_gpo2_streamout_translator_avalon_universal_master_0_waitrequest), // .waitrequest
.av_readdatavalid (video_in_subsystem_top_io_gpo2_streamout_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
.av_byteenable (video_in_subsystem_top_io_gpo2_streamout_translator_avalon_universal_master_0_byteenable), // .byteenable
.av_burstcount (video_in_subsystem_top_io_gpo2_streamout_translator_avalon_universal_master_0_burstcount), // .burstcount
.av_debugaccess (video_in_subsystem_top_io_gpo2_streamout_translator_avalon_universal_master_0_debugaccess), // .debugaccess
.av_lock (video_in_subsystem_top_io_gpo2_streamout_translator_avalon_universal_master_0_lock), // .lock
.cp_valid (video_in_subsystem_top_io_gpo2_streamout_agent_cp_valid), // cp.valid
.cp_data (video_in_subsystem_top_io_gpo2_streamout_agent_cp_data), // .data
.cp_startofpacket (video_in_subsystem_top_io_gpo2_streamout_agent_cp_startofpacket), // .startofpacket
.cp_endofpacket (video_in_subsystem_top_io_gpo2_streamout_agent_cp_endofpacket), // .endofpacket
.cp_ready (video_in_subsystem_top_io_gpo2_streamout_agent_cp_ready), // .ready
.rp_valid (rsp_mux_001_src_valid), // rp.valid
.rp_data (rsp_mux_001_src_data), // .data
.rp_channel (rsp_mux_001_src_channel), // .channel
.rp_startofpacket (rsp_mux_001_src_startofpacket), // .startofpacket
.rp_endofpacket (rsp_mux_001_src_endofpacket), // .endofpacket
.rp_ready (rsp_mux_001_src_ready), // .ready
.av_response (), // (terminated)
.av_writeresponsevalid () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_ORI_BURST_SIZE_H (73),
.PKT_ORI_BURST_SIZE_L (71),
.PKT_RESPONSE_STATUS_H (70),
.PKT_RESPONSE_STATUS_L (69),
.PKT_BURST_SIZE_H (52),
.PKT_BURST_SIZE_L (50),
.PKT_TRANS_LOCK (44),
.PKT_BEGIN_BURST (57),
.PKT_PROTECTION_H (64),
.PKT_PROTECTION_L (62),
.PKT_BURSTWRAP_H (49),
.PKT_BURSTWRAP_L (49),
.PKT_BYTE_CNT_H (48),
.PKT_BYTE_CNT_L (46),
.PKT_ADDR_H (39),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (40),
.PKT_TRANS_POSTED (41),
.PKT_TRANS_WRITE (42),
.PKT_TRANS_READ (43),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (59),
.PKT_SRC_ID_L (59),
.PKT_DEST_ID_H (60),
.PKT_DEST_ID_L (60),
.PKT_SYMBOL_W (8),
.ST_CHANNEL_W (2),
.ST_DATA_W (74),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.ECC_ENABLE (0)
) expansion_jp2_s1_agent (
.clk (System_PLL_sys_clk_clk), // clk.clk
.reset (Expansion_JP2_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (expansion_jp2_s1_agent_m0_address), // m0.address
.m0_burstcount (expansion_jp2_s1_agent_m0_burstcount), // .burstcount
.m0_byteenable (expansion_jp2_s1_agent_m0_byteenable), // .byteenable
.m0_debugaccess (expansion_jp2_s1_agent_m0_debugaccess), // .debugaccess
.m0_lock (expansion_jp2_s1_agent_m0_lock), // .lock
.m0_readdata (expansion_jp2_s1_agent_m0_readdata), // .readdata
.m0_readdatavalid (expansion_jp2_s1_agent_m0_readdatavalid), // .readdatavalid
.m0_read (expansion_jp2_s1_agent_m0_read), // .read
.m0_waitrequest (expansion_jp2_s1_agent_m0_waitrequest), // .waitrequest
.m0_writedata (expansion_jp2_s1_agent_m0_writedata), // .writedata
.m0_write (expansion_jp2_s1_agent_m0_write), // .write
.rp_endofpacket (expansion_jp2_s1_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (expansion_jp2_s1_agent_rp_ready), // .ready
.rp_valid (expansion_jp2_s1_agent_rp_valid), // .valid
.rp_data (expansion_jp2_s1_agent_rp_data), // .data
.rp_startofpacket (expansion_jp2_s1_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_mux_src_ready), // cp.ready
.cp_valid (cmd_mux_src_valid), // .valid
.cp_data (cmd_mux_src_data), // .data
.cp_startofpacket (cmd_mux_src_startofpacket), // .startofpacket
.cp_endofpacket (cmd_mux_src_endofpacket), // .endofpacket
.cp_channel (cmd_mux_src_channel), // .channel
.rf_sink_ready (expansion_jp2_s1_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (expansion_jp2_s1_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (expansion_jp2_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (expansion_jp2_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (expansion_jp2_s1_agent_rsp_fifo_out_data), // .data
.rf_source_ready (expansion_jp2_s1_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (expansion_jp2_s1_agent_rf_source_valid), // .valid
.rf_source_startofpacket (expansion_jp2_s1_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (expansion_jp2_s1_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (expansion_jp2_s1_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (avalon_st_adapter_out_0_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (avalon_st_adapter_out_0_valid), // .valid
.rdata_fifo_sink_data (avalon_st_adapter_out_0_data), // .data
.rdata_fifo_sink_error (avalon_st_adapter_out_0_error), // .error
.rdata_fifo_src_ready (expansion_jp2_s1_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (expansion_jp2_s1_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (expansion_jp2_s1_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (75),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) expansion_jp2_s1_agent_rsp_fifo (
.clk (System_PLL_sys_clk_clk), // clk.clk
.reset (Expansion_JP2_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (expansion_jp2_s1_agent_rf_source_data), // in.data
.in_valid (expansion_jp2_s1_agent_rf_source_valid), // .valid
.in_ready (expansion_jp2_s1_agent_rf_source_ready), // .ready
.in_startofpacket (expansion_jp2_s1_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (expansion_jp2_s1_agent_rf_source_endofpacket), // .endofpacket
.out_data (expansion_jp2_s1_agent_rsp_fifo_out_data), // out.data
.out_valid (expansion_jp2_s1_agent_rsp_fifo_out_valid), // .valid
.out_ready (expansion_jp2_s1_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (expansion_jp2_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (expansion_jp2_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
Computer_System_mm_interconnect_4_router router (
.sink_ready (video_in_subsystem_top_io_gpi2_streamin_agent_cp_ready), // sink.ready
.sink_valid (video_in_subsystem_top_io_gpi2_streamin_agent_cp_valid), // .valid
.sink_data (video_in_subsystem_top_io_gpi2_streamin_agent_cp_data), // .data
.sink_startofpacket (video_in_subsystem_top_io_gpi2_streamin_agent_cp_startofpacket), // .startofpacket
.sink_endofpacket (video_in_subsystem_top_io_gpi2_streamin_agent_cp_endofpacket), // .endofpacket
.clk (System_PLL_sys_clk_clk), // clk.clk
.reset (Expansion_JP2_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_src_ready), // src.ready
.src_valid (router_src_valid), // .valid
.src_data (router_src_data), // .data
.src_channel (router_src_channel), // .channel
.src_startofpacket (router_src_startofpacket), // .startofpacket
.src_endofpacket (router_src_endofpacket) // .endofpacket
);
Computer_System_mm_interconnect_4_router router_001 (
.sink_ready (video_in_subsystem_top_io_gpo2_streamout_agent_cp_ready), // sink.ready
.sink_valid (video_in_subsystem_top_io_gpo2_streamout_agent_cp_valid), // .valid
.sink_data (video_in_subsystem_top_io_gpo2_streamout_agent_cp_data), // .data
.sink_startofpacket (video_in_subsystem_top_io_gpo2_streamout_agent_cp_startofpacket), // .startofpacket
.sink_endofpacket (video_in_subsystem_top_io_gpo2_streamout_agent_cp_endofpacket), // .endofpacket
.clk (System_PLL_sys_clk_clk), // clk.clk
.reset (Expansion_JP2_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_001_src_ready), // src.ready
.src_valid (router_001_src_valid), // .valid
.src_data (router_001_src_data), // .data
.src_channel (router_001_src_channel), // .channel
.src_startofpacket (router_001_src_startofpacket), // .startofpacket
.src_endofpacket (router_001_src_endofpacket) // .endofpacket
);
Computer_System_mm_interconnect_4_router_002 router_002 (
.sink_ready (expansion_jp2_s1_agent_rp_ready), // sink.ready
.sink_valid (expansion_jp2_s1_agent_rp_valid), // .valid
.sink_data (expansion_jp2_s1_agent_rp_data), // .data
.sink_startofpacket (expansion_jp2_s1_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (expansion_jp2_s1_agent_rp_endofpacket), // .endofpacket
.clk (System_PLL_sys_clk_clk), // clk.clk
.reset (Expansion_JP2_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_002_src_ready), // src.ready
.src_valid (router_002_src_valid), // .valid
.src_data (router_002_src_data), // .data
.src_channel (router_002_src_channel), // .channel
.src_startofpacket (router_002_src_startofpacket), // .startofpacket
.src_endofpacket (router_002_src_endofpacket) // .endofpacket
);
Computer_System_mm_interconnect_4_cmd_demux cmd_demux (
.clk (System_PLL_sys_clk_clk), // clk.clk
.reset (Expansion_JP2_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_src_ready), // sink.ready
.sink_channel (router_src_channel), // .channel
.sink_data (router_src_data), // .data
.sink_startofpacket (router_src_startofpacket), // .startofpacket
.sink_endofpacket (router_src_endofpacket), // .endofpacket
.sink_valid (router_src_valid), // .valid
.src0_ready (cmd_demux_src0_ready), // src0.ready
.src0_valid (cmd_demux_src0_valid), // .valid
.src0_data (cmd_demux_src0_data), // .data
.src0_channel (cmd_demux_src0_channel), // .channel
.src0_startofpacket (cmd_demux_src0_startofpacket), // .startofpacket
.src0_endofpacket (cmd_demux_src0_endofpacket) // .endofpacket
);
Computer_System_mm_interconnect_4_cmd_demux cmd_demux_001 (
.clk (System_PLL_sys_clk_clk), // clk.clk
.reset (Expansion_JP2_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_001_src_ready), // sink.ready
.sink_channel (router_001_src_channel), // .channel
.sink_data (router_001_src_data), // .data
.sink_startofpacket (router_001_src_startofpacket), // .startofpacket
.sink_endofpacket (router_001_src_endofpacket), // .endofpacket
.sink_valid (router_001_src_valid), // .valid
.src0_ready (cmd_demux_001_src0_ready), // src0.ready
.src0_valid (cmd_demux_001_src0_valid), // .valid
.src0_data (cmd_demux_001_src0_data), // .data
.src0_channel (cmd_demux_001_src0_channel), // .channel
.src0_startofpacket (cmd_demux_001_src0_startofpacket), // .startofpacket
.src0_endofpacket (cmd_demux_001_src0_endofpacket) // .endofpacket
);
Computer_System_mm_interconnect_4_cmd_mux cmd_mux (
.clk (System_PLL_sys_clk_clk), // clk.clk
.reset (Expansion_JP2_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_src_ready), // src.ready
.src_valid (cmd_mux_src_valid), // .valid
.src_data (cmd_mux_src_data), // .data
.src_channel (cmd_mux_src_channel), // .channel
.src_startofpacket (cmd_mux_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_src0_ready), // sink0.ready
.sink0_valid (cmd_demux_src0_valid), // .valid
.sink0_channel (cmd_demux_src0_channel), // .channel
.sink0_data (cmd_demux_src0_data), // .data
.sink0_startofpacket (cmd_demux_src0_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_src0_endofpacket), // .endofpacket
.sink1_ready (cmd_demux_001_src0_ready), // sink1.ready
.sink1_valid (cmd_demux_001_src0_valid), // .valid
.sink1_channel (cmd_demux_001_src0_channel), // .channel
.sink1_data (cmd_demux_001_src0_data), // .data
.sink1_startofpacket (cmd_demux_001_src0_startofpacket), // .startofpacket
.sink1_endofpacket (cmd_demux_001_src0_endofpacket) // .endofpacket
);
Computer_System_mm_interconnect_4_rsp_demux rsp_demux (
.clk (System_PLL_sys_clk_clk), // clk.clk
.reset (Expansion_JP2_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_002_src_ready), // sink.ready
.sink_channel (router_002_src_channel), // .channel
.sink_data (router_002_src_data), // .data
.sink_startofpacket (router_002_src_startofpacket), // .startofpacket
.sink_endofpacket (router_002_src_endofpacket), // .endofpacket
.sink_valid (router_002_src_valid), // .valid
.src0_ready (rsp_demux_src0_ready), // src0.ready
.src0_valid (rsp_demux_src0_valid), // .valid
.src0_data (rsp_demux_src0_data), // .data
.src0_channel (rsp_demux_src0_channel), // .channel
.src0_startofpacket (rsp_demux_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_src0_endofpacket), // .endofpacket
.src1_ready (rsp_demux_src1_ready), // src1.ready
.src1_valid (rsp_demux_src1_valid), // .valid
.src1_data (rsp_demux_src1_data), // .data
.src1_channel (rsp_demux_src1_channel), // .channel
.src1_startofpacket (rsp_demux_src1_startofpacket), // .startofpacket
.src1_endofpacket (rsp_demux_src1_endofpacket) // .endofpacket
);
Computer_System_mm_interconnect_4_rsp_mux rsp_mux (
.clk (System_PLL_sys_clk_clk), // clk.clk
.reset (Expansion_JP2_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (rsp_mux_src_ready), // src.ready
.src_valid (rsp_mux_src_valid), // .valid
.src_data (rsp_mux_src_data), // .data
.src_channel (rsp_mux_src_channel), // .channel
.src_startofpacket (rsp_mux_src_startofpacket), // .startofpacket
.src_endofpacket (rsp_mux_src_endofpacket), // .endofpacket
.sink0_ready (rsp_demux_src0_ready), // sink0.ready
.sink0_valid (rsp_demux_src0_valid), // .valid
.sink0_channel (rsp_demux_src0_channel), // .channel
.sink0_data (rsp_demux_src0_data), // .data
.sink0_startofpacket (rsp_demux_src0_startofpacket), // .startofpacket
.sink0_endofpacket (rsp_demux_src0_endofpacket) // .endofpacket
);
Computer_System_mm_interconnect_4_rsp_mux rsp_mux_001 (
.clk (System_PLL_sys_clk_clk), // clk.clk
.reset (Expansion_JP2_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (rsp_mux_001_src_ready), // src.ready
.src_valid (rsp_mux_001_src_valid), // .valid
.src_data (rsp_mux_001_src_data), // .data
.src_channel (rsp_mux_001_src_channel), // .channel
.src_startofpacket (rsp_mux_001_src_startofpacket), // .startofpacket
.src_endofpacket (rsp_mux_001_src_endofpacket), // .endofpacket
.sink0_ready (rsp_demux_src1_ready), // sink0.ready
.sink0_valid (rsp_demux_src1_valid), // .valid
.sink0_channel (rsp_demux_src1_channel), // .channel
.sink0_data (rsp_demux_src1_data), // .data
.sink0_startofpacket (rsp_demux_src1_startofpacket), // .startofpacket
.sink0_endofpacket (rsp_demux_src1_endofpacket) // .endofpacket
);
Computer_System_mm_interconnect_0_avalon_st_adapter #(
.inBitsPerSymbol (34),
.inUsePackets (0),
.inDataWidth (34),
.inChannelWidth (0),
.inErrorWidth (0),
.inUseEmptyPort (0),
.inUseValid (1),
.inUseReady (1),
.inReadyLatency (0),
.outDataWidth (34),
.outChannelWidth (0),
.outErrorWidth (1),
.outUseEmptyPort (0),
.outUseValid (1),
.outUseReady (1),
.outReadyLatency (0)
) avalon_st_adapter (
.in_clk_0_clk (System_PLL_sys_clk_clk), // in_clk_0.clk
.in_rst_0_reset (Expansion_JP2_reset_reset_bridge_in_reset_reset), // in_rst_0.reset
.in_0_data (expansion_jp2_s1_agent_rdata_fifo_src_data), // in_0.data
.in_0_valid (expansion_jp2_s1_agent_rdata_fifo_src_valid), // .valid
.in_0_ready (expansion_jp2_s1_agent_rdata_fifo_src_ready), // .ready
.out_0_data (avalon_st_adapter_out_0_data), // out_0.data
.out_0_valid (avalon_st_adapter_out_0_valid), // .valid
.out_0_ready (avalon_st_adapter_out_0_ready), // .ready
.out_0_error (avalon_st_adapter_out_0_error) // .error
);
endmodule
|
module sky130_fd_sc_hdll__inputiso0n (
X ,
A ,
SLEEP_B
);
// Module ports
output X ;
input A ;
input SLEEP_B;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Name Output Other arguments
and and0 (X , A, SLEEP_B );
endmodule
|
module sky130_fd_sc_hd__edfxtp (
Q ,
CLK ,
D ,
DE ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Q ;
input CLK ;
input D ;
input DE ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire buf_Q ;
reg notifier ;
wire D_delayed ;
wire DE_delayed ;
wire CLK_delayed;
wire mux_out ;
wire awake ;
wire cond0 ;
// Name Output Other arguments
sky130_fd_sc_hd__udp_mux_2to1 mux_2to10 (mux_out, buf_Q, D_delayed, DE_delayed );
sky130_fd_sc_hd__udp_dff$P_pp$PG$N dff0 (buf_Q , mux_out, CLK_delayed, notifier, VPWR, VGND);
assign awake = ( VPWR === 1'b1 );
assign cond0 = ( awake && ( DE_delayed === 1'b1 ) );
buf buf0 (Q , buf_Q );
endmodule
|
module Tx8b10b #(
parameter FILL_WORD_RD0 = 10'b0011111010, // Send when no data present & RD=-1
parameter FILL_WORD_RD1 = 10'b1100000101, // Send when no data present & RD=1
parameter FILL_WORD_FLIP = 1'b1, // Flip status of Running Disparity when using fill word
parameter LOG2_DEPTH = 4 // log2(depth of FIFO buffer). Must be an integer.
)
(
input clk, // System clock
input rst, // Reset, synchronous and active high
input en, // Enable strobe for transmitting
input [7:0] dataIn, // Data to transmit
input writeStrobe, // Write data to transmit FIFO
output dataPresent, // FIFO has data still in it
output halfFull, // FIFO halfway full
output full, // FIFO is completely full. Don't write to it.
output tx // Transmit bit
);
wire [7:0] dataToEncode;
reg [3:0] outCounter;
reg [1:9] shiftOut;
reg readStrobe;
reg runDisparity6b; // 1=RD is +1, 0=RD is -1
reg runDisparity4b; // 1=RD is +1, 0=RD is -1
reg useAlt;
reg dataPresentLatch;
reg busy; // Only used when no FIFO is present
if (LOG2_DEPTH > 0) begin
Fifo #(
.WIDTH(8), ///< Width of data word
.LOG2_DEPTH(LOG2_DEPTH) ///< log2(depth of FIFO). Must be an integer
)
txFifo
(
// Inputs
.clk(clk), ///< System clock
.rst(rst), ///< Reset FIFO pointer
.write(writeStrobe), ///< Write strobe (1 clk)
.read(readStrobe), ///< Read strobe (1 clk)
.dataIn(dataIn), ///< [WIDTH-1:0] Data to write
// Outputs
.dataOut(dataToEncode), ///< [WIDTH-1:0] Data from FIFO
.dataPresent(dataPresent), ///< Data is present in FIFO
.halfFull(halfFull), ///< FIFO is half full
.full(full) ///< FIFO is full
);
end
else begin
assign dataToEncode = dataIn;
always @(posedge clk) begin
if (rst) begin
busy <= 1'b0;
end
else begin
busy <= busy ? (~readStrobe & busy) : writeStrobe;
end
end
end
assign tx = shiftOut[1];
initial begin
busy = 1'b0;
runDisparity6b = 1'b0;
runDisparity4b = 1'b0;
outCounter = 'd0;
shiftOut = 'd0;
useAlt = 1'b0;
dataPresentLatch = 1'b0;
end
always @(posedge clk) begin
if (rst) begin
runDisparity6b <= 1'b0;
runDisparity4b <= 1'b0;
outCounter <= 'd0;
shiftOut <= 'd0;
useAlt <= 1'b0;
dataPresentLatch <= 1'b0;
end
else if (en) begin
if (outCounter == 'd0) begin
readStrobe <= 1'b0;
outCounter <= 'd9;
shiftOut[7:9] <= {shiftOut[8:9], 1'b0};
// 5b/6b Encoder
useAlt <= 1'b0;
dataPresentLatch <= dataPresent;
if (dataPresent) begin
case ({dataToEncode[4:0], runDisparity6b})
6'b000000 : begin shiftOut[1:6] <= 6'b100111; runDisparity4b <= 1'b1; end
6'b000001 : begin shiftOut[1:6] <= 6'b011000; runDisparity4b <= 1'b0; end
6'b000010 : begin shiftOut[1:6] <= 6'b011101; runDisparity4b <= 1'b1; end
6'b000011 : begin shiftOut[1:6] <= 6'b100010; runDisparity4b <= 1'b0; end
6'b000100 : begin shiftOut[1:6] <= 6'b101101; runDisparity4b <= 1'b1; end
6'b000101 : begin shiftOut[1:6] <= 6'b010010; runDisparity4b <= 1'b0; end
6'b000110 : begin shiftOut[1:6] <= 6'b110001; runDisparity4b <= 1'b0; end
6'b000111 : begin shiftOut[1:6] <= 6'b110001; runDisparity4b <= 1'b1; end
6'b001000 : begin shiftOut[1:6] <= 6'b110101; runDisparity4b <= 1'b1; end
6'b001001 : begin shiftOut[1:6] <= 6'b001010; runDisparity4b <= 1'b0; end
6'b001010 : begin shiftOut[1:6] <= 6'b101001; runDisparity4b <= 1'b0; end
6'b001011 : begin shiftOut[1:6] <= 6'b101001; runDisparity4b <= 1'b1; end
6'b001100 : begin shiftOut[1:6] <= 6'b011001; runDisparity4b <= 1'b0; end
6'b001101 : begin shiftOut[1:6] <= 6'b011001; runDisparity4b <= 1'b1; end
6'b001110 : begin shiftOut[1:6] <= 6'b111000; runDisparity4b <= 1'b0; end
6'b001111 : begin shiftOut[1:6] <= 6'b000111; runDisparity4b <= 1'b1; end
6'b010000 : begin shiftOut[1:6] <= 6'b111001; runDisparity4b <= 1'b1; end
6'b010001 : begin shiftOut[1:6] <= 6'b000110; runDisparity4b <= 1'b0; end
6'b010010 : begin shiftOut[1:6] <= 6'b100101; runDisparity4b <= 1'b0; end
6'b010011 : begin shiftOut[1:6] <= 6'b100101; runDisparity4b <= 1'b1; end
6'b010100 : begin shiftOut[1:6] <= 6'b010101; runDisparity4b <= 1'b0; end
6'b010101 : begin shiftOut[1:6] <= 6'b010101; runDisparity4b <= 1'b1; end
6'b010110 : begin shiftOut[1:6] <= 6'b110100; runDisparity4b <= 1'b0; end
6'b010111 : begin shiftOut[1:6] <= 6'b110100; runDisparity4b <= 1'b1; useAlt <= 1'b1; end
6'b011000 : begin shiftOut[1:6] <= 6'b001101; runDisparity4b <= 1'b0; end
6'b011001 : begin shiftOut[1:6] <= 6'b001101; runDisparity4b <= 1'b1; end
6'b011010 : begin shiftOut[1:6] <= 6'b101100; runDisparity4b <= 1'b0; end
6'b011011 : begin shiftOut[1:6] <= 6'b101100; runDisparity4b <= 1'b1; useAlt <= 1'b1; end
6'b011100 : begin shiftOut[1:6] <= 6'b011100; runDisparity4b <= 1'b0; end
6'b011101 : begin shiftOut[1:6] <= 6'b011100; runDisparity4b <= 1'b1; useAlt <= 1'b1; end
6'b011110 : begin shiftOut[1:6] <= 6'b010111; runDisparity4b <= 1'b1; end
6'b011111 : begin shiftOut[1:6] <= 6'b101000; runDisparity4b <= 1'b0; end
6'b100000 : begin shiftOut[1:6] <= 6'b011011; runDisparity4b <= 1'b1; end
6'b100001 : begin shiftOut[1:6] <= 6'b100100; runDisparity4b <= 1'b0; end
6'b100010 : begin shiftOut[1:6] <= 6'b100011; runDisparity4b <= 1'b0; useAlt <= 1'b1; end
6'b100011 : begin shiftOut[1:6] <= 6'b100011; runDisparity4b <= 1'b1; end
6'b100100 : begin shiftOut[1:6] <= 6'b010011; runDisparity4b <= 1'b0; useAlt <= 1'b1; end
6'b100101 : begin shiftOut[1:6] <= 6'b010011; runDisparity4b <= 1'b1; end
6'b100110 : begin shiftOut[1:6] <= 6'b110010; runDisparity4b <= 1'b0; end
6'b100111 : begin shiftOut[1:6] <= 6'b110010; runDisparity4b <= 1'b1; end
6'b101000 : begin shiftOut[1:6] <= 6'b001011; runDisparity4b <= 1'b0; useAlt <= 1'b1; end
6'b101001 : begin shiftOut[1:6] <= 6'b001011; runDisparity4b <= 1'b1; end
6'b101010 : begin shiftOut[1:6] <= 6'b101010; runDisparity4b <= 1'b0; end
6'b101011 : begin shiftOut[1:6] <= 6'b101010; runDisparity4b <= 1'b1; end
6'b101100 : begin shiftOut[1:6] <= 6'b011010; runDisparity4b <= 1'b0; end
6'b101101 : begin shiftOut[1:6] <= 6'b011010; runDisparity4b <= 1'b1; end
6'b101110 : begin shiftOut[1:6] <= 6'b111010; runDisparity4b <= 1'b1; end
6'b101111 : begin shiftOut[1:6] <= 6'b000101; runDisparity4b <= 1'b0; end
6'b110000 : begin shiftOut[1:6] <= 6'b110011; runDisparity4b <= 1'b1; end
6'b110001 : begin shiftOut[1:6] <= 6'b001100; runDisparity4b <= 1'b0; end
6'b110010 : begin shiftOut[1:6] <= 6'b100110; runDisparity4b <= 1'b0; end
6'b110011 : begin shiftOut[1:6] <= 6'b100110; runDisparity4b <= 1'b1; end
6'b110100 : begin shiftOut[1:6] <= 6'b010110; runDisparity4b <= 1'b0; end
6'b110101 : begin shiftOut[1:6] <= 6'b010110; runDisparity4b <= 1'b1; end
6'b110110 : begin shiftOut[1:6] <= 6'b110110; runDisparity4b <= 1'b1; end
6'b110111 : begin shiftOut[1:6] <= 6'b001001; runDisparity4b <= 1'b0; end
6'b111000 : begin shiftOut[1:6] <= 6'b001110; runDisparity4b <= 1'b0; end
6'b111001 : begin shiftOut[1:6] <= 6'b001110; runDisparity4b <= 1'b1; end
6'b111010 : begin shiftOut[1:6] <= 6'b101110; runDisparity4b <= 1'b1; end
6'b111011 : begin shiftOut[1:6] <= 6'b010001; runDisparity4b <= 1'b0; end
6'b111100 : begin shiftOut[1:6] <= 6'b011110; runDisparity4b <= 1'b1; end
6'b111101 : begin shiftOut[1:6] <= 6'b100001; runDisparity4b <= 1'b0; end
6'b111110 : begin shiftOut[1:6] <= 6'b101011; runDisparity4b <= 1'b1; end
6'b111111 : begin shiftOut[1:6] <= 6'b010100; runDisparity4b <= 1'b0; end
endcase
end
else begin
shiftOut[1:6] <= (runDisparity4b) ? FILL_WORD_RD1[9:4] : FILL_WORD_RD0[9:4];
runDisparity6b <= runDisparity4b;
end
end
else if (outCounter == 'd9) begin
outCounter <= outCounter - 2'd1;
shiftOut[1:5] <= shiftOut[2:6];
// 3b/4b Encoder
if (dataPresentLatch) begin
readStrobe <= 1'b1;
case ({dataToEncode[7:5], runDisparity4b})
4'b0000 : begin shiftOut[6:9] <= 4'b1011; runDisparity6b <= 1'b1; end
4'b0001 : begin shiftOut[6:9] <= 4'b0100; runDisparity6b <= 1'b0; end
4'b0010 : begin shiftOut[6:9] <= 4'b1001; runDisparity6b <= 1'b0; end
4'b0011 : begin shiftOut[6:9] <= 4'b1001; runDisparity6b <= 1'b1; end
4'b0100 : begin shiftOut[6:9] <= 4'b0101; runDisparity6b <= 1'b0; end
4'b0101 : begin shiftOut[6:9] <= 4'b0101; runDisparity6b <= 1'b1; end
4'b0110 : begin shiftOut[6:9] <= 4'b1100; runDisparity6b <= 1'b0; end
4'b0111 : begin shiftOut[6:9] <= 4'b0011; runDisparity6b <= 1'b1; end
4'b1000 : begin shiftOut[6:9] <= 4'b1101; runDisparity6b <= 1'b1; end
4'b1001 : begin shiftOut[6:9] <= 4'b0010; runDisparity6b <= 1'b0; end
4'b1010 : begin shiftOut[6:9] <= 4'b1010; runDisparity6b <= 1'b0; end
4'b1011 : begin shiftOut[6:9] <= 4'b1010; runDisparity6b <= 1'b1; end
4'b1100 : begin shiftOut[6:9] <= 4'b0110; runDisparity6b <= 1'b0; end
4'b1101 : begin shiftOut[6:9] <= 4'b0110; runDisparity6b <= 1'b1; end
4'b1110 : begin shiftOut[6:9] <= (useAlt) ? 4'b0111 : 4'b1110; runDisparity6b <= 1'b1; end
4'b1111 : begin shiftOut[6:9] <= (useAlt) ? 4'b1000 : 4'b0001; runDisparity6b <= 1'b0; end
endcase
end
else begin
readStrobe <= 1'b0;
shiftOut[6:9] <= (runDisparity4b) ? FILL_WORD_RD1[3:0] : FILL_WORD_RD0[3:0];
runDisparity4b <= FILL_WORD_FLIP ^ runDisparity6b;
end
end
else begin
readStrobe <= 1'b0;
outCounter <= outCounter - 2'd1;
shiftOut <= {shiftOut[2:9], 1'b0};
end
end
else begin
readStrobe <= 1'b0;
end
end
endmodule
|
module incrementCounter (pcprev, newpc); //increments value from PC counter to next instruction
input [31:0] pcprev; //setting up inputs and outputs
reg [31:0] newpcreg;
output [31:0] newpc;
always@ (pcprev) begin //whenever pcprev changes, do the following
assign newpcreg = pcprev + 1; //add 1 to pcprev and assign that value as the output, as memory is an array of 32 bit elements
end
assign newpc = newpcreg; //assigning actual output
endmodule
|
module ProgramCounter(clk, in, out, rst); //keeps track of the current address in I-mem
input clk; //clock as input
input rst; //reset value
input [31:0] in; //in as input
output [31:0] out; //out as output
reg signed [31:0] out;//out register
always @(posedge clk)//run when at clock positive edge
out = rst ? 32'b00000000000000000000000000000000 : in ; // reset state
endmodule
|
module InstrMemory(addr, out);
input [31:0] addr;
output [31:0] out;
reg [31:0] out;
reg[31:0] mem [0:1000]; //hard coded to 1000 elements, just for simplicity's sake
initial $readmemb("prog2.bin",mem); //reading in memory
always @(*) //output the memory at the desired address
out = mem[addr];
endmodule
|
module sky130_fd_sc_lp__nand4_m (
Y ,
A ,
B ,
C ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input B ;
input C ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__nand4 base (
.Y(Y),
.A(A),
.B(B),
.C(C),
.D(D),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
|
module sky130_fd_sc_lp__nand4_m (
Y,
A,
B,
C,
D
);
output Y;
input A;
input B;
input C;
input D;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__nand4 base (
.Y(Y),
.A(A),
.B(B),
.C(C),
.D(D)
);
endmodule
|
module test;
reg[`WIDTH-1:0] data;
reg[`SHIFT_WIDTH-1:0] shift;
reg[`OPS-1:0] op;
wire[`WIDTH-1:0] result;
reg[`WIDTH-1:0] corr_result;
reg[`WIDTH-1:0] test_vals[0:`TESTS-1];
reg[`SHIFT_WIDTH-1:0] test_shifts[0:`TESTS-1];
reg start;
reg[`WIDTH-1:0] tests;
initial begin
$dumpfile("dump.vcd");
$dumpvars;
data = $random;
op = 2'b00;
for (tests = 0; tests < `TESTS; ++tests) begin
test_vals[tests] = $random;//32'b10000000000000000000000000000000;
test_shifts[tests] = $random % 32;
end
data = 0;
shift = test_shifts[0];
tests = 0;
start = 1'b0;
end
reg clk_reg = 1'b0;
wire clk;
assign clk = clk_reg;
always #5 clk_reg <= ~clk_reg;
shifter uut(data, shift, op, start, result);
always @(negedge clk) begin
#2 start <= 1'b0;
if (corr_result != result)
$display("Invalid result : expected - %d, got - %d", corr_result, result);
end
always @(posedge clk) begin
tests <= tests + 1;
data <= test_vals[tests];
shift <= test_shifts[tests];
start <= 1'b1;
case (op)
`LEFT_SHIFTA: corr_result <= $signed(test_vals[tests]) <<< test_shifts[tests];
`LEFT_SHIFTL: corr_result <= test_vals[tests] << test_shifts[tests];
`RIGHT_SHIFTA: corr_result <= $signed(test_vals[tests]) >>> test_shifts[tests];
`RIGHT_SHIFTL: corr_result <= test_vals[tests] >> test_shifts[tests];
default: $display("Invalid op");
endcase
if (tests >= `TESTS-1)
#20 $finish;
end
endmodule
|
module test_axis_frame_fifo;
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg [7:0] input_axis_tdata = 0;
reg input_axis_tvalid = 0;
reg input_axis_tlast = 0;
reg input_axis_tuser = 0;
reg output_axis_tready = 0;
// Outputs
wire input_axis_tready;
wire [7:0] output_axis_tdata;
wire output_axis_tvalid;
wire output_axis_tlast;
initial begin
// myhdl integration
$from_myhdl(clk,
rst,
current_test,
input_axis_tdata,
input_axis_tvalid,
input_axis_tlast,
input_axis_tuser,
output_axis_tready);
$to_myhdl(input_axis_tready,
output_axis_tdata,
output_axis_tvalid,
output_axis_tlast);
// dump file
$dumpfile("test_axis_frame_fifo.lxt");
$dumpvars(0, test_axis_frame_fifo);
end
axis_frame_fifo #(
.ADDR_WIDTH(9),
.DATA_WIDTH(8),
.DROP_WHEN_FULL(0)
)
UUT (
.clk(clk),
.rst(rst),
// AXI input
.input_axis_tdata(input_axis_tdata),
.input_axis_tvalid(input_axis_tvalid),
.input_axis_tready(input_axis_tready),
.input_axis_tlast(input_axis_tlast),
.input_axis_tuser(input_axis_tuser),
// AXI output
.output_axis_tdata(output_axis_tdata),
.output_axis_tvalid(output_axis_tvalid),
.output_axis_tready(output_axis_tready),
.output_axis_tlast(output_axis_tlast)
);
endmodule
|
module will assert this signal, following which dram contents will be available in the fifo
num_keys
);
localparam NUM_STATES=5;
localparam STATE_IDLE=1;
localparam STATE_START_FLUSH=2;
localparam STATE_WAIT_READ=4;
localparam STATE_READ_DATA=8;
localparam STATE_WRITE_FIFO=16;
////////////Ports///////////////////
input clk;
input reset;
//Interface for external writes//
output [63:0] dram_fifo_readdata;
input dram_fifo_read;
output dram_fifo_empty;
// Write control inputs and outputs
output wire control_fixed_location;
output reg [ADDRESS_WIDTH-1:0] control_read_base;
output wire [ADDRESS_WIDTH-1:0] control_read_length;
output reg control_go;
input wire control_done;
// Write user logic inputs and outputs
output reg user_read_buffer;
input wire [255:0] user_buffer_output_data;
input wire user_data_available;
input dram_flush;
input [31:0] num_keys;
///////////Registers/////////////////////
reg [ADDRESS_WIDTH-1:0] control_read_base_next;
reg [ADDRESS_WIDTH-1:0] control_read_length_next;
reg control_go_next;
reg user_read_buffer_next;
reg [NUM_STATES-1:0] state, state_next;
reg [31:0] counter,counter_next;
reg [63:0] dram_wr_val, dram_wr_val_next;
assign control_fixed_location=1'b0;
assign control_read_length = 32;
wire dram_fifo_full;
reg dram_fifo_write, dram_fifo_write_next;
always@(*)
begin
dram_fifo_write_next = 1'b0;
control_read_base_next = control_read_base;
control_go_next = 1'b0;
user_read_buffer_next = 1'b0;
state_next = state;
counter_next = counter;
dram_wr_val_next = dram_wr_val;
case(state)
STATE_IDLE: begin
if(dram_flush) begin //if fifo is not empty, start reading first key
counter_next = 0;
state_next = STATE_START_FLUSH;
end
end
STATE_START_FLUSH: begin
control_read_base_next = DDR_BASE+(counter<<5);
control_go_next = 1'b1;
state_next = STATE_WAIT_READ;
end
STATE_WAIT_READ: begin
if(user_data_available) begin
state_next = STATE_READ_DATA;
user_read_buffer_next = 1'b1;
end
end
STATE_READ_DATA: begin
dram_wr_val_next = {user_buffer_output_data[31:0],user_buffer_output_data[63:32]}; //write 64 bits [key and value]
counter_next = counter+1;
state_next = STATE_WRITE_FIFO;
end
STATE_WRITE_FIFO: begin
if(!dram_fifo_full) begin
dram_fifo_write_next = 1'b1;
//state_next = (counter==TOTAL_DATA)?STATE_IDLE:STATE_START_FLUSH;
state_next = (counter==num_keys)?STATE_IDLE:STATE_START_FLUSH;
end
end
endcase
end
always@(posedge clk or posedge reset)
begin
if(reset) begin
state <= STATE_IDLE;
dram_fifo_write <= 1'b0;
control_read_base <= 0;
control_go <= 0;
user_read_buffer <= 1'b0;
counter <= 0;
dram_wr_val <= 0;
end
else begin
state <= state_next;
dram_fifo_write <= dram_fifo_write_next;
control_read_base <= control_read_base_next;
control_go <= control_go_next;
user_read_buffer <= user_read_buffer_next;
counter <= counter_next;
dram_wr_val <= dram_wr_val_next;
end
end
//External accumulator FIFO (receives external updates from netfpga pipeline)
txfifo #(
.DATA_WIDTH(64),
.LOCAL_FIFO_DEPTH(32)
)fifo (
.clock (clk),
.aclr (reset),
.data (dram_wr_val), //write key and value
.rdreq (dram_fifo_read),
.wrreq (dram_fifo_write),
.q (dram_fifo_readdata),
.empty (dram_fifo_empty),
.full (dram_fifo_full),
.usedw (),
.almost_full ()
);
endmodule
|
module soc_system_cpu_s1_jtag_debug_module_sysclk (
// inputs:
clk,
ir_in,
sr,
vs_udr,
vs_uir,
// outputs:
jdo,
take_action_break_a,
take_action_break_b,
take_action_break_c,
take_action_ocimem_a,
take_action_ocimem_b,
take_action_tracectrl,
take_action_tracemem_a,
take_action_tracemem_b,
take_no_action_break_a,
take_no_action_break_b,
take_no_action_break_c,
take_no_action_ocimem_a,
take_no_action_tracemem_a
)
;
output [ 37: 0] jdo;
output take_action_break_a;
output take_action_break_b;
output take_action_break_c;
output take_action_ocimem_a;
output take_action_ocimem_b;
output take_action_tracectrl;
output take_action_tracemem_a;
output take_action_tracemem_b;
output take_no_action_break_a;
output take_no_action_break_b;
output take_no_action_break_c;
output take_no_action_ocimem_a;
output take_no_action_tracemem_a;
input clk;
input [ 1: 0] ir_in;
input [ 37: 0] sr;
input vs_udr;
input vs_uir;
reg enable_action_strobe /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */;
reg [ 1: 0] ir /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */;
reg [ 37: 0] jdo /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */;
reg jxuir /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */;
reg sync2_udr /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */;
reg sync2_uir /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */;
wire sync_udr;
wire sync_uir;
wire take_action_break_a;
wire take_action_break_b;
wire take_action_break_c;
wire take_action_ocimem_a;
wire take_action_ocimem_b;
wire take_action_tracectrl;
wire take_action_tracemem_a;
wire take_action_tracemem_b;
wire take_no_action_break_a;
wire take_no_action_break_b;
wire take_no_action_break_c;
wire take_no_action_ocimem_a;
wire take_no_action_tracemem_a;
wire unxunused_resetxx3;
wire unxunused_resetxx4;
reg update_jdo_strobe /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */;
assign unxunused_resetxx3 = 1'b1;
altera_std_synchronizer the_altera_std_synchronizer3
(
.clk (clk),
.din (vs_udr),
.dout (sync_udr),
.reset_n (unxunused_resetxx3)
);
defparam the_altera_std_synchronizer3.depth = 2;
assign unxunused_resetxx4 = 1'b1;
altera_std_synchronizer the_altera_std_synchronizer4
(
.clk (clk),
.din (vs_uir),
.dout (sync_uir),
.reset_n (unxunused_resetxx4)
);
defparam the_altera_std_synchronizer4.depth = 2;
always @(posedge clk)
begin
sync2_udr <= sync_udr;
update_jdo_strobe <= sync_udr & ~sync2_udr;
enable_action_strobe <= update_jdo_strobe;
sync2_uir <= sync_uir;
jxuir <= sync_uir & ~sync2_uir;
end
assign take_action_ocimem_a = enable_action_strobe && (ir == 2'b00) &&
~jdo[35] && jdo[34];
assign take_no_action_ocimem_a = enable_action_strobe && (ir == 2'b00) &&
~jdo[35] && ~jdo[34];
assign take_action_ocimem_b = enable_action_strobe && (ir == 2'b00) &&
jdo[35];
assign take_action_tracemem_a = enable_action_strobe && (ir == 2'b01) &&
~jdo[37] &&
jdo[36];
assign take_no_action_tracemem_a = enable_action_strobe && (ir == 2'b01) &&
~jdo[37] &&
~jdo[36];
assign take_action_tracemem_b = enable_action_strobe && (ir == 2'b01) &&
jdo[37];
assign take_action_break_a = enable_action_strobe && (ir == 2'b10) &&
~jdo[36] &&
jdo[37];
assign take_no_action_break_a = enable_action_strobe && (ir == 2'b10) &&
~jdo[36] &&
~jdo[37];
assign take_action_break_b = enable_action_strobe && (ir == 2'b10) &&
jdo[36] && ~jdo[35] &&
jdo[37];
assign take_no_action_break_b = enable_action_strobe && (ir == 2'b10) &&
jdo[36] && ~jdo[35] &&
~jdo[37];
assign take_action_break_c = enable_action_strobe && (ir == 2'b10) &&
jdo[36] && jdo[35] &&
jdo[37];
assign take_no_action_break_c = enable_action_strobe && (ir == 2'b10) &&
jdo[36] && jdo[35] &&
~jdo[37];
assign take_action_tracectrl = enable_action_strobe && (ir == 2'b11) &&
jdo[15];
always @(posedge clk)
begin
if (jxuir)
ir <= ir_in;
if (update_jdo_strobe)
jdo <= sr;
end
endmodule
|
module test_axis_srl_register;
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg [7:0] input_axis_tdata = 8'd0;
reg input_axis_tvalid = 1'b0;
reg input_axis_tlast = 1'b0;
reg input_axis_tuser = 1'b0;
reg output_axis_tready = 1'b0;
// Outputs
wire input_axis_tready;
wire [7:0] output_axis_tdata;
wire output_axis_tvalid;
wire output_axis_tlast;
wire output_axis_tuser;
initial begin
// myhdl integration
$from_myhdl(clk,
rst,
current_test,
input_axis_tdata,
input_axis_tvalid,
input_axis_tlast,
input_axis_tuser,
output_axis_tready);
$to_myhdl(input_axis_tready,
output_axis_tdata,
output_axis_tvalid,
output_axis_tlast,
output_axis_tuser);
// dump file
$dumpfile("test_axis_srl_register.lxt");
$dumpvars(0, test_axis_srl_register);
end
axis_srl_register #(
.DATA_WIDTH(8)
)
UUT (
.clk(clk),
.rst(rst),
// axi input
.input_axis_tdata(input_axis_tdata),
.input_axis_tvalid(input_axis_tvalid),
.input_axis_tready(input_axis_tready),
.input_axis_tlast(input_axis_tlast),
.input_axis_tuser(input_axis_tuser),
// axi output
.output_axis_tdata(output_axis_tdata),
.output_axis_tvalid(output_axis_tvalid),
.output_axis_tready(output_axis_tready),
.output_axis_tlast(output_axis_tlast),
.output_axis_tuser(output_axis_tuser)
);
endmodule
|
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
// verilator lint_off WIDTH
typedef enum logic[2:0] {P=0, W=1'b1, E, N, S} Dirs;
typedef enum integer {UP=0, UW=1'b1} UNSIZED;
// verilator lint_on WIDTH
localparam LEN = 3;
localparam COL = 4;
localparam [59:0] SEQ = {LEN'(N), LEN'(E), LEN'(W), LEN'(P)
,LEN'(S), LEN'(E), LEN'(W), LEN'(P)
,LEN'(S), LEN'(N), LEN'(W), LEN'(P)
,LEN'(S), LEN'(N), LEN'(E), LEN'(P)
,LEN'(S), LEN'(N), LEN'(E), LEN'(W)};
bit [59:0] SE2 = {N, E, W, P
,S, E, W, P
,S, N, W, P
,S, N, E, P
,S, N, E, W};
initial begin
if (SEQ != 60'o32104210431043204321) $stop;
if (SE2 != 60'o32104210431043204321) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
endmodule
|
module top();
// Inputs are registered
reg A;
reg B;
reg C_N;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Y;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
B = 1'bX;
C_N = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 B = 1'b0;
#60 C_N = 1'b0;
#80 VGND = 1'b0;
#100 VNB = 1'b0;
#120 VPB = 1'b0;
#140 VPWR = 1'b0;
#160 A = 1'b1;
#180 B = 1'b1;
#200 C_N = 1'b1;
#220 VGND = 1'b1;
#240 VNB = 1'b1;
#260 VPB = 1'b1;
#280 VPWR = 1'b1;
#300 A = 1'b0;
#320 B = 1'b0;
#340 C_N = 1'b0;
#360 VGND = 1'b0;
#380 VNB = 1'b0;
#400 VPB = 1'b0;
#420 VPWR = 1'b0;
#440 VPWR = 1'b1;
#460 VPB = 1'b1;
#480 VNB = 1'b1;
#500 VGND = 1'b1;
#520 C_N = 1'b1;
#540 B = 1'b1;
#560 A = 1'b1;
#580 VPWR = 1'bx;
#600 VPB = 1'bx;
#620 VNB = 1'bx;
#640 VGND = 1'bx;
#660 C_N = 1'bx;
#680 B = 1'bx;
#700 A = 1'bx;
end
sky130_fd_sc_hd__nor3b dut (.A(A), .B(B), .C_N(C_N), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Y(Y));
endmodule
|
module sky130_fd_sc_hs__nor3b (
Y ,
A ,
B ,
C_N
);
output Y ;
input A ;
input B ;
input C_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
endmodule
|
module module_decoder
(
input clk,
input reset,
input davail,
input [3:0]din,
input tbm_hdr,
input tbm_trl,
input roc_hdr,
input idle_in,
output idle_out,
output reg running,
input [7:0]xorsum,
input [1:0]error_in,
output [1:0]error_out,
output reg write,
output reg [15:0]data
);
// --- error flags -----------------------------------------------------
reg [1:0]sme; // state machine error
reg [2:0]ef; // external error flags
wire [4:0]error_flags = {ef, sme};
/*
bit 0: no TBM trailer or ROC header after TBM header
bit 1: idle pattern detected during readout
bit 2: code error
bit 3: frame error
bit 4: one of the four errors detected
*/
// --- idle detector ---------------------------------------------------
reg [2:0]idle_reg;
reg idle_data;
always @(posedge clk or posedge reset)
begin
if (reset)
begin
idle_reg <= 0;
idle_data <= 0;
end
else if (davail)
begin
idle_reg <= {idle_reg[1:0], &din};
idle_data <= &idle_reg;
end
end
assign idle_out = idle_data;
wire idle = idle_data & idle_in;
// --- data delay chain
reg [3:0]d0;
reg [3:0]d1;
reg [3:0]d2;
always @(posedge clk or posedge reset)
begin
if (reset) {d2, d1, d0} <= 12'd0;
else if (davail) {d2, d1, d0} <= {d1, d0, din};
end
// --- decoder FSM -----------------------------------------------------
localparam SM_IDLE = 6'd0;
localparam SM_H0 = 6'd1;
localparam SM_H1 = 6'd2;
localparam SM_H2 = 6'd3; // writeH
localparam SM_H3 = 6'd4;
localparam SM_H4 = 6'd5; // writeH
localparam SM_H5 = 6'd6;
localparam SM_H6 = 6'd7;
localparam SM_H7 = 6'd8;
localparam SM_H8 = 6'd9;
localparam SM_R0 = 6'd10; // writeR
localparam SM_R1 = 6'd11;
localparam SM_R2 = 6'd12;
localparam SM_R3 = 6'd13; // writeP
localparam SM_R4 = 6'd14;
localparam SM_R5 = 6'd15;
localparam SM_R6 = 6'd16; // writeP
localparam SM_T0 = 6'd20;
localparam SM_T1 = 6'd21;
localparam SM_T2 = 6'd22; // writeT
localparam SM_T3 = 6'd23;
localparam SM_T4 = 6'd24; // writeT
localparam SM_T5 = 6'd25;
localparam SM_ERR = 6'd26;
reg [5:0]sm;
always @(posedge clk or posedge reset)
begin
if (reset)
begin
sm <= SM_IDLE;
sme <= 0;
end
else
begin if (davail)
case (sm)
// --- TBM header detection
SM_IDLE: if (tbm_hdr)
begin
sme <= 2'b00; sm <= SM_H0;
end
SM_H0: sm <= SM_H1; // D0
SM_H1: sm <= SM_H2; // D1
SM_H2: sm <= SM_H3; // D2
SM_H3: sm <= SM_H4; // D3
SM_H4: sm <= SM_H5;
SM_H5: sm <= SM_H6;
// earliest possible position for TT or RH
SM_H6: if (tbm_trl) sm <= SM_T0;
else if (roc_hdr) sm <= SM_R0;
else sm <= SM_H7;
// delayed position
SM_H7: if (tbm_trl) sm <= SM_T0;
else if (roc_hdr) sm <= SM_R0;
else sm <= SM_H8;
// delayed position
SM_H8: if (tbm_trl) sm <= SM_T0;
else if (roc_hdr) sm <= SM_R0;
else
begin
sme[0] <= 1'b1; sm <= SM_ERR;
end
// --- ROC data
SM_R0: sm <= SM_R1;
SM_R1: if (tbm_trl) sm <= SM_T0;
else sm <= SM_R2;
SM_R2: if (tbm_trl) sm <= SM_T0;
else if (roc_hdr) sm <= SM_R0;
else sm <= SM_R3;
SM_R3: if (tbm_trl) sm <= SM_T0;
else if (roc_hdr) sm <= SM_R0;
else sm <= SM_R4;
SM_R4: if (tbm_trl) sm <= SM_T0;
else if (roc_hdr) sm <= SM_R0;
else sm <= SM_R5;
SM_R5: if (tbm_trl) sm <= SM_T0;
else sm <= SM_R6;
SM_R6: if (tbm_trl) sm <= SM_T0;
else if (idle)
begin
sme[1] <= 1'b1; sm <= SM_ERR;
end
else sm <= SM_R1;
SM_ERR: sm <= SM_T0; // set error flags
SM_T0: sm <= SM_T1; // D0
SM_T1: sm <= SM_T2; // D1
SM_T2: sm <= SM_T3; // D2
SM_T3: sm <= SM_T4; // D3
SM_T4: sm <= SM_T5;
default: sm <= SM_IDLE;
endcase
end
end // always
always @(posedge clk or posedge reset)
begin
if (reset) running <= 0;
else running = |sm;
end
// --- error handling --------------------------------------------------
assign error_out = error_flags[1:0];
always @(posedge clk or posedge reset)
begin
if (reset) ef <= 0;
else
begin
if (sm==SM_IDLE) ef <= 0;
else
begin
if (error_in[0]) ef[0] <= 1'b1;
if (error_in[1]) ef[1] <= 1'b1;
ef[2] <= |{ef[1:0], sme};
end
end
end
// --- data handling ---------------------------------------------------
reg [1:0]send;
reg [15:0]data2;
wire writeH = davail && (sm==SM_H2 || sm==SM_H4); // write TBM header
wire writeR = davail && sm==SM_R0; // write ROC header
wire writeP = davail && (sm==SM_R3 || sm==SM_R6); // write ROC data
wire writeT = davail && (sm==SM_T2 || sm==SM_T4); // write TBM trailer
always @(posedge clk or posedge reset)
begin
if (reset)
begin
send <= 0;
write <= 0;
data <= 16'd0;
end
else
begin
write <= writeH || writeR || writeT || (|send && davail);
case (sm)
SM_H2: data <= {4'b1010, 4'b0000, d1, d0};
SM_H4: data <= {4'b1000, 4'b0000, d1, d0};
SM_R0: data <= {4'b0100, xorsum, 2'b00, d0[1:0]};
SM_R3: data <= {4'b0000, d2, d1, d0};
SM_R6:
begin
data2 <= {4'b0010, d2, d1, d0};
if (!(tbm_trl || roc_hdr || idle_data)) send <= 2'b11;
end
SM_T2: data <= error_flags[4] ?
{3'b111, error_flags, 4'd0, 4'd0} :
{3'b111, error_flags, d1, d0};
SM_T4: data <= error_flags[4] ?
{3'b110, error_flags, 4'd0, 4'd0} :
{3'b110, error_flags, d1, d0};
default:
begin
if (tbm_trl || roc_hdr) send <= 2'b00;
else if (send[1]) begin send[1] <= 0; data <= data2; end
else if (send[0]) send[0] <= 0;
end
endcase
end
end
endmodule
|
module compare(
clk,
rstn,
cnt,
blockcnt,
bestmode,
bestmode16,
bestmode32,
modebest,
modebest16,
modebest32,
mode2,
mode3,
mode4,
mode5,
mode6,
mode7,
mode8,
mode9,
mode10,
mode11,
mode12,
mode13,
mode14,
mode15,
mode16,
mode17,
mode18,
mode19,
mode20,
mode21,
mode22,
mode23,
mode24,
mode25,
mode26,
mode27,
mode28,
mode29,
mode30,
mode31,
mode32,
mode33
);
parameter MODE=21;
parameter DIGIT=0;
input clk;
input rstn;
input [5:0] cnt;
input [6:0] blockcnt;
output [5:0] bestmode;
output [5:0] bestmode16;
output [5:0] bestmode32;
output [MODE-DIGIT:0] modebest;
output [MODE-DIGIT+2:0] modebest16;
output [MODE-DIGIT+4:0] modebest32;
input [MODE:0] mode2;
input [MODE:0] mode3;
input [MODE:0] mode4;
input [MODE:0] mode5;
input [MODE:0] mode6;
input [MODE:0] mode7;
input [MODE:0] mode8;
input [MODE:0] mode9;
input [MODE:0] mode10;
input [MODE:0] mode11;
input [MODE:0] mode12;
input [MODE:0] mode13;
input [MODE:0] mode14;
input [MODE:0] mode15;
input [MODE:0] mode16;
input [MODE:0] mode17;
input [MODE:0] mode18;
input [MODE:0] mode19;
input [MODE:0] mode20;
input [MODE:0] mode21;
input [MODE:0] mode22;
input [MODE:0] mode23;
input [MODE:0] mode24;
input [MODE:0] mode25;
input [MODE:0] mode26;
input [MODE:0] mode27;
input [MODE:0] mode28;
input [MODE:0] mode29;
input [MODE:0] mode30;
input [MODE:0] mode31;
input [MODE:0] mode32;
input [MODE:0] mode33;
//===================state============================
reg comparebegin;
reg comparebegin16;
reg comparerun16;
reg comparebegin32;
reg comparerun32;
reg comparerun32_reg;
always@(posedge clk or negedge rstn)
if(!rstn)
comparerun16 <= 1'b0;
else if((cnt == 'd5) && (blockcnt[1:0]==2'b00) && blockcnt[6:2])
comparerun16 <= 1'b1;
else if(cnt == 'd37)
comparerun16 <= 1'b0;
always@(posedge clk or negedge rstn)
if(!rstn)
comparerun32 <= 1'b0;
else if((blockcnt[3:0]=='d0)&&(cnt == 'd6) && blockcnt[6:4])
comparerun32 <= 1'b1;
else if(cnt == 'd38)
comparerun32 <= 1'b0;
always@(posedge clk or negedge rstn)
if(!rstn)
comparerun32_reg <= 1'b0;
else
comparerun32_reg <= comparerun32;
always@(posedge clk or negedge rstn)
if(!rstn)
comparebegin <= 1'b0;
else if((cnt == 'd2) && blockcnt)
comparebegin <= 1'b1;
else
comparebegin <= 1'b0;
always@(posedge clk or negedge rstn)
if(!rstn)
comparebegin16 <= 1'b0;
else
comparebegin16 <= comparebegin;
always@(posedge clk or negedge rstn)
if(!rstn)
comparebegin32 <= 1'b0;
else if(blockcnt[3:0]=='d0)
comparebegin32 <= comparebegin16;
//=======================8*8=========================
reg [5:0] bestmode;
reg [MODE-DIGIT:0] modebest;
reg [MODE-DIGIT:0] mode_reg;
reg [MODE-DIGIT:0] mode2_reg;
reg [MODE-DIGIT:0] mode3_reg;
reg [MODE-DIGIT:0] mode4_reg;
reg [MODE-DIGIT:0] mode5_reg;
reg [MODE-DIGIT:0] mode6_reg;
reg [MODE-DIGIT:0] mode7_reg;
reg [MODE-DIGIT:0] mode8_reg;
reg [MODE-DIGIT:0] mode9_reg;
reg [MODE-DIGIT:0] mode10_reg;
reg [MODE-DIGIT:0] mode11_reg;
reg [MODE-DIGIT:0] mode12_reg;
reg [MODE-DIGIT:0] mode13_reg;
reg [MODE-DIGIT:0] mode14_reg;
reg [MODE-DIGIT:0] mode15_reg;
reg [MODE-DIGIT:0] mode16_reg;
reg [MODE-DIGIT:0] mode17_reg;
reg [MODE-DIGIT:0] mode18_reg;
reg [MODE-DIGIT:0] mode19_reg;
reg [MODE-DIGIT:0] mode20_reg;
reg [MODE-DIGIT:0] mode21_reg;
reg [MODE-DIGIT:0] mode22_reg;
reg [MODE-DIGIT:0] mode23_reg;
reg [MODE-DIGIT:0] mode24_reg;
reg [MODE-DIGIT:0] mode25_reg;
reg [MODE-DIGIT:0] mode26_reg;
reg [MODE-DIGIT:0] mode27_reg;
reg [MODE-DIGIT:0] mode28_reg;
reg [MODE-DIGIT:0] mode29_reg;
reg [MODE-DIGIT:0] mode30_reg;
reg [MODE-DIGIT:0] mode31_reg;
reg [MODE-DIGIT:0] mode32_reg;
reg [MODE-DIGIT:0] mode33_reg;
always@(posedge clk or negedge rstn)
if(!rstn)
begin
mode2_reg <= 'd0;
mode3_reg <= 'd0;
mode4_reg <= 'd0;
mode5_reg <= 'd0;
mode6_reg <= 'd0;
mode7_reg <= 'd0;
mode8_reg <= 'd0;
mode9_reg <= 'd0;
mode10_reg <= 'd0;
mode11_reg <= 'd0;
mode12_reg <= 'd0;
mode13_reg <= 'd0;
mode14_reg <= 'd0;
mode15_reg <= 'd0;
mode16_reg <= 'd0;
mode17_reg <= 'd0;
mode18_reg <= 'd0;
mode19_reg <= 'd0;
mode20_reg <= 'd0;
mode21_reg <= 'd0;
mode22_reg <= 'd0;
mode23_reg <= 'd0;
mode24_reg <= 'd0;
mode25_reg <= 'd0;
mode26_reg <= 'd0;
mode27_reg <= 'd0;
mode28_reg <= 'd0;
mode29_reg <= 'd0;
mode30_reg <= 'd0;
mode31_reg <= 'd0;
mode32_reg <= 'd0;
mode33_reg <= 'd0;
end
else if(comparebegin)
begin
mode2_reg <= mode2[MODE:DIGIT];
mode3_reg <= mode3[MODE:DIGIT];
mode4_reg <= mode4[MODE:DIGIT];
mode5_reg <= mode5[MODE:DIGIT];
mode6_reg <= mode6[MODE:DIGIT];
mode7_reg <= mode7[MODE:DIGIT];
mode8_reg <= mode8[MODE:DIGIT];
mode9_reg <= mode9[MODE:DIGIT];
mode10_reg <= mode10[MODE:DIGIT];
mode11_reg <= mode11[MODE:DIGIT];
mode12_reg <= mode12[MODE:DIGIT];
mode13_reg <= mode13[MODE:DIGIT];
mode14_reg <= mode14[MODE:DIGIT];
mode15_reg <= mode15[MODE:DIGIT];
mode16_reg <= mode16[MODE:DIGIT];
mode17_reg <= mode17[MODE:DIGIT];
mode18_reg <= mode18[MODE:DIGIT];
mode19_reg <= mode19[MODE:DIGIT];
mode20_reg <= mode20[MODE:DIGIT];
mode21_reg <= mode21[MODE:DIGIT];
mode22_reg <= mode22[MODE:DIGIT];
mode23_reg <= mode23[MODE:DIGIT];
mode24_reg <= mode24[MODE:DIGIT];
mode25_reg <= mode25[MODE:DIGIT];
mode26_reg <= mode26[MODE:DIGIT];
mode27_reg <= mode27[MODE:DIGIT];
mode28_reg <= mode28[MODE:DIGIT];
mode29_reg <= mode29[MODE:DIGIT];
mode30_reg <= mode30[MODE:DIGIT];
mode31_reg <= mode31[MODE:DIGIT];
mode32_reg <= mode32[MODE:DIGIT];
mode33_reg <= mode33[MODE:DIGIT];
end
always@(posedge clk or negedge rstn)
if(!rstn)
mode_reg <= 'd0;
else
case(cnt)
'd3:mode_reg <= mode3[MODE:DIGIT];
'd4:mode_reg <= mode4_reg;
'd5:mode_reg <= mode5_reg;
'd6:mode_reg <= mode6_reg;
'd7:mode_reg <= mode7_reg;
'd8:mode_reg <= mode8_reg;
'd9:mode_reg <= mode9_reg;
'd10:mode_reg <= mode10_reg;
'd11:mode_reg <= mode11_reg;
'd12:mode_reg <= mode12_reg;
'd13:mode_reg <= mode13_reg;
'd14:mode_reg <= mode14_reg;
'd15:mode_reg <= mode15_reg;
'd16:mode_reg <= mode16_reg;
'd17:mode_reg <= mode17_reg;
'd18:mode_reg <= mode18_reg;
'd19:mode_reg <= mode19_reg;
'd20:mode_reg <= mode20_reg;
'd21:mode_reg <= mode21_reg;
'd22:mode_reg <= mode22_reg;
'd23:mode_reg <= mode23_reg;
'd24:mode_reg <= mode24_reg;
'd25:mode_reg <= mode25_reg;
'd26:mode_reg <= mode26_reg;
'd27:mode_reg <= mode27_reg;
'd28:mode_reg <= mode28_reg;
'd29:mode_reg <= mode29_reg;
'd30:mode_reg <= mode30_reg;
'd31:mode_reg <= mode31_reg;
'd32:mode_reg <= mode32_reg;
'd33:mode_reg <= mode33_reg;
default:mode_reg <= {(MODE-DIGIT+1){1'b1}};
endcase
always@(posedge clk or negedge rstn)
if(!rstn)
begin
bestmode <= 'd0;
modebest <= {(MODE-DIGIT+1){1'b1}};
end
else if(comparebegin)
begin
bestmode <= 'd2;
modebest <= mode2[MODE:DIGIT];
end
else if (modebest > mode_reg)
begin
bestmode <= cnt-1;
modebest <= mode_reg;
end
else
begin
bestmode <= bestmode;
modebest <= modebest;
end
//=======================16*16=======================
reg [5:0] bestmode16;
reg [MODE-DIGIT+2:0] modebest16;
reg [MODE-DIGIT+2:0] mode_reg16;
reg [MODE-DIGIT+2:0] mode2_reg16;
reg [MODE-DIGIT+2:0] mode3_reg16;
reg [MODE-DIGIT+2:0] mode4_reg16;
reg [MODE-DIGIT+2:0] mode5_reg16;
reg [MODE-DIGIT+2:0] mode6_reg16;
reg [MODE-DIGIT+2:0] mode7_reg16;
reg [MODE-DIGIT+2:0] mode8_reg16;
reg [MODE-DIGIT+2:0] mode9_reg16;
reg [MODE-DIGIT+2:0] mode10_reg16;
reg [MODE-DIGIT+2:0] mode11_reg16;
reg [MODE-DIGIT+2:0] mode12_reg16;
reg [MODE-DIGIT+2:0] mode13_reg16;
reg [MODE-DIGIT+2:0] mode14_reg16;
reg [MODE-DIGIT+2:0] mode15_reg16;
reg [MODE-DIGIT+2:0] mode16_reg16;
reg [MODE-DIGIT+2:0] mode17_reg16;
reg [MODE-DIGIT+2:0] mode18_reg16;
reg [MODE-DIGIT+2:0] mode19_reg16;
reg [MODE-DIGIT+2:0] mode20_reg16;
reg [MODE-DIGIT+2:0] mode21_reg16;
reg [MODE-DIGIT+2:0] mode22_reg16;
reg [MODE-DIGIT+2:0] mode23_reg16;
reg [MODE-DIGIT+2:0] mode24_reg16;
reg [MODE-DIGIT+2:0] mode25_reg16;
reg [MODE-DIGIT+2:0] mode26_reg16;
reg [MODE-DIGIT+2:0] mode27_reg16;
reg [MODE-DIGIT+2:0] mode28_reg16;
reg [MODE-DIGIT+2:0] mode29_reg16;
reg [MODE-DIGIT+2:0] mode30_reg16;
reg [MODE-DIGIT+2:0] mode31_reg16;
reg [MODE-DIGIT+2:0] mode32_reg16;
reg [MODE-DIGIT+2:0] mode33_reg16;
reg [MODE-DIGIT+2:0] adda16;
reg [MODE-DIGIT:0] addb16;
wire [MODE-DIGIT+2:0] sum16;
always@(posedge clk or negedge rstn)
if(!rstn)
adda16 <= 'd0;
else
case(cnt)
'd4 : adda16 <= mode2_reg16 ;
'd5 : adda16 <= mode3_reg16 ;
'd6 : adda16 <= mode4_reg16 ;
'd7 : adda16 <= mode5_reg16 ;
'd8 : adda16 <= mode6_reg16 ;
'd9 : adda16 <= mode7_reg16 ;
'd10 : adda16 <= mode8_reg16 ;
'd11 : adda16 <= mode9_reg16 ;
'd12 : adda16 <= mode10_reg16 ;
'd13 : adda16 <= mode11_reg16 ;
'd14 : adda16 <= mode12_reg16 ;
'd15 : adda16 <= mode13_reg16 ;
'd16 : adda16 <= mode14_reg16 ;
'd17 : adda16 <= mode15_reg16 ;
'd18 : adda16 <= mode16_reg16 ;
'd19 : adda16 <= mode17_reg16 ;
'd20 : adda16 <= mode18_reg16 ;
'd21 : adda16 <= mode19_reg16 ;
'd22 : adda16 <= mode20_reg16 ;
'd23 : adda16 <= mode21_reg16 ;
'd24 : adda16 <= mode22_reg16 ;
'd25 : adda16 <= mode23_reg16 ;
'd26 : adda16 <= mode24_reg16 ;
'd27 : adda16 <= mode25_reg16 ;
'd28 : adda16 <= mode26_reg16 ;
'd29 : adda16 <= mode27_reg16 ;
'd30 : adda16 <= mode28_reg16 ;
'd31 : adda16 <= mode29_reg16 ;
'd32 : adda16 <= mode30_reg16 ;
'd33 : adda16 <= mode31_reg16 ;
'd34 : adda16 <= mode32_reg16 ;
'd35 : adda16 <= mode33_reg16 ;
default: adda16 <= 'd0;
endcase
always@(posedge clk or negedge rstn)
if(!rstn)
addb16 <= 'd0;
else
case(cnt)
'd4 : addb16 <= mode2_reg ;
'd5 : addb16 <= mode3_reg ;
'd6 : addb16 <= mode4_reg ;
'd7 : addb16 <= mode5_reg ;
'd8 : addb16 <= mode6_reg ;
'd9 : addb16 <= mode7_reg ;
'd10 : addb16 <= mode8_reg ;
'd11 : addb16 <= mode9_reg ;
'd12 : addb16 <= mode10_reg ;
'd13 : addb16 <= mode11_reg ;
'd14 : addb16 <= mode12_reg ;
'd15 : addb16 <= mode13_reg ;
'd16 : addb16 <= mode14_reg ;
'd17 : addb16 <= mode15_reg ;
'd18 : addb16 <= mode16_reg ;
'd19 : addb16 <= mode17_reg ;
'd20 : addb16 <= mode18_reg ;
'd21 : addb16 <= mode19_reg ;
'd22 : addb16 <= mode20_reg ;
'd23 : addb16 <= mode21_reg ;
'd24 : addb16 <= mode22_reg ;
'd25 : addb16 <= mode23_reg ;
'd26 : addb16 <= mode24_reg ;
'd27 : addb16 <= mode25_reg ;
'd28 : addb16 <= mode26_reg ;
'd29 : addb16 <= mode27_reg ;
'd30 : addb16 <= mode28_reg ;
'd31 : addb16 <= mode29_reg ;
'd32 : addb16 <= mode30_reg ;
'd33 : addb16 <= mode31_reg ;
'd34 : addb16 <= mode32_reg ;
'd35 : addb16 <= mode33_reg ;
default: addb16 <= 'd0;
endcase
assign sum16=adda16+addb16;
always@(posedge clk or negedge rstn)
if(!rstn)
begin
mode2_reg16 <= 'd0;
mode3_reg16 <= 'd0;
mode4_reg16 <= 'd0;
mode5_reg16 <= 'd0;
mode6_reg16 <= 'd0;
mode7_reg16 <= 'd0;
mode8_reg16 <= 'd0;
mode9_reg16 <= 'd0;
mode10_reg16 <= 'd0;
mode11_reg16 <= 'd0;
mode12_reg16 <= 'd0;
mode13_reg16 <= 'd0;
mode14_reg16 <= 'd0;
mode15_reg16 <= 'd0;
mode16_reg16 <= 'd0;
mode17_reg16 <= 'd0;
mode18_reg16 <= 'd0;
mode19_reg16 <= 'd0;
mode20_reg16 <= 'd0;
mode21_reg16 <= 'd0;
mode22_reg16 <= 'd0;
mode23_reg16 <= 'd0;
mode24_reg16 <= 'd0;
mode25_reg16 <= 'd0;
mode26_reg16 <= 'd0;
mode27_reg16 <= 'd0;
mode28_reg16 <= 'd0;
mode29_reg16 <= 'd0;
mode30_reg16 <= 'd0;
mode31_reg16 <= 'd0;
mode32_reg16 <= 'd0;
mode33_reg16 <= 'd0;
end
else if(comparebegin && (blockcnt[1:0]==2'b01))
begin
mode2_reg16 <= 'd0;
mode3_reg16 <= 'd0;
mode4_reg16 <= 'd0;
mode5_reg16 <= 'd0;
mode6_reg16 <= 'd0;
mode7_reg16 <= 'd0;
mode8_reg16 <= 'd0;
mode9_reg16 <= 'd0;
mode10_reg16 <= 'd0;
mode11_reg16 <= 'd0;
mode12_reg16 <= 'd0;
mode13_reg16 <= 'd0;
mode14_reg16 <= 'd0;
mode15_reg16 <= 'd0;
mode16_reg16 <= 'd0;
mode17_reg16 <= 'd0;
mode18_reg16 <= 'd0;
mode19_reg16 <= 'd0;
mode20_reg16 <= 'd0;
mode21_reg16 <= 'd0;
mode22_reg16 <= 'd0;
mode23_reg16 <= 'd0;
mode24_reg16 <= 'd0;
mode25_reg16 <= 'd0;
mode26_reg16 <= 'd0;
mode27_reg16 <= 'd0;
mode28_reg16 <= 'd0;
mode29_reg16 <= 'd0;
mode30_reg16 <= 'd0;
mode31_reg16 <= 'd0;
mode32_reg16 <= 'd0;
mode33_reg16 <= 'd0;
end
else
begin
case(cnt)
'd5 :mode2_reg16 <= sum16;
'd6 :mode3_reg16 <= sum16;
'd7 :mode4_reg16 <= sum16;
'd8 :mode5_reg16 <= sum16;
'd9 :mode6_reg16 <= sum16;
'd10 :mode7_reg16 <= sum16;
'd11 :mode8_reg16 <= sum16;
'd12 :mode9_reg16 <= sum16;
'd13 :mode10_reg16 <= sum16;
'd14 :mode11_reg16 <= sum16;
'd15 :mode12_reg16 <= sum16;
'd16 :mode13_reg16 <= sum16;
'd17 :mode14_reg16 <= sum16;
'd18 :mode15_reg16 <= sum16;
'd19 :mode16_reg16 <= sum16;
'd20 :mode17_reg16 <= sum16;
'd21 :mode18_reg16 <= sum16;
'd22 :mode19_reg16 <= sum16;
'd23 :mode20_reg16 <= sum16;
'd24 :mode21_reg16 <= sum16;
'd25 :mode22_reg16 <= sum16;
'd26 :mode23_reg16 <= sum16;
'd27 :mode24_reg16 <= sum16;
'd28 :mode25_reg16 <= sum16;
'd29 :mode26_reg16 <= sum16;
'd30 :mode27_reg16 <= sum16;
'd31 :mode28_reg16 <= sum16;
'd32 :mode29_reg16 <= sum16;
'd33 :mode30_reg16 <= sum16;
'd34 :mode31_reg16 <= sum16;
'd35 :mode32_reg16 <= sum16;
'd36 :mode33_reg16 <= sum16;
default:
begin
mode2_reg16 <= mode2_reg16 ;
mode3_reg16 <= mode3_reg16 ;
mode4_reg16 <= mode4_reg16 ;
mode5_reg16 <= mode5_reg16 ;
mode6_reg16 <= mode6_reg16 ;
mode7_reg16 <= mode7_reg16 ;
mode8_reg16 <= mode8_reg16 ;
mode9_reg16 <= mode9_reg16 ;
mode10_reg16 <= mode10_reg16;
mode11_reg16 <= mode11_reg16;
mode12_reg16 <= mode12_reg16;
mode13_reg16 <= mode13_reg16;
mode14_reg16 <= mode14_reg16;
mode15_reg16 <= mode15_reg16;
mode16_reg16 <= mode16_reg16;
mode17_reg16 <= mode17_reg16;
mode18_reg16 <= mode18_reg16;
mode19_reg16 <= mode19_reg16;
mode20_reg16 <= mode20_reg16;
mode21_reg16 <= mode21_reg16;
mode22_reg16 <= mode22_reg16;
mode23_reg16 <= mode23_reg16;
mode24_reg16 <= mode24_reg16;
mode25_reg16 <= mode25_reg16;
mode26_reg16 <= mode26_reg16;
mode27_reg16 <= mode27_reg16;
mode28_reg16 <= mode28_reg16;
mode29_reg16 <= mode29_reg16;
mode30_reg16 <= mode30_reg16;
mode31_reg16 <= mode31_reg16;
mode32_reg16 <= mode32_reg16;
mode33_reg16 <= mode33_reg16;
end
endcase
end
always@(posedge clk or negedge rstn)
if(!rstn)
mode_reg16 <= 'd0;
else
mode_reg16 <= sum16 ;
always@(posedge clk or negedge rstn)
if(!rstn)
begin
bestmode16 <= 'd0;
modebest16 <= {(MODE-DIGIT+3){1'b1}};
end
else if(comparebegin16)
begin
bestmode16 <= 'd2;
modebest16 <= {(MODE-DIGIT+3){1'b1}};
end
else if ((modebest16 > mode_reg16) & comparerun16)
begin
bestmode16 <= cnt-4;
modebest16 <= mode_reg16;
end
else
begin
bestmode16 <= bestmode16;
modebest16 <= modebest16;
end
//=======================32*32=======================
reg [5:0] bestmode32;
reg [MODE-DIGIT+4:0] modebest32;
reg [MODE-DIGIT+4:0] mode_reg32;
reg [MODE-DIGIT+4:0] mode2_reg32;
reg [MODE-DIGIT+4:0] mode3_reg32;
reg [MODE-DIGIT+4:0] mode4_reg32;
reg [MODE-DIGIT+4:0] mode5_reg32;
reg [MODE-DIGIT+4:0] mode6_reg32;
reg [MODE-DIGIT+4:0] mode7_reg32;
reg [MODE-DIGIT+4:0] mode8_reg32;
reg [MODE-DIGIT+4:0] mode9_reg32;
reg [MODE-DIGIT+4:0] mode10_reg32;
reg [MODE-DIGIT+4:0] mode11_reg32;
reg [MODE-DIGIT+4:0] mode12_reg32;
reg [MODE-DIGIT+4:0] mode13_reg32;
reg [MODE-DIGIT+4:0] mode14_reg32;
reg [MODE-DIGIT+4:0] mode15_reg32;
reg [MODE-DIGIT+4:0] mode16_reg32;
reg [MODE-DIGIT+4:0] mode17_reg32;
reg [MODE-DIGIT+4:0] mode18_reg32;
reg [MODE-DIGIT+4:0] mode19_reg32;
reg [MODE-DIGIT+4:0] mode20_reg32;
reg [MODE-DIGIT+4:0] mode21_reg32;
reg [MODE-DIGIT+4:0] mode22_reg32;
reg [MODE-DIGIT+4:0] mode23_reg32;
reg [MODE-DIGIT+4:0] mode24_reg32;
reg [MODE-DIGIT+4:0] mode25_reg32;
reg [MODE-DIGIT+4:0] mode26_reg32;
reg [MODE-DIGIT+4:0] mode27_reg32;
reg [MODE-DIGIT+4:0] mode28_reg32;
reg [MODE-DIGIT+4:0] mode29_reg32;
reg [MODE-DIGIT+4:0] mode30_reg32;
reg [MODE-DIGIT+4:0] mode31_reg32;
reg [MODE-DIGIT+4:0] mode32_reg32;
reg [MODE-DIGIT+4:0] mode33_reg32;
reg [MODE-DIGIT+4:0] adda32;
reg [MODE-DIGIT+2:0] addb32;
wire [MODE-DIGIT+4:0] sum32;
always@(posedge clk or negedge rstn)
if(!rstn)
adda32 <= 'd0;
else
case(cnt)
'd6 : adda32 <= mode2_reg32 ;
'd7 : adda32 <= mode3_reg32 ;
'd8 : adda32 <= mode4_reg32 ;
'd9 : adda32 <= mode5_reg32 ;
'd10 : adda32 <= mode6_reg32 ;
'd11 : adda32 <= mode7_reg32 ;
'd12 : adda32 <= mode8_reg32 ;
'd13 : adda32 <= mode9_reg32 ;
'd14 : adda32 <= mode10_reg32 ;
'd15 : adda32 <= mode11_reg32 ;
'd16 : adda32 <= mode12_reg32 ;
'd17 : adda32 <= mode13_reg32 ;
'd18 : adda32 <= mode14_reg32 ;
'd19 : adda32 <= mode15_reg32 ;
'd20 : adda32 <= mode16_reg32 ;
'd21 : adda32 <= mode17_reg32 ;
'd22 : adda32 <= mode18_reg32 ;
'd23 : adda32 <= mode19_reg32 ;
'd24 : adda32 <= mode20_reg32 ;
'd25 : adda32 <= mode21_reg32 ;
'd26 : adda32 <= mode22_reg32 ;
'd27 : adda32 <= mode23_reg32 ;
'd28 : adda32 <= mode24_reg32 ;
'd29 : adda32 <= mode25_reg32 ;
'd30 : adda32 <= mode26_reg32 ;
'd31 : adda32 <= mode27_reg32 ;
'd32 : adda32 <= mode28_reg32 ;
'd33 : adda32 <= mode29_reg32 ;
'd34 : adda32 <= mode30_reg32 ;
'd35 : adda32 <= mode31_reg32 ;
'd36 : adda32 <= mode32_reg32 ;
'd37 : adda32 <= mode33_reg32 ;
default: adda32 <= 'd0;
endcase
always@(posedge clk or negedge rstn)
if(!rstn)
addb32 <= 'd0;
else if(comparerun16)
addb32 <= mode_reg16;
assign sum32=adda32+addb32;
always@(posedge clk or negedge rstn)
if(!rstn)
begin
mode2_reg32 <= 'd0;
mode3_reg32 <= 'd0;
mode4_reg32 <= 'd0;
mode5_reg32 <= 'd0;
mode6_reg32 <= 'd0;
mode7_reg32 <= 'd0;
mode8_reg32 <= 'd0;
mode9_reg32 <= 'd0;
mode10_reg32 <= 'd0;
mode11_reg32 <= 'd0;
mode12_reg32 <= 'd0;
mode13_reg32 <= 'd0;
mode14_reg32 <= 'd0;
mode15_reg32 <= 'd0;
mode16_reg32 <= 'd0;
mode17_reg32 <= 'd0;
mode18_reg32 <= 'd0;
mode19_reg32 <= 'd0;
mode20_reg32 <= 'd0;
mode21_reg32 <= 'd0;
mode22_reg32 <= 'd0;
mode23_reg32 <= 'd0;
mode24_reg32 <= 'd0;
mode25_reg32 <= 'd0;
mode26_reg32 <= 'd0;
mode27_reg32 <= 'd0;
mode28_reg32 <= 'd0;
mode29_reg32 <= 'd0;
mode30_reg32 <= 'd0;
mode31_reg32 <= 'd0;
mode32_reg32 <= 'd0;
mode33_reg32 <= 'd0;
end
else if(comparebegin && (blockcnt[3:0]=='d3))
begin
mode2_reg32 <= 'd0;
mode3_reg32 <= 'd0;
mode4_reg32 <= 'd0;
mode5_reg32 <= 'd0;
mode6_reg32 <= 'd0;
mode7_reg32 <= 'd0;
mode8_reg32 <= 'd0;
mode9_reg32 <= 'd0;
mode10_reg32 <= 'd0;
mode11_reg32 <= 'd0;
mode12_reg32 <= 'd0;
mode13_reg32 <= 'd0;
mode14_reg32 <= 'd0;
mode15_reg32 <= 'd0;
mode16_reg32 <= 'd0;
mode17_reg32 <= 'd0;
mode18_reg32 <= 'd0;
mode19_reg32 <= 'd0;
mode20_reg32 <= 'd0;
mode21_reg32 <= 'd0;
mode22_reg32 <= 'd0;
mode23_reg32 <= 'd0;
mode24_reg32 <= 'd0;
mode25_reg32 <= 'd0;
mode26_reg32 <= 'd0;
mode27_reg32 <= 'd0;
mode28_reg32 <= 'd0;
mode29_reg32 <= 'd0;
mode30_reg32 <= 'd0;
mode31_reg32 <= 'd0;
mode32_reg32 <= 'd0;
mode33_reg32 <= 'd0;
end
else if(blockcnt[1:0]=='d0)
begin
case(cnt)
'd7 :mode2_reg32 <= sum32;
'd8 :mode3_reg32 <= sum32;
'd9 :mode4_reg32 <= sum32;
'd10 :mode5_reg32 <= sum32;
'd11 :mode6_reg32 <= sum32;
'd12 :mode7_reg32 <= sum32;
'd13 :mode8_reg32 <= sum32;
'd14 :mode9_reg32 <= sum32;
'd15 :mode10_reg32 <= sum32;
'd16 :mode11_reg32 <= sum32;
'd17 :mode12_reg32 <= sum32;
'd18 :mode13_reg32 <= sum32;
'd19 :mode14_reg32 <= sum32;
'd20 :mode15_reg32 <= sum32;
'd21 :mode16_reg32 <= sum32;
'd22 :mode17_reg32 <= sum32;
'd23 :mode18_reg32 <= sum32;
'd24 :mode19_reg32 <= sum32;
'd25 :mode20_reg32 <= sum32;
'd26 :mode21_reg32 <= sum32;
'd27 :mode22_reg32 <= sum32;
'd28 :mode23_reg32 <= sum32;
'd29 :mode24_reg32 <= sum32;
'd30 :mode25_reg32 <= sum32;
'd31 :mode26_reg32 <= sum32;
'd32 :mode27_reg32 <= sum32;
'd33 :mode28_reg32 <= sum32;
'd34 :mode29_reg32 <= sum32;
'd35 :mode30_reg32 <= sum32;
'd36 :mode31_reg32 <= sum32;
'd37 :mode32_reg32 <= sum32;
'd38 :mode33_reg32 <= sum32;
default:
begin
mode2_reg32 <= mode2_reg32 ;
mode3_reg32 <= mode3_reg32 ;
mode4_reg32 <= mode4_reg32 ;
mode5_reg32 <= mode5_reg32 ;
mode6_reg32 <= mode6_reg32 ;
mode7_reg32 <= mode7_reg32 ;
mode8_reg32 <= mode8_reg32 ;
mode9_reg32 <= mode9_reg32 ;
mode10_reg32 <= mode10_reg32;
mode11_reg32 <= mode11_reg32;
mode12_reg32 <= mode12_reg32;
mode13_reg32 <= mode13_reg32;
mode14_reg32 <= mode14_reg32;
mode15_reg32 <= mode15_reg32;
mode16_reg32 <= mode16_reg32;
mode17_reg32 <= mode17_reg32;
mode18_reg32 <= mode18_reg32;
mode19_reg32 <= mode19_reg32;
mode20_reg32 <= mode20_reg32;
mode21_reg32 <= mode21_reg32;
mode22_reg32 <= mode22_reg32;
mode23_reg32 <= mode23_reg32;
mode24_reg32 <= mode24_reg32;
mode25_reg32 <= mode25_reg32;
mode26_reg32 <= mode26_reg32;
mode27_reg32 <= mode27_reg32;
mode28_reg32 <= mode28_reg32;
mode29_reg32 <= mode29_reg32;
mode30_reg32 <= mode30_reg32;
mode31_reg32 <= mode31_reg32;
mode32_reg32 <= mode32_reg32;
mode33_reg32 <= mode33_reg32;
end
endcase
end
always@(posedge clk or negedge rstn)
if(!rstn)
mode_reg32 <= 'd0;
else if(comparerun32)
mode_reg32 <= sum32;
always@(posedge clk or negedge rstn)
if(!rstn)
begin
bestmode32 <= 'd0;
modebest32 <= {(MODE-DIGIT+5){1'b1}};
end
else if(comparebegin32)
begin
bestmode32 <= 'd2;
modebest32 <= {(MODE-DIGIT+5){1'b1}};
end
else if ((modebest32 > mode_reg32) & comparerun32_reg)
begin
bestmode32 <= cnt-6;
modebest32 <= mode_reg32;
end
else
begin
bestmode32 <= bestmode32;
modebest32 <= modebest32;
end
endmodule
|
module design_1_xbar_0 (
aclk,
aresetn,
s_axi_awaddr,
s_axi_awprot,
s_axi_awvalid,
s_axi_awready,
s_axi_wdata,
s_axi_wstrb,
s_axi_wvalid,
s_axi_wready,
s_axi_bresp,
s_axi_bvalid,
s_axi_bready,
s_axi_araddr,
s_axi_arprot,
s_axi_arvalid,
s_axi_arready,
s_axi_rdata,
s_axi_rresp,
s_axi_rvalid,
s_axi_rready,
m_axi_awaddr,
m_axi_awprot,
m_axi_awvalid,
m_axi_awready,
m_axi_wdata,
m_axi_wstrb,
m_axi_wvalid,
m_axi_wready,
m_axi_bresp,
m_axi_bvalid,
m_axi_bready,
m_axi_araddr,
m_axi_arprot,
m_axi_arvalid,
m_axi_arready,
m_axi_rdata,
m_axi_rresp,
m_axi_rvalid,
m_axi_rready
);
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLKIF CLK" *)
input wire aclk;
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RSTIF RST" *)
input wire aresetn;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWADDR" *)
input wire [31 : 0] s_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWPROT" *)
input wire [2 : 0] s_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWVALID" *)
input wire [0 : 0] s_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWREADY" *)
output wire [0 : 0] s_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WDATA" *)
input wire [31 : 0] s_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WSTRB" *)
input wire [3 : 0] s_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WVALID" *)
input wire [0 : 0] s_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WREADY" *)
output wire [0 : 0] s_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI BRESP" *)
output wire [1 : 0] s_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI BVALID" *)
output wire [0 : 0] s_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI BREADY" *)
input wire [0 : 0] s_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARADDR" *)
input wire [31 : 0] s_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARPROT" *)
input wire [2 : 0] s_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARVALID" *)
input wire [0 : 0] s_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARREADY" *)
output wire [0 : 0] s_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RDATA" *)
output wire [31 : 0] s_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RRESP" *)
output wire [1 : 0] s_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RVALID" *)
output wire [0 : 0] s_axi_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RREADY" *)
input wire [0 : 0] s_axi_rready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWADDR [31:0] [31:0], xilinx.com:interface:aximm:1.0 M01_AXI AWADDR [31:0] [63:32]" *)
output wire [63 : 0] m_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWPROT [2:0] [2:0], xilinx.com:interface:aximm:1.0 M01_AXI AWPROT [2:0] [5:3]" *)
output wire [5 : 0] m_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI AWVALID [0:0] [1:1]" *)
output wire [1 : 0] m_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI AWREADY [0:0] [1:1]" *)
input wire [1 : 0] m_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI WDATA [31:0] [31:0], xilinx.com:interface:aximm:1.0 M01_AXI WDATA [31:0] [63:32]" *)
output wire [63 : 0] m_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI WSTRB [3:0] [3:0], xilinx.com:interface:aximm:1.0 M01_AXI WSTRB [3:0] [7:4]" *)
output wire [7 : 0] m_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI WVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI WVALID [0:0] [1:1]" *)
output wire [1 : 0] m_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI WREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI WREADY [0:0] [1:1]" *)
input wire [1 : 0] m_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI BRESP [1:0] [1:0], xilinx.com:interface:aximm:1.0 M01_AXI BRESP [1:0] [3:2]" *)
input wire [3 : 0] m_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI BVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI BVALID [0:0] [1:1]" *)
input wire [1 : 0] m_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI BREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI BREADY [0:0] [1:1]" *)
output wire [1 : 0] m_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARADDR [31:0] [31:0], xilinx.com:interface:aximm:1.0 M01_AXI ARADDR [31:0] [63:32]" *)
output wire [63 : 0] m_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARPROT [2:0] [2:0], xilinx.com:interface:aximm:1.0 M01_AXI ARPROT [2:0] [5:3]" *)
output wire [5 : 0] m_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI ARVALID [0:0] [1:1]" *)
output wire [1 : 0] m_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI ARREADY [0:0] [1:1]" *)
input wire [1 : 0] m_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RDATA [31:0] [31:0], xilinx.com:interface:aximm:1.0 M01_AXI RDATA [31:0] [63:32]" *)
input wire [63 : 0] m_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RRESP [1:0] [1:0], xilinx.com:interface:aximm:1.0 M01_AXI RRESP [1:0] [3:2]" *)
input wire [3 : 0] m_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI RVALID [0:0] [1:1]" *)
input wire [1 : 0] m_axi_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI RREADY [0:0] [1:1]" *)
output wire [1 : 0] m_axi_rready;
axi_crossbar_v2_1_axi_crossbar #(
.C_FAMILY("zynq"),
.C_NUM_SLAVE_SLOTS(1),
.C_NUM_MASTER_SLOTS(2),
.C_AXI_ID_WIDTH(1),
.C_AXI_ADDR_WIDTH(32),
.C_AXI_DATA_WIDTH(32),
.C_AXI_PROTOCOL(2),
.C_NUM_ADDR_RANGES(1),
.C_M_AXI_BASE_ADDR(128'H0000000042c100000000000042c00000),
.C_M_AXI_ADDR_WIDTH(64'H0000001000000010),
.C_S_AXI_BASE_ID(32'H00000000),
.C_S_AXI_THREAD_ID_WIDTH(32'H00000000),
.C_AXI_SUPPORTS_USER_SIGNALS(0),
.C_AXI_AWUSER_WIDTH(1),
.C_AXI_ARUSER_WIDTH(1),
.C_AXI_WUSER_WIDTH(1),
.C_AXI_RUSER_WIDTH(1),
.C_AXI_BUSER_WIDTH(1),
.C_M_AXI_WRITE_CONNECTIVITY(64'HFFFFFFFFFFFFFFFF),
.C_M_AXI_READ_CONNECTIVITY(64'HFFFFFFFFFFFFFFFF),
.C_R_REGISTER(1),
.C_S_AXI_SINGLE_THREAD(32'H00000001),
.C_S_AXI_WRITE_ACCEPTANCE(32'H00000001),
.C_S_AXI_READ_ACCEPTANCE(32'H00000001),
.C_M_AXI_WRITE_ISSUING(64'H0000000100000001),
.C_M_AXI_READ_ISSUING(64'H0000000100000001),
.C_S_AXI_ARB_PRIORITY(32'H00000000),
.C_M_AXI_SECURE(32'H00000000),
.C_CONNECTIVITY_MODE(0)
) inst (
.aclk(aclk),
.aresetn(aresetn),
.s_axi_awid(1'H0),
.s_axi_awaddr(s_axi_awaddr),
.s_axi_awlen(8'H00),
.s_axi_awsize(3'H0),
.s_axi_awburst(2'H0),
.s_axi_awlock(1'H0),
.s_axi_awcache(4'H0),
.s_axi_awprot(s_axi_awprot),
.s_axi_awqos(4'H0),
.s_axi_awuser(1'H0),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_awready(s_axi_awready),
.s_axi_wid(1'H0),
.s_axi_wdata(s_axi_wdata),
.s_axi_wstrb(s_axi_wstrb),
.s_axi_wlast(1'H1),
.s_axi_wuser(1'H0),
.s_axi_wvalid(s_axi_wvalid),
.s_axi_wready(s_axi_wready),
.s_axi_bid(),
.s_axi_bresp(s_axi_bresp),
.s_axi_buser(),
.s_axi_bvalid(s_axi_bvalid),
.s_axi_bready(s_axi_bready),
.s_axi_arid(1'H0),
.s_axi_araddr(s_axi_araddr),
.s_axi_arlen(8'H00),
.s_axi_arsize(3'H0),
.s_axi_arburst(2'H0),
.s_axi_arlock(1'H0),
.s_axi_arcache(4'H0),
.s_axi_arprot(s_axi_arprot),
.s_axi_arqos(4'H0),
.s_axi_aruser(1'H0),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_arready(s_axi_arready),
.s_axi_rid(),
.s_axi_rdata(s_axi_rdata),
.s_axi_rresp(s_axi_rresp),
.s_axi_rlast(),
.s_axi_ruser(),
.s_axi_rvalid(s_axi_rvalid),
.s_axi_rready(s_axi_rready),
.m_axi_awid(),
.m_axi_awaddr(m_axi_awaddr),
.m_axi_awlen(),
.m_axi_awsize(),
.m_axi_awburst(),
.m_axi_awlock(),
.m_axi_awcache(),
.m_axi_awprot(m_axi_awprot),
.m_axi_awregion(),
.m_axi_awqos(),
.m_axi_awuser(),
.m_axi_awvalid(m_axi_awvalid),
.m_axi_awready(m_axi_awready),
.m_axi_wid(),
.m_axi_wdata(m_axi_wdata),
.m_axi_wstrb(m_axi_wstrb),
.m_axi_wlast(),
.m_axi_wuser(),
.m_axi_wvalid(m_axi_wvalid),
.m_axi_wready(m_axi_wready),
.m_axi_bid(2'H0),
.m_axi_bresp(m_axi_bresp),
.m_axi_buser(2'H0),
.m_axi_bvalid(m_axi_bvalid),
.m_axi_bready(m_axi_bready),
.m_axi_arid(),
.m_axi_araddr(m_axi_araddr),
.m_axi_arlen(),
.m_axi_arsize(),
.m_axi_arburst(),
.m_axi_arlock(),
.m_axi_arcache(),
.m_axi_arprot(m_axi_arprot),
.m_axi_arregion(),
.m_axi_arqos(),
.m_axi_aruser(),
.m_axi_arvalid(m_axi_arvalid),
.m_axi_arready(m_axi_arready),
.m_axi_rid(2'H0),
.m_axi_rdata(m_axi_rdata),
.m_axi_rresp(m_axi_rresp),
.m_axi_rlast(2'H3),
.m_axi_ruser(2'H0),
.m_axi_rvalid(m_axi_rvalid),
.m_axi_rready(m_axi_rready)
);
endmodule
|
module sky130_fd_sc_lp__dfbbn (
Q ,
Q_N ,
D ,
CLK_N ,
SET_B ,
RESET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
// Module ports
output Q ;
output Q_N ;
input D ;
input CLK_N ;
input SET_B ;
input RESET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
// Local signals
wire RESET ;
wire SET ;
wire CLK ;
wire buf_Q ;
wire CLK_N_delayed ;
wire RESET_B_delayed;
wire SET_B_delayed ;
// Delay Name Output Other arguments
not not0 (RESET , RESET_B );
not not1 (SET , SET_B );
not not2 (CLK , CLK_N );
sky130_fd_sc_lp__udp_dff$NSR_pp$PG$N `UNIT_DELAY dff0 (buf_Q , SET, RESET, CLK, D, , VPWR, VGND);
buf buf0 (Q , buf_Q );
not not3 (Q_N , buf_Q );
endmodule
|
module gfx_interp(clk_i, rst_i,
ack_i, ack_o,
write_i,
// Variables needed for interpolation
edge0_i, edge1_i, area_i,
// Raster position
x_i, y_i, x_o, y_o,
factor0_o, factor1_o,
write_o
);
parameter point_width = 16;
parameter delay_width = 5;
parameter div_delay = point_width+1;
parameter result_width = 4;
input clk_i;
input rst_i;
input ack_i;
output reg ack_o;
input write_i;
input [2*point_width-1:0] edge0_i;
input [2*point_width-1:0] edge1_i;
input [2*point_width-1:0] area_i;
input [point_width-1:0] x_i;
input [point_width-1:0] y_i;
output [point_width-1:0] x_o;
output [point_width-1:0] y_o;
// Generated pixel coordinates
output [point_width-1:0] factor0_o;
output [point_width-1:0] factor1_o;
// Write pixel output signal
output write_o;
// calculates factor0
wire [point_width-1:0] interp0_quotient; // result
wire [point_width-1:0] interp0_reminder;
wire interp0_div_by_zero;
wire interp0_overflow;
// calculates factor1
wire [point_width-1:0] interp1_quotient; // result
wire [point_width-1:0] interp1_reminder;
wire interp1_div_by_zero;
wire interp1_overflow;
reg [delay_width-1:0] phase_counter;
wire division_enable;
always @(posedge clk_i or posedge rst_i)
if(rst_i)
phase_counter <= 1'b0;
else if(division_enable)
phase_counter <= (phase_counter + 1'b1 == div_delay) ? 1'b0 : phase_counter + 1'b1;
// State machine
reg state;
parameter wait_state = 1'b0,
write_state = 1'b1;
// Manage states
always @(posedge clk_i or posedge rst_i)
if(rst_i)
state <= wait_state;
else
case (state)
wait_state:
if(write_o)
state <= write_state;
write_state:
if(ack_i)
state <= wait_state;
endcase
always @(posedge clk_i or posedge rst_i)
begin
// Reset
if(rst_i)
ack_o <= 1'b0;
else
case (state)
wait_state:
ack_o <= 1'b0;
write_state:
if(ack_i)
ack_o <= 1'b1;
endcase
end
wire [point_width-1:0] zeroes = 1'b0;
// division unit 0
div_uu #(2*point_width) dut0 (
.clk (clk_i),
.ena (division_enable),
.z ({edge0_i[point_width-1:0], zeroes}),
.d (area_i[point_width-1:0]),
.q (interp0_quotient),
.s (interp0_reminder),
.div0 (interp0_div_by_zero),
.ovf (interp0_overflow)
);
// division unit 1
div_uu #(2*point_width) dut1 (
.clk (clk_i),
.ena (division_enable),
.z ({edge1_i[point_width-1:0], zeroes}),
.d (area_i[point_width-1:0]),
.q (interp1_quotient),
.s (interp1_reminder),
.div0 (interp1_div_by_zero),
.ovf (interp1_overflow)
);
wire result_full;
wire result_valid;
wire [result_width:0] result_count;
wire result_deque = result_valid & (state == wait_state);
assign write_o = result_deque;
assign division_enable = ~result_full;
wire delay_valid;
wire [delay_width-1:0] delay_phase_counter;
wire division_complete = division_enable & delay_valid & (phase_counter == delay_phase_counter);
wire [point_width-1:0] delay_x, delay_y;
// Fifo for finished results
basic_fifo result_fifo(
.clk_i ( clk_i ),
.rst_i ( rst_i ),
.data_i ( {interp0_quotient, interp1_quotient, delay_x, delay_y} ),
.enq_i ( division_complete ),
.full_o ( result_full ), // TODO: use?
.count_o ( result_count ),
.data_o ( {factor0_o, factor1_o, x_o, y_o} ),
.valid_o ( result_valid ),
.deq_i ( result_deque )
);
defparam result_fifo.fifo_width = 4*point_width;
defparam result_fifo.fifo_bit_depth = result_width;
// Another Fifo for current calculations
basic_fifo queue_fifo(
.clk_i ( clk_i ),
.rst_i ( rst_i ),
.data_i ( {phase_counter, x_i, y_i} ),
.enq_i ( write_i ),
.full_o ( ), // TODO: use?
.count_o ( ),
.data_o ( {delay_phase_counter, delay_x, delay_y} ),
.valid_o ( delay_valid ),
.deq_i ( division_complete )
);
defparam queue_fifo.fifo_width = delay_width + 2*point_width;
defparam queue_fifo.fifo_bit_depth = delay_width;
endmodule
|
module sky130_fd_sc_ms__ebufn_2 (
Z ,
A ,
TE_B,
VPWR,
VGND,
VPB ,
VNB
);
output Z ;
input A ;
input TE_B;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ms__ebufn base (
.Z(Z),
.A(A),
.TE_B(TE_B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
|
module sky130_fd_sc_ms__ebufn_2 (
Z ,
A ,
TE_B
);
output Z ;
input A ;
input TE_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__ebufn base (
.Z(Z),
.A(A),
.TE_B(TE_B)
);
endmodule
|
module generates the video timing based on the parameters specified
// by the test program.
//
axis_gen #(
.DLY (DLY),
.INTERLACE (INTERLACE),
.DATA_WIDTH (TDATA_WIDTH)
)
axis_gen_i (
.aclk (aclk ),
.rst (rst ),
.axis_tready (axis_tready ),
.axis_tvalid (axis_tvalid),
.axis_tdata_video (axis_video),
.axis_tlast (axis_eol ),
.axis_tuser_sof (axis_sof ),
.fid (fid),
.active_pixels (active_pixels),
.active_lines (active_lines )
);
timing_gen #(
.DLY (DLY),
.INTERLACE (INTERLACE),
.DATA_WIDTH (VDATA_WIDTH)
)
timing_gen_i (
.clk (video_clk),
.rst (rst),
.ce (ce),
.active_lines (active_lines ),
.total_lines (total_lines ),
.vsync_start (vsync_start ),
.vsync_end (vsync_end ),
.active_pixels (active_pixels),
.total_pixels (total_pixels ),
.hsync_start (hsync_start ),
.hsync_end (hsync_end ),
.hsync (vtg_hsync ),
.vsync (vtg_vsync ),
.hblank (vtg_hblank ),
.vblank (vtg_vblank ),
.de (vtg_act_vid ),
.field_id (vtg_field_id ),
.video_data ()
);
//------------------------------------------------------------------------------
// Top level Video output bridge -- DUT
//
tutorial_v_axi4s_vid_out_0_0
dut (
.aclk (aclk),
.rst (rst),
.aclken (aclken ),
.aresetn (aresetn),
.s_axis_video_tdata (axis_video ),
.s_axis_video_tvalid (axis_tvalid),
.s_axis_video_tready (axis_tready),
.s_axis_video_tuser (axis_sof ),
.s_axis_video_tlast (axis_eol ),
.fid (fid),
.vid_io_out_clk (video_clk),
.vid_io_out_ce (vid_ce),
.vid_active_video (de),
.vid_vsync (vsync),
.vid_hsync (hsync),
.vid_vblank (hblank),
.vid_hblank (vblank),
.vid_field_id (vid_field_id),
.vid_data (video_data),
.vtg_vsync (vtg_vsync ),
.vtg_hsync (vtg_hsync ),
.vtg_vblank (vtg_vblank),
.vtg_hblank (vtg_hblank),
.vtg_active_video (vtg_act_vid),
.vtg_field_id (vtg_field_id),
.vtg_ce (ce),
.locked (vtg_locked), //out
.wr_error (wr_error ), //out
.empty (rd_error ) //out
);
//
// Test program : This program controls the operation of the test bench.
//
test_vid_out #(
.DLY (DLY),
.NUM_TESTS (NUM_TESTS)
)
test_vid_out_i (
.clk (video_clk),
.error (error),
.frame_complete (frame_complete),
.rst (rst),
.total_lines (total_lines),
.active_lines (active_lines),
.vsync_start (vsync_start ),
.vsync_end (vsync_end ),
.total_pixels (total_pixels ),
.active_pixels (active_pixels),
.hsync_start (hsync_start ),
.hsync_end (hsync_end )
);
phy_emulation #(
.DLY (DLY),
.INTERLACE (INTERLACE),
.DATA_WIDTH (VDATA_WIDTH)
)
phy_emulation_i (
.clk (video_clk),
.rst (rst),
.vid_ce (vid_ce),
.hsync (hsync),
.vsync (vsync),
.de (de),
.vid_field_id (vid_field_id),
.video_data (video_data),
.error_out (error),
.frame_complete (frame_complete)
);
endmodule
|
module axis_gen #(
parameter DLY = 1,
parameter INTERLACE = 0,
parameter DATA_WIDTH = 24
)
(
input wire aclk,
input wire rst,
input wire axis_tready,
output wire axis_tvalid,
output reg [DATA_WIDTH-1:0] axis_tdata_video,
output reg axis_tlast,
output reg fid,
output reg axis_tuser_sof,
input wire [13:0] active_pixels,
input wire [13:0] active_lines
);
// variable declarations
reg [13:0] pixel_count = 0;
reg [13:0] line_count = 0;
wire eol;
wire sof;
reg eol_1;
wire set_axis_tvalid;
real duty_cycle_phase_accum;
assign eol = pixel_count == active_pixels - 1;
assign sof = line_count == 0 && pixel_count == 0;
assign axis_tvalid = 1;
// delay eol
always @ (posedge aclk)
eol_1 <= eol;
//
// pixel counter
//
// Cleared to 0 on reset and at active pixels - 1. Otherwise
// increments every clock cycle.
//
always @ (posedge aclk) begin
if (axis_tready & axis_tvalid)
begin
if (rst || eol)
pixel_count <= 0;
else
pixel_count <= pixel_count + 1;
end
end
//
// Line counter
//
// Set to line 0 on reset or max lines. Increments coincident with pixel 0.
//
always @ (posedge aclk)
if (axis_tready)
begin
if (rst || ((line_count >= active_lines - 1) && eol) )begin
line_count <= 0;
end
else if (eol)
line_count <= line_count + 1;
end
// Generate the video outputs. The video is gengerated procedurally
// according to the line and pixel number. This makes it so the checking
// side can reconstruct the expected data by the same procedure.
always @ (posedge aclk) begin
if (rst) begin
axis_tlast <= 0;
axis_tuser_sof <= 0;
if (INTERLACE)
fid <= 1;
else
fid <= 0;
end
else if (axis_tready) begin
axis_tdata_video <= INTERLACE && ((!fid && sof) || (fid && !sof))?
{~line_count, ~pixel_count[11:0]}:
{line_count, pixel_count[11:0]};
axis_tlast <= eol;
axis_tuser_sof <= sof;
// set field ID bit
if (INTERLACE) begin
if (sof)
fid <= ~fid;
end
else begin
fid <= 0; // always field 0 if not interlaced
end
end
end
endmodule
|
module timing_gen #(
parameter DLY = 1,
parameter INTERLACE = 0,
parameter DATA_WIDTH = 24
)
(
input wire clk,
input wire rst,
input wire ce,
input wire [13:0] active_lines,
input wire [13:0] total_lines,
input wire [13:0] vsync_start,
input wire [13:0] vsync_end,
input wire [13:0] active_pixels,
input wire [13:0] total_pixels,
input wire [13:0] hsync_start,
input wire [13:0] hsync_end,
output wire hsync,
output wire vsync,
output wire hblank,
output wire vblank,
output reg field_id = 0,
output wire de,
output wire [DATA_WIDTH-1:0] video_data
);
// variable declarations
reg [13:0] pixel_count = 0;
reg [13:0] line_count = 0;
reg [8:0] frame_count = 0;
//
// pixel counter
//
// Cleared to 0 on reset. Rolls over when it reaches total_pixels-1. Otherwise
// increments every clock cycle.
//
always @ (posedge clk) begin
if (rst)
# DLY pixel_count <= 0;
else if (ce) begin
if (pixel_count == total_pixels-1)
# DLY pixel_count <= 0;
else
# DLY pixel_count <= pixel_count + 1;
end
end
//
// Line counter
//
// Set to line 0 on reset. Increments coincident with pixel 0.
//
always @ (posedge clk) begin
if (rst) begin
line_count <= # DLY 0;
frame_count <= # DLY 0;
field_id <= # DLY 0;
end
else if (ce) begin
if (frame_count >= 13)
begin
$display ("Frame counter timed out. Test error.");
$display("*******************************");
$display("** ERROR. TEST FAILED !!!");
$display("*******************************");
$stop;
end
else if (pixel_count == total_pixels - 1)
if (line_count == total_lines - 1) begin
line_count <= 0;
frame_count <= frame_count +1;
if (INTERLACE)
field_id <= ~field_id;
else
field_id <= 0; // for non interlace, always field 0
end
else
line_count <= # DLY line_count + 1;
end
end
//
// Generate the hasync, vsync and data enable timing signals at the appropriate place on each line
// by examining the pixel counter.
//
assign hsync = pixel_count >= hsync_start && pixel_count <= hsync_end;
assign vsync = line_count >= vsync_start && line_count <= vsync_end;
assign hblank = !(pixel_count <= (active_pixels-1));
assign vblank = !(line_count <= (active_lines -1));
assign de = line_count <= (active_lines -1) && pixel_count <= (active_pixels - 1);
// Generate the video outputs. The video is generated procedurally
// according to the line and pixel number. This makes it so the checking
// side can reconstruct the expected data by the same procedure.
assign video_data = {line_count , pixel_count[11:0]};
endmodule
|
module test_vid_out #(
parameter DLY = 1,
parameter NUM_TESTS = 2
)
(
input wire clk,
input wire error,
input wire frame_complete,
output reg rst,
output reg [13:0] total_lines,
output reg [13:0] active_lines,
output reg [13:0] vsync_start,
output reg [13:0] vsync_end,
output reg [13:0] total_pixels,
output reg [13:0] active_pixels,
output reg [13:0] hsync_start,
output reg [13:0] hsync_end
);
integer i;
reg [11:0] h_size = 103;
reg [11:0] v_size = 81;
reg [9:0] h_blank = 15;
reg [9:0] v_blank = 8;
reg [9:0] h_sync = 8;
reg [9:0] v_sync = 3;
reg [9:0] h_fp = 3;
reg [9:0] v_fp = 2;
// Task to test one line standard
task test_a_line_std;
input [11:0] h_size;
input [11:0] v_size;
begin
$display("Frame Size is %d x %d ", h_size, v_size);
// Hold reset for several cycles,
rst <= 1;
repeat (10) @ (posedge clk);
rst <= # DLY 0;
wait (frame_complete);
$display("frame_complete");
end
endtask
//
// Stimulus loop
//
// Calls test_a_line_std task for a certain number of line standards
//
initial begin
for (i = 0; i< NUM_TESTS; i= i+1) begin
total_lines = v_size + v_blank;
active_lines = v_size;
vsync_start = v_size + v_fp -1;
vsync_end = vsync_start + v_sync;
total_pixels = h_size + h_blank;
active_pixels = h_size;
hsync_start = h_size + h_fp -1;
hsync_end = hsync_start + h_sync;
$display("Format # %0d", i);
test_a_line_std (
h_size,
v_size
);
h_size= h_size +33;
v_size = v_size + 27;
end
$display("Test passed after testing %0d video formats.", NUM_TESTS);
$display("***************************************");
$display("** Test completed successfully **");
$display("** Simulation finished successfully **");
$display("***************************************");
$stop;
end
endmodule
|
module phy_emulation #(
parameter DLY = 1,
parameter INTERLACE = 0,
parameter DATA_WIDTH = 24
)
(
input wire clk,
input wire rst,
input wire vid_ce,
input wire hsync,
input wire vsync,
input wire de,
input wire vid_field_id,
input wire [DATA_WIDTH-1:0] video_data,
output reg error_out,
output reg frame_complete
);
// variable declarations
reg [13:0] pixel_count;
reg [13:0] line_count;
reg [DATA_WIDTH-1:0] video_data_1;
reg de_1;
reg de_2;
reg hsync_1;
reg vsync_1;
wire[DATA_WIDTH-1:0] expected_video_data;
reg count_valid = 0;
wire vsync_rising;
reg vblank;
wire compare_valid;
assign vsync_rising = vsync & !vsync_1;
assign compare_valid = de & count_valid & !frame_complete;
// Delay data and eol to match with pixel and line numbers
always @ (posedge clk) begin
if (vid_ce) begin
video_data_1 <= video_data;
de_1 <= de;
de_2 <= de_1;
hsync_1 <= hsync;
vsync_1 <= vsync;
end
end
//
// pixel counter
//
// Cleared to 0 on reset and hsync. Rolls over when it reaches total_pixels-1. Otherwise
// increments every data enable.
//
always @ (posedge clk) begin
if (vid_ce) begin
if (rst || hsync)
pixel_count <= 0;
else if (de_1)
pixel_count <= pixel_count + 1;
end
end
//
// Line counter
//
// Set to line 0 on reset or vsync. Increments coincident with rising edge
// of de.
//
always @ (posedge clk) begin
if (rst)begin
line_count <= 0;
count_valid <= 0;
frame_complete <= 0;
end
else if (vid_ce) begin
if (vsync_rising) begin // count is valid after 1st vsync
vblank <= 1; // set flag to indicate this is during vert. blank
line_count <= 0;
if ( !INTERLACE || vid_field_id) // for interlace start with field 1
count_valid <= 1;
// if count_valid is already asserted, the frame is complete
// For interlace, additionally, wait for field 2
if ( count_valid && (!INTERLACE || vid_field_id))
frame_complete <= 1;
end
else if (&line_count)
begin
$display ("Line counter reached maximum value. Test error.");
$stop;
end
else if (de & !de_1) begin// increment on every rising de after vblank
if (!vblank)
line_count <= line_count + 1;
vblank <= 0;
end
end
end
// Generate the video outputs. The video is gengerated procedurally
// according to the line and pixel number. This makes it so the checking
// side can reconstruct the expected data by the same procedure.
assign expected_video_data = vid_field_id?
{~line_count, ~pixel_count[11:0]}: //invert data for field 1
{line_count, pixel_count[11:0]};
always @ (posedge clk) begin
if (vid_ce) begin
error_out <= 0;
if (compare_valid) begin
# DLY #DLY if (video_data_1 != expected_video_data) begin
$display ("Data Mismatch. Expected: %h, received: %h. Test error.",
expected_video_data, video_data_1);
error_out <= 1;
$display("*******************************");
$display("** ERROR. TEST FAILED !!!");
$display("*******************************");
$stop;
end
end
end
end
endmodule
|
module sky130_fd_sc_lp__o221ai_0 (
Y ,
A1 ,
A2 ,
B1 ,
B2 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__o221ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2),
.C1(C1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
|
module sky130_fd_sc_lp__o221ai_0 (
Y ,
A1,
A2,
B1,
B2,
C1
);
output Y ;
input A1;
input A2;
input B1;
input B2;
input C1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__o221ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2),
.C1(C1)
);
endmodule
|
module soc_design_SystemID (
// inputs:
address,
clock,
reset_n,
// outputs:
readdata
)
;
output [ 31: 0] readdata;
input address;
input clock;
input reset_n;
wire [ 31: 0] readdata;
//control_slave, which is an e_avalon_slave
assign readdata = address ? 1500949681 : 255;
endmodule
|
module HBM_ONE_STACK_INTF #(
`ifdef XIL_TIMING
parameter LOC = "UNPLACED",
`endif
parameter CLK_SEL_00 = "FALSE",
parameter CLK_SEL_01 = "FALSE",
parameter CLK_SEL_02 = "FALSE",
parameter CLK_SEL_03 = "FALSE",
parameter CLK_SEL_04 = "FALSE",
parameter CLK_SEL_05 = "FALSE",
parameter CLK_SEL_06 = "FALSE",
parameter CLK_SEL_07 = "FALSE",
parameter CLK_SEL_08 = "FALSE",
parameter CLK_SEL_09 = "FALSE",
parameter CLK_SEL_10 = "FALSE",
parameter CLK_SEL_11 = "FALSE",
parameter CLK_SEL_12 = "FALSE",
parameter CLK_SEL_13 = "FALSE",
parameter CLK_SEL_14 = "FALSE",
parameter CLK_SEL_15 = "FALSE",
parameter integer DATARATE_00 = 1800,
parameter integer DATARATE_01 = 1800,
parameter integer DATARATE_02 = 1800,
parameter integer DATARATE_03 = 1800,
parameter integer DATARATE_04 = 1800,
parameter integer DATARATE_05 = 1800,
parameter integer DATARATE_06 = 1800,
parameter integer DATARATE_07 = 1800,
parameter DA_LOCKOUT = "FALSE",
parameter [0:0] IS_APB_0_PCLK_INVERTED = 1'b0,
parameter [0:0] IS_APB_0_PRESET_N_INVERTED = 1'b0,
parameter [0:0] IS_AXI_00_ACLK_INVERTED = 1'b0,
parameter [0:0] IS_AXI_00_ARESET_N_INVERTED = 1'b0,
parameter [0:0] IS_AXI_01_ACLK_INVERTED = 1'b0,
parameter [0:0] IS_AXI_01_ARESET_N_INVERTED = 1'b0,
parameter [0:0] IS_AXI_02_ACLK_INVERTED = 1'b0,
parameter [0:0] IS_AXI_02_ARESET_N_INVERTED = 1'b0,
parameter [0:0] IS_AXI_03_ACLK_INVERTED = 1'b0,
parameter [0:0] IS_AXI_03_ARESET_N_INVERTED = 1'b0,
parameter [0:0] IS_AXI_04_ACLK_INVERTED = 1'b0,
parameter [0:0] IS_AXI_04_ARESET_N_INVERTED = 1'b0,
parameter [0:0] IS_AXI_05_ACLK_INVERTED = 1'b0,
parameter [0:0] IS_AXI_05_ARESET_N_INVERTED = 1'b0,
parameter [0:0] IS_AXI_06_ACLK_INVERTED = 1'b0,
parameter [0:0] IS_AXI_06_ARESET_N_INVERTED = 1'b0,
parameter [0:0] IS_AXI_07_ACLK_INVERTED = 1'b0,
parameter [0:0] IS_AXI_07_ARESET_N_INVERTED = 1'b0,
parameter [0:0] IS_AXI_08_ACLK_INVERTED = 1'b0,
parameter [0:0] IS_AXI_08_ARESET_N_INVERTED = 1'b0,
parameter [0:0] IS_AXI_09_ACLK_INVERTED = 1'b0,
parameter [0:0] IS_AXI_09_ARESET_N_INVERTED = 1'b0,
parameter [0:0] IS_AXI_10_ACLK_INVERTED = 1'b0,
parameter [0:0] IS_AXI_10_ARESET_N_INVERTED = 1'b0,
parameter [0:0] IS_AXI_11_ACLK_INVERTED = 1'b0,
parameter [0:0] IS_AXI_11_ARESET_N_INVERTED = 1'b0,
parameter [0:0] IS_AXI_12_ACLK_INVERTED = 1'b0,
parameter [0:0] IS_AXI_12_ARESET_N_INVERTED = 1'b0,
parameter [0:0] IS_AXI_13_ACLK_INVERTED = 1'b0,
parameter [0:0] IS_AXI_13_ARESET_N_INVERTED = 1'b0,
parameter [0:0] IS_AXI_14_ACLK_INVERTED = 1'b0,
parameter [0:0] IS_AXI_14_ARESET_N_INVERTED = 1'b0,
parameter [0:0] IS_AXI_15_ACLK_INVERTED = 1'b0,
parameter [0:0] IS_AXI_15_ARESET_N_INVERTED = 1'b0,
parameter MC_ENABLE_0 = "FALSE",
parameter MC_ENABLE_1 = "FALSE",
parameter MC_ENABLE_2 = "FALSE",
parameter MC_ENABLE_3 = "FALSE",
parameter MC_ENABLE_4 = "FALSE",
parameter MC_ENABLE_5 = "FALSE",
parameter MC_ENABLE_6 = "FALSE",
parameter MC_ENABLE_7 = "FALSE",
parameter MC_ENABLE_APB = "FALSE",
parameter integer PAGEHIT_PERCENT_00 = 75,
parameter PHY_ENABLE_00 = "FALSE",
parameter PHY_ENABLE_01 = "FALSE",
parameter PHY_ENABLE_02 = "FALSE",
parameter PHY_ENABLE_03 = "FALSE",
parameter PHY_ENABLE_04 = "FALSE",
parameter PHY_ENABLE_05 = "FALSE",
parameter PHY_ENABLE_06 = "FALSE",
parameter PHY_ENABLE_07 = "FALSE",
parameter PHY_ENABLE_08 = "FALSE",
parameter PHY_ENABLE_09 = "FALSE",
parameter PHY_ENABLE_10 = "FALSE",
parameter PHY_ENABLE_11 = "FALSE",
parameter PHY_ENABLE_12 = "FALSE",
parameter PHY_ENABLE_13 = "FALSE",
parameter PHY_ENABLE_14 = "FALSE",
parameter PHY_ENABLE_15 = "FALSE",
parameter PHY_ENABLE_APB = "FALSE",
parameter PHY_PCLK_INVERT_01 = "FALSE",
parameter integer READ_PERCENT_00 = 50,
parameter integer READ_PERCENT_01 = 50,
parameter integer READ_PERCENT_02 = 50,
parameter integer READ_PERCENT_03 = 50,
parameter integer READ_PERCENT_04 = 50,
parameter integer READ_PERCENT_05 = 50,
parameter integer READ_PERCENT_06 = 50,
parameter integer READ_PERCENT_07 = 50,
parameter integer READ_PERCENT_08 = 50,
parameter integer READ_PERCENT_09 = 50,
parameter integer READ_PERCENT_10 = 50,
parameter integer READ_PERCENT_11 = 50,
parameter integer READ_PERCENT_12 = 50,
parameter integer READ_PERCENT_13 = 50,
parameter integer READ_PERCENT_14 = 50,
parameter integer READ_PERCENT_15 = 50,
parameter SIM_DEVICE = "ULTRASCALE_PLUS",
parameter integer STACK_LOCATION = 0,
parameter SWITCH_ENABLE = "FALSE",
parameter integer WRITE_PERCENT_00 = 50,
parameter integer WRITE_PERCENT_01 = 50,
parameter integer WRITE_PERCENT_02 = 50,
parameter integer WRITE_PERCENT_03 = 50,
parameter integer WRITE_PERCENT_04 = 50,
parameter integer WRITE_PERCENT_05 = 50,
parameter integer WRITE_PERCENT_06 = 50,
parameter integer WRITE_PERCENT_07 = 50,
parameter integer WRITE_PERCENT_08 = 50,
parameter integer WRITE_PERCENT_09 = 50,
parameter integer WRITE_PERCENT_10 = 50,
parameter integer WRITE_PERCENT_11 = 50,
parameter integer WRITE_PERCENT_12 = 50,
parameter integer WRITE_PERCENT_13 = 50,
parameter integer WRITE_PERCENT_14 = 50,
parameter integer WRITE_PERCENT_15 = 50
)(
output [31:0] APB_0_PRDATA,
output APB_0_PREADY,
output APB_0_PSLVERR,
output AXI_00_ARREADY,
output AXI_00_AWREADY,
output [5:0] AXI_00_BID,
output [1:0] AXI_00_BRESP,
output AXI_00_BVALID,
output [1:0] AXI_00_DFI_AW_AERR_N,
output AXI_00_DFI_CLK_BUF,
output [7:0] AXI_00_DFI_DBI_BYTE_DISABLE,
output [20:0] AXI_00_DFI_DW_RDDATA_DBI,
output [7:0] AXI_00_DFI_DW_RDDATA_DERR,
output [1:0] AXI_00_DFI_DW_RDDATA_VALID,
output AXI_00_DFI_INIT_COMPLETE,
output AXI_00_DFI_PHYUPD_REQ,
output AXI_00_DFI_PHY_LP_STATE,
output AXI_00_DFI_RST_N_BUF,
output [5:0] AXI_00_MC_STATUS,
output [7:0] AXI_00_PHY_STATUS,
output [255:0] AXI_00_RDATA,
output [31:0] AXI_00_RDATA_PARITY,
output [5:0] AXI_00_RID,
output AXI_00_RLAST,
output [1:0] AXI_00_RRESP,
output AXI_00_RVALID,
output AXI_00_WREADY,
output AXI_01_ARREADY,
output AXI_01_AWREADY,
output [5:0] AXI_01_BID,
output [1:0] AXI_01_BRESP,
output AXI_01_BVALID,
output [1:0] AXI_01_DFI_AW_AERR_N,
output AXI_01_DFI_CLK_BUF,
output [7:0] AXI_01_DFI_DBI_BYTE_DISABLE,
output [20:0] AXI_01_DFI_DW_RDDATA_DBI,
output [7:0] AXI_01_DFI_DW_RDDATA_DERR,
output [1:0] AXI_01_DFI_DW_RDDATA_VALID,
output AXI_01_DFI_INIT_COMPLETE,
output AXI_01_DFI_PHYUPD_REQ,
output AXI_01_DFI_PHY_LP_STATE,
output AXI_01_DFI_RST_N_BUF,
output [255:0] AXI_01_RDATA,
output [31:0] AXI_01_RDATA_PARITY,
output [5:0] AXI_01_RID,
output AXI_01_RLAST,
output [1:0] AXI_01_RRESP,
output AXI_01_RVALID,
output AXI_01_WREADY,
output AXI_02_ARREADY,
output AXI_02_AWREADY,
output [5:0] AXI_02_BID,
output [1:0] AXI_02_BRESP,
output AXI_02_BVALID,
output [1:0] AXI_02_DFI_AW_AERR_N,
output AXI_02_DFI_CLK_BUF,
output [7:0] AXI_02_DFI_DBI_BYTE_DISABLE,
output [20:0] AXI_02_DFI_DW_RDDATA_DBI,
output [7:0] AXI_02_DFI_DW_RDDATA_DERR,
output [1:0] AXI_02_DFI_DW_RDDATA_VALID,
output AXI_02_DFI_INIT_COMPLETE,
output AXI_02_DFI_PHYUPD_REQ,
output AXI_02_DFI_PHY_LP_STATE,
output AXI_02_DFI_RST_N_BUF,
output [5:0] AXI_02_MC_STATUS,
output [7:0] AXI_02_PHY_STATUS,
output [255:0] AXI_02_RDATA,
output [31:0] AXI_02_RDATA_PARITY,
output [5:0] AXI_02_RID,
output AXI_02_RLAST,
output [1:0] AXI_02_RRESP,
output AXI_02_RVALID,
output AXI_02_WREADY,
output AXI_03_ARREADY,
output AXI_03_AWREADY,
output [5:0] AXI_03_BID,
output [1:0] AXI_03_BRESP,
output AXI_03_BVALID,
output [1:0] AXI_03_DFI_AW_AERR_N,
output AXI_03_DFI_CLK_BUF,
output [7:0] AXI_03_DFI_DBI_BYTE_DISABLE,
output [20:0] AXI_03_DFI_DW_RDDATA_DBI,
output [7:0] AXI_03_DFI_DW_RDDATA_DERR,
output [1:0] AXI_03_DFI_DW_RDDATA_VALID,
output AXI_03_DFI_INIT_COMPLETE,
output AXI_03_DFI_PHYUPD_REQ,
output AXI_03_DFI_PHY_LP_STATE,
output AXI_03_DFI_RST_N_BUF,
output [255:0] AXI_03_RDATA,
output [31:0] AXI_03_RDATA_PARITY,
output [5:0] AXI_03_RID,
output AXI_03_RLAST,
output [1:0] AXI_03_RRESP,
output AXI_03_RVALID,
output AXI_03_WREADY,
output AXI_04_ARREADY,
output AXI_04_AWREADY,
output [5:0] AXI_04_BID,
output [1:0] AXI_04_BRESP,
output AXI_04_BVALID,
output [1:0] AXI_04_DFI_AW_AERR_N,
output AXI_04_DFI_CLK_BUF,
output [7:0] AXI_04_DFI_DBI_BYTE_DISABLE,
output [20:0] AXI_04_DFI_DW_RDDATA_DBI,
output [7:0] AXI_04_DFI_DW_RDDATA_DERR,
output [1:0] AXI_04_DFI_DW_RDDATA_VALID,
output AXI_04_DFI_INIT_COMPLETE,
output AXI_04_DFI_PHYUPD_REQ,
output AXI_04_DFI_PHY_LP_STATE,
output AXI_04_DFI_RST_N_BUF,
output [5:0] AXI_04_MC_STATUS,
output [7:0] AXI_04_PHY_STATUS,
output [255:0] AXI_04_RDATA,
output [31:0] AXI_04_RDATA_PARITY,
output [5:0] AXI_04_RID,
output AXI_04_RLAST,
output [1:0] AXI_04_RRESP,
output AXI_04_RVALID,
output AXI_04_WREADY,
output AXI_05_ARREADY,
output AXI_05_AWREADY,
output [5:0] AXI_05_BID,
output [1:0] AXI_05_BRESP,
output AXI_05_BVALID,
output [1:0] AXI_05_DFI_AW_AERR_N,
output AXI_05_DFI_CLK_BUF,
output [7:0] AXI_05_DFI_DBI_BYTE_DISABLE,
output [20:0] AXI_05_DFI_DW_RDDATA_DBI,
output [7:0] AXI_05_DFI_DW_RDDATA_DERR,
output [1:0] AXI_05_DFI_DW_RDDATA_VALID,
output AXI_05_DFI_INIT_COMPLETE,
output AXI_05_DFI_PHYUPD_REQ,
output AXI_05_DFI_PHY_LP_STATE,
output AXI_05_DFI_RST_N_BUF,
output [255:0] AXI_05_RDATA,
output [31:0] AXI_05_RDATA_PARITY,
output [5:0] AXI_05_RID,
output AXI_05_RLAST,
output [1:0] AXI_05_RRESP,
output AXI_05_RVALID,
output AXI_05_WREADY,
output AXI_06_ARREADY,
output AXI_06_AWREADY,
output [5:0] AXI_06_BID,
output [1:0] AXI_06_BRESP,
output AXI_06_BVALID,
output [1:0] AXI_06_DFI_AW_AERR_N,
output AXI_06_DFI_CLK_BUF,
output [7:0] AXI_06_DFI_DBI_BYTE_DISABLE,
output [20:0] AXI_06_DFI_DW_RDDATA_DBI,
output [7:0] AXI_06_DFI_DW_RDDATA_DERR,
output [1:0] AXI_06_DFI_DW_RDDATA_VALID,
output AXI_06_DFI_INIT_COMPLETE,
output AXI_06_DFI_PHYUPD_REQ,
output AXI_06_DFI_PHY_LP_STATE,
output AXI_06_DFI_RST_N_BUF,
output [5:0] AXI_06_MC_STATUS,
output [7:0] AXI_06_PHY_STATUS,
output [255:0] AXI_06_RDATA,
output [31:0] AXI_06_RDATA_PARITY,
output [5:0] AXI_06_RID,
output AXI_06_RLAST,
output [1:0] AXI_06_RRESP,
output AXI_06_RVALID,
output AXI_06_WREADY,
output AXI_07_ARREADY,
output AXI_07_AWREADY,
output [5:0] AXI_07_BID,
output [1:0] AXI_07_BRESP,
output AXI_07_BVALID,
output [1:0] AXI_07_DFI_AW_AERR_N,
output AXI_07_DFI_CLK_BUF,
output [7:0] AXI_07_DFI_DBI_BYTE_DISABLE,
output [20:0] AXI_07_DFI_DW_RDDATA_DBI,
output [7:0] AXI_07_DFI_DW_RDDATA_DERR,
output [1:0] AXI_07_DFI_DW_RDDATA_VALID,
output AXI_07_DFI_INIT_COMPLETE,
output AXI_07_DFI_PHYUPD_REQ,
output AXI_07_DFI_PHY_LP_STATE,
output AXI_07_DFI_RST_N_BUF,
output [255:0] AXI_07_RDATA,
output [31:0] AXI_07_RDATA_PARITY,
output [5:0] AXI_07_RID,
output AXI_07_RLAST,
output [1:0] AXI_07_RRESP,
output AXI_07_RVALID,
output AXI_07_WREADY,
output AXI_08_ARREADY,
output AXI_08_AWREADY,
output [5:0] AXI_08_BID,
output [1:0] AXI_08_BRESP,
output AXI_08_BVALID,
output [1:0] AXI_08_DFI_AW_AERR_N,
output AXI_08_DFI_CLK_BUF,
output [7:0] AXI_08_DFI_DBI_BYTE_DISABLE,
output [20:0] AXI_08_DFI_DW_RDDATA_DBI,
output [7:0] AXI_08_DFI_DW_RDDATA_DERR,
output [1:0] AXI_08_DFI_DW_RDDATA_VALID,
output AXI_08_DFI_INIT_COMPLETE,
output AXI_08_DFI_PHYUPD_REQ,
output AXI_08_DFI_PHY_LP_STATE,
output AXI_08_DFI_RST_N_BUF,
output [5:0] AXI_08_MC_STATUS,
output [7:0] AXI_08_PHY_STATUS,
output [255:0] AXI_08_RDATA,
output [31:0] AXI_08_RDATA_PARITY,
output [5:0] AXI_08_RID,
output AXI_08_RLAST,
output [1:0] AXI_08_RRESP,
output AXI_08_RVALID,
output AXI_08_WREADY,
output AXI_09_ARREADY,
output AXI_09_AWREADY,
output [5:0] AXI_09_BID,
output [1:0] AXI_09_BRESP,
output AXI_09_BVALID,
output [1:0] AXI_09_DFI_AW_AERR_N,
output AXI_09_DFI_CLK_BUF,
output [7:0] AXI_09_DFI_DBI_BYTE_DISABLE,
output [20:0] AXI_09_DFI_DW_RDDATA_DBI,
output [7:0] AXI_09_DFI_DW_RDDATA_DERR,
output [1:0] AXI_09_DFI_DW_RDDATA_VALID,
output AXI_09_DFI_INIT_COMPLETE,
output AXI_09_DFI_PHYUPD_REQ,
output AXI_09_DFI_PHY_LP_STATE,
output AXI_09_DFI_RST_N_BUF,
output [255:0] AXI_09_RDATA,
output [31:0] AXI_09_RDATA_PARITY,
output [5:0] AXI_09_RID,
output AXI_09_RLAST,
output [1:0] AXI_09_RRESP,
output AXI_09_RVALID,
output AXI_09_WREADY,
output AXI_10_ARREADY,
output AXI_10_AWREADY,
output [5:0] AXI_10_BID,
output [1:0] AXI_10_BRESP,
output AXI_10_BVALID,
output [1:0] AXI_10_DFI_AW_AERR_N,
output AXI_10_DFI_CLK_BUF,
output [7:0] AXI_10_DFI_DBI_BYTE_DISABLE,
output [20:0] AXI_10_DFI_DW_RDDATA_DBI,
output [7:0] AXI_10_DFI_DW_RDDATA_DERR,
output [1:0] AXI_10_DFI_DW_RDDATA_VALID,
output AXI_10_DFI_INIT_COMPLETE,
output AXI_10_DFI_PHYUPD_REQ,
output AXI_10_DFI_PHY_LP_STATE,
output AXI_10_DFI_RST_N_BUF,
output [5:0] AXI_10_MC_STATUS,
output [7:0] AXI_10_PHY_STATUS,
output [255:0] AXI_10_RDATA,
output [31:0] AXI_10_RDATA_PARITY,
output [5:0] AXI_10_RID,
output AXI_10_RLAST,
output [1:0] AXI_10_RRESP,
output AXI_10_RVALID,
output AXI_10_WREADY,
output AXI_11_ARREADY,
output AXI_11_AWREADY,
output [5:0] AXI_11_BID,
output [1:0] AXI_11_BRESP,
output AXI_11_BVALID,
output [1:0] AXI_11_DFI_AW_AERR_N,
output AXI_11_DFI_CLK_BUF,
output [7:0] AXI_11_DFI_DBI_BYTE_DISABLE,
output [20:0] AXI_11_DFI_DW_RDDATA_DBI,
output [7:0] AXI_11_DFI_DW_RDDATA_DERR,
output [1:0] AXI_11_DFI_DW_RDDATA_VALID,
output AXI_11_DFI_INIT_COMPLETE,
output AXI_11_DFI_PHYUPD_REQ,
output AXI_11_DFI_PHY_LP_STATE,
output AXI_11_DFI_RST_N_BUF,
output [255:0] AXI_11_RDATA,
output [31:0] AXI_11_RDATA_PARITY,
output [5:0] AXI_11_RID,
output AXI_11_RLAST,
output [1:0] AXI_11_RRESP,
output AXI_11_RVALID,
output AXI_11_WREADY,
output AXI_12_ARREADY,
output AXI_12_AWREADY,
output [5:0] AXI_12_BID,
output [1:0] AXI_12_BRESP,
output AXI_12_BVALID,
output [1:0] AXI_12_DFI_AW_AERR_N,
output AXI_12_DFI_CLK_BUF,
output [7:0] AXI_12_DFI_DBI_BYTE_DISABLE,
output [20:0] AXI_12_DFI_DW_RDDATA_DBI,
output [7:0] AXI_12_DFI_DW_RDDATA_DERR,
output [1:0] AXI_12_DFI_DW_RDDATA_VALID,
output AXI_12_DFI_INIT_COMPLETE,
output AXI_12_DFI_PHYUPD_REQ,
output AXI_12_DFI_PHY_LP_STATE,
output AXI_12_DFI_RST_N_BUF,
output [5:0] AXI_12_MC_STATUS,
output [7:0] AXI_12_PHY_STATUS,
output [255:0] AXI_12_RDATA,
output [31:0] AXI_12_RDATA_PARITY,
output [5:0] AXI_12_RID,
output AXI_12_RLAST,
output [1:0] AXI_12_RRESP,
output AXI_12_RVALID,
output AXI_12_WREADY,
output AXI_13_ARREADY,
output AXI_13_AWREADY,
output [5:0] AXI_13_BID,
output [1:0] AXI_13_BRESP,
output AXI_13_BVALID,
output [1:0] AXI_13_DFI_AW_AERR_N,
output AXI_13_DFI_CLK_BUF,
output [7:0] AXI_13_DFI_DBI_BYTE_DISABLE,
output [20:0] AXI_13_DFI_DW_RDDATA_DBI,
output [7:0] AXI_13_DFI_DW_RDDATA_DERR,
output [1:0] AXI_13_DFI_DW_RDDATA_VALID,
output AXI_13_DFI_INIT_COMPLETE,
output AXI_13_DFI_PHYUPD_REQ,
output AXI_13_DFI_PHY_LP_STATE,
output AXI_13_DFI_RST_N_BUF,
output [255:0] AXI_13_RDATA,
output [31:0] AXI_13_RDATA_PARITY,
output [5:0] AXI_13_RID,
output AXI_13_RLAST,
output [1:0] AXI_13_RRESP,
output AXI_13_RVALID,
output AXI_13_WREADY,
output AXI_14_ARREADY,
output AXI_14_AWREADY,
output [5:0] AXI_14_BID,
output [1:0] AXI_14_BRESP,
output AXI_14_BVALID,
output [1:0] AXI_14_DFI_AW_AERR_N,
output AXI_14_DFI_CLK_BUF,
output [7:0] AXI_14_DFI_DBI_BYTE_DISABLE,
output [20:0] AXI_14_DFI_DW_RDDATA_DBI,
output [7:0] AXI_14_DFI_DW_RDDATA_DERR,
output [1:0] AXI_14_DFI_DW_RDDATA_VALID,
output AXI_14_DFI_INIT_COMPLETE,
output AXI_14_DFI_PHYUPD_REQ,
output AXI_14_DFI_PHY_LP_STATE,
output AXI_14_DFI_RST_N_BUF,
output [5:0] AXI_14_MC_STATUS,
output [7:0] AXI_14_PHY_STATUS,
output [255:0] AXI_14_RDATA,
output [31:0] AXI_14_RDATA_PARITY,
output [5:0] AXI_14_RID,
output AXI_14_RLAST,
output [1:0] AXI_14_RRESP,
output AXI_14_RVALID,
output AXI_14_WREADY,
output AXI_15_ARREADY,
output AXI_15_AWREADY,
output [5:0] AXI_15_BID,
output [1:0] AXI_15_BRESP,
output AXI_15_BVALID,
output [1:0] AXI_15_DFI_AW_AERR_N,
output AXI_15_DFI_CLK_BUF,
output [7:0] AXI_15_DFI_DBI_BYTE_DISABLE,
output [20:0] AXI_15_DFI_DW_RDDATA_DBI,
output [7:0] AXI_15_DFI_DW_RDDATA_DERR,
output [1:0] AXI_15_DFI_DW_RDDATA_VALID,
output AXI_15_DFI_INIT_COMPLETE,
output AXI_15_DFI_PHYUPD_REQ,
output AXI_15_DFI_PHY_LP_STATE,
output AXI_15_DFI_RST_N_BUF,
output [255:0] AXI_15_RDATA,
output [31:0] AXI_15_RDATA_PARITY,
output [5:0] AXI_15_RID,
output AXI_15_RLAST,
output [1:0] AXI_15_RRESP,
output AXI_15_RVALID,
output AXI_15_WREADY,
output DRAM_0_STAT_CATTRIP,
output [2:0] DRAM_0_STAT_TEMP,
input [21:0] APB_0_PADDR,
input APB_0_PCLK,
input APB_0_PENABLE,
input APB_0_PRESET_N,
input APB_0_PSEL,
input [31:0] APB_0_PWDATA,
input APB_0_PWRITE,
input AXI_00_ACLK,
input [36:0] AXI_00_ARADDR,
input [1:0] AXI_00_ARBURST,
input AXI_00_ARESET_N,
input [5:0] AXI_00_ARID,
input [3:0] AXI_00_ARLEN,
input [2:0] AXI_00_ARSIZE,
input AXI_00_ARVALID,
input [36:0] AXI_00_AWADDR,
input [1:0] AXI_00_AWBURST,
input [5:0] AXI_00_AWID,
input [3:0] AXI_00_AWLEN,
input [2:0] AXI_00_AWSIZE,
input AXI_00_AWVALID,
input AXI_00_BREADY,
input AXI_00_DFI_LP_PWR_X_REQ,
input AXI_00_RREADY,
input [255:0] AXI_00_WDATA,
input [31:0] AXI_00_WDATA_PARITY,
input AXI_00_WLAST,
input [31:0] AXI_00_WSTRB,
input AXI_00_WVALID,
input AXI_01_ACLK,
input [36:0] AXI_01_ARADDR,
input [1:0] AXI_01_ARBURST,
input AXI_01_ARESET_N,
input [5:0] AXI_01_ARID,
input [3:0] AXI_01_ARLEN,
input [2:0] AXI_01_ARSIZE,
input AXI_01_ARVALID,
input [36:0] AXI_01_AWADDR,
input [1:0] AXI_01_AWBURST,
input [5:0] AXI_01_AWID,
input [3:0] AXI_01_AWLEN,
input [2:0] AXI_01_AWSIZE,
input AXI_01_AWVALID,
input AXI_01_BREADY,
input AXI_01_DFI_LP_PWR_X_REQ,
input AXI_01_RREADY,
input [255:0] AXI_01_WDATA,
input [31:0] AXI_01_WDATA_PARITY,
input AXI_01_WLAST,
input [31:0] AXI_01_WSTRB,
input AXI_01_WVALID,
input AXI_02_ACLK,
input [36:0] AXI_02_ARADDR,
input [1:0] AXI_02_ARBURST,
input AXI_02_ARESET_N,
input [5:0] AXI_02_ARID,
input [3:0] AXI_02_ARLEN,
input [2:0] AXI_02_ARSIZE,
input AXI_02_ARVALID,
input [36:0] AXI_02_AWADDR,
input [1:0] AXI_02_AWBURST,
input [5:0] AXI_02_AWID,
input [3:0] AXI_02_AWLEN,
input [2:0] AXI_02_AWSIZE,
input AXI_02_AWVALID,
input AXI_02_BREADY,
input AXI_02_DFI_LP_PWR_X_REQ,
input AXI_02_RREADY,
input [255:0] AXI_02_WDATA,
input [31:0] AXI_02_WDATA_PARITY,
input AXI_02_WLAST,
input [31:0] AXI_02_WSTRB,
input AXI_02_WVALID,
input AXI_03_ACLK,
input [36:0] AXI_03_ARADDR,
input [1:0] AXI_03_ARBURST,
input AXI_03_ARESET_N,
input [5:0] AXI_03_ARID,
input [3:0] AXI_03_ARLEN,
input [2:0] AXI_03_ARSIZE,
input AXI_03_ARVALID,
input [36:0] AXI_03_AWADDR,
input [1:0] AXI_03_AWBURST,
input [5:0] AXI_03_AWID,
input [3:0] AXI_03_AWLEN,
input [2:0] AXI_03_AWSIZE,
input AXI_03_AWVALID,
input AXI_03_BREADY,
input AXI_03_DFI_LP_PWR_X_REQ,
input AXI_03_RREADY,
input [255:0] AXI_03_WDATA,
input [31:0] AXI_03_WDATA_PARITY,
input AXI_03_WLAST,
input [31:0] AXI_03_WSTRB,
input AXI_03_WVALID,
input AXI_04_ACLK,
input [36:0] AXI_04_ARADDR,
input [1:0] AXI_04_ARBURST,
input AXI_04_ARESET_N,
input [5:0] AXI_04_ARID,
input [3:0] AXI_04_ARLEN,
input [2:0] AXI_04_ARSIZE,
input AXI_04_ARVALID,
input [36:0] AXI_04_AWADDR,
input [1:0] AXI_04_AWBURST,
input [5:0] AXI_04_AWID,
input [3:0] AXI_04_AWLEN,
input [2:0] AXI_04_AWSIZE,
input AXI_04_AWVALID,
input AXI_04_BREADY,
input AXI_04_DFI_LP_PWR_X_REQ,
input AXI_04_RREADY,
input [255:0] AXI_04_WDATA,
input [31:0] AXI_04_WDATA_PARITY,
input AXI_04_WLAST,
input [31:0] AXI_04_WSTRB,
input AXI_04_WVALID,
input AXI_05_ACLK,
input [36:0] AXI_05_ARADDR,
input [1:0] AXI_05_ARBURST,
input AXI_05_ARESET_N,
input [5:0] AXI_05_ARID,
input [3:0] AXI_05_ARLEN,
input [2:0] AXI_05_ARSIZE,
input AXI_05_ARVALID,
input [36:0] AXI_05_AWADDR,
input [1:0] AXI_05_AWBURST,
input [5:0] AXI_05_AWID,
input [3:0] AXI_05_AWLEN,
input [2:0] AXI_05_AWSIZE,
input AXI_05_AWVALID,
input AXI_05_BREADY,
input AXI_05_DFI_LP_PWR_X_REQ,
input AXI_05_RREADY,
input [255:0] AXI_05_WDATA,
input [31:0] AXI_05_WDATA_PARITY,
input AXI_05_WLAST,
input [31:0] AXI_05_WSTRB,
input AXI_05_WVALID,
input AXI_06_ACLK,
input [36:0] AXI_06_ARADDR,
input [1:0] AXI_06_ARBURST,
input AXI_06_ARESET_N,
input [5:0] AXI_06_ARID,
input [3:0] AXI_06_ARLEN,
input [2:0] AXI_06_ARSIZE,
input AXI_06_ARVALID,
input [36:0] AXI_06_AWADDR,
input [1:0] AXI_06_AWBURST,
input [5:0] AXI_06_AWID,
input [3:0] AXI_06_AWLEN,
input [2:0] AXI_06_AWSIZE,
input AXI_06_AWVALID,
input AXI_06_BREADY,
input AXI_06_DFI_LP_PWR_X_REQ,
input AXI_06_RREADY,
input [255:0] AXI_06_WDATA,
input [31:0] AXI_06_WDATA_PARITY,
input AXI_06_WLAST,
input [31:0] AXI_06_WSTRB,
input AXI_06_WVALID,
input AXI_07_ACLK,
input [36:0] AXI_07_ARADDR,
input [1:0] AXI_07_ARBURST,
input AXI_07_ARESET_N,
input [5:0] AXI_07_ARID,
input [3:0] AXI_07_ARLEN,
input [2:0] AXI_07_ARSIZE,
input AXI_07_ARVALID,
input [36:0] AXI_07_AWADDR,
input [1:0] AXI_07_AWBURST,
input [5:0] AXI_07_AWID,
input [3:0] AXI_07_AWLEN,
input [2:0] AXI_07_AWSIZE,
input AXI_07_AWVALID,
input AXI_07_BREADY,
input AXI_07_DFI_LP_PWR_X_REQ,
input AXI_07_RREADY,
input [255:0] AXI_07_WDATA,
input [31:0] AXI_07_WDATA_PARITY,
input AXI_07_WLAST,
input [31:0] AXI_07_WSTRB,
input AXI_07_WVALID,
input AXI_08_ACLK,
input [36:0] AXI_08_ARADDR,
input [1:0] AXI_08_ARBURST,
input AXI_08_ARESET_N,
input [5:0] AXI_08_ARID,
input [3:0] AXI_08_ARLEN,
input [2:0] AXI_08_ARSIZE,
input AXI_08_ARVALID,
input [36:0] AXI_08_AWADDR,
input [1:0] AXI_08_AWBURST,
input [5:0] AXI_08_AWID,
input [3:0] AXI_08_AWLEN,
input [2:0] AXI_08_AWSIZE,
input AXI_08_AWVALID,
input AXI_08_BREADY,
input AXI_08_DFI_LP_PWR_X_REQ,
input AXI_08_RREADY,
input [255:0] AXI_08_WDATA,
input [31:0] AXI_08_WDATA_PARITY,
input AXI_08_WLAST,
input [31:0] AXI_08_WSTRB,
input AXI_08_WVALID,
input AXI_09_ACLK,
input [36:0] AXI_09_ARADDR,
input [1:0] AXI_09_ARBURST,
input AXI_09_ARESET_N,
input [5:0] AXI_09_ARID,
input [3:0] AXI_09_ARLEN,
input [2:0] AXI_09_ARSIZE,
input AXI_09_ARVALID,
input [36:0] AXI_09_AWADDR,
input [1:0] AXI_09_AWBURST,
input [5:0] AXI_09_AWID,
input [3:0] AXI_09_AWLEN,
input [2:0] AXI_09_AWSIZE,
input AXI_09_AWVALID,
input AXI_09_BREADY,
input AXI_09_DFI_LP_PWR_X_REQ,
input AXI_09_RREADY,
input [255:0] AXI_09_WDATA,
input [31:0] AXI_09_WDATA_PARITY,
input AXI_09_WLAST,
input [31:0] AXI_09_WSTRB,
input AXI_09_WVALID,
input AXI_10_ACLK,
input [36:0] AXI_10_ARADDR,
input [1:0] AXI_10_ARBURST,
input AXI_10_ARESET_N,
input [5:0] AXI_10_ARID,
input [3:0] AXI_10_ARLEN,
input [2:0] AXI_10_ARSIZE,
input AXI_10_ARVALID,
input [36:0] AXI_10_AWADDR,
input [1:0] AXI_10_AWBURST,
input [5:0] AXI_10_AWID,
input [3:0] AXI_10_AWLEN,
input [2:0] AXI_10_AWSIZE,
input AXI_10_AWVALID,
input AXI_10_BREADY,
input AXI_10_DFI_LP_PWR_X_REQ,
input AXI_10_RREADY,
input [255:0] AXI_10_WDATA,
input [31:0] AXI_10_WDATA_PARITY,
input AXI_10_WLAST,
input [31:0] AXI_10_WSTRB,
input AXI_10_WVALID,
input AXI_11_ACLK,
input [36:0] AXI_11_ARADDR,
input [1:0] AXI_11_ARBURST,
input AXI_11_ARESET_N,
input [5:0] AXI_11_ARID,
input [3:0] AXI_11_ARLEN,
input [2:0] AXI_11_ARSIZE,
input AXI_11_ARVALID,
input [36:0] AXI_11_AWADDR,
input [1:0] AXI_11_AWBURST,
input [5:0] AXI_11_AWID,
input [3:0] AXI_11_AWLEN,
input [2:0] AXI_11_AWSIZE,
input AXI_11_AWVALID,
input AXI_11_BREADY,
input AXI_11_DFI_LP_PWR_X_REQ,
input AXI_11_RREADY,
input [255:0] AXI_11_WDATA,
input [31:0] AXI_11_WDATA_PARITY,
input AXI_11_WLAST,
input [31:0] AXI_11_WSTRB,
input AXI_11_WVALID,
input AXI_12_ACLK,
input [36:0] AXI_12_ARADDR,
input [1:0] AXI_12_ARBURST,
input AXI_12_ARESET_N,
input [5:0] AXI_12_ARID,
input [3:0] AXI_12_ARLEN,
input [2:0] AXI_12_ARSIZE,
input AXI_12_ARVALID,
input [36:0] AXI_12_AWADDR,
input [1:0] AXI_12_AWBURST,
input [5:0] AXI_12_AWID,
input [3:0] AXI_12_AWLEN,
input [2:0] AXI_12_AWSIZE,
input AXI_12_AWVALID,
input AXI_12_BREADY,
input AXI_12_DFI_LP_PWR_X_REQ,
input AXI_12_RREADY,
input [255:0] AXI_12_WDATA,
input [31:0] AXI_12_WDATA_PARITY,
input AXI_12_WLAST,
input [31:0] AXI_12_WSTRB,
input AXI_12_WVALID,
input AXI_13_ACLK,
input [36:0] AXI_13_ARADDR,
input [1:0] AXI_13_ARBURST,
input AXI_13_ARESET_N,
input [5:0] AXI_13_ARID,
input [3:0] AXI_13_ARLEN,
input [2:0] AXI_13_ARSIZE,
input AXI_13_ARVALID,
input [36:0] AXI_13_AWADDR,
input [1:0] AXI_13_AWBURST,
input [5:0] AXI_13_AWID,
input [3:0] AXI_13_AWLEN,
input [2:0] AXI_13_AWSIZE,
input AXI_13_AWVALID,
input AXI_13_BREADY,
input AXI_13_DFI_LP_PWR_X_REQ,
input AXI_13_RREADY,
input [255:0] AXI_13_WDATA,
input [31:0] AXI_13_WDATA_PARITY,
input AXI_13_WLAST,
input [31:0] AXI_13_WSTRB,
input AXI_13_WVALID,
input AXI_14_ACLK,
input [36:0] AXI_14_ARADDR,
input [1:0] AXI_14_ARBURST,
input AXI_14_ARESET_N,
input [5:0] AXI_14_ARID,
input [3:0] AXI_14_ARLEN,
input [2:0] AXI_14_ARSIZE,
input AXI_14_ARVALID,
input [36:0] AXI_14_AWADDR,
input [1:0] AXI_14_AWBURST,
input [5:0] AXI_14_AWID,
input [3:0] AXI_14_AWLEN,
input [2:0] AXI_14_AWSIZE,
input AXI_14_AWVALID,
input AXI_14_BREADY,
input AXI_14_DFI_LP_PWR_X_REQ,
input AXI_14_RREADY,
input [255:0] AXI_14_WDATA,
input [31:0] AXI_14_WDATA_PARITY,
input AXI_14_WLAST,
input [31:0] AXI_14_WSTRB,
input AXI_14_WVALID,
input AXI_15_ACLK,
input [36:0] AXI_15_ARADDR,
input [1:0] AXI_15_ARBURST,
input AXI_15_ARESET_N,
input [5:0] AXI_15_ARID,
input [3:0] AXI_15_ARLEN,
input [2:0] AXI_15_ARSIZE,
input AXI_15_ARVALID,
input [36:0] AXI_15_AWADDR,
input [1:0] AXI_15_AWBURST,
input [5:0] AXI_15_AWID,
input [3:0] AXI_15_AWLEN,
input [2:0] AXI_15_AWSIZE,
input AXI_15_AWVALID,
input AXI_15_BREADY,
input AXI_15_DFI_LP_PWR_X_REQ,
input AXI_15_RREADY,
input [255:0] AXI_15_WDATA,
input [31:0] AXI_15_WDATA_PARITY,
input AXI_15_WLAST,
input [31:0] AXI_15_WSTRB,
input AXI_15_WVALID,
input BSCAN_DRCK,
input BSCAN_TCK,
input HBM_REF_CLK,
input MBIST_EN_00,
input MBIST_EN_01,
input MBIST_EN_02,
input MBIST_EN_03,
input MBIST_EN_04,
input MBIST_EN_05,
input MBIST_EN_06,
input MBIST_EN_07
);
// define constants
localparam MODULE_NAME = "HBM_ONE_STACK_INTF";
// Parameter encodings and registers
localparam PHY_PCLK_INVERT_01_FALSE = 0;
localparam PHY_PCLK_INVERT_01_TRUE = 1;
reg trig_attr;
// include dynamic registers - XILINX test only
`ifdef XIL_DR
`include "HBM_ONE_STACK_INTF_dr.v"
`else
localparam [40:1] CLK_SEL_00_REG = CLK_SEL_00;
localparam [40:1] CLK_SEL_01_REG = CLK_SEL_01;
localparam [40:1] CLK_SEL_02_REG = CLK_SEL_02;
localparam [40:1] CLK_SEL_03_REG = CLK_SEL_03;
localparam [40:1] CLK_SEL_04_REG = CLK_SEL_04;
localparam [40:1] CLK_SEL_05_REG = CLK_SEL_05;
localparam [40:1] CLK_SEL_06_REG = CLK_SEL_06;
localparam [40:1] CLK_SEL_07_REG = CLK_SEL_07;
localparam [40:1] CLK_SEL_08_REG = CLK_SEL_08;
localparam [40:1] CLK_SEL_09_REG = CLK_SEL_09;
localparam [40:1] CLK_SEL_10_REG = CLK_SEL_10;
localparam [40:1] CLK_SEL_11_REG = CLK_SEL_11;
localparam [40:1] CLK_SEL_12_REG = CLK_SEL_12;
localparam [40:1] CLK_SEL_13_REG = CLK_SEL_13;
localparam [40:1] CLK_SEL_14_REG = CLK_SEL_14;
localparam [40:1] CLK_SEL_15_REG = CLK_SEL_15;
localparam [10:0] DATARATE_00_REG = DATARATE_00;
localparam [10:0] DATARATE_01_REG = DATARATE_01;
localparam [10:0] DATARATE_02_REG = DATARATE_02;
localparam [10:0] DATARATE_03_REG = DATARATE_03;
localparam [10:0] DATARATE_04_REG = DATARATE_04;
localparam [10:0] DATARATE_05_REG = DATARATE_05;
localparam [10:0] DATARATE_06_REG = DATARATE_06;
localparam [10:0] DATARATE_07_REG = DATARATE_07;
localparam [40:1] DA_LOCKOUT_REG = DA_LOCKOUT;
localparam [0:0] IS_APB_0_PCLK_INVERTED_REG = IS_APB_0_PCLK_INVERTED;
localparam [0:0] IS_APB_0_PRESET_N_INVERTED_REG = IS_APB_0_PRESET_N_INVERTED;
localparam [0:0] IS_AXI_00_ACLK_INVERTED_REG = IS_AXI_00_ACLK_INVERTED;
localparam [0:0] IS_AXI_00_ARESET_N_INVERTED_REG = IS_AXI_00_ARESET_N_INVERTED;
localparam [0:0] IS_AXI_01_ACLK_INVERTED_REG = IS_AXI_01_ACLK_INVERTED;
localparam [0:0] IS_AXI_01_ARESET_N_INVERTED_REG = IS_AXI_01_ARESET_N_INVERTED;
localparam [0:0] IS_AXI_02_ACLK_INVERTED_REG = IS_AXI_02_ACLK_INVERTED;
localparam [0:0] IS_AXI_02_ARESET_N_INVERTED_REG = IS_AXI_02_ARESET_N_INVERTED;
localparam [0:0] IS_AXI_03_ACLK_INVERTED_REG = IS_AXI_03_ACLK_INVERTED;
localparam [0:0] IS_AXI_03_ARESET_N_INVERTED_REG = IS_AXI_03_ARESET_N_INVERTED;
localparam [0:0] IS_AXI_04_ACLK_INVERTED_REG = IS_AXI_04_ACLK_INVERTED;
localparam [0:0] IS_AXI_04_ARESET_N_INVERTED_REG = IS_AXI_04_ARESET_N_INVERTED;
localparam [0:0] IS_AXI_05_ACLK_INVERTED_REG = IS_AXI_05_ACLK_INVERTED;
localparam [0:0] IS_AXI_05_ARESET_N_INVERTED_REG = IS_AXI_05_ARESET_N_INVERTED;
localparam [0:0] IS_AXI_06_ACLK_INVERTED_REG = IS_AXI_06_ACLK_INVERTED;
localparam [0:0] IS_AXI_06_ARESET_N_INVERTED_REG = IS_AXI_06_ARESET_N_INVERTED;
localparam [0:0] IS_AXI_07_ACLK_INVERTED_REG = IS_AXI_07_ACLK_INVERTED;
localparam [0:0] IS_AXI_07_ARESET_N_INVERTED_REG = IS_AXI_07_ARESET_N_INVERTED;
localparam [0:0] IS_AXI_08_ACLK_INVERTED_REG = IS_AXI_08_ACLK_INVERTED;
localparam [0:0] IS_AXI_08_ARESET_N_INVERTED_REG = IS_AXI_08_ARESET_N_INVERTED;
localparam [0:0] IS_AXI_09_ACLK_INVERTED_REG = IS_AXI_09_ACLK_INVERTED;
localparam [0:0] IS_AXI_09_ARESET_N_INVERTED_REG = IS_AXI_09_ARESET_N_INVERTED;
localparam [0:0] IS_AXI_10_ACLK_INVERTED_REG = IS_AXI_10_ACLK_INVERTED;
localparam [0:0] IS_AXI_10_ARESET_N_INVERTED_REG = IS_AXI_10_ARESET_N_INVERTED;
localparam [0:0] IS_AXI_11_ACLK_INVERTED_REG = IS_AXI_11_ACLK_INVERTED;
localparam [0:0] IS_AXI_11_ARESET_N_INVERTED_REG = IS_AXI_11_ARESET_N_INVERTED;
localparam [0:0] IS_AXI_12_ACLK_INVERTED_REG = IS_AXI_12_ACLK_INVERTED;
localparam [0:0] IS_AXI_12_ARESET_N_INVERTED_REG = IS_AXI_12_ARESET_N_INVERTED;
localparam [0:0] IS_AXI_13_ACLK_INVERTED_REG = IS_AXI_13_ACLK_INVERTED;
localparam [0:0] IS_AXI_13_ARESET_N_INVERTED_REG = IS_AXI_13_ARESET_N_INVERTED;
localparam [0:0] IS_AXI_14_ACLK_INVERTED_REG = IS_AXI_14_ACLK_INVERTED;
localparam [0:0] IS_AXI_14_ARESET_N_INVERTED_REG = IS_AXI_14_ARESET_N_INVERTED;
localparam [0:0] IS_AXI_15_ACLK_INVERTED_REG = IS_AXI_15_ACLK_INVERTED;
localparam [0:0] IS_AXI_15_ARESET_N_INVERTED_REG = IS_AXI_15_ARESET_N_INVERTED;
localparam [40:1] MC_ENABLE_0_REG = MC_ENABLE_0;
localparam [40:1] MC_ENABLE_1_REG = MC_ENABLE_1;
localparam [40:1] MC_ENABLE_2_REG = MC_ENABLE_2;
localparam [40:1] MC_ENABLE_3_REG = MC_ENABLE_3;
localparam [40:1] MC_ENABLE_4_REG = MC_ENABLE_4;
localparam [40:1] MC_ENABLE_5_REG = MC_ENABLE_5;
localparam [40:1] MC_ENABLE_6_REG = MC_ENABLE_6;
localparam [40:1] MC_ENABLE_7_REG = MC_ENABLE_7;
localparam [40:1] MC_ENABLE_APB_REG = MC_ENABLE_APB;
localparam [6:0] PAGEHIT_PERCENT_00_REG = PAGEHIT_PERCENT_00;
localparam [40:1] PHY_ENABLE_00_REG = PHY_ENABLE_00;
localparam [40:1] PHY_ENABLE_01_REG = PHY_ENABLE_01;
localparam [40:1] PHY_ENABLE_02_REG = PHY_ENABLE_02;
localparam [40:1] PHY_ENABLE_03_REG = PHY_ENABLE_03;
localparam [40:1] PHY_ENABLE_04_REG = PHY_ENABLE_04;
localparam [40:1] PHY_ENABLE_05_REG = PHY_ENABLE_05;
localparam [40:1] PHY_ENABLE_06_REG = PHY_ENABLE_06;
localparam [40:1] PHY_ENABLE_07_REG = PHY_ENABLE_07;
localparam [40:1] PHY_ENABLE_08_REG = PHY_ENABLE_08;
localparam [40:1] PHY_ENABLE_09_REG = PHY_ENABLE_09;
localparam [40:1] PHY_ENABLE_10_REG = PHY_ENABLE_10;
localparam [40:1] PHY_ENABLE_11_REG = PHY_ENABLE_11;
localparam [40:1] PHY_ENABLE_12_REG = PHY_ENABLE_12;
localparam [40:1] PHY_ENABLE_13_REG = PHY_ENABLE_13;
localparam [40:1] PHY_ENABLE_14_REG = PHY_ENABLE_14;
localparam [40:1] PHY_ENABLE_15_REG = PHY_ENABLE_15;
localparam [40:1] PHY_ENABLE_APB_REG = PHY_ENABLE_APB;
localparam [40:1] PHY_PCLK_INVERT_01_REG = PHY_PCLK_INVERT_01;
localparam [6:0] READ_PERCENT_00_REG = READ_PERCENT_00;
localparam [6:0] READ_PERCENT_01_REG = READ_PERCENT_01;
localparam [6:0] READ_PERCENT_02_REG = READ_PERCENT_02;
localparam [6:0] READ_PERCENT_03_REG = READ_PERCENT_03;
localparam [6:0] READ_PERCENT_04_REG = READ_PERCENT_04;
localparam [6:0] READ_PERCENT_05_REG = READ_PERCENT_05;
localparam [6:0] READ_PERCENT_06_REG = READ_PERCENT_06;
localparam [6:0] READ_PERCENT_07_REG = READ_PERCENT_07;
localparam [6:0] READ_PERCENT_08_REG = READ_PERCENT_08;
localparam [6:0] READ_PERCENT_09_REG = READ_PERCENT_09;
localparam [6:0] READ_PERCENT_10_REG = READ_PERCENT_10;
localparam [6:0] READ_PERCENT_11_REG = READ_PERCENT_11;
localparam [6:0] READ_PERCENT_12_REG = READ_PERCENT_12;
localparam [6:0] READ_PERCENT_13_REG = READ_PERCENT_13;
localparam [6:0] READ_PERCENT_14_REG = READ_PERCENT_14;
localparam [6:0] READ_PERCENT_15_REG = READ_PERCENT_15;
localparam [152:1] SIM_DEVICE_REG = SIM_DEVICE;
localparam [0:0] STACK_LOCATION_REG = STACK_LOCATION;
localparam [40:1] SWITCH_ENABLE_REG = SWITCH_ENABLE;
localparam [6:0] WRITE_PERCENT_00_REG = WRITE_PERCENT_00;
localparam [6:0] WRITE_PERCENT_01_REG = WRITE_PERCENT_01;
localparam [6:0] WRITE_PERCENT_02_REG = WRITE_PERCENT_02;
localparam [6:0] WRITE_PERCENT_03_REG = WRITE_PERCENT_03;
localparam [6:0] WRITE_PERCENT_04_REG = WRITE_PERCENT_04;
localparam [6:0] WRITE_PERCENT_05_REG = WRITE_PERCENT_05;
localparam [6:0] WRITE_PERCENT_06_REG = WRITE_PERCENT_06;
localparam [6:0] WRITE_PERCENT_07_REG = WRITE_PERCENT_07;
localparam [6:0] WRITE_PERCENT_08_REG = WRITE_PERCENT_08;
localparam [6:0] WRITE_PERCENT_09_REG = WRITE_PERCENT_09;
localparam [6:0] WRITE_PERCENT_10_REG = WRITE_PERCENT_10;
localparam [6:0] WRITE_PERCENT_11_REG = WRITE_PERCENT_11;
localparam [6:0] WRITE_PERCENT_12_REG = WRITE_PERCENT_12;
localparam [6:0] WRITE_PERCENT_13_REG = WRITE_PERCENT_13;
localparam [6:0] WRITE_PERCENT_14_REG = WRITE_PERCENT_14;
localparam [6:0] WRITE_PERCENT_15_REG = WRITE_PERCENT_15;
`endif
localparam [7:0] ANALOG_MUX_SEL_0_REG = 8'h00;
localparam [40:1] APB_BYPASS_EN_REG = "FALSE";
localparam [40:1] AXI_BYPASS_EN_REG = "FALSE";
localparam [40:1] BLI_TESTMODE_SEL_REG = "FALSE";
localparam [51:0] DBG_BYPASS_VAL_REG = 52'hFFFFFFFFFFFFF;
localparam [40:1] DEBUG_MODE_REG = "FALSE";
localparam [51:0] DFI_BYPASS_VAL_REG = 52'h0000000000000;
localparam [40:1] DLL_TESTMODE_SEL_0_REG = "FALSE";
localparam [40:1] IO_TESTMODE_SEL_0_REG = "FALSE";
localparam [40:1] MC_CSSD_SEL_0_REG = "FALSE";
localparam [40:1] MC_CSSD_SEL_1_REG = "FALSE";
localparam [40:1] MC_CSSD_SEL_2_REG = "FALSE";
localparam [40:1] MC_CSSD_SEL_3_REG = "FALSE";
localparam [40:1] MC_CSSD_SEL_4_REG = "FALSE";
localparam [40:1] MC_CSSD_SEL_5_REG = "FALSE";
localparam [40:1] MC_CSSD_SEL_6_REG = "FALSE";
localparam [40:1] MC_CSSD_SEL_7_REG = "FALSE";
localparam [40:1] MC_TESTMODE_SEL_0_REG = "FALSE";
localparam [40:1] MC_TESTMODE_SEL_1_REG = "FALSE";
localparam [40:1] MC_TESTMODE_SEL_2_REG = "FALSE";
localparam [40:1] MC_TESTMODE_SEL_3_REG = "FALSE";
localparam [40:1] MC_TESTMODE_SEL_4_REG = "FALSE";
localparam [40:1] MC_TESTMODE_SEL_5_REG = "FALSE";
localparam [40:1] MC_TESTMODE_SEL_6_REG = "FALSE";
localparam [40:1] MC_TESTMODE_SEL_7_REG = "FALSE";
localparam [40:1] PHY_CSSD_SEL_0_REG = "FALSE";
localparam [40:1] PHY_TESTMODE_SEL_0_REG = "FALSE";
localparam [40:1] SW_TESTMODE_SEL_0_REG = "FALSE";
`ifdef XIL_XECLIB
wire PHY_PCLK_INVERT_01_BIN;
`else
reg PHY_PCLK_INVERT_01_BIN;
`endif
reg attr_test;
reg attr_err;
tri0 glblGSR = glbl.GSR;
wire APB_0_PREADY_out;
wire APB_0_PSLVERR_out;
wire AXI_00_ARREADY_out;
wire AXI_00_AWREADY_out;
wire AXI_00_BVALID_out;
wire AXI_00_DFI_CLK_BUF_out;
wire AXI_00_DFI_INIT_COMPLETE_out;
wire AXI_00_DFI_PHYUPD_REQ_out;
wire AXI_00_DFI_PHY_LP_STATE_out;
wire AXI_00_DFI_RST_N_BUF_out;
wire AXI_00_RLAST_out;
wire AXI_00_RVALID_out;
wire AXI_00_WREADY_out;
wire AXI_01_ARREADY_out;
wire AXI_01_AWREADY_out;
wire AXI_01_BVALID_out;
wire AXI_01_DFI_CLK_BUF_out;
wire AXI_01_DFI_INIT_COMPLETE_out;
wire AXI_01_DFI_PHYUPD_REQ_out;
wire AXI_01_DFI_PHY_LP_STATE_out;
wire AXI_01_DFI_RST_N_BUF_out;
wire AXI_01_RLAST_out;
wire AXI_01_RVALID_out;
wire AXI_01_WREADY_out;
wire AXI_02_ARREADY_out;
wire AXI_02_AWREADY_out;
wire AXI_02_BVALID_out;
wire AXI_02_DFI_CLK_BUF_out;
wire AXI_02_DFI_INIT_COMPLETE_out;
wire AXI_02_DFI_PHYUPD_REQ_out;
wire AXI_02_DFI_PHY_LP_STATE_out;
wire AXI_02_DFI_RST_N_BUF_out;
wire AXI_02_RLAST_out;
wire AXI_02_RVALID_out;
wire AXI_02_WREADY_out;
wire AXI_03_ARREADY_out;
wire AXI_03_AWREADY_out;
wire AXI_03_BVALID_out;
wire AXI_03_DFI_CLK_BUF_out;
wire AXI_03_DFI_INIT_COMPLETE_out;
wire AXI_03_DFI_PHYUPD_REQ_out;
wire AXI_03_DFI_PHY_LP_STATE_out;
wire AXI_03_DFI_RST_N_BUF_out;
wire AXI_03_RLAST_out;
wire AXI_03_RVALID_out;
wire AXI_03_WREADY_out;
wire AXI_04_ARREADY_out;
wire AXI_04_AWREADY_out;
wire AXI_04_BVALID_out;
wire AXI_04_DFI_CLK_BUF_out;
wire AXI_04_DFI_INIT_COMPLETE_out;
wire AXI_04_DFI_PHYUPD_REQ_out;
wire AXI_04_DFI_PHY_LP_STATE_out;
wire AXI_04_DFI_RST_N_BUF_out;
wire AXI_04_RLAST_out;
wire AXI_04_RVALID_out;
wire AXI_04_WREADY_out;
wire AXI_05_ARREADY_out;
wire AXI_05_AWREADY_out;
wire AXI_05_BVALID_out;
wire AXI_05_DFI_CLK_BUF_out;
wire AXI_05_DFI_INIT_COMPLETE_out;
wire AXI_05_DFI_PHYUPD_REQ_out;
wire AXI_05_DFI_PHY_LP_STATE_out;
wire AXI_05_DFI_RST_N_BUF_out;
wire AXI_05_RLAST_out;
wire AXI_05_RVALID_out;
wire AXI_05_WREADY_out;
wire AXI_06_ARREADY_out;
wire AXI_06_AWREADY_out;
wire AXI_06_BVALID_out;
wire AXI_06_DFI_CLK_BUF_out;
wire AXI_06_DFI_INIT_COMPLETE_out;
wire AXI_06_DFI_PHYUPD_REQ_out;
wire AXI_06_DFI_PHY_LP_STATE_out;
wire AXI_06_DFI_RST_N_BUF_out;
wire AXI_06_RLAST_out;
wire AXI_06_RVALID_out;
wire AXI_06_WREADY_out;
wire AXI_07_ARREADY_out;
wire AXI_07_AWREADY_out;
wire AXI_07_BVALID_out;
wire AXI_07_DFI_CLK_BUF_out;
wire AXI_07_DFI_INIT_COMPLETE_out;
wire AXI_07_DFI_PHYUPD_REQ_out;
wire AXI_07_DFI_PHY_LP_STATE_out;
wire AXI_07_DFI_RST_N_BUF_out;
wire AXI_07_RLAST_out;
wire AXI_07_RVALID_out;
wire AXI_07_WREADY_out;
wire AXI_08_ARREADY_out;
wire AXI_08_AWREADY_out;
wire AXI_08_BVALID_out;
wire AXI_08_DFI_CLK_BUF_out;
wire AXI_08_DFI_INIT_COMPLETE_out;
wire AXI_08_DFI_PHYUPD_REQ_out;
wire AXI_08_DFI_PHY_LP_STATE_out;
wire AXI_08_DFI_RST_N_BUF_out;
wire AXI_08_RLAST_out;
wire AXI_08_RVALID_out;
wire AXI_08_WREADY_out;
wire AXI_09_ARREADY_out;
wire AXI_09_AWREADY_out;
wire AXI_09_BVALID_out;
wire AXI_09_DFI_CLK_BUF_out;
wire AXI_09_DFI_INIT_COMPLETE_out;
wire AXI_09_DFI_PHYUPD_REQ_out;
wire AXI_09_DFI_PHY_LP_STATE_out;
wire AXI_09_DFI_RST_N_BUF_out;
wire AXI_09_RLAST_out;
wire AXI_09_RVALID_out;
wire AXI_09_WREADY_out;
wire AXI_10_ARREADY_out;
wire AXI_10_AWREADY_out;
wire AXI_10_BVALID_out;
wire AXI_10_DFI_CLK_BUF_out;
wire AXI_10_DFI_INIT_COMPLETE_out;
wire AXI_10_DFI_PHYUPD_REQ_out;
wire AXI_10_DFI_PHY_LP_STATE_out;
wire AXI_10_DFI_RST_N_BUF_out;
wire AXI_10_RLAST_out;
wire AXI_10_RVALID_out;
wire AXI_10_WREADY_out;
wire AXI_11_ARREADY_out;
wire AXI_11_AWREADY_out;
wire AXI_11_BVALID_out;
wire AXI_11_DFI_CLK_BUF_out;
wire AXI_11_DFI_INIT_COMPLETE_out;
wire AXI_11_DFI_PHYUPD_REQ_out;
wire AXI_11_DFI_PHY_LP_STATE_out;
wire AXI_11_DFI_RST_N_BUF_out;
wire AXI_11_RLAST_out;
wire AXI_11_RVALID_out;
wire AXI_11_WREADY_out;
wire AXI_12_ARREADY_out;
wire AXI_12_AWREADY_out;
wire AXI_12_BVALID_out;
wire AXI_12_DFI_CLK_BUF_out;
wire AXI_12_DFI_INIT_COMPLETE_out;
wire AXI_12_DFI_PHYUPD_REQ_out;
wire AXI_12_DFI_PHY_LP_STATE_out;
wire AXI_12_DFI_RST_N_BUF_out;
wire AXI_12_RLAST_out;
wire AXI_12_RVALID_out;
wire AXI_12_WREADY_out;
wire AXI_13_ARREADY_out;
wire AXI_13_AWREADY_out;
wire AXI_13_BVALID_out;
wire AXI_13_DFI_CLK_BUF_out;
wire AXI_13_DFI_INIT_COMPLETE_out;
wire AXI_13_DFI_PHYUPD_REQ_out;
wire AXI_13_DFI_PHY_LP_STATE_out;
wire AXI_13_DFI_RST_N_BUF_out;
wire AXI_13_RLAST_out;
wire AXI_13_RVALID_out;
wire AXI_13_WREADY_out;
wire AXI_14_ARREADY_out;
wire AXI_14_AWREADY_out;
wire AXI_14_BVALID_out;
wire AXI_14_DFI_CLK_BUF_out;
wire AXI_14_DFI_INIT_COMPLETE_out;
wire AXI_14_DFI_PHYUPD_REQ_out;
wire AXI_14_DFI_PHY_LP_STATE_out;
wire AXI_14_DFI_RST_N_BUF_out;
wire AXI_14_RLAST_out;
wire AXI_14_RVALID_out;
wire AXI_14_WREADY_out;
wire AXI_15_ARREADY_out;
wire AXI_15_AWREADY_out;
wire AXI_15_BVALID_out;
wire AXI_15_DFI_CLK_BUF_out;
wire AXI_15_DFI_INIT_COMPLETE_out;
wire AXI_15_DFI_PHYUPD_REQ_out;
wire AXI_15_DFI_PHY_LP_STATE_out;
wire AXI_15_DFI_RST_N_BUF_out;
wire AXI_15_RLAST_out;
wire AXI_15_RVALID_out;
wire AXI_15_WREADY_out;
wire DRAM_0_STAT_CATTRIP_out;
wire [17:0] DBG_OUT_00_out;
wire [17:0] DBG_OUT_01_out;
wire [17:0] DBG_OUT_02_out;
wire [17:0] DBG_OUT_03_out;
wire [17:0] DBG_OUT_04_out;
wire [17:0] DBG_OUT_05_out;
wire [17:0] DBG_OUT_06_out;
wire [17:0] DBG_OUT_07_out;
wire [17:0] DBG_OUT_08_out;
wire [17:0] DBG_OUT_09_out;
wire [17:0] DBG_OUT_10_out;
wire [17:0] DBG_OUT_11_out;
wire [17:0] DBG_OUT_12_out;
wire [17:0] DBG_OUT_13_out;
wire [17:0] DBG_OUT_14_out;
wire [17:0] DBG_OUT_15_out;
wire [1:0] AXI_00_BRESP_out;
wire [1:0] AXI_00_DFI_AW_AERR_N_out;
wire [1:0] AXI_00_DFI_DW_RDDATA_VALID_out;
wire [1:0] AXI_00_RRESP_out;
wire [1:0] AXI_01_BRESP_out;
wire [1:0] AXI_01_DFI_AW_AERR_N_out;
wire [1:0] AXI_01_DFI_DW_RDDATA_VALID_out;
wire [1:0] AXI_01_RRESP_out;
wire [1:0] AXI_02_BRESP_out;
wire [1:0] AXI_02_DFI_AW_AERR_N_out;
wire [1:0] AXI_02_DFI_DW_RDDATA_VALID_out;
wire [1:0] AXI_02_RRESP_out;
wire [1:0] AXI_03_BRESP_out;
wire [1:0] AXI_03_DFI_AW_AERR_N_out;
wire [1:0] AXI_03_DFI_DW_RDDATA_VALID_out;
wire [1:0] AXI_03_RRESP_out;
wire [1:0] AXI_04_BRESP_out;
wire [1:0] AXI_04_DFI_AW_AERR_N_out;
wire [1:0] AXI_04_DFI_DW_RDDATA_VALID_out;
wire [1:0] AXI_04_RRESP_out;
wire [1:0] AXI_05_BRESP_out;
wire [1:0] AXI_05_DFI_AW_AERR_N_out;
wire [1:0] AXI_05_DFI_DW_RDDATA_VALID_out;
wire [1:0] AXI_05_RRESP_out;
wire [1:0] AXI_06_BRESP_out;
wire [1:0] AXI_06_DFI_AW_AERR_N_out;
wire [1:0] AXI_06_DFI_DW_RDDATA_VALID_out;
wire [1:0] AXI_06_RRESP_out;
wire [1:0] AXI_07_BRESP_out;
wire [1:0] AXI_07_DFI_AW_AERR_N_out;
wire [1:0] AXI_07_DFI_DW_RDDATA_VALID_out;
wire [1:0] AXI_07_RRESP_out;
wire [1:0] AXI_08_BRESP_out;
wire [1:0] AXI_08_DFI_AW_AERR_N_out;
wire [1:0] AXI_08_DFI_DW_RDDATA_VALID_out;
wire [1:0] AXI_08_RRESP_out;
wire [1:0] AXI_09_BRESP_out;
wire [1:0] AXI_09_DFI_AW_AERR_N_out;
wire [1:0] AXI_09_DFI_DW_RDDATA_VALID_out;
wire [1:0] AXI_09_RRESP_out;
wire [1:0] AXI_10_BRESP_out;
wire [1:0] AXI_10_DFI_AW_AERR_N_out;
wire [1:0] AXI_10_DFI_DW_RDDATA_VALID_out;
wire [1:0] AXI_10_RRESP_out;
wire [1:0] AXI_11_BRESP_out;
wire [1:0] AXI_11_DFI_AW_AERR_N_out;
wire [1:0] AXI_11_DFI_DW_RDDATA_VALID_out;
wire [1:0] AXI_11_RRESP_out;
wire [1:0] AXI_12_BRESP_out;
wire [1:0] AXI_12_DFI_AW_AERR_N_out;
wire [1:0] AXI_12_DFI_DW_RDDATA_VALID_out;
wire [1:0] AXI_12_RRESP_out;
wire [1:0] AXI_13_BRESP_out;
wire [1:0] AXI_13_DFI_AW_AERR_N_out;
wire [1:0] AXI_13_DFI_DW_RDDATA_VALID_out;
wire [1:0] AXI_13_RRESP_out;
wire [1:0] AXI_14_BRESP_out;
wire [1:0] AXI_14_DFI_AW_AERR_N_out;
wire [1:0] AXI_14_DFI_DW_RDDATA_VALID_out;
wire [1:0] AXI_14_RRESP_out;
wire [1:0] AXI_15_BRESP_out;
wire [1:0] AXI_15_DFI_AW_AERR_N_out;
wire [1:0] AXI_15_DFI_DW_RDDATA_VALID_out;
wire [1:0] AXI_15_RRESP_out;
wire [1:0] DLL_SCAN_OUT_00_out;
wire [1:0] IO_SCAN_OUT_00_out;
wire [1:0] MC_SCAN_OUT_00_out;
wire [1:0] MC_SCAN_OUT_01_out;
wire [1:0] MC_SCAN_OUT_02_out;
wire [1:0] MC_SCAN_OUT_03_out;
wire [1:0] MC_SCAN_OUT_04_out;
wire [1:0] MC_SCAN_OUT_05_out;
wire [1:0] MC_SCAN_OUT_06_out;
wire [1:0] MC_SCAN_OUT_07_out;
wire [1:0] PHY_SCAN_OUT_00_out;
wire [1:0] STATUS_00_out;
wire [1:0] STATUS_01_out;
wire [1:0] STATUS_02_out;
wire [1:0] STATUS_03_out;
wire [1:0] STATUS_04_out;
wire [1:0] STATUS_05_out;
wire [1:0] STATUS_06_out;
wire [1:0] STATUS_07_out;
wire [1:0] SW_SCAN_OUT_00_out;
wire [1:0] SW_SCAN_OUT_01_out;
wire [1:0] SW_SCAN_OUT_02_out;
wire [1:0] SW_SCAN_OUT_03_out;
wire [20:0] AXI_00_DFI_DW_RDDATA_DBI_out;
wire [20:0] AXI_01_DFI_DW_RDDATA_DBI_out;
wire [20:0] AXI_02_DFI_DW_RDDATA_DBI_out;
wire [20:0] AXI_03_DFI_DW_RDDATA_DBI_out;
wire [20:0] AXI_04_DFI_DW_RDDATA_DBI_out;
wire [20:0] AXI_05_DFI_DW_RDDATA_DBI_out;
wire [20:0] AXI_06_DFI_DW_RDDATA_DBI_out;
wire [20:0] AXI_07_DFI_DW_RDDATA_DBI_out;
wire [20:0] AXI_08_DFI_DW_RDDATA_DBI_out;
wire [20:0] AXI_09_DFI_DW_RDDATA_DBI_out;
wire [20:0] AXI_10_DFI_DW_RDDATA_DBI_out;
wire [20:0] AXI_11_DFI_DW_RDDATA_DBI_out;
wire [20:0] AXI_12_DFI_DW_RDDATA_DBI_out;
wire [20:0] AXI_13_DFI_DW_RDDATA_DBI_out;
wire [20:0] AXI_14_DFI_DW_RDDATA_DBI_out;
wire [20:0] AXI_15_DFI_DW_RDDATA_DBI_out;
wire [255:0] AXI_00_RDATA_out;
wire [255:0] AXI_01_RDATA_out;
wire [255:0] AXI_02_RDATA_out;
wire [255:0] AXI_03_RDATA_out;
wire [255:0] AXI_04_RDATA_out;
wire [255:0] AXI_05_RDATA_out;
wire [255:0] AXI_06_RDATA_out;
wire [255:0] AXI_07_RDATA_out;
wire [255:0] AXI_08_RDATA_out;
wire [255:0] AXI_09_RDATA_out;
wire [255:0] AXI_10_RDATA_out;
wire [255:0] AXI_11_RDATA_out;
wire [255:0] AXI_12_RDATA_out;
wire [255:0] AXI_13_RDATA_out;
wire [255:0] AXI_14_RDATA_out;
wire [255:0] AXI_15_RDATA_out;
wire [2:0] DRAM_0_STAT_TEMP_out;
wire [31:0] APB_0_PRDATA_out;
wire [31:0] AXI_00_RDATA_PARITY_out;
wire [31:0] AXI_01_RDATA_PARITY_out;
wire [31:0] AXI_02_RDATA_PARITY_out;
wire [31:0] AXI_03_RDATA_PARITY_out;
wire [31:0] AXI_04_RDATA_PARITY_out;
wire [31:0] AXI_05_RDATA_PARITY_out;
wire [31:0] AXI_06_RDATA_PARITY_out;
wire [31:0] AXI_07_RDATA_PARITY_out;
wire [31:0] AXI_08_RDATA_PARITY_out;
wire [31:0] AXI_09_RDATA_PARITY_out;
wire [31:0] AXI_10_RDATA_PARITY_out;
wire [31:0] AXI_11_RDATA_PARITY_out;
wire [31:0] AXI_12_RDATA_PARITY_out;
wire [31:0] AXI_13_RDATA_PARITY_out;
wire [31:0] AXI_14_RDATA_PARITY_out;
wire [31:0] AXI_15_RDATA_PARITY_out;
wire [5:0] AXI_00_BID_out;
wire [5:0] AXI_00_MC_STATUS_out;
wire [5:0] AXI_00_RID_out;
wire [5:0] AXI_01_BID_out;
wire [5:0] AXI_01_RID_out;
wire [5:0] AXI_02_BID_out;
wire [5:0] AXI_02_MC_STATUS_out;
wire [5:0] AXI_02_RID_out;
wire [5:0] AXI_03_BID_out;
wire [5:0] AXI_03_RID_out;
wire [5:0] AXI_04_BID_out;
wire [5:0] AXI_04_MC_STATUS_out;
wire [5:0] AXI_04_RID_out;
wire [5:0] AXI_05_BID_out;
wire [5:0] AXI_05_RID_out;
wire [5:0] AXI_06_BID_out;
wire [5:0] AXI_06_MC_STATUS_out;
wire [5:0] AXI_06_RID_out;
wire [5:0] AXI_07_BID_out;
wire [5:0] AXI_07_RID_out;
wire [5:0] AXI_08_BID_out;
wire [5:0] AXI_08_MC_STATUS_out;
wire [5:0] AXI_08_RID_out;
wire [5:0] AXI_09_BID_out;
wire [5:0] AXI_09_RID_out;
wire [5:0] AXI_10_BID_out;
wire [5:0] AXI_10_MC_STATUS_out;
wire [5:0] AXI_10_RID_out;
wire [5:0] AXI_11_BID_out;
wire [5:0] AXI_11_RID_out;
wire [5:0] AXI_12_BID_out;
wire [5:0] AXI_12_MC_STATUS_out;
wire [5:0] AXI_12_RID_out;
wire [5:0] AXI_13_BID_out;
wire [5:0] AXI_13_RID_out;
wire [5:0] AXI_14_BID_out;
wire [5:0] AXI_14_MC_STATUS_out;
wire [5:0] AXI_14_RID_out;
wire [5:0] AXI_15_BID_out;
wire [5:0] AXI_15_RID_out;
wire [7:0] AXI_00_DFI_DBI_BYTE_DISABLE_out;
wire [7:0] AXI_00_DFI_DW_RDDATA_DERR_out;
wire [7:0] AXI_00_PHY_STATUS_out;
wire [7:0] AXI_01_DFI_DBI_BYTE_DISABLE_out;
wire [7:0] AXI_01_DFI_DW_RDDATA_DERR_out;
wire [7:0] AXI_02_DFI_DBI_BYTE_DISABLE_out;
wire [7:0] AXI_02_DFI_DW_RDDATA_DERR_out;
wire [7:0] AXI_02_PHY_STATUS_out;
wire [7:0] AXI_03_DFI_DBI_BYTE_DISABLE_out;
wire [7:0] AXI_03_DFI_DW_RDDATA_DERR_out;
wire [7:0] AXI_04_DFI_DBI_BYTE_DISABLE_out;
wire [7:0] AXI_04_DFI_DW_RDDATA_DERR_out;
wire [7:0] AXI_04_PHY_STATUS_out;
wire [7:0] AXI_05_DFI_DBI_BYTE_DISABLE_out;
wire [7:0] AXI_05_DFI_DW_RDDATA_DERR_out;
wire [7:0] AXI_06_DFI_DBI_BYTE_DISABLE_out;
wire [7:0] AXI_06_DFI_DW_RDDATA_DERR_out;
wire [7:0] AXI_06_PHY_STATUS_out;
wire [7:0] AXI_07_DFI_DBI_BYTE_DISABLE_out;
wire [7:0] AXI_07_DFI_DW_RDDATA_DERR_out;
wire [7:0] AXI_08_DFI_DBI_BYTE_DISABLE_out;
wire [7:0] AXI_08_DFI_DW_RDDATA_DERR_out;
wire [7:0] AXI_08_PHY_STATUS_out;
wire [7:0] AXI_09_DFI_DBI_BYTE_DISABLE_out;
wire [7:0] AXI_09_DFI_DW_RDDATA_DERR_out;
wire [7:0] AXI_10_DFI_DBI_BYTE_DISABLE_out;
wire [7:0] AXI_10_DFI_DW_RDDATA_DERR_out;
wire [7:0] AXI_10_PHY_STATUS_out;
wire [7:0] AXI_11_DFI_DBI_BYTE_DISABLE_out;
wire [7:0] AXI_11_DFI_DW_RDDATA_DERR_out;
wire [7:0] AXI_12_DFI_DBI_BYTE_DISABLE_out;
wire [7:0] AXI_12_DFI_DW_RDDATA_DERR_out;
wire [7:0] AXI_12_PHY_STATUS_out;
wire [7:0] AXI_13_DFI_DBI_BYTE_DISABLE_out;
wire [7:0] AXI_13_DFI_DW_RDDATA_DERR_out;
wire [7:0] AXI_14_DFI_DBI_BYTE_DISABLE_out;
wire [7:0] AXI_14_DFI_DW_RDDATA_DERR_out;
wire [7:0] AXI_14_PHY_STATUS_out;
wire [7:0] AXI_15_DFI_DBI_BYTE_DISABLE_out;
wire [7:0] AXI_15_DFI_DW_RDDATA_DERR_out;
wire [7:0] BLI_SCAN_OUT_00_out;
wire [7:0] BLI_SCAN_OUT_01_out;
wire [7:0] BLI_SCAN_OUT_02_out;
wire [7:0] BLI_SCAN_OUT_03_out;
wire [7:0] BLI_SCAN_OUT_04_out;
wire [7:0] BLI_SCAN_OUT_05_out;
wire [7:0] BLI_SCAN_OUT_06_out;
wire [7:0] BLI_SCAN_OUT_07_out;
wire [7:0] BLI_SCAN_OUT_08_out;
wire [7:0] BLI_SCAN_OUT_09_out;
wire [7:0] BLI_SCAN_OUT_10_out;
wire [7:0] BLI_SCAN_OUT_11_out;
wire [7:0] BLI_SCAN_OUT_12_out;
wire [7:0] BLI_SCAN_OUT_13_out;
wire [7:0] BLI_SCAN_OUT_14_out;
wire [7:0] BLI_SCAN_OUT_15_out;
wire ANALOG_HBM_SEL_00_in;
wire APB_0_PCLK_in;
wire APB_0_PENABLE_in;
wire APB_0_PRESET_N_in;
wire APB_0_PSEL_in;
wire APB_0_PWRITE_in;
wire AXI_00_ACLK_in;
wire AXI_00_ARESET_N_in;
wire AXI_00_ARVALID_in;
wire AXI_00_AWVALID_in;
wire AXI_00_BREADY_in;
wire AXI_00_DFI_LP_PWR_X_REQ_in;
wire AXI_00_RREADY_in;
wire AXI_00_WLAST_in;
wire AXI_00_WVALID_in;
wire AXI_01_ACLK_in;
wire AXI_01_ARESET_N_in;
wire AXI_01_ARVALID_in;
wire AXI_01_AWVALID_in;
wire AXI_01_BREADY_in;
wire AXI_01_DFI_LP_PWR_X_REQ_in;
wire AXI_01_RREADY_in;
wire AXI_01_WLAST_in;
wire AXI_01_WVALID_in;
wire AXI_02_ACLK_in;
wire AXI_02_ARESET_N_in;
wire AXI_02_ARVALID_in;
wire AXI_02_AWVALID_in;
wire AXI_02_BREADY_in;
wire AXI_02_DFI_LP_PWR_X_REQ_in;
wire AXI_02_RREADY_in;
wire AXI_02_WLAST_in;
wire AXI_02_WVALID_in;
wire AXI_03_ACLK_in;
wire AXI_03_ARESET_N_in;
wire AXI_03_ARVALID_in;
wire AXI_03_AWVALID_in;
wire AXI_03_BREADY_in;
wire AXI_03_DFI_LP_PWR_X_REQ_in;
wire AXI_03_RREADY_in;
wire AXI_03_WLAST_in;
wire AXI_03_WVALID_in;
wire AXI_04_ACLK_in;
wire AXI_04_ARESET_N_in;
wire AXI_04_ARVALID_in;
wire AXI_04_AWVALID_in;
wire AXI_04_BREADY_in;
wire AXI_04_DFI_LP_PWR_X_REQ_in;
wire AXI_04_RREADY_in;
wire AXI_04_WLAST_in;
wire AXI_04_WVALID_in;
wire AXI_05_ACLK_in;
wire AXI_05_ARESET_N_in;
wire AXI_05_ARVALID_in;
wire AXI_05_AWVALID_in;
wire AXI_05_BREADY_in;
wire AXI_05_DFI_LP_PWR_X_REQ_in;
wire AXI_05_RREADY_in;
wire AXI_05_WLAST_in;
wire AXI_05_WVALID_in;
wire AXI_06_ACLK_in;
wire AXI_06_ARESET_N_in;
wire AXI_06_ARVALID_in;
wire AXI_06_AWVALID_in;
wire AXI_06_BREADY_in;
wire AXI_06_DFI_LP_PWR_X_REQ_in;
wire AXI_06_RREADY_in;
wire AXI_06_WLAST_in;
wire AXI_06_WVALID_in;
wire AXI_07_ACLK_in;
wire AXI_07_ARESET_N_in;
wire AXI_07_ARVALID_in;
wire AXI_07_AWVALID_in;
wire AXI_07_BREADY_in;
wire AXI_07_DFI_LP_PWR_X_REQ_in;
wire AXI_07_RREADY_in;
wire AXI_07_WLAST_in;
wire AXI_07_WVALID_in;
wire AXI_08_ACLK_in;
wire AXI_08_ARESET_N_in;
wire AXI_08_ARVALID_in;
wire AXI_08_AWVALID_in;
wire AXI_08_BREADY_in;
wire AXI_08_DFI_LP_PWR_X_REQ_in;
wire AXI_08_RREADY_in;
wire AXI_08_WLAST_in;
wire AXI_08_WVALID_in;
wire AXI_09_ACLK_in;
wire AXI_09_ARESET_N_in;
wire AXI_09_ARVALID_in;
wire AXI_09_AWVALID_in;
wire AXI_09_BREADY_in;
wire AXI_09_DFI_LP_PWR_X_REQ_in;
wire AXI_09_RREADY_in;
wire AXI_09_WLAST_in;
wire AXI_09_WVALID_in;
wire AXI_10_ACLK_in;
wire AXI_10_ARESET_N_in;
wire AXI_10_ARVALID_in;
wire AXI_10_AWVALID_in;
wire AXI_10_BREADY_in;
wire AXI_10_DFI_LP_PWR_X_REQ_in;
wire AXI_10_RREADY_in;
wire AXI_10_WLAST_in;
wire AXI_10_WVALID_in;
wire AXI_11_ACLK_in;
wire AXI_11_ARESET_N_in;
wire AXI_11_ARVALID_in;
wire AXI_11_AWVALID_in;
wire AXI_11_BREADY_in;
wire AXI_11_DFI_LP_PWR_X_REQ_in;
wire AXI_11_RREADY_in;
wire AXI_11_WLAST_in;
wire AXI_11_WVALID_in;
wire AXI_12_ACLK_in;
wire AXI_12_ARESET_N_in;
wire AXI_12_ARVALID_in;
wire AXI_12_AWVALID_in;
wire AXI_12_BREADY_in;
wire AXI_12_DFI_LP_PWR_X_REQ_in;
wire AXI_12_RREADY_in;
wire AXI_12_WLAST_in;
wire AXI_12_WVALID_in;
wire AXI_13_ACLK_in;
wire AXI_13_ARESET_N_in;
wire AXI_13_ARVALID_in;
wire AXI_13_AWVALID_in;
wire AXI_13_BREADY_in;
wire AXI_13_DFI_LP_PWR_X_REQ_in;
wire AXI_13_RREADY_in;
wire AXI_13_WLAST_in;
wire AXI_13_WVALID_in;
wire AXI_14_ACLK_in;
wire AXI_14_ARESET_N_in;
wire AXI_14_ARVALID_in;
wire AXI_14_AWVALID_in;
wire AXI_14_BREADY_in;
wire AXI_14_DFI_LP_PWR_X_REQ_in;
wire AXI_14_RREADY_in;
wire AXI_14_WLAST_in;
wire AXI_14_WVALID_in;
wire AXI_15_ACLK_in;
wire AXI_15_ARESET_N_in;
wire AXI_15_ARVALID_in;
wire AXI_15_AWVALID_in;
wire AXI_15_BREADY_in;
wire AXI_15_DFI_LP_PWR_X_REQ_in;
wire AXI_15_RREADY_in;
wire AXI_15_WLAST_in;
wire AXI_15_WVALID_in;
wire BLI_SCAN_ENABLE_00_in;
wire BLI_SCAN_ENABLE_01_in;
wire BLI_SCAN_ENABLE_02_in;
wire BLI_SCAN_ENABLE_03_in;
wire BLI_SCAN_ENABLE_04_in;
wire BLI_SCAN_ENABLE_05_in;
wire BLI_SCAN_ENABLE_06_in;
wire BLI_SCAN_ENABLE_07_in;
wire BLI_SCAN_ENABLE_08_in;
wire BLI_SCAN_ENABLE_09_in;
wire BLI_SCAN_ENABLE_10_in;
wire BLI_SCAN_ENABLE_11_in;
wire BLI_SCAN_ENABLE_12_in;
wire BLI_SCAN_ENABLE_13_in;
wire BLI_SCAN_ENABLE_14_in;
wire BLI_SCAN_ENABLE_15_in;
wire BSCAN_DRCK_in;
wire BSCAN_TCK_in;
wire DLL_SCAN_CK_00_in;
wire DLL_SCAN_ENABLE_00_in;
wire DLL_SCAN_MODE_00_in;
wire DLL_SCAN_RST_N_00_in;
wire HBM_REF_CLK_in;
wire IO_SCAN_CK_00_in;
wire IO_SCAN_ENABLE_00_in;
wire IO_SCAN_MODE_00_in;
wire IO_SCAN_RST_N_00_in;
wire MBIST_EN_00_in;
wire MBIST_EN_01_in;
wire MBIST_EN_02_in;
wire MBIST_EN_03_in;
wire MBIST_EN_04_in;
wire MBIST_EN_05_in;
wire MBIST_EN_06_in;
wire MBIST_EN_07_in;
wire MC_SCAN_CK_00_in;
wire MC_SCAN_CK_01_in;
wire MC_SCAN_CK_02_in;
wire MC_SCAN_CK_03_in;
wire MC_SCAN_CK_04_in;
wire MC_SCAN_CK_05_in;
wire MC_SCAN_CK_06_in;
wire MC_SCAN_CK_07_in;
wire MC_SCAN_ENABLE_00_in;
wire MC_SCAN_ENABLE_01_in;
wire MC_SCAN_ENABLE_02_in;
wire MC_SCAN_ENABLE_03_in;
wire MC_SCAN_ENABLE_04_in;
wire MC_SCAN_ENABLE_05_in;
wire MC_SCAN_ENABLE_06_in;
wire MC_SCAN_ENABLE_07_in;
wire MC_SCAN_MODE_00_in;
wire MC_SCAN_MODE_01_in;
wire MC_SCAN_MODE_02_in;
wire MC_SCAN_MODE_03_in;
wire MC_SCAN_MODE_04_in;
wire MC_SCAN_MODE_05_in;
wire MC_SCAN_MODE_06_in;
wire MC_SCAN_MODE_07_in;
wire MC_SCAN_RST_N_00_in;
wire MC_SCAN_RST_N_01_in;
wire MC_SCAN_RST_N_02_in;
wire MC_SCAN_RST_N_03_in;
wire MC_SCAN_RST_N_04_in;
wire MC_SCAN_RST_N_05_in;
wire MC_SCAN_RST_N_06_in;
wire MC_SCAN_RST_N_07_in;
wire PHY_SCAN_CK_00_in;
wire PHY_SCAN_ENABLE_00_in;
wire PHY_SCAN_MODE_00_in;
wire PHY_SCAN_RST_N_00_in;
wire SW_SCAN_CK_00_in;
wire SW_SCAN_ENABLE_00_in;
wire SW_SCAN_MODE_00_in;
wire SW_SCAN_RST_N_00_in;
wire [1:0] AXI_00_ARBURST_in;
wire [1:0] AXI_00_AWBURST_in;
wire [1:0] AXI_01_ARBURST_in;
wire [1:0] AXI_01_AWBURST_in;
wire [1:0] AXI_02_ARBURST_in;
wire [1:0] AXI_02_AWBURST_in;
wire [1:0] AXI_03_ARBURST_in;
wire [1:0] AXI_03_AWBURST_in;
wire [1:0] AXI_04_ARBURST_in;
wire [1:0] AXI_04_AWBURST_in;
wire [1:0] AXI_05_ARBURST_in;
wire [1:0] AXI_05_AWBURST_in;
wire [1:0] AXI_06_ARBURST_in;
wire [1:0] AXI_06_AWBURST_in;
wire [1:0] AXI_07_ARBURST_in;
wire [1:0] AXI_07_AWBURST_in;
wire [1:0] AXI_08_ARBURST_in;
wire [1:0] AXI_08_AWBURST_in;
wire [1:0] AXI_09_ARBURST_in;
wire [1:0] AXI_09_AWBURST_in;
wire [1:0] AXI_10_ARBURST_in;
wire [1:0] AXI_10_AWBURST_in;
wire [1:0] AXI_11_ARBURST_in;
wire [1:0] AXI_11_AWBURST_in;
wire [1:0] AXI_12_ARBURST_in;
wire [1:0] AXI_12_AWBURST_in;
wire [1:0] AXI_13_ARBURST_in;
wire [1:0] AXI_13_AWBURST_in;
wire [1:0] AXI_14_ARBURST_in;
wire [1:0] AXI_14_AWBURST_in;
wire [1:0] AXI_15_ARBURST_in;
wire [1:0] AXI_15_AWBURST_in;
wire [1:0] DLL_SCAN_IN_00_in;
wire [1:0] IO_SCAN_IN_00_in;
wire [1:0] MC_SCAN_IN_00_in;
wire [1:0] MC_SCAN_IN_01_in;
wire [1:0] MC_SCAN_IN_02_in;
wire [1:0] MC_SCAN_IN_03_in;
wire [1:0] MC_SCAN_IN_04_in;
wire [1:0] MC_SCAN_IN_05_in;
wire [1:0] MC_SCAN_IN_06_in;
wire [1:0] MC_SCAN_IN_07_in;
wire [1:0] PHY_SCAN_IN_00_in;
wire [1:0] SW_SCAN_IN_00_in;
wire [1:0] SW_SCAN_IN_01_in;
wire [1:0] SW_SCAN_IN_02_in;
wire [1:0] SW_SCAN_IN_03_in;
wire [21:0] APB_0_PADDR_in;
wire [23:0] DBG_IN_00_in;
wire [23:0] DBG_IN_01_in;
wire [23:0] DBG_IN_02_in;
wire [23:0] DBG_IN_03_in;
wire [23:0] DBG_IN_04_in;
wire [23:0] DBG_IN_05_in;
wire [23:0] DBG_IN_06_in;
wire [23:0] DBG_IN_07_in;
wire [23:0] DBG_IN_08_in;
wire [23:0] DBG_IN_09_in;
wire [23:0] DBG_IN_10_in;
wire [23:0] DBG_IN_11_in;
wire [23:0] DBG_IN_12_in;
wire [23:0] DBG_IN_13_in;
wire [23:0] DBG_IN_14_in;
wire [23:0] DBG_IN_15_in;
wire [255:0] AXI_00_WDATA_in;
wire [255:0] AXI_01_WDATA_in;
wire [255:0] AXI_02_WDATA_in;
wire [255:0] AXI_03_WDATA_in;
wire [255:0] AXI_04_WDATA_in;
wire [255:0] AXI_05_WDATA_in;
wire [255:0] AXI_06_WDATA_in;
wire [255:0] AXI_07_WDATA_in;
wire [255:0] AXI_08_WDATA_in;
wire [255:0] AXI_09_WDATA_in;
wire [255:0] AXI_10_WDATA_in;
wire [255:0] AXI_11_WDATA_in;
wire [255:0] AXI_12_WDATA_in;
wire [255:0] AXI_13_WDATA_in;
wire [255:0] AXI_14_WDATA_in;
wire [255:0] AXI_15_WDATA_in;
wire [2:0] AXI_00_ARSIZE_in;
wire [2:0] AXI_00_AWSIZE_in;
wire [2:0] AXI_01_ARSIZE_in;
wire [2:0] AXI_01_AWSIZE_in;
wire [2:0] AXI_02_ARSIZE_in;
wire [2:0] AXI_02_AWSIZE_in;
wire [2:0] AXI_03_ARSIZE_in;
wire [2:0] AXI_03_AWSIZE_in;
wire [2:0] AXI_04_ARSIZE_in;
wire [2:0] AXI_04_AWSIZE_in;
wire [2:0] AXI_05_ARSIZE_in;
wire [2:0] AXI_05_AWSIZE_in;
wire [2:0] AXI_06_ARSIZE_in;
wire [2:0] AXI_06_AWSIZE_in;
wire [2:0] AXI_07_ARSIZE_in;
wire [2:0] AXI_07_AWSIZE_in;
wire [2:0] AXI_08_ARSIZE_in;
wire [2:0] AXI_08_AWSIZE_in;
wire [2:0] AXI_09_ARSIZE_in;
wire [2:0] AXI_09_AWSIZE_in;
wire [2:0] AXI_10_ARSIZE_in;
wire [2:0] AXI_10_AWSIZE_in;
wire [2:0] AXI_11_ARSIZE_in;
wire [2:0] AXI_11_AWSIZE_in;
wire [2:0] AXI_12_ARSIZE_in;
wire [2:0] AXI_12_AWSIZE_in;
wire [2:0] AXI_13_ARSIZE_in;
wire [2:0] AXI_13_AWSIZE_in;
wire [2:0] AXI_14_ARSIZE_in;
wire [2:0] AXI_14_AWSIZE_in;
wire [2:0] AXI_15_ARSIZE_in;
wire [2:0] AXI_15_AWSIZE_in;
wire [31:0] APB_0_PWDATA_in;
wire [31:0] AXI_00_WDATA_PARITY_in;
wire [31:0] AXI_00_WSTRB_in;
wire [31:0] AXI_01_WDATA_PARITY_in;
wire [31:0] AXI_01_WSTRB_in;
wire [31:0] AXI_02_WDATA_PARITY_in;
wire [31:0] AXI_02_WSTRB_in;
wire [31:0] AXI_03_WDATA_PARITY_in;
wire [31:0] AXI_03_WSTRB_in;
wire [31:0] AXI_04_WDATA_PARITY_in;
wire [31:0] AXI_04_WSTRB_in;
wire [31:0] AXI_05_WDATA_PARITY_in;
wire [31:0] AXI_05_WSTRB_in;
wire [31:0] AXI_06_WDATA_PARITY_in;
wire [31:0] AXI_06_WSTRB_in;
wire [31:0] AXI_07_WDATA_PARITY_in;
wire [31:0] AXI_07_WSTRB_in;
wire [31:0] AXI_08_WDATA_PARITY_in;
wire [31:0] AXI_08_WSTRB_in;
wire [31:0] AXI_09_WDATA_PARITY_in;
wire [31:0] AXI_09_WSTRB_in;
wire [31:0] AXI_10_WDATA_PARITY_in;
wire [31:0] AXI_10_WSTRB_in;
wire [31:0] AXI_11_WDATA_PARITY_in;
wire [31:0] AXI_11_WSTRB_in;
wire [31:0] AXI_12_WDATA_PARITY_in;
wire [31:0] AXI_12_WSTRB_in;
wire [31:0] AXI_13_WDATA_PARITY_in;
wire [31:0] AXI_13_WSTRB_in;
wire [31:0] AXI_14_WDATA_PARITY_in;
wire [31:0] AXI_14_WSTRB_in;
wire [31:0] AXI_15_WDATA_PARITY_in;
wire [31:0] AXI_15_WSTRB_in;
wire [36:0] AXI_00_ARADDR_in;
wire [36:0] AXI_00_AWADDR_in;
wire [36:0] AXI_01_ARADDR_in;
wire [36:0] AXI_01_AWADDR_in;
wire [36:0] AXI_02_ARADDR_in;
wire [36:0] AXI_02_AWADDR_in;
wire [36:0] AXI_03_ARADDR_in;
wire [36:0] AXI_03_AWADDR_in;
wire [36:0] AXI_04_ARADDR_in;
wire [36:0] AXI_04_AWADDR_in;
wire [36:0] AXI_05_ARADDR_in;
wire [36:0] AXI_05_AWADDR_in;
wire [36:0] AXI_06_ARADDR_in;
wire [36:0] AXI_06_AWADDR_in;
wire [36:0] AXI_07_ARADDR_in;
wire [36:0] AXI_07_AWADDR_in;
wire [36:0] AXI_08_ARADDR_in;
wire [36:0] AXI_08_AWADDR_in;
wire [36:0] AXI_09_ARADDR_in;
wire [36:0] AXI_09_AWADDR_in;
wire [36:0] AXI_10_ARADDR_in;
wire [36:0] AXI_10_AWADDR_in;
wire [36:0] AXI_11_ARADDR_in;
wire [36:0] AXI_11_AWADDR_in;
wire [36:0] AXI_12_ARADDR_in;
wire [36:0] AXI_12_AWADDR_in;
wire [36:0] AXI_13_ARADDR_in;
wire [36:0] AXI_13_AWADDR_in;
wire [36:0] AXI_14_ARADDR_in;
wire [36:0] AXI_14_AWADDR_in;
wire [36:0] AXI_15_ARADDR_in;
wire [36:0] AXI_15_AWADDR_in;
wire [3:0] AXI_00_ARLEN_in;
wire [3:0] AXI_00_AWLEN_in;
wire [3:0] AXI_01_ARLEN_in;
wire [3:0] AXI_01_AWLEN_in;
wire [3:0] AXI_02_ARLEN_in;
wire [3:0] AXI_02_AWLEN_in;
wire [3:0] AXI_03_ARLEN_in;
wire [3:0] AXI_03_AWLEN_in;
wire [3:0] AXI_04_ARLEN_in;
wire [3:0] AXI_04_AWLEN_in;
wire [3:0] AXI_05_ARLEN_in;
wire [3:0] AXI_05_AWLEN_in;
wire [3:0] AXI_06_ARLEN_in;
wire [3:0] AXI_06_AWLEN_in;
wire [3:0] AXI_07_ARLEN_in;
wire [3:0] AXI_07_AWLEN_in;
wire [3:0] AXI_08_ARLEN_in;
wire [3:0] AXI_08_AWLEN_in;
wire [3:0] AXI_09_ARLEN_in;
wire [3:0] AXI_09_AWLEN_in;
wire [3:0] AXI_10_ARLEN_in;
wire [3:0] AXI_10_AWLEN_in;
wire [3:0] AXI_11_ARLEN_in;
wire [3:0] AXI_11_AWLEN_in;
wire [3:0] AXI_12_ARLEN_in;
wire [3:0] AXI_12_AWLEN_in;
wire [3:0] AXI_13_ARLEN_in;
wire [3:0] AXI_13_AWLEN_in;
wire [3:0] AXI_14_ARLEN_in;
wire [3:0] AXI_14_AWLEN_in;
wire [3:0] AXI_15_ARLEN_in;
wire [3:0] AXI_15_AWLEN_in;
wire [5:0] AXI_00_ARID_in;
wire [5:0] AXI_00_AWID_in;
wire [5:0] AXI_01_ARID_in;
wire [5:0] AXI_01_AWID_in;
wire [5:0] AXI_02_ARID_in;
wire [5:0] AXI_02_AWID_in;
wire [5:0] AXI_03_ARID_in;
wire [5:0] AXI_03_AWID_in;
wire [5:0] AXI_04_ARID_in;
wire [5:0] AXI_04_AWID_in;
wire [5:0] AXI_05_ARID_in;
wire [5:0] AXI_05_AWID_in;
wire [5:0] AXI_06_ARID_in;
wire [5:0] AXI_06_AWID_in;
wire [5:0] AXI_07_ARID_in;
wire [5:0] AXI_07_AWID_in;
wire [5:0] AXI_08_ARID_in;
wire [5:0] AXI_08_AWID_in;
wire [5:0] AXI_09_ARID_in;
wire [5:0] AXI_09_AWID_in;
wire [5:0] AXI_10_ARID_in;
wire [5:0] AXI_10_AWID_in;
wire [5:0] AXI_11_ARID_in;
wire [5:0] AXI_11_AWID_in;
wire [5:0] AXI_12_ARID_in;
wire [5:0] AXI_12_AWID_in;
wire [5:0] AXI_13_ARID_in;
wire [5:0] AXI_13_AWID_in;
wire [5:0] AXI_14_ARID_in;
wire [5:0] AXI_14_AWID_in;
wire [5:0] AXI_15_ARID_in;
wire [5:0] AXI_15_AWID_in;
wire [7:0] BLI_SCAN_IN_00_in;
wire [7:0] BLI_SCAN_IN_01_in;
wire [7:0] BLI_SCAN_IN_02_in;
wire [7:0] BLI_SCAN_IN_03_in;
wire [7:0] BLI_SCAN_IN_04_in;
wire [7:0] BLI_SCAN_IN_05_in;
wire [7:0] BLI_SCAN_IN_06_in;
wire [7:0] BLI_SCAN_IN_07_in;
wire [7:0] BLI_SCAN_IN_08_in;
wire [7:0] BLI_SCAN_IN_09_in;
wire [7:0] BLI_SCAN_IN_10_in;
wire [7:0] BLI_SCAN_IN_11_in;
wire [7:0] BLI_SCAN_IN_12_in;
wire [7:0] BLI_SCAN_IN_13_in;
wire [7:0] BLI_SCAN_IN_14_in;
wire [7:0] BLI_SCAN_IN_15_in;
assign APB_0_PRDATA = APB_0_PRDATA_out;
assign APB_0_PREADY = APB_0_PREADY_out;
assign APB_0_PSLVERR = APB_0_PSLVERR_out;
assign AXI_00_ARREADY = AXI_00_ARREADY_out;
assign AXI_00_AWREADY = AXI_00_AWREADY_out;
assign AXI_00_BID = AXI_00_BID_out;
assign AXI_00_BRESP = AXI_00_BRESP_out;
assign AXI_00_BVALID = AXI_00_BVALID_out;
assign AXI_00_DFI_AW_AERR_N = AXI_00_DFI_AW_AERR_N_out;
assign AXI_00_DFI_CLK_BUF = AXI_00_DFI_CLK_BUF_out;
assign AXI_00_DFI_DBI_BYTE_DISABLE = AXI_00_DFI_DBI_BYTE_DISABLE_out;
assign AXI_00_DFI_DW_RDDATA_DBI = AXI_00_DFI_DW_RDDATA_DBI_out;
assign AXI_00_DFI_DW_RDDATA_DERR = AXI_00_DFI_DW_RDDATA_DERR_out;
assign AXI_00_DFI_DW_RDDATA_VALID = AXI_00_DFI_DW_RDDATA_VALID_out;
assign AXI_00_DFI_INIT_COMPLETE = AXI_00_DFI_INIT_COMPLETE_out;
assign AXI_00_DFI_PHYUPD_REQ = AXI_00_DFI_PHYUPD_REQ_out;
assign AXI_00_DFI_PHY_LP_STATE = AXI_00_DFI_PHY_LP_STATE_out;
assign AXI_00_DFI_RST_N_BUF = AXI_00_DFI_RST_N_BUF_out;
assign AXI_00_MC_STATUS = AXI_00_MC_STATUS_out;
assign AXI_00_PHY_STATUS = AXI_00_PHY_STATUS_out;
assign AXI_00_RDATA = AXI_00_RDATA_out;
assign AXI_00_RDATA_PARITY = AXI_00_RDATA_PARITY_out;
assign AXI_00_RID = AXI_00_RID_out;
assign AXI_00_RLAST = AXI_00_RLAST_out;
assign AXI_00_RRESP = AXI_00_RRESP_out;
assign AXI_00_RVALID = AXI_00_RVALID_out;
assign AXI_00_WREADY = AXI_00_WREADY_out;
assign AXI_01_ARREADY = AXI_01_ARREADY_out;
assign AXI_01_AWREADY = AXI_01_AWREADY_out;
assign AXI_01_BID = AXI_01_BID_out;
assign AXI_01_BRESP = AXI_01_BRESP_out;
assign AXI_01_BVALID = AXI_01_BVALID_out;
assign AXI_01_DFI_AW_AERR_N = AXI_01_DFI_AW_AERR_N_out;
assign AXI_01_DFI_CLK_BUF = AXI_01_DFI_CLK_BUF_out;
assign AXI_01_DFI_DBI_BYTE_DISABLE = AXI_01_DFI_DBI_BYTE_DISABLE_out;
assign AXI_01_DFI_DW_RDDATA_DBI = AXI_01_DFI_DW_RDDATA_DBI_out;
assign AXI_01_DFI_DW_RDDATA_DERR = AXI_01_DFI_DW_RDDATA_DERR_out;
assign AXI_01_DFI_DW_RDDATA_VALID = AXI_01_DFI_DW_RDDATA_VALID_out;
assign AXI_01_DFI_INIT_COMPLETE = AXI_01_DFI_INIT_COMPLETE_out;
assign AXI_01_DFI_PHYUPD_REQ = AXI_01_DFI_PHYUPD_REQ_out;
assign AXI_01_DFI_PHY_LP_STATE = AXI_01_DFI_PHY_LP_STATE_out;
assign AXI_01_DFI_RST_N_BUF = AXI_01_DFI_RST_N_BUF_out;
assign AXI_01_RDATA = AXI_01_RDATA_out;
assign AXI_01_RDATA_PARITY = AXI_01_RDATA_PARITY_out;
assign AXI_01_RID = AXI_01_RID_out;
assign AXI_01_RLAST = AXI_01_RLAST_out;
assign AXI_01_RRESP = AXI_01_RRESP_out;
assign AXI_01_RVALID = AXI_01_RVALID_out;
assign AXI_01_WREADY = AXI_01_WREADY_out;
assign AXI_02_ARREADY = AXI_02_ARREADY_out;
assign AXI_02_AWREADY = AXI_02_AWREADY_out;
assign AXI_02_BID = AXI_02_BID_out;
assign AXI_02_BRESP = AXI_02_BRESP_out;
assign AXI_02_BVALID = AXI_02_BVALID_out;
assign AXI_02_DFI_AW_AERR_N = AXI_02_DFI_AW_AERR_N_out;
assign AXI_02_DFI_CLK_BUF = AXI_02_DFI_CLK_BUF_out;
assign AXI_02_DFI_DBI_BYTE_DISABLE = AXI_02_DFI_DBI_BYTE_DISABLE_out;
assign AXI_02_DFI_DW_RDDATA_DBI = AXI_02_DFI_DW_RDDATA_DBI_out;
assign AXI_02_DFI_DW_RDDATA_DERR = AXI_02_DFI_DW_RDDATA_DERR_out;
assign AXI_02_DFI_DW_RDDATA_VALID = AXI_02_DFI_DW_RDDATA_VALID_out;
assign AXI_02_DFI_INIT_COMPLETE = AXI_02_DFI_INIT_COMPLETE_out;
assign AXI_02_DFI_PHYUPD_REQ = AXI_02_DFI_PHYUPD_REQ_out;
assign AXI_02_DFI_PHY_LP_STATE = AXI_02_DFI_PHY_LP_STATE_out;
assign AXI_02_DFI_RST_N_BUF = AXI_02_DFI_RST_N_BUF_out;
assign AXI_02_MC_STATUS = AXI_02_MC_STATUS_out;
assign AXI_02_PHY_STATUS = AXI_02_PHY_STATUS_out;
assign AXI_02_RDATA = AXI_02_RDATA_out;
assign AXI_02_RDATA_PARITY = AXI_02_RDATA_PARITY_out;
assign AXI_02_RID = AXI_02_RID_out;
assign AXI_02_RLAST = AXI_02_RLAST_out;
assign AXI_02_RRESP = AXI_02_RRESP_out;
assign AXI_02_RVALID = AXI_02_RVALID_out;
assign AXI_02_WREADY = AXI_02_WREADY_out;
assign AXI_03_ARREADY = AXI_03_ARREADY_out;
assign AXI_03_AWREADY = AXI_03_AWREADY_out;
assign AXI_03_BID = AXI_03_BID_out;
assign AXI_03_BRESP = AXI_03_BRESP_out;
assign AXI_03_BVALID = AXI_03_BVALID_out;
assign AXI_03_DFI_AW_AERR_N = AXI_03_DFI_AW_AERR_N_out;
assign AXI_03_DFI_CLK_BUF = AXI_03_DFI_CLK_BUF_out;
assign AXI_03_DFI_DBI_BYTE_DISABLE = AXI_03_DFI_DBI_BYTE_DISABLE_out;
assign AXI_03_DFI_DW_RDDATA_DBI = AXI_03_DFI_DW_RDDATA_DBI_out;
assign AXI_03_DFI_DW_RDDATA_DERR = AXI_03_DFI_DW_RDDATA_DERR_out;
assign AXI_03_DFI_DW_RDDATA_VALID = AXI_03_DFI_DW_RDDATA_VALID_out;
assign AXI_03_DFI_INIT_COMPLETE = AXI_03_DFI_INIT_COMPLETE_out;
assign AXI_03_DFI_PHYUPD_REQ = AXI_03_DFI_PHYUPD_REQ_out;
assign AXI_03_DFI_PHY_LP_STATE = AXI_03_DFI_PHY_LP_STATE_out;
assign AXI_03_DFI_RST_N_BUF = AXI_03_DFI_RST_N_BUF_out;
assign AXI_03_RDATA = AXI_03_RDATA_out;
assign AXI_03_RDATA_PARITY = AXI_03_RDATA_PARITY_out;
assign AXI_03_RID = AXI_03_RID_out;
assign AXI_03_RLAST = AXI_03_RLAST_out;
assign AXI_03_RRESP = AXI_03_RRESP_out;
assign AXI_03_RVALID = AXI_03_RVALID_out;
assign AXI_03_WREADY = AXI_03_WREADY_out;
assign AXI_04_ARREADY = AXI_04_ARREADY_out;
assign AXI_04_AWREADY = AXI_04_AWREADY_out;
assign AXI_04_BID = AXI_04_BID_out;
assign AXI_04_BRESP = AXI_04_BRESP_out;
assign AXI_04_BVALID = AXI_04_BVALID_out;
assign AXI_04_DFI_AW_AERR_N = AXI_04_DFI_AW_AERR_N_out;
assign AXI_04_DFI_CLK_BUF = AXI_04_DFI_CLK_BUF_out;
assign AXI_04_DFI_DBI_BYTE_DISABLE = AXI_04_DFI_DBI_BYTE_DISABLE_out;
assign AXI_04_DFI_DW_RDDATA_DBI = AXI_04_DFI_DW_RDDATA_DBI_out;
assign AXI_04_DFI_DW_RDDATA_DERR = AXI_04_DFI_DW_RDDATA_DERR_out;
assign AXI_04_DFI_DW_RDDATA_VALID = AXI_04_DFI_DW_RDDATA_VALID_out;
assign AXI_04_DFI_INIT_COMPLETE = AXI_04_DFI_INIT_COMPLETE_out;
assign AXI_04_DFI_PHYUPD_REQ = AXI_04_DFI_PHYUPD_REQ_out;
assign AXI_04_DFI_PHY_LP_STATE = AXI_04_DFI_PHY_LP_STATE_out;
assign AXI_04_DFI_RST_N_BUF = AXI_04_DFI_RST_N_BUF_out;
assign AXI_04_MC_STATUS = AXI_04_MC_STATUS_out;
assign AXI_04_PHY_STATUS = AXI_04_PHY_STATUS_out;
assign AXI_04_RDATA = AXI_04_RDATA_out;
assign AXI_04_RDATA_PARITY = AXI_04_RDATA_PARITY_out;
assign AXI_04_RID = AXI_04_RID_out;
assign AXI_04_RLAST = AXI_04_RLAST_out;
assign AXI_04_RRESP = AXI_04_RRESP_out;
assign AXI_04_RVALID = AXI_04_RVALID_out;
assign AXI_04_WREADY = AXI_04_WREADY_out;
assign AXI_05_ARREADY = AXI_05_ARREADY_out;
assign AXI_05_AWREADY = AXI_05_AWREADY_out;
assign AXI_05_BID = AXI_05_BID_out;
assign AXI_05_BRESP = AXI_05_BRESP_out;
assign AXI_05_BVALID = AXI_05_BVALID_out;
assign AXI_05_DFI_AW_AERR_N = AXI_05_DFI_AW_AERR_N_out;
assign AXI_05_DFI_CLK_BUF = AXI_05_DFI_CLK_BUF_out;
assign AXI_05_DFI_DBI_BYTE_DISABLE = AXI_05_DFI_DBI_BYTE_DISABLE_out;
assign AXI_05_DFI_DW_RDDATA_DBI = AXI_05_DFI_DW_RDDATA_DBI_out;
assign AXI_05_DFI_DW_RDDATA_DERR = AXI_05_DFI_DW_RDDATA_DERR_out;
assign AXI_05_DFI_DW_RDDATA_VALID = AXI_05_DFI_DW_RDDATA_VALID_out;
assign AXI_05_DFI_INIT_COMPLETE = AXI_05_DFI_INIT_COMPLETE_out;
assign AXI_05_DFI_PHYUPD_REQ = AXI_05_DFI_PHYUPD_REQ_out;
assign AXI_05_DFI_PHY_LP_STATE = AXI_05_DFI_PHY_LP_STATE_out;
assign AXI_05_DFI_RST_N_BUF = AXI_05_DFI_RST_N_BUF_out;
assign AXI_05_RDATA = AXI_05_RDATA_out;
assign AXI_05_RDATA_PARITY = AXI_05_RDATA_PARITY_out;
assign AXI_05_RID = AXI_05_RID_out;
assign AXI_05_RLAST = AXI_05_RLAST_out;
assign AXI_05_RRESP = AXI_05_RRESP_out;
assign AXI_05_RVALID = AXI_05_RVALID_out;
assign AXI_05_WREADY = AXI_05_WREADY_out;
assign AXI_06_ARREADY = AXI_06_ARREADY_out;
assign AXI_06_AWREADY = AXI_06_AWREADY_out;
assign AXI_06_BID = AXI_06_BID_out;
assign AXI_06_BRESP = AXI_06_BRESP_out;
assign AXI_06_BVALID = AXI_06_BVALID_out;
assign AXI_06_DFI_AW_AERR_N = AXI_06_DFI_AW_AERR_N_out;
assign AXI_06_DFI_CLK_BUF = AXI_06_DFI_CLK_BUF_out;
assign AXI_06_DFI_DBI_BYTE_DISABLE = AXI_06_DFI_DBI_BYTE_DISABLE_out;
assign AXI_06_DFI_DW_RDDATA_DBI = AXI_06_DFI_DW_RDDATA_DBI_out;
assign AXI_06_DFI_DW_RDDATA_DERR = AXI_06_DFI_DW_RDDATA_DERR_out;
assign AXI_06_DFI_DW_RDDATA_VALID = AXI_06_DFI_DW_RDDATA_VALID_out;
assign AXI_06_DFI_INIT_COMPLETE = AXI_06_DFI_INIT_COMPLETE_out;
assign AXI_06_DFI_PHYUPD_REQ = AXI_06_DFI_PHYUPD_REQ_out;
assign AXI_06_DFI_PHY_LP_STATE = AXI_06_DFI_PHY_LP_STATE_out;
assign AXI_06_DFI_RST_N_BUF = AXI_06_DFI_RST_N_BUF_out;
assign AXI_06_MC_STATUS = AXI_06_MC_STATUS_out;
assign AXI_06_PHY_STATUS = AXI_06_PHY_STATUS_out;
assign AXI_06_RDATA = AXI_06_RDATA_out;
assign AXI_06_RDATA_PARITY = AXI_06_RDATA_PARITY_out;
assign AXI_06_RID = AXI_06_RID_out;
assign AXI_06_RLAST = AXI_06_RLAST_out;
assign AXI_06_RRESP = AXI_06_RRESP_out;
assign AXI_06_RVALID = AXI_06_RVALID_out;
assign AXI_06_WREADY = AXI_06_WREADY_out;
assign AXI_07_ARREADY = AXI_07_ARREADY_out;
assign AXI_07_AWREADY = AXI_07_AWREADY_out;
assign AXI_07_BID = AXI_07_BID_out;
assign AXI_07_BRESP = AXI_07_BRESP_out;
assign AXI_07_BVALID = AXI_07_BVALID_out;
assign AXI_07_DFI_AW_AERR_N = AXI_07_DFI_AW_AERR_N_out;
assign AXI_07_DFI_CLK_BUF = AXI_07_DFI_CLK_BUF_out;
assign AXI_07_DFI_DBI_BYTE_DISABLE = AXI_07_DFI_DBI_BYTE_DISABLE_out;
assign AXI_07_DFI_DW_RDDATA_DBI = AXI_07_DFI_DW_RDDATA_DBI_out;
assign AXI_07_DFI_DW_RDDATA_DERR = AXI_07_DFI_DW_RDDATA_DERR_out;
assign AXI_07_DFI_DW_RDDATA_VALID = AXI_07_DFI_DW_RDDATA_VALID_out;
assign AXI_07_DFI_INIT_COMPLETE = AXI_07_DFI_INIT_COMPLETE_out;
assign AXI_07_DFI_PHYUPD_REQ = AXI_07_DFI_PHYUPD_REQ_out;
assign AXI_07_DFI_PHY_LP_STATE = AXI_07_DFI_PHY_LP_STATE_out;
assign AXI_07_DFI_RST_N_BUF = AXI_07_DFI_RST_N_BUF_out;
assign AXI_07_RDATA = AXI_07_RDATA_out;
assign AXI_07_RDATA_PARITY = AXI_07_RDATA_PARITY_out;
assign AXI_07_RID = AXI_07_RID_out;
assign AXI_07_RLAST = AXI_07_RLAST_out;
assign AXI_07_RRESP = AXI_07_RRESP_out;
assign AXI_07_RVALID = AXI_07_RVALID_out;
assign AXI_07_WREADY = AXI_07_WREADY_out;
assign AXI_08_ARREADY = AXI_08_ARREADY_out;
assign AXI_08_AWREADY = AXI_08_AWREADY_out;
assign AXI_08_BID = AXI_08_BID_out;
assign AXI_08_BRESP = AXI_08_BRESP_out;
assign AXI_08_BVALID = AXI_08_BVALID_out;
assign AXI_08_DFI_AW_AERR_N = AXI_08_DFI_AW_AERR_N_out;
assign AXI_08_DFI_CLK_BUF = AXI_08_DFI_CLK_BUF_out;
assign AXI_08_DFI_DBI_BYTE_DISABLE = AXI_08_DFI_DBI_BYTE_DISABLE_out;
assign AXI_08_DFI_DW_RDDATA_DBI = AXI_08_DFI_DW_RDDATA_DBI_out;
assign AXI_08_DFI_DW_RDDATA_DERR = AXI_08_DFI_DW_RDDATA_DERR_out;
assign AXI_08_DFI_DW_RDDATA_VALID = AXI_08_DFI_DW_RDDATA_VALID_out;
assign AXI_08_DFI_INIT_COMPLETE = AXI_08_DFI_INIT_COMPLETE_out;
assign AXI_08_DFI_PHYUPD_REQ = AXI_08_DFI_PHYUPD_REQ_out;
assign AXI_08_DFI_PHY_LP_STATE = AXI_08_DFI_PHY_LP_STATE_out;
assign AXI_08_DFI_RST_N_BUF = AXI_08_DFI_RST_N_BUF_out;
assign AXI_08_MC_STATUS = AXI_08_MC_STATUS_out;
assign AXI_08_PHY_STATUS = AXI_08_PHY_STATUS_out;
assign AXI_08_RDATA = AXI_08_RDATA_out;
assign AXI_08_RDATA_PARITY = AXI_08_RDATA_PARITY_out;
assign AXI_08_RID = AXI_08_RID_out;
assign AXI_08_RLAST = AXI_08_RLAST_out;
assign AXI_08_RRESP = AXI_08_RRESP_out;
assign AXI_08_RVALID = AXI_08_RVALID_out;
assign AXI_08_WREADY = AXI_08_WREADY_out;
assign AXI_09_ARREADY = AXI_09_ARREADY_out;
assign AXI_09_AWREADY = AXI_09_AWREADY_out;
assign AXI_09_BID = AXI_09_BID_out;
assign AXI_09_BRESP = AXI_09_BRESP_out;
assign AXI_09_BVALID = AXI_09_BVALID_out;
assign AXI_09_DFI_AW_AERR_N = AXI_09_DFI_AW_AERR_N_out;
assign AXI_09_DFI_CLK_BUF = AXI_09_DFI_CLK_BUF_out;
assign AXI_09_DFI_DBI_BYTE_DISABLE = AXI_09_DFI_DBI_BYTE_DISABLE_out;
assign AXI_09_DFI_DW_RDDATA_DBI = AXI_09_DFI_DW_RDDATA_DBI_out;
assign AXI_09_DFI_DW_RDDATA_DERR = AXI_09_DFI_DW_RDDATA_DERR_out;
assign AXI_09_DFI_DW_RDDATA_VALID = AXI_09_DFI_DW_RDDATA_VALID_out;
assign AXI_09_DFI_INIT_COMPLETE = AXI_09_DFI_INIT_COMPLETE_out;
assign AXI_09_DFI_PHYUPD_REQ = AXI_09_DFI_PHYUPD_REQ_out;
assign AXI_09_DFI_PHY_LP_STATE = AXI_09_DFI_PHY_LP_STATE_out;
assign AXI_09_DFI_RST_N_BUF = AXI_09_DFI_RST_N_BUF_out;
assign AXI_09_RDATA = AXI_09_RDATA_out;
assign AXI_09_RDATA_PARITY = AXI_09_RDATA_PARITY_out;
assign AXI_09_RID = AXI_09_RID_out;
assign AXI_09_RLAST = AXI_09_RLAST_out;
assign AXI_09_RRESP = AXI_09_RRESP_out;
assign AXI_09_RVALID = AXI_09_RVALID_out;
assign AXI_09_WREADY = AXI_09_WREADY_out;
assign AXI_10_ARREADY = AXI_10_ARREADY_out;
assign AXI_10_AWREADY = AXI_10_AWREADY_out;
assign AXI_10_BID = AXI_10_BID_out;
assign AXI_10_BRESP = AXI_10_BRESP_out;
assign AXI_10_BVALID = AXI_10_BVALID_out;
assign AXI_10_DFI_AW_AERR_N = AXI_10_DFI_AW_AERR_N_out;
assign AXI_10_DFI_CLK_BUF = AXI_10_DFI_CLK_BUF_out;
assign AXI_10_DFI_DBI_BYTE_DISABLE = AXI_10_DFI_DBI_BYTE_DISABLE_out;
assign AXI_10_DFI_DW_RDDATA_DBI = AXI_10_DFI_DW_RDDATA_DBI_out;
assign AXI_10_DFI_DW_RDDATA_DERR = AXI_10_DFI_DW_RDDATA_DERR_out;
assign AXI_10_DFI_DW_RDDATA_VALID = AXI_10_DFI_DW_RDDATA_VALID_out;
assign AXI_10_DFI_INIT_COMPLETE = AXI_10_DFI_INIT_COMPLETE_out;
assign AXI_10_DFI_PHYUPD_REQ = AXI_10_DFI_PHYUPD_REQ_out;
assign AXI_10_DFI_PHY_LP_STATE = AXI_10_DFI_PHY_LP_STATE_out;
assign AXI_10_DFI_RST_N_BUF = AXI_10_DFI_RST_N_BUF_out;
assign AXI_10_MC_STATUS = AXI_10_MC_STATUS_out;
assign AXI_10_PHY_STATUS = AXI_10_PHY_STATUS_out;
assign AXI_10_RDATA = AXI_10_RDATA_out;
assign AXI_10_RDATA_PARITY = AXI_10_RDATA_PARITY_out;
assign AXI_10_RID = AXI_10_RID_out;
assign AXI_10_RLAST = AXI_10_RLAST_out;
assign AXI_10_RRESP = AXI_10_RRESP_out;
assign AXI_10_RVALID = AXI_10_RVALID_out;
assign AXI_10_WREADY = AXI_10_WREADY_out;
assign AXI_11_ARREADY = AXI_11_ARREADY_out;
assign AXI_11_AWREADY = AXI_11_AWREADY_out;
assign AXI_11_BID = AXI_11_BID_out;
assign AXI_11_BRESP = AXI_11_BRESP_out;
assign AXI_11_BVALID = AXI_11_BVALID_out;
assign AXI_11_DFI_AW_AERR_N = AXI_11_DFI_AW_AERR_N_out;
assign AXI_11_DFI_CLK_BUF = AXI_11_DFI_CLK_BUF_out;
assign AXI_11_DFI_DBI_BYTE_DISABLE = AXI_11_DFI_DBI_BYTE_DISABLE_out;
assign AXI_11_DFI_DW_RDDATA_DBI = AXI_11_DFI_DW_RDDATA_DBI_out;
assign AXI_11_DFI_DW_RDDATA_DERR = AXI_11_DFI_DW_RDDATA_DERR_out;
assign AXI_11_DFI_DW_RDDATA_VALID = AXI_11_DFI_DW_RDDATA_VALID_out;
assign AXI_11_DFI_INIT_COMPLETE = AXI_11_DFI_INIT_COMPLETE_out;
assign AXI_11_DFI_PHYUPD_REQ = AXI_11_DFI_PHYUPD_REQ_out;
assign AXI_11_DFI_PHY_LP_STATE = AXI_11_DFI_PHY_LP_STATE_out;
assign AXI_11_DFI_RST_N_BUF = AXI_11_DFI_RST_N_BUF_out;
assign AXI_11_RDATA = AXI_11_RDATA_out;
assign AXI_11_RDATA_PARITY = AXI_11_RDATA_PARITY_out;
assign AXI_11_RID = AXI_11_RID_out;
assign AXI_11_RLAST = AXI_11_RLAST_out;
assign AXI_11_RRESP = AXI_11_RRESP_out;
assign AXI_11_RVALID = AXI_11_RVALID_out;
assign AXI_11_WREADY = AXI_11_WREADY_out;
assign AXI_12_ARREADY = AXI_12_ARREADY_out;
assign AXI_12_AWREADY = AXI_12_AWREADY_out;
assign AXI_12_BID = AXI_12_BID_out;
assign AXI_12_BRESP = AXI_12_BRESP_out;
assign AXI_12_BVALID = AXI_12_BVALID_out;
assign AXI_12_DFI_AW_AERR_N = AXI_12_DFI_AW_AERR_N_out;
assign AXI_12_DFI_CLK_BUF = AXI_12_DFI_CLK_BUF_out;
assign AXI_12_DFI_DBI_BYTE_DISABLE = AXI_12_DFI_DBI_BYTE_DISABLE_out;
assign AXI_12_DFI_DW_RDDATA_DBI = AXI_12_DFI_DW_RDDATA_DBI_out;
assign AXI_12_DFI_DW_RDDATA_DERR = AXI_12_DFI_DW_RDDATA_DERR_out;
assign AXI_12_DFI_DW_RDDATA_VALID = AXI_12_DFI_DW_RDDATA_VALID_out;
assign AXI_12_DFI_INIT_COMPLETE = AXI_12_DFI_INIT_COMPLETE_out;
assign AXI_12_DFI_PHYUPD_REQ = AXI_12_DFI_PHYUPD_REQ_out;
assign AXI_12_DFI_PHY_LP_STATE = AXI_12_DFI_PHY_LP_STATE_out;
assign AXI_12_DFI_RST_N_BUF = AXI_12_DFI_RST_N_BUF_out;
assign AXI_12_MC_STATUS = AXI_12_MC_STATUS_out;
assign AXI_12_PHY_STATUS = AXI_12_PHY_STATUS_out;
assign AXI_12_RDATA = AXI_12_RDATA_out;
assign AXI_12_RDATA_PARITY = AXI_12_RDATA_PARITY_out;
assign AXI_12_RID = AXI_12_RID_out;
assign AXI_12_RLAST = AXI_12_RLAST_out;
assign AXI_12_RRESP = AXI_12_RRESP_out;
assign AXI_12_RVALID = AXI_12_RVALID_out;
assign AXI_12_WREADY = AXI_12_WREADY_out;
assign AXI_13_ARREADY = AXI_13_ARREADY_out;
assign AXI_13_AWREADY = AXI_13_AWREADY_out;
assign AXI_13_BID = AXI_13_BID_out;
assign AXI_13_BRESP = AXI_13_BRESP_out;
assign AXI_13_BVALID = AXI_13_BVALID_out;
assign AXI_13_DFI_AW_AERR_N = AXI_13_DFI_AW_AERR_N_out;
assign AXI_13_DFI_CLK_BUF = AXI_13_DFI_CLK_BUF_out;
assign AXI_13_DFI_DBI_BYTE_DISABLE = AXI_13_DFI_DBI_BYTE_DISABLE_out;
assign AXI_13_DFI_DW_RDDATA_DBI = AXI_13_DFI_DW_RDDATA_DBI_out;
assign AXI_13_DFI_DW_RDDATA_DERR = AXI_13_DFI_DW_RDDATA_DERR_out;
assign AXI_13_DFI_DW_RDDATA_VALID = AXI_13_DFI_DW_RDDATA_VALID_out;
assign AXI_13_DFI_INIT_COMPLETE = AXI_13_DFI_INIT_COMPLETE_out;
assign AXI_13_DFI_PHYUPD_REQ = AXI_13_DFI_PHYUPD_REQ_out;
assign AXI_13_DFI_PHY_LP_STATE = AXI_13_DFI_PHY_LP_STATE_out;
assign AXI_13_DFI_RST_N_BUF = AXI_13_DFI_RST_N_BUF_out;
assign AXI_13_RDATA = AXI_13_RDATA_out;
assign AXI_13_RDATA_PARITY = AXI_13_RDATA_PARITY_out;
assign AXI_13_RID = AXI_13_RID_out;
assign AXI_13_RLAST = AXI_13_RLAST_out;
assign AXI_13_RRESP = AXI_13_RRESP_out;
assign AXI_13_RVALID = AXI_13_RVALID_out;
assign AXI_13_WREADY = AXI_13_WREADY_out;
assign AXI_14_ARREADY = AXI_14_ARREADY_out;
assign AXI_14_AWREADY = AXI_14_AWREADY_out;
assign AXI_14_BID = AXI_14_BID_out;
assign AXI_14_BRESP = AXI_14_BRESP_out;
assign AXI_14_BVALID = AXI_14_BVALID_out;
assign AXI_14_DFI_AW_AERR_N = AXI_14_DFI_AW_AERR_N_out;
assign AXI_14_DFI_CLK_BUF = AXI_14_DFI_CLK_BUF_out;
assign AXI_14_DFI_DBI_BYTE_DISABLE = AXI_14_DFI_DBI_BYTE_DISABLE_out;
assign AXI_14_DFI_DW_RDDATA_DBI = AXI_14_DFI_DW_RDDATA_DBI_out;
assign AXI_14_DFI_DW_RDDATA_DERR = AXI_14_DFI_DW_RDDATA_DERR_out;
assign AXI_14_DFI_DW_RDDATA_VALID = AXI_14_DFI_DW_RDDATA_VALID_out;
assign AXI_14_DFI_INIT_COMPLETE = AXI_14_DFI_INIT_COMPLETE_out;
assign AXI_14_DFI_PHYUPD_REQ = AXI_14_DFI_PHYUPD_REQ_out;
assign AXI_14_DFI_PHY_LP_STATE = AXI_14_DFI_PHY_LP_STATE_out;
assign AXI_14_DFI_RST_N_BUF = AXI_14_DFI_RST_N_BUF_out;
assign AXI_14_MC_STATUS = AXI_14_MC_STATUS_out;
assign AXI_14_PHY_STATUS = AXI_14_PHY_STATUS_out;
assign AXI_14_RDATA = AXI_14_RDATA_out;
assign AXI_14_RDATA_PARITY = AXI_14_RDATA_PARITY_out;
assign AXI_14_RID = AXI_14_RID_out;
assign AXI_14_RLAST = AXI_14_RLAST_out;
assign AXI_14_RRESP = AXI_14_RRESP_out;
assign AXI_14_RVALID = AXI_14_RVALID_out;
assign AXI_14_WREADY = AXI_14_WREADY_out;
assign AXI_15_ARREADY = AXI_15_ARREADY_out;
assign AXI_15_AWREADY = AXI_15_AWREADY_out;
assign AXI_15_BID = AXI_15_BID_out;
assign AXI_15_BRESP = AXI_15_BRESP_out;
assign AXI_15_BVALID = AXI_15_BVALID_out;
assign AXI_15_DFI_AW_AERR_N = AXI_15_DFI_AW_AERR_N_out;
assign AXI_15_DFI_CLK_BUF = AXI_15_DFI_CLK_BUF_out;
assign AXI_15_DFI_DBI_BYTE_DISABLE = AXI_15_DFI_DBI_BYTE_DISABLE_out;
assign AXI_15_DFI_DW_RDDATA_DBI = AXI_15_DFI_DW_RDDATA_DBI_out;
assign AXI_15_DFI_DW_RDDATA_DERR = AXI_15_DFI_DW_RDDATA_DERR_out;
assign AXI_15_DFI_DW_RDDATA_VALID = AXI_15_DFI_DW_RDDATA_VALID_out;
assign AXI_15_DFI_INIT_COMPLETE = AXI_15_DFI_INIT_COMPLETE_out;
assign AXI_15_DFI_PHYUPD_REQ = AXI_15_DFI_PHYUPD_REQ_out;
assign AXI_15_DFI_PHY_LP_STATE = AXI_15_DFI_PHY_LP_STATE_out;
assign AXI_15_DFI_RST_N_BUF = AXI_15_DFI_RST_N_BUF_out;
assign AXI_15_RDATA = AXI_15_RDATA_out;
assign AXI_15_RDATA_PARITY = AXI_15_RDATA_PARITY_out;
assign AXI_15_RID = AXI_15_RID_out;
assign AXI_15_RLAST = AXI_15_RLAST_out;
assign AXI_15_RRESP = AXI_15_RRESP_out;
assign AXI_15_RVALID = AXI_15_RVALID_out;
assign AXI_15_WREADY = AXI_15_WREADY_out;
assign DRAM_0_STAT_CATTRIP = DRAM_0_STAT_CATTRIP_out;
assign DRAM_0_STAT_TEMP = DRAM_0_STAT_TEMP_out;
assign APB_0_PADDR_in = APB_0_PADDR;
assign APB_0_PCLK_in = APB_0_PCLK;
assign APB_0_PENABLE_in = APB_0_PENABLE;
assign APB_0_PRESET_N_in = APB_0_PRESET_N;
assign APB_0_PSEL_in = APB_0_PSEL;
assign APB_0_PWDATA_in = APB_0_PWDATA;
assign APB_0_PWRITE_in = APB_0_PWRITE;
assign AXI_00_ACLK_in = AXI_00_ACLK;
assign AXI_00_ARADDR_in = AXI_00_ARADDR;
assign AXI_00_ARBURST_in = AXI_00_ARBURST;
assign AXI_00_ARESET_N_in = AXI_00_ARESET_N;
assign AXI_00_ARID_in = AXI_00_ARID;
assign AXI_00_ARLEN_in = AXI_00_ARLEN;
assign AXI_00_ARSIZE_in = AXI_00_ARSIZE;
assign AXI_00_ARVALID_in = AXI_00_ARVALID;
assign AXI_00_AWADDR_in = AXI_00_AWADDR;
assign AXI_00_AWBURST_in = AXI_00_AWBURST;
assign AXI_00_AWID_in = AXI_00_AWID;
assign AXI_00_AWLEN_in = AXI_00_AWLEN;
assign AXI_00_AWSIZE_in = AXI_00_AWSIZE;
assign AXI_00_AWVALID_in = AXI_00_AWVALID;
assign AXI_00_BREADY_in = AXI_00_BREADY;
assign AXI_00_DFI_LP_PWR_X_REQ_in = AXI_00_DFI_LP_PWR_X_REQ;
assign AXI_00_RREADY_in = AXI_00_RREADY;
assign AXI_00_WDATA_PARITY_in = AXI_00_WDATA_PARITY;
assign AXI_00_WDATA_in = AXI_00_WDATA;
assign AXI_00_WLAST_in = AXI_00_WLAST;
assign AXI_00_WSTRB_in = AXI_00_WSTRB;
assign AXI_00_WVALID_in = AXI_00_WVALID;
assign AXI_01_ACLK_in = AXI_01_ACLK;
assign AXI_01_ARADDR_in = AXI_01_ARADDR;
assign AXI_01_ARBURST_in = AXI_01_ARBURST;
assign AXI_01_ARESET_N_in = AXI_01_ARESET_N;
assign AXI_01_ARID_in = AXI_01_ARID;
assign AXI_01_ARLEN_in = AXI_01_ARLEN;
assign AXI_01_ARSIZE_in = AXI_01_ARSIZE;
assign AXI_01_ARVALID_in = AXI_01_ARVALID;
assign AXI_01_AWADDR_in = AXI_01_AWADDR;
assign AXI_01_AWBURST_in = AXI_01_AWBURST;
assign AXI_01_AWID_in = AXI_01_AWID;
assign AXI_01_AWLEN_in = AXI_01_AWLEN;
assign AXI_01_AWSIZE_in = AXI_01_AWSIZE;
assign AXI_01_AWVALID_in = AXI_01_AWVALID;
assign AXI_01_BREADY_in = AXI_01_BREADY;
assign AXI_01_DFI_LP_PWR_X_REQ_in = AXI_01_DFI_LP_PWR_X_REQ;
assign AXI_01_RREADY_in = AXI_01_RREADY;
assign AXI_01_WDATA_PARITY_in = AXI_01_WDATA_PARITY;
assign AXI_01_WDATA_in = AXI_01_WDATA;
assign AXI_01_WLAST_in = AXI_01_WLAST;
assign AXI_01_WSTRB_in = AXI_01_WSTRB;
assign AXI_01_WVALID_in = AXI_01_WVALID;
assign AXI_02_ACLK_in = AXI_02_ACLK;
assign AXI_02_ARADDR_in = AXI_02_ARADDR;
assign AXI_02_ARBURST_in = AXI_02_ARBURST;
assign AXI_02_ARESET_N_in = AXI_02_ARESET_N;
assign AXI_02_ARID_in = AXI_02_ARID;
assign AXI_02_ARLEN_in = AXI_02_ARLEN;
assign AXI_02_ARSIZE_in = AXI_02_ARSIZE;
assign AXI_02_ARVALID_in = AXI_02_ARVALID;
assign AXI_02_AWADDR_in = AXI_02_AWADDR;
assign AXI_02_AWBURST_in = AXI_02_AWBURST;
assign AXI_02_AWID_in = AXI_02_AWID;
assign AXI_02_AWLEN_in = AXI_02_AWLEN;
assign AXI_02_AWSIZE_in = AXI_02_AWSIZE;
assign AXI_02_AWVALID_in = AXI_02_AWVALID;
assign AXI_02_BREADY_in = AXI_02_BREADY;
assign AXI_02_DFI_LP_PWR_X_REQ_in = AXI_02_DFI_LP_PWR_X_REQ;
assign AXI_02_RREADY_in = AXI_02_RREADY;
assign AXI_02_WDATA_PARITY_in = AXI_02_WDATA_PARITY;
assign AXI_02_WDATA_in = AXI_02_WDATA;
assign AXI_02_WLAST_in = AXI_02_WLAST;
assign AXI_02_WSTRB_in = AXI_02_WSTRB;
assign AXI_02_WVALID_in = AXI_02_WVALID;
assign AXI_03_ACLK_in = AXI_03_ACLK;
assign AXI_03_ARADDR_in = AXI_03_ARADDR;
assign AXI_03_ARBURST_in = AXI_03_ARBURST;
assign AXI_03_ARESET_N_in = AXI_03_ARESET_N;
assign AXI_03_ARID_in = AXI_03_ARID;
assign AXI_03_ARLEN_in = AXI_03_ARLEN;
assign AXI_03_ARSIZE_in = AXI_03_ARSIZE;
assign AXI_03_ARVALID_in = AXI_03_ARVALID;
assign AXI_03_AWADDR_in = AXI_03_AWADDR;
assign AXI_03_AWBURST_in = AXI_03_AWBURST;
assign AXI_03_AWID_in = AXI_03_AWID;
assign AXI_03_AWLEN_in = AXI_03_AWLEN;
assign AXI_03_AWSIZE_in = AXI_03_AWSIZE;
assign AXI_03_AWVALID_in = AXI_03_AWVALID;
assign AXI_03_BREADY_in = AXI_03_BREADY;
assign AXI_03_DFI_LP_PWR_X_REQ_in = AXI_03_DFI_LP_PWR_X_REQ;
assign AXI_03_RREADY_in = AXI_03_RREADY;
assign AXI_03_WDATA_PARITY_in = AXI_03_WDATA_PARITY;
assign AXI_03_WDATA_in = AXI_03_WDATA;
assign AXI_03_WLAST_in = AXI_03_WLAST;
assign AXI_03_WSTRB_in = AXI_03_WSTRB;
assign AXI_03_WVALID_in = AXI_03_WVALID;
assign AXI_04_ACLK_in = AXI_04_ACLK;
assign AXI_04_ARADDR_in = AXI_04_ARADDR;
assign AXI_04_ARBURST_in = AXI_04_ARBURST;
assign AXI_04_ARESET_N_in = AXI_04_ARESET_N;
assign AXI_04_ARID_in = AXI_04_ARID;
assign AXI_04_ARLEN_in = AXI_04_ARLEN;
assign AXI_04_ARSIZE_in = AXI_04_ARSIZE;
assign AXI_04_ARVALID_in = AXI_04_ARVALID;
assign AXI_04_AWADDR_in = AXI_04_AWADDR;
assign AXI_04_AWBURST_in = AXI_04_AWBURST;
assign AXI_04_AWID_in = AXI_04_AWID;
assign AXI_04_AWLEN_in = AXI_04_AWLEN;
assign AXI_04_AWSIZE_in = AXI_04_AWSIZE;
assign AXI_04_AWVALID_in = AXI_04_AWVALID;
assign AXI_04_BREADY_in = AXI_04_BREADY;
assign AXI_04_DFI_LP_PWR_X_REQ_in = AXI_04_DFI_LP_PWR_X_REQ;
assign AXI_04_RREADY_in = AXI_04_RREADY;
assign AXI_04_WDATA_PARITY_in = AXI_04_WDATA_PARITY;
assign AXI_04_WDATA_in = AXI_04_WDATA;
assign AXI_04_WLAST_in = AXI_04_WLAST;
assign AXI_04_WSTRB_in = AXI_04_WSTRB;
assign AXI_04_WVALID_in = AXI_04_WVALID;
assign AXI_05_ACLK_in = AXI_05_ACLK;
assign AXI_05_ARADDR_in = AXI_05_ARADDR;
assign AXI_05_ARBURST_in = AXI_05_ARBURST;
assign AXI_05_ARESET_N_in = AXI_05_ARESET_N;
assign AXI_05_ARID_in = AXI_05_ARID;
assign AXI_05_ARLEN_in = AXI_05_ARLEN;
assign AXI_05_ARSIZE_in = AXI_05_ARSIZE;
assign AXI_05_ARVALID_in = AXI_05_ARVALID;
assign AXI_05_AWADDR_in = AXI_05_AWADDR;
assign AXI_05_AWBURST_in = AXI_05_AWBURST;
assign AXI_05_AWID_in = AXI_05_AWID;
assign AXI_05_AWLEN_in = AXI_05_AWLEN;
assign AXI_05_AWSIZE_in = AXI_05_AWSIZE;
assign AXI_05_AWVALID_in = AXI_05_AWVALID;
assign AXI_05_BREADY_in = AXI_05_BREADY;
assign AXI_05_DFI_LP_PWR_X_REQ_in = AXI_05_DFI_LP_PWR_X_REQ;
assign AXI_05_RREADY_in = AXI_05_RREADY;
assign AXI_05_WDATA_PARITY_in = AXI_05_WDATA_PARITY;
assign AXI_05_WDATA_in = AXI_05_WDATA;
assign AXI_05_WLAST_in = AXI_05_WLAST;
assign AXI_05_WSTRB_in = AXI_05_WSTRB;
assign AXI_05_WVALID_in = AXI_05_WVALID;
assign AXI_06_ACLK_in = AXI_06_ACLK;
assign AXI_06_ARADDR_in = AXI_06_ARADDR;
assign AXI_06_ARBURST_in = AXI_06_ARBURST;
assign AXI_06_ARESET_N_in = AXI_06_ARESET_N;
assign AXI_06_ARID_in = AXI_06_ARID;
assign AXI_06_ARLEN_in = AXI_06_ARLEN;
assign AXI_06_ARSIZE_in = AXI_06_ARSIZE;
assign AXI_06_ARVALID_in = AXI_06_ARVALID;
assign AXI_06_AWADDR_in = AXI_06_AWADDR;
assign AXI_06_AWBURST_in = AXI_06_AWBURST;
assign AXI_06_AWID_in = AXI_06_AWID;
assign AXI_06_AWLEN_in = AXI_06_AWLEN;
assign AXI_06_AWSIZE_in = AXI_06_AWSIZE;
assign AXI_06_AWVALID_in = AXI_06_AWVALID;
assign AXI_06_BREADY_in = AXI_06_BREADY;
assign AXI_06_DFI_LP_PWR_X_REQ_in = AXI_06_DFI_LP_PWR_X_REQ;
assign AXI_06_RREADY_in = AXI_06_RREADY;
assign AXI_06_WDATA_PARITY_in = AXI_06_WDATA_PARITY;
assign AXI_06_WDATA_in = AXI_06_WDATA;
assign AXI_06_WLAST_in = AXI_06_WLAST;
assign AXI_06_WSTRB_in = AXI_06_WSTRB;
assign AXI_06_WVALID_in = AXI_06_WVALID;
assign AXI_07_ACLK_in = AXI_07_ACLK;
assign AXI_07_ARADDR_in = AXI_07_ARADDR;
assign AXI_07_ARBURST_in = AXI_07_ARBURST;
assign AXI_07_ARESET_N_in = AXI_07_ARESET_N;
assign AXI_07_ARID_in = AXI_07_ARID;
assign AXI_07_ARLEN_in = AXI_07_ARLEN;
assign AXI_07_ARSIZE_in = AXI_07_ARSIZE;
assign AXI_07_ARVALID_in = AXI_07_ARVALID;
assign AXI_07_AWADDR_in = AXI_07_AWADDR;
assign AXI_07_AWBURST_in = AXI_07_AWBURST;
assign AXI_07_AWID_in = AXI_07_AWID;
assign AXI_07_AWLEN_in = AXI_07_AWLEN;
assign AXI_07_AWSIZE_in = AXI_07_AWSIZE;
assign AXI_07_AWVALID_in = AXI_07_AWVALID;
assign AXI_07_BREADY_in = AXI_07_BREADY;
assign AXI_07_DFI_LP_PWR_X_REQ_in = AXI_07_DFI_LP_PWR_X_REQ;
assign AXI_07_RREADY_in = AXI_07_RREADY;
assign AXI_07_WDATA_PARITY_in = AXI_07_WDATA_PARITY;
assign AXI_07_WDATA_in = AXI_07_WDATA;
assign AXI_07_WLAST_in = AXI_07_WLAST;
assign AXI_07_WSTRB_in = AXI_07_WSTRB;
assign AXI_07_WVALID_in = AXI_07_WVALID;
assign AXI_08_ACLK_in = AXI_08_ACLK;
assign AXI_08_ARADDR_in = AXI_08_ARADDR;
assign AXI_08_ARBURST_in = AXI_08_ARBURST;
assign AXI_08_ARESET_N_in = AXI_08_ARESET_N;
assign AXI_08_ARID_in = AXI_08_ARID;
assign AXI_08_ARLEN_in = AXI_08_ARLEN;
assign AXI_08_ARSIZE_in = AXI_08_ARSIZE;
assign AXI_08_ARVALID_in = AXI_08_ARVALID;
assign AXI_08_AWADDR_in = AXI_08_AWADDR;
assign AXI_08_AWBURST_in = AXI_08_AWBURST;
assign AXI_08_AWID_in = AXI_08_AWID;
assign AXI_08_AWLEN_in = AXI_08_AWLEN;
assign AXI_08_AWSIZE_in = AXI_08_AWSIZE;
assign AXI_08_AWVALID_in = AXI_08_AWVALID;
assign AXI_08_BREADY_in = AXI_08_BREADY;
assign AXI_08_DFI_LP_PWR_X_REQ_in = AXI_08_DFI_LP_PWR_X_REQ;
assign AXI_08_RREADY_in = AXI_08_RREADY;
assign AXI_08_WDATA_PARITY_in = AXI_08_WDATA_PARITY;
assign AXI_08_WDATA_in = AXI_08_WDATA;
assign AXI_08_WLAST_in = AXI_08_WLAST;
assign AXI_08_WSTRB_in = AXI_08_WSTRB;
assign AXI_08_WVALID_in = AXI_08_WVALID;
assign AXI_09_ACLK_in = AXI_09_ACLK;
assign AXI_09_ARADDR_in = AXI_09_ARADDR;
assign AXI_09_ARBURST_in = AXI_09_ARBURST;
assign AXI_09_ARESET_N_in = AXI_09_ARESET_N;
assign AXI_09_ARID_in = AXI_09_ARID;
assign AXI_09_ARLEN_in = AXI_09_ARLEN;
assign AXI_09_ARSIZE_in = AXI_09_ARSIZE;
assign AXI_09_ARVALID_in = AXI_09_ARVALID;
assign AXI_09_AWADDR_in = AXI_09_AWADDR;
assign AXI_09_AWBURST_in = AXI_09_AWBURST;
assign AXI_09_AWID_in = AXI_09_AWID;
assign AXI_09_AWLEN_in = AXI_09_AWLEN;
assign AXI_09_AWSIZE_in = AXI_09_AWSIZE;
assign AXI_09_AWVALID_in = AXI_09_AWVALID;
assign AXI_09_BREADY_in = AXI_09_BREADY;
assign AXI_09_DFI_LP_PWR_X_REQ_in = AXI_09_DFI_LP_PWR_X_REQ;
assign AXI_09_RREADY_in = AXI_09_RREADY;
assign AXI_09_WDATA_PARITY_in = AXI_09_WDATA_PARITY;
assign AXI_09_WDATA_in = AXI_09_WDATA;
assign AXI_09_WLAST_in = AXI_09_WLAST;
assign AXI_09_WSTRB_in = AXI_09_WSTRB;
assign AXI_09_WVALID_in = AXI_09_WVALID;
assign AXI_10_ACLK_in = AXI_10_ACLK;
assign AXI_10_ARADDR_in = AXI_10_ARADDR;
assign AXI_10_ARBURST_in = AXI_10_ARBURST;
assign AXI_10_ARESET_N_in = AXI_10_ARESET_N;
assign AXI_10_ARID_in = AXI_10_ARID;
assign AXI_10_ARLEN_in = AXI_10_ARLEN;
assign AXI_10_ARSIZE_in = AXI_10_ARSIZE;
assign AXI_10_ARVALID_in = AXI_10_ARVALID;
assign AXI_10_AWADDR_in = AXI_10_AWADDR;
assign AXI_10_AWBURST_in = AXI_10_AWBURST;
assign AXI_10_AWID_in = AXI_10_AWID;
assign AXI_10_AWLEN_in = AXI_10_AWLEN;
assign AXI_10_AWSIZE_in = AXI_10_AWSIZE;
assign AXI_10_AWVALID_in = AXI_10_AWVALID;
assign AXI_10_BREADY_in = AXI_10_BREADY;
assign AXI_10_DFI_LP_PWR_X_REQ_in = AXI_10_DFI_LP_PWR_X_REQ;
assign AXI_10_RREADY_in = AXI_10_RREADY;
assign AXI_10_WDATA_PARITY_in = AXI_10_WDATA_PARITY;
assign AXI_10_WDATA_in = AXI_10_WDATA;
assign AXI_10_WLAST_in = AXI_10_WLAST;
assign AXI_10_WSTRB_in = AXI_10_WSTRB;
assign AXI_10_WVALID_in = AXI_10_WVALID;
assign AXI_11_ACLK_in = AXI_11_ACLK;
assign AXI_11_ARADDR_in = AXI_11_ARADDR;
assign AXI_11_ARBURST_in = AXI_11_ARBURST;
assign AXI_11_ARESET_N_in = AXI_11_ARESET_N;
assign AXI_11_ARID_in = AXI_11_ARID;
assign AXI_11_ARLEN_in = AXI_11_ARLEN;
assign AXI_11_ARSIZE_in = AXI_11_ARSIZE;
assign AXI_11_ARVALID_in = AXI_11_ARVALID;
assign AXI_11_AWADDR_in = AXI_11_AWADDR;
assign AXI_11_AWBURST_in = AXI_11_AWBURST;
assign AXI_11_AWID_in = AXI_11_AWID;
assign AXI_11_AWLEN_in = AXI_11_AWLEN;
assign AXI_11_AWSIZE_in = AXI_11_AWSIZE;
assign AXI_11_AWVALID_in = AXI_11_AWVALID;
assign AXI_11_BREADY_in = AXI_11_BREADY;
assign AXI_11_DFI_LP_PWR_X_REQ_in = AXI_11_DFI_LP_PWR_X_REQ;
assign AXI_11_RREADY_in = AXI_11_RREADY;
assign AXI_11_WDATA_PARITY_in = AXI_11_WDATA_PARITY;
assign AXI_11_WDATA_in = AXI_11_WDATA;
assign AXI_11_WLAST_in = AXI_11_WLAST;
assign AXI_11_WSTRB_in = AXI_11_WSTRB;
assign AXI_11_WVALID_in = AXI_11_WVALID;
assign AXI_12_ACLK_in = AXI_12_ACLK;
assign AXI_12_ARADDR_in = AXI_12_ARADDR;
assign AXI_12_ARBURST_in = AXI_12_ARBURST;
assign AXI_12_ARESET_N_in = AXI_12_ARESET_N;
assign AXI_12_ARID_in = AXI_12_ARID;
assign AXI_12_ARLEN_in = AXI_12_ARLEN;
assign AXI_12_ARSIZE_in = AXI_12_ARSIZE;
assign AXI_12_ARVALID_in = AXI_12_ARVALID;
assign AXI_12_AWADDR_in = AXI_12_AWADDR;
assign AXI_12_AWBURST_in = AXI_12_AWBURST;
assign AXI_12_AWID_in = AXI_12_AWID;
assign AXI_12_AWLEN_in = AXI_12_AWLEN;
assign AXI_12_AWSIZE_in = AXI_12_AWSIZE;
assign AXI_12_AWVALID_in = AXI_12_AWVALID;
assign AXI_12_BREADY_in = AXI_12_BREADY;
assign AXI_12_DFI_LP_PWR_X_REQ_in = AXI_12_DFI_LP_PWR_X_REQ;
assign AXI_12_RREADY_in = AXI_12_RREADY;
assign AXI_12_WDATA_PARITY_in = AXI_12_WDATA_PARITY;
assign AXI_12_WDATA_in = AXI_12_WDATA;
assign AXI_12_WLAST_in = AXI_12_WLAST;
assign AXI_12_WSTRB_in = AXI_12_WSTRB;
assign AXI_12_WVALID_in = AXI_12_WVALID;
assign AXI_13_ACLK_in = AXI_13_ACLK;
assign AXI_13_ARADDR_in = AXI_13_ARADDR;
assign AXI_13_ARBURST_in = AXI_13_ARBURST;
assign AXI_13_ARESET_N_in = AXI_13_ARESET_N;
assign AXI_13_ARID_in = AXI_13_ARID;
assign AXI_13_ARLEN_in = AXI_13_ARLEN;
assign AXI_13_ARSIZE_in = AXI_13_ARSIZE;
assign AXI_13_ARVALID_in = AXI_13_ARVALID;
assign AXI_13_AWADDR_in = AXI_13_AWADDR;
assign AXI_13_AWBURST_in = AXI_13_AWBURST;
assign AXI_13_AWID_in = AXI_13_AWID;
assign AXI_13_AWLEN_in = AXI_13_AWLEN;
assign AXI_13_AWSIZE_in = AXI_13_AWSIZE;
assign AXI_13_AWVALID_in = AXI_13_AWVALID;
assign AXI_13_BREADY_in = AXI_13_BREADY;
assign AXI_13_DFI_LP_PWR_X_REQ_in = AXI_13_DFI_LP_PWR_X_REQ;
assign AXI_13_RREADY_in = AXI_13_RREADY;
assign AXI_13_WDATA_PARITY_in = AXI_13_WDATA_PARITY;
assign AXI_13_WDATA_in = AXI_13_WDATA;
assign AXI_13_WLAST_in = AXI_13_WLAST;
assign AXI_13_WSTRB_in = AXI_13_WSTRB;
assign AXI_13_WVALID_in = AXI_13_WVALID;
assign AXI_14_ACLK_in = AXI_14_ACLK;
assign AXI_14_ARADDR_in = AXI_14_ARADDR;
assign AXI_14_ARBURST_in = AXI_14_ARBURST;
assign AXI_14_ARESET_N_in = AXI_14_ARESET_N;
assign AXI_14_ARID_in = AXI_14_ARID;
assign AXI_14_ARLEN_in = AXI_14_ARLEN;
assign AXI_14_ARSIZE_in = AXI_14_ARSIZE;
assign AXI_14_ARVALID_in = AXI_14_ARVALID;
assign AXI_14_AWADDR_in = AXI_14_AWADDR;
assign AXI_14_AWBURST_in = AXI_14_AWBURST;
assign AXI_14_AWID_in = AXI_14_AWID;
assign AXI_14_AWLEN_in = AXI_14_AWLEN;
assign AXI_14_AWSIZE_in = AXI_14_AWSIZE;
assign AXI_14_AWVALID_in = AXI_14_AWVALID;
assign AXI_14_BREADY_in = AXI_14_BREADY;
assign AXI_14_DFI_LP_PWR_X_REQ_in = AXI_14_DFI_LP_PWR_X_REQ;
assign AXI_14_RREADY_in = AXI_14_RREADY;
assign AXI_14_WDATA_PARITY_in = AXI_14_WDATA_PARITY;
assign AXI_14_WDATA_in = AXI_14_WDATA;
assign AXI_14_WLAST_in = AXI_14_WLAST;
assign AXI_14_WSTRB_in = AXI_14_WSTRB;
assign AXI_14_WVALID_in = AXI_14_WVALID;
assign AXI_15_ACLK_in = AXI_15_ACLK;
assign AXI_15_ARADDR_in = AXI_15_ARADDR;
assign AXI_15_ARBURST_in = AXI_15_ARBURST;
assign AXI_15_ARESET_N_in = AXI_15_ARESET_N;
assign AXI_15_ARID_in = AXI_15_ARID;
assign AXI_15_ARLEN_in = AXI_15_ARLEN;
assign AXI_15_ARSIZE_in = AXI_15_ARSIZE;
assign AXI_15_ARVALID_in = AXI_15_ARVALID;
assign AXI_15_AWADDR_in = AXI_15_AWADDR;
assign AXI_15_AWBURST_in = AXI_15_AWBURST;
assign AXI_15_AWID_in = AXI_15_AWID;
assign AXI_15_AWLEN_in = AXI_15_AWLEN;
assign AXI_15_AWSIZE_in = AXI_15_AWSIZE;
assign AXI_15_AWVALID_in = AXI_15_AWVALID;
assign AXI_15_BREADY_in = AXI_15_BREADY;
assign AXI_15_DFI_LP_PWR_X_REQ_in = AXI_15_DFI_LP_PWR_X_REQ;
assign AXI_15_RREADY_in = AXI_15_RREADY;
assign AXI_15_WDATA_PARITY_in = AXI_15_WDATA_PARITY;
assign AXI_15_WDATA_in = AXI_15_WDATA;
assign AXI_15_WLAST_in = AXI_15_WLAST;
assign AXI_15_WSTRB_in = AXI_15_WSTRB;
assign AXI_15_WVALID_in = AXI_15_WVALID;
assign BSCAN_DRCK_in = BSCAN_DRCK;
assign BSCAN_TCK_in = BSCAN_TCK;
assign HBM_REF_CLK_in = HBM_REF_CLK;
assign MBIST_EN_00_in = MBIST_EN_00;
assign MBIST_EN_01_in = MBIST_EN_01;
assign MBIST_EN_02_in = MBIST_EN_02;
assign MBIST_EN_03_in = MBIST_EN_03;
assign MBIST_EN_04_in = MBIST_EN_04;
assign MBIST_EN_05_in = MBIST_EN_05;
assign MBIST_EN_06_in = MBIST_EN_06;
assign MBIST_EN_07_in = MBIST_EN_07;
`ifndef XIL_XECLIB
initial begin
trig_attr = 1'b0;
`ifdef XIL_ATTR_TEST
attr_test = 1'b1;
`else
attr_test = 1'b0;
`endif
attr_err = 1'b0;
#1;
trig_attr = ~trig_attr;
end
`endif
`ifndef XIL_XECLIB
always @ (trig_attr) begin
#1;
if ((attr_test == 1'b1) ||
((CLK_SEL_00_REG != "FALSE") &&
(CLK_SEL_00_REG != "TRUE"))) begin
$display("Error: [Unisim %s-105] CLK_SEL_00 attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, CLK_SEL_00_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((CLK_SEL_01_REG != "FALSE") &&
(CLK_SEL_01_REG != "TRUE"))) begin
$display("Error: [Unisim %s-106] CLK_SEL_01 attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, CLK_SEL_01_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((CLK_SEL_02_REG != "FALSE") &&
(CLK_SEL_02_REG != "TRUE"))) begin
$display("Error: [Unisim %s-107] CLK_SEL_02 attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, CLK_SEL_02_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((CLK_SEL_03_REG != "FALSE") &&
(CLK_SEL_03_REG != "TRUE"))) begin
$display("Error: [Unisim %s-108] CLK_SEL_03 attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, CLK_SEL_03_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((CLK_SEL_04_REG != "FALSE") &&
(CLK_SEL_04_REG != "TRUE"))) begin
$display("Error: [Unisim %s-109] CLK_SEL_04 attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, CLK_SEL_04_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((CLK_SEL_05_REG != "FALSE") &&
(CLK_SEL_05_REG != "TRUE"))) begin
$display("Error: [Unisim %s-110] CLK_SEL_05 attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, CLK_SEL_05_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((CLK_SEL_06_REG != "FALSE") &&
(CLK_SEL_06_REG != "TRUE"))) begin
$display("Error: [Unisim %s-111] CLK_SEL_06 attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, CLK_SEL_06_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((CLK_SEL_07_REG != "FALSE") &&
(CLK_SEL_07_REG != "TRUE"))) begin
$display("Error: [Unisim %s-112] CLK_SEL_07 attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, CLK_SEL_07_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((CLK_SEL_08_REG != "FALSE") &&
(CLK_SEL_08_REG != "TRUE"))) begin
$display("Error: [Unisim %s-113] CLK_SEL_08 attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, CLK_SEL_08_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((CLK_SEL_09_REG != "FALSE") &&
(CLK_SEL_09_REG != "TRUE"))) begin
$display("Error: [Unisim %s-114] CLK_SEL_09 attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, CLK_SEL_09_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((CLK_SEL_10_REG != "FALSE") &&
(CLK_SEL_10_REG != "TRUE"))) begin
$display("Error: [Unisim %s-115] CLK_SEL_10 attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, CLK_SEL_10_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((CLK_SEL_11_REG != "FALSE") &&
(CLK_SEL_11_REG != "TRUE"))) begin
$display("Error: [Unisim %s-116] CLK_SEL_11 attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, CLK_SEL_11_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((CLK_SEL_12_REG != "FALSE") &&
(CLK_SEL_12_REG != "TRUE"))) begin
$display("Error: [Unisim %s-117] CLK_SEL_12 attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, CLK_SEL_12_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((CLK_SEL_13_REG != "FALSE") &&
(CLK_SEL_13_REG != "TRUE"))) begin
$display("Error: [Unisim %s-118] CLK_SEL_13 attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, CLK_SEL_13_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((CLK_SEL_14_REG != "FALSE") &&
(CLK_SEL_14_REG != "TRUE"))) begin
$display("Error: [Unisim %s-119] CLK_SEL_14 attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, CLK_SEL_14_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((CLK_SEL_15_REG != "FALSE") &&
(CLK_SEL_15_REG != "TRUE"))) begin
$display("Error: [Unisim %s-120] CLK_SEL_15 attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, CLK_SEL_15_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((DATARATE_00_REG < 50) || (DATARATE_00_REG > 1800))) begin
$display("Error: [Unisim %s-121] DATARATE_00 attribute is set to %d. Legal values for this attribute are 50 to 1800. Instance: %m", MODULE_NAME, DATARATE_00_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((DATARATE_01_REG < 50) || (DATARATE_01_REG > 1800))) begin
$display("Error: [Unisim %s-122] DATARATE_01 attribute is set to %d. Legal values for this attribute are 50 to 1800. Instance: %m", MODULE_NAME, DATARATE_01_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((DATARATE_02_REG < 50) || (DATARATE_02_REG > 1800))) begin
$display("Error: [Unisim %s-123] DATARATE_02 attribute is set to %d. Legal values for this attribute are 50 to 1800. Instance: %m", MODULE_NAME, DATARATE_02_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((DATARATE_03_REG < 50) || (DATARATE_03_REG > 1800))) begin
$display("Error: [Unisim %s-124] DATARATE_03 attribute is set to %d. Legal values for this attribute are 50 to 1800. Instance: %m", MODULE_NAME, DATARATE_03_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((DATARATE_04_REG < 50) || (DATARATE_04_REG > 1800))) begin
$display("Error: [Unisim %s-125] DATARATE_04 attribute is set to %d. Legal values for this attribute are 50 to 1800. Instance: %m", MODULE_NAME, DATARATE_04_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((DATARATE_05_REG < 50) || (DATARATE_05_REG > 1800))) begin
$display("Error: [Unisim %s-126] DATARATE_05 attribute is set to %d. Legal values for this attribute are 50 to 1800. Instance: %m", MODULE_NAME, DATARATE_05_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((DATARATE_06_REG < 50) || (DATARATE_06_REG > 1800))) begin
$display("Error: [Unisim %s-127] DATARATE_06 attribute is set to %d. Legal values for this attribute are 50 to 1800. Instance: %m", MODULE_NAME, DATARATE_06_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((DATARATE_07_REG < 50) || (DATARATE_07_REG > 1800))) begin
$display("Error: [Unisim %s-128] DATARATE_07 attribute is set to %d. Legal values for this attribute are 50 to 1800. Instance: %m", MODULE_NAME, DATARATE_07_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((DA_LOCKOUT_REG != "FALSE") &&
(DA_LOCKOUT_REG != "TRUE"))) begin
$display("Error: [Unisim %s-129] DA_LOCKOUT attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, DA_LOCKOUT_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((MC_ENABLE_0_REG != "FALSE") &&
(MC_ENABLE_0_REG != "TRUE"))) begin
$display("Error: [Unisim %s-177] MC_ENABLE_0 attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, MC_ENABLE_0_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((MC_ENABLE_1_REG != "FALSE") &&
(MC_ENABLE_1_REG != "TRUE"))) begin
$display("Error: [Unisim %s-178] MC_ENABLE_1 attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, MC_ENABLE_1_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((MC_ENABLE_2_REG != "FALSE") &&
(MC_ENABLE_2_REG != "TRUE"))) begin
$display("Error: [Unisim %s-179] MC_ENABLE_2 attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, MC_ENABLE_2_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((MC_ENABLE_3_REG != "FALSE") &&
(MC_ENABLE_3_REG != "TRUE"))) begin
$display("Error: [Unisim %s-180] MC_ENABLE_3 attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, MC_ENABLE_3_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((MC_ENABLE_4_REG != "FALSE") &&
(MC_ENABLE_4_REG != "TRUE"))) begin
$display("Error: [Unisim %s-181] MC_ENABLE_4 attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, MC_ENABLE_4_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((MC_ENABLE_5_REG != "FALSE") &&
(MC_ENABLE_5_REG != "TRUE"))) begin
$display("Error: [Unisim %s-182] MC_ENABLE_5 attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, MC_ENABLE_5_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((MC_ENABLE_6_REG != "FALSE") &&
(MC_ENABLE_6_REG != "TRUE"))) begin
$display("Error: [Unisim %s-183] MC_ENABLE_6 attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, MC_ENABLE_6_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((MC_ENABLE_7_REG != "FALSE") &&
(MC_ENABLE_7_REG != "TRUE"))) begin
$display("Error: [Unisim %s-184] MC_ENABLE_7 attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, MC_ENABLE_7_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((MC_ENABLE_APB_REG != "FALSE") &&
(MC_ENABLE_APB_REG != "TRUE"))) begin
$display("Error: [Unisim %s-185] MC_ENABLE_APB attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, MC_ENABLE_APB_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((PAGEHIT_PERCENT_00_REG < 0) || (PAGEHIT_PERCENT_00_REG > 100))) begin
$display("Error: [Unisim %s-194] PAGEHIT_PERCENT_00 attribute is set to %d. Legal values for this attribute are 0 to 100. Instance: %m", MODULE_NAME, PAGEHIT_PERCENT_00_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((PHY_ENABLE_00_REG != "FALSE") &&
(PHY_ENABLE_00_REG != "TRUE"))) begin
$display("Error: [Unisim %s-196] PHY_ENABLE_00 attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, PHY_ENABLE_00_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((PHY_ENABLE_01_REG != "FALSE") &&
(PHY_ENABLE_01_REG != "TRUE"))) begin
$display("Error: [Unisim %s-197] PHY_ENABLE_01 attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, PHY_ENABLE_01_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((PHY_ENABLE_02_REG != "FALSE") &&
(PHY_ENABLE_02_REG != "TRUE"))) begin
$display("Error: [Unisim %s-198] PHY_ENABLE_02 attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, PHY_ENABLE_02_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((PHY_ENABLE_03_REG != "FALSE") &&
(PHY_ENABLE_03_REG != "TRUE"))) begin
$display("Error: [Unisim %s-199] PHY_ENABLE_03 attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, PHY_ENABLE_03_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((PHY_ENABLE_04_REG != "FALSE") &&
(PHY_ENABLE_04_REG != "TRUE"))) begin
$display("Error: [Unisim %s-200] PHY_ENABLE_04 attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, PHY_ENABLE_04_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((PHY_ENABLE_05_REG != "FALSE") &&
(PHY_ENABLE_05_REG != "TRUE"))) begin
$display("Error: [Unisim %s-201] PHY_ENABLE_05 attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, PHY_ENABLE_05_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((PHY_ENABLE_06_REG != "FALSE") &&
(PHY_ENABLE_06_REG != "TRUE"))) begin
$display("Error: [Unisim %s-202] PHY_ENABLE_06 attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, PHY_ENABLE_06_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((PHY_ENABLE_07_REG != "FALSE") &&
(PHY_ENABLE_07_REG != "TRUE"))) begin
$display("Error: [Unisim %s-203] PHY_ENABLE_07 attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, PHY_ENABLE_07_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((PHY_ENABLE_08_REG != "FALSE") &&
(PHY_ENABLE_08_REG != "TRUE"))) begin
$display("Error: [Unisim %s-204] PHY_ENABLE_08 attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, PHY_ENABLE_08_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((PHY_ENABLE_09_REG != "FALSE") &&
(PHY_ENABLE_09_REG != "TRUE"))) begin
$display("Error: [Unisim %s-205] PHY_ENABLE_09 attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, PHY_ENABLE_09_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((PHY_ENABLE_10_REG != "FALSE") &&
(PHY_ENABLE_10_REG != "TRUE"))) begin
$display("Error: [Unisim %s-206] PHY_ENABLE_10 attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, PHY_ENABLE_10_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((PHY_ENABLE_11_REG != "FALSE") &&
(PHY_ENABLE_11_REG != "TRUE"))) begin
$display("Error: [Unisim %s-207] PHY_ENABLE_11 attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, PHY_ENABLE_11_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((PHY_ENABLE_12_REG != "FALSE") &&
(PHY_ENABLE_12_REG != "TRUE"))) begin
$display("Error: [Unisim %s-208] PHY_ENABLE_12 attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, PHY_ENABLE_12_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((PHY_ENABLE_13_REG != "FALSE") &&
(PHY_ENABLE_13_REG != "TRUE"))) begin
$display("Error: [Unisim %s-209] PHY_ENABLE_13 attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, PHY_ENABLE_13_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((PHY_ENABLE_14_REG != "FALSE") &&
(PHY_ENABLE_14_REG != "TRUE"))) begin
$display("Error: [Unisim %s-210] PHY_ENABLE_14 attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, PHY_ENABLE_14_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((PHY_ENABLE_15_REG != "FALSE") &&
(PHY_ENABLE_15_REG != "TRUE"))) begin
$display("Error: [Unisim %s-211] PHY_ENABLE_15 attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, PHY_ENABLE_15_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((PHY_ENABLE_APB_REG != "FALSE") &&
(PHY_ENABLE_APB_REG != "TRUE"))) begin
$display("Error: [Unisim %s-212] PHY_ENABLE_APB attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, PHY_ENABLE_APB_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((PHY_PCLK_INVERT_01_REG != "FALSE") &&
(PHY_PCLK_INVERT_01_REG != "TRUE"))) begin
$display("Error: [Unisim %s-213] PHY_PCLK_INVERT_01 attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, PHY_PCLK_INVERT_01_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((READ_PERCENT_00_REG < 0) || (READ_PERCENT_00_REG > 100))) begin
$display("Error: [Unisim %s-215] READ_PERCENT_00 attribute is set to %d. Legal values for this attribute are 0 to 100. Instance: %m", MODULE_NAME, READ_PERCENT_00_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((READ_PERCENT_01_REG < 0) || (READ_PERCENT_01_REG > 100))) begin
$display("Error: [Unisim %s-216] READ_PERCENT_01 attribute is set to %d. Legal values for this attribute are 0 to 100. Instance: %m", MODULE_NAME, READ_PERCENT_01_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((READ_PERCENT_02_REG < 0) || (READ_PERCENT_02_REG > 100))) begin
$display("Error: [Unisim %s-217] READ_PERCENT_02 attribute is set to %d. Legal values for this attribute are 0 to 100. Instance: %m", MODULE_NAME, READ_PERCENT_02_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((READ_PERCENT_03_REG < 0) || (READ_PERCENT_03_REG > 100))) begin
$display("Error: [Unisim %s-218] READ_PERCENT_03 attribute is set to %d. Legal values for this attribute are 0 to 100. Instance: %m", MODULE_NAME, READ_PERCENT_03_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((READ_PERCENT_04_REG < 0) || (READ_PERCENT_04_REG > 100))) begin
$display("Error: [Unisim %s-219] READ_PERCENT_04 attribute is set to %d. Legal values for this attribute are 0 to 100. Instance: %m", MODULE_NAME, READ_PERCENT_04_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((READ_PERCENT_05_REG < 0) || (READ_PERCENT_05_REG > 100))) begin
$display("Error: [Unisim %s-220] READ_PERCENT_05 attribute is set to %d. Legal values for this attribute are 0 to 100. Instance: %m", MODULE_NAME, READ_PERCENT_05_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((READ_PERCENT_06_REG < 0) || (READ_PERCENT_06_REG > 100))) begin
$display("Error: [Unisim %s-221] READ_PERCENT_06 attribute is set to %d. Legal values for this attribute are 0 to 100. Instance: %m", MODULE_NAME, READ_PERCENT_06_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((READ_PERCENT_07_REG < 0) || (READ_PERCENT_07_REG > 100))) begin
$display("Error: [Unisim %s-222] READ_PERCENT_07 attribute is set to %d. Legal values for this attribute are 0 to 100. Instance: %m", MODULE_NAME, READ_PERCENT_07_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((READ_PERCENT_08_REG < 0) || (READ_PERCENT_08_REG > 100))) begin
$display("Error: [Unisim %s-223] READ_PERCENT_08 attribute is set to %d. Legal values for this attribute are 0 to 100. Instance: %m", MODULE_NAME, READ_PERCENT_08_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((READ_PERCENT_09_REG < 0) || (READ_PERCENT_09_REG > 100))) begin
$display("Error: [Unisim %s-224] READ_PERCENT_09 attribute is set to %d. Legal values for this attribute are 0 to 100. Instance: %m", MODULE_NAME, READ_PERCENT_09_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((READ_PERCENT_10_REG < 0) || (READ_PERCENT_10_REG > 100))) begin
$display("Error: [Unisim %s-225] READ_PERCENT_10 attribute is set to %d. Legal values for this attribute are 0 to 100. Instance: %m", MODULE_NAME, READ_PERCENT_10_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((READ_PERCENT_11_REG < 0) || (READ_PERCENT_11_REG > 100))) begin
$display("Error: [Unisim %s-226] READ_PERCENT_11 attribute is set to %d. Legal values for this attribute are 0 to 100. Instance: %m", MODULE_NAME, READ_PERCENT_11_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((READ_PERCENT_12_REG < 0) || (READ_PERCENT_12_REG > 100))) begin
$display("Error: [Unisim %s-227] READ_PERCENT_12 attribute is set to %d. Legal values for this attribute are 0 to 100. Instance: %m", MODULE_NAME, READ_PERCENT_12_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((READ_PERCENT_13_REG < 0) || (READ_PERCENT_13_REG > 100))) begin
$display("Error: [Unisim %s-228] READ_PERCENT_13 attribute is set to %d. Legal values for this attribute are 0 to 100. Instance: %m", MODULE_NAME, READ_PERCENT_13_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((READ_PERCENT_14_REG < 0) || (READ_PERCENT_14_REG > 100))) begin
$display("Error: [Unisim %s-229] READ_PERCENT_14 attribute is set to %d. Legal values for this attribute are 0 to 100. Instance: %m", MODULE_NAME, READ_PERCENT_14_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((READ_PERCENT_15_REG < 0) || (READ_PERCENT_15_REG > 100))) begin
$display("Error: [Unisim %s-230] READ_PERCENT_15 attribute is set to %d. Legal values for this attribute are 0 to 100. Instance: %m", MODULE_NAME, READ_PERCENT_15_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((SIM_DEVICE_REG != "ULTRASCALE_PLUS") &&
(SIM_DEVICE_REG != "ULTRASCALE_PLUS_ES1") &&
(SIM_DEVICE_REG != "ULTRASCALE_PLUS_ES2"))) begin
$display("Error: [Unisim %s-231] SIM_DEVICE attribute is set to %s. Legal values for this attribute are ULTRASCALE_PLUS, ULTRASCALE_PLUS_ES1 or ULTRASCALE_PLUS_ES2. Instance: %m", MODULE_NAME, SIM_DEVICE_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((STACK_LOCATION_REG != 0) &&
(STACK_LOCATION_REG != 1))) begin
$display("Error: [Unisim %s-232] STACK_LOCATION attribute is set to %d. Legal values for this attribute are 0 or 1. Instance: %m", MODULE_NAME, STACK_LOCATION_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((SWITCH_ENABLE_REG != "FALSE") &&
(SWITCH_ENABLE_REG != "TRUE"))) begin
$display("Error: [Unisim %s-233] SWITCH_ENABLE attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, SWITCH_ENABLE_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((WRITE_PERCENT_00_REG < 0) || (WRITE_PERCENT_00_REG > 100))) begin
$display("Error: [Unisim %s-235] WRITE_PERCENT_00 attribute is set to %d. Legal values for this attribute are 0 to 100. Instance: %m", MODULE_NAME, WRITE_PERCENT_00_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((WRITE_PERCENT_01_REG < 0) || (WRITE_PERCENT_01_REG > 100))) begin
$display("Error: [Unisim %s-236] WRITE_PERCENT_01 attribute is set to %d. Legal values for this attribute are 0 to 100. Instance: %m", MODULE_NAME, WRITE_PERCENT_01_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((WRITE_PERCENT_02_REG < 0) || (WRITE_PERCENT_02_REG > 100))) begin
$display("Error: [Unisim %s-237] WRITE_PERCENT_02 attribute is set to %d. Legal values for this attribute are 0 to 100. Instance: %m", MODULE_NAME, WRITE_PERCENT_02_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((WRITE_PERCENT_03_REG < 0) || (WRITE_PERCENT_03_REG > 100))) begin
$display("Error: [Unisim %s-238] WRITE_PERCENT_03 attribute is set to %d. Legal values for this attribute are 0 to 100. Instance: %m", MODULE_NAME, WRITE_PERCENT_03_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((WRITE_PERCENT_04_REG < 0) || (WRITE_PERCENT_04_REG > 100))) begin
$display("Error: [Unisim %s-239] WRITE_PERCENT_04 attribute is set to %d. Legal values for this attribute are 0 to 100. Instance: %m", MODULE_NAME, WRITE_PERCENT_04_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((WRITE_PERCENT_05_REG < 0) || (WRITE_PERCENT_05_REG > 100))) begin
$display("Error: [Unisim %s-240] WRITE_PERCENT_05 attribute is set to %d. Legal values for this attribute are 0 to 100. Instance: %m", MODULE_NAME, WRITE_PERCENT_05_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((WRITE_PERCENT_06_REG < 0) || (WRITE_PERCENT_06_REG > 100))) begin
$display("Error: [Unisim %s-241] WRITE_PERCENT_06 attribute is set to %d. Legal values for this attribute are 0 to 100. Instance: %m", MODULE_NAME, WRITE_PERCENT_06_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((WRITE_PERCENT_07_REG < 0) || (WRITE_PERCENT_07_REG > 100))) begin
$display("Error: [Unisim %s-242] WRITE_PERCENT_07 attribute is set to %d. Legal values for this attribute are 0 to 100. Instance: %m", MODULE_NAME, WRITE_PERCENT_07_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((WRITE_PERCENT_08_REG < 0) || (WRITE_PERCENT_08_REG > 100))) begin
$display("Error: [Unisim %s-243] WRITE_PERCENT_08 attribute is set to %d. Legal values for this attribute are 0 to 100. Instance: %m", MODULE_NAME, WRITE_PERCENT_08_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((WRITE_PERCENT_09_REG < 0) || (WRITE_PERCENT_09_REG > 100))) begin
$display("Error: [Unisim %s-244] WRITE_PERCENT_09 attribute is set to %d. Legal values for this attribute are 0 to 100. Instance: %m", MODULE_NAME, WRITE_PERCENT_09_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((WRITE_PERCENT_10_REG < 0) || (WRITE_PERCENT_10_REG > 100))) begin
$display("Error: [Unisim %s-245] WRITE_PERCENT_10 attribute is set to %d. Legal values for this attribute are 0 to 100. Instance: %m", MODULE_NAME, WRITE_PERCENT_10_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((WRITE_PERCENT_11_REG < 0) || (WRITE_PERCENT_11_REG > 100))) begin
$display("Error: [Unisim %s-246] WRITE_PERCENT_11 attribute is set to %d. Legal values for this attribute are 0 to 100. Instance: %m", MODULE_NAME, WRITE_PERCENT_11_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((WRITE_PERCENT_12_REG < 0) || (WRITE_PERCENT_12_REG > 100))) begin
$display("Error: [Unisim %s-247] WRITE_PERCENT_12 attribute is set to %d. Legal values for this attribute are 0 to 100. Instance: %m", MODULE_NAME, WRITE_PERCENT_12_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((WRITE_PERCENT_13_REG < 0) || (WRITE_PERCENT_13_REG > 100))) begin
$display("Error: [Unisim %s-248] WRITE_PERCENT_13 attribute is set to %d. Legal values for this attribute are 0 to 100. Instance: %m", MODULE_NAME, WRITE_PERCENT_13_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((WRITE_PERCENT_14_REG < 0) || (WRITE_PERCENT_14_REG > 100))) begin
$display("Error: [Unisim %s-249] WRITE_PERCENT_14 attribute is set to %d. Legal values for this attribute are 0 to 100. Instance: %m", MODULE_NAME, WRITE_PERCENT_14_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((WRITE_PERCENT_15_REG < 0) || (WRITE_PERCENT_15_REG > 100))) begin
$display("Error: [Unisim %s-250] WRITE_PERCENT_15 attribute is set to %d. Legal values for this attribute are 0 to 100. Instance: %m", MODULE_NAME, WRITE_PERCENT_15_REG);
attr_err = 1'b1;
end
if (attr_err == 1'b1) #1 $finish;
end
`endif
assign ANALOG_HBM_SEL_00_in = 1'b1; // tie off
assign BLI_SCAN_ENABLE_00_in = 1'b1; // tie off
assign BLI_SCAN_ENABLE_01_in = 1'b1; // tie off
assign BLI_SCAN_ENABLE_02_in = 1'b1; // tie off
assign BLI_SCAN_ENABLE_03_in = 1'b1; // tie off
assign BLI_SCAN_ENABLE_04_in = 1'b1; // tie off
assign BLI_SCAN_ENABLE_05_in = 1'b1; // tie off
assign BLI_SCAN_ENABLE_06_in = 1'b1; // tie off
assign BLI_SCAN_ENABLE_07_in = 1'b1; // tie off
assign BLI_SCAN_ENABLE_08_in = 1'b1; // tie off
assign BLI_SCAN_ENABLE_09_in = 1'b1; // tie off
assign BLI_SCAN_ENABLE_10_in = 1'b1; // tie off
assign BLI_SCAN_ENABLE_11_in = 1'b1; // tie off
assign BLI_SCAN_ENABLE_12_in = 1'b1; // tie off
assign BLI_SCAN_ENABLE_13_in = 1'b1; // tie off
assign BLI_SCAN_ENABLE_14_in = 1'b1; // tie off
assign BLI_SCAN_ENABLE_15_in = 1'b1; // tie off
assign BLI_SCAN_IN_00_in = 8'b11111111; // tie off
assign BLI_SCAN_IN_01_in = 8'b11111111; // tie off
assign BLI_SCAN_IN_02_in = 8'b11111111; // tie off
assign BLI_SCAN_IN_03_in = 8'b11111111; // tie off
assign BLI_SCAN_IN_04_in = 8'b11111111; // tie off
assign BLI_SCAN_IN_05_in = 8'b11111111; // tie off
assign BLI_SCAN_IN_06_in = 8'b11111111; // tie off
assign BLI_SCAN_IN_07_in = 8'b11111111; // tie off
assign BLI_SCAN_IN_08_in = 8'b11111111; // tie off
assign BLI_SCAN_IN_09_in = 8'b11111111; // tie off
assign BLI_SCAN_IN_10_in = 8'b11111111; // tie off
assign BLI_SCAN_IN_11_in = 8'b11111111; // tie off
assign BLI_SCAN_IN_12_in = 8'b11111111; // tie off
assign BLI_SCAN_IN_13_in = 8'b11111111; // tie off
assign BLI_SCAN_IN_14_in = 8'b11111111; // tie off
assign BLI_SCAN_IN_15_in = 8'b11111111; // tie off
assign DBG_IN_00_in = 24'b111111111111111111111111; // tie off
assign DBG_IN_01_in = 24'b111111111111111111111111; // tie off
assign DBG_IN_02_in = 24'b111111111111111111111111; // tie off
assign DBG_IN_03_in = 24'b111111111111111111111111; // tie off
assign DBG_IN_04_in = 24'b111111111111111111111111; // tie off
assign DBG_IN_05_in = 24'b111111111111111111111111; // tie off
assign DBG_IN_06_in = 24'b111111111111111111111111; // tie off
assign DBG_IN_07_in = 24'b111111111111111111111111; // tie off
assign DBG_IN_08_in = 24'b111111111111111111111111; // tie off
assign DBG_IN_09_in = 24'b111111111111111111111111; // tie off
assign DBG_IN_10_in = 24'b111111111111111111111111; // tie off
assign DBG_IN_11_in = 24'b111111111111111111111111; // tie off
assign DBG_IN_12_in = 24'b111111111111111111111111; // tie off
assign DBG_IN_13_in = 24'b111111111111111111111111; // tie off
assign DBG_IN_14_in = 24'b111111111111111111111111; // tie off
assign DBG_IN_15_in = 24'b111111111111111111111111; // tie off
assign DLL_SCAN_CK_00_in = 1'b1; // tie off
assign DLL_SCAN_ENABLE_00_in = 1'b1; // tie off
assign DLL_SCAN_IN_00_in = 2'b11; // tie off
assign DLL_SCAN_MODE_00_in = 1'b1; // tie off
assign DLL_SCAN_RST_N_00_in = 1'b1; // tie off
assign IO_SCAN_CK_00_in = 1'b1; // tie off
assign IO_SCAN_ENABLE_00_in = 1'b1; // tie off
assign IO_SCAN_IN_00_in = 2'b11; // tie off
assign IO_SCAN_MODE_00_in = 1'b1; // tie off
assign IO_SCAN_RST_N_00_in = 1'b1; // tie off
assign MC_SCAN_CK_00_in = 1'b1; // tie off
assign MC_SCAN_CK_01_in = 1'b1; // tie off
assign MC_SCAN_CK_02_in = 1'b1; // tie off
assign MC_SCAN_CK_03_in = 1'b1; // tie off
assign MC_SCAN_CK_04_in = 1'b1; // tie off
assign MC_SCAN_CK_05_in = 1'b1; // tie off
assign MC_SCAN_CK_06_in = 1'b1; // tie off
assign MC_SCAN_CK_07_in = 1'b1; // tie off
assign MC_SCAN_ENABLE_00_in = 1'b1; // tie off
assign MC_SCAN_ENABLE_01_in = 1'b1; // tie off
assign MC_SCAN_ENABLE_02_in = 1'b1; // tie off
assign MC_SCAN_ENABLE_03_in = 1'b1; // tie off
assign MC_SCAN_ENABLE_04_in = 1'b1; // tie off
assign MC_SCAN_ENABLE_05_in = 1'b1; // tie off
assign MC_SCAN_ENABLE_06_in = 1'b1; // tie off
assign MC_SCAN_ENABLE_07_in = 1'b1; // tie off
assign MC_SCAN_IN_00_in = 2'b11; // tie off
assign MC_SCAN_IN_01_in = 2'b11; // tie off
assign MC_SCAN_IN_02_in = 2'b11; // tie off
assign MC_SCAN_IN_03_in = 2'b11; // tie off
assign MC_SCAN_IN_04_in = 2'b11; // tie off
assign MC_SCAN_IN_05_in = 2'b11; // tie off
assign MC_SCAN_IN_06_in = 2'b11; // tie off
assign MC_SCAN_IN_07_in = 2'b11; // tie off
assign MC_SCAN_MODE_00_in = 1'b1; // tie off
assign MC_SCAN_MODE_01_in = 1'b1; // tie off
assign MC_SCAN_MODE_02_in = 1'b1; // tie off
assign MC_SCAN_MODE_03_in = 1'b1; // tie off
assign MC_SCAN_MODE_04_in = 1'b1; // tie off
assign MC_SCAN_MODE_05_in = 1'b1; // tie off
assign MC_SCAN_MODE_06_in = 1'b1; // tie off
assign MC_SCAN_MODE_07_in = 1'b1; // tie off
assign MC_SCAN_RST_N_00_in = 1'b1; // tie off
assign MC_SCAN_RST_N_01_in = 1'b1; // tie off
assign MC_SCAN_RST_N_02_in = 1'b1; // tie off
assign MC_SCAN_RST_N_03_in = 1'b1; // tie off
assign MC_SCAN_RST_N_04_in = 1'b1; // tie off
assign MC_SCAN_RST_N_05_in = 1'b1; // tie off
assign MC_SCAN_RST_N_06_in = 1'b1; // tie off
assign MC_SCAN_RST_N_07_in = 1'b1; // tie off
assign PHY_SCAN_CK_00_in = 1'b1; // tie off
assign PHY_SCAN_ENABLE_00_in = 1'b1; // tie off
assign PHY_SCAN_IN_00_in = 2'b11; // tie off
assign PHY_SCAN_MODE_00_in = 1'b1; // tie off
assign PHY_SCAN_RST_N_00_in = 1'b1; // tie off
assign SW_SCAN_CK_00_in = 1'b1; // tie off
assign SW_SCAN_ENABLE_00_in = 1'b1; // tie off
assign SW_SCAN_IN_00_in = 2'b11; // tie off
assign SW_SCAN_IN_01_in = 2'b11; // tie off
assign SW_SCAN_IN_02_in = 2'b11; // tie off
assign SW_SCAN_IN_03_in = 2'b11; // tie off
assign SW_SCAN_MODE_00_in = 1'b1; // tie off
assign SW_SCAN_RST_N_00_in = 1'b1; // tie off
SIP_HBM_ONE_STACK_INTF SIP_HBM_ONE_STACK_INTF_INST (
.ANALOG_MUX_SEL_0 (ANALOG_MUX_SEL_0_REG),
.APB_BYPASS_EN (APB_BYPASS_EN_REG),
.AXI_BYPASS_EN (AXI_BYPASS_EN_REG),
.BLI_TESTMODE_SEL (BLI_TESTMODE_SEL_REG),
.CLK_SEL_00 (CLK_SEL_00_REG),
.CLK_SEL_01 (CLK_SEL_01_REG),
.CLK_SEL_02 (CLK_SEL_02_REG),
.CLK_SEL_03 (CLK_SEL_03_REG),
.CLK_SEL_04 (CLK_SEL_04_REG),
.CLK_SEL_05 (CLK_SEL_05_REG),
.CLK_SEL_06 (CLK_SEL_06_REG),
.CLK_SEL_07 (CLK_SEL_07_REG),
.CLK_SEL_08 (CLK_SEL_08_REG),
.CLK_SEL_09 (CLK_SEL_09_REG),
.CLK_SEL_10 (CLK_SEL_10_REG),
.CLK_SEL_11 (CLK_SEL_11_REG),
.CLK_SEL_12 (CLK_SEL_12_REG),
.CLK_SEL_13 (CLK_SEL_13_REG),
.CLK_SEL_14 (CLK_SEL_14_REG),
.CLK_SEL_15 (CLK_SEL_15_REG),
.DATARATE_00 (DATARATE_00_REG),
.DATARATE_01 (DATARATE_01_REG),
.DATARATE_02 (DATARATE_02_REG),
.DATARATE_03 (DATARATE_03_REG),
.DATARATE_04 (DATARATE_04_REG),
.DATARATE_05 (DATARATE_05_REG),
.DATARATE_06 (DATARATE_06_REG),
.DATARATE_07 (DATARATE_07_REG),
.DA_LOCKOUT (DA_LOCKOUT_REG),
.DBG_BYPASS_VAL (DBG_BYPASS_VAL_REG),
.DEBUG_MODE (DEBUG_MODE_REG),
.DFI_BYPASS_VAL (DFI_BYPASS_VAL_REG),
.DLL_TESTMODE_SEL_0 (DLL_TESTMODE_SEL_0_REG),
.IO_TESTMODE_SEL_0 (IO_TESTMODE_SEL_0_REG),
.IS_APB_0_PCLK_INVERTED (IS_APB_0_PCLK_INVERTED_REG),
.IS_APB_0_PRESET_N_INVERTED (IS_APB_0_PRESET_N_INVERTED_REG),
.IS_AXI_00_ACLK_INVERTED (IS_AXI_00_ACLK_INVERTED_REG),
.IS_AXI_00_ARESET_N_INVERTED (IS_AXI_00_ARESET_N_INVERTED_REG),
.IS_AXI_01_ACLK_INVERTED (IS_AXI_01_ACLK_INVERTED_REG),
.IS_AXI_01_ARESET_N_INVERTED (IS_AXI_01_ARESET_N_INVERTED_REG),
.IS_AXI_02_ACLK_INVERTED (IS_AXI_02_ACLK_INVERTED_REG),
.IS_AXI_02_ARESET_N_INVERTED (IS_AXI_02_ARESET_N_INVERTED_REG),
.IS_AXI_03_ACLK_INVERTED (IS_AXI_03_ACLK_INVERTED_REG),
.IS_AXI_03_ARESET_N_INVERTED (IS_AXI_03_ARESET_N_INVERTED_REG),
.IS_AXI_04_ACLK_INVERTED (IS_AXI_04_ACLK_INVERTED_REG),
.IS_AXI_04_ARESET_N_INVERTED (IS_AXI_04_ARESET_N_INVERTED_REG),
.IS_AXI_05_ACLK_INVERTED (IS_AXI_05_ACLK_INVERTED_REG),
.IS_AXI_05_ARESET_N_INVERTED (IS_AXI_05_ARESET_N_INVERTED_REG),
.IS_AXI_06_ACLK_INVERTED (IS_AXI_06_ACLK_INVERTED_REG),
.IS_AXI_06_ARESET_N_INVERTED (IS_AXI_06_ARESET_N_INVERTED_REG),
.IS_AXI_07_ACLK_INVERTED (IS_AXI_07_ACLK_INVERTED_REG),
.IS_AXI_07_ARESET_N_INVERTED (IS_AXI_07_ARESET_N_INVERTED_REG),
.IS_AXI_08_ACLK_INVERTED (IS_AXI_08_ACLK_INVERTED_REG),
.IS_AXI_08_ARESET_N_INVERTED (IS_AXI_08_ARESET_N_INVERTED_REG),
.IS_AXI_09_ACLK_INVERTED (IS_AXI_09_ACLK_INVERTED_REG),
.IS_AXI_09_ARESET_N_INVERTED (IS_AXI_09_ARESET_N_INVERTED_REG),
.IS_AXI_10_ACLK_INVERTED (IS_AXI_10_ACLK_INVERTED_REG),
.IS_AXI_10_ARESET_N_INVERTED (IS_AXI_10_ARESET_N_INVERTED_REG),
.IS_AXI_11_ACLK_INVERTED (IS_AXI_11_ACLK_INVERTED_REG),
.IS_AXI_11_ARESET_N_INVERTED (IS_AXI_11_ARESET_N_INVERTED_REG),
.IS_AXI_12_ACLK_INVERTED (IS_AXI_12_ACLK_INVERTED_REG),
.IS_AXI_12_ARESET_N_INVERTED (IS_AXI_12_ARESET_N_INVERTED_REG),
.IS_AXI_13_ACLK_INVERTED (IS_AXI_13_ACLK_INVERTED_REG),
.IS_AXI_13_ARESET_N_INVERTED (IS_AXI_13_ARESET_N_INVERTED_REG),
.IS_AXI_14_ACLK_INVERTED (IS_AXI_14_ACLK_INVERTED_REG),
.IS_AXI_14_ARESET_N_INVERTED (IS_AXI_14_ARESET_N_INVERTED_REG),
.IS_AXI_15_ACLK_INVERTED (IS_AXI_15_ACLK_INVERTED_REG),
.IS_AXI_15_ARESET_N_INVERTED (IS_AXI_15_ARESET_N_INVERTED_REG),
.MC_CSSD_SEL_0 (MC_CSSD_SEL_0_REG),
.MC_CSSD_SEL_1 (MC_CSSD_SEL_1_REG),
.MC_CSSD_SEL_2 (MC_CSSD_SEL_2_REG),
.MC_CSSD_SEL_3 (MC_CSSD_SEL_3_REG),
.MC_CSSD_SEL_4 (MC_CSSD_SEL_4_REG),
.MC_CSSD_SEL_5 (MC_CSSD_SEL_5_REG),
.MC_CSSD_SEL_6 (MC_CSSD_SEL_6_REG),
.MC_CSSD_SEL_7 (MC_CSSD_SEL_7_REG),
.MC_ENABLE_0 (MC_ENABLE_0_REG),
.MC_ENABLE_1 (MC_ENABLE_1_REG),
.MC_ENABLE_2 (MC_ENABLE_2_REG),
.MC_ENABLE_3 (MC_ENABLE_3_REG),
.MC_ENABLE_4 (MC_ENABLE_4_REG),
.MC_ENABLE_5 (MC_ENABLE_5_REG),
.MC_ENABLE_6 (MC_ENABLE_6_REG),
.MC_ENABLE_7 (MC_ENABLE_7_REG),
.MC_ENABLE_APB (MC_ENABLE_APB_REG),
.MC_TESTMODE_SEL_0 (MC_TESTMODE_SEL_0_REG),
.MC_TESTMODE_SEL_1 (MC_TESTMODE_SEL_1_REG),
.MC_TESTMODE_SEL_2 (MC_TESTMODE_SEL_2_REG),
.MC_TESTMODE_SEL_3 (MC_TESTMODE_SEL_3_REG),
.MC_TESTMODE_SEL_4 (MC_TESTMODE_SEL_4_REG),
.MC_TESTMODE_SEL_5 (MC_TESTMODE_SEL_5_REG),
.MC_TESTMODE_SEL_6 (MC_TESTMODE_SEL_6_REG),
.MC_TESTMODE_SEL_7 (MC_TESTMODE_SEL_7_REG),
.PAGEHIT_PERCENT_00 (PAGEHIT_PERCENT_00_REG),
.PHY_CSSD_SEL_0 (PHY_CSSD_SEL_0_REG),
.PHY_ENABLE_00 (PHY_ENABLE_00_REG),
.PHY_ENABLE_01 (PHY_ENABLE_01_REG),
.PHY_ENABLE_02 (PHY_ENABLE_02_REG),
.PHY_ENABLE_03 (PHY_ENABLE_03_REG),
.PHY_ENABLE_04 (PHY_ENABLE_04_REG),
.PHY_ENABLE_05 (PHY_ENABLE_05_REG),
.PHY_ENABLE_06 (PHY_ENABLE_06_REG),
.PHY_ENABLE_07 (PHY_ENABLE_07_REG),
.PHY_ENABLE_08 (PHY_ENABLE_08_REG),
.PHY_ENABLE_09 (PHY_ENABLE_09_REG),
.PHY_ENABLE_10 (PHY_ENABLE_10_REG),
.PHY_ENABLE_11 (PHY_ENABLE_11_REG),
.PHY_ENABLE_12 (PHY_ENABLE_12_REG),
.PHY_ENABLE_13 (PHY_ENABLE_13_REG),
.PHY_ENABLE_14 (PHY_ENABLE_14_REG),
.PHY_ENABLE_15 (PHY_ENABLE_15_REG),
.PHY_ENABLE_APB (PHY_ENABLE_APB_REG),
.PHY_PCLK_INVERT_01 (PHY_PCLK_INVERT_01_REG),
.PHY_TESTMODE_SEL_0 (PHY_TESTMODE_SEL_0_REG),
.READ_PERCENT_00 (READ_PERCENT_00_REG),
.READ_PERCENT_01 (READ_PERCENT_01_REG),
.READ_PERCENT_02 (READ_PERCENT_02_REG),
.READ_PERCENT_03 (READ_PERCENT_03_REG),
.READ_PERCENT_04 (READ_PERCENT_04_REG),
.READ_PERCENT_05 (READ_PERCENT_05_REG),
.READ_PERCENT_06 (READ_PERCENT_06_REG),
.READ_PERCENT_07 (READ_PERCENT_07_REG),
.READ_PERCENT_08 (READ_PERCENT_08_REG),
.READ_PERCENT_09 (READ_PERCENT_09_REG),
.READ_PERCENT_10 (READ_PERCENT_10_REG),
.READ_PERCENT_11 (READ_PERCENT_11_REG),
.READ_PERCENT_12 (READ_PERCENT_12_REG),
.READ_PERCENT_13 (READ_PERCENT_13_REG),
.READ_PERCENT_14 (READ_PERCENT_14_REG),
.READ_PERCENT_15 (READ_PERCENT_15_REG),
.STACK_LOCATION (STACK_LOCATION_REG),
.SWITCH_ENABLE (SWITCH_ENABLE_REG),
.SW_TESTMODE_SEL_0 (SW_TESTMODE_SEL_0_REG),
.WRITE_PERCENT_00 (WRITE_PERCENT_00_REG),
.WRITE_PERCENT_01 (WRITE_PERCENT_01_REG),
.WRITE_PERCENT_02 (WRITE_PERCENT_02_REG),
.WRITE_PERCENT_03 (WRITE_PERCENT_03_REG),
.WRITE_PERCENT_04 (WRITE_PERCENT_04_REG),
.WRITE_PERCENT_05 (WRITE_PERCENT_05_REG),
.WRITE_PERCENT_06 (WRITE_PERCENT_06_REG),
.WRITE_PERCENT_07 (WRITE_PERCENT_07_REG),
.WRITE_PERCENT_08 (WRITE_PERCENT_08_REG),
.WRITE_PERCENT_09 (WRITE_PERCENT_09_REG),
.WRITE_PERCENT_10 (WRITE_PERCENT_10_REG),
.WRITE_PERCENT_11 (WRITE_PERCENT_11_REG),
.WRITE_PERCENT_12 (WRITE_PERCENT_12_REG),
.WRITE_PERCENT_13 (WRITE_PERCENT_13_REG),
.WRITE_PERCENT_14 (WRITE_PERCENT_14_REG),
.WRITE_PERCENT_15 (WRITE_PERCENT_15_REG),
.APB_0_PRDATA (APB_0_PRDATA_out),
.APB_0_PREADY (APB_0_PREADY_out),
.APB_0_PSLVERR (APB_0_PSLVERR_out),
.AXI_00_ARREADY (AXI_00_ARREADY_out),
.AXI_00_AWREADY (AXI_00_AWREADY_out),
.AXI_00_BID (AXI_00_BID_out),
.AXI_00_BRESP (AXI_00_BRESP_out),
.AXI_00_BVALID (AXI_00_BVALID_out),
.AXI_00_DFI_AW_AERR_N (AXI_00_DFI_AW_AERR_N_out),
.AXI_00_DFI_CLK_BUF (AXI_00_DFI_CLK_BUF_out),
.AXI_00_DFI_DBI_BYTE_DISABLE (AXI_00_DFI_DBI_BYTE_DISABLE_out),
.AXI_00_DFI_DW_RDDATA_DBI (AXI_00_DFI_DW_RDDATA_DBI_out),
.AXI_00_DFI_DW_RDDATA_DERR (AXI_00_DFI_DW_RDDATA_DERR_out),
.AXI_00_DFI_DW_RDDATA_VALID (AXI_00_DFI_DW_RDDATA_VALID_out),
.AXI_00_DFI_INIT_COMPLETE (AXI_00_DFI_INIT_COMPLETE_out),
.AXI_00_DFI_PHYUPD_REQ (AXI_00_DFI_PHYUPD_REQ_out),
.AXI_00_DFI_PHY_LP_STATE (AXI_00_DFI_PHY_LP_STATE_out),
.AXI_00_DFI_RST_N_BUF (AXI_00_DFI_RST_N_BUF_out),
.AXI_00_MC_STATUS (AXI_00_MC_STATUS_out),
.AXI_00_PHY_STATUS (AXI_00_PHY_STATUS_out),
.AXI_00_RDATA (AXI_00_RDATA_out),
.AXI_00_RDATA_PARITY (AXI_00_RDATA_PARITY_out),
.AXI_00_RID (AXI_00_RID_out),
.AXI_00_RLAST (AXI_00_RLAST_out),
.AXI_00_RRESP (AXI_00_RRESP_out),
.AXI_00_RVALID (AXI_00_RVALID_out),
.AXI_00_WREADY (AXI_00_WREADY_out),
.AXI_01_ARREADY (AXI_01_ARREADY_out),
.AXI_01_AWREADY (AXI_01_AWREADY_out),
.AXI_01_BID (AXI_01_BID_out),
.AXI_01_BRESP (AXI_01_BRESP_out),
.AXI_01_BVALID (AXI_01_BVALID_out),
.AXI_01_DFI_AW_AERR_N (AXI_01_DFI_AW_AERR_N_out),
.AXI_01_DFI_CLK_BUF (AXI_01_DFI_CLK_BUF_out),
.AXI_01_DFI_DBI_BYTE_DISABLE (AXI_01_DFI_DBI_BYTE_DISABLE_out),
.AXI_01_DFI_DW_RDDATA_DBI (AXI_01_DFI_DW_RDDATA_DBI_out),
.AXI_01_DFI_DW_RDDATA_DERR (AXI_01_DFI_DW_RDDATA_DERR_out),
.AXI_01_DFI_DW_RDDATA_VALID (AXI_01_DFI_DW_RDDATA_VALID_out),
.AXI_01_DFI_INIT_COMPLETE (AXI_01_DFI_INIT_COMPLETE_out),
.AXI_01_DFI_PHYUPD_REQ (AXI_01_DFI_PHYUPD_REQ_out),
.AXI_01_DFI_PHY_LP_STATE (AXI_01_DFI_PHY_LP_STATE_out),
.AXI_01_DFI_RST_N_BUF (AXI_01_DFI_RST_N_BUF_out),
.AXI_01_RDATA (AXI_01_RDATA_out),
.AXI_01_RDATA_PARITY (AXI_01_RDATA_PARITY_out),
.AXI_01_RID (AXI_01_RID_out),
.AXI_01_RLAST (AXI_01_RLAST_out),
.AXI_01_RRESP (AXI_01_RRESP_out),
.AXI_01_RVALID (AXI_01_RVALID_out),
.AXI_01_WREADY (AXI_01_WREADY_out),
.AXI_02_ARREADY (AXI_02_ARREADY_out),
.AXI_02_AWREADY (AXI_02_AWREADY_out),
.AXI_02_BID (AXI_02_BID_out),
.AXI_02_BRESP (AXI_02_BRESP_out),
.AXI_02_BVALID (AXI_02_BVALID_out),
.AXI_02_DFI_AW_AERR_N (AXI_02_DFI_AW_AERR_N_out),
.AXI_02_DFI_CLK_BUF (AXI_02_DFI_CLK_BUF_out),
.AXI_02_DFI_DBI_BYTE_DISABLE (AXI_02_DFI_DBI_BYTE_DISABLE_out),
.AXI_02_DFI_DW_RDDATA_DBI (AXI_02_DFI_DW_RDDATA_DBI_out),
.AXI_02_DFI_DW_RDDATA_DERR (AXI_02_DFI_DW_RDDATA_DERR_out),
.AXI_02_DFI_DW_RDDATA_VALID (AXI_02_DFI_DW_RDDATA_VALID_out),
.AXI_02_DFI_INIT_COMPLETE (AXI_02_DFI_INIT_COMPLETE_out),
.AXI_02_DFI_PHYUPD_REQ (AXI_02_DFI_PHYUPD_REQ_out),
.AXI_02_DFI_PHY_LP_STATE (AXI_02_DFI_PHY_LP_STATE_out),
.AXI_02_DFI_RST_N_BUF (AXI_02_DFI_RST_N_BUF_out),
.AXI_02_MC_STATUS (AXI_02_MC_STATUS_out),
.AXI_02_PHY_STATUS (AXI_02_PHY_STATUS_out),
.AXI_02_RDATA (AXI_02_RDATA_out),
.AXI_02_RDATA_PARITY (AXI_02_RDATA_PARITY_out),
.AXI_02_RID (AXI_02_RID_out),
.AXI_02_RLAST (AXI_02_RLAST_out),
.AXI_02_RRESP (AXI_02_RRESP_out),
.AXI_02_RVALID (AXI_02_RVALID_out),
.AXI_02_WREADY (AXI_02_WREADY_out),
.AXI_03_ARREADY (AXI_03_ARREADY_out),
.AXI_03_AWREADY (AXI_03_AWREADY_out),
.AXI_03_BID (AXI_03_BID_out),
.AXI_03_BRESP (AXI_03_BRESP_out),
.AXI_03_BVALID (AXI_03_BVALID_out),
.AXI_03_DFI_AW_AERR_N (AXI_03_DFI_AW_AERR_N_out),
.AXI_03_DFI_CLK_BUF (AXI_03_DFI_CLK_BUF_out),
.AXI_03_DFI_DBI_BYTE_DISABLE (AXI_03_DFI_DBI_BYTE_DISABLE_out),
.AXI_03_DFI_DW_RDDATA_DBI (AXI_03_DFI_DW_RDDATA_DBI_out),
.AXI_03_DFI_DW_RDDATA_DERR (AXI_03_DFI_DW_RDDATA_DERR_out),
.AXI_03_DFI_DW_RDDATA_VALID (AXI_03_DFI_DW_RDDATA_VALID_out),
.AXI_03_DFI_INIT_COMPLETE (AXI_03_DFI_INIT_COMPLETE_out),
.AXI_03_DFI_PHYUPD_REQ (AXI_03_DFI_PHYUPD_REQ_out),
.AXI_03_DFI_PHY_LP_STATE (AXI_03_DFI_PHY_LP_STATE_out),
.AXI_03_DFI_RST_N_BUF (AXI_03_DFI_RST_N_BUF_out),
.AXI_03_RDATA (AXI_03_RDATA_out),
.AXI_03_RDATA_PARITY (AXI_03_RDATA_PARITY_out),
.AXI_03_RID (AXI_03_RID_out),
.AXI_03_RLAST (AXI_03_RLAST_out),
.AXI_03_RRESP (AXI_03_RRESP_out),
.AXI_03_RVALID (AXI_03_RVALID_out),
.AXI_03_WREADY (AXI_03_WREADY_out),
.AXI_04_ARREADY (AXI_04_ARREADY_out),
.AXI_04_AWREADY (AXI_04_AWREADY_out),
.AXI_04_BID (AXI_04_BID_out),
.AXI_04_BRESP (AXI_04_BRESP_out),
.AXI_04_BVALID (AXI_04_BVALID_out),
.AXI_04_DFI_AW_AERR_N (AXI_04_DFI_AW_AERR_N_out),
.AXI_04_DFI_CLK_BUF (AXI_04_DFI_CLK_BUF_out),
.AXI_04_DFI_DBI_BYTE_DISABLE (AXI_04_DFI_DBI_BYTE_DISABLE_out),
.AXI_04_DFI_DW_RDDATA_DBI (AXI_04_DFI_DW_RDDATA_DBI_out),
.AXI_04_DFI_DW_RDDATA_DERR (AXI_04_DFI_DW_RDDATA_DERR_out),
.AXI_04_DFI_DW_RDDATA_VALID (AXI_04_DFI_DW_RDDATA_VALID_out),
.AXI_04_DFI_INIT_COMPLETE (AXI_04_DFI_INIT_COMPLETE_out),
.AXI_04_DFI_PHYUPD_REQ (AXI_04_DFI_PHYUPD_REQ_out),
.AXI_04_DFI_PHY_LP_STATE (AXI_04_DFI_PHY_LP_STATE_out),
.AXI_04_DFI_RST_N_BUF (AXI_04_DFI_RST_N_BUF_out),
.AXI_04_MC_STATUS (AXI_04_MC_STATUS_out),
.AXI_04_PHY_STATUS (AXI_04_PHY_STATUS_out),
.AXI_04_RDATA (AXI_04_RDATA_out),
.AXI_04_RDATA_PARITY (AXI_04_RDATA_PARITY_out),
.AXI_04_RID (AXI_04_RID_out),
.AXI_04_RLAST (AXI_04_RLAST_out),
.AXI_04_RRESP (AXI_04_RRESP_out),
.AXI_04_RVALID (AXI_04_RVALID_out),
.AXI_04_WREADY (AXI_04_WREADY_out),
.AXI_05_ARREADY (AXI_05_ARREADY_out),
.AXI_05_AWREADY (AXI_05_AWREADY_out),
.AXI_05_BID (AXI_05_BID_out),
.AXI_05_BRESP (AXI_05_BRESP_out),
.AXI_05_BVALID (AXI_05_BVALID_out),
.AXI_05_DFI_AW_AERR_N (AXI_05_DFI_AW_AERR_N_out),
.AXI_05_DFI_CLK_BUF (AXI_05_DFI_CLK_BUF_out),
.AXI_05_DFI_DBI_BYTE_DISABLE (AXI_05_DFI_DBI_BYTE_DISABLE_out),
.AXI_05_DFI_DW_RDDATA_DBI (AXI_05_DFI_DW_RDDATA_DBI_out),
.AXI_05_DFI_DW_RDDATA_DERR (AXI_05_DFI_DW_RDDATA_DERR_out),
.AXI_05_DFI_DW_RDDATA_VALID (AXI_05_DFI_DW_RDDATA_VALID_out),
.AXI_05_DFI_INIT_COMPLETE (AXI_05_DFI_INIT_COMPLETE_out),
.AXI_05_DFI_PHYUPD_REQ (AXI_05_DFI_PHYUPD_REQ_out),
.AXI_05_DFI_PHY_LP_STATE (AXI_05_DFI_PHY_LP_STATE_out),
.AXI_05_DFI_RST_N_BUF (AXI_05_DFI_RST_N_BUF_out),
.AXI_05_RDATA (AXI_05_RDATA_out),
.AXI_05_RDATA_PARITY (AXI_05_RDATA_PARITY_out),
.AXI_05_RID (AXI_05_RID_out),
.AXI_05_RLAST (AXI_05_RLAST_out),
.AXI_05_RRESP (AXI_05_RRESP_out),
.AXI_05_RVALID (AXI_05_RVALID_out),
.AXI_05_WREADY (AXI_05_WREADY_out),
.AXI_06_ARREADY (AXI_06_ARREADY_out),
.AXI_06_AWREADY (AXI_06_AWREADY_out),
.AXI_06_BID (AXI_06_BID_out),
.AXI_06_BRESP (AXI_06_BRESP_out),
.AXI_06_BVALID (AXI_06_BVALID_out),
.AXI_06_DFI_AW_AERR_N (AXI_06_DFI_AW_AERR_N_out),
.AXI_06_DFI_CLK_BUF (AXI_06_DFI_CLK_BUF_out),
.AXI_06_DFI_DBI_BYTE_DISABLE (AXI_06_DFI_DBI_BYTE_DISABLE_out),
.AXI_06_DFI_DW_RDDATA_DBI (AXI_06_DFI_DW_RDDATA_DBI_out),
.AXI_06_DFI_DW_RDDATA_DERR (AXI_06_DFI_DW_RDDATA_DERR_out),
.AXI_06_DFI_DW_RDDATA_VALID (AXI_06_DFI_DW_RDDATA_VALID_out),
.AXI_06_DFI_INIT_COMPLETE (AXI_06_DFI_INIT_COMPLETE_out),
.AXI_06_DFI_PHYUPD_REQ (AXI_06_DFI_PHYUPD_REQ_out),
.AXI_06_DFI_PHY_LP_STATE (AXI_06_DFI_PHY_LP_STATE_out),
.AXI_06_DFI_RST_N_BUF (AXI_06_DFI_RST_N_BUF_out),
.AXI_06_MC_STATUS (AXI_06_MC_STATUS_out),
.AXI_06_PHY_STATUS (AXI_06_PHY_STATUS_out),
.AXI_06_RDATA (AXI_06_RDATA_out),
.AXI_06_RDATA_PARITY (AXI_06_RDATA_PARITY_out),
.AXI_06_RID (AXI_06_RID_out),
.AXI_06_RLAST (AXI_06_RLAST_out),
.AXI_06_RRESP (AXI_06_RRESP_out),
.AXI_06_RVALID (AXI_06_RVALID_out),
.AXI_06_WREADY (AXI_06_WREADY_out),
.AXI_07_ARREADY (AXI_07_ARREADY_out),
.AXI_07_AWREADY (AXI_07_AWREADY_out),
.AXI_07_BID (AXI_07_BID_out),
.AXI_07_BRESP (AXI_07_BRESP_out),
.AXI_07_BVALID (AXI_07_BVALID_out),
.AXI_07_DFI_AW_AERR_N (AXI_07_DFI_AW_AERR_N_out),
.AXI_07_DFI_CLK_BUF (AXI_07_DFI_CLK_BUF_out),
.AXI_07_DFI_DBI_BYTE_DISABLE (AXI_07_DFI_DBI_BYTE_DISABLE_out),
.AXI_07_DFI_DW_RDDATA_DBI (AXI_07_DFI_DW_RDDATA_DBI_out),
.AXI_07_DFI_DW_RDDATA_DERR (AXI_07_DFI_DW_RDDATA_DERR_out),
.AXI_07_DFI_DW_RDDATA_VALID (AXI_07_DFI_DW_RDDATA_VALID_out),
.AXI_07_DFI_INIT_COMPLETE (AXI_07_DFI_INIT_COMPLETE_out),
.AXI_07_DFI_PHYUPD_REQ (AXI_07_DFI_PHYUPD_REQ_out),
.AXI_07_DFI_PHY_LP_STATE (AXI_07_DFI_PHY_LP_STATE_out),
.AXI_07_DFI_RST_N_BUF (AXI_07_DFI_RST_N_BUF_out),
.AXI_07_RDATA (AXI_07_RDATA_out),
.AXI_07_RDATA_PARITY (AXI_07_RDATA_PARITY_out),
.AXI_07_RID (AXI_07_RID_out),
.AXI_07_RLAST (AXI_07_RLAST_out),
.AXI_07_RRESP (AXI_07_RRESP_out),
.AXI_07_RVALID (AXI_07_RVALID_out),
.AXI_07_WREADY (AXI_07_WREADY_out),
.AXI_08_ARREADY (AXI_08_ARREADY_out),
.AXI_08_AWREADY (AXI_08_AWREADY_out),
.AXI_08_BID (AXI_08_BID_out),
.AXI_08_BRESP (AXI_08_BRESP_out),
.AXI_08_BVALID (AXI_08_BVALID_out),
.AXI_08_DFI_AW_AERR_N (AXI_08_DFI_AW_AERR_N_out),
.AXI_08_DFI_CLK_BUF (AXI_08_DFI_CLK_BUF_out),
.AXI_08_DFI_DBI_BYTE_DISABLE (AXI_08_DFI_DBI_BYTE_DISABLE_out),
.AXI_08_DFI_DW_RDDATA_DBI (AXI_08_DFI_DW_RDDATA_DBI_out),
.AXI_08_DFI_DW_RDDATA_DERR (AXI_08_DFI_DW_RDDATA_DERR_out),
.AXI_08_DFI_DW_RDDATA_VALID (AXI_08_DFI_DW_RDDATA_VALID_out),
.AXI_08_DFI_INIT_COMPLETE (AXI_08_DFI_INIT_COMPLETE_out),
.AXI_08_DFI_PHYUPD_REQ (AXI_08_DFI_PHYUPD_REQ_out),
.AXI_08_DFI_PHY_LP_STATE (AXI_08_DFI_PHY_LP_STATE_out),
.AXI_08_DFI_RST_N_BUF (AXI_08_DFI_RST_N_BUF_out),
.AXI_08_MC_STATUS (AXI_08_MC_STATUS_out),
.AXI_08_PHY_STATUS (AXI_08_PHY_STATUS_out),
.AXI_08_RDATA (AXI_08_RDATA_out),
.AXI_08_RDATA_PARITY (AXI_08_RDATA_PARITY_out),
.AXI_08_RID (AXI_08_RID_out),
.AXI_08_RLAST (AXI_08_RLAST_out),
.AXI_08_RRESP (AXI_08_RRESP_out),
.AXI_08_RVALID (AXI_08_RVALID_out),
.AXI_08_WREADY (AXI_08_WREADY_out),
.AXI_09_ARREADY (AXI_09_ARREADY_out),
.AXI_09_AWREADY (AXI_09_AWREADY_out),
.AXI_09_BID (AXI_09_BID_out),
.AXI_09_BRESP (AXI_09_BRESP_out),
.AXI_09_BVALID (AXI_09_BVALID_out),
.AXI_09_DFI_AW_AERR_N (AXI_09_DFI_AW_AERR_N_out),
.AXI_09_DFI_CLK_BUF (AXI_09_DFI_CLK_BUF_out),
.AXI_09_DFI_DBI_BYTE_DISABLE (AXI_09_DFI_DBI_BYTE_DISABLE_out),
.AXI_09_DFI_DW_RDDATA_DBI (AXI_09_DFI_DW_RDDATA_DBI_out),
.AXI_09_DFI_DW_RDDATA_DERR (AXI_09_DFI_DW_RDDATA_DERR_out),
.AXI_09_DFI_DW_RDDATA_VALID (AXI_09_DFI_DW_RDDATA_VALID_out),
.AXI_09_DFI_INIT_COMPLETE (AXI_09_DFI_INIT_COMPLETE_out),
.AXI_09_DFI_PHYUPD_REQ (AXI_09_DFI_PHYUPD_REQ_out),
.AXI_09_DFI_PHY_LP_STATE (AXI_09_DFI_PHY_LP_STATE_out),
.AXI_09_DFI_RST_N_BUF (AXI_09_DFI_RST_N_BUF_out),
.AXI_09_RDATA (AXI_09_RDATA_out),
.AXI_09_RDATA_PARITY (AXI_09_RDATA_PARITY_out),
.AXI_09_RID (AXI_09_RID_out),
.AXI_09_RLAST (AXI_09_RLAST_out),
.AXI_09_RRESP (AXI_09_RRESP_out),
.AXI_09_RVALID (AXI_09_RVALID_out),
.AXI_09_WREADY (AXI_09_WREADY_out),
.AXI_10_ARREADY (AXI_10_ARREADY_out),
.AXI_10_AWREADY (AXI_10_AWREADY_out),
.AXI_10_BID (AXI_10_BID_out),
.AXI_10_BRESP (AXI_10_BRESP_out),
.AXI_10_BVALID (AXI_10_BVALID_out),
.AXI_10_DFI_AW_AERR_N (AXI_10_DFI_AW_AERR_N_out),
.AXI_10_DFI_CLK_BUF (AXI_10_DFI_CLK_BUF_out),
.AXI_10_DFI_DBI_BYTE_DISABLE (AXI_10_DFI_DBI_BYTE_DISABLE_out),
.AXI_10_DFI_DW_RDDATA_DBI (AXI_10_DFI_DW_RDDATA_DBI_out),
.AXI_10_DFI_DW_RDDATA_DERR (AXI_10_DFI_DW_RDDATA_DERR_out),
.AXI_10_DFI_DW_RDDATA_VALID (AXI_10_DFI_DW_RDDATA_VALID_out),
.AXI_10_DFI_INIT_COMPLETE (AXI_10_DFI_INIT_COMPLETE_out),
.AXI_10_DFI_PHYUPD_REQ (AXI_10_DFI_PHYUPD_REQ_out),
.AXI_10_DFI_PHY_LP_STATE (AXI_10_DFI_PHY_LP_STATE_out),
.AXI_10_DFI_RST_N_BUF (AXI_10_DFI_RST_N_BUF_out),
.AXI_10_MC_STATUS (AXI_10_MC_STATUS_out),
.AXI_10_PHY_STATUS (AXI_10_PHY_STATUS_out),
.AXI_10_RDATA (AXI_10_RDATA_out),
.AXI_10_RDATA_PARITY (AXI_10_RDATA_PARITY_out),
.AXI_10_RID (AXI_10_RID_out),
.AXI_10_RLAST (AXI_10_RLAST_out),
.AXI_10_RRESP (AXI_10_RRESP_out),
.AXI_10_RVALID (AXI_10_RVALID_out),
.AXI_10_WREADY (AXI_10_WREADY_out),
.AXI_11_ARREADY (AXI_11_ARREADY_out),
.AXI_11_AWREADY (AXI_11_AWREADY_out),
.AXI_11_BID (AXI_11_BID_out),
.AXI_11_BRESP (AXI_11_BRESP_out),
.AXI_11_BVALID (AXI_11_BVALID_out),
.AXI_11_DFI_AW_AERR_N (AXI_11_DFI_AW_AERR_N_out),
.AXI_11_DFI_CLK_BUF (AXI_11_DFI_CLK_BUF_out),
.AXI_11_DFI_DBI_BYTE_DISABLE (AXI_11_DFI_DBI_BYTE_DISABLE_out),
.AXI_11_DFI_DW_RDDATA_DBI (AXI_11_DFI_DW_RDDATA_DBI_out),
.AXI_11_DFI_DW_RDDATA_DERR (AXI_11_DFI_DW_RDDATA_DERR_out),
.AXI_11_DFI_DW_RDDATA_VALID (AXI_11_DFI_DW_RDDATA_VALID_out),
.AXI_11_DFI_INIT_COMPLETE (AXI_11_DFI_INIT_COMPLETE_out),
.AXI_11_DFI_PHYUPD_REQ (AXI_11_DFI_PHYUPD_REQ_out),
.AXI_11_DFI_PHY_LP_STATE (AXI_11_DFI_PHY_LP_STATE_out),
.AXI_11_DFI_RST_N_BUF (AXI_11_DFI_RST_N_BUF_out),
.AXI_11_RDATA (AXI_11_RDATA_out),
.AXI_11_RDATA_PARITY (AXI_11_RDATA_PARITY_out),
.AXI_11_RID (AXI_11_RID_out),
.AXI_11_RLAST (AXI_11_RLAST_out),
.AXI_11_RRESP (AXI_11_RRESP_out),
.AXI_11_RVALID (AXI_11_RVALID_out),
.AXI_11_WREADY (AXI_11_WREADY_out),
.AXI_12_ARREADY (AXI_12_ARREADY_out),
.AXI_12_AWREADY (AXI_12_AWREADY_out),
.AXI_12_BID (AXI_12_BID_out),
.AXI_12_BRESP (AXI_12_BRESP_out),
.AXI_12_BVALID (AXI_12_BVALID_out),
.AXI_12_DFI_AW_AERR_N (AXI_12_DFI_AW_AERR_N_out),
.AXI_12_DFI_CLK_BUF (AXI_12_DFI_CLK_BUF_out),
.AXI_12_DFI_DBI_BYTE_DISABLE (AXI_12_DFI_DBI_BYTE_DISABLE_out),
.AXI_12_DFI_DW_RDDATA_DBI (AXI_12_DFI_DW_RDDATA_DBI_out),
.AXI_12_DFI_DW_RDDATA_DERR (AXI_12_DFI_DW_RDDATA_DERR_out),
.AXI_12_DFI_DW_RDDATA_VALID (AXI_12_DFI_DW_RDDATA_VALID_out),
.AXI_12_DFI_INIT_COMPLETE (AXI_12_DFI_INIT_COMPLETE_out),
.AXI_12_DFI_PHYUPD_REQ (AXI_12_DFI_PHYUPD_REQ_out),
.AXI_12_DFI_PHY_LP_STATE (AXI_12_DFI_PHY_LP_STATE_out),
.AXI_12_DFI_RST_N_BUF (AXI_12_DFI_RST_N_BUF_out),
.AXI_12_MC_STATUS (AXI_12_MC_STATUS_out),
.AXI_12_PHY_STATUS (AXI_12_PHY_STATUS_out),
.AXI_12_RDATA (AXI_12_RDATA_out),
.AXI_12_RDATA_PARITY (AXI_12_RDATA_PARITY_out),
.AXI_12_RID (AXI_12_RID_out),
.AXI_12_RLAST (AXI_12_RLAST_out),
.AXI_12_RRESP (AXI_12_RRESP_out),
.AXI_12_RVALID (AXI_12_RVALID_out),
.AXI_12_WREADY (AXI_12_WREADY_out),
.AXI_13_ARREADY (AXI_13_ARREADY_out),
.AXI_13_AWREADY (AXI_13_AWREADY_out),
.AXI_13_BID (AXI_13_BID_out),
.AXI_13_BRESP (AXI_13_BRESP_out),
.AXI_13_BVALID (AXI_13_BVALID_out),
.AXI_13_DFI_AW_AERR_N (AXI_13_DFI_AW_AERR_N_out),
.AXI_13_DFI_CLK_BUF (AXI_13_DFI_CLK_BUF_out),
.AXI_13_DFI_DBI_BYTE_DISABLE (AXI_13_DFI_DBI_BYTE_DISABLE_out),
.AXI_13_DFI_DW_RDDATA_DBI (AXI_13_DFI_DW_RDDATA_DBI_out),
.AXI_13_DFI_DW_RDDATA_DERR (AXI_13_DFI_DW_RDDATA_DERR_out),
.AXI_13_DFI_DW_RDDATA_VALID (AXI_13_DFI_DW_RDDATA_VALID_out),
.AXI_13_DFI_INIT_COMPLETE (AXI_13_DFI_INIT_COMPLETE_out),
.AXI_13_DFI_PHYUPD_REQ (AXI_13_DFI_PHYUPD_REQ_out),
.AXI_13_DFI_PHY_LP_STATE (AXI_13_DFI_PHY_LP_STATE_out),
.AXI_13_DFI_RST_N_BUF (AXI_13_DFI_RST_N_BUF_out),
.AXI_13_RDATA (AXI_13_RDATA_out),
.AXI_13_RDATA_PARITY (AXI_13_RDATA_PARITY_out),
.AXI_13_RID (AXI_13_RID_out),
.AXI_13_RLAST (AXI_13_RLAST_out),
.AXI_13_RRESP (AXI_13_RRESP_out),
.AXI_13_RVALID (AXI_13_RVALID_out),
.AXI_13_WREADY (AXI_13_WREADY_out),
.AXI_14_ARREADY (AXI_14_ARREADY_out),
.AXI_14_AWREADY (AXI_14_AWREADY_out),
.AXI_14_BID (AXI_14_BID_out),
.AXI_14_BRESP (AXI_14_BRESP_out),
.AXI_14_BVALID (AXI_14_BVALID_out),
.AXI_14_DFI_AW_AERR_N (AXI_14_DFI_AW_AERR_N_out),
.AXI_14_DFI_CLK_BUF (AXI_14_DFI_CLK_BUF_out),
.AXI_14_DFI_DBI_BYTE_DISABLE (AXI_14_DFI_DBI_BYTE_DISABLE_out),
.AXI_14_DFI_DW_RDDATA_DBI (AXI_14_DFI_DW_RDDATA_DBI_out),
.AXI_14_DFI_DW_RDDATA_DERR (AXI_14_DFI_DW_RDDATA_DERR_out),
.AXI_14_DFI_DW_RDDATA_VALID (AXI_14_DFI_DW_RDDATA_VALID_out),
.AXI_14_DFI_INIT_COMPLETE (AXI_14_DFI_INIT_COMPLETE_out),
.AXI_14_DFI_PHYUPD_REQ (AXI_14_DFI_PHYUPD_REQ_out),
.AXI_14_DFI_PHY_LP_STATE (AXI_14_DFI_PHY_LP_STATE_out),
.AXI_14_DFI_RST_N_BUF (AXI_14_DFI_RST_N_BUF_out),
.AXI_14_MC_STATUS (AXI_14_MC_STATUS_out),
.AXI_14_PHY_STATUS (AXI_14_PHY_STATUS_out),
.AXI_14_RDATA (AXI_14_RDATA_out),
.AXI_14_RDATA_PARITY (AXI_14_RDATA_PARITY_out),
.AXI_14_RID (AXI_14_RID_out),
.AXI_14_RLAST (AXI_14_RLAST_out),
.AXI_14_RRESP (AXI_14_RRESP_out),
.AXI_14_RVALID (AXI_14_RVALID_out),
.AXI_14_WREADY (AXI_14_WREADY_out),
.AXI_15_ARREADY (AXI_15_ARREADY_out),
.AXI_15_AWREADY (AXI_15_AWREADY_out),
.AXI_15_BID (AXI_15_BID_out),
.AXI_15_BRESP (AXI_15_BRESP_out),
.AXI_15_BVALID (AXI_15_BVALID_out),
.AXI_15_DFI_AW_AERR_N (AXI_15_DFI_AW_AERR_N_out),
.AXI_15_DFI_CLK_BUF (AXI_15_DFI_CLK_BUF_out),
.AXI_15_DFI_DBI_BYTE_DISABLE (AXI_15_DFI_DBI_BYTE_DISABLE_out),
.AXI_15_DFI_DW_RDDATA_DBI (AXI_15_DFI_DW_RDDATA_DBI_out),
.AXI_15_DFI_DW_RDDATA_DERR (AXI_15_DFI_DW_RDDATA_DERR_out),
.AXI_15_DFI_DW_RDDATA_VALID (AXI_15_DFI_DW_RDDATA_VALID_out),
.AXI_15_DFI_INIT_COMPLETE (AXI_15_DFI_INIT_COMPLETE_out),
.AXI_15_DFI_PHYUPD_REQ (AXI_15_DFI_PHYUPD_REQ_out),
.AXI_15_DFI_PHY_LP_STATE (AXI_15_DFI_PHY_LP_STATE_out),
.AXI_15_DFI_RST_N_BUF (AXI_15_DFI_RST_N_BUF_out),
.AXI_15_RDATA (AXI_15_RDATA_out),
.AXI_15_RDATA_PARITY (AXI_15_RDATA_PARITY_out),
.AXI_15_RID (AXI_15_RID_out),
.AXI_15_RLAST (AXI_15_RLAST_out),
.AXI_15_RRESP (AXI_15_RRESP_out),
.AXI_15_RVALID (AXI_15_RVALID_out),
.AXI_15_WREADY (AXI_15_WREADY_out),
.BLI_SCAN_OUT_00 (BLI_SCAN_OUT_00_out),
.BLI_SCAN_OUT_01 (BLI_SCAN_OUT_01_out),
.BLI_SCAN_OUT_02 (BLI_SCAN_OUT_02_out),
.BLI_SCAN_OUT_03 (BLI_SCAN_OUT_03_out),
.BLI_SCAN_OUT_04 (BLI_SCAN_OUT_04_out),
.BLI_SCAN_OUT_05 (BLI_SCAN_OUT_05_out),
.BLI_SCAN_OUT_06 (BLI_SCAN_OUT_06_out),
.BLI_SCAN_OUT_07 (BLI_SCAN_OUT_07_out),
.BLI_SCAN_OUT_08 (BLI_SCAN_OUT_08_out),
.BLI_SCAN_OUT_09 (BLI_SCAN_OUT_09_out),
.BLI_SCAN_OUT_10 (BLI_SCAN_OUT_10_out),
.BLI_SCAN_OUT_11 (BLI_SCAN_OUT_11_out),
.BLI_SCAN_OUT_12 (BLI_SCAN_OUT_12_out),
.BLI_SCAN_OUT_13 (BLI_SCAN_OUT_13_out),
.BLI_SCAN_OUT_14 (BLI_SCAN_OUT_14_out),
.BLI_SCAN_OUT_15 (BLI_SCAN_OUT_15_out),
.DBG_OUT_00 (DBG_OUT_00_out),
.DBG_OUT_01 (DBG_OUT_01_out),
.DBG_OUT_02 (DBG_OUT_02_out),
.DBG_OUT_03 (DBG_OUT_03_out),
.DBG_OUT_04 (DBG_OUT_04_out),
.DBG_OUT_05 (DBG_OUT_05_out),
.DBG_OUT_06 (DBG_OUT_06_out),
.DBG_OUT_07 (DBG_OUT_07_out),
.DBG_OUT_08 (DBG_OUT_08_out),
.DBG_OUT_09 (DBG_OUT_09_out),
.DBG_OUT_10 (DBG_OUT_10_out),
.DBG_OUT_11 (DBG_OUT_11_out),
.DBG_OUT_12 (DBG_OUT_12_out),
.DBG_OUT_13 (DBG_OUT_13_out),
.DBG_OUT_14 (DBG_OUT_14_out),
.DBG_OUT_15 (DBG_OUT_15_out),
.DLL_SCAN_OUT_00 (DLL_SCAN_OUT_00_out),
.DRAM_0_STAT_CATTRIP (DRAM_0_STAT_CATTRIP_out),
.DRAM_0_STAT_TEMP (DRAM_0_STAT_TEMP_out),
.IO_SCAN_OUT_00 (IO_SCAN_OUT_00_out),
.MC_SCAN_OUT_00 (MC_SCAN_OUT_00_out),
.MC_SCAN_OUT_01 (MC_SCAN_OUT_01_out),
.MC_SCAN_OUT_02 (MC_SCAN_OUT_02_out),
.MC_SCAN_OUT_03 (MC_SCAN_OUT_03_out),
.MC_SCAN_OUT_04 (MC_SCAN_OUT_04_out),
.MC_SCAN_OUT_05 (MC_SCAN_OUT_05_out),
.MC_SCAN_OUT_06 (MC_SCAN_OUT_06_out),
.MC_SCAN_OUT_07 (MC_SCAN_OUT_07_out),
.PHY_SCAN_OUT_00 (PHY_SCAN_OUT_00_out),
.STATUS_00 (STATUS_00_out),
.STATUS_01 (STATUS_01_out),
.STATUS_02 (STATUS_02_out),
.STATUS_03 (STATUS_03_out),
.STATUS_04 (STATUS_04_out),
.STATUS_05 (STATUS_05_out),
.STATUS_06 (STATUS_06_out),
.STATUS_07 (STATUS_07_out),
.SW_SCAN_OUT_00 (SW_SCAN_OUT_00_out),
.SW_SCAN_OUT_01 (SW_SCAN_OUT_01_out),
.SW_SCAN_OUT_02 (SW_SCAN_OUT_02_out),
.SW_SCAN_OUT_03 (SW_SCAN_OUT_03_out),
.ANALOG_HBM_SEL_00 (ANALOG_HBM_SEL_00_in),
.APB_0_PADDR (APB_0_PADDR_in),
.APB_0_PCLK (APB_0_PCLK_in),
.APB_0_PENABLE (APB_0_PENABLE_in),
.APB_0_PRESET_N (APB_0_PRESET_N_in),
.APB_0_PSEL (APB_0_PSEL_in),
.APB_0_PWDATA (APB_0_PWDATA_in),
.APB_0_PWRITE (APB_0_PWRITE_in),
.AXI_00_ACLK (AXI_00_ACLK_in),
.AXI_00_ARADDR (AXI_00_ARADDR_in),
.AXI_00_ARBURST (AXI_00_ARBURST_in),
.AXI_00_ARESET_N (AXI_00_ARESET_N_in),
.AXI_00_ARID (AXI_00_ARID_in),
.AXI_00_ARLEN (AXI_00_ARLEN_in),
.AXI_00_ARSIZE (AXI_00_ARSIZE_in),
.AXI_00_ARVALID (AXI_00_ARVALID_in),
.AXI_00_AWADDR (AXI_00_AWADDR_in),
.AXI_00_AWBURST (AXI_00_AWBURST_in),
.AXI_00_AWID (AXI_00_AWID_in),
.AXI_00_AWLEN (AXI_00_AWLEN_in),
.AXI_00_AWSIZE (AXI_00_AWSIZE_in),
.AXI_00_AWVALID (AXI_00_AWVALID_in),
.AXI_00_BREADY (AXI_00_BREADY_in),
.AXI_00_DFI_LP_PWR_X_REQ (AXI_00_DFI_LP_PWR_X_REQ_in),
.AXI_00_RREADY (AXI_00_RREADY_in),
.AXI_00_WDATA (AXI_00_WDATA_in),
.AXI_00_WDATA_PARITY (AXI_00_WDATA_PARITY_in),
.AXI_00_WLAST (AXI_00_WLAST_in),
.AXI_00_WSTRB (AXI_00_WSTRB_in),
.AXI_00_WVALID (AXI_00_WVALID_in),
.AXI_01_ACLK (AXI_01_ACLK_in),
.AXI_01_ARADDR (AXI_01_ARADDR_in),
.AXI_01_ARBURST (AXI_01_ARBURST_in),
.AXI_01_ARESET_N (AXI_01_ARESET_N_in),
.AXI_01_ARID (AXI_01_ARID_in),
.AXI_01_ARLEN (AXI_01_ARLEN_in),
.AXI_01_ARSIZE (AXI_01_ARSIZE_in),
.AXI_01_ARVALID (AXI_01_ARVALID_in),
.AXI_01_AWADDR (AXI_01_AWADDR_in),
.AXI_01_AWBURST (AXI_01_AWBURST_in),
.AXI_01_AWID (AXI_01_AWID_in),
.AXI_01_AWLEN (AXI_01_AWLEN_in),
.AXI_01_AWSIZE (AXI_01_AWSIZE_in),
.AXI_01_AWVALID (AXI_01_AWVALID_in),
.AXI_01_BREADY (AXI_01_BREADY_in),
.AXI_01_DFI_LP_PWR_X_REQ (AXI_01_DFI_LP_PWR_X_REQ_in),
.AXI_01_RREADY (AXI_01_RREADY_in),
.AXI_01_WDATA (AXI_01_WDATA_in),
.AXI_01_WDATA_PARITY (AXI_01_WDATA_PARITY_in),
.AXI_01_WLAST (AXI_01_WLAST_in),
.AXI_01_WSTRB (AXI_01_WSTRB_in),
.AXI_01_WVALID (AXI_01_WVALID_in),
.AXI_02_ACLK (AXI_02_ACLK_in),
.AXI_02_ARADDR (AXI_02_ARADDR_in),
.AXI_02_ARBURST (AXI_02_ARBURST_in),
.AXI_02_ARESET_N (AXI_02_ARESET_N_in),
.AXI_02_ARID (AXI_02_ARID_in),
.AXI_02_ARLEN (AXI_02_ARLEN_in),
.AXI_02_ARSIZE (AXI_02_ARSIZE_in),
.AXI_02_ARVALID (AXI_02_ARVALID_in),
.AXI_02_AWADDR (AXI_02_AWADDR_in),
.AXI_02_AWBURST (AXI_02_AWBURST_in),
.AXI_02_AWID (AXI_02_AWID_in),
.AXI_02_AWLEN (AXI_02_AWLEN_in),
.AXI_02_AWSIZE (AXI_02_AWSIZE_in),
.AXI_02_AWVALID (AXI_02_AWVALID_in),
.AXI_02_BREADY (AXI_02_BREADY_in),
.AXI_02_DFI_LP_PWR_X_REQ (AXI_02_DFI_LP_PWR_X_REQ_in),
.AXI_02_RREADY (AXI_02_RREADY_in),
.AXI_02_WDATA (AXI_02_WDATA_in),
.AXI_02_WDATA_PARITY (AXI_02_WDATA_PARITY_in),
.AXI_02_WLAST (AXI_02_WLAST_in),
.AXI_02_WSTRB (AXI_02_WSTRB_in),
.AXI_02_WVALID (AXI_02_WVALID_in),
.AXI_03_ACLK (AXI_03_ACLK_in),
.AXI_03_ARADDR (AXI_03_ARADDR_in),
.AXI_03_ARBURST (AXI_03_ARBURST_in),
.AXI_03_ARESET_N (AXI_03_ARESET_N_in),
.AXI_03_ARID (AXI_03_ARID_in),
.AXI_03_ARLEN (AXI_03_ARLEN_in),
.AXI_03_ARSIZE (AXI_03_ARSIZE_in),
.AXI_03_ARVALID (AXI_03_ARVALID_in),
.AXI_03_AWADDR (AXI_03_AWADDR_in),
.AXI_03_AWBURST (AXI_03_AWBURST_in),
.AXI_03_AWID (AXI_03_AWID_in),
.AXI_03_AWLEN (AXI_03_AWLEN_in),
.AXI_03_AWSIZE (AXI_03_AWSIZE_in),
.AXI_03_AWVALID (AXI_03_AWVALID_in),
.AXI_03_BREADY (AXI_03_BREADY_in),
.AXI_03_DFI_LP_PWR_X_REQ (AXI_03_DFI_LP_PWR_X_REQ_in),
.AXI_03_RREADY (AXI_03_RREADY_in),
.AXI_03_WDATA (AXI_03_WDATA_in),
.AXI_03_WDATA_PARITY (AXI_03_WDATA_PARITY_in),
.AXI_03_WLAST (AXI_03_WLAST_in),
.AXI_03_WSTRB (AXI_03_WSTRB_in),
.AXI_03_WVALID (AXI_03_WVALID_in),
.AXI_04_ACLK (AXI_04_ACLK_in),
.AXI_04_ARADDR (AXI_04_ARADDR_in),
.AXI_04_ARBURST (AXI_04_ARBURST_in),
.AXI_04_ARESET_N (AXI_04_ARESET_N_in),
.AXI_04_ARID (AXI_04_ARID_in),
.AXI_04_ARLEN (AXI_04_ARLEN_in),
.AXI_04_ARSIZE (AXI_04_ARSIZE_in),
.AXI_04_ARVALID (AXI_04_ARVALID_in),
.AXI_04_AWADDR (AXI_04_AWADDR_in),
.AXI_04_AWBURST (AXI_04_AWBURST_in),
.AXI_04_AWID (AXI_04_AWID_in),
.AXI_04_AWLEN (AXI_04_AWLEN_in),
.AXI_04_AWSIZE (AXI_04_AWSIZE_in),
.AXI_04_AWVALID (AXI_04_AWVALID_in),
.AXI_04_BREADY (AXI_04_BREADY_in),
.AXI_04_DFI_LP_PWR_X_REQ (AXI_04_DFI_LP_PWR_X_REQ_in),
.AXI_04_RREADY (AXI_04_RREADY_in),
.AXI_04_WDATA (AXI_04_WDATA_in),
.AXI_04_WDATA_PARITY (AXI_04_WDATA_PARITY_in),
.AXI_04_WLAST (AXI_04_WLAST_in),
.AXI_04_WSTRB (AXI_04_WSTRB_in),
.AXI_04_WVALID (AXI_04_WVALID_in),
.AXI_05_ACLK (AXI_05_ACLK_in),
.AXI_05_ARADDR (AXI_05_ARADDR_in),
.AXI_05_ARBURST (AXI_05_ARBURST_in),
.AXI_05_ARESET_N (AXI_05_ARESET_N_in),
.AXI_05_ARID (AXI_05_ARID_in),
.AXI_05_ARLEN (AXI_05_ARLEN_in),
.AXI_05_ARSIZE (AXI_05_ARSIZE_in),
.AXI_05_ARVALID (AXI_05_ARVALID_in),
.AXI_05_AWADDR (AXI_05_AWADDR_in),
.AXI_05_AWBURST (AXI_05_AWBURST_in),
.AXI_05_AWID (AXI_05_AWID_in),
.AXI_05_AWLEN (AXI_05_AWLEN_in),
.AXI_05_AWSIZE (AXI_05_AWSIZE_in),
.AXI_05_AWVALID (AXI_05_AWVALID_in),
.AXI_05_BREADY (AXI_05_BREADY_in),
.AXI_05_DFI_LP_PWR_X_REQ (AXI_05_DFI_LP_PWR_X_REQ_in),
.AXI_05_RREADY (AXI_05_RREADY_in),
.AXI_05_WDATA (AXI_05_WDATA_in),
.AXI_05_WDATA_PARITY (AXI_05_WDATA_PARITY_in),
.AXI_05_WLAST (AXI_05_WLAST_in),
.AXI_05_WSTRB (AXI_05_WSTRB_in),
.AXI_05_WVALID (AXI_05_WVALID_in),
.AXI_06_ACLK (AXI_06_ACLK_in),
.AXI_06_ARADDR (AXI_06_ARADDR_in),
.AXI_06_ARBURST (AXI_06_ARBURST_in),
.AXI_06_ARESET_N (AXI_06_ARESET_N_in),
.AXI_06_ARID (AXI_06_ARID_in),
.AXI_06_ARLEN (AXI_06_ARLEN_in),
.AXI_06_ARSIZE (AXI_06_ARSIZE_in),
.AXI_06_ARVALID (AXI_06_ARVALID_in),
.AXI_06_AWADDR (AXI_06_AWADDR_in),
.AXI_06_AWBURST (AXI_06_AWBURST_in),
.AXI_06_AWID (AXI_06_AWID_in),
.AXI_06_AWLEN (AXI_06_AWLEN_in),
.AXI_06_AWSIZE (AXI_06_AWSIZE_in),
.AXI_06_AWVALID (AXI_06_AWVALID_in),
.AXI_06_BREADY (AXI_06_BREADY_in),
.AXI_06_DFI_LP_PWR_X_REQ (AXI_06_DFI_LP_PWR_X_REQ_in),
.AXI_06_RREADY (AXI_06_RREADY_in),
.AXI_06_WDATA (AXI_06_WDATA_in),
.AXI_06_WDATA_PARITY (AXI_06_WDATA_PARITY_in),
.AXI_06_WLAST (AXI_06_WLAST_in),
.AXI_06_WSTRB (AXI_06_WSTRB_in),
.AXI_06_WVALID (AXI_06_WVALID_in),
.AXI_07_ACLK (AXI_07_ACLK_in),
.AXI_07_ARADDR (AXI_07_ARADDR_in),
.AXI_07_ARBURST (AXI_07_ARBURST_in),
.AXI_07_ARESET_N (AXI_07_ARESET_N_in),
.AXI_07_ARID (AXI_07_ARID_in),
.AXI_07_ARLEN (AXI_07_ARLEN_in),
.AXI_07_ARSIZE (AXI_07_ARSIZE_in),
.AXI_07_ARVALID (AXI_07_ARVALID_in),
.AXI_07_AWADDR (AXI_07_AWADDR_in),
.AXI_07_AWBURST (AXI_07_AWBURST_in),
.AXI_07_AWID (AXI_07_AWID_in),
.AXI_07_AWLEN (AXI_07_AWLEN_in),
.AXI_07_AWSIZE (AXI_07_AWSIZE_in),
.AXI_07_AWVALID (AXI_07_AWVALID_in),
.AXI_07_BREADY (AXI_07_BREADY_in),
.AXI_07_DFI_LP_PWR_X_REQ (AXI_07_DFI_LP_PWR_X_REQ_in),
.AXI_07_RREADY (AXI_07_RREADY_in),
.AXI_07_WDATA (AXI_07_WDATA_in),
.AXI_07_WDATA_PARITY (AXI_07_WDATA_PARITY_in),
.AXI_07_WLAST (AXI_07_WLAST_in),
.AXI_07_WSTRB (AXI_07_WSTRB_in),
.AXI_07_WVALID (AXI_07_WVALID_in),
.AXI_08_ACLK (AXI_08_ACLK_in),
.AXI_08_ARADDR (AXI_08_ARADDR_in),
.AXI_08_ARBURST (AXI_08_ARBURST_in),
.AXI_08_ARESET_N (AXI_08_ARESET_N_in),
.AXI_08_ARID (AXI_08_ARID_in),
.AXI_08_ARLEN (AXI_08_ARLEN_in),
.AXI_08_ARSIZE (AXI_08_ARSIZE_in),
.AXI_08_ARVALID (AXI_08_ARVALID_in),
.AXI_08_AWADDR (AXI_08_AWADDR_in),
.AXI_08_AWBURST (AXI_08_AWBURST_in),
.AXI_08_AWID (AXI_08_AWID_in),
.AXI_08_AWLEN (AXI_08_AWLEN_in),
.AXI_08_AWSIZE (AXI_08_AWSIZE_in),
.AXI_08_AWVALID (AXI_08_AWVALID_in),
.AXI_08_BREADY (AXI_08_BREADY_in),
.AXI_08_DFI_LP_PWR_X_REQ (AXI_08_DFI_LP_PWR_X_REQ_in),
.AXI_08_RREADY (AXI_08_RREADY_in),
.AXI_08_WDATA (AXI_08_WDATA_in),
.AXI_08_WDATA_PARITY (AXI_08_WDATA_PARITY_in),
.AXI_08_WLAST (AXI_08_WLAST_in),
.AXI_08_WSTRB (AXI_08_WSTRB_in),
.AXI_08_WVALID (AXI_08_WVALID_in),
.AXI_09_ACLK (AXI_09_ACLK_in),
.AXI_09_ARADDR (AXI_09_ARADDR_in),
.AXI_09_ARBURST (AXI_09_ARBURST_in),
.AXI_09_ARESET_N (AXI_09_ARESET_N_in),
.AXI_09_ARID (AXI_09_ARID_in),
.AXI_09_ARLEN (AXI_09_ARLEN_in),
.AXI_09_ARSIZE (AXI_09_ARSIZE_in),
.AXI_09_ARVALID (AXI_09_ARVALID_in),
.AXI_09_AWADDR (AXI_09_AWADDR_in),
.AXI_09_AWBURST (AXI_09_AWBURST_in),
.AXI_09_AWID (AXI_09_AWID_in),
.AXI_09_AWLEN (AXI_09_AWLEN_in),
.AXI_09_AWSIZE (AXI_09_AWSIZE_in),
.AXI_09_AWVALID (AXI_09_AWVALID_in),
.AXI_09_BREADY (AXI_09_BREADY_in),
.AXI_09_DFI_LP_PWR_X_REQ (AXI_09_DFI_LP_PWR_X_REQ_in),
.AXI_09_RREADY (AXI_09_RREADY_in),
.AXI_09_WDATA (AXI_09_WDATA_in),
.AXI_09_WDATA_PARITY (AXI_09_WDATA_PARITY_in),
.AXI_09_WLAST (AXI_09_WLAST_in),
.AXI_09_WSTRB (AXI_09_WSTRB_in),
.AXI_09_WVALID (AXI_09_WVALID_in),
.AXI_10_ACLK (AXI_10_ACLK_in),
.AXI_10_ARADDR (AXI_10_ARADDR_in),
.AXI_10_ARBURST (AXI_10_ARBURST_in),
.AXI_10_ARESET_N (AXI_10_ARESET_N_in),
.AXI_10_ARID (AXI_10_ARID_in),
.AXI_10_ARLEN (AXI_10_ARLEN_in),
.AXI_10_ARSIZE (AXI_10_ARSIZE_in),
.AXI_10_ARVALID (AXI_10_ARVALID_in),
.AXI_10_AWADDR (AXI_10_AWADDR_in),
.AXI_10_AWBURST (AXI_10_AWBURST_in),
.AXI_10_AWID (AXI_10_AWID_in),
.AXI_10_AWLEN (AXI_10_AWLEN_in),
.AXI_10_AWSIZE (AXI_10_AWSIZE_in),
.AXI_10_AWVALID (AXI_10_AWVALID_in),
.AXI_10_BREADY (AXI_10_BREADY_in),
.AXI_10_DFI_LP_PWR_X_REQ (AXI_10_DFI_LP_PWR_X_REQ_in),
.AXI_10_RREADY (AXI_10_RREADY_in),
.AXI_10_WDATA (AXI_10_WDATA_in),
.AXI_10_WDATA_PARITY (AXI_10_WDATA_PARITY_in),
.AXI_10_WLAST (AXI_10_WLAST_in),
.AXI_10_WSTRB (AXI_10_WSTRB_in),
.AXI_10_WVALID (AXI_10_WVALID_in),
.AXI_11_ACLK (AXI_11_ACLK_in),
.AXI_11_ARADDR (AXI_11_ARADDR_in),
.AXI_11_ARBURST (AXI_11_ARBURST_in),
.AXI_11_ARESET_N (AXI_11_ARESET_N_in),
.AXI_11_ARID (AXI_11_ARID_in),
.AXI_11_ARLEN (AXI_11_ARLEN_in),
.AXI_11_ARSIZE (AXI_11_ARSIZE_in),
.AXI_11_ARVALID (AXI_11_ARVALID_in),
.AXI_11_AWADDR (AXI_11_AWADDR_in),
.AXI_11_AWBURST (AXI_11_AWBURST_in),
.AXI_11_AWID (AXI_11_AWID_in),
.AXI_11_AWLEN (AXI_11_AWLEN_in),
.AXI_11_AWSIZE (AXI_11_AWSIZE_in),
.AXI_11_AWVALID (AXI_11_AWVALID_in),
.AXI_11_BREADY (AXI_11_BREADY_in),
.AXI_11_DFI_LP_PWR_X_REQ (AXI_11_DFI_LP_PWR_X_REQ_in),
.AXI_11_RREADY (AXI_11_RREADY_in),
.AXI_11_WDATA (AXI_11_WDATA_in),
.AXI_11_WDATA_PARITY (AXI_11_WDATA_PARITY_in),
.AXI_11_WLAST (AXI_11_WLAST_in),
.AXI_11_WSTRB (AXI_11_WSTRB_in),
.AXI_11_WVALID (AXI_11_WVALID_in),
.AXI_12_ACLK (AXI_12_ACLK_in),
.AXI_12_ARADDR (AXI_12_ARADDR_in),
.AXI_12_ARBURST (AXI_12_ARBURST_in),
.AXI_12_ARESET_N (AXI_12_ARESET_N_in),
.AXI_12_ARID (AXI_12_ARID_in),
.AXI_12_ARLEN (AXI_12_ARLEN_in),
.AXI_12_ARSIZE (AXI_12_ARSIZE_in),
.AXI_12_ARVALID (AXI_12_ARVALID_in),
.AXI_12_AWADDR (AXI_12_AWADDR_in),
.AXI_12_AWBURST (AXI_12_AWBURST_in),
.AXI_12_AWID (AXI_12_AWID_in),
.AXI_12_AWLEN (AXI_12_AWLEN_in),
.AXI_12_AWSIZE (AXI_12_AWSIZE_in),
.AXI_12_AWVALID (AXI_12_AWVALID_in),
.AXI_12_BREADY (AXI_12_BREADY_in),
.AXI_12_DFI_LP_PWR_X_REQ (AXI_12_DFI_LP_PWR_X_REQ_in),
.AXI_12_RREADY (AXI_12_RREADY_in),
.AXI_12_WDATA (AXI_12_WDATA_in),
.AXI_12_WDATA_PARITY (AXI_12_WDATA_PARITY_in),
.AXI_12_WLAST (AXI_12_WLAST_in),
.AXI_12_WSTRB (AXI_12_WSTRB_in),
.AXI_12_WVALID (AXI_12_WVALID_in),
.AXI_13_ACLK (AXI_13_ACLK_in),
.AXI_13_ARADDR (AXI_13_ARADDR_in),
.AXI_13_ARBURST (AXI_13_ARBURST_in),
.AXI_13_ARESET_N (AXI_13_ARESET_N_in),
.AXI_13_ARID (AXI_13_ARID_in),
.AXI_13_ARLEN (AXI_13_ARLEN_in),
.AXI_13_ARSIZE (AXI_13_ARSIZE_in),
.AXI_13_ARVALID (AXI_13_ARVALID_in),
.AXI_13_AWADDR (AXI_13_AWADDR_in),
.AXI_13_AWBURST (AXI_13_AWBURST_in),
.AXI_13_AWID (AXI_13_AWID_in),
.AXI_13_AWLEN (AXI_13_AWLEN_in),
.AXI_13_AWSIZE (AXI_13_AWSIZE_in),
.AXI_13_AWVALID (AXI_13_AWVALID_in),
.AXI_13_BREADY (AXI_13_BREADY_in),
.AXI_13_DFI_LP_PWR_X_REQ (AXI_13_DFI_LP_PWR_X_REQ_in),
.AXI_13_RREADY (AXI_13_RREADY_in),
.AXI_13_WDATA (AXI_13_WDATA_in),
.AXI_13_WDATA_PARITY (AXI_13_WDATA_PARITY_in),
.AXI_13_WLAST (AXI_13_WLAST_in),
.AXI_13_WSTRB (AXI_13_WSTRB_in),
.AXI_13_WVALID (AXI_13_WVALID_in),
.AXI_14_ACLK (AXI_14_ACLK_in),
.AXI_14_ARADDR (AXI_14_ARADDR_in),
.AXI_14_ARBURST (AXI_14_ARBURST_in),
.AXI_14_ARESET_N (AXI_14_ARESET_N_in),
.AXI_14_ARID (AXI_14_ARID_in),
.AXI_14_ARLEN (AXI_14_ARLEN_in),
.AXI_14_ARSIZE (AXI_14_ARSIZE_in),
.AXI_14_ARVALID (AXI_14_ARVALID_in),
.AXI_14_AWADDR (AXI_14_AWADDR_in),
.AXI_14_AWBURST (AXI_14_AWBURST_in),
.AXI_14_AWID (AXI_14_AWID_in),
.AXI_14_AWLEN (AXI_14_AWLEN_in),
.AXI_14_AWSIZE (AXI_14_AWSIZE_in),
.AXI_14_AWVALID (AXI_14_AWVALID_in),
.AXI_14_BREADY (AXI_14_BREADY_in),
.AXI_14_DFI_LP_PWR_X_REQ (AXI_14_DFI_LP_PWR_X_REQ_in),
.AXI_14_RREADY (AXI_14_RREADY_in),
.AXI_14_WDATA (AXI_14_WDATA_in),
.AXI_14_WDATA_PARITY (AXI_14_WDATA_PARITY_in),
.AXI_14_WLAST (AXI_14_WLAST_in),
.AXI_14_WSTRB (AXI_14_WSTRB_in),
.AXI_14_WVALID (AXI_14_WVALID_in),
.AXI_15_ACLK (AXI_15_ACLK_in),
.AXI_15_ARADDR (AXI_15_ARADDR_in),
.AXI_15_ARBURST (AXI_15_ARBURST_in),
.AXI_15_ARESET_N (AXI_15_ARESET_N_in),
.AXI_15_ARID (AXI_15_ARID_in),
.AXI_15_ARLEN (AXI_15_ARLEN_in),
.AXI_15_ARSIZE (AXI_15_ARSIZE_in),
.AXI_15_ARVALID (AXI_15_ARVALID_in),
.AXI_15_AWADDR (AXI_15_AWADDR_in),
.AXI_15_AWBURST (AXI_15_AWBURST_in),
.AXI_15_AWID (AXI_15_AWID_in),
.AXI_15_AWLEN (AXI_15_AWLEN_in),
.AXI_15_AWSIZE (AXI_15_AWSIZE_in),
.AXI_15_AWVALID (AXI_15_AWVALID_in),
.AXI_15_BREADY (AXI_15_BREADY_in),
.AXI_15_DFI_LP_PWR_X_REQ (AXI_15_DFI_LP_PWR_X_REQ_in),
.AXI_15_RREADY (AXI_15_RREADY_in),
.AXI_15_WDATA (AXI_15_WDATA_in),
.AXI_15_WDATA_PARITY (AXI_15_WDATA_PARITY_in),
.AXI_15_WLAST (AXI_15_WLAST_in),
.AXI_15_WSTRB (AXI_15_WSTRB_in),
.AXI_15_WVALID (AXI_15_WVALID_in),
.BLI_SCAN_ENABLE_00 (BLI_SCAN_ENABLE_00_in),
.BLI_SCAN_ENABLE_01 (BLI_SCAN_ENABLE_01_in),
.BLI_SCAN_ENABLE_02 (BLI_SCAN_ENABLE_02_in),
.BLI_SCAN_ENABLE_03 (BLI_SCAN_ENABLE_03_in),
.BLI_SCAN_ENABLE_04 (BLI_SCAN_ENABLE_04_in),
.BLI_SCAN_ENABLE_05 (BLI_SCAN_ENABLE_05_in),
.BLI_SCAN_ENABLE_06 (BLI_SCAN_ENABLE_06_in),
.BLI_SCAN_ENABLE_07 (BLI_SCAN_ENABLE_07_in),
.BLI_SCAN_ENABLE_08 (BLI_SCAN_ENABLE_08_in),
.BLI_SCAN_ENABLE_09 (BLI_SCAN_ENABLE_09_in),
.BLI_SCAN_ENABLE_10 (BLI_SCAN_ENABLE_10_in),
.BLI_SCAN_ENABLE_11 (BLI_SCAN_ENABLE_11_in),
.BLI_SCAN_ENABLE_12 (BLI_SCAN_ENABLE_12_in),
.BLI_SCAN_ENABLE_13 (BLI_SCAN_ENABLE_13_in),
.BLI_SCAN_ENABLE_14 (BLI_SCAN_ENABLE_14_in),
.BLI_SCAN_ENABLE_15 (BLI_SCAN_ENABLE_15_in),
.BLI_SCAN_IN_00 (BLI_SCAN_IN_00_in),
.BLI_SCAN_IN_01 (BLI_SCAN_IN_01_in),
.BLI_SCAN_IN_02 (BLI_SCAN_IN_02_in),
.BLI_SCAN_IN_03 (BLI_SCAN_IN_03_in),
.BLI_SCAN_IN_04 (BLI_SCAN_IN_04_in),
.BLI_SCAN_IN_05 (BLI_SCAN_IN_05_in),
.BLI_SCAN_IN_06 (BLI_SCAN_IN_06_in),
.BLI_SCAN_IN_07 (BLI_SCAN_IN_07_in),
.BLI_SCAN_IN_08 (BLI_SCAN_IN_08_in),
.BLI_SCAN_IN_09 (BLI_SCAN_IN_09_in),
.BLI_SCAN_IN_10 (BLI_SCAN_IN_10_in),
.BLI_SCAN_IN_11 (BLI_SCAN_IN_11_in),
.BLI_SCAN_IN_12 (BLI_SCAN_IN_12_in),
.BLI_SCAN_IN_13 (BLI_SCAN_IN_13_in),
.BLI_SCAN_IN_14 (BLI_SCAN_IN_14_in),
.BLI_SCAN_IN_15 (BLI_SCAN_IN_15_in),
.BSCAN_DRCK (BSCAN_DRCK_in),
.BSCAN_TCK (BSCAN_TCK_in),
.DBG_IN_00 (DBG_IN_00_in),
.DBG_IN_01 (DBG_IN_01_in),
.DBG_IN_02 (DBG_IN_02_in),
.DBG_IN_03 (DBG_IN_03_in),
.DBG_IN_04 (DBG_IN_04_in),
.DBG_IN_05 (DBG_IN_05_in),
.DBG_IN_06 (DBG_IN_06_in),
.DBG_IN_07 (DBG_IN_07_in),
.DBG_IN_08 (DBG_IN_08_in),
.DBG_IN_09 (DBG_IN_09_in),
.DBG_IN_10 (DBG_IN_10_in),
.DBG_IN_11 (DBG_IN_11_in),
.DBG_IN_12 (DBG_IN_12_in),
.DBG_IN_13 (DBG_IN_13_in),
.DBG_IN_14 (DBG_IN_14_in),
.DBG_IN_15 (DBG_IN_15_in),
.DLL_SCAN_CK_00 (DLL_SCAN_CK_00_in),
.DLL_SCAN_ENABLE_00 (DLL_SCAN_ENABLE_00_in),
.DLL_SCAN_IN_00 (DLL_SCAN_IN_00_in),
.DLL_SCAN_MODE_00 (DLL_SCAN_MODE_00_in),
.DLL_SCAN_RST_N_00 (DLL_SCAN_RST_N_00_in),
.HBM_REF_CLK (HBM_REF_CLK_in),
.IO_SCAN_CK_00 (IO_SCAN_CK_00_in),
.IO_SCAN_ENABLE_00 (IO_SCAN_ENABLE_00_in),
.IO_SCAN_IN_00 (IO_SCAN_IN_00_in),
.IO_SCAN_MODE_00 (IO_SCAN_MODE_00_in),
.IO_SCAN_RST_N_00 (IO_SCAN_RST_N_00_in),
.MBIST_EN_00 (MBIST_EN_00_in),
.MBIST_EN_01 (MBIST_EN_01_in),
.MBIST_EN_02 (MBIST_EN_02_in),
.MBIST_EN_03 (MBIST_EN_03_in),
.MBIST_EN_04 (MBIST_EN_04_in),
.MBIST_EN_05 (MBIST_EN_05_in),
.MBIST_EN_06 (MBIST_EN_06_in),
.MBIST_EN_07 (MBIST_EN_07_in),
.MC_SCAN_CK_00 (MC_SCAN_CK_00_in),
.MC_SCAN_CK_01 (MC_SCAN_CK_01_in),
.MC_SCAN_CK_02 (MC_SCAN_CK_02_in),
.MC_SCAN_CK_03 (MC_SCAN_CK_03_in),
.MC_SCAN_CK_04 (MC_SCAN_CK_04_in),
.MC_SCAN_CK_05 (MC_SCAN_CK_05_in),
.MC_SCAN_CK_06 (MC_SCAN_CK_06_in),
.MC_SCAN_CK_07 (MC_SCAN_CK_07_in),
.MC_SCAN_ENABLE_00 (MC_SCAN_ENABLE_00_in),
.MC_SCAN_ENABLE_01 (MC_SCAN_ENABLE_01_in),
.MC_SCAN_ENABLE_02 (MC_SCAN_ENABLE_02_in),
.MC_SCAN_ENABLE_03 (MC_SCAN_ENABLE_03_in),
.MC_SCAN_ENABLE_04 (MC_SCAN_ENABLE_04_in),
.MC_SCAN_ENABLE_05 (MC_SCAN_ENABLE_05_in),
.MC_SCAN_ENABLE_06 (MC_SCAN_ENABLE_06_in),
.MC_SCAN_ENABLE_07 (MC_SCAN_ENABLE_07_in),
.MC_SCAN_IN_00 (MC_SCAN_IN_00_in),
.MC_SCAN_IN_01 (MC_SCAN_IN_01_in),
.MC_SCAN_IN_02 (MC_SCAN_IN_02_in),
.MC_SCAN_IN_03 (MC_SCAN_IN_03_in),
.MC_SCAN_IN_04 (MC_SCAN_IN_04_in),
.MC_SCAN_IN_05 (MC_SCAN_IN_05_in),
.MC_SCAN_IN_06 (MC_SCAN_IN_06_in),
.MC_SCAN_IN_07 (MC_SCAN_IN_07_in),
.MC_SCAN_MODE_00 (MC_SCAN_MODE_00_in),
.MC_SCAN_MODE_01 (MC_SCAN_MODE_01_in),
.MC_SCAN_MODE_02 (MC_SCAN_MODE_02_in),
.MC_SCAN_MODE_03 (MC_SCAN_MODE_03_in),
.MC_SCAN_MODE_04 (MC_SCAN_MODE_04_in),
.MC_SCAN_MODE_05 (MC_SCAN_MODE_05_in),
.MC_SCAN_MODE_06 (MC_SCAN_MODE_06_in),
.MC_SCAN_MODE_07 (MC_SCAN_MODE_07_in),
.MC_SCAN_RST_N_00 (MC_SCAN_RST_N_00_in),
.MC_SCAN_RST_N_01 (MC_SCAN_RST_N_01_in),
.MC_SCAN_RST_N_02 (MC_SCAN_RST_N_02_in),
.MC_SCAN_RST_N_03 (MC_SCAN_RST_N_03_in),
.MC_SCAN_RST_N_04 (MC_SCAN_RST_N_04_in),
.MC_SCAN_RST_N_05 (MC_SCAN_RST_N_05_in),
.MC_SCAN_RST_N_06 (MC_SCAN_RST_N_06_in),
.MC_SCAN_RST_N_07 (MC_SCAN_RST_N_07_in),
.PHY_SCAN_CK_00 (PHY_SCAN_CK_00_in),
.PHY_SCAN_ENABLE_00 (PHY_SCAN_ENABLE_00_in),
.PHY_SCAN_IN_00 (PHY_SCAN_IN_00_in),
.PHY_SCAN_MODE_00 (PHY_SCAN_MODE_00_in),
.PHY_SCAN_RST_N_00 (PHY_SCAN_RST_N_00_in),
.SW_SCAN_CK_00 (SW_SCAN_CK_00_in),
.SW_SCAN_ENABLE_00 (SW_SCAN_ENABLE_00_in),
.SW_SCAN_IN_00 (SW_SCAN_IN_00_in),
.SW_SCAN_IN_01 (SW_SCAN_IN_01_in),
.SW_SCAN_IN_02 (SW_SCAN_IN_02_in),
.SW_SCAN_IN_03 (SW_SCAN_IN_03_in),
.SW_SCAN_MODE_00 (SW_SCAN_MODE_00_in),
.SW_SCAN_RST_N_00 (SW_SCAN_RST_N_00_in),
.GSR (glblGSR)
);
endmodule
|
module network_module(
input clk156,
input reset,
input aresetn,
input dclk,
input txusrclk,
input txusrclk2,
output txclk322,
//input ref_clk_n,
input areset_refclk_bufh,
input areset_clk156,
input mmcm_locked_clk156,
input gttxreset_txusrclk2,
input gttxreset,
input gtrxreset,
input txuserrdy,
input qplllock,
input qplloutclk,
input qplloutrefclk,
input reset_counter_done,
output tx_resetdone,
output txp,
output txn,
input rxp,
input rxn,
//Axi Stream Interface
input[63:0] tx_axis_tdata,
input tx_axis_tvalid,
input tx_axis_tlast,
input tx_axis_tuser,
input[7:0] tx_axis_tkeep,
output tx_axis_tready,
output[63:0] rx_axis_tdata,
output rx_axis_tvalid,
output rx_axis_tlast,
output rx_axis_tuser,
output[7:0] rx_axis_tkeep,
input rx_axis_tready,
input core_reset, //TODO
input tx_fault,
input signal_detect,
// input[4:0] prtad,
input[7:0] tx_ifg_delay,
output tx_disable,
//status signals
output rx_fifo_overflow,
output [29:0] rx_statistics_vector,
output rx_statistics_valid,
output[7:0] core_status
);
wire[535:0] configuration_vector;
assign configuration_vector = 0;
wire[63:0] xgmii_txd;
wire[7:0] xgmii_txc;
wire[63:0] xgmii_rxd;
wire[7:0] xgmii_rxc;
reg[63:0] xgmii_txd_reg;
reg[7:0] xgmii_txc_reg;
reg[63:0] xgmii_rxd_reg;
reg[7:0] xgmii_rxc_reg;
reg[63:0] xgmii_txd_reg2;
reg[7:0] xgmii_txc_reg2;
reg[63:0] xgmii_rxd_reg2;
reg[7:0] xgmii_rxc_reg2;
reg[63:0] xgmii_txd_reg3;
reg[7:0] xgmii_txc_reg3;
reg[63:0] xgmii_rxd_reg3;
reg[7:0] xgmii_rxc_reg3;
wire[63:0] axi_str_tdata_to_xgmac;
wire[7:0] axi_str_tkeep_to_xgmac;
wire axi_str_tvalid_to_xgmac;
wire axi_str_tlast_to_xgmac;
wire axi_str_tready_to_xgmac;
wire[63:0] axi_str_rd_tdata_to_fifo;
wire[7:0] axi_str_rd_tkeep_to_fifo;
wire[0:0] axi_str_rd_tuser_to_fifo;
wire axi_str_rd_tvalid_to_fifo;
wire axi_str_rd_tlast_to_fifo;
// Wires for axi register slices
wire tx_axis_slice2interface_tvalid;
wire tx_axis_slice2interface_tready;
wire[63:0] tx_axis_slice2interface_tdata;
wire[7:0] tx_axis_slice2interface_tkeep;
wire tx_axis_slice2interface_tlast;
wire rx_axis_interface2slice_tvalid;
wire rx_axis_interface2slice_tready;
wire[63:0] rx_axis_interface2slice_tdata;
wire[7:0] rx_axis_interface2slice_tkeep;
wire rx_axis_interface2slice_tlast;
//wire resetdone;
//assign resetdone = tx_resetdone & rx_resetdone;
// Delay serial paths
always @(posedge clk156) begin
xgmii_rxd_reg <= xgmii_rxd;
xgmii_rxc_reg <= xgmii_rxc;
xgmii_txd_reg <= xgmii_txd;
xgmii_txc_reg <= xgmii_txc;
xgmii_rxd_reg2 <= xgmii_rxd_reg;
xgmii_rxc_reg2 <= xgmii_rxc_reg;
xgmii_txd_reg2 <= xgmii_txd_reg;
xgmii_txc_reg2 <= xgmii_txc_reg;
xgmii_rxd_reg3 <= xgmii_rxd_reg2;
xgmii_rxc_reg3 <= xgmii_rxc_reg2;
xgmii_txd_reg3 <= xgmii_txd_reg2;
xgmii_txc_reg3 <= xgmii_txc_reg2;
/*if (reset == 1'b1) begin
xgmii_rxd_reg <= 0;
xgmii_rxc_reg <= 0;
xgmii_txd_reg <= 0;
xgmii_txc_reg <= 0;
end
else begin
xgmii_rxd_reg <= xgmii_rxd;
xgmii_rxc_reg <= xgmii_rxc;
xgmii_txd_reg <= xgmii_txd;
xgmii_txc_reg <= xgmii_txc;
end*/
end
wire drp_req; // output wire drp_req
wire drp_den_o; // output wire drp_den_o
wire drp_dwe_o; // output wire drp_dwe_o
wire[15:0] drp_daddr_o; // output wire [15 : 0] drp_daddr_o
wire[15:0] drp_di_o; // output wire [15 : 0] drp_di_o
wire drp_drdy_o; // output wire drp_drdy_o
wire[15:0] drp_drpdo_o; // output wire [15 : 0] drp_drpdo_o
ten_gig_eth_pcs_pma_ip //# (
//.EXAMPLE_SIM_GTRESET_SPEEDUP("TRUE") ) //Does not affect hardware
ten_gig_eth_pcs_pma_inst
(
.coreclk(clk156),
.dclk(dclk),
.txusrclk(txusrclk),
.txusrclk2(txusrclk2),
.areset(reset),
.txoutclk(txclk322),
//.areset_refclk_bufh(areset_refclk_bufh),
.areset_coreclk(areset_clk156),
//.mmcm_locked_clk156(mmcm_locked_clk156),
//.gttxreset_txusrclk2(gttxreset_txusrclk2),
.gttxreset(gttxreset),
.gtrxreset(gtrxreset),
.txuserrdy(txuserrdy),
.qplllock(qplllock),
.qplloutclk(qplloutclk),
.qplloutrefclk(qplloutrefclk),
.reset_counter_done(reset_counter_done),
.xgmii_txd(xgmii_txd_reg3),
.xgmii_txc(xgmii_txc_reg3),
.xgmii_rxd(xgmii_rxd),
.xgmii_rxc(xgmii_rxc),
.txp(txp),
.txn(txn),
.rxp(rxp),
.rxn(rxn),
.configuration_vector(configuration_vector),
.status_vector(),
.core_status(core_status),
.tx_resetdone(tx_resetdone),
.rx_resetdone(),
.signal_detect(signal_detect),
.tx_fault(tx_fault),
//extra drp signals introduced in vivado 2013.4 core gen
.drp_req(drp_req), // output wire drp_req
.drp_gnt(drp_req), // input wire drp_gnt
.drp_den_o(drp_den_o), // output wire drp_den_o
.drp_dwe_o(drp_dwe_o), // output wire drp_dwe_o
.drp_daddr_o(drp_daddr_o), // output wire [15 : 0] drp_daddr_o
.drp_di_o(drp_di_o), // output wire [15 : 0] drp_di_o
.drp_drdy_o(drp_drdy_o), // output wire drp_drdy_o
.drp_drpdo_o(drp_drpdo_o), // output wire [15 : 0] drp_drpdo_o
.drp_den_i(drp_den_o), // input wire drp_den_i
.drp_dwe_i(drp_dwe_o), // input wire drp_dwe_i
.drp_daddr_i(drp_daddr_o), // input wire [15 : 0] drp_daddr_i
.drp_di_i(drp_di_o), // input wire [15 : 0] drp_di_i
.drp_drdy_i(drp_drdy_o), // input wire drp_drdy_i
.drp_drpdo_i(drp_drpdo_o),
.pma_pmd_type(3'b101),
//.pma_pmd_type(pma_pmd_type),
.tx_disable(tx_disable),
.sim_speedup_control(1'b0)
);
ten_gig_eth_mac_ip ten_gig_eth_mac_inst
(
.reset(reset),
.tx_axis_aresetn(~reset),
.tx_axis_tdata(axi_str_tdata_to_xgmac),
.tx_axis_tvalid(axi_str_tvalid_to_xgmac),
.tx_axis_tlast(axi_str_tlast_to_xgmac),
.tx_axis_tuser(1'b0),
.tx_ifg_delay(tx_ifg_delay),
.tx_axis_tkeep(axi_str_tkeep_to_xgmac),
.tx_axis_tready(axi_str_tready_from_xgmac),
.tx_statistics_vector(),
.tx_statistics_valid(),
.rx_axis_aresetn(~reset),
.rx_axis_tdata(axi_str_rd_tdata_to_fifo),
.rx_axis_tvalid(axi_str_rd_tvalid_to_fifo),
.rx_axis_tuser(axi_str_rd_tuser_to_fifo),
.rx_axis_tlast(axi_str_rd_tlast_to_fifo),
.rx_axis_tkeep(axi_str_rd_tkeep_to_fifo),
.rx_statistics_vector(rx_statistics_vector),
.rx_statistics_valid(rx_statistics_valid),
.pause_val(16'b0),
.pause_req(1'b0),
.tx_configuration_vector(80'h00000000000000000016),
.rx_configuration_vector(80'h00000000000000000016),
.status_vector(),
.tx_clk0(clk156),
.tx_dcm_locked(mmcm_locked_clk156),
.xgmii_txd(xgmii_txd),
.xgmii_txc(xgmii_txc),
.rx_clk0(clk156),
.rx_dcm_locked(mmcm_locked_clk156),
.xgmii_rxd(xgmii_rxd_reg3),
.xgmii_rxc(xgmii_rxc_reg3)
);
/*rx_interface
rx_interface_i (
.axi_str_tdata_from_xgmac (axi_str_rd_tdata_to_fifo ),
.axi_str_tkeep_from_xgmac (axi_str_rd_tkeep_to_fifo ),
.axi_str_tvalid_from_xgmac (axi_str_rd_tvalid_to_fifo ),
.axi_str_tlast_from_xgmac (axi_str_rd_tlast_to_fifo ),
.axi_str_tuser_from_xgmac (axi_str_rd_tuser_to_fifo ),
//.mac_id (48'h000000000000 ),
//.mac_id_valid (1'b0 ),
.rx_statistics_vector (rx_statistics_vector ),
.rx_statistics_valid (rx_statistics_valid ),
//.promiscuous_mode_en (1'b0 ),
.axi_str_tready_from_fifo (rx_axis_interface2slice_tready),
.axi_str_tdata_to_fifo (rx_axis_interface2slice_tdata),
.axi_str_tkeep_to_fifo (rx_axis_interface2slice_tkeep),
.axi_str_tvalid_to_fifo (rx_axis_interface2slice_tvalid),
.axi_str_tlast_to_fifo (rx_axis_interface2slice_tlast),
.rd_data_count ( ), //TODO
.rd_pkt_len ( ),
.rx_fifo_overflow (rx_fifo_overflow), //TODO
.user_clk (clk156 ),
.soft_reset (reset ),
.reset (reset )
);*/
rx_isolation rx_interface_i (
.axi_str_tdata_from_xgmac (axi_str_rd_tdata_to_fifo ),
.axi_str_tkeep_from_xgmac (axi_str_rd_tkeep_to_fifo ),
.axi_str_tvalid_from_xgmac (axi_str_rd_tvalid_to_fifo ),
.axi_str_tlast_from_xgmac (axi_str_rd_tlast_to_fifo ),
.axi_str_tready_from_fifo (rx_axis_interface2slice_tready),
.axi_str_tdata_to_fifo (rx_axis_interface2slice_tdata),
.axi_str_tkeep_to_fifo (rx_axis_interface2slice_tkeep),
.axi_str_tvalid_to_fifo (rx_axis_interface2slice_tvalid),
.axi_str_tlast_to_fifo (rx_axis_interface2slice_tlast),
.user_clk (clk156),
.reset (reset)
);
tx_interface tx_interface_i (
//tx_isolation tx_interface_i (
.axi_str_tdata_to_xgmac (axi_str_tdata_to_xgmac ),
.axi_str_tkeep_to_xgmac (axi_str_tkeep_to_xgmac ),
.axi_str_tvalid_to_xgmac (axi_str_tvalid_to_xgmac ),
.axi_str_tlast_to_xgmac (axi_str_tlast_to_xgmac ),
.axi_str_tuser_to_xgmac (axi_str_tuser_to_xgmac ),
.axi_str_tready_from_xgmac(axi_str_tready_from_xgmac ),
.axi_str_tready_to_fifo (tx_axis_slice2interface_tready),
.axi_str_tdata_from_fifo (tx_axis_slice2interface_tdata),
.axi_str_tkeep_from_fifo (tx_axis_slice2interface_tkeep),
.axi_str_tvalid_from_fifo (tx_axis_slice2interface_tvalid),
.axi_str_tlast_from_fifo (tx_axis_slice2interface_tlast),
.user_clk (clk156),
.reset (reset)
);
// TX Input Slice
axis_register_slice_64 axis_register_input_slice(
.aclk(clk156),
.aresetn(aresetn),
.s_axis_tvalid(tx_axis_tvalid),
.s_axis_tready(tx_axis_tready),
.s_axis_tdata(tx_axis_tdata),
.s_axis_tkeep(tx_axis_tkeep),
.s_axis_tlast(tx_axis_tlast),
.m_axis_tvalid(tx_axis_slice2interface_tvalid),
.m_axis_tready(tx_axis_slice2interface_tready),
.m_axis_tdata(tx_axis_slice2interface_tdata),
.m_axis_tkeep(tx_axis_slice2interface_tkeep),
.m_axis_tlast(tx_axis_slice2interface_tlast)
);
// RX Output slice
axis_register_slice_64 axis_register_output_slice(
.aclk(clk156),
.aresetn(aresetn),
.s_axis_tvalid(rx_axis_interface2slice_tvalid),
.s_axis_tready(rx_axis_interface2slice_tready),
.s_axis_tdata(rx_axis_interface2slice_tdata),
.s_axis_tkeep(rx_axis_interface2slice_tkeep),
.s_axis_tlast(rx_axis_interface2slice_tlast),
.m_axis_tvalid(rx_axis_tvalid),
.m_axis_tready(rx_axis_tready),
.m_axis_tdata(rx_axis_tdata),
.m_axis_tkeep(rx_axis_tkeep),
.m_axis_tlast(rx_axis_tlast)
);
endmodule
|
module interface
assign d_out = d_out_3;
assign empty = !full_3; // if the last stage is empty, the fifo is empty
assign si = shift_in;
assign so = shift_out;
wire [ADDRSIZE:0] fifo_ram_count = wa_m - ra_m;
assign mux_rm_2 = full_r2; // mux control of SRAM data bypass if only one value in stage r2
assign d_out_2 = mux_rm_2 ? d_out_r2 : d_out_m2; // additional data mux for SRAM bypass
// write port control of SRAM
assign wen = si && !so && full_1 // enter new value into SRAM, because regs are filled
|| si && !m_empty; // if a value is in the SRAM, then we have to shift through or shift in
// read port control of SRAM
assign ren = so && !m_empty;
assign m_empty = (wa_m == ra_m);
always @ (posedge clk or negedge res_n) begin
if (!res_n) begin
full_m1 <= 1'b0;
full_m2 <= 1'b0;
end else begin
full_m1 <= ren; // no control of m1
full_m2 <= full_m1
|| full_m2 && !so && full_r2; // no rescue possible
end
end
// pointer management
always @(*) begin
wa = wa_m + 1'b1; // wa_m is the address stored in mem addr register
ra = ra_m + 1'b1;
end
always @ (posedge clk or negedge res_n) begin
if (!res_n) begin
wa_m <= {ADDRSIZE {1'b0}};
ra_m <= {ADDRSIZE {1'b0}};
end else begin
if (wen) begin
wa_m <= wa; // next mem write addr to mem addr register
end
if (ren) begin
ra_m <= ra;
end
end
end
//=====================================================================================================
//-----------------------------------------------------------------------------------------------------
//---------INSTANTIATIONS HERE-------------------------------------------------------------------------
//-----------------------------------------------------------------------------------------------------
//=====================================================================================================
openhmc_sync_fifo_reg_stage #(.DWIDTH(DATASIZE))
sync_fifo_reg_stage_3_I (
.clk(clk),
.res_n(res_n),
.d_in(d_in),
.d_in_p(d_out_2),
.p_full(full_2),
.n_full(1'b1),
.si(si),
.so(so),
.full(full_3),
.d_out(d_out_3)
);
openhmc_ram #(
.DATASIZE(DATASIZE), // Memory data word width
.ADDRSIZE(ADDRSIZE), // Number of memory address bits
.PIPELINED(1)
)
ram(
.clk(clk),
.wen(wen),
.wdata(d_in),
.waddr(wa),
.ren(ren),
.raddr(ra),
.rdata(d_out_m2)
);
`ifdef CAG_ASSERTIONS
if (DISABLE_SHIFT_OUT_ASSERT == 0)
shift_out_and_empty: assert property (@(posedge clk) disable iff(!res_n) (shift_out |-> !empty));
if (DISABLE_XCHECK_ASSERT == 0)
dout_known: assert property (@(posedge clk) disable iff(!res_n) (!empty |-> !$isunknown(d_out)));
final
begin
if (DISABLE_EMPTY_ASSERT == 0)
begin
empty_not_set_assert: assert (empty);
end
end
`endif // CAG_ASSERTIONS
endmodule
|
module inputs)
reg [13-1:0] Addr; // To memory of IS42S16160.v
reg [1:0] Ba; // To memory of IS42S16160.v
reg CLOCK_100; // To controller of sdram_controller3.v
reg CLOCK_100_del_3ns; // To controller of sdram_controller3.v
reg CLOCK_50; // To controller of sdram_controller3.v
reg Cas_n; // To memory of IS42S16160.v
reg Cke; // To memory of IS42S16160.v
reg Clk; // To memory of IS42S16160.v
reg Cs_n; // To memory of IS42S16160.v
reg [1:0] Dqm; // To memory of IS42S16160.v
reg Ras_n; // To memory of IS42S16160.v
reg We_n; // To memory of IS42S16160.v
reg [23:0] address; // To controller of sdram_controller3.v
reg clk; // To core of core.v
reg [31:0] data_in; // To controller of sdram_controller3.v
reg rst; // To controller of sdram_controller3.v
reg rx; // To core of core.v
reg [3:0] switches; // To core of core.v
wire rst_n;
assign rst_n = ~rst;
always @* begin
clk <= CLOCK_50;
end
// End of automatics
core core(
// Outputs
.LED (LED[7:0]),
.tx (tx),
.snd_out (snd_out),
.snd_signals (snd_signals[3:0]),
.dram_data_out (dram_data_in[31:0]),
.dram_addr (dram_addr[23:0]),
.dram_req_read (dram_req_read),
.dram_req_write (dram_req_write),
// Inputs
.clk (clk),
.rst_n (rst_n),
.rx (rx),
.switches (switches[3:0]),
.dram_data_in (dram_data_out[31:0]),
.dram_data_valid (dram_data_valid),
.dram_write_complete (dram_write_complete));
sdram_controller3 controller(
// Outputs
.data_out (dram_data_out[31:0]),
.data_valid (dram_data_valid),
.write_complete (dram_write_complete),
.DRAM_ADDR (DRAM_ADDR[12:0]),
.DRAM_BA (DRAM_BA[1:0]),
.DRAM_CAS_N (DRAM_CAS_N),
.DRAM_CKE (DRAM_CKE),
.DRAM_CLK (DRAM_CLK),
.DRAM_CS_N (DRAM_CS_N),
.DRAM_DQM (DRAM_DQM[1:0]),
.DRAM_RAS_N (DRAM_RAS_N),
.DRAM_WE_N (DRAM_WE_N),
// Inouts
.DRAM_DQ (DRAM_DQ[15:0]),
// Inputs
.CLOCK_50 (CLOCK_50),
.CLOCK_100 (CLOCK_100),
.CLOCK_100_del_3ns(CLOCK_100_del_3ns),
.rst (rst),
.address (dram_addr[23:0]),
.req_read (dram_req_read),
.req_write (dram_req_write),
.data_in (dram_data_in[31:0]));
IS42S16160 memory(
// Inouts
.Dq (DRAM_DQ[16-1:0]),
// Inputs
.Addr (DRAM_ADDR[13-1:0]),
.Ba (DRAM_BA[1:0]),
.Clk (DRAM_CLK),
.Cke (DRAM_CKE),
.Cs_n (DRAM_CS_N),
.Ras_n (DRAM_RAS_N),
.Cas_n (DRAM_CAS_N),
.We_n (DRAM_WE_N),
.Dqm (DRAM_DQM[1:0]));
initial begin
CLOCK_50 = 0;
CLOCK_100 = 0;
rst = 1;
$dumpfile("dump.vcd");
$dumpvars;
#9000 $finish;
end // initial begin
initial begin
#60 rst = 0;
end
always #10 CLOCK_50 <= ~CLOCK_50;
always #5 begin
CLOCK_100 <= ~CLOCK_100;
end
always @(CLOCK_100) begin
#3
CLOCK_100_del_3ns <= CLOCK_100;
end
endmodule
|
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