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module sky130_fd_sc_hd__and2 (
X ,
A ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire and0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
and and0 (and0_out_X , A, B );
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, and0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
|
module Approx_adder_W16 ( add_sub, in1, in2, res );
input [15:0] in1;
input [15:0] in2;
output [16:0] res;
input add_sub;
wire n33, n34, n35, n36, n37, n38, n39, n40, n41, n42, n43, n44, n45, n46,
n47, n48, n49, n50, n51, n52, n53, n54, n55, n56, n57, n58, n59, n60,
n61, n62, n63, n64, n65, n66, n67, n68, n69, n70, n71, n72, n73, n74,
n75, n76, n77, n78, n79, n80, n81, n82, n83, n84, n85, n86, n87, n88,
n89, n90, n91, n92, n93, n94, n95, n96, n97, n98, n99, n100, n101,
n102, n103, n104, n105, n106, n107, n108, n109, n110;
NAND2XLTS U51 ( .A(n33), .B(n87), .Y(n89) );
XOR2X1TS U52 ( .A(n62), .B(in2[11]), .Y(n94) );
NAND2X1TS U53 ( .A(n71), .B(in1[13]), .Y(n87) );
NAND2X1TS U54 ( .A(n74), .B(n36), .Y(n58) );
NAND2BX1TS U55 ( .AN(in2[13]), .B(n59), .Y(n74) );
NAND2X1TS U56 ( .A(n67), .B(n36), .Y(n68) );
CMPR32X2TS U57 ( .A(n100), .B(in1[6]), .C(n99), .CO(n55), .S(res[6]) );
OR2X2TS U58 ( .A(n51), .B(n35), .Y(n34) );
INVX4TS U59 ( .A(n35), .Y(n36) );
NOR2X4TS U60 ( .A(n53), .B(in2[8]), .Y(n57) );
INVX4TS U61 ( .A(add_sub), .Y(n35) );
CLKINVX6TS U62 ( .A(in2[1]), .Y(n44) );
CLKINVX6TS U63 ( .A(in2[3]), .Y(n42) );
CLKINVX6TS U64 ( .A(in2[0]), .Y(n43) );
INVX8TS U65 ( .A(in2[2]), .Y(n41) );
NAND2BX2TS U66 ( .AN(in2[11]), .B(n61), .Y(n67) );
NOR2XLTS U67 ( .A(n61), .B(n35), .Y(n62) );
INVX2TS U68 ( .A(n78), .Y(n77) );
NOR2X4TS U69 ( .A(n67), .B(in2[12]), .Y(n59) );
NOR2X4TS U70 ( .A(n65), .B(in2[10]), .Y(n61) );
AO21X2TS U71 ( .A0(n33), .A1(n70), .B0(n72), .Y(n37) );
NAND2X2TS U72 ( .A(n76), .B(in1[15]), .Y(n78) );
XNOR2X2TS U73 ( .A(n58), .B(in2[14]), .Y(n73) );
NOR2X2TS U74 ( .A(n59), .B(n35), .Y(n60) );
ADDFHX2TS U75 ( .A(n56), .B(in1[7]), .CI(n55), .CO(n97), .S(res[7]) );
OAI31X1TS U76 ( .A0(in2[2]), .A1(in2[1]), .A2(in2[0]), .B0(n36), .Y(n106) );
NAND2X2TS U77 ( .A(n83), .B(n82), .Y(n85) );
NOR2X2TS U78 ( .A(n73), .B(in1[14]), .Y(n81) );
NAND2X2TS U79 ( .A(n73), .B(in1[14]), .Y(n82) );
NOR2X2TS U80 ( .A(n39), .B(n86), .Y(n38) );
INVX2TS U81 ( .A(n86), .Y(n33) );
NAND2X2TS U82 ( .A(n69), .B(in1[12]), .Y(n90) );
OR2X2TS U83 ( .A(n69), .B(in1[12]), .Y(n46) );
XNOR2X2TS U84 ( .A(n68), .B(in2[12]), .Y(n69) );
NOR2BX2TS U85 ( .AN(in1[5]), .B(n110), .Y(n99) );
NAND2BXLTS U86 ( .AN(in1[5]), .B(n110), .Y(res[5]) );
XNOR2X2TS U87 ( .A(n50), .B(in2[5]), .Y(n110) );
NAND2BXLTS U88 ( .AN(in1[4]), .B(n109), .Y(res[4]) );
OAI21XLTS U89 ( .A0(in2[1]), .A1(n102), .B0(n101), .Y(res[1]) );
OAI21XLTS U90 ( .A0(in2[2]), .A1(n104), .B0(n103), .Y(res[2]) );
OAI21XLTS U91 ( .A0(in2[3]), .A1(n106), .B0(n105), .Y(res[3]) );
XOR2X1TS U92 ( .A(n108), .B(in2[4]), .Y(n109) );
OR2X1TS U93 ( .A(in2[0]), .B(in1[0]), .Y(res[0]) );
XNOR2X1TS U94 ( .A(n34), .B(in2[7]), .Y(n56) );
OAI21X1TS U95 ( .A0(n74), .A1(in2[14]), .B0(n36), .Y(n75) );
AO21X2TS U96 ( .A0(n79), .A1(n45), .B0(n77), .Y(res[16]) );
NAND2X2TS U97 ( .A(n45), .B(n78), .Y(n80) );
OR2X2TS U98 ( .A(n76), .B(in1[15]), .Y(n45) );
NOR2X2TS U99 ( .A(n49), .B(n35), .Y(n50) );
AFHCONX4TS U100 ( .A(in1[10]), .B(n95), .CI(n96), .CON(n93), .S(res[10]) );
AOI21X4TS U101 ( .A0(n91), .A1(n38), .B0(n37), .Y(n84) );
XNOR2X1TS U102 ( .A(n79), .B(n80), .Y(res[15]) );
OAI21X4TS U103 ( .A0(n84), .A1(n81), .B0(n82), .Y(n79) );
XNOR2X2TS U104 ( .A(n75), .B(in2[15]), .Y(n76) );
AFHCONX4TS U105 ( .A(in1[8]), .B(n98), .CI(n97), .CON(n63), .S(res[8]) );
AFHCINX4TS U106 ( .CIN(n63), .B(n64), .A(in1[9]), .S(res[9]), .CO(n96) );
NOR2X8TS U107 ( .A(n47), .B(in2[6]), .Y(n51) );
NAND2X4TS U108 ( .A(n47), .B(add_sub), .Y(n48) );
NAND2X8TS U109 ( .A(n49), .B(n40), .Y(n47) );
AFHCINX4TS U110 ( .CIN(n93), .B(n94), .A(in1[11]), .S(res[11]), .CO(n91) );
NOR2X8TS U111 ( .A(n107), .B(in2[4]), .Y(n49) );
XOR2X4TS U112 ( .A(n60), .B(in2[13]), .Y(n71) );
NAND2BX4TS U113 ( .AN(in2[7]), .B(n51), .Y(n53) );
NAND2BX4TS U114 ( .AN(in2[9]), .B(n57), .Y(n65) );
INVX2TS U115 ( .A(in2[5]), .Y(n40) );
NOR2X2TS U116 ( .A(n71), .B(in1[13]), .Y(n86) );
INVX2TS U117 ( .A(n90), .Y(n70) );
INVX2TS U118 ( .A(n46), .Y(n39) );
XNOR2X1TS U119 ( .A(n48), .B(in2[6]), .Y(n100) );
XNOR2X1TS U120 ( .A(n54), .B(in2[8]), .Y(n98) );
NAND2X1TS U121 ( .A(n53), .B(n36), .Y(n54) );
XOR2X1TS U122 ( .A(n52), .B(in2[9]), .Y(n64) );
NOR2X1TS U123 ( .A(n57), .B(n35), .Y(n52) );
XNOR2X1TS U124 ( .A(n92), .B(n91), .Y(res[12]) );
NAND2X1TS U125 ( .A(n46), .B(n90), .Y(n92) );
XOR2X1TS U126 ( .A(n89), .B(n88), .Y(res[13]) );
AOI21X1TS U127 ( .A0(n91), .A1(n46), .B0(n70), .Y(n88) );
XOR2X1TS U128 ( .A(n85), .B(n84), .Y(res[14]) );
INVX2TS U129 ( .A(n81), .Y(n83) );
NAND4X8TS U130 ( .A(n44), .B(n43), .C(n42), .D(n41), .Y(n107) );
INVX2TS U131 ( .A(n87), .Y(n72) );
NAND2X1TS U132 ( .A(n65), .B(n36), .Y(n66) );
XNOR2X1TS U133 ( .A(n66), .B(in2[10]), .Y(n95) );
NAND2X1TS U134 ( .A(in2[0]), .B(n36), .Y(n102) );
AOI21X1TS U135 ( .A0(in2[1]), .A1(n102), .B0(in1[1]), .Y(n101) );
OAI21X1TS U136 ( .A0(in2[1]), .A1(in2[0]), .B0(n36), .Y(n104) );
AOI21X1TS U137 ( .A0(in2[2]), .A1(n104), .B0(in1[2]), .Y(n103) );
AOI21X1TS U138 ( .A0(in2[3]), .A1(n106), .B0(in1[3]), .Y(n105) );
NAND2X1TS U139 ( .A(n107), .B(n36), .Y(n108) );
initial $sdf_annotate("Approx_adder_add_approx_flow_syn_constraints.tcl_LOALPL6_syn.sdf");
endmodule
|
module ecfg_elink (/*AUTOARG*/
// Outputs
txwr_gated_access, elink_en, clk_config, e_chipid,
// Inputs
txwr_access, txwr_packet, clk, reset
);
parameter RFAW = 6; // 32 registers for now
parameter PW = 104; // 32 registers for now
parameter ID = 12'h000;
parameter DEFAULT_CHIPID = 12'h808;
/******************************/
/*REGISTER ACCESS */
/******************************/
input txwr_access;
input [PW-1:0] txwr_packet;
/******************************/
/*FILTERED WRITE FOR TX FIFO */
/******************************/
output txwr_gated_access;
/******************************/
/*Clock/reset */
/******************************/
input clk;
input reset; // POR "hard reset"
/******************************/
/*Outputs */
/******************************/
output elink_en; // elink master enable
output [15:0] clk_config; // clock settings (for pll)
output [11:0] e_chipid; // chip-id for Epiphany
/*------------------------CODE BODY---------------------------------------*/
//registers
reg ecfg_reset_reg;
reg [15:0] ecfg_clk_reg;
reg [11:0] ecfg_chipid_reg;
reg [31:0] mi_dout;
//wires
wire ecfg_read;
wire ecfg_write;
wire ecfg_clk_write;
wire ecfg_chipid_write;
wire ecfg_reset_write;
wire mi_en;
wire [31:0] mi_addr;
wire [31:0] mi_din;
packet2emesh pe2 (
// Outputs
.access_out (),
.write_out (mi_we),
.datamode_out (),
.ctrlmode_out (),
.dstaddr_out (mi_addr[31:0]),
.data_out (mi_din[31:0]),
.srcaddr_out (),
// Inputs
.packet_in (txwr_packet[PW-1:0])
);
/*****************************/
/*ADDRESS DECODE LOGIC */
/*****************************/
assign mi_en = txwr_access &
(mi_addr[31:20]==ID) &
(mi_addr[10:8]==3'h2);
//read/write decode
assign ecfg_write = mi_en & mi_we;
assign ecfg_read = mi_en & ~mi_we;
//Config write enables
assign ecfg_reset_write = ecfg_write & (mi_addr[RFAW+1:2]==`E_RESET);
assign ecfg_clk_write = ecfg_write & (mi_addr[RFAW+1:2]==`E_CLK);
assign ecfg_chipid_write = ecfg_write & (mi_addr[RFAW+1:2]==`E_CHIPID);
/*****************************/
/*FILTER ACCESS */
/*****************************/
assign txwr_gated_access = txwr_access & ~(ecfg_reset_write |
ecfg_clk_write |
ecfg_chipid_write);
//###########################
//# RESET REG
//###########################
always @ (posedge clk)
if(reset)
ecfg_reset_reg <= 1'b0;
else if (ecfg_reset_write)
ecfg_reset_reg <= mi_din[0];
assign elink_en = ~ecfg_reset_reg;
//###########################
//# CCLK/LCLK (PLL)
//###########################
always @ (posedge clk)
if(reset)
ecfg_clk_reg[15:0] <= 16'h573;//all clocks on at lowest speed
else if (ecfg_clk_write)
ecfg_clk_reg[15:0] <= mi_din[15:0];
assign clk_config[15:0] = ecfg_clk_reg[15:0];
//###########################
//# CHIPID
//###########################
always @ (posedge clk)
if(reset)
ecfg_chipid_reg[11:0] <= DEFAULT_CHIPID;
else if (ecfg_chipid_write)
ecfg_chipid_reg[11:0] <= mi_din[11:0];
assign e_chipid[11:0]=ecfg_chipid_reg[5:2];
endmodule
|
module pixel_panning
(
input din,
input clk, // dot clock
input clk_en, // dot clock
input [3:0] pp_ctl, // pixel panning control signals
input mode_13_ctl,
input r_n,
input by_4_syn_cclk,
output dout,
output dout_1
);
reg [8:0] shift_ff;
reg [7:0] mux_ctl; // mux control signals
wire [7:0] int_d;
wire [7:0] mux_ctl_8_f_op;
assign int_d[7] = mux_ctl[7] ? din : shift_ff[8];
assign int_d[6] = mux_ctl[6] ? din : shift_ff[7];
assign int_d[5] = mux_ctl[5] ? din : shift_ff[6];
assign int_d[4] = mux_ctl[4] ? din : shift_ff[5];
assign int_d[3] = mux_ctl[3] ? din : shift_ff[4];
assign int_d[2] = mux_ctl[2] ? din : shift_ff[3];
assign int_d[1] = mux_ctl[1] ? din : shift_ff[2];
assign int_d[0] = mux_ctl[0] ? din : shift_ff[1];
// Inferring 9 flops
always@(posedge clk or negedge r_n) begin
if(~r_n) shift_ff[8:0] <= 8'b0;
else if (clk_en) begin
shift_ff[8] <= din;
shift_ff[7] <= int_d[7];
shift_ff[6] <= int_d[6];
shift_ff[5] <= int_d[5];
shift_ff[4] <= int_d[4];
shift_ff[3] <= int_d[3];
shift_ff[2] <= int_d[2];
shift_ff[1] <= int_d[1];
shift_ff[0] <= int_d[0];
end
end
assign mux_ctl_8_f_op = mode_13_ctl ? 8'b0001_0000 : 8'b0000_0000;
// Realizing mux control signals
always @(pp_ctl or mode_13_ctl or mux_ctl_8_f_op or by_4_syn_cclk) begin
case(pp_ctl) // synopsys parallel_case
4'h0: mux_ctl = (by_4_syn_cclk) ? 8'b0000_1000 : 8'b1000_0000;
4'h1: mux_ctl = 8'b0100_0000;
4'h2: mux_ctl = (mode_13_ctl) ? 8'b0100_0000 : 8'b0010_0000;
4'h3: mux_ctl = 8'b0001_0000;
4'h4: mux_ctl = (mode_13_ctl) ? 8'b0010_0000 : 8'b0000_1000;
4'h5: mux_ctl = 8'b0000_0100;
4'h6: mux_ctl = (mode_13_ctl) ? 8'b0001_0000 : 8'b0000_0010;
4'h7: mux_ctl = 8'b0000_0001;
4'h8: mux_ctl = mux_ctl_8_f_op;
4'h9: mux_ctl = mux_ctl_8_f_op;
4'ha: mux_ctl = mux_ctl_8_f_op;
4'hb: mux_ctl = mux_ctl_8_f_op;
4'hc: mux_ctl = mux_ctl_8_f_op;
4'hd: mux_ctl = mux_ctl_8_f_op;
4'he: mux_ctl = mux_ctl_8_f_op;
4'hf: mux_ctl = mux_ctl_8_f_op;
endcase
end
assign dout = shift_ff[0];
assign dout_1 = int_d[0];
endmodule
|
module communication_tb;
initial begin
$dumpfile("communication.vcd");
$dumpvars(0, communication_tb);
# 1100000000 $finish; // 1 100 000 000 ns = 1.1s
end
reg clk=0;
always #`H_PERIOD clk = !clk; // 41.666 ns = a half period of the 12MHz clock
wire transmit;
wire [7:0] tx_byte;
reg received;
reg [7:0] rx_byte;
wire en;
wire [39:0] m;
wire set;
wire error;
reg [39:0] m2=40315426; // value of m to send (for 440 Hz)
initial begin
#`PERIOD10 rx_byte = `BYTE0;
#`PERIOD received = 1;
#`PERIOD received = 0;
#`PERIOD10 rx_byte = m2[7:0];
#`PERIOD received = 1;
#`PERIOD received = 0;
#`PERIOD10 rx_byte = `BYTE1;
#`PERIOD received = 1;
#`PERIOD received = 0;
#`PERIOD10 rx_byte = m2[15:8];
#`PERIOD received = 1;
#`PERIOD received = 0;
#`PERIOD10 rx_byte = `BYTE2;
#`PERIOD received = 1;
#`PERIOD received = 0;
#`PERIOD10 rx_byte = m2[23:16];
#`PERIOD received = 1;
#`PERIOD received = 0;
#`PERIOD10 rx_byte = `BYTE3;
#`PERIOD received = 1;
#`PERIOD received = 0;
#`PERIOD10 rx_byte = m2[31:24];
#`PERIOD received = 1;
#`PERIOD received = 0;
#`PERIOD10 rx_byte = `BYTE4;
#`PERIOD received = 1;
#`PERIOD received = 0;
#`PERIOD10 rx_byte = m2[39:32];
#`PERIOD received = 1;
#`PERIOD received = 0;
#`PERIOD10 rx_byte = `SET;
#`PERIOD received = 1;
#`PERIOD received = 0;
#`PERIOD10 rx_byte = `ENABLE;
#`PERIOD received = 1;
#`PERIOD received = 0;
#`PERIOD10 rx_byte = 0; // generate an error
#`PERIOD received = 1;
#`PERIOD received = 0;
end
communication com(.clk(clk), .transmit(transmit), .tx_byte(tx_byte), .received(received), .rx_byte(rx_byte), .en(en), .m(m), .set(set), .error(error));
endmodule
|
module th54w32 ( y, a, b, c, d );
output y;
input a, b, c, d;
specify
specparam CDS_LIBNAME = "static";
specparam CDS_CELLNAME = "th54w32";
specparam CDS_VIEWNAME = "schematic";
endspecify
nfet_b N13 ( .d(net037), .g(y), .s(cds_globals.gnd_),
.b(cds_globals.gnd_));
nfet_b N14 ( .d(net32), .g(c), .s(net037), .b(cds_globals.gnd_));
nfet_b N6 ( .d(net45), .g(y), .s(cds_globals.gnd_),
.b(cds_globals.gnd_));
nfet_b N5 ( .d(net32), .g(b), .s(net037), .b(cds_globals.gnd_));
nfet_b N4 ( .d(net45), .g(c), .s(net44), .b(cds_globals.gnd_));
nfet_b N15 ( .d(net32), .g(d), .s(net037), .b(cds_globals.gnd_));
nfet_b N3 ( .d(net44), .g(d), .s(cds_globals.gnd_),
.b(cds_globals.gnd_));
nfet_b N2 ( .d(net45), .g(b), .s(cds_globals.gnd_),
.b(cds_globals.gnd_));
nfet_b N1 ( .d(net32), .g(a), .s(net45), .b(cds_globals.gnd_));
pfet_b P11 ( .b(cds_globals.vdd_), .g(b), .s(net036), .d(net047));
pfet_b P7 ( .b(cds_globals.vdd_), .g(c), .s(net047), .d(net32));
pfet_b P10 ( .b(cds_globals.vdd_), .g(d), .s(net047), .d(net32));
pfet_b P5 ( .b(cds_globals.vdd_), .g(y), .s(cds_globals.vdd_),
.d(net036));
pfet_b P4 ( .b(cds_globals.vdd_), .g(y), .s(cds_globals.vdd_),
.d(net47));
pfet_b P3 ( .b(cds_globals.vdd_), .g(a), .s(net47), .d(net32));
pfet_b P2 ( .b(cds_globals.vdd_), .g(c), .s(net34), .d(net47));
pfet_b P1 ( .b(cds_globals.vdd_), .g(d), .s(net49), .d(net34));
pfet_b P0 ( .b(cds_globals.vdd_), .g(b), .s(cds_globals.vdd_),
.d(net49));
inv I2 ( y, net32);
endmodule
|
module
input bs_chain_tdo_i; // from Boundary Scan Chain
input mbist_tdo_i; // from Mbist Chain
// Wires which depend on the state of the TAP FSM
reg test_logic_reset;
reg run_test_idle;
reg select_dr_scan;
reg capture_dr;
reg shift_dr;
reg exit1_dr;
reg pause_dr;
reg exit2_dr;
reg update_dr;
reg select_ir_scan;
reg capture_ir;
reg shift_ir;
reg exit1_ir;
reg pause_ir;
reg exit2_ir;
reg update_ir;
// Wires which depend on the current value in the IR
reg user1_select;
reg sample_preload_select;
reg idcode_select;
reg user1_select;
reg debug_select;
reg bypass_select;
// TDO and enable
reg tdo_pad_o;
reg tdo_padoe_o;
assign tdi_o = tdi_pad_i;
assign test_logic_reset_o = test_logic_reset;
assign run_test_idle_o = run_test_idle;
assign shift_dr_o = shift_dr;
assign pause_dr_o = pause_dr;
assign update_dr_o = update_dr;
assign capture_dr_o = capture_dr;
assign sample_preload_select_o = sample_preload_select;
assign user1_select_o = user1_select;
assign user2_select_o = user2_select;
/**********************************************************************************
* *
* TAP State Machine: Fully JTAG compliant *
* *
**********************************************************************************/
// Definition of machine state values. We could one-hot encode this, and use 16
// registers, but this uses binary encoding for the minimum of 4 DFF's instead.
`define STATE_test_logic_reset 4'hF
`define STATE_run_test_idle 4'hC
`define STATE_select_dr_scan 4'h7
`define STATE_capture_dr 4'h6
`define STATE_shift_dr 4'h2
`define STATE_exit1_dr 4'h1
`define STATE_pause_dr 4'h3
`define STATE_exit2_dr 4'h0
`define STATE_update_dr 4'h5
`define STATE_select_ir_scan 4'h4
`define STATE_capture_ir 4'hE
`define STATE_shift_ir 4'hA
`define STATE_exit1_ir 4'h9
`define STATE_pause_ir 4'hB
`define STATE_exit2_ir 4'h8
`define STATE_update_ir 4'hD
reg [3:0] TAP_state = `STATE_test_logic_reset; // current state of the TAP controller
reg [3:0] next_TAP_state; // state TAP will take at next rising TCK, combinational signal
// sequential part of the FSM
always @ (posedge tck_pad_i or negedge trstn_pad_i)
begin
if(trstn_pad_i == 0)
TAP_state = `STATE_test_logic_reset;
else
TAP_state = next_TAP_state;
end
// Determination of next state; purely combinatorial
always @ (TAP_state or tms_pad_i)
begin
case(TAP_state)
`STATE_test_logic_reset:
begin
if(tms_pad_i) next_TAP_state = `STATE_test_logic_reset;
else next_TAP_state = `STATE_run_test_idle;
end
`STATE_run_test_idle:
begin
if(tms_pad_i) next_TAP_state = `STATE_select_dr_scan;
else next_TAP_state = `STATE_run_test_idle;
end
`STATE_select_dr_scan:
begin
if(tms_pad_i) next_TAP_state = `STATE_select_ir_scan;
else next_TAP_state = `STATE_capture_dr;
end
`STATE_capture_dr:
begin
if(tms_pad_i) next_TAP_state = `STATE_exit1_dr;
else next_TAP_state = `STATE_shift_dr;
end
`STATE_shift_dr:
begin
if(tms_pad_i) next_TAP_state = `STATE_exit1_dr;
else next_TAP_state = `STATE_shift_dr;
end
`STATE_exit1_dr:
begin
if(tms_pad_i) next_TAP_state = `STATE_update_dr;
else next_TAP_state = `STATE_pause_dr;
end
`STATE_pause_dr:
begin
if(tms_pad_i) next_TAP_state = `STATE_exit2_dr;
else next_TAP_state = `STATE_pause_dr;
end
`STATE_exit2_dr:
begin
if(tms_pad_i) next_TAP_state = `STATE_update_dr;
else next_TAP_state = `STATE_shift_dr;
end
`STATE_update_dr:
begin
if(tms_pad_i) next_TAP_state = `STATE_select_dr_scan;
else next_TAP_state = `STATE_run_test_idle;
end
`STATE_select_ir_scan:
begin
if(tms_pad_i) next_TAP_state = `STATE_test_logic_reset;
else next_TAP_state = `STATE_capture_ir;
end
`STATE_capture_ir:
begin
if(tms_pad_i) next_TAP_state = `STATE_exit1_ir;
else next_TAP_state = `STATE_shift_ir;
end
`STATE_shift_ir:
begin
if(tms_pad_i) next_TAP_state = `STATE_exit1_ir;
else next_TAP_state = `STATE_shift_ir;
end
`STATE_exit1_ir:
begin
if(tms_pad_i) next_TAP_state = `STATE_update_ir;
else next_TAP_state = `STATE_pause_ir;
end
`STATE_pause_ir:
begin
if(tms_pad_i) next_TAP_state = `STATE_exit2_ir;
else next_TAP_state = `STATE_pause_ir;
end
`STATE_exit2_ir:
begin
if(tms_pad_i) next_TAP_state = `STATE_update_ir;
else next_TAP_state = `STATE_shift_ir;
end
`STATE_update_ir:
begin
if(tms_pad_i) next_TAP_state = `STATE_select_dr_scan;
else next_TAP_state = `STATE_run_test_idle;
end
default: next_TAP_state = `STATE_test_logic_reset; // can't actually happen
endcase
end
// Outputs of state machine, pure combinatorial
always @ (TAP_state)
begin
// Default everything to 0, keeps the case statement simple
test_logic_reset = 1'b0;
run_test_idle = 1'b0;
select_dr_scan = 1'b0;
capture_dr = 1'b0;
shift_dr = 1'b0;
exit1_dr = 1'b0;
pause_dr = 1'b0;
exit2_dr = 1'b0;
update_dr = 1'b0;
select_ir_scan = 1'b0;
capture_ir = 1'b0;
shift_ir = 1'b0;
exit1_ir = 1'b0;
pause_ir = 1'b0;
exit2_ir = 1'b0;
update_ir = 1'b0;
case(TAP_state)
`STATE_test_logic_reset: test_logic_reset = 1'b1;
`STATE_run_test_idle: run_test_idle = 1'b1;
`STATE_select_dr_scan: select_dr_scan = 1'b1;
`STATE_capture_dr: capture_dr = 1'b1;
`STATE_shift_dr: shift_dr = 1'b1;
`STATE_exit1_dr: exit1_dr = 1'b1;
`STATE_pause_dr: pause_dr = 1'b1;
`STATE_exit2_dr: exit2_dr = 1'b1;
`STATE_update_dr: update_dr = 1'b1;
`STATE_select_ir_scan: select_ir_scan = 1'b1;
`STATE_capture_ir: capture_ir = 1'b1;
`STATE_shift_ir: shift_ir = 1'b1;
`STATE_exit1_ir: exit1_ir = 1'b1;
`STATE_pause_ir: pause_ir = 1'b1;
`STATE_exit2_ir: exit2_ir = 1'b1;
`STATE_update_ir: update_ir = 1'b1;
default: ;
endcase
end
/**********************************************************************************
* *
* End: TAP State Machine *
* *
**********************************************************************************/
/**********************************************************************************
* *
* jtag_ir: JTAG Instruction Register *
* *
**********************************************************************************/
reg [`IR_LENGTH-1:0] jtag_ir; // Instruction register
reg [`IR_LENGTH-1:0] latched_jtag_ir; //, latched_jtag_ir_neg;
wire instruction_tdo;
always @ (posedge tck_pad_i or negedge trstn_pad_i)
begin
if(trstn_pad_i == 0)
jtag_ir[`IR_LENGTH-1:0] <= `IR_LENGTH'b0;
else if (test_logic_reset == 1)
jtag_ir[`IR_LENGTH-1:0] <= `IR_LENGTH'b0;
else if(capture_ir)
jtag_ir <= 4'b0101; // This value is fixed for easier fault detection
else if(shift_ir)
jtag_ir[`IR_LENGTH-1:0] <= {tdi_pad_i, jtag_ir[`IR_LENGTH-1:1]};
end
assign instruction_tdo = jtag_ir[0]; // This is latched on a negative TCK edge after the output MUX
// Updating jtag_ir (Instruction Register)
// jtag_ir should be latched on FALLING EDGE of TCK when capture_ir == 1
always @ (negedge tck_pad_i or negedge trstn_pad_i)
begin
if(trstn_pad_i == 0)
latched_jtag_ir <= `IDCODE; // IDCODE selected after reset
else if (test_logic_reset)
latched_jtag_ir <= `IDCODE; // IDCODE selected after reset
else if(update_ir)
latched_jtag_ir <= jtag_ir;
end
/**********************************************************************************
* *
* End: jtag_ir *
* *
**********************************************************************************/
/**********************************************************************************
* *
* idcode logic *
* *
**********************************************************************************/
reg [31:0] idcode_reg;
wire idcode_tdo;
always @ (posedge tck_pad_i or negedge trstn_pad_i)
begin
if(trstn_pad_i == 0)
idcode_reg <= `IDCODE_VALUE; // IDCODE selected after reset
else if (test_logic_reset)
idcode_reg <= `IDCODE_VALUE; // IDCODE selected after reset
else if(idcode_select & capture_dr)
idcode_reg <= `IDCODE_VALUE;
else if(idcode_select & shift_dr)
idcode_reg <= {tdi_pad_i, idcode_reg[31:1]};
end
assign idcode_tdo = idcode_reg[0]; // This is latched on a negative TCK edge after the output MUX
/**********************************************************************************
* *
* End: idcode logic *
* *
**********************************************************************************/
/**********************************************************************************
* *
* Bypass logic *
* *
**********************************************************************************/
wire bypassed_tdo;
reg bypass_reg; // This is a 1-bit register
always @ (posedge tck_pad_i or negedge trstn_pad_i)
begin
if (trstn_pad_i == 0)
bypass_reg <= 1'b0;
else if (test_logic_reset == 1)
bypass_reg <= 1'b0;
else if (bypass_select & capture_dr)
bypass_reg<= 1'b0;
else if(bypass_select & shift_dr)
bypass_reg<= tdi_pad_i;
end
assign bypassed_tdo = bypass_reg; // This is latched on a negative TCK edge after the output MUX
/**********************************************************************************
* *
* End: Bypass logic *
* *
**********************************************************************************/
/**********************************************************************************
* *
* Selecting active data register *
* *
**********************************************************************************/
always @ (latched_jtag_ir)
begin
user1_select = 1'b0;
sample_preload_select = 1'b0;
idcode_select = 1'b0;
user1_select = 1'b0;
debug_select = 1'b0;
bypass_select = 1'b0;
case(latched_jtag_ir) /* synthesis parallel_case */
`USER1: user1_select = 1'b1; // External test
`SAMPLE_PRELOAD: sample_preload_select = 1'b1; // Sample preload
`IDCODE: idcode_select = 1'b1; // ID Code
`USER2: user1_select = 1'b1; // Mbist test
`DEBUG: debug_select = 1'b1; // Debug
`BYPASS: bypass_select = 1'b1; // BYPASS
default: bypass_select = 1'b1; // BYPASS
endcase
end
/**********************************************************************************
* *
* Multiplexing TDO data *
* *
**********************************************************************************/
reg tdo_mux_out; // really just a wire
always @ (shift_ir or instruction_tdo or latched_jtag_ir or idcode_tdo or
debug_tdo_i or bs_chain_tdo_i or mbist_tdo_i or bypassed_tdo or
bs_chain_tdo_i)
begin
if(shift_ir)
tdo_mux_out = instruction_tdo;
else
begin
case(latched_jtag_ir) // synthesis parallel_case
`IDCODE: tdo_mux_out = idcode_tdo; // Reading ID code
`DEBUG: tdo_mux_out = debug_tdo_i; // Debug
`SAMPLE_PRELOAD: tdo_mux_out = bs_chain_tdo_i; // Sampling/Preloading
`USER1: tdo_mux_out = bs_chain_tdo_i; // External test
`USER2: tdo_mux_out = mbist_tdo_i; // Mbist test
default: tdo_mux_out = bypassed_tdo; // BYPASS instruction
endcase
end
end
// TDO changes state at negative edge of TCK
always @ (negedge tck_pad_i)
begin
tdo_pad_o = tdo_mux_out;
end
// Tristate control for tdo_pad_o pin
always @ (posedge tck_pad_i)
begin
tdo_padoe_o <= shift_ir | shift_dr;
end
/**********************************************************************************
* *
* End: Multiplexing TDO data *
* *
**********************************************************************************/
endmodule
|
module omsp_dbg_hwbrk (
// OUTPUTs
brk_halt, // Hardware breakpoint command
brk_pnd, // Hardware break/watch-point pending
brk_dout, // Hardware break/watch-point register data input
// INPUTs
brk_reg_rd, // Hardware break/watch-point register read select
brk_reg_wr, // Hardware break/watch-point register write select
dbg_din, // Debug register data input
eu_mab, // Execution-Unit Memory address bus
eu_mb_en, // Execution-Unit Memory bus enable
eu_mb_wr, // Execution-Unit Memory bus write transfer
eu_mdb_in, // Memory data bus input
eu_mdb_out, // Memory data bus output
exec_done, // Execution completed
fe_mb_en, // Frontend Memory bus enable
mclk, // Main system clock
pc, // Program counter
por // Power on reset
);
// OUTPUTs
//=========
output brk_halt; // Hardware breakpoint command
output brk_pnd; // Hardware break/watch-point pending
output [15:0] brk_dout; // Hardware break/watch-point register data input
// INPUTs
//=========
input [3:0] brk_reg_rd; // Hardware break/watch-point register read select
input [3:0] brk_reg_wr; // Hardware break/watch-point register write select
input [15:0] dbg_din; // Debug register data input
input [15:0] eu_mab; // Execution-Unit Memory address bus
input eu_mb_en; // Execution-Unit Memory bus enable
input [1:0] eu_mb_wr; // Execution-Unit Memory bus write transfer
input [15:0] eu_mdb_in; // Memory data bus input
input [15:0] eu_mdb_out; // Memory data bus output
input exec_done; // Execution completed
input fe_mb_en; // Frontend Memory bus enable
input mclk; // Main system clock
input [15:0] pc; // Program counter
input por; // Power on reset
//=============================================================================
// 1) WIRE & PARAMETER DECLARATION
//=============================================================================
wire range_wr_set;
wire range_rd_set;
wire addr1_wr_set;
wire addr1_rd_set;
wire addr0_wr_set;
wire addr0_rd_set;
parameter BRK_CTL = 0,
BRK_STAT = 1,
BRK_ADDR0 = 2,
BRK_ADDR1 = 3;
//=============================================================================
// 2) CONFIGURATION REGISTERS
//=============================================================================
// BRK_CTL Register
//-----------------------------------------------------------------------------
// 7 6 5 4 3 2 1 0
// Reserved RANGE_MODE INST_EN BREAK_EN ACCESS_MODE
//
// ACCESS_MODE: - 00 : Disabled
// - 01 : Detect read access
// - 10 : Detect write access
// - 11 : Detect read/write access
// NOTE: '10' & '11' modes are not supported on the instruction flow
//
// BREAK_EN: - 0 : Watchmode enable
// - 1 : Break enable
//
// INST_EN: - 0 : Checks are done on the execution unit (data flow)
// - 1 : Checks are done on the frontend (instruction flow)
//
// RANGE_MODE: - 0 : Address match on BRK_ADDR0 or BRK_ADDR1
// - 1 : Address match on BRK_ADDR0->BRK_ADDR1 range
//
//-----------------------------------------------------------------------------
reg [4:0] brk_ctl;
wire brk_ctl_wr = brk_reg_wr[BRK_CTL];
always @ (posedge mclk or posedge por)
if (por) brk_ctl <= 5'h00;
else if (brk_ctl_wr) brk_ctl <= {`HWBRK_RANGE & dbg_din[4], dbg_din[3:0]};
wire [7:0] brk_ctl_full = {3'b000, brk_ctl};
// BRK_STAT Register
//-----------------------------------------------------------------------------
// 7 6 5 4 3 2 1 0
// Reserved RANGE_WR RANGE_RD ADDR1_WR ADDR1_RD ADDR0_WR ADDR0_RD
//-----------------------------------------------------------------------------
reg [5:0] brk_stat;
wire brk_stat_wr = brk_reg_wr[BRK_STAT];
wire [5:0] brk_stat_set = {range_wr_set & `HWBRK_RANGE,
range_rd_set & `HWBRK_RANGE,
addr1_wr_set, addr1_rd_set,
addr0_wr_set, addr0_rd_set};
wire [5:0] brk_stat_clr = ~dbg_din[5:0];
always @ (posedge mclk or posedge por)
if (por) brk_stat <= 6'h00;
else if (brk_stat_wr) brk_stat <= ((brk_stat & brk_stat_clr) | brk_stat_set);
else brk_stat <= (brk_stat | brk_stat_set);
wire [7:0] brk_stat_full = {2'b00, brk_stat};
wire brk_pnd = |brk_stat;
// BRK_ADDR0 Register
//-----------------------------------------------------------------------------
reg [15:0] brk_addr0;
wire brk_addr0_wr = brk_reg_wr[BRK_ADDR0];
always @ (posedge mclk or posedge por)
if (por) brk_addr0 <= 16'h0000;
else if (brk_addr0_wr) brk_addr0 <= dbg_din;
// BRK_ADDR1/DATA0 Register
//-----------------------------------------------------------------------------
reg [15:0] brk_addr1;
wire brk_addr1_wr = brk_reg_wr[BRK_ADDR1];
always @ (posedge mclk or posedge por)
if (por) brk_addr1 <= 16'h0000;
else if (brk_addr1_wr) brk_addr1 <= dbg_din;
//============================================================================
// 3) DATA OUTPUT GENERATION
//============================================================================
wire [15:0] brk_ctl_rd = {8'h00, brk_ctl_full} & {16{brk_reg_rd[BRK_CTL]}};
wire [15:0] brk_stat_rd = {8'h00, brk_stat_full} & {16{brk_reg_rd[BRK_STAT]}};
wire [15:0] brk_addr0_rd = brk_addr0 & {16{brk_reg_rd[BRK_ADDR0]}};
wire [15:0] brk_addr1_rd = brk_addr1 & {16{brk_reg_rd[BRK_ADDR1]}};
wire [15:0] brk_dout = brk_ctl_rd |
brk_stat_rd |
brk_addr0_rd |
brk_addr1_rd;
//============================================================================
// 4) BREAKPOINT / WATCHPOINT GENERATION
//============================================================================
// Comparators
//---------------------------
// Note: here the comparison logic is instanciated several times in order
// to improve the timings, at the cost of a bit more area.
wire equ_d_addr0 = eu_mb_en & (eu_mab==brk_addr0) & ~brk_ctl[`BRK_RANGE];
wire equ_d_addr1 = eu_mb_en & (eu_mab==brk_addr1) & ~brk_ctl[`BRK_RANGE];
wire equ_d_range = eu_mb_en & ((eu_mab>=brk_addr0) & (eu_mab<=brk_addr1)) &
brk_ctl[`BRK_RANGE] & `HWBRK_RANGE;
reg fe_mb_en_buf;
always @ (posedge mclk or posedge por)
if (por) fe_mb_en_buf <= 1'b0;
else fe_mb_en_buf <= fe_mb_en;
wire equ_i_addr0 = fe_mb_en_buf & (pc==brk_addr0) & ~brk_ctl[`BRK_RANGE];
wire equ_i_addr1 = fe_mb_en_buf & (pc==brk_addr1) & ~brk_ctl[`BRK_RANGE];
wire equ_i_range = fe_mb_en_buf & ((pc>=brk_addr0) & (pc<=brk_addr1)) &
brk_ctl[`BRK_RANGE] & `HWBRK_RANGE;
// Detect accesses
//---------------------------
// Detect Instruction read access
wire i_addr0_rd = equ_i_addr0 & brk_ctl[`BRK_I_EN];
wire i_addr1_rd = equ_i_addr1 & brk_ctl[`BRK_I_EN];
wire i_range_rd = equ_i_range & brk_ctl[`BRK_I_EN];
// Detect Execution-Unit write access
wire d_addr0_wr = equ_d_addr0 & ~brk_ctl[`BRK_I_EN] & |eu_mb_wr;
wire d_addr1_wr = equ_d_addr1 & ~brk_ctl[`BRK_I_EN] & |eu_mb_wr;
wire d_range_wr = equ_d_range & ~brk_ctl[`BRK_I_EN] & |eu_mb_wr;
// Detect DATA read access
// Whenever an "ADD r9. &0x200" instruction is executed, &0x200 will be read
// before being written back. In that case, the read flag should not be set.
// In general, We should here make sure no write access occures during the
// same instruction cycle before setting the read flag.
reg [2:0] d_rd_trig;
always @ (posedge mclk or posedge por)
if (por) d_rd_trig <= 3'h0;
else if (exec_done) d_rd_trig <= 3'h0;
else d_rd_trig <= {equ_d_range & ~brk_ctl[`BRK_I_EN] & ~|eu_mb_wr,
equ_d_addr1 & ~brk_ctl[`BRK_I_EN] & ~|eu_mb_wr,
equ_d_addr0 & ~brk_ctl[`BRK_I_EN] & ~|eu_mb_wr};
wire d_addr0_rd = d_rd_trig[0] & exec_done & ~d_addr0_wr;
wire d_addr1_rd = d_rd_trig[1] & exec_done & ~d_addr1_wr;
wire d_range_rd = d_rd_trig[2] & exec_done & ~d_range_wr;
// Set flags
assign addr0_rd_set = brk_ctl[`BRK_MODE_RD] & (d_addr0_rd | i_addr0_rd);
assign addr0_wr_set = brk_ctl[`BRK_MODE_WR] & d_addr0_wr;
assign addr1_rd_set = brk_ctl[`BRK_MODE_RD] & (d_addr1_rd | i_addr1_rd);
assign addr1_wr_set = brk_ctl[`BRK_MODE_WR] & d_addr1_wr;
assign range_rd_set = brk_ctl[`BRK_MODE_RD] & (d_range_rd | i_range_rd);
assign range_wr_set = brk_ctl[`BRK_MODE_WR] & d_range_wr;
// Break CPU
assign brk_halt = brk_ctl[`BRK_EN] & |brk_stat_set;
endmodule
|
module sky130_fd_sc_hdll__sdfxtp_1 (
Q ,
CLK ,
D ,
SCD ,
SCE ,
VPWR,
VGND,
VPB ,
VNB
);
output Q ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hdll__sdfxtp base (
.Q(Q),
.CLK(CLK),
.D(D),
.SCD(SCD),
.SCE(SCE),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
|
module sky130_fd_sc_hdll__sdfxtp_1 (
Q ,
CLK,
D ,
SCD,
SCE
);
output Q ;
input CLK;
input D ;
input SCD;
input SCE;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hdll__sdfxtp base (
.Q(Q),
.CLK(CLK),
.D(D),
.SCD(SCD),
.SCE(SCE)
);
endmodule
|
module deepgate_top(
// 50MHz clock input
input clk50MHz,
// Input from reset button (active low)
input rst_n,
// cclk input from AVR, high when AVR is ready
input cclk,
// Outputs to the 8 onboard LEDs
output wire [7:0] led,
// AVR SPI connections
output spi_miso,
input spi_ss,
input spi_mosi,
input spi_sck,
// AVR ADC channel select
output [3:0] spi_channel,
// Serial connections
input avr_tx, // AVR Tx => FPGA Rx
output avr_rx, // AVR Rx => FPGA Tx
input avr_rx_busy, // AVR Rx buffer full
//SDRAM interface
output sdram_clk,
output sdram_cle,
output sdram_dqm,
output sdram_cs,
output sdram_we,
output sdram_cas,
output sdram_ras,
output [1:0] sdram_ba,
output [12:0] sdram_a,
inout [7:0] sdram_dq
);
`include "param_include.v"
wire rst = ~rst_n; //becomes active high
wire clk;
//wire pllLock;
wire pllFeedbackClk;
/*
PLL_BASE#(
.BANDWIDTH ("OPTIMIZED"),
.CLKFBOUT_MULT (10),
.CLKFBOUT_PHASE (0.0),
.CLKIN_PERIOD ("20"),
.CLKOUT0_DIVIDE (5),
.CLKOUT0_DUTY_CYCLE (0.5),
.CLKOUT0_PHASE (0.0),
.CLK_FEEDBACK ("CLKFBOUT"),
//.COMPENSATION ("INTERNAL"),
.DIVCLK_DIVIDE (1),
.REF_JITTER (0.1),
.RESET_ON_LOSS_OF_LOCK ("FALSE")
)
PLL_BASE_inst(
.CLKFBOUT (pllFeedbackClk),
.CLKOUT0 (clk),
// .LOCKED (pllLock),
.CLKFBIN (pllFeedbackClk),
.CLKIN (clk50MHz),
.RST (0)
);
*/
assign clk = clk50MHz;
wire [7:0] tx_data;
wire tx_busy;
wire [7:0] rx_data;
wire new_rx_data;
wire newTXData;
avr_interface AVR (
.clk (clk),
.rst (rst),
.cclk (cclk),
.spi_miso (spi_miso),
.spi_mosi (spi_mosi),
.spi_sck (spi_sck),
.spi_ss (spi_ss),
.spi_channel (spi_channel),
.tx (avr_rx),
.rx (avr_tx),
.channel (4'd15),
.tx_data (tx_data),
.new_tx_data (newTXData),
.tx_busy (tx_busy),
.tx_block (avr_rx_busy),
.rx_data (rx_data),
.new_rx_data (new_rx_data)
);
wire [31:0] sdramDataTX;
wire [31:0] sdramDataRX;
wire [22:0] sdramAddr;
wire sdramBusy;
wire sdramTXValid;
wire sdramRXValid;
wire sdramRW;
sdram SDRAM (
.clk (clk),
.rst (rst),
// these signals go directly to the IO pins
.sdram_clk (sdram_clk),
.sdram_cle (sdram_cle),
.sdram_cs (sdram_cs),
.sdram_cas (sdram_cas),
.sdram_ras (sdram_ras),
.sdram_we (sdram_we),
.sdram_dqm (sdram_dqm),
.sdram_ba (sdram_ba),
.sdram_a (sdram_a),
.sdram_dq (sdram_dq),
// User interface
.addr (sdramAddr), // address to read/write
.rw (sdramRW), // 1 = write, 0 = read
.data_in (sdramDataTX), // sdram data to write
.data_out (sdramDataRX), // sdram data from read
.busy (sdramBusy), // controller is busy when high
.in_valid (sdramTXValid), // pulse high to initiate a read/write
.out_valid (sdramRXValid) // pulses high when data from read is valid
);
wire procBegin;
wire procComplete;
wire [7:0] networkDataIn;
wire [7:0] networkOut;
wire networkIdle;
wire networkRead;
wire inputRead;
wire [7:0] weightData;
wire [NUM_TILES - 1'b1 : 0] pipelineLock;
wire [NUM_TILES - 1'b1 : 0] weightRAMwrEn;
//neural network
tile_network ANN(
.clk_i (clk),
.en_i (procBegin),
.data_rd_o (inputRead),
.data_rd_i (networkRead),
.data_i (networkDataIn),
.network_idle_o (networkIdle),
.data_o (networkOut),
.proc_complete_o (procComplete),
.weight_wr_i (weightRAMwrEn),
.weight_data_i (weightData),
.pipeline_lock_o (pipelineLock)
);
master_control MCU(
.clk (clk),
.rst (rst),
//AVR SPI
.TXBusy (tx_busy),
.newRXData (new_rx_data),
.RXData (rx_data),
.TXDataBuffer (tx_data),
.newTXData (newTXData),
//MLPNN
.inputRead (inputRead),
.networkIdle (networkIdle),
.procComplete (procComplete),
.networkOut (networkOut),
.networkDataIn (networkDataIn),
.procBegin (procBegin),
.networkRead (networkRead),
.weightRAMwrEn (weightRAMwrEn),
.weightDataOut (weightData),
.pipelineLock (pipelineLock),
.sdramBusy (sdramBusy),
.sdramRXValid (sdramRXValid),
.sdramDataRX (sdramDataRX),
.sdramDataTX (sdramDataTX),
.sdramAddr (sdramAddr),
.sdramTXValid (sdramTXValid),
.sdramRW (sdramRW),
.LED (led)
);
endmodule
|
module BRAMSHIFT_512 (d, q, shift, CLK);
parameter shift_bitsize = 9;
parameter width = 1;
parameter input_pipe_steps = 0;
parameter output_pipe_steps = 0;
output wire [(width*32)-1:0] q;
input wire [(width*32)-1:0] d;
input wire CLK;
input wire [shift_bitsize-1:0] shift;
reg [shift_bitsize-1:0] a_read;
reg [shift_bitsize-1:0] a_write;
reg [shift_bitsize-1:0] true_shift;
wire [(width*32)-1:0] sigin;
datapipe #(.data_width(width*32),.pipe_steps(input_pipe_steps)) input_pipe (
.data(d),
.piped_data(sigin),
.CLK(CLK));
wire [(width*32)-1:0] sigout;
datapipe #(.data_width(width*32),.pipe_steps(output_pipe_steps)) output_pipe (
.data(sigout),
.piped_data(q),
.CLK(CLK));
always@(posedge CLK)
begin
true_shift <= shift + 2; //compensate internal delays, shift is usually tigged
a_read <= a_read + 1;
a_write <= a_read + true_shift;
end
genvar k;
generate
for (k=0; k < width; k=k+1) begin : BRAMS
RAMB16_S36_S36 #(
.INIT_A(36'h000000000), // Value of output RAM registers on Port A at startup
.INIT_B(36'h000000000), // Value of output RAM registers on Port B at startup
.SRVAL_A(36'h000000000), // Port A output value upon SSR assertion
.SRVAL_B(36'h000000000), // Port B output value upon SSR assertion
.WRITE_MODE_A("WRITE_FIRST"), // WRITE_FIRST, READ_FIRST or NO_CHANGE
.WRITE_MODE_B("WRITE_FIRST"), // WRITE_FIRST, READ_FIRST or NO_CHANGE
.SIM_COLLISION_CHECK("ALL"), // "NONE", "WARNING_ONLY", "GENERATE_X_ONLY", "ALL"
// The following INIT_xx declarations specify the initial contents of the RAM
// Address 0 to 127
.INIT_00(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
.INIT_01(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
.INIT_02(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
.INIT_03(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
.INIT_04(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
.INIT_05(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
.INIT_06(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
.INIT_07(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
.INIT_08(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
.INIT_09(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
.INIT_0A(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
.INIT_0B(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
.INIT_0C(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
.INIT_0D(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
.INIT_0E(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
.INIT_0F(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
// Address 128 to 255
.INIT_10(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
.INIT_11(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
.INIT_12(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
.INIT_13(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
.INIT_14(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
.INIT_15(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
.INIT_16(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
.INIT_17(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
.INIT_18(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
.INIT_19(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
.INIT_1A(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
.INIT_1B(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
.INIT_1C(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
.INIT_1D(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
.INIT_1E(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
.INIT_1F(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
// Address 256 to 383
.INIT_20(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
.INIT_21(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
.INIT_22(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
.INIT_23(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
.INIT_24(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
.INIT_25(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
.INIT_26(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
.INIT_27(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
.INIT_28(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
.INIT_29(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
.INIT_2A(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
.INIT_2B(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
.INIT_2C(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
.INIT_2D(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
.INIT_2E(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
.INIT_2F(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
// Address 384 to 511
.INIT_30(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
.INIT_31(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
.INIT_32(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
.INIT_33(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
.INIT_34(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
.INIT_35(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
.INIT_36(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
.INIT_37(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
.INIT_38(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
.INIT_39(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
.INIT_3A(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
.INIT_3B(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
.INIT_3C(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
.INIT_3D(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
.INIT_3E(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
.INIT_3F(256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
// The next set of INITP_xx are for the parity bits
// Address 0 to 127
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
// Address 128 to 255
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
// Address 256 to 383
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
// Address 384 to 511
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000)
) RAMB32_SHIFT (
.DOA(sigout[((k+1)*32)-1:(k*32)]), // Port A 32-bit Data Output
.DOB(), // Port B 32-bit Data Output
.ADDRA({'b0,a_read}), // Port A 9-bit Address Input
.ADDRB({'b0,a_write}), // Port B 9-bit Address Input
.CLKA(CLK), // Port A Clock
.CLKB(CLK), // Port B Clock
.DIA('b0), // Port A 32-bit Data Input
.DIB(sigin[((k+1)*32)-1:(k*32)]), // Port B 32-bit Data Input
.DOPA(), // Port A 4-bit Parity Output
.DOPB(), // Port B 4-bit Parity Output
.DIPA('b0), // Port A 4-bit parity Input
.DIPB('b0), // Port-B 4-bit parity Input
.ENA(1'b1), // Port A RAM Enable Input
.ENB(1'b1), // Port B RAM Enable Input
.SSRA(1'b0), // Port A Synchronous Set/Reset Input
.SSRB(1'b0), // Port B Synchronous Set/Reset Input
.WEA(1'b0), // Port A Write Enable Input
.WEB(1'b1) // Port B Write Enable Input
);
end
endgenerate
endmodule
|
module UARTSample(
clk_x4,
rst_x,
i_rx,
o_tx,
o_data,
o_tx_error,
o_rx_error);
input clk_x4;
input rst_x;
input i_rx;
output o_tx;
output [7:0] o_data;
output o_tx_error;
output o_rx_error;
wire [7:0] w_out;
wire w_out_valid;
wire w_tx_error;
wire w_rx_error;
wire w_busy;
wire w_busy_posedge;
reg [7:0] r_in;
reg r_in_valid;
reg r_tx_error;
reg r_rx_error;
reg [7:0] r_data;
reg [2:0] r_state;
reg r_busy_d;
localparam S_TX_WAIT = 3'b000;
localparam S_TX_H = 3'b001;
localparam S_TX_E = 3'b011;
localparam S_TX_L = 3'b010;
localparam S_TX_O = 3'b110;
localparam C_H = 8'h48;
localparam C_E = 8'h45;
localparam C_L = 8'h4c;
localparam C_O = 8'h4f;
assign o_tx_error = r_tx_error;
assign o_rx_error = r_rx_error;
assign o_data = r_data;
assign w_in = 8'h00;
assign w_in_valid = 1'b0;
assign w_busy_posedge = !r_busy_d & w_busy;
assign w_busy_negedge = r_busy_d & !w_busy;
always @ (posedge clk_x4 or negedge rst_x) begin
if (!rst_x) begin
r_tx_error <= 1'b0;
end else begin
r_tx_error <= r_tx_error | w_tx_error;
end
end
always @ (posedge clk_x4 or negedge rst_x) begin
if (!rst_x) begin
r_rx_error <= 1'b0;
end else begin
r_rx_error <= r_rx_error | w_rx_error;
end
end
always @ (posedge clk_x4 or negedge rst_x) begin
if (!rst_x) begin
r_data <= 8'h00;
end else begin
if (w_out_valid) begin
r_data <= w_out;
end
end
end
always @ (posedge clk_x4) begin
r_busy_d <= w_busy;
end
always @ (posedge clk_x4 or negedge rst_x) begin
if (!rst_x) begin
r_state <= S_TX_WAIT;
r_in <= 8'h00;
r_in_valid <= 1'b0;
end else begin
case (r_state)
S_TX_WAIT: begin
if ((w_out == 8'h0d) && w_out_valid) begin
r_state <= S_TX_H;
r_in <= C_H;
r_in_valid <= 1'b1;
end
end
S_TX_H: begin
if (w_busy_posedge) begin
r_in_valid <= 1'b0;
end else if (w_busy_negedge) begin
r_state <= S_TX_E;
r_in <= C_E;
r_in_valid <= 1'b1;
end
end
S_TX_E: begin
if (w_busy_posedge) begin
r_in_valid <= 1'b0;
end else if (w_busy_negedge) begin
r_state <= S_TX_L;
r_in <= C_L;
r_in_valid <= 1'b1;
end
end
S_TX_L: begin
if (w_busy_posedge) begin
r_in_valid <= 1'b0;
end else if (w_busy_negedge) begin
r_state <= S_TX_O;
r_in <= C_O;
r_in_valid <= 1'b1;
end
end
S_TX_O: begin
if (w_busy_posedge) begin
r_in_valid <= 1'b0;
end else if (w_busy_negedge) begin
r_state <= S_TX_WAIT;
r_in <= 8'h00;
end
end
endcase
end
end
UART uart(
.clk_x4 (clk_x4 ),
.rst_x (rst_x ),
.i_rx (i_rx ),
.o_tx (o_tx ),
.i_data (r_in ),
.i_valid (r_in_valid ),
.o_busy (w_busy ),
.o_data (w_out ),
.o_valid (w_out_valid),
.o_tx_error(w_tx_error ),
.o_rx_error(w_rx_error ));
endmodule
|
module pll100M (
inclk0,
c0);
input inclk0;
output c0;
wire [4:0] sub_wire0;
wire [0:0] sub_wire4 = 1'h0;
wire [0:0] sub_wire1 = sub_wire0[0:0];
wire c0 = sub_wire1;
wire sub_wire2 = inclk0;
wire [1:0] sub_wire3 = {sub_wire4, sub_wire2};
altpll altpll_component (
.inclk (sub_wire3),
.clk (sub_wire0),
.activeclock (),
.areset (1'b0),
.clkbad (),
.clkena ({6{1'b1}}),
.clkloss (),
.clkswitch (1'b0),
.configupdate (1'b0),
.enable0 (),
.enable1 (),
.extclk (),
.extclkena ({4{1'b1}}),
.fbin (1'b1),
.fbmimicbidir (),
.fbout (),
.fref (),
.icdrclk (),
.locked (),
.pfdena (1'b1),
.phasecounterselect ({4{1'b1}}),
.phasedone (),
.phasestep (1'b1),
.phaseupdown (1'b1),
.pllena (1'b1),
.scanaclr (1'b0),
.scanclk (1'b0),
.scanclkena (1'b1),
.scandata (1'b0),
.scandataout (),
.scandone (),
.scanread (1'b0),
.scanwrite (1'b0),
.sclkout0 (),
.sclkout1 (),
.vcooverrange (),
.vcounderrange ());
defparam
altpll_component.bandwidth_type = "AUTO",
altpll_component.clk0_divide_by = 1,
altpll_component.clk0_duty_cycle = 50,
altpll_component.clk0_multiply_by = 2,
altpll_component.clk0_phase_shift = "0",
altpll_component.compensate_clock = "CLK0",
altpll_component.inclk0_input_frequency = 20000,
altpll_component.intended_device_family = "Cyclone IV E",
altpll_component.lpm_hint = "CBX_MODULE_PREFIX=pll100M",
altpll_component.lpm_type = "altpll",
altpll_component.operation_mode = "NORMAL",
altpll_component.pll_type = "AUTO",
altpll_component.port_activeclock = "PORT_UNUSED",
altpll_component.port_areset = "PORT_UNUSED",
altpll_component.port_clkbad0 = "PORT_UNUSED",
altpll_component.port_clkbad1 = "PORT_UNUSED",
altpll_component.port_clkloss = "PORT_UNUSED",
altpll_component.port_clkswitch = "PORT_UNUSED",
altpll_component.port_configupdate = "PORT_UNUSED",
altpll_component.port_fbin = "PORT_UNUSED",
altpll_component.port_inclk0 = "PORT_USED",
altpll_component.port_inclk1 = "PORT_UNUSED",
altpll_component.port_locked = "PORT_UNUSED",
altpll_component.port_pfdena = "PORT_UNUSED",
altpll_component.port_phasecounterselect = "PORT_UNUSED",
altpll_component.port_phasedone = "PORT_UNUSED",
altpll_component.port_phasestep = "PORT_UNUSED",
altpll_component.port_phaseupdown = "PORT_UNUSED",
altpll_component.port_pllena = "PORT_UNUSED",
altpll_component.port_scanaclr = "PORT_UNUSED",
altpll_component.port_scanclk = "PORT_UNUSED",
altpll_component.port_scanclkena = "PORT_UNUSED",
altpll_component.port_scandata = "PORT_UNUSED",
altpll_component.port_scandataout = "PORT_UNUSED",
altpll_component.port_scandone = "PORT_UNUSED",
altpll_component.port_scanread = "PORT_UNUSED",
altpll_component.port_scanwrite = "PORT_UNUSED",
altpll_component.port_clk0 = "PORT_USED",
altpll_component.port_clk1 = "PORT_UNUSED",
altpll_component.port_clk2 = "PORT_UNUSED",
altpll_component.port_clk3 = "PORT_UNUSED",
altpll_component.port_clk4 = "PORT_UNUSED",
altpll_component.port_clk5 = "PORT_UNUSED",
altpll_component.port_clkena0 = "PORT_UNUSED",
altpll_component.port_clkena1 = "PORT_UNUSED",
altpll_component.port_clkena2 = "PORT_UNUSED",
altpll_component.port_clkena3 = "PORT_UNUSED",
altpll_component.port_clkena4 = "PORT_UNUSED",
altpll_component.port_clkena5 = "PORT_UNUSED",
altpll_component.port_extclk0 = "PORT_UNUSED",
altpll_component.port_extclk1 = "PORT_UNUSED",
altpll_component.port_extclk2 = "PORT_UNUSED",
altpll_component.port_extclk3 = "PORT_UNUSED",
altpll_component.width_clock = 5;
endmodule
|
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(GPIO_I, GPIO_O, GPIO_T, SDIO0_WP, TTC0_WAVE0_OUT,
TTC0_WAVE1_OUT, TTC0_WAVE2_OUT, USB0_PORT_INDCTL, USB0_VBUS_PWRSELECT,
USB0_VBUS_PWRFAULT, M_AXI_GP0_ARVALID, M_AXI_GP0_AWVALID, M_AXI_GP0_BREADY,
M_AXI_GP0_RREADY, M_AXI_GP0_WLAST, M_AXI_GP0_WVALID, M_AXI_GP0_ARID, M_AXI_GP0_AWID,
M_AXI_GP0_WID, M_AXI_GP0_ARBURST, M_AXI_GP0_ARLOCK, M_AXI_GP0_ARSIZE, M_AXI_GP0_AWBURST,
M_AXI_GP0_AWLOCK, M_AXI_GP0_AWSIZE, M_AXI_GP0_ARPROT, M_AXI_GP0_AWPROT, M_AXI_GP0_ARADDR,
M_AXI_GP0_AWADDR, M_AXI_GP0_WDATA, M_AXI_GP0_ARCACHE, M_AXI_GP0_ARLEN, M_AXI_GP0_ARQOS,
M_AXI_GP0_AWCACHE, M_AXI_GP0_AWLEN, M_AXI_GP0_AWQOS, M_AXI_GP0_WSTRB, M_AXI_GP0_ACLK,
M_AXI_GP0_ARREADY, M_AXI_GP0_AWREADY, M_AXI_GP0_BVALID, M_AXI_GP0_RLAST,
M_AXI_GP0_RVALID, M_AXI_GP0_WREADY, M_AXI_GP0_BID, M_AXI_GP0_RID, M_AXI_GP0_BRESP,
M_AXI_GP0_RRESP, M_AXI_GP0_RDATA, FCLK_CLK0, FCLK_RESET0_N, MIO, DDR_CAS_n, DDR_CKE, DDR_Clk_n,
DDR_Clk, DDR_CS_n, DDR_DRSTB, DDR_ODT, DDR_RAS_n, DDR_WEB, DDR_BankAddr, DDR_Addr, DDR_VRN,
DDR_VRP, DDR_DM, DDR_DQ, DDR_DQS_n, DDR_DQS, PS_SRSTB, PS_CLK, PS_PORB)
/* synthesis syn_black_box black_box_pad_pin="GPIO_I[63:0],GPIO_O[63:0],GPIO_T[63:0],SDIO0_WP,TTC0_WAVE0_OUT,TTC0_WAVE1_OUT,TTC0_WAVE2_OUT,USB0_PORT_INDCTL[1:0],USB0_VBUS_PWRSELECT,USB0_VBUS_PWRFAULT,M_AXI_GP0_ARVALID,M_AXI_GP0_AWVALID,M_AXI_GP0_BREADY,M_AXI_GP0_RREADY,M_AXI_GP0_WLAST,M_AXI_GP0_WVALID,M_AXI_GP0_ARID[11:0],M_AXI_GP0_AWID[11:0],M_AXI_GP0_WID[11:0],M_AXI_GP0_ARBURST[1:0],M_AXI_GP0_ARLOCK[1:0],M_AXI_GP0_ARSIZE[2:0],M_AXI_GP0_AWBURST[1:0],M_AXI_GP0_AWLOCK[1:0],M_AXI_GP0_AWSIZE[2:0],M_AXI_GP0_ARPROT[2:0],M_AXI_GP0_AWPROT[2:0],M_AXI_GP0_ARADDR[31:0],M_AXI_GP0_AWADDR[31:0],M_AXI_GP0_WDATA[31:0],M_AXI_GP0_ARCACHE[3:0],M_AXI_GP0_ARLEN[3:0],M_AXI_GP0_ARQOS[3:0],M_AXI_GP0_AWCACHE[3:0],M_AXI_GP0_AWLEN[3:0],M_AXI_GP0_AWQOS[3:0],M_AXI_GP0_WSTRB[3:0],M_AXI_GP0_ACLK,M_AXI_GP0_ARREADY,M_AXI_GP0_AWREADY,M_AXI_GP0_BVALID,M_AXI_GP0_RLAST,M_AXI_GP0_RVALID,M_AXI_GP0_WREADY,M_AXI_GP0_BID[11:0],M_AXI_GP0_RID[11:0],M_AXI_GP0_BRESP[1:0],M_AXI_GP0_RRESP[1:0],M_AXI_GP0_RDATA[31:0],FCLK_CLK0,FCLK_RESET0_N,MIO[53:0],DDR_CAS_n,DDR_CKE,DDR_Clk_n,DDR_Clk,DDR_CS_n,DDR_DRSTB,DDR_ODT,DDR_RAS_n,DDR_WEB,DDR_BankAddr[2:0],DDR_Addr[14:0],DDR_VRN,DDR_VRP,DDR_DM[3:0],DDR_DQ[31:0],DDR_DQS_n[3:0],DDR_DQS[3:0],PS_SRSTB,PS_CLK,PS_PORB" */;
input [63:0]GPIO_I;
output [63:0]GPIO_O;
output [63:0]GPIO_T;
input SDIO0_WP;
output TTC0_WAVE0_OUT;
output TTC0_WAVE1_OUT;
output TTC0_WAVE2_OUT;
output [1:0]USB0_PORT_INDCTL;
output USB0_VBUS_PWRSELECT;
input USB0_VBUS_PWRFAULT;
output M_AXI_GP0_ARVALID;
output M_AXI_GP0_AWVALID;
output M_AXI_GP0_BREADY;
output M_AXI_GP0_RREADY;
output M_AXI_GP0_WLAST;
output M_AXI_GP0_WVALID;
output [11:0]M_AXI_GP0_ARID;
output [11:0]M_AXI_GP0_AWID;
output [11:0]M_AXI_GP0_WID;
output [1:0]M_AXI_GP0_ARBURST;
output [1:0]M_AXI_GP0_ARLOCK;
output [2:0]M_AXI_GP0_ARSIZE;
output [1:0]M_AXI_GP0_AWBURST;
output [1:0]M_AXI_GP0_AWLOCK;
output [2:0]M_AXI_GP0_AWSIZE;
output [2:0]M_AXI_GP0_ARPROT;
output [2:0]M_AXI_GP0_AWPROT;
output [31:0]M_AXI_GP0_ARADDR;
output [31:0]M_AXI_GP0_AWADDR;
output [31:0]M_AXI_GP0_WDATA;
output [3:0]M_AXI_GP0_ARCACHE;
output [3:0]M_AXI_GP0_ARLEN;
output [3:0]M_AXI_GP0_ARQOS;
output [3:0]M_AXI_GP0_AWCACHE;
output [3:0]M_AXI_GP0_AWLEN;
output [3:0]M_AXI_GP0_AWQOS;
output [3:0]M_AXI_GP0_WSTRB;
input M_AXI_GP0_ACLK;
input M_AXI_GP0_ARREADY;
input M_AXI_GP0_AWREADY;
input M_AXI_GP0_BVALID;
input M_AXI_GP0_RLAST;
input M_AXI_GP0_RVALID;
input M_AXI_GP0_WREADY;
input [11:0]M_AXI_GP0_BID;
input [11:0]M_AXI_GP0_RID;
input [1:0]M_AXI_GP0_BRESP;
input [1:0]M_AXI_GP0_RRESP;
input [31:0]M_AXI_GP0_RDATA;
output FCLK_CLK0;
output FCLK_RESET0_N;
inout [53:0]MIO;
inout DDR_CAS_n;
inout DDR_CKE;
inout DDR_Clk_n;
inout DDR_Clk;
inout DDR_CS_n;
inout DDR_DRSTB;
inout DDR_ODT;
inout DDR_RAS_n;
inout DDR_WEB;
inout [2:0]DDR_BankAddr;
inout [14:0]DDR_Addr;
inout DDR_VRN;
inout DDR_VRP;
inout [3:0]DDR_DM;
inout [31:0]DDR_DQ;
inout [3:0]DDR_DQS_n;
inout [3:0]DDR_DQS;
inout PS_SRSTB;
inout PS_CLK;
inout PS_PORB;
endmodule
|
module EggTimer(
input [7:0]SW,
input [2:0]KEY,
input CLOCK_50,
output [6:0]HEX0,
output [6:0]HEX1,
output [6:0]HEX2,
output [6:0]HEX3,
output [9:0]LEDR,
output [7:0]LEDG
);
reg [3:0] counter0 = 0;
reg [3:0] counter1 = 0;
reg [3:0] counter2 = 0;
reg [3:0] counter3 = 0;
reg [9:0] ledr_buf = 10'b0000000000;
reg [0:0] pause = 0; //0 is pause, 1 is continue
reg [0:0] reset_buf = 1;
wire RESET;
wire KEY2 = KEY[2];
//Get clock signal of period=1000ms
ClkDivider(CLOCK_50, CLK);
/*
* PAUSE SIGNAL
*/
TFlipFlop(.t(~KEY2), .clk(CLOCK_50), .q(PAUSE));
TFlipFlop(.t(~KEY[1]), .clk(CLOCK_50), .q(MINUTE));
DFlipFlop(.d(~KEY[0]), .clk(CLOCK_50), .q(RESET));
assign LEDG[0] = RESET;
assign LEDG[1] = ~KEY2;
assign LEDG[2] = pause;
assign LEDG[3] = reset_buf;
always @(posedge CLK or posedge RESET or posedge ~KEY2) begin
if (~KEY2 == 1'b1) begin
pause <= ~PAUSE;
reset_buf <= 0;
end else
if (RESET == 1'b1) begin
reset_buf <= 1;
pause <= 0;
counter0 <= 0;
counter1 <= 0;
counter2 <= 0;
counter3 <= 0;
ledr_buf <= 0;
end else
if (CLK == 1'b1) begin
if (pause == 1'b0) begin
if (reset_buf == 1) begin
if (MINUTE == 1'b0) begin
if (SW[3:0] <= 9) begin
counter0 <= SW[3:0];
end else begin
counter0 <= 9;
end
if (SW[7:4] <= 5) begin
counter1 <= SW[7:4];
end else begin
counter1 <= 5;
end
end
if (MINUTE == 1'b1) begin
if (SW[3:0] <= 9) begin
counter2 <= SW[3:0];
end else begin
counter2 <= 9;
end
if (SW[7:4] <= 5) begin
counter3 <= SW[7:4];
end else begin
counter3 <= 5;
end
end
end
end else if (pause == 1'b1) begin
if (counter0 != 0) begin
counter0 <= counter0 - 1;
end else if (counter1 != 0) begin
counter1 <= counter1 - 1;
counter0 <= 9;
end else if (counter2 != 0) begin
counter2 <= counter2 - 1;
counter1 <= 5;
counter0 <= 9;
end else if (counter3 != 0) begin
counter3 <= counter3 - 1;
counter2 <= 9;
counter1 <= 5;
counter0 <= 9;
end else
if (reset_buf == 0) begin
ledr_buf <= ~ledr_buf;
end
end
end
end
seven_seg(counter0, HEX0);
seven_seg(counter1, HEX1);
seven_seg(counter2, HEX2);
seven_seg(counter3, HEX3);
ledr(ledr_buf, LEDR[9:0]);
endmodule
|
module ClkDivider(input clkIn, output clkOut);
reg[31: 0] counter;
reg clkReg;
assign clkOut = clkReg;
always @(posedge clkIn) begin
counter <= counter + 1;
if (counter == 25000000) begin
clkReg <= ~clkReg;
counter <= 0;
end
end
endmodule
|
module seven_seg (
input [3:0] num,
output [6:0] display
);
assign display =
num == 0 ? ~7'b0111111:
num == 1 ? ~7'b0000110:
num == 2 ? ~7'b1011011:
num == 3 ? ~7'b1001111:
num == 4 ? ~7'b1100110:
num == 5 ? ~7'b1101101:
num == 6 ? ~7'b1111101:
num == 7 ? ~7'b0000111:
num == 8 ? ~7'b1111111:
num == 9 ? ~7'b1100111:
7'bxxxxxxx;
endmodule
|
module ledr(
input [9:0] buffer,
output [9:0] lights
);
assign lights = buffer;
endmodule
|
module TFlipFlop(
input t, clk,
output reg q
);
always @(posedge t) begin
if (t) q = ~q;
end
endmodule
|
module DFlipFlop(
input d, clk,
output reg q
);
always @(posedge clk) begin
if (q != d) q = d;
end
endmodule
|
module Inverter (
input positive,
output negative
);
assign negative = ~positive;
endmodule
|
module flag_domain_crossing(
input wire CLK_A,
input wire CLK_B,
input wire FLAG_IN_CLK_A,
output wire FLAG_OUT_CLK_B
);
reg FLAG_TOGGLE_CLK_A;
initial FLAG_TOGGLE_CLK_A = 0;
always @(posedge CLK_A)
begin
if (FLAG_IN_CLK_A)
begin
FLAG_TOGGLE_CLK_A <= ~FLAG_TOGGLE_CLK_A;
end
end
(* ASYNC_REG = "TRUE" *) reg flag_out_d_ff_1;
(* ASYNC_REG = "TRUE" *) reg flag_out_d_ff_2;
reg flag_out_d_ff_3;
always @(posedge CLK_B) // first stage
begin
flag_out_d_ff_1 <= FLAG_TOGGLE_CLK_A;
end
always @(posedge CLK_B) // second stage
begin
flag_out_d_ff_2 <= flag_out_d_ff_1;
end
always @(posedge CLK_B)
begin
flag_out_d_ff_3 <= flag_out_d_ff_2;
end
assign FLAG_OUT_CLK_B = (flag_out_d_ff_3 ^ flag_out_d_ff_2); // XOR
endmodule
|
module mkBiasWorker4B(
input wciS0_Clk,
input wciS0_MReset_n,
input [2 : 0] wciS0_MCmd,
input wciS0_MAddrSpace,
input [3 : 0] wciS0_MByteEn,
input [31 : 0] wciS0_MAddr,
input [31 : 0] wciS0_MData,
output [1 : 0] wciS0_SResp,
output [31 : 0] wciS0_SData,
output wciS0_SThreadBusy,
output [1 : 0] wciS0_SFlag,
input [1 : 0] wciS0_MFlag,
input [2 : 0] wsiS0_MCmd,
input wsiS0_MReqLast,
input wsiS0_MBurstPrecise,
input [11 : 0] wsiS0_MBurstLength,
input [31 : 0] wsiS0_MData,
input [3 : 0] wsiS0_MByteEn,
input [7 : 0] wsiS0_MReqInfo,
output wsiS0_SThreadBusy,
output wsiS0_SReset_n,
input wsiS0_MReset_n,
output [2 : 0] wsiM0_MCmd,
output wsiM0_MReqLast,
output wsiM0_MBurstPrecise,
output [11 : 0] wsiM0_MBurstLength,
output [31 : 0] wsiM0_MData,
output [3 : 0] wsiM0_MByteEn,
output [7 : 0] wsiM0_MReqInfo,
input wsiM0_SThreadBusy,
output wsiM0_MReset_n,
input wsiM0_SReset_n );
// Instance the VHDL Bias Worker "bias_vhdl"...
bias_vhdl bias_vi(
.ctl_Clk (wciS0_Clk), // in std_logic;
.ctl_MAddr (wciS0_MAddr[4:0]), // in std_logic_vector(4 downto 0);
.ctl_MAddrSpace (wciS0_MAddrSpace), // in std_logic_vector(0 downto 0);
.ctl_MCmd (wciS0_MCmd), // in std_logic_vector(2 downto 0);
.ctl_MData (wciS0_MData), // in std_logic_vector(31 downto 0);
.ctl_MFlag (wciS0_MFlag), // in std_logic_vector(1 downto 0);
.ctl_MReset_n (wciS0_MReset_n), // in std_logic;
.ctl_SData (wciS0_SData), // out std_logic_vector(31 downto 0);
.ctl_SFlag (wciS0_SFlag), // out std_logic_vector(1 downto 0);
.ctl_SResp (wciS0_SResp), // out std_logic_vector(1 downto 0);
.ctl_SThreadBusy (wciS0_SThreadBusy), // out std_logic_vector(0 downto 0);
.in_MBurstLength (wsiS0_MBurstLength), // in std_logic_vector(11 downto 0);
.in_MByteEn (wsiS0_MByteEn), // in std_logic_vector(3 downto 0);
.in_MCmd (wsiS0_MCmd), // in std_logic_vector(2 downto 0);
.in_MData (wsiS0_MData), // in std_logic_vector(31 downto 0);
.in_MBurstPrecise (wsiS0_MBurstPrecise), // in std_logic;
.in_MReqInfo (wsiS0_MReqInfo), // in std_logic_vector(7 downto 0);
.in_MReqLast (wsiS0_MReqLast), // in std_logic;
.in_MReset_n (wsiS0_MReset_n), // in std_logic;
.in_SReset_n (wsiS0_SReset_n), // out std_logic;
.in_SThreadBusy (wsiS0_SThreadBusy), // out std_logic_vector(0 downto 0);
.out_SReset_n (wsiM0_SReset_n), // in std_logic;
.out_SThreadBusy (wsiM0_SThreadBusy), // in std_logic_vector(0 downto 0);
.out_MBurstLength (wsiM0_MBurstLength), // out std_logic_vector(11 downto 0);
.out_MByteEn (wsiM0_MByteEn), // out std_logic_vector(3 downto 0);
.out_MCmd (wsiM0_MCmd), // out std_logic_vector(2 downto 0);
.out_MData (wsiM0_MData), // out std_logic_vector(31 downto 0);
.out_MBurstPrecise (wsiM0_MBurstPrecise), // out std_logic;
.out_MReqInfo (wsiM0_MReqInfo), // out std_logic_vector(7 downto 0);
.out_MReqLast (wsiM0_MReqLast), // out std_logic;
.out_MReset_n (wsiM0_MReset_n) // out std_logic
);
endmodule
|
module sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap_4 (
X ,
A ,
VPWRIN,
VPWR ,
VGND ,
VPB
);
output X ;
input A ;
input VPWRIN;
input VPWR ;
input VGND ;
input VPB ;
sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap base (
.X(X),
.A(A),
.VPWRIN(VPWRIN),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB)
);
endmodule
|
module sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap_4 (
X,
A
);
output X;
input A;
// Voltage supply signals
wire VPWRIN;
supply1 VPWR ;
supply0 VGND ;
supply1 VPB ;
sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap base (
.X(X),
.A(A)
);
endmodule
|
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
reg toggle;
integer cyc; initial cyc=1;
wire [7:0] cyc_copy = cyc[7:0];
always @ (negedge clk) begin
AssertionFalse1: assert (cyc<100);
assert (!(cyc==5) || toggle);
// FIX cover {cyc==3 || cyc==4};
// FIX cover {cyc==9} report "DefaultClock,expect=1";
// FIX cover {(cyc==5)->toggle} report "ToggleLogIf,expect=1";
end
always @ (posedge clk) begin
if (cyc!=0) begin
cyc <= cyc + 1;
toggle <= !cyc[0];
if (cyc==7) assert (cyc[0] == cyc[1]); // bug743
if (cyc==9) begin
`ifdef FAILING_ASSERTIONS
assert (0) else $info;
assert (0) else $info("Info message");
assume (0) else $info("Info message from failing assumption");
assert (0) else $info("Info message, cyc=%d", cyc);
InWarningBlock: assert (0) else $warning("Warning.... 1.0=%f 2.0=%f", 1.0, 2.0);
InErrorBlock: assert (0) else $error("Error....");
assert (0) else $fatal(1,"Fatal....");
`endif
end
if (cyc==10) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
end
endmodule
|
module sky130_fd_sc_hd__and4b (
X ,
A_N,
B ,
C ,
D
);
output X ;
input A_N;
input B ;
input C ;
input D ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
|
module bsg_mul_booth_4_block_rep #(parameter [31:0] blocks_p=1
,parameter S_above_vec_p=0
,parameter dot_bar_vec_p=0
,parameter B_vec_p=0
,parameter one_vec_p=0
)
( input [4:0][2:0] SDN_i
, input cr_i
, input [blocks_p-1:0][3:0][1:0] y_vec_i
, output cl_o
, output [blocks_p-1:0] c_o
, output [blocks_p-1:0] s_o
);
wire [blocks_p:0] ci_local;
genvar i;
for (i = 0; i < blocks_p; i=i+1)
begin: rof
localparam S_above_vec_tmp = (S_above_vec_p >> (i << 2)) & 4'hf;
localparam S_dot_bar_vec_tmp = (dot_bar_vec_p >> (i << 2)) & 4'hf;
localparam B_vec_tmp = (B_vec_p >> (i << 2)) & 4'hf;
localparam one_vec_tmp = (one_vec_p >> (i << 2)) & 4'hf;
bsg_mul_booth_4_block #(
.S_above_vec_p(S_above_vec_tmp)
,.dot_bar_vec_p(S_dot_bar_vec_tmp)
,.B_vec_p(B_vec_tmp)
,.one_vec_p(one_vec_tmp)
)
b4b (.SDN_i(SDN_i), .y_i (y_vec_i[i])
, .cr_i(ci_local[i]), .cl_o(ci_local[i+1]), .c_o (c_o[i]), .s_o (s_o[i]));
end // block: rof
assign ci_local[0] = cr_i;
assign cl_o = ci_local[blocks_p];
endmodule
|
module axi_bram_reader #
(
parameter integer AXI_DATA_WIDTH = 32,
parameter integer AXI_ADDR_WIDTH = 32,
parameter integer BRAM_DATA_WIDTH = 32,
parameter integer BRAM_ADDR_WIDTH = 10
)
(
// System signals
input wire aclk,
input wire aresetn,
// Slave side
input wire [AXI_ADDR_WIDTH-1:0] s_axi_araddr, // AXI4-Lite slave: Read address
input wire s_axi_arvalid, // AXI4-Lite slave: Read address valid
output wire s_axi_arready, // AXI4-Lite slave: Read address ready
output wire [AXI_DATA_WIDTH-1:0] s_axi_rdata, // AXI4-Lite slave: Read data
output wire [1:0] s_axi_rresp, // AXI4-Lite slave: Read data response
output wire s_axi_rvalid, // AXI4-Lite slave: Read data valid
input wire s_axi_rready, // AXI4-Lite slave: Read data ready
// BRAM port
output wire bram_porta_clk,
output wire bram_porta_rst,
output wire [BRAM_ADDR_WIDTH-1:0] bram_porta_addr,
input wire [BRAM_DATA_WIDTH-1:0] bram_porta_rddata
);
function integer clogb2 (input integer value);
for(clogb2 = 0; value > 0; clogb2 = clogb2 + 1) value = value >> 1;
endfunction
localparam integer ADDR_LSB = clogb2(AXI_DATA_WIDTH/8 - 1);
reg int_arready_reg, int_arready_next;
reg int_rvalid_reg, int_rvalid_next;
always @(posedge aclk)
begin
if(~aresetn)
begin
int_arready_reg <= 1'b0;
int_rvalid_reg <= 1'b0;
end
else
begin
int_arready_reg <= int_arready_next;
int_rvalid_reg <= int_rvalid_next;
end
end
always @*
begin
int_arready_next = int_arready_reg;
int_rvalid_next = int_rvalid_reg;
if(s_axi_arvalid)
begin
int_arready_next = 1'b1;
int_rvalid_next = 1'b1;
end
if(int_arready_reg)
begin
int_arready_next = 1'b0;
end
if(s_axi_rready & int_rvalid_reg)
begin
int_rvalid_next = 1'b0;
end
end
assign s_axi_rresp = 2'd0;
assign s_axi_arready = int_arready_reg;
assign s_axi_rdata = bram_porta_rddata;
assign s_axi_rvalid = int_rvalid_reg;
assign bram_porta_clk = aclk;
assign bram_porta_rst = ~aresetn;
assign bram_porta_addr = s_axi_araddr[ADDR_LSB+BRAM_ADDR_WIDTH-1:ADDR_LSB];
endmodule
|
module des_comp_gen_fx_color
(
input clk,
input rstn,
input signed [31:0] dx_fx, // 16.16
input signed [31:0] dy_fx, // 16.16
input [95:0] cmp_i,
output [7:0] curr_i
);
reg signed [57:0] ix;
reg signed [57:0] iy;
reg signed [57:0] ixy;
reg signed [19:0] curr;
assign curr_i = (curr[19]) ? 8'h00 : // Under flow.
(curr[18]) ? 8'hff : // Over flow.
curr[17:10]; // Normal.
wire [17:0] sp_fx;
wire signed [25:0] idx_fx;
wire signed [25:0] idy_fx;
assign sp_fx = flt_fx_8p10(cmp_i[95:64]);
assign idx_fx = flt_fx_16p10(cmp_i[63:32]);
assign idy_fx = flt_fx_16p10(cmp_i[31:0]);
always @(posedge clk) begin
ix <= dx_fx * idx_fx; // 16.16 * 16.10 = 32.26
iy <= dy_fx * idy_fx; // 16.16 * 16.10 = 32.26
ixy <= iy + ix; // 32.26 + 32.26 = 32.26
curr <= ixy[35:16] + {2'b00, sp_fx}; // 10.10 + 10.10 = 10.10
end
//////////////////////////////////////////////////////////////////
// Float to fixed converts floating point numbers to 16.16 sign
//
//
function [25:0] flt_fx_16p10;
input [31:0] fp_in; // Floating point in IEEE fmt
// 16.10, Color.
reg [7:0] bias_exp; /* Real exponent -127 - 128 */
reg [7:0] bias_exp2; /* Real exponent 2's comp */
reg [47:0] bias_mant; /* mantissa expanded to 16.16 fmt */
reg [47:0] int_fixed_out;
reg [31:0] fixed_out;
begin
bias_mant = {25'h0001, fp_in[22:0]};
bias_exp = fp_in[30:23] - 8'd127;
bias_exp2 = ~bias_exp + 8'h1;
// infinity or NaN - Don't do anything special, will overflow
// zero condition
if (fp_in[30:0] == 31'b0) int_fixed_out = 0;
// negative exponent
else if (bias_exp[7]) int_fixed_out = bias_mant >> bias_exp2;
// positive exponent
else int_fixed_out = bias_mant << bias_exp;
fixed_out = int_fixed_out[38:13];
flt_fx_16p10 = (fp_in[31]) ? ~fixed_out[25:0] + 26'h1 : fixed_out[25:0];
end
endfunction
function [17:0] flt_fx_8p10;
input [31:0] fp_in; // Floating point in IEEE fmt
// 16.10, Color.
reg [7:0] bias_exp; /* Real exponent -127 - 128 */
reg [7:0] bias_exp2; /* Real exponent 2's comp */
reg [47:0] bias_mant; /* mantissa expanded to 16.16 fmt */
reg [47:0] int_fixed_out;
reg [31:0] fixed_out;
begin
bias_mant = {25'h0001, fp_in[22:0]};
bias_exp = fp_in[30:23] - 8'd127;
bias_exp2 = ~bias_exp + 8'h1;
// infinity or NaN - Don't do anything special, will overflow
// zero condition
if (fp_in[30:0] == 31'b0) int_fixed_out = 0;
// negative exponent
else if (bias_exp[7]) int_fixed_out = bias_mant >> bias_exp2;
// positive exponent
else int_fixed_out = bias_mant << bias_exp;
fixed_out = int_fixed_out[31:13];
flt_fx_8p10 = (fp_in[31]) ? ~fixed_out[17:0] + 18'h1 : fixed_out[17:0];
end
endfunction
endmodule
|
module sky130_fd_sc_hvl__nor3 (
Y,
A,
B,
C
);
// Module ports
output Y;
input A;
input B;
input C;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire nor0_out_Y;
// Name Output Other arguments
nor nor0 (nor0_out_Y, C, A, B );
buf buf0 (Y , nor0_out_Y );
endmodule
|
module sky130_fd_sc_ms__clkinv (
Y,
A
);
output Y;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
|
module sky130_fd_sc_ls__nand4bb_2 (
Y ,
A_N ,
B_N ,
C ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A_N ;
input B_N ;
input C ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__nand4bb base (
.Y(Y),
.A_N(A_N),
.B_N(B_N),
.C(C),
.D(D),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
|
module sky130_fd_sc_ls__nand4bb_2 (
Y ,
A_N,
B_N,
C ,
D
);
output Y ;
input A_N;
input B_N;
input C ;
input D ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__nand4bb base (
.Y(Y),
.A_N(A_N),
.B_N(B_N),
.C(C),
.D(D)
);
endmodule
|
module sky130_fd_sc_hvl__lsbuflv2hv_symmetric (
//# {{data|Data Signals}}
input A,
output X
);
// Voltage supply signals
supply1 VPWR ;
supply0 VGND ;
supply1 LVPWR;
supply1 VPB ;
supply0 VNB ;
endmodule
|
module sky130_fd_sc_hs__tapmet1 (
VPWR,
VGND
);
input VPWR;
input VGND;
endmodule
|
module sky130_fd_sc_lp__a31oi (
Y ,
A1,
A2,
A3,
B1
);
// Module ports
output Y ;
input A1;
input A2;
input A3;
input B1;
// Local signals
wire and0_out ;
wire nor0_out_Y;
// Name Output Other arguments
and and0 (and0_out , A3, A1, A2 );
nor nor0 (nor0_out_Y, B1, and0_out );
buf buf0 (Y , nor0_out_Y );
endmodule
|
module if_id_buffer(
input wire clock,
input wire reset,
input wire[`SIGNAL_BUS] stall,
input wire[`INST_ADDR_BUS] if_program_counter,
input wire[`INST_DATA_BUS] if_instruction,
output reg[`INST_ADDR_BUS] id_program_counter,
output reg[`INST_DATA_BUS] id_instruction
);
always @ (posedge clock) begin
if (reset == `ENABLE) begin
id_program_counter <= 0; // FIXME: Zero word should be used here, but 0 is used, check it later.
id_instruction <= 0; // FIXME: Zero word should be used here, but 0 is used, check it later.
end else if (stall[1] == `ENABLE && stall[2] == `DISABLE) begin
id_program_counter <= 0; // FIXME: Zero word should be used here, but 0 is used, check it later.
id_instruction <= 0; // FIXME: Zero word should be used here, but 0 is used, check it later.
end else if (stall[1] == `DISABLE) begin
id_program_counter <= if_program_counter;
id_instruction <= if_instruction;
end
end
endmodule
|
module counters_8bit_with_TD_ff(
input Clk,
input Enable,
input Clear,
output [7:0] Q
);
T_ff_with_D_ff SR0 (.Clk(Clk), .T(Enable), .reset_n(Clear), .Q(Q[0]));
T_ff_with_D_ff SR1 (.Clk(Clk), .T(Enable & Q[0]), .reset_n(Clear), .Q(Q[1]));
T_ff_with_D_ff SR2 (.Clk(Clk), .T(Enable & Q[0] & Q[1]), .reset_n(Clear), .Q(Q[2]));
T_ff_with_D_ff SR3 (.Clk(Clk), .T(Enable & Q[0] & Q[1] & Q[2]), .reset_n(Clear), .Q(Q[3]));
T_ff_with_D_ff SR4 (.Clk(Clk), .T(Enable & Q[0] & Q[1] & Q[2] & Q[3]), .reset_n(Clear), .Q(Q[4]));
T_ff_with_D_ff SR5 (.Clk(Clk), .T(Enable & Q[0] & Q[1] & Q[2] & Q[3] & Q[4]), .reset_n(Clear), .Q(Q[5]));
T_ff_with_D_ff SR6 (.Clk(Clk), .T(Enable & Q[0] & Q[1] & Q[2] & Q[3] & Q[4] & Q[5]), .reset_n(Clear), .Q(Q[6]));
T_ff_with_D_ff SR7 (.Clk(Clk), .T(Enable & Q[0] & Q[1] & Q[2] & Q[3] & Q[4] & Q[5] & Q[6]), .reset_n(Clear), .Q(Q[7]));
endmodule
|
module sky130_fd_sc_ls__buf_2 (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__buf base (
.X(X),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
|
module sky130_fd_sc_ls__buf_2 (
X,
A
);
output X;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__buf base (
.X(X),
.A(A)
);
endmodule
|
module altera_up_video_camera_decoder (
// Inputs
clk,
reset,
PIXEL_DATA,
LINE_VALID,
FRAME_VALID,
ready,
// Bidirectional
// Outputs
data,
startofpacket,
endofpacket,
valid
);
/*****************************************************************************
* Parameter Declarations *
*****************************************************************************/
parameter DW = 9;
/*****************************************************************************
* Port Declarations *
*****************************************************************************/
// Inputs
input clk;
input reset;
input [DW: 0] PIXEL_DATA;
input LINE_VALID;
input FRAME_VALID;
input ready;
// Bidirectional
// Outputs
output reg [DW: 0] data;
output reg startofpacket;
output reg endofpacket;
output reg valid;
/*****************************************************************************
* Constant Declarations *
*****************************************************************************/
/*****************************************************************************
* Internal Wires and Registers Declarations *
*****************************************************************************/
// Internal Wires
wire read_temps;
// Internal Registers
reg [DW: 0] io_pixel_data;
reg io_line_valid;
reg io_frame_valid;
reg frame_sync;
reg [DW: 0] temp_data;
reg temp_start;
reg temp_end;
reg temp_valid;
// State Machine Registers
/*****************************************************************************
* Finite State Machine(s) *
*****************************************************************************/
/*****************************************************************************
* Sequential Logic *
*****************************************************************************/
// Input Registers
always @ (posedge clk)
begin
io_pixel_data <= PIXEL_DATA;
io_line_valid <= LINE_VALID;
io_frame_valid <= FRAME_VALID;
end
// Output Registers
always @ (posedge clk)
begin
if (reset)
begin
data <= 'h0;
startofpacket <= 1'b0;
endofpacket <= 1'b0;
valid <= 1'b0;
end
else if (read_temps)
begin
data <= temp_data;
startofpacket <= temp_start;
endofpacket <= temp_end;
valid <= temp_valid;
end
else if (ready)
valid <= 1'b0;
end
// Internal Registers
always @ (posedge clk)
begin
if (reset)
frame_sync <= 1'b0;
else if (~io_frame_valid)
frame_sync <= 1'b1;
else if (io_line_valid & io_frame_valid)
frame_sync <= 1'b0;
end
always @ (posedge clk)
begin
if (reset)
begin
temp_data <= 'h0;
temp_start <= 1'b0;
temp_end <= 1'b0;
temp_valid <= 1'b0;
end
else if (read_temps)
begin
temp_data <= io_pixel_data;
temp_start <= frame_sync;
temp_end <= ~io_frame_valid;
temp_valid <= io_line_valid & io_frame_valid;
end
else if (~io_frame_valid)
begin
temp_end <= ~io_frame_valid;
end
end
/*****************************************************************************
* Combinational Logic *
*****************************************************************************/
// Output Assignments
// Internal Assignments
assign read_temps = (ready | ~valid) &
((io_line_valid & io_frame_valid) |
((temp_start | temp_end) & temp_valid));
/*****************************************************************************
* Internal Modules *
*****************************************************************************/
endmodule
|
module PmodESP32
(AXI_LITE_GPIO_araddr,
AXI_LITE_GPIO_arready,
AXI_LITE_GPIO_arvalid,
AXI_LITE_GPIO_awaddr,
AXI_LITE_GPIO_awready,
AXI_LITE_GPIO_awvalid,
AXI_LITE_GPIO_bready,
AXI_LITE_GPIO_bresp,
AXI_LITE_GPIO_bvalid,
AXI_LITE_GPIO_rdata,
AXI_LITE_GPIO_rready,
AXI_LITE_GPIO_rresp,
AXI_LITE_GPIO_rvalid,
AXI_LITE_GPIO_wdata,
AXI_LITE_GPIO_wready,
AXI_LITE_GPIO_wstrb,
AXI_LITE_GPIO_wvalid,
AXI_LITE_UART_araddr,
AXI_LITE_UART_arready,
AXI_LITE_UART_arvalid,
AXI_LITE_UART_awaddr,
AXI_LITE_UART_awready,
AXI_LITE_UART_awvalid,
AXI_LITE_UART_bready,
AXI_LITE_UART_bresp,
AXI_LITE_UART_bvalid,
AXI_LITE_UART_rdata,
AXI_LITE_UART_rready,
AXI_LITE_UART_rresp,
AXI_LITE_UART_rvalid,
AXI_LITE_UART_wdata,
AXI_LITE_UART_wready,
AXI_LITE_UART_wstrb,
AXI_LITE_UART_wvalid,
Pmod_out_pin10_i,
Pmod_out_pin10_o,
Pmod_out_pin10_t,
Pmod_out_pin1_i,
Pmod_out_pin1_o,
Pmod_out_pin1_t,
Pmod_out_pin2_i,
Pmod_out_pin2_o,
Pmod_out_pin2_t,
Pmod_out_pin3_i,
Pmod_out_pin3_o,
Pmod_out_pin3_t,
Pmod_out_pin4_i,
Pmod_out_pin4_o,
Pmod_out_pin4_t,
Pmod_out_pin7_i,
Pmod_out_pin7_o,
Pmod_out_pin7_t,
Pmod_out_pin8_i,
Pmod_out_pin8_o,
Pmod_out_pin8_t,
Pmod_out_pin9_i,
Pmod_out_pin9_o,
Pmod_out_pin9_t,
gpio_interrupt,
s_axi_aclk,
s_axi_aresetn,
uart_interrupt);
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 AXI_LITE_GPIO " *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME AXI_LITE_GPIO, ADDR_WIDTH 9, ARUSER_WIDTH 0, AWUSER_WIDTH 0, BUSER_WIDTH 0, CLK_DOMAIN PmodESP32_s_axi_aclk_0, DATA_WIDTH 32, FREQ_HZ 100000000, HAS_BRESP 1, HAS_BURST 0, HAS_CACHE 0, HAS_LOCK 0, HAS_PROT 0, HAS_QOS 0, HAS_REGION 0, HAS_RRESP 1, HAS_WSTRB 1, ID_WIDTH 0, MAX_BURST_LENGTH 1, NUM_READ_OUTSTANDING 1, NUM_READ_THREADS 1, NUM_WRITE_OUTSTANDING 1, NUM_WRITE_THREADS 1, PHASE 0.000, PROTOCOL AXI4LITE, READ_WRITE_MODE READ_WRITE, RUSER_BITS_PER_BYTE 0, RUSER_WIDTH 0, SUPPORTS_NARROW_BURST 0, WUSER_BITS_PER_BYTE 0, WUSER_WIDTH 0" *) input [8:0]AXI_LITE_GPIO_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 AXI_LITE_GPIO " *) output AXI_LITE_GPIO_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 AXI_LITE_GPIO " *) input AXI_LITE_GPIO_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 AXI_LITE_GPIO " *) input [8:0]AXI_LITE_GPIO_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 AXI_LITE_GPIO " *) output AXI_LITE_GPIO_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 AXI_LITE_GPIO " *) input AXI_LITE_GPIO_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 AXI_LITE_GPIO " *) input AXI_LITE_GPIO_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 AXI_LITE_GPIO " *) output [1:0]AXI_LITE_GPIO_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 AXI_LITE_GPIO " *) output AXI_LITE_GPIO_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 AXI_LITE_GPIO " *) output [31:0]AXI_LITE_GPIO_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 AXI_LITE_GPIO " *) input AXI_LITE_GPIO_rready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 AXI_LITE_GPIO " *) output [1:0]AXI_LITE_GPIO_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 AXI_LITE_GPIO " *) output AXI_LITE_GPIO_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 AXI_LITE_GPIO " *) input [31:0]AXI_LITE_GPIO_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 AXI_LITE_GPIO " *) output AXI_LITE_GPIO_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 AXI_LITE_GPIO " *) input [3:0]AXI_LITE_GPIO_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 AXI_LITE_GPIO " *) input AXI_LITE_GPIO_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 AXI_LITE_UART " *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME AXI_LITE_UART, ADDR_WIDTH 4, ARUSER_WIDTH 0, AWUSER_WIDTH 0, BUSER_WIDTH 0, CLK_DOMAIN PmodESP32_s_axi_aclk_0, DATA_WIDTH 32, FREQ_HZ 100000000, HAS_BRESP 1, HAS_BURST 0, HAS_CACHE 0, HAS_LOCK 0, HAS_PROT 0, HAS_QOS 0, HAS_REGION 0, HAS_RRESP 1, HAS_WSTRB 1, ID_WIDTH 0, MAX_BURST_LENGTH 1, NUM_READ_OUTSTANDING 1, NUM_READ_THREADS 1, NUM_WRITE_OUTSTANDING 1, NUM_WRITE_THREADS 1, PHASE 0.000, PROTOCOL AXI4LITE, READ_WRITE_MODE READ_WRITE, RUSER_BITS_PER_BYTE 0, RUSER_WIDTH 0, SUPPORTS_NARROW_BURST 0, WUSER_BITS_PER_BYTE 0, WUSER_WIDTH 0" *) input [3:0]AXI_LITE_UART_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 AXI_LITE_UART " *) output AXI_LITE_UART_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 AXI_LITE_UART " *) input AXI_LITE_UART_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 AXI_LITE_UART " *) input [3:0]AXI_LITE_UART_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 AXI_LITE_UART " *) output AXI_LITE_UART_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 AXI_LITE_UART " *) input AXI_LITE_UART_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 AXI_LITE_UART " *) input AXI_LITE_UART_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 AXI_LITE_UART " *) output [1:0]AXI_LITE_UART_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 AXI_LITE_UART " *) output AXI_LITE_UART_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 AXI_LITE_UART " *) output [31:0]AXI_LITE_UART_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 AXI_LITE_UART " *) input AXI_LITE_UART_rready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 AXI_LITE_UART " *) output [1:0]AXI_LITE_UART_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 AXI_LITE_UART " *) output AXI_LITE_UART_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 AXI_LITE_UART " *) input [31:0]AXI_LITE_UART_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 AXI_LITE_UART " *) output AXI_LITE_UART_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 AXI_LITE_UART " *) input [3:0]AXI_LITE_UART_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 AXI_LITE_UART " *) input AXI_LITE_UART_wvalid;
(* X_INTERFACE_INFO = "digilentinc.com:interface:pmod:1.0 Pmod_out " *) input Pmod_out_pin10_i;
(* X_INTERFACE_INFO = "digilentinc.com:interface:pmod:1.0 Pmod_out " *) output Pmod_out_pin10_o;
(* X_INTERFACE_INFO = "digilentinc.com:interface:pmod:1.0 Pmod_out " *) output Pmod_out_pin10_t;
(* X_INTERFACE_INFO = "digilentinc.com:interface:pmod:1.0 Pmod_out " *) input Pmod_out_pin1_i;
(* X_INTERFACE_INFO = "digilentinc.com:interface:pmod:1.0 Pmod_out " *) output Pmod_out_pin1_o;
(* X_INTERFACE_INFO = "digilentinc.com:interface:pmod:1.0 Pmod_out " *) output Pmod_out_pin1_t;
(* X_INTERFACE_INFO = "digilentinc.com:interface:pmod:1.0 Pmod_out " *) input Pmod_out_pin2_i;
(* X_INTERFACE_INFO = "digilentinc.com:interface:pmod:1.0 Pmod_out " *) output Pmod_out_pin2_o;
(* X_INTERFACE_INFO = "digilentinc.com:interface:pmod:1.0 Pmod_out " *) output Pmod_out_pin2_t;
(* X_INTERFACE_INFO = "digilentinc.com:interface:pmod:1.0 Pmod_out " *) input Pmod_out_pin3_i;
(* X_INTERFACE_INFO = "digilentinc.com:interface:pmod:1.0 Pmod_out " *) output Pmod_out_pin3_o;
(* X_INTERFACE_INFO = "digilentinc.com:interface:pmod:1.0 Pmod_out " *) output Pmod_out_pin3_t;
(* X_INTERFACE_INFO = "digilentinc.com:interface:pmod:1.0 Pmod_out " *) input Pmod_out_pin4_i;
(* X_INTERFACE_INFO = "digilentinc.com:interface:pmod:1.0 Pmod_out " *) output Pmod_out_pin4_o;
(* X_INTERFACE_INFO = "digilentinc.com:interface:pmod:1.0 Pmod_out " *) output Pmod_out_pin4_t;
(* X_INTERFACE_INFO = "digilentinc.com:interface:pmod:1.0 Pmod_out " *) input Pmod_out_pin7_i;
(* X_INTERFACE_INFO = "digilentinc.com:interface:pmod:1.0 Pmod_out " *) output Pmod_out_pin7_o;
(* X_INTERFACE_INFO = "digilentinc.com:interface:pmod:1.0 Pmod_out " *) output Pmod_out_pin7_t;
(* X_INTERFACE_INFO = "digilentinc.com:interface:pmod:1.0 Pmod_out " *) input Pmod_out_pin8_i;
(* X_INTERFACE_INFO = "digilentinc.com:interface:pmod:1.0 Pmod_out " *) output Pmod_out_pin8_o;
(* X_INTERFACE_INFO = "digilentinc.com:interface:pmod:1.0 Pmod_out " *) output Pmod_out_pin8_t;
(* X_INTERFACE_INFO = "digilentinc.com:interface:pmod:1.0 Pmod_out " *) input Pmod_out_pin9_i;
(* X_INTERFACE_INFO = "digilentinc.com:interface:pmod:1.0 Pmod_out " *) output Pmod_out_pin9_o;
(* X_INTERFACE_INFO = "digilentinc.com:interface:pmod:1.0 Pmod_out " *) output Pmod_out_pin9_t;
(* X_INTERFACE_INFO = "xilinx.com:signal:interrupt:1.0 INTR.GPIO_INTERRUPT INTERRUPT" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME INTR.GPIO_INTERRUPT, PortWidth 1, SENSITIVITY LEVEL_HIGH" *) output gpio_interrupt;
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLK.S_AXI_ACLK CLK" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME CLK.S_AXI_ACLK, ASSOCIATED_BUSIF AXI_LITE_GPIO:AXI_LITE_UART, ASSOCIATED_RESET s_axi_aresetn, CLK_DOMAIN PmodESP32_s_axi_aclk_0, FREQ_HZ 100000000, PHASE 0.000" *) input s_axi_aclk;
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RST.S_AXI_ARESETN RST" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME RST.S_AXI_ARESETN, POLARITY ACTIVE_LOW" *) input s_axi_aresetn;
(* X_INTERFACE_INFO = "xilinx.com:signal:interrupt:1.0 INTR.UART_INTERRUPT INTERRUPT" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME INTR.UART_INTERRUPT, PortWidth 1, SENSITIVITY EDGE_RISING" *) output uart_interrupt;
wire [3:0]S_AXI_0_1_ARADDR;
wire S_AXI_0_1_ARREADY;
wire S_AXI_0_1_ARVALID;
wire [3:0]S_AXI_0_1_AWADDR;
wire S_AXI_0_1_AWREADY;
wire S_AXI_0_1_AWVALID;
wire S_AXI_0_1_BREADY;
wire [1:0]S_AXI_0_1_BRESP;
wire S_AXI_0_1_BVALID;
wire [31:0]S_AXI_0_1_RDATA;
wire S_AXI_0_1_RREADY;
wire [1:0]S_AXI_0_1_RRESP;
wire S_AXI_0_1_RVALID;
wire [31:0]S_AXI_0_1_WDATA;
wire S_AXI_0_1_WREADY;
wire [3:0]S_AXI_0_1_WSTRB;
wire S_AXI_0_1_WVALID;
wire [8:0]S_AXI_1_1_ARADDR;
wire S_AXI_1_1_ARREADY;
wire S_AXI_1_1_ARVALID;
wire [8:0]S_AXI_1_1_AWADDR;
wire S_AXI_1_1_AWREADY;
wire S_AXI_1_1_AWVALID;
wire S_AXI_1_1_BREADY;
wire [1:0]S_AXI_1_1_BRESP;
wire S_AXI_1_1_BVALID;
wire [31:0]S_AXI_1_1_RDATA;
wire S_AXI_1_1_RREADY;
wire [1:0]S_AXI_1_1_RRESP;
wire S_AXI_1_1_RVALID;
wire [31:0]S_AXI_1_1_WDATA;
wire S_AXI_1_1_WREADY;
wire [3:0]S_AXI_1_1_WSTRB;
wire S_AXI_1_1_WVALID;
wire [3:0]axi_gpio_0_GPIO2_TRI_I;
wire [3:0]axi_gpio_0_GPIO2_TRI_O;
wire [3:0]axi_gpio_0_GPIO2_TRI_T;
wire [1:0]axi_gpio_0_GPIO_TRI_I;
wire [1:0]axi_gpio_0_GPIO_TRI_O;
wire [1:0]axi_gpio_0_GPIO_TRI_T;
wire axi_gpio_0_ip2intc_irpt;
wire axi_uartlite_0_UART_RxD;
wire axi_uartlite_0_UART_TxD;
wire axi_uartlite_0_interrupt;
wire pmod_bridge_0_Pmod_out_PIN10_I;
wire pmod_bridge_0_Pmod_out_PIN10_O;
wire pmod_bridge_0_Pmod_out_PIN10_T;
wire pmod_bridge_0_Pmod_out_PIN1_I;
wire pmod_bridge_0_Pmod_out_PIN1_O;
wire pmod_bridge_0_Pmod_out_PIN1_T;
wire pmod_bridge_0_Pmod_out_PIN2_I;
wire pmod_bridge_0_Pmod_out_PIN2_O;
wire pmod_bridge_0_Pmod_out_PIN2_T;
wire pmod_bridge_0_Pmod_out_PIN3_I;
wire pmod_bridge_0_Pmod_out_PIN3_O;
wire pmod_bridge_0_Pmod_out_PIN3_T;
wire pmod_bridge_0_Pmod_out_PIN4_I;
wire pmod_bridge_0_Pmod_out_PIN4_O;
wire pmod_bridge_0_Pmod_out_PIN4_T;
wire pmod_bridge_0_Pmod_out_PIN7_I;
wire pmod_bridge_0_Pmod_out_PIN7_O;
wire pmod_bridge_0_Pmod_out_PIN7_T;
wire pmod_bridge_0_Pmod_out_PIN8_I;
wire pmod_bridge_0_Pmod_out_PIN8_O;
wire pmod_bridge_0_Pmod_out_PIN8_T;
wire pmod_bridge_0_Pmod_out_PIN9_I;
wire pmod_bridge_0_Pmod_out_PIN9_O;
wire pmod_bridge_0_Pmod_out_PIN9_T;
wire s_axi_aclk_0_1;
wire s_axi_aresetn_0_1;
assign AXI_LITE_GPIO_arready = S_AXI_1_1_ARREADY;
assign AXI_LITE_GPIO_awready = S_AXI_1_1_AWREADY;
assign AXI_LITE_GPIO_bresp[1:0] = S_AXI_1_1_BRESP;
assign AXI_LITE_GPIO_bvalid = S_AXI_1_1_BVALID;
assign AXI_LITE_GPIO_rdata[31:0] = S_AXI_1_1_RDATA;
assign AXI_LITE_GPIO_rresp[1:0] = S_AXI_1_1_RRESP;
assign AXI_LITE_GPIO_rvalid = S_AXI_1_1_RVALID;
assign AXI_LITE_GPIO_wready = S_AXI_1_1_WREADY;
assign AXI_LITE_UART_arready = S_AXI_0_1_ARREADY;
assign AXI_LITE_UART_awready = S_AXI_0_1_AWREADY;
assign AXI_LITE_UART_bresp[1:0] = S_AXI_0_1_BRESP;
assign AXI_LITE_UART_bvalid = S_AXI_0_1_BVALID;
assign AXI_LITE_UART_rdata[31:0] = S_AXI_0_1_RDATA;
assign AXI_LITE_UART_rresp[1:0] = S_AXI_0_1_RRESP;
assign AXI_LITE_UART_rvalid = S_AXI_0_1_RVALID;
assign AXI_LITE_UART_wready = S_AXI_0_1_WREADY;
assign Pmod_out_pin10_o = pmod_bridge_0_Pmod_out_PIN10_O;
assign Pmod_out_pin10_t = pmod_bridge_0_Pmod_out_PIN10_T;
assign Pmod_out_pin1_o = pmod_bridge_0_Pmod_out_PIN1_O;
assign Pmod_out_pin1_t = pmod_bridge_0_Pmod_out_PIN1_T;
assign Pmod_out_pin2_o = pmod_bridge_0_Pmod_out_PIN2_O;
assign Pmod_out_pin2_t = pmod_bridge_0_Pmod_out_PIN2_T;
assign Pmod_out_pin3_o = pmod_bridge_0_Pmod_out_PIN3_O;
assign Pmod_out_pin3_t = pmod_bridge_0_Pmod_out_PIN3_T;
assign Pmod_out_pin4_o = pmod_bridge_0_Pmod_out_PIN4_O;
assign Pmod_out_pin4_t = pmod_bridge_0_Pmod_out_PIN4_T;
assign Pmod_out_pin7_o = pmod_bridge_0_Pmod_out_PIN7_O;
assign Pmod_out_pin7_t = pmod_bridge_0_Pmod_out_PIN7_T;
assign Pmod_out_pin8_o = pmod_bridge_0_Pmod_out_PIN8_O;
assign Pmod_out_pin8_t = pmod_bridge_0_Pmod_out_PIN8_T;
assign Pmod_out_pin9_o = pmod_bridge_0_Pmod_out_PIN9_O;
assign Pmod_out_pin9_t = pmod_bridge_0_Pmod_out_PIN9_T;
assign S_AXI_0_1_ARADDR = AXI_LITE_UART_araddr[3:0];
assign S_AXI_0_1_ARVALID = AXI_LITE_UART_arvalid;
assign S_AXI_0_1_AWADDR = AXI_LITE_UART_awaddr[3:0];
assign S_AXI_0_1_AWVALID = AXI_LITE_UART_awvalid;
assign S_AXI_0_1_BREADY = AXI_LITE_UART_bready;
assign S_AXI_0_1_RREADY = AXI_LITE_UART_rready;
assign S_AXI_0_1_WDATA = AXI_LITE_UART_wdata[31:0];
assign S_AXI_0_1_WSTRB = AXI_LITE_UART_wstrb[3:0];
assign S_AXI_0_1_WVALID = AXI_LITE_UART_wvalid;
assign S_AXI_1_1_ARADDR = AXI_LITE_GPIO_araddr[8:0];
assign S_AXI_1_1_ARVALID = AXI_LITE_GPIO_arvalid;
assign S_AXI_1_1_AWADDR = AXI_LITE_GPIO_awaddr[8:0];
assign S_AXI_1_1_AWVALID = AXI_LITE_GPIO_awvalid;
assign S_AXI_1_1_BREADY = AXI_LITE_GPIO_bready;
assign S_AXI_1_1_RREADY = AXI_LITE_GPIO_rready;
assign S_AXI_1_1_WDATA = AXI_LITE_GPIO_wdata[31:0];
assign S_AXI_1_1_WSTRB = AXI_LITE_GPIO_wstrb[3:0];
assign S_AXI_1_1_WVALID = AXI_LITE_GPIO_wvalid;
assign gpio_interrupt = axi_gpio_0_ip2intc_irpt;
assign pmod_bridge_0_Pmod_out_PIN10_I = Pmod_out_pin10_i;
assign pmod_bridge_0_Pmod_out_PIN1_I = Pmod_out_pin1_i;
assign pmod_bridge_0_Pmod_out_PIN2_I = Pmod_out_pin2_i;
assign pmod_bridge_0_Pmod_out_PIN3_I = Pmod_out_pin3_i;
assign pmod_bridge_0_Pmod_out_PIN4_I = Pmod_out_pin4_i;
assign pmod_bridge_0_Pmod_out_PIN7_I = Pmod_out_pin7_i;
assign pmod_bridge_0_Pmod_out_PIN8_I = Pmod_out_pin8_i;
assign pmod_bridge_0_Pmod_out_PIN9_I = Pmod_out_pin9_i;
assign s_axi_aclk_0_1 = s_axi_aclk;
assign s_axi_aresetn_0_1 = s_axi_aresetn;
assign uart_interrupt = axi_uartlite_0_interrupt;
PmodESP32_axi_gpio_0_0 axi_gpio_0
(.gpio2_io_i(axi_gpio_0_GPIO2_TRI_I),
.gpio2_io_o(axi_gpio_0_GPIO2_TRI_O),
.gpio2_io_t(axi_gpio_0_GPIO2_TRI_T),
.gpio_io_i(axi_gpio_0_GPIO_TRI_I),
.gpio_io_o(axi_gpio_0_GPIO_TRI_O),
.gpio_io_t(axi_gpio_0_GPIO_TRI_T),
.ip2intc_irpt(axi_gpio_0_ip2intc_irpt),
.s_axi_aclk(s_axi_aclk_0_1),
.s_axi_araddr(S_AXI_1_1_ARADDR),
.s_axi_aresetn(s_axi_aresetn_0_1),
.s_axi_arready(S_AXI_1_1_ARREADY),
.s_axi_arvalid(S_AXI_1_1_ARVALID),
.s_axi_awaddr(S_AXI_1_1_AWADDR),
.s_axi_awready(S_AXI_1_1_AWREADY),
.s_axi_awvalid(S_AXI_1_1_AWVALID),
.s_axi_bready(S_AXI_1_1_BREADY),
.s_axi_bresp(S_AXI_1_1_BRESP),
.s_axi_bvalid(S_AXI_1_1_BVALID),
.s_axi_rdata(S_AXI_1_1_RDATA),
.s_axi_rready(S_AXI_1_1_RREADY),
.s_axi_rresp(S_AXI_1_1_RRESP),
.s_axi_rvalid(S_AXI_1_1_RVALID),
.s_axi_wdata(S_AXI_1_1_WDATA),
.s_axi_wready(S_AXI_1_1_WREADY),
.s_axi_wstrb(S_AXI_1_1_WSTRB),
.s_axi_wvalid(S_AXI_1_1_WVALID));
PmodESP32_axi_uartlite_0_0 axi_uartlite_0
(.interrupt(axi_uartlite_0_interrupt),
.rx(axi_uartlite_0_UART_RxD),
.s_axi_aclk(s_axi_aclk_0_1),
.s_axi_araddr(S_AXI_0_1_ARADDR),
.s_axi_aresetn(s_axi_aresetn_0_1),
.s_axi_arready(S_AXI_0_1_ARREADY),
.s_axi_arvalid(S_AXI_0_1_ARVALID),
.s_axi_awaddr(S_AXI_0_1_AWADDR),
.s_axi_awready(S_AXI_0_1_AWREADY),
.s_axi_awvalid(S_AXI_0_1_AWVALID),
.s_axi_bready(S_AXI_0_1_BREADY),
.s_axi_bresp(S_AXI_0_1_BRESP),
.s_axi_bvalid(S_AXI_0_1_BVALID),
.s_axi_rdata(S_AXI_0_1_RDATA),
.s_axi_rready(S_AXI_0_1_RREADY),
.s_axi_rresp(S_AXI_0_1_RRESP),
.s_axi_rvalid(S_AXI_0_1_RVALID),
.s_axi_wdata(S_AXI_0_1_WDATA),
.s_axi_wready(S_AXI_0_1_WREADY),
.s_axi_wstrb(S_AXI_0_1_WSTRB),
.s_axi_wvalid(S_AXI_0_1_WVALID),
.tx(axi_uartlite_0_UART_TxD));
PmodESP32_pmod_bridge_0_0 pmod_bridge_0
(.in1_O(axi_uartlite_0_UART_TxD),
.in2_I(axi_uartlite_0_UART_RxD),
.in_bottom_bus_I(axi_gpio_0_GPIO2_TRI_I),
.in_bottom_bus_O(axi_gpio_0_GPIO2_TRI_O),
.in_bottom_bus_T(axi_gpio_0_GPIO2_TRI_T),
.in_top_uart_gpio_bus_I(axi_gpio_0_GPIO_TRI_I),
.in_top_uart_gpio_bus_O(axi_gpio_0_GPIO_TRI_O),
.in_top_uart_gpio_bus_T(axi_gpio_0_GPIO_TRI_T),
.out0_I(pmod_bridge_0_Pmod_out_PIN1_I),
.out0_O(pmod_bridge_0_Pmod_out_PIN1_O),
.out0_T(pmod_bridge_0_Pmod_out_PIN1_T),
.out1_I(pmod_bridge_0_Pmod_out_PIN2_I),
.out1_O(pmod_bridge_0_Pmod_out_PIN2_O),
.out1_T(pmod_bridge_0_Pmod_out_PIN2_T),
.out2_I(pmod_bridge_0_Pmod_out_PIN3_I),
.out2_O(pmod_bridge_0_Pmod_out_PIN3_O),
.out2_T(pmod_bridge_0_Pmod_out_PIN3_T),
.out3_I(pmod_bridge_0_Pmod_out_PIN4_I),
.out3_O(pmod_bridge_0_Pmod_out_PIN4_O),
.out3_T(pmod_bridge_0_Pmod_out_PIN4_T),
.out4_I(pmod_bridge_0_Pmod_out_PIN7_I),
.out4_O(pmod_bridge_0_Pmod_out_PIN7_O),
.out4_T(pmod_bridge_0_Pmod_out_PIN7_T),
.out5_I(pmod_bridge_0_Pmod_out_PIN8_I),
.out5_O(pmod_bridge_0_Pmod_out_PIN8_O),
.out5_T(pmod_bridge_0_Pmod_out_PIN8_T),
.out6_I(pmod_bridge_0_Pmod_out_PIN9_I),
.out6_O(pmod_bridge_0_Pmod_out_PIN9_O),
.out6_T(pmod_bridge_0_Pmod_out_PIN9_T),
.out7_I(pmod_bridge_0_Pmod_out_PIN10_I),
.out7_O(pmod_bridge_0_Pmod_out_PIN10_O),
.out7_T(pmod_bridge_0_Pmod_out_PIN10_T));
endmodule
|
module jt10_adpcmb_gain(
input rst_n,
input clk, // CPU clock
input cen55,
input [ 7:0] tl, // ADPCM Total Level
input signed [15:0] pcm_in,
output reg signed [15:0] pcm_out
);
wire signed [15:0] factor = {8'd0, tl};
wire signed [31:0] pcm_mul = pcm_in * factor; // linear gain
always @(posedge clk) if(cen55)
pcm_out <= pcm_mul[23:8];
endmodule
|
module sky130_fd_sc_ms__o311a_1 (
X ,
A1 ,
A2 ,
A3 ,
B1 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ms__o311a base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.C1(C1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
|
module sky130_fd_sc_ms__o311a_1 (
X ,
A1,
A2,
A3,
B1,
C1
);
output X ;
input A1;
input A2;
input A3;
input B1;
input C1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__o311a base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.C1(C1)
);
endmodule
|
module priority_encoder #
(
parameter WIDTH = 4,
// LSB priority: "LOW", "HIGH"
parameter LSB_PRIORITY = "LOW"
)
(
input wire [WIDTH-1:0] input_unencoded,
output wire output_valid,
output wire [$clog2(WIDTH)-1:0] output_encoded,
output wire [WIDTH-1:0] output_unencoded
);
// power-of-two width
parameter W1 = 2**$clog2(WIDTH);
parameter W2 = W1/2;
generate
if (WIDTH == 1) begin
// one input
assign output_valid = input_unencoded;
assign output_encoded = 0;
end else if (WIDTH == 2) begin
// two inputs - just an OR gate
assign output_valid = |input_unencoded;
if (LSB_PRIORITY == "LOW") begin
assign output_encoded = input_unencoded[1];
end else begin
assign output_encoded = ~input_unencoded[0];
end
end else begin
// more than two inputs - split into two parts and recurse
// also pad input to correct power-of-two width
wire [$clog2(W2)-1:0] out1, out2;
wire valid1, valid2;
priority_encoder #(
.WIDTH(W2),
.LSB_PRIORITY(LSB_PRIORITY)
)
priority_encoder_inst1 (
.input_unencoded(input_unencoded[W2-1:0]),
.output_valid(valid1),
.output_encoded(out1)
);
priority_encoder #(
.WIDTH(W2),
.LSB_PRIORITY(LSB_PRIORITY)
)
priority_encoder_inst2 (
.input_unencoded({{W1-WIDTH{1'b0}}, input_unencoded[WIDTH-1:W2]}),
.output_valid(valid2),
.output_encoded(out2)
);
// multiplexer to select part
assign output_valid = valid1 | valid2;
if (LSB_PRIORITY == "LOW") begin
assign output_encoded = valid2 ? {1'b1, out2} : {1'b0, out1};
end else begin
assign output_encoded = valid1 ? {1'b0, out1} : {1'b1, out2};
end
end
endgenerate
// unencoded output
assign output_unencoded = 1 << output_encoded;
endmodule
|
module sky130_fd_sc_hs__a211oi (
Y ,
A1 ,
A2 ,
B1 ,
C1 ,
VPWR,
VGND
);
// Module ports
output Y ;
input A1 ;
input A2 ;
input B1 ;
input C1 ;
input VPWR;
input VGND;
// Local signals
wire C1 and0_out ;
wire nor0_out_Y ;
wire u_vpwr_vgnd0_out_Y;
// Name Output Other arguments
and and0 (and0_out , A1, A2 );
nor nor0 (nor0_out_Y , and0_out, B1, C1 );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_Y, nor0_out_Y, VPWR, VGND);
buf buf0 (Y , u_vpwr_vgnd0_out_Y );
endmodule
|
module limbus_cpu_oci_test_bench (
// inputs:
dct_buffer,
dct_count,
test_ending,
test_has_ended
)
;
input [ 29: 0] dct_buffer;
input [ 3: 0] dct_count;
input test_ending;
input test_has_ended;
endmodule
|
module soc_design_SystemID (
// inputs:
address,
clock,
reset_n,
// outputs:
readdata
)
;
output [ 31: 0] readdata;
input address;
input clock;
input reset_n;
wire [ 31: 0] readdata;
//control_slave, which is an e_avalon_slave
assign readdata = address ? 1500009189 : 255;
endmodule
|
module TX_control
#( parameter INTER_BYTE_DELAY = 1000000, // ciclos de reloj de espera entre el envio de 2 bytes consecutivos
parameter WAIT_FOR_REGISTER_DELAY = 100 // tiempo de espera para iniciar la transmision luego de registrar el dato a enviar
)(
input clock,
input reset,
input PB, // Push Button
input send16, // Indica si se deben enviar 8 o 16 bits
input [15:0] dataIn16, // Dato que se desea transmitir de 16 bits
output reg [7:0] tx_data, // Datos entregados al driver UART para transmision
output reg tx_start, // Pulso para iniciar transmision por la UART
output reg busy // Indica si hay una transmision en proceso
);
reg [2:0] next_state, state;
reg [15:0] tx_data16;
reg [31:0] hold_state_timer;
//state encoding
localparam IDLE = 3'd0; // Modo espera
localparam REGISTER_DATAIN16 = 3'd1; // Cuando se presiona boton, registrar 16 bits a enviar
localparam SEND_BYTE_0 = 3'd2; // Enviar el primer byte
localparam DELAY_BYTE_0 = 3'd3; // Esperar un tiempo suficiente para que la transmision anterior termine
localparam SEND_BYTE_1 = 3'd4; // Si es necesario, enviar el segundo byte
localparam DELAY_BYTE_1 = 3'd5; // Esperar a que la transmision anterior termine
// combo logic of FSM
always@(*) begin
//default assignments
next_state = state;
busy = 1'b1;
tx_start = 1'b0;
tx_data = tx_data16[7:0];
case (state)
IDLE: begin
busy = 1'b0;
if(PB) begin
next_state=REGISTER_DATAIN16;
end
end
REGISTER_DATAIN16: begin
if(hold_state_timer >= WAIT_FOR_REGISTER_DELAY)
next_state=SEND_BYTE_0;
end
SEND_BYTE_0: begin
next_state = DELAY_BYTE_0;
tx_start = 1'b1;
end
DELAY_BYTE_0: begin
//tx_data = tx_data16[15:8];
if(hold_state_timer >= INTER_BYTE_DELAY) begin
if (send16)
next_state = SEND_BYTE_1;
else
next_state = IDLE;
end
end
SEND_BYTE_1: begin
tx_data = tx_data16[15:8];
next_state = DELAY_BYTE_1;
tx_start = 1'b1;
end
DELAY_BYTE_1: begin
if(hold_state_timer >= INTER_BYTE_DELAY)
next_state = IDLE;
end
endcase
end
//when clock ticks, update the state
always@(posedge clock) begin
if(reset)
state <= IDLE;
else
state <= next_state;
end
// registra los datos a enviar
always@ (posedge clock) begin
if(state == REGISTER_DATAIN16)
tx_data16 <= dataIn16;
end
//activa timer para retener un estado por cierto numero de ciclos de reloj
always@(posedge clock) begin
if(state == DELAY_BYTE_0 || state == DELAY_BYTE_1 || state == REGISTER_DATAIN16) begin
hold_state_timer <= hold_state_timer + 1;
end else begin
hold_state_timer <= 0;
end
end
endmodule
|
module will perform one shift per input
data bit, so if the input data bus is not required tie data_in to zero and set DATA_WIDTH
to the required number of shifts per clock cycle.
STYLE
Specify implementation style. Can be "AUTO", "LOOP", or "REDUCTION". When "AUTO"
is selected, implemenation will be "LOOP" or "REDUCTION" based on synthesis translate
directives. "REDUCTION" and "LOOP" are functionally identical, however they simulate
and synthesize differently. "REDUCTION" is implemented with a loop over a Verilog
reduction operator. "LOOP" is implemented as a doubly-nested loop with no reduction
operator. "REDUCTION" is very fast for simulation in iverilog and synthesizes well in
Quartus but synthesizes poorly in ISE, likely due to large inferred XOR gates causing
problems with the optimizer. "LOOP" synthesizes will in both ISE and Quartus. "AUTO"
will default to "REDUCTION" when simulating and "LOOP" for synthesizers that obey
synthesis translate directives.
Settings for common LFSR/CRC implementations:
Name Configuration Length Polynomial Initial value Notes
CRC16-IBM Galois, bit-reverse 16 16'h8005 16'hffff
CRC16-CCITT Galois 16 16'h1021 16'h1d0f
CRC32 Galois, bit-reverse 32 32'h04c11db7 32'hffffffff Ethernet FCS; invert final output
PRBS6 Fibonacci 6 6'h21 any
PRBS7 Fibonacci 7 7'h41 any
PRBS9 Fibonacci 9 9'h021 any ITU V.52
PRBS10 Fibonacci 10 10'h081 any ITU
PRBS11 Fibonacci 11 11'h201 any ITU O.152
PRBS15 Fibonacci, inverted 15 15'h4001 any ITU O.152
PRBS17 Fibonacci 17 17'h04001 any
PRBS20 Fibonacci 20 20'h00009 any ITU V.57
PRBS23 Fibonacci, inverted 23 23'h040001 any ITU O.151
PRBS29 Fibonacci, inverted 29 29'h08000001 any
PRBS31 Fibonacci, inverted 31 31'h10000001 any
64b66b Fibonacci, bit-reverse 58 58'h8000000001 any 10G Ethernet
128b130b Galois, bit-reverse 23 23'h210125 any PCIe gen 3
*/
reg [LFSR_WIDTH-1:0] lfsr_mask_state[LFSR_WIDTH-1:0];
reg [DATA_WIDTH-1:0] lfsr_mask_data[LFSR_WIDTH-1:0];
reg [LFSR_WIDTH-1:0] output_mask_state[DATA_WIDTH-1:0];
reg [DATA_WIDTH-1:0] output_mask_data[DATA_WIDTH-1:0];
reg [LFSR_WIDTH-1:0] state_val = 0;
reg [DATA_WIDTH-1:0] data_val = 0;
integer i, j, k;
initial begin
// init bit masks
for (i = 0; i < LFSR_WIDTH; i = i + 1) begin
lfsr_mask_state[i] = {LFSR_WIDTH{1'b0}};
lfsr_mask_state[i][i] = 1'b1;
lfsr_mask_data[i] = {DATA_WIDTH{1'b0}};
end
for (i = 0; i < DATA_WIDTH; i = i + 1) begin
output_mask_state[i] = {LFSR_WIDTH{1'b0}};
if (i < LFSR_WIDTH) begin
output_mask_state[i][i] = 1'b1;
end
output_mask_data[i] = {DATA_WIDTH{1'b0}};
end
// simulate shift register
if (LFSR_CONFIG == "FIBONACCI") begin
// Fibonacci configuration
for (i = DATA_WIDTH-1; i >= 0; i = i - 1) begin
// determine shift in value
// current value in last FF, XOR with input data bit (MSB first)
state_val = lfsr_mask_state[LFSR_WIDTH-1];
data_val = lfsr_mask_data[LFSR_WIDTH-1];
data_val = data_val ^ (1 << i);
// add XOR inputs from correct indicies
for (j = 1; j < LFSR_WIDTH; j = j + 1) begin
if (LFSR_POLY & (1 << j)) begin
state_val = lfsr_mask_state[j-1] ^ state_val;
data_val = lfsr_mask_data[j-1] ^ data_val;
end
end
// shift
for (j = LFSR_WIDTH-1; j > 0; j = j - 1) begin
lfsr_mask_state[j] = lfsr_mask_state[j-1];
lfsr_mask_data[j] = lfsr_mask_data[j-1];
end
for (j = DATA_WIDTH-1; j > 0; j = j - 1) begin
output_mask_state[j] = output_mask_state[j-1];
output_mask_data[j] = output_mask_data[j-1];
end
output_mask_state[0] = state_val;
output_mask_data[0] = data_val;
if (LFSR_FEED_FORWARD) begin
// only shift in new input data
state_val = {LFSR_WIDTH{1'b0}};
data_val = 1 << i;
end
lfsr_mask_state[0] = state_val;
lfsr_mask_data[0] = data_val;
end
end else if (LFSR_CONFIG == "GALOIS") begin
// Galois configuration
for (i = DATA_WIDTH-1; i >= 0; i = i - 1) begin
// determine shift in value
// current value in last FF, XOR with input data bit (MSB first)
state_val = lfsr_mask_state[LFSR_WIDTH-1];
data_val = lfsr_mask_data[LFSR_WIDTH-1];
data_val = data_val ^ (1 << i);
// shift
for (j = LFSR_WIDTH-1; j > 0; j = j - 1) begin
lfsr_mask_state[j] = lfsr_mask_state[j-1];
lfsr_mask_data[j] = lfsr_mask_data[j-1];
end
for (j = DATA_WIDTH-1; j > 0; j = j - 1) begin
output_mask_state[j] = output_mask_state[j-1];
output_mask_data[j] = output_mask_data[j-1];
end
output_mask_state[0] = state_val;
output_mask_data[0] = data_val;
if (LFSR_FEED_FORWARD) begin
// only shift in new input data
state_val = {LFSR_WIDTH{1'b0}};
data_val = 1 << i;
end
lfsr_mask_state[0] = state_val;
lfsr_mask_data[0] = data_val;
// add XOR inputs at correct indicies
for (j = 1; j < LFSR_WIDTH; j = j + 1) begin
if (LFSR_POLY & (1 << j)) begin
lfsr_mask_state[j] = lfsr_mask_state[j] ^ state_val;
lfsr_mask_data[j] = lfsr_mask_data[j] ^ data_val;
end
end
end
end else begin
$error("Error: unknown configuration setting!");
$finish;
end
// reverse bits if selected
if (REVERSE) begin
// reverse order
for (i = 0; i < LFSR_WIDTH/2; i = i + 1) begin
state_val = lfsr_mask_state[i];
data_val = lfsr_mask_data[i];
lfsr_mask_state[i] = lfsr_mask_state[LFSR_WIDTH-i-1];
lfsr_mask_data[i] = lfsr_mask_data[LFSR_WIDTH-i-1];
lfsr_mask_state[LFSR_WIDTH-i-1] = state_val;
lfsr_mask_data[LFSR_WIDTH-i-1] = data_val;
end
for (i = 0; i < DATA_WIDTH/2; i = i + 1) begin
state_val = output_mask_state[i];
data_val = output_mask_data[i];
output_mask_state[i] = output_mask_state[DATA_WIDTH-i-1];
output_mask_data[i] = output_mask_data[DATA_WIDTH-i-1];
output_mask_state[DATA_WIDTH-i-1] = state_val;
output_mask_data[DATA_WIDTH-i-1] = data_val;
end
// reverse bits
for (i = 0; i < LFSR_WIDTH; i = i + 1) begin
state_val = 0;
for (j = 0; j < LFSR_WIDTH; j = j + 1) begin
state_val[j] = lfsr_mask_state[i][LFSR_WIDTH-j-1];
end
lfsr_mask_state[i] = state_val;
data_val = 0;
for (j = 0; j < DATA_WIDTH; j = j + 1) begin
data_val[j] = lfsr_mask_data[i][DATA_WIDTH-j-1];
end
lfsr_mask_data[i] = data_val;
end
for (i = 0; i < DATA_WIDTH; i = i + 1) begin
state_val = 0;
for (j = 0; j < LFSR_WIDTH; j = j + 1) begin
state_val[j] = output_mask_state[i][LFSR_WIDTH-j-1];
end
output_mask_state[i] = state_val;
data_val = 0;
for (j = 0; j < DATA_WIDTH; j = j + 1) begin
data_val[j] = output_mask_data[i][DATA_WIDTH-j-1];
end
output_mask_data[i] = data_val;
end
end
// for (i = 0; i < LFSR_WIDTH; i = i + 1) begin
// $display("%b %b", lfsr_mask_state[i], lfsr_mask_data[i]);
// end
end
// synthesis translate_off
`define SIMULATION
// synthesis translate_on
`ifdef SIMULATION
// "AUTO" style is "REDUCTION" for faster simulation
parameter STYLE_INT = (STYLE == "AUTO") ? "REDUCTION" : STYLE;
`else
// "AUTO" style is "LOOP" for better synthesis result
parameter STYLE_INT = (STYLE == "AUTO") ? "LOOP" : STYLE;
`endif
genvar n;
generate
if (STYLE_INT == "REDUCTION") begin
// use Verilog reduction operator
// fast in iverilog
// significantly larger than generated code with ISE (inferred wide XORs may be tripping up optimizer)
// slightly smaller than generated code with Quartus
// --> better for simulation
for (n = 0; n < LFSR_WIDTH; n = n + 1) begin : loop1
assign state_out[n] = ^{(state_in & lfsr_mask_state[n]), (data_in & lfsr_mask_data[n])};
end
for (n = 0; n < DATA_WIDTH; n = n + 1) begin : loop2
assign data_out[n] = ^{(state_in & output_mask_state[n]), (data_in & output_mask_data[n])};
end
end else if (STYLE_INT == "LOOP") begin
// use nested loops
// very slow in iverilog
// slightly smaller than generated code with ISE
// same size as generated code with Quartus
// --> better for synthesis
reg [LFSR_WIDTH-1:0] state_out_reg = 0;
reg [DATA_WIDTH-1:0] data_out_reg = 0;
assign state_out = state_out_reg;
assign data_out = data_out_reg;
always @* begin
for (i = 0; i < LFSR_WIDTH; i = i + 1) begin
state_out_reg[i] = 0;
for (j = 0; j < LFSR_WIDTH; j = j + 1) begin
if (lfsr_mask_state[i][j]) begin
state_out_reg[i] = state_out_reg[i] ^ state_in[j];
end
end
for (j = 0; j < DATA_WIDTH; j = j + 1) begin
if (lfsr_mask_data[i][j]) begin
state_out_reg[i] = state_out_reg[i] ^ data_in[j];
end
end
end
for (i = 0; i < DATA_WIDTH; i = i + 1) begin
data_out_reg[i] = 0;
for (j = 0; j < LFSR_WIDTH; j = j + 1) begin
if (output_mask_state[i][j]) begin
data_out_reg[i] = data_out_reg[i] ^ state_in[j];
end
end
for (j = 0; j < DATA_WIDTH; j = j + 1) begin
if (output_mask_data[i][j]) begin
data_out_reg[i] = data_out_reg[i] ^ data_in[j];
end
end
end
end
end else begin
initial begin
$error("Error: unknown style setting!");
$finish;
end
end
endgenerate
endmodule
|
module addsub(/*AUTOARG*/
// Outputs
data_c,overflow,
// Inputs
data_a, data_b, sign, addsub
);
// input clk;
input [31:0] data_a;
input [31:0] data_b;
//input [31:0] data_c;
input sign;
input addsub;
output overflow;
reg [32:0] temp;
output reg [31:0] data_c;
always @(/*AUTOSENSE*/addsub or data_a or data_b or sign) begin
case ({addsub, sign})
00:
temp <= {data_a[31], data_a} + {data_b[31], data_b};
01:
temp[31:0] <= data_a + data_b;
10:
temp <= {data_b[31], data_b} - {data_a[31], data_a};
11:
temp[31:0] <= data_b - data_a;
default:
data_c <= 32'h00000000;
endcase // case ({add_sub, sign})
data_c <= temp[31:0];
end
assign overflow = temp[32] != temp[31];
endmodule
|
module
input [5:0] A;
input [7:0] Din;
output [7:0] Dout;
input [2:0] CS_n;
input CS;
input R_W_n;
output RDY;
input MASTERCLK;
input CLK2;
input [1:0] Ilatch;
input [3:0] idump_in;
output HSYNC, HBLANK;
output VSYNC, VBLANK;
output [7:0] COLOROUT;
input RES_n;
output AUD0, AUD1;
output reg [3:0] audv0, audv1;
// Data output register
reg [7:0] Dout;
// Video control signal registers
wire HSYNC;
reg VSYNC, VBLANK;
// Horizontal pixel counter
reg [7:0] hCount;
reg [3:0] hCountReset;
reg clk_30;
reg [7:0] clk_30_count;
wire [3:0] Idump;
// Pixel counter update
always @(posedge MASTERCLK)
begin
// Reset operation
if (~RES_n) begin
hCount <= 8'd0;
hCountReset[3:1] <= 3'd0;
clk_30 <= 0;
clk_30_count <= 0;
latchedInputs <= 2'b11;
end
else begin
if (inputLatchReset)
latchedInputs <= 2'b11;
else
latchedInputs <= latchedInputs & Ilatch;
if (clk_30_count == 57) begin
clk_30 <= ~clk_30;
clk_30_count <= 0;
end else begin
clk_30_count <= clk_30_count + 1;
end
// Increment the count and reset if necessary
if ((hCountReset[3]) ||(hCount == 8'd227))
hCount <= 8'd0;
else
hCount <= hCount + 8'd1;
// Software resets are delayed by three cycles
hCountReset[3:1] <= hCountReset[2:0];
end
end
assign HSYNC = (hCount >= 8'd20) && (hCount < 8'd36);
assign HBLANK = (hCount < 8'd68);
// Screen object registers
// These registers are set by the software and used to generate pixels
reg [7:0] player0Pos, player1Pos, missile0Pos, missile1Pos, ballPos;
reg [4:0] player0Size, player1Size;
reg [7:0] player0Color, player1Color, ballColor, pfColor, bgColor;
reg [3:0] player0Motion, player1Motion, missile0Motion, missile1Motion,
ballMotion;
reg missile0Enable, missile1Enable, ballEnable, R_ballEnable;
reg [1:0] ballSize;
reg [19:0] pfGraphic;
reg [7:0] player0Graphic, player1Graphic;
reg [7:0] R_player0Graphic, R_player1Graphic;
reg pfReflect, player0Reflect, player1Reflect;
reg prioCtrl;
reg pfColorCtrl;
reg [14:0] collisionLatch;
reg missile0Lock, missile1Lock;
reg player0VertDelay, player1VertDelay, ballVertDelay;
reg [3:0] audc0, audc1;
reg [4:0] audf0, audf1;
// Pixel number calculation
wire [7:0] pixelNum;
//audio control
audio audio_ctrl(.AUDC0(audc0),
.AUDC1(audc1),
.AUDF0(audf0),
.AUDF1(audf1),
.CLK_30(clk_30), //30khz clock
.AUD0(AUD0),
.AUD1(AUD1));
assign pixelNum = (hCount >= 8'd68) ? (hCount - 8'd68) : 8'd227;
// Pixel tests. For each pixel and screen object, a test is done based on the
// screen objects register to determine if the screen object should show on that
// pixel. The results of all the tests are fed into logic to pick which displayed
// object has priority and color the pixel the color of that object.
// Playfield pixel test
wire [5:0] pfPixelNum;
wire pfPixelOn, pfLeftPixelVal, pfRightPixelVal;
assign pfPixelNum = pixelNum[7:2];
assign pfLeftPixelVal = pfGraphic[pfPixelNum];
assign pfRightPixelVal = (pfReflect == 1'b0)? pfGraphic[pfPixelNum - 6'd20]:
pfGraphic[6'd39 - pfPixelNum];
assign pfPixelOn = (pfPixelNum < 6'd20)? pfLeftPixelVal : pfRightPixelVal;
// Player 0 sprite pixel test
wire pl0PixelOn;
wire [7:0] pl0Mask, pl0MaskDel;
assign pl0MaskDel = (player0VertDelay)? R_player0Graphic : player0Graphic;
assign pl0Mask = (!player0Reflect)? pl0MaskDel : {pl0MaskDel[0], pl0MaskDel[1],
pl0MaskDel[2], pl0MaskDel[3],
pl0MaskDel[4], pl0MaskDel[5],
pl0MaskDel[6], pl0MaskDel[7]};
objPixelOn player0_test(pixelNum, player0Pos, player0Size[2:0], pl0Mask, pl0PixelOn);
// Player 1 sprite pixel test
wire pl1PixelOn;
wire [7:0] pl1Mask, pl1MaskDel;
assign pl1MaskDel = (player1VertDelay)? R_player1Graphic : player1Graphic;
assign pl1Mask = (!player1Reflect)? pl1MaskDel : {pl1MaskDel[0], pl1MaskDel[1],
pl1MaskDel[2], pl1MaskDel[3],
pl1MaskDel[4], pl1MaskDel[5],
pl1MaskDel[6], pl1MaskDel[7]};
objPixelOn player1_test(pixelNum, player1Pos, player1Size[2:0], pl1Mask, pl1PixelOn);
// Missile 0 pixel test
wire mis0PixelOn, mis0PixelOut;
wire [7:0] mis0ActualPos;
reg [7:0] mis0Mask;
always @(player0Size)
begin
case(player0Size[4:3])
2'd0: mis0Mask <= 8'h01;
2'd1: mis0Mask <= 8'h03;
2'd2: mis0Mask <= 8'h0F;
2'd3: mis0Mask <= 8'hFF;
endcase
end
assign mis0ActualPos = (missile0Lock)? player0Pos : missile0Pos;
objPixelOn missile0_test(pixelNum, mis0ActualPos, player0Size[2:0], mis0Mask, mis0PixelOut);
assign mis0PixelOn = mis0PixelOut && missile0Enable;
// Missile 1 pixel test
wire mis1PixelOn, mis1PixelOut;
wire [7:0] mis1ActualPos;
reg [7:0] mis1Mask;
always @(player1Size)
begin
case(player1Size[4:3])
2'd0: mis1Mask <= 8'h01;
2'd1: mis1Mask <= 8'h03;
2'd2: mis1Mask <= 8'h0F;
2'd3: mis1Mask <= 8'hFF;
endcase
end
assign mis1ActualPos = (missile1Lock)? player1Pos : missile1Pos;
objPixelOn missile1_test(pixelNum, mis1ActualPos, player1Size[2:0], mis1Mask, mis1PixelOut);
assign mis1PixelOn = mis1PixelOut && missile1Enable;
// Ball pixel test
wire ballPixelOut, ballPixelOn, ballEnableDel;
reg [7:0] ballMask;
always @(ballSize)
begin
case(ballSize)
2'd0: ballMask <= 8'h01;
2'd1: ballMask <= 8'h03;
2'd2: ballMask <= 8'h0F;
2'd3: ballMask <= 8'hFF;
endcase
end
objPixelOn ball_test(pixelNum, ballPos, 3'd0, ballMask, ballPixelOut);
assign ballEnableDel = ((ballVertDelay)? R_ballEnable : ballEnable);
assign ballPixelOn = ballPixelOut && ballEnableDel;
// Playfield color selection
// The programmer can select a unique color for the playfield or have it match
// the player's sprites colors
reg [7:0] pfActualColor;
always @(pfColorCtrl, pfColor, player0Color, player1Color, pfPixelNum)
begin
if (pfColorCtrl)
begin
if (pfPixelNum < 6'd20)
pfActualColor <= player0Color;
else
pfActualColor <= player1Color;
end
else
pfActualColor <= pfColor;
end
// Final pixel color selection
reg [7:0] pixelColor;
assign COLOROUT = (HBLANK)? 8'b0 : pixelColor;
// This combinational logic uses a priority encoder like structure to select
// the highest priority screen object and color the pixel.
always @(prioCtrl, pfPixelOn, pl0PixelOn, pl1PixelOn, mis0PixelOn, mis1PixelOn,
ballPixelOn, pfActualColor, player0Color, player1Color, bgColor)
begin
// Show the playfield behind the players
if (!prioCtrl)
begin
if (pl0PixelOn || mis0PixelOn)
pixelColor <= player0Color;
else if (pl1PixelOn || mis1PixelOn)
pixelColor <= player1Color;
else if (pfPixelOn)
pixelColor <= pfActualColor;
else
pixelColor <= bgColor;
end
// Otherwise, show the playfield in front of the players
else begin
if (pfPixelOn)
pixelColor <= pfActualColor;
else if (pl0PixelOn || mis0PixelOn)
pixelColor <= player0Color;
else if (pl1PixelOn || mis1PixelOn)
pixelColor <= player1Color;
else
pixelColor <= bgColor;
end
end
// Collision register and latching update
wire [14:0] collisions;
reg collisionLatchReset;
assign collisions = {pl0PixelOn && pl1PixelOn, mis0PixelOn && mis1PixelOn,
ballPixelOn && pfPixelOn,
mis1PixelOn && pfPixelOn, mis1PixelOn && ballPixelOn,
mis0PixelOn && pfPixelOn, mis0PixelOn && ballPixelOn,
pl1PixelOn && pfPixelOn, pl1PixelOn && ballPixelOn,
pl0PixelOn && pfPixelOn, pl0PixelOn && ballPixelOn,
mis1PixelOn && pl0PixelOn, mis1PixelOn && pl1PixelOn,
mis0PixelOn && pl1PixelOn, mis0PixelOn && pl0PixelOn};
always @(posedge MASTERCLK, posedge collisionLatchReset)
begin
if (collisionLatchReset)
collisionLatch <= 15'b000000000000000;
else
collisionLatch <= collisionLatch | collisions;
end
// WSYNC logic
// When a WSYNC is signalled by the programmer, the CPU ready line is lowered
// until the end of a scanline
reg wSync, wSyncReset;
always @(hCount, wSyncReset)
begin
if (hCount == 8'd0)
wSync <= 1'b0;
else if (wSyncReset && hCount > 8'd2)
wSync <= 1'b1;
end
assign RDY = ~wSync;
// Latched input registers and update
wire [1:0] latchedInputsValue;
reg inputLatchEnabled;
reg inputLatchReset;
reg [1:0] latchedInputs;
/*always_ff @(Ilatch, inputLatchReset)
begin
if (inputLatchReset)
latchedInputs <= 2'b11;
else
latchedInputs <= latchedInputs & Ilatch;
end*/
assign latchedInputsValue = (inputLatchEnabled)? latchedInputs : Ilatch;
// Dumped input registers update
reg inputDumpEnabled;
assign Idump = (inputDumpEnabled)? 4'b0000 : idump_in;
// Software operations
always @(posedge CLK2)
begin
// Reset operation
if (~RES_n) begin
inputLatchReset <= 1'b0;
collisionLatchReset <= 1'b0;
hCountReset[0] <= 1'b0;
wSyncReset <= 1'b0;
Dout <= 8'b00000000;
end
// If the chip is enabled, execute an operation
else if (CS) begin
// Software reset signals
inputLatchReset <= ({R_W_n, A[5:0]} == `VBLANK && Din[6] && !inputLatchEnabled);
collisionLatchReset <= ({R_W_n, A[5:0]} == `CXCLR);
hCountReset[0] <= ({R_W_n, A[5:0]} == `RSYNC);
wSyncReset <= ({R_W_n, A[5:0]} == `WSYNC) && !wSync;
case({R_W_n, A[5:0]})
// Collision latch reads
`CXM0P, `CXM0P_7800: Dout <= {collisionLatch[1:0],6'b000000};
`CXM1P, `CXM1P_7800: Dout <= {collisionLatch[3:2],6'b000000};
`CXP0FB, `CXP0FB_7800: Dout <= {collisionLatch[5:4],6'b000000};
`CXP1FB, `CXP1FB_7800: Dout <= {collisionLatch[7:6],6'b000000};
`CXM0FB, `CXM0FB_7800: Dout <= {collisionLatch[9:8],6'b000000};
`CXM1FB, `CXM1FB_7800: Dout <= {collisionLatch[11:10],6'b000000};
`CXBLPF, `CXBLPF_7800: Dout <= {collisionLatch[12],7'b0000000};
`CXPPMM, `CXPPMM_7800: Dout <= {collisionLatch[14:13],6'b000000};
// I/O reads
`INPT0, `INPT0_7800: Dout <= {Idump[0], 7'b0000000};
`INPT1, `INPT1_7800: Dout <= {Idump[1], 7'b0000000};
`INPT2, `INPT2_7800: Dout <= {Idump[2], 7'b0000000};
`INPT3, `INPT3_7800: Dout <= {Idump[3], 7'b0000000};
`INPT4, `INPT4_7800: Dout <= {latchedInputsValue[0], 7'b0000000};
`INPT5, `INPT5_7800: Dout <= {latchedInputsValue[1], 7'b0000000};
// Video signals
`VSYNC: VSYNC <= Din[1];
`VBLANK: begin
inputLatchEnabled <= Din[6];
inputDumpEnabled <= Din[7];
VBLANK <= Din[1];
end
`WSYNC:;
`RSYNC:;
// Screen object register access
`NUSIZ0: player0Size <= {Din[5:4],Din[2:0]};
`NUSIZ1: player1Size <= {Din[5:4],Din[2:0]};
`COLUP0: player0Color <= Din;
`COLUP1: player1Color <= Din;
`COLUPF: pfColor <= Din;
`COLUBK: bgColor <= Din;
`CTRLPF: begin
pfReflect <= Din[0];
pfColorCtrl <= Din[1];
prioCtrl <= Din[2];
ballSize <= Din[5:4];
end
`REFP0: player0Reflect <= Din[3];
`REFP1: player1Reflect <= Din[3];
`PF0: pfGraphic[3:0] <= Din[7:4];
`PF1: pfGraphic[11:4] <= {Din[0], Din[1], Din[2], Din[3],
Din[4], Din[5], Din[6], Din[7]};
`PF2: pfGraphic[19:12] <= Din[7:0];
`RESP0: player0Pos <= pixelNum;
`RESP1: player1Pos <= pixelNum;
`RESM0: missile0Pos <= pixelNum;
`RESM1: missile1Pos <= pixelNum;
`RESBL: ballPos <= pixelNum;
// Audio controls
`AUDC0: audc0 <= Din[3:0];
`AUDC1: audc1 <= Din[3:0];
`AUDF0: audf0 <= Din[4:0];
`AUDF1: audf1 <= Din[4:0];
`AUDV0: audv0 <= Din[3:0];
`AUDV1: audv1 <= Din[3:0];
// Screen object register access
`GRP0: begin
player0Graphic <= {Din[0], Din[1], Din[2], Din[3],
Din[4], Din[5], Din[6], Din[7]};
R_player1Graphic <= player1Graphic;
end
`GRP1: begin
player1Graphic <= {Din[0], Din[1], Din[2], Din[3],
Din[4], Din[5], Din[6], Din[7]};
R_player0Graphic <= player0Graphic;
R_ballEnable <= ballEnable;
end
`ENAM0: missile0Enable <= Din[1];
`ENAM1: missile1Enable <= Din[1];
`ENABL: ballEnable <= Din[1];
`HMP0: player0Motion <= Din[7:4];
`HMP1: player1Motion <= Din[7:4];
`HMM0: missile0Motion <= Din[7:4];
`HMM1: missile1Motion <= Din[7:4];
`HMBL: ballMotion <= Din[7:4];
`VDELP0: player0VertDelay <= Din[0];
`VDELP1: player1VertDelay <= Din[0];
`VDELBL: ballVertDelay <= Din[0];
`RESMP0: missile0Lock <= Din[1];
`RESMP1: missile1Lock <= Din[1];
// Strobed line that initiates an object move
`HMOVE: begin
player0Pos <= player0Pos - {{4{player0Motion[3]}},
player0Motion[3:0]};
player1Pos <= player1Pos - {{4{player1Motion[3]}},
player1Motion[3:0]};
missile0Pos <= missile0Pos - {{4{missile0Motion[3]}},
missile0Motion[3:0]};
missile1Pos <= missile1Pos - {{4{missile1Motion[3]}},
missile1Motion[3:0]};
ballPos <= ballPos - {{4{ballMotion[3]}},ballMotion[3:0]};
end
// Motion register clear
`HMCLR: begin
player0Motion <= Din[7:4];
player1Motion <= Din[7:4];
missile0Motion <= Din[7:4];
missile1Motion <= Din[7:4];
ballMotion <= Din[7:4];
end
`CXCLR:;
default: Dout <= 8'b00000000;
endcase
end
// If the chip is not enabled, do nothing
else begin
inputLatchReset <= 1'b0;
collisionLatchReset <= 1'b0;
hCountReset[0] <= 1'b0;
wSyncReset <= 1'b0;
Dout <= 8'b00000000;
end
end
endmodule
|
module objPixelOn(pixelNum, objPos, objSize, objMask, pixelOn);
input [7:0] pixelNum, objPos, objMask;
input [2:0] objSize;
output pixelOn;
wire [7:0] objIndex;
wire [8:0] objByteIndex;
wire objMaskOn, objPosOn;
reg objSizeOn;
reg [2:0] objMaskSel;
assign objIndex = pixelNum - objPos - 8'd1;
assign objByteIndex = 9'b1 << (objIndex[7:3]);
always @(objSize, objByteIndex)
begin
case (objSize)
3'd0: objSizeOn <= (objByteIndex & 9'b00000001) != 0;
3'd1: objSizeOn <= (objByteIndex & 9'b00000101) != 0;
3'd2: objSizeOn <= (objByteIndex & 9'b00010001) != 0;
3'd3: objSizeOn <= (objByteIndex & 9'b00010101) != 0;
3'd4: objSizeOn <= (objByteIndex & 9'b10000001) != 0;
3'd5: objSizeOn <= (objByteIndex & 9'b00000011) != 0;
3'd6: objSizeOn <= (objByteIndex & 9'b10010001) != 0;
3'd7: objSizeOn <= (objByteIndex & 9'b00001111) != 0;
endcase
end
always @(objSize, objIndex)
begin
case (objSize)
3'd5: objMaskSel <= objIndex[3:1];
3'd7: objMaskSel <= objIndex[4:2];
default: objMaskSel <= objIndex[2:0];
endcase
end
assign objMaskOn = objMask[objMaskSel];
assign objPosOn = (pixelNum > objPos) && ({1'b0, pixelNum} <= {1'b0, objPos} + 9'd72);
assign pixelOn = objSizeOn && objMaskOn && objPosOn;
endmodule
|
module cpu_0_oci_test_bench (
// inputs:
dct_buffer,
dct_count,
test_ending,
test_has_ended
)
;
input [ 29: 0] dct_buffer;
input [ 3: 0] dct_count;
input test_ending;
input test_has_ended;
endmodule
|
module e203_exu_alu_dpath(
//////////////////////////////////////////////////////
// ALU request the datapath
input alu_req_alu,
input alu_req_alu_add ,
input alu_req_alu_sub ,
input alu_req_alu_xor ,
input alu_req_alu_sll ,
input alu_req_alu_srl ,
input alu_req_alu_sra ,
input alu_req_alu_or ,
input alu_req_alu_and ,
input alu_req_alu_slt ,
input alu_req_alu_sltu,
input alu_req_alu_lui ,
input [`E203_XLEN-1:0] alu_req_alu_op1,
input [`E203_XLEN-1:0] alu_req_alu_op2,
output [`E203_XLEN-1:0] alu_req_alu_res,
//////////////////////////////////////////////////////
// BJP request the datapath
input bjp_req_alu,
input [`E203_XLEN-1:0] bjp_req_alu_op1,
input [`E203_XLEN-1:0] bjp_req_alu_op2,
input bjp_req_alu_cmp_eq ,
input bjp_req_alu_cmp_ne ,
input bjp_req_alu_cmp_lt ,
input bjp_req_alu_cmp_gt ,
input bjp_req_alu_cmp_ltu,
input bjp_req_alu_cmp_gtu,
input bjp_req_alu_add,
output bjp_req_alu_cmp_res,
output [`E203_XLEN-1:0] bjp_req_alu_add_res,
//////////////////////////////////////////////////////
// AGU request the datapath
input agu_req_alu,
input [`E203_XLEN-1:0] agu_req_alu_op1,
input [`E203_XLEN-1:0] agu_req_alu_op2,
input agu_req_alu_swap,
input agu_req_alu_add ,
input agu_req_alu_and ,
input agu_req_alu_or ,
input agu_req_alu_xor ,
input agu_req_alu_max ,
input agu_req_alu_min ,
input agu_req_alu_maxu,
input agu_req_alu_minu,
output [`E203_XLEN-1:0] agu_req_alu_res,
input agu_sbf_0_ena,
input [`E203_XLEN-1:0] agu_sbf_0_nxt,
output [`E203_XLEN-1:0] agu_sbf_0_r,
input agu_sbf_1_ena,
input [`E203_XLEN-1:0] agu_sbf_1_nxt,
output [`E203_XLEN-1:0] agu_sbf_1_r,
`ifdef E203_SUPPORT_SHARE_MULDIV //{
//////////////////////////////////////////////////////
// MULDIV request the datapath
input muldiv_req_alu,
input [`E203_ALU_ADDER_WIDTH-1:0] muldiv_req_alu_op1,
input [`E203_ALU_ADDER_WIDTH-1:0] muldiv_req_alu_op2,
input muldiv_req_alu_add ,
input muldiv_req_alu_sub ,
output [`E203_ALU_ADDER_WIDTH-1:0] muldiv_req_alu_res,
input muldiv_sbf_0_ena,
input [33-1:0] muldiv_sbf_0_nxt,
output [33-1:0] muldiv_sbf_0_r,
input muldiv_sbf_1_ena,
input [33-1:0] muldiv_sbf_1_nxt,
output [33-1:0] muldiv_sbf_1_r,
`endif//E203_SUPPORT_SHARE_MULDIV}
input clk,
input rst_n
);
`ifdef E203_XLEN_IS_32
// This is the correct config since E200 is 32bits core
`else
!!! ERROR: There must be something wrong, our core must be 32bits wide !!!
`endif
wire [`E203_XLEN-1:0] mux_op1;
wire [`E203_XLEN-1:0] mux_op2;
wire [`E203_XLEN-1:0] misc_op1 = mux_op1[`E203_XLEN-1:0];
wire [`E203_XLEN-1:0] misc_op2 = mux_op2[`E203_XLEN-1:0];
// Only the regular ALU use shifter
wire [`E203_XLEN-1:0] shifter_op1 = alu_req_alu_op1[`E203_XLEN-1:0];
wire [`E203_XLEN-1:0] shifter_op2 = alu_req_alu_op2[`E203_XLEN-1:0];
wire op_max;
wire op_min ;
wire op_maxu;
wire op_minu;
wire op_add;
wire op_sub;
wire op_addsub = op_add | op_sub;
wire op_or;
wire op_xor;
wire op_and;
wire op_sll;
wire op_srl;
wire op_sra;
wire op_slt;
wire op_sltu;
wire op_mvop2;
wire op_cmp_eq ;
wire op_cmp_ne ;
wire op_cmp_lt ;
wire op_cmp_gt ;
wire op_cmp_ltu;
wire op_cmp_gtu;
wire cmp_res;
wire sbf_0_ena;
wire [33-1:0] sbf_0_nxt;
wire [33-1:0] sbf_0_r;
wire sbf_1_ena;
wire [33-1:0] sbf_1_nxt;
wire [33-1:0] sbf_1_r;
//////////////////////////////////////////////////////////////
// Impelment the Left-Shifter
//
// The Left-Shifter will be used to handle the shift op
wire [`E203_XLEN-1:0] shifter_in1;
wire [5-1:0] shifter_in2;
wire [`E203_XLEN-1:0] shifter_res;
wire op_shift = op_sra | op_sll | op_srl;
// Make sure to use logic-gating to gateoff the
assign shifter_in1 = {`E203_XLEN{op_shift}} &
// In order to save area and just use one left-shifter, we
// convert the right-shift op into left-shift operation
(
(op_sra | op_srl) ?
{
shifter_op1[00],shifter_op1[01],shifter_op1[02],shifter_op1[03],
shifter_op1[04],shifter_op1[05],shifter_op1[06],shifter_op1[07],
shifter_op1[08],shifter_op1[09],shifter_op1[10],shifter_op1[11],
shifter_op1[12],shifter_op1[13],shifter_op1[14],shifter_op1[15],
shifter_op1[16],shifter_op1[17],shifter_op1[18],shifter_op1[19],
shifter_op1[20],shifter_op1[21],shifter_op1[22],shifter_op1[23],
shifter_op1[24],shifter_op1[25],shifter_op1[26],shifter_op1[27],
shifter_op1[28],shifter_op1[29],shifter_op1[30],shifter_op1[31]
} : shifter_op1
);
assign shifter_in2 = {5{op_shift}} & shifter_op2[4:0];
assign shifter_res = (shifter_in1 << shifter_in2);
wire [`E203_XLEN-1:0] sll_res = shifter_res;
wire [`E203_XLEN-1:0] srl_res =
{
shifter_res[00],shifter_res[01],shifter_res[02],shifter_res[03],
shifter_res[04],shifter_res[05],shifter_res[06],shifter_res[07],
shifter_res[08],shifter_res[09],shifter_res[10],shifter_res[11],
shifter_res[12],shifter_res[13],shifter_res[14],shifter_res[15],
shifter_res[16],shifter_res[17],shifter_res[18],shifter_res[19],
shifter_res[20],shifter_res[21],shifter_res[22],shifter_res[23],
shifter_res[24],shifter_res[25],shifter_res[26],shifter_res[27],
shifter_res[28],shifter_res[29],shifter_res[30],shifter_res[31]
};
wire [`E203_XLEN-1:0] eff_mask = (~(`E203_XLEN'b0)) >> shifter_in2;
wire [`E203_XLEN-1:0] sra_res =
(srl_res & eff_mask) | ({32{shifter_op1[31]}} & (~eff_mask));
//////////////////////////////////////////////////////////////
// Impelment the Adder
//
// The Adder will be reused to handle the add/sub/compare op
// Only the MULDIV request ALU-adder with 35bits operand with sign extended
// already, all other unit request ALU-adder with 32bits opereand without sign extended
// For non-MULDIV operands
wire op_unsigned = op_sltu | op_cmp_ltu | op_cmp_gtu | op_maxu | op_minu;
wire [`E203_ALU_ADDER_WIDTH-1:0] misc_adder_op1 =
{{`E203_ALU_ADDER_WIDTH-`E203_XLEN{(~op_unsigned) & misc_op1[`E203_XLEN-1]}},misc_op1};
wire [`E203_ALU_ADDER_WIDTH-1:0] misc_adder_op2 =
{{`E203_ALU_ADDER_WIDTH-`E203_XLEN{(~op_unsigned) & misc_op2[`E203_XLEN-1]}},misc_op2};
wire [`E203_ALU_ADDER_WIDTH-1:0] adder_op1 =
`ifdef E203_SUPPORT_SHARE_MULDIV //{
muldiv_req_alu ? muldiv_req_alu_op1 :
`endif//E203_SUPPORT_SHARE_MULDIV}
misc_adder_op1;
wire [`E203_ALU_ADDER_WIDTH-1:0] adder_op2 =
`ifdef E203_SUPPORT_SHARE_MULDIV //{
muldiv_req_alu ? muldiv_req_alu_op2 :
`endif//E203_SUPPORT_SHARE_MULDIV}
misc_adder_op2;
wire adder_cin;
wire [`E203_ALU_ADDER_WIDTH-1:0] adder_in1;
wire [`E203_ALU_ADDER_WIDTH-1:0] adder_in2;
wire [`E203_ALU_ADDER_WIDTH-1:0] adder_res;
wire adder_add;
wire adder_sub;
assign adder_add =
`ifdef E203_SUPPORT_SHARE_MULDIV //{
muldiv_req_alu ? muldiv_req_alu_add :
`endif//E203_SUPPORT_SHARE_MULDIV}
op_add;
assign adder_sub =
`ifdef E203_SUPPORT_SHARE_MULDIV //{
muldiv_req_alu ? muldiv_req_alu_sub :
`endif//E203_SUPPORT_SHARE_MULDIV}
(
// The original sub instruction
(op_sub)
// The compare lt or gt instruction
| (op_cmp_lt | op_cmp_gt |
op_cmp_ltu | op_cmp_gtu |
op_max | op_maxu |
op_min | op_minu |
op_slt | op_sltu
));
wire adder_addsub = adder_add | adder_sub;
// Make sure to use logic-gating to gateoff the
assign adder_in1 = {`E203_ALU_ADDER_WIDTH{adder_addsub}} & (adder_op1);
assign adder_in2 = {`E203_ALU_ADDER_WIDTH{adder_addsub}} & (adder_sub ? (~adder_op2) : adder_op2);
assign adder_cin = adder_addsub & adder_sub;
assign adder_res = adder_in1 + adder_in2 + adder_cin;
//////////////////////////////////////////////////////////////
// Impelment the XOR-er
//
// The XOR-er will be reused to handle the XOR and compare op
wire [`E203_XLEN-1:0] xorer_in1;
wire [`E203_XLEN-1:0] xorer_in2;
wire xorer_op =
op_xor
// The compare eq or ne instruction
| (op_cmp_eq | op_cmp_ne);
// Make sure to use logic-gating to gateoff the
assign xorer_in1 = {`E203_XLEN{xorer_op}} & misc_op1;
assign xorer_in2 = {`E203_XLEN{xorer_op}} & misc_op2;
wire [`E203_XLEN-1:0] xorer_res = xorer_in1 ^ xorer_in2;
// The OR and AND is too light-weight, so no need to gate off
wire [`E203_XLEN-1:0] orer_res = misc_op1 | misc_op2;
wire [`E203_XLEN-1:0] ander_res = misc_op1 & misc_op2;
//////////////////////////////////////////////////////////////
// Generate the CMP operation result
// It is Non-Equal if the XOR result have any bit non-zero
wire neq = (|xorer_res);
wire cmp_res_ne = (op_cmp_ne & neq);
// It is Equal if it is not Non-Equal
wire cmp_res_eq = op_cmp_eq & (~neq);
// It is Less-Than if the adder result is negative
wire cmp_res_lt = op_cmp_lt & adder_res[`E203_XLEN];
wire cmp_res_ltu = op_cmp_ltu & adder_res[`E203_XLEN];
// It is Greater-Than if the adder result is postive
wire op1_gt_op2 = (~adder_res[`E203_XLEN]);
wire cmp_res_gt = op_cmp_gt & op1_gt_op2;
wire cmp_res_gtu = op_cmp_gtu & op1_gt_op2;
assign cmp_res = cmp_res_eq
| cmp_res_ne
| cmp_res_lt
| cmp_res_gt
| cmp_res_ltu
| cmp_res_gtu;
//////////////////////////////////////////////////////////////
// Generate the mvop2 result
// Just directly use op2 since the op2 will be the immediate
wire [`E203_XLEN-1:0] mvop2_res = misc_op2;
//////////////////////////////////////////////////////////////
// Generate the SLT and SLTU result
// Just directly use op2 since the op2 will be the immediate
wire op_slttu = (op_slt | op_sltu);
// The SLT and SLTU is reusing the adder to do the comparasion
// It is Less-Than if the adder result is negative
wire slttu_cmp_lt = op_slttu & adder_res[`E203_XLEN];
wire [`E203_XLEN-1:0] slttu_res =
slttu_cmp_lt ?
`E203_XLEN'b1 : `E203_XLEN'b0;
//////////////////////////////////////////////////////////////
// Generate the Max/Min result
wire maxmin_sel_op1 = ((op_max | op_maxu) & op1_gt_op2)
| ((op_min | op_minu) & (~op1_gt_op2));
wire [`E203_XLEN-1:0] maxmin_res = maxmin_sel_op1 ? misc_op1 : misc_op2;
//////////////////////////////////////////////////////////////
// Generate the final result
wire [`E203_XLEN-1:0] alu_dpath_res =
({`E203_XLEN{op_or }} & orer_res )
| ({`E203_XLEN{op_and }} & ander_res)
| ({`E203_XLEN{op_xor }} & xorer_res)
| ({`E203_XLEN{op_addsub }} & adder_res[`E203_XLEN-1:0])
| ({`E203_XLEN{op_srl }} & srl_res)
| ({`E203_XLEN{op_sll }} & sll_res)
| ({`E203_XLEN{op_sra }} & sra_res)
| ({`E203_XLEN{op_mvop2 }} & mvop2_res)
| ({`E203_XLEN{op_slttu }} & slttu_res)
| ({`E203_XLEN{op_max | op_maxu | op_min | op_minu}} & maxmin_res)
;
//////////////////////////////////////////////////////////////
// Implement the SBF: Shared Buffers
sirv_gnrl_dffl #(33) sbf_0_dffl (sbf_0_ena, sbf_0_nxt, sbf_0_r, clk);
sirv_gnrl_dffl #(33) sbf_1_dffl (sbf_1_ena, sbf_1_nxt, sbf_1_r, clk);
/////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////
// The ALU-Datapath Mux for the requestors
localparam DPATH_MUX_WIDTH = ((`E203_XLEN*2)+21);
assign {
mux_op1
,mux_op2
,op_max
,op_min
,op_maxu
,op_minu
,op_add
,op_sub
,op_or
,op_xor
,op_and
,op_sll
,op_srl
,op_sra
,op_slt
,op_sltu
,op_mvop2
,op_cmp_eq
,op_cmp_ne
,op_cmp_lt
,op_cmp_gt
,op_cmp_ltu
,op_cmp_gtu
}
=
({DPATH_MUX_WIDTH{alu_req_alu}} & {
alu_req_alu_op1
,alu_req_alu_op2
,1'b0
,1'b0
,1'b0
,1'b0
,alu_req_alu_add
,alu_req_alu_sub
,alu_req_alu_or
,alu_req_alu_xor
,alu_req_alu_and
,alu_req_alu_sll
,alu_req_alu_srl
,alu_req_alu_sra
,alu_req_alu_slt
,alu_req_alu_sltu
,alu_req_alu_lui// LUI just move-Op2 operation
,1'b0
,1'b0
,1'b0
,1'b0
,1'b0
,1'b0
})
| ({DPATH_MUX_WIDTH{bjp_req_alu}} & {
bjp_req_alu_op1
,bjp_req_alu_op2
,1'b0
,1'b0
,1'b0
,1'b0
,bjp_req_alu_add
,1'b0
,1'b0
,1'b0
,1'b0
,1'b0
,1'b0
,1'b0
,1'b0
,1'b0
,1'b0
,bjp_req_alu_cmp_eq
,bjp_req_alu_cmp_ne
,bjp_req_alu_cmp_lt
,bjp_req_alu_cmp_gt
,bjp_req_alu_cmp_ltu
,bjp_req_alu_cmp_gtu
})
| ({DPATH_MUX_WIDTH{agu_req_alu}} & {
agu_req_alu_op1
,agu_req_alu_op2
,agu_req_alu_max
,agu_req_alu_min
,agu_req_alu_maxu
,agu_req_alu_minu
,agu_req_alu_add
,1'b0
,agu_req_alu_or
,agu_req_alu_xor
,agu_req_alu_and
,1'b0
,1'b0
,1'b0
,1'b0
,1'b0
,agu_req_alu_swap// SWAP just move-Op2 operation
,1'b0
,1'b0
,1'b0
,1'b0
,1'b0
,1'b0
})
;
assign alu_req_alu_res = alu_dpath_res[`E203_XLEN-1:0];
assign agu_req_alu_res = alu_dpath_res[`E203_XLEN-1:0];
assign bjp_req_alu_add_res = alu_dpath_res[`E203_XLEN-1:0];
assign bjp_req_alu_cmp_res = cmp_res;
`ifdef E203_SUPPORT_SHARE_MULDIV //{
assign muldiv_req_alu_res = adder_res;
`endif//E203_SUPPORT_SHARE_MULDIV}
assign sbf_0_ena =
`ifdef E203_SUPPORT_SHARE_MULDIV //{
muldiv_req_alu ? muldiv_sbf_0_ena :
`endif//E203_SUPPORT_SHARE_MULDIV}
agu_sbf_0_ena;
assign sbf_1_ena =
`ifdef E203_SUPPORT_SHARE_MULDIV //{
muldiv_req_alu ? muldiv_sbf_1_ena :
`endif//E203_SUPPORT_SHARE_MULDIV}
agu_sbf_1_ena;
assign sbf_0_nxt =
`ifdef E203_SUPPORT_SHARE_MULDIV //{
muldiv_req_alu ? muldiv_sbf_0_nxt :
`endif//E203_SUPPORT_SHARE_MULDIV}
{1'b0,agu_sbf_0_nxt};
assign sbf_1_nxt =
`ifdef E203_SUPPORT_SHARE_MULDIV //{
muldiv_req_alu ? muldiv_sbf_1_nxt :
`endif//E203_SUPPORT_SHARE_MULDIV}
{1'b0,agu_sbf_1_nxt};
assign agu_sbf_0_r = sbf_0_r[`E203_XLEN-1:0];
assign agu_sbf_1_r = sbf_1_r[`E203_XLEN-1:0];
`ifdef E203_SUPPORT_SHARE_MULDIV //{
assign muldiv_sbf_0_r = sbf_0_r;
assign muldiv_sbf_1_r = sbf_1_r;
`endif//E203_SUPPORT_SHARE_MULDIV}
endmodule
|
module sky130_fd_sc_hdll__a31oi (
Y ,
A1 ,
A2 ,
A3 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
|
module sky130_fd_sc_ms__o211a (
X ,
A1 ,
A2 ,
B1 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A1 ;
input A2 ;
input B1 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire or0_out ;
wire and0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
or or0 (or0_out , A2, A1 );
and and0 (and0_out_X , or0_out, B1, C1 );
sky130_fd_sc_ms__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, and0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
|
module mig_7series_v2_0_axi4_wrapper #(
parameter C_AXI_ID_WIDTH = 4, // The AXI id width used for read and write
// This is an integer between 1-16
parameter C_AXI_ADDR_WIDTH = 32, // This is AXI address width for all
// SI and MI slots
parameter C_AXI_DATA_WIDTH = 32, // Width of the AXI write and read data
parameter C_AXI_NBURST_SUPPORT = 0, // Support for narrow burst transfers
// 1-supported, 0-not supported
parameter C_BEGIN_ADDRESS = 0, // Start address of the address map
parameter C_END_ADDRESS = 32'hFFFF_FFFF, // End address of the address map
parameter CTL_SIG_WIDTH = 2, // Control signal width
parameter WR_STS_WIDTH = 16, // Write port status signal width
parameter RD_STS_WIDTH = 16, // Read port status signal width
parameter EN_UPSIZER = 0, // There is no upsizer code
parameter WDG_TIMER_WIDTH = 9
)
(
input aclk, // AXI input clock
input aresetn, // Active low AXI reset signal
// User interface command port
input cmd_en, // Asserted to indicate a valid command
// and address
input [2:0] cmd, // Write or read command
// 000 - READ with INCR bursts
// 001 - READ with WRAP bursts
// 01x - Reserved
// 100 - WRITE with INCR bursts
// 101 - WRITE with WRAP bursts
input [7:0] blen, // Burst length calculated as blen+1
input [31:0] addr, // Address for the read or the write
// transaction
input [CTL_SIG_WIDTH-1:0] ctl, // control command for read or write
// transaction
input wdog_mask, // Mask the watchdog timeouts
output cmd_ack,// Indicates the command has been accepted
// User interface write ports
input wrdata_vld, // Asserted to indicate a valid write
// data
input [C_AXI_DATA_WIDTH-1:0] wrdata, // Write data
input [C_AXI_DATA_WIDTH/8-1:0] wrdata_bvld, // Byte valids for the write data
input wrdata_cmptd,// Last data to be transferred
output reg wrdata_rdy, // Indicates that the write data is
// ready to be accepted
output reg wrdata_sts_vld, // Indicates a write status after
// completion of a write transfer
output [WR_STS_WIDTH-1:0] wrdata_sts, // Status of the write transaction
// User interface read ports
input rddata_rdy, // Data ready to be accepted
output reg rddata_vld, // Indicates a valid read data available
output reg [C_AXI_DATA_WIDTH-1:0] rddata, // Read data
output [C_AXI_DATA_WIDTH/8-1:0] rddata_bvld, // Byte valids for read data
output reg rddata_cmptd, // Indicates last data present and
// valid status
output [RD_STS_WIDTH-1:0] rddata_sts, // Status of the read transaction
// AXI write address channel signals
input axi_wready, // Indicates slave is ready to accept a
// write address
output [C_AXI_ID_WIDTH-1:0] axi_wid, // Write ID
output [C_AXI_ADDR_WIDTH-1:0] axi_waddr, // Write address
output [7:0] axi_wlen, // Write Burst Length
output [2:0] axi_wsize, // Write Burst size
output [1:0] axi_wburst, // Write Burst type
output [1:0] axi_wlock, // Write lock type
output [3:0] axi_wcache, // Write Cache type
output [2:0] axi_wprot, // Write Protection type
output reg axi_wvalid, // Write address valid
// AXI write data channel signals
input axi_wd_wready, // Write data ready
output [C_AXI_ID_WIDTH-1:0] axi_wd_wid, // Write ID tag
output reg [C_AXI_DATA_WIDTH-1:0] axi_wd_data, // Write data
output reg [C_AXI_DATA_WIDTH/8-1:0] axi_wd_strb, // Write strobes
output reg axi_wd_last, // Last write transaction
output axi_wd_valid, // Write valid
// AXI write response channel signals
input [C_AXI_ID_WIDTH-1:0] axi_wd_bid, // Response ID
input [1:0] axi_wd_bresp, // Write response
input axi_wd_bvalid, // Write reponse valid
output reg axi_wd_bready, // Response ready
// AXI read address channel signals
input axi_rready, // Read address ready
output [C_AXI_ID_WIDTH-1:0] axi_rid, // Read ID
output [C_AXI_ADDR_WIDTH-1:0] axi_raddr, // Read address
output [7:0] axi_rlen, // Read Burst Length
output [2:0] axi_rsize, // Read Burst size
output [1:0] axi_rburst, // Read Burst type
output [1:0] axi_rlock, // Read lock type
output [3:0] axi_rcache, // Read Cache type
output [2:0] axi_rprot, // Read Protection type
output reg axi_rvalid, // Read address valid
// AXI read data channel signals
input [C_AXI_ID_WIDTH-1:0] axi_rd_bid, // Response ID
input [1:0] axi_rd_rresp, // Read response
input axi_rd_rvalid, // Read reponse valid
input [C_AXI_DATA_WIDTH-1:0] axi_rd_data, // Read data
input axi_rd_last, // Read last
output reg axi_rd_rready // Read Response ready
);
//*****************************************************************************
// Internal parameter declarations
//*****************************************************************************
parameter [8:0] AXI_WRIDLE = 9'd0,
AXI_WRCTL = 9'd1,
AXI_WRRDY = 9'd2,
AXI_WRDAT = 9'd3,
AXI_WRDAT_WT = 9'd4,
AXI_WRDAT_LST = 9'd5,
AXI_WRDAT_DMY = 9'd6,
AXI_WRRESP_WT = 9'd7,
AXI_WRTO = 9'd8;
parameter [5:0] AXI_RDIDLE = 6'd0,
AXI_RDCTL = 6'd1,
AXI_RDDAT = 6'd2,
AXI_RDDAT_LST = 6'd3,
AXI_RDDAT_WT = 6'd4,
AXI_RDTO = 6'd5;
//*****************************************************************************
// Internal register and wire declarations
//*****************************************************************************
reg wrap_w;
reg [7:0] blen_w;
reg [7:0] blen_w_minus_1;
reg [C_AXI_ADDR_WIDTH-1:0] addr_w;
reg [CTL_SIG_WIDTH-1:0] ctl_w;
reg wrap_r;
reg [7:0] blen_r;
reg [C_AXI_ADDR_WIDTH-1:0] addr_r;
reg [CTL_SIG_WIDTH-1:0] ctl_r;
reg [8:0] wstate;
reg [8:0] next_wstate;
reg wr_cmd_start;
reg [WDG_TIMER_WIDTH-1:0] wr_wdog_cntr;
reg wrdata_vld_r;
reg wrdata_cmptd_r;
reg [7:0] wr_len_cntr;
reg [7:0] rd_len_cntr;
reg [7:0] blen_cntr;
reg [3:0] wr_cntr;
reg [C_AXI_DATA_WIDTH-1:0] wrdata_r1;
reg [C_AXI_DATA_WIDTH-1:0] wrdata_r2;
reg wrdata_mux_ctrl;
reg [2:0] wrdata_fsm_sts;
reg [3:0] brespid_r;
reg [1:0] bresp_r;
reg [5:0] rstate;
reg [5:0] next_rstate;
reg [WDG_TIMER_WIDTH-1:0] rd_wdog_cntr;
reg rd_cmd_start;
reg rlast;
reg [3:0] rd_cntr;
reg rddata_ppld;
reg [C_AXI_DATA_WIDTH-1:0] rddata_p1;
reg err_resp;
reg [1:0] rddata_fsm_sts;
reg rrid_err;
reg pending_one_trans;
reg axi_wready_l;
wire wr_cmd_timeout;
wire wr_done;
wire wr_last;
wire rd_cmd_timeout;
//*****************************************************************************
// Address and control register logic
//*****************************************************************************
always @(posedge aclk) begin
if (!aresetn) begin
wrap_w <= 1'b0;
blen_w <= 8'h0;
blen_w_minus_1 <= 8'h0;
addr_w <= {C_AXI_ADDR_WIDTH{1'b0}};
ctl_w <= {CTL_SIG_WIDTH{1'b0}};
end
else if (wstate[AXI_WRIDLE] & next_wstate[AXI_WRIDLE] &
cmd_en & cmd[2]) begin
wrap_w <= cmd[0];
blen_w <= blen;
blen_w_minus_1 <= blen - 8'h01;
addr_w <= addr;
ctl_w <= ctl;
end
end
always @(posedge aclk) begin
if (!aresetn) begin
wrap_r <= 1'b0;
blen_r <= 8'h0;
addr_r <= {C_AXI_ADDR_WIDTH{1'b0}};
ctl_r <= {CTL_SIG_WIDTH{1'b0}};
end
else if (rstate[AXI_RDIDLE] & next_rstate[AXI_RDIDLE] &
cmd_en & !cmd[2]) begin
wrap_r <= cmd[0];
blen_r <= blen;
addr_r <= addr;
ctl_r <= ctl;
end
end
assign cmd_ack = (wstate[AXI_WRIDLE] & next_wstate[AXI_WRCTL]) |
(rstate[AXI_RDIDLE] & next_rstate[AXI_RDCTL]);
//*****************************************************************************
// Write data state machine control signals
//*****************************************************************************
always @(posedge aclk)
if (!aresetn)
wr_cmd_start <= 1'b0;
else if (cmd_en & cmd[2] & wstate[AXI_WRIDLE])
wr_cmd_start <= 1'b1;
else if (wstate[AXI_WRCTL])
wr_cmd_start <= 1'b0;
always @(posedge aclk)
if (wstate[AXI_WRIDLE] |
(axi_wd_wready & (wstate[AXI_WRDAT] | wstate[AXI_WRDAT_WT] | wstate[AXI_WRDAT_LST] | wstate[AXI_WRDAT_DMY])) |
(axi_wd_bvalid & wstate[AXI_WRRESP_WT]))
wr_wdog_cntr <= 'h0;
else if (!wstate[AXI_WRTO] & !wdog_mask)
wr_wdog_cntr <= wr_wdog_cntr + 'h1;
always @(posedge aclk)
wrdata_vld_r <= wrdata_vld;
always @(posedge aclk)
if (wstate[AXI_WRIDLE])
wrdata_cmptd_r <= 1'b0;
else if (wrdata_cmptd & wrdata_vld)
wrdata_cmptd_r <= 1'b1;
always @(posedge aclk)
if (wstate[AXI_WRIDLE])
blen_cntr <= 8'h0;
else if (wrdata_vld & wrdata_rdy)
blen_cntr <= blen_cntr + 8'h01;
always @(posedge aclk)
if (wstate[AXI_WRIDLE])
pending_one_trans <= 1'b0;
else if (next_wstate[AXI_WRDAT] & wstate[AXI_WRDAT_WT])
pending_one_trans <= 1'b0;
else if (wstate[AXI_WRDAT] & next_wstate[AXI_WRDAT_WT] & wr_last & !axi_wd_wready)
pending_one_trans <= 1'b1;
always @(posedge aclk)
if (wstate[AXI_WRIDLE])
wr_len_cntr <= 8'h0;
else if ((wstate[AXI_WRDAT_DMY] | wstate[AXI_WRDAT] | wstate[AXI_WRDAT_WT]) &
axi_wd_valid & axi_wd_wready)
wr_len_cntr <= wr_len_cntr + 8'h01;
always @(posedge aclk)
if (wstate[AXI_WRIDLE])
axi_wready_l <= 1'b0;
else if (axi_wready)
axi_wready_l <= 1'b1;
assign wr_cmd_timeout = wr_wdog_cntr[WDG_TIMER_WIDTH-1] & !wdog_mask;
assign wr_last = (wr_len_cntr >= blen_w_minus_1);
assign wr_done = (blen_cntr >= blen_w);
//*****************************************************************************
// Write data state machine
//*****************************************************************************
always @(posedge aclk) begin
if (!aresetn)
wstate <= 9'h1;
else
wstate <= next_wstate;
end
always @(*) begin
next_wstate = 9'h0;
case (1'b1)
wstate[AXI_WRIDLE]: begin // 9'h001
if (wr_cmd_start)
next_wstate[AXI_WRCTL] = 1'b1;
else
next_wstate[AXI_WRIDLE] = 1'b1;
end
wstate[AXI_WRCTL]: begin // 9'h002
if (wr_cmd_timeout)
next_wstate[AXI_WRTO] = 1'b1;
else if (axi_wvalid)
next_wstate[AXI_WRRDY] = 1'b1;
else
next_wstate[AXI_WRCTL] = 1'b1;
end
wstate[AXI_WRRDY]: begin // 9'h004
if (wrdata_cmptd_r & wrdata_rdy)
next_wstate[AXI_WRDAT_LST] = 1'b1;
else if (wrdata_vld_r & wrdata_rdy)
next_wstate[AXI_WRDAT] = 1'b1;
else
next_wstate[AXI_WRRDY] = 1'b1;
end
wstate[AXI_WRDAT]: begin // 9'h008
if (wr_cmd_timeout)
next_wstate[AXI_WRTO] = 1'b1;
else if (axi_wd_wready & wrdata_cmptd_r & (wr_last | ~(|blen_w)))
next_wstate[AXI_WRDAT_LST] = 1'b1;
else if (axi_wd_wready & wrdata_cmptd_r & !wr_done &
(wr_len_cntr != 8'h00))
next_wstate[AXI_WRDAT_DMY] = 1'b1;
else if (!axi_wd_wready)
next_wstate[AXI_WRDAT_WT] = 1'b1;
else
next_wstate[AXI_WRDAT] = 1'b1;
end
wstate[AXI_WRDAT_WT]: begin // 9'h010
if (wr_cmd_timeout)
next_wstate[AXI_WRTO] = 1'b1;
else if (axi_wd_wready) begin
if (pending_one_trans & wrdata_cmptd_r & (wr_last | ~(|blen_w)))
next_wstate[AXI_WRDAT_LST] = 1'b1;
else if (!pending_one_trans & wrdata_cmptd_r & !wr_done &
(wr_len_cntr != 8'h00))
next_wstate[AXI_WRDAT_DMY] = 1'b1;
else
next_wstate[AXI_WRDAT] = 1'b1;
end
else
next_wstate[AXI_WRDAT_WT] = 1'b1;
end
wstate[AXI_WRDAT_LST]: begin // 9'h020
if (wr_cmd_timeout)
next_wstate[AXI_WRTO] = 1'b1;
else if (axi_wd_valid & axi_wd_wready)
next_wstate[AXI_WRRESP_WT] = 1'b1;
else
next_wstate[AXI_WRDAT_LST] = 1'b1;
end
wstate[AXI_WRDAT_DMY]: begin // 9'h040
if (wr_cmd_timeout)
next_wstate[AXI_WRTO] = 1'b1;
else if (wrdata_cmptd_r & wr_last)
next_wstate[AXI_WRDAT_LST] = 1'b1;
else if (!wr_last & !axi_wd_wready)
next_wstate[AXI_WRDAT_WT] = 1'b1;
else
next_wstate[AXI_WRDAT_DMY] = 1'b1;
end
wstate[AXI_WRRESP_WT]: begin // 9'h080
if (wr_cmd_timeout)
next_wstate[AXI_WRTO] = 1'b1;
else if (axi_wd_bvalid &
(EN_UPSIZER == 1 || (EN_UPSIZER == 0 & axi_wready_l)))
next_wstate[AXI_WRIDLE] = 1'b1;
else
next_wstate[AXI_WRRESP_WT] = 1'b1;
end
wstate[AXI_WRTO]: begin // 9'h100
next_wstate[AXI_WRIDLE] = 1'b1;
end
endcase
end
//*****************************************************************************
// Write channel control signals
//*****************************************************************************
always @(posedge aclk)
if (!aresetn)
wr_cntr <= 4'h0;
else if (wstate[AXI_WRRESP_WT] & next_wstate[AXI_WRIDLE])
wr_cntr <= wr_cntr + 4'h1;
always @(posedge aclk)
if (!aresetn)
axi_wvalid <= 1'b0;
else if ((wstate[AXI_WRCTL] & next_wstate[AXI_WRRDY] & axi_wready) ||
(axi_wready & !wstate[AXI_WRCTL]))
axi_wvalid <= 1'b0;
else if (wstate[AXI_WRCTL])
axi_wvalid <= 1'b1;
assign awid = wr_cntr;
assign axi_waddr = addr_w;
assign axi_wid = wr_cntr;
assign axi_wlen = blen_w;
assign axi_wburst = {1'b0, wrap_w} + 2'b01;
assign axi_wsize = ctl_w[2:0];
// Not supported and hence assigned zeros
assign axi_wlock = 2'b0;
assign axi_wcache = 4'b0;
assign axi_wprot = 3'b0;
//*****************************************************************************
// Write channel data signals
//*****************************************************************************
always @(posedge aclk) begin
if (wstate[AXI_WRIDLE]) begin
wrdata_r1 <= 'h0;
wrdata_r2 <= 'h0;
end
else if (wrdata_rdy & wrdata_vld & (wstate[AXI_WRDAT] | wstate[AXI_WRRDY] |
wstate[AXI_WRDAT_LST])) begin
wrdata_r1 <= wrdata;
wrdata_r2 <= wrdata_r1;
end
end
always @(posedge aclk)
if (!aresetn)
wrdata_rdy <= 1'b0;
else if (wstate[AXI_WRDAT_LST] | (wstate[AXI_WRDAT] & next_wstate[AXI_WRDAT_WT]))
wrdata_rdy <= 1'b0;
else if (wstate[AXI_WRDAT] |
(wstate[AXI_WRCTL] & next_wstate[AXI_WRRDY]) |
(wstate[AXI_WRDAT_WT] & next_wstate[AXI_WRDAT]))
wrdata_rdy <= 1'b1;
always @(posedge aclk)
if (!aresetn)
wrdata_sts_vld <= 1'b0;
else if (wstate[AXI_WRIDLE])
wrdata_sts_vld <= 1'b0;
else if ((wstate[AXI_WRRESP_WT] | wstate[AXI_WRTO]) & next_wstate[AXI_WRIDLE])
wrdata_sts_vld <= 1'b1;
always @(posedge aclk)
if (!aresetn)
wrdata_mux_ctrl <= 1'b0;
else if ((wstate[AXI_WRDAT_WT] & (next_wstate[AXI_WRDAT] | next_wstate[AXI_WRDAT_LST])) |
wstate[AXI_WRIDLE])
wrdata_mux_ctrl <= 1'b0;
else if (wstate[AXI_WRDAT] & next_wstate[AXI_WRDAT_WT] & !pending_one_trans)
wrdata_mux_ctrl <= 1'b1;
always @(posedge aclk)
if (!aresetn)
axi_wd_last <= 1'b0;
else if (wstate[AXI_WRDAT_LST] & next_wstate[AXI_WRRESP_WT])
axi_wd_last <= 1'b0;
else if ((wstate[AXI_WRDAT] | wstate[AXI_WRDAT_DMY] | wstate[AXI_WRRDY] | wstate[AXI_WRDAT_WT]) &
next_wstate[AXI_WRDAT_LST])
axi_wd_last <= 1'b1;
generate
begin: data_axi_wr
if (C_AXI_NBURST_SUPPORT == 1) begin
end
else begin
always @(posedge aclk)
if (wstate[AXI_WRIDLE])
axi_wd_data <= 'h0;
else if (axi_wd_wready & (wstate[AXI_WRDAT] | wstate[AXI_WRDAT_WT]) & wrdata_mux_ctrl &
~next_wstate[AXI_WRDAT_LST])
axi_wd_data <= wrdata_r2;
else if ((axi_wd_wready & (wstate[AXI_WRDAT] |
(wstate[AXI_WRDAT_WT] & next_wstate[AXI_WRDAT_LST]) |
(wstate[AXI_WRDAT_LST] & !next_wstate[AXI_WRRESP_WT]))) |
(wstate[AXI_WRRDY] & next_wstate[AXI_WRDAT]))
axi_wd_data <= wrdata_r1;
always @(posedge aclk)
if (wstate[AXI_WRIDLE])
axi_wd_strb <= {(C_AXI_DATA_WIDTH/8){1'b0}};
else if ((axi_wd_wready & (wstate[AXI_WRDAT] |
(next_wstate[AXI_WRDAT_LST] & (wstate[AXI_WRRDY] | wstate[AXI_WRDAT])) |
((wstate[AXI_WRRDY] | wstate[AXI_WRDAT_WT]) &
next_wstate[AXI_WRDAT]))) |
(next_wstate[AXI_WRDAT_LST] & !axi_wd_wready &
(wstate[AXI_WRDAT] | wstate[AXI_WRDAT_LST] |
wstate[AXI_WRDAT_DMY] | wstate[AXI_WRDAT_WT])) |
(wstate[AXI_WRRDY] & next_wstate[AXI_WRDAT]) |
((wstate[AXI_WRDAT] | wstate[AXI_WRDAT_DMY]) & next_wstate[AXI_WRDAT_WT]) |
(wstate[AXI_WRDAT_WT]))
axi_wd_strb <= {(C_AXI_DATA_WIDTH/8){1'b1}};
else
axi_wd_strb <= {(C_AXI_DATA_WIDTH/8){1'b0}};
end
end
endgenerate
assign axi_wd_wid = wr_cntr;
assign axi_wd_valid = wstate[AXI_WRDAT] | wstate[AXI_WRDAT_LST] |
wstate[AXI_WRDAT_DMY] | wstate[AXI_WRDAT_WT];
//*****************************************************************************
// Write response and status signals
//*****************************************************************************
always @(posedge aclk)
if (!aresetn)
axi_wd_bready <= 1'b0;
else if (next_wstate[AXI_WRIDLE] & wstate[AXI_WRRESP_WT])
axi_wd_bready <= 1'b0;
else if (wstate[AXI_WRRESP_WT])
axi_wd_bready <= 1'b1;
always @(posedge aclk)
if (wstate[AXI_WRIDLE])
wrdata_fsm_sts <= 3'b000;
else begin
if (next_wstate[AXI_WRTO]) begin
if (wstate[AXI_WRDAT])
wrdata_fsm_sts <= 3'b001;
else if (wstate[AXI_WRDAT_WT])
wrdata_fsm_sts <= 3'b010;
else if (wstate[AXI_WRDAT_DMY])
wrdata_fsm_sts <= 3'b011;
else if (wstate[AXI_WRRESP_WT])
wrdata_fsm_sts <= 3'b100;
end
end
always @(posedge aclk)
if (wstate[AXI_WRIDLE]) begin
brespid_r <= 4'h0;
bresp_r <= 2'b00;
end
else if (wstate[AXI_WRRESP_WT] & axi_wd_bvalid) begin
brespid_r <= axi_wd_bid;
bresp_r <= axi_wd_bresp;
end
assign wrdata_sts = {{{WR_STS_WIDTH-8}{1'b0}},wrdata_fsm_sts,brespid_r[3:0],bresp_r};
//*****************************************************************************
// Read data state machine control signals
//*****************************************************************************
always @(posedge aclk)
if (rstate[AXI_RDIDLE] | axi_rready | axi_rd_rvalid)
rd_wdog_cntr <= 'h0;
else if (!rstate[AXI_RDTO])
rd_wdog_cntr <= rd_wdog_cntr + 'h1;
always @(posedge aclk)
if (!aresetn)
rd_cmd_start <= 1'b0;
else if (cmd_en & !cmd[2] & rstate[AXI_RDIDLE])
rd_cmd_start <= 1'b1;
else if (rstate[AXI_RDCTL])
rd_cmd_start <= 1'b0;
always @(posedge aclk)
if (rstate[AXI_RDIDLE])
rlast <= 1'b0;
else if (axi_rd_last & axi_rd_rvalid)
rlast <= 1'b1;
assign rd_cmd_timeout = rd_wdog_cntr[WDG_TIMER_WIDTH-1] & !wdog_mask;
//*****************************************************************************
// Read data state machine
//*****************************************************************************
always @(posedge aclk) begin
if (!aresetn)
rstate <= 6'h1;
else
rstate <= next_rstate;
end
always @(*) begin
next_rstate = 6'h0;
case (1'b1)
rstate[AXI_RDIDLE]: begin // 6'h01
if (rd_cmd_start)
next_rstate[AXI_RDCTL] = 1'b1;
else
next_rstate[AXI_RDIDLE] = 1'b1;
end
rstate[AXI_RDCTL]: begin // 6'h02
if (rd_cmd_timeout)
next_rstate[AXI_RDTO] = 1'b1;
else if (axi_rready & axi_rvalid) begin
if (rddata_rdy)
next_rstate[AXI_RDDAT] = 1'b1;
else
next_rstate[AXI_RDDAT_WT] = 1'b1;
end
else
next_rstate[AXI_RDCTL] = 1'b1;
end
rstate[AXI_RDDAT]: begin // 6'h04
if (rd_cmd_timeout)
next_rstate[AXI_RDTO] = 1'b1;
else if (rddata_rdy) begin
if (rlast)
next_rstate[AXI_RDDAT_LST] = 1'b1;
else
next_rstate[AXI_RDDAT] = 1'b1;
end
else
next_rstate[AXI_RDDAT_WT] = 1'b1;
end
rstate[AXI_RDDAT_LST]: begin // 6'h08
if (rddata_cmptd & rddata_vld & rddata_rdy)
next_rstate[AXI_RDIDLE] = 1'b1;
else
next_rstate[AXI_RDDAT_LST] = 1'b1;
end
rstate[AXI_RDDAT_WT]: begin // 6'h10
if (rddata_rdy) begin
if (rlast)
next_rstate[AXI_RDDAT_LST] = 1'b1;
else
next_rstate[AXI_RDDAT] = 1'b1;
end
else
next_rstate[AXI_RDDAT_WT] = 1'b1;
end
rstate[AXI_RDTO]: begin // 6'h20
next_rstate[AXI_RDIDLE] = 1'b1;
end
endcase
end
//*****************************************************************************
// Read Address control signals
//*****************************************************************************
always @(posedge aclk)
if (!aresetn)
rd_cntr <= 4'h0;
else if (rstate[AXI_RDDAT_LST] & next_rstate[AXI_RDIDLE])
rd_cntr <= rd_cntr + 4'h1;
always @(posedge aclk)
if (!aresetn)
axi_rvalid <= 1'b0;
else if (rstate[AXI_RDCTL] & next_rstate[AXI_RDDAT])
axi_rvalid <= 1'b0;
else if (rstate[AXI_RDCTL])
axi_rvalid <= 1'b1;
assign axi_rid = rd_cntr;
generate
begin: addr_axi_rd
if (C_AXI_DATA_WIDTH == 256)
assign axi_raddr = {addr_r[C_AXI_ADDR_WIDTH-1:5], 5'b0};
else if (C_AXI_DATA_WIDTH == 128)
assign axi_raddr = {addr_r[C_AXI_ADDR_WIDTH-1:4], 4'b0};
else if (C_AXI_DATA_WIDTH == 64)
assign axi_raddr = {addr_r[C_AXI_ADDR_WIDTH-1:3], 3'b0};
else
assign axi_raddr = {addr_r[C_AXI_ADDR_WIDTH-1:2], 2'b0};
end
endgenerate
assign axi_rlen = blen_r;
assign axi_rburst = {1'b0, wrap_r} + 2'b01;
assign axi_rsize = ctl_r[2:0];
// Not supported and hence assigned zeros
assign axi_rlock = 2'b0;
assign axi_rcache = 4'b0;
assign axi_rprot = 3'b0;
//*****************************************************************************
// Read channel data signals
//*****************************************************************************
always @(posedge aclk)
if (!aresetn)
rddata_vld <= 1'b0;
else if ((rddata_vld & !axi_rd_rvalid & rstate[AXI_RDDAT]) |
(rddata_rdy & rstate[AXI_RDDAT_LST]) |
(rstate[AXI_RDDAT_WT] & next_rstate[AXI_RDDAT] & rddata_ppld) |
(rddata_rdy & axi_rd_rvalid & axi_rd_last) |
rstate[AXI_RDIDLE])
rddata_vld <= 1'b0;
else if ((rstate[AXI_RDDAT] & axi_rd_rvalid & !axi_rd_last) |
((rstate[AXI_RDDAT] | rstate[AXI_RDDAT_WT]) & next_rstate[AXI_RDDAT_LST] & rlast) |
(rstate[AXI_RDDAT_LST] & axi_rd_rvalid & axi_rd_last & axi_rd_rready) |
rstate[AXI_RDTO])
rddata_vld <= 1'b1;
always @(posedge aclk)
if (!aresetn)
rddata_ppld <= 1'b0;
else if (rddata_vld & rddata_rdy)
rddata_ppld <= 1'b0;
else if (!rddata_vld & axi_rd_rvalid & axi_rd_rready & rstate[AXI_RDDAT_WT])
rddata_ppld <= 1'b1;
always @(posedge aclk)
if (!aresetn)
axi_rd_rready <= 1'b0;
else if (rstate[AXI_RDIDLE] |
(rstate[AXI_RDDAT] & next_rstate[AXI_RDDAT_WT]) |
(rstate[AXI_RDDAT_WT] & !next_rstate[AXI_RDDAT] & rddata_ppld) |
(next_rstate[AXI_RDDAT_LST] & (rstate[AXI_RDDAT] | rstate[AXI_RDDAT_WT])))
axi_rd_rready <= 1'b0;
else if ((next_rstate[AXI_RDDAT] & (rstate[AXI_RDCTL] | rstate[AXI_RDDAT_WT])) |
(next_rstate[AXI_RDDAT_LST] & rstate[AXI_RDDAT_WT] & rddata_ppld) |
(rstate[AXI_RDDAT_WT] & !rddata_ppld) |
(rstate[AXI_RDDAT_LST] & axi_rd_rvalid & axi_rd_last))
axi_rd_rready <= 1'b1;
always @(posedge aclk)
if (axi_rd_rvalid)
rddata_p1 <= axi_rd_data;
generate
begin: data_axi_rd
if (C_AXI_NBURST_SUPPORT == 1) begin
end
else begin
always @(posedge aclk)
if (axi_rd_rvalid & !rddata_ppld)
rddata <= axi_rd_data;
else if (rddata_rdy & rddata_vld & rddata_ppld)
rddata <= rddata_p1;
assign rddata_bvld = {{C_AXI_DATA_WIDTH/32}{4'hF}};
end
end
endgenerate
always @(posedge aclk)
if (!aresetn)
rddata_cmptd <= 1'b0;
else if ((next_rstate[AXI_RDIDLE] & rstate[AXI_RDDAT_LST]) |
rstate[AXI_RDIDLE])
rddata_cmptd <= 1'b0;
else if (((rstate[AXI_RDDAT] | rstate[AXI_RDDAT_WT]) & next_rstate[AXI_RDDAT_LST] & rlast) |
(rstate[AXI_RDDAT_LST] & axi_rd_rvalid & axi_rd_last & axi_rd_rready) |
rstate[AXI_RDTO])
rddata_cmptd <= 1'b1;
always @(posedge aclk)
if (rstate[AXI_RDIDLE])
err_resp <= 1'b0;
else if (axi_rd_rvalid & axi_rd_rresp[1])
err_resp <= 1'b1;
always @(posedge aclk)
if (rstate[AXI_RDIDLE] & next_rstate[AXI_RDCTL])
rddata_fsm_sts <= 2'b00;
else if (rstate[AXI_RDCTL] & next_rstate[AXI_RDTO])
rddata_fsm_sts <= 2'b01;
else if (rstate[AXI_RDDAT] & next_rstate[AXI_RDTO])
rddata_fsm_sts <= 2'b10;
always @(posedge aclk)
if (rstate[AXI_RDIDLE] & next_rstate[AXI_RDCTL])
rrid_err <= 1'b0;
else if (axi_rd_rvalid & axi_rd_bid != rd_cntr)
rrid_err <= 1'b1;
always @(posedge aclk)
if (rstate[AXI_RDIDLE])
rd_len_cntr <= 8'h0;
else if (axi_rd_rvalid & axi_rd_rready)
rd_len_cntr <= rd_len_cntr + 8'h01;
assign rddata_sts = {{(RD_STS_WIDTH-12){1'b0}},rd_len_cntr,rddata_fsm_sts,rrid_err,err_resp};
// synthesis translate_off
always @(posedge aclk) begin
if (rd_cmd_timeout)
$display ("ERR: Read timeout occured at time %t", $time);
if (wr_cmd_timeout)
$display ("ERR: Write timeout occured at time %t", $time);
end
// synthesis translate_on
endmodule
|
module sky130_fd_sc_ls__or4 (
X,
A,
B,
C,
D
);
// Module ports
output X;
input A;
input B;
input C;
input D;
// Local signals
wire or0_out_X;
// Name Output Other arguments
or or0 (or0_out_X, D, C, B, A );
buf buf0 (X , or0_out_X );
endmodule
|
module mfp_ahb_lite_eic
(
//ABB-Lite side
input HCLK,
input HRESETn,
input [ 31 : 0 ] HADDR,
input [ 2 : 0 ] HBURST,
input HMASTLOCK, // ignored
input [ 3 : 0 ] HPROT, // ignored
input HSEL,
input [ 2 : 0 ] HSIZE,
input [ 1 : 0 ] HTRANS,
input [ 31 : 0 ] HWDATA,
input HWRITE,
output reg [ 31 : 0 ] HRDATA,
output HREADY,
output HRESP,
input SI_Endian, // ignored
//Interrupt side
input [ `EIC_CHANNELS-1 : 0 ] signal,
//CPU side
output [ 17 : 1 ] EIC_Offset,
output [ 3 : 0 ] EIC_ShadowSet,
output [ 7 : 0 ] EIC_Interrupt,
output [ 5 : 0 ] EIC_Vector,
output EIC_Present,
input EIC_IAck,
input [ 7 : 0 ] EIC_IPL,
input [ 5 : 0 ] EIC_IVN,
input [ 17 : 1 ] EIC_ION
);
assign HRESP = 1'b0;
assign HREADY = 1'b1;
wire [ `EIC_ADDR_WIDTH - 1 : 0 ] read_addr;
wire [ 31 : 0 ] read_data;
reg [ `EIC_ADDR_WIDTH - 1 : 0 ] write_addr;
wire [ 31 : 0 ] write_data;
reg write_enable;
wire [ `EIC_ADDR_WIDTH - 1 : 0 ] ADDR = HADDR [ `EIC_ADDR_WIDTH + 2 : 2 ];
parameter HTRANS_IDLE = 2'b0;
wire NeedRead = HTRANS != HTRANS_IDLE && HSEL;
wire NeedWrite = NeedRead & HWRITE;
assign write_data = HWDATA;
assign read_addr = ADDR;
always @ (posedge HCLK)
if(~HRESETn)
write_enable <= 1'b0;
else begin
if(NeedRead)
HRDATA <= read_data;
if(NeedWrite)
write_addr <= ADDR;
write_enable <= NeedWrite;
end
mfp_eic_core eic_core
(
.CLK ( HCLK ),
.RESETn ( HRESETn ),
.signal ( signal ),
.read_addr ( read_addr ),
.read_data ( read_data ),
.write_addr ( write_addr ),
.write_data ( write_data ),
.write_enable ( write_enable ),
.EIC_Offset ( EIC_Offset ),
.EIC_ShadowSet ( EIC_ShadowSet ),
.EIC_Interrupt ( EIC_Interrupt ),
.EIC_Vector ( EIC_Vector ),
.EIC_Present ( EIC_Present ),
.EIC_IAck ( EIC_IAck ),
.EIC_IPL ( EIC_IPL ),
.EIC_IVN ( EIC_IVN ),
.EIC_ION ( EIC_ION )
);
endmodule
|
module drawEnemy(
input clk,
input wire [9:0] characterPositionX,
input wire [8:0] characterPositionY,
input wire [9:0] drawingPositionX,
input wire [8:0] drawingPositionY,
output reg [2:0] rgb
);
reg [9:0] x;
reg [9:0] y;
initial begin
x = 'd0;
y = 'd0;
end
always @(posedge clk) begin
x <= (drawingPositionX - characterPositionX + 16);
y <= (drawingPositionY - characterPositionY + 16);
if(x==4 && y==1) begin rgb <= 3'b001; end
else if(x==5 && y==1) begin rgb <= 3'b001; end
else if(x==6 && y==1) begin rgb <= 3'b001; end
else if(x==7 && y==1) begin rgb <= 3'b001; end
else if(x==20 && y==1) begin rgb <= 3'b001; end
else if(x==21 && y==1) begin rgb <= 3'b001; end
else if(x==22 && y==1) begin rgb <= 3'b001; end
else if(x==4 && y==2) begin rgb <= 3'b001; end
else if(x==5 && y==2) begin rgb <= 3'b001; end
else if(x==6 && y==2) begin rgb <= 3'b001; end
else if(x==7 && y==2) begin rgb <= 3'b001; end
else if(x==8 && y==2) begin rgb <= 3'b001; end
else if(x==18 && y==2) begin rgb <= 3'b001; end
else if(x==19 && y==2) begin rgb <= 3'b001; end
else if(x==20 && y==2) begin rgb <= 3'b001; end
else if(x==21 && y==2) begin rgb <= 3'b001; end
else if(x==22 && y==2) begin rgb <= 3'b001; end
else if(x==4 && y==3) begin rgb <= 3'b001; end
else if(x==5 && y==3) begin rgb <= 3'b001; end
else if(x==6 && y==3) begin rgb <= 3'b001; end
else if(x==7 && y==3) begin rgb <= 3'b001; end
else if(x==8 && y==3) begin rgb <= 3'b001; end
else if(x==9 && y==3) begin rgb <= 3'b101; end
else if(x==10 && y==3) begin rgb <= 3'b101; end
else if(x==11 && y==3) begin rgb <= 3'b101; end
else if(x==12 && y==3) begin rgb <= 3'b101; end
else if(x==13 && y==3) begin rgb <= 3'b101; end
else if(x==14 && y==3) begin rgb <= 3'b101; end
else if(x==15 && y==3) begin rgb <= 3'b101; end
else if(x==16 && y==3) begin rgb <= 3'b101; end
else if(x==17 && y==3) begin rgb <= 3'b001; end
else if(x==18 && y==3) begin rgb <= 3'b001; end
else if(x==19 && y==3) begin rgb <= 3'b001; end
else if(x==20 && y==3) begin rgb <= 3'b001; end
else if(x==21 && y==3) begin rgb <= 3'b001; end
else if(x==22 && y==3) begin rgb <= 3'b001; end
else if(x==4 && y==4) begin rgb <= 3'b001; end
else if(x==5 && y==4) begin rgb <= 3'b001; end
else if(x==6 && y==4) begin rgb <= 3'b101; end
else if(x==7 && y==4) begin rgb <= 3'b101; end
else if(x==8 && y==4) begin rgb <= 3'b101; end
else if(x==9 && y==4) begin rgb <= 3'b101; end
else if(x==10 && y==4) begin rgb <= 3'b101; end
else if(x==11 && y==4) begin rgb <= 3'b101; end
else if(x==12 && y==4) begin rgb <= 3'b101; end
else if(x==13 && y==4) begin rgb <= 3'b101; end
else if(x==14 && y==4) begin rgb <= 3'b101; end
else if(x==15 && y==4) begin rgb <= 3'b101; end
else if(x==16 && y==4) begin rgb <= 3'b001; end
else if(x==17 && y==4) begin rgb <= 3'b001; end
else if(x==18 && y==4) begin rgb <= 3'b001; end
else if(x==19 && y==4) begin rgb <= 3'b001; end
else if(x==20 && y==4) begin rgb <= 3'b001; end
else if(x==21 && y==4) begin rgb <= 3'b001; end
else if(x==22 && y==4) begin rgb <= 3'b001; end
else if(x==4 && y==5) begin rgb <= 3'b001; end
else if(x==5 && y==5) begin rgb <= 3'b101; end
else if(x==6 && y==5) begin rgb <= 3'b101; end
else if(x==7 && y==5) begin rgb <= 3'b101; end
else if(x==8 && y==5) begin rgb <= 3'b101; end
else if(x==9 && y==5) begin rgb <= 3'b101; end
else if(x==10 && y==5) begin rgb <= 3'b101; end
else if(x==11 && y==5) begin rgb <= 3'b101; end
else if(x==12 && y==5) begin rgb <= 3'b101; end
else if(x==13 && y==5) begin rgb <= 3'b101; end
else if(x==14 && y==5) begin rgb <= 3'b101; end
else if(x==15 && y==5) begin rgb <= 3'b101; end
else if(x==16 && y==5) begin rgb <= 3'b001; end
else if(x==17 && y==5) begin rgb <= 3'b001; end
else if(x==18 && y==5) begin rgb <= 3'b001; end
else if(x==19 && y==5) begin rgb <= 3'b001; end
else if(x==20 && y==5) begin rgb <= 3'b001; end
else if(x==21 && y==5) begin rgb <= 3'b001; end
else if(x==22 && y==5) begin rgb <= 3'b001; end
else if(x==4 && y==6) begin rgb <= 3'b101; end
else if(x==5 && y==6) begin rgb <= 3'b101; end
else if(x==6 && y==6) begin rgb <= 3'b101; end
else if(x==7 && y==6) begin rgb <= 3'b101; end
else if(x==8 && y==6) begin rgb <= 3'b101; end
else if(x==9 && y==6) begin rgb <= 3'b101; end
else if(x==10 && y==6) begin rgb <= 3'b101; end
else if(x==11 && y==6) begin rgb <= 3'b101; end
else if(x==12 && y==6) begin rgb <= 3'b101; end
else if(x==13 && y==6) begin rgb <= 3'b101; end
else if(x==14 && y==6) begin rgb <= 3'b101; end
else if(x==15 && y==6) begin rgb <= 3'b101; end
else if(x==16 && y==6) begin rgb <= 3'b101; end
else if(x==17 && y==6) begin rgb <= 3'b001; end
else if(x==18 && y==6) begin rgb <= 3'b001; end
else if(x==19 && y==6) begin rgb <= 3'b001; end
else if(x==20 && y==6) begin rgb <= 3'b001; end
else if(x==21 && y==6) begin rgb <= 3'b001; end
else if(x==22 && y==6) begin rgb <= 3'b001; end
else if(x==4 && y==7) begin rgb <= 3'b101; end
else if(x==5 && y==7) begin rgb <= 3'b101; end
else if(x==6 && y==7) begin rgb <= 3'b101; end
else if(x==7 && y==7) begin rgb <= 3'b101; end
else if(x==8 && y==7) begin rgb <= 3'b101; end
else if(x==9 && y==7) begin rgb <= 3'b101; end
else if(x==10 && y==7) begin rgb <= 3'b101; end
else if(x==11 && y==7) begin rgb <= 3'b101; end
else if(x==12 && y==7) begin rgb <= 3'b101; end
else if(x==13 && y==7) begin rgb <= 3'b101; end
else if(x==14 && y==7) begin rgb <= 3'b101; end
else if(x==15 && y==7) begin rgb <= 3'b101; end
else if(x==16 && y==7) begin rgb <= 3'b101; end
else if(x==17 && y==7) begin rgb <= 3'b101; end
else if(x==18 && y==7) begin rgb <= 3'b101; end
else if(x==19 && y==7) begin rgb <= 3'b001; end
else if(x==20 && y==7) begin rgb <= 3'b001; end
else if(x==21 && y==7) begin rgb <= 3'b001; end
else if(x==22 && y==7) begin rgb <= 3'b001; end
else if(x==3 && y==8) begin rgb <= 3'b101; end
else if(x==4 && y==8) begin rgb <= 3'b101; end
else if(x==5 && y==8) begin rgb <= 3'b101; end
else if(x==6 && y==8) begin rgb <= 3'b101; end
else if(x==7 && y==8) begin rgb <= 3'b101; end
else if(x==8 && y==8) begin rgb <= 3'b101; end
else if(x==9 && y==8) begin rgb <= 3'b101; end
else if(x==10 && y==8) begin rgb <= 3'b101; end
else if(x==11 && y==8) begin rgb <= 3'b101; end
else if(x==12 && y==8) begin rgb <= 3'b101; end
else if(x==13 && y==8) begin rgb <= 3'b101; end
else if(x==14 && y==8) begin rgb <= 3'b101; end
else if(x==15 && y==8) begin rgb <= 3'b101; end
else if(x==16 && y==8) begin rgb <= 3'b101; end
else if(x==17 && y==8) begin rgb <= 3'b101; end
else if(x==18 && y==8) begin rgb <= 3'b101; end
else if(x==19 && y==8) begin rgb <= 3'b101; end
else if(x==20 && y==8) begin rgb <= 3'b101; end
else if(x==21 && y==8) begin rgb <= 3'b101; end
else if(x==22 && y==8) begin rgb <= 3'b101; end
else if(x==3 && y==9) begin rgb <= 3'b101; end
else if(x==4 && y==9) begin rgb <= 3'b101; end
else if(x==5 && y==9) begin rgb <= 3'b101; end
else if(x==6 && y==9) begin rgb <= 3'b101; end
else if(x==7 && y==9) begin rgb <= 3'b101; end
else if(x==8 && y==9) begin rgb <= 3'b101; end
else if(x==9 && y==9) begin rgb <= 3'b101; end
else if(x==10 && y==9) begin rgb <= 3'b101; end
else if(x==11 && y==9) begin rgb <= 3'b101; end
else if(x==12 && y==9) begin rgb <= 3'b101; end
else if(x==13 && y==9) begin rgb <= 3'b101; end
else if(x==14 && y==9) begin rgb <= 3'b101; end
else if(x==15 && y==9) begin rgb <= 3'b101; end
else if(x==16 && y==9) begin rgb <= 3'b101; end
else if(x==17 && y==9) begin rgb <= 3'b101; end
else if(x==18 && y==9) begin rgb <= 3'b101; end
else if(x==19 && y==9) begin rgb <= 3'b101; end
else if(x==20 && y==9) begin rgb <= 3'b101; end
else if(x==21 && y==9) begin rgb <= 3'b101; end
else if(x==22 && y==9) begin rgb <= 3'b101; end
else if(x==29 && y==9) begin rgb <= 3'b001; end
else if(x==3 && y==10) begin rgb <= 3'b101; end
else if(x==4 && y==10) begin rgb <= 3'b101; end
else if(x==5 && y==10) begin rgb <= 3'b101; end
else if(x==6 && y==10) begin rgb <= 3'b111; end
else if(x==7 && y==10) begin rgb <= 3'b101; end
else if(x==8 && y==10) begin rgb <= 3'b101; end
else if(x==9 && y==10) begin rgb <= 3'b101; end
else if(x==10 && y==10) begin rgb <= 3'b101; end
else if(x==11 && y==10) begin rgb <= 3'b101; end
else if(x==12 && y==10) begin rgb <= 3'b101; end
else if(x==13 && y==10) begin rgb <= 3'b101; end
else if(x==14 && y==10) begin rgb <= 3'b111; end
else if(x==15 && y==10) begin rgb <= 3'b101; end
else if(x==16 && y==10) begin rgb <= 3'b101; end
else if(x==17 && y==10) begin rgb <= 3'b101; end
else if(x==18 && y==10) begin rgb <= 3'b101; end
else if(x==19 && y==10) begin rgb <= 3'b101; end
else if(x==20 && y==10) begin rgb <= 3'b101; end
else if(x==21 && y==10) begin rgb <= 3'b101; end
else if(x==22 && y==10) begin rgb <= 3'b101; end
else if(x==28 && y==10) begin rgb <= 3'b001; end
else if(x==29 && y==10) begin rgb <= 3'b001; end
else if(x==3 && y==11) begin rgb <= 3'b101; end
else if(x==4 && y==11) begin rgb <= 3'b101; end
else if(x==5 && y==11) begin rgb <= 3'b111; end
else if(x==7 && y==11) begin rgb <= 3'b111; end
else if(x==8 && y==11) begin rgb <= 3'b101; end
else if(x==9 && y==11) begin rgb <= 3'b101; end
else if(x==10 && y==11) begin rgb <= 3'b101; end
else if(x==11 && y==11) begin rgb <= 3'b101; end
else if(x==12 && y==11) begin rgb <= 3'b101; end
else if(x==13 && y==11) begin rgb <= 3'b111; end
else if(x==15 && y==11) begin rgb <= 3'b111; end
else if(x==16 && y==11) begin rgb <= 3'b101; end
else if(x==17 && y==11) begin rgb <= 3'b101; end
else if(x==18 && y==11) begin rgb <= 3'b101; end
else if(x==19 && y==11) begin rgb <= 3'b101; end
else if(x==20 && y==11) begin rgb <= 3'b101; end
else if(x==21 && y==11) begin rgb <= 3'b101; end
else if(x==22 && y==11) begin rgb <= 3'b101; end
else if(x==26 && y==11) begin rgb <= 3'b001; end
else if(x==27 && y==11) begin rgb <= 3'b001; end
else if(x==28 && y==11) begin rgb <= 3'b001; end
else if(x==29 && y==11) begin rgb <= 3'b001; end
else if(x==3 && y==12) begin rgb <= 3'b101; end
else if(x==4 && y==12) begin rgb <= 3'b101; end
else if(x==5 && y==12) begin rgb <= 3'b111; end
else if(x==7 && y==12) begin rgb <= 3'b111; end
else if(x==8 && y==12) begin rgb <= 3'b101; end
else if(x==9 && y==12) begin rgb <= 3'b101; end
else if(x==10 && y==12) begin rgb <= 3'b101; end
else if(x==11 && y==12) begin rgb <= 3'b101; end
else if(x==12 && y==12) begin rgb <= 3'b101; end
else if(x==13 && y==12) begin rgb <= 3'b111; end
else if(x==15 && y==12) begin rgb <= 3'b111; end
else if(x==16 && y==12) begin rgb <= 3'b101; end
else if(x==17 && y==12) begin rgb <= 3'b101; end
else if(x==18 && y==12) begin rgb <= 3'b101; end
else if(x==19 && y==12) begin rgb <= 3'b101; end
else if(x==20 && y==12) begin rgb <= 3'b101; end
else if(x==21 && y==12) begin rgb <= 3'b101; end
else if(x==22 && y==12) begin rgb <= 3'b101; end
else if(x==26 && y==12) begin rgb <= 3'b001; end
else if(x==27 && y==12) begin rgb <= 3'b001; end
else if(x==28 && y==12) begin rgb <= 3'b001; end
else if(x==3 && y==13) begin rgb <= 3'b101; end
else if(x==4 && y==13) begin rgb <= 3'b101; end
else if(x==5 && y==13) begin rgb <= 3'b101; end
else if(x==6 && y==13) begin rgb <= 3'b111; end
else if(x==7 && y==13) begin rgb <= 3'b101; end
else if(x==8 && y==13) begin rgb <= 3'b101; end
else if(x==9 && y==13) begin rgb <= 3'b101; end
else if(x==10 && y==13) begin rgb <= 3'b101; end
else if(x==11 && y==13) begin rgb <= 3'b101; end
else if(x==12 && y==13) begin rgb <= 3'b101; end
else if(x==13 && y==13) begin rgb <= 3'b101; end
else if(x==14 && y==13) begin rgb <= 3'b111; end
else if(x==15 && y==13) begin rgb <= 3'b101; end
else if(x==16 && y==13) begin rgb <= 3'b101; end
else if(x==17 && y==13) begin rgb <= 3'b101; end
else if(x==18 && y==13) begin rgb <= 3'b101; end
else if(x==19 && y==13) begin rgb <= 3'b101; end
else if(x==20 && y==13) begin rgb <= 3'b101; end
else if(x==21 && y==13) begin rgb <= 3'b101; end
else if(x==22 && y==13) begin rgb <= 3'b101; end
else if(x==25 && y==13) begin rgb <= 3'b101; end
else if(x==3 && y==14) begin rgb <= 3'b101; end
else if(x==4 && y==14) begin rgb <= 3'b101; end
else if(x==5 && y==14) begin rgb <= 3'b101; end
else if(x==6 && y==14) begin rgb <= 3'b101; end
else if(x==7 && y==14) begin rgb <= 3'b101; end
else if(x==8 && y==14) begin rgb <= 3'b101; end
else if(x==9 && y==14) begin rgb <= 3'b101; end
else if(x==10 && y==14) begin rgb <= 3'b101; end
else if(x==11 && y==14) begin rgb <= 3'b101; end
else if(x==12 && y==14) begin rgb <= 3'b101; end
else if(x==13 && y==14) begin rgb <= 3'b101; end
else if(x==14 && y==14) begin rgb <= 3'b101; end
else if(x==15 && y==14) begin rgb <= 3'b101; end
else if(x==16 && y==14) begin rgb <= 3'b101; end
else if(x==17 && y==14) begin rgb <= 3'b101; end
else if(x==18 && y==14) begin rgb <= 3'b101; end
else if(x==19 && y==14) begin rgb <= 3'b101; end
else if(x==20 && y==14) begin rgb <= 3'b101; end
else if(x==21 && y==14) begin rgb <= 3'b101; end
else if(x==22 && y==14) begin rgb <= 3'b101; end
else if(x==23 && y==14) begin rgb <= 3'b101; end
else if(x==25 && y==14) begin rgb <= 3'b101; end
else if(x==3 && y==15) begin rgb <= 3'b101; end
else if(x==4 && y==15) begin rgb <= 3'b101; end
else if(x==5 && y==15) begin rgb <= 3'b101; end
else if(x==6 && y==15) begin rgb <= 3'b101; end
else if(x==7 && y==15) begin rgb <= 3'b101; end
else if(x==9 && y==15) begin rgb <= 3'b101; end
else if(x==11 && y==15) begin rgb <= 3'b101; end
else if(x==13 && y==15) begin rgb <= 3'b101; end
else if(x==14 && y==15) begin rgb <= 3'b101; end
else if(x==15 && y==15) begin rgb <= 3'b101; end
else if(x==16 && y==15) begin rgb <= 3'b101; end
else if(x==17 && y==15) begin rgb <= 3'b101; end
else if(x==18 && y==15) begin rgb <= 3'b101; end
else if(x==19 && y==15) begin rgb <= 3'b101; end
else if(x==20 && y==15) begin rgb <= 3'b101; end
else if(x==21 && y==15) begin rgb <= 3'b101; end
else if(x==22 && y==15) begin rgb <= 3'b101; end
else if(x==23 && y==15) begin rgb <= 3'b101; end
else if(x==25 && y==15) begin rgb <= 3'b101; end
else if(x==3 && y==16) begin rgb <= 3'b101; end
else if(x==4 && y==16) begin rgb <= 3'b101; end
else if(x==5 && y==16) begin rgb <= 3'b101; end
else if(x==6 && y==16) begin rgb <= 3'b101; end
else if(x==7 && y==16) begin rgb <= 3'b101; end
else if(x==8 && y==16) begin rgb <= 3'b101; end
else if(x==10 && y==16) begin rgb <= 3'b111; end
else if(x==12 && y==16) begin rgb <= 3'b111; end
else if(x==13 && y==16) begin rgb <= 3'b111; end
else if(x==14 && y==16) begin rgb <= 3'b111; end
else if(x==15 && y==16) begin rgb <= 3'b111; end
else if(x==16 && y==16) begin rgb <= 3'b101; end
else if(x==17 && y==16) begin rgb <= 3'b101; end
else if(x==18 && y==16) begin rgb <= 3'b101; end
else if(x==19 && y==16) begin rgb <= 3'b101; end
else if(x==20 && y==16) begin rgb <= 3'b101; end
else if(x==21 && y==16) begin rgb <= 3'b101; end
else if(x==22 && y==16) begin rgb <= 3'b101; end
else if(x==23 && y==16) begin rgb <= 3'b101; end
else if(x==25 && y==16) begin rgb <= 3'b101; end
else if(x==3 && y==17) begin rgb <= 3'b101; end
else if(x==4 && y==17) begin rgb <= 3'b101; end
else if(x==6 && y==17) begin rgb <= 3'b101; end
else if(x==7 && y==17) begin rgb <= 3'b111; end
else if(x==8 && y==17) begin rgb <= 3'b111; end
else if(x==9 && y==17) begin rgb <= 3'b111; end
else if(x==10 && y==17) begin rgb <= 3'b111; end
else if(x==11 && y==17) begin rgb <= 3'b111; end
else if(x==12 && y==17) begin rgb <= 3'b111; end
else if(x==13 && y==17) begin rgb <= 3'b111; end
else if(x==14 && y==17) begin rgb <= 3'b111; end
else if(x==15 && y==17) begin rgb <= 3'b111; end
else if(x==17 && y==17) begin rgb <= 3'b111; end
else if(x==18 && y==17) begin rgb <= 3'b101; end
else if(x==19 && y==17) begin rgb <= 3'b101; end
else if(x==20 && y==17) begin rgb <= 3'b101; end
else if(x==21 && y==17) begin rgb <= 3'b101; end
else if(x==22 && y==17) begin rgb <= 3'b101; end
else if(x==23 && y==17) begin rgb <= 3'b101; end
else if(x==26 && y==17) begin rgb <= 3'b101; end
else if(x==3 && y==18) begin rgb <= 3'b101; end
else if(x==4 && y==18) begin rgb <= 3'b101; end
else if(x==6 && y==18) begin rgb <= 3'b111; end
else if(x==7 && y==18) begin rgb <= 3'b111; end
else if(x==8 && y==18) begin rgb <= 3'b111; end
else if(x==9 && y==18) begin rgb <= 3'b111; end
else if(x==10 && y==18) begin rgb <= 3'b111; end
else if(x==11 && y==18) begin rgb <= 3'b111; end
else if(x==12 && y==18) begin rgb <= 3'b111; end
else if(x==13 && y==18) begin rgb <= 3'b111; end
else if(x==14 && y==18) begin rgb <= 3'b111; end
else if(x==15 && y==18) begin rgb <= 3'b111; end
else if(x==17 && y==18) begin rgb <= 3'b111; end
else if(x==18 && y==18) begin rgb <= 3'b111; end
else if(x==19 && y==18) begin rgb <= 3'b101; end
else if(x==20 && y==18) begin rgb <= 3'b101; end
else if(x==21 && y==18) begin rgb <= 3'b101; end
else if(x==22 && y==18) begin rgb <= 3'b101; end
else if(x==23 && y==18) begin rgb <= 3'b101; end
else if(x==26 && y==18) begin rgb <= 3'b101; end
else if(x==2 && y==19) begin rgb <= 3'b101; end
else if(x==6 && y==19) begin rgb <= 3'b111; end
else if(x==7 && y==19) begin rgb <= 3'b111; end
else if(x==8 && y==19) begin rgb <= 3'b111; end
else if(x==9 && y==19) begin rgb <= 3'b111; end
else if(x==10 && y==19) begin rgb <= 3'b111; end
else if(x==11 && y==19) begin rgb <= 3'b111; end
else if(x==12 && y==19) begin rgb <= 3'b111; end
else if(x==13 && y==19) begin rgb <= 3'b111; end
else if(x==17 && y==19) begin rgb <= 3'b111; end
else if(x==18 && y==19) begin rgb <= 3'b111; end
else if(x==19 && y==19) begin rgb <= 3'b111; end
else if(x==20 && y==19) begin rgb <= 3'b101; end
else if(x==21 && y==19) begin rgb <= 3'b101; end
else if(x==22 && y==19) begin rgb <= 3'b101; end
else if(x==23 && y==19) begin rgb <= 3'b101; end
else if(x==27 && y==19) begin rgb <= 3'b101; end
else if(x==2 && y==20) begin rgb <= 3'b101; end
else if(x==3 && y==20) begin rgb <= 3'b101; end
else if(x==4 && y==20) begin rgb <= 3'b111; end
else if(x==5 && y==20) begin rgb <= 3'b111; end
else if(x==6 && y==20) begin rgb <= 3'b111; end
else if(x==7 && y==20) begin rgb <= 3'b111; end
else if(x==8 && y==20) begin rgb <= 3'b111; end
else if(x==9 && y==20) begin rgb <= 3'b111; end
else if(x==10 && y==20) begin rgb <= 3'b111; end
else if(x==11 && y==20) begin rgb <= 3'b111; end
else if(x==12 && y==20) begin rgb <= 3'b111; end
else if(x==13 && y==20) begin rgb <= 3'b111; end
else if(x==14 && y==20) begin rgb <= 3'b111; end
else if(x==15 && y==20) begin rgb <= 3'b111; end
else if(x==16 && y==20) begin rgb <= 3'b111; end
else if(x==17 && y==20) begin rgb <= 3'b111; end
else if(x==18 && y==20) begin rgb <= 3'b111; end
else if(x==19 && y==20) begin rgb <= 3'b111; end
else if(x==20 && y==20) begin rgb <= 3'b111; end
else if(x==21 && y==20) begin rgb <= 3'b101; end
else if(x==22 && y==20) begin rgb <= 3'b101; end
else if(x==23 && y==20) begin rgb <= 3'b101; end
else if(x==27 && y==20) begin rgb <= 3'b101; end
else if(x==2 && y==21) begin rgb <= 3'b101; end
else if(x==3 && y==21) begin rgb <= 3'b101; end
else if(x==4 && y==21) begin rgb <= 3'b111; end
else if(x==5 && y==21) begin rgb <= 3'b111; end
else if(x==6 && y==21) begin rgb <= 3'b111; end
else if(x==7 && y==21) begin rgb <= 3'b111; end
else if(x==8 && y==21) begin rgb <= 3'b111; end
else if(x==9 && y==21) begin rgb <= 3'b111; end
else if(x==10 && y==21) begin rgb <= 3'b111; end
else if(x==11 && y==21) begin rgb <= 3'b111; end
else if(x==12 && y==21) begin rgb <= 3'b111; end
else if(x==13 && y==21) begin rgb <= 3'b111; end
else if(x==14 && y==21) begin rgb <= 3'b111; end
else if(x==15 && y==21) begin rgb <= 3'b111; end
else if(x==16 && y==21) begin rgb <= 3'b111; end
else if(x==17 && y==21) begin rgb <= 3'b111; end
else if(x==18 && y==21) begin rgb <= 3'b111; end
else if(x==19 && y==21) begin rgb <= 3'b111; end
else if(x==20 && y==21) begin rgb <= 3'b111; end
else if(x==21 && y==21) begin rgb <= 3'b101; end
else if(x==22 && y==21) begin rgb <= 3'b101; end
else if(x==23 && y==21) begin rgb <= 3'b101; end
else if(x==27 && y==21) begin rgb <= 3'b101; end
else if(x==2 && y==22) begin rgb <= 3'b101; end
else if(x==3 && y==22) begin rgb <= 3'b101; end
else if(x==4 && y==22) begin rgb <= 3'b111; end
else if(x==5 && y==22) begin rgb <= 3'b111; end
else if(x==6 && y==22) begin rgb <= 3'b111; end
else if(x==7 && y==22) begin rgb <= 3'b111; end
else if(x==8 && y==22) begin rgb <= 3'b111; end
else if(x==9 && y==22) begin rgb <= 3'b111; end
else if(x==10 && y==22) begin rgb <= 3'b111; end
else if(x==11 && y==22) begin rgb <= 3'b111; end
else if(x==12 && y==22) begin rgb <= 3'b111; end
else if(x==13 && y==22) begin rgb <= 3'b111; end
else if(x==14 && y==22) begin rgb <= 3'b111; end
else if(x==15 && y==22) begin rgb <= 3'b111; end
else if(x==16 && y==22) begin rgb <= 3'b111; end
else if(x==17 && y==22) begin rgb <= 3'b111; end
else if(x==18 && y==22) begin rgb <= 3'b111; end
else if(x==19 && y==22) begin rgb <= 3'b111; end
else if(x==20 && y==22) begin rgb <= 3'b111; end
else if(x==21 && y==22) begin rgb <= 3'b101; end
else if(x==22 && y==22) begin rgb <= 3'b101; end
else if(x==23 && y==22) begin rgb <= 3'b101; end
else if(x==26 && y==22) begin rgb <= 3'b101; end
else if(x==2 && y==23) begin rgb <= 3'b101; end
else if(x==3 && y==23) begin rgb <= 3'b101; end
else if(x==4 && y==23) begin rgb <= 3'b111; end
else if(x==5 && y==23) begin rgb <= 3'b111; end
else if(x==6 && y==23) begin rgb <= 3'b111; end
else if(x==7 && y==23) begin rgb <= 3'b111; end
else if(x==8 && y==23) begin rgb <= 3'b111; end
else if(x==9 && y==23) begin rgb <= 3'b111; end
else if(x==10 && y==23) begin rgb <= 3'b111; end
else if(x==11 && y==23) begin rgb <= 3'b111; end
else if(x==12 && y==23) begin rgb <= 3'b111; end
else if(x==13 && y==23) begin rgb <= 3'b111; end
else if(x==14 && y==23) begin rgb <= 3'b111; end
else if(x==15 && y==23) begin rgb <= 3'b111; end
else if(x==16 && y==23) begin rgb <= 3'b111; end
else if(x==17 && y==23) begin rgb <= 3'b111; end
else if(x==18 && y==23) begin rgb <= 3'b111; end
else if(x==19 && y==23) begin rgb <= 3'b111; end
else if(x==20 && y==23) begin rgb <= 3'b111; end
else if(x==21 && y==23) begin rgb <= 3'b101; end
else if(x==22 && y==23) begin rgb <= 3'b101; end
else if(x==23 && y==23) begin rgb <= 3'b101; end
else if(x==26 && y==23) begin rgb <= 3'b101; end
else if(x==2 && y==24) begin rgb <= 3'b101; end
else if(x==3 && y==24) begin rgb <= 3'b101; end
else if(x==4 && y==24) begin rgb <= 3'b101; end
else if(x==5 && y==24) begin rgb <= 3'b111; end
else if(x==6 && y==24) begin rgb <= 3'b111; end
else if(x==7 && y==24) begin rgb <= 3'b111; end
else if(x==8 && y==24) begin rgb <= 3'b111; end
else if(x==9 && y==24) begin rgb <= 3'b111; end
else if(x==10 && y==24) begin rgb <= 3'b111; end
else if(x==11 && y==24) begin rgb <= 3'b111; end
else if(x==12 && y==24) begin rgb <= 3'b111; end
else if(x==13 && y==24) begin rgb <= 3'b111; end
else if(x==14 && y==24) begin rgb <= 3'b111; end
else if(x==15 && y==24) begin rgb <= 3'b111; end
else if(x==16 && y==24) begin rgb <= 3'b111; end
else if(x==17 && y==24) begin rgb <= 3'b111; end
else if(x==18 && y==24) begin rgb <= 3'b111; end
else if(x==19 && y==24) begin rgb <= 3'b111; end
else if(x==20 && y==24) begin rgb <= 3'b101; end
else if(x==21 && y==24) begin rgb <= 3'b101; end
else if(x==22 && y==24) begin rgb <= 3'b101; end
else if(x==23 && y==24) begin rgb <= 3'b101; end
else if(x==24 && y==24) begin rgb <= 3'b101; end
else if(x==25 && y==24) begin rgb <= 3'b101; end
else if(x==2 && y==25) begin rgb <= 3'b101; end
else if(x==3 && y==25) begin rgb <= 3'b101; end
else if(x==4 && y==25) begin rgb <= 3'b101; end
else if(x==5 && y==25) begin rgb <= 3'b101; end
else if(x==6 && y==25) begin rgb <= 3'b111; end
else if(x==7 && y==25) begin rgb <= 3'b111; end
else if(x==8 && y==25) begin rgb <= 3'b111; end
else if(x==9 && y==25) begin rgb <= 3'b111; end
else if(x==10 && y==25) begin rgb <= 3'b111; end
else if(x==11 && y==25) begin rgb <= 3'b111; end
else if(x==12 && y==25) begin rgb <= 3'b111; end
else if(x==13 && y==25) begin rgb <= 3'b111; end
else if(x==14 && y==25) begin rgb <= 3'b111; end
else if(x==15 && y==25) begin rgb <= 3'b111; end
else if(x==16 && y==25) begin rgb <= 3'b111; end
else if(x==17 && y==25) begin rgb <= 3'b111; end
else if(x==18 && y==25) begin rgb <= 3'b111; end
else if(x==19 && y==25) begin rgb <= 3'b101; end
else if(x==20 && y==25) begin rgb <= 3'b101; end
else if(x==21 && y==25) begin rgb <= 3'b101; end
else if(x==22 && y==25) begin rgb <= 3'b101; end
else if(x==2 && y==26) begin rgb <= 3'b101; end
else if(x==3 && y==26) begin rgb <= 3'b101; end
else if(x==4 && y==26) begin rgb <= 3'b101; end
else if(x==5 && y==26) begin rgb <= 3'b101; end
else if(x==6 && y==26) begin rgb <= 3'b101; end
else if(x==7 && y==26) begin rgb <= 3'b111; end
else if(x==8 && y==26) begin rgb <= 3'b111; end
else if(x==9 && y==26) begin rgb <= 3'b111; end
else if(x==10 && y==26) begin rgb <= 3'b111; end
else if(x==11 && y==26) begin rgb <= 3'b111; end
else if(x==12 && y==26) begin rgb <= 3'b111; end
else if(x==13 && y==26) begin rgb <= 3'b111; end
else if(x==14 && y==26) begin rgb <= 3'b111; end
else if(x==15 && y==26) begin rgb <= 3'b111; end
else if(x==16 && y==26) begin rgb <= 3'b111; end
else if(x==17 && y==26) begin rgb <= 3'b111; end
else if(x==18 && y==26) begin rgb <= 3'b101; end
else if(x==19 && y==26) begin rgb <= 3'b101; end
else if(x==5 && y==27) begin rgb <= 3'b101; end
else if(x==6 && y==27) begin rgb <= 3'b101; end
else if(x==7 && y==27) begin rgb <= 3'b101; end
else if(x==8 && y==27) begin rgb <= 3'b101; end
else if(x==9 && y==27) begin rgb <= 3'b111; end
else if(x==10 && y==27) begin rgb <= 3'b111; end
else if(x==11 && y==27) begin rgb <= 3'b111; end
else if(x==12 && y==27) begin rgb <= 3'b111; end
else if(x==13 && y==27) begin rgb <= 3'b111; end
else if(x==14 && y==27) begin rgb <= 3'b111; end
else if(x==15 && y==27) begin rgb <= 3'b111; end
else if(x==16 && y==27) begin rgb <= 3'b101; end
else if(x==17 && y==27) begin rgb <= 3'b101; end
else if(x==7 && y==28) begin rgb <= 3'b101; end
else if(x==8 && y==28) begin rgb <= 3'b101; end
else if(x==9 && y==28) begin rgb <= 3'b101; end
else if(x==10 && y==28) begin rgb <= 3'b101; end
else if(x==11 && y==28) begin rgb <= 3'b101; end
else if(x==12 && y==28) begin rgb <= 3'b101; end
else if(x==13 && y==28) begin rgb <= 3'b101; end
else if(x==14 && y==28) begin rgb <= 3'b101; end
else if(x==15 && y==28) begin rgb <= 3'b101; end
else begin rgb <= 3'b000; end// Width: 30, Height: 30 From: C:/Users/ITPCC/OneDrive/Documents/CPE223/Gun/pink_beam.png
end
endmodule
|
module uart_sync_flops
(
// internal signals
rst_i,
clk_i,
stage1_rst_i,
stage1_clk_en_i,
async_dat_i,
sync_dat_o
);
parameter Tp = 1;
parameter width = 1;
parameter init_value = 1'b0;
input rst_i; // reset input
input clk_i; // clock input
input stage1_rst_i; // synchronous reset for stage 1 FF
input stage1_clk_en_i; // synchronous clock enable for stage 1 FF
input [width-1:0] async_dat_i; // asynchronous data input
output [width-1:0] sync_dat_o; // synchronous data output
//
// Interal signal declarations
//
reg [width-1:0] sync_dat_o;
reg [width-1:0] flop_0;
// first stage
always @ (posedge clk_i or posedge rst_i)
begin
if (rst_i)
flop_0 <= #Tp {width{init_value}};
else
flop_0 <= #Tp async_dat_i;
end
// second stage
always @ (posedge clk_i or posedge rst_i)
begin
if (rst_i)
sync_dat_o <= #Tp {width{init_value}};
else if (stage1_rst_i)
sync_dat_o <= #Tp {width{init_value}};
else if (stage1_clk_en_i)
sync_dat_o <= #Tp flop_0;
end
endmodule
|
module spi_slave #(
parameter WORDSIZE = 8, /* Size of SPI word. Can be anything from 1 to 32. */
parameter CPOL = 0, /* SPI clock polarity. Can be 0 or 1. */
parameter CPHA = 0, /* SPI clock phase. Can be 0 or 1. */
parameter MSB_FIRST = 1, /* MSB transmit first enable. Can be 0 or 1. */
) (
input clk, /* clock */
input mosi, /* SPI bus MOSI signal */
output miso, /* SPI bus MISO signal */
input sck, /* SPI bus clock signal */
input ss, /* SPI bus slave select signal */
output rx_irq, /* Receive interrupt */
output [WORDSIZE - 1 : 0] rx_data, /* Received data */
input [WORDSIZE - 1 : 0] tx_data, /* Transmit data */
);
/* Synchronized input signals. */
wire mosi_s;
wire sck_rising_s;
wire sck_falling_s;
wire ss_s;
sync_signal sync_mosi(.clk(clk), .in(mosi), .out(mosi_s));
sync_signal sync_sck(.clk(clk), .in(sck), .rising(sck_rising_s), .falling(sck_falling_s));
sync_signal sync_ss(.clk(clk), .in(ss), .out(ss_s));
/* SCK sample and setup edges. */
wire sck_sample_edge;
wire sck_setup_edge;
assign sck_sample_edge = (CPOL ^ CPHA) ? sck_falling_s : sck_rising_s;
assign sck_setup_edge = (CPOL ^ CPHA) ? sck_rising_s : sck_falling_s;
/* Output buffers. */
reg miso_r;
reg rx_irq_r;
reg [WORDSIZE - 1 : 0] rx_data_r;
assign miso = miso_r;
assign rx_irq = rx_irq_r;
assign rx_data = rx_data_r;
/* Receive and transmit shift registers. */
reg [WORDSIZE - 1 : 0] rx_shiftreg;
reg [WORDSIZE - 1 : 0] tx_shiftreg;
reg [5:0] bit_count;
initial begin
bit_count <= 0;
rx_shiftreg <= 0;
tx_shiftreg <= 0;
miso_r <= 0;
rx_irq_r <= 0;
rx_data_r <= 0;
end
always @(posedge clk) begin
/* Check if slave select is not active */
if (ss_s) begin
bit_count <= 0;
rx_shiftreg <= 0;
tx_shiftreg <= 0;
miso_r <= 0;
rx_irq_r <= 0;
/* Check if slave select is active */
end else begin
/* Check if we are at the start of a word. */
if (bit_count == 0) begin
if (CPHA) begin
/* Reload the TX shift register. */
tx_shiftreg <= tx_data;
miso_r <= 0;
end else begin
/* Reload the TX shift register and
* put the first bit onto the bus. */
if (MSB_FIRST) begin
tx_shiftreg <= tx_data << 1;
miso_r <= tx_data[WORDSIZE - 1];
end else begin
tx_shiftreg <= tx_data >> 1;
miso_r <= tx_data[0];
end
end
/* Check if we are at a setup edge of SCK. */
end else if (sck_setup_edge) begin
/* Put the next bit onto the bus. */
if (MSB_FIRST) begin
miso_r <= tx_shiftreg[WORDSIZE - 1];
tx_shiftreg <= tx_shiftreg << 1;
end else begin
miso_r <= tx_shiftreg[0];
tx_shiftreg <= tx_shiftreg >> 1;
end
end
/* Check if we are at a sample edge of SCK. */
if (sck_sample_edge && (bit_count < WORDSIZE)) begin
/* Get the next bit from the bus. */
if (MSB_FIRST) begin
rx_shiftreg <= rx_shiftreg << 1;
rx_shiftreg[0] <= mosi_s;
end else begin
rx_shiftreg <= rx_shiftreg >> 1;
rx_shiftreg[WORDSIZE - 1] <= mosi_s;
end
bit_count <= bit_count + 1;
end
/* If we received a full word, trigger the RX interrupt. */
if (bit_count >= WORDSIZE) begin
bit_count <= 0;
rx_data_r <= rx_shiftreg;
rx_irq_r <= 1;
end else begin
rx_irq_r <= 0;
end
end
end
endmodule
|
module rx_DS_char_tb();
reg rxClk, rxReset, dv;
reg [1:0] d;
wire [7:0] q;
wire nchar, lchar;
wire parityError;
rx_DS_char charDecoder(
.rxClk(rxClk),
.rxReset(rxReset),
.d(d),
.dValid(dv),
.q(q),
.nchar(nchar),
.lchar(lchar),
.parityError(parityError)
);
always begin
#10; rxClk = ~rxClk;
end
task bitPair;
input [1:0] pair;
begin
{dv, d} <= {1'b1, pair};
#20;
{dv, d} <= {1'b0, pair};
#20;
end
endtask
task nch;
input oddp;
input [7:0] chr;
begin
bitPair({1'b0, oddp});
bitPair(chr[1:0]);
bitPair(chr[3:2]);
bitPair(chr[5:4]);
bitPair(chr[7:6]);
end
endtask
task lch;
input oddp;
input [1:0] chr;
begin
bitPair({1'b1, oddp});
bitPair(chr);
end
endtask
task null;
input oddp;
begin
lch(oddp, 2'b11);
lch(0, 0);
end
endtask
initial begin
$dumpfile("wtf.vcd");
$dumpvars;
{rxClk, rxReset, dv, d} <= 0;
#10;
rxReset <= 1;
#20;
rxReset <= 0;
#20;
null(0);
null(0);
nch(1, 8'h41);
lch(0, 2);
null(1);
null(0);
nch(1, 8'h4F);
lch(1, 2);
lch(1, 3); // NULL character with parity error.
lch(1, 0); // This result in parityError being asserted.
null(1);
null(0);
nch(1, 8'h41);
nch(1, 8'h62);
nch(0, 8'h63);
nch(1, 8'h64);
lch(1, 2);
null(1);
null(0);
$display("@I Done.");
$stop;
end
endmodule
|
module lsu_excpctl ( /*AUTOARG*/
// Outputs
so, lsu_exu_st_dtlb_perr_g, lsu_ffu_st_dtlb_perr_g,
lsu_defr_trp_taken_g, lsu_tlu_defr_trp_taken_g,
lsu_mmu_defr_trp_taken_g, lsu_st_dtlb_perr_g,
lsu_dmmu_sfsr_trp_wr, lsu_dsfsr_din_g, lsu_tlb_perr_ld_rq_kill_w,
lsu_spu_early_flush_g, lsu_local_early_flush_g,
lsu_tlu_early_flush_w, lsu_tlu_early_flush2_w, lsu_ttype_vld_m2,
lsu_ttype_vld_m2_bf1, lsu_ifu_flush_pipe_w, lsu_exu_flush_pipe_w,
lsu_mmu_flush_pipe_w, lsu_ffu_flush_pipe_w, lsu_tlu_wtchpt_trp_g,
lsu_tlu_dmmu_miss_g, lsu_tlu_misalign_addr_ldst_atm_m,
lsu_tlu_daccess_excptn_g, lsu_tlu_daccess_prot_g,
lsu_tlu_priv_action_g, lsu_ifu_tlb_data_su, lsu_ifu_tlb_data_ue,
lsu_ifu_tlb_tag_ue, lsu_tlu_ttype_m2, lsu_tlu_ttype_vld_m2,
stb_cam_sqsh_msk, stb_cam_hit_bf, stb_cam_hit_bf1,
tte_data_perror_unc, asi_tte_data_perror, asi_tte_tag_perror,
// Inputs
rclk, si, se, grst_l, arst_l, tlb_rd_tte_data_ebit,
tlb_rd_tte_data_pbit, tlb_rd_tte_data_nfobit,
tlb_rd_tte_data_wbit, tlb_cam_hit, tlb_pgnum_b39,
lsu_ldst_va_b39_m, lsu_sun4r_va_m_l, lsu_sun4r_pgsz_b2t0_e,
lsu_sun4v_pgsz_b2t0_e, tlu_early_flush_pipe_w, ifu_lsu_flush_w,
ifu_lsu_nceen, lsu_tlb_asi_data_perr_g, lsu_tlb_asi_tag_perr_g,
stb_state_vld0, stb_state_vld1, stb_state_vld2, stb_state_vld3,
ifu_tlu_thrid_e, tlu_lsu_priv_trap_m, tlu_lsu_pstate_priv,
st_inst_vld_e, ld_inst_vld_e, ifu_lsu_alt_space_e, lsu_ldst_va_m,
hpv_priv_m, hpstate_en_m, stb_cam_hit, dtlb_bypass_m,
lsu_alt_space_m, atomic_m, ldst_dbl_m, fp_ldst_m, lda_internal_m,
sta_internal_m, cam_real_m, data_rd_vld_g, tag_rd_vld_g,
ldst_sz_m, asi_internal_m, rd_only_ltlb_asi_e, wr_only_ltlb_asi_e,
dfill_tlb_asi_e, ifill_tlb_asi_e, nofault_asi_m, as_if_user_asi_m,
atomic_asi_m, phy_use_ec_asi_m, phy_byp_ec_asi_m, quad_asi_m,
binit_quad_asi_m, blk_asi_m, recognized_asi_m, strm_asi_m,
mmu_rd_only_asi_m, rd_only_asi_m, wr_only_asi_m, unimp_asi_m,
lsu_nonalt_nucl_access_m, va_wtchpt_cmp_en_m,
lsu_va_match_b47_b32_m, lsu_va_match_b31_b3_m,
va_wtchpt_msk_match_m, ifu_tlu_inst_vld_m,
exu_tlu_misalign_addr_jmpl_rtn_m, exu_tlu_va_oor_m,
tlu_dsfsr_flt_vld, tlu_lsu_pstate_cle, tlu_lsu_pstate_am,
lsu_excpctl_asi_state_m, lsu_tlu_nonalt_ldst_m,
lsu_squash_va_oor_m, lsu_tlu_xslating_ldst_m, lsu_tlu_ctxt_sel_m,
lsu_tlu_write_op_m, lsu_memref_m, lsu_flsh_inst_m,
tte_data_parity_error, tte_tag_parity_error
);
input rclk;
input si;
input se;
input grst_l;
input arst_l;
output so;
//=================================================================
// input from tlb
// input [`STLB_DATA_NFO:`STLB_DATA_W] tlb_rd_tte_data ; // tte data from tlb
input tlb_rd_tte_data_ebit;
input tlb_rd_tte_data_pbit;
input tlb_rd_tte_data_nfobit;
input tlb_rd_tte_data_wbit;
input tlb_cam_hit;
input tlb_pgnum_b39;
// input tlb_rd_tte_data_locked ; // lock bit from tte
//=================================================================
input lsu_ldst_va_b39_m ;
input lsu_sun4r_va_m_l ;
input [2:0] lsu_sun4r_pgsz_b2t0_e ;
input [2:0] lsu_sun4v_pgsz_b2t0_e ;
input tlu_early_flush_pipe_w;
input ifu_lsu_flush_w;
input [3:0] ifu_lsu_nceen ; // uncorrectible error enable
input lsu_tlb_asi_data_perr_g ;
input lsu_tlb_asi_tag_perr_g ;
input [7:0] stb_state_vld0 ; // valid bits - stb0
input [7:0] stb_state_vld1 ; // valid bits - stb1
input [7:0] stb_state_vld2 ; // valid bits - stb2
input [7:0] stb_state_vld3 ; // valid bits - stb3
input [1:0] ifu_tlu_thrid_e ; // thread-id.
input tlu_lsu_priv_trap_m ; // daccess-excp in tlu
output lsu_exu_st_dtlb_perr_g ;
output lsu_ffu_st_dtlb_perr_g ;
output lsu_defr_trp_taken_g ;
output lsu_tlu_defr_trp_taken_g ;
output lsu_mmu_defr_trp_taken_g ;
output [3:0] lsu_st_dtlb_perr_g ;
output [3:0] lsu_dmmu_sfsr_trp_wr; // sfsr wr based on trap.
output [23:0] lsu_dsfsr_din_g;
output lsu_tlb_perr_ld_rq_kill_w ;
output lsu_spu_early_flush_g;
output lsu_local_early_flush_g; //to lsu
// output lsu_dctl_early_flush_w;
output lsu_tlu_early_flush_w;
output lsu_tlu_early_flush2_w;
output lsu_ttype_vld_m2;
output lsu_ttype_vld_m2_bf1;
// output lsu_stbctl_flush_pipe_w ;
// output lsu_stbrwctl_flush_pipe_w ;
//output lsu_flush_pipe_w;
output lsu_ifu_flush_pipe_w;
output lsu_exu_flush_pipe_w;
output lsu_mmu_flush_pipe_w;
output lsu_ffu_flush_pipe_w;
output lsu_tlu_wtchpt_trp_g ; // watchpt trap has occurred.
output lsu_tlu_dmmu_miss_g;
output lsu_tlu_misalign_addr_ldst_atm_m ; // mem_addr unaligned
// output lsu_tlu_priv_violtn_g;
wire lsu_tlu_priv_violtn_g;
output lsu_tlu_daccess_excptn_g;
output lsu_tlu_daccess_prot_g;
output lsu_tlu_priv_action_g;
// output lsu_tlu_tte_ebit_g;
// output lsu_tlu_spec_access_epage_g;
// output lsu_tlu_uncache_atomic_g;
// output lsu_tlu_illegal_asi_action_g;
// output lsu_tlu_flt_ld_nfo_pg_g;
//output lsu_tlu_asi_rd_unc;
output lsu_ifu_tlb_data_su ; // specific to st ue
output lsu_ifu_tlb_data_ue ; // dtlb data asi rd parity error ; now ld ue
output lsu_ifu_tlb_tag_ue ; // dtlb tag asi rd parity error
output [8:0] lsu_tlu_ttype_m2;
output lsu_tlu_ttype_vld_m2;
output [7:0] stb_cam_sqsh_msk ; // squash spurious hits
output stb_cam_hit_bf; // buffered stb_cam_hit for qctl1.
output stb_cam_hit_bf1; // buffered stb_cam_hit for stb_rwctl, dctl.
input [3:0] tlu_lsu_pstate_priv ;
// input [3:0] tlu_lsu_hpv_priv;
// input [3:0] tlu_lsu_hpstate_en;
input st_inst_vld_e;
input ld_inst_vld_e;
input ifu_lsu_alt_space_e; // alternate space ld/st
//interface between lsu_dctldp
input [7:0] lsu_ldst_va_m;
//interface between lsu_excpctl and lsu_dctl
output tte_data_perror_unc;
//output tte_data_perror_corr;
output asi_tte_data_perror ;
output asi_tte_tag_perror ;
input hpv_priv_m;
input hpstate_en_m;
input stb_cam_hit ;
input dtlb_bypass_m;
input lsu_alt_space_m;
input atomic_m;
// input atomic_g;
input ldst_dbl_m;
input fp_ldst_m;
// input lsu_inst_vld_w;
input lda_internal_m;
input sta_internal_m;
input cam_real_m;
// input va_wtchpt_match;
input data_rd_vld_g;
input tag_rd_vld_g;
input [1:0] ldst_sz_m;
input asi_internal_m;
// input dfill_thread0;
// input dfill_thread1;
// input dfill_thread2;
// input dfill_thread3;
wire ld_inst_vld_unflushed;
wire st_inst_vld_unflushed;
// input flsh_inst_g;
// input unc_err_trap_g;
//asi decode
input rd_only_ltlb_asi_e;
input wr_only_ltlb_asi_e;
input dfill_tlb_asi_e;
input ifill_tlb_asi_e;
input nofault_asi_m;
input as_if_user_asi_m;
input atomic_asi_m;
input phy_use_ec_asi_m;
input phy_byp_ec_asi_m;
// input tlb_byp_asi_m;
input quad_asi_m;
input binit_quad_asi_m;
input blk_asi_m;
// input blk_cmt_asi_m;
input recognized_asi_m;
input strm_asi_m;
input mmu_rd_only_asi_m;
input rd_only_asi_m;
input wr_only_asi_m;
input unimp_asi_m;
input lsu_nonalt_nucl_access_m ;
input va_wtchpt_cmp_en_m; //from dctl
input lsu_va_match_b47_b32_m; //from qdp1
input lsu_va_match_b31_b3_m; //from qdp1
input va_wtchpt_msk_match_m; //from dctldp
input ifu_tlu_inst_vld_m ;
input exu_tlu_misalign_addr_jmpl_rtn_m;// misaligned addr - jmpl or return addr
input exu_tlu_va_oor_m; // ??? - to be used in sfsr
input [3:0] tlu_dsfsr_flt_vld;
input [3:0] tlu_lsu_pstate_cle ; // current little endian
input [3:0] tlu_lsu_pstate_am ; // address mask
input [7:0] lsu_excpctl_asi_state_m ; // ASI State + imm asi
input lsu_tlu_nonalt_ldst_m ; // non-alternate load or store // FORCE
input lsu_squash_va_oor_m ; // squash va_oor for mem-op. // FORCE
input lsu_tlu_xslating_ldst_m ;// xslating ldst,atomic etc // FORCE
input [2:0] lsu_tlu_ctxt_sel_m; // context selected:0-p,1-s,2-n // FORCE
input lsu_tlu_write_op_m; // FORCE
input lsu_memref_m ;
input lsu_flsh_inst_m ;
input tte_data_parity_error ;
input tte_tag_parity_error ;
wire other_flush_pipe_w ;
wire defr_trp_taken ;
wire defr_trp_taken_m, defr_trp_taken_byp, defr_trp_taken_m_din ;
wire tlb_tte_vld_m, tlb_tte_vld_g ;
wire priv_pg_usr_mode_m, priv_pg_usr_mode_g, priv_pg_usr_mode;
wire nfo_pg_nonnfo_asi_m, nfo_pg_nonnfo_asi_g, nfo_pg_nonnfo_asi;
wire spec_access_epage_m, spec_access_epage_g, spec_access_epage ;
wire nonwr_pg_st_access;
//=========================================================================================
// MISCELLANEOUS
//=========================================================================================
wire clk;
assign clk = rclk;
wire reset;
wire dbb_reset_l;
dffrl_async rstff(.din (grst_l),
.q (dbb_reset_l),
.clk (clk), .se(se), .si(), .so(),
.rst_l (arst_l));
assign reset = ~dbb_reset_l ;
bw_u1_buf_30x UZsize_stb_cam_hit_bf1 (.a(stb_cam_hit), .z(stb_cam_hit_bf1)); //to dctl, stb_rwctl
bw_u1_buf_30x UZsize_stb_cam_hit_bf (.a(stb_cam_hit), .z(stb_cam_hit_bf )); //to qctl1
wire ld_inst_vld_m;
wire st_inst_vld_m;
dff_s #(2) inst_vld_stgm (
.din ({ld_inst_vld_e, st_inst_vld_e}),
.q ({ld_inst_vld_m, st_inst_vld_m}),
.clk (clk),
.se (se), .si (), .so ()
);
dff_s #(2) inst_vld_stgg (
.din ({ld_inst_vld_m, st_inst_vld_m}),
.q ({ld_inst_vld_unflushed, st_inst_vld_unflushed}),
.clk (clk),
.se (se), .si (), .so ()
);
wire tlu_priv_trap_g ;
dff_s #(1) tprivtrp_g (
.din (tlu_lsu_priv_trap_m),
.q (tlu_priv_trap_g),
.clk (clk),
.se (se), .si (), .so ()
);
//=========================================================================================
// Thread Staging
//=========================================================================================
wire [1:0] thrid_m, thrid_g ;
dff_s #(2) tid_stgm (
.din (ifu_tlu_thrid_e[1:0]),
.q (thrid_m[1:0]),
.clk (clk),
.se (se), .si (), .so ()
);
wire thread0_m, thread1_m, thread2_m, thread3_m;
assign thread0_m = ~thrid_m[1] & ~thrid_m[0] ;
assign thread1_m = ~thrid_m[1] & thrid_m[0] ;
assign thread2_m = thrid_m[1] & ~thrid_m[0] ;
assign thread3_m = thrid_m[1] & thrid_m[0] ;
wire thread0_g, thread1_g, thread2_g, thread3_g ;
dff_s #(4) tid_stgg (
.din ({thread0_m, thread1_m, thread2_m, thread3_m}),
.q ({thread0_g, thread1_g, thread2_g, thread3_g}),
.clk (clk),
.se (se), .si (), .so ()
);
//=========================================================================================
// INST_VLD_W GENERATION
//=========================================================================================
assign thrid_g[0] = thread1_g | thread3_g ;
assign thrid_g[1] = thread2_g | thread3_g ;
wire flush_w_inst_vld_m ;
wire lsu_inst_vld_w ;
wire lsu_flush_pipe_w;
assign flush_w_inst_vld_m =
ifu_tlu_inst_vld_m &
~(lsu_flush_pipe_w & (thrid_m[1:0] == thrid_g[1:0])) ; // really lsu_flush_pipe_w
dff_s stgw_ivld (
.din (flush_w_inst_vld_m),
.q (lsu_inst_vld_w),
.clk (clk),
.se (se), .si (), .so ()
);
//========================================================================
// Miscellaneous
//========================================================================
// Moved to excpctl from stb_rwctl as excpctl is closer to stb-cam.
mux4ds #(8) stbvld_mx (
.in0 (~stb_state_vld0[7:0]),
.in1 (~stb_state_vld1[7:0]),
.in2 (~stb_state_vld2[7:0]),
.in3 (~stb_state_vld3[7:0]),
.sel0 (thread0_g),
.sel1 (thread1_g),
.sel2 (thread2_g),
.sel3 (thread3_g),
.dout (stb_cam_sqsh_msk[7:0])
);
//========================================================================
// Exception Handling Begin
//========================================================================
//va watch point
wire va_match_g;
wire va_wtchpt_msk_match_g;
wire va_wtchpt_en_m ;
assign va_wtchpt_en_m =
va_wtchpt_cmp_en_m &
(((~asi_internal_m & recognized_asi_m) & lsu_alt_space_m) | ~lsu_alt_space_m) // Bug5226
& (ld_inst_vld_m | st_inst_vld_m) & //bug 3681
~(hpv_priv_m & hpstate_en_m) // ECO 4178
& ~cam_real_m ; // ECO 5470 (TO_2_0)
//bug6480
wire lsu_va_match_m;
wire pstate_am_m ;
assign lsu_va_match_m = ((lsu_va_match_b47_b32_m & lsu_va_match_b31_b3_m) & ~pstate_am_m) |
(lsu_va_match_b31_b3_m & pstate_am_m);
dff_s #(3) stgwtch_g (
.din ({va_wtchpt_en_m,
lsu_va_match_m,
va_wtchpt_msk_match_m}),
.q ({va_wtchpt_en_g,
va_match_g,
va_wtchpt_msk_match_g}),
.clk (clk),
.se (se), .si (), .so ()
);
// These signals will eventually generate exceptions.
wire va_wtchpt_match;
assign va_wtchpt_match =
va_match_g & va_wtchpt_msk_match_g & lsu_inst_vld_w & va_wtchpt_en_g;
assign lsu_tlu_wtchpt_trp_g = va_wtchpt_match ;
// tlb related exceptions/errors
wire tlb_daccess_excptn_e, tlb_daccess_excptn_m ;
wire tlb_daccess_excptn_e_d1;
wire tlb_illgl_pgsz_m ;
assign tlb_daccess_excptn_e =
((rd_only_ltlb_asi_e & st_inst_vld_e) |
(wr_only_ltlb_asi_e & ld_inst_vld_e)) & ifu_lsu_alt_space_e ;
dff_s #(1) tlbex_stgm (
.din ({tlb_daccess_excptn_e}),
.q ({tlb_daccess_excptn_e_d1}),
.clk (clk),
.se (se), .si (), .so ()
);
assign tlb_daccess_excptn_m = tlb_daccess_excptn_e_d1 | tlb_illgl_pgsz_m;
wire pstate_priv_m;
//wire pstate_priv;
mux4ds #(1) pstate_priv_m_mux (
.in0 (tlu_lsu_pstate_priv[0]),
.in1 (tlu_lsu_pstate_priv[1]),
.in2 (tlu_lsu_pstate_priv[2]),
.in3 (tlu_lsu_pstate_priv[3]),
.sel0 (thread0_m),
.sel1 (thread1_m),
.sel2 (thread2_m),
.sel3 (thread3_m),
.dout (pstate_priv_m)
);
//dff #(1) priv_stgg (
// .din (pstate_priv_m),
// .q (pstate_priv),
// .clk (clk),
// .se (se), .si (), .so ()
// );
// privilege violation - priv page accessed in user mode
//timing
//assign priv_pg_usr_mode = // data access exception; TT=h30
// (ld_inst_vld_unflushed | st_inst_vld_unflushed) & ~(pstate_priv | hpv_priv) & tlb_rd_tte_data_pbit ;
//SC2 wire hpv_priv_m;
assign priv_pg_usr_mode_m = (ld_inst_vld_m | st_inst_vld_m) & ~(pstate_priv_m | hpv_priv_m);
dff_s #(1) priv_pg_usr_mode_stgg (
.din (priv_pg_usr_mode_m),
.q (priv_pg_usr_mode_g),
.clk (clk),
.se (se), .si (), .so ()
);
assign priv_pg_usr_mode = priv_pg_usr_mode_g & tlb_rd_tte_data_pbit ;
// protection violation - store to a page that does not have write permission
//timing
//assign nonwr_pg_st_access = // data access protection; TT=h33
// st_inst_vld_unflushed &
// ~tlb_rd_tte_data_wbit & ~lsu_dtlb_bypass_g & tlb_cam_hit_g ;
// //lsu_dtlb_bypass_g) ; // W=1 in bypass mode - In bypass mode this trap will never happen !!!
assign nonwr_pg_st_access = ~tlb_rd_tte_data_wbit & st_inst_vld_unflushed & tlb_tte_vld_g;
wire daccess_prot ;
assign daccess_prot = nonwr_pg_st_access ;
//((~lsu_dtlb_bypass_g & tlb_cam_hit_g) | (tlb_byp_asi_g & lsu_alt_space_g)) ;
// access to a page marked with the nfo with an asi other than nfo asi.
//timing
//assign nfo_pg_nonnfo_asi = // data access exception; TT=h30
// (ld_inst_vld_unflushed | st_inst_vld_unflushed) & // any access
// ((~nofault_asi_g & lsu_alt_space_g) | ~lsu_alt_space_g) // in alternate space or not
// & tlb_rd_tte_data_nfobit ;
assign nfo_pg_nonnfo_asi_m = (ld_inst_vld_m | st_inst_vld_m) &
((~nofault_asi_m & lsu_alt_space_m) | ~lsu_alt_space_m) ;
dff_s #(1) nfo_pg_nonnfo_asi_stgg (
.din (nfo_pg_nonnfo_asi_m),
.q (nfo_pg_nonnfo_asi_g),
.clk (clk),
.se (se), .si (), .so ()
);
assign nfo_pg_nonnfo_asi = nfo_pg_nonnfo_asi_g & tlb_rd_tte_data_nfobit ;
// as_if_usr asi accesses priv page.
//timing
//assign as_if_usr_priv_pg = // data access exception; TT=h30
// (ld_inst_vld_unflushed | st_inst_vld_unflushed) & as_if_user_asi_g & lsu_alt_space_g &
// tlb_rd_tte_data_pbit ;
wire as_if_usr_priv_pg_m, as_if_usr_priv_pg_g, as_if_usr_priv_pg;
assign as_if_usr_priv_pg_m = (ld_inst_vld_m | st_inst_vld_m) & as_if_user_asi_m & lsu_alt_space_m;
dff_s #(1) as_if_usr_priv_pg_stgg (
.din (as_if_usr_priv_pg_m),
.q (as_if_usr_priv_pg_g),
.clk (clk),
.se (se), .si (), .so ()
);
assign as_if_usr_priv_pg = as_if_usr_priv_pg_g & tlb_rd_tte_data_pbit ;
// non-cacheable address - iospace PA[39] = 1
// atomic access to non-cacheable space.
wire atm_access_w_nc, atomic_g;
dff_s #(1) atm_stgg (
.din (atomic_m),
.q (atomic_g),
.clk (clk),
.se (se), .si (), .so ()
);
assign atm_access_w_nc = atomic_g & tlb_pgnum_b39 ; // io space
// atomic inst with unsupported asi.
//timing
//assign atm_access_unsup_asi = atomic_g & ~atomic_asi_g & lsu_alt_space_g ;
wire atm_access_unsup_asi_m, atm_access_unsup_asi;
assign atm_access_unsup_asi_m = atomic_m & ~atomic_asi_m & lsu_alt_space_m;
dff_s #(1) atm_access_unsup_asi_stgg (
.din (atm_access_unsup_asi_m),
.q (atm_access_unsup_asi),
.clk (clk),
.se (se), .si (), .so ()
);
//timing
//assign tlb_tte_vld_g = ~lsu_dtlb_bypass_g & tlb_cam_hit_g ;
wire dmmu_va_oor_m ;
assign tlb_tte_vld_m = ~dtlb_bypass_m & tlb_cam_hit &
~((unimp_asi_m | asi_internal_m | ~recognized_asi_m) &
lsu_alt_space_m) & // Bug 3541,5186
~dmmu_va_oor_m ; // Bug 5070
dff_s #(1) tlb_tte_vld_stgg (
.din (tlb_tte_vld_m),
.q (tlb_tte_vld_g),
.clk (clk),
.se (se), .si (), .so ()
);
wire pg_with_ebit_m, pg_with_ebit_g, pg_with_ebit ;
//timing
//assign pg_with_ebit =
// (tlb_rd_tte_data_ebit & tlb_tte_vld_g) | // tte
// (lsu_dtlb_bypass_g & ~(phy_use_ec_asi_g & lsu_alt_space_g)) | // regular bypass
// (tlb_byp_asi_g & ~phy_use_ec_asi_g & lsu_alt_space_g) ; // phy_byp
assign pg_with_ebit_m =
(dtlb_bypass_m & ~(phy_use_ec_asi_m & lsu_alt_space_m) &
(lsu_ldst_va_b39_m & ~pstate_am_m)) |
// regular bypass // Bug 4296,5050 related.
(dtlb_bypass_m & (phy_byp_ec_asi_m & lsu_alt_space_m)) ; // phy_byp
dff_s #(1) pg_with_ebit_stgg (
.din (pg_with_ebit_m),
.q (pg_with_ebit_g),
.clk (clk),
.se (se), .si (), .so ()
);
assign pg_with_ebit = (tlb_rd_tte_data_ebit & tlb_tte_vld_g) | // tte
pg_with_ebit_g;
//timing
//assign spec_access_epage =
// ((ld_inst_vld_unflushed & nofault_asi_g & lsu_alt_space_g) | // spec load
// flsh_inst_g) & // flush inst
// pg_with_ebit ; // page with side effects
//// tlb_rd_tte_data_ebit ; // page with side effects
assign spec_access_epage_m =
// Bug 5166
((ld_inst_vld_m & ~atomic_m) & nofault_asi_m & lsu_alt_space_m); // spec load
dff_s #(1) spec_access_epage_stgg (
.din (spec_access_epage_m),
.q (spec_access_epage_g),
.clk (clk),
.se (se), .si (), .so ()
);
// remove flsh_inst_g ??
//assign spec_access_epage = (spec_access_epage_g | flsh_inst_g) & pg_with_ebit;
assign spec_access_epage = (spec_access_epage_g) & pg_with_ebit;
wire quad_asi_non_ldstda_m;
// covers regular quad asi AND binit.
assign quad_asi_non_ldstda_m =
quad_asi_m & lsu_alt_space_m &
((~ldst_dbl_m & ld_inst_vld_m) | // only lddbl should use
(fp_ldst_m & (ld_inst_vld_m | st_inst_vld_m))) ; // float should not use
wire true_quad_non_ldda_m ;
// catches case where st or non-ldd uses asi
assign true_quad_non_ldda_m =
(quad_asi_m & ~binit_quad_asi_m) & lsu_alt_space_m &
((~ldst_dbl_m & ld_inst_vld_m) | st_inst_vld_m) ;
wire blk_asi_non_ldstdfa_m ;
assign blk_asi_non_ldstdfa_m = blk_asi_m & lsu_alt_space_m &
~(ldst_dbl_m & fp_ldst_m) & (ld_inst_vld_m | st_inst_vld_m) ;
// trap on illegal asi
wire illegal_asi_trap_m, illegal_asi_trap_g, illegal_asi_trap_m_d1 ;
assign illegal_asi_trap_m =
((ld_inst_vld_m | st_inst_vld_m) & lsu_alt_space_m & ~recognized_asi_m) |
((ld_inst_vld_m | st_inst_vld_m) & asi_internal_m & fp_ldst_m & lsu_alt_space_m) | // Bug 4382
blk_asi_non_ldstdfa_m |
quad_asi_non_ldstda_m |
true_quad_non_ldda_m ;
dff_s #(1) illegal_asi_trap_stgg (
.din (illegal_asi_trap_m),
.q (illegal_asi_trap_m_d1),
.clk (clk),
.se (se), .si (), .so ()
);
//need lsu_inst_vld_w ??
// assign illegal_asi_trap_g = illegal_asi_trap_m_d1 & lsu_inst_vld_w;
assign illegal_asi_trap_g = illegal_asi_trap_m_d1;
wire wr_to_strm_sync_m ;
//timing
//assign wr_to_strm_sync =
// strm_asi & ((ldst_va_g[7:0] == 8'hA0) | (ldst_va_g[7:0] == 8'h68)) &
// st_inst_vld_unflushed & lsu_alt_space_g ;
assign wr_to_strm_sync_m = // Bug 5742
strm_asi_m & (lsu_ldst_va_m[7:0] == 8'hA0) & st_inst_vld_m & lsu_alt_space_m ;
/*dff #(1) wr_to_strm_sync_stgg (
.din (wr_to_strm_sync_m),
.q (wr_to_strm_sync),
.clk (clk),
.se (se), .si (), .so ()
);*/
// HPV Changes
// Push back into previous stage.
// qualification with hpv_priv and hpstate_en required to ensure hypervisor
// is not trying to access.
//SC2 wire hpv_priv_e;
//SC2 mux4ds #(1) hpv_priv_e_mux (
//SC2 .in0 (tlu_lsu_hpv_priv[0]),
//SC2 .in1 (tlu_lsu_hpv_priv[1]),
//SC2 .in2 (tlu_lsu_hpv_priv[2]),
//SC2 .in3 (tlu_lsu_hpv_priv[3]),
//SC2 .sel0 (thread0_e),
//SC2 .sel1 (thread1_e),
//SC2 .sel2 (thread2_e),
//SC2 .sel3 (thread3_e),
//SC2 .dout (hpv_priv_e)
//SC2);
//SC2 wire hpstate_en_e;
//SC2 mux4ds #(1) hpstate_en_e_mux (
//SC2 .in0 (tlu_lsu_hpstate_en[0]),
//SC2 .in1 (tlu_lsu_hpstate_en[1]),
//SC2 .in2 (tlu_lsu_hpstate_en[2]),
//SC2 .in3 (tlu_lsu_hpstate_en[3]),
//SC2 .sel0 (thread0_e),
//SC2 .sel1 (thread1_e),
//SC2 .sel2 (thread2_e),
//SC2 .sel3 (thread3_e),
//SC2 .dout (hpstate_en_e)
//SC2);
//SC2 wire hpstate_en_m;
//SC2 dff #(2) hpv_stgm (
//SC2 .din ({hpv_priv_e, hpstate_en_e}),
//SC2 .q ({hpv_priv_m, hpstate_en_m}),
//SC2 .clk (clk),
//SC2 .se (se), .si (), .so ()
//SC2 );
//SC2 wire hpv_priv, hpstate_en;
//SC2 dff #(2) hpv_stgg (
//SC2 .din ({hpv_priv_m, hpstate_en_m}),
//SC2 .q ({hpv_priv, hpstate_en}),
//SC2 .clk (clk),
//SC2 .se (se), .si (), .so ()
//SC2 );
/*assign priv_action = (ld_inst_vld_unflushed | st_inst_vld_unflushed) & ~lsu_asi_state[7] &
~pstate_priv & ~(hpv_priv & hpstate_en) & lsu_alt_space_g ;*/
// Generate a stage earlier
wire priv_action_m, priv_action;
assign priv_action_m = (ld_inst_vld_m | st_inst_vld_m) &
((~lsu_excpctl_asi_state_m[7] & lsu_alt_space_m) | // alt_space
lsu_nonalt_nucl_access_m) & // non-alt space - nucleus ctxt
~pstate_priv_m & ~(hpv_priv_m & hpstate_en_m) ;
/*assign priv_action_m = (ld_inst_vld_m | st_inst_vld_m) & ~lsu_excpctl_asi_state_m[7] &
~pstate_priv_m & ~(hpv_priv_m & hpstate_en_m) & lsu_alt_space_m ;*/
dff_s pact_stgg (
.din (priv_action_m),
.q (priv_action),
.clk (clk),
.se (se), .si (), .so ()
);
// Take data_access exception if supervisor uses hypervisor asi
wire hpv_asi_range_m;
wire spv_use_hpv_m ;
//timing
//assign hpv_asi_range =
// ~lsu_asi_state[7] & (
// (~lsu_asi_state[6] & lsu_asi_state[5] & lsu_asi_state[4]) | // 0x3?
// ( lsu_asi_state[6]));
assign hpv_asi_range_m =
~lsu_excpctl_asi_state_m[7] & (
(~lsu_excpctl_asi_state_m[6] & lsu_excpctl_asi_state_m[5] & lsu_excpctl_asi_state_m[4]) | // 0x3?
( lsu_excpctl_asi_state_m[6])); // 0x4?,5?,6?,7?
// Take data_access exception if supervisor uses hypervisor asi
assign spv_use_hpv_m = (ld_inst_vld_m | st_inst_vld_m) &
hpv_asi_range_m &
pstate_priv_m & ~hpv_priv_m & lsu_alt_space_m ;
// EARLY TRAPS
// memory address not aligned
wire qw_align_addr,blk_align_addr ;
wire hw_align_addr,wd_align_addr,dw_align_addr;
assign hw_align_addr = ~lsu_ldst_va_m[0] ; // half-word addr
assign wd_align_addr = ~lsu_ldst_va_m[1] & ~lsu_ldst_va_m[0] ; // word addr
assign dw_align_addr = ~lsu_ldst_va_m[2] & ~lsu_ldst_va_m[1] & ~lsu_ldst_va_m[0] ; // dw addr
assign qw_align_addr = ~lsu_ldst_va_m[3] & ~lsu_ldst_va_m[2] & ~lsu_ldst_va_m[1] & ~lsu_ldst_va_m[0] ; // qw addr
assign blk_align_addr =
~lsu_ldst_va_m[5] & ~lsu_ldst_va_m[4] & ~lsu_ldst_va_m[3] &
~lsu_ldst_va_m[2] & ~lsu_ldst_va_m[1] & ~lsu_ldst_va_m[0] ; // 64B aligned addr for block ld/st
wire hw_size,wd_size,dw_size;
//assign byte_size = ~ldst_sz_m[1] & ~ldst_sz_m[0] ; // byte size
assign hw_size = ~ldst_sz_m[1] & ldst_sz_m[0] ; // half-word size
assign wd_size = ldst_sz_m[1] & ~ldst_sz_m[0] ; // word size
assign dw_size = ldst_sz_m[1] & ldst_sz_m[0] ; // double-word size
wire mem_addr_not_align ;
assign mem_addr_not_align
= (((hw_size & ~hw_align_addr) | // half-word check
(wd_size & ~wd_align_addr) | // word check
(dw_size & ~dw_align_addr) | // double word check
//((quad_asi_m | binit_quad_asi_m) & lsu_alt_space_m & ldst_dbl_m & ~qw_align_addr) | // quad word check
(blk_asi_m & lsu_alt_space_m & fp_ldst_m & ldst_dbl_m & ~blk_align_addr)) & // 64B blk ld/st check
//(blk_asi_m & lsu_alt_space_m & blk_asi_m & ~blk_align_addr)) & // 64B blk ld/st check
(ld_inst_vld_m | st_inst_vld_m)) |
// check only for loads
(((quad_asi_m | binit_quad_asi_m) & lsu_alt_space_m & ldst_dbl_m & ~qw_align_addr) & ld_inst_vld_m) ; // quad word check
// To be removed !! Now supported for both ld and st thru unimp_asi.
//wire blkst_cmt_daccess_excp_m ;
//assign blkst_cmt_daccess_excp_m =
// (blk_cmt_asi_m & lsu_alt_space_m & fp_ldst_m & ldst_dbl_m & st_inst_vld_m) ;
wire stdf_maddr_not_align, lddf_maddr_not_align ;
assign stdf_maddr_not_align
= st_inst_vld_m & fp_ldst_m & ldst_dbl_m & wd_align_addr & ~dw_align_addr
& ~((blk_asi_m | quad_asi_m) & lsu_alt_space_m);
assign lddf_maddr_not_align
= ld_inst_vld_m & fp_ldst_m & ldst_dbl_m & wd_align_addr & ~dw_align_addr
& ~((blk_asi_m | quad_asi_m) & lsu_alt_space_m);
// internal asi access by ld/st other than ldxa/stxa/lddfa/stdfa.
wire asi_internal_non_xdw ;
assign asi_internal_non_xdw
= (st_inst_vld_m | ld_inst_vld_m) & lsu_alt_space_m & asi_internal_m &
~(dw_size & (~ldst_dbl_m | fp_ldst_m)) ; //bug4149;
// asi related
// rd-only mmu asi requiring va decode.
wire mmu_rd_only_asi_wva_m ;
assign mmu_rd_only_asi_wva_m =
((lsu_excpctl_asi_state_m[7:0]==8'h58) & (
(lsu_ldst_va_m[7:0] == 8'h00) | // dtag_target
(lsu_ldst_va_m[7:0] == 8'h20))) | // dsync_far
((lsu_excpctl_asi_state_m[7:0]==8'h50) &
(lsu_ldst_va_m[7:0] == 8'h00)) ; // itag_target
wire wr_to_rd_only_asi, rd_of_wr_only_asi, unimp_asi_used;
assign wr_to_rd_only_asi =
((mmu_rd_only_asi_wva_m |// mmu with non-unique asi
mmu_rd_only_asi_m | // mmu with unique asi
rd_only_asi_m) // non mmu
& st_inst_vld_m & lsu_alt_space_m) |
wr_to_strm_sync_m ; // Bug 5399
assign rd_of_wr_only_asi = wr_only_asi_m & ld_inst_vld_m & lsu_alt_space_m ;
assign unimp_asi_used = unimp_asi_m & (ld_inst_vld_m | st_inst_vld_m) & lsu_alt_space_m ;
wire asi_related_trap_m ; // asi_related_trap_g;
assign asi_related_trap_m = wr_to_rd_only_asi | rd_of_wr_only_asi | unimp_asi_used | asi_internal_non_xdw ;
// Illegal page size for tlb fill
wire [2:0] pgszr_m,pgszv_m ;
dff_s #(6) pgsz_stgm (
.din ({lsu_sun4r_pgsz_b2t0_e[2:0],lsu_sun4v_pgsz_b2t0_e[2:0]}),
.q ({pgszr_m[2:0],pgszv_m[2:0]}),
.clk (clk),
.se (se), .si (), .so ()
);
wire [2:0] pgsz_m ;
assign pgsz_m[2:0] = lsu_sun4r_va_m_l ? pgszv_m[2:0] : pgszr_m[2:0] ;
wire illgl_pgsz_m ;
assign illgl_pgsz_m =
(~pgsz_m[2] & pgsz_m[1] & ~pgsz_m[0]) | // 010 ; 512K
( pgsz_m[2] & ~pgsz_m[1] & ~pgsz_m[0]) | // 100 ; 32M
( pgsz_m[2] & pgsz_m[1] & ~pgsz_m[0]) | // 110 ; 2G
( pgsz_m[2] & pgsz_m[1] & pgsz_m[0]) ; // 111 ; 16G
wire ifill_tlb_asi_m,dfill_tlb_asi_m ;
dff_s #(2) idfill_stgm (
.din ({ifill_tlb_asi_e,dfill_tlb_asi_e}),
.q ({ifill_tlb_asi_m,dfill_tlb_asi_m}),
.clk (clk),
.se (se), .si (), .so ()
);
assign tlb_illgl_pgsz_m =
(ifill_tlb_asi_m | dfill_tlb_asi_m) & st_inst_vld_m & lsu_alt_space_m & illgl_pgsz_m ;
wire [8:0] early_ttype_m,early_ttype_g ;
wire early_trap_vld_m, early_trap_vld_g ;
assign early_trap_vld_m =
stdf_maddr_not_align | lddf_maddr_not_align |
mem_addr_not_align ;
wire lsu_tlu_misalign_addr_ldst_atm_m ;
assign lsu_tlu_misalign_addr_ldst_atm_m = early_trap_vld_m ;
// mux select order must be maintained
assign early_ttype_m[8:0] =
stdf_maddr_not_align ? 9'h036 :
lddf_maddr_not_align ? 9'h035 :
mem_addr_not_align ? 9'h034 : 9'hxxx ;
dff_s #(10) etrp_stgg (
.din ({early_ttype_m[8:0],early_trap_vld_m}),
.q ({early_ttype_g[8:0],early_trap_vld_g}),
.clk (clk),
.se (se), .si (), .so ()
);
wire daccess_excptn_early_m, daccess_excptn_early_g ;
wire atm_access_w_nc_byp_m,atm_access_w_nc_byp_g ;
assign atm_access_w_nc_byp_m =
atomic_m & dtlb_bypass_m & (lsu_ldst_va_b39_m & ~pstate_am_m) ;
//Bug 5050
dff_s atmbyp_stgg (
.din (atm_access_w_nc_byp_m),
.q (atm_access_w_nc_byp_g),
.clk (clk),
.se (se), .si (), .so ()
);
assign daccess_excptn_early_m =
asi_related_trap_m | tlb_daccess_excptn_m |
spv_use_hpv_m |
atm_access_w_nc_byp_m ; // Bug 4281.
dff_s #(1) dearly_stgg (
.din (daccess_excptn_early_m),
.q (daccess_excptn_early_g),
.clk (clk),
.se (se), .si (), .so ()
);
wire daccess_excptn;
assign daccess_excptn =
(priv_pg_usr_mode | as_if_usr_priv_pg | nfo_pg_nonnfo_asi |
atm_access_w_nc ) & tlb_tte_vld_g |
illegal_asi_trap_g | daccess_excptn_early_g | atm_access_unsup_asi | //bug4622
spec_access_epage ;
wire [3:0] lsu_nceen_d1;
dff_s #(4) nceen_d1_ff (
.din (ifu_lsu_nceen[3:0]),
.q (lsu_nceen_d1[3:0]),
.clk (clk),
.se (se), .si (), .so ()
);
wire nceen_pipe_g ;
assign nceen_pipe_g =
(thread0_g & lsu_nceen_d1[0]) | (thread1_g & lsu_nceen_d1[1]) |
(thread2_g & lsu_nceen_d1[2]) | (thread3_g & lsu_nceen_d1[3]) ;
// correctible dtlb data parity error on cam will cause dmmu miss.
// prefetch will rely on the ld_inst_vld/st_inst_vld not being asserted
// to prevent mmu_miss from being signalled if prefetch does not translate.
// Timing Change : Remove data perror from dmmu_miss ; to be treated as disrupting trap.
wire dmmu_miss_m, dmmu_miss_m_d1;
assign dmmu_miss_m =
~tlb_cam_hit & ~dtlb_bypass_m &
(ld_inst_vld_m | st_inst_vld_m) &
~(lda_internal_m | sta_internal_m | early_trap_vld_m) ;
dff_s #(1) dmmu_miss_stgg (
.din (dmmu_miss_m),
.q (dmmu_miss_m_d1),
.clk (clk),
.se (se), .si (), .so ()
);
//need lsu_inst_vld_w ??
wire dmmu_miss_g;
assign dmmu_miss_g = dmmu_miss_m_d1 & lsu_inst_vld_w;
wire [8:0] dmiss_type ;
wire cam_real_g;
dff_s #(1) cam_real_stgg (
.din (cam_real_m),
.q (cam_real_g),
.clk (clk),
.se (se), .si (), .so ()
);
assign dmiss_type[8:0] = cam_real_g ? 9'h03f : 9'h068 ;
// two wtchpt matches
//assign lsu_tlu_ttype_m2[8:0] =
// early_trap_vld_g ? early_ttype_g[8:0] :
// priv_action ? 9'h037 :
// va_wtchpt_match ? 9'h062 :
// daccess_excptn ? 9'h030 :
// dmmu_miss_g ? dmiss_type[8:0] : // dmmu_miss
// daccess_error ? 9'h032 :
// daccess_prot ? 9'h06c :
// spubyp_trap_active_g ? {3'b000,spubyp_ttype[5:0]} : // should be no other tttype to compare to.
// 9'bx_xxxx_xxxx ;
wire early_trap_vld_sel, priv_action_sel, va_wtchpt_match_sel, daccess_excptn_sel, dmmu_miss_sel,
daccess_prot_sel ;
// Need to maintain this order in selects. Based on priority of traps
assign early_trap_vld_sel = early_trap_vld_g;
assign priv_action_sel = ~early_trap_vld_sel & priv_action;
assign va_wtchpt_match_sel = ~early_trap_vld_sel & ~priv_action_sel & va_wtchpt_match;
assign daccess_excptn_sel = ~early_trap_vld_sel & ~priv_action_sel & ~va_wtchpt_match_sel &
daccess_excptn;
assign dmmu_miss_sel = ~early_trap_vld_sel & ~priv_action_sel & ~va_wtchpt_match_sel &
~daccess_excptn_sel & dmmu_miss_g;
assign daccess_prot_sel = ~early_trap_vld_sel & ~priv_action_sel & ~va_wtchpt_match_sel &
~daccess_excptn_sel & ~dmmu_miss_sel & daccess_prot;
assign lsu_tlu_ttype_m2[8:0] =
({9{early_trap_vld_sel}} & early_ttype_g[8:0]) |
({9{priv_action_sel}} & 9'h037 ) |
({9{va_wtchpt_match_sel}} & 9'h062 ) |
({9{daccess_excptn_sel}} & 9'h030 ) |
({9{dmmu_miss_sel}} & dmiss_type[8:0] ) |
({9{daccess_prot_sel}} & 9'h06c ) ;
assign lsu_tlu_ttype_vld_m2 = dmmu_miss_g | daccess_excptn | daccess_prot |
priv_action | early_trap_vld_g |
va_wtchpt_match ;
assign lsu_ttype_vld_m2 = lsu_tlu_ttype_vld_m2 | defr_trp_taken ; //to stb_rwctl
assign lsu_ttype_vld_m2_bf1 = lsu_ttype_vld_m2; //to dctl, qctl1
wire squash_priority_g ; // Bug 4678
assign squash_priority_g = priv_action | early_trap_vld_g | va_wtchpt_match ;
assign lsu_tlu_dmmu_miss_g = dmmu_miss_g & ~squash_priority_g ;
assign lsu_tlu_priv_violtn_g = (priv_pg_usr_mode | as_if_usr_priv_pg) & tlb_tte_vld_g ;
wire dmmu_va_oor_g ;
assign lsu_tlu_daccess_excptn_g =
(daccess_excptn | dmmu_va_oor_g // Bug 5036
| tlu_priv_trap_g) & ~squash_priority_g ;
// prioritize daccess_excptn higher than daccess_prot. This may
// be a critical path which needs to be resolved -> qual. now
// in mmu.
//assign lsu_tlu_daccess_prot_g = daccess_prot ;
wire daccess_prot_g;
assign daccess_prot_g = daccess_prot &
~(tlu_priv_trap_g | daccess_excptn | squash_priority_g) ;
assign lsu_tlu_daccess_prot_g = daccess_prot & ~squash_priority_g ; // Bug 5336.
assign lsu_tlu_priv_action_g = priv_action ;
//assign lsu_tlu_tte_ebit_g = tlb_rd_tte_data_ebit & tlb_tte_vld_g ;
wire lsu_tlu_tte_ebit_g;
assign lsu_tlu_tte_ebit_g = pg_with_ebit ;
//assign lsu_tlu_spec_access_epage_g = spec_access_epage & tlb_tte_vld_g ; // page with side effects
wire lsu_tlu_spec_access_epage_g ;
assign lsu_tlu_spec_access_epage_g = spec_access_epage ; // page with side effects
wire lsu_tlu_uncache_atomic_g;
assign lsu_tlu_uncache_atomic_g =
(atm_access_w_nc & tlb_tte_vld_g) |
(atm_access_w_nc_byp_g) ;
// Define illegal asi actions
// see sfsr description - excludes cases where 02 and 04 are set for ftype !!!
wire lsu_tlu_flt_ld_nfo_pg_g;
assign lsu_tlu_flt_ld_nfo_pg_g = nfo_pg_nonnfo_asi & tlb_tte_vld_g ;
wire illgl_asi_action_pre_m,illgl_asi_action_pre_g ;
assign illgl_asi_action_pre_m = asi_related_trap_m | tlb_daccess_excptn_m | illegal_asi_trap_m | spv_use_hpv_m ; // bug 4181; //bug3660
dff_s illglasi_g (
.din (illgl_asi_action_pre_m),
.q (illgl_asi_action_pre_g),
.clk (clk),
.se (se), .si (), .so ()
);
wire lsu_tlu_illegal_asi_action_g;
assign lsu_tlu_illegal_asi_action_g =
atm_access_unsup_asi | (illgl_asi_action_pre_g) & // Bug 4825
~(lsu_tlu_spec_access_epage_g | lsu_tlu_uncache_atomic_g) ;
//(illgl_asi_action_pre_g | (atm_access_unsup_asi)) &
//~(lsu_tlu_spec_access_epage_g | lsu_tlu_uncache_atomic_g) ;
//=========================================================================================
// Generate Flush Pipe
//=========================================================================================
assign other_flush_pipe_w =
tlu_early_flush_pipe_w | (lsu_tlu_ttype_vld_m2 & lsu_inst_vld_w) |
defr_trp_taken ; // deferred trap.
assign lsu_ifu_flush_pipe_w = other_flush_pipe_w ;
assign lsu_exu_flush_pipe_w = other_flush_pipe_w ;
assign lsu_mmu_flush_pipe_w = other_flush_pipe_w ;
assign lsu_ffu_flush_pipe_w = other_flush_pipe_w ;
assign lsu_flush_pipe_w = other_flush_pipe_w | ifu_lsu_flush_w ;
//assign lsu_qctl1_flush_pipe_w = lsu_flush_pipe_w ;
//assign lsu_stbctl_flush_pipe_w = lsu_flush_pipe_w ;
//assign lsu_stbrwctl_flush_pipe_w = lsu_flush_pipe_w ;
//=========================================================================================
// Early Traps to SPU
//=========================================================================================
// detect st to ma/strm sync - data-access exception.
//wire st_to_sync_dexcp_m ;
// qual with alt_space not required - spu will do it.
//assign st_to_sync_dexcp_m = // Bug 5704
//strm_asi_m & ((lsu_ldst_va_m[7:0] == 8'ha0) | (lsu_ldst_va_m[7:0] == 8'h68)) & st_inst_vld_m ;
wire early_flush_m ;
assign early_flush_m =
(atomic_m & lsu_alt_space_m) | // Bug 4650 - alt-space atomics should flush.
priv_action_m |
early_trap_vld_m | // mem-addr-not-aligned.
illegal_asi_trap_m | // for fp non use of internal asi.
//st_to_sync_dexcp_m | // Bug 5742
//wr_to_strm_sync_m | // Bug 5890 - redundant - make room.
defr_trp_taken_m_din | // Bug 5890
daccess_excptn_early_m ;
/*asi_related_trap_m | // Bug 2592
spv_use_hpv_m |
wr_to_strm_sync_m;*/
dff_s eflushspu_g (
.din (early_flush_m),
.q (lsu_spu_early_flush_g),
.clk (clk),
.se (se), .si (), .so ()
);
dff_s eflushspu2_g (
.din (early_flush_m),
.q (lsu_local_early_flush_g),
.clk (clk),
.se (se), .si (), .so ()
);
dff_s eflushtlu_g (
.din (early_flush_m),
.q (lsu_tlu_early_flush_w),
.clk (clk),
.se (se), .si (), .so ()
);
dff_s eflushtlu2_g (
.din (early_flush_m),
.q (lsu_tlu_early_flush2_w),
.clk (clk),
.se (se), .si (), .so ()
);
//=========================================================================================
// Parity Error Checking
//=========================================================================================
// DTLB Parity Errors.
// ASI read of Tag/Data :
// - uncorrectible error
// - logging occurs on read.
// - precise trap is taken when ldxa completes if nceen set.
// - if not set then ldxa is allowed to complete.
// CAM Read of Tag/Data :
// - correctible if locked bit not set.
// - takes disrupting trap later.
// - uncorrectible if locked bit set.
// - both are treated as precise traps.
// - if errors not enabled, then load completes as if hit in L1.
// ** TLB error will cause a trap which will preclude concurrent dcache,dtag **
// ** parity errors. **
// cam related tte data parity error - error assumed correctible if locked
// bit is not set. Will cause a dmmu_miss for correction.
// qualify with cam_hit ??
wire tte_data_perror_unc ;
assign lsu_tlb_perr_ld_rq_kill_w =
//tte_data_perror_corr | (tte_data_perror_unc & nceen_pipe_g) ;
(tte_data_perror_unc & nceen_pipe_g) ;
// correctible dtlb errors no longer supported.
/*assign tte_data_perror_corr =
tte_data_parity_error & ~tlb_rd_tte_data_locked & tlb_tte_vld_g &
(ld_inst_vld_unflushed | st_inst_vld_unflushed) & lsu_inst_vld_w ;*/
// caused for both locked and unlocked entries.
assign tte_data_perror_unc =
//tte_data_parity_error & tlb_rd_tte_data_locked & tlb_tte_vld_g &
tte_data_parity_error & tlb_tte_vld_g &
(ld_inst_vld_unflushed | st_inst_vld_unflushed) & lsu_inst_vld_w &
~lsu_flush_pipe_w ;
// Asi rd parity error detection
wire asi_tte_data_perror,asi_tte_tag_perror ;
assign asi_tte_data_perror =
tte_data_parity_error & data_rd_vld_g ;
// For data tte read, both tag and data arrays are read.
// Parity error on asi read of tag should not be reported.
assign asi_tte_tag_perror =
tte_tag_parity_error & tag_rd_vld_g & ~data_rd_vld_g ;
wire st_dtlb_perror ;
assign st_dtlb_perror = tte_data_parity_error & tlb_tte_vld_g &
st_inst_vld_unflushed & lsu_inst_vld_w ;
// ~lsu_flush_pipe_w ;
wire cancel_err_flush ;
assign cancel_err_flush = // Bug 5165
((priv_pg_usr_mode | nfo_pg_nonnfo_asi |
atm_access_w_nc) & tlb_tte_vld_g) | // bug6052/eco6620
spec_access_epage |
nonwr_pg_st_access ;
// Bug 6877
wire squash_err ;
assign squash_err =
// assume always higher priority. BE - share common terms elsewhere.
tlu_early_flush_pipe_w | defr_trp_taken | ifu_lsu_flush_w |
// isolate to daccess_excptn/daccess_prot as per Bug 5165.
(lsu_tlu_ttype_vld_m2 & ~(daccess_excptn_sel | daccess_prot_sel)) |
((daccess_excptn_sel | daccess_prot_sel) & ~cancel_err_flush) ;
wire tlb_data_su_g ;
assign tlb_data_su_g = st_dtlb_perror & ~atomic_g &
~squash_err ;
//~(lsu_flush_pipe_w & ~cancel_err_flush) ; // Bug 6877
wire ld_dtlb_perror ;
assign ld_dtlb_perror = tte_data_parity_error & tlb_tte_vld_g &
ld_inst_vld_unflushed & lsu_inst_vld_w &
~squash_err ;
wire tlb_data_ue_g ;
assign tlb_data_ue_g =
ld_dtlb_perror | // synchronous to pipe - xslate ; ue is for ld now.
lsu_tlb_asi_data_perr_g ; // asychronous to pipe - asi rd
/* Simplify for Bug 5888.
wire st_noatom_dtlb_perr ; // atomics not represented.
assign st_noatom_dtlb_perr = st_dtlb_perror & ~lsu_flush_pipe_w & ~atomic_g ;
wire st_noatom_dtlb_perr_en ;
assign st_noatom_dtlb_perr_en = st_noatom_dtlb_perr & nceen_pipe_g ; */
wire st_noatom_dtlb_perr_en ;
wire st_dtlb_perr_en ;
assign st_noatom_dtlb_perr_en = st_dtlb_perr_en & ~atomic_g ;
// rm corr err. reporting
dff_s #(3) terr_stgd1 (
.din ({tlb_data_su_g,tlb_data_ue_g,lsu_tlb_asi_tag_perr_g}),
//.din ({st_noatom_dtlb_perr,tlb_data_ue_g,lsu_tlb_asi_tag_perr_g}),
.q ({lsu_ifu_tlb_data_su,lsu_ifu_tlb_data_ue,lsu_ifu_tlb_tag_ue}),
.clk (clk),
.se (se), .si (), .so ()
);
// If st dtlb parity error detected, then need to invalidate st in stb.
// Considered unrecoverable for the thread itself.
assign st_dtlb_perr_en = st_dtlb_perror & ~lsu_flush_pipe_w & nceen_pipe_g ;
// Kill will happen for atomics also.
//assign lsu_exu_st_dtlb_perr_g = st_dtlb_perr_en ;
assign lsu_exu_st_dtlb_perr_g = st_noatom_dtlb_perr_en ; // Bug 5888
assign lsu_ffu_st_dtlb_perr_g = st_noatom_dtlb_perr_en ; // Bug 5910/ECO 6529
assign lsu_st_dtlb_perr_g[0] = st_dtlb_perr_en & thread0_g ;
assign lsu_st_dtlb_perr_g[1] = st_dtlb_perr_en & thread1_g ;
assign lsu_st_dtlb_perr_g[2] = st_dtlb_perr_en & thread2_g ;
assign lsu_st_dtlb_perr_g[3] = st_dtlb_perr_en & thread3_g ;
//==========================================================================
// DEFERRED TRAP DUE TO STORE
//==========================================================================
// Cases :
// defr_trp_m=1,ifu_flush_w=0.
// - defr_trp is generated.
// - next inst will not take redundant deferred trap as
// its inst_vld will be annulled by trap flush.
// defr_trp_m=1,ifu_flush_w=1.
// - defr_trp is generated. TLU annuls.
// - Other units see redundant defr_trp flush ORed with ifu_flush_w.
// - next inst will not take redundant deferred trap as
// its inst_vld will be annulled by ifu_flush_w .
// Log Deferred trap. Take on next available inst from thread.
// Inst vld must be qualified with flush.
wire st_defr_trp_en0,st_defr_trp_en1,st_defr_trp_en2,st_defr_trp_en3 ;
wire st_defr_trp0,st_defr_trp1,st_defr_trp2,st_defr_trp3 ;
assign st_defr_trp_en0 = st_noatom_dtlb_perr_en & thread0_g ;
assign st_defr_trp_en1 = st_noatom_dtlb_perr_en & thread1_g ;
assign st_defr_trp_en2 = st_noatom_dtlb_perr_en & thread2_g ;
assign st_defr_trp_en3 = st_noatom_dtlb_perr_en & thread3_g ;
wire stpend_rst0_m,stpend_rst1_m,stpend_rst2_m,stpend_rst3_m;
wire stpend_rst0_w,stpend_rst1_w,stpend_rst2_w,stpend_rst3_w;
wire stpend_rst0,stpend_rst1,stpend_rst2,stpend_rst3;
assign stpend_rst0_m = reset |
((st_defr_trp0 | st_defr_trp_en0) & thread0_m & flush_w_inst_vld_m);
assign stpend_rst1_m = reset |
((st_defr_trp1 | st_defr_trp_en1) & thread1_m & flush_w_inst_vld_m);
assign stpend_rst2_m = reset |
((st_defr_trp2 | st_defr_trp_en2) & thread2_m & flush_w_inst_vld_m);
assign stpend_rst3_m = reset |
((st_defr_trp3 | st_defr_trp_en3) & thread3_m & flush_w_inst_vld_m);
// Postphone reset by a cycle - 4916
dff_s #(4) stpend_d1 (
.din ({stpend_rst3_m,stpend_rst2_m,stpend_rst1_m,stpend_rst0_m}),
.q ({stpend_rst3_w,stpend_rst2_w,stpend_rst1_w,stpend_rst0_w}),
.clk (clk),
.se (se), .si (), .so ()
);
// Prevent reset if inst is flushed by ifu.
assign stpend_rst3 = stpend_rst3_w & ~ifu_lsu_flush_w ;
assign stpend_rst2 = stpend_rst2_w & ~ifu_lsu_flush_w ;
assign stpend_rst1 = stpend_rst1_w & ~ifu_lsu_flush_w ;
assign stpend_rst0 = stpend_rst0_w & ~ifu_lsu_flush_w ;
dffre_s #(1) deftrp_t0 (
.din (st_defr_trp_en0),
.q (st_defr_trp0),
.rst (stpend_rst0),
.en (st_defr_trp_en0),
.clk (clk),
.se (se), .si (), .so ()
);
dffre_s #(1) deftrp_t1 (
.din (st_defr_trp_en1),
.q (st_defr_trp1),
.rst (stpend_rst1),
.en (st_defr_trp_en1),
.clk (clk),
.se (se), .si (), .so ()
);
dffre_s #(1) deftrp_t2 (
.din (st_defr_trp_en2),
.q (st_defr_trp2),
.rst (stpend_rst2),
.en (st_defr_trp_en2),
.clk (clk),
.se (se), .si (), .so ()
);
dffre_s #(1) deftrp_t3 (
.din (st_defr_trp_en3),
.q (st_defr_trp3),
.rst (stpend_rst3),
.en (st_defr_trp_en3),
.clk (clk),
.se (se), .si (), .so ()
);
// Deferred trap can be taken on any instruction.
// Selection is based on next thread available.
//instruction n+2, and the following...
assign defr_trp_taken_m =
//ifu_tlu_inst_vld_m & (
flush_w_inst_vld_m & ( // <= rely of flush by defr-trp to clear
// pended defr-trp
(st_defr_trp0 & thread0_m) |
(st_defr_trp1 & thread1_m) |
(st_defr_trp2 & thread2_m) |
(st_defr_trp3 & thread3_m)) ;
assign defr_trp_taken_byp =
//ifu_tlu_inst_vld_m & (
flush_w_inst_vld_m & (
(st_defr_trp_en0 & thread0_m) |
(st_defr_trp_en1 & thread1_m) |
(st_defr_trp_en2 & thread2_m) |
(st_defr_trp_en3 & thread3_m) );
assign defr_trp_taken_m_din = defr_trp_taken_m | defr_trp_taken_byp;
dff_s #(1) defr_trp_taken_stgg (
.din (defr_trp_taken_m_din),
.q (defr_trp_taken),
.clk (clk),
.se (se), .si (), .so ()
);
assign lsu_defr_trp_taken_g = defr_trp_taken ;
assign lsu_tlu_defr_trp_taken_g = defr_trp_taken ;
assign lsu_mmu_defr_trp_taken_g = defr_trp_taken ;
//==========================================================================
// DSFSR/SFAR WR
//==========================================================================
wire [3:0] pstate_cle,pstate_am ;
// flop'n use to prevent timing path.
dff_s #(8) cle_stg (
.din ({tlu_lsu_pstate_cle[3:0],tlu_lsu_pstate_am[3:0]}),
.q ({pstate_cle[3:0],pstate_am[3:0]}),
.clk (clk),
.se (se), .si (), .so ()
);
wire pstate_cle_m ;
assign pstate_cle_m =
(thread0_m & pstate_cle[0]) |
(thread1_m & pstate_cle[1]) |
(thread2_m & pstate_cle[2]) |
(thread3_m & pstate_cle[3]);
wire [3:0] dsfsr_asi_sel_m ;
wire prim_asi_sel ;
assign prim_asi_sel =
exu_tlu_misalign_addr_jmpl_rtn_m | (lsu_tlu_nonalt_ldst_m & ~lsu_nonalt_nucl_access_m) ;
assign dsfsr_asi_sel_m[0] = // ASI_PRIMARY
prim_asi_sel & ~pstate_cle_m;
// Does asi_primary_little make sense for jmpl/return ?
assign dsfsr_asi_sel_m[1] = // ASI_PRIMARY_LITTLE
prim_asi_sel & pstate_cle_m;
assign dsfsr_asi_sel_m[2] = // ASI_NUCLEUS
lsu_nonalt_nucl_access_m & ~pstate_cle_m;
assign dsfsr_asi_sel_m[3] = // ASI_NUCLEUS_LITTLE
lsu_nonalt_nucl_access_m & pstate_cle_m;
/*assign dsfsr_asi_sel_m[4] = // assigned asi
~(exu_tlu_misalign_addr_jmpl_rtn_m | lsu_tlu_nonalt_ldst_m);*/
wire [7:0] asi_state_g ;
// flop'n use to prevent timing path.
dff_s #(8) asistate_stgg (
.din (lsu_excpctl_asi_state_m[7:0]),
.q (asi_state_g[7:0]),
.clk (clk),
.se (se), .si (), .so ()
);
wire [7:0] dsfsr_asi_g ;
wire [3:0] dsfsr_asi_sel_g ;
/*assign dsfsr_asi_g[7:0] =(dsfsr_asi_sel_g[0] ? 8'h80 : 8'h00) |
(dsfsr_asi_sel_g[1] ? 8'h88 : 8'h00) |
(dsfsr_asi_sel_g[2] ? asi_state_g[7:0] : 8'h00);*/
// Bug 4212 - spec problem
assign dsfsr_asi_g[7:0] =(dsfsr_asi_sel_g[0] ? 8'h80 :
(dsfsr_asi_sel_g[1] ? 8'h88 :
(dsfsr_asi_sel_g[2] ? 8'h04 :
(dsfsr_asi_sel_g[3] ? 8'h0C : asi_state_g[7:0]))));
assign pstate_am_m =
(thread0_m & pstate_am[0]) |
(thread1_m & pstate_am[1]) |
(thread2_m & pstate_am[2]) |
(thread3_m & pstate_am[3]);
assign dmmu_va_oor_m = exu_tlu_va_oor_m & ~pstate_am_m & lsu_memref_m & ~lsu_squash_va_oor_m;
wire [3:0] dsfsr_flt_vld;
dff_s #(4) fltvld_stgd1 (
.din (tlu_dsfsr_flt_vld[3:0]),
.q (dsfsr_flt_vld[3:0]),
.clk (clk),
.se (se), .si (), .so ()
);
wire dsfsr_flt_vld_m ;
assign dsfsr_flt_vld_m =
(thread0_m & dsfsr_flt_vld[0]) |
(thread1_m & dsfsr_flt_vld[1]) |
(thread2_m & dsfsr_flt_vld[2]) |
(thread3_m & dsfsr_flt_vld[3]);
wire ldst_xslate_g,flsh_inst_g,dsfsr_flt_vld_g,dsfsr_wr_op_g ;
wire misalign_addr_jmpl_rtn_g,misalign_addr_ldst_atm_g ;
wire [2:0] dsfsr_ctxt_sel ;
// flop flt_vld and use
dff_s #(14) dsfsr_stgg (
.din ({dsfsr_asi_sel_m[3:0],dmmu_va_oor_m,// memref_m,
lsu_tlu_xslating_ldst_m,lsu_flsh_inst_m,lsu_tlu_ctxt_sel_m[2:0],
dsfsr_flt_vld_m,lsu_tlu_write_op_m,exu_tlu_misalign_addr_jmpl_rtn_m,
lsu_tlu_misalign_addr_ldst_atm_m}),
.q ({dsfsr_asi_sel_g[3:0],dmmu_va_oor_g,ldst_xslate_g,// memref_g,
flsh_inst_g,dsfsr_ctxt_sel[2:0],dsfsr_flt_vld_g, dsfsr_wr_op_g,
misalign_addr_jmpl_rtn_g,misalign_addr_ldst_atm_g}),
.clk (clk),
.se (se), .si (), .so ()
);
// To be set only for data_access_exception traps - only one can be
// reported at any time.
wire [6:0] dsfsr_ftype_g ;
assign dsfsr_ftype_g[6] = 1'b0;
assign dsfsr_ftype_g[5] = dmmu_va_oor_g | lsu_tlu_wtchpt_trp_g;
assign dsfsr_ftype_g[4] = lsu_tlu_flt_ld_nfo_pg_g;
assign dsfsr_ftype_g[3] = lsu_tlu_illegal_asi_action_g
| tlu_priv_trap_g ; // Bug 4799
//assign dsfsr_ftype_g[3] = lsu_tlu_illegal_asi_action_g | tlu_mmu_sync_data_excp_g;
assign dsfsr_ftype_g[2] = (lsu_tlu_uncache_atomic_g & ~atm_access_unsup_asi);
assign dsfsr_ftype_g[1] = lsu_tlu_spec_access_epage_g;
assign dsfsr_ftype_g[0] = lsu_tlu_priv_violtn_g;
wire dsfsr_side_effect_g ;
assign dsfsr_side_effect_g = lsu_tlu_tte_ebit_g & (ldst_xslate_g | flsh_inst_g);
// Fault Type based on Priority Encoding of Traps
wire [6:0] dsfsr_pe_ftype_g ;
wire dsfsr_ftype_zero ;
// Is this needed ? Doesn't it default to zero ?
assign dsfsr_pe_ftype_g[6:0] = dsfsr_ftype_zero ? 7'h00 : dsfsr_ftype_g[6:0];
// set to 11 when the access does not have a translating asi.
wire [1:0] dsfsr_ctxt_g ;
assign dsfsr_ctxt_g[1:0] =
dsfsr_ctxt_sel[0] ? 2'b00 :
dsfsr_ctxt_sel[1] ? 2'b01 :
dsfsr_ctxt_sel[2] ? 2'b10 : 2'b11;
assign lsu_dsfsr_din_g[23:0] =
{dsfsr_asi_g[7:0],
2'b0,
dsfsr_pe_ftype_g[6:0],
dsfsr_side_effect_g,
dsfsr_ctxt_g[1:0],
1'b0, // Bug 3323 - Arch change
//pstate_priv,
dsfsr_wr_op_g, // pipe
dsfsr_flt_vld_g,
1'b1};
// This is going to be a critical path !!!
// Assume that traps in front-end cause instructions to be no`oped
// further down the pipeline. Thus there is no need to qualify writes
// to dsfsr with writes to isfsr
wire dsfsr_trp_wr_g ;
wire dsfsr_trp_wr_pre_m,dsfsr_trp_wr_pre_g ;
assign dsfsr_trp_wr_pre_m =
spv_use_hpv_m | // Bug 3254 ; add new data-access-excp
// spec_access_epage_m | // Bug 3515
priv_action_m |
exu_tlu_misalign_addr_jmpl_rtn_m |
lsu_tlu_misalign_addr_ldst_atm_m ;
dff_s dsfsrtrg_stgg (
.din (dsfsr_trp_wr_pre_m),
.q (dsfsr_trp_wr_pre_g),
.clk (clk),
.se (se), .si (), .so ()
);
assign dsfsr_trp_wr_g =
((lsu_tlu_priv_violtn_g |
lsu_tlu_spec_access_epage_g | // Bug 3515 - uncomment out.
lsu_tlu_uncache_atomic_g | lsu_tlu_illegal_asi_action_g |
lsu_tlu_flt_ld_nfo_pg_g | dmmu_va_oor_g) | // data access exceptions
daccess_prot | // daccess_excptn not excluded.
lsu_tlu_wtchpt_trp_g | // watchpoint trap
dsfsr_trp_wr_pre_g |
tlu_priv_trap_g // scratchpad/queue daccess;Bug 4799
) &
lsu_inst_vld_w & ~(ifu_lsu_flush_w | defr_trp_taken) ; // Bug 4444,5196
assign dsfsr_ftype_zero =
daccess_prot_g | lsu_tlu_priv_action_g | lsu_tlu_wtchpt_trp_g |
misalign_addr_jmpl_rtn_g | misalign_addr_ldst_atm_g;
// terms below can be made common. (grape)
assign lsu_dmmu_sfsr_trp_wr[0] = dsfsr_trp_wr_g & thread0_g;
assign lsu_dmmu_sfsr_trp_wr[1] = dsfsr_trp_wr_g & thread1_g;
assign lsu_dmmu_sfsr_trp_wr[2] = dsfsr_trp_wr_g & thread2_g;
assign lsu_dmmu_sfsr_trp_wr[3] = dsfsr_trp_wr_g & thread3_g;
//==========================================================================
// Exception Handling End
//==========================================================================
endmodule
|
module mc_dlp
#(parameter BYTES = 16)
(
input reset_n,
input mclock,
input hst_clock,
input dlp_req,
input [4:0] dlp_wcnt,
input [27:0] dlp_org,
input dlp_gnt,
input dlp_push,
output reg dlp_mc_done,
output reg dlp_arb_req,
output reg [4:0] dlp_arb_wcnt,
output reg [27:0] dlp_arb_addr,
output reg dlp_ready
);
reg [27:0] capt_org;
reg [4:0] capt_wcnt;
reg dlp_req_toggle;
reg req_sync_1, req_sync_2, req_sync_3;
reg dlp_gnt_toggle;
reg gnt_sync_1, gnt_sync_2, gnt_sync_3;
reg [1:0] request_count;
reg [4:0] dlp_count;
localparam DLP = 3'h1;
// Capture request and control the ready signal
always @ (posedge hst_clock or negedge reset_n) begin
if(!reset_n) begin
dlp_ready <= 1'b1;
dlp_req_toggle <= 1'b0;
gnt_sync_1 <= 1'b0;
gnt_sync_2 <= 1'b0;
gnt_sync_3 <= 1'b0;
end else begin
if(dlp_req==1'b1) begin
dlp_req_toggle <= ~dlp_req_toggle;
capt_org <= dlp_org;
capt_wcnt <= dlp_wcnt;
dlp_ready <= 1'b0;
end // if (dlp_req==1'b1)
// synchronize the gnt toggle from mclock domain
gnt_sync_1 <= dlp_gnt_toggle;
gnt_sync_2 <= gnt_sync_1;
gnt_sync_3 <= gnt_sync_2;
if(gnt_sync_2 ^ gnt_sync_3) dlp_ready <= 1'b1;
end // else: !if(!reset_n)
end // always @ (posedge hst_clock or negedge reset_n)
// Issue requests to the arbiter
always @ (posedge mclock or negedge reset_n) begin
if(!reset_n) begin
dlp_arb_req <= 1'b0;
dlp_gnt_toggle <= 1'b0;
req_sync_1 <= 1'b0;
req_sync_2 <= 1'b0;
req_sync_3 <= 1'b0;
dlp_mc_done <= 1'b0;
dlp_arb_addr <= 28'b0;
dlp_arb_req <= 1'b0;
dlp_count <= 5'b0;
end else begin
req_sync_1 <= dlp_req_toggle;
req_sync_2 <= req_sync_1;
req_sync_3 <= req_sync_2;
if(req_sync_2 ^ req_sync_3) begin
dlp_arb_addr <= capt_org;
dlp_arb_req <= 1'b1;
dlp_arb_wcnt <= capt_wcnt;
end // if (req_sync_2==1'b1 && req_sync_3==1'b0)
if(dlp_gnt==1'b1) begin
dlp_arb_req <= 1'b0;
dlp_gnt_toggle <= ~dlp_gnt_toggle;
end // if (dlp_gnt==1'b1)
if (dlp_push && ~dlp_mc_done)
dlp_count <= dlp_count + 5'h1;
else if(dlp_mc_done)
dlp_count <= 5'h0;
if (dlp_push && ~dlp_mc_done) begin
if (BYTES == 4) dlp_mc_done <= &dlp_count; // FIXME.
else if (BYTES == 8) dlp_mc_done <= dlp_count[0]; // FIXME.
else dlp_mc_done <= (dlp_count == dlp_arb_wcnt);
end
else dlp_mc_done <= 1'b0;
end // else: !if(!reset_n)
end // always @ (posedge mclock or negedge reset_n)
endmodule
|
module drv_bus_req(
input clk_sys,
input ready,
input r,
input w,
input in,
input [0:7] a1,
input [0:15] a2,
input [0:15] a3,
input zw,
output reg zg,
input ans_any,
output dw,
output dr,
output din,
output dpn,
output [0:3] dnb,
output [0:15] dad,
output [0:15] ddt
);
// registered data input/output
reg ir, iw, iin;
reg [0:7] ia1;
reg [0:15] ia2;
reg [0:15] ia3;
// request trigger
wire req = ready & (r | w | in);
localparam IDLE = 4'd0;
localparam REQ = 4'd1;
reg [0:0] state = IDLE;
always @ (posedge clk_sys) begin
case (state)
IDLE: begin
if (req) begin
ir <= r;
iw <= w;
iin <= in;
ia1 <= a1;
ia2 <= a2;
ia3 <= a3;
zg <= 1;
state <= REQ;
end
end
REQ: begin
if (zw & ans_any) begin
zg <= 0;
state <= IDLE;
end
end
endcase
end
wire zwzg = zw & zg;
assign dw = zwzg ? iw : 1'd0;
assign dr = zwzg ? ir : 1'd0;
assign din = zwzg ? iin : 1'd0;
assign dpn = zwzg ? ia1[3] : 1'd0;
assign dnb = zwzg ? ia1[4:7] : 4'd0;
assign dad = zwzg ? ia2 : 16'd0;
assign ddt = zwzg ? ia3 : 16'd0;
endmodule
|
module rom_firbank_96_192(
input wire clk,
input wire [3:0] addr,
output wire [23:0] data);
reg [23:0] data_ff;
assign data = data_ff;
always @(posedge clk) begin
case(addr)
0: data_ff <= 24'h16B4E1; // 1488097
1: data_ff <= 24'h050C70; // 330864
2: data_ff <= 24'hFD6D3E; // -168642
3: data_ff <= 24'hFEFCB7; // -66377
4: data_ff <= 24'h003573; // 13683
5: data_ff <= 24'h0013DD; // 5085
6: data_ff <= 24'hFFFF42; // -190
7: data_ff <= 24'hFFFFF6; // -10
8: data_ff <= 24'h1C8992; // 1870226
9: data_ff <= 24'h0DAAE0; // 895712
10: data_ff <= 24'hFF750F; // -35569
11: data_ff <= 24'hFDCF4A; // -143542
12: data_ff <= 24'hFFE0FC; // -7940
13: data_ff <= 24'h002F67; // 12135
14: data_ff <= 24'h00036F; // 879
15: data_ff <= 24'hFFFF93; // -109
default: data_ff <= 0;
endcase
end
endmodule
|
module sky130_fd_sc_ms__fah (
COUT,
SUM ,
A ,
B ,
CI ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output COUT;
output SUM ;
input A ;
input B ;
input CI ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire xor0_out_SUM ;
wire pwrgood_pp0_out_SUM ;
wire a_b ;
wire a_ci ;
wire b_ci ;
wire or0_out_COUT ;
wire pwrgood_pp1_out_COUT;
// Name Output Other arguments
xor xor0 (xor0_out_SUM , A, B, CI );
sky130_fd_sc_ms__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_SUM , xor0_out_SUM, VPWR, VGND);
buf buf0 (SUM , pwrgood_pp0_out_SUM );
and and0 (a_b , A, B );
and and1 (a_ci , A, CI );
and and2 (b_ci , B, CI );
or or0 (or0_out_COUT , a_b, a_ci, b_ci );
sky130_fd_sc_ms__udp_pwrgood_pp$PG pwrgood_pp1 (pwrgood_pp1_out_COUT, or0_out_COUT, VPWR, VGND);
buf buf1 (COUT , pwrgood_pp1_out_COUT );
endmodule
|
module sky130_fd_sc_ms__o21ai (
Y ,
A1 ,
A2 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A1 ;
input A2 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire or0_out ;
wire nand0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
or or0 (or0_out , A2, A1 );
nand nand0 (nand0_out_Y , B1, or0_out );
sky130_fd_sc_ms__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nand0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
|
module xgmii_mux (
clock,
data0x,
data1x,
data2x,
data3x,
sel,
result);
input clock;
input [65:0] data0x;
input [65:0] data1x;
input [65:0] data2x;
input [65:0] data3x;
input [1:0] sel;
output [65:0] result;
wire [65:0] sub_wire0;
wire [65:0] sub_wire5 = data3x[65:0];
wire [65:0] sub_wire4 = data2x[65:0];
wire [65:0] sub_wire3 = data1x[65:0];
wire [65:0] result = sub_wire0[65:0];
wire [65:0] sub_wire1 = data0x[65:0];
wire [263:0] sub_wire2 = {sub_wire5, sub_wire4, sub_wire3, sub_wire1};
lpm_mux LPM_MUX_component (
.clock (clock),
.data (sub_wire2),
.sel (sel),
.result (sub_wire0)
// synopsys translate_off
,
.aclr (),
.clken ()
// synopsys translate_on
);
defparam
LPM_MUX_component.lpm_pipeline = 1,
LPM_MUX_component.lpm_size = 4,
LPM_MUX_component.lpm_type = "LPM_MUX",
LPM_MUX_component.lpm_width = 66,
LPM_MUX_component.lpm_widths = 2;
endmodule
|
module sky130_fd_sc_lp__iso1n (
X ,
A ,
SLEEP_B
);
// Module ports
output X ;
input A ;
input SLEEP_B;
// Module supplies
supply1 VPWR ;
supply0 KAGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire SLEEP;
// Name Output Other arguments
not not0 (SLEEP , SLEEP_B );
or or0 (X , A, SLEEP );
endmodule
|
module fpgaminer_top (osc_clk, RxD, TxD, anode, segment, disp_switch);
// The LOOP_LOG2 parameter determines how unrolled the SHA-256
// calculations are. For example, a setting of 1 will completely
// unroll the calculations, resulting in 128 rounds and a large, fast
// design.
//
// A setting of 2 will result in 64 rounds, with half the size and
// half the speed. 3 will be 32 rounds, with 1/4th the size and speed.
// And so on.
//
// Valid range: [0, 5]
`ifdef CONFIG_LOOP_LOG2
parameter LOOP_LOG2 = `CONFIG_LOOP_LOG2;
`else
parameter LOOP_LOG2 = 5;
`endif
// No need to adjust these parameters
localparam [5:0] LOOP = (6'd1 << LOOP_LOG2);
// The nonce will always be larger at the time we discover a valid
// hash. This is its offset from the nonce that gave rise to the valid
// hash (except when LOOP_LOG2 == 0 or 1, where the offset is 131 or
// 66 respectively).
localparam [31:0] GOLDEN_NONCE_OFFSET = (32'd1 << (7 - LOOP_LOG2)) + 32'd1;
input osc_clk;
////
reg [255:0] state = 0;
reg [511:0] data = 0;
reg [31:0] nonce = 32'h00000000;
//// PLL
wire hash_clk;
`ifndef SIM
main_pll pll_blk (.CLKIN_IN(osc_clk), .CLK0_OUT(hash_clk));
// main_pll pll_blk (.CLKIN_IN(osc_clk), .CLK2X_OUT(hash_clk));
`else
assign hash_clk = osc_clk;
`endif
//// Hashers
wire [255:0] hash, hash2;
reg [5:0] cnt = 6'd0;
reg feedback = 1'b0;
sha256_transform #(.LOOP(LOOP)) uut (
.clk(hash_clk),
.feedback(feedback),
.cnt(cnt),
.rx_state(state),
.rx_input(data),
.tx_hash(hash)
);
sha256_transform #(.LOOP(LOOP)) uut2 (
.clk(hash_clk),
.feedback(feedback),
.cnt(cnt),
.rx_state(256'h5be0cd191f83d9ab9b05688c510e527fa54ff53a3c6ef372bb67ae856a09e667),
.rx_input({256'h0000010000000000000000000000000000000000000000000000000080000000, hash}),
.tx_hash(hash2)
);
//// Virtual Wire Control
reg [255:0] midstate_buf = 0, data_buf = 0;
wire [255:0] midstate_vw, data2_vw;
input RxD;
serial_receive serrx (.clk(hash_clk), .RxD(RxD), .midstate(midstate_vw), .data2(data2_vw));
//// Virtual Wire Output
reg [31:0] golden_nonce = 0;
reg serial_send;
wire serial_busy;
output TxD;
serial_transmit sertx (.clk(hash_clk), .TxD(TxD), .send(serial_send), .busy(serial_busy), .word(golden_nonce));
//// Control Unit
reg is_golden_ticket = 1'b0;
reg feedback_d1 = 1'b1;
wire [5:0] cnt_next;
wire [31:0] nonce_next;
wire feedback_next;
`ifndef SIM
wire reset;
assign reset = 1'b0;
`else
reg reset = 1'b0; // NOTE: Reset is not currently used in the actual FPGA; for simulation only.
`endif
assign cnt_next = reset ? 6'd0 : (LOOP == 1) ? 6'd0 : (cnt + 6'd1) & (LOOP-1);
// On the first count (cnt==0), load data from previous stage (no feedback)
// on 1..LOOP-1, take feedback from current stage
// This reduces the throughput by a factor of (LOOP), but also reduces the design size by the same amount
assign feedback_next = (LOOP == 1) ? 1'b0 : (cnt_next != {(LOOP_LOG2){1'b0}});
assign nonce_next =
reset ? 32'd0 :
feedback_next ? nonce : (nonce + 32'd1);
always @ (posedge hash_clk)
begin
`ifdef SIM
//midstate_buf <= 256'h2b3f81261b3cfd001db436cfd4c8f3f9c7450c9a0d049bee71cba0ea2619c0b5;
//data_buf <= 256'h00000000000000000000000080000000_00000000_39f3001b6b7b8d4dc14bfc31;
//nonce <= 30411740;
`else
midstate_buf <= midstate_vw;
data_buf <= data2_vw;
`endif
cnt <= cnt_next;
feedback <= feedback_next;
feedback_d1 <= feedback;
// Give new data to the hasher
state <= midstate_buf;
data <= {384'h000002800000000000000000000000000000000000000000000000000000000000000000000000000000000080000000, nonce_next, data_buf[95:0]};
nonce <= nonce_next;
// Check to see if the last hash generated is valid.
is_golden_ticket <= (hash2[255:224] == 32'h00000000) && !feedback_d1;
if(is_golden_ticket)
begin
// TODO: Find a more compact calculation for this
if (LOOP == 1)
golden_nonce <= nonce - 32'd131;
else if (LOOP == 2)
golden_nonce <= nonce - 32'd66;
else
golden_nonce <= nonce - GOLDEN_NONCE_OFFSET;
if (!serial_busy) serial_send <= 1;
end // if (is_golden_ticket)
else
serial_send <= 0;
`ifdef SIM
if (!feedback_d1)
$display ("nonce: %8x\nhash2: %64x\n", nonce, hash2);
`endif
end
// die debuggenlichten
input disp_switch;
output [7:0] segment;
output [3:0] anode;
wire [7:0] segment_data;
// inverted signals, so 1111.. to turn it off
assign segment = disp_switch? segment_data : {8{1'b1}};
// raw7seg disp(.clk(hash_clk), .segment(segment_data), .anode(anode), .word({midstate_vw[15:0], data2_vw[15:0]}));
raw7seg disp(.clk(hash_clk), .segment(segment_data), .anode(anode), .word(golden_nonce));
endmodule
|
module sky130_fd_sc_hd__dlymetal6s4s (
X,
A
);
// Module ports
output X;
input A;
// Local signals
wire buf0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X, A );
buf buf1 (X , buf0_out_X );
endmodule
|
module sky130_fd_sc_ms__ha (
COUT,
SUM ,
A ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
output COUT;
output SUM ;
input A ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
|
module hps_sdram_p0_iss_probe (
probe_input
);
parameter WIDTH = 1;
parameter ID_NAME = "PROB";
input [WIDTH-1:0] probe_input;
altsource_probe iss_probe_inst (
.probe (probe_input),
.source ()
// synopsys translate_off
,
.clr (),
.ena (),
.ir_in (),
.ir_out (),
.jtag_state_cdr (),
.jtag_state_cir (),
.jtag_state_e1dr (),
.jtag_state_sdr (),
.jtag_state_tlr (),
.jtag_state_udr (),
.jtag_state_uir (),
.raw_tck (),
.source_clk (),
.source_ena (),
.tdi (),
.tdo (),
.usr1 ()
// synopsys translate_on
);
defparam
iss_probe_inst.enable_metastability = "NO",
iss_probe_inst.instance_id = ID_NAME,
iss_probe_inst.probe_width = WIDTH,
iss_probe_inst.sld_auto_instance_index = "YES",
iss_probe_inst.sld_instance_index = 0,
iss_probe_inst.source_initial_value = "0",
iss_probe_inst.source_width = 0;
endmodule
|
module sky130_fd_sc_lp__o221a (
X ,
A1,
A2,
B1,
B2,
C1
);
output X ;
input A1;
input A2;
input B1;
input B2;
input C1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
|
module pcieCore_pipe_reset #
(
//---------- Global ------------------------------------
parameter PCIE_SIM_SPEEDUP = "FALSE", // PCIe sim speedup
parameter PCIE_GT_DEVICE = "GTX",
parameter PCIE_PLL_SEL = "CPLL", // PCIe PLL select for Gen1/Gen2 only
parameter PCIE_POWER_SAVING = "TRUE", // PCIe power saving
parameter PCIE_TXBUF_EN = "FALSE", // PCIe TX buffer enable
parameter PCIE_LANE = 1, // PCIe number of lanes
//---------- Local -------------------------------------
parameter CFG_WAIT_MAX = 6'd63, // Configuration wait max
parameter BYPASS_RXCDRLOCK = 1 // Bypass RXCDRLOCK
)
(
//---------- Input -------------------------------------
input RST_CLK,
input RST_RXUSRCLK,
input RST_DCLK,
input RST_RST_N,
input [PCIE_LANE-1:0] RST_DRP_DONE,
input [PCIE_LANE-1:0] RST_RXPMARESETDONE,
input [PCIE_LANE-1:0] RST_CPLLLOCK,
input RST_QPLL_IDLE,
input [PCIE_LANE-1:0] RST_RATE_IDLE,
input [PCIE_LANE-1:0] RST_RXCDRLOCK,
input RST_MMCM_LOCK,
input [PCIE_LANE-1:0] RST_RESETDONE,
input [PCIE_LANE-1:0] RST_PHYSTATUS,
input [PCIE_LANE-1:0] RST_TXSYNC_DONE,
//---------- Output ------------------------------------
output RST_CPLLRESET,
output RST_CPLLPD,
output reg RST_DRP_START,
output reg RST_DRP_X16X20_MODE,
output reg RST_DRP_X16,
output RST_RXUSRCLK_RESET,
output RST_DCLK_RESET,
output RST_GTRESET,
output RST_USERRDY,
output RST_TXSYNC_START,
output RST_IDLE,
output [4:0] RST_FSM
);
//---------- Input Register ----------------------------
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [PCIE_LANE-1:0] drp_done_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [PCIE_LANE-1:0] rxpmaresetdone_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [PCIE_LANE-1:0] cplllock_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg qpll_idle_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [PCIE_LANE-1:0] rate_idle_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [PCIE_LANE-1:0] rxcdrlock_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg mmcm_lock_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [PCIE_LANE-1:0] resetdone_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [PCIE_LANE-1:0] phystatus_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [PCIE_LANE-1:0] txsync_done_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [PCIE_LANE-1:0] drp_done_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [PCIE_LANE-1:0] rxpmaresetdone_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [PCIE_LANE-1:0] cplllock_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg qpll_idle_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [PCIE_LANE-1:0] rate_idle_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [PCIE_LANE-1:0] rxcdrlock_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg mmcm_lock_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [PCIE_LANE-1:0] resetdone_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [PCIE_LANE-1:0] phystatus_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [PCIE_LANE-1:0] txsync_done_reg2;
//---------- Internal Signal ---------------------------
reg [ 5:0] cfg_wait_cnt = 6'd0;
//---------- Output Register ---------------------------
reg cpllreset = 1'd0;
reg cpllpd = 1'd0;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxusrclk_rst_reg1 = 1'd0;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxusrclk_rst_reg2 = 1'd0;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg dclk_rst_reg1 = 1'd0;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg dclk_rst_reg2 = 1'd0;
reg gtreset = 1'd0;
reg userrdy = 1'd0;
reg [4:0] fsm = 5'h2;
//---------- FSM ---------------------------------------
localparam FSM_IDLE = 5'h0;
localparam FSM_CFG_WAIT = 5'h1;
localparam FSM_CPLLRESET = 5'h2;
localparam FSM_DRP_X16_START = 5'h3;
localparam FSM_DRP_X16_DONE = 5'h4;
localparam FSM_CPLLLOCK = 5'h5;
localparam FSM_DRP = 5'h6;
localparam FSM_GTRESET = 5'h7;
localparam FSM_RXPMARESETDONE_1 = 5'h8;
localparam FSM_RXPMARESETDONE_2 = 5'h9;
localparam FSM_DRP_X20_START = 5'hA;
localparam FSM_DRP_X20_DONE = 5'hB;
localparam FSM_MMCM_LOCK = 5'hC;
localparam FSM_RESETDONE = 5'hD;
localparam FSM_CPLL_PD = 5'hE;
localparam FSM_TXSYNC_START = 5'hF;
localparam FSM_TXSYNC_DONE = 5'h10;
//---------- Input FF ----------------------------------------------------------
always @ (posedge RST_CLK)
begin
if (!RST_RST_N)
begin
//---------- 1st Stage FF --------------------------
drp_done_reg1 <= {PCIE_LANE{1'd0}};
rxpmaresetdone_reg1 <= {PCIE_LANE{1'd0}};
cplllock_reg1 <= {PCIE_LANE{1'd0}};
qpll_idle_reg1 <= 1'd0;
rate_idle_reg1 <= {PCIE_LANE{1'd0}};
rxcdrlock_reg1 <= {PCIE_LANE{1'd0}};
mmcm_lock_reg1 <= 1'd0;
resetdone_reg1 <= {PCIE_LANE{1'd0}};
phystatus_reg1 <= {PCIE_LANE{1'd0}};
txsync_done_reg1 <= {PCIE_LANE{1'd0}};
//---------- 2nd Stage FF --------------------------
drp_done_reg2 <= {PCIE_LANE{1'd0}};
rxpmaresetdone_reg2 <= {PCIE_LANE{1'd0}};
cplllock_reg2 <= {PCIE_LANE{1'd0}};
qpll_idle_reg2 <= 1'd0;
rate_idle_reg2 <= {PCIE_LANE{1'd0}};
rxcdrlock_reg2 <= {PCIE_LANE{1'd0}};
mmcm_lock_reg2 <= 1'd0;
resetdone_reg2 <= {PCIE_LANE{1'd0}};
phystatus_reg2 <= {PCIE_LANE{1'd0}};
txsync_done_reg2 <= {PCIE_LANE{1'd0}};
end
else
begin
//---------- 1st Stage FF --------------------------
drp_done_reg1 <= RST_DRP_DONE;
rxpmaresetdone_reg1 <= RST_RXPMARESETDONE;
cplllock_reg1 <= RST_CPLLLOCK;
qpll_idle_reg1 <= RST_QPLL_IDLE;
rate_idle_reg1 <= RST_RATE_IDLE;
rxcdrlock_reg1 <= RST_RXCDRLOCK;
mmcm_lock_reg1 <= RST_MMCM_LOCK;
resetdone_reg1 <= RST_RESETDONE;
phystatus_reg1 <= RST_PHYSTATUS;
txsync_done_reg1 <= RST_TXSYNC_DONE;
//---------- 2nd Stage FF --------------------------
drp_done_reg2 <= drp_done_reg1;
rxpmaresetdone_reg2 <= rxpmaresetdone_reg1;
cplllock_reg2 <= cplllock_reg1;
qpll_idle_reg2 <= qpll_idle_reg1;
rate_idle_reg2 <= rate_idle_reg1;
rxcdrlock_reg2 <= rxcdrlock_reg1;
mmcm_lock_reg2 <= mmcm_lock_reg1;
resetdone_reg2 <= resetdone_reg1;
phystatus_reg2 <= phystatus_reg1;
txsync_done_reg2 <= txsync_done_reg1;
end
end
//---------- Configuration Reset Wait Counter ----------------------------------
always @ (posedge RST_CLK)
begin
if (!RST_RST_N)
cfg_wait_cnt <= 6'd0;
else
//---------- Increment Configuration Reset Wait Counter
if ((fsm == FSM_CFG_WAIT) && (cfg_wait_cnt < CFG_WAIT_MAX))
cfg_wait_cnt <= cfg_wait_cnt + 6'd1;
//---------- Hold Configuration Reset Wait Counter -
else if ((fsm == FSM_CFG_WAIT) && (cfg_wait_cnt == CFG_WAIT_MAX))
cfg_wait_cnt <= cfg_wait_cnt;
//---------- Reset Configuration Reset Wait Counter
else
cfg_wait_cnt <= 6'd0;
end
//---------- PIPE Reset FSM ----------------------------------------------------
always @ (posedge RST_CLK)
begin
if (!RST_RST_N)
begin
fsm <= FSM_CFG_WAIT;
cpllreset <= 1'd0;
cpllpd <= 1'd0;
gtreset <= 1'd0;
userrdy <= 1'd0;
end
else
begin
case (fsm)
//---------- Idle State ----------------------------
FSM_IDLE :
begin
if (!RST_RST_N)
begin
fsm <= FSM_CFG_WAIT;
cpllreset <= 1'd0;
cpllpd <= 1'd0;
gtreset <= 1'd0;
userrdy <= 1'd0;
end
else
begin
fsm <= FSM_IDLE;
cpllreset <= cpllreset;
cpllpd <= cpllpd;
gtreset <= gtreset;
userrdy <= userrdy;
end
end
//---------- Wait for Configuration Reset Delay ---
FSM_CFG_WAIT :
begin
fsm <= ((cfg_wait_cnt == CFG_WAIT_MAX) ? FSM_CPLLRESET : FSM_CFG_WAIT);
cpllreset <= cpllreset;
cpllpd <= cpllpd;
gtreset <= gtreset;
userrdy <= userrdy;
end
//---------- Hold CPLL and GTX Channel in Reset ----
FSM_CPLLRESET :
begin
fsm <= ((&(~cplllock_reg2) && (&(~resetdone_reg2))) ? FSM_CPLLLOCK : FSM_CPLLRESET);
cpllreset <= 1'd1;
cpllpd <= cpllpd;
gtreset <= 1'd1;
userrdy <= userrdy;
end
//---------- Wait for CPLL Lock --------------------
FSM_CPLLLOCK :
begin
fsm <= (&cplllock_reg2 ? FSM_DRP : FSM_CPLLLOCK);
cpllreset <= 1'd0;
cpllpd <= cpllpd;
gtreset <= gtreset;
userrdy <= userrdy;
end
//---------- Wait for DRP Done to Setup Gen1 -------
FSM_DRP :
begin
fsm <= (&rate_idle_reg2 ? ((PCIE_GT_DEVICE == "GTX") ? FSM_GTRESET : FSM_DRP_X16_START) : FSM_DRP);
cpllreset <= cpllreset;
cpllpd <= cpllpd;
gtreset <= gtreset;
userrdy <= userrdy;
end
//---------- Start DRP x16 -------------------------
FSM_DRP_X16_START :
begin
fsm <= &(~drp_done_reg2) ? FSM_DRP_X16_DONE : FSM_DRP_X16_START;
cpllreset <= cpllreset;
cpllpd <= cpllpd;
gtreset <= gtreset;
userrdy <= userrdy;
end
//---------- Wait for DRP x16 Done -----------------
FSM_DRP_X16_DONE :
begin
fsm <= (&drp_done_reg2) ? FSM_GTRESET : FSM_DRP_X16_DONE;
cpllreset <= cpllreset;
cpllpd <= cpllpd;
gtreset <= gtreset;
userrdy <= userrdy;
end
//---------- Release GTX Channel Reset -------------
FSM_GTRESET :
begin
fsm <= (PCIE_GT_DEVICE == "GTX") ? FSM_MMCM_LOCK : FSM_RXPMARESETDONE_1;
cpllreset <= cpllreset;
cpllpd <= cpllpd;
gtreset <= 1'b0;
userrdy <= userrdy;
end
//---------- Wait for RXPMARESETDONE Assertion -----
FSM_RXPMARESETDONE_1 :
begin
fsm <= (&rxpmaresetdone_reg2 || (PCIE_SIM_SPEEDUP == "TRUE")) ? FSM_RXPMARESETDONE_2 : FSM_RXPMARESETDONE_1;
cpllreset <= cpllreset;
cpllpd <= cpllpd;
gtreset <= gtreset;
userrdy <= userrdy;
end
//---------- Wait for RXPMARESETDONE De-assertion --
FSM_RXPMARESETDONE_2 :
begin
fsm <= (&(~rxpmaresetdone_reg2) || (PCIE_SIM_SPEEDUP == "TRUE")) ? FSM_DRP_X20_START : FSM_RXPMARESETDONE_2;
cpllreset <= cpllreset;
cpllpd <= cpllpd;
gtreset <= gtreset;
userrdy <= userrdy;
end
//---------- Start DRP x20 -------------------------
FSM_DRP_X20_START :
begin
fsm <= &(~drp_done_reg2) ? FSM_DRP_X20_DONE : FSM_DRP_X20_START;
cpllreset <= cpllreset;
cpllpd <= cpllpd;
gtreset <= gtreset;
userrdy <= userrdy;
end
//---------- Wait for DRP x20 Done -----------------
FSM_DRP_X20_DONE :
begin
fsm <= (&drp_done_reg2) ? FSM_MMCM_LOCK : FSM_DRP_X20_DONE;
cpllreset <= cpllreset;
cpllpd <= cpllpd;
gtreset <= gtreset;
userrdy <= userrdy;
end
//---------- Wait for MMCM and RX CDR Lock ---------
FSM_MMCM_LOCK :
begin
if (mmcm_lock_reg2 && (&rxcdrlock_reg2 || (BYPASS_RXCDRLOCK == 1)) && (qpll_idle_reg2 || (PCIE_PLL_SEL == "CPLL")))
begin
fsm <= FSM_RESETDONE;
cpllreset <= cpllreset;
cpllpd <= cpllpd;
gtreset <= gtreset;
userrdy <= 1'd1;
end
else
begin
fsm <= FSM_MMCM_LOCK;
cpllreset <= cpllreset;
cpllpd <= cpllpd;
gtreset <= gtreset;
userrdy <= 1'd0;
end
end
//---------- Wait for [TX/RX]RESETDONE and PHYSTATUS
FSM_RESETDONE :
begin
fsm <= (&resetdone_reg2 && (&(~phystatus_reg2)) ? FSM_CPLL_PD : FSM_RESETDONE);
cpllreset <= cpllreset;
cpllpd <= cpllpd;
gtreset <= gtreset;
userrdy <= userrdy;
end
//---------- Power-Down CPLL if QPLL is Used for Gen1/Gen2
FSM_CPLL_PD :
begin
fsm <= ((PCIE_TXBUF_EN == "TRUE") ? FSM_IDLE : FSM_TXSYNC_START);
cpllreset <= cpllreset;
cpllpd <= (PCIE_PLL_SEL == "QPLL");
gtreset <= gtreset;
userrdy <= userrdy;
end
//---------- Start TX Sync -------------------------
FSM_TXSYNC_START :
begin
fsm <= (&(~txsync_done_reg2) ? FSM_TXSYNC_DONE : FSM_TXSYNC_START);
cpllreset <= cpllreset;
cpllpd <= cpllpd;
gtreset <= gtreset;
userrdy <= userrdy;
end
//---------- Wait for TX Sync Done -----------------
FSM_TXSYNC_DONE :
begin
fsm <= (&txsync_done_reg2 ? FSM_IDLE : FSM_TXSYNC_DONE);
cpllreset <= cpllreset;
cpllpd <= cpllpd;
gtreset <= gtreset;
userrdy <= userrdy;
end
//---------- Default State -------------------------
default :
begin
fsm <= FSM_CFG_WAIT;
cpllreset <= 1'd0;
cpllpd <= 1'd0;
gtreset <= 1'd0;
userrdy <= 1'd0;
end
endcase
end
end
//---------- RXUSRCLK Reset Synchronizer ---------------------------------------
always @ (posedge RST_RXUSRCLK)
begin
if (cpllreset)
begin
rxusrclk_rst_reg1 <= 1'd1;
rxusrclk_rst_reg2 <= 1'd1;
end
else
begin
rxusrclk_rst_reg1 <= 1'd0;
rxusrclk_rst_reg2 <= rxusrclk_rst_reg1;
end
end
//---------- DCLK Reset Synchronizer -------------------------------------------
always @ (posedge RST_DCLK)
begin
if (fsm == FSM_CFG_WAIT)
begin
dclk_rst_reg1 <= 1'd1;
dclk_rst_reg2 <= dclk_rst_reg1;
end
else
begin
dclk_rst_reg1 <= 1'd0;
dclk_rst_reg2 <= dclk_rst_reg1;
end
end
//---------- PIPE Reset Output -------------------------------------------------
assign RST_CPLLRESET = cpllreset;
assign RST_CPLLPD = ((PCIE_POWER_SAVING == "FALSE") ? 1'd0 : cpllpd);
assign RST_RXUSRCLK_RESET = rxusrclk_rst_reg2;
assign RST_DCLK_RESET = dclk_rst_reg2;
assign RST_GTRESET = gtreset;
assign RST_USERRDY = userrdy;
assign RST_TXSYNC_START = (fsm == FSM_TXSYNC_START);
assign RST_IDLE = (fsm == FSM_IDLE);
assign RST_FSM = fsm;
//--------------------------------------------------------------------------------------------------
// Register Output
//--------------------------------------------------------------------------------------------------
always @ (posedge RST_CLK)
begin
if (!RST_RST_N)
begin
RST_DRP_START <= 1'd0;
RST_DRP_X16X20_MODE <= 1'd0;
RST_DRP_X16 <= 1'd0;
end
else
begin
RST_DRP_START <= (fsm == FSM_DRP_X16_START) || (fsm == FSM_DRP_X20_START);
RST_DRP_X16X20_MODE <= (fsm == FSM_DRP_X16_START) || (fsm == FSM_DRP_X16_DONE) || (fsm == FSM_DRP_X20_START) || (fsm == FSM_DRP_X20_DONE);
RST_DRP_X16 <= (fsm == FSM_DRP_X16_START) || (fsm == FSM_DRP_X16_DONE);
end
end
endmodule
|
module INSTRUCTION_CACHE_SIMULATION();
parameter HIGH = 1'b1 ;
parameter LOW = 1'b0 ;
parameter ADDRESS_WIDTH = 32 ;
parameter WORD_SIZE = 4 ;
parameter WORD_PER_BLOCK = 16 ;
parameter INS_RAM_DEPTH = 64 ;
localparam WORD_WIDTH = WORD_SIZE*8 ;
localparam BLOCK_WIDTH = WORD_WIDTH*WORD_PER_BLOCK ;
localparam BLOCK_ADDRESS_WIDTH = 26 ;
// Inputs
reg clk ;
reg stall_instruction_cache ;
reg [ADDRESS_WIDTH - 1 : 0] pc ;
reg pc_valid ;
reg address_to_l2_ready_instruction_cache ;
reg data_from_l2_valid_instruction_cache ;
reg [BLOCK_WIDTH - 1 : 0] data_from_l2_instruction_cache ;
// Outputs
wire [ADDRESS_WIDTH - 1 : 0] instruction ;
wire instruction_cache_ready ;
wire address_to_l2_valid_instruction_cache ;
wire [BLOCK_ADDRESS_WIDTH - 1: 0] address_to_l2_instruction_cache ;
wire data_from_l2_ready_instruction_cache ;
// Instantiate the Unit Under Test (UUT)
INSTRUCTION_CACHE uut(
.CLK(clk),
.STALL_INSTRUCTION_CACHE(stall_instruction_cache),
.PC(pc),
.PC_VALID(pc_valid),
.INSTRUCTION(instruction),
.INSTRUCTION_CACHE_READY(instruction_cache_ready),
.ADDRESS_TO_L2_READY_INSTRUCTION_CACHE(address_to_l2_ready_instruction_cache),
.ADDRESS_TO_L2_VALID_INSTRUCTION_CACHE(address_to_l2_valid_instruction_cache),
.ADDRESS_TO_L2_INSTRUCTION_CACHE(address_to_l2_instruction_cache),
.DATA_FROM_L2_READY_INSTRUCTION_CACHE(data_from_l2_ready_instruction_cache),
.DATA_FROM_L2_VALID_INSTRUCTION_CACHE(data_from_l2_valid_instruction_cache),
.DATA_FROM_L2_INSTRUCTION_CACHE(data_from_l2_instruction_cache)
);
// L2 Cache emulators
reg [WORD_WIDTH - 1 : 0] instruction_memory [0: INS_RAM_DEPTH - 1 ] ;
reg [BLOCK_WIDTH - 1 : 0] l2_memory [0: INS_RAM_DEPTH/WORD_PER_BLOCK - 1] ;
integer i,j;
initial
begin
// Initialize Inputs
clk = LOW ;
address_to_l2_ready_instruction_cache = HIGH ;
stall_instruction_cache = LOW ;
pc = 32'd8 ;
pc_valid = HIGH ;
//add
$readmemh("D:/Study/Verilog/RISC-V/verification programs/add/add.hex",instruction_memory);
for(i=0;i<INS_RAM_DEPTH/WORD_PER_BLOCK;i=i+1)
begin
l2_memory[i] = {BLOCK_WIDTH{1'b0}} ;
for(j=0;j<WORD_PER_BLOCK;j=j+1)
begin
l2_memory[i] = l2_memory[i] << WORD_WIDTH ;
l2_memory[i] = l2_memory[i] | instruction_memory[i*WORD_PER_BLOCK + j] ;
end
end
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
#100;
while(!instruction_cache_ready | stall_instruction_cache)
begin
#100;
end
pc = 32'd0 ;
#200;
while(!instruction_cache_ready | stall_instruction_cache)
begin
#100;
end
pc = 32'd8 ;
#200;
while(!instruction_cache_ready | stall_instruction_cache)
begin
#100;
end
pc = 32'd12 ;
#200;
while(!instruction_cache_ready | stall_instruction_cache)
begin
#100;
end
pc = 32'd4 ;
#200;
while(!instruction_cache_ready | stall_instruction_cache)
begin
#100;
end
pc = 32'd0 ;
#200;
while(!instruction_cache_ready | stall_instruction_cache)
begin
#100;
end
pc = 32'd16 ;
#200;
while(!instruction_cache_ready | stall_instruction_cache)
begin
#100;
end
pc = 32'd20 ;
#200;
while(!instruction_cache_ready | stall_instruction_cache)
begin
#100;
end
pc = 32'd4 ;
#200;
end
always
begin
#100;
clk=!clk;
end
always@(posedge clk)
begin
if(data_from_l2_ready_instruction_cache == HIGH)
begin
if(address_to_l2_valid_instruction_cache == HIGH)
begin
data_from_l2_valid_instruction_cache <= HIGH ;
data_from_l2_instruction_cache <= l2_memory [address_to_l2_instruction_cache] ;
end
else
begin
data_from_l2_valid_instruction_cache <= LOW ;
data_from_l2_instruction_cache <= {BLOCK_WIDTH{1'b0}} ;
end
end
else
begin
data_from_l2_valid_instruction_cache <= LOW ;
data_from_l2_instruction_cache <= {BLOCK_WIDTH{1'b0}} ;
end
end
endmodule
|
module address(
input CLK,
input [7:0] featurebits, // peripheral enable/disable
input [2:0] MAPPER, // MCU detected mapper
input [23:0] SNES_ADDR, // requested address from SNES
input [7:0] SNES_PA, // peripheral address from SNES
input SNES_ROMSEL, // ROMSEL from SNES
output [23:0] MAPPED_ADDR,// Address to request from SRAM0
output SRAM0_HIT, // enable SRAM0
output SRAM1_HIT, // enable SRAM1
output IS_SAVERAM, // address/CS mapped as SRAM?
output IS_GAMEPAKRAM, // address mapped as gamepak RAM?
output IS_ROM, // address mapped as ROM?
output IS_WRITABLE, // address somehow mapped as writable area?
input [23:0] SAVERAM_MASK,
input [23:0] ROM_MASK,
output msu_enable,
output gsu_enable,
output r213f_enable,
output snescmd_enable,
output nmicmd_enable,
output return_vector_enable,
output branch1_enable,
output branch2_enable
);
parameter [2:0]
FEAT_MSU1 = 3,
FEAT_213F = 4
;
wire [23:0] SRAM_SNES_ADDR;
/* ROM (max. 2 MB) at:
Bank 0x00-0x3f, Offset 8000-ffff
Bank 0x40-0x5f, Offset 0000-ffff
XXX: higan also accepts the following:
Bank 0x00-0x3f, Offset 0000-7fff
This duplicates the mapping in the 0000-7fff range.
*/
assign IS_ROM = ((~|SNES_ADDR[23:22] & SNES_ADDR[15])
|(!SNES_ADDR[23] & SNES_ADDR[22] & !SNES_ADDR[21]));
/* Save RAM (max. 128 kB) at:
Bank 0x78-0x79, Offset 0000-ffff */
assign IS_SAVERAM = SAVERAM_MASK[0] & (!SNES_ADDR[23] & &SNES_ADDR[22:20] & SNES_ADDR[19] & ~|SNES_ADDR[18:17]);
/* Gamepak RAM (max. 128 kB) at:
Bank 0x00-0x3f, Offset 6000-7fff
Bank 0x70-0x71, Offset 0000-ffff
Bank 0x80-0xbf, Offset 6000-7fff
XXX: Hmm, this doesn't seem to be making much sense. Two of the areas are
512 kB in size! Only 16 banks of 8 kB are needed for 128 kB.
Using these instead:
Bank 0x00-0x0f, Offset 6000-7fff
Bank 0x70-0x71, Offset 0000-ffff
Bank 0x80-0x8f, Offset 6000-7fff
XXX: higan maps the gamepak RAM at:
Bank 0x60-0x7f, Offset 0000-ffff
This effectively duplicates the mapping in 0x60-0x61, 0x62-0x63, etc.
*/
assign IS_GAMEPAKRAM = ((~|SNES_ADDR[22:20] & (SNES_ADDR[15:13] == 3'b011))
|(&SNES_ADDR[22:20] & ~|SNES_ADDR[19:17]));
assign IS_WRITABLE = IS_SAVERAM | IS_GAMEPAKRAM;
/* The Save RAM, ROM and gamepak RAM are laid out in the physical RAM as follows:
Save RAM addresses:
Bank 0x78-0x79: 0111 100a xxxx xxxx xxxx xxxx mapped to:
1110 000a xxxx xxxx xxxx xxxx
ROM addresses:
Bank 0x00-0x3f: address 00aa bbbb 1xxx xxxx xxxx xxxx mapped to:
000a abbb bxxx xxxx xxxx xxxx
Bank 0x40-0x5f: address 010a bbbb xxxx xxxx xxxx xxxx mapped to:
000a bbbb xxxx xxxx xxxx xxxx
Gamepak RAM addresses:
Bank 0x00-0x0f: address 0000 aaaa 011x xxxx xxxx xxxx mapped to:
1100 000a aaax xxxx xxxx xxxx
Bank 0x70-0x71: address 0111 000a xxxx xxxx xxxx xxxx mapped to:
1100 000a xxxx xxxx xxxx xxxx
Bank 0x80-0x8f: address 1000 aaaa 011x xxxx xxxx xxxx mapped to:
1100 000a aaax xxxx xxxx xxxx
*/
assign SRAM_SNES_ADDR = IS_SAVERAM
? (24'hE00000 | SNES_ADDR[16:0] & SAVERAM_MASK)
: (IS_ROM
? (~|SNES_ADDR[23:22] & SNES_ADDR[15])
? /* Bank 0x00-0x3f, Offset 8000-ffff */
({3'b000, SNES_ADDR[21:16], SNES_ADDR[14:0]} & ROM_MASK)
: /* Bank 0x40-0x5f, Offset 0000-ffff */
({3'b000, SNES_ADDR[20:0]} & ROM_MASK)
: (IS_GAMEPAKRAM
? (~|SNES_ADDR[22:20] & (SNES_ADDR[15:13] == 3'b011))
? /* Banks 0x00-0x0f and 0x80-0x8f */
({7'b1100000, SNES_ADDR[19:16], SNES_ADDR[12:0]})
: /* Banks 0x70-0x71 */
({7'b1100000, SNES_ADDR[16:0]})
: SNES_ADDR));
assign MAPPED_ADDR = SRAM_SNES_ADDR;
assign SRAM0_HIT = IS_ROM | (!IS_GAMEPAKRAM & IS_WRITABLE);
assign SRAM1_HIT = IS_GAMEPAKRAM;
assign msu_enable = featurebits[FEAT_MSU1] & (!SNES_ADDR[22] && ((SNES_ADDR[15:0] & 16'hfff8) == 16'h2000));
/* GSU MMIO interface is at:
Bank 0x00-0x3f, Offset 3000-32ff
Bank 0x80-0xbf, Offset 3000-32ff */
wire gsu_enable_w = (!SNES_ADDR[22] & (SNES_ADDR[15:10] == 6'b001100) & (!SNES_ADDR[9] | !SNES_ADDR[8]));
assign gsu_enable = gsu_enable_w;
assign r213f_enable = featurebits[FEAT_213F] & (SNES_PA == 8'h3f);
assign snescmd_enable = ({SNES_ADDR[22], SNES_ADDR[15:9]} == 8'b0_0010101);
assign nmicmd_enable = (SNES_ADDR == 24'h002BF2);
assign return_vector_enable = (SNES_ADDR == 24'h002A5A);
assign branch1_enable = (SNES_ADDR == 24'h002A13);
assign branch2_enable = (SNES_ADDR == 24'h002A4D);
endmodule
|
module sky130_fd_sc_hd__dlxbp (
//# {{data|Data Signals}}
input D ,
output Q ,
output Q_N ,
//# {{clocks|Clocking}}
input GATE,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
|
module soc_design_SystemID (
// inputs:
address,
clock,
reset_n,
// outputs:
readdata
)
;
output [ 31: 0] readdata;
input address;
input clock;
input reset_n;
wire [ 31: 0] readdata;
//control_slave, which is an e_avalon_slave
assign readdata = address ? 1499934064 : 255;
endmodule
|
module sky130_fd_sc_hd__nor2 (
//# {{data|Data Signals}}
input A,
input B,
output Y
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
|
module jbus_monitor(
jbus_j_ad,
jbus_j_req_out_l_0,
jbus_j_req_out_l_1,
jbus_j_req_out_l_2,
jbus_j_req_out_l_3,
jbus_j_req_out_l_4,
jbus_j_req_out_l_5,
jbus_j_req_out_l_6,
jbus_j_adp,
jbus_j_adtype,
jbus_j_pack0,
jbus_j_pack1,
jbus_j_pack2,
jbus_j_pack3,
jbus_j_pack4,
jbus_j_pack5,
jbus_j_pack6,
jbus_j_par,
jbus_j_rst,
jbus_j_por,
jbus_j_clk,
jbus_j_err,
jbus_j_change_l,
local_ports
);
input [5:0] jbus_j_req_out_l_0;
input [5:0] jbus_j_req_out_l_1;
input [5:0] jbus_j_req_out_l_2;
input [5:0] jbus_j_req_out_l_3;
input [5:0] jbus_j_req_out_l_4;
input [5:0] jbus_j_req_out_l_5;
input [5:0] jbus_j_req_out_l_6;
inout [127:0] jbus_j_ad;
inout [7:0] jbus_j_adtype;
inout [3:0] jbus_j_adp;
input [2:0] jbus_j_pack0;
input [2:0] jbus_j_pack1;
input [2:0] jbus_j_pack2;
input [2:0] jbus_j_pack3;
input [2:0] jbus_j_pack4;
input [2:0] jbus_j_pack5;
input [2:0] jbus_j_pack6;
input jbus_j_par;
input jbus_j_rst;
input jbus_j_por;
input jbus_j_clk;
input [6:0] local_ports;
input [6:0] jbus_j_err;
input jbus_j_change_l;
reg [5:0] j_req_out_l_0;
reg [5:0] j_req_out_l_1;
reg [5:0] j_req_out_l_2;
reg [5:0] j_req_out_l_3;
reg [5:0] j_req_out_l_4;
reg [5:0] j_req_out_l_5;
reg [5:0] j_req_out_l_6;
reg [6:0] j_err;
reg j_change_l;
reg [127:0] j_ad;
reg [7:0] j_adtype;
reg [3:0] j_adp;
reg [2:0] j_pack0;
reg [2:0] j_pack1;
reg [2:0] j_pack2;
reg [2:0] j_pack3;
reg [2:0] j_pack4;
reg [2:0] j_pack5;
reg [2:0] j_pack6;
reg j_par;
reg j_rst;
reg j_clk;
reg j_por;
reg [127:0] transaction_name;
wire [127:0] jbus_transaction;
reg bus_is_idle;
reg uncompleted_accesses;
`ifdef NO_JBUS_MON
`else
initial begin
j_rst = 1'b0;
$new_jbus_mon_cycle(
j_ad, j_adtype, j_adp,
j_req_out_l_0, j_req_out_l_1, j_req_out_l_2,
j_req_out_l_3, j_req_out_l_4, j_req_out_l_5,
j_req_out_l_6,
j_pack0, j_pack1, j_pack2,
j_pack3, j_pack4, j_pack5, j_pack6, j_par, j_rst, j_por, local_ports, j_err, j_change_l);
$new_jbus_check_cycle(
j_ad, j_adtype, j_adp,
j_req_out_l_0, j_req_out_l_1, j_req_out_l_2,
j_req_out_l_3, j_req_out_l_4, j_req_out_l_5,
j_req_out_l_6,
j_pack0, j_pack1, j_pack2,
j_pack3, j_pack4, j_pack5, j_pack6, j_par, j_rst, j_por, local_ports, j_err, j_change_l);
end
always @(posedge jbus_j_clk) begin
//$display("%b %h %h %b", jbus_j_req, jbus_j_ad[127:64], jbus_j_ad[63:0], jbus_j_adtype);
$new_jbus_mon_cycle(
jbus_j_ad, jbus_j_adtype, jbus_j_adp,
jbus_j_req_out_l_0, jbus_j_req_out_l_1, jbus_j_req_out_l_2,
jbus_j_req_out_l_3, jbus_j_req_out_l_4, jbus_j_req_out_l_5,
jbus_j_req_out_l_6,
jbus_j_pack0, jbus_j_pack1, jbus_j_pack2,
jbus_j_pack3, jbus_j_pack4, jbus_j_pack5, jbus_j_pack6,
jbus_j_par, jbus_j_rst, jbus_j_por,
local_ports, jbus_j_err, jbus_j_change_l);
$new_jbus_check_cycle(
jbus_j_ad, jbus_j_adtype, jbus_j_adp,
jbus_j_req_out_l_0, jbus_j_req_out_l_1, jbus_j_req_out_l_2,
jbus_j_req_out_l_3, jbus_j_req_out_l_4, jbus_j_req_out_l_5,
jbus_j_req_out_l_6,
jbus_j_pack0, jbus_j_pack1, jbus_j_pack2,
jbus_j_pack3, jbus_j_pack4, jbus_j_pack5, jbus_j_pack6,
jbus_j_par, jbus_j_rst, jbus_j_por,
local_ports, jbus_j_err, jbus_j_change_l);
#1
$jbus_mon_outputs(bus_is_idle, uncompleted_accesses);
$jbus_check_outputs(j_ad, j_adtype, j_adp, transaction_name);
end
assign jbus_j_ad = j_ad;
assign jbus_j_adp = j_adp;
assign jbus_j_adtype = j_adtype;
assign jbus_transaction = transaction_name;
`endif
endmodule
|
module test_bsg;
reg div_req;
reg signed_div;
wire ready_and_o;
wire done;
reg reset;
reg clk;
integer i, f1, f2, f3, f4;
reg [`WIDTH-1:0] dividend;
reg [`WIDTH-1:0] divisor;
wire [`WIDTH-1:0] quotient;
wire [`WIDTH-1:0] remainder;
reg [`WIDTH-1:0] u_dividend;
reg [`WIDTH-1:0] u_divisor;
reg [`WIDTH-1:0] u_quotient;
reg [`WIDTH-1:0] u_remainder;
longint s_dividend;
longint s_divisor;
longint s_quotient;
longint s_remainder;
bsg_idiv_iterative #(.width_p(`WIDTH)) dut (
.dividend_i(dividend),
.divisor_i(divisor),
.v_i(div_req),
.signed_div_i(signed_div),
.quotient_o(quotient),
.remainder_o(remainder),
.ready_and_o( ready_and_o ),
.v_o(done),
.yumi_i( done ),
.reset_i(reset),
.clk_i(clk));
initial clk = 0;
initial reset = 1;
initial #15 reset = 0;
always #10 clk = ~clk;
initial #25 begin
$init();
f1 = $fopen("s_output.txt","w");
f2 = $fopen("u_output.txt","w");
f3 = $fopen("s.txt","w");
f4 = $fopen("u.txt","w");
for (i=0; i<`ITERS; i=i+1) begin
$get_stim(dividend, divisor);
// do the signed case
`ifdef SIGN
s_dividend = {{(64 - `WIDTH){dividend[`WIDTH-1]}}, dividend[`WIDTH-1:0]};
s_divisor = {{(64 - `WIDTH){divisor[`WIDTH-1]}}, divisor[`WIDTH-1:0]};
signed_div = 1;
wait (ready_and_o == 1);
div_req = 1;
wait (ready_and_o == 0);
div_req = 0;
wait (done == 1);
s_quotient = {{(64 - `WIDTH){quotient[`WIDTH-1]}}, quotient[`WIDTH-1:0]};
s_remainder = {{(64 - `WIDTH){remainder[`WIDTH-1]}}, remainder[`WIDTH-1:0]};
$fwrite(f1,"%d %d %d %d\n", s_dividend, s_divisor, s_quotient, s_remainder);
$fwrite(f3,"%d %d\n", s_dividend, s_divisor);
`endif
// do the unsigned case
`ifdef UNSIGN
u_dividend = dividend;
u_divisor = divisor;
signed_div = 0;
wait (ready_and_o == 1);
div_req = 1;
wait (ready_and_o == 0);
div_req = 0;
wait (done == 1);
u_quotient = quotient;
u_remainder = remainder;
$fwrite(f2,"%d %d %d %d\n", u_dividend, u_divisor, u_quotient, u_remainder);
$fwrite(f4,"%d %d\n", u_dividend, u_divisor);
`endif
end
$fclose(f1);
$fclose(f2);
$fclose(f3);
$fclose(f4);
$done;
#80 $finish;
end
endmodule
|
module system_auto_us_0
(s_axi_aclk,
s_axi_aresetn,
s_axi_awaddr,
s_axi_awlen,
s_axi_awsize,
s_axi_awburst,
s_axi_awlock,
s_axi_awcache,
s_axi_awprot,
s_axi_awregion,
s_axi_awqos,
s_axi_awvalid,
s_axi_awready,
s_axi_wdata,
s_axi_wstrb,
s_axi_wlast,
s_axi_wvalid,
s_axi_wready,
s_axi_bresp,
s_axi_bvalid,
s_axi_bready,
s_axi_araddr,
s_axi_arlen,
s_axi_arsize,
s_axi_arburst,
s_axi_arlock,
s_axi_arcache,
s_axi_arprot,
s_axi_arregion,
s_axi_arqos,
s_axi_arvalid,
s_axi_arready,
s_axi_rdata,
s_axi_rresp,
s_axi_rlast,
s_axi_rvalid,
s_axi_rready,
m_axi_awaddr,
m_axi_awlen,
m_axi_awsize,
m_axi_awburst,
m_axi_awlock,
m_axi_awcache,
m_axi_awprot,
m_axi_awregion,
m_axi_awqos,
m_axi_awvalid,
m_axi_awready,
m_axi_wdata,
m_axi_wstrb,
m_axi_wlast,
m_axi_wvalid,
m_axi_wready,
m_axi_bresp,
m_axi_bvalid,
m_axi_bready,
m_axi_araddr,
m_axi_arlen,
m_axi_arsize,
m_axi_arburst,
m_axi_arlock,
m_axi_arcache,
m_axi_arprot,
m_axi_arregion,
m_axi_arqos,
m_axi_arvalid,
m_axi_arready,
m_axi_rdata,
m_axi_rresp,
m_axi_rlast,
m_axi_rvalid,
m_axi_rready);
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 SI_CLK CLK" *) input s_axi_aclk;
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 SI_RST RST" *) input s_axi_aresetn;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWADDR" *) input [31:0]s_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLEN" *) input [7:0]s_axi_awlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWSIZE" *) input [2:0]s_axi_awsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWBURST" *) input [1:0]s_axi_awburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLOCK" *) input [0:0]s_axi_awlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWCACHE" *) input [3:0]s_axi_awcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWPROT" *) input [2:0]s_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWREGION" *) input [3:0]s_axi_awregion;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWQOS" *) input [3:0]s_axi_awqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWVALID" *) input s_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWREADY" *) output s_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WDATA" *) input [31:0]s_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WSTRB" *) input [3:0]s_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WLAST" *) input s_axi_wlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WVALID" *) input s_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WREADY" *) output s_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BRESP" *) output [1:0]s_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BVALID" *) output s_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BREADY" *) input s_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARADDR" *) input [31:0]s_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLEN" *) input [7:0]s_axi_arlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARSIZE" *) input [2:0]s_axi_arsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARBURST" *) input [1:0]s_axi_arburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLOCK" *) input [0:0]s_axi_arlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARCACHE" *) input [3:0]s_axi_arcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARPROT" *) input [2:0]s_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARREGION" *) input [3:0]s_axi_arregion;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARQOS" *) input [3:0]s_axi_arqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARVALID" *) input s_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARREADY" *) output s_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RDATA" *) output [31:0]s_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RRESP" *) output [1:0]s_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RLAST" *) output s_axi_rlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RVALID" *) output s_axi_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RREADY" *) input s_axi_rready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWADDR" *) output [31:0]m_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWLEN" *) output [7:0]m_axi_awlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWSIZE" *) output [2:0]m_axi_awsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWBURST" *) output [1:0]m_axi_awburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWLOCK" *) output [0:0]m_axi_awlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWCACHE" *) output [3:0]m_axi_awcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWPROT" *) output [2:0]m_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWREGION" *) output [3:0]m_axi_awregion;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWQOS" *) output [3:0]m_axi_awqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWVALID" *) output m_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWREADY" *) input m_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WDATA" *) output [63:0]m_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WSTRB" *) output [7:0]m_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WLAST" *) output m_axi_wlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WVALID" *) output m_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WREADY" *) input m_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BRESP" *) input [1:0]m_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BVALID" *) input m_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BREADY" *) output m_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARADDR" *) output [31:0]m_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARLEN" *) output [7:0]m_axi_arlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARSIZE" *) output [2:0]m_axi_arsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARBURST" *) output [1:0]m_axi_arburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARLOCK" *) output [0:0]m_axi_arlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARCACHE" *) output [3:0]m_axi_arcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARPROT" *) output [2:0]m_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARREGION" *) output [3:0]m_axi_arregion;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARQOS" *) output [3:0]m_axi_arqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARVALID" *) output m_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARREADY" *) input m_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RDATA" *) input [63:0]m_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RRESP" *) input [1:0]m_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RLAST" *) input m_axi_rlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RVALID" *) input m_axi_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RREADY" *) output m_axi_rready;
wire [31:0]m_axi_araddr;
wire [1:0]m_axi_arburst;
wire [3:0]m_axi_arcache;
wire [7:0]m_axi_arlen;
wire [0:0]m_axi_arlock;
wire [2:0]m_axi_arprot;
wire [3:0]m_axi_arqos;
wire m_axi_arready;
wire [3:0]m_axi_arregion;
wire [2:0]m_axi_arsize;
wire m_axi_arvalid;
wire [31:0]m_axi_awaddr;
wire [1:0]m_axi_awburst;
wire [3:0]m_axi_awcache;
wire [7:0]m_axi_awlen;
wire [0:0]m_axi_awlock;
wire [2:0]m_axi_awprot;
wire [3:0]m_axi_awqos;
wire m_axi_awready;
wire [3:0]m_axi_awregion;
wire [2:0]m_axi_awsize;
wire m_axi_awvalid;
wire m_axi_bready;
wire [1:0]m_axi_bresp;
wire m_axi_bvalid;
wire [63:0]m_axi_rdata;
wire m_axi_rlast;
wire m_axi_rready;
wire [1:0]m_axi_rresp;
wire m_axi_rvalid;
wire [63:0]m_axi_wdata;
wire m_axi_wlast;
wire m_axi_wready;
wire [7:0]m_axi_wstrb;
wire m_axi_wvalid;
wire s_axi_aclk;
wire [31:0]s_axi_araddr;
wire [1:0]s_axi_arburst;
wire [3:0]s_axi_arcache;
wire s_axi_aresetn;
wire [7:0]s_axi_arlen;
wire [0:0]s_axi_arlock;
wire [2:0]s_axi_arprot;
wire [3:0]s_axi_arqos;
wire s_axi_arready;
wire [3:0]s_axi_arregion;
wire [2:0]s_axi_arsize;
wire s_axi_arvalid;
wire [31:0]s_axi_awaddr;
wire [1:0]s_axi_awburst;
wire [3:0]s_axi_awcache;
wire [7:0]s_axi_awlen;
wire [0:0]s_axi_awlock;
wire [2:0]s_axi_awprot;
wire [3:0]s_axi_awqos;
wire s_axi_awready;
wire [3:0]s_axi_awregion;
wire [2:0]s_axi_awsize;
wire s_axi_awvalid;
wire s_axi_bready;
wire [1:0]s_axi_bresp;
wire s_axi_bvalid;
wire [31:0]s_axi_rdata;
wire s_axi_rlast;
wire s_axi_rready;
wire [1:0]s_axi_rresp;
wire s_axi_rvalid;
wire [31:0]s_axi_wdata;
wire s_axi_wlast;
wire s_axi_wready;
wire [3:0]s_axi_wstrb;
wire s_axi_wvalid;
wire [0:0]NLW_inst_s_axi_bid_UNCONNECTED;
wire [0:0]NLW_inst_s_axi_rid_UNCONNECTED;
(* C_AXI_ADDR_WIDTH = "32" *)
(* C_AXI_IS_ACLK_ASYNC = "0" *)
(* C_AXI_PROTOCOL = "0" *)
(* C_AXI_SUPPORTS_READ = "1" *)
(* C_AXI_SUPPORTS_WRITE = "1" *)
(* C_FAMILY = "zynq" *)
(* C_FIFO_MODE = "0" *)
(* C_MAX_SPLIT_BEATS = "16" *)
(* C_M_AXI_ACLK_RATIO = "2" *)
(* C_M_AXI_BYTES_LOG = "3" *)
(* C_M_AXI_DATA_WIDTH = "64" *)
(* C_PACKING_LEVEL = "1" *)
(* C_RATIO = "0" *)
(* C_RATIO_LOG = "0" *)
(* C_SUPPORTS_ID = "0" *)
(* C_SYNCHRONIZER_STAGE = "3" *)
(* C_S_AXI_ACLK_RATIO = "1" *)
(* C_S_AXI_BYTES_LOG = "2" *)
(* C_S_AXI_DATA_WIDTH = "32" *)
(* C_S_AXI_ID_WIDTH = "1" *)
(* DowngradeIPIdentifiedWarnings = "yes" *)
(* P_AXI3 = "1" *)
(* P_AXI4 = "0" *)
(* P_AXILITE = "2" *)
(* P_CONVERSION = "2" *)
(* P_MAX_SPLIT_BEATS = "16" *)
system_auto_us_0_axi_dwidth_converter_v2_1_11_top inst
(.m_axi_aclk(1'b0),
.m_axi_araddr(m_axi_araddr),
.m_axi_arburst(m_axi_arburst),
.m_axi_arcache(m_axi_arcache),
.m_axi_aresetn(1'b0),
.m_axi_arlen(m_axi_arlen),
.m_axi_arlock(m_axi_arlock),
.m_axi_arprot(m_axi_arprot),
.m_axi_arqos(m_axi_arqos),
.m_axi_arready(m_axi_arready),
.m_axi_arregion(m_axi_arregion),
.m_axi_arsize(m_axi_arsize),
.m_axi_arvalid(m_axi_arvalid),
.m_axi_awaddr(m_axi_awaddr),
.m_axi_awburst(m_axi_awburst),
.m_axi_awcache(m_axi_awcache),
.m_axi_awlen(m_axi_awlen),
.m_axi_awlock(m_axi_awlock),
.m_axi_awprot(m_axi_awprot),
.m_axi_awqos(m_axi_awqos),
.m_axi_awready(m_axi_awready),
.m_axi_awregion(m_axi_awregion),
.m_axi_awsize(m_axi_awsize),
.m_axi_awvalid(m_axi_awvalid),
.m_axi_bready(m_axi_bready),
.m_axi_bresp(m_axi_bresp),
.m_axi_bvalid(m_axi_bvalid),
.m_axi_rdata(m_axi_rdata),
.m_axi_rlast(m_axi_rlast),
.m_axi_rready(m_axi_rready),
.m_axi_rresp(m_axi_rresp),
.m_axi_rvalid(m_axi_rvalid),
.m_axi_wdata(m_axi_wdata),
.m_axi_wlast(m_axi_wlast),
.m_axi_wready(m_axi_wready),
.m_axi_wstrb(m_axi_wstrb),
.m_axi_wvalid(m_axi_wvalid),
.s_axi_aclk(s_axi_aclk),
.s_axi_araddr(s_axi_araddr),
.s_axi_arburst(s_axi_arburst),
.s_axi_arcache(s_axi_arcache),
.s_axi_aresetn(s_axi_aresetn),
.s_axi_arid(1'b0),
.s_axi_arlen(s_axi_arlen),
.s_axi_arlock(s_axi_arlock),
.s_axi_arprot(s_axi_arprot),
.s_axi_arqos(s_axi_arqos),
.s_axi_arready(s_axi_arready),
.s_axi_arregion(s_axi_arregion),
.s_axi_arsize(s_axi_arsize),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_awaddr(s_axi_awaddr),
.s_axi_awburst(s_axi_awburst),
.s_axi_awcache(s_axi_awcache),
.s_axi_awid(1'b0),
.s_axi_awlen(s_axi_awlen),
.s_axi_awlock(s_axi_awlock),
.s_axi_awprot(s_axi_awprot),
.s_axi_awqos(s_axi_awqos),
.s_axi_awready(s_axi_awready),
.s_axi_awregion(s_axi_awregion),
.s_axi_awsize(s_axi_awsize),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_bid(NLW_inst_s_axi_bid_UNCONNECTED[0]),
.s_axi_bready(s_axi_bready),
.s_axi_bresp(s_axi_bresp),
.s_axi_bvalid(s_axi_bvalid),
.s_axi_rdata(s_axi_rdata),
.s_axi_rid(NLW_inst_s_axi_rid_UNCONNECTED[0]),
.s_axi_rlast(s_axi_rlast),
.s_axi_rready(s_axi_rready),
.s_axi_rresp(s_axi_rresp),
.s_axi_rvalid(s_axi_rvalid),
.s_axi_wdata(s_axi_wdata),
.s_axi_wlast(s_axi_wlast),
.s_axi_wready(s_axi_wready),
.s_axi_wstrb(s_axi_wstrb),
.s_axi_wvalid(s_axi_wvalid));
endmodule
|
module system_auto_us_0_axi_dwidth_converter_v2_1_11_a_upsizer
(wr_cmd_valid,
SR,
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29] ,
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[0] ,
Q,
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]_0 ,
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[56] ,
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[7] ,
\USE_RTL_CURR_WORD.pre_next_word_q_reg[1] ,
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[48] ,
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[6] ,
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[40] ,
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[5] ,
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[32] ,
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[4] ,
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[24] ,
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[3] ,
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[16] ,
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[2] ,
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[8] ,
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[1] ,
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[0]_0 ,
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[0] ,
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg[63] ,
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg[55] ,
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg[47] ,
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg[39] ,
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg[31] ,
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg[23] ,
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg[15] ,
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg[7] ,
E,
s_axi_wready,
\USE_RTL_LENGTH.first_mi_word_q_reg ,
\USE_RTL_LENGTH.first_mi_word_q_reg_0 ,
D,
\USE_RTL_CURR_WORD.current_word_q_reg[2] ,
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[0]_1 ,
s_ready_i_reg,
m_axi_awvalid,
wrap_buffer_available_reg,
\USE_REGISTER.M_AXI_WVALID_q_reg ,
s_axi_aresetn,
s_axi_aclk,
s_axi_wlast,
p_251_in,
out,
\USE_RTL_CURR_WORD.current_word_q_reg[0] ,
\USE_REGISTER.M_AXI_WVALID_q_reg_0 ,
m_axi_wready,
\USE_REGISTER.M_AXI_WVALID_q_reg_1 ,
wrap_buffer_available,
s_axi_wvalid,
first_word_q,
\USE_RTL_CURR_WORD.current_word_q_reg[2]_0 ,
s_axi_wstrb,
sr_awvalid,
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28] ,
\USE_RTL_LENGTH.length_counter_q_reg[2] ,
\USE_RTL_LENGTH.length_counter_q_reg[5] ,
\USE_RTL_LENGTH.length_counter_q_reg[3] ,
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[7] ,
\USE_RTL_CURR_WORD.pre_next_word_q_reg[2] ,
\USE_RTL_CURR_WORD.pre_next_word_q_reg[2]_0 ,
\USE_RTL_CURR_WORD.pre_next_word_q_reg[1]_0 ,
\USE_RTL_LENGTH.length_counter_q_reg[0] ,
m_axi_awready,
in);
output wr_cmd_valid;
output [0:0]SR;
output \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29] ;
output \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[0] ;
output [14:0]Q;
output \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]_0 ;
output \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[56] ;
output \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[7] ;
output \USE_RTL_CURR_WORD.pre_next_word_q_reg[1] ;
output \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[48] ;
output \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[6] ;
output \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[40] ;
output \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[5] ;
output \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[32] ;
output \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[4] ;
output \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[24] ;
output \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[3] ;
output \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[16] ;
output \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[2] ;
output \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[8] ;
output \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[1] ;
output \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[0]_0 ;
output \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[0] ;
output [0:0]\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg[63] ;
output [0:0]\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg[55] ;
output [0:0]\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg[47] ;
output [0:0]\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg[39] ;
output [0:0]\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg[31] ;
output [0:0]\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg[23] ;
output [0:0]\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg[15] ;
output [0:0]\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg[7] ;
output [0:0]E;
output s_axi_wready;
output \USE_RTL_LENGTH.first_mi_word_q_reg ;
output \USE_RTL_LENGTH.first_mi_word_q_reg_0 ;
output [2:0]D;
output [2:0]\USE_RTL_CURR_WORD.current_word_q_reg[2] ;
output \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[0]_1 ;
output s_ready_i_reg;
output m_axi_awvalid;
output wrap_buffer_available_reg;
output \USE_REGISTER.M_AXI_WVALID_q_reg ;
input s_axi_aresetn;
input s_axi_aclk;
input s_axi_wlast;
input p_251_in;
input out;
input \USE_RTL_CURR_WORD.current_word_q_reg[0] ;
input \USE_REGISTER.M_AXI_WVALID_q_reg_0 ;
input m_axi_wready;
input \USE_REGISTER.M_AXI_WVALID_q_reg_1 ;
input wrap_buffer_available;
input s_axi_wvalid;
input first_word_q;
input [2:0]\USE_RTL_CURR_WORD.current_word_q_reg[2]_0 ;
input [3:0]s_axi_wstrb;
input sr_awvalid;
input \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28] ;
input \USE_RTL_LENGTH.length_counter_q_reg[2] ;
input \USE_RTL_LENGTH.length_counter_q_reg[5] ;
input \USE_RTL_LENGTH.length_counter_q_reg[3] ;
input \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[7] ;
input [2:0]\USE_RTL_CURR_WORD.pre_next_word_q_reg[2] ;
input \USE_RTL_CURR_WORD.pre_next_word_q_reg[2]_0 ;
input \USE_RTL_CURR_WORD.pre_next_word_q_reg[1]_0 ;
input \USE_RTL_LENGTH.length_counter_q_reg[0] ;
input m_axi_awready;
input [27:0]in;
wire [2:0]D;
wire [0:0]E;
wire [14:0]Q;
wire [0:0]SR;
wire \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28] ;
wire \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29] ;
wire \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]_0 ;
wire \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[7] ;
wire \USE_REGISTER.M_AXI_WVALID_q_reg ;
wire \USE_REGISTER.M_AXI_WVALID_q_reg_0 ;
wire \USE_REGISTER.M_AXI_WVALID_q_reg_1 ;
wire \USE_RTL_CURR_WORD.current_word_q_reg[0] ;
wire [2:0]\USE_RTL_CURR_WORD.current_word_q_reg[2] ;
wire [2:0]\USE_RTL_CURR_WORD.current_word_q_reg[2]_0 ;
wire \USE_RTL_CURR_WORD.pre_next_word_q_reg[1] ;
wire \USE_RTL_CURR_WORD.pre_next_word_q_reg[1]_0 ;
wire [2:0]\USE_RTL_CURR_WORD.pre_next_word_q_reg[2] ;
wire \USE_RTL_CURR_WORD.pre_next_word_q_reg[2]_0 ;
wire \USE_RTL_LENGTH.first_mi_word_q_reg ;
wire \USE_RTL_LENGTH.first_mi_word_q_reg_0 ;
wire \USE_RTL_LENGTH.length_counter_q_reg[0] ;
wire \USE_RTL_LENGTH.length_counter_q_reg[2] ;
wire \USE_RTL_LENGTH.length_counter_q_reg[3] ;
wire \USE_RTL_LENGTH.length_counter_q_reg[5] ;
wire \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[0] ;
wire \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[0]_0 ;
wire \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[0]_1 ;
wire \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[0] ;
wire [0:0]\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg[7] ;
wire \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[8] ;
wire \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[1] ;
wire [0:0]\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg[15] ;
wire \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[16] ;
wire \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[2] ;
wire [0:0]\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg[23] ;
wire \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[24] ;
wire \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[3] ;
wire [0:0]\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg[31] ;
wire \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[32] ;
wire \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[4] ;
wire [0:0]\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg[39] ;
wire \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[40] ;
wire \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[5] ;
wire [0:0]\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg[47] ;
wire \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[48] ;
wire \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[6] ;
wire [0:0]\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg[55] ;
wire \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[56] ;
wire \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[7] ;
wire [0:0]\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg[63] ;
wire cmd_push_block;
wire cmd_push_block0;
wire first_word_q;
wire [27:0]in;
wire m_axi_awready;
wire m_axi_awvalid;
wire m_axi_wready;
wire out;
wire p_251_in;
wire s_axi_aclk;
wire s_axi_aresetn;
wire s_axi_wlast;
wire s_axi_wready;
wire [3:0]s_axi_wstrb;
wire s_axi_wvalid;
wire s_ready_i_reg;
wire sr_awvalid;
wire wr_cmd_valid;
wire wrap_buffer_available;
wire wrap_buffer_available_reg;
system_auto_us_0_generic_baseblocks_v2_1_0_command_fifo \GEN_CMD_QUEUE.cmd_queue
(.D(D),
.E(E),
.Q(Q),
.SR(SR),
.\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28]_0 (\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28] ),
.\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]_0 (\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29] ),
.\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]_1 (\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]_0 ),
.\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[7]_0 (\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[7] ),
.\USE_REGISTER.M_AXI_WVALID_q_reg (\USE_REGISTER.M_AXI_WVALID_q_reg ),
.\USE_REGISTER.M_AXI_WVALID_q_reg_0 (\USE_REGISTER.M_AXI_WVALID_q_reg_0 ),
.\USE_REGISTER.M_AXI_WVALID_q_reg_1 (\USE_REGISTER.M_AXI_WVALID_q_reg_1 ),
.\USE_RTL_CURR_WORD.current_word_q_reg[0] (\USE_RTL_CURR_WORD.current_word_q_reg[0] ),
.\USE_RTL_CURR_WORD.current_word_q_reg[2] (\USE_RTL_CURR_WORD.current_word_q_reg[2] ),
.\USE_RTL_CURR_WORD.current_word_q_reg[2]_0 (\USE_RTL_CURR_WORD.current_word_q_reg[2]_0 ),
.\USE_RTL_CURR_WORD.first_word_q_reg (wr_cmd_valid),
.\USE_RTL_CURR_WORD.pre_next_word_q_reg[1] (\USE_RTL_CURR_WORD.pre_next_word_q_reg[1] ),
.\USE_RTL_CURR_WORD.pre_next_word_q_reg[1]_0 (\USE_RTL_CURR_WORD.pre_next_word_q_reg[1]_0 ),
.\USE_RTL_CURR_WORD.pre_next_word_q_reg[2] (\USE_RTL_CURR_WORD.pre_next_word_q_reg[2] ),
.\USE_RTL_CURR_WORD.pre_next_word_q_reg[2]_0 (\USE_RTL_CURR_WORD.pre_next_word_q_reg[2]_0 ),
.\USE_RTL_LENGTH.first_mi_word_q_reg (\USE_RTL_LENGTH.first_mi_word_q_reg ),
.\USE_RTL_LENGTH.first_mi_word_q_reg_0 (\USE_RTL_LENGTH.first_mi_word_q_reg_0 ),
.\USE_RTL_LENGTH.length_counter_q_reg[0] (\USE_RTL_LENGTH.length_counter_q_reg[0] ),
.\USE_RTL_LENGTH.length_counter_q_reg[2] (\USE_RTL_LENGTH.length_counter_q_reg[2] ),
.\USE_RTL_LENGTH.length_counter_q_reg[3] (\USE_RTL_LENGTH.length_counter_q_reg[3] ),
.\USE_RTL_LENGTH.length_counter_q_reg[5] (\USE_RTL_LENGTH.length_counter_q_reg[5] ),
.\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[0] (\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[0] ),
.\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[0]_0 (\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[0]_0 ),
.\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[0]_1 (\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[0]_1 ),
.\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[0] (\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[0] ),
.\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg[7] (\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg[7] ),
.\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[8] (\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[8] ),
.\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[1] (\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[1] ),
.\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg[15] (\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg[15] ),
.\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[16] (\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[16] ),
.\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[2] (\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[2] ),
.\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg[23] (\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg[23] ),
.\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[24] (\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[24] ),
.\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[3] (\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[3] ),
.\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg[31] (\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg[31] ),
.\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[32] (\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[32] ),
.\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[4] (\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[4] ),
.\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg[39] (\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg[39] ),
.\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[40] (\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[40] ),
.\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[5] (\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[5] ),
.\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg[47] (\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg[47] ),
.\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[48] (\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[48] ),
.\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[6] (\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[6] ),
.\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg[55] (\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg[55] ),
.\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[56] (\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[56] ),
.\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[7] (\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[7] ),
.\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg[63] (\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg[63] ),
.cmd_push_block(cmd_push_block),
.cmd_push_block0(cmd_push_block0),
.first_word_q(first_word_q),
.in(in),
.m_axi_awready(m_axi_awready),
.m_axi_awvalid(m_axi_awvalid),
.m_axi_wready(m_axi_wready),
.out(out),
.p_251_in(p_251_in),
.s_axi_aclk(s_axi_aclk),
.s_axi_aresetn(s_axi_aresetn),
.s_axi_wlast(s_axi_wlast),
.s_axi_wready(s_axi_wready),
.s_axi_wstrb(s_axi_wstrb),
.s_axi_wvalid(s_axi_wvalid),
.s_ready_i_reg(s_ready_i_reg),
.sr_awvalid(sr_awvalid),
.wrap_buffer_available(wrap_buffer_available),
.wrap_buffer_available_reg(wrap_buffer_available_reg));
FDRE cmd_push_block_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(cmd_push_block0),
.Q(cmd_push_block),
.R(s_axi_aresetn));
endmodule
|
module system_auto_us_0_axi_dwidth_converter_v2_1_11_a_upsizer__parameterized0
(rd_cmd_valid,
E,
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29] ,
\s_axi_rdata[31] ,
Q,
pop_mi_data,
\USE_RTL_LENGTH.first_mi_word_q_reg ,
first_word_reg,
D,
\current_word_1_reg[2] ,
s_axi_rvalid,
\M_AXI_RDATA_I_reg[63] ,
s_ready_i_reg,
m_axi_arvalid,
s_axi_aresetn,
s_axi_aclk,
wrap_buffer_available,
\USE_RTL_LENGTH.length_counter_q_reg[7] ,
use_wrap_buffer,
first_word,
\current_word_1_reg[2]_0 ,
mr_rvalid,
s_axi_rready,
wrap_buffer_available_reg,
sr_arvalid,
wrap_buffer_available_reg_0,
\pre_next_word_1_reg[2] ,
\pre_next_word_1_reg[2]_0 ,
\pre_next_word_1_reg[1] ,
first_mi_word_q,
m_axi_arready,
out,
in);
output rd_cmd_valid;
output [0:0]E;
output \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29] ;
output \s_axi_rdata[31] ;
output [12:0]Q;
output pop_mi_data;
output \USE_RTL_LENGTH.first_mi_word_q_reg ;
output first_word_reg;
output [2:0]D;
output [2:0]\current_word_1_reg[2] ;
output s_axi_rvalid;
output [0:0]\M_AXI_RDATA_I_reg[63] ;
output s_ready_i_reg;
output m_axi_arvalid;
input s_axi_aresetn;
input s_axi_aclk;
input wrap_buffer_available;
input \USE_RTL_LENGTH.length_counter_q_reg[7] ;
input use_wrap_buffer;
input first_word;
input [2:0]\current_word_1_reg[2]_0 ;
input mr_rvalid;
input s_axi_rready;
input wrap_buffer_available_reg;
input sr_arvalid;
input wrap_buffer_available_reg_0;
input [2:0]\pre_next_word_1_reg[2] ;
input \pre_next_word_1_reg[2]_0 ;
input \pre_next_word_1_reg[1] ;
input first_mi_word_q;
input m_axi_arready;
input out;
input [27:0]in;
wire [2:0]D;
wire [0:0]E;
wire [0:0]\M_AXI_RDATA_I_reg[63] ;
wire [12:0]Q;
wire \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29] ;
wire \USE_RTL_LENGTH.first_mi_word_q_reg ;
wire \USE_RTL_LENGTH.length_counter_q_reg[7] ;
wire cmd_push_block;
wire cmd_push_block0;
wire [2:0]\current_word_1_reg[2] ;
wire [2:0]\current_word_1_reg[2]_0 ;
wire first_mi_word_q;
wire first_word;
wire first_word_reg;
wire [27:0]in;
wire m_axi_arready;
wire m_axi_arvalid;
wire mr_rvalid;
wire out;
wire pop_mi_data;
wire \pre_next_word_1_reg[1] ;
wire [2:0]\pre_next_word_1_reg[2] ;
wire \pre_next_word_1_reg[2]_0 ;
wire rd_cmd_valid;
wire s_axi_aclk;
wire s_axi_aresetn;
wire \s_axi_rdata[31] ;
wire s_axi_rready;
wire s_axi_rvalid;
wire s_ready_i_reg;
wire sr_arvalid;
wire use_wrap_buffer;
wire wrap_buffer_available;
wire wrap_buffer_available_reg;
wire wrap_buffer_available_reg_0;
system_auto_us_0_generic_baseblocks_v2_1_0_command_fifo_1 \GEN_CMD_QUEUE.cmd_queue
(.D(D),
.E(E),
.\M_AXI_RDATA_I_reg[63] (rd_cmd_valid),
.\M_AXI_RDATA_I_reg[63]_0 (\M_AXI_RDATA_I_reg[63] ),
.Q(Q),
.\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]_0 (\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29] ),
.\USE_RTL_LENGTH.first_mi_word_q_reg (\USE_RTL_LENGTH.first_mi_word_q_reg ),
.\USE_RTL_LENGTH.length_counter_q_reg[7] (\USE_RTL_LENGTH.length_counter_q_reg[7] ),
.cmd_push_block(cmd_push_block),
.cmd_push_block0(cmd_push_block0),
.\current_word_1_reg[2] (\current_word_1_reg[2] ),
.\current_word_1_reg[2]_0 (\current_word_1_reg[2]_0 ),
.first_mi_word_q(first_mi_word_q),
.first_word(first_word),
.first_word_reg(first_word_reg),
.in(in),
.m_axi_arready(m_axi_arready),
.m_axi_arvalid(m_axi_arvalid),
.mr_rvalid(mr_rvalid),
.out(out),
.pop_mi_data(pop_mi_data),
.\pre_next_word_1_reg[1] (\pre_next_word_1_reg[1] ),
.\pre_next_word_1_reg[2] (\pre_next_word_1_reg[2] ),
.\pre_next_word_1_reg[2]_0 (\pre_next_word_1_reg[2]_0 ),
.s_axi_aclk(s_axi_aclk),
.s_axi_aresetn(s_axi_aresetn),
.\s_axi_rdata[31] (\s_axi_rdata[31] ),
.s_axi_rready(s_axi_rready),
.s_axi_rvalid(s_axi_rvalid),
.s_ready_i_reg(s_ready_i_reg),
.sr_arvalid(sr_arvalid),
.use_wrap_buffer(use_wrap_buffer),
.wrap_buffer_available(wrap_buffer_available),
.wrap_buffer_available_reg(wrap_buffer_available_reg),
.wrap_buffer_available_reg_0(wrap_buffer_available_reg_0));
FDRE cmd_push_block_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(cmd_push_block0),
.Q(cmd_push_block),
.R(s_axi_aresetn));
endmodule
|
module system_auto_us_0_axi_dwidth_converter_v2_1_11_axi_upsizer
(m_axi_wstrb,
m_axi_wvalid,
Q,
m_axi_awlen,
m_axi_arlen,
m_axi_wdata,
\m_axi_awregion[3] ,
m_axi_rready,
s_axi_rlast,
s_axi_awready,
s_axi_arready,
s_axi_wready,
m_axi_awvalid,
s_axi_rdata,
s_axi_rvalid,
m_axi_arvalid,
s_axi_rresp,
m_axi_awburst,
m_axi_awaddr,
m_axi_awsize,
m_axi_arsize,
m_axi_arburst,
m_axi_araddr,
m_axi_wlast,
m_axi_wready,
s_axi_wlast,
out,
s_axi_wvalid,
s_axi_wdata,
s_axi_aclk,
D,
m_axi_rlast,
m_axi_rresp,
m_axi_rdata,
\s_axi_arregion[3] ,
s_axi_awvalid,
s_axi_arvalid,
s_axi_wstrb,
m_axi_awready,
s_axi_rready,
m_axi_arready,
m_axi_rvalid);
output [7:0]m_axi_wstrb;
output m_axi_wvalid;
output [44:0]Q;
output [7:0]m_axi_awlen;
output [7:0]m_axi_arlen;
output [63:0]m_axi_wdata;
output [41:0]\m_axi_awregion[3] ;
output m_axi_rready;
output s_axi_rlast;
output s_axi_awready;
output s_axi_arready;
output s_axi_wready;
output m_axi_awvalid;
output [31:0]s_axi_rdata;
output s_axi_rvalid;
output m_axi_arvalid;
output [1:0]s_axi_rresp;
output [1:0]m_axi_awburst;
output [5:0]m_axi_awaddr;
output [2:0]m_axi_awsize;
output [2:0]m_axi_arsize;
output [1:0]m_axi_arburst;
output [2:0]m_axi_araddr;
output m_axi_wlast;
input m_axi_wready;
input s_axi_wlast;
input out;
input s_axi_wvalid;
input [31:0]s_axi_wdata;
input s_axi_aclk;
input [60:0]D;
input m_axi_rlast;
input [1:0]m_axi_rresp;
input [63:0]m_axi_rdata;
input [60:0]\s_axi_arregion[3] ;
input s_axi_awvalid;
input s_axi_arvalid;
input [3:0]s_axi_wstrb;
input m_axi_awready;
input s_axi_rready;
input m_axi_arready;
input m_axi_rvalid;
wire [60:0]D;
wire M_AXI_RLAST;
wire [44:0]Q;
wire \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_10 ;
wire \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_11 ;
wire \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_12 ;
wire \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_13 ;
wire \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_14 ;
wire \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_15 ;
wire \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_16 ;
wire \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_17 ;
wire \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_18 ;
wire \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_19 ;
wire \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_20 ;
wire \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_21 ;
wire \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_22 ;
wire \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_23 ;
wire \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_24 ;
wire \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_25 ;
wire \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_26 ;
wire \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_27 ;
wire \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_28 ;
wire \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_29 ;
wire \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_30 ;
wire \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_31 ;
wire \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_32 ;
wire \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_33 ;
wire \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_34 ;
wire \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_35 ;
wire \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_36 ;
wire \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_37 ;
wire \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_38 ;
wire \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_39 ;
wire \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_40 ;
wire \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_41 ;
wire \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_42 ;
wire \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_43 ;
wire \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_44 ;
wire \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_45 ;
wire \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_46 ;
wire \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_47 ;
wire \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_48 ;
wire \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_49 ;
wire \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_5 ;
wire \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_50 ;
wire \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_51 ;
wire \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_52 ;
wire \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_53 ;
wire \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_54 ;
wire \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_55 ;
wire \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_56 ;
wire \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_57 ;
wire \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_58 ;
wire \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_59 ;
wire \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_6 ;
wire \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_60 ;
wire \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_61 ;
wire \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_62 ;
wire \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_63 ;
wire \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_64 ;
wire \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_65 ;
wire \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_66 ;
wire \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_67 ;
wire \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_68 ;
wire \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_7 ;
wire \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_8 ;
wire \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_9 ;
wire \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_38 ;
wire \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_39 ;
wire \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_43 ;
wire \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_47 ;
wire \USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_48 ;
wire \USE_READ.read_addr_inst_n_10 ;
wire \USE_READ.read_addr_inst_n_11 ;
wire \USE_READ.read_addr_inst_n_12 ;
wire \USE_READ.read_addr_inst_n_13 ;
wire \USE_READ.read_addr_inst_n_14 ;
wire \USE_READ.read_addr_inst_n_15 ;
wire \USE_READ.read_addr_inst_n_16 ;
wire \USE_READ.read_addr_inst_n_18 ;
wire \USE_READ.read_addr_inst_n_19 ;
wire \USE_READ.read_addr_inst_n_2 ;
wire \USE_READ.read_addr_inst_n_28 ;
wire \USE_READ.read_addr_inst_n_3 ;
wire \USE_READ.read_addr_inst_n_8 ;
wire \USE_READ.read_addr_inst_n_9 ;
wire \USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst_n_1 ;
wire \USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst_n_14 ;
wire \USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst_n_15 ;
wire \USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst_n_16 ;
wire \USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst_n_17 ;
wire \USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst_n_18 ;
wire \USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst_n_19 ;
wire \USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst_n_20 ;
wire \USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst_n_21 ;
wire \USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst_n_25 ;
wire \USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst_n_26 ;
wire \USE_WRITE.write_addr_inst_n_1 ;
wire \USE_WRITE.write_addr_inst_n_11 ;
wire \USE_WRITE.write_addr_inst_n_12 ;
wire \USE_WRITE.write_addr_inst_n_13 ;
wire \USE_WRITE.write_addr_inst_n_14 ;
wire \USE_WRITE.write_addr_inst_n_15 ;
wire \USE_WRITE.write_addr_inst_n_16 ;
wire \USE_WRITE.write_addr_inst_n_17 ;
wire \USE_WRITE.write_addr_inst_n_18 ;
wire \USE_WRITE.write_addr_inst_n_19 ;
wire \USE_WRITE.write_addr_inst_n_2 ;
wire \USE_WRITE.write_addr_inst_n_20 ;
wire \USE_WRITE.write_addr_inst_n_21 ;
wire \USE_WRITE.write_addr_inst_n_22 ;
wire \USE_WRITE.write_addr_inst_n_23 ;
wire \USE_WRITE.write_addr_inst_n_24 ;
wire \USE_WRITE.write_addr_inst_n_25 ;
wire \USE_WRITE.write_addr_inst_n_26 ;
wire \USE_WRITE.write_addr_inst_n_27 ;
wire \USE_WRITE.write_addr_inst_n_28 ;
wire \USE_WRITE.write_addr_inst_n_29 ;
wire \USE_WRITE.write_addr_inst_n_3 ;
wire \USE_WRITE.write_addr_inst_n_30 ;
wire \USE_WRITE.write_addr_inst_n_31 ;
wire \USE_WRITE.write_addr_inst_n_32 ;
wire \USE_WRITE.write_addr_inst_n_33 ;
wire \USE_WRITE.write_addr_inst_n_34 ;
wire \USE_WRITE.write_addr_inst_n_35 ;
wire \USE_WRITE.write_addr_inst_n_36 ;
wire \USE_WRITE.write_addr_inst_n_37 ;
wire \USE_WRITE.write_addr_inst_n_47 ;
wire \USE_WRITE.write_addr_inst_n_48 ;
wire \USE_WRITE.write_addr_inst_n_55 ;
wire \USE_WRITE.write_addr_inst_n_56 ;
wire \USE_WRITE.write_addr_inst_n_58 ;
wire \USE_WRITE.write_addr_inst_n_59 ;
wire cmd_complete_wrap_i;
wire cmd_complete_wrap_i_6;
wire [2:0]cmd_first_word_i;
wire [2:0]cmd_first_word_i_4;
wire cmd_fix_i;
wire cmd_fix_i_8;
wire [0:0]cmd_last_word;
wire cmd_modified_i;
wire cmd_modified_i_7;
wire cmd_packed_wrap_i;
wire cmd_packed_wrap_i_5;
wire [2:0]current_word_1;
wire [2:0]current_word_q;
wire first_mi_word_q;
wire first_word;
wire first_word_q;
wire [2:0]m_axi_araddr;
wire [1:0]m_axi_arburst;
wire [7:0]m_axi_arlen;
wire m_axi_arready;
wire [2:0]m_axi_arsize;
wire m_axi_arvalid;
wire [5:0]m_axi_awaddr;
wire [1:0]m_axi_awburst;
wire [7:0]m_axi_awlen;
wire m_axi_awready;
wire [41:0]\m_axi_awregion[3] ;
wire [2:0]m_axi_awsize;
wire m_axi_awvalid;
wire [63:0]m_axi_rdata;
wire m_axi_rlast;
wire m_axi_rready;
wire [1:0]m_axi_rresp;
wire m_axi_rvalid;
wire [63:0]m_axi_wdata;
wire m_axi_wlast;
wire m_axi_wready;
wire [7:0]m_axi_wstrb;
wire m_axi_wvalid;
wire [1:0]mr_rresp;
wire mr_rvalid;
wire [2:0]next_word;
wire [2:0]next_word_1;
wire out;
wire p_102_out;
wire p_131_out;
wire p_15_in;
wire p_160_out;
wire p_189_out;
wire [22:16]p_1_out;
wire [22:16]p_1_out_3;
wire p_222_out;
wire p_251_in;
wire p_41_out;
wire p_71_out;
wire p_7_in;
wire pop_mi_data;
wire pop_si_data;
wire [2:0]pre_next_word;
wire [2:0]pre_next_word_1;
wire [2:0]pre_next_word_2;
wire [2:0]pre_next_word_q;
wire \r_pipe/p_1_in ;
wire [2:2]rd_cmd_first_word;
wire rd_cmd_fix;
wire [2:1]rd_cmd_next_word;
wire rd_cmd_valid;
wire s_axi_aclk;
wire s_axi_arready;
wire [60:0]\s_axi_arregion[3] ;
wire s_axi_arvalid;
wire s_axi_awready;
wire s_axi_awvalid;
wire [31:0]s_axi_rdata;
wire s_axi_rlast;
wire s_axi_rready;
wire [1:0]s_axi_rresp;
wire s_axi_rvalid;
wire [31:0]s_axi_wdata;
wire s_axi_wlast;
wire s_axi_wready;
wire [3:0]s_axi_wstrb;
wire s_axi_wvalid;
wire si_register_slice_inst_n_0;
wire si_register_slice_inst_n_1;
wire si_register_slice_inst_n_109;
wire si_register_slice_inst_n_110;
wire si_register_slice_inst_n_111;
wire si_register_slice_inst_n_112;
wire si_register_slice_inst_n_113;
wire si_register_slice_inst_n_114;
wire si_register_slice_inst_n_146;
wire si_register_slice_inst_n_147;
wire si_register_slice_inst_n_148;
wire si_register_slice_inst_n_149;
wire si_register_slice_inst_n_150;
wire si_register_slice_inst_n_151;
wire sr_arvalid;
wire sr_awvalid;
wire use_wrap_buffer;
wire [0:0]wr_cmd_first_word;
wire wr_cmd_fix;
wire wr_cmd_modified;
wire [2:1]wr_cmd_next_word;
wire wr_cmd_packed_wrap;
wire wr_cmd_valid;
wire wrap_buffer_available;
wire wrap_buffer_available_0;
system_auto_us_0_axi_register_slice_v2_1_11_axi_register_slice \USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst
(.E(\r_pipe/p_1_in ),
.Q({M_AXI_RLAST,mr_rresp,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_5 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_6 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_7 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_8 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_9 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_10 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_11 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_12 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_13 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_14 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_15 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_16 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_17 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_18 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_19 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_20 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_21 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_22 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_23 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_24 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_25 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_26 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_27 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_28 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_29 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_30 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_31 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_32 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_33 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_34 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_35 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_36 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_37 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_38 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_39 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_40 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_41 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_42 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_43 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_44 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_45 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_46 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_47 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_48 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_49 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_50 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_51 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_52 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_53 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_54 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_55 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_56 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_57 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_58 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_59 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_60 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_61 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_62 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_63 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_64 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_65 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_66 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_67 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_68 }),
.\aresetn_d_reg[0] (si_register_slice_inst_n_1),
.\aresetn_d_reg[1] (si_register_slice_inst_n_0),
.m_axi_rdata(m_axi_rdata),
.m_axi_rlast(m_axi_rlast),
.m_axi_rready(m_axi_rready),
.m_axi_rresp(m_axi_rresp),
.m_axi_rvalid(m_axi_rvalid),
.mr_rvalid(mr_rvalid),
.rd_cmd_valid(rd_cmd_valid),
.s_axi_aclk(s_axi_aclk),
.use_wrap_buffer_reg(\USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_38 ));
system_auto_us_0_axi_dwidth_converter_v2_1_11_r_upsizer \USE_READ.gen_non_fifo_r_upsizer.read_data_inst
(.D(pre_next_word),
.E(p_15_in),
.Q({M_AXI_RLAST,mr_rresp,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_5 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_6 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_7 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_8 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_9 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_10 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_11 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_12 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_13 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_14 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_15 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_16 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_17 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_18 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_19 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_20 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_21 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_22 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_23 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_24 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_25 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_26 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_27 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_28 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_29 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_30 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_31 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_32 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_33 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_34 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_35 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_36 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_37 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_38 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_39 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_40 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_41 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_42 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_43 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_44 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_45 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_46 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_47 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_48 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_49 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_50 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_51 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_52 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_53 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_54 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_55 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_56 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_57 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_58 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_59 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_60 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_61 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_62 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_63 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_64 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_65 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_66 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_67 ,\USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst_n_68 }),
.\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[13] (next_word),
.\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[25] (\USE_READ.read_addr_inst_n_3 ),
.\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28] (\USE_READ.read_addr_inst_n_18 ),
.\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29] ({rd_cmd_fix,rd_cmd_first_word,rd_cmd_next_word,\USE_READ.read_addr_inst_n_8 ,\USE_READ.read_addr_inst_n_9 ,\USE_READ.read_addr_inst_n_10 ,\USE_READ.read_addr_inst_n_11 ,\USE_READ.read_addr_inst_n_12 ,\USE_READ.read_addr_inst_n_13 ,\USE_READ.read_addr_inst_n_14 ,\USE_READ.read_addr_inst_n_15 ,\USE_READ.read_addr_inst_n_16 }),
.\USE_RTL_ADDR.addr_q_reg[4] (\USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_48 ),
.\current_word_1_reg[0]_0 (\USE_READ.read_addr_inst_n_19 ),
.\current_word_1_reg[2]_0 (pre_next_word_1),
.\current_word_1_reg[2]_1 (\USE_READ.read_addr_inst_n_2 ),
.first_mi_word_q(first_mi_word_q),
.first_word(first_word),
.first_word_reg_0(current_word_1),
.\m_payload_i_reg[0] (\r_pipe/p_1_in ),
.m_valid_i_reg(p_7_in),
.mr_rvalid(mr_rvalid),
.pop_mi_data(pop_mi_data),
.\pre_next_word_1_reg[2]_0 (\USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_43 ),
.\pre_next_word_1_reg[2]_1 (\USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_47 ),
.rd_cmd_valid(rd_cmd_valid),
.s_axi_aclk(s_axi_aclk),
.s_axi_aresetn(\USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst_n_1 ),
.s_axi_rdata(s_axi_rdata),
.s_axi_rlast(s_axi_rlast),
.s_axi_rready(s_axi_rready),
.s_axi_rresp(s_axi_rresp),
.s_ready_i_reg(\USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_38 ),
.use_wrap_buffer(use_wrap_buffer),
.use_wrap_buffer_reg_0(\USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_39 ),
.wrap_buffer_available(wrap_buffer_available));
system_auto_us_0_axi_dwidth_converter_v2_1_11_a_upsizer__parameterized0 \USE_READ.read_addr_inst
(.D(pre_next_word),
.E(p_15_in),
.\M_AXI_RDATA_I_reg[63] (p_7_in),
.Q({rd_cmd_fix,rd_cmd_first_word,rd_cmd_next_word,\USE_READ.read_addr_inst_n_8 ,\USE_READ.read_addr_inst_n_9 ,\USE_READ.read_addr_inst_n_10 ,\USE_READ.read_addr_inst_n_11 ,\USE_READ.read_addr_inst_n_12 ,\USE_READ.read_addr_inst_n_13 ,\USE_READ.read_addr_inst_n_14 ,\USE_READ.read_addr_inst_n_15 ,\USE_READ.read_addr_inst_n_16 }),
.\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29] (\USE_READ.read_addr_inst_n_2 ),
.\USE_RTL_LENGTH.first_mi_word_q_reg (\USE_READ.read_addr_inst_n_18 ),
.\USE_RTL_LENGTH.length_counter_q_reg[7] (\USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_39 ),
.\current_word_1_reg[2] (next_word),
.\current_word_1_reg[2]_0 (current_word_1),
.first_mi_word_q(first_mi_word_q),
.first_word(first_word),
.first_word_reg(\USE_READ.read_addr_inst_n_19 ),
.in({cmd_fix_i,cmd_modified_i,cmd_complete_wrap_i,cmd_packed_wrap_i,cmd_first_word_i,p_1_out,si_register_slice_inst_n_146,si_register_slice_inst_n_147,si_register_slice_inst_n_148,si_register_slice_inst_n_149,si_register_slice_inst_n_150,si_register_slice_inst_n_151,m_axi_arlen}),
.m_axi_arready(m_axi_arready),
.m_axi_arvalid(m_axi_arvalid),
.mr_rvalid(mr_rvalid),
.out(out),
.pop_mi_data(pop_mi_data),
.\pre_next_word_1_reg[1] (\USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_47 ),
.\pre_next_word_1_reg[2] (pre_next_word_1),
.\pre_next_word_1_reg[2]_0 (\USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_43 ),
.rd_cmd_valid(rd_cmd_valid),
.s_axi_aclk(s_axi_aclk),
.s_axi_aresetn(\USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst_n_1 ),
.\s_axi_rdata[31] (\USE_READ.read_addr_inst_n_3 ),
.s_axi_rready(s_axi_rready),
.s_axi_rvalid(s_axi_rvalid),
.s_ready_i_reg(\USE_READ.read_addr_inst_n_28 ),
.sr_arvalid(sr_arvalid),
.use_wrap_buffer(use_wrap_buffer),
.wrap_buffer_available(wrap_buffer_available),
.wrap_buffer_available_reg(s_axi_rlast),
.wrap_buffer_available_reg_0(\USE_READ.gen_non_fifo_r_upsizer.read_data_inst_n_48 ));
system_auto_us_0_axi_dwidth_converter_v2_1_11_w_upsizer \USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst
(.D(pre_next_word_2),
.E(pop_si_data),
.Q({wr_cmd_fix,wr_cmd_modified,wr_cmd_packed_wrap,wr_cmd_first_word,wr_cmd_next_word,cmd_last_word,\USE_WRITE.write_addr_inst_n_11 ,\USE_WRITE.write_addr_inst_n_12 ,\USE_WRITE.write_addr_inst_n_13 ,\USE_WRITE.write_addr_inst_n_14 ,\USE_WRITE.write_addr_inst_n_15 ,\USE_WRITE.write_addr_inst_n_16 ,\USE_WRITE.write_addr_inst_n_17 ,\USE_WRITE.write_addr_inst_n_18 }),
.SR(\USE_WRITE.write_addr_inst_n_1 ),
.\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[13] (next_word_1),
.\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[17] (\USE_WRITE.write_addr_inst_n_48 ),
.\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[18] (\USE_WRITE.write_addr_inst_n_47 ),
.\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[19] (\USE_WRITE.write_addr_inst_n_19 ),
.\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[25] (\USE_WRITE.write_addr_inst_n_21 ),
.\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[25]_0 (\USE_WRITE.write_addr_inst_n_24 ),
.\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[25]_1 (\USE_WRITE.write_addr_inst_n_26 ),
.\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[25]_2 (\USE_WRITE.write_addr_inst_n_28 ),
.\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[25]_3 (\USE_WRITE.write_addr_inst_n_30 ),
.\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[25]_4 (\USE_WRITE.write_addr_inst_n_32 ),
.\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[25]_5 (\USE_WRITE.write_addr_inst_n_34 ),
.\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[25]_6 (\USE_WRITE.write_addr_inst_n_36 ),
.\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[27] (\USE_WRITE.write_addr_inst_n_2 ),
.\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28] (\USE_WRITE.write_addr_inst_n_20 ),
.\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28]_0 (\USE_WRITE.write_addr_inst_n_23 ),
.\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28]_1 (\USE_WRITE.write_addr_inst_n_25 ),
.\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28]_2 (\USE_WRITE.write_addr_inst_n_27 ),
.\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28]_3 (\USE_WRITE.write_addr_inst_n_29 ),
.\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28]_4 (\USE_WRITE.write_addr_inst_n_31 ),
.\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28]_5 (\USE_WRITE.write_addr_inst_n_33 ),
.\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28]_6 (\USE_WRITE.write_addr_inst_n_35 ),
.\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28]_7 (\USE_WRITE.write_addr_inst_n_55 ),
.\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29] (\USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst_n_19 ),
.\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]_0 (\USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst_n_26 ),
.\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]_1 (\USE_WRITE.write_addr_inst_n_22 ),
.\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg (\USE_WRITE.write_addr_inst_n_58 ),
.\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_0 (\USE_WRITE.write_addr_inst_n_59 ),
.\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_1 (\USE_WRITE.write_addr_inst_n_37 ),
.\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_2 (p_41_out),
.\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_3 (p_71_out),
.\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_4 (p_102_out),
.\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_5 (p_131_out),
.\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_6 (p_160_out),
.\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_7 (p_189_out),
.\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_8 (p_222_out),
.\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_9 (\USE_WRITE.write_addr_inst_n_3 ),
.\USE_REGISTER.M_AXI_WLAST_q_reg_0 (\USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst_n_1 ),
.\USE_RTL_CURR_WORD.current_word_q_reg[2]_0 (pre_next_word_q),
.\USE_RTL_CURR_WORD.pre_next_word_q_reg[2]_0 (\USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst_n_21 ),
.\USE_RTL_CURR_WORD.pre_next_word_q_reg[2]_1 (\USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst_n_25 ),
.\USE_RTL_LENGTH.first_mi_word_q_reg_0 (\USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst_n_14 ),
.\USE_RTL_LENGTH.first_mi_word_q_reg_1 (\USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst_n_15 ),
.\USE_RTL_LENGTH.first_mi_word_q_reg_2 (\USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst_n_16 ),
.\USE_RTL_LENGTH.length_counter_q_reg[3]_0 (\USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst_n_20 ),
.\USE_RTL_LENGTH.length_counter_q_reg[7]_0 (\USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst_n_18 ),
.\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[0]_0 (\USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst_n_17 ),
.\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg[7]_0 (current_word_q),
.first_word_q(first_word_q),
.m_axi_wdata(m_axi_wdata),
.m_axi_wlast(m_axi_wlast),
.m_axi_wready(m_axi_wready),
.m_axi_wstrb(m_axi_wstrb),
.m_axi_wvalid(m_axi_wvalid),
.out(out),
.p_251_in(p_251_in),
.s_axi_aclk(s_axi_aclk),
.s_axi_wdata(s_axi_wdata),
.s_axi_wlast(s_axi_wlast),
.s_axi_wvalid(s_axi_wvalid),
.wr_cmd_valid(wr_cmd_valid),
.wrap_buffer_available(wrap_buffer_available_0));
system_auto_us_0_axi_dwidth_converter_v2_1_11_a_upsizer \USE_WRITE.write_addr_inst
(.D(pre_next_word_2),
.E(pop_si_data),
.Q({wr_cmd_fix,wr_cmd_modified,wr_cmd_packed_wrap,wr_cmd_first_word,wr_cmd_next_word,cmd_last_word,\USE_WRITE.write_addr_inst_n_11 ,\USE_WRITE.write_addr_inst_n_12 ,\USE_WRITE.write_addr_inst_n_13 ,\USE_WRITE.write_addr_inst_n_14 ,\USE_WRITE.write_addr_inst_n_15 ,\USE_WRITE.write_addr_inst_n_16 ,\USE_WRITE.write_addr_inst_n_17 ,\USE_WRITE.write_addr_inst_n_18 }),
.SR(\USE_WRITE.write_addr_inst_n_1 ),
.\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28] (\USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst_n_15 ),
.\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29] (\USE_WRITE.write_addr_inst_n_2 ),
.\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]_0 (\USE_WRITE.write_addr_inst_n_19 ),
.\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[7] (\USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst_n_17 ),
.\USE_REGISTER.M_AXI_WVALID_q_reg (\USE_WRITE.write_addr_inst_n_59 ),
.\USE_REGISTER.M_AXI_WVALID_q_reg_0 (\USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst_n_16 ),
.\USE_REGISTER.M_AXI_WVALID_q_reg_1 (m_axi_wvalid),
.\USE_RTL_CURR_WORD.current_word_q_reg[0] (\USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst_n_26 ),
.\USE_RTL_CURR_WORD.current_word_q_reg[2] (next_word_1),
.\USE_RTL_CURR_WORD.current_word_q_reg[2]_0 (current_word_q),
.\USE_RTL_CURR_WORD.pre_next_word_q_reg[1] (\USE_WRITE.write_addr_inst_n_22 ),
.\USE_RTL_CURR_WORD.pre_next_word_q_reg[1]_0 (\USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst_n_25 ),
.\USE_RTL_CURR_WORD.pre_next_word_q_reg[2] (pre_next_word_q),
.\USE_RTL_CURR_WORD.pre_next_word_q_reg[2]_0 (\USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst_n_21 ),
.\USE_RTL_LENGTH.first_mi_word_q_reg (\USE_WRITE.write_addr_inst_n_47 ),
.\USE_RTL_LENGTH.first_mi_word_q_reg_0 (\USE_WRITE.write_addr_inst_n_48 ),
.\USE_RTL_LENGTH.length_counter_q_reg[0] (\USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst_n_20 ),
.\USE_RTL_LENGTH.length_counter_q_reg[2] (\USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst_n_14 ),
.\USE_RTL_LENGTH.length_counter_q_reg[3] (\USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst_n_19 ),
.\USE_RTL_LENGTH.length_counter_q_reg[5] (\USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst_n_18 ),
.\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[0] (\USE_WRITE.write_addr_inst_n_3 ),
.\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[0]_0 (\USE_WRITE.write_addr_inst_n_35 ),
.\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[0]_1 (\USE_WRITE.write_addr_inst_n_55 ),
.\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[0] (\USE_WRITE.write_addr_inst_n_36 ),
.\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg[7] (p_222_out),
.\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[8] (\USE_WRITE.write_addr_inst_n_33 ),
.\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[1] (\USE_WRITE.write_addr_inst_n_34 ),
.\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg[15] (p_189_out),
.\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[16] (\USE_WRITE.write_addr_inst_n_31 ),
.\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[2] (\USE_WRITE.write_addr_inst_n_32 ),
.\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg[23] (p_160_out),
.\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[24] (\USE_WRITE.write_addr_inst_n_29 ),
.\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[3] (\USE_WRITE.write_addr_inst_n_30 ),
.\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg[31] (p_131_out),
.\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[32] (\USE_WRITE.write_addr_inst_n_27 ),
.\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[4] (\USE_WRITE.write_addr_inst_n_28 ),
.\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg[39] (p_102_out),
.\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[40] (\USE_WRITE.write_addr_inst_n_25 ),
.\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[5] (\USE_WRITE.write_addr_inst_n_26 ),
.\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg[47] (p_71_out),
.\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[48] (\USE_WRITE.write_addr_inst_n_23 ),
.\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[6] (\USE_WRITE.write_addr_inst_n_24 ),
.\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg[55] (p_41_out),
.\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[56] (\USE_WRITE.write_addr_inst_n_20 ),
.\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[7] (\USE_WRITE.write_addr_inst_n_21 ),
.\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg[63] (\USE_WRITE.write_addr_inst_n_37 ),
.first_word_q(first_word_q),
.in({cmd_fix_i_8,cmd_modified_i_7,cmd_complete_wrap_i_6,cmd_packed_wrap_i_5,cmd_first_word_i_4,p_1_out_3,si_register_slice_inst_n_109,si_register_slice_inst_n_110,si_register_slice_inst_n_111,si_register_slice_inst_n_112,si_register_slice_inst_n_113,si_register_slice_inst_n_114,m_axi_awlen}),
.m_axi_awready(m_axi_awready),
.m_axi_awvalid(m_axi_awvalid),
.m_axi_wready(m_axi_wready),
.out(out),
.p_251_in(p_251_in),
.s_axi_aclk(s_axi_aclk),
.s_axi_aresetn(\USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst_n_1 ),
.s_axi_wlast(s_axi_wlast),
.s_axi_wready(s_axi_wready),
.s_axi_wstrb(s_axi_wstrb),
.s_axi_wvalid(s_axi_wvalid),
.s_ready_i_reg(\USE_WRITE.write_addr_inst_n_56 ),
.sr_awvalid(sr_awvalid),
.wr_cmd_valid(wr_cmd_valid),
.wrap_buffer_available(wrap_buffer_available_0),
.wrap_buffer_available_reg(\USE_WRITE.write_addr_inst_n_58 ));
system_auto_us_0_axi_register_slice_v2_1_11_axi_register_slice__parameterized0 si_register_slice_inst
(.D(D),
.Q(Q),
.\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29] ({cmd_fix_i,cmd_modified_i,cmd_complete_wrap_i,cmd_packed_wrap_i,cmd_first_word_i,p_1_out,si_register_slice_inst_n_146,si_register_slice_inst_n_147,si_register_slice_inst_n_148,si_register_slice_inst_n_149,si_register_slice_inst_n_150,si_register_slice_inst_n_151,m_axi_arlen}),
.\aresetn_d_reg[1] (si_register_slice_inst_n_1),
.cmd_push_block_reg(\USE_READ.read_addr_inst_n_28 ),
.cmd_push_block_reg_0(\USE_WRITE.write_addr_inst_n_56 ),
.in({cmd_fix_i_8,cmd_modified_i_7,cmd_complete_wrap_i_6,cmd_packed_wrap_i_5,cmd_first_word_i_4,p_1_out_3,si_register_slice_inst_n_109,si_register_slice_inst_n_110,si_register_slice_inst_n_111,si_register_slice_inst_n_112,si_register_slice_inst_n_113,si_register_slice_inst_n_114,m_axi_awlen}),
.m_axi_araddr(m_axi_araddr),
.m_axi_arburst(m_axi_arburst),
.m_axi_arsize(m_axi_arsize),
.m_axi_awaddr(m_axi_awaddr),
.m_axi_awburst(m_axi_awburst),
.\m_axi_awregion[3] (\m_axi_awregion[3] ),
.m_axi_awsize(m_axi_awsize),
.s_axi_aclk(s_axi_aclk),
.s_axi_aresetn(\USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst_n_1 ),
.s_axi_arready(s_axi_arready),
.\s_axi_arregion[3] (\s_axi_arregion[3] ),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_awready(s_axi_awready),
.s_axi_awvalid(s_axi_awvalid),
.s_ready_i_reg(si_register_slice_inst_n_0),
.sr_arvalid(sr_arvalid),
.sr_awvalid(sr_awvalid));
endmodule
|
module system_auto_us_0_axi_dwidth_converter_v2_1_11_r_upsizer
(first_mi_word_q,
first_word,
s_axi_rlast,
use_wrap_buffer,
wrap_buffer_available,
s_axi_rdata,
\m_payload_i_reg[0] ,
s_ready_i_reg,
use_wrap_buffer_reg_0,
first_word_reg_0,
\pre_next_word_1_reg[2]_0 ,
\current_word_1_reg[2]_0 ,
\pre_next_word_1_reg[2]_1 ,
\USE_RTL_ADDR.addr_q_reg[4] ,
s_axi_rresp,
s_axi_aresetn,
pop_mi_data,
Q,
s_axi_aclk,
E,
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29] ,
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[25] ,
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28] ,
s_axi_rready,
rd_cmd_valid,
mr_rvalid,
\current_word_1_reg[2]_1 ,
\current_word_1_reg[0]_0 ,
m_valid_i_reg,
D,
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[13] );
output first_mi_word_q;
output first_word;
output s_axi_rlast;
output use_wrap_buffer;
output wrap_buffer_available;
output [31:0]s_axi_rdata;
output [0:0]\m_payload_i_reg[0] ;
output s_ready_i_reg;
output use_wrap_buffer_reg_0;
output [2:0]first_word_reg_0;
output \pre_next_word_1_reg[2]_0 ;
output [2:0]\current_word_1_reg[2]_0 ;
output \pre_next_word_1_reg[2]_1 ;
output \USE_RTL_ADDR.addr_q_reg[4] ;
output [1:0]s_axi_rresp;
input s_axi_aresetn;
input pop_mi_data;
input [66:0]Q;
input s_axi_aclk;
input [0:0]E;
input [12:0]\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29] ;
input \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[25] ;
input \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28] ;
input s_axi_rready;
input rd_cmd_valid;
input mr_rvalid;
input \current_word_1_reg[2]_1 ;
input \current_word_1_reg[0]_0 ;
input [0:0]m_valid_i_reg;
input [2:0]D;
input [2:0]\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[13] ;
wire [2:0]D;
wire [0:0]E;
wire [63:0]M_AXI_RDATA_I;
wire [66:0]Q;
wire [2:0]\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[13] ;
wire \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[25] ;
wire \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28] ;
wire [12:0]\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29] ;
wire \USE_RTL_ADDR.addr_q[4]_i_5_n_0 ;
wire \USE_RTL_ADDR.addr_q[4]_i_6_n_0 ;
wire \USE_RTL_ADDR.addr_q[4]_i_7_n_0 ;
wire \USE_RTL_ADDR.addr_q_reg[4] ;
wire \USE_RTL_LENGTH.length_counter_q[0]_i_1__0_n_0 ;
wire \USE_RTL_LENGTH.length_counter_q[1]_i_1__0_n_0 ;
wire \USE_RTL_LENGTH.length_counter_q[2]_i_1__0_n_0 ;
wire \USE_RTL_LENGTH.length_counter_q[2]_i_2_n_0 ;
wire \USE_RTL_LENGTH.length_counter_q[3]_i_1__0_n_0 ;
wire \USE_RTL_LENGTH.length_counter_q[3]_i_2__0_n_0 ;
wire \USE_RTL_LENGTH.length_counter_q[4]_i_1__0_n_0 ;
wire \USE_RTL_LENGTH.length_counter_q[5]_i_1__0_n_0 ;
wire \USE_RTL_LENGTH.length_counter_q[6]_i_1__0_n_0 ;
wire \USE_RTL_LENGTH.length_counter_q[7]_i_1__0_n_0 ;
wire \USE_RTL_LENGTH.length_counter_q[7]_i_2__0_n_0 ;
wire [7:0]\USE_RTL_LENGTH.length_counter_q_reg ;
wire \current_word_1_reg[0]_0 ;
wire [2:0]\current_word_1_reg[2]_0 ;
wire \current_word_1_reg[2]_1 ;
wire first_mi_word_q;
wire first_word;
wire [2:0]first_word_reg_0;
wire [0:0]\m_payload_i_reg[0] ;
wire [0:0]m_valid_i_reg;
wire mr_rvalid;
wire pop_mi_data;
wire \pre_next_word_1_reg[2]_0 ;
wire \pre_next_word_1_reg[2]_1 ;
wire rd_cmd_valid;
wire [1:0]rresp_wrap_buffer;
wire s_axi_aclk;
wire s_axi_aresetn;
wire [31:0]s_axi_rdata;
wire s_axi_rlast;
wire s_axi_rlast_INST_0_i_3_n_0;
wire s_axi_rlast_INST_0_i_4_n_0;
wire s_axi_rlast_INST_0_i_5_n_0;
wire s_axi_rlast_INST_0_i_6_n_0;
wire s_axi_rready;
wire [1:0]s_axi_rresp;
wire s_ready_i_reg;
wire use_wrap_buffer;
wire use_wrap_buffer_i_1_n_0;
wire use_wrap_buffer_i_2_n_0;
wire use_wrap_buffer_reg_0;
wire wrap_buffer_available;
wire wrap_buffer_available_i_1__0_n_0;
wire wrap_buffer_available_i_2__0_n_0;
FDRE \M_AXI_RDATA_I_reg[0]
(.C(s_axi_aclk),
.CE(m_valid_i_reg),
.D(Q[0]),
.Q(M_AXI_RDATA_I[0]),
.R(s_axi_aresetn));
FDRE \M_AXI_RDATA_I_reg[10]
(.C(s_axi_aclk),
.CE(m_valid_i_reg),
.D(Q[10]),
.Q(M_AXI_RDATA_I[10]),
.R(s_axi_aresetn));
FDRE \M_AXI_RDATA_I_reg[11]
(.C(s_axi_aclk),
.CE(m_valid_i_reg),
.D(Q[11]),
.Q(M_AXI_RDATA_I[11]),
.R(s_axi_aresetn));
FDRE \M_AXI_RDATA_I_reg[12]
(.C(s_axi_aclk),
.CE(m_valid_i_reg),
.D(Q[12]),
.Q(M_AXI_RDATA_I[12]),
.R(s_axi_aresetn));
FDRE \M_AXI_RDATA_I_reg[13]
(.C(s_axi_aclk),
.CE(m_valid_i_reg),
.D(Q[13]),
.Q(M_AXI_RDATA_I[13]),
.R(s_axi_aresetn));
FDRE \M_AXI_RDATA_I_reg[14]
(.C(s_axi_aclk),
.CE(m_valid_i_reg),
.D(Q[14]),
.Q(M_AXI_RDATA_I[14]),
.R(s_axi_aresetn));
FDRE \M_AXI_RDATA_I_reg[15]
(.C(s_axi_aclk),
.CE(m_valid_i_reg),
.D(Q[15]),
.Q(M_AXI_RDATA_I[15]),
.R(s_axi_aresetn));
FDRE \M_AXI_RDATA_I_reg[16]
(.C(s_axi_aclk),
.CE(m_valid_i_reg),
.D(Q[16]),
.Q(M_AXI_RDATA_I[16]),
.R(s_axi_aresetn));
FDRE \M_AXI_RDATA_I_reg[17]
(.C(s_axi_aclk),
.CE(m_valid_i_reg),
.D(Q[17]),
.Q(M_AXI_RDATA_I[17]),
.R(s_axi_aresetn));
FDRE \M_AXI_RDATA_I_reg[18]
(.C(s_axi_aclk),
.CE(m_valid_i_reg),
.D(Q[18]),
.Q(M_AXI_RDATA_I[18]),
.R(s_axi_aresetn));
FDRE \M_AXI_RDATA_I_reg[19]
(.C(s_axi_aclk),
.CE(m_valid_i_reg),
.D(Q[19]),
.Q(M_AXI_RDATA_I[19]),
.R(s_axi_aresetn));
FDRE \M_AXI_RDATA_I_reg[1]
(.C(s_axi_aclk),
.CE(m_valid_i_reg),
.D(Q[1]),
.Q(M_AXI_RDATA_I[1]),
.R(s_axi_aresetn));
FDRE \M_AXI_RDATA_I_reg[20]
(.C(s_axi_aclk),
.CE(m_valid_i_reg),
.D(Q[20]),
.Q(M_AXI_RDATA_I[20]),
.R(s_axi_aresetn));
FDRE \M_AXI_RDATA_I_reg[21]
(.C(s_axi_aclk),
.CE(m_valid_i_reg),
.D(Q[21]),
.Q(M_AXI_RDATA_I[21]),
.R(s_axi_aresetn));
FDRE \M_AXI_RDATA_I_reg[22]
(.C(s_axi_aclk),
.CE(m_valid_i_reg),
.D(Q[22]),
.Q(M_AXI_RDATA_I[22]),
.R(s_axi_aresetn));
FDRE \M_AXI_RDATA_I_reg[23]
(.C(s_axi_aclk),
.CE(m_valid_i_reg),
.D(Q[23]),
.Q(M_AXI_RDATA_I[23]),
.R(s_axi_aresetn));
FDRE \M_AXI_RDATA_I_reg[24]
(.C(s_axi_aclk),
.CE(m_valid_i_reg),
.D(Q[24]),
.Q(M_AXI_RDATA_I[24]),
.R(s_axi_aresetn));
FDRE \M_AXI_RDATA_I_reg[25]
(.C(s_axi_aclk),
.CE(m_valid_i_reg),
.D(Q[25]),
.Q(M_AXI_RDATA_I[25]),
.R(s_axi_aresetn));
FDRE \M_AXI_RDATA_I_reg[26]
(.C(s_axi_aclk),
.CE(m_valid_i_reg),
.D(Q[26]),
.Q(M_AXI_RDATA_I[26]),
.R(s_axi_aresetn));
FDRE \M_AXI_RDATA_I_reg[27]
(.C(s_axi_aclk),
.CE(m_valid_i_reg),
.D(Q[27]),
.Q(M_AXI_RDATA_I[27]),
.R(s_axi_aresetn));
FDRE \M_AXI_RDATA_I_reg[28]
(.C(s_axi_aclk),
.CE(m_valid_i_reg),
.D(Q[28]),
.Q(M_AXI_RDATA_I[28]),
.R(s_axi_aresetn));
FDRE \M_AXI_RDATA_I_reg[29]
(.C(s_axi_aclk),
.CE(m_valid_i_reg),
.D(Q[29]),
.Q(M_AXI_RDATA_I[29]),
.R(s_axi_aresetn));
FDRE \M_AXI_RDATA_I_reg[2]
(.C(s_axi_aclk),
.CE(m_valid_i_reg),
.D(Q[2]),
.Q(M_AXI_RDATA_I[2]),
.R(s_axi_aresetn));
FDRE \M_AXI_RDATA_I_reg[30]
(.C(s_axi_aclk),
.CE(m_valid_i_reg),
.D(Q[30]),
.Q(M_AXI_RDATA_I[30]),
.R(s_axi_aresetn));
FDRE \M_AXI_RDATA_I_reg[31]
(.C(s_axi_aclk),
.CE(m_valid_i_reg),
.D(Q[31]),
.Q(M_AXI_RDATA_I[31]),
.R(s_axi_aresetn));
FDRE \M_AXI_RDATA_I_reg[32]
(.C(s_axi_aclk),
.CE(m_valid_i_reg),
.D(Q[32]),
.Q(M_AXI_RDATA_I[32]),
.R(s_axi_aresetn));
FDRE \M_AXI_RDATA_I_reg[33]
(.C(s_axi_aclk),
.CE(m_valid_i_reg),
.D(Q[33]),
.Q(M_AXI_RDATA_I[33]),
.R(s_axi_aresetn));
FDRE \M_AXI_RDATA_I_reg[34]
(.C(s_axi_aclk),
.CE(m_valid_i_reg),
.D(Q[34]),
.Q(M_AXI_RDATA_I[34]),
.R(s_axi_aresetn));
FDRE \M_AXI_RDATA_I_reg[35]
(.C(s_axi_aclk),
.CE(m_valid_i_reg),
.D(Q[35]),
.Q(M_AXI_RDATA_I[35]),
.R(s_axi_aresetn));
FDRE \M_AXI_RDATA_I_reg[36]
(.C(s_axi_aclk),
.CE(m_valid_i_reg),
.D(Q[36]),
.Q(M_AXI_RDATA_I[36]),
.R(s_axi_aresetn));
FDRE \M_AXI_RDATA_I_reg[37]
(.C(s_axi_aclk),
.CE(m_valid_i_reg),
.D(Q[37]),
.Q(M_AXI_RDATA_I[37]),
.R(s_axi_aresetn));
FDRE \M_AXI_RDATA_I_reg[38]
(.C(s_axi_aclk),
.CE(m_valid_i_reg),
.D(Q[38]),
.Q(M_AXI_RDATA_I[38]),
.R(s_axi_aresetn));
FDRE \M_AXI_RDATA_I_reg[39]
(.C(s_axi_aclk),
.CE(m_valid_i_reg),
.D(Q[39]),
.Q(M_AXI_RDATA_I[39]),
.R(s_axi_aresetn));
FDRE \M_AXI_RDATA_I_reg[3]
(.C(s_axi_aclk),
.CE(m_valid_i_reg),
.D(Q[3]),
.Q(M_AXI_RDATA_I[3]),
.R(s_axi_aresetn));
FDRE \M_AXI_RDATA_I_reg[40]
(.C(s_axi_aclk),
.CE(m_valid_i_reg),
.D(Q[40]),
.Q(M_AXI_RDATA_I[40]),
.R(s_axi_aresetn));
FDRE \M_AXI_RDATA_I_reg[41]
(.C(s_axi_aclk),
.CE(m_valid_i_reg),
.D(Q[41]),
.Q(M_AXI_RDATA_I[41]),
.R(s_axi_aresetn));
FDRE \M_AXI_RDATA_I_reg[42]
(.C(s_axi_aclk),
.CE(m_valid_i_reg),
.D(Q[42]),
.Q(M_AXI_RDATA_I[42]),
.R(s_axi_aresetn));
FDRE \M_AXI_RDATA_I_reg[43]
(.C(s_axi_aclk),
.CE(m_valid_i_reg),
.D(Q[43]),
.Q(M_AXI_RDATA_I[43]),
.R(s_axi_aresetn));
FDRE \M_AXI_RDATA_I_reg[44]
(.C(s_axi_aclk),
.CE(m_valid_i_reg),
.D(Q[44]),
.Q(M_AXI_RDATA_I[44]),
.R(s_axi_aresetn));
FDRE \M_AXI_RDATA_I_reg[45]
(.C(s_axi_aclk),
.CE(m_valid_i_reg),
.D(Q[45]),
.Q(M_AXI_RDATA_I[45]),
.R(s_axi_aresetn));
FDRE \M_AXI_RDATA_I_reg[46]
(.C(s_axi_aclk),
.CE(m_valid_i_reg),
.D(Q[46]),
.Q(M_AXI_RDATA_I[46]),
.R(s_axi_aresetn));
FDRE \M_AXI_RDATA_I_reg[47]
(.C(s_axi_aclk),
.CE(m_valid_i_reg),
.D(Q[47]),
.Q(M_AXI_RDATA_I[47]),
.R(s_axi_aresetn));
FDRE \M_AXI_RDATA_I_reg[48]
(.C(s_axi_aclk),
.CE(m_valid_i_reg),
.D(Q[48]),
.Q(M_AXI_RDATA_I[48]),
.R(s_axi_aresetn));
FDRE \M_AXI_RDATA_I_reg[49]
(.C(s_axi_aclk),
.CE(m_valid_i_reg),
.D(Q[49]),
.Q(M_AXI_RDATA_I[49]),
.R(s_axi_aresetn));
FDRE \M_AXI_RDATA_I_reg[4]
(.C(s_axi_aclk),
.CE(m_valid_i_reg),
.D(Q[4]),
.Q(M_AXI_RDATA_I[4]),
.R(s_axi_aresetn));
FDRE \M_AXI_RDATA_I_reg[50]
(.C(s_axi_aclk),
.CE(m_valid_i_reg),
.D(Q[50]),
.Q(M_AXI_RDATA_I[50]),
.R(s_axi_aresetn));
FDRE \M_AXI_RDATA_I_reg[51]
(.C(s_axi_aclk),
.CE(m_valid_i_reg),
.D(Q[51]),
.Q(M_AXI_RDATA_I[51]),
.R(s_axi_aresetn));
FDRE \M_AXI_RDATA_I_reg[52]
(.C(s_axi_aclk),
.CE(m_valid_i_reg),
.D(Q[52]),
.Q(M_AXI_RDATA_I[52]),
.R(s_axi_aresetn));
FDRE \M_AXI_RDATA_I_reg[53]
(.C(s_axi_aclk),
.CE(m_valid_i_reg),
.D(Q[53]),
.Q(M_AXI_RDATA_I[53]),
.R(s_axi_aresetn));
FDRE \M_AXI_RDATA_I_reg[54]
(.C(s_axi_aclk),
.CE(m_valid_i_reg),
.D(Q[54]),
.Q(M_AXI_RDATA_I[54]),
.R(s_axi_aresetn));
FDRE \M_AXI_RDATA_I_reg[55]
(.C(s_axi_aclk),
.CE(m_valid_i_reg),
.D(Q[55]),
.Q(M_AXI_RDATA_I[55]),
.R(s_axi_aresetn));
FDRE \M_AXI_RDATA_I_reg[56]
(.C(s_axi_aclk),
.CE(m_valid_i_reg),
.D(Q[56]),
.Q(M_AXI_RDATA_I[56]),
.R(s_axi_aresetn));
FDRE \M_AXI_RDATA_I_reg[57]
(.C(s_axi_aclk),
.CE(m_valid_i_reg),
.D(Q[57]),
.Q(M_AXI_RDATA_I[57]),
.R(s_axi_aresetn));
FDRE \M_AXI_RDATA_I_reg[58]
(.C(s_axi_aclk),
.CE(m_valid_i_reg),
.D(Q[58]),
.Q(M_AXI_RDATA_I[58]),
.R(s_axi_aresetn));
FDRE \M_AXI_RDATA_I_reg[59]
(.C(s_axi_aclk),
.CE(m_valid_i_reg),
.D(Q[59]),
.Q(M_AXI_RDATA_I[59]),
.R(s_axi_aresetn));
FDRE \M_AXI_RDATA_I_reg[5]
(.C(s_axi_aclk),
.CE(m_valid_i_reg),
.D(Q[5]),
.Q(M_AXI_RDATA_I[5]),
.R(s_axi_aresetn));
FDRE \M_AXI_RDATA_I_reg[60]
(.C(s_axi_aclk),
.CE(m_valid_i_reg),
.D(Q[60]),
.Q(M_AXI_RDATA_I[60]),
.R(s_axi_aresetn));
FDRE \M_AXI_RDATA_I_reg[61]
(.C(s_axi_aclk),
.CE(m_valid_i_reg),
.D(Q[61]),
.Q(M_AXI_RDATA_I[61]),
.R(s_axi_aresetn));
FDRE \M_AXI_RDATA_I_reg[62]
(.C(s_axi_aclk),
.CE(m_valid_i_reg),
.D(Q[62]),
.Q(M_AXI_RDATA_I[62]),
.R(s_axi_aresetn));
FDRE \M_AXI_RDATA_I_reg[63]
(.C(s_axi_aclk),
.CE(m_valid_i_reg),
.D(Q[63]),
.Q(M_AXI_RDATA_I[63]),
.R(s_axi_aresetn));
FDRE \M_AXI_RDATA_I_reg[6]
(.C(s_axi_aclk),
.CE(m_valid_i_reg),
.D(Q[6]),
.Q(M_AXI_RDATA_I[6]),
.R(s_axi_aresetn));
FDRE \M_AXI_RDATA_I_reg[7]
(.C(s_axi_aclk),
.CE(m_valid_i_reg),
.D(Q[7]),
.Q(M_AXI_RDATA_I[7]),
.R(s_axi_aresetn));
FDRE \M_AXI_RDATA_I_reg[8]
(.C(s_axi_aclk),
.CE(m_valid_i_reg),
.D(Q[8]),
.Q(M_AXI_RDATA_I[8]),
.R(s_axi_aresetn));
FDRE \M_AXI_RDATA_I_reg[9]
(.C(s_axi_aclk),
.CE(m_valid_i_reg),
.D(Q[9]),
.Q(M_AXI_RDATA_I[9]),
.R(s_axi_aresetn));
LUT6 #(
.INIT(64'h0000000000000004))
\USE_RTL_ADDR.addr_q[4]_i_4
(.I0(wrap_buffer_available),
.I1(s_axi_rlast_INST_0_i_6_n_0),
.I2(\USE_RTL_ADDR.addr_q[4]_i_5_n_0 ),
.I3(s_axi_rlast_INST_0_i_5_n_0),
.I4(\USE_RTL_ADDR.addr_q[4]_i_6_n_0 ),
.I5(\USE_RTL_ADDR.addr_q[4]_i_7_n_0 ),
.O(\USE_RTL_ADDR.addr_q_reg[4] ));
(* SOFT_HLUTNM = "soft_lutpair37" *)
LUT3 #(
.INIT(8'hB8))
\USE_RTL_ADDR.addr_q[4]_i_5
(.I0(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29] [7]),
.I1(first_mi_word_q),
.I2(\USE_RTL_LENGTH.length_counter_q_reg [7]),
.O(\USE_RTL_ADDR.addr_q[4]_i_5_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair35" *)
LUT3 #(
.INIT(8'hB8))
\USE_RTL_ADDR.addr_q[4]_i_6
(.I0(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29] [4]),
.I1(first_mi_word_q),
.I2(\USE_RTL_LENGTH.length_counter_q_reg [4]),
.O(\USE_RTL_ADDR.addr_q[4]_i_6_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair34" *)
LUT3 #(
.INIT(8'hB8))
\USE_RTL_ADDR.addr_q[4]_i_7
(.I0(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29] [5]),
.I1(first_mi_word_q),
.I2(\USE_RTL_LENGTH.length_counter_q_reg [5]),
.O(\USE_RTL_ADDR.addr_q[4]_i_7_n_0 ));
FDSE \USE_RTL_LENGTH.first_mi_word_q_reg
(.C(s_axi_aclk),
.CE(pop_mi_data),
.D(Q[66]),
.Q(first_mi_word_q),
.S(s_axi_aresetn));
LUT3 #(
.INIT(8'h1D))
\USE_RTL_LENGTH.length_counter_q[0]_i_1__0
(.I0(\USE_RTL_LENGTH.length_counter_q_reg [0]),
.I1(first_mi_word_q),
.I2(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29] [0]),
.O(\USE_RTL_LENGTH.length_counter_q[0]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair33" *)
LUT5 #(
.INIT(32'hCCA533A5))
\USE_RTL_LENGTH.length_counter_q[1]_i_1__0
(.I0(\USE_RTL_LENGTH.length_counter_q_reg [1]),
.I1(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29] [1]),
.I2(\USE_RTL_LENGTH.length_counter_q_reg [0]),
.I3(first_mi_word_q),
.I4(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29] [0]),
.O(\USE_RTL_LENGTH.length_counter_q[1]_i_1__0_n_0 ));
LUT6 #(
.INIT(64'hEEEEFA051111FA05))
\USE_RTL_LENGTH.length_counter_q[2]_i_1__0
(.I0(\USE_RTL_LENGTH.length_counter_q[2]_i_2_n_0 ),
.I1(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29] [1]),
.I2(\USE_RTL_LENGTH.length_counter_q_reg [1]),
.I3(\USE_RTL_LENGTH.length_counter_q_reg [2]),
.I4(first_mi_word_q),
.I5(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29] [2]),
.O(\USE_RTL_LENGTH.length_counter_q[2]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair37" *)
LUT3 #(
.INIT(8'hB8))
\USE_RTL_LENGTH.length_counter_q[2]_i_2
(.I0(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29] [0]),
.I1(first_mi_word_q),
.I2(\USE_RTL_LENGTH.length_counter_q_reg [0]),
.O(\USE_RTL_LENGTH.length_counter_q[2]_i_2_n_0 ));
LUT6 #(
.INIT(64'hC3AAC355CCAACCAA))
\USE_RTL_LENGTH.length_counter_q[3]_i_1__0
(.I0(\USE_RTL_LENGTH.length_counter_q_reg [3]),
.I1(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29] [3]),
.I2(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29] [2]),
.I3(first_mi_word_q),
.I4(\USE_RTL_LENGTH.length_counter_q_reg [2]),
.I5(\USE_RTL_LENGTH.length_counter_q[3]_i_2__0_n_0 ),
.O(\USE_RTL_LENGTH.length_counter_q[3]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair33" *)
LUT5 #(
.INIT(32'h00053305))
\USE_RTL_LENGTH.length_counter_q[3]_i_2__0
(.I0(\USE_RTL_LENGTH.length_counter_q_reg [1]),
.I1(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29] [1]),
.I2(\USE_RTL_LENGTH.length_counter_q_reg [0]),
.I3(first_mi_word_q),
.I4(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29] [0]),
.O(\USE_RTL_LENGTH.length_counter_q[3]_i_2__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair35" *)
LUT4 #(
.INIT(16'h56A6))
\USE_RTL_LENGTH.length_counter_q[4]_i_1__0
(.I0(s_axi_rlast_INST_0_i_6_n_0),
.I1(\USE_RTL_LENGTH.length_counter_q_reg [4]),
.I2(first_mi_word_q),
.I3(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29] [4]),
.O(\USE_RTL_LENGTH.length_counter_q[4]_i_1__0_n_0 ));
LUT6 #(
.INIT(64'hC3AAC355CCAACCAA))
\USE_RTL_LENGTH.length_counter_q[5]_i_1__0
(.I0(\USE_RTL_LENGTH.length_counter_q_reg [5]),
.I1(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29] [5]),
.I2(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29] [4]),
.I3(first_mi_word_q),
.I4(\USE_RTL_LENGTH.length_counter_q_reg [4]),
.I5(s_axi_rlast_INST_0_i_6_n_0),
.O(\USE_RTL_LENGTH.length_counter_q[5]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair36" *)
LUT4 #(
.INIT(16'h1DE2))
\USE_RTL_LENGTH.length_counter_q[6]_i_1__0
(.I0(\USE_RTL_LENGTH.length_counter_q_reg [6]),
.I1(first_mi_word_q),
.I2(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29] [6]),
.I3(\USE_RTL_LENGTH.length_counter_q[7]_i_2__0_n_0 ),
.O(\USE_RTL_LENGTH.length_counter_q[6]_i_1__0_n_0 ));
LUT6 #(
.INIT(64'hC3AAC355CCAACCAA))
\USE_RTL_LENGTH.length_counter_q[7]_i_1__0
(.I0(\USE_RTL_LENGTH.length_counter_q_reg [7]),
.I1(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29] [7]),
.I2(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29] [6]),
.I3(first_mi_word_q),
.I4(\USE_RTL_LENGTH.length_counter_q_reg [6]),
.I5(\USE_RTL_LENGTH.length_counter_q[7]_i_2__0_n_0 ),
.O(\USE_RTL_LENGTH.length_counter_q[7]_i_1__0_n_0 ));
LUT6 #(
.INIT(64'h0000003050500030))
\USE_RTL_LENGTH.length_counter_q[7]_i_2__0
(.I0(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29] [4]),
.I1(\USE_RTL_LENGTH.length_counter_q_reg [4]),
.I2(s_axi_rlast_INST_0_i_6_n_0),
.I3(\USE_RTL_LENGTH.length_counter_q_reg [5]),
.I4(first_mi_word_q),
.I5(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29] [5]),
.O(\USE_RTL_LENGTH.length_counter_q[7]_i_2__0_n_0 ));
FDRE \USE_RTL_LENGTH.length_counter_q_reg[0]
(.C(s_axi_aclk),
.CE(pop_mi_data),
.D(\USE_RTL_LENGTH.length_counter_q[0]_i_1__0_n_0 ),
.Q(\USE_RTL_LENGTH.length_counter_q_reg [0]),
.R(s_axi_aresetn));
FDRE \USE_RTL_LENGTH.length_counter_q_reg[1]
(.C(s_axi_aclk),
.CE(pop_mi_data),
.D(\USE_RTL_LENGTH.length_counter_q[1]_i_1__0_n_0 ),
.Q(\USE_RTL_LENGTH.length_counter_q_reg [1]),
.R(s_axi_aresetn));
FDRE \USE_RTL_LENGTH.length_counter_q_reg[2]
(.C(s_axi_aclk),
.CE(pop_mi_data),
.D(\USE_RTL_LENGTH.length_counter_q[2]_i_1__0_n_0 ),
.Q(\USE_RTL_LENGTH.length_counter_q_reg [2]),
.R(s_axi_aresetn));
FDRE \USE_RTL_LENGTH.length_counter_q_reg[3]
(.C(s_axi_aclk),
.CE(pop_mi_data),
.D(\USE_RTL_LENGTH.length_counter_q[3]_i_1__0_n_0 ),
.Q(\USE_RTL_LENGTH.length_counter_q_reg [3]),
.R(s_axi_aresetn));
FDRE \USE_RTL_LENGTH.length_counter_q_reg[4]
(.C(s_axi_aclk),
.CE(pop_mi_data),
.D(\USE_RTL_LENGTH.length_counter_q[4]_i_1__0_n_0 ),
.Q(\USE_RTL_LENGTH.length_counter_q_reg [4]),
.R(s_axi_aresetn));
FDRE \USE_RTL_LENGTH.length_counter_q_reg[5]
(.C(s_axi_aclk),
.CE(pop_mi_data),
.D(\USE_RTL_LENGTH.length_counter_q[5]_i_1__0_n_0 ),
.Q(\USE_RTL_LENGTH.length_counter_q_reg [5]),
.R(s_axi_aresetn));
FDRE \USE_RTL_LENGTH.length_counter_q_reg[6]
(.C(s_axi_aclk),
.CE(pop_mi_data),
.D(\USE_RTL_LENGTH.length_counter_q[6]_i_1__0_n_0 ),
.Q(\USE_RTL_LENGTH.length_counter_q_reg [6]),
.R(s_axi_aresetn));
FDRE \USE_RTL_LENGTH.length_counter_q_reg[7]
(.C(s_axi_aclk),
.CE(pop_mi_data),
.D(\USE_RTL_LENGTH.length_counter_q[7]_i_1__0_n_0 ),
.Q(\USE_RTL_LENGTH.length_counter_q_reg [7]),
.R(s_axi_aresetn));
FDRE \current_word_1_reg[0]
(.C(s_axi_aclk),
.CE(E),
.D(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[13] [0]),
.Q(first_word_reg_0[0]),
.R(s_axi_aresetn));
FDRE \current_word_1_reg[1]
(.C(s_axi_aclk),
.CE(E),
.D(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[13] [1]),
.Q(first_word_reg_0[1]),
.R(s_axi_aresetn));
FDRE \current_word_1_reg[2]
(.C(s_axi_aclk),
.CE(E),
.D(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[13] [2]),
.Q(first_word_reg_0[2]),
.R(s_axi_aresetn));
FDSE first_word_reg
(.C(s_axi_aclk),
.CE(E),
.D(s_axi_rlast),
.Q(first_word),
.S(s_axi_aresetn));
LUT6 #(
.INIT(64'hF2000000FFFFFFFF))
\m_payload_i[66]_i_1
(.I0(s_axi_rlast),
.I1(use_wrap_buffer),
.I2(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28] ),
.I3(s_axi_rready),
.I4(rd_cmd_valid),
.I5(mr_rvalid),
.O(\m_payload_i_reg[0] ));
LUT4 #(
.INIT(16'h01FD))
\pre_next_word_1[2]_i_3
(.I0(\current_word_1_reg[2]_0 [2]),
.I1(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29] [12]),
.I2(first_word),
.I3(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29] [10]),
.O(\pre_next_word_1_reg[2]_0 ));
LUT4 #(
.INIT(16'hFE02))
\pre_next_word_1[2]_i_4
(.I0(\current_word_1_reg[2]_0 [1]),
.I1(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29] [12]),
.I2(first_word),
.I3(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29] [9]),
.O(\pre_next_word_1_reg[2]_1 ));
FDRE \pre_next_word_1_reg[0]
(.C(s_axi_aclk),
.CE(E),
.D(D[0]),
.Q(\current_word_1_reg[2]_0 [0]),
.R(s_axi_aresetn));
FDRE \pre_next_word_1_reg[1]
(.C(s_axi_aclk),
.CE(E),
.D(D[1]),
.Q(\current_word_1_reg[2]_0 [1]),
.R(s_axi_aresetn));
FDRE \pre_next_word_1_reg[2]
(.C(s_axi_aclk),
.CE(E),
.D(D[2]),
.Q(\current_word_1_reg[2]_0 [2]),
.R(s_axi_aresetn));
FDRE \rresp_wrap_buffer_reg[0]
(.C(s_axi_aclk),
.CE(m_valid_i_reg),
.D(Q[64]),
.Q(rresp_wrap_buffer[0]),
.R(s_axi_aresetn));
FDRE \rresp_wrap_buffer_reg[1]
(.C(s_axi_aclk),
.CE(m_valid_i_reg),
.D(Q[65]),
.Q(rresp_wrap_buffer[1]),
.R(s_axi_aresetn));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\s_axi_rdata[0]_INST_0
(.I0(M_AXI_RDATA_I[0]),
.I1(M_AXI_RDATA_I[32]),
.I2(use_wrap_buffer),
.I3(Q[0]),
.I4(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[25] ),
.I5(Q[32]),
.O(s_axi_rdata[0]));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\s_axi_rdata[10]_INST_0
(.I0(M_AXI_RDATA_I[10]),
.I1(M_AXI_RDATA_I[42]),
.I2(use_wrap_buffer),
.I3(Q[10]),
.I4(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[25] ),
.I5(Q[42]),
.O(s_axi_rdata[10]));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\s_axi_rdata[11]_INST_0
(.I0(M_AXI_RDATA_I[11]),
.I1(M_AXI_RDATA_I[43]),
.I2(use_wrap_buffer),
.I3(Q[11]),
.I4(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[25] ),
.I5(Q[43]),
.O(s_axi_rdata[11]));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\s_axi_rdata[12]_INST_0
(.I0(M_AXI_RDATA_I[12]),
.I1(M_AXI_RDATA_I[44]),
.I2(use_wrap_buffer),
.I3(Q[12]),
.I4(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[25] ),
.I5(Q[44]),
.O(s_axi_rdata[12]));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\s_axi_rdata[13]_INST_0
(.I0(M_AXI_RDATA_I[13]),
.I1(M_AXI_RDATA_I[45]),
.I2(use_wrap_buffer),
.I3(Q[13]),
.I4(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[25] ),
.I5(Q[45]),
.O(s_axi_rdata[13]));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\s_axi_rdata[14]_INST_0
(.I0(M_AXI_RDATA_I[14]),
.I1(M_AXI_RDATA_I[46]),
.I2(use_wrap_buffer),
.I3(Q[14]),
.I4(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[25] ),
.I5(Q[46]),
.O(s_axi_rdata[14]));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\s_axi_rdata[15]_INST_0
(.I0(M_AXI_RDATA_I[15]),
.I1(M_AXI_RDATA_I[47]),
.I2(use_wrap_buffer),
.I3(Q[15]),
.I4(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[25] ),
.I5(Q[47]),
.O(s_axi_rdata[15]));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\s_axi_rdata[16]_INST_0
(.I0(M_AXI_RDATA_I[16]),
.I1(M_AXI_RDATA_I[48]),
.I2(use_wrap_buffer),
.I3(Q[16]),
.I4(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[25] ),
.I5(Q[48]),
.O(s_axi_rdata[16]));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\s_axi_rdata[17]_INST_0
(.I0(M_AXI_RDATA_I[17]),
.I1(M_AXI_RDATA_I[49]),
.I2(use_wrap_buffer),
.I3(Q[17]),
.I4(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[25] ),
.I5(Q[49]),
.O(s_axi_rdata[17]));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\s_axi_rdata[18]_INST_0
(.I0(M_AXI_RDATA_I[18]),
.I1(M_AXI_RDATA_I[50]),
.I2(use_wrap_buffer),
.I3(Q[18]),
.I4(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[25] ),
.I5(Q[50]),
.O(s_axi_rdata[18]));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\s_axi_rdata[19]_INST_0
(.I0(M_AXI_RDATA_I[19]),
.I1(M_AXI_RDATA_I[51]),
.I2(use_wrap_buffer),
.I3(Q[19]),
.I4(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[25] ),
.I5(Q[51]),
.O(s_axi_rdata[19]));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\s_axi_rdata[1]_INST_0
(.I0(M_AXI_RDATA_I[1]),
.I1(M_AXI_RDATA_I[33]),
.I2(use_wrap_buffer),
.I3(Q[1]),
.I4(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[25] ),
.I5(Q[33]),
.O(s_axi_rdata[1]));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\s_axi_rdata[20]_INST_0
(.I0(M_AXI_RDATA_I[20]),
.I1(M_AXI_RDATA_I[52]),
.I2(use_wrap_buffer),
.I3(Q[20]),
.I4(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[25] ),
.I5(Q[52]),
.O(s_axi_rdata[20]));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\s_axi_rdata[21]_INST_0
(.I0(M_AXI_RDATA_I[21]),
.I1(M_AXI_RDATA_I[53]),
.I2(use_wrap_buffer),
.I3(Q[21]),
.I4(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[25] ),
.I5(Q[53]),
.O(s_axi_rdata[21]));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\s_axi_rdata[22]_INST_0
(.I0(M_AXI_RDATA_I[22]),
.I1(M_AXI_RDATA_I[54]),
.I2(use_wrap_buffer),
.I3(Q[22]),
.I4(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[25] ),
.I5(Q[54]),
.O(s_axi_rdata[22]));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\s_axi_rdata[23]_INST_0
(.I0(M_AXI_RDATA_I[23]),
.I1(M_AXI_RDATA_I[55]),
.I2(use_wrap_buffer),
.I3(Q[23]),
.I4(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[25] ),
.I5(Q[55]),
.O(s_axi_rdata[23]));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\s_axi_rdata[24]_INST_0
(.I0(M_AXI_RDATA_I[24]),
.I1(M_AXI_RDATA_I[56]),
.I2(use_wrap_buffer),
.I3(Q[24]),
.I4(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[25] ),
.I5(Q[56]),
.O(s_axi_rdata[24]));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\s_axi_rdata[25]_INST_0
(.I0(M_AXI_RDATA_I[25]),
.I1(M_AXI_RDATA_I[57]),
.I2(use_wrap_buffer),
.I3(Q[25]),
.I4(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[25] ),
.I5(Q[57]),
.O(s_axi_rdata[25]));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\s_axi_rdata[26]_INST_0
(.I0(M_AXI_RDATA_I[26]),
.I1(M_AXI_RDATA_I[58]),
.I2(use_wrap_buffer),
.I3(Q[26]),
.I4(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[25] ),
.I5(Q[58]),
.O(s_axi_rdata[26]));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\s_axi_rdata[27]_INST_0
(.I0(M_AXI_RDATA_I[27]),
.I1(M_AXI_RDATA_I[59]),
.I2(use_wrap_buffer),
.I3(Q[27]),
.I4(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[25] ),
.I5(Q[59]),
.O(s_axi_rdata[27]));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\s_axi_rdata[28]_INST_0
(.I0(M_AXI_RDATA_I[28]),
.I1(M_AXI_RDATA_I[60]),
.I2(use_wrap_buffer),
.I3(Q[28]),
.I4(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[25] ),
.I5(Q[60]),
.O(s_axi_rdata[28]));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\s_axi_rdata[29]_INST_0
(.I0(M_AXI_RDATA_I[29]),
.I1(M_AXI_RDATA_I[61]),
.I2(use_wrap_buffer),
.I3(Q[29]),
.I4(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[25] ),
.I5(Q[61]),
.O(s_axi_rdata[29]));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\s_axi_rdata[2]_INST_0
(.I0(M_AXI_RDATA_I[2]),
.I1(M_AXI_RDATA_I[34]),
.I2(use_wrap_buffer),
.I3(Q[2]),
.I4(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[25] ),
.I5(Q[34]),
.O(s_axi_rdata[2]));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\s_axi_rdata[30]_INST_0
(.I0(M_AXI_RDATA_I[30]),
.I1(M_AXI_RDATA_I[62]),
.I2(use_wrap_buffer),
.I3(Q[30]),
.I4(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[25] ),
.I5(Q[62]),
.O(s_axi_rdata[30]));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\s_axi_rdata[31]_INST_0
(.I0(M_AXI_RDATA_I[31]),
.I1(M_AXI_RDATA_I[63]),
.I2(use_wrap_buffer),
.I3(Q[31]),
.I4(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[25] ),
.I5(Q[63]),
.O(s_axi_rdata[31]));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\s_axi_rdata[3]_INST_0
(.I0(M_AXI_RDATA_I[3]),
.I1(M_AXI_RDATA_I[35]),
.I2(use_wrap_buffer),
.I3(Q[3]),
.I4(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[25] ),
.I5(Q[35]),
.O(s_axi_rdata[3]));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\s_axi_rdata[4]_INST_0
(.I0(M_AXI_RDATA_I[4]),
.I1(M_AXI_RDATA_I[36]),
.I2(use_wrap_buffer),
.I3(Q[4]),
.I4(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[25] ),
.I5(Q[36]),
.O(s_axi_rdata[4]));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\s_axi_rdata[5]_INST_0
(.I0(M_AXI_RDATA_I[5]),
.I1(M_AXI_RDATA_I[37]),
.I2(use_wrap_buffer),
.I3(Q[5]),
.I4(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[25] ),
.I5(Q[37]),
.O(s_axi_rdata[5]));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\s_axi_rdata[6]_INST_0
(.I0(M_AXI_RDATA_I[6]),
.I1(M_AXI_RDATA_I[38]),
.I2(use_wrap_buffer),
.I3(Q[6]),
.I4(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[25] ),
.I5(Q[38]),
.O(s_axi_rdata[6]));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\s_axi_rdata[7]_INST_0
(.I0(M_AXI_RDATA_I[7]),
.I1(M_AXI_RDATA_I[39]),
.I2(use_wrap_buffer),
.I3(Q[7]),
.I4(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[25] ),
.I5(Q[39]),
.O(s_axi_rdata[7]));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\s_axi_rdata[8]_INST_0
(.I0(M_AXI_RDATA_I[8]),
.I1(M_AXI_RDATA_I[40]),
.I2(use_wrap_buffer),
.I3(Q[8]),
.I4(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[25] ),
.I5(Q[40]),
.O(s_axi_rdata[8]));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\s_axi_rdata[9]_INST_0
(.I0(M_AXI_RDATA_I[9]),
.I1(M_AXI_RDATA_I[41]),
.I2(use_wrap_buffer),
.I3(Q[9]),
.I4(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[25] ),
.I5(Q[41]),
.O(s_axi_rdata[9]));
LUT6 #(
.INIT(64'h0000F100F1000000))
s_axi_rlast_INST_0
(.I0(wrap_buffer_available),
.I1(use_wrap_buffer_reg_0),
.I2(use_wrap_buffer),
.I3(\current_word_1_reg[0]_0 ),
.I4(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29] [8]),
.I5(s_axi_rlast_INST_0_i_3_n_0),
.O(s_axi_rlast));
LUT6 #(
.INIT(64'hFFFEEEFEFFFFFFFF))
s_axi_rlast_INST_0_i_1
(.I0(s_axi_rlast_INST_0_i_4_n_0),
.I1(s_axi_rlast_INST_0_i_5_n_0),
.I2(\USE_RTL_LENGTH.length_counter_q_reg [7]),
.I3(first_mi_word_q),
.I4(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29] [7]),
.I5(s_axi_rlast_INST_0_i_6_n_0),
.O(use_wrap_buffer_reg_0));
LUT4 #(
.INIT(16'h01FD))
s_axi_rlast_INST_0_i_3
(.I0(first_word_reg_0[2]),
.I1(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29] [12]),
.I2(first_word),
.I3(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29] [11]),
.O(s_axi_rlast_INST_0_i_3_n_0));
(* SOFT_HLUTNM = "soft_lutpair34" *)
LUT5 #(
.INIT(32'hFFFACCFA))
s_axi_rlast_INST_0_i_4
(.I0(\USE_RTL_LENGTH.length_counter_q_reg [5]),
.I1(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29] [5]),
.I2(\USE_RTL_LENGTH.length_counter_q_reg [4]),
.I3(first_mi_word_q),
.I4(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29] [4]),
.O(s_axi_rlast_INST_0_i_4_n_0));
(* SOFT_HLUTNM = "soft_lutpair36" *)
LUT3 #(
.INIT(8'hB8))
s_axi_rlast_INST_0_i_5
(.I0(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29] [6]),
.I1(first_mi_word_q),
.I2(\USE_RTL_LENGTH.length_counter_q_reg [6]),
.O(s_axi_rlast_INST_0_i_5_n_0));
LUT6 #(
.INIT(64'h0000003050500030))
s_axi_rlast_INST_0_i_6
(.I0(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29] [2]),
.I1(\USE_RTL_LENGTH.length_counter_q_reg [2]),
.I2(\USE_RTL_LENGTH.length_counter_q[3]_i_2__0_n_0 ),
.I3(\USE_RTL_LENGTH.length_counter_q_reg [3]),
.I4(first_mi_word_q),
.I5(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29] [3]),
.O(s_axi_rlast_INST_0_i_6_n_0));
(* SOFT_HLUTNM = "soft_lutpair38" *)
LUT3 #(
.INIT(8'hB8))
\s_axi_rresp[0]_INST_0
(.I0(rresp_wrap_buffer[0]),
.I1(use_wrap_buffer),
.I2(Q[64]),
.O(s_axi_rresp[0]));
(* SOFT_HLUTNM = "soft_lutpair38" *)
LUT3 #(
.INIT(8'hB8))
\s_axi_rresp[1]_INST_0
(.I0(rresp_wrap_buffer[1]),
.I1(use_wrap_buffer),
.I2(Q[65]),
.O(s_axi_rresp[1]));
LUT6 #(
.INIT(64'h888888888888888A))
s_ready_i_i_2__0
(.I0(s_axi_rready),
.I1(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28] ),
.I2(\current_word_1_reg[2]_1 ),
.I3(use_wrap_buffer),
.I4(use_wrap_buffer_reg_0),
.I5(wrap_buffer_available),
.O(s_ready_i_reg));
LUT6 #(
.INIT(64'hCC0CCCBECC0CCC0C))
use_wrap_buffer_i_1
(.I0(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28] ),
.I1(use_wrap_buffer),
.I2(s_axi_rlast),
.I3(use_wrap_buffer_i_2_n_0),
.I4(use_wrap_buffer_reg_0),
.I5(wrap_buffer_available),
.O(use_wrap_buffer_i_1_n_0));
LUT4 #(
.INIT(16'h1FFF))
use_wrap_buffer_i_2
(.I0(use_wrap_buffer),
.I1(mr_rvalid),
.I2(rd_cmd_valid),
.I3(s_axi_rready),
.O(use_wrap_buffer_i_2_n_0));
FDRE use_wrap_buffer_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(use_wrap_buffer_i_1_n_0),
.Q(use_wrap_buffer),
.R(s_axi_aresetn));
LUT6 #(
.INIT(64'hFFFFFFF800008888))
wrap_buffer_available_i_1__0
(.I0(m_valid_i_reg),
.I1(s_axi_rready),
.I2(use_wrap_buffer_reg_0),
.I3(use_wrap_buffer_i_2_n_0),
.I4(wrap_buffer_available_i_2__0_n_0),
.I5(wrap_buffer_available),
.O(wrap_buffer_available_i_1__0_n_0));
LUT5 #(
.INIT(32'h0000FFFE))
wrap_buffer_available_i_2__0
(.I0(wrap_buffer_available),
.I1(use_wrap_buffer_reg_0),
.I2(use_wrap_buffer),
.I3(\current_word_1_reg[2]_1 ),
.I4(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28] ),
.O(wrap_buffer_available_i_2__0_n_0));
FDRE wrap_buffer_available_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(wrap_buffer_available_i_1__0_n_0),
.Q(wrap_buffer_available),
.R(s_axi_aresetn));
endmodule
|
module system_auto_us_0_axi_dwidth_converter_v2_1_11_top
(s_axi_aclk,
s_axi_aresetn,
s_axi_awid,
s_axi_awaddr,
s_axi_awlen,
s_axi_awsize,
s_axi_awburst,
s_axi_awlock,
s_axi_awcache,
s_axi_awprot,
s_axi_awregion,
s_axi_awqos,
s_axi_awvalid,
s_axi_awready,
s_axi_wdata,
s_axi_wstrb,
s_axi_wlast,
s_axi_wvalid,
s_axi_wready,
s_axi_bid,
s_axi_bresp,
s_axi_bvalid,
s_axi_bready,
s_axi_arid,
s_axi_araddr,
s_axi_arlen,
s_axi_arsize,
s_axi_arburst,
s_axi_arlock,
s_axi_arcache,
s_axi_arprot,
s_axi_arregion,
s_axi_arqos,
s_axi_arvalid,
s_axi_arready,
s_axi_rid,
s_axi_rdata,
s_axi_rresp,
s_axi_rlast,
s_axi_rvalid,
s_axi_rready,
m_axi_aclk,
m_axi_aresetn,
m_axi_awaddr,
m_axi_awlen,
m_axi_awsize,
m_axi_awburst,
m_axi_awlock,
m_axi_awcache,
m_axi_awprot,
m_axi_awregion,
m_axi_awqos,
m_axi_awvalid,
m_axi_awready,
m_axi_wdata,
m_axi_wstrb,
m_axi_wlast,
m_axi_wvalid,
m_axi_wready,
m_axi_bresp,
m_axi_bvalid,
m_axi_bready,
m_axi_araddr,
m_axi_arlen,
m_axi_arsize,
m_axi_arburst,
m_axi_arlock,
m_axi_arcache,
m_axi_arprot,
m_axi_arregion,
m_axi_arqos,
m_axi_arvalid,
m_axi_arready,
m_axi_rdata,
m_axi_rresp,
m_axi_rlast,
m_axi_rvalid,
m_axi_rready);
(* keep = "true" *) input s_axi_aclk;
(* keep = "true" *) input s_axi_aresetn;
input [0:0]s_axi_awid;
input [31:0]s_axi_awaddr;
input [7:0]s_axi_awlen;
input [2:0]s_axi_awsize;
input [1:0]s_axi_awburst;
input [0:0]s_axi_awlock;
input [3:0]s_axi_awcache;
input [2:0]s_axi_awprot;
input [3:0]s_axi_awregion;
input [3:0]s_axi_awqos;
input s_axi_awvalid;
output s_axi_awready;
input [31:0]s_axi_wdata;
input [3:0]s_axi_wstrb;
input s_axi_wlast;
input s_axi_wvalid;
output s_axi_wready;
output [0:0]s_axi_bid;
output [1:0]s_axi_bresp;
output s_axi_bvalid;
input s_axi_bready;
input [0:0]s_axi_arid;
input [31:0]s_axi_araddr;
input [7:0]s_axi_arlen;
input [2:0]s_axi_arsize;
input [1:0]s_axi_arburst;
input [0:0]s_axi_arlock;
input [3:0]s_axi_arcache;
input [2:0]s_axi_arprot;
input [3:0]s_axi_arregion;
input [3:0]s_axi_arqos;
input s_axi_arvalid;
output s_axi_arready;
output [0:0]s_axi_rid;
output [31:0]s_axi_rdata;
output [1:0]s_axi_rresp;
output s_axi_rlast;
output s_axi_rvalid;
input s_axi_rready;
(* keep = "true" *) input m_axi_aclk;
(* keep = "true" *) input m_axi_aresetn;
output [31:0]m_axi_awaddr;
output [7:0]m_axi_awlen;
output [2:0]m_axi_awsize;
output [1:0]m_axi_awburst;
output [0:0]m_axi_awlock;
output [3:0]m_axi_awcache;
output [2:0]m_axi_awprot;
output [3:0]m_axi_awregion;
output [3:0]m_axi_awqos;
output m_axi_awvalid;
input m_axi_awready;
output [63:0]m_axi_wdata;
output [7:0]m_axi_wstrb;
output m_axi_wlast;
output m_axi_wvalid;
input m_axi_wready;
input [1:0]m_axi_bresp;
input m_axi_bvalid;
output m_axi_bready;
output [31:0]m_axi_araddr;
output [7:0]m_axi_arlen;
output [2:0]m_axi_arsize;
output [1:0]m_axi_arburst;
output [0:0]m_axi_arlock;
output [3:0]m_axi_arcache;
output [2:0]m_axi_arprot;
output [3:0]m_axi_arregion;
output [3:0]m_axi_arqos;
output m_axi_arvalid;
input m_axi_arready;
input [63:0]m_axi_rdata;
input [1:0]m_axi_rresp;
input m_axi_rlast;
input m_axi_rvalid;
output m_axi_rready;
wire \<const0> ;
(* RTL_KEEP = "true" *) wire m_axi_aclk;
wire [31:0]m_axi_araddr;
wire [1:0]m_axi_arburst;
wire [3:0]m_axi_arcache;
(* RTL_KEEP = "true" *) wire m_axi_aresetn;
wire [7:0]m_axi_arlen;
wire [0:0]m_axi_arlock;
wire [2:0]m_axi_arprot;
wire [3:0]m_axi_arqos;
wire m_axi_arready;
wire [3:0]m_axi_arregion;
wire [2:0]m_axi_arsize;
wire m_axi_arvalid;
wire [31:0]m_axi_awaddr;
wire [1:0]m_axi_awburst;
wire [3:0]m_axi_awcache;
wire [7:0]m_axi_awlen;
wire [0:0]m_axi_awlock;
wire [2:0]m_axi_awprot;
wire [3:0]m_axi_awqos;
wire m_axi_awready;
wire [3:0]m_axi_awregion;
wire [2:0]m_axi_awsize;
wire m_axi_awvalid;
wire [1:0]m_axi_bresp;
wire m_axi_bvalid;
wire [63:0]m_axi_rdata;
wire m_axi_rlast;
wire m_axi_rready;
wire [1:0]m_axi_rresp;
wire m_axi_rvalid;
wire [63:0]m_axi_wdata;
wire m_axi_wlast;
wire m_axi_wready;
wire [7:0]m_axi_wstrb;
wire m_axi_wvalid;
(* RTL_KEEP = "true" *) wire s_axi_aclk;
wire [31:0]s_axi_araddr;
wire [1:0]s_axi_arburst;
wire [3:0]s_axi_arcache;
(* RTL_KEEP = "true" *) wire s_axi_aresetn;
wire [7:0]s_axi_arlen;
wire [0:0]s_axi_arlock;
wire [2:0]s_axi_arprot;
wire [3:0]s_axi_arqos;
wire s_axi_arready;
wire [3:0]s_axi_arregion;
wire [2:0]s_axi_arsize;
wire s_axi_arvalid;
wire [31:0]s_axi_awaddr;
wire [1:0]s_axi_awburst;
wire [3:0]s_axi_awcache;
wire [7:0]s_axi_awlen;
wire [0:0]s_axi_awlock;
wire [2:0]s_axi_awprot;
wire [3:0]s_axi_awqos;
wire s_axi_awready;
wire [3:0]s_axi_awregion;
wire [2:0]s_axi_awsize;
wire s_axi_awvalid;
wire s_axi_bready;
wire [31:0]s_axi_rdata;
wire s_axi_rlast;
wire s_axi_rready;
wire [1:0]s_axi_rresp;
wire s_axi_rvalid;
wire [31:0]s_axi_wdata;
wire s_axi_wlast;
wire s_axi_wready;
wire [3:0]s_axi_wstrb;
wire s_axi_wvalid;
assign m_axi_bready = s_axi_bready;
assign s_axi_bid[0] = \<const0> ;
assign s_axi_bresp[1:0] = m_axi_bresp;
assign s_axi_bvalid = m_axi_bvalid;
assign s_axi_rid[0] = \<const0> ;
GND GND
(.G(\<const0> ));
system_auto_us_0_axi_dwidth_converter_v2_1_11_axi_upsizer \gen_upsizer.gen_full_upsizer.axi_upsizer_inst
(.D({s_axi_awregion,s_axi_awqos,s_axi_awlock,s_axi_awlen,s_axi_awcache,s_axi_awburst,s_axi_awsize,s_axi_awprot,s_axi_awaddr}),
.Q({m_axi_arregion,m_axi_arqos,m_axi_arlock,m_axi_arcache,m_axi_arprot,m_axi_araddr[31:3]}),
.m_axi_araddr(m_axi_araddr[2:0]),
.m_axi_arburst(m_axi_arburst),
.m_axi_arlen(m_axi_arlen),
.m_axi_arready(m_axi_arready),
.m_axi_arsize(m_axi_arsize),
.m_axi_arvalid(m_axi_arvalid),
.m_axi_awaddr(m_axi_awaddr[5:0]),
.m_axi_awburst(m_axi_awburst),
.m_axi_awlen(m_axi_awlen),
.m_axi_awready(m_axi_awready),
.\m_axi_awregion[3] ({m_axi_awregion,m_axi_awqos,m_axi_awlock,m_axi_awcache,m_axi_awprot,m_axi_awaddr[31:6]}),
.m_axi_awsize(m_axi_awsize),
.m_axi_awvalid(m_axi_awvalid),
.m_axi_rdata(m_axi_rdata),
.m_axi_rlast(m_axi_rlast),
.m_axi_rready(m_axi_rready),
.m_axi_rresp(m_axi_rresp),
.m_axi_rvalid(m_axi_rvalid),
.m_axi_wdata(m_axi_wdata),
.m_axi_wlast(m_axi_wlast),
.m_axi_wready(m_axi_wready),
.m_axi_wstrb(m_axi_wstrb),
.m_axi_wvalid(m_axi_wvalid),
.out(s_axi_aresetn),
.s_axi_aclk(s_axi_aclk),
.s_axi_arready(s_axi_arready),
.\s_axi_arregion[3] ({s_axi_arregion,s_axi_arqos,s_axi_arlock,s_axi_arlen,s_axi_arcache,s_axi_arburst,s_axi_arsize,s_axi_arprot,s_axi_araddr}),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_awready(s_axi_awready),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_rdata(s_axi_rdata),
.s_axi_rlast(s_axi_rlast),
.s_axi_rready(s_axi_rready),
.s_axi_rresp(s_axi_rresp),
.s_axi_rvalid(s_axi_rvalid),
.s_axi_wdata(s_axi_wdata),
.s_axi_wlast(s_axi_wlast),
.s_axi_wready(s_axi_wready),
.s_axi_wstrb(s_axi_wstrb),
.s_axi_wvalid(s_axi_wvalid));
endmodule
|
module system_auto_us_0_axi_dwidth_converter_v2_1_11_w_upsizer
(first_word_q,
\USE_REGISTER.M_AXI_WLAST_q_reg_0 ,
p_251_in,
m_axi_wstrb,
wrap_buffer_available,
m_axi_wvalid,
m_axi_wlast,
\USE_RTL_LENGTH.first_mi_word_q_reg_0 ,
\USE_RTL_LENGTH.first_mi_word_q_reg_1 ,
\USE_RTL_LENGTH.first_mi_word_q_reg_2 ,
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[0]_0 ,
\USE_RTL_LENGTH.length_counter_q_reg[7]_0 ,
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29] ,
\USE_RTL_LENGTH.length_counter_q_reg[3]_0 ,
\USE_RTL_CURR_WORD.pre_next_word_q_reg[2]_0 ,
\USE_RTL_CURR_WORD.current_word_q_reg[2]_0 ,
\USE_RTL_CURR_WORD.pre_next_word_q_reg[2]_1 ,
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]_0 ,
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg[7]_0 ,
m_axi_wdata,
E,
s_axi_wlast,
s_axi_aclk,
SR,
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg ,
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_0 ,
m_axi_wready,
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[25] ,
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[25]_0 ,
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[25]_1 ,
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[25]_2 ,
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[25]_3 ,
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[25]_4 ,
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[25]_5 ,
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[25]_6 ,
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_1 ,
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_2 ,
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_3 ,
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_4 ,
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_5 ,
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_6 ,
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_7 ,
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_8 ,
Q,
s_axi_wdata,
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28] ,
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28]_0 ,
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28]_1 ,
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28]_2 ,
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28]_3 ,
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28]_4 ,
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28]_5 ,
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28]_6 ,
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[17] ,
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[18] ,
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[27] ,
s_axi_wvalid,
wr_cmd_valid,
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_9 ,
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28]_7 ,
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[19] ,
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]_1 ,
out,
D,
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[13] );
output first_word_q;
output \USE_REGISTER.M_AXI_WLAST_q_reg_0 ;
output p_251_in;
output [7:0]m_axi_wstrb;
output wrap_buffer_available;
output m_axi_wvalid;
output m_axi_wlast;
output \USE_RTL_LENGTH.first_mi_word_q_reg_0 ;
output \USE_RTL_LENGTH.first_mi_word_q_reg_1 ;
output \USE_RTL_LENGTH.first_mi_word_q_reg_2 ;
output \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[0]_0 ;
output \USE_RTL_LENGTH.length_counter_q_reg[7]_0 ;
output \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29] ;
output \USE_RTL_LENGTH.length_counter_q_reg[3]_0 ;
output \USE_RTL_CURR_WORD.pre_next_word_q_reg[2]_0 ;
output [2:0]\USE_RTL_CURR_WORD.current_word_q_reg[2]_0 ;
output \USE_RTL_CURR_WORD.pre_next_word_q_reg[2]_1 ;
output \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]_0 ;
output [2:0]\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg[7]_0 ;
output [63:0]m_axi_wdata;
input [0:0]E;
input s_axi_wlast;
input s_axi_aclk;
input [0:0]SR;
input \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg ;
input \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_0 ;
input m_axi_wready;
input \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[25] ;
input \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[25]_0 ;
input \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[25]_1 ;
input \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[25]_2 ;
input \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[25]_3 ;
input \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[25]_4 ;
input \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[25]_5 ;
input \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[25]_6 ;
input [0:0]\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_1 ;
input [0:0]\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_2 ;
input [0:0]\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_3 ;
input [0:0]\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_4 ;
input [0:0]\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_5 ;
input [0:0]\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_6 ;
input [0:0]\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_7 ;
input [0:0]\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_8 ;
input [14:0]Q;
input [31:0]s_axi_wdata;
input \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28] ;
input \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28]_0 ;
input \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28]_1 ;
input \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28]_2 ;
input \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28]_3 ;
input \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28]_4 ;
input \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28]_5 ;
input \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28]_6 ;
input \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[17] ;
input \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[18] ;
input \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[27] ;
input s_axi_wvalid;
input wr_cmd_valid;
input \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_9 ;
input \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28]_7 ;
input \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[19] ;
input \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]_1 ;
input out;
input [2:0]D;
input [2:0]\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[13] ;
wire [2:0]D;
wire [0:0]E;
wire [14:0]Q;
wire [0:0]SR;
wire \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[29]_i_6_n_0 ;
wire [2:0]\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[13] ;
wire \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[17] ;
wire \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[18] ;
wire \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[19] ;
wire \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[25] ;
wire \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[25]_0 ;
wire \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[25]_1 ;
wire \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[25]_2 ;
wire \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[25]_3 ;
wire \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[25]_4 ;
wire \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[25]_5 ;
wire \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[25]_6 ;
wire \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[27] ;
wire \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28] ;
wire \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28]_0 ;
wire \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28]_1 ;
wire \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28]_2 ;
wire \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28]_3 ;
wire \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28]_4 ;
wire \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28]_5 ;
wire \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28]_6 ;
wire \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28]_7 ;
wire \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29] ;
wire \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]_0 ;
wire \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]_1 ;
wire \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg ;
wire \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_0 ;
wire [0:0]\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_1 ;
wire [0:0]\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_2 ;
wire [0:0]\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_3 ;
wire [0:0]\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_4 ;
wire [0:0]\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_5 ;
wire [0:0]\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_6 ;
wire [0:0]\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_7 ;
wire [0:0]\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_8 ;
wire \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_9 ;
wire \USE_REGISTER.M_AXI_WLAST_q_i_1_n_0 ;
wire \USE_REGISTER.M_AXI_WLAST_q_reg_0 ;
wire [2:0]\USE_RTL_CURR_WORD.current_word_q_reg[2]_0 ;
wire \USE_RTL_CURR_WORD.pre_next_word_q_reg[2]_0 ;
wire \USE_RTL_CURR_WORD.pre_next_word_q_reg[2]_1 ;
wire \USE_RTL_LENGTH.first_mi_word_q_i_6_n_0 ;
wire \USE_RTL_LENGTH.first_mi_word_q_i_7_n_0 ;
wire \USE_RTL_LENGTH.first_mi_word_q_reg_0 ;
wire \USE_RTL_LENGTH.first_mi_word_q_reg_1 ;
wire \USE_RTL_LENGTH.first_mi_word_q_reg_2 ;
wire \USE_RTL_LENGTH.length_counter_q[0]_i_1_n_0 ;
wire \USE_RTL_LENGTH.length_counter_q[1]_i_1_n_0 ;
wire \USE_RTL_LENGTH.length_counter_q[2]_i_1_n_0 ;
wire \USE_RTL_LENGTH.length_counter_q[3]_i_1_n_0 ;
wire \USE_RTL_LENGTH.length_counter_q[4]_i_1_n_0 ;
wire \USE_RTL_LENGTH.length_counter_q[5]_i_1_n_0 ;
wire \USE_RTL_LENGTH.length_counter_q[5]_i_2_n_0 ;
wire \USE_RTL_LENGTH.length_counter_q[6]_i_1_n_0 ;
wire \USE_RTL_LENGTH.length_counter_q[7]_i_1_n_0 ;
wire \USE_RTL_LENGTH.length_counter_q[7]_i_3_n_0 ;
wire [7:0]\USE_RTL_LENGTH.length_counter_q_reg ;
wire \USE_RTL_LENGTH.length_counter_q_reg[3]_0 ;
wire \USE_RTL_LENGTH.length_counter_q_reg[7]_0 ;
wire \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[7]_i_1_n_0 ;
wire \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[0]_0 ;
wire \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I[0]_i_1_n_0 ;
wire [7:0]\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg ;
wire [2:0]\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg[7]_0 ;
wire \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wstrb_wrap_buffer_q[0]_i_1_n_0 ;
wire \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wstrb_wrap_buffer_q_reg_n_0_[0] ;
wire \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[10]_i_1_n_0 ;
wire \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[11]_i_1_n_0 ;
wire \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[12]_i_1_n_0 ;
wire \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[13]_i_1_n_0 ;
wire \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[14]_i_1_n_0 ;
wire \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[15]_i_1_n_0 ;
wire \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[15]_i_2_n_0 ;
wire \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[8]_i_1_n_0 ;
wire \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[9]_i_1_n_0 ;
wire \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I[1]_i_1_n_0 ;
wire [7:0]\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg ;
wire \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wstrb_wrap_buffer_q[1]_i_1_n_0 ;
wire \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[16]_i_1_n_0 ;
wire \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[17]_i_1_n_0 ;
wire \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[18]_i_1_n_0 ;
wire \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[19]_i_1_n_0 ;
wire \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[20]_i_1_n_0 ;
wire \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[21]_i_1_n_0 ;
wire \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[22]_i_1_n_0 ;
wire \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[23]_i_1_n_0 ;
wire \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[23]_i_2_n_0 ;
wire \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I[2]_i_1_n_0 ;
wire [7:0]\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg ;
wire \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wstrb_wrap_buffer_q[2]_i_1_n_0 ;
wire \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[24]_i_1_n_0 ;
wire \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[25]_i_1_n_0 ;
wire \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[26]_i_1_n_0 ;
wire \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[27]_i_1_n_0 ;
wire \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[28]_i_1_n_0 ;
wire \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[29]_i_1_n_0 ;
wire \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[30]_i_1_n_0 ;
wire \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[31]_i_1_n_0 ;
wire \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[31]_i_2_n_0 ;
wire \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I[3]_i_1_n_0 ;
wire [7:0]\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg ;
wire \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wstrb_wrap_buffer_q[3]_i_1_n_0 ;
wire \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[32]_i_1_n_0 ;
wire \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[33]_i_1_n_0 ;
wire \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[34]_i_1_n_0 ;
wire \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[35]_i_1_n_0 ;
wire \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[36]_i_1_n_0 ;
wire \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[37]_i_1_n_0 ;
wire \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[38]_i_1_n_0 ;
wire \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[39]_i_1_n_0 ;
wire \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[39]_i_2_n_0 ;
wire \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I[4]_i_1_n_0 ;
wire [7:0]\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg ;
wire \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wstrb_wrap_buffer_q[4]_i_1_n_0 ;
wire \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[40]_i_1_n_0 ;
wire \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[41]_i_1_n_0 ;
wire \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[42]_i_1_n_0 ;
wire \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[43]_i_1_n_0 ;
wire \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[44]_i_1_n_0 ;
wire \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[45]_i_1_n_0 ;
wire \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[46]_i_1_n_0 ;
wire \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[47]_i_1_n_0 ;
wire \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[47]_i_2_n_0 ;
wire \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I[5]_i_1_n_0 ;
wire [7:0]\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg ;
wire \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wstrb_wrap_buffer_q[5]_i_1_n_0 ;
wire \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[48]_i_1_n_0 ;
wire \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[49]_i_1_n_0 ;
wire \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[50]_i_1_n_0 ;
wire \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[51]_i_1_n_0 ;
wire \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[52]_i_1_n_0 ;
wire \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[53]_i_1_n_0 ;
wire \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[54]_i_1_n_0 ;
wire \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[55]_i_1_n_0 ;
wire \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[55]_i_2_n_0 ;
wire \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I[6]_i_1_n_0 ;
wire [7:0]\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg ;
wire \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wstrb_wrap_buffer_q[6]_i_1_n_0 ;
wire \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[56]_i_1_n_0 ;
wire \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[57]_i_1_n_0 ;
wire \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[58]_i_1_n_0 ;
wire \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[59]_i_1_n_0 ;
wire \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[60]_i_1_n_0 ;
wire \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[61]_i_1_n_0 ;
wire \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[62]_i_1_n_0 ;
wire \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_10_n_0 ;
wire \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_11_n_0 ;
wire \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_13_n_0 ;
wire \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_14_n_0 ;
wire \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_2_n_0 ;
wire \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_3_n_0 ;
wire \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_5_n_0 ;
wire \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_6_n_0 ;
wire \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_8_n_0 ;
wire \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I[7]_i_1_n_0 ;
wire [7:0]\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg ;
wire \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wstrb_wrap_buffer_q[7]_i_1_n_0 ;
wire first_mi_word_q;
wire first_word_q;
wire [63:0]m_axi_wdata;
wire m_axi_wlast;
wire m_axi_wready;
wire [7:0]m_axi_wstrb;
wire m_axi_wvalid;
wire out;
wire [7:0]p_1_in;
wire p_251_in;
wire s_axi_aclk;
wire [31:0]s_axi_wdata;
wire s_axi_wlast;
wire s_axi_wvalid;
wire wr_cmd_valid;
wire wrap_buffer_available;
wire wstrb_wrap_buffer_1;
wire wstrb_wrap_buffer_2;
wire wstrb_wrap_buffer_3;
wire wstrb_wrap_buffer_4;
wire wstrb_wrap_buffer_5;
wire wstrb_wrap_buffer_6;
wire wstrb_wrap_buffer_7;
LUT6 #(
.INIT(64'h000000000000B847))
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[29]_i_2
(.I0(\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg[7]_0 [0]),
.I1(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]_1 ),
.I2(Q[11]),
.I3(Q[8]),
.I4(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[29]_i_6_n_0 ),
.I5(\USE_RTL_LENGTH.length_counter_q_reg[3]_0 ),
.O(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]_0 ));
LUT6 #(
.INIT(64'hD000D0D000000000))
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[29]_i_5
(.I0(m_axi_wvalid),
.I1(m_axi_wready),
.I2(s_axi_wvalid),
.I3(wrap_buffer_available),
.I4(Q[12]),
.I5(wr_cmd_valid),
.O(\USE_RTL_LENGTH.first_mi_word_q_reg_2 ));
(* SOFT_HLUTNM = "soft_lutpair50" *)
LUT3 #(
.INIT(8'hB8))
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[29]_i_6
(.I0(Q[2]),
.I1(first_mi_word_q),
.I2(\USE_RTL_LENGTH.length_counter_q_reg [2]),
.O(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[29]_i_6_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair45" *)
LUT5 #(
.INIT(32'hFFFACCFA))
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[29]_i_7
(.I0(\USE_RTL_LENGTH.length_counter_q_reg [3]),
.I1(Q[3]),
.I2(\USE_RTL_LENGTH.length_counter_q_reg [4]),
.I3(first_mi_word_q),
.I4(Q[4]),
.O(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29] ));
LUT4 #(
.INIT(16'hBA8A))
\USE_REGISTER.M_AXI_WLAST_q_i_1
(.I0(s_axi_wlast),
.I1(m_axi_wready),
.I2(m_axi_wvalid),
.I3(m_axi_wlast),
.O(\USE_REGISTER.M_AXI_WLAST_q_i_1_n_0 ));
FDRE \USE_REGISTER.M_AXI_WLAST_q_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(\USE_REGISTER.M_AXI_WLAST_q_i_1_n_0 ),
.Q(m_axi_wlast),
.R(\USE_REGISTER.M_AXI_WLAST_q_reg_0 ));
FDRE \USE_REGISTER.M_AXI_WVALID_q_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_0 ),
.Q(m_axi_wvalid),
.R(\USE_REGISTER.M_AXI_WLAST_q_reg_0 ));
FDRE \USE_RTL_CURR_WORD.current_word_q_reg[0]
(.C(s_axi_aclk),
.CE(E),
.D(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[13] [0]),
.Q(\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg[7]_0 [0]),
.R(\USE_REGISTER.M_AXI_WLAST_q_reg_0 ));
FDRE \USE_RTL_CURR_WORD.current_word_q_reg[1]
(.C(s_axi_aclk),
.CE(E),
.D(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[13] [1]),
.Q(\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg[7]_0 [1]),
.R(\USE_REGISTER.M_AXI_WLAST_q_reg_0 ));
FDRE \USE_RTL_CURR_WORD.current_word_q_reg[2]
(.C(s_axi_aclk),
.CE(E),
.D(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[13] [2]),
.Q(\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg[7]_0 [2]),
.R(\USE_REGISTER.M_AXI_WLAST_q_reg_0 ));
FDSE \USE_RTL_CURR_WORD.first_word_q_reg
(.C(s_axi_aclk),
.CE(E),
.D(s_axi_wlast),
.Q(first_word_q),
.S(\USE_REGISTER.M_AXI_WLAST_q_reg_0 ));
LUT4 #(
.INIT(16'h01FD))
\USE_RTL_CURR_WORD.pre_next_word_q[2]_i_2
(.I0(\USE_RTL_CURR_WORD.current_word_q_reg[2]_0 [2]),
.I1(Q[14]),
.I2(first_word_q),
.I3(Q[10]),
.O(\USE_RTL_CURR_WORD.pre_next_word_q_reg[2]_0 ));
LUT4 #(
.INIT(16'h01FD))
\USE_RTL_CURR_WORD.pre_next_word_q[2]_i_4
(.I0(\USE_RTL_CURR_WORD.current_word_q_reg[2]_0 [1]),
.I1(Q[14]),
.I2(first_word_q),
.I3(Q[9]),
.O(\USE_RTL_CURR_WORD.pre_next_word_q_reg[2]_1 ));
FDRE \USE_RTL_CURR_WORD.pre_next_word_q_reg[0]
(.C(s_axi_aclk),
.CE(E),
.D(D[0]),
.Q(\USE_RTL_CURR_WORD.current_word_q_reg[2]_0 [0]),
.R(\USE_REGISTER.M_AXI_WLAST_q_reg_0 ));
FDRE \USE_RTL_CURR_WORD.pre_next_word_q_reg[1]
(.C(s_axi_aclk),
.CE(E),
.D(D[1]),
.Q(\USE_RTL_CURR_WORD.current_word_q_reg[2]_0 [1]),
.R(\USE_REGISTER.M_AXI_WLAST_q_reg_0 ));
FDRE \USE_RTL_CURR_WORD.pre_next_word_q_reg[2]
(.C(s_axi_aclk),
.CE(E),
.D(D[2]),
.Q(\USE_RTL_CURR_WORD.current_word_q_reg[2]_0 [2]),
.R(\USE_REGISTER.M_AXI_WLAST_q_reg_0 ));
LUT6 #(
.INIT(64'hFFFF000400000000))
\USE_RTL_LENGTH.first_mi_word_q_i_1
(.I0(\USE_RTL_LENGTH.first_mi_word_q_reg_0 ),
.I1(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[17] ),
.I2(\USE_RTL_LENGTH.first_mi_word_q_reg_1 ),
.I3(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[18] ),
.I4(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[27] ),
.I5(\USE_RTL_LENGTH.first_mi_word_q_reg_2 ),
.O(p_251_in));
(* SOFT_HLUTNM = "soft_lutpair48" *)
LUT4 #(
.INIT(16'hFEAE))
\USE_RTL_LENGTH.first_mi_word_q_i_2
(.I0(\USE_RTL_LENGTH.length_counter_q_reg[3]_0 ),
.I1(\USE_RTL_LENGTH.length_counter_q_reg [2]),
.I2(first_mi_word_q),
.I3(Q[2]),
.O(\USE_RTL_LENGTH.first_mi_word_q_reg_0 ));
LUT6 #(
.INIT(64'hFFFFFFFFFFFFFFFB))
\USE_RTL_LENGTH.first_mi_word_q_i_4
(.I0(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[19] ),
.I1(Q[13]),
.I2(\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[0]_0 ),
.I3(\USE_RTL_LENGTH.first_mi_word_q_i_6_n_0 ),
.I4(\USE_RTL_LENGTH.first_mi_word_q_i_7_n_0 ),
.I5(\USE_RTL_LENGTH.length_counter_q_reg[7]_0 ),
.O(\USE_RTL_LENGTH.first_mi_word_q_reg_1 ));
(* SOFT_HLUTNM = "soft_lutpair49" *)
LUT3 #(
.INIT(8'hB8))
\USE_RTL_LENGTH.first_mi_word_q_i_6
(.I0(Q[4]),
.I1(first_mi_word_q),
.I2(\USE_RTL_LENGTH.length_counter_q_reg [4]),
.O(\USE_RTL_LENGTH.first_mi_word_q_i_6_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair45" *)
LUT3 #(
.INIT(8'hB8))
\USE_RTL_LENGTH.first_mi_word_q_i_7
(.I0(Q[3]),
.I1(first_mi_word_q),
.I2(\USE_RTL_LENGTH.length_counter_q_reg [3]),
.O(\USE_RTL_LENGTH.first_mi_word_q_i_7_n_0 ));
FDSE \USE_RTL_LENGTH.first_mi_word_q_reg
(.C(s_axi_aclk),
.CE(p_251_in),
.D(s_axi_wlast),
.Q(first_mi_word_q),
.S(\USE_REGISTER.M_AXI_WLAST_q_reg_0 ));
(* SOFT_HLUTNM = "soft_lutpair50" *)
LUT3 #(
.INIT(8'h1D))
\USE_RTL_LENGTH.length_counter_q[0]_i_1
(.I0(\USE_RTL_LENGTH.length_counter_q_reg [0]),
.I1(first_mi_word_q),
.I2(Q[0]),
.O(\USE_RTL_LENGTH.length_counter_q[0]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair46" *)
LUT5 #(
.INIT(32'hCCA533A5))
\USE_RTL_LENGTH.length_counter_q[1]_i_1
(.I0(\USE_RTL_LENGTH.length_counter_q_reg [0]),
.I1(Q[0]),
.I2(\USE_RTL_LENGTH.length_counter_q_reg [1]),
.I3(first_mi_word_q),
.I4(Q[1]),
.O(\USE_RTL_LENGTH.length_counter_q[1]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair48" *)
LUT4 #(
.INIT(16'hB847))
\USE_RTL_LENGTH.length_counter_q[2]_i_1
(.I0(Q[2]),
.I1(first_mi_word_q),
.I2(\USE_RTL_LENGTH.length_counter_q_reg [2]),
.I3(\USE_RTL_LENGTH.length_counter_q_reg[3]_0 ),
.O(\USE_RTL_LENGTH.length_counter_q[2]_i_1_n_0 ));
LUT6 #(
.INIT(64'hB8B8B88BB874B847))
\USE_RTL_LENGTH.length_counter_q[3]_i_1
(.I0(Q[3]),
.I1(first_mi_word_q),
.I2(\USE_RTL_LENGTH.length_counter_q_reg [3]),
.I3(\USE_RTL_LENGTH.length_counter_q_reg[3]_0 ),
.I4(\USE_RTL_LENGTH.length_counter_q_reg [2]),
.I5(Q[2]),
.O(\USE_RTL_LENGTH.length_counter_q[3]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair46" *)
LUT5 #(
.INIT(32'hFFFACCFA))
\USE_RTL_LENGTH.length_counter_q[3]_i_2
(.I0(\USE_RTL_LENGTH.length_counter_q_reg [0]),
.I1(Q[0]),
.I2(\USE_RTL_LENGTH.length_counter_q_reg [1]),
.I3(first_mi_word_q),
.I4(Q[1]),
.O(\USE_RTL_LENGTH.length_counter_q_reg[3]_0 ));
LUT6 #(
.INIT(64'hCCAACCAAC3AAC355))
\USE_RTL_LENGTH.length_counter_q[4]_i_1
(.I0(\USE_RTL_LENGTH.length_counter_q_reg [4]),
.I1(Q[4]),
.I2(Q[3]),
.I3(first_mi_word_q),
.I4(\USE_RTL_LENGTH.length_counter_q_reg [3]),
.I5(\USE_RTL_LENGTH.first_mi_word_q_reg_0 ),
.O(\USE_RTL_LENGTH.length_counter_q[4]_i_1_n_0 ));
LUT6 #(
.INIT(64'hC3AAC355CCAACCAA))
\USE_RTL_LENGTH.length_counter_q[5]_i_1
(.I0(\USE_RTL_LENGTH.length_counter_q_reg [5]),
.I1(Q[5]),
.I2(Q[4]),
.I3(first_mi_word_q),
.I4(\USE_RTL_LENGTH.length_counter_q_reg [4]),
.I5(\USE_RTL_LENGTH.length_counter_q[5]_i_2_n_0 ),
.O(\USE_RTL_LENGTH.length_counter_q[5]_i_1_n_0 ));
LUT6 #(
.INIT(64'h0000000305050003))
\USE_RTL_LENGTH.length_counter_q[5]_i_2
(.I0(Q[2]),
.I1(\USE_RTL_LENGTH.length_counter_q_reg [2]),
.I2(\USE_RTL_LENGTH.length_counter_q_reg[3]_0 ),
.I3(\USE_RTL_LENGTH.length_counter_q_reg [3]),
.I4(first_mi_word_q),
.I5(Q[3]),
.O(\USE_RTL_LENGTH.length_counter_q[5]_i_2_n_0 ));
LUT6 #(
.INIT(64'hC3AAC355CCAACCAA))
\USE_RTL_LENGTH.length_counter_q[6]_i_1
(.I0(\USE_RTL_LENGTH.length_counter_q_reg [6]),
.I1(Q[6]),
.I2(Q[5]),
.I3(first_mi_word_q),
.I4(\USE_RTL_LENGTH.length_counter_q_reg [5]),
.I5(\USE_RTL_LENGTH.length_counter_q[7]_i_3_n_0 ),
.O(\USE_RTL_LENGTH.length_counter_q[6]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair47" *)
LUT5 #(
.INIT(32'hE21DE2E2))
\USE_RTL_LENGTH.length_counter_q[7]_i_1
(.I0(\USE_RTL_LENGTH.length_counter_q_reg [7]),
.I1(first_mi_word_q),
.I2(Q[7]),
.I3(\USE_RTL_LENGTH.length_counter_q_reg[7]_0 ),
.I4(\USE_RTL_LENGTH.length_counter_q[7]_i_3_n_0 ),
.O(\USE_RTL_LENGTH.length_counter_q[7]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair44" *)
LUT5 #(
.INIT(32'hFFFACCFA))
\USE_RTL_LENGTH.length_counter_q[7]_i_2
(.I0(\USE_RTL_LENGTH.length_counter_q_reg [5]),
.I1(Q[5]),
.I2(\USE_RTL_LENGTH.length_counter_q_reg [6]),
.I3(first_mi_word_q),
.I4(Q[6]),
.O(\USE_RTL_LENGTH.length_counter_q_reg[7]_0 ));
LUT6 #(
.INIT(64'h0000000305050003))
\USE_RTL_LENGTH.length_counter_q[7]_i_3
(.I0(Q[3]),
.I1(\USE_RTL_LENGTH.length_counter_q_reg [3]),
.I2(\USE_RTL_LENGTH.first_mi_word_q_reg_0 ),
.I3(\USE_RTL_LENGTH.length_counter_q_reg [4]),
.I4(first_mi_word_q),
.I5(Q[4]),
.O(\USE_RTL_LENGTH.length_counter_q[7]_i_3_n_0 ));
FDRE \USE_RTL_LENGTH.length_counter_q_reg[0]
(.C(s_axi_aclk),
.CE(p_251_in),
.D(\USE_RTL_LENGTH.length_counter_q[0]_i_1_n_0 ),
.Q(\USE_RTL_LENGTH.length_counter_q_reg [0]),
.R(\USE_REGISTER.M_AXI_WLAST_q_reg_0 ));
FDRE \USE_RTL_LENGTH.length_counter_q_reg[1]
(.C(s_axi_aclk),
.CE(p_251_in),
.D(\USE_RTL_LENGTH.length_counter_q[1]_i_1_n_0 ),
.Q(\USE_RTL_LENGTH.length_counter_q_reg [1]),
.R(\USE_REGISTER.M_AXI_WLAST_q_reg_0 ));
FDRE \USE_RTL_LENGTH.length_counter_q_reg[2]
(.C(s_axi_aclk),
.CE(p_251_in),
.D(\USE_RTL_LENGTH.length_counter_q[2]_i_1_n_0 ),
.Q(\USE_RTL_LENGTH.length_counter_q_reg [2]),
.R(\USE_REGISTER.M_AXI_WLAST_q_reg_0 ));
FDRE \USE_RTL_LENGTH.length_counter_q_reg[3]
(.C(s_axi_aclk),
.CE(p_251_in),
.D(\USE_RTL_LENGTH.length_counter_q[3]_i_1_n_0 ),
.Q(\USE_RTL_LENGTH.length_counter_q_reg [3]),
.R(\USE_REGISTER.M_AXI_WLAST_q_reg_0 ));
FDRE \USE_RTL_LENGTH.length_counter_q_reg[4]
(.C(s_axi_aclk),
.CE(p_251_in),
.D(\USE_RTL_LENGTH.length_counter_q[4]_i_1_n_0 ),
.Q(\USE_RTL_LENGTH.length_counter_q_reg [4]),
.R(\USE_REGISTER.M_AXI_WLAST_q_reg_0 ));
FDRE \USE_RTL_LENGTH.length_counter_q_reg[5]
(.C(s_axi_aclk),
.CE(p_251_in),
.D(\USE_RTL_LENGTH.length_counter_q[5]_i_1_n_0 ),
.Q(\USE_RTL_LENGTH.length_counter_q_reg [5]),
.R(\USE_REGISTER.M_AXI_WLAST_q_reg_0 ));
FDRE \USE_RTL_LENGTH.length_counter_q_reg[6]
(.C(s_axi_aclk),
.CE(p_251_in),
.D(\USE_RTL_LENGTH.length_counter_q[6]_i_1_n_0 ),
.Q(\USE_RTL_LENGTH.length_counter_q_reg [6]),
.R(\USE_REGISTER.M_AXI_WLAST_q_reg_0 ));
FDRE \USE_RTL_LENGTH.length_counter_q_reg[7]
(.C(s_axi_aclk),
.CE(p_251_in),
.D(\USE_RTL_LENGTH.length_counter_q[7]_i_1_n_0 ),
.Q(\USE_RTL_LENGTH.length_counter_q_reg [7]),
.R(\USE_REGISTER.M_AXI_WLAST_q_reg_0 ));
LUT5 #(
.INIT(32'hF044F000))
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[0]_i_1
(.I0(\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_6_n_0 ),
.I1(\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wstrb_wrap_buffer_q_reg_n_0_[0] ),
.I2(s_axi_wdata[0]),
.I3(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28]_6 ),
.I4(\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg [0]),
.O(p_1_in[0]));
LUT5 #(
.INIT(32'hF044F000))
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[1]_i_1
(.I0(\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_6_n_0 ),
.I1(\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wstrb_wrap_buffer_q_reg_n_0_[0] ),
.I2(s_axi_wdata[1]),
.I3(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28]_6 ),
.I4(\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg [1]),
.O(p_1_in[1]));
LUT5 #(
.INIT(32'hF044F000))
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[2]_i_1
(.I0(\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_6_n_0 ),
.I1(\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wstrb_wrap_buffer_q_reg_n_0_[0] ),
.I2(s_axi_wdata[2]),
.I3(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28]_6 ),
.I4(\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg [2]),
.O(p_1_in[2]));
LUT5 #(
.INIT(32'hF044F000))
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[3]_i_1
(.I0(\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_6_n_0 ),
.I1(\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wstrb_wrap_buffer_q_reg_n_0_[0] ),
.I2(s_axi_wdata[3]),
.I3(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28]_6 ),
.I4(\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg [3]),
.O(p_1_in[3]));
LUT5 #(
.INIT(32'hF044F000))
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[4]_i_1
(.I0(\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_6_n_0 ),
.I1(\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wstrb_wrap_buffer_q_reg_n_0_[0] ),
.I2(s_axi_wdata[4]),
.I3(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28]_6 ),
.I4(\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg [4]),
.O(p_1_in[4]));
LUT5 #(
.INIT(32'hF044F000))
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[5]_i_1
(.I0(\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_6_n_0 ),
.I1(\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wstrb_wrap_buffer_q_reg_n_0_[0] ),
.I2(s_axi_wdata[5]),
.I3(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28]_6 ),
.I4(\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg [5]),
.O(p_1_in[5]));
LUT5 #(
.INIT(32'hF044F000))
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[6]_i_1
(.I0(\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_6_n_0 ),
.I1(\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wstrb_wrap_buffer_q_reg_n_0_[0] ),
.I2(s_axi_wdata[6]),
.I3(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28]_6 ),
.I4(\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg [6]),
.O(p_1_in[6]));
LUT5 #(
.INIT(32'hEAFFEAEA))
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[7]_i_1
(.I0(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28]_6 ),
.I1(m_axi_wvalid),
.I2(m_axi_wready),
.I3(\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_5_n_0 ),
.I4(\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wstrb_wrap_buffer_q_reg_n_0_[0] ),
.O(\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[7]_i_1_n_0 ));
LUT5 #(
.INIT(32'hF044F000))
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[7]_i_2
(.I0(\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_6_n_0 ),
.I1(\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wstrb_wrap_buffer_q_reg_n_0_[0] ),
.I2(s_axi_wdata[7]),
.I3(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28]_6 ),
.I4(\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg [7]),
.O(p_1_in[7]));
FDRE \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[0]
(.C(s_axi_aclk),
.CE(\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[7]_i_1_n_0 ),
.D(p_1_in[0]),
.Q(m_axi_wdata[0]),
.R(\USE_REGISTER.M_AXI_WLAST_q_reg_0 ));
FDRE \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[1]
(.C(s_axi_aclk),
.CE(\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[7]_i_1_n_0 ),
.D(p_1_in[1]),
.Q(m_axi_wdata[1]),
.R(\USE_REGISTER.M_AXI_WLAST_q_reg_0 ));
FDRE \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[2]
(.C(s_axi_aclk),
.CE(\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[7]_i_1_n_0 ),
.D(p_1_in[2]),
.Q(m_axi_wdata[2]),
.R(\USE_REGISTER.M_AXI_WLAST_q_reg_0 ));
FDRE \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[3]
(.C(s_axi_aclk),
.CE(\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[7]_i_1_n_0 ),
.D(p_1_in[3]),
.Q(m_axi_wdata[3]),
.R(\USE_REGISTER.M_AXI_WLAST_q_reg_0 ));
FDRE \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[4]
(.C(s_axi_aclk),
.CE(\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[7]_i_1_n_0 ),
.D(p_1_in[4]),
.Q(m_axi_wdata[4]),
.R(\USE_REGISTER.M_AXI_WLAST_q_reg_0 ));
FDRE \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[5]
(.C(s_axi_aclk),
.CE(\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[7]_i_1_n_0 ),
.D(p_1_in[5]),
.Q(m_axi_wdata[5]),
.R(\USE_REGISTER.M_AXI_WLAST_q_reg_0 ));
FDRE \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[6]
(.C(s_axi_aclk),
.CE(\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[7]_i_1_n_0 ),
.D(p_1_in[6]),
.Q(m_axi_wdata[6]),
.R(\USE_REGISTER.M_AXI_WLAST_q_reg_0 ));
FDRE \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[7]
(.C(s_axi_aclk),
.CE(\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[7]_i_1_n_0 ),
.D(p_1_in[7]),
.Q(m_axi_wdata[7]),
.R(\USE_REGISTER.M_AXI_WLAST_q_reg_0 ));
LUT6 #(
.INIT(64'hFFFFFFFF44F4F4F4))
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I[0]_i_1
(.I0(\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_5_n_0 ),
.I1(\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wstrb_wrap_buffer_q_reg_n_0_[0] ),
.I2(m_axi_wstrb[0]),
.I3(m_axi_wready),
.I4(m_axi_wvalid),
.I5(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[25]_6 ),
.O(\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I[0]_i_1_n_0 ));
FDRE \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[0]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I[0]_i_1_n_0 ),
.Q(m_axi_wstrb[0]),
.R(\USE_REGISTER.M_AXI_WLAST_q_reg_0 ));
FDRE \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg[0]
(.C(s_axi_aclk),
.CE(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_8 ),
.D(s_axi_wdata[0]),
.Q(\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg [0]),
.R(SR));
FDRE \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg[1]
(.C(s_axi_aclk),
.CE(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_8 ),
.D(s_axi_wdata[1]),
.Q(\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg [1]),
.R(SR));
FDRE \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg[2]
(.C(s_axi_aclk),
.CE(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_8 ),
.D(s_axi_wdata[2]),
.Q(\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg [2]),
.R(SR));
FDRE \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg[3]
(.C(s_axi_aclk),
.CE(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_8 ),
.D(s_axi_wdata[3]),
.Q(\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg [3]),
.R(SR));
FDRE \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg[4]
(.C(s_axi_aclk),
.CE(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_8 ),
.D(s_axi_wdata[4]),
.Q(\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg [4]),
.R(SR));
FDRE \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg[5]
(.C(s_axi_aclk),
.CE(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_8 ),
.D(s_axi_wdata[5]),
.Q(\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg [5]),
.R(SR));
FDRE \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg[6]
(.C(s_axi_aclk),
.CE(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_8 ),
.D(s_axi_wdata[6]),
.Q(\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg [6]),
.R(SR));
FDRE \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg[7]
(.C(s_axi_aclk),
.CE(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_8 ),
.D(s_axi_wdata[7]),
.Q(\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg [7]),
.R(SR));
LUT2 #(
.INIT(4'hE))
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wstrb_wrap_buffer_q[0]_i_1
(.I0(\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wstrb_wrap_buffer_q_reg_n_0_[0] ),
.I1(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_8 ),
.O(\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wstrb_wrap_buffer_q[0]_i_1_n_0 ));
FDRE \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wstrb_wrap_buffer_q_reg[0]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wstrb_wrap_buffer_q[0]_i_1_n_0 ),
.Q(\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wstrb_wrap_buffer_q_reg_n_0_[0] ),
.R(SR));
LUT5 #(
.INIT(32'hF044F000))
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[10]_i_1
(.I0(\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_6_n_0 ),
.I1(wstrb_wrap_buffer_1),
.I2(s_axi_wdata[10]),
.I3(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28]_5 ),
.I4(\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg [2]),
.O(\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[10]_i_1_n_0 ));
LUT5 #(
.INIT(32'hF044F000))
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[11]_i_1
(.I0(\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_6_n_0 ),
.I1(wstrb_wrap_buffer_1),
.I2(s_axi_wdata[11]),
.I3(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28]_5 ),
.I4(\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg [3]),
.O(\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[11]_i_1_n_0 ));
LUT5 #(
.INIT(32'hF044F000))
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[12]_i_1
(.I0(\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_6_n_0 ),
.I1(wstrb_wrap_buffer_1),
.I2(s_axi_wdata[12]),
.I3(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28]_5 ),
.I4(\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg [4]),
.O(\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[12]_i_1_n_0 ));
LUT5 #(
.INIT(32'hF044F000))
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[13]_i_1
(.I0(\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_6_n_0 ),
.I1(wstrb_wrap_buffer_1),
.I2(s_axi_wdata[13]),
.I3(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28]_5 ),
.I4(\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg [5]),
.O(\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[13]_i_1_n_0 ));
LUT5 #(
.INIT(32'hF044F000))
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[14]_i_1
(.I0(\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_6_n_0 ),
.I1(wstrb_wrap_buffer_1),
.I2(s_axi_wdata[14]),
.I3(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28]_5 ),
.I4(\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg [6]),
.O(\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[14]_i_1_n_0 ));
LUT5 #(
.INIT(32'hEAFFEAEA))
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[15]_i_1
(.I0(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28]_5 ),
.I1(m_axi_wvalid),
.I2(m_axi_wready),
.I3(\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_5_n_0 ),
.I4(wstrb_wrap_buffer_1),
.O(\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[15]_i_1_n_0 ));
LUT5 #(
.INIT(32'hF044F000))
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[15]_i_2
(.I0(\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_6_n_0 ),
.I1(wstrb_wrap_buffer_1),
.I2(s_axi_wdata[15]),
.I3(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28]_5 ),
.I4(\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg [7]),
.O(\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[15]_i_2_n_0 ));
LUT5 #(
.INIT(32'hF044F000))
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[8]_i_1
(.I0(\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_6_n_0 ),
.I1(wstrb_wrap_buffer_1),
.I2(s_axi_wdata[8]),
.I3(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28]_5 ),
.I4(\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg [0]),
.O(\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[8]_i_1_n_0 ));
LUT5 #(
.INIT(32'hF044F000))
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[9]_i_1
(.I0(\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_6_n_0 ),
.I1(wstrb_wrap_buffer_1),
.I2(s_axi_wdata[9]),
.I3(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28]_5 ),
.I4(\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg [1]),
.O(\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[9]_i_1_n_0 ));
FDRE \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[10]
(.C(s_axi_aclk),
.CE(\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[15]_i_1_n_0 ),
.D(\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[10]_i_1_n_0 ),
.Q(m_axi_wdata[10]),
.R(\USE_REGISTER.M_AXI_WLAST_q_reg_0 ));
FDRE \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[11]
(.C(s_axi_aclk),
.CE(\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[15]_i_1_n_0 ),
.D(\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[11]_i_1_n_0 ),
.Q(m_axi_wdata[11]),
.R(\USE_REGISTER.M_AXI_WLAST_q_reg_0 ));
FDRE \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[12]
(.C(s_axi_aclk),
.CE(\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[15]_i_1_n_0 ),
.D(\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[12]_i_1_n_0 ),
.Q(m_axi_wdata[12]),
.R(\USE_REGISTER.M_AXI_WLAST_q_reg_0 ));
FDRE \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[13]
(.C(s_axi_aclk),
.CE(\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[15]_i_1_n_0 ),
.D(\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[13]_i_1_n_0 ),
.Q(m_axi_wdata[13]),
.R(\USE_REGISTER.M_AXI_WLAST_q_reg_0 ));
FDRE \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[14]
(.C(s_axi_aclk),
.CE(\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[15]_i_1_n_0 ),
.D(\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[14]_i_1_n_0 ),
.Q(m_axi_wdata[14]),
.R(\USE_REGISTER.M_AXI_WLAST_q_reg_0 ));
FDRE \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[15]
(.C(s_axi_aclk),
.CE(\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[15]_i_1_n_0 ),
.D(\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[15]_i_2_n_0 ),
.Q(m_axi_wdata[15]),
.R(\USE_REGISTER.M_AXI_WLAST_q_reg_0 ));
FDRE \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[8]
(.C(s_axi_aclk),
.CE(\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[15]_i_1_n_0 ),
.D(\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[8]_i_1_n_0 ),
.Q(m_axi_wdata[8]),
.R(\USE_REGISTER.M_AXI_WLAST_q_reg_0 ));
FDRE \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[9]
(.C(s_axi_aclk),
.CE(\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[15]_i_1_n_0 ),
.D(\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[9]_i_1_n_0 ),
.Q(m_axi_wdata[9]),
.R(\USE_REGISTER.M_AXI_WLAST_q_reg_0 ));
LUT6 #(
.INIT(64'hFFFFFFFF44F4F4F4))
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I[1]_i_1
(.I0(\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_5_n_0 ),
.I1(wstrb_wrap_buffer_1),
.I2(m_axi_wstrb[1]),
.I3(m_axi_wready),
.I4(m_axi_wvalid),
.I5(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[25]_5 ),
.O(\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I[1]_i_1_n_0 ));
FDRE \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[1]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I[1]_i_1_n_0 ),
.Q(m_axi_wstrb[1]),
.R(\USE_REGISTER.M_AXI_WLAST_q_reg_0 ));
FDRE \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg[10]
(.C(s_axi_aclk),
.CE(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_7 ),
.D(s_axi_wdata[10]),
.Q(\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg [2]),
.R(SR));
FDRE \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg[11]
(.C(s_axi_aclk),
.CE(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_7 ),
.D(s_axi_wdata[11]),
.Q(\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg [3]),
.R(SR));
FDRE \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg[12]
(.C(s_axi_aclk),
.CE(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_7 ),
.D(s_axi_wdata[12]),
.Q(\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg [4]),
.R(SR));
FDRE \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg[13]
(.C(s_axi_aclk),
.CE(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_7 ),
.D(s_axi_wdata[13]),
.Q(\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg [5]),
.R(SR));
FDRE \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg[14]
(.C(s_axi_aclk),
.CE(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_7 ),
.D(s_axi_wdata[14]),
.Q(\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg [6]),
.R(SR));
FDRE \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg[15]
(.C(s_axi_aclk),
.CE(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_7 ),
.D(s_axi_wdata[15]),
.Q(\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg [7]),
.R(SR));
FDRE \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg[8]
(.C(s_axi_aclk),
.CE(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_7 ),
.D(s_axi_wdata[8]),
.Q(\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg [0]),
.R(SR));
FDRE \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg[9]
(.C(s_axi_aclk),
.CE(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_7 ),
.D(s_axi_wdata[9]),
.Q(\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg [1]),
.R(SR));
LUT2 #(
.INIT(4'hE))
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wstrb_wrap_buffer_q[1]_i_1
(.I0(wstrb_wrap_buffer_1),
.I1(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_7 ),
.O(\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wstrb_wrap_buffer_q[1]_i_1_n_0 ));
FDRE \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wstrb_wrap_buffer_q_reg[1]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wstrb_wrap_buffer_q[1]_i_1_n_0 ),
.Q(wstrb_wrap_buffer_1),
.R(SR));
LUT5 #(
.INIT(32'hF044F000))
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[16]_i_1
(.I0(\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_6_n_0 ),
.I1(wstrb_wrap_buffer_2),
.I2(s_axi_wdata[16]),
.I3(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28]_4 ),
.I4(\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg [0]),
.O(\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[16]_i_1_n_0 ));
LUT5 #(
.INIT(32'hF044F000))
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[17]_i_1
(.I0(\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_6_n_0 ),
.I1(wstrb_wrap_buffer_2),
.I2(s_axi_wdata[17]),
.I3(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28]_4 ),
.I4(\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg [1]),
.O(\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[17]_i_1_n_0 ));
LUT5 #(
.INIT(32'hF044F000))
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[18]_i_1
(.I0(\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_6_n_0 ),
.I1(wstrb_wrap_buffer_2),
.I2(s_axi_wdata[18]),
.I3(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28]_4 ),
.I4(\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg [2]),
.O(\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[18]_i_1_n_0 ));
LUT5 #(
.INIT(32'hF044F000))
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[19]_i_1
(.I0(\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_6_n_0 ),
.I1(wstrb_wrap_buffer_2),
.I2(s_axi_wdata[19]),
.I3(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28]_4 ),
.I4(\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg [3]),
.O(\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[19]_i_1_n_0 ));
LUT5 #(
.INIT(32'hF044F000))
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[20]_i_1
(.I0(\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_6_n_0 ),
.I1(wstrb_wrap_buffer_2),
.I2(s_axi_wdata[20]),
.I3(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28]_4 ),
.I4(\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg [4]),
.O(\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[20]_i_1_n_0 ));
LUT5 #(
.INIT(32'hF044F000))
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[21]_i_1
(.I0(\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_6_n_0 ),
.I1(wstrb_wrap_buffer_2),
.I2(s_axi_wdata[21]),
.I3(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28]_4 ),
.I4(\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg [5]),
.O(\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[21]_i_1_n_0 ));
LUT5 #(
.INIT(32'hF044F000))
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[22]_i_1
(.I0(\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_6_n_0 ),
.I1(wstrb_wrap_buffer_2),
.I2(s_axi_wdata[22]),
.I3(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28]_4 ),
.I4(\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg [6]),
.O(\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[22]_i_1_n_0 ));
LUT5 #(
.INIT(32'hEAFFEAEA))
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[23]_i_1
(.I0(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28]_4 ),
.I1(m_axi_wvalid),
.I2(m_axi_wready),
.I3(\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_5_n_0 ),
.I4(wstrb_wrap_buffer_2),
.O(\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[23]_i_1_n_0 ));
LUT5 #(
.INIT(32'hF044F000))
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[23]_i_2
(.I0(\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_6_n_0 ),
.I1(wstrb_wrap_buffer_2),
.I2(s_axi_wdata[23]),
.I3(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28]_4 ),
.I4(\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg [7]),
.O(\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[23]_i_2_n_0 ));
FDRE \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[16]
(.C(s_axi_aclk),
.CE(\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[23]_i_1_n_0 ),
.D(\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[16]_i_1_n_0 ),
.Q(m_axi_wdata[16]),
.R(\USE_REGISTER.M_AXI_WLAST_q_reg_0 ));
FDRE \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[17]
(.C(s_axi_aclk),
.CE(\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[23]_i_1_n_0 ),
.D(\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[17]_i_1_n_0 ),
.Q(m_axi_wdata[17]),
.R(\USE_REGISTER.M_AXI_WLAST_q_reg_0 ));
FDRE \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[18]
(.C(s_axi_aclk),
.CE(\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[23]_i_1_n_0 ),
.D(\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[18]_i_1_n_0 ),
.Q(m_axi_wdata[18]),
.R(\USE_REGISTER.M_AXI_WLAST_q_reg_0 ));
FDRE \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[19]
(.C(s_axi_aclk),
.CE(\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[23]_i_1_n_0 ),
.D(\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[19]_i_1_n_0 ),
.Q(m_axi_wdata[19]),
.R(\USE_REGISTER.M_AXI_WLAST_q_reg_0 ));
FDRE \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[20]
(.C(s_axi_aclk),
.CE(\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[23]_i_1_n_0 ),
.D(\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[20]_i_1_n_0 ),
.Q(m_axi_wdata[20]),
.R(\USE_REGISTER.M_AXI_WLAST_q_reg_0 ));
FDRE \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[21]
(.C(s_axi_aclk),
.CE(\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[23]_i_1_n_0 ),
.D(\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[21]_i_1_n_0 ),
.Q(m_axi_wdata[21]),
.R(\USE_REGISTER.M_AXI_WLAST_q_reg_0 ));
FDRE \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[22]
(.C(s_axi_aclk),
.CE(\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[23]_i_1_n_0 ),
.D(\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[22]_i_1_n_0 ),
.Q(m_axi_wdata[22]),
.R(\USE_REGISTER.M_AXI_WLAST_q_reg_0 ));
FDRE \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[23]
(.C(s_axi_aclk),
.CE(\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[23]_i_1_n_0 ),
.D(\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[23]_i_2_n_0 ),
.Q(m_axi_wdata[23]),
.R(\USE_REGISTER.M_AXI_WLAST_q_reg_0 ));
LUT6 #(
.INIT(64'hFFFFFFFF44F4F4F4))
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I[2]_i_1
(.I0(\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_5_n_0 ),
.I1(wstrb_wrap_buffer_2),
.I2(m_axi_wstrb[2]),
.I3(m_axi_wready),
.I4(m_axi_wvalid),
.I5(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[25]_4 ),
.O(\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I[2]_i_1_n_0 ));
FDRE \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[2]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I[2]_i_1_n_0 ),
.Q(m_axi_wstrb[2]),
.R(\USE_REGISTER.M_AXI_WLAST_q_reg_0 ));
FDRE \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg[16]
(.C(s_axi_aclk),
.CE(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_6 ),
.D(s_axi_wdata[16]),
.Q(\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg [0]),
.R(SR));
FDRE \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg[17]
(.C(s_axi_aclk),
.CE(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_6 ),
.D(s_axi_wdata[17]),
.Q(\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg [1]),
.R(SR));
FDRE \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg[18]
(.C(s_axi_aclk),
.CE(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_6 ),
.D(s_axi_wdata[18]),
.Q(\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg [2]),
.R(SR));
FDRE \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg[19]
(.C(s_axi_aclk),
.CE(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_6 ),
.D(s_axi_wdata[19]),
.Q(\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg [3]),
.R(SR));
FDRE \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg[20]
(.C(s_axi_aclk),
.CE(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_6 ),
.D(s_axi_wdata[20]),
.Q(\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg [4]),
.R(SR));
FDRE \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg[21]
(.C(s_axi_aclk),
.CE(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_6 ),
.D(s_axi_wdata[21]),
.Q(\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg [5]),
.R(SR));
FDRE \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg[22]
(.C(s_axi_aclk),
.CE(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_6 ),
.D(s_axi_wdata[22]),
.Q(\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg [6]),
.R(SR));
FDRE \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg[23]
(.C(s_axi_aclk),
.CE(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_6 ),
.D(s_axi_wdata[23]),
.Q(\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg [7]),
.R(SR));
LUT2 #(
.INIT(4'hE))
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wstrb_wrap_buffer_q[2]_i_1
(.I0(wstrb_wrap_buffer_2),
.I1(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_6 ),
.O(\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wstrb_wrap_buffer_q[2]_i_1_n_0 ));
FDRE \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wstrb_wrap_buffer_q_reg[2]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wstrb_wrap_buffer_q[2]_i_1_n_0 ),
.Q(wstrb_wrap_buffer_2),
.R(SR));
LUT5 #(
.INIT(32'hF044F000))
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[24]_i_1
(.I0(\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_6_n_0 ),
.I1(wstrb_wrap_buffer_3),
.I2(s_axi_wdata[24]),
.I3(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28]_3 ),
.I4(\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg [0]),
.O(\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[24]_i_1_n_0 ));
LUT5 #(
.INIT(32'hF044F000))
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[25]_i_1
(.I0(\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_6_n_0 ),
.I1(wstrb_wrap_buffer_3),
.I2(s_axi_wdata[25]),
.I3(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28]_3 ),
.I4(\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg [1]),
.O(\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[25]_i_1_n_0 ));
LUT5 #(
.INIT(32'hF044F000))
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[26]_i_1
(.I0(\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_6_n_0 ),
.I1(wstrb_wrap_buffer_3),
.I2(s_axi_wdata[26]),
.I3(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28]_3 ),
.I4(\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg [2]),
.O(\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[26]_i_1_n_0 ));
LUT5 #(
.INIT(32'hF044F000))
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[27]_i_1
(.I0(\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_6_n_0 ),
.I1(wstrb_wrap_buffer_3),
.I2(s_axi_wdata[27]),
.I3(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28]_3 ),
.I4(\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg [3]),
.O(\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[27]_i_1_n_0 ));
LUT5 #(
.INIT(32'hF044F000))
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[28]_i_1
(.I0(\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_6_n_0 ),
.I1(wstrb_wrap_buffer_3),
.I2(s_axi_wdata[28]),
.I3(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28]_3 ),
.I4(\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg [4]),
.O(\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[28]_i_1_n_0 ));
LUT5 #(
.INIT(32'hF044F000))
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[29]_i_1
(.I0(\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_6_n_0 ),
.I1(wstrb_wrap_buffer_3),
.I2(s_axi_wdata[29]),
.I3(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28]_3 ),
.I4(\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg [5]),
.O(\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[29]_i_1_n_0 ));
LUT5 #(
.INIT(32'hF044F000))
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[30]_i_1
(.I0(\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_6_n_0 ),
.I1(wstrb_wrap_buffer_3),
.I2(s_axi_wdata[30]),
.I3(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28]_3 ),
.I4(\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg [6]),
.O(\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[30]_i_1_n_0 ));
LUT5 #(
.INIT(32'hEAFFEAEA))
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[31]_i_1
(.I0(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28]_3 ),
.I1(m_axi_wvalid),
.I2(m_axi_wready),
.I3(\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_5_n_0 ),
.I4(wstrb_wrap_buffer_3),
.O(\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[31]_i_1_n_0 ));
LUT5 #(
.INIT(32'hF044F000))
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[31]_i_2
(.I0(\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_6_n_0 ),
.I1(wstrb_wrap_buffer_3),
.I2(s_axi_wdata[31]),
.I3(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28]_3 ),
.I4(\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg [7]),
.O(\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[31]_i_2_n_0 ));
FDRE \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[24]
(.C(s_axi_aclk),
.CE(\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[31]_i_1_n_0 ),
.D(\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[24]_i_1_n_0 ),
.Q(m_axi_wdata[24]),
.R(\USE_REGISTER.M_AXI_WLAST_q_reg_0 ));
FDRE \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[25]
(.C(s_axi_aclk),
.CE(\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[31]_i_1_n_0 ),
.D(\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[25]_i_1_n_0 ),
.Q(m_axi_wdata[25]),
.R(\USE_REGISTER.M_AXI_WLAST_q_reg_0 ));
FDRE \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[26]
(.C(s_axi_aclk),
.CE(\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[31]_i_1_n_0 ),
.D(\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[26]_i_1_n_0 ),
.Q(m_axi_wdata[26]),
.R(\USE_REGISTER.M_AXI_WLAST_q_reg_0 ));
FDRE \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[27]
(.C(s_axi_aclk),
.CE(\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[31]_i_1_n_0 ),
.D(\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[27]_i_1_n_0 ),
.Q(m_axi_wdata[27]),
.R(\USE_REGISTER.M_AXI_WLAST_q_reg_0 ));
FDRE \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[28]
(.C(s_axi_aclk),
.CE(\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[31]_i_1_n_0 ),
.D(\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[28]_i_1_n_0 ),
.Q(m_axi_wdata[28]),
.R(\USE_REGISTER.M_AXI_WLAST_q_reg_0 ));
FDRE \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[29]
(.C(s_axi_aclk),
.CE(\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[31]_i_1_n_0 ),
.D(\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[29]_i_1_n_0 ),
.Q(m_axi_wdata[29]),
.R(\USE_REGISTER.M_AXI_WLAST_q_reg_0 ));
FDRE \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[30]
(.C(s_axi_aclk),
.CE(\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[31]_i_1_n_0 ),
.D(\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[30]_i_1_n_0 ),
.Q(m_axi_wdata[30]),
.R(\USE_REGISTER.M_AXI_WLAST_q_reg_0 ));
FDRE \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[31]
(.C(s_axi_aclk),
.CE(\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[31]_i_1_n_0 ),
.D(\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[31]_i_2_n_0 ),
.Q(m_axi_wdata[31]),
.R(\USE_REGISTER.M_AXI_WLAST_q_reg_0 ));
LUT6 #(
.INIT(64'hFFFFFFFF44F4F4F4))
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I[3]_i_1
(.I0(\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_5_n_0 ),
.I1(wstrb_wrap_buffer_3),
.I2(m_axi_wstrb[3]),
.I3(m_axi_wready),
.I4(m_axi_wvalid),
.I5(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[25]_3 ),
.O(\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I[3]_i_1_n_0 ));
FDRE \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[3]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I[3]_i_1_n_0 ),
.Q(m_axi_wstrb[3]),
.R(\USE_REGISTER.M_AXI_WLAST_q_reg_0 ));
FDRE \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg[24]
(.C(s_axi_aclk),
.CE(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_5 ),
.D(s_axi_wdata[24]),
.Q(\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg [0]),
.R(SR));
FDRE \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg[25]
(.C(s_axi_aclk),
.CE(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_5 ),
.D(s_axi_wdata[25]),
.Q(\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg [1]),
.R(SR));
FDRE \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg[26]
(.C(s_axi_aclk),
.CE(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_5 ),
.D(s_axi_wdata[26]),
.Q(\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg [2]),
.R(SR));
FDRE \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg[27]
(.C(s_axi_aclk),
.CE(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_5 ),
.D(s_axi_wdata[27]),
.Q(\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg [3]),
.R(SR));
FDRE \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg[28]
(.C(s_axi_aclk),
.CE(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_5 ),
.D(s_axi_wdata[28]),
.Q(\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg [4]),
.R(SR));
FDRE \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg[29]
(.C(s_axi_aclk),
.CE(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_5 ),
.D(s_axi_wdata[29]),
.Q(\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg [5]),
.R(SR));
FDRE \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg[30]
(.C(s_axi_aclk),
.CE(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_5 ),
.D(s_axi_wdata[30]),
.Q(\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg [6]),
.R(SR));
FDRE \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg[31]
(.C(s_axi_aclk),
.CE(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_5 ),
.D(s_axi_wdata[31]),
.Q(\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg [7]),
.R(SR));
LUT2 #(
.INIT(4'hE))
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wstrb_wrap_buffer_q[3]_i_1
(.I0(wstrb_wrap_buffer_3),
.I1(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_5 ),
.O(\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wstrb_wrap_buffer_q[3]_i_1_n_0 ));
FDRE \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wstrb_wrap_buffer_q_reg[3]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wstrb_wrap_buffer_q[3]_i_1_n_0 ),
.Q(wstrb_wrap_buffer_3),
.R(SR));
LUT5 #(
.INIT(32'hF044F000))
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[32]_i_1
(.I0(\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_6_n_0 ),
.I1(wstrb_wrap_buffer_4),
.I2(s_axi_wdata[0]),
.I3(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28]_2 ),
.I4(\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg [0]),
.O(\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[32]_i_1_n_0 ));
LUT5 #(
.INIT(32'hF044F000))
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[33]_i_1
(.I0(\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_6_n_0 ),
.I1(wstrb_wrap_buffer_4),
.I2(s_axi_wdata[1]),
.I3(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28]_2 ),
.I4(\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg [1]),
.O(\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[33]_i_1_n_0 ));
LUT5 #(
.INIT(32'hF044F000))
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[34]_i_1
(.I0(\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_6_n_0 ),
.I1(wstrb_wrap_buffer_4),
.I2(s_axi_wdata[2]),
.I3(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28]_2 ),
.I4(\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg [2]),
.O(\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[34]_i_1_n_0 ));
LUT5 #(
.INIT(32'hF044F000))
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[35]_i_1
(.I0(\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_6_n_0 ),
.I1(wstrb_wrap_buffer_4),
.I2(s_axi_wdata[3]),
.I3(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28]_2 ),
.I4(\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg [3]),
.O(\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[35]_i_1_n_0 ));
LUT5 #(
.INIT(32'hF044F000))
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[36]_i_1
(.I0(\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_6_n_0 ),
.I1(wstrb_wrap_buffer_4),
.I2(s_axi_wdata[4]),
.I3(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28]_2 ),
.I4(\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg [4]),
.O(\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[36]_i_1_n_0 ));
LUT5 #(
.INIT(32'hF044F000))
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[37]_i_1
(.I0(\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_6_n_0 ),
.I1(wstrb_wrap_buffer_4),
.I2(s_axi_wdata[5]),
.I3(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28]_2 ),
.I4(\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg [5]),
.O(\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[37]_i_1_n_0 ));
LUT5 #(
.INIT(32'hF044F000))
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[38]_i_1
(.I0(\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_6_n_0 ),
.I1(wstrb_wrap_buffer_4),
.I2(s_axi_wdata[6]),
.I3(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28]_2 ),
.I4(\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg [6]),
.O(\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[38]_i_1_n_0 ));
LUT5 #(
.INIT(32'hEAFFEAEA))
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[39]_i_1
(.I0(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28]_2 ),
.I1(m_axi_wvalid),
.I2(m_axi_wready),
.I3(\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_5_n_0 ),
.I4(wstrb_wrap_buffer_4),
.O(\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[39]_i_1_n_0 ));
LUT5 #(
.INIT(32'hF044F000))
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[39]_i_2
(.I0(\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_6_n_0 ),
.I1(wstrb_wrap_buffer_4),
.I2(s_axi_wdata[7]),
.I3(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28]_2 ),
.I4(\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg [7]),
.O(\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[39]_i_2_n_0 ));
FDRE \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[32]
(.C(s_axi_aclk),
.CE(\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[39]_i_1_n_0 ),
.D(\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[32]_i_1_n_0 ),
.Q(m_axi_wdata[32]),
.R(\USE_REGISTER.M_AXI_WLAST_q_reg_0 ));
FDRE \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[33]
(.C(s_axi_aclk),
.CE(\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[39]_i_1_n_0 ),
.D(\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[33]_i_1_n_0 ),
.Q(m_axi_wdata[33]),
.R(\USE_REGISTER.M_AXI_WLAST_q_reg_0 ));
FDRE \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[34]
(.C(s_axi_aclk),
.CE(\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[39]_i_1_n_0 ),
.D(\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[34]_i_1_n_0 ),
.Q(m_axi_wdata[34]),
.R(\USE_REGISTER.M_AXI_WLAST_q_reg_0 ));
FDRE \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[35]
(.C(s_axi_aclk),
.CE(\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[39]_i_1_n_0 ),
.D(\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[35]_i_1_n_0 ),
.Q(m_axi_wdata[35]),
.R(\USE_REGISTER.M_AXI_WLAST_q_reg_0 ));
FDRE \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[36]
(.C(s_axi_aclk),
.CE(\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[39]_i_1_n_0 ),
.D(\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[36]_i_1_n_0 ),
.Q(m_axi_wdata[36]),
.R(\USE_REGISTER.M_AXI_WLAST_q_reg_0 ));
FDRE \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[37]
(.C(s_axi_aclk),
.CE(\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[39]_i_1_n_0 ),
.D(\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[37]_i_1_n_0 ),
.Q(m_axi_wdata[37]),
.R(\USE_REGISTER.M_AXI_WLAST_q_reg_0 ));
FDRE \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[38]
(.C(s_axi_aclk),
.CE(\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[39]_i_1_n_0 ),
.D(\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[38]_i_1_n_0 ),
.Q(m_axi_wdata[38]),
.R(\USE_REGISTER.M_AXI_WLAST_q_reg_0 ));
FDRE \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[39]
(.C(s_axi_aclk),
.CE(\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[39]_i_1_n_0 ),
.D(\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[39]_i_2_n_0 ),
.Q(m_axi_wdata[39]),
.R(\USE_REGISTER.M_AXI_WLAST_q_reg_0 ));
LUT6 #(
.INIT(64'hFFFFFFFF44F4F4F4))
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I[4]_i_1
(.I0(\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_5_n_0 ),
.I1(wstrb_wrap_buffer_4),
.I2(m_axi_wstrb[4]),
.I3(m_axi_wready),
.I4(m_axi_wvalid),
.I5(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[25]_2 ),
.O(\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I[4]_i_1_n_0 ));
FDRE \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[4]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I[4]_i_1_n_0 ),
.Q(m_axi_wstrb[4]),
.R(\USE_REGISTER.M_AXI_WLAST_q_reg_0 ));
FDRE \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg[32]
(.C(s_axi_aclk),
.CE(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_4 ),
.D(s_axi_wdata[0]),
.Q(\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg [0]),
.R(SR));
FDRE \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg[33]
(.C(s_axi_aclk),
.CE(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_4 ),
.D(s_axi_wdata[1]),
.Q(\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg [1]),
.R(SR));
FDRE \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg[34]
(.C(s_axi_aclk),
.CE(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_4 ),
.D(s_axi_wdata[2]),
.Q(\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg [2]),
.R(SR));
FDRE \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg[35]
(.C(s_axi_aclk),
.CE(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_4 ),
.D(s_axi_wdata[3]),
.Q(\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg [3]),
.R(SR));
FDRE \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg[36]
(.C(s_axi_aclk),
.CE(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_4 ),
.D(s_axi_wdata[4]),
.Q(\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg [4]),
.R(SR));
FDRE \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg[37]
(.C(s_axi_aclk),
.CE(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_4 ),
.D(s_axi_wdata[5]),
.Q(\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg [5]),
.R(SR));
FDRE \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg[38]
(.C(s_axi_aclk),
.CE(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_4 ),
.D(s_axi_wdata[6]),
.Q(\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg [6]),
.R(SR));
FDRE \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg[39]
(.C(s_axi_aclk),
.CE(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_4 ),
.D(s_axi_wdata[7]),
.Q(\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg [7]),
.R(SR));
LUT2 #(
.INIT(4'hE))
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wstrb_wrap_buffer_q[4]_i_1
(.I0(wstrb_wrap_buffer_4),
.I1(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_4 ),
.O(\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wstrb_wrap_buffer_q[4]_i_1_n_0 ));
FDRE \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wstrb_wrap_buffer_q_reg[4]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wstrb_wrap_buffer_q[4]_i_1_n_0 ),
.Q(wstrb_wrap_buffer_4),
.R(SR));
LUT5 #(
.INIT(32'hF044F000))
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[40]_i_1
(.I0(\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_6_n_0 ),
.I1(wstrb_wrap_buffer_5),
.I2(s_axi_wdata[8]),
.I3(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28]_1 ),
.I4(\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg [0]),
.O(\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[40]_i_1_n_0 ));
LUT5 #(
.INIT(32'hF044F000))
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[41]_i_1
(.I0(\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_6_n_0 ),
.I1(wstrb_wrap_buffer_5),
.I2(s_axi_wdata[9]),
.I3(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28]_1 ),
.I4(\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg [1]),
.O(\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[41]_i_1_n_0 ));
LUT5 #(
.INIT(32'hF044F000))
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[42]_i_1
(.I0(\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_6_n_0 ),
.I1(wstrb_wrap_buffer_5),
.I2(s_axi_wdata[10]),
.I3(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28]_1 ),
.I4(\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg [2]),
.O(\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[42]_i_1_n_0 ));
LUT5 #(
.INIT(32'hF044F000))
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[43]_i_1
(.I0(\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_6_n_0 ),
.I1(wstrb_wrap_buffer_5),
.I2(s_axi_wdata[11]),
.I3(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28]_1 ),
.I4(\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg [3]),
.O(\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[43]_i_1_n_0 ));
LUT5 #(
.INIT(32'hF044F000))
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[44]_i_1
(.I0(\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_6_n_0 ),
.I1(wstrb_wrap_buffer_5),
.I2(s_axi_wdata[12]),
.I3(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28]_1 ),
.I4(\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg [4]),
.O(\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[44]_i_1_n_0 ));
LUT5 #(
.INIT(32'hF044F000))
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[45]_i_1
(.I0(\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_6_n_0 ),
.I1(wstrb_wrap_buffer_5),
.I2(s_axi_wdata[13]),
.I3(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28]_1 ),
.I4(\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg [5]),
.O(\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[45]_i_1_n_0 ));
LUT5 #(
.INIT(32'hF044F000))
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[46]_i_1
(.I0(\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_6_n_0 ),
.I1(wstrb_wrap_buffer_5),
.I2(s_axi_wdata[14]),
.I3(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28]_1 ),
.I4(\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg [6]),
.O(\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[46]_i_1_n_0 ));
LUT5 #(
.INIT(32'hEAFFEAEA))
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[47]_i_1
(.I0(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28]_1 ),
.I1(m_axi_wvalid),
.I2(m_axi_wready),
.I3(\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_5_n_0 ),
.I4(wstrb_wrap_buffer_5),
.O(\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[47]_i_1_n_0 ));
LUT5 #(
.INIT(32'hF044F000))
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[47]_i_2
(.I0(\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_6_n_0 ),
.I1(wstrb_wrap_buffer_5),
.I2(s_axi_wdata[15]),
.I3(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28]_1 ),
.I4(\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg [7]),
.O(\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[47]_i_2_n_0 ));
FDRE \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[40]
(.C(s_axi_aclk),
.CE(\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[47]_i_1_n_0 ),
.D(\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[40]_i_1_n_0 ),
.Q(m_axi_wdata[40]),
.R(\USE_REGISTER.M_AXI_WLAST_q_reg_0 ));
FDRE \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[41]
(.C(s_axi_aclk),
.CE(\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[47]_i_1_n_0 ),
.D(\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[41]_i_1_n_0 ),
.Q(m_axi_wdata[41]),
.R(\USE_REGISTER.M_AXI_WLAST_q_reg_0 ));
FDRE \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[42]
(.C(s_axi_aclk),
.CE(\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[47]_i_1_n_0 ),
.D(\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[42]_i_1_n_0 ),
.Q(m_axi_wdata[42]),
.R(\USE_REGISTER.M_AXI_WLAST_q_reg_0 ));
FDRE \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[43]
(.C(s_axi_aclk),
.CE(\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[47]_i_1_n_0 ),
.D(\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[43]_i_1_n_0 ),
.Q(m_axi_wdata[43]),
.R(\USE_REGISTER.M_AXI_WLAST_q_reg_0 ));
FDRE \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[44]
(.C(s_axi_aclk),
.CE(\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[47]_i_1_n_0 ),
.D(\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[44]_i_1_n_0 ),
.Q(m_axi_wdata[44]),
.R(\USE_REGISTER.M_AXI_WLAST_q_reg_0 ));
FDRE \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[45]
(.C(s_axi_aclk),
.CE(\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[47]_i_1_n_0 ),
.D(\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[45]_i_1_n_0 ),
.Q(m_axi_wdata[45]),
.R(\USE_REGISTER.M_AXI_WLAST_q_reg_0 ));
FDRE \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[46]
(.C(s_axi_aclk),
.CE(\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[47]_i_1_n_0 ),
.D(\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[46]_i_1_n_0 ),
.Q(m_axi_wdata[46]),
.R(\USE_REGISTER.M_AXI_WLAST_q_reg_0 ));
FDRE \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[47]
(.C(s_axi_aclk),
.CE(\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[47]_i_1_n_0 ),
.D(\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[47]_i_2_n_0 ),
.Q(m_axi_wdata[47]),
.R(\USE_REGISTER.M_AXI_WLAST_q_reg_0 ));
LUT6 #(
.INIT(64'hFFFFFFFF44F4F4F4))
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I[5]_i_1
(.I0(\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_5_n_0 ),
.I1(wstrb_wrap_buffer_5),
.I2(m_axi_wstrb[5]),
.I3(m_axi_wready),
.I4(m_axi_wvalid),
.I5(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[25]_1 ),
.O(\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I[5]_i_1_n_0 ));
FDRE \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[5]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I[5]_i_1_n_0 ),
.Q(m_axi_wstrb[5]),
.R(\USE_REGISTER.M_AXI_WLAST_q_reg_0 ));
FDRE \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg[40]
(.C(s_axi_aclk),
.CE(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_3 ),
.D(s_axi_wdata[8]),
.Q(\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg [0]),
.R(SR));
FDRE \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg[41]
(.C(s_axi_aclk),
.CE(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_3 ),
.D(s_axi_wdata[9]),
.Q(\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg [1]),
.R(SR));
FDRE \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg[42]
(.C(s_axi_aclk),
.CE(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_3 ),
.D(s_axi_wdata[10]),
.Q(\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg [2]),
.R(SR));
FDRE \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg[43]
(.C(s_axi_aclk),
.CE(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_3 ),
.D(s_axi_wdata[11]),
.Q(\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg [3]),
.R(SR));
FDRE \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg[44]
(.C(s_axi_aclk),
.CE(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_3 ),
.D(s_axi_wdata[12]),
.Q(\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg [4]),
.R(SR));
FDRE \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg[45]
(.C(s_axi_aclk),
.CE(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_3 ),
.D(s_axi_wdata[13]),
.Q(\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg [5]),
.R(SR));
FDRE \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg[46]
(.C(s_axi_aclk),
.CE(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_3 ),
.D(s_axi_wdata[14]),
.Q(\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg [6]),
.R(SR));
FDRE \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg[47]
(.C(s_axi_aclk),
.CE(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_3 ),
.D(s_axi_wdata[15]),
.Q(\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg [7]),
.R(SR));
LUT2 #(
.INIT(4'hE))
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wstrb_wrap_buffer_q[5]_i_1
(.I0(wstrb_wrap_buffer_5),
.I1(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_3 ),
.O(\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wstrb_wrap_buffer_q[5]_i_1_n_0 ));
FDRE \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wstrb_wrap_buffer_q_reg[5]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wstrb_wrap_buffer_q[5]_i_1_n_0 ),
.Q(wstrb_wrap_buffer_5),
.R(SR));
LUT5 #(
.INIT(32'hF044F000))
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[48]_i_1
(.I0(\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_6_n_0 ),
.I1(wstrb_wrap_buffer_6),
.I2(s_axi_wdata[16]),
.I3(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28]_0 ),
.I4(\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg [0]),
.O(\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[48]_i_1_n_0 ));
LUT5 #(
.INIT(32'hF044F000))
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[49]_i_1
(.I0(\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_6_n_0 ),
.I1(wstrb_wrap_buffer_6),
.I2(s_axi_wdata[17]),
.I3(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28]_0 ),
.I4(\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg [1]),
.O(\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[49]_i_1_n_0 ));
LUT5 #(
.INIT(32'hF044F000))
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[50]_i_1
(.I0(\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_6_n_0 ),
.I1(wstrb_wrap_buffer_6),
.I2(s_axi_wdata[18]),
.I3(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28]_0 ),
.I4(\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg [2]),
.O(\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[50]_i_1_n_0 ));
LUT5 #(
.INIT(32'hF044F000))
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[51]_i_1
(.I0(\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_6_n_0 ),
.I1(wstrb_wrap_buffer_6),
.I2(s_axi_wdata[19]),
.I3(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28]_0 ),
.I4(\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg [3]),
.O(\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[51]_i_1_n_0 ));
LUT5 #(
.INIT(32'hF044F000))
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[52]_i_1
(.I0(\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_6_n_0 ),
.I1(wstrb_wrap_buffer_6),
.I2(s_axi_wdata[20]),
.I3(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28]_0 ),
.I4(\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg [4]),
.O(\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[52]_i_1_n_0 ));
LUT5 #(
.INIT(32'hF044F000))
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[53]_i_1
(.I0(\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_6_n_0 ),
.I1(wstrb_wrap_buffer_6),
.I2(s_axi_wdata[21]),
.I3(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28]_0 ),
.I4(\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg [5]),
.O(\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[53]_i_1_n_0 ));
LUT5 #(
.INIT(32'hF044F000))
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[54]_i_1
(.I0(\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_6_n_0 ),
.I1(wstrb_wrap_buffer_6),
.I2(s_axi_wdata[22]),
.I3(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28]_0 ),
.I4(\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg [6]),
.O(\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[54]_i_1_n_0 ));
LUT5 #(
.INIT(32'hEAFFEAEA))
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[55]_i_1
(.I0(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28]_0 ),
.I1(m_axi_wvalid),
.I2(m_axi_wready),
.I3(\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_5_n_0 ),
.I4(wstrb_wrap_buffer_6),
.O(\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[55]_i_1_n_0 ));
LUT5 #(
.INIT(32'hF044F000))
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[55]_i_2
(.I0(\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_6_n_0 ),
.I1(wstrb_wrap_buffer_6),
.I2(s_axi_wdata[23]),
.I3(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28]_0 ),
.I4(\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg [7]),
.O(\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[55]_i_2_n_0 ));
FDRE \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[48]
(.C(s_axi_aclk),
.CE(\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[55]_i_1_n_0 ),
.D(\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[48]_i_1_n_0 ),
.Q(m_axi_wdata[48]),
.R(\USE_REGISTER.M_AXI_WLAST_q_reg_0 ));
FDRE \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[49]
(.C(s_axi_aclk),
.CE(\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[55]_i_1_n_0 ),
.D(\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[49]_i_1_n_0 ),
.Q(m_axi_wdata[49]),
.R(\USE_REGISTER.M_AXI_WLAST_q_reg_0 ));
FDRE \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[50]
(.C(s_axi_aclk),
.CE(\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[55]_i_1_n_0 ),
.D(\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[50]_i_1_n_0 ),
.Q(m_axi_wdata[50]),
.R(\USE_REGISTER.M_AXI_WLAST_q_reg_0 ));
FDRE \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[51]
(.C(s_axi_aclk),
.CE(\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[55]_i_1_n_0 ),
.D(\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[51]_i_1_n_0 ),
.Q(m_axi_wdata[51]),
.R(\USE_REGISTER.M_AXI_WLAST_q_reg_0 ));
FDRE \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[52]
(.C(s_axi_aclk),
.CE(\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[55]_i_1_n_0 ),
.D(\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[52]_i_1_n_0 ),
.Q(m_axi_wdata[52]),
.R(\USE_REGISTER.M_AXI_WLAST_q_reg_0 ));
FDRE \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[53]
(.C(s_axi_aclk),
.CE(\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[55]_i_1_n_0 ),
.D(\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[53]_i_1_n_0 ),
.Q(m_axi_wdata[53]),
.R(\USE_REGISTER.M_AXI_WLAST_q_reg_0 ));
FDRE \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[54]
(.C(s_axi_aclk),
.CE(\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[55]_i_1_n_0 ),
.D(\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[54]_i_1_n_0 ),
.Q(m_axi_wdata[54]),
.R(\USE_REGISTER.M_AXI_WLAST_q_reg_0 ));
FDRE \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[55]
(.C(s_axi_aclk),
.CE(\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[55]_i_1_n_0 ),
.D(\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[55]_i_2_n_0 ),
.Q(m_axi_wdata[55]),
.R(\USE_REGISTER.M_AXI_WLAST_q_reg_0 ));
LUT6 #(
.INIT(64'hFFFFFFFF44F4F4F4))
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I[6]_i_1
(.I0(\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_5_n_0 ),
.I1(wstrb_wrap_buffer_6),
.I2(m_axi_wstrb[6]),
.I3(m_axi_wready),
.I4(m_axi_wvalid),
.I5(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[25]_0 ),
.O(\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I[6]_i_1_n_0 ));
FDRE \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[6]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I[6]_i_1_n_0 ),
.Q(m_axi_wstrb[6]),
.R(\USE_REGISTER.M_AXI_WLAST_q_reg_0 ));
FDRE \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg[48]
(.C(s_axi_aclk),
.CE(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_2 ),
.D(s_axi_wdata[16]),
.Q(\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg [0]),
.R(SR));
FDRE \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg[49]
(.C(s_axi_aclk),
.CE(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_2 ),
.D(s_axi_wdata[17]),
.Q(\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg [1]),
.R(SR));
FDRE \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg[50]
(.C(s_axi_aclk),
.CE(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_2 ),
.D(s_axi_wdata[18]),
.Q(\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg [2]),
.R(SR));
FDRE \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg[51]
(.C(s_axi_aclk),
.CE(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_2 ),
.D(s_axi_wdata[19]),
.Q(\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg [3]),
.R(SR));
FDRE \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg[52]
(.C(s_axi_aclk),
.CE(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_2 ),
.D(s_axi_wdata[20]),
.Q(\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg [4]),
.R(SR));
FDRE \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg[53]
(.C(s_axi_aclk),
.CE(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_2 ),
.D(s_axi_wdata[21]),
.Q(\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg [5]),
.R(SR));
FDRE \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg[54]
(.C(s_axi_aclk),
.CE(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_2 ),
.D(s_axi_wdata[22]),
.Q(\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg [6]),
.R(SR));
FDRE \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg[55]
(.C(s_axi_aclk),
.CE(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_2 ),
.D(s_axi_wdata[23]),
.Q(\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg [7]),
.R(SR));
LUT2 #(
.INIT(4'hE))
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wstrb_wrap_buffer_q[6]_i_1
(.I0(wstrb_wrap_buffer_6),
.I1(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_2 ),
.O(\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wstrb_wrap_buffer_q[6]_i_1_n_0 ));
FDRE \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wstrb_wrap_buffer_q_reg[6]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wstrb_wrap_buffer_q[6]_i_1_n_0 ),
.Q(wstrb_wrap_buffer_6),
.R(SR));
LUT5 #(
.INIT(32'hF044F000))
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[56]_i_1
(.I0(\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_6_n_0 ),
.I1(wstrb_wrap_buffer_7),
.I2(s_axi_wdata[24]),
.I3(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28] ),
.I4(\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg [0]),
.O(\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[56]_i_1_n_0 ));
LUT5 #(
.INIT(32'hF044F000))
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[57]_i_1
(.I0(\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_6_n_0 ),
.I1(wstrb_wrap_buffer_7),
.I2(s_axi_wdata[25]),
.I3(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28] ),
.I4(\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg [1]),
.O(\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[57]_i_1_n_0 ));
LUT5 #(
.INIT(32'hF044F000))
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[58]_i_1
(.I0(\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_6_n_0 ),
.I1(wstrb_wrap_buffer_7),
.I2(s_axi_wdata[26]),
.I3(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28] ),
.I4(\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg [2]),
.O(\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[58]_i_1_n_0 ));
LUT5 #(
.INIT(32'hF044F000))
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[59]_i_1
(.I0(\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_6_n_0 ),
.I1(wstrb_wrap_buffer_7),
.I2(s_axi_wdata[27]),
.I3(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28] ),
.I4(\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg [3]),
.O(\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[59]_i_1_n_0 ));
LUT5 #(
.INIT(32'hF044F000))
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[60]_i_1
(.I0(\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_6_n_0 ),
.I1(wstrb_wrap_buffer_7),
.I2(s_axi_wdata[28]),
.I3(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28] ),
.I4(\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg [4]),
.O(\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[60]_i_1_n_0 ));
LUT5 #(
.INIT(32'hF044F000))
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[61]_i_1
(.I0(\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_6_n_0 ),
.I1(wstrb_wrap_buffer_7),
.I2(s_axi_wdata[29]),
.I3(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28] ),
.I4(\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg [5]),
.O(\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[61]_i_1_n_0 ));
LUT5 #(
.INIT(32'hF044F000))
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[62]_i_1
(.I0(\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_6_n_0 ),
.I1(wstrb_wrap_buffer_7),
.I2(s_axi_wdata[30]),
.I3(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28] ),
.I4(\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg [6]),
.O(\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[62]_i_1_n_0 ));
LUT1 #(
.INIT(2'h1))
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_1
(.I0(out),
.O(\USE_REGISTER.M_AXI_WLAST_q_reg_0 ));
(* SOFT_HLUTNM = "soft_lutpair49" *)
LUT3 #(
.INIT(8'hB8))
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_10
(.I0(Q[6]),
.I1(first_mi_word_q),
.I2(\USE_RTL_LENGTH.length_counter_q_reg [6]),
.O(\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_10_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFFFFFFEFEA))
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_11
(.I0(\USE_RTL_LENGTH.first_mi_word_q_i_7_n_0 ),
.I1(Q[2]),
.I2(first_mi_word_q),
.I3(\USE_RTL_LENGTH.length_counter_q_reg [2]),
.I4(\USE_RTL_LENGTH.first_mi_word_q_i_6_n_0 ),
.I5(\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_14_n_0 ),
.O(\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_11_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFFFFFFDFD5))
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_13
(.I0(Q[13]),
.I1(Q[7]),
.I2(first_mi_word_q),
.I3(\USE_RTL_LENGTH.length_counter_q_reg [7]),
.I4(\USE_RTL_LENGTH.first_mi_word_q_i_6_n_0 ),
.I5(\USE_RTL_LENGTH.first_mi_word_q_i_7_n_0 ),
.O(\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_13_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair44" *)
LUT3 #(
.INIT(8'hB8))
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_14
(.I0(Q[5]),
.I1(first_mi_word_q),
.I2(\USE_RTL_LENGTH.length_counter_q_reg [5]),
.O(\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_14_n_0 ));
LUT5 #(
.INIT(32'hEAFFEAEA))
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_2
(.I0(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28] ),
.I1(m_axi_wvalid),
.I2(m_axi_wready),
.I3(\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_5_n_0 ),
.I4(wstrb_wrap_buffer_7),
.O(\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_2_n_0 ));
LUT5 #(
.INIT(32'hF044F000))
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_3
(.I0(\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_6_n_0 ),
.I1(wstrb_wrap_buffer_7),
.I2(s_axi_wdata[31]),
.I3(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28] ),
.I4(\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg [7]),
.O(\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_3_n_0 ));
LUT3 #(
.INIT(8'hDF))
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_5
(.I0(wrap_buffer_available),
.I1(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_9 ),
.I2(\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_8_n_0 ),
.O(\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_5_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFFFFFFFFFB))
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_6
(.I0(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_9 ),
.I1(wrap_buffer_available),
.I2(\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[0]_0 ),
.I3(\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_10_n_0 ),
.I4(\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_11_n_0 ),
.I5(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28]_7 ),
.O(\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_6_n_0 ));
LUT6 #(
.INIT(64'h0000000000000004))
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_8
(.I0(\USE_RTL_LENGTH.first_mi_word_q_reg_0 ),
.I1(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[17] ),
.I2(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[19] ),
.I3(\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_13_n_0 ),
.I4(\USE_RTL_LENGTH.length_counter_q_reg[7]_0 ),
.I5(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[18] ),
.O(\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_8_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair47" *)
LUT3 #(
.INIT(8'hB8))
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_9
(.I0(Q[7]),
.I1(first_mi_word_q),
.I2(\USE_RTL_LENGTH.length_counter_q_reg [7]),
.O(\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[0]_0 ));
FDRE \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[56]
(.C(s_axi_aclk),
.CE(\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_2_n_0 ),
.D(\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[56]_i_1_n_0 ),
.Q(m_axi_wdata[56]),
.R(\USE_REGISTER.M_AXI_WLAST_q_reg_0 ));
FDRE \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[57]
(.C(s_axi_aclk),
.CE(\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_2_n_0 ),
.D(\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[57]_i_1_n_0 ),
.Q(m_axi_wdata[57]),
.R(\USE_REGISTER.M_AXI_WLAST_q_reg_0 ));
FDRE \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[58]
(.C(s_axi_aclk),
.CE(\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_2_n_0 ),
.D(\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[58]_i_1_n_0 ),
.Q(m_axi_wdata[58]),
.R(\USE_REGISTER.M_AXI_WLAST_q_reg_0 ));
FDRE \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[59]
(.C(s_axi_aclk),
.CE(\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_2_n_0 ),
.D(\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[59]_i_1_n_0 ),
.Q(m_axi_wdata[59]),
.R(\USE_REGISTER.M_AXI_WLAST_q_reg_0 ));
FDRE \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[60]
(.C(s_axi_aclk),
.CE(\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_2_n_0 ),
.D(\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[60]_i_1_n_0 ),
.Q(m_axi_wdata[60]),
.R(\USE_REGISTER.M_AXI_WLAST_q_reg_0 ));
FDRE \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[61]
(.C(s_axi_aclk),
.CE(\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_2_n_0 ),
.D(\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[61]_i_1_n_0 ),
.Q(m_axi_wdata[61]),
.R(\USE_REGISTER.M_AXI_WLAST_q_reg_0 ));
FDRE \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[62]
(.C(s_axi_aclk),
.CE(\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_2_n_0 ),
.D(\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[62]_i_1_n_0 ),
.Q(m_axi_wdata[62]),
.R(\USE_REGISTER.M_AXI_WLAST_q_reg_0 ));
FDRE \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[63]
(.C(s_axi_aclk),
.CE(\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_2_n_0 ),
.D(\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_3_n_0 ),
.Q(m_axi_wdata[63]),
.R(\USE_REGISTER.M_AXI_WLAST_q_reg_0 ));
LUT6 #(
.INIT(64'hFFFFFFFF44F4F4F4))
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I[7]_i_1
(.I0(\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_5_n_0 ),
.I1(wstrb_wrap_buffer_7),
.I2(m_axi_wstrb[7]),
.I3(m_axi_wready),
.I4(m_axi_wvalid),
.I5(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[25] ),
.O(\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I[7]_i_1_n_0 ));
FDRE \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[7]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I[7]_i_1_n_0 ),
.Q(m_axi_wstrb[7]),
.R(\USE_REGISTER.M_AXI_WLAST_q_reg_0 ));
FDRE \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg[56]
(.C(s_axi_aclk),
.CE(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_1 ),
.D(s_axi_wdata[24]),
.Q(\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg [0]),
.R(SR));
FDRE \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg[57]
(.C(s_axi_aclk),
.CE(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_1 ),
.D(s_axi_wdata[25]),
.Q(\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg [1]),
.R(SR));
FDRE \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg[58]
(.C(s_axi_aclk),
.CE(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_1 ),
.D(s_axi_wdata[26]),
.Q(\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg [2]),
.R(SR));
FDRE \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg[59]
(.C(s_axi_aclk),
.CE(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_1 ),
.D(s_axi_wdata[27]),
.Q(\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg [3]),
.R(SR));
FDRE \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg[60]
(.C(s_axi_aclk),
.CE(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_1 ),
.D(s_axi_wdata[28]),
.Q(\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg [4]),
.R(SR));
FDRE \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg[61]
(.C(s_axi_aclk),
.CE(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_1 ),
.D(s_axi_wdata[29]),
.Q(\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg [5]),
.R(SR));
FDRE \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg[62]
(.C(s_axi_aclk),
.CE(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_1 ),
.D(s_axi_wdata[30]),
.Q(\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg [6]),
.R(SR));
FDRE \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg[63]
(.C(s_axi_aclk),
.CE(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_1 ),
.D(s_axi_wdata[31]),
.Q(\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg [7]),
.R(SR));
LUT2 #(
.INIT(4'hE))
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wstrb_wrap_buffer_q[7]_i_1
(.I0(wstrb_wrap_buffer_7),
.I1(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg_1 ),
.O(\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wstrb_wrap_buffer_q[7]_i_1_n_0 ));
FDRE \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wstrb_wrap_buffer_q_reg[7]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wstrb_wrap_buffer_q[7]_i_1_n_0 ),
.Q(wstrb_wrap_buffer_7),
.R(SR));
FDRE wrap_buffer_available_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg ),
.Q(wrap_buffer_available),
.R(\USE_REGISTER.M_AXI_WLAST_q_reg_0 ));
endmodule
|
module system_auto_us_0_axi_register_slice_v2_1_11_axi_register_slice
(m_axi_rready,
mr_rvalid,
Q,
s_axi_aclk,
m_axi_rlast,
m_axi_rresp,
m_axi_rdata,
m_axi_rvalid,
rd_cmd_valid,
use_wrap_buffer_reg,
\aresetn_d_reg[1] ,
\aresetn_d_reg[0] ,
E);
output m_axi_rready;
output mr_rvalid;
output [66:0]Q;
input s_axi_aclk;
input m_axi_rlast;
input [1:0]m_axi_rresp;
input [63:0]m_axi_rdata;
input m_axi_rvalid;
input rd_cmd_valid;
input use_wrap_buffer_reg;
input \aresetn_d_reg[1] ;
input \aresetn_d_reg[0] ;
input [0:0]E;
wire [0:0]E;
wire [66:0]Q;
wire \aresetn_d_reg[0] ;
wire \aresetn_d_reg[1] ;
wire [63:0]m_axi_rdata;
wire m_axi_rlast;
wire m_axi_rready;
wire [1:0]m_axi_rresp;
wire m_axi_rvalid;
wire mr_rvalid;
wire rd_cmd_valid;
wire s_axi_aclk;
wire use_wrap_buffer_reg;
system_auto_us_0_axi_register_slice_v2_1_11_axic_register_slice__parameterized2 r_pipe
(.E(E),
.Q(Q),
.\aresetn_d_reg[0] (\aresetn_d_reg[0] ),
.\aresetn_d_reg[1] (\aresetn_d_reg[1] ),
.m_axi_rdata(m_axi_rdata),
.m_axi_rlast(m_axi_rlast),
.m_axi_rready(m_axi_rready),
.m_axi_rresp(m_axi_rresp),
.m_axi_rvalid(m_axi_rvalid),
.mr_rvalid(mr_rvalid),
.rd_cmd_valid(rd_cmd_valid),
.s_axi_aclk(s_axi_aclk),
.use_wrap_buffer_reg(use_wrap_buffer_reg));
endmodule
|
module system_auto_us_0_axi_register_slice_v2_1_11_axi_register_slice__parameterized0
(s_ready_i_reg,
\aresetn_d_reg[1] ,
sr_awvalid,
sr_arvalid,
Q,
s_axi_arready,
s_axi_awready,
\m_axi_awregion[3] ,
m_axi_awburst,
in,
m_axi_awaddr,
m_axi_awsize,
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29] ,
m_axi_arsize,
m_axi_arburst,
m_axi_araddr,
s_axi_aresetn,
s_axi_aclk,
cmd_push_block_reg,
s_axi_arvalid,
cmd_push_block_reg_0,
s_axi_awvalid,
D,
\s_axi_arregion[3] );
output s_ready_i_reg;
output \aresetn_d_reg[1] ;
output sr_awvalid;
output sr_arvalid;
output [44:0]Q;
output s_axi_arready;
output s_axi_awready;
output [41:0]\m_axi_awregion[3] ;
output [1:0]m_axi_awburst;
output [27:0]in;
output [5:0]m_axi_awaddr;
output [2:0]m_axi_awsize;
output [27:0]\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29] ;
output [2:0]m_axi_arsize;
output [1:0]m_axi_arburst;
output [2:0]m_axi_araddr;
input s_axi_aresetn;
input s_axi_aclk;
input cmd_push_block_reg;
input s_axi_arvalid;
input cmd_push_block_reg_0;
input s_axi_awvalid;
input [60:0]D;
input [60:0]\s_axi_arregion[3] ;
wire [60:0]D;
wire [44:0]Q;
wire [27:0]\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29] ;
wire \aresetn_d_reg[1] ;
wire cmd_push_block_reg;
wire cmd_push_block_reg_0;
wire [27:0]in;
wire [2:0]m_axi_araddr;
wire [1:0]m_axi_arburst;
wire [2:0]m_axi_arsize;
wire [5:0]m_axi_awaddr;
wire [1:0]m_axi_awburst;
wire [41:0]\m_axi_awregion[3] ;
wire [2:0]m_axi_awsize;
wire s_axi_aclk;
wire s_axi_aresetn;
wire s_axi_arready;
wire [60:0]\s_axi_arregion[3] ;
wire s_axi_arvalid;
wire s_axi_awready;
wire s_axi_awvalid;
wire s_ready_i_reg;
wire sr_arvalid;
wire sr_awvalid;
system_auto_us_0_axi_register_slice_v2_1_11_axic_register_slice ar_pipe
(.Q(Q),
.\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29] (\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29] ),
.\aresetn_d_reg[0] (\aresetn_d_reg[1] ),
.cmd_push_block_reg(cmd_push_block_reg),
.m_axi_araddr(m_axi_araddr),
.m_axi_arburst(m_axi_arburst),
.m_axi_arsize(m_axi_arsize),
.s_axi_aclk(s_axi_aclk),
.s_axi_aresetn(s_axi_aresetn),
.s_axi_arready(s_axi_arready),
.\s_axi_arregion[3] (\s_axi_arregion[3] ),
.s_axi_arvalid(s_axi_arvalid),
.s_ready_i_reg_0(s_ready_i_reg),
.sr_arvalid(sr_arvalid));
system_auto_us_0_axi_register_slice_v2_1_11_axic_register_slice_0 aw_pipe
(.D(D),
.\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[26] (in[24]),
.\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[27] (in[25]),
.\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28] (in[26]),
.\aresetn_d_reg[1] (\aresetn_d_reg[1] ),
.\aresetn_d_reg[1]_0 (s_ready_i_reg),
.cmd_push_block_reg(cmd_push_block_reg_0),
.in({in[27],in[23:0]}),
.m_axi_awaddr(m_axi_awaddr),
.m_axi_awburst(m_axi_awburst),
.\m_axi_awregion[3] (\m_axi_awregion[3] ),
.m_axi_awsize(m_axi_awsize),
.s_axi_aclk(s_axi_aclk),
.s_axi_aresetn(s_axi_aresetn),
.s_axi_awready(s_axi_awready),
.s_axi_awvalid(s_axi_awvalid),
.sr_awvalid(sr_awvalid));
endmodule
|
module system_auto_us_0_axi_register_slice_v2_1_11_axic_register_slice
(s_ready_i_reg_0,
sr_arvalid,
Q,
s_axi_arready,
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29] ,
m_axi_arsize,
m_axi_arburst,
m_axi_araddr,
s_axi_aresetn,
\aresetn_d_reg[0] ,
s_axi_aclk,
cmd_push_block_reg,
s_axi_arvalid,
\s_axi_arregion[3] );
output s_ready_i_reg_0;
output sr_arvalid;
output [44:0]Q;
output s_axi_arready;
output [27:0]\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29] ;
output [2:0]m_axi_arsize;
output [1:0]m_axi_arburst;
output [2:0]m_axi_araddr;
input s_axi_aresetn;
input \aresetn_d_reg[0] ;
input s_axi_aclk;
input cmd_push_block_reg;
input s_axi_arvalid;
input [60:0]\s_axi_arregion[3] ;
wire [44:0]Q;
wire [27:0]\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29] ;
wire \USE_READ.read_addr_inst/access_need_extra_word__3 ;
wire [2:2]\USE_READ.read_addr_inst/cmd_next_word_ii__10 ;
wire \USE_RTL_FIFO.data_srl_reg[31][11]_srl32_i_2_n_0 ;
wire \USE_RTL_FIFO.data_srl_reg[31][11]_srl32_i_3_n_0 ;
wire \USE_RTL_FIFO.data_srl_reg[31][12]_srl32_i_2_n_0 ;
wire \USE_RTL_FIFO.data_srl_reg[31][16]_srl32_i_2_n_0 ;
wire \USE_RTL_FIFO.data_srl_reg[31][18]_srl32_i_2__0_n_0 ;
wire \USE_RTL_FIFO.data_srl_reg[31][18]_srl32_i_3__0_n_0 ;
wire \USE_RTL_FIFO.data_srl_reg[31][18]_srl32_i_4_n_0 ;
wire \USE_RTL_FIFO.data_srl_reg[31][18]_srl32_i_5_n_0 ;
wire \USE_RTL_FIFO.data_srl_reg[31][19]_srl32_i_2__0_n_0 ;
wire \USE_RTL_FIFO.data_srl_reg[31][19]_srl32_i_3_n_0 ;
wire \USE_RTL_FIFO.data_srl_reg[31][19]_srl32_i_4_n_0 ;
wire \USE_RTL_FIFO.data_srl_reg[31][26]_srl32_i_2_n_0 ;
wire \aresetn_d_reg[0] ;
wire cmd_push_block_reg;
wire [2:0]m_axi_araddr;
wire \m_axi_araddr[0]_INST_0_i_1_n_0 ;
wire \m_axi_araddr[1]_INST_0_i_1_n_0 ;
wire \m_axi_araddr[1]_INST_0_i_2_n_0 ;
wire \m_axi_araddr[1]_INST_0_i_3_n_0 ;
wire \m_axi_araddr[1]_INST_0_i_4_n_0 ;
wire \m_axi_araddr[1]_INST_0_i_5_n_0 ;
wire \m_axi_araddr[2]_INST_0_i_1_n_0 ;
wire \m_axi_araddr[2]_INST_0_i_2_n_0 ;
wire \m_axi_araddr[2]_INST_0_i_3_n_0 ;
wire [1:0]m_axi_arburst;
wire \m_axi_arburst[0]_INST_0_i_1_n_0 ;
wire \m_axi_arburst[0]_INST_0_i_2_n_0 ;
wire \m_axi_arburst[1]_INST_0_i_1_n_0 ;
wire \m_axi_arburst[1]_INST_0_i_2_n_0 ;
wire \m_axi_arlen[0]_INST_0_i_1_n_0 ;
wire \m_axi_arlen[0]_INST_0_i_3_n_0 ;
wire \m_axi_arlen[0]_INST_0_i_4_n_0 ;
wire \m_axi_arlen[1]_INST_0_i_10_n_0 ;
wire \m_axi_arlen[1]_INST_0_i_1_n_0 ;
wire \m_axi_arlen[1]_INST_0_i_2_n_0 ;
wire \m_axi_arlen[1]_INST_0_i_3_n_0 ;
wire \m_axi_arlen[1]_INST_0_i_4_n_0 ;
wire \m_axi_arlen[1]_INST_0_i_5_n_0 ;
wire \m_axi_arlen[1]_INST_0_i_6_n_0 ;
wire \m_axi_arlen[1]_INST_0_i_7_n_0 ;
wire \m_axi_arlen[1]_INST_0_i_8_n_0 ;
wire \m_axi_arlen[1]_INST_0_i_9_n_0 ;
wire \m_axi_arlen[2]_INST_0_i_1_n_0 ;
wire \m_axi_arlen[2]_INST_0_i_2_n_0 ;
wire \m_axi_arlen[3]_INST_0_i_1_n_0 ;
wire \m_axi_arlen[3]_INST_0_i_2_n_0 ;
wire \m_axi_arlen[3]_INST_0_i_3_n_0 ;
wire \m_axi_arlen[3]_INST_0_i_4_n_0 ;
wire \m_axi_arlen[3]_INST_0_i_5_n_0 ;
wire \m_axi_arlen[3]_INST_0_i_6_n_0 ;
wire \m_axi_arlen[3]_INST_0_i_7_n_0 ;
wire \m_axi_arlen[4]_INST_0_i_1_n_0 ;
wire \m_axi_arlen[4]_INST_0_i_2_n_0 ;
wire \m_axi_arlen[5]_INST_0_i_1_n_0 ;
wire \m_axi_arlen[5]_INST_0_i_2_n_0 ;
wire \m_axi_arlen[6]_INST_0_i_1_n_0 ;
wire \m_axi_arlen[6]_INST_0_i_2_n_0 ;
wire \m_axi_arlen[7]_INST_0_i_1_n_0 ;
wire \m_axi_arlen[7]_INST_0_i_2_n_0 ;
wire \m_axi_arlen[7]_INST_0_i_3_n_0 ;
wire [2:0]m_axi_arsize;
wire \m_payload_i[31]_i_1__0_n_0 ;
wire m_valid_i_i_1_n_0;
wire s_axi_aclk;
wire s_axi_aresetn;
wire [7:0]s_axi_arlen_ii;
wire s_axi_arready;
wire [60:0]\s_axi_arregion[3] ;
wire s_axi_arvalid;
wire s_ready_i_i_1_n_0;
wire s_ready_i_reg_0;
wire [2:0]sr_araddr;
wire [1:0]sr_arburst;
wire [2:0]sr_arsize;
wire sr_arvalid;
(* SOFT_HLUTNM = "soft_lutpair71" *)
LUT3 #(
.INIT(8'h02))
\USE_RTL_FIFO.data_srl_reg[31][10]_srl32_i_1__0
(.I0(sr_arsize[1]),
.I1(sr_arsize[2]),
.I2(sr_arsize[0]),
.O(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29] [10]));
LUT5 #(
.INIT(32'hFFFFAAAE))
\USE_RTL_FIFO.data_srl_reg[31][11]_srl32_i_1__0
(.I0(\USE_RTL_FIFO.data_srl_reg[31][11]_srl32_i_2_n_0 ),
.I1(s_axi_arlen_ii[0]),
.I2(sr_arsize[1]),
.I3(sr_arsize[0]),
.I4(\USE_RTL_FIFO.data_srl_reg[31][11]_srl32_i_3_n_0 ),
.O(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29] [11]));
(* SOFT_HLUTNM = "soft_lutpair69" *)
LUT3 #(
.INIT(8'hFD))
\USE_RTL_FIFO.data_srl_reg[31][11]_srl32_i_2
(.I0(sr_arburst[1]),
.I1(sr_arburst[0]),
.I2(\m_axi_araddr[1]_INST_0_i_2_n_0 ),
.O(\USE_RTL_FIFO.data_srl_reg[31][11]_srl32_i_2_n_0 ));
LUT6 #(
.INIT(64'hFEFEFCECFEAAFCA8))
\USE_RTL_FIFO.data_srl_reg[31][11]_srl32_i_3
(.I0(s_axi_arlen_ii[2]),
.I1(sr_arsize[2]),
.I2(sr_arsize[1]),
.I3(s_axi_arlen_ii[1]),
.I4(sr_arsize[0]),
.I5(s_axi_arlen_ii[0]),
.O(\USE_RTL_FIFO.data_srl_reg[31][11]_srl32_i_3_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFFFFFFF888))
\USE_RTL_FIFO.data_srl_reg[31][12]_srl32_i_1__0
(.I0(\m_axi_araddr[1]_INST_0_i_4_n_0 ),
.I1(s_axi_arlen_ii[0]),
.I2(s_axi_arlen_ii[1]),
.I3(\m_axi_araddr[1]_INST_0_i_5_n_0 ),
.I4(\USE_RTL_FIFO.data_srl_reg[31][12]_srl32_i_2_n_0 ),
.I5(\USE_RTL_FIFO.data_srl_reg[31][11]_srl32_i_2_n_0 ),
.O(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29] [12]));
(* SOFT_HLUTNM = "soft_lutpair62" *)
LUT4 #(
.INIT(16'hFE00))
\USE_RTL_FIFO.data_srl_reg[31][12]_srl32_i_2
(.I0(sr_arsize[0]),
.I1(sr_arsize[1]),
.I2(sr_arsize[2]),
.I3(s_axi_arlen_ii[2]),
.O(\USE_RTL_FIFO.data_srl_reg[31][12]_srl32_i_2_n_0 ));
LUT6 #(
.INIT(64'hFFFEFFEEFFFEEEEE))
\USE_RTL_FIFO.data_srl_reg[31][13]_srl32_i_1__0
(.I0(s_axi_arlen_ii[2]),
.I1(\USE_RTL_FIFO.data_srl_reg[31][11]_srl32_i_2_n_0 ),
.I2(sr_arsize[0]),
.I3(\m_axi_araddr[2]_INST_0_i_3_n_0 ),
.I4(s_axi_arlen_ii[1]),
.I5(s_axi_arlen_ii[0]),
.O(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29] [13]));
LUT6 #(
.INIT(64'h00000000022202AA))
\USE_RTL_FIFO.data_srl_reg[31][16]_srl32_i_1__0
(.I0(sr_araddr[2]),
.I1(\m_axi_araddr[2]_INST_0_i_3_n_0 ),
.I2(sr_arsize[0]),
.I3(s_axi_arlen_ii[1]),
.I4(s_axi_arlen_ii[0]),
.I5(\USE_RTL_FIFO.data_srl_reg[31][16]_srl32_i_2_n_0 ),
.O(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29] [14]));
(* SOFT_HLUTNM = "soft_lutpair69" *)
LUT4 #(
.INIT(16'hFFEF))
\USE_RTL_FIFO.data_srl_reg[31][16]_srl32_i_2
(.I0(\m_axi_araddr[1]_INST_0_i_2_n_0 ),
.I1(sr_arburst[0]),
.I2(sr_arburst[1]),
.I3(s_axi_arlen_ii[2]),
.O(\USE_RTL_FIFO.data_srl_reg[31][16]_srl32_i_2_n_0 ));
LUT6 #(
.INIT(64'h1414144414141044))
\USE_RTL_FIFO.data_srl_reg[31][17]_srl32_i_1__0
(.I0(\m_axi_araddr[1]_INST_0_i_1_n_0 ),
.I1(sr_araddr[0]),
.I2(s_axi_arlen_ii[0]),
.I3(sr_arburst[1]),
.I4(sr_arburst[0]),
.I5(\m_axi_araddr[1]_INST_0_i_2_n_0 ),
.O(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29] [15]));
LUT6 #(
.INIT(64'h8848488848884888))
\USE_RTL_FIFO.data_srl_reg[31][18]_srl32_i_1__0
(.I0(sr_araddr[1]),
.I1(\USE_RTL_FIFO.data_srl_reg[31][18]_srl32_i_2__0_n_0 ),
.I2(\USE_RTL_FIFO.data_srl_reg[31][18]_srl32_i_3__0_n_0 ),
.I3(\USE_RTL_FIFO.data_srl_reg[31][18]_srl32_i_4_n_0 ),
.I4(s_axi_arlen_ii[0]),
.I5(\USE_RTL_FIFO.data_srl_reg[31][18]_srl32_i_5_n_0 ),
.O(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29] [16]));
LUT6 #(
.INIT(64'h0000FFFC0000EEFC))
\USE_RTL_FIFO.data_srl_reg[31][18]_srl32_i_2__0
(.I0(s_axi_arlen_ii[2]),
.I1(\USE_RTL_FIFO.data_srl_reg[31][11]_srl32_i_2_n_0 ),
.I2(s_axi_arlen_ii[1]),
.I3(sr_arsize[0]),
.I4(\m_axi_araddr[2]_INST_0_i_3_n_0 ),
.I5(s_axi_arlen_ii[0]),
.O(\USE_RTL_FIFO.data_srl_reg[31][18]_srl32_i_2__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair73" *)
LUT2 #(
.INIT(4'hE))
\USE_RTL_FIFO.data_srl_reg[31][18]_srl32_i_3__0
(.I0(sr_arburst[0]),
.I1(sr_arburst[1]),
.O(\USE_RTL_FIFO.data_srl_reg[31][18]_srl32_i_3__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair65" *)
LUT5 #(
.INIT(32'h02030200))
\USE_RTL_FIFO.data_srl_reg[31][18]_srl32_i_4
(.I0(s_axi_arlen_ii[0]),
.I1(sr_arsize[2]),
.I2(sr_arsize[1]),
.I3(sr_arsize[0]),
.I4(s_axi_arlen_ii[1]),
.O(\USE_RTL_FIFO.data_srl_reg[31][18]_srl32_i_4_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair68" *)
LUT4 #(
.INIT(16'h0002))
\USE_RTL_FIFO.data_srl_reg[31][18]_srl32_i_5
(.I0(sr_araddr[0]),
.I1(sr_arsize[0]),
.I2(sr_arsize[1]),
.I3(sr_arsize[2]),
.O(\USE_RTL_FIFO.data_srl_reg[31][18]_srl32_i_5_n_0 ));
LUT6 #(
.INIT(64'h2228282828282828))
\USE_RTL_FIFO.data_srl_reg[31][19]_srl32_i_1__0
(.I0(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29] [13]),
.I1(\USE_RTL_FIFO.data_srl_reg[31][19]_srl32_i_2__0_n_0 ),
.I2(\USE_RTL_FIFO.data_srl_reg[31][19]_srl32_i_3_n_0 ),
.I3(\USE_RTL_FIFO.data_srl_reg[31][18]_srl32_i_4_n_0 ),
.I4(\USE_RTL_FIFO.data_srl_reg[31][18]_srl32_i_3__0_n_0 ),
.I5(sr_araddr[1]),
.O(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29] [17]));
LUT6 #(
.INIT(64'h7888788877887888))
\USE_RTL_FIFO.data_srl_reg[31][19]_srl32_i_2__0
(.I0(sr_araddr[2]),
.I1(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29] [13]),
.I2(\m_axi_arlen[0]_INST_0_i_3_n_0 ),
.I3(\USE_RTL_FIFO.data_srl_reg[31][18]_srl32_i_3__0_n_0 ),
.I4(s_axi_arlen_ii[1]),
.I5(\m_axi_araddr[1]_INST_0_i_5_n_0 ),
.O(\USE_RTL_FIFO.data_srl_reg[31][19]_srl32_i_2__0_n_0 ));
LUT6 #(
.INIT(64'hFFFFF08088888080))
\USE_RTL_FIFO.data_srl_reg[31][19]_srl32_i_3
(.I0(\USE_RTL_FIFO.data_srl_reg[31][18]_srl32_i_5_n_0 ),
.I1(\m_axi_arlen[1]_INST_0_i_6_n_0 ),
.I2(sr_arburst[1]),
.I3(\m_axi_araddr[1]_INST_0_i_2_n_0 ),
.I4(sr_arburst[0]),
.I5(\USE_RTL_FIFO.data_srl_reg[31][19]_srl32_i_4_n_0 ),
.O(\USE_RTL_FIFO.data_srl_reg[31][19]_srl32_i_3_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair63" *)
LUT5 #(
.INIT(32'h00000080))
\USE_RTL_FIFO.data_srl_reg[31][19]_srl32_i_4
(.I0(sr_araddr[0]),
.I1(sr_araddr[1]),
.I2(s_axi_arlen_ii[0]),
.I3(sr_arsize[2]),
.I4(sr_arsize[1]),
.O(\USE_RTL_FIFO.data_srl_reg[31][19]_srl32_i_4_n_0 ));
LUT6 #(
.INIT(64'h0001000100010000))
\USE_RTL_FIFO.data_srl_reg[31][20]_srl32_i_1__0
(.I0(sr_arsize[2]),
.I1(sr_arsize[1]),
.I2(sr_arsize[0]),
.I3(sr_araddr[0]),
.I4(s_axi_arlen_ii[0]),
.I5(\USE_RTL_FIFO.data_srl_reg[31][11]_srl32_i_2_n_0 ),
.O(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29] [18]));
LUT6 #(
.INIT(64'h8888882288888828))
\USE_RTL_FIFO.data_srl_reg[31][21]_srl32_i_1__0
(.I0(\USE_RTL_FIFO.data_srl_reg[31][18]_srl32_i_2__0_n_0 ),
.I1(sr_araddr[1]),
.I2(sr_arsize[0]),
.I3(sr_arsize[1]),
.I4(sr_arsize[2]),
.I5(sr_araddr[0]),
.O(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29] [19]));
(* SOFT_HLUTNM = "soft_lutpair74" *)
LUT2 #(
.INIT(4'h8))
\USE_RTL_FIFO.data_srl_reg[31][22]_srl32_i_1__0
(.I0(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29] [13]),
.I1(\USE_READ.read_addr_inst/cmd_next_word_ii__10 ),
.O(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29] [20]));
LUT6 #(
.INIT(64'hFFF5FF07000A00F8))
\USE_RTL_FIFO.data_srl_reg[31][22]_srl32_i_2__0
(.I0(sr_araddr[1]),
.I1(sr_araddr[0]),
.I2(sr_arsize[1]),
.I3(sr_arsize[2]),
.I4(sr_arsize[0]),
.I5(sr_araddr[2]),
.O(\USE_READ.read_addr_inst/cmd_next_word_ii__10 ));
LUT6 #(
.INIT(64'h0100010001000000))
\USE_RTL_FIFO.data_srl_reg[31][23]_srl32_i_1__0
(.I0(sr_arsize[2]),
.I1(sr_arsize[1]),
.I2(sr_arsize[0]),
.I3(sr_araddr[0]),
.I4(s_axi_arlen_ii[0]),
.I5(\USE_RTL_FIFO.data_srl_reg[31][11]_srl32_i_2_n_0 ),
.O(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29] [21]));
(* SOFT_HLUTNM = "soft_lutpair67" *)
LUT2 #(
.INIT(4'h8))
\USE_RTL_FIFO.data_srl_reg[31][24]_srl32_i_1__0
(.I0(\USE_RTL_FIFO.data_srl_reg[31][18]_srl32_i_2__0_n_0 ),
.I1(sr_araddr[1]),
.O(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29] [22]));
(* SOFT_HLUTNM = "soft_lutpair74" *)
LUT2 #(
.INIT(4'h8))
\USE_RTL_FIFO.data_srl_reg[31][25]_srl32_i_1__0
(.I0(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29] [13]),
.I1(sr_araddr[2]),
.O(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29] [23]));
LUT6 #(
.INIT(64'h5554555455540000))
\USE_RTL_FIFO.data_srl_reg[31][26]_srl32_i_1
(.I0(\USE_RTL_FIFO.data_srl_reg[31][26]_srl32_i_2_n_0 ),
.I1(sr_araddr[2]),
.I2(sr_araddr[1]),
.I3(sr_araddr[0]),
.I4(\m_axi_araddr[1]_INST_0_i_2_n_0 ),
.I5(\USE_RTL_FIFO.data_srl_reg[31][11]_srl32_i_3_n_0 ),
.O(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29] [24]));
(* SOFT_HLUTNM = "soft_lutpair72" *)
LUT3 #(
.INIT(8'hDF))
\USE_RTL_FIFO.data_srl_reg[31][26]_srl32_i_2
(.I0(sr_arburst[1]),
.I1(sr_arburst[0]),
.I2(Q[33]),
.O(\USE_RTL_FIFO.data_srl_reg[31][26]_srl32_i_2_n_0 ));
LUT5 #(
.INIT(32'h13100000))
\USE_RTL_FIFO.data_srl_reg[31][27]_srl32_i_1
(.I0(\m_axi_araddr[1]_INST_0_i_1_n_0 ),
.I1(\USE_RTL_FIFO.data_srl_reg[31][11]_srl32_i_2_n_0 ),
.I2(s_axi_arlen_ii[2]),
.I3(\m_axi_arburst[0]_INST_0_i_2_n_0 ),
.I4(Q[33]),
.O(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29] [25]));
LUT6 #(
.INIT(64'hFEFEFE0000000000))
\USE_RTL_FIFO.data_srl_reg[31][28]_srl32_i_1
(.I0(\m_axi_araddr[2]_INST_0_i_2_n_0 ),
.I1(s_axi_arlen_ii[1]),
.I2(s_axi_arlen_ii[0]),
.I3(sr_arburst[1]),
.I4(sr_arburst[0]),
.I5(Q[33]),
.O(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29] [26]));
LUT2 #(
.INIT(4'h1))
\USE_RTL_FIFO.data_srl_reg[31][29]_srl32_i_1__0
(.I0(sr_arburst[1]),
.I1(sr_arburst[0]),
.O(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29] [27]));
(* SOFT_HLUTNM = "soft_lutpair70" *)
LUT3 #(
.INIT(8'h01))
\USE_RTL_FIFO.data_srl_reg[31][8]_srl32_i_1__0
(.I0(sr_arsize[0]),
.I1(sr_arsize[1]),
.I2(sr_arsize[2]),
.O(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29] [8]));
(* SOFT_HLUTNM = "soft_lutpair70" *)
LUT3 #(
.INIT(8'h02))
\USE_RTL_FIFO.data_srl_reg[31][9]_srl32_i_1__0
(.I0(sr_arsize[0]),
.I1(sr_arsize[1]),
.I2(sr_arsize[2]),
.O(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29] [9]));
FDRE #(
.INIT(1'b0))
\aresetn_d_reg[1]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\aresetn_d_reg[0] ),
.Q(s_ready_i_reg_0),
.R(s_axi_aresetn));
LUT6 #(
.INIT(64'hEEEEEEEFCCCCCCCC))
\m_axi_araddr[0]_INST_0
(.I0(\m_axi_araddr[2]_INST_0_i_1_n_0 ),
.I1(\m_axi_araddr[0]_INST_0_i_1_n_0 ),
.I2(s_axi_arlen_ii[0]),
.I3(\m_axi_araddr[1]_INST_0_i_2_n_0 ),
.I4(\m_axi_araddr[1]_INST_0_i_1_n_0 ),
.I5(sr_araddr[0]),
.O(m_axi_araddr[0]));
LUT6 #(
.INIT(64'h0004000000040400))
\m_axi_araddr[0]_INST_0_i_1
(.I0(\m_axi_araddr[2]_INST_0_i_2_n_0 ),
.I1(sr_araddr[0]),
.I2(sr_arsize[2]),
.I3(sr_arsize[1]),
.I4(sr_arsize[0]),
.I5(s_axi_arlen_ii[1]),
.O(\m_axi_araddr[0]_INST_0_i_1_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFFA0A0A0B0))
\m_axi_araddr[1]_INST_0
(.I0(\m_axi_araddr[2]_INST_0_i_1_n_0 ),
.I1(\m_axi_araddr[1]_INST_0_i_1_n_0 ),
.I2(sr_araddr[1]),
.I3(s_axi_arlen_ii[1]),
.I4(\m_axi_araddr[1]_INST_0_i_2_n_0 ),
.I5(\m_axi_araddr[1]_INST_0_i_3_n_0 ),
.O(m_axi_araddr[1]));
(* SOFT_HLUTNM = "soft_lutpair64" *)
LUT3 #(
.INIT(8'hFE))
\m_axi_araddr[1]_INST_0_i_1
(.I0(sr_arsize[2]),
.I1(sr_arsize[1]),
.I2(sr_arsize[0]),
.O(\m_axi_araddr[1]_INST_0_i_1_n_0 ));
LUT5 #(
.INIT(32'hFFFFFFFE))
\m_axi_araddr[1]_INST_0_i_2
(.I0(s_axi_arlen_ii[3]),
.I1(s_axi_arlen_ii[6]),
.I2(s_axi_arlen_ii[7]),
.I3(s_axi_arlen_ii[5]),
.I4(s_axi_arlen_ii[4]),
.O(\m_axi_araddr[1]_INST_0_i_2_n_0 ));
LUT6 #(
.INIT(64'h0004000400044444))
\m_axi_araddr[1]_INST_0_i_3
(.I0(\m_axi_araddr[2]_INST_0_i_2_n_0 ),
.I1(sr_araddr[1]),
.I2(\m_axi_araddr[1]_INST_0_i_4_n_0 ),
.I3(s_axi_arlen_ii[1]),
.I4(\m_axi_araddr[1]_INST_0_i_5_n_0 ),
.I5(s_axi_arlen_ii[0]),
.O(\m_axi_araddr[1]_INST_0_i_3_n_0 ));
LUT2 #(
.INIT(4'hE))
\m_axi_araddr[1]_INST_0_i_4
(.I0(sr_arsize[0]),
.I1(sr_arsize[2]),
.O(\m_axi_araddr[1]_INST_0_i_4_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair68" *)
LUT3 #(
.INIT(8'hEF))
\m_axi_araddr[1]_INST_0_i_5
(.I0(sr_arsize[2]),
.I1(sr_arsize[1]),
.I2(sr_arsize[0]),
.O(\m_axi_araddr[1]_INST_0_i_5_n_0 ));
LUT6 #(
.INIT(64'hAAABABAB00000000))
\m_axi_araddr[2]_INST_0
(.I0(\m_axi_araddr[2]_INST_0_i_1_n_0 ),
.I1(\m_axi_araddr[2]_INST_0_i_2_n_0 ),
.I2(\m_axi_araddr[2]_INST_0_i_3_n_0 ),
.I3(sr_arsize[0]),
.I4(s_axi_arlen_ii[1]),
.I5(sr_araddr[2]),
.O(m_axi_araddr[2]));
LUT6 #(
.INIT(64'hDFDFDFDFDFDFDFFF))
\m_axi_araddr[2]_INST_0_i_1
(.I0(Q[33]),
.I1(sr_arburst[0]),
.I2(sr_arburst[1]),
.I3(s_axi_arlen_ii[0]),
.I4(s_axi_arlen_ii[1]),
.I5(\m_axi_araddr[2]_INST_0_i_2_n_0 ),
.O(\m_axi_araddr[2]_INST_0_i_1_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFFFFFFFFFE))
\m_axi_araddr[2]_INST_0_i_2
(.I0(s_axi_arlen_ii[4]),
.I1(s_axi_arlen_ii[5]),
.I2(s_axi_arlen_ii[7]),
.I3(s_axi_arlen_ii[6]),
.I4(s_axi_arlen_ii[3]),
.I5(s_axi_arlen_ii[2]),
.O(\m_axi_araddr[2]_INST_0_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair63" *)
LUT2 #(
.INIT(4'hE))
\m_axi_araddr[2]_INST_0_i_3
(.I0(sr_arsize[1]),
.I1(sr_arsize[2]),
.O(\m_axi_araddr[2]_INST_0_i_3_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFF00004000))
\m_axi_arburst[0]_INST_0
(.I0(\m_axi_araddr[1]_INST_0_i_2_n_0 ),
.I1(Q[33]),
.I2(s_axi_arlen_ii[2]),
.I3(sr_arburst[1]),
.I4(\m_axi_araddr[1]_INST_0_i_1_n_0 ),
.I5(\m_axi_arburst[0]_INST_0_i_1_n_0 ),
.O(m_axi_arburst[0]));
LUT6 #(
.INIT(64'hFFFFFFFF10000000))
\m_axi_arburst[0]_INST_0_i_1
(.I0(\m_axi_araddr[1]_INST_0_i_2_n_0 ),
.I1(s_axi_arlen_ii[2]),
.I2(Q[33]),
.I3(sr_arburst[1]),
.I4(\m_axi_arburst[0]_INST_0_i_2_n_0 ),
.I5(sr_arburst[0]),
.O(\m_axi_arburst[0]_INST_0_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair65" *)
LUT5 #(
.INIT(32'h03030700))
\m_axi_arburst[0]_INST_0_i_2
(.I0(sr_arsize[0]),
.I1(sr_arsize[1]),
.I2(sr_arsize[2]),
.I3(s_axi_arlen_ii[0]),
.I4(s_axi_arlen_ii[1]),
.O(\m_axi_arburst[0]_INST_0_i_2_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFDFF00FF00))
\m_axi_arburst[1]_INST_0
(.I0(Q[33]),
.I1(\m_axi_araddr[1]_INST_0_i_2_n_0 ),
.I2(\m_axi_arburst[1]_INST_0_i_1_n_0 ),
.I3(\m_axi_arburst[1]_INST_0_i_2_n_0 ),
.I4(sr_arburst[0]),
.I5(sr_arburst[1]),
.O(m_axi_arburst[1]));
(* SOFT_HLUTNM = "soft_lutpair71" *)
LUT3 #(
.INIT(8'hF8))
\m_axi_arburst[1]_INST_0_i_1
(.I0(sr_arsize[1]),
.I1(sr_arsize[0]),
.I2(sr_arsize[2]),
.O(\m_axi_arburst[1]_INST_0_i_1_n_0 ));
LUT6 #(
.INIT(64'hFF00A000BB00B100))
\m_axi_arburst[1]_INST_0_i_2
(.I0(s_axi_arlen_ii[2]),
.I1(s_axi_arlen_ii[0]),
.I2(sr_arsize[0]),
.I3(sr_arburst[1]),
.I4(sr_arsize[1]),
.I5(s_axi_arlen_ii[1]),
.O(\m_axi_arburst[1]_INST_0_i_2_n_0 ));
LUT6 #(
.INIT(64'h00151515FFEAEAEA))
\m_axi_arlen[0]_INST_0
(.I0(\m_axi_arlen[0]_INST_0_i_1_n_0 ),
.I1(s_axi_arlen_ii[1]),
.I2(\m_axi_arlen[6]_INST_0_i_2_n_0 ),
.I3(\m_axi_arlen[7]_INST_0_i_2_n_0 ),
.I4(s_axi_arlen_ii[0]),
.I5(\USE_READ.read_addr_inst/access_need_extra_word__3 ),
.O(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29] [0]));
LUT6 #(
.INIT(64'h0000000000000A0C))
\m_axi_arlen[0]_INST_0_i_1
(.I0(s_axi_arlen_ii[2]),
.I1(s_axi_arlen_ii[3]),
.I2(\m_axi_arlen[7]_INST_0_i_2_n_0 ),
.I3(sr_arsize[0]),
.I4(sr_arsize[1]),
.I5(sr_arsize[2]),
.O(\m_axi_arlen[0]_INST_0_i_1_n_0 ));
LUT6 #(
.INIT(64'hFFF8F8F800000000))
\m_axi_arlen[0]_INST_0_i_2
(.I0(sr_araddr[2]),
.I1(\m_axi_arlen[0]_INST_0_i_3_n_0 ),
.I2(\m_axi_arlen[1]_INST_0_i_3_n_0 ),
.I3(\m_axi_arlen[0]_INST_0_i_4_n_0 ),
.I4(\m_axi_arlen[3]_INST_0_i_6_n_0 ),
.I5(\m_axi_arlen[3]_INST_0_i_5_n_0 ),
.O(\USE_READ.read_addr_inst/access_need_extra_word__3 ));
(* SOFT_HLUTNM = "soft_lutpair64" *)
LUT5 #(
.INIT(32'h00230020))
\m_axi_arlen[0]_INST_0_i_3
(.I0(s_axi_arlen_ii[0]),
.I1(sr_arsize[2]),
.I2(sr_arsize[1]),
.I3(sr_arsize[0]),
.I4(s_axi_arlen_ii[2]),
.O(\m_axi_arlen[0]_INST_0_i_3_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair62" *)
LUT5 #(
.INIT(32'h02030202))
\m_axi_arlen[0]_INST_0_i_4
(.I0(sr_araddr[2]),
.I1(sr_arsize[2]),
.I2(sr_arsize[1]),
.I3(sr_arsize[0]),
.I4(s_axi_arlen_ii[2]),
.O(\m_axi_arlen[0]_INST_0_i_4_n_0 ));
LUT6 #(
.INIT(64'h151515EA15EA15EA))
\m_axi_arlen[1]_INST_0
(.I0(\m_axi_arlen[1]_INST_0_i_1_n_0 ),
.I1(\m_axi_arlen[1]_INST_0_i_2_n_0 ),
.I2(\m_axi_arlen[1]_INST_0_i_3_n_0 ),
.I3(\m_axi_arlen[1]_INST_0_i_4_n_0 ),
.I4(\m_axi_arlen[7]_INST_0_i_2_n_0 ),
.I5(s_axi_arlen_ii[1]),
.O(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29] [1]));
LUT6 #(
.INIT(64'hAAAAAAAAFFAAEAAA))
\m_axi_arlen[1]_INST_0_i_1
(.I0(\m_axi_arlen[1]_INST_0_i_5_n_0 ),
.I1(\m_axi_arlen[1]_INST_0_i_6_n_0 ),
.I2(sr_araddr[0]),
.I3(\m_axi_arlen[3]_INST_0_i_4_n_0 ),
.I4(sr_araddr[2]),
.I5(\m_axi_araddr[1]_INST_0_i_1_n_0 ),
.O(\m_axi_arlen[1]_INST_0_i_1_n_0 ));
LUT6 #(
.INIT(64'h1000000000000000))
\m_axi_arlen[1]_INST_0_i_10
(.I0(sr_arsize[0]),
.I1(sr_arsize[2]),
.I2(sr_araddr[0]),
.I3(sr_araddr[2]),
.I4(s_axi_arlen_ii[0]),
.I5(s_axi_arlen_ii[1]),
.O(\m_axi_arlen[1]_INST_0_i_10_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair66" *)
LUT4 #(
.INIT(16'h0800))
\m_axi_arlen[1]_INST_0_i_2
(.I0(Q[33]),
.I1(sr_arburst[0]),
.I2(sr_arburst[1]),
.I3(s_axi_arlen_ii[2]),
.O(\m_axi_arlen[1]_INST_0_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair61" *)
LUT5 #(
.INIT(32'h0000E888))
\m_axi_arlen[1]_INST_0_i_3
(.I0(sr_araddr[2]),
.I1(s_axi_arlen_ii[1]),
.I2(s_axi_arlen_ii[0]),
.I3(sr_araddr[1]),
.I4(\m_axi_araddr[1]_INST_0_i_5_n_0 ),
.O(\m_axi_arlen[1]_INST_0_i_3_n_0 ));
LUT6 #(
.INIT(64'hFFFFF888F888F888))
\m_axi_arlen[1]_INST_0_i_4
(.I0(\m_axi_arlen[1]_INST_0_i_7_n_0 ),
.I1(s_axi_arlen_ii[4]),
.I2(\m_axi_arlen[1]_INST_0_i_8_n_0 ),
.I3(s_axi_arlen_ii[3]),
.I4(s_axi_arlen_ii[2]),
.I5(\m_axi_arlen[6]_INST_0_i_2_n_0 ),
.O(\m_axi_arlen[1]_INST_0_i_4_n_0 ));
LUT6 #(
.INIT(64'hFFFF0000F4000000))
\m_axi_arlen[1]_INST_0_i_5
(.I0(\m_axi_araddr[1]_INST_0_i_1_n_0 ),
.I1(\m_axi_arlen[1]_INST_0_i_9_n_0 ),
.I2(\m_axi_arlen[1]_INST_0_i_10_n_0 ),
.I3(s_axi_arlen_ii[3]),
.I4(\m_axi_arlen[3]_INST_0_i_5_n_0 ),
.I5(\m_axi_arlen[7]_INST_0_i_3_n_0 ),
.O(\m_axi_arlen[1]_INST_0_i_5_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair61" *)
LUT2 #(
.INIT(4'h8))
\m_axi_arlen[1]_INST_0_i_6
(.I0(s_axi_arlen_ii[0]),
.I1(s_axi_arlen_ii[1]),
.O(\m_axi_arlen[1]_INST_0_i_6_n_0 ));
LUT6 #(
.INIT(64'h00000000000000A8))
\m_axi_arlen[1]_INST_0_i_7
(.I0(Q[33]),
.I1(sr_arburst[0]),
.I2(sr_arburst[1]),
.I3(sr_arsize[0]),
.I4(sr_arsize[1]),
.I5(sr_arsize[2]),
.O(\m_axi_arlen[1]_INST_0_i_7_n_0 ));
LUT6 #(
.INIT(64'h000000000000A800))
\m_axi_arlen[1]_INST_0_i_8
(.I0(Q[33]),
.I1(sr_arburst[0]),
.I2(sr_arburst[1]),
.I3(sr_arsize[0]),
.I4(sr_arsize[1]),
.I5(sr_arsize[2]),
.O(\m_axi_arlen[1]_INST_0_i_8_n_0 ));
LUT6 #(
.INIT(64'hA8A8A800A800A800))
\m_axi_arlen[1]_INST_0_i_9
(.I0(sr_araddr[1]),
.I1(sr_araddr[2]),
.I2(s_axi_arlen_ii[2]),
.I3(s_axi_arlen_ii[1]),
.I4(sr_araddr[0]),
.I5(s_axi_arlen_ii[0]),
.O(\m_axi_arlen[1]_INST_0_i_9_n_0 ));
LUT6 #(
.INIT(64'h5555566656665666))
\m_axi_arlen[2]_INST_0
(.I0(\m_axi_arlen[2]_INST_0_i_1_n_0 ),
.I1(\m_axi_arlen[2]_INST_0_i_2_n_0 ),
.I2(s_axi_arlen_ii[3]),
.I3(\m_axi_arlen[6]_INST_0_i_2_n_0 ),
.I4(\m_axi_arlen[7]_INST_0_i_2_n_0 ),
.I5(s_axi_arlen_ii[2]),
.O(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29] [2]));
LUT6 #(
.INIT(64'hFFFFEAAAEAAAEAAA))
\m_axi_arlen[2]_INST_0_i_1
(.I0(\m_axi_arlen[3]_INST_0_i_1_n_0 ),
.I1(s_axi_arlen_ii[2]),
.I2(\m_axi_arlen[3]_INST_0_i_5_n_0 ),
.I3(\m_axi_arlen[7]_INST_0_i_3_n_0 ),
.I4(s_axi_arlen_ii[4]),
.I5(\m_axi_arlen[3]_INST_0_i_2_n_0 ),
.O(\m_axi_arlen[2]_INST_0_i_1_n_0 ));
LUT6 #(
.INIT(64'h0000000000000A0C))
\m_axi_arlen[2]_INST_0_i_2
(.I0(s_axi_arlen_ii[4]),
.I1(s_axi_arlen_ii[5]),
.I2(\m_axi_arlen[7]_INST_0_i_2_n_0 ),
.I3(sr_arsize[0]),
.I4(sr_arsize[1]),
.I5(sr_arsize[2]),
.O(\m_axi_arlen[2]_INST_0_i_2_n_0 ));
LUT6 #(
.INIT(64'h00003777FFFFC888))
\m_axi_arlen[3]_INST_0
(.I0(\m_axi_arlen[3]_INST_0_i_1_n_0 ),
.I1(s_axi_arlen_ii[4]),
.I2(s_axi_arlen_ii[5]),
.I3(\m_axi_arlen[3]_INST_0_i_2_n_0 ),
.I4(\m_axi_arlen[7]_INST_0_i_1_n_0 ),
.I5(\m_axi_arlen[3]_INST_0_i_3_n_0 ),
.O(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29] [3]));
LUT6 #(
.INIT(64'h5540400000000000))
\m_axi_arlen[3]_INST_0_i_1
(.I0(\m_axi_araddr[1]_INST_0_i_5_n_0 ),
.I1(sr_araddr[1]),
.I2(s_axi_arlen_ii[0]),
.I3(s_axi_arlen_ii[1]),
.I4(sr_araddr[2]),
.I5(\m_axi_arlen[3]_INST_0_i_4_n_0 ),
.O(\m_axi_arlen[3]_INST_0_i_1_n_0 ));
LUT6 #(
.INIT(64'h4040400040000000))
\m_axi_arlen[3]_INST_0_i_2
(.I0(\m_axi_araddr[1]_INST_0_i_1_n_0 ),
.I1(\m_axi_arlen[3]_INST_0_i_5_n_0 ),
.I2(s_axi_arlen_ii[3]),
.I3(sr_araddr[2]),
.I4(s_axi_arlen_ii[2]),
.I5(\m_axi_arlen[3]_INST_0_i_6_n_0 ),
.O(\m_axi_arlen[3]_INST_0_i_2_n_0 ));
LUT5 #(
.INIT(32'hFFFFF888))
\m_axi_arlen[3]_INST_0_i_3
(.I0(s_axi_arlen_ii[3]),
.I1(\m_axi_arlen[7]_INST_0_i_2_n_0 ),
.I2(\m_axi_arlen[6]_INST_0_i_2_n_0 ),
.I3(s_axi_arlen_ii[4]),
.I4(\m_axi_arlen[3]_INST_0_i_7_n_0 ),
.O(\m_axi_arlen[3]_INST_0_i_3_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair66" *)
LUT5 #(
.INIT(32'h20000000))
\m_axi_arlen[3]_INST_0_i_4
(.I0(s_axi_arlen_ii[3]),
.I1(sr_arburst[1]),
.I2(sr_arburst[0]),
.I3(Q[33]),
.I4(s_axi_arlen_ii[2]),
.O(\m_axi_arlen[3]_INST_0_i_4_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair73" *)
LUT3 #(
.INIT(8'h40))
\m_axi_arlen[3]_INST_0_i_5
(.I0(sr_arburst[1]),
.I1(sr_arburst[0]),
.I2(Q[33]),
.O(\m_axi_arlen[3]_INST_0_i_5_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair67" *)
LUT4 #(
.INIT(16'hEA80))
\m_axi_arlen[3]_INST_0_i_6
(.I0(sr_araddr[1]),
.I1(s_axi_arlen_ii[0]),
.I2(sr_araddr[0]),
.I3(s_axi_arlen_ii[1]),
.O(\m_axi_arlen[3]_INST_0_i_6_n_0 ));
LUT6 #(
.INIT(64'h0000000000000A0C))
\m_axi_arlen[3]_INST_0_i_7
(.I0(s_axi_arlen_ii[5]),
.I1(s_axi_arlen_ii[6]),
.I2(\m_axi_arlen[7]_INST_0_i_2_n_0 ),
.I3(sr_arsize[0]),
.I4(sr_arsize[1]),
.I5(sr_arsize[2]),
.O(\m_axi_arlen[3]_INST_0_i_7_n_0 ));
LUT6 #(
.INIT(64'h5555566656665666))
\m_axi_arlen[4]_INST_0
(.I0(\m_axi_arlen[4]_INST_0_i_1_n_0 ),
.I1(\m_axi_arlen[4]_INST_0_i_2_n_0 ),
.I2(s_axi_arlen_ii[5]),
.I3(\m_axi_arlen[6]_INST_0_i_2_n_0 ),
.I4(\m_axi_arlen[7]_INST_0_i_2_n_0 ),
.I5(s_axi_arlen_ii[4]),
.O(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29] [4]));
LUT6 #(
.INIT(64'hFFFF0000F0800000))
\m_axi_arlen[4]_INST_0_i_1
(.I0(\m_axi_arlen[3]_INST_0_i_2_n_0 ),
.I1(s_axi_arlen_ii[6]),
.I2(s_axi_arlen_ii[5]),
.I3(\m_axi_arlen[3]_INST_0_i_1_n_0 ),
.I4(s_axi_arlen_ii[4]),
.I5(\m_axi_arlen[7]_INST_0_i_1_n_0 ),
.O(\m_axi_arlen[4]_INST_0_i_1_n_0 ));
LUT6 #(
.INIT(64'h0000000000000A0C))
\m_axi_arlen[4]_INST_0_i_2
(.I0(s_axi_arlen_ii[6]),
.I1(s_axi_arlen_ii[7]),
.I2(\m_axi_arlen[7]_INST_0_i_2_n_0 ),
.I3(sr_arsize[0]),
.I4(sr_arsize[1]),
.I5(sr_arsize[2]),
.O(\m_axi_arlen[4]_INST_0_i_2_n_0 ));
LUT6 #(
.INIT(64'h07070F0F07F8F0F0))
\m_axi_arlen[5]_INST_0
(.I0(\m_axi_arlen[7]_INST_0_i_1_n_0 ),
.I1(s_axi_arlen_ii[4]),
.I2(\m_axi_arlen[5]_INST_0_i_1_n_0 ),
.I3(\m_axi_arlen[7]_INST_0_i_2_n_0 ),
.I4(s_axi_arlen_ii[5]),
.I5(\m_axi_arlen[5]_INST_0_i_2_n_0 ),
.O(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29] [5]));
LUT6 #(
.INIT(64'hE0000000A0000000))
\m_axi_arlen[5]_INST_0_i_1
(.I0(\m_axi_arlen[3]_INST_0_i_1_n_0 ),
.I1(\m_axi_arlen[3]_INST_0_i_2_n_0 ),
.I2(s_axi_arlen_ii[6]),
.I3(s_axi_arlen_ii[4]),
.I4(s_axi_arlen_ii[5]),
.I5(s_axi_arlen_ii[7]),
.O(\m_axi_arlen[5]_INST_0_i_1_n_0 ));
LUT6 #(
.INIT(64'h00000000000A0C00))
\m_axi_arlen[5]_INST_0_i_2
(.I0(s_axi_arlen_ii[6]),
.I1(s_axi_arlen_ii[7]),
.I2(\m_axi_arlen[7]_INST_0_i_2_n_0 ),
.I3(sr_arsize[0]),
.I4(sr_arsize[1]),
.I5(sr_arsize[2]),
.O(\m_axi_arlen[5]_INST_0_i_2_n_0 ));
LUT5 #(
.INIT(32'h556A6A6A))
\m_axi_arlen[6]_INST_0
(.I0(\m_axi_arlen[6]_INST_0_i_1_n_0 ),
.I1(\m_axi_arlen[6]_INST_0_i_2_n_0 ),
.I2(s_axi_arlen_ii[7]),
.I3(\m_axi_arlen[7]_INST_0_i_2_n_0 ),
.I4(s_axi_arlen_ii[6]),
.O(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29] [6]));
LUT6 #(
.INIT(64'hE0000000A0000000))
\m_axi_arlen[6]_INST_0_i_1
(.I0(\m_axi_arlen[7]_INST_0_i_1_n_0 ),
.I1(\m_axi_arlen[3]_INST_0_i_1_n_0 ),
.I2(s_axi_arlen_ii[6]),
.I3(s_axi_arlen_ii[4]),
.I4(s_axi_arlen_ii[5]),
.I5(s_axi_arlen_ii[7]),
.O(\m_axi_arlen[6]_INST_0_i_1_n_0 ));
LUT6 #(
.INIT(64'h1000100010000000))
\m_axi_arlen[6]_INST_0_i_2
(.I0(sr_arsize[0]),
.I1(sr_arsize[2]),
.I2(sr_arsize[1]),
.I3(Q[33]),
.I4(sr_arburst[0]),
.I5(sr_arburst[1]),
.O(\m_axi_arlen[6]_INST_0_i_2_n_0 ));
LUT6 #(
.INIT(64'h7FFF000080000000))
\m_axi_arlen[7]_INST_0
(.I0(\m_axi_arlen[7]_INST_0_i_1_n_0 ),
.I1(s_axi_arlen_ii[6]),
.I2(s_axi_arlen_ii[4]),
.I3(s_axi_arlen_ii[5]),
.I4(s_axi_arlen_ii[7]),
.I5(\m_axi_arlen[7]_INST_0_i_2_n_0 ),
.O(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29] [7]));
LUT6 #(
.INIT(64'h0000800000000000))
\m_axi_arlen[7]_INST_0_i_1
(.I0(\m_axi_arlen[7]_INST_0_i_3_n_0 ),
.I1(s_axi_arlen_ii[2]),
.I2(Q[33]),
.I3(sr_arburst[0]),
.I4(sr_arburst[1]),
.I5(s_axi_arlen_ii[3]),
.O(\m_axi_arlen[7]_INST_0_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair72" *)
LUT3 #(
.INIT(8'h1F))
\m_axi_arlen[7]_INST_0_i_2
(.I0(sr_arburst[1]),
.I1(sr_arburst[0]),
.I2(Q[33]),
.O(\m_axi_arlen[7]_INST_0_i_2_n_0 ));
LUT6 #(
.INIT(64'h0000008000000000))
\m_axi_arlen[7]_INST_0_i_3
(.I0(sr_araddr[2]),
.I1(s_axi_arlen_ii[0]),
.I2(s_axi_arlen_ii[1]),
.I3(sr_arsize[0]),
.I4(sr_arsize[2]),
.I5(sr_arsize[1]),
.O(\m_axi_arlen[7]_INST_0_i_3_n_0 ));
LUT6 #(
.INIT(64'hAAAAAAAAFFFFFFFE))
\m_axi_arsize[0]_INST_0
(.I0(sr_arsize[0]),
.I1(s_axi_arlen_ii[2]),
.I2(\m_axi_araddr[1]_INST_0_i_2_n_0 ),
.I3(s_axi_arlen_ii[1]),
.I4(s_axi_arlen_ii[0]),
.I5(\m_axi_arlen[7]_INST_0_i_2_n_0 ),
.O(m_axi_arsize[0]));
LUT6 #(
.INIT(64'hAAAAAAAAFFFFFFFE))
\m_axi_arsize[1]_INST_0
(.I0(sr_arsize[1]),
.I1(s_axi_arlen_ii[2]),
.I2(\m_axi_araddr[1]_INST_0_i_2_n_0 ),
.I3(s_axi_arlen_ii[1]),
.I4(s_axi_arlen_ii[0]),
.I5(\m_axi_arlen[7]_INST_0_i_2_n_0 ),
.O(m_axi_arsize[1]));
LUT6 #(
.INIT(64'hFFFF000100000000))
\m_axi_arsize[2]_INST_0
(.I0(s_axi_arlen_ii[2]),
.I1(\m_axi_araddr[1]_INST_0_i_2_n_0 ),
.I2(s_axi_arlen_ii[1]),
.I3(s_axi_arlen_ii[0]),
.I4(\m_axi_arlen[7]_INST_0_i_2_n_0 ),
.I5(sr_arsize[2]),
.O(m_axi_arsize[2]));
LUT1 #(
.INIT(2'h1))
\m_payload_i[31]_i_1__0
(.I0(sr_arvalid),
.O(\m_payload_i[31]_i_1__0_n_0 ));
FDRE \m_payload_i_reg[0]
(.C(s_axi_aclk),
.CE(\m_payload_i[31]_i_1__0_n_0 ),
.D(\s_axi_arregion[3] [0]),
.Q(sr_araddr[0]),
.R(1'b0));
FDRE \m_payload_i_reg[10]
(.C(s_axi_aclk),
.CE(\m_payload_i[31]_i_1__0_n_0 ),
.D(\s_axi_arregion[3] [10]),
.Q(Q[7]),
.R(1'b0));
FDRE \m_payload_i_reg[11]
(.C(s_axi_aclk),
.CE(\m_payload_i[31]_i_1__0_n_0 ),
.D(\s_axi_arregion[3] [11]),
.Q(Q[8]),
.R(1'b0));
FDRE \m_payload_i_reg[12]
(.C(s_axi_aclk),
.CE(\m_payload_i[31]_i_1__0_n_0 ),
.D(\s_axi_arregion[3] [12]),
.Q(Q[9]),
.R(1'b0));
FDRE \m_payload_i_reg[13]
(.C(s_axi_aclk),
.CE(\m_payload_i[31]_i_1__0_n_0 ),
.D(\s_axi_arregion[3] [13]),
.Q(Q[10]),
.R(1'b0));
FDRE \m_payload_i_reg[14]
(.C(s_axi_aclk),
.CE(\m_payload_i[31]_i_1__0_n_0 ),
.D(\s_axi_arregion[3] [14]),
.Q(Q[11]),
.R(1'b0));
FDRE \m_payload_i_reg[15]
(.C(s_axi_aclk),
.CE(\m_payload_i[31]_i_1__0_n_0 ),
.D(\s_axi_arregion[3] [15]),
.Q(Q[12]),
.R(1'b0));
FDRE \m_payload_i_reg[16]
(.C(s_axi_aclk),
.CE(\m_payload_i[31]_i_1__0_n_0 ),
.D(\s_axi_arregion[3] [16]),
.Q(Q[13]),
.R(1'b0));
FDRE \m_payload_i_reg[17]
(.C(s_axi_aclk),
.CE(\m_payload_i[31]_i_1__0_n_0 ),
.D(\s_axi_arregion[3] [17]),
.Q(Q[14]),
.R(1'b0));
FDRE \m_payload_i_reg[18]
(.C(s_axi_aclk),
.CE(\m_payload_i[31]_i_1__0_n_0 ),
.D(\s_axi_arregion[3] [18]),
.Q(Q[15]),
.R(1'b0));
FDRE \m_payload_i_reg[19]
(.C(s_axi_aclk),
.CE(\m_payload_i[31]_i_1__0_n_0 ),
.D(\s_axi_arregion[3] [19]),
.Q(Q[16]),
.R(1'b0));
FDRE \m_payload_i_reg[1]
(.C(s_axi_aclk),
.CE(\m_payload_i[31]_i_1__0_n_0 ),
.D(\s_axi_arregion[3] [1]),
.Q(sr_araddr[1]),
.R(1'b0));
FDRE \m_payload_i_reg[20]
(.C(s_axi_aclk),
.CE(\m_payload_i[31]_i_1__0_n_0 ),
.D(\s_axi_arregion[3] [20]),
.Q(Q[17]),
.R(1'b0));
FDRE \m_payload_i_reg[21]
(.C(s_axi_aclk),
.CE(\m_payload_i[31]_i_1__0_n_0 ),
.D(\s_axi_arregion[3] [21]),
.Q(Q[18]),
.R(1'b0));
FDRE \m_payload_i_reg[22]
(.C(s_axi_aclk),
.CE(\m_payload_i[31]_i_1__0_n_0 ),
.D(\s_axi_arregion[3] [22]),
.Q(Q[19]),
.R(1'b0));
FDRE \m_payload_i_reg[23]
(.C(s_axi_aclk),
.CE(\m_payload_i[31]_i_1__0_n_0 ),
.D(\s_axi_arregion[3] [23]),
.Q(Q[20]),
.R(1'b0));
FDRE \m_payload_i_reg[24]
(.C(s_axi_aclk),
.CE(\m_payload_i[31]_i_1__0_n_0 ),
.D(\s_axi_arregion[3] [24]),
.Q(Q[21]),
.R(1'b0));
FDRE \m_payload_i_reg[25]
(.C(s_axi_aclk),
.CE(\m_payload_i[31]_i_1__0_n_0 ),
.D(\s_axi_arregion[3] [25]),
.Q(Q[22]),
.R(1'b0));
FDRE \m_payload_i_reg[26]
(.C(s_axi_aclk),
.CE(\m_payload_i[31]_i_1__0_n_0 ),
.D(\s_axi_arregion[3] [26]),
.Q(Q[23]),
.R(1'b0));
FDRE \m_payload_i_reg[27]
(.C(s_axi_aclk),
.CE(\m_payload_i[31]_i_1__0_n_0 ),
.D(\s_axi_arregion[3] [27]),
.Q(Q[24]),
.R(1'b0));
FDRE \m_payload_i_reg[28]
(.C(s_axi_aclk),
.CE(\m_payload_i[31]_i_1__0_n_0 ),
.D(\s_axi_arregion[3] [28]),
.Q(Q[25]),
.R(1'b0));
FDRE \m_payload_i_reg[29]
(.C(s_axi_aclk),
.CE(\m_payload_i[31]_i_1__0_n_0 ),
.D(\s_axi_arregion[3] [29]),
.Q(Q[26]),
.R(1'b0));
FDRE \m_payload_i_reg[2]
(.C(s_axi_aclk),
.CE(\m_payload_i[31]_i_1__0_n_0 ),
.D(\s_axi_arregion[3] [2]),
.Q(sr_araddr[2]),
.R(1'b0));
FDRE \m_payload_i_reg[30]
(.C(s_axi_aclk),
.CE(\m_payload_i[31]_i_1__0_n_0 ),
.D(\s_axi_arregion[3] [30]),
.Q(Q[27]),
.R(1'b0));
FDRE \m_payload_i_reg[31]
(.C(s_axi_aclk),
.CE(\m_payload_i[31]_i_1__0_n_0 ),
.D(\s_axi_arregion[3] [31]),
.Q(Q[28]),
.R(1'b0));
FDRE \m_payload_i_reg[32]
(.C(s_axi_aclk),
.CE(\m_payload_i[31]_i_1__0_n_0 ),
.D(\s_axi_arregion[3] [32]),
.Q(Q[29]),
.R(1'b0));
FDRE \m_payload_i_reg[33]
(.C(s_axi_aclk),
.CE(\m_payload_i[31]_i_1__0_n_0 ),
.D(\s_axi_arregion[3] [33]),
.Q(Q[30]),
.R(1'b0));
FDRE \m_payload_i_reg[34]
(.C(s_axi_aclk),
.CE(\m_payload_i[31]_i_1__0_n_0 ),
.D(\s_axi_arregion[3] [34]),
.Q(Q[31]),
.R(1'b0));
FDRE \m_payload_i_reg[35]
(.C(s_axi_aclk),
.CE(\m_payload_i[31]_i_1__0_n_0 ),
.D(\s_axi_arregion[3] [35]),
.Q(sr_arsize[0]),
.R(1'b0));
FDRE \m_payload_i_reg[36]
(.C(s_axi_aclk),
.CE(\m_payload_i[31]_i_1__0_n_0 ),
.D(\s_axi_arregion[3] [36]),
.Q(sr_arsize[1]),
.R(1'b0));
FDRE \m_payload_i_reg[37]
(.C(s_axi_aclk),
.CE(\m_payload_i[31]_i_1__0_n_0 ),
.D(\s_axi_arregion[3] [37]),
.Q(sr_arsize[2]),
.R(1'b0));
FDRE \m_payload_i_reg[38]
(.C(s_axi_aclk),
.CE(\m_payload_i[31]_i_1__0_n_0 ),
.D(\s_axi_arregion[3] [38]),
.Q(sr_arburst[0]),
.R(1'b0));
FDRE \m_payload_i_reg[39]
(.C(s_axi_aclk),
.CE(\m_payload_i[31]_i_1__0_n_0 ),
.D(\s_axi_arregion[3] [39]),
.Q(sr_arburst[1]),
.R(1'b0));
FDRE \m_payload_i_reg[3]
(.C(s_axi_aclk),
.CE(\m_payload_i[31]_i_1__0_n_0 ),
.D(\s_axi_arregion[3] [3]),
.Q(Q[0]),
.R(1'b0));
FDRE \m_payload_i_reg[40]
(.C(s_axi_aclk),
.CE(\m_payload_i[31]_i_1__0_n_0 ),
.D(\s_axi_arregion[3] [40]),
.Q(Q[32]),
.R(1'b0));
FDRE \m_payload_i_reg[41]
(.C(s_axi_aclk),
.CE(\m_payload_i[31]_i_1__0_n_0 ),
.D(\s_axi_arregion[3] [41]),
.Q(Q[33]),
.R(1'b0));
FDRE \m_payload_i_reg[42]
(.C(s_axi_aclk),
.CE(\m_payload_i[31]_i_1__0_n_0 ),
.D(\s_axi_arregion[3] [42]),
.Q(Q[34]),
.R(1'b0));
FDRE \m_payload_i_reg[43]
(.C(s_axi_aclk),
.CE(\m_payload_i[31]_i_1__0_n_0 ),
.D(\s_axi_arregion[3] [43]),
.Q(Q[35]),
.R(1'b0));
FDRE \m_payload_i_reg[44]
(.C(s_axi_aclk),
.CE(\m_payload_i[31]_i_1__0_n_0 ),
.D(\s_axi_arregion[3] [44]),
.Q(s_axi_arlen_ii[0]),
.R(1'b0));
FDRE \m_payload_i_reg[45]
(.C(s_axi_aclk),
.CE(\m_payload_i[31]_i_1__0_n_0 ),
.D(\s_axi_arregion[3] [45]),
.Q(s_axi_arlen_ii[1]),
.R(1'b0));
FDRE \m_payload_i_reg[46]
(.C(s_axi_aclk),
.CE(\m_payload_i[31]_i_1__0_n_0 ),
.D(\s_axi_arregion[3] [46]),
.Q(s_axi_arlen_ii[2]),
.R(1'b0));
FDRE \m_payload_i_reg[47]
(.C(s_axi_aclk),
.CE(\m_payload_i[31]_i_1__0_n_0 ),
.D(\s_axi_arregion[3] [47]),
.Q(s_axi_arlen_ii[3]),
.R(1'b0));
FDRE \m_payload_i_reg[48]
(.C(s_axi_aclk),
.CE(\m_payload_i[31]_i_1__0_n_0 ),
.D(\s_axi_arregion[3] [48]),
.Q(s_axi_arlen_ii[4]),
.R(1'b0));
FDRE \m_payload_i_reg[49]
(.C(s_axi_aclk),
.CE(\m_payload_i[31]_i_1__0_n_0 ),
.D(\s_axi_arregion[3] [49]),
.Q(s_axi_arlen_ii[5]),
.R(1'b0));
FDRE \m_payload_i_reg[4]
(.C(s_axi_aclk),
.CE(\m_payload_i[31]_i_1__0_n_0 ),
.D(\s_axi_arregion[3] [4]),
.Q(Q[1]),
.R(1'b0));
FDRE \m_payload_i_reg[50]
(.C(s_axi_aclk),
.CE(\m_payload_i[31]_i_1__0_n_0 ),
.D(\s_axi_arregion[3] [50]),
.Q(s_axi_arlen_ii[6]),
.R(1'b0));
FDRE \m_payload_i_reg[51]
(.C(s_axi_aclk),
.CE(\m_payload_i[31]_i_1__0_n_0 ),
.D(\s_axi_arregion[3] [51]),
.Q(s_axi_arlen_ii[7]),
.R(1'b0));
FDRE \m_payload_i_reg[52]
(.C(s_axi_aclk),
.CE(\m_payload_i[31]_i_1__0_n_0 ),
.D(\s_axi_arregion[3] [52]),
.Q(Q[36]),
.R(1'b0));
FDRE \m_payload_i_reg[54]
(.C(s_axi_aclk),
.CE(\m_payload_i[31]_i_1__0_n_0 ),
.D(\s_axi_arregion[3] [53]),
.Q(Q[37]),
.R(1'b0));
FDRE \m_payload_i_reg[55]
(.C(s_axi_aclk),
.CE(\m_payload_i[31]_i_1__0_n_0 ),
.D(\s_axi_arregion[3] [54]),
.Q(Q[38]),
.R(1'b0));
FDRE \m_payload_i_reg[56]
(.C(s_axi_aclk),
.CE(\m_payload_i[31]_i_1__0_n_0 ),
.D(\s_axi_arregion[3] [55]),
.Q(Q[39]),
.R(1'b0));
FDRE \m_payload_i_reg[57]
(.C(s_axi_aclk),
.CE(\m_payload_i[31]_i_1__0_n_0 ),
.D(\s_axi_arregion[3] [56]),
.Q(Q[40]),
.R(1'b0));
FDRE \m_payload_i_reg[58]
(.C(s_axi_aclk),
.CE(\m_payload_i[31]_i_1__0_n_0 ),
.D(\s_axi_arregion[3] [57]),
.Q(Q[41]),
.R(1'b0));
FDRE \m_payload_i_reg[59]
(.C(s_axi_aclk),
.CE(\m_payload_i[31]_i_1__0_n_0 ),
.D(\s_axi_arregion[3] [58]),
.Q(Q[42]),
.R(1'b0));
FDRE \m_payload_i_reg[5]
(.C(s_axi_aclk),
.CE(\m_payload_i[31]_i_1__0_n_0 ),
.D(\s_axi_arregion[3] [5]),
.Q(Q[2]),
.R(1'b0));
FDRE \m_payload_i_reg[60]
(.C(s_axi_aclk),
.CE(\m_payload_i[31]_i_1__0_n_0 ),
.D(\s_axi_arregion[3] [59]),
.Q(Q[43]),
.R(1'b0));
FDRE \m_payload_i_reg[61]
(.C(s_axi_aclk),
.CE(\m_payload_i[31]_i_1__0_n_0 ),
.D(\s_axi_arregion[3] [60]),
.Q(Q[44]),
.R(1'b0));
FDRE \m_payload_i_reg[6]
(.C(s_axi_aclk),
.CE(\m_payload_i[31]_i_1__0_n_0 ),
.D(\s_axi_arregion[3] [6]),
.Q(Q[3]),
.R(1'b0));
FDRE \m_payload_i_reg[7]
(.C(s_axi_aclk),
.CE(\m_payload_i[31]_i_1__0_n_0 ),
.D(\s_axi_arregion[3] [7]),
.Q(Q[4]),
.R(1'b0));
FDRE \m_payload_i_reg[8]
(.C(s_axi_aclk),
.CE(\m_payload_i[31]_i_1__0_n_0 ),
.D(\s_axi_arregion[3] [8]),
.Q(Q[5]),
.R(1'b0));
FDRE \m_payload_i_reg[9]
(.C(s_axi_aclk),
.CE(\m_payload_i[31]_i_1__0_n_0 ),
.D(\s_axi_arregion[3] [9]),
.Q(Q[6]),
.R(1'b0));
LUT4 #(
.INIT(16'hB100))
m_valid_i_i_1
(.I0(s_axi_arready),
.I1(cmd_push_block_reg),
.I2(s_axi_arvalid),
.I3(s_ready_i_reg_0),
.O(m_valid_i_i_1_n_0));
FDRE m_valid_i_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(m_valid_i_i_1_n_0),
.Q(sr_arvalid),
.R(1'b0));
LUT5 #(
.INIT(32'hDD5F0000))
s_ready_i_i_1
(.I0(s_ready_i_reg_0),
.I1(cmd_push_block_reg),
.I2(s_axi_arvalid),
.I3(sr_arvalid),
.I4(\aresetn_d_reg[0] ),
.O(s_ready_i_i_1_n_0));
FDRE s_ready_i_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_ready_i_i_1_n_0),
.Q(s_axi_arready),
.R(1'b0));
endmodule
|
module system_auto_us_0_axi_register_slice_v2_1_11_axic_register_slice_0
(\aresetn_d_reg[1] ,
sr_awvalid,
s_axi_awready,
\m_axi_awregion[3] ,
m_axi_awburst,
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[27] ,
m_axi_awaddr,
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28] ,
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[26] ,
in,
m_axi_awsize,
s_axi_aresetn,
s_axi_aclk,
cmd_push_block_reg,
s_axi_awvalid,
\aresetn_d_reg[1]_0 ,
D);
output \aresetn_d_reg[1] ;
output sr_awvalid;
output s_axi_awready;
output [41:0]\m_axi_awregion[3] ;
output [1:0]m_axi_awburst;
output \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[27] ;
output [5:0]m_axi_awaddr;
output \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28] ;
output \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[26] ;
output [24:0]in;
output [2:0]m_axi_awsize;
input s_axi_aresetn;
input s_axi_aclk;
input cmd_push_block_reg;
input s_axi_awvalid;
input \aresetn_d_reg[1]_0 ;
input [60:0]D;
wire [60:0]D;
wire \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[26] ;
wire \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[27] ;
wire \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28] ;
wire \USE_RTL_FIFO.data_srl_reg[31][18]_srl32_i_2_n_0 ;
wire \USE_RTL_FIFO.data_srl_reg[31][18]_srl32_i_3_n_0 ;
wire \USE_RTL_FIFO.data_srl_reg[31][19]_srl32_i_2_n_0 ;
wire \USE_RTL_FIFO.data_srl_reg[31][22]_srl32_i_2_n_0 ;
wire \aresetn_d_reg[1] ;
wire \aresetn_d_reg[1]_0 ;
wire cmd_push_block_reg;
wire [24:0]in;
wire [5:0]m_axi_awaddr;
wire \m_axi_awaddr[0]_INST_0_i_1_n_0 ;
wire \m_axi_awaddr[1]_INST_0_i_1_n_0 ;
wire \m_axi_awaddr[2]_INST_0_i_1_n_0 ;
wire \m_axi_awaddr[2]_INST_0_i_3_n_0 ;
wire \m_axi_awaddr[2]_INST_0_i_4_n_0 ;
wire \m_axi_awaddr[2]_INST_0_i_5_n_0 ;
wire \m_axi_awaddr[2]_INST_0_i_6_n_0 ;
wire \m_axi_awaddr[3]_INST_0_i_1_n_0 ;
wire \m_axi_awaddr[3]_INST_0_i_2_n_0 ;
wire \m_axi_awaddr[4]_INST_0_i_1_n_0 ;
wire \m_axi_awaddr[5]_INST_0_i_3_n_0 ;
wire \m_axi_awaddr[5]_INST_0_i_4_n_0 ;
wire \m_axi_awaddr[5]_INST_0_i_5_n_0 ;
wire \m_axi_awaddr[5]_INST_0_i_6_n_0 ;
wire \m_axi_awaddr[5]_INST_0_i_7_n_0 ;
wire \m_axi_awaddr[5]_INST_0_i_8_n_0 ;
wire \m_axi_awaddr[5]_INST_0_i_9_n_0 ;
wire [1:0]m_axi_awburst;
wire \m_axi_awlen[0]_INST_0_i_1_n_0 ;
wire \m_axi_awlen[0]_INST_0_i_2_n_0 ;
wire \m_axi_awlen[0]_INST_0_i_3_n_0 ;
wire \m_axi_awlen[3]_INST_0_i_1_n_0 ;
wire \m_axi_awlen[5]_INST_0_i_1_n_0 ;
wire \m_axi_awlen[5]_INST_0_i_2_n_0 ;
wire \m_axi_awlen[6]_INST_0_i_1_n_0 ;
wire \m_axi_awlen[6]_INST_0_i_2_n_0 ;
wire \m_axi_awlen[6]_INST_0_i_3_n_0 ;
wire \m_axi_awlen[6]_INST_0_i_4_n_0 ;
wire \m_axi_awlen[7]_INST_0_i_10_n_0 ;
wire \m_axi_awlen[7]_INST_0_i_11_n_0 ;
wire \m_axi_awlen[7]_INST_0_i_12_n_0 ;
wire \m_axi_awlen[7]_INST_0_i_13_n_0 ;
wire \m_axi_awlen[7]_INST_0_i_14_n_0 ;
wire \m_axi_awlen[7]_INST_0_i_15_n_0 ;
wire \m_axi_awlen[7]_INST_0_i_1_n_0 ;
wire \m_axi_awlen[7]_INST_0_i_2_n_0 ;
wire \m_axi_awlen[7]_INST_0_i_3_n_0 ;
wire \m_axi_awlen[7]_INST_0_i_4_n_0 ;
wire \m_axi_awlen[7]_INST_0_i_5_n_0 ;
wire \m_axi_awlen[7]_INST_0_i_6_n_0 ;
wire \m_axi_awlen[7]_INST_0_i_7_n_0 ;
wire \m_axi_awlen[7]_INST_0_i_8_n_0 ;
wire \m_axi_awlen[7]_INST_0_i_9_n_0 ;
wire [41:0]\m_axi_awregion[3] ;
wire [2:0]m_axi_awsize;
wire \m_payload_i[31]_i_1_n_0 ;
wire \m_payload_i_reg_n_0_[3] ;
wire \m_payload_i_reg_n_0_[4] ;
wire \m_payload_i_reg_n_0_[5] ;
wire m_valid_i_i_1__1_n_0;
wire s_axi_aclk;
wire s_axi_aresetn;
wire [7:0]s_axi_awlen_ii;
wire s_axi_awready;
wire s_axi_awvalid;
wire s_ready_i_i_1_n_0;
wire [2:0]sr_awaddr;
wire [1:0]sr_awburst;
wire [2:0]sr_awsize;
wire sr_awvalid;
(* SOFT_HLUTNM = "soft_lutpair81" *)
LUT3 #(
.INIT(8'h10))
\USE_RTL_FIFO.data_srl_reg[31][10]_srl32_i_1
(.I0(sr_awsize[0]),
.I1(sr_awsize[2]),
.I2(sr_awsize[1]),
.O(in[10]));
(* SOFT_HLUTNM = "soft_lutpair81" *)
LUT5 #(
.INIT(32'hAAAAAAAE))
\USE_RTL_FIFO.data_srl_reg[31][11]_srl32_i_1
(.I0(\m_axi_awaddr[2]_INST_0_i_6_n_0 ),
.I1(s_axi_awlen_ii[0]),
.I2(sr_awsize[0]),
.I3(sr_awsize[2]),
.I4(sr_awsize[1]),
.O(in[11]));
LUT6 #(
.INIT(64'hAAAAAAAAAAAAFEBA))
\USE_RTL_FIFO.data_srl_reg[31][12]_srl32_i_1
(.I0(\m_axi_awaddr[2]_INST_0_i_6_n_0 ),
.I1(sr_awsize[0]),
.I2(s_axi_awlen_ii[1]),
.I3(s_axi_awlen_ii[0]),
.I4(sr_awsize[1]),
.I5(sr_awsize[2]),
.O(in[12]));
LUT1 #(
.INIT(2'h1))
\USE_RTL_FIFO.data_srl_reg[31][13]_srl32_i_1
(.I0(\m_axi_awaddr[2]_INST_0_i_1_n_0 ),
.O(in[13]));
(* SOFT_HLUTNM = "soft_lutpair91" *)
LUT2 #(
.INIT(4'h8))
\USE_RTL_FIFO.data_srl_reg[31][16]_srl32_i_1
(.I0(\m_axi_awaddr[2]_INST_0_i_1_n_0 ),
.I1(sr_awaddr[2]),
.O(in[14]));
LUT6 #(
.INIT(64'h380038003800C800))
\USE_RTL_FIFO.data_srl_reg[31][17]_srl32_i_1
(.I0(\m_axi_awaddr[2]_INST_0_i_6_n_0 ),
.I1(sr_awaddr[0]),
.I2(s_axi_awlen_ii[0]),
.I3(in[8]),
.I4(sr_awburst[0]),
.I5(sr_awburst[1]),
.O(in[15]));
LUT6 #(
.INIT(64'h1414141141414144))
\USE_RTL_FIFO.data_srl_reg[31][18]_srl32_i_1
(.I0(\USE_RTL_FIFO.data_srl_reg[31][18]_srl32_i_2_n_0 ),
.I1(\USE_RTL_FIFO.data_srl_reg[31][18]_srl32_i_3_n_0 ),
.I2(\m_axi_awaddr[1]_INST_0_i_1_n_0 ),
.I3(sr_awburst[1]),
.I4(sr_awburst[0]),
.I5(sr_awaddr[1]),
.O(in[16]));
LUT6 #(
.INIT(64'h00100000FFFFFFFF))
\USE_RTL_FIFO.data_srl_reg[31][18]_srl32_i_2
(.I0(\m_axi_awaddr[5]_INST_0_i_7_n_0 ),
.I1(\m_axi_awaddr[2]_INST_0_i_4_n_0 ),
.I2(\m_axi_awaddr[2]_INST_0_i_3_n_0 ),
.I3(\m_axi_awaddr[5]_INST_0_i_4_n_0 ),
.I4(\m_axi_awaddr[1]_INST_0_i_1_n_0 ),
.I5(\m_axi_awaddr[0]_INST_0_i_1_n_0 ),
.O(\USE_RTL_FIFO.data_srl_reg[31][18]_srl32_i_2_n_0 ));
LUT6 #(
.INIT(64'h0000E00000000000))
\USE_RTL_FIFO.data_srl_reg[31][18]_srl32_i_3
(.I0(sr_awburst[0]),
.I1(sr_awburst[1]),
.I2(sr_awaddr[0]),
.I3(\m_axi_awaddr[0]_INST_0_i_1_n_0 ),
.I4(sr_awsize[0]),
.I5(s_axi_awlen_ii[0]),
.O(\USE_RTL_FIFO.data_srl_reg[31][18]_srl32_i_3_n_0 ));
LUT6 #(
.INIT(64'h03EFFC00FC0003EF))
\USE_RTL_FIFO.data_srl_reg[31][19]_srl32_i_1
(.I0(\m_axi_awaddr[5]_INST_0_i_6_n_0 ),
.I1(sr_awburst[0]),
.I2(sr_awburst[1]),
.I3(\m_axi_awaddr[2]_INST_0_i_5_n_0 ),
.I4(\m_axi_awlen[7]_INST_0_i_8_n_0 ),
.I5(\USE_RTL_FIFO.data_srl_reg[31][19]_srl32_i_2_n_0 ),
.O(in[17]));
(* SOFT_HLUTNM = "soft_lutpair77" *)
LUT2 #(
.INIT(4'hB))
\USE_RTL_FIFO.data_srl_reg[31][19]_srl32_i_2
(.I0(\m_axi_awaddr[2]_INST_0_i_1_n_0 ),
.I1(sr_awaddr[2]),
.O(\USE_RTL_FIFO.data_srl_reg[31][19]_srl32_i_2_n_0 ));
LUT6 #(
.INIT(64'h0000000001010100))
\USE_RTL_FIFO.data_srl_reg[31][20]_srl32_i_1
(.I0(sr_awsize[1]),
.I1(sr_awsize[2]),
.I2(sr_awsize[0]),
.I3(s_axi_awlen_ii[0]),
.I4(\m_axi_awaddr[2]_INST_0_i_6_n_0 ),
.I5(sr_awaddr[0]),
.O(in[18]));
LUT6 #(
.INIT(64'h4441444144414444))
\USE_RTL_FIFO.data_srl_reg[31][21]_srl32_i_1
(.I0(\USE_RTL_FIFO.data_srl_reg[31][18]_srl32_i_2_n_0 ),
.I1(sr_awaddr[1]),
.I2(sr_awsize[1]),
.I3(sr_awsize[2]),
.I4(sr_awsize[0]),
.I5(sr_awaddr[0]),
.O(in[19]));
LUT6 #(
.INIT(64'h4015151515404040))
\USE_RTL_FIFO.data_srl_reg[31][22]_srl32_i_1
(.I0(\m_axi_awaddr[2]_INST_0_i_1_n_0 ),
.I1(\USE_RTL_FIFO.data_srl_reg[31][22]_srl32_i_2_n_0 ),
.I2(sr_awaddr[1]),
.I3(\m_axi_awlen[6]_INST_0_i_4_n_0 ),
.I4(sr_awsize[1]),
.I5(sr_awaddr[2]),
.O(in[20]));
(* SOFT_HLUTNM = "soft_lutpair86" *)
LUT4 #(
.INIT(16'h000E))
\USE_RTL_FIFO.data_srl_reg[31][22]_srl32_i_2
(.I0(sr_awaddr[0]),
.I1(sr_awsize[0]),
.I2(sr_awsize[2]),
.I3(sr_awsize[1]),
.O(\USE_RTL_FIFO.data_srl_reg[31][22]_srl32_i_2_n_0 ));
LUT6 #(
.INIT(64'h0002000200020000))
\USE_RTL_FIFO.data_srl_reg[31][23]_srl32_i_1
(.I0(sr_awaddr[0]),
.I1(sr_awsize[1]),
.I2(sr_awsize[2]),
.I3(sr_awsize[0]),
.I4(s_axi_awlen_ii[0]),
.I5(\m_axi_awaddr[2]_INST_0_i_6_n_0 ),
.O(in[21]));
(* SOFT_HLUTNM = "soft_lutpair85" *)
LUT2 #(
.INIT(4'h2))
\USE_RTL_FIFO.data_srl_reg[31][24]_srl32_i_1
(.I0(sr_awaddr[1]),
.I1(\USE_RTL_FIFO.data_srl_reg[31][18]_srl32_i_2_n_0 ),
.O(in[22]));
(* SOFT_HLUTNM = "soft_lutpair91" *)
LUT2 #(
.INIT(4'h2))
\USE_RTL_FIFO.data_srl_reg[31][25]_srl32_i_1
(.I0(sr_awaddr[2]),
.I1(\m_axi_awaddr[2]_INST_0_i_1_n_0 ),
.O(in[23]));
(* SOFT_HLUTNM = "soft_lutpair90" *)
LUT2 #(
.INIT(4'h1))
\USE_RTL_FIFO.data_srl_reg[31][29]_srl32_i_1
(.I0(sr_awburst[0]),
.I1(sr_awburst[1]),
.O(in[24]));
(* SOFT_HLUTNM = "soft_lutpair80" *)
LUT3 #(
.INIT(8'h01))
\USE_RTL_FIFO.data_srl_reg[31][8]_srl32_i_1
(.I0(sr_awsize[1]),
.I1(sr_awsize[2]),
.I2(sr_awsize[0]),
.O(in[8]));
(* SOFT_HLUTNM = "soft_lutpair86" *)
LUT3 #(
.INIT(8'h02))
\USE_RTL_FIFO.data_srl_reg[31][9]_srl32_i_1
(.I0(sr_awsize[0]),
.I1(sr_awsize[2]),
.I2(sr_awsize[1]),
.O(in[9]));
FDRE #(
.INIT(1'b0))
\aresetn_d_reg[0]
(.C(s_axi_aclk),
.CE(1'b1),
.D(1'b1),
.Q(\aresetn_d_reg[1] ),
.R(s_axi_aresetn));
LUT6 #(
.INIT(64'h00000000A2AAAAAA))
\m_axi_awaddr[0]_INST_0
(.I0(sr_awaddr[0]),
.I1(\m_axi_awaddr[0]_INST_0_i_1_n_0 ),
.I2(sr_awsize[0]),
.I3(s_axi_awlen_ii[0]),
.I4(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[27] ),
.I5(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[26] ),
.O(m_axi_awaddr[0]));
(* SOFT_HLUTNM = "soft_lutpair76" *)
LUT2 #(
.INIT(4'h1))
\m_axi_awaddr[0]_INST_0_i_1
(.I0(sr_awsize[2]),
.I1(sr_awsize[1]),
.O(\m_axi_awaddr[0]_INST_0_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair85" *)
LUT4 #(
.INIT(16'h008A))
\m_axi_awaddr[1]_INST_0
(.I0(sr_awaddr[1]),
.I1(\m_axi_awaddr[1]_INST_0_i_1_n_0 ),
.I2(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[27] ),
.I3(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[26] ),
.O(m_axi_awaddr[1]));
(* SOFT_HLUTNM = "soft_lutpair79" *)
LUT5 #(
.INIT(32'hFFFFFF1B))
\m_axi_awaddr[1]_INST_0_i_1
(.I0(sr_awsize[0]),
.I1(s_axi_awlen_ii[1]),
.I2(s_axi_awlen_ii[0]),
.I3(sr_awsize[1]),
.I4(sr_awsize[2]),
.O(\m_axi_awaddr[1]_INST_0_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair77" *)
LUT5 #(
.INIT(32'h88008F00))
\m_axi_awaddr[2]_INST_0
(.I0(\m_axi_awaddr[2]_INST_0_i_1_n_0 ),
.I1(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28] ),
.I2(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[26] ),
.I3(sr_awaddr[2]),
.I4(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[27] ),
.O(m_axi_awaddr[2]));
LUT6 #(
.INIT(64'h0000000000000020))
\m_axi_awaddr[2]_INST_0_i_1
(.I0(sr_awburst[1]),
.I1(sr_awburst[0]),
.I2(\m_axi_awaddr[2]_INST_0_i_3_n_0 ),
.I3(\m_axi_awaddr[2]_INST_0_i_4_n_0 ),
.I4(\m_axi_awaddr[5]_INST_0_i_7_n_0 ),
.I5(\m_axi_awaddr[2]_INST_0_i_5_n_0 ),
.O(\m_axi_awaddr[2]_INST_0_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair93" *)
LUT2 #(
.INIT(4'h2))
\m_axi_awaddr[2]_INST_0_i_2
(.I0(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28] ),
.I1(\m_axi_awaddr[2]_INST_0_i_6_n_0 ),
.O(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[27] ));
(* SOFT_HLUTNM = "soft_lutpair79" *)
LUT5 #(
.INIT(32'h0033557F))
\m_axi_awaddr[2]_INST_0_i_3
(.I0(sr_awsize[1]),
.I1(s_axi_awlen_ii[0]),
.I2(sr_awsize[0]),
.I3(s_axi_awlen_ii[1]),
.I4(sr_awsize[2]),
.O(\m_axi_awaddr[2]_INST_0_i_3_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair82" *)
LUT4 #(
.INIT(16'hAAA8))
\m_axi_awaddr[2]_INST_0_i_4
(.I0(s_axi_awlen_ii[2]),
.I1(sr_awsize[0]),
.I2(sr_awsize[2]),
.I3(sr_awsize[1]),
.O(\m_axi_awaddr[2]_INST_0_i_4_n_0 ));
LUT6 #(
.INIT(64'h000F0A0C00000A0C))
\m_axi_awaddr[2]_INST_0_i_5
(.I0(s_axi_awlen_ii[1]),
.I1(s_axi_awlen_ii[2]),
.I2(sr_awsize[2]),
.I3(sr_awsize[0]),
.I4(sr_awsize[1]),
.I5(s_axi_awlen_ii[0]),
.O(\m_axi_awaddr[2]_INST_0_i_5_n_0 ));
LUT6 #(
.INIT(64'hFFFFAEFFFFFFFFFF))
\m_axi_awaddr[2]_INST_0_i_6
(.I0(\m_axi_awaddr[5]_INST_0_i_7_n_0 ),
.I1(s_axi_awlen_ii[2]),
.I2(in[8]),
.I3(\m_axi_awaddr[2]_INST_0_i_3_n_0 ),
.I4(sr_awburst[0]),
.I5(sr_awburst[1]),
.O(\m_axi_awaddr[2]_INST_0_i_6_n_0 ));
LUT6 #(
.INIT(64'hA9AAAAAA999AAAAA))
\m_axi_awaddr[3]_INST_0
(.I0(\m_payload_i_reg_n_0_[3] ),
.I1(sr_awsize[2]),
.I2(sr_awsize[1]),
.I3(\m_axi_awaddr[3]_INST_0_i_1_n_0 ),
.I4(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[26] ),
.I5(\m_axi_awaddr[3]_INST_0_i_2_n_0 ),
.O(m_axi_awaddr[3]));
(* SOFT_HLUTNM = "soft_lutpair89" *)
LUT3 #(
.INIT(8'hB8))
\m_axi_awaddr[3]_INST_0_i_1
(.I0(s_axi_awlen_ii[2]),
.I1(sr_awsize[0]),
.I2(s_axi_awlen_ii[3]),
.O(\m_axi_awaddr[3]_INST_0_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair88" *)
LUT3 #(
.INIT(8'h53))
\m_axi_awaddr[3]_INST_0_i_2
(.I0(s_axi_awlen_ii[0]),
.I1(s_axi_awlen_ii[1]),
.I2(sr_awsize[0]),
.O(\m_axi_awaddr[3]_INST_0_i_2_n_0 ));
LUT5 #(
.INIT(32'hAA6AAAAA))
\m_axi_awaddr[4]_INST_0
(.I0(\m_payload_i_reg_n_0_[4] ),
.I1(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28] ),
.I2(\m_payload_i_reg_n_0_[3] ),
.I3(\m_axi_awaddr[4]_INST_0_i_1_n_0 ),
.I4(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[26] ),
.O(m_axi_awaddr[4]));
LUT6 #(
.INIT(64'h8AAAA2A28AAAAAAA))
\m_axi_awaddr[4]_INST_0_i_1
(.I0(\m_axi_awlen[3]_INST_0_i_1_n_0 ),
.I1(sr_awsize[2]),
.I2(sr_awsize[0]),
.I3(s_axi_awlen_ii[1]),
.I4(sr_awsize[1]),
.I5(s_axi_awlen_ii[0]),
.O(\m_axi_awaddr[4]_INST_0_i_1_n_0 ));
LUT6 #(
.INIT(64'hAAAAAAAA6AAAAAAA))
\m_axi_awaddr[5]_INST_0
(.I0(\m_payload_i_reg_n_0_[5] ),
.I1(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[26] ),
.I2(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28] ),
.I3(\m_payload_i_reg_n_0_[3] ),
.I4(\m_payload_i_reg_n_0_[4] ),
.I5(\m_axi_awaddr[5]_INST_0_i_3_n_0 ),
.O(m_axi_awaddr[5]));
LUT6 #(
.INIT(64'h1010101010101000))
\m_axi_awaddr[5]_INST_0_i_1
(.I0(\m_axi_awaddr[5]_INST_0_i_4_n_0 ),
.I1(\m_axi_awaddr[5]_INST_0_i_5_n_0 ),
.I2(\m_axi_awaddr[5]_INST_0_i_6_n_0 ),
.I3(sr_awaddr[2]),
.I4(sr_awaddr[1]),
.I5(sr_awaddr[0]),
.O(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[26] ));
LUT6 #(
.INIT(64'h00000000AAAAAAA8))
\m_axi_awaddr[5]_INST_0_i_2
(.I0(\m_axi_awregion[3] [30]),
.I1(s_axi_awlen_ii[0]),
.I2(s_axi_awlen_ii[1]),
.I3(s_axi_awlen_ii[2]),
.I4(\m_axi_awaddr[5]_INST_0_i_7_n_0 ),
.I5(in[24]),
.O(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28] ));
(* SOFT_HLUTNM = "soft_lutpair76" *)
LUT5 #(
.INIT(32'h30233323))
\m_axi_awaddr[5]_INST_0_i_3
(.I0(\m_axi_awaddr[3]_INST_0_i_2_n_0 ),
.I1(\m_axi_awaddr[5]_INST_0_i_8_n_0 ),
.I2(sr_awsize[2]),
.I3(sr_awsize[1]),
.I4(\m_axi_awaddr[3]_INST_0_i_1_n_0 ),
.O(\m_axi_awaddr[5]_INST_0_i_3_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair92" *)
LUT2 #(
.INIT(4'hB))
\m_axi_awaddr[5]_INST_0_i_4
(.I0(sr_awburst[0]),
.I1(sr_awburst[1]),
.O(\m_axi_awaddr[5]_INST_0_i_4_n_0 ));
LUT5 #(
.INIT(32'h0001FFFF))
\m_axi_awaddr[5]_INST_0_i_5
(.I0(\m_axi_awaddr[5]_INST_0_i_7_n_0 ),
.I1(s_axi_awlen_ii[2]),
.I2(s_axi_awlen_ii[1]),
.I3(s_axi_awlen_ii[0]),
.I4(\m_axi_awregion[3] [30]),
.O(\m_axi_awaddr[5]_INST_0_i_5_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFFFFFFFFFE))
\m_axi_awaddr[5]_INST_0_i_6
(.I0(s_axi_awlen_ii[6]),
.I1(s_axi_awlen_ii[5]),
.I2(s_axi_awlen_ii[3]),
.I3(s_axi_awlen_ii[4]),
.I4(s_axi_awlen_ii[7]),
.I5(\m_axi_awaddr[5]_INST_0_i_9_n_0 ),
.O(\m_axi_awaddr[5]_INST_0_i_6_n_0 ));
LUT5 #(
.INIT(32'hFFFFFFFE))
\m_axi_awaddr[5]_INST_0_i_7
(.I0(s_axi_awlen_ii[3]),
.I1(s_axi_awlen_ii[7]),
.I2(s_axi_awlen_ii[6]),
.I3(s_axi_awlen_ii[4]),
.I4(s_axi_awlen_ii[5]),
.O(\m_axi_awaddr[5]_INST_0_i_7_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair80" *)
LUT5 #(
.INIT(32'h000A000C))
\m_axi_awaddr[5]_INST_0_i_8
(.I0(s_axi_awlen_ii[4]),
.I1(s_axi_awlen_ii[5]),
.I2(sr_awsize[1]),
.I3(sr_awsize[2]),
.I4(sr_awsize[0]),
.O(\m_axi_awaddr[5]_INST_0_i_8_n_0 ));
LUT6 #(
.INIT(64'hFFFFFAFAEECCEA88))
\m_axi_awaddr[5]_INST_0_i_9
(.I0(s_axi_awlen_ii[2]),
.I1(sr_awsize[1]),
.I2(s_axi_awlen_ii[0]),
.I3(sr_awsize[0]),
.I4(s_axi_awlen_ii[1]),
.I5(sr_awsize[2]),
.O(\m_axi_awaddr[5]_INST_0_i_9_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair92" *)
LUT2 #(
.INIT(4'hE))
\m_axi_awburst[0]_INST_0
(.I0(sr_awburst[0]),
.I1(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[27] ),
.O(m_axi_awburst[0]));
(* SOFT_HLUTNM = "soft_lutpair90" *)
LUT2 #(
.INIT(4'h2))
\m_axi_awburst[1]_INST_0
(.I0(sr_awburst[1]),
.I1(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[27] ),
.O(m_axi_awburst[1]));
(* SOFT_HLUTNM = "soft_lutpair83" *)
LUT4 #(
.INIT(16'h9599))
\m_axi_awlen[0]_INST_0
(.I0(\m_axi_awlen[0]_INST_0_i_1_n_0 ),
.I1(\m_axi_awlen[0]_INST_0_i_2_n_0 ),
.I2(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28] ),
.I3(s_axi_awlen_ii[0]),
.O(in[0]));
LUT6 #(
.INIT(64'h0000FFFF0000E000))
\m_axi_awlen[0]_INST_0_i_1
(.I0(sr_awburst[0]),
.I1(sr_awburst[1]),
.I2(\m_axi_awaddr[2]_INST_0_i_5_n_0 ),
.I3(sr_awaddr[2]),
.I4(\m_axi_awlen[7]_INST_0_i_9_n_0 ),
.I5(\m_axi_awlen[7]_INST_0_i_8_n_0 ),
.O(\m_axi_awlen[0]_INST_0_i_1_n_0 ));
LUT6 #(
.INIT(64'h575F5757575F5F5F))
\m_axi_awlen[0]_INST_0_i_2
(.I0(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28] ),
.I1(\m_axi_awlen[6]_INST_0_i_4_n_0 ),
.I2(\m_axi_awlen[0]_INST_0_i_3_n_0 ),
.I3(s_axi_awlen_ii[1]),
.I4(sr_awsize[1]),
.I5(s_axi_awlen_ii[3]),
.O(\m_axi_awlen[0]_INST_0_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair82" *)
LUT4 #(
.INIT(16'h0008))
\m_axi_awlen[0]_INST_0_i_3
(.I0(s_axi_awlen_ii[2]),
.I1(sr_awsize[0]),
.I2(sr_awsize[2]),
.I3(sr_awsize[1]),
.O(\m_axi_awlen[0]_INST_0_i_3_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair75" *)
LUT4 #(
.INIT(16'h959A))
\m_axi_awlen[1]_INST_0
(.I0(\m_axi_awlen[5]_INST_0_i_1_n_0 ),
.I1(\m_axi_awlen[3]_INST_0_i_1_n_0 ),
.I2(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28] ),
.I3(s_axi_awlen_ii[1]),
.O(in[1]));
(* SOFT_HLUTNM = "soft_lutpair75" *)
LUT5 #(
.INIT(32'hD1FF2E00))
\m_axi_awlen[2]_INST_0
(.I0(s_axi_awlen_ii[1]),
.I1(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28] ),
.I2(\m_axi_awlen[3]_INST_0_i_1_n_0 ),
.I3(\m_axi_awlen[5]_INST_0_i_1_n_0 ),
.I4(\m_axi_awlen[6]_INST_0_i_2_n_0 ),
.O(in[2]));
LUT6 #(
.INIT(64'h08880800F777F7FF))
\m_axi_awlen[3]_INST_0
(.I0(\m_axi_awlen[6]_INST_0_i_2_n_0 ),
.I1(\m_axi_awlen[5]_INST_0_i_1_n_0 ),
.I2(\m_axi_awlen[3]_INST_0_i_1_n_0 ),
.I3(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28] ),
.I4(s_axi_awlen_ii[1]),
.I5(\m_axi_awlen[7]_INST_0_i_4_n_0 ),
.O(in[3]));
LUT6 #(
.INIT(64'hFCCDFCFDFFCDFFFD))
\m_axi_awlen[3]_INST_0_i_1
(.I0(s_axi_awlen_ii[4]),
.I1(sr_awsize[2]),
.I2(sr_awsize[0]),
.I3(sr_awsize[1]),
.I4(s_axi_awlen_ii[3]),
.I5(s_axi_awlen_ii[2]),
.O(\m_axi_awlen[3]_INST_0_i_1_n_0 ));
LUT5 #(
.INIT(32'hBFFF4000))
\m_axi_awlen[4]_INST_0
(.I0(\m_axi_awlen[7]_INST_0_i_4_n_0 ),
.I1(\m_axi_awlen[5]_INST_0_i_2_n_0 ),
.I2(\m_axi_awlen[5]_INST_0_i_1_n_0 ),
.I3(\m_axi_awlen[6]_INST_0_i_2_n_0 ),
.I4(\m_axi_awlen[7]_INST_0_i_2_n_0 ),
.O(in[4]));
LUT6 #(
.INIT(64'hFFFF7FFF00008000))
\m_axi_awlen[5]_INST_0
(.I0(\m_axi_awlen[7]_INST_0_i_2_n_0 ),
.I1(\m_axi_awlen[6]_INST_0_i_2_n_0 ),
.I2(\m_axi_awlen[5]_INST_0_i_1_n_0 ),
.I3(\m_axi_awlen[5]_INST_0_i_2_n_0 ),
.I4(\m_axi_awlen[7]_INST_0_i_4_n_0 ),
.I5(\m_axi_awlen[7]_INST_0_i_5_n_0 ),
.O(in[5]));
LUT5 #(
.INIT(32'h00003222))
\m_axi_awlen[5]_INST_0_i_1
(.I0(\m_axi_awlen[7]_INST_0_i_8_n_0 ),
.I1(\m_axi_awlen[7]_INST_0_i_9_n_0 ),
.I2(sr_awaddr[2]),
.I3(\m_axi_awlen[6]_INST_0_i_3_n_0 ),
.I4(\m_axi_awlen[7]_INST_0_i_11_n_0 ),
.O(\m_axi_awlen[5]_INST_0_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair88" *)
LUT3 #(
.INIT(8'h2E))
\m_axi_awlen[5]_INST_0_i_2
(.I0(s_axi_awlen_ii[1]),
.I1(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28] ),
.I2(\m_axi_awlen[3]_INST_0_i_1_n_0 ),
.O(\m_axi_awlen[5]_INST_0_i_2_n_0 ));
LUT6 #(
.INIT(64'h20000000DFFFFFFF))
\m_axi_awlen[6]_INST_0
(.I0(\m_axi_awlen[7]_INST_0_i_5_n_0 ),
.I1(\m_axi_awlen[7]_INST_0_i_4_n_0 ),
.I2(\m_axi_awlen[6]_INST_0_i_1_n_0 ),
.I3(\m_axi_awlen[6]_INST_0_i_2_n_0 ),
.I4(\m_axi_awlen[7]_INST_0_i_2_n_0 ),
.I5(\m_axi_awlen[7]_INST_0_i_1_n_0 ),
.O(in[6]));
LUT6 #(
.INIT(64'h0055004000000000))
\m_axi_awlen[6]_INST_0_i_1
(.I0(\m_axi_awlen[7]_INST_0_i_11_n_0 ),
.I1(\m_axi_awlen[6]_INST_0_i_3_n_0 ),
.I2(sr_awaddr[2]),
.I3(\m_axi_awlen[7]_INST_0_i_9_n_0 ),
.I4(\m_axi_awlen[7]_INST_0_i_8_n_0 ),
.I5(\m_axi_awlen[5]_INST_0_i_2_n_0 ),
.O(\m_axi_awlen[6]_INST_0_i_1_n_0 ));
LUT6 #(
.INIT(64'hFACACACACACACACA))
\m_axi_awlen[6]_INST_0_i_2
(.I0(s_axi_awlen_ii[2]),
.I1(\m_axi_awaddr[5]_INST_0_i_8_n_0 ),
.I2(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28] ),
.I3(sr_awsize[1]),
.I4(\m_axi_awlen[6]_INST_0_i_4_n_0 ),
.I5(s_axi_awlen_ii[3]),
.O(\m_axi_awlen[6]_INST_0_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair84" *)
LUT3 #(
.INIT(8'hA8))
\m_axi_awlen[6]_INST_0_i_3
(.I0(\m_axi_awaddr[2]_INST_0_i_5_n_0 ),
.I1(sr_awburst[1]),
.I2(sr_awburst[0]),
.O(\m_axi_awlen[6]_INST_0_i_3_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair89" *)
LUT2 #(
.INIT(4'h1))
\m_axi_awlen[6]_INST_0_i_4
(.I0(sr_awsize[2]),
.I1(sr_awsize[0]),
.O(\m_axi_awlen[6]_INST_0_i_4_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFF00040000))
\m_axi_awlen[7]_INST_0
(.I0(\m_axi_awlen[7]_INST_0_i_1_n_0 ),
.I1(\m_axi_awlen[7]_INST_0_i_2_n_0 ),
.I2(\m_axi_awlen[7]_INST_0_i_3_n_0 ),
.I3(\m_axi_awlen[7]_INST_0_i_4_n_0 ),
.I4(\m_axi_awlen[7]_INST_0_i_5_n_0 ),
.I5(\m_axi_awlen[7]_INST_0_i_6_n_0 ),
.O(in[7]));
LUT6 #(
.INIT(64'hFFF3FFFF55555555))
\m_axi_awlen[7]_INST_0_i_1
(.I0(s_axi_awlen_ii[6]),
.I1(sr_awsize[1]),
.I2(sr_awsize[2]),
.I3(sr_awsize[0]),
.I4(s_axi_awlen_ii[7]),
.I5(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28] ),
.O(\m_axi_awlen[7]_INST_0_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair84" *)
LUT4 #(
.INIT(16'hE000))
\m_axi_awlen[7]_INST_0_i_10
(.I0(sr_awburst[0]),
.I1(sr_awburst[1]),
.I2(\m_axi_awaddr[2]_INST_0_i_5_n_0 ),
.I3(sr_awaddr[2]),
.O(\m_axi_awlen[7]_INST_0_i_10_n_0 ));
LUT6 #(
.INIT(64'hDDDDDDDD1111D1DD))
\m_axi_awlen[7]_INST_0_i_11
(.I0(s_axi_awlen_ii[0]),
.I1(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28] ),
.I2(\m_axi_awlen[7]_INST_0_i_13_n_0 ),
.I3(s_axi_awlen_ii[2]),
.I4(\m_axi_awlen[6]_INST_0_i_4_n_0 ),
.I5(\m_axi_awlen[7]_INST_0_i_15_n_0 ),
.O(\m_axi_awlen[7]_INST_0_i_11_n_0 ));
LUT6 #(
.INIT(64'hFFFFF3F3F5F5F0FF))
\m_axi_awlen[7]_INST_0_i_12
(.I0(s_axi_awlen_ii[4]),
.I1(s_axi_awlen_ii[5]),
.I2(sr_awsize[2]),
.I3(s_axi_awlen_ii[6]),
.I4(sr_awsize[1]),
.I5(sr_awsize[0]),
.O(\m_axi_awlen[7]_INST_0_i_12_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair78" *)
LUT3 #(
.INIT(8'hEF))
\m_axi_awlen[7]_INST_0_i_13
(.I0(sr_awsize[1]),
.I1(sr_awsize[2]),
.I2(sr_awsize[0]),
.O(\m_axi_awlen[7]_INST_0_i_13_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair78" *)
LUT5 #(
.INIT(32'h03080008))
\m_axi_awlen[7]_INST_0_i_14
(.I0(s_axi_awlen_ii[5]),
.I1(sr_awsize[1]),
.I2(sr_awsize[2]),
.I3(sr_awsize[0]),
.I4(s_axi_awlen_ii[6]),
.O(\m_axi_awlen[7]_INST_0_i_14_n_0 ));
LUT6 #(
.INIT(64'h3530353535353535))
\m_axi_awlen[7]_INST_0_i_15
(.I0(s_axi_awlen_ii[3]),
.I1(s_axi_awlen_ii[1]),
.I2(sr_awsize[1]),
.I3(sr_awsize[2]),
.I4(sr_awsize[0]),
.I5(s_axi_awlen_ii[2]),
.O(\m_axi_awlen[7]_INST_0_i_15_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair87" *)
LUT3 #(
.INIT(8'hE0))
\m_axi_awlen[7]_INST_0_i_2
(.I0(s_axi_awlen_ii[4]),
.I1(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28] ),
.I2(\m_axi_awlen[7]_INST_0_i_7_n_0 ),
.O(\m_axi_awlen[7]_INST_0_i_2_n_0 ));
LUT6 #(
.INIT(64'hFFFFF5F7FFFFFFFF))
\m_axi_awlen[7]_INST_0_i_3
(.I0(\m_axi_awlen[5]_INST_0_i_2_n_0 ),
.I1(\m_axi_awlen[7]_INST_0_i_8_n_0 ),
.I2(\m_axi_awlen[7]_INST_0_i_9_n_0 ),
.I3(\m_axi_awlen[7]_INST_0_i_10_n_0 ),
.I4(\m_axi_awlen[7]_INST_0_i_11_n_0 ),
.I5(\m_axi_awlen[6]_INST_0_i_2_n_0 ),
.O(\m_axi_awlen[7]_INST_0_i_3_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair87" *)
LUT3 #(
.INIT(8'h8B))
\m_axi_awlen[7]_INST_0_i_4
(.I0(\m_axi_awlen[7]_INST_0_i_12_n_0 ),
.I1(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28] ),
.I2(s_axi_awlen_ii[3]),
.O(\m_axi_awlen[7]_INST_0_i_4_n_0 ));
LUT6 #(
.INIT(64'hE222EEEEE222E222))
\m_axi_awlen[7]_INST_0_i_5
(.I0(s_axi_awlen_ii[5]),
.I1(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28] ),
.I2(in[10]),
.I3(s_axi_awlen_ii[6]),
.I4(\m_axi_awlen[7]_INST_0_i_13_n_0 ),
.I5(s_axi_awlen_ii[7]),
.O(\m_axi_awlen[7]_INST_0_i_5_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair83" *)
LUT2 #(
.INIT(4'h2))
\m_axi_awlen[7]_INST_0_i_6
(.I0(s_axi_awlen_ii[7]),
.I1(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28] ),
.O(\m_axi_awlen[7]_INST_0_i_6_n_0 ));
LUT6 #(
.INIT(64'hBBBBBBBBBBBBBFBB))
\m_axi_awlen[7]_INST_0_i_7
(.I0(\m_axi_awlen[7]_INST_0_i_14_n_0 ),
.I1(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28] ),
.I2(sr_awsize[1]),
.I3(s_axi_awlen_ii[7]),
.I4(sr_awsize[0]),
.I5(sr_awsize[2]),
.O(\m_axi_awlen[7]_INST_0_i_7_n_0 ));
LUT6 #(
.INIT(64'h08AE08AE08AE0808))
\m_axi_awlen[7]_INST_0_i_8
(.I0(\USE_RTL_FIFO.data_srl_reg[31][18]_srl32_i_3_n_0 ),
.I1(sr_awaddr[1]),
.I2(\USE_RTL_FIFO.data_srl_reg[31][18]_srl32_i_2_n_0 ),
.I3(\m_axi_awaddr[1]_INST_0_i_1_n_0 ),
.I4(sr_awburst[1]),
.I5(sr_awburst[0]),
.O(\m_axi_awlen[7]_INST_0_i_8_n_0 ));
LUT6 #(
.INIT(64'hFBFFFAFFFBFFFBFF))
\m_axi_awlen[7]_INST_0_i_9
(.I0(\m_axi_awaddr[5]_INST_0_i_5_n_0 ),
.I1(\m_axi_awaddr[2]_INST_0_i_5_n_0 ),
.I2(sr_awburst[1]),
.I3(sr_awburst[0]),
.I4(\m_axi_awaddr[2]_INST_0_i_1_n_0 ),
.I5(sr_awaddr[2]),
.O(\m_axi_awlen[7]_INST_0_i_9_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair94" *)
LUT2 #(
.INIT(4'hE))
\m_axi_awsize[0]_INST_0
(.I0(sr_awsize[0]),
.I1(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28] ),
.O(m_axi_awsize[0]));
(* SOFT_HLUTNM = "soft_lutpair94" *)
LUT2 #(
.INIT(4'hE))
\m_axi_awsize[1]_INST_0
(.I0(sr_awsize[1]),
.I1(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28] ),
.O(m_axi_awsize[1]));
(* SOFT_HLUTNM = "soft_lutpair93" *)
LUT2 #(
.INIT(4'h2))
\m_axi_awsize[2]_INST_0
(.I0(sr_awsize[2]),
.I1(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28] ),
.O(m_axi_awsize[2]));
LUT1 #(
.INIT(2'h1))
\m_payload_i[31]_i_1
(.I0(sr_awvalid),
.O(\m_payload_i[31]_i_1_n_0 ));
FDRE \m_payload_i_reg[0]
(.C(s_axi_aclk),
.CE(\m_payload_i[31]_i_1_n_0 ),
.D(D[0]),
.Q(sr_awaddr[0]),
.R(1'b0));
FDRE \m_payload_i_reg[10]
(.C(s_axi_aclk),
.CE(\m_payload_i[31]_i_1_n_0 ),
.D(D[10]),
.Q(\m_axi_awregion[3] [4]),
.R(1'b0));
FDRE \m_payload_i_reg[11]
(.C(s_axi_aclk),
.CE(\m_payload_i[31]_i_1_n_0 ),
.D(D[11]),
.Q(\m_axi_awregion[3] [5]),
.R(1'b0));
FDRE \m_payload_i_reg[12]
(.C(s_axi_aclk),
.CE(\m_payload_i[31]_i_1_n_0 ),
.D(D[12]),
.Q(\m_axi_awregion[3] [6]),
.R(1'b0));
FDRE \m_payload_i_reg[13]
(.C(s_axi_aclk),
.CE(\m_payload_i[31]_i_1_n_0 ),
.D(D[13]),
.Q(\m_axi_awregion[3] [7]),
.R(1'b0));
FDRE \m_payload_i_reg[14]
(.C(s_axi_aclk),
.CE(\m_payload_i[31]_i_1_n_0 ),
.D(D[14]),
.Q(\m_axi_awregion[3] [8]),
.R(1'b0));
FDRE \m_payload_i_reg[15]
(.C(s_axi_aclk),
.CE(\m_payload_i[31]_i_1_n_0 ),
.D(D[15]),
.Q(\m_axi_awregion[3] [9]),
.R(1'b0));
FDRE \m_payload_i_reg[16]
(.C(s_axi_aclk),
.CE(\m_payload_i[31]_i_1_n_0 ),
.D(D[16]),
.Q(\m_axi_awregion[3] [10]),
.R(1'b0));
FDRE \m_payload_i_reg[17]
(.C(s_axi_aclk),
.CE(\m_payload_i[31]_i_1_n_0 ),
.D(D[17]),
.Q(\m_axi_awregion[3] [11]),
.R(1'b0));
FDRE \m_payload_i_reg[18]
(.C(s_axi_aclk),
.CE(\m_payload_i[31]_i_1_n_0 ),
.D(D[18]),
.Q(\m_axi_awregion[3] [12]),
.R(1'b0));
FDRE \m_payload_i_reg[19]
(.C(s_axi_aclk),
.CE(\m_payload_i[31]_i_1_n_0 ),
.D(D[19]),
.Q(\m_axi_awregion[3] [13]),
.R(1'b0));
FDRE \m_payload_i_reg[1]
(.C(s_axi_aclk),
.CE(\m_payload_i[31]_i_1_n_0 ),
.D(D[1]),
.Q(sr_awaddr[1]),
.R(1'b0));
FDRE \m_payload_i_reg[20]
(.C(s_axi_aclk),
.CE(\m_payload_i[31]_i_1_n_0 ),
.D(D[20]),
.Q(\m_axi_awregion[3] [14]),
.R(1'b0));
FDRE \m_payload_i_reg[21]
(.C(s_axi_aclk),
.CE(\m_payload_i[31]_i_1_n_0 ),
.D(D[21]),
.Q(\m_axi_awregion[3] [15]),
.R(1'b0));
FDRE \m_payload_i_reg[22]
(.C(s_axi_aclk),
.CE(\m_payload_i[31]_i_1_n_0 ),
.D(D[22]),
.Q(\m_axi_awregion[3] [16]),
.R(1'b0));
FDRE \m_payload_i_reg[23]
(.C(s_axi_aclk),
.CE(\m_payload_i[31]_i_1_n_0 ),
.D(D[23]),
.Q(\m_axi_awregion[3] [17]),
.R(1'b0));
FDRE \m_payload_i_reg[24]
(.C(s_axi_aclk),
.CE(\m_payload_i[31]_i_1_n_0 ),
.D(D[24]),
.Q(\m_axi_awregion[3] [18]),
.R(1'b0));
FDRE \m_payload_i_reg[25]
(.C(s_axi_aclk),
.CE(\m_payload_i[31]_i_1_n_0 ),
.D(D[25]),
.Q(\m_axi_awregion[3] [19]),
.R(1'b0));
FDRE \m_payload_i_reg[26]
(.C(s_axi_aclk),
.CE(\m_payload_i[31]_i_1_n_0 ),
.D(D[26]),
.Q(\m_axi_awregion[3] [20]),
.R(1'b0));
FDRE \m_payload_i_reg[27]
(.C(s_axi_aclk),
.CE(\m_payload_i[31]_i_1_n_0 ),
.D(D[27]),
.Q(\m_axi_awregion[3] [21]),
.R(1'b0));
FDRE \m_payload_i_reg[28]
(.C(s_axi_aclk),
.CE(\m_payload_i[31]_i_1_n_0 ),
.D(D[28]),
.Q(\m_axi_awregion[3] [22]),
.R(1'b0));
FDRE \m_payload_i_reg[29]
(.C(s_axi_aclk),
.CE(\m_payload_i[31]_i_1_n_0 ),
.D(D[29]),
.Q(\m_axi_awregion[3] [23]),
.R(1'b0));
FDRE \m_payload_i_reg[2]
(.C(s_axi_aclk),
.CE(\m_payload_i[31]_i_1_n_0 ),
.D(D[2]),
.Q(sr_awaddr[2]),
.R(1'b0));
FDRE \m_payload_i_reg[30]
(.C(s_axi_aclk),
.CE(\m_payload_i[31]_i_1_n_0 ),
.D(D[30]),
.Q(\m_axi_awregion[3] [24]),
.R(1'b0));
FDRE \m_payload_i_reg[31]
(.C(s_axi_aclk),
.CE(\m_payload_i[31]_i_1_n_0 ),
.D(D[31]),
.Q(\m_axi_awregion[3] [25]),
.R(1'b0));
FDRE \m_payload_i_reg[32]
(.C(s_axi_aclk),
.CE(\m_payload_i[31]_i_1_n_0 ),
.D(D[32]),
.Q(\m_axi_awregion[3] [26]),
.R(1'b0));
FDRE \m_payload_i_reg[33]
(.C(s_axi_aclk),
.CE(\m_payload_i[31]_i_1_n_0 ),
.D(D[33]),
.Q(\m_axi_awregion[3] [27]),
.R(1'b0));
FDRE \m_payload_i_reg[34]
(.C(s_axi_aclk),
.CE(\m_payload_i[31]_i_1_n_0 ),
.D(D[34]),
.Q(\m_axi_awregion[3] [28]),
.R(1'b0));
FDRE \m_payload_i_reg[35]
(.C(s_axi_aclk),
.CE(\m_payload_i[31]_i_1_n_0 ),
.D(D[35]),
.Q(sr_awsize[0]),
.R(1'b0));
FDRE \m_payload_i_reg[36]
(.C(s_axi_aclk),
.CE(\m_payload_i[31]_i_1_n_0 ),
.D(D[36]),
.Q(sr_awsize[1]),
.R(1'b0));
FDRE \m_payload_i_reg[37]
(.C(s_axi_aclk),
.CE(\m_payload_i[31]_i_1_n_0 ),
.D(D[37]),
.Q(sr_awsize[2]),
.R(1'b0));
FDRE \m_payload_i_reg[38]
(.C(s_axi_aclk),
.CE(\m_payload_i[31]_i_1_n_0 ),
.D(D[38]),
.Q(sr_awburst[0]),
.R(1'b0));
FDRE \m_payload_i_reg[39]
(.C(s_axi_aclk),
.CE(\m_payload_i[31]_i_1_n_0 ),
.D(D[39]),
.Q(sr_awburst[1]),
.R(1'b0));
FDRE \m_payload_i_reg[3]
(.C(s_axi_aclk),
.CE(\m_payload_i[31]_i_1_n_0 ),
.D(D[3]),
.Q(\m_payload_i_reg_n_0_[3] ),
.R(1'b0));
FDRE \m_payload_i_reg[40]
(.C(s_axi_aclk),
.CE(\m_payload_i[31]_i_1_n_0 ),
.D(D[40]),
.Q(\m_axi_awregion[3] [29]),
.R(1'b0));
FDRE \m_payload_i_reg[41]
(.C(s_axi_aclk),
.CE(\m_payload_i[31]_i_1_n_0 ),
.D(D[41]),
.Q(\m_axi_awregion[3] [30]),
.R(1'b0));
FDRE \m_payload_i_reg[42]
(.C(s_axi_aclk),
.CE(\m_payload_i[31]_i_1_n_0 ),
.D(D[42]),
.Q(\m_axi_awregion[3] [31]),
.R(1'b0));
FDRE \m_payload_i_reg[43]
(.C(s_axi_aclk),
.CE(\m_payload_i[31]_i_1_n_0 ),
.D(D[43]),
.Q(\m_axi_awregion[3] [32]),
.R(1'b0));
FDRE \m_payload_i_reg[44]
(.C(s_axi_aclk),
.CE(\m_payload_i[31]_i_1_n_0 ),
.D(D[44]),
.Q(s_axi_awlen_ii[0]),
.R(1'b0));
FDRE \m_payload_i_reg[45]
(.C(s_axi_aclk),
.CE(\m_payload_i[31]_i_1_n_0 ),
.D(D[45]),
.Q(s_axi_awlen_ii[1]),
.R(1'b0));
FDRE \m_payload_i_reg[46]
(.C(s_axi_aclk),
.CE(\m_payload_i[31]_i_1_n_0 ),
.D(D[46]),
.Q(s_axi_awlen_ii[2]),
.R(1'b0));
FDRE \m_payload_i_reg[47]
(.C(s_axi_aclk),
.CE(\m_payload_i[31]_i_1_n_0 ),
.D(D[47]),
.Q(s_axi_awlen_ii[3]),
.R(1'b0));
FDRE \m_payload_i_reg[48]
(.C(s_axi_aclk),
.CE(\m_payload_i[31]_i_1_n_0 ),
.D(D[48]),
.Q(s_axi_awlen_ii[4]),
.R(1'b0));
FDRE \m_payload_i_reg[49]
(.C(s_axi_aclk),
.CE(\m_payload_i[31]_i_1_n_0 ),
.D(D[49]),
.Q(s_axi_awlen_ii[5]),
.R(1'b0));
FDRE \m_payload_i_reg[4]
(.C(s_axi_aclk),
.CE(\m_payload_i[31]_i_1_n_0 ),
.D(D[4]),
.Q(\m_payload_i_reg_n_0_[4] ),
.R(1'b0));
FDRE \m_payload_i_reg[50]
(.C(s_axi_aclk),
.CE(\m_payload_i[31]_i_1_n_0 ),
.D(D[50]),
.Q(s_axi_awlen_ii[6]),
.R(1'b0));
FDRE \m_payload_i_reg[51]
(.C(s_axi_aclk),
.CE(\m_payload_i[31]_i_1_n_0 ),
.D(D[51]),
.Q(s_axi_awlen_ii[7]),
.R(1'b0));
FDRE \m_payload_i_reg[52]
(.C(s_axi_aclk),
.CE(\m_payload_i[31]_i_1_n_0 ),
.D(D[52]),
.Q(\m_axi_awregion[3] [33]),
.R(1'b0));
FDRE \m_payload_i_reg[54]
(.C(s_axi_aclk),
.CE(\m_payload_i[31]_i_1_n_0 ),
.D(D[53]),
.Q(\m_axi_awregion[3] [34]),
.R(1'b0));
FDRE \m_payload_i_reg[55]
(.C(s_axi_aclk),
.CE(\m_payload_i[31]_i_1_n_0 ),
.D(D[54]),
.Q(\m_axi_awregion[3] [35]),
.R(1'b0));
FDRE \m_payload_i_reg[56]
(.C(s_axi_aclk),
.CE(\m_payload_i[31]_i_1_n_0 ),
.D(D[55]),
.Q(\m_axi_awregion[3] [36]),
.R(1'b0));
FDRE \m_payload_i_reg[57]
(.C(s_axi_aclk),
.CE(\m_payload_i[31]_i_1_n_0 ),
.D(D[56]),
.Q(\m_axi_awregion[3] [37]),
.R(1'b0));
FDRE \m_payload_i_reg[58]
(.C(s_axi_aclk),
.CE(\m_payload_i[31]_i_1_n_0 ),
.D(D[57]),
.Q(\m_axi_awregion[3] [38]),
.R(1'b0));
FDRE \m_payload_i_reg[59]
(.C(s_axi_aclk),
.CE(\m_payload_i[31]_i_1_n_0 ),
.D(D[58]),
.Q(\m_axi_awregion[3] [39]),
.R(1'b0));
FDRE \m_payload_i_reg[5]
(.C(s_axi_aclk),
.CE(\m_payload_i[31]_i_1_n_0 ),
.D(D[5]),
.Q(\m_payload_i_reg_n_0_[5] ),
.R(1'b0));
FDRE \m_payload_i_reg[60]
(.C(s_axi_aclk),
.CE(\m_payload_i[31]_i_1_n_0 ),
.D(D[59]),
.Q(\m_axi_awregion[3] [40]),
.R(1'b0));
FDRE \m_payload_i_reg[61]
(.C(s_axi_aclk),
.CE(\m_payload_i[31]_i_1_n_0 ),
.D(D[60]),
.Q(\m_axi_awregion[3] [41]),
.R(1'b0));
FDRE \m_payload_i_reg[6]
(.C(s_axi_aclk),
.CE(\m_payload_i[31]_i_1_n_0 ),
.D(D[6]),
.Q(\m_axi_awregion[3] [0]),
.R(1'b0));
FDRE \m_payload_i_reg[7]
(.C(s_axi_aclk),
.CE(\m_payload_i[31]_i_1_n_0 ),
.D(D[7]),
.Q(\m_axi_awregion[3] [1]),
.R(1'b0));
FDRE \m_payload_i_reg[8]
(.C(s_axi_aclk),
.CE(\m_payload_i[31]_i_1_n_0 ),
.D(D[8]),
.Q(\m_axi_awregion[3] [2]),
.R(1'b0));
FDRE \m_payload_i_reg[9]
(.C(s_axi_aclk),
.CE(\m_payload_i[31]_i_1_n_0 ),
.D(D[9]),
.Q(\m_axi_awregion[3] [3]),
.R(1'b0));
LUT4 #(
.INIT(16'hB100))
m_valid_i_i_1__1
(.I0(s_axi_awready),
.I1(cmd_push_block_reg),
.I2(s_axi_awvalid),
.I3(\aresetn_d_reg[1]_0 ),
.O(m_valid_i_i_1__1_n_0));
FDRE m_valid_i_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(m_valid_i_i_1__1_n_0),
.Q(sr_awvalid),
.R(1'b0));
LUT5 #(
.INIT(32'hDD5F0000))
s_ready_i_i_1
(.I0(\aresetn_d_reg[1]_0 ),
.I1(cmd_push_block_reg),
.I2(s_axi_awvalid),
.I3(sr_awvalid),
.I4(\aresetn_d_reg[1] ),
.O(s_ready_i_i_1_n_0));
FDRE s_ready_i_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_ready_i_i_1_n_0),
.Q(s_axi_awready),
.R(1'b0));
endmodule
|
module system_auto_us_0_axi_register_slice_v2_1_11_axic_register_slice__parameterized2
(m_axi_rready,
mr_rvalid,
Q,
s_axi_aclk,
m_axi_rlast,
m_axi_rresp,
m_axi_rdata,
m_axi_rvalid,
rd_cmd_valid,
use_wrap_buffer_reg,
\aresetn_d_reg[1] ,
\aresetn_d_reg[0] ,
E);
output m_axi_rready;
output mr_rvalid;
output [66:0]Q;
input s_axi_aclk;
input m_axi_rlast;
input [1:0]m_axi_rresp;
input [63:0]m_axi_rdata;
input m_axi_rvalid;
input rd_cmd_valid;
input use_wrap_buffer_reg;
input \aresetn_d_reg[1] ;
input \aresetn_d_reg[0] ;
input [0:0]E;
wire [0:0]E;
wire [66:0]Q;
wire \aresetn_d_reg[0] ;
wire \aresetn_d_reg[1] ;
wire [63:0]m_axi_rdata;
wire m_axi_rlast;
wire m_axi_rready;
wire [1:0]m_axi_rresp;
wire m_axi_rvalid;
wire m_valid_i_i_1__0_n_0;
wire mr_rvalid;
wire rd_cmd_valid;
wire s_axi_aclk;
wire s_ready_i_i_1_n_0;
wire [66:0]skid_buffer;
wire \skid_buffer_reg_n_0_[0] ;
wire \skid_buffer_reg_n_0_[10] ;
wire \skid_buffer_reg_n_0_[11] ;
wire \skid_buffer_reg_n_0_[12] ;
wire \skid_buffer_reg_n_0_[13] ;
wire \skid_buffer_reg_n_0_[14] ;
wire \skid_buffer_reg_n_0_[15] ;
wire \skid_buffer_reg_n_0_[16] ;
wire \skid_buffer_reg_n_0_[17] ;
wire \skid_buffer_reg_n_0_[18] ;
wire \skid_buffer_reg_n_0_[19] ;
wire \skid_buffer_reg_n_0_[1] ;
wire \skid_buffer_reg_n_0_[20] ;
wire \skid_buffer_reg_n_0_[21] ;
wire \skid_buffer_reg_n_0_[22] ;
wire \skid_buffer_reg_n_0_[23] ;
wire \skid_buffer_reg_n_0_[24] ;
wire \skid_buffer_reg_n_0_[25] ;
wire \skid_buffer_reg_n_0_[26] ;
wire \skid_buffer_reg_n_0_[27] ;
wire \skid_buffer_reg_n_0_[28] ;
wire \skid_buffer_reg_n_0_[29] ;
wire \skid_buffer_reg_n_0_[2] ;
wire \skid_buffer_reg_n_0_[30] ;
wire \skid_buffer_reg_n_0_[31] ;
wire \skid_buffer_reg_n_0_[32] ;
wire \skid_buffer_reg_n_0_[33] ;
wire \skid_buffer_reg_n_0_[34] ;
wire \skid_buffer_reg_n_0_[35] ;
wire \skid_buffer_reg_n_0_[36] ;
wire \skid_buffer_reg_n_0_[37] ;
wire \skid_buffer_reg_n_0_[38] ;
wire \skid_buffer_reg_n_0_[39] ;
wire \skid_buffer_reg_n_0_[3] ;
wire \skid_buffer_reg_n_0_[40] ;
wire \skid_buffer_reg_n_0_[41] ;
wire \skid_buffer_reg_n_0_[42] ;
wire \skid_buffer_reg_n_0_[43] ;
wire \skid_buffer_reg_n_0_[44] ;
wire \skid_buffer_reg_n_0_[45] ;
wire \skid_buffer_reg_n_0_[46] ;
wire \skid_buffer_reg_n_0_[47] ;
wire \skid_buffer_reg_n_0_[48] ;
wire \skid_buffer_reg_n_0_[49] ;
wire \skid_buffer_reg_n_0_[4] ;
wire \skid_buffer_reg_n_0_[50] ;
wire \skid_buffer_reg_n_0_[51] ;
wire \skid_buffer_reg_n_0_[52] ;
wire \skid_buffer_reg_n_0_[53] ;
wire \skid_buffer_reg_n_0_[54] ;
wire \skid_buffer_reg_n_0_[55] ;
wire \skid_buffer_reg_n_0_[56] ;
wire \skid_buffer_reg_n_0_[57] ;
wire \skid_buffer_reg_n_0_[58] ;
wire \skid_buffer_reg_n_0_[59] ;
wire \skid_buffer_reg_n_0_[5] ;
wire \skid_buffer_reg_n_0_[60] ;
wire \skid_buffer_reg_n_0_[61] ;
wire \skid_buffer_reg_n_0_[62] ;
wire \skid_buffer_reg_n_0_[63] ;
wire \skid_buffer_reg_n_0_[64] ;
wire \skid_buffer_reg_n_0_[65] ;
wire \skid_buffer_reg_n_0_[66] ;
wire \skid_buffer_reg_n_0_[6] ;
wire \skid_buffer_reg_n_0_[7] ;
wire \skid_buffer_reg_n_0_[8] ;
wire \skid_buffer_reg_n_0_[9] ;
wire use_wrap_buffer_reg;
LUT3 #(
.INIT(8'hB8))
\m_payload_i[0]_i_1
(.I0(m_axi_rdata[0]),
.I1(m_axi_rready),
.I2(\skid_buffer_reg_n_0_[0] ),
.O(skid_buffer[0]));
(* SOFT_HLUTNM = "soft_lutpair28" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[10]_i_1
(.I0(m_axi_rdata[10]),
.I1(m_axi_rready),
.I2(\skid_buffer_reg_n_0_[10] ),
.O(skid_buffer[10]));
(* SOFT_HLUTNM = "soft_lutpair27" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[11]_i_1
(.I0(m_axi_rdata[11]),
.I1(m_axi_rready),
.I2(\skid_buffer_reg_n_0_[11] ),
.O(skid_buffer[11]));
(* SOFT_HLUTNM = "soft_lutpair27" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[12]_i_1
(.I0(m_axi_rdata[12]),
.I1(m_axi_rready),
.I2(\skid_buffer_reg_n_0_[12] ),
.O(skid_buffer[12]));
(* SOFT_HLUTNM = "soft_lutpair26" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[13]_i_1
(.I0(m_axi_rdata[13]),
.I1(m_axi_rready),
.I2(\skid_buffer_reg_n_0_[13] ),
.O(skid_buffer[13]));
(* SOFT_HLUTNM = "soft_lutpair26" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[14]_i_1
(.I0(m_axi_rdata[14]),
.I1(m_axi_rready),
.I2(\skid_buffer_reg_n_0_[14] ),
.O(skid_buffer[14]));
(* SOFT_HLUTNM = "soft_lutpair25" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[15]_i_1
(.I0(m_axi_rdata[15]),
.I1(m_axi_rready),
.I2(\skid_buffer_reg_n_0_[15] ),
.O(skid_buffer[15]));
(* SOFT_HLUTNM = "soft_lutpair25" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[16]_i_1
(.I0(m_axi_rdata[16]),
.I1(m_axi_rready),
.I2(\skid_buffer_reg_n_0_[16] ),
.O(skid_buffer[16]));
(* SOFT_HLUTNM = "soft_lutpair24" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[17]_i_1
(.I0(m_axi_rdata[17]),
.I1(m_axi_rready),
.I2(\skid_buffer_reg_n_0_[17] ),
.O(skid_buffer[17]));
(* SOFT_HLUTNM = "soft_lutpair24" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[18]_i_1
(.I0(m_axi_rdata[18]),
.I1(m_axi_rready),
.I2(\skid_buffer_reg_n_0_[18] ),
.O(skid_buffer[18]));
(* SOFT_HLUTNM = "soft_lutpair23" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[19]_i_1
(.I0(m_axi_rdata[19]),
.I1(m_axi_rready),
.I2(\skid_buffer_reg_n_0_[19] ),
.O(skid_buffer[19]));
(* SOFT_HLUTNM = "soft_lutpair32" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[1]_i_1
(.I0(m_axi_rdata[1]),
.I1(m_axi_rready),
.I2(\skid_buffer_reg_n_0_[1] ),
.O(skid_buffer[1]));
(* SOFT_HLUTNM = "soft_lutpair23" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[20]_i_1
(.I0(m_axi_rdata[20]),
.I1(m_axi_rready),
.I2(\skid_buffer_reg_n_0_[20] ),
.O(skid_buffer[20]));
(* SOFT_HLUTNM = "soft_lutpair22" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[21]_i_1
(.I0(m_axi_rdata[21]),
.I1(m_axi_rready),
.I2(\skid_buffer_reg_n_0_[21] ),
.O(skid_buffer[21]));
(* SOFT_HLUTNM = "soft_lutpair22" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[22]_i_1
(.I0(m_axi_rdata[22]),
.I1(m_axi_rready),
.I2(\skid_buffer_reg_n_0_[22] ),
.O(skid_buffer[22]));
(* SOFT_HLUTNM = "soft_lutpair21" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[23]_i_1
(.I0(m_axi_rdata[23]),
.I1(m_axi_rready),
.I2(\skid_buffer_reg_n_0_[23] ),
.O(skid_buffer[23]));
(* SOFT_HLUTNM = "soft_lutpair21" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[24]_i_1
(.I0(m_axi_rdata[24]),
.I1(m_axi_rready),
.I2(\skid_buffer_reg_n_0_[24] ),
.O(skid_buffer[24]));
(* SOFT_HLUTNM = "soft_lutpair20" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[25]_i_1
(.I0(m_axi_rdata[25]),
.I1(m_axi_rready),
.I2(\skid_buffer_reg_n_0_[25] ),
.O(skid_buffer[25]));
(* SOFT_HLUTNM = "soft_lutpair20" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[26]_i_1
(.I0(m_axi_rdata[26]),
.I1(m_axi_rready),
.I2(\skid_buffer_reg_n_0_[26] ),
.O(skid_buffer[26]));
(* SOFT_HLUTNM = "soft_lutpair19" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[27]_i_1
(.I0(m_axi_rdata[27]),
.I1(m_axi_rready),
.I2(\skid_buffer_reg_n_0_[27] ),
.O(skid_buffer[27]));
(* SOFT_HLUTNM = "soft_lutpair19" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[28]_i_1
(.I0(m_axi_rdata[28]),
.I1(m_axi_rready),
.I2(\skid_buffer_reg_n_0_[28] ),
.O(skid_buffer[28]));
(* SOFT_HLUTNM = "soft_lutpair18" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[29]_i_1
(.I0(m_axi_rdata[29]),
.I1(m_axi_rready),
.I2(\skid_buffer_reg_n_0_[29] ),
.O(skid_buffer[29]));
(* SOFT_HLUTNM = "soft_lutpair32" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[2]_i_1
(.I0(m_axi_rdata[2]),
.I1(m_axi_rready),
.I2(\skid_buffer_reg_n_0_[2] ),
.O(skid_buffer[2]));
(* SOFT_HLUTNM = "soft_lutpair18" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[30]_i_1
(.I0(m_axi_rdata[30]),
.I1(m_axi_rready),
.I2(\skid_buffer_reg_n_0_[30] ),
.O(skid_buffer[30]));
(* SOFT_HLUTNM = "soft_lutpair17" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[31]_i_1__1
(.I0(m_axi_rdata[31]),
.I1(m_axi_rready),
.I2(\skid_buffer_reg_n_0_[31] ),
.O(skid_buffer[31]));
(* SOFT_HLUTNM = "soft_lutpair17" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[32]_i_1
(.I0(m_axi_rdata[32]),
.I1(m_axi_rready),
.I2(\skid_buffer_reg_n_0_[32] ),
.O(skid_buffer[32]));
(* SOFT_HLUTNM = "soft_lutpair16" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[33]_i_1
(.I0(m_axi_rdata[33]),
.I1(m_axi_rready),
.I2(\skid_buffer_reg_n_0_[33] ),
.O(skid_buffer[33]));
(* SOFT_HLUTNM = "soft_lutpair16" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[34]_i_1
(.I0(m_axi_rdata[34]),
.I1(m_axi_rready),
.I2(\skid_buffer_reg_n_0_[34] ),
.O(skid_buffer[34]));
(* SOFT_HLUTNM = "soft_lutpair15" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[35]_i_1
(.I0(m_axi_rdata[35]),
.I1(m_axi_rready),
.I2(\skid_buffer_reg_n_0_[35] ),
.O(skid_buffer[35]));
(* SOFT_HLUTNM = "soft_lutpair15" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[36]_i_1
(.I0(m_axi_rdata[36]),
.I1(m_axi_rready),
.I2(\skid_buffer_reg_n_0_[36] ),
.O(skid_buffer[36]));
(* SOFT_HLUTNM = "soft_lutpair14" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[37]_i_1
(.I0(m_axi_rdata[37]),
.I1(m_axi_rready),
.I2(\skid_buffer_reg_n_0_[37] ),
.O(skid_buffer[37]));
(* SOFT_HLUTNM = "soft_lutpair14" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[38]_i_1
(.I0(m_axi_rdata[38]),
.I1(m_axi_rready),
.I2(\skid_buffer_reg_n_0_[38] ),
.O(skid_buffer[38]));
(* SOFT_HLUTNM = "soft_lutpair13" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[39]_i_1
(.I0(m_axi_rdata[39]),
.I1(m_axi_rready),
.I2(\skid_buffer_reg_n_0_[39] ),
.O(skid_buffer[39]));
(* SOFT_HLUTNM = "soft_lutpair31" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[3]_i_1
(.I0(m_axi_rdata[3]),
.I1(m_axi_rready),
.I2(\skid_buffer_reg_n_0_[3] ),
.O(skid_buffer[3]));
(* SOFT_HLUTNM = "soft_lutpair13" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[40]_i_1
(.I0(m_axi_rdata[40]),
.I1(m_axi_rready),
.I2(\skid_buffer_reg_n_0_[40] ),
.O(skid_buffer[40]));
(* SOFT_HLUTNM = "soft_lutpair12" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[41]_i_1
(.I0(m_axi_rdata[41]),
.I1(m_axi_rready),
.I2(\skid_buffer_reg_n_0_[41] ),
.O(skid_buffer[41]));
(* SOFT_HLUTNM = "soft_lutpair12" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[42]_i_1
(.I0(m_axi_rdata[42]),
.I1(m_axi_rready),
.I2(\skid_buffer_reg_n_0_[42] ),
.O(skid_buffer[42]));
(* SOFT_HLUTNM = "soft_lutpair11" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[43]_i_1
(.I0(m_axi_rdata[43]),
.I1(m_axi_rready),
.I2(\skid_buffer_reg_n_0_[43] ),
.O(skid_buffer[43]));
(* SOFT_HLUTNM = "soft_lutpair11" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[44]_i_1
(.I0(m_axi_rdata[44]),
.I1(m_axi_rready),
.I2(\skid_buffer_reg_n_0_[44] ),
.O(skid_buffer[44]));
(* SOFT_HLUTNM = "soft_lutpair10" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[45]_i_1
(.I0(m_axi_rdata[45]),
.I1(m_axi_rready),
.I2(\skid_buffer_reg_n_0_[45] ),
.O(skid_buffer[45]));
(* SOFT_HLUTNM = "soft_lutpair10" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[46]_i_1
(.I0(m_axi_rdata[46]),
.I1(m_axi_rready),
.I2(\skid_buffer_reg_n_0_[46] ),
.O(skid_buffer[46]));
(* SOFT_HLUTNM = "soft_lutpair9" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[47]_i_1
(.I0(m_axi_rdata[47]),
.I1(m_axi_rready),
.I2(\skid_buffer_reg_n_0_[47] ),
.O(skid_buffer[47]));
(* SOFT_HLUTNM = "soft_lutpair9" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[48]_i_1
(.I0(m_axi_rdata[48]),
.I1(m_axi_rready),
.I2(\skid_buffer_reg_n_0_[48] ),
.O(skid_buffer[48]));
(* SOFT_HLUTNM = "soft_lutpair8" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[49]_i_1
(.I0(m_axi_rdata[49]),
.I1(m_axi_rready),
.I2(\skid_buffer_reg_n_0_[49] ),
.O(skid_buffer[49]));
(* SOFT_HLUTNM = "soft_lutpair31" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[4]_i_1
(.I0(m_axi_rdata[4]),
.I1(m_axi_rready),
.I2(\skid_buffer_reg_n_0_[4] ),
.O(skid_buffer[4]));
(* SOFT_HLUTNM = "soft_lutpair8" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[50]_i_1
(.I0(m_axi_rdata[50]),
.I1(m_axi_rready),
.I2(\skid_buffer_reg_n_0_[50] ),
.O(skid_buffer[50]));
(* SOFT_HLUTNM = "soft_lutpair7" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[51]_i_1
(.I0(m_axi_rdata[51]),
.I1(m_axi_rready),
.I2(\skid_buffer_reg_n_0_[51] ),
.O(skid_buffer[51]));
(* SOFT_HLUTNM = "soft_lutpair7" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[52]_i_1
(.I0(m_axi_rdata[52]),
.I1(m_axi_rready),
.I2(\skid_buffer_reg_n_0_[52] ),
.O(skid_buffer[52]));
(* SOFT_HLUTNM = "soft_lutpair6" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[53]_i_1
(.I0(m_axi_rdata[53]),
.I1(m_axi_rready),
.I2(\skid_buffer_reg_n_0_[53] ),
.O(skid_buffer[53]));
(* SOFT_HLUTNM = "soft_lutpair6" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[54]_i_1
(.I0(m_axi_rdata[54]),
.I1(m_axi_rready),
.I2(\skid_buffer_reg_n_0_[54] ),
.O(skid_buffer[54]));
(* SOFT_HLUTNM = "soft_lutpair5" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[55]_i_1
(.I0(m_axi_rdata[55]),
.I1(m_axi_rready),
.I2(\skid_buffer_reg_n_0_[55] ),
.O(skid_buffer[55]));
(* SOFT_HLUTNM = "soft_lutpair5" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[56]_i_1
(.I0(m_axi_rdata[56]),
.I1(m_axi_rready),
.I2(\skid_buffer_reg_n_0_[56] ),
.O(skid_buffer[56]));
(* SOFT_HLUTNM = "soft_lutpair4" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[57]_i_1
(.I0(m_axi_rdata[57]),
.I1(m_axi_rready),
.I2(\skid_buffer_reg_n_0_[57] ),
.O(skid_buffer[57]));
(* SOFT_HLUTNM = "soft_lutpair4" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[58]_i_1
(.I0(m_axi_rdata[58]),
.I1(m_axi_rready),
.I2(\skid_buffer_reg_n_0_[58] ),
.O(skid_buffer[58]));
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[59]_i_1
(.I0(m_axi_rdata[59]),
.I1(m_axi_rready),
.I2(\skid_buffer_reg_n_0_[59] ),
.O(skid_buffer[59]));
(* SOFT_HLUTNM = "soft_lutpair30" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[5]_i_1
(.I0(m_axi_rdata[5]),
.I1(m_axi_rready),
.I2(\skid_buffer_reg_n_0_[5] ),
.O(skid_buffer[5]));
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[60]_i_1
(.I0(m_axi_rdata[60]),
.I1(m_axi_rready),
.I2(\skid_buffer_reg_n_0_[60] ),
.O(skid_buffer[60]));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[61]_i_1
(.I0(m_axi_rdata[61]),
.I1(m_axi_rready),
.I2(\skid_buffer_reg_n_0_[61] ),
.O(skid_buffer[61]));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[62]_i_1
(.I0(m_axi_rdata[62]),
.I1(m_axi_rready),
.I2(\skid_buffer_reg_n_0_[62] ),
.O(skid_buffer[62]));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[63]_i_1
(.I0(m_axi_rdata[63]),
.I1(m_axi_rready),
.I2(\skid_buffer_reg_n_0_[63] ),
.O(skid_buffer[63]));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[64]_i_1
(.I0(m_axi_rresp[0]),
.I1(m_axi_rready),
.I2(\skid_buffer_reg_n_0_[64] ),
.O(skid_buffer[64]));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[65]_i_1
(.I0(m_axi_rresp[1]),
.I1(m_axi_rready),
.I2(\skid_buffer_reg_n_0_[65] ),
.O(skid_buffer[65]));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[66]_i_2
(.I0(m_axi_rlast),
.I1(m_axi_rready),
.I2(\skid_buffer_reg_n_0_[66] ),
.O(skid_buffer[66]));
(* SOFT_HLUTNM = "soft_lutpair30" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[6]_i_1
(.I0(m_axi_rdata[6]),
.I1(m_axi_rready),
.I2(\skid_buffer_reg_n_0_[6] ),
.O(skid_buffer[6]));
(* SOFT_HLUTNM = "soft_lutpair29" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[7]_i_1
(.I0(m_axi_rdata[7]),
.I1(m_axi_rready),
.I2(\skid_buffer_reg_n_0_[7] ),
.O(skid_buffer[7]));
(* SOFT_HLUTNM = "soft_lutpair29" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[8]_i_1
(.I0(m_axi_rdata[8]),
.I1(m_axi_rready),
.I2(\skid_buffer_reg_n_0_[8] ),
.O(skid_buffer[8]));
(* SOFT_HLUTNM = "soft_lutpair28" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[9]_i_1
(.I0(m_axi_rdata[9]),
.I1(m_axi_rready),
.I2(\skid_buffer_reg_n_0_[9] ),
.O(skid_buffer[9]));
FDRE \m_payload_i_reg[0]
(.C(s_axi_aclk),
.CE(E),
.D(skid_buffer[0]),
.Q(Q[0]),
.R(1'b0));
FDRE \m_payload_i_reg[10]
(.C(s_axi_aclk),
.CE(E),
.D(skid_buffer[10]),
.Q(Q[10]),
.R(1'b0));
FDRE \m_payload_i_reg[11]
(.C(s_axi_aclk),
.CE(E),
.D(skid_buffer[11]),
.Q(Q[11]),
.R(1'b0));
FDRE \m_payload_i_reg[12]
(.C(s_axi_aclk),
.CE(E),
.D(skid_buffer[12]),
.Q(Q[12]),
.R(1'b0));
FDRE \m_payload_i_reg[13]
(.C(s_axi_aclk),
.CE(E),
.D(skid_buffer[13]),
.Q(Q[13]),
.R(1'b0));
FDRE \m_payload_i_reg[14]
(.C(s_axi_aclk),
.CE(E),
.D(skid_buffer[14]),
.Q(Q[14]),
.R(1'b0));
FDRE \m_payload_i_reg[15]
(.C(s_axi_aclk),
.CE(E),
.D(skid_buffer[15]),
.Q(Q[15]),
.R(1'b0));
FDRE \m_payload_i_reg[16]
(.C(s_axi_aclk),
.CE(E),
.D(skid_buffer[16]),
.Q(Q[16]),
.R(1'b0));
FDRE \m_payload_i_reg[17]
(.C(s_axi_aclk),
.CE(E),
.D(skid_buffer[17]),
.Q(Q[17]),
.R(1'b0));
FDRE \m_payload_i_reg[18]
(.C(s_axi_aclk),
.CE(E),
.D(skid_buffer[18]),
.Q(Q[18]),
.R(1'b0));
FDRE \m_payload_i_reg[19]
(.C(s_axi_aclk),
.CE(E),
.D(skid_buffer[19]),
.Q(Q[19]),
.R(1'b0));
FDRE \m_payload_i_reg[1]
(.C(s_axi_aclk),
.CE(E),
.D(skid_buffer[1]),
.Q(Q[1]),
.R(1'b0));
FDRE \m_payload_i_reg[20]
(.C(s_axi_aclk),
.CE(E),
.D(skid_buffer[20]),
.Q(Q[20]),
.R(1'b0));
FDRE \m_payload_i_reg[21]
(.C(s_axi_aclk),
.CE(E),
.D(skid_buffer[21]),
.Q(Q[21]),
.R(1'b0));
FDRE \m_payload_i_reg[22]
(.C(s_axi_aclk),
.CE(E),
.D(skid_buffer[22]),
.Q(Q[22]),
.R(1'b0));
FDRE \m_payload_i_reg[23]
(.C(s_axi_aclk),
.CE(E),
.D(skid_buffer[23]),
.Q(Q[23]),
.R(1'b0));
FDRE \m_payload_i_reg[24]
(.C(s_axi_aclk),
.CE(E),
.D(skid_buffer[24]),
.Q(Q[24]),
.R(1'b0));
FDRE \m_payload_i_reg[25]
(.C(s_axi_aclk),
.CE(E),
.D(skid_buffer[25]),
.Q(Q[25]),
.R(1'b0));
FDRE \m_payload_i_reg[26]
(.C(s_axi_aclk),
.CE(E),
.D(skid_buffer[26]),
.Q(Q[26]),
.R(1'b0));
FDRE \m_payload_i_reg[27]
(.C(s_axi_aclk),
.CE(E),
.D(skid_buffer[27]),
.Q(Q[27]),
.R(1'b0));
FDRE \m_payload_i_reg[28]
(.C(s_axi_aclk),
.CE(E),
.D(skid_buffer[28]),
.Q(Q[28]),
.R(1'b0));
FDRE \m_payload_i_reg[29]
(.C(s_axi_aclk),
.CE(E),
.D(skid_buffer[29]),
.Q(Q[29]),
.R(1'b0));
FDRE \m_payload_i_reg[2]
(.C(s_axi_aclk),
.CE(E),
.D(skid_buffer[2]),
.Q(Q[2]),
.R(1'b0));
FDRE \m_payload_i_reg[30]
(.C(s_axi_aclk),
.CE(E),
.D(skid_buffer[30]),
.Q(Q[30]),
.R(1'b0));
FDRE \m_payload_i_reg[31]
(.C(s_axi_aclk),
.CE(E),
.D(skid_buffer[31]),
.Q(Q[31]),
.R(1'b0));
FDRE \m_payload_i_reg[32]
(.C(s_axi_aclk),
.CE(E),
.D(skid_buffer[32]),
.Q(Q[32]),
.R(1'b0));
FDRE \m_payload_i_reg[33]
(.C(s_axi_aclk),
.CE(E),
.D(skid_buffer[33]),
.Q(Q[33]),
.R(1'b0));
FDRE \m_payload_i_reg[34]
(.C(s_axi_aclk),
.CE(E),
.D(skid_buffer[34]),
.Q(Q[34]),
.R(1'b0));
FDRE \m_payload_i_reg[35]
(.C(s_axi_aclk),
.CE(E),
.D(skid_buffer[35]),
.Q(Q[35]),
.R(1'b0));
FDRE \m_payload_i_reg[36]
(.C(s_axi_aclk),
.CE(E),
.D(skid_buffer[36]),
.Q(Q[36]),
.R(1'b0));
FDRE \m_payload_i_reg[37]
(.C(s_axi_aclk),
.CE(E),
.D(skid_buffer[37]),
.Q(Q[37]),
.R(1'b0));
FDRE \m_payload_i_reg[38]
(.C(s_axi_aclk),
.CE(E),
.D(skid_buffer[38]),
.Q(Q[38]),
.R(1'b0));
FDRE \m_payload_i_reg[39]
(.C(s_axi_aclk),
.CE(E),
.D(skid_buffer[39]),
.Q(Q[39]),
.R(1'b0));
FDRE \m_payload_i_reg[3]
(.C(s_axi_aclk),
.CE(E),
.D(skid_buffer[3]),
.Q(Q[3]),
.R(1'b0));
FDRE \m_payload_i_reg[40]
(.C(s_axi_aclk),
.CE(E),
.D(skid_buffer[40]),
.Q(Q[40]),
.R(1'b0));
FDRE \m_payload_i_reg[41]
(.C(s_axi_aclk),
.CE(E),
.D(skid_buffer[41]),
.Q(Q[41]),
.R(1'b0));
FDRE \m_payload_i_reg[42]
(.C(s_axi_aclk),
.CE(E),
.D(skid_buffer[42]),
.Q(Q[42]),
.R(1'b0));
FDRE \m_payload_i_reg[43]
(.C(s_axi_aclk),
.CE(E),
.D(skid_buffer[43]),
.Q(Q[43]),
.R(1'b0));
FDRE \m_payload_i_reg[44]
(.C(s_axi_aclk),
.CE(E),
.D(skid_buffer[44]),
.Q(Q[44]),
.R(1'b0));
FDRE \m_payload_i_reg[45]
(.C(s_axi_aclk),
.CE(E),
.D(skid_buffer[45]),
.Q(Q[45]),
.R(1'b0));
FDRE \m_payload_i_reg[46]
(.C(s_axi_aclk),
.CE(E),
.D(skid_buffer[46]),
.Q(Q[46]),
.R(1'b0));
FDRE \m_payload_i_reg[47]
(.C(s_axi_aclk),
.CE(E),
.D(skid_buffer[47]),
.Q(Q[47]),
.R(1'b0));
FDRE \m_payload_i_reg[48]
(.C(s_axi_aclk),
.CE(E),
.D(skid_buffer[48]),
.Q(Q[48]),
.R(1'b0));
FDRE \m_payload_i_reg[49]
(.C(s_axi_aclk),
.CE(E),
.D(skid_buffer[49]),
.Q(Q[49]),
.R(1'b0));
FDRE \m_payload_i_reg[4]
(.C(s_axi_aclk),
.CE(E),
.D(skid_buffer[4]),
.Q(Q[4]),
.R(1'b0));
FDRE \m_payload_i_reg[50]
(.C(s_axi_aclk),
.CE(E),
.D(skid_buffer[50]),
.Q(Q[50]),
.R(1'b0));
FDRE \m_payload_i_reg[51]
(.C(s_axi_aclk),
.CE(E),
.D(skid_buffer[51]),
.Q(Q[51]),
.R(1'b0));
FDRE \m_payload_i_reg[52]
(.C(s_axi_aclk),
.CE(E),
.D(skid_buffer[52]),
.Q(Q[52]),
.R(1'b0));
FDRE \m_payload_i_reg[53]
(.C(s_axi_aclk),
.CE(E),
.D(skid_buffer[53]),
.Q(Q[53]),
.R(1'b0));
FDRE \m_payload_i_reg[54]
(.C(s_axi_aclk),
.CE(E),
.D(skid_buffer[54]),
.Q(Q[54]),
.R(1'b0));
FDRE \m_payload_i_reg[55]
(.C(s_axi_aclk),
.CE(E),
.D(skid_buffer[55]),
.Q(Q[55]),
.R(1'b0));
FDRE \m_payload_i_reg[56]
(.C(s_axi_aclk),
.CE(E),
.D(skid_buffer[56]),
.Q(Q[56]),
.R(1'b0));
FDRE \m_payload_i_reg[57]
(.C(s_axi_aclk),
.CE(E),
.D(skid_buffer[57]),
.Q(Q[57]),
.R(1'b0));
FDRE \m_payload_i_reg[58]
(.C(s_axi_aclk),
.CE(E),
.D(skid_buffer[58]),
.Q(Q[58]),
.R(1'b0));
FDRE \m_payload_i_reg[59]
(.C(s_axi_aclk),
.CE(E),
.D(skid_buffer[59]),
.Q(Q[59]),
.R(1'b0));
FDRE \m_payload_i_reg[5]
(.C(s_axi_aclk),
.CE(E),
.D(skid_buffer[5]),
.Q(Q[5]),
.R(1'b0));
FDRE \m_payload_i_reg[60]
(.C(s_axi_aclk),
.CE(E),
.D(skid_buffer[60]),
.Q(Q[60]),
.R(1'b0));
FDRE \m_payload_i_reg[61]
(.C(s_axi_aclk),
.CE(E),
.D(skid_buffer[61]),
.Q(Q[61]),
.R(1'b0));
FDRE \m_payload_i_reg[62]
(.C(s_axi_aclk),
.CE(E),
.D(skid_buffer[62]),
.Q(Q[62]),
.R(1'b0));
FDRE \m_payload_i_reg[63]
(.C(s_axi_aclk),
.CE(E),
.D(skid_buffer[63]),
.Q(Q[63]),
.R(1'b0));
FDRE \m_payload_i_reg[64]
(.C(s_axi_aclk),
.CE(E),
.D(skid_buffer[64]),
.Q(Q[64]),
.R(1'b0));
FDRE \m_payload_i_reg[65]
(.C(s_axi_aclk),
.CE(E),
.D(skid_buffer[65]),
.Q(Q[65]),
.R(1'b0));
FDRE \m_payload_i_reg[66]
(.C(s_axi_aclk),
.CE(E),
.D(skid_buffer[66]),
.Q(Q[66]),
.R(1'b0));
FDRE \m_payload_i_reg[6]
(.C(s_axi_aclk),
.CE(E),
.D(skid_buffer[6]),
.Q(Q[6]),
.R(1'b0));
FDRE \m_payload_i_reg[7]
(.C(s_axi_aclk),
.CE(E),
.D(skid_buffer[7]),
.Q(Q[7]),
.R(1'b0));
FDRE \m_payload_i_reg[8]
(.C(s_axi_aclk),
.CE(E),
.D(skid_buffer[8]),
.Q(Q[8]),
.R(1'b0));
FDRE \m_payload_i_reg[9]
(.C(s_axi_aclk),
.CE(E),
.D(skid_buffer[9]),
.Q(Q[9]),
.R(1'b0));
LUT6 #(
.INIT(64'hDDFDFDFD00000000))
m_valid_i_i_1__0
(.I0(m_axi_rready),
.I1(m_axi_rvalid),
.I2(mr_rvalid),
.I3(rd_cmd_valid),
.I4(use_wrap_buffer_reg),
.I5(\aresetn_d_reg[1] ),
.O(m_valid_i_i_1__0_n_0));
FDRE m_valid_i_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(m_valid_i_i_1__0_n_0),
.Q(mr_rvalid),
.R(1'b0));
LUT6 #(
.INIT(64'hD5D5FFD500000000))
s_ready_i_i_1
(.I0(mr_rvalid),
.I1(rd_cmd_valid),
.I2(use_wrap_buffer_reg),
.I3(m_axi_rready),
.I4(m_axi_rvalid),
.I5(\aresetn_d_reg[0] ),
.O(s_ready_i_i_1_n_0));
FDRE s_ready_i_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_ready_i_i_1_n_0),
.Q(m_axi_rready),
.R(1'b0));
FDRE \skid_buffer_reg[0]
(.C(s_axi_aclk),
.CE(m_axi_rready),
.D(m_axi_rdata[0]),
.Q(\skid_buffer_reg_n_0_[0] ),
.R(1'b0));
FDRE \skid_buffer_reg[10]
(.C(s_axi_aclk),
.CE(m_axi_rready),
.D(m_axi_rdata[10]),
.Q(\skid_buffer_reg_n_0_[10] ),
.R(1'b0));
FDRE \skid_buffer_reg[11]
(.C(s_axi_aclk),
.CE(m_axi_rready),
.D(m_axi_rdata[11]),
.Q(\skid_buffer_reg_n_0_[11] ),
.R(1'b0));
FDRE \skid_buffer_reg[12]
(.C(s_axi_aclk),
.CE(m_axi_rready),
.D(m_axi_rdata[12]),
.Q(\skid_buffer_reg_n_0_[12] ),
.R(1'b0));
FDRE \skid_buffer_reg[13]
(.C(s_axi_aclk),
.CE(m_axi_rready),
.D(m_axi_rdata[13]),
.Q(\skid_buffer_reg_n_0_[13] ),
.R(1'b0));
FDRE \skid_buffer_reg[14]
(.C(s_axi_aclk),
.CE(m_axi_rready),
.D(m_axi_rdata[14]),
.Q(\skid_buffer_reg_n_0_[14] ),
.R(1'b0));
FDRE \skid_buffer_reg[15]
(.C(s_axi_aclk),
.CE(m_axi_rready),
.D(m_axi_rdata[15]),
.Q(\skid_buffer_reg_n_0_[15] ),
.R(1'b0));
FDRE \skid_buffer_reg[16]
(.C(s_axi_aclk),
.CE(m_axi_rready),
.D(m_axi_rdata[16]),
.Q(\skid_buffer_reg_n_0_[16] ),
.R(1'b0));
FDRE \skid_buffer_reg[17]
(.C(s_axi_aclk),
.CE(m_axi_rready),
.D(m_axi_rdata[17]),
.Q(\skid_buffer_reg_n_0_[17] ),
.R(1'b0));
FDRE \skid_buffer_reg[18]
(.C(s_axi_aclk),
.CE(m_axi_rready),
.D(m_axi_rdata[18]),
.Q(\skid_buffer_reg_n_0_[18] ),
.R(1'b0));
FDRE \skid_buffer_reg[19]
(.C(s_axi_aclk),
.CE(m_axi_rready),
.D(m_axi_rdata[19]),
.Q(\skid_buffer_reg_n_0_[19] ),
.R(1'b0));
FDRE \skid_buffer_reg[1]
(.C(s_axi_aclk),
.CE(m_axi_rready),
.D(m_axi_rdata[1]),
.Q(\skid_buffer_reg_n_0_[1] ),
.R(1'b0));
FDRE \skid_buffer_reg[20]
(.C(s_axi_aclk),
.CE(m_axi_rready),
.D(m_axi_rdata[20]),
.Q(\skid_buffer_reg_n_0_[20] ),
.R(1'b0));
FDRE \skid_buffer_reg[21]
(.C(s_axi_aclk),
.CE(m_axi_rready),
.D(m_axi_rdata[21]),
.Q(\skid_buffer_reg_n_0_[21] ),
.R(1'b0));
FDRE \skid_buffer_reg[22]
(.C(s_axi_aclk),
.CE(m_axi_rready),
.D(m_axi_rdata[22]),
.Q(\skid_buffer_reg_n_0_[22] ),
.R(1'b0));
FDRE \skid_buffer_reg[23]
(.C(s_axi_aclk),
.CE(m_axi_rready),
.D(m_axi_rdata[23]),
.Q(\skid_buffer_reg_n_0_[23] ),
.R(1'b0));
FDRE \skid_buffer_reg[24]
(.C(s_axi_aclk),
.CE(m_axi_rready),
.D(m_axi_rdata[24]),
.Q(\skid_buffer_reg_n_0_[24] ),
.R(1'b0));
FDRE \skid_buffer_reg[25]
(.C(s_axi_aclk),
.CE(m_axi_rready),
.D(m_axi_rdata[25]),
.Q(\skid_buffer_reg_n_0_[25] ),
.R(1'b0));
FDRE \skid_buffer_reg[26]
(.C(s_axi_aclk),
.CE(m_axi_rready),
.D(m_axi_rdata[26]),
.Q(\skid_buffer_reg_n_0_[26] ),
.R(1'b0));
FDRE \skid_buffer_reg[27]
(.C(s_axi_aclk),
.CE(m_axi_rready),
.D(m_axi_rdata[27]),
.Q(\skid_buffer_reg_n_0_[27] ),
.R(1'b0));
FDRE \skid_buffer_reg[28]
(.C(s_axi_aclk),
.CE(m_axi_rready),
.D(m_axi_rdata[28]),
.Q(\skid_buffer_reg_n_0_[28] ),
.R(1'b0));
FDRE \skid_buffer_reg[29]
(.C(s_axi_aclk),
.CE(m_axi_rready),
.D(m_axi_rdata[29]),
.Q(\skid_buffer_reg_n_0_[29] ),
.R(1'b0));
FDRE \skid_buffer_reg[2]
(.C(s_axi_aclk),
.CE(m_axi_rready),
.D(m_axi_rdata[2]),
.Q(\skid_buffer_reg_n_0_[2] ),
.R(1'b0));
FDRE \skid_buffer_reg[30]
(.C(s_axi_aclk),
.CE(m_axi_rready),
.D(m_axi_rdata[30]),
.Q(\skid_buffer_reg_n_0_[30] ),
.R(1'b0));
FDRE \skid_buffer_reg[31]
(.C(s_axi_aclk),
.CE(m_axi_rready),
.D(m_axi_rdata[31]),
.Q(\skid_buffer_reg_n_0_[31] ),
.R(1'b0));
FDRE \skid_buffer_reg[32]
(.C(s_axi_aclk),
.CE(m_axi_rready),
.D(m_axi_rdata[32]),
.Q(\skid_buffer_reg_n_0_[32] ),
.R(1'b0));
FDRE \skid_buffer_reg[33]
(.C(s_axi_aclk),
.CE(m_axi_rready),
.D(m_axi_rdata[33]),
.Q(\skid_buffer_reg_n_0_[33] ),
.R(1'b0));
FDRE \skid_buffer_reg[34]
(.C(s_axi_aclk),
.CE(m_axi_rready),
.D(m_axi_rdata[34]),
.Q(\skid_buffer_reg_n_0_[34] ),
.R(1'b0));
FDRE \skid_buffer_reg[35]
(.C(s_axi_aclk),
.CE(m_axi_rready),
.D(m_axi_rdata[35]),
.Q(\skid_buffer_reg_n_0_[35] ),
.R(1'b0));
FDRE \skid_buffer_reg[36]
(.C(s_axi_aclk),
.CE(m_axi_rready),
.D(m_axi_rdata[36]),
.Q(\skid_buffer_reg_n_0_[36] ),
.R(1'b0));
FDRE \skid_buffer_reg[37]
(.C(s_axi_aclk),
.CE(m_axi_rready),
.D(m_axi_rdata[37]),
.Q(\skid_buffer_reg_n_0_[37] ),
.R(1'b0));
FDRE \skid_buffer_reg[38]
(.C(s_axi_aclk),
.CE(m_axi_rready),
.D(m_axi_rdata[38]),
.Q(\skid_buffer_reg_n_0_[38] ),
.R(1'b0));
FDRE \skid_buffer_reg[39]
(.C(s_axi_aclk),
.CE(m_axi_rready),
.D(m_axi_rdata[39]),
.Q(\skid_buffer_reg_n_0_[39] ),
.R(1'b0));
FDRE \skid_buffer_reg[3]
(.C(s_axi_aclk),
.CE(m_axi_rready),
.D(m_axi_rdata[3]),
.Q(\skid_buffer_reg_n_0_[3] ),
.R(1'b0));
FDRE \skid_buffer_reg[40]
(.C(s_axi_aclk),
.CE(m_axi_rready),
.D(m_axi_rdata[40]),
.Q(\skid_buffer_reg_n_0_[40] ),
.R(1'b0));
FDRE \skid_buffer_reg[41]
(.C(s_axi_aclk),
.CE(m_axi_rready),
.D(m_axi_rdata[41]),
.Q(\skid_buffer_reg_n_0_[41] ),
.R(1'b0));
FDRE \skid_buffer_reg[42]
(.C(s_axi_aclk),
.CE(m_axi_rready),
.D(m_axi_rdata[42]),
.Q(\skid_buffer_reg_n_0_[42] ),
.R(1'b0));
FDRE \skid_buffer_reg[43]
(.C(s_axi_aclk),
.CE(m_axi_rready),
.D(m_axi_rdata[43]),
.Q(\skid_buffer_reg_n_0_[43] ),
.R(1'b0));
FDRE \skid_buffer_reg[44]
(.C(s_axi_aclk),
.CE(m_axi_rready),
.D(m_axi_rdata[44]),
.Q(\skid_buffer_reg_n_0_[44] ),
.R(1'b0));
FDRE \skid_buffer_reg[45]
(.C(s_axi_aclk),
.CE(m_axi_rready),
.D(m_axi_rdata[45]),
.Q(\skid_buffer_reg_n_0_[45] ),
.R(1'b0));
FDRE \skid_buffer_reg[46]
(.C(s_axi_aclk),
.CE(m_axi_rready),
.D(m_axi_rdata[46]),
.Q(\skid_buffer_reg_n_0_[46] ),
.R(1'b0));
FDRE \skid_buffer_reg[47]
(.C(s_axi_aclk),
.CE(m_axi_rready),
.D(m_axi_rdata[47]),
.Q(\skid_buffer_reg_n_0_[47] ),
.R(1'b0));
FDRE \skid_buffer_reg[48]
(.C(s_axi_aclk),
.CE(m_axi_rready),
.D(m_axi_rdata[48]),
.Q(\skid_buffer_reg_n_0_[48] ),
.R(1'b0));
FDRE \skid_buffer_reg[49]
(.C(s_axi_aclk),
.CE(m_axi_rready),
.D(m_axi_rdata[49]),
.Q(\skid_buffer_reg_n_0_[49] ),
.R(1'b0));
FDRE \skid_buffer_reg[4]
(.C(s_axi_aclk),
.CE(m_axi_rready),
.D(m_axi_rdata[4]),
.Q(\skid_buffer_reg_n_0_[4] ),
.R(1'b0));
FDRE \skid_buffer_reg[50]
(.C(s_axi_aclk),
.CE(m_axi_rready),
.D(m_axi_rdata[50]),
.Q(\skid_buffer_reg_n_0_[50] ),
.R(1'b0));
FDRE \skid_buffer_reg[51]
(.C(s_axi_aclk),
.CE(m_axi_rready),
.D(m_axi_rdata[51]),
.Q(\skid_buffer_reg_n_0_[51] ),
.R(1'b0));
FDRE \skid_buffer_reg[52]
(.C(s_axi_aclk),
.CE(m_axi_rready),
.D(m_axi_rdata[52]),
.Q(\skid_buffer_reg_n_0_[52] ),
.R(1'b0));
FDRE \skid_buffer_reg[53]
(.C(s_axi_aclk),
.CE(m_axi_rready),
.D(m_axi_rdata[53]),
.Q(\skid_buffer_reg_n_0_[53] ),
.R(1'b0));
FDRE \skid_buffer_reg[54]
(.C(s_axi_aclk),
.CE(m_axi_rready),
.D(m_axi_rdata[54]),
.Q(\skid_buffer_reg_n_0_[54] ),
.R(1'b0));
FDRE \skid_buffer_reg[55]
(.C(s_axi_aclk),
.CE(m_axi_rready),
.D(m_axi_rdata[55]),
.Q(\skid_buffer_reg_n_0_[55] ),
.R(1'b0));
FDRE \skid_buffer_reg[56]
(.C(s_axi_aclk),
.CE(m_axi_rready),
.D(m_axi_rdata[56]),
.Q(\skid_buffer_reg_n_0_[56] ),
.R(1'b0));
FDRE \skid_buffer_reg[57]
(.C(s_axi_aclk),
.CE(m_axi_rready),
.D(m_axi_rdata[57]),
.Q(\skid_buffer_reg_n_0_[57] ),
.R(1'b0));
FDRE \skid_buffer_reg[58]
(.C(s_axi_aclk),
.CE(m_axi_rready),
.D(m_axi_rdata[58]),
.Q(\skid_buffer_reg_n_0_[58] ),
.R(1'b0));
FDRE \skid_buffer_reg[59]
(.C(s_axi_aclk),
.CE(m_axi_rready),
.D(m_axi_rdata[59]),
.Q(\skid_buffer_reg_n_0_[59] ),
.R(1'b0));
FDRE \skid_buffer_reg[5]
(.C(s_axi_aclk),
.CE(m_axi_rready),
.D(m_axi_rdata[5]),
.Q(\skid_buffer_reg_n_0_[5] ),
.R(1'b0));
FDRE \skid_buffer_reg[60]
(.C(s_axi_aclk),
.CE(m_axi_rready),
.D(m_axi_rdata[60]),
.Q(\skid_buffer_reg_n_0_[60] ),
.R(1'b0));
FDRE \skid_buffer_reg[61]
(.C(s_axi_aclk),
.CE(m_axi_rready),
.D(m_axi_rdata[61]),
.Q(\skid_buffer_reg_n_0_[61] ),
.R(1'b0));
FDRE \skid_buffer_reg[62]
(.C(s_axi_aclk),
.CE(m_axi_rready),
.D(m_axi_rdata[62]),
.Q(\skid_buffer_reg_n_0_[62] ),
.R(1'b0));
FDRE \skid_buffer_reg[63]
(.C(s_axi_aclk),
.CE(m_axi_rready),
.D(m_axi_rdata[63]),
.Q(\skid_buffer_reg_n_0_[63] ),
.R(1'b0));
FDRE \skid_buffer_reg[64]
(.C(s_axi_aclk),
.CE(m_axi_rready),
.D(m_axi_rresp[0]),
.Q(\skid_buffer_reg_n_0_[64] ),
.R(1'b0));
FDRE \skid_buffer_reg[65]
(.C(s_axi_aclk),
.CE(m_axi_rready),
.D(m_axi_rresp[1]),
.Q(\skid_buffer_reg_n_0_[65] ),
.R(1'b0));
FDRE \skid_buffer_reg[66]
(.C(s_axi_aclk),
.CE(m_axi_rready),
.D(m_axi_rlast),
.Q(\skid_buffer_reg_n_0_[66] ),
.R(1'b0));
FDRE \skid_buffer_reg[6]
(.C(s_axi_aclk),
.CE(m_axi_rready),
.D(m_axi_rdata[6]),
.Q(\skid_buffer_reg_n_0_[6] ),
.R(1'b0));
FDRE \skid_buffer_reg[7]
(.C(s_axi_aclk),
.CE(m_axi_rready),
.D(m_axi_rdata[7]),
.Q(\skid_buffer_reg_n_0_[7] ),
.R(1'b0));
FDRE \skid_buffer_reg[8]
(.C(s_axi_aclk),
.CE(m_axi_rready),
.D(m_axi_rdata[8]),
.Q(\skid_buffer_reg_n_0_[8] ),
.R(1'b0));
FDRE \skid_buffer_reg[9]
(.C(s_axi_aclk),
.CE(m_axi_rready),
.D(m_axi_rdata[9]),
.Q(\skid_buffer_reg_n_0_[9] ),
.R(1'b0));
endmodule
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