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module system_auto_us_0_generic_baseblocks_v2_1_0_command_fifo
(\USE_RTL_CURR_WORD.first_word_q_reg ,
SR,
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]_0 ,
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[0] ,
Q,
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]_1 ,
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[56] ,
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[7] ,
\USE_RTL_CURR_WORD.pre_next_word_q_reg[1] ,
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[48] ,
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[6] ,
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[40] ,
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[5] ,
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[32] ,
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[4] ,
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[24] ,
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[3] ,
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[16] ,
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[2] ,
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[8] ,
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[1] ,
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[0]_0 ,
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[0] ,
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg[63] ,
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg[55] ,
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg[47] ,
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg[39] ,
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg[31] ,
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg[23] ,
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg[15] ,
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg[7] ,
E,
s_axi_wready,
\USE_RTL_LENGTH.first_mi_word_q_reg ,
\USE_RTL_LENGTH.first_mi_word_q_reg_0 ,
D,
\USE_RTL_CURR_WORD.current_word_q_reg[2] ,
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[0]_1 ,
s_ready_i_reg,
cmd_push_block0,
m_axi_awvalid,
wrap_buffer_available_reg,
\USE_REGISTER.M_AXI_WVALID_q_reg ,
s_axi_aresetn,
s_axi_aclk,
s_axi_wlast,
p_251_in,
out,
\USE_RTL_CURR_WORD.current_word_q_reg[0] ,
\USE_REGISTER.M_AXI_WVALID_q_reg_0 ,
m_axi_wready,
\USE_REGISTER.M_AXI_WVALID_q_reg_1 ,
wrap_buffer_available,
s_axi_wvalid,
first_word_q,
\USE_RTL_CURR_WORD.current_word_q_reg[2]_0 ,
s_axi_wstrb,
cmd_push_block,
sr_awvalid,
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28]_0 ,
\USE_RTL_LENGTH.length_counter_q_reg[2] ,
\USE_RTL_LENGTH.length_counter_q_reg[5] ,
\USE_RTL_LENGTH.length_counter_q_reg[3] ,
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[7]_0 ,
\USE_RTL_CURR_WORD.pre_next_word_q_reg[2] ,
\USE_RTL_CURR_WORD.pre_next_word_q_reg[2]_0 ,
\USE_RTL_CURR_WORD.pre_next_word_q_reg[1]_0 ,
\USE_RTL_LENGTH.length_counter_q_reg[0] ,
m_axi_awready,
in);
output \USE_RTL_CURR_WORD.first_word_q_reg ;
output [0:0]SR;
output \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]_0 ;
output \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[0] ;
output [14:0]Q;
output \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]_1 ;
output \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[56] ;
output \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[7] ;
output \USE_RTL_CURR_WORD.pre_next_word_q_reg[1] ;
output \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[48] ;
output \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[6] ;
output \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[40] ;
output \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[5] ;
output \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[32] ;
output \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[4] ;
output \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[24] ;
output \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[3] ;
output \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[16] ;
output \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[2] ;
output \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[8] ;
output \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[1] ;
output \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[0]_0 ;
output \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[0] ;
output [0:0]\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg[63] ;
output [0:0]\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg[55] ;
output [0:0]\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg[47] ;
output [0:0]\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg[39] ;
output [0:0]\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg[31] ;
output [0:0]\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg[23] ;
output [0:0]\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg[15] ;
output [0:0]\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg[7] ;
output [0:0]E;
output s_axi_wready;
output \USE_RTL_LENGTH.first_mi_word_q_reg ;
output \USE_RTL_LENGTH.first_mi_word_q_reg_0 ;
output [2:0]D;
output [2:0]\USE_RTL_CURR_WORD.current_word_q_reg[2] ;
output \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[0]_1 ;
output s_ready_i_reg;
output cmd_push_block0;
output m_axi_awvalid;
output wrap_buffer_available_reg;
output \USE_REGISTER.M_AXI_WVALID_q_reg ;
input s_axi_aresetn;
input s_axi_aclk;
input s_axi_wlast;
input p_251_in;
input out;
input \USE_RTL_CURR_WORD.current_word_q_reg[0] ;
input \USE_REGISTER.M_AXI_WVALID_q_reg_0 ;
input m_axi_wready;
input \USE_REGISTER.M_AXI_WVALID_q_reg_1 ;
input wrap_buffer_available;
input s_axi_wvalid;
input first_word_q;
input [2:0]\USE_RTL_CURR_WORD.current_word_q_reg[2]_0 ;
input [3:0]s_axi_wstrb;
input cmd_push_block;
input sr_awvalid;
input \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28]_0 ;
input \USE_RTL_LENGTH.length_counter_q_reg[2] ;
input \USE_RTL_LENGTH.length_counter_q_reg[5] ;
input \USE_RTL_LENGTH.length_counter_q_reg[3] ;
input \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[7]_0 ;
input [2:0]\USE_RTL_CURR_WORD.pre_next_word_q_reg[2] ;
input \USE_RTL_CURR_WORD.pre_next_word_q_reg[2]_0 ;
input \USE_RTL_CURR_WORD.pre_next_word_q_reg[1]_0 ;
input \USE_RTL_LENGTH.length_counter_q_reg[0] ;
input m_axi_awready;
input [27:0]in;
wire [2:0]D;
wire [0:0]E;
wire [14:0]Q;
wire [0:0]SR;
wire \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[29]_i_1_n_0 ;
wire \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[29]_i_3_n_0 ;
wire \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28]_0 ;
wire \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]_0 ;
wire \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]_1 ;
wire \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[7]_0 ;
wire \USE_REGISTER.M_AXI_WVALID_q_i_2_n_0 ;
wire \USE_REGISTER.M_AXI_WVALID_q_i_3_n_0 ;
wire \USE_REGISTER.M_AXI_WVALID_q_reg ;
wire \USE_REGISTER.M_AXI_WVALID_q_reg_0 ;
wire \USE_REGISTER.M_AXI_WVALID_q_reg_1 ;
wire \USE_RTL_ADDR.addr_q[0]_i_1_n_0 ;
wire \USE_RTL_ADDR.addr_q[1]_i_1_n_0 ;
wire \USE_RTL_ADDR.addr_q[2]_i_1_n_0 ;
wire \USE_RTL_ADDR.addr_q[3]_i_1_n_0 ;
wire \USE_RTL_ADDR.addr_q[4]_i_2_n_0 ;
wire \USE_RTL_ADDR.addr_q[4]_i_3_n_0 ;
wire [4:0]\USE_RTL_ADDR.addr_q_reg__0 ;
wire \USE_RTL_CURR_WORD.current_word_q_reg[0] ;
wire [2:0]\USE_RTL_CURR_WORD.current_word_q_reg[2] ;
wire [2:0]\USE_RTL_CURR_WORD.current_word_q_reg[2]_0 ;
wire \USE_RTL_CURR_WORD.first_word_q_reg ;
wire \USE_RTL_CURR_WORD.pre_next_word_q[2]_i_3_n_0 ;
wire \USE_RTL_CURR_WORD.pre_next_word_q_reg[1] ;
wire \USE_RTL_CURR_WORD.pre_next_word_q_reg[1]_0 ;
wire [2:0]\USE_RTL_CURR_WORD.pre_next_word_q_reg[2] ;
wire \USE_RTL_CURR_WORD.pre_next_word_q_reg[2]_0 ;
wire \USE_RTL_FIFO.data_srl_reg[31][0]_srl32_n_0 ;
wire \USE_RTL_FIFO.data_srl_reg[31][10]_srl32_n_0 ;
wire \USE_RTL_FIFO.data_srl_reg[31][11]_srl32_n_0 ;
wire \USE_RTL_FIFO.data_srl_reg[31][12]_srl32_n_0 ;
wire \USE_RTL_FIFO.data_srl_reg[31][13]_srl32_n_0 ;
wire \USE_RTL_FIFO.data_srl_reg[31][16]_srl32_n_0 ;
wire \USE_RTL_FIFO.data_srl_reg[31][17]_srl32_n_0 ;
wire \USE_RTL_FIFO.data_srl_reg[31][18]_srl32_n_0 ;
wire \USE_RTL_FIFO.data_srl_reg[31][19]_srl32_n_0 ;
wire \USE_RTL_FIFO.data_srl_reg[31][1]_srl32_n_0 ;
wire \USE_RTL_FIFO.data_srl_reg[31][20]_srl32_n_0 ;
wire \USE_RTL_FIFO.data_srl_reg[31][21]_srl32_n_0 ;
wire \USE_RTL_FIFO.data_srl_reg[31][22]_srl32_n_0 ;
wire \USE_RTL_FIFO.data_srl_reg[31][23]_srl32_n_0 ;
wire \USE_RTL_FIFO.data_srl_reg[31][24]_srl32_n_0 ;
wire \USE_RTL_FIFO.data_srl_reg[31][25]_srl32_n_0 ;
wire \USE_RTL_FIFO.data_srl_reg[31][26]_srl32_n_0 ;
wire \USE_RTL_FIFO.data_srl_reg[31][27]_srl32_n_0 ;
wire \USE_RTL_FIFO.data_srl_reg[31][28]_srl32_n_0 ;
wire \USE_RTL_FIFO.data_srl_reg[31][29]_srl32_n_0 ;
wire \USE_RTL_FIFO.data_srl_reg[31][2]_srl32_n_0 ;
wire \USE_RTL_FIFO.data_srl_reg[31][3]_srl32_n_0 ;
wire \USE_RTL_FIFO.data_srl_reg[31][4]_srl32_n_0 ;
wire \USE_RTL_FIFO.data_srl_reg[31][5]_srl32_n_0 ;
wire \USE_RTL_FIFO.data_srl_reg[31][6]_srl32_n_0 ;
wire \USE_RTL_FIFO.data_srl_reg[31][7]_srl32_n_0 ;
wire \USE_RTL_FIFO.data_srl_reg[31][8]_srl32_n_0 ;
wire \USE_RTL_FIFO.data_srl_reg[31][9]_srl32_n_0 ;
wire \USE_RTL_LENGTH.first_mi_word_q_reg ;
wire \USE_RTL_LENGTH.first_mi_word_q_reg_0 ;
wire \USE_RTL_LENGTH.length_counter_q_reg[0] ;
wire \USE_RTL_LENGTH.length_counter_q_reg[2] ;
wire \USE_RTL_LENGTH.length_counter_q_reg[3] ;
wire \USE_RTL_LENGTH.length_counter_q_reg[5] ;
wire \USE_RTL_VALID_WRITE.buffer_Full_q_i_1_n_0 ;
wire \USE_RTL_VALID_WRITE.buffer_Full_q_i_2_n_0 ;
wire \USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst/wrap_buffer_available0 ;
wire \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[0] ;
wire \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[0]_0 ;
wire \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[0]_1 ;
wire \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[0] ;
wire \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q[7]_i_3_n_0 ;
wire [0:0]\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg[7] ;
wire \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[8] ;
wire \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[1] ;
wire [0:0]\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg[15] ;
wire \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[16] ;
wire \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[2] ;
wire [0:0]\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg[23] ;
wire \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[24] ;
wire \WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[3] ;
wire [0:0]\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg[31] ;
wire \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[32] ;
wire \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[4] ;
wire [0:0]\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg[39] ;
wire \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[40] ;
wire \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[5] ;
wire [0:0]\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg[47] ;
wire \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[48] ;
wire \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[6] ;
wire [0:0]\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg[55] ;
wire \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[56] ;
wire \WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[7] ;
wire [0:0]\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg[63] ;
wire addr_q;
wire buffer_Full_q;
wire [2:1]cmd_last_word;
wire cmd_push_block;
wire cmd_push_block0;
wire [2:0]cmd_step;
wire data_Exists_I;
wire data_Exists_I_i_2_n_0;
wire first_word_q;
wire [27:0]in;
wire m_axi_awready;
wire m_axi_awvalid;
wire m_axi_wready;
wire next_Data_Exists;
wire out;
wire p_251_in;
wire s_axi_aclk;
wire s_axi_aresetn;
wire s_axi_wlast;
wire s_axi_wready;
wire [3:0]s_axi_wstrb;
wire s_axi_wvalid;
wire s_ready_i_reg;
wire sr_awvalid;
wire valid_Write;
wire wr_cmd_complete_wrap;
wire [2:1]wr_cmd_first_word;
wire [2:0]wr_cmd_mask;
wire [0:0]wr_cmd_next_word;
wire [2:2]wr_cmd_offset;
wire wrap_buffer_available;
wire wrap_buffer_available_reg;
wire \NLW_USE_RTL_FIFO.data_srl_reg[31][0]_srl32_Q31_UNCONNECTED ;
wire \NLW_USE_RTL_FIFO.data_srl_reg[31][10]_srl32_Q31_UNCONNECTED ;
wire \NLW_USE_RTL_FIFO.data_srl_reg[31][11]_srl32_Q31_UNCONNECTED ;
wire \NLW_USE_RTL_FIFO.data_srl_reg[31][12]_srl32_Q31_UNCONNECTED ;
wire \NLW_USE_RTL_FIFO.data_srl_reg[31][13]_srl32_Q31_UNCONNECTED ;
wire \NLW_USE_RTL_FIFO.data_srl_reg[31][16]_srl32_Q31_UNCONNECTED ;
wire \NLW_USE_RTL_FIFO.data_srl_reg[31][17]_srl32_Q31_UNCONNECTED ;
wire \NLW_USE_RTL_FIFO.data_srl_reg[31][18]_srl32_Q31_UNCONNECTED ;
wire \NLW_USE_RTL_FIFO.data_srl_reg[31][19]_srl32_Q31_UNCONNECTED ;
wire \NLW_USE_RTL_FIFO.data_srl_reg[31][1]_srl32_Q31_UNCONNECTED ;
wire \NLW_USE_RTL_FIFO.data_srl_reg[31][20]_srl32_Q31_UNCONNECTED ;
wire \NLW_USE_RTL_FIFO.data_srl_reg[31][21]_srl32_Q31_UNCONNECTED ;
wire \NLW_USE_RTL_FIFO.data_srl_reg[31][22]_srl32_Q31_UNCONNECTED ;
wire \NLW_USE_RTL_FIFO.data_srl_reg[31][23]_srl32_Q31_UNCONNECTED ;
wire \NLW_USE_RTL_FIFO.data_srl_reg[31][24]_srl32_Q31_UNCONNECTED ;
wire \NLW_USE_RTL_FIFO.data_srl_reg[31][25]_srl32_Q31_UNCONNECTED ;
wire \NLW_USE_RTL_FIFO.data_srl_reg[31][26]_srl32_Q31_UNCONNECTED ;
wire \NLW_USE_RTL_FIFO.data_srl_reg[31][27]_srl32_Q31_UNCONNECTED ;
wire \NLW_USE_RTL_FIFO.data_srl_reg[31][28]_srl32_Q31_UNCONNECTED ;
wire \NLW_USE_RTL_FIFO.data_srl_reg[31][29]_srl32_Q31_UNCONNECTED ;
wire \NLW_USE_RTL_FIFO.data_srl_reg[31][2]_srl32_Q31_UNCONNECTED ;
wire \NLW_USE_RTL_FIFO.data_srl_reg[31][3]_srl32_Q31_UNCONNECTED ;
wire \NLW_USE_RTL_FIFO.data_srl_reg[31][4]_srl32_Q31_UNCONNECTED ;
wire \NLW_USE_RTL_FIFO.data_srl_reg[31][5]_srl32_Q31_UNCONNECTED ;
wire \NLW_USE_RTL_FIFO.data_srl_reg[31][6]_srl32_Q31_UNCONNECTED ;
wire \NLW_USE_RTL_FIFO.data_srl_reg[31][7]_srl32_Q31_UNCONNECTED ;
wire \NLW_USE_RTL_FIFO.data_srl_reg[31][8]_srl32_Q31_UNCONNECTED ;
wire \NLW_USE_RTL_FIFO.data_srl_reg[31][9]_srl32_Q31_UNCONNECTED ;
LUT6 #(
.INIT(64'hAA080000FFFFFFFF))
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[29]_i_1
(.I0(s_axi_wlast),
.I1(\USE_RTL_CURR_WORD.current_word_q_reg[0] ),
.I2(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[29]_i_3_n_0 ),
.I3(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]_0 ),
.I4(\USE_REGISTER.M_AXI_WVALID_q_reg_0 ),
.I5(\USE_RTL_CURR_WORD.first_word_q_reg ),
.O(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[29]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFFFFFEFFFF))
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[29]_i_3
(.I0(\USE_RTL_LENGTH.first_mi_word_q_reg ),
.I1(\USE_RTL_LENGTH.length_counter_q_reg[5] ),
.I2(\USE_RTL_LENGTH.length_counter_q_reg[3] ),
.I3(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[7]_0 ),
.I4(Q[13]),
.I5(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]_1 ),
.O(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[29]_i_3_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFF0001FFFF))
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[29]_i_4
(.I0(\USE_RTL_CURR_WORD.current_word_q_reg[2] [2]),
.I1(\USE_RTL_CURR_WORD.current_word_q_reg[2] [1]),
.I2(wr_cmd_complete_wrap),
.I3(\USE_RTL_CURR_WORD.current_word_q_reg[2] [0]),
.I4(Q[13]),
.I5(Q[14]),
.O(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]_0 ));
LUT5 #(
.INIT(32'h6665666A))
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[29]_i_8
(.I0(cmd_last_word[2]),
.I1(wr_cmd_first_word[2]),
.I2(first_word_q),
.I3(Q[14]),
.I4(\USE_RTL_CURR_WORD.current_word_q_reg[2]_0 [2]),
.O(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]_1 ));
FDRE \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[0]
(.C(s_axi_aclk),
.CE(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[29]_i_1_n_0 ),
.D(\USE_RTL_FIFO.data_srl_reg[31][0]_srl32_n_0 ),
.Q(Q[0]),
.R(s_axi_aresetn));
FDRE \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[10]
(.C(s_axi_aclk),
.CE(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[29]_i_1_n_0 ),
.D(\USE_RTL_FIFO.data_srl_reg[31][10]_srl32_n_0 ),
.Q(cmd_step[2]),
.R(s_axi_aresetn));
FDRE \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[11]
(.C(s_axi_aclk),
.CE(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[29]_i_1_n_0 ),
.D(\USE_RTL_FIFO.data_srl_reg[31][11]_srl32_n_0 ),
.Q(wr_cmd_mask[0]),
.R(s_axi_aresetn));
FDRE \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[12]
(.C(s_axi_aclk),
.CE(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[29]_i_1_n_0 ),
.D(\USE_RTL_FIFO.data_srl_reg[31][12]_srl32_n_0 ),
.Q(wr_cmd_mask[1]),
.R(s_axi_aresetn));
FDRE \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[13]
(.C(s_axi_aclk),
.CE(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[29]_i_1_n_0 ),
.D(\USE_RTL_FIFO.data_srl_reg[31][13]_srl32_n_0 ),
.Q(wr_cmd_mask[2]),
.R(s_axi_aresetn));
FDRE \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[16]
(.C(s_axi_aclk),
.CE(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[29]_i_1_n_0 ),
.D(\USE_RTL_FIFO.data_srl_reg[31][16]_srl32_n_0 ),
.Q(wr_cmd_offset),
.R(s_axi_aresetn));
FDRE \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[17]
(.C(s_axi_aclk),
.CE(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[29]_i_1_n_0 ),
.D(\USE_RTL_FIFO.data_srl_reg[31][17]_srl32_n_0 ),
.Q(Q[8]),
.R(s_axi_aresetn));
FDRE \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[18]
(.C(s_axi_aclk),
.CE(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[29]_i_1_n_0 ),
.D(\USE_RTL_FIFO.data_srl_reg[31][18]_srl32_n_0 ),
.Q(cmd_last_word[1]),
.R(s_axi_aresetn));
FDRE \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[19]
(.C(s_axi_aclk),
.CE(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[29]_i_1_n_0 ),
.D(\USE_RTL_FIFO.data_srl_reg[31][19]_srl32_n_0 ),
.Q(cmd_last_word[2]),
.R(s_axi_aresetn));
FDRE \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[1]
(.C(s_axi_aclk),
.CE(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[29]_i_1_n_0 ),
.D(\USE_RTL_FIFO.data_srl_reg[31][1]_srl32_n_0 ),
.Q(Q[1]),
.R(s_axi_aresetn));
FDRE \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[20]
(.C(s_axi_aclk),
.CE(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[29]_i_1_n_0 ),
.D(\USE_RTL_FIFO.data_srl_reg[31][20]_srl32_n_0 ),
.Q(wr_cmd_next_word),
.R(s_axi_aresetn));
FDRE \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[21]
(.C(s_axi_aclk),
.CE(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[29]_i_1_n_0 ),
.D(\USE_RTL_FIFO.data_srl_reg[31][21]_srl32_n_0 ),
.Q(Q[9]),
.R(s_axi_aresetn));
FDRE \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[22]
(.C(s_axi_aclk),
.CE(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[29]_i_1_n_0 ),
.D(\USE_RTL_FIFO.data_srl_reg[31][22]_srl32_n_0 ),
.Q(Q[10]),
.R(s_axi_aresetn));
FDRE \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[23]
(.C(s_axi_aclk),
.CE(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[29]_i_1_n_0 ),
.D(\USE_RTL_FIFO.data_srl_reg[31][23]_srl32_n_0 ),
.Q(Q[11]),
.R(s_axi_aresetn));
FDRE \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[24]
(.C(s_axi_aclk),
.CE(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[29]_i_1_n_0 ),
.D(\USE_RTL_FIFO.data_srl_reg[31][24]_srl32_n_0 ),
.Q(wr_cmd_first_word[1]),
.R(s_axi_aresetn));
FDRE \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[25]
(.C(s_axi_aclk),
.CE(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[29]_i_1_n_0 ),
.D(\USE_RTL_FIFO.data_srl_reg[31][25]_srl32_n_0 ),
.Q(wr_cmd_first_word[2]),
.R(s_axi_aresetn));
FDRE \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[26]
(.C(s_axi_aclk),
.CE(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[29]_i_1_n_0 ),
.D(\USE_RTL_FIFO.data_srl_reg[31][26]_srl32_n_0 ),
.Q(Q[12]),
.R(s_axi_aresetn));
FDRE \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[27]
(.C(s_axi_aclk),
.CE(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[29]_i_1_n_0 ),
.D(\USE_RTL_FIFO.data_srl_reg[31][27]_srl32_n_0 ),
.Q(wr_cmd_complete_wrap),
.R(s_axi_aresetn));
FDRE \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28]
(.C(s_axi_aclk),
.CE(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[29]_i_1_n_0 ),
.D(\USE_RTL_FIFO.data_srl_reg[31][28]_srl32_n_0 ),
.Q(Q[13]),
.R(s_axi_aresetn));
FDRE \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]
(.C(s_axi_aclk),
.CE(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[29]_i_1_n_0 ),
.D(\USE_RTL_FIFO.data_srl_reg[31][29]_srl32_n_0 ),
.Q(Q[14]),
.R(s_axi_aresetn));
FDRE \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[2]
(.C(s_axi_aclk),
.CE(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[29]_i_1_n_0 ),
.D(\USE_RTL_FIFO.data_srl_reg[31][2]_srl32_n_0 ),
.Q(Q[2]),
.R(s_axi_aresetn));
FDRE \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[3]
(.C(s_axi_aclk),
.CE(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[29]_i_1_n_0 ),
.D(\USE_RTL_FIFO.data_srl_reg[31][3]_srl32_n_0 ),
.Q(Q[3]),
.R(s_axi_aresetn));
FDRE \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[4]
(.C(s_axi_aclk),
.CE(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[29]_i_1_n_0 ),
.D(\USE_RTL_FIFO.data_srl_reg[31][4]_srl32_n_0 ),
.Q(Q[4]),
.R(s_axi_aresetn));
FDRE \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[5]
(.C(s_axi_aclk),
.CE(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[29]_i_1_n_0 ),
.D(\USE_RTL_FIFO.data_srl_reg[31][5]_srl32_n_0 ),
.Q(Q[5]),
.R(s_axi_aresetn));
FDRE \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[6]
(.C(s_axi_aclk),
.CE(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[29]_i_1_n_0 ),
.D(\USE_RTL_FIFO.data_srl_reg[31][6]_srl32_n_0 ),
.Q(Q[6]),
.R(s_axi_aresetn));
FDRE \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[7]
(.C(s_axi_aclk),
.CE(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[29]_i_1_n_0 ),
.D(\USE_RTL_FIFO.data_srl_reg[31][7]_srl32_n_0 ),
.Q(Q[7]),
.R(s_axi_aresetn));
FDRE \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[8]
(.C(s_axi_aclk),
.CE(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[29]_i_1_n_0 ),
.D(\USE_RTL_FIFO.data_srl_reg[31][8]_srl32_n_0 ),
.Q(cmd_step[0]),
.R(s_axi_aresetn));
FDRE \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[9]
(.C(s_axi_aclk),
.CE(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[29]_i_1_n_0 ),
.D(\USE_RTL_FIFO.data_srl_reg[31][9]_srl32_n_0 ),
.Q(cmd_step[1]),
.R(s_axi_aresetn));
FDRE \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg
(.C(s_axi_aclk),
.CE(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[29]_i_1_n_0 ),
.D(data_Exists_I),
.Q(\USE_RTL_CURR_WORD.first_word_q_reg ),
.R(s_axi_aresetn));
LUT6 #(
.INIT(64'h0080FFFF00800080))
\USE_REGISTER.M_AXI_WVALID_q_i_1
(.I0(\USE_RTL_CURR_WORD.first_word_q_reg ),
.I1(\USE_REGISTER.M_AXI_WVALID_q_i_2_n_0 ),
.I2(s_axi_wvalid),
.I3(\USE_REGISTER.M_AXI_WVALID_q_i_3_n_0 ),
.I4(m_axi_wready),
.I5(\USE_REGISTER.M_AXI_WVALID_q_reg_1 ),
.O(\USE_REGISTER.M_AXI_WVALID_q_reg ));
LUT5 #(
.INIT(32'hAAAAABAA))
\USE_REGISTER.M_AXI_WVALID_q_i_2
(.I0(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]_0 ),
.I1(\USE_RTL_LENGTH.first_mi_word_q_reg ),
.I2(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28]_0 ),
.I3(\USE_RTL_LENGTH.first_mi_word_q_reg_0 ),
.I4(\USE_RTL_LENGTH.length_counter_q_reg[2] ),
.O(\USE_REGISTER.M_AXI_WVALID_q_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair53" *)
LUT3 #(
.INIT(8'h40))
\USE_REGISTER.M_AXI_WVALID_q_i_3
(.I0(wrap_buffer_available),
.I1(Q[12]),
.I2(\USE_RTL_CURR_WORD.first_word_q_reg ),
.O(\USE_REGISTER.M_AXI_WVALID_q_i_3_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair52" *)
LUT1 #(
.INIT(2'h1))
\USE_RTL_ADDR.addr_q[0]_i_1
(.I0(\USE_RTL_ADDR.addr_q_reg__0 [0]),
.O(\USE_RTL_ADDR.addr_q[0]_i_1_n_0 ));
LUT6 #(
.INIT(64'hAAAAAA9A55555565))
\USE_RTL_ADDR.addr_q[1]_i_1
(.I0(\USE_RTL_ADDR.addr_q_reg__0 [0]),
.I1(cmd_push_block),
.I2(sr_awvalid),
.I3(buffer_Full_q),
.I4(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[29]_i_1_n_0 ),
.I5(\USE_RTL_ADDR.addr_q_reg__0 [1]),
.O(\USE_RTL_ADDR.addr_q[1]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair52" *)
LUT5 #(
.INIT(32'hBF40F40B))
\USE_RTL_ADDR.addr_q[2]_i_1
(.I0(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[29]_i_1_n_0 ),
.I1(valid_Write),
.I2(\USE_RTL_ADDR.addr_q_reg__0 [0]),
.I3(\USE_RTL_ADDR.addr_q_reg__0 [2]),
.I4(\USE_RTL_ADDR.addr_q_reg__0 [1]),
.O(\USE_RTL_ADDR.addr_q[2]_i_1_n_0 ));
LUT6 #(
.INIT(64'hDFFF2000FFBA0045))
\USE_RTL_ADDR.addr_q[3]_i_1
(.I0(\USE_RTL_ADDR.addr_q_reg__0 [1]),
.I1(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[29]_i_1_n_0 ),
.I2(valid_Write),
.I3(\USE_RTL_ADDR.addr_q_reg__0 [0]),
.I4(\USE_RTL_ADDR.addr_q_reg__0 [3]),
.I5(\USE_RTL_ADDR.addr_q_reg__0 [2]),
.O(\USE_RTL_ADDR.addr_q[3]_i_1_n_0 ));
LUT6 #(
.INIT(64'h80808080800C8080))
\USE_RTL_ADDR.addr_q[4]_i_1
(.I0(data_Exists_I_i_2_n_0),
.I1(data_Exists_I),
.I2(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[29]_i_1_n_0 ),
.I3(buffer_Full_q),
.I4(sr_awvalid),
.I5(cmd_push_block),
.O(addr_q));
LUT6 #(
.INIT(64'h6AAAAAAAAAAAAAA9))
\USE_RTL_ADDR.addr_q[4]_i_2
(.I0(\USE_RTL_ADDR.addr_q_reg__0 [4]),
.I1(\USE_RTL_ADDR.addr_q_reg__0 [3]),
.I2(\USE_RTL_ADDR.addr_q_reg__0 [1]),
.I3(\USE_RTL_ADDR.addr_q[4]_i_3_n_0 ),
.I4(\USE_RTL_ADDR.addr_q_reg__0 [0]),
.I5(\USE_RTL_ADDR.addr_q_reg__0 [2]),
.O(\USE_RTL_ADDR.addr_q[4]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair55" *)
LUT4 #(
.INIT(16'h0004))
\USE_RTL_ADDR.addr_q[4]_i_3
(.I0(cmd_push_block),
.I1(sr_awvalid),
.I2(buffer_Full_q),
.I3(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[29]_i_1_n_0 ),
.O(\USE_RTL_ADDR.addr_q[4]_i_3_n_0 ));
FDRE \USE_RTL_ADDR.addr_q_reg[0]
(.C(s_axi_aclk),
.CE(addr_q),
.D(\USE_RTL_ADDR.addr_q[0]_i_1_n_0 ),
.Q(\USE_RTL_ADDR.addr_q_reg__0 [0]),
.R(s_axi_aresetn));
FDRE \USE_RTL_ADDR.addr_q_reg[1]
(.C(s_axi_aclk),
.CE(addr_q),
.D(\USE_RTL_ADDR.addr_q[1]_i_1_n_0 ),
.Q(\USE_RTL_ADDR.addr_q_reg__0 [1]),
.R(s_axi_aresetn));
FDRE \USE_RTL_ADDR.addr_q_reg[2]
(.C(s_axi_aclk),
.CE(addr_q),
.D(\USE_RTL_ADDR.addr_q[2]_i_1_n_0 ),
.Q(\USE_RTL_ADDR.addr_q_reg__0 [2]),
.R(s_axi_aresetn));
FDRE \USE_RTL_ADDR.addr_q_reg[3]
(.C(s_axi_aclk),
.CE(addr_q),
.D(\USE_RTL_ADDR.addr_q[3]_i_1_n_0 ),
.Q(\USE_RTL_ADDR.addr_q_reg__0 [3]),
.R(s_axi_aresetn));
FDRE \USE_RTL_ADDR.addr_q_reg[4]
(.C(s_axi_aclk),
.CE(addr_q),
.D(\USE_RTL_ADDR.addr_q[4]_i_2_n_0 ),
.Q(\USE_RTL_ADDR.addr_q_reg__0 [4]),
.R(s_axi_aresetn));
LUT5 #(
.INIT(32'h888A8880))
\USE_RTL_CURR_WORD.current_word_q[0]_i_1
(.I0(wr_cmd_mask[0]),
.I1(wr_cmd_next_word),
.I2(first_word_q),
.I3(Q[14]),
.I4(\USE_RTL_CURR_WORD.pre_next_word_q_reg[2] [0]),
.O(\USE_RTL_CURR_WORD.current_word_q_reg[2] [0]));
LUT5 #(
.INIT(32'h888A8880))
\USE_RTL_CURR_WORD.current_word_q[1]_i_1
(.I0(wr_cmd_mask[1]),
.I1(Q[9]),
.I2(first_word_q),
.I3(Q[14]),
.I4(\USE_RTL_CURR_WORD.pre_next_word_q_reg[2] [1]),
.O(\USE_RTL_CURR_WORD.current_word_q_reg[2] [1]));
LUT5 #(
.INIT(32'h888A8880))
\USE_RTL_CURR_WORD.current_word_q[2]_i_1
(.I0(wr_cmd_mask[2]),
.I1(Q[10]),
.I2(first_word_q),
.I3(Q[14]),
.I4(\USE_RTL_CURR_WORD.pre_next_word_q_reg[2] [2]),
.O(\USE_RTL_CURR_WORD.current_word_q_reg[2] [2]));
LUT6 #(
.INIT(64'hAAAA08AA00000000))
\USE_RTL_CURR_WORD.first_word_q_i_1
(.I0(s_axi_wvalid),
.I1(Q[12]),
.I2(wrap_buffer_available),
.I3(\USE_REGISTER.M_AXI_WVALID_q_reg_1 ),
.I4(m_axi_wready),
.I5(\USE_RTL_CURR_WORD.first_word_q_reg ),
.O(E));
LUT6 #(
.INIT(64'h0002AAA2AAA80008))
\USE_RTL_CURR_WORD.pre_next_word_q[0]_i_1
(.I0(wr_cmd_mask[0]),
.I1(\USE_RTL_CURR_WORD.pre_next_word_q_reg[2] [0]),
.I2(Q[14]),
.I3(first_word_q),
.I4(wr_cmd_next_word),
.I5(cmd_step[0]),
.O(D[0]));
LUT6 #(
.INIT(64'h8882228222288828))
\USE_RTL_CURR_WORD.pre_next_word_q[1]_i_1
(.I0(wr_cmd_mask[1]),
.I1(cmd_step[1]),
.I2(Q[9]),
.I3(\USE_RTL_CURR_WORD.pre_next_word_q_reg[1] ),
.I4(\USE_RTL_CURR_WORD.pre_next_word_q_reg[2] [1]),
.I5(\USE_RTL_CURR_WORD.pre_next_word_q[2]_i_3_n_0 ),
.O(D[1]));
(* SOFT_HLUTNM = "soft_lutpair51" *)
LUT2 #(
.INIT(4'h1))
\USE_RTL_CURR_WORD.pre_next_word_q[1]_i_2
(.I0(Q[14]),
.I1(first_word_q),
.O(\USE_RTL_CURR_WORD.pre_next_word_q_reg[1] ));
LUT6 #(
.INIT(64'h2882828228282882))
\USE_RTL_CURR_WORD.pre_next_word_q[2]_i_1
(.I0(wr_cmd_mask[2]),
.I1(cmd_step[2]),
.I2(\USE_RTL_CURR_WORD.pre_next_word_q_reg[2]_0 ),
.I3(cmd_step[1]),
.I4(\USE_RTL_CURR_WORD.pre_next_word_q[2]_i_3_n_0 ),
.I5(\USE_RTL_CURR_WORD.pre_next_word_q_reg[1]_0 ),
.O(D[2]));
LUT5 #(
.INIT(32'h888A8880))
\USE_RTL_CURR_WORD.pre_next_word_q[2]_i_3
(.I0(cmd_step[0]),
.I1(wr_cmd_next_word),
.I2(first_word_q),
.I3(Q[14]),
.I4(\USE_RTL_CURR_WORD.pre_next_word_q_reg[2] [0]),
.O(\USE_RTL_CURR_WORD.pre_next_word_q[2]_i_3_n_0 ));
(* srl_bus_name = "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.write_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] " *)
(* srl_name = "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.write_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][0]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\USE_RTL_FIFO.data_srl_reg[31][0]_srl32
(.A(\USE_RTL_ADDR.addr_q_reg__0 ),
.CE(valid_Write),
.CLK(s_axi_aclk),
.D(in[0]),
.Q(\USE_RTL_FIFO.data_srl_reg[31][0]_srl32_n_0 ),
.Q31(\NLW_USE_RTL_FIFO.data_srl_reg[31][0]_srl32_Q31_UNCONNECTED ));
LUT3 #(
.INIT(8'h04))
\USE_RTL_FIFO.data_srl_reg[31][0]_srl32_i_1
(.I0(buffer_Full_q),
.I1(sr_awvalid),
.I2(cmd_push_block),
.O(valid_Write));
(* srl_bus_name = "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.write_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] " *)
(* srl_name = "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.write_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][10]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\USE_RTL_FIFO.data_srl_reg[31][10]_srl32
(.A(\USE_RTL_ADDR.addr_q_reg__0 ),
.CE(valid_Write),
.CLK(s_axi_aclk),
.D(in[10]),
.Q(\USE_RTL_FIFO.data_srl_reg[31][10]_srl32_n_0 ),
.Q31(\NLW_USE_RTL_FIFO.data_srl_reg[31][10]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.write_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] " *)
(* srl_name = "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.write_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][11]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\USE_RTL_FIFO.data_srl_reg[31][11]_srl32
(.A(\USE_RTL_ADDR.addr_q_reg__0 ),
.CE(valid_Write),
.CLK(s_axi_aclk),
.D(in[11]),
.Q(\USE_RTL_FIFO.data_srl_reg[31][11]_srl32_n_0 ),
.Q31(\NLW_USE_RTL_FIFO.data_srl_reg[31][11]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.write_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] " *)
(* srl_name = "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.write_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][12]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\USE_RTL_FIFO.data_srl_reg[31][12]_srl32
(.A(\USE_RTL_ADDR.addr_q_reg__0 ),
.CE(valid_Write),
.CLK(s_axi_aclk),
.D(in[12]),
.Q(\USE_RTL_FIFO.data_srl_reg[31][12]_srl32_n_0 ),
.Q31(\NLW_USE_RTL_FIFO.data_srl_reg[31][12]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.write_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] " *)
(* srl_name = "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.write_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][13]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\USE_RTL_FIFO.data_srl_reg[31][13]_srl32
(.A(\USE_RTL_ADDR.addr_q_reg__0 ),
.CE(valid_Write),
.CLK(s_axi_aclk),
.D(in[13]),
.Q(\USE_RTL_FIFO.data_srl_reg[31][13]_srl32_n_0 ),
.Q31(\NLW_USE_RTL_FIFO.data_srl_reg[31][13]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.write_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] " *)
(* srl_name = "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.write_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][16]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\USE_RTL_FIFO.data_srl_reg[31][16]_srl32
(.A(\USE_RTL_ADDR.addr_q_reg__0 ),
.CE(valid_Write),
.CLK(s_axi_aclk),
.D(in[14]),
.Q(\USE_RTL_FIFO.data_srl_reg[31][16]_srl32_n_0 ),
.Q31(\NLW_USE_RTL_FIFO.data_srl_reg[31][16]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.write_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] " *)
(* srl_name = "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.write_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][17]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\USE_RTL_FIFO.data_srl_reg[31][17]_srl32
(.A(\USE_RTL_ADDR.addr_q_reg__0 ),
.CE(valid_Write),
.CLK(s_axi_aclk),
.D(in[15]),
.Q(\USE_RTL_FIFO.data_srl_reg[31][17]_srl32_n_0 ),
.Q31(\NLW_USE_RTL_FIFO.data_srl_reg[31][17]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.write_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] " *)
(* srl_name = "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.write_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][18]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\USE_RTL_FIFO.data_srl_reg[31][18]_srl32
(.A(\USE_RTL_ADDR.addr_q_reg__0 ),
.CE(valid_Write),
.CLK(s_axi_aclk),
.D(in[16]),
.Q(\USE_RTL_FIFO.data_srl_reg[31][18]_srl32_n_0 ),
.Q31(\NLW_USE_RTL_FIFO.data_srl_reg[31][18]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.write_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] " *)
(* srl_name = "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.write_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][19]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\USE_RTL_FIFO.data_srl_reg[31][19]_srl32
(.A(\USE_RTL_ADDR.addr_q_reg__0 ),
.CE(valid_Write),
.CLK(s_axi_aclk),
.D(in[17]),
.Q(\USE_RTL_FIFO.data_srl_reg[31][19]_srl32_n_0 ),
.Q31(\NLW_USE_RTL_FIFO.data_srl_reg[31][19]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.write_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] " *)
(* srl_name = "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.write_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][1]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\USE_RTL_FIFO.data_srl_reg[31][1]_srl32
(.A(\USE_RTL_ADDR.addr_q_reg__0 ),
.CE(valid_Write),
.CLK(s_axi_aclk),
.D(in[1]),
.Q(\USE_RTL_FIFO.data_srl_reg[31][1]_srl32_n_0 ),
.Q31(\NLW_USE_RTL_FIFO.data_srl_reg[31][1]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.write_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] " *)
(* srl_name = "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.write_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][20]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\USE_RTL_FIFO.data_srl_reg[31][20]_srl32
(.A(\USE_RTL_ADDR.addr_q_reg__0 ),
.CE(valid_Write),
.CLK(s_axi_aclk),
.D(in[18]),
.Q(\USE_RTL_FIFO.data_srl_reg[31][20]_srl32_n_0 ),
.Q31(\NLW_USE_RTL_FIFO.data_srl_reg[31][20]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.write_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] " *)
(* srl_name = "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.write_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][21]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\USE_RTL_FIFO.data_srl_reg[31][21]_srl32
(.A(\USE_RTL_ADDR.addr_q_reg__0 ),
.CE(valid_Write),
.CLK(s_axi_aclk),
.D(in[19]),
.Q(\USE_RTL_FIFO.data_srl_reg[31][21]_srl32_n_0 ),
.Q31(\NLW_USE_RTL_FIFO.data_srl_reg[31][21]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.write_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] " *)
(* srl_name = "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.write_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][22]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\USE_RTL_FIFO.data_srl_reg[31][22]_srl32
(.A(\USE_RTL_ADDR.addr_q_reg__0 ),
.CE(valid_Write),
.CLK(s_axi_aclk),
.D(in[20]),
.Q(\USE_RTL_FIFO.data_srl_reg[31][22]_srl32_n_0 ),
.Q31(\NLW_USE_RTL_FIFO.data_srl_reg[31][22]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.write_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] " *)
(* srl_name = "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.write_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][23]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\USE_RTL_FIFO.data_srl_reg[31][23]_srl32
(.A(\USE_RTL_ADDR.addr_q_reg__0 ),
.CE(valid_Write),
.CLK(s_axi_aclk),
.D(in[21]),
.Q(\USE_RTL_FIFO.data_srl_reg[31][23]_srl32_n_0 ),
.Q31(\NLW_USE_RTL_FIFO.data_srl_reg[31][23]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.write_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] " *)
(* srl_name = "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.write_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][24]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\USE_RTL_FIFO.data_srl_reg[31][24]_srl32
(.A(\USE_RTL_ADDR.addr_q_reg__0 ),
.CE(valid_Write),
.CLK(s_axi_aclk),
.D(in[22]),
.Q(\USE_RTL_FIFO.data_srl_reg[31][24]_srl32_n_0 ),
.Q31(\NLW_USE_RTL_FIFO.data_srl_reg[31][24]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.write_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] " *)
(* srl_name = "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.write_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][25]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\USE_RTL_FIFO.data_srl_reg[31][25]_srl32
(.A(\USE_RTL_ADDR.addr_q_reg__0 ),
.CE(valid_Write),
.CLK(s_axi_aclk),
.D(in[23]),
.Q(\USE_RTL_FIFO.data_srl_reg[31][25]_srl32_n_0 ),
.Q31(\NLW_USE_RTL_FIFO.data_srl_reg[31][25]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.write_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] " *)
(* srl_name = "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.write_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][26]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\USE_RTL_FIFO.data_srl_reg[31][26]_srl32
(.A(\USE_RTL_ADDR.addr_q_reg__0 ),
.CE(valid_Write),
.CLK(s_axi_aclk),
.D(in[24]),
.Q(\USE_RTL_FIFO.data_srl_reg[31][26]_srl32_n_0 ),
.Q31(\NLW_USE_RTL_FIFO.data_srl_reg[31][26]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.write_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] " *)
(* srl_name = "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.write_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][27]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\USE_RTL_FIFO.data_srl_reg[31][27]_srl32
(.A(\USE_RTL_ADDR.addr_q_reg__0 ),
.CE(valid_Write),
.CLK(s_axi_aclk),
.D(in[25]),
.Q(\USE_RTL_FIFO.data_srl_reg[31][27]_srl32_n_0 ),
.Q31(\NLW_USE_RTL_FIFO.data_srl_reg[31][27]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.write_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] " *)
(* srl_name = "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.write_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][28]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\USE_RTL_FIFO.data_srl_reg[31][28]_srl32
(.A(\USE_RTL_ADDR.addr_q_reg__0 ),
.CE(valid_Write),
.CLK(s_axi_aclk),
.D(in[26]),
.Q(\USE_RTL_FIFO.data_srl_reg[31][28]_srl32_n_0 ),
.Q31(\NLW_USE_RTL_FIFO.data_srl_reg[31][28]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.write_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] " *)
(* srl_name = "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.write_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][29]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\USE_RTL_FIFO.data_srl_reg[31][29]_srl32
(.A(\USE_RTL_ADDR.addr_q_reg__0 ),
.CE(valid_Write),
.CLK(s_axi_aclk),
.D(in[27]),
.Q(\USE_RTL_FIFO.data_srl_reg[31][29]_srl32_n_0 ),
.Q31(\NLW_USE_RTL_FIFO.data_srl_reg[31][29]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.write_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] " *)
(* srl_name = "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.write_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][2]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\USE_RTL_FIFO.data_srl_reg[31][2]_srl32
(.A(\USE_RTL_ADDR.addr_q_reg__0 ),
.CE(valid_Write),
.CLK(s_axi_aclk),
.D(in[2]),
.Q(\USE_RTL_FIFO.data_srl_reg[31][2]_srl32_n_0 ),
.Q31(\NLW_USE_RTL_FIFO.data_srl_reg[31][2]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.write_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] " *)
(* srl_name = "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.write_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][3]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\USE_RTL_FIFO.data_srl_reg[31][3]_srl32
(.A(\USE_RTL_ADDR.addr_q_reg__0 ),
.CE(valid_Write),
.CLK(s_axi_aclk),
.D(in[3]),
.Q(\USE_RTL_FIFO.data_srl_reg[31][3]_srl32_n_0 ),
.Q31(\NLW_USE_RTL_FIFO.data_srl_reg[31][3]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.write_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] " *)
(* srl_name = "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.write_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][4]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\USE_RTL_FIFO.data_srl_reg[31][4]_srl32
(.A(\USE_RTL_ADDR.addr_q_reg__0 ),
.CE(valid_Write),
.CLK(s_axi_aclk),
.D(in[4]),
.Q(\USE_RTL_FIFO.data_srl_reg[31][4]_srl32_n_0 ),
.Q31(\NLW_USE_RTL_FIFO.data_srl_reg[31][4]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.write_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] " *)
(* srl_name = "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.write_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][5]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\USE_RTL_FIFO.data_srl_reg[31][5]_srl32
(.A(\USE_RTL_ADDR.addr_q_reg__0 ),
.CE(valid_Write),
.CLK(s_axi_aclk),
.D(in[5]),
.Q(\USE_RTL_FIFO.data_srl_reg[31][5]_srl32_n_0 ),
.Q31(\NLW_USE_RTL_FIFO.data_srl_reg[31][5]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.write_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] " *)
(* srl_name = "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.write_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][6]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\USE_RTL_FIFO.data_srl_reg[31][6]_srl32
(.A(\USE_RTL_ADDR.addr_q_reg__0 ),
.CE(valid_Write),
.CLK(s_axi_aclk),
.D(in[6]),
.Q(\USE_RTL_FIFO.data_srl_reg[31][6]_srl32_n_0 ),
.Q31(\NLW_USE_RTL_FIFO.data_srl_reg[31][6]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.write_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] " *)
(* srl_name = "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.write_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][7]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\USE_RTL_FIFO.data_srl_reg[31][7]_srl32
(.A(\USE_RTL_ADDR.addr_q_reg__0 ),
.CE(valid_Write),
.CLK(s_axi_aclk),
.D(in[7]),
.Q(\USE_RTL_FIFO.data_srl_reg[31][7]_srl32_n_0 ),
.Q31(\NLW_USE_RTL_FIFO.data_srl_reg[31][7]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.write_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] " *)
(* srl_name = "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.write_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][8]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\USE_RTL_FIFO.data_srl_reg[31][8]_srl32
(.A(\USE_RTL_ADDR.addr_q_reg__0 ),
.CE(valid_Write),
.CLK(s_axi_aclk),
.D(in[8]),
.Q(\USE_RTL_FIFO.data_srl_reg[31][8]_srl32_n_0 ),
.Q31(\NLW_USE_RTL_FIFO.data_srl_reg[31][8]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.write_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] " *)
(* srl_name = "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_WRITE.write_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][9]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\USE_RTL_FIFO.data_srl_reg[31][9]_srl32
(.A(\USE_RTL_ADDR.addr_q_reg__0 ),
.CE(valid_Write),
.CLK(s_axi_aclk),
.D(in[9]),
.Q(\USE_RTL_FIFO.data_srl_reg[31][9]_srl32_n_0 ),
.Q31(\NLW_USE_RTL_FIFO.data_srl_reg[31][9]_srl32_Q31_UNCONNECTED ));
LUT5 #(
.INIT(32'h999A9995))
\USE_RTL_LENGTH.first_mi_word_q_i_3
(.I0(Q[8]),
.I1(Q[11]),
.I2(first_word_q),
.I3(Q[14]),
.I4(\USE_RTL_CURR_WORD.current_word_q_reg[2]_0 [0]),
.O(\USE_RTL_LENGTH.first_mi_word_q_reg_0 ));
LUT5 #(
.INIT(32'h6665666A))
\USE_RTL_LENGTH.first_mi_word_q_i_5
(.I0(cmd_last_word[1]),
.I1(wr_cmd_first_word[1]),
.I2(first_word_q),
.I3(Q[14]),
.I4(\USE_RTL_CURR_WORD.current_word_q_reg[2]_0 [1]),
.O(\USE_RTL_LENGTH.first_mi_word_q_reg ));
LUT6 #(
.INIT(64'h00FFFFFF00040000))
\USE_RTL_VALID_WRITE.buffer_Full_q_i_1
(.I0(cmd_push_block),
.I1(sr_awvalid),
.I2(\USE_RTL_VALID_WRITE.buffer_Full_q_i_2_n_0 ),
.I3(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[29]_i_1_n_0 ),
.I4(data_Exists_I),
.I5(buffer_Full_q),
.O(\USE_RTL_VALID_WRITE.buffer_Full_q_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair54" *)
LUT5 #(
.INIT(32'hFF7FFFFF))
\USE_RTL_VALID_WRITE.buffer_Full_q_i_2
(.I0(\USE_RTL_ADDR.addr_q_reg__0 [2]),
.I1(\USE_RTL_ADDR.addr_q_reg__0 [1]),
.I2(\USE_RTL_ADDR.addr_q_reg__0 [4]),
.I3(\USE_RTL_ADDR.addr_q_reg__0 [0]),
.I4(\USE_RTL_ADDR.addr_q_reg__0 [3]),
.O(\USE_RTL_VALID_WRITE.buffer_Full_q_i_2_n_0 ));
FDRE \USE_RTL_VALID_WRITE.buffer_Full_q_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(\USE_RTL_VALID_WRITE.buffer_Full_q_i_1_n_0 ),
.Q(buffer_Full_q),
.R(s_axi_aresetn));
(* SOFT_HLUTNM = "soft_lutpair56" *)
LUT4 #(
.INIT(16'h8F00))
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[7]_i_3
(.I0(s_axi_wstrb[0]),
.I1(\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q[7]_i_3_n_0 ),
.I2(Q[13]),
.I3(\USE_REGISTER.M_AXI_WVALID_q_reg_0 ),
.O(\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[0]_0 ));
LUT6 #(
.INIT(64'h000002A200000000))
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I[0]_i_2
(.I0(\USE_REGISTER.M_AXI_WVALID_q_reg_0 ),
.I1(wr_cmd_first_word[2]),
.I2(\USE_RTL_CURR_WORD.pre_next_word_q_reg[1] ),
.I3(\USE_RTL_CURR_WORD.current_word_q_reg[2]_0 [2]),
.I4(wr_cmd_offset),
.I5(s_axi_wstrb[0]),
.O(\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[0] ));
LUT4 #(
.INIT(16'h80FF))
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q[7]_i_1
(.I0(\USE_RTL_CURR_WORD.first_word_q_reg ),
.I1(s_axi_wlast),
.I2(p_251_in),
.I3(out),
.O(SR));
LUT6 #(
.INIT(64'h0000000080000000))
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q[7]_i_2
(.I0(s_axi_wstrb[0]),
.I1(\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q[7]_i_3_n_0 ),
.I2(s_axi_wvalid),
.I3(\USE_RTL_CURR_WORD.first_word_q_reg ),
.I4(Q[12]),
.I5(wrap_buffer_available),
.O(\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg[7] ));
(* SOFT_HLUTNM = "soft_lutpair51" *)
LUT5 #(
.INIT(32'h00005457))
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q[7]_i_3
(.I0(wr_cmd_first_word[2]),
.I1(first_word_q),
.I2(Q[14]),
.I3(\USE_RTL_CURR_WORD.current_word_q_reg[2]_0 [2]),
.I4(wr_cmd_offset),
.O(\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q[7]_i_3_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair58" *)
LUT4 #(
.INIT(16'hD500))
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[15]_i_3
(.I0(Q[13]),
.I1(s_axi_wstrb[1]),
.I2(\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q[7]_i_3_n_0 ),
.I3(\USE_REGISTER.M_AXI_WVALID_q_reg_0 ),
.O(\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[8] ));
LUT6 #(
.INIT(64'h000002A200000000))
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I[1]_i_2
(.I0(\USE_REGISTER.M_AXI_WVALID_q_reg_0 ),
.I1(wr_cmd_first_word[2]),
.I2(\USE_RTL_CURR_WORD.pre_next_word_q_reg[1] ),
.I3(\USE_RTL_CURR_WORD.current_word_q_reg[2]_0 [2]),
.I4(wr_cmd_offset),
.I5(s_axi_wstrb[1]),
.O(\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[1] ));
LUT6 #(
.INIT(64'h0000000080000000))
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q[15]_i_1
(.I0(s_axi_wstrb[1]),
.I1(\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q[7]_i_3_n_0 ),
.I2(s_axi_wvalid),
.I3(\USE_RTL_CURR_WORD.first_word_q_reg ),
.I4(Q[12]),
.I5(wrap_buffer_available),
.O(\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg[15] ));
(* SOFT_HLUTNM = "soft_lutpair59" *)
LUT4 #(
.INIT(16'hD500))
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[23]_i_3
(.I0(Q[13]),
.I1(s_axi_wstrb[2]),
.I2(\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q[7]_i_3_n_0 ),
.I3(\USE_REGISTER.M_AXI_WVALID_q_reg_0 ),
.O(\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[16] ));
LUT6 #(
.INIT(64'h000002A200000000))
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I[2]_i_2
(.I0(\USE_REGISTER.M_AXI_WVALID_q_reg_0 ),
.I1(wr_cmd_first_word[2]),
.I2(\USE_RTL_CURR_WORD.pre_next_word_q_reg[1] ),
.I3(\USE_RTL_CURR_WORD.current_word_q_reg[2]_0 [2]),
.I4(wr_cmd_offset),
.I5(s_axi_wstrb[2]),
.O(\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[2] ));
LUT6 #(
.INIT(64'h0000000080000000))
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q[23]_i_1
(.I0(s_axi_wstrb[2]),
.I1(\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q[7]_i_3_n_0 ),
.I2(s_axi_wvalid),
.I3(\USE_RTL_CURR_WORD.first_word_q_reg ),
.I4(Q[12]),
.I5(wrap_buffer_available),
.O(\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg[23] ));
(* SOFT_HLUTNM = "soft_lutpair57" *)
LUT4 #(
.INIT(16'hD500))
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[31]_i_3
(.I0(Q[13]),
.I1(s_axi_wstrb[3]),
.I2(\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q[7]_i_3_n_0 ),
.I3(\USE_REGISTER.M_AXI_WVALID_q_reg_0 ),
.O(\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[24] ));
LUT6 #(
.INIT(64'h000002A200000000))
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I[3]_i_2
(.I0(\USE_REGISTER.M_AXI_WVALID_q_reg_0 ),
.I1(wr_cmd_first_word[2]),
.I2(\USE_RTL_CURR_WORD.pre_next_word_q_reg[1] ),
.I3(\USE_RTL_CURR_WORD.current_word_q_reg[2]_0 [2]),
.I4(wr_cmd_offset),
.I5(s_axi_wstrb[3]),
.O(\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[3] ));
LUT6 #(
.INIT(64'h0000000080000000))
\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q[31]_i_1
(.I0(s_axi_wstrb[3]),
.I1(\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q[7]_i_3_n_0 ),
.I2(s_axi_wvalid),
.I3(\USE_RTL_CURR_WORD.first_word_q_reg ),
.I4(Q[12]),
.I5(wrap_buffer_available),
.O(\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg[31] ));
(* SOFT_HLUTNM = "soft_lutpair56" *)
LUT4 #(
.INIT(16'h7500))
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[39]_i_3
(.I0(Q[13]),
.I1(\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q[7]_i_3_n_0 ),
.I2(s_axi_wstrb[0]),
.I3(\USE_REGISTER.M_AXI_WVALID_q_reg_0 ),
.O(\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[32] ));
LUT6 #(
.INIT(64'h8888888888800080))
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I[4]_i_2
(.I0(\USE_REGISTER.M_AXI_WVALID_q_reg_0 ),
.I1(s_axi_wstrb[0]),
.I2(wr_cmd_first_word[2]),
.I3(\USE_RTL_CURR_WORD.pre_next_word_q_reg[1] ),
.I4(\USE_RTL_CURR_WORD.current_word_q_reg[2]_0 [2]),
.I5(wr_cmd_offset),
.O(\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[4] ));
LUT6 #(
.INIT(64'h0000000020000000))
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q[39]_i_1
(.I0(s_axi_wstrb[0]),
.I1(\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q[7]_i_3_n_0 ),
.I2(s_axi_wvalid),
.I3(\USE_RTL_CURR_WORD.first_word_q_reg ),
.I4(Q[12]),
.I5(wrap_buffer_available),
.O(\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q_reg[39] ));
(* SOFT_HLUTNM = "soft_lutpair58" *)
LUT4 #(
.INIT(16'h7500))
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[47]_i_3
(.I0(Q[13]),
.I1(\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q[7]_i_3_n_0 ),
.I2(s_axi_wstrb[1]),
.I3(\USE_REGISTER.M_AXI_WVALID_q_reg_0 ),
.O(\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[40] ));
LUT6 #(
.INIT(64'h8888888888800080))
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I[5]_i_2
(.I0(\USE_REGISTER.M_AXI_WVALID_q_reg_0 ),
.I1(s_axi_wstrb[1]),
.I2(wr_cmd_first_word[2]),
.I3(\USE_RTL_CURR_WORD.pre_next_word_q_reg[1] ),
.I4(\USE_RTL_CURR_WORD.current_word_q_reg[2]_0 [2]),
.I5(wr_cmd_offset),
.O(\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[5] ));
LUT6 #(
.INIT(64'h0000000020000000))
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q[47]_i_1
(.I0(s_axi_wstrb[1]),
.I1(\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q[7]_i_3_n_0 ),
.I2(s_axi_wvalid),
.I3(\USE_RTL_CURR_WORD.first_word_q_reg ),
.I4(Q[12]),
.I5(wrap_buffer_available),
.O(\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[1].USE_RTL_DATA.wdata_wrap_buffer_q_reg[47] ));
(* SOFT_HLUTNM = "soft_lutpair59" *)
LUT4 #(
.INIT(16'h7500))
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[55]_i_3
(.I0(Q[13]),
.I1(\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q[7]_i_3_n_0 ),
.I2(s_axi_wstrb[2]),
.I3(\USE_REGISTER.M_AXI_WVALID_q_reg_0 ),
.O(\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[48] ));
LUT6 #(
.INIT(64'h8888888888800080))
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I[6]_i_2
(.I0(\USE_REGISTER.M_AXI_WVALID_q_reg_0 ),
.I1(s_axi_wstrb[2]),
.I2(wr_cmd_first_word[2]),
.I3(\USE_RTL_CURR_WORD.pre_next_word_q_reg[1] ),
.I4(\USE_RTL_CURR_WORD.current_word_q_reg[2]_0 [2]),
.I5(wr_cmd_offset),
.O(\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[6] ));
LUT6 #(
.INIT(64'h0000000020000000))
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q[55]_i_1
(.I0(s_axi_wstrb[2]),
.I1(\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q[7]_i_3_n_0 ),
.I2(s_axi_wvalid),
.I3(\USE_RTL_CURR_WORD.first_word_q_reg ),
.I4(Q[12]),
.I5(wrap_buffer_available),
.O(\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[2].USE_RTL_DATA.wdata_wrap_buffer_q_reg[55] ));
LUT5 #(
.INIT(32'hFFFFFFBF))
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_12
(.I0(\USE_RTL_LENGTH.length_counter_q_reg[0] ),
.I1(Q[13]),
.I2(\USE_RTL_LENGTH.first_mi_word_q_reg_0 ),
.I3(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]_1 ),
.I4(\USE_RTL_LENGTH.first_mi_word_q_reg ),
.O(\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[0]_1 ));
(* SOFT_HLUTNM = "soft_lutpair57" *)
LUT4 #(
.INIT(16'h7500))
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_4
(.I0(Q[13]),
.I1(\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q[7]_i_3_n_0 ),
.I2(s_axi_wstrb[3]),
.I3(\USE_REGISTER.M_AXI_WVALID_q_reg_0 ),
.O(\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[56] ));
LUT6 #(
.INIT(64'h75557575FFFFFFFF))
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I[63]_i_7
(.I0(\USE_RTL_CURR_WORD.first_word_q_reg ),
.I1(m_axi_wready),
.I2(\USE_REGISTER.M_AXI_WVALID_q_reg_1 ),
.I3(wrap_buffer_available),
.I4(Q[12]),
.I5(s_axi_wvalid),
.O(\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.USE_REGISTER.M_AXI_WDATA_I_reg[0] ));
LUT6 #(
.INIT(64'h8888888888800080))
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I[7]_i_2
(.I0(\USE_REGISTER.M_AXI_WVALID_q_reg_0 ),
.I1(s_axi_wstrb[3]),
.I2(wr_cmd_first_word[2]),
.I3(\USE_RTL_CURR_WORD.pre_next_word_q_reg[1] ),
.I4(\USE_RTL_CURR_WORD.current_word_q_reg[2]_0 [2]),
.I5(wr_cmd_offset),
.O(\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.USE_REGISTER.M_AXI_WSTRB_I_reg[7] ));
LUT6 #(
.INIT(64'h0000000020000000))
\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q[63]_i_1
(.I0(s_axi_wstrb[3]),
.I1(\WORD_LANE[0].USE_ALWAYS_PACKER.BYTE_LANE[0].USE_RTL_DATA.wdata_wrap_buffer_q[7]_i_3_n_0 ),
.I2(s_axi_wvalid),
.I3(\USE_RTL_CURR_WORD.first_word_q_reg ),
.I4(Q[12]),
.I5(wrap_buffer_available),
.O(\WORD_LANE[1].USE_ALWAYS_PACKER.BYTE_LANE[3].USE_RTL_DATA.wdata_wrap_buffer_q_reg[63] ));
(* SOFT_HLUTNM = "soft_lutpair55" *)
LUT4 #(
.INIT(16'h00D0))
cmd_push_block_i_1
(.I0(buffer_Full_q),
.I1(cmd_push_block),
.I2(sr_awvalid),
.I3(m_axi_awready),
.O(cmd_push_block0));
LUT6 #(
.INIT(64'hC4C4C4C4C4CFC4C4))
data_Exists_I_i_1
(.I0(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[29]_i_1_n_0 ),
.I1(data_Exists_I),
.I2(data_Exists_I_i_2_n_0),
.I3(buffer_Full_q),
.I4(sr_awvalid),
.I5(cmd_push_block),
.O(next_Data_Exists));
(* SOFT_HLUTNM = "soft_lutpair54" *)
LUT5 #(
.INIT(32'hFFFFFFFE))
data_Exists_I_i_2
(.I0(\USE_RTL_ADDR.addr_q_reg__0 [2]),
.I1(\USE_RTL_ADDR.addr_q_reg__0 [1]),
.I2(\USE_RTL_ADDR.addr_q_reg__0 [3]),
.I3(\USE_RTL_ADDR.addr_q_reg__0 [0]),
.I4(\USE_RTL_ADDR.addr_q_reg__0 [4]),
.O(data_Exists_I_i_2_n_0));
FDRE data_Exists_I_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(next_Data_Exists),
.Q(data_Exists_I),
.R(s_axi_aresetn));
(* SOFT_HLUTNM = "soft_lutpair60" *)
LUT3 #(
.INIT(8'h8A))
m_axi_awvalid_INST_0
(.I0(sr_awvalid),
.I1(cmd_push_block),
.I2(buffer_Full_q),
.O(m_axi_awvalid));
LUT5 #(
.INIT(32'h8AAA8A8A))
s_axi_wready_INST_0
(.I0(\USE_RTL_CURR_WORD.first_word_q_reg ),
.I1(m_axi_wready),
.I2(\USE_REGISTER.M_AXI_WVALID_q_reg_1 ),
.I3(wrap_buffer_available),
.I4(Q[12]),
.O(s_axi_wready));
(* SOFT_HLUTNM = "soft_lutpair60" *)
LUT4 #(
.INIT(16'hB000))
s_ready_i_i_2
(.I0(cmd_push_block),
.I1(buffer_Full_q),
.I2(m_axi_awready),
.I3(out),
.O(s_ready_i_reg));
LUT5 #(
.INIT(32'hBFFFAAAA))
wrap_buffer_available_i_1
(.I0(\USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst/wrap_buffer_available0 ),
.I1(\USE_RTL_CURR_WORD.first_word_q_reg ),
.I2(s_axi_wlast),
.I3(p_251_in),
.I4(wrap_buffer_available),
.O(wrap_buffer_available_reg));
(* SOFT_HLUTNM = "soft_lutpair53" *)
LUT5 #(
.INIT(32'h20000000))
wrap_buffer_available_i_2
(.I0(\USE_REGISTER.M_AXI_WVALID_q_i_2_n_0 ),
.I1(wrap_buffer_available),
.I2(Q[12]),
.I3(\USE_RTL_CURR_WORD.first_word_q_reg ),
.I4(s_axi_wvalid),
.O(\USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst/wrap_buffer_available0 ));
endmodule
|
module system_auto_us_0_generic_baseblocks_v2_1_0_command_fifo_1
(\M_AXI_RDATA_I_reg[63] ,
E,
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]_0 ,
\s_axi_rdata[31] ,
Q,
pop_mi_data,
\USE_RTL_LENGTH.first_mi_word_q_reg ,
first_word_reg,
D,
\current_word_1_reg[2] ,
s_axi_rvalid,
\M_AXI_RDATA_I_reg[63]_0 ,
s_ready_i_reg,
cmd_push_block0,
m_axi_arvalid,
s_axi_aresetn,
s_axi_aclk,
wrap_buffer_available,
\USE_RTL_LENGTH.length_counter_q_reg[7] ,
use_wrap_buffer,
first_word,
\current_word_1_reg[2]_0 ,
mr_rvalid,
s_axi_rready,
wrap_buffer_available_reg,
cmd_push_block,
sr_arvalid,
wrap_buffer_available_reg_0,
\pre_next_word_1_reg[2] ,
\pre_next_word_1_reg[2]_0 ,
\pre_next_word_1_reg[1] ,
first_mi_word_q,
m_axi_arready,
out,
in);
output \M_AXI_RDATA_I_reg[63] ;
output [0:0]E;
output \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]_0 ;
output \s_axi_rdata[31] ;
output [12:0]Q;
output pop_mi_data;
output \USE_RTL_LENGTH.first_mi_word_q_reg ;
output first_word_reg;
output [2:0]D;
output [2:0]\current_word_1_reg[2] ;
output s_axi_rvalid;
output [0:0]\M_AXI_RDATA_I_reg[63]_0 ;
output s_ready_i_reg;
output cmd_push_block0;
output m_axi_arvalid;
input s_axi_aresetn;
input s_axi_aclk;
input wrap_buffer_available;
input \USE_RTL_LENGTH.length_counter_q_reg[7] ;
input use_wrap_buffer;
input first_word;
input [2:0]\current_word_1_reg[2]_0 ;
input mr_rvalid;
input s_axi_rready;
input wrap_buffer_available_reg;
input cmd_push_block;
input sr_arvalid;
input wrap_buffer_available_reg_0;
input [2:0]\pre_next_word_1_reg[2] ;
input \pre_next_word_1_reg[2]_0 ;
input \pre_next_word_1_reg[1] ;
input first_mi_word_q;
input m_axi_arready;
input out;
input [27:0]in;
wire [2:0]D;
wire [0:0]E;
wire \M_AXI_RDATA_I_reg[63] ;
wire [0:0]\M_AXI_RDATA_I_reg[63]_0 ;
wire [12:0]Q;
wire \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[29]_i_1__0_n_0 ;
wire \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]_0 ;
wire \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg_n_0_[10] ;
wire \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg_n_0_[17] ;
wire \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg_n_0_[18] ;
wire \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg_n_0_[8] ;
wire \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg_n_0_[9] ;
wire \USE_RTL_ADDR.addr_q[0]_i_1__0_n_0 ;
wire \USE_RTL_ADDR.addr_q[1]_i_1__0_n_0 ;
wire \USE_RTL_ADDR.addr_q[2]_i_1__0_n_0 ;
wire \USE_RTL_ADDR.addr_q[3]_i_1__0_n_0 ;
wire \USE_RTL_ADDR.addr_q[4]_i_2__0_n_0 ;
wire \USE_RTL_ADDR.addr_q[4]_i_3__0_n_0 ;
wire [4:0]\USE_RTL_ADDR.addr_q_reg__0 ;
wire \USE_RTL_FIFO.data_srl_reg[31][0]_srl32_n_0 ;
wire \USE_RTL_FIFO.data_srl_reg[31][10]_srl32_n_0 ;
wire \USE_RTL_FIFO.data_srl_reg[31][11]_srl32_n_0 ;
wire \USE_RTL_FIFO.data_srl_reg[31][12]_srl32_n_0 ;
wire \USE_RTL_FIFO.data_srl_reg[31][13]_srl32_n_0 ;
wire \USE_RTL_FIFO.data_srl_reg[31][16]_srl32_n_0 ;
wire \USE_RTL_FIFO.data_srl_reg[31][17]_srl32_n_0 ;
wire \USE_RTL_FIFO.data_srl_reg[31][18]_srl32_n_0 ;
wire \USE_RTL_FIFO.data_srl_reg[31][19]_srl32_n_0 ;
wire \USE_RTL_FIFO.data_srl_reg[31][1]_srl32_n_0 ;
wire \USE_RTL_FIFO.data_srl_reg[31][20]_srl32_n_0 ;
wire \USE_RTL_FIFO.data_srl_reg[31][21]_srl32_n_0 ;
wire \USE_RTL_FIFO.data_srl_reg[31][22]_srl32_n_0 ;
wire \USE_RTL_FIFO.data_srl_reg[31][23]_srl32_n_0 ;
wire \USE_RTL_FIFO.data_srl_reg[31][24]_srl32_n_0 ;
wire \USE_RTL_FIFO.data_srl_reg[31][25]_srl32_n_0 ;
wire \USE_RTL_FIFO.data_srl_reg[31][26]_srl32_n_0 ;
wire \USE_RTL_FIFO.data_srl_reg[31][27]_srl32_n_0 ;
wire \USE_RTL_FIFO.data_srl_reg[31][28]_srl32_n_0 ;
wire \USE_RTL_FIFO.data_srl_reg[31][29]_srl32_n_0 ;
wire \USE_RTL_FIFO.data_srl_reg[31][2]_srl32_n_0 ;
wire \USE_RTL_FIFO.data_srl_reg[31][3]_srl32_n_0 ;
wire \USE_RTL_FIFO.data_srl_reg[31][4]_srl32_n_0 ;
wire \USE_RTL_FIFO.data_srl_reg[31][5]_srl32_n_0 ;
wire \USE_RTL_FIFO.data_srl_reg[31][6]_srl32_n_0 ;
wire \USE_RTL_FIFO.data_srl_reg[31][7]_srl32_n_0 ;
wire \USE_RTL_FIFO.data_srl_reg[31][8]_srl32_n_0 ;
wire \USE_RTL_FIFO.data_srl_reg[31][9]_srl32_n_0 ;
wire \USE_RTL_LENGTH.first_mi_word_q_reg ;
wire \USE_RTL_LENGTH.length_counter_q_reg[7] ;
wire \USE_RTL_VALID_WRITE.buffer_Full_q_i_1__0_n_0 ;
wire \USE_RTL_VALID_WRITE.buffer_Full_q_i_2__0_n_0 ;
wire addr_q;
wire buffer_Full_q;
wire cmd_push_block;
wire cmd_push_block0;
wire [2:0]\current_word_1_reg[2] ;
wire [2:0]\current_word_1_reg[2]_0 ;
wire data_Exists_I;
wire data_Exists_I_i_2__0_n_0;
wire first_mi_word_q;
wire first_word;
wire first_word_reg;
wire [27:0]in;
wire m_axi_arready;
wire m_axi_arvalid;
wire mr_rvalid;
wire next_Data_Exists;
wire out;
wire pop_mi_data;
wire \pre_next_word_1[1]_i_2_n_0 ;
wire \pre_next_word_1[2]_i_5_n_0 ;
wire \pre_next_word_1_reg[1] ;
wire [2:0]\pre_next_word_1_reg[2] ;
wire \pre_next_word_1_reg[2]_0 ;
wire rd_cmd_complete_wrap;
wire [1:0]rd_cmd_first_word;
wire [2:0]rd_cmd_mask;
wire rd_cmd_modified;
wire [0:0]rd_cmd_next_word;
wire [2:2]rd_cmd_offset;
wire rd_cmd_packed_wrap;
wire s_axi_aclk;
wire s_axi_aresetn;
wire \s_axi_rdata[31] ;
wire s_axi_rlast_INST_0_i_7_n_0;
wire s_axi_rready;
wire s_axi_rvalid;
wire s_ready_i_reg;
wire sr_arvalid;
wire use_wrap_buffer;
wire valid_Write;
wire wrap_buffer_available;
wire wrap_buffer_available_reg;
wire wrap_buffer_available_reg_0;
wire \NLW_USE_RTL_FIFO.data_srl_reg[31][0]_srl32_Q31_UNCONNECTED ;
wire \NLW_USE_RTL_FIFO.data_srl_reg[31][10]_srl32_Q31_UNCONNECTED ;
wire \NLW_USE_RTL_FIFO.data_srl_reg[31][11]_srl32_Q31_UNCONNECTED ;
wire \NLW_USE_RTL_FIFO.data_srl_reg[31][12]_srl32_Q31_UNCONNECTED ;
wire \NLW_USE_RTL_FIFO.data_srl_reg[31][13]_srl32_Q31_UNCONNECTED ;
wire \NLW_USE_RTL_FIFO.data_srl_reg[31][16]_srl32_Q31_UNCONNECTED ;
wire \NLW_USE_RTL_FIFO.data_srl_reg[31][17]_srl32_Q31_UNCONNECTED ;
wire \NLW_USE_RTL_FIFO.data_srl_reg[31][18]_srl32_Q31_UNCONNECTED ;
wire \NLW_USE_RTL_FIFO.data_srl_reg[31][19]_srl32_Q31_UNCONNECTED ;
wire \NLW_USE_RTL_FIFO.data_srl_reg[31][1]_srl32_Q31_UNCONNECTED ;
wire \NLW_USE_RTL_FIFO.data_srl_reg[31][20]_srl32_Q31_UNCONNECTED ;
wire \NLW_USE_RTL_FIFO.data_srl_reg[31][21]_srl32_Q31_UNCONNECTED ;
wire \NLW_USE_RTL_FIFO.data_srl_reg[31][22]_srl32_Q31_UNCONNECTED ;
wire \NLW_USE_RTL_FIFO.data_srl_reg[31][23]_srl32_Q31_UNCONNECTED ;
wire \NLW_USE_RTL_FIFO.data_srl_reg[31][24]_srl32_Q31_UNCONNECTED ;
wire \NLW_USE_RTL_FIFO.data_srl_reg[31][25]_srl32_Q31_UNCONNECTED ;
wire \NLW_USE_RTL_FIFO.data_srl_reg[31][26]_srl32_Q31_UNCONNECTED ;
wire \NLW_USE_RTL_FIFO.data_srl_reg[31][27]_srl32_Q31_UNCONNECTED ;
wire \NLW_USE_RTL_FIFO.data_srl_reg[31][28]_srl32_Q31_UNCONNECTED ;
wire \NLW_USE_RTL_FIFO.data_srl_reg[31][29]_srl32_Q31_UNCONNECTED ;
wire \NLW_USE_RTL_FIFO.data_srl_reg[31][2]_srl32_Q31_UNCONNECTED ;
wire \NLW_USE_RTL_FIFO.data_srl_reg[31][3]_srl32_Q31_UNCONNECTED ;
wire \NLW_USE_RTL_FIFO.data_srl_reg[31][4]_srl32_Q31_UNCONNECTED ;
wire \NLW_USE_RTL_FIFO.data_srl_reg[31][5]_srl32_Q31_UNCONNECTED ;
wire \NLW_USE_RTL_FIFO.data_srl_reg[31][6]_srl32_Q31_UNCONNECTED ;
wire \NLW_USE_RTL_FIFO.data_srl_reg[31][7]_srl32_Q31_UNCONNECTED ;
wire \NLW_USE_RTL_FIFO.data_srl_reg[31][8]_srl32_Q31_UNCONNECTED ;
wire \NLW_USE_RTL_FIFO.data_srl_reg[31][9]_srl32_Q31_UNCONNECTED ;
(* SOFT_HLUTNM = "soft_lutpair41" *)
LUT5 #(
.INIT(32'h00800000))
\M_AXI_RDATA_I[63]_i_1
(.I0(mr_rvalid),
.I1(\M_AXI_RDATA_I_reg[63] ),
.I2(first_mi_word_q),
.I3(use_wrap_buffer),
.I4(rd_cmd_packed_wrap),
.O(\M_AXI_RDATA_I_reg[63]_0 ));
LUT6 #(
.INIT(64'h0000AA02FFFFFFFF))
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[29]_i_1__0
(.I0(E),
.I1(wrap_buffer_available),
.I2(\USE_RTL_LENGTH.length_counter_q_reg[7] ),
.I3(use_wrap_buffer),
.I4(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]_0 ),
.I5(\M_AXI_RDATA_I_reg[63] ),
.O(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[29]_i_1__0_n_0 ));
LUT6 #(
.INIT(64'h01FDFE02FFFFFFFF))
\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[29]_i_2__0
(.I0(\current_word_1_reg[2]_0 [2]),
.I1(Q[12]),
.I2(first_word),
.I3(Q[11]),
.I4(Q[8]),
.I5(first_word_reg),
.O(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]_0 ));
FDRE \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[0]
(.C(s_axi_aclk),
.CE(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[29]_i_1__0_n_0 ),
.D(\USE_RTL_FIFO.data_srl_reg[31][0]_srl32_n_0 ),
.Q(Q[0]),
.R(s_axi_aresetn));
FDRE \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[10]
(.C(s_axi_aclk),
.CE(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[29]_i_1__0_n_0 ),
.D(\USE_RTL_FIFO.data_srl_reg[31][10]_srl32_n_0 ),
.Q(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg_n_0_[10] ),
.R(s_axi_aresetn));
FDRE \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[11]
(.C(s_axi_aclk),
.CE(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[29]_i_1__0_n_0 ),
.D(\USE_RTL_FIFO.data_srl_reg[31][11]_srl32_n_0 ),
.Q(rd_cmd_mask[0]),
.R(s_axi_aresetn));
FDRE \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[12]
(.C(s_axi_aclk),
.CE(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[29]_i_1__0_n_0 ),
.D(\USE_RTL_FIFO.data_srl_reg[31][12]_srl32_n_0 ),
.Q(rd_cmd_mask[1]),
.R(s_axi_aresetn));
FDRE \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[13]
(.C(s_axi_aclk),
.CE(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[29]_i_1__0_n_0 ),
.D(\USE_RTL_FIFO.data_srl_reg[31][13]_srl32_n_0 ),
.Q(rd_cmd_mask[2]),
.R(s_axi_aresetn));
FDRE \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[16]
(.C(s_axi_aclk),
.CE(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[29]_i_1__0_n_0 ),
.D(\USE_RTL_FIFO.data_srl_reg[31][16]_srl32_n_0 ),
.Q(rd_cmd_offset),
.R(s_axi_aresetn));
FDRE \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[17]
(.C(s_axi_aclk),
.CE(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[29]_i_1__0_n_0 ),
.D(\USE_RTL_FIFO.data_srl_reg[31][17]_srl32_n_0 ),
.Q(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg_n_0_[17] ),
.R(s_axi_aresetn));
FDRE \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[18]
(.C(s_axi_aclk),
.CE(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[29]_i_1__0_n_0 ),
.D(\USE_RTL_FIFO.data_srl_reg[31][18]_srl32_n_0 ),
.Q(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg_n_0_[18] ),
.R(s_axi_aresetn));
FDRE \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[19]
(.C(s_axi_aclk),
.CE(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[29]_i_1__0_n_0 ),
.D(\USE_RTL_FIFO.data_srl_reg[31][19]_srl32_n_0 ),
.Q(Q[8]),
.R(s_axi_aresetn));
FDRE \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[1]
(.C(s_axi_aclk),
.CE(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[29]_i_1__0_n_0 ),
.D(\USE_RTL_FIFO.data_srl_reg[31][1]_srl32_n_0 ),
.Q(Q[1]),
.R(s_axi_aresetn));
FDRE \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[20]
(.C(s_axi_aclk),
.CE(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[29]_i_1__0_n_0 ),
.D(\USE_RTL_FIFO.data_srl_reg[31][20]_srl32_n_0 ),
.Q(rd_cmd_next_word),
.R(s_axi_aresetn));
FDRE \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[21]
(.C(s_axi_aclk),
.CE(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[29]_i_1__0_n_0 ),
.D(\USE_RTL_FIFO.data_srl_reg[31][21]_srl32_n_0 ),
.Q(Q[9]),
.R(s_axi_aresetn));
FDRE \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[22]
(.C(s_axi_aclk),
.CE(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[29]_i_1__0_n_0 ),
.D(\USE_RTL_FIFO.data_srl_reg[31][22]_srl32_n_0 ),
.Q(Q[10]),
.R(s_axi_aresetn));
FDRE \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[23]
(.C(s_axi_aclk),
.CE(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[29]_i_1__0_n_0 ),
.D(\USE_RTL_FIFO.data_srl_reg[31][23]_srl32_n_0 ),
.Q(rd_cmd_first_word[0]),
.R(s_axi_aresetn));
FDRE \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[24]
(.C(s_axi_aclk),
.CE(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[29]_i_1__0_n_0 ),
.D(\USE_RTL_FIFO.data_srl_reg[31][24]_srl32_n_0 ),
.Q(rd_cmd_first_word[1]),
.R(s_axi_aresetn));
FDRE \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[25]
(.C(s_axi_aclk),
.CE(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[29]_i_1__0_n_0 ),
.D(\USE_RTL_FIFO.data_srl_reg[31][25]_srl32_n_0 ),
.Q(Q[11]),
.R(s_axi_aresetn));
FDRE \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[26]
(.C(s_axi_aclk),
.CE(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[29]_i_1__0_n_0 ),
.D(\USE_RTL_FIFO.data_srl_reg[31][26]_srl32_n_0 ),
.Q(rd_cmd_packed_wrap),
.R(s_axi_aresetn));
FDRE \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[27]
(.C(s_axi_aclk),
.CE(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[29]_i_1__0_n_0 ),
.D(\USE_RTL_FIFO.data_srl_reg[31][27]_srl32_n_0 ),
.Q(rd_cmd_complete_wrap),
.R(s_axi_aresetn));
FDRE \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[28]
(.C(s_axi_aclk),
.CE(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[29]_i_1__0_n_0 ),
.D(\USE_RTL_FIFO.data_srl_reg[31][28]_srl32_n_0 ),
.Q(rd_cmd_modified),
.R(s_axi_aresetn));
FDRE \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]
(.C(s_axi_aclk),
.CE(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[29]_i_1__0_n_0 ),
.D(\USE_RTL_FIFO.data_srl_reg[31][29]_srl32_n_0 ),
.Q(Q[12]),
.R(s_axi_aresetn));
FDRE \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[2]
(.C(s_axi_aclk),
.CE(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[29]_i_1__0_n_0 ),
.D(\USE_RTL_FIFO.data_srl_reg[31][2]_srl32_n_0 ),
.Q(Q[2]),
.R(s_axi_aresetn));
FDRE \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[3]
(.C(s_axi_aclk),
.CE(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[29]_i_1__0_n_0 ),
.D(\USE_RTL_FIFO.data_srl_reg[31][3]_srl32_n_0 ),
.Q(Q[3]),
.R(s_axi_aresetn));
FDRE \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[4]
(.C(s_axi_aclk),
.CE(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[29]_i_1__0_n_0 ),
.D(\USE_RTL_FIFO.data_srl_reg[31][4]_srl32_n_0 ),
.Q(Q[4]),
.R(s_axi_aresetn));
FDRE \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[5]
(.C(s_axi_aclk),
.CE(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[29]_i_1__0_n_0 ),
.D(\USE_RTL_FIFO.data_srl_reg[31][5]_srl32_n_0 ),
.Q(Q[5]),
.R(s_axi_aresetn));
FDRE \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[6]
(.C(s_axi_aclk),
.CE(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[29]_i_1__0_n_0 ),
.D(\USE_RTL_FIFO.data_srl_reg[31][6]_srl32_n_0 ),
.Q(Q[6]),
.R(s_axi_aresetn));
FDRE \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[7]
(.C(s_axi_aclk),
.CE(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[29]_i_1__0_n_0 ),
.D(\USE_RTL_FIFO.data_srl_reg[31][7]_srl32_n_0 ),
.Q(Q[7]),
.R(s_axi_aresetn));
FDRE \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[8]
(.C(s_axi_aclk),
.CE(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[29]_i_1__0_n_0 ),
.D(\USE_RTL_FIFO.data_srl_reg[31][8]_srl32_n_0 ),
.Q(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg_n_0_[8] ),
.R(s_axi_aresetn));
FDRE \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[9]
(.C(s_axi_aclk),
.CE(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[29]_i_1__0_n_0 ),
.D(\USE_RTL_FIFO.data_srl_reg[31][9]_srl32_n_0 ),
.Q(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg_n_0_[9] ),
.R(s_axi_aresetn));
FDRE \USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_VALID_Q_reg
(.C(s_axi_aclk),
.CE(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[29]_i_1__0_n_0 ),
.D(data_Exists_I),
.Q(\M_AXI_RDATA_I_reg[63] ),
.R(s_axi_aresetn));
(* SOFT_HLUTNM = "soft_lutpair39" *)
LUT1 #(
.INIT(2'h1))
\USE_RTL_ADDR.addr_q[0]_i_1__0
(.I0(\USE_RTL_ADDR.addr_q_reg__0 [0]),
.O(\USE_RTL_ADDR.addr_q[0]_i_1__0_n_0 ));
LUT6 #(
.INIT(64'hAAAAAA9A55555565))
\USE_RTL_ADDR.addr_q[1]_i_1__0
(.I0(\USE_RTL_ADDR.addr_q_reg__0 [0]),
.I1(cmd_push_block),
.I2(sr_arvalid),
.I3(buffer_Full_q),
.I4(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[29]_i_1__0_n_0 ),
.I5(\USE_RTL_ADDR.addr_q_reg__0 [1]),
.O(\USE_RTL_ADDR.addr_q[1]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair39" *)
LUT5 #(
.INIT(32'hBF40F40B))
\USE_RTL_ADDR.addr_q[2]_i_1__0
(.I0(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[29]_i_1__0_n_0 ),
.I1(valid_Write),
.I2(\USE_RTL_ADDR.addr_q_reg__0 [0]),
.I3(\USE_RTL_ADDR.addr_q_reg__0 [2]),
.I4(\USE_RTL_ADDR.addr_q_reg__0 [1]),
.O(\USE_RTL_ADDR.addr_q[2]_i_1__0_n_0 ));
LUT6 #(
.INIT(64'hBFFF4000FFF4000B))
\USE_RTL_ADDR.addr_q[3]_i_1__0
(.I0(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[29]_i_1__0_n_0 ),
.I1(valid_Write),
.I2(\USE_RTL_ADDR.addr_q_reg__0 [0]),
.I3(\USE_RTL_ADDR.addr_q_reg__0 [1]),
.I4(\USE_RTL_ADDR.addr_q_reg__0 [3]),
.I5(\USE_RTL_ADDR.addr_q_reg__0 [2]),
.O(\USE_RTL_ADDR.addr_q[3]_i_1__0_n_0 ));
LUT6 #(
.INIT(64'h80808080800C8080))
\USE_RTL_ADDR.addr_q[4]_i_1__0
(.I0(data_Exists_I_i_2__0_n_0),
.I1(data_Exists_I),
.I2(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[29]_i_1__0_n_0 ),
.I3(buffer_Full_q),
.I4(sr_arvalid),
.I5(cmd_push_block),
.O(addr_q));
LUT6 #(
.INIT(64'h6AAAAAAAAAAAAAA9))
\USE_RTL_ADDR.addr_q[4]_i_2__0
(.I0(\USE_RTL_ADDR.addr_q_reg__0 [4]),
.I1(\USE_RTL_ADDR.addr_q_reg__0 [3]),
.I2(\USE_RTL_ADDR.addr_q[4]_i_3__0_n_0 ),
.I3(\USE_RTL_ADDR.addr_q_reg__0 [0]),
.I4(\USE_RTL_ADDR.addr_q_reg__0 [1]),
.I5(\USE_RTL_ADDR.addr_q_reg__0 [2]),
.O(\USE_RTL_ADDR.addr_q[4]_i_2__0_n_0 ));
LUT6 #(
.INIT(64'h8080808888888888))
\USE_RTL_ADDR.addr_q[4]_i_3__0
(.I0(valid_Write),
.I1(\M_AXI_RDATA_I_reg[63] ),
.I2(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg[29]_0 ),
.I3(use_wrap_buffer),
.I4(wrap_buffer_available_reg_0),
.I5(E),
.O(\USE_RTL_ADDR.addr_q[4]_i_3__0_n_0 ));
FDRE \USE_RTL_ADDR.addr_q_reg[0]
(.C(s_axi_aclk),
.CE(addr_q),
.D(\USE_RTL_ADDR.addr_q[0]_i_1__0_n_0 ),
.Q(\USE_RTL_ADDR.addr_q_reg__0 [0]),
.R(s_axi_aresetn));
FDRE \USE_RTL_ADDR.addr_q_reg[1]
(.C(s_axi_aclk),
.CE(addr_q),
.D(\USE_RTL_ADDR.addr_q[1]_i_1__0_n_0 ),
.Q(\USE_RTL_ADDR.addr_q_reg__0 [1]),
.R(s_axi_aresetn));
FDRE \USE_RTL_ADDR.addr_q_reg[2]
(.C(s_axi_aclk),
.CE(addr_q),
.D(\USE_RTL_ADDR.addr_q[2]_i_1__0_n_0 ),
.Q(\USE_RTL_ADDR.addr_q_reg__0 [2]),
.R(s_axi_aresetn));
FDRE \USE_RTL_ADDR.addr_q_reg[3]
(.C(s_axi_aclk),
.CE(addr_q),
.D(\USE_RTL_ADDR.addr_q[3]_i_1__0_n_0 ),
.Q(\USE_RTL_ADDR.addr_q_reg__0 [3]),
.R(s_axi_aresetn));
FDRE \USE_RTL_ADDR.addr_q_reg[4]
(.C(s_axi_aclk),
.CE(addr_q),
.D(\USE_RTL_ADDR.addr_q[4]_i_2__0_n_0 ),
.Q(\USE_RTL_ADDR.addr_q_reg__0 [4]),
.R(s_axi_aresetn));
(* srl_bus_name = "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] " *)
(* srl_name = "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][0]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\USE_RTL_FIFO.data_srl_reg[31][0]_srl32
(.A(\USE_RTL_ADDR.addr_q_reg__0 ),
.CE(valid_Write),
.CLK(s_axi_aclk),
.D(in[0]),
.Q(\USE_RTL_FIFO.data_srl_reg[31][0]_srl32_n_0 ),
.Q31(\NLW_USE_RTL_FIFO.data_srl_reg[31][0]_srl32_Q31_UNCONNECTED ));
LUT3 #(
.INIT(8'h04))
\USE_RTL_FIFO.data_srl_reg[31][0]_srl32_i_1__0
(.I0(buffer_Full_q),
.I1(sr_arvalid),
.I2(cmd_push_block),
.O(valid_Write));
(* srl_bus_name = "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] " *)
(* srl_name = "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][10]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\USE_RTL_FIFO.data_srl_reg[31][10]_srl32
(.A(\USE_RTL_ADDR.addr_q_reg__0 ),
.CE(valid_Write),
.CLK(s_axi_aclk),
.D(in[10]),
.Q(\USE_RTL_FIFO.data_srl_reg[31][10]_srl32_n_0 ),
.Q31(\NLW_USE_RTL_FIFO.data_srl_reg[31][10]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] " *)
(* srl_name = "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][11]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\USE_RTL_FIFO.data_srl_reg[31][11]_srl32
(.A(\USE_RTL_ADDR.addr_q_reg__0 ),
.CE(valid_Write),
.CLK(s_axi_aclk),
.D(in[11]),
.Q(\USE_RTL_FIFO.data_srl_reg[31][11]_srl32_n_0 ),
.Q31(\NLW_USE_RTL_FIFO.data_srl_reg[31][11]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] " *)
(* srl_name = "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][12]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\USE_RTL_FIFO.data_srl_reg[31][12]_srl32
(.A(\USE_RTL_ADDR.addr_q_reg__0 ),
.CE(valid_Write),
.CLK(s_axi_aclk),
.D(in[12]),
.Q(\USE_RTL_FIFO.data_srl_reg[31][12]_srl32_n_0 ),
.Q31(\NLW_USE_RTL_FIFO.data_srl_reg[31][12]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] " *)
(* srl_name = "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][13]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\USE_RTL_FIFO.data_srl_reg[31][13]_srl32
(.A(\USE_RTL_ADDR.addr_q_reg__0 ),
.CE(valid_Write),
.CLK(s_axi_aclk),
.D(in[13]),
.Q(\USE_RTL_FIFO.data_srl_reg[31][13]_srl32_n_0 ),
.Q31(\NLW_USE_RTL_FIFO.data_srl_reg[31][13]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] " *)
(* srl_name = "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][16]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\USE_RTL_FIFO.data_srl_reg[31][16]_srl32
(.A(\USE_RTL_ADDR.addr_q_reg__0 ),
.CE(valid_Write),
.CLK(s_axi_aclk),
.D(in[14]),
.Q(\USE_RTL_FIFO.data_srl_reg[31][16]_srl32_n_0 ),
.Q31(\NLW_USE_RTL_FIFO.data_srl_reg[31][16]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] " *)
(* srl_name = "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][17]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\USE_RTL_FIFO.data_srl_reg[31][17]_srl32
(.A(\USE_RTL_ADDR.addr_q_reg__0 ),
.CE(valid_Write),
.CLK(s_axi_aclk),
.D(in[15]),
.Q(\USE_RTL_FIFO.data_srl_reg[31][17]_srl32_n_0 ),
.Q31(\NLW_USE_RTL_FIFO.data_srl_reg[31][17]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] " *)
(* srl_name = "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][18]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\USE_RTL_FIFO.data_srl_reg[31][18]_srl32
(.A(\USE_RTL_ADDR.addr_q_reg__0 ),
.CE(valid_Write),
.CLK(s_axi_aclk),
.D(in[16]),
.Q(\USE_RTL_FIFO.data_srl_reg[31][18]_srl32_n_0 ),
.Q31(\NLW_USE_RTL_FIFO.data_srl_reg[31][18]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] " *)
(* srl_name = "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][19]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\USE_RTL_FIFO.data_srl_reg[31][19]_srl32
(.A(\USE_RTL_ADDR.addr_q_reg__0 ),
.CE(valid_Write),
.CLK(s_axi_aclk),
.D(in[17]),
.Q(\USE_RTL_FIFO.data_srl_reg[31][19]_srl32_n_0 ),
.Q31(\NLW_USE_RTL_FIFO.data_srl_reg[31][19]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] " *)
(* srl_name = "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][1]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\USE_RTL_FIFO.data_srl_reg[31][1]_srl32
(.A(\USE_RTL_ADDR.addr_q_reg__0 ),
.CE(valid_Write),
.CLK(s_axi_aclk),
.D(in[1]),
.Q(\USE_RTL_FIFO.data_srl_reg[31][1]_srl32_n_0 ),
.Q31(\NLW_USE_RTL_FIFO.data_srl_reg[31][1]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] " *)
(* srl_name = "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][20]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\USE_RTL_FIFO.data_srl_reg[31][20]_srl32
(.A(\USE_RTL_ADDR.addr_q_reg__0 ),
.CE(valid_Write),
.CLK(s_axi_aclk),
.D(in[18]),
.Q(\USE_RTL_FIFO.data_srl_reg[31][20]_srl32_n_0 ),
.Q31(\NLW_USE_RTL_FIFO.data_srl_reg[31][20]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] " *)
(* srl_name = "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][21]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\USE_RTL_FIFO.data_srl_reg[31][21]_srl32
(.A(\USE_RTL_ADDR.addr_q_reg__0 ),
.CE(valid_Write),
.CLK(s_axi_aclk),
.D(in[19]),
.Q(\USE_RTL_FIFO.data_srl_reg[31][21]_srl32_n_0 ),
.Q31(\NLW_USE_RTL_FIFO.data_srl_reg[31][21]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] " *)
(* srl_name = "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][22]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\USE_RTL_FIFO.data_srl_reg[31][22]_srl32
(.A(\USE_RTL_ADDR.addr_q_reg__0 ),
.CE(valid_Write),
.CLK(s_axi_aclk),
.D(in[20]),
.Q(\USE_RTL_FIFO.data_srl_reg[31][22]_srl32_n_0 ),
.Q31(\NLW_USE_RTL_FIFO.data_srl_reg[31][22]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] " *)
(* srl_name = "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][23]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\USE_RTL_FIFO.data_srl_reg[31][23]_srl32
(.A(\USE_RTL_ADDR.addr_q_reg__0 ),
.CE(valid_Write),
.CLK(s_axi_aclk),
.D(in[21]),
.Q(\USE_RTL_FIFO.data_srl_reg[31][23]_srl32_n_0 ),
.Q31(\NLW_USE_RTL_FIFO.data_srl_reg[31][23]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] " *)
(* srl_name = "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][24]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\USE_RTL_FIFO.data_srl_reg[31][24]_srl32
(.A(\USE_RTL_ADDR.addr_q_reg__0 ),
.CE(valid_Write),
.CLK(s_axi_aclk),
.D(in[22]),
.Q(\USE_RTL_FIFO.data_srl_reg[31][24]_srl32_n_0 ),
.Q31(\NLW_USE_RTL_FIFO.data_srl_reg[31][24]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] " *)
(* srl_name = "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][25]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\USE_RTL_FIFO.data_srl_reg[31][25]_srl32
(.A(\USE_RTL_ADDR.addr_q_reg__0 ),
.CE(valid_Write),
.CLK(s_axi_aclk),
.D(in[23]),
.Q(\USE_RTL_FIFO.data_srl_reg[31][25]_srl32_n_0 ),
.Q31(\NLW_USE_RTL_FIFO.data_srl_reg[31][25]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] " *)
(* srl_name = "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][26]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\USE_RTL_FIFO.data_srl_reg[31][26]_srl32
(.A(\USE_RTL_ADDR.addr_q_reg__0 ),
.CE(valid_Write),
.CLK(s_axi_aclk),
.D(in[24]),
.Q(\USE_RTL_FIFO.data_srl_reg[31][26]_srl32_n_0 ),
.Q31(\NLW_USE_RTL_FIFO.data_srl_reg[31][26]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] " *)
(* srl_name = "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][27]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\USE_RTL_FIFO.data_srl_reg[31][27]_srl32
(.A(\USE_RTL_ADDR.addr_q_reg__0 ),
.CE(valid_Write),
.CLK(s_axi_aclk),
.D(in[25]),
.Q(\USE_RTL_FIFO.data_srl_reg[31][27]_srl32_n_0 ),
.Q31(\NLW_USE_RTL_FIFO.data_srl_reg[31][27]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] " *)
(* srl_name = "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][28]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\USE_RTL_FIFO.data_srl_reg[31][28]_srl32
(.A(\USE_RTL_ADDR.addr_q_reg__0 ),
.CE(valid_Write),
.CLK(s_axi_aclk),
.D(in[26]),
.Q(\USE_RTL_FIFO.data_srl_reg[31][28]_srl32_n_0 ),
.Q31(\NLW_USE_RTL_FIFO.data_srl_reg[31][28]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] " *)
(* srl_name = "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][29]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\USE_RTL_FIFO.data_srl_reg[31][29]_srl32
(.A(\USE_RTL_ADDR.addr_q_reg__0 ),
.CE(valid_Write),
.CLK(s_axi_aclk),
.D(in[27]),
.Q(\USE_RTL_FIFO.data_srl_reg[31][29]_srl32_n_0 ),
.Q31(\NLW_USE_RTL_FIFO.data_srl_reg[31][29]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] " *)
(* srl_name = "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][2]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\USE_RTL_FIFO.data_srl_reg[31][2]_srl32
(.A(\USE_RTL_ADDR.addr_q_reg__0 ),
.CE(valid_Write),
.CLK(s_axi_aclk),
.D(in[2]),
.Q(\USE_RTL_FIFO.data_srl_reg[31][2]_srl32_n_0 ),
.Q31(\NLW_USE_RTL_FIFO.data_srl_reg[31][2]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] " *)
(* srl_name = "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][3]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\USE_RTL_FIFO.data_srl_reg[31][3]_srl32
(.A(\USE_RTL_ADDR.addr_q_reg__0 ),
.CE(valid_Write),
.CLK(s_axi_aclk),
.D(in[3]),
.Q(\USE_RTL_FIFO.data_srl_reg[31][3]_srl32_n_0 ),
.Q31(\NLW_USE_RTL_FIFO.data_srl_reg[31][3]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] " *)
(* srl_name = "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][4]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\USE_RTL_FIFO.data_srl_reg[31][4]_srl32
(.A(\USE_RTL_ADDR.addr_q_reg__0 ),
.CE(valid_Write),
.CLK(s_axi_aclk),
.D(in[4]),
.Q(\USE_RTL_FIFO.data_srl_reg[31][4]_srl32_n_0 ),
.Q31(\NLW_USE_RTL_FIFO.data_srl_reg[31][4]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] " *)
(* srl_name = "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][5]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\USE_RTL_FIFO.data_srl_reg[31][5]_srl32
(.A(\USE_RTL_ADDR.addr_q_reg__0 ),
.CE(valid_Write),
.CLK(s_axi_aclk),
.D(in[5]),
.Q(\USE_RTL_FIFO.data_srl_reg[31][5]_srl32_n_0 ),
.Q31(\NLW_USE_RTL_FIFO.data_srl_reg[31][5]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] " *)
(* srl_name = "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][6]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\USE_RTL_FIFO.data_srl_reg[31][6]_srl32
(.A(\USE_RTL_ADDR.addr_q_reg__0 ),
.CE(valid_Write),
.CLK(s_axi_aclk),
.D(in[6]),
.Q(\USE_RTL_FIFO.data_srl_reg[31][6]_srl32_n_0 ),
.Q31(\NLW_USE_RTL_FIFO.data_srl_reg[31][6]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] " *)
(* srl_name = "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][7]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\USE_RTL_FIFO.data_srl_reg[31][7]_srl32
(.A(\USE_RTL_ADDR.addr_q_reg__0 ),
.CE(valid_Write),
.CLK(s_axi_aclk),
.D(in[7]),
.Q(\USE_RTL_FIFO.data_srl_reg[31][7]_srl32_n_0 ),
.Q31(\NLW_USE_RTL_FIFO.data_srl_reg[31][7]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] " *)
(* srl_name = "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][8]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\USE_RTL_FIFO.data_srl_reg[31][8]_srl32
(.A(\USE_RTL_ADDR.addr_q_reg__0 ),
.CE(valid_Write),
.CLK(s_axi_aclk),
.D(in[8]),
.Q(\USE_RTL_FIFO.data_srl_reg[31][8]_srl32_n_0 ),
.Q31(\NLW_USE_RTL_FIFO.data_srl_reg[31][8]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31] " *)
(* srl_name = "inst/\gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.read_addr_inst/GEN_CMD_QUEUE.cmd_queue/USE_RTL_FIFO.data_srl_reg[31][9]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\USE_RTL_FIFO.data_srl_reg[31][9]_srl32
(.A(\USE_RTL_ADDR.addr_q_reg__0 ),
.CE(valid_Write),
.CLK(s_axi_aclk),
.D(in[9]),
.Q(\USE_RTL_FIFO.data_srl_reg[31][9]_srl32_n_0 ),
.Q31(\NLW_USE_RTL_FIFO.data_srl_reg[31][9]_srl32_Q31_UNCONNECTED ));
LUT6 #(
.INIT(64'h8000808080008000))
\USE_RTL_LENGTH.first_mi_word_q_i_1__0
(.I0(mr_rvalid),
.I1(\M_AXI_RDATA_I_reg[63] ),
.I2(s_axi_rready),
.I3(\USE_RTL_LENGTH.first_mi_word_q_reg ),
.I4(use_wrap_buffer),
.I5(wrap_buffer_available_reg),
.O(pop_mi_data));
LUT6 #(
.INIT(64'h00FFFFFF00040000))
\USE_RTL_VALID_WRITE.buffer_Full_q_i_1__0
(.I0(cmd_push_block),
.I1(sr_arvalid),
.I2(\USE_RTL_VALID_WRITE.buffer_Full_q_i_2__0_n_0 ),
.I3(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[29]_i_1__0_n_0 ),
.I4(data_Exists_I),
.I5(buffer_Full_q),
.O(\USE_RTL_VALID_WRITE.buffer_Full_q_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair42" *)
LUT5 #(
.INIT(32'hFF7FFFFF))
\USE_RTL_VALID_WRITE.buffer_Full_q_i_2__0
(.I0(\USE_RTL_ADDR.addr_q_reg__0 [2]),
.I1(\USE_RTL_ADDR.addr_q_reg__0 [1]),
.I2(\USE_RTL_ADDR.addr_q_reg__0 [4]),
.I3(\USE_RTL_ADDR.addr_q_reg__0 [0]),
.I4(\USE_RTL_ADDR.addr_q_reg__0 [3]),
.O(\USE_RTL_VALID_WRITE.buffer_Full_q_i_2__0_n_0 ));
FDRE \USE_RTL_VALID_WRITE.buffer_Full_q_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(\USE_RTL_VALID_WRITE.buffer_Full_q_i_1__0_n_0 ),
.Q(buffer_Full_q),
.R(s_axi_aresetn));
(* SOFT_HLUTNM = "soft_lutpair43" *)
LUT4 #(
.INIT(16'h00D0))
cmd_push_block_i_1__0
(.I0(buffer_Full_q),
.I1(cmd_push_block),
.I2(sr_arvalid),
.I3(m_axi_arready),
.O(cmd_push_block0));
(* SOFT_HLUTNM = "soft_lutpair40" *)
LUT5 #(
.INIT(32'h888A8880))
\current_word_1[0]_i_1
(.I0(rd_cmd_mask[0]),
.I1(rd_cmd_next_word),
.I2(first_word),
.I3(Q[12]),
.I4(\pre_next_word_1_reg[2] [0]),
.O(\current_word_1_reg[2] [0]));
LUT5 #(
.INIT(32'h888A8880))
\current_word_1[1]_i_1
(.I0(rd_cmd_mask[1]),
.I1(Q[9]),
.I2(first_word),
.I3(Q[12]),
.I4(\pre_next_word_1_reg[2] [1]),
.O(\current_word_1_reg[2] [1]));
LUT5 #(
.INIT(32'h888A8880))
\current_word_1[2]_i_1
(.I0(rd_cmd_mask[2]),
.I1(Q[10]),
.I2(first_word),
.I3(Q[12]),
.I4(\pre_next_word_1_reg[2] [2]),
.O(\current_word_1_reg[2] [2]));
LUT6 #(
.INIT(64'hC4C4C4C4C4CFC4C4))
data_Exists_I_i_1__0
(.I0(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q[29]_i_1__0_n_0 ),
.I1(data_Exists_I),
.I2(data_Exists_I_i_2__0_n_0),
.I3(buffer_Full_q),
.I4(sr_arvalid),
.I5(cmd_push_block),
.O(next_Data_Exists));
(* SOFT_HLUTNM = "soft_lutpair42" *)
LUT5 #(
.INIT(32'hFFFFFFFE))
data_Exists_I_i_2__0
(.I0(\USE_RTL_ADDR.addr_q_reg__0 [2]),
.I1(\USE_RTL_ADDR.addr_q_reg__0 [1]),
.I2(\USE_RTL_ADDR.addr_q_reg__0 [3]),
.I3(\USE_RTL_ADDR.addr_q_reg__0 [0]),
.I4(\USE_RTL_ADDR.addr_q_reg__0 [4]),
.O(data_Exists_I_i_2__0_n_0));
FDRE data_Exists_I_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(next_Data_Exists),
.Q(data_Exists_I),
.R(s_axi_aresetn));
LUT3 #(
.INIT(8'h8A))
m_axi_arvalid_INST_0
(.I0(sr_arvalid),
.I1(cmd_push_block),
.I2(buffer_Full_q),
.O(m_axi_arvalid));
LUT6 #(
.INIT(64'hDDDDDDDDDDDDDDDF))
\m_payload_i[66]_i_3
(.I0(rd_cmd_modified),
.I1(Q[12]),
.I2(\current_word_1_reg[2] [2]),
.I3(\current_word_1_reg[2] [1]),
.I4(rd_cmd_complete_wrap),
.I5(\current_word_1_reg[2] [0]),
.O(\USE_RTL_LENGTH.first_mi_word_q_reg ));
LUT6 #(
.INIT(64'h0002AAA2AAA80008))
\pre_next_word_1[0]_i_1
(.I0(rd_cmd_mask[0]),
.I1(\pre_next_word_1_reg[2] [0]),
.I2(Q[12]),
.I3(first_word),
.I4(rd_cmd_next_word),
.I5(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg_n_0_[8] ),
.O(D[0]));
LUT6 #(
.INIT(64'h8882228222288828))
\pre_next_word_1[1]_i_1
(.I0(rd_cmd_mask[1]),
.I1(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg_n_0_[9] ),
.I2(Q[9]),
.I3(\pre_next_word_1[1]_i_2_n_0 ),
.I4(\pre_next_word_1_reg[2] [1]),
.I5(\pre_next_word_1[2]_i_5_n_0 ),
.O(D[1]));
(* SOFT_HLUTNM = "soft_lutpair40" *)
LUT2 #(
.INIT(4'h1))
\pre_next_word_1[1]_i_2
(.I0(Q[12]),
.I1(first_word),
.O(\pre_next_word_1[1]_i_2_n_0 ));
LUT4 #(
.INIT(16'hAA80))
\pre_next_word_1[2]_i_1
(.I0(s_axi_rready),
.I1(\M_AXI_RDATA_I_reg[63] ),
.I2(mr_rvalid),
.I3(use_wrap_buffer),
.O(E));
LUT6 #(
.INIT(64'h2828288228828282))
\pre_next_word_1[2]_i_2
(.I0(rd_cmd_mask[2]),
.I1(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg_n_0_[10] ),
.I2(\pre_next_word_1_reg[2]_0 ),
.I3(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg_n_0_[9] ),
.I4(\pre_next_word_1_reg[1] ),
.I5(\pre_next_word_1[2]_i_5_n_0 ),
.O(D[2]));
LUT5 #(
.INIT(32'h888A8880))
\pre_next_word_1[2]_i_5
(.I0(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg_n_0_[8] ),
.I1(rd_cmd_next_word),
.I2(first_word),
.I3(Q[12]),
.I4(\pre_next_word_1_reg[2] [0]),
.O(\pre_next_word_1[2]_i_5_n_0 ));
LUT5 #(
.INIT(32'h00005457))
\s_axi_rdata[31]_INST_0_i_1
(.I0(Q[11]),
.I1(first_word),
.I2(Q[12]),
.I3(\current_word_1_reg[2]_0 [2]),
.I4(rd_cmd_offset),
.O(\s_axi_rdata[31] ));
LUT6 #(
.INIT(64'h00000000FE0201FD))
s_axi_rlast_INST_0_i_2
(.I0(\current_word_1_reg[2]_0 [0]),
.I1(Q[12]),
.I2(first_word),
.I3(rd_cmd_first_word[0]),
.I4(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg_n_0_[17] ),
.I5(s_axi_rlast_INST_0_i_7_n_0),
.O(first_word_reg));
LUT5 #(
.INIT(32'h6665666A))
s_axi_rlast_INST_0_i_7
(.I0(\USE_FF_OUT.USE_RTL_OUTPUT_PIPELINE.M_MESG_Q_reg_n_0_[18] ),
.I1(rd_cmd_first_word[1]),
.I2(first_word),
.I3(Q[12]),
.I4(\current_word_1_reg[2]_0 [1]),
.O(s_axi_rlast_INST_0_i_7_n_0));
(* SOFT_HLUTNM = "soft_lutpair41" *)
LUT3 #(
.INIT(8'hF8))
s_axi_rvalid_INST_0
(.I0(\M_AXI_RDATA_I_reg[63] ),
.I1(mr_rvalid),
.I2(use_wrap_buffer),
.O(s_axi_rvalid));
(* SOFT_HLUTNM = "soft_lutpair43" *)
LUT4 #(
.INIT(16'hB000))
s_ready_i_i_2__1
(.I0(cmd_push_block),
.I1(buffer_Full_q),
.I2(m_axi_arready),
.I3(out),
.O(s_ready_i_reg));
endmodule
|
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
|
module sky130_fd_sc_lp__invkapwr_1 (
Y ,
A ,
VPWR ,
VGND ,
KAPWR,
VPB ,
VNB
);
output Y ;
input A ;
input VPWR ;
input VGND ;
input KAPWR;
input VPB ;
input VNB ;
sky130_fd_sc_lp__invkapwr base (
.Y(Y),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.KAPWR(KAPWR),
.VPB(VPB),
.VNB(VNB)
);
endmodule
|
module sky130_fd_sc_lp__invkapwr_1 (
Y,
A
);
output Y;
input A;
// Voltage supply signals
supply1 VPWR ;
supply0 VGND ;
supply1 KAPWR;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__invkapwr base (
.Y(Y),
.A(A)
);
endmodule
|
module
.addr_o(addr),
.clk_i(clk_f20),
.maddr_i(maddr_i),
.mcmd_i(mcmd_i),
.mdata_i(mdata_i),
.mreset_n_i(mreset_n_i),
.mrespaccept_i(mrespaccept_i),
.rd_data_i(rd_data),
.rd_err_i(rd_err),
.rd_wr_o(rd_wr),
.reset_n_i(res_f20_n_i),
.scmdaccept_o(scmdaccept_o),
.sdata_o(sdata_o),
.sresp_o(sresp_o),
.trans_done_i(trans_done),
.trans_start_o(trans_start),
.wr_data_o(wr_data)
);
// End of Generated Instance Port Map for u0_ocp_target_i
endmodule
|
module top #(
`include "includes/x393_parameters.vh" // SuppressThisWarning VEditor - partially used
)
(
// sata serial data iface
input wire RXN,
input wire RXP,
output wire TXN,
output wire TXP,
// sata clocking iface
input wire EXTCLK_P,
input wire EXTCLK_N
);
wire axi_aclk0;
wire sclk ; // Just output from SATA subsystem SuppressThisWarning VEditor Not used
wire sata_rst; // Just output from SATA subsystem SuppressThisWarning VEditor Not used
wire extrst;
wire [3:0] fclk;
wire [3:0] frst;
//wire axi_aclk;
wire axi_rst;
wire hclk;
wire comb_rst;
wire [31:0] maxi1_araddr;
wire maxi1_arvalid;
wire maxi1_arready;
wire [11:0] maxi1_arid;
wire [3:0] maxi1_arlen;
wire [1:0] maxi1_arsize;
wire [1:0] maxi1_arburst;
wire [31:0] maxi1_rdata;
wire maxi1_rvalid;
wire maxi1_rready;
wire [11:0] maxi1_rid;
wire maxi1_rlast;
wire [1:0] maxi1_rresp;
wire [31:0] maxi1_awaddr;
wire maxi1_awvalid;
wire maxi1_awready;
wire [11:0] maxi1_awid;
wire [3:0] maxi1_awlen;
wire [1:0] maxi1_awsize;
wire [1:0] maxi1_awburst;
wire [31:0] maxi1_wdata;
wire maxi1_wvalid;
wire maxi1_wready;
wire [11:0] maxi1_wid;
wire maxi1_wlast;
wire [3:0] maxi1_wstb;
wire maxi1_bvalid;
wire maxi1_bready;
wire [11:0] maxi1_bid;
wire [1:0] maxi1_bresp;
reg axi_rst_pre;
// membridge
wire [31:0] afi3_awaddr; // output[31:0]
wire afi3_awvalid; // output
wire afi3_awready; // input
wire [ 5:0] afi3_awid; // output[5:0]
wire [ 1:0] afi3_awlock; // output[1:0]
wire [ 3:0] afi3_awcache; // output[3:0]
wire [ 2:0] afi3_awprot; // output[2:0]
wire [ 3:0] afi3_awlen; // output[3:0]
wire [ 1:0] afi3_awsize; // output[2:0]
wire [ 1:0] afi3_awburst; // output[1:0]
wire [ 3:0] afi3_awqos; // output[3:0]
wire [63:0] afi3_wdata; // output[63:0]
wire afi3_wvalid; // output
wire afi3_wready; // input
wire [ 5:0] afi3_wid; // output[5:0]
wire afi3_wlast; // output
wire [ 7:0] afi3_wstrb; // output[7:0]
wire afi3_bvalid; // input
wire afi3_bready; // output
wire [ 5:0] afi3_bid; // input[5:0]
wire [ 1:0] afi3_bresp; // input[1:0]
wire [ 7:0] afi3_wcount; // input[7:0]
wire [ 5:0] afi3_wacount; // input[5:0]
wire afi3_wrissuecap1en; // output
wire [31:0] afi3_araddr; // output[31:0]
wire afi3_arvalid; // output
wire afi3_arready; // input
wire [ 5:0] afi3_arid; // output[5:0]
wire [ 1:0] afi3_arlock; // output[1:0]
wire [ 3:0] afi3_arcache; // output[3:0]
wire [ 2:0] afi3_arprot; // output[2:0]
wire [ 3:0] afi3_arlen; // output[3:0]
wire [ 1:0] afi3_arsize; // output[2:0]
wire [ 1:0] afi3_arburst; // output[1:0]
wire [ 3:0] afi3_arqos; // output[3:0]
wire [63:0] afi3_rdata; // input[63:0]
wire afi3_rvalid; // input
wire afi3_rready; // output
wire [ 5:0] afi3_rid; // input[5:0]
wire afi3_rlast; // input
wire [ 1:0] afi3_rresp; // input[2:0]
wire [ 7:0] afi3_rcount; // input[7:0]
wire [ 2:0] afi3_racount; // input[2:0]
wire afi3_rdissuecap1en; // output
wire irq; // ps7 IRQ
assign comb_rst=~frst[0] | frst[1];
always @(posedge comb_rst or posedge axi_aclk0) begin
if (comb_rst) axi_rst_pre <= 1'b1;
else axi_rst_pre <= 1'b0;
end
select_clk_buf #(
.BUFFER_TYPE("BUFG")
) bufg_axi_aclk0_i (
.o (axi_aclk0), // output
.i (fclk[0]), // input
.clr (1'b0) // input
);
select_clk_buf #(
.BUFFER_TYPE("BUFG")
) bufg_axi_rst_i (
.o (axi_rst), // output
.i (axi_rst_pre), // input
.clr (1'b0) // input
);
select_clk_buf #(
.BUFFER_TYPE("BUFG")
) bufg_extrst_i (
.o (extrst), // output
.i (axi_rst_pre), // input
.clr (1'b0) // input
);
axi_hp_clk #(
.CLKIN_PERIOD(20.000),
.CLKFBOUT_MULT_AXIHP(18),
.CLKFBOUT_DIV_AXIHP(6)
) axi_hp_clk_i (
.rst (axi_rst), // input
.clk_in (axi_aclk0), // input
.clk_axihp (hclk), // output
.locked_axihp () // output // not controlled?
);
sata_ahci_top sata_top(
.sata_clk (sclk),
// reliable clock to source drp and cpll lock det circuits
.reliable_clk (axi_aclk0),
.hclk (hclk),
.sata_rst (sata_rst),
.arst (extrst),
.ACLK (axi_aclk0),
.ARESETN (axi_rst/* | sata_rst*/),
// AXI PS Master GP1: Read Address
.ARADDR (maxi1_araddr),
.ARVALID (maxi1_arvalid),
.ARREADY (maxi1_arready),
.ARID (maxi1_arid),
.ARLEN (maxi1_arlen),
.ARSIZE (maxi1_arsize),
.ARBURST (maxi1_arburst),
// AXI PS Master GP1: Read Data
.RDATA (maxi1_rdata),
.RVALID (maxi1_rvalid),
.RREADY (maxi1_rready),
.RID (maxi1_rid),
.RLAST (maxi1_rlast),
.RRESP (maxi1_rresp),
// AXI PS Master GP1: Write Address
.AWADDR (maxi1_awaddr),
.AWVALID (maxi1_awvalid),
.AWREADY (maxi1_awready),
.AWID (maxi1_awid),
.AWLEN (maxi1_awlen),
.AWSIZE (maxi1_awsize),
.AWBURST (maxi1_awburst),
// AXI PS Master GP1: Write Data
.WDATA (maxi1_wdata),
.WVALID (maxi1_wvalid),
.WREADY (maxi1_wready),
.WID (maxi1_wid),
.WLAST (maxi1_wlast),
.WSTRB (maxi1_wstb),
// AXI PS Master GP1: Write response
.BVALID (maxi1_bvalid),
.BREADY (maxi1_bready),
.BID (maxi1_bid),
.BRESP (maxi1_bresp),
/*
* Data interface
*/
.afi_awaddr (afi3_awaddr),
.afi_awvalid (afi3_awvalid),
.afi_awready (afi3_awready),
.afi_awid (afi3_awid),
.afi_awlock (afi3_awlock),
.afi_awcache (afi3_awcache),
.afi_awprot (afi3_awprot),
.afi_awlen (afi3_awlen),
.afi_awsize (afi3_awsize),
.afi_awburst (afi3_awburst),
.afi_awqos (afi3_awqos),
// write data
.afi_wdata (afi3_wdata),
.afi_wvalid (afi3_wvalid),
.afi_wready (afi3_wready),
.afi_wid (afi3_wid),
.afi_wlast (afi3_wlast),
.afi_wstrb (afi3_wstrb),
// write response
.afi_bvalid (afi3_bvalid),
.afi_bready (afi3_bready),
.afi_bid (afi3_bid),
.afi_bresp (afi3_bresp),
// PL extra (non-AXI) signal
.afi_wcount (afi3_wcount),
.afi_wacount (afi3_wacount),
.afi_wrissuecap1en (afi3_wrissuecap1en),
// AXI_HP signals - read channel
// read address
.afi_araddr (afi3_araddr),
.afi_arvalid (afi3_arvalid),
.afi_arready (afi3_arready),
.afi_arid (afi3_arid),
.afi_arlock (afi3_arlock),
.afi_arcache (afi3_arcache),
.afi_arprot (afi3_arprot),
.afi_arlen (afi3_arlen),
.afi_arsize (afi3_arsize),
.afi_arburst (afi3_arburst),
.afi_arqos (afi3_arqos),
// read data
.afi_rdata (afi3_rdata),
.afi_rvalid (afi3_rvalid),
.afi_rready (afi3_rready),
.afi_rid (afi3_rid),
.afi_rlast (afi3_rlast),
.afi_rresp (afi3_rresp),
// PL extra (non-AXI) signal
.afi_rcount (afi3_rcount),
.afi_racount (afi3_racount),
.afi_rdissuecap1en (afi3_rdissuecap1en),
.irq (irq), // output wire
/*
* PHY
*/
.TXN (TXN),
.TXP (TXP),
.RXN (RXN),
.RXP (RXP),
.EXTCLK_P (EXTCLK_P),
.EXTCLK_N (EXTCLK_N)
);
PS7 ps7_i (
// EMIO interface
// CAN interface
.EMIOCAN0PHYTX(), // CAN 0 TX, output
.EMIOCAN0PHYRX(), // CAN 0 RX, input
.EMIOCAN1PHYTX(), // Can 1 TX, output
.EMIOCAN1PHYRX(), // CAN 1 RX, input
// GMII 0
.EMIOENET0GMIICRS(), // GMII 0 Carrier sense, input
.EMIOENET0GMIICOL(), // GMII 0 Collision detect, input
.EMIOENET0EXTINTIN(), // GMII 0 Controller Interrupt input, input
// GMII 0 TX signals
.EMIOENET0GMIITXCLK(), // GMII 0 TX clock, input
.EMIOENET0GMIITXD(), // GMII 0 Tx Data[7:0], output
.EMIOENET0GMIITXEN(), // GMII 0 Tx En, output
.EMIOENET0GMIITXER(), // GMII 0 Tx Err, output
// GMII 0 TX timestamp signals
.EMIOENET0SOFTX(), // GMII 0 Tx Tx Start-of-Frame, output
.EMIOENET0PTPDELAYREQTX(), // GMII 0 Tx PTP delay req frame detected, output
.EMIOENET0PTPPDELAYREQTX(), // GMII 0 Tx PTP peer delay frame detect, output
.EMIOENET0PTPPDELAYRESPTX(), // GMII 0 Tx PTP pear delay response frame detected, output
.EMIOENET0PTPSYNCFRAMETX(), // GMII 0 Tx PTP sync frame detected, output
// GMII 0 RX signals
.EMIOENET0GMIIRXCLK(), // GMII 0 Rx Clock, input
.EMIOENET0GMIIRXD(), // GMII 0 Rx Data (7:0), input
.EMIOENET0GMIIRXDV(), // GMII 0 Rx Data valid, input
.EMIOENET0GMIIRXER(), // GMII 0 Rx Error, input
// GMII 0 RX timestamp signals
.EMIOENET0SOFRX(), // GMII 0 Rx Start of Frame, output
.EMIOENET0PTPDELAYREQRX(), // GMII 0 Rx PTP delay req frame detected
.EMIOENET0PTPPDELAYREQRX(), // GMII 0 Rx PTP peer delay frame detected, output
.EMIOENET0PTPPDELAYRESPRX(), // GMII 0 Rx PTP peer delay response frame detected, output
.EMIOENET0PTPSYNCFRAMERX(), // GMII 0 Rx PTP sync frame detected, output
// MDIO 0
.EMIOENET0MDIOMDC(), // MDIO 0 MD clock output, output
.EMIOENET0MDIOO(), // MDIO 0 MD data output, output
.EMIOENET0MDIOTN(), // MDIO 0 MD data 3-state, output
.EMIOENET0MDIOI(), // MDIO 0 MD data input, input
// GMII 1
.EMIOENET1GMIICRS(), // GMII 1 Carrier sense, input
.EMIOENET1GMIICOL(), // GMII 1 Collision detect, input
.EMIOENET1EXTINTIN(), // GMII 1 Controller Interrupt input, input
// GMII 1 TX signals
.EMIOENET1GMIITXCLK(), // GMII 1 TX clock, input
.EMIOENET1GMIITXD(), // GMII 1 Tx Data[7:0], output
.EMIOENET1GMIITXEN(), // GMII 1 Tx En, output
.EMIOENET1GMIITXER(), // GMII 1 Tx Err, output
// GMII 1 TX timestamp signals
.EMIOENET1SOFTX(), // GMII 1 Tx Tx Start-of-Frame, output
.EMIOENET1PTPDELAYREQTX(), // GMII 1 Tx PTP delay req frame detected, output
.EMIOENET1PTPPDELAYREQTX(), // GMII 1 Tx PTP peer delay frame detect, output
.EMIOENET1PTPPDELAYRESPTX(), // GMII 1 Tx PTP pear delay response frame detected, output
.EMIOENET1PTPSYNCFRAMETX(), // GMII 1 Tx PTP sync frame detected, output
// GMII 1 RX signals
.EMIOENET1GMIIRXCLK(), // GMII 1 Rx Clock, input
.EMIOENET1GMIIRXD(), // GMII 1 Rx Data (7:0), input
.EMIOENET1GMIIRXDV(), // GMII 1 Rx Data valid, input
.EMIOENET1GMIIRXER(), // GMII 1 Rx Error, input
// GMII 1 RX timestamp signals
.EMIOENET1SOFRX(), // GMII 1 Rx Start of Frame, output
.EMIOENET1PTPDELAYREQRX(), // GMII 1 Rx PTP delay req frame detected
.EMIOENET1PTPPDELAYREQRX(), // GMII 1 Rx PTP peer delay frame detected, output
.EMIOENET1PTPPDELAYRESPRX(), // GMII 1 Rx PTP peer delay response frame detected, output
.EMIOENET1PTPSYNCFRAMERX(), // GMII 1 Rx PTP sync frame detected, output
// MDIO 1
.EMIOENET1MDIOMDC(), // MDIO 1 MD clock output, output
.EMIOENET1MDIOO(), // MDIO 1 MD data output, output
.EMIOENET1MDIOTN(), // MDIO 1 MD data 3-state, output
.EMIOENET1MDIOI(), // MDIO 1 MD data input, input
// EMIO GPIO
.EMIOGPIOO(), // EMIO GPIO Data out[63:0], output
.EMIOGPIOI(/*gpio_in[63:0]*/), // EMIO GPIO Data in[63:0], input
.EMIOGPIOTN(), // EMIO GPIO OutputEnable[63:0], output
// EMIO I2C 0
.EMIOI2C0SCLO(), // I2C 0 SCL OUT, output // manual says input
.EMIOI2C0SCLI(), // I2C 0 SCL IN, input // manual says output
.EMIOI2C0SCLTN(), // I2C 0 SCL EN, output // manual says input
.EMIOI2C0SDAO(), // I2C 0 SDA OUT, output // manual says input
.EMIOI2C0SDAI(), // I2C 0 SDA IN, input // manual says output
.EMIOI2C0SDATN(), // I2C 0 SDA EN, output // manual says input
// EMIO I2C 1
.EMIOI2C1SCLO(), // I2C 1 SCL OUT, output // manual says input
.EMIOI2C1SCLI(), // I2C 1 SCL IN, input // manual says output
.EMIOI2C1SCLTN(), // I2C 1 SCL EN, output // manual says input
.EMIOI2C1SDAO(), // I2C 1 SDA OUT, output // manual says input
.EMIOI2C1SDAI(), // I2C 1 SDA IN, input // manual says output
.EMIOI2C1SDATN(), // I2C 1 SDA EN, output // manual says input
// JTAG
.EMIOPJTAGTCK(), // JTAG TCK, input
.EMIOPJTAGTMS(), // JTAG TMS, input
.EMIOPJTAGTDI(), // JTAG TDI, input
.EMIOPJTAGTDO(), // JTAG TDO, output
.EMIOPJTAGTDTN(), // JTAG TDO OE, output
// SDIO 0
.EMIOSDIO0CLKFB(), // SDIO 0 Clock feedback, input
.EMIOSDIO0CLK(), // SDIO 0 Clock, output
.EMIOSDIO0CMDI(), // SDIO 0 Command in, input
.EMIOSDIO0CMDO(), // SDIO 0 Command out, output
.EMIOSDIO0CMDTN(), // SDIO 0 command OE, output
.EMIOSDIO0DATAI(), // SDIO 0 Data in [3:0], input
.EMIOSDIO0DATAO(), // SDIO 0 Data out [3:0], output
.EMIOSDIO0DATATN(), // SDIO 0 Data OE [3:0], output
.EMIOSDIO0CDN(), // SDIO 0 Card detect, input
.EMIOSDIO0WP(), // SDIO 0 Write protect, input
.EMIOSDIO0BUSPOW(), // SDIO 0 Power control, output
.EMIOSDIO0LED(), // SDIO 0 LED control, output
.EMIOSDIO0BUSVOLT(), // SDIO 0 Bus voltage [2:0], output
// SDIO 1
.EMIOSDIO1CLKFB(), // SDIO 1 Clock feedback, input
.EMIOSDIO1CLK(), // SDIO 1 Clock, output
.EMIOSDIO1CMDI(), // SDIO 1 Command in, input
.EMIOSDIO1CMDO(), // SDIO 1 Command out, output
.EMIOSDIO1CMDTN(), // SDIO 1 command OE, output
.EMIOSDIO1DATAI(), // SDIO 1 Data in [3:0], input
.EMIOSDIO1DATAO(), // SDIO 1 Data out [3:0], output
.EMIOSDIO1DATATN(), // SDIO 1 Data OE [3:0], output
.EMIOSDIO1CDN(), // SDIO 1 Card detect, input
.EMIOSDIO1WP(), // SDIO 1 Write protect, input
.EMIOSDIO1BUSPOW(), // SDIO 1 Power control, output
.EMIOSDIO1LED(), // SDIO 1 LED control, output
.EMIOSDIO1BUSVOLT(), // SDIO 1 Bus voltage [2:0], output
// SPI 0
.EMIOSPI0SCLKI(), // SPI 0 CLK in , input
.EMIOSPI0SCLKO(), // SPI 0 CLK out, output
.EMIOSPI0SCLKTN(), // SPI 0 CLK OE, output
.EMIOSPI0SI(), // SPI 0 MOSI in , input
.EMIOSPI0MO(), // SPI 0 MOSI out , output
.EMIOSPI0MOTN(), // SPI 0 MOSI OE, output
.EMIOSPI0MI(), // SPI 0 MISO in, input
.EMIOSPI0SO(), // SPI 0 MISO out, output
.EMIOSPI0STN(), // SPI 0 MISO OE, output
.EMIOSPI0SSIN(), // SPI 0 Slave select 0 in, input
.EMIOSPI0SSON(), // SPI 0 Slave select [2:0] out, output
.EMIOSPI0SSNTN(), // SPI 0 Slave select OE, output
// SPI 1
.EMIOSPI1SCLKI(), // SPI 1 CLK in , input
.EMIOSPI1SCLKO(), // SPI 1 CLK out, output
.EMIOSPI1SCLKTN(), // SPI 1 CLK OE, output
.EMIOSPI1SI(), // SPI 1 MOSI in , input
.EMIOSPI1MO(), // SPI 1 MOSI out , output
.EMIOSPI1MOTN(), // SPI 1 MOSI OE, output
.EMIOSPI1MI(), // SPI 1 MISO in, input
.EMIOSPI1SO(), // SPI 1 MISO out, output
.EMIOSPI1STN(), // SPI 1 MISO OE, output
.EMIOSPI1SSIN(), // SPI 1 Slave select 0 in, input
.EMIOSPI1SSON(), // SPI 1 Slave select [2:0] out, output
.EMIOSPI1SSNTN(), // SPI 1 Slave select OE, output
// TPIU signals (Trace)
.EMIOTRACECTL(), // Trace CTL, output
.EMIOTRACEDATA(), // Trace Data[31:0], output
.EMIOTRACECLK(), // Trace CLK, input
// Timers/counters
.EMIOTTC0CLKI(), // Counter/Timer 0 clock in [2:0], input
.EMIOTTC0WAVEO(), // Counter/Timer 0 wave out[2:0], output
.EMIOTTC1CLKI(), // Counter/Timer 1 clock in [2:0], input
.EMIOTTC1WAVEO(), // Counter/Timer 1 wave out[2:0], output
//UART 0
.EMIOUART0TX(), // UART 0 Transmit, output
.EMIOUART0RX(), // UART 0 Receive, input
.EMIOUART0CTSN(), // UART 0 Clear To Send, input
.EMIOUART0RTSN(), // UART 0 Ready to Send, output
.EMIOUART0DSRN(), // UART 0 Data Set Ready , input
.EMIOUART0DCDN(), // UART 0 Data Carrier Detect, input
.EMIOUART0RIN(), // UART 0 Ring Indicator, input
.EMIOUART0DTRN(), // UART 0 Data Terminal Ready, output
//UART 1
.EMIOUART1TX(), // UART 1 Transmit, output
.EMIOUART1RX(), // UART 1 Receive, input
.EMIOUART1CTSN(), // UART 1 Clear To Send, input
.EMIOUART1RTSN(), // UART 1 Ready to Send, output
.EMIOUART1DSRN(), // UART 1 Data Set Ready , input
.EMIOUART1DCDN(), // UART 1 Data Carrier Detect, input
.EMIOUART1RIN(), // UART 1 Ring Indicator, input
.EMIOUART1DTRN(), // UART 1 Data Terminal Ready, output
// USB 0
.EMIOUSB0PORTINDCTL(), // USB 0 Port Indicator [1:0], output
.EMIOUSB0VBUSPWRFAULT(), // USB 0 Power Fault, input
.EMIOUSB0VBUSPWRSELECT(), // USB 0 Power Select, output
// USB 1
.EMIOUSB1PORTINDCTL(), // USB 1 Port Indicator [1:0], output
.EMIOUSB1VBUSPWRFAULT(), // USB 1 Power Fault, input
.EMIOUSB1VBUSPWRSELECT(), // USB 1 Power Select, output
// Watchdog Timer
.EMIOWDTCLKI(), // Watchdog Timer Clock in, input
.EMIOWDTRSTO(), // Watchdog Timer Reset out, output
// DMAC 0
.DMA0ACLK(), // DMAC 0 Clock, input
.DMA0DRVALID(), // DMAC 0 DMA Request Valid, input
.DMA0DRLAST(), // DMAC 0 DMA Request Last, input
.DMA0DRTYPE(), // DMAC 0 DMA Request Type [1:0] ()single/burst/ackn flush/reserved), input
.DMA0DRREADY(), // DMAC 0 DMA Request Ready, output
.DMA0DAVALID(), // DMAC 0 DMA Acknowledge Valid (DA_TYPE[1:0] valid), output
.DMA0DAREADY(), // DMAC 0 DMA Acknowledge (peripheral can accept DA_TYPE[1:0]), input
.DMA0DATYPE(), // DMAC 0 DMA Ackbowledge TYpe (completed single AXI, completed burst AXI, flush request), output
.DMA0RSTN(), // DMAC 0 RESET output (reserved, do not use), output
// DMAC 1
.DMA1ACLK(), // DMAC 1 Clock, input
.DMA1DRVALID(), // DMAC 1 DMA Request Valid, input
.DMA1DRLAST(), // DMAC 1 DMA Request Last, input
.DMA1DRTYPE(), // DMAC 1 DMA Request Type [1:0] ()single/burst/ackn flush/reserved), input
.DMA1DRREADY(), // DMAC 1 DMA Request Ready, output
.DMA1DAVALID(), // DMAC 1 DMA Acknowledge Valid (DA_TYPE[1:0] valid), output
.DMA1DAREADY(), // DMAC 1 DMA Acknowledge (peripheral can accept DA_TYPE[1:0]), input
.DMA1DATYPE(), // DMAC 1 DMA Ackbowledge TYpe (completed single AXI, completed burst AXI, flush request), output
.DMA1RSTN(), // DMAC 1 RESET output (reserved, do not use), output
// DMAC 2
.DMA2ACLK(), // DMAC 2 Clock, input
.DMA2DRVALID(), // DMAC 2 DMA Request Valid, input
.DMA2DRLAST(), // DMAC 2 DMA Request Last, input
.DMA2DRTYPE(), // DMAC 2 DMA Request Type [1:0] ()single/burst/ackn flush/reserved), input
.DMA2DRREADY(), // DMAC 2 DMA Request Ready, output
.DMA2DAVALID(), // DMAC 2 DMA Acknowledge Valid (DA_TYPE[1:0] valid), output
.DMA2DAREADY(), // DMAC 2 DMA Acknowledge (peripheral can accept DA_TYPE[1:0]), input
.DMA2DATYPE(), // DMAC 2 DMA Ackbowledge TYpe (completed single AXI, completed burst AXI, flush request), output
.DMA2RSTN(), // DMAC 2 RESET output (reserved, do not use), output
// DMAC 3
.DMA3ACLK(), // DMAC 3 Clock, input
.DMA3DRVALID(), // DMAC 3 DMA Request Valid, input
.DMA3DRLAST(), // DMAC 3 DMA Request Last, input
.DMA3DRTYPE(), // DMAC 3 DMA Request Type [1:0] ()single/burst/ackn flush/reserved), input
.DMA3DRREADY(), // DMAC 3 DMA Request Ready, output
.DMA3DAVALID(), // DMAC 3 DMA Acknowledge Valid (DA_TYPE[1:0] valid), output
.DMA3DAREADY(), // DMAC 3 DMA Acknowledge (peripheral can accept DA_TYPE[1:0]), input
.DMA3DATYPE(), // DMAC 3 DMA Ackbowledge TYpe (completed single AXI, completed burst AXI, flush request), output
.DMA3RSTN(), // DMAC 3 RESET output (reserved, do not use), output
// Interrupt signals
.IRQF2P({19'b0,irq}), // Interrupts, PL to PS [19:0], input
.IRQP2F(), // Interrupts, PS to PL [28:0], output
// Event Signals
.EVENTEVENTI(), // EVENT Wake up one or both CPU from WFE state, input
.EVENTEVENTO(), // EVENT Asserted when one of the COUs executed SEV instruction, output
.EVENTSTANDBYWFE(), // EVENT CPU standby mode [1:0], asserted when CPU is waiting for an event, output
.EVENTSTANDBYWFI(), // EVENT CPU standby mode [1:0], asserted when CPU is waiting for an interrupt, output
// PL Resets and clocks
.FCLKCLK(fclk[3:0]), // PL Clocks [3:0], output
.FCLKCLKTRIGN(), // PL Clock Throttle Control [3:0], input
.FCLKRESETN(frst[3:0]), // PL General purpose user reset [3:0], output (active low)
// Debug signals
.FTMTP2FDEBUG(), // Debug General purpose debug output [31:0], output
.FTMTF2PDEBUG(), // Debug General purpose debug input [31:0], input
.FTMTP2FTRIG(), // Debug Trigger PS to PL [3:0], output
.FTMTP2FTRIGACK(), // Debug Trigger PS to PL acknowledge[3:0], input
.FTMTF2PTRIG(), // Debug Trigger PL to PS [3:0], input
.FTMTF2PTRIGACK(), // Debug Trigger PL to PS acknowledge[3:0], output
.FTMDTRACEINCLOCK(), // Debug Trace PL to PS Clock, input
.FTMDTRACEINVALID(), // Debug Trace PL to PS Clock, data&id valid, input
.FTMDTRACEINDATA(), // Debug Trace PL to PS data [31:0], input
.FTMDTRACEINATID(), // Debug Trace PL to PS ID [3:0], input
// DDR Urgent
.DDRARB(), // DDR Urgent[3:0], input
// SRAM interrupt (on rising edge)
.EMIOSRAMINTIN(), // SRAM interrupt #50 shared with NAND busy, input
// AXI interfaces
.FPGAIDLEN(1'b1), //Idle PL AXI interfaces (active low), input
// AXI PS Master GP0
// AXI PS Master GP0: Clock, Reset
.MAXIGP0ACLK(/*axi_aclk*/), // AXI PS Master GP0 Clock , input
// .MAXIGP0ACLK(/*fclk[0]*/), // AXI PS Master GP0 Clock , input
// .MAXIGP0ACLK(/*~fclk[0]*/), // AXI PS Master GP0 Clock , input
// .MAXIGP0ACLK(/*axi_naclk*/), // AXI PS Master GP0 Clock , input
//
.MAXIGP0ARESETN(), // AXI PS Master GP0 Reset, output
// AXI PS Master GP0: Read Address
.MAXIGP0ARADDR (/*axi_araddr[31:0]*/), // AXI PS Master GP0 ARADDR[31:0], output
.MAXIGP0ARVALID (/*axi_arvalid*/), // AXI PS Master GP0 ARVALID, output
.MAXIGP0ARREADY (/*axi_arready*/), // AXI PS Master GP0 ARREADY, input
.MAXIGP0ARID (/*axi_arid[11:0]*/), // AXI PS Master GP0 ARID[11:0], output
.MAXIGP0ARLOCK (), // AXI PS Master GP0 ARLOCK[1:0], output
.MAXIGP0ARCACHE (),// AXI PS Master GP0 ARCACHE[3:0], output
.MAXIGP0ARPROT(), // AXI PS Master GP0 ARPROT[2:0], output
.MAXIGP0ARLEN (/*axi_arlen[3:0]*/), // AXI PS Master GP0 ARLEN[3:0], output
.MAXIGP0ARSIZE (/*axi_arsize[1:0]*/), // AXI PS Master GP0 ARSIZE[1:0], output
.MAXIGP0ARBURST (/*axi_arburst[1:0]*/),// AXI PS Master GP0 ARBURST[1:0], output
.MAXIGP0ARQOS (), // AXI PS Master GP0 ARQOS[3:0], output
// AXI PS Master GP0: Read Data
.MAXIGP0RDATA (/*axi_rdata[31:0]*/), // AXI PS Master GP0 RDATA[31:0], input
.MAXIGP0RVALID (/*axi_rvalid*/), // AXI PS Master GP0 RVALID, input
.MAXIGP0RREADY (/*axi_rready*/), // AXI PS Master GP0 RREADY, output
.MAXIGP0RID (/*axi_rid[11:0]*/), // AXI PS Master GP0 RID[11:0], input
.MAXIGP0RLAST (/*axi_rlast*/), // AXI PS Master GP0 RLAST, input
.MAXIGP0RRESP (/*axi_rresp[1:0]*/), // AXI PS Master GP0 RRESP[1:0], input
// AXI PS Master GP0: Write Address
.MAXIGP0AWADDR (/*axi_awaddr[31:0]*/), // AXI PS Master GP0 AWADDR[31:0], output
.MAXIGP0AWVALID (/*axi_awvalid*/), // AXI PS Master GP0 AWVALID, output
.MAXIGP0AWREADY (/*axi_awready*/), // AXI PS Master GP0 AWREADY, input
.MAXIGP0AWID (/*axi_awid[11:0]*/), // AXI PS Master GP0 AWID[11:0], output
.MAXIGP0AWLOCK (), // AXI PS Master GP0 AWLOCK[1:0], output
.MAXIGP0AWCACHE (),// AXI PS Master GP0 AWCACHE[3:0], output
.MAXIGP0AWPROT (), // AXI PS Master GP0 AWPROT[2:0], output
.MAXIGP0AWLEN (/*axi_awlen[3:0]*/), // AXI PS Master GP0 AWLEN[3:0], output
.MAXIGP0AWSIZE (/*axi_awsize[1:0]*/), // AXI PS Master GP0 AWSIZE[1:0], output
.MAXIGP0AWBURST (/*axi_awburst[1:0]*/),// AXI PS Master GP0 AWBURST[1:0], output
.MAXIGP0AWQOS (), // AXI PS Master GP0 AWQOS[3:0], output
// AXI PS Master GP0: Write Data
.MAXIGP0WDATA (/*axi_wdata[31:0]*/), // AXI PS Master GP0 WDATA[31:0], output
.MAXIGP0WVALID (/*axi_wvalid*/), // AXI PS Master GP0 WVALID, output
.MAXIGP0WREADY (/*axi_wready*/), // AXI PS Master GP0 WREADY, input
.MAXIGP0WID (/*axi_wid[11:0]*/), // AXI PS Master GP0 WID[11:0], output
.MAXIGP0WLAST (/*axi_wlast*/), // AXI PS Master GP0 WLAST, output
.MAXIGP0WSTRB (/*axi_wstb[3:0]*/), // AXI PS Master GP0 WSTRB[3:0], output
// AXI PS Master GP0: Write response
.MAXIGP0BVALID (/*axi_bvalid*/), // AXI PS Master GP0 BVALID, input
.MAXIGP0BREADY (/*axi_bready*/), // AXI PS Master GP0 BREADY, output
.MAXIGP0BID (/*axi_bid[11:0]*/), // AXI PS Master GP0 BID[11:0], input
.MAXIGP0BRESP (/*axi_bresp[1:0]*/), // AXI PS Master GP0 BRESP[1:0], input
// AXI PS Master GP1
// AXI PS Master GP1: Clock, Reset
.MAXIGP1ACLK (axi_aclk0), // AXI PS Master GP1 Clock , input
.MAXIGP1ARESETN (), // AXI PS Master GP1 Reset, output
// AXI PS Master GP1: Read Address
.MAXIGP1ARADDR (maxi1_araddr), // AXI PS Master GP1 ARADDR[31:0], output
.MAXIGP1ARVALID (maxi1_arvalid), // AXI PS Master GP1 ARVALID, output
.MAXIGP1ARREADY (maxi1_arready), // AXI PS Master GP1 ARREADY, input
.MAXIGP1ARID (maxi1_arid), // AXI PS Master GP1 ARID[11:0], output
.MAXIGP1ARLOCK (), // AXI PS Master GP1 ARLOCK[1:0], output
.MAXIGP1ARCACHE (), // AXI PS Master GP1 ARCACHE[3:0], output
.MAXIGP1ARPROT (), // AXI PS Master GP1 ARPROT[2:0], output
.MAXIGP1ARLEN (maxi1_arlen), // AXI PS Master GP1 ARLEN[3:0], output
.MAXIGP1ARSIZE (maxi1_arsize), // AXI PS Master GP1 ARSIZE[1:0], output
.MAXIGP1ARBURST (maxi1_arburst), // AXI PS Master GP1 ARBURST[1:0], output
.MAXIGP1ARQOS (), // AXI PS Master GP1 ARQOS[3:0], output
// AXI PS Master GP1: Read Data
.MAXIGP1RDATA (maxi1_rdata), // AXI PS Master GP1 RDATA[31:0], input
.MAXIGP1RVALID (maxi1_rvalid), // AXI PS Master GP1 RVALID, input
.MAXIGP1RREADY (maxi1_rready), // AXI PS Master GP1 RREADY, output
.MAXIGP1RID (maxi1_rid), // AXI PS Master GP1 RID[11:0], input
.MAXIGP1RLAST (maxi1_rlast), // AXI PS Master GP1 RLAST, input
.MAXIGP1RRESP (maxi1_rresp), // AXI PS Master GP1 RRESP[1:0], input
// AXI PS Master GP1: Write Address
.MAXIGP1AWADDR (maxi1_awaddr), // AXI PS Master GP1 AWADDR[31:0], output
.MAXIGP1AWVALID (maxi1_awvalid), // AXI PS Master GP1 AWVALID, output
.MAXIGP1AWREADY (maxi1_awready), // AXI PS Master GP1 AWREADY, input
.MAXIGP1AWID (maxi1_awid), // AXI PS Master GP1 AWID[11:0], output
.MAXIGP1AWLOCK (), // AXI PS Master GP1 AWLOCK[1:0], output
.MAXIGP1AWCACHE (), // AXI PS Master GP1 AWCACHE[3:0], output
.MAXIGP1AWPROT (), // AXI PS Master GP1 AWPROT[2:0], output
.MAXIGP1AWLEN (maxi1_awlen), // AXI PS Master GP1 AWLEN[3:0], output
.MAXIGP1AWSIZE (maxi1_awsize), // AXI PS Master GP1 AWSIZE[1:0], output
.MAXIGP1AWBURST (maxi1_awburst), // AXI PS Master GP1 AWBURST[1:0], output
.MAXIGP1AWQOS (), // AXI PS Master GP1 AWQOS[3:0], output
// AXI PS Master GP1: Write Data
.MAXIGP1WDATA (maxi1_wdata), // AXI PS Master GP1 WDATA[31:0], output
.MAXIGP1WVALID (maxi1_wvalid), // AXI PS Master GP1 WVALID, output
.MAXIGP1WREADY (maxi1_wready), // AXI PS Master GP1 WREADY, input
.MAXIGP1WID (maxi1_wid), // AXI PS Master GP1 WID[11:0], output
.MAXIGP1WLAST (maxi1_wlast), // AXI PS Master GP1 WLAST, output
.MAXIGP1WSTRB (maxi1_wstb), // AXI PS Master GP1 maxi1_wstb[3:0], output
// AXI PS Master GP1: Write response
.MAXIGP1BVALID (maxi1_bvalid), // AXI PS Master GP1 BVALID, input
.MAXIGP1BREADY (maxi1_bready), // AXI PS Master GP1 BREADY, output
.MAXIGP1BID (maxi1_bid), // AXI PS Master GP1 BID[11:0], input
.MAXIGP1BRESP (maxi1_bresp), // AXI PS Master GP1 BRESP[1:0], input
// AXI PS Slave GP0
// AXI PS Slave GP0: Clock, Reset
.SAXIGP0ACLK(), // AXI PS Slave GP0 Clock , input
.SAXIGP0ARESETN(), // AXI PS Slave GP0 Reset, output
// AXI PS Slave GP0: Read Address
.SAXIGP0ARADDR(), // AXI PS Slave GP0 ARADDR[31:0], input
.SAXIGP0ARVALID(), // AXI PS Slave GP0 ARVALID, input
.SAXIGP0ARREADY(), // AXI PS Slave GP0 ARREADY, output
.SAXIGP0ARID(), // AXI PS Slave GP0 ARID[5:0], input
.SAXIGP0ARLOCK(), // AXI PS Slave GP0 ARLOCK[1:0], input
.SAXIGP0ARCACHE(), // AXI PS Slave GP0 ARCACHE[3:0], input
.SAXIGP0ARPROT(), // AXI PS Slave GP0 ARPROT[2:0], input
.SAXIGP0ARLEN(), // AXI PS Slave GP0 ARLEN[3:0], input
.SAXIGP0ARSIZE(), // AXI PS Slave GP0 ARSIZE[1:0], input
.SAXIGP0ARBURST(), // AXI PS Slave GP0 ARBURST[1:0], input
.SAXIGP0ARQOS(), // AXI PS Slave GP0 ARQOS[3:0], input
// AXI PS Slave GP0: Read Data
.SAXIGP0RDATA(), // AXI PS Slave GP0 RDATA[31:0], output
.SAXIGP0RVALID(), // AXI PS Slave GP0 RVALID, output
.SAXIGP0RREADY(), // AXI PS Slave GP0 RREADY, input
.SAXIGP0RID(), // AXI PS Slave GP0 RID[5:0], output
.SAXIGP0RLAST(), // AXI PS Slave GP0 RLAST, output
.SAXIGP0RRESP(), // AXI PS Slave GP0 RRESP[1:0], output
// AXI PS Slave GP0: Write Address
.SAXIGP0AWADDR(), // AXI PS Slave GP0 AWADDR[31:0], input
.SAXIGP0AWVALID(), // AXI PS Slave GP0 AWVALID, input
.SAXIGP0AWREADY(), // AXI PS Slave GP0 AWREADY, output
.SAXIGP0AWID(), // AXI PS Slave GP0 AWID[5:0], input
.SAXIGP0AWLOCK(), // AXI PS Slave GP0 AWLOCK[1:0], input
.SAXIGP0AWCACHE(), // AXI PS Slave GP0 AWCACHE[3:0], input
.SAXIGP0AWPROT(), // AXI PS Slave GP0 AWPROT[2:0], input
.SAXIGP0AWLEN(), // AXI PS Slave GP0 AWLEN[3:0], input
.SAXIGP0AWSIZE(), // AXI PS Slave GP0 AWSIZE[1:0], input
.SAXIGP0AWBURST(), // AXI PS Slave GP0 AWBURST[1:0], input
.SAXIGP0AWQOS(), // AXI PS Slave GP0 AWQOS[3:0], input
// AXI PS Slave GP0: Write Data
.SAXIGP0WDATA(), // AXI PS Slave GP0 WDATA[31:0], input
.SAXIGP0WVALID(), // AXI PS Slave GP0 WVALID, input
.SAXIGP0WREADY(), // AXI PS Slave GP0 WREADY, output
.SAXIGP0WID(), // AXI PS Slave GP0 WID[5:0], input
.SAXIGP0WLAST(), // AXI PS Slave GP0 WLAST, input
.SAXIGP0WSTRB(), // AXI PS Slave GP0 WSTRB[3:0], input
// AXI PS Slave GP0: Write response
.SAXIGP0BVALID(), // AXI PS Slave GP0 BVALID, output
.SAXIGP0BREADY(), // AXI PS Slave GP0 BREADY, input
.SAXIGP0BID(), // AXI PS Slave GP0 BID[5:0], output //TODO: Update range !!!
.SAXIGP0BRESP(), // AXI PS Slave GP0 BRESP[1:0], output
// AXI PS Slave GP1
// AXI PS Slave GP1: Clock, Reset
.SAXIGP1ACLK(), // AXI PS Slave GP1 Clock , input
.SAXIGP1ARESETN(), // AXI PS Slave GP1 Reset, output
// AXI PS Slave GP1: Read Address
.SAXIGP1ARADDR(), // AXI PS Slave GP1 ARADDR[31:0], input
.SAXIGP1ARVALID(), // AXI PS Slave GP1 ARVALID, input
.SAXIGP1ARREADY(), // AXI PS Slave GP1 ARREADY, output
.SAXIGP1ARID(), // AXI PS Slave GP1 ARID[5:0], input
.SAXIGP1ARLOCK(), // AXI PS Slave GP1 ARLOCK[1:0], input
.SAXIGP1ARCACHE(), // AXI PS Slave GP1 ARCACHE[3:0], input
.SAXIGP1ARPROT(), // AXI PS Slave GP1 ARPROT[2:0], input
.SAXIGP1ARLEN(), // AXI PS Slave GP1 ARLEN[3:0], input
.SAXIGP1ARSIZE(), // AXI PS Slave GP1 ARSIZE[1:0], input
.SAXIGP1ARBURST(), // AXI PS Slave GP1 ARBURST[1:0], input
.SAXIGP1ARQOS(), // AXI PS Slave GP1 ARQOS[3:0], input
// AXI PS Slave GP1: Read Data
.SAXIGP1RDATA(), // AXI PS Slave GP1 RDATA[31:0], output
.SAXIGP1RVALID(), // AXI PS Slave GP1 RVALID, output
.SAXIGP1RREADY(), // AXI PS Slave GP1 RREADY, input
.SAXIGP1RID(), // AXI PS Slave GP1 RID[5:0], output
.SAXIGP1RLAST(), // AXI PS Slave GP1 RLAST, output
.SAXIGP1RRESP(), // AXI PS Slave GP1 RRESP[1:0], output
// AXI PS Slave GP1: Write Address
.SAXIGP1AWADDR(), // AXI PS Slave GP1 AWADDR[31:0], input
.SAXIGP1AWVALID(), // AXI PS Slave GP1 AWVALID, input
.SAXIGP1AWREADY(), // AXI PS Slave GP1 AWREADY, output
.SAXIGP1AWID(), // AXI PS Slave GP1 AWID[5:0], input
.SAXIGP1AWLOCK(), // AXI PS Slave GP1 AWLOCK[1:0], input
.SAXIGP1AWCACHE(), // AXI PS Slave GP1 AWCACHE[3:0], input
.SAXIGP1AWPROT(), // AXI PS Slave GP1 AWPROT[2:0], input
.SAXIGP1AWLEN(), // AXI PS Slave GP1 AWLEN[3:0], input
.SAXIGP1AWSIZE(), // AXI PS Slave GP1 AWSIZE[1:0], input
.SAXIGP1AWBURST(), // AXI PS Slave GP1 AWBURST[1:0], input
.SAXIGP1AWQOS(), // AXI PS Slave GP1 AWQOS[3:0], input
// AXI PS Slave GP1: Write Data
.SAXIGP1WDATA(), // AXI PS Slave GP1 WDATA[31:0], input
.SAXIGP1WVALID(), // AXI PS Slave GP1 WVALID, input
.SAXIGP1WREADY(), // AXI PS Slave GP1 WREADY, output
.SAXIGP1WID(), // AXI PS Slave GP1 WID[5:0], input
.SAXIGP1WLAST(), // AXI PS Slave GP1 WLAST, input
.SAXIGP1WSTRB(), // AXI PS Slave GP1 WSTRB[3:0], input
// AXI PS Slave GP1: Write response
.SAXIGP1BVALID(), // AXI PS Slave GP1 BVALID, output
.SAXIGP1BREADY(), // AXI PS Slave GP1 BREADY, input
.SAXIGP1BID(), // AXI PS Slave GP1 BID[5:0], output
.SAXIGP1BRESP(), // AXI PS Slave GP1 BRESP[1:0], output
// AXI PS Slave HP0
// AXI PS Slave HP0: Clock, Reset
.SAXIHP0ACLK(), // AXI PS Slave HP0 Clock , input
.SAXIHP0ARESETN(), // AXI PS Slave HP0 Reset, output
// AXI PS Slave HP0: Read Address
.SAXIHP0ARADDR(), // AXI PS Slave HP0 ARADDR[31:0], input
.SAXIHP0ARVALID(), // AXI PS Slave HP0 ARVALID, input
.SAXIHP0ARREADY(), // AXI PS Slave HP0 ARREADY, output
.SAXIHP0ARID(), // AXI PS Slave HP0 ARID[5:0], input
.SAXIHP0ARLOCK(), // AXI PS Slave HP0 ARLOCK[1:0], input
.SAXIHP0ARCACHE(), // AXI PS Slave HP0 ARCACHE[3:0], input
.SAXIHP0ARPROT(), // AXI PS Slave HP0 ARPROT[2:0], input
.SAXIHP0ARLEN(), // AXI PS Slave HP0 ARLEN[3:0], input
.SAXIHP0ARSIZE(), // AXI PS Slave HP0 ARSIZE[2:0], input
.SAXIHP0ARBURST(), // AXI PS Slave HP0 ARBURST[1:0], input
.SAXIHP0ARQOS(), // AXI PS Slave HP0 ARQOS[3:0], input
// AXI PS Slave HP0: Read Data
.SAXIHP0RDATA(), // AXI PS Slave HP0 RDATA[63:0], output
.SAXIHP0RVALID(), // AXI PS Slave HP0 RVALID, output
.SAXIHP0RREADY(), // AXI PS Slave HP0 RREADY, input
.SAXIHP0RID(), // AXI PS Slave HP0 RID[5:0], output
.SAXIHP0RLAST(), // AXI PS Slave HP0 RLAST, output
.SAXIHP0RRESP(), // AXI PS Slave HP0 RRESP[1:0], output
.SAXIHP0RCOUNT(), // AXI PS Slave HP0 RCOUNT[7:0], output
.SAXIHP0RACOUNT(), // AXI PS Slave HP0 RACOUNT[2:0], output
.SAXIHP0RDISSUECAP1EN(), // AXI PS Slave HP0 RDISSUECAP1EN, input
// AXI PS Slave HP0: Write Address
.SAXIHP0AWADDR(), // AXI PS Slave HP0 AWADDR[31:0], input
.SAXIHP0AWVALID(), // AXI PS Slave HP0 AWVALID, input
.SAXIHP0AWREADY(), // AXI PS Slave HP0 AWREADY, output
.SAXIHP0AWID(), // AXI PS Slave HP0 AWID[5:0], input
.SAXIHP0AWLOCK(), // AXI PS Slave HP0 AWLOCK[1:0], input
.SAXIHP0AWCACHE(), // AXI PS Slave HP0 AWCACHE[3:0], input
.SAXIHP0AWPROT(), // AXI PS Slave HP0 AWPROT[2:0], input
.SAXIHP0AWLEN(), // AXI PS Slave HP0 AWLEN[3:0], input
.SAXIHP0AWSIZE(), // AXI PS Slave HP0 AWSIZE[1:0], input
.SAXIHP0AWBURST(), // AXI PS Slave HP0 AWBURST[1:0], input
.SAXIHP0AWQOS(), // AXI PS Slave HP0 AWQOS[3:0], input
// AXI PS Slave HP0: Write Data
.SAXIHP0WDATA(), // AXI PS Slave HP0 WDATA[63:0], input
.SAXIHP0WVALID(), // AXI PS Slave HP0 WVALID, input
.SAXIHP0WREADY(), // AXI PS Slave HP0 WREADY, output
.SAXIHP0WID(), // AXI PS Slave HP0 WID[5:0], input
.SAXIHP0WLAST(), // AXI PS Slave HP0 WLAST, input
.SAXIHP0WSTRB(), // AXI PS Slave HP0 WSTRB[7:0], input
.SAXIHP0WCOUNT(), // AXI PS Slave HP0 WCOUNT[7:0], output
.SAXIHP0WACOUNT(), // AXI PS Slave HP0 WACOUNT[5:0], output
.SAXIHP0WRISSUECAP1EN(), // AXI PS Slave HP0 WRISSUECAP1EN, input
// AXI PS Slave HP0: Write response
.SAXIHP0BVALID(), // AXI PS Slave HP0 BVALID, output
.SAXIHP0BREADY(), // AXI PS Slave HP0 BREADY, input
.SAXIHP0BID(), // AXI PS Slave HP0 BID[5:0], output
.SAXIHP0BRESP(), // AXI PS Slave HP0 BRESP[1:0], output
// AXI PS Slave HP1
// AXI PS Slave 1: Clock, Reset
.SAXIHP1ACLK(), // AXI PS Slave HP1 Clock , input
.SAXIHP1ARESETN(), // AXI PS Slave HP1 Reset, output
// AXI PS Slave HP1: Read Address
.SAXIHP1ARADDR(), // AXI PS Slave HP1 ARADDR[31:0], input
.SAXIHP1ARVALID(), // AXI PS Slave HP1 ARVALID, input
.SAXIHP1ARREADY(), // AXI PS Slave HP1 ARREADY, output
.SAXIHP1ARID(), // AXI PS Slave HP1 ARID[5:0], input
.SAXIHP1ARLOCK(), // AXI PS Slave HP1 ARLOCK[1:0], input
.SAXIHP1ARCACHE(), // AXI PS Slave HP1 ARCACHE[3:0], input
.SAXIHP1ARPROT(), // AXI PS Slave HP1 ARPROT[2:0], input
.SAXIHP1ARLEN(), // AXI PS Slave HP1 ARLEN[3:0], input
.SAXIHP1ARSIZE(), // AXI PS Slave HP1 ARSIZE[2:0], input
.SAXIHP1ARBURST(), // AXI PS Slave HP1 ARBURST[1:0], input
.SAXIHP1ARQOS(), // AXI PS Slave HP1 ARQOS[3:0], input
// AXI PS Slave HP1: Read Data
.SAXIHP1RDATA(), // AXI PS Slave HP1 RDATA[63:0], output
.SAXIHP1RVALID(), // AXI PS Slave HP1 RVALID, output
.SAXIHP1RREADY(), // AXI PS Slave HP1 RREADY, input
.SAXIHP1RID(), // AXI PS Slave HP1 RID[5:0], output
.SAXIHP1RLAST(), // AXI PS Slave HP1 RLAST, output
.SAXIHP1RRESP(), // AXI PS Slave HP1 RRESP[1:0], output
.SAXIHP1RCOUNT(), // AXI PS Slave HP1 RCOUNT[7:0], output
.SAXIHP1RACOUNT(), // AXI PS Slave HP1 RACOUNT[2:0], output
.SAXIHP1RDISSUECAP1EN(), // AXI PS Slave HP1 RDISSUECAP1EN, input
// AXI PS Slave HP1: Write Address
.SAXIHP1AWADDR(), // AXI PS Slave HP1 AWADDR[31:0], input
.SAXIHP1AWVALID(), // AXI PS Slave HP1 AWVALID, input
.SAXIHP1AWREADY(), // AXI PS Slave HP1 AWREADY, output
.SAXIHP1AWID(), // AXI PS Slave HP1 AWID[5:0], input
.SAXIHP1AWLOCK(), // AXI PS Slave HP1 AWLOCK[1:0], input
.SAXIHP1AWCACHE(), // AXI PS Slave HP1 AWCACHE[3:0], input
.SAXIHP1AWPROT(), // AXI PS Slave HP1 AWPROT[2:0], input
.SAXIHP1AWLEN(), // AXI PS Slave HP1 AWLEN[3:0], input
.SAXIHP1AWSIZE(), // AXI PS Slave HP1 AWSIZE[1:0], input
.SAXIHP1AWBURST(), // AXI PS Slave HP1 AWBURST[1:0], input
.SAXIHP1AWQOS(), // AXI PS Slave HP1 AWQOS[3:0], input
// AXI PS Slave HP1: Write Data
.SAXIHP1WDATA(), // AXI PS Slave HP1 WDATA[63:0], input
.SAXIHP1WVALID(), // AXI PS Slave HP1 WVALID, input
.SAXIHP1WREADY(), // AXI PS Slave HP1 WREADY, output
.SAXIHP1WID(), // AXI PS Slave HP1 WID[5:0], input
.SAXIHP1WLAST(), // AXI PS Slave HP1 WLAST, input
.SAXIHP1WSTRB(), // AXI PS Slave HP1 WSTRB[7:0], input
.SAXIHP1WCOUNT(), // AXI PS Slave HP1 WCOUNT[7:0], output
.SAXIHP1WACOUNT(), // AXI PS Slave HP1 WACOUNT[5:0], output
.SAXIHP1WRISSUECAP1EN(), // AXI PS Slave HP1 WRISSUECAP1EN, input
// AXI PS Slave HP1: Write response
.SAXIHP1BVALID(), // AXI PS Slave HP1 BVALID, output
.SAXIHP1BREADY(), // AXI PS Slave HP1 BREADY, input
.SAXIHP1BID(), // AXI PS Slave HP1 BID[5:0], output
.SAXIHP1BRESP(), // AXI PS Slave HP1 BRESP[1:0], output
// AXI PS Slave HP2
// AXI PS Slave HP2: Clock, Reset
.SAXIHP2ACLK(), // AXI PS Slave HP2 Clock , input
.SAXIHP2ARESETN(), // AXI PS Slave HP2 Reset, output
// AXI PS Slave HP2: Read Address
.SAXIHP2ARADDR(), // AXI PS Slave HP2 ARADDR[31:0], input
.SAXIHP2ARVALID(), // AXI PS Slave HP2 ARVALID, input
.SAXIHP2ARREADY(), // AXI PS Slave HP2 ARREADY, output
.SAXIHP2ARID(), // AXI PS Slave HP2 ARID[5:0], input
.SAXIHP2ARLOCK(), // AXI PS Slave HP2 ARLOCK[1:0], input
.SAXIHP2ARCACHE(), // AXI PS Slave HP2 ARCACHE[3:0], input
.SAXIHP2ARPROT(), // AXI PS Slave HP2 ARPROT[2:0], input
.SAXIHP2ARLEN(), // AXI PS Slave HP2 ARLEN[3:0], input
.SAXIHP2ARSIZE(), // AXI PS Slave HP2 ARSIZE[2:0], input
.SAXIHP2ARBURST(), // AXI PS Slave HP2 ARBURST[1:0], input
.SAXIHP2ARQOS(), // AXI PS Slave HP2 ARQOS[3:0], input
// AXI PS Slave HP2: Read Data
.SAXIHP2RDATA(), // AXI PS Slave HP2 RDATA[63:0], output
.SAXIHP2RVALID(), // AXI PS Slave HP2 RVALID, output
.SAXIHP2RREADY(), // AXI PS Slave HP2 RREADY, input
.SAXIHP2RID(), // AXI PS Slave HP2 RID[5:0], output
.SAXIHP2RLAST(), // AXI PS Slave HP2 RLAST, output
.SAXIHP2RRESP(), // AXI PS Slave HP2 RRESP[1:0], output
.SAXIHP2RCOUNT(), // AXI PS Slave HP2 RCOUNT[7:0], output
.SAXIHP2RACOUNT(), // AXI PS Slave HP2 RACOUNT[2:0], output
.SAXIHP2RDISSUECAP1EN(), // AXI PS Slave HP2 RDISSUECAP1EN, input
// AXI PS Slave HP2: Write Address
.SAXIHP2AWADDR(), // AXI PS Slave HP2 AWADDR[31:0], input
.SAXIHP2AWVALID(), // AXI PS Slave HP2 AWVALID, input
.SAXIHP2AWREADY(), // AXI PS Slave HP2 AWREADY, output
.SAXIHP2AWID(), // AXI PS Slave HP2 AWID[5:0], input
.SAXIHP2AWLOCK(), // AXI PS Slave HP2 AWLOCK[1:0], input
.SAXIHP2AWCACHE(), // AXI PS Slave HP2 AWCACHE[3:0], input
.SAXIHP2AWPROT(), // AXI PS Slave HP2 AWPROT[2:0], input
.SAXIHP2AWLEN(), // AXI PS Slave HP2 AWLEN[3:0], input
.SAXIHP2AWSIZE(), // AXI PS Slave HP2 AWSIZE[1:0], input
.SAXIHP2AWBURST(), // AXI PS Slave HP2 AWBURST[1:0], input
.SAXIHP2AWQOS(), // AXI PS Slave HP2 AWQOS[3:0], input
// AXI PS Slave HP2: Write Data
.SAXIHP2WDATA(), // AXI PS Slave HP2 WDATA[63:0], input
.SAXIHP2WVALID(), // AXI PS Slave HP2 WVALID, input
.SAXIHP2WREADY(), // AXI PS Slave HP2 WREADY, output
.SAXIHP2WID(), // AXI PS Slave HP2 WID[5:0], input
.SAXIHP2WLAST(), // AXI PS Slave HP2 WLAST, input
.SAXIHP2WSTRB(), // AXI PS Slave HP2 WSTRB[7:0], input
.SAXIHP2WCOUNT(), // AXI PS Slave HP2 WCOUNT[7:0], output
.SAXIHP2WACOUNT(), // AXI PS Slave HP2 WACOUNT[5:0], output
.SAXIHP2WRISSUECAP1EN(), // AXI PS Slave HP2 WRISSUECAP1EN, input
// AXI PS Slave HP2: Write response
.SAXIHP2BVALID(), // AXI PS Slave HP2 BVALID, output
.SAXIHP2BREADY(), // AXI PS Slave HP2 BREADY, input
.SAXIHP2BID(), // AXI PS Slave HP2 BID[5:0], output
.SAXIHP2BRESP(), // AXI PS Slave HP2 BRESP[1:0], output
// AXI PS Slave HP3
// AXI PS Slave HP3: Clock, Reset
.SAXIHP3ACLK (hclk), // AXI PS Slave HP3 Clock , input
.SAXIHP3ARESETN(), // AXI PS Slave HP3 Reset, output
// AXI PS Slave HP3: Read Address
.SAXIHP3ARADDR (afi3_araddr), // AXI PS Slave HP3 ARADDR[31:0], input
.SAXIHP3ARVALID (afi3_arvalid), // AXI PS Slave HP3 ARVALID, input
.SAXIHP3ARREADY (afi3_arready), // AXI PS Slave HP3 ARREADY, output
.SAXIHP3ARID (afi3_arid), // AXI PS Slave HP3 ARID[5:0], input
.SAXIHP3ARLOCK (afi3_arlock), // AXI PS Slave HP3 ARLOCK[1:0], input
.SAXIHP3ARCACHE (afi3_arcache), // AXI PS Slave HP3 ARCACHE[3:0], input
.SAXIHP3ARPROT (afi3_arprot), // AXI PS Slave HP3 ARPROT[2:0], input
.SAXIHP3ARLEN (afi3_arlen), // AXI PS Slave HP3 ARLEN[3:0], input
.SAXIHP3ARSIZE (afi3_arsize), // AXI PS Slave HP3 ARSIZE[2:0], input
.SAXIHP3ARBURST (afi3_arburst), // AXI PS Slave HP3 ARBURST[1:0], input
.SAXIHP3ARQOS (afi3_arqos), // AXI PS Slave HP3 ARQOS[3:0], input
// AXI PS Slave HP3: Read Data
.SAXIHP3RDATA (afi3_rdata), // AXI PS Slave HP3 RDATA[63:0], output
.SAXIHP3RVALID (afi3_rvalid), // AXI PS Slave HP3 RVALID, output
.SAXIHP3RREADY (afi3_rready), // AXI PS Slave HP3 RREADY, input
.SAXIHP3RID (afi3_rid), // AXI PS Slave HP3 RID[5:0], output
.SAXIHP3RLAST (afi3_rlast), // AXI PS Slave HP3 RLAST, output
.SAXIHP3RRESP (afi3_rresp), // AXI PS Slave HP3 RRESP[1:0], output
.SAXIHP3RCOUNT (afi3_rcount), // AXI PS Slave HP3 RCOUNT[7:0], output
.SAXIHP3RACOUNT (afi3_racount), // AXI PS Slave HP3 RACOUNT[2:0], output
.SAXIHP3RDISSUECAP1EN (afi3_rdissuecap1en), // AXI PS Slave HP3 RDISSUECAP1EN, input
// AXI PS Slave HP3: Write Address
.SAXIHP3AWADDR (afi3_awaddr), // AXI PS Slave HP3 AWADDR[31:0], input
.SAXIHP3AWVALID (afi3_awvalid), // AXI PS Slave HP3 AWVALID, input
.SAXIHP3AWREADY (afi3_awready), // AXI PS Slave HP3 AWREADY, output
.SAXIHP3AWID (afi3_awid), // AXI PS Slave HP3 AWID[5:0], input
.SAXIHP3AWLOCK (afi3_awlock), // AXI PS Slave HP3 AWLOCK[1:0], input
.SAXIHP3AWCACHE (afi3_awcache), // AXI PS Slave HP3 AWCACHE[3:0], input
.SAXIHP3AWPROT (afi3_awprot), // AXI PS Slave HP3 AWPROT[2:0], input
.SAXIHP3AWLEN (afi3_awlen), // AXI PS Slave HP3 AWLEN[3:0], input
.SAXIHP3AWSIZE (afi3_awsize), // AXI PS Slave HP3 AWSIZE[1:0], input
.SAXIHP3AWBURST (afi3_awburst), // AXI PS Slave HP3 AWBURST[1:0], input
.SAXIHP3AWQOS (afi3_awqos), // AXI PS Slave HP3 AWQOS[3:0], input
// AXI PS Slave HP3: Write Data
.SAXIHP3WDATA (afi3_wdata), // AXI PS Slave HP3 WDATA[63:0], input
.SAXIHP3WVALID (afi3_wvalid), // AXI PS Slave HP3 WVALID, input
.SAXIHP3WREADY (afi3_wready), // AXI PS Slave HP3 WREADY, output
.SAXIHP3WID (afi3_wid), // AXI PS Slave HP3 WID[5:0], input
.SAXIHP3WLAST (afi3_wlast), // AXI PS Slave HP3 WLAST, input
.SAXIHP3WSTRB (afi3_wstrb), // AXI PS Slave HP3 WSTRB[7:0], input
.SAXIHP3WCOUNT (afi3_wcount), // AXI PS Slave HP3 WCOUNT[7:0], output
.SAXIHP3WACOUNT (afi3_wacount), // AXI PS Slave HP3 WACOUNT[5:0], output
.SAXIHP3WRISSUECAP1EN (afi3_wrissuecap1en), // AXI PS Slave HP3 WRISSUECAP1EN, input
// AXI PS Slave HP3: Write response
.SAXIHP3BVALID (afi3_bvalid), // AXI PS Slave HP3 BVALID, output
.SAXIHP3BREADY (afi3_bready), // AXI PS Slave HP3 BREADY, input
.SAXIHP3BID (afi3_bid), // AXI PS Slave HP3 BID[5:0], output
.SAXIHP3BRESP (afi3_bresp), // AXI PS Slave HP3 BRESP[1:0], output
// AXI PS Slave ACP
// AXI PS Slave ACP: Clock, Reset
.SAXIACPACLK(), // AXI PS Slave ACP Clock, input
.SAXIACPARESETN(), // AXI PS Slave ACP Reset, output
// AXI PS Slave ACP: Read Address
.SAXIACPARADDR(), // AXI PS Slave ACP ARADDR[31:0], input
.SAXIACPARVALID(), // AXI PS Slave ACP ARVALID, input
.SAXIACPARREADY(), // AXI PS Slave ACP ARREADY, output
.SAXIACPARID(), // AXI PS Slave ACP ARID[2:0], input
.SAXIACPARLOCK(), // AXI PS Slave ACP ARLOCK[1:0], input
.SAXIACPARCACHE(), // AXI PS Slave ACP ARCACHE[3:0], input
.SAXIACPARPROT(), // AXI PS Slave ACP ARPROT[2:0], input
.SAXIACPARLEN(), // AXI PS Slave ACP ARLEN[3:0], input
.SAXIACPARSIZE(), // AXI PS Slave ACP ARSIZE[2:0], input
.SAXIACPARBURST(), // AXI PS Slave ACP ARBURST[1:0], input
.SAXIACPARQOS(), // AXI PS Slave ACP ARQOS[3:0], input
.SAXIACPARUSER(), // AXI PS Slave ACP ARUSER[4:0], input
// AXI PS Slave ACP: Read Data
.SAXIACPRDATA(), // AXI PS Slave ACP RDATA[63:0], output
.SAXIACPRVALID(), // AXI PS Slave ACP RVALID, output
.SAXIACPRREADY(), // AXI PS Slave ACP RREADY, input
.SAXIACPRID(), // AXI PS Slave ACP RID[2:0], output
.SAXIACPRLAST(), // AXI PS Slave ACP RLAST, output
.SAXIACPRRESP(), // AXI PS Slave ACP RRESP[1:0], output
// AXI PS Slave ACP: Write Address
.SAXIACPAWADDR(), // AXI PS Slave ACP AWADDR[31:0], input
.SAXIACPAWVALID(), // AXI PS Slave ACP AWVALID, input
.SAXIACPAWREADY(), // AXI PS Slave ACP AWREADY, output
.SAXIACPAWID(), // AXI PS Slave ACP AWID[2:0], input
.SAXIACPAWLOCK(), // AXI PS Slave ACP AWLOCK[1:0], input
.SAXIACPAWCACHE(), // AXI PS Slave ACP AWCACHE[3:0], input
.SAXIACPAWPROT(), // AXI PS Slave ACP AWPROT[2:0], input
.SAXIACPAWLEN(), // AXI PS Slave ACP AWLEN[3:0], input
.SAXIACPAWSIZE(), // AXI PS Slave ACP AWSIZE[1:0], input
.SAXIACPAWBURST(), // AXI PS Slave ACP AWBURST[1:0], input
.SAXIACPAWQOS(), // AXI PS Slave ACP AWQOS[3:0], input
.SAXIACPAWUSER(), // AXI PS Slave ACP AWUSER[4:0], input
// AXI PS Slave ACP: Write Data
.SAXIACPWDATA(), // AXI PS Slave ACP WDATA[63:0], input
.SAXIACPWVALID(), // AXI PS Slave ACP WVALID, input
.SAXIACPWREADY(), // AXI PS Slave ACP WREADY, output
.SAXIACPWID(), // AXI PS Slave ACP WID[2:0], input
.SAXIACPWLAST(), // AXI PS Slave ACP WLAST, input
.SAXIACPWSTRB(), // AXI PS Slave ACP WSTRB[7:0], input
// AXI PS Slave ACP: Write response
.SAXIACPBVALID(), // AXI PS Slave ACP BVALID, output
.SAXIACPBREADY(), // AXI PS Slave ACP BREADY, input
.SAXIACPBID(), // AXI PS Slave ACP BID[2:0], output
.SAXIACPBRESP(), // AXI PS Slave ACP BRESP[1:0], output
// Direct connection to PS package pads
.DDRA(), // PS DDRA[14:0], inout
.DDRBA(), // PS DDRBA[2:0], inout
.DDRCASB(), // PS DDRCASB, inout
.DDRCKE(), // PS DDRCKE, inout
.DDRCKP(), // PS DDRCKP, inout
.DDRCKN(), // PS DDRCKN, inout
.DDRCSB(), // PS DDRCSB, inout
.DDRDM(), // PS DDRDM[3:0], inout
.DDRDQ(), // PS DDRDQ[31:0], inout
.DDRDQSP(), // PS DDRDQSP[3:0], inout
.DDRDQSN(), // PS DDRDQSN[3:0], inout
.DDRDRSTB(), // PS DDRDRSTB, inout
.DDRODT(), // PS DDRODT, inout
.DDRRASB(), // PS DDRRASB, inout
.DDRVRN(), // PS DDRVRN, inout
.DDRVRP(), // PS DDRVRP, inout
.DDRWEB(), // PS DDRWEB, inout
.MIO(), // PS MIO[53:0], inout // clg225 has less
.PSCLK(), // PS PSCLK, inout
.PSPORB(), // PS PSPORB, inout
.PSSRSTB() // PS PSSRSTB, inout
);
endmodule
|
module accumulator_processor (clk, reset, op, signal, read, write, req, grant, state);
input clk, reset, signal, grant;
input [1:0] op;
input [31:0] read;
output [31:0] write;
output req;
output [6:0] state;
reg req = 0;
reg [6:0] state;
reg [1:0] op_internal;
reg [31:0] A;
reg [31:0] B;
reg [31:0] result;
integer slowdown = 0;
integer seed = 8882371;
localparam
NOP = 2'b00, // No operation
FETCH = 2'b01, // Fetch an operand from the memory
SEND = 2'b10; // Send a result to the memory
localparam
REQ1 = 7'b0000001, // Request 1 state - requests the bus to receive A
RECA = 7'b0000010, // Receive A state - receives A from the bus
REQ2 = 7'b0000100, // Request 2 state - requests the bus to receive B
RECB = 7'b0001000, // Receive B state - receives B from the bus
ADD = 7'b0010000, // Add state - adds A and B
REQ3 = 7'b0100000, // Request 3 state - requests the bus to send the result
RSLT = 7'b1000000; // Result state - sends the result over the bus
assign op = (op_internal == FETCH || op_internal == SEND) ? op_internal : 2'bz;
assign write = (state == RSLT) ? result : 32'bz;
reg [4*8:1] state_string;
always @(*)
begin
case (state)
7'b0000001: state_string = "REQ1";
7'b0000010: state_string = "RECA";
7'b0000100: state_string = "REQ2";
7'b0001000: state_string = "RECB";
7'b0010000: state_string = "ADD ";
7'b0100000: state_string = "REQ3";
7'b1000000: state_string = "RSLT";
default: state_string = "UNKN";
endcase
end
always @(posedge clk, posedge reset)
begin
if (reset) begin
state <= REQ1;
op_internal <= NOP;
end
else begin
case (state)
REQ1:
begin
req <= 1'b1;
if (grant && !signal) begin
state <= RECA;
end
end
RECA:
begin
op_internal <= FETCH;
A <= read;
if (signal) begin
op_internal <= NOP;
req <= 1'b0;
state <= REQ2;
end
end
REQ2:
begin
req <= 1'b1;
if (grant && !signal) begin
state <= RECB;
end
end
RECB:
begin
op_internal <= FETCH;
B <= read;
if (signal) begin
op_internal <= NOP;
req <= 1'b0;
state <= ADD;
// Set the slowdown here
slowdown <= 1000 + ({$random(seed)} % 9000);
end
end
ADD:
begin
result <= A + B;
if (slowdown != 0) begin
slowdown <= slowdown - 1;
end
else begin
state <= REQ3;
end
end
REQ3:
begin
req <= 1'b1;
if (grant && !signal) begin
state <= RSLT;
end
end
RSLT:
begin
op_internal <= SEND;
if (signal) begin
op_internal <= NOP;
req <= 1'b0;
state <= REQ1;
end
end
endcase
end
end
endmodule
|
module soc_system_jtag_uart_sim_scfifo_w (
// inputs:
clk,
fifo_wdata,
fifo_wr,
// outputs:
fifo_FF,
r_dat,
wfifo_empty,
wfifo_used
)
;
output fifo_FF;
output [ 7: 0] r_dat;
output wfifo_empty;
output [ 5: 0] wfifo_used;
input clk;
input [ 7: 0] fifo_wdata;
input fifo_wr;
wire fifo_FF;
wire [ 7: 0] r_dat;
wire wfifo_empty;
wire [ 5: 0] wfifo_used;
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
always @(posedge clk)
begin
if (fifo_wr)
$write("%c", fifo_wdata);
end
assign wfifo_used = {6{1'b0}};
assign r_dat = {8{1'b0}};
assign fifo_FF = 1'b0;
assign wfifo_empty = 1'b1;
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
endmodule
|
module soc_system_jtag_uart_scfifo_w (
// inputs:
clk,
fifo_clear,
fifo_wdata,
fifo_wr,
rd_wfifo,
// outputs:
fifo_FF,
r_dat,
wfifo_empty,
wfifo_used
)
;
output fifo_FF;
output [ 7: 0] r_dat;
output wfifo_empty;
output [ 5: 0] wfifo_used;
input clk;
input fifo_clear;
input [ 7: 0] fifo_wdata;
input fifo_wr;
input rd_wfifo;
wire fifo_FF;
wire [ 7: 0] r_dat;
wire wfifo_empty;
wire [ 5: 0] wfifo_used;
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
soc_system_jtag_uart_sim_scfifo_w the_soc_system_jtag_uart_sim_scfifo_w
(
.clk (clk),
.fifo_FF (fifo_FF),
.fifo_wdata (fifo_wdata),
.fifo_wr (fifo_wr),
.r_dat (r_dat),
.wfifo_empty (wfifo_empty),
.wfifo_used (wfifo_used)
);
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
//synthesis read_comments_as_HDL on
// scfifo wfifo
// (
// .aclr (fifo_clear),
// .clock (clk),
// .data (fifo_wdata),
// .empty (wfifo_empty),
// .full (fifo_FF),
// .q (r_dat),
// .rdreq (rd_wfifo),
// .usedw (wfifo_used),
// .wrreq (fifo_wr)
// );
//
// defparam wfifo.lpm_hint = "RAM_BLOCK_TYPE=AUTO",
// wfifo.lpm_numwords = 64,
// wfifo.lpm_showahead = "OFF",
// wfifo.lpm_type = "scfifo",
// wfifo.lpm_width = 8,
// wfifo.lpm_widthu = 6,
// wfifo.overflow_checking = "OFF",
// wfifo.underflow_checking = "OFF",
// wfifo.use_eab = "ON";
//
//synthesis read_comments_as_HDL off
endmodule
|
module soc_system_jtag_uart_sim_scfifo_r (
// inputs:
clk,
fifo_rd,
rst_n,
// outputs:
fifo_EF,
fifo_rdata,
rfifo_full,
rfifo_used
)
;
output fifo_EF;
output [ 7: 0] fifo_rdata;
output rfifo_full;
output [ 5: 0] rfifo_used;
input clk;
input fifo_rd;
input rst_n;
reg [ 31: 0] bytes_left;
wire fifo_EF;
reg fifo_rd_d;
wire [ 7: 0] fifo_rdata;
wire new_rom;
wire [ 31: 0] num_bytes;
wire [ 6: 0] rfifo_entries;
wire rfifo_full;
wire [ 5: 0] rfifo_used;
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
// Generate rfifo_entries for simulation
always @(posedge clk or negedge rst_n)
begin
if (rst_n == 0)
begin
bytes_left <= 32'h0;
fifo_rd_d <= 1'b0;
end
else
begin
fifo_rd_d <= fifo_rd;
// decrement on read
if (fifo_rd_d)
bytes_left <= bytes_left - 1'b1;
// catch new contents
if (new_rom)
bytes_left <= num_bytes;
end
end
assign fifo_EF = bytes_left == 32'b0;
assign rfifo_full = bytes_left > 7'h40;
assign rfifo_entries = (rfifo_full) ? 7'h40 : bytes_left;
assign rfifo_used = rfifo_entries[5 : 0];
assign new_rom = 1'b0;
assign num_bytes = 32'b0;
assign fifo_rdata = 8'b0;
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
endmodule
|
module soc_system_jtag_uart_scfifo_r (
// inputs:
clk,
fifo_clear,
fifo_rd,
rst_n,
t_dat,
wr_rfifo,
// outputs:
fifo_EF,
fifo_rdata,
rfifo_full,
rfifo_used
)
;
output fifo_EF;
output [ 7: 0] fifo_rdata;
output rfifo_full;
output [ 5: 0] rfifo_used;
input clk;
input fifo_clear;
input fifo_rd;
input rst_n;
input [ 7: 0] t_dat;
input wr_rfifo;
wire fifo_EF;
wire [ 7: 0] fifo_rdata;
wire rfifo_full;
wire [ 5: 0] rfifo_used;
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
soc_system_jtag_uart_sim_scfifo_r the_soc_system_jtag_uart_sim_scfifo_r
(
.clk (clk),
.fifo_EF (fifo_EF),
.fifo_rd (fifo_rd),
.fifo_rdata (fifo_rdata),
.rfifo_full (rfifo_full),
.rfifo_used (rfifo_used),
.rst_n (rst_n)
);
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
//synthesis read_comments_as_HDL on
// scfifo rfifo
// (
// .aclr (fifo_clear),
// .clock (clk),
// .data (t_dat),
// .empty (fifo_EF),
// .full (rfifo_full),
// .q (fifo_rdata),
// .rdreq (fifo_rd),
// .usedw (rfifo_used),
// .wrreq (wr_rfifo)
// );
//
// defparam rfifo.lpm_hint = "RAM_BLOCK_TYPE=AUTO",
// rfifo.lpm_numwords = 64,
// rfifo.lpm_showahead = "OFF",
// rfifo.lpm_type = "scfifo",
// rfifo.lpm_width = 8,
// rfifo.lpm_widthu = 6,
// rfifo.overflow_checking = "OFF",
// rfifo.underflow_checking = "OFF",
// rfifo.use_eab = "ON";
//
//synthesis read_comments_as_HDL off
endmodule
|
module soc_system_jtag_uart (
// inputs:
av_address,
av_chipselect,
av_read_n,
av_write_n,
av_writedata,
clk,
rst_n,
// outputs:
av_irq,
av_readdata,
av_waitrequest,
dataavailable,
readyfordata
)
/* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"R101,C106,D101,D103\"" */ ;
output av_irq;
output [ 31: 0] av_readdata;
output av_waitrequest;
output dataavailable;
output readyfordata;
input av_address;
input av_chipselect;
input av_read_n;
input av_write_n;
input [ 31: 0] av_writedata;
input clk;
input rst_n;
reg ac;
wire activity;
wire av_irq;
wire [ 31: 0] av_readdata;
reg av_waitrequest;
reg dataavailable;
reg fifo_AE;
reg fifo_AF;
wire fifo_EF;
wire fifo_FF;
wire fifo_clear;
wire fifo_rd;
wire [ 7: 0] fifo_rdata;
wire [ 7: 0] fifo_wdata;
reg fifo_wr;
reg ien_AE;
reg ien_AF;
wire ipen_AE;
wire ipen_AF;
reg pause_irq;
wire [ 7: 0] r_dat;
wire r_ena;
reg r_val;
wire rd_wfifo;
reg read_0;
reg readyfordata;
wire rfifo_full;
wire [ 5: 0] rfifo_used;
reg rvalid;
reg sim_r_ena;
reg sim_t_dat;
reg sim_t_ena;
reg sim_t_pause;
wire [ 7: 0] t_dat;
reg t_dav;
wire t_ena;
wire t_pause;
wire wfifo_empty;
wire [ 5: 0] wfifo_used;
reg woverflow;
wire wr_rfifo;
//avalon_jtag_slave, which is an e_avalon_slave
assign rd_wfifo = r_ena & ~wfifo_empty;
assign wr_rfifo = t_ena & ~rfifo_full;
assign fifo_clear = ~rst_n;
soc_system_jtag_uart_scfifo_w the_soc_system_jtag_uart_scfifo_w
(
.clk (clk),
.fifo_FF (fifo_FF),
.fifo_clear (fifo_clear),
.fifo_wdata (fifo_wdata),
.fifo_wr (fifo_wr),
.r_dat (r_dat),
.rd_wfifo (rd_wfifo),
.wfifo_empty (wfifo_empty),
.wfifo_used (wfifo_used)
);
soc_system_jtag_uart_scfifo_r the_soc_system_jtag_uart_scfifo_r
(
.clk (clk),
.fifo_EF (fifo_EF),
.fifo_clear (fifo_clear),
.fifo_rd (fifo_rd),
.fifo_rdata (fifo_rdata),
.rfifo_full (rfifo_full),
.rfifo_used (rfifo_used),
.rst_n (rst_n),
.t_dat (t_dat),
.wr_rfifo (wr_rfifo)
);
assign ipen_AE = ien_AE & fifo_AE;
assign ipen_AF = ien_AF & (pause_irq | fifo_AF);
assign av_irq = ipen_AE | ipen_AF;
assign activity = t_pause | t_ena;
always @(posedge clk or negedge rst_n)
begin
if (rst_n == 0)
pause_irq <= 1'b0;
else // only if fifo is not empty...
if (t_pause & ~fifo_EF)
pause_irq <= 1'b1;
else if (read_0)
pause_irq <= 1'b0;
end
always @(posedge clk or negedge rst_n)
begin
if (rst_n == 0)
begin
r_val <= 1'b0;
t_dav <= 1'b1;
end
else
begin
r_val <= r_ena & ~wfifo_empty;
t_dav <= ~rfifo_full;
end
end
always @(posedge clk or negedge rst_n)
begin
if (rst_n == 0)
begin
fifo_AE <= 1'b0;
fifo_AF <= 1'b0;
fifo_wr <= 1'b0;
rvalid <= 1'b0;
read_0 <= 1'b0;
ien_AE <= 1'b0;
ien_AF <= 1'b0;
ac <= 1'b0;
woverflow <= 1'b0;
av_waitrequest <= 1'b1;
end
else
begin
fifo_AE <= {fifo_FF,wfifo_used} <= 8;
fifo_AF <= (7'h40 - {rfifo_full,rfifo_used}) <= 8;
fifo_wr <= 1'b0;
read_0 <= 1'b0;
av_waitrequest <= ~(av_chipselect & (~av_write_n | ~av_read_n) & av_waitrequest);
if (activity)
ac <= 1'b1;
// write
if (av_chipselect & ~av_write_n & av_waitrequest)
// addr 1 is control; addr 0 is data
if (av_address)
begin
ien_AF <= av_writedata[0];
ien_AE <= av_writedata[1];
if (av_writedata[10] & ~activity)
ac <= 1'b0;
end
else
begin
fifo_wr <= ~fifo_FF;
woverflow <= fifo_FF;
end
// read
if (av_chipselect & ~av_read_n & av_waitrequest)
begin
// addr 1 is interrupt; addr 0 is data
if (~av_address)
rvalid <= ~fifo_EF;
read_0 <= ~av_address;
end
end
end
assign fifo_wdata = av_writedata[7 : 0];
assign fifo_rd = (av_chipselect & ~av_read_n & av_waitrequest & ~av_address) ? ~fifo_EF : 1'b0;
assign av_readdata = read_0 ? { {9{1'b0}},rfifo_full,rfifo_used,rvalid,woverflow,~fifo_FF,~fifo_EF,1'b0,ac,ipen_AE,ipen_AF,fifo_rdata } : { {9{1'b0}},(7'h40 - {fifo_FF,wfifo_used}),rvalid,woverflow,~fifo_FF,~fifo_EF,1'b0,ac,ipen_AE,ipen_AF,{6{1'b0}},ien_AE,ien_AF };
always @(posedge clk or negedge rst_n)
begin
if (rst_n == 0)
readyfordata <= 0;
else
readyfordata <= ~fifo_FF;
end
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
// Tie off Atlantic Interface signals not used for simulation
always @(posedge clk)
begin
sim_t_pause <= 1'b0;
sim_t_ena <= 1'b0;
sim_t_dat <= t_dav ? r_dat : {8{r_val}};
sim_r_ena <= 1'b0;
end
assign r_ena = sim_r_ena;
assign t_ena = sim_t_ena;
assign t_dat = sim_t_dat;
assign t_pause = sim_t_pause;
always @(fifo_EF)
begin
dataavailable = ~fifo_EF;
end
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
//synthesis read_comments_as_HDL on
// alt_jtag_atlantic soc_system_jtag_uart_alt_jtag_atlantic
// (
// .clk (clk),
// .r_dat (r_dat),
// .r_ena (r_ena),
// .r_val (r_val),
// .rst_n (rst_n),
// .t_dat (t_dat),
// .t_dav (t_dav),
// .t_ena (t_ena),
// .t_pause (t_pause)
// );
//
// defparam soc_system_jtag_uart_alt_jtag_atlantic.INSTANCE_ID = 0,
// soc_system_jtag_uart_alt_jtag_atlantic.LOG2_RXFIFO_DEPTH = 6,
// soc_system_jtag_uart_alt_jtag_atlantic.LOG2_TXFIFO_DEPTH = 6,
// soc_system_jtag_uart_alt_jtag_atlantic.SLD_AUTO_INSTANCE_INDEX = "YES";
//
// always @(posedge clk or negedge rst_n)
// begin
// if (rst_n == 0)
// dataavailable <= 0;
// else
// dataavailable <= ~fifo_EF;
// end
//
//
//synthesis read_comments_as_HDL off
endmodule
|
module sky130_fd_sc_ls__sedfxtp (
Q ,
CLK,
D ,
DE ,
SCD,
SCE
);
output Q ;
input CLK;
input D ;
input DE ;
input SCD;
input SCE;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
|
module ringbuffer #(parameter AW = 8, DW = 48)
(
input reset,
input clock,
input read_clock_enable,
input write_clock_enable,
output [DW-1:0] read_data,
input [DW-1:0] write_data,
output reg empty,
output reg overflow);
reg [AW-1:0] next_write_addr;
reg [AW-1:0] read_addr;
reg [AW-1:0] write_addr;
wire mem_read_clock_enable;
wire mem_write_clock_enable;
assign empty = read_addr == write_addr;
assign overflow = next_write_addr == read_addr;
always @(negedge reset or negedge clock) begin
if (~reset) begin
write_addr <= 0;
next_write_addr <= 1;
end
else
if (write_clock_enable)
if (~overflow) begin
write_addr <= write_addr + 1;
next_write_addr <= next_write_addr + 1;
end
end
always @(negedge reset or negedge clock) begin
if (~reset) begin
read_addr <= 0;
end
else begin
if (read_clock_enable)
if (~empty)
read_addr <= read_addr + 1;
end
end
assign mem_read_clock_enable = ~empty & read_clock_enable;
assign mem_write_clock_enable = ~overflow & write_clock_enable;
buffer #(.AW(AW), .DW(DW))
MEM (
.clock(clock),
.write_clock_enable(mem_write_clock_enable),
.write_data(write_data),
.write_addr(write_addr),
.read_clock_enable(mem_read_clock_enable),
.read_data(read_data),
.read_addr(read_addr));
endmodule
|
module soc_system_mm_interconnect_1 (
input wire [11:0] hps_0_h2f_lw_axi_master_awid, // hps_0_h2f_lw_axi_master.awid
input wire [20:0] hps_0_h2f_lw_axi_master_awaddr, // .awaddr
input wire [3:0] hps_0_h2f_lw_axi_master_awlen, // .awlen
input wire [2:0] hps_0_h2f_lw_axi_master_awsize, // .awsize
input wire [1:0] hps_0_h2f_lw_axi_master_awburst, // .awburst
input wire [1:0] hps_0_h2f_lw_axi_master_awlock, // .awlock
input wire [3:0] hps_0_h2f_lw_axi_master_awcache, // .awcache
input wire [2:0] hps_0_h2f_lw_axi_master_awprot, // .awprot
input wire hps_0_h2f_lw_axi_master_awvalid, // .awvalid
output wire hps_0_h2f_lw_axi_master_awready, // .awready
input wire [11:0] hps_0_h2f_lw_axi_master_wid, // .wid
input wire [31:0] hps_0_h2f_lw_axi_master_wdata, // .wdata
input wire [3:0] hps_0_h2f_lw_axi_master_wstrb, // .wstrb
input wire hps_0_h2f_lw_axi_master_wlast, // .wlast
input wire hps_0_h2f_lw_axi_master_wvalid, // .wvalid
output wire hps_0_h2f_lw_axi_master_wready, // .wready
output wire [11:0] hps_0_h2f_lw_axi_master_bid, // .bid
output wire [1:0] hps_0_h2f_lw_axi_master_bresp, // .bresp
output wire hps_0_h2f_lw_axi_master_bvalid, // .bvalid
input wire hps_0_h2f_lw_axi_master_bready, // .bready
input wire [11:0] hps_0_h2f_lw_axi_master_arid, // .arid
input wire [20:0] hps_0_h2f_lw_axi_master_araddr, // .araddr
input wire [3:0] hps_0_h2f_lw_axi_master_arlen, // .arlen
input wire [2:0] hps_0_h2f_lw_axi_master_arsize, // .arsize
input wire [1:0] hps_0_h2f_lw_axi_master_arburst, // .arburst
input wire [1:0] hps_0_h2f_lw_axi_master_arlock, // .arlock
input wire [3:0] hps_0_h2f_lw_axi_master_arcache, // .arcache
input wire [2:0] hps_0_h2f_lw_axi_master_arprot, // .arprot
input wire hps_0_h2f_lw_axi_master_arvalid, // .arvalid
output wire hps_0_h2f_lw_axi_master_arready, // .arready
output wire [11:0] hps_0_h2f_lw_axi_master_rid, // .rid
output wire [31:0] hps_0_h2f_lw_axi_master_rdata, // .rdata
output wire [1:0] hps_0_h2f_lw_axi_master_rresp, // .rresp
output wire hps_0_h2f_lw_axi_master_rlast, // .rlast
output wire hps_0_h2f_lw_axi_master_rvalid, // .rvalid
input wire hps_0_h2f_lw_axi_master_rready, // .rready
input wire clk_0_clk_clk, // clk_0_clk.clk
input wire clk_stream_clk_clk, // clk_stream_clk.clk
input wire alt_vip_vfr_vga_clock_reset_reset_reset_bridge_in_reset_reset, // alt_vip_vfr_vga_clock_reset_reset_reset_bridge_in_reset.reset
input wire ece453_0_clock_reset_reset_bridge_in_reset_reset, // ece453_0_clock_reset_reset_bridge_in_reset.reset
input wire hps_0_h2f_lw_axi_master_agent_clk_reset_reset_bridge_in_reset_reset, // hps_0_h2f_lw_axi_master_agent_clk_reset_reset_bridge_in_reset.reset
input wire jtag_uart_reset_reset_bridge_in_reset_reset, // jtag_uart_reset_reset_bridge_in_reset.reset
input wire master_non_sec_clk_reset_reset_bridge_in_reset_reset, // master_non_sec_clk_reset_reset_bridge_in_reset.reset
input wire [31:0] master_non_sec_master_address, // master_non_sec_master.address
output wire master_non_sec_master_waitrequest, // .waitrequest
input wire [3:0] master_non_sec_master_byteenable, // .byteenable
input wire master_non_sec_master_read, // .read
output wire [31:0] master_non_sec_master_readdata, // .readdata
output wire master_non_sec_master_readdatavalid, // .readdatavalid
input wire master_non_sec_master_write, // .write
input wire [31:0] master_non_sec_master_writedata, // .writedata
output wire [4:0] alt_vip_vfr_vga_avalon_slave_address, // alt_vip_vfr_vga_avalon_slave.address
output wire alt_vip_vfr_vga_avalon_slave_write, // .write
output wire alt_vip_vfr_vga_avalon_slave_read, // .read
input wire [31:0] alt_vip_vfr_vga_avalon_slave_readdata, // .readdata
output wire [31:0] alt_vip_vfr_vga_avalon_slave_writedata, // .writedata
output wire [3:0] ece453_0_avalon_slave_0_address, // ece453_0_avalon_slave_0.address
output wire ece453_0_avalon_slave_0_write, // .write
output wire ece453_0_avalon_slave_0_read, // .read
input wire [31:0] ece453_0_avalon_slave_0_readdata, // .readdata
output wire [31:0] ece453_0_avalon_slave_0_writedata, // .writedata
output wire [3:0] ece453_0_avalon_slave_0_byteenable, // .byteenable
output wire [0:0] intr_capturer_0_avalon_slave_0_address, // intr_capturer_0_avalon_slave_0.address
output wire intr_capturer_0_avalon_slave_0_read, // .read
input wire [31:0] intr_capturer_0_avalon_slave_0_readdata, // .readdata
output wire [0:0] jtag_uart_avalon_jtag_slave_address, // jtag_uart_avalon_jtag_slave.address
output wire jtag_uart_avalon_jtag_slave_write, // .write
output wire jtag_uart_avalon_jtag_slave_read, // .read
input wire [31:0] jtag_uart_avalon_jtag_slave_readdata, // .readdata
output wire [31:0] jtag_uart_avalon_jtag_slave_writedata, // .writedata
input wire jtag_uart_avalon_jtag_slave_waitrequest, // .waitrequest
output wire jtag_uart_avalon_jtag_slave_chipselect, // .chipselect
output wire [0:0] sysid_qsys_control_slave_address, // sysid_qsys_control_slave.address
input wire [31:0] sysid_qsys_control_slave_readdata // .readdata
);
wire master_non_sec_master_translator_avalon_universal_master_0_waitrequest; // master_non_sec_master_agent:av_waitrequest -> master_non_sec_master_translator:uav_waitrequest
wire [31:0] master_non_sec_master_translator_avalon_universal_master_0_readdata; // master_non_sec_master_agent:av_readdata -> master_non_sec_master_translator:uav_readdata
wire master_non_sec_master_translator_avalon_universal_master_0_debugaccess; // master_non_sec_master_translator:uav_debugaccess -> master_non_sec_master_agent:av_debugaccess
wire [31:0] master_non_sec_master_translator_avalon_universal_master_0_address; // master_non_sec_master_translator:uav_address -> master_non_sec_master_agent:av_address
wire master_non_sec_master_translator_avalon_universal_master_0_read; // master_non_sec_master_translator:uav_read -> master_non_sec_master_agent:av_read
wire [3:0] master_non_sec_master_translator_avalon_universal_master_0_byteenable; // master_non_sec_master_translator:uav_byteenable -> master_non_sec_master_agent:av_byteenable
wire master_non_sec_master_translator_avalon_universal_master_0_readdatavalid; // master_non_sec_master_agent:av_readdatavalid -> master_non_sec_master_translator:uav_readdatavalid
wire master_non_sec_master_translator_avalon_universal_master_0_lock; // master_non_sec_master_translator:uav_lock -> master_non_sec_master_agent:av_lock
wire master_non_sec_master_translator_avalon_universal_master_0_write; // master_non_sec_master_translator:uav_write -> master_non_sec_master_agent:av_write
wire [31:0] master_non_sec_master_translator_avalon_universal_master_0_writedata; // master_non_sec_master_translator:uav_writedata -> master_non_sec_master_agent:av_writedata
wire [2:0] master_non_sec_master_translator_avalon_universal_master_0_burstcount; // master_non_sec_master_translator:uav_burstcount -> master_non_sec_master_agent:av_burstcount
wire [31:0] jtag_uart_avalon_jtag_slave_agent_m0_readdata; // jtag_uart_avalon_jtag_slave_translator:uav_readdata -> jtag_uart_avalon_jtag_slave_agent:m0_readdata
wire jtag_uart_avalon_jtag_slave_agent_m0_waitrequest; // jtag_uart_avalon_jtag_slave_translator:uav_waitrequest -> jtag_uart_avalon_jtag_slave_agent:m0_waitrequest
wire jtag_uart_avalon_jtag_slave_agent_m0_debugaccess; // jtag_uart_avalon_jtag_slave_agent:m0_debugaccess -> jtag_uart_avalon_jtag_slave_translator:uav_debugaccess
wire [31:0] jtag_uart_avalon_jtag_slave_agent_m0_address; // jtag_uart_avalon_jtag_slave_agent:m0_address -> jtag_uart_avalon_jtag_slave_translator:uav_address
wire [3:0] jtag_uart_avalon_jtag_slave_agent_m0_byteenable; // jtag_uart_avalon_jtag_slave_agent:m0_byteenable -> jtag_uart_avalon_jtag_slave_translator:uav_byteenable
wire jtag_uart_avalon_jtag_slave_agent_m0_read; // jtag_uart_avalon_jtag_slave_agent:m0_read -> jtag_uart_avalon_jtag_slave_translator:uav_read
wire jtag_uart_avalon_jtag_slave_agent_m0_readdatavalid; // jtag_uart_avalon_jtag_slave_translator:uav_readdatavalid -> jtag_uart_avalon_jtag_slave_agent:m0_readdatavalid
wire jtag_uart_avalon_jtag_slave_agent_m0_lock; // jtag_uart_avalon_jtag_slave_agent:m0_lock -> jtag_uart_avalon_jtag_slave_translator:uav_lock
wire [31:0] jtag_uart_avalon_jtag_slave_agent_m0_writedata; // jtag_uart_avalon_jtag_slave_agent:m0_writedata -> jtag_uart_avalon_jtag_slave_translator:uav_writedata
wire jtag_uart_avalon_jtag_slave_agent_m0_write; // jtag_uart_avalon_jtag_slave_agent:m0_write -> jtag_uart_avalon_jtag_slave_translator:uav_write
wire [2:0] jtag_uart_avalon_jtag_slave_agent_m0_burstcount; // jtag_uart_avalon_jtag_slave_agent:m0_burstcount -> jtag_uart_avalon_jtag_slave_translator:uav_burstcount
wire jtag_uart_avalon_jtag_slave_agent_rf_source_valid; // jtag_uart_avalon_jtag_slave_agent:rf_source_valid -> jtag_uart_avalon_jtag_slave_agent_rsp_fifo:in_valid
wire [127:0] jtag_uart_avalon_jtag_slave_agent_rf_source_data; // jtag_uart_avalon_jtag_slave_agent:rf_source_data -> jtag_uart_avalon_jtag_slave_agent_rsp_fifo:in_data
wire jtag_uart_avalon_jtag_slave_agent_rf_source_ready; // jtag_uart_avalon_jtag_slave_agent_rsp_fifo:in_ready -> jtag_uart_avalon_jtag_slave_agent:rf_source_ready
wire jtag_uart_avalon_jtag_slave_agent_rf_source_startofpacket; // jtag_uart_avalon_jtag_slave_agent:rf_source_startofpacket -> jtag_uart_avalon_jtag_slave_agent_rsp_fifo:in_startofpacket
wire jtag_uart_avalon_jtag_slave_agent_rf_source_endofpacket; // jtag_uart_avalon_jtag_slave_agent:rf_source_endofpacket -> jtag_uart_avalon_jtag_slave_agent_rsp_fifo:in_endofpacket
wire jtag_uart_avalon_jtag_slave_agent_rsp_fifo_out_valid; // jtag_uart_avalon_jtag_slave_agent_rsp_fifo:out_valid -> jtag_uart_avalon_jtag_slave_agent:rf_sink_valid
wire [127:0] jtag_uart_avalon_jtag_slave_agent_rsp_fifo_out_data; // jtag_uart_avalon_jtag_slave_agent_rsp_fifo:out_data -> jtag_uart_avalon_jtag_slave_agent:rf_sink_data
wire jtag_uart_avalon_jtag_slave_agent_rsp_fifo_out_ready; // jtag_uart_avalon_jtag_slave_agent:rf_sink_ready -> jtag_uart_avalon_jtag_slave_agent_rsp_fifo:out_ready
wire jtag_uart_avalon_jtag_slave_agent_rsp_fifo_out_startofpacket; // jtag_uart_avalon_jtag_slave_agent_rsp_fifo:out_startofpacket -> jtag_uart_avalon_jtag_slave_agent:rf_sink_startofpacket
wire jtag_uart_avalon_jtag_slave_agent_rsp_fifo_out_endofpacket; // jtag_uart_avalon_jtag_slave_agent_rsp_fifo:out_endofpacket -> jtag_uart_avalon_jtag_slave_agent:rf_sink_endofpacket
wire jtag_uart_avalon_jtag_slave_agent_rdata_fifo_src_valid; // jtag_uart_avalon_jtag_slave_agent:rdata_fifo_src_valid -> jtag_uart_avalon_jtag_slave_agent_rdata_fifo:in_valid
wire [33:0] jtag_uart_avalon_jtag_slave_agent_rdata_fifo_src_data; // jtag_uart_avalon_jtag_slave_agent:rdata_fifo_src_data -> jtag_uart_avalon_jtag_slave_agent_rdata_fifo:in_data
wire jtag_uart_avalon_jtag_slave_agent_rdata_fifo_src_ready; // jtag_uart_avalon_jtag_slave_agent_rdata_fifo:in_ready -> jtag_uart_avalon_jtag_slave_agent:rdata_fifo_src_ready
wire [31:0] alt_vip_vfr_vga_avalon_slave_agent_m0_readdata; // alt_vip_vfr_vga_avalon_slave_translator:uav_readdata -> alt_vip_vfr_vga_avalon_slave_agent:m0_readdata
wire alt_vip_vfr_vga_avalon_slave_agent_m0_waitrequest; // alt_vip_vfr_vga_avalon_slave_translator:uav_waitrequest -> alt_vip_vfr_vga_avalon_slave_agent:m0_waitrequest
wire alt_vip_vfr_vga_avalon_slave_agent_m0_debugaccess; // alt_vip_vfr_vga_avalon_slave_agent:m0_debugaccess -> alt_vip_vfr_vga_avalon_slave_translator:uav_debugaccess
wire [31:0] alt_vip_vfr_vga_avalon_slave_agent_m0_address; // alt_vip_vfr_vga_avalon_slave_agent:m0_address -> alt_vip_vfr_vga_avalon_slave_translator:uav_address
wire [3:0] alt_vip_vfr_vga_avalon_slave_agent_m0_byteenable; // alt_vip_vfr_vga_avalon_slave_agent:m0_byteenable -> alt_vip_vfr_vga_avalon_slave_translator:uav_byteenable
wire alt_vip_vfr_vga_avalon_slave_agent_m0_read; // alt_vip_vfr_vga_avalon_slave_agent:m0_read -> alt_vip_vfr_vga_avalon_slave_translator:uav_read
wire alt_vip_vfr_vga_avalon_slave_agent_m0_readdatavalid; // alt_vip_vfr_vga_avalon_slave_translator:uav_readdatavalid -> alt_vip_vfr_vga_avalon_slave_agent:m0_readdatavalid
wire alt_vip_vfr_vga_avalon_slave_agent_m0_lock; // alt_vip_vfr_vga_avalon_slave_agent:m0_lock -> alt_vip_vfr_vga_avalon_slave_translator:uav_lock
wire [31:0] alt_vip_vfr_vga_avalon_slave_agent_m0_writedata; // alt_vip_vfr_vga_avalon_slave_agent:m0_writedata -> alt_vip_vfr_vga_avalon_slave_translator:uav_writedata
wire alt_vip_vfr_vga_avalon_slave_agent_m0_write; // alt_vip_vfr_vga_avalon_slave_agent:m0_write -> alt_vip_vfr_vga_avalon_slave_translator:uav_write
wire [2:0] alt_vip_vfr_vga_avalon_slave_agent_m0_burstcount; // alt_vip_vfr_vga_avalon_slave_agent:m0_burstcount -> alt_vip_vfr_vga_avalon_slave_translator:uav_burstcount
wire alt_vip_vfr_vga_avalon_slave_agent_rf_source_valid; // alt_vip_vfr_vga_avalon_slave_agent:rf_source_valid -> alt_vip_vfr_vga_avalon_slave_agent_rsp_fifo:in_valid
wire [127:0] alt_vip_vfr_vga_avalon_slave_agent_rf_source_data; // alt_vip_vfr_vga_avalon_slave_agent:rf_source_data -> alt_vip_vfr_vga_avalon_slave_agent_rsp_fifo:in_data
wire alt_vip_vfr_vga_avalon_slave_agent_rf_source_ready; // alt_vip_vfr_vga_avalon_slave_agent_rsp_fifo:in_ready -> alt_vip_vfr_vga_avalon_slave_agent:rf_source_ready
wire alt_vip_vfr_vga_avalon_slave_agent_rf_source_startofpacket; // alt_vip_vfr_vga_avalon_slave_agent:rf_source_startofpacket -> alt_vip_vfr_vga_avalon_slave_agent_rsp_fifo:in_startofpacket
wire alt_vip_vfr_vga_avalon_slave_agent_rf_source_endofpacket; // alt_vip_vfr_vga_avalon_slave_agent:rf_source_endofpacket -> alt_vip_vfr_vga_avalon_slave_agent_rsp_fifo:in_endofpacket
wire alt_vip_vfr_vga_avalon_slave_agent_rsp_fifo_out_valid; // alt_vip_vfr_vga_avalon_slave_agent_rsp_fifo:out_valid -> alt_vip_vfr_vga_avalon_slave_agent:rf_sink_valid
wire [127:0] alt_vip_vfr_vga_avalon_slave_agent_rsp_fifo_out_data; // alt_vip_vfr_vga_avalon_slave_agent_rsp_fifo:out_data -> alt_vip_vfr_vga_avalon_slave_agent:rf_sink_data
wire alt_vip_vfr_vga_avalon_slave_agent_rsp_fifo_out_ready; // alt_vip_vfr_vga_avalon_slave_agent:rf_sink_ready -> alt_vip_vfr_vga_avalon_slave_agent_rsp_fifo:out_ready
wire alt_vip_vfr_vga_avalon_slave_agent_rsp_fifo_out_startofpacket; // alt_vip_vfr_vga_avalon_slave_agent_rsp_fifo:out_startofpacket -> alt_vip_vfr_vga_avalon_slave_agent:rf_sink_startofpacket
wire alt_vip_vfr_vga_avalon_slave_agent_rsp_fifo_out_endofpacket; // alt_vip_vfr_vga_avalon_slave_agent_rsp_fifo:out_endofpacket -> alt_vip_vfr_vga_avalon_slave_agent:rf_sink_endofpacket
wire alt_vip_vfr_vga_avalon_slave_agent_rdata_fifo_src_valid; // alt_vip_vfr_vga_avalon_slave_agent:rdata_fifo_src_valid -> alt_vip_vfr_vga_avalon_slave_agent_rdata_fifo:in_valid
wire [33:0] alt_vip_vfr_vga_avalon_slave_agent_rdata_fifo_src_data; // alt_vip_vfr_vga_avalon_slave_agent:rdata_fifo_src_data -> alt_vip_vfr_vga_avalon_slave_agent_rdata_fifo:in_data
wire alt_vip_vfr_vga_avalon_slave_agent_rdata_fifo_src_ready; // alt_vip_vfr_vga_avalon_slave_agent_rdata_fifo:in_ready -> alt_vip_vfr_vga_avalon_slave_agent:rdata_fifo_src_ready
wire [31:0] ece453_0_avalon_slave_0_agent_m0_readdata; // ece453_0_avalon_slave_0_translator:uav_readdata -> ece453_0_avalon_slave_0_agent:m0_readdata
wire ece453_0_avalon_slave_0_agent_m0_waitrequest; // ece453_0_avalon_slave_0_translator:uav_waitrequest -> ece453_0_avalon_slave_0_agent:m0_waitrequest
wire ece453_0_avalon_slave_0_agent_m0_debugaccess; // ece453_0_avalon_slave_0_agent:m0_debugaccess -> ece453_0_avalon_slave_0_translator:uav_debugaccess
wire [31:0] ece453_0_avalon_slave_0_agent_m0_address; // ece453_0_avalon_slave_0_agent:m0_address -> ece453_0_avalon_slave_0_translator:uav_address
wire [3:0] ece453_0_avalon_slave_0_agent_m0_byteenable; // ece453_0_avalon_slave_0_agent:m0_byteenable -> ece453_0_avalon_slave_0_translator:uav_byteenable
wire ece453_0_avalon_slave_0_agent_m0_read; // ece453_0_avalon_slave_0_agent:m0_read -> ece453_0_avalon_slave_0_translator:uav_read
wire ece453_0_avalon_slave_0_agent_m0_readdatavalid; // ece453_0_avalon_slave_0_translator:uav_readdatavalid -> ece453_0_avalon_slave_0_agent:m0_readdatavalid
wire ece453_0_avalon_slave_0_agent_m0_lock; // ece453_0_avalon_slave_0_agent:m0_lock -> ece453_0_avalon_slave_0_translator:uav_lock
wire [31:0] ece453_0_avalon_slave_0_agent_m0_writedata; // ece453_0_avalon_slave_0_agent:m0_writedata -> ece453_0_avalon_slave_0_translator:uav_writedata
wire ece453_0_avalon_slave_0_agent_m0_write; // ece453_0_avalon_slave_0_agent:m0_write -> ece453_0_avalon_slave_0_translator:uav_write
wire [2:0] ece453_0_avalon_slave_0_agent_m0_burstcount; // ece453_0_avalon_slave_0_agent:m0_burstcount -> ece453_0_avalon_slave_0_translator:uav_burstcount
wire ece453_0_avalon_slave_0_agent_rf_source_valid; // ece453_0_avalon_slave_0_agent:rf_source_valid -> ece453_0_avalon_slave_0_agent_rsp_fifo:in_valid
wire [127:0] ece453_0_avalon_slave_0_agent_rf_source_data; // ece453_0_avalon_slave_0_agent:rf_source_data -> ece453_0_avalon_slave_0_agent_rsp_fifo:in_data
wire ece453_0_avalon_slave_0_agent_rf_source_ready; // ece453_0_avalon_slave_0_agent_rsp_fifo:in_ready -> ece453_0_avalon_slave_0_agent:rf_source_ready
wire ece453_0_avalon_slave_0_agent_rf_source_startofpacket; // ece453_0_avalon_slave_0_agent:rf_source_startofpacket -> ece453_0_avalon_slave_0_agent_rsp_fifo:in_startofpacket
wire ece453_0_avalon_slave_0_agent_rf_source_endofpacket; // ece453_0_avalon_slave_0_agent:rf_source_endofpacket -> ece453_0_avalon_slave_0_agent_rsp_fifo:in_endofpacket
wire ece453_0_avalon_slave_0_agent_rsp_fifo_out_valid; // ece453_0_avalon_slave_0_agent_rsp_fifo:out_valid -> ece453_0_avalon_slave_0_agent:rf_sink_valid
wire [127:0] ece453_0_avalon_slave_0_agent_rsp_fifo_out_data; // ece453_0_avalon_slave_0_agent_rsp_fifo:out_data -> ece453_0_avalon_slave_0_agent:rf_sink_data
wire ece453_0_avalon_slave_0_agent_rsp_fifo_out_ready; // ece453_0_avalon_slave_0_agent:rf_sink_ready -> ece453_0_avalon_slave_0_agent_rsp_fifo:out_ready
wire ece453_0_avalon_slave_0_agent_rsp_fifo_out_startofpacket; // ece453_0_avalon_slave_0_agent_rsp_fifo:out_startofpacket -> ece453_0_avalon_slave_0_agent:rf_sink_startofpacket
wire ece453_0_avalon_slave_0_agent_rsp_fifo_out_endofpacket; // ece453_0_avalon_slave_0_agent_rsp_fifo:out_endofpacket -> ece453_0_avalon_slave_0_agent:rf_sink_endofpacket
wire ece453_0_avalon_slave_0_agent_rdata_fifo_src_valid; // ece453_0_avalon_slave_0_agent:rdata_fifo_src_valid -> ece453_0_avalon_slave_0_agent_rdata_fifo:in_valid
wire [33:0] ece453_0_avalon_slave_0_agent_rdata_fifo_src_data; // ece453_0_avalon_slave_0_agent:rdata_fifo_src_data -> ece453_0_avalon_slave_0_agent_rdata_fifo:in_data
wire ece453_0_avalon_slave_0_agent_rdata_fifo_src_ready; // ece453_0_avalon_slave_0_agent_rdata_fifo:in_ready -> ece453_0_avalon_slave_0_agent:rdata_fifo_src_ready
wire [31:0] sysid_qsys_control_slave_agent_m0_readdata; // sysid_qsys_control_slave_translator:uav_readdata -> sysid_qsys_control_slave_agent:m0_readdata
wire sysid_qsys_control_slave_agent_m0_waitrequest; // sysid_qsys_control_slave_translator:uav_waitrequest -> sysid_qsys_control_slave_agent:m0_waitrequest
wire sysid_qsys_control_slave_agent_m0_debugaccess; // sysid_qsys_control_slave_agent:m0_debugaccess -> sysid_qsys_control_slave_translator:uav_debugaccess
wire [31:0] sysid_qsys_control_slave_agent_m0_address; // sysid_qsys_control_slave_agent:m0_address -> sysid_qsys_control_slave_translator:uav_address
wire [3:0] sysid_qsys_control_slave_agent_m0_byteenable; // sysid_qsys_control_slave_agent:m0_byteenable -> sysid_qsys_control_slave_translator:uav_byteenable
wire sysid_qsys_control_slave_agent_m0_read; // sysid_qsys_control_slave_agent:m0_read -> sysid_qsys_control_slave_translator:uav_read
wire sysid_qsys_control_slave_agent_m0_readdatavalid; // sysid_qsys_control_slave_translator:uav_readdatavalid -> sysid_qsys_control_slave_agent:m0_readdatavalid
wire sysid_qsys_control_slave_agent_m0_lock; // sysid_qsys_control_slave_agent:m0_lock -> sysid_qsys_control_slave_translator:uav_lock
wire [31:0] sysid_qsys_control_slave_agent_m0_writedata; // sysid_qsys_control_slave_agent:m0_writedata -> sysid_qsys_control_slave_translator:uav_writedata
wire sysid_qsys_control_slave_agent_m0_write; // sysid_qsys_control_slave_agent:m0_write -> sysid_qsys_control_slave_translator:uav_write
wire [2:0] sysid_qsys_control_slave_agent_m0_burstcount; // sysid_qsys_control_slave_agent:m0_burstcount -> sysid_qsys_control_slave_translator:uav_burstcount
wire sysid_qsys_control_slave_agent_rf_source_valid; // sysid_qsys_control_slave_agent:rf_source_valid -> sysid_qsys_control_slave_agent_rsp_fifo:in_valid
wire [127:0] sysid_qsys_control_slave_agent_rf_source_data; // sysid_qsys_control_slave_agent:rf_source_data -> sysid_qsys_control_slave_agent_rsp_fifo:in_data
wire sysid_qsys_control_slave_agent_rf_source_ready; // sysid_qsys_control_slave_agent_rsp_fifo:in_ready -> sysid_qsys_control_slave_agent:rf_source_ready
wire sysid_qsys_control_slave_agent_rf_source_startofpacket; // sysid_qsys_control_slave_agent:rf_source_startofpacket -> sysid_qsys_control_slave_agent_rsp_fifo:in_startofpacket
wire sysid_qsys_control_slave_agent_rf_source_endofpacket; // sysid_qsys_control_slave_agent:rf_source_endofpacket -> sysid_qsys_control_slave_agent_rsp_fifo:in_endofpacket
wire sysid_qsys_control_slave_agent_rsp_fifo_out_valid; // sysid_qsys_control_slave_agent_rsp_fifo:out_valid -> sysid_qsys_control_slave_agent:rf_sink_valid
wire [127:0] sysid_qsys_control_slave_agent_rsp_fifo_out_data; // sysid_qsys_control_slave_agent_rsp_fifo:out_data -> sysid_qsys_control_slave_agent:rf_sink_data
wire sysid_qsys_control_slave_agent_rsp_fifo_out_ready; // sysid_qsys_control_slave_agent:rf_sink_ready -> sysid_qsys_control_slave_agent_rsp_fifo:out_ready
wire sysid_qsys_control_slave_agent_rsp_fifo_out_startofpacket; // sysid_qsys_control_slave_agent_rsp_fifo:out_startofpacket -> sysid_qsys_control_slave_agent:rf_sink_startofpacket
wire sysid_qsys_control_slave_agent_rsp_fifo_out_endofpacket; // sysid_qsys_control_slave_agent_rsp_fifo:out_endofpacket -> sysid_qsys_control_slave_agent:rf_sink_endofpacket
wire sysid_qsys_control_slave_agent_rdata_fifo_src_valid; // sysid_qsys_control_slave_agent:rdata_fifo_src_valid -> sysid_qsys_control_slave_agent_rdata_fifo:in_valid
wire [33:0] sysid_qsys_control_slave_agent_rdata_fifo_src_data; // sysid_qsys_control_slave_agent:rdata_fifo_src_data -> sysid_qsys_control_slave_agent_rdata_fifo:in_data
wire sysid_qsys_control_slave_agent_rdata_fifo_src_ready; // sysid_qsys_control_slave_agent_rdata_fifo:in_ready -> sysid_qsys_control_slave_agent:rdata_fifo_src_ready
wire [31:0] intr_capturer_0_avalon_slave_0_agent_m0_readdata; // intr_capturer_0_avalon_slave_0_translator:uav_readdata -> intr_capturer_0_avalon_slave_0_agent:m0_readdata
wire intr_capturer_0_avalon_slave_0_agent_m0_waitrequest; // intr_capturer_0_avalon_slave_0_translator:uav_waitrequest -> intr_capturer_0_avalon_slave_0_agent:m0_waitrequest
wire intr_capturer_0_avalon_slave_0_agent_m0_debugaccess; // intr_capturer_0_avalon_slave_0_agent:m0_debugaccess -> intr_capturer_0_avalon_slave_0_translator:uav_debugaccess
wire [31:0] intr_capturer_0_avalon_slave_0_agent_m0_address; // intr_capturer_0_avalon_slave_0_agent:m0_address -> intr_capturer_0_avalon_slave_0_translator:uav_address
wire [3:0] intr_capturer_0_avalon_slave_0_agent_m0_byteenable; // intr_capturer_0_avalon_slave_0_agent:m0_byteenable -> intr_capturer_0_avalon_slave_0_translator:uav_byteenable
wire intr_capturer_0_avalon_slave_0_agent_m0_read; // intr_capturer_0_avalon_slave_0_agent:m0_read -> intr_capturer_0_avalon_slave_0_translator:uav_read
wire intr_capturer_0_avalon_slave_0_agent_m0_readdatavalid; // intr_capturer_0_avalon_slave_0_translator:uav_readdatavalid -> intr_capturer_0_avalon_slave_0_agent:m0_readdatavalid
wire intr_capturer_0_avalon_slave_0_agent_m0_lock; // intr_capturer_0_avalon_slave_0_agent:m0_lock -> intr_capturer_0_avalon_slave_0_translator:uav_lock
wire [31:0] intr_capturer_0_avalon_slave_0_agent_m0_writedata; // intr_capturer_0_avalon_slave_0_agent:m0_writedata -> intr_capturer_0_avalon_slave_0_translator:uav_writedata
wire intr_capturer_0_avalon_slave_0_agent_m0_write; // intr_capturer_0_avalon_slave_0_agent:m0_write -> intr_capturer_0_avalon_slave_0_translator:uav_write
wire [2:0] intr_capturer_0_avalon_slave_0_agent_m0_burstcount; // intr_capturer_0_avalon_slave_0_agent:m0_burstcount -> intr_capturer_0_avalon_slave_0_translator:uav_burstcount
wire intr_capturer_0_avalon_slave_0_agent_rf_source_valid; // intr_capturer_0_avalon_slave_0_agent:rf_source_valid -> intr_capturer_0_avalon_slave_0_agent_rsp_fifo:in_valid
wire [127:0] intr_capturer_0_avalon_slave_0_agent_rf_source_data; // intr_capturer_0_avalon_slave_0_agent:rf_source_data -> intr_capturer_0_avalon_slave_0_agent_rsp_fifo:in_data
wire intr_capturer_0_avalon_slave_0_agent_rf_source_ready; // intr_capturer_0_avalon_slave_0_agent_rsp_fifo:in_ready -> intr_capturer_0_avalon_slave_0_agent:rf_source_ready
wire intr_capturer_0_avalon_slave_0_agent_rf_source_startofpacket; // intr_capturer_0_avalon_slave_0_agent:rf_source_startofpacket -> intr_capturer_0_avalon_slave_0_agent_rsp_fifo:in_startofpacket
wire intr_capturer_0_avalon_slave_0_agent_rf_source_endofpacket; // intr_capturer_0_avalon_slave_0_agent:rf_source_endofpacket -> intr_capturer_0_avalon_slave_0_agent_rsp_fifo:in_endofpacket
wire intr_capturer_0_avalon_slave_0_agent_rsp_fifo_out_valid; // intr_capturer_0_avalon_slave_0_agent_rsp_fifo:out_valid -> intr_capturer_0_avalon_slave_0_agent:rf_sink_valid
wire [127:0] intr_capturer_0_avalon_slave_0_agent_rsp_fifo_out_data; // intr_capturer_0_avalon_slave_0_agent_rsp_fifo:out_data -> intr_capturer_0_avalon_slave_0_agent:rf_sink_data
wire intr_capturer_0_avalon_slave_0_agent_rsp_fifo_out_ready; // intr_capturer_0_avalon_slave_0_agent:rf_sink_ready -> intr_capturer_0_avalon_slave_0_agent_rsp_fifo:out_ready
wire intr_capturer_0_avalon_slave_0_agent_rsp_fifo_out_startofpacket; // intr_capturer_0_avalon_slave_0_agent_rsp_fifo:out_startofpacket -> intr_capturer_0_avalon_slave_0_agent:rf_sink_startofpacket
wire intr_capturer_0_avalon_slave_0_agent_rsp_fifo_out_endofpacket; // intr_capturer_0_avalon_slave_0_agent_rsp_fifo:out_endofpacket -> intr_capturer_0_avalon_slave_0_agent:rf_sink_endofpacket
wire intr_capturer_0_avalon_slave_0_agent_rdata_fifo_src_valid; // intr_capturer_0_avalon_slave_0_agent:rdata_fifo_src_valid -> intr_capturer_0_avalon_slave_0_agent_rdata_fifo:in_valid
wire [33:0] intr_capturer_0_avalon_slave_0_agent_rdata_fifo_src_data; // intr_capturer_0_avalon_slave_0_agent:rdata_fifo_src_data -> intr_capturer_0_avalon_slave_0_agent_rdata_fifo:in_data
wire intr_capturer_0_avalon_slave_0_agent_rdata_fifo_src_ready; // intr_capturer_0_avalon_slave_0_agent_rdata_fifo:in_ready -> intr_capturer_0_avalon_slave_0_agent:rdata_fifo_src_ready
wire cmd_mux_004_src_valid; // cmd_mux_004:src_valid -> intr_capturer_0_avalon_slave_0_agent:cp_valid
wire [126:0] cmd_mux_004_src_data; // cmd_mux_004:src_data -> intr_capturer_0_avalon_slave_0_agent:cp_data
wire cmd_mux_004_src_ready; // intr_capturer_0_avalon_slave_0_agent:cp_ready -> cmd_mux_004:src_ready
wire [4:0] cmd_mux_004_src_channel; // cmd_mux_004:src_channel -> intr_capturer_0_avalon_slave_0_agent:cp_channel
wire cmd_mux_004_src_startofpacket; // cmd_mux_004:src_startofpacket -> intr_capturer_0_avalon_slave_0_agent:cp_startofpacket
wire cmd_mux_004_src_endofpacket; // cmd_mux_004:src_endofpacket -> intr_capturer_0_avalon_slave_0_agent:cp_endofpacket
wire hps_0_h2f_lw_axi_master_agent_write_cp_valid; // hps_0_h2f_lw_axi_master_agent:write_cp_valid -> router:sink_valid
wire [126:0] hps_0_h2f_lw_axi_master_agent_write_cp_data; // hps_0_h2f_lw_axi_master_agent:write_cp_data -> router:sink_data
wire hps_0_h2f_lw_axi_master_agent_write_cp_ready; // router:sink_ready -> hps_0_h2f_lw_axi_master_agent:write_cp_ready
wire hps_0_h2f_lw_axi_master_agent_write_cp_startofpacket; // hps_0_h2f_lw_axi_master_agent:write_cp_startofpacket -> router:sink_startofpacket
wire hps_0_h2f_lw_axi_master_agent_write_cp_endofpacket; // hps_0_h2f_lw_axi_master_agent:write_cp_endofpacket -> router:sink_endofpacket
wire hps_0_h2f_lw_axi_master_agent_read_cp_valid; // hps_0_h2f_lw_axi_master_agent:read_cp_valid -> router_001:sink_valid
wire [126:0] hps_0_h2f_lw_axi_master_agent_read_cp_data; // hps_0_h2f_lw_axi_master_agent:read_cp_data -> router_001:sink_data
wire hps_0_h2f_lw_axi_master_agent_read_cp_ready; // router_001:sink_ready -> hps_0_h2f_lw_axi_master_agent:read_cp_ready
wire hps_0_h2f_lw_axi_master_agent_read_cp_startofpacket; // hps_0_h2f_lw_axi_master_agent:read_cp_startofpacket -> router_001:sink_startofpacket
wire hps_0_h2f_lw_axi_master_agent_read_cp_endofpacket; // hps_0_h2f_lw_axi_master_agent:read_cp_endofpacket -> router_001:sink_endofpacket
wire master_non_sec_master_agent_cp_valid; // master_non_sec_master_agent:cp_valid -> router_002:sink_valid
wire [126:0] master_non_sec_master_agent_cp_data; // master_non_sec_master_agent:cp_data -> router_002:sink_data
wire master_non_sec_master_agent_cp_ready; // router_002:sink_ready -> master_non_sec_master_agent:cp_ready
wire master_non_sec_master_agent_cp_startofpacket; // master_non_sec_master_agent:cp_startofpacket -> router_002:sink_startofpacket
wire master_non_sec_master_agent_cp_endofpacket; // master_non_sec_master_agent:cp_endofpacket -> router_002:sink_endofpacket
wire jtag_uart_avalon_jtag_slave_agent_rp_valid; // jtag_uart_avalon_jtag_slave_agent:rp_valid -> router_003:sink_valid
wire [126:0] jtag_uart_avalon_jtag_slave_agent_rp_data; // jtag_uart_avalon_jtag_slave_agent:rp_data -> router_003:sink_data
wire jtag_uart_avalon_jtag_slave_agent_rp_ready; // router_003:sink_ready -> jtag_uart_avalon_jtag_slave_agent:rp_ready
wire jtag_uart_avalon_jtag_slave_agent_rp_startofpacket; // jtag_uart_avalon_jtag_slave_agent:rp_startofpacket -> router_003:sink_startofpacket
wire jtag_uart_avalon_jtag_slave_agent_rp_endofpacket; // jtag_uart_avalon_jtag_slave_agent:rp_endofpacket -> router_003:sink_endofpacket
wire router_003_src_valid; // router_003:src_valid -> rsp_demux:sink_valid
wire [126:0] router_003_src_data; // router_003:src_data -> rsp_demux:sink_data
wire router_003_src_ready; // rsp_demux:sink_ready -> router_003:src_ready
wire [4:0] router_003_src_channel; // router_003:src_channel -> rsp_demux:sink_channel
wire router_003_src_startofpacket; // router_003:src_startofpacket -> rsp_demux:sink_startofpacket
wire router_003_src_endofpacket; // router_003:src_endofpacket -> rsp_demux:sink_endofpacket
wire alt_vip_vfr_vga_avalon_slave_agent_rp_valid; // alt_vip_vfr_vga_avalon_slave_agent:rp_valid -> router_004:sink_valid
wire [126:0] alt_vip_vfr_vga_avalon_slave_agent_rp_data; // alt_vip_vfr_vga_avalon_slave_agent:rp_data -> router_004:sink_data
wire alt_vip_vfr_vga_avalon_slave_agent_rp_ready; // router_004:sink_ready -> alt_vip_vfr_vga_avalon_slave_agent:rp_ready
wire alt_vip_vfr_vga_avalon_slave_agent_rp_startofpacket; // alt_vip_vfr_vga_avalon_slave_agent:rp_startofpacket -> router_004:sink_startofpacket
wire alt_vip_vfr_vga_avalon_slave_agent_rp_endofpacket; // alt_vip_vfr_vga_avalon_slave_agent:rp_endofpacket -> router_004:sink_endofpacket
wire router_004_src_valid; // router_004:src_valid -> rsp_demux_001:sink_valid
wire [126:0] router_004_src_data; // router_004:src_data -> rsp_demux_001:sink_data
wire router_004_src_ready; // rsp_demux_001:sink_ready -> router_004:src_ready
wire [4:0] router_004_src_channel; // router_004:src_channel -> rsp_demux_001:sink_channel
wire router_004_src_startofpacket; // router_004:src_startofpacket -> rsp_demux_001:sink_startofpacket
wire router_004_src_endofpacket; // router_004:src_endofpacket -> rsp_demux_001:sink_endofpacket
wire ece453_0_avalon_slave_0_agent_rp_valid; // ece453_0_avalon_slave_0_agent:rp_valid -> router_005:sink_valid
wire [126:0] ece453_0_avalon_slave_0_agent_rp_data; // ece453_0_avalon_slave_0_agent:rp_data -> router_005:sink_data
wire ece453_0_avalon_slave_0_agent_rp_ready; // router_005:sink_ready -> ece453_0_avalon_slave_0_agent:rp_ready
wire ece453_0_avalon_slave_0_agent_rp_startofpacket; // ece453_0_avalon_slave_0_agent:rp_startofpacket -> router_005:sink_startofpacket
wire ece453_0_avalon_slave_0_agent_rp_endofpacket; // ece453_0_avalon_slave_0_agent:rp_endofpacket -> router_005:sink_endofpacket
wire router_005_src_valid; // router_005:src_valid -> rsp_demux_002:sink_valid
wire [126:0] router_005_src_data; // router_005:src_data -> rsp_demux_002:sink_data
wire router_005_src_ready; // rsp_demux_002:sink_ready -> router_005:src_ready
wire [4:0] router_005_src_channel; // router_005:src_channel -> rsp_demux_002:sink_channel
wire router_005_src_startofpacket; // router_005:src_startofpacket -> rsp_demux_002:sink_startofpacket
wire router_005_src_endofpacket; // router_005:src_endofpacket -> rsp_demux_002:sink_endofpacket
wire sysid_qsys_control_slave_agent_rp_valid; // sysid_qsys_control_slave_agent:rp_valid -> router_006:sink_valid
wire [126:0] sysid_qsys_control_slave_agent_rp_data; // sysid_qsys_control_slave_agent:rp_data -> router_006:sink_data
wire sysid_qsys_control_slave_agent_rp_ready; // router_006:sink_ready -> sysid_qsys_control_slave_agent:rp_ready
wire sysid_qsys_control_slave_agent_rp_startofpacket; // sysid_qsys_control_slave_agent:rp_startofpacket -> router_006:sink_startofpacket
wire sysid_qsys_control_slave_agent_rp_endofpacket; // sysid_qsys_control_slave_agent:rp_endofpacket -> router_006:sink_endofpacket
wire router_006_src_valid; // router_006:src_valid -> rsp_demux_003:sink_valid
wire [126:0] router_006_src_data; // router_006:src_data -> rsp_demux_003:sink_data
wire router_006_src_ready; // rsp_demux_003:sink_ready -> router_006:src_ready
wire [4:0] router_006_src_channel; // router_006:src_channel -> rsp_demux_003:sink_channel
wire router_006_src_startofpacket; // router_006:src_startofpacket -> rsp_demux_003:sink_startofpacket
wire router_006_src_endofpacket; // router_006:src_endofpacket -> rsp_demux_003:sink_endofpacket
wire intr_capturer_0_avalon_slave_0_agent_rp_valid; // intr_capturer_0_avalon_slave_0_agent:rp_valid -> router_007:sink_valid
wire [126:0] intr_capturer_0_avalon_slave_0_agent_rp_data; // intr_capturer_0_avalon_slave_0_agent:rp_data -> router_007:sink_data
wire intr_capturer_0_avalon_slave_0_agent_rp_ready; // router_007:sink_ready -> intr_capturer_0_avalon_slave_0_agent:rp_ready
wire intr_capturer_0_avalon_slave_0_agent_rp_startofpacket; // intr_capturer_0_avalon_slave_0_agent:rp_startofpacket -> router_007:sink_startofpacket
wire intr_capturer_0_avalon_slave_0_agent_rp_endofpacket; // intr_capturer_0_avalon_slave_0_agent:rp_endofpacket -> router_007:sink_endofpacket
wire router_007_src_valid; // router_007:src_valid -> rsp_demux_004:sink_valid
wire [126:0] router_007_src_data; // router_007:src_data -> rsp_demux_004:sink_data
wire router_007_src_ready; // rsp_demux_004:sink_ready -> router_007:src_ready
wire [4:0] router_007_src_channel; // router_007:src_channel -> rsp_demux_004:sink_channel
wire router_007_src_startofpacket; // router_007:src_startofpacket -> rsp_demux_004:sink_startofpacket
wire router_007_src_endofpacket; // router_007:src_endofpacket -> rsp_demux_004:sink_endofpacket
wire router_src_valid; // router:src_valid -> hps_0_h2f_lw_axi_master_wr_limiter:cmd_sink_valid
wire [126:0] router_src_data; // router:src_data -> hps_0_h2f_lw_axi_master_wr_limiter:cmd_sink_data
wire router_src_ready; // hps_0_h2f_lw_axi_master_wr_limiter:cmd_sink_ready -> router:src_ready
wire [4:0] router_src_channel; // router:src_channel -> hps_0_h2f_lw_axi_master_wr_limiter:cmd_sink_channel
wire router_src_startofpacket; // router:src_startofpacket -> hps_0_h2f_lw_axi_master_wr_limiter:cmd_sink_startofpacket
wire router_src_endofpacket; // router:src_endofpacket -> hps_0_h2f_lw_axi_master_wr_limiter:cmd_sink_endofpacket
wire [126:0] hps_0_h2f_lw_axi_master_wr_limiter_cmd_src_data; // hps_0_h2f_lw_axi_master_wr_limiter:cmd_src_data -> cmd_demux:sink_data
wire hps_0_h2f_lw_axi_master_wr_limiter_cmd_src_ready; // cmd_demux:sink_ready -> hps_0_h2f_lw_axi_master_wr_limiter:cmd_src_ready
wire [4:0] hps_0_h2f_lw_axi_master_wr_limiter_cmd_src_channel; // hps_0_h2f_lw_axi_master_wr_limiter:cmd_src_channel -> cmd_demux:sink_channel
wire hps_0_h2f_lw_axi_master_wr_limiter_cmd_src_startofpacket; // hps_0_h2f_lw_axi_master_wr_limiter:cmd_src_startofpacket -> cmd_demux:sink_startofpacket
wire hps_0_h2f_lw_axi_master_wr_limiter_cmd_src_endofpacket; // hps_0_h2f_lw_axi_master_wr_limiter:cmd_src_endofpacket -> cmd_demux:sink_endofpacket
wire rsp_mux_src_valid; // rsp_mux:src_valid -> hps_0_h2f_lw_axi_master_wr_limiter:rsp_sink_valid
wire [126:0] rsp_mux_src_data; // rsp_mux:src_data -> hps_0_h2f_lw_axi_master_wr_limiter:rsp_sink_data
wire rsp_mux_src_ready; // hps_0_h2f_lw_axi_master_wr_limiter:rsp_sink_ready -> rsp_mux:src_ready
wire [4:0] rsp_mux_src_channel; // rsp_mux:src_channel -> hps_0_h2f_lw_axi_master_wr_limiter:rsp_sink_channel
wire rsp_mux_src_startofpacket; // rsp_mux:src_startofpacket -> hps_0_h2f_lw_axi_master_wr_limiter:rsp_sink_startofpacket
wire rsp_mux_src_endofpacket; // rsp_mux:src_endofpacket -> hps_0_h2f_lw_axi_master_wr_limiter:rsp_sink_endofpacket
wire hps_0_h2f_lw_axi_master_wr_limiter_rsp_src_valid; // hps_0_h2f_lw_axi_master_wr_limiter:rsp_src_valid -> hps_0_h2f_lw_axi_master_agent:write_rp_valid
wire [126:0] hps_0_h2f_lw_axi_master_wr_limiter_rsp_src_data; // hps_0_h2f_lw_axi_master_wr_limiter:rsp_src_data -> hps_0_h2f_lw_axi_master_agent:write_rp_data
wire hps_0_h2f_lw_axi_master_wr_limiter_rsp_src_ready; // hps_0_h2f_lw_axi_master_agent:write_rp_ready -> hps_0_h2f_lw_axi_master_wr_limiter:rsp_src_ready
wire [4:0] hps_0_h2f_lw_axi_master_wr_limiter_rsp_src_channel; // hps_0_h2f_lw_axi_master_wr_limiter:rsp_src_channel -> hps_0_h2f_lw_axi_master_agent:write_rp_channel
wire hps_0_h2f_lw_axi_master_wr_limiter_rsp_src_startofpacket; // hps_0_h2f_lw_axi_master_wr_limiter:rsp_src_startofpacket -> hps_0_h2f_lw_axi_master_agent:write_rp_startofpacket
wire hps_0_h2f_lw_axi_master_wr_limiter_rsp_src_endofpacket; // hps_0_h2f_lw_axi_master_wr_limiter:rsp_src_endofpacket -> hps_0_h2f_lw_axi_master_agent:write_rp_endofpacket
wire router_001_src_valid; // router_001:src_valid -> hps_0_h2f_lw_axi_master_rd_limiter:cmd_sink_valid
wire [126:0] router_001_src_data; // router_001:src_data -> hps_0_h2f_lw_axi_master_rd_limiter:cmd_sink_data
wire router_001_src_ready; // hps_0_h2f_lw_axi_master_rd_limiter:cmd_sink_ready -> router_001:src_ready
wire [4:0] router_001_src_channel; // router_001:src_channel -> hps_0_h2f_lw_axi_master_rd_limiter:cmd_sink_channel
wire router_001_src_startofpacket; // router_001:src_startofpacket -> hps_0_h2f_lw_axi_master_rd_limiter:cmd_sink_startofpacket
wire router_001_src_endofpacket; // router_001:src_endofpacket -> hps_0_h2f_lw_axi_master_rd_limiter:cmd_sink_endofpacket
wire [126:0] hps_0_h2f_lw_axi_master_rd_limiter_cmd_src_data; // hps_0_h2f_lw_axi_master_rd_limiter:cmd_src_data -> cmd_demux_001:sink_data
wire hps_0_h2f_lw_axi_master_rd_limiter_cmd_src_ready; // cmd_demux_001:sink_ready -> hps_0_h2f_lw_axi_master_rd_limiter:cmd_src_ready
wire [4:0] hps_0_h2f_lw_axi_master_rd_limiter_cmd_src_channel; // hps_0_h2f_lw_axi_master_rd_limiter:cmd_src_channel -> cmd_demux_001:sink_channel
wire hps_0_h2f_lw_axi_master_rd_limiter_cmd_src_startofpacket; // hps_0_h2f_lw_axi_master_rd_limiter:cmd_src_startofpacket -> cmd_demux_001:sink_startofpacket
wire hps_0_h2f_lw_axi_master_rd_limiter_cmd_src_endofpacket; // hps_0_h2f_lw_axi_master_rd_limiter:cmd_src_endofpacket -> cmd_demux_001:sink_endofpacket
wire rsp_mux_001_src_valid; // rsp_mux_001:src_valid -> hps_0_h2f_lw_axi_master_rd_limiter:rsp_sink_valid
wire [126:0] rsp_mux_001_src_data; // rsp_mux_001:src_data -> hps_0_h2f_lw_axi_master_rd_limiter:rsp_sink_data
wire rsp_mux_001_src_ready; // hps_0_h2f_lw_axi_master_rd_limiter:rsp_sink_ready -> rsp_mux_001:src_ready
wire [4:0] rsp_mux_001_src_channel; // rsp_mux_001:src_channel -> hps_0_h2f_lw_axi_master_rd_limiter:rsp_sink_channel
wire rsp_mux_001_src_startofpacket; // rsp_mux_001:src_startofpacket -> hps_0_h2f_lw_axi_master_rd_limiter:rsp_sink_startofpacket
wire rsp_mux_001_src_endofpacket; // rsp_mux_001:src_endofpacket -> hps_0_h2f_lw_axi_master_rd_limiter:rsp_sink_endofpacket
wire hps_0_h2f_lw_axi_master_rd_limiter_rsp_src_valid; // hps_0_h2f_lw_axi_master_rd_limiter:rsp_src_valid -> hps_0_h2f_lw_axi_master_agent:read_rp_valid
wire [126:0] hps_0_h2f_lw_axi_master_rd_limiter_rsp_src_data; // hps_0_h2f_lw_axi_master_rd_limiter:rsp_src_data -> hps_0_h2f_lw_axi_master_agent:read_rp_data
wire hps_0_h2f_lw_axi_master_rd_limiter_rsp_src_ready; // hps_0_h2f_lw_axi_master_agent:read_rp_ready -> hps_0_h2f_lw_axi_master_rd_limiter:rsp_src_ready
wire [4:0] hps_0_h2f_lw_axi_master_rd_limiter_rsp_src_channel; // hps_0_h2f_lw_axi_master_rd_limiter:rsp_src_channel -> hps_0_h2f_lw_axi_master_agent:read_rp_channel
wire hps_0_h2f_lw_axi_master_rd_limiter_rsp_src_startofpacket; // hps_0_h2f_lw_axi_master_rd_limiter:rsp_src_startofpacket -> hps_0_h2f_lw_axi_master_agent:read_rp_startofpacket
wire hps_0_h2f_lw_axi_master_rd_limiter_rsp_src_endofpacket; // hps_0_h2f_lw_axi_master_rd_limiter:rsp_src_endofpacket -> hps_0_h2f_lw_axi_master_agent:read_rp_endofpacket
wire router_002_src_valid; // router_002:src_valid -> master_non_sec_master_limiter:cmd_sink_valid
wire [126:0] router_002_src_data; // router_002:src_data -> master_non_sec_master_limiter:cmd_sink_data
wire router_002_src_ready; // master_non_sec_master_limiter:cmd_sink_ready -> router_002:src_ready
wire [4:0] router_002_src_channel; // router_002:src_channel -> master_non_sec_master_limiter:cmd_sink_channel
wire router_002_src_startofpacket; // router_002:src_startofpacket -> master_non_sec_master_limiter:cmd_sink_startofpacket
wire router_002_src_endofpacket; // router_002:src_endofpacket -> master_non_sec_master_limiter:cmd_sink_endofpacket
wire [126:0] master_non_sec_master_limiter_cmd_src_data; // master_non_sec_master_limiter:cmd_src_data -> cmd_demux_002:sink_data
wire master_non_sec_master_limiter_cmd_src_ready; // cmd_demux_002:sink_ready -> master_non_sec_master_limiter:cmd_src_ready
wire [4:0] master_non_sec_master_limiter_cmd_src_channel; // master_non_sec_master_limiter:cmd_src_channel -> cmd_demux_002:sink_channel
wire master_non_sec_master_limiter_cmd_src_startofpacket; // master_non_sec_master_limiter:cmd_src_startofpacket -> cmd_demux_002:sink_startofpacket
wire master_non_sec_master_limiter_cmd_src_endofpacket; // master_non_sec_master_limiter:cmd_src_endofpacket -> cmd_demux_002:sink_endofpacket
wire rsp_mux_002_src_valid; // rsp_mux_002:src_valid -> master_non_sec_master_limiter:rsp_sink_valid
wire [126:0] rsp_mux_002_src_data; // rsp_mux_002:src_data -> master_non_sec_master_limiter:rsp_sink_data
wire rsp_mux_002_src_ready; // master_non_sec_master_limiter:rsp_sink_ready -> rsp_mux_002:src_ready
wire [4:0] rsp_mux_002_src_channel; // rsp_mux_002:src_channel -> master_non_sec_master_limiter:rsp_sink_channel
wire rsp_mux_002_src_startofpacket; // rsp_mux_002:src_startofpacket -> master_non_sec_master_limiter:rsp_sink_startofpacket
wire rsp_mux_002_src_endofpacket; // rsp_mux_002:src_endofpacket -> master_non_sec_master_limiter:rsp_sink_endofpacket
wire master_non_sec_master_limiter_rsp_src_valid; // master_non_sec_master_limiter:rsp_src_valid -> master_non_sec_master_agent:rp_valid
wire [126:0] master_non_sec_master_limiter_rsp_src_data; // master_non_sec_master_limiter:rsp_src_data -> master_non_sec_master_agent:rp_data
wire master_non_sec_master_limiter_rsp_src_ready; // master_non_sec_master_agent:rp_ready -> master_non_sec_master_limiter:rsp_src_ready
wire [4:0] master_non_sec_master_limiter_rsp_src_channel; // master_non_sec_master_limiter:rsp_src_channel -> master_non_sec_master_agent:rp_channel
wire master_non_sec_master_limiter_rsp_src_startofpacket; // master_non_sec_master_limiter:rsp_src_startofpacket -> master_non_sec_master_agent:rp_startofpacket
wire master_non_sec_master_limiter_rsp_src_endofpacket; // master_non_sec_master_limiter:rsp_src_endofpacket -> master_non_sec_master_agent:rp_endofpacket
wire cmd_mux_src_valid; // cmd_mux:src_valid -> jtag_uart_avalon_jtag_slave_burst_adapter:sink0_valid
wire [126:0] cmd_mux_src_data; // cmd_mux:src_data -> jtag_uart_avalon_jtag_slave_burst_adapter:sink0_data
wire cmd_mux_src_ready; // jtag_uart_avalon_jtag_slave_burst_adapter:sink0_ready -> cmd_mux:src_ready
wire [4:0] cmd_mux_src_channel; // cmd_mux:src_channel -> jtag_uart_avalon_jtag_slave_burst_adapter:sink0_channel
wire cmd_mux_src_startofpacket; // cmd_mux:src_startofpacket -> jtag_uart_avalon_jtag_slave_burst_adapter:sink0_startofpacket
wire cmd_mux_src_endofpacket; // cmd_mux:src_endofpacket -> jtag_uart_avalon_jtag_slave_burst_adapter:sink0_endofpacket
wire jtag_uart_avalon_jtag_slave_burst_adapter_source0_valid; // jtag_uart_avalon_jtag_slave_burst_adapter:source0_valid -> jtag_uart_avalon_jtag_slave_agent:cp_valid
wire [126:0] jtag_uart_avalon_jtag_slave_burst_adapter_source0_data; // jtag_uart_avalon_jtag_slave_burst_adapter:source0_data -> jtag_uart_avalon_jtag_slave_agent:cp_data
wire jtag_uart_avalon_jtag_slave_burst_adapter_source0_ready; // jtag_uart_avalon_jtag_slave_agent:cp_ready -> jtag_uart_avalon_jtag_slave_burst_adapter:source0_ready
wire [4:0] jtag_uart_avalon_jtag_slave_burst_adapter_source0_channel; // jtag_uart_avalon_jtag_slave_burst_adapter:source0_channel -> jtag_uart_avalon_jtag_slave_agent:cp_channel
wire jtag_uart_avalon_jtag_slave_burst_adapter_source0_startofpacket; // jtag_uart_avalon_jtag_slave_burst_adapter:source0_startofpacket -> jtag_uart_avalon_jtag_slave_agent:cp_startofpacket
wire jtag_uart_avalon_jtag_slave_burst_adapter_source0_endofpacket; // jtag_uart_avalon_jtag_slave_burst_adapter:source0_endofpacket -> jtag_uart_avalon_jtag_slave_agent:cp_endofpacket
wire cmd_mux_001_src_valid; // cmd_mux_001:src_valid -> alt_vip_vfr_vga_avalon_slave_burst_adapter:sink0_valid
wire [126:0] cmd_mux_001_src_data; // cmd_mux_001:src_data -> alt_vip_vfr_vga_avalon_slave_burst_adapter:sink0_data
wire cmd_mux_001_src_ready; // alt_vip_vfr_vga_avalon_slave_burst_adapter:sink0_ready -> cmd_mux_001:src_ready
wire [4:0] cmd_mux_001_src_channel; // cmd_mux_001:src_channel -> alt_vip_vfr_vga_avalon_slave_burst_adapter:sink0_channel
wire cmd_mux_001_src_startofpacket; // cmd_mux_001:src_startofpacket -> alt_vip_vfr_vga_avalon_slave_burst_adapter:sink0_startofpacket
wire cmd_mux_001_src_endofpacket; // cmd_mux_001:src_endofpacket -> alt_vip_vfr_vga_avalon_slave_burst_adapter:sink0_endofpacket
wire alt_vip_vfr_vga_avalon_slave_burst_adapter_source0_valid; // alt_vip_vfr_vga_avalon_slave_burst_adapter:source0_valid -> alt_vip_vfr_vga_avalon_slave_agent:cp_valid
wire [126:0] alt_vip_vfr_vga_avalon_slave_burst_adapter_source0_data; // alt_vip_vfr_vga_avalon_slave_burst_adapter:source0_data -> alt_vip_vfr_vga_avalon_slave_agent:cp_data
wire alt_vip_vfr_vga_avalon_slave_burst_adapter_source0_ready; // alt_vip_vfr_vga_avalon_slave_agent:cp_ready -> alt_vip_vfr_vga_avalon_slave_burst_adapter:source0_ready
wire [4:0] alt_vip_vfr_vga_avalon_slave_burst_adapter_source0_channel; // alt_vip_vfr_vga_avalon_slave_burst_adapter:source0_channel -> alt_vip_vfr_vga_avalon_slave_agent:cp_channel
wire alt_vip_vfr_vga_avalon_slave_burst_adapter_source0_startofpacket; // alt_vip_vfr_vga_avalon_slave_burst_adapter:source0_startofpacket -> alt_vip_vfr_vga_avalon_slave_agent:cp_startofpacket
wire alt_vip_vfr_vga_avalon_slave_burst_adapter_source0_endofpacket; // alt_vip_vfr_vga_avalon_slave_burst_adapter:source0_endofpacket -> alt_vip_vfr_vga_avalon_slave_agent:cp_endofpacket
wire cmd_mux_002_src_valid; // cmd_mux_002:src_valid -> ece453_0_avalon_slave_0_burst_adapter:sink0_valid
wire [126:0] cmd_mux_002_src_data; // cmd_mux_002:src_data -> ece453_0_avalon_slave_0_burst_adapter:sink0_data
wire cmd_mux_002_src_ready; // ece453_0_avalon_slave_0_burst_adapter:sink0_ready -> cmd_mux_002:src_ready
wire [4:0] cmd_mux_002_src_channel; // cmd_mux_002:src_channel -> ece453_0_avalon_slave_0_burst_adapter:sink0_channel
wire cmd_mux_002_src_startofpacket; // cmd_mux_002:src_startofpacket -> ece453_0_avalon_slave_0_burst_adapter:sink0_startofpacket
wire cmd_mux_002_src_endofpacket; // cmd_mux_002:src_endofpacket -> ece453_0_avalon_slave_0_burst_adapter:sink0_endofpacket
wire ece453_0_avalon_slave_0_burst_adapter_source0_valid; // ece453_0_avalon_slave_0_burst_adapter:source0_valid -> ece453_0_avalon_slave_0_agent:cp_valid
wire [126:0] ece453_0_avalon_slave_0_burst_adapter_source0_data; // ece453_0_avalon_slave_0_burst_adapter:source0_data -> ece453_0_avalon_slave_0_agent:cp_data
wire ece453_0_avalon_slave_0_burst_adapter_source0_ready; // ece453_0_avalon_slave_0_agent:cp_ready -> ece453_0_avalon_slave_0_burst_adapter:source0_ready
wire [4:0] ece453_0_avalon_slave_0_burst_adapter_source0_channel; // ece453_0_avalon_slave_0_burst_adapter:source0_channel -> ece453_0_avalon_slave_0_agent:cp_channel
wire ece453_0_avalon_slave_0_burst_adapter_source0_startofpacket; // ece453_0_avalon_slave_0_burst_adapter:source0_startofpacket -> ece453_0_avalon_slave_0_agent:cp_startofpacket
wire ece453_0_avalon_slave_0_burst_adapter_source0_endofpacket; // ece453_0_avalon_slave_0_burst_adapter:source0_endofpacket -> ece453_0_avalon_slave_0_agent:cp_endofpacket
wire cmd_mux_003_src_valid; // cmd_mux_003:src_valid -> sysid_qsys_control_slave_burst_adapter:sink0_valid
wire [126:0] cmd_mux_003_src_data; // cmd_mux_003:src_data -> sysid_qsys_control_slave_burst_adapter:sink0_data
wire cmd_mux_003_src_ready; // sysid_qsys_control_slave_burst_adapter:sink0_ready -> cmd_mux_003:src_ready
wire [4:0] cmd_mux_003_src_channel; // cmd_mux_003:src_channel -> sysid_qsys_control_slave_burst_adapter:sink0_channel
wire cmd_mux_003_src_startofpacket; // cmd_mux_003:src_startofpacket -> sysid_qsys_control_slave_burst_adapter:sink0_startofpacket
wire cmd_mux_003_src_endofpacket; // cmd_mux_003:src_endofpacket -> sysid_qsys_control_slave_burst_adapter:sink0_endofpacket
wire sysid_qsys_control_slave_burst_adapter_source0_valid; // sysid_qsys_control_slave_burst_adapter:source0_valid -> sysid_qsys_control_slave_agent:cp_valid
wire [126:0] sysid_qsys_control_slave_burst_adapter_source0_data; // sysid_qsys_control_slave_burst_adapter:source0_data -> sysid_qsys_control_slave_agent:cp_data
wire sysid_qsys_control_slave_burst_adapter_source0_ready; // sysid_qsys_control_slave_agent:cp_ready -> sysid_qsys_control_slave_burst_adapter:source0_ready
wire [4:0] sysid_qsys_control_slave_burst_adapter_source0_channel; // sysid_qsys_control_slave_burst_adapter:source0_channel -> sysid_qsys_control_slave_agent:cp_channel
wire sysid_qsys_control_slave_burst_adapter_source0_startofpacket; // sysid_qsys_control_slave_burst_adapter:source0_startofpacket -> sysid_qsys_control_slave_agent:cp_startofpacket
wire sysid_qsys_control_slave_burst_adapter_source0_endofpacket; // sysid_qsys_control_slave_burst_adapter:source0_endofpacket -> sysid_qsys_control_slave_agent:cp_endofpacket
wire cmd_demux_src0_valid; // cmd_demux:src0_valid -> cmd_mux:sink0_valid
wire [126:0] cmd_demux_src0_data; // cmd_demux:src0_data -> cmd_mux:sink0_data
wire cmd_demux_src0_ready; // cmd_mux:sink0_ready -> cmd_demux:src0_ready
wire [4:0] cmd_demux_src0_channel; // cmd_demux:src0_channel -> cmd_mux:sink0_channel
wire cmd_demux_src0_startofpacket; // cmd_demux:src0_startofpacket -> cmd_mux:sink0_startofpacket
wire cmd_demux_src0_endofpacket; // cmd_demux:src0_endofpacket -> cmd_mux:sink0_endofpacket
wire cmd_demux_src2_valid; // cmd_demux:src2_valid -> cmd_mux_002:sink0_valid
wire [126:0] cmd_demux_src2_data; // cmd_demux:src2_data -> cmd_mux_002:sink0_data
wire cmd_demux_src2_ready; // cmd_mux_002:sink0_ready -> cmd_demux:src2_ready
wire [4:0] cmd_demux_src2_channel; // cmd_demux:src2_channel -> cmd_mux_002:sink0_channel
wire cmd_demux_src2_startofpacket; // cmd_demux:src2_startofpacket -> cmd_mux_002:sink0_startofpacket
wire cmd_demux_src2_endofpacket; // cmd_demux:src2_endofpacket -> cmd_mux_002:sink0_endofpacket
wire cmd_demux_src3_valid; // cmd_demux:src3_valid -> cmd_mux_003:sink0_valid
wire [126:0] cmd_demux_src3_data; // cmd_demux:src3_data -> cmd_mux_003:sink0_data
wire cmd_demux_src3_ready; // cmd_mux_003:sink0_ready -> cmd_demux:src3_ready
wire [4:0] cmd_demux_src3_channel; // cmd_demux:src3_channel -> cmd_mux_003:sink0_channel
wire cmd_demux_src3_startofpacket; // cmd_demux:src3_startofpacket -> cmd_mux_003:sink0_startofpacket
wire cmd_demux_src3_endofpacket; // cmd_demux:src3_endofpacket -> cmd_mux_003:sink0_endofpacket
wire cmd_demux_001_src0_valid; // cmd_demux_001:src0_valid -> cmd_mux:sink1_valid
wire [126:0] cmd_demux_001_src0_data; // cmd_demux_001:src0_data -> cmd_mux:sink1_data
wire cmd_demux_001_src0_ready; // cmd_mux:sink1_ready -> cmd_demux_001:src0_ready
wire [4:0] cmd_demux_001_src0_channel; // cmd_demux_001:src0_channel -> cmd_mux:sink1_channel
wire cmd_demux_001_src0_startofpacket; // cmd_demux_001:src0_startofpacket -> cmd_mux:sink1_startofpacket
wire cmd_demux_001_src0_endofpacket; // cmd_demux_001:src0_endofpacket -> cmd_mux:sink1_endofpacket
wire cmd_demux_001_src2_valid; // cmd_demux_001:src2_valid -> cmd_mux_002:sink1_valid
wire [126:0] cmd_demux_001_src2_data; // cmd_demux_001:src2_data -> cmd_mux_002:sink1_data
wire cmd_demux_001_src2_ready; // cmd_mux_002:sink1_ready -> cmd_demux_001:src2_ready
wire [4:0] cmd_demux_001_src2_channel; // cmd_demux_001:src2_channel -> cmd_mux_002:sink1_channel
wire cmd_demux_001_src2_startofpacket; // cmd_demux_001:src2_startofpacket -> cmd_mux_002:sink1_startofpacket
wire cmd_demux_001_src2_endofpacket; // cmd_demux_001:src2_endofpacket -> cmd_mux_002:sink1_endofpacket
wire cmd_demux_001_src3_valid; // cmd_demux_001:src3_valid -> cmd_mux_003:sink1_valid
wire [126:0] cmd_demux_001_src3_data; // cmd_demux_001:src3_data -> cmd_mux_003:sink1_data
wire cmd_demux_001_src3_ready; // cmd_mux_003:sink1_ready -> cmd_demux_001:src3_ready
wire [4:0] cmd_demux_001_src3_channel; // cmd_demux_001:src3_channel -> cmd_mux_003:sink1_channel
wire cmd_demux_001_src3_startofpacket; // cmd_demux_001:src3_startofpacket -> cmd_mux_003:sink1_startofpacket
wire cmd_demux_001_src3_endofpacket; // cmd_demux_001:src3_endofpacket -> cmd_mux_003:sink1_endofpacket
wire cmd_demux_002_src0_valid; // cmd_demux_002:src0_valid -> cmd_mux:sink2_valid
wire [126:0] cmd_demux_002_src0_data; // cmd_demux_002:src0_data -> cmd_mux:sink2_data
wire cmd_demux_002_src0_ready; // cmd_mux:sink2_ready -> cmd_demux_002:src0_ready
wire [4:0] cmd_demux_002_src0_channel; // cmd_demux_002:src0_channel -> cmd_mux:sink2_channel
wire cmd_demux_002_src0_startofpacket; // cmd_demux_002:src0_startofpacket -> cmd_mux:sink2_startofpacket
wire cmd_demux_002_src0_endofpacket; // cmd_demux_002:src0_endofpacket -> cmd_mux:sink2_endofpacket
wire cmd_demux_002_src2_valid; // cmd_demux_002:src2_valid -> cmd_mux_003:sink2_valid
wire [126:0] cmd_demux_002_src2_data; // cmd_demux_002:src2_data -> cmd_mux_003:sink2_data
wire cmd_demux_002_src2_ready; // cmd_mux_003:sink2_ready -> cmd_demux_002:src2_ready
wire [4:0] cmd_demux_002_src2_channel; // cmd_demux_002:src2_channel -> cmd_mux_003:sink2_channel
wire cmd_demux_002_src2_startofpacket; // cmd_demux_002:src2_startofpacket -> cmd_mux_003:sink2_startofpacket
wire cmd_demux_002_src2_endofpacket; // cmd_demux_002:src2_endofpacket -> cmd_mux_003:sink2_endofpacket
wire cmd_demux_002_src3_valid; // cmd_demux_002:src3_valid -> cmd_mux_004:sink0_valid
wire [126:0] cmd_demux_002_src3_data; // cmd_demux_002:src3_data -> cmd_mux_004:sink0_data
wire cmd_demux_002_src3_ready; // cmd_mux_004:sink0_ready -> cmd_demux_002:src3_ready
wire [4:0] cmd_demux_002_src3_channel; // cmd_demux_002:src3_channel -> cmd_mux_004:sink0_channel
wire cmd_demux_002_src3_startofpacket; // cmd_demux_002:src3_startofpacket -> cmd_mux_004:sink0_startofpacket
wire cmd_demux_002_src3_endofpacket; // cmd_demux_002:src3_endofpacket -> cmd_mux_004:sink0_endofpacket
wire rsp_demux_src0_valid; // rsp_demux:src0_valid -> rsp_mux:sink0_valid
wire [126:0] rsp_demux_src0_data; // rsp_demux:src0_data -> rsp_mux:sink0_data
wire rsp_demux_src0_ready; // rsp_mux:sink0_ready -> rsp_demux:src0_ready
wire [4:0] rsp_demux_src0_channel; // rsp_demux:src0_channel -> rsp_mux:sink0_channel
wire rsp_demux_src0_startofpacket; // rsp_demux:src0_startofpacket -> rsp_mux:sink0_startofpacket
wire rsp_demux_src0_endofpacket; // rsp_demux:src0_endofpacket -> rsp_mux:sink0_endofpacket
wire rsp_demux_src1_valid; // rsp_demux:src1_valid -> rsp_mux_001:sink0_valid
wire [126:0] rsp_demux_src1_data; // rsp_demux:src1_data -> rsp_mux_001:sink0_data
wire rsp_demux_src1_ready; // rsp_mux_001:sink0_ready -> rsp_demux:src1_ready
wire [4:0] rsp_demux_src1_channel; // rsp_demux:src1_channel -> rsp_mux_001:sink0_channel
wire rsp_demux_src1_startofpacket; // rsp_demux:src1_startofpacket -> rsp_mux_001:sink0_startofpacket
wire rsp_demux_src1_endofpacket; // rsp_demux:src1_endofpacket -> rsp_mux_001:sink0_endofpacket
wire rsp_demux_src2_valid; // rsp_demux:src2_valid -> rsp_mux_002:sink0_valid
wire [126:0] rsp_demux_src2_data; // rsp_demux:src2_data -> rsp_mux_002:sink0_data
wire rsp_demux_src2_ready; // rsp_mux_002:sink0_ready -> rsp_demux:src2_ready
wire [4:0] rsp_demux_src2_channel; // rsp_demux:src2_channel -> rsp_mux_002:sink0_channel
wire rsp_demux_src2_startofpacket; // rsp_demux:src2_startofpacket -> rsp_mux_002:sink0_startofpacket
wire rsp_demux_src2_endofpacket; // rsp_demux:src2_endofpacket -> rsp_mux_002:sink0_endofpacket
wire rsp_demux_002_src0_valid; // rsp_demux_002:src0_valid -> rsp_mux:sink2_valid
wire [126:0] rsp_demux_002_src0_data; // rsp_demux_002:src0_data -> rsp_mux:sink2_data
wire rsp_demux_002_src0_ready; // rsp_mux:sink2_ready -> rsp_demux_002:src0_ready
wire [4:0] rsp_demux_002_src0_channel; // rsp_demux_002:src0_channel -> rsp_mux:sink2_channel
wire rsp_demux_002_src0_startofpacket; // rsp_demux_002:src0_startofpacket -> rsp_mux:sink2_startofpacket
wire rsp_demux_002_src0_endofpacket; // rsp_demux_002:src0_endofpacket -> rsp_mux:sink2_endofpacket
wire rsp_demux_002_src1_valid; // rsp_demux_002:src1_valid -> rsp_mux_001:sink2_valid
wire [126:0] rsp_demux_002_src1_data; // rsp_demux_002:src1_data -> rsp_mux_001:sink2_data
wire rsp_demux_002_src1_ready; // rsp_mux_001:sink2_ready -> rsp_demux_002:src1_ready
wire [4:0] rsp_demux_002_src1_channel; // rsp_demux_002:src1_channel -> rsp_mux_001:sink2_channel
wire rsp_demux_002_src1_startofpacket; // rsp_demux_002:src1_startofpacket -> rsp_mux_001:sink2_startofpacket
wire rsp_demux_002_src1_endofpacket; // rsp_demux_002:src1_endofpacket -> rsp_mux_001:sink2_endofpacket
wire rsp_demux_003_src0_valid; // rsp_demux_003:src0_valid -> rsp_mux:sink3_valid
wire [126:0] rsp_demux_003_src0_data; // rsp_demux_003:src0_data -> rsp_mux:sink3_data
wire rsp_demux_003_src0_ready; // rsp_mux:sink3_ready -> rsp_demux_003:src0_ready
wire [4:0] rsp_demux_003_src0_channel; // rsp_demux_003:src0_channel -> rsp_mux:sink3_channel
wire rsp_demux_003_src0_startofpacket; // rsp_demux_003:src0_startofpacket -> rsp_mux:sink3_startofpacket
wire rsp_demux_003_src0_endofpacket; // rsp_demux_003:src0_endofpacket -> rsp_mux:sink3_endofpacket
wire rsp_demux_003_src1_valid; // rsp_demux_003:src1_valid -> rsp_mux_001:sink3_valid
wire [126:0] rsp_demux_003_src1_data; // rsp_demux_003:src1_data -> rsp_mux_001:sink3_data
wire rsp_demux_003_src1_ready; // rsp_mux_001:sink3_ready -> rsp_demux_003:src1_ready
wire [4:0] rsp_demux_003_src1_channel; // rsp_demux_003:src1_channel -> rsp_mux_001:sink3_channel
wire rsp_demux_003_src1_startofpacket; // rsp_demux_003:src1_startofpacket -> rsp_mux_001:sink3_startofpacket
wire rsp_demux_003_src1_endofpacket; // rsp_demux_003:src1_endofpacket -> rsp_mux_001:sink3_endofpacket
wire rsp_demux_003_src2_valid; // rsp_demux_003:src2_valid -> rsp_mux_002:sink2_valid
wire [126:0] rsp_demux_003_src2_data; // rsp_demux_003:src2_data -> rsp_mux_002:sink2_data
wire rsp_demux_003_src2_ready; // rsp_mux_002:sink2_ready -> rsp_demux_003:src2_ready
wire [4:0] rsp_demux_003_src2_channel; // rsp_demux_003:src2_channel -> rsp_mux_002:sink2_channel
wire rsp_demux_003_src2_startofpacket; // rsp_demux_003:src2_startofpacket -> rsp_mux_002:sink2_startofpacket
wire rsp_demux_003_src2_endofpacket; // rsp_demux_003:src2_endofpacket -> rsp_mux_002:sink2_endofpacket
wire rsp_demux_004_src0_valid; // rsp_demux_004:src0_valid -> rsp_mux_002:sink3_valid
wire [126:0] rsp_demux_004_src0_data; // rsp_demux_004:src0_data -> rsp_mux_002:sink3_data
wire rsp_demux_004_src0_ready; // rsp_mux_002:sink3_ready -> rsp_demux_004:src0_ready
wire [4:0] rsp_demux_004_src0_channel; // rsp_demux_004:src0_channel -> rsp_mux_002:sink3_channel
wire rsp_demux_004_src0_startofpacket; // rsp_demux_004:src0_startofpacket -> rsp_mux_002:sink3_startofpacket
wire rsp_demux_004_src0_endofpacket; // rsp_demux_004:src0_endofpacket -> rsp_mux_002:sink3_endofpacket
wire cmd_demux_src1_valid; // cmd_demux:src1_valid -> crosser:in_valid
wire [126:0] cmd_demux_src1_data; // cmd_demux:src1_data -> crosser:in_data
wire cmd_demux_src1_ready; // crosser:in_ready -> cmd_demux:src1_ready
wire [4:0] cmd_demux_src1_channel; // cmd_demux:src1_channel -> crosser:in_channel
wire cmd_demux_src1_startofpacket; // cmd_demux:src1_startofpacket -> crosser:in_startofpacket
wire cmd_demux_src1_endofpacket; // cmd_demux:src1_endofpacket -> crosser:in_endofpacket
wire crosser_out_valid; // crosser:out_valid -> cmd_mux_001:sink0_valid
wire [126:0] crosser_out_data; // crosser:out_data -> cmd_mux_001:sink0_data
wire crosser_out_ready; // cmd_mux_001:sink0_ready -> crosser:out_ready
wire [4:0] crosser_out_channel; // crosser:out_channel -> cmd_mux_001:sink0_channel
wire crosser_out_startofpacket; // crosser:out_startofpacket -> cmd_mux_001:sink0_startofpacket
wire crosser_out_endofpacket; // crosser:out_endofpacket -> cmd_mux_001:sink0_endofpacket
wire cmd_demux_001_src1_valid; // cmd_demux_001:src1_valid -> crosser_001:in_valid
wire [126:0] cmd_demux_001_src1_data; // cmd_demux_001:src1_data -> crosser_001:in_data
wire cmd_demux_001_src1_ready; // crosser_001:in_ready -> cmd_demux_001:src1_ready
wire [4:0] cmd_demux_001_src1_channel; // cmd_demux_001:src1_channel -> crosser_001:in_channel
wire cmd_demux_001_src1_startofpacket; // cmd_demux_001:src1_startofpacket -> crosser_001:in_startofpacket
wire cmd_demux_001_src1_endofpacket; // cmd_demux_001:src1_endofpacket -> crosser_001:in_endofpacket
wire crosser_001_out_valid; // crosser_001:out_valid -> cmd_mux_001:sink1_valid
wire [126:0] crosser_001_out_data; // crosser_001:out_data -> cmd_mux_001:sink1_data
wire crosser_001_out_ready; // cmd_mux_001:sink1_ready -> crosser_001:out_ready
wire [4:0] crosser_001_out_channel; // crosser_001:out_channel -> cmd_mux_001:sink1_channel
wire crosser_001_out_startofpacket; // crosser_001:out_startofpacket -> cmd_mux_001:sink1_startofpacket
wire crosser_001_out_endofpacket; // crosser_001:out_endofpacket -> cmd_mux_001:sink1_endofpacket
wire cmd_demux_002_src1_valid; // cmd_demux_002:src1_valid -> crosser_002:in_valid
wire [126:0] cmd_demux_002_src1_data; // cmd_demux_002:src1_data -> crosser_002:in_data
wire cmd_demux_002_src1_ready; // crosser_002:in_ready -> cmd_demux_002:src1_ready
wire [4:0] cmd_demux_002_src1_channel; // cmd_demux_002:src1_channel -> crosser_002:in_channel
wire cmd_demux_002_src1_startofpacket; // cmd_demux_002:src1_startofpacket -> crosser_002:in_startofpacket
wire cmd_demux_002_src1_endofpacket; // cmd_demux_002:src1_endofpacket -> crosser_002:in_endofpacket
wire crosser_002_out_valid; // crosser_002:out_valid -> cmd_mux_001:sink2_valid
wire [126:0] crosser_002_out_data; // crosser_002:out_data -> cmd_mux_001:sink2_data
wire crosser_002_out_ready; // cmd_mux_001:sink2_ready -> crosser_002:out_ready
wire [4:0] crosser_002_out_channel; // crosser_002:out_channel -> cmd_mux_001:sink2_channel
wire crosser_002_out_startofpacket; // crosser_002:out_startofpacket -> cmd_mux_001:sink2_startofpacket
wire crosser_002_out_endofpacket; // crosser_002:out_endofpacket -> cmd_mux_001:sink2_endofpacket
wire rsp_demux_001_src0_valid; // rsp_demux_001:src0_valid -> crosser_003:in_valid
wire [126:0] rsp_demux_001_src0_data; // rsp_demux_001:src0_data -> crosser_003:in_data
wire rsp_demux_001_src0_ready; // crosser_003:in_ready -> rsp_demux_001:src0_ready
wire [4:0] rsp_demux_001_src0_channel; // rsp_demux_001:src0_channel -> crosser_003:in_channel
wire rsp_demux_001_src0_startofpacket; // rsp_demux_001:src0_startofpacket -> crosser_003:in_startofpacket
wire rsp_demux_001_src0_endofpacket; // rsp_demux_001:src0_endofpacket -> crosser_003:in_endofpacket
wire crosser_003_out_valid; // crosser_003:out_valid -> rsp_mux:sink1_valid
wire [126:0] crosser_003_out_data; // crosser_003:out_data -> rsp_mux:sink1_data
wire crosser_003_out_ready; // rsp_mux:sink1_ready -> crosser_003:out_ready
wire [4:0] crosser_003_out_channel; // crosser_003:out_channel -> rsp_mux:sink1_channel
wire crosser_003_out_startofpacket; // crosser_003:out_startofpacket -> rsp_mux:sink1_startofpacket
wire crosser_003_out_endofpacket; // crosser_003:out_endofpacket -> rsp_mux:sink1_endofpacket
wire rsp_demux_001_src1_valid; // rsp_demux_001:src1_valid -> crosser_004:in_valid
wire [126:0] rsp_demux_001_src1_data; // rsp_demux_001:src1_data -> crosser_004:in_data
wire rsp_demux_001_src1_ready; // crosser_004:in_ready -> rsp_demux_001:src1_ready
wire [4:0] rsp_demux_001_src1_channel; // rsp_demux_001:src1_channel -> crosser_004:in_channel
wire rsp_demux_001_src1_startofpacket; // rsp_demux_001:src1_startofpacket -> crosser_004:in_startofpacket
wire rsp_demux_001_src1_endofpacket; // rsp_demux_001:src1_endofpacket -> crosser_004:in_endofpacket
wire crosser_004_out_valid; // crosser_004:out_valid -> rsp_mux_001:sink1_valid
wire [126:0] crosser_004_out_data; // crosser_004:out_data -> rsp_mux_001:sink1_data
wire crosser_004_out_ready; // rsp_mux_001:sink1_ready -> crosser_004:out_ready
wire [4:0] crosser_004_out_channel; // crosser_004:out_channel -> rsp_mux_001:sink1_channel
wire crosser_004_out_startofpacket; // crosser_004:out_startofpacket -> rsp_mux_001:sink1_startofpacket
wire crosser_004_out_endofpacket; // crosser_004:out_endofpacket -> rsp_mux_001:sink1_endofpacket
wire rsp_demux_001_src2_valid; // rsp_demux_001:src2_valid -> crosser_005:in_valid
wire [126:0] rsp_demux_001_src2_data; // rsp_demux_001:src2_data -> crosser_005:in_data
wire rsp_demux_001_src2_ready; // crosser_005:in_ready -> rsp_demux_001:src2_ready
wire [4:0] rsp_demux_001_src2_channel; // rsp_demux_001:src2_channel -> crosser_005:in_channel
wire rsp_demux_001_src2_startofpacket; // rsp_demux_001:src2_startofpacket -> crosser_005:in_startofpacket
wire rsp_demux_001_src2_endofpacket; // rsp_demux_001:src2_endofpacket -> crosser_005:in_endofpacket
wire crosser_005_out_valid; // crosser_005:out_valid -> rsp_mux_002:sink1_valid
wire [126:0] crosser_005_out_data; // crosser_005:out_data -> rsp_mux_002:sink1_data
wire crosser_005_out_ready; // rsp_mux_002:sink1_ready -> crosser_005:out_ready
wire [4:0] crosser_005_out_channel; // crosser_005:out_channel -> rsp_mux_002:sink1_channel
wire crosser_005_out_startofpacket; // crosser_005:out_startofpacket -> rsp_mux_002:sink1_startofpacket
wire crosser_005_out_endofpacket; // crosser_005:out_endofpacket -> rsp_mux_002:sink1_endofpacket
wire [4:0] hps_0_h2f_lw_axi_master_wr_limiter_cmd_valid_data; // hps_0_h2f_lw_axi_master_wr_limiter:cmd_src_valid -> cmd_demux:sink_valid
wire [4:0] hps_0_h2f_lw_axi_master_rd_limiter_cmd_valid_data; // hps_0_h2f_lw_axi_master_rd_limiter:cmd_src_valid -> cmd_demux_001:sink_valid
wire [4:0] master_non_sec_master_limiter_cmd_valid_data; // master_non_sec_master_limiter:cmd_src_valid -> cmd_demux_002:sink_valid
wire jtag_uart_avalon_jtag_slave_agent_rdata_fifo_out_valid; // jtag_uart_avalon_jtag_slave_agent_rdata_fifo:out_valid -> avalon_st_adapter:in_0_valid
wire [33:0] jtag_uart_avalon_jtag_slave_agent_rdata_fifo_out_data; // jtag_uart_avalon_jtag_slave_agent_rdata_fifo:out_data -> avalon_st_adapter:in_0_data
wire jtag_uart_avalon_jtag_slave_agent_rdata_fifo_out_ready; // avalon_st_adapter:in_0_ready -> jtag_uart_avalon_jtag_slave_agent_rdata_fifo:out_ready
wire avalon_st_adapter_out_0_valid; // avalon_st_adapter:out_0_valid -> jtag_uart_avalon_jtag_slave_agent:rdata_fifo_sink_valid
wire [33:0] avalon_st_adapter_out_0_data; // avalon_st_adapter:out_0_data -> jtag_uart_avalon_jtag_slave_agent:rdata_fifo_sink_data
wire avalon_st_adapter_out_0_ready; // jtag_uart_avalon_jtag_slave_agent:rdata_fifo_sink_ready -> avalon_st_adapter:out_0_ready
wire [0:0] avalon_st_adapter_out_0_error; // avalon_st_adapter:out_0_error -> jtag_uart_avalon_jtag_slave_agent:rdata_fifo_sink_error
wire alt_vip_vfr_vga_avalon_slave_agent_rdata_fifo_out_valid; // alt_vip_vfr_vga_avalon_slave_agent_rdata_fifo:out_valid -> avalon_st_adapter_001:in_0_valid
wire [33:0] alt_vip_vfr_vga_avalon_slave_agent_rdata_fifo_out_data; // alt_vip_vfr_vga_avalon_slave_agent_rdata_fifo:out_data -> avalon_st_adapter_001:in_0_data
wire alt_vip_vfr_vga_avalon_slave_agent_rdata_fifo_out_ready; // avalon_st_adapter_001:in_0_ready -> alt_vip_vfr_vga_avalon_slave_agent_rdata_fifo:out_ready
wire avalon_st_adapter_001_out_0_valid; // avalon_st_adapter_001:out_0_valid -> alt_vip_vfr_vga_avalon_slave_agent:rdata_fifo_sink_valid
wire [33:0] avalon_st_adapter_001_out_0_data; // avalon_st_adapter_001:out_0_data -> alt_vip_vfr_vga_avalon_slave_agent:rdata_fifo_sink_data
wire avalon_st_adapter_001_out_0_ready; // alt_vip_vfr_vga_avalon_slave_agent:rdata_fifo_sink_ready -> avalon_st_adapter_001:out_0_ready
wire [0:0] avalon_st_adapter_001_out_0_error; // avalon_st_adapter_001:out_0_error -> alt_vip_vfr_vga_avalon_slave_agent:rdata_fifo_sink_error
wire ece453_0_avalon_slave_0_agent_rdata_fifo_out_valid; // ece453_0_avalon_slave_0_agent_rdata_fifo:out_valid -> avalon_st_adapter_002:in_0_valid
wire [33:0] ece453_0_avalon_slave_0_agent_rdata_fifo_out_data; // ece453_0_avalon_slave_0_agent_rdata_fifo:out_data -> avalon_st_adapter_002:in_0_data
wire ece453_0_avalon_slave_0_agent_rdata_fifo_out_ready; // avalon_st_adapter_002:in_0_ready -> ece453_0_avalon_slave_0_agent_rdata_fifo:out_ready
wire avalon_st_adapter_002_out_0_valid; // avalon_st_adapter_002:out_0_valid -> ece453_0_avalon_slave_0_agent:rdata_fifo_sink_valid
wire [33:0] avalon_st_adapter_002_out_0_data; // avalon_st_adapter_002:out_0_data -> ece453_0_avalon_slave_0_agent:rdata_fifo_sink_data
wire avalon_st_adapter_002_out_0_ready; // ece453_0_avalon_slave_0_agent:rdata_fifo_sink_ready -> avalon_st_adapter_002:out_0_ready
wire [0:0] avalon_st_adapter_002_out_0_error; // avalon_st_adapter_002:out_0_error -> ece453_0_avalon_slave_0_agent:rdata_fifo_sink_error
wire sysid_qsys_control_slave_agent_rdata_fifo_out_valid; // sysid_qsys_control_slave_agent_rdata_fifo:out_valid -> avalon_st_adapter_003:in_0_valid
wire [33:0] sysid_qsys_control_slave_agent_rdata_fifo_out_data; // sysid_qsys_control_slave_agent_rdata_fifo:out_data -> avalon_st_adapter_003:in_0_data
wire sysid_qsys_control_slave_agent_rdata_fifo_out_ready; // avalon_st_adapter_003:in_0_ready -> sysid_qsys_control_slave_agent_rdata_fifo:out_ready
wire avalon_st_adapter_003_out_0_valid; // avalon_st_adapter_003:out_0_valid -> sysid_qsys_control_slave_agent:rdata_fifo_sink_valid
wire [33:0] avalon_st_adapter_003_out_0_data; // avalon_st_adapter_003:out_0_data -> sysid_qsys_control_slave_agent:rdata_fifo_sink_data
wire avalon_st_adapter_003_out_0_ready; // sysid_qsys_control_slave_agent:rdata_fifo_sink_ready -> avalon_st_adapter_003:out_0_ready
wire [0:0] avalon_st_adapter_003_out_0_error; // avalon_st_adapter_003:out_0_error -> sysid_qsys_control_slave_agent:rdata_fifo_sink_error
wire intr_capturer_0_avalon_slave_0_agent_rdata_fifo_out_valid; // intr_capturer_0_avalon_slave_0_agent_rdata_fifo:out_valid -> avalon_st_adapter_004:in_0_valid
wire [33:0] intr_capturer_0_avalon_slave_0_agent_rdata_fifo_out_data; // intr_capturer_0_avalon_slave_0_agent_rdata_fifo:out_data -> avalon_st_adapter_004:in_0_data
wire intr_capturer_0_avalon_slave_0_agent_rdata_fifo_out_ready; // avalon_st_adapter_004:in_0_ready -> intr_capturer_0_avalon_slave_0_agent_rdata_fifo:out_ready
wire avalon_st_adapter_004_out_0_valid; // avalon_st_adapter_004:out_0_valid -> intr_capturer_0_avalon_slave_0_agent:rdata_fifo_sink_valid
wire [33:0] avalon_st_adapter_004_out_0_data; // avalon_st_adapter_004:out_0_data -> intr_capturer_0_avalon_slave_0_agent:rdata_fifo_sink_data
wire avalon_st_adapter_004_out_0_ready; // intr_capturer_0_avalon_slave_0_agent:rdata_fifo_sink_ready -> avalon_st_adapter_004:out_0_ready
wire [0:0] avalon_st_adapter_004_out_0_error; // avalon_st_adapter_004:out_0_error -> intr_capturer_0_avalon_slave_0_agent:rdata_fifo_sink_error
altera_merlin_master_translator #(
.AV_ADDRESS_W (32),
.AV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (32),
.UAV_BURSTCOUNT_W (3),
.USE_READ (1),
.USE_WRITE (1),
.USE_BEGINBURSTTRANSFER (0),
.USE_BEGINTRANSFER (0),
.USE_CHIPSELECT (0),
.USE_BURSTCOUNT (0),
.USE_READDATAVALID (1),
.USE_WAITREQUEST (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (1),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_LINEWRAPBURSTS (0),
.AV_REGISTERINCOMINGSIGNALS (0)
) master_non_sec_master_translator (
.clk (clk_0_clk_clk), // clk.clk
.reset (jtag_uart_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (master_non_sec_master_translator_avalon_universal_master_0_address), // avalon_universal_master_0.address
.uav_burstcount (master_non_sec_master_translator_avalon_universal_master_0_burstcount), // .burstcount
.uav_read (master_non_sec_master_translator_avalon_universal_master_0_read), // .read
.uav_write (master_non_sec_master_translator_avalon_universal_master_0_write), // .write
.uav_waitrequest (master_non_sec_master_translator_avalon_universal_master_0_waitrequest), // .waitrequest
.uav_readdatavalid (master_non_sec_master_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
.uav_byteenable (master_non_sec_master_translator_avalon_universal_master_0_byteenable), // .byteenable
.uav_readdata (master_non_sec_master_translator_avalon_universal_master_0_readdata), // .readdata
.uav_writedata (master_non_sec_master_translator_avalon_universal_master_0_writedata), // .writedata
.uav_lock (master_non_sec_master_translator_avalon_universal_master_0_lock), // .lock
.uav_debugaccess (master_non_sec_master_translator_avalon_universal_master_0_debugaccess), // .debugaccess
.av_address (master_non_sec_master_address), // avalon_anti_master_0.address
.av_waitrequest (master_non_sec_master_waitrequest), // .waitrequest
.av_byteenable (master_non_sec_master_byteenable), // .byteenable
.av_read (master_non_sec_master_read), // .read
.av_readdata (master_non_sec_master_readdata), // .readdata
.av_readdatavalid (master_non_sec_master_readdatavalid), // .readdatavalid
.av_write (master_non_sec_master_write), // .write
.av_writedata (master_non_sec_master_writedata), // .writedata
.av_burstcount (1'b1), // (terminated)
.av_beginbursttransfer (1'b0), // (terminated)
.av_begintransfer (1'b0), // (terminated)
.av_chipselect (1'b0), // (terminated)
.av_lock (1'b0), // (terminated)
.av_debugaccess (1'b0), // (terminated)
.uav_clken (), // (terminated)
.av_clken (1'b1), // (terminated)
.uav_response (2'b00), // (terminated)
.av_response (), // (terminated)
.uav_writeresponsevalid (1'b0), // (terminated)
.av_writeresponsevalid () // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (1),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (1),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (32),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (1),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) jtag_uart_avalon_jtag_slave_translator (
.clk (clk_0_clk_clk), // clk.clk
.reset (jtag_uart_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (jtag_uart_avalon_jtag_slave_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (jtag_uart_avalon_jtag_slave_agent_m0_burstcount), // .burstcount
.uav_read (jtag_uart_avalon_jtag_slave_agent_m0_read), // .read
.uav_write (jtag_uart_avalon_jtag_slave_agent_m0_write), // .write
.uav_waitrequest (jtag_uart_avalon_jtag_slave_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (jtag_uart_avalon_jtag_slave_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (jtag_uart_avalon_jtag_slave_agent_m0_byteenable), // .byteenable
.uav_readdata (jtag_uart_avalon_jtag_slave_agent_m0_readdata), // .readdata
.uav_writedata (jtag_uart_avalon_jtag_slave_agent_m0_writedata), // .writedata
.uav_lock (jtag_uart_avalon_jtag_slave_agent_m0_lock), // .lock
.uav_debugaccess (jtag_uart_avalon_jtag_slave_agent_m0_debugaccess), // .debugaccess
.av_address (jtag_uart_avalon_jtag_slave_address), // avalon_anti_slave_0.address
.av_write (jtag_uart_avalon_jtag_slave_write), // .write
.av_read (jtag_uart_avalon_jtag_slave_read), // .read
.av_readdata (jtag_uart_avalon_jtag_slave_readdata), // .readdata
.av_writedata (jtag_uart_avalon_jtag_slave_writedata), // .writedata
.av_waitrequest (jtag_uart_avalon_jtag_slave_waitrequest), // .waitrequest
.av_chipselect (jtag_uart_avalon_jtag_slave_chipselect), // .chipselect
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_byteenable (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (5),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (1),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (32),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (1),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (0),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (0),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) alt_vip_vfr_vga_avalon_slave_translator (
.clk (clk_stream_clk_clk), // clk.clk
.reset (alt_vip_vfr_vga_clock_reset_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (alt_vip_vfr_vga_avalon_slave_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (alt_vip_vfr_vga_avalon_slave_agent_m0_burstcount), // .burstcount
.uav_read (alt_vip_vfr_vga_avalon_slave_agent_m0_read), // .read
.uav_write (alt_vip_vfr_vga_avalon_slave_agent_m0_write), // .write
.uav_waitrequest (alt_vip_vfr_vga_avalon_slave_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (alt_vip_vfr_vga_avalon_slave_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (alt_vip_vfr_vga_avalon_slave_agent_m0_byteenable), // .byteenable
.uav_readdata (alt_vip_vfr_vga_avalon_slave_agent_m0_readdata), // .readdata
.uav_writedata (alt_vip_vfr_vga_avalon_slave_agent_m0_writedata), // .writedata
.uav_lock (alt_vip_vfr_vga_avalon_slave_agent_m0_lock), // .lock
.uav_debugaccess (alt_vip_vfr_vga_avalon_slave_agent_m0_debugaccess), // .debugaccess
.av_address (alt_vip_vfr_vga_avalon_slave_address), // avalon_anti_slave_0.address
.av_write (alt_vip_vfr_vga_avalon_slave_write), // .write
.av_read (alt_vip_vfr_vga_avalon_slave_read), // .read
.av_readdata (alt_vip_vfr_vga_avalon_slave_readdata), // .readdata
.av_writedata (alt_vip_vfr_vga_avalon_slave_writedata), // .writedata
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_byteenable (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_waitrequest (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_chipselect (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (4),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (32),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (0),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (0),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) ece453_0_avalon_slave_0_translator (
.clk (clk_0_clk_clk), // clk.clk
.reset (ece453_0_clock_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (ece453_0_avalon_slave_0_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (ece453_0_avalon_slave_0_agent_m0_burstcount), // .burstcount
.uav_read (ece453_0_avalon_slave_0_agent_m0_read), // .read
.uav_write (ece453_0_avalon_slave_0_agent_m0_write), // .write
.uav_waitrequest (ece453_0_avalon_slave_0_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (ece453_0_avalon_slave_0_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (ece453_0_avalon_slave_0_agent_m0_byteenable), // .byteenable
.uav_readdata (ece453_0_avalon_slave_0_agent_m0_readdata), // .readdata
.uav_writedata (ece453_0_avalon_slave_0_agent_m0_writedata), // .writedata
.uav_lock (ece453_0_avalon_slave_0_agent_m0_lock), // .lock
.uav_debugaccess (ece453_0_avalon_slave_0_agent_m0_debugaccess), // .debugaccess
.av_address (ece453_0_avalon_slave_0_address), // avalon_anti_slave_0.address
.av_write (ece453_0_avalon_slave_0_write), // .write
.av_read (ece453_0_avalon_slave_0_read), // .read
.av_readdata (ece453_0_avalon_slave_0_readdata), // .readdata
.av_writedata (ece453_0_avalon_slave_0_writedata), // .writedata
.av_byteenable (ece453_0_avalon_slave_0_byteenable), // .byteenable
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_waitrequest (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_chipselect (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (1),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (32),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (0),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) sysid_qsys_control_slave_translator (
.clk (clk_0_clk_clk), // clk.clk
.reset (jtag_uart_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (sysid_qsys_control_slave_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (sysid_qsys_control_slave_agent_m0_burstcount), // .burstcount
.uav_read (sysid_qsys_control_slave_agent_m0_read), // .read
.uav_write (sysid_qsys_control_slave_agent_m0_write), // .write
.uav_waitrequest (sysid_qsys_control_slave_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (sysid_qsys_control_slave_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (sysid_qsys_control_slave_agent_m0_byteenable), // .byteenable
.uav_readdata (sysid_qsys_control_slave_agent_m0_readdata), // .readdata
.uav_writedata (sysid_qsys_control_slave_agent_m0_writedata), // .writedata
.uav_lock (sysid_qsys_control_slave_agent_m0_lock), // .lock
.uav_debugaccess (sysid_qsys_control_slave_agent_m0_debugaccess), // .debugaccess
.av_address (sysid_qsys_control_slave_address), // avalon_anti_slave_0.address
.av_readdata (sysid_qsys_control_slave_readdata), // .readdata
.av_write (), // (terminated)
.av_read (), // (terminated)
.av_writedata (), // (terminated)
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_byteenable (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_waitrequest (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_chipselect (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (1),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (32),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (0),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) intr_capturer_0_avalon_slave_0_translator (
.clk (clk_0_clk_clk), // clk.clk
.reset (jtag_uart_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (intr_capturer_0_avalon_slave_0_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (intr_capturer_0_avalon_slave_0_agent_m0_burstcount), // .burstcount
.uav_read (intr_capturer_0_avalon_slave_0_agent_m0_read), // .read
.uav_write (intr_capturer_0_avalon_slave_0_agent_m0_write), // .write
.uav_waitrequest (intr_capturer_0_avalon_slave_0_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (intr_capturer_0_avalon_slave_0_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (intr_capturer_0_avalon_slave_0_agent_m0_byteenable), // .byteenable
.uav_readdata (intr_capturer_0_avalon_slave_0_agent_m0_readdata), // .readdata
.uav_writedata (intr_capturer_0_avalon_slave_0_agent_m0_writedata), // .writedata
.uav_lock (intr_capturer_0_avalon_slave_0_agent_m0_lock), // .lock
.uav_debugaccess (intr_capturer_0_avalon_slave_0_agent_m0_debugaccess), // .debugaccess
.av_address (intr_capturer_0_avalon_slave_0_address), // avalon_anti_slave_0.address
.av_read (intr_capturer_0_avalon_slave_0_read), // .read
.av_readdata (intr_capturer_0_avalon_slave_0_readdata), // .readdata
.av_write (), // (terminated)
.av_writedata (), // (terminated)
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_byteenable (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_waitrequest (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_chipselect (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_axi_master_ni #(
.ID_WIDTH (12),
.ADDR_WIDTH (21),
.RDATA_WIDTH (32),
.WDATA_WIDTH (32),
.ADDR_USER_WIDTH (1),
.DATA_USER_WIDTH (1),
.AXI_BURST_LENGTH_WIDTH (4),
.AXI_LOCK_WIDTH (2),
.AXI_VERSION ("AXI3"),
.WRITE_ISSUING_CAPABILITY (8),
.READ_ISSUING_CAPABILITY (8),
.PKT_BEGIN_BURST (95),
.PKT_CACHE_H (121),
.PKT_CACHE_L (118),
.PKT_ADDR_SIDEBAND_H (93),
.PKT_ADDR_SIDEBAND_L (93),
.PKT_PROTECTION_H (117),
.PKT_PROTECTION_L (115),
.PKT_BURST_SIZE_H (90),
.PKT_BURST_SIZE_L (88),
.PKT_BURST_TYPE_H (92),
.PKT_BURST_TYPE_L (91),
.PKT_RESPONSE_STATUS_L (122),
.PKT_RESPONSE_STATUS_H (123),
.PKT_BURSTWRAP_H (87),
.PKT_BURSTWRAP_L (81),
.PKT_BYTE_CNT_H (80),
.PKT_BYTE_CNT_L (74),
.PKT_ADDR_H (67),
.PKT_ADDR_L (36),
.PKT_TRANS_EXCLUSIVE (73),
.PKT_TRANS_LOCK (72),
.PKT_TRANS_COMPRESSED_READ (68),
.PKT_TRANS_POSTED (69),
.PKT_TRANS_WRITE (70),
.PKT_TRANS_READ (71),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (99),
.PKT_SRC_ID_L (97),
.PKT_DEST_ID_H (102),
.PKT_DEST_ID_L (100),
.PKT_THREAD_ID_H (114),
.PKT_THREAD_ID_L (103),
.PKT_QOS_L (96),
.PKT_QOS_H (96),
.PKT_ORI_BURST_SIZE_L (124),
.PKT_ORI_BURST_SIZE_H (126),
.PKT_DATA_SIDEBAND_H (94),
.PKT_DATA_SIDEBAND_L (94),
.ST_DATA_W (127),
.ST_CHANNEL_W (5),
.ID (0)
) hps_0_h2f_lw_axi_master_agent (
.aclk (clk_0_clk_clk), // clk.clk
.aresetn (~hps_0_h2f_lw_axi_master_agent_clk_reset_reset_bridge_in_reset_reset), // clk_reset.reset_n
.write_cp_valid (hps_0_h2f_lw_axi_master_agent_write_cp_valid), // write_cp.valid
.write_cp_data (hps_0_h2f_lw_axi_master_agent_write_cp_data), // .data
.write_cp_startofpacket (hps_0_h2f_lw_axi_master_agent_write_cp_startofpacket), // .startofpacket
.write_cp_endofpacket (hps_0_h2f_lw_axi_master_agent_write_cp_endofpacket), // .endofpacket
.write_cp_ready (hps_0_h2f_lw_axi_master_agent_write_cp_ready), // .ready
.write_rp_valid (hps_0_h2f_lw_axi_master_wr_limiter_rsp_src_valid), // write_rp.valid
.write_rp_data (hps_0_h2f_lw_axi_master_wr_limiter_rsp_src_data), // .data
.write_rp_channel (hps_0_h2f_lw_axi_master_wr_limiter_rsp_src_channel), // .channel
.write_rp_startofpacket (hps_0_h2f_lw_axi_master_wr_limiter_rsp_src_startofpacket), // .startofpacket
.write_rp_endofpacket (hps_0_h2f_lw_axi_master_wr_limiter_rsp_src_endofpacket), // .endofpacket
.write_rp_ready (hps_0_h2f_lw_axi_master_wr_limiter_rsp_src_ready), // .ready
.read_cp_valid (hps_0_h2f_lw_axi_master_agent_read_cp_valid), // read_cp.valid
.read_cp_data (hps_0_h2f_lw_axi_master_agent_read_cp_data), // .data
.read_cp_startofpacket (hps_0_h2f_lw_axi_master_agent_read_cp_startofpacket), // .startofpacket
.read_cp_endofpacket (hps_0_h2f_lw_axi_master_agent_read_cp_endofpacket), // .endofpacket
.read_cp_ready (hps_0_h2f_lw_axi_master_agent_read_cp_ready), // .ready
.read_rp_valid (hps_0_h2f_lw_axi_master_rd_limiter_rsp_src_valid), // read_rp.valid
.read_rp_data (hps_0_h2f_lw_axi_master_rd_limiter_rsp_src_data), // .data
.read_rp_channel (hps_0_h2f_lw_axi_master_rd_limiter_rsp_src_channel), // .channel
.read_rp_startofpacket (hps_0_h2f_lw_axi_master_rd_limiter_rsp_src_startofpacket), // .startofpacket
.read_rp_endofpacket (hps_0_h2f_lw_axi_master_rd_limiter_rsp_src_endofpacket), // .endofpacket
.read_rp_ready (hps_0_h2f_lw_axi_master_rd_limiter_rsp_src_ready), // .ready
.awid (hps_0_h2f_lw_axi_master_awid), // altera_axi_slave.awid
.awaddr (hps_0_h2f_lw_axi_master_awaddr), // .awaddr
.awlen (hps_0_h2f_lw_axi_master_awlen), // .awlen
.awsize (hps_0_h2f_lw_axi_master_awsize), // .awsize
.awburst (hps_0_h2f_lw_axi_master_awburst), // .awburst
.awlock (hps_0_h2f_lw_axi_master_awlock), // .awlock
.awcache (hps_0_h2f_lw_axi_master_awcache), // .awcache
.awprot (hps_0_h2f_lw_axi_master_awprot), // .awprot
.awvalid (hps_0_h2f_lw_axi_master_awvalid), // .awvalid
.awready (hps_0_h2f_lw_axi_master_awready), // .awready
.wid (hps_0_h2f_lw_axi_master_wid), // .wid
.wdata (hps_0_h2f_lw_axi_master_wdata), // .wdata
.wstrb (hps_0_h2f_lw_axi_master_wstrb), // .wstrb
.wlast (hps_0_h2f_lw_axi_master_wlast), // .wlast
.wvalid (hps_0_h2f_lw_axi_master_wvalid), // .wvalid
.wready (hps_0_h2f_lw_axi_master_wready), // .wready
.bid (hps_0_h2f_lw_axi_master_bid), // .bid
.bresp (hps_0_h2f_lw_axi_master_bresp), // .bresp
.bvalid (hps_0_h2f_lw_axi_master_bvalid), // .bvalid
.bready (hps_0_h2f_lw_axi_master_bready), // .bready
.arid (hps_0_h2f_lw_axi_master_arid), // .arid
.araddr (hps_0_h2f_lw_axi_master_araddr), // .araddr
.arlen (hps_0_h2f_lw_axi_master_arlen), // .arlen
.arsize (hps_0_h2f_lw_axi_master_arsize), // .arsize
.arburst (hps_0_h2f_lw_axi_master_arburst), // .arburst
.arlock (hps_0_h2f_lw_axi_master_arlock), // .arlock
.arcache (hps_0_h2f_lw_axi_master_arcache), // .arcache
.arprot (hps_0_h2f_lw_axi_master_arprot), // .arprot
.arvalid (hps_0_h2f_lw_axi_master_arvalid), // .arvalid
.arready (hps_0_h2f_lw_axi_master_arready), // .arready
.rid (hps_0_h2f_lw_axi_master_rid), // .rid
.rdata (hps_0_h2f_lw_axi_master_rdata), // .rdata
.rresp (hps_0_h2f_lw_axi_master_rresp), // .rresp
.rlast (hps_0_h2f_lw_axi_master_rlast), // .rlast
.rvalid (hps_0_h2f_lw_axi_master_rvalid), // .rvalid
.rready (hps_0_h2f_lw_axi_master_rready), // .rready
.awuser (1'b0), // (terminated)
.aruser (1'b0), // (terminated)
.awqos (4'b0000), // (terminated)
.arqos (4'b0000), // (terminated)
.awregion (4'b0000), // (terminated)
.arregion (4'b0000), // (terminated)
.wuser (1'b0), // (terminated)
.ruser (), // (terminated)
.buser () // (terminated)
);
altera_merlin_master_agent #(
.PKT_ORI_BURST_SIZE_H (126),
.PKT_ORI_BURST_SIZE_L (124),
.PKT_RESPONSE_STATUS_H (123),
.PKT_RESPONSE_STATUS_L (122),
.PKT_QOS_H (96),
.PKT_QOS_L (96),
.PKT_DATA_SIDEBAND_H (94),
.PKT_DATA_SIDEBAND_L (94),
.PKT_ADDR_SIDEBAND_H (93),
.PKT_ADDR_SIDEBAND_L (93),
.PKT_BURST_TYPE_H (92),
.PKT_BURST_TYPE_L (91),
.PKT_CACHE_H (121),
.PKT_CACHE_L (118),
.PKT_THREAD_ID_H (114),
.PKT_THREAD_ID_L (103),
.PKT_BURST_SIZE_H (90),
.PKT_BURST_SIZE_L (88),
.PKT_TRANS_EXCLUSIVE (73),
.PKT_TRANS_LOCK (72),
.PKT_BEGIN_BURST (95),
.PKT_PROTECTION_H (117),
.PKT_PROTECTION_L (115),
.PKT_BURSTWRAP_H (87),
.PKT_BURSTWRAP_L (81),
.PKT_BYTE_CNT_H (80),
.PKT_BYTE_CNT_L (74),
.PKT_ADDR_H (67),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (68),
.PKT_TRANS_POSTED (69),
.PKT_TRANS_WRITE (70),
.PKT_TRANS_READ (71),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (99),
.PKT_SRC_ID_L (97),
.PKT_DEST_ID_H (102),
.PKT_DEST_ID_L (100),
.ST_DATA_W (127),
.ST_CHANNEL_W (5),
.AV_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_RSP (0),
.ID (1),
.BURSTWRAP_VALUE (127),
.CACHE_VALUE (0),
.SECURE_ACCESS_BIT (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) master_non_sec_master_agent (
.clk (clk_0_clk_clk), // clk.clk
.reset (jtag_uart_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.av_address (master_non_sec_master_translator_avalon_universal_master_0_address), // av.address
.av_write (master_non_sec_master_translator_avalon_universal_master_0_write), // .write
.av_read (master_non_sec_master_translator_avalon_universal_master_0_read), // .read
.av_writedata (master_non_sec_master_translator_avalon_universal_master_0_writedata), // .writedata
.av_readdata (master_non_sec_master_translator_avalon_universal_master_0_readdata), // .readdata
.av_waitrequest (master_non_sec_master_translator_avalon_universal_master_0_waitrequest), // .waitrequest
.av_readdatavalid (master_non_sec_master_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
.av_byteenable (master_non_sec_master_translator_avalon_universal_master_0_byteenable), // .byteenable
.av_burstcount (master_non_sec_master_translator_avalon_universal_master_0_burstcount), // .burstcount
.av_debugaccess (master_non_sec_master_translator_avalon_universal_master_0_debugaccess), // .debugaccess
.av_lock (master_non_sec_master_translator_avalon_universal_master_0_lock), // .lock
.cp_valid (master_non_sec_master_agent_cp_valid), // cp.valid
.cp_data (master_non_sec_master_agent_cp_data), // .data
.cp_startofpacket (master_non_sec_master_agent_cp_startofpacket), // .startofpacket
.cp_endofpacket (master_non_sec_master_agent_cp_endofpacket), // .endofpacket
.cp_ready (master_non_sec_master_agent_cp_ready), // .ready
.rp_valid (master_non_sec_master_limiter_rsp_src_valid), // rp.valid
.rp_data (master_non_sec_master_limiter_rsp_src_data), // .data
.rp_channel (master_non_sec_master_limiter_rsp_src_channel), // .channel
.rp_startofpacket (master_non_sec_master_limiter_rsp_src_startofpacket), // .startofpacket
.rp_endofpacket (master_non_sec_master_limiter_rsp_src_endofpacket), // .endofpacket
.rp_ready (master_non_sec_master_limiter_rsp_src_ready), // .ready
.av_response (), // (terminated)
.av_writeresponsevalid () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_ORI_BURST_SIZE_H (126),
.PKT_ORI_BURST_SIZE_L (124),
.PKT_RESPONSE_STATUS_H (123),
.PKT_RESPONSE_STATUS_L (122),
.PKT_BURST_SIZE_H (90),
.PKT_BURST_SIZE_L (88),
.PKT_TRANS_LOCK (72),
.PKT_BEGIN_BURST (95),
.PKT_PROTECTION_H (117),
.PKT_PROTECTION_L (115),
.PKT_BURSTWRAP_H (87),
.PKT_BURSTWRAP_L (81),
.PKT_BYTE_CNT_H (80),
.PKT_BYTE_CNT_L (74),
.PKT_ADDR_H (67),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (68),
.PKT_TRANS_POSTED (69),
.PKT_TRANS_WRITE (70),
.PKT_TRANS_READ (71),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (99),
.PKT_SRC_ID_L (97),
.PKT_DEST_ID_H (102),
.PKT_DEST_ID_L (100),
.PKT_SYMBOL_W (8),
.ST_CHANNEL_W (5),
.ST_DATA_W (127),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (1),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.ECC_ENABLE (0)
) jtag_uart_avalon_jtag_slave_agent (
.clk (clk_0_clk_clk), // clk.clk
.reset (jtag_uart_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (jtag_uart_avalon_jtag_slave_agent_m0_address), // m0.address
.m0_burstcount (jtag_uart_avalon_jtag_slave_agent_m0_burstcount), // .burstcount
.m0_byteenable (jtag_uart_avalon_jtag_slave_agent_m0_byteenable), // .byteenable
.m0_debugaccess (jtag_uart_avalon_jtag_slave_agent_m0_debugaccess), // .debugaccess
.m0_lock (jtag_uart_avalon_jtag_slave_agent_m0_lock), // .lock
.m0_readdata (jtag_uart_avalon_jtag_slave_agent_m0_readdata), // .readdata
.m0_readdatavalid (jtag_uart_avalon_jtag_slave_agent_m0_readdatavalid), // .readdatavalid
.m0_read (jtag_uart_avalon_jtag_slave_agent_m0_read), // .read
.m0_waitrequest (jtag_uart_avalon_jtag_slave_agent_m0_waitrequest), // .waitrequest
.m0_writedata (jtag_uart_avalon_jtag_slave_agent_m0_writedata), // .writedata
.m0_write (jtag_uart_avalon_jtag_slave_agent_m0_write), // .write
.rp_endofpacket (jtag_uart_avalon_jtag_slave_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (jtag_uart_avalon_jtag_slave_agent_rp_ready), // .ready
.rp_valid (jtag_uart_avalon_jtag_slave_agent_rp_valid), // .valid
.rp_data (jtag_uart_avalon_jtag_slave_agent_rp_data), // .data
.rp_startofpacket (jtag_uart_avalon_jtag_slave_agent_rp_startofpacket), // .startofpacket
.cp_ready (jtag_uart_avalon_jtag_slave_burst_adapter_source0_ready), // cp.ready
.cp_valid (jtag_uart_avalon_jtag_slave_burst_adapter_source0_valid), // .valid
.cp_data (jtag_uart_avalon_jtag_slave_burst_adapter_source0_data), // .data
.cp_startofpacket (jtag_uart_avalon_jtag_slave_burst_adapter_source0_startofpacket), // .startofpacket
.cp_endofpacket (jtag_uart_avalon_jtag_slave_burst_adapter_source0_endofpacket), // .endofpacket
.cp_channel (jtag_uart_avalon_jtag_slave_burst_adapter_source0_channel), // .channel
.rf_sink_ready (jtag_uart_avalon_jtag_slave_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (jtag_uart_avalon_jtag_slave_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (jtag_uart_avalon_jtag_slave_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (jtag_uart_avalon_jtag_slave_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (jtag_uart_avalon_jtag_slave_agent_rsp_fifo_out_data), // .data
.rf_source_ready (jtag_uart_avalon_jtag_slave_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (jtag_uart_avalon_jtag_slave_agent_rf_source_valid), // .valid
.rf_source_startofpacket (jtag_uart_avalon_jtag_slave_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (jtag_uart_avalon_jtag_slave_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (jtag_uart_avalon_jtag_slave_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (avalon_st_adapter_out_0_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (avalon_st_adapter_out_0_valid), // .valid
.rdata_fifo_sink_data (avalon_st_adapter_out_0_data), // .data
.rdata_fifo_sink_error (avalon_st_adapter_out_0_error), // .error
.rdata_fifo_src_ready (jtag_uart_avalon_jtag_slave_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (jtag_uart_avalon_jtag_slave_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (jtag_uart_avalon_jtag_slave_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (128),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) jtag_uart_avalon_jtag_slave_agent_rsp_fifo (
.clk (clk_0_clk_clk), // clk.clk
.reset (jtag_uart_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (jtag_uart_avalon_jtag_slave_agent_rf_source_data), // in.data
.in_valid (jtag_uart_avalon_jtag_slave_agent_rf_source_valid), // .valid
.in_ready (jtag_uart_avalon_jtag_slave_agent_rf_source_ready), // .ready
.in_startofpacket (jtag_uart_avalon_jtag_slave_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (jtag_uart_avalon_jtag_slave_agent_rf_source_endofpacket), // .endofpacket
.out_data (jtag_uart_avalon_jtag_slave_agent_rsp_fifo_out_data), // out.data
.out_valid (jtag_uart_avalon_jtag_slave_agent_rsp_fifo_out_valid), // .valid
.out_ready (jtag_uart_avalon_jtag_slave_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (jtag_uart_avalon_jtag_slave_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (jtag_uart_avalon_jtag_slave_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (34),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (0),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (0),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) jtag_uart_avalon_jtag_slave_agent_rdata_fifo (
.clk (clk_0_clk_clk), // clk.clk
.reset (jtag_uart_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (jtag_uart_avalon_jtag_slave_agent_rdata_fifo_src_data), // in.data
.in_valid (jtag_uart_avalon_jtag_slave_agent_rdata_fifo_src_valid), // .valid
.in_ready (jtag_uart_avalon_jtag_slave_agent_rdata_fifo_src_ready), // .ready
.out_data (jtag_uart_avalon_jtag_slave_agent_rdata_fifo_out_data), // out.data
.out_valid (jtag_uart_avalon_jtag_slave_agent_rdata_fifo_out_valid), // .valid
.out_ready (jtag_uart_avalon_jtag_slave_agent_rdata_fifo_out_ready), // .ready
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_startofpacket (1'b0), // (terminated)
.in_endofpacket (1'b0), // (terminated)
.out_startofpacket (), // (terminated)
.out_endofpacket (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_ORI_BURST_SIZE_H (126),
.PKT_ORI_BURST_SIZE_L (124),
.PKT_RESPONSE_STATUS_H (123),
.PKT_RESPONSE_STATUS_L (122),
.PKT_BURST_SIZE_H (90),
.PKT_BURST_SIZE_L (88),
.PKT_TRANS_LOCK (72),
.PKT_BEGIN_BURST (95),
.PKT_PROTECTION_H (117),
.PKT_PROTECTION_L (115),
.PKT_BURSTWRAP_H (87),
.PKT_BURSTWRAP_L (81),
.PKT_BYTE_CNT_H (80),
.PKT_BYTE_CNT_L (74),
.PKT_ADDR_H (67),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (68),
.PKT_TRANS_POSTED (69),
.PKT_TRANS_WRITE (70),
.PKT_TRANS_READ (71),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (99),
.PKT_SRC_ID_L (97),
.PKT_DEST_ID_H (102),
.PKT_DEST_ID_L (100),
.PKT_SYMBOL_W (8),
.ST_CHANNEL_W (5),
.ST_DATA_W (127),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (1),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.ECC_ENABLE (0)
) alt_vip_vfr_vga_avalon_slave_agent (
.clk (clk_stream_clk_clk), // clk.clk
.reset (alt_vip_vfr_vga_clock_reset_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (alt_vip_vfr_vga_avalon_slave_agent_m0_address), // m0.address
.m0_burstcount (alt_vip_vfr_vga_avalon_slave_agent_m0_burstcount), // .burstcount
.m0_byteenable (alt_vip_vfr_vga_avalon_slave_agent_m0_byteenable), // .byteenable
.m0_debugaccess (alt_vip_vfr_vga_avalon_slave_agent_m0_debugaccess), // .debugaccess
.m0_lock (alt_vip_vfr_vga_avalon_slave_agent_m0_lock), // .lock
.m0_readdata (alt_vip_vfr_vga_avalon_slave_agent_m0_readdata), // .readdata
.m0_readdatavalid (alt_vip_vfr_vga_avalon_slave_agent_m0_readdatavalid), // .readdatavalid
.m0_read (alt_vip_vfr_vga_avalon_slave_agent_m0_read), // .read
.m0_waitrequest (alt_vip_vfr_vga_avalon_slave_agent_m0_waitrequest), // .waitrequest
.m0_writedata (alt_vip_vfr_vga_avalon_slave_agent_m0_writedata), // .writedata
.m0_write (alt_vip_vfr_vga_avalon_slave_agent_m0_write), // .write
.rp_endofpacket (alt_vip_vfr_vga_avalon_slave_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (alt_vip_vfr_vga_avalon_slave_agent_rp_ready), // .ready
.rp_valid (alt_vip_vfr_vga_avalon_slave_agent_rp_valid), // .valid
.rp_data (alt_vip_vfr_vga_avalon_slave_agent_rp_data), // .data
.rp_startofpacket (alt_vip_vfr_vga_avalon_slave_agent_rp_startofpacket), // .startofpacket
.cp_ready (alt_vip_vfr_vga_avalon_slave_burst_adapter_source0_ready), // cp.ready
.cp_valid (alt_vip_vfr_vga_avalon_slave_burst_adapter_source0_valid), // .valid
.cp_data (alt_vip_vfr_vga_avalon_slave_burst_adapter_source0_data), // .data
.cp_startofpacket (alt_vip_vfr_vga_avalon_slave_burst_adapter_source0_startofpacket), // .startofpacket
.cp_endofpacket (alt_vip_vfr_vga_avalon_slave_burst_adapter_source0_endofpacket), // .endofpacket
.cp_channel (alt_vip_vfr_vga_avalon_slave_burst_adapter_source0_channel), // .channel
.rf_sink_ready (alt_vip_vfr_vga_avalon_slave_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (alt_vip_vfr_vga_avalon_slave_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (alt_vip_vfr_vga_avalon_slave_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (alt_vip_vfr_vga_avalon_slave_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (alt_vip_vfr_vga_avalon_slave_agent_rsp_fifo_out_data), // .data
.rf_source_ready (alt_vip_vfr_vga_avalon_slave_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (alt_vip_vfr_vga_avalon_slave_agent_rf_source_valid), // .valid
.rf_source_startofpacket (alt_vip_vfr_vga_avalon_slave_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (alt_vip_vfr_vga_avalon_slave_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (alt_vip_vfr_vga_avalon_slave_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (avalon_st_adapter_001_out_0_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (avalon_st_adapter_001_out_0_valid), // .valid
.rdata_fifo_sink_data (avalon_st_adapter_001_out_0_data), // .data
.rdata_fifo_sink_error (avalon_st_adapter_001_out_0_error), // .error
.rdata_fifo_src_ready (alt_vip_vfr_vga_avalon_slave_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (alt_vip_vfr_vga_avalon_slave_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (alt_vip_vfr_vga_avalon_slave_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (128),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) alt_vip_vfr_vga_avalon_slave_agent_rsp_fifo (
.clk (clk_stream_clk_clk), // clk.clk
.reset (alt_vip_vfr_vga_clock_reset_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (alt_vip_vfr_vga_avalon_slave_agent_rf_source_data), // in.data
.in_valid (alt_vip_vfr_vga_avalon_slave_agent_rf_source_valid), // .valid
.in_ready (alt_vip_vfr_vga_avalon_slave_agent_rf_source_ready), // .ready
.in_startofpacket (alt_vip_vfr_vga_avalon_slave_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (alt_vip_vfr_vga_avalon_slave_agent_rf_source_endofpacket), // .endofpacket
.out_data (alt_vip_vfr_vga_avalon_slave_agent_rsp_fifo_out_data), // out.data
.out_valid (alt_vip_vfr_vga_avalon_slave_agent_rsp_fifo_out_valid), // .valid
.out_ready (alt_vip_vfr_vga_avalon_slave_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (alt_vip_vfr_vga_avalon_slave_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (alt_vip_vfr_vga_avalon_slave_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (34),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (0),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (0),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) alt_vip_vfr_vga_avalon_slave_agent_rdata_fifo (
.clk (clk_stream_clk_clk), // clk.clk
.reset (alt_vip_vfr_vga_clock_reset_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (alt_vip_vfr_vga_avalon_slave_agent_rdata_fifo_src_data), // in.data
.in_valid (alt_vip_vfr_vga_avalon_slave_agent_rdata_fifo_src_valid), // .valid
.in_ready (alt_vip_vfr_vga_avalon_slave_agent_rdata_fifo_src_ready), // .ready
.out_data (alt_vip_vfr_vga_avalon_slave_agent_rdata_fifo_out_data), // out.data
.out_valid (alt_vip_vfr_vga_avalon_slave_agent_rdata_fifo_out_valid), // .valid
.out_ready (alt_vip_vfr_vga_avalon_slave_agent_rdata_fifo_out_ready), // .ready
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_startofpacket (1'b0), // (terminated)
.in_endofpacket (1'b0), // (terminated)
.out_startofpacket (), // (terminated)
.out_endofpacket (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_ORI_BURST_SIZE_H (126),
.PKT_ORI_BURST_SIZE_L (124),
.PKT_RESPONSE_STATUS_H (123),
.PKT_RESPONSE_STATUS_L (122),
.PKT_BURST_SIZE_H (90),
.PKT_BURST_SIZE_L (88),
.PKT_TRANS_LOCK (72),
.PKT_BEGIN_BURST (95),
.PKT_PROTECTION_H (117),
.PKT_PROTECTION_L (115),
.PKT_BURSTWRAP_H (87),
.PKT_BURSTWRAP_L (81),
.PKT_BYTE_CNT_H (80),
.PKT_BYTE_CNT_L (74),
.PKT_ADDR_H (67),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (68),
.PKT_TRANS_POSTED (69),
.PKT_TRANS_WRITE (70),
.PKT_TRANS_READ (71),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (99),
.PKT_SRC_ID_L (97),
.PKT_DEST_ID_H (102),
.PKT_DEST_ID_L (100),
.PKT_SYMBOL_W (8),
.ST_CHANNEL_W (5),
.ST_DATA_W (127),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (1),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.ECC_ENABLE (0)
) ece453_0_avalon_slave_0_agent (
.clk (clk_0_clk_clk), // clk.clk
.reset (ece453_0_clock_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (ece453_0_avalon_slave_0_agent_m0_address), // m0.address
.m0_burstcount (ece453_0_avalon_slave_0_agent_m0_burstcount), // .burstcount
.m0_byteenable (ece453_0_avalon_slave_0_agent_m0_byteenable), // .byteenable
.m0_debugaccess (ece453_0_avalon_slave_0_agent_m0_debugaccess), // .debugaccess
.m0_lock (ece453_0_avalon_slave_0_agent_m0_lock), // .lock
.m0_readdata (ece453_0_avalon_slave_0_agent_m0_readdata), // .readdata
.m0_readdatavalid (ece453_0_avalon_slave_0_agent_m0_readdatavalid), // .readdatavalid
.m0_read (ece453_0_avalon_slave_0_agent_m0_read), // .read
.m0_waitrequest (ece453_0_avalon_slave_0_agent_m0_waitrequest), // .waitrequest
.m0_writedata (ece453_0_avalon_slave_0_agent_m0_writedata), // .writedata
.m0_write (ece453_0_avalon_slave_0_agent_m0_write), // .write
.rp_endofpacket (ece453_0_avalon_slave_0_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (ece453_0_avalon_slave_0_agent_rp_ready), // .ready
.rp_valid (ece453_0_avalon_slave_0_agent_rp_valid), // .valid
.rp_data (ece453_0_avalon_slave_0_agent_rp_data), // .data
.rp_startofpacket (ece453_0_avalon_slave_0_agent_rp_startofpacket), // .startofpacket
.cp_ready (ece453_0_avalon_slave_0_burst_adapter_source0_ready), // cp.ready
.cp_valid (ece453_0_avalon_slave_0_burst_adapter_source0_valid), // .valid
.cp_data (ece453_0_avalon_slave_0_burst_adapter_source0_data), // .data
.cp_startofpacket (ece453_0_avalon_slave_0_burst_adapter_source0_startofpacket), // .startofpacket
.cp_endofpacket (ece453_0_avalon_slave_0_burst_adapter_source0_endofpacket), // .endofpacket
.cp_channel (ece453_0_avalon_slave_0_burst_adapter_source0_channel), // .channel
.rf_sink_ready (ece453_0_avalon_slave_0_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (ece453_0_avalon_slave_0_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (ece453_0_avalon_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (ece453_0_avalon_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (ece453_0_avalon_slave_0_agent_rsp_fifo_out_data), // .data
.rf_source_ready (ece453_0_avalon_slave_0_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (ece453_0_avalon_slave_0_agent_rf_source_valid), // .valid
.rf_source_startofpacket (ece453_0_avalon_slave_0_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (ece453_0_avalon_slave_0_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (ece453_0_avalon_slave_0_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (avalon_st_adapter_002_out_0_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (avalon_st_adapter_002_out_0_valid), // .valid
.rdata_fifo_sink_data (avalon_st_adapter_002_out_0_data), // .data
.rdata_fifo_sink_error (avalon_st_adapter_002_out_0_error), // .error
.rdata_fifo_src_ready (ece453_0_avalon_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (ece453_0_avalon_slave_0_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (ece453_0_avalon_slave_0_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (128),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) ece453_0_avalon_slave_0_agent_rsp_fifo (
.clk (clk_0_clk_clk), // clk.clk
.reset (ece453_0_clock_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (ece453_0_avalon_slave_0_agent_rf_source_data), // in.data
.in_valid (ece453_0_avalon_slave_0_agent_rf_source_valid), // .valid
.in_ready (ece453_0_avalon_slave_0_agent_rf_source_ready), // .ready
.in_startofpacket (ece453_0_avalon_slave_0_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (ece453_0_avalon_slave_0_agent_rf_source_endofpacket), // .endofpacket
.out_data (ece453_0_avalon_slave_0_agent_rsp_fifo_out_data), // out.data
.out_valid (ece453_0_avalon_slave_0_agent_rsp_fifo_out_valid), // .valid
.out_ready (ece453_0_avalon_slave_0_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (ece453_0_avalon_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (ece453_0_avalon_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (34),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (0),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (0),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) ece453_0_avalon_slave_0_agent_rdata_fifo (
.clk (clk_0_clk_clk), // clk.clk
.reset (ece453_0_clock_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (ece453_0_avalon_slave_0_agent_rdata_fifo_src_data), // in.data
.in_valid (ece453_0_avalon_slave_0_agent_rdata_fifo_src_valid), // .valid
.in_ready (ece453_0_avalon_slave_0_agent_rdata_fifo_src_ready), // .ready
.out_data (ece453_0_avalon_slave_0_agent_rdata_fifo_out_data), // out.data
.out_valid (ece453_0_avalon_slave_0_agent_rdata_fifo_out_valid), // .valid
.out_ready (ece453_0_avalon_slave_0_agent_rdata_fifo_out_ready), // .ready
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_startofpacket (1'b0), // (terminated)
.in_endofpacket (1'b0), // (terminated)
.out_startofpacket (), // (terminated)
.out_endofpacket (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_ORI_BURST_SIZE_H (126),
.PKT_ORI_BURST_SIZE_L (124),
.PKT_RESPONSE_STATUS_H (123),
.PKT_RESPONSE_STATUS_L (122),
.PKT_BURST_SIZE_H (90),
.PKT_BURST_SIZE_L (88),
.PKT_TRANS_LOCK (72),
.PKT_BEGIN_BURST (95),
.PKT_PROTECTION_H (117),
.PKT_PROTECTION_L (115),
.PKT_BURSTWRAP_H (87),
.PKT_BURSTWRAP_L (81),
.PKT_BYTE_CNT_H (80),
.PKT_BYTE_CNT_L (74),
.PKT_ADDR_H (67),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (68),
.PKT_TRANS_POSTED (69),
.PKT_TRANS_WRITE (70),
.PKT_TRANS_READ (71),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (99),
.PKT_SRC_ID_L (97),
.PKT_DEST_ID_H (102),
.PKT_DEST_ID_L (100),
.PKT_SYMBOL_W (8),
.ST_CHANNEL_W (5),
.ST_DATA_W (127),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (1),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.ECC_ENABLE (0)
) sysid_qsys_control_slave_agent (
.clk (clk_0_clk_clk), // clk.clk
.reset (jtag_uart_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (sysid_qsys_control_slave_agent_m0_address), // m0.address
.m0_burstcount (sysid_qsys_control_slave_agent_m0_burstcount), // .burstcount
.m0_byteenable (sysid_qsys_control_slave_agent_m0_byteenable), // .byteenable
.m0_debugaccess (sysid_qsys_control_slave_agent_m0_debugaccess), // .debugaccess
.m0_lock (sysid_qsys_control_slave_agent_m0_lock), // .lock
.m0_readdata (sysid_qsys_control_slave_agent_m0_readdata), // .readdata
.m0_readdatavalid (sysid_qsys_control_slave_agent_m0_readdatavalid), // .readdatavalid
.m0_read (sysid_qsys_control_slave_agent_m0_read), // .read
.m0_waitrequest (sysid_qsys_control_slave_agent_m0_waitrequest), // .waitrequest
.m0_writedata (sysid_qsys_control_slave_agent_m0_writedata), // .writedata
.m0_write (sysid_qsys_control_slave_agent_m0_write), // .write
.rp_endofpacket (sysid_qsys_control_slave_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (sysid_qsys_control_slave_agent_rp_ready), // .ready
.rp_valid (sysid_qsys_control_slave_agent_rp_valid), // .valid
.rp_data (sysid_qsys_control_slave_agent_rp_data), // .data
.rp_startofpacket (sysid_qsys_control_slave_agent_rp_startofpacket), // .startofpacket
.cp_ready (sysid_qsys_control_slave_burst_adapter_source0_ready), // cp.ready
.cp_valid (sysid_qsys_control_slave_burst_adapter_source0_valid), // .valid
.cp_data (sysid_qsys_control_slave_burst_adapter_source0_data), // .data
.cp_startofpacket (sysid_qsys_control_slave_burst_adapter_source0_startofpacket), // .startofpacket
.cp_endofpacket (sysid_qsys_control_slave_burst_adapter_source0_endofpacket), // .endofpacket
.cp_channel (sysid_qsys_control_slave_burst_adapter_source0_channel), // .channel
.rf_sink_ready (sysid_qsys_control_slave_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (sysid_qsys_control_slave_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (sysid_qsys_control_slave_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (sysid_qsys_control_slave_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (sysid_qsys_control_slave_agent_rsp_fifo_out_data), // .data
.rf_source_ready (sysid_qsys_control_slave_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (sysid_qsys_control_slave_agent_rf_source_valid), // .valid
.rf_source_startofpacket (sysid_qsys_control_slave_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (sysid_qsys_control_slave_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (sysid_qsys_control_slave_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (avalon_st_adapter_003_out_0_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (avalon_st_adapter_003_out_0_valid), // .valid
.rdata_fifo_sink_data (avalon_st_adapter_003_out_0_data), // .data
.rdata_fifo_sink_error (avalon_st_adapter_003_out_0_error), // .error
.rdata_fifo_src_ready (sysid_qsys_control_slave_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (sysid_qsys_control_slave_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (sysid_qsys_control_slave_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (128),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) sysid_qsys_control_slave_agent_rsp_fifo (
.clk (clk_0_clk_clk), // clk.clk
.reset (jtag_uart_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (sysid_qsys_control_slave_agent_rf_source_data), // in.data
.in_valid (sysid_qsys_control_slave_agent_rf_source_valid), // .valid
.in_ready (sysid_qsys_control_slave_agent_rf_source_ready), // .ready
.in_startofpacket (sysid_qsys_control_slave_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (sysid_qsys_control_slave_agent_rf_source_endofpacket), // .endofpacket
.out_data (sysid_qsys_control_slave_agent_rsp_fifo_out_data), // out.data
.out_valid (sysid_qsys_control_slave_agent_rsp_fifo_out_valid), // .valid
.out_ready (sysid_qsys_control_slave_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (sysid_qsys_control_slave_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (sysid_qsys_control_slave_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (34),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (0),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (0),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) sysid_qsys_control_slave_agent_rdata_fifo (
.clk (clk_0_clk_clk), // clk.clk
.reset (jtag_uart_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (sysid_qsys_control_slave_agent_rdata_fifo_src_data), // in.data
.in_valid (sysid_qsys_control_slave_agent_rdata_fifo_src_valid), // .valid
.in_ready (sysid_qsys_control_slave_agent_rdata_fifo_src_ready), // .ready
.out_data (sysid_qsys_control_slave_agent_rdata_fifo_out_data), // out.data
.out_valid (sysid_qsys_control_slave_agent_rdata_fifo_out_valid), // .valid
.out_ready (sysid_qsys_control_slave_agent_rdata_fifo_out_ready), // .ready
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_startofpacket (1'b0), // (terminated)
.in_endofpacket (1'b0), // (terminated)
.out_startofpacket (), // (terminated)
.out_endofpacket (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_ORI_BURST_SIZE_H (126),
.PKT_ORI_BURST_SIZE_L (124),
.PKT_RESPONSE_STATUS_H (123),
.PKT_RESPONSE_STATUS_L (122),
.PKT_BURST_SIZE_H (90),
.PKT_BURST_SIZE_L (88),
.PKT_TRANS_LOCK (72),
.PKT_BEGIN_BURST (95),
.PKT_PROTECTION_H (117),
.PKT_PROTECTION_L (115),
.PKT_BURSTWRAP_H (87),
.PKT_BURSTWRAP_L (81),
.PKT_BYTE_CNT_H (80),
.PKT_BYTE_CNT_L (74),
.PKT_ADDR_H (67),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (68),
.PKT_TRANS_POSTED (69),
.PKT_TRANS_WRITE (70),
.PKT_TRANS_READ (71),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (99),
.PKT_SRC_ID_L (97),
.PKT_DEST_ID_H (102),
.PKT_DEST_ID_L (100),
.PKT_SYMBOL_W (8),
.ST_CHANNEL_W (5),
.ST_DATA_W (127),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (1),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.ECC_ENABLE (0)
) intr_capturer_0_avalon_slave_0_agent (
.clk (clk_0_clk_clk), // clk.clk
.reset (jtag_uart_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (intr_capturer_0_avalon_slave_0_agent_m0_address), // m0.address
.m0_burstcount (intr_capturer_0_avalon_slave_0_agent_m0_burstcount), // .burstcount
.m0_byteenable (intr_capturer_0_avalon_slave_0_agent_m0_byteenable), // .byteenable
.m0_debugaccess (intr_capturer_0_avalon_slave_0_agent_m0_debugaccess), // .debugaccess
.m0_lock (intr_capturer_0_avalon_slave_0_agent_m0_lock), // .lock
.m0_readdata (intr_capturer_0_avalon_slave_0_agent_m0_readdata), // .readdata
.m0_readdatavalid (intr_capturer_0_avalon_slave_0_agent_m0_readdatavalid), // .readdatavalid
.m0_read (intr_capturer_0_avalon_slave_0_agent_m0_read), // .read
.m0_waitrequest (intr_capturer_0_avalon_slave_0_agent_m0_waitrequest), // .waitrequest
.m0_writedata (intr_capturer_0_avalon_slave_0_agent_m0_writedata), // .writedata
.m0_write (intr_capturer_0_avalon_slave_0_agent_m0_write), // .write
.rp_endofpacket (intr_capturer_0_avalon_slave_0_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (intr_capturer_0_avalon_slave_0_agent_rp_ready), // .ready
.rp_valid (intr_capturer_0_avalon_slave_0_agent_rp_valid), // .valid
.rp_data (intr_capturer_0_avalon_slave_0_agent_rp_data), // .data
.rp_startofpacket (intr_capturer_0_avalon_slave_0_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_mux_004_src_ready), // cp.ready
.cp_valid (cmd_mux_004_src_valid), // .valid
.cp_data (cmd_mux_004_src_data), // .data
.cp_startofpacket (cmd_mux_004_src_startofpacket), // .startofpacket
.cp_endofpacket (cmd_mux_004_src_endofpacket), // .endofpacket
.cp_channel (cmd_mux_004_src_channel), // .channel
.rf_sink_ready (intr_capturer_0_avalon_slave_0_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (intr_capturer_0_avalon_slave_0_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (intr_capturer_0_avalon_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (intr_capturer_0_avalon_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (intr_capturer_0_avalon_slave_0_agent_rsp_fifo_out_data), // .data
.rf_source_ready (intr_capturer_0_avalon_slave_0_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (intr_capturer_0_avalon_slave_0_agent_rf_source_valid), // .valid
.rf_source_startofpacket (intr_capturer_0_avalon_slave_0_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (intr_capturer_0_avalon_slave_0_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (intr_capturer_0_avalon_slave_0_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (avalon_st_adapter_004_out_0_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (avalon_st_adapter_004_out_0_valid), // .valid
.rdata_fifo_sink_data (avalon_st_adapter_004_out_0_data), // .data
.rdata_fifo_sink_error (avalon_st_adapter_004_out_0_error), // .error
.rdata_fifo_src_ready (intr_capturer_0_avalon_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (intr_capturer_0_avalon_slave_0_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (intr_capturer_0_avalon_slave_0_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (128),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) intr_capturer_0_avalon_slave_0_agent_rsp_fifo (
.clk (clk_0_clk_clk), // clk.clk
.reset (jtag_uart_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (intr_capturer_0_avalon_slave_0_agent_rf_source_data), // in.data
.in_valid (intr_capturer_0_avalon_slave_0_agent_rf_source_valid), // .valid
.in_ready (intr_capturer_0_avalon_slave_0_agent_rf_source_ready), // .ready
.in_startofpacket (intr_capturer_0_avalon_slave_0_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (intr_capturer_0_avalon_slave_0_agent_rf_source_endofpacket), // .endofpacket
.out_data (intr_capturer_0_avalon_slave_0_agent_rsp_fifo_out_data), // out.data
.out_valid (intr_capturer_0_avalon_slave_0_agent_rsp_fifo_out_valid), // .valid
.out_ready (intr_capturer_0_avalon_slave_0_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (intr_capturer_0_avalon_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (intr_capturer_0_avalon_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (34),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (0),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (0),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) intr_capturer_0_avalon_slave_0_agent_rdata_fifo (
.clk (clk_0_clk_clk), // clk.clk
.reset (jtag_uart_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (intr_capturer_0_avalon_slave_0_agent_rdata_fifo_src_data), // in.data
.in_valid (intr_capturer_0_avalon_slave_0_agent_rdata_fifo_src_valid), // .valid
.in_ready (intr_capturer_0_avalon_slave_0_agent_rdata_fifo_src_ready), // .ready
.out_data (intr_capturer_0_avalon_slave_0_agent_rdata_fifo_out_data), // out.data
.out_valid (intr_capturer_0_avalon_slave_0_agent_rdata_fifo_out_valid), // .valid
.out_ready (intr_capturer_0_avalon_slave_0_agent_rdata_fifo_out_ready), // .ready
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_startofpacket (1'b0), // (terminated)
.in_endofpacket (1'b0), // (terminated)
.out_startofpacket (), // (terminated)
.out_endofpacket (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
soc_system_mm_interconnect_1_router router (
.sink_ready (hps_0_h2f_lw_axi_master_agent_write_cp_ready), // sink.ready
.sink_valid (hps_0_h2f_lw_axi_master_agent_write_cp_valid), // .valid
.sink_data (hps_0_h2f_lw_axi_master_agent_write_cp_data), // .data
.sink_startofpacket (hps_0_h2f_lw_axi_master_agent_write_cp_startofpacket), // .startofpacket
.sink_endofpacket (hps_0_h2f_lw_axi_master_agent_write_cp_endofpacket), // .endofpacket
.clk (clk_0_clk_clk), // clk.clk
.reset (hps_0_h2f_lw_axi_master_agent_clk_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_src_ready), // src.ready
.src_valid (router_src_valid), // .valid
.src_data (router_src_data), // .data
.src_channel (router_src_channel), // .channel
.src_startofpacket (router_src_startofpacket), // .startofpacket
.src_endofpacket (router_src_endofpacket) // .endofpacket
);
soc_system_mm_interconnect_1_router router_001 (
.sink_ready (hps_0_h2f_lw_axi_master_agent_read_cp_ready), // sink.ready
.sink_valid (hps_0_h2f_lw_axi_master_agent_read_cp_valid), // .valid
.sink_data (hps_0_h2f_lw_axi_master_agent_read_cp_data), // .data
.sink_startofpacket (hps_0_h2f_lw_axi_master_agent_read_cp_startofpacket), // .startofpacket
.sink_endofpacket (hps_0_h2f_lw_axi_master_agent_read_cp_endofpacket), // .endofpacket
.clk (clk_0_clk_clk), // clk.clk
.reset (hps_0_h2f_lw_axi_master_agent_clk_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_001_src_ready), // src.ready
.src_valid (router_001_src_valid), // .valid
.src_data (router_001_src_data), // .data
.src_channel (router_001_src_channel), // .channel
.src_startofpacket (router_001_src_startofpacket), // .startofpacket
.src_endofpacket (router_001_src_endofpacket) // .endofpacket
);
soc_system_mm_interconnect_1_router_002 router_002 (
.sink_ready (master_non_sec_master_agent_cp_ready), // sink.ready
.sink_valid (master_non_sec_master_agent_cp_valid), // .valid
.sink_data (master_non_sec_master_agent_cp_data), // .data
.sink_startofpacket (master_non_sec_master_agent_cp_startofpacket), // .startofpacket
.sink_endofpacket (master_non_sec_master_agent_cp_endofpacket), // .endofpacket
.clk (clk_0_clk_clk), // clk.clk
.reset (jtag_uart_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_002_src_ready), // src.ready
.src_valid (router_002_src_valid), // .valid
.src_data (router_002_src_data), // .data
.src_channel (router_002_src_channel), // .channel
.src_startofpacket (router_002_src_startofpacket), // .startofpacket
.src_endofpacket (router_002_src_endofpacket) // .endofpacket
);
soc_system_mm_interconnect_1_router_003 router_003 (
.sink_ready (jtag_uart_avalon_jtag_slave_agent_rp_ready), // sink.ready
.sink_valid (jtag_uart_avalon_jtag_slave_agent_rp_valid), // .valid
.sink_data (jtag_uart_avalon_jtag_slave_agent_rp_data), // .data
.sink_startofpacket (jtag_uart_avalon_jtag_slave_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (jtag_uart_avalon_jtag_slave_agent_rp_endofpacket), // .endofpacket
.clk (clk_0_clk_clk), // clk.clk
.reset (jtag_uart_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_003_src_ready), // src.ready
.src_valid (router_003_src_valid), // .valid
.src_data (router_003_src_data), // .data
.src_channel (router_003_src_channel), // .channel
.src_startofpacket (router_003_src_startofpacket), // .startofpacket
.src_endofpacket (router_003_src_endofpacket) // .endofpacket
);
soc_system_mm_interconnect_1_router_003 router_004 (
.sink_ready (alt_vip_vfr_vga_avalon_slave_agent_rp_ready), // sink.ready
.sink_valid (alt_vip_vfr_vga_avalon_slave_agent_rp_valid), // .valid
.sink_data (alt_vip_vfr_vga_avalon_slave_agent_rp_data), // .data
.sink_startofpacket (alt_vip_vfr_vga_avalon_slave_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (alt_vip_vfr_vga_avalon_slave_agent_rp_endofpacket), // .endofpacket
.clk (clk_stream_clk_clk), // clk.clk
.reset (alt_vip_vfr_vga_clock_reset_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_004_src_ready), // src.ready
.src_valid (router_004_src_valid), // .valid
.src_data (router_004_src_data), // .data
.src_channel (router_004_src_channel), // .channel
.src_startofpacket (router_004_src_startofpacket), // .startofpacket
.src_endofpacket (router_004_src_endofpacket) // .endofpacket
);
soc_system_mm_interconnect_1_router_005 router_005 (
.sink_ready (ece453_0_avalon_slave_0_agent_rp_ready), // sink.ready
.sink_valid (ece453_0_avalon_slave_0_agent_rp_valid), // .valid
.sink_data (ece453_0_avalon_slave_0_agent_rp_data), // .data
.sink_startofpacket (ece453_0_avalon_slave_0_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (ece453_0_avalon_slave_0_agent_rp_endofpacket), // .endofpacket
.clk (clk_0_clk_clk), // clk.clk
.reset (ece453_0_clock_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_005_src_ready), // src.ready
.src_valid (router_005_src_valid), // .valid
.src_data (router_005_src_data), // .data
.src_channel (router_005_src_channel), // .channel
.src_startofpacket (router_005_src_startofpacket), // .startofpacket
.src_endofpacket (router_005_src_endofpacket) // .endofpacket
);
soc_system_mm_interconnect_1_router_003 router_006 (
.sink_ready (sysid_qsys_control_slave_agent_rp_ready), // sink.ready
.sink_valid (sysid_qsys_control_slave_agent_rp_valid), // .valid
.sink_data (sysid_qsys_control_slave_agent_rp_data), // .data
.sink_startofpacket (sysid_qsys_control_slave_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (sysid_qsys_control_slave_agent_rp_endofpacket), // .endofpacket
.clk (clk_0_clk_clk), // clk.clk
.reset (jtag_uart_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_006_src_ready), // src.ready
.src_valid (router_006_src_valid), // .valid
.src_data (router_006_src_data), // .data
.src_channel (router_006_src_channel), // .channel
.src_startofpacket (router_006_src_startofpacket), // .startofpacket
.src_endofpacket (router_006_src_endofpacket) // .endofpacket
);
soc_system_mm_interconnect_1_router_007 router_007 (
.sink_ready (intr_capturer_0_avalon_slave_0_agent_rp_ready), // sink.ready
.sink_valid (intr_capturer_0_avalon_slave_0_agent_rp_valid), // .valid
.sink_data (intr_capturer_0_avalon_slave_0_agent_rp_data), // .data
.sink_startofpacket (intr_capturer_0_avalon_slave_0_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (intr_capturer_0_avalon_slave_0_agent_rp_endofpacket), // .endofpacket
.clk (clk_0_clk_clk), // clk.clk
.reset (jtag_uart_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_007_src_ready), // src.ready
.src_valid (router_007_src_valid), // .valid
.src_data (router_007_src_data), // .data
.src_channel (router_007_src_channel), // .channel
.src_startofpacket (router_007_src_startofpacket), // .startofpacket
.src_endofpacket (router_007_src_endofpacket) // .endofpacket
);
altera_merlin_traffic_limiter #(
.PKT_DEST_ID_H (102),
.PKT_DEST_ID_L (100),
.PKT_SRC_ID_H (99),
.PKT_SRC_ID_L (97),
.PKT_BYTE_CNT_H (80),
.PKT_BYTE_CNT_L (74),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_TRANS_POSTED (69),
.PKT_TRANS_WRITE (70),
.MAX_OUTSTANDING_RESPONSES (7),
.PIPELINED (0),
.ST_DATA_W (127),
.ST_CHANNEL_W (5),
.VALID_WIDTH (5),
.ENFORCE_ORDER (1),
.PREVENT_HAZARDS (0),
.SUPPORTS_POSTED_WRITES (1),
.SUPPORTS_NONPOSTED_WRITES (0),
.REORDER (0)
) hps_0_h2f_lw_axi_master_wr_limiter (
.clk (clk_0_clk_clk), // clk.clk
.reset (hps_0_h2f_lw_axi_master_agent_clk_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.cmd_sink_ready (router_src_ready), // cmd_sink.ready
.cmd_sink_valid (router_src_valid), // .valid
.cmd_sink_data (router_src_data), // .data
.cmd_sink_channel (router_src_channel), // .channel
.cmd_sink_startofpacket (router_src_startofpacket), // .startofpacket
.cmd_sink_endofpacket (router_src_endofpacket), // .endofpacket
.cmd_src_ready (hps_0_h2f_lw_axi_master_wr_limiter_cmd_src_ready), // cmd_src.ready
.cmd_src_data (hps_0_h2f_lw_axi_master_wr_limiter_cmd_src_data), // .data
.cmd_src_channel (hps_0_h2f_lw_axi_master_wr_limiter_cmd_src_channel), // .channel
.cmd_src_startofpacket (hps_0_h2f_lw_axi_master_wr_limiter_cmd_src_startofpacket), // .startofpacket
.cmd_src_endofpacket (hps_0_h2f_lw_axi_master_wr_limiter_cmd_src_endofpacket), // .endofpacket
.rsp_sink_ready (rsp_mux_src_ready), // rsp_sink.ready
.rsp_sink_valid (rsp_mux_src_valid), // .valid
.rsp_sink_channel (rsp_mux_src_channel), // .channel
.rsp_sink_data (rsp_mux_src_data), // .data
.rsp_sink_startofpacket (rsp_mux_src_startofpacket), // .startofpacket
.rsp_sink_endofpacket (rsp_mux_src_endofpacket), // .endofpacket
.rsp_src_ready (hps_0_h2f_lw_axi_master_wr_limiter_rsp_src_ready), // rsp_src.ready
.rsp_src_valid (hps_0_h2f_lw_axi_master_wr_limiter_rsp_src_valid), // .valid
.rsp_src_data (hps_0_h2f_lw_axi_master_wr_limiter_rsp_src_data), // .data
.rsp_src_channel (hps_0_h2f_lw_axi_master_wr_limiter_rsp_src_channel), // .channel
.rsp_src_startofpacket (hps_0_h2f_lw_axi_master_wr_limiter_rsp_src_startofpacket), // .startofpacket
.rsp_src_endofpacket (hps_0_h2f_lw_axi_master_wr_limiter_rsp_src_endofpacket), // .endofpacket
.cmd_src_valid (hps_0_h2f_lw_axi_master_wr_limiter_cmd_valid_data) // cmd_valid.data
);
altera_merlin_traffic_limiter #(
.PKT_DEST_ID_H (102),
.PKT_DEST_ID_L (100),
.PKT_SRC_ID_H (99),
.PKT_SRC_ID_L (97),
.PKT_BYTE_CNT_H (80),
.PKT_BYTE_CNT_L (74),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_TRANS_POSTED (69),
.PKT_TRANS_WRITE (70),
.MAX_OUTSTANDING_RESPONSES (7),
.PIPELINED (0),
.ST_DATA_W (127),
.ST_CHANNEL_W (5),
.VALID_WIDTH (5),
.ENFORCE_ORDER (1),
.PREVENT_HAZARDS (0),
.SUPPORTS_POSTED_WRITES (1),
.SUPPORTS_NONPOSTED_WRITES (0),
.REORDER (0)
) hps_0_h2f_lw_axi_master_rd_limiter (
.clk (clk_0_clk_clk), // clk.clk
.reset (hps_0_h2f_lw_axi_master_agent_clk_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.cmd_sink_ready (router_001_src_ready), // cmd_sink.ready
.cmd_sink_valid (router_001_src_valid), // .valid
.cmd_sink_data (router_001_src_data), // .data
.cmd_sink_channel (router_001_src_channel), // .channel
.cmd_sink_startofpacket (router_001_src_startofpacket), // .startofpacket
.cmd_sink_endofpacket (router_001_src_endofpacket), // .endofpacket
.cmd_src_ready (hps_0_h2f_lw_axi_master_rd_limiter_cmd_src_ready), // cmd_src.ready
.cmd_src_data (hps_0_h2f_lw_axi_master_rd_limiter_cmd_src_data), // .data
.cmd_src_channel (hps_0_h2f_lw_axi_master_rd_limiter_cmd_src_channel), // .channel
.cmd_src_startofpacket (hps_0_h2f_lw_axi_master_rd_limiter_cmd_src_startofpacket), // .startofpacket
.cmd_src_endofpacket (hps_0_h2f_lw_axi_master_rd_limiter_cmd_src_endofpacket), // .endofpacket
.rsp_sink_ready (rsp_mux_001_src_ready), // rsp_sink.ready
.rsp_sink_valid (rsp_mux_001_src_valid), // .valid
.rsp_sink_channel (rsp_mux_001_src_channel), // .channel
.rsp_sink_data (rsp_mux_001_src_data), // .data
.rsp_sink_startofpacket (rsp_mux_001_src_startofpacket), // .startofpacket
.rsp_sink_endofpacket (rsp_mux_001_src_endofpacket), // .endofpacket
.rsp_src_ready (hps_0_h2f_lw_axi_master_rd_limiter_rsp_src_ready), // rsp_src.ready
.rsp_src_valid (hps_0_h2f_lw_axi_master_rd_limiter_rsp_src_valid), // .valid
.rsp_src_data (hps_0_h2f_lw_axi_master_rd_limiter_rsp_src_data), // .data
.rsp_src_channel (hps_0_h2f_lw_axi_master_rd_limiter_rsp_src_channel), // .channel
.rsp_src_startofpacket (hps_0_h2f_lw_axi_master_rd_limiter_rsp_src_startofpacket), // .startofpacket
.rsp_src_endofpacket (hps_0_h2f_lw_axi_master_rd_limiter_rsp_src_endofpacket), // .endofpacket
.cmd_src_valid (hps_0_h2f_lw_axi_master_rd_limiter_cmd_valid_data) // cmd_valid.data
);
altera_merlin_traffic_limiter #(
.PKT_DEST_ID_H (102),
.PKT_DEST_ID_L (100),
.PKT_SRC_ID_H (99),
.PKT_SRC_ID_L (97),
.PKT_BYTE_CNT_H (80),
.PKT_BYTE_CNT_L (74),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_TRANS_POSTED (69),
.PKT_TRANS_WRITE (70),
.MAX_OUTSTANDING_RESPONSES (7),
.PIPELINED (0),
.ST_DATA_W (127),
.ST_CHANNEL_W (5),
.VALID_WIDTH (5),
.ENFORCE_ORDER (1),
.PREVENT_HAZARDS (0),
.SUPPORTS_POSTED_WRITES (1),
.SUPPORTS_NONPOSTED_WRITES (0),
.REORDER (0)
) master_non_sec_master_limiter (
.clk (clk_0_clk_clk), // clk.clk
.reset (jtag_uart_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.cmd_sink_ready (router_002_src_ready), // cmd_sink.ready
.cmd_sink_valid (router_002_src_valid), // .valid
.cmd_sink_data (router_002_src_data), // .data
.cmd_sink_channel (router_002_src_channel), // .channel
.cmd_sink_startofpacket (router_002_src_startofpacket), // .startofpacket
.cmd_sink_endofpacket (router_002_src_endofpacket), // .endofpacket
.cmd_src_ready (master_non_sec_master_limiter_cmd_src_ready), // cmd_src.ready
.cmd_src_data (master_non_sec_master_limiter_cmd_src_data), // .data
.cmd_src_channel (master_non_sec_master_limiter_cmd_src_channel), // .channel
.cmd_src_startofpacket (master_non_sec_master_limiter_cmd_src_startofpacket), // .startofpacket
.cmd_src_endofpacket (master_non_sec_master_limiter_cmd_src_endofpacket), // .endofpacket
.rsp_sink_ready (rsp_mux_002_src_ready), // rsp_sink.ready
.rsp_sink_valid (rsp_mux_002_src_valid), // .valid
.rsp_sink_channel (rsp_mux_002_src_channel), // .channel
.rsp_sink_data (rsp_mux_002_src_data), // .data
.rsp_sink_startofpacket (rsp_mux_002_src_startofpacket), // .startofpacket
.rsp_sink_endofpacket (rsp_mux_002_src_endofpacket), // .endofpacket
.rsp_src_ready (master_non_sec_master_limiter_rsp_src_ready), // rsp_src.ready
.rsp_src_valid (master_non_sec_master_limiter_rsp_src_valid), // .valid
.rsp_src_data (master_non_sec_master_limiter_rsp_src_data), // .data
.rsp_src_channel (master_non_sec_master_limiter_rsp_src_channel), // .channel
.rsp_src_startofpacket (master_non_sec_master_limiter_rsp_src_startofpacket), // .startofpacket
.rsp_src_endofpacket (master_non_sec_master_limiter_rsp_src_endofpacket), // .endofpacket
.cmd_src_valid (master_non_sec_master_limiter_cmd_valid_data) // cmd_valid.data
);
altera_merlin_burst_adapter #(
.PKT_ADDR_H (67),
.PKT_ADDR_L (36),
.PKT_BEGIN_BURST (95),
.PKT_BYTE_CNT_H (80),
.PKT_BYTE_CNT_L (74),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_BURST_SIZE_H (90),
.PKT_BURST_SIZE_L (88),
.PKT_BURST_TYPE_H (92),
.PKT_BURST_TYPE_L (91),
.PKT_BURSTWRAP_H (87),
.PKT_BURSTWRAP_L (81),
.PKT_TRANS_COMPRESSED_READ (68),
.PKT_TRANS_WRITE (70),
.PKT_TRANS_READ (71),
.OUT_NARROW_SIZE (0),
.IN_NARROW_SIZE (1),
.OUT_FIXED (0),
.OUT_COMPLETE_WRAP (0),
.ST_DATA_W (127),
.ST_CHANNEL_W (5),
.OUT_BYTE_CNT_H (76),
.OUT_BURSTWRAP_H (87),
.COMPRESSED_READ_SUPPORT (1),
.BYTEENABLE_SYNTHESIS (1),
.PIPE_INPUTS (0),
.NO_WRAP_SUPPORT (0),
.INCOMPLETE_WRAP_SUPPORT (0),
.BURSTWRAP_CONST_MASK (0),
.BURSTWRAP_CONST_VALUE (0),
.ADAPTER_VERSION ("13.1")
) jtag_uart_avalon_jtag_slave_burst_adapter (
.clk (clk_0_clk_clk), // cr0.clk
.reset (jtag_uart_reset_reset_bridge_in_reset_reset), // cr0_reset.reset
.sink0_valid (cmd_mux_src_valid), // sink0.valid
.sink0_data (cmd_mux_src_data), // .data
.sink0_channel (cmd_mux_src_channel), // .channel
.sink0_startofpacket (cmd_mux_src_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_mux_src_endofpacket), // .endofpacket
.sink0_ready (cmd_mux_src_ready), // .ready
.source0_valid (jtag_uart_avalon_jtag_slave_burst_adapter_source0_valid), // source0.valid
.source0_data (jtag_uart_avalon_jtag_slave_burst_adapter_source0_data), // .data
.source0_channel (jtag_uart_avalon_jtag_slave_burst_adapter_source0_channel), // .channel
.source0_startofpacket (jtag_uart_avalon_jtag_slave_burst_adapter_source0_startofpacket), // .startofpacket
.source0_endofpacket (jtag_uart_avalon_jtag_slave_burst_adapter_source0_endofpacket), // .endofpacket
.source0_ready (jtag_uart_avalon_jtag_slave_burst_adapter_source0_ready) // .ready
);
altera_merlin_burst_adapter #(
.PKT_ADDR_H (67),
.PKT_ADDR_L (36),
.PKT_BEGIN_BURST (95),
.PKT_BYTE_CNT_H (80),
.PKT_BYTE_CNT_L (74),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_BURST_SIZE_H (90),
.PKT_BURST_SIZE_L (88),
.PKT_BURST_TYPE_H (92),
.PKT_BURST_TYPE_L (91),
.PKT_BURSTWRAP_H (87),
.PKT_BURSTWRAP_L (81),
.PKT_TRANS_COMPRESSED_READ (68),
.PKT_TRANS_WRITE (70),
.PKT_TRANS_READ (71),
.OUT_NARROW_SIZE (0),
.IN_NARROW_SIZE (1),
.OUT_FIXED (0),
.OUT_COMPLETE_WRAP (0),
.ST_DATA_W (127),
.ST_CHANNEL_W (5),
.OUT_BYTE_CNT_H (76),
.OUT_BURSTWRAP_H (87),
.COMPRESSED_READ_SUPPORT (1),
.BYTEENABLE_SYNTHESIS (1),
.PIPE_INPUTS (0),
.NO_WRAP_SUPPORT (0),
.INCOMPLETE_WRAP_SUPPORT (0),
.BURSTWRAP_CONST_MASK (0),
.BURSTWRAP_CONST_VALUE (0),
.ADAPTER_VERSION ("13.1")
) alt_vip_vfr_vga_avalon_slave_burst_adapter (
.clk (clk_stream_clk_clk), // cr0.clk
.reset (alt_vip_vfr_vga_clock_reset_reset_reset_bridge_in_reset_reset), // cr0_reset.reset
.sink0_valid (cmd_mux_001_src_valid), // sink0.valid
.sink0_data (cmd_mux_001_src_data), // .data
.sink0_channel (cmd_mux_001_src_channel), // .channel
.sink0_startofpacket (cmd_mux_001_src_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_mux_001_src_endofpacket), // .endofpacket
.sink0_ready (cmd_mux_001_src_ready), // .ready
.source0_valid (alt_vip_vfr_vga_avalon_slave_burst_adapter_source0_valid), // source0.valid
.source0_data (alt_vip_vfr_vga_avalon_slave_burst_adapter_source0_data), // .data
.source0_channel (alt_vip_vfr_vga_avalon_slave_burst_adapter_source0_channel), // .channel
.source0_startofpacket (alt_vip_vfr_vga_avalon_slave_burst_adapter_source0_startofpacket), // .startofpacket
.source0_endofpacket (alt_vip_vfr_vga_avalon_slave_burst_adapter_source0_endofpacket), // .endofpacket
.source0_ready (alt_vip_vfr_vga_avalon_slave_burst_adapter_source0_ready) // .ready
);
altera_merlin_burst_adapter #(
.PKT_ADDR_H (67),
.PKT_ADDR_L (36),
.PKT_BEGIN_BURST (95),
.PKT_BYTE_CNT_H (80),
.PKT_BYTE_CNT_L (74),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_BURST_SIZE_H (90),
.PKT_BURST_SIZE_L (88),
.PKT_BURST_TYPE_H (92),
.PKT_BURST_TYPE_L (91),
.PKT_BURSTWRAP_H (87),
.PKT_BURSTWRAP_L (81),
.PKT_TRANS_COMPRESSED_READ (68),
.PKT_TRANS_WRITE (70),
.PKT_TRANS_READ (71),
.OUT_NARROW_SIZE (0),
.IN_NARROW_SIZE (1),
.OUT_FIXED (0),
.OUT_COMPLETE_WRAP (0),
.ST_DATA_W (127),
.ST_CHANNEL_W (5),
.OUT_BYTE_CNT_H (76),
.OUT_BURSTWRAP_H (87),
.COMPRESSED_READ_SUPPORT (1),
.BYTEENABLE_SYNTHESIS (1),
.PIPE_INPUTS (0),
.NO_WRAP_SUPPORT (0),
.INCOMPLETE_WRAP_SUPPORT (0),
.BURSTWRAP_CONST_MASK (0),
.BURSTWRAP_CONST_VALUE (0),
.ADAPTER_VERSION ("13.1")
) ece453_0_avalon_slave_0_burst_adapter (
.clk (clk_0_clk_clk), // cr0.clk
.reset (ece453_0_clock_reset_reset_bridge_in_reset_reset), // cr0_reset.reset
.sink0_valid (cmd_mux_002_src_valid), // sink0.valid
.sink0_data (cmd_mux_002_src_data), // .data
.sink0_channel (cmd_mux_002_src_channel), // .channel
.sink0_startofpacket (cmd_mux_002_src_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_mux_002_src_endofpacket), // .endofpacket
.sink0_ready (cmd_mux_002_src_ready), // .ready
.source0_valid (ece453_0_avalon_slave_0_burst_adapter_source0_valid), // source0.valid
.source0_data (ece453_0_avalon_slave_0_burst_adapter_source0_data), // .data
.source0_channel (ece453_0_avalon_slave_0_burst_adapter_source0_channel), // .channel
.source0_startofpacket (ece453_0_avalon_slave_0_burst_adapter_source0_startofpacket), // .startofpacket
.source0_endofpacket (ece453_0_avalon_slave_0_burst_adapter_source0_endofpacket), // .endofpacket
.source0_ready (ece453_0_avalon_slave_0_burst_adapter_source0_ready) // .ready
);
altera_merlin_burst_adapter #(
.PKT_ADDR_H (67),
.PKT_ADDR_L (36),
.PKT_BEGIN_BURST (95),
.PKT_BYTE_CNT_H (80),
.PKT_BYTE_CNT_L (74),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_BURST_SIZE_H (90),
.PKT_BURST_SIZE_L (88),
.PKT_BURST_TYPE_H (92),
.PKT_BURST_TYPE_L (91),
.PKT_BURSTWRAP_H (87),
.PKT_BURSTWRAP_L (81),
.PKT_TRANS_COMPRESSED_READ (68),
.PKT_TRANS_WRITE (70),
.PKT_TRANS_READ (71),
.OUT_NARROW_SIZE (0),
.IN_NARROW_SIZE (1),
.OUT_FIXED (0),
.OUT_COMPLETE_WRAP (0),
.ST_DATA_W (127),
.ST_CHANNEL_W (5),
.OUT_BYTE_CNT_H (76),
.OUT_BURSTWRAP_H (87),
.COMPRESSED_READ_SUPPORT (1),
.BYTEENABLE_SYNTHESIS (1),
.PIPE_INPUTS (0),
.NO_WRAP_SUPPORT (0),
.INCOMPLETE_WRAP_SUPPORT (0),
.BURSTWRAP_CONST_MASK (0),
.BURSTWRAP_CONST_VALUE (0),
.ADAPTER_VERSION ("13.1")
) sysid_qsys_control_slave_burst_adapter (
.clk (clk_0_clk_clk), // cr0.clk
.reset (jtag_uart_reset_reset_bridge_in_reset_reset), // cr0_reset.reset
.sink0_valid (cmd_mux_003_src_valid), // sink0.valid
.sink0_data (cmd_mux_003_src_data), // .data
.sink0_channel (cmd_mux_003_src_channel), // .channel
.sink0_startofpacket (cmd_mux_003_src_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_mux_003_src_endofpacket), // .endofpacket
.sink0_ready (cmd_mux_003_src_ready), // .ready
.source0_valid (sysid_qsys_control_slave_burst_adapter_source0_valid), // source0.valid
.source0_data (sysid_qsys_control_slave_burst_adapter_source0_data), // .data
.source0_channel (sysid_qsys_control_slave_burst_adapter_source0_channel), // .channel
.source0_startofpacket (sysid_qsys_control_slave_burst_adapter_source0_startofpacket), // .startofpacket
.source0_endofpacket (sysid_qsys_control_slave_burst_adapter_source0_endofpacket), // .endofpacket
.source0_ready (sysid_qsys_control_slave_burst_adapter_source0_ready) // .ready
);
soc_system_mm_interconnect_1_cmd_demux cmd_demux (
.clk (clk_0_clk_clk), // clk.clk
.reset (hps_0_h2f_lw_axi_master_agent_clk_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (hps_0_h2f_lw_axi_master_wr_limiter_cmd_src_ready), // sink.ready
.sink_channel (hps_0_h2f_lw_axi_master_wr_limiter_cmd_src_channel), // .channel
.sink_data (hps_0_h2f_lw_axi_master_wr_limiter_cmd_src_data), // .data
.sink_startofpacket (hps_0_h2f_lw_axi_master_wr_limiter_cmd_src_startofpacket), // .startofpacket
.sink_endofpacket (hps_0_h2f_lw_axi_master_wr_limiter_cmd_src_endofpacket), // .endofpacket
.sink_valid (hps_0_h2f_lw_axi_master_wr_limiter_cmd_valid_data), // sink_valid.data
.src0_ready (cmd_demux_src0_ready), // src0.ready
.src0_valid (cmd_demux_src0_valid), // .valid
.src0_data (cmd_demux_src0_data), // .data
.src0_channel (cmd_demux_src0_channel), // .channel
.src0_startofpacket (cmd_demux_src0_startofpacket), // .startofpacket
.src0_endofpacket (cmd_demux_src0_endofpacket), // .endofpacket
.src1_ready (cmd_demux_src1_ready), // src1.ready
.src1_valid (cmd_demux_src1_valid), // .valid
.src1_data (cmd_demux_src1_data), // .data
.src1_channel (cmd_demux_src1_channel), // .channel
.src1_startofpacket (cmd_demux_src1_startofpacket), // .startofpacket
.src1_endofpacket (cmd_demux_src1_endofpacket), // .endofpacket
.src2_ready (cmd_demux_src2_ready), // src2.ready
.src2_valid (cmd_demux_src2_valid), // .valid
.src2_data (cmd_demux_src2_data), // .data
.src2_channel (cmd_demux_src2_channel), // .channel
.src2_startofpacket (cmd_demux_src2_startofpacket), // .startofpacket
.src2_endofpacket (cmd_demux_src2_endofpacket), // .endofpacket
.src3_ready (cmd_demux_src3_ready), // src3.ready
.src3_valid (cmd_demux_src3_valid), // .valid
.src3_data (cmd_demux_src3_data), // .data
.src3_channel (cmd_demux_src3_channel), // .channel
.src3_startofpacket (cmd_demux_src3_startofpacket), // .startofpacket
.src3_endofpacket (cmd_demux_src3_endofpacket) // .endofpacket
);
soc_system_mm_interconnect_1_cmd_demux cmd_demux_001 (
.clk (clk_0_clk_clk), // clk.clk
.reset (hps_0_h2f_lw_axi_master_agent_clk_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (hps_0_h2f_lw_axi_master_rd_limiter_cmd_src_ready), // sink.ready
.sink_channel (hps_0_h2f_lw_axi_master_rd_limiter_cmd_src_channel), // .channel
.sink_data (hps_0_h2f_lw_axi_master_rd_limiter_cmd_src_data), // .data
.sink_startofpacket (hps_0_h2f_lw_axi_master_rd_limiter_cmd_src_startofpacket), // .startofpacket
.sink_endofpacket (hps_0_h2f_lw_axi_master_rd_limiter_cmd_src_endofpacket), // .endofpacket
.sink_valid (hps_0_h2f_lw_axi_master_rd_limiter_cmd_valid_data), // sink_valid.data
.src0_ready (cmd_demux_001_src0_ready), // src0.ready
.src0_valid (cmd_demux_001_src0_valid), // .valid
.src0_data (cmd_demux_001_src0_data), // .data
.src0_channel (cmd_demux_001_src0_channel), // .channel
.src0_startofpacket (cmd_demux_001_src0_startofpacket), // .startofpacket
.src0_endofpacket (cmd_demux_001_src0_endofpacket), // .endofpacket
.src1_ready (cmd_demux_001_src1_ready), // src1.ready
.src1_valid (cmd_demux_001_src1_valid), // .valid
.src1_data (cmd_demux_001_src1_data), // .data
.src1_channel (cmd_demux_001_src1_channel), // .channel
.src1_startofpacket (cmd_demux_001_src1_startofpacket), // .startofpacket
.src1_endofpacket (cmd_demux_001_src1_endofpacket), // .endofpacket
.src2_ready (cmd_demux_001_src2_ready), // src2.ready
.src2_valid (cmd_demux_001_src2_valid), // .valid
.src2_data (cmd_demux_001_src2_data), // .data
.src2_channel (cmd_demux_001_src2_channel), // .channel
.src2_startofpacket (cmd_demux_001_src2_startofpacket), // .startofpacket
.src2_endofpacket (cmd_demux_001_src2_endofpacket), // .endofpacket
.src3_ready (cmd_demux_001_src3_ready), // src3.ready
.src3_valid (cmd_demux_001_src3_valid), // .valid
.src3_data (cmd_demux_001_src3_data), // .data
.src3_channel (cmd_demux_001_src3_channel), // .channel
.src3_startofpacket (cmd_demux_001_src3_startofpacket), // .startofpacket
.src3_endofpacket (cmd_demux_001_src3_endofpacket) // .endofpacket
);
soc_system_mm_interconnect_1_cmd_demux cmd_demux_002 (
.clk (clk_0_clk_clk), // clk.clk
.reset (jtag_uart_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (master_non_sec_master_limiter_cmd_src_ready), // sink.ready
.sink_channel (master_non_sec_master_limiter_cmd_src_channel), // .channel
.sink_data (master_non_sec_master_limiter_cmd_src_data), // .data
.sink_startofpacket (master_non_sec_master_limiter_cmd_src_startofpacket), // .startofpacket
.sink_endofpacket (master_non_sec_master_limiter_cmd_src_endofpacket), // .endofpacket
.sink_valid (master_non_sec_master_limiter_cmd_valid_data), // sink_valid.data
.src0_ready (cmd_demux_002_src0_ready), // src0.ready
.src0_valid (cmd_demux_002_src0_valid), // .valid
.src0_data (cmd_demux_002_src0_data), // .data
.src0_channel (cmd_demux_002_src0_channel), // .channel
.src0_startofpacket (cmd_demux_002_src0_startofpacket), // .startofpacket
.src0_endofpacket (cmd_demux_002_src0_endofpacket), // .endofpacket
.src1_ready (cmd_demux_002_src1_ready), // src1.ready
.src1_valid (cmd_demux_002_src1_valid), // .valid
.src1_data (cmd_demux_002_src1_data), // .data
.src1_channel (cmd_demux_002_src1_channel), // .channel
.src1_startofpacket (cmd_demux_002_src1_startofpacket), // .startofpacket
.src1_endofpacket (cmd_demux_002_src1_endofpacket), // .endofpacket
.src2_ready (cmd_demux_002_src2_ready), // src2.ready
.src2_valid (cmd_demux_002_src2_valid), // .valid
.src2_data (cmd_demux_002_src2_data), // .data
.src2_channel (cmd_demux_002_src2_channel), // .channel
.src2_startofpacket (cmd_demux_002_src2_startofpacket), // .startofpacket
.src2_endofpacket (cmd_demux_002_src2_endofpacket), // .endofpacket
.src3_ready (cmd_demux_002_src3_ready), // src3.ready
.src3_valid (cmd_demux_002_src3_valid), // .valid
.src3_data (cmd_demux_002_src3_data), // .data
.src3_channel (cmd_demux_002_src3_channel), // .channel
.src3_startofpacket (cmd_demux_002_src3_startofpacket), // .startofpacket
.src3_endofpacket (cmd_demux_002_src3_endofpacket) // .endofpacket
);
soc_system_mm_interconnect_1_cmd_mux cmd_mux (
.clk (clk_0_clk_clk), // clk.clk
.reset (jtag_uart_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_src_ready), // src.ready
.src_valid (cmd_mux_src_valid), // .valid
.src_data (cmd_mux_src_data), // .data
.src_channel (cmd_mux_src_channel), // .channel
.src_startofpacket (cmd_mux_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_src0_ready), // sink0.ready
.sink0_valid (cmd_demux_src0_valid), // .valid
.sink0_channel (cmd_demux_src0_channel), // .channel
.sink0_data (cmd_demux_src0_data), // .data
.sink0_startofpacket (cmd_demux_src0_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_src0_endofpacket), // .endofpacket
.sink1_ready (cmd_demux_001_src0_ready), // sink1.ready
.sink1_valid (cmd_demux_001_src0_valid), // .valid
.sink1_channel (cmd_demux_001_src0_channel), // .channel
.sink1_data (cmd_demux_001_src0_data), // .data
.sink1_startofpacket (cmd_demux_001_src0_startofpacket), // .startofpacket
.sink1_endofpacket (cmd_demux_001_src0_endofpacket), // .endofpacket
.sink2_ready (cmd_demux_002_src0_ready), // sink2.ready
.sink2_valid (cmd_demux_002_src0_valid), // .valid
.sink2_channel (cmd_demux_002_src0_channel), // .channel
.sink2_data (cmd_demux_002_src0_data), // .data
.sink2_startofpacket (cmd_demux_002_src0_startofpacket), // .startofpacket
.sink2_endofpacket (cmd_demux_002_src0_endofpacket) // .endofpacket
);
soc_system_mm_interconnect_1_cmd_mux cmd_mux_001 (
.clk (clk_stream_clk_clk), // clk.clk
.reset (alt_vip_vfr_vga_clock_reset_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_001_src_ready), // src.ready
.src_valid (cmd_mux_001_src_valid), // .valid
.src_data (cmd_mux_001_src_data), // .data
.src_channel (cmd_mux_001_src_channel), // .channel
.src_startofpacket (cmd_mux_001_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_001_src_endofpacket), // .endofpacket
.sink0_ready (crosser_out_ready), // sink0.ready
.sink0_valid (crosser_out_valid), // .valid
.sink0_channel (crosser_out_channel), // .channel
.sink0_data (crosser_out_data), // .data
.sink0_startofpacket (crosser_out_startofpacket), // .startofpacket
.sink0_endofpacket (crosser_out_endofpacket), // .endofpacket
.sink1_ready (crosser_001_out_ready), // sink1.ready
.sink1_valid (crosser_001_out_valid), // .valid
.sink1_channel (crosser_001_out_channel), // .channel
.sink1_data (crosser_001_out_data), // .data
.sink1_startofpacket (crosser_001_out_startofpacket), // .startofpacket
.sink1_endofpacket (crosser_001_out_endofpacket), // .endofpacket
.sink2_ready (crosser_002_out_ready), // sink2.ready
.sink2_valid (crosser_002_out_valid), // .valid
.sink2_channel (crosser_002_out_channel), // .channel
.sink2_data (crosser_002_out_data), // .data
.sink2_startofpacket (crosser_002_out_startofpacket), // .startofpacket
.sink2_endofpacket (crosser_002_out_endofpacket) // .endofpacket
);
soc_system_mm_interconnect_1_cmd_mux_002 cmd_mux_002 (
.clk (clk_0_clk_clk), // clk.clk
.reset (ece453_0_clock_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_002_src_ready), // src.ready
.src_valid (cmd_mux_002_src_valid), // .valid
.src_data (cmd_mux_002_src_data), // .data
.src_channel (cmd_mux_002_src_channel), // .channel
.src_startofpacket (cmd_mux_002_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_002_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_src2_ready), // sink0.ready
.sink0_valid (cmd_demux_src2_valid), // .valid
.sink0_channel (cmd_demux_src2_channel), // .channel
.sink0_data (cmd_demux_src2_data), // .data
.sink0_startofpacket (cmd_demux_src2_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_src2_endofpacket), // .endofpacket
.sink1_ready (cmd_demux_001_src2_ready), // sink1.ready
.sink1_valid (cmd_demux_001_src2_valid), // .valid
.sink1_channel (cmd_demux_001_src2_channel), // .channel
.sink1_data (cmd_demux_001_src2_data), // .data
.sink1_startofpacket (cmd_demux_001_src2_startofpacket), // .startofpacket
.sink1_endofpacket (cmd_demux_001_src2_endofpacket) // .endofpacket
);
soc_system_mm_interconnect_1_cmd_mux cmd_mux_003 (
.clk (clk_0_clk_clk), // clk.clk
.reset (jtag_uart_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_003_src_ready), // src.ready
.src_valid (cmd_mux_003_src_valid), // .valid
.src_data (cmd_mux_003_src_data), // .data
.src_channel (cmd_mux_003_src_channel), // .channel
.src_startofpacket (cmd_mux_003_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_003_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_src3_ready), // sink0.ready
.sink0_valid (cmd_demux_src3_valid), // .valid
.sink0_channel (cmd_demux_src3_channel), // .channel
.sink0_data (cmd_demux_src3_data), // .data
.sink0_startofpacket (cmd_demux_src3_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_src3_endofpacket), // .endofpacket
.sink1_ready (cmd_demux_001_src3_ready), // sink1.ready
.sink1_valid (cmd_demux_001_src3_valid), // .valid
.sink1_channel (cmd_demux_001_src3_channel), // .channel
.sink1_data (cmd_demux_001_src3_data), // .data
.sink1_startofpacket (cmd_demux_001_src3_startofpacket), // .startofpacket
.sink1_endofpacket (cmd_demux_001_src3_endofpacket), // .endofpacket
.sink2_ready (cmd_demux_002_src2_ready), // sink2.ready
.sink2_valid (cmd_demux_002_src2_valid), // .valid
.sink2_channel (cmd_demux_002_src2_channel), // .channel
.sink2_data (cmd_demux_002_src2_data), // .data
.sink2_startofpacket (cmd_demux_002_src2_startofpacket), // .startofpacket
.sink2_endofpacket (cmd_demux_002_src2_endofpacket) // .endofpacket
);
soc_system_mm_interconnect_1_cmd_mux_004 cmd_mux_004 (
.clk (clk_0_clk_clk), // clk.clk
.reset (jtag_uart_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_004_src_ready), // src.ready
.src_valid (cmd_mux_004_src_valid), // .valid
.src_data (cmd_mux_004_src_data), // .data
.src_channel (cmd_mux_004_src_channel), // .channel
.src_startofpacket (cmd_mux_004_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_004_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_002_src3_ready), // sink0.ready
.sink0_valid (cmd_demux_002_src3_valid), // .valid
.sink0_channel (cmd_demux_002_src3_channel), // .channel
.sink0_data (cmd_demux_002_src3_data), // .data
.sink0_startofpacket (cmd_demux_002_src3_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_002_src3_endofpacket) // .endofpacket
);
soc_system_mm_interconnect_1_rsp_demux rsp_demux (
.clk (clk_0_clk_clk), // clk.clk
.reset (jtag_uart_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_003_src_ready), // sink.ready
.sink_channel (router_003_src_channel), // .channel
.sink_data (router_003_src_data), // .data
.sink_startofpacket (router_003_src_startofpacket), // .startofpacket
.sink_endofpacket (router_003_src_endofpacket), // .endofpacket
.sink_valid (router_003_src_valid), // .valid
.src0_ready (rsp_demux_src0_ready), // src0.ready
.src0_valid (rsp_demux_src0_valid), // .valid
.src0_data (rsp_demux_src0_data), // .data
.src0_channel (rsp_demux_src0_channel), // .channel
.src0_startofpacket (rsp_demux_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_src0_endofpacket), // .endofpacket
.src1_ready (rsp_demux_src1_ready), // src1.ready
.src1_valid (rsp_demux_src1_valid), // .valid
.src1_data (rsp_demux_src1_data), // .data
.src1_channel (rsp_demux_src1_channel), // .channel
.src1_startofpacket (rsp_demux_src1_startofpacket), // .startofpacket
.src1_endofpacket (rsp_demux_src1_endofpacket), // .endofpacket
.src2_ready (rsp_demux_src2_ready), // src2.ready
.src2_valid (rsp_demux_src2_valid), // .valid
.src2_data (rsp_demux_src2_data), // .data
.src2_channel (rsp_demux_src2_channel), // .channel
.src2_startofpacket (rsp_demux_src2_startofpacket), // .startofpacket
.src2_endofpacket (rsp_demux_src2_endofpacket) // .endofpacket
);
soc_system_mm_interconnect_1_rsp_demux_001 rsp_demux_001 (
.clk (clk_stream_clk_clk), // clk.clk
.reset (alt_vip_vfr_vga_clock_reset_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_004_src_ready), // sink.ready
.sink_channel (router_004_src_channel), // .channel
.sink_data (router_004_src_data), // .data
.sink_startofpacket (router_004_src_startofpacket), // .startofpacket
.sink_endofpacket (router_004_src_endofpacket), // .endofpacket
.sink_valid (router_004_src_valid), // .valid
.src0_ready (rsp_demux_001_src0_ready), // src0.ready
.src0_valid (rsp_demux_001_src0_valid), // .valid
.src0_data (rsp_demux_001_src0_data), // .data
.src0_channel (rsp_demux_001_src0_channel), // .channel
.src0_startofpacket (rsp_demux_001_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_001_src0_endofpacket), // .endofpacket
.src1_ready (rsp_demux_001_src1_ready), // src1.ready
.src1_valid (rsp_demux_001_src1_valid), // .valid
.src1_data (rsp_demux_001_src1_data), // .data
.src1_channel (rsp_demux_001_src1_channel), // .channel
.src1_startofpacket (rsp_demux_001_src1_startofpacket), // .startofpacket
.src1_endofpacket (rsp_demux_001_src1_endofpacket), // .endofpacket
.src2_ready (rsp_demux_001_src2_ready), // src2.ready
.src2_valid (rsp_demux_001_src2_valid), // .valid
.src2_data (rsp_demux_001_src2_data), // .data
.src2_channel (rsp_demux_001_src2_channel), // .channel
.src2_startofpacket (rsp_demux_001_src2_startofpacket), // .startofpacket
.src2_endofpacket (rsp_demux_001_src2_endofpacket) // .endofpacket
);
soc_system_mm_interconnect_1_rsp_demux_002 rsp_demux_002 (
.clk (clk_0_clk_clk), // clk.clk
.reset (ece453_0_clock_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_005_src_ready), // sink.ready
.sink_channel (router_005_src_channel), // .channel
.sink_data (router_005_src_data), // .data
.sink_startofpacket (router_005_src_startofpacket), // .startofpacket
.sink_endofpacket (router_005_src_endofpacket), // .endofpacket
.sink_valid (router_005_src_valid), // .valid
.src0_ready (rsp_demux_002_src0_ready), // src0.ready
.src0_valid (rsp_demux_002_src0_valid), // .valid
.src0_data (rsp_demux_002_src0_data), // .data
.src0_channel (rsp_demux_002_src0_channel), // .channel
.src0_startofpacket (rsp_demux_002_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_002_src0_endofpacket), // .endofpacket
.src1_ready (rsp_demux_002_src1_ready), // src1.ready
.src1_valid (rsp_demux_002_src1_valid), // .valid
.src1_data (rsp_demux_002_src1_data), // .data
.src1_channel (rsp_demux_002_src1_channel), // .channel
.src1_startofpacket (rsp_demux_002_src1_startofpacket), // .startofpacket
.src1_endofpacket (rsp_demux_002_src1_endofpacket) // .endofpacket
);
soc_system_mm_interconnect_1_rsp_demux rsp_demux_003 (
.clk (clk_0_clk_clk), // clk.clk
.reset (jtag_uart_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_006_src_ready), // sink.ready
.sink_channel (router_006_src_channel), // .channel
.sink_data (router_006_src_data), // .data
.sink_startofpacket (router_006_src_startofpacket), // .startofpacket
.sink_endofpacket (router_006_src_endofpacket), // .endofpacket
.sink_valid (router_006_src_valid), // .valid
.src0_ready (rsp_demux_003_src0_ready), // src0.ready
.src0_valid (rsp_demux_003_src0_valid), // .valid
.src0_data (rsp_demux_003_src0_data), // .data
.src0_channel (rsp_demux_003_src0_channel), // .channel
.src0_startofpacket (rsp_demux_003_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_003_src0_endofpacket), // .endofpacket
.src1_ready (rsp_demux_003_src1_ready), // src1.ready
.src1_valid (rsp_demux_003_src1_valid), // .valid
.src1_data (rsp_demux_003_src1_data), // .data
.src1_channel (rsp_demux_003_src1_channel), // .channel
.src1_startofpacket (rsp_demux_003_src1_startofpacket), // .startofpacket
.src1_endofpacket (rsp_demux_003_src1_endofpacket), // .endofpacket
.src2_ready (rsp_demux_003_src2_ready), // src2.ready
.src2_valid (rsp_demux_003_src2_valid), // .valid
.src2_data (rsp_demux_003_src2_data), // .data
.src2_channel (rsp_demux_003_src2_channel), // .channel
.src2_startofpacket (rsp_demux_003_src2_startofpacket), // .startofpacket
.src2_endofpacket (rsp_demux_003_src2_endofpacket) // .endofpacket
);
soc_system_mm_interconnect_1_rsp_demux_004 rsp_demux_004 (
.clk (clk_0_clk_clk), // clk.clk
.reset (jtag_uart_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_007_src_ready), // sink.ready
.sink_channel (router_007_src_channel), // .channel
.sink_data (router_007_src_data), // .data
.sink_startofpacket (router_007_src_startofpacket), // .startofpacket
.sink_endofpacket (router_007_src_endofpacket), // .endofpacket
.sink_valid (router_007_src_valid), // .valid
.src0_ready (rsp_demux_004_src0_ready), // src0.ready
.src0_valid (rsp_demux_004_src0_valid), // .valid
.src0_data (rsp_demux_004_src0_data), // .data
.src0_channel (rsp_demux_004_src0_channel), // .channel
.src0_startofpacket (rsp_demux_004_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_004_src0_endofpacket) // .endofpacket
);
soc_system_mm_interconnect_1_rsp_mux rsp_mux (
.clk (clk_0_clk_clk), // clk.clk
.reset (hps_0_h2f_lw_axi_master_agent_clk_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (rsp_mux_src_ready), // src.ready
.src_valid (rsp_mux_src_valid), // .valid
.src_data (rsp_mux_src_data), // .data
.src_channel (rsp_mux_src_channel), // .channel
.src_startofpacket (rsp_mux_src_startofpacket), // .startofpacket
.src_endofpacket (rsp_mux_src_endofpacket), // .endofpacket
.sink0_ready (rsp_demux_src0_ready), // sink0.ready
.sink0_valid (rsp_demux_src0_valid), // .valid
.sink0_channel (rsp_demux_src0_channel), // .channel
.sink0_data (rsp_demux_src0_data), // .data
.sink0_startofpacket (rsp_demux_src0_startofpacket), // .startofpacket
.sink0_endofpacket (rsp_demux_src0_endofpacket), // .endofpacket
.sink1_ready (crosser_003_out_ready), // sink1.ready
.sink1_valid (crosser_003_out_valid), // .valid
.sink1_channel (crosser_003_out_channel), // .channel
.sink1_data (crosser_003_out_data), // .data
.sink1_startofpacket (crosser_003_out_startofpacket), // .startofpacket
.sink1_endofpacket (crosser_003_out_endofpacket), // .endofpacket
.sink2_ready (rsp_demux_002_src0_ready), // sink2.ready
.sink2_valid (rsp_demux_002_src0_valid), // .valid
.sink2_channel (rsp_demux_002_src0_channel), // .channel
.sink2_data (rsp_demux_002_src0_data), // .data
.sink2_startofpacket (rsp_demux_002_src0_startofpacket), // .startofpacket
.sink2_endofpacket (rsp_demux_002_src0_endofpacket), // .endofpacket
.sink3_ready (rsp_demux_003_src0_ready), // sink3.ready
.sink3_valid (rsp_demux_003_src0_valid), // .valid
.sink3_channel (rsp_demux_003_src0_channel), // .channel
.sink3_data (rsp_demux_003_src0_data), // .data
.sink3_startofpacket (rsp_demux_003_src0_startofpacket), // .startofpacket
.sink3_endofpacket (rsp_demux_003_src0_endofpacket) // .endofpacket
);
soc_system_mm_interconnect_1_rsp_mux rsp_mux_001 (
.clk (clk_0_clk_clk), // clk.clk
.reset (hps_0_h2f_lw_axi_master_agent_clk_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (rsp_mux_001_src_ready), // src.ready
.src_valid (rsp_mux_001_src_valid), // .valid
.src_data (rsp_mux_001_src_data), // .data
.src_channel (rsp_mux_001_src_channel), // .channel
.src_startofpacket (rsp_mux_001_src_startofpacket), // .startofpacket
.src_endofpacket (rsp_mux_001_src_endofpacket), // .endofpacket
.sink0_ready (rsp_demux_src1_ready), // sink0.ready
.sink0_valid (rsp_demux_src1_valid), // .valid
.sink0_channel (rsp_demux_src1_channel), // .channel
.sink0_data (rsp_demux_src1_data), // .data
.sink0_startofpacket (rsp_demux_src1_startofpacket), // .startofpacket
.sink0_endofpacket (rsp_demux_src1_endofpacket), // .endofpacket
.sink1_ready (crosser_004_out_ready), // sink1.ready
.sink1_valid (crosser_004_out_valid), // .valid
.sink1_channel (crosser_004_out_channel), // .channel
.sink1_data (crosser_004_out_data), // .data
.sink1_startofpacket (crosser_004_out_startofpacket), // .startofpacket
.sink1_endofpacket (crosser_004_out_endofpacket), // .endofpacket
.sink2_ready (rsp_demux_002_src1_ready), // sink2.ready
.sink2_valid (rsp_demux_002_src1_valid), // .valid
.sink2_channel (rsp_demux_002_src1_channel), // .channel
.sink2_data (rsp_demux_002_src1_data), // .data
.sink2_startofpacket (rsp_demux_002_src1_startofpacket), // .startofpacket
.sink2_endofpacket (rsp_demux_002_src1_endofpacket), // .endofpacket
.sink3_ready (rsp_demux_003_src1_ready), // sink3.ready
.sink3_valid (rsp_demux_003_src1_valid), // .valid
.sink3_channel (rsp_demux_003_src1_channel), // .channel
.sink3_data (rsp_demux_003_src1_data), // .data
.sink3_startofpacket (rsp_demux_003_src1_startofpacket), // .startofpacket
.sink3_endofpacket (rsp_demux_003_src1_endofpacket) // .endofpacket
);
soc_system_mm_interconnect_1_rsp_mux rsp_mux_002 (
.clk (clk_0_clk_clk), // clk.clk
.reset (jtag_uart_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (rsp_mux_002_src_ready), // src.ready
.src_valid (rsp_mux_002_src_valid), // .valid
.src_data (rsp_mux_002_src_data), // .data
.src_channel (rsp_mux_002_src_channel), // .channel
.src_startofpacket (rsp_mux_002_src_startofpacket), // .startofpacket
.src_endofpacket (rsp_mux_002_src_endofpacket), // .endofpacket
.sink0_ready (rsp_demux_src2_ready), // sink0.ready
.sink0_valid (rsp_demux_src2_valid), // .valid
.sink0_channel (rsp_demux_src2_channel), // .channel
.sink0_data (rsp_demux_src2_data), // .data
.sink0_startofpacket (rsp_demux_src2_startofpacket), // .startofpacket
.sink0_endofpacket (rsp_demux_src2_endofpacket), // .endofpacket
.sink1_ready (crosser_005_out_ready), // sink1.ready
.sink1_valid (crosser_005_out_valid), // .valid
.sink1_channel (crosser_005_out_channel), // .channel
.sink1_data (crosser_005_out_data), // .data
.sink1_startofpacket (crosser_005_out_startofpacket), // .startofpacket
.sink1_endofpacket (crosser_005_out_endofpacket), // .endofpacket
.sink2_ready (rsp_demux_003_src2_ready), // sink2.ready
.sink2_valid (rsp_demux_003_src2_valid), // .valid
.sink2_channel (rsp_demux_003_src2_channel), // .channel
.sink2_data (rsp_demux_003_src2_data), // .data
.sink2_startofpacket (rsp_demux_003_src2_startofpacket), // .startofpacket
.sink2_endofpacket (rsp_demux_003_src2_endofpacket), // .endofpacket
.sink3_ready (rsp_demux_004_src0_ready), // sink3.ready
.sink3_valid (rsp_demux_004_src0_valid), // .valid
.sink3_channel (rsp_demux_004_src0_channel), // .channel
.sink3_data (rsp_demux_004_src0_data), // .data
.sink3_startofpacket (rsp_demux_004_src0_startofpacket), // .startofpacket
.sink3_endofpacket (rsp_demux_004_src0_endofpacket) // .endofpacket
);
altera_avalon_st_handshake_clock_crosser #(
.DATA_WIDTH (127),
.BITS_PER_SYMBOL (127),
.USE_PACKETS (1),
.USE_CHANNEL (1),
.CHANNEL_WIDTH (5),
.USE_ERROR (0),
.ERROR_WIDTH (1),
.VALID_SYNC_DEPTH (2),
.READY_SYNC_DEPTH (2),
.USE_OUTPUT_PIPELINE (0)
) crosser (
.in_clk (clk_0_clk_clk), // in_clk.clk
.in_reset (hps_0_h2f_lw_axi_master_agent_clk_reset_reset_bridge_in_reset_reset), // in_clk_reset.reset
.out_clk (clk_stream_clk_clk), // out_clk.clk
.out_reset (alt_vip_vfr_vga_clock_reset_reset_reset_bridge_in_reset_reset), // out_clk_reset.reset
.in_ready (cmd_demux_src1_ready), // in.ready
.in_valid (cmd_demux_src1_valid), // .valid
.in_startofpacket (cmd_demux_src1_startofpacket), // .startofpacket
.in_endofpacket (cmd_demux_src1_endofpacket), // .endofpacket
.in_channel (cmd_demux_src1_channel), // .channel
.in_data (cmd_demux_src1_data), // .data
.out_ready (crosser_out_ready), // out.ready
.out_valid (crosser_out_valid), // .valid
.out_startofpacket (crosser_out_startofpacket), // .startofpacket
.out_endofpacket (crosser_out_endofpacket), // .endofpacket
.out_channel (crosser_out_channel), // .channel
.out_data (crosser_out_data), // .data
.in_empty (1'b0), // (terminated)
.in_error (1'b0), // (terminated)
.out_empty (), // (terminated)
.out_error () // (terminated)
);
altera_avalon_st_handshake_clock_crosser #(
.DATA_WIDTH (127),
.BITS_PER_SYMBOL (127),
.USE_PACKETS (1),
.USE_CHANNEL (1),
.CHANNEL_WIDTH (5),
.USE_ERROR (0),
.ERROR_WIDTH (1),
.VALID_SYNC_DEPTH (2),
.READY_SYNC_DEPTH (2),
.USE_OUTPUT_PIPELINE (0)
) crosser_001 (
.in_clk (clk_0_clk_clk), // in_clk.clk
.in_reset (hps_0_h2f_lw_axi_master_agent_clk_reset_reset_bridge_in_reset_reset), // in_clk_reset.reset
.out_clk (clk_stream_clk_clk), // out_clk.clk
.out_reset (alt_vip_vfr_vga_clock_reset_reset_reset_bridge_in_reset_reset), // out_clk_reset.reset
.in_ready (cmd_demux_001_src1_ready), // in.ready
.in_valid (cmd_demux_001_src1_valid), // .valid
.in_startofpacket (cmd_demux_001_src1_startofpacket), // .startofpacket
.in_endofpacket (cmd_demux_001_src1_endofpacket), // .endofpacket
.in_channel (cmd_demux_001_src1_channel), // .channel
.in_data (cmd_demux_001_src1_data), // .data
.out_ready (crosser_001_out_ready), // out.ready
.out_valid (crosser_001_out_valid), // .valid
.out_startofpacket (crosser_001_out_startofpacket), // .startofpacket
.out_endofpacket (crosser_001_out_endofpacket), // .endofpacket
.out_channel (crosser_001_out_channel), // .channel
.out_data (crosser_001_out_data), // .data
.in_empty (1'b0), // (terminated)
.in_error (1'b0), // (terminated)
.out_empty (), // (terminated)
.out_error () // (terminated)
);
altera_avalon_st_handshake_clock_crosser #(
.DATA_WIDTH (127),
.BITS_PER_SYMBOL (127),
.USE_PACKETS (1),
.USE_CHANNEL (1),
.CHANNEL_WIDTH (5),
.USE_ERROR (0),
.ERROR_WIDTH (1),
.VALID_SYNC_DEPTH (2),
.READY_SYNC_DEPTH (2),
.USE_OUTPUT_PIPELINE (0)
) crosser_002 (
.in_clk (clk_0_clk_clk), // in_clk.clk
.in_reset (jtag_uart_reset_reset_bridge_in_reset_reset), // in_clk_reset.reset
.out_clk (clk_stream_clk_clk), // out_clk.clk
.out_reset (alt_vip_vfr_vga_clock_reset_reset_reset_bridge_in_reset_reset), // out_clk_reset.reset
.in_ready (cmd_demux_002_src1_ready), // in.ready
.in_valid (cmd_demux_002_src1_valid), // .valid
.in_startofpacket (cmd_demux_002_src1_startofpacket), // .startofpacket
.in_endofpacket (cmd_demux_002_src1_endofpacket), // .endofpacket
.in_channel (cmd_demux_002_src1_channel), // .channel
.in_data (cmd_demux_002_src1_data), // .data
.out_ready (crosser_002_out_ready), // out.ready
.out_valid (crosser_002_out_valid), // .valid
.out_startofpacket (crosser_002_out_startofpacket), // .startofpacket
.out_endofpacket (crosser_002_out_endofpacket), // .endofpacket
.out_channel (crosser_002_out_channel), // .channel
.out_data (crosser_002_out_data), // .data
.in_empty (1'b0), // (terminated)
.in_error (1'b0), // (terminated)
.out_empty (), // (terminated)
.out_error () // (terminated)
);
altera_avalon_st_handshake_clock_crosser #(
.DATA_WIDTH (127),
.BITS_PER_SYMBOL (127),
.USE_PACKETS (1),
.USE_CHANNEL (1),
.CHANNEL_WIDTH (5),
.USE_ERROR (0),
.ERROR_WIDTH (1),
.VALID_SYNC_DEPTH (2),
.READY_SYNC_DEPTH (2),
.USE_OUTPUT_PIPELINE (0)
) crosser_003 (
.in_clk (clk_stream_clk_clk), // in_clk.clk
.in_reset (alt_vip_vfr_vga_clock_reset_reset_reset_bridge_in_reset_reset), // in_clk_reset.reset
.out_clk (clk_0_clk_clk), // out_clk.clk
.out_reset (hps_0_h2f_lw_axi_master_agent_clk_reset_reset_bridge_in_reset_reset), // out_clk_reset.reset
.in_ready (rsp_demux_001_src0_ready), // in.ready
.in_valid (rsp_demux_001_src0_valid), // .valid
.in_startofpacket (rsp_demux_001_src0_startofpacket), // .startofpacket
.in_endofpacket (rsp_demux_001_src0_endofpacket), // .endofpacket
.in_channel (rsp_demux_001_src0_channel), // .channel
.in_data (rsp_demux_001_src0_data), // .data
.out_ready (crosser_003_out_ready), // out.ready
.out_valid (crosser_003_out_valid), // .valid
.out_startofpacket (crosser_003_out_startofpacket), // .startofpacket
.out_endofpacket (crosser_003_out_endofpacket), // .endofpacket
.out_channel (crosser_003_out_channel), // .channel
.out_data (crosser_003_out_data), // .data
.in_empty (1'b0), // (terminated)
.in_error (1'b0), // (terminated)
.out_empty (), // (terminated)
.out_error () // (terminated)
);
altera_avalon_st_handshake_clock_crosser #(
.DATA_WIDTH (127),
.BITS_PER_SYMBOL (127),
.USE_PACKETS (1),
.USE_CHANNEL (1),
.CHANNEL_WIDTH (5),
.USE_ERROR (0),
.ERROR_WIDTH (1),
.VALID_SYNC_DEPTH (2),
.READY_SYNC_DEPTH (2),
.USE_OUTPUT_PIPELINE (0)
) crosser_004 (
.in_clk (clk_stream_clk_clk), // in_clk.clk
.in_reset (alt_vip_vfr_vga_clock_reset_reset_reset_bridge_in_reset_reset), // in_clk_reset.reset
.out_clk (clk_0_clk_clk), // out_clk.clk
.out_reset (hps_0_h2f_lw_axi_master_agent_clk_reset_reset_bridge_in_reset_reset), // out_clk_reset.reset
.in_ready (rsp_demux_001_src1_ready), // in.ready
.in_valid (rsp_demux_001_src1_valid), // .valid
.in_startofpacket (rsp_demux_001_src1_startofpacket), // .startofpacket
.in_endofpacket (rsp_demux_001_src1_endofpacket), // .endofpacket
.in_channel (rsp_demux_001_src1_channel), // .channel
.in_data (rsp_demux_001_src1_data), // .data
.out_ready (crosser_004_out_ready), // out.ready
.out_valid (crosser_004_out_valid), // .valid
.out_startofpacket (crosser_004_out_startofpacket), // .startofpacket
.out_endofpacket (crosser_004_out_endofpacket), // .endofpacket
.out_channel (crosser_004_out_channel), // .channel
.out_data (crosser_004_out_data), // .data
.in_empty (1'b0), // (terminated)
.in_error (1'b0), // (terminated)
.out_empty (), // (terminated)
.out_error () // (terminated)
);
altera_avalon_st_handshake_clock_crosser #(
.DATA_WIDTH (127),
.BITS_PER_SYMBOL (127),
.USE_PACKETS (1),
.USE_CHANNEL (1),
.CHANNEL_WIDTH (5),
.USE_ERROR (0),
.ERROR_WIDTH (1),
.VALID_SYNC_DEPTH (2),
.READY_SYNC_DEPTH (2),
.USE_OUTPUT_PIPELINE (0)
) crosser_005 (
.in_clk (clk_stream_clk_clk), // in_clk.clk
.in_reset (alt_vip_vfr_vga_clock_reset_reset_reset_bridge_in_reset_reset), // in_clk_reset.reset
.out_clk (clk_0_clk_clk), // out_clk.clk
.out_reset (jtag_uart_reset_reset_bridge_in_reset_reset), // out_clk_reset.reset
.in_ready (rsp_demux_001_src2_ready), // in.ready
.in_valid (rsp_demux_001_src2_valid), // .valid
.in_startofpacket (rsp_demux_001_src2_startofpacket), // .startofpacket
.in_endofpacket (rsp_demux_001_src2_endofpacket), // .endofpacket
.in_channel (rsp_demux_001_src2_channel), // .channel
.in_data (rsp_demux_001_src2_data), // .data
.out_ready (crosser_005_out_ready), // out.ready
.out_valid (crosser_005_out_valid), // .valid
.out_startofpacket (crosser_005_out_startofpacket), // .startofpacket
.out_endofpacket (crosser_005_out_endofpacket), // .endofpacket
.out_channel (crosser_005_out_channel), // .channel
.out_data (crosser_005_out_data), // .data
.in_empty (1'b0), // (terminated)
.in_error (1'b0), // (terminated)
.out_empty (), // (terminated)
.out_error () // (terminated)
);
soc_system_mm_interconnect_1_avalon_st_adapter #(
.inBitsPerSymbol (34),
.inUsePackets (0),
.inDataWidth (34),
.inChannelWidth (0),
.inErrorWidth (0),
.inUseEmptyPort (0),
.inUseValid (1),
.inUseReady (1),
.inReadyLatency (0),
.outDataWidth (34),
.outChannelWidth (0),
.outErrorWidth (1),
.outUseEmptyPort (0),
.outUseValid (1),
.outUseReady (1),
.outReadyLatency (0)
) avalon_st_adapter (
.in_clk_0_clk (clk_0_clk_clk), // in_clk_0.clk
.in_rst_0_reset (jtag_uart_reset_reset_bridge_in_reset_reset), // in_rst_0.reset
.in_0_data (jtag_uart_avalon_jtag_slave_agent_rdata_fifo_out_data), // in_0.data
.in_0_valid (jtag_uart_avalon_jtag_slave_agent_rdata_fifo_out_valid), // .valid
.in_0_ready (jtag_uart_avalon_jtag_slave_agent_rdata_fifo_out_ready), // .ready
.out_0_data (avalon_st_adapter_out_0_data), // out_0.data
.out_0_valid (avalon_st_adapter_out_0_valid), // .valid
.out_0_ready (avalon_st_adapter_out_0_ready), // .ready
.out_0_error (avalon_st_adapter_out_0_error) // .error
);
soc_system_mm_interconnect_1_avalon_st_adapter #(
.inBitsPerSymbol (34),
.inUsePackets (0),
.inDataWidth (34),
.inChannelWidth (0),
.inErrorWidth (0),
.inUseEmptyPort (0),
.inUseValid (1),
.inUseReady (1),
.inReadyLatency (0),
.outDataWidth (34),
.outChannelWidth (0),
.outErrorWidth (1),
.outUseEmptyPort (0),
.outUseValid (1),
.outUseReady (1),
.outReadyLatency (0)
) avalon_st_adapter_001 (
.in_clk_0_clk (clk_stream_clk_clk), // in_clk_0.clk
.in_rst_0_reset (alt_vip_vfr_vga_clock_reset_reset_reset_bridge_in_reset_reset), // in_rst_0.reset
.in_0_data (alt_vip_vfr_vga_avalon_slave_agent_rdata_fifo_out_data), // in_0.data
.in_0_valid (alt_vip_vfr_vga_avalon_slave_agent_rdata_fifo_out_valid), // .valid
.in_0_ready (alt_vip_vfr_vga_avalon_slave_agent_rdata_fifo_out_ready), // .ready
.out_0_data (avalon_st_adapter_001_out_0_data), // out_0.data
.out_0_valid (avalon_st_adapter_001_out_0_valid), // .valid
.out_0_ready (avalon_st_adapter_001_out_0_ready), // .ready
.out_0_error (avalon_st_adapter_001_out_0_error) // .error
);
soc_system_mm_interconnect_1_avalon_st_adapter #(
.inBitsPerSymbol (34),
.inUsePackets (0),
.inDataWidth (34),
.inChannelWidth (0),
.inErrorWidth (0),
.inUseEmptyPort (0),
.inUseValid (1),
.inUseReady (1),
.inReadyLatency (0),
.outDataWidth (34),
.outChannelWidth (0),
.outErrorWidth (1),
.outUseEmptyPort (0),
.outUseValid (1),
.outUseReady (1),
.outReadyLatency (0)
) avalon_st_adapter_002 (
.in_clk_0_clk (clk_0_clk_clk), // in_clk_0.clk
.in_rst_0_reset (ece453_0_clock_reset_reset_bridge_in_reset_reset), // in_rst_0.reset
.in_0_data (ece453_0_avalon_slave_0_agent_rdata_fifo_out_data), // in_0.data
.in_0_valid (ece453_0_avalon_slave_0_agent_rdata_fifo_out_valid), // .valid
.in_0_ready (ece453_0_avalon_slave_0_agent_rdata_fifo_out_ready), // .ready
.out_0_data (avalon_st_adapter_002_out_0_data), // out_0.data
.out_0_valid (avalon_st_adapter_002_out_0_valid), // .valid
.out_0_ready (avalon_st_adapter_002_out_0_ready), // .ready
.out_0_error (avalon_st_adapter_002_out_0_error) // .error
);
soc_system_mm_interconnect_1_avalon_st_adapter #(
.inBitsPerSymbol (34),
.inUsePackets (0),
.inDataWidth (34),
.inChannelWidth (0),
.inErrorWidth (0),
.inUseEmptyPort (0),
.inUseValid (1),
.inUseReady (1),
.inReadyLatency (0),
.outDataWidth (34),
.outChannelWidth (0),
.outErrorWidth (1),
.outUseEmptyPort (0),
.outUseValid (1),
.outUseReady (1),
.outReadyLatency (0)
) avalon_st_adapter_003 (
.in_clk_0_clk (clk_0_clk_clk), // in_clk_0.clk
.in_rst_0_reset (jtag_uart_reset_reset_bridge_in_reset_reset), // in_rst_0.reset
.in_0_data (sysid_qsys_control_slave_agent_rdata_fifo_out_data), // in_0.data
.in_0_valid (sysid_qsys_control_slave_agent_rdata_fifo_out_valid), // .valid
.in_0_ready (sysid_qsys_control_slave_agent_rdata_fifo_out_ready), // .ready
.out_0_data (avalon_st_adapter_003_out_0_data), // out_0.data
.out_0_valid (avalon_st_adapter_003_out_0_valid), // .valid
.out_0_ready (avalon_st_adapter_003_out_0_ready), // .ready
.out_0_error (avalon_st_adapter_003_out_0_error) // .error
);
soc_system_mm_interconnect_1_avalon_st_adapter #(
.inBitsPerSymbol (34),
.inUsePackets (0),
.inDataWidth (34),
.inChannelWidth (0),
.inErrorWidth (0),
.inUseEmptyPort (0),
.inUseValid (1),
.inUseReady (1),
.inReadyLatency (0),
.outDataWidth (34),
.outChannelWidth (0),
.outErrorWidth (1),
.outUseEmptyPort (0),
.outUseValid (1),
.outUseReady (1),
.outReadyLatency (0)
) avalon_st_adapter_004 (
.in_clk_0_clk (clk_0_clk_clk), // in_clk_0.clk
.in_rst_0_reset (jtag_uart_reset_reset_bridge_in_reset_reset), // in_rst_0.reset
.in_0_data (intr_capturer_0_avalon_slave_0_agent_rdata_fifo_out_data), // in_0.data
.in_0_valid (intr_capturer_0_avalon_slave_0_agent_rdata_fifo_out_valid), // .valid
.in_0_ready (intr_capturer_0_avalon_slave_0_agent_rdata_fifo_out_ready), // .ready
.out_0_data (avalon_st_adapter_004_out_0_data), // out_0.data
.out_0_valid (avalon_st_adapter_004_out_0_valid), // .valid
.out_0_ready (avalon_st_adapter_004_out_0_ready), // .ready
.out_0_error (avalon_st_adapter_004_out_0_error) // .error
);
endmodule
|
module top(
output reg serial_tx,
input serial_rx,
(* dont_touch = "true" *) input clk100,
input cpu_reset,
output [13:0] ddram_a,
output [2:0] ddram_ba,
output ddram_ras_n,
output ddram_cas_n,
output ddram_we_n,
output ddram_cs_n,
output [1:0] ddram_dm,
inout [15:0] ddram_dq,
output [1:0] ddram_dqs_p,
output [1:0] ddram_dqs_n,
output ddram_clk_p,
output ddram_clk_n,
output ddram_cke,
output ddram_odt,
output ddram_reset_n
);
wire main_ctrl_reset_reset_re;
wire main_ctrl_reset_reset_r;
wire main_ctrl_reset_reset_we;
reg main_ctrl_reset_reset_w = 1'd0;
reg [31:0] main_ctrl_storage = 32'd305419896;
reg main_ctrl_re = 1'd0;
wire [31:0] main_ctrl_bus_errors_status;
wire main_ctrl_bus_errors_we;
wire main_ctrl_reset;
wire main_ctrl_bus_error;
reg [31:0] main_ctrl_bus_errors = 32'd0;
wire main_cpu_reset;
wire [29:0] main_cpu_ibus_adr;
wire [31:0] main_cpu_ibus_dat_w;
wire [31:0] main_cpu_ibus_dat_r;
wire [3:0] main_cpu_ibus_sel;
wire main_cpu_ibus_cyc;
wire main_cpu_ibus_stb;
wire main_cpu_ibus_ack;
wire main_cpu_ibus_we;
wire [2:0] main_cpu_ibus_cti;
wire [1:0] main_cpu_ibus_bte;
wire main_cpu_ibus_err;
wire [29:0] main_cpu_dbus_adr;
wire [31:0] main_cpu_dbus_dat_w;
wire [31:0] main_cpu_dbus_dat_r;
wire [3:0] main_cpu_dbus_sel;
wire main_cpu_dbus_cyc;
wire main_cpu_dbus_stb;
wire main_cpu_dbus_ack;
wire main_cpu_dbus_we;
wire [2:0] main_cpu_dbus_cti;
wire [1:0] main_cpu_dbus_bte;
wire main_cpu_dbus_err;
reg [31:0] main_cpu_interrupt = 32'd0;
wire [29:0] main_interface0_soc_bus_adr;
wire [31:0] main_interface0_soc_bus_dat_w;
wire [31:0] main_interface0_soc_bus_dat_r;
wire [3:0] main_interface0_soc_bus_sel;
wire main_interface0_soc_bus_cyc;
wire main_interface0_soc_bus_stb;
wire main_interface0_soc_bus_ack;
wire main_interface0_soc_bus_we;
wire [2:0] main_interface0_soc_bus_cti;
wire [1:0] main_interface0_soc_bus_bte;
wire main_interface0_soc_bus_err;
wire [29:0] main_interface1_soc_bus_adr;
wire [31:0] main_interface1_soc_bus_dat_w;
wire [31:0] main_interface1_soc_bus_dat_r;
wire [3:0] main_interface1_soc_bus_sel;
wire main_interface1_soc_bus_cyc;
wire main_interface1_soc_bus_stb;
wire main_interface1_soc_bus_ack;
wire main_interface1_soc_bus_we;
wire [2:0] main_interface1_soc_bus_cti;
wire [1:0] main_interface1_soc_bus_bte;
wire main_interface1_soc_bus_err;
wire [29:0] main_rom_bus_adr;
wire [31:0] main_rom_bus_dat_w;
wire [31:0] main_rom_bus_dat_r;
wire [3:0] main_rom_bus_sel;
wire main_rom_bus_cyc;
wire main_rom_bus_stb;
reg main_rom_bus_ack = 1'd0;
wire main_rom_bus_we;
wire [2:0] main_rom_bus_cti;
wire [1:0] main_rom_bus_bte;
reg main_rom_bus_err = 1'd0;
wire [12:0] main_rom_adr;
wire [31:0] main_rom_dat_r;
wire [29:0] main_sram_bus_adr;
wire [31:0] main_sram_bus_dat_w;
wire [31:0] main_sram_bus_dat_r;
wire [3:0] main_sram_bus_sel;
wire main_sram_bus_cyc;
wire main_sram_bus_stb;
reg main_sram_bus_ack = 1'd0;
wire main_sram_bus_we;
wire [2:0] main_sram_bus_cti;
wire [1:0] main_sram_bus_bte;
reg main_sram_bus_err = 1'd0;
wire [12:0] main_sram_adr;
wire [31:0] main_sram_dat_r;
reg [3:0] main_sram_we = 4'd0;
wire [31:0] main_sram_dat_w;
reg [31:0] main_uart_phy_storage = 32'd9895604;
reg main_uart_phy_re = 1'd0;
wire main_uart_phy_sink_valid;
reg main_uart_phy_sink_ready = 1'd0;
wire main_uart_phy_sink_first;
wire main_uart_phy_sink_last;
wire [7:0] main_uart_phy_sink_payload_data;
reg main_uart_phy_uart_clk_txen = 1'd0;
reg [31:0] main_uart_phy_phase_accumulator_tx = 32'd0;
reg [7:0] main_uart_phy_tx_reg = 8'd0;
reg [3:0] main_uart_phy_tx_bitcount = 4'd0;
reg main_uart_phy_tx_busy = 1'd0;
reg main_uart_phy_source_valid = 1'd0;
wire main_uart_phy_source_ready;
reg main_uart_phy_source_first = 1'd0;
reg main_uart_phy_source_last = 1'd0;
reg [7:0] main_uart_phy_source_payload_data = 8'd0;
reg main_uart_phy_uart_clk_rxen = 1'd0;
reg [31:0] main_uart_phy_phase_accumulator_rx = 32'd0;
wire main_uart_phy_rx;
reg main_uart_phy_rx_r = 1'd0;
reg [7:0] main_uart_phy_rx_reg = 8'd0;
reg [3:0] main_uart_phy_rx_bitcount = 4'd0;
reg main_uart_phy_rx_busy = 1'd0;
wire main_uart_rxtx_re;
wire [7:0] main_uart_rxtx_r;
wire main_uart_rxtx_we;
wire [7:0] main_uart_rxtx_w;
wire main_uart_txfull_status;
wire main_uart_txfull_we;
wire main_uart_rxempty_status;
wire main_uart_rxempty_we;
wire main_uart_irq;
wire main_uart_tx_status;
reg main_uart_tx_pending = 1'd0;
wire main_uart_tx_trigger;
reg main_uart_tx_clear = 1'd0;
reg main_uart_tx_old_trigger = 1'd0;
wire main_uart_rx_status;
reg main_uart_rx_pending = 1'd0;
wire main_uart_rx_trigger;
reg main_uart_rx_clear = 1'd0;
reg main_uart_rx_old_trigger = 1'd0;
wire main_uart_eventmanager_status_re;
wire [1:0] main_uart_eventmanager_status_r;
wire main_uart_eventmanager_status_we;
reg [1:0] main_uart_eventmanager_status_w = 2'd0;
wire main_uart_eventmanager_pending_re;
wire [1:0] main_uart_eventmanager_pending_r;
wire main_uart_eventmanager_pending_we;
reg [1:0] main_uart_eventmanager_pending_w = 2'd0;
reg [1:0] main_uart_eventmanager_storage = 2'd0;
reg main_uart_eventmanager_re = 1'd0;
wire main_uart_tx_fifo_sink_valid;
wire main_uart_tx_fifo_sink_ready;
reg main_uart_tx_fifo_sink_first = 1'd0;
reg main_uart_tx_fifo_sink_last = 1'd0;
wire [7:0] main_uart_tx_fifo_sink_payload_data;
wire main_uart_tx_fifo_source_valid;
wire main_uart_tx_fifo_source_ready;
wire main_uart_tx_fifo_source_first;
wire main_uart_tx_fifo_source_last;
wire [7:0] main_uart_tx_fifo_source_payload_data;
wire main_uart_tx_fifo_re;
reg main_uart_tx_fifo_readable = 1'd0;
wire main_uart_tx_fifo_syncfifo_we;
wire main_uart_tx_fifo_syncfifo_writable;
wire main_uart_tx_fifo_syncfifo_re;
wire main_uart_tx_fifo_syncfifo_readable;
wire [9:0] main_uart_tx_fifo_syncfifo_din;
wire [9:0] main_uart_tx_fifo_syncfifo_dout;
reg [4:0] main_uart_tx_fifo_level0 = 5'd0;
reg main_uart_tx_fifo_replace = 1'd0;
reg [3:0] main_uart_tx_fifo_produce = 4'd0;
reg [3:0] main_uart_tx_fifo_consume = 4'd0;
reg [3:0] main_uart_tx_fifo_wrport_adr = 4'd0;
wire [9:0] main_uart_tx_fifo_wrport_dat_r;
wire main_uart_tx_fifo_wrport_we;
wire [9:0] main_uart_tx_fifo_wrport_dat_w;
wire main_uart_tx_fifo_do_read;
wire [3:0] main_uart_tx_fifo_rdport_adr;
wire [9:0] main_uart_tx_fifo_rdport_dat_r;
wire main_uart_tx_fifo_rdport_re;
wire [4:0] main_uart_tx_fifo_level1;
wire [7:0] main_uart_tx_fifo_fifo_in_payload_data;
wire main_uart_tx_fifo_fifo_in_first;
wire main_uart_tx_fifo_fifo_in_last;
wire [7:0] main_uart_tx_fifo_fifo_out_payload_data;
wire main_uart_tx_fifo_fifo_out_first;
wire main_uart_tx_fifo_fifo_out_last;
wire main_uart_rx_fifo_sink_valid;
wire main_uart_rx_fifo_sink_ready;
wire main_uart_rx_fifo_sink_first;
wire main_uart_rx_fifo_sink_last;
wire [7:0] main_uart_rx_fifo_sink_payload_data;
wire main_uart_rx_fifo_source_valid;
wire main_uart_rx_fifo_source_ready;
wire main_uart_rx_fifo_source_first;
wire main_uart_rx_fifo_source_last;
wire [7:0] main_uart_rx_fifo_source_payload_data;
wire main_uart_rx_fifo_re;
reg main_uart_rx_fifo_readable = 1'd0;
wire main_uart_rx_fifo_syncfifo_we;
wire main_uart_rx_fifo_syncfifo_writable;
wire main_uart_rx_fifo_syncfifo_re;
wire main_uart_rx_fifo_syncfifo_readable;
wire [9:0] main_uart_rx_fifo_syncfifo_din;
wire [9:0] main_uart_rx_fifo_syncfifo_dout;
reg [4:0] main_uart_rx_fifo_level0 = 5'd0;
reg main_uart_rx_fifo_replace = 1'd0;
reg [3:0] main_uart_rx_fifo_produce = 4'd0;
reg [3:0] main_uart_rx_fifo_consume = 4'd0;
reg [3:0] main_uart_rx_fifo_wrport_adr = 4'd0;
wire [9:0] main_uart_rx_fifo_wrport_dat_r;
wire main_uart_rx_fifo_wrport_we;
wire [9:0] main_uart_rx_fifo_wrport_dat_w;
wire main_uart_rx_fifo_do_read;
wire [3:0] main_uart_rx_fifo_rdport_adr;
wire [9:0] main_uart_rx_fifo_rdport_dat_r;
wire main_uart_rx_fifo_rdport_re;
wire [4:0] main_uart_rx_fifo_level1;
wire [7:0] main_uart_rx_fifo_fifo_in_payload_data;
wire main_uart_rx_fifo_fifo_in_first;
wire main_uart_rx_fifo_fifo_in_last;
wire [7:0] main_uart_rx_fifo_fifo_out_payload_data;
wire main_uart_rx_fifo_fifo_out_first;
wire main_uart_rx_fifo_fifo_out_last;
reg main_uart_reset = 1'd0;
reg [31:0] main_timer0_load_storage = 32'd0;
reg main_timer0_load_re = 1'd0;
reg [31:0] main_timer0_reload_storage = 32'd0;
reg main_timer0_reload_re = 1'd0;
reg main_timer0_en_storage = 1'd0;
reg main_timer0_en_re = 1'd0;
reg main_timer0_update_value_storage = 1'd0;
reg main_timer0_update_value_re = 1'd0;
reg [31:0] main_timer0_value_status = 32'd0;
wire main_timer0_value_we;
wire main_timer0_irq;
wire main_timer0_zero_status;
reg main_timer0_zero_pending = 1'd0;
wire main_timer0_zero_trigger;
reg main_timer0_zero_clear = 1'd0;
reg main_timer0_zero_old_trigger = 1'd0;
wire main_timer0_eventmanager_status_re;
wire main_timer0_eventmanager_status_r;
wire main_timer0_eventmanager_status_we;
wire main_timer0_eventmanager_status_w;
wire main_timer0_eventmanager_pending_re;
wire main_timer0_eventmanager_pending_r;
wire main_timer0_eventmanager_pending_we;
wire main_timer0_eventmanager_pending_w;
reg main_timer0_eventmanager_storage = 1'd0;
reg main_timer0_eventmanager_re = 1'd0;
reg [31:0] main_timer0_value = 32'd0;
reg [13:0] main_interface_adr = 14'd0;
reg main_interface_we = 1'd0;
wire [7:0] main_interface_dat_w;
wire [7:0] main_interface_dat_r;
wire [29:0] main_bus_wishbone_adr;
wire [31:0] main_bus_wishbone_dat_w;
wire [31:0] main_bus_wishbone_dat_r;
wire [3:0] main_bus_wishbone_sel;
wire main_bus_wishbone_cyc;
wire main_bus_wishbone_stb;
reg main_bus_wishbone_ack = 1'd0;
wire main_bus_wishbone_we;
wire [2:0] main_bus_wishbone_cti;
wire [1:0] main_bus_wishbone_bte;
reg main_bus_wishbone_err = 1'd0;
wire [29:0] main_interface0_wb_sdram_adr;
wire [31:0] main_interface0_wb_sdram_dat_w;
reg [31:0] main_interface0_wb_sdram_dat_r = 32'd0;
wire [3:0] main_interface0_wb_sdram_sel;
wire main_interface0_wb_sdram_cyc;
wire main_interface0_wb_sdram_stb;
reg main_interface0_wb_sdram_ack = 1'd0;
wire main_interface0_wb_sdram_we;
wire [2:0] main_interface0_wb_sdram_cti;
wire [1:0] main_interface0_wb_sdram_bte;
reg main_interface0_wb_sdram_err = 1'd0;
wire sys_clk;
wire sys_rst;
wire sys4x_clk;
wire sys4x_dqs_clk;
wire clk200_clk;
wire clk200_rst;
wire main_pll_clkin;
wire main_reset;
wire main_locked;
wire main_clkin;
wire main_clkout0;
wire main_clkout_buf0;
wire main_clkout1;
wire main_clkout_buf1;
wire main_clkout2;
wire main_clkout_buf2;
wire main_clkout3;
wire main_clkout_buf3;
reg [3:0] main_reset_counter = 4'd15;
reg main_ic_reset = 1'd1;
reg [4:0] main_a7ddrphy_half_sys8x_taps_storage = 5'd16;
reg main_a7ddrphy_half_sys8x_taps_re = 1'd0;
wire main_a7ddrphy_cdly_rst_re;
wire main_a7ddrphy_cdly_rst_r;
wire main_a7ddrphy_cdly_rst_we;
reg main_a7ddrphy_cdly_rst_w = 1'd0;
wire main_a7ddrphy_cdly_inc_re;
wire main_a7ddrphy_cdly_inc_r;
wire main_a7ddrphy_cdly_inc_we;
reg main_a7ddrphy_cdly_inc_w = 1'd0;
reg [1:0] main_a7ddrphy_dly_sel_storage = 2'd0;
reg main_a7ddrphy_dly_sel_re = 1'd0;
wire main_a7ddrphy_rdly_dq_rst_re;
wire main_a7ddrphy_rdly_dq_rst_r;
wire main_a7ddrphy_rdly_dq_rst_we;
reg main_a7ddrphy_rdly_dq_rst_w = 1'd0;
wire main_a7ddrphy_rdly_dq_inc_re;
wire main_a7ddrphy_rdly_dq_inc_r;
wire main_a7ddrphy_rdly_dq_inc_we;
reg main_a7ddrphy_rdly_dq_inc_w = 1'd0;
wire main_a7ddrphy_rdly_dq_bitslip_rst_re;
wire main_a7ddrphy_rdly_dq_bitslip_rst_r;
wire main_a7ddrphy_rdly_dq_bitslip_rst_we;
reg main_a7ddrphy_rdly_dq_bitslip_rst_w = 1'd0;
wire main_a7ddrphy_rdly_dq_bitslip_re;
wire main_a7ddrphy_rdly_dq_bitslip_r;
wire main_a7ddrphy_rdly_dq_bitslip_we;
reg main_a7ddrphy_rdly_dq_bitslip_w = 1'd0;
wire [13:0] main_a7ddrphy_dfi_p0_address;
wire [2:0] main_a7ddrphy_dfi_p0_bank;
wire main_a7ddrphy_dfi_p0_cas_n;
wire main_a7ddrphy_dfi_p0_cs_n;
wire main_a7ddrphy_dfi_p0_ras_n;
wire main_a7ddrphy_dfi_p0_we_n;
wire main_a7ddrphy_dfi_p0_cke;
wire main_a7ddrphy_dfi_p0_odt;
wire main_a7ddrphy_dfi_p0_reset_n;
wire main_a7ddrphy_dfi_p0_act_n;
wire [31:0] main_a7ddrphy_dfi_p0_wrdata;
wire main_a7ddrphy_dfi_p0_wrdata_en;
wire [3:0] main_a7ddrphy_dfi_p0_wrdata_mask;
wire main_a7ddrphy_dfi_p0_rddata_en;
reg [31:0] main_a7ddrphy_dfi_p0_rddata = 32'd0;
reg main_a7ddrphy_dfi_p0_rddata_valid = 1'd0;
wire [13:0] main_a7ddrphy_dfi_p1_address;
wire [2:0] main_a7ddrphy_dfi_p1_bank;
wire main_a7ddrphy_dfi_p1_cas_n;
wire main_a7ddrphy_dfi_p1_cs_n;
wire main_a7ddrphy_dfi_p1_ras_n;
wire main_a7ddrphy_dfi_p1_we_n;
wire main_a7ddrphy_dfi_p1_cke;
wire main_a7ddrphy_dfi_p1_odt;
wire main_a7ddrphy_dfi_p1_reset_n;
wire main_a7ddrphy_dfi_p1_act_n;
wire [31:0] main_a7ddrphy_dfi_p1_wrdata;
wire main_a7ddrphy_dfi_p1_wrdata_en;
wire [3:0] main_a7ddrphy_dfi_p1_wrdata_mask;
wire main_a7ddrphy_dfi_p1_rddata_en;
reg [31:0] main_a7ddrphy_dfi_p1_rddata = 32'd0;
reg main_a7ddrphy_dfi_p1_rddata_valid = 1'd0;
wire [13:0] main_a7ddrphy_dfi_p2_address;
wire [2:0] main_a7ddrphy_dfi_p2_bank;
wire main_a7ddrphy_dfi_p2_cas_n;
wire main_a7ddrphy_dfi_p2_cs_n;
wire main_a7ddrphy_dfi_p2_ras_n;
wire main_a7ddrphy_dfi_p2_we_n;
wire main_a7ddrphy_dfi_p2_cke;
wire main_a7ddrphy_dfi_p2_odt;
wire main_a7ddrphy_dfi_p2_reset_n;
wire main_a7ddrphy_dfi_p2_act_n;
wire [31:0] main_a7ddrphy_dfi_p2_wrdata;
wire main_a7ddrphy_dfi_p2_wrdata_en;
wire [3:0] main_a7ddrphy_dfi_p2_wrdata_mask;
wire main_a7ddrphy_dfi_p2_rddata_en;
reg [31:0] main_a7ddrphy_dfi_p2_rddata = 32'd0;
reg main_a7ddrphy_dfi_p2_rddata_valid = 1'd0;
wire [13:0] main_a7ddrphy_dfi_p3_address;
wire [2:0] main_a7ddrphy_dfi_p3_bank;
wire main_a7ddrphy_dfi_p3_cas_n;
wire main_a7ddrphy_dfi_p3_cs_n;
wire main_a7ddrphy_dfi_p3_ras_n;
wire main_a7ddrphy_dfi_p3_we_n;
wire main_a7ddrphy_dfi_p3_cke;
wire main_a7ddrphy_dfi_p3_odt;
wire main_a7ddrphy_dfi_p3_reset_n;
wire main_a7ddrphy_dfi_p3_act_n;
wire [31:0] main_a7ddrphy_dfi_p3_wrdata;
wire main_a7ddrphy_dfi_p3_wrdata_en;
wire [3:0] main_a7ddrphy_dfi_p3_wrdata_mask;
wire main_a7ddrphy_dfi_p3_rddata_en;
reg [31:0] main_a7ddrphy_dfi_p3_rddata = 32'd0;
reg main_a7ddrphy_dfi_p3_rddata_valid = 1'd0;
wire main_a7ddrphy_sd_clk_se_nodelay;
reg main_a7ddrphy_oe_dqs = 1'd0;
wire main_a7ddrphy_dqs_preamble;
wire main_a7ddrphy_dqs_postamble;
reg [7:0] main_a7ddrphy_dqs_serdes_pattern = 8'd85;
wire main_a7ddrphy_dqs_nodelay0;
wire main_a7ddrphy_dqs_t0;
wire main_a7ddrphy0;
wire main_a7ddrphy_dqs_nodelay1;
wire main_a7ddrphy_dqs_t1;
wire main_a7ddrphy1;
reg main_a7ddrphy_oe_dq = 1'd0;
wire main_a7ddrphy_dq_o_nodelay0;
wire main_a7ddrphy_dq_i_nodelay0;
wire main_a7ddrphy_dq_i_delayed0;
wire main_a7ddrphy_dq_t0;
wire [7:0] main_a7ddrphy_dq_i_data0;
wire [7:0] main_a7ddrphy_bitslip0_i;
reg [7:0] main_a7ddrphy_bitslip0_o = 8'd0;
reg [2:0] main_a7ddrphy_bitslip0_value = 3'd0;
reg [15:0] main_a7ddrphy_bitslip0_r = 16'd0;
wire main_a7ddrphy_dq_o_nodelay1;
wire main_a7ddrphy_dq_i_nodelay1;
wire main_a7ddrphy_dq_i_delayed1;
wire main_a7ddrphy_dq_t1;
wire [7:0] main_a7ddrphy_dq_i_data1;
wire [7:0] main_a7ddrphy_bitslip1_i;
reg [7:0] main_a7ddrphy_bitslip1_o = 8'd0;
reg [2:0] main_a7ddrphy_bitslip1_value = 3'd0;
reg [15:0] main_a7ddrphy_bitslip1_r = 16'd0;
wire main_a7ddrphy_dq_o_nodelay2;
wire main_a7ddrphy_dq_i_nodelay2;
wire main_a7ddrphy_dq_i_delayed2;
wire main_a7ddrphy_dq_t2;
wire [7:0] main_a7ddrphy_dq_i_data2;
wire [7:0] main_a7ddrphy_bitslip2_i;
reg [7:0] main_a7ddrphy_bitslip2_o = 8'd0;
reg [2:0] main_a7ddrphy_bitslip2_value = 3'd0;
reg [15:0] main_a7ddrphy_bitslip2_r = 16'd0;
wire main_a7ddrphy_dq_o_nodelay3;
wire main_a7ddrphy_dq_i_nodelay3;
wire main_a7ddrphy_dq_i_delayed3;
wire main_a7ddrphy_dq_t3;
wire [7:0] main_a7ddrphy_dq_i_data3;
wire [7:0] main_a7ddrphy_bitslip3_i;
reg [7:0] main_a7ddrphy_bitslip3_o = 8'd0;
reg [2:0] main_a7ddrphy_bitslip3_value = 3'd0;
reg [15:0] main_a7ddrphy_bitslip3_r = 16'd0;
wire main_a7ddrphy_dq_o_nodelay4;
wire main_a7ddrphy_dq_i_nodelay4;
wire main_a7ddrphy_dq_i_delayed4;
wire main_a7ddrphy_dq_t4;
wire [7:0] main_a7ddrphy_dq_i_data4;
wire [7:0] main_a7ddrphy_bitslip4_i;
reg [7:0] main_a7ddrphy_bitslip4_o = 8'd0;
reg [2:0] main_a7ddrphy_bitslip4_value = 3'd0;
reg [15:0] main_a7ddrphy_bitslip4_r = 16'd0;
wire main_a7ddrphy_dq_o_nodelay5;
wire main_a7ddrphy_dq_i_nodelay5;
wire main_a7ddrphy_dq_i_delayed5;
wire main_a7ddrphy_dq_t5;
wire [7:0] main_a7ddrphy_dq_i_data5;
wire [7:0] main_a7ddrphy_bitslip5_i;
reg [7:0] main_a7ddrphy_bitslip5_o = 8'd0;
reg [2:0] main_a7ddrphy_bitslip5_value = 3'd0;
reg [15:0] main_a7ddrphy_bitslip5_r = 16'd0;
wire main_a7ddrphy_dq_o_nodelay6;
wire main_a7ddrphy_dq_i_nodelay6;
wire main_a7ddrphy_dq_i_delayed6;
wire main_a7ddrphy_dq_t6;
wire [7:0] main_a7ddrphy_dq_i_data6;
wire [7:0] main_a7ddrphy_bitslip6_i;
reg [7:0] main_a7ddrphy_bitslip6_o = 8'd0;
reg [2:0] main_a7ddrphy_bitslip6_value = 3'd0;
reg [15:0] main_a7ddrphy_bitslip6_r = 16'd0;
wire main_a7ddrphy_dq_o_nodelay7;
wire main_a7ddrphy_dq_i_nodelay7;
wire main_a7ddrphy_dq_i_delayed7;
wire main_a7ddrphy_dq_t7;
wire [7:0] main_a7ddrphy_dq_i_data7;
wire [7:0] main_a7ddrphy_bitslip7_i;
reg [7:0] main_a7ddrphy_bitslip7_o = 8'd0;
reg [2:0] main_a7ddrphy_bitslip7_value = 3'd0;
reg [15:0] main_a7ddrphy_bitslip7_r = 16'd0;
wire main_a7ddrphy_dq_o_nodelay8;
wire main_a7ddrphy_dq_i_nodelay8;
wire main_a7ddrphy_dq_i_delayed8;
wire main_a7ddrphy_dq_t8;
wire [7:0] main_a7ddrphy_dq_i_data8;
wire [7:0] main_a7ddrphy_bitslip8_i;
reg [7:0] main_a7ddrphy_bitslip8_o = 8'd0;
reg [2:0] main_a7ddrphy_bitslip8_value = 3'd0;
reg [15:0] main_a7ddrphy_bitslip8_r = 16'd0;
wire main_a7ddrphy_dq_o_nodelay9;
wire main_a7ddrphy_dq_i_nodelay9;
wire main_a7ddrphy_dq_i_delayed9;
wire main_a7ddrphy_dq_t9;
wire [7:0] main_a7ddrphy_dq_i_data9;
wire [7:0] main_a7ddrphy_bitslip9_i;
reg [7:0] main_a7ddrphy_bitslip9_o = 8'd0;
reg [2:0] main_a7ddrphy_bitslip9_value = 3'd0;
reg [15:0] main_a7ddrphy_bitslip9_r = 16'd0;
wire main_a7ddrphy_dq_o_nodelay10;
wire main_a7ddrphy_dq_i_nodelay10;
wire main_a7ddrphy_dq_i_delayed10;
wire main_a7ddrphy_dq_t10;
wire [7:0] main_a7ddrphy_dq_i_data10;
wire [7:0] main_a7ddrphy_bitslip10_i;
reg [7:0] main_a7ddrphy_bitslip10_o = 8'd0;
reg [2:0] main_a7ddrphy_bitslip10_value = 3'd0;
reg [15:0] main_a7ddrphy_bitslip10_r = 16'd0;
wire main_a7ddrphy_dq_o_nodelay11;
wire main_a7ddrphy_dq_i_nodelay11;
wire main_a7ddrphy_dq_i_delayed11;
wire main_a7ddrphy_dq_t11;
wire [7:0] main_a7ddrphy_dq_i_data11;
wire [7:0] main_a7ddrphy_bitslip11_i;
reg [7:0] main_a7ddrphy_bitslip11_o = 8'd0;
reg [2:0] main_a7ddrphy_bitslip11_value = 3'd0;
reg [15:0] main_a7ddrphy_bitslip11_r = 16'd0;
wire main_a7ddrphy_dq_o_nodelay12;
wire main_a7ddrphy_dq_i_nodelay12;
wire main_a7ddrphy_dq_i_delayed12;
wire main_a7ddrphy_dq_t12;
wire [7:0] main_a7ddrphy_dq_i_data12;
wire [7:0] main_a7ddrphy_bitslip12_i;
reg [7:0] main_a7ddrphy_bitslip12_o = 8'd0;
reg [2:0] main_a7ddrphy_bitslip12_value = 3'd0;
reg [15:0] main_a7ddrphy_bitslip12_r = 16'd0;
wire main_a7ddrphy_dq_o_nodelay13;
wire main_a7ddrphy_dq_i_nodelay13;
wire main_a7ddrphy_dq_i_delayed13;
wire main_a7ddrphy_dq_t13;
wire [7:0] main_a7ddrphy_dq_i_data13;
wire [7:0] main_a7ddrphy_bitslip13_i;
reg [7:0] main_a7ddrphy_bitslip13_o = 8'd0;
reg [2:0] main_a7ddrphy_bitslip13_value = 3'd0;
reg [15:0] main_a7ddrphy_bitslip13_r = 16'd0;
wire main_a7ddrphy_dq_o_nodelay14;
wire main_a7ddrphy_dq_i_nodelay14;
wire main_a7ddrphy_dq_i_delayed14;
wire main_a7ddrphy_dq_t14;
wire [7:0] main_a7ddrphy_dq_i_data14;
wire [7:0] main_a7ddrphy_bitslip14_i;
reg [7:0] main_a7ddrphy_bitslip14_o = 8'd0;
reg [2:0] main_a7ddrphy_bitslip14_value = 3'd0;
reg [15:0] main_a7ddrphy_bitslip14_r = 16'd0;
wire main_a7ddrphy_dq_o_nodelay15;
wire main_a7ddrphy_dq_i_nodelay15;
wire main_a7ddrphy_dq_i_delayed15;
wire main_a7ddrphy_dq_t15;
wire [7:0] main_a7ddrphy_dq_i_data15;
wire [7:0] main_a7ddrphy_bitslip15_i;
reg [7:0] main_a7ddrphy_bitslip15_o = 8'd0;
reg [2:0] main_a7ddrphy_bitslip15_value = 3'd0;
reg [15:0] main_a7ddrphy_bitslip15_r = 16'd0;
reg main_a7ddrphy_n_rddata_en0 = 1'd0;
reg main_a7ddrphy_n_rddata_en1 = 1'd0;
reg main_a7ddrphy_n_rddata_en2 = 1'd0;
reg main_a7ddrphy_n_rddata_en3 = 1'd0;
reg main_a7ddrphy_n_rddata_en4 = 1'd0;
reg main_a7ddrphy_n_rddata_en5 = 1'd0;
reg main_a7ddrphy_n_rddata_en6 = 1'd0;
reg main_a7ddrphy_n_rddata_en7 = 1'd0;
wire main_a7ddrphy_oe;
reg [3:0] main_a7ddrphy_last_wrdata_en = 4'd0;
wire [13:0] main_sdram_inti_p0_address;
wire [2:0] main_sdram_inti_p0_bank;
reg main_sdram_inti_p0_cas_n = 1'd1;
reg main_sdram_inti_p0_cs_n = 1'd1;
reg main_sdram_inti_p0_ras_n = 1'd1;
reg main_sdram_inti_p0_we_n = 1'd1;
wire main_sdram_inti_p0_cke;
wire main_sdram_inti_p0_odt;
wire main_sdram_inti_p0_reset_n;
reg main_sdram_inti_p0_act_n = 1'd1;
wire [31:0] main_sdram_inti_p0_wrdata;
wire main_sdram_inti_p0_wrdata_en;
wire [3:0] main_sdram_inti_p0_wrdata_mask;
wire main_sdram_inti_p0_rddata_en;
reg [31:0] main_sdram_inti_p0_rddata = 32'd0;
reg main_sdram_inti_p0_rddata_valid = 1'd0;
wire [13:0] main_sdram_inti_p1_address;
wire [2:0] main_sdram_inti_p1_bank;
reg main_sdram_inti_p1_cas_n = 1'd1;
reg main_sdram_inti_p1_cs_n = 1'd1;
reg main_sdram_inti_p1_ras_n = 1'd1;
reg main_sdram_inti_p1_we_n = 1'd1;
wire main_sdram_inti_p1_cke;
wire main_sdram_inti_p1_odt;
wire main_sdram_inti_p1_reset_n;
reg main_sdram_inti_p1_act_n = 1'd1;
wire [31:0] main_sdram_inti_p1_wrdata;
wire main_sdram_inti_p1_wrdata_en;
wire [3:0] main_sdram_inti_p1_wrdata_mask;
wire main_sdram_inti_p1_rddata_en;
reg [31:0] main_sdram_inti_p1_rddata = 32'd0;
reg main_sdram_inti_p1_rddata_valid = 1'd0;
wire [13:0] main_sdram_inti_p2_address;
wire [2:0] main_sdram_inti_p2_bank;
reg main_sdram_inti_p2_cas_n = 1'd1;
reg main_sdram_inti_p2_cs_n = 1'd1;
reg main_sdram_inti_p2_ras_n = 1'd1;
reg main_sdram_inti_p2_we_n = 1'd1;
wire main_sdram_inti_p2_cke;
wire main_sdram_inti_p2_odt;
wire main_sdram_inti_p2_reset_n;
reg main_sdram_inti_p2_act_n = 1'd1;
wire [31:0] main_sdram_inti_p2_wrdata;
wire main_sdram_inti_p2_wrdata_en;
wire [3:0] main_sdram_inti_p2_wrdata_mask;
wire main_sdram_inti_p2_rddata_en;
reg [31:0] main_sdram_inti_p2_rddata = 32'd0;
reg main_sdram_inti_p2_rddata_valid = 1'd0;
wire [13:0] main_sdram_inti_p3_address;
wire [2:0] main_sdram_inti_p3_bank;
reg main_sdram_inti_p3_cas_n = 1'd1;
reg main_sdram_inti_p3_cs_n = 1'd1;
reg main_sdram_inti_p3_ras_n = 1'd1;
reg main_sdram_inti_p3_we_n = 1'd1;
wire main_sdram_inti_p3_cke;
wire main_sdram_inti_p3_odt;
wire main_sdram_inti_p3_reset_n;
reg main_sdram_inti_p3_act_n = 1'd1;
wire [31:0] main_sdram_inti_p3_wrdata;
wire main_sdram_inti_p3_wrdata_en;
wire [3:0] main_sdram_inti_p3_wrdata_mask;
wire main_sdram_inti_p3_rddata_en;
reg [31:0] main_sdram_inti_p3_rddata = 32'd0;
reg main_sdram_inti_p3_rddata_valid = 1'd0;
wire [13:0] main_sdram_slave_p0_address;
wire [2:0] main_sdram_slave_p0_bank;
wire main_sdram_slave_p0_cas_n;
wire main_sdram_slave_p0_cs_n;
wire main_sdram_slave_p0_ras_n;
wire main_sdram_slave_p0_we_n;
wire main_sdram_slave_p0_cke;
wire main_sdram_slave_p0_odt;
wire main_sdram_slave_p0_reset_n;
wire main_sdram_slave_p0_act_n;
wire [31:0] main_sdram_slave_p0_wrdata;
wire main_sdram_slave_p0_wrdata_en;
wire [3:0] main_sdram_slave_p0_wrdata_mask;
wire main_sdram_slave_p0_rddata_en;
reg [31:0] main_sdram_slave_p0_rddata = 32'd0;
reg main_sdram_slave_p0_rddata_valid = 1'd0;
wire [13:0] main_sdram_slave_p1_address;
wire [2:0] main_sdram_slave_p1_bank;
wire main_sdram_slave_p1_cas_n;
wire main_sdram_slave_p1_cs_n;
wire main_sdram_slave_p1_ras_n;
wire main_sdram_slave_p1_we_n;
wire main_sdram_slave_p1_cke;
wire main_sdram_slave_p1_odt;
wire main_sdram_slave_p1_reset_n;
wire main_sdram_slave_p1_act_n;
wire [31:0] main_sdram_slave_p1_wrdata;
wire main_sdram_slave_p1_wrdata_en;
wire [3:0] main_sdram_slave_p1_wrdata_mask;
wire main_sdram_slave_p1_rddata_en;
reg [31:0] main_sdram_slave_p1_rddata = 32'd0;
reg main_sdram_slave_p1_rddata_valid = 1'd0;
wire [13:0] main_sdram_slave_p2_address;
wire [2:0] main_sdram_slave_p2_bank;
wire main_sdram_slave_p2_cas_n;
wire main_sdram_slave_p2_cs_n;
wire main_sdram_slave_p2_ras_n;
wire main_sdram_slave_p2_we_n;
wire main_sdram_slave_p2_cke;
wire main_sdram_slave_p2_odt;
wire main_sdram_slave_p2_reset_n;
wire main_sdram_slave_p2_act_n;
wire [31:0] main_sdram_slave_p2_wrdata;
wire main_sdram_slave_p2_wrdata_en;
wire [3:0] main_sdram_slave_p2_wrdata_mask;
wire main_sdram_slave_p2_rddata_en;
reg [31:0] main_sdram_slave_p2_rddata = 32'd0;
reg main_sdram_slave_p2_rddata_valid = 1'd0;
wire [13:0] main_sdram_slave_p3_address;
wire [2:0] main_sdram_slave_p3_bank;
wire main_sdram_slave_p3_cas_n;
wire main_sdram_slave_p3_cs_n;
wire main_sdram_slave_p3_ras_n;
wire main_sdram_slave_p3_we_n;
wire main_sdram_slave_p3_cke;
wire main_sdram_slave_p3_odt;
wire main_sdram_slave_p3_reset_n;
wire main_sdram_slave_p3_act_n;
wire [31:0] main_sdram_slave_p3_wrdata;
wire main_sdram_slave_p3_wrdata_en;
wire [3:0] main_sdram_slave_p3_wrdata_mask;
wire main_sdram_slave_p3_rddata_en;
reg [31:0] main_sdram_slave_p3_rddata = 32'd0;
reg main_sdram_slave_p3_rddata_valid = 1'd0;
reg [13:0] main_sdram_master_p0_address = 14'd0;
reg [2:0] main_sdram_master_p0_bank = 3'd0;
reg main_sdram_master_p0_cas_n = 1'd1;
reg main_sdram_master_p0_cs_n = 1'd1;
reg main_sdram_master_p0_ras_n = 1'd1;
reg main_sdram_master_p0_we_n = 1'd1;
reg main_sdram_master_p0_cke = 1'd0;
reg main_sdram_master_p0_odt = 1'd0;
reg main_sdram_master_p0_reset_n = 1'd0;
reg main_sdram_master_p0_act_n = 1'd1;
reg [31:0] main_sdram_master_p0_wrdata = 32'd0;
reg main_sdram_master_p0_wrdata_en = 1'd0;
reg [3:0] main_sdram_master_p0_wrdata_mask = 4'd0;
reg main_sdram_master_p0_rddata_en = 1'd0;
wire [31:0] main_sdram_master_p0_rddata;
wire main_sdram_master_p0_rddata_valid;
reg [13:0] main_sdram_master_p1_address = 14'd0;
reg [2:0] main_sdram_master_p1_bank = 3'd0;
reg main_sdram_master_p1_cas_n = 1'd1;
reg main_sdram_master_p1_cs_n = 1'd1;
reg main_sdram_master_p1_ras_n = 1'd1;
reg main_sdram_master_p1_we_n = 1'd1;
reg main_sdram_master_p1_cke = 1'd0;
reg main_sdram_master_p1_odt = 1'd0;
reg main_sdram_master_p1_reset_n = 1'd0;
reg main_sdram_master_p1_act_n = 1'd1;
reg [31:0] main_sdram_master_p1_wrdata = 32'd0;
reg main_sdram_master_p1_wrdata_en = 1'd0;
reg [3:0] main_sdram_master_p1_wrdata_mask = 4'd0;
reg main_sdram_master_p1_rddata_en = 1'd0;
wire [31:0] main_sdram_master_p1_rddata;
wire main_sdram_master_p1_rddata_valid;
reg [13:0] main_sdram_master_p2_address = 14'd0;
reg [2:0] main_sdram_master_p2_bank = 3'd0;
reg main_sdram_master_p2_cas_n = 1'd1;
reg main_sdram_master_p2_cs_n = 1'd1;
reg main_sdram_master_p2_ras_n = 1'd1;
reg main_sdram_master_p2_we_n = 1'd1;
reg main_sdram_master_p2_cke = 1'd0;
reg main_sdram_master_p2_odt = 1'd0;
reg main_sdram_master_p2_reset_n = 1'd0;
reg main_sdram_master_p2_act_n = 1'd1;
reg [31:0] main_sdram_master_p2_wrdata = 32'd0;
reg main_sdram_master_p2_wrdata_en = 1'd0;
reg [3:0] main_sdram_master_p2_wrdata_mask = 4'd0;
reg main_sdram_master_p2_rddata_en = 1'd0;
wire [31:0] main_sdram_master_p2_rddata;
wire main_sdram_master_p2_rddata_valid;
reg [13:0] main_sdram_master_p3_address = 14'd0;
reg [2:0] main_sdram_master_p3_bank = 3'd0;
reg main_sdram_master_p3_cas_n = 1'd1;
reg main_sdram_master_p3_cs_n = 1'd1;
reg main_sdram_master_p3_ras_n = 1'd1;
reg main_sdram_master_p3_we_n = 1'd1;
reg main_sdram_master_p3_cke = 1'd0;
reg main_sdram_master_p3_odt = 1'd0;
reg main_sdram_master_p3_reset_n = 1'd0;
reg main_sdram_master_p3_act_n = 1'd1;
reg [31:0] main_sdram_master_p3_wrdata = 32'd0;
reg main_sdram_master_p3_wrdata_en = 1'd0;
reg [3:0] main_sdram_master_p3_wrdata_mask = 4'd0;
reg main_sdram_master_p3_rddata_en = 1'd0;
wire [31:0] main_sdram_master_p3_rddata;
wire main_sdram_master_p3_rddata_valid;
reg [3:0] main_sdram_storage = 4'd0;
reg main_sdram_re = 1'd0;
reg [5:0] main_sdram_phaseinjector0_command_storage = 6'd0;
reg main_sdram_phaseinjector0_command_re = 1'd0;
wire main_sdram_phaseinjector0_command_issue_re;
wire main_sdram_phaseinjector0_command_issue_r;
wire main_sdram_phaseinjector0_command_issue_we;
reg main_sdram_phaseinjector0_command_issue_w = 1'd0;
reg [13:0] main_sdram_phaseinjector0_address_storage = 14'd0;
reg main_sdram_phaseinjector0_address_re = 1'd0;
reg [2:0] main_sdram_phaseinjector0_baddress_storage = 3'd0;
reg main_sdram_phaseinjector0_baddress_re = 1'd0;
reg [31:0] main_sdram_phaseinjector0_wrdata_storage = 32'd0;
reg main_sdram_phaseinjector0_wrdata_re = 1'd0;
reg [31:0] main_sdram_phaseinjector0_status = 32'd0;
wire main_sdram_phaseinjector0_we;
reg [5:0] main_sdram_phaseinjector1_command_storage = 6'd0;
reg main_sdram_phaseinjector1_command_re = 1'd0;
wire main_sdram_phaseinjector1_command_issue_re;
wire main_sdram_phaseinjector1_command_issue_r;
wire main_sdram_phaseinjector1_command_issue_we;
reg main_sdram_phaseinjector1_command_issue_w = 1'd0;
reg [13:0] main_sdram_phaseinjector1_address_storage = 14'd0;
reg main_sdram_phaseinjector1_address_re = 1'd0;
reg [2:0] main_sdram_phaseinjector1_baddress_storage = 3'd0;
reg main_sdram_phaseinjector1_baddress_re = 1'd0;
reg [31:0] main_sdram_phaseinjector1_wrdata_storage = 32'd0;
reg main_sdram_phaseinjector1_wrdata_re = 1'd0;
reg [31:0] main_sdram_phaseinjector1_status = 32'd0;
wire main_sdram_phaseinjector1_we;
reg [5:0] main_sdram_phaseinjector2_command_storage = 6'd0;
reg main_sdram_phaseinjector2_command_re = 1'd0;
wire main_sdram_phaseinjector2_command_issue_re;
wire main_sdram_phaseinjector2_command_issue_r;
wire main_sdram_phaseinjector2_command_issue_we;
reg main_sdram_phaseinjector2_command_issue_w = 1'd0;
reg [13:0] main_sdram_phaseinjector2_address_storage = 14'd0;
reg main_sdram_phaseinjector2_address_re = 1'd0;
reg [2:0] main_sdram_phaseinjector2_baddress_storage = 3'd0;
reg main_sdram_phaseinjector2_baddress_re = 1'd0;
reg [31:0] main_sdram_phaseinjector2_wrdata_storage = 32'd0;
reg main_sdram_phaseinjector2_wrdata_re = 1'd0;
reg [31:0] main_sdram_phaseinjector2_status = 32'd0;
wire main_sdram_phaseinjector2_we;
reg [5:0] main_sdram_phaseinjector3_command_storage = 6'd0;
reg main_sdram_phaseinjector3_command_re = 1'd0;
wire main_sdram_phaseinjector3_command_issue_re;
wire main_sdram_phaseinjector3_command_issue_r;
wire main_sdram_phaseinjector3_command_issue_we;
reg main_sdram_phaseinjector3_command_issue_w = 1'd0;
reg [13:0] main_sdram_phaseinjector3_address_storage = 14'd0;
reg main_sdram_phaseinjector3_address_re = 1'd0;
reg [2:0] main_sdram_phaseinjector3_baddress_storage = 3'd0;
reg main_sdram_phaseinjector3_baddress_re = 1'd0;
reg [31:0] main_sdram_phaseinjector3_wrdata_storage = 32'd0;
reg main_sdram_phaseinjector3_wrdata_re = 1'd0;
reg [31:0] main_sdram_phaseinjector3_status = 32'd0;
wire main_sdram_phaseinjector3_we;
wire main_sdram_interface_bank0_valid;
wire main_sdram_interface_bank0_ready;
wire main_sdram_interface_bank0_we;
wire [20:0] main_sdram_interface_bank0_addr;
wire main_sdram_interface_bank0_lock;
wire main_sdram_interface_bank0_wdata_ready;
wire main_sdram_interface_bank0_rdata_valid;
wire main_sdram_interface_bank1_valid;
wire main_sdram_interface_bank1_ready;
wire main_sdram_interface_bank1_we;
wire [20:0] main_sdram_interface_bank1_addr;
wire main_sdram_interface_bank1_lock;
wire main_sdram_interface_bank1_wdata_ready;
wire main_sdram_interface_bank1_rdata_valid;
wire main_sdram_interface_bank2_valid;
wire main_sdram_interface_bank2_ready;
wire main_sdram_interface_bank2_we;
wire [20:0] main_sdram_interface_bank2_addr;
wire main_sdram_interface_bank2_lock;
wire main_sdram_interface_bank2_wdata_ready;
wire main_sdram_interface_bank2_rdata_valid;
wire main_sdram_interface_bank3_valid;
wire main_sdram_interface_bank3_ready;
wire main_sdram_interface_bank3_we;
wire [20:0] main_sdram_interface_bank3_addr;
wire main_sdram_interface_bank3_lock;
wire main_sdram_interface_bank3_wdata_ready;
wire main_sdram_interface_bank3_rdata_valid;
wire main_sdram_interface_bank4_valid;
wire main_sdram_interface_bank4_ready;
wire main_sdram_interface_bank4_we;
wire [20:0] main_sdram_interface_bank4_addr;
wire main_sdram_interface_bank4_lock;
wire main_sdram_interface_bank4_wdata_ready;
wire main_sdram_interface_bank4_rdata_valid;
wire main_sdram_interface_bank5_valid;
wire main_sdram_interface_bank5_ready;
wire main_sdram_interface_bank5_we;
wire [20:0] main_sdram_interface_bank5_addr;
wire main_sdram_interface_bank5_lock;
wire main_sdram_interface_bank5_wdata_ready;
wire main_sdram_interface_bank5_rdata_valid;
wire main_sdram_interface_bank6_valid;
wire main_sdram_interface_bank6_ready;
wire main_sdram_interface_bank6_we;
wire [20:0] main_sdram_interface_bank6_addr;
wire main_sdram_interface_bank6_lock;
wire main_sdram_interface_bank6_wdata_ready;
wire main_sdram_interface_bank6_rdata_valid;
wire main_sdram_interface_bank7_valid;
wire main_sdram_interface_bank7_ready;
wire main_sdram_interface_bank7_we;
wire [20:0] main_sdram_interface_bank7_addr;
wire main_sdram_interface_bank7_lock;
wire main_sdram_interface_bank7_wdata_ready;
wire main_sdram_interface_bank7_rdata_valid;
reg [127:0] main_sdram_interface_wdata = 128'd0;
reg [15:0] main_sdram_interface_wdata_we = 16'd0;
wire [127:0] main_sdram_interface_rdata;
reg [13:0] main_sdram_dfi_p0_address = 14'd0;
reg [2:0] main_sdram_dfi_p0_bank = 3'd0;
reg main_sdram_dfi_p0_cas_n = 1'd1;
reg main_sdram_dfi_p0_cs_n = 1'd1;
reg main_sdram_dfi_p0_ras_n = 1'd1;
reg main_sdram_dfi_p0_we_n = 1'd1;
wire main_sdram_dfi_p0_cke;
wire main_sdram_dfi_p0_odt;
wire main_sdram_dfi_p0_reset_n;
reg main_sdram_dfi_p0_act_n = 1'd1;
wire [31:0] main_sdram_dfi_p0_wrdata;
reg main_sdram_dfi_p0_wrdata_en = 1'd0;
wire [3:0] main_sdram_dfi_p0_wrdata_mask;
reg main_sdram_dfi_p0_rddata_en = 1'd0;
wire [31:0] main_sdram_dfi_p0_rddata;
wire main_sdram_dfi_p0_rddata_valid;
reg [13:0] main_sdram_dfi_p1_address = 14'd0;
reg [2:0] main_sdram_dfi_p1_bank = 3'd0;
reg main_sdram_dfi_p1_cas_n = 1'd1;
reg main_sdram_dfi_p1_cs_n = 1'd1;
reg main_sdram_dfi_p1_ras_n = 1'd1;
reg main_sdram_dfi_p1_we_n = 1'd1;
wire main_sdram_dfi_p1_cke;
wire main_sdram_dfi_p1_odt;
wire main_sdram_dfi_p1_reset_n;
reg main_sdram_dfi_p1_act_n = 1'd1;
wire [31:0] main_sdram_dfi_p1_wrdata;
reg main_sdram_dfi_p1_wrdata_en = 1'd0;
wire [3:0] main_sdram_dfi_p1_wrdata_mask;
reg main_sdram_dfi_p1_rddata_en = 1'd0;
wire [31:0] main_sdram_dfi_p1_rddata;
wire main_sdram_dfi_p1_rddata_valid;
reg [13:0] main_sdram_dfi_p2_address = 14'd0;
reg [2:0] main_sdram_dfi_p2_bank = 3'd0;
reg main_sdram_dfi_p2_cas_n = 1'd1;
reg main_sdram_dfi_p2_cs_n = 1'd1;
reg main_sdram_dfi_p2_ras_n = 1'd1;
reg main_sdram_dfi_p2_we_n = 1'd1;
wire main_sdram_dfi_p2_cke;
wire main_sdram_dfi_p2_odt;
wire main_sdram_dfi_p2_reset_n;
reg main_sdram_dfi_p2_act_n = 1'd1;
wire [31:0] main_sdram_dfi_p2_wrdata;
reg main_sdram_dfi_p2_wrdata_en = 1'd0;
wire [3:0] main_sdram_dfi_p2_wrdata_mask;
reg main_sdram_dfi_p2_rddata_en = 1'd0;
wire [31:0] main_sdram_dfi_p2_rddata;
wire main_sdram_dfi_p2_rddata_valid;
reg [13:0] main_sdram_dfi_p3_address = 14'd0;
reg [2:0] main_sdram_dfi_p3_bank = 3'd0;
reg main_sdram_dfi_p3_cas_n = 1'd1;
reg main_sdram_dfi_p3_cs_n = 1'd1;
reg main_sdram_dfi_p3_ras_n = 1'd1;
reg main_sdram_dfi_p3_we_n = 1'd1;
wire main_sdram_dfi_p3_cke;
wire main_sdram_dfi_p3_odt;
wire main_sdram_dfi_p3_reset_n;
reg main_sdram_dfi_p3_act_n = 1'd1;
wire [31:0] main_sdram_dfi_p3_wrdata;
reg main_sdram_dfi_p3_wrdata_en = 1'd0;
wire [3:0] main_sdram_dfi_p3_wrdata_mask;
reg main_sdram_dfi_p3_rddata_en = 1'd0;
wire [31:0] main_sdram_dfi_p3_rddata;
wire main_sdram_dfi_p3_rddata_valid;
reg main_sdram_cmd_valid = 1'd0;
reg main_sdram_cmd_ready = 1'd0;
reg main_sdram_cmd_last = 1'd0;
reg [13:0] main_sdram_cmd_payload_a = 14'd0;
reg [2:0] main_sdram_cmd_payload_ba = 3'd0;
reg main_sdram_cmd_payload_cas = 1'd0;
reg main_sdram_cmd_payload_ras = 1'd0;
reg main_sdram_cmd_payload_we = 1'd0;
reg main_sdram_cmd_payload_is_read = 1'd0;
reg main_sdram_cmd_payload_is_write = 1'd0;
wire main_sdram_wants_refresh;
wire main_sdram_wants_zqcs;
wire main_sdram_timer_wait;
wire main_sdram_timer_done0;
wire [8:0] main_sdram_timer_count0;
wire main_sdram_timer_done1;
reg [8:0] main_sdram_timer_count1 = 9'd390;
wire main_sdram_postponer_req_i;
reg main_sdram_postponer_req_o = 1'd0;
reg main_sdram_postponer_count = 1'd0;
reg main_sdram_sequencer_start0 = 1'd0;
wire main_sdram_sequencer_done0;
wire main_sdram_sequencer_start1;
reg main_sdram_sequencer_done1 = 1'd0;
reg [5:0] main_sdram_sequencer_counter = 6'd0;
reg main_sdram_sequencer_count = 1'd0;
wire main_sdram_zqcs_timer_wait;
wire main_sdram_zqcs_timer_done0;
wire [25:0] main_sdram_zqcs_timer_count0;
wire main_sdram_zqcs_timer_done1;
reg [25:0] main_sdram_zqcs_timer_count1 = 26'd49999999;
reg main_sdram_zqcs_executer_start = 1'd0;
reg main_sdram_zqcs_executer_done = 1'd0;
reg [4:0] main_sdram_zqcs_executer_counter = 5'd0;
wire main_sdram_bankmachine0_req_valid;
wire main_sdram_bankmachine0_req_ready;
wire main_sdram_bankmachine0_req_we;
wire [20:0] main_sdram_bankmachine0_req_addr;
wire main_sdram_bankmachine0_req_lock;
reg main_sdram_bankmachine0_req_wdata_ready = 1'd0;
reg main_sdram_bankmachine0_req_rdata_valid = 1'd0;
wire main_sdram_bankmachine0_refresh_req;
reg main_sdram_bankmachine0_refresh_gnt = 1'd0;
reg main_sdram_bankmachine0_cmd_valid = 1'd0;
reg main_sdram_bankmachine0_cmd_ready = 1'd0;
reg [13:0] main_sdram_bankmachine0_cmd_payload_a = 14'd0;
wire [2:0] main_sdram_bankmachine0_cmd_payload_ba;
reg main_sdram_bankmachine0_cmd_payload_cas = 1'd0;
reg main_sdram_bankmachine0_cmd_payload_ras = 1'd0;
reg main_sdram_bankmachine0_cmd_payload_we = 1'd0;
reg main_sdram_bankmachine0_cmd_payload_is_cmd = 1'd0;
reg main_sdram_bankmachine0_cmd_payload_is_read = 1'd0;
reg main_sdram_bankmachine0_cmd_payload_is_write = 1'd0;
reg main_sdram_bankmachine0_auto_precharge = 1'd0;
wire main_sdram_bankmachine0_cmd_buffer_lookahead_sink_valid;
wire main_sdram_bankmachine0_cmd_buffer_lookahead_sink_ready;
reg main_sdram_bankmachine0_cmd_buffer_lookahead_sink_first = 1'd0;
reg main_sdram_bankmachine0_cmd_buffer_lookahead_sink_last = 1'd0;
wire main_sdram_bankmachine0_cmd_buffer_lookahead_sink_payload_we;
wire [20:0] main_sdram_bankmachine0_cmd_buffer_lookahead_sink_payload_addr;
wire main_sdram_bankmachine0_cmd_buffer_lookahead_source_valid;
wire main_sdram_bankmachine0_cmd_buffer_lookahead_source_ready;
wire main_sdram_bankmachine0_cmd_buffer_lookahead_source_first;
wire main_sdram_bankmachine0_cmd_buffer_lookahead_source_last;
wire main_sdram_bankmachine0_cmd_buffer_lookahead_source_payload_we;
wire [20:0] main_sdram_bankmachine0_cmd_buffer_lookahead_source_payload_addr;
wire main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_we;
wire main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable;
wire main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_re;
wire main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable;
wire [23:0] main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_din;
wire [23:0] main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout;
reg [3:0] main_sdram_bankmachine0_cmd_buffer_lookahead_level = 4'd0;
reg main_sdram_bankmachine0_cmd_buffer_lookahead_replace = 1'd0;
reg [2:0] main_sdram_bankmachine0_cmd_buffer_lookahead_produce = 3'd0;
reg [2:0] main_sdram_bankmachine0_cmd_buffer_lookahead_consume = 3'd0;
reg [2:0] main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr = 3'd0;
wire [23:0] main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_dat_r;
wire main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_we;
wire [23:0] main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_dat_w;
wire main_sdram_bankmachine0_cmd_buffer_lookahead_do_read;
wire [2:0] main_sdram_bankmachine0_cmd_buffer_lookahead_rdport_adr;
wire [23:0] main_sdram_bankmachine0_cmd_buffer_lookahead_rdport_dat_r;
wire main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_we;
wire [20:0] main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_addr;
wire main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_first;
wire main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_last;
wire main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we;
wire [20:0] main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr;
wire main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_first;
wire main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_last;
wire main_sdram_bankmachine0_cmd_buffer_sink_valid;
wire main_sdram_bankmachine0_cmd_buffer_sink_ready;
wire main_sdram_bankmachine0_cmd_buffer_sink_first;
wire main_sdram_bankmachine0_cmd_buffer_sink_last;
wire main_sdram_bankmachine0_cmd_buffer_sink_payload_we;
wire [20:0] main_sdram_bankmachine0_cmd_buffer_sink_payload_addr;
wire main_sdram_bankmachine0_cmd_buffer_source_valid;
wire main_sdram_bankmachine0_cmd_buffer_source_ready;
wire main_sdram_bankmachine0_cmd_buffer_source_first;
wire main_sdram_bankmachine0_cmd_buffer_source_last;
reg main_sdram_bankmachine0_cmd_buffer_source_payload_we = 1'd0;
reg [20:0] main_sdram_bankmachine0_cmd_buffer_source_payload_addr = 21'd0;
wire main_sdram_bankmachine0_cmd_buffer_pipe_ce;
wire main_sdram_bankmachine0_cmd_buffer_busy;
reg main_sdram_bankmachine0_cmd_buffer_valid_n = 1'd0;
reg main_sdram_bankmachine0_cmd_buffer_first_n = 1'd0;
reg main_sdram_bankmachine0_cmd_buffer_last_n = 1'd0;
reg [13:0] main_sdram_bankmachine0_row = 14'd0;
reg main_sdram_bankmachine0_row_opened = 1'd0;
wire main_sdram_bankmachine0_row_hit;
reg main_sdram_bankmachine0_row_open = 1'd0;
reg main_sdram_bankmachine0_row_close = 1'd0;
reg main_sdram_bankmachine0_row_col_n_addr_sel = 1'd0;
wire main_sdram_bankmachine0_twtpcon_valid;
(* dont_touch = "true" *) reg main_sdram_bankmachine0_twtpcon_ready = 1'd1;
reg [2:0] main_sdram_bankmachine0_twtpcon_count = 3'd0;
wire main_sdram_bankmachine0_trccon_valid;
(* dont_touch = "true" *) reg main_sdram_bankmachine0_trccon_ready = 1'd1;
reg [1:0] main_sdram_bankmachine0_trccon_count = 2'd0;
wire main_sdram_bankmachine0_trascon_valid;
(* dont_touch = "true" *) reg main_sdram_bankmachine0_trascon_ready = 1'd1;
reg [1:0] main_sdram_bankmachine0_trascon_count = 2'd0;
wire main_sdram_bankmachine1_req_valid;
wire main_sdram_bankmachine1_req_ready;
wire main_sdram_bankmachine1_req_we;
wire [20:0] main_sdram_bankmachine1_req_addr;
wire main_sdram_bankmachine1_req_lock;
reg main_sdram_bankmachine1_req_wdata_ready = 1'd0;
reg main_sdram_bankmachine1_req_rdata_valid = 1'd0;
wire main_sdram_bankmachine1_refresh_req;
reg main_sdram_bankmachine1_refresh_gnt = 1'd0;
reg main_sdram_bankmachine1_cmd_valid = 1'd0;
reg main_sdram_bankmachine1_cmd_ready = 1'd0;
reg [13:0] main_sdram_bankmachine1_cmd_payload_a = 14'd0;
wire [2:0] main_sdram_bankmachine1_cmd_payload_ba;
reg main_sdram_bankmachine1_cmd_payload_cas = 1'd0;
reg main_sdram_bankmachine1_cmd_payload_ras = 1'd0;
reg main_sdram_bankmachine1_cmd_payload_we = 1'd0;
reg main_sdram_bankmachine1_cmd_payload_is_cmd = 1'd0;
reg main_sdram_bankmachine1_cmd_payload_is_read = 1'd0;
reg main_sdram_bankmachine1_cmd_payload_is_write = 1'd0;
reg main_sdram_bankmachine1_auto_precharge = 1'd0;
wire main_sdram_bankmachine1_cmd_buffer_lookahead_sink_valid;
wire main_sdram_bankmachine1_cmd_buffer_lookahead_sink_ready;
reg main_sdram_bankmachine1_cmd_buffer_lookahead_sink_first = 1'd0;
reg main_sdram_bankmachine1_cmd_buffer_lookahead_sink_last = 1'd0;
wire main_sdram_bankmachine1_cmd_buffer_lookahead_sink_payload_we;
wire [20:0] main_sdram_bankmachine1_cmd_buffer_lookahead_sink_payload_addr;
wire main_sdram_bankmachine1_cmd_buffer_lookahead_source_valid;
wire main_sdram_bankmachine1_cmd_buffer_lookahead_source_ready;
wire main_sdram_bankmachine1_cmd_buffer_lookahead_source_first;
wire main_sdram_bankmachine1_cmd_buffer_lookahead_source_last;
wire main_sdram_bankmachine1_cmd_buffer_lookahead_source_payload_we;
wire [20:0] main_sdram_bankmachine1_cmd_buffer_lookahead_source_payload_addr;
wire main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_we;
wire main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable;
wire main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_re;
wire main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable;
wire [23:0] main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_din;
wire [23:0] main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout;
reg [3:0] main_sdram_bankmachine1_cmd_buffer_lookahead_level = 4'd0;
reg main_sdram_bankmachine1_cmd_buffer_lookahead_replace = 1'd0;
reg [2:0] main_sdram_bankmachine1_cmd_buffer_lookahead_produce = 3'd0;
reg [2:0] main_sdram_bankmachine1_cmd_buffer_lookahead_consume = 3'd0;
reg [2:0] main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr = 3'd0;
wire [23:0] main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_dat_r;
wire main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_we;
wire [23:0] main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_dat_w;
wire main_sdram_bankmachine1_cmd_buffer_lookahead_do_read;
wire [2:0] main_sdram_bankmachine1_cmd_buffer_lookahead_rdport_adr;
wire [23:0] main_sdram_bankmachine1_cmd_buffer_lookahead_rdport_dat_r;
wire main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_we;
wire [20:0] main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_addr;
wire main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_first;
wire main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_last;
wire main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we;
wire [20:0] main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr;
wire main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_first;
wire main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_last;
wire main_sdram_bankmachine1_cmd_buffer_sink_valid;
wire main_sdram_bankmachine1_cmd_buffer_sink_ready;
wire main_sdram_bankmachine1_cmd_buffer_sink_first;
wire main_sdram_bankmachine1_cmd_buffer_sink_last;
wire main_sdram_bankmachine1_cmd_buffer_sink_payload_we;
wire [20:0] main_sdram_bankmachine1_cmd_buffer_sink_payload_addr;
wire main_sdram_bankmachine1_cmd_buffer_source_valid;
wire main_sdram_bankmachine1_cmd_buffer_source_ready;
wire main_sdram_bankmachine1_cmd_buffer_source_first;
wire main_sdram_bankmachine1_cmd_buffer_source_last;
reg main_sdram_bankmachine1_cmd_buffer_source_payload_we = 1'd0;
reg [20:0] main_sdram_bankmachine1_cmd_buffer_source_payload_addr = 21'd0;
wire main_sdram_bankmachine1_cmd_buffer_pipe_ce;
wire main_sdram_bankmachine1_cmd_buffer_busy;
reg main_sdram_bankmachine1_cmd_buffer_valid_n = 1'd0;
reg main_sdram_bankmachine1_cmd_buffer_first_n = 1'd0;
reg main_sdram_bankmachine1_cmd_buffer_last_n = 1'd0;
reg [13:0] main_sdram_bankmachine1_row = 14'd0;
reg main_sdram_bankmachine1_row_opened = 1'd0;
wire main_sdram_bankmachine1_row_hit;
reg main_sdram_bankmachine1_row_open = 1'd0;
reg main_sdram_bankmachine1_row_close = 1'd0;
reg main_sdram_bankmachine1_row_col_n_addr_sel = 1'd0;
wire main_sdram_bankmachine1_twtpcon_valid;
(* dont_touch = "true" *) reg main_sdram_bankmachine1_twtpcon_ready = 1'd1;
reg [2:0] main_sdram_bankmachine1_twtpcon_count = 3'd0;
wire main_sdram_bankmachine1_trccon_valid;
(* dont_touch = "true" *) reg main_sdram_bankmachine1_trccon_ready = 1'd1;
reg [1:0] main_sdram_bankmachine1_trccon_count = 2'd0;
wire main_sdram_bankmachine1_trascon_valid;
(* dont_touch = "true" *) reg main_sdram_bankmachine1_trascon_ready = 1'd1;
reg [1:0] main_sdram_bankmachine1_trascon_count = 2'd0;
wire main_sdram_bankmachine2_req_valid;
wire main_sdram_bankmachine2_req_ready;
wire main_sdram_bankmachine2_req_we;
wire [20:0] main_sdram_bankmachine2_req_addr;
wire main_sdram_bankmachine2_req_lock;
reg main_sdram_bankmachine2_req_wdata_ready = 1'd0;
reg main_sdram_bankmachine2_req_rdata_valid = 1'd0;
wire main_sdram_bankmachine2_refresh_req;
reg main_sdram_bankmachine2_refresh_gnt = 1'd0;
reg main_sdram_bankmachine2_cmd_valid = 1'd0;
reg main_sdram_bankmachine2_cmd_ready = 1'd0;
reg [13:0] main_sdram_bankmachine2_cmd_payload_a = 14'd0;
wire [2:0] main_sdram_bankmachine2_cmd_payload_ba;
reg main_sdram_bankmachine2_cmd_payload_cas = 1'd0;
reg main_sdram_bankmachine2_cmd_payload_ras = 1'd0;
reg main_sdram_bankmachine2_cmd_payload_we = 1'd0;
reg main_sdram_bankmachine2_cmd_payload_is_cmd = 1'd0;
reg main_sdram_bankmachine2_cmd_payload_is_read = 1'd0;
reg main_sdram_bankmachine2_cmd_payload_is_write = 1'd0;
reg main_sdram_bankmachine2_auto_precharge = 1'd0;
wire main_sdram_bankmachine2_cmd_buffer_lookahead_sink_valid;
wire main_sdram_bankmachine2_cmd_buffer_lookahead_sink_ready;
reg main_sdram_bankmachine2_cmd_buffer_lookahead_sink_first = 1'd0;
reg main_sdram_bankmachine2_cmd_buffer_lookahead_sink_last = 1'd0;
wire main_sdram_bankmachine2_cmd_buffer_lookahead_sink_payload_we;
wire [20:0] main_sdram_bankmachine2_cmd_buffer_lookahead_sink_payload_addr;
wire main_sdram_bankmachine2_cmd_buffer_lookahead_source_valid;
wire main_sdram_bankmachine2_cmd_buffer_lookahead_source_ready;
wire main_sdram_bankmachine2_cmd_buffer_lookahead_source_first;
wire main_sdram_bankmachine2_cmd_buffer_lookahead_source_last;
wire main_sdram_bankmachine2_cmd_buffer_lookahead_source_payload_we;
wire [20:0] main_sdram_bankmachine2_cmd_buffer_lookahead_source_payload_addr;
wire main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_we;
wire main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable;
wire main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_re;
wire main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable;
wire [23:0] main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_din;
wire [23:0] main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout;
reg [3:0] main_sdram_bankmachine2_cmd_buffer_lookahead_level = 4'd0;
reg main_sdram_bankmachine2_cmd_buffer_lookahead_replace = 1'd0;
reg [2:0] main_sdram_bankmachine2_cmd_buffer_lookahead_produce = 3'd0;
reg [2:0] main_sdram_bankmachine2_cmd_buffer_lookahead_consume = 3'd0;
reg [2:0] main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr = 3'd0;
wire [23:0] main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_dat_r;
wire main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_we;
wire [23:0] main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_dat_w;
wire main_sdram_bankmachine2_cmd_buffer_lookahead_do_read;
wire [2:0] main_sdram_bankmachine2_cmd_buffer_lookahead_rdport_adr;
wire [23:0] main_sdram_bankmachine2_cmd_buffer_lookahead_rdport_dat_r;
wire main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_we;
wire [20:0] main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_addr;
wire main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_first;
wire main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_last;
wire main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we;
wire [20:0] main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr;
wire main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_first;
wire main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_last;
wire main_sdram_bankmachine2_cmd_buffer_sink_valid;
wire main_sdram_bankmachine2_cmd_buffer_sink_ready;
wire main_sdram_bankmachine2_cmd_buffer_sink_first;
wire main_sdram_bankmachine2_cmd_buffer_sink_last;
wire main_sdram_bankmachine2_cmd_buffer_sink_payload_we;
wire [20:0] main_sdram_bankmachine2_cmd_buffer_sink_payload_addr;
wire main_sdram_bankmachine2_cmd_buffer_source_valid;
wire main_sdram_bankmachine2_cmd_buffer_source_ready;
wire main_sdram_bankmachine2_cmd_buffer_source_first;
wire main_sdram_bankmachine2_cmd_buffer_source_last;
reg main_sdram_bankmachine2_cmd_buffer_source_payload_we = 1'd0;
reg [20:0] main_sdram_bankmachine2_cmd_buffer_source_payload_addr = 21'd0;
wire main_sdram_bankmachine2_cmd_buffer_pipe_ce;
wire main_sdram_bankmachine2_cmd_buffer_busy;
reg main_sdram_bankmachine2_cmd_buffer_valid_n = 1'd0;
reg main_sdram_bankmachine2_cmd_buffer_first_n = 1'd0;
reg main_sdram_bankmachine2_cmd_buffer_last_n = 1'd0;
reg [13:0] main_sdram_bankmachine2_row = 14'd0;
reg main_sdram_bankmachine2_row_opened = 1'd0;
wire main_sdram_bankmachine2_row_hit;
reg main_sdram_bankmachine2_row_open = 1'd0;
reg main_sdram_bankmachine2_row_close = 1'd0;
reg main_sdram_bankmachine2_row_col_n_addr_sel = 1'd0;
wire main_sdram_bankmachine2_twtpcon_valid;
(* dont_touch = "true" *) reg main_sdram_bankmachine2_twtpcon_ready = 1'd1;
reg [2:0] main_sdram_bankmachine2_twtpcon_count = 3'd0;
wire main_sdram_bankmachine2_trccon_valid;
(* dont_touch = "true" *) reg main_sdram_bankmachine2_trccon_ready = 1'd1;
reg [1:0] main_sdram_bankmachine2_trccon_count = 2'd0;
wire main_sdram_bankmachine2_trascon_valid;
(* dont_touch = "true" *) reg main_sdram_bankmachine2_trascon_ready = 1'd1;
reg [1:0] main_sdram_bankmachine2_trascon_count = 2'd0;
wire main_sdram_bankmachine3_req_valid;
wire main_sdram_bankmachine3_req_ready;
wire main_sdram_bankmachine3_req_we;
wire [20:0] main_sdram_bankmachine3_req_addr;
wire main_sdram_bankmachine3_req_lock;
reg main_sdram_bankmachine3_req_wdata_ready = 1'd0;
reg main_sdram_bankmachine3_req_rdata_valid = 1'd0;
wire main_sdram_bankmachine3_refresh_req;
reg main_sdram_bankmachine3_refresh_gnt = 1'd0;
reg main_sdram_bankmachine3_cmd_valid = 1'd0;
reg main_sdram_bankmachine3_cmd_ready = 1'd0;
reg [13:0] main_sdram_bankmachine3_cmd_payload_a = 14'd0;
wire [2:0] main_sdram_bankmachine3_cmd_payload_ba;
reg main_sdram_bankmachine3_cmd_payload_cas = 1'd0;
reg main_sdram_bankmachine3_cmd_payload_ras = 1'd0;
reg main_sdram_bankmachine3_cmd_payload_we = 1'd0;
reg main_sdram_bankmachine3_cmd_payload_is_cmd = 1'd0;
reg main_sdram_bankmachine3_cmd_payload_is_read = 1'd0;
reg main_sdram_bankmachine3_cmd_payload_is_write = 1'd0;
reg main_sdram_bankmachine3_auto_precharge = 1'd0;
wire main_sdram_bankmachine3_cmd_buffer_lookahead_sink_valid;
wire main_sdram_bankmachine3_cmd_buffer_lookahead_sink_ready;
reg main_sdram_bankmachine3_cmd_buffer_lookahead_sink_first = 1'd0;
reg main_sdram_bankmachine3_cmd_buffer_lookahead_sink_last = 1'd0;
wire main_sdram_bankmachine3_cmd_buffer_lookahead_sink_payload_we;
wire [20:0] main_sdram_bankmachine3_cmd_buffer_lookahead_sink_payload_addr;
wire main_sdram_bankmachine3_cmd_buffer_lookahead_source_valid;
wire main_sdram_bankmachine3_cmd_buffer_lookahead_source_ready;
wire main_sdram_bankmachine3_cmd_buffer_lookahead_source_first;
wire main_sdram_bankmachine3_cmd_buffer_lookahead_source_last;
wire main_sdram_bankmachine3_cmd_buffer_lookahead_source_payload_we;
wire [20:0] main_sdram_bankmachine3_cmd_buffer_lookahead_source_payload_addr;
wire main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_we;
wire main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable;
wire main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_re;
wire main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable;
wire [23:0] main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_din;
wire [23:0] main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout;
reg [3:0] main_sdram_bankmachine3_cmd_buffer_lookahead_level = 4'd0;
reg main_sdram_bankmachine3_cmd_buffer_lookahead_replace = 1'd0;
reg [2:0] main_sdram_bankmachine3_cmd_buffer_lookahead_produce = 3'd0;
reg [2:0] main_sdram_bankmachine3_cmd_buffer_lookahead_consume = 3'd0;
reg [2:0] main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr = 3'd0;
wire [23:0] main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_dat_r;
wire main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_we;
wire [23:0] main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_dat_w;
wire main_sdram_bankmachine3_cmd_buffer_lookahead_do_read;
wire [2:0] main_sdram_bankmachine3_cmd_buffer_lookahead_rdport_adr;
wire [23:0] main_sdram_bankmachine3_cmd_buffer_lookahead_rdport_dat_r;
wire main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_we;
wire [20:0] main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_addr;
wire main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_first;
wire main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_last;
wire main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we;
wire [20:0] main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr;
wire main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_first;
wire main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_last;
wire main_sdram_bankmachine3_cmd_buffer_sink_valid;
wire main_sdram_bankmachine3_cmd_buffer_sink_ready;
wire main_sdram_bankmachine3_cmd_buffer_sink_first;
wire main_sdram_bankmachine3_cmd_buffer_sink_last;
wire main_sdram_bankmachine3_cmd_buffer_sink_payload_we;
wire [20:0] main_sdram_bankmachine3_cmd_buffer_sink_payload_addr;
wire main_sdram_bankmachine3_cmd_buffer_source_valid;
wire main_sdram_bankmachine3_cmd_buffer_source_ready;
wire main_sdram_bankmachine3_cmd_buffer_source_first;
wire main_sdram_bankmachine3_cmd_buffer_source_last;
reg main_sdram_bankmachine3_cmd_buffer_source_payload_we = 1'd0;
reg [20:0] main_sdram_bankmachine3_cmd_buffer_source_payload_addr = 21'd0;
wire main_sdram_bankmachine3_cmd_buffer_pipe_ce;
wire main_sdram_bankmachine3_cmd_buffer_busy;
reg main_sdram_bankmachine3_cmd_buffer_valid_n = 1'd0;
reg main_sdram_bankmachine3_cmd_buffer_first_n = 1'd0;
reg main_sdram_bankmachine3_cmd_buffer_last_n = 1'd0;
reg [13:0] main_sdram_bankmachine3_row = 14'd0;
reg main_sdram_bankmachine3_row_opened = 1'd0;
wire main_sdram_bankmachine3_row_hit;
reg main_sdram_bankmachine3_row_open = 1'd0;
reg main_sdram_bankmachine3_row_close = 1'd0;
reg main_sdram_bankmachine3_row_col_n_addr_sel = 1'd0;
wire main_sdram_bankmachine3_twtpcon_valid;
(* dont_touch = "true" *) reg main_sdram_bankmachine3_twtpcon_ready = 1'd1;
reg [2:0] main_sdram_bankmachine3_twtpcon_count = 3'd0;
wire main_sdram_bankmachine3_trccon_valid;
(* dont_touch = "true" *) reg main_sdram_bankmachine3_trccon_ready = 1'd1;
reg [1:0] main_sdram_bankmachine3_trccon_count = 2'd0;
wire main_sdram_bankmachine3_trascon_valid;
(* dont_touch = "true" *) reg main_sdram_bankmachine3_trascon_ready = 1'd1;
reg [1:0] main_sdram_bankmachine3_trascon_count = 2'd0;
wire main_sdram_bankmachine4_req_valid;
wire main_sdram_bankmachine4_req_ready;
wire main_sdram_bankmachine4_req_we;
wire [20:0] main_sdram_bankmachine4_req_addr;
wire main_sdram_bankmachine4_req_lock;
reg main_sdram_bankmachine4_req_wdata_ready = 1'd0;
reg main_sdram_bankmachine4_req_rdata_valid = 1'd0;
wire main_sdram_bankmachine4_refresh_req;
reg main_sdram_bankmachine4_refresh_gnt = 1'd0;
reg main_sdram_bankmachine4_cmd_valid = 1'd0;
reg main_sdram_bankmachine4_cmd_ready = 1'd0;
reg [13:0] main_sdram_bankmachine4_cmd_payload_a = 14'd0;
wire [2:0] main_sdram_bankmachine4_cmd_payload_ba;
reg main_sdram_bankmachine4_cmd_payload_cas = 1'd0;
reg main_sdram_bankmachine4_cmd_payload_ras = 1'd0;
reg main_sdram_bankmachine4_cmd_payload_we = 1'd0;
reg main_sdram_bankmachine4_cmd_payload_is_cmd = 1'd0;
reg main_sdram_bankmachine4_cmd_payload_is_read = 1'd0;
reg main_sdram_bankmachine4_cmd_payload_is_write = 1'd0;
reg main_sdram_bankmachine4_auto_precharge = 1'd0;
wire main_sdram_bankmachine4_cmd_buffer_lookahead_sink_valid;
wire main_sdram_bankmachine4_cmd_buffer_lookahead_sink_ready;
reg main_sdram_bankmachine4_cmd_buffer_lookahead_sink_first = 1'd0;
reg main_sdram_bankmachine4_cmd_buffer_lookahead_sink_last = 1'd0;
wire main_sdram_bankmachine4_cmd_buffer_lookahead_sink_payload_we;
wire [20:0] main_sdram_bankmachine4_cmd_buffer_lookahead_sink_payload_addr;
wire main_sdram_bankmachine4_cmd_buffer_lookahead_source_valid;
wire main_sdram_bankmachine4_cmd_buffer_lookahead_source_ready;
wire main_sdram_bankmachine4_cmd_buffer_lookahead_source_first;
wire main_sdram_bankmachine4_cmd_buffer_lookahead_source_last;
wire main_sdram_bankmachine4_cmd_buffer_lookahead_source_payload_we;
wire [20:0] main_sdram_bankmachine4_cmd_buffer_lookahead_source_payload_addr;
wire main_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_we;
wire main_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable;
wire main_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_re;
wire main_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_readable;
wire [23:0] main_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_din;
wire [23:0] main_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout;
reg [3:0] main_sdram_bankmachine4_cmd_buffer_lookahead_level = 4'd0;
reg main_sdram_bankmachine4_cmd_buffer_lookahead_replace = 1'd0;
reg [2:0] main_sdram_bankmachine4_cmd_buffer_lookahead_produce = 3'd0;
reg [2:0] main_sdram_bankmachine4_cmd_buffer_lookahead_consume = 3'd0;
reg [2:0] main_sdram_bankmachine4_cmd_buffer_lookahead_wrport_adr = 3'd0;
wire [23:0] main_sdram_bankmachine4_cmd_buffer_lookahead_wrport_dat_r;
wire main_sdram_bankmachine4_cmd_buffer_lookahead_wrport_we;
wire [23:0] main_sdram_bankmachine4_cmd_buffer_lookahead_wrport_dat_w;
wire main_sdram_bankmachine4_cmd_buffer_lookahead_do_read;
wire [2:0] main_sdram_bankmachine4_cmd_buffer_lookahead_rdport_adr;
wire [23:0] main_sdram_bankmachine4_cmd_buffer_lookahead_rdport_dat_r;
wire main_sdram_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_we;
wire [20:0] main_sdram_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_addr;
wire main_sdram_bankmachine4_cmd_buffer_lookahead_fifo_in_first;
wire main_sdram_bankmachine4_cmd_buffer_lookahead_fifo_in_last;
wire main_sdram_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we;
wire [20:0] main_sdram_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr;
wire main_sdram_bankmachine4_cmd_buffer_lookahead_fifo_out_first;
wire main_sdram_bankmachine4_cmd_buffer_lookahead_fifo_out_last;
wire main_sdram_bankmachine4_cmd_buffer_sink_valid;
wire main_sdram_bankmachine4_cmd_buffer_sink_ready;
wire main_sdram_bankmachine4_cmd_buffer_sink_first;
wire main_sdram_bankmachine4_cmd_buffer_sink_last;
wire main_sdram_bankmachine4_cmd_buffer_sink_payload_we;
wire [20:0] main_sdram_bankmachine4_cmd_buffer_sink_payload_addr;
wire main_sdram_bankmachine4_cmd_buffer_source_valid;
wire main_sdram_bankmachine4_cmd_buffer_source_ready;
wire main_sdram_bankmachine4_cmd_buffer_source_first;
wire main_sdram_bankmachine4_cmd_buffer_source_last;
reg main_sdram_bankmachine4_cmd_buffer_source_payload_we = 1'd0;
reg [20:0] main_sdram_bankmachine4_cmd_buffer_source_payload_addr = 21'd0;
wire main_sdram_bankmachine4_cmd_buffer_pipe_ce;
wire main_sdram_bankmachine4_cmd_buffer_busy;
reg main_sdram_bankmachine4_cmd_buffer_valid_n = 1'd0;
reg main_sdram_bankmachine4_cmd_buffer_first_n = 1'd0;
reg main_sdram_bankmachine4_cmd_buffer_last_n = 1'd0;
reg [13:0] main_sdram_bankmachine4_row = 14'd0;
reg main_sdram_bankmachine4_row_opened = 1'd0;
wire main_sdram_bankmachine4_row_hit;
reg main_sdram_bankmachine4_row_open = 1'd0;
reg main_sdram_bankmachine4_row_close = 1'd0;
reg main_sdram_bankmachine4_row_col_n_addr_sel = 1'd0;
wire main_sdram_bankmachine4_twtpcon_valid;
(* dont_touch = "true" *) reg main_sdram_bankmachine4_twtpcon_ready = 1'd1;
reg [2:0] main_sdram_bankmachine4_twtpcon_count = 3'd0;
wire main_sdram_bankmachine4_trccon_valid;
(* dont_touch = "true" *) reg main_sdram_bankmachine4_trccon_ready = 1'd1;
reg [1:0] main_sdram_bankmachine4_trccon_count = 2'd0;
wire main_sdram_bankmachine4_trascon_valid;
(* dont_touch = "true" *) reg main_sdram_bankmachine4_trascon_ready = 1'd1;
reg [1:0] main_sdram_bankmachine4_trascon_count = 2'd0;
wire main_sdram_bankmachine5_req_valid;
wire main_sdram_bankmachine5_req_ready;
wire main_sdram_bankmachine5_req_we;
wire [20:0] main_sdram_bankmachine5_req_addr;
wire main_sdram_bankmachine5_req_lock;
reg main_sdram_bankmachine5_req_wdata_ready = 1'd0;
reg main_sdram_bankmachine5_req_rdata_valid = 1'd0;
wire main_sdram_bankmachine5_refresh_req;
reg main_sdram_bankmachine5_refresh_gnt = 1'd0;
reg main_sdram_bankmachine5_cmd_valid = 1'd0;
reg main_sdram_bankmachine5_cmd_ready = 1'd0;
reg [13:0] main_sdram_bankmachine5_cmd_payload_a = 14'd0;
wire [2:0] main_sdram_bankmachine5_cmd_payload_ba;
reg main_sdram_bankmachine5_cmd_payload_cas = 1'd0;
reg main_sdram_bankmachine5_cmd_payload_ras = 1'd0;
reg main_sdram_bankmachine5_cmd_payload_we = 1'd0;
reg main_sdram_bankmachine5_cmd_payload_is_cmd = 1'd0;
reg main_sdram_bankmachine5_cmd_payload_is_read = 1'd0;
reg main_sdram_bankmachine5_cmd_payload_is_write = 1'd0;
reg main_sdram_bankmachine5_auto_precharge = 1'd0;
wire main_sdram_bankmachine5_cmd_buffer_lookahead_sink_valid;
wire main_sdram_bankmachine5_cmd_buffer_lookahead_sink_ready;
reg main_sdram_bankmachine5_cmd_buffer_lookahead_sink_first = 1'd0;
reg main_sdram_bankmachine5_cmd_buffer_lookahead_sink_last = 1'd0;
wire main_sdram_bankmachine5_cmd_buffer_lookahead_sink_payload_we;
wire [20:0] main_sdram_bankmachine5_cmd_buffer_lookahead_sink_payload_addr;
wire main_sdram_bankmachine5_cmd_buffer_lookahead_source_valid;
wire main_sdram_bankmachine5_cmd_buffer_lookahead_source_ready;
wire main_sdram_bankmachine5_cmd_buffer_lookahead_source_first;
wire main_sdram_bankmachine5_cmd_buffer_lookahead_source_last;
wire main_sdram_bankmachine5_cmd_buffer_lookahead_source_payload_we;
wire [20:0] main_sdram_bankmachine5_cmd_buffer_lookahead_source_payload_addr;
wire main_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_we;
wire main_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable;
wire main_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_re;
wire main_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_readable;
wire [23:0] main_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_din;
wire [23:0] main_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout;
reg [3:0] main_sdram_bankmachine5_cmd_buffer_lookahead_level = 4'd0;
reg main_sdram_bankmachine5_cmd_buffer_lookahead_replace = 1'd0;
reg [2:0] main_sdram_bankmachine5_cmd_buffer_lookahead_produce = 3'd0;
reg [2:0] main_sdram_bankmachine5_cmd_buffer_lookahead_consume = 3'd0;
reg [2:0] main_sdram_bankmachine5_cmd_buffer_lookahead_wrport_adr = 3'd0;
wire [23:0] main_sdram_bankmachine5_cmd_buffer_lookahead_wrport_dat_r;
wire main_sdram_bankmachine5_cmd_buffer_lookahead_wrport_we;
wire [23:0] main_sdram_bankmachine5_cmd_buffer_lookahead_wrport_dat_w;
wire main_sdram_bankmachine5_cmd_buffer_lookahead_do_read;
wire [2:0] main_sdram_bankmachine5_cmd_buffer_lookahead_rdport_adr;
wire [23:0] main_sdram_bankmachine5_cmd_buffer_lookahead_rdport_dat_r;
wire main_sdram_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_we;
wire [20:0] main_sdram_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_addr;
wire main_sdram_bankmachine5_cmd_buffer_lookahead_fifo_in_first;
wire main_sdram_bankmachine5_cmd_buffer_lookahead_fifo_in_last;
wire main_sdram_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we;
wire [20:0] main_sdram_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr;
wire main_sdram_bankmachine5_cmd_buffer_lookahead_fifo_out_first;
wire main_sdram_bankmachine5_cmd_buffer_lookahead_fifo_out_last;
wire main_sdram_bankmachine5_cmd_buffer_sink_valid;
wire main_sdram_bankmachine5_cmd_buffer_sink_ready;
wire main_sdram_bankmachine5_cmd_buffer_sink_first;
wire main_sdram_bankmachine5_cmd_buffer_sink_last;
wire main_sdram_bankmachine5_cmd_buffer_sink_payload_we;
wire [20:0] main_sdram_bankmachine5_cmd_buffer_sink_payload_addr;
wire main_sdram_bankmachine5_cmd_buffer_source_valid;
wire main_sdram_bankmachine5_cmd_buffer_source_ready;
wire main_sdram_bankmachine5_cmd_buffer_source_first;
wire main_sdram_bankmachine5_cmd_buffer_source_last;
reg main_sdram_bankmachine5_cmd_buffer_source_payload_we = 1'd0;
reg [20:0] main_sdram_bankmachine5_cmd_buffer_source_payload_addr = 21'd0;
wire main_sdram_bankmachine5_cmd_buffer_pipe_ce;
wire main_sdram_bankmachine5_cmd_buffer_busy;
reg main_sdram_bankmachine5_cmd_buffer_valid_n = 1'd0;
reg main_sdram_bankmachine5_cmd_buffer_first_n = 1'd0;
reg main_sdram_bankmachine5_cmd_buffer_last_n = 1'd0;
reg [13:0] main_sdram_bankmachine5_row = 14'd0;
reg main_sdram_bankmachine5_row_opened = 1'd0;
wire main_sdram_bankmachine5_row_hit;
reg main_sdram_bankmachine5_row_open = 1'd0;
reg main_sdram_bankmachine5_row_close = 1'd0;
reg main_sdram_bankmachine5_row_col_n_addr_sel = 1'd0;
wire main_sdram_bankmachine5_twtpcon_valid;
(* dont_touch = "true" *) reg main_sdram_bankmachine5_twtpcon_ready = 1'd1;
reg [2:0] main_sdram_bankmachine5_twtpcon_count = 3'd0;
wire main_sdram_bankmachine5_trccon_valid;
(* dont_touch = "true" *) reg main_sdram_bankmachine5_trccon_ready = 1'd1;
reg [1:0] main_sdram_bankmachine5_trccon_count = 2'd0;
wire main_sdram_bankmachine5_trascon_valid;
(* dont_touch = "true" *) reg main_sdram_bankmachine5_trascon_ready = 1'd1;
reg [1:0] main_sdram_bankmachine5_trascon_count = 2'd0;
wire main_sdram_bankmachine6_req_valid;
wire main_sdram_bankmachine6_req_ready;
wire main_sdram_bankmachine6_req_we;
wire [20:0] main_sdram_bankmachine6_req_addr;
wire main_sdram_bankmachine6_req_lock;
reg main_sdram_bankmachine6_req_wdata_ready = 1'd0;
reg main_sdram_bankmachine6_req_rdata_valid = 1'd0;
wire main_sdram_bankmachine6_refresh_req;
reg main_sdram_bankmachine6_refresh_gnt = 1'd0;
reg main_sdram_bankmachine6_cmd_valid = 1'd0;
reg main_sdram_bankmachine6_cmd_ready = 1'd0;
reg [13:0] main_sdram_bankmachine6_cmd_payload_a = 14'd0;
wire [2:0] main_sdram_bankmachine6_cmd_payload_ba;
reg main_sdram_bankmachine6_cmd_payload_cas = 1'd0;
reg main_sdram_bankmachine6_cmd_payload_ras = 1'd0;
reg main_sdram_bankmachine6_cmd_payload_we = 1'd0;
reg main_sdram_bankmachine6_cmd_payload_is_cmd = 1'd0;
reg main_sdram_bankmachine6_cmd_payload_is_read = 1'd0;
reg main_sdram_bankmachine6_cmd_payload_is_write = 1'd0;
reg main_sdram_bankmachine6_auto_precharge = 1'd0;
wire main_sdram_bankmachine6_cmd_buffer_lookahead_sink_valid;
wire main_sdram_bankmachine6_cmd_buffer_lookahead_sink_ready;
reg main_sdram_bankmachine6_cmd_buffer_lookahead_sink_first = 1'd0;
reg main_sdram_bankmachine6_cmd_buffer_lookahead_sink_last = 1'd0;
wire main_sdram_bankmachine6_cmd_buffer_lookahead_sink_payload_we;
wire [20:0] main_sdram_bankmachine6_cmd_buffer_lookahead_sink_payload_addr;
wire main_sdram_bankmachine6_cmd_buffer_lookahead_source_valid;
wire main_sdram_bankmachine6_cmd_buffer_lookahead_source_ready;
wire main_sdram_bankmachine6_cmd_buffer_lookahead_source_first;
wire main_sdram_bankmachine6_cmd_buffer_lookahead_source_last;
wire main_sdram_bankmachine6_cmd_buffer_lookahead_source_payload_we;
wire [20:0] main_sdram_bankmachine6_cmd_buffer_lookahead_source_payload_addr;
wire main_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_we;
wire main_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable;
wire main_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_re;
wire main_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_readable;
wire [23:0] main_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_din;
wire [23:0] main_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout;
reg [3:0] main_sdram_bankmachine6_cmd_buffer_lookahead_level = 4'd0;
reg main_sdram_bankmachine6_cmd_buffer_lookahead_replace = 1'd0;
reg [2:0] main_sdram_bankmachine6_cmd_buffer_lookahead_produce = 3'd0;
reg [2:0] main_sdram_bankmachine6_cmd_buffer_lookahead_consume = 3'd0;
reg [2:0] main_sdram_bankmachine6_cmd_buffer_lookahead_wrport_adr = 3'd0;
wire [23:0] main_sdram_bankmachine6_cmd_buffer_lookahead_wrport_dat_r;
wire main_sdram_bankmachine6_cmd_buffer_lookahead_wrport_we;
wire [23:0] main_sdram_bankmachine6_cmd_buffer_lookahead_wrport_dat_w;
wire main_sdram_bankmachine6_cmd_buffer_lookahead_do_read;
wire [2:0] main_sdram_bankmachine6_cmd_buffer_lookahead_rdport_adr;
wire [23:0] main_sdram_bankmachine6_cmd_buffer_lookahead_rdport_dat_r;
wire main_sdram_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_we;
wire [20:0] main_sdram_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_addr;
wire main_sdram_bankmachine6_cmd_buffer_lookahead_fifo_in_first;
wire main_sdram_bankmachine6_cmd_buffer_lookahead_fifo_in_last;
wire main_sdram_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we;
wire [20:0] main_sdram_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr;
wire main_sdram_bankmachine6_cmd_buffer_lookahead_fifo_out_first;
wire main_sdram_bankmachine6_cmd_buffer_lookahead_fifo_out_last;
wire main_sdram_bankmachine6_cmd_buffer_sink_valid;
wire main_sdram_bankmachine6_cmd_buffer_sink_ready;
wire main_sdram_bankmachine6_cmd_buffer_sink_first;
wire main_sdram_bankmachine6_cmd_buffer_sink_last;
wire main_sdram_bankmachine6_cmd_buffer_sink_payload_we;
wire [20:0] main_sdram_bankmachine6_cmd_buffer_sink_payload_addr;
wire main_sdram_bankmachine6_cmd_buffer_source_valid;
wire main_sdram_bankmachine6_cmd_buffer_source_ready;
wire main_sdram_bankmachine6_cmd_buffer_source_first;
wire main_sdram_bankmachine6_cmd_buffer_source_last;
reg main_sdram_bankmachine6_cmd_buffer_source_payload_we = 1'd0;
reg [20:0] main_sdram_bankmachine6_cmd_buffer_source_payload_addr = 21'd0;
wire main_sdram_bankmachine6_cmd_buffer_pipe_ce;
wire main_sdram_bankmachine6_cmd_buffer_busy;
reg main_sdram_bankmachine6_cmd_buffer_valid_n = 1'd0;
reg main_sdram_bankmachine6_cmd_buffer_first_n = 1'd0;
reg main_sdram_bankmachine6_cmd_buffer_last_n = 1'd0;
reg [13:0] main_sdram_bankmachine6_row = 14'd0;
reg main_sdram_bankmachine6_row_opened = 1'd0;
wire main_sdram_bankmachine6_row_hit;
reg main_sdram_bankmachine6_row_open = 1'd0;
reg main_sdram_bankmachine6_row_close = 1'd0;
reg main_sdram_bankmachine6_row_col_n_addr_sel = 1'd0;
wire main_sdram_bankmachine6_twtpcon_valid;
(* dont_touch = "true" *) reg main_sdram_bankmachine6_twtpcon_ready = 1'd1;
reg [2:0] main_sdram_bankmachine6_twtpcon_count = 3'd0;
wire main_sdram_bankmachine6_trccon_valid;
(* dont_touch = "true" *) reg main_sdram_bankmachine6_trccon_ready = 1'd1;
reg [1:0] main_sdram_bankmachine6_trccon_count = 2'd0;
wire main_sdram_bankmachine6_trascon_valid;
(* dont_touch = "true" *) reg main_sdram_bankmachine6_trascon_ready = 1'd1;
reg [1:0] main_sdram_bankmachine6_trascon_count = 2'd0;
wire main_sdram_bankmachine7_req_valid;
wire main_sdram_bankmachine7_req_ready;
wire main_sdram_bankmachine7_req_we;
wire [20:0] main_sdram_bankmachine7_req_addr;
wire main_sdram_bankmachine7_req_lock;
reg main_sdram_bankmachine7_req_wdata_ready = 1'd0;
reg main_sdram_bankmachine7_req_rdata_valid = 1'd0;
wire main_sdram_bankmachine7_refresh_req;
reg main_sdram_bankmachine7_refresh_gnt = 1'd0;
reg main_sdram_bankmachine7_cmd_valid = 1'd0;
reg main_sdram_bankmachine7_cmd_ready = 1'd0;
reg [13:0] main_sdram_bankmachine7_cmd_payload_a = 14'd0;
wire [2:0] main_sdram_bankmachine7_cmd_payload_ba;
reg main_sdram_bankmachine7_cmd_payload_cas = 1'd0;
reg main_sdram_bankmachine7_cmd_payload_ras = 1'd0;
reg main_sdram_bankmachine7_cmd_payload_we = 1'd0;
reg main_sdram_bankmachine7_cmd_payload_is_cmd = 1'd0;
reg main_sdram_bankmachine7_cmd_payload_is_read = 1'd0;
reg main_sdram_bankmachine7_cmd_payload_is_write = 1'd0;
reg main_sdram_bankmachine7_auto_precharge = 1'd0;
wire main_sdram_bankmachine7_cmd_buffer_lookahead_sink_valid;
wire main_sdram_bankmachine7_cmd_buffer_lookahead_sink_ready;
reg main_sdram_bankmachine7_cmd_buffer_lookahead_sink_first = 1'd0;
reg main_sdram_bankmachine7_cmd_buffer_lookahead_sink_last = 1'd0;
wire main_sdram_bankmachine7_cmd_buffer_lookahead_sink_payload_we;
wire [20:0] main_sdram_bankmachine7_cmd_buffer_lookahead_sink_payload_addr;
wire main_sdram_bankmachine7_cmd_buffer_lookahead_source_valid;
wire main_sdram_bankmachine7_cmd_buffer_lookahead_source_ready;
wire main_sdram_bankmachine7_cmd_buffer_lookahead_source_first;
wire main_sdram_bankmachine7_cmd_buffer_lookahead_source_last;
wire main_sdram_bankmachine7_cmd_buffer_lookahead_source_payload_we;
wire [20:0] main_sdram_bankmachine7_cmd_buffer_lookahead_source_payload_addr;
wire main_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_we;
wire main_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable;
wire main_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_re;
wire main_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_readable;
wire [23:0] main_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_din;
wire [23:0] main_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout;
reg [3:0] main_sdram_bankmachine7_cmd_buffer_lookahead_level = 4'd0;
reg main_sdram_bankmachine7_cmd_buffer_lookahead_replace = 1'd0;
reg [2:0] main_sdram_bankmachine7_cmd_buffer_lookahead_produce = 3'd0;
reg [2:0] main_sdram_bankmachine7_cmd_buffer_lookahead_consume = 3'd0;
reg [2:0] main_sdram_bankmachine7_cmd_buffer_lookahead_wrport_adr = 3'd0;
wire [23:0] main_sdram_bankmachine7_cmd_buffer_lookahead_wrport_dat_r;
wire main_sdram_bankmachine7_cmd_buffer_lookahead_wrport_we;
wire [23:0] main_sdram_bankmachine7_cmd_buffer_lookahead_wrport_dat_w;
wire main_sdram_bankmachine7_cmd_buffer_lookahead_do_read;
wire [2:0] main_sdram_bankmachine7_cmd_buffer_lookahead_rdport_adr;
wire [23:0] main_sdram_bankmachine7_cmd_buffer_lookahead_rdport_dat_r;
wire main_sdram_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_we;
wire [20:0] main_sdram_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_addr;
wire main_sdram_bankmachine7_cmd_buffer_lookahead_fifo_in_first;
wire main_sdram_bankmachine7_cmd_buffer_lookahead_fifo_in_last;
wire main_sdram_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we;
wire [20:0] main_sdram_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr;
wire main_sdram_bankmachine7_cmd_buffer_lookahead_fifo_out_first;
wire main_sdram_bankmachine7_cmd_buffer_lookahead_fifo_out_last;
wire main_sdram_bankmachine7_cmd_buffer_sink_valid;
wire main_sdram_bankmachine7_cmd_buffer_sink_ready;
wire main_sdram_bankmachine7_cmd_buffer_sink_first;
wire main_sdram_bankmachine7_cmd_buffer_sink_last;
wire main_sdram_bankmachine7_cmd_buffer_sink_payload_we;
wire [20:0] main_sdram_bankmachine7_cmd_buffer_sink_payload_addr;
wire main_sdram_bankmachine7_cmd_buffer_source_valid;
wire main_sdram_bankmachine7_cmd_buffer_source_ready;
wire main_sdram_bankmachine7_cmd_buffer_source_first;
wire main_sdram_bankmachine7_cmd_buffer_source_last;
reg main_sdram_bankmachine7_cmd_buffer_source_payload_we = 1'd0;
reg [20:0] main_sdram_bankmachine7_cmd_buffer_source_payload_addr = 21'd0;
wire main_sdram_bankmachine7_cmd_buffer_pipe_ce;
wire main_sdram_bankmachine7_cmd_buffer_busy;
reg main_sdram_bankmachine7_cmd_buffer_valid_n = 1'd0;
reg main_sdram_bankmachine7_cmd_buffer_first_n = 1'd0;
reg main_sdram_bankmachine7_cmd_buffer_last_n = 1'd0;
reg [13:0] main_sdram_bankmachine7_row = 14'd0;
reg main_sdram_bankmachine7_row_opened = 1'd0;
wire main_sdram_bankmachine7_row_hit;
reg main_sdram_bankmachine7_row_open = 1'd0;
reg main_sdram_bankmachine7_row_close = 1'd0;
reg main_sdram_bankmachine7_row_col_n_addr_sel = 1'd0;
wire main_sdram_bankmachine7_twtpcon_valid;
(* dont_touch = "true" *) reg main_sdram_bankmachine7_twtpcon_ready = 1'd1;
reg [2:0] main_sdram_bankmachine7_twtpcon_count = 3'd0;
wire main_sdram_bankmachine7_trccon_valid;
(* dont_touch = "true" *) reg main_sdram_bankmachine7_trccon_ready = 1'd1;
reg [1:0] main_sdram_bankmachine7_trccon_count = 2'd0;
wire main_sdram_bankmachine7_trascon_valid;
(* dont_touch = "true" *) reg main_sdram_bankmachine7_trascon_ready = 1'd1;
reg [1:0] main_sdram_bankmachine7_trascon_count = 2'd0;
wire main_sdram_ras_allowed;
wire main_sdram_cas_allowed;
reg main_sdram_choose_cmd_want_reads = 1'd0;
reg main_sdram_choose_cmd_want_writes = 1'd0;
reg main_sdram_choose_cmd_want_cmds = 1'd0;
reg main_sdram_choose_cmd_want_activates = 1'd0;
wire main_sdram_choose_cmd_cmd_valid;
reg main_sdram_choose_cmd_cmd_ready = 1'd0;
wire [13:0] main_sdram_choose_cmd_cmd_payload_a;
wire [2:0] main_sdram_choose_cmd_cmd_payload_ba;
reg main_sdram_choose_cmd_cmd_payload_cas = 1'd0;
reg main_sdram_choose_cmd_cmd_payload_ras = 1'd0;
reg main_sdram_choose_cmd_cmd_payload_we = 1'd0;
wire main_sdram_choose_cmd_cmd_payload_is_cmd;
wire main_sdram_choose_cmd_cmd_payload_is_read;
wire main_sdram_choose_cmd_cmd_payload_is_write;
reg [7:0] main_sdram_choose_cmd_valids = 8'd0;
wire [7:0] main_sdram_choose_cmd_request;
reg [2:0] main_sdram_choose_cmd_grant = 3'd0;
wire main_sdram_choose_cmd_ce;
reg main_sdram_choose_req_want_reads = 1'd0;
reg main_sdram_choose_req_want_writes = 1'd0;
reg main_sdram_choose_req_want_cmds = 1'd0;
reg main_sdram_choose_req_want_activates = 1'd0;
wire main_sdram_choose_req_cmd_valid;
reg main_sdram_choose_req_cmd_ready = 1'd0;
wire [13:0] main_sdram_choose_req_cmd_payload_a;
wire [2:0] main_sdram_choose_req_cmd_payload_ba;
reg main_sdram_choose_req_cmd_payload_cas = 1'd0;
reg main_sdram_choose_req_cmd_payload_ras = 1'd0;
reg main_sdram_choose_req_cmd_payload_we = 1'd0;
wire main_sdram_choose_req_cmd_payload_is_cmd;
wire main_sdram_choose_req_cmd_payload_is_read;
wire main_sdram_choose_req_cmd_payload_is_write;
reg [7:0] main_sdram_choose_req_valids = 8'd0;
wire [7:0] main_sdram_choose_req_request;
reg [2:0] main_sdram_choose_req_grant = 3'd0;
wire main_sdram_choose_req_ce;
reg [13:0] main_sdram_nop_a = 14'd0;
reg [2:0] main_sdram_nop_ba = 3'd0;
reg [1:0] main_sdram_steerer_sel0 = 2'd0;
reg [1:0] main_sdram_steerer_sel1 = 2'd0;
reg [1:0] main_sdram_steerer_sel2 = 2'd0;
reg [1:0] main_sdram_steerer_sel3 = 2'd0;
reg main_sdram_steerer0 = 1'd1;
reg main_sdram_steerer1 = 1'd1;
reg main_sdram_steerer2 = 1'd1;
reg main_sdram_steerer3 = 1'd1;
reg main_sdram_steerer4 = 1'd1;
reg main_sdram_steerer5 = 1'd1;
reg main_sdram_steerer6 = 1'd1;
reg main_sdram_steerer7 = 1'd1;
wire main_sdram_trrdcon_valid;
(* dont_touch = "true" *) reg main_sdram_trrdcon_ready = 1'd1;
reg main_sdram_trrdcon_count = 1'd0;
wire main_sdram_tfawcon_valid;
(* dont_touch = "true" *) reg main_sdram_tfawcon_ready = 1'd1;
wire [1:0] main_sdram_tfawcon_count;
reg [2:0] main_sdram_tfawcon_window = 3'd0;
wire main_sdram_tccdcon_valid;
(* dont_touch = "true" *) reg main_sdram_tccdcon_ready = 1'd1;
reg main_sdram_tccdcon_count = 1'd0;
wire main_sdram_twtrcon_valid;
(* dont_touch = "true" *) reg main_sdram_twtrcon_ready = 1'd1;
reg [2:0] main_sdram_twtrcon_count = 3'd0;
wire main_sdram_read_available;
wire main_sdram_write_available;
reg main_sdram_en0 = 1'd0;
wire main_sdram_max_time0;
reg [4:0] main_sdram_time0 = 5'd0;
reg main_sdram_en1 = 1'd0;
wire main_sdram_max_time1;
reg [3:0] main_sdram_time1 = 4'd0;
wire main_sdram_go_to_refresh;
reg main_port_cmd_valid = 1'd0;
wire main_port_cmd_ready;
reg main_port_cmd_payload_we = 1'd0;
wire [23:0] main_port_cmd_payload_addr;
reg main_port_wdata_valid = 1'd0;
wire main_port_wdata_ready;
wire [127:0] main_port_wdata_payload_data;
wire [15:0] main_port_wdata_payload_we;
wire main_port_rdata_valid;
reg main_port_rdata_ready = 1'd0;
wire [127:0] main_port_rdata_payload_data;
wire [29:0] main_interface1_wb_sdram_adr;
wire [31:0] main_interface1_wb_sdram_dat_w;
wire [31:0] main_interface1_wb_sdram_dat_r;
wire [3:0] main_interface1_wb_sdram_sel;
wire main_interface1_wb_sdram_cyc;
wire main_interface1_wb_sdram_stb;
wire main_interface1_wb_sdram_ack;
wire main_interface1_wb_sdram_we;
wire [2:0] main_interface1_wb_sdram_cti;
wire [1:0] main_interface1_wb_sdram_bte;
wire main_interface1_wb_sdram_err;
wire [29:0] main_adr;
wire [127:0] main_dat_w;
wire [127:0] main_dat_r;
wire [15:0] main_sel;
reg main_cyc = 1'd0;
reg main_stb = 1'd0;
reg main_ack = 1'd0;
reg main_we = 1'd0;
wire [8:0] main_data_port_adr;
wire [127:0] main_data_port_dat_r;
reg [15:0] main_data_port_we = 16'd0;
reg [127:0] main_data_port_dat_w = 128'd0;
reg main_write_from_slave = 1'd0;
reg [1:0] main_adr_offset_r = 2'd0;
wire [8:0] main_tag_port_adr;
wire [23:0] main_tag_port_dat_r;
reg main_tag_port_we = 1'd0;
wire [23:0] main_tag_port_dat_w;
wire [22:0] main_tag_do_tag;
wire main_tag_do_dirty;
wire [22:0] main_tag_di_tag;
reg main_tag_di_dirty = 1'd0;
reg main_word_clr = 1'd0;
reg main_word_inc = 1'd0;
reg builder_wb2csr_state = 1'd0;
reg builder_wb2csr_next_state = 1'd0;
wire builder_pll_fb;
reg [1:0] builder_refresher_state = 2'd0;
reg [1:0] builder_refresher_next_state = 2'd0;
reg [2:0] builder_bankmachine0_state = 3'd0;
reg [2:0] builder_bankmachine0_next_state = 3'd0;
reg [2:0] builder_bankmachine1_state = 3'd0;
reg [2:0] builder_bankmachine1_next_state = 3'd0;
reg [2:0] builder_bankmachine2_state = 3'd0;
reg [2:0] builder_bankmachine2_next_state = 3'd0;
reg [2:0] builder_bankmachine3_state = 3'd0;
reg [2:0] builder_bankmachine3_next_state = 3'd0;
reg [2:0] builder_bankmachine4_state = 3'd0;
reg [2:0] builder_bankmachine4_next_state = 3'd0;
reg [2:0] builder_bankmachine5_state = 3'd0;
reg [2:0] builder_bankmachine5_next_state = 3'd0;
reg [2:0] builder_bankmachine6_state = 3'd0;
reg [2:0] builder_bankmachine6_next_state = 3'd0;
reg [2:0] builder_bankmachine7_state = 3'd0;
reg [2:0] builder_bankmachine7_next_state = 3'd0;
reg [3:0] builder_multiplexer_state = 4'd0;
reg [3:0] builder_multiplexer_next_state = 4'd0;
wire builder_roundrobin0_request;
wire builder_roundrobin0_grant;
wire builder_roundrobin0_ce;
wire builder_roundrobin1_request;
wire builder_roundrobin1_grant;
wire builder_roundrobin1_ce;
wire builder_roundrobin2_request;
wire builder_roundrobin2_grant;
wire builder_roundrobin2_ce;
wire builder_roundrobin3_request;
wire builder_roundrobin3_grant;
wire builder_roundrobin3_ce;
wire builder_roundrobin4_request;
wire builder_roundrobin4_grant;
wire builder_roundrobin4_ce;
wire builder_roundrobin5_request;
wire builder_roundrobin5_grant;
wire builder_roundrobin5_ce;
wire builder_roundrobin6_request;
wire builder_roundrobin6_grant;
wire builder_roundrobin6_ce;
wire builder_roundrobin7_request;
wire builder_roundrobin7_grant;
wire builder_roundrobin7_ce;
reg [2:0] builder_rbank = 3'd0;
reg [2:0] builder_wbank = 3'd0;
reg builder_locked0 = 1'd0;
reg builder_locked1 = 1'd0;
reg builder_locked2 = 1'd0;
reg builder_locked3 = 1'd0;
reg builder_locked4 = 1'd0;
reg builder_locked5 = 1'd0;
reg builder_locked6 = 1'd0;
reg builder_locked7 = 1'd0;
reg builder_new_master_wdata_ready0 = 1'd0;
reg builder_new_master_wdata_ready1 = 1'd0;
reg builder_new_master_wdata_ready2 = 1'd0;
reg builder_new_master_rdata_valid0 = 1'd0;
reg builder_new_master_rdata_valid1 = 1'd0;
reg builder_new_master_rdata_valid2 = 1'd0;
reg builder_new_master_rdata_valid3 = 1'd0;
reg builder_new_master_rdata_valid4 = 1'd0;
reg builder_new_master_rdata_valid5 = 1'd0;
reg builder_new_master_rdata_valid6 = 1'd0;
reg builder_new_master_rdata_valid7 = 1'd0;
reg builder_new_master_rdata_valid8 = 1'd0;
reg builder_new_master_rdata_valid9 = 1'd0;
reg [2:0] builder_fullmemorywe_state = 3'd0;
reg [2:0] builder_fullmemorywe_next_state = 3'd0;
reg [1:0] builder_litedramwishbone2native_state = 2'd0;
reg [1:0] builder_litedramwishbone2native_next_state = 2'd0;
wire builder_wb_sdram_con_request;
wire builder_wb_sdram_con_grant;
wire [29:0] builder_minsoc_shared_adr;
wire [31:0] builder_minsoc_shared_dat_w;
reg [31:0] builder_minsoc_shared_dat_r = 32'd0;
wire [3:0] builder_minsoc_shared_sel;
wire builder_minsoc_shared_cyc;
wire builder_minsoc_shared_stb;
reg builder_minsoc_shared_ack = 1'd0;
wire builder_minsoc_shared_we;
wire [2:0] builder_minsoc_shared_cti;
wire [1:0] builder_minsoc_shared_bte;
wire builder_minsoc_shared_err;
wire [1:0] builder_minsoc_request;
reg builder_minsoc_grant = 1'd0;
reg [3:0] builder_minsoc_slave_sel = 4'd0;
reg [3:0] builder_minsoc_slave_sel_r = 4'd0;
reg builder_minsoc_error = 1'd0;
wire builder_minsoc_wait;
wire builder_minsoc_done;
reg [19:0] builder_minsoc_count = 20'd1000000;
wire [13:0] builder_minsoc_interface0_bank_bus_adr;
wire builder_minsoc_interface0_bank_bus_we;
wire [7:0] builder_minsoc_interface0_bank_bus_dat_w;
reg [7:0] builder_minsoc_interface0_bank_bus_dat_r = 8'd0;
wire builder_minsoc_csrbank0_scratch3_re;
wire [7:0] builder_minsoc_csrbank0_scratch3_r;
wire builder_minsoc_csrbank0_scratch3_we;
wire [7:0] builder_minsoc_csrbank0_scratch3_w;
wire builder_minsoc_csrbank0_scratch2_re;
wire [7:0] builder_minsoc_csrbank0_scratch2_r;
wire builder_minsoc_csrbank0_scratch2_we;
wire [7:0] builder_minsoc_csrbank0_scratch2_w;
wire builder_minsoc_csrbank0_scratch1_re;
wire [7:0] builder_minsoc_csrbank0_scratch1_r;
wire builder_minsoc_csrbank0_scratch1_we;
wire [7:0] builder_minsoc_csrbank0_scratch1_w;
wire builder_minsoc_csrbank0_scratch0_re;
wire [7:0] builder_minsoc_csrbank0_scratch0_r;
wire builder_minsoc_csrbank0_scratch0_we;
wire [7:0] builder_minsoc_csrbank0_scratch0_w;
wire builder_minsoc_csrbank0_bus_errors3_re;
wire [7:0] builder_minsoc_csrbank0_bus_errors3_r;
wire builder_minsoc_csrbank0_bus_errors3_we;
wire [7:0] builder_minsoc_csrbank0_bus_errors3_w;
wire builder_minsoc_csrbank0_bus_errors2_re;
wire [7:0] builder_minsoc_csrbank0_bus_errors2_r;
wire builder_minsoc_csrbank0_bus_errors2_we;
wire [7:0] builder_minsoc_csrbank0_bus_errors2_w;
wire builder_minsoc_csrbank0_bus_errors1_re;
wire [7:0] builder_minsoc_csrbank0_bus_errors1_r;
wire builder_minsoc_csrbank0_bus_errors1_we;
wire [7:0] builder_minsoc_csrbank0_bus_errors1_w;
wire builder_minsoc_csrbank0_bus_errors0_re;
wire [7:0] builder_minsoc_csrbank0_bus_errors0_r;
wire builder_minsoc_csrbank0_bus_errors0_we;
wire [7:0] builder_minsoc_csrbank0_bus_errors0_w;
wire builder_minsoc_csrbank0_sel;
wire [13:0] builder_minsoc_interface1_bank_bus_adr;
wire builder_minsoc_interface1_bank_bus_we;
wire [7:0] builder_minsoc_interface1_bank_bus_dat_w;
reg [7:0] builder_minsoc_interface1_bank_bus_dat_r = 8'd0;
wire builder_minsoc_csrbank1_half_sys8x_taps0_re;
wire [4:0] builder_minsoc_csrbank1_half_sys8x_taps0_r;
wire builder_minsoc_csrbank1_half_sys8x_taps0_we;
wire [4:0] builder_minsoc_csrbank1_half_sys8x_taps0_w;
wire builder_minsoc_csrbank1_dly_sel0_re;
wire [1:0] builder_minsoc_csrbank1_dly_sel0_r;
wire builder_minsoc_csrbank1_dly_sel0_we;
wire [1:0] builder_minsoc_csrbank1_dly_sel0_w;
wire builder_minsoc_csrbank1_sel;
wire [13:0] builder_minsoc_interface2_bank_bus_adr;
wire builder_minsoc_interface2_bank_bus_we;
wire [7:0] builder_minsoc_interface2_bank_bus_dat_w;
reg [7:0] builder_minsoc_interface2_bank_bus_dat_r = 8'd0;
wire builder_minsoc_csrbank2_dfii_control0_re;
wire [3:0] builder_minsoc_csrbank2_dfii_control0_r;
wire builder_minsoc_csrbank2_dfii_control0_we;
wire [3:0] builder_minsoc_csrbank2_dfii_control0_w;
wire builder_minsoc_csrbank2_dfii_pi0_command0_re;
wire [5:0] builder_minsoc_csrbank2_dfii_pi0_command0_r;
wire builder_minsoc_csrbank2_dfii_pi0_command0_we;
wire [5:0] builder_minsoc_csrbank2_dfii_pi0_command0_w;
wire builder_minsoc_csrbank2_dfii_pi0_address1_re;
wire [5:0] builder_minsoc_csrbank2_dfii_pi0_address1_r;
wire builder_minsoc_csrbank2_dfii_pi0_address1_we;
wire [5:0] builder_minsoc_csrbank2_dfii_pi0_address1_w;
wire builder_minsoc_csrbank2_dfii_pi0_address0_re;
wire [7:0] builder_minsoc_csrbank2_dfii_pi0_address0_r;
wire builder_minsoc_csrbank2_dfii_pi0_address0_we;
wire [7:0] builder_minsoc_csrbank2_dfii_pi0_address0_w;
wire builder_minsoc_csrbank2_dfii_pi0_baddress0_re;
wire [2:0] builder_minsoc_csrbank2_dfii_pi0_baddress0_r;
wire builder_minsoc_csrbank2_dfii_pi0_baddress0_we;
wire [2:0] builder_minsoc_csrbank2_dfii_pi0_baddress0_w;
wire builder_minsoc_csrbank2_dfii_pi0_wrdata3_re;
wire [7:0] builder_minsoc_csrbank2_dfii_pi0_wrdata3_r;
wire builder_minsoc_csrbank2_dfii_pi0_wrdata3_we;
wire [7:0] builder_minsoc_csrbank2_dfii_pi0_wrdata3_w;
wire builder_minsoc_csrbank2_dfii_pi0_wrdata2_re;
wire [7:0] builder_minsoc_csrbank2_dfii_pi0_wrdata2_r;
wire builder_minsoc_csrbank2_dfii_pi0_wrdata2_we;
wire [7:0] builder_minsoc_csrbank2_dfii_pi0_wrdata2_w;
wire builder_minsoc_csrbank2_dfii_pi0_wrdata1_re;
wire [7:0] builder_minsoc_csrbank2_dfii_pi0_wrdata1_r;
wire builder_minsoc_csrbank2_dfii_pi0_wrdata1_we;
wire [7:0] builder_minsoc_csrbank2_dfii_pi0_wrdata1_w;
wire builder_minsoc_csrbank2_dfii_pi0_wrdata0_re;
wire [7:0] builder_minsoc_csrbank2_dfii_pi0_wrdata0_r;
wire builder_minsoc_csrbank2_dfii_pi0_wrdata0_we;
wire [7:0] builder_minsoc_csrbank2_dfii_pi0_wrdata0_w;
wire builder_minsoc_csrbank2_dfii_pi0_rddata3_re;
wire [7:0] builder_minsoc_csrbank2_dfii_pi0_rddata3_r;
wire builder_minsoc_csrbank2_dfii_pi0_rddata3_we;
wire [7:0] builder_minsoc_csrbank2_dfii_pi0_rddata3_w;
wire builder_minsoc_csrbank2_dfii_pi0_rddata2_re;
wire [7:0] builder_minsoc_csrbank2_dfii_pi0_rddata2_r;
wire builder_minsoc_csrbank2_dfii_pi0_rddata2_we;
wire [7:0] builder_minsoc_csrbank2_dfii_pi0_rddata2_w;
wire builder_minsoc_csrbank2_dfii_pi0_rddata1_re;
wire [7:0] builder_minsoc_csrbank2_dfii_pi0_rddata1_r;
wire builder_minsoc_csrbank2_dfii_pi0_rddata1_we;
wire [7:0] builder_minsoc_csrbank2_dfii_pi0_rddata1_w;
wire builder_minsoc_csrbank2_dfii_pi0_rddata0_re;
wire [7:0] builder_minsoc_csrbank2_dfii_pi0_rddata0_r;
wire builder_minsoc_csrbank2_dfii_pi0_rddata0_we;
wire [7:0] builder_minsoc_csrbank2_dfii_pi0_rddata0_w;
wire builder_minsoc_csrbank2_dfii_pi1_command0_re;
wire [5:0] builder_minsoc_csrbank2_dfii_pi1_command0_r;
wire builder_minsoc_csrbank2_dfii_pi1_command0_we;
wire [5:0] builder_minsoc_csrbank2_dfii_pi1_command0_w;
wire builder_minsoc_csrbank2_dfii_pi1_address1_re;
wire [5:0] builder_minsoc_csrbank2_dfii_pi1_address1_r;
wire builder_minsoc_csrbank2_dfii_pi1_address1_we;
wire [5:0] builder_minsoc_csrbank2_dfii_pi1_address1_w;
wire builder_minsoc_csrbank2_dfii_pi1_address0_re;
wire [7:0] builder_minsoc_csrbank2_dfii_pi1_address0_r;
wire builder_minsoc_csrbank2_dfii_pi1_address0_we;
wire [7:0] builder_minsoc_csrbank2_dfii_pi1_address0_w;
wire builder_minsoc_csrbank2_dfii_pi1_baddress0_re;
wire [2:0] builder_minsoc_csrbank2_dfii_pi1_baddress0_r;
wire builder_minsoc_csrbank2_dfii_pi1_baddress0_we;
wire [2:0] builder_minsoc_csrbank2_dfii_pi1_baddress0_w;
wire builder_minsoc_csrbank2_dfii_pi1_wrdata3_re;
wire [7:0] builder_minsoc_csrbank2_dfii_pi1_wrdata3_r;
wire builder_minsoc_csrbank2_dfii_pi1_wrdata3_we;
wire [7:0] builder_minsoc_csrbank2_dfii_pi1_wrdata3_w;
wire builder_minsoc_csrbank2_dfii_pi1_wrdata2_re;
wire [7:0] builder_minsoc_csrbank2_dfii_pi1_wrdata2_r;
wire builder_minsoc_csrbank2_dfii_pi1_wrdata2_we;
wire [7:0] builder_minsoc_csrbank2_dfii_pi1_wrdata2_w;
wire builder_minsoc_csrbank2_dfii_pi1_wrdata1_re;
wire [7:0] builder_minsoc_csrbank2_dfii_pi1_wrdata1_r;
wire builder_minsoc_csrbank2_dfii_pi1_wrdata1_we;
wire [7:0] builder_minsoc_csrbank2_dfii_pi1_wrdata1_w;
wire builder_minsoc_csrbank2_dfii_pi1_wrdata0_re;
wire [7:0] builder_minsoc_csrbank2_dfii_pi1_wrdata0_r;
wire builder_minsoc_csrbank2_dfii_pi1_wrdata0_we;
wire [7:0] builder_minsoc_csrbank2_dfii_pi1_wrdata0_w;
wire builder_minsoc_csrbank2_dfii_pi1_rddata3_re;
wire [7:0] builder_minsoc_csrbank2_dfii_pi1_rddata3_r;
wire builder_minsoc_csrbank2_dfii_pi1_rddata3_we;
wire [7:0] builder_minsoc_csrbank2_dfii_pi1_rddata3_w;
wire builder_minsoc_csrbank2_dfii_pi1_rddata2_re;
wire [7:0] builder_minsoc_csrbank2_dfii_pi1_rddata2_r;
wire builder_minsoc_csrbank2_dfii_pi1_rddata2_we;
wire [7:0] builder_minsoc_csrbank2_dfii_pi1_rddata2_w;
wire builder_minsoc_csrbank2_dfii_pi1_rddata1_re;
wire [7:0] builder_minsoc_csrbank2_dfii_pi1_rddata1_r;
wire builder_minsoc_csrbank2_dfii_pi1_rddata1_we;
wire [7:0] builder_minsoc_csrbank2_dfii_pi1_rddata1_w;
wire builder_minsoc_csrbank2_dfii_pi1_rddata0_re;
wire [7:0] builder_minsoc_csrbank2_dfii_pi1_rddata0_r;
wire builder_minsoc_csrbank2_dfii_pi1_rddata0_we;
wire [7:0] builder_minsoc_csrbank2_dfii_pi1_rddata0_w;
wire builder_minsoc_csrbank2_dfii_pi2_command0_re;
wire [5:0] builder_minsoc_csrbank2_dfii_pi2_command0_r;
wire builder_minsoc_csrbank2_dfii_pi2_command0_we;
wire [5:0] builder_minsoc_csrbank2_dfii_pi2_command0_w;
wire builder_minsoc_csrbank2_dfii_pi2_address1_re;
wire [5:0] builder_minsoc_csrbank2_dfii_pi2_address1_r;
wire builder_minsoc_csrbank2_dfii_pi2_address1_we;
wire [5:0] builder_minsoc_csrbank2_dfii_pi2_address1_w;
wire builder_minsoc_csrbank2_dfii_pi2_address0_re;
wire [7:0] builder_minsoc_csrbank2_dfii_pi2_address0_r;
wire builder_minsoc_csrbank2_dfii_pi2_address0_we;
wire [7:0] builder_minsoc_csrbank2_dfii_pi2_address0_w;
wire builder_minsoc_csrbank2_dfii_pi2_baddress0_re;
wire [2:0] builder_minsoc_csrbank2_dfii_pi2_baddress0_r;
wire builder_minsoc_csrbank2_dfii_pi2_baddress0_we;
wire [2:0] builder_minsoc_csrbank2_dfii_pi2_baddress0_w;
wire builder_minsoc_csrbank2_dfii_pi2_wrdata3_re;
wire [7:0] builder_minsoc_csrbank2_dfii_pi2_wrdata3_r;
wire builder_minsoc_csrbank2_dfii_pi2_wrdata3_we;
wire [7:0] builder_minsoc_csrbank2_dfii_pi2_wrdata3_w;
wire builder_minsoc_csrbank2_dfii_pi2_wrdata2_re;
wire [7:0] builder_minsoc_csrbank2_dfii_pi2_wrdata2_r;
wire builder_minsoc_csrbank2_dfii_pi2_wrdata2_we;
wire [7:0] builder_minsoc_csrbank2_dfii_pi2_wrdata2_w;
wire builder_minsoc_csrbank2_dfii_pi2_wrdata1_re;
wire [7:0] builder_minsoc_csrbank2_dfii_pi2_wrdata1_r;
wire builder_minsoc_csrbank2_dfii_pi2_wrdata1_we;
wire [7:0] builder_minsoc_csrbank2_dfii_pi2_wrdata1_w;
wire builder_minsoc_csrbank2_dfii_pi2_wrdata0_re;
wire [7:0] builder_minsoc_csrbank2_dfii_pi2_wrdata0_r;
wire builder_minsoc_csrbank2_dfii_pi2_wrdata0_we;
wire [7:0] builder_minsoc_csrbank2_dfii_pi2_wrdata0_w;
wire builder_minsoc_csrbank2_dfii_pi2_rddata3_re;
wire [7:0] builder_minsoc_csrbank2_dfii_pi2_rddata3_r;
wire builder_minsoc_csrbank2_dfii_pi2_rddata3_we;
wire [7:0] builder_minsoc_csrbank2_dfii_pi2_rddata3_w;
wire builder_minsoc_csrbank2_dfii_pi2_rddata2_re;
wire [7:0] builder_minsoc_csrbank2_dfii_pi2_rddata2_r;
wire builder_minsoc_csrbank2_dfii_pi2_rddata2_we;
wire [7:0] builder_minsoc_csrbank2_dfii_pi2_rddata2_w;
wire builder_minsoc_csrbank2_dfii_pi2_rddata1_re;
wire [7:0] builder_minsoc_csrbank2_dfii_pi2_rddata1_r;
wire builder_minsoc_csrbank2_dfii_pi2_rddata1_we;
wire [7:0] builder_minsoc_csrbank2_dfii_pi2_rddata1_w;
wire builder_minsoc_csrbank2_dfii_pi2_rddata0_re;
wire [7:0] builder_minsoc_csrbank2_dfii_pi2_rddata0_r;
wire builder_minsoc_csrbank2_dfii_pi2_rddata0_we;
wire [7:0] builder_minsoc_csrbank2_dfii_pi2_rddata0_w;
wire builder_minsoc_csrbank2_dfii_pi3_command0_re;
wire [5:0] builder_minsoc_csrbank2_dfii_pi3_command0_r;
wire builder_minsoc_csrbank2_dfii_pi3_command0_we;
wire [5:0] builder_minsoc_csrbank2_dfii_pi3_command0_w;
wire builder_minsoc_csrbank2_dfii_pi3_address1_re;
wire [5:0] builder_minsoc_csrbank2_dfii_pi3_address1_r;
wire builder_minsoc_csrbank2_dfii_pi3_address1_we;
wire [5:0] builder_minsoc_csrbank2_dfii_pi3_address1_w;
wire builder_minsoc_csrbank2_dfii_pi3_address0_re;
wire [7:0] builder_minsoc_csrbank2_dfii_pi3_address0_r;
wire builder_minsoc_csrbank2_dfii_pi3_address0_we;
wire [7:0] builder_minsoc_csrbank2_dfii_pi3_address0_w;
wire builder_minsoc_csrbank2_dfii_pi3_baddress0_re;
wire [2:0] builder_minsoc_csrbank2_dfii_pi3_baddress0_r;
wire builder_minsoc_csrbank2_dfii_pi3_baddress0_we;
wire [2:0] builder_minsoc_csrbank2_dfii_pi3_baddress0_w;
wire builder_minsoc_csrbank2_dfii_pi3_wrdata3_re;
wire [7:0] builder_minsoc_csrbank2_dfii_pi3_wrdata3_r;
wire builder_minsoc_csrbank2_dfii_pi3_wrdata3_we;
wire [7:0] builder_minsoc_csrbank2_dfii_pi3_wrdata3_w;
wire builder_minsoc_csrbank2_dfii_pi3_wrdata2_re;
wire [7:0] builder_minsoc_csrbank2_dfii_pi3_wrdata2_r;
wire builder_minsoc_csrbank2_dfii_pi3_wrdata2_we;
wire [7:0] builder_minsoc_csrbank2_dfii_pi3_wrdata2_w;
wire builder_minsoc_csrbank2_dfii_pi3_wrdata1_re;
wire [7:0] builder_minsoc_csrbank2_dfii_pi3_wrdata1_r;
wire builder_minsoc_csrbank2_dfii_pi3_wrdata1_we;
wire [7:0] builder_minsoc_csrbank2_dfii_pi3_wrdata1_w;
wire builder_minsoc_csrbank2_dfii_pi3_wrdata0_re;
wire [7:0] builder_minsoc_csrbank2_dfii_pi3_wrdata0_r;
wire builder_minsoc_csrbank2_dfii_pi3_wrdata0_we;
wire [7:0] builder_minsoc_csrbank2_dfii_pi3_wrdata0_w;
wire builder_minsoc_csrbank2_dfii_pi3_rddata3_re;
wire [7:0] builder_minsoc_csrbank2_dfii_pi3_rddata3_r;
wire builder_minsoc_csrbank2_dfii_pi3_rddata3_we;
wire [7:0] builder_minsoc_csrbank2_dfii_pi3_rddata3_w;
wire builder_minsoc_csrbank2_dfii_pi3_rddata2_re;
wire [7:0] builder_minsoc_csrbank2_dfii_pi3_rddata2_r;
wire builder_minsoc_csrbank2_dfii_pi3_rddata2_we;
wire [7:0] builder_minsoc_csrbank2_dfii_pi3_rddata2_w;
wire builder_minsoc_csrbank2_dfii_pi3_rddata1_re;
wire [7:0] builder_minsoc_csrbank2_dfii_pi3_rddata1_r;
wire builder_minsoc_csrbank2_dfii_pi3_rddata1_we;
wire [7:0] builder_minsoc_csrbank2_dfii_pi3_rddata1_w;
wire builder_minsoc_csrbank2_dfii_pi3_rddata0_re;
wire [7:0] builder_minsoc_csrbank2_dfii_pi3_rddata0_r;
wire builder_minsoc_csrbank2_dfii_pi3_rddata0_we;
wire [7:0] builder_minsoc_csrbank2_dfii_pi3_rddata0_w;
wire builder_minsoc_csrbank2_sel;
wire [13:0] builder_minsoc_interface3_bank_bus_adr;
wire builder_minsoc_interface3_bank_bus_we;
wire [7:0] builder_minsoc_interface3_bank_bus_dat_w;
reg [7:0] builder_minsoc_interface3_bank_bus_dat_r = 8'd0;
wire builder_minsoc_csrbank3_load3_re;
wire [7:0] builder_minsoc_csrbank3_load3_r;
wire builder_minsoc_csrbank3_load3_we;
wire [7:0] builder_minsoc_csrbank3_load3_w;
wire builder_minsoc_csrbank3_load2_re;
wire [7:0] builder_minsoc_csrbank3_load2_r;
wire builder_minsoc_csrbank3_load2_we;
wire [7:0] builder_minsoc_csrbank3_load2_w;
wire builder_minsoc_csrbank3_load1_re;
wire [7:0] builder_minsoc_csrbank3_load1_r;
wire builder_minsoc_csrbank3_load1_we;
wire [7:0] builder_minsoc_csrbank3_load1_w;
wire builder_minsoc_csrbank3_load0_re;
wire [7:0] builder_minsoc_csrbank3_load0_r;
wire builder_minsoc_csrbank3_load0_we;
wire [7:0] builder_minsoc_csrbank3_load0_w;
wire builder_minsoc_csrbank3_reload3_re;
wire [7:0] builder_minsoc_csrbank3_reload3_r;
wire builder_minsoc_csrbank3_reload3_we;
wire [7:0] builder_minsoc_csrbank3_reload3_w;
wire builder_minsoc_csrbank3_reload2_re;
wire [7:0] builder_minsoc_csrbank3_reload2_r;
wire builder_minsoc_csrbank3_reload2_we;
wire [7:0] builder_minsoc_csrbank3_reload2_w;
wire builder_minsoc_csrbank3_reload1_re;
wire [7:0] builder_minsoc_csrbank3_reload1_r;
wire builder_minsoc_csrbank3_reload1_we;
wire [7:0] builder_minsoc_csrbank3_reload1_w;
wire builder_minsoc_csrbank3_reload0_re;
wire [7:0] builder_minsoc_csrbank3_reload0_r;
wire builder_minsoc_csrbank3_reload0_we;
wire [7:0] builder_minsoc_csrbank3_reload0_w;
wire builder_minsoc_csrbank3_en0_re;
wire builder_minsoc_csrbank3_en0_r;
wire builder_minsoc_csrbank3_en0_we;
wire builder_minsoc_csrbank3_en0_w;
wire builder_minsoc_csrbank3_update_value0_re;
wire builder_minsoc_csrbank3_update_value0_r;
wire builder_minsoc_csrbank3_update_value0_we;
wire builder_minsoc_csrbank3_update_value0_w;
wire builder_minsoc_csrbank3_value3_re;
wire [7:0] builder_minsoc_csrbank3_value3_r;
wire builder_minsoc_csrbank3_value3_we;
wire [7:0] builder_minsoc_csrbank3_value3_w;
wire builder_minsoc_csrbank3_value2_re;
wire [7:0] builder_minsoc_csrbank3_value2_r;
wire builder_minsoc_csrbank3_value2_we;
wire [7:0] builder_minsoc_csrbank3_value2_w;
wire builder_minsoc_csrbank3_value1_re;
wire [7:0] builder_minsoc_csrbank3_value1_r;
wire builder_minsoc_csrbank3_value1_we;
wire [7:0] builder_minsoc_csrbank3_value1_w;
wire builder_minsoc_csrbank3_value0_re;
wire [7:0] builder_minsoc_csrbank3_value0_r;
wire builder_minsoc_csrbank3_value0_we;
wire [7:0] builder_minsoc_csrbank3_value0_w;
wire builder_minsoc_csrbank3_ev_enable0_re;
wire builder_minsoc_csrbank3_ev_enable0_r;
wire builder_minsoc_csrbank3_ev_enable0_we;
wire builder_minsoc_csrbank3_ev_enable0_w;
wire builder_minsoc_csrbank3_sel;
wire [13:0] builder_minsoc_interface4_bank_bus_adr;
wire builder_minsoc_interface4_bank_bus_we;
wire [7:0] builder_minsoc_interface4_bank_bus_dat_w;
reg [7:0] builder_minsoc_interface4_bank_bus_dat_r = 8'd0;
wire builder_minsoc_csrbank4_txfull_re;
wire builder_minsoc_csrbank4_txfull_r;
wire builder_minsoc_csrbank4_txfull_we;
wire builder_minsoc_csrbank4_txfull_w;
wire builder_minsoc_csrbank4_rxempty_re;
wire builder_minsoc_csrbank4_rxempty_r;
wire builder_minsoc_csrbank4_rxempty_we;
wire builder_minsoc_csrbank4_rxempty_w;
wire builder_minsoc_csrbank4_ev_enable0_re;
wire [1:0] builder_minsoc_csrbank4_ev_enable0_r;
wire builder_minsoc_csrbank4_ev_enable0_we;
wire [1:0] builder_minsoc_csrbank4_ev_enable0_w;
wire builder_minsoc_csrbank4_sel;
wire [13:0] builder_minsoc_interface5_bank_bus_adr;
wire builder_minsoc_interface5_bank_bus_we;
wire [7:0] builder_minsoc_interface5_bank_bus_dat_w;
reg [7:0] builder_minsoc_interface5_bank_bus_dat_r = 8'd0;
wire builder_minsoc_csrbank5_tuning_word3_re;
wire [7:0] builder_minsoc_csrbank5_tuning_word3_r;
wire builder_minsoc_csrbank5_tuning_word3_we;
wire [7:0] builder_minsoc_csrbank5_tuning_word3_w;
wire builder_minsoc_csrbank5_tuning_word2_re;
wire [7:0] builder_minsoc_csrbank5_tuning_word2_r;
wire builder_minsoc_csrbank5_tuning_word2_we;
wire [7:0] builder_minsoc_csrbank5_tuning_word2_w;
wire builder_minsoc_csrbank5_tuning_word1_re;
wire [7:0] builder_minsoc_csrbank5_tuning_word1_r;
wire builder_minsoc_csrbank5_tuning_word1_we;
wire [7:0] builder_minsoc_csrbank5_tuning_word1_w;
wire builder_minsoc_csrbank5_tuning_word0_re;
wire [7:0] builder_minsoc_csrbank5_tuning_word0_r;
wire builder_minsoc_csrbank5_tuning_word0_we;
wire [7:0] builder_minsoc_csrbank5_tuning_word0_w;
wire builder_minsoc_csrbank5_sel;
wire [13:0] builder_minsoc_adr;
wire builder_minsoc_we;
wire [7:0] builder_minsoc_dat_w;
wire [7:0] builder_minsoc_dat_r;
reg builder_rhs_array_muxed0 = 1'd0;
reg [13:0] builder_rhs_array_muxed1 = 14'd0;
reg [2:0] builder_rhs_array_muxed2 = 3'd0;
reg builder_rhs_array_muxed3 = 1'd0;
reg builder_rhs_array_muxed4 = 1'd0;
reg builder_rhs_array_muxed5 = 1'd0;
reg builder_t_array_muxed0 = 1'd0;
reg builder_t_array_muxed1 = 1'd0;
reg builder_t_array_muxed2 = 1'd0;
reg builder_rhs_array_muxed6 = 1'd0;
reg [13:0] builder_rhs_array_muxed7 = 14'd0;
reg [2:0] builder_rhs_array_muxed8 = 3'd0;
reg builder_rhs_array_muxed9 = 1'd0;
reg builder_rhs_array_muxed10 = 1'd0;
reg builder_rhs_array_muxed11 = 1'd0;
reg builder_t_array_muxed3 = 1'd0;
reg builder_t_array_muxed4 = 1'd0;
reg builder_t_array_muxed5 = 1'd0;
reg [20:0] builder_rhs_array_muxed12 = 21'd0;
reg builder_rhs_array_muxed13 = 1'd0;
reg builder_rhs_array_muxed14 = 1'd0;
reg [20:0] builder_rhs_array_muxed15 = 21'd0;
reg builder_rhs_array_muxed16 = 1'd0;
reg builder_rhs_array_muxed17 = 1'd0;
reg [20:0] builder_rhs_array_muxed18 = 21'd0;
reg builder_rhs_array_muxed19 = 1'd0;
reg builder_rhs_array_muxed20 = 1'd0;
reg [20:0] builder_rhs_array_muxed21 = 21'd0;
reg builder_rhs_array_muxed22 = 1'd0;
reg builder_rhs_array_muxed23 = 1'd0;
reg [20:0] builder_rhs_array_muxed24 = 21'd0;
reg builder_rhs_array_muxed25 = 1'd0;
reg builder_rhs_array_muxed26 = 1'd0;
reg [20:0] builder_rhs_array_muxed27 = 21'd0;
reg builder_rhs_array_muxed28 = 1'd0;
reg builder_rhs_array_muxed29 = 1'd0;
reg [20:0] builder_rhs_array_muxed30 = 21'd0;
reg builder_rhs_array_muxed31 = 1'd0;
reg builder_rhs_array_muxed32 = 1'd0;
reg [20:0] builder_rhs_array_muxed33 = 21'd0;
reg builder_rhs_array_muxed34 = 1'd0;
reg builder_rhs_array_muxed35 = 1'd0;
reg [29:0] builder_rhs_array_muxed36 = 30'd0;
reg [31:0] builder_rhs_array_muxed37 = 32'd0;
reg [3:0] builder_rhs_array_muxed38 = 4'd0;
reg builder_rhs_array_muxed39 = 1'd0;
reg builder_rhs_array_muxed40 = 1'd0;
reg builder_rhs_array_muxed41 = 1'd0;
reg [2:0] builder_rhs_array_muxed42 = 3'd0;
reg [1:0] builder_rhs_array_muxed43 = 2'd0;
reg [29:0] builder_rhs_array_muxed44 = 30'd0;
reg [31:0] builder_rhs_array_muxed45 = 32'd0;
reg [3:0] builder_rhs_array_muxed46 = 4'd0;
reg builder_rhs_array_muxed47 = 1'd0;
reg builder_rhs_array_muxed48 = 1'd0;
reg builder_rhs_array_muxed49 = 1'd0;
reg [2:0] builder_rhs_array_muxed50 = 3'd0;
reg [1:0] builder_rhs_array_muxed51 = 2'd0;
reg [2:0] builder_array_muxed0 = 3'd0;
reg [13:0] builder_array_muxed1 = 14'd0;
reg builder_array_muxed2 = 1'd0;
reg builder_array_muxed3 = 1'd0;
reg builder_array_muxed4 = 1'd0;
reg builder_array_muxed5 = 1'd0;
reg builder_array_muxed6 = 1'd0;
reg [2:0] builder_array_muxed7 = 3'd0;
reg [13:0] builder_array_muxed8 = 14'd0;
reg builder_array_muxed9 = 1'd0;
reg builder_array_muxed10 = 1'd0;
reg builder_array_muxed11 = 1'd0;
reg builder_array_muxed12 = 1'd0;
reg builder_array_muxed13 = 1'd0;
reg [2:0] builder_array_muxed14 = 3'd0;
reg [13:0] builder_array_muxed15 = 14'd0;
reg builder_array_muxed16 = 1'd0;
reg builder_array_muxed17 = 1'd0;
reg builder_array_muxed18 = 1'd0;
reg builder_array_muxed19 = 1'd0;
reg builder_array_muxed20 = 1'd0;
reg [2:0] builder_array_muxed21 = 3'd0;
reg [13:0] builder_array_muxed22 = 14'd0;
reg builder_array_muxed23 = 1'd0;
reg builder_array_muxed24 = 1'd0;
reg builder_array_muxed25 = 1'd0;
reg builder_array_muxed26 = 1'd0;
reg builder_array_muxed27 = 1'd0;
(* async_reg = "true", mr_ff = "true", dont_touch = "true" *) reg builder_regs0 = 1'd0;
(* async_reg = "true", dont_touch = "true" *) reg builder_regs1 = 1'd0;
wire builder_xilinxasyncresetsynchronizerimpl0;
wire builder_xilinxasyncresetsynchronizerimpl0_rst_meta;
wire builder_xilinxasyncresetsynchronizerimpl1;
wire builder_xilinxasyncresetsynchronizerimpl1_rst_meta;
wire builder_xilinxasyncresetsynchronizerimpl1_expr;
wire builder_xilinxasyncresetsynchronizerimpl2;
wire builder_xilinxasyncresetsynchronizerimpl2_rst_meta;
wire builder_xilinxasyncresetsynchronizerimpl2_expr;
wire builder_xilinxasyncresetsynchronizerimpl3;
wire builder_xilinxasyncresetsynchronizerimpl3_rst_meta;
assign main_cpu_reset = main_ctrl_reset;
assign main_ctrl_bus_error = builder_minsoc_error;
always @(*) begin
main_cpu_interrupt <= 32'd0;
main_cpu_interrupt[1] <= main_timer0_irq;
main_cpu_interrupt[0] <= main_uart_irq;
end
assign main_ctrl_reset = main_ctrl_reset_reset_re;
assign main_ctrl_bus_errors_status = main_ctrl_bus_errors;
assign main_interface0_soc_bus_adr = main_cpu_ibus_adr;
assign main_interface0_soc_bus_dat_w = main_cpu_ibus_dat_w;
assign main_cpu_ibus_dat_r = main_interface0_soc_bus_dat_r;
assign main_interface0_soc_bus_sel = main_cpu_ibus_sel;
assign main_interface0_soc_bus_cyc = main_cpu_ibus_cyc;
assign main_interface0_soc_bus_stb = main_cpu_ibus_stb;
assign main_cpu_ibus_ack = main_interface0_soc_bus_ack;
assign main_interface0_soc_bus_we = main_cpu_ibus_we;
assign main_interface0_soc_bus_cti = main_cpu_ibus_cti;
assign main_interface0_soc_bus_bte = main_cpu_ibus_bte;
assign main_cpu_ibus_err = main_interface0_soc_bus_err;
assign main_interface1_soc_bus_adr = main_cpu_dbus_adr;
assign main_interface1_soc_bus_dat_w = main_cpu_dbus_dat_w;
assign main_cpu_dbus_dat_r = main_interface1_soc_bus_dat_r;
assign main_interface1_soc_bus_sel = main_cpu_dbus_sel;
assign main_interface1_soc_bus_cyc = main_cpu_dbus_cyc;
assign main_interface1_soc_bus_stb = main_cpu_dbus_stb;
assign main_cpu_dbus_ack = main_interface1_soc_bus_ack;
assign main_interface1_soc_bus_we = main_cpu_dbus_we;
assign main_interface1_soc_bus_cti = main_cpu_dbus_cti;
assign main_interface1_soc_bus_bte = main_cpu_dbus_bte;
assign main_cpu_dbus_err = main_interface1_soc_bus_err;
assign main_rom_adr = main_rom_bus_adr[12:0];
assign main_rom_bus_dat_r = main_rom_dat_r;
always @(*) begin
main_sram_we <= 4'd0;
main_sram_we[0] <= (((main_sram_bus_cyc & main_sram_bus_stb) & main_sram_bus_we) & main_sram_bus_sel[0]);
main_sram_we[1] <= (((main_sram_bus_cyc & main_sram_bus_stb) & main_sram_bus_we) & main_sram_bus_sel[1]);
main_sram_we[2] <= (((main_sram_bus_cyc & main_sram_bus_stb) & main_sram_bus_we) & main_sram_bus_sel[2]);
main_sram_we[3] <= (((main_sram_bus_cyc & main_sram_bus_stb) & main_sram_bus_we) & main_sram_bus_sel[3]);
end
assign main_sram_adr = main_sram_bus_adr[12:0];
assign main_sram_bus_dat_r = main_sram_dat_r;
assign main_sram_dat_w = main_sram_bus_dat_w;
assign main_uart_tx_fifo_sink_valid = main_uart_rxtx_re;
assign main_uart_tx_fifo_sink_payload_data = main_uart_rxtx_r;
assign main_uart_txfull_status = (~main_uart_tx_fifo_sink_ready);
assign main_uart_phy_sink_valid = main_uart_tx_fifo_source_valid;
assign main_uart_tx_fifo_source_ready = main_uart_phy_sink_ready;
assign main_uart_phy_sink_first = main_uart_tx_fifo_source_first;
assign main_uart_phy_sink_last = main_uart_tx_fifo_source_last;
assign main_uart_phy_sink_payload_data = main_uart_tx_fifo_source_payload_data;
assign main_uart_tx_trigger = (~main_uart_tx_fifo_sink_ready);
assign main_uart_rx_fifo_sink_valid = main_uart_phy_source_valid;
assign main_uart_phy_source_ready = main_uart_rx_fifo_sink_ready;
assign main_uart_rx_fifo_sink_first = main_uart_phy_source_first;
assign main_uart_rx_fifo_sink_last = main_uart_phy_source_last;
assign main_uart_rx_fifo_sink_payload_data = main_uart_phy_source_payload_data;
assign main_uart_rxempty_status = (~main_uart_rx_fifo_source_valid);
assign main_uart_rxtx_w = main_uart_rx_fifo_source_payload_data;
assign main_uart_rx_fifo_source_ready = main_uart_rx_clear;
assign main_uart_rx_trigger = (~main_uart_rx_fifo_source_valid);
always @(*) begin
main_uart_tx_clear <= 1'd0;
if ((main_uart_eventmanager_pending_re & main_uart_eventmanager_pending_r[0])) begin
main_uart_tx_clear <= 1'd1;
end
end
always @(*) begin
main_uart_eventmanager_status_w <= 2'd0;
main_uart_eventmanager_status_w[0] <= main_uart_tx_status;
main_uart_eventmanager_status_w[1] <= main_uart_rx_status;
end
always @(*) begin
main_uart_rx_clear <= 1'd0;
if ((main_uart_eventmanager_pending_re & main_uart_eventmanager_pending_r[1])) begin
main_uart_rx_clear <= 1'd1;
end
end
always @(*) begin
main_uart_eventmanager_pending_w <= 2'd0;
main_uart_eventmanager_pending_w[0] <= main_uart_tx_pending;
main_uart_eventmanager_pending_w[1] <= main_uart_rx_pending;
end
assign main_uart_irq = ((main_uart_eventmanager_pending_w[0] & main_uart_eventmanager_storage[0]) | (main_uart_eventmanager_pending_w[1] & main_uart_eventmanager_storage[1]));
assign main_uart_tx_status = main_uart_tx_trigger;
assign main_uart_rx_status = main_uart_rx_trigger;
assign main_uart_tx_fifo_syncfifo_din = {main_uart_tx_fifo_fifo_in_last, main_uart_tx_fifo_fifo_in_first, main_uart_tx_fifo_fifo_in_payload_data};
assign {main_uart_tx_fifo_fifo_out_last, main_uart_tx_fifo_fifo_out_first, main_uart_tx_fifo_fifo_out_payload_data} = main_uart_tx_fifo_syncfifo_dout;
assign main_uart_tx_fifo_sink_ready = main_uart_tx_fifo_syncfifo_writable;
assign main_uart_tx_fifo_syncfifo_we = main_uart_tx_fifo_sink_valid;
assign main_uart_tx_fifo_fifo_in_first = main_uart_tx_fifo_sink_first;
assign main_uart_tx_fifo_fifo_in_last = main_uart_tx_fifo_sink_last;
assign main_uart_tx_fifo_fifo_in_payload_data = main_uart_tx_fifo_sink_payload_data;
assign main_uart_tx_fifo_source_valid = main_uart_tx_fifo_readable;
assign main_uart_tx_fifo_source_first = main_uart_tx_fifo_fifo_out_first;
assign main_uart_tx_fifo_source_last = main_uart_tx_fifo_fifo_out_last;
assign main_uart_tx_fifo_source_payload_data = main_uart_tx_fifo_fifo_out_payload_data;
assign main_uart_tx_fifo_re = main_uart_tx_fifo_source_ready;
assign main_uart_tx_fifo_syncfifo_re = (main_uart_tx_fifo_syncfifo_readable & ((~main_uart_tx_fifo_readable) | main_uart_tx_fifo_re));
assign main_uart_tx_fifo_level1 = (main_uart_tx_fifo_level0 + main_uart_tx_fifo_readable);
always @(*) begin
main_uart_tx_fifo_wrport_adr <= 4'd0;
if (main_uart_tx_fifo_replace) begin
main_uart_tx_fifo_wrport_adr <= (main_uart_tx_fifo_produce - 1'd1);
end else begin
main_uart_tx_fifo_wrport_adr <= main_uart_tx_fifo_produce;
end
end
assign main_uart_tx_fifo_wrport_dat_w = main_uart_tx_fifo_syncfifo_din;
assign main_uart_tx_fifo_wrport_we = (main_uart_tx_fifo_syncfifo_we & (main_uart_tx_fifo_syncfifo_writable | main_uart_tx_fifo_replace));
assign main_uart_tx_fifo_do_read = (main_uart_tx_fifo_syncfifo_readable & main_uart_tx_fifo_syncfifo_re);
assign main_uart_tx_fifo_rdport_adr = main_uart_tx_fifo_consume;
assign main_uart_tx_fifo_syncfifo_dout = main_uart_tx_fifo_rdport_dat_r;
assign main_uart_tx_fifo_rdport_re = main_uart_tx_fifo_do_read;
assign main_uart_tx_fifo_syncfifo_writable = (main_uart_tx_fifo_level0 != 5'd16);
assign main_uart_tx_fifo_syncfifo_readable = (main_uart_tx_fifo_level0 != 1'd0);
assign main_uart_rx_fifo_syncfifo_din = {main_uart_rx_fifo_fifo_in_last, main_uart_rx_fifo_fifo_in_first, main_uart_rx_fifo_fifo_in_payload_data};
assign {main_uart_rx_fifo_fifo_out_last, main_uart_rx_fifo_fifo_out_first, main_uart_rx_fifo_fifo_out_payload_data} = main_uart_rx_fifo_syncfifo_dout;
assign main_uart_rx_fifo_sink_ready = main_uart_rx_fifo_syncfifo_writable;
assign main_uart_rx_fifo_syncfifo_we = main_uart_rx_fifo_sink_valid;
assign main_uart_rx_fifo_fifo_in_first = main_uart_rx_fifo_sink_first;
assign main_uart_rx_fifo_fifo_in_last = main_uart_rx_fifo_sink_last;
assign main_uart_rx_fifo_fifo_in_payload_data = main_uart_rx_fifo_sink_payload_data;
assign main_uart_rx_fifo_source_valid = main_uart_rx_fifo_readable;
assign main_uart_rx_fifo_source_first = main_uart_rx_fifo_fifo_out_first;
assign main_uart_rx_fifo_source_last = main_uart_rx_fifo_fifo_out_last;
assign main_uart_rx_fifo_source_payload_data = main_uart_rx_fifo_fifo_out_payload_data;
assign main_uart_rx_fifo_re = main_uart_rx_fifo_source_ready;
assign main_uart_rx_fifo_syncfifo_re = (main_uart_rx_fifo_syncfifo_readable & ((~main_uart_rx_fifo_readable) | main_uart_rx_fifo_re));
assign main_uart_rx_fifo_level1 = (main_uart_rx_fifo_level0 + main_uart_rx_fifo_readable);
always @(*) begin
main_uart_rx_fifo_wrport_adr <= 4'd0;
if (main_uart_rx_fifo_replace) begin
main_uart_rx_fifo_wrport_adr <= (main_uart_rx_fifo_produce - 1'd1);
end else begin
main_uart_rx_fifo_wrport_adr <= main_uart_rx_fifo_produce;
end
end
assign main_uart_rx_fifo_wrport_dat_w = main_uart_rx_fifo_syncfifo_din;
assign main_uart_rx_fifo_wrport_we = (main_uart_rx_fifo_syncfifo_we & (main_uart_rx_fifo_syncfifo_writable | main_uart_rx_fifo_replace));
assign main_uart_rx_fifo_do_read = (main_uart_rx_fifo_syncfifo_readable & main_uart_rx_fifo_syncfifo_re);
assign main_uart_rx_fifo_rdport_adr = main_uart_rx_fifo_consume;
assign main_uart_rx_fifo_syncfifo_dout = main_uart_rx_fifo_rdport_dat_r;
assign main_uart_rx_fifo_rdport_re = main_uart_rx_fifo_do_read;
assign main_uart_rx_fifo_syncfifo_writable = (main_uart_rx_fifo_level0 != 5'd16);
assign main_uart_rx_fifo_syncfifo_readable = (main_uart_rx_fifo_level0 != 1'd0);
assign main_timer0_zero_trigger = (main_timer0_value != 1'd0);
assign main_timer0_eventmanager_status_w = main_timer0_zero_status;
always @(*) begin
main_timer0_zero_clear <= 1'd0;
if ((main_timer0_eventmanager_pending_re & main_timer0_eventmanager_pending_r)) begin
main_timer0_zero_clear <= 1'd1;
end
end
assign main_timer0_eventmanager_pending_w = main_timer0_zero_pending;
assign main_timer0_irq = (main_timer0_eventmanager_pending_w & main_timer0_eventmanager_storage);
assign main_timer0_zero_status = main_timer0_zero_trigger;
assign main_interface_dat_w = main_bus_wishbone_dat_w;
assign main_bus_wishbone_dat_r = main_interface_dat_r;
always @(*) begin
builder_wb2csr_next_state <= 1'd0;
main_interface_adr <= 14'd0;
main_interface_we <= 1'd0;
main_bus_wishbone_ack <= 1'd0;
builder_wb2csr_next_state <= builder_wb2csr_state;
case (builder_wb2csr_state)
1'd1: begin
main_bus_wishbone_ack <= 1'd1;
builder_wb2csr_next_state <= 1'd0;
end
default: begin
if ((main_bus_wishbone_cyc & main_bus_wishbone_stb)) begin
main_interface_adr <= main_bus_wishbone_adr;
main_interface_we <= main_bus_wishbone_we;
builder_wb2csr_next_state <= 1'd1;
end
end
endcase
end
assign main_reset = (~cpu_reset);
assign main_clkin = main_pll_clkin;
assign sys_clk = main_clkout_buf0;
assign sys4x_clk = main_clkout_buf1;
assign sys4x_dqs_clk = main_clkout_buf2;
assign clk200_clk = main_clkout_buf3;
always @(*) begin
main_a7ddrphy_dqs_serdes_pattern <= 8'd85;
if ((main_a7ddrphy_dqs_preamble | main_a7ddrphy_dqs_postamble)) begin
main_a7ddrphy_dqs_serdes_pattern <= 1'd0;
end else begin
main_a7ddrphy_dqs_serdes_pattern <= 7'd85;
end
end
assign main_a7ddrphy_bitslip0_i = main_a7ddrphy_dq_i_data0;
assign main_a7ddrphy_bitslip1_i = main_a7ddrphy_dq_i_data1;
assign main_a7ddrphy_bitslip2_i = main_a7ddrphy_dq_i_data2;
assign main_a7ddrphy_bitslip3_i = main_a7ddrphy_dq_i_data3;
assign main_a7ddrphy_bitslip4_i = main_a7ddrphy_dq_i_data4;
assign main_a7ddrphy_bitslip5_i = main_a7ddrphy_dq_i_data5;
assign main_a7ddrphy_bitslip6_i = main_a7ddrphy_dq_i_data6;
assign main_a7ddrphy_bitslip7_i = main_a7ddrphy_dq_i_data7;
assign main_a7ddrphy_bitslip8_i = main_a7ddrphy_dq_i_data8;
assign main_a7ddrphy_bitslip9_i = main_a7ddrphy_dq_i_data9;
assign main_a7ddrphy_bitslip10_i = main_a7ddrphy_dq_i_data10;
assign main_a7ddrphy_bitslip11_i = main_a7ddrphy_dq_i_data11;
assign main_a7ddrphy_bitslip12_i = main_a7ddrphy_dq_i_data12;
assign main_a7ddrphy_bitslip13_i = main_a7ddrphy_dq_i_data13;
assign main_a7ddrphy_bitslip14_i = main_a7ddrphy_dq_i_data14;
assign main_a7ddrphy_bitslip15_i = main_a7ddrphy_dq_i_data15;
always @(*) begin
main_a7ddrphy_dfi_p0_rddata <= 32'd0;
main_a7ddrphy_dfi_p0_rddata[0] <= main_a7ddrphy_bitslip0_o[0];
main_a7ddrphy_dfi_p0_rddata[16] <= main_a7ddrphy_bitslip0_o[1];
main_a7ddrphy_dfi_p0_rddata[1] <= main_a7ddrphy_bitslip1_o[0];
main_a7ddrphy_dfi_p0_rddata[17] <= main_a7ddrphy_bitslip1_o[1];
main_a7ddrphy_dfi_p0_rddata[2] <= main_a7ddrphy_bitslip2_o[0];
main_a7ddrphy_dfi_p0_rddata[18] <= main_a7ddrphy_bitslip2_o[1];
main_a7ddrphy_dfi_p0_rddata[3] <= main_a7ddrphy_bitslip3_o[0];
main_a7ddrphy_dfi_p0_rddata[19] <= main_a7ddrphy_bitslip3_o[1];
main_a7ddrphy_dfi_p0_rddata[4] <= main_a7ddrphy_bitslip4_o[0];
main_a7ddrphy_dfi_p0_rddata[20] <= main_a7ddrphy_bitslip4_o[1];
main_a7ddrphy_dfi_p0_rddata[5] <= main_a7ddrphy_bitslip5_o[0];
main_a7ddrphy_dfi_p0_rddata[21] <= main_a7ddrphy_bitslip5_o[1];
main_a7ddrphy_dfi_p0_rddata[6] <= main_a7ddrphy_bitslip6_o[0];
main_a7ddrphy_dfi_p0_rddata[22] <= main_a7ddrphy_bitslip6_o[1];
main_a7ddrphy_dfi_p0_rddata[7] <= main_a7ddrphy_bitslip7_o[0];
main_a7ddrphy_dfi_p0_rddata[23] <= main_a7ddrphy_bitslip7_o[1];
main_a7ddrphy_dfi_p0_rddata[8] <= main_a7ddrphy_bitslip8_o[0];
main_a7ddrphy_dfi_p0_rddata[24] <= main_a7ddrphy_bitslip8_o[1];
main_a7ddrphy_dfi_p0_rddata[9] <= main_a7ddrphy_bitslip9_o[0];
main_a7ddrphy_dfi_p0_rddata[25] <= main_a7ddrphy_bitslip9_o[1];
main_a7ddrphy_dfi_p0_rddata[10] <= main_a7ddrphy_bitslip10_o[0];
main_a7ddrphy_dfi_p0_rddata[26] <= main_a7ddrphy_bitslip10_o[1];
main_a7ddrphy_dfi_p0_rddata[11] <= main_a7ddrphy_bitslip11_o[0];
main_a7ddrphy_dfi_p0_rddata[27] <= main_a7ddrphy_bitslip11_o[1];
main_a7ddrphy_dfi_p0_rddata[12] <= main_a7ddrphy_bitslip12_o[0];
main_a7ddrphy_dfi_p0_rddata[28] <= main_a7ddrphy_bitslip12_o[1];
main_a7ddrphy_dfi_p0_rddata[13] <= main_a7ddrphy_bitslip13_o[0];
main_a7ddrphy_dfi_p0_rddata[29] <= main_a7ddrphy_bitslip13_o[1];
main_a7ddrphy_dfi_p0_rddata[14] <= main_a7ddrphy_bitslip14_o[0];
main_a7ddrphy_dfi_p0_rddata[30] <= main_a7ddrphy_bitslip14_o[1];
main_a7ddrphy_dfi_p0_rddata[15] <= main_a7ddrphy_bitslip15_o[0];
main_a7ddrphy_dfi_p0_rddata[31] <= main_a7ddrphy_bitslip15_o[1];
end
always @(*) begin
main_a7ddrphy_dfi_p1_rddata <= 32'd0;
main_a7ddrphy_dfi_p1_rddata[0] <= main_a7ddrphy_bitslip0_o[2];
main_a7ddrphy_dfi_p1_rddata[16] <= main_a7ddrphy_bitslip0_o[3];
main_a7ddrphy_dfi_p1_rddata[1] <= main_a7ddrphy_bitslip1_o[2];
main_a7ddrphy_dfi_p1_rddata[17] <= main_a7ddrphy_bitslip1_o[3];
main_a7ddrphy_dfi_p1_rddata[2] <= main_a7ddrphy_bitslip2_o[2];
main_a7ddrphy_dfi_p1_rddata[18] <= main_a7ddrphy_bitslip2_o[3];
main_a7ddrphy_dfi_p1_rddata[3] <= main_a7ddrphy_bitslip3_o[2];
main_a7ddrphy_dfi_p1_rddata[19] <= main_a7ddrphy_bitslip3_o[3];
main_a7ddrphy_dfi_p1_rddata[4] <= main_a7ddrphy_bitslip4_o[2];
main_a7ddrphy_dfi_p1_rddata[20] <= main_a7ddrphy_bitslip4_o[3];
main_a7ddrphy_dfi_p1_rddata[5] <= main_a7ddrphy_bitslip5_o[2];
main_a7ddrphy_dfi_p1_rddata[21] <= main_a7ddrphy_bitslip5_o[3];
main_a7ddrphy_dfi_p1_rddata[6] <= main_a7ddrphy_bitslip6_o[2];
main_a7ddrphy_dfi_p1_rddata[22] <= main_a7ddrphy_bitslip6_o[3];
main_a7ddrphy_dfi_p1_rddata[7] <= main_a7ddrphy_bitslip7_o[2];
main_a7ddrphy_dfi_p1_rddata[23] <= main_a7ddrphy_bitslip7_o[3];
main_a7ddrphy_dfi_p1_rddata[8] <= main_a7ddrphy_bitslip8_o[2];
main_a7ddrphy_dfi_p1_rddata[24] <= main_a7ddrphy_bitslip8_o[3];
main_a7ddrphy_dfi_p1_rddata[9] <= main_a7ddrphy_bitslip9_o[2];
main_a7ddrphy_dfi_p1_rddata[25] <= main_a7ddrphy_bitslip9_o[3];
main_a7ddrphy_dfi_p1_rddata[10] <= main_a7ddrphy_bitslip10_o[2];
main_a7ddrphy_dfi_p1_rddata[26] <= main_a7ddrphy_bitslip10_o[3];
main_a7ddrphy_dfi_p1_rddata[11] <= main_a7ddrphy_bitslip11_o[2];
main_a7ddrphy_dfi_p1_rddata[27] <= main_a7ddrphy_bitslip11_o[3];
main_a7ddrphy_dfi_p1_rddata[12] <= main_a7ddrphy_bitslip12_o[2];
main_a7ddrphy_dfi_p1_rddata[28] <= main_a7ddrphy_bitslip12_o[3];
main_a7ddrphy_dfi_p1_rddata[13] <= main_a7ddrphy_bitslip13_o[2];
main_a7ddrphy_dfi_p1_rddata[29] <= main_a7ddrphy_bitslip13_o[3];
main_a7ddrphy_dfi_p1_rddata[14] <= main_a7ddrphy_bitslip14_o[2];
main_a7ddrphy_dfi_p1_rddata[30] <= main_a7ddrphy_bitslip14_o[3];
main_a7ddrphy_dfi_p1_rddata[15] <= main_a7ddrphy_bitslip15_o[2];
main_a7ddrphy_dfi_p1_rddata[31] <= main_a7ddrphy_bitslip15_o[3];
end
always @(*) begin
main_a7ddrphy_dfi_p2_rddata <= 32'd0;
main_a7ddrphy_dfi_p2_rddata[0] <= main_a7ddrphy_bitslip0_o[4];
main_a7ddrphy_dfi_p2_rddata[16] <= main_a7ddrphy_bitslip0_o[5];
main_a7ddrphy_dfi_p2_rddata[1] <= main_a7ddrphy_bitslip1_o[4];
main_a7ddrphy_dfi_p2_rddata[17] <= main_a7ddrphy_bitslip1_o[5];
main_a7ddrphy_dfi_p2_rddata[2] <= main_a7ddrphy_bitslip2_o[4];
main_a7ddrphy_dfi_p2_rddata[18] <= main_a7ddrphy_bitslip2_o[5];
main_a7ddrphy_dfi_p2_rddata[3] <= main_a7ddrphy_bitslip3_o[4];
main_a7ddrphy_dfi_p2_rddata[19] <= main_a7ddrphy_bitslip3_o[5];
main_a7ddrphy_dfi_p2_rddata[4] <= main_a7ddrphy_bitslip4_o[4];
main_a7ddrphy_dfi_p2_rddata[20] <= main_a7ddrphy_bitslip4_o[5];
main_a7ddrphy_dfi_p2_rddata[5] <= main_a7ddrphy_bitslip5_o[4];
main_a7ddrphy_dfi_p2_rddata[21] <= main_a7ddrphy_bitslip5_o[5];
main_a7ddrphy_dfi_p2_rddata[6] <= main_a7ddrphy_bitslip6_o[4];
main_a7ddrphy_dfi_p2_rddata[22] <= main_a7ddrphy_bitslip6_o[5];
main_a7ddrphy_dfi_p2_rddata[7] <= main_a7ddrphy_bitslip7_o[4];
main_a7ddrphy_dfi_p2_rddata[23] <= main_a7ddrphy_bitslip7_o[5];
main_a7ddrphy_dfi_p2_rddata[8] <= main_a7ddrphy_bitslip8_o[4];
main_a7ddrphy_dfi_p2_rddata[24] <= main_a7ddrphy_bitslip8_o[5];
main_a7ddrphy_dfi_p2_rddata[9] <= main_a7ddrphy_bitslip9_o[4];
main_a7ddrphy_dfi_p2_rddata[25] <= main_a7ddrphy_bitslip9_o[5];
main_a7ddrphy_dfi_p2_rddata[10] <= main_a7ddrphy_bitslip10_o[4];
main_a7ddrphy_dfi_p2_rddata[26] <= main_a7ddrphy_bitslip10_o[5];
main_a7ddrphy_dfi_p2_rddata[11] <= main_a7ddrphy_bitslip11_o[4];
main_a7ddrphy_dfi_p2_rddata[27] <= main_a7ddrphy_bitslip11_o[5];
main_a7ddrphy_dfi_p2_rddata[12] <= main_a7ddrphy_bitslip12_o[4];
main_a7ddrphy_dfi_p2_rddata[28] <= main_a7ddrphy_bitslip12_o[5];
main_a7ddrphy_dfi_p2_rddata[13] <= main_a7ddrphy_bitslip13_o[4];
main_a7ddrphy_dfi_p2_rddata[29] <= main_a7ddrphy_bitslip13_o[5];
main_a7ddrphy_dfi_p2_rddata[14] <= main_a7ddrphy_bitslip14_o[4];
main_a7ddrphy_dfi_p2_rddata[30] <= main_a7ddrphy_bitslip14_o[5];
main_a7ddrphy_dfi_p2_rddata[15] <= main_a7ddrphy_bitslip15_o[4];
main_a7ddrphy_dfi_p2_rddata[31] <= main_a7ddrphy_bitslip15_o[5];
end
always @(*) begin
main_a7ddrphy_dfi_p3_rddata <= 32'd0;
main_a7ddrphy_dfi_p3_rddata[0] <= main_a7ddrphy_bitslip0_o[6];
main_a7ddrphy_dfi_p3_rddata[16] <= main_a7ddrphy_bitslip0_o[7];
main_a7ddrphy_dfi_p3_rddata[1] <= main_a7ddrphy_bitslip1_o[6];
main_a7ddrphy_dfi_p3_rddata[17] <= main_a7ddrphy_bitslip1_o[7];
main_a7ddrphy_dfi_p3_rddata[2] <= main_a7ddrphy_bitslip2_o[6];
main_a7ddrphy_dfi_p3_rddata[18] <= main_a7ddrphy_bitslip2_o[7];
main_a7ddrphy_dfi_p3_rddata[3] <= main_a7ddrphy_bitslip3_o[6];
main_a7ddrphy_dfi_p3_rddata[19] <= main_a7ddrphy_bitslip3_o[7];
main_a7ddrphy_dfi_p3_rddata[4] <= main_a7ddrphy_bitslip4_o[6];
main_a7ddrphy_dfi_p3_rddata[20] <= main_a7ddrphy_bitslip4_o[7];
main_a7ddrphy_dfi_p3_rddata[5] <= main_a7ddrphy_bitslip5_o[6];
main_a7ddrphy_dfi_p3_rddata[21] <= main_a7ddrphy_bitslip5_o[7];
main_a7ddrphy_dfi_p3_rddata[6] <= main_a7ddrphy_bitslip6_o[6];
main_a7ddrphy_dfi_p3_rddata[22] <= main_a7ddrphy_bitslip6_o[7];
main_a7ddrphy_dfi_p3_rddata[7] <= main_a7ddrphy_bitslip7_o[6];
main_a7ddrphy_dfi_p3_rddata[23] <= main_a7ddrphy_bitslip7_o[7];
main_a7ddrphy_dfi_p3_rddata[8] <= main_a7ddrphy_bitslip8_o[6];
main_a7ddrphy_dfi_p3_rddata[24] <= main_a7ddrphy_bitslip8_o[7];
main_a7ddrphy_dfi_p3_rddata[9] <= main_a7ddrphy_bitslip9_o[6];
main_a7ddrphy_dfi_p3_rddata[25] <= main_a7ddrphy_bitslip9_o[7];
main_a7ddrphy_dfi_p3_rddata[10] <= main_a7ddrphy_bitslip10_o[6];
main_a7ddrphy_dfi_p3_rddata[26] <= main_a7ddrphy_bitslip10_o[7];
main_a7ddrphy_dfi_p3_rddata[11] <= main_a7ddrphy_bitslip11_o[6];
main_a7ddrphy_dfi_p3_rddata[27] <= main_a7ddrphy_bitslip11_o[7];
main_a7ddrphy_dfi_p3_rddata[12] <= main_a7ddrphy_bitslip12_o[6];
main_a7ddrphy_dfi_p3_rddata[28] <= main_a7ddrphy_bitslip12_o[7];
main_a7ddrphy_dfi_p3_rddata[13] <= main_a7ddrphy_bitslip13_o[6];
main_a7ddrphy_dfi_p3_rddata[29] <= main_a7ddrphy_bitslip13_o[7];
main_a7ddrphy_dfi_p3_rddata[14] <= main_a7ddrphy_bitslip14_o[6];
main_a7ddrphy_dfi_p3_rddata[30] <= main_a7ddrphy_bitslip14_o[7];
main_a7ddrphy_dfi_p3_rddata[15] <= main_a7ddrphy_bitslip15_o[6];
main_a7ddrphy_dfi_p3_rddata[31] <= main_a7ddrphy_bitslip15_o[7];
end
assign main_a7ddrphy_oe = ((main_a7ddrphy_last_wrdata_en[1] | main_a7ddrphy_last_wrdata_en[2]) | main_a7ddrphy_last_wrdata_en[3]);
assign main_a7ddrphy_dqs_preamble = (main_a7ddrphy_last_wrdata_en[1] & (~main_a7ddrphy_last_wrdata_en[2]));
assign main_a7ddrphy_dqs_postamble = (main_a7ddrphy_last_wrdata_en[3] & (~main_a7ddrphy_last_wrdata_en[2]));
assign main_a7ddrphy_dfi_p0_address = main_sdram_master_p0_address;
assign main_a7ddrphy_dfi_p0_bank = main_sdram_master_p0_bank;
assign main_a7ddrphy_dfi_p0_cas_n = main_sdram_master_p0_cas_n;
assign main_a7ddrphy_dfi_p0_cs_n = main_sdram_master_p0_cs_n;
assign main_a7ddrphy_dfi_p0_ras_n = main_sdram_master_p0_ras_n;
assign main_a7ddrphy_dfi_p0_we_n = main_sdram_master_p0_we_n;
assign main_a7ddrphy_dfi_p0_cke = main_sdram_master_p0_cke;
assign main_a7ddrphy_dfi_p0_odt = main_sdram_master_p0_odt;
assign main_a7ddrphy_dfi_p0_reset_n = main_sdram_master_p0_reset_n;
assign main_a7ddrphy_dfi_p0_act_n = main_sdram_master_p0_act_n;
assign main_a7ddrphy_dfi_p0_wrdata = main_sdram_master_p0_wrdata;
assign main_a7ddrphy_dfi_p0_wrdata_en = main_sdram_master_p0_wrdata_en;
assign main_a7ddrphy_dfi_p0_wrdata_mask = main_sdram_master_p0_wrdata_mask;
assign main_a7ddrphy_dfi_p0_rddata_en = main_sdram_master_p0_rddata_en;
assign main_sdram_master_p0_rddata = main_a7ddrphy_dfi_p0_rddata;
assign main_sdram_master_p0_rddata_valid = main_a7ddrphy_dfi_p0_rddata_valid;
assign main_a7ddrphy_dfi_p1_address = main_sdram_master_p1_address;
assign main_a7ddrphy_dfi_p1_bank = main_sdram_master_p1_bank;
assign main_a7ddrphy_dfi_p1_cas_n = main_sdram_master_p1_cas_n;
assign main_a7ddrphy_dfi_p1_cs_n = main_sdram_master_p1_cs_n;
assign main_a7ddrphy_dfi_p1_ras_n = main_sdram_master_p1_ras_n;
assign main_a7ddrphy_dfi_p1_we_n = main_sdram_master_p1_we_n;
assign main_a7ddrphy_dfi_p1_cke = main_sdram_master_p1_cke;
assign main_a7ddrphy_dfi_p1_odt = main_sdram_master_p1_odt;
assign main_a7ddrphy_dfi_p1_reset_n = main_sdram_master_p1_reset_n;
assign main_a7ddrphy_dfi_p1_act_n = main_sdram_master_p1_act_n;
assign main_a7ddrphy_dfi_p1_wrdata = main_sdram_master_p1_wrdata;
assign main_a7ddrphy_dfi_p1_wrdata_en = main_sdram_master_p1_wrdata_en;
assign main_a7ddrphy_dfi_p1_wrdata_mask = main_sdram_master_p1_wrdata_mask;
assign main_a7ddrphy_dfi_p1_rddata_en = main_sdram_master_p1_rddata_en;
assign main_sdram_master_p1_rddata = main_a7ddrphy_dfi_p1_rddata;
assign main_sdram_master_p1_rddata_valid = main_a7ddrphy_dfi_p1_rddata_valid;
assign main_a7ddrphy_dfi_p2_address = main_sdram_master_p2_address;
assign main_a7ddrphy_dfi_p2_bank = main_sdram_master_p2_bank;
assign main_a7ddrphy_dfi_p2_cas_n = main_sdram_master_p2_cas_n;
assign main_a7ddrphy_dfi_p2_cs_n = main_sdram_master_p2_cs_n;
assign main_a7ddrphy_dfi_p2_ras_n = main_sdram_master_p2_ras_n;
assign main_a7ddrphy_dfi_p2_we_n = main_sdram_master_p2_we_n;
assign main_a7ddrphy_dfi_p2_cke = main_sdram_master_p2_cke;
assign main_a7ddrphy_dfi_p2_odt = main_sdram_master_p2_odt;
assign main_a7ddrphy_dfi_p2_reset_n = main_sdram_master_p2_reset_n;
assign main_a7ddrphy_dfi_p2_act_n = main_sdram_master_p2_act_n;
assign main_a7ddrphy_dfi_p2_wrdata = main_sdram_master_p2_wrdata;
assign main_a7ddrphy_dfi_p2_wrdata_en = main_sdram_master_p2_wrdata_en;
assign main_a7ddrphy_dfi_p2_wrdata_mask = main_sdram_master_p2_wrdata_mask;
assign main_a7ddrphy_dfi_p2_rddata_en = main_sdram_master_p2_rddata_en;
assign main_sdram_master_p2_rddata = main_a7ddrphy_dfi_p2_rddata;
assign main_sdram_master_p2_rddata_valid = main_a7ddrphy_dfi_p2_rddata_valid;
assign main_a7ddrphy_dfi_p3_address = main_sdram_master_p3_address;
assign main_a7ddrphy_dfi_p3_bank = main_sdram_master_p3_bank;
assign main_a7ddrphy_dfi_p3_cas_n = main_sdram_master_p3_cas_n;
assign main_a7ddrphy_dfi_p3_cs_n = main_sdram_master_p3_cs_n;
assign main_a7ddrphy_dfi_p3_ras_n = main_sdram_master_p3_ras_n;
assign main_a7ddrphy_dfi_p3_we_n = main_sdram_master_p3_we_n;
assign main_a7ddrphy_dfi_p3_cke = main_sdram_master_p3_cke;
assign main_a7ddrphy_dfi_p3_odt = main_sdram_master_p3_odt;
assign main_a7ddrphy_dfi_p3_reset_n = main_sdram_master_p3_reset_n;
assign main_a7ddrphy_dfi_p3_act_n = main_sdram_master_p3_act_n;
assign main_a7ddrphy_dfi_p3_wrdata = main_sdram_master_p3_wrdata;
assign main_a7ddrphy_dfi_p3_wrdata_en = main_sdram_master_p3_wrdata_en;
assign main_a7ddrphy_dfi_p3_wrdata_mask = main_sdram_master_p3_wrdata_mask;
assign main_a7ddrphy_dfi_p3_rddata_en = main_sdram_master_p3_rddata_en;
assign main_sdram_master_p3_rddata = main_a7ddrphy_dfi_p3_rddata;
assign main_sdram_master_p3_rddata_valid = main_a7ddrphy_dfi_p3_rddata_valid;
assign main_sdram_slave_p0_address = main_sdram_dfi_p0_address;
assign main_sdram_slave_p0_bank = main_sdram_dfi_p0_bank;
assign main_sdram_slave_p0_cas_n = main_sdram_dfi_p0_cas_n;
assign main_sdram_slave_p0_cs_n = main_sdram_dfi_p0_cs_n;
assign main_sdram_slave_p0_ras_n = main_sdram_dfi_p0_ras_n;
assign main_sdram_slave_p0_we_n = main_sdram_dfi_p0_we_n;
assign main_sdram_slave_p0_cke = main_sdram_dfi_p0_cke;
assign main_sdram_slave_p0_odt = main_sdram_dfi_p0_odt;
assign main_sdram_slave_p0_reset_n = main_sdram_dfi_p0_reset_n;
assign main_sdram_slave_p0_act_n = main_sdram_dfi_p0_act_n;
assign main_sdram_slave_p0_wrdata = main_sdram_dfi_p0_wrdata;
assign main_sdram_slave_p0_wrdata_en = main_sdram_dfi_p0_wrdata_en;
assign main_sdram_slave_p0_wrdata_mask = main_sdram_dfi_p0_wrdata_mask;
assign main_sdram_slave_p0_rddata_en = main_sdram_dfi_p0_rddata_en;
assign main_sdram_dfi_p0_rddata = main_sdram_slave_p0_rddata;
assign main_sdram_dfi_p0_rddata_valid = main_sdram_slave_p0_rddata_valid;
assign main_sdram_slave_p1_address = main_sdram_dfi_p1_address;
assign main_sdram_slave_p1_bank = main_sdram_dfi_p1_bank;
assign main_sdram_slave_p1_cas_n = main_sdram_dfi_p1_cas_n;
assign main_sdram_slave_p1_cs_n = main_sdram_dfi_p1_cs_n;
assign main_sdram_slave_p1_ras_n = main_sdram_dfi_p1_ras_n;
assign main_sdram_slave_p1_we_n = main_sdram_dfi_p1_we_n;
assign main_sdram_slave_p1_cke = main_sdram_dfi_p1_cke;
assign main_sdram_slave_p1_odt = main_sdram_dfi_p1_odt;
assign main_sdram_slave_p1_reset_n = main_sdram_dfi_p1_reset_n;
assign main_sdram_slave_p1_act_n = main_sdram_dfi_p1_act_n;
assign main_sdram_slave_p1_wrdata = main_sdram_dfi_p1_wrdata;
assign main_sdram_slave_p1_wrdata_en = main_sdram_dfi_p1_wrdata_en;
assign main_sdram_slave_p1_wrdata_mask = main_sdram_dfi_p1_wrdata_mask;
assign main_sdram_slave_p1_rddata_en = main_sdram_dfi_p1_rddata_en;
assign main_sdram_dfi_p1_rddata = main_sdram_slave_p1_rddata;
assign main_sdram_dfi_p1_rddata_valid = main_sdram_slave_p1_rddata_valid;
assign main_sdram_slave_p2_address = main_sdram_dfi_p2_address;
assign main_sdram_slave_p2_bank = main_sdram_dfi_p2_bank;
assign main_sdram_slave_p2_cas_n = main_sdram_dfi_p2_cas_n;
assign main_sdram_slave_p2_cs_n = main_sdram_dfi_p2_cs_n;
assign main_sdram_slave_p2_ras_n = main_sdram_dfi_p2_ras_n;
assign main_sdram_slave_p2_we_n = main_sdram_dfi_p2_we_n;
assign main_sdram_slave_p2_cke = main_sdram_dfi_p2_cke;
assign main_sdram_slave_p2_odt = main_sdram_dfi_p2_odt;
assign main_sdram_slave_p2_reset_n = main_sdram_dfi_p2_reset_n;
assign main_sdram_slave_p2_act_n = main_sdram_dfi_p2_act_n;
assign main_sdram_slave_p2_wrdata = main_sdram_dfi_p2_wrdata;
assign main_sdram_slave_p2_wrdata_en = main_sdram_dfi_p2_wrdata_en;
assign main_sdram_slave_p2_wrdata_mask = main_sdram_dfi_p2_wrdata_mask;
assign main_sdram_slave_p2_rddata_en = main_sdram_dfi_p2_rddata_en;
assign main_sdram_dfi_p2_rddata = main_sdram_slave_p2_rddata;
assign main_sdram_dfi_p2_rddata_valid = main_sdram_slave_p2_rddata_valid;
assign main_sdram_slave_p3_address = main_sdram_dfi_p3_address;
assign main_sdram_slave_p3_bank = main_sdram_dfi_p3_bank;
assign main_sdram_slave_p3_cas_n = main_sdram_dfi_p3_cas_n;
assign main_sdram_slave_p3_cs_n = main_sdram_dfi_p3_cs_n;
assign main_sdram_slave_p3_ras_n = main_sdram_dfi_p3_ras_n;
assign main_sdram_slave_p3_we_n = main_sdram_dfi_p3_we_n;
assign main_sdram_slave_p3_cke = main_sdram_dfi_p3_cke;
assign main_sdram_slave_p3_odt = main_sdram_dfi_p3_odt;
assign main_sdram_slave_p3_reset_n = main_sdram_dfi_p3_reset_n;
assign main_sdram_slave_p3_act_n = main_sdram_dfi_p3_act_n;
assign main_sdram_slave_p3_wrdata = main_sdram_dfi_p3_wrdata;
assign main_sdram_slave_p3_wrdata_en = main_sdram_dfi_p3_wrdata_en;
assign main_sdram_slave_p3_wrdata_mask = main_sdram_dfi_p3_wrdata_mask;
assign main_sdram_slave_p3_rddata_en = main_sdram_dfi_p3_rddata_en;
assign main_sdram_dfi_p3_rddata = main_sdram_slave_p3_rddata;
assign main_sdram_dfi_p3_rddata_valid = main_sdram_slave_p3_rddata_valid;
always @(*) begin
main_sdram_slave_p2_rddata <= 32'd0;
main_sdram_slave_p2_rddata_valid <= 1'd0;
main_sdram_slave_p3_rddata <= 32'd0;
main_sdram_slave_p3_rddata_valid <= 1'd0;
main_sdram_inti_p0_rddata <= 32'd0;
main_sdram_inti_p0_rddata_valid <= 1'd0;
main_sdram_master_p0_address <= 14'd0;
main_sdram_master_p0_bank <= 3'd0;
main_sdram_master_p0_cas_n <= 1'd1;
main_sdram_master_p0_cs_n <= 1'd1;
main_sdram_master_p0_ras_n <= 1'd1;
main_sdram_master_p0_we_n <= 1'd1;
main_sdram_master_p0_cke <= 1'd0;
main_sdram_master_p0_odt <= 1'd0;
main_sdram_master_p0_reset_n <= 1'd0;
main_sdram_master_p0_act_n <= 1'd1;
main_sdram_master_p0_wrdata <= 32'd0;
main_sdram_inti_p1_rddata <= 32'd0;
main_sdram_master_p0_wrdata_en <= 1'd0;
main_sdram_inti_p1_rddata_valid <= 1'd0;
main_sdram_master_p0_wrdata_mask <= 4'd0;
main_sdram_master_p0_rddata_en <= 1'd0;
main_sdram_master_p1_address <= 14'd0;
main_sdram_master_p1_bank <= 3'd0;
main_sdram_master_p1_cas_n <= 1'd1;
main_sdram_master_p1_cs_n <= 1'd1;
main_sdram_master_p1_ras_n <= 1'd1;
main_sdram_master_p1_we_n <= 1'd1;
main_sdram_master_p1_cke <= 1'd0;
main_sdram_master_p1_odt <= 1'd0;
main_sdram_master_p1_reset_n <= 1'd0;
main_sdram_master_p1_act_n <= 1'd1;
main_sdram_master_p1_wrdata <= 32'd0;
main_sdram_inti_p2_rddata <= 32'd0;
main_sdram_master_p1_wrdata_en <= 1'd0;
main_sdram_inti_p2_rddata_valid <= 1'd0;
main_sdram_master_p1_wrdata_mask <= 4'd0;
main_sdram_master_p1_rddata_en <= 1'd0;
main_sdram_master_p2_address <= 14'd0;
main_sdram_master_p2_bank <= 3'd0;
main_sdram_master_p2_cas_n <= 1'd1;
main_sdram_master_p2_cs_n <= 1'd1;
main_sdram_master_p2_ras_n <= 1'd1;
main_sdram_master_p2_we_n <= 1'd1;
main_sdram_master_p2_cke <= 1'd0;
main_sdram_master_p2_odt <= 1'd0;
main_sdram_master_p2_reset_n <= 1'd0;
main_sdram_master_p2_act_n <= 1'd1;
main_sdram_master_p2_wrdata <= 32'd0;
main_sdram_inti_p3_rddata <= 32'd0;
main_sdram_master_p2_wrdata_en <= 1'd0;
main_sdram_inti_p3_rddata_valid <= 1'd0;
main_sdram_master_p2_wrdata_mask <= 4'd0;
main_sdram_master_p2_rddata_en <= 1'd0;
main_sdram_master_p3_address <= 14'd0;
main_sdram_master_p3_bank <= 3'd0;
main_sdram_master_p3_cas_n <= 1'd1;
main_sdram_master_p3_cs_n <= 1'd1;
main_sdram_master_p3_ras_n <= 1'd1;
main_sdram_master_p3_we_n <= 1'd1;
main_sdram_master_p3_cke <= 1'd0;
main_sdram_master_p3_odt <= 1'd0;
main_sdram_master_p3_reset_n <= 1'd0;
main_sdram_master_p3_act_n <= 1'd1;
main_sdram_master_p3_wrdata <= 32'd0;
main_sdram_master_p3_wrdata_en <= 1'd0;
main_sdram_master_p3_wrdata_mask <= 4'd0;
main_sdram_master_p3_rddata_en <= 1'd0;
main_sdram_slave_p0_rddata <= 32'd0;
main_sdram_slave_p0_rddata_valid <= 1'd0;
main_sdram_slave_p1_rddata <= 32'd0;
main_sdram_slave_p1_rddata_valid <= 1'd0;
if (main_sdram_storage[0]) begin
main_sdram_master_p0_address <= main_sdram_slave_p0_address;
main_sdram_master_p0_bank <= main_sdram_slave_p0_bank;
main_sdram_master_p0_cas_n <= main_sdram_slave_p0_cas_n;
main_sdram_master_p0_cs_n <= main_sdram_slave_p0_cs_n;
main_sdram_master_p0_ras_n <= main_sdram_slave_p0_ras_n;
main_sdram_master_p0_we_n <= main_sdram_slave_p0_we_n;
main_sdram_master_p0_cke <= main_sdram_slave_p0_cke;
main_sdram_master_p0_odt <= main_sdram_slave_p0_odt;
main_sdram_master_p0_reset_n <= main_sdram_slave_p0_reset_n;
main_sdram_master_p0_act_n <= main_sdram_slave_p0_act_n;
main_sdram_master_p0_wrdata <= main_sdram_slave_p0_wrdata;
main_sdram_master_p0_wrdata_en <= main_sdram_slave_p0_wrdata_en;
main_sdram_master_p0_wrdata_mask <= main_sdram_slave_p0_wrdata_mask;
main_sdram_master_p0_rddata_en <= main_sdram_slave_p0_rddata_en;
main_sdram_slave_p0_rddata <= main_sdram_master_p0_rddata;
main_sdram_slave_p0_rddata_valid <= main_sdram_master_p0_rddata_valid;
main_sdram_master_p1_address <= main_sdram_slave_p1_address;
main_sdram_master_p1_bank <= main_sdram_slave_p1_bank;
main_sdram_master_p1_cas_n <= main_sdram_slave_p1_cas_n;
main_sdram_master_p1_cs_n <= main_sdram_slave_p1_cs_n;
main_sdram_master_p1_ras_n <= main_sdram_slave_p1_ras_n;
main_sdram_master_p1_we_n <= main_sdram_slave_p1_we_n;
main_sdram_master_p1_cke <= main_sdram_slave_p1_cke;
main_sdram_master_p1_odt <= main_sdram_slave_p1_odt;
main_sdram_master_p1_reset_n <= main_sdram_slave_p1_reset_n;
main_sdram_master_p1_act_n <= main_sdram_slave_p1_act_n;
main_sdram_master_p1_wrdata <= main_sdram_slave_p1_wrdata;
main_sdram_master_p1_wrdata_en <= main_sdram_slave_p1_wrdata_en;
main_sdram_master_p1_wrdata_mask <= main_sdram_slave_p1_wrdata_mask;
main_sdram_master_p1_rddata_en <= main_sdram_slave_p1_rddata_en;
main_sdram_slave_p1_rddata <= main_sdram_master_p1_rddata;
main_sdram_slave_p1_rddata_valid <= main_sdram_master_p1_rddata_valid;
main_sdram_master_p2_address <= main_sdram_slave_p2_address;
main_sdram_master_p2_bank <= main_sdram_slave_p2_bank;
main_sdram_master_p2_cas_n <= main_sdram_slave_p2_cas_n;
main_sdram_master_p2_cs_n <= main_sdram_slave_p2_cs_n;
main_sdram_master_p2_ras_n <= main_sdram_slave_p2_ras_n;
main_sdram_master_p2_we_n <= main_sdram_slave_p2_we_n;
main_sdram_master_p2_cke <= main_sdram_slave_p2_cke;
main_sdram_master_p2_odt <= main_sdram_slave_p2_odt;
main_sdram_master_p2_reset_n <= main_sdram_slave_p2_reset_n;
main_sdram_master_p2_act_n <= main_sdram_slave_p2_act_n;
main_sdram_master_p2_wrdata <= main_sdram_slave_p2_wrdata;
main_sdram_master_p2_wrdata_en <= main_sdram_slave_p2_wrdata_en;
main_sdram_master_p2_wrdata_mask <= main_sdram_slave_p2_wrdata_mask;
main_sdram_master_p2_rddata_en <= main_sdram_slave_p2_rddata_en;
main_sdram_slave_p2_rddata <= main_sdram_master_p2_rddata;
main_sdram_slave_p2_rddata_valid <= main_sdram_master_p2_rddata_valid;
main_sdram_master_p3_address <= main_sdram_slave_p3_address;
main_sdram_master_p3_bank <= main_sdram_slave_p3_bank;
main_sdram_master_p3_cas_n <= main_sdram_slave_p3_cas_n;
main_sdram_master_p3_cs_n <= main_sdram_slave_p3_cs_n;
main_sdram_master_p3_ras_n <= main_sdram_slave_p3_ras_n;
main_sdram_master_p3_we_n <= main_sdram_slave_p3_we_n;
main_sdram_master_p3_cke <= main_sdram_slave_p3_cke;
main_sdram_master_p3_odt <= main_sdram_slave_p3_odt;
main_sdram_master_p3_reset_n <= main_sdram_slave_p3_reset_n;
main_sdram_master_p3_act_n <= main_sdram_slave_p3_act_n;
main_sdram_master_p3_wrdata <= main_sdram_slave_p3_wrdata;
main_sdram_master_p3_wrdata_en <= main_sdram_slave_p3_wrdata_en;
main_sdram_master_p3_wrdata_mask <= main_sdram_slave_p3_wrdata_mask;
main_sdram_master_p3_rddata_en <= main_sdram_slave_p3_rddata_en;
main_sdram_slave_p3_rddata <= main_sdram_master_p3_rddata;
main_sdram_slave_p3_rddata_valid <= main_sdram_master_p3_rddata_valid;
end else begin
main_sdram_master_p0_address <= main_sdram_inti_p0_address;
main_sdram_master_p0_bank <= main_sdram_inti_p0_bank;
main_sdram_master_p0_cas_n <= main_sdram_inti_p0_cas_n;
main_sdram_master_p0_cs_n <= main_sdram_inti_p0_cs_n;
main_sdram_master_p0_ras_n <= main_sdram_inti_p0_ras_n;
main_sdram_master_p0_we_n <= main_sdram_inti_p0_we_n;
main_sdram_master_p0_cke <= main_sdram_inti_p0_cke;
main_sdram_master_p0_odt <= main_sdram_inti_p0_odt;
main_sdram_master_p0_reset_n <= main_sdram_inti_p0_reset_n;
main_sdram_master_p0_act_n <= main_sdram_inti_p0_act_n;
main_sdram_master_p0_wrdata <= main_sdram_inti_p0_wrdata;
main_sdram_master_p0_wrdata_en <= main_sdram_inti_p0_wrdata_en;
main_sdram_master_p0_wrdata_mask <= main_sdram_inti_p0_wrdata_mask;
main_sdram_master_p0_rddata_en <= main_sdram_inti_p0_rddata_en;
main_sdram_inti_p0_rddata <= main_sdram_master_p0_rddata;
main_sdram_inti_p0_rddata_valid <= main_sdram_master_p0_rddata_valid;
main_sdram_master_p1_address <= main_sdram_inti_p1_address;
main_sdram_master_p1_bank <= main_sdram_inti_p1_bank;
main_sdram_master_p1_cas_n <= main_sdram_inti_p1_cas_n;
main_sdram_master_p1_cs_n <= main_sdram_inti_p1_cs_n;
main_sdram_master_p1_ras_n <= main_sdram_inti_p1_ras_n;
main_sdram_master_p1_we_n <= main_sdram_inti_p1_we_n;
main_sdram_master_p1_cke <= main_sdram_inti_p1_cke;
main_sdram_master_p1_odt <= main_sdram_inti_p1_odt;
main_sdram_master_p1_reset_n <= main_sdram_inti_p1_reset_n;
main_sdram_master_p1_act_n <= main_sdram_inti_p1_act_n;
main_sdram_master_p1_wrdata <= main_sdram_inti_p1_wrdata;
main_sdram_master_p1_wrdata_en <= main_sdram_inti_p1_wrdata_en;
main_sdram_master_p1_wrdata_mask <= main_sdram_inti_p1_wrdata_mask;
main_sdram_master_p1_rddata_en <= main_sdram_inti_p1_rddata_en;
main_sdram_inti_p1_rddata <= main_sdram_master_p1_rddata;
main_sdram_inti_p1_rddata_valid <= main_sdram_master_p1_rddata_valid;
main_sdram_master_p2_address <= main_sdram_inti_p2_address;
main_sdram_master_p2_bank <= main_sdram_inti_p2_bank;
main_sdram_master_p2_cas_n <= main_sdram_inti_p2_cas_n;
main_sdram_master_p2_cs_n <= main_sdram_inti_p2_cs_n;
main_sdram_master_p2_ras_n <= main_sdram_inti_p2_ras_n;
main_sdram_master_p2_we_n <= main_sdram_inti_p2_we_n;
main_sdram_master_p2_cke <= main_sdram_inti_p2_cke;
main_sdram_master_p2_odt <= main_sdram_inti_p2_odt;
main_sdram_master_p2_reset_n <= main_sdram_inti_p2_reset_n;
main_sdram_master_p2_act_n <= main_sdram_inti_p2_act_n;
main_sdram_master_p2_wrdata <= main_sdram_inti_p2_wrdata;
main_sdram_master_p2_wrdata_en <= main_sdram_inti_p2_wrdata_en;
main_sdram_master_p2_wrdata_mask <= main_sdram_inti_p2_wrdata_mask;
main_sdram_master_p2_rddata_en <= main_sdram_inti_p2_rddata_en;
main_sdram_inti_p2_rddata <= main_sdram_master_p2_rddata;
main_sdram_inti_p2_rddata_valid <= main_sdram_master_p2_rddata_valid;
main_sdram_master_p3_address <= main_sdram_inti_p3_address;
main_sdram_master_p3_bank <= main_sdram_inti_p3_bank;
main_sdram_master_p3_cas_n <= main_sdram_inti_p3_cas_n;
main_sdram_master_p3_cs_n <= main_sdram_inti_p3_cs_n;
main_sdram_master_p3_ras_n <= main_sdram_inti_p3_ras_n;
main_sdram_master_p3_we_n <= main_sdram_inti_p3_we_n;
main_sdram_master_p3_cke <= main_sdram_inti_p3_cke;
main_sdram_master_p3_odt <= main_sdram_inti_p3_odt;
main_sdram_master_p3_reset_n <= main_sdram_inti_p3_reset_n;
main_sdram_master_p3_act_n <= main_sdram_inti_p3_act_n;
main_sdram_master_p3_wrdata <= main_sdram_inti_p3_wrdata;
main_sdram_master_p3_wrdata_en <= main_sdram_inti_p3_wrdata_en;
main_sdram_master_p3_wrdata_mask <= main_sdram_inti_p3_wrdata_mask;
main_sdram_master_p3_rddata_en <= main_sdram_inti_p3_rddata_en;
main_sdram_inti_p3_rddata <= main_sdram_master_p3_rddata;
main_sdram_inti_p3_rddata_valid <= main_sdram_master_p3_rddata_valid;
end
end
assign main_sdram_inti_p0_cke = main_sdram_storage[1];
assign main_sdram_inti_p1_cke = main_sdram_storage[1];
assign main_sdram_inti_p2_cke = main_sdram_storage[1];
assign main_sdram_inti_p3_cke = main_sdram_storage[1];
assign main_sdram_inti_p0_odt = main_sdram_storage[2];
assign main_sdram_inti_p1_odt = main_sdram_storage[2];
assign main_sdram_inti_p2_odt = main_sdram_storage[2];
assign main_sdram_inti_p3_odt = main_sdram_storage[2];
assign main_sdram_inti_p0_reset_n = main_sdram_storage[3];
assign main_sdram_inti_p1_reset_n = main_sdram_storage[3];
assign main_sdram_inti_p2_reset_n = main_sdram_storage[3];
assign main_sdram_inti_p3_reset_n = main_sdram_storage[3];
always @(*) begin
main_sdram_inti_p0_cs_n <= 1'd1;
main_sdram_inti_p0_ras_n <= 1'd1;
main_sdram_inti_p0_we_n <= 1'd1;
main_sdram_inti_p0_cas_n <= 1'd1;
if (main_sdram_phaseinjector0_command_issue_re) begin
main_sdram_inti_p0_cs_n <= {1{(~main_sdram_phaseinjector0_command_storage[0])}};
main_sdram_inti_p0_we_n <= (~main_sdram_phaseinjector0_command_storage[1]);
main_sdram_inti_p0_cas_n <= (~main_sdram_phaseinjector0_command_storage[2]);
main_sdram_inti_p0_ras_n <= (~main_sdram_phaseinjector0_command_storage[3]);
end else begin
main_sdram_inti_p0_cs_n <= {1{1'd1}};
main_sdram_inti_p0_we_n <= 1'd1;
main_sdram_inti_p0_cas_n <= 1'd1;
main_sdram_inti_p0_ras_n <= 1'd1;
end
end
assign main_sdram_inti_p0_address = main_sdram_phaseinjector0_address_storage;
assign main_sdram_inti_p0_bank = main_sdram_phaseinjector0_baddress_storage;
assign main_sdram_inti_p0_wrdata_en = (main_sdram_phaseinjector0_command_issue_re & main_sdram_phaseinjector0_command_storage[4]);
assign main_sdram_inti_p0_rddata_en = (main_sdram_phaseinjector0_command_issue_re & main_sdram_phaseinjector0_command_storage[5]);
assign main_sdram_inti_p0_wrdata = main_sdram_phaseinjector0_wrdata_storage;
assign main_sdram_inti_p0_wrdata_mask = 1'd0;
always @(*) begin
main_sdram_inti_p1_cs_n <= 1'd1;
main_sdram_inti_p1_ras_n <= 1'd1;
main_sdram_inti_p1_we_n <= 1'd1;
main_sdram_inti_p1_cas_n <= 1'd1;
if (main_sdram_phaseinjector1_command_issue_re) begin
main_sdram_inti_p1_cs_n <= {1{(~main_sdram_phaseinjector1_command_storage[0])}};
main_sdram_inti_p1_we_n <= (~main_sdram_phaseinjector1_command_storage[1]);
main_sdram_inti_p1_cas_n <= (~main_sdram_phaseinjector1_command_storage[2]);
main_sdram_inti_p1_ras_n <= (~main_sdram_phaseinjector1_command_storage[3]);
end else begin
main_sdram_inti_p1_cs_n <= {1{1'd1}};
main_sdram_inti_p1_we_n <= 1'd1;
main_sdram_inti_p1_cas_n <= 1'd1;
main_sdram_inti_p1_ras_n <= 1'd1;
end
end
assign main_sdram_inti_p1_address = main_sdram_phaseinjector1_address_storage;
assign main_sdram_inti_p1_bank = main_sdram_phaseinjector1_baddress_storage;
assign main_sdram_inti_p1_wrdata_en = (main_sdram_phaseinjector1_command_issue_re & main_sdram_phaseinjector1_command_storage[4]);
assign main_sdram_inti_p1_rddata_en = (main_sdram_phaseinjector1_command_issue_re & main_sdram_phaseinjector1_command_storage[5]);
assign main_sdram_inti_p1_wrdata = main_sdram_phaseinjector1_wrdata_storage;
assign main_sdram_inti_p1_wrdata_mask = 1'd0;
always @(*) begin
main_sdram_inti_p2_cs_n <= 1'd1;
main_sdram_inti_p2_ras_n <= 1'd1;
main_sdram_inti_p2_we_n <= 1'd1;
main_sdram_inti_p2_cas_n <= 1'd1;
if (main_sdram_phaseinjector2_command_issue_re) begin
main_sdram_inti_p2_cs_n <= {1{(~main_sdram_phaseinjector2_command_storage[0])}};
main_sdram_inti_p2_we_n <= (~main_sdram_phaseinjector2_command_storage[1]);
main_sdram_inti_p2_cas_n <= (~main_sdram_phaseinjector2_command_storage[2]);
main_sdram_inti_p2_ras_n <= (~main_sdram_phaseinjector2_command_storage[3]);
end else begin
main_sdram_inti_p2_cs_n <= {1{1'd1}};
main_sdram_inti_p2_we_n <= 1'd1;
main_sdram_inti_p2_cas_n <= 1'd1;
main_sdram_inti_p2_ras_n <= 1'd1;
end
end
assign main_sdram_inti_p2_address = main_sdram_phaseinjector2_address_storage;
assign main_sdram_inti_p2_bank = main_sdram_phaseinjector2_baddress_storage;
assign main_sdram_inti_p2_wrdata_en = (main_sdram_phaseinjector2_command_issue_re & main_sdram_phaseinjector2_command_storage[4]);
assign main_sdram_inti_p2_rddata_en = (main_sdram_phaseinjector2_command_issue_re & main_sdram_phaseinjector2_command_storage[5]);
assign main_sdram_inti_p2_wrdata = main_sdram_phaseinjector2_wrdata_storage;
assign main_sdram_inti_p2_wrdata_mask = 1'd0;
always @(*) begin
main_sdram_inti_p3_cs_n <= 1'd1;
main_sdram_inti_p3_ras_n <= 1'd1;
main_sdram_inti_p3_we_n <= 1'd1;
main_sdram_inti_p3_cas_n <= 1'd1;
if (main_sdram_phaseinjector3_command_issue_re) begin
main_sdram_inti_p3_cs_n <= {1{(~main_sdram_phaseinjector3_command_storage[0])}};
main_sdram_inti_p3_we_n <= (~main_sdram_phaseinjector3_command_storage[1]);
main_sdram_inti_p3_cas_n <= (~main_sdram_phaseinjector3_command_storage[2]);
main_sdram_inti_p3_ras_n <= (~main_sdram_phaseinjector3_command_storage[3]);
end else begin
main_sdram_inti_p3_cs_n <= {1{1'd1}};
main_sdram_inti_p3_we_n <= 1'd1;
main_sdram_inti_p3_cas_n <= 1'd1;
main_sdram_inti_p3_ras_n <= 1'd1;
end
end
assign main_sdram_inti_p3_address = main_sdram_phaseinjector3_address_storage;
assign main_sdram_inti_p3_bank = main_sdram_phaseinjector3_baddress_storage;
assign main_sdram_inti_p3_wrdata_en = (main_sdram_phaseinjector3_command_issue_re & main_sdram_phaseinjector3_command_storage[4]);
assign main_sdram_inti_p3_rddata_en = (main_sdram_phaseinjector3_command_issue_re & main_sdram_phaseinjector3_command_storage[5]);
assign main_sdram_inti_p3_wrdata = main_sdram_phaseinjector3_wrdata_storage;
assign main_sdram_inti_p3_wrdata_mask = 1'd0;
assign main_sdram_bankmachine0_req_valid = main_sdram_interface_bank0_valid;
assign main_sdram_interface_bank0_ready = main_sdram_bankmachine0_req_ready;
assign main_sdram_bankmachine0_req_we = main_sdram_interface_bank0_we;
assign main_sdram_bankmachine0_req_addr = main_sdram_interface_bank0_addr;
assign main_sdram_interface_bank0_lock = main_sdram_bankmachine0_req_lock;
assign main_sdram_interface_bank0_wdata_ready = main_sdram_bankmachine0_req_wdata_ready;
assign main_sdram_interface_bank0_rdata_valid = main_sdram_bankmachine0_req_rdata_valid;
assign main_sdram_bankmachine1_req_valid = main_sdram_interface_bank1_valid;
assign main_sdram_interface_bank1_ready = main_sdram_bankmachine1_req_ready;
assign main_sdram_bankmachine1_req_we = main_sdram_interface_bank1_we;
assign main_sdram_bankmachine1_req_addr = main_sdram_interface_bank1_addr;
assign main_sdram_interface_bank1_lock = main_sdram_bankmachine1_req_lock;
assign main_sdram_interface_bank1_wdata_ready = main_sdram_bankmachine1_req_wdata_ready;
assign main_sdram_interface_bank1_rdata_valid = main_sdram_bankmachine1_req_rdata_valid;
assign main_sdram_bankmachine2_req_valid = main_sdram_interface_bank2_valid;
assign main_sdram_interface_bank2_ready = main_sdram_bankmachine2_req_ready;
assign main_sdram_bankmachine2_req_we = main_sdram_interface_bank2_we;
assign main_sdram_bankmachine2_req_addr = main_sdram_interface_bank2_addr;
assign main_sdram_interface_bank2_lock = main_sdram_bankmachine2_req_lock;
assign main_sdram_interface_bank2_wdata_ready = main_sdram_bankmachine2_req_wdata_ready;
assign main_sdram_interface_bank2_rdata_valid = main_sdram_bankmachine2_req_rdata_valid;
assign main_sdram_bankmachine3_req_valid = main_sdram_interface_bank3_valid;
assign main_sdram_interface_bank3_ready = main_sdram_bankmachine3_req_ready;
assign main_sdram_bankmachine3_req_we = main_sdram_interface_bank3_we;
assign main_sdram_bankmachine3_req_addr = main_sdram_interface_bank3_addr;
assign main_sdram_interface_bank3_lock = main_sdram_bankmachine3_req_lock;
assign main_sdram_interface_bank3_wdata_ready = main_sdram_bankmachine3_req_wdata_ready;
assign main_sdram_interface_bank3_rdata_valid = main_sdram_bankmachine3_req_rdata_valid;
assign main_sdram_bankmachine4_req_valid = main_sdram_interface_bank4_valid;
assign main_sdram_interface_bank4_ready = main_sdram_bankmachine4_req_ready;
assign main_sdram_bankmachine4_req_we = main_sdram_interface_bank4_we;
assign main_sdram_bankmachine4_req_addr = main_sdram_interface_bank4_addr;
assign main_sdram_interface_bank4_lock = main_sdram_bankmachine4_req_lock;
assign main_sdram_interface_bank4_wdata_ready = main_sdram_bankmachine4_req_wdata_ready;
assign main_sdram_interface_bank4_rdata_valid = main_sdram_bankmachine4_req_rdata_valid;
assign main_sdram_bankmachine5_req_valid = main_sdram_interface_bank5_valid;
assign main_sdram_interface_bank5_ready = main_sdram_bankmachine5_req_ready;
assign main_sdram_bankmachine5_req_we = main_sdram_interface_bank5_we;
assign main_sdram_bankmachine5_req_addr = main_sdram_interface_bank5_addr;
assign main_sdram_interface_bank5_lock = main_sdram_bankmachine5_req_lock;
assign main_sdram_interface_bank5_wdata_ready = main_sdram_bankmachine5_req_wdata_ready;
assign main_sdram_interface_bank5_rdata_valid = main_sdram_bankmachine5_req_rdata_valid;
assign main_sdram_bankmachine6_req_valid = main_sdram_interface_bank6_valid;
assign main_sdram_interface_bank6_ready = main_sdram_bankmachine6_req_ready;
assign main_sdram_bankmachine6_req_we = main_sdram_interface_bank6_we;
assign main_sdram_bankmachine6_req_addr = main_sdram_interface_bank6_addr;
assign main_sdram_interface_bank6_lock = main_sdram_bankmachine6_req_lock;
assign main_sdram_interface_bank6_wdata_ready = main_sdram_bankmachine6_req_wdata_ready;
assign main_sdram_interface_bank6_rdata_valid = main_sdram_bankmachine6_req_rdata_valid;
assign main_sdram_bankmachine7_req_valid = main_sdram_interface_bank7_valid;
assign main_sdram_interface_bank7_ready = main_sdram_bankmachine7_req_ready;
assign main_sdram_bankmachine7_req_we = main_sdram_interface_bank7_we;
assign main_sdram_bankmachine7_req_addr = main_sdram_interface_bank7_addr;
assign main_sdram_interface_bank7_lock = main_sdram_bankmachine7_req_lock;
assign main_sdram_interface_bank7_wdata_ready = main_sdram_bankmachine7_req_wdata_ready;
assign main_sdram_interface_bank7_rdata_valid = main_sdram_bankmachine7_req_rdata_valid;
assign main_sdram_timer_wait = (~main_sdram_timer_done0);
assign main_sdram_postponer_req_i = main_sdram_timer_done0;
assign main_sdram_wants_refresh = main_sdram_postponer_req_o;
assign main_sdram_wants_zqcs = main_sdram_zqcs_timer_done0;
assign main_sdram_zqcs_timer_wait = (~main_sdram_zqcs_executer_done);
assign main_sdram_timer_done1 = (main_sdram_timer_count1 == 1'd0);
assign main_sdram_timer_done0 = main_sdram_timer_done1;
assign main_sdram_timer_count0 = main_sdram_timer_count1;
assign main_sdram_sequencer_start1 = (main_sdram_sequencer_start0 | (main_sdram_sequencer_count != 1'd0));
assign main_sdram_sequencer_done0 = (main_sdram_sequencer_done1 & (main_sdram_sequencer_count == 1'd0));
assign main_sdram_zqcs_timer_done1 = (main_sdram_zqcs_timer_count1 == 1'd0);
assign main_sdram_zqcs_timer_done0 = main_sdram_zqcs_timer_done1;
assign main_sdram_zqcs_timer_count0 = main_sdram_zqcs_timer_count1;
always @(*) begin
main_sdram_zqcs_executer_start <= 1'd0;
main_sdram_cmd_last <= 1'd0;
main_sdram_sequencer_start0 <= 1'd0;
builder_refresher_next_state <= 2'd0;
main_sdram_cmd_valid <= 1'd0;
builder_refresher_next_state <= builder_refresher_state;
case (builder_refresher_state)
1'd1: begin
main_sdram_cmd_valid <= 1'd1;
if (main_sdram_cmd_ready) begin
main_sdram_sequencer_start0 <= 1'd1;
builder_refresher_next_state <= 2'd2;
end
end
2'd2: begin
main_sdram_cmd_valid <= 1'd1;
if (main_sdram_sequencer_done0) begin
if (main_sdram_wants_zqcs) begin
main_sdram_zqcs_executer_start <= 1'd1;
builder_refresher_next_state <= 2'd3;
end else begin
main_sdram_cmd_valid <= 1'd0;
main_sdram_cmd_last <= 1'd1;
builder_refresher_next_state <= 1'd0;
end
end
end
2'd3: begin
main_sdram_cmd_valid <= 1'd1;
if (main_sdram_zqcs_executer_done) begin
main_sdram_cmd_valid <= 1'd0;
main_sdram_cmd_last <= 1'd1;
builder_refresher_next_state <= 1'd0;
end
end
default: begin
if (1'd1) begin
if (main_sdram_wants_refresh) begin
builder_refresher_next_state <= 1'd1;
end
end
end
endcase
end
assign main_sdram_bankmachine0_cmd_buffer_lookahead_sink_valid = main_sdram_bankmachine0_req_valid;
assign main_sdram_bankmachine0_req_ready = main_sdram_bankmachine0_cmd_buffer_lookahead_sink_ready;
assign main_sdram_bankmachine0_cmd_buffer_lookahead_sink_payload_we = main_sdram_bankmachine0_req_we;
assign main_sdram_bankmachine0_cmd_buffer_lookahead_sink_payload_addr = main_sdram_bankmachine0_req_addr;
assign main_sdram_bankmachine0_cmd_buffer_sink_valid = main_sdram_bankmachine0_cmd_buffer_lookahead_source_valid;
assign main_sdram_bankmachine0_cmd_buffer_lookahead_source_ready = main_sdram_bankmachine0_cmd_buffer_sink_ready;
assign main_sdram_bankmachine0_cmd_buffer_sink_first = main_sdram_bankmachine0_cmd_buffer_lookahead_source_first;
assign main_sdram_bankmachine0_cmd_buffer_sink_last = main_sdram_bankmachine0_cmd_buffer_lookahead_source_last;
assign main_sdram_bankmachine0_cmd_buffer_sink_payload_we = main_sdram_bankmachine0_cmd_buffer_lookahead_source_payload_we;
assign main_sdram_bankmachine0_cmd_buffer_sink_payload_addr = main_sdram_bankmachine0_cmd_buffer_lookahead_source_payload_addr;
assign main_sdram_bankmachine0_cmd_buffer_source_ready = (main_sdram_bankmachine0_req_wdata_ready | main_sdram_bankmachine0_req_rdata_valid);
assign main_sdram_bankmachine0_req_lock = (main_sdram_bankmachine0_cmd_buffer_lookahead_source_valid | main_sdram_bankmachine0_cmd_buffer_source_valid);
assign main_sdram_bankmachine0_row_hit = (main_sdram_bankmachine0_row == main_sdram_bankmachine0_cmd_buffer_source_payload_addr[20:7]);
assign main_sdram_bankmachine0_cmd_payload_ba = 1'd0;
always @(*) begin
main_sdram_bankmachine0_cmd_payload_a <= 14'd0;
if (main_sdram_bankmachine0_row_col_n_addr_sel) begin
main_sdram_bankmachine0_cmd_payload_a <= main_sdram_bankmachine0_cmd_buffer_source_payload_addr[20:7];
end else begin
main_sdram_bankmachine0_cmd_payload_a <= ((main_sdram_bankmachine0_auto_precharge <<< 4'd10) | {main_sdram_bankmachine0_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
end
end
assign main_sdram_bankmachine0_twtpcon_valid = ((main_sdram_bankmachine0_cmd_valid & main_sdram_bankmachine0_cmd_ready) & main_sdram_bankmachine0_cmd_payload_is_write);
assign main_sdram_bankmachine0_trccon_valid = ((main_sdram_bankmachine0_cmd_valid & main_sdram_bankmachine0_cmd_ready) & main_sdram_bankmachine0_row_open);
assign main_sdram_bankmachine0_trascon_valid = ((main_sdram_bankmachine0_cmd_valid & main_sdram_bankmachine0_cmd_ready) & main_sdram_bankmachine0_row_open);
always @(*) begin
main_sdram_bankmachine0_auto_precharge <= 1'd0;
if ((main_sdram_bankmachine0_cmd_buffer_lookahead_source_valid & main_sdram_bankmachine0_cmd_buffer_source_valid)) begin
if ((main_sdram_bankmachine0_cmd_buffer_lookahead_source_payload_addr[20:7] != main_sdram_bankmachine0_cmd_buffer_source_payload_addr[20:7])) begin
main_sdram_bankmachine0_auto_precharge <= (main_sdram_bankmachine0_row_close == 1'd0);
end
end
end
assign main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_din = {main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_last, main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_first, main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_addr, main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_we};
assign {main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_last, main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_first, main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr, main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we} = main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout;
assign main_sdram_bankmachine0_cmd_buffer_lookahead_sink_ready = main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable;
assign main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_we = main_sdram_bankmachine0_cmd_buffer_lookahead_sink_valid;
assign main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_first = main_sdram_bankmachine0_cmd_buffer_lookahead_sink_first;
assign main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_last = main_sdram_bankmachine0_cmd_buffer_lookahead_sink_last;
assign main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_we = main_sdram_bankmachine0_cmd_buffer_lookahead_sink_payload_we;
assign main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_addr = main_sdram_bankmachine0_cmd_buffer_lookahead_sink_payload_addr;
assign main_sdram_bankmachine0_cmd_buffer_lookahead_source_valid = main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable;
assign main_sdram_bankmachine0_cmd_buffer_lookahead_source_first = main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_first;
assign main_sdram_bankmachine0_cmd_buffer_lookahead_source_last = main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_last;
assign main_sdram_bankmachine0_cmd_buffer_lookahead_source_payload_we = main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we;
assign main_sdram_bankmachine0_cmd_buffer_lookahead_source_payload_addr = main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr;
assign main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_re = main_sdram_bankmachine0_cmd_buffer_lookahead_source_ready;
always @(*) begin
main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr <= 3'd0;
if (main_sdram_bankmachine0_cmd_buffer_lookahead_replace) begin
main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr <= (main_sdram_bankmachine0_cmd_buffer_lookahead_produce - 1'd1);
end else begin
main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr <= main_sdram_bankmachine0_cmd_buffer_lookahead_produce;
end
end
assign main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_dat_w = main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_din;
assign main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_we = (main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_we & (main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable | main_sdram_bankmachine0_cmd_buffer_lookahead_replace));
assign main_sdram_bankmachine0_cmd_buffer_lookahead_do_read = (main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable & main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_re);
assign main_sdram_bankmachine0_cmd_buffer_lookahead_rdport_adr = main_sdram_bankmachine0_cmd_buffer_lookahead_consume;
assign main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout = main_sdram_bankmachine0_cmd_buffer_lookahead_rdport_dat_r;
assign main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable = (main_sdram_bankmachine0_cmd_buffer_lookahead_level != 4'd8);
assign main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable = (main_sdram_bankmachine0_cmd_buffer_lookahead_level != 1'd0);
assign main_sdram_bankmachine0_cmd_buffer_pipe_ce = (main_sdram_bankmachine0_cmd_buffer_source_ready | (~main_sdram_bankmachine0_cmd_buffer_valid_n));
assign main_sdram_bankmachine0_cmd_buffer_sink_ready = main_sdram_bankmachine0_cmd_buffer_pipe_ce;
assign main_sdram_bankmachine0_cmd_buffer_source_valid = main_sdram_bankmachine0_cmd_buffer_valid_n;
assign main_sdram_bankmachine0_cmd_buffer_busy = (1'd0 | main_sdram_bankmachine0_cmd_buffer_valid_n);
assign main_sdram_bankmachine0_cmd_buffer_source_first = main_sdram_bankmachine0_cmd_buffer_first_n;
assign main_sdram_bankmachine0_cmd_buffer_source_last = main_sdram_bankmachine0_cmd_buffer_last_n;
always @(*) begin
main_sdram_bankmachine0_row_col_n_addr_sel <= 1'd0;
main_sdram_bankmachine0_refresh_gnt <= 1'd0;
main_sdram_bankmachine0_cmd_valid <= 1'd0;
main_sdram_bankmachine0_cmd_payload_cas <= 1'd0;
main_sdram_bankmachine0_cmd_payload_ras <= 1'd0;
main_sdram_bankmachine0_cmd_payload_we <= 1'd0;
main_sdram_bankmachine0_cmd_payload_is_cmd <= 1'd0;
main_sdram_bankmachine0_row_open <= 1'd0;
main_sdram_bankmachine0_cmd_payload_is_read <= 1'd0;
main_sdram_bankmachine0_row_close <= 1'd0;
main_sdram_bankmachine0_cmd_payload_is_write <= 1'd0;
builder_bankmachine0_next_state <= 3'd0;
main_sdram_bankmachine0_req_wdata_ready <= 1'd0;
main_sdram_bankmachine0_req_rdata_valid <= 1'd0;
builder_bankmachine0_next_state <= builder_bankmachine0_state;
case (builder_bankmachine0_state)
1'd1: begin
if ((main_sdram_bankmachine0_twtpcon_ready & main_sdram_bankmachine0_trascon_ready)) begin
main_sdram_bankmachine0_cmd_valid <= 1'd1;
if (main_sdram_bankmachine0_cmd_ready) begin
builder_bankmachine0_next_state <= 3'd5;
end
main_sdram_bankmachine0_cmd_payload_ras <= 1'd1;
main_sdram_bankmachine0_cmd_payload_we <= 1'd1;
main_sdram_bankmachine0_cmd_payload_is_cmd <= 1'd1;
end
main_sdram_bankmachine0_row_close <= 1'd1;
end
2'd2: begin
if ((main_sdram_bankmachine0_twtpcon_ready & main_sdram_bankmachine0_trascon_ready)) begin
builder_bankmachine0_next_state <= 3'd5;
end
main_sdram_bankmachine0_row_close <= 1'd1;
end
2'd3: begin
if (main_sdram_bankmachine0_trccon_ready) begin
main_sdram_bankmachine0_row_col_n_addr_sel <= 1'd1;
main_sdram_bankmachine0_row_open <= 1'd1;
main_sdram_bankmachine0_cmd_valid <= 1'd1;
main_sdram_bankmachine0_cmd_payload_is_cmd <= 1'd1;
if (main_sdram_bankmachine0_cmd_ready) begin
builder_bankmachine0_next_state <= 3'd6;
end
main_sdram_bankmachine0_cmd_payload_ras <= 1'd1;
end
end
3'd4: begin
if (main_sdram_bankmachine0_twtpcon_ready) begin
main_sdram_bankmachine0_refresh_gnt <= 1'd1;
end
main_sdram_bankmachine0_row_close <= 1'd1;
main_sdram_bankmachine0_cmd_payload_is_cmd <= 1'd1;
if ((~main_sdram_bankmachine0_refresh_req)) begin
builder_bankmachine0_next_state <= 1'd0;
end
end
3'd5: begin
builder_bankmachine0_next_state <= 2'd3;
end
3'd6: begin
builder_bankmachine0_next_state <= 1'd0;
end
default: begin
if (main_sdram_bankmachine0_refresh_req) begin
builder_bankmachine0_next_state <= 3'd4;
end else begin
if (main_sdram_bankmachine0_cmd_buffer_source_valid) begin
if (main_sdram_bankmachine0_row_opened) begin
if (main_sdram_bankmachine0_row_hit) begin
main_sdram_bankmachine0_cmd_valid <= 1'd1;
if (main_sdram_bankmachine0_cmd_buffer_source_payload_we) begin
main_sdram_bankmachine0_req_wdata_ready <= main_sdram_bankmachine0_cmd_ready;
main_sdram_bankmachine0_cmd_payload_is_write <= 1'd1;
main_sdram_bankmachine0_cmd_payload_we <= 1'd1;
end else begin
main_sdram_bankmachine0_req_rdata_valid <= main_sdram_bankmachine0_cmd_ready;
main_sdram_bankmachine0_cmd_payload_is_read <= 1'd1;
end
main_sdram_bankmachine0_cmd_payload_cas <= 1'd1;
if ((main_sdram_bankmachine0_cmd_ready & main_sdram_bankmachine0_auto_precharge)) begin
builder_bankmachine0_next_state <= 2'd2;
end
end else begin
builder_bankmachine0_next_state <= 1'd1;
end
end else begin
builder_bankmachine0_next_state <= 2'd3;
end
end
end
end
endcase
end
assign main_sdram_bankmachine1_cmd_buffer_lookahead_sink_valid = main_sdram_bankmachine1_req_valid;
assign main_sdram_bankmachine1_req_ready = main_sdram_bankmachine1_cmd_buffer_lookahead_sink_ready;
assign main_sdram_bankmachine1_cmd_buffer_lookahead_sink_payload_we = main_sdram_bankmachine1_req_we;
assign main_sdram_bankmachine1_cmd_buffer_lookahead_sink_payload_addr = main_sdram_bankmachine1_req_addr;
assign main_sdram_bankmachine1_cmd_buffer_sink_valid = main_sdram_bankmachine1_cmd_buffer_lookahead_source_valid;
assign main_sdram_bankmachine1_cmd_buffer_lookahead_source_ready = main_sdram_bankmachine1_cmd_buffer_sink_ready;
assign main_sdram_bankmachine1_cmd_buffer_sink_first = main_sdram_bankmachine1_cmd_buffer_lookahead_source_first;
assign main_sdram_bankmachine1_cmd_buffer_sink_last = main_sdram_bankmachine1_cmd_buffer_lookahead_source_last;
assign main_sdram_bankmachine1_cmd_buffer_sink_payload_we = main_sdram_bankmachine1_cmd_buffer_lookahead_source_payload_we;
assign main_sdram_bankmachine1_cmd_buffer_sink_payload_addr = main_sdram_bankmachine1_cmd_buffer_lookahead_source_payload_addr;
assign main_sdram_bankmachine1_cmd_buffer_source_ready = (main_sdram_bankmachine1_req_wdata_ready | main_sdram_bankmachine1_req_rdata_valid);
assign main_sdram_bankmachine1_req_lock = (main_sdram_bankmachine1_cmd_buffer_lookahead_source_valid | main_sdram_bankmachine1_cmd_buffer_source_valid);
assign main_sdram_bankmachine1_row_hit = (main_sdram_bankmachine1_row == main_sdram_bankmachine1_cmd_buffer_source_payload_addr[20:7]);
assign main_sdram_bankmachine1_cmd_payload_ba = 1'd1;
always @(*) begin
main_sdram_bankmachine1_cmd_payload_a <= 14'd0;
if (main_sdram_bankmachine1_row_col_n_addr_sel) begin
main_sdram_bankmachine1_cmd_payload_a <= main_sdram_bankmachine1_cmd_buffer_source_payload_addr[20:7];
end else begin
main_sdram_bankmachine1_cmd_payload_a <= ((main_sdram_bankmachine1_auto_precharge <<< 4'd10) | {main_sdram_bankmachine1_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
end
end
assign main_sdram_bankmachine1_twtpcon_valid = ((main_sdram_bankmachine1_cmd_valid & main_sdram_bankmachine1_cmd_ready) & main_sdram_bankmachine1_cmd_payload_is_write);
assign main_sdram_bankmachine1_trccon_valid = ((main_sdram_bankmachine1_cmd_valid & main_sdram_bankmachine1_cmd_ready) & main_sdram_bankmachine1_row_open);
assign main_sdram_bankmachine1_trascon_valid = ((main_sdram_bankmachine1_cmd_valid & main_sdram_bankmachine1_cmd_ready) & main_sdram_bankmachine1_row_open);
always @(*) begin
main_sdram_bankmachine1_auto_precharge <= 1'd0;
if ((main_sdram_bankmachine1_cmd_buffer_lookahead_source_valid & main_sdram_bankmachine1_cmd_buffer_source_valid)) begin
if ((main_sdram_bankmachine1_cmd_buffer_lookahead_source_payload_addr[20:7] != main_sdram_bankmachine1_cmd_buffer_source_payload_addr[20:7])) begin
main_sdram_bankmachine1_auto_precharge <= (main_sdram_bankmachine1_row_close == 1'd0);
end
end
end
assign main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_din = {main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_last, main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_first, main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_addr, main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_we};
assign {main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_last, main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_first, main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr, main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we} = main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout;
assign main_sdram_bankmachine1_cmd_buffer_lookahead_sink_ready = main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable;
assign main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_we = main_sdram_bankmachine1_cmd_buffer_lookahead_sink_valid;
assign main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_first = main_sdram_bankmachine1_cmd_buffer_lookahead_sink_first;
assign main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_last = main_sdram_bankmachine1_cmd_buffer_lookahead_sink_last;
assign main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_we = main_sdram_bankmachine1_cmd_buffer_lookahead_sink_payload_we;
assign main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_addr = main_sdram_bankmachine1_cmd_buffer_lookahead_sink_payload_addr;
assign main_sdram_bankmachine1_cmd_buffer_lookahead_source_valid = main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable;
assign main_sdram_bankmachine1_cmd_buffer_lookahead_source_first = main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_first;
assign main_sdram_bankmachine1_cmd_buffer_lookahead_source_last = main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_last;
assign main_sdram_bankmachine1_cmd_buffer_lookahead_source_payload_we = main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we;
assign main_sdram_bankmachine1_cmd_buffer_lookahead_source_payload_addr = main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr;
assign main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_re = main_sdram_bankmachine1_cmd_buffer_lookahead_source_ready;
always @(*) begin
main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr <= 3'd0;
if (main_sdram_bankmachine1_cmd_buffer_lookahead_replace) begin
main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr <= (main_sdram_bankmachine1_cmd_buffer_lookahead_produce - 1'd1);
end else begin
main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr <= main_sdram_bankmachine1_cmd_buffer_lookahead_produce;
end
end
assign main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_dat_w = main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_din;
assign main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_we = (main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_we & (main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable | main_sdram_bankmachine1_cmd_buffer_lookahead_replace));
assign main_sdram_bankmachine1_cmd_buffer_lookahead_do_read = (main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable & main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_re);
assign main_sdram_bankmachine1_cmd_buffer_lookahead_rdport_adr = main_sdram_bankmachine1_cmd_buffer_lookahead_consume;
assign main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout = main_sdram_bankmachine1_cmd_buffer_lookahead_rdport_dat_r;
assign main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable = (main_sdram_bankmachine1_cmd_buffer_lookahead_level != 4'd8);
assign main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable = (main_sdram_bankmachine1_cmd_buffer_lookahead_level != 1'd0);
assign main_sdram_bankmachine1_cmd_buffer_pipe_ce = (main_sdram_bankmachine1_cmd_buffer_source_ready | (~main_sdram_bankmachine1_cmd_buffer_valid_n));
assign main_sdram_bankmachine1_cmd_buffer_sink_ready = main_sdram_bankmachine1_cmd_buffer_pipe_ce;
assign main_sdram_bankmachine1_cmd_buffer_source_valid = main_sdram_bankmachine1_cmd_buffer_valid_n;
assign main_sdram_bankmachine1_cmd_buffer_busy = (1'd0 | main_sdram_bankmachine1_cmd_buffer_valid_n);
assign main_sdram_bankmachine1_cmd_buffer_source_first = main_sdram_bankmachine1_cmd_buffer_first_n;
assign main_sdram_bankmachine1_cmd_buffer_source_last = main_sdram_bankmachine1_cmd_buffer_last_n;
always @(*) begin
main_sdram_bankmachine1_cmd_payload_we <= 1'd0;
main_sdram_bankmachine1_cmd_payload_is_cmd <= 1'd0;
main_sdram_bankmachine1_row_open <= 1'd0;
main_sdram_bankmachine1_cmd_payload_is_read <= 1'd0;
main_sdram_bankmachine1_row_close <= 1'd0;
main_sdram_bankmachine1_cmd_payload_is_write <= 1'd0;
main_sdram_bankmachine1_req_wdata_ready <= 1'd0;
main_sdram_bankmachine1_req_rdata_valid <= 1'd0;
main_sdram_bankmachine1_row_col_n_addr_sel <= 1'd0;
main_sdram_bankmachine1_refresh_gnt <= 1'd0;
main_sdram_bankmachine1_cmd_valid <= 1'd0;
builder_bankmachine1_next_state <= 3'd0;
main_sdram_bankmachine1_cmd_payload_cas <= 1'd0;
main_sdram_bankmachine1_cmd_payload_ras <= 1'd0;
builder_bankmachine1_next_state <= builder_bankmachine1_state;
case (builder_bankmachine1_state)
1'd1: begin
if ((main_sdram_bankmachine1_twtpcon_ready & main_sdram_bankmachine1_trascon_ready)) begin
main_sdram_bankmachine1_cmd_valid <= 1'd1;
if (main_sdram_bankmachine1_cmd_ready) begin
builder_bankmachine1_next_state <= 3'd5;
end
main_sdram_bankmachine1_cmd_payload_ras <= 1'd1;
main_sdram_bankmachine1_cmd_payload_we <= 1'd1;
main_sdram_bankmachine1_cmd_payload_is_cmd <= 1'd1;
end
main_sdram_bankmachine1_row_close <= 1'd1;
end
2'd2: begin
if ((main_sdram_bankmachine1_twtpcon_ready & main_sdram_bankmachine1_trascon_ready)) begin
builder_bankmachine1_next_state <= 3'd5;
end
main_sdram_bankmachine1_row_close <= 1'd1;
end
2'd3: begin
if (main_sdram_bankmachine1_trccon_ready) begin
main_sdram_bankmachine1_row_col_n_addr_sel <= 1'd1;
main_sdram_bankmachine1_row_open <= 1'd1;
main_sdram_bankmachine1_cmd_valid <= 1'd1;
main_sdram_bankmachine1_cmd_payload_is_cmd <= 1'd1;
if (main_sdram_bankmachine1_cmd_ready) begin
builder_bankmachine1_next_state <= 3'd6;
end
main_sdram_bankmachine1_cmd_payload_ras <= 1'd1;
end
end
3'd4: begin
if (main_sdram_bankmachine1_twtpcon_ready) begin
main_sdram_bankmachine1_refresh_gnt <= 1'd1;
end
main_sdram_bankmachine1_row_close <= 1'd1;
main_sdram_bankmachine1_cmd_payload_is_cmd <= 1'd1;
if ((~main_sdram_bankmachine1_refresh_req)) begin
builder_bankmachine1_next_state <= 1'd0;
end
end
3'd5: begin
builder_bankmachine1_next_state <= 2'd3;
end
3'd6: begin
builder_bankmachine1_next_state <= 1'd0;
end
default: begin
if (main_sdram_bankmachine1_refresh_req) begin
builder_bankmachine1_next_state <= 3'd4;
end else begin
if (main_sdram_bankmachine1_cmd_buffer_source_valid) begin
if (main_sdram_bankmachine1_row_opened) begin
if (main_sdram_bankmachine1_row_hit) begin
main_sdram_bankmachine1_cmd_valid <= 1'd1;
if (main_sdram_bankmachine1_cmd_buffer_source_payload_we) begin
main_sdram_bankmachine1_req_wdata_ready <= main_sdram_bankmachine1_cmd_ready;
main_sdram_bankmachine1_cmd_payload_is_write <= 1'd1;
main_sdram_bankmachine1_cmd_payload_we <= 1'd1;
end else begin
main_sdram_bankmachine1_req_rdata_valid <= main_sdram_bankmachine1_cmd_ready;
main_sdram_bankmachine1_cmd_payload_is_read <= 1'd1;
end
main_sdram_bankmachine1_cmd_payload_cas <= 1'd1;
if ((main_sdram_bankmachine1_cmd_ready & main_sdram_bankmachine1_auto_precharge)) begin
builder_bankmachine1_next_state <= 2'd2;
end
end else begin
builder_bankmachine1_next_state <= 1'd1;
end
end else begin
builder_bankmachine1_next_state <= 2'd3;
end
end
end
end
endcase
end
assign main_sdram_bankmachine2_cmd_buffer_lookahead_sink_valid = main_sdram_bankmachine2_req_valid;
assign main_sdram_bankmachine2_req_ready = main_sdram_bankmachine2_cmd_buffer_lookahead_sink_ready;
assign main_sdram_bankmachine2_cmd_buffer_lookahead_sink_payload_we = main_sdram_bankmachine2_req_we;
assign main_sdram_bankmachine2_cmd_buffer_lookahead_sink_payload_addr = main_sdram_bankmachine2_req_addr;
assign main_sdram_bankmachine2_cmd_buffer_sink_valid = main_sdram_bankmachine2_cmd_buffer_lookahead_source_valid;
assign main_sdram_bankmachine2_cmd_buffer_lookahead_source_ready = main_sdram_bankmachine2_cmd_buffer_sink_ready;
assign main_sdram_bankmachine2_cmd_buffer_sink_first = main_sdram_bankmachine2_cmd_buffer_lookahead_source_first;
assign main_sdram_bankmachine2_cmd_buffer_sink_last = main_sdram_bankmachine2_cmd_buffer_lookahead_source_last;
assign main_sdram_bankmachine2_cmd_buffer_sink_payload_we = main_sdram_bankmachine2_cmd_buffer_lookahead_source_payload_we;
assign main_sdram_bankmachine2_cmd_buffer_sink_payload_addr = main_sdram_bankmachine2_cmd_buffer_lookahead_source_payload_addr;
assign main_sdram_bankmachine2_cmd_buffer_source_ready = (main_sdram_bankmachine2_req_wdata_ready | main_sdram_bankmachine2_req_rdata_valid);
assign main_sdram_bankmachine2_req_lock = (main_sdram_bankmachine2_cmd_buffer_lookahead_source_valid | main_sdram_bankmachine2_cmd_buffer_source_valid);
assign main_sdram_bankmachine2_row_hit = (main_sdram_bankmachine2_row == main_sdram_bankmachine2_cmd_buffer_source_payload_addr[20:7]);
assign main_sdram_bankmachine2_cmd_payload_ba = 2'd2;
always @(*) begin
main_sdram_bankmachine2_cmd_payload_a <= 14'd0;
if (main_sdram_bankmachine2_row_col_n_addr_sel) begin
main_sdram_bankmachine2_cmd_payload_a <= main_sdram_bankmachine2_cmd_buffer_source_payload_addr[20:7];
end else begin
main_sdram_bankmachine2_cmd_payload_a <= ((main_sdram_bankmachine2_auto_precharge <<< 4'd10) | {main_sdram_bankmachine2_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
end
end
assign main_sdram_bankmachine2_twtpcon_valid = ((main_sdram_bankmachine2_cmd_valid & main_sdram_bankmachine2_cmd_ready) & main_sdram_bankmachine2_cmd_payload_is_write);
assign main_sdram_bankmachine2_trccon_valid = ((main_sdram_bankmachine2_cmd_valid & main_sdram_bankmachine2_cmd_ready) & main_sdram_bankmachine2_row_open);
assign main_sdram_bankmachine2_trascon_valid = ((main_sdram_bankmachine2_cmd_valid & main_sdram_bankmachine2_cmd_ready) & main_sdram_bankmachine2_row_open);
always @(*) begin
main_sdram_bankmachine2_auto_precharge <= 1'd0;
if ((main_sdram_bankmachine2_cmd_buffer_lookahead_source_valid & main_sdram_bankmachine2_cmd_buffer_source_valid)) begin
if ((main_sdram_bankmachine2_cmd_buffer_lookahead_source_payload_addr[20:7] != main_sdram_bankmachine2_cmd_buffer_source_payload_addr[20:7])) begin
main_sdram_bankmachine2_auto_precharge <= (main_sdram_bankmachine2_row_close == 1'd0);
end
end
end
assign main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_din = {main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_last, main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_first, main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_addr, main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_we};
assign {main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_last, main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_first, main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr, main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we} = main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout;
assign main_sdram_bankmachine2_cmd_buffer_lookahead_sink_ready = main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable;
assign main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_we = main_sdram_bankmachine2_cmd_buffer_lookahead_sink_valid;
assign main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_first = main_sdram_bankmachine2_cmd_buffer_lookahead_sink_first;
assign main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_last = main_sdram_bankmachine2_cmd_buffer_lookahead_sink_last;
assign main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_we = main_sdram_bankmachine2_cmd_buffer_lookahead_sink_payload_we;
assign main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_addr = main_sdram_bankmachine2_cmd_buffer_lookahead_sink_payload_addr;
assign main_sdram_bankmachine2_cmd_buffer_lookahead_source_valid = main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable;
assign main_sdram_bankmachine2_cmd_buffer_lookahead_source_first = main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_first;
assign main_sdram_bankmachine2_cmd_buffer_lookahead_source_last = main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_last;
assign main_sdram_bankmachine2_cmd_buffer_lookahead_source_payload_we = main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we;
assign main_sdram_bankmachine2_cmd_buffer_lookahead_source_payload_addr = main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr;
assign main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_re = main_sdram_bankmachine2_cmd_buffer_lookahead_source_ready;
always @(*) begin
main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr <= 3'd0;
if (main_sdram_bankmachine2_cmd_buffer_lookahead_replace) begin
main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr <= (main_sdram_bankmachine2_cmd_buffer_lookahead_produce - 1'd1);
end else begin
main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr <= main_sdram_bankmachine2_cmd_buffer_lookahead_produce;
end
end
assign main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_dat_w = main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_din;
assign main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_we = (main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_we & (main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable | main_sdram_bankmachine2_cmd_buffer_lookahead_replace));
assign main_sdram_bankmachine2_cmd_buffer_lookahead_do_read = (main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable & main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_re);
assign main_sdram_bankmachine2_cmd_buffer_lookahead_rdport_adr = main_sdram_bankmachine2_cmd_buffer_lookahead_consume;
assign main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout = main_sdram_bankmachine2_cmd_buffer_lookahead_rdport_dat_r;
assign main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable = (main_sdram_bankmachine2_cmd_buffer_lookahead_level != 4'd8);
assign main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable = (main_sdram_bankmachine2_cmd_buffer_lookahead_level != 1'd0);
assign main_sdram_bankmachine2_cmd_buffer_pipe_ce = (main_sdram_bankmachine2_cmd_buffer_source_ready | (~main_sdram_bankmachine2_cmd_buffer_valid_n));
assign main_sdram_bankmachine2_cmd_buffer_sink_ready = main_sdram_bankmachine2_cmd_buffer_pipe_ce;
assign main_sdram_bankmachine2_cmd_buffer_source_valid = main_sdram_bankmachine2_cmd_buffer_valid_n;
assign main_sdram_bankmachine2_cmd_buffer_busy = (1'd0 | main_sdram_bankmachine2_cmd_buffer_valid_n);
assign main_sdram_bankmachine2_cmd_buffer_source_first = main_sdram_bankmachine2_cmd_buffer_first_n;
assign main_sdram_bankmachine2_cmd_buffer_source_last = main_sdram_bankmachine2_cmd_buffer_last_n;
always @(*) begin
main_sdram_bankmachine2_cmd_payload_cas <= 1'd0;
main_sdram_bankmachine2_cmd_payload_ras <= 1'd0;
main_sdram_bankmachine2_cmd_payload_we <= 1'd0;
main_sdram_bankmachine2_cmd_payload_is_cmd <= 1'd0;
main_sdram_bankmachine2_row_open <= 1'd0;
main_sdram_bankmachine2_cmd_payload_is_read <= 1'd0;
main_sdram_bankmachine2_row_close <= 1'd0;
main_sdram_bankmachine2_cmd_payload_is_write <= 1'd0;
builder_bankmachine2_next_state <= 3'd0;
main_sdram_bankmachine2_req_wdata_ready <= 1'd0;
main_sdram_bankmachine2_req_rdata_valid <= 1'd0;
main_sdram_bankmachine2_row_col_n_addr_sel <= 1'd0;
main_sdram_bankmachine2_refresh_gnt <= 1'd0;
main_sdram_bankmachine2_cmd_valid <= 1'd0;
builder_bankmachine2_next_state <= builder_bankmachine2_state;
case (builder_bankmachine2_state)
1'd1: begin
if ((main_sdram_bankmachine2_twtpcon_ready & main_sdram_bankmachine2_trascon_ready)) begin
main_sdram_bankmachine2_cmd_valid <= 1'd1;
if (main_sdram_bankmachine2_cmd_ready) begin
builder_bankmachine2_next_state <= 3'd5;
end
main_sdram_bankmachine2_cmd_payload_ras <= 1'd1;
main_sdram_bankmachine2_cmd_payload_we <= 1'd1;
main_sdram_bankmachine2_cmd_payload_is_cmd <= 1'd1;
end
main_sdram_bankmachine2_row_close <= 1'd1;
end
2'd2: begin
if ((main_sdram_bankmachine2_twtpcon_ready & main_sdram_bankmachine2_trascon_ready)) begin
builder_bankmachine2_next_state <= 3'd5;
end
main_sdram_bankmachine2_row_close <= 1'd1;
end
2'd3: begin
if (main_sdram_bankmachine2_trccon_ready) begin
main_sdram_bankmachine2_row_col_n_addr_sel <= 1'd1;
main_sdram_bankmachine2_row_open <= 1'd1;
main_sdram_bankmachine2_cmd_valid <= 1'd1;
main_sdram_bankmachine2_cmd_payload_is_cmd <= 1'd1;
if (main_sdram_bankmachine2_cmd_ready) begin
builder_bankmachine2_next_state <= 3'd6;
end
main_sdram_bankmachine2_cmd_payload_ras <= 1'd1;
end
end
3'd4: begin
if (main_sdram_bankmachine2_twtpcon_ready) begin
main_sdram_bankmachine2_refresh_gnt <= 1'd1;
end
main_sdram_bankmachine2_row_close <= 1'd1;
main_sdram_bankmachine2_cmd_payload_is_cmd <= 1'd1;
if ((~main_sdram_bankmachine2_refresh_req)) begin
builder_bankmachine2_next_state <= 1'd0;
end
end
3'd5: begin
builder_bankmachine2_next_state <= 2'd3;
end
3'd6: begin
builder_bankmachine2_next_state <= 1'd0;
end
default: begin
if (main_sdram_bankmachine2_refresh_req) begin
builder_bankmachine2_next_state <= 3'd4;
end else begin
if (main_sdram_bankmachine2_cmd_buffer_source_valid) begin
if (main_sdram_bankmachine2_row_opened) begin
if (main_sdram_bankmachine2_row_hit) begin
main_sdram_bankmachine2_cmd_valid <= 1'd1;
if (main_sdram_bankmachine2_cmd_buffer_source_payload_we) begin
main_sdram_bankmachine2_req_wdata_ready <= main_sdram_bankmachine2_cmd_ready;
main_sdram_bankmachine2_cmd_payload_is_write <= 1'd1;
main_sdram_bankmachine2_cmd_payload_we <= 1'd1;
end else begin
main_sdram_bankmachine2_req_rdata_valid <= main_sdram_bankmachine2_cmd_ready;
main_sdram_bankmachine2_cmd_payload_is_read <= 1'd1;
end
main_sdram_bankmachine2_cmd_payload_cas <= 1'd1;
if ((main_sdram_bankmachine2_cmd_ready & main_sdram_bankmachine2_auto_precharge)) begin
builder_bankmachine2_next_state <= 2'd2;
end
end else begin
builder_bankmachine2_next_state <= 1'd1;
end
end else begin
builder_bankmachine2_next_state <= 2'd3;
end
end
end
end
endcase
end
assign main_sdram_bankmachine3_cmd_buffer_lookahead_sink_valid = main_sdram_bankmachine3_req_valid;
assign main_sdram_bankmachine3_req_ready = main_sdram_bankmachine3_cmd_buffer_lookahead_sink_ready;
assign main_sdram_bankmachine3_cmd_buffer_lookahead_sink_payload_we = main_sdram_bankmachine3_req_we;
assign main_sdram_bankmachine3_cmd_buffer_lookahead_sink_payload_addr = main_sdram_bankmachine3_req_addr;
assign main_sdram_bankmachine3_cmd_buffer_sink_valid = main_sdram_bankmachine3_cmd_buffer_lookahead_source_valid;
assign main_sdram_bankmachine3_cmd_buffer_lookahead_source_ready = main_sdram_bankmachine3_cmd_buffer_sink_ready;
assign main_sdram_bankmachine3_cmd_buffer_sink_first = main_sdram_bankmachine3_cmd_buffer_lookahead_source_first;
assign main_sdram_bankmachine3_cmd_buffer_sink_last = main_sdram_bankmachine3_cmd_buffer_lookahead_source_last;
assign main_sdram_bankmachine3_cmd_buffer_sink_payload_we = main_sdram_bankmachine3_cmd_buffer_lookahead_source_payload_we;
assign main_sdram_bankmachine3_cmd_buffer_sink_payload_addr = main_sdram_bankmachine3_cmd_buffer_lookahead_source_payload_addr;
assign main_sdram_bankmachine3_cmd_buffer_source_ready = (main_sdram_bankmachine3_req_wdata_ready | main_sdram_bankmachine3_req_rdata_valid);
assign main_sdram_bankmachine3_req_lock = (main_sdram_bankmachine3_cmd_buffer_lookahead_source_valid | main_sdram_bankmachine3_cmd_buffer_source_valid);
assign main_sdram_bankmachine3_row_hit = (main_sdram_bankmachine3_row == main_sdram_bankmachine3_cmd_buffer_source_payload_addr[20:7]);
assign main_sdram_bankmachine3_cmd_payload_ba = 2'd3;
always @(*) begin
main_sdram_bankmachine3_cmd_payload_a <= 14'd0;
if (main_sdram_bankmachine3_row_col_n_addr_sel) begin
main_sdram_bankmachine3_cmd_payload_a <= main_sdram_bankmachine3_cmd_buffer_source_payload_addr[20:7];
end else begin
main_sdram_bankmachine3_cmd_payload_a <= ((main_sdram_bankmachine3_auto_precharge <<< 4'd10) | {main_sdram_bankmachine3_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
end
end
assign main_sdram_bankmachine3_twtpcon_valid = ((main_sdram_bankmachine3_cmd_valid & main_sdram_bankmachine3_cmd_ready) & main_sdram_bankmachine3_cmd_payload_is_write);
assign main_sdram_bankmachine3_trccon_valid = ((main_sdram_bankmachine3_cmd_valid & main_sdram_bankmachine3_cmd_ready) & main_sdram_bankmachine3_row_open);
assign main_sdram_bankmachine3_trascon_valid = ((main_sdram_bankmachine3_cmd_valid & main_sdram_bankmachine3_cmd_ready) & main_sdram_bankmachine3_row_open);
always @(*) begin
main_sdram_bankmachine3_auto_precharge <= 1'd0;
if ((main_sdram_bankmachine3_cmd_buffer_lookahead_source_valid & main_sdram_bankmachine3_cmd_buffer_source_valid)) begin
if ((main_sdram_bankmachine3_cmd_buffer_lookahead_source_payload_addr[20:7] != main_sdram_bankmachine3_cmd_buffer_source_payload_addr[20:7])) begin
main_sdram_bankmachine3_auto_precharge <= (main_sdram_bankmachine3_row_close == 1'd0);
end
end
end
assign main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_din = {main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_last, main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_first, main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_addr, main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_we};
assign {main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_last, main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_first, main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr, main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we} = main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout;
assign main_sdram_bankmachine3_cmd_buffer_lookahead_sink_ready = main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable;
assign main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_we = main_sdram_bankmachine3_cmd_buffer_lookahead_sink_valid;
assign main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_first = main_sdram_bankmachine3_cmd_buffer_lookahead_sink_first;
assign main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_last = main_sdram_bankmachine3_cmd_buffer_lookahead_sink_last;
assign main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_we = main_sdram_bankmachine3_cmd_buffer_lookahead_sink_payload_we;
assign main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_addr = main_sdram_bankmachine3_cmd_buffer_lookahead_sink_payload_addr;
assign main_sdram_bankmachine3_cmd_buffer_lookahead_source_valid = main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable;
assign main_sdram_bankmachine3_cmd_buffer_lookahead_source_first = main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_first;
assign main_sdram_bankmachine3_cmd_buffer_lookahead_source_last = main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_last;
assign main_sdram_bankmachine3_cmd_buffer_lookahead_source_payload_we = main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we;
assign main_sdram_bankmachine3_cmd_buffer_lookahead_source_payload_addr = main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr;
assign main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_re = main_sdram_bankmachine3_cmd_buffer_lookahead_source_ready;
always @(*) begin
main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr <= 3'd0;
if (main_sdram_bankmachine3_cmd_buffer_lookahead_replace) begin
main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr <= (main_sdram_bankmachine3_cmd_buffer_lookahead_produce - 1'd1);
end else begin
main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr <= main_sdram_bankmachine3_cmd_buffer_lookahead_produce;
end
end
assign main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_dat_w = main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_din;
assign main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_we = (main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_we & (main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable | main_sdram_bankmachine3_cmd_buffer_lookahead_replace));
assign main_sdram_bankmachine3_cmd_buffer_lookahead_do_read = (main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable & main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_re);
assign main_sdram_bankmachine3_cmd_buffer_lookahead_rdport_adr = main_sdram_bankmachine3_cmd_buffer_lookahead_consume;
assign main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout = main_sdram_bankmachine3_cmd_buffer_lookahead_rdport_dat_r;
assign main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable = (main_sdram_bankmachine3_cmd_buffer_lookahead_level != 4'd8);
assign main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable = (main_sdram_bankmachine3_cmd_buffer_lookahead_level != 1'd0);
assign main_sdram_bankmachine3_cmd_buffer_pipe_ce = (main_sdram_bankmachine3_cmd_buffer_source_ready | (~main_sdram_bankmachine3_cmd_buffer_valid_n));
assign main_sdram_bankmachine3_cmd_buffer_sink_ready = main_sdram_bankmachine3_cmd_buffer_pipe_ce;
assign main_sdram_bankmachine3_cmd_buffer_source_valid = main_sdram_bankmachine3_cmd_buffer_valid_n;
assign main_sdram_bankmachine3_cmd_buffer_busy = (1'd0 | main_sdram_bankmachine3_cmd_buffer_valid_n);
assign main_sdram_bankmachine3_cmd_buffer_source_first = main_sdram_bankmachine3_cmd_buffer_first_n;
assign main_sdram_bankmachine3_cmd_buffer_source_last = main_sdram_bankmachine3_cmd_buffer_last_n;
always @(*) begin
main_sdram_bankmachine3_req_wdata_ready <= 1'd0;
main_sdram_bankmachine3_req_rdata_valid <= 1'd0;
main_sdram_bankmachine3_row_col_n_addr_sel <= 1'd0;
main_sdram_bankmachine3_refresh_gnt <= 1'd0;
main_sdram_bankmachine3_cmd_valid <= 1'd0;
builder_bankmachine3_next_state <= 3'd0;
main_sdram_bankmachine3_cmd_payload_cas <= 1'd0;
main_sdram_bankmachine3_cmd_payload_ras <= 1'd0;
main_sdram_bankmachine3_cmd_payload_we <= 1'd0;
main_sdram_bankmachine3_cmd_payload_is_cmd <= 1'd0;
main_sdram_bankmachine3_row_open <= 1'd0;
main_sdram_bankmachine3_cmd_payload_is_read <= 1'd0;
main_sdram_bankmachine3_row_close <= 1'd0;
main_sdram_bankmachine3_cmd_payload_is_write <= 1'd0;
builder_bankmachine3_next_state <= builder_bankmachine3_state;
case (builder_bankmachine3_state)
1'd1: begin
if ((main_sdram_bankmachine3_twtpcon_ready & main_sdram_bankmachine3_trascon_ready)) begin
main_sdram_bankmachine3_cmd_valid <= 1'd1;
if (main_sdram_bankmachine3_cmd_ready) begin
builder_bankmachine3_next_state <= 3'd5;
end
main_sdram_bankmachine3_cmd_payload_ras <= 1'd1;
main_sdram_bankmachine3_cmd_payload_we <= 1'd1;
main_sdram_bankmachine3_cmd_payload_is_cmd <= 1'd1;
end
main_sdram_bankmachine3_row_close <= 1'd1;
end
2'd2: begin
if ((main_sdram_bankmachine3_twtpcon_ready & main_sdram_bankmachine3_trascon_ready)) begin
builder_bankmachine3_next_state <= 3'd5;
end
main_sdram_bankmachine3_row_close <= 1'd1;
end
2'd3: begin
if (main_sdram_bankmachine3_trccon_ready) begin
main_sdram_bankmachine3_row_col_n_addr_sel <= 1'd1;
main_sdram_bankmachine3_row_open <= 1'd1;
main_sdram_bankmachine3_cmd_valid <= 1'd1;
main_sdram_bankmachine3_cmd_payload_is_cmd <= 1'd1;
if (main_sdram_bankmachine3_cmd_ready) begin
builder_bankmachine3_next_state <= 3'd6;
end
main_sdram_bankmachine3_cmd_payload_ras <= 1'd1;
end
end
3'd4: begin
if (main_sdram_bankmachine3_twtpcon_ready) begin
main_sdram_bankmachine3_refresh_gnt <= 1'd1;
end
main_sdram_bankmachine3_row_close <= 1'd1;
main_sdram_bankmachine3_cmd_payload_is_cmd <= 1'd1;
if ((~main_sdram_bankmachine3_refresh_req)) begin
builder_bankmachine3_next_state <= 1'd0;
end
end
3'd5: begin
builder_bankmachine3_next_state <= 2'd3;
end
3'd6: begin
builder_bankmachine3_next_state <= 1'd0;
end
default: begin
if (main_sdram_bankmachine3_refresh_req) begin
builder_bankmachine3_next_state <= 3'd4;
end else begin
if (main_sdram_bankmachine3_cmd_buffer_source_valid) begin
if (main_sdram_bankmachine3_row_opened) begin
if (main_sdram_bankmachine3_row_hit) begin
main_sdram_bankmachine3_cmd_valid <= 1'd1;
if (main_sdram_bankmachine3_cmd_buffer_source_payload_we) begin
main_sdram_bankmachine3_req_wdata_ready <= main_sdram_bankmachine3_cmd_ready;
main_sdram_bankmachine3_cmd_payload_is_write <= 1'd1;
main_sdram_bankmachine3_cmd_payload_we <= 1'd1;
end else begin
main_sdram_bankmachine3_req_rdata_valid <= main_sdram_bankmachine3_cmd_ready;
main_sdram_bankmachine3_cmd_payload_is_read <= 1'd1;
end
main_sdram_bankmachine3_cmd_payload_cas <= 1'd1;
if ((main_sdram_bankmachine3_cmd_ready & main_sdram_bankmachine3_auto_precharge)) begin
builder_bankmachine3_next_state <= 2'd2;
end
end else begin
builder_bankmachine3_next_state <= 1'd1;
end
end else begin
builder_bankmachine3_next_state <= 2'd3;
end
end
end
end
endcase
end
assign main_sdram_bankmachine4_cmd_buffer_lookahead_sink_valid = main_sdram_bankmachine4_req_valid;
assign main_sdram_bankmachine4_req_ready = main_sdram_bankmachine4_cmd_buffer_lookahead_sink_ready;
assign main_sdram_bankmachine4_cmd_buffer_lookahead_sink_payload_we = main_sdram_bankmachine4_req_we;
assign main_sdram_bankmachine4_cmd_buffer_lookahead_sink_payload_addr = main_sdram_bankmachine4_req_addr;
assign main_sdram_bankmachine4_cmd_buffer_sink_valid = main_sdram_bankmachine4_cmd_buffer_lookahead_source_valid;
assign main_sdram_bankmachine4_cmd_buffer_lookahead_source_ready = main_sdram_bankmachine4_cmd_buffer_sink_ready;
assign main_sdram_bankmachine4_cmd_buffer_sink_first = main_sdram_bankmachine4_cmd_buffer_lookahead_source_first;
assign main_sdram_bankmachine4_cmd_buffer_sink_last = main_sdram_bankmachine4_cmd_buffer_lookahead_source_last;
assign main_sdram_bankmachine4_cmd_buffer_sink_payload_we = main_sdram_bankmachine4_cmd_buffer_lookahead_source_payload_we;
assign main_sdram_bankmachine4_cmd_buffer_sink_payload_addr = main_sdram_bankmachine4_cmd_buffer_lookahead_source_payload_addr;
assign main_sdram_bankmachine4_cmd_buffer_source_ready = (main_sdram_bankmachine4_req_wdata_ready | main_sdram_bankmachine4_req_rdata_valid);
assign main_sdram_bankmachine4_req_lock = (main_sdram_bankmachine4_cmd_buffer_lookahead_source_valid | main_sdram_bankmachine4_cmd_buffer_source_valid);
assign main_sdram_bankmachine4_row_hit = (main_sdram_bankmachine4_row == main_sdram_bankmachine4_cmd_buffer_source_payload_addr[20:7]);
assign main_sdram_bankmachine4_cmd_payload_ba = 3'd4;
always @(*) begin
main_sdram_bankmachine4_cmd_payload_a <= 14'd0;
if (main_sdram_bankmachine4_row_col_n_addr_sel) begin
main_sdram_bankmachine4_cmd_payload_a <= main_sdram_bankmachine4_cmd_buffer_source_payload_addr[20:7];
end else begin
main_sdram_bankmachine4_cmd_payload_a <= ((main_sdram_bankmachine4_auto_precharge <<< 4'd10) | {main_sdram_bankmachine4_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
end
end
assign main_sdram_bankmachine4_twtpcon_valid = ((main_sdram_bankmachine4_cmd_valid & main_sdram_bankmachine4_cmd_ready) & main_sdram_bankmachine4_cmd_payload_is_write);
assign main_sdram_bankmachine4_trccon_valid = ((main_sdram_bankmachine4_cmd_valid & main_sdram_bankmachine4_cmd_ready) & main_sdram_bankmachine4_row_open);
assign main_sdram_bankmachine4_trascon_valid = ((main_sdram_bankmachine4_cmd_valid & main_sdram_bankmachine4_cmd_ready) & main_sdram_bankmachine4_row_open);
always @(*) begin
main_sdram_bankmachine4_auto_precharge <= 1'd0;
if ((main_sdram_bankmachine4_cmd_buffer_lookahead_source_valid & main_sdram_bankmachine4_cmd_buffer_source_valid)) begin
if ((main_sdram_bankmachine4_cmd_buffer_lookahead_source_payload_addr[20:7] != main_sdram_bankmachine4_cmd_buffer_source_payload_addr[20:7])) begin
main_sdram_bankmachine4_auto_precharge <= (main_sdram_bankmachine4_row_close == 1'd0);
end
end
end
assign main_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_din = {main_sdram_bankmachine4_cmd_buffer_lookahead_fifo_in_last, main_sdram_bankmachine4_cmd_buffer_lookahead_fifo_in_first, main_sdram_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_addr, main_sdram_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_we};
assign {main_sdram_bankmachine4_cmd_buffer_lookahead_fifo_out_last, main_sdram_bankmachine4_cmd_buffer_lookahead_fifo_out_first, main_sdram_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr, main_sdram_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we} = main_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout;
assign main_sdram_bankmachine4_cmd_buffer_lookahead_sink_ready = main_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable;
assign main_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_we = main_sdram_bankmachine4_cmd_buffer_lookahead_sink_valid;
assign main_sdram_bankmachine4_cmd_buffer_lookahead_fifo_in_first = main_sdram_bankmachine4_cmd_buffer_lookahead_sink_first;
assign main_sdram_bankmachine4_cmd_buffer_lookahead_fifo_in_last = main_sdram_bankmachine4_cmd_buffer_lookahead_sink_last;
assign main_sdram_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_we = main_sdram_bankmachine4_cmd_buffer_lookahead_sink_payload_we;
assign main_sdram_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_addr = main_sdram_bankmachine4_cmd_buffer_lookahead_sink_payload_addr;
assign main_sdram_bankmachine4_cmd_buffer_lookahead_source_valid = main_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_readable;
assign main_sdram_bankmachine4_cmd_buffer_lookahead_source_first = main_sdram_bankmachine4_cmd_buffer_lookahead_fifo_out_first;
assign main_sdram_bankmachine4_cmd_buffer_lookahead_source_last = main_sdram_bankmachine4_cmd_buffer_lookahead_fifo_out_last;
assign main_sdram_bankmachine4_cmd_buffer_lookahead_source_payload_we = main_sdram_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we;
assign main_sdram_bankmachine4_cmd_buffer_lookahead_source_payload_addr = main_sdram_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr;
assign main_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_re = main_sdram_bankmachine4_cmd_buffer_lookahead_source_ready;
always @(*) begin
main_sdram_bankmachine4_cmd_buffer_lookahead_wrport_adr <= 3'd0;
if (main_sdram_bankmachine4_cmd_buffer_lookahead_replace) begin
main_sdram_bankmachine4_cmd_buffer_lookahead_wrport_adr <= (main_sdram_bankmachine4_cmd_buffer_lookahead_produce - 1'd1);
end else begin
main_sdram_bankmachine4_cmd_buffer_lookahead_wrport_adr <= main_sdram_bankmachine4_cmd_buffer_lookahead_produce;
end
end
assign main_sdram_bankmachine4_cmd_buffer_lookahead_wrport_dat_w = main_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_din;
assign main_sdram_bankmachine4_cmd_buffer_lookahead_wrport_we = (main_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_we & (main_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable | main_sdram_bankmachine4_cmd_buffer_lookahead_replace));
assign main_sdram_bankmachine4_cmd_buffer_lookahead_do_read = (main_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_readable & main_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_re);
assign main_sdram_bankmachine4_cmd_buffer_lookahead_rdport_adr = main_sdram_bankmachine4_cmd_buffer_lookahead_consume;
assign main_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout = main_sdram_bankmachine4_cmd_buffer_lookahead_rdport_dat_r;
assign main_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable = (main_sdram_bankmachine4_cmd_buffer_lookahead_level != 4'd8);
assign main_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_readable = (main_sdram_bankmachine4_cmd_buffer_lookahead_level != 1'd0);
assign main_sdram_bankmachine4_cmd_buffer_pipe_ce = (main_sdram_bankmachine4_cmd_buffer_source_ready | (~main_sdram_bankmachine4_cmd_buffer_valid_n));
assign main_sdram_bankmachine4_cmd_buffer_sink_ready = main_sdram_bankmachine4_cmd_buffer_pipe_ce;
assign main_sdram_bankmachine4_cmd_buffer_source_valid = main_sdram_bankmachine4_cmd_buffer_valid_n;
assign main_sdram_bankmachine4_cmd_buffer_busy = (1'd0 | main_sdram_bankmachine4_cmd_buffer_valid_n);
assign main_sdram_bankmachine4_cmd_buffer_source_first = main_sdram_bankmachine4_cmd_buffer_first_n;
assign main_sdram_bankmachine4_cmd_buffer_source_last = main_sdram_bankmachine4_cmd_buffer_last_n;
always @(*) begin
main_sdram_bankmachine4_cmd_payload_cas <= 1'd0;
main_sdram_bankmachine4_cmd_payload_ras <= 1'd0;
main_sdram_bankmachine4_cmd_payload_we <= 1'd0;
main_sdram_bankmachine4_cmd_payload_is_cmd <= 1'd0;
main_sdram_bankmachine4_row_open <= 1'd0;
main_sdram_bankmachine4_cmd_payload_is_read <= 1'd0;
main_sdram_bankmachine4_row_close <= 1'd0;
main_sdram_bankmachine4_cmd_payload_is_write <= 1'd0;
builder_bankmachine4_next_state <= 3'd0;
main_sdram_bankmachine4_req_wdata_ready <= 1'd0;
main_sdram_bankmachine4_req_rdata_valid <= 1'd0;
main_sdram_bankmachine4_row_col_n_addr_sel <= 1'd0;
main_sdram_bankmachine4_refresh_gnt <= 1'd0;
main_sdram_bankmachine4_cmd_valid <= 1'd0;
builder_bankmachine4_next_state <= builder_bankmachine4_state;
case (builder_bankmachine4_state)
1'd1: begin
if ((main_sdram_bankmachine4_twtpcon_ready & main_sdram_bankmachine4_trascon_ready)) begin
main_sdram_bankmachine4_cmd_valid <= 1'd1;
if (main_sdram_bankmachine4_cmd_ready) begin
builder_bankmachine4_next_state <= 3'd5;
end
main_sdram_bankmachine4_cmd_payload_ras <= 1'd1;
main_sdram_bankmachine4_cmd_payload_we <= 1'd1;
main_sdram_bankmachine4_cmd_payload_is_cmd <= 1'd1;
end
main_sdram_bankmachine4_row_close <= 1'd1;
end
2'd2: begin
if ((main_sdram_bankmachine4_twtpcon_ready & main_sdram_bankmachine4_trascon_ready)) begin
builder_bankmachine4_next_state <= 3'd5;
end
main_sdram_bankmachine4_row_close <= 1'd1;
end
2'd3: begin
if (main_sdram_bankmachine4_trccon_ready) begin
main_sdram_bankmachine4_row_col_n_addr_sel <= 1'd1;
main_sdram_bankmachine4_row_open <= 1'd1;
main_sdram_bankmachine4_cmd_valid <= 1'd1;
main_sdram_bankmachine4_cmd_payload_is_cmd <= 1'd1;
if (main_sdram_bankmachine4_cmd_ready) begin
builder_bankmachine4_next_state <= 3'd6;
end
main_sdram_bankmachine4_cmd_payload_ras <= 1'd1;
end
end
3'd4: begin
if (main_sdram_bankmachine4_twtpcon_ready) begin
main_sdram_bankmachine4_refresh_gnt <= 1'd1;
end
main_sdram_bankmachine4_row_close <= 1'd1;
main_sdram_bankmachine4_cmd_payload_is_cmd <= 1'd1;
if ((~main_sdram_bankmachine4_refresh_req)) begin
builder_bankmachine4_next_state <= 1'd0;
end
end
3'd5: begin
builder_bankmachine4_next_state <= 2'd3;
end
3'd6: begin
builder_bankmachine4_next_state <= 1'd0;
end
default: begin
if (main_sdram_bankmachine4_refresh_req) begin
builder_bankmachine4_next_state <= 3'd4;
end else begin
if (main_sdram_bankmachine4_cmd_buffer_source_valid) begin
if (main_sdram_bankmachine4_row_opened) begin
if (main_sdram_bankmachine4_row_hit) begin
main_sdram_bankmachine4_cmd_valid <= 1'd1;
if (main_sdram_bankmachine4_cmd_buffer_source_payload_we) begin
main_sdram_bankmachine4_req_wdata_ready <= main_sdram_bankmachine4_cmd_ready;
main_sdram_bankmachine4_cmd_payload_is_write <= 1'd1;
main_sdram_bankmachine4_cmd_payload_we <= 1'd1;
end else begin
main_sdram_bankmachine4_req_rdata_valid <= main_sdram_bankmachine4_cmd_ready;
main_sdram_bankmachine4_cmd_payload_is_read <= 1'd1;
end
main_sdram_bankmachine4_cmd_payload_cas <= 1'd1;
if ((main_sdram_bankmachine4_cmd_ready & main_sdram_bankmachine4_auto_precharge)) begin
builder_bankmachine4_next_state <= 2'd2;
end
end else begin
builder_bankmachine4_next_state <= 1'd1;
end
end else begin
builder_bankmachine4_next_state <= 2'd3;
end
end
end
end
endcase
end
assign main_sdram_bankmachine5_cmd_buffer_lookahead_sink_valid = main_sdram_bankmachine5_req_valid;
assign main_sdram_bankmachine5_req_ready = main_sdram_bankmachine5_cmd_buffer_lookahead_sink_ready;
assign main_sdram_bankmachine5_cmd_buffer_lookahead_sink_payload_we = main_sdram_bankmachine5_req_we;
assign main_sdram_bankmachine5_cmd_buffer_lookahead_sink_payload_addr = main_sdram_bankmachine5_req_addr;
assign main_sdram_bankmachine5_cmd_buffer_sink_valid = main_sdram_bankmachine5_cmd_buffer_lookahead_source_valid;
assign main_sdram_bankmachine5_cmd_buffer_lookahead_source_ready = main_sdram_bankmachine5_cmd_buffer_sink_ready;
assign main_sdram_bankmachine5_cmd_buffer_sink_first = main_sdram_bankmachine5_cmd_buffer_lookahead_source_first;
assign main_sdram_bankmachine5_cmd_buffer_sink_last = main_sdram_bankmachine5_cmd_buffer_lookahead_source_last;
assign main_sdram_bankmachine5_cmd_buffer_sink_payload_we = main_sdram_bankmachine5_cmd_buffer_lookahead_source_payload_we;
assign main_sdram_bankmachine5_cmd_buffer_sink_payload_addr = main_sdram_bankmachine5_cmd_buffer_lookahead_source_payload_addr;
assign main_sdram_bankmachine5_cmd_buffer_source_ready = (main_sdram_bankmachine5_req_wdata_ready | main_sdram_bankmachine5_req_rdata_valid);
assign main_sdram_bankmachine5_req_lock = (main_sdram_bankmachine5_cmd_buffer_lookahead_source_valid | main_sdram_bankmachine5_cmd_buffer_source_valid);
assign main_sdram_bankmachine5_row_hit = (main_sdram_bankmachine5_row == main_sdram_bankmachine5_cmd_buffer_source_payload_addr[20:7]);
assign main_sdram_bankmachine5_cmd_payload_ba = 3'd5;
always @(*) begin
main_sdram_bankmachine5_cmd_payload_a <= 14'd0;
if (main_sdram_bankmachine5_row_col_n_addr_sel) begin
main_sdram_bankmachine5_cmd_payload_a <= main_sdram_bankmachine5_cmd_buffer_source_payload_addr[20:7];
end else begin
main_sdram_bankmachine5_cmd_payload_a <= ((main_sdram_bankmachine5_auto_precharge <<< 4'd10) | {main_sdram_bankmachine5_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
end
end
assign main_sdram_bankmachine5_twtpcon_valid = ((main_sdram_bankmachine5_cmd_valid & main_sdram_bankmachine5_cmd_ready) & main_sdram_bankmachine5_cmd_payload_is_write);
assign main_sdram_bankmachine5_trccon_valid = ((main_sdram_bankmachine5_cmd_valid & main_sdram_bankmachine5_cmd_ready) & main_sdram_bankmachine5_row_open);
assign main_sdram_bankmachine5_trascon_valid = ((main_sdram_bankmachine5_cmd_valid & main_sdram_bankmachine5_cmd_ready) & main_sdram_bankmachine5_row_open);
always @(*) begin
main_sdram_bankmachine5_auto_precharge <= 1'd0;
if ((main_sdram_bankmachine5_cmd_buffer_lookahead_source_valid & main_sdram_bankmachine5_cmd_buffer_source_valid)) begin
if ((main_sdram_bankmachine5_cmd_buffer_lookahead_source_payload_addr[20:7] != main_sdram_bankmachine5_cmd_buffer_source_payload_addr[20:7])) begin
main_sdram_bankmachine5_auto_precharge <= (main_sdram_bankmachine5_row_close == 1'd0);
end
end
end
assign main_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_din = {main_sdram_bankmachine5_cmd_buffer_lookahead_fifo_in_last, main_sdram_bankmachine5_cmd_buffer_lookahead_fifo_in_first, main_sdram_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_addr, main_sdram_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_we};
assign {main_sdram_bankmachine5_cmd_buffer_lookahead_fifo_out_last, main_sdram_bankmachine5_cmd_buffer_lookahead_fifo_out_first, main_sdram_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr, main_sdram_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we} = main_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout;
assign main_sdram_bankmachine5_cmd_buffer_lookahead_sink_ready = main_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable;
assign main_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_we = main_sdram_bankmachine5_cmd_buffer_lookahead_sink_valid;
assign main_sdram_bankmachine5_cmd_buffer_lookahead_fifo_in_first = main_sdram_bankmachine5_cmd_buffer_lookahead_sink_first;
assign main_sdram_bankmachine5_cmd_buffer_lookahead_fifo_in_last = main_sdram_bankmachine5_cmd_buffer_lookahead_sink_last;
assign main_sdram_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_we = main_sdram_bankmachine5_cmd_buffer_lookahead_sink_payload_we;
assign main_sdram_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_addr = main_sdram_bankmachine5_cmd_buffer_lookahead_sink_payload_addr;
assign main_sdram_bankmachine5_cmd_buffer_lookahead_source_valid = main_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_readable;
assign main_sdram_bankmachine5_cmd_buffer_lookahead_source_first = main_sdram_bankmachine5_cmd_buffer_lookahead_fifo_out_first;
assign main_sdram_bankmachine5_cmd_buffer_lookahead_source_last = main_sdram_bankmachine5_cmd_buffer_lookahead_fifo_out_last;
assign main_sdram_bankmachine5_cmd_buffer_lookahead_source_payload_we = main_sdram_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we;
assign main_sdram_bankmachine5_cmd_buffer_lookahead_source_payload_addr = main_sdram_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr;
assign main_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_re = main_sdram_bankmachine5_cmd_buffer_lookahead_source_ready;
always @(*) begin
main_sdram_bankmachine5_cmd_buffer_lookahead_wrport_adr <= 3'd0;
if (main_sdram_bankmachine5_cmd_buffer_lookahead_replace) begin
main_sdram_bankmachine5_cmd_buffer_lookahead_wrport_adr <= (main_sdram_bankmachine5_cmd_buffer_lookahead_produce - 1'd1);
end else begin
main_sdram_bankmachine5_cmd_buffer_lookahead_wrport_adr <= main_sdram_bankmachine5_cmd_buffer_lookahead_produce;
end
end
assign main_sdram_bankmachine5_cmd_buffer_lookahead_wrport_dat_w = main_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_din;
assign main_sdram_bankmachine5_cmd_buffer_lookahead_wrport_we = (main_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_we & (main_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable | main_sdram_bankmachine5_cmd_buffer_lookahead_replace));
assign main_sdram_bankmachine5_cmd_buffer_lookahead_do_read = (main_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_readable & main_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_re);
assign main_sdram_bankmachine5_cmd_buffer_lookahead_rdport_adr = main_sdram_bankmachine5_cmd_buffer_lookahead_consume;
assign main_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout = main_sdram_bankmachine5_cmd_buffer_lookahead_rdport_dat_r;
assign main_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable = (main_sdram_bankmachine5_cmd_buffer_lookahead_level != 4'd8);
assign main_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_readable = (main_sdram_bankmachine5_cmd_buffer_lookahead_level != 1'd0);
assign main_sdram_bankmachine5_cmd_buffer_pipe_ce = (main_sdram_bankmachine5_cmd_buffer_source_ready | (~main_sdram_bankmachine5_cmd_buffer_valid_n));
assign main_sdram_bankmachine5_cmd_buffer_sink_ready = main_sdram_bankmachine5_cmd_buffer_pipe_ce;
assign main_sdram_bankmachine5_cmd_buffer_source_valid = main_sdram_bankmachine5_cmd_buffer_valid_n;
assign main_sdram_bankmachine5_cmd_buffer_busy = (1'd0 | main_sdram_bankmachine5_cmd_buffer_valid_n);
assign main_sdram_bankmachine5_cmd_buffer_source_first = main_sdram_bankmachine5_cmd_buffer_first_n;
assign main_sdram_bankmachine5_cmd_buffer_source_last = main_sdram_bankmachine5_cmd_buffer_last_n;
always @(*) begin
main_sdram_bankmachine5_cmd_valid <= 1'd0;
builder_bankmachine5_next_state <= 3'd0;
main_sdram_bankmachine5_cmd_payload_cas <= 1'd0;
main_sdram_bankmachine5_cmd_payload_ras <= 1'd0;
main_sdram_bankmachine5_cmd_payload_we <= 1'd0;
main_sdram_bankmachine5_cmd_payload_is_cmd <= 1'd0;
main_sdram_bankmachine5_row_open <= 1'd0;
main_sdram_bankmachine5_cmd_payload_is_read <= 1'd0;
main_sdram_bankmachine5_row_close <= 1'd0;
main_sdram_bankmachine5_cmd_payload_is_write <= 1'd0;
main_sdram_bankmachine5_req_wdata_ready <= 1'd0;
main_sdram_bankmachine5_req_rdata_valid <= 1'd0;
main_sdram_bankmachine5_row_col_n_addr_sel <= 1'd0;
main_sdram_bankmachine5_refresh_gnt <= 1'd0;
builder_bankmachine5_next_state <= builder_bankmachine5_state;
case (builder_bankmachine5_state)
1'd1: begin
if ((main_sdram_bankmachine5_twtpcon_ready & main_sdram_bankmachine5_trascon_ready)) begin
main_sdram_bankmachine5_cmd_valid <= 1'd1;
if (main_sdram_bankmachine5_cmd_ready) begin
builder_bankmachine5_next_state <= 3'd5;
end
main_sdram_bankmachine5_cmd_payload_ras <= 1'd1;
main_sdram_bankmachine5_cmd_payload_we <= 1'd1;
main_sdram_bankmachine5_cmd_payload_is_cmd <= 1'd1;
end
main_sdram_bankmachine5_row_close <= 1'd1;
end
2'd2: begin
if ((main_sdram_bankmachine5_twtpcon_ready & main_sdram_bankmachine5_trascon_ready)) begin
builder_bankmachine5_next_state <= 3'd5;
end
main_sdram_bankmachine5_row_close <= 1'd1;
end
2'd3: begin
if (main_sdram_bankmachine5_trccon_ready) begin
main_sdram_bankmachine5_row_col_n_addr_sel <= 1'd1;
main_sdram_bankmachine5_row_open <= 1'd1;
main_sdram_bankmachine5_cmd_valid <= 1'd1;
main_sdram_bankmachine5_cmd_payload_is_cmd <= 1'd1;
if (main_sdram_bankmachine5_cmd_ready) begin
builder_bankmachine5_next_state <= 3'd6;
end
main_sdram_bankmachine5_cmd_payload_ras <= 1'd1;
end
end
3'd4: begin
if (main_sdram_bankmachine5_twtpcon_ready) begin
main_sdram_bankmachine5_refresh_gnt <= 1'd1;
end
main_sdram_bankmachine5_row_close <= 1'd1;
main_sdram_bankmachine5_cmd_payload_is_cmd <= 1'd1;
if ((~main_sdram_bankmachine5_refresh_req)) begin
builder_bankmachine5_next_state <= 1'd0;
end
end
3'd5: begin
builder_bankmachine5_next_state <= 2'd3;
end
3'd6: begin
builder_bankmachine5_next_state <= 1'd0;
end
default: begin
if (main_sdram_bankmachine5_refresh_req) begin
builder_bankmachine5_next_state <= 3'd4;
end else begin
if (main_sdram_bankmachine5_cmd_buffer_source_valid) begin
if (main_sdram_bankmachine5_row_opened) begin
if (main_sdram_bankmachine5_row_hit) begin
main_sdram_bankmachine5_cmd_valid <= 1'd1;
if (main_sdram_bankmachine5_cmd_buffer_source_payload_we) begin
main_sdram_bankmachine5_req_wdata_ready <= main_sdram_bankmachine5_cmd_ready;
main_sdram_bankmachine5_cmd_payload_is_write <= 1'd1;
main_sdram_bankmachine5_cmd_payload_we <= 1'd1;
end else begin
main_sdram_bankmachine5_req_rdata_valid <= main_sdram_bankmachine5_cmd_ready;
main_sdram_bankmachine5_cmd_payload_is_read <= 1'd1;
end
main_sdram_bankmachine5_cmd_payload_cas <= 1'd1;
if ((main_sdram_bankmachine5_cmd_ready & main_sdram_bankmachine5_auto_precharge)) begin
builder_bankmachine5_next_state <= 2'd2;
end
end else begin
builder_bankmachine5_next_state <= 1'd1;
end
end else begin
builder_bankmachine5_next_state <= 2'd3;
end
end
end
end
endcase
end
assign main_sdram_bankmachine6_cmd_buffer_lookahead_sink_valid = main_sdram_bankmachine6_req_valid;
assign main_sdram_bankmachine6_req_ready = main_sdram_bankmachine6_cmd_buffer_lookahead_sink_ready;
assign main_sdram_bankmachine6_cmd_buffer_lookahead_sink_payload_we = main_sdram_bankmachine6_req_we;
assign main_sdram_bankmachine6_cmd_buffer_lookahead_sink_payload_addr = main_sdram_bankmachine6_req_addr;
assign main_sdram_bankmachine6_cmd_buffer_sink_valid = main_sdram_bankmachine6_cmd_buffer_lookahead_source_valid;
assign main_sdram_bankmachine6_cmd_buffer_lookahead_source_ready = main_sdram_bankmachine6_cmd_buffer_sink_ready;
assign main_sdram_bankmachine6_cmd_buffer_sink_first = main_sdram_bankmachine6_cmd_buffer_lookahead_source_first;
assign main_sdram_bankmachine6_cmd_buffer_sink_last = main_sdram_bankmachine6_cmd_buffer_lookahead_source_last;
assign main_sdram_bankmachine6_cmd_buffer_sink_payload_we = main_sdram_bankmachine6_cmd_buffer_lookahead_source_payload_we;
assign main_sdram_bankmachine6_cmd_buffer_sink_payload_addr = main_sdram_bankmachine6_cmd_buffer_lookahead_source_payload_addr;
assign main_sdram_bankmachine6_cmd_buffer_source_ready = (main_sdram_bankmachine6_req_wdata_ready | main_sdram_bankmachine6_req_rdata_valid);
assign main_sdram_bankmachine6_req_lock = (main_sdram_bankmachine6_cmd_buffer_lookahead_source_valid | main_sdram_bankmachine6_cmd_buffer_source_valid);
assign main_sdram_bankmachine6_row_hit = (main_sdram_bankmachine6_row == main_sdram_bankmachine6_cmd_buffer_source_payload_addr[20:7]);
assign main_sdram_bankmachine6_cmd_payload_ba = 3'd6;
always @(*) begin
main_sdram_bankmachine6_cmd_payload_a <= 14'd0;
if (main_sdram_bankmachine6_row_col_n_addr_sel) begin
main_sdram_bankmachine6_cmd_payload_a <= main_sdram_bankmachine6_cmd_buffer_source_payload_addr[20:7];
end else begin
main_sdram_bankmachine6_cmd_payload_a <= ((main_sdram_bankmachine6_auto_precharge <<< 4'd10) | {main_sdram_bankmachine6_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
end
end
assign main_sdram_bankmachine6_twtpcon_valid = ((main_sdram_bankmachine6_cmd_valid & main_sdram_bankmachine6_cmd_ready) & main_sdram_bankmachine6_cmd_payload_is_write);
assign main_sdram_bankmachine6_trccon_valid = ((main_sdram_bankmachine6_cmd_valid & main_sdram_bankmachine6_cmd_ready) & main_sdram_bankmachine6_row_open);
assign main_sdram_bankmachine6_trascon_valid = ((main_sdram_bankmachine6_cmd_valid & main_sdram_bankmachine6_cmd_ready) & main_sdram_bankmachine6_row_open);
always @(*) begin
main_sdram_bankmachine6_auto_precharge <= 1'd0;
if ((main_sdram_bankmachine6_cmd_buffer_lookahead_source_valid & main_sdram_bankmachine6_cmd_buffer_source_valid)) begin
if ((main_sdram_bankmachine6_cmd_buffer_lookahead_source_payload_addr[20:7] != main_sdram_bankmachine6_cmd_buffer_source_payload_addr[20:7])) begin
main_sdram_bankmachine6_auto_precharge <= (main_sdram_bankmachine6_row_close == 1'd0);
end
end
end
assign main_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_din = {main_sdram_bankmachine6_cmd_buffer_lookahead_fifo_in_last, main_sdram_bankmachine6_cmd_buffer_lookahead_fifo_in_first, main_sdram_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_addr, main_sdram_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_we};
assign {main_sdram_bankmachine6_cmd_buffer_lookahead_fifo_out_last, main_sdram_bankmachine6_cmd_buffer_lookahead_fifo_out_first, main_sdram_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr, main_sdram_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we} = main_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout;
assign main_sdram_bankmachine6_cmd_buffer_lookahead_sink_ready = main_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable;
assign main_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_we = main_sdram_bankmachine6_cmd_buffer_lookahead_sink_valid;
assign main_sdram_bankmachine6_cmd_buffer_lookahead_fifo_in_first = main_sdram_bankmachine6_cmd_buffer_lookahead_sink_first;
assign main_sdram_bankmachine6_cmd_buffer_lookahead_fifo_in_last = main_sdram_bankmachine6_cmd_buffer_lookahead_sink_last;
assign main_sdram_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_we = main_sdram_bankmachine6_cmd_buffer_lookahead_sink_payload_we;
assign main_sdram_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_addr = main_sdram_bankmachine6_cmd_buffer_lookahead_sink_payload_addr;
assign main_sdram_bankmachine6_cmd_buffer_lookahead_source_valid = main_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_readable;
assign main_sdram_bankmachine6_cmd_buffer_lookahead_source_first = main_sdram_bankmachine6_cmd_buffer_lookahead_fifo_out_first;
assign main_sdram_bankmachine6_cmd_buffer_lookahead_source_last = main_sdram_bankmachine6_cmd_buffer_lookahead_fifo_out_last;
assign main_sdram_bankmachine6_cmd_buffer_lookahead_source_payload_we = main_sdram_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we;
assign main_sdram_bankmachine6_cmd_buffer_lookahead_source_payload_addr = main_sdram_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr;
assign main_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_re = main_sdram_bankmachine6_cmd_buffer_lookahead_source_ready;
always @(*) begin
main_sdram_bankmachine6_cmd_buffer_lookahead_wrport_adr <= 3'd0;
if (main_sdram_bankmachine6_cmd_buffer_lookahead_replace) begin
main_sdram_bankmachine6_cmd_buffer_lookahead_wrport_adr <= (main_sdram_bankmachine6_cmd_buffer_lookahead_produce - 1'd1);
end else begin
main_sdram_bankmachine6_cmd_buffer_lookahead_wrport_adr <= main_sdram_bankmachine6_cmd_buffer_lookahead_produce;
end
end
assign main_sdram_bankmachine6_cmd_buffer_lookahead_wrport_dat_w = main_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_din;
assign main_sdram_bankmachine6_cmd_buffer_lookahead_wrport_we = (main_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_we & (main_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable | main_sdram_bankmachine6_cmd_buffer_lookahead_replace));
assign main_sdram_bankmachine6_cmd_buffer_lookahead_do_read = (main_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_readable & main_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_re);
assign main_sdram_bankmachine6_cmd_buffer_lookahead_rdport_adr = main_sdram_bankmachine6_cmd_buffer_lookahead_consume;
assign main_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout = main_sdram_bankmachine6_cmd_buffer_lookahead_rdport_dat_r;
assign main_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable = (main_sdram_bankmachine6_cmd_buffer_lookahead_level != 4'd8);
assign main_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_readable = (main_sdram_bankmachine6_cmd_buffer_lookahead_level != 1'd0);
assign main_sdram_bankmachine6_cmd_buffer_pipe_ce = (main_sdram_bankmachine6_cmd_buffer_source_ready | (~main_sdram_bankmachine6_cmd_buffer_valid_n));
assign main_sdram_bankmachine6_cmd_buffer_sink_ready = main_sdram_bankmachine6_cmd_buffer_pipe_ce;
assign main_sdram_bankmachine6_cmd_buffer_source_valid = main_sdram_bankmachine6_cmd_buffer_valid_n;
assign main_sdram_bankmachine6_cmd_buffer_busy = (1'd0 | main_sdram_bankmachine6_cmd_buffer_valid_n);
assign main_sdram_bankmachine6_cmd_buffer_source_first = main_sdram_bankmachine6_cmd_buffer_first_n;
assign main_sdram_bankmachine6_cmd_buffer_source_last = main_sdram_bankmachine6_cmd_buffer_last_n;
always @(*) begin
main_sdram_bankmachine6_row_open <= 1'd0;
main_sdram_bankmachine6_cmd_payload_is_read <= 1'd0;
main_sdram_bankmachine6_row_close <= 1'd0;
main_sdram_bankmachine6_cmd_payload_is_write <= 1'd0;
builder_bankmachine6_next_state <= 3'd0;
main_sdram_bankmachine6_req_wdata_ready <= 1'd0;
main_sdram_bankmachine6_req_rdata_valid <= 1'd0;
main_sdram_bankmachine6_row_col_n_addr_sel <= 1'd0;
main_sdram_bankmachine6_refresh_gnt <= 1'd0;
main_sdram_bankmachine6_cmd_valid <= 1'd0;
main_sdram_bankmachine6_cmd_payload_cas <= 1'd0;
main_sdram_bankmachine6_cmd_payload_ras <= 1'd0;
main_sdram_bankmachine6_cmd_payload_we <= 1'd0;
main_sdram_bankmachine6_cmd_payload_is_cmd <= 1'd0;
builder_bankmachine6_next_state <= builder_bankmachine6_state;
case (builder_bankmachine6_state)
1'd1: begin
if ((main_sdram_bankmachine6_twtpcon_ready & main_sdram_bankmachine6_trascon_ready)) begin
main_sdram_bankmachine6_cmd_valid <= 1'd1;
if (main_sdram_bankmachine6_cmd_ready) begin
builder_bankmachine6_next_state <= 3'd5;
end
main_sdram_bankmachine6_cmd_payload_ras <= 1'd1;
main_sdram_bankmachine6_cmd_payload_we <= 1'd1;
main_sdram_bankmachine6_cmd_payload_is_cmd <= 1'd1;
end
main_sdram_bankmachine6_row_close <= 1'd1;
end
2'd2: begin
if ((main_sdram_bankmachine6_twtpcon_ready & main_sdram_bankmachine6_trascon_ready)) begin
builder_bankmachine6_next_state <= 3'd5;
end
main_sdram_bankmachine6_row_close <= 1'd1;
end
2'd3: begin
if (main_sdram_bankmachine6_trccon_ready) begin
main_sdram_bankmachine6_row_col_n_addr_sel <= 1'd1;
main_sdram_bankmachine6_row_open <= 1'd1;
main_sdram_bankmachine6_cmd_valid <= 1'd1;
main_sdram_bankmachine6_cmd_payload_is_cmd <= 1'd1;
if (main_sdram_bankmachine6_cmd_ready) begin
builder_bankmachine6_next_state <= 3'd6;
end
main_sdram_bankmachine6_cmd_payload_ras <= 1'd1;
end
end
3'd4: begin
if (main_sdram_bankmachine6_twtpcon_ready) begin
main_sdram_bankmachine6_refresh_gnt <= 1'd1;
end
main_sdram_bankmachine6_row_close <= 1'd1;
main_sdram_bankmachine6_cmd_payload_is_cmd <= 1'd1;
if ((~main_sdram_bankmachine6_refresh_req)) begin
builder_bankmachine6_next_state <= 1'd0;
end
end
3'd5: begin
builder_bankmachine6_next_state <= 2'd3;
end
3'd6: begin
builder_bankmachine6_next_state <= 1'd0;
end
default: begin
if (main_sdram_bankmachine6_refresh_req) begin
builder_bankmachine6_next_state <= 3'd4;
end else begin
if (main_sdram_bankmachine6_cmd_buffer_source_valid) begin
if (main_sdram_bankmachine6_row_opened) begin
if (main_sdram_bankmachine6_row_hit) begin
main_sdram_bankmachine6_cmd_valid <= 1'd1;
if (main_sdram_bankmachine6_cmd_buffer_source_payload_we) begin
main_sdram_bankmachine6_req_wdata_ready <= main_sdram_bankmachine6_cmd_ready;
main_sdram_bankmachine6_cmd_payload_is_write <= 1'd1;
main_sdram_bankmachine6_cmd_payload_we <= 1'd1;
end else begin
main_sdram_bankmachine6_req_rdata_valid <= main_sdram_bankmachine6_cmd_ready;
main_sdram_bankmachine6_cmd_payload_is_read <= 1'd1;
end
main_sdram_bankmachine6_cmd_payload_cas <= 1'd1;
if ((main_sdram_bankmachine6_cmd_ready & main_sdram_bankmachine6_auto_precharge)) begin
builder_bankmachine6_next_state <= 2'd2;
end
end else begin
builder_bankmachine6_next_state <= 1'd1;
end
end else begin
builder_bankmachine6_next_state <= 2'd3;
end
end
end
end
endcase
end
assign main_sdram_bankmachine7_cmd_buffer_lookahead_sink_valid = main_sdram_bankmachine7_req_valid;
assign main_sdram_bankmachine7_req_ready = main_sdram_bankmachine7_cmd_buffer_lookahead_sink_ready;
assign main_sdram_bankmachine7_cmd_buffer_lookahead_sink_payload_we = main_sdram_bankmachine7_req_we;
assign main_sdram_bankmachine7_cmd_buffer_lookahead_sink_payload_addr = main_sdram_bankmachine7_req_addr;
assign main_sdram_bankmachine7_cmd_buffer_sink_valid = main_sdram_bankmachine7_cmd_buffer_lookahead_source_valid;
assign main_sdram_bankmachine7_cmd_buffer_lookahead_source_ready = main_sdram_bankmachine7_cmd_buffer_sink_ready;
assign main_sdram_bankmachine7_cmd_buffer_sink_first = main_sdram_bankmachine7_cmd_buffer_lookahead_source_first;
assign main_sdram_bankmachine7_cmd_buffer_sink_last = main_sdram_bankmachine7_cmd_buffer_lookahead_source_last;
assign main_sdram_bankmachine7_cmd_buffer_sink_payload_we = main_sdram_bankmachine7_cmd_buffer_lookahead_source_payload_we;
assign main_sdram_bankmachine7_cmd_buffer_sink_payload_addr = main_sdram_bankmachine7_cmd_buffer_lookahead_source_payload_addr;
assign main_sdram_bankmachine7_cmd_buffer_source_ready = (main_sdram_bankmachine7_req_wdata_ready | main_sdram_bankmachine7_req_rdata_valid);
assign main_sdram_bankmachine7_req_lock = (main_sdram_bankmachine7_cmd_buffer_lookahead_source_valid | main_sdram_bankmachine7_cmd_buffer_source_valid);
assign main_sdram_bankmachine7_row_hit = (main_sdram_bankmachine7_row == main_sdram_bankmachine7_cmd_buffer_source_payload_addr[20:7]);
assign main_sdram_bankmachine7_cmd_payload_ba = 3'd7;
always @(*) begin
main_sdram_bankmachine7_cmd_payload_a <= 14'd0;
if (main_sdram_bankmachine7_row_col_n_addr_sel) begin
main_sdram_bankmachine7_cmd_payload_a <= main_sdram_bankmachine7_cmd_buffer_source_payload_addr[20:7];
end else begin
main_sdram_bankmachine7_cmd_payload_a <= ((main_sdram_bankmachine7_auto_precharge <<< 4'd10) | {main_sdram_bankmachine7_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
end
end
assign main_sdram_bankmachine7_twtpcon_valid = ((main_sdram_bankmachine7_cmd_valid & main_sdram_bankmachine7_cmd_ready) & main_sdram_bankmachine7_cmd_payload_is_write);
assign main_sdram_bankmachine7_trccon_valid = ((main_sdram_bankmachine7_cmd_valid & main_sdram_bankmachine7_cmd_ready) & main_sdram_bankmachine7_row_open);
assign main_sdram_bankmachine7_trascon_valid = ((main_sdram_bankmachine7_cmd_valid & main_sdram_bankmachine7_cmd_ready) & main_sdram_bankmachine7_row_open);
always @(*) begin
main_sdram_bankmachine7_auto_precharge <= 1'd0;
if ((main_sdram_bankmachine7_cmd_buffer_lookahead_source_valid & main_sdram_bankmachine7_cmd_buffer_source_valid)) begin
if ((main_sdram_bankmachine7_cmd_buffer_lookahead_source_payload_addr[20:7] != main_sdram_bankmachine7_cmd_buffer_source_payload_addr[20:7])) begin
main_sdram_bankmachine7_auto_precharge <= (main_sdram_bankmachine7_row_close == 1'd0);
end
end
end
assign main_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_din = {main_sdram_bankmachine7_cmd_buffer_lookahead_fifo_in_last, main_sdram_bankmachine7_cmd_buffer_lookahead_fifo_in_first, main_sdram_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_addr, main_sdram_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_we};
assign {main_sdram_bankmachine7_cmd_buffer_lookahead_fifo_out_last, main_sdram_bankmachine7_cmd_buffer_lookahead_fifo_out_first, main_sdram_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr, main_sdram_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we} = main_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout;
assign main_sdram_bankmachine7_cmd_buffer_lookahead_sink_ready = main_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable;
assign main_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_we = main_sdram_bankmachine7_cmd_buffer_lookahead_sink_valid;
assign main_sdram_bankmachine7_cmd_buffer_lookahead_fifo_in_first = main_sdram_bankmachine7_cmd_buffer_lookahead_sink_first;
assign main_sdram_bankmachine7_cmd_buffer_lookahead_fifo_in_last = main_sdram_bankmachine7_cmd_buffer_lookahead_sink_last;
assign main_sdram_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_we = main_sdram_bankmachine7_cmd_buffer_lookahead_sink_payload_we;
assign main_sdram_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_addr = main_sdram_bankmachine7_cmd_buffer_lookahead_sink_payload_addr;
assign main_sdram_bankmachine7_cmd_buffer_lookahead_source_valid = main_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_readable;
assign main_sdram_bankmachine7_cmd_buffer_lookahead_source_first = main_sdram_bankmachine7_cmd_buffer_lookahead_fifo_out_first;
assign main_sdram_bankmachine7_cmd_buffer_lookahead_source_last = main_sdram_bankmachine7_cmd_buffer_lookahead_fifo_out_last;
assign main_sdram_bankmachine7_cmd_buffer_lookahead_source_payload_we = main_sdram_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we;
assign main_sdram_bankmachine7_cmd_buffer_lookahead_source_payload_addr = main_sdram_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr;
assign main_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_re = main_sdram_bankmachine7_cmd_buffer_lookahead_source_ready;
always @(*) begin
main_sdram_bankmachine7_cmd_buffer_lookahead_wrport_adr <= 3'd0;
if (main_sdram_bankmachine7_cmd_buffer_lookahead_replace) begin
main_sdram_bankmachine7_cmd_buffer_lookahead_wrport_adr <= (main_sdram_bankmachine7_cmd_buffer_lookahead_produce - 1'd1);
end else begin
main_sdram_bankmachine7_cmd_buffer_lookahead_wrport_adr <= main_sdram_bankmachine7_cmd_buffer_lookahead_produce;
end
end
assign main_sdram_bankmachine7_cmd_buffer_lookahead_wrport_dat_w = main_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_din;
assign main_sdram_bankmachine7_cmd_buffer_lookahead_wrport_we = (main_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_we & (main_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable | main_sdram_bankmachine7_cmd_buffer_lookahead_replace));
assign main_sdram_bankmachine7_cmd_buffer_lookahead_do_read = (main_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_readable & main_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_re);
assign main_sdram_bankmachine7_cmd_buffer_lookahead_rdport_adr = main_sdram_bankmachine7_cmd_buffer_lookahead_consume;
assign main_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout = main_sdram_bankmachine7_cmd_buffer_lookahead_rdport_dat_r;
assign main_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable = (main_sdram_bankmachine7_cmd_buffer_lookahead_level != 4'd8);
assign main_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_readable = (main_sdram_bankmachine7_cmd_buffer_lookahead_level != 1'd0);
assign main_sdram_bankmachine7_cmd_buffer_pipe_ce = (main_sdram_bankmachine7_cmd_buffer_source_ready | (~main_sdram_bankmachine7_cmd_buffer_valid_n));
assign main_sdram_bankmachine7_cmd_buffer_sink_ready = main_sdram_bankmachine7_cmd_buffer_pipe_ce;
assign main_sdram_bankmachine7_cmd_buffer_source_valid = main_sdram_bankmachine7_cmd_buffer_valid_n;
assign main_sdram_bankmachine7_cmd_buffer_busy = (1'd0 | main_sdram_bankmachine7_cmd_buffer_valid_n);
assign main_sdram_bankmachine7_cmd_buffer_source_first = main_sdram_bankmachine7_cmd_buffer_first_n;
assign main_sdram_bankmachine7_cmd_buffer_source_last = main_sdram_bankmachine7_cmd_buffer_last_n;
always @(*) begin
builder_bankmachine7_next_state <= 3'd0;
main_sdram_bankmachine7_cmd_payload_cas <= 1'd0;
main_sdram_bankmachine7_cmd_payload_ras <= 1'd0;
main_sdram_bankmachine7_cmd_payload_we <= 1'd0;
main_sdram_bankmachine7_cmd_payload_is_cmd <= 1'd0;
main_sdram_bankmachine7_row_open <= 1'd0;
main_sdram_bankmachine7_cmd_payload_is_read <= 1'd0;
main_sdram_bankmachine7_row_close <= 1'd0;
main_sdram_bankmachine7_cmd_payload_is_write <= 1'd0;
main_sdram_bankmachine7_req_wdata_ready <= 1'd0;
main_sdram_bankmachine7_req_rdata_valid <= 1'd0;
main_sdram_bankmachine7_row_col_n_addr_sel <= 1'd0;
main_sdram_bankmachine7_refresh_gnt <= 1'd0;
main_sdram_bankmachine7_cmd_valid <= 1'd0;
builder_bankmachine7_next_state <= builder_bankmachine7_state;
case (builder_bankmachine7_state)
1'd1: begin
if ((main_sdram_bankmachine7_twtpcon_ready & main_sdram_bankmachine7_trascon_ready)) begin
main_sdram_bankmachine7_cmd_valid <= 1'd1;
if (main_sdram_bankmachine7_cmd_ready) begin
builder_bankmachine7_next_state <= 3'd5;
end
main_sdram_bankmachine7_cmd_payload_ras <= 1'd1;
main_sdram_bankmachine7_cmd_payload_we <= 1'd1;
main_sdram_bankmachine7_cmd_payload_is_cmd <= 1'd1;
end
main_sdram_bankmachine7_row_close <= 1'd1;
end
2'd2: begin
if ((main_sdram_bankmachine7_twtpcon_ready & main_sdram_bankmachine7_trascon_ready)) begin
builder_bankmachine7_next_state <= 3'd5;
end
main_sdram_bankmachine7_row_close <= 1'd1;
end
2'd3: begin
if (main_sdram_bankmachine7_trccon_ready) begin
main_sdram_bankmachine7_row_col_n_addr_sel <= 1'd1;
main_sdram_bankmachine7_row_open <= 1'd1;
main_sdram_bankmachine7_cmd_valid <= 1'd1;
main_sdram_bankmachine7_cmd_payload_is_cmd <= 1'd1;
if (main_sdram_bankmachine7_cmd_ready) begin
builder_bankmachine7_next_state <= 3'd6;
end
main_sdram_bankmachine7_cmd_payload_ras <= 1'd1;
end
end
3'd4: begin
if (main_sdram_bankmachine7_twtpcon_ready) begin
main_sdram_bankmachine7_refresh_gnt <= 1'd1;
end
main_sdram_bankmachine7_row_close <= 1'd1;
main_sdram_bankmachine7_cmd_payload_is_cmd <= 1'd1;
if ((~main_sdram_bankmachine7_refresh_req)) begin
builder_bankmachine7_next_state <= 1'd0;
end
end
3'd5: begin
builder_bankmachine7_next_state <= 2'd3;
end
3'd6: begin
builder_bankmachine7_next_state <= 1'd0;
end
default: begin
if (main_sdram_bankmachine7_refresh_req) begin
builder_bankmachine7_next_state <= 3'd4;
end else begin
if (main_sdram_bankmachine7_cmd_buffer_source_valid) begin
if (main_sdram_bankmachine7_row_opened) begin
if (main_sdram_bankmachine7_row_hit) begin
main_sdram_bankmachine7_cmd_valid <= 1'd1;
if (main_sdram_bankmachine7_cmd_buffer_source_payload_we) begin
main_sdram_bankmachine7_req_wdata_ready <= main_sdram_bankmachine7_cmd_ready;
main_sdram_bankmachine7_cmd_payload_is_write <= 1'd1;
main_sdram_bankmachine7_cmd_payload_we <= 1'd1;
end else begin
main_sdram_bankmachine7_req_rdata_valid <= main_sdram_bankmachine7_cmd_ready;
main_sdram_bankmachine7_cmd_payload_is_read <= 1'd1;
end
main_sdram_bankmachine7_cmd_payload_cas <= 1'd1;
if ((main_sdram_bankmachine7_cmd_ready & main_sdram_bankmachine7_auto_precharge)) begin
builder_bankmachine7_next_state <= 2'd2;
end
end else begin
builder_bankmachine7_next_state <= 1'd1;
end
end else begin
builder_bankmachine7_next_state <= 2'd3;
end
end
end
end
endcase
end
assign main_sdram_trrdcon_valid = ((main_sdram_choose_cmd_cmd_valid & main_sdram_choose_cmd_cmd_ready) & ((main_sdram_choose_cmd_cmd_payload_ras & (~main_sdram_choose_cmd_cmd_payload_cas)) & (~main_sdram_choose_cmd_cmd_payload_we)));
assign main_sdram_tfawcon_valid = ((main_sdram_choose_cmd_cmd_valid & main_sdram_choose_cmd_cmd_ready) & ((main_sdram_choose_cmd_cmd_payload_ras & (~main_sdram_choose_cmd_cmd_payload_cas)) & (~main_sdram_choose_cmd_cmd_payload_we)));
assign main_sdram_ras_allowed = (main_sdram_trrdcon_ready & main_sdram_tfawcon_ready);
assign main_sdram_tccdcon_valid = ((main_sdram_choose_req_cmd_valid & main_sdram_choose_req_cmd_ready) & (main_sdram_choose_req_cmd_payload_is_write | main_sdram_choose_req_cmd_payload_is_read));
assign main_sdram_cas_allowed = main_sdram_tccdcon_ready;
assign main_sdram_twtrcon_valid = ((main_sdram_choose_req_cmd_valid & main_sdram_choose_req_cmd_ready) & main_sdram_choose_req_cmd_payload_is_write);
assign main_sdram_read_available = ((((((((main_sdram_bankmachine0_cmd_valid & main_sdram_bankmachine0_cmd_payload_is_read) | (main_sdram_bankmachine1_cmd_valid & main_sdram_bankmachine1_cmd_payload_is_read)) | (main_sdram_bankmachine2_cmd_valid & main_sdram_bankmachine2_cmd_payload_is_read)) | (main_sdram_bankmachine3_cmd_valid & main_sdram_bankmachine3_cmd_payload_is_read)) | (main_sdram_bankmachine4_cmd_valid & main_sdram_bankmachine4_cmd_payload_is_read)) | (main_sdram_bankmachine5_cmd_valid & main_sdram_bankmachine5_cmd_payload_is_read)) | (main_sdram_bankmachine6_cmd_valid & main_sdram_bankmachine6_cmd_payload_is_read)) | (main_sdram_bankmachine7_cmd_valid & main_sdram_bankmachine7_cmd_payload_is_read));
assign main_sdram_write_available = ((((((((main_sdram_bankmachine0_cmd_valid & main_sdram_bankmachine0_cmd_payload_is_write) | (main_sdram_bankmachine1_cmd_valid & main_sdram_bankmachine1_cmd_payload_is_write)) | (main_sdram_bankmachine2_cmd_valid & main_sdram_bankmachine2_cmd_payload_is_write)) | (main_sdram_bankmachine3_cmd_valid & main_sdram_bankmachine3_cmd_payload_is_write)) | (main_sdram_bankmachine4_cmd_valid & main_sdram_bankmachine4_cmd_payload_is_write)) | (main_sdram_bankmachine5_cmd_valid & main_sdram_bankmachine5_cmd_payload_is_write)) | (main_sdram_bankmachine6_cmd_valid & main_sdram_bankmachine6_cmd_payload_is_write)) | (main_sdram_bankmachine7_cmd_valid & main_sdram_bankmachine7_cmd_payload_is_write));
assign main_sdram_max_time0 = (main_sdram_time0 == 1'd0);
assign main_sdram_max_time1 = (main_sdram_time1 == 1'd0);
assign main_sdram_bankmachine0_refresh_req = main_sdram_cmd_valid;
assign main_sdram_bankmachine1_refresh_req = main_sdram_cmd_valid;
assign main_sdram_bankmachine2_refresh_req = main_sdram_cmd_valid;
assign main_sdram_bankmachine3_refresh_req = main_sdram_cmd_valid;
assign main_sdram_bankmachine4_refresh_req = main_sdram_cmd_valid;
assign main_sdram_bankmachine5_refresh_req = main_sdram_cmd_valid;
assign main_sdram_bankmachine6_refresh_req = main_sdram_cmd_valid;
assign main_sdram_bankmachine7_refresh_req = main_sdram_cmd_valid;
assign main_sdram_go_to_refresh = (((((((main_sdram_bankmachine0_refresh_gnt & main_sdram_bankmachine1_refresh_gnt) & main_sdram_bankmachine2_refresh_gnt) & main_sdram_bankmachine3_refresh_gnt) & main_sdram_bankmachine4_refresh_gnt) & main_sdram_bankmachine5_refresh_gnt) & main_sdram_bankmachine6_refresh_gnt) & main_sdram_bankmachine7_refresh_gnt);
assign main_sdram_interface_rdata = {main_sdram_dfi_p3_rddata, main_sdram_dfi_p2_rddata, main_sdram_dfi_p1_rddata, main_sdram_dfi_p0_rddata};
assign {main_sdram_dfi_p3_wrdata, main_sdram_dfi_p2_wrdata, main_sdram_dfi_p1_wrdata, main_sdram_dfi_p0_wrdata} = main_sdram_interface_wdata;
assign {main_sdram_dfi_p3_wrdata_mask, main_sdram_dfi_p2_wrdata_mask, main_sdram_dfi_p1_wrdata_mask, main_sdram_dfi_p0_wrdata_mask} = (~main_sdram_interface_wdata_we);
always @(*) begin
main_sdram_choose_cmd_valids <= 8'd0;
main_sdram_choose_cmd_valids[0] <= (main_sdram_bankmachine0_cmd_valid & (((main_sdram_bankmachine0_cmd_payload_is_cmd & main_sdram_choose_cmd_want_cmds) & ((~((main_sdram_bankmachine0_cmd_payload_ras & (~main_sdram_bankmachine0_cmd_payload_cas)) & (~main_sdram_bankmachine0_cmd_payload_we))) | main_sdram_choose_cmd_want_activates)) | ((main_sdram_bankmachine0_cmd_payload_is_read == main_sdram_choose_cmd_want_reads) & (main_sdram_bankmachine0_cmd_payload_is_write == main_sdram_choose_cmd_want_writes))));
main_sdram_choose_cmd_valids[1] <= (main_sdram_bankmachine1_cmd_valid & (((main_sdram_bankmachine1_cmd_payload_is_cmd & main_sdram_choose_cmd_want_cmds) & ((~((main_sdram_bankmachine1_cmd_payload_ras & (~main_sdram_bankmachine1_cmd_payload_cas)) & (~main_sdram_bankmachine1_cmd_payload_we))) | main_sdram_choose_cmd_want_activates)) | ((main_sdram_bankmachine1_cmd_payload_is_read == main_sdram_choose_cmd_want_reads) & (main_sdram_bankmachine1_cmd_payload_is_write == main_sdram_choose_cmd_want_writes))));
main_sdram_choose_cmd_valids[2] <= (main_sdram_bankmachine2_cmd_valid & (((main_sdram_bankmachine2_cmd_payload_is_cmd & main_sdram_choose_cmd_want_cmds) & ((~((main_sdram_bankmachine2_cmd_payload_ras & (~main_sdram_bankmachine2_cmd_payload_cas)) & (~main_sdram_bankmachine2_cmd_payload_we))) | main_sdram_choose_cmd_want_activates)) | ((main_sdram_bankmachine2_cmd_payload_is_read == main_sdram_choose_cmd_want_reads) & (main_sdram_bankmachine2_cmd_payload_is_write == main_sdram_choose_cmd_want_writes))));
main_sdram_choose_cmd_valids[3] <= (main_sdram_bankmachine3_cmd_valid & (((main_sdram_bankmachine3_cmd_payload_is_cmd & main_sdram_choose_cmd_want_cmds) & ((~((main_sdram_bankmachine3_cmd_payload_ras & (~main_sdram_bankmachine3_cmd_payload_cas)) & (~main_sdram_bankmachine3_cmd_payload_we))) | main_sdram_choose_cmd_want_activates)) | ((main_sdram_bankmachine3_cmd_payload_is_read == main_sdram_choose_cmd_want_reads) & (main_sdram_bankmachine3_cmd_payload_is_write == main_sdram_choose_cmd_want_writes))));
main_sdram_choose_cmd_valids[4] <= (main_sdram_bankmachine4_cmd_valid & (((main_sdram_bankmachine4_cmd_payload_is_cmd & main_sdram_choose_cmd_want_cmds) & ((~((main_sdram_bankmachine4_cmd_payload_ras & (~main_sdram_bankmachine4_cmd_payload_cas)) & (~main_sdram_bankmachine4_cmd_payload_we))) | main_sdram_choose_cmd_want_activates)) | ((main_sdram_bankmachine4_cmd_payload_is_read == main_sdram_choose_cmd_want_reads) & (main_sdram_bankmachine4_cmd_payload_is_write == main_sdram_choose_cmd_want_writes))));
main_sdram_choose_cmd_valids[5] <= (main_sdram_bankmachine5_cmd_valid & (((main_sdram_bankmachine5_cmd_payload_is_cmd & main_sdram_choose_cmd_want_cmds) & ((~((main_sdram_bankmachine5_cmd_payload_ras & (~main_sdram_bankmachine5_cmd_payload_cas)) & (~main_sdram_bankmachine5_cmd_payload_we))) | main_sdram_choose_cmd_want_activates)) | ((main_sdram_bankmachine5_cmd_payload_is_read == main_sdram_choose_cmd_want_reads) & (main_sdram_bankmachine5_cmd_payload_is_write == main_sdram_choose_cmd_want_writes))));
main_sdram_choose_cmd_valids[6] <= (main_sdram_bankmachine6_cmd_valid & (((main_sdram_bankmachine6_cmd_payload_is_cmd & main_sdram_choose_cmd_want_cmds) & ((~((main_sdram_bankmachine6_cmd_payload_ras & (~main_sdram_bankmachine6_cmd_payload_cas)) & (~main_sdram_bankmachine6_cmd_payload_we))) | main_sdram_choose_cmd_want_activates)) | ((main_sdram_bankmachine6_cmd_payload_is_read == main_sdram_choose_cmd_want_reads) & (main_sdram_bankmachine6_cmd_payload_is_write == main_sdram_choose_cmd_want_writes))));
main_sdram_choose_cmd_valids[7] <= (main_sdram_bankmachine7_cmd_valid & (((main_sdram_bankmachine7_cmd_payload_is_cmd & main_sdram_choose_cmd_want_cmds) & ((~((main_sdram_bankmachine7_cmd_payload_ras & (~main_sdram_bankmachine7_cmd_payload_cas)) & (~main_sdram_bankmachine7_cmd_payload_we))) | main_sdram_choose_cmd_want_activates)) | ((main_sdram_bankmachine7_cmd_payload_is_read == main_sdram_choose_cmd_want_reads) & (main_sdram_bankmachine7_cmd_payload_is_write == main_sdram_choose_cmd_want_writes))));
end
assign main_sdram_choose_cmd_request = main_sdram_choose_cmd_valids;
assign main_sdram_choose_cmd_cmd_valid = builder_rhs_array_muxed0;
assign main_sdram_choose_cmd_cmd_payload_a = builder_rhs_array_muxed1;
assign main_sdram_choose_cmd_cmd_payload_ba = builder_rhs_array_muxed2;
assign main_sdram_choose_cmd_cmd_payload_is_read = builder_rhs_array_muxed3;
assign main_sdram_choose_cmd_cmd_payload_is_write = builder_rhs_array_muxed4;
assign main_sdram_choose_cmd_cmd_payload_is_cmd = builder_rhs_array_muxed5;
always @(*) begin
main_sdram_choose_cmd_cmd_payload_cas <= 1'd0;
if (main_sdram_choose_cmd_cmd_valid) begin
main_sdram_choose_cmd_cmd_payload_cas <= builder_t_array_muxed0;
end
end
always @(*) begin
main_sdram_choose_cmd_cmd_payload_ras <= 1'd0;
if (main_sdram_choose_cmd_cmd_valid) begin
main_sdram_choose_cmd_cmd_payload_ras <= builder_t_array_muxed1;
end
end
always @(*) begin
main_sdram_choose_cmd_cmd_payload_we <= 1'd0;
if (main_sdram_choose_cmd_cmd_valid) begin
main_sdram_choose_cmd_cmd_payload_we <= builder_t_array_muxed2;
end
end
assign main_sdram_choose_cmd_ce = (main_sdram_choose_cmd_cmd_ready | (~main_sdram_choose_cmd_cmd_valid));
always @(*) begin
main_sdram_choose_req_valids <= 8'd0;
main_sdram_choose_req_valids[0] <= (main_sdram_bankmachine0_cmd_valid & (((main_sdram_bankmachine0_cmd_payload_is_cmd & main_sdram_choose_req_want_cmds) & ((~((main_sdram_bankmachine0_cmd_payload_ras & (~main_sdram_bankmachine0_cmd_payload_cas)) & (~main_sdram_bankmachine0_cmd_payload_we))) | main_sdram_choose_req_want_activates)) | ((main_sdram_bankmachine0_cmd_payload_is_read == main_sdram_choose_req_want_reads) & (main_sdram_bankmachine0_cmd_payload_is_write == main_sdram_choose_req_want_writes))));
main_sdram_choose_req_valids[1] <= (main_sdram_bankmachine1_cmd_valid & (((main_sdram_bankmachine1_cmd_payload_is_cmd & main_sdram_choose_req_want_cmds) & ((~((main_sdram_bankmachine1_cmd_payload_ras & (~main_sdram_bankmachine1_cmd_payload_cas)) & (~main_sdram_bankmachine1_cmd_payload_we))) | main_sdram_choose_req_want_activates)) | ((main_sdram_bankmachine1_cmd_payload_is_read == main_sdram_choose_req_want_reads) & (main_sdram_bankmachine1_cmd_payload_is_write == main_sdram_choose_req_want_writes))));
main_sdram_choose_req_valids[2] <= (main_sdram_bankmachine2_cmd_valid & (((main_sdram_bankmachine2_cmd_payload_is_cmd & main_sdram_choose_req_want_cmds) & ((~((main_sdram_bankmachine2_cmd_payload_ras & (~main_sdram_bankmachine2_cmd_payload_cas)) & (~main_sdram_bankmachine2_cmd_payload_we))) | main_sdram_choose_req_want_activates)) | ((main_sdram_bankmachine2_cmd_payload_is_read == main_sdram_choose_req_want_reads) & (main_sdram_bankmachine2_cmd_payload_is_write == main_sdram_choose_req_want_writes))));
main_sdram_choose_req_valids[3] <= (main_sdram_bankmachine3_cmd_valid & (((main_sdram_bankmachine3_cmd_payload_is_cmd & main_sdram_choose_req_want_cmds) & ((~((main_sdram_bankmachine3_cmd_payload_ras & (~main_sdram_bankmachine3_cmd_payload_cas)) & (~main_sdram_bankmachine3_cmd_payload_we))) | main_sdram_choose_req_want_activates)) | ((main_sdram_bankmachine3_cmd_payload_is_read == main_sdram_choose_req_want_reads) & (main_sdram_bankmachine3_cmd_payload_is_write == main_sdram_choose_req_want_writes))));
main_sdram_choose_req_valids[4] <= (main_sdram_bankmachine4_cmd_valid & (((main_sdram_bankmachine4_cmd_payload_is_cmd & main_sdram_choose_req_want_cmds) & ((~((main_sdram_bankmachine4_cmd_payload_ras & (~main_sdram_bankmachine4_cmd_payload_cas)) & (~main_sdram_bankmachine4_cmd_payload_we))) | main_sdram_choose_req_want_activates)) | ((main_sdram_bankmachine4_cmd_payload_is_read == main_sdram_choose_req_want_reads) & (main_sdram_bankmachine4_cmd_payload_is_write == main_sdram_choose_req_want_writes))));
main_sdram_choose_req_valids[5] <= (main_sdram_bankmachine5_cmd_valid & (((main_sdram_bankmachine5_cmd_payload_is_cmd & main_sdram_choose_req_want_cmds) & ((~((main_sdram_bankmachine5_cmd_payload_ras & (~main_sdram_bankmachine5_cmd_payload_cas)) & (~main_sdram_bankmachine5_cmd_payload_we))) | main_sdram_choose_req_want_activates)) | ((main_sdram_bankmachine5_cmd_payload_is_read == main_sdram_choose_req_want_reads) & (main_sdram_bankmachine5_cmd_payload_is_write == main_sdram_choose_req_want_writes))));
main_sdram_choose_req_valids[6] <= (main_sdram_bankmachine6_cmd_valid & (((main_sdram_bankmachine6_cmd_payload_is_cmd & main_sdram_choose_req_want_cmds) & ((~((main_sdram_bankmachine6_cmd_payload_ras & (~main_sdram_bankmachine6_cmd_payload_cas)) & (~main_sdram_bankmachine6_cmd_payload_we))) | main_sdram_choose_req_want_activates)) | ((main_sdram_bankmachine6_cmd_payload_is_read == main_sdram_choose_req_want_reads) & (main_sdram_bankmachine6_cmd_payload_is_write == main_sdram_choose_req_want_writes))));
main_sdram_choose_req_valids[7] <= (main_sdram_bankmachine7_cmd_valid & (((main_sdram_bankmachine7_cmd_payload_is_cmd & main_sdram_choose_req_want_cmds) & ((~((main_sdram_bankmachine7_cmd_payload_ras & (~main_sdram_bankmachine7_cmd_payload_cas)) & (~main_sdram_bankmachine7_cmd_payload_we))) | main_sdram_choose_req_want_activates)) | ((main_sdram_bankmachine7_cmd_payload_is_read == main_sdram_choose_req_want_reads) & (main_sdram_bankmachine7_cmd_payload_is_write == main_sdram_choose_req_want_writes))));
end
assign main_sdram_choose_req_request = main_sdram_choose_req_valids;
assign main_sdram_choose_req_cmd_valid = builder_rhs_array_muxed6;
assign main_sdram_choose_req_cmd_payload_a = builder_rhs_array_muxed7;
assign main_sdram_choose_req_cmd_payload_ba = builder_rhs_array_muxed8;
assign main_sdram_choose_req_cmd_payload_is_read = builder_rhs_array_muxed9;
assign main_sdram_choose_req_cmd_payload_is_write = builder_rhs_array_muxed10;
assign main_sdram_choose_req_cmd_payload_is_cmd = builder_rhs_array_muxed11;
always @(*) begin
main_sdram_choose_req_cmd_payload_cas <= 1'd0;
if (main_sdram_choose_req_cmd_valid) begin
main_sdram_choose_req_cmd_payload_cas <= builder_t_array_muxed3;
end
end
always @(*) begin
main_sdram_choose_req_cmd_payload_ras <= 1'd0;
if (main_sdram_choose_req_cmd_valid) begin
main_sdram_choose_req_cmd_payload_ras <= builder_t_array_muxed4;
end
end
always @(*) begin
main_sdram_choose_req_cmd_payload_we <= 1'd0;
if (main_sdram_choose_req_cmd_valid) begin
main_sdram_choose_req_cmd_payload_we <= builder_t_array_muxed5;
end
end
always @(*) begin
main_sdram_bankmachine0_cmd_ready <= 1'd0;
if (((main_sdram_choose_cmd_cmd_valid & main_sdram_choose_cmd_cmd_ready) & (main_sdram_choose_cmd_grant == 1'd0))) begin
main_sdram_bankmachine0_cmd_ready <= 1'd1;
end
if (((main_sdram_choose_req_cmd_valid & main_sdram_choose_req_cmd_ready) & (main_sdram_choose_req_grant == 1'd0))) begin
main_sdram_bankmachine0_cmd_ready <= 1'd1;
end
end
always @(*) begin
main_sdram_bankmachine1_cmd_ready <= 1'd0;
if (((main_sdram_choose_cmd_cmd_valid & main_sdram_choose_cmd_cmd_ready) & (main_sdram_choose_cmd_grant == 1'd1))) begin
main_sdram_bankmachine1_cmd_ready <= 1'd1;
end
if (((main_sdram_choose_req_cmd_valid & main_sdram_choose_req_cmd_ready) & (main_sdram_choose_req_grant == 1'd1))) begin
main_sdram_bankmachine1_cmd_ready <= 1'd1;
end
end
always @(*) begin
main_sdram_bankmachine2_cmd_ready <= 1'd0;
if (((main_sdram_choose_cmd_cmd_valid & main_sdram_choose_cmd_cmd_ready) & (main_sdram_choose_cmd_grant == 2'd2))) begin
main_sdram_bankmachine2_cmd_ready <= 1'd1;
end
if (((main_sdram_choose_req_cmd_valid & main_sdram_choose_req_cmd_ready) & (main_sdram_choose_req_grant == 2'd2))) begin
main_sdram_bankmachine2_cmd_ready <= 1'd1;
end
end
always @(*) begin
main_sdram_bankmachine3_cmd_ready <= 1'd0;
if (((main_sdram_choose_cmd_cmd_valid & main_sdram_choose_cmd_cmd_ready) & (main_sdram_choose_cmd_grant == 2'd3))) begin
main_sdram_bankmachine3_cmd_ready <= 1'd1;
end
if (((main_sdram_choose_req_cmd_valid & main_sdram_choose_req_cmd_ready) & (main_sdram_choose_req_grant == 2'd3))) begin
main_sdram_bankmachine3_cmd_ready <= 1'd1;
end
end
always @(*) begin
main_sdram_bankmachine4_cmd_ready <= 1'd0;
if (((main_sdram_choose_cmd_cmd_valid & main_sdram_choose_cmd_cmd_ready) & (main_sdram_choose_cmd_grant == 3'd4))) begin
main_sdram_bankmachine4_cmd_ready <= 1'd1;
end
if (((main_sdram_choose_req_cmd_valid & main_sdram_choose_req_cmd_ready) & (main_sdram_choose_req_grant == 3'd4))) begin
main_sdram_bankmachine4_cmd_ready <= 1'd1;
end
end
always @(*) begin
main_sdram_bankmachine5_cmd_ready <= 1'd0;
if (((main_sdram_choose_cmd_cmd_valid & main_sdram_choose_cmd_cmd_ready) & (main_sdram_choose_cmd_grant == 3'd5))) begin
main_sdram_bankmachine5_cmd_ready <= 1'd1;
end
if (((main_sdram_choose_req_cmd_valid & main_sdram_choose_req_cmd_ready) & (main_sdram_choose_req_grant == 3'd5))) begin
main_sdram_bankmachine5_cmd_ready <= 1'd1;
end
end
always @(*) begin
main_sdram_bankmachine6_cmd_ready <= 1'd0;
if (((main_sdram_choose_cmd_cmd_valid & main_sdram_choose_cmd_cmd_ready) & (main_sdram_choose_cmd_grant == 3'd6))) begin
main_sdram_bankmachine6_cmd_ready <= 1'd1;
end
if (((main_sdram_choose_req_cmd_valid & main_sdram_choose_req_cmd_ready) & (main_sdram_choose_req_grant == 3'd6))) begin
main_sdram_bankmachine6_cmd_ready <= 1'd1;
end
end
always @(*) begin
main_sdram_bankmachine7_cmd_ready <= 1'd0;
if (((main_sdram_choose_cmd_cmd_valid & main_sdram_choose_cmd_cmd_ready) & (main_sdram_choose_cmd_grant == 3'd7))) begin
main_sdram_bankmachine7_cmd_ready <= 1'd1;
end
if (((main_sdram_choose_req_cmd_valid & main_sdram_choose_req_cmd_ready) & (main_sdram_choose_req_grant == 3'd7))) begin
main_sdram_bankmachine7_cmd_ready <= 1'd1;
end
end
assign main_sdram_choose_req_ce = (main_sdram_choose_req_cmd_ready | (~main_sdram_choose_req_cmd_valid));
assign main_sdram_dfi_p0_reset_n = 1'd1;
assign main_sdram_dfi_p0_cke = {1{main_sdram_steerer0}};
assign main_sdram_dfi_p0_odt = {1{main_sdram_steerer1}};
assign main_sdram_dfi_p1_reset_n = 1'd1;
assign main_sdram_dfi_p1_cke = {1{main_sdram_steerer2}};
assign main_sdram_dfi_p1_odt = {1{main_sdram_steerer3}};
assign main_sdram_dfi_p2_reset_n = 1'd1;
assign main_sdram_dfi_p2_cke = {1{main_sdram_steerer4}};
assign main_sdram_dfi_p2_odt = {1{main_sdram_steerer5}};
assign main_sdram_dfi_p3_reset_n = 1'd1;
assign main_sdram_dfi_p3_cke = {1{main_sdram_steerer6}};
assign main_sdram_dfi_p3_odt = {1{main_sdram_steerer7}};
assign main_sdram_tfawcon_count = ((main_sdram_tfawcon_window[0] + main_sdram_tfawcon_window[1]) + main_sdram_tfawcon_window[2]);
always @(*) begin
main_sdram_cmd_ready <= 1'd0;
main_sdram_choose_cmd_cmd_ready <= 1'd0;
main_sdram_choose_req_want_reads <= 1'd0;
main_sdram_choose_req_want_writes <= 1'd0;
main_sdram_en1 <= 1'd0;
main_sdram_choose_req_cmd_ready <= 1'd0;
main_sdram_steerer_sel2 <= 2'd0;
main_sdram_steerer_sel0 <= 2'd0;
main_sdram_steerer_sel1 <= 2'd0;
main_sdram_en0 <= 1'd0;
builder_multiplexer_next_state <= 4'd0;
main_sdram_choose_cmd_want_activates <= 1'd0;
main_sdram_steerer_sel3 <= 2'd0;
builder_multiplexer_next_state <= builder_multiplexer_state;
case (builder_multiplexer_state)
1'd1: begin
main_sdram_en1 <= 1'd1;
main_sdram_choose_req_want_writes <= 1'd1;
if (1'd0) begin
main_sdram_choose_req_cmd_ready <= (main_sdram_cas_allowed & ((~((main_sdram_choose_req_cmd_payload_ras & (~main_sdram_choose_req_cmd_payload_cas)) & (~main_sdram_choose_req_cmd_payload_we))) | main_sdram_ras_allowed));
end else begin
main_sdram_choose_cmd_want_activates <= main_sdram_ras_allowed;
main_sdram_choose_cmd_cmd_ready <= ((~((main_sdram_choose_cmd_cmd_payload_ras & (~main_sdram_choose_cmd_cmd_payload_cas)) & (~main_sdram_choose_cmd_cmd_payload_we))) | main_sdram_ras_allowed);
main_sdram_choose_req_cmd_ready <= main_sdram_cas_allowed;
end
main_sdram_steerer_sel0 <= 1'd0;
main_sdram_steerer_sel1 <= 1'd0;
main_sdram_steerer_sel2 <= 1'd1;
main_sdram_steerer_sel3 <= 2'd2;
if (main_sdram_read_available) begin
if (((~main_sdram_write_available) | main_sdram_max_time1)) begin
builder_multiplexer_next_state <= 2'd3;
end
end
if (main_sdram_go_to_refresh) begin
builder_multiplexer_next_state <= 2'd2;
end
end
2'd2: begin
main_sdram_steerer_sel0 <= 2'd3;
main_sdram_cmd_ready <= 1'd1;
if (main_sdram_cmd_last) begin
builder_multiplexer_next_state <= 1'd0;
end
end
2'd3: begin
if (main_sdram_twtrcon_ready) begin
builder_multiplexer_next_state <= 1'd0;
end
end
3'd4: begin
builder_multiplexer_next_state <= 3'd5;
end
3'd5: begin
builder_multiplexer_next_state <= 3'd6;
end
3'd6: begin
builder_multiplexer_next_state <= 3'd7;
end
3'd7: begin
builder_multiplexer_next_state <= 4'd8;
end
4'd8: begin
builder_multiplexer_next_state <= 4'd9;
end
4'd9: begin
builder_multiplexer_next_state <= 4'd10;
end
4'd10: begin
builder_multiplexer_next_state <= 4'd11;
end
4'd11: begin
builder_multiplexer_next_state <= 1'd1;
end
default: begin
main_sdram_en0 <= 1'd1;
main_sdram_choose_req_want_reads <= 1'd1;
if (1'd0) begin
main_sdram_choose_req_cmd_ready <= (main_sdram_cas_allowed & ((~((main_sdram_choose_req_cmd_payload_ras & (~main_sdram_choose_req_cmd_payload_cas)) & (~main_sdram_choose_req_cmd_payload_we))) | main_sdram_ras_allowed));
end else begin
main_sdram_choose_cmd_want_activates <= main_sdram_ras_allowed;
main_sdram_choose_cmd_cmd_ready <= ((~((main_sdram_choose_cmd_cmd_payload_ras & (~main_sdram_choose_cmd_cmd_payload_cas)) & (~main_sdram_choose_cmd_cmd_payload_we))) | main_sdram_ras_allowed);
main_sdram_choose_req_cmd_ready <= main_sdram_cas_allowed;
end
main_sdram_steerer_sel0 <= 1'd0;
main_sdram_steerer_sel1 <= 1'd1;
main_sdram_steerer_sel2 <= 2'd2;
main_sdram_steerer_sel3 <= 1'd0;
if (main_sdram_write_available) begin
if (((~main_sdram_read_available) | main_sdram_max_time0)) begin
builder_multiplexer_next_state <= 3'd4;
end
end
if (main_sdram_go_to_refresh) begin
builder_multiplexer_next_state <= 2'd2;
end
end
endcase
end
assign builder_roundrobin0_request = {(((main_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((builder_locked0 | (main_sdram_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_sdram_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_sdram_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_sdram_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_sdram_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_sdram_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_sdram_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_port_cmd_valid)};
assign builder_roundrobin0_ce = ((~main_sdram_interface_bank0_valid) & (~main_sdram_interface_bank0_lock));
assign main_sdram_interface_bank0_addr = builder_rhs_array_muxed12;
assign main_sdram_interface_bank0_we = builder_rhs_array_muxed13;
assign main_sdram_interface_bank0_valid = builder_rhs_array_muxed14;
assign builder_roundrobin1_request = {(((main_port_cmd_payload_addr[9:7] == 1'd1) & (~(((((((builder_locked1 | (main_sdram_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_sdram_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_sdram_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_sdram_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_sdram_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_sdram_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_sdram_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_port_cmd_valid)};
assign builder_roundrobin1_ce = ((~main_sdram_interface_bank1_valid) & (~main_sdram_interface_bank1_lock));
assign main_sdram_interface_bank1_addr = builder_rhs_array_muxed15;
assign main_sdram_interface_bank1_we = builder_rhs_array_muxed16;
assign main_sdram_interface_bank1_valid = builder_rhs_array_muxed17;
assign builder_roundrobin2_request = {(((main_port_cmd_payload_addr[9:7] == 2'd2) & (~(((((((builder_locked2 | (main_sdram_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_sdram_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_sdram_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_sdram_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_sdram_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_sdram_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_sdram_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_port_cmd_valid)};
assign builder_roundrobin2_ce = ((~main_sdram_interface_bank2_valid) & (~main_sdram_interface_bank2_lock));
assign main_sdram_interface_bank2_addr = builder_rhs_array_muxed18;
assign main_sdram_interface_bank2_we = builder_rhs_array_muxed19;
assign main_sdram_interface_bank2_valid = builder_rhs_array_muxed20;
assign builder_roundrobin3_request = {(((main_port_cmd_payload_addr[9:7] == 2'd3) & (~(((((((builder_locked3 | (main_sdram_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_sdram_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_sdram_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_sdram_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_sdram_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_sdram_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_sdram_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_port_cmd_valid)};
assign builder_roundrobin3_ce = ((~main_sdram_interface_bank3_valid) & (~main_sdram_interface_bank3_lock));
assign main_sdram_interface_bank3_addr = builder_rhs_array_muxed21;
assign main_sdram_interface_bank3_we = builder_rhs_array_muxed22;
assign main_sdram_interface_bank3_valid = builder_rhs_array_muxed23;
assign builder_roundrobin4_request = {(((main_port_cmd_payload_addr[9:7] == 3'd4) & (~(((((((builder_locked4 | (main_sdram_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_sdram_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_sdram_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_sdram_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_sdram_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_sdram_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_sdram_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_port_cmd_valid)};
assign builder_roundrobin4_ce = ((~main_sdram_interface_bank4_valid) & (~main_sdram_interface_bank4_lock));
assign main_sdram_interface_bank4_addr = builder_rhs_array_muxed24;
assign main_sdram_interface_bank4_we = builder_rhs_array_muxed25;
assign main_sdram_interface_bank4_valid = builder_rhs_array_muxed26;
assign builder_roundrobin5_request = {(((main_port_cmd_payload_addr[9:7] == 3'd5) & (~(((((((builder_locked5 | (main_sdram_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_sdram_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_sdram_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_sdram_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_sdram_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_sdram_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_sdram_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_port_cmd_valid)};
assign builder_roundrobin5_ce = ((~main_sdram_interface_bank5_valid) & (~main_sdram_interface_bank5_lock));
assign main_sdram_interface_bank5_addr = builder_rhs_array_muxed27;
assign main_sdram_interface_bank5_we = builder_rhs_array_muxed28;
assign main_sdram_interface_bank5_valid = builder_rhs_array_muxed29;
assign builder_roundrobin6_request = {(((main_port_cmd_payload_addr[9:7] == 3'd6) & (~(((((((builder_locked6 | (main_sdram_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_sdram_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_sdram_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_sdram_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_sdram_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_sdram_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_sdram_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_port_cmd_valid)};
assign builder_roundrobin6_ce = ((~main_sdram_interface_bank6_valid) & (~main_sdram_interface_bank6_lock));
assign main_sdram_interface_bank6_addr = builder_rhs_array_muxed30;
assign main_sdram_interface_bank6_we = builder_rhs_array_muxed31;
assign main_sdram_interface_bank6_valid = builder_rhs_array_muxed32;
assign builder_roundrobin7_request = {(((main_port_cmd_payload_addr[9:7] == 3'd7) & (~(((((((builder_locked7 | (main_sdram_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_sdram_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_sdram_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_sdram_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_sdram_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_sdram_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_sdram_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))))) & main_port_cmd_valid)};
assign builder_roundrobin7_ce = ((~main_sdram_interface_bank7_valid) & (~main_sdram_interface_bank7_lock));
assign main_sdram_interface_bank7_addr = builder_rhs_array_muxed33;
assign main_sdram_interface_bank7_we = builder_rhs_array_muxed34;
assign main_sdram_interface_bank7_valid = builder_rhs_array_muxed35;
assign main_port_cmd_ready = ((((((((1'd0 | (((builder_roundrobin0_grant == 1'd0) & ((main_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((builder_locked0 | (main_sdram_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_sdram_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_sdram_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_sdram_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_sdram_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_sdram_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_sdram_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0)))))) & main_sdram_interface_bank0_ready)) | (((builder_roundrobin1_grant == 1'd0) & ((main_port_cmd_payload_addr[9:7] == 1'd1) & (~(((((((builder_locked1 | (main_sdram_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_sdram_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_sdram_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_sdram_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_sdram_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_sdram_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_sdram_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0)))))) & main_sdram_interface_bank1_ready)) | (((builder_roundrobin2_grant == 1'd0) & ((main_port_cmd_payload_addr[9:7] == 2'd2) & (~(((((((builder_locked2 | (main_sdram_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_sdram_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_sdram_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_sdram_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_sdram_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_sdram_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_sdram_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0)))))) & main_sdram_interface_bank2_ready)) | (((builder_roundrobin3_grant == 1'd0) & ((main_port_cmd_payload_addr[9:7] == 2'd3) & (~(((((((builder_locked3 | (main_sdram_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_sdram_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_sdram_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_sdram_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_sdram_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_sdram_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_sdram_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0)))))) & main_sdram_interface_bank3_ready)) | (((builder_roundrobin4_grant == 1'd0) & ((main_port_cmd_payload_addr[9:7] == 3'd4) & (~(((((((builder_locked4 | (main_sdram_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_sdram_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_sdram_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_sdram_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_sdram_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_sdram_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_sdram_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0)))))) & main_sdram_interface_bank4_ready)) | (((builder_roundrobin5_grant == 1'd0) & ((main_port_cmd_payload_addr[9:7] == 3'd5) & (~(((((((builder_locked5 | (main_sdram_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_sdram_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_sdram_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_sdram_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_sdram_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_sdram_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_sdram_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0)))))) & main_sdram_interface_bank5_ready)) | (((builder_roundrobin6_grant == 1'd0) & ((main_port_cmd_payload_addr[9:7] == 3'd6) & (~(((((((builder_locked6 | (main_sdram_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_sdram_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_sdram_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_sdram_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_sdram_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_sdram_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_sdram_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0)))))) & main_sdram_interface_bank6_ready)) | (((builder_roundrobin7_grant == 1'd0) & ((main_port_cmd_payload_addr[9:7] == 3'd7) & (~(((((((builder_locked7 | (main_sdram_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_sdram_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_sdram_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_sdram_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_sdram_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_sdram_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_sdram_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0)))))) & main_sdram_interface_bank7_ready));
assign main_port_wdata_ready = builder_new_master_wdata_ready2;
assign main_port_rdata_valid = builder_new_master_rdata_valid9;
always @(*) begin
main_sdram_interface_wdata <= 128'd0;
main_sdram_interface_wdata_we <= 16'd0;
case ({builder_new_master_wdata_ready2})
1'd1: begin
main_sdram_interface_wdata <= main_port_wdata_payload_data;
main_sdram_interface_wdata_we <= main_port_wdata_payload_we;
end
default: begin
main_sdram_interface_wdata <= 1'd0;
main_sdram_interface_wdata_we <= 1'd0;
end
endcase
end
assign main_port_rdata_payload_data = main_sdram_interface_rdata;
assign builder_roundrobin0_grant = 1'd0;
assign builder_roundrobin1_grant = 1'd0;
assign builder_roundrobin2_grant = 1'd0;
assign builder_roundrobin3_grant = 1'd0;
assign builder_roundrobin4_grant = 1'd0;
assign builder_roundrobin5_grant = 1'd0;
assign builder_roundrobin6_grant = 1'd0;
assign builder_roundrobin7_grant = 1'd0;
assign main_data_port_adr = main_interface0_wb_sdram_adr[10:2];
always @(*) begin
main_data_port_dat_w <= 128'd0;
main_data_port_we <= 16'd0;
if (main_write_from_slave) begin
main_data_port_dat_w <= main_dat_r;
main_data_port_we <= {16{1'd1}};
end else begin
main_data_port_dat_w <= {4{main_interface0_wb_sdram_dat_w}};
if ((((main_interface0_wb_sdram_cyc & main_interface0_wb_sdram_stb) & main_interface0_wb_sdram_we) & main_interface0_wb_sdram_ack)) begin
main_data_port_we <= {({4{(main_interface0_wb_sdram_adr[1:0] == 1'd0)}} & main_interface0_wb_sdram_sel), ({4{(main_interface0_wb_sdram_adr[1:0] == 1'd1)}} & main_interface0_wb_sdram_sel), ({4{(main_interface0_wb_sdram_adr[1:0] == 2'd2)}} & main_interface0_wb_sdram_sel), ({4{(main_interface0_wb_sdram_adr[1:0] == 2'd3)}} & main_interface0_wb_sdram_sel)};
end
end
end
assign main_dat_w = main_data_port_dat_r;
assign main_sel = 16'd65535;
always @(*) begin
main_interface0_wb_sdram_dat_r <= 32'd0;
case (main_adr_offset_r)
1'd0: begin
main_interface0_wb_sdram_dat_r <= main_data_port_dat_r[127:96];
end
1'd1: begin
main_interface0_wb_sdram_dat_r <= main_data_port_dat_r[95:64];
end
2'd2: begin
main_interface0_wb_sdram_dat_r <= main_data_port_dat_r[63:32];
end
default: begin
main_interface0_wb_sdram_dat_r <= main_data_port_dat_r[31:0];
end
endcase
end
assign {main_tag_do_dirty, main_tag_do_tag} = main_tag_port_dat_r;
assign main_tag_port_dat_w = {main_tag_di_dirty, main_tag_di_tag};
assign main_tag_port_adr = main_interface0_wb_sdram_adr[10:2];
assign main_tag_di_tag = main_interface0_wb_sdram_adr[29:11];
assign main_adr = {main_tag_do_tag, main_interface0_wb_sdram_adr[10:2]};
always @(*) begin
builder_fullmemorywe_next_state <= 3'd0;
main_tag_di_dirty <= 1'd0;
main_word_clr <= 1'd0;
main_interface0_wb_sdram_ack <= 1'd0;
main_word_inc <= 1'd0;
main_write_from_slave <= 1'd0;
main_cyc <= 1'd0;
main_stb <= 1'd0;
main_tag_port_we <= 1'd0;
main_we <= 1'd0;
builder_fullmemorywe_next_state <= builder_fullmemorywe_state;
case (builder_fullmemorywe_state)
1'd1: begin
main_word_clr <= 1'd1;
if ((main_tag_do_tag == main_interface0_wb_sdram_adr[29:11])) begin
main_interface0_wb_sdram_ack <= 1'd1;
if (main_interface0_wb_sdram_we) begin
main_tag_di_dirty <= 1'd1;
main_tag_port_we <= 1'd1;
end
builder_fullmemorywe_next_state <= 1'd0;
end else begin
if (main_tag_do_dirty) begin
builder_fullmemorywe_next_state <= 2'd2;
end else begin
builder_fullmemorywe_next_state <= 2'd3;
end
end
end
2'd2: begin
main_stb <= 1'd1;
main_cyc <= 1'd1;
main_we <= 1'd1;
if (main_ack) begin
main_word_inc <= 1'd1;
if (1'd1) begin
builder_fullmemorywe_next_state <= 2'd3;
end
end
end
2'd3: begin
main_tag_port_we <= 1'd1;
main_word_clr <= 1'd1;
builder_fullmemorywe_next_state <= 3'd4;
end
3'd4: begin
main_stb <= 1'd1;
main_cyc <= 1'd1;
main_we <= 1'd0;
if (main_ack) begin
main_write_from_slave <= 1'd1;
main_word_inc <= 1'd1;
if (1'd1) begin
builder_fullmemorywe_next_state <= 1'd1;
end else begin
builder_fullmemorywe_next_state <= 3'd4;
end
end
end
default: begin
if ((main_interface0_wb_sdram_cyc & main_interface0_wb_sdram_stb)) begin
builder_fullmemorywe_next_state <= 1'd1;
end
end
endcase
end
assign main_port_cmd_payload_addr = (main_adr - 1'd0);
assign main_port_wdata_payload_we = main_sel;
assign main_port_wdata_payload_data = main_dat_w;
assign main_dat_r = main_port_rdata_payload_data;
always @(*) begin
main_port_rdata_ready <= 1'd0;
main_port_wdata_valid <= 1'd0;
main_port_cmd_valid <= 1'd0;
builder_litedramwishbone2native_next_state <= 2'd0;
main_ack <= 1'd0;
main_port_cmd_payload_we <= 1'd0;
builder_litedramwishbone2native_next_state <= builder_litedramwishbone2native_state;
case (builder_litedramwishbone2native_state)
1'd1: begin
main_port_wdata_valid <= 1'd1;
if (main_port_wdata_ready) begin
main_ack <= 1'd1;
builder_litedramwishbone2native_next_state <= 1'd0;
end
end
2'd2: begin
main_port_rdata_ready <= 1'd1;
if (main_port_rdata_valid) begin
main_ack <= 1'd1;
builder_litedramwishbone2native_next_state <= 1'd0;
end
end
default: begin
main_port_cmd_valid <= (main_cyc & main_stb);
main_port_cmd_payload_we <= main_we;
if ((main_port_cmd_valid & main_port_cmd_ready)) begin
if (main_we) begin
builder_litedramwishbone2native_next_state <= 1'd1;
end else begin
builder_litedramwishbone2native_next_state <= 2'd2;
end
end
end
endcase
end
assign main_interface0_wb_sdram_adr = builder_rhs_array_muxed36;
assign main_interface0_wb_sdram_dat_w = builder_rhs_array_muxed37;
assign main_interface0_wb_sdram_sel = builder_rhs_array_muxed38;
assign main_interface0_wb_sdram_cyc = builder_rhs_array_muxed39;
assign main_interface0_wb_sdram_stb = builder_rhs_array_muxed40;
assign main_interface0_wb_sdram_we = builder_rhs_array_muxed41;
assign main_interface0_wb_sdram_cti = builder_rhs_array_muxed42;
assign main_interface0_wb_sdram_bte = builder_rhs_array_muxed43;
assign main_interface1_wb_sdram_dat_r = main_interface0_wb_sdram_dat_r;
assign main_interface1_wb_sdram_ack = (main_interface0_wb_sdram_ack & (builder_wb_sdram_con_grant == 1'd0));
assign main_interface1_wb_sdram_err = (main_interface0_wb_sdram_err & (builder_wb_sdram_con_grant == 1'd0));
assign builder_wb_sdram_con_request = {main_interface1_wb_sdram_cyc};
assign builder_wb_sdram_con_grant = 1'd0;
assign builder_minsoc_shared_adr = builder_rhs_array_muxed44;
assign builder_minsoc_shared_dat_w = builder_rhs_array_muxed45;
assign builder_minsoc_shared_sel = builder_rhs_array_muxed46;
assign builder_minsoc_shared_cyc = builder_rhs_array_muxed47;
assign builder_minsoc_shared_stb = builder_rhs_array_muxed48;
assign builder_minsoc_shared_we = builder_rhs_array_muxed49;
assign builder_minsoc_shared_cti = builder_rhs_array_muxed50;
assign builder_minsoc_shared_bte = builder_rhs_array_muxed51;
assign main_interface0_soc_bus_dat_r = builder_minsoc_shared_dat_r;
assign main_interface1_soc_bus_dat_r = builder_minsoc_shared_dat_r;
assign main_interface0_soc_bus_ack = (builder_minsoc_shared_ack & (builder_minsoc_grant == 1'd0));
assign main_interface1_soc_bus_ack = (builder_minsoc_shared_ack & (builder_minsoc_grant == 1'd1));
assign main_interface0_soc_bus_err = (builder_minsoc_shared_err & (builder_minsoc_grant == 1'd0));
assign main_interface1_soc_bus_err = (builder_minsoc_shared_err & (builder_minsoc_grant == 1'd1));
assign builder_minsoc_request = {main_interface1_soc_bus_cyc, main_interface0_soc_bus_cyc};
always @(*) begin
builder_minsoc_slave_sel <= 4'd0;
builder_minsoc_slave_sel[0] <= (builder_minsoc_shared_adr[28:13] == 1'd0);
builder_minsoc_slave_sel[1] <= (builder_minsoc_shared_adr[28:13] == 10'd512);
builder_minsoc_slave_sel[2] <= (builder_minsoc_shared_adr[28:22] == 2'd2);
builder_minsoc_slave_sel[3] <= (builder_minsoc_shared_adr[28:26] == 3'd4);
end
assign main_rom_bus_adr = builder_minsoc_shared_adr;
assign main_rom_bus_dat_w = builder_minsoc_shared_dat_w;
assign main_rom_bus_sel = builder_minsoc_shared_sel;
assign main_rom_bus_stb = builder_minsoc_shared_stb;
assign main_rom_bus_we = builder_minsoc_shared_we;
assign main_rom_bus_cti = builder_minsoc_shared_cti;
assign main_rom_bus_bte = builder_minsoc_shared_bte;
assign main_sram_bus_adr = builder_minsoc_shared_adr;
assign main_sram_bus_dat_w = builder_minsoc_shared_dat_w;
assign main_sram_bus_sel = builder_minsoc_shared_sel;
assign main_sram_bus_stb = builder_minsoc_shared_stb;
assign main_sram_bus_we = builder_minsoc_shared_we;
assign main_sram_bus_cti = builder_minsoc_shared_cti;
assign main_sram_bus_bte = builder_minsoc_shared_bte;
assign main_bus_wishbone_adr = builder_minsoc_shared_adr;
assign main_bus_wishbone_dat_w = builder_minsoc_shared_dat_w;
assign main_bus_wishbone_sel = builder_minsoc_shared_sel;
assign main_bus_wishbone_stb = builder_minsoc_shared_stb;
assign main_bus_wishbone_we = builder_minsoc_shared_we;
assign main_bus_wishbone_cti = builder_minsoc_shared_cti;
assign main_bus_wishbone_bte = builder_minsoc_shared_bte;
assign main_interface1_wb_sdram_adr = builder_minsoc_shared_adr;
assign main_interface1_wb_sdram_dat_w = builder_minsoc_shared_dat_w;
assign main_interface1_wb_sdram_sel = builder_minsoc_shared_sel;
assign main_interface1_wb_sdram_stb = builder_minsoc_shared_stb;
assign main_interface1_wb_sdram_we = builder_minsoc_shared_we;
assign main_interface1_wb_sdram_cti = builder_minsoc_shared_cti;
assign main_interface1_wb_sdram_bte = builder_minsoc_shared_bte;
assign main_rom_bus_cyc = (builder_minsoc_shared_cyc & builder_minsoc_slave_sel[0]);
assign main_sram_bus_cyc = (builder_minsoc_shared_cyc & builder_minsoc_slave_sel[1]);
assign main_bus_wishbone_cyc = (builder_minsoc_shared_cyc & builder_minsoc_slave_sel[2]);
assign main_interface1_wb_sdram_cyc = (builder_minsoc_shared_cyc & builder_minsoc_slave_sel[3]);
assign builder_minsoc_shared_err = (((main_rom_bus_err | main_sram_bus_err) | main_bus_wishbone_err) | main_interface1_wb_sdram_err);
assign builder_minsoc_wait = ((builder_minsoc_shared_stb & builder_minsoc_shared_cyc) & (~builder_minsoc_shared_ack));
always @(*) begin
builder_minsoc_shared_dat_r <= 32'd0;
builder_minsoc_error <= 1'd0;
builder_minsoc_shared_ack <= 1'd0;
builder_minsoc_shared_ack <= (((main_rom_bus_ack | main_sram_bus_ack) | main_bus_wishbone_ack) | main_interface1_wb_sdram_ack);
builder_minsoc_shared_dat_r <= (((({32{builder_minsoc_slave_sel_r[0]}} & main_rom_bus_dat_r) | ({32{builder_minsoc_slave_sel_r[1]}} & main_sram_bus_dat_r)) | ({32{builder_minsoc_slave_sel_r[2]}} & main_bus_wishbone_dat_r)) | ({32{builder_minsoc_slave_sel_r[3]}} & main_interface1_wb_sdram_dat_r));
if (builder_minsoc_done) begin
builder_minsoc_shared_dat_r <= 32'd4294967295;
builder_minsoc_shared_ack <= 1'd1;
builder_minsoc_error <= 1'd1;
end
end
assign builder_minsoc_done = (builder_minsoc_count == 1'd0);
assign builder_minsoc_csrbank0_sel = (builder_minsoc_interface0_bank_bus_adr[13:9] == 1'd0);
assign main_ctrl_reset_reset_r = builder_minsoc_interface0_bank_bus_dat_w[0];
assign main_ctrl_reset_reset_re = ((builder_minsoc_csrbank0_sel & builder_minsoc_interface0_bank_bus_we) & (builder_minsoc_interface0_bank_bus_adr[3:0] == 1'd0));
assign main_ctrl_reset_reset_we = ((builder_minsoc_csrbank0_sel & (~builder_minsoc_interface0_bank_bus_we)) & (builder_minsoc_interface0_bank_bus_adr[3:0] == 1'd0));
assign builder_minsoc_csrbank0_scratch3_r = builder_minsoc_interface0_bank_bus_dat_w[7:0];
assign builder_minsoc_csrbank0_scratch3_re = ((builder_minsoc_csrbank0_sel & builder_minsoc_interface0_bank_bus_we) & (builder_minsoc_interface0_bank_bus_adr[3:0] == 1'd1));
assign builder_minsoc_csrbank0_scratch3_we = ((builder_minsoc_csrbank0_sel & (~builder_minsoc_interface0_bank_bus_we)) & (builder_minsoc_interface0_bank_bus_adr[3:0] == 1'd1));
assign builder_minsoc_csrbank0_scratch2_r = builder_minsoc_interface0_bank_bus_dat_w[7:0];
assign builder_minsoc_csrbank0_scratch2_re = ((builder_minsoc_csrbank0_sel & builder_minsoc_interface0_bank_bus_we) & (builder_minsoc_interface0_bank_bus_adr[3:0] == 2'd2));
assign builder_minsoc_csrbank0_scratch2_we = ((builder_minsoc_csrbank0_sel & (~builder_minsoc_interface0_bank_bus_we)) & (builder_minsoc_interface0_bank_bus_adr[3:0] == 2'd2));
assign builder_minsoc_csrbank0_scratch1_r = builder_minsoc_interface0_bank_bus_dat_w[7:0];
assign builder_minsoc_csrbank0_scratch1_re = ((builder_minsoc_csrbank0_sel & builder_minsoc_interface0_bank_bus_we) & (builder_minsoc_interface0_bank_bus_adr[3:0] == 2'd3));
assign builder_minsoc_csrbank0_scratch1_we = ((builder_minsoc_csrbank0_sel & (~builder_minsoc_interface0_bank_bus_we)) & (builder_minsoc_interface0_bank_bus_adr[3:0] == 2'd3));
assign builder_minsoc_csrbank0_scratch0_r = builder_minsoc_interface0_bank_bus_dat_w[7:0];
assign builder_minsoc_csrbank0_scratch0_re = ((builder_minsoc_csrbank0_sel & builder_minsoc_interface0_bank_bus_we) & (builder_minsoc_interface0_bank_bus_adr[3:0] == 3'd4));
assign builder_minsoc_csrbank0_scratch0_we = ((builder_minsoc_csrbank0_sel & (~builder_minsoc_interface0_bank_bus_we)) & (builder_minsoc_interface0_bank_bus_adr[3:0] == 3'd4));
assign builder_minsoc_csrbank0_bus_errors3_r = builder_minsoc_interface0_bank_bus_dat_w[7:0];
assign builder_minsoc_csrbank0_bus_errors3_re = ((builder_minsoc_csrbank0_sel & builder_minsoc_interface0_bank_bus_we) & (builder_minsoc_interface0_bank_bus_adr[3:0] == 3'd5));
assign builder_minsoc_csrbank0_bus_errors3_we = ((builder_minsoc_csrbank0_sel & (~builder_minsoc_interface0_bank_bus_we)) & (builder_minsoc_interface0_bank_bus_adr[3:0] == 3'd5));
assign builder_minsoc_csrbank0_bus_errors2_r = builder_minsoc_interface0_bank_bus_dat_w[7:0];
assign builder_minsoc_csrbank0_bus_errors2_re = ((builder_minsoc_csrbank0_sel & builder_minsoc_interface0_bank_bus_we) & (builder_minsoc_interface0_bank_bus_adr[3:0] == 3'd6));
assign builder_minsoc_csrbank0_bus_errors2_we = ((builder_minsoc_csrbank0_sel & (~builder_minsoc_interface0_bank_bus_we)) & (builder_minsoc_interface0_bank_bus_adr[3:0] == 3'd6));
assign builder_minsoc_csrbank0_bus_errors1_r = builder_minsoc_interface0_bank_bus_dat_w[7:0];
assign builder_minsoc_csrbank0_bus_errors1_re = ((builder_minsoc_csrbank0_sel & builder_minsoc_interface0_bank_bus_we) & (builder_minsoc_interface0_bank_bus_adr[3:0] == 3'd7));
assign builder_minsoc_csrbank0_bus_errors1_we = ((builder_minsoc_csrbank0_sel & (~builder_minsoc_interface0_bank_bus_we)) & (builder_minsoc_interface0_bank_bus_adr[3:0] == 3'd7));
assign builder_minsoc_csrbank0_bus_errors0_r = builder_minsoc_interface0_bank_bus_dat_w[7:0];
assign builder_minsoc_csrbank0_bus_errors0_re = ((builder_minsoc_csrbank0_sel & builder_minsoc_interface0_bank_bus_we) & (builder_minsoc_interface0_bank_bus_adr[3:0] == 4'd8));
assign builder_minsoc_csrbank0_bus_errors0_we = ((builder_minsoc_csrbank0_sel & (~builder_minsoc_interface0_bank_bus_we)) & (builder_minsoc_interface0_bank_bus_adr[3:0] == 4'd8));
assign builder_minsoc_csrbank0_scratch3_w = main_ctrl_storage[31:24];
assign builder_minsoc_csrbank0_scratch2_w = main_ctrl_storage[23:16];
assign builder_minsoc_csrbank0_scratch1_w = main_ctrl_storage[15:8];
assign builder_minsoc_csrbank0_scratch0_w = main_ctrl_storage[7:0];
assign builder_minsoc_csrbank0_bus_errors3_w = main_ctrl_bus_errors_status[31:24];
assign builder_minsoc_csrbank0_bus_errors2_w = main_ctrl_bus_errors_status[23:16];
assign builder_minsoc_csrbank0_bus_errors1_w = main_ctrl_bus_errors_status[15:8];
assign builder_minsoc_csrbank0_bus_errors0_w = main_ctrl_bus_errors_status[7:0];
assign main_ctrl_bus_errors_we = builder_minsoc_csrbank0_bus_errors0_we;
assign builder_minsoc_csrbank1_sel = (builder_minsoc_interface1_bank_bus_adr[13:9] == 3'd5);
assign builder_minsoc_csrbank1_half_sys8x_taps0_r = builder_minsoc_interface1_bank_bus_dat_w[4:0];
assign builder_minsoc_csrbank1_half_sys8x_taps0_re = ((builder_minsoc_csrbank1_sel & builder_minsoc_interface1_bank_bus_we) & (builder_minsoc_interface1_bank_bus_adr[2:0] == 1'd0));
assign builder_minsoc_csrbank1_half_sys8x_taps0_we = ((builder_minsoc_csrbank1_sel & (~builder_minsoc_interface1_bank_bus_we)) & (builder_minsoc_interface1_bank_bus_adr[2:0] == 1'd0));
assign main_a7ddrphy_cdly_rst_r = builder_minsoc_interface1_bank_bus_dat_w[0];
assign main_a7ddrphy_cdly_rst_re = ((builder_minsoc_csrbank1_sel & builder_minsoc_interface1_bank_bus_we) & (builder_minsoc_interface1_bank_bus_adr[2:0] == 1'd1));
assign main_a7ddrphy_cdly_rst_we = ((builder_minsoc_csrbank1_sel & (~builder_minsoc_interface1_bank_bus_we)) & (builder_minsoc_interface1_bank_bus_adr[2:0] == 1'd1));
assign main_a7ddrphy_cdly_inc_r = builder_minsoc_interface1_bank_bus_dat_w[0];
assign main_a7ddrphy_cdly_inc_re = ((builder_minsoc_csrbank1_sel & builder_minsoc_interface1_bank_bus_we) & (builder_minsoc_interface1_bank_bus_adr[2:0] == 2'd2));
assign main_a7ddrphy_cdly_inc_we = ((builder_minsoc_csrbank1_sel & (~builder_minsoc_interface1_bank_bus_we)) & (builder_minsoc_interface1_bank_bus_adr[2:0] == 2'd2));
assign builder_minsoc_csrbank1_dly_sel0_r = builder_minsoc_interface1_bank_bus_dat_w[1:0];
assign builder_minsoc_csrbank1_dly_sel0_re = ((builder_minsoc_csrbank1_sel & builder_minsoc_interface1_bank_bus_we) & (builder_minsoc_interface1_bank_bus_adr[2:0] == 2'd3));
assign builder_minsoc_csrbank1_dly_sel0_we = ((builder_minsoc_csrbank1_sel & (~builder_minsoc_interface1_bank_bus_we)) & (builder_minsoc_interface1_bank_bus_adr[2:0] == 2'd3));
assign main_a7ddrphy_rdly_dq_rst_r = builder_minsoc_interface1_bank_bus_dat_w[0];
assign main_a7ddrphy_rdly_dq_rst_re = ((builder_minsoc_csrbank1_sel & builder_minsoc_interface1_bank_bus_we) & (builder_minsoc_interface1_bank_bus_adr[2:0] == 3'd4));
assign main_a7ddrphy_rdly_dq_rst_we = ((builder_minsoc_csrbank1_sel & (~builder_minsoc_interface1_bank_bus_we)) & (builder_minsoc_interface1_bank_bus_adr[2:0] == 3'd4));
assign main_a7ddrphy_rdly_dq_inc_r = builder_minsoc_interface1_bank_bus_dat_w[0];
assign main_a7ddrphy_rdly_dq_inc_re = ((builder_minsoc_csrbank1_sel & builder_minsoc_interface1_bank_bus_we) & (builder_minsoc_interface1_bank_bus_adr[2:0] == 3'd5));
assign main_a7ddrphy_rdly_dq_inc_we = ((builder_minsoc_csrbank1_sel & (~builder_minsoc_interface1_bank_bus_we)) & (builder_minsoc_interface1_bank_bus_adr[2:0] == 3'd5));
assign main_a7ddrphy_rdly_dq_bitslip_rst_r = builder_minsoc_interface1_bank_bus_dat_w[0];
assign main_a7ddrphy_rdly_dq_bitslip_rst_re = ((builder_minsoc_csrbank1_sel & builder_minsoc_interface1_bank_bus_we) & (builder_minsoc_interface1_bank_bus_adr[2:0] == 3'd6));
assign main_a7ddrphy_rdly_dq_bitslip_rst_we = ((builder_minsoc_csrbank1_sel & (~builder_minsoc_interface1_bank_bus_we)) & (builder_minsoc_interface1_bank_bus_adr[2:0] == 3'd6));
assign main_a7ddrphy_rdly_dq_bitslip_r = builder_minsoc_interface1_bank_bus_dat_w[0];
assign main_a7ddrphy_rdly_dq_bitslip_re = ((builder_minsoc_csrbank1_sel & builder_minsoc_interface1_bank_bus_we) & (builder_minsoc_interface1_bank_bus_adr[2:0] == 3'd7));
assign main_a7ddrphy_rdly_dq_bitslip_we = ((builder_minsoc_csrbank1_sel & (~builder_minsoc_interface1_bank_bus_we)) & (builder_minsoc_interface1_bank_bus_adr[2:0] == 3'd7));
assign builder_minsoc_csrbank1_half_sys8x_taps0_w = main_a7ddrphy_half_sys8x_taps_storage[4:0];
assign builder_minsoc_csrbank1_dly_sel0_w = main_a7ddrphy_dly_sel_storage[1:0];
assign builder_minsoc_csrbank2_sel = (builder_minsoc_interface2_bank_bus_adr[13:9] == 4'd8);
assign builder_minsoc_csrbank2_dfii_control0_r = builder_minsoc_interface2_bank_bus_dat_w[3:0];
assign builder_minsoc_csrbank2_dfii_control0_re = ((builder_minsoc_csrbank2_sel & builder_minsoc_interface2_bank_bus_we) & (builder_minsoc_interface2_bank_bus_adr[5:0] == 1'd0));
assign builder_minsoc_csrbank2_dfii_control0_we = ((builder_minsoc_csrbank2_sel & (~builder_minsoc_interface2_bank_bus_we)) & (builder_minsoc_interface2_bank_bus_adr[5:0] == 1'd0));
assign builder_minsoc_csrbank2_dfii_pi0_command0_r = builder_minsoc_interface2_bank_bus_dat_w[5:0];
assign builder_minsoc_csrbank2_dfii_pi0_command0_re = ((builder_minsoc_csrbank2_sel & builder_minsoc_interface2_bank_bus_we) & (builder_minsoc_interface2_bank_bus_adr[5:0] == 1'd1));
assign builder_minsoc_csrbank2_dfii_pi0_command0_we = ((builder_minsoc_csrbank2_sel & (~builder_minsoc_interface2_bank_bus_we)) & (builder_minsoc_interface2_bank_bus_adr[5:0] == 1'd1));
assign main_sdram_phaseinjector0_command_issue_r = builder_minsoc_interface2_bank_bus_dat_w[0];
assign main_sdram_phaseinjector0_command_issue_re = ((builder_minsoc_csrbank2_sel & builder_minsoc_interface2_bank_bus_we) & (builder_minsoc_interface2_bank_bus_adr[5:0] == 2'd2));
assign main_sdram_phaseinjector0_command_issue_we = ((builder_minsoc_csrbank2_sel & (~builder_minsoc_interface2_bank_bus_we)) & (builder_minsoc_interface2_bank_bus_adr[5:0] == 2'd2));
assign builder_minsoc_csrbank2_dfii_pi0_address1_r = builder_minsoc_interface2_bank_bus_dat_w[5:0];
assign builder_minsoc_csrbank2_dfii_pi0_address1_re = ((builder_minsoc_csrbank2_sel & builder_minsoc_interface2_bank_bus_we) & (builder_minsoc_interface2_bank_bus_adr[5:0] == 2'd3));
assign builder_minsoc_csrbank2_dfii_pi0_address1_we = ((builder_minsoc_csrbank2_sel & (~builder_minsoc_interface2_bank_bus_we)) & (builder_minsoc_interface2_bank_bus_adr[5:0] == 2'd3));
assign builder_minsoc_csrbank2_dfii_pi0_address0_r = builder_minsoc_interface2_bank_bus_dat_w[7:0];
assign builder_minsoc_csrbank2_dfii_pi0_address0_re = ((builder_minsoc_csrbank2_sel & builder_minsoc_interface2_bank_bus_we) & (builder_minsoc_interface2_bank_bus_adr[5:0] == 3'd4));
assign builder_minsoc_csrbank2_dfii_pi0_address0_we = ((builder_minsoc_csrbank2_sel & (~builder_minsoc_interface2_bank_bus_we)) & (builder_minsoc_interface2_bank_bus_adr[5:0] == 3'd4));
assign builder_minsoc_csrbank2_dfii_pi0_baddress0_r = builder_minsoc_interface2_bank_bus_dat_w[2:0];
assign builder_minsoc_csrbank2_dfii_pi0_baddress0_re = ((builder_minsoc_csrbank2_sel & builder_minsoc_interface2_bank_bus_we) & (builder_minsoc_interface2_bank_bus_adr[5:0] == 3'd5));
assign builder_minsoc_csrbank2_dfii_pi0_baddress0_we = ((builder_minsoc_csrbank2_sel & (~builder_minsoc_interface2_bank_bus_we)) & (builder_minsoc_interface2_bank_bus_adr[5:0] == 3'd5));
assign builder_minsoc_csrbank2_dfii_pi0_wrdata3_r = builder_minsoc_interface2_bank_bus_dat_w[7:0];
assign builder_minsoc_csrbank2_dfii_pi0_wrdata3_re = ((builder_minsoc_csrbank2_sel & builder_minsoc_interface2_bank_bus_we) & (builder_minsoc_interface2_bank_bus_adr[5:0] == 3'd6));
assign builder_minsoc_csrbank2_dfii_pi0_wrdata3_we = ((builder_minsoc_csrbank2_sel & (~builder_minsoc_interface2_bank_bus_we)) & (builder_minsoc_interface2_bank_bus_adr[5:0] == 3'd6));
assign builder_minsoc_csrbank2_dfii_pi0_wrdata2_r = builder_minsoc_interface2_bank_bus_dat_w[7:0];
assign builder_minsoc_csrbank2_dfii_pi0_wrdata2_re = ((builder_minsoc_csrbank2_sel & builder_minsoc_interface2_bank_bus_we) & (builder_minsoc_interface2_bank_bus_adr[5:0] == 3'd7));
assign builder_minsoc_csrbank2_dfii_pi0_wrdata2_we = ((builder_minsoc_csrbank2_sel & (~builder_minsoc_interface2_bank_bus_we)) & (builder_minsoc_interface2_bank_bus_adr[5:0] == 3'd7));
assign builder_minsoc_csrbank2_dfii_pi0_wrdata1_r = builder_minsoc_interface2_bank_bus_dat_w[7:0];
assign builder_minsoc_csrbank2_dfii_pi0_wrdata1_re = ((builder_minsoc_csrbank2_sel & builder_minsoc_interface2_bank_bus_we) & (builder_minsoc_interface2_bank_bus_adr[5:0] == 4'd8));
assign builder_minsoc_csrbank2_dfii_pi0_wrdata1_we = ((builder_minsoc_csrbank2_sel & (~builder_minsoc_interface2_bank_bus_we)) & (builder_minsoc_interface2_bank_bus_adr[5:0] == 4'd8));
assign builder_minsoc_csrbank2_dfii_pi0_wrdata0_r = builder_minsoc_interface2_bank_bus_dat_w[7:0];
assign builder_minsoc_csrbank2_dfii_pi0_wrdata0_re = ((builder_minsoc_csrbank2_sel & builder_minsoc_interface2_bank_bus_we) & (builder_minsoc_interface2_bank_bus_adr[5:0] == 4'd9));
assign builder_minsoc_csrbank2_dfii_pi0_wrdata0_we = ((builder_minsoc_csrbank2_sel & (~builder_minsoc_interface2_bank_bus_we)) & (builder_minsoc_interface2_bank_bus_adr[5:0] == 4'd9));
assign builder_minsoc_csrbank2_dfii_pi0_rddata3_r = builder_minsoc_interface2_bank_bus_dat_w[7:0];
assign builder_minsoc_csrbank2_dfii_pi0_rddata3_re = ((builder_minsoc_csrbank2_sel & builder_minsoc_interface2_bank_bus_we) & (builder_minsoc_interface2_bank_bus_adr[5:0] == 4'd10));
assign builder_minsoc_csrbank2_dfii_pi0_rddata3_we = ((builder_minsoc_csrbank2_sel & (~builder_minsoc_interface2_bank_bus_we)) & (builder_minsoc_interface2_bank_bus_adr[5:0] == 4'd10));
assign builder_minsoc_csrbank2_dfii_pi0_rddata2_r = builder_minsoc_interface2_bank_bus_dat_w[7:0];
assign builder_minsoc_csrbank2_dfii_pi0_rddata2_re = ((builder_minsoc_csrbank2_sel & builder_minsoc_interface2_bank_bus_we) & (builder_minsoc_interface2_bank_bus_adr[5:0] == 4'd11));
assign builder_minsoc_csrbank2_dfii_pi0_rddata2_we = ((builder_minsoc_csrbank2_sel & (~builder_minsoc_interface2_bank_bus_we)) & (builder_minsoc_interface2_bank_bus_adr[5:0] == 4'd11));
assign builder_minsoc_csrbank2_dfii_pi0_rddata1_r = builder_minsoc_interface2_bank_bus_dat_w[7:0];
assign builder_minsoc_csrbank2_dfii_pi0_rddata1_re = ((builder_minsoc_csrbank2_sel & builder_minsoc_interface2_bank_bus_we) & (builder_minsoc_interface2_bank_bus_adr[5:0] == 4'd12));
assign builder_minsoc_csrbank2_dfii_pi0_rddata1_we = ((builder_minsoc_csrbank2_sel & (~builder_minsoc_interface2_bank_bus_we)) & (builder_minsoc_interface2_bank_bus_adr[5:0] == 4'd12));
assign builder_minsoc_csrbank2_dfii_pi0_rddata0_r = builder_minsoc_interface2_bank_bus_dat_w[7:0];
assign builder_minsoc_csrbank2_dfii_pi0_rddata0_re = ((builder_minsoc_csrbank2_sel & builder_minsoc_interface2_bank_bus_we) & (builder_minsoc_interface2_bank_bus_adr[5:0] == 4'd13));
assign builder_minsoc_csrbank2_dfii_pi0_rddata0_we = ((builder_minsoc_csrbank2_sel & (~builder_minsoc_interface2_bank_bus_we)) & (builder_minsoc_interface2_bank_bus_adr[5:0] == 4'd13));
assign builder_minsoc_csrbank2_dfii_pi1_command0_r = builder_minsoc_interface2_bank_bus_dat_w[5:0];
assign builder_minsoc_csrbank2_dfii_pi1_command0_re = ((builder_minsoc_csrbank2_sel & builder_minsoc_interface2_bank_bus_we) & (builder_minsoc_interface2_bank_bus_adr[5:0] == 4'd14));
assign builder_minsoc_csrbank2_dfii_pi1_command0_we = ((builder_minsoc_csrbank2_sel & (~builder_minsoc_interface2_bank_bus_we)) & (builder_minsoc_interface2_bank_bus_adr[5:0] == 4'd14));
assign main_sdram_phaseinjector1_command_issue_r = builder_minsoc_interface2_bank_bus_dat_w[0];
assign main_sdram_phaseinjector1_command_issue_re = ((builder_minsoc_csrbank2_sel & builder_minsoc_interface2_bank_bus_we) & (builder_minsoc_interface2_bank_bus_adr[5:0] == 4'd15));
assign main_sdram_phaseinjector1_command_issue_we = ((builder_minsoc_csrbank2_sel & (~builder_minsoc_interface2_bank_bus_we)) & (builder_minsoc_interface2_bank_bus_adr[5:0] == 4'd15));
assign builder_minsoc_csrbank2_dfii_pi1_address1_r = builder_minsoc_interface2_bank_bus_dat_w[5:0];
assign builder_minsoc_csrbank2_dfii_pi1_address1_re = ((builder_minsoc_csrbank2_sel & builder_minsoc_interface2_bank_bus_we) & (builder_minsoc_interface2_bank_bus_adr[5:0] == 5'd16));
assign builder_minsoc_csrbank2_dfii_pi1_address1_we = ((builder_minsoc_csrbank2_sel & (~builder_minsoc_interface2_bank_bus_we)) & (builder_minsoc_interface2_bank_bus_adr[5:0] == 5'd16));
assign builder_minsoc_csrbank2_dfii_pi1_address0_r = builder_minsoc_interface2_bank_bus_dat_w[7:0];
assign builder_minsoc_csrbank2_dfii_pi1_address0_re = ((builder_minsoc_csrbank2_sel & builder_minsoc_interface2_bank_bus_we) & (builder_minsoc_interface2_bank_bus_adr[5:0] == 5'd17));
assign builder_minsoc_csrbank2_dfii_pi1_address0_we = ((builder_minsoc_csrbank2_sel & (~builder_minsoc_interface2_bank_bus_we)) & (builder_minsoc_interface2_bank_bus_adr[5:0] == 5'd17));
assign builder_minsoc_csrbank2_dfii_pi1_baddress0_r = builder_minsoc_interface2_bank_bus_dat_w[2:0];
assign builder_minsoc_csrbank2_dfii_pi1_baddress0_re = ((builder_minsoc_csrbank2_sel & builder_minsoc_interface2_bank_bus_we) & (builder_minsoc_interface2_bank_bus_adr[5:0] == 5'd18));
assign builder_minsoc_csrbank2_dfii_pi1_baddress0_we = ((builder_minsoc_csrbank2_sel & (~builder_minsoc_interface2_bank_bus_we)) & (builder_minsoc_interface2_bank_bus_adr[5:0] == 5'd18));
assign builder_minsoc_csrbank2_dfii_pi1_wrdata3_r = builder_minsoc_interface2_bank_bus_dat_w[7:0];
assign builder_minsoc_csrbank2_dfii_pi1_wrdata3_re = ((builder_minsoc_csrbank2_sel & builder_minsoc_interface2_bank_bus_we) & (builder_minsoc_interface2_bank_bus_adr[5:0] == 5'd19));
assign builder_minsoc_csrbank2_dfii_pi1_wrdata3_we = ((builder_minsoc_csrbank2_sel & (~builder_minsoc_interface2_bank_bus_we)) & (builder_minsoc_interface2_bank_bus_adr[5:0] == 5'd19));
assign builder_minsoc_csrbank2_dfii_pi1_wrdata2_r = builder_minsoc_interface2_bank_bus_dat_w[7:0];
assign builder_minsoc_csrbank2_dfii_pi1_wrdata2_re = ((builder_minsoc_csrbank2_sel & builder_minsoc_interface2_bank_bus_we) & (builder_minsoc_interface2_bank_bus_adr[5:0] == 5'd20));
assign builder_minsoc_csrbank2_dfii_pi1_wrdata2_we = ((builder_minsoc_csrbank2_sel & (~builder_minsoc_interface2_bank_bus_we)) & (builder_minsoc_interface2_bank_bus_adr[5:0] == 5'd20));
assign builder_minsoc_csrbank2_dfii_pi1_wrdata1_r = builder_minsoc_interface2_bank_bus_dat_w[7:0];
assign builder_minsoc_csrbank2_dfii_pi1_wrdata1_re = ((builder_minsoc_csrbank2_sel & builder_minsoc_interface2_bank_bus_we) & (builder_minsoc_interface2_bank_bus_adr[5:0] == 5'd21));
assign builder_minsoc_csrbank2_dfii_pi1_wrdata1_we = ((builder_minsoc_csrbank2_sel & (~builder_minsoc_interface2_bank_bus_we)) & (builder_minsoc_interface2_bank_bus_adr[5:0] == 5'd21));
assign builder_minsoc_csrbank2_dfii_pi1_wrdata0_r = builder_minsoc_interface2_bank_bus_dat_w[7:0];
assign builder_minsoc_csrbank2_dfii_pi1_wrdata0_re = ((builder_minsoc_csrbank2_sel & builder_minsoc_interface2_bank_bus_we) & (builder_minsoc_interface2_bank_bus_adr[5:0] == 5'd22));
assign builder_minsoc_csrbank2_dfii_pi1_wrdata0_we = ((builder_minsoc_csrbank2_sel & (~builder_minsoc_interface2_bank_bus_we)) & (builder_minsoc_interface2_bank_bus_adr[5:0] == 5'd22));
assign builder_minsoc_csrbank2_dfii_pi1_rddata3_r = builder_minsoc_interface2_bank_bus_dat_w[7:0];
assign builder_minsoc_csrbank2_dfii_pi1_rddata3_re = ((builder_minsoc_csrbank2_sel & builder_minsoc_interface2_bank_bus_we) & (builder_minsoc_interface2_bank_bus_adr[5:0] == 5'd23));
assign builder_minsoc_csrbank2_dfii_pi1_rddata3_we = ((builder_minsoc_csrbank2_sel & (~builder_minsoc_interface2_bank_bus_we)) & (builder_minsoc_interface2_bank_bus_adr[5:0] == 5'd23));
assign builder_minsoc_csrbank2_dfii_pi1_rddata2_r = builder_minsoc_interface2_bank_bus_dat_w[7:0];
assign builder_minsoc_csrbank2_dfii_pi1_rddata2_re = ((builder_minsoc_csrbank2_sel & builder_minsoc_interface2_bank_bus_we) & (builder_minsoc_interface2_bank_bus_adr[5:0] == 5'd24));
assign builder_minsoc_csrbank2_dfii_pi1_rddata2_we = ((builder_minsoc_csrbank2_sel & (~builder_minsoc_interface2_bank_bus_we)) & (builder_minsoc_interface2_bank_bus_adr[5:0] == 5'd24));
assign builder_minsoc_csrbank2_dfii_pi1_rddata1_r = builder_minsoc_interface2_bank_bus_dat_w[7:0];
assign builder_minsoc_csrbank2_dfii_pi1_rddata1_re = ((builder_minsoc_csrbank2_sel & builder_minsoc_interface2_bank_bus_we) & (builder_minsoc_interface2_bank_bus_adr[5:0] == 5'd25));
assign builder_minsoc_csrbank2_dfii_pi1_rddata1_we = ((builder_minsoc_csrbank2_sel & (~builder_minsoc_interface2_bank_bus_we)) & (builder_minsoc_interface2_bank_bus_adr[5:0] == 5'd25));
assign builder_minsoc_csrbank2_dfii_pi1_rddata0_r = builder_minsoc_interface2_bank_bus_dat_w[7:0];
assign builder_minsoc_csrbank2_dfii_pi1_rddata0_re = ((builder_minsoc_csrbank2_sel & builder_minsoc_interface2_bank_bus_we) & (builder_minsoc_interface2_bank_bus_adr[5:0] == 5'd26));
assign builder_minsoc_csrbank2_dfii_pi1_rddata0_we = ((builder_minsoc_csrbank2_sel & (~builder_minsoc_interface2_bank_bus_we)) & (builder_minsoc_interface2_bank_bus_adr[5:0] == 5'd26));
assign builder_minsoc_csrbank2_dfii_pi2_command0_r = builder_minsoc_interface2_bank_bus_dat_w[5:0];
assign builder_minsoc_csrbank2_dfii_pi2_command0_re = ((builder_minsoc_csrbank2_sel & builder_minsoc_interface2_bank_bus_we) & (builder_minsoc_interface2_bank_bus_adr[5:0] == 5'd27));
assign builder_minsoc_csrbank2_dfii_pi2_command0_we = ((builder_minsoc_csrbank2_sel & (~builder_minsoc_interface2_bank_bus_we)) & (builder_minsoc_interface2_bank_bus_adr[5:0] == 5'd27));
assign main_sdram_phaseinjector2_command_issue_r = builder_minsoc_interface2_bank_bus_dat_w[0];
assign main_sdram_phaseinjector2_command_issue_re = ((builder_minsoc_csrbank2_sel & builder_minsoc_interface2_bank_bus_we) & (builder_minsoc_interface2_bank_bus_adr[5:0] == 5'd28));
assign main_sdram_phaseinjector2_command_issue_we = ((builder_minsoc_csrbank2_sel & (~builder_minsoc_interface2_bank_bus_we)) & (builder_minsoc_interface2_bank_bus_adr[5:0] == 5'd28));
assign builder_minsoc_csrbank2_dfii_pi2_address1_r = builder_minsoc_interface2_bank_bus_dat_w[5:0];
assign builder_minsoc_csrbank2_dfii_pi2_address1_re = ((builder_minsoc_csrbank2_sel & builder_minsoc_interface2_bank_bus_we) & (builder_minsoc_interface2_bank_bus_adr[5:0] == 5'd29));
assign builder_minsoc_csrbank2_dfii_pi2_address1_we = ((builder_minsoc_csrbank2_sel & (~builder_minsoc_interface2_bank_bus_we)) & (builder_minsoc_interface2_bank_bus_adr[5:0] == 5'd29));
assign builder_minsoc_csrbank2_dfii_pi2_address0_r = builder_minsoc_interface2_bank_bus_dat_w[7:0];
assign builder_minsoc_csrbank2_dfii_pi2_address0_re = ((builder_minsoc_csrbank2_sel & builder_minsoc_interface2_bank_bus_we) & (builder_minsoc_interface2_bank_bus_adr[5:0] == 5'd30));
assign builder_minsoc_csrbank2_dfii_pi2_address0_we = ((builder_minsoc_csrbank2_sel & (~builder_minsoc_interface2_bank_bus_we)) & (builder_minsoc_interface2_bank_bus_adr[5:0] == 5'd30));
assign builder_minsoc_csrbank2_dfii_pi2_baddress0_r = builder_minsoc_interface2_bank_bus_dat_w[2:0];
assign builder_minsoc_csrbank2_dfii_pi2_baddress0_re = ((builder_minsoc_csrbank2_sel & builder_minsoc_interface2_bank_bus_we) & (builder_minsoc_interface2_bank_bus_adr[5:0] == 5'd31));
assign builder_minsoc_csrbank2_dfii_pi2_baddress0_we = ((builder_minsoc_csrbank2_sel & (~builder_minsoc_interface2_bank_bus_we)) & (builder_minsoc_interface2_bank_bus_adr[5:0] == 5'd31));
assign builder_minsoc_csrbank2_dfii_pi2_wrdata3_r = builder_minsoc_interface2_bank_bus_dat_w[7:0];
assign builder_minsoc_csrbank2_dfii_pi2_wrdata3_re = ((builder_minsoc_csrbank2_sel & builder_minsoc_interface2_bank_bus_we) & (builder_minsoc_interface2_bank_bus_adr[5:0] == 6'd32));
assign builder_minsoc_csrbank2_dfii_pi2_wrdata3_we = ((builder_minsoc_csrbank2_sel & (~builder_minsoc_interface2_bank_bus_we)) & (builder_minsoc_interface2_bank_bus_adr[5:0] == 6'd32));
assign builder_minsoc_csrbank2_dfii_pi2_wrdata2_r = builder_minsoc_interface2_bank_bus_dat_w[7:0];
assign builder_minsoc_csrbank2_dfii_pi2_wrdata2_re = ((builder_minsoc_csrbank2_sel & builder_minsoc_interface2_bank_bus_we) & (builder_minsoc_interface2_bank_bus_adr[5:0] == 6'd33));
assign builder_minsoc_csrbank2_dfii_pi2_wrdata2_we = ((builder_minsoc_csrbank2_sel & (~builder_minsoc_interface2_bank_bus_we)) & (builder_minsoc_interface2_bank_bus_adr[5:0] == 6'd33));
assign builder_minsoc_csrbank2_dfii_pi2_wrdata1_r = builder_minsoc_interface2_bank_bus_dat_w[7:0];
assign builder_minsoc_csrbank2_dfii_pi2_wrdata1_re = ((builder_minsoc_csrbank2_sel & builder_minsoc_interface2_bank_bus_we) & (builder_minsoc_interface2_bank_bus_adr[5:0] == 6'd34));
assign builder_minsoc_csrbank2_dfii_pi2_wrdata1_we = ((builder_minsoc_csrbank2_sel & (~builder_minsoc_interface2_bank_bus_we)) & (builder_minsoc_interface2_bank_bus_adr[5:0] == 6'd34));
assign builder_minsoc_csrbank2_dfii_pi2_wrdata0_r = builder_minsoc_interface2_bank_bus_dat_w[7:0];
assign builder_minsoc_csrbank2_dfii_pi2_wrdata0_re = ((builder_minsoc_csrbank2_sel & builder_minsoc_interface2_bank_bus_we) & (builder_minsoc_interface2_bank_bus_adr[5:0] == 6'd35));
assign builder_minsoc_csrbank2_dfii_pi2_wrdata0_we = ((builder_minsoc_csrbank2_sel & (~builder_minsoc_interface2_bank_bus_we)) & (builder_minsoc_interface2_bank_bus_adr[5:0] == 6'd35));
assign builder_minsoc_csrbank2_dfii_pi2_rddata3_r = builder_minsoc_interface2_bank_bus_dat_w[7:0];
assign builder_minsoc_csrbank2_dfii_pi2_rddata3_re = ((builder_minsoc_csrbank2_sel & builder_minsoc_interface2_bank_bus_we) & (builder_minsoc_interface2_bank_bus_adr[5:0] == 6'd36));
assign builder_minsoc_csrbank2_dfii_pi2_rddata3_we = ((builder_minsoc_csrbank2_sel & (~builder_minsoc_interface2_bank_bus_we)) & (builder_minsoc_interface2_bank_bus_adr[5:0] == 6'd36));
assign builder_minsoc_csrbank2_dfii_pi2_rddata2_r = builder_minsoc_interface2_bank_bus_dat_w[7:0];
assign builder_minsoc_csrbank2_dfii_pi2_rddata2_re = ((builder_minsoc_csrbank2_sel & builder_minsoc_interface2_bank_bus_we) & (builder_minsoc_interface2_bank_bus_adr[5:0] == 6'd37));
assign builder_minsoc_csrbank2_dfii_pi2_rddata2_we = ((builder_minsoc_csrbank2_sel & (~builder_minsoc_interface2_bank_bus_we)) & (builder_minsoc_interface2_bank_bus_adr[5:0] == 6'd37));
assign builder_minsoc_csrbank2_dfii_pi2_rddata1_r = builder_minsoc_interface2_bank_bus_dat_w[7:0];
assign builder_minsoc_csrbank2_dfii_pi2_rddata1_re = ((builder_minsoc_csrbank2_sel & builder_minsoc_interface2_bank_bus_we) & (builder_minsoc_interface2_bank_bus_adr[5:0] == 6'd38));
assign builder_minsoc_csrbank2_dfii_pi2_rddata1_we = ((builder_minsoc_csrbank2_sel & (~builder_minsoc_interface2_bank_bus_we)) & (builder_minsoc_interface2_bank_bus_adr[5:0] == 6'd38));
assign builder_minsoc_csrbank2_dfii_pi2_rddata0_r = builder_minsoc_interface2_bank_bus_dat_w[7:0];
assign builder_minsoc_csrbank2_dfii_pi2_rddata0_re = ((builder_minsoc_csrbank2_sel & builder_minsoc_interface2_bank_bus_we) & (builder_minsoc_interface2_bank_bus_adr[5:0] == 6'd39));
assign builder_minsoc_csrbank2_dfii_pi2_rddata0_we = ((builder_minsoc_csrbank2_sel & (~builder_minsoc_interface2_bank_bus_we)) & (builder_minsoc_interface2_bank_bus_adr[5:0] == 6'd39));
assign builder_minsoc_csrbank2_dfii_pi3_command0_r = builder_minsoc_interface2_bank_bus_dat_w[5:0];
assign builder_minsoc_csrbank2_dfii_pi3_command0_re = ((builder_minsoc_csrbank2_sel & builder_minsoc_interface2_bank_bus_we) & (builder_minsoc_interface2_bank_bus_adr[5:0] == 6'd40));
assign builder_minsoc_csrbank2_dfii_pi3_command0_we = ((builder_minsoc_csrbank2_sel & (~builder_minsoc_interface2_bank_bus_we)) & (builder_minsoc_interface2_bank_bus_adr[5:0] == 6'd40));
assign main_sdram_phaseinjector3_command_issue_r = builder_minsoc_interface2_bank_bus_dat_w[0];
assign main_sdram_phaseinjector3_command_issue_re = ((builder_minsoc_csrbank2_sel & builder_minsoc_interface2_bank_bus_we) & (builder_minsoc_interface2_bank_bus_adr[5:0] == 6'd41));
assign main_sdram_phaseinjector3_command_issue_we = ((builder_minsoc_csrbank2_sel & (~builder_minsoc_interface2_bank_bus_we)) & (builder_minsoc_interface2_bank_bus_adr[5:0] == 6'd41));
assign builder_minsoc_csrbank2_dfii_pi3_address1_r = builder_minsoc_interface2_bank_bus_dat_w[5:0];
assign builder_minsoc_csrbank2_dfii_pi3_address1_re = ((builder_minsoc_csrbank2_sel & builder_minsoc_interface2_bank_bus_we) & (builder_minsoc_interface2_bank_bus_adr[5:0] == 6'd42));
assign builder_minsoc_csrbank2_dfii_pi3_address1_we = ((builder_minsoc_csrbank2_sel & (~builder_minsoc_interface2_bank_bus_we)) & (builder_minsoc_interface2_bank_bus_adr[5:0] == 6'd42));
assign builder_minsoc_csrbank2_dfii_pi3_address0_r = builder_minsoc_interface2_bank_bus_dat_w[7:0];
assign builder_minsoc_csrbank2_dfii_pi3_address0_re = ((builder_minsoc_csrbank2_sel & builder_minsoc_interface2_bank_bus_we) & (builder_minsoc_interface2_bank_bus_adr[5:0] == 6'd43));
assign builder_minsoc_csrbank2_dfii_pi3_address0_we = ((builder_minsoc_csrbank2_sel & (~builder_minsoc_interface2_bank_bus_we)) & (builder_minsoc_interface2_bank_bus_adr[5:0] == 6'd43));
assign builder_minsoc_csrbank2_dfii_pi3_baddress0_r = builder_minsoc_interface2_bank_bus_dat_w[2:0];
assign builder_minsoc_csrbank2_dfii_pi3_baddress0_re = ((builder_minsoc_csrbank2_sel & builder_minsoc_interface2_bank_bus_we) & (builder_minsoc_interface2_bank_bus_adr[5:0] == 6'd44));
assign builder_minsoc_csrbank2_dfii_pi3_baddress0_we = ((builder_minsoc_csrbank2_sel & (~builder_minsoc_interface2_bank_bus_we)) & (builder_minsoc_interface2_bank_bus_adr[5:0] == 6'd44));
assign builder_minsoc_csrbank2_dfii_pi3_wrdata3_r = builder_minsoc_interface2_bank_bus_dat_w[7:0];
assign builder_minsoc_csrbank2_dfii_pi3_wrdata3_re = ((builder_minsoc_csrbank2_sel & builder_minsoc_interface2_bank_bus_we) & (builder_minsoc_interface2_bank_bus_adr[5:0] == 6'd45));
assign builder_minsoc_csrbank2_dfii_pi3_wrdata3_we = ((builder_minsoc_csrbank2_sel & (~builder_minsoc_interface2_bank_bus_we)) & (builder_minsoc_interface2_bank_bus_adr[5:0] == 6'd45));
assign builder_minsoc_csrbank2_dfii_pi3_wrdata2_r = builder_minsoc_interface2_bank_bus_dat_w[7:0];
assign builder_minsoc_csrbank2_dfii_pi3_wrdata2_re = ((builder_minsoc_csrbank2_sel & builder_minsoc_interface2_bank_bus_we) & (builder_minsoc_interface2_bank_bus_adr[5:0] == 6'd46));
assign builder_minsoc_csrbank2_dfii_pi3_wrdata2_we = ((builder_minsoc_csrbank2_sel & (~builder_minsoc_interface2_bank_bus_we)) & (builder_minsoc_interface2_bank_bus_adr[5:0] == 6'd46));
assign builder_minsoc_csrbank2_dfii_pi3_wrdata1_r = builder_minsoc_interface2_bank_bus_dat_w[7:0];
assign builder_minsoc_csrbank2_dfii_pi3_wrdata1_re = ((builder_minsoc_csrbank2_sel & builder_minsoc_interface2_bank_bus_we) & (builder_minsoc_interface2_bank_bus_adr[5:0] == 6'd47));
assign builder_minsoc_csrbank2_dfii_pi3_wrdata1_we = ((builder_minsoc_csrbank2_sel & (~builder_minsoc_interface2_bank_bus_we)) & (builder_minsoc_interface2_bank_bus_adr[5:0] == 6'd47));
assign builder_minsoc_csrbank2_dfii_pi3_wrdata0_r = builder_minsoc_interface2_bank_bus_dat_w[7:0];
assign builder_minsoc_csrbank2_dfii_pi3_wrdata0_re = ((builder_minsoc_csrbank2_sel & builder_minsoc_interface2_bank_bus_we) & (builder_minsoc_interface2_bank_bus_adr[5:0] == 6'd48));
assign builder_minsoc_csrbank2_dfii_pi3_wrdata0_we = ((builder_minsoc_csrbank2_sel & (~builder_minsoc_interface2_bank_bus_we)) & (builder_minsoc_interface2_bank_bus_adr[5:0] == 6'd48));
assign builder_minsoc_csrbank2_dfii_pi3_rddata3_r = builder_minsoc_interface2_bank_bus_dat_w[7:0];
assign builder_minsoc_csrbank2_dfii_pi3_rddata3_re = ((builder_minsoc_csrbank2_sel & builder_minsoc_interface2_bank_bus_we) & (builder_minsoc_interface2_bank_bus_adr[5:0] == 6'd49));
assign builder_minsoc_csrbank2_dfii_pi3_rddata3_we = ((builder_minsoc_csrbank2_sel & (~builder_minsoc_interface2_bank_bus_we)) & (builder_minsoc_interface2_bank_bus_adr[5:0] == 6'd49));
assign builder_minsoc_csrbank2_dfii_pi3_rddata2_r = builder_minsoc_interface2_bank_bus_dat_w[7:0];
assign builder_minsoc_csrbank2_dfii_pi3_rddata2_re = ((builder_minsoc_csrbank2_sel & builder_minsoc_interface2_bank_bus_we) & (builder_minsoc_interface2_bank_bus_adr[5:0] == 6'd50));
assign builder_minsoc_csrbank2_dfii_pi3_rddata2_we = ((builder_minsoc_csrbank2_sel & (~builder_minsoc_interface2_bank_bus_we)) & (builder_minsoc_interface2_bank_bus_adr[5:0] == 6'd50));
assign builder_minsoc_csrbank2_dfii_pi3_rddata1_r = builder_minsoc_interface2_bank_bus_dat_w[7:0];
assign builder_minsoc_csrbank2_dfii_pi3_rddata1_re = ((builder_minsoc_csrbank2_sel & builder_minsoc_interface2_bank_bus_we) & (builder_minsoc_interface2_bank_bus_adr[5:0] == 6'd51));
assign builder_minsoc_csrbank2_dfii_pi3_rddata1_we = ((builder_minsoc_csrbank2_sel & (~builder_minsoc_interface2_bank_bus_we)) & (builder_minsoc_interface2_bank_bus_adr[5:0] == 6'd51));
assign builder_minsoc_csrbank2_dfii_pi3_rddata0_r = builder_minsoc_interface2_bank_bus_dat_w[7:0];
assign builder_minsoc_csrbank2_dfii_pi3_rddata0_re = ((builder_minsoc_csrbank2_sel & builder_minsoc_interface2_bank_bus_we) & (builder_minsoc_interface2_bank_bus_adr[5:0] == 6'd52));
assign builder_minsoc_csrbank2_dfii_pi3_rddata0_we = ((builder_minsoc_csrbank2_sel & (~builder_minsoc_interface2_bank_bus_we)) & (builder_minsoc_interface2_bank_bus_adr[5:0] == 6'd52));
assign builder_minsoc_csrbank2_dfii_control0_w = main_sdram_storage[3:0];
assign builder_minsoc_csrbank2_dfii_pi0_command0_w = main_sdram_phaseinjector0_command_storage[5:0];
assign builder_minsoc_csrbank2_dfii_pi0_address1_w = main_sdram_phaseinjector0_address_storage[13:8];
assign builder_minsoc_csrbank2_dfii_pi0_address0_w = main_sdram_phaseinjector0_address_storage[7:0];
assign builder_minsoc_csrbank2_dfii_pi0_baddress0_w = main_sdram_phaseinjector0_baddress_storage[2:0];
assign builder_minsoc_csrbank2_dfii_pi0_wrdata3_w = main_sdram_phaseinjector0_wrdata_storage[31:24];
assign builder_minsoc_csrbank2_dfii_pi0_wrdata2_w = main_sdram_phaseinjector0_wrdata_storage[23:16];
assign builder_minsoc_csrbank2_dfii_pi0_wrdata1_w = main_sdram_phaseinjector0_wrdata_storage[15:8];
assign builder_minsoc_csrbank2_dfii_pi0_wrdata0_w = main_sdram_phaseinjector0_wrdata_storage[7:0];
assign builder_minsoc_csrbank2_dfii_pi0_rddata3_w = main_sdram_phaseinjector0_status[31:24];
assign builder_minsoc_csrbank2_dfii_pi0_rddata2_w = main_sdram_phaseinjector0_status[23:16];
assign builder_minsoc_csrbank2_dfii_pi0_rddata1_w = main_sdram_phaseinjector0_status[15:8];
assign builder_minsoc_csrbank2_dfii_pi0_rddata0_w = main_sdram_phaseinjector0_status[7:0];
assign main_sdram_phaseinjector0_we = builder_minsoc_csrbank2_dfii_pi0_rddata0_we;
assign builder_minsoc_csrbank2_dfii_pi1_command0_w = main_sdram_phaseinjector1_command_storage[5:0];
assign builder_minsoc_csrbank2_dfii_pi1_address1_w = main_sdram_phaseinjector1_address_storage[13:8];
assign builder_minsoc_csrbank2_dfii_pi1_address0_w = main_sdram_phaseinjector1_address_storage[7:0];
assign builder_minsoc_csrbank2_dfii_pi1_baddress0_w = main_sdram_phaseinjector1_baddress_storage[2:0];
assign builder_minsoc_csrbank2_dfii_pi1_wrdata3_w = main_sdram_phaseinjector1_wrdata_storage[31:24];
assign builder_minsoc_csrbank2_dfii_pi1_wrdata2_w = main_sdram_phaseinjector1_wrdata_storage[23:16];
assign builder_minsoc_csrbank2_dfii_pi1_wrdata1_w = main_sdram_phaseinjector1_wrdata_storage[15:8];
assign builder_minsoc_csrbank2_dfii_pi1_wrdata0_w = main_sdram_phaseinjector1_wrdata_storage[7:0];
assign builder_minsoc_csrbank2_dfii_pi1_rddata3_w = main_sdram_phaseinjector1_status[31:24];
assign builder_minsoc_csrbank2_dfii_pi1_rddata2_w = main_sdram_phaseinjector1_status[23:16];
assign builder_minsoc_csrbank2_dfii_pi1_rddata1_w = main_sdram_phaseinjector1_status[15:8];
assign builder_minsoc_csrbank2_dfii_pi1_rddata0_w = main_sdram_phaseinjector1_status[7:0];
assign main_sdram_phaseinjector1_we = builder_minsoc_csrbank2_dfii_pi1_rddata0_we;
assign builder_minsoc_csrbank2_dfii_pi2_command0_w = main_sdram_phaseinjector2_command_storage[5:0];
assign builder_minsoc_csrbank2_dfii_pi2_address1_w = main_sdram_phaseinjector2_address_storage[13:8];
assign builder_minsoc_csrbank2_dfii_pi2_address0_w = main_sdram_phaseinjector2_address_storage[7:0];
assign builder_minsoc_csrbank2_dfii_pi2_baddress0_w = main_sdram_phaseinjector2_baddress_storage[2:0];
assign builder_minsoc_csrbank2_dfii_pi2_wrdata3_w = main_sdram_phaseinjector2_wrdata_storage[31:24];
assign builder_minsoc_csrbank2_dfii_pi2_wrdata2_w = main_sdram_phaseinjector2_wrdata_storage[23:16];
assign builder_minsoc_csrbank2_dfii_pi2_wrdata1_w = main_sdram_phaseinjector2_wrdata_storage[15:8];
assign builder_minsoc_csrbank2_dfii_pi2_wrdata0_w = main_sdram_phaseinjector2_wrdata_storage[7:0];
assign builder_minsoc_csrbank2_dfii_pi2_rddata3_w = main_sdram_phaseinjector2_status[31:24];
assign builder_minsoc_csrbank2_dfii_pi2_rddata2_w = main_sdram_phaseinjector2_status[23:16];
assign builder_minsoc_csrbank2_dfii_pi2_rddata1_w = main_sdram_phaseinjector2_status[15:8];
assign builder_minsoc_csrbank2_dfii_pi2_rddata0_w = main_sdram_phaseinjector2_status[7:0];
assign main_sdram_phaseinjector2_we = builder_minsoc_csrbank2_dfii_pi2_rddata0_we;
assign builder_minsoc_csrbank2_dfii_pi3_command0_w = main_sdram_phaseinjector3_command_storage[5:0];
assign builder_minsoc_csrbank2_dfii_pi3_address1_w = main_sdram_phaseinjector3_address_storage[13:8];
assign builder_minsoc_csrbank2_dfii_pi3_address0_w = main_sdram_phaseinjector3_address_storage[7:0];
assign builder_minsoc_csrbank2_dfii_pi3_baddress0_w = main_sdram_phaseinjector3_baddress_storage[2:0];
assign builder_minsoc_csrbank2_dfii_pi3_wrdata3_w = main_sdram_phaseinjector3_wrdata_storage[31:24];
assign builder_minsoc_csrbank2_dfii_pi3_wrdata2_w = main_sdram_phaseinjector3_wrdata_storage[23:16];
assign builder_minsoc_csrbank2_dfii_pi3_wrdata1_w = main_sdram_phaseinjector3_wrdata_storage[15:8];
assign builder_minsoc_csrbank2_dfii_pi3_wrdata0_w = main_sdram_phaseinjector3_wrdata_storage[7:0];
assign builder_minsoc_csrbank2_dfii_pi3_rddata3_w = main_sdram_phaseinjector3_status[31:24];
assign builder_minsoc_csrbank2_dfii_pi3_rddata2_w = main_sdram_phaseinjector3_status[23:16];
assign builder_minsoc_csrbank2_dfii_pi3_rddata1_w = main_sdram_phaseinjector3_status[15:8];
assign builder_minsoc_csrbank2_dfii_pi3_rddata0_w = main_sdram_phaseinjector3_status[7:0];
assign main_sdram_phaseinjector3_we = builder_minsoc_csrbank2_dfii_pi3_rddata0_we;
assign builder_minsoc_csrbank3_sel = (builder_minsoc_interface3_bank_bus_adr[13:9] == 3'd4);
assign builder_minsoc_csrbank3_load3_r = builder_minsoc_interface3_bank_bus_dat_w[7:0];
assign builder_minsoc_csrbank3_load3_re = ((builder_minsoc_csrbank3_sel & builder_minsoc_interface3_bank_bus_we) & (builder_minsoc_interface3_bank_bus_adr[4:0] == 1'd0));
assign builder_minsoc_csrbank3_load3_we = ((builder_minsoc_csrbank3_sel & (~builder_minsoc_interface3_bank_bus_we)) & (builder_minsoc_interface3_bank_bus_adr[4:0] == 1'd0));
assign builder_minsoc_csrbank3_load2_r = builder_minsoc_interface3_bank_bus_dat_w[7:0];
assign builder_minsoc_csrbank3_load2_re = ((builder_minsoc_csrbank3_sel & builder_minsoc_interface3_bank_bus_we) & (builder_minsoc_interface3_bank_bus_adr[4:0] == 1'd1));
assign builder_minsoc_csrbank3_load2_we = ((builder_minsoc_csrbank3_sel & (~builder_minsoc_interface3_bank_bus_we)) & (builder_minsoc_interface3_bank_bus_adr[4:0] == 1'd1));
assign builder_minsoc_csrbank3_load1_r = builder_minsoc_interface3_bank_bus_dat_w[7:0];
assign builder_minsoc_csrbank3_load1_re = ((builder_minsoc_csrbank3_sel & builder_minsoc_interface3_bank_bus_we) & (builder_minsoc_interface3_bank_bus_adr[4:0] == 2'd2));
assign builder_minsoc_csrbank3_load1_we = ((builder_minsoc_csrbank3_sel & (~builder_minsoc_interface3_bank_bus_we)) & (builder_minsoc_interface3_bank_bus_adr[4:0] == 2'd2));
assign builder_minsoc_csrbank3_load0_r = builder_minsoc_interface3_bank_bus_dat_w[7:0];
assign builder_minsoc_csrbank3_load0_re = ((builder_minsoc_csrbank3_sel & builder_minsoc_interface3_bank_bus_we) & (builder_minsoc_interface3_bank_bus_adr[4:0] == 2'd3));
assign builder_minsoc_csrbank3_load0_we = ((builder_minsoc_csrbank3_sel & (~builder_minsoc_interface3_bank_bus_we)) & (builder_minsoc_interface3_bank_bus_adr[4:0] == 2'd3));
assign builder_minsoc_csrbank3_reload3_r = builder_minsoc_interface3_bank_bus_dat_w[7:0];
assign builder_minsoc_csrbank3_reload3_re = ((builder_minsoc_csrbank3_sel & builder_minsoc_interface3_bank_bus_we) & (builder_minsoc_interface3_bank_bus_adr[4:0] == 3'd4));
assign builder_minsoc_csrbank3_reload3_we = ((builder_minsoc_csrbank3_sel & (~builder_minsoc_interface3_bank_bus_we)) & (builder_minsoc_interface3_bank_bus_adr[4:0] == 3'd4));
assign builder_minsoc_csrbank3_reload2_r = builder_minsoc_interface3_bank_bus_dat_w[7:0];
assign builder_minsoc_csrbank3_reload2_re = ((builder_minsoc_csrbank3_sel & builder_minsoc_interface3_bank_bus_we) & (builder_minsoc_interface3_bank_bus_adr[4:0] == 3'd5));
assign builder_minsoc_csrbank3_reload2_we = ((builder_minsoc_csrbank3_sel & (~builder_minsoc_interface3_bank_bus_we)) & (builder_minsoc_interface3_bank_bus_adr[4:0] == 3'd5));
assign builder_minsoc_csrbank3_reload1_r = builder_minsoc_interface3_bank_bus_dat_w[7:0];
assign builder_minsoc_csrbank3_reload1_re = ((builder_minsoc_csrbank3_sel & builder_minsoc_interface3_bank_bus_we) & (builder_minsoc_interface3_bank_bus_adr[4:0] == 3'd6));
assign builder_minsoc_csrbank3_reload1_we = ((builder_minsoc_csrbank3_sel & (~builder_minsoc_interface3_bank_bus_we)) & (builder_minsoc_interface3_bank_bus_adr[4:0] == 3'd6));
assign builder_minsoc_csrbank3_reload0_r = builder_minsoc_interface3_bank_bus_dat_w[7:0];
assign builder_minsoc_csrbank3_reload0_re = ((builder_minsoc_csrbank3_sel & builder_minsoc_interface3_bank_bus_we) & (builder_minsoc_interface3_bank_bus_adr[4:0] == 3'd7));
assign builder_minsoc_csrbank3_reload0_we = ((builder_minsoc_csrbank3_sel & (~builder_minsoc_interface3_bank_bus_we)) & (builder_minsoc_interface3_bank_bus_adr[4:0] == 3'd7));
assign builder_minsoc_csrbank3_en0_r = builder_minsoc_interface3_bank_bus_dat_w[0];
assign builder_minsoc_csrbank3_en0_re = ((builder_minsoc_csrbank3_sel & builder_minsoc_interface3_bank_bus_we) & (builder_minsoc_interface3_bank_bus_adr[4:0] == 4'd8));
assign builder_minsoc_csrbank3_en0_we = ((builder_minsoc_csrbank3_sel & (~builder_minsoc_interface3_bank_bus_we)) & (builder_minsoc_interface3_bank_bus_adr[4:0] == 4'd8));
assign builder_minsoc_csrbank3_update_value0_r = builder_minsoc_interface3_bank_bus_dat_w[0];
assign builder_minsoc_csrbank3_update_value0_re = ((builder_minsoc_csrbank3_sel & builder_minsoc_interface3_bank_bus_we) & (builder_minsoc_interface3_bank_bus_adr[4:0] == 4'd9));
assign builder_minsoc_csrbank3_update_value0_we = ((builder_minsoc_csrbank3_sel & (~builder_minsoc_interface3_bank_bus_we)) & (builder_minsoc_interface3_bank_bus_adr[4:0] == 4'd9));
assign builder_minsoc_csrbank3_value3_r = builder_minsoc_interface3_bank_bus_dat_w[7:0];
assign builder_minsoc_csrbank3_value3_re = ((builder_minsoc_csrbank3_sel & builder_minsoc_interface3_bank_bus_we) & (builder_minsoc_interface3_bank_bus_adr[4:0] == 4'd10));
assign builder_minsoc_csrbank3_value3_we = ((builder_minsoc_csrbank3_sel & (~builder_minsoc_interface3_bank_bus_we)) & (builder_minsoc_interface3_bank_bus_adr[4:0] == 4'd10));
assign builder_minsoc_csrbank3_value2_r = builder_minsoc_interface3_bank_bus_dat_w[7:0];
assign builder_minsoc_csrbank3_value2_re = ((builder_minsoc_csrbank3_sel & builder_minsoc_interface3_bank_bus_we) & (builder_minsoc_interface3_bank_bus_adr[4:0] == 4'd11));
assign builder_minsoc_csrbank3_value2_we = ((builder_minsoc_csrbank3_sel & (~builder_minsoc_interface3_bank_bus_we)) & (builder_minsoc_interface3_bank_bus_adr[4:0] == 4'd11));
assign builder_minsoc_csrbank3_value1_r = builder_minsoc_interface3_bank_bus_dat_w[7:0];
assign builder_minsoc_csrbank3_value1_re = ((builder_minsoc_csrbank3_sel & builder_minsoc_interface3_bank_bus_we) & (builder_minsoc_interface3_bank_bus_adr[4:0] == 4'd12));
assign builder_minsoc_csrbank3_value1_we = ((builder_minsoc_csrbank3_sel & (~builder_minsoc_interface3_bank_bus_we)) & (builder_minsoc_interface3_bank_bus_adr[4:0] == 4'd12));
assign builder_minsoc_csrbank3_value0_r = builder_minsoc_interface3_bank_bus_dat_w[7:0];
assign builder_minsoc_csrbank3_value0_re = ((builder_minsoc_csrbank3_sel & builder_minsoc_interface3_bank_bus_we) & (builder_minsoc_interface3_bank_bus_adr[4:0] == 4'd13));
assign builder_minsoc_csrbank3_value0_we = ((builder_minsoc_csrbank3_sel & (~builder_minsoc_interface3_bank_bus_we)) & (builder_minsoc_interface3_bank_bus_adr[4:0] == 4'd13));
assign main_timer0_eventmanager_status_r = builder_minsoc_interface3_bank_bus_dat_w[0];
assign main_timer0_eventmanager_status_re = ((builder_minsoc_csrbank3_sel & builder_minsoc_interface3_bank_bus_we) & (builder_minsoc_interface3_bank_bus_adr[4:0] == 4'd14));
assign main_timer0_eventmanager_status_we = ((builder_minsoc_csrbank3_sel & (~builder_minsoc_interface3_bank_bus_we)) & (builder_minsoc_interface3_bank_bus_adr[4:0] == 4'd14));
assign main_timer0_eventmanager_pending_r = builder_minsoc_interface3_bank_bus_dat_w[0];
assign main_timer0_eventmanager_pending_re = ((builder_minsoc_csrbank3_sel & builder_minsoc_interface3_bank_bus_we) & (builder_minsoc_interface3_bank_bus_adr[4:0] == 4'd15));
assign main_timer0_eventmanager_pending_we = ((builder_minsoc_csrbank3_sel & (~builder_minsoc_interface3_bank_bus_we)) & (builder_minsoc_interface3_bank_bus_adr[4:0] == 4'd15));
assign builder_minsoc_csrbank3_ev_enable0_r = builder_minsoc_interface3_bank_bus_dat_w[0];
assign builder_minsoc_csrbank3_ev_enable0_re = ((builder_minsoc_csrbank3_sel & builder_minsoc_interface3_bank_bus_we) & (builder_minsoc_interface3_bank_bus_adr[4:0] == 5'd16));
assign builder_minsoc_csrbank3_ev_enable0_we = ((builder_minsoc_csrbank3_sel & (~builder_minsoc_interface3_bank_bus_we)) & (builder_minsoc_interface3_bank_bus_adr[4:0] == 5'd16));
assign builder_minsoc_csrbank3_load3_w = main_timer0_load_storage[31:24];
assign builder_minsoc_csrbank3_load2_w = main_timer0_load_storage[23:16];
assign builder_minsoc_csrbank3_load1_w = main_timer0_load_storage[15:8];
assign builder_minsoc_csrbank3_load0_w = main_timer0_load_storage[7:0];
assign builder_minsoc_csrbank3_reload3_w = main_timer0_reload_storage[31:24];
assign builder_minsoc_csrbank3_reload2_w = main_timer0_reload_storage[23:16];
assign builder_minsoc_csrbank3_reload1_w = main_timer0_reload_storage[15:8];
assign builder_minsoc_csrbank3_reload0_w = main_timer0_reload_storage[7:0];
assign builder_minsoc_csrbank3_en0_w = main_timer0_en_storage;
assign builder_minsoc_csrbank3_update_value0_w = main_timer0_update_value_storage;
assign builder_minsoc_csrbank3_value3_w = main_timer0_value_status[31:24];
assign builder_minsoc_csrbank3_value2_w = main_timer0_value_status[23:16];
assign builder_minsoc_csrbank3_value1_w = main_timer0_value_status[15:8];
assign builder_minsoc_csrbank3_value0_w = main_timer0_value_status[7:0];
assign main_timer0_value_we = builder_minsoc_csrbank3_value0_we;
assign builder_minsoc_csrbank3_ev_enable0_w = main_timer0_eventmanager_storage;
assign builder_minsoc_csrbank4_sel = (builder_minsoc_interface4_bank_bus_adr[13:9] == 2'd3);
assign main_uart_rxtx_r = builder_minsoc_interface4_bank_bus_dat_w[7:0];
assign main_uart_rxtx_re = ((builder_minsoc_csrbank4_sel & builder_minsoc_interface4_bank_bus_we) & (builder_minsoc_interface4_bank_bus_adr[2:0] == 1'd0));
assign main_uart_rxtx_we = ((builder_minsoc_csrbank4_sel & (~builder_minsoc_interface4_bank_bus_we)) & (builder_minsoc_interface4_bank_bus_adr[2:0] == 1'd0));
assign builder_minsoc_csrbank4_txfull_r = builder_minsoc_interface4_bank_bus_dat_w[0];
assign builder_minsoc_csrbank4_txfull_re = ((builder_minsoc_csrbank4_sel & builder_minsoc_interface4_bank_bus_we) & (builder_minsoc_interface4_bank_bus_adr[2:0] == 1'd1));
assign builder_minsoc_csrbank4_txfull_we = ((builder_minsoc_csrbank4_sel & (~builder_minsoc_interface4_bank_bus_we)) & (builder_minsoc_interface4_bank_bus_adr[2:0] == 1'd1));
assign builder_minsoc_csrbank4_rxempty_r = builder_minsoc_interface4_bank_bus_dat_w[0];
assign builder_minsoc_csrbank4_rxempty_re = ((builder_minsoc_csrbank4_sel & builder_minsoc_interface4_bank_bus_we) & (builder_minsoc_interface4_bank_bus_adr[2:0] == 2'd2));
assign builder_minsoc_csrbank4_rxempty_we = ((builder_minsoc_csrbank4_sel & (~builder_minsoc_interface4_bank_bus_we)) & (builder_minsoc_interface4_bank_bus_adr[2:0] == 2'd2));
assign main_uart_eventmanager_status_r = builder_minsoc_interface4_bank_bus_dat_w[1:0];
assign main_uart_eventmanager_status_re = ((builder_minsoc_csrbank4_sel & builder_minsoc_interface4_bank_bus_we) & (builder_minsoc_interface4_bank_bus_adr[2:0] == 2'd3));
assign main_uart_eventmanager_status_we = ((builder_minsoc_csrbank4_sel & (~builder_minsoc_interface4_bank_bus_we)) & (builder_minsoc_interface4_bank_bus_adr[2:0] == 2'd3));
assign main_uart_eventmanager_pending_r = builder_minsoc_interface4_bank_bus_dat_w[1:0];
assign main_uart_eventmanager_pending_re = ((builder_minsoc_csrbank4_sel & builder_minsoc_interface4_bank_bus_we) & (builder_minsoc_interface4_bank_bus_adr[2:0] == 3'd4));
assign main_uart_eventmanager_pending_we = ((builder_minsoc_csrbank4_sel & (~builder_minsoc_interface4_bank_bus_we)) & (builder_minsoc_interface4_bank_bus_adr[2:0] == 3'd4));
assign builder_minsoc_csrbank4_ev_enable0_r = builder_minsoc_interface4_bank_bus_dat_w[1:0];
assign builder_minsoc_csrbank4_ev_enable0_re = ((builder_minsoc_csrbank4_sel & builder_minsoc_interface4_bank_bus_we) & (builder_minsoc_interface4_bank_bus_adr[2:0] == 3'd5));
assign builder_minsoc_csrbank4_ev_enable0_we = ((builder_minsoc_csrbank4_sel & (~builder_minsoc_interface4_bank_bus_we)) & (builder_minsoc_interface4_bank_bus_adr[2:0] == 3'd5));
assign builder_minsoc_csrbank4_txfull_w = main_uart_txfull_status;
assign main_uart_txfull_we = builder_minsoc_csrbank4_txfull_we;
assign builder_minsoc_csrbank4_rxempty_w = main_uart_rxempty_status;
assign main_uart_rxempty_we = builder_minsoc_csrbank4_rxempty_we;
assign builder_minsoc_csrbank4_ev_enable0_w = main_uart_eventmanager_storage[1:0];
assign builder_minsoc_csrbank5_sel = (builder_minsoc_interface5_bank_bus_adr[13:9] == 2'd2);
assign builder_minsoc_csrbank5_tuning_word3_r = builder_minsoc_interface5_bank_bus_dat_w[7:0];
assign builder_minsoc_csrbank5_tuning_word3_re = ((builder_minsoc_csrbank5_sel & builder_minsoc_interface5_bank_bus_we) & (builder_minsoc_interface5_bank_bus_adr[1:0] == 1'd0));
assign builder_minsoc_csrbank5_tuning_word3_we = ((builder_minsoc_csrbank5_sel & (~builder_minsoc_interface5_bank_bus_we)) & (builder_minsoc_interface5_bank_bus_adr[1:0] == 1'd0));
assign builder_minsoc_csrbank5_tuning_word2_r = builder_minsoc_interface5_bank_bus_dat_w[7:0];
assign builder_minsoc_csrbank5_tuning_word2_re = ((builder_minsoc_csrbank5_sel & builder_minsoc_interface5_bank_bus_we) & (builder_minsoc_interface5_bank_bus_adr[1:0] == 1'd1));
assign builder_minsoc_csrbank5_tuning_word2_we = ((builder_minsoc_csrbank5_sel & (~builder_minsoc_interface5_bank_bus_we)) & (builder_minsoc_interface5_bank_bus_adr[1:0] == 1'd1));
assign builder_minsoc_csrbank5_tuning_word1_r = builder_minsoc_interface5_bank_bus_dat_w[7:0];
assign builder_minsoc_csrbank5_tuning_word1_re = ((builder_minsoc_csrbank5_sel & builder_minsoc_interface5_bank_bus_we) & (builder_minsoc_interface5_bank_bus_adr[1:0] == 2'd2));
assign builder_minsoc_csrbank5_tuning_word1_we = ((builder_minsoc_csrbank5_sel & (~builder_minsoc_interface5_bank_bus_we)) & (builder_minsoc_interface5_bank_bus_adr[1:0] == 2'd2));
assign builder_minsoc_csrbank5_tuning_word0_r = builder_minsoc_interface5_bank_bus_dat_w[7:0];
assign builder_minsoc_csrbank5_tuning_word0_re = ((builder_minsoc_csrbank5_sel & builder_minsoc_interface5_bank_bus_we) & (builder_minsoc_interface5_bank_bus_adr[1:0] == 2'd3));
assign builder_minsoc_csrbank5_tuning_word0_we = ((builder_minsoc_csrbank5_sel & (~builder_minsoc_interface5_bank_bus_we)) & (builder_minsoc_interface5_bank_bus_adr[1:0] == 2'd3));
assign builder_minsoc_csrbank5_tuning_word3_w = main_uart_phy_storage[31:24];
assign builder_minsoc_csrbank5_tuning_word2_w = main_uart_phy_storage[23:16];
assign builder_minsoc_csrbank5_tuning_word1_w = main_uart_phy_storage[15:8];
assign builder_minsoc_csrbank5_tuning_word0_w = main_uart_phy_storage[7:0];
assign builder_minsoc_adr = main_interface_adr;
assign builder_minsoc_we = main_interface_we;
assign builder_minsoc_dat_w = main_interface_dat_w;
assign main_interface_dat_r = builder_minsoc_dat_r;
assign builder_minsoc_interface0_bank_bus_adr = builder_minsoc_adr;
assign builder_minsoc_interface1_bank_bus_adr = builder_minsoc_adr;
assign builder_minsoc_interface2_bank_bus_adr = builder_minsoc_adr;
assign builder_minsoc_interface3_bank_bus_adr = builder_minsoc_adr;
assign builder_minsoc_interface4_bank_bus_adr = builder_minsoc_adr;
assign builder_minsoc_interface5_bank_bus_adr = builder_minsoc_adr;
assign builder_minsoc_interface0_bank_bus_we = builder_minsoc_we;
assign builder_minsoc_interface1_bank_bus_we = builder_minsoc_we;
assign builder_minsoc_interface2_bank_bus_we = builder_minsoc_we;
assign builder_minsoc_interface3_bank_bus_we = builder_minsoc_we;
assign builder_minsoc_interface4_bank_bus_we = builder_minsoc_we;
assign builder_minsoc_interface5_bank_bus_we = builder_minsoc_we;
assign builder_minsoc_interface0_bank_bus_dat_w = builder_minsoc_dat_w;
assign builder_minsoc_interface1_bank_bus_dat_w = builder_minsoc_dat_w;
assign builder_minsoc_interface2_bank_bus_dat_w = builder_minsoc_dat_w;
assign builder_minsoc_interface3_bank_bus_dat_w = builder_minsoc_dat_w;
assign builder_minsoc_interface4_bank_bus_dat_w = builder_minsoc_dat_w;
assign builder_minsoc_interface5_bank_bus_dat_w = builder_minsoc_dat_w;
assign builder_minsoc_dat_r = (((((builder_minsoc_interface0_bank_bus_dat_r | builder_minsoc_interface1_bank_bus_dat_r) | builder_minsoc_interface2_bank_bus_dat_r) | builder_minsoc_interface3_bank_bus_dat_r) | builder_minsoc_interface4_bank_bus_dat_r) | builder_minsoc_interface5_bank_bus_dat_r);
always @(*) begin
builder_rhs_array_muxed0 <= 1'd0;
case (main_sdram_choose_cmd_grant)
1'd0: begin
builder_rhs_array_muxed0 <= main_sdram_choose_cmd_valids[0];
end
1'd1: begin
builder_rhs_array_muxed0 <= main_sdram_choose_cmd_valids[1];
end
2'd2: begin
builder_rhs_array_muxed0 <= main_sdram_choose_cmd_valids[2];
end
2'd3: begin
builder_rhs_array_muxed0 <= main_sdram_choose_cmd_valids[3];
end
3'd4: begin
builder_rhs_array_muxed0 <= main_sdram_choose_cmd_valids[4];
end
3'd5: begin
builder_rhs_array_muxed0 <= main_sdram_choose_cmd_valids[5];
end
3'd6: begin
builder_rhs_array_muxed0 <= main_sdram_choose_cmd_valids[6];
end
default: begin
builder_rhs_array_muxed0 <= main_sdram_choose_cmd_valids[7];
end
endcase
end
always @(*) begin
builder_rhs_array_muxed1 <= 14'd0;
case (main_sdram_choose_cmd_grant)
1'd0: begin
builder_rhs_array_muxed1 <= main_sdram_bankmachine0_cmd_payload_a;
end
1'd1: begin
builder_rhs_array_muxed1 <= main_sdram_bankmachine1_cmd_payload_a;
end
2'd2: begin
builder_rhs_array_muxed1 <= main_sdram_bankmachine2_cmd_payload_a;
end
2'd3: begin
builder_rhs_array_muxed1 <= main_sdram_bankmachine3_cmd_payload_a;
end
3'd4: begin
builder_rhs_array_muxed1 <= main_sdram_bankmachine4_cmd_payload_a;
end
3'd5: begin
builder_rhs_array_muxed1 <= main_sdram_bankmachine5_cmd_payload_a;
end
3'd6: begin
builder_rhs_array_muxed1 <= main_sdram_bankmachine6_cmd_payload_a;
end
default: begin
builder_rhs_array_muxed1 <= main_sdram_bankmachine7_cmd_payload_a;
end
endcase
end
always @(*) begin
builder_rhs_array_muxed2 <= 3'd0;
case (main_sdram_choose_cmd_grant)
1'd0: begin
builder_rhs_array_muxed2 <= main_sdram_bankmachine0_cmd_payload_ba;
end
1'd1: begin
builder_rhs_array_muxed2 <= main_sdram_bankmachine1_cmd_payload_ba;
end
2'd2: begin
builder_rhs_array_muxed2 <= main_sdram_bankmachine2_cmd_payload_ba;
end
2'd3: begin
builder_rhs_array_muxed2 <= main_sdram_bankmachine3_cmd_payload_ba;
end
3'd4: begin
builder_rhs_array_muxed2 <= main_sdram_bankmachine4_cmd_payload_ba;
end
3'd5: begin
builder_rhs_array_muxed2 <= main_sdram_bankmachine5_cmd_payload_ba;
end
3'd6: begin
builder_rhs_array_muxed2 <= main_sdram_bankmachine6_cmd_payload_ba;
end
default: begin
builder_rhs_array_muxed2 <= main_sdram_bankmachine7_cmd_payload_ba;
end
endcase
end
always @(*) begin
builder_rhs_array_muxed3 <= 1'd0;
case (main_sdram_choose_cmd_grant)
1'd0: begin
builder_rhs_array_muxed3 <= main_sdram_bankmachine0_cmd_payload_is_read;
end
1'd1: begin
builder_rhs_array_muxed3 <= main_sdram_bankmachine1_cmd_payload_is_read;
end
2'd2: begin
builder_rhs_array_muxed3 <= main_sdram_bankmachine2_cmd_payload_is_read;
end
2'd3: begin
builder_rhs_array_muxed3 <= main_sdram_bankmachine3_cmd_payload_is_read;
end
3'd4: begin
builder_rhs_array_muxed3 <= main_sdram_bankmachine4_cmd_payload_is_read;
end
3'd5: begin
builder_rhs_array_muxed3 <= main_sdram_bankmachine5_cmd_payload_is_read;
end
3'd6: begin
builder_rhs_array_muxed3 <= main_sdram_bankmachine6_cmd_payload_is_read;
end
default: begin
builder_rhs_array_muxed3 <= main_sdram_bankmachine7_cmd_payload_is_read;
end
endcase
end
always @(*) begin
builder_rhs_array_muxed4 <= 1'd0;
case (main_sdram_choose_cmd_grant)
1'd0: begin
builder_rhs_array_muxed4 <= main_sdram_bankmachine0_cmd_payload_is_write;
end
1'd1: begin
builder_rhs_array_muxed4 <= main_sdram_bankmachine1_cmd_payload_is_write;
end
2'd2: begin
builder_rhs_array_muxed4 <= main_sdram_bankmachine2_cmd_payload_is_write;
end
2'd3: begin
builder_rhs_array_muxed4 <= main_sdram_bankmachine3_cmd_payload_is_write;
end
3'd4: begin
builder_rhs_array_muxed4 <= main_sdram_bankmachine4_cmd_payload_is_write;
end
3'd5: begin
builder_rhs_array_muxed4 <= main_sdram_bankmachine5_cmd_payload_is_write;
end
3'd6: begin
builder_rhs_array_muxed4 <= main_sdram_bankmachine6_cmd_payload_is_write;
end
default: begin
builder_rhs_array_muxed4 <= main_sdram_bankmachine7_cmd_payload_is_write;
end
endcase
end
always @(*) begin
builder_rhs_array_muxed5 <= 1'd0;
case (main_sdram_choose_cmd_grant)
1'd0: begin
builder_rhs_array_muxed5 <= main_sdram_bankmachine0_cmd_payload_is_cmd;
end
1'd1: begin
builder_rhs_array_muxed5 <= main_sdram_bankmachine1_cmd_payload_is_cmd;
end
2'd2: begin
builder_rhs_array_muxed5 <= main_sdram_bankmachine2_cmd_payload_is_cmd;
end
2'd3: begin
builder_rhs_array_muxed5 <= main_sdram_bankmachine3_cmd_payload_is_cmd;
end
3'd4: begin
builder_rhs_array_muxed5 <= main_sdram_bankmachine4_cmd_payload_is_cmd;
end
3'd5: begin
builder_rhs_array_muxed5 <= main_sdram_bankmachine5_cmd_payload_is_cmd;
end
3'd6: begin
builder_rhs_array_muxed5 <= main_sdram_bankmachine6_cmd_payload_is_cmd;
end
default: begin
builder_rhs_array_muxed5 <= main_sdram_bankmachine7_cmd_payload_is_cmd;
end
endcase
end
always @(*) begin
builder_t_array_muxed0 <= 1'd0;
case (main_sdram_choose_cmd_grant)
1'd0: begin
builder_t_array_muxed0 <= main_sdram_bankmachine0_cmd_payload_cas;
end
1'd1: begin
builder_t_array_muxed0 <= main_sdram_bankmachine1_cmd_payload_cas;
end
2'd2: begin
builder_t_array_muxed0 <= main_sdram_bankmachine2_cmd_payload_cas;
end
2'd3: begin
builder_t_array_muxed0 <= main_sdram_bankmachine3_cmd_payload_cas;
end
3'd4: begin
builder_t_array_muxed0 <= main_sdram_bankmachine4_cmd_payload_cas;
end
3'd5: begin
builder_t_array_muxed0 <= main_sdram_bankmachine5_cmd_payload_cas;
end
3'd6: begin
builder_t_array_muxed0 <= main_sdram_bankmachine6_cmd_payload_cas;
end
default: begin
builder_t_array_muxed0 <= main_sdram_bankmachine7_cmd_payload_cas;
end
endcase
end
always @(*) begin
builder_t_array_muxed1 <= 1'd0;
case (main_sdram_choose_cmd_grant)
1'd0: begin
builder_t_array_muxed1 <= main_sdram_bankmachine0_cmd_payload_ras;
end
1'd1: begin
builder_t_array_muxed1 <= main_sdram_bankmachine1_cmd_payload_ras;
end
2'd2: begin
builder_t_array_muxed1 <= main_sdram_bankmachine2_cmd_payload_ras;
end
2'd3: begin
builder_t_array_muxed1 <= main_sdram_bankmachine3_cmd_payload_ras;
end
3'd4: begin
builder_t_array_muxed1 <= main_sdram_bankmachine4_cmd_payload_ras;
end
3'd5: begin
builder_t_array_muxed1 <= main_sdram_bankmachine5_cmd_payload_ras;
end
3'd6: begin
builder_t_array_muxed1 <= main_sdram_bankmachine6_cmd_payload_ras;
end
default: begin
builder_t_array_muxed1 <= main_sdram_bankmachine7_cmd_payload_ras;
end
endcase
end
always @(*) begin
builder_t_array_muxed2 <= 1'd0;
case (main_sdram_choose_cmd_grant)
1'd0: begin
builder_t_array_muxed2 <= main_sdram_bankmachine0_cmd_payload_we;
end
1'd1: begin
builder_t_array_muxed2 <= main_sdram_bankmachine1_cmd_payload_we;
end
2'd2: begin
builder_t_array_muxed2 <= main_sdram_bankmachine2_cmd_payload_we;
end
2'd3: begin
builder_t_array_muxed2 <= main_sdram_bankmachine3_cmd_payload_we;
end
3'd4: begin
builder_t_array_muxed2 <= main_sdram_bankmachine4_cmd_payload_we;
end
3'd5: begin
builder_t_array_muxed2 <= main_sdram_bankmachine5_cmd_payload_we;
end
3'd6: begin
builder_t_array_muxed2 <= main_sdram_bankmachine6_cmd_payload_we;
end
default: begin
builder_t_array_muxed2 <= main_sdram_bankmachine7_cmd_payload_we;
end
endcase
end
always @(*) begin
builder_rhs_array_muxed6 <= 1'd0;
case (main_sdram_choose_req_grant)
1'd0: begin
builder_rhs_array_muxed6 <= main_sdram_choose_req_valids[0];
end
1'd1: begin
builder_rhs_array_muxed6 <= main_sdram_choose_req_valids[1];
end
2'd2: begin
builder_rhs_array_muxed6 <= main_sdram_choose_req_valids[2];
end
2'd3: begin
builder_rhs_array_muxed6 <= main_sdram_choose_req_valids[3];
end
3'd4: begin
builder_rhs_array_muxed6 <= main_sdram_choose_req_valids[4];
end
3'd5: begin
builder_rhs_array_muxed6 <= main_sdram_choose_req_valids[5];
end
3'd6: begin
builder_rhs_array_muxed6 <= main_sdram_choose_req_valids[6];
end
default: begin
builder_rhs_array_muxed6 <= main_sdram_choose_req_valids[7];
end
endcase
end
always @(*) begin
builder_rhs_array_muxed7 <= 14'd0;
case (main_sdram_choose_req_grant)
1'd0: begin
builder_rhs_array_muxed7 <= main_sdram_bankmachine0_cmd_payload_a;
end
1'd1: begin
builder_rhs_array_muxed7 <= main_sdram_bankmachine1_cmd_payload_a;
end
2'd2: begin
builder_rhs_array_muxed7 <= main_sdram_bankmachine2_cmd_payload_a;
end
2'd3: begin
builder_rhs_array_muxed7 <= main_sdram_bankmachine3_cmd_payload_a;
end
3'd4: begin
builder_rhs_array_muxed7 <= main_sdram_bankmachine4_cmd_payload_a;
end
3'd5: begin
builder_rhs_array_muxed7 <= main_sdram_bankmachine5_cmd_payload_a;
end
3'd6: begin
builder_rhs_array_muxed7 <= main_sdram_bankmachine6_cmd_payload_a;
end
default: begin
builder_rhs_array_muxed7 <= main_sdram_bankmachine7_cmd_payload_a;
end
endcase
end
always @(*) begin
builder_rhs_array_muxed8 <= 3'd0;
case (main_sdram_choose_req_grant)
1'd0: begin
builder_rhs_array_muxed8 <= main_sdram_bankmachine0_cmd_payload_ba;
end
1'd1: begin
builder_rhs_array_muxed8 <= main_sdram_bankmachine1_cmd_payload_ba;
end
2'd2: begin
builder_rhs_array_muxed8 <= main_sdram_bankmachine2_cmd_payload_ba;
end
2'd3: begin
builder_rhs_array_muxed8 <= main_sdram_bankmachine3_cmd_payload_ba;
end
3'd4: begin
builder_rhs_array_muxed8 <= main_sdram_bankmachine4_cmd_payload_ba;
end
3'd5: begin
builder_rhs_array_muxed8 <= main_sdram_bankmachine5_cmd_payload_ba;
end
3'd6: begin
builder_rhs_array_muxed8 <= main_sdram_bankmachine6_cmd_payload_ba;
end
default: begin
builder_rhs_array_muxed8 <= main_sdram_bankmachine7_cmd_payload_ba;
end
endcase
end
always @(*) begin
builder_rhs_array_muxed9 <= 1'd0;
case (main_sdram_choose_req_grant)
1'd0: begin
builder_rhs_array_muxed9 <= main_sdram_bankmachine0_cmd_payload_is_read;
end
1'd1: begin
builder_rhs_array_muxed9 <= main_sdram_bankmachine1_cmd_payload_is_read;
end
2'd2: begin
builder_rhs_array_muxed9 <= main_sdram_bankmachine2_cmd_payload_is_read;
end
2'd3: begin
builder_rhs_array_muxed9 <= main_sdram_bankmachine3_cmd_payload_is_read;
end
3'd4: begin
builder_rhs_array_muxed9 <= main_sdram_bankmachine4_cmd_payload_is_read;
end
3'd5: begin
builder_rhs_array_muxed9 <= main_sdram_bankmachine5_cmd_payload_is_read;
end
3'd6: begin
builder_rhs_array_muxed9 <= main_sdram_bankmachine6_cmd_payload_is_read;
end
default: begin
builder_rhs_array_muxed9 <= main_sdram_bankmachine7_cmd_payload_is_read;
end
endcase
end
always @(*) begin
builder_rhs_array_muxed10 <= 1'd0;
case (main_sdram_choose_req_grant)
1'd0: begin
builder_rhs_array_muxed10 <= main_sdram_bankmachine0_cmd_payload_is_write;
end
1'd1: begin
builder_rhs_array_muxed10 <= main_sdram_bankmachine1_cmd_payload_is_write;
end
2'd2: begin
builder_rhs_array_muxed10 <= main_sdram_bankmachine2_cmd_payload_is_write;
end
2'd3: begin
builder_rhs_array_muxed10 <= main_sdram_bankmachine3_cmd_payload_is_write;
end
3'd4: begin
builder_rhs_array_muxed10 <= main_sdram_bankmachine4_cmd_payload_is_write;
end
3'd5: begin
builder_rhs_array_muxed10 <= main_sdram_bankmachine5_cmd_payload_is_write;
end
3'd6: begin
builder_rhs_array_muxed10 <= main_sdram_bankmachine6_cmd_payload_is_write;
end
default: begin
builder_rhs_array_muxed10 <= main_sdram_bankmachine7_cmd_payload_is_write;
end
endcase
end
always @(*) begin
builder_rhs_array_muxed11 <= 1'd0;
case (main_sdram_choose_req_grant)
1'd0: begin
builder_rhs_array_muxed11 <= main_sdram_bankmachine0_cmd_payload_is_cmd;
end
1'd1: begin
builder_rhs_array_muxed11 <= main_sdram_bankmachine1_cmd_payload_is_cmd;
end
2'd2: begin
builder_rhs_array_muxed11 <= main_sdram_bankmachine2_cmd_payload_is_cmd;
end
2'd3: begin
builder_rhs_array_muxed11 <= main_sdram_bankmachine3_cmd_payload_is_cmd;
end
3'd4: begin
builder_rhs_array_muxed11 <= main_sdram_bankmachine4_cmd_payload_is_cmd;
end
3'd5: begin
builder_rhs_array_muxed11 <= main_sdram_bankmachine5_cmd_payload_is_cmd;
end
3'd6: begin
builder_rhs_array_muxed11 <= main_sdram_bankmachine6_cmd_payload_is_cmd;
end
default: begin
builder_rhs_array_muxed11 <= main_sdram_bankmachine7_cmd_payload_is_cmd;
end
endcase
end
always @(*) begin
builder_t_array_muxed3 <= 1'd0;
case (main_sdram_choose_req_grant)
1'd0: begin
builder_t_array_muxed3 <= main_sdram_bankmachine0_cmd_payload_cas;
end
1'd1: begin
builder_t_array_muxed3 <= main_sdram_bankmachine1_cmd_payload_cas;
end
2'd2: begin
builder_t_array_muxed3 <= main_sdram_bankmachine2_cmd_payload_cas;
end
2'd3: begin
builder_t_array_muxed3 <= main_sdram_bankmachine3_cmd_payload_cas;
end
3'd4: begin
builder_t_array_muxed3 <= main_sdram_bankmachine4_cmd_payload_cas;
end
3'd5: begin
builder_t_array_muxed3 <= main_sdram_bankmachine5_cmd_payload_cas;
end
3'd6: begin
builder_t_array_muxed3 <= main_sdram_bankmachine6_cmd_payload_cas;
end
default: begin
builder_t_array_muxed3 <= main_sdram_bankmachine7_cmd_payload_cas;
end
endcase
end
always @(*) begin
builder_t_array_muxed4 <= 1'd0;
case (main_sdram_choose_req_grant)
1'd0: begin
builder_t_array_muxed4 <= main_sdram_bankmachine0_cmd_payload_ras;
end
1'd1: begin
builder_t_array_muxed4 <= main_sdram_bankmachine1_cmd_payload_ras;
end
2'd2: begin
builder_t_array_muxed4 <= main_sdram_bankmachine2_cmd_payload_ras;
end
2'd3: begin
builder_t_array_muxed4 <= main_sdram_bankmachine3_cmd_payload_ras;
end
3'd4: begin
builder_t_array_muxed4 <= main_sdram_bankmachine4_cmd_payload_ras;
end
3'd5: begin
builder_t_array_muxed4 <= main_sdram_bankmachine5_cmd_payload_ras;
end
3'd6: begin
builder_t_array_muxed4 <= main_sdram_bankmachine6_cmd_payload_ras;
end
default: begin
builder_t_array_muxed4 <= main_sdram_bankmachine7_cmd_payload_ras;
end
endcase
end
always @(*) begin
builder_t_array_muxed5 <= 1'd0;
case (main_sdram_choose_req_grant)
1'd0: begin
builder_t_array_muxed5 <= main_sdram_bankmachine0_cmd_payload_we;
end
1'd1: begin
builder_t_array_muxed5 <= main_sdram_bankmachine1_cmd_payload_we;
end
2'd2: begin
builder_t_array_muxed5 <= main_sdram_bankmachine2_cmd_payload_we;
end
2'd3: begin
builder_t_array_muxed5 <= main_sdram_bankmachine3_cmd_payload_we;
end
3'd4: begin
builder_t_array_muxed5 <= main_sdram_bankmachine4_cmd_payload_we;
end
3'd5: begin
builder_t_array_muxed5 <= main_sdram_bankmachine5_cmd_payload_we;
end
3'd6: begin
builder_t_array_muxed5 <= main_sdram_bankmachine6_cmd_payload_we;
end
default: begin
builder_t_array_muxed5 <= main_sdram_bankmachine7_cmd_payload_we;
end
endcase
end
always @(*) begin
builder_rhs_array_muxed12 <= 21'd0;
case (builder_roundrobin0_grant)
default: begin
builder_rhs_array_muxed12 <= {main_port_cmd_payload_addr[23:10], main_port_cmd_payload_addr[6:0]};
end
endcase
end
always @(*) begin
builder_rhs_array_muxed13 <= 1'd0;
case (builder_roundrobin0_grant)
default: begin
builder_rhs_array_muxed13 <= main_port_cmd_payload_we;
end
endcase
end
always @(*) begin
builder_rhs_array_muxed14 <= 1'd0;
case (builder_roundrobin0_grant)
default: begin
builder_rhs_array_muxed14 <= (((main_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((builder_locked0 | (main_sdram_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_sdram_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_sdram_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_sdram_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_sdram_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_sdram_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_sdram_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_port_cmd_valid);
end
endcase
end
always @(*) begin
builder_rhs_array_muxed15 <= 21'd0;
case (builder_roundrobin1_grant)
default: begin
builder_rhs_array_muxed15 <= {main_port_cmd_payload_addr[23:10], main_port_cmd_payload_addr[6:0]};
end
endcase
end
always @(*) begin
builder_rhs_array_muxed16 <= 1'd0;
case (builder_roundrobin1_grant)
default: begin
builder_rhs_array_muxed16 <= main_port_cmd_payload_we;
end
endcase
end
always @(*) begin
builder_rhs_array_muxed17 <= 1'd0;
case (builder_roundrobin1_grant)
default: begin
builder_rhs_array_muxed17 <= (((main_port_cmd_payload_addr[9:7] == 1'd1) & (~(((((((builder_locked1 | (main_sdram_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_sdram_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_sdram_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_sdram_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_sdram_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_sdram_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_sdram_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_port_cmd_valid);
end
endcase
end
always @(*) begin
builder_rhs_array_muxed18 <= 21'd0;
case (builder_roundrobin2_grant)
default: begin
builder_rhs_array_muxed18 <= {main_port_cmd_payload_addr[23:10], main_port_cmd_payload_addr[6:0]};
end
endcase
end
always @(*) begin
builder_rhs_array_muxed19 <= 1'd0;
case (builder_roundrobin2_grant)
default: begin
builder_rhs_array_muxed19 <= main_port_cmd_payload_we;
end
endcase
end
always @(*) begin
builder_rhs_array_muxed20 <= 1'd0;
case (builder_roundrobin2_grant)
default: begin
builder_rhs_array_muxed20 <= (((main_port_cmd_payload_addr[9:7] == 2'd2) & (~(((((((builder_locked2 | (main_sdram_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_sdram_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_sdram_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_sdram_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_sdram_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_sdram_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_sdram_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_port_cmd_valid);
end
endcase
end
always @(*) begin
builder_rhs_array_muxed21 <= 21'd0;
case (builder_roundrobin3_grant)
default: begin
builder_rhs_array_muxed21 <= {main_port_cmd_payload_addr[23:10], main_port_cmd_payload_addr[6:0]};
end
endcase
end
always @(*) begin
builder_rhs_array_muxed22 <= 1'd0;
case (builder_roundrobin3_grant)
default: begin
builder_rhs_array_muxed22 <= main_port_cmd_payload_we;
end
endcase
end
always @(*) begin
builder_rhs_array_muxed23 <= 1'd0;
case (builder_roundrobin3_grant)
default: begin
builder_rhs_array_muxed23 <= (((main_port_cmd_payload_addr[9:7] == 2'd3) & (~(((((((builder_locked3 | (main_sdram_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_sdram_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_sdram_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_sdram_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_sdram_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_sdram_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_sdram_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_port_cmd_valid);
end
endcase
end
always @(*) begin
builder_rhs_array_muxed24 <= 21'd0;
case (builder_roundrobin4_grant)
default: begin
builder_rhs_array_muxed24 <= {main_port_cmd_payload_addr[23:10], main_port_cmd_payload_addr[6:0]};
end
endcase
end
always @(*) begin
builder_rhs_array_muxed25 <= 1'd0;
case (builder_roundrobin4_grant)
default: begin
builder_rhs_array_muxed25 <= main_port_cmd_payload_we;
end
endcase
end
always @(*) begin
builder_rhs_array_muxed26 <= 1'd0;
case (builder_roundrobin4_grant)
default: begin
builder_rhs_array_muxed26 <= (((main_port_cmd_payload_addr[9:7] == 3'd4) & (~(((((((builder_locked4 | (main_sdram_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_sdram_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_sdram_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_sdram_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_sdram_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_sdram_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_sdram_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_port_cmd_valid);
end
endcase
end
always @(*) begin
builder_rhs_array_muxed27 <= 21'd0;
case (builder_roundrobin5_grant)
default: begin
builder_rhs_array_muxed27 <= {main_port_cmd_payload_addr[23:10], main_port_cmd_payload_addr[6:0]};
end
endcase
end
always @(*) begin
builder_rhs_array_muxed28 <= 1'd0;
case (builder_roundrobin5_grant)
default: begin
builder_rhs_array_muxed28 <= main_port_cmd_payload_we;
end
endcase
end
always @(*) begin
builder_rhs_array_muxed29 <= 1'd0;
case (builder_roundrobin5_grant)
default: begin
builder_rhs_array_muxed29 <= (((main_port_cmd_payload_addr[9:7] == 3'd5) & (~(((((((builder_locked5 | (main_sdram_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_sdram_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_sdram_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_sdram_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_sdram_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_sdram_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_sdram_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_port_cmd_valid);
end
endcase
end
always @(*) begin
builder_rhs_array_muxed30 <= 21'd0;
case (builder_roundrobin6_grant)
default: begin
builder_rhs_array_muxed30 <= {main_port_cmd_payload_addr[23:10], main_port_cmd_payload_addr[6:0]};
end
endcase
end
always @(*) begin
builder_rhs_array_muxed31 <= 1'd0;
case (builder_roundrobin6_grant)
default: begin
builder_rhs_array_muxed31 <= main_port_cmd_payload_we;
end
endcase
end
always @(*) begin
builder_rhs_array_muxed32 <= 1'd0;
case (builder_roundrobin6_grant)
default: begin
builder_rhs_array_muxed32 <= (((main_port_cmd_payload_addr[9:7] == 3'd6) & (~(((((((builder_locked6 | (main_sdram_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_sdram_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_sdram_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_sdram_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_sdram_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_sdram_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_sdram_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_port_cmd_valid);
end
endcase
end
always @(*) begin
builder_rhs_array_muxed33 <= 21'd0;
case (builder_roundrobin7_grant)
default: begin
builder_rhs_array_muxed33 <= {main_port_cmd_payload_addr[23:10], main_port_cmd_payload_addr[6:0]};
end
endcase
end
always @(*) begin
builder_rhs_array_muxed34 <= 1'd0;
case (builder_roundrobin7_grant)
default: begin
builder_rhs_array_muxed34 <= main_port_cmd_payload_we;
end
endcase
end
always @(*) begin
builder_rhs_array_muxed35 <= 1'd0;
case (builder_roundrobin7_grant)
default: begin
builder_rhs_array_muxed35 <= (((main_port_cmd_payload_addr[9:7] == 3'd7) & (~(((((((builder_locked7 | (main_sdram_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_sdram_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_sdram_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_sdram_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_sdram_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_sdram_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_sdram_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))))) & main_port_cmd_valid);
end
endcase
end
always @(*) begin
builder_rhs_array_muxed36 <= 30'd0;
case (builder_wb_sdram_con_grant)
default: begin
builder_rhs_array_muxed36 <= main_interface1_wb_sdram_adr;
end
endcase
end
always @(*) begin
builder_rhs_array_muxed37 <= 32'd0;
case (builder_wb_sdram_con_grant)
default: begin
builder_rhs_array_muxed37 <= main_interface1_wb_sdram_dat_w;
end
endcase
end
always @(*) begin
builder_rhs_array_muxed38 <= 4'd0;
case (builder_wb_sdram_con_grant)
default: begin
builder_rhs_array_muxed38 <= main_interface1_wb_sdram_sel;
end
endcase
end
always @(*) begin
builder_rhs_array_muxed39 <= 1'd0;
case (builder_wb_sdram_con_grant)
default: begin
builder_rhs_array_muxed39 <= main_interface1_wb_sdram_cyc;
end
endcase
end
always @(*) begin
builder_rhs_array_muxed40 <= 1'd0;
case (builder_wb_sdram_con_grant)
default: begin
builder_rhs_array_muxed40 <= main_interface1_wb_sdram_stb;
end
endcase
end
always @(*) begin
builder_rhs_array_muxed41 <= 1'd0;
case (builder_wb_sdram_con_grant)
default: begin
builder_rhs_array_muxed41 <= main_interface1_wb_sdram_we;
end
endcase
end
always @(*) begin
builder_rhs_array_muxed42 <= 3'd0;
case (builder_wb_sdram_con_grant)
default: begin
builder_rhs_array_muxed42 <= main_interface1_wb_sdram_cti;
end
endcase
end
always @(*) begin
builder_rhs_array_muxed43 <= 2'd0;
case (builder_wb_sdram_con_grant)
default: begin
builder_rhs_array_muxed43 <= main_interface1_wb_sdram_bte;
end
endcase
end
always @(*) begin
builder_rhs_array_muxed44 <= 30'd0;
case (builder_minsoc_grant)
1'd0: begin
builder_rhs_array_muxed44 <= main_interface0_soc_bus_adr;
end
default: begin
builder_rhs_array_muxed44 <= main_interface1_soc_bus_adr;
end
endcase
end
always @(*) begin
builder_rhs_array_muxed45 <= 32'd0;
case (builder_minsoc_grant)
1'd0: begin
builder_rhs_array_muxed45 <= main_interface0_soc_bus_dat_w;
end
default: begin
builder_rhs_array_muxed45 <= main_interface1_soc_bus_dat_w;
end
endcase
end
always @(*) begin
builder_rhs_array_muxed46 <= 4'd0;
case (builder_minsoc_grant)
1'd0: begin
builder_rhs_array_muxed46 <= main_interface0_soc_bus_sel;
end
default: begin
builder_rhs_array_muxed46 <= main_interface1_soc_bus_sel;
end
endcase
end
always @(*) begin
builder_rhs_array_muxed47 <= 1'd0;
case (builder_minsoc_grant)
1'd0: begin
builder_rhs_array_muxed47 <= main_interface0_soc_bus_cyc;
end
default: begin
builder_rhs_array_muxed47 <= main_interface1_soc_bus_cyc;
end
endcase
end
always @(*) begin
builder_rhs_array_muxed48 <= 1'd0;
case (builder_minsoc_grant)
1'd0: begin
builder_rhs_array_muxed48 <= main_interface0_soc_bus_stb;
end
default: begin
builder_rhs_array_muxed48 <= main_interface1_soc_bus_stb;
end
endcase
end
always @(*) begin
builder_rhs_array_muxed49 <= 1'd0;
case (builder_minsoc_grant)
1'd0: begin
builder_rhs_array_muxed49 <= main_interface0_soc_bus_we;
end
default: begin
builder_rhs_array_muxed49 <= main_interface1_soc_bus_we;
end
endcase
end
always @(*) begin
builder_rhs_array_muxed50 <= 3'd0;
case (builder_minsoc_grant)
1'd0: begin
builder_rhs_array_muxed50 <= main_interface0_soc_bus_cti;
end
default: begin
builder_rhs_array_muxed50 <= main_interface1_soc_bus_cti;
end
endcase
end
always @(*) begin
builder_rhs_array_muxed51 <= 2'd0;
case (builder_minsoc_grant)
1'd0: begin
builder_rhs_array_muxed51 <= main_interface0_soc_bus_bte;
end
default: begin
builder_rhs_array_muxed51 <= main_interface1_soc_bus_bte;
end
endcase
end
always @(*) begin
builder_array_muxed0 <= 3'd0;
case (main_sdram_steerer_sel0)
1'd0: begin
builder_array_muxed0 <= main_sdram_nop_ba[2:0];
end
1'd1: begin
builder_array_muxed0 <= main_sdram_choose_cmd_cmd_payload_ba[2:0];
end
2'd2: begin
builder_array_muxed0 <= main_sdram_choose_req_cmd_payload_ba[2:0];
end
default: begin
builder_array_muxed0 <= main_sdram_cmd_payload_ba[2:0];
end
endcase
end
always @(*) begin
builder_array_muxed1 <= 14'd0;
case (main_sdram_steerer_sel0)
1'd0: begin
builder_array_muxed1 <= main_sdram_nop_a;
end
1'd1: begin
builder_array_muxed1 <= main_sdram_choose_cmd_cmd_payload_a;
end
2'd2: begin
builder_array_muxed1 <= main_sdram_choose_req_cmd_payload_a;
end
default: begin
builder_array_muxed1 <= main_sdram_cmd_payload_a;
end
endcase
end
always @(*) begin
builder_array_muxed2 <= 1'd0;
case (main_sdram_steerer_sel0)
1'd0: begin
builder_array_muxed2 <= 1'd0;
end
1'd1: begin
builder_array_muxed2 <= ((main_sdram_choose_cmd_cmd_valid & main_sdram_choose_cmd_cmd_ready) & main_sdram_choose_cmd_cmd_payload_cas);
end
2'd2: begin
builder_array_muxed2 <= ((main_sdram_choose_req_cmd_valid & main_sdram_choose_req_cmd_ready) & main_sdram_choose_req_cmd_payload_cas);
end
default: begin
builder_array_muxed2 <= ((main_sdram_cmd_valid & main_sdram_cmd_ready) & main_sdram_cmd_payload_cas);
end
endcase
end
always @(*) begin
builder_array_muxed3 <= 1'd0;
case (main_sdram_steerer_sel0)
1'd0: begin
builder_array_muxed3 <= 1'd0;
end
1'd1: begin
builder_array_muxed3 <= ((main_sdram_choose_cmd_cmd_valid & main_sdram_choose_cmd_cmd_ready) & main_sdram_choose_cmd_cmd_payload_ras);
end
2'd2: begin
builder_array_muxed3 <= ((main_sdram_choose_req_cmd_valid & main_sdram_choose_req_cmd_ready) & main_sdram_choose_req_cmd_payload_ras);
end
default: begin
builder_array_muxed3 <= ((main_sdram_cmd_valid & main_sdram_cmd_ready) & main_sdram_cmd_payload_ras);
end
endcase
end
always @(*) begin
builder_array_muxed4 <= 1'd0;
case (main_sdram_steerer_sel0)
1'd0: begin
builder_array_muxed4 <= 1'd0;
end
1'd1: begin
builder_array_muxed4 <= ((main_sdram_choose_cmd_cmd_valid & main_sdram_choose_cmd_cmd_ready) & main_sdram_choose_cmd_cmd_payload_we);
end
2'd2: begin
builder_array_muxed4 <= ((main_sdram_choose_req_cmd_valid & main_sdram_choose_req_cmd_ready) & main_sdram_choose_req_cmd_payload_we);
end
default: begin
builder_array_muxed4 <= ((main_sdram_cmd_valid & main_sdram_cmd_ready) & main_sdram_cmd_payload_we);
end
endcase
end
always @(*) begin
builder_array_muxed5 <= 1'd0;
case (main_sdram_steerer_sel0)
1'd0: begin
builder_array_muxed5 <= 1'd0;
end
1'd1: begin
builder_array_muxed5 <= ((main_sdram_choose_cmd_cmd_valid & main_sdram_choose_cmd_cmd_ready) & main_sdram_choose_cmd_cmd_payload_is_read);
end
2'd2: begin
builder_array_muxed5 <= ((main_sdram_choose_req_cmd_valid & main_sdram_choose_req_cmd_ready) & main_sdram_choose_req_cmd_payload_is_read);
end
default: begin
builder_array_muxed5 <= ((main_sdram_cmd_valid & main_sdram_cmd_ready) & main_sdram_cmd_payload_is_read);
end
endcase
end
always @(*) begin
builder_array_muxed6 <= 1'd0;
case (main_sdram_steerer_sel0)
1'd0: begin
builder_array_muxed6 <= 1'd0;
end
1'd1: begin
builder_array_muxed6 <= ((main_sdram_choose_cmd_cmd_valid & main_sdram_choose_cmd_cmd_ready) & main_sdram_choose_cmd_cmd_payload_is_write);
end
2'd2: begin
builder_array_muxed6 <= ((main_sdram_choose_req_cmd_valid & main_sdram_choose_req_cmd_ready) & main_sdram_choose_req_cmd_payload_is_write);
end
default: begin
builder_array_muxed6 <= ((main_sdram_cmd_valid & main_sdram_cmd_ready) & main_sdram_cmd_payload_is_write);
end
endcase
end
always @(*) begin
builder_array_muxed7 <= 3'd0;
case (main_sdram_steerer_sel1)
1'd0: begin
builder_array_muxed7 <= main_sdram_nop_ba[2:0];
end
1'd1: begin
builder_array_muxed7 <= main_sdram_choose_cmd_cmd_payload_ba[2:0];
end
2'd2: begin
builder_array_muxed7 <= main_sdram_choose_req_cmd_payload_ba[2:0];
end
default: begin
builder_array_muxed7 <= main_sdram_cmd_payload_ba[2:0];
end
endcase
end
always @(*) begin
builder_array_muxed8 <= 14'd0;
case (main_sdram_steerer_sel1)
1'd0: begin
builder_array_muxed8 <= main_sdram_nop_a;
end
1'd1: begin
builder_array_muxed8 <= main_sdram_choose_cmd_cmd_payload_a;
end
2'd2: begin
builder_array_muxed8 <= main_sdram_choose_req_cmd_payload_a;
end
default: begin
builder_array_muxed8 <= main_sdram_cmd_payload_a;
end
endcase
end
always @(*) begin
builder_array_muxed9 <= 1'd0;
case (main_sdram_steerer_sel1)
1'd0: begin
builder_array_muxed9 <= 1'd0;
end
1'd1: begin
builder_array_muxed9 <= ((main_sdram_choose_cmd_cmd_valid & main_sdram_choose_cmd_cmd_ready) & main_sdram_choose_cmd_cmd_payload_cas);
end
2'd2: begin
builder_array_muxed9 <= ((main_sdram_choose_req_cmd_valid & main_sdram_choose_req_cmd_ready) & main_sdram_choose_req_cmd_payload_cas);
end
default: begin
builder_array_muxed9 <= ((main_sdram_cmd_valid & main_sdram_cmd_ready) & main_sdram_cmd_payload_cas);
end
endcase
end
always @(*) begin
builder_array_muxed10 <= 1'd0;
case (main_sdram_steerer_sel1)
1'd0: begin
builder_array_muxed10 <= 1'd0;
end
1'd1: begin
builder_array_muxed10 <= ((main_sdram_choose_cmd_cmd_valid & main_sdram_choose_cmd_cmd_ready) & main_sdram_choose_cmd_cmd_payload_ras);
end
2'd2: begin
builder_array_muxed10 <= ((main_sdram_choose_req_cmd_valid & main_sdram_choose_req_cmd_ready) & main_sdram_choose_req_cmd_payload_ras);
end
default: begin
builder_array_muxed10 <= ((main_sdram_cmd_valid & main_sdram_cmd_ready) & main_sdram_cmd_payload_ras);
end
endcase
end
always @(*) begin
builder_array_muxed11 <= 1'd0;
case (main_sdram_steerer_sel1)
1'd0: begin
builder_array_muxed11 <= 1'd0;
end
1'd1: begin
builder_array_muxed11 <= ((main_sdram_choose_cmd_cmd_valid & main_sdram_choose_cmd_cmd_ready) & main_sdram_choose_cmd_cmd_payload_we);
end
2'd2: begin
builder_array_muxed11 <= ((main_sdram_choose_req_cmd_valid & main_sdram_choose_req_cmd_ready) & main_sdram_choose_req_cmd_payload_we);
end
default: begin
builder_array_muxed11 <= ((main_sdram_cmd_valid & main_sdram_cmd_ready) & main_sdram_cmd_payload_we);
end
endcase
end
always @(*) begin
builder_array_muxed12 <= 1'd0;
case (main_sdram_steerer_sel1)
1'd0: begin
builder_array_muxed12 <= 1'd0;
end
1'd1: begin
builder_array_muxed12 <= ((main_sdram_choose_cmd_cmd_valid & main_sdram_choose_cmd_cmd_ready) & main_sdram_choose_cmd_cmd_payload_is_read);
end
2'd2: begin
builder_array_muxed12 <= ((main_sdram_choose_req_cmd_valid & main_sdram_choose_req_cmd_ready) & main_sdram_choose_req_cmd_payload_is_read);
end
default: begin
builder_array_muxed12 <= ((main_sdram_cmd_valid & main_sdram_cmd_ready) & main_sdram_cmd_payload_is_read);
end
endcase
end
always @(*) begin
builder_array_muxed13 <= 1'd0;
case (main_sdram_steerer_sel1)
1'd0: begin
builder_array_muxed13 <= 1'd0;
end
1'd1: begin
builder_array_muxed13 <= ((main_sdram_choose_cmd_cmd_valid & main_sdram_choose_cmd_cmd_ready) & main_sdram_choose_cmd_cmd_payload_is_write);
end
2'd2: begin
builder_array_muxed13 <= ((main_sdram_choose_req_cmd_valid & main_sdram_choose_req_cmd_ready) & main_sdram_choose_req_cmd_payload_is_write);
end
default: begin
builder_array_muxed13 <= ((main_sdram_cmd_valid & main_sdram_cmd_ready) & main_sdram_cmd_payload_is_write);
end
endcase
end
always @(*) begin
builder_array_muxed14 <= 3'd0;
case (main_sdram_steerer_sel2)
1'd0: begin
builder_array_muxed14 <= main_sdram_nop_ba[2:0];
end
1'd1: begin
builder_array_muxed14 <= main_sdram_choose_cmd_cmd_payload_ba[2:0];
end
2'd2: begin
builder_array_muxed14 <= main_sdram_choose_req_cmd_payload_ba[2:0];
end
default: begin
builder_array_muxed14 <= main_sdram_cmd_payload_ba[2:0];
end
endcase
end
always @(*) begin
builder_array_muxed15 <= 14'd0;
case (main_sdram_steerer_sel2)
1'd0: begin
builder_array_muxed15 <= main_sdram_nop_a;
end
1'd1: begin
builder_array_muxed15 <= main_sdram_choose_cmd_cmd_payload_a;
end
2'd2: begin
builder_array_muxed15 <= main_sdram_choose_req_cmd_payload_a;
end
default: begin
builder_array_muxed15 <= main_sdram_cmd_payload_a;
end
endcase
end
always @(*) begin
builder_array_muxed16 <= 1'd0;
case (main_sdram_steerer_sel2)
1'd0: begin
builder_array_muxed16 <= 1'd0;
end
1'd1: begin
builder_array_muxed16 <= ((main_sdram_choose_cmd_cmd_valid & main_sdram_choose_cmd_cmd_ready) & main_sdram_choose_cmd_cmd_payload_cas);
end
2'd2: begin
builder_array_muxed16 <= ((main_sdram_choose_req_cmd_valid & main_sdram_choose_req_cmd_ready) & main_sdram_choose_req_cmd_payload_cas);
end
default: begin
builder_array_muxed16 <= ((main_sdram_cmd_valid & main_sdram_cmd_ready) & main_sdram_cmd_payload_cas);
end
endcase
end
always @(*) begin
builder_array_muxed17 <= 1'd0;
case (main_sdram_steerer_sel2)
1'd0: begin
builder_array_muxed17 <= 1'd0;
end
1'd1: begin
builder_array_muxed17 <= ((main_sdram_choose_cmd_cmd_valid & main_sdram_choose_cmd_cmd_ready) & main_sdram_choose_cmd_cmd_payload_ras);
end
2'd2: begin
builder_array_muxed17 <= ((main_sdram_choose_req_cmd_valid & main_sdram_choose_req_cmd_ready) & main_sdram_choose_req_cmd_payload_ras);
end
default: begin
builder_array_muxed17 <= ((main_sdram_cmd_valid & main_sdram_cmd_ready) & main_sdram_cmd_payload_ras);
end
endcase
end
always @(*) begin
builder_array_muxed18 <= 1'd0;
case (main_sdram_steerer_sel2)
1'd0: begin
builder_array_muxed18 <= 1'd0;
end
1'd1: begin
builder_array_muxed18 <= ((main_sdram_choose_cmd_cmd_valid & main_sdram_choose_cmd_cmd_ready) & main_sdram_choose_cmd_cmd_payload_we);
end
2'd2: begin
builder_array_muxed18 <= ((main_sdram_choose_req_cmd_valid & main_sdram_choose_req_cmd_ready) & main_sdram_choose_req_cmd_payload_we);
end
default: begin
builder_array_muxed18 <= ((main_sdram_cmd_valid & main_sdram_cmd_ready) & main_sdram_cmd_payload_we);
end
endcase
end
always @(*) begin
builder_array_muxed19 <= 1'd0;
case (main_sdram_steerer_sel2)
1'd0: begin
builder_array_muxed19 <= 1'd0;
end
1'd1: begin
builder_array_muxed19 <= ((main_sdram_choose_cmd_cmd_valid & main_sdram_choose_cmd_cmd_ready) & main_sdram_choose_cmd_cmd_payload_is_read);
end
2'd2: begin
builder_array_muxed19 <= ((main_sdram_choose_req_cmd_valid & main_sdram_choose_req_cmd_ready) & main_sdram_choose_req_cmd_payload_is_read);
end
default: begin
builder_array_muxed19 <= ((main_sdram_cmd_valid & main_sdram_cmd_ready) & main_sdram_cmd_payload_is_read);
end
endcase
end
always @(*) begin
builder_array_muxed20 <= 1'd0;
case (main_sdram_steerer_sel2)
1'd0: begin
builder_array_muxed20 <= 1'd0;
end
1'd1: begin
builder_array_muxed20 <= ((main_sdram_choose_cmd_cmd_valid & main_sdram_choose_cmd_cmd_ready) & main_sdram_choose_cmd_cmd_payload_is_write);
end
2'd2: begin
builder_array_muxed20 <= ((main_sdram_choose_req_cmd_valid & main_sdram_choose_req_cmd_ready) & main_sdram_choose_req_cmd_payload_is_write);
end
default: begin
builder_array_muxed20 <= ((main_sdram_cmd_valid & main_sdram_cmd_ready) & main_sdram_cmd_payload_is_write);
end
endcase
end
always @(*) begin
builder_array_muxed21 <= 3'd0;
case (main_sdram_steerer_sel3)
1'd0: begin
builder_array_muxed21 <= main_sdram_nop_ba[2:0];
end
1'd1: begin
builder_array_muxed21 <= main_sdram_choose_cmd_cmd_payload_ba[2:0];
end
2'd2: begin
builder_array_muxed21 <= main_sdram_choose_req_cmd_payload_ba[2:0];
end
default: begin
builder_array_muxed21 <= main_sdram_cmd_payload_ba[2:0];
end
endcase
end
always @(*) begin
builder_array_muxed22 <= 14'd0;
case (main_sdram_steerer_sel3)
1'd0: begin
builder_array_muxed22 <= main_sdram_nop_a;
end
1'd1: begin
builder_array_muxed22 <= main_sdram_choose_cmd_cmd_payload_a;
end
2'd2: begin
builder_array_muxed22 <= main_sdram_choose_req_cmd_payload_a;
end
default: begin
builder_array_muxed22 <= main_sdram_cmd_payload_a;
end
endcase
end
always @(*) begin
builder_array_muxed23 <= 1'd0;
case (main_sdram_steerer_sel3)
1'd0: begin
builder_array_muxed23 <= 1'd0;
end
1'd1: begin
builder_array_muxed23 <= ((main_sdram_choose_cmd_cmd_valid & main_sdram_choose_cmd_cmd_ready) & main_sdram_choose_cmd_cmd_payload_cas);
end
2'd2: begin
builder_array_muxed23 <= ((main_sdram_choose_req_cmd_valid & main_sdram_choose_req_cmd_ready) & main_sdram_choose_req_cmd_payload_cas);
end
default: begin
builder_array_muxed23 <= ((main_sdram_cmd_valid & main_sdram_cmd_ready) & main_sdram_cmd_payload_cas);
end
endcase
end
always @(*) begin
builder_array_muxed24 <= 1'd0;
case (main_sdram_steerer_sel3)
1'd0: begin
builder_array_muxed24 <= 1'd0;
end
1'd1: begin
builder_array_muxed24 <= ((main_sdram_choose_cmd_cmd_valid & main_sdram_choose_cmd_cmd_ready) & main_sdram_choose_cmd_cmd_payload_ras);
end
2'd2: begin
builder_array_muxed24 <= ((main_sdram_choose_req_cmd_valid & main_sdram_choose_req_cmd_ready) & main_sdram_choose_req_cmd_payload_ras);
end
default: begin
builder_array_muxed24 <= ((main_sdram_cmd_valid & main_sdram_cmd_ready) & main_sdram_cmd_payload_ras);
end
endcase
end
always @(*) begin
builder_array_muxed25 <= 1'd0;
case (main_sdram_steerer_sel3)
1'd0: begin
builder_array_muxed25 <= 1'd0;
end
1'd1: begin
builder_array_muxed25 <= ((main_sdram_choose_cmd_cmd_valid & main_sdram_choose_cmd_cmd_ready) & main_sdram_choose_cmd_cmd_payload_we);
end
2'd2: begin
builder_array_muxed25 <= ((main_sdram_choose_req_cmd_valid & main_sdram_choose_req_cmd_ready) & main_sdram_choose_req_cmd_payload_we);
end
default: begin
builder_array_muxed25 <= ((main_sdram_cmd_valid & main_sdram_cmd_ready) & main_sdram_cmd_payload_we);
end
endcase
end
always @(*) begin
builder_array_muxed26 <= 1'd0;
case (main_sdram_steerer_sel3)
1'd0: begin
builder_array_muxed26 <= 1'd0;
end
1'd1: begin
builder_array_muxed26 <= ((main_sdram_choose_cmd_cmd_valid & main_sdram_choose_cmd_cmd_ready) & main_sdram_choose_cmd_cmd_payload_is_read);
end
2'd2: begin
builder_array_muxed26 <= ((main_sdram_choose_req_cmd_valid & main_sdram_choose_req_cmd_ready) & main_sdram_choose_req_cmd_payload_is_read);
end
default: begin
builder_array_muxed26 <= ((main_sdram_cmd_valid & main_sdram_cmd_ready) & main_sdram_cmd_payload_is_read);
end
endcase
end
always @(*) begin
builder_array_muxed27 <= 1'd0;
case (main_sdram_steerer_sel3)
1'd0: begin
builder_array_muxed27 <= 1'd0;
end
1'd1: begin
builder_array_muxed27 <= ((main_sdram_choose_cmd_cmd_valid & main_sdram_choose_cmd_cmd_ready) & main_sdram_choose_cmd_cmd_payload_is_write);
end
2'd2: begin
builder_array_muxed27 <= ((main_sdram_choose_req_cmd_valid & main_sdram_choose_req_cmd_ready) & main_sdram_choose_req_cmd_payload_is_write);
end
default: begin
builder_array_muxed27 <= ((main_sdram_cmd_valid & main_sdram_cmd_ready) & main_sdram_cmd_payload_is_write);
end
endcase
end
assign main_uart_phy_rx = builder_regs1;
assign builder_xilinxasyncresetsynchronizerimpl0 = ((~main_locked) | main_reset);
assign builder_xilinxasyncresetsynchronizerimpl1 = ((~main_locked) | main_reset);
assign builder_xilinxasyncresetsynchronizerimpl2 = ((~main_locked) | main_reset);
assign builder_xilinxasyncresetsynchronizerimpl3 = ((~main_locked) | main_reset);
always @(posedge clk200_clk) begin
if ((main_reset_counter != 1'd0)) begin
main_reset_counter <= (main_reset_counter - 1'd1);
end else begin
main_ic_reset <= 1'd0;
end
if (clk200_rst) begin
main_reset_counter <= 4'd15;
main_ic_reset <= 1'd1;
end
end
always @(posedge sys_clk) begin
if ((main_ctrl_bus_errors != 32'd4294967295)) begin
if (main_ctrl_bus_error) begin
main_ctrl_bus_errors <= (main_ctrl_bus_errors + 1'd1);
end
end
main_rom_bus_ack <= 1'd0;
if (((main_rom_bus_cyc & main_rom_bus_stb) & (~main_rom_bus_ack))) begin
main_rom_bus_ack <= 1'd1;
end
main_sram_bus_ack <= 1'd0;
if (((main_sram_bus_cyc & main_sram_bus_stb) & (~main_sram_bus_ack))) begin
main_sram_bus_ack <= 1'd1;
end
main_uart_phy_sink_ready <= 1'd0;
if (((main_uart_phy_sink_valid & (~main_uart_phy_tx_busy)) & (~main_uart_phy_sink_ready))) begin
main_uart_phy_tx_reg <= main_uart_phy_sink_payload_data;
main_uart_phy_tx_bitcount <= 1'd0;
main_uart_phy_tx_busy <= 1'd1;
serial_tx <= 1'd0;
end else begin
if ((main_uart_phy_uart_clk_txen & main_uart_phy_tx_busy)) begin
main_uart_phy_tx_bitcount <= (main_uart_phy_tx_bitcount + 1'd1);
if ((main_uart_phy_tx_bitcount == 4'd8)) begin
serial_tx <= 1'd1;
end else begin
if ((main_uart_phy_tx_bitcount == 4'd9)) begin
serial_tx <= 1'd1;
main_uart_phy_tx_busy <= 1'd0;
main_uart_phy_sink_ready <= 1'd1;
end else begin
serial_tx <= main_uart_phy_tx_reg[0];
main_uart_phy_tx_reg <= {1'd0, main_uart_phy_tx_reg[7:1]};
end
end
end
end
if (main_uart_phy_tx_busy) begin
{main_uart_phy_uart_clk_txen, main_uart_phy_phase_accumulator_tx} <= (main_uart_phy_phase_accumulator_tx + main_uart_phy_storage);
end else begin
{main_uart_phy_uart_clk_txen, main_uart_phy_phase_accumulator_tx} <= 1'd0;
end
main_uart_phy_source_valid <= 1'd0;
main_uart_phy_rx_r <= main_uart_phy_rx;
if ((~main_uart_phy_rx_busy)) begin
if (((~main_uart_phy_rx) & main_uart_phy_rx_r)) begin
main_uart_phy_rx_busy <= 1'd1;
main_uart_phy_rx_bitcount <= 1'd0;
end
end else begin
if (main_uart_phy_uart_clk_rxen) begin
main_uart_phy_rx_bitcount <= (main_uart_phy_rx_bitcount + 1'd1);
if ((main_uart_phy_rx_bitcount == 1'd0)) begin
if (main_uart_phy_rx) begin
main_uart_phy_rx_busy <= 1'd0;
end
end else begin
if ((main_uart_phy_rx_bitcount == 4'd9)) begin
main_uart_phy_rx_busy <= 1'd0;
if (main_uart_phy_rx) begin
main_uart_phy_source_payload_data <= main_uart_phy_rx_reg;
main_uart_phy_source_valid <= 1'd1;
end
end else begin
main_uart_phy_rx_reg <= {main_uart_phy_rx, main_uart_phy_rx_reg[7:1]};
end
end
end
end
if (main_uart_phy_rx_busy) begin
{main_uart_phy_uart_clk_rxen, main_uart_phy_phase_accumulator_rx} <= (main_uart_phy_phase_accumulator_rx + main_uart_phy_storage);
end else begin
{main_uart_phy_uart_clk_rxen, main_uart_phy_phase_accumulator_rx} <= 32'd2147483648;
end
if (main_uart_tx_clear) begin
main_uart_tx_pending <= 1'd0;
end
main_uart_tx_old_trigger <= main_uart_tx_trigger;
if (((~main_uart_tx_trigger) & main_uart_tx_old_trigger)) begin
main_uart_tx_pending <= 1'd1;
end
if (main_uart_rx_clear) begin
main_uart_rx_pending <= 1'd0;
end
main_uart_rx_old_trigger <= main_uart_rx_trigger;
if (((~main_uart_rx_trigger) & main_uart_rx_old_trigger)) begin
main_uart_rx_pending <= 1'd1;
end
if (main_uart_tx_fifo_syncfifo_re) begin
main_uart_tx_fifo_readable <= 1'd1;
end else begin
if (main_uart_tx_fifo_re) begin
main_uart_tx_fifo_readable <= 1'd0;
end
end
if (((main_uart_tx_fifo_syncfifo_we & main_uart_tx_fifo_syncfifo_writable) & (~main_uart_tx_fifo_replace))) begin
main_uart_tx_fifo_produce <= (main_uart_tx_fifo_produce + 1'd1);
end
if (main_uart_tx_fifo_do_read) begin
main_uart_tx_fifo_consume <= (main_uart_tx_fifo_consume + 1'd1);
end
if (((main_uart_tx_fifo_syncfifo_we & main_uart_tx_fifo_syncfifo_writable) & (~main_uart_tx_fifo_replace))) begin
if ((~main_uart_tx_fifo_do_read)) begin
main_uart_tx_fifo_level0 <= (main_uart_tx_fifo_level0 + 1'd1);
end
end else begin
if (main_uart_tx_fifo_do_read) begin
main_uart_tx_fifo_level0 <= (main_uart_tx_fifo_level0 - 1'd1);
end
end
if (main_uart_rx_fifo_syncfifo_re) begin
main_uart_rx_fifo_readable <= 1'd1;
end else begin
if (main_uart_rx_fifo_re) begin
main_uart_rx_fifo_readable <= 1'd0;
end
end
if (((main_uart_rx_fifo_syncfifo_we & main_uart_rx_fifo_syncfifo_writable) & (~main_uart_rx_fifo_replace))) begin
main_uart_rx_fifo_produce <= (main_uart_rx_fifo_produce + 1'd1);
end
if (main_uart_rx_fifo_do_read) begin
main_uart_rx_fifo_consume <= (main_uart_rx_fifo_consume + 1'd1);
end
if (((main_uart_rx_fifo_syncfifo_we & main_uart_rx_fifo_syncfifo_writable) & (~main_uart_rx_fifo_replace))) begin
if ((~main_uart_rx_fifo_do_read)) begin
main_uart_rx_fifo_level0 <= (main_uart_rx_fifo_level0 + 1'd1);
end
end else begin
if (main_uart_rx_fifo_do_read) begin
main_uart_rx_fifo_level0 <= (main_uart_rx_fifo_level0 - 1'd1);
end
end
if (main_uart_reset) begin
main_uart_tx_pending <= 1'd0;
main_uart_tx_old_trigger <= 1'd0;
main_uart_rx_pending <= 1'd0;
main_uart_rx_old_trigger <= 1'd0;
main_uart_tx_fifo_readable <= 1'd0;
main_uart_tx_fifo_level0 <= 5'd0;
main_uart_tx_fifo_produce <= 4'd0;
main_uart_tx_fifo_consume <= 4'd0;
main_uart_rx_fifo_readable <= 1'd0;
main_uart_rx_fifo_level0 <= 5'd0;
main_uart_rx_fifo_produce <= 4'd0;
main_uart_rx_fifo_consume <= 4'd0;
end
if (main_timer0_en_storage) begin
if ((main_timer0_value == 1'd0)) begin
main_timer0_value <= main_timer0_reload_storage;
end else begin
main_timer0_value <= (main_timer0_value - 1'd1);
end
end else begin
main_timer0_value <= main_timer0_load_storage;
end
if (main_timer0_update_value_re) begin
main_timer0_value_status <= main_timer0_value;
end
if (main_timer0_zero_clear) begin
main_timer0_zero_pending <= 1'd0;
end
main_timer0_zero_old_trigger <= main_timer0_zero_trigger;
if (((~main_timer0_zero_trigger) & main_timer0_zero_old_trigger)) begin
main_timer0_zero_pending <= 1'd1;
end
builder_wb2csr_state <= builder_wb2csr_next_state;
if (main_a7ddrphy_dly_sel_storage[0]) begin
if (main_a7ddrphy_rdly_dq_bitslip_rst_re) begin
main_a7ddrphy_bitslip0_value <= 1'd0;
end else begin
if (main_a7ddrphy_rdly_dq_bitslip_re) begin
main_a7ddrphy_bitslip0_value <= (main_a7ddrphy_bitslip0_value + 1'd1);
end
end
end
if (main_a7ddrphy_dly_sel_storage[0]) begin
if (main_a7ddrphy_rdly_dq_bitslip_rst_re) begin
main_a7ddrphy_bitslip1_value <= 1'd0;
end else begin
if (main_a7ddrphy_rdly_dq_bitslip_re) begin
main_a7ddrphy_bitslip1_value <= (main_a7ddrphy_bitslip1_value + 1'd1);
end
end
end
if (main_a7ddrphy_dly_sel_storage[0]) begin
if (main_a7ddrphy_rdly_dq_bitslip_rst_re) begin
main_a7ddrphy_bitslip2_value <= 1'd0;
end else begin
if (main_a7ddrphy_rdly_dq_bitslip_re) begin
main_a7ddrphy_bitslip2_value <= (main_a7ddrphy_bitslip2_value + 1'd1);
end
end
end
if (main_a7ddrphy_dly_sel_storage[0]) begin
if (main_a7ddrphy_rdly_dq_bitslip_rst_re) begin
main_a7ddrphy_bitslip3_value <= 1'd0;
end else begin
if (main_a7ddrphy_rdly_dq_bitslip_re) begin
main_a7ddrphy_bitslip3_value <= (main_a7ddrphy_bitslip3_value + 1'd1);
end
end
end
if (main_a7ddrphy_dly_sel_storage[0]) begin
if (main_a7ddrphy_rdly_dq_bitslip_rst_re) begin
main_a7ddrphy_bitslip4_value <= 1'd0;
end else begin
if (main_a7ddrphy_rdly_dq_bitslip_re) begin
main_a7ddrphy_bitslip4_value <= (main_a7ddrphy_bitslip4_value + 1'd1);
end
end
end
if (main_a7ddrphy_dly_sel_storage[0]) begin
if (main_a7ddrphy_rdly_dq_bitslip_rst_re) begin
main_a7ddrphy_bitslip5_value <= 1'd0;
end else begin
if (main_a7ddrphy_rdly_dq_bitslip_re) begin
main_a7ddrphy_bitslip5_value <= (main_a7ddrphy_bitslip5_value + 1'd1);
end
end
end
if (main_a7ddrphy_dly_sel_storage[0]) begin
if (main_a7ddrphy_rdly_dq_bitslip_rst_re) begin
main_a7ddrphy_bitslip6_value <= 1'd0;
end else begin
if (main_a7ddrphy_rdly_dq_bitslip_re) begin
main_a7ddrphy_bitslip6_value <= (main_a7ddrphy_bitslip6_value + 1'd1);
end
end
end
if (main_a7ddrphy_dly_sel_storage[0]) begin
if (main_a7ddrphy_rdly_dq_bitslip_rst_re) begin
main_a7ddrphy_bitslip7_value <= 1'd0;
end else begin
if (main_a7ddrphy_rdly_dq_bitslip_re) begin
main_a7ddrphy_bitslip7_value <= (main_a7ddrphy_bitslip7_value + 1'd1);
end
end
end
if (main_a7ddrphy_dly_sel_storage[1]) begin
if (main_a7ddrphy_rdly_dq_bitslip_rst_re) begin
main_a7ddrphy_bitslip8_value <= 1'd0;
end else begin
if (main_a7ddrphy_rdly_dq_bitslip_re) begin
main_a7ddrphy_bitslip8_value <= (main_a7ddrphy_bitslip8_value + 1'd1);
end
end
end
if (main_a7ddrphy_dly_sel_storage[1]) begin
if (main_a7ddrphy_rdly_dq_bitslip_rst_re) begin
main_a7ddrphy_bitslip9_value <= 1'd0;
end else begin
if (main_a7ddrphy_rdly_dq_bitslip_re) begin
main_a7ddrphy_bitslip9_value <= (main_a7ddrphy_bitslip9_value + 1'd1);
end
end
end
if (main_a7ddrphy_dly_sel_storage[1]) begin
if (main_a7ddrphy_rdly_dq_bitslip_rst_re) begin
main_a7ddrphy_bitslip10_value <= 1'd0;
end else begin
if (main_a7ddrphy_rdly_dq_bitslip_re) begin
main_a7ddrphy_bitslip10_value <= (main_a7ddrphy_bitslip10_value + 1'd1);
end
end
end
if (main_a7ddrphy_dly_sel_storage[1]) begin
if (main_a7ddrphy_rdly_dq_bitslip_rst_re) begin
main_a7ddrphy_bitslip11_value <= 1'd0;
end else begin
if (main_a7ddrphy_rdly_dq_bitslip_re) begin
main_a7ddrphy_bitslip11_value <= (main_a7ddrphy_bitslip11_value + 1'd1);
end
end
end
if (main_a7ddrphy_dly_sel_storage[1]) begin
if (main_a7ddrphy_rdly_dq_bitslip_rst_re) begin
main_a7ddrphy_bitslip12_value <= 1'd0;
end else begin
if (main_a7ddrphy_rdly_dq_bitslip_re) begin
main_a7ddrphy_bitslip12_value <= (main_a7ddrphy_bitslip12_value + 1'd1);
end
end
end
if (main_a7ddrphy_dly_sel_storage[1]) begin
if (main_a7ddrphy_rdly_dq_bitslip_rst_re) begin
main_a7ddrphy_bitslip13_value <= 1'd0;
end else begin
if (main_a7ddrphy_rdly_dq_bitslip_re) begin
main_a7ddrphy_bitslip13_value <= (main_a7ddrphy_bitslip13_value + 1'd1);
end
end
end
if (main_a7ddrphy_dly_sel_storage[1]) begin
if (main_a7ddrphy_rdly_dq_bitslip_rst_re) begin
main_a7ddrphy_bitslip14_value <= 1'd0;
end else begin
if (main_a7ddrphy_rdly_dq_bitslip_re) begin
main_a7ddrphy_bitslip14_value <= (main_a7ddrphy_bitslip14_value + 1'd1);
end
end
end
if (main_a7ddrphy_dly_sel_storage[1]) begin
if (main_a7ddrphy_rdly_dq_bitslip_rst_re) begin
main_a7ddrphy_bitslip15_value <= 1'd0;
end else begin
if (main_a7ddrphy_rdly_dq_bitslip_re) begin
main_a7ddrphy_bitslip15_value <= (main_a7ddrphy_bitslip15_value + 1'd1);
end
end
end
main_a7ddrphy_n_rddata_en0 <= main_a7ddrphy_dfi_p2_rddata_en;
main_a7ddrphy_n_rddata_en1 <= main_a7ddrphy_n_rddata_en0;
main_a7ddrphy_n_rddata_en2 <= main_a7ddrphy_n_rddata_en1;
main_a7ddrphy_n_rddata_en3 <= main_a7ddrphy_n_rddata_en2;
main_a7ddrphy_n_rddata_en4 <= main_a7ddrphy_n_rddata_en3;
main_a7ddrphy_n_rddata_en5 <= main_a7ddrphy_n_rddata_en4;
main_a7ddrphy_n_rddata_en6 <= main_a7ddrphy_n_rddata_en5;
main_a7ddrphy_n_rddata_en7 <= main_a7ddrphy_n_rddata_en6;
main_a7ddrphy_dfi_p0_rddata_valid <= main_a7ddrphy_n_rddata_en7;
main_a7ddrphy_dfi_p1_rddata_valid <= main_a7ddrphy_n_rddata_en7;
main_a7ddrphy_dfi_p2_rddata_valid <= main_a7ddrphy_n_rddata_en7;
main_a7ddrphy_dfi_p3_rddata_valid <= main_a7ddrphy_n_rddata_en7;
main_a7ddrphy_last_wrdata_en <= {main_a7ddrphy_last_wrdata_en[2:0], main_a7ddrphy_dfi_p3_wrdata_en};
main_a7ddrphy_oe_dqs <= main_a7ddrphy_oe;
main_a7ddrphy_oe_dq <= main_a7ddrphy_oe;
main_a7ddrphy_bitslip0_r <= {main_a7ddrphy_bitslip0_i, main_a7ddrphy_bitslip0_r[15:8]};
case (main_a7ddrphy_bitslip0_value)
1'd0: begin
main_a7ddrphy_bitslip0_o <= main_a7ddrphy_bitslip0_r[7:0];
end
1'd1: begin
main_a7ddrphy_bitslip0_o <= main_a7ddrphy_bitslip0_r[8:1];
end
2'd2: begin
main_a7ddrphy_bitslip0_o <= main_a7ddrphy_bitslip0_r[9:2];
end
2'd3: begin
main_a7ddrphy_bitslip0_o <= main_a7ddrphy_bitslip0_r[10:3];
end
3'd4: begin
main_a7ddrphy_bitslip0_o <= main_a7ddrphy_bitslip0_r[11:4];
end
3'd5: begin
main_a7ddrphy_bitslip0_o <= main_a7ddrphy_bitslip0_r[12:5];
end
3'd6: begin
main_a7ddrphy_bitslip0_o <= main_a7ddrphy_bitslip0_r[13:6];
end
3'd7: begin
main_a7ddrphy_bitslip0_o <= main_a7ddrphy_bitslip0_r[14:7];
end
endcase
main_a7ddrphy_bitslip1_r <= {main_a7ddrphy_bitslip1_i, main_a7ddrphy_bitslip1_r[15:8]};
case (main_a7ddrphy_bitslip1_value)
1'd0: begin
main_a7ddrphy_bitslip1_o <= main_a7ddrphy_bitslip1_r[7:0];
end
1'd1: begin
main_a7ddrphy_bitslip1_o <= main_a7ddrphy_bitslip1_r[8:1];
end
2'd2: begin
main_a7ddrphy_bitslip1_o <= main_a7ddrphy_bitslip1_r[9:2];
end
2'd3: begin
main_a7ddrphy_bitslip1_o <= main_a7ddrphy_bitslip1_r[10:3];
end
3'd4: begin
main_a7ddrphy_bitslip1_o <= main_a7ddrphy_bitslip1_r[11:4];
end
3'd5: begin
main_a7ddrphy_bitslip1_o <= main_a7ddrphy_bitslip1_r[12:5];
end
3'd6: begin
main_a7ddrphy_bitslip1_o <= main_a7ddrphy_bitslip1_r[13:6];
end
3'd7: begin
main_a7ddrphy_bitslip1_o <= main_a7ddrphy_bitslip1_r[14:7];
end
endcase
main_a7ddrphy_bitslip2_r <= {main_a7ddrphy_bitslip2_i, main_a7ddrphy_bitslip2_r[15:8]};
case (main_a7ddrphy_bitslip2_value)
1'd0: begin
main_a7ddrphy_bitslip2_o <= main_a7ddrphy_bitslip2_r[7:0];
end
1'd1: begin
main_a7ddrphy_bitslip2_o <= main_a7ddrphy_bitslip2_r[8:1];
end
2'd2: begin
main_a7ddrphy_bitslip2_o <= main_a7ddrphy_bitslip2_r[9:2];
end
2'd3: begin
main_a7ddrphy_bitslip2_o <= main_a7ddrphy_bitslip2_r[10:3];
end
3'd4: begin
main_a7ddrphy_bitslip2_o <= main_a7ddrphy_bitslip2_r[11:4];
end
3'd5: begin
main_a7ddrphy_bitslip2_o <= main_a7ddrphy_bitslip2_r[12:5];
end
3'd6: begin
main_a7ddrphy_bitslip2_o <= main_a7ddrphy_bitslip2_r[13:6];
end
3'd7: begin
main_a7ddrphy_bitslip2_o <= main_a7ddrphy_bitslip2_r[14:7];
end
endcase
main_a7ddrphy_bitslip3_r <= {main_a7ddrphy_bitslip3_i, main_a7ddrphy_bitslip3_r[15:8]};
case (main_a7ddrphy_bitslip3_value)
1'd0: begin
main_a7ddrphy_bitslip3_o <= main_a7ddrphy_bitslip3_r[7:0];
end
1'd1: begin
main_a7ddrphy_bitslip3_o <= main_a7ddrphy_bitslip3_r[8:1];
end
2'd2: begin
main_a7ddrphy_bitslip3_o <= main_a7ddrphy_bitslip3_r[9:2];
end
2'd3: begin
main_a7ddrphy_bitslip3_o <= main_a7ddrphy_bitslip3_r[10:3];
end
3'd4: begin
main_a7ddrphy_bitslip3_o <= main_a7ddrphy_bitslip3_r[11:4];
end
3'd5: begin
main_a7ddrphy_bitslip3_o <= main_a7ddrphy_bitslip3_r[12:5];
end
3'd6: begin
main_a7ddrphy_bitslip3_o <= main_a7ddrphy_bitslip3_r[13:6];
end
3'd7: begin
main_a7ddrphy_bitslip3_o <= main_a7ddrphy_bitslip3_r[14:7];
end
endcase
main_a7ddrphy_bitslip4_r <= {main_a7ddrphy_bitslip4_i, main_a7ddrphy_bitslip4_r[15:8]};
case (main_a7ddrphy_bitslip4_value)
1'd0: begin
main_a7ddrphy_bitslip4_o <= main_a7ddrphy_bitslip4_r[7:0];
end
1'd1: begin
main_a7ddrphy_bitslip4_o <= main_a7ddrphy_bitslip4_r[8:1];
end
2'd2: begin
main_a7ddrphy_bitslip4_o <= main_a7ddrphy_bitslip4_r[9:2];
end
2'd3: begin
main_a7ddrphy_bitslip4_o <= main_a7ddrphy_bitslip4_r[10:3];
end
3'd4: begin
main_a7ddrphy_bitslip4_o <= main_a7ddrphy_bitslip4_r[11:4];
end
3'd5: begin
main_a7ddrphy_bitslip4_o <= main_a7ddrphy_bitslip4_r[12:5];
end
3'd6: begin
main_a7ddrphy_bitslip4_o <= main_a7ddrphy_bitslip4_r[13:6];
end
3'd7: begin
main_a7ddrphy_bitslip4_o <= main_a7ddrphy_bitslip4_r[14:7];
end
endcase
main_a7ddrphy_bitslip5_r <= {main_a7ddrphy_bitslip5_i, main_a7ddrphy_bitslip5_r[15:8]};
case (main_a7ddrphy_bitslip5_value)
1'd0: begin
main_a7ddrphy_bitslip5_o <= main_a7ddrphy_bitslip5_r[7:0];
end
1'd1: begin
main_a7ddrphy_bitslip5_o <= main_a7ddrphy_bitslip5_r[8:1];
end
2'd2: begin
main_a7ddrphy_bitslip5_o <= main_a7ddrphy_bitslip5_r[9:2];
end
2'd3: begin
main_a7ddrphy_bitslip5_o <= main_a7ddrphy_bitslip5_r[10:3];
end
3'd4: begin
main_a7ddrphy_bitslip5_o <= main_a7ddrphy_bitslip5_r[11:4];
end
3'd5: begin
main_a7ddrphy_bitslip5_o <= main_a7ddrphy_bitslip5_r[12:5];
end
3'd6: begin
main_a7ddrphy_bitslip5_o <= main_a7ddrphy_bitslip5_r[13:6];
end
3'd7: begin
main_a7ddrphy_bitslip5_o <= main_a7ddrphy_bitslip5_r[14:7];
end
endcase
main_a7ddrphy_bitslip6_r <= {main_a7ddrphy_bitslip6_i, main_a7ddrphy_bitslip6_r[15:8]};
case (main_a7ddrphy_bitslip6_value)
1'd0: begin
main_a7ddrphy_bitslip6_o <= main_a7ddrphy_bitslip6_r[7:0];
end
1'd1: begin
main_a7ddrphy_bitslip6_o <= main_a7ddrphy_bitslip6_r[8:1];
end
2'd2: begin
main_a7ddrphy_bitslip6_o <= main_a7ddrphy_bitslip6_r[9:2];
end
2'd3: begin
main_a7ddrphy_bitslip6_o <= main_a7ddrphy_bitslip6_r[10:3];
end
3'd4: begin
main_a7ddrphy_bitslip6_o <= main_a7ddrphy_bitslip6_r[11:4];
end
3'd5: begin
main_a7ddrphy_bitslip6_o <= main_a7ddrphy_bitslip6_r[12:5];
end
3'd6: begin
main_a7ddrphy_bitslip6_o <= main_a7ddrphy_bitslip6_r[13:6];
end
3'd7: begin
main_a7ddrphy_bitslip6_o <= main_a7ddrphy_bitslip6_r[14:7];
end
endcase
main_a7ddrphy_bitslip7_r <= {main_a7ddrphy_bitslip7_i, main_a7ddrphy_bitslip7_r[15:8]};
case (main_a7ddrphy_bitslip7_value)
1'd0: begin
main_a7ddrphy_bitslip7_o <= main_a7ddrphy_bitslip7_r[7:0];
end
1'd1: begin
main_a7ddrphy_bitslip7_o <= main_a7ddrphy_bitslip7_r[8:1];
end
2'd2: begin
main_a7ddrphy_bitslip7_o <= main_a7ddrphy_bitslip7_r[9:2];
end
2'd3: begin
main_a7ddrphy_bitslip7_o <= main_a7ddrphy_bitslip7_r[10:3];
end
3'd4: begin
main_a7ddrphy_bitslip7_o <= main_a7ddrphy_bitslip7_r[11:4];
end
3'd5: begin
main_a7ddrphy_bitslip7_o <= main_a7ddrphy_bitslip7_r[12:5];
end
3'd6: begin
main_a7ddrphy_bitslip7_o <= main_a7ddrphy_bitslip7_r[13:6];
end
3'd7: begin
main_a7ddrphy_bitslip7_o <= main_a7ddrphy_bitslip7_r[14:7];
end
endcase
main_a7ddrphy_bitslip8_r <= {main_a7ddrphy_bitslip8_i, main_a7ddrphy_bitslip8_r[15:8]};
case (main_a7ddrphy_bitslip8_value)
1'd0: begin
main_a7ddrphy_bitslip8_o <= main_a7ddrphy_bitslip8_r[7:0];
end
1'd1: begin
main_a7ddrphy_bitslip8_o <= main_a7ddrphy_bitslip8_r[8:1];
end
2'd2: begin
main_a7ddrphy_bitslip8_o <= main_a7ddrphy_bitslip8_r[9:2];
end
2'd3: begin
main_a7ddrphy_bitslip8_o <= main_a7ddrphy_bitslip8_r[10:3];
end
3'd4: begin
main_a7ddrphy_bitslip8_o <= main_a7ddrphy_bitslip8_r[11:4];
end
3'd5: begin
main_a7ddrphy_bitslip8_o <= main_a7ddrphy_bitslip8_r[12:5];
end
3'd6: begin
main_a7ddrphy_bitslip8_o <= main_a7ddrphy_bitslip8_r[13:6];
end
3'd7: begin
main_a7ddrphy_bitslip8_o <= main_a7ddrphy_bitslip8_r[14:7];
end
endcase
main_a7ddrphy_bitslip9_r <= {main_a7ddrphy_bitslip9_i, main_a7ddrphy_bitslip9_r[15:8]};
case (main_a7ddrphy_bitslip9_value)
1'd0: begin
main_a7ddrphy_bitslip9_o <= main_a7ddrphy_bitslip9_r[7:0];
end
1'd1: begin
main_a7ddrphy_bitslip9_o <= main_a7ddrphy_bitslip9_r[8:1];
end
2'd2: begin
main_a7ddrphy_bitslip9_o <= main_a7ddrphy_bitslip9_r[9:2];
end
2'd3: begin
main_a7ddrphy_bitslip9_o <= main_a7ddrphy_bitslip9_r[10:3];
end
3'd4: begin
main_a7ddrphy_bitslip9_o <= main_a7ddrphy_bitslip9_r[11:4];
end
3'd5: begin
main_a7ddrphy_bitslip9_o <= main_a7ddrphy_bitslip9_r[12:5];
end
3'd6: begin
main_a7ddrphy_bitslip9_o <= main_a7ddrphy_bitslip9_r[13:6];
end
3'd7: begin
main_a7ddrphy_bitslip9_o <= main_a7ddrphy_bitslip9_r[14:7];
end
endcase
main_a7ddrphy_bitslip10_r <= {main_a7ddrphy_bitslip10_i, main_a7ddrphy_bitslip10_r[15:8]};
case (main_a7ddrphy_bitslip10_value)
1'd0: begin
main_a7ddrphy_bitslip10_o <= main_a7ddrphy_bitslip10_r[7:0];
end
1'd1: begin
main_a7ddrphy_bitslip10_o <= main_a7ddrphy_bitslip10_r[8:1];
end
2'd2: begin
main_a7ddrphy_bitslip10_o <= main_a7ddrphy_bitslip10_r[9:2];
end
2'd3: begin
main_a7ddrphy_bitslip10_o <= main_a7ddrphy_bitslip10_r[10:3];
end
3'd4: begin
main_a7ddrphy_bitslip10_o <= main_a7ddrphy_bitslip10_r[11:4];
end
3'd5: begin
main_a7ddrphy_bitslip10_o <= main_a7ddrphy_bitslip10_r[12:5];
end
3'd6: begin
main_a7ddrphy_bitslip10_o <= main_a7ddrphy_bitslip10_r[13:6];
end
3'd7: begin
main_a7ddrphy_bitslip10_o <= main_a7ddrphy_bitslip10_r[14:7];
end
endcase
main_a7ddrphy_bitslip11_r <= {main_a7ddrphy_bitslip11_i, main_a7ddrphy_bitslip11_r[15:8]};
case (main_a7ddrphy_bitslip11_value)
1'd0: begin
main_a7ddrphy_bitslip11_o <= main_a7ddrphy_bitslip11_r[7:0];
end
1'd1: begin
main_a7ddrphy_bitslip11_o <= main_a7ddrphy_bitslip11_r[8:1];
end
2'd2: begin
main_a7ddrphy_bitslip11_o <= main_a7ddrphy_bitslip11_r[9:2];
end
2'd3: begin
main_a7ddrphy_bitslip11_o <= main_a7ddrphy_bitslip11_r[10:3];
end
3'd4: begin
main_a7ddrphy_bitslip11_o <= main_a7ddrphy_bitslip11_r[11:4];
end
3'd5: begin
main_a7ddrphy_bitslip11_o <= main_a7ddrphy_bitslip11_r[12:5];
end
3'd6: begin
main_a7ddrphy_bitslip11_o <= main_a7ddrphy_bitslip11_r[13:6];
end
3'd7: begin
main_a7ddrphy_bitslip11_o <= main_a7ddrphy_bitslip11_r[14:7];
end
endcase
main_a7ddrphy_bitslip12_r <= {main_a7ddrphy_bitslip12_i, main_a7ddrphy_bitslip12_r[15:8]};
case (main_a7ddrphy_bitslip12_value)
1'd0: begin
main_a7ddrphy_bitslip12_o <= main_a7ddrphy_bitslip12_r[7:0];
end
1'd1: begin
main_a7ddrphy_bitslip12_o <= main_a7ddrphy_bitslip12_r[8:1];
end
2'd2: begin
main_a7ddrphy_bitslip12_o <= main_a7ddrphy_bitslip12_r[9:2];
end
2'd3: begin
main_a7ddrphy_bitslip12_o <= main_a7ddrphy_bitslip12_r[10:3];
end
3'd4: begin
main_a7ddrphy_bitslip12_o <= main_a7ddrphy_bitslip12_r[11:4];
end
3'd5: begin
main_a7ddrphy_bitslip12_o <= main_a7ddrphy_bitslip12_r[12:5];
end
3'd6: begin
main_a7ddrphy_bitslip12_o <= main_a7ddrphy_bitslip12_r[13:6];
end
3'd7: begin
main_a7ddrphy_bitslip12_o <= main_a7ddrphy_bitslip12_r[14:7];
end
endcase
main_a7ddrphy_bitslip13_r <= {main_a7ddrphy_bitslip13_i, main_a7ddrphy_bitslip13_r[15:8]};
case (main_a7ddrphy_bitslip13_value)
1'd0: begin
main_a7ddrphy_bitslip13_o <= main_a7ddrphy_bitslip13_r[7:0];
end
1'd1: begin
main_a7ddrphy_bitslip13_o <= main_a7ddrphy_bitslip13_r[8:1];
end
2'd2: begin
main_a7ddrphy_bitslip13_o <= main_a7ddrphy_bitslip13_r[9:2];
end
2'd3: begin
main_a7ddrphy_bitslip13_o <= main_a7ddrphy_bitslip13_r[10:3];
end
3'd4: begin
main_a7ddrphy_bitslip13_o <= main_a7ddrphy_bitslip13_r[11:4];
end
3'd5: begin
main_a7ddrphy_bitslip13_o <= main_a7ddrphy_bitslip13_r[12:5];
end
3'd6: begin
main_a7ddrphy_bitslip13_o <= main_a7ddrphy_bitslip13_r[13:6];
end
3'd7: begin
main_a7ddrphy_bitslip13_o <= main_a7ddrphy_bitslip13_r[14:7];
end
endcase
main_a7ddrphy_bitslip14_r <= {main_a7ddrphy_bitslip14_i, main_a7ddrphy_bitslip14_r[15:8]};
case (main_a7ddrphy_bitslip14_value)
1'd0: begin
main_a7ddrphy_bitslip14_o <= main_a7ddrphy_bitslip14_r[7:0];
end
1'd1: begin
main_a7ddrphy_bitslip14_o <= main_a7ddrphy_bitslip14_r[8:1];
end
2'd2: begin
main_a7ddrphy_bitslip14_o <= main_a7ddrphy_bitslip14_r[9:2];
end
2'd3: begin
main_a7ddrphy_bitslip14_o <= main_a7ddrphy_bitslip14_r[10:3];
end
3'd4: begin
main_a7ddrphy_bitslip14_o <= main_a7ddrphy_bitslip14_r[11:4];
end
3'd5: begin
main_a7ddrphy_bitslip14_o <= main_a7ddrphy_bitslip14_r[12:5];
end
3'd6: begin
main_a7ddrphy_bitslip14_o <= main_a7ddrphy_bitslip14_r[13:6];
end
3'd7: begin
main_a7ddrphy_bitslip14_o <= main_a7ddrphy_bitslip14_r[14:7];
end
endcase
main_a7ddrphy_bitslip15_r <= {main_a7ddrphy_bitslip15_i, main_a7ddrphy_bitslip15_r[15:8]};
case (main_a7ddrphy_bitslip15_value)
1'd0: begin
main_a7ddrphy_bitslip15_o <= main_a7ddrphy_bitslip15_r[7:0];
end
1'd1: begin
main_a7ddrphy_bitslip15_o <= main_a7ddrphy_bitslip15_r[8:1];
end
2'd2: begin
main_a7ddrphy_bitslip15_o <= main_a7ddrphy_bitslip15_r[9:2];
end
2'd3: begin
main_a7ddrphy_bitslip15_o <= main_a7ddrphy_bitslip15_r[10:3];
end
3'd4: begin
main_a7ddrphy_bitslip15_o <= main_a7ddrphy_bitslip15_r[11:4];
end
3'd5: begin
main_a7ddrphy_bitslip15_o <= main_a7ddrphy_bitslip15_r[12:5];
end
3'd6: begin
main_a7ddrphy_bitslip15_o <= main_a7ddrphy_bitslip15_r[13:6];
end
3'd7: begin
main_a7ddrphy_bitslip15_o <= main_a7ddrphy_bitslip15_r[14:7];
end
endcase
if (main_sdram_inti_p0_rddata_valid) begin
main_sdram_phaseinjector0_status <= main_sdram_inti_p0_rddata;
end
if (main_sdram_inti_p1_rddata_valid) begin
main_sdram_phaseinjector1_status <= main_sdram_inti_p1_rddata;
end
if (main_sdram_inti_p2_rddata_valid) begin
main_sdram_phaseinjector2_status <= main_sdram_inti_p2_rddata;
end
if (main_sdram_inti_p3_rddata_valid) begin
main_sdram_phaseinjector3_status <= main_sdram_inti_p3_rddata;
end
if ((main_sdram_timer_wait & (~main_sdram_timer_done0))) begin
main_sdram_timer_count1 <= (main_sdram_timer_count1 - 1'd1);
end else begin
main_sdram_timer_count1 <= 9'd390;
end
main_sdram_postponer_req_o <= 1'd0;
if (main_sdram_postponer_req_i) begin
main_sdram_postponer_count <= (main_sdram_postponer_count - 1'd1);
if ((main_sdram_postponer_count == 1'd0)) begin
main_sdram_postponer_count <= 1'd0;
main_sdram_postponer_req_o <= 1'd1;
end
end
if (main_sdram_sequencer_start0) begin
main_sdram_sequencer_count <= 1'd0;
end else begin
if (main_sdram_sequencer_done1) begin
if ((main_sdram_sequencer_count != 1'd0)) begin
main_sdram_sequencer_count <= (main_sdram_sequencer_count - 1'd1);
end
end
end
main_sdram_cmd_payload_a <= 1'd0;
main_sdram_cmd_payload_ba <= 1'd0;
main_sdram_cmd_payload_cas <= 1'd0;
main_sdram_cmd_payload_ras <= 1'd0;
main_sdram_cmd_payload_we <= 1'd0;
main_sdram_sequencer_done1 <= 1'd0;
if ((main_sdram_sequencer_start1 & (main_sdram_sequencer_counter == 1'd0))) begin
main_sdram_cmd_payload_a <= 11'd1024;
main_sdram_cmd_payload_ba <= 1'd0;
main_sdram_cmd_payload_cas <= 1'd0;
main_sdram_cmd_payload_ras <= 1'd1;
main_sdram_cmd_payload_we <= 1'd1;
end
if ((main_sdram_sequencer_counter == 2'd2)) begin
main_sdram_cmd_payload_a <= 1'd0;
main_sdram_cmd_payload_ba <= 1'd0;
main_sdram_cmd_payload_cas <= 1'd1;
main_sdram_cmd_payload_ras <= 1'd1;
main_sdram_cmd_payload_we <= 1'd0;
end
if ((main_sdram_sequencer_counter == 6'd34)) begin
main_sdram_cmd_payload_a <= 1'd0;
main_sdram_cmd_payload_ba <= 1'd0;
main_sdram_cmd_payload_cas <= 1'd0;
main_sdram_cmd_payload_ras <= 1'd0;
main_sdram_cmd_payload_we <= 1'd0;
main_sdram_sequencer_done1 <= 1'd1;
end
if ((main_sdram_sequencer_counter == 6'd34)) begin
main_sdram_sequencer_counter <= 1'd0;
end else begin
if ((main_sdram_sequencer_counter != 1'd0)) begin
main_sdram_sequencer_counter <= (main_sdram_sequencer_counter + 1'd1);
end else begin
if (main_sdram_sequencer_start1) begin
main_sdram_sequencer_counter <= 1'd1;
end
end
end
if ((main_sdram_zqcs_timer_wait & (~main_sdram_zqcs_timer_done0))) begin
main_sdram_zqcs_timer_count1 <= (main_sdram_zqcs_timer_count1 - 1'd1);
end else begin
main_sdram_zqcs_timer_count1 <= 26'd49999999;
end
main_sdram_zqcs_executer_done <= 1'd0;
if ((main_sdram_zqcs_executer_start & (main_sdram_zqcs_executer_counter == 1'd0))) begin
main_sdram_cmd_payload_a <= 11'd1024;
main_sdram_cmd_payload_ba <= 1'd0;
main_sdram_cmd_payload_cas <= 1'd0;
main_sdram_cmd_payload_ras <= 1'd1;
main_sdram_cmd_payload_we <= 1'd1;
end
if ((main_sdram_zqcs_executer_counter == 2'd2)) begin
main_sdram_cmd_payload_a <= 1'd0;
main_sdram_cmd_payload_ba <= 1'd0;
main_sdram_cmd_payload_cas <= 1'd0;
main_sdram_cmd_payload_ras <= 1'd0;
main_sdram_cmd_payload_we <= 1'd1;
end
if ((main_sdram_zqcs_executer_counter == 5'd18)) begin
main_sdram_cmd_payload_a <= 1'd0;
main_sdram_cmd_payload_ba <= 1'd0;
main_sdram_cmd_payload_cas <= 1'd0;
main_sdram_cmd_payload_ras <= 1'd0;
main_sdram_cmd_payload_we <= 1'd0;
main_sdram_zqcs_executer_done <= 1'd1;
end
if ((main_sdram_zqcs_executer_counter == 5'd18)) begin
main_sdram_zqcs_executer_counter <= 1'd0;
end else begin
if ((main_sdram_zqcs_executer_counter != 1'd0)) begin
main_sdram_zqcs_executer_counter <= (main_sdram_zqcs_executer_counter + 1'd1);
end else begin
if (main_sdram_zqcs_executer_start) begin
main_sdram_zqcs_executer_counter <= 1'd1;
end
end
end
builder_refresher_state <= builder_refresher_next_state;
if (main_sdram_bankmachine0_row_close) begin
main_sdram_bankmachine0_row_opened <= 1'd0;
end else begin
if (main_sdram_bankmachine0_row_open) begin
main_sdram_bankmachine0_row_opened <= 1'd1;
main_sdram_bankmachine0_row <= main_sdram_bankmachine0_cmd_buffer_source_payload_addr[20:7];
end
end
if (((main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_we & main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable) & (~main_sdram_bankmachine0_cmd_buffer_lookahead_replace))) begin
main_sdram_bankmachine0_cmd_buffer_lookahead_produce <= (main_sdram_bankmachine0_cmd_buffer_lookahead_produce + 1'd1);
end
if (main_sdram_bankmachine0_cmd_buffer_lookahead_do_read) begin
main_sdram_bankmachine0_cmd_buffer_lookahead_consume <= (main_sdram_bankmachine0_cmd_buffer_lookahead_consume + 1'd1);
end
if (((main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_we & main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable) & (~main_sdram_bankmachine0_cmd_buffer_lookahead_replace))) begin
if ((~main_sdram_bankmachine0_cmd_buffer_lookahead_do_read)) begin
main_sdram_bankmachine0_cmd_buffer_lookahead_level <= (main_sdram_bankmachine0_cmd_buffer_lookahead_level + 1'd1);
end
end else begin
if (main_sdram_bankmachine0_cmd_buffer_lookahead_do_read) begin
main_sdram_bankmachine0_cmd_buffer_lookahead_level <= (main_sdram_bankmachine0_cmd_buffer_lookahead_level - 1'd1);
end
end
if (main_sdram_bankmachine0_cmd_buffer_pipe_ce) begin
main_sdram_bankmachine0_cmd_buffer_valid_n <= main_sdram_bankmachine0_cmd_buffer_sink_valid;
end
if (main_sdram_bankmachine0_cmd_buffer_pipe_ce) begin
main_sdram_bankmachine0_cmd_buffer_first_n <= (main_sdram_bankmachine0_cmd_buffer_sink_valid & main_sdram_bankmachine0_cmd_buffer_sink_first);
main_sdram_bankmachine0_cmd_buffer_last_n <= (main_sdram_bankmachine0_cmd_buffer_sink_valid & main_sdram_bankmachine0_cmd_buffer_sink_last);
end
if (main_sdram_bankmachine0_cmd_buffer_pipe_ce) begin
main_sdram_bankmachine0_cmd_buffer_source_payload_we <= main_sdram_bankmachine0_cmd_buffer_sink_payload_we;
main_sdram_bankmachine0_cmd_buffer_source_payload_addr <= main_sdram_bankmachine0_cmd_buffer_sink_payload_addr;
end
if (main_sdram_bankmachine0_twtpcon_valid) begin
main_sdram_bankmachine0_twtpcon_count <= 3'd4;
if (1'd0) begin
main_sdram_bankmachine0_twtpcon_ready <= 1'd1;
end else begin
main_sdram_bankmachine0_twtpcon_ready <= 1'd0;
end
end else begin
if ((~main_sdram_bankmachine0_twtpcon_ready)) begin
main_sdram_bankmachine0_twtpcon_count <= (main_sdram_bankmachine0_twtpcon_count - 1'd1);
if ((main_sdram_bankmachine0_twtpcon_count == 1'd1)) begin
main_sdram_bankmachine0_twtpcon_ready <= 1'd1;
end
end
end
if (main_sdram_bankmachine0_trccon_valid) begin
main_sdram_bankmachine0_trccon_count <= 2'd3;
if (1'd0) begin
main_sdram_bankmachine0_trccon_ready <= 1'd1;
end else begin
main_sdram_bankmachine0_trccon_ready <= 1'd0;
end
end else begin
if ((~main_sdram_bankmachine0_trccon_ready)) begin
main_sdram_bankmachine0_trccon_count <= (main_sdram_bankmachine0_trccon_count - 1'd1);
if ((main_sdram_bankmachine0_trccon_count == 1'd1)) begin
main_sdram_bankmachine0_trccon_ready <= 1'd1;
end
end
end
if (main_sdram_bankmachine0_trascon_valid) begin
main_sdram_bankmachine0_trascon_count <= 2'd2;
if (1'd0) begin
main_sdram_bankmachine0_trascon_ready <= 1'd1;
end else begin
main_sdram_bankmachine0_trascon_ready <= 1'd0;
end
end else begin
if ((~main_sdram_bankmachine0_trascon_ready)) begin
main_sdram_bankmachine0_trascon_count <= (main_sdram_bankmachine0_trascon_count - 1'd1);
if ((main_sdram_bankmachine0_trascon_count == 1'd1)) begin
main_sdram_bankmachine0_trascon_ready <= 1'd1;
end
end
end
builder_bankmachine0_state <= builder_bankmachine0_next_state;
if (main_sdram_bankmachine1_row_close) begin
main_sdram_bankmachine1_row_opened <= 1'd0;
end else begin
if (main_sdram_bankmachine1_row_open) begin
main_sdram_bankmachine1_row_opened <= 1'd1;
main_sdram_bankmachine1_row <= main_sdram_bankmachine1_cmd_buffer_source_payload_addr[20:7];
end
end
if (((main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_we & main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable) & (~main_sdram_bankmachine1_cmd_buffer_lookahead_replace))) begin
main_sdram_bankmachine1_cmd_buffer_lookahead_produce <= (main_sdram_bankmachine1_cmd_buffer_lookahead_produce + 1'd1);
end
if (main_sdram_bankmachine1_cmd_buffer_lookahead_do_read) begin
main_sdram_bankmachine1_cmd_buffer_lookahead_consume <= (main_sdram_bankmachine1_cmd_buffer_lookahead_consume + 1'd1);
end
if (((main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_we & main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable) & (~main_sdram_bankmachine1_cmd_buffer_lookahead_replace))) begin
if ((~main_sdram_bankmachine1_cmd_buffer_lookahead_do_read)) begin
main_sdram_bankmachine1_cmd_buffer_lookahead_level <= (main_sdram_bankmachine1_cmd_buffer_lookahead_level + 1'd1);
end
end else begin
if (main_sdram_bankmachine1_cmd_buffer_lookahead_do_read) begin
main_sdram_bankmachine1_cmd_buffer_lookahead_level <= (main_sdram_bankmachine1_cmd_buffer_lookahead_level - 1'd1);
end
end
if (main_sdram_bankmachine1_cmd_buffer_pipe_ce) begin
main_sdram_bankmachine1_cmd_buffer_valid_n <= main_sdram_bankmachine1_cmd_buffer_sink_valid;
end
if (main_sdram_bankmachine1_cmd_buffer_pipe_ce) begin
main_sdram_bankmachine1_cmd_buffer_first_n <= (main_sdram_bankmachine1_cmd_buffer_sink_valid & main_sdram_bankmachine1_cmd_buffer_sink_first);
main_sdram_bankmachine1_cmd_buffer_last_n <= (main_sdram_bankmachine1_cmd_buffer_sink_valid & main_sdram_bankmachine1_cmd_buffer_sink_last);
end
if (main_sdram_bankmachine1_cmd_buffer_pipe_ce) begin
main_sdram_bankmachine1_cmd_buffer_source_payload_we <= main_sdram_bankmachine1_cmd_buffer_sink_payload_we;
main_sdram_bankmachine1_cmd_buffer_source_payload_addr <= main_sdram_bankmachine1_cmd_buffer_sink_payload_addr;
end
if (main_sdram_bankmachine1_twtpcon_valid) begin
main_sdram_bankmachine1_twtpcon_count <= 3'd4;
if (1'd0) begin
main_sdram_bankmachine1_twtpcon_ready <= 1'd1;
end else begin
main_sdram_bankmachine1_twtpcon_ready <= 1'd0;
end
end else begin
if ((~main_sdram_bankmachine1_twtpcon_ready)) begin
main_sdram_bankmachine1_twtpcon_count <= (main_sdram_bankmachine1_twtpcon_count - 1'd1);
if ((main_sdram_bankmachine1_twtpcon_count == 1'd1)) begin
main_sdram_bankmachine1_twtpcon_ready <= 1'd1;
end
end
end
if (main_sdram_bankmachine1_trccon_valid) begin
main_sdram_bankmachine1_trccon_count <= 2'd3;
if (1'd0) begin
main_sdram_bankmachine1_trccon_ready <= 1'd1;
end else begin
main_sdram_bankmachine1_trccon_ready <= 1'd0;
end
end else begin
if ((~main_sdram_bankmachine1_trccon_ready)) begin
main_sdram_bankmachine1_trccon_count <= (main_sdram_bankmachine1_trccon_count - 1'd1);
if ((main_sdram_bankmachine1_trccon_count == 1'd1)) begin
main_sdram_bankmachine1_trccon_ready <= 1'd1;
end
end
end
if (main_sdram_bankmachine1_trascon_valid) begin
main_sdram_bankmachine1_trascon_count <= 2'd2;
if (1'd0) begin
main_sdram_bankmachine1_trascon_ready <= 1'd1;
end else begin
main_sdram_bankmachine1_trascon_ready <= 1'd0;
end
end else begin
if ((~main_sdram_bankmachine1_trascon_ready)) begin
main_sdram_bankmachine1_trascon_count <= (main_sdram_bankmachine1_trascon_count - 1'd1);
if ((main_sdram_bankmachine1_trascon_count == 1'd1)) begin
main_sdram_bankmachine1_trascon_ready <= 1'd1;
end
end
end
builder_bankmachine1_state <= builder_bankmachine1_next_state;
if (main_sdram_bankmachine2_row_close) begin
main_sdram_bankmachine2_row_opened <= 1'd0;
end else begin
if (main_sdram_bankmachine2_row_open) begin
main_sdram_bankmachine2_row_opened <= 1'd1;
main_sdram_bankmachine2_row <= main_sdram_bankmachine2_cmd_buffer_source_payload_addr[20:7];
end
end
if (((main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_we & main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable) & (~main_sdram_bankmachine2_cmd_buffer_lookahead_replace))) begin
main_sdram_bankmachine2_cmd_buffer_lookahead_produce <= (main_sdram_bankmachine2_cmd_buffer_lookahead_produce + 1'd1);
end
if (main_sdram_bankmachine2_cmd_buffer_lookahead_do_read) begin
main_sdram_bankmachine2_cmd_buffer_lookahead_consume <= (main_sdram_bankmachine2_cmd_buffer_lookahead_consume + 1'd1);
end
if (((main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_we & main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable) & (~main_sdram_bankmachine2_cmd_buffer_lookahead_replace))) begin
if ((~main_sdram_bankmachine2_cmd_buffer_lookahead_do_read)) begin
main_sdram_bankmachine2_cmd_buffer_lookahead_level <= (main_sdram_bankmachine2_cmd_buffer_lookahead_level + 1'd1);
end
end else begin
if (main_sdram_bankmachine2_cmd_buffer_lookahead_do_read) begin
main_sdram_bankmachine2_cmd_buffer_lookahead_level <= (main_sdram_bankmachine2_cmd_buffer_lookahead_level - 1'd1);
end
end
if (main_sdram_bankmachine2_cmd_buffer_pipe_ce) begin
main_sdram_bankmachine2_cmd_buffer_valid_n <= main_sdram_bankmachine2_cmd_buffer_sink_valid;
end
if (main_sdram_bankmachine2_cmd_buffer_pipe_ce) begin
main_sdram_bankmachine2_cmd_buffer_first_n <= (main_sdram_bankmachine2_cmd_buffer_sink_valid & main_sdram_bankmachine2_cmd_buffer_sink_first);
main_sdram_bankmachine2_cmd_buffer_last_n <= (main_sdram_bankmachine2_cmd_buffer_sink_valid & main_sdram_bankmachine2_cmd_buffer_sink_last);
end
if (main_sdram_bankmachine2_cmd_buffer_pipe_ce) begin
main_sdram_bankmachine2_cmd_buffer_source_payload_we <= main_sdram_bankmachine2_cmd_buffer_sink_payload_we;
main_sdram_bankmachine2_cmd_buffer_source_payload_addr <= main_sdram_bankmachine2_cmd_buffer_sink_payload_addr;
end
if (main_sdram_bankmachine2_twtpcon_valid) begin
main_sdram_bankmachine2_twtpcon_count <= 3'd4;
if (1'd0) begin
main_sdram_bankmachine2_twtpcon_ready <= 1'd1;
end else begin
main_sdram_bankmachine2_twtpcon_ready <= 1'd0;
end
end else begin
if ((~main_sdram_bankmachine2_twtpcon_ready)) begin
main_sdram_bankmachine2_twtpcon_count <= (main_sdram_bankmachine2_twtpcon_count - 1'd1);
if ((main_sdram_bankmachine2_twtpcon_count == 1'd1)) begin
main_sdram_bankmachine2_twtpcon_ready <= 1'd1;
end
end
end
if (main_sdram_bankmachine2_trccon_valid) begin
main_sdram_bankmachine2_trccon_count <= 2'd3;
if (1'd0) begin
main_sdram_bankmachine2_trccon_ready <= 1'd1;
end else begin
main_sdram_bankmachine2_trccon_ready <= 1'd0;
end
end else begin
if ((~main_sdram_bankmachine2_trccon_ready)) begin
main_sdram_bankmachine2_trccon_count <= (main_sdram_bankmachine2_trccon_count - 1'd1);
if ((main_sdram_bankmachine2_trccon_count == 1'd1)) begin
main_sdram_bankmachine2_trccon_ready <= 1'd1;
end
end
end
if (main_sdram_bankmachine2_trascon_valid) begin
main_sdram_bankmachine2_trascon_count <= 2'd2;
if (1'd0) begin
main_sdram_bankmachine2_trascon_ready <= 1'd1;
end else begin
main_sdram_bankmachine2_trascon_ready <= 1'd0;
end
end else begin
if ((~main_sdram_bankmachine2_trascon_ready)) begin
main_sdram_bankmachine2_trascon_count <= (main_sdram_bankmachine2_trascon_count - 1'd1);
if ((main_sdram_bankmachine2_trascon_count == 1'd1)) begin
main_sdram_bankmachine2_trascon_ready <= 1'd1;
end
end
end
builder_bankmachine2_state <= builder_bankmachine2_next_state;
if (main_sdram_bankmachine3_row_close) begin
main_sdram_bankmachine3_row_opened <= 1'd0;
end else begin
if (main_sdram_bankmachine3_row_open) begin
main_sdram_bankmachine3_row_opened <= 1'd1;
main_sdram_bankmachine3_row <= main_sdram_bankmachine3_cmd_buffer_source_payload_addr[20:7];
end
end
if (((main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_we & main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable) & (~main_sdram_bankmachine3_cmd_buffer_lookahead_replace))) begin
main_sdram_bankmachine3_cmd_buffer_lookahead_produce <= (main_sdram_bankmachine3_cmd_buffer_lookahead_produce + 1'd1);
end
if (main_sdram_bankmachine3_cmd_buffer_lookahead_do_read) begin
main_sdram_bankmachine3_cmd_buffer_lookahead_consume <= (main_sdram_bankmachine3_cmd_buffer_lookahead_consume + 1'd1);
end
if (((main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_we & main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable) & (~main_sdram_bankmachine3_cmd_buffer_lookahead_replace))) begin
if ((~main_sdram_bankmachine3_cmd_buffer_lookahead_do_read)) begin
main_sdram_bankmachine3_cmd_buffer_lookahead_level <= (main_sdram_bankmachine3_cmd_buffer_lookahead_level + 1'd1);
end
end else begin
if (main_sdram_bankmachine3_cmd_buffer_lookahead_do_read) begin
main_sdram_bankmachine3_cmd_buffer_lookahead_level <= (main_sdram_bankmachine3_cmd_buffer_lookahead_level - 1'd1);
end
end
if (main_sdram_bankmachine3_cmd_buffer_pipe_ce) begin
main_sdram_bankmachine3_cmd_buffer_valid_n <= main_sdram_bankmachine3_cmd_buffer_sink_valid;
end
if (main_sdram_bankmachine3_cmd_buffer_pipe_ce) begin
main_sdram_bankmachine3_cmd_buffer_first_n <= (main_sdram_bankmachine3_cmd_buffer_sink_valid & main_sdram_bankmachine3_cmd_buffer_sink_first);
main_sdram_bankmachine3_cmd_buffer_last_n <= (main_sdram_bankmachine3_cmd_buffer_sink_valid & main_sdram_bankmachine3_cmd_buffer_sink_last);
end
if (main_sdram_bankmachine3_cmd_buffer_pipe_ce) begin
main_sdram_bankmachine3_cmd_buffer_source_payload_we <= main_sdram_bankmachine3_cmd_buffer_sink_payload_we;
main_sdram_bankmachine3_cmd_buffer_source_payload_addr <= main_sdram_bankmachine3_cmd_buffer_sink_payload_addr;
end
if (main_sdram_bankmachine3_twtpcon_valid) begin
main_sdram_bankmachine3_twtpcon_count <= 3'd4;
if (1'd0) begin
main_sdram_bankmachine3_twtpcon_ready <= 1'd1;
end else begin
main_sdram_bankmachine3_twtpcon_ready <= 1'd0;
end
end else begin
if ((~main_sdram_bankmachine3_twtpcon_ready)) begin
main_sdram_bankmachine3_twtpcon_count <= (main_sdram_bankmachine3_twtpcon_count - 1'd1);
if ((main_sdram_bankmachine3_twtpcon_count == 1'd1)) begin
main_sdram_bankmachine3_twtpcon_ready <= 1'd1;
end
end
end
if (main_sdram_bankmachine3_trccon_valid) begin
main_sdram_bankmachine3_trccon_count <= 2'd3;
if (1'd0) begin
main_sdram_bankmachine3_trccon_ready <= 1'd1;
end else begin
main_sdram_bankmachine3_trccon_ready <= 1'd0;
end
end else begin
if ((~main_sdram_bankmachine3_trccon_ready)) begin
main_sdram_bankmachine3_trccon_count <= (main_sdram_bankmachine3_trccon_count - 1'd1);
if ((main_sdram_bankmachine3_trccon_count == 1'd1)) begin
main_sdram_bankmachine3_trccon_ready <= 1'd1;
end
end
end
if (main_sdram_bankmachine3_trascon_valid) begin
main_sdram_bankmachine3_trascon_count <= 2'd2;
if (1'd0) begin
main_sdram_bankmachine3_trascon_ready <= 1'd1;
end else begin
main_sdram_bankmachine3_trascon_ready <= 1'd0;
end
end else begin
if ((~main_sdram_bankmachine3_trascon_ready)) begin
main_sdram_bankmachine3_trascon_count <= (main_sdram_bankmachine3_trascon_count - 1'd1);
if ((main_sdram_bankmachine3_trascon_count == 1'd1)) begin
main_sdram_bankmachine3_trascon_ready <= 1'd1;
end
end
end
builder_bankmachine3_state <= builder_bankmachine3_next_state;
if (main_sdram_bankmachine4_row_close) begin
main_sdram_bankmachine4_row_opened <= 1'd0;
end else begin
if (main_sdram_bankmachine4_row_open) begin
main_sdram_bankmachine4_row_opened <= 1'd1;
main_sdram_bankmachine4_row <= main_sdram_bankmachine4_cmd_buffer_source_payload_addr[20:7];
end
end
if (((main_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_we & main_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable) & (~main_sdram_bankmachine4_cmd_buffer_lookahead_replace))) begin
main_sdram_bankmachine4_cmd_buffer_lookahead_produce <= (main_sdram_bankmachine4_cmd_buffer_lookahead_produce + 1'd1);
end
if (main_sdram_bankmachine4_cmd_buffer_lookahead_do_read) begin
main_sdram_bankmachine4_cmd_buffer_lookahead_consume <= (main_sdram_bankmachine4_cmd_buffer_lookahead_consume + 1'd1);
end
if (((main_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_we & main_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable) & (~main_sdram_bankmachine4_cmd_buffer_lookahead_replace))) begin
if ((~main_sdram_bankmachine4_cmd_buffer_lookahead_do_read)) begin
main_sdram_bankmachine4_cmd_buffer_lookahead_level <= (main_sdram_bankmachine4_cmd_buffer_lookahead_level + 1'd1);
end
end else begin
if (main_sdram_bankmachine4_cmd_buffer_lookahead_do_read) begin
main_sdram_bankmachine4_cmd_buffer_lookahead_level <= (main_sdram_bankmachine4_cmd_buffer_lookahead_level - 1'd1);
end
end
if (main_sdram_bankmachine4_cmd_buffer_pipe_ce) begin
main_sdram_bankmachine4_cmd_buffer_valid_n <= main_sdram_bankmachine4_cmd_buffer_sink_valid;
end
if (main_sdram_bankmachine4_cmd_buffer_pipe_ce) begin
main_sdram_bankmachine4_cmd_buffer_first_n <= (main_sdram_bankmachine4_cmd_buffer_sink_valid & main_sdram_bankmachine4_cmd_buffer_sink_first);
main_sdram_bankmachine4_cmd_buffer_last_n <= (main_sdram_bankmachine4_cmd_buffer_sink_valid & main_sdram_bankmachine4_cmd_buffer_sink_last);
end
if (main_sdram_bankmachine4_cmd_buffer_pipe_ce) begin
main_sdram_bankmachine4_cmd_buffer_source_payload_we <= main_sdram_bankmachine4_cmd_buffer_sink_payload_we;
main_sdram_bankmachine4_cmd_buffer_source_payload_addr <= main_sdram_bankmachine4_cmd_buffer_sink_payload_addr;
end
if (main_sdram_bankmachine4_twtpcon_valid) begin
main_sdram_bankmachine4_twtpcon_count <= 3'd4;
if (1'd0) begin
main_sdram_bankmachine4_twtpcon_ready <= 1'd1;
end else begin
main_sdram_bankmachine4_twtpcon_ready <= 1'd0;
end
end else begin
if ((~main_sdram_bankmachine4_twtpcon_ready)) begin
main_sdram_bankmachine4_twtpcon_count <= (main_sdram_bankmachine4_twtpcon_count - 1'd1);
if ((main_sdram_bankmachine4_twtpcon_count == 1'd1)) begin
main_sdram_bankmachine4_twtpcon_ready <= 1'd1;
end
end
end
if (main_sdram_bankmachine4_trccon_valid) begin
main_sdram_bankmachine4_trccon_count <= 2'd3;
if (1'd0) begin
main_sdram_bankmachine4_trccon_ready <= 1'd1;
end else begin
main_sdram_bankmachine4_trccon_ready <= 1'd0;
end
end else begin
if ((~main_sdram_bankmachine4_trccon_ready)) begin
main_sdram_bankmachine4_trccon_count <= (main_sdram_bankmachine4_trccon_count - 1'd1);
if ((main_sdram_bankmachine4_trccon_count == 1'd1)) begin
main_sdram_bankmachine4_trccon_ready <= 1'd1;
end
end
end
if (main_sdram_bankmachine4_trascon_valid) begin
main_sdram_bankmachine4_trascon_count <= 2'd2;
if (1'd0) begin
main_sdram_bankmachine4_trascon_ready <= 1'd1;
end else begin
main_sdram_bankmachine4_trascon_ready <= 1'd0;
end
end else begin
if ((~main_sdram_bankmachine4_trascon_ready)) begin
main_sdram_bankmachine4_trascon_count <= (main_sdram_bankmachine4_trascon_count - 1'd1);
if ((main_sdram_bankmachine4_trascon_count == 1'd1)) begin
main_sdram_bankmachine4_trascon_ready <= 1'd1;
end
end
end
builder_bankmachine4_state <= builder_bankmachine4_next_state;
if (main_sdram_bankmachine5_row_close) begin
main_sdram_bankmachine5_row_opened <= 1'd0;
end else begin
if (main_sdram_bankmachine5_row_open) begin
main_sdram_bankmachine5_row_opened <= 1'd1;
main_sdram_bankmachine5_row <= main_sdram_bankmachine5_cmd_buffer_source_payload_addr[20:7];
end
end
if (((main_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_we & main_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable) & (~main_sdram_bankmachine5_cmd_buffer_lookahead_replace))) begin
main_sdram_bankmachine5_cmd_buffer_lookahead_produce <= (main_sdram_bankmachine5_cmd_buffer_lookahead_produce + 1'd1);
end
if (main_sdram_bankmachine5_cmd_buffer_lookahead_do_read) begin
main_sdram_bankmachine5_cmd_buffer_lookahead_consume <= (main_sdram_bankmachine5_cmd_buffer_lookahead_consume + 1'd1);
end
if (((main_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_we & main_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable) & (~main_sdram_bankmachine5_cmd_buffer_lookahead_replace))) begin
if ((~main_sdram_bankmachine5_cmd_buffer_lookahead_do_read)) begin
main_sdram_bankmachine5_cmd_buffer_lookahead_level <= (main_sdram_bankmachine5_cmd_buffer_lookahead_level + 1'd1);
end
end else begin
if (main_sdram_bankmachine5_cmd_buffer_lookahead_do_read) begin
main_sdram_bankmachine5_cmd_buffer_lookahead_level <= (main_sdram_bankmachine5_cmd_buffer_lookahead_level - 1'd1);
end
end
if (main_sdram_bankmachine5_cmd_buffer_pipe_ce) begin
main_sdram_bankmachine5_cmd_buffer_valid_n <= main_sdram_bankmachine5_cmd_buffer_sink_valid;
end
if (main_sdram_bankmachine5_cmd_buffer_pipe_ce) begin
main_sdram_bankmachine5_cmd_buffer_first_n <= (main_sdram_bankmachine5_cmd_buffer_sink_valid & main_sdram_bankmachine5_cmd_buffer_sink_first);
main_sdram_bankmachine5_cmd_buffer_last_n <= (main_sdram_bankmachine5_cmd_buffer_sink_valid & main_sdram_bankmachine5_cmd_buffer_sink_last);
end
if (main_sdram_bankmachine5_cmd_buffer_pipe_ce) begin
main_sdram_bankmachine5_cmd_buffer_source_payload_we <= main_sdram_bankmachine5_cmd_buffer_sink_payload_we;
main_sdram_bankmachine5_cmd_buffer_source_payload_addr <= main_sdram_bankmachine5_cmd_buffer_sink_payload_addr;
end
if (main_sdram_bankmachine5_twtpcon_valid) begin
main_sdram_bankmachine5_twtpcon_count <= 3'd4;
if (1'd0) begin
main_sdram_bankmachine5_twtpcon_ready <= 1'd1;
end else begin
main_sdram_bankmachine5_twtpcon_ready <= 1'd0;
end
end else begin
if ((~main_sdram_bankmachine5_twtpcon_ready)) begin
main_sdram_bankmachine5_twtpcon_count <= (main_sdram_bankmachine5_twtpcon_count - 1'd1);
if ((main_sdram_bankmachine5_twtpcon_count == 1'd1)) begin
main_sdram_bankmachine5_twtpcon_ready <= 1'd1;
end
end
end
if (main_sdram_bankmachine5_trccon_valid) begin
main_sdram_bankmachine5_trccon_count <= 2'd3;
if (1'd0) begin
main_sdram_bankmachine5_trccon_ready <= 1'd1;
end else begin
main_sdram_bankmachine5_trccon_ready <= 1'd0;
end
end else begin
if ((~main_sdram_bankmachine5_trccon_ready)) begin
main_sdram_bankmachine5_trccon_count <= (main_sdram_bankmachine5_trccon_count - 1'd1);
if ((main_sdram_bankmachine5_trccon_count == 1'd1)) begin
main_sdram_bankmachine5_trccon_ready <= 1'd1;
end
end
end
if (main_sdram_bankmachine5_trascon_valid) begin
main_sdram_bankmachine5_trascon_count <= 2'd2;
if (1'd0) begin
main_sdram_bankmachine5_trascon_ready <= 1'd1;
end else begin
main_sdram_bankmachine5_trascon_ready <= 1'd0;
end
end else begin
if ((~main_sdram_bankmachine5_trascon_ready)) begin
main_sdram_bankmachine5_trascon_count <= (main_sdram_bankmachine5_trascon_count - 1'd1);
if ((main_sdram_bankmachine5_trascon_count == 1'd1)) begin
main_sdram_bankmachine5_trascon_ready <= 1'd1;
end
end
end
builder_bankmachine5_state <= builder_bankmachine5_next_state;
if (main_sdram_bankmachine6_row_close) begin
main_sdram_bankmachine6_row_opened <= 1'd0;
end else begin
if (main_sdram_bankmachine6_row_open) begin
main_sdram_bankmachine6_row_opened <= 1'd1;
main_sdram_bankmachine6_row <= main_sdram_bankmachine6_cmd_buffer_source_payload_addr[20:7];
end
end
if (((main_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_we & main_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable) & (~main_sdram_bankmachine6_cmd_buffer_lookahead_replace))) begin
main_sdram_bankmachine6_cmd_buffer_lookahead_produce <= (main_sdram_bankmachine6_cmd_buffer_lookahead_produce + 1'd1);
end
if (main_sdram_bankmachine6_cmd_buffer_lookahead_do_read) begin
main_sdram_bankmachine6_cmd_buffer_lookahead_consume <= (main_sdram_bankmachine6_cmd_buffer_lookahead_consume + 1'd1);
end
if (((main_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_we & main_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable) & (~main_sdram_bankmachine6_cmd_buffer_lookahead_replace))) begin
if ((~main_sdram_bankmachine6_cmd_buffer_lookahead_do_read)) begin
main_sdram_bankmachine6_cmd_buffer_lookahead_level <= (main_sdram_bankmachine6_cmd_buffer_lookahead_level + 1'd1);
end
end else begin
if (main_sdram_bankmachine6_cmd_buffer_lookahead_do_read) begin
main_sdram_bankmachine6_cmd_buffer_lookahead_level <= (main_sdram_bankmachine6_cmd_buffer_lookahead_level - 1'd1);
end
end
if (main_sdram_bankmachine6_cmd_buffer_pipe_ce) begin
main_sdram_bankmachine6_cmd_buffer_valid_n <= main_sdram_bankmachine6_cmd_buffer_sink_valid;
end
if (main_sdram_bankmachine6_cmd_buffer_pipe_ce) begin
main_sdram_bankmachine6_cmd_buffer_first_n <= (main_sdram_bankmachine6_cmd_buffer_sink_valid & main_sdram_bankmachine6_cmd_buffer_sink_first);
main_sdram_bankmachine6_cmd_buffer_last_n <= (main_sdram_bankmachine6_cmd_buffer_sink_valid & main_sdram_bankmachine6_cmd_buffer_sink_last);
end
if (main_sdram_bankmachine6_cmd_buffer_pipe_ce) begin
main_sdram_bankmachine6_cmd_buffer_source_payload_we <= main_sdram_bankmachine6_cmd_buffer_sink_payload_we;
main_sdram_bankmachine6_cmd_buffer_source_payload_addr <= main_sdram_bankmachine6_cmd_buffer_sink_payload_addr;
end
if (main_sdram_bankmachine6_twtpcon_valid) begin
main_sdram_bankmachine6_twtpcon_count <= 3'd4;
if (1'd0) begin
main_sdram_bankmachine6_twtpcon_ready <= 1'd1;
end else begin
main_sdram_bankmachine6_twtpcon_ready <= 1'd0;
end
end else begin
if ((~main_sdram_bankmachine6_twtpcon_ready)) begin
main_sdram_bankmachine6_twtpcon_count <= (main_sdram_bankmachine6_twtpcon_count - 1'd1);
if ((main_sdram_bankmachine6_twtpcon_count == 1'd1)) begin
main_sdram_bankmachine6_twtpcon_ready <= 1'd1;
end
end
end
if (main_sdram_bankmachine6_trccon_valid) begin
main_sdram_bankmachine6_trccon_count <= 2'd3;
if (1'd0) begin
main_sdram_bankmachine6_trccon_ready <= 1'd1;
end else begin
main_sdram_bankmachine6_trccon_ready <= 1'd0;
end
end else begin
if ((~main_sdram_bankmachine6_trccon_ready)) begin
main_sdram_bankmachine6_trccon_count <= (main_sdram_bankmachine6_trccon_count - 1'd1);
if ((main_sdram_bankmachine6_trccon_count == 1'd1)) begin
main_sdram_bankmachine6_trccon_ready <= 1'd1;
end
end
end
if (main_sdram_bankmachine6_trascon_valid) begin
main_sdram_bankmachine6_trascon_count <= 2'd2;
if (1'd0) begin
main_sdram_bankmachine6_trascon_ready <= 1'd1;
end else begin
main_sdram_bankmachine6_trascon_ready <= 1'd0;
end
end else begin
if ((~main_sdram_bankmachine6_trascon_ready)) begin
main_sdram_bankmachine6_trascon_count <= (main_sdram_bankmachine6_trascon_count - 1'd1);
if ((main_sdram_bankmachine6_trascon_count == 1'd1)) begin
main_sdram_bankmachine6_trascon_ready <= 1'd1;
end
end
end
builder_bankmachine6_state <= builder_bankmachine6_next_state;
if (main_sdram_bankmachine7_row_close) begin
main_sdram_bankmachine7_row_opened <= 1'd0;
end else begin
if (main_sdram_bankmachine7_row_open) begin
main_sdram_bankmachine7_row_opened <= 1'd1;
main_sdram_bankmachine7_row <= main_sdram_bankmachine7_cmd_buffer_source_payload_addr[20:7];
end
end
if (((main_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_we & main_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable) & (~main_sdram_bankmachine7_cmd_buffer_lookahead_replace))) begin
main_sdram_bankmachine7_cmd_buffer_lookahead_produce <= (main_sdram_bankmachine7_cmd_buffer_lookahead_produce + 1'd1);
end
if (main_sdram_bankmachine7_cmd_buffer_lookahead_do_read) begin
main_sdram_bankmachine7_cmd_buffer_lookahead_consume <= (main_sdram_bankmachine7_cmd_buffer_lookahead_consume + 1'd1);
end
if (((main_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_we & main_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable) & (~main_sdram_bankmachine7_cmd_buffer_lookahead_replace))) begin
if ((~main_sdram_bankmachine7_cmd_buffer_lookahead_do_read)) begin
main_sdram_bankmachine7_cmd_buffer_lookahead_level <= (main_sdram_bankmachine7_cmd_buffer_lookahead_level + 1'd1);
end
end else begin
if (main_sdram_bankmachine7_cmd_buffer_lookahead_do_read) begin
main_sdram_bankmachine7_cmd_buffer_lookahead_level <= (main_sdram_bankmachine7_cmd_buffer_lookahead_level - 1'd1);
end
end
if (main_sdram_bankmachine7_cmd_buffer_pipe_ce) begin
main_sdram_bankmachine7_cmd_buffer_valid_n <= main_sdram_bankmachine7_cmd_buffer_sink_valid;
end
if (main_sdram_bankmachine7_cmd_buffer_pipe_ce) begin
main_sdram_bankmachine7_cmd_buffer_first_n <= (main_sdram_bankmachine7_cmd_buffer_sink_valid & main_sdram_bankmachine7_cmd_buffer_sink_first);
main_sdram_bankmachine7_cmd_buffer_last_n <= (main_sdram_bankmachine7_cmd_buffer_sink_valid & main_sdram_bankmachine7_cmd_buffer_sink_last);
end
if (main_sdram_bankmachine7_cmd_buffer_pipe_ce) begin
main_sdram_bankmachine7_cmd_buffer_source_payload_we <= main_sdram_bankmachine7_cmd_buffer_sink_payload_we;
main_sdram_bankmachine7_cmd_buffer_source_payload_addr <= main_sdram_bankmachine7_cmd_buffer_sink_payload_addr;
end
if (main_sdram_bankmachine7_twtpcon_valid) begin
main_sdram_bankmachine7_twtpcon_count <= 3'd4;
if (1'd0) begin
main_sdram_bankmachine7_twtpcon_ready <= 1'd1;
end else begin
main_sdram_bankmachine7_twtpcon_ready <= 1'd0;
end
end else begin
if ((~main_sdram_bankmachine7_twtpcon_ready)) begin
main_sdram_bankmachine7_twtpcon_count <= (main_sdram_bankmachine7_twtpcon_count - 1'd1);
if ((main_sdram_bankmachine7_twtpcon_count == 1'd1)) begin
main_sdram_bankmachine7_twtpcon_ready <= 1'd1;
end
end
end
if (main_sdram_bankmachine7_trccon_valid) begin
main_sdram_bankmachine7_trccon_count <= 2'd3;
if (1'd0) begin
main_sdram_bankmachine7_trccon_ready <= 1'd1;
end else begin
main_sdram_bankmachine7_trccon_ready <= 1'd0;
end
end else begin
if ((~main_sdram_bankmachine7_trccon_ready)) begin
main_sdram_bankmachine7_trccon_count <= (main_sdram_bankmachine7_trccon_count - 1'd1);
if ((main_sdram_bankmachine7_trccon_count == 1'd1)) begin
main_sdram_bankmachine7_trccon_ready <= 1'd1;
end
end
end
if (main_sdram_bankmachine7_trascon_valid) begin
main_sdram_bankmachine7_trascon_count <= 2'd2;
if (1'd0) begin
main_sdram_bankmachine7_trascon_ready <= 1'd1;
end else begin
main_sdram_bankmachine7_trascon_ready <= 1'd0;
end
end else begin
if ((~main_sdram_bankmachine7_trascon_ready)) begin
main_sdram_bankmachine7_trascon_count <= (main_sdram_bankmachine7_trascon_count - 1'd1);
if ((main_sdram_bankmachine7_trascon_count == 1'd1)) begin
main_sdram_bankmachine7_trascon_ready <= 1'd1;
end
end
end
builder_bankmachine7_state <= builder_bankmachine7_next_state;
if ((~main_sdram_en0)) begin
main_sdram_time0 <= 5'd31;
end else begin
if ((~main_sdram_max_time0)) begin
main_sdram_time0 <= (main_sdram_time0 - 1'd1);
end
end
if ((~main_sdram_en1)) begin
main_sdram_time1 <= 4'd15;
end else begin
if ((~main_sdram_max_time1)) begin
main_sdram_time1 <= (main_sdram_time1 - 1'd1);
end
end
if (main_sdram_choose_cmd_ce) begin
case (main_sdram_choose_cmd_grant)
1'd0: begin
if (main_sdram_choose_cmd_request[1]) begin
main_sdram_choose_cmd_grant <= 1'd1;
end else begin
if (main_sdram_choose_cmd_request[2]) begin
main_sdram_choose_cmd_grant <= 2'd2;
end else begin
if (main_sdram_choose_cmd_request[3]) begin
main_sdram_choose_cmd_grant <= 2'd3;
end else begin
if (main_sdram_choose_cmd_request[4]) begin
main_sdram_choose_cmd_grant <= 3'd4;
end else begin
if (main_sdram_choose_cmd_request[5]) begin
main_sdram_choose_cmd_grant <= 3'd5;
end else begin
if (main_sdram_choose_cmd_request[6]) begin
main_sdram_choose_cmd_grant <= 3'd6;
end else begin
if (main_sdram_choose_cmd_request[7]) begin
main_sdram_choose_cmd_grant <= 3'd7;
end
end
end
end
end
end
end
end
1'd1: begin
if (main_sdram_choose_cmd_request[2]) begin
main_sdram_choose_cmd_grant <= 2'd2;
end else begin
if (main_sdram_choose_cmd_request[3]) begin
main_sdram_choose_cmd_grant <= 2'd3;
end else begin
if (main_sdram_choose_cmd_request[4]) begin
main_sdram_choose_cmd_grant <= 3'd4;
end else begin
if (main_sdram_choose_cmd_request[5]) begin
main_sdram_choose_cmd_grant <= 3'd5;
end else begin
if (main_sdram_choose_cmd_request[6]) begin
main_sdram_choose_cmd_grant <= 3'd6;
end else begin
if (main_sdram_choose_cmd_request[7]) begin
main_sdram_choose_cmd_grant <= 3'd7;
end else begin
if (main_sdram_choose_cmd_request[0]) begin
main_sdram_choose_cmd_grant <= 1'd0;
end
end
end
end
end
end
end
end
2'd2: begin
if (main_sdram_choose_cmd_request[3]) begin
main_sdram_choose_cmd_grant <= 2'd3;
end else begin
if (main_sdram_choose_cmd_request[4]) begin
main_sdram_choose_cmd_grant <= 3'd4;
end else begin
if (main_sdram_choose_cmd_request[5]) begin
main_sdram_choose_cmd_grant <= 3'd5;
end else begin
if (main_sdram_choose_cmd_request[6]) begin
main_sdram_choose_cmd_grant <= 3'd6;
end else begin
if (main_sdram_choose_cmd_request[7]) begin
main_sdram_choose_cmd_grant <= 3'd7;
end else begin
if (main_sdram_choose_cmd_request[0]) begin
main_sdram_choose_cmd_grant <= 1'd0;
end else begin
if (main_sdram_choose_cmd_request[1]) begin
main_sdram_choose_cmd_grant <= 1'd1;
end
end
end
end
end
end
end
end
2'd3: begin
if (main_sdram_choose_cmd_request[4]) begin
main_sdram_choose_cmd_grant <= 3'd4;
end else begin
if (main_sdram_choose_cmd_request[5]) begin
main_sdram_choose_cmd_grant <= 3'd5;
end else begin
if (main_sdram_choose_cmd_request[6]) begin
main_sdram_choose_cmd_grant <= 3'd6;
end else begin
if (main_sdram_choose_cmd_request[7]) begin
main_sdram_choose_cmd_grant <= 3'd7;
end else begin
if (main_sdram_choose_cmd_request[0]) begin
main_sdram_choose_cmd_grant <= 1'd0;
end else begin
if (main_sdram_choose_cmd_request[1]) begin
main_sdram_choose_cmd_grant <= 1'd1;
end else begin
if (main_sdram_choose_cmd_request[2]) begin
main_sdram_choose_cmd_grant <= 2'd2;
end
end
end
end
end
end
end
end
3'd4: begin
if (main_sdram_choose_cmd_request[5]) begin
main_sdram_choose_cmd_grant <= 3'd5;
end else begin
if (main_sdram_choose_cmd_request[6]) begin
main_sdram_choose_cmd_grant <= 3'd6;
end else begin
if (main_sdram_choose_cmd_request[7]) begin
main_sdram_choose_cmd_grant <= 3'd7;
end else begin
if (main_sdram_choose_cmd_request[0]) begin
main_sdram_choose_cmd_grant <= 1'd0;
end else begin
if (main_sdram_choose_cmd_request[1]) begin
main_sdram_choose_cmd_grant <= 1'd1;
end else begin
if (main_sdram_choose_cmd_request[2]) begin
main_sdram_choose_cmd_grant <= 2'd2;
end else begin
if (main_sdram_choose_cmd_request[3]) begin
main_sdram_choose_cmd_grant <= 2'd3;
end
end
end
end
end
end
end
end
3'd5: begin
if (main_sdram_choose_cmd_request[6]) begin
main_sdram_choose_cmd_grant <= 3'd6;
end else begin
if (main_sdram_choose_cmd_request[7]) begin
main_sdram_choose_cmd_grant <= 3'd7;
end else begin
if (main_sdram_choose_cmd_request[0]) begin
main_sdram_choose_cmd_grant <= 1'd0;
end else begin
if (main_sdram_choose_cmd_request[1]) begin
main_sdram_choose_cmd_grant <= 1'd1;
end else begin
if (main_sdram_choose_cmd_request[2]) begin
main_sdram_choose_cmd_grant <= 2'd2;
end else begin
if (main_sdram_choose_cmd_request[3]) begin
main_sdram_choose_cmd_grant <= 2'd3;
end else begin
if (main_sdram_choose_cmd_request[4]) begin
main_sdram_choose_cmd_grant <= 3'd4;
end
end
end
end
end
end
end
end
3'd6: begin
if (main_sdram_choose_cmd_request[7]) begin
main_sdram_choose_cmd_grant <= 3'd7;
end else begin
if (main_sdram_choose_cmd_request[0]) begin
main_sdram_choose_cmd_grant <= 1'd0;
end else begin
if (main_sdram_choose_cmd_request[1]) begin
main_sdram_choose_cmd_grant <= 1'd1;
end else begin
if (main_sdram_choose_cmd_request[2]) begin
main_sdram_choose_cmd_grant <= 2'd2;
end else begin
if (main_sdram_choose_cmd_request[3]) begin
main_sdram_choose_cmd_grant <= 2'd3;
end else begin
if (main_sdram_choose_cmd_request[4]) begin
main_sdram_choose_cmd_grant <= 3'd4;
end else begin
if (main_sdram_choose_cmd_request[5]) begin
main_sdram_choose_cmd_grant <= 3'd5;
end
end
end
end
end
end
end
end
3'd7: begin
if (main_sdram_choose_cmd_request[0]) begin
main_sdram_choose_cmd_grant <= 1'd0;
end else begin
if (main_sdram_choose_cmd_request[1]) begin
main_sdram_choose_cmd_grant <= 1'd1;
end else begin
if (main_sdram_choose_cmd_request[2]) begin
main_sdram_choose_cmd_grant <= 2'd2;
end else begin
if (main_sdram_choose_cmd_request[3]) begin
main_sdram_choose_cmd_grant <= 2'd3;
end else begin
if (main_sdram_choose_cmd_request[4]) begin
main_sdram_choose_cmd_grant <= 3'd4;
end else begin
if (main_sdram_choose_cmd_request[5]) begin
main_sdram_choose_cmd_grant <= 3'd5;
end else begin
if (main_sdram_choose_cmd_request[6]) begin
main_sdram_choose_cmd_grant <= 3'd6;
end
end
end
end
end
end
end
end
endcase
end
if (main_sdram_choose_req_ce) begin
case (main_sdram_choose_req_grant)
1'd0: begin
if (main_sdram_choose_req_request[1]) begin
main_sdram_choose_req_grant <= 1'd1;
end else begin
if (main_sdram_choose_req_request[2]) begin
main_sdram_choose_req_grant <= 2'd2;
end else begin
if (main_sdram_choose_req_request[3]) begin
main_sdram_choose_req_grant <= 2'd3;
end else begin
if (main_sdram_choose_req_request[4]) begin
main_sdram_choose_req_grant <= 3'd4;
end else begin
if (main_sdram_choose_req_request[5]) begin
main_sdram_choose_req_grant <= 3'd5;
end else begin
if (main_sdram_choose_req_request[6]) begin
main_sdram_choose_req_grant <= 3'd6;
end else begin
if (main_sdram_choose_req_request[7]) begin
main_sdram_choose_req_grant <= 3'd7;
end
end
end
end
end
end
end
end
1'd1: begin
if (main_sdram_choose_req_request[2]) begin
main_sdram_choose_req_grant <= 2'd2;
end else begin
if (main_sdram_choose_req_request[3]) begin
main_sdram_choose_req_grant <= 2'd3;
end else begin
if (main_sdram_choose_req_request[4]) begin
main_sdram_choose_req_grant <= 3'd4;
end else begin
if (main_sdram_choose_req_request[5]) begin
main_sdram_choose_req_grant <= 3'd5;
end else begin
if (main_sdram_choose_req_request[6]) begin
main_sdram_choose_req_grant <= 3'd6;
end else begin
if (main_sdram_choose_req_request[7]) begin
main_sdram_choose_req_grant <= 3'd7;
end else begin
if (main_sdram_choose_req_request[0]) begin
main_sdram_choose_req_grant <= 1'd0;
end
end
end
end
end
end
end
end
2'd2: begin
if (main_sdram_choose_req_request[3]) begin
main_sdram_choose_req_grant <= 2'd3;
end else begin
if (main_sdram_choose_req_request[4]) begin
main_sdram_choose_req_grant <= 3'd4;
end else begin
if (main_sdram_choose_req_request[5]) begin
main_sdram_choose_req_grant <= 3'd5;
end else begin
if (main_sdram_choose_req_request[6]) begin
main_sdram_choose_req_grant <= 3'd6;
end else begin
if (main_sdram_choose_req_request[7]) begin
main_sdram_choose_req_grant <= 3'd7;
end else begin
if (main_sdram_choose_req_request[0]) begin
main_sdram_choose_req_grant <= 1'd0;
end else begin
if (main_sdram_choose_req_request[1]) begin
main_sdram_choose_req_grant <= 1'd1;
end
end
end
end
end
end
end
end
2'd3: begin
if (main_sdram_choose_req_request[4]) begin
main_sdram_choose_req_grant <= 3'd4;
end else begin
if (main_sdram_choose_req_request[5]) begin
main_sdram_choose_req_grant <= 3'd5;
end else begin
if (main_sdram_choose_req_request[6]) begin
main_sdram_choose_req_grant <= 3'd6;
end else begin
if (main_sdram_choose_req_request[7]) begin
main_sdram_choose_req_grant <= 3'd7;
end else begin
if (main_sdram_choose_req_request[0]) begin
main_sdram_choose_req_grant <= 1'd0;
end else begin
if (main_sdram_choose_req_request[1]) begin
main_sdram_choose_req_grant <= 1'd1;
end else begin
if (main_sdram_choose_req_request[2]) begin
main_sdram_choose_req_grant <= 2'd2;
end
end
end
end
end
end
end
end
3'd4: begin
if (main_sdram_choose_req_request[5]) begin
main_sdram_choose_req_grant <= 3'd5;
end else begin
if (main_sdram_choose_req_request[6]) begin
main_sdram_choose_req_grant <= 3'd6;
end else begin
if (main_sdram_choose_req_request[7]) begin
main_sdram_choose_req_grant <= 3'd7;
end else begin
if (main_sdram_choose_req_request[0]) begin
main_sdram_choose_req_grant <= 1'd0;
end else begin
if (main_sdram_choose_req_request[1]) begin
main_sdram_choose_req_grant <= 1'd1;
end else begin
if (main_sdram_choose_req_request[2]) begin
main_sdram_choose_req_grant <= 2'd2;
end else begin
if (main_sdram_choose_req_request[3]) begin
main_sdram_choose_req_grant <= 2'd3;
end
end
end
end
end
end
end
end
3'd5: begin
if (main_sdram_choose_req_request[6]) begin
main_sdram_choose_req_grant <= 3'd6;
end else begin
if (main_sdram_choose_req_request[7]) begin
main_sdram_choose_req_grant <= 3'd7;
end else begin
if (main_sdram_choose_req_request[0]) begin
main_sdram_choose_req_grant <= 1'd0;
end else begin
if (main_sdram_choose_req_request[1]) begin
main_sdram_choose_req_grant <= 1'd1;
end else begin
if (main_sdram_choose_req_request[2]) begin
main_sdram_choose_req_grant <= 2'd2;
end else begin
if (main_sdram_choose_req_request[3]) begin
main_sdram_choose_req_grant <= 2'd3;
end else begin
if (main_sdram_choose_req_request[4]) begin
main_sdram_choose_req_grant <= 3'd4;
end
end
end
end
end
end
end
end
3'd6: begin
if (main_sdram_choose_req_request[7]) begin
main_sdram_choose_req_grant <= 3'd7;
end else begin
if (main_sdram_choose_req_request[0]) begin
main_sdram_choose_req_grant <= 1'd0;
end else begin
if (main_sdram_choose_req_request[1]) begin
main_sdram_choose_req_grant <= 1'd1;
end else begin
if (main_sdram_choose_req_request[2]) begin
main_sdram_choose_req_grant <= 2'd2;
end else begin
if (main_sdram_choose_req_request[3]) begin
main_sdram_choose_req_grant <= 2'd3;
end else begin
if (main_sdram_choose_req_request[4]) begin
main_sdram_choose_req_grant <= 3'd4;
end else begin
if (main_sdram_choose_req_request[5]) begin
main_sdram_choose_req_grant <= 3'd5;
end
end
end
end
end
end
end
end
3'd7: begin
if (main_sdram_choose_req_request[0]) begin
main_sdram_choose_req_grant <= 1'd0;
end else begin
if (main_sdram_choose_req_request[1]) begin
main_sdram_choose_req_grant <= 1'd1;
end else begin
if (main_sdram_choose_req_request[2]) begin
main_sdram_choose_req_grant <= 2'd2;
end else begin
if (main_sdram_choose_req_request[3]) begin
main_sdram_choose_req_grant <= 2'd3;
end else begin
if (main_sdram_choose_req_request[4]) begin
main_sdram_choose_req_grant <= 3'd4;
end else begin
if (main_sdram_choose_req_request[5]) begin
main_sdram_choose_req_grant <= 3'd5;
end else begin
if (main_sdram_choose_req_request[6]) begin
main_sdram_choose_req_grant <= 3'd6;
end
end
end
end
end
end
end
end
endcase
end
main_sdram_dfi_p0_cs_n <= 1'd0;
main_sdram_dfi_p0_bank <= builder_array_muxed0;
main_sdram_dfi_p0_address <= builder_array_muxed1;
main_sdram_dfi_p0_cas_n <= (~builder_array_muxed2);
main_sdram_dfi_p0_ras_n <= (~builder_array_muxed3);
main_sdram_dfi_p0_we_n <= (~builder_array_muxed4);
main_sdram_dfi_p0_rddata_en <= builder_array_muxed5;
main_sdram_dfi_p0_wrdata_en <= builder_array_muxed6;
main_sdram_dfi_p1_cs_n <= 1'd0;
main_sdram_dfi_p1_bank <= builder_array_muxed7;
main_sdram_dfi_p1_address <= builder_array_muxed8;
main_sdram_dfi_p1_cas_n <= (~builder_array_muxed9);
main_sdram_dfi_p1_ras_n <= (~builder_array_muxed10);
main_sdram_dfi_p1_we_n <= (~builder_array_muxed11);
main_sdram_dfi_p1_rddata_en <= builder_array_muxed12;
main_sdram_dfi_p1_wrdata_en <= builder_array_muxed13;
main_sdram_dfi_p2_cs_n <= 1'd0;
main_sdram_dfi_p2_bank <= builder_array_muxed14;
main_sdram_dfi_p2_address <= builder_array_muxed15;
main_sdram_dfi_p2_cas_n <= (~builder_array_muxed16);
main_sdram_dfi_p2_ras_n <= (~builder_array_muxed17);
main_sdram_dfi_p2_we_n <= (~builder_array_muxed18);
main_sdram_dfi_p2_rddata_en <= builder_array_muxed19;
main_sdram_dfi_p2_wrdata_en <= builder_array_muxed20;
main_sdram_dfi_p3_cs_n <= 1'd0;
main_sdram_dfi_p3_bank <= builder_array_muxed21;
main_sdram_dfi_p3_address <= builder_array_muxed22;
main_sdram_dfi_p3_cas_n <= (~builder_array_muxed23);
main_sdram_dfi_p3_ras_n <= (~builder_array_muxed24);
main_sdram_dfi_p3_we_n <= (~builder_array_muxed25);
main_sdram_dfi_p3_rddata_en <= builder_array_muxed26;
main_sdram_dfi_p3_wrdata_en <= builder_array_muxed27;
if (main_sdram_trrdcon_valid) begin
main_sdram_trrdcon_count <= 1'd1;
if (1'd0) begin
main_sdram_trrdcon_ready <= 1'd1;
end else begin
main_sdram_trrdcon_ready <= 1'd0;
end
end else begin
if ((~main_sdram_trrdcon_ready)) begin
main_sdram_trrdcon_count <= (main_sdram_trrdcon_count - 1'd1);
if ((main_sdram_trrdcon_count == 1'd1)) begin
main_sdram_trrdcon_ready <= 1'd1;
end
end
end
main_sdram_tfawcon_window <= {main_sdram_tfawcon_window, main_sdram_tfawcon_valid};
if ((main_sdram_tfawcon_count < 3'd4)) begin
if ((main_sdram_tfawcon_count == 2'd3)) begin
main_sdram_tfawcon_ready <= (~main_sdram_tfawcon_valid);
end else begin
main_sdram_tfawcon_ready <= 1'd1;
end
end
if (main_sdram_tccdcon_valid) begin
main_sdram_tccdcon_count <= 1'd0;
if (1'd1) begin
main_sdram_tccdcon_ready <= 1'd1;
end else begin
main_sdram_tccdcon_ready <= 1'd0;
end
end else begin
if ((~main_sdram_tccdcon_ready)) begin
main_sdram_tccdcon_count <= (main_sdram_tccdcon_count - 1'd1);
if ((main_sdram_tccdcon_count == 1'd1)) begin
main_sdram_tccdcon_ready <= 1'd1;
end
end
end
if (main_sdram_twtrcon_valid) begin
main_sdram_twtrcon_count <= 3'd4;
if (1'd0) begin
main_sdram_twtrcon_ready <= 1'd1;
end else begin
main_sdram_twtrcon_ready <= 1'd0;
end
end else begin
if ((~main_sdram_twtrcon_ready)) begin
main_sdram_twtrcon_count <= (main_sdram_twtrcon_count - 1'd1);
if ((main_sdram_twtrcon_count == 1'd1)) begin
main_sdram_twtrcon_ready <= 1'd1;
end
end
end
builder_multiplexer_state <= builder_multiplexer_next_state;
if (((builder_roundrobin0_grant == 1'd0) & main_sdram_interface_bank0_rdata_valid)) begin
builder_rbank <= 1'd0;
end
if (((builder_roundrobin0_grant == 1'd0) & main_sdram_interface_bank0_wdata_ready)) begin
builder_wbank <= 1'd0;
end
if (((builder_roundrobin1_grant == 1'd0) & main_sdram_interface_bank1_rdata_valid)) begin
builder_rbank <= 1'd1;
end
if (((builder_roundrobin1_grant == 1'd0) & main_sdram_interface_bank1_wdata_ready)) begin
builder_wbank <= 1'd1;
end
if (((builder_roundrobin2_grant == 1'd0) & main_sdram_interface_bank2_rdata_valid)) begin
builder_rbank <= 2'd2;
end
if (((builder_roundrobin2_grant == 1'd0) & main_sdram_interface_bank2_wdata_ready)) begin
builder_wbank <= 2'd2;
end
if (((builder_roundrobin3_grant == 1'd0) & main_sdram_interface_bank3_rdata_valid)) begin
builder_rbank <= 2'd3;
end
if (((builder_roundrobin3_grant == 1'd0) & main_sdram_interface_bank3_wdata_ready)) begin
builder_wbank <= 2'd3;
end
if (((builder_roundrobin4_grant == 1'd0) & main_sdram_interface_bank4_rdata_valid)) begin
builder_rbank <= 3'd4;
end
if (((builder_roundrobin4_grant == 1'd0) & main_sdram_interface_bank4_wdata_ready)) begin
builder_wbank <= 3'd4;
end
if (((builder_roundrobin5_grant == 1'd0) & main_sdram_interface_bank5_rdata_valid)) begin
builder_rbank <= 3'd5;
end
if (((builder_roundrobin5_grant == 1'd0) & main_sdram_interface_bank5_wdata_ready)) begin
builder_wbank <= 3'd5;
end
if (((builder_roundrobin6_grant == 1'd0) & main_sdram_interface_bank6_rdata_valid)) begin
builder_rbank <= 3'd6;
end
if (((builder_roundrobin6_grant == 1'd0) & main_sdram_interface_bank6_wdata_ready)) begin
builder_wbank <= 3'd6;
end
if (((builder_roundrobin7_grant == 1'd0) & main_sdram_interface_bank7_rdata_valid)) begin
builder_rbank <= 3'd7;
end
if (((builder_roundrobin7_grant == 1'd0) & main_sdram_interface_bank7_wdata_ready)) begin
builder_wbank <= 3'd7;
end
builder_new_master_wdata_ready0 <= ((((((((1'd0 | ((builder_roundrobin0_grant == 1'd0) & main_sdram_interface_bank0_wdata_ready)) | ((builder_roundrobin1_grant == 1'd0) & main_sdram_interface_bank1_wdata_ready)) | ((builder_roundrobin2_grant == 1'd0) & main_sdram_interface_bank2_wdata_ready)) | ((builder_roundrobin3_grant == 1'd0) & main_sdram_interface_bank3_wdata_ready)) | ((builder_roundrobin4_grant == 1'd0) & main_sdram_interface_bank4_wdata_ready)) | ((builder_roundrobin5_grant == 1'd0) & main_sdram_interface_bank5_wdata_ready)) | ((builder_roundrobin6_grant == 1'd0) & main_sdram_interface_bank6_wdata_ready)) | ((builder_roundrobin7_grant == 1'd0) & main_sdram_interface_bank7_wdata_ready));
builder_new_master_wdata_ready1 <= builder_new_master_wdata_ready0;
builder_new_master_wdata_ready2 <= builder_new_master_wdata_ready1;
builder_new_master_rdata_valid0 <= ((((((((1'd0 | ((builder_roundrobin0_grant == 1'd0) & main_sdram_interface_bank0_rdata_valid)) | ((builder_roundrobin1_grant == 1'd0) & main_sdram_interface_bank1_rdata_valid)) | ((builder_roundrobin2_grant == 1'd0) & main_sdram_interface_bank2_rdata_valid)) | ((builder_roundrobin3_grant == 1'd0) & main_sdram_interface_bank3_rdata_valid)) | ((builder_roundrobin4_grant == 1'd0) & main_sdram_interface_bank4_rdata_valid)) | ((builder_roundrobin5_grant == 1'd0) & main_sdram_interface_bank5_rdata_valid)) | ((builder_roundrobin6_grant == 1'd0) & main_sdram_interface_bank6_rdata_valid)) | ((builder_roundrobin7_grant == 1'd0) & main_sdram_interface_bank7_rdata_valid));
builder_new_master_rdata_valid1 <= builder_new_master_rdata_valid0;
builder_new_master_rdata_valid2 <= builder_new_master_rdata_valid1;
builder_new_master_rdata_valid3 <= builder_new_master_rdata_valid2;
builder_new_master_rdata_valid4 <= builder_new_master_rdata_valid3;
builder_new_master_rdata_valid5 <= builder_new_master_rdata_valid4;
builder_new_master_rdata_valid6 <= builder_new_master_rdata_valid5;
builder_new_master_rdata_valid7 <= builder_new_master_rdata_valid6;
builder_new_master_rdata_valid8 <= builder_new_master_rdata_valid7;
builder_new_master_rdata_valid9 <= builder_new_master_rdata_valid8;
main_adr_offset_r <= main_interface0_wb_sdram_adr[1:0];
builder_fullmemorywe_state <= builder_fullmemorywe_next_state;
builder_litedramwishbone2native_state <= builder_litedramwishbone2native_next_state;
case (builder_minsoc_grant)
1'd0: begin
if ((~builder_minsoc_request[0])) begin
if (builder_minsoc_request[1]) begin
builder_minsoc_grant <= 1'd1;
end
end
end
1'd1: begin
if ((~builder_minsoc_request[1])) begin
if (builder_minsoc_request[0]) begin
builder_minsoc_grant <= 1'd0;
end
end
end
endcase
builder_minsoc_slave_sel_r <= builder_minsoc_slave_sel;
if (builder_minsoc_wait) begin
if ((~builder_minsoc_done)) begin
builder_minsoc_count <= (builder_minsoc_count - 1'd1);
end
end else begin
builder_minsoc_count <= 20'd1000000;
end
builder_minsoc_interface0_bank_bus_dat_r <= 1'd0;
if (builder_minsoc_csrbank0_sel) begin
case (builder_minsoc_interface0_bank_bus_adr[3:0])
1'd0: begin
builder_minsoc_interface0_bank_bus_dat_r <= main_ctrl_reset_reset_w;
end
1'd1: begin
builder_minsoc_interface0_bank_bus_dat_r <= builder_minsoc_csrbank0_scratch3_w;
end
2'd2: begin
builder_minsoc_interface0_bank_bus_dat_r <= builder_minsoc_csrbank0_scratch2_w;
end
2'd3: begin
builder_minsoc_interface0_bank_bus_dat_r <= builder_minsoc_csrbank0_scratch1_w;
end
3'd4: begin
builder_minsoc_interface0_bank_bus_dat_r <= builder_minsoc_csrbank0_scratch0_w;
end
3'd5: begin
builder_minsoc_interface0_bank_bus_dat_r <= builder_minsoc_csrbank0_bus_errors3_w;
end
3'd6: begin
builder_minsoc_interface0_bank_bus_dat_r <= builder_minsoc_csrbank0_bus_errors2_w;
end
3'd7: begin
builder_minsoc_interface0_bank_bus_dat_r <= builder_minsoc_csrbank0_bus_errors1_w;
end
4'd8: begin
builder_minsoc_interface0_bank_bus_dat_r <= builder_minsoc_csrbank0_bus_errors0_w;
end
endcase
end
if (builder_minsoc_csrbank0_scratch3_re) begin
main_ctrl_storage[31:24] <= builder_minsoc_csrbank0_scratch3_r;
end
if (builder_minsoc_csrbank0_scratch2_re) begin
main_ctrl_storage[23:16] <= builder_minsoc_csrbank0_scratch2_r;
end
if (builder_minsoc_csrbank0_scratch1_re) begin
main_ctrl_storage[15:8] <= builder_minsoc_csrbank0_scratch1_r;
end
if (builder_minsoc_csrbank0_scratch0_re) begin
main_ctrl_storage[7:0] <= builder_minsoc_csrbank0_scratch0_r;
end
main_ctrl_re <= builder_minsoc_csrbank0_scratch0_re;
builder_minsoc_interface1_bank_bus_dat_r <= 1'd0;
if (builder_minsoc_csrbank1_sel) begin
case (builder_minsoc_interface1_bank_bus_adr[2:0])
1'd0: begin
builder_minsoc_interface1_bank_bus_dat_r <= builder_minsoc_csrbank1_half_sys8x_taps0_w;
end
1'd1: begin
builder_minsoc_interface1_bank_bus_dat_r <= main_a7ddrphy_cdly_rst_w;
end
2'd2: begin
builder_minsoc_interface1_bank_bus_dat_r <= main_a7ddrphy_cdly_inc_w;
end
2'd3: begin
builder_minsoc_interface1_bank_bus_dat_r <= builder_minsoc_csrbank1_dly_sel0_w;
end
3'd4: begin
builder_minsoc_interface1_bank_bus_dat_r <= main_a7ddrphy_rdly_dq_rst_w;
end
3'd5: begin
builder_minsoc_interface1_bank_bus_dat_r <= main_a7ddrphy_rdly_dq_inc_w;
end
3'd6: begin
builder_minsoc_interface1_bank_bus_dat_r <= main_a7ddrphy_rdly_dq_bitslip_rst_w;
end
3'd7: begin
builder_minsoc_interface1_bank_bus_dat_r <= main_a7ddrphy_rdly_dq_bitslip_w;
end
endcase
end
if (builder_minsoc_csrbank1_half_sys8x_taps0_re) begin
main_a7ddrphy_half_sys8x_taps_storage[4:0] <= builder_minsoc_csrbank1_half_sys8x_taps0_r;
end
main_a7ddrphy_half_sys8x_taps_re <= builder_minsoc_csrbank1_half_sys8x_taps0_re;
if (builder_minsoc_csrbank1_dly_sel0_re) begin
main_a7ddrphy_dly_sel_storage[1:0] <= builder_minsoc_csrbank1_dly_sel0_r;
end
main_a7ddrphy_dly_sel_re <= builder_minsoc_csrbank1_dly_sel0_re;
builder_minsoc_interface2_bank_bus_dat_r <= 1'd0;
if (builder_minsoc_csrbank2_sel) begin
case (builder_minsoc_interface2_bank_bus_adr[5:0])
1'd0: begin
builder_minsoc_interface2_bank_bus_dat_r <= builder_minsoc_csrbank2_dfii_control0_w;
end
1'd1: begin
builder_minsoc_interface2_bank_bus_dat_r <= builder_minsoc_csrbank2_dfii_pi0_command0_w;
end
2'd2: begin
builder_minsoc_interface2_bank_bus_dat_r <= main_sdram_phaseinjector0_command_issue_w;
end
2'd3: begin
builder_minsoc_interface2_bank_bus_dat_r <= builder_minsoc_csrbank2_dfii_pi0_address1_w;
end
3'd4: begin
builder_minsoc_interface2_bank_bus_dat_r <= builder_minsoc_csrbank2_dfii_pi0_address0_w;
end
3'd5: begin
builder_minsoc_interface2_bank_bus_dat_r <= builder_minsoc_csrbank2_dfii_pi0_baddress0_w;
end
3'd6: begin
builder_minsoc_interface2_bank_bus_dat_r <= builder_minsoc_csrbank2_dfii_pi0_wrdata3_w;
end
3'd7: begin
builder_minsoc_interface2_bank_bus_dat_r <= builder_minsoc_csrbank2_dfii_pi0_wrdata2_w;
end
4'd8: begin
builder_minsoc_interface2_bank_bus_dat_r <= builder_minsoc_csrbank2_dfii_pi0_wrdata1_w;
end
4'd9: begin
builder_minsoc_interface2_bank_bus_dat_r <= builder_minsoc_csrbank2_dfii_pi0_wrdata0_w;
end
4'd10: begin
builder_minsoc_interface2_bank_bus_dat_r <= builder_minsoc_csrbank2_dfii_pi0_rddata3_w;
end
4'd11: begin
builder_minsoc_interface2_bank_bus_dat_r <= builder_minsoc_csrbank2_dfii_pi0_rddata2_w;
end
4'd12: begin
builder_minsoc_interface2_bank_bus_dat_r <= builder_minsoc_csrbank2_dfii_pi0_rddata1_w;
end
4'd13: begin
builder_minsoc_interface2_bank_bus_dat_r <= builder_minsoc_csrbank2_dfii_pi0_rddata0_w;
end
4'd14: begin
builder_minsoc_interface2_bank_bus_dat_r <= builder_minsoc_csrbank2_dfii_pi1_command0_w;
end
4'd15: begin
builder_minsoc_interface2_bank_bus_dat_r <= main_sdram_phaseinjector1_command_issue_w;
end
5'd16: begin
builder_minsoc_interface2_bank_bus_dat_r <= builder_minsoc_csrbank2_dfii_pi1_address1_w;
end
5'd17: begin
builder_minsoc_interface2_bank_bus_dat_r <= builder_minsoc_csrbank2_dfii_pi1_address0_w;
end
5'd18: begin
builder_minsoc_interface2_bank_bus_dat_r <= builder_minsoc_csrbank2_dfii_pi1_baddress0_w;
end
5'd19: begin
builder_minsoc_interface2_bank_bus_dat_r <= builder_minsoc_csrbank2_dfii_pi1_wrdata3_w;
end
5'd20: begin
builder_minsoc_interface2_bank_bus_dat_r <= builder_minsoc_csrbank2_dfii_pi1_wrdata2_w;
end
5'd21: begin
builder_minsoc_interface2_bank_bus_dat_r <= builder_minsoc_csrbank2_dfii_pi1_wrdata1_w;
end
5'd22: begin
builder_minsoc_interface2_bank_bus_dat_r <= builder_minsoc_csrbank2_dfii_pi1_wrdata0_w;
end
5'd23: begin
builder_minsoc_interface2_bank_bus_dat_r <= builder_minsoc_csrbank2_dfii_pi1_rddata3_w;
end
5'd24: begin
builder_minsoc_interface2_bank_bus_dat_r <= builder_minsoc_csrbank2_dfii_pi1_rddata2_w;
end
5'd25: begin
builder_minsoc_interface2_bank_bus_dat_r <= builder_minsoc_csrbank2_dfii_pi1_rddata1_w;
end
5'd26: begin
builder_minsoc_interface2_bank_bus_dat_r <= builder_minsoc_csrbank2_dfii_pi1_rddata0_w;
end
5'd27: begin
builder_minsoc_interface2_bank_bus_dat_r <= builder_minsoc_csrbank2_dfii_pi2_command0_w;
end
5'd28: begin
builder_minsoc_interface2_bank_bus_dat_r <= main_sdram_phaseinjector2_command_issue_w;
end
5'd29: begin
builder_minsoc_interface2_bank_bus_dat_r <= builder_minsoc_csrbank2_dfii_pi2_address1_w;
end
5'd30: begin
builder_minsoc_interface2_bank_bus_dat_r <= builder_minsoc_csrbank2_dfii_pi2_address0_w;
end
5'd31: begin
builder_minsoc_interface2_bank_bus_dat_r <= builder_minsoc_csrbank2_dfii_pi2_baddress0_w;
end
6'd32: begin
builder_minsoc_interface2_bank_bus_dat_r <= builder_minsoc_csrbank2_dfii_pi2_wrdata3_w;
end
6'd33: begin
builder_minsoc_interface2_bank_bus_dat_r <= builder_minsoc_csrbank2_dfii_pi2_wrdata2_w;
end
6'd34: begin
builder_minsoc_interface2_bank_bus_dat_r <= builder_minsoc_csrbank2_dfii_pi2_wrdata1_w;
end
6'd35: begin
builder_minsoc_interface2_bank_bus_dat_r <= builder_minsoc_csrbank2_dfii_pi2_wrdata0_w;
end
6'd36: begin
builder_minsoc_interface2_bank_bus_dat_r <= builder_minsoc_csrbank2_dfii_pi2_rddata3_w;
end
6'd37: begin
builder_minsoc_interface2_bank_bus_dat_r <= builder_minsoc_csrbank2_dfii_pi2_rddata2_w;
end
6'd38: begin
builder_minsoc_interface2_bank_bus_dat_r <= builder_minsoc_csrbank2_dfii_pi2_rddata1_w;
end
6'd39: begin
builder_minsoc_interface2_bank_bus_dat_r <= builder_minsoc_csrbank2_dfii_pi2_rddata0_w;
end
6'd40: begin
builder_minsoc_interface2_bank_bus_dat_r <= builder_minsoc_csrbank2_dfii_pi3_command0_w;
end
6'd41: begin
builder_minsoc_interface2_bank_bus_dat_r <= main_sdram_phaseinjector3_command_issue_w;
end
6'd42: begin
builder_minsoc_interface2_bank_bus_dat_r <= builder_minsoc_csrbank2_dfii_pi3_address1_w;
end
6'd43: begin
builder_minsoc_interface2_bank_bus_dat_r <= builder_minsoc_csrbank2_dfii_pi3_address0_w;
end
6'd44: begin
builder_minsoc_interface2_bank_bus_dat_r <= builder_minsoc_csrbank2_dfii_pi3_baddress0_w;
end
6'd45: begin
builder_minsoc_interface2_bank_bus_dat_r <= builder_minsoc_csrbank2_dfii_pi3_wrdata3_w;
end
6'd46: begin
builder_minsoc_interface2_bank_bus_dat_r <= builder_minsoc_csrbank2_dfii_pi3_wrdata2_w;
end
6'd47: begin
builder_minsoc_interface2_bank_bus_dat_r <= builder_minsoc_csrbank2_dfii_pi3_wrdata1_w;
end
6'd48: begin
builder_minsoc_interface2_bank_bus_dat_r <= builder_minsoc_csrbank2_dfii_pi3_wrdata0_w;
end
6'd49: begin
builder_minsoc_interface2_bank_bus_dat_r <= builder_minsoc_csrbank2_dfii_pi3_rddata3_w;
end
6'd50: begin
builder_minsoc_interface2_bank_bus_dat_r <= builder_minsoc_csrbank2_dfii_pi3_rddata2_w;
end
6'd51: begin
builder_minsoc_interface2_bank_bus_dat_r <= builder_minsoc_csrbank2_dfii_pi3_rddata1_w;
end
6'd52: begin
builder_minsoc_interface2_bank_bus_dat_r <= builder_minsoc_csrbank2_dfii_pi3_rddata0_w;
end
endcase
end
if (builder_minsoc_csrbank2_dfii_control0_re) begin
main_sdram_storage[3:0] <= builder_minsoc_csrbank2_dfii_control0_r;
end
main_sdram_re <= builder_minsoc_csrbank2_dfii_control0_re;
if (builder_minsoc_csrbank2_dfii_pi0_command0_re) begin
main_sdram_phaseinjector0_command_storage[5:0] <= builder_minsoc_csrbank2_dfii_pi0_command0_r;
end
main_sdram_phaseinjector0_command_re <= builder_minsoc_csrbank2_dfii_pi0_command0_re;
if (builder_minsoc_csrbank2_dfii_pi0_address1_re) begin
main_sdram_phaseinjector0_address_storage[13:8] <= builder_minsoc_csrbank2_dfii_pi0_address1_r;
end
if (builder_minsoc_csrbank2_dfii_pi0_address0_re) begin
main_sdram_phaseinjector0_address_storage[7:0] <= builder_minsoc_csrbank2_dfii_pi0_address0_r;
end
main_sdram_phaseinjector0_address_re <= builder_minsoc_csrbank2_dfii_pi0_address0_re;
if (builder_minsoc_csrbank2_dfii_pi0_baddress0_re) begin
main_sdram_phaseinjector0_baddress_storage[2:0] <= builder_minsoc_csrbank2_dfii_pi0_baddress0_r;
end
main_sdram_phaseinjector0_baddress_re <= builder_minsoc_csrbank2_dfii_pi0_baddress0_re;
if (builder_minsoc_csrbank2_dfii_pi0_wrdata3_re) begin
main_sdram_phaseinjector0_wrdata_storage[31:24] <= builder_minsoc_csrbank2_dfii_pi0_wrdata3_r;
end
if (builder_minsoc_csrbank2_dfii_pi0_wrdata2_re) begin
main_sdram_phaseinjector0_wrdata_storage[23:16] <= builder_minsoc_csrbank2_dfii_pi0_wrdata2_r;
end
if (builder_minsoc_csrbank2_dfii_pi0_wrdata1_re) begin
main_sdram_phaseinjector0_wrdata_storage[15:8] <= builder_minsoc_csrbank2_dfii_pi0_wrdata1_r;
end
if (builder_minsoc_csrbank2_dfii_pi0_wrdata0_re) begin
main_sdram_phaseinjector0_wrdata_storage[7:0] <= builder_minsoc_csrbank2_dfii_pi0_wrdata0_r;
end
main_sdram_phaseinjector0_wrdata_re <= builder_minsoc_csrbank2_dfii_pi0_wrdata0_re;
if (builder_minsoc_csrbank2_dfii_pi1_command0_re) begin
main_sdram_phaseinjector1_command_storage[5:0] <= builder_minsoc_csrbank2_dfii_pi1_command0_r;
end
main_sdram_phaseinjector1_command_re <= builder_minsoc_csrbank2_dfii_pi1_command0_re;
if (builder_minsoc_csrbank2_dfii_pi1_address1_re) begin
main_sdram_phaseinjector1_address_storage[13:8] <= builder_minsoc_csrbank2_dfii_pi1_address1_r;
end
if (builder_minsoc_csrbank2_dfii_pi1_address0_re) begin
main_sdram_phaseinjector1_address_storage[7:0] <= builder_minsoc_csrbank2_dfii_pi1_address0_r;
end
main_sdram_phaseinjector1_address_re <= builder_minsoc_csrbank2_dfii_pi1_address0_re;
if (builder_minsoc_csrbank2_dfii_pi1_baddress0_re) begin
main_sdram_phaseinjector1_baddress_storage[2:0] <= builder_minsoc_csrbank2_dfii_pi1_baddress0_r;
end
main_sdram_phaseinjector1_baddress_re <= builder_minsoc_csrbank2_dfii_pi1_baddress0_re;
if (builder_minsoc_csrbank2_dfii_pi1_wrdata3_re) begin
main_sdram_phaseinjector1_wrdata_storage[31:24] <= builder_minsoc_csrbank2_dfii_pi1_wrdata3_r;
end
if (builder_minsoc_csrbank2_dfii_pi1_wrdata2_re) begin
main_sdram_phaseinjector1_wrdata_storage[23:16] <= builder_minsoc_csrbank2_dfii_pi1_wrdata2_r;
end
if (builder_minsoc_csrbank2_dfii_pi1_wrdata1_re) begin
main_sdram_phaseinjector1_wrdata_storage[15:8] <= builder_minsoc_csrbank2_dfii_pi1_wrdata1_r;
end
if (builder_minsoc_csrbank2_dfii_pi1_wrdata0_re) begin
main_sdram_phaseinjector1_wrdata_storage[7:0] <= builder_minsoc_csrbank2_dfii_pi1_wrdata0_r;
end
main_sdram_phaseinjector1_wrdata_re <= builder_minsoc_csrbank2_dfii_pi1_wrdata0_re;
if (builder_minsoc_csrbank2_dfii_pi2_command0_re) begin
main_sdram_phaseinjector2_command_storage[5:0] <= builder_minsoc_csrbank2_dfii_pi2_command0_r;
end
main_sdram_phaseinjector2_command_re <= builder_minsoc_csrbank2_dfii_pi2_command0_re;
if (builder_minsoc_csrbank2_dfii_pi2_address1_re) begin
main_sdram_phaseinjector2_address_storage[13:8] <= builder_minsoc_csrbank2_dfii_pi2_address1_r;
end
if (builder_minsoc_csrbank2_dfii_pi2_address0_re) begin
main_sdram_phaseinjector2_address_storage[7:0] <= builder_minsoc_csrbank2_dfii_pi2_address0_r;
end
main_sdram_phaseinjector2_address_re <= builder_minsoc_csrbank2_dfii_pi2_address0_re;
if (builder_minsoc_csrbank2_dfii_pi2_baddress0_re) begin
main_sdram_phaseinjector2_baddress_storage[2:0] <= builder_minsoc_csrbank2_dfii_pi2_baddress0_r;
end
main_sdram_phaseinjector2_baddress_re <= builder_minsoc_csrbank2_dfii_pi2_baddress0_re;
if (builder_minsoc_csrbank2_dfii_pi2_wrdata3_re) begin
main_sdram_phaseinjector2_wrdata_storage[31:24] <= builder_minsoc_csrbank2_dfii_pi2_wrdata3_r;
end
if (builder_minsoc_csrbank2_dfii_pi2_wrdata2_re) begin
main_sdram_phaseinjector2_wrdata_storage[23:16] <= builder_minsoc_csrbank2_dfii_pi2_wrdata2_r;
end
if (builder_minsoc_csrbank2_dfii_pi2_wrdata1_re) begin
main_sdram_phaseinjector2_wrdata_storage[15:8] <= builder_minsoc_csrbank2_dfii_pi2_wrdata1_r;
end
if (builder_minsoc_csrbank2_dfii_pi2_wrdata0_re) begin
main_sdram_phaseinjector2_wrdata_storage[7:0] <= builder_minsoc_csrbank2_dfii_pi2_wrdata0_r;
end
main_sdram_phaseinjector2_wrdata_re <= builder_minsoc_csrbank2_dfii_pi2_wrdata0_re;
if (builder_minsoc_csrbank2_dfii_pi3_command0_re) begin
main_sdram_phaseinjector3_command_storage[5:0] <= builder_minsoc_csrbank2_dfii_pi3_command0_r;
end
main_sdram_phaseinjector3_command_re <= builder_minsoc_csrbank2_dfii_pi3_command0_re;
if (builder_minsoc_csrbank2_dfii_pi3_address1_re) begin
main_sdram_phaseinjector3_address_storage[13:8] <= builder_minsoc_csrbank2_dfii_pi3_address1_r;
end
if (builder_minsoc_csrbank2_dfii_pi3_address0_re) begin
main_sdram_phaseinjector3_address_storage[7:0] <= builder_minsoc_csrbank2_dfii_pi3_address0_r;
end
main_sdram_phaseinjector3_address_re <= builder_minsoc_csrbank2_dfii_pi3_address0_re;
if (builder_minsoc_csrbank2_dfii_pi3_baddress0_re) begin
main_sdram_phaseinjector3_baddress_storage[2:0] <= builder_minsoc_csrbank2_dfii_pi3_baddress0_r;
end
main_sdram_phaseinjector3_baddress_re <= builder_minsoc_csrbank2_dfii_pi3_baddress0_re;
if (builder_minsoc_csrbank2_dfii_pi3_wrdata3_re) begin
main_sdram_phaseinjector3_wrdata_storage[31:24] <= builder_minsoc_csrbank2_dfii_pi3_wrdata3_r;
end
if (builder_minsoc_csrbank2_dfii_pi3_wrdata2_re) begin
main_sdram_phaseinjector3_wrdata_storage[23:16] <= builder_minsoc_csrbank2_dfii_pi3_wrdata2_r;
end
if (builder_minsoc_csrbank2_dfii_pi3_wrdata1_re) begin
main_sdram_phaseinjector3_wrdata_storage[15:8] <= builder_minsoc_csrbank2_dfii_pi3_wrdata1_r;
end
if (builder_minsoc_csrbank2_dfii_pi3_wrdata0_re) begin
main_sdram_phaseinjector3_wrdata_storage[7:0] <= builder_minsoc_csrbank2_dfii_pi3_wrdata0_r;
end
main_sdram_phaseinjector3_wrdata_re <= builder_minsoc_csrbank2_dfii_pi3_wrdata0_re;
builder_minsoc_interface3_bank_bus_dat_r <= 1'd0;
if (builder_minsoc_csrbank3_sel) begin
case (builder_minsoc_interface3_bank_bus_adr[4:0])
1'd0: begin
builder_minsoc_interface3_bank_bus_dat_r <= builder_minsoc_csrbank3_load3_w;
end
1'd1: begin
builder_minsoc_interface3_bank_bus_dat_r <= builder_minsoc_csrbank3_load2_w;
end
2'd2: begin
builder_minsoc_interface3_bank_bus_dat_r <= builder_minsoc_csrbank3_load1_w;
end
2'd3: begin
builder_minsoc_interface3_bank_bus_dat_r <= builder_minsoc_csrbank3_load0_w;
end
3'd4: begin
builder_minsoc_interface3_bank_bus_dat_r <= builder_minsoc_csrbank3_reload3_w;
end
3'd5: begin
builder_minsoc_interface3_bank_bus_dat_r <= builder_minsoc_csrbank3_reload2_w;
end
3'd6: begin
builder_minsoc_interface3_bank_bus_dat_r <= builder_minsoc_csrbank3_reload1_w;
end
3'd7: begin
builder_minsoc_interface3_bank_bus_dat_r <= builder_minsoc_csrbank3_reload0_w;
end
4'd8: begin
builder_minsoc_interface3_bank_bus_dat_r <= builder_minsoc_csrbank3_en0_w;
end
4'd9: begin
builder_minsoc_interface3_bank_bus_dat_r <= builder_minsoc_csrbank3_update_value0_w;
end
4'd10: begin
builder_minsoc_interface3_bank_bus_dat_r <= builder_minsoc_csrbank3_value3_w;
end
4'd11: begin
builder_minsoc_interface3_bank_bus_dat_r <= builder_minsoc_csrbank3_value2_w;
end
4'd12: begin
builder_minsoc_interface3_bank_bus_dat_r <= builder_minsoc_csrbank3_value1_w;
end
4'd13: begin
builder_minsoc_interface3_bank_bus_dat_r <= builder_minsoc_csrbank3_value0_w;
end
4'd14: begin
builder_minsoc_interface3_bank_bus_dat_r <= main_timer0_eventmanager_status_w;
end
4'd15: begin
builder_minsoc_interface3_bank_bus_dat_r <= main_timer0_eventmanager_pending_w;
end
5'd16: begin
builder_minsoc_interface3_bank_bus_dat_r <= builder_minsoc_csrbank3_ev_enable0_w;
end
endcase
end
if (builder_minsoc_csrbank3_load3_re) begin
main_timer0_load_storage[31:24] <= builder_minsoc_csrbank3_load3_r;
end
if (builder_minsoc_csrbank3_load2_re) begin
main_timer0_load_storage[23:16] <= builder_minsoc_csrbank3_load2_r;
end
if (builder_minsoc_csrbank3_load1_re) begin
main_timer0_load_storage[15:8] <= builder_minsoc_csrbank3_load1_r;
end
if (builder_minsoc_csrbank3_load0_re) begin
main_timer0_load_storage[7:0] <= builder_minsoc_csrbank3_load0_r;
end
main_timer0_load_re <= builder_minsoc_csrbank3_load0_re;
if (builder_minsoc_csrbank3_reload3_re) begin
main_timer0_reload_storage[31:24] <= builder_minsoc_csrbank3_reload3_r;
end
if (builder_minsoc_csrbank3_reload2_re) begin
main_timer0_reload_storage[23:16] <= builder_minsoc_csrbank3_reload2_r;
end
if (builder_minsoc_csrbank3_reload1_re) begin
main_timer0_reload_storage[15:8] <= builder_minsoc_csrbank3_reload1_r;
end
if (builder_minsoc_csrbank3_reload0_re) begin
main_timer0_reload_storage[7:0] <= builder_minsoc_csrbank3_reload0_r;
end
main_timer0_reload_re <= builder_minsoc_csrbank3_reload0_re;
if (builder_minsoc_csrbank3_en0_re) begin
main_timer0_en_storage <= builder_minsoc_csrbank3_en0_r;
end
main_timer0_en_re <= builder_minsoc_csrbank3_en0_re;
if (builder_minsoc_csrbank3_update_value0_re) begin
main_timer0_update_value_storage <= builder_minsoc_csrbank3_update_value0_r;
end
main_timer0_update_value_re <= builder_minsoc_csrbank3_update_value0_re;
if (builder_minsoc_csrbank3_ev_enable0_re) begin
main_timer0_eventmanager_storage <= builder_minsoc_csrbank3_ev_enable0_r;
end
main_timer0_eventmanager_re <= builder_minsoc_csrbank3_ev_enable0_re;
builder_minsoc_interface4_bank_bus_dat_r <= 1'd0;
if (builder_minsoc_csrbank4_sel) begin
case (builder_minsoc_interface4_bank_bus_adr[2:0])
1'd0: begin
builder_minsoc_interface4_bank_bus_dat_r <= main_uart_rxtx_w;
end
1'd1: begin
builder_minsoc_interface4_bank_bus_dat_r <= builder_minsoc_csrbank4_txfull_w;
end
2'd2: begin
builder_minsoc_interface4_bank_bus_dat_r <= builder_minsoc_csrbank4_rxempty_w;
end
2'd3: begin
builder_minsoc_interface4_bank_bus_dat_r <= main_uart_eventmanager_status_w;
end
3'd4: begin
builder_minsoc_interface4_bank_bus_dat_r <= main_uart_eventmanager_pending_w;
end
3'd5: begin
builder_minsoc_interface4_bank_bus_dat_r <= builder_minsoc_csrbank4_ev_enable0_w;
end
endcase
end
if (builder_minsoc_csrbank4_ev_enable0_re) begin
main_uart_eventmanager_storage[1:0] <= builder_minsoc_csrbank4_ev_enable0_r;
end
main_uart_eventmanager_re <= builder_minsoc_csrbank4_ev_enable0_re;
builder_minsoc_interface5_bank_bus_dat_r <= 1'd0;
if (builder_minsoc_csrbank5_sel) begin
case (builder_minsoc_interface5_bank_bus_adr[1:0])
1'd0: begin
builder_minsoc_interface5_bank_bus_dat_r <= builder_minsoc_csrbank5_tuning_word3_w;
end
1'd1: begin
builder_minsoc_interface5_bank_bus_dat_r <= builder_minsoc_csrbank5_tuning_word2_w;
end
2'd2: begin
builder_minsoc_interface5_bank_bus_dat_r <= builder_minsoc_csrbank5_tuning_word1_w;
end
2'd3: begin
builder_minsoc_interface5_bank_bus_dat_r <= builder_minsoc_csrbank5_tuning_word0_w;
end
endcase
end
if (builder_minsoc_csrbank5_tuning_word3_re) begin
main_uart_phy_storage[31:24] <= builder_minsoc_csrbank5_tuning_word3_r;
end
if (builder_minsoc_csrbank5_tuning_word2_re) begin
main_uart_phy_storage[23:16] <= builder_minsoc_csrbank5_tuning_word2_r;
end
if (builder_minsoc_csrbank5_tuning_word1_re) begin
main_uart_phy_storage[15:8] <= builder_minsoc_csrbank5_tuning_word1_r;
end
if (builder_minsoc_csrbank5_tuning_word0_re) begin
main_uart_phy_storage[7:0] <= builder_minsoc_csrbank5_tuning_word0_r;
end
main_uart_phy_re <= builder_minsoc_csrbank5_tuning_word0_re;
if (sys_rst) begin
main_ctrl_storage <= 32'd305419896;
main_ctrl_re <= 1'd0;
main_ctrl_bus_errors <= 32'd0;
main_rom_bus_ack <= 1'd0;
main_sram_bus_ack <= 1'd0;
serial_tx <= 1'd1;
main_uart_phy_storage <= 32'd9895604;
main_uart_phy_re <= 1'd0;
main_uart_phy_sink_ready <= 1'd0;
main_uart_phy_uart_clk_txen <= 1'd0;
main_uart_phy_phase_accumulator_tx <= 32'd0;
main_uart_phy_tx_reg <= 8'd0;
main_uart_phy_tx_bitcount <= 4'd0;
main_uart_phy_tx_busy <= 1'd0;
main_uart_phy_source_valid <= 1'd0;
main_uart_phy_source_payload_data <= 8'd0;
main_uart_phy_uart_clk_rxen <= 1'd0;
main_uart_phy_phase_accumulator_rx <= 32'd0;
main_uart_phy_rx_r <= 1'd0;
main_uart_phy_rx_reg <= 8'd0;
main_uart_phy_rx_bitcount <= 4'd0;
main_uart_phy_rx_busy <= 1'd0;
main_uart_tx_pending <= 1'd0;
main_uart_tx_old_trigger <= 1'd0;
main_uart_rx_pending <= 1'd0;
main_uart_rx_old_trigger <= 1'd0;
main_uart_eventmanager_storage <= 2'd0;
main_uart_eventmanager_re <= 1'd0;
main_uart_tx_fifo_readable <= 1'd0;
main_uart_tx_fifo_level0 <= 5'd0;
main_uart_tx_fifo_produce <= 4'd0;
main_uart_tx_fifo_consume <= 4'd0;
main_uart_rx_fifo_readable <= 1'd0;
main_uart_rx_fifo_level0 <= 5'd0;
main_uart_rx_fifo_produce <= 4'd0;
main_uart_rx_fifo_consume <= 4'd0;
main_timer0_load_storage <= 32'd0;
main_timer0_load_re <= 1'd0;
main_timer0_reload_storage <= 32'd0;
main_timer0_reload_re <= 1'd0;
main_timer0_en_storage <= 1'd0;
main_timer0_en_re <= 1'd0;
main_timer0_update_value_storage <= 1'd0;
main_timer0_update_value_re <= 1'd0;
main_timer0_value_status <= 32'd0;
main_timer0_zero_pending <= 1'd0;
main_timer0_zero_old_trigger <= 1'd0;
main_timer0_eventmanager_storage <= 1'd0;
main_timer0_eventmanager_re <= 1'd0;
main_timer0_value <= 32'd0;
main_a7ddrphy_half_sys8x_taps_storage <= 5'd16;
main_a7ddrphy_half_sys8x_taps_re <= 1'd0;
main_a7ddrphy_dly_sel_storage <= 2'd0;
main_a7ddrphy_dly_sel_re <= 1'd0;
main_a7ddrphy_dfi_p0_rddata_valid <= 1'd0;
main_a7ddrphy_dfi_p1_rddata_valid <= 1'd0;
main_a7ddrphy_dfi_p2_rddata_valid <= 1'd0;
main_a7ddrphy_dfi_p3_rddata_valid <= 1'd0;
main_a7ddrphy_oe_dqs <= 1'd0;
main_a7ddrphy_oe_dq <= 1'd0;
main_a7ddrphy_bitslip0_o <= 8'd0;
main_a7ddrphy_bitslip0_value <= 3'd0;
main_a7ddrphy_bitslip0_r <= 16'd0;
main_a7ddrphy_bitslip1_o <= 8'd0;
main_a7ddrphy_bitslip1_value <= 3'd0;
main_a7ddrphy_bitslip1_r <= 16'd0;
main_a7ddrphy_bitslip2_o <= 8'd0;
main_a7ddrphy_bitslip2_value <= 3'd0;
main_a7ddrphy_bitslip2_r <= 16'd0;
main_a7ddrphy_bitslip3_o <= 8'd0;
main_a7ddrphy_bitslip3_value <= 3'd0;
main_a7ddrphy_bitslip3_r <= 16'd0;
main_a7ddrphy_bitslip4_o <= 8'd0;
main_a7ddrphy_bitslip4_value <= 3'd0;
main_a7ddrphy_bitslip4_r <= 16'd0;
main_a7ddrphy_bitslip5_o <= 8'd0;
main_a7ddrphy_bitslip5_value <= 3'd0;
main_a7ddrphy_bitslip5_r <= 16'd0;
main_a7ddrphy_bitslip6_o <= 8'd0;
main_a7ddrphy_bitslip6_value <= 3'd0;
main_a7ddrphy_bitslip6_r <= 16'd0;
main_a7ddrphy_bitslip7_o <= 8'd0;
main_a7ddrphy_bitslip7_value <= 3'd0;
main_a7ddrphy_bitslip7_r <= 16'd0;
main_a7ddrphy_bitslip8_o <= 8'd0;
main_a7ddrphy_bitslip8_value <= 3'd0;
main_a7ddrphy_bitslip8_r <= 16'd0;
main_a7ddrphy_bitslip9_o <= 8'd0;
main_a7ddrphy_bitslip9_value <= 3'd0;
main_a7ddrphy_bitslip9_r <= 16'd0;
main_a7ddrphy_bitslip10_o <= 8'd0;
main_a7ddrphy_bitslip10_value <= 3'd0;
main_a7ddrphy_bitslip10_r <= 16'd0;
main_a7ddrphy_bitslip11_o <= 8'd0;
main_a7ddrphy_bitslip11_value <= 3'd0;
main_a7ddrphy_bitslip11_r <= 16'd0;
main_a7ddrphy_bitslip12_o <= 8'd0;
main_a7ddrphy_bitslip12_value <= 3'd0;
main_a7ddrphy_bitslip12_r <= 16'd0;
main_a7ddrphy_bitslip13_o <= 8'd0;
main_a7ddrphy_bitslip13_value <= 3'd0;
main_a7ddrphy_bitslip13_r <= 16'd0;
main_a7ddrphy_bitslip14_o <= 8'd0;
main_a7ddrphy_bitslip14_value <= 3'd0;
main_a7ddrphy_bitslip14_r <= 16'd0;
main_a7ddrphy_bitslip15_o <= 8'd0;
main_a7ddrphy_bitslip15_value <= 3'd0;
main_a7ddrphy_bitslip15_r <= 16'd0;
main_a7ddrphy_n_rddata_en0 <= 1'd0;
main_a7ddrphy_n_rddata_en1 <= 1'd0;
main_a7ddrphy_n_rddata_en2 <= 1'd0;
main_a7ddrphy_n_rddata_en3 <= 1'd0;
main_a7ddrphy_n_rddata_en4 <= 1'd0;
main_a7ddrphy_n_rddata_en5 <= 1'd0;
main_a7ddrphy_n_rddata_en6 <= 1'd0;
main_a7ddrphy_n_rddata_en7 <= 1'd0;
main_a7ddrphy_last_wrdata_en <= 4'd0;
main_sdram_storage <= 4'd0;
main_sdram_re <= 1'd0;
main_sdram_phaseinjector0_command_storage <= 6'd0;
main_sdram_phaseinjector0_command_re <= 1'd0;
main_sdram_phaseinjector0_address_storage <= 14'd0;
main_sdram_phaseinjector0_address_re <= 1'd0;
main_sdram_phaseinjector0_baddress_storage <= 3'd0;
main_sdram_phaseinjector0_baddress_re <= 1'd0;
main_sdram_phaseinjector0_wrdata_storage <= 32'd0;
main_sdram_phaseinjector0_wrdata_re <= 1'd0;
main_sdram_phaseinjector0_status <= 32'd0;
main_sdram_phaseinjector1_command_storage <= 6'd0;
main_sdram_phaseinjector1_command_re <= 1'd0;
main_sdram_phaseinjector1_address_storage <= 14'd0;
main_sdram_phaseinjector1_address_re <= 1'd0;
main_sdram_phaseinjector1_baddress_storage <= 3'd0;
main_sdram_phaseinjector1_baddress_re <= 1'd0;
main_sdram_phaseinjector1_wrdata_storage <= 32'd0;
main_sdram_phaseinjector1_wrdata_re <= 1'd0;
main_sdram_phaseinjector1_status <= 32'd0;
main_sdram_phaseinjector2_command_storage <= 6'd0;
main_sdram_phaseinjector2_command_re <= 1'd0;
main_sdram_phaseinjector2_address_storage <= 14'd0;
main_sdram_phaseinjector2_address_re <= 1'd0;
main_sdram_phaseinjector2_baddress_storage <= 3'd0;
main_sdram_phaseinjector2_baddress_re <= 1'd0;
main_sdram_phaseinjector2_wrdata_storage <= 32'd0;
main_sdram_phaseinjector2_wrdata_re <= 1'd0;
main_sdram_phaseinjector2_status <= 32'd0;
main_sdram_phaseinjector3_command_storage <= 6'd0;
main_sdram_phaseinjector3_command_re <= 1'd0;
main_sdram_phaseinjector3_address_storage <= 14'd0;
main_sdram_phaseinjector3_address_re <= 1'd0;
main_sdram_phaseinjector3_baddress_storage <= 3'd0;
main_sdram_phaseinjector3_baddress_re <= 1'd0;
main_sdram_phaseinjector3_wrdata_storage <= 32'd0;
main_sdram_phaseinjector3_wrdata_re <= 1'd0;
main_sdram_phaseinjector3_status <= 32'd0;
main_sdram_dfi_p0_address <= 14'd0;
main_sdram_dfi_p0_bank <= 3'd0;
main_sdram_dfi_p0_cas_n <= 1'd1;
main_sdram_dfi_p0_cs_n <= 1'd1;
main_sdram_dfi_p0_ras_n <= 1'd1;
main_sdram_dfi_p0_we_n <= 1'd1;
main_sdram_dfi_p0_wrdata_en <= 1'd0;
main_sdram_dfi_p0_rddata_en <= 1'd0;
main_sdram_dfi_p1_address <= 14'd0;
main_sdram_dfi_p1_bank <= 3'd0;
main_sdram_dfi_p1_cas_n <= 1'd1;
main_sdram_dfi_p1_cs_n <= 1'd1;
main_sdram_dfi_p1_ras_n <= 1'd1;
main_sdram_dfi_p1_we_n <= 1'd1;
main_sdram_dfi_p1_wrdata_en <= 1'd0;
main_sdram_dfi_p1_rddata_en <= 1'd0;
main_sdram_dfi_p2_address <= 14'd0;
main_sdram_dfi_p2_bank <= 3'd0;
main_sdram_dfi_p2_cas_n <= 1'd1;
main_sdram_dfi_p2_cs_n <= 1'd1;
main_sdram_dfi_p2_ras_n <= 1'd1;
main_sdram_dfi_p2_we_n <= 1'd1;
main_sdram_dfi_p2_wrdata_en <= 1'd0;
main_sdram_dfi_p2_rddata_en <= 1'd0;
main_sdram_dfi_p3_address <= 14'd0;
main_sdram_dfi_p3_bank <= 3'd0;
main_sdram_dfi_p3_cas_n <= 1'd1;
main_sdram_dfi_p3_cs_n <= 1'd1;
main_sdram_dfi_p3_ras_n <= 1'd1;
main_sdram_dfi_p3_we_n <= 1'd1;
main_sdram_dfi_p3_wrdata_en <= 1'd0;
main_sdram_dfi_p3_rddata_en <= 1'd0;
main_sdram_cmd_payload_a <= 14'd0;
main_sdram_cmd_payload_ba <= 3'd0;
main_sdram_cmd_payload_cas <= 1'd0;
main_sdram_cmd_payload_ras <= 1'd0;
main_sdram_cmd_payload_we <= 1'd0;
main_sdram_timer_count1 <= 9'd390;
main_sdram_postponer_req_o <= 1'd0;
main_sdram_postponer_count <= 1'd0;
main_sdram_sequencer_done1 <= 1'd0;
main_sdram_sequencer_counter <= 6'd0;
main_sdram_sequencer_count <= 1'd0;
main_sdram_zqcs_timer_count1 <= 26'd49999999;
main_sdram_zqcs_executer_done <= 1'd0;
main_sdram_zqcs_executer_counter <= 5'd0;
main_sdram_bankmachine0_cmd_buffer_lookahead_level <= 4'd0;
main_sdram_bankmachine0_cmd_buffer_lookahead_produce <= 3'd0;
main_sdram_bankmachine0_cmd_buffer_lookahead_consume <= 3'd0;
main_sdram_bankmachine0_cmd_buffer_source_payload_we <= 1'd0;
main_sdram_bankmachine0_cmd_buffer_source_payload_addr <= 21'd0;
main_sdram_bankmachine0_cmd_buffer_valid_n <= 1'd0;
main_sdram_bankmachine0_cmd_buffer_first_n <= 1'd0;
main_sdram_bankmachine0_cmd_buffer_last_n <= 1'd0;
main_sdram_bankmachine0_row <= 14'd0;
main_sdram_bankmachine0_row_opened <= 1'd0;
main_sdram_bankmachine0_twtpcon_ready <= 1'd1;
main_sdram_bankmachine0_twtpcon_count <= 3'd0;
main_sdram_bankmachine0_trccon_ready <= 1'd1;
main_sdram_bankmachine0_trccon_count <= 2'd0;
main_sdram_bankmachine0_trascon_ready <= 1'd1;
main_sdram_bankmachine0_trascon_count <= 2'd0;
main_sdram_bankmachine1_cmd_buffer_lookahead_level <= 4'd0;
main_sdram_bankmachine1_cmd_buffer_lookahead_produce <= 3'd0;
main_sdram_bankmachine1_cmd_buffer_lookahead_consume <= 3'd0;
main_sdram_bankmachine1_cmd_buffer_source_payload_we <= 1'd0;
main_sdram_bankmachine1_cmd_buffer_source_payload_addr <= 21'd0;
main_sdram_bankmachine1_cmd_buffer_valid_n <= 1'd0;
main_sdram_bankmachine1_cmd_buffer_first_n <= 1'd0;
main_sdram_bankmachine1_cmd_buffer_last_n <= 1'd0;
main_sdram_bankmachine1_row <= 14'd0;
main_sdram_bankmachine1_row_opened <= 1'd0;
main_sdram_bankmachine1_twtpcon_ready <= 1'd1;
main_sdram_bankmachine1_twtpcon_count <= 3'd0;
main_sdram_bankmachine1_trccon_ready <= 1'd1;
main_sdram_bankmachine1_trccon_count <= 2'd0;
main_sdram_bankmachine1_trascon_ready <= 1'd1;
main_sdram_bankmachine1_trascon_count <= 2'd0;
main_sdram_bankmachine2_cmd_buffer_lookahead_level <= 4'd0;
main_sdram_bankmachine2_cmd_buffer_lookahead_produce <= 3'd0;
main_sdram_bankmachine2_cmd_buffer_lookahead_consume <= 3'd0;
main_sdram_bankmachine2_cmd_buffer_source_payload_we <= 1'd0;
main_sdram_bankmachine2_cmd_buffer_source_payload_addr <= 21'd0;
main_sdram_bankmachine2_cmd_buffer_valid_n <= 1'd0;
main_sdram_bankmachine2_cmd_buffer_first_n <= 1'd0;
main_sdram_bankmachine2_cmd_buffer_last_n <= 1'd0;
main_sdram_bankmachine2_row <= 14'd0;
main_sdram_bankmachine2_row_opened <= 1'd0;
main_sdram_bankmachine2_twtpcon_ready <= 1'd1;
main_sdram_bankmachine2_twtpcon_count <= 3'd0;
main_sdram_bankmachine2_trccon_ready <= 1'd1;
main_sdram_bankmachine2_trccon_count <= 2'd0;
main_sdram_bankmachine2_trascon_ready <= 1'd1;
main_sdram_bankmachine2_trascon_count <= 2'd0;
main_sdram_bankmachine3_cmd_buffer_lookahead_level <= 4'd0;
main_sdram_bankmachine3_cmd_buffer_lookahead_produce <= 3'd0;
main_sdram_bankmachine3_cmd_buffer_lookahead_consume <= 3'd0;
main_sdram_bankmachine3_cmd_buffer_source_payload_we <= 1'd0;
main_sdram_bankmachine3_cmd_buffer_source_payload_addr <= 21'd0;
main_sdram_bankmachine3_cmd_buffer_valid_n <= 1'd0;
main_sdram_bankmachine3_cmd_buffer_first_n <= 1'd0;
main_sdram_bankmachine3_cmd_buffer_last_n <= 1'd0;
main_sdram_bankmachine3_row <= 14'd0;
main_sdram_bankmachine3_row_opened <= 1'd0;
main_sdram_bankmachine3_twtpcon_ready <= 1'd1;
main_sdram_bankmachine3_twtpcon_count <= 3'd0;
main_sdram_bankmachine3_trccon_ready <= 1'd1;
main_sdram_bankmachine3_trccon_count <= 2'd0;
main_sdram_bankmachine3_trascon_ready <= 1'd1;
main_sdram_bankmachine3_trascon_count <= 2'd0;
main_sdram_bankmachine4_cmd_buffer_lookahead_level <= 4'd0;
main_sdram_bankmachine4_cmd_buffer_lookahead_produce <= 3'd0;
main_sdram_bankmachine4_cmd_buffer_lookahead_consume <= 3'd0;
main_sdram_bankmachine4_cmd_buffer_source_payload_we <= 1'd0;
main_sdram_bankmachine4_cmd_buffer_source_payload_addr <= 21'd0;
main_sdram_bankmachine4_cmd_buffer_valid_n <= 1'd0;
main_sdram_bankmachine4_cmd_buffer_first_n <= 1'd0;
main_sdram_bankmachine4_cmd_buffer_last_n <= 1'd0;
main_sdram_bankmachine4_row <= 14'd0;
main_sdram_bankmachine4_row_opened <= 1'd0;
main_sdram_bankmachine4_twtpcon_ready <= 1'd1;
main_sdram_bankmachine4_twtpcon_count <= 3'd0;
main_sdram_bankmachine4_trccon_ready <= 1'd1;
main_sdram_bankmachine4_trccon_count <= 2'd0;
main_sdram_bankmachine4_trascon_ready <= 1'd1;
main_sdram_bankmachine4_trascon_count <= 2'd0;
main_sdram_bankmachine5_cmd_buffer_lookahead_level <= 4'd0;
main_sdram_bankmachine5_cmd_buffer_lookahead_produce <= 3'd0;
main_sdram_bankmachine5_cmd_buffer_lookahead_consume <= 3'd0;
main_sdram_bankmachine5_cmd_buffer_source_payload_we <= 1'd0;
main_sdram_bankmachine5_cmd_buffer_source_payload_addr <= 21'd0;
main_sdram_bankmachine5_cmd_buffer_valid_n <= 1'd0;
main_sdram_bankmachine5_cmd_buffer_first_n <= 1'd0;
main_sdram_bankmachine5_cmd_buffer_last_n <= 1'd0;
main_sdram_bankmachine5_row <= 14'd0;
main_sdram_bankmachine5_row_opened <= 1'd0;
main_sdram_bankmachine5_twtpcon_ready <= 1'd1;
main_sdram_bankmachine5_twtpcon_count <= 3'd0;
main_sdram_bankmachine5_trccon_ready <= 1'd1;
main_sdram_bankmachine5_trccon_count <= 2'd0;
main_sdram_bankmachine5_trascon_ready <= 1'd1;
main_sdram_bankmachine5_trascon_count <= 2'd0;
main_sdram_bankmachine6_cmd_buffer_lookahead_level <= 4'd0;
main_sdram_bankmachine6_cmd_buffer_lookahead_produce <= 3'd0;
main_sdram_bankmachine6_cmd_buffer_lookahead_consume <= 3'd0;
main_sdram_bankmachine6_cmd_buffer_source_payload_we <= 1'd0;
main_sdram_bankmachine6_cmd_buffer_source_payload_addr <= 21'd0;
main_sdram_bankmachine6_cmd_buffer_valid_n <= 1'd0;
main_sdram_bankmachine6_cmd_buffer_first_n <= 1'd0;
main_sdram_bankmachine6_cmd_buffer_last_n <= 1'd0;
main_sdram_bankmachine6_row <= 14'd0;
main_sdram_bankmachine6_row_opened <= 1'd0;
main_sdram_bankmachine6_twtpcon_ready <= 1'd1;
main_sdram_bankmachine6_twtpcon_count <= 3'd0;
main_sdram_bankmachine6_trccon_ready <= 1'd1;
main_sdram_bankmachine6_trccon_count <= 2'd0;
main_sdram_bankmachine6_trascon_ready <= 1'd1;
main_sdram_bankmachine6_trascon_count <= 2'd0;
main_sdram_bankmachine7_cmd_buffer_lookahead_level <= 4'd0;
main_sdram_bankmachine7_cmd_buffer_lookahead_produce <= 3'd0;
main_sdram_bankmachine7_cmd_buffer_lookahead_consume <= 3'd0;
main_sdram_bankmachine7_cmd_buffer_source_payload_we <= 1'd0;
main_sdram_bankmachine7_cmd_buffer_source_payload_addr <= 21'd0;
main_sdram_bankmachine7_cmd_buffer_valid_n <= 1'd0;
main_sdram_bankmachine7_cmd_buffer_first_n <= 1'd0;
main_sdram_bankmachine7_cmd_buffer_last_n <= 1'd0;
main_sdram_bankmachine7_row <= 14'd0;
main_sdram_bankmachine7_row_opened <= 1'd0;
main_sdram_bankmachine7_twtpcon_ready <= 1'd1;
main_sdram_bankmachine7_twtpcon_count <= 3'd0;
main_sdram_bankmachine7_trccon_ready <= 1'd1;
main_sdram_bankmachine7_trccon_count <= 2'd0;
main_sdram_bankmachine7_trascon_ready <= 1'd1;
main_sdram_bankmachine7_trascon_count <= 2'd0;
main_sdram_choose_cmd_grant <= 3'd0;
main_sdram_choose_req_grant <= 3'd0;
main_sdram_trrdcon_ready <= 1'd1;
main_sdram_trrdcon_count <= 1'd0;
main_sdram_tfawcon_ready <= 1'd1;
main_sdram_tfawcon_window <= 3'd0;
main_sdram_tccdcon_ready <= 1'd1;
main_sdram_tccdcon_count <= 1'd0;
main_sdram_twtrcon_ready <= 1'd1;
main_sdram_twtrcon_count <= 3'd0;
main_sdram_time0 <= 5'd0;
main_sdram_time1 <= 4'd0;
main_adr_offset_r <= 2'd0;
builder_wb2csr_state <= 1'd0;
builder_refresher_state <= 2'd0;
builder_bankmachine0_state <= 3'd0;
builder_bankmachine1_state <= 3'd0;
builder_bankmachine2_state <= 3'd0;
builder_bankmachine3_state <= 3'd0;
builder_bankmachine4_state <= 3'd0;
builder_bankmachine5_state <= 3'd0;
builder_bankmachine6_state <= 3'd0;
builder_bankmachine7_state <= 3'd0;
builder_multiplexer_state <= 4'd0;
builder_rbank <= 3'd0;
builder_wbank <= 3'd0;
builder_new_master_wdata_ready0 <= 1'd0;
builder_new_master_wdata_ready1 <= 1'd0;
builder_new_master_wdata_ready2 <= 1'd0;
builder_new_master_rdata_valid0 <= 1'd0;
builder_new_master_rdata_valid1 <= 1'd0;
builder_new_master_rdata_valid2 <= 1'd0;
builder_new_master_rdata_valid3 <= 1'd0;
builder_new_master_rdata_valid4 <= 1'd0;
builder_new_master_rdata_valid5 <= 1'd0;
builder_new_master_rdata_valid6 <= 1'd0;
builder_new_master_rdata_valid7 <= 1'd0;
builder_new_master_rdata_valid8 <= 1'd0;
builder_new_master_rdata_valid9 <= 1'd0;
builder_fullmemorywe_state <= 3'd0;
builder_litedramwishbone2native_state <= 2'd0;
builder_minsoc_grant <= 1'd0;
builder_minsoc_slave_sel_r <= 4'd0;
builder_minsoc_count <= 20'd1000000;
builder_minsoc_interface0_bank_bus_dat_r <= 8'd0;
builder_minsoc_interface1_bank_bus_dat_r <= 8'd0;
builder_minsoc_interface2_bank_bus_dat_r <= 8'd0;
builder_minsoc_interface3_bank_bus_dat_r <= 8'd0;
builder_minsoc_interface4_bank_bus_dat_r <= 8'd0;
builder_minsoc_interface5_bank_bus_dat_r <= 8'd0;
end
builder_regs0 <= serial_rx;
builder_regs1 <= builder_regs0;
end
reg [31:0] mem[0:8191];
reg [31:0] memdat;
always @(posedge sys_clk) begin
memdat <= mem[main_rom_adr];
end
assign main_rom_dat_r = memdat;
initial begin
$readmemh("mem.init", mem);
end
reg [31:0] mem_1[0:8191];
reg [12:0] memadr;
always @(posedge sys_clk) begin
if (main_sram_we[0])
mem_1[main_sram_adr][7:0] <= main_sram_dat_w[7:0];
if (main_sram_we[1])
mem_1[main_sram_adr][15:8] <= main_sram_dat_w[15:8];
if (main_sram_we[2])
mem_1[main_sram_adr][23:16] <= main_sram_dat_w[23:16];
if (main_sram_we[3])
mem_1[main_sram_adr][31:24] <= main_sram_dat_w[31:24];
memadr <= main_sram_adr;
end
assign main_sram_dat_r = mem_1[memadr];
initial begin
$readmemh("mem_1.init", mem_1);
end
reg [9:0] storage[0:15];
reg [9:0] memdat_1;
reg [9:0] memdat_2;
always @(posedge sys_clk) begin
if (main_uart_tx_fifo_wrport_we)
storage[main_uart_tx_fifo_wrport_adr] <= main_uart_tx_fifo_wrport_dat_w;
memdat_1 <= storage[main_uart_tx_fifo_wrport_adr];
end
always @(posedge sys_clk) begin
if (main_uart_tx_fifo_rdport_re)
memdat_2 <= storage[main_uart_tx_fifo_rdport_adr];
end
assign main_uart_tx_fifo_wrport_dat_r = memdat_1;
assign main_uart_tx_fifo_rdport_dat_r = memdat_2;
reg [9:0] storage_1[0:15];
reg [9:0] memdat_3;
reg [9:0] memdat_4;
always @(posedge sys_clk) begin
if (main_uart_rx_fifo_wrport_we)
storage_1[main_uart_rx_fifo_wrport_adr] <= main_uart_rx_fifo_wrport_dat_w;
memdat_3 <= storage_1[main_uart_rx_fifo_wrport_adr];
end
always @(posedge sys_clk) begin
if (main_uart_rx_fifo_rdport_re)
memdat_4 <= storage_1[main_uart_rx_fifo_rdport_adr];
end
assign main_uart_rx_fifo_wrport_dat_r = memdat_3;
assign main_uart_rx_fifo_rdport_dat_r = memdat_4;
BUFG BUFG(
.I(clk100),
.O(main_pll_clkin)
);
BUFG BUFG_1(
.I(main_clkout0),
.O(main_clkout_buf0)
);
BUFG BUFG_2(
.I(main_clkout1),
.O(main_clkout_buf1)
);
BUFG BUFG_3(
.I(main_clkout2),
.O(main_clkout_buf2)
);
BUFG BUFG_4(
.I(main_clkout3),
.O(main_clkout_buf3)
);
IDELAYCTRL IDELAYCTRL(
.REFCLK(clk200_clk),
.RST(main_ic_reset)
);
OSERDESE2 #(
.DATA_RATE_OQ("DDR"),
.DATA_RATE_TQ("BUF"),
.DATA_WIDTH(4'd8),
.SERDES_MODE("MASTER"),
.TRISTATE_WIDTH(1'd1)
) OSERDESE2 (
.CLK(sys4x_clk),
.CLKDIV(sys_clk),
.D1(1'd0),
.D2(1'd1),
.D3(1'd0),
.D4(1'd1),
.D5(1'd0),
.D6(1'd1),
.D7(1'd0),
.D8(1'd1),
.OCE(1'd1),
.RST(sys_rst),
.OQ(main_a7ddrphy_sd_clk_se_nodelay)
);
OBUFDS OBUFDS(
.I(main_a7ddrphy_sd_clk_se_nodelay),
.O(ddram_clk_p),
.OB(ddram_clk_n)
);
OSERDESE2 #(
.DATA_RATE_OQ("DDR"),
.DATA_RATE_TQ("BUF"),
.DATA_WIDTH(4'd8),
.SERDES_MODE("MASTER"),
.TRISTATE_WIDTH(1'd1)
) OSERDESE2_1 (
.CLK(sys4x_clk),
.CLKDIV(sys_clk),
.D1(main_a7ddrphy_dfi_p0_address[0]),
.D2(main_a7ddrphy_dfi_p0_address[0]),
.D3(main_a7ddrphy_dfi_p1_address[0]),
.D4(main_a7ddrphy_dfi_p1_address[0]),
.D5(main_a7ddrphy_dfi_p2_address[0]),
.D6(main_a7ddrphy_dfi_p2_address[0]),
.D7(main_a7ddrphy_dfi_p3_address[0]),
.D8(main_a7ddrphy_dfi_p3_address[0]),
.OCE(1'd1),
.RST(sys_rst),
.OQ(ddram_a[0])
);
OSERDESE2 #(
.DATA_RATE_OQ("DDR"),
.DATA_RATE_TQ("BUF"),
.DATA_WIDTH(4'd8),
.SERDES_MODE("MASTER"),
.TRISTATE_WIDTH(1'd1)
) OSERDESE2_2 (
.CLK(sys4x_clk),
.CLKDIV(sys_clk),
.D1(main_a7ddrphy_dfi_p0_address[1]),
.D2(main_a7ddrphy_dfi_p0_address[1]),
.D3(main_a7ddrphy_dfi_p1_address[1]),
.D4(main_a7ddrphy_dfi_p1_address[1]),
.D5(main_a7ddrphy_dfi_p2_address[1]),
.D6(main_a7ddrphy_dfi_p2_address[1]),
.D7(main_a7ddrphy_dfi_p3_address[1]),
.D8(main_a7ddrphy_dfi_p3_address[1]),
.OCE(1'd1),
.RST(sys_rst),
.OQ(ddram_a[1])
);
OSERDESE2 #(
.DATA_RATE_OQ("DDR"),
.DATA_RATE_TQ("BUF"),
.DATA_WIDTH(4'd8),
.SERDES_MODE("MASTER"),
.TRISTATE_WIDTH(1'd1)
) OSERDESE2_3 (
.CLK(sys4x_clk),
.CLKDIV(sys_clk),
.D1(main_a7ddrphy_dfi_p0_address[2]),
.D2(main_a7ddrphy_dfi_p0_address[2]),
.D3(main_a7ddrphy_dfi_p1_address[2]),
.D4(main_a7ddrphy_dfi_p1_address[2]),
.D5(main_a7ddrphy_dfi_p2_address[2]),
.D6(main_a7ddrphy_dfi_p2_address[2]),
.D7(main_a7ddrphy_dfi_p3_address[2]),
.D8(main_a7ddrphy_dfi_p3_address[2]),
.OCE(1'd1),
.RST(sys_rst),
.OQ(ddram_a[2])
);
OSERDESE2 #(
.DATA_RATE_OQ("DDR"),
.DATA_RATE_TQ("BUF"),
.DATA_WIDTH(4'd8),
.SERDES_MODE("MASTER"),
.TRISTATE_WIDTH(1'd1)
) OSERDESE2_4 (
.CLK(sys4x_clk),
.CLKDIV(sys_clk),
.D1(main_a7ddrphy_dfi_p0_address[3]),
.D2(main_a7ddrphy_dfi_p0_address[3]),
.D3(main_a7ddrphy_dfi_p1_address[3]),
.D4(main_a7ddrphy_dfi_p1_address[3]),
.D5(main_a7ddrphy_dfi_p2_address[3]),
.D6(main_a7ddrphy_dfi_p2_address[3]),
.D7(main_a7ddrphy_dfi_p3_address[3]),
.D8(main_a7ddrphy_dfi_p3_address[3]),
.OCE(1'd1),
.RST(sys_rst),
.OQ(ddram_a[3])
);
OSERDESE2 #(
.DATA_RATE_OQ("DDR"),
.DATA_RATE_TQ("BUF"),
.DATA_WIDTH(4'd8),
.SERDES_MODE("MASTER"),
.TRISTATE_WIDTH(1'd1)
) OSERDESE2_5 (
.CLK(sys4x_clk),
.CLKDIV(sys_clk),
.D1(main_a7ddrphy_dfi_p0_address[4]),
.D2(main_a7ddrphy_dfi_p0_address[4]),
.D3(main_a7ddrphy_dfi_p1_address[4]),
.D4(main_a7ddrphy_dfi_p1_address[4]),
.D5(main_a7ddrphy_dfi_p2_address[4]),
.D6(main_a7ddrphy_dfi_p2_address[4]),
.D7(main_a7ddrphy_dfi_p3_address[4]),
.D8(main_a7ddrphy_dfi_p3_address[4]),
.OCE(1'd1),
.RST(sys_rst),
.OQ(ddram_a[4])
);
OSERDESE2 #(
.DATA_RATE_OQ("DDR"),
.DATA_RATE_TQ("BUF"),
.DATA_WIDTH(4'd8),
.SERDES_MODE("MASTER"),
.TRISTATE_WIDTH(1'd1)
) OSERDESE2_6 (
.CLK(sys4x_clk),
.CLKDIV(sys_clk),
.D1(main_a7ddrphy_dfi_p0_address[5]),
.D2(main_a7ddrphy_dfi_p0_address[5]),
.D3(main_a7ddrphy_dfi_p1_address[5]),
.D4(main_a7ddrphy_dfi_p1_address[5]),
.D5(main_a7ddrphy_dfi_p2_address[5]),
.D6(main_a7ddrphy_dfi_p2_address[5]),
.D7(main_a7ddrphy_dfi_p3_address[5]),
.D8(main_a7ddrphy_dfi_p3_address[5]),
.OCE(1'd1),
.RST(sys_rst),
.OQ(ddram_a[5])
);
OSERDESE2 #(
.DATA_RATE_OQ("DDR"),
.DATA_RATE_TQ("BUF"),
.DATA_WIDTH(4'd8),
.SERDES_MODE("MASTER"),
.TRISTATE_WIDTH(1'd1)
) OSERDESE2_7 (
.CLK(sys4x_clk),
.CLKDIV(sys_clk),
.D1(main_a7ddrphy_dfi_p0_address[6]),
.D2(main_a7ddrphy_dfi_p0_address[6]),
.D3(main_a7ddrphy_dfi_p1_address[6]),
.D4(main_a7ddrphy_dfi_p1_address[6]),
.D5(main_a7ddrphy_dfi_p2_address[6]),
.D6(main_a7ddrphy_dfi_p2_address[6]),
.D7(main_a7ddrphy_dfi_p3_address[6]),
.D8(main_a7ddrphy_dfi_p3_address[6]),
.OCE(1'd1),
.RST(sys_rst),
.OQ(ddram_a[6])
);
OSERDESE2 #(
.DATA_RATE_OQ("DDR"),
.DATA_RATE_TQ("BUF"),
.DATA_WIDTH(4'd8),
.SERDES_MODE("MASTER"),
.TRISTATE_WIDTH(1'd1)
) OSERDESE2_8 (
.CLK(sys4x_clk),
.CLKDIV(sys_clk),
.D1(main_a7ddrphy_dfi_p0_address[7]),
.D2(main_a7ddrphy_dfi_p0_address[7]),
.D3(main_a7ddrphy_dfi_p1_address[7]),
.D4(main_a7ddrphy_dfi_p1_address[7]),
.D5(main_a7ddrphy_dfi_p2_address[7]),
.D6(main_a7ddrphy_dfi_p2_address[7]),
.D7(main_a7ddrphy_dfi_p3_address[7]),
.D8(main_a7ddrphy_dfi_p3_address[7]),
.OCE(1'd1),
.RST(sys_rst),
.OQ(ddram_a[7])
);
OSERDESE2 #(
.DATA_RATE_OQ("DDR"),
.DATA_RATE_TQ("BUF"),
.DATA_WIDTH(4'd8),
.SERDES_MODE("MASTER"),
.TRISTATE_WIDTH(1'd1)
) OSERDESE2_9 (
.CLK(sys4x_clk),
.CLKDIV(sys_clk),
.D1(main_a7ddrphy_dfi_p0_address[8]),
.D2(main_a7ddrphy_dfi_p0_address[8]),
.D3(main_a7ddrphy_dfi_p1_address[8]),
.D4(main_a7ddrphy_dfi_p1_address[8]),
.D5(main_a7ddrphy_dfi_p2_address[8]),
.D6(main_a7ddrphy_dfi_p2_address[8]),
.D7(main_a7ddrphy_dfi_p3_address[8]),
.D8(main_a7ddrphy_dfi_p3_address[8]),
.OCE(1'd1),
.RST(sys_rst),
.OQ(ddram_a[8])
);
OSERDESE2 #(
.DATA_RATE_OQ("DDR"),
.DATA_RATE_TQ("BUF"),
.DATA_WIDTH(4'd8),
.SERDES_MODE("MASTER"),
.TRISTATE_WIDTH(1'd1)
) OSERDESE2_10 (
.CLK(sys4x_clk),
.CLKDIV(sys_clk),
.D1(main_a7ddrphy_dfi_p0_address[9]),
.D2(main_a7ddrphy_dfi_p0_address[9]),
.D3(main_a7ddrphy_dfi_p1_address[9]),
.D4(main_a7ddrphy_dfi_p1_address[9]),
.D5(main_a7ddrphy_dfi_p2_address[9]),
.D6(main_a7ddrphy_dfi_p2_address[9]),
.D7(main_a7ddrphy_dfi_p3_address[9]),
.D8(main_a7ddrphy_dfi_p3_address[9]),
.OCE(1'd1),
.RST(sys_rst),
.OQ(ddram_a[9])
);
OSERDESE2 #(
.DATA_RATE_OQ("DDR"),
.DATA_RATE_TQ("BUF"),
.DATA_WIDTH(4'd8),
.SERDES_MODE("MASTER"),
.TRISTATE_WIDTH(1'd1)
) OSERDESE2_11 (
.CLK(sys4x_clk),
.CLKDIV(sys_clk),
.D1(main_a7ddrphy_dfi_p0_address[10]),
.D2(main_a7ddrphy_dfi_p0_address[10]),
.D3(main_a7ddrphy_dfi_p1_address[10]),
.D4(main_a7ddrphy_dfi_p1_address[10]),
.D5(main_a7ddrphy_dfi_p2_address[10]),
.D6(main_a7ddrphy_dfi_p2_address[10]),
.D7(main_a7ddrphy_dfi_p3_address[10]),
.D8(main_a7ddrphy_dfi_p3_address[10]),
.OCE(1'd1),
.RST(sys_rst),
.OQ(ddram_a[10])
);
OSERDESE2 #(
.DATA_RATE_OQ("DDR"),
.DATA_RATE_TQ("BUF"),
.DATA_WIDTH(4'd8),
.SERDES_MODE("MASTER"),
.TRISTATE_WIDTH(1'd1)
) OSERDESE2_12 (
.CLK(sys4x_clk),
.CLKDIV(sys_clk),
.D1(main_a7ddrphy_dfi_p0_address[11]),
.D2(main_a7ddrphy_dfi_p0_address[11]),
.D3(main_a7ddrphy_dfi_p1_address[11]),
.D4(main_a7ddrphy_dfi_p1_address[11]),
.D5(main_a7ddrphy_dfi_p2_address[11]),
.D6(main_a7ddrphy_dfi_p2_address[11]),
.D7(main_a7ddrphy_dfi_p3_address[11]),
.D8(main_a7ddrphy_dfi_p3_address[11]),
.OCE(1'd1),
.RST(sys_rst),
.OQ(ddram_a[11])
);
OSERDESE2 #(
.DATA_RATE_OQ("DDR"),
.DATA_RATE_TQ("BUF"),
.DATA_WIDTH(4'd8),
.SERDES_MODE("MASTER"),
.TRISTATE_WIDTH(1'd1)
) OSERDESE2_13 (
.CLK(sys4x_clk),
.CLKDIV(sys_clk),
.D1(main_a7ddrphy_dfi_p0_address[12]),
.D2(main_a7ddrphy_dfi_p0_address[12]),
.D3(main_a7ddrphy_dfi_p1_address[12]),
.D4(main_a7ddrphy_dfi_p1_address[12]),
.D5(main_a7ddrphy_dfi_p2_address[12]),
.D6(main_a7ddrphy_dfi_p2_address[12]),
.D7(main_a7ddrphy_dfi_p3_address[12]),
.D8(main_a7ddrphy_dfi_p3_address[12]),
.OCE(1'd1),
.RST(sys_rst),
.OQ(ddram_a[12])
);
OSERDESE2 #(
.DATA_RATE_OQ("DDR"),
.DATA_RATE_TQ("BUF"),
.DATA_WIDTH(4'd8),
.SERDES_MODE("MASTER"),
.TRISTATE_WIDTH(1'd1)
) OSERDESE2_14 (
.CLK(sys4x_clk),
.CLKDIV(sys_clk),
.D1(main_a7ddrphy_dfi_p0_address[13]),
.D2(main_a7ddrphy_dfi_p0_address[13]),
.D3(main_a7ddrphy_dfi_p1_address[13]),
.D4(main_a7ddrphy_dfi_p1_address[13]),
.D5(main_a7ddrphy_dfi_p2_address[13]),
.D6(main_a7ddrphy_dfi_p2_address[13]),
.D7(main_a7ddrphy_dfi_p3_address[13]),
.D8(main_a7ddrphy_dfi_p3_address[13]),
.OCE(1'd1),
.RST(sys_rst),
.OQ(ddram_a[13])
);
OSERDESE2 #(
.DATA_RATE_OQ("DDR"),
.DATA_RATE_TQ("BUF"),
.DATA_WIDTH(4'd8),
.SERDES_MODE("MASTER"),
.TRISTATE_WIDTH(1'd1)
) OSERDESE2_15 (
.CLK(sys4x_clk),
.CLKDIV(sys_clk),
.D1(main_a7ddrphy_dfi_p0_bank[0]),
.D2(main_a7ddrphy_dfi_p0_bank[0]),
.D3(main_a7ddrphy_dfi_p1_bank[0]),
.D4(main_a7ddrphy_dfi_p1_bank[0]),
.D5(main_a7ddrphy_dfi_p2_bank[0]),
.D6(main_a7ddrphy_dfi_p2_bank[0]),
.D7(main_a7ddrphy_dfi_p3_bank[0]),
.D8(main_a7ddrphy_dfi_p3_bank[0]),
.OCE(1'd1),
.RST(sys_rst),
.OQ(ddram_ba[0])
);
OSERDESE2 #(
.DATA_RATE_OQ("DDR"),
.DATA_RATE_TQ("BUF"),
.DATA_WIDTH(4'd8),
.SERDES_MODE("MASTER"),
.TRISTATE_WIDTH(1'd1)
) OSERDESE2_16 (
.CLK(sys4x_clk),
.CLKDIV(sys_clk),
.D1(main_a7ddrphy_dfi_p0_bank[1]),
.D2(main_a7ddrphy_dfi_p0_bank[1]),
.D3(main_a7ddrphy_dfi_p1_bank[1]),
.D4(main_a7ddrphy_dfi_p1_bank[1]),
.D5(main_a7ddrphy_dfi_p2_bank[1]),
.D6(main_a7ddrphy_dfi_p2_bank[1]),
.D7(main_a7ddrphy_dfi_p3_bank[1]),
.D8(main_a7ddrphy_dfi_p3_bank[1]),
.OCE(1'd1),
.RST(sys_rst),
.OQ(ddram_ba[1])
);
OSERDESE2 #(
.DATA_RATE_OQ("DDR"),
.DATA_RATE_TQ("BUF"),
.DATA_WIDTH(4'd8),
.SERDES_MODE("MASTER"),
.TRISTATE_WIDTH(1'd1)
) OSERDESE2_17 (
.CLK(sys4x_clk),
.CLKDIV(sys_clk),
.D1(main_a7ddrphy_dfi_p0_bank[2]),
.D2(main_a7ddrphy_dfi_p0_bank[2]),
.D3(main_a7ddrphy_dfi_p1_bank[2]),
.D4(main_a7ddrphy_dfi_p1_bank[2]),
.D5(main_a7ddrphy_dfi_p2_bank[2]),
.D6(main_a7ddrphy_dfi_p2_bank[2]),
.D7(main_a7ddrphy_dfi_p3_bank[2]),
.D8(main_a7ddrphy_dfi_p3_bank[2]),
.OCE(1'd1),
.RST(sys_rst),
.OQ(ddram_ba[2])
);
OSERDESE2 #(
.DATA_RATE_OQ("DDR"),
.DATA_RATE_TQ("BUF"),
.DATA_WIDTH(4'd8),
.SERDES_MODE("MASTER"),
.TRISTATE_WIDTH(1'd1)
) OSERDESE2_18 (
.CLK(sys4x_clk),
.CLKDIV(sys_clk),
.D1(main_a7ddrphy_dfi_p0_ras_n),
.D2(main_a7ddrphy_dfi_p0_ras_n),
.D3(main_a7ddrphy_dfi_p1_ras_n),
.D4(main_a7ddrphy_dfi_p1_ras_n),
.D5(main_a7ddrphy_dfi_p2_ras_n),
.D6(main_a7ddrphy_dfi_p2_ras_n),
.D7(main_a7ddrphy_dfi_p3_ras_n),
.D8(main_a7ddrphy_dfi_p3_ras_n),
.OCE(1'd1),
.RST(sys_rst),
.OQ(ddram_ras_n)
);
OSERDESE2 #(
.DATA_RATE_OQ("DDR"),
.DATA_RATE_TQ("BUF"),
.DATA_WIDTH(4'd8),
.SERDES_MODE("MASTER"),
.TRISTATE_WIDTH(1'd1)
) OSERDESE2_19 (
.CLK(sys4x_clk),
.CLKDIV(sys_clk),
.D1(main_a7ddrphy_dfi_p0_cas_n),
.D2(main_a7ddrphy_dfi_p0_cas_n),
.D3(main_a7ddrphy_dfi_p1_cas_n),
.D4(main_a7ddrphy_dfi_p1_cas_n),
.D5(main_a7ddrphy_dfi_p2_cas_n),
.D6(main_a7ddrphy_dfi_p2_cas_n),
.D7(main_a7ddrphy_dfi_p3_cas_n),
.D8(main_a7ddrphy_dfi_p3_cas_n),
.OCE(1'd1),
.RST(sys_rst),
.OQ(ddram_cas_n)
);
OSERDESE2 #(
.DATA_RATE_OQ("DDR"),
.DATA_RATE_TQ("BUF"),
.DATA_WIDTH(4'd8),
.SERDES_MODE("MASTER"),
.TRISTATE_WIDTH(1'd1)
) OSERDESE2_20 (
.CLK(sys4x_clk),
.CLKDIV(sys_clk),
.D1(main_a7ddrphy_dfi_p0_we_n),
.D2(main_a7ddrphy_dfi_p0_we_n),
.D3(main_a7ddrphy_dfi_p1_we_n),
.D4(main_a7ddrphy_dfi_p1_we_n),
.D5(main_a7ddrphy_dfi_p2_we_n),
.D6(main_a7ddrphy_dfi_p2_we_n),
.D7(main_a7ddrphy_dfi_p3_we_n),
.D8(main_a7ddrphy_dfi_p3_we_n),
.OCE(1'd1),
.RST(sys_rst),
.OQ(ddram_we_n)
);
OSERDESE2 #(
.DATA_RATE_OQ("DDR"),
.DATA_RATE_TQ("BUF"),
.DATA_WIDTH(4'd8),
.SERDES_MODE("MASTER"),
.TRISTATE_WIDTH(1'd1)
) OSERDESE2_21 (
.CLK(sys4x_clk),
.CLKDIV(sys_clk),
.D1(main_a7ddrphy_dfi_p0_cke),
.D2(main_a7ddrphy_dfi_p0_cke),
.D3(main_a7ddrphy_dfi_p1_cke),
.D4(main_a7ddrphy_dfi_p1_cke),
.D5(main_a7ddrphy_dfi_p2_cke),
.D6(main_a7ddrphy_dfi_p2_cke),
.D7(main_a7ddrphy_dfi_p3_cke),
.D8(main_a7ddrphy_dfi_p3_cke),
.OCE(1'd1),
.RST(sys_rst),
.OQ(ddram_cke)
);
OSERDESE2 #(
.DATA_RATE_OQ("DDR"),
.DATA_RATE_TQ("BUF"),
.DATA_WIDTH(4'd8),
.SERDES_MODE("MASTER"),
.TRISTATE_WIDTH(1'd1)
) OSERDESE2_22 (
.CLK(sys4x_clk),
.CLKDIV(sys_clk),
.D1(main_a7ddrphy_dfi_p0_odt),
.D2(main_a7ddrphy_dfi_p0_odt),
.D3(main_a7ddrphy_dfi_p1_odt),
.D4(main_a7ddrphy_dfi_p1_odt),
.D5(main_a7ddrphy_dfi_p2_odt),
.D6(main_a7ddrphy_dfi_p2_odt),
.D7(main_a7ddrphy_dfi_p3_odt),
.D8(main_a7ddrphy_dfi_p3_odt),
.OCE(1'd1),
.RST(sys_rst),
.OQ(ddram_odt)
);
OSERDESE2 #(
.DATA_RATE_OQ("DDR"),
.DATA_RATE_TQ("BUF"),
.DATA_WIDTH(4'd8),
.SERDES_MODE("MASTER"),
.TRISTATE_WIDTH(1'd1)
) OSERDESE2_23 (
.CLK(sys4x_clk),
.CLKDIV(sys_clk),
.D1(main_a7ddrphy_dfi_p0_reset_n),
.D2(main_a7ddrphy_dfi_p0_reset_n),
.D3(main_a7ddrphy_dfi_p1_reset_n),
.D4(main_a7ddrphy_dfi_p1_reset_n),
.D5(main_a7ddrphy_dfi_p2_reset_n),
.D6(main_a7ddrphy_dfi_p2_reset_n),
.D7(main_a7ddrphy_dfi_p3_reset_n),
.D8(main_a7ddrphy_dfi_p3_reset_n),
.OCE(1'd1),
.RST(sys_rst),
.OQ(ddram_reset_n)
);
OSERDESE2 #(
.DATA_RATE_OQ("DDR"),
.DATA_RATE_TQ("BUF"),
.DATA_WIDTH(4'd8),
.SERDES_MODE("MASTER"),
.TRISTATE_WIDTH(1'd1)
) OSERDESE2_24 (
.CLK(sys4x_clk),
.CLKDIV(sys_clk),
.D1(main_a7ddrphy_dfi_p0_cs_n),
.D2(main_a7ddrphy_dfi_p0_cs_n),
.D3(main_a7ddrphy_dfi_p1_cs_n),
.D4(main_a7ddrphy_dfi_p1_cs_n),
.D5(main_a7ddrphy_dfi_p2_cs_n),
.D6(main_a7ddrphy_dfi_p2_cs_n),
.D7(main_a7ddrphy_dfi_p3_cs_n),
.D8(main_a7ddrphy_dfi_p3_cs_n),
.OCE(1'd1),
.RST(sys_rst),
.OQ(ddram_cs_n)
);
OSERDESE2 #(
.DATA_RATE_OQ("DDR"),
.DATA_RATE_TQ("BUF"),
.DATA_WIDTH(4'd8),
.SERDES_MODE("MASTER"),
.TRISTATE_WIDTH(1'd1)
) OSERDESE2_25 (
.CLK(sys4x_clk),
.CLKDIV(sys_clk),
.D1(main_a7ddrphy_dfi_p0_wrdata_mask[0]),
.D2(main_a7ddrphy_dfi_p0_wrdata_mask[2]),
.D3(main_a7ddrphy_dfi_p1_wrdata_mask[0]),
.D4(main_a7ddrphy_dfi_p1_wrdata_mask[2]),
.D5(main_a7ddrphy_dfi_p2_wrdata_mask[0]),
.D6(main_a7ddrphy_dfi_p2_wrdata_mask[2]),
.D7(main_a7ddrphy_dfi_p3_wrdata_mask[0]),
.D8(main_a7ddrphy_dfi_p3_wrdata_mask[2]),
.OCE(1'd1),
.RST(sys_rst),
.OQ(ddram_dm[0])
);
OSERDESE2 #(
.DATA_RATE_OQ("DDR"),
.DATA_RATE_TQ("BUF"),
.DATA_WIDTH(4'd8),
.SERDES_MODE("MASTER"),
.TRISTATE_WIDTH(1'd1)
) OSERDESE2_26 (
.CLK(sys4x_dqs_clk),
.CLKDIV(sys_clk),
.D1(main_a7ddrphy_dqs_serdes_pattern[0]),
.D2(main_a7ddrphy_dqs_serdes_pattern[1]),
.D3(main_a7ddrphy_dqs_serdes_pattern[2]),
.D4(main_a7ddrphy_dqs_serdes_pattern[3]),
.D5(main_a7ddrphy_dqs_serdes_pattern[4]),
.D6(main_a7ddrphy_dqs_serdes_pattern[5]),
.D7(main_a7ddrphy_dqs_serdes_pattern[6]),
.D8(main_a7ddrphy_dqs_serdes_pattern[7]),
.OCE(1'd1),
.RST(sys_rst),
.T1((~main_a7ddrphy_oe_dqs)),
.TCE(1'd1),
.OFB(main_a7ddrphy0),
.OQ(main_a7ddrphy_dqs_nodelay0),
.TQ(main_a7ddrphy_dqs_t0)
);
OBUFTDS OBUFTDS(
.I(main_a7ddrphy_dqs_nodelay0),
.T(main_a7ddrphy_dqs_t0),
.O(ddram_dqs_p[0]),
.OB(ddram_dqs_n[0])
);
OSERDESE2 #(
.DATA_RATE_OQ("DDR"),
.DATA_RATE_TQ("BUF"),
.DATA_WIDTH(4'd8),
.SERDES_MODE("MASTER"),
.TRISTATE_WIDTH(1'd1)
) OSERDESE2_27 (
.CLK(sys4x_clk),
.CLKDIV(sys_clk),
.D1(main_a7ddrphy_dfi_p0_wrdata_mask[1]),
.D2(main_a7ddrphy_dfi_p0_wrdata_mask[3]),
.D3(main_a7ddrphy_dfi_p1_wrdata_mask[1]),
.D4(main_a7ddrphy_dfi_p1_wrdata_mask[3]),
.D5(main_a7ddrphy_dfi_p2_wrdata_mask[1]),
.D6(main_a7ddrphy_dfi_p2_wrdata_mask[3]),
.D7(main_a7ddrphy_dfi_p3_wrdata_mask[1]),
.D8(main_a7ddrphy_dfi_p3_wrdata_mask[3]),
.OCE(1'd1),
.RST(sys_rst),
.OQ(ddram_dm[1])
);
OSERDESE2 #(
.DATA_RATE_OQ("DDR"),
.DATA_RATE_TQ("BUF"),
.DATA_WIDTH(4'd8),
.SERDES_MODE("MASTER"),
.TRISTATE_WIDTH(1'd1)
) OSERDESE2_28 (
.CLK(sys4x_dqs_clk),
.CLKDIV(sys_clk),
.D1(main_a7ddrphy_dqs_serdes_pattern[0]),
.D2(main_a7ddrphy_dqs_serdes_pattern[1]),
.D3(main_a7ddrphy_dqs_serdes_pattern[2]),
.D4(main_a7ddrphy_dqs_serdes_pattern[3]),
.D5(main_a7ddrphy_dqs_serdes_pattern[4]),
.D6(main_a7ddrphy_dqs_serdes_pattern[5]),
.D7(main_a7ddrphy_dqs_serdes_pattern[6]),
.D8(main_a7ddrphy_dqs_serdes_pattern[7]),
.OCE(1'd1),
.RST(sys_rst),
.T1((~main_a7ddrphy_oe_dqs)),
.TCE(1'd1),
.OFB(main_a7ddrphy1),
.OQ(main_a7ddrphy_dqs_nodelay1),
.TQ(main_a7ddrphy_dqs_t1)
);
OBUFTDS OBUFTDS_1(
.I(main_a7ddrphy_dqs_nodelay1),
.T(main_a7ddrphy_dqs_t1),
.O(ddram_dqs_p[1]),
.OB(ddram_dqs_n[1])
);
OSERDESE2 #(
.DATA_RATE_OQ("DDR"),
.DATA_RATE_TQ("BUF"),
.DATA_WIDTH(4'd8),
.SERDES_MODE("MASTER"),
.TRISTATE_WIDTH(1'd1)
) OSERDESE2_29 (
.CLK(sys4x_clk),
.CLKDIV(sys_clk),
.D1(main_a7ddrphy_dfi_p0_wrdata[0]),
.D2(main_a7ddrphy_dfi_p0_wrdata[16]),
.D3(main_a7ddrphy_dfi_p1_wrdata[0]),
.D4(main_a7ddrphy_dfi_p1_wrdata[16]),
.D5(main_a7ddrphy_dfi_p2_wrdata[0]),
.D6(main_a7ddrphy_dfi_p2_wrdata[16]),
.D7(main_a7ddrphy_dfi_p3_wrdata[0]),
.D8(main_a7ddrphy_dfi_p3_wrdata[16]),
.OCE(1'd1),
.RST(sys_rst),
.T1((~main_a7ddrphy_oe_dq)),
.TCE(1'd1),
.OQ(main_a7ddrphy_dq_o_nodelay0),
.TQ(main_a7ddrphy_dq_t0)
);
ISERDESE2 #(
.DATA_RATE("DDR"),
.DATA_WIDTH(4'd8),
.INTERFACE_TYPE("NETWORKING"),
.IOBDELAY("IFD"),
.NUM_CE(1'd1),
.SERDES_MODE("MASTER")
) ISERDESE2 (
.BITSLIP(1'd0),
.CE1(1'd1),
.CLK(sys4x_clk),
.CLKB((~sys4x_clk)),
.CLKDIV(sys_clk),
.DDLY(main_a7ddrphy_dq_i_delayed0),
.RST(sys_rst),
.Q1(main_a7ddrphy_dq_i_data0[7]),
.Q2(main_a7ddrphy_dq_i_data0[6]),
.Q3(main_a7ddrphy_dq_i_data0[5]),
.Q4(main_a7ddrphy_dq_i_data0[4]),
.Q5(main_a7ddrphy_dq_i_data0[3]),
.Q6(main_a7ddrphy_dq_i_data0[2]),
.Q7(main_a7ddrphy_dq_i_data0[1]),
.Q8(main_a7ddrphy_dq_i_data0[0])
);
IDELAYE2 #(
.CINVCTRL_SEL("FALSE"),
.DELAY_SRC("IDATAIN"),
.HIGH_PERFORMANCE_MODE("TRUE"),
.IDELAY_TYPE("VARIABLE"),
.IDELAY_VALUE(1'd0),
.PIPE_SEL("FALSE"),
.REFCLK_FREQUENCY(200.0),
.SIGNAL_PATTERN("DATA")
) IDELAYE2 (
.C(sys_clk),
.CE((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_inc_re)),
.IDATAIN(main_a7ddrphy_dq_i_nodelay0),
.INC(1'd1),
.LD((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_rst_re)),
.LDPIPEEN(1'd0),
.DATAOUT(main_a7ddrphy_dq_i_delayed0)
);
IOBUF IOBUF(
.I(main_a7ddrphy_dq_o_nodelay0),
.T(main_a7ddrphy_dq_t0),
.IO(ddram_dq[0]),
.O(main_a7ddrphy_dq_i_nodelay0)
);
OSERDESE2 #(
.DATA_RATE_OQ("DDR"),
.DATA_RATE_TQ("BUF"),
.DATA_WIDTH(4'd8),
.SERDES_MODE("MASTER"),
.TRISTATE_WIDTH(1'd1)
) OSERDESE2_30 (
.CLK(sys4x_clk),
.CLKDIV(sys_clk),
.D1(main_a7ddrphy_dfi_p0_wrdata[1]),
.D2(main_a7ddrphy_dfi_p0_wrdata[17]),
.D3(main_a7ddrphy_dfi_p1_wrdata[1]),
.D4(main_a7ddrphy_dfi_p1_wrdata[17]),
.D5(main_a7ddrphy_dfi_p2_wrdata[1]),
.D6(main_a7ddrphy_dfi_p2_wrdata[17]),
.D7(main_a7ddrphy_dfi_p3_wrdata[1]),
.D8(main_a7ddrphy_dfi_p3_wrdata[17]),
.OCE(1'd1),
.RST(sys_rst),
.T1((~main_a7ddrphy_oe_dq)),
.TCE(1'd1),
.OQ(main_a7ddrphy_dq_o_nodelay1),
.TQ(main_a7ddrphy_dq_t1)
);
ISERDESE2 #(
.DATA_RATE("DDR"),
.DATA_WIDTH(4'd8),
.INTERFACE_TYPE("NETWORKING"),
.IOBDELAY("IFD"),
.NUM_CE(1'd1),
.SERDES_MODE("MASTER")
) ISERDESE2_1 (
.BITSLIP(1'd0),
.CE1(1'd1),
.CLK(sys4x_clk),
.CLKB((~sys4x_clk)),
.CLKDIV(sys_clk),
.DDLY(main_a7ddrphy_dq_i_delayed1),
.RST(sys_rst),
.Q1(main_a7ddrphy_dq_i_data1[7]),
.Q2(main_a7ddrphy_dq_i_data1[6]),
.Q3(main_a7ddrphy_dq_i_data1[5]),
.Q4(main_a7ddrphy_dq_i_data1[4]),
.Q5(main_a7ddrphy_dq_i_data1[3]),
.Q6(main_a7ddrphy_dq_i_data1[2]),
.Q7(main_a7ddrphy_dq_i_data1[1]),
.Q8(main_a7ddrphy_dq_i_data1[0])
);
IDELAYE2 #(
.CINVCTRL_SEL("FALSE"),
.DELAY_SRC("IDATAIN"),
.HIGH_PERFORMANCE_MODE("TRUE"),
.IDELAY_TYPE("VARIABLE"),
.IDELAY_VALUE(1'd0),
.PIPE_SEL("FALSE"),
.REFCLK_FREQUENCY(200.0),
.SIGNAL_PATTERN("DATA")
) IDELAYE2_1 (
.C(sys_clk),
.CE((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_inc_re)),
.IDATAIN(main_a7ddrphy_dq_i_nodelay1),
.INC(1'd1),
.LD((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_rst_re)),
.LDPIPEEN(1'd0),
.DATAOUT(main_a7ddrphy_dq_i_delayed1)
);
IOBUF IOBUF_1(
.I(main_a7ddrphy_dq_o_nodelay1),
.T(main_a7ddrphy_dq_t1),
.IO(ddram_dq[1]),
.O(main_a7ddrphy_dq_i_nodelay1)
);
OSERDESE2 #(
.DATA_RATE_OQ("DDR"),
.DATA_RATE_TQ("BUF"),
.DATA_WIDTH(4'd8),
.SERDES_MODE("MASTER"),
.TRISTATE_WIDTH(1'd1)
) OSERDESE2_31 (
.CLK(sys4x_clk),
.CLKDIV(sys_clk),
.D1(main_a7ddrphy_dfi_p0_wrdata[2]),
.D2(main_a7ddrphy_dfi_p0_wrdata[18]),
.D3(main_a7ddrphy_dfi_p1_wrdata[2]),
.D4(main_a7ddrphy_dfi_p1_wrdata[18]),
.D5(main_a7ddrphy_dfi_p2_wrdata[2]),
.D6(main_a7ddrphy_dfi_p2_wrdata[18]),
.D7(main_a7ddrphy_dfi_p3_wrdata[2]),
.D8(main_a7ddrphy_dfi_p3_wrdata[18]),
.OCE(1'd1),
.RST(sys_rst),
.T1((~main_a7ddrphy_oe_dq)),
.TCE(1'd1),
.OQ(main_a7ddrphy_dq_o_nodelay2),
.TQ(main_a7ddrphy_dq_t2)
);
ISERDESE2 #(
.DATA_RATE("DDR"),
.DATA_WIDTH(4'd8),
.INTERFACE_TYPE("NETWORKING"),
.IOBDELAY("IFD"),
.NUM_CE(1'd1),
.SERDES_MODE("MASTER")
) ISERDESE2_2 (
.BITSLIP(1'd0),
.CE1(1'd1),
.CLK(sys4x_clk),
.CLKB((~sys4x_clk)),
.CLKDIV(sys_clk),
.DDLY(main_a7ddrphy_dq_i_delayed2),
.RST(sys_rst),
.Q1(main_a7ddrphy_dq_i_data2[7]),
.Q2(main_a7ddrphy_dq_i_data2[6]),
.Q3(main_a7ddrphy_dq_i_data2[5]),
.Q4(main_a7ddrphy_dq_i_data2[4]),
.Q5(main_a7ddrphy_dq_i_data2[3]),
.Q6(main_a7ddrphy_dq_i_data2[2]),
.Q7(main_a7ddrphy_dq_i_data2[1]),
.Q8(main_a7ddrphy_dq_i_data2[0])
);
IDELAYE2 #(
.CINVCTRL_SEL("FALSE"),
.DELAY_SRC("IDATAIN"),
.HIGH_PERFORMANCE_MODE("TRUE"),
.IDELAY_TYPE("VARIABLE"),
.IDELAY_VALUE(1'd0),
.PIPE_SEL("FALSE"),
.REFCLK_FREQUENCY(200.0),
.SIGNAL_PATTERN("DATA")
) IDELAYE2_2 (
.C(sys_clk),
.CE((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_inc_re)),
.IDATAIN(main_a7ddrphy_dq_i_nodelay2),
.INC(1'd1),
.LD((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_rst_re)),
.LDPIPEEN(1'd0),
.DATAOUT(main_a7ddrphy_dq_i_delayed2)
);
IOBUF IOBUF_2(
.I(main_a7ddrphy_dq_o_nodelay2),
.T(main_a7ddrphy_dq_t2),
.IO(ddram_dq[2]),
.O(main_a7ddrphy_dq_i_nodelay2)
);
OSERDESE2 #(
.DATA_RATE_OQ("DDR"),
.DATA_RATE_TQ("BUF"),
.DATA_WIDTH(4'd8),
.SERDES_MODE("MASTER"),
.TRISTATE_WIDTH(1'd1)
) OSERDESE2_32 (
.CLK(sys4x_clk),
.CLKDIV(sys_clk),
.D1(main_a7ddrphy_dfi_p0_wrdata[3]),
.D2(main_a7ddrphy_dfi_p0_wrdata[19]),
.D3(main_a7ddrphy_dfi_p1_wrdata[3]),
.D4(main_a7ddrphy_dfi_p1_wrdata[19]),
.D5(main_a7ddrphy_dfi_p2_wrdata[3]),
.D6(main_a7ddrphy_dfi_p2_wrdata[19]),
.D7(main_a7ddrphy_dfi_p3_wrdata[3]),
.D8(main_a7ddrphy_dfi_p3_wrdata[19]),
.OCE(1'd1),
.RST(sys_rst),
.T1((~main_a7ddrphy_oe_dq)),
.TCE(1'd1),
.OQ(main_a7ddrphy_dq_o_nodelay3),
.TQ(main_a7ddrphy_dq_t3)
);
ISERDESE2 #(
.DATA_RATE("DDR"),
.DATA_WIDTH(4'd8),
.INTERFACE_TYPE("NETWORKING"),
.IOBDELAY("IFD"),
.NUM_CE(1'd1),
.SERDES_MODE("MASTER")
) ISERDESE2_3 (
.BITSLIP(1'd0),
.CE1(1'd1),
.CLK(sys4x_clk),
.CLKB((~sys4x_clk)),
.CLKDIV(sys_clk),
.DDLY(main_a7ddrphy_dq_i_delayed3),
.RST(sys_rst),
.Q1(main_a7ddrphy_dq_i_data3[7]),
.Q2(main_a7ddrphy_dq_i_data3[6]),
.Q3(main_a7ddrphy_dq_i_data3[5]),
.Q4(main_a7ddrphy_dq_i_data3[4]),
.Q5(main_a7ddrphy_dq_i_data3[3]),
.Q6(main_a7ddrphy_dq_i_data3[2]),
.Q7(main_a7ddrphy_dq_i_data3[1]),
.Q8(main_a7ddrphy_dq_i_data3[0])
);
IDELAYE2 #(
.CINVCTRL_SEL("FALSE"),
.DELAY_SRC("IDATAIN"),
.HIGH_PERFORMANCE_MODE("TRUE"),
.IDELAY_TYPE("VARIABLE"),
.IDELAY_VALUE(1'd0),
.PIPE_SEL("FALSE"),
.REFCLK_FREQUENCY(200.0),
.SIGNAL_PATTERN("DATA")
) IDELAYE2_3 (
.C(sys_clk),
.CE((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_inc_re)),
.IDATAIN(main_a7ddrphy_dq_i_nodelay3),
.INC(1'd1),
.LD((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_rst_re)),
.LDPIPEEN(1'd0),
.DATAOUT(main_a7ddrphy_dq_i_delayed3)
);
IOBUF IOBUF_3(
.I(main_a7ddrphy_dq_o_nodelay3),
.T(main_a7ddrphy_dq_t3),
.IO(ddram_dq[3]),
.O(main_a7ddrphy_dq_i_nodelay3)
);
OSERDESE2 #(
.DATA_RATE_OQ("DDR"),
.DATA_RATE_TQ("BUF"),
.DATA_WIDTH(4'd8),
.SERDES_MODE("MASTER"),
.TRISTATE_WIDTH(1'd1)
) OSERDESE2_33 (
.CLK(sys4x_clk),
.CLKDIV(sys_clk),
.D1(main_a7ddrphy_dfi_p0_wrdata[4]),
.D2(main_a7ddrphy_dfi_p0_wrdata[20]),
.D3(main_a7ddrphy_dfi_p1_wrdata[4]),
.D4(main_a7ddrphy_dfi_p1_wrdata[20]),
.D5(main_a7ddrphy_dfi_p2_wrdata[4]),
.D6(main_a7ddrphy_dfi_p2_wrdata[20]),
.D7(main_a7ddrphy_dfi_p3_wrdata[4]),
.D8(main_a7ddrphy_dfi_p3_wrdata[20]),
.OCE(1'd1),
.RST(sys_rst),
.T1((~main_a7ddrphy_oe_dq)),
.TCE(1'd1),
.OQ(main_a7ddrphy_dq_o_nodelay4),
.TQ(main_a7ddrphy_dq_t4)
);
ISERDESE2 #(
.DATA_RATE("DDR"),
.DATA_WIDTH(4'd8),
.INTERFACE_TYPE("NETWORKING"),
.IOBDELAY("IFD"),
.NUM_CE(1'd1),
.SERDES_MODE("MASTER")
) ISERDESE2_4 (
.BITSLIP(1'd0),
.CE1(1'd1),
.CLK(sys4x_clk),
.CLKB((~sys4x_clk)),
.CLKDIV(sys_clk),
.DDLY(main_a7ddrphy_dq_i_delayed4),
.RST(sys_rst),
.Q1(main_a7ddrphy_dq_i_data4[7]),
.Q2(main_a7ddrphy_dq_i_data4[6]),
.Q3(main_a7ddrphy_dq_i_data4[5]),
.Q4(main_a7ddrphy_dq_i_data4[4]),
.Q5(main_a7ddrphy_dq_i_data4[3]),
.Q6(main_a7ddrphy_dq_i_data4[2]),
.Q7(main_a7ddrphy_dq_i_data4[1]),
.Q8(main_a7ddrphy_dq_i_data4[0])
);
IDELAYE2 #(
.CINVCTRL_SEL("FALSE"),
.DELAY_SRC("IDATAIN"),
.HIGH_PERFORMANCE_MODE("TRUE"),
.IDELAY_TYPE("VARIABLE"),
.IDELAY_VALUE(1'd0),
.PIPE_SEL("FALSE"),
.REFCLK_FREQUENCY(200.0),
.SIGNAL_PATTERN("DATA")
) IDELAYE2_4 (
.C(sys_clk),
.CE((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_inc_re)),
.IDATAIN(main_a7ddrphy_dq_i_nodelay4),
.INC(1'd1),
.LD((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_rst_re)),
.LDPIPEEN(1'd0),
.DATAOUT(main_a7ddrphy_dq_i_delayed4)
);
IOBUF IOBUF_4(
.I(main_a7ddrphy_dq_o_nodelay4),
.T(main_a7ddrphy_dq_t4),
.IO(ddram_dq[4]),
.O(main_a7ddrphy_dq_i_nodelay4)
);
OSERDESE2 #(
.DATA_RATE_OQ("DDR"),
.DATA_RATE_TQ("BUF"),
.DATA_WIDTH(4'd8),
.SERDES_MODE("MASTER"),
.TRISTATE_WIDTH(1'd1)
) OSERDESE2_34 (
.CLK(sys4x_clk),
.CLKDIV(sys_clk),
.D1(main_a7ddrphy_dfi_p0_wrdata[5]),
.D2(main_a7ddrphy_dfi_p0_wrdata[21]),
.D3(main_a7ddrphy_dfi_p1_wrdata[5]),
.D4(main_a7ddrphy_dfi_p1_wrdata[21]),
.D5(main_a7ddrphy_dfi_p2_wrdata[5]),
.D6(main_a7ddrphy_dfi_p2_wrdata[21]),
.D7(main_a7ddrphy_dfi_p3_wrdata[5]),
.D8(main_a7ddrphy_dfi_p3_wrdata[21]),
.OCE(1'd1),
.RST(sys_rst),
.T1((~main_a7ddrphy_oe_dq)),
.TCE(1'd1),
.OQ(main_a7ddrphy_dq_o_nodelay5),
.TQ(main_a7ddrphy_dq_t5)
);
ISERDESE2 #(
.DATA_RATE("DDR"),
.DATA_WIDTH(4'd8),
.INTERFACE_TYPE("NETWORKING"),
.IOBDELAY("IFD"),
.NUM_CE(1'd1),
.SERDES_MODE("MASTER")
) ISERDESE2_5 (
.BITSLIP(1'd0),
.CE1(1'd1),
.CLK(sys4x_clk),
.CLKB((~sys4x_clk)),
.CLKDIV(sys_clk),
.DDLY(main_a7ddrphy_dq_i_delayed5),
.RST(sys_rst),
.Q1(main_a7ddrphy_dq_i_data5[7]),
.Q2(main_a7ddrphy_dq_i_data5[6]),
.Q3(main_a7ddrphy_dq_i_data5[5]),
.Q4(main_a7ddrphy_dq_i_data5[4]),
.Q5(main_a7ddrphy_dq_i_data5[3]),
.Q6(main_a7ddrphy_dq_i_data5[2]),
.Q7(main_a7ddrphy_dq_i_data5[1]),
.Q8(main_a7ddrphy_dq_i_data5[0])
);
IDELAYE2 #(
.CINVCTRL_SEL("FALSE"),
.DELAY_SRC("IDATAIN"),
.HIGH_PERFORMANCE_MODE("TRUE"),
.IDELAY_TYPE("VARIABLE"),
.IDELAY_VALUE(1'd0),
.PIPE_SEL("FALSE"),
.REFCLK_FREQUENCY(200.0),
.SIGNAL_PATTERN("DATA")
) IDELAYE2_5 (
.C(sys_clk),
.CE((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_inc_re)),
.IDATAIN(main_a7ddrphy_dq_i_nodelay5),
.INC(1'd1),
.LD((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_rst_re)),
.LDPIPEEN(1'd0),
.DATAOUT(main_a7ddrphy_dq_i_delayed5)
);
IOBUF IOBUF_5(
.I(main_a7ddrphy_dq_o_nodelay5),
.T(main_a7ddrphy_dq_t5),
.IO(ddram_dq[5]),
.O(main_a7ddrphy_dq_i_nodelay5)
);
OSERDESE2 #(
.DATA_RATE_OQ("DDR"),
.DATA_RATE_TQ("BUF"),
.DATA_WIDTH(4'd8),
.SERDES_MODE("MASTER"),
.TRISTATE_WIDTH(1'd1)
) OSERDESE2_35 (
.CLK(sys4x_clk),
.CLKDIV(sys_clk),
.D1(main_a7ddrphy_dfi_p0_wrdata[6]),
.D2(main_a7ddrphy_dfi_p0_wrdata[22]),
.D3(main_a7ddrphy_dfi_p1_wrdata[6]),
.D4(main_a7ddrphy_dfi_p1_wrdata[22]),
.D5(main_a7ddrphy_dfi_p2_wrdata[6]),
.D6(main_a7ddrphy_dfi_p2_wrdata[22]),
.D7(main_a7ddrphy_dfi_p3_wrdata[6]),
.D8(main_a7ddrphy_dfi_p3_wrdata[22]),
.OCE(1'd1),
.RST(sys_rst),
.T1((~main_a7ddrphy_oe_dq)),
.TCE(1'd1),
.OQ(main_a7ddrphy_dq_o_nodelay6),
.TQ(main_a7ddrphy_dq_t6)
);
ISERDESE2 #(
.DATA_RATE("DDR"),
.DATA_WIDTH(4'd8),
.INTERFACE_TYPE("NETWORKING"),
.IOBDELAY("IFD"),
.NUM_CE(1'd1),
.SERDES_MODE("MASTER")
) ISERDESE2_6 (
.BITSLIP(1'd0),
.CE1(1'd1),
.CLK(sys4x_clk),
.CLKB((~sys4x_clk)),
.CLKDIV(sys_clk),
.DDLY(main_a7ddrphy_dq_i_delayed6),
.RST(sys_rst),
.Q1(main_a7ddrphy_dq_i_data6[7]),
.Q2(main_a7ddrphy_dq_i_data6[6]),
.Q3(main_a7ddrphy_dq_i_data6[5]),
.Q4(main_a7ddrphy_dq_i_data6[4]),
.Q5(main_a7ddrphy_dq_i_data6[3]),
.Q6(main_a7ddrphy_dq_i_data6[2]),
.Q7(main_a7ddrphy_dq_i_data6[1]),
.Q8(main_a7ddrphy_dq_i_data6[0])
);
IDELAYE2 #(
.CINVCTRL_SEL("FALSE"),
.DELAY_SRC("IDATAIN"),
.HIGH_PERFORMANCE_MODE("TRUE"),
.IDELAY_TYPE("VARIABLE"),
.IDELAY_VALUE(1'd0),
.PIPE_SEL("FALSE"),
.REFCLK_FREQUENCY(200.0),
.SIGNAL_PATTERN("DATA")
) IDELAYE2_6 (
.C(sys_clk),
.CE((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_inc_re)),
.IDATAIN(main_a7ddrphy_dq_i_nodelay6),
.INC(1'd1),
.LD((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_rst_re)),
.LDPIPEEN(1'd0),
.DATAOUT(main_a7ddrphy_dq_i_delayed6)
);
IOBUF IOBUF_6(
.I(main_a7ddrphy_dq_o_nodelay6),
.T(main_a7ddrphy_dq_t6),
.IO(ddram_dq[6]),
.O(main_a7ddrphy_dq_i_nodelay6)
);
OSERDESE2 #(
.DATA_RATE_OQ("DDR"),
.DATA_RATE_TQ("BUF"),
.DATA_WIDTH(4'd8),
.SERDES_MODE("MASTER"),
.TRISTATE_WIDTH(1'd1)
) OSERDESE2_36 (
.CLK(sys4x_clk),
.CLKDIV(sys_clk),
.D1(main_a7ddrphy_dfi_p0_wrdata[7]),
.D2(main_a7ddrphy_dfi_p0_wrdata[23]),
.D3(main_a7ddrphy_dfi_p1_wrdata[7]),
.D4(main_a7ddrphy_dfi_p1_wrdata[23]),
.D5(main_a7ddrphy_dfi_p2_wrdata[7]),
.D6(main_a7ddrphy_dfi_p2_wrdata[23]),
.D7(main_a7ddrphy_dfi_p3_wrdata[7]),
.D8(main_a7ddrphy_dfi_p3_wrdata[23]),
.OCE(1'd1),
.RST(sys_rst),
.T1((~main_a7ddrphy_oe_dq)),
.TCE(1'd1),
.OQ(main_a7ddrphy_dq_o_nodelay7),
.TQ(main_a7ddrphy_dq_t7)
);
ISERDESE2 #(
.DATA_RATE("DDR"),
.DATA_WIDTH(4'd8),
.INTERFACE_TYPE("NETWORKING"),
.IOBDELAY("IFD"),
.NUM_CE(1'd1),
.SERDES_MODE("MASTER")
) ISERDESE2_7 (
.BITSLIP(1'd0),
.CE1(1'd1),
.CLK(sys4x_clk),
.CLKB((~sys4x_clk)),
.CLKDIV(sys_clk),
.DDLY(main_a7ddrphy_dq_i_delayed7),
.RST(sys_rst),
.Q1(main_a7ddrphy_dq_i_data7[7]),
.Q2(main_a7ddrphy_dq_i_data7[6]),
.Q3(main_a7ddrphy_dq_i_data7[5]),
.Q4(main_a7ddrphy_dq_i_data7[4]),
.Q5(main_a7ddrphy_dq_i_data7[3]),
.Q6(main_a7ddrphy_dq_i_data7[2]),
.Q7(main_a7ddrphy_dq_i_data7[1]),
.Q8(main_a7ddrphy_dq_i_data7[0])
);
IDELAYE2 #(
.CINVCTRL_SEL("FALSE"),
.DELAY_SRC("IDATAIN"),
.HIGH_PERFORMANCE_MODE("TRUE"),
.IDELAY_TYPE("VARIABLE"),
.IDELAY_VALUE(1'd0),
.PIPE_SEL("FALSE"),
.REFCLK_FREQUENCY(200.0),
.SIGNAL_PATTERN("DATA")
) IDELAYE2_7 (
.C(sys_clk),
.CE((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_inc_re)),
.IDATAIN(main_a7ddrphy_dq_i_nodelay7),
.INC(1'd1),
.LD((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_rst_re)),
.LDPIPEEN(1'd0),
.DATAOUT(main_a7ddrphy_dq_i_delayed7)
);
IOBUF IOBUF_7(
.I(main_a7ddrphy_dq_o_nodelay7),
.T(main_a7ddrphy_dq_t7),
.IO(ddram_dq[7]),
.O(main_a7ddrphy_dq_i_nodelay7)
);
OSERDESE2 #(
.DATA_RATE_OQ("DDR"),
.DATA_RATE_TQ("BUF"),
.DATA_WIDTH(4'd8),
.SERDES_MODE("MASTER"),
.TRISTATE_WIDTH(1'd1)
) OSERDESE2_37 (
.CLK(sys4x_clk),
.CLKDIV(sys_clk),
.D1(main_a7ddrphy_dfi_p0_wrdata[8]),
.D2(main_a7ddrphy_dfi_p0_wrdata[24]),
.D3(main_a7ddrphy_dfi_p1_wrdata[8]),
.D4(main_a7ddrphy_dfi_p1_wrdata[24]),
.D5(main_a7ddrphy_dfi_p2_wrdata[8]),
.D6(main_a7ddrphy_dfi_p2_wrdata[24]),
.D7(main_a7ddrphy_dfi_p3_wrdata[8]),
.D8(main_a7ddrphy_dfi_p3_wrdata[24]),
.OCE(1'd1),
.RST(sys_rst),
.T1((~main_a7ddrphy_oe_dq)),
.TCE(1'd1),
.OQ(main_a7ddrphy_dq_o_nodelay8),
.TQ(main_a7ddrphy_dq_t8)
);
ISERDESE2 #(
.DATA_RATE("DDR"),
.DATA_WIDTH(4'd8),
.INTERFACE_TYPE("NETWORKING"),
.IOBDELAY("IFD"),
.NUM_CE(1'd1),
.SERDES_MODE("MASTER")
) ISERDESE2_8 (
.BITSLIP(1'd0),
.CE1(1'd1),
.CLK(sys4x_clk),
.CLKB((~sys4x_clk)),
.CLKDIV(sys_clk),
.DDLY(main_a7ddrphy_dq_i_delayed8),
.RST(sys_rst),
.Q1(main_a7ddrphy_dq_i_data8[7]),
.Q2(main_a7ddrphy_dq_i_data8[6]),
.Q3(main_a7ddrphy_dq_i_data8[5]),
.Q4(main_a7ddrphy_dq_i_data8[4]),
.Q5(main_a7ddrphy_dq_i_data8[3]),
.Q6(main_a7ddrphy_dq_i_data8[2]),
.Q7(main_a7ddrphy_dq_i_data8[1]),
.Q8(main_a7ddrphy_dq_i_data8[0])
);
IDELAYE2 #(
.CINVCTRL_SEL("FALSE"),
.DELAY_SRC("IDATAIN"),
.HIGH_PERFORMANCE_MODE("TRUE"),
.IDELAY_TYPE("VARIABLE"),
.IDELAY_VALUE(1'd0),
.PIPE_SEL("FALSE"),
.REFCLK_FREQUENCY(200.0),
.SIGNAL_PATTERN("DATA")
) IDELAYE2_8 (
.C(sys_clk),
.CE((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_inc_re)),
.IDATAIN(main_a7ddrphy_dq_i_nodelay8),
.INC(1'd1),
.LD((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_rst_re)),
.LDPIPEEN(1'd0),
.DATAOUT(main_a7ddrphy_dq_i_delayed8)
);
IOBUF IOBUF_8(
.I(main_a7ddrphy_dq_o_nodelay8),
.T(main_a7ddrphy_dq_t8),
.IO(ddram_dq[8]),
.O(main_a7ddrphy_dq_i_nodelay8)
);
OSERDESE2 #(
.DATA_RATE_OQ("DDR"),
.DATA_RATE_TQ("BUF"),
.DATA_WIDTH(4'd8),
.SERDES_MODE("MASTER"),
.TRISTATE_WIDTH(1'd1)
) OSERDESE2_38 (
.CLK(sys4x_clk),
.CLKDIV(sys_clk),
.D1(main_a7ddrphy_dfi_p0_wrdata[9]),
.D2(main_a7ddrphy_dfi_p0_wrdata[25]),
.D3(main_a7ddrphy_dfi_p1_wrdata[9]),
.D4(main_a7ddrphy_dfi_p1_wrdata[25]),
.D5(main_a7ddrphy_dfi_p2_wrdata[9]),
.D6(main_a7ddrphy_dfi_p2_wrdata[25]),
.D7(main_a7ddrphy_dfi_p3_wrdata[9]),
.D8(main_a7ddrphy_dfi_p3_wrdata[25]),
.OCE(1'd1),
.RST(sys_rst),
.T1((~main_a7ddrphy_oe_dq)),
.TCE(1'd1),
.OQ(main_a7ddrphy_dq_o_nodelay9),
.TQ(main_a7ddrphy_dq_t9)
);
ISERDESE2 #(
.DATA_RATE("DDR"),
.DATA_WIDTH(4'd8),
.INTERFACE_TYPE("NETWORKING"),
.IOBDELAY("IFD"),
.NUM_CE(1'd1),
.SERDES_MODE("MASTER")
) ISERDESE2_9 (
.BITSLIP(1'd0),
.CE1(1'd1),
.CLK(sys4x_clk),
.CLKB((~sys4x_clk)),
.CLKDIV(sys_clk),
.DDLY(main_a7ddrphy_dq_i_delayed9),
.RST(sys_rst),
.Q1(main_a7ddrphy_dq_i_data9[7]),
.Q2(main_a7ddrphy_dq_i_data9[6]),
.Q3(main_a7ddrphy_dq_i_data9[5]),
.Q4(main_a7ddrphy_dq_i_data9[4]),
.Q5(main_a7ddrphy_dq_i_data9[3]),
.Q6(main_a7ddrphy_dq_i_data9[2]),
.Q7(main_a7ddrphy_dq_i_data9[1]),
.Q8(main_a7ddrphy_dq_i_data9[0])
);
IDELAYE2 #(
.CINVCTRL_SEL("FALSE"),
.DELAY_SRC("IDATAIN"),
.HIGH_PERFORMANCE_MODE("TRUE"),
.IDELAY_TYPE("VARIABLE"),
.IDELAY_VALUE(1'd0),
.PIPE_SEL("FALSE"),
.REFCLK_FREQUENCY(200.0),
.SIGNAL_PATTERN("DATA")
) IDELAYE2_9 (
.C(sys_clk),
.CE((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_inc_re)),
.IDATAIN(main_a7ddrphy_dq_i_nodelay9),
.INC(1'd1),
.LD((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_rst_re)),
.LDPIPEEN(1'd0),
.DATAOUT(main_a7ddrphy_dq_i_delayed9)
);
IOBUF IOBUF_9(
.I(main_a7ddrphy_dq_o_nodelay9),
.T(main_a7ddrphy_dq_t9),
.IO(ddram_dq[9]),
.O(main_a7ddrphy_dq_i_nodelay9)
);
OSERDESE2 #(
.DATA_RATE_OQ("DDR"),
.DATA_RATE_TQ("BUF"),
.DATA_WIDTH(4'd8),
.SERDES_MODE("MASTER"),
.TRISTATE_WIDTH(1'd1)
) OSERDESE2_39 (
.CLK(sys4x_clk),
.CLKDIV(sys_clk),
.D1(main_a7ddrphy_dfi_p0_wrdata[10]),
.D2(main_a7ddrphy_dfi_p0_wrdata[26]),
.D3(main_a7ddrphy_dfi_p1_wrdata[10]),
.D4(main_a7ddrphy_dfi_p1_wrdata[26]),
.D5(main_a7ddrphy_dfi_p2_wrdata[10]),
.D6(main_a7ddrphy_dfi_p2_wrdata[26]),
.D7(main_a7ddrphy_dfi_p3_wrdata[10]),
.D8(main_a7ddrphy_dfi_p3_wrdata[26]),
.OCE(1'd1),
.RST(sys_rst),
.T1((~main_a7ddrphy_oe_dq)),
.TCE(1'd1),
.OQ(main_a7ddrphy_dq_o_nodelay10),
.TQ(main_a7ddrphy_dq_t10)
);
ISERDESE2 #(
.DATA_RATE("DDR"),
.DATA_WIDTH(4'd8),
.INTERFACE_TYPE("NETWORKING"),
.IOBDELAY("IFD"),
.NUM_CE(1'd1),
.SERDES_MODE("MASTER")
) ISERDESE2_10 (
.BITSLIP(1'd0),
.CE1(1'd1),
.CLK(sys4x_clk),
.CLKB((~sys4x_clk)),
.CLKDIV(sys_clk),
.DDLY(main_a7ddrphy_dq_i_delayed10),
.RST(sys_rst),
.Q1(main_a7ddrphy_dq_i_data10[7]),
.Q2(main_a7ddrphy_dq_i_data10[6]),
.Q3(main_a7ddrphy_dq_i_data10[5]),
.Q4(main_a7ddrphy_dq_i_data10[4]),
.Q5(main_a7ddrphy_dq_i_data10[3]),
.Q6(main_a7ddrphy_dq_i_data10[2]),
.Q7(main_a7ddrphy_dq_i_data10[1]),
.Q8(main_a7ddrphy_dq_i_data10[0])
);
IDELAYE2 #(
.CINVCTRL_SEL("FALSE"),
.DELAY_SRC("IDATAIN"),
.HIGH_PERFORMANCE_MODE("TRUE"),
.IDELAY_TYPE("VARIABLE"),
.IDELAY_VALUE(1'd0),
.PIPE_SEL("FALSE"),
.REFCLK_FREQUENCY(200.0),
.SIGNAL_PATTERN("DATA")
) IDELAYE2_10 (
.C(sys_clk),
.CE((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_inc_re)),
.IDATAIN(main_a7ddrphy_dq_i_nodelay10),
.INC(1'd1),
.LD((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_rst_re)),
.LDPIPEEN(1'd0),
.DATAOUT(main_a7ddrphy_dq_i_delayed10)
);
IOBUF IOBUF_10(
.I(main_a7ddrphy_dq_o_nodelay10),
.T(main_a7ddrphy_dq_t10),
.IO(ddram_dq[10]),
.O(main_a7ddrphy_dq_i_nodelay10)
);
OSERDESE2 #(
.DATA_RATE_OQ("DDR"),
.DATA_RATE_TQ("BUF"),
.DATA_WIDTH(4'd8),
.SERDES_MODE("MASTER"),
.TRISTATE_WIDTH(1'd1)
) OSERDESE2_40 (
.CLK(sys4x_clk),
.CLKDIV(sys_clk),
.D1(main_a7ddrphy_dfi_p0_wrdata[11]),
.D2(main_a7ddrphy_dfi_p0_wrdata[27]),
.D3(main_a7ddrphy_dfi_p1_wrdata[11]),
.D4(main_a7ddrphy_dfi_p1_wrdata[27]),
.D5(main_a7ddrphy_dfi_p2_wrdata[11]),
.D6(main_a7ddrphy_dfi_p2_wrdata[27]),
.D7(main_a7ddrphy_dfi_p3_wrdata[11]),
.D8(main_a7ddrphy_dfi_p3_wrdata[27]),
.OCE(1'd1),
.RST(sys_rst),
.T1((~main_a7ddrphy_oe_dq)),
.TCE(1'd1),
.OQ(main_a7ddrphy_dq_o_nodelay11),
.TQ(main_a7ddrphy_dq_t11)
);
ISERDESE2 #(
.DATA_RATE("DDR"),
.DATA_WIDTH(4'd8),
.INTERFACE_TYPE("NETWORKING"),
.IOBDELAY("IFD"),
.NUM_CE(1'd1),
.SERDES_MODE("MASTER")
) ISERDESE2_11 (
.BITSLIP(1'd0),
.CE1(1'd1),
.CLK(sys4x_clk),
.CLKB((~sys4x_clk)),
.CLKDIV(sys_clk),
.DDLY(main_a7ddrphy_dq_i_delayed11),
.RST(sys_rst),
.Q1(main_a7ddrphy_dq_i_data11[7]),
.Q2(main_a7ddrphy_dq_i_data11[6]),
.Q3(main_a7ddrphy_dq_i_data11[5]),
.Q4(main_a7ddrphy_dq_i_data11[4]),
.Q5(main_a7ddrphy_dq_i_data11[3]),
.Q6(main_a7ddrphy_dq_i_data11[2]),
.Q7(main_a7ddrphy_dq_i_data11[1]),
.Q8(main_a7ddrphy_dq_i_data11[0])
);
IDELAYE2 #(
.CINVCTRL_SEL("FALSE"),
.DELAY_SRC("IDATAIN"),
.HIGH_PERFORMANCE_MODE("TRUE"),
.IDELAY_TYPE("VARIABLE"),
.IDELAY_VALUE(1'd0),
.PIPE_SEL("FALSE"),
.REFCLK_FREQUENCY(200.0),
.SIGNAL_PATTERN("DATA")
) IDELAYE2_11 (
.C(sys_clk),
.CE((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_inc_re)),
.IDATAIN(main_a7ddrphy_dq_i_nodelay11),
.INC(1'd1),
.LD((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_rst_re)),
.LDPIPEEN(1'd0),
.DATAOUT(main_a7ddrphy_dq_i_delayed11)
);
IOBUF IOBUF_11(
.I(main_a7ddrphy_dq_o_nodelay11),
.T(main_a7ddrphy_dq_t11),
.IO(ddram_dq[11]),
.O(main_a7ddrphy_dq_i_nodelay11)
);
OSERDESE2 #(
.DATA_RATE_OQ("DDR"),
.DATA_RATE_TQ("BUF"),
.DATA_WIDTH(4'd8),
.SERDES_MODE("MASTER"),
.TRISTATE_WIDTH(1'd1)
) OSERDESE2_41 (
.CLK(sys4x_clk),
.CLKDIV(sys_clk),
.D1(main_a7ddrphy_dfi_p0_wrdata[12]),
.D2(main_a7ddrphy_dfi_p0_wrdata[28]),
.D3(main_a7ddrphy_dfi_p1_wrdata[12]),
.D4(main_a7ddrphy_dfi_p1_wrdata[28]),
.D5(main_a7ddrphy_dfi_p2_wrdata[12]),
.D6(main_a7ddrphy_dfi_p2_wrdata[28]),
.D7(main_a7ddrphy_dfi_p3_wrdata[12]),
.D8(main_a7ddrphy_dfi_p3_wrdata[28]),
.OCE(1'd1),
.RST(sys_rst),
.T1((~main_a7ddrphy_oe_dq)),
.TCE(1'd1),
.OQ(main_a7ddrphy_dq_o_nodelay12),
.TQ(main_a7ddrphy_dq_t12)
);
ISERDESE2 #(
.DATA_RATE("DDR"),
.DATA_WIDTH(4'd8),
.INTERFACE_TYPE("NETWORKING"),
.IOBDELAY("IFD"),
.NUM_CE(1'd1),
.SERDES_MODE("MASTER")
) ISERDESE2_12 (
.BITSLIP(1'd0),
.CE1(1'd1),
.CLK(sys4x_clk),
.CLKB((~sys4x_clk)),
.CLKDIV(sys_clk),
.DDLY(main_a7ddrphy_dq_i_delayed12),
.RST(sys_rst),
.Q1(main_a7ddrphy_dq_i_data12[7]),
.Q2(main_a7ddrphy_dq_i_data12[6]),
.Q3(main_a7ddrphy_dq_i_data12[5]),
.Q4(main_a7ddrphy_dq_i_data12[4]),
.Q5(main_a7ddrphy_dq_i_data12[3]),
.Q6(main_a7ddrphy_dq_i_data12[2]),
.Q7(main_a7ddrphy_dq_i_data12[1]),
.Q8(main_a7ddrphy_dq_i_data12[0])
);
IDELAYE2 #(
.CINVCTRL_SEL("FALSE"),
.DELAY_SRC("IDATAIN"),
.HIGH_PERFORMANCE_MODE("TRUE"),
.IDELAY_TYPE("VARIABLE"),
.IDELAY_VALUE(1'd0),
.PIPE_SEL("FALSE"),
.REFCLK_FREQUENCY(200.0),
.SIGNAL_PATTERN("DATA")
) IDELAYE2_12 (
.C(sys_clk),
.CE((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_inc_re)),
.IDATAIN(main_a7ddrphy_dq_i_nodelay12),
.INC(1'd1),
.LD((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_rst_re)),
.LDPIPEEN(1'd0),
.DATAOUT(main_a7ddrphy_dq_i_delayed12)
);
IOBUF IOBUF_12(
.I(main_a7ddrphy_dq_o_nodelay12),
.T(main_a7ddrphy_dq_t12),
.IO(ddram_dq[12]),
.O(main_a7ddrphy_dq_i_nodelay12)
);
OSERDESE2 #(
.DATA_RATE_OQ("DDR"),
.DATA_RATE_TQ("BUF"),
.DATA_WIDTH(4'd8),
.SERDES_MODE("MASTER"),
.TRISTATE_WIDTH(1'd1)
) OSERDESE2_42 (
.CLK(sys4x_clk),
.CLKDIV(sys_clk),
.D1(main_a7ddrphy_dfi_p0_wrdata[13]),
.D2(main_a7ddrphy_dfi_p0_wrdata[29]),
.D3(main_a7ddrphy_dfi_p1_wrdata[13]),
.D4(main_a7ddrphy_dfi_p1_wrdata[29]),
.D5(main_a7ddrphy_dfi_p2_wrdata[13]),
.D6(main_a7ddrphy_dfi_p2_wrdata[29]),
.D7(main_a7ddrphy_dfi_p3_wrdata[13]),
.D8(main_a7ddrphy_dfi_p3_wrdata[29]),
.OCE(1'd1),
.RST(sys_rst),
.T1((~main_a7ddrphy_oe_dq)),
.TCE(1'd1),
.OQ(main_a7ddrphy_dq_o_nodelay13),
.TQ(main_a7ddrphy_dq_t13)
);
ISERDESE2 #(
.DATA_RATE("DDR"),
.DATA_WIDTH(4'd8),
.INTERFACE_TYPE("NETWORKING"),
.IOBDELAY("IFD"),
.NUM_CE(1'd1),
.SERDES_MODE("MASTER")
) ISERDESE2_13 (
.BITSLIP(1'd0),
.CE1(1'd1),
.CLK(sys4x_clk),
.CLKB((~sys4x_clk)),
.CLKDIV(sys_clk),
.DDLY(main_a7ddrphy_dq_i_delayed13),
.RST(sys_rst),
.Q1(main_a7ddrphy_dq_i_data13[7]),
.Q2(main_a7ddrphy_dq_i_data13[6]),
.Q3(main_a7ddrphy_dq_i_data13[5]),
.Q4(main_a7ddrphy_dq_i_data13[4]),
.Q5(main_a7ddrphy_dq_i_data13[3]),
.Q6(main_a7ddrphy_dq_i_data13[2]),
.Q7(main_a7ddrphy_dq_i_data13[1]),
.Q8(main_a7ddrphy_dq_i_data13[0])
);
IDELAYE2 #(
.CINVCTRL_SEL("FALSE"),
.DELAY_SRC("IDATAIN"),
.HIGH_PERFORMANCE_MODE("TRUE"),
.IDELAY_TYPE("VARIABLE"),
.IDELAY_VALUE(1'd0),
.PIPE_SEL("FALSE"),
.REFCLK_FREQUENCY(200.0),
.SIGNAL_PATTERN("DATA")
) IDELAYE2_13 (
.C(sys_clk),
.CE((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_inc_re)),
.IDATAIN(main_a7ddrphy_dq_i_nodelay13),
.INC(1'd1),
.LD((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_rst_re)),
.LDPIPEEN(1'd0),
.DATAOUT(main_a7ddrphy_dq_i_delayed13)
);
IOBUF IOBUF_13(
.I(main_a7ddrphy_dq_o_nodelay13),
.T(main_a7ddrphy_dq_t13),
.IO(ddram_dq[13]),
.O(main_a7ddrphy_dq_i_nodelay13)
);
OSERDESE2 #(
.DATA_RATE_OQ("DDR"),
.DATA_RATE_TQ("BUF"),
.DATA_WIDTH(4'd8),
.SERDES_MODE("MASTER"),
.TRISTATE_WIDTH(1'd1)
) OSERDESE2_43 (
.CLK(sys4x_clk),
.CLKDIV(sys_clk),
.D1(main_a7ddrphy_dfi_p0_wrdata[14]),
.D2(main_a7ddrphy_dfi_p0_wrdata[30]),
.D3(main_a7ddrphy_dfi_p1_wrdata[14]),
.D4(main_a7ddrphy_dfi_p1_wrdata[30]),
.D5(main_a7ddrphy_dfi_p2_wrdata[14]),
.D6(main_a7ddrphy_dfi_p2_wrdata[30]),
.D7(main_a7ddrphy_dfi_p3_wrdata[14]),
.D8(main_a7ddrphy_dfi_p3_wrdata[30]),
.OCE(1'd1),
.RST(sys_rst),
.T1((~main_a7ddrphy_oe_dq)),
.TCE(1'd1),
.OQ(main_a7ddrphy_dq_o_nodelay14),
.TQ(main_a7ddrphy_dq_t14)
);
ISERDESE2 #(
.DATA_RATE("DDR"),
.DATA_WIDTH(4'd8),
.INTERFACE_TYPE("NETWORKING"),
.IOBDELAY("IFD"),
.NUM_CE(1'd1),
.SERDES_MODE("MASTER")
) ISERDESE2_14 (
.BITSLIP(1'd0),
.CE1(1'd1),
.CLK(sys4x_clk),
.CLKB((~sys4x_clk)),
.CLKDIV(sys_clk),
.DDLY(main_a7ddrphy_dq_i_delayed14),
.RST(sys_rst),
.Q1(main_a7ddrphy_dq_i_data14[7]),
.Q2(main_a7ddrphy_dq_i_data14[6]),
.Q3(main_a7ddrphy_dq_i_data14[5]),
.Q4(main_a7ddrphy_dq_i_data14[4]),
.Q5(main_a7ddrphy_dq_i_data14[3]),
.Q6(main_a7ddrphy_dq_i_data14[2]),
.Q7(main_a7ddrphy_dq_i_data14[1]),
.Q8(main_a7ddrphy_dq_i_data14[0])
);
IDELAYE2 #(
.CINVCTRL_SEL("FALSE"),
.DELAY_SRC("IDATAIN"),
.HIGH_PERFORMANCE_MODE("TRUE"),
.IDELAY_TYPE("VARIABLE"),
.IDELAY_VALUE(1'd0),
.PIPE_SEL("FALSE"),
.REFCLK_FREQUENCY(200.0),
.SIGNAL_PATTERN("DATA")
) IDELAYE2_14 (
.C(sys_clk),
.CE((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_inc_re)),
.IDATAIN(main_a7ddrphy_dq_i_nodelay14),
.INC(1'd1),
.LD((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_rst_re)),
.LDPIPEEN(1'd0),
.DATAOUT(main_a7ddrphy_dq_i_delayed14)
);
IOBUF IOBUF_14(
.I(main_a7ddrphy_dq_o_nodelay14),
.T(main_a7ddrphy_dq_t14),
.IO(ddram_dq[14]),
.O(main_a7ddrphy_dq_i_nodelay14)
);
OSERDESE2 #(
.DATA_RATE_OQ("DDR"),
.DATA_RATE_TQ("BUF"),
.DATA_WIDTH(4'd8),
.SERDES_MODE("MASTER"),
.TRISTATE_WIDTH(1'd1)
) OSERDESE2_44 (
.CLK(sys4x_clk),
.CLKDIV(sys_clk),
.D1(main_a7ddrphy_dfi_p0_wrdata[15]),
.D2(main_a7ddrphy_dfi_p0_wrdata[31]),
.D3(main_a7ddrphy_dfi_p1_wrdata[15]),
.D4(main_a7ddrphy_dfi_p1_wrdata[31]),
.D5(main_a7ddrphy_dfi_p2_wrdata[15]),
.D6(main_a7ddrphy_dfi_p2_wrdata[31]),
.D7(main_a7ddrphy_dfi_p3_wrdata[15]),
.D8(main_a7ddrphy_dfi_p3_wrdata[31]),
.OCE(1'd1),
.RST(sys_rst),
.T1((~main_a7ddrphy_oe_dq)),
.TCE(1'd1),
.OQ(main_a7ddrphy_dq_o_nodelay15),
.TQ(main_a7ddrphy_dq_t15)
);
ISERDESE2 #(
.DATA_RATE("DDR"),
.DATA_WIDTH(4'd8),
.INTERFACE_TYPE("NETWORKING"),
.IOBDELAY("IFD"),
.NUM_CE(1'd1),
.SERDES_MODE("MASTER")
) ISERDESE2_15 (
.BITSLIP(1'd0),
.CE1(1'd1),
.CLK(sys4x_clk),
.CLKB((~sys4x_clk)),
.CLKDIV(sys_clk),
.DDLY(main_a7ddrphy_dq_i_delayed15),
.RST(sys_rst),
.Q1(main_a7ddrphy_dq_i_data15[7]),
.Q2(main_a7ddrphy_dq_i_data15[6]),
.Q3(main_a7ddrphy_dq_i_data15[5]),
.Q4(main_a7ddrphy_dq_i_data15[4]),
.Q5(main_a7ddrphy_dq_i_data15[3]),
.Q6(main_a7ddrphy_dq_i_data15[2]),
.Q7(main_a7ddrphy_dq_i_data15[1]),
.Q8(main_a7ddrphy_dq_i_data15[0])
);
IDELAYE2 #(
.CINVCTRL_SEL("FALSE"),
.DELAY_SRC("IDATAIN"),
.HIGH_PERFORMANCE_MODE("TRUE"),
.IDELAY_TYPE("VARIABLE"),
.IDELAY_VALUE(1'd0),
.PIPE_SEL("FALSE"),
.REFCLK_FREQUENCY(200.0),
.SIGNAL_PATTERN("DATA")
) IDELAYE2_15 (
.C(sys_clk),
.CE((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_inc_re)),
.IDATAIN(main_a7ddrphy_dq_i_nodelay15),
.INC(1'd1),
.LD((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_rst_re)),
.LDPIPEEN(1'd0),
.DATAOUT(main_a7ddrphy_dq_i_delayed15)
);
IOBUF IOBUF_15(
.I(main_a7ddrphy_dq_o_nodelay15),
.T(main_a7ddrphy_dq_t15),
.IO(ddram_dq[15]),
.O(main_a7ddrphy_dq_i_nodelay15)
);
reg [23:0] storage_2[0:7];
reg [23:0] memdat_5;
always @(posedge sys_clk) begin
if (main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_we)
storage_2[main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr] <= main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_dat_w;
memdat_5 <= storage_2[main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr];
end
always @(posedge sys_clk) begin
end
assign main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_dat_r = memdat_5;
assign main_sdram_bankmachine0_cmd_buffer_lookahead_rdport_dat_r = storage_2[main_sdram_bankmachine0_cmd_buffer_lookahead_rdport_adr];
reg [23:0] storage_3[0:7];
reg [23:0] memdat_6;
always @(posedge sys_clk) begin
if (main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_we)
storage_3[main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr] <= main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_dat_w;
memdat_6 <= storage_3[main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr];
end
always @(posedge sys_clk) begin
end
assign main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_dat_r = memdat_6;
assign main_sdram_bankmachine1_cmd_buffer_lookahead_rdport_dat_r = storage_3[main_sdram_bankmachine1_cmd_buffer_lookahead_rdport_adr];
reg [23:0] storage_4[0:7];
reg [23:0] memdat_7;
always @(posedge sys_clk) begin
if (main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_we)
storage_4[main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr] <= main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_dat_w;
memdat_7 <= storage_4[main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr];
end
always @(posedge sys_clk) begin
end
assign main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_dat_r = memdat_7;
assign main_sdram_bankmachine2_cmd_buffer_lookahead_rdport_dat_r = storage_4[main_sdram_bankmachine2_cmd_buffer_lookahead_rdport_adr];
reg [23:0] storage_5[0:7];
reg [23:0] memdat_8;
always @(posedge sys_clk) begin
if (main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_we)
storage_5[main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr] <= main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_dat_w;
memdat_8 <= storage_5[main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr];
end
always @(posedge sys_clk) begin
end
assign main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_dat_r = memdat_8;
assign main_sdram_bankmachine3_cmd_buffer_lookahead_rdport_dat_r = storage_5[main_sdram_bankmachine3_cmd_buffer_lookahead_rdport_adr];
reg [23:0] storage_6[0:7];
reg [23:0] memdat_9;
always @(posedge sys_clk) begin
if (main_sdram_bankmachine4_cmd_buffer_lookahead_wrport_we)
storage_6[main_sdram_bankmachine4_cmd_buffer_lookahead_wrport_adr] <= main_sdram_bankmachine4_cmd_buffer_lookahead_wrport_dat_w;
memdat_9 <= storage_6[main_sdram_bankmachine4_cmd_buffer_lookahead_wrport_adr];
end
always @(posedge sys_clk) begin
end
assign main_sdram_bankmachine4_cmd_buffer_lookahead_wrport_dat_r = memdat_9;
assign main_sdram_bankmachine4_cmd_buffer_lookahead_rdport_dat_r = storage_6[main_sdram_bankmachine4_cmd_buffer_lookahead_rdport_adr];
reg [23:0] storage_7[0:7];
reg [23:0] memdat_10;
always @(posedge sys_clk) begin
if (main_sdram_bankmachine5_cmd_buffer_lookahead_wrport_we)
storage_7[main_sdram_bankmachine5_cmd_buffer_lookahead_wrport_adr] <= main_sdram_bankmachine5_cmd_buffer_lookahead_wrport_dat_w;
memdat_10 <= storage_7[main_sdram_bankmachine5_cmd_buffer_lookahead_wrport_adr];
end
always @(posedge sys_clk) begin
end
assign main_sdram_bankmachine5_cmd_buffer_lookahead_wrport_dat_r = memdat_10;
assign main_sdram_bankmachine5_cmd_buffer_lookahead_rdport_dat_r = storage_7[main_sdram_bankmachine5_cmd_buffer_lookahead_rdport_adr];
reg [23:0] storage_8[0:7];
reg [23:0] memdat_11;
always @(posedge sys_clk) begin
if (main_sdram_bankmachine6_cmd_buffer_lookahead_wrport_we)
storage_8[main_sdram_bankmachine6_cmd_buffer_lookahead_wrport_adr] <= main_sdram_bankmachine6_cmd_buffer_lookahead_wrport_dat_w;
memdat_11 <= storage_8[main_sdram_bankmachine6_cmd_buffer_lookahead_wrport_adr];
end
always @(posedge sys_clk) begin
end
assign main_sdram_bankmachine6_cmd_buffer_lookahead_wrport_dat_r = memdat_11;
assign main_sdram_bankmachine6_cmd_buffer_lookahead_rdport_dat_r = storage_8[main_sdram_bankmachine6_cmd_buffer_lookahead_rdport_adr];
reg [23:0] storage_9[0:7];
reg [23:0] memdat_12;
always @(posedge sys_clk) begin
if (main_sdram_bankmachine7_cmd_buffer_lookahead_wrport_we)
storage_9[main_sdram_bankmachine7_cmd_buffer_lookahead_wrport_adr] <= main_sdram_bankmachine7_cmd_buffer_lookahead_wrport_dat_w;
memdat_12 <= storage_9[main_sdram_bankmachine7_cmd_buffer_lookahead_wrport_adr];
end
always @(posedge sys_clk) begin
end
assign main_sdram_bankmachine7_cmd_buffer_lookahead_wrport_dat_r = memdat_12;
assign main_sdram_bankmachine7_cmd_buffer_lookahead_rdport_dat_r = storage_9[main_sdram_bankmachine7_cmd_buffer_lookahead_rdport_adr];
reg [23:0] tag_mem[0:511];
reg [8:0] memadr_1;
always @(posedge sys_clk) begin
if (main_tag_port_we)
tag_mem[main_tag_port_adr] <= main_tag_port_dat_w;
memadr_1 <= main_tag_port_adr;
end
assign main_tag_port_dat_r = tag_mem[memadr_1];
VexRiscv VexRiscv(
.clk(sys_clk),
.dBusWishbone_ACK(main_cpu_dbus_ack),
.dBusWishbone_DAT_MISO(main_cpu_dbus_dat_r),
.dBusWishbone_ERR(main_cpu_dbus_err),
.externalInterruptArray(main_cpu_interrupt),
.externalResetVector(1'd0),
.iBusWishbone_ACK(main_cpu_ibus_ack),
.iBusWishbone_DAT_MISO(main_cpu_ibus_dat_r),
.iBusWishbone_ERR(main_cpu_ibus_err),
.reset((sys_rst | main_cpu_reset)),
.softwareInterrupt(1'd0),
.timerInterrupt(1'd0),
.dBusWishbone_ADR(main_cpu_dbus_adr),
.dBusWishbone_BTE(main_cpu_dbus_bte),
.dBusWishbone_CTI(main_cpu_dbus_cti),
.dBusWishbone_CYC(main_cpu_dbus_cyc),
.dBusWishbone_DAT_MOSI(main_cpu_dbus_dat_w),
.dBusWishbone_SEL(main_cpu_dbus_sel),
.dBusWishbone_STB(main_cpu_dbus_stb),
.dBusWishbone_WE(main_cpu_dbus_we),
.iBusWishbone_ADR(main_cpu_ibus_adr),
.iBusWishbone_BTE(main_cpu_ibus_bte),
.iBusWishbone_CTI(main_cpu_ibus_cti),
.iBusWishbone_CYC(main_cpu_ibus_cyc),
.iBusWishbone_DAT_MOSI(main_cpu_ibus_dat_w),
.iBusWishbone_SEL(main_cpu_ibus_sel),
.iBusWishbone_STB(main_cpu_ibus_stb),
.iBusWishbone_WE(main_cpu_ibus_we)
);
PLLE2_ADV #(
.CLKFBOUT_MULT(5'd16),
.CLKIN1_PERIOD(10.0),
.CLKOUT0_DIVIDE(6'd32),
.CLKOUT0_PHASE(1'd0),
.CLKOUT1_DIVIDE(4'd8),
.CLKOUT1_PHASE(1'd0),
.CLKOUT2_DIVIDE(4'd8),
.CLKOUT2_PHASE(7'd90),
.CLKOUT3_DIVIDE(4'd8),
.CLKOUT3_PHASE(1'd0),
.DIVCLK_DIVIDE(1'd1),
.REF_JITTER1(0.01),
.STARTUP_WAIT("FALSE")
) PLLE2_ADV (
.CLKFBIN(builder_pll_fb),
.CLKIN1(main_clkin),
.RST(main_reset),
.CLKFBOUT(builder_pll_fb),
.CLKOUT0(main_clkout0),
.CLKOUT1(main_clkout1),
.CLKOUT2(main_clkout2),
.CLKOUT3(main_clkout3),
.LOCKED(main_locked)
);
reg [7:0] data_mem_grain0[0:511];
reg [8:0] memadr_2;
always @(posedge sys_clk) begin
if (main_data_port_we[0])
data_mem_grain0[main_data_port_adr] <= main_data_port_dat_w[7:0];
memadr_2 <= main_data_port_adr;
end
assign main_data_port_dat_r[7:0] = data_mem_grain0[memadr_2];
reg [7:0] data_mem_grain1[0:511];
reg [8:0] memadr_3;
always @(posedge sys_clk) begin
if (main_data_port_we[1])
data_mem_grain1[main_data_port_adr] <= main_data_port_dat_w[15:8];
memadr_3 <= main_data_port_adr;
end
assign main_data_port_dat_r[15:8] = data_mem_grain1[memadr_3];
reg [7:0] data_mem_grain2[0:511];
reg [8:0] memadr_4;
always @(posedge sys_clk) begin
if (main_data_port_we[2])
data_mem_grain2[main_data_port_adr] <= main_data_port_dat_w[23:16];
memadr_4 <= main_data_port_adr;
end
assign main_data_port_dat_r[23:16] = data_mem_grain2[memadr_4];
reg [7:0] data_mem_grain3[0:511];
reg [8:0] memadr_5;
always @(posedge sys_clk) begin
if (main_data_port_we[3])
data_mem_grain3[main_data_port_adr] <= main_data_port_dat_w[31:24];
memadr_5 <= main_data_port_adr;
end
assign main_data_port_dat_r[31:24] = data_mem_grain3[memadr_5];
reg [7:0] data_mem_grain4[0:511];
reg [8:0] memadr_6;
always @(posedge sys_clk) begin
if (main_data_port_we[4])
data_mem_grain4[main_data_port_adr] <= main_data_port_dat_w[39:32];
memadr_6 <= main_data_port_adr;
end
assign main_data_port_dat_r[39:32] = data_mem_grain4[memadr_6];
reg [7:0] data_mem_grain5[0:511];
reg [8:0] memadr_7;
always @(posedge sys_clk) begin
if (main_data_port_we[5])
data_mem_grain5[main_data_port_adr] <= main_data_port_dat_w[47:40];
memadr_7 <= main_data_port_adr;
end
assign main_data_port_dat_r[47:40] = data_mem_grain5[memadr_7];
reg [7:0] data_mem_grain6[0:511];
reg [8:0] memadr_8;
always @(posedge sys_clk) begin
if (main_data_port_we[6])
data_mem_grain6[main_data_port_adr] <= main_data_port_dat_w[55:48];
memadr_8 <= main_data_port_adr;
end
assign main_data_port_dat_r[55:48] = data_mem_grain6[memadr_8];
reg [7:0] data_mem_grain7[0:511];
reg [8:0] memadr_9;
always @(posedge sys_clk) begin
if (main_data_port_we[7])
data_mem_grain7[main_data_port_adr] <= main_data_port_dat_w[63:56];
memadr_9 <= main_data_port_adr;
end
assign main_data_port_dat_r[63:56] = data_mem_grain7[memadr_9];
reg [7:0] data_mem_grain8[0:511];
reg [8:0] memadr_10;
always @(posedge sys_clk) begin
if (main_data_port_we[8])
data_mem_grain8[main_data_port_adr] <= main_data_port_dat_w[71:64];
memadr_10 <= main_data_port_adr;
end
assign main_data_port_dat_r[71:64] = data_mem_grain8[memadr_10];
reg [7:0] data_mem_grain9[0:511];
reg [8:0] memadr_11;
always @(posedge sys_clk) begin
if (main_data_port_we[9])
data_mem_grain9[main_data_port_adr] <= main_data_port_dat_w[79:72];
memadr_11 <= main_data_port_adr;
end
assign main_data_port_dat_r[79:72] = data_mem_grain9[memadr_11];
reg [7:0] data_mem_grain10[0:511];
reg [8:0] memadr_12;
always @(posedge sys_clk) begin
if (main_data_port_we[10])
data_mem_grain10[main_data_port_adr] <= main_data_port_dat_w[87:80];
memadr_12 <= main_data_port_adr;
end
assign main_data_port_dat_r[87:80] = data_mem_grain10[memadr_12];
reg [7:0] data_mem_grain11[0:511];
reg [8:0] memadr_13;
always @(posedge sys_clk) begin
if (main_data_port_we[11])
data_mem_grain11[main_data_port_adr] <= main_data_port_dat_w[95:88];
memadr_13 <= main_data_port_adr;
end
assign main_data_port_dat_r[95:88] = data_mem_grain11[memadr_13];
reg [7:0] data_mem_grain12[0:511];
reg [8:0] memadr_14;
always @(posedge sys_clk) begin
if (main_data_port_we[12])
data_mem_grain12[main_data_port_adr] <= main_data_port_dat_w[103:96];
memadr_14 <= main_data_port_adr;
end
assign main_data_port_dat_r[103:96] = data_mem_grain12[memadr_14];
reg [7:0] data_mem_grain13[0:511];
reg [8:0] memadr_15;
always @(posedge sys_clk) begin
if (main_data_port_we[13])
data_mem_grain13[main_data_port_adr] <= main_data_port_dat_w[111:104];
memadr_15 <= main_data_port_adr;
end
assign main_data_port_dat_r[111:104] = data_mem_grain13[memadr_15];
reg [7:0] data_mem_grain14[0:511];
reg [8:0] memadr_16;
always @(posedge sys_clk) begin
if (main_data_port_we[14])
data_mem_grain14[main_data_port_adr] <= main_data_port_dat_w[119:112];
memadr_16 <= main_data_port_adr;
end
assign main_data_port_dat_r[119:112] = data_mem_grain14[memadr_16];
reg [7:0] data_mem_grain15[0:511];
reg [8:0] memadr_17;
always @(posedge sys_clk) begin
if (main_data_port_we[15])
data_mem_grain15[main_data_port_adr] <= main_data_port_dat_w[127:120];
memadr_17 <= main_data_port_adr;
end
assign main_data_port_dat_r[127:120] = data_mem_grain15[memadr_17];
(* ars_ff1 = "true", async_reg = "true" *) FDPE #(
.INIT(1'd1)
) FDPE (
.C(sys_clk),
.CE(1'd1),
.D(1'd0),
.PRE(builder_xilinxasyncresetsynchronizerimpl0),
.Q(builder_xilinxasyncresetsynchronizerimpl0_rst_meta)
);
(* ars_ff2 = "true", async_reg = "true" *) FDPE #(
.INIT(1'd1)
) FDPE_1 (
.C(sys_clk),
.CE(1'd1),
.D(builder_xilinxasyncresetsynchronizerimpl0_rst_meta),
.PRE(builder_xilinxasyncresetsynchronizerimpl0),
.Q(sys_rst)
);
(* ars_ff1 = "true", async_reg = "true" *) FDPE #(
.INIT(1'd1)
) FDPE_2 (
.C(sys4x_clk),
.CE(1'd1),
.D(1'd0),
.PRE(builder_xilinxasyncresetsynchronizerimpl1),
.Q(builder_xilinxasyncresetsynchronizerimpl1_rst_meta)
);
(* ars_ff2 = "true", async_reg = "true" *) FDPE #(
.INIT(1'd1)
) FDPE_3 (
.C(sys4x_clk),
.CE(1'd1),
.D(builder_xilinxasyncresetsynchronizerimpl1_rst_meta),
.PRE(builder_xilinxasyncresetsynchronizerimpl1),
.Q(builder_xilinxasyncresetsynchronizerimpl1_expr)
);
(* ars_ff1 = "true", async_reg = "true" *) FDPE #(
.INIT(1'd1)
) FDPE_4 (
.C(sys4x_dqs_clk),
.CE(1'd1),
.D(1'd0),
.PRE(builder_xilinxasyncresetsynchronizerimpl2),
.Q(builder_xilinxasyncresetsynchronizerimpl2_rst_meta)
);
(* ars_ff2 = "true", async_reg = "true" *) FDPE #(
.INIT(1'd1)
) FDPE_5 (
.C(sys4x_dqs_clk),
.CE(1'd1),
.D(builder_xilinxasyncresetsynchronizerimpl2_rst_meta),
.PRE(builder_xilinxasyncresetsynchronizerimpl2),
.Q(builder_xilinxasyncresetsynchronizerimpl2_expr)
);
(* ars_ff1 = "true", async_reg = "true" *) FDPE #(
.INIT(1'd1)
) FDPE_6 (
.C(clk200_clk),
.CE(1'd1),
.D(1'd0),
.PRE(builder_xilinxasyncresetsynchronizerimpl3),
.Q(builder_xilinxasyncresetsynchronizerimpl3_rst_meta)
);
(* ars_ff2 = "true", async_reg = "true" *) FDPE #(
.INIT(1'd1)
) FDPE_7 (
.C(clk200_clk),
.CE(1'd1),
.D(builder_xilinxasyncresetsynchronizerimpl3_rst_meta),
.PRE(builder_xilinxasyncresetsynchronizerimpl3),
.Q(clk200_rst)
);
endmodule
|
module system_vga_buffer_0_0
(clk_w,
clk_r,
wen,
x_addr_w,
y_addr_w,
x_addr_r,
y_addr_r,
data_w,
data_r);
(* x_interface_info = "xilinx.com:signal:clock:1.0 clk CLK" *) input clk_w;
input clk_r;
input wen;
input [9:0]x_addr_w;
input [9:0]y_addr_w;
input [9:0]x_addr_r;
input [9:0]y_addr_r;
input [23:0]data_w;
output [23:0]data_r;
wire clk_r;
wire clk_w;
wire [23:0]data_r;
wire [23:0]data_w;
wire wen;
wire [9:0]x_addr_r;
wire [9:0]x_addr_w;
wire [9:0]y_addr_r;
wire [9:0]y_addr_w;
system_vga_buffer_0_0_vga_buffer U0
(.D({y_addr_w[1:0],x_addr_w}),
.clk_r(clk_r),
.clk_w(clk_w),
.data_r(data_r),
.data_w(data_w),
.wen(wen),
.\y_addr_r[1] ({y_addr_r[1:0],x_addr_r}));
endmodule
|
module system_vga_buffer_0_0_vga_buffer
(data_r,
clk_w,
clk_r,
wen,
data_w,
D,
\y_addr_r[1] );
output [23:0]data_r;
input clk_w;
input clk_r;
input wen;
input [23:0]data_w;
input [11:0]D;
input [11:0]\y_addr_r[1] ;
wire [11:0]D;
wire [11:0]addr_r;
wire [11:0]addr_w;
wire [11:0]c_addr_r;
wire [11:0]c_addr_w;
wire clk_r;
wire clk_w;
wire [23:0]data_r;
wire [23:0]data_w;
wire wen;
wire [11:0]\y_addr_r[1] ;
wire NLW_data_reg_0_CASCADEOUTA_UNCONNECTED;
wire NLW_data_reg_0_CASCADEOUTB_UNCONNECTED;
wire NLW_data_reg_0_DBITERR_UNCONNECTED;
wire NLW_data_reg_0_INJECTDBITERR_UNCONNECTED;
wire NLW_data_reg_0_INJECTSBITERR_UNCONNECTED;
wire NLW_data_reg_0_SBITERR_UNCONNECTED;
wire [31:0]NLW_data_reg_0_DOADO_UNCONNECTED;
wire [31:8]NLW_data_reg_0_DOBDO_UNCONNECTED;
wire [3:0]NLW_data_reg_0_DOPADOP_UNCONNECTED;
wire [3:1]NLW_data_reg_0_DOPBDOP_UNCONNECTED;
wire [7:0]NLW_data_reg_0_ECCPARITY_UNCONNECTED;
wire [8:0]NLW_data_reg_0_RDADDRECC_UNCONNECTED;
wire NLW_data_reg_1_CASCADEOUTA_UNCONNECTED;
wire NLW_data_reg_1_CASCADEOUTB_UNCONNECTED;
wire NLW_data_reg_1_DBITERR_UNCONNECTED;
wire NLW_data_reg_1_INJECTDBITERR_UNCONNECTED;
wire NLW_data_reg_1_INJECTSBITERR_UNCONNECTED;
wire NLW_data_reg_1_SBITERR_UNCONNECTED;
wire [31:0]NLW_data_reg_1_DOADO_UNCONNECTED;
wire [31:8]NLW_data_reg_1_DOBDO_UNCONNECTED;
wire [3:0]NLW_data_reg_1_DOPADOP_UNCONNECTED;
wire [3:1]NLW_data_reg_1_DOPBDOP_UNCONNECTED;
wire [7:0]NLW_data_reg_1_ECCPARITY_UNCONNECTED;
wire [8:0]NLW_data_reg_1_RDADDRECC_UNCONNECTED;
wire NLW_data_reg_2_CASCADEOUTA_UNCONNECTED;
wire NLW_data_reg_2_CASCADEOUTB_UNCONNECTED;
wire NLW_data_reg_2_DBITERR_UNCONNECTED;
wire NLW_data_reg_2_INJECTDBITERR_UNCONNECTED;
wire NLW_data_reg_2_INJECTSBITERR_UNCONNECTED;
wire NLW_data_reg_2_SBITERR_UNCONNECTED;
wire [31:0]NLW_data_reg_2_DOADO_UNCONNECTED;
wire [31:6]NLW_data_reg_2_DOBDO_UNCONNECTED;
wire [3:0]NLW_data_reg_2_DOPADOP_UNCONNECTED;
wire [3:0]NLW_data_reg_2_DOPBDOP_UNCONNECTED;
wire [7:0]NLW_data_reg_2_ECCPARITY_UNCONNECTED;
wire [8:0]NLW_data_reg_2_RDADDRECC_UNCONNECTED;
FDRE \addr_r_reg[0]
(.C(clk_r),
.CE(1'b1),
.D(c_addr_r[0]),
.Q(addr_r[0]),
.R(1'b0));
FDRE \addr_r_reg[10]
(.C(clk_r),
.CE(1'b1),
.D(c_addr_r[10]),
.Q(addr_r[10]),
.R(1'b0));
FDRE \addr_r_reg[11]
(.C(clk_r),
.CE(1'b1),
.D(c_addr_r[11]),
.Q(addr_r[11]),
.R(1'b0));
FDRE \addr_r_reg[1]
(.C(clk_r),
.CE(1'b1),
.D(c_addr_r[1]),
.Q(addr_r[1]),
.R(1'b0));
FDRE \addr_r_reg[2]
(.C(clk_r),
.CE(1'b1),
.D(c_addr_r[2]),
.Q(addr_r[2]),
.R(1'b0));
FDRE \addr_r_reg[3]
(.C(clk_r),
.CE(1'b1),
.D(c_addr_r[3]),
.Q(addr_r[3]),
.R(1'b0));
FDRE \addr_r_reg[4]
(.C(clk_r),
.CE(1'b1),
.D(c_addr_r[4]),
.Q(addr_r[4]),
.R(1'b0));
FDRE \addr_r_reg[5]
(.C(clk_r),
.CE(1'b1),
.D(c_addr_r[5]),
.Q(addr_r[5]),
.R(1'b0));
FDRE \addr_r_reg[6]
(.C(clk_r),
.CE(1'b1),
.D(c_addr_r[6]),
.Q(addr_r[6]),
.R(1'b0));
FDRE \addr_r_reg[7]
(.C(clk_r),
.CE(1'b1),
.D(c_addr_r[7]),
.Q(addr_r[7]),
.R(1'b0));
FDRE \addr_r_reg[8]
(.C(clk_r),
.CE(1'b1),
.D(c_addr_r[8]),
.Q(addr_r[8]),
.R(1'b0));
FDRE \addr_r_reg[9]
(.C(clk_r),
.CE(1'b1),
.D(c_addr_r[9]),
.Q(addr_r[9]),
.R(1'b0));
FDRE \addr_w_reg[0]
(.C(clk_w),
.CE(wen),
.D(c_addr_w[0]),
.Q(addr_w[0]),
.R(1'b0));
FDRE \addr_w_reg[10]
(.C(clk_w),
.CE(wen),
.D(c_addr_w[10]),
.Q(addr_w[10]),
.R(1'b0));
FDRE \addr_w_reg[11]
(.C(clk_w),
.CE(wen),
.D(c_addr_w[11]),
.Q(addr_w[11]),
.R(1'b0));
FDRE \addr_w_reg[1]
(.C(clk_w),
.CE(wen),
.D(c_addr_w[1]),
.Q(addr_w[1]),
.R(1'b0));
FDRE \addr_w_reg[2]
(.C(clk_w),
.CE(wen),
.D(c_addr_w[2]),
.Q(addr_w[2]),
.R(1'b0));
FDRE \addr_w_reg[3]
(.C(clk_w),
.CE(wen),
.D(c_addr_w[3]),
.Q(addr_w[3]),
.R(1'b0));
FDRE \addr_w_reg[4]
(.C(clk_w),
.CE(wen),
.D(c_addr_w[4]),
.Q(addr_w[4]),
.R(1'b0));
FDRE \addr_w_reg[5]
(.C(clk_w),
.CE(wen),
.D(c_addr_w[5]),
.Q(addr_w[5]),
.R(1'b0));
FDRE \addr_w_reg[6]
(.C(clk_w),
.CE(wen),
.D(c_addr_w[6]),
.Q(addr_w[6]),
.R(1'b0));
FDRE \addr_w_reg[7]
(.C(clk_w),
.CE(wen),
.D(c_addr_w[7]),
.Q(addr_w[7]),
.R(1'b0));
FDRE \addr_w_reg[8]
(.C(clk_w),
.CE(wen),
.D(c_addr_w[8]),
.Q(addr_w[8]),
.R(1'b0));
FDRE \addr_w_reg[9]
(.C(clk_w),
.CE(wen),
.D(c_addr_w[9]),
.Q(addr_w[9]),
.R(1'b0));
FDRE \c_addr_r_reg[0]
(.C(clk_r),
.CE(1'b1),
.D(\y_addr_r[1] [0]),
.Q(c_addr_r[0]),
.R(1'b0));
FDRE \c_addr_r_reg[10]
(.C(clk_r),
.CE(1'b1),
.D(\y_addr_r[1] [10]),
.Q(c_addr_r[10]),
.R(1'b0));
FDRE \c_addr_r_reg[11]
(.C(clk_r),
.CE(1'b1),
.D(\y_addr_r[1] [11]),
.Q(c_addr_r[11]),
.R(1'b0));
FDRE \c_addr_r_reg[1]
(.C(clk_r),
.CE(1'b1),
.D(\y_addr_r[1] [1]),
.Q(c_addr_r[1]),
.R(1'b0));
FDRE \c_addr_r_reg[2]
(.C(clk_r),
.CE(1'b1),
.D(\y_addr_r[1] [2]),
.Q(c_addr_r[2]),
.R(1'b0));
FDRE \c_addr_r_reg[3]
(.C(clk_r),
.CE(1'b1),
.D(\y_addr_r[1] [3]),
.Q(c_addr_r[3]),
.R(1'b0));
FDRE \c_addr_r_reg[4]
(.C(clk_r),
.CE(1'b1),
.D(\y_addr_r[1] [4]),
.Q(c_addr_r[4]),
.R(1'b0));
FDRE \c_addr_r_reg[5]
(.C(clk_r),
.CE(1'b1),
.D(\y_addr_r[1] [5]),
.Q(c_addr_r[5]),
.R(1'b0));
FDRE \c_addr_r_reg[6]
(.C(clk_r),
.CE(1'b1),
.D(\y_addr_r[1] [6]),
.Q(c_addr_r[6]),
.R(1'b0));
FDRE \c_addr_r_reg[7]
(.C(clk_r),
.CE(1'b1),
.D(\y_addr_r[1] [7]),
.Q(c_addr_r[7]),
.R(1'b0));
FDRE \c_addr_r_reg[8]
(.C(clk_r),
.CE(1'b1),
.D(\y_addr_r[1] [8]),
.Q(c_addr_r[8]),
.R(1'b0));
FDRE \c_addr_r_reg[9]
(.C(clk_r),
.CE(1'b1),
.D(\y_addr_r[1] [9]),
.Q(c_addr_r[9]),
.R(1'b0));
FDRE \c_addr_w_reg[0]
(.C(clk_w),
.CE(wen),
.D(D[0]),
.Q(c_addr_w[0]),
.R(1'b0));
FDRE \c_addr_w_reg[10]
(.C(clk_w),
.CE(wen),
.D(D[10]),
.Q(c_addr_w[10]),
.R(1'b0));
FDRE \c_addr_w_reg[11]
(.C(clk_w),
.CE(wen),
.D(D[11]),
.Q(c_addr_w[11]),
.R(1'b0));
FDRE \c_addr_w_reg[1]
(.C(clk_w),
.CE(wen),
.D(D[1]),
.Q(c_addr_w[1]),
.R(1'b0));
FDRE \c_addr_w_reg[2]
(.C(clk_w),
.CE(wen),
.D(D[2]),
.Q(c_addr_w[2]),
.R(1'b0));
FDRE \c_addr_w_reg[3]
(.C(clk_w),
.CE(wen),
.D(D[3]),
.Q(c_addr_w[3]),
.R(1'b0));
FDRE \c_addr_w_reg[4]
(.C(clk_w),
.CE(wen),
.D(D[4]),
.Q(c_addr_w[4]),
.R(1'b0));
FDRE \c_addr_w_reg[5]
(.C(clk_w),
.CE(wen),
.D(D[5]),
.Q(c_addr_w[5]),
.R(1'b0));
FDRE \c_addr_w_reg[6]
(.C(clk_w),
.CE(wen),
.D(D[6]),
.Q(c_addr_w[6]),
.R(1'b0));
FDRE \c_addr_w_reg[7]
(.C(clk_w),
.CE(wen),
.D(D[7]),
.Q(c_addr_w[7]),
.R(1'b0));
FDRE \c_addr_w_reg[8]
(.C(clk_w),
.CE(wen),
.D(D[8]),
.Q(c_addr_w[8]),
.R(1'b0));
FDRE \c_addr_w_reg[9]
(.C(clk_w),
.CE(wen),
.D(D[9]),
.Q(c_addr_w[9]),
.R(1'b0));
(* CLOCK_DOMAINS = "INDEPENDENT" *)
(* \MEM.PORTA.DATA_BIT_LAYOUT = "p1_d8" *)
(* \MEM.PORTB.DATA_BIT_LAYOUT = "p1_d8" *)
(* METHODOLOGY_DRC_VIOS = "{SYNTH-6 {cell *THIS*}}" *)
(* RTL_RAM_BITS = "98304" *)
(* RTL_RAM_NAME = "data" *)
(* bram_addr_begin = "0" *)
(* bram_addr_end = "4095" *)
(* bram_slice_begin = "0" *)
(* bram_slice_end = "8" *)
RAMB36E1 #(
.DOA_REG(0),
.DOB_REG(0),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
.READ_WIDTH_A(9),
.READ_WIDTH_B(9),
.RSTREG_PRIORITY_A("RSTREG"),
.RSTREG_PRIORITY_B("RSTREG"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("NO_CHANGE"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(9),
.WRITE_WIDTH_B(9))
data_reg_0
(.ADDRARDADDR({1'b1,addr_w,1'b1,1'b1,1'b1}),
.ADDRBWRADDR({1'b1,addr_r,1'b1,1'b1,1'b1}),
.CASCADEINA(1'b1),
.CASCADEINB(1'b1),
.CASCADEOUTA(NLW_data_reg_0_CASCADEOUTA_UNCONNECTED),
.CASCADEOUTB(NLW_data_reg_0_CASCADEOUTB_UNCONNECTED),
.CLKARDCLK(clk_w),
.CLKBWRCLK(clk_r),
.DBITERR(NLW_data_reg_0_DBITERR_UNCONNECTED),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,data_w[7:0]}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
.DIPADIP({1'b0,1'b0,1'b0,data_w[8]}),
.DIPBDIP({1'b0,1'b0,1'b0,1'b1}),
.DOADO(NLW_data_reg_0_DOADO_UNCONNECTED[31:0]),
.DOBDO({NLW_data_reg_0_DOBDO_UNCONNECTED[31:8],data_r[7:0]}),
.DOPADOP(NLW_data_reg_0_DOPADOP_UNCONNECTED[3:0]),
.DOPBDOP({NLW_data_reg_0_DOPBDOP_UNCONNECTED[3:1],data_r[8]}),
.ECCPARITY(NLW_data_reg_0_ECCPARITY_UNCONNECTED[7:0]),
.ENARDEN(wen),
.ENBWREN(1'b1),
.INJECTDBITERR(NLW_data_reg_0_INJECTDBITERR_UNCONNECTED),
.INJECTSBITERR(NLW_data_reg_0_INJECTSBITERR_UNCONNECTED),
.RDADDRECC(NLW_data_reg_0_RDADDRECC_UNCONNECTED[8:0]),
.REGCEAREGCE(1'b0),
.REGCEB(1'b0),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(NLW_data_reg_0_SBITERR_UNCONNECTED),
.WEA({wen,wen,wen,1'b1}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
(* CLOCK_DOMAINS = "INDEPENDENT" *)
(* \MEM.PORTA.DATA_BIT_LAYOUT = "p1_d8" *)
(* \MEM.PORTB.DATA_BIT_LAYOUT = "p1_d8" *)
(* METHODOLOGY_DRC_VIOS = "{SYNTH-6 {cell *THIS*}}" *)
(* RTL_RAM_BITS = "98304" *)
(* RTL_RAM_NAME = "data" *)
(* bram_addr_begin = "0" *)
(* bram_addr_end = "4095" *)
(* bram_slice_begin = "9" *)
(* bram_slice_end = "17" *)
RAMB36E1 #(
.DOA_REG(0),
.DOB_REG(0),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
.READ_WIDTH_A(9),
.READ_WIDTH_B(9),
.RSTREG_PRIORITY_A("RSTREG"),
.RSTREG_PRIORITY_B("RSTREG"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("NO_CHANGE"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(9),
.WRITE_WIDTH_B(9))
data_reg_1
(.ADDRARDADDR({1'b1,addr_w,1'b1,1'b1,1'b1}),
.ADDRBWRADDR({1'b1,addr_r,1'b1,1'b1,1'b1}),
.CASCADEINA(1'b1),
.CASCADEINB(1'b1),
.CASCADEOUTA(NLW_data_reg_1_CASCADEOUTA_UNCONNECTED),
.CASCADEOUTB(NLW_data_reg_1_CASCADEOUTB_UNCONNECTED),
.CLKARDCLK(clk_w),
.CLKBWRCLK(clk_r),
.DBITERR(NLW_data_reg_1_DBITERR_UNCONNECTED),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,data_w[16:9]}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
.DIPADIP({1'b0,1'b0,1'b0,data_w[17]}),
.DIPBDIP({1'b0,1'b0,1'b0,1'b1}),
.DOADO(NLW_data_reg_1_DOADO_UNCONNECTED[31:0]),
.DOBDO({NLW_data_reg_1_DOBDO_UNCONNECTED[31:8],data_r[16:9]}),
.DOPADOP(NLW_data_reg_1_DOPADOP_UNCONNECTED[3:0]),
.DOPBDOP({NLW_data_reg_1_DOPBDOP_UNCONNECTED[3:1],data_r[17]}),
.ECCPARITY(NLW_data_reg_1_ECCPARITY_UNCONNECTED[7:0]),
.ENARDEN(wen),
.ENBWREN(1'b1),
.INJECTDBITERR(NLW_data_reg_1_INJECTDBITERR_UNCONNECTED),
.INJECTSBITERR(NLW_data_reg_1_INJECTSBITERR_UNCONNECTED),
.RDADDRECC(NLW_data_reg_1_RDADDRECC_UNCONNECTED[8:0]),
.REGCEAREGCE(1'b0),
.REGCEB(1'b0),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(NLW_data_reg_1_SBITERR_UNCONNECTED),
.WEA({wen,wen,wen,1'b1}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
(* CLOCK_DOMAINS = "INDEPENDENT" *)
(* \MEM.PORTA.DATA_BIT_LAYOUT = "p0_d6" *)
(* \MEM.PORTB.DATA_BIT_LAYOUT = "p0_d6" *)
(* METHODOLOGY_DRC_VIOS = "{SYNTH-6 {cell *THIS*}}" *)
(* RTL_RAM_BITS = "98304" *)
(* RTL_RAM_NAME = "data" *)
(* bram_addr_begin = "0" *)
(* bram_addr_end = "4095" *)
(* bram_slice_begin = "18" *)
(* bram_slice_end = "23" *)
RAMB36E1 #(
.DOA_REG(0),
.DOB_REG(0),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
.READ_WIDTH_A(9),
.READ_WIDTH_B(9),
.RSTREG_PRIORITY_A("RSTREG"),
.RSTREG_PRIORITY_B("RSTREG"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("NO_CHANGE"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(9),
.WRITE_WIDTH_B(9))
data_reg_2
(.ADDRARDADDR({1'b1,addr_w,1'b1,1'b1,1'b1}),
.ADDRBWRADDR({1'b1,addr_r,1'b1,1'b1,1'b1}),
.CASCADEINA(1'b1),
.CASCADEINB(1'b1),
.CASCADEOUTA(NLW_data_reg_2_CASCADEOUTA_UNCONNECTED),
.CASCADEOUTB(NLW_data_reg_2_CASCADEOUTB_UNCONNECTED),
.CLKARDCLK(clk_w),
.CLKBWRCLK(clk_r),
.DBITERR(NLW_data_reg_2_DBITERR_UNCONNECTED),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,data_w[23:18]}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
.DIPADIP({1'b0,1'b0,1'b0,1'b0}),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO(NLW_data_reg_2_DOADO_UNCONNECTED[31:0]),
.DOBDO({NLW_data_reg_2_DOBDO_UNCONNECTED[31:6],data_r[23:18]}),
.DOPADOP(NLW_data_reg_2_DOPADOP_UNCONNECTED[3:0]),
.DOPBDOP(NLW_data_reg_2_DOPBDOP_UNCONNECTED[3:0]),
.ECCPARITY(NLW_data_reg_2_ECCPARITY_UNCONNECTED[7:0]),
.ENARDEN(wen),
.ENBWREN(1'b1),
.INJECTDBITERR(NLW_data_reg_2_INJECTDBITERR_UNCONNECTED),
.INJECTSBITERR(NLW_data_reg_2_INJECTSBITERR_UNCONNECTED),
.RDADDRECC(NLW_data_reg_2_RDADDRECC_UNCONNECTED[8:0]),
.REGCEAREGCE(1'b0),
.REGCEB(1'b0),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(NLW_data_reg_2_SBITERR_UNCONNECTED),
.WEA({wen,wen,wen,1'b1}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
endmodule
|
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
|
module chip1(
input clk,
input b1,
input b2,
input[3:0] SW,
input rot_a, rot_b, rot_center,
output[7:0] led,
output vga_red,
output vga_green,
output vga_blue,
output vga_hsync,
output vga_vsync,
output [3:0]j4,
input spi_miso, output spi_mosi, output spi_sck, output dac_cs, output dac_clr,
output spi_rom_cs,
output spi_amp_cs,
output spi_adc_conv,
output strataflash_oe,
output strataflash_ce,
output strataflash_we,
output platformflash_oe,
input ps2_clk,
input ps2_data
);
// access to DAC
assign spi_mosi = 0, spi_sck = 0, dac_cs = 0, dac_clr = 0;
// block other devices to access to DAC
assign spi_rom_cs = 1, spi_amp_cs = 1, spi_adc_conv = 0;
assign strataflash_oe = 1, strataflash_ce = 1, strataflash_we = 1;
assign platformflash_oe = 0;
wire[4:0] vga_bus;
assign {vga_red, vga_green, vga_blue, vga_hsync, vga_vsync} = vga_bus;
wire[1:0] ps2_bus = {ps2_clk, ps2_data};
// assign j4 = 0, vga_bus = 0;
wire[3:0] btns = {0, 0, b2, b1};
ag_main agate(clk, btns, SW, led, j4, vga_bus, ps2_bus);
endmodule
|
module altera_tse_multi_mac_pcs_pma_gige
#(
parameter USE_SYNC_RESET = 0, // Use Synchronized Reset Inputs
parameter RESET_LEVEL = 1'b 1 , // Reset Active Level
parameter ENABLE_GMII_LOOPBACK = 1, // GMII_LOOPBACK_ENA : Enable GMII Loopback Logic
parameter ENABLE_HD_LOGIC = 1, // HD_LOGIC_ENA : Enable Half Duplex Logic
parameter ENABLE_SUP_ADDR = 1, // SUP_ADDR_ENA : Enable Supplemental Addresses
parameter ENA_HASH = 1, // ENA_HASH Enable Hash Table
parameter STAT_CNT_ENA = 1, // STAT_CNT_ENA Enable Statistic Counters
parameter MDIO_CLK_DIV = 40 , // Host Clock Division - MDC Generation
parameter CORE_VERSION = 16'h3, // ALTERA Core Version
parameter CUST_VERSION = 1 , // Customer Core Version
parameter REDUCED_INTERFACE_ENA = 0, // Enable the RGMII Interface
parameter ENABLE_MDIO = 1, // Enable the MDIO Interface
parameter ENABLE_MAGIC_DETECT = 1, // Enable magic packet detection
parameter ENABLE_PADDING = 1, // Enable padding operation.
parameter ENABLE_LGTH_CHECK = 1, // Enable frame length checking.
parameter GBIT_ONLY = 1, // Enable Gigabit only operation.
parameter MBIT_ONLY = 1, // Enable Megabit (10/100) only operation.
parameter REDUCED_CONTROL = 0, // Reduced control for MAC LITE
parameter CRC32DWIDTH = 4'b 1000, // input data width (informal, not for change)
parameter CRC32GENDELAY = 3'b 110, // when the data from the generator is valid
parameter CRC32CHECK16BIT = 1'b 0, // 1 compare two times 16 bit of the CRC (adds one pipeline step)
parameter CRC32S1L2_EXTERN = 1'b0, // false: merge enable
parameter ENABLE_SHIFT16 = 0, // Enable byte stuffing at packet header
parameter ENABLE_MAC_FLOW_CTRL = 1'b1, // Option to enable flow control
parameter ENABLE_MAC_TXADDR_SET = 1'b1, // Option to enable MAC address insertion onto 'to-be-transmitted' Ethernet frames on MAC TX data path
parameter ENABLE_MAC_RX_VLAN = 1'b1, // Option to enable VLAN tagged Ethernet frames on MAC RX data path
parameter ENABLE_MAC_TX_VLAN = 1'b1, // Option to enable VLAN tagged Ethernet frames on MAC TX data path
parameter PHY_IDENTIFIER = 32'h 00000000, // PHY Identifier
parameter DEV_VERSION = 16'h 0001 , // Customer Phy's Core Version
parameter ENABLE_SGMII = 1, // Enable SGMII logic for synthesis
parameter ENABLE_CLK_SHARING = 1, // Option to share clock for multiple channels (Clocks are rate-matched).
parameter ENABLE_REG_SHARING = 0, // Option to share register space. Uses certain hard-coded values from input.
parameter ENABLE_EXTENDED_STAT_REG = 0, // Enable a few extended statistic registers
parameter MAX_CHANNELS = 1, // The number of channels in Multi-TSE component
parameter ENABLE_PKT_CLASS = 1, // Enable Packet Classification Av-ST Interface
parameter ENABLE_RX_FIFO_STATUS = 1, // Enable Receive FIFO Almost Full status interface
parameter CHANNEL_WIDTH = 1, // The width of the channel interface
parameter EXPORT_PWRDN = 1'b0, // Option to export the Alt2gxb powerdown signal
parameter DEVICE_FAMILY = "ARRIAGX", // The device family the the core is targetted for.
parameter TRANSCEIVER_OPTION = 1'b0, // Option to select transceiver block for MAC PCS PMA Instantiation. Valid Values are 0 and 1: 0 - GXB (GIGE Mode) 1 - LVDS IO
parameter ENABLE_ALT_RECONFIG = 0, // Option to expose the altreconfig ports
parameter SYNCHRONIZER_DEPTH = 3, // Number of synchronizer
// Internal parameters
parameter STARTING_CHANNEL_NUMBER = 0,
parameter ADDR_WIDTH = (MAX_CHANNELS > 16)? 13 :
(MAX_CHANNELS > 8)? 12 :
(MAX_CHANNELS > 4)? 11 :
(MAX_CHANNELS > 2)? 10 :
(MAX_CHANNELS > 1)? 9 : 8
)
// Port List
(
// RESET / MAC REG IF / MDIO
input wire reset, // Asynchronous Reset - clk Domain
input wire clk, // 25MHz Host Interface Clock
input wire read, // Register Read Strobe
input wire write, // Register Write Strobe
input wire [ADDR_WIDTH-1:0] address, // Register Address
input wire [31:0] writedata, // Write Data for Host Bus
output wire [31:0] readdata, // Read Data to Host Bus
output wire waitrequest, // Interface Busy
output wire mdc, // 2.5MHz Inteface
input wire mdio_in, // MDIO Input
output wire mdio_out, // MDIO Output
output wire mdio_oen, // MDIO Output Enable
// DEVICE SPECIFIC SIGNALS
input wire gxb_cal_blk_clk, // GXB Calibration Clock
input wire ref_clk, // Rference Clock
// SHARED CLK SIGNALS
output wire mac_rx_clk, // Av-ST Receive Clock
output wire mac_tx_clk, // Av-ST Transmit Clock
// SHARED RX STATUS
input wire rx_afull_clk, // Almost full clk
input wire [1:0] rx_afull_data, // Almost full data
input wire rx_afull_valid, // Almost full valid
input wire [CHANNEL_WIDTH-1:0] rx_afull_channel, // Almost full channel
// CHANNEL 0
// PCS SIGNALS TO PHY
input wire rxp_0, // Differential Receive Data
output wire txp_0, // Differential Transmit Data
input wire gxb_pwrdn_in_0, // Powerdown signal to GXB
output wire pcs_pwrdn_out_0, // Powerdown Enable from PCS
output wire rx_recovclkout_0, // Receiver Recovered Clock
output wire led_crs_0, // Carrier Sense
output wire led_link_0, // Valid Link
output wire led_col_0, // Collision Indication
output wire led_an_0, // Auto-Negotiation Status
output wire led_char_err_0, // Character Error
output wire led_disp_err_0, // Disparity Error
// AV-ST TX & RX
output wire mac_rx_clk_0, // Av-ST Receive Clock
output wire mac_tx_clk_0, // Av-ST Transmit Clock
output wire data_rx_sop_0, // Start of Packet
output wire data_rx_eop_0, // End of Packet
output wire [7:0] data_rx_data_0, // Data from FIFO
output wire [4:0] data_rx_error_0, // Receive packet error
output wire data_rx_valid_0, // Data Receive FIFO Valid
input wire data_rx_ready_0, // Data Receive Ready
output wire [4:0] pkt_class_data_0, // Frame Type Indication
output wire pkt_class_valid_0, // Frame Type Indication Valid
input wire data_tx_error_0, // STATUS FIFO (Tx frame Error from Apps)
input wire [7:0] data_tx_data_0, // Data from FIFO transmit
input wire data_tx_valid_0, // Data FIFO transmit Empty
input wire data_tx_sop_0, // Start of Packet
input wire data_tx_eop_0, // END of Packet
output wire data_tx_ready_0, // Data FIFO transmit Read Enable
// STAND_ALONE CONDUITS
output wire tx_ff_uflow_0, // TX FIFO underflow occured (Synchronous with tx_clk)
input wire tx_crc_fwd_0, // Forward Current Frame with CRC from Application
input wire xoff_gen_0, // Xoff Pause frame generate
input wire xon_gen_0, // Xon Pause frame generate
input wire magic_sleep_n_0, // Enable Sleep Mode
output wire magic_wakeup_0, // Wake Up Request
// RECONFIG BLOCK SIGNALS
input wire reconfig_clk_0, // Clock for reconfiguration block
input wire reconfig_busy_0, // Busy from reconfiguration block
input wire [3:0] reconfig_togxb_0, // Signals from the reconfig block to the GXB block
output wire [16:0] reconfig_fromgxb_0, // Signals from the gxb block to the reconfig block
// CHANNEL 1
// PCS SIGNALS TO PHY
input wire rxp_1, // Differential Receive Data
output wire txp_1, // Differential Transmit Data
input wire gxb_pwrdn_in_1, // Powerdown signal to GXB
output wire pcs_pwrdn_out_1, // Powerdown Enable from PCS
output wire rx_recovclkout_1, // Receiver Recovered Clock
output wire led_crs_1, // Carrier Sense
output wire led_link_1, // Valid Link
output wire led_col_1, // Collision Indication
output wire led_an_1, // Auto-Negotiation Status
output wire led_char_err_1, // Character Error
output wire led_disp_err_1, // Disparity Error
// AV-ST TX & RX
output wire mac_rx_clk_1, // Av-ST Receive Clock
output wire mac_tx_clk_1, // Av-ST Transmit Clock
output wire data_rx_sop_1, // Start of Packet
output wire data_rx_eop_1, // End of Packet
output wire [7:0] data_rx_data_1, // Data from FIFO
output wire [4:0] data_rx_error_1, // Receive packet error
output wire data_rx_valid_1, // Data Receive FIFO Valid
input wire data_rx_ready_1, // Data Receive Ready
output wire [4:0] pkt_class_data_1, // Frame Type Indication
output wire pkt_class_valid_1, // Frame Type Indication Valid
input wire data_tx_error_1, // STATUS FIFO (Tx frame Error from Apps)
input wire [7:0] data_tx_data_1, // Data from FIFO transmit
input wire data_tx_valid_1, // Data FIFO transmit Empty
input wire data_tx_sop_1, // Start of Packet
input wire data_tx_eop_1, // END of Packet
output wire data_tx_ready_1, // Data FIFO transmit Read Enable
// STAND_ALONE CONDUITS
output wire tx_ff_uflow_1, // TX FIFO underflow occured (Synchronous with tx_clk)
input wire tx_crc_fwd_1, // Forward Current Frame with CRC from Application
input wire xoff_gen_1, // Xoff Pause frame generate
input wire xon_gen_1, // Xon Pause frame generate
input wire magic_sleep_n_1, // Enable Sleep Mode
output wire magic_wakeup_1, // Wake Up Request
// RECONFIG BLOCK SIGNALS
input wire reconfig_clk_1, // Clock for reconfiguration block
input wire reconfig_busy_1, // Busy from reconfiguration block
input wire [3:0] reconfig_togxb_1, // Signals from the reconfig block to the GXB block
output wire [16:0] reconfig_fromgxb_1, // Signals from the gxb block to the reconfig block
// CHANNEL 2
// PCS SIGNALS TO PHY
input wire rxp_2, // Differential Receive Data
output wire txp_2, // Differential Transmit Data
input wire gxb_pwrdn_in_2, // Powerdown signal to GXB
output wire pcs_pwrdn_out_2, // Powerdown Enable from PCS
output wire rx_recovclkout_2, // Receiver Recovered Clock
output wire led_crs_2, // Carrier Sense
output wire led_link_2, // Valid Link
output wire led_col_2, // Collision Indication
output wire led_an_2, // Auto-Negotiation Status
output wire led_char_err_2, // Character Error
output wire led_disp_err_2, // Disparity Error
// AV-ST TX & RX
output wire mac_rx_clk_2, // Av-ST Receive Clock
output wire mac_tx_clk_2, // Av-ST Transmit Clock
output wire data_rx_sop_2, // Start of Packet
output wire data_rx_eop_2, // End of Packet
output wire [7:0] data_rx_data_2, // Data from FIFO
output wire [4:0] data_rx_error_2, // Receive packet error
output wire data_rx_valid_2, // Data Receive FIFO Valid
input wire data_rx_ready_2, // Data Receive Ready
output wire [4:0] pkt_class_data_2, // Frame Type Indication
output wire pkt_class_valid_2, // Frame Type Indication Valid
input wire data_tx_error_2, // STATUS FIFO (Tx frame Error from Apps)
input wire [7:0] data_tx_data_2, // Data from FIFO transmit
input wire data_tx_valid_2, // Data FIFO transmit Empty
input wire data_tx_sop_2, // Start of Packet
input wire data_tx_eop_2, // END of Packet
output wire data_tx_ready_2, // Data FIFO transmit Read Enable
// STAND_ALONE CONDUITS
output wire tx_ff_uflow_2, // TX FIFO underflow occured (Synchronous with tx_clk)
input wire tx_crc_fwd_2, // Forward Current Frame with CRC from Application
input wire xoff_gen_2, // Xoff Pause frame generate
input wire xon_gen_2, // Xon Pause frame generate
input wire magic_sleep_n_2, // Enable Sleep Mode
output wire magic_wakeup_2, // Wake Up Request
// RECONFIG BLOCK SIGNALS
input wire reconfig_clk_2, // Clock for reconfiguration block
input wire reconfig_busy_2, // Busy from reconfiguration block
input wire [3:0] reconfig_togxb_2, // Signals from the reconfig block to the GXB block
output wire [16:0] reconfig_fromgxb_2, // Signals from the gxb block to the reconfig block
// CHANNEL 3
// PCS SIGNALS TO PHY
input wire rxp_3, // Differential Receive Data
output wire txp_3, // Differential Transmit Data
input wire gxb_pwrdn_in_3, // Powerdown signal to GXB
output wire pcs_pwrdn_out_3, // Powerdown Enable from PCS
output wire rx_recovclkout_3, // Receiver Recovered Clock
output wire led_crs_3, // Carrier Sense
output wire led_link_3, // Valid Link
output wire led_col_3, // Collision Indication
output wire led_an_3, // Auto-Negotiation Status
output wire led_char_err_3, // Character Error
output wire led_disp_err_3, // Disparity Error
// AV-ST TX & RX
output wire mac_rx_clk_3, // Av-ST Receive Clock
output wire mac_tx_clk_3, // Av-ST Transmit Clock
output wire data_rx_sop_3, // Start of Packet
output wire data_rx_eop_3, // End of Packet
output wire [7:0] data_rx_data_3, // Data from FIFO
output wire [4:0] data_rx_error_3, // Receive packet error
output wire data_rx_valid_3, // Data Receive FIFO Valid
input wire data_rx_ready_3, // Data Receive Ready
output wire [4:0] pkt_class_data_3, // Frame Type Indication
output wire pkt_class_valid_3, // Frame Type Indication Valid
input wire data_tx_error_3, // STATUS FIFO (Tx frame Error from Apps)
input wire [7:0] data_tx_data_3, // Data from FIFO transmit
input wire data_tx_valid_3, // Data FIFO transmit Empty
input wire data_tx_sop_3, // Start of Packet
input wire data_tx_eop_3, // END of Packet
output wire data_tx_ready_3, // Data FIFO transmit Read Enable
// STAND_ALONE CONDUITS
output wire tx_ff_uflow_3, // TX FIFO underflow occured (Synchronous with tx_clk)
input wire tx_crc_fwd_3, // Forward Current Frame with CRC from Application
input wire xoff_gen_3, // Xoff Pause frame generate
input wire xon_gen_3, // Xon Pause frame generate
input wire magic_sleep_n_3, // Enable Sleep Mode
output wire magic_wakeup_3, // Wake Up Request
// RECONFIG BLOCK SIGNALS
input wire reconfig_clk_3, // Clock for reconfiguration block
input wire reconfig_busy_3, // Busy from reconfiguration block
input wire [3:0] reconfig_togxb_3, // Signals from the reconfig block to the GXB block
output wire [16:0] reconfig_fromgxb_3, // Signals from the gxb block to the reconfig block
// CHANNEL 4
// PCS SIGNALS TO PHY
input wire rxp_4, // Differential Receive Data
output wire txp_4, // Differential Transmit Data
input wire gxb_pwrdn_in_4, // Powerdown signal to GXB
output wire pcs_pwrdn_out_4, // Powerdown Enable from PCS
output wire rx_recovclkout_4, // Receiver Recovered Clock
output wire led_crs_4, // Carrier Sense
output wire led_link_4, // Valid Link
output wire led_col_4, // Collision Indication
output wire led_an_4, // Auto-Negotiation Status
output wire led_char_err_4, // Character Error
output wire led_disp_err_4, // Disparity Error
// AV-ST TX & RX
output wire mac_rx_clk_4, // Av-ST Receive Clock
output wire mac_tx_clk_4, // Av-ST Transmit Clock
output wire data_rx_sop_4, // Start of Packet
output wire data_rx_eop_4, // End of Packet
output wire [7:0] data_rx_data_4, // Data from FIFO
output wire [4:0] data_rx_error_4, // Receive packet error
output wire data_rx_valid_4, // Data Receive FIFO Valid
input wire data_rx_ready_4, // Data Receive Ready
output wire [4:0] pkt_class_data_4, // Frame Type Indication
output wire pkt_class_valid_4, // Frame Type Indication Valid
input wire data_tx_error_4, // STATUS FIFO (Tx frame Error from Apps)
input wire [7:0] data_tx_data_4, // Data from FIFO transmit
input wire data_tx_valid_4, // Data FIFO transmit Empty
input wire data_tx_sop_4, // Start of Packet
input wire data_tx_eop_4, // END of Packet
output wire data_tx_ready_4, // Data FIFO transmit Read Enable
// STAND_ALONE CONDUITS
output wire tx_ff_uflow_4, // TX FIFO underflow occured (Synchronous with tx_clk)
input wire tx_crc_fwd_4, // Forward Current Frame with CRC from Application
input wire xoff_gen_4, // Xoff Pause frame generate
input wire xon_gen_4, // Xon Pause frame generate
input wire magic_sleep_n_4, // Enable Sleep Mode
output wire magic_wakeup_4, // Wake Up Request
// RECONFIG BLOCK SIGNALS
input wire reconfig_clk_4, // Clock for reconfiguration block
input wire reconfig_busy_4, // Busy from reconfiguration block
input wire [3:0] reconfig_togxb_4, // Signals from the reconfig block to the GXB block
output wire [16:0] reconfig_fromgxb_4, // Signals from the gxb block to the reconfig block
// CHANNEL 5
// PCS SIGNALS TO PHY
input wire rxp_5, // Differential Receive Data
output wire txp_5, // Differential Transmit Data
input wire gxb_pwrdn_in_5, // Powerdown signal to GXB
output wire pcs_pwrdn_out_5, // Powerdown Enable from PCS
output wire rx_recovclkout_5, // Receiver Recovered Clock
output wire led_crs_5, // Carrier Sense
output wire led_link_5, // Valid Link
output wire led_col_5, // Collision Indication
output wire led_an_5, // Auto-Negotiation Status
output wire led_char_err_5, // Character Error
output wire led_disp_err_5, // Disparity Error
// AV-ST TX & RX
output wire mac_rx_clk_5, // Av-ST Receive Clock
output wire mac_tx_clk_5, // Av-ST Transmit Clock
output wire data_rx_sop_5, // Start of Packet
output wire data_rx_eop_5, // End of Packet
output wire [7:0] data_rx_data_5, // Data from FIFO
output wire [4:0] data_rx_error_5, // Receive packet error
output wire data_rx_valid_5, // Data Receive FIFO Valid
input wire data_rx_ready_5, // Data Receive Ready
output wire [4:0] pkt_class_data_5, // Frame Type Indication
output wire pkt_class_valid_5, // Frame Type Indication Valid
input wire data_tx_error_5, // STATUS FIFO (Tx frame Error from Apps)
input wire [7:0] data_tx_data_5, // Data from FIFO transmit
input wire data_tx_valid_5, // Data FIFO transmit Empty
input wire data_tx_sop_5, // Start of Packet
input wire data_tx_eop_5, // END of Packet
output wire data_tx_ready_5, // Data FIFO transmit Read Enable
// STAND_ALONE CONDUITS
output wire tx_ff_uflow_5, // TX FIFO underflow occured (Synchronous with tx_clk)
input wire tx_crc_fwd_5, // Forward Current Frame with CRC from Application
input wire xoff_gen_5, // Xoff Pause frame generate
input wire xon_gen_5, // Xon Pause frame generate
input wire magic_sleep_n_5, // Enable Sleep Mode
output wire magic_wakeup_5, // Wake Up Request
// RECONFIG BLOCK SIGNALS
input wire reconfig_clk_5, // Clock for reconfiguration block
input wire reconfig_busy_5, // Busy from reconfiguration block
input wire [3:0] reconfig_togxb_5, // Signals from the reconfig block to the GXB block
output wire [16:0] reconfig_fromgxb_5, // Signals from the gxb block to the reconfig block
// CHANNEL 6
// PCS SIGNALS TO PHY
input wire rxp_6, // Differential Receive Data
output wire txp_6, // Differential Transmit Data
input wire gxb_pwrdn_in_6, // Powerdown signal to GXB
output wire pcs_pwrdn_out_6, // Powerdown Enable from PCS
output wire rx_recovclkout_6, // Receiver Recovered Clock
output wire led_crs_6, // Carrier Sense
output wire led_link_6, // Valid Link
output wire led_col_6, // Collision Indication
output wire led_an_6, // Auto-Negotiation Status
output wire led_char_err_6, // Character Error
output wire led_disp_err_6, // Disparity Error
// AV-ST TX & RX
output wire mac_rx_clk_6, // Av-ST Receive Clock
output wire mac_tx_clk_6, // Av-ST Transmit Clock
output wire data_rx_sop_6, // Start of Packet
output wire data_rx_eop_6, // End of Packet
output wire [7:0] data_rx_data_6, // Data from FIFO
output wire [4:0] data_rx_error_6, // Receive packet error
output wire data_rx_valid_6, // Data Receive FIFO Valid
input wire data_rx_ready_6, // Data Receive Ready
output wire [4:0] pkt_class_data_6, // Frame Type Indication
output wire pkt_class_valid_6, // Frame Type Indication Valid
input wire data_tx_error_6, // STATUS FIFO (Tx frame Error from Apps)
input wire [7:0] data_tx_data_6, // Data from FIFO transmit
input wire data_tx_valid_6, // Data FIFO transmit Empty
input wire data_tx_sop_6, // Start of Packet
input wire data_tx_eop_6, // END of Packet
output wire data_tx_ready_6, // Data FIFO transmit Read Enable
// STAND_ALONE CONDUITS
output wire tx_ff_uflow_6, // TX FIFO underflow occured (Synchronous with tx_clk)
input wire tx_crc_fwd_6, // Forward Current Frame with CRC from Application
input wire xoff_gen_6, // Xoff Pause frame generate
input wire xon_gen_6, // Xon Pause frame generate
input wire magic_sleep_n_6, // Enable Sleep Mode
output wire magic_wakeup_6, // Wake Up Request
// RECONFIG BLOCK SIGNALS
input wire reconfig_clk_6, // Clock for reconfiguration block
input wire reconfig_busy_6, // Busy from reconfiguration block
input wire [3:0] reconfig_togxb_6, // Signals from the reconfig block to the GXB block
output wire [16:0] reconfig_fromgxb_6, // Signals from the gxb block to the reconfig block
// CHANNEL 7
// PCS SIGNALS TO PHY
input wire rxp_7, // Differential Receive Data
output wire txp_7, // Differential Transmit Data
input wire gxb_pwrdn_in_7, // Powerdown signal to GXB
output wire pcs_pwrdn_out_7, // Powerdown Enable from PCS
output wire rx_recovclkout_7, // Receiver Recovered Clock
output wire led_crs_7, // Carrier Sense
output wire led_link_7, // Valid Link
output wire led_col_7, // Collision Indication
output wire led_an_7, // Auto-Negotiation Status
output wire led_char_err_7, // Character Error
output wire led_disp_err_7, // Disparity Error
// AV-ST TX & RX
output wire mac_rx_clk_7, // Av-ST Receive Clock
output wire mac_tx_clk_7, // Av-ST Transmit Clock
output wire data_rx_sop_7, // Start of Packet
output wire data_rx_eop_7, // End of Packet
output wire [7:0] data_rx_data_7, // Data from FIFO
output wire [4:0] data_rx_error_7, // Receive packet error
output wire data_rx_valid_7, // Data Receive FIFO Valid
input wire data_rx_ready_7, // Data Receive Ready
output wire [4:0] pkt_class_data_7, // Frame Type Indication
output wire pkt_class_valid_7, // Frame Type Indication Valid
input wire data_tx_error_7, // STATUS FIFO (Tx frame Error from Apps)
input wire [7:0] data_tx_data_7, // Data from FIFO transmit
input wire data_tx_valid_7, // Data FIFO transmit Empty
input wire data_tx_sop_7, // Start of Packet
input wire data_tx_eop_7, // END of Packet
output wire data_tx_ready_7, // Data FIFO transmit Read Enable
// STAND_ALONE CONDUITS
output wire tx_ff_uflow_7, // TX FIFO underflow occured (Synchronous with tx_clk)
input wire tx_crc_fwd_7, // Forward Current Frame with CRC from Application
input wire xoff_gen_7, // Xoff Pause frame generate
input wire xon_gen_7, // Xon Pause frame generate
input wire magic_sleep_n_7, // Enable Sleep Mode
output wire magic_wakeup_7, // Wake Up Request
// RECONFIG BLOCK SIGNALS
input wire reconfig_clk_7, // Clock for reconfiguration block
input wire reconfig_busy_7, // Busy from reconfiguration block
input wire [3:0] reconfig_togxb_7, // Signals from the reconfig block to the GXB block
output wire [16:0] reconfig_fromgxb_7, // Signals from the gxb block to the reconfig block
// CHANNEL 8
// PCS SIGNALS TO PHY
input wire rxp_8, // Differential Receive Data
output wire txp_8, // Differential Transmit Data
input wire gxb_pwrdn_in_8, // Powerdown signal to GXB
output wire pcs_pwrdn_out_8, // Powerdown Enable from PCS
output wire rx_recovclkout_8, // Receiver Recovered Clock
output wire led_crs_8, // Carrier Sense
output wire led_link_8, // Valid Link
output wire led_col_8, // Collision Indication
output wire led_an_8, // Auto-Negotiation Status
output wire led_char_err_8, // Character Error
output wire led_disp_err_8, // Disparity Error
// AV-ST TX & RX
output wire mac_rx_clk_8, // Av-ST Receive Clock
output wire mac_tx_clk_8, // Av-ST Transmit Clock
output wire data_rx_sop_8, // Start of Packet
output wire data_rx_eop_8, // End of Packet
output wire [7:0] data_rx_data_8, // Data from FIFO
output wire [4:0] data_rx_error_8, // Receive packet error
output wire data_rx_valid_8, // Data Receive FIFO Valid
input wire data_rx_ready_8, // Data Receive Ready
output wire [4:0] pkt_class_data_8, // Frame Type Indication
output wire pkt_class_valid_8, // Frame Type Indication Valid
input wire data_tx_error_8, // STATUS FIFO (Tx frame Error from Apps)
input wire [7:0] data_tx_data_8, // Data from FIFO transmit
input wire data_tx_valid_8, // Data FIFO transmit Empty
input wire data_tx_sop_8, // Start of Packet
input wire data_tx_eop_8, // END of Packet
output wire data_tx_ready_8, // Data FIFO transmit Read Enable
// STAND_ALONE CONDUITS
output wire tx_ff_uflow_8, // TX FIFO underflow occured (Synchronous with tx_clk)
input wire tx_crc_fwd_8, // Forward Current Frame with CRC from Application
input wire xoff_gen_8, // Xoff Pause frame generate
input wire xon_gen_8, // Xon Pause frame generate
input wire magic_sleep_n_8, // Enable Sleep Mode
output wire magic_wakeup_8, // Wake Up Request
// RECONFIG BLOCK SIGNALS
input wire reconfig_clk_8, // Clock for reconfiguration block
input wire reconfig_busy_8, // Busy from reconfiguration block
input wire [3:0] reconfig_togxb_8, // Signals from the reconfig block to the GXB block
output wire [16:0] reconfig_fromgxb_8, // Signals from the gxb block to the reconfig block
// CHANNEL 9
// PCS SIGNALS TO PHY
input wire rxp_9, // Differential Receive Data
output wire txp_9, // Differential Transmit Data
input wire gxb_pwrdn_in_9, // Powerdown signal to GXB
output wire pcs_pwrdn_out_9, // Powerdown Enable from PCS
output wire rx_recovclkout_9, // Receiver Recovered Clock
output wire led_crs_9, // Carrier Sense
output wire led_link_9, // Valid Link
output wire led_col_9, // Collision Indication
output wire led_an_9, // Auto-Negotiation Status
output wire led_char_err_9, // Character Error
output wire led_disp_err_9, // Disparity Error
// AV-ST TX & RX
output wire mac_rx_clk_9, // Av-ST Receive Clock
output wire mac_tx_clk_9, // Av-ST Transmit Clock
output wire data_rx_sop_9, // Start of Packet
output wire data_rx_eop_9, // End of Packet
output wire [7:0] data_rx_data_9, // Data from FIFO
output wire [4:0] data_rx_error_9, // Receive packet error
output wire data_rx_valid_9, // Data Receive FIFO Valid
input wire data_rx_ready_9, // Data Receive Ready
output wire [4:0] pkt_class_data_9, // Frame Type Indication
output wire pkt_class_valid_9, // Frame Type Indication Valid
input wire data_tx_error_9, // STATUS FIFO (Tx frame Error from Apps)
input wire [7:0] data_tx_data_9, // Data from FIFO transmit
input wire data_tx_valid_9, // Data FIFO transmit Empty
input wire data_tx_sop_9, // Start of Packet
input wire data_tx_eop_9, // END of Packet
output wire data_tx_ready_9, // Data FIFO transmit Read Enable
// STAND_ALONE CONDUITS
output wire tx_ff_uflow_9, // TX FIFO underflow occured (Synchronous with tx_clk)
input wire tx_crc_fwd_9, // Forward Current Frame with CRC from Application
input wire xoff_gen_9, // Xoff Pause frame generate
input wire xon_gen_9, // Xon Pause frame generate
input wire magic_sleep_n_9, // Enable Sleep Mode
output wire magic_wakeup_9, // Wake Up Request
// RECONFIG BLOCK SIGNALS
input wire reconfig_clk_9, // Clock for reconfiguration block
input wire reconfig_busy_9, // Busy from reconfiguration block
input wire [3:0] reconfig_togxb_9, // Signals from the reconfig block to the GXB block
output wire [16:0] reconfig_fromgxb_9, // Signals from the gxb block to the reconfig block
// CHANNEL 10
// PCS SIGNALS TO PHY
input wire rxp_10, // Differential Receive Data
output wire txp_10, // Differential Transmit Data
input wire gxb_pwrdn_in_10, // Powerdown signal to GXB
output wire pcs_pwrdn_out_10, // Powerdown Enable from PCS
output wire rx_recovclkout_10, // Receiver Recovered Clock
output wire led_crs_10, // Carrier Sense
output wire led_link_10, // Valid Link
output wire led_col_10, // Collision Indication
output wire led_an_10, // Auto-Negotiation Status
output wire led_char_err_10, // Character Error
output wire led_disp_err_10, // Disparity Error
// AV-ST TX & RX
output wire mac_rx_clk_10, // Av-ST Receive Clock
output wire mac_tx_clk_10, // Av-ST Transmit Clock
output wire data_rx_sop_10, // Start of Packet
output wire data_rx_eop_10, // End of Packet
output wire [7:0] data_rx_data_10, // Data from FIFO
output wire [4:0] data_rx_error_10, // Receive packet error
output wire data_rx_valid_10, // Data Receive FIFO Valid
input wire data_rx_ready_10, // Data Receive Ready
output wire [4:0] pkt_class_data_10, // Frame Type Indication
output wire pkt_class_valid_10, // Frame Type Indication Valid
input wire data_tx_error_10, // STATUS FIFO (Tx frame Error from Apps)
input wire [7:0] data_tx_data_10, // Data from FIFO transmit
input wire data_tx_valid_10, // Data FIFO transmit Empty
input wire data_tx_sop_10, // Start of Packet
input wire data_tx_eop_10, // END of Packet
output wire data_tx_ready_10, // Data FIFO transmit Read Enable
// STAND_ALONE CONDUITS
output wire tx_ff_uflow_10, // TX FIFO underflow occured (Synchronous with tx_clk)
input wire tx_crc_fwd_10, // Forward Current Frame with CRC from Application
input wire xoff_gen_10, // Xoff Pause frame generate
input wire xon_gen_10, // Xon Pause frame generate
input wire magic_sleep_n_10, // Enable Sleep Mode
output wire magic_wakeup_10, // Wake Up Request
// RECONFIG BLOCK SIGNALS
input wire reconfig_clk_10, // Clock for reconfiguration block
input wire reconfig_busy_10, // Busy from reconfiguration block
input wire [3:0] reconfig_togxb_10, // Signals from the reconfig block to the GXB block
output wire [16:0] reconfig_fromgxb_10, // Signals from the gxb block to the reconfig block
// CHANNEL 11
// PCS SIGNALS TO PHY
input wire rxp_11, // Differential Receive Data
output wire txp_11, // Differential Transmit Data
input wire gxb_pwrdn_in_11, // Powerdown signal to GXB
output wire pcs_pwrdn_out_11, // Powerdown Enable from PCS
output wire rx_recovclkout_11, // Receiver Recovered Clock
output wire led_crs_11, // Carrier Sense
output wire led_link_11, // Valid Link
output wire led_col_11, // Collision Indication
output wire led_an_11, // Auto-Negotiation Status
output wire led_char_err_11, // Character Error
output wire led_disp_err_11, // Disparity Error
// AV-ST TX & RX
output wire mac_rx_clk_11, // Av-ST Receive Clock
output wire mac_tx_clk_11, // Av-ST Transmit Clock
output wire data_rx_sop_11, // Start of Packet
output wire data_rx_eop_11, // End of Packet
output wire [7:0] data_rx_data_11, // Data from FIFO
output wire [4:0] data_rx_error_11, // Receive packet error
output wire data_rx_valid_11, // Data Receive FIFO Valid
input wire data_rx_ready_11, // Data Receive Ready
output wire [4:0] pkt_class_data_11, // Frame Type Indication
output wire pkt_class_valid_11, // Frame Type Indication Valid
input wire data_tx_error_11, // STATUS FIFO (Tx frame Error from Apps)
input wire [7:0] data_tx_data_11, // Data from FIFO transmit
input wire data_tx_valid_11, // Data FIFO transmit Empty
input wire data_tx_sop_11, // Start of Packet
input wire data_tx_eop_11, // END of Packet
output wire data_tx_ready_11, // Data FIFO transmit Read Enable
// STAND_ALONE CONDUITS
output wire tx_ff_uflow_11, // TX FIFO underflow occured (Synchronous with tx_clk)
input wire tx_crc_fwd_11, // Forward Current Frame with CRC from Application
input wire xoff_gen_11, // Xoff Pause frame generate
input wire xon_gen_11, // Xon Pause frame generate
input wire magic_sleep_n_11, // Enable Sleep Mode
output wire magic_wakeup_11, // Wake Up Request
// RECONFIG BLOCK SIGNALS
input wire reconfig_clk_11, // Clock for reconfiguration block
input wire reconfig_busy_11, // Busy from reconfiguration block
input wire [3:0] reconfig_togxb_11, // Signals from the reconfig block to the GXB block
output wire [16:0] reconfig_fromgxb_11, // Signals from the gxb block to the reconfig block
// CHANNEL 12
// PCS SIGNALS TO PHY
input wire rxp_12, // Differential Receive Data
output wire txp_12, // Differential Transmit Data
input wire gxb_pwrdn_in_12, // Powerdown signal to GXB
output wire pcs_pwrdn_out_12, // Powerdown Enable from PCS
output wire rx_recovclkout_12, // Receiver Recovered Clock
output wire led_crs_12, // Carrier Sense
output wire led_link_12, // Valid Link
output wire led_col_12, // Collision Indication
output wire led_an_12, // Auto-Negotiation Status
output wire led_char_err_12, // Character Error
output wire led_disp_err_12, // Disparity Error
// AV-ST TX & RX
output wire mac_rx_clk_12, // Av-ST Receive Clock
output wire mac_tx_clk_12, // Av-ST Transmit Clock
output wire data_rx_sop_12, // Start of Packet
output wire data_rx_eop_12, // End of Packet
output wire [7:0] data_rx_data_12, // Data from FIFO
output wire [4:0] data_rx_error_12, // Receive packet error
output wire data_rx_valid_12, // Data Receive FIFO Valid
input wire data_rx_ready_12, // Data Receive Ready
output wire [4:0] pkt_class_data_12, // Frame Type Indication
output wire pkt_class_valid_12, // Frame Type Indication Valid
input wire data_tx_error_12, // STATUS FIFO (Tx frame Error from Apps)
input wire [7:0] data_tx_data_12, // Data from FIFO transmit
input wire data_tx_valid_12, // Data FIFO transmit Empty
input wire data_tx_sop_12, // Start of Packet
input wire data_tx_eop_12, // END of Packet
output wire data_tx_ready_12, // Data FIFO transmit Read Enable
// STAND_ALONE CONDUITS
output wire tx_ff_uflow_12, // TX FIFO underflow occured (Synchronous with tx_clk)
input wire tx_crc_fwd_12, // Forward Current Frame with CRC from Application
input wire xoff_gen_12, // Xoff Pause frame generate
input wire xon_gen_12, // Xon Pause frame generate
input wire magic_sleep_n_12, // Enable Sleep Mode
output wire magic_wakeup_12, // Wake Up Request
// RECONFIG BLOCK SIGNALS
input wire reconfig_clk_12, // Clock for reconfiguration block
input wire reconfig_busy_12, // Busy from reconfiguration block
input wire [3:0] reconfig_togxb_12, // Signals from the reconfig block to the GXB block
output wire [16:0] reconfig_fromgxb_12, // Signals from the gxb block to the reconfig block
// CHANNEL 13
// PCS SIGNALS TO PHY
input wire rxp_13, // Differential Receive Data
output wire txp_13, // Differential Transmit Data
input wire gxb_pwrdn_in_13, // Powerdown signal to GXB
output wire pcs_pwrdn_out_13, // Powerdown Enable from PCS
output wire rx_recovclkout_13, // Receiver Recovered Clock
output wire led_crs_13, // Carrier Sense
output wire led_link_13, // Valid Link
output wire led_col_13, // Collision Indication
output wire led_an_13, // Auto-Negotiation Status
output wire led_char_err_13, // Character Error
output wire led_disp_err_13, // Disparity Error
// AV-ST TX & RX
output wire mac_rx_clk_13, // Av-ST Receive Clock
output wire mac_tx_clk_13, // Av-ST Transmit Clock
output wire data_rx_sop_13, // Start of Packet
output wire data_rx_eop_13, // End of Packet
output wire [7:0] data_rx_data_13, // Data from FIFO
output wire [4:0] data_rx_error_13, // Receive packet error
output wire data_rx_valid_13, // Data Receive FIFO Valid
input wire data_rx_ready_13, // Data Receive Ready
output wire [4:0] pkt_class_data_13, // Frame Type Indication
output wire pkt_class_valid_13, // Frame Type Indication Valid
input wire data_tx_error_13, // STATUS FIFO (Tx frame Error from Apps)
input wire [7:0] data_tx_data_13, // Data from FIFO transmit
input wire data_tx_valid_13, // Data FIFO transmit Empty
input wire data_tx_sop_13, // Start of Packet
input wire data_tx_eop_13, // END of Packet
output wire data_tx_ready_13, // Data FIFO transmit Read Enable
// STAND_ALONE CONDUITS
output wire tx_ff_uflow_13, // TX FIFO underflow occured (Synchronous with tx_clk)
input wire tx_crc_fwd_13, // Forward Current Frame with CRC from Application
input wire xoff_gen_13, // Xoff Pause frame generate
input wire xon_gen_13, // Xon Pause frame generate
input wire magic_sleep_n_13, // Enable Sleep Mode
output wire magic_wakeup_13, // Wake Up Request
// RECONFIG BLOCK SIGNALS
input wire reconfig_clk_13, // Clock for reconfiguration block
input wire reconfig_busy_13, // Busy from reconfiguration block
input wire [3:0] reconfig_togxb_13, // Signals from the reconfig block to the GXB block
output wire [16:0] reconfig_fromgxb_13, // Signals from the gxb block to the reconfig block
// CHANNEL 14
// PCS SIGNALS TO PHY
input wire rxp_14, // Differential Receive Data
output wire txp_14, // Differential Transmit Data
input wire gxb_pwrdn_in_14, // Powerdown signal to GXB
output wire pcs_pwrdn_out_14, // Powerdown Enable from PCS
output wire rx_recovclkout_14, // Receiver Recovered Clock
output wire led_crs_14, // Carrier Sense
output wire led_link_14, // Valid Link
output wire led_col_14, // Collision Indication
output wire led_an_14, // Auto-Negotiation Status
output wire led_char_err_14, // Character Error
output wire led_disp_err_14, // Disparity Error
// AV-ST TX & RX
output wire mac_rx_clk_14, // Av-ST Receive Clock
output wire mac_tx_clk_14, // Av-ST Transmit Clock
output wire data_rx_sop_14, // Start of Packet
output wire data_rx_eop_14, // End of Packet
output wire [7:0] data_rx_data_14, // Data from FIFO
output wire [4:0] data_rx_error_14, // Receive packet error
output wire data_rx_valid_14, // Data Receive FIFO Valid
input wire data_rx_ready_14, // Data Receive Ready
output wire [4:0] pkt_class_data_14, // Frame Type Indication
output wire pkt_class_valid_14, // Frame Type Indication Valid
input wire data_tx_error_14, // STATUS FIFO (Tx frame Error from Apps)
input wire [7:0] data_tx_data_14, // Data from FIFO transmit
input wire data_tx_valid_14, // Data FIFO transmit Empty
input wire data_tx_sop_14, // Start of Packet
input wire data_tx_eop_14, // END of Packet
output wire data_tx_ready_14, // Data FIFO transmit Read Enable
// STAND_ALONE CONDUITS
output wire tx_ff_uflow_14, // TX FIFO underflow occured (Synchronous with tx_clk)
input wire tx_crc_fwd_14, // Forward Current Frame with CRC from Application
input wire xoff_gen_14, // Xoff Pause frame generate
input wire xon_gen_14, // Xon Pause frame generate
input wire magic_sleep_n_14, // Enable Sleep Mode
output wire magic_wakeup_14, // Wake Up Request
// RECONFIG BLOCK SIGNALS
input wire reconfig_clk_14, // Clock for reconfiguration block
input wire reconfig_busy_14, // Busy from reconfiguration block
input wire [3:0] reconfig_togxb_14, // Signals from the reconfig block to the GXB block
output wire [16:0] reconfig_fromgxb_14, // Signals from the gxb block to the reconfig block
// CHANNEL 15
// PCS SIGNALS TO PHY
input wire rxp_15, // Differential Receive Data
output wire txp_15, // Differential Transmit Data
input wire gxb_pwrdn_in_15, // Powerdown signal to GXB
output wire pcs_pwrdn_out_15, // Powerdown Enable from PCS
output wire rx_recovclkout_15, // Receiver Recovered Clock
output wire led_crs_15, // Carrier Sense
output wire led_link_15, // Valid Link
output wire led_col_15, // Collision Indication
output wire led_an_15, // Auto-Negotiation Status
output wire led_char_err_15, // Character Error
output wire led_disp_err_15, // Disparity Error
// AV-ST TX & RX
output wire mac_rx_clk_15, // Av-ST Receive Clock
output wire mac_tx_clk_15, // Av-ST Transmit Clock
output wire data_rx_sop_15, // Start of Packet
output wire data_rx_eop_15, // End of Packet
output wire [7:0] data_rx_data_15, // Data from FIFO
output wire [4:0] data_rx_error_15, // Receive packet error
output wire data_rx_valid_15, // Data Receive FIFO Valid
input wire data_rx_ready_15, // Data Receive Ready
output wire [4:0] pkt_class_data_15, // Frame Type Indication
output wire pkt_class_valid_15, // Frame Type Indication Valid
input wire data_tx_error_15, // STATUS FIFO (Tx frame Error from Apps)
input wire [7:0] data_tx_data_15, // Data from FIFO transmit
input wire data_tx_valid_15, // Data FIFO transmit Empty
input wire data_tx_sop_15, // Start of Packet
input wire data_tx_eop_15, // END of Packet
output wire data_tx_ready_15, // Data FIFO transmit Read Enable
// STAND_ALONE CONDUITS
output wire tx_ff_uflow_15, // TX FIFO underflow occured (Synchronous with tx_clk)
input wire tx_crc_fwd_15, // Forward Current Frame with CRC from Application
input wire xoff_gen_15, // Xoff Pause frame generate
input wire xon_gen_15, // Xon Pause frame generate
input wire magic_sleep_n_15, // Enable Sleep Mode
output wire magic_wakeup_15, // Wake Up Request
// RECONFIG BLOCK SIGNALS
input wire reconfig_clk_15, // Clock for reconfiguration block
input wire reconfig_busy_15, // Busy from reconfiguration block
input wire [3:0] reconfig_togxb_15, // Signals from the reconfig block to the GXB block
output wire [16:0] reconfig_fromgxb_15, // Signals from the gxb block to the reconfig block
// CHANNEL 16
// PCS SIGNALS TO PHY
input wire rxp_16, // Differential Receive Data
output wire txp_16, // Differential Transmit Data
input wire gxb_pwrdn_in_16, // Powerdown signal to GXB
output wire pcs_pwrdn_out_16, // Powerdown Enable from PCS
output wire rx_recovclkout_16, // Receiver Recovered Clock
output wire led_crs_16, // Carrier Sense
output wire led_link_16, // Valid Link
output wire led_col_16, // Collision Indication
output wire led_an_16, // Auto-Negotiation Status
output wire led_char_err_16, // Character Error
output wire led_disp_err_16, // Disparity Error
// AV-ST TX & RX
output wire mac_rx_clk_16, // Av-ST Receive Clock
output wire mac_tx_clk_16, // Av-ST Transmit Clock
output wire data_rx_sop_16, // Start of Packet
output wire data_rx_eop_16, // End of Packet
output wire [7:0] data_rx_data_16, // Data from FIFO
output wire [4:0] data_rx_error_16, // Receive packet error
output wire data_rx_valid_16, // Data Receive FIFO Valid
input wire data_rx_ready_16, // Data Receive Ready
output wire [4:0] pkt_class_data_16, // Frame Type Indication
output wire pkt_class_valid_16, // Frame Type Indication Valid
input wire data_tx_error_16, // STATUS FIFO (Tx frame Error from Apps)
input wire [7:0] data_tx_data_16, // Data from FIFO transmit
input wire data_tx_valid_16, // Data FIFO transmit Empty
input wire data_tx_sop_16, // Start of Packet
input wire data_tx_eop_16, // END of Packet
output wire data_tx_ready_16, // Data FIFO transmit Read Enable
// STAND_ALONE CONDUITS
output wire tx_ff_uflow_16, // TX FIFO underflow occured (Synchronous with tx_clk)
input wire tx_crc_fwd_16, // Forward Current Frame with CRC from Application
input wire xoff_gen_16, // Xoff Pause frame generate
input wire xon_gen_16, // Xon Pause frame generate
input wire magic_sleep_n_16, // Enable Sleep Mode
output wire magic_wakeup_16, // Wake Up Request
// RECONFIG BLOCK SIGNALS
input wire reconfig_clk_16, // Clock for reconfiguration block
input wire reconfig_busy_16, // Busy from reconfiguration block
input wire [3:0] reconfig_togxb_16, // Signals from the reconfig block to the GXB block
output wire [16:0] reconfig_fromgxb_16, // Signals from the gxb block to the reconfig block
// CHANNEL 17
// PCS SIGNALS TO PHY
input wire rxp_17, // Differential Receive Data
output wire txp_17, // Differential Transmit Data
input wire gxb_pwrdn_in_17, // Powerdown signal to GXB
output wire pcs_pwrdn_out_17, // Powerdown Enable from PCS
output wire rx_recovclkout_17, // Receiver Recovered Clock
output wire led_crs_17, // Carrier Sense
output wire led_link_17, // Valid Link
output wire led_col_17, // Collision Indication
output wire led_an_17, // Auto-Negotiation Status
output wire led_char_err_17, // Character Error
output wire led_disp_err_17, // Disparity Error
// AV-ST TX & RX
output wire mac_rx_clk_17, // Av-ST Receive Clock
output wire mac_tx_clk_17, // Av-ST Transmit Clock
output wire data_rx_sop_17, // Start of Packet
output wire data_rx_eop_17, // End of Packet
output wire [7:0] data_rx_data_17, // Data from FIFO
output wire [4:0] data_rx_error_17, // Receive packet error
output wire data_rx_valid_17, // Data Receive FIFO Valid
input wire data_rx_ready_17, // Data Receive Ready
output wire [4:0] pkt_class_data_17, // Frame Type Indication
output wire pkt_class_valid_17, // Frame Type Indication Valid
input wire data_tx_error_17, // STATUS FIFO (Tx frame Error from Apps)
input wire [7:0] data_tx_data_17, // Data from FIFO transmit
input wire data_tx_valid_17, // Data FIFO transmit Empty
input wire data_tx_sop_17, // Start of Packet
input wire data_tx_eop_17, // END of Packet
output wire data_tx_ready_17, // Data FIFO transmit Read Enable
// STAND_ALONE CONDUITS
output wire tx_ff_uflow_17, // TX FIFO underflow occured (Synchronous with tx_clk)
input wire tx_crc_fwd_17, // Forward Current Frame with CRC from Application
input wire xoff_gen_17, // Xoff Pause frame generate
input wire xon_gen_17, // Xon Pause frame generate
input wire magic_sleep_n_17, // Enable Sleep Mode
output wire magic_wakeup_17, // Wake Up Request
// RECONFIG BLOCK SIGNALS
input wire reconfig_clk_17, // Clock for reconfiguration block
input wire reconfig_busy_17, // Busy from reconfiguration block
input wire [3:0] reconfig_togxb_17, // Signals from the reconfig block to the GXB block
output wire [16:0] reconfig_fromgxb_17, // Signals from the gxb block to the reconfig block
// CHANNEL 18
// PCS SIGNALS TO PHY
input wire rxp_18, // Differential Receive Data
output wire txp_18, // Differential Transmit Data
input wire gxb_pwrdn_in_18, // Powerdown signal to GXB
output wire pcs_pwrdn_out_18, // Powerdown Enable from PCS
output wire rx_recovclkout_18, // Receiver Recovered Clock
output wire led_crs_18, // Carrier Sense
output wire led_link_18, // Valid Link
output wire led_col_18, // Collision Indication
output wire led_an_18, // Auto-Negotiation Status
output wire led_char_err_18, // Character Error
output wire led_disp_err_18, // Disparity Error
// AV-ST TX & RX
output wire mac_rx_clk_18, // Av-ST Receive Clock
output wire mac_tx_clk_18, // Av-ST Transmit Clock
output wire data_rx_sop_18, // Start of Packet
output wire data_rx_eop_18, // End of Packet
output wire [7:0] data_rx_data_18, // Data from FIFO
output wire [4:0] data_rx_error_18, // Receive packet error
output wire data_rx_valid_18, // Data Receive FIFO Valid
input wire data_rx_ready_18, // Data Receive Ready
output wire [4:0] pkt_class_data_18, // Frame Type Indication
output wire pkt_class_valid_18, // Frame Type Indication Valid
input wire data_tx_error_18, // STATUS FIFO (Tx frame Error from Apps)
input wire [7:0] data_tx_data_18, // Data from FIFO transmit
input wire data_tx_valid_18, // Data FIFO transmit Empty
input wire data_tx_sop_18, // Start of Packet
input wire data_tx_eop_18, // END of Packet
output wire data_tx_ready_18, // Data FIFO transmit Read Enable
// STAND_ALONE CONDUITS
output wire tx_ff_uflow_18, // TX FIFO underflow occured (Synchronous with tx_clk)
input wire tx_crc_fwd_18, // Forward Current Frame with CRC from Application
input wire xoff_gen_18, // Xoff Pause frame generate
input wire xon_gen_18, // Xon Pause frame generate
input wire magic_sleep_n_18, // Enable Sleep Mode
output wire magic_wakeup_18, // Wake Up Request
// RECONFIG BLOCK SIGNALS
input wire reconfig_clk_18, // Clock for reconfiguration block
input wire reconfig_busy_18, // Busy from reconfiguration block
input wire [3:0] reconfig_togxb_18, // Signals from the reconfig block to the GXB block
output wire [16:0] reconfig_fromgxb_18, // Signals from the gxb block to the reconfig block
// CHANNEL 19
// PCS SIGNALS TO PHY
input wire rxp_19, // Differential Receive Data
output wire txp_19, // Differential Transmit Data
input wire gxb_pwrdn_in_19, // Powerdown signal to GXB
output wire pcs_pwrdn_out_19, // Powerdown Enable from PCS
output wire rx_recovclkout_19, // Receiver Recovered Clock
output wire led_crs_19, // Carrier Sense
output wire led_link_19, // Valid Link
output wire led_col_19, // Collision Indication
output wire led_an_19, // Auto-Negotiation Status
output wire led_char_err_19, // Character Error
output wire led_disp_err_19, // Disparity Error
// AV-ST TX & RX
output wire mac_rx_clk_19, // Av-ST Receive Clock
output wire mac_tx_clk_19, // Av-ST Transmit Clock
output wire data_rx_sop_19, // Start of Packet
output wire data_rx_eop_19, // End of Packet
output wire [7:0] data_rx_data_19, // Data from FIFO
output wire [4:0] data_rx_error_19, // Receive packet error
output wire data_rx_valid_19, // Data Receive FIFO Valid
input wire data_rx_ready_19, // Data Receive Ready
output wire [4:0] pkt_class_data_19, // Frame Type Indication
output wire pkt_class_valid_19, // Frame Type Indication Valid
input wire data_tx_error_19, // STATUS FIFO (Tx frame Error from Apps)
input wire [7:0] data_tx_data_19, // Data from FIFO transmit
input wire data_tx_valid_19, // Data FIFO transmit Empty
input wire data_tx_sop_19, // Start of Packet
input wire data_tx_eop_19, // END of Packet
output wire data_tx_ready_19, // Data FIFO transmit Read Enable
// STAND_ALONE CONDUITS
output wire tx_ff_uflow_19, // TX FIFO underflow occured (Synchronous with tx_clk)
input wire tx_crc_fwd_19, // Forward Current Frame with CRC from Application
input wire xoff_gen_19, // Xoff Pause frame generate
input wire xon_gen_19, // Xon Pause frame generate
input wire magic_sleep_n_19, // Enable Sleep Mode
output wire magic_wakeup_19, // Wake Up Request
// RECONFIG BLOCK SIGNALS
input wire reconfig_clk_19, // Clock for reconfiguration block
input wire reconfig_busy_19, // Busy from reconfiguration block
input wire [3:0] reconfig_togxb_19, // Signals from the reconfig block to the GXB block
output wire [16:0] reconfig_fromgxb_19, // Signals from the gxb block to the reconfig block
// CHANNEL 20
// PCS SIGNALS TO PHY
input wire rxp_20, // Differential Receive Data
output wire txp_20, // Differential Transmit Data
input wire gxb_pwrdn_in_20, // Powerdown signal to GXB
output wire pcs_pwrdn_out_20, // Powerdown Enable from PCS
output wire rx_recovclkout_20, // Receiver Recovered Clock
output wire led_crs_20, // Carrier Sense
output wire led_link_20, // Valid Link
output wire led_col_20, // Collision Indication
output wire led_an_20, // Auto-Negotiation Status
output wire led_char_err_20, // Character Error
output wire led_disp_err_20, // Disparity Error
// AV-ST TX & RX
output wire mac_rx_clk_20, // Av-ST Receive Clock
output wire mac_tx_clk_20, // Av-ST Transmit Clock
output wire data_rx_sop_20, // Start of Packet
output wire data_rx_eop_20, // End of Packet
output wire [7:0] data_rx_data_20, // Data from FIFO
output wire [4:0] data_rx_error_20, // Receive packet error
output wire data_rx_valid_20, // Data Receive FIFO Valid
input wire data_rx_ready_20, // Data Receive Ready
output wire [4:0] pkt_class_data_20, // Frame Type Indication
output wire pkt_class_valid_20, // Frame Type Indication Valid
input wire data_tx_error_20, // STATUS FIFO (Tx frame Error from Apps)
input wire [7:0] data_tx_data_20, // Data from FIFO transmit
input wire data_tx_valid_20, // Data FIFO transmit Empty
input wire data_tx_sop_20, // Start of Packet
input wire data_tx_eop_20, // END of Packet
output wire data_tx_ready_20, // Data FIFO transmit Read Enable
// STAND_ALONE CONDUITS
output wire tx_ff_uflow_20, // TX FIFO underflow occured (Synchronous with tx_clk)
input wire tx_crc_fwd_20, // Forward Current Frame with CRC from Application
input wire xoff_gen_20, // Xoff Pause frame generate
input wire xon_gen_20, // Xon Pause frame generate
input wire magic_sleep_n_20, // Enable Sleep Mode
output wire magic_wakeup_20, // Wake Up Request
// RECONFIG BLOCK SIGNALS
input wire reconfig_clk_20, // Clock for reconfiguration block
input wire reconfig_busy_20, // Busy from reconfiguration block
input wire [3:0] reconfig_togxb_20, // Signals from the reconfig block to the GXB block
output wire [16:0] reconfig_fromgxb_20, // Signals from the gxb block to the reconfig block
// CHANNEL 21
// PCS SIGNALS TO PHY
input wire rxp_21, // Differential Receive Data
output wire txp_21, // Differential Transmit Data
input wire gxb_pwrdn_in_21, // Powerdown signal to GXB
output wire pcs_pwrdn_out_21, // Powerdown Enable from PCS
output wire rx_recovclkout_21, // Receiver Recovered Clock
output wire led_crs_21, // Carrier Sense
output wire led_link_21, // Valid Link
output wire led_col_21, // Collision Indication
output wire led_an_21, // Auto-Negotiation Status
output wire led_char_err_21, // Character Error
output wire led_disp_err_21, // Disparity Error
// AV-ST TX & RX
output wire mac_rx_clk_21, // Av-ST Receive Clock
output wire mac_tx_clk_21, // Av-ST Transmit Clock
output wire data_rx_sop_21, // Start of Packet
output wire data_rx_eop_21, // End of Packet
output wire [7:0] data_rx_data_21, // Data from FIFO
output wire [4:0] data_rx_error_21, // Receive packet error
output wire data_rx_valid_21, // Data Receive FIFO Valid
input wire data_rx_ready_21, // Data Receive Ready
output wire [4:0] pkt_class_data_21, // Frame Type Indication
output wire pkt_class_valid_21, // Frame Type Indication Valid
input wire data_tx_error_21, // STATUS FIFO (Tx frame Error from Apps)
input wire [7:0] data_tx_data_21, // Data from FIFO transmit
input wire data_tx_valid_21, // Data FIFO transmit Empty
input wire data_tx_sop_21, // Start of Packet
input wire data_tx_eop_21, // END of Packet
output wire data_tx_ready_21, // Data FIFO transmit Read Enable
// STAND_ALONE CONDUITS
output wire tx_ff_uflow_21, // TX FIFO underflow occured (Synchronous with tx_clk)
input wire tx_crc_fwd_21, // Forward Current Frame with CRC from Application
input wire xoff_gen_21, // Xoff Pause frame generate
input wire xon_gen_21, // Xon Pause frame generate
input wire magic_sleep_n_21, // Enable Sleep Mode
output wire magic_wakeup_21, // Wake Up Request
// RECONFIG BLOCK SIGNALS
input wire reconfig_clk_21, // Clock for reconfiguration block
input wire reconfig_busy_21, // Busy from reconfiguration block
input wire [3:0] reconfig_togxb_21, // Signals from the reconfig block to the GXB block
output wire [16:0] reconfig_fromgxb_21, // Signals from the gxb block to the reconfig block
// CHANNEL 22
// PCS SIGNALS TO PHY
input wire rxp_22, // Differential Receive Data
output wire txp_22, // Differential Transmit Data
input wire gxb_pwrdn_in_22, // Powerdown signal to GXB
output wire pcs_pwrdn_out_22, // Powerdown Enable from PCS
output wire rx_recovclkout_22, // Receiver Recovered Clock
output wire led_crs_22, // Carrier Sense
output wire led_link_22, // Valid Link
output wire led_col_22, // Collision Indication
output wire led_an_22, // Auto-Negotiation Status
output wire led_char_err_22, // Character Error
output wire led_disp_err_22, // Disparity Error
// AV-ST TX & RX
output wire mac_rx_clk_22, // Av-ST Receive Clock
output wire mac_tx_clk_22, // Av-ST Transmit Clock
output wire data_rx_sop_22, // Start of Packet
output wire data_rx_eop_22, // End of Packet
output wire [7:0] data_rx_data_22, // Data from FIFO
output wire [4:0] data_rx_error_22, // Receive packet error
output wire data_rx_valid_22, // Data Receive FIFO Valid
input wire data_rx_ready_22, // Data Receive Ready
output wire [4:0] pkt_class_data_22, // Frame Type Indication
output wire pkt_class_valid_22, // Frame Type Indication Valid
input wire data_tx_error_22, // STATUS FIFO (Tx frame Error from Apps)
input wire [7:0] data_tx_data_22, // Data from FIFO transmit
input wire data_tx_valid_22, // Data FIFO transmit Empty
input wire data_tx_sop_22, // Start of Packet
input wire data_tx_eop_22, // END of Packet
output wire data_tx_ready_22, // Data FIFO transmit Read Enable
// STAND_ALONE CONDUITS
output wire tx_ff_uflow_22, // TX FIFO underflow occured (Synchronous with tx_clk)
input wire tx_crc_fwd_22, // Forward Current Frame with CRC from Application
input wire xoff_gen_22, // Xoff Pause frame generate
input wire xon_gen_22, // Xon Pause frame generate
input wire magic_sleep_n_22, // Enable Sleep Mode
output wire magic_wakeup_22, // Wake Up Request
// RECONFIG BLOCK SIGNALS
input wire reconfig_clk_22, // Clock for reconfiguration block
input wire reconfig_busy_22, // Busy from reconfiguration block
input wire [3:0] reconfig_togxb_22, // Signals from the reconfig block to the GXB block
output wire [16:0] reconfig_fromgxb_22, // Signals from the gxb block to the reconfig block
// CHANNEL 23
// PCS SIGNALS TO PHY
input wire rxp_23, // Differential Receive Data
output wire txp_23, // Differential Transmit Data
input wire gxb_pwrdn_in_23, // Powerdown signal to GXB
output wire pcs_pwrdn_out_23, // Powerdown Enable from PCS
output wire rx_recovclkout_23, // Receiver Recovered Clock
output wire led_crs_23, // Carrier Sense
output wire led_link_23, // Valid Link
output wire led_col_23, // Collision Indication
output wire led_an_23, // Auto-Negotiation Status
output wire led_char_err_23, // Character Error
output wire led_disp_err_23, // Disparity Error
// AV-ST TX & RX
output wire mac_rx_clk_23, // Av-ST Receive Clock
output wire mac_tx_clk_23, // Av-ST Transmit Clock
output wire data_rx_sop_23, // Start of Packet
output wire data_rx_eop_23, // End of Packet
output wire [7:0] data_rx_data_23, // Data from FIFO
output wire [4:0] data_rx_error_23, // Receive packet error
output wire data_rx_valid_23, // Data Receive FIFO Valid
input wire data_rx_ready_23, // Data Receive Ready
output wire [4:0] pkt_class_data_23, // Frame Type Indication
output wire pkt_class_valid_23, // Frame Type Indication Valid
input wire data_tx_error_23, // STATUS FIFO (Tx frame Error from Apps)
input wire [7:0] data_tx_data_23, // Data from FIFO transmit
input wire data_tx_valid_23, // Data FIFO transmit Empty
input wire data_tx_sop_23, // Start of Packet
input wire data_tx_eop_23, // END of Packet
output wire data_tx_ready_23, // Data FIFO transmit Read Enable
// STAND_ALONE CONDUITS
output wire tx_ff_uflow_23, // TX FIFO underflow occured (Synchronous with tx_clk)
input wire tx_crc_fwd_23, // Forward Current Frame with CRC from Application
input wire xoff_gen_23, // Xoff Pause frame generate
input wire xon_gen_23, // Xon Pause frame generate
input wire magic_sleep_n_23, // Enable Sleep Mode
output wire magic_wakeup_23, // Wake Up Request
// RECONFIG BLOCK SIGNALS
input wire reconfig_clk_23, // Clock for reconfiguration block
input wire reconfig_busy_23, // Busy from reconfiguration block
input wire [3:0] reconfig_togxb_23, // Signals from the reconfig block to the GXB block
output wire [16:0] reconfig_fromgxb_23); // Signals from the gxb block to the reconfig block
wire [23:0] pcs_pwrdn_out_sig;
wire [23:0] gxb_pwrdn_in_sig;
wire gige_pma_reset;
wire [23:0] led_char_err_gx;
wire [23:0] link_status;
//wire [23:0] pcs_clk;
wire tx_pcs_clk_c0;
wire tx_pcs_clk_c1;
wire tx_pcs_clk_c2;
wire tx_pcs_clk_c3;
wire tx_pcs_clk_c4;
wire tx_pcs_clk_c5;
wire tx_pcs_clk_c6;
wire tx_pcs_clk_c7;
wire tx_pcs_clk_c8;
wire tx_pcs_clk_c9;
wire tx_pcs_clk_c10;
wire tx_pcs_clk_c11;
wire tx_pcs_clk_c12;
wire tx_pcs_clk_c13;
wire tx_pcs_clk_c14;
wire tx_pcs_clk_c15;
wire tx_pcs_clk_c16;
wire tx_pcs_clk_c17;
wire tx_pcs_clk_c18;
wire tx_pcs_clk_c19;
wire tx_pcs_clk_c20;
wire tx_pcs_clk_c21;
wire tx_pcs_clk_c22;
wire tx_pcs_clk_c23;
wire rx_pcs_clk_c0;
wire rx_pcs_clk_c1;
wire rx_pcs_clk_c2;
wire rx_pcs_clk_c3;
wire rx_pcs_clk_c4;
wire rx_pcs_clk_c5;
wire rx_pcs_clk_c6;
wire rx_pcs_clk_c7;
wire rx_pcs_clk_c8;
wire rx_pcs_clk_c9;
wire rx_pcs_clk_c10;
wire rx_pcs_clk_c11;
wire rx_pcs_clk_c12;
wire rx_pcs_clk_c13;
wire rx_pcs_clk_c14;
wire rx_pcs_clk_c15;
wire rx_pcs_clk_c16;
wire rx_pcs_clk_c17;
wire rx_pcs_clk_c18;
wire rx_pcs_clk_c19;
wire rx_pcs_clk_c20;
wire rx_pcs_clk_c21;
wire rx_pcs_clk_c22;
wire rx_pcs_clk_c23;
wire [23:0] rx_char_err_gx;
wire [23:0] rx_disp_err;
wire [23:0] rx_syncstatus;
wire [23:0] rx_runlengthviolation;
wire [23:0] rx_patterndetect;
wire [23:0] rx_runningdisp;
wire [23:0] rx_rmfifodatadeleted;
wire [23:0] rx_rmfifodatainserted;
wire [23:0] pcs_rx_rmfifodatadeleted;
wire [23:0] pcs_rx_rmfifodatainserted;
wire [23:0] pcs_rx_carrierdetected;
wire rx_kchar_0;
wire [7:0] rx_frame_0;
wire pcs_rx_kchar_0;
wire [7:0] pcs_rx_frame_0;
wire tx_kchar_0;
wire [7:0] tx_frame_0;
wire rx_kchar_1;
wire [7:0] rx_frame_1;
wire pcs_rx_kchar_1;
wire [7:0] pcs_rx_frame_1;
wire tx_kchar_1;
wire [7:0] tx_frame_1;
wire rx_kchar_2;
wire [7:0] rx_frame_2;
wire pcs_rx_kchar_2;
wire [7:0] pcs_rx_frame_2;
wire tx_kchar_2;
wire [7:0] tx_frame_2;
wire rx_kchar_3;
wire [7:0] rx_frame_3;
wire pcs_rx_kchar_3;
wire [7:0] pcs_rx_frame_3;
wire tx_kchar_3;
wire [7:0] tx_frame_3;
wire rx_kchar_4;
wire [7:0] rx_frame_4;
wire pcs_rx_kchar_4;
wire [7:0] pcs_rx_frame_4;
wire tx_kchar_4;
wire [7:0] tx_frame_4;
wire rx_kchar_5;
wire [7:0] rx_frame_5;
wire pcs_rx_kchar_5;
wire [7:0] pcs_rx_frame_5;
wire tx_kchar_5;
wire [7:0] tx_frame_5;
wire rx_kchar_6;
wire [7:0] rx_frame_6;
wire pcs_rx_kchar_6;
wire [7:0] pcs_rx_frame_6;
wire tx_kchar_6;
wire [7:0] tx_frame_6;
wire rx_kchar_7;
wire [7:0] rx_frame_7;
wire pcs_rx_kchar_7;
wire [7:0] pcs_rx_frame_7;
wire tx_kchar_7;
wire [7:0] tx_frame_7;
wire rx_kchar_8;
wire [7:0] rx_frame_8;
wire pcs_rx_kchar_8;
wire [7:0] pcs_rx_frame_8;
wire tx_kchar_8;
wire [7:0] tx_frame_8;
wire rx_kchar_9;
wire [7:0] rx_frame_9;
wire pcs_rx_kchar_9;
wire [7:0] pcs_rx_frame_9;
wire tx_kchar_9;
wire [7:0] tx_frame_9;
wire rx_kchar_10;
wire [7:0] rx_frame_10;
wire pcs_rx_kchar_10;
wire [7:0] pcs_rx_frame_10;
wire tx_kchar_10;
wire [7:0] tx_frame_10;
wire rx_kchar_11;
wire [7:0] rx_frame_11;
wire pcs_rx_kchar_11;
wire [7:0] pcs_rx_frame_11;
wire tx_kchar_11;
wire [7:0] tx_frame_11;
wire rx_kchar_12;
wire [7:0] rx_frame_12;
wire pcs_rx_kchar_12;
wire [7:0] pcs_rx_frame_12;
wire tx_kchar_12;
wire [7:0] tx_frame_12;
wire rx_kchar_13;
wire [7:0] rx_frame_13;
wire pcs_rx_kchar_13;
wire [7:0] pcs_rx_frame_13;
wire tx_kchar_13;
wire [7:0] tx_frame_13;
wire rx_kchar_14;
wire [7:0] rx_frame_14;
wire pcs_rx_kchar_14;
wire [7:0] pcs_rx_frame_14;
wire tx_kchar_14;
wire [7:0] tx_frame_14;
wire rx_kchar_15;
wire [7:0] rx_frame_15;
wire pcs_rx_kchar_15;
wire [7:0] pcs_rx_frame_15;
wire tx_kchar_15;
wire [7:0] tx_frame_15;
wire rx_kchar_16;
wire [7:0] rx_frame_16;
wire pcs_rx_kchar_16;
wire [7:0] pcs_rx_frame_16;
wire tx_kchar_16;
wire [7:0] tx_frame_16;
wire rx_kchar_17;
wire [7:0] rx_frame_17;
wire pcs_rx_kchar_17;
wire [7:0] pcs_rx_frame_17;
wire tx_kchar_17;
wire [7:0] tx_frame_17;
wire rx_kchar_18;
wire [7:0] rx_frame_18;
wire pcs_rx_kchar_18;
wire [7:0] pcs_rx_frame_18;
wire tx_kchar_18;
wire [7:0] tx_frame_18;
wire rx_kchar_19;
wire [7:0] rx_frame_19;
wire pcs_rx_kchar_19;
wire [7:0] pcs_rx_frame_19;
wire tx_kchar_19;
wire [7:0] tx_frame_19;
wire rx_kchar_20;
wire [7:0] rx_frame_20;
wire pcs_rx_kchar_20;
wire [7:0] pcs_rx_frame_20;
wire tx_kchar_20;
wire [7:0] tx_frame_20;
wire rx_kchar_21;
wire [7:0] rx_frame_21;
wire pcs_rx_kchar_21;
wire [7:0] pcs_rx_frame_21;
wire tx_kchar_21;
wire [7:0] tx_frame_21;
wire rx_kchar_22;
wire [7:0] rx_frame_22;
wire pcs_rx_kchar_22;
wire [7:0] pcs_rx_frame_22;
wire tx_kchar_22;
wire [7:0] tx_frame_22;
wire rx_kchar_23;
wire [7:0] rx_frame_23;
wire pcs_rx_kchar_23;
wire [7:0] pcs_rx_frame_23;
wire tx_kchar_23;
wire [7:0] tx_frame_23;
wire sd_loopback_0;
wire sd_loopback_1;
wire sd_loopback_2;
wire sd_loopback_3;
wire sd_loopback_4;
wire sd_loopback_5;
wire sd_loopback_6;
wire sd_loopback_7;
wire sd_loopback_8;
wire sd_loopback_9;
wire sd_loopback_10;
wire sd_loopback_11;
wire sd_loopback_12;
wire sd_loopback_13;
wire sd_loopback_14;
wire sd_loopback_15;
wire sd_loopback_16;
wire sd_loopback_17;
wire sd_loopback_18;
wire sd_loopback_19;
wire sd_loopback_20;
wire sd_loopback_21;
wire sd_loopback_22;
wire sd_loopback_23;
wire reset_rx_pcs_clk_c0_int;
wire reset_rx_pcs_clk_c1_int;
wire reset_rx_pcs_clk_c2_int;
wire reset_rx_pcs_clk_c3_int;
wire reset_rx_pcs_clk_c4_int;
wire reset_rx_pcs_clk_c5_int;
wire reset_rx_pcs_clk_c6_int;
wire reset_rx_pcs_clk_c7_int;
wire reset_rx_pcs_clk_c8_int;
wire reset_rx_pcs_clk_c9_int;
wire reset_rx_pcs_clk_c10_int;
wire reset_rx_pcs_clk_c11_int;
wire reset_rx_pcs_clk_c12_int;
wire reset_rx_pcs_clk_c13_int;
wire reset_rx_pcs_clk_c14_int;
wire reset_rx_pcs_clk_c15_int;
wire reset_rx_pcs_clk_c16_int;
wire reset_rx_pcs_clk_c17_int;
wire reset_rx_pcs_clk_c18_int;
wire reset_rx_pcs_clk_c19_int;
wire reset_rx_pcs_clk_c20_int;
wire reset_rx_pcs_clk_c21_int;
wire reset_rx_pcs_clk_c22_int;
wire reset_rx_pcs_clk_c23_int;
wire pll_powerdown_sqcnr_0,tx_digitalreset_sqcnr_0,rx_analogreset_sqcnr_0,rx_digitalreset_sqcnr_0,gxb_powerdown_sqcnr_0,pll_locked_0,rx_freqlocked_0;
wire pll_powerdown_sqcnr_1,tx_digitalreset_sqcnr_1,rx_analogreset_sqcnr_1,rx_digitalreset_sqcnr_1,gxb_powerdown_sqcnr_1,pll_locked_1,rx_freqlocked_1;
wire pll_powerdown_sqcnr_2,tx_digitalreset_sqcnr_2,rx_analogreset_sqcnr_2,rx_digitalreset_sqcnr_2,gxb_powerdown_sqcnr_2,pll_locked_2,rx_freqlocked_2;
wire pll_powerdown_sqcnr_3,tx_digitalreset_sqcnr_3,rx_analogreset_sqcnr_3,rx_digitalreset_sqcnr_3,gxb_powerdown_sqcnr_3,pll_locked_3,rx_freqlocked_3;
wire pll_powerdown_sqcnr_4,tx_digitalreset_sqcnr_4,rx_analogreset_sqcnr_4,rx_digitalreset_sqcnr_4,gxb_powerdown_sqcnr_4,pll_locked_4,rx_freqlocked_4;
wire pll_powerdown_sqcnr_5,tx_digitalreset_sqcnr_5,rx_analogreset_sqcnr_5,rx_digitalreset_sqcnr_5,gxb_powerdown_sqcnr_5,pll_locked_5,rx_freqlocked_5;
wire pll_powerdown_sqcnr_6,tx_digitalreset_sqcnr_6,rx_analogreset_sqcnr_6,rx_digitalreset_sqcnr_6,gxb_powerdown_sqcnr_6,pll_locked_6,rx_freqlocked_6;
wire pll_powerdown_sqcnr_7,tx_digitalreset_sqcnr_7,rx_analogreset_sqcnr_7,rx_digitalreset_sqcnr_7,gxb_powerdown_sqcnr_7,pll_locked_7,rx_freqlocked_7;
wire pll_powerdown_sqcnr_8,tx_digitalreset_sqcnr_8,rx_analogreset_sqcnr_8,rx_digitalreset_sqcnr_8,gxb_powerdown_sqcnr_8,pll_locked_8,rx_freqlocked_8;
wire pll_powerdown_sqcnr_9,tx_digitalreset_sqcnr_9,rx_analogreset_sqcnr_9,rx_digitalreset_sqcnr_9,gxb_powerdown_sqcnr_9,pll_locked_9,rx_freqlocked_9;
wire pll_powerdown_sqcnr_10,tx_digitalreset_sqcnr_10,rx_analogreset_sqcnr_10,rx_digitalreset_sqcnr_10,gxb_powerdown_sqcnr_10,pll_locked_10,rx_freqlocked_10;
wire pll_powerdown_sqcnr_11,tx_digitalreset_sqcnr_11,rx_analogreset_sqcnr_11,rx_digitalreset_sqcnr_11,gxb_powerdown_sqcnr_11,pll_locked_11,rx_freqlocked_11;
wire pll_powerdown_sqcnr_12,tx_digitalreset_sqcnr_12,rx_analogreset_sqcnr_12,rx_digitalreset_sqcnr_12,gxb_powerdown_sqcnr_12,pll_locked_12,rx_freqlocked_12;
wire pll_powerdown_sqcnr_13,tx_digitalreset_sqcnr_13,rx_analogreset_sqcnr_13,rx_digitalreset_sqcnr_13,gxb_powerdown_sqcnr_13,pll_locked_13,rx_freqlocked_13;
wire pll_powerdown_sqcnr_14,tx_digitalreset_sqcnr_14,rx_analogreset_sqcnr_14,rx_digitalreset_sqcnr_14,gxb_powerdown_sqcnr_14,pll_locked_14,rx_freqlocked_14;
wire pll_powerdown_sqcnr_15,tx_digitalreset_sqcnr_15,rx_analogreset_sqcnr_15,rx_digitalreset_sqcnr_15,gxb_powerdown_sqcnr_15,pll_locked_15,rx_freqlocked_15;
wire pll_powerdown_sqcnr_16,tx_digitalreset_sqcnr_16,rx_analogreset_sqcnr_16,rx_digitalreset_sqcnr_16,gxb_powerdown_sqcnr_16,pll_locked_16,rx_freqlocked_16;
wire pll_powerdown_sqcnr_17,tx_digitalreset_sqcnr_17,rx_analogreset_sqcnr_17,rx_digitalreset_sqcnr_17,gxb_powerdown_sqcnr_17,pll_locked_17,rx_freqlocked_17;
wire pll_powerdown_sqcnr_18,tx_digitalreset_sqcnr_18,rx_analogreset_sqcnr_18,rx_digitalreset_sqcnr_18,gxb_powerdown_sqcnr_18,pll_locked_18,rx_freqlocked_18;
wire pll_powerdown_sqcnr_19,tx_digitalreset_sqcnr_19,rx_analogreset_sqcnr_19,rx_digitalreset_sqcnr_19,gxb_powerdown_sqcnr_19,pll_locked_19,rx_freqlocked_19;
wire pll_powerdown_sqcnr_20,tx_digitalreset_sqcnr_20,rx_analogreset_sqcnr_20,rx_digitalreset_sqcnr_20,gxb_powerdown_sqcnr_20,pll_locked_20,rx_freqlocked_20;
wire pll_powerdown_sqcnr_21,tx_digitalreset_sqcnr_21,rx_analogreset_sqcnr_21,rx_digitalreset_sqcnr_21,gxb_powerdown_sqcnr_21,pll_locked_21,rx_freqlocked_21;
wire pll_powerdown_sqcnr_22,tx_digitalreset_sqcnr_22,rx_analogreset_sqcnr_22,rx_digitalreset_sqcnr_22,gxb_powerdown_sqcnr_22,pll_locked_22,rx_freqlocked_22;
wire pll_powerdown_sqcnr_23,tx_digitalreset_sqcnr_23,rx_analogreset_sqcnr_23,rx_digitalreset_sqcnr_23,gxb_powerdown_sqcnr_23,pll_locked_23,rx_freqlocked_23;
// Assign pcs clock for all channels
//assign pcs_clk = {pcs_clk_c23,pcs_clk_c22,pcs_clk_c21,pcs_clk_c20,pcs_clk_c19,pcs_clk_c18,pcs_clk_c17,pcs_clk_c16,pcs_clk_c15,pcs_clk_c14,pcs_clk_c13,pcs_clk_c12,pcs_clk_c11,pcs_clk_c10,pcs_clk_c9,pcs_clk_c8,pcs_clk_c7,pcs_clk_c6,pcs_clk_c5,pcs_clk_c4,pcs_clk_c3,pcs_clk_c2,pcs_clk_c1,pcs_clk_c0};
// Assign the character error and link status to top level leds
// ------------------------------------------------------------
assign led_char_err_0 = led_char_err_gx[0];
assign led_link_0 = link_status[0];
assign led_char_err_1 = led_char_err_gx[1];
assign led_link_1 = link_status[1];
assign led_char_err_2 = led_char_err_gx[2];
assign led_link_2 = link_status[2];
assign led_char_err_3 = led_char_err_gx[3];
assign led_link_3 = link_status[3];
assign led_char_err_4 = led_char_err_gx[4];
assign led_link_4 = link_status[4];
assign led_char_err_5 = led_char_err_gx[5];
assign led_link_5 = link_status[5];
assign led_char_err_6 = led_char_err_gx[6];
assign led_link_6 = link_status[6];
assign led_char_err_7 = led_char_err_gx[7];
assign led_link_7 = link_status[7];
assign led_char_err_8 = led_char_err_gx[8];
assign led_link_8 = link_status[8];
assign led_char_err_9 = led_char_err_gx[9];
assign led_link_9 = link_status[9];
assign led_char_err_10 = led_char_err_gx[10];
assign led_link_10 = link_status[10];
assign led_char_err_11 = led_char_err_gx[11];
assign led_link_11 = link_status[11];
assign led_char_err_12 = led_char_err_gx[12];
assign led_link_12 = link_status[12];
assign led_char_err_13 = led_char_err_gx[13];
assign led_link_13 = link_status[13];
assign led_char_err_14 = led_char_err_gx[14];
assign led_link_14 = link_status[14];
assign led_char_err_15 = led_char_err_gx[15];
assign led_link_15 = link_status[15];
assign led_char_err_16 = led_char_err_gx[16];
assign led_link_16 = link_status[16];
assign led_char_err_17 = led_char_err_gx[17];
assign led_link_17 = link_status[17];
assign led_char_err_18 = led_char_err_gx[18];
assign led_link_18 = link_status[18];
assign led_char_err_19 = led_char_err_gx[19];
assign led_link_19 = link_status[19];
assign led_char_err_20 = led_char_err_gx[20];
assign led_link_20 = link_status[20];
assign led_char_err_21 = led_char_err_gx[21];
assign led_link_21 = link_status[21];
assign led_char_err_22 = led_char_err_gx[22];
assign led_link_22 = link_status[22];
assign led_char_err_23 = led_char_err_gx[23];
assign led_link_23 = link_status[23];
//Resets the Reset Sequencer for the rising edge of Reset signal
// ---------------------------------------------------------------
reg reset_p1, reset_p2;
reg reset_posedge;
always@(posedge clk)
begin
reset_p1 <= reset;
reset_p2 <= reset_p1;
reset_posedge <= reset_p1 & ~reset_p2;
end
// Instantiation of the MAC_PCS core that connects to a PMA
// --------------------------------------------------------
altera_tse_top_multi_mac_pcs_gige U_MULTI_MAC_PCS(
.reset(reset), //INPUT : ASYNCHRONOUS RESET - clk DOMAIN
.clk(clk), //INPUT : CLOCK
.read(read), //INPUT : REGISTER READ TRANSACTION
.ref_clk(ref_clk), //INPUT : REFERENCE CLOCK
.write(write), //INPUT : REGISTER WRITE TRANSACTION
.address(address), //INPUT : REGISTER ADDRESS
.writedata(writedata), //INPUT : REGISTER WRITE DATA
.readdata(readdata), //OUTPUT : REGISTER READ DATA
.waitrequest(waitrequest), //OUTPUT : TRANSACTION BUSY, ACTIVE LOW
.mdc(mdc), //OUTPUT : MDIO Clock
.mdio_out(mdio_out), //OUTPUT : Outgoing MDIO DATA
.mdio_in(mdio_in), //INPUT : Incoming MDIO DATA
.mdio_oen(mdio_oen), //OUTPUT : MDIO Output Enable
.mac_rx_clk(mac_rx_clk), //OUTPUT : Av-ST Rx Clock
.mac_tx_clk(mac_tx_clk), //OUTPUT : Av-ST Tx Clock
.rx_afull_clk(rx_afull_clk), //INPUT : AFull Status Clock
.rx_afull_data(rx_afull_data), //INPUT : AFull Status Data
.rx_afull_valid(rx_afull_valid), //INPUT : AFull Status Valid
.rx_afull_channel(rx_afull_channel), //INPUT : AFull Status Channel
// Channel 0
.rx_carrierdetected_0(pcs_rx_carrierdetected[0]),
.rx_rmfifodatadeleted_0(pcs_rx_rmfifodatadeleted[0]),
.rx_rmfifodatainserted_0(pcs_rx_rmfifodatainserted[0]),
.rx_clkout_0(rx_pcs_clk_c0), //INPUT : Receive Clock
.tx_clkout_0(tx_pcs_clk_c0), //INPUT : Transmit Clock
.rx_kchar_0(pcs_rx_kchar_0), //INPUT : Special Character Indication
.tx_kchar_0(tx_kchar_0), //OUTPUT : Special Character Indication
.rx_frame_0(pcs_rx_frame_0), //INPUT : Frame
.tx_frame_0(tx_frame_0), //OUTPUT : Frame
.sd_loopback_0(sd_loopback_0), //OUTPUT : SERDES Loopback Enable
.powerdown_0(pcs_pwrdn_out_sig[0]), //OUTPUT : Powerdown Enable
.led_col_0(led_col_0), //OUTPUT : Collision Indication
.led_an_0(led_an_0), //OUTPUT : Auto Negotiation Status
.led_char_err_0(led_char_err_gx[0]), //INPUT : Character error
.led_crs_0(led_crs_0), //OUTPUT : Carrier sense
.led_link_0(link_status[0]), //INPUT : Valid link
.mac_rx_clk_0(mac_rx_clk_0), //OUTPUT : Av-ST Rx Clock
.mac_tx_clk_0(mac_tx_clk_0), //OUTPUT : Av-ST Tx Clock
.data_rx_sop_0(data_rx_sop_0), //OUTPUT : Start of Packet
.data_rx_eop_0(data_rx_eop_0), //OUTPUT : End of Packet
.data_rx_data_0(data_rx_data_0), //OUTPUT : Data from FIFO
.data_rx_error_0(data_rx_error_0), //OUTPUT : Receive packet error
.data_rx_valid_0(data_rx_valid_0), //OUTPUT : Data Receive FIFO Valid
.data_rx_ready_0(data_rx_ready_0), //OUTPUT : Data Receive Ready
.pkt_class_data_0(pkt_class_data_0), //OUTPUT : Frame Type Indication
.pkt_class_valid_0(pkt_class_valid_0), //OUTPUT : Frame Type Indication Valid
.data_tx_error_0(data_tx_error_0), //INPUT : Status
.data_tx_data_0(data_tx_data_0), //INPUT : Data from FIFO transmit
.data_tx_valid_0(data_tx_valid_0), //INPUT : Data FIFO transmit Empty
.data_tx_sop_0(data_tx_sop_0), //INPUT : Start of Packet
.data_tx_eop_0(data_tx_eop_0), //INPUT : End of Packet
.data_tx_ready_0(data_tx_ready_0), //OUTPUT : Data FIFO transmit Read Enable
.tx_ff_uflow_0(tx_ff_uflow_0), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
.tx_crc_fwd_0(tx_crc_fwd_0), //INPUT : Forward Current Frame with CRC from Application
.xoff_gen_0(xoff_gen_0), //INPUT : XOFF PAUSE FRAME GENERATE
.xon_gen_0(xon_gen_0), //INPUT : XON PAUSE FRAME GENERATE
.magic_sleep_n_0(magic_sleep_n_0), //INPUT : MAC SLEEP MODE CONTROL
.magic_wakeup_0(magic_wakeup_0), //OUTPUT : MAC WAKE-UP INDICATION
// Channel 1
.rx_carrierdetected_1(pcs_rx_carrierdetected[1]),
.rx_rmfifodatadeleted_1(pcs_rx_rmfifodatadeleted[1]),
.rx_rmfifodatainserted_1(pcs_rx_rmfifodatainserted[1]),
.rx_clkout_1(rx_pcs_clk_c1), //INPUT : Receive Clock
.tx_clkout_1(tx_pcs_clk_c1), //INPUT : Transmit Clock
.rx_kchar_1(pcs_rx_kchar_1), //INPUT : Special Character Indication
.tx_kchar_1(tx_kchar_1), //OUTPUT : Special Character Indication
.rx_frame_1(pcs_rx_frame_1), //INPUT : Frame
.tx_frame_1(tx_frame_1), //OUTPUT : Frame
.sd_loopback_1(sd_loopback_1), //OUTPUT : SERDES Loopback Enable
.powerdown_1(pcs_pwrdn_out_sig[1]), //OUTPUT : Powerdown Enable
.led_col_1(led_col_1), //OUTPUT : Collision Indication
.led_an_1(led_an_1), //OUTPUT : Auto Negotiation Status
.led_char_err_1(led_char_err_gx[1]), //INPUT : Character error
.led_crs_1(led_crs_1), //OUTPUT : Carrier sense
.led_link_1(link_status[1]), //INPUT : Valid link
.mac_rx_clk_1(mac_rx_clk_1), //OUTPUT : Av-ST Rx Clock
.mac_tx_clk_1(mac_tx_clk_1), //OUTPUT : Av-ST Tx Clock
.data_rx_sop_1(data_rx_sop_1), //OUTPUT : Start of Packet
.data_rx_eop_1(data_rx_eop_1), //OUTPUT : End of Packet
.data_rx_data_1(data_rx_data_1), //OUTPUT : Data from FIFO
.data_rx_error_1(data_rx_error_1), //OUTPUT : Receive packet error
.data_rx_valid_1(data_rx_valid_1), //OUTPUT : Data Receive FIFO Valid
.data_rx_ready_1(data_rx_ready_1), //OUTPUT : Data Receive Ready
.pkt_class_data_1(pkt_class_data_1), //OUTPUT : Frame Type Indication
.pkt_class_valid_1(pkt_class_valid_1), //OUTPUT : Frame Type Indication Valid
.data_tx_error_1(data_tx_error_1), //INPUT : Status
.data_tx_data_1(data_tx_data_1), //INPUT : Data from FIFO transmit
.data_tx_valid_1(data_tx_valid_1), //INPUT : Data FIFO transmit Empty
.data_tx_sop_1(data_tx_sop_1), //INPUT : Start of Packet
.data_tx_eop_1(data_tx_eop_1), //INPUT : End of Packet
.data_tx_ready_1(data_tx_ready_1), //OUTPUT : Data FIFO transmit Read Enable
.tx_ff_uflow_1(tx_ff_uflow_1), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
.tx_crc_fwd_1(tx_crc_fwd_1), //INPUT : Forward Current Frame with CRC from Application
.xoff_gen_1(xoff_gen_1), //INPUT : XOFF PAUSE FRAME GENERATE
.xon_gen_1(xon_gen_1), //INPUT : XON PAUSE FRAME GENERATE
.magic_sleep_n_1(magic_sleep_n_1), //INPUT : MAC SLEEP MODE CONTROL
.magic_wakeup_1(magic_wakeup_1), //OUTPUT : MAC WAKE-UP INDICATION
// Channel 2
.rx_carrierdetected_2(pcs_rx_carrierdetected[2]),
.rx_rmfifodatadeleted_2(pcs_rx_rmfifodatadeleted[2]),
.rx_rmfifodatainserted_2(pcs_rx_rmfifodatainserted[2]),
.rx_clkout_2(rx_pcs_clk_c2), //INPUT : Receive Clock
.tx_clkout_2(tx_pcs_clk_c2), //INPUT : Transmit Clock
.rx_kchar_2(pcs_rx_kchar_2), //INPUT : Special Character Indication
.tx_kchar_2(tx_kchar_2), //OUTPUT : Special Character Indication
.rx_frame_2(pcs_rx_frame_2), //INPUT : Frame
.tx_frame_2(tx_frame_2), //OUTPUT : Frame
.sd_loopback_2(sd_loopback_2), //OUTPUT : SERDES Loopback Enable
.powerdown_2(pcs_pwrdn_out_sig[2]), //OUTPUT : Powerdown Enable
.led_col_2(led_col_2), //OUTPUT : Collision Indication
.led_an_2(led_an_2), //OUTPUT : Auto Negotiation Status
.led_char_err_2(led_char_err_gx[2]), //INPUT : Character error
.led_crs_2(led_crs_2), //OUTPUT : Carrier sense
.led_link_2(link_status[2]), //INPUT : Valid link
.mac_rx_clk_2(mac_rx_clk_2), //OUTPUT : Av-ST Rx Clock
.mac_tx_clk_2(mac_tx_clk_2), //OUTPUT : Av-ST Tx Clock
.data_rx_sop_2(data_rx_sop_2), //OUTPUT : Start of Packet
.data_rx_eop_2(data_rx_eop_2), //OUTPUT : End of Packet
.data_rx_data_2(data_rx_data_2), //OUTPUT : Data from FIFO
.data_rx_error_2(data_rx_error_2), //OUTPUT : Receive packet error
.data_rx_valid_2(data_rx_valid_2), //OUTPUT : Data Receive FIFO Valid
.data_rx_ready_2(data_rx_ready_2), //OUTPUT : Data Receive Ready
.pkt_class_data_2(pkt_class_data_2), //OUTPUT : Frame Type Indication
.pkt_class_valid_2(pkt_class_valid_2), //OUTPUT : Frame Type Indication Valid
.data_tx_error_2(data_tx_error_2), //INPUT : Status
.data_tx_data_2(data_tx_data_2), //INPUT : Data from FIFO transmit
.data_tx_valid_2(data_tx_valid_2), //INPUT : Data FIFO transmit Empty
.data_tx_sop_2(data_tx_sop_2), //INPUT : Start of Packet
.data_tx_eop_2(data_tx_eop_2), //INPUT : End of Packet
.data_tx_ready_2(data_tx_ready_2), //OUTPUT : Data FIFO transmit Read Enable
.tx_ff_uflow_2(tx_ff_uflow_2), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
.tx_crc_fwd_2(tx_crc_fwd_2), //INPUT : Forward Current Frame with CRC from Application
.xoff_gen_2(xoff_gen_2), //INPUT : XOFF PAUSE FRAME GENERATE
.xon_gen_2(xon_gen_2), //INPUT : XON PAUSE FRAME GENERATE
.magic_sleep_n_2(magic_sleep_n_2), //INPUT : MAC SLEEP MODE CONTROL
.magic_wakeup_2(magic_wakeup_2), //OUTPUT : MAC WAKE-UP INDICATION
// Channel 3
.rx_carrierdetected_3(pcs_rx_carrierdetected[3]),
.rx_rmfifodatadeleted_3(pcs_rx_rmfifodatadeleted[3]),
.rx_rmfifodatainserted_3(pcs_rx_rmfifodatainserted[3]),
.rx_clkout_3(rx_pcs_clk_c3), //INPUT : Receive Clock
.tx_clkout_3(tx_pcs_clk_c3), //INPUT : Transmit Clock
.rx_kchar_3(pcs_rx_kchar_3), //INPUT : Special Character Indication
.tx_kchar_3(tx_kchar_3), //OUTPUT : Special Character Indication
.rx_frame_3(pcs_rx_frame_3), //INPUT : Frame
.tx_frame_3(tx_frame_3), //OUTPUT : Frame
.sd_loopback_3(sd_loopback_3), //OUTPUT : SERDES Loopback Enable
.powerdown_3(pcs_pwrdn_out_sig[3]), //OUTPUT : Powerdown Enable
.led_col_3(led_col_3), //OUTPUT : Collision Indication
.led_an_3(led_an_3), //OUTPUT : Auto Negotiation Status
.led_char_err_3(led_char_err_gx[3]), //INPUT : Character error
.led_crs_3(led_crs_3), //OUTPUT : Carrier sense
.led_link_3(link_status[3]), //INPUT : Valid link
.mac_rx_clk_3(mac_rx_clk_3), //OUTPUT : Av-ST Rx Clock
.mac_tx_clk_3(mac_tx_clk_3), //OUTPUT : Av-ST Tx Clock
.data_rx_sop_3(data_rx_sop_3), //OUTPUT : Start of Packet
.data_rx_eop_3(data_rx_eop_3), //OUTPUT : End of Packet
.data_rx_data_3(data_rx_data_3), //OUTPUT : Data from FIFO
.data_rx_error_3(data_rx_error_3), //OUTPUT : Receive packet error
.data_rx_valid_3(data_rx_valid_3), //OUTPUT : Data Receive FIFO Valid
.data_rx_ready_3(data_rx_ready_3), //OUTPUT : Data Receive Ready
.pkt_class_data_3(pkt_class_data_3), //OUTPUT : Frame Type Indication
.pkt_class_valid_3(pkt_class_valid_3), //OUTPUT : Frame Type Indication Valid
.data_tx_error_3(data_tx_error_3), //INPUT : Status
.data_tx_data_3(data_tx_data_3), //INPUT : Data from FIFO transmit
.data_tx_valid_3(data_tx_valid_3), //INPUT : Data FIFO transmit Empty
.data_tx_sop_3(data_tx_sop_3), //INPUT : Start of Packet
.data_tx_eop_3(data_tx_eop_3), //INPUT : End of Packet
.data_tx_ready_3(data_tx_ready_3), //OUTPUT : Data FIFO transmit Read Enable
.tx_ff_uflow_3(tx_ff_uflow_3), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
.tx_crc_fwd_3(tx_crc_fwd_3), //INPUT : Forward Current Frame with CRC from Application
.xoff_gen_3(xoff_gen_3), //INPUT : XOFF PAUSE FRAME GENERATE
.xon_gen_3(xon_gen_3), //INPUT : XON PAUSE FRAME GENERATE
.magic_sleep_n_3(magic_sleep_n_3), //INPUT : MAC SLEEP MODE CONTROL
.magic_wakeup_3(magic_wakeup_3), //OUTPUT : MAC WAKE-UP INDICATION
// Channel 4
.rx_carrierdetected_4(pcs_rx_carrierdetected[4]),
.rx_rmfifodatadeleted_4(pcs_rx_rmfifodatadeleted[4]),
.rx_rmfifodatainserted_4(pcs_rx_rmfifodatainserted[4]),
.rx_clkout_4(rx_pcs_clk_c4), //INPUT : Receive Clock
.tx_clkout_4(tx_pcs_clk_c4), //INPUT : Transmit Clock
.rx_kchar_4(pcs_rx_kchar_4), //INPUT : Special Character Indication
.tx_kchar_4(tx_kchar_4), //OUTPUT : Special Character Indication
.rx_frame_4(pcs_rx_frame_4), //INPUT : Frame
.tx_frame_4(tx_frame_4), //OUTPUT : Frame
.sd_loopback_4(sd_loopback_4), //OUTPUT : SERDES Loopback Enable
.powerdown_4(pcs_pwrdn_out_sig[4]), //OUTPUT : Powerdown Enable
.led_col_4(led_col_4), //OUTPUT : Collision Indication
.led_an_4(led_an_4), //OUTPUT : Auto Negotiation Status
.led_char_err_4(led_char_err_gx[4]), //INPUT : Character error
.led_crs_4(led_crs_4), //OUTPUT : Carrier sense
.led_link_4(link_status[4]), //INPUT : Valid link
.mac_rx_clk_4(mac_rx_clk_4), //OUTPUT : Av-ST Rx Clock
.mac_tx_clk_4(mac_tx_clk_4), //OUTPUT : Av-ST Tx Clock
.data_rx_sop_4(data_rx_sop_4), //OUTPUT : Start of Packet
.data_rx_eop_4(data_rx_eop_4), //OUTPUT : End of Packet
.data_rx_data_4(data_rx_data_4), //OUTPUT : Data from FIFO
.data_rx_error_4(data_rx_error_4), //OUTPUT : Receive packet error
.data_rx_valid_4(data_rx_valid_4), //OUTPUT : Data Receive FIFO Valid
.data_rx_ready_4(data_rx_ready_4), //OUTPUT : Data Receive Ready
.pkt_class_data_4(pkt_class_data_4), //OUTPUT : Frame Type Indication
.pkt_class_valid_4(pkt_class_valid_4), //OUTPUT : Frame Type Indication Valid
.data_tx_error_4(data_tx_error_4), //INPUT : Status
.data_tx_data_4(data_tx_data_4), //INPUT : Data from FIFO transmit
.data_tx_valid_4(data_tx_valid_4), //INPUT : Data FIFO transmit Empty
.data_tx_sop_4(data_tx_sop_4), //INPUT : Start of Packet
.data_tx_eop_4(data_tx_eop_4), //INPUT : End of Packet
.data_tx_ready_4(data_tx_ready_4), //OUTPUT : Data FIFO transmit Read Enable
.tx_ff_uflow_4(tx_ff_uflow_4), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
.tx_crc_fwd_4(tx_crc_fwd_4), //INPUT : Forward Current Frame with CRC from Application
.xoff_gen_4(xoff_gen_4), //INPUT : XOFF PAUSE FRAME GENERATE
.xon_gen_4(xon_gen_4), //INPUT : XON PAUSE FRAME GENERATE
.magic_sleep_n_4(magic_sleep_n_4), //INPUT : MAC SLEEP MODE CONTROL
.magic_wakeup_4(magic_wakeup_4), //OUTPUT : MAC WAKE-UP INDICATION
// Channel 5
.rx_carrierdetected_5(pcs_rx_carrierdetected[5]),
.rx_rmfifodatadeleted_5(pcs_rx_rmfifodatadeleted[5]),
.rx_rmfifodatainserted_5(pcs_rx_rmfifodatainserted[5]),
.rx_clkout_5(rx_pcs_clk_c5), //INPUT : Receive Clock
.tx_clkout_5(tx_pcs_clk_c5), //INPUT : Transmit Clock
.rx_kchar_5(pcs_rx_kchar_5), //INPUT : Special Character Indication
.tx_kchar_5(tx_kchar_5), //OUTPUT : Special Character Indication
.rx_frame_5(pcs_rx_frame_5), //INPUT : Frame
.tx_frame_5(tx_frame_5), //OUTPUT : Frame
.sd_loopback_5(sd_loopback_5), //OUTPUT : SERDES Loopback Enable
.powerdown_5(pcs_pwrdn_out_sig[5]), //OUTPUT : Powerdown Enable
.led_col_5(led_col_5), //OUTPUT : Collision Indication
.led_an_5(led_an_5), //OUTPUT : Auto Negotiation Status
.led_char_err_5(led_char_err_gx[5]), //INPUT : Character error
.led_crs_5(led_crs_5), //OUTPUT : Carrier sense
.led_link_5(link_status[5]), //INPUT : Valid link
.mac_rx_clk_5(mac_rx_clk_5), //OUTPUT : Av-ST Rx Clock
.mac_tx_clk_5(mac_tx_clk_5), //OUTPUT : Av-ST Tx Clock
.data_rx_sop_5(data_rx_sop_5), //OUTPUT : Start of Packet
.data_rx_eop_5(data_rx_eop_5), //OUTPUT : End of Packet
.data_rx_data_5(data_rx_data_5), //OUTPUT : Data from FIFO
.data_rx_error_5(data_rx_error_5), //OUTPUT : Receive packet error
.data_rx_valid_5(data_rx_valid_5), //OUTPUT : Data Receive FIFO Valid
.data_rx_ready_5(data_rx_ready_5), //OUTPUT : Data Receive Ready
.pkt_class_data_5(pkt_class_data_5), //OUTPUT : Frame Type Indication
.pkt_class_valid_5(pkt_class_valid_5), //OUTPUT : Frame Type Indication Valid
.data_tx_error_5(data_tx_error_5), //INPUT : Status
.data_tx_data_5(data_tx_data_5), //INPUT : Data from FIFO transmit
.data_tx_valid_5(data_tx_valid_5), //INPUT : Data FIFO transmit Empty
.data_tx_sop_5(data_tx_sop_5), //INPUT : Start of Packet
.data_tx_eop_5(data_tx_eop_5), //INPUT : End of Packet
.data_tx_ready_5(data_tx_ready_5), //OUTPUT : Data FIFO transmit Read Enable
.tx_ff_uflow_5(tx_ff_uflow_5), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
.tx_crc_fwd_5(tx_crc_fwd_5), //INPUT : Forward Current Frame with CRC from Application
.xoff_gen_5(xoff_gen_5), //INPUT : XOFF PAUSE FRAME GENERATE
.xon_gen_5(xon_gen_5), //INPUT : XON PAUSE FRAME GENERATE
.magic_sleep_n_5(magic_sleep_n_5), //INPUT : MAC SLEEP MODE CONTROL
.magic_wakeup_5(magic_wakeup_5), //OUTPUT : MAC WAKE-UP INDICATION
// Channel 6
.rx_carrierdetected_6(pcs_rx_carrierdetected[6]),
.rx_rmfifodatadeleted_6(pcs_rx_rmfifodatadeleted[6]),
.rx_rmfifodatainserted_6(pcs_rx_rmfifodatainserted[6]),
.rx_clkout_6(rx_pcs_clk_c6), //INPUT : Receive Clock
.tx_clkout_6(tx_pcs_clk_c6), //INPUT : Transmit Clock
.rx_kchar_6(pcs_rx_kchar_6), //INPUT : Special Character Indication
.tx_kchar_6(tx_kchar_6), //OUTPUT : Special Character Indication
.rx_frame_6(pcs_rx_frame_6), //INPUT : Frame
.tx_frame_6(tx_frame_6), //OUTPUT : Frame
.sd_loopback_6(sd_loopback_6), //OUTPUT : SERDES Loopback Enable
.powerdown_6(pcs_pwrdn_out_sig[6]), //OUTPUT : Powerdown Enable
.led_col_6(led_col_6), //OUTPUT : Collision Indication
.led_an_6(led_an_6), //OUTPUT : Auto Negotiation Status
.led_char_err_6(led_char_err_gx[6]), //INPUT : Character error
.led_crs_6(led_crs_6), //OUTPUT : Carrier sense
.led_link_6(link_status[6]), //INPUT : Valid link
.mac_rx_clk_6(mac_rx_clk_6), //OUTPUT : Av-ST Rx Clock
.mac_tx_clk_6(mac_tx_clk_6), //OUTPUT : Av-ST Tx Clock
.data_rx_sop_6(data_rx_sop_6), //OUTPUT : Start of Packet
.data_rx_eop_6(data_rx_eop_6), //OUTPUT : End of Packet
.data_rx_data_6(data_rx_data_6), //OUTPUT : Data from FIFO
.data_rx_error_6(data_rx_error_6), //OUTPUT : Receive packet error
.data_rx_valid_6(data_rx_valid_6), //OUTPUT : Data Receive FIFO Valid
.data_rx_ready_6(data_rx_ready_6), //OUTPUT : Data Receive Ready
.pkt_class_data_6(pkt_class_data_6), //OUTPUT : Frame Type Indication
.pkt_class_valid_6(pkt_class_valid_6), //OUTPUT : Frame Type Indication Valid
.data_tx_error_6(data_tx_error_6), //INPUT : Status
.data_tx_data_6(data_tx_data_6), //INPUT : Data from FIFO transmit
.data_tx_valid_6(data_tx_valid_6), //INPUT : Data FIFO transmit Empty
.data_tx_sop_6(data_tx_sop_6), //INPUT : Start of Packet
.data_tx_eop_6(data_tx_eop_6), //INPUT : End of Packet
.data_tx_ready_6(data_tx_ready_6), //OUTPUT : Data FIFO transmit Read Enable
.tx_ff_uflow_6(tx_ff_uflow_6), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
.tx_crc_fwd_6(tx_crc_fwd_6), //INPUT : Forward Current Frame with CRC from Application
.xoff_gen_6(xoff_gen_6), //INPUT : XOFF PAUSE FRAME GENERATE
.xon_gen_6(xon_gen_6), //INPUT : XON PAUSE FRAME GENERATE
.magic_sleep_n_6(magic_sleep_n_6), //INPUT : MAC SLEEP MODE CONTROL
.magic_wakeup_6(magic_wakeup_6), //OUTPUT : MAC WAKE-UP INDICATION
// Channel 7
.rx_carrierdetected_7(pcs_rx_carrierdetected[7]),
.rx_rmfifodatadeleted_7(pcs_rx_rmfifodatadeleted[7]),
.rx_rmfifodatainserted_7(pcs_rx_rmfifodatainserted[7]),
.rx_clkout_7(rx_pcs_clk_c7), //INPUT : Receive Clock
.tx_clkout_7(tx_pcs_clk_c7), //INPUT : Transmit Clock
.rx_kchar_7(pcs_rx_kchar_7), //INPUT : Special Character Indication
.tx_kchar_7(tx_kchar_7), //OUTPUT : Special Character Indication
.rx_frame_7(pcs_rx_frame_7), //INPUT : Frame
.tx_frame_7(tx_frame_7), //OUTPUT : Frame
.sd_loopback_7(sd_loopback_7), //OUTPUT : SERDES Loopback Enable
.powerdown_7(pcs_pwrdn_out_sig[7]), //OUTPUT : Powerdown Enable
.led_col_7(led_col_7), //OUTPUT : Collision Indication
.led_an_7(led_an_7), //OUTPUT : Auto Negotiation Status
.led_char_err_7(led_char_err_gx[7]), //INPUT : Character error
.led_crs_7(led_crs_7), //OUTPUT : Carrier sense
.led_link_7(link_status[7]), //INPUT : Valid link
.mac_rx_clk_7(mac_rx_clk_7), //OUTPUT : Av-ST Rx Clock
.mac_tx_clk_7(mac_tx_clk_7), //OUTPUT : Av-ST Tx Clock
.data_rx_sop_7(data_rx_sop_7), //OUTPUT : Start of Packet
.data_rx_eop_7(data_rx_eop_7), //OUTPUT : End of Packet
.data_rx_data_7(data_rx_data_7), //OUTPUT : Data from FIFO
.data_rx_error_7(data_rx_error_7), //OUTPUT : Receive packet error
.data_rx_valid_7(data_rx_valid_7), //OUTPUT : Data Receive FIFO Valid
.data_rx_ready_7(data_rx_ready_7), //OUTPUT : Data Receive Ready
.pkt_class_data_7(pkt_class_data_7), //OUTPUT : Frame Type Indication
.pkt_class_valid_7(pkt_class_valid_7), //OUTPUT : Frame Type Indication Valid
.data_tx_error_7(data_tx_error_7), //INPUT : Status
.data_tx_data_7(data_tx_data_7), //INPUT : Data from FIFO transmit
.data_tx_valid_7(data_tx_valid_7), //INPUT : Data FIFO transmit Empty
.data_tx_sop_7(data_tx_sop_7), //INPUT : Start of Packet
.data_tx_eop_7(data_tx_eop_7), //INPUT : End of Packet
.data_tx_ready_7(data_tx_ready_7), //OUTPUT : Data FIFO transmit Read Enable
.tx_ff_uflow_7(tx_ff_uflow_7), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
.tx_crc_fwd_7(tx_crc_fwd_7), //INPUT : Forward Current Frame with CRC from Application
.xoff_gen_7(xoff_gen_7), //INPUT : XOFF PAUSE FRAME GENERATE
.xon_gen_7(xon_gen_7), //INPUT : XON PAUSE FRAME GENERATE
.magic_sleep_n_7(magic_sleep_n_7), //INPUT : MAC SLEEP MODE CONTROL
.magic_wakeup_7(magic_wakeup_7), //OUTPUT : MAC WAKE-UP INDICATION
// Channel 8
.rx_carrierdetected_8(pcs_rx_carrierdetected[8]),
.rx_rmfifodatadeleted_8(pcs_rx_rmfifodatadeleted[8]),
.rx_rmfifodatainserted_8(pcs_rx_rmfifodatainserted[8]),
.rx_clkout_8(rx_pcs_clk_c8), //INPUT : Receive Clock
.tx_clkout_8(tx_pcs_clk_c8), //INPUT : Transmit Clock
.rx_kchar_8(pcs_rx_kchar_8), //INPUT : Special Character Indication
.tx_kchar_8(tx_kchar_8), //OUTPUT : Special Character Indication
.rx_frame_8(pcs_rx_frame_8), //INPUT : Frame
.tx_frame_8(tx_frame_8), //OUTPUT : Frame
.sd_loopback_8(sd_loopback_8), //OUTPUT : SERDES Loopback Enable
.powerdown_8(pcs_pwrdn_out_sig[8]), //OUTPUT : Powerdown Enable
.led_col_8(led_col_8), //OUTPUT : Collision Indication
.led_an_8(led_an_8), //OUTPUT : Auto Negotiation Status
.led_char_err_8(led_char_err_gx[8]), //INPUT : Character error
.led_crs_8(led_crs_8), //OUTPUT : Carrier sense
.led_link_8(link_status[8]), //INPUT : Valid link
.mac_rx_clk_8(mac_rx_clk_8), //OUTPUT : Av-ST Rx Clock
.mac_tx_clk_8(mac_tx_clk_8), //OUTPUT : Av-ST Tx Clock
.data_rx_sop_8(data_rx_sop_8), //OUTPUT : Start of Packet
.data_rx_eop_8(data_rx_eop_8), //OUTPUT : End of Packet
.data_rx_data_8(data_rx_data_8), //OUTPUT : Data from FIFO
.data_rx_error_8(data_rx_error_8), //OUTPUT : Receive packet error
.data_rx_valid_8(data_rx_valid_8), //OUTPUT : Data Receive FIFO Valid
.data_rx_ready_8(data_rx_ready_8), //OUTPUT : Data Receive Ready
.pkt_class_data_8(pkt_class_data_8), //OUTPUT : Frame Type Indication
.pkt_class_valid_8(pkt_class_valid_8), //OUTPUT : Frame Type Indication Valid
.data_tx_error_8(data_tx_error_8), //INPUT : Status
.data_tx_data_8(data_tx_data_8), //INPUT : Data from FIFO transmit
.data_tx_valid_8(data_tx_valid_8), //INPUT : Data FIFO transmit Empty
.data_tx_sop_8(data_tx_sop_8), //INPUT : Start of Packet
.data_tx_eop_8(data_tx_eop_8), //INPUT : End of Packet
.data_tx_ready_8(data_tx_ready_8), //OUTPUT : Data FIFO transmit Read Enable
.tx_ff_uflow_8(tx_ff_uflow_8), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
.tx_crc_fwd_8(tx_crc_fwd_8), //INPUT : Forward Current Frame with CRC from Application
.xoff_gen_8(xoff_gen_8), //INPUT : XOFF PAUSE FRAME GENERATE
.xon_gen_8(xon_gen_8), //INPUT : XON PAUSE FRAME GENERATE
.magic_sleep_n_8(magic_sleep_n_8), //INPUT : MAC SLEEP MODE CONTROL
.magic_wakeup_8(magic_wakeup_8), //OUTPUT : MAC WAKE-UP INDICATION
// Channel 9
.rx_carrierdetected_9(pcs_rx_carrierdetected[9]),
.rx_rmfifodatadeleted_9(pcs_rx_rmfifodatadeleted[9]),
.rx_rmfifodatainserted_9(pcs_rx_rmfifodatainserted[9]),
.rx_clkout_9(rx_pcs_clk_c9), //INPUT : Receive Clock
.tx_clkout_9(tx_pcs_clk_c9), //INPUT : Transmit Clock
.rx_kchar_9(pcs_rx_kchar_9), //INPUT : Special Character Indication
.tx_kchar_9(tx_kchar_9), //OUTPUT : Special Character Indication
.rx_frame_9(pcs_rx_frame_9), //INPUT : Frame
.tx_frame_9(tx_frame_9), //OUTPUT : Frame
.sd_loopback_9(sd_loopback_9), //OUTPUT : SERDES Loopback Enable
.powerdown_9(pcs_pwrdn_out_sig[9]), //OUTPUT : Powerdown Enable
.led_col_9(led_col_9), //OUTPUT : Collision Indication
.led_an_9(led_an_9), //OUTPUT : Auto Negotiation Status
.led_char_err_9(led_char_err_gx[9]), //INPUT : Character error
.led_crs_9(led_crs_9), //OUTPUT : Carrier sense
.led_link_9(link_status[9]), //INPUT : Valid link
.mac_rx_clk_9(mac_rx_clk_9), //OUTPUT : Av-ST Rx Clock
.mac_tx_clk_9(mac_tx_clk_9), //OUTPUT : Av-ST Tx Clock
.data_rx_sop_9(data_rx_sop_9), //OUTPUT : Start of Packet
.data_rx_eop_9(data_rx_eop_9), //OUTPUT : End of Packet
.data_rx_data_9(data_rx_data_9), //OUTPUT : Data from FIFO
.data_rx_error_9(data_rx_error_9), //OUTPUT : Receive packet error
.data_rx_valid_9(data_rx_valid_9), //OUTPUT : Data Receive FIFO Valid
.data_rx_ready_9(data_rx_ready_9), //OUTPUT : Data Receive Ready
.pkt_class_data_9(pkt_class_data_9), //OUTPUT : Frame Type Indication
.pkt_class_valid_9(pkt_class_valid_9), //OUTPUT : Frame Type Indication Valid
.data_tx_error_9(data_tx_error_9), //INPUT : Status
.data_tx_data_9(data_tx_data_9), //INPUT : Data from FIFO transmit
.data_tx_valid_9(data_tx_valid_9), //INPUT : Data FIFO transmit Empty
.data_tx_sop_9(data_tx_sop_9), //INPUT : Start of Packet
.data_tx_eop_9(data_tx_eop_9), //INPUT : End of Packet
.data_tx_ready_9(data_tx_ready_9), //OUTPUT : Data FIFO transmit Read Enable
.tx_ff_uflow_9(tx_ff_uflow_9), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
.tx_crc_fwd_9(tx_crc_fwd_9), //INPUT : Forward Current Frame with CRC from Application
.xoff_gen_9(xoff_gen_9), //INPUT : XOFF PAUSE FRAME GENERATE
.xon_gen_9(xon_gen_9), //INPUT : XON PAUSE FRAME GENERATE
.magic_sleep_n_9(magic_sleep_n_9), //INPUT : MAC SLEEP MODE CONTROL
.magic_wakeup_9(magic_wakeup_9), //OUTPUT : MAC WAKE-UP INDICATION
// Channel 10
.rx_carrierdetected_10(pcs_rx_carrierdetected[10]),
.rx_rmfifodatadeleted_10(pcs_rx_rmfifodatadeleted[10]),
.rx_rmfifodatainserted_10(pcs_rx_rmfifodatainserted[10]),
.rx_clkout_10(rx_pcs_clk_c10), //INPUT : Receive Clock
.tx_clkout_10(tx_pcs_clk_c10), //INPUT : Transmit Clock
.rx_kchar_10(pcs_rx_kchar_10), //INPUT : Special Character Indication
.tx_kchar_10(tx_kchar_10), //OUTPUT : Special Character Indication
.rx_frame_10(pcs_rx_frame_10), //INPUT : Frame
.tx_frame_10(tx_frame_10), //OUTPUT : Frame
.sd_loopback_10(sd_loopback_10), //OUTPUT : SERDES Loopback Enable
.powerdown_10(pcs_pwrdn_out_sig[10]), //OUTPUT : Powerdown Enable
.led_col_10(led_col_10), //OUTPUT : Collision Indication
.led_an_10(led_an_10), //OUTPUT : Auto Negotiation Status
.led_char_err_10(led_char_err_gx[10]), //INPUT : Character error
.led_crs_10(led_crs_10), //OUTPUT : Carrier sense
.led_link_10(link_status[10]), //INPUT : Valid link
.mac_rx_clk_10(mac_rx_clk_10), //OUTPUT : Av-ST Rx Clock
.mac_tx_clk_10(mac_tx_clk_10), //OUTPUT : Av-ST Tx Clock
.data_rx_sop_10(data_rx_sop_10), //OUTPUT : Start of Packet
.data_rx_eop_10(data_rx_eop_10), //OUTPUT : End of Packet
.data_rx_data_10(data_rx_data_10), //OUTPUT : Data from FIFO
.data_rx_error_10(data_rx_error_10), //OUTPUT : Receive packet error
.data_rx_valid_10(data_rx_valid_10), //OUTPUT : Data Receive FIFO Valid
.data_rx_ready_10(data_rx_ready_10), //OUTPUT : Data Receive Ready
.pkt_class_data_10(pkt_class_data_10), //OUTPUT : Frame Type Indication
.pkt_class_valid_10(pkt_class_valid_10), //OUTPUT : Frame Type Indication Valid
.data_tx_error_10(data_tx_error_10), //INPUT : Status
.data_tx_data_10(data_tx_data_10), //INPUT : Data from FIFO transmit
.data_tx_valid_10(data_tx_valid_10), //INPUT : Data FIFO transmit Empty
.data_tx_sop_10(data_tx_sop_10), //INPUT : Start of Packet
.data_tx_eop_10(data_tx_eop_10), //INPUT : End of Packet
.data_tx_ready_10(data_tx_ready_10), //OUTPUT : Data FIFO transmit Read Enable
.tx_ff_uflow_10(tx_ff_uflow_10), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
.tx_crc_fwd_10(tx_crc_fwd_10), //INPUT : Forward Current Frame with CRC from Application
.xoff_gen_10(xoff_gen_10), //INPUT : XOFF PAUSE FRAME GENERATE
.xon_gen_10(xon_gen_10), //INPUT : XON PAUSE FRAME GENERATE
.magic_sleep_n_10(magic_sleep_n_10), //INPUT : MAC SLEEP MODE CONTROL
.magic_wakeup_10(magic_wakeup_10), //OUTPUT : MAC WAKE-UP INDICATION
// Channel 11
.rx_carrierdetected_11(pcs_rx_carrierdetected[11]),
.rx_rmfifodatadeleted_11(pcs_rx_rmfifodatadeleted[11]),
.rx_rmfifodatainserted_11(pcs_rx_rmfifodatainserted[11]),
.rx_clkout_11(rx_pcs_clk_c11), //INPUT : Receive Clock
.tx_clkout_11(tx_pcs_clk_c11), //INPUT : Transmit Clock
.rx_kchar_11(pcs_rx_kchar_11), //INPUT : Special Character Indication
.tx_kchar_11(tx_kchar_11), //OUTPUT : Special Character Indication
.rx_frame_11(pcs_rx_frame_11), //INPUT : Frame
.tx_frame_11(tx_frame_11), //OUTPUT : Frame
.sd_loopback_11(sd_loopback_11), //OUTPUT : SERDES Loopback Enable
.powerdown_11(pcs_pwrdn_out_sig[11]), //OUTPUT : Powerdown Enable
.led_col_11(led_col_11), //OUTPUT : Collision Indication
.led_an_11(led_an_11), //OUTPUT : Auto Negotiation Status
.led_char_err_11(led_char_err_gx[11]), //INPUT : Character error
.led_crs_11(led_crs_11), //OUTPUT : Carrier sense
.led_link_11(link_status[11]), //INPUT : Valid link
.mac_rx_clk_11(mac_rx_clk_11), //OUTPUT : Av-ST Rx Clock
.mac_tx_clk_11(mac_tx_clk_11), //OUTPUT : Av-ST Tx Clock
.data_rx_sop_11(data_rx_sop_11), //OUTPUT : Start of Packet
.data_rx_eop_11(data_rx_eop_11), //OUTPUT : End of Packet
.data_rx_data_11(data_rx_data_11), //OUTPUT : Data from FIFO
.data_rx_error_11(data_rx_error_11), //OUTPUT : Receive packet error
.data_rx_valid_11(data_rx_valid_11), //OUTPUT : Data Receive FIFO Valid
.data_rx_ready_11(data_rx_ready_11), //OUTPUT : Data Receive Ready
.pkt_class_data_11(pkt_class_data_11), //OUTPUT : Frame Type Indication
.pkt_class_valid_11(pkt_class_valid_11), //OUTPUT : Frame Type Indication Valid
.data_tx_error_11(data_tx_error_11), //INPUT : Status
.data_tx_data_11(data_tx_data_11), //INPUT : Data from FIFO transmit
.data_tx_valid_11(data_tx_valid_11), //INPUT : Data FIFO transmit Empty
.data_tx_sop_11(data_tx_sop_11), //INPUT : Start of Packet
.data_tx_eop_11(data_tx_eop_11), //INPUT : End of Packet
.data_tx_ready_11(data_tx_ready_11), //OUTPUT : Data FIFO transmit Read Enable
.tx_ff_uflow_11(tx_ff_uflow_11), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
.tx_crc_fwd_11(tx_crc_fwd_11), //INPUT : Forward Current Frame with CRC from Application
.xoff_gen_11(xoff_gen_11), //INPUT : XOFF PAUSE FRAME GENERATE
.xon_gen_11(xon_gen_11), //INPUT : XON PAUSE FRAME GENERATE
.magic_sleep_n_11(magic_sleep_n_11), //INPUT : MAC SLEEP MODE CONTROL
.magic_wakeup_11(magic_wakeup_11), //OUTPUT : MAC WAKE-UP INDICATION
// Channel 12
.rx_carrierdetected_12(pcs_rx_carrierdetected[12]),
.rx_rmfifodatadeleted_12(pcs_rx_rmfifodatadeleted[12]),
.rx_rmfifodatainserted_12(pcs_rx_rmfifodatainserted[12]),
.rx_clkout_12(rx_pcs_clk_c12), //INPUT : Receive Clock
.tx_clkout_12(tx_pcs_clk_c12), //INPUT : Transmit Clock
.rx_kchar_12(pcs_rx_kchar_12), //INPUT : Special Character Indication
.tx_kchar_12(tx_kchar_12), //OUTPUT : Special Character Indication
.rx_frame_12(pcs_rx_frame_12), //INPUT : Frame
.tx_frame_12(tx_frame_12), //OUTPUT : Frame
.sd_loopback_12(sd_loopback_12), //OUTPUT : SERDES Loopback Enable
.powerdown_12(pcs_pwrdn_out_sig[12]), //OUTPUT : Powerdown Enable
.led_col_12(led_col_12), //OUTPUT : Collision Indication
.led_an_12(led_an_12), //OUTPUT : Auto Negotiation Status
.led_char_err_12(led_char_err_gx[12]), //INPUT : Character error
.led_crs_12(led_crs_12), //OUTPUT : Carrier sense
.led_link_12(link_status[12]), //INPUT : Valid link
.mac_rx_clk_12(mac_rx_clk_12), //OUTPUT : Av-ST Rx Clock
.mac_tx_clk_12(mac_tx_clk_12), //OUTPUT : Av-ST Tx Clock
.data_rx_sop_12(data_rx_sop_12), //OUTPUT : Start of Packet
.data_rx_eop_12(data_rx_eop_12), //OUTPUT : End of Packet
.data_rx_data_12(data_rx_data_12), //OUTPUT : Data from FIFO
.data_rx_error_12(data_rx_error_12), //OUTPUT : Receive packet error
.data_rx_valid_12(data_rx_valid_12), //OUTPUT : Data Receive FIFO Valid
.data_rx_ready_12(data_rx_ready_12), //OUTPUT : Data Receive Ready
.pkt_class_data_12(pkt_class_data_12), //OUTPUT : Frame Type Indication
.pkt_class_valid_12(pkt_class_valid_12), //OUTPUT : Frame Type Indication Valid
.data_tx_error_12(data_tx_error_12), //INPUT : Status
.data_tx_data_12(data_tx_data_12), //INPUT : Data from FIFO transmit
.data_tx_valid_12(data_tx_valid_12), //INPUT : Data FIFO transmit Empty
.data_tx_sop_12(data_tx_sop_12), //INPUT : Start of Packet
.data_tx_eop_12(data_tx_eop_12), //INPUT : End of Packet
.data_tx_ready_12(data_tx_ready_12), //OUTPUT : Data FIFO transmit Read Enable
.tx_ff_uflow_12(tx_ff_uflow_12), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
.tx_crc_fwd_12(tx_crc_fwd_12), //INPUT : Forward Current Frame with CRC from Application
.xoff_gen_12(xoff_gen_12), //INPUT : XOFF PAUSE FRAME GENERATE
.xon_gen_12(xon_gen_12), //INPUT : XON PAUSE FRAME GENERATE
.magic_sleep_n_12(magic_sleep_n_12), //INPUT : MAC SLEEP MODE CONTROL
.magic_wakeup_12(magic_wakeup_12), //OUTPUT : MAC WAKE-UP INDICATION
// Channel 13
.rx_carrierdetected_13(pcs_rx_carrierdetected[13]),
.rx_rmfifodatadeleted_13(pcs_rx_rmfifodatadeleted[13]),
.rx_rmfifodatainserted_13(pcs_rx_rmfifodatainserted[13]),
.rx_clkout_13(rx_pcs_clk_c13), //INPUT : Receive Clock
.tx_clkout_13(tx_pcs_clk_c13), //INPUT : Transmit Clock
.rx_kchar_13(pcs_rx_kchar_13), //INPUT : Special Character Indication
.tx_kchar_13(tx_kchar_13), //OUTPUT : Special Character Indication
.rx_frame_13(pcs_rx_frame_13), //INPUT : Frame
.tx_frame_13(tx_frame_13), //OUTPUT : Frame
.sd_loopback_13(sd_loopback_13), //OUTPUT : SERDES Loopback Enable
.powerdown_13(pcs_pwrdn_out_sig[13]), //OUTPUT : Powerdown Enable
.led_col_13(led_col_13), //OUTPUT : Collision Indication
.led_an_13(led_an_13), //OUTPUT : Auto Negotiation Status
.led_char_err_13(led_char_err_gx[13]), //INPUT : Character error
.led_crs_13(led_crs_13), //OUTPUT : Carrier sense
.led_link_13(link_status[13]), //INPUT : Valid link
.mac_rx_clk_13(mac_rx_clk_13), //OUTPUT : Av-ST Rx Clock
.mac_tx_clk_13(mac_tx_clk_13), //OUTPUT : Av-ST Tx Clock
.data_rx_sop_13(data_rx_sop_13), //OUTPUT : Start of Packet
.data_rx_eop_13(data_rx_eop_13), //OUTPUT : End of Packet
.data_rx_data_13(data_rx_data_13), //OUTPUT : Data from FIFO
.data_rx_error_13(data_rx_error_13), //OUTPUT : Receive packet error
.data_rx_valid_13(data_rx_valid_13), //OUTPUT : Data Receive FIFO Valid
.data_rx_ready_13(data_rx_ready_13), //OUTPUT : Data Receive Ready
.pkt_class_data_13(pkt_class_data_13), //OUTPUT : Frame Type Indication
.pkt_class_valid_13(pkt_class_valid_13), //OUTPUT : Frame Type Indication Valid
.data_tx_error_13(data_tx_error_13), //INPUT : Status
.data_tx_data_13(data_tx_data_13), //INPUT : Data from FIFO transmit
.data_tx_valid_13(data_tx_valid_13), //INPUT : Data FIFO transmit Empty
.data_tx_sop_13(data_tx_sop_13), //INPUT : Start of Packet
.data_tx_eop_13(data_tx_eop_13), //INPUT : End of Packet
.data_tx_ready_13(data_tx_ready_13), //OUTPUT : Data FIFO transmit Read Enable
.tx_ff_uflow_13(tx_ff_uflow_13), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
.tx_crc_fwd_13(tx_crc_fwd_13), //INPUT : Forward Current Frame with CRC from Application
.xoff_gen_13(xoff_gen_13), //INPUT : XOFF PAUSE FRAME GENERATE
.xon_gen_13(xon_gen_13), //INPUT : XON PAUSE FRAME GENERATE
.magic_sleep_n_13(magic_sleep_n_13), //INPUT : MAC SLEEP MODE CONTROL
.magic_wakeup_13(magic_wakeup_13), //OUTPUT : MAC WAKE-UP INDICATION
// Channel 14
.rx_carrierdetected_14(pcs_rx_carrierdetected[14]),
.rx_rmfifodatadeleted_14(pcs_rx_rmfifodatadeleted[14]),
.rx_rmfifodatainserted_14(pcs_rx_rmfifodatainserted[14]),
.rx_clkout_14(rx_pcs_clk_c14), //INPUT : Receive Clock
.tx_clkout_14(tx_pcs_clk_c14), //INPUT : Transmit Clock
.rx_kchar_14(pcs_rx_kchar_14), //INPUT : Special Character Indication
.tx_kchar_14(tx_kchar_14), //OUTPUT : Special Character Indication
.rx_frame_14(pcs_rx_frame_14), //INPUT : Frame
.tx_frame_14(tx_frame_14), //OUTPUT : Frame
.sd_loopback_14(sd_loopback_14), //OUTPUT : SERDES Loopback Enable
.powerdown_14(pcs_pwrdn_out_sig[14]), //OUTPUT : Powerdown Enable
.led_col_14(led_col_14), //OUTPUT : Collision Indication
.led_an_14(led_an_14), //OUTPUT : Auto Negotiation Status
.led_char_err_14(led_char_err_gx[14]), //INPUT : Character error
.led_crs_14(led_crs_14), //OUTPUT : Carrier sense
.led_link_14(link_status[14]), //INPUT : Valid link
.mac_rx_clk_14(mac_rx_clk_14), //OUTPUT : Av-ST Rx Clock
.mac_tx_clk_14(mac_tx_clk_14), //OUTPUT : Av-ST Tx Clock
.data_rx_sop_14(data_rx_sop_14), //OUTPUT : Start of Packet
.data_rx_eop_14(data_rx_eop_14), //OUTPUT : End of Packet
.data_rx_data_14(data_rx_data_14), //OUTPUT : Data from FIFO
.data_rx_error_14(data_rx_error_14), //OUTPUT : Receive packet error
.data_rx_valid_14(data_rx_valid_14), //OUTPUT : Data Receive FIFO Valid
.data_rx_ready_14(data_rx_ready_14), //OUTPUT : Data Receive Ready
.pkt_class_data_14(pkt_class_data_14), //OUTPUT : Frame Type Indication
.pkt_class_valid_14(pkt_class_valid_14), //OUTPUT : Frame Type Indication Valid
.data_tx_error_14(data_tx_error_14), //INPUT : Status
.data_tx_data_14(data_tx_data_14), //INPUT : Data from FIFO transmit
.data_tx_valid_14(data_tx_valid_14), //INPUT : Data FIFO transmit Empty
.data_tx_sop_14(data_tx_sop_14), //INPUT : Start of Packet
.data_tx_eop_14(data_tx_eop_14), //INPUT : End of Packet
.data_tx_ready_14(data_tx_ready_14), //OUTPUT : Data FIFO transmit Read Enable
.tx_ff_uflow_14(tx_ff_uflow_14), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
.tx_crc_fwd_14(tx_crc_fwd_14), //INPUT : Forward Current Frame with CRC from Application
.xoff_gen_14(xoff_gen_14), //INPUT : XOFF PAUSE FRAME GENERATE
.xon_gen_14(xon_gen_14), //INPUT : XON PAUSE FRAME GENERATE
.magic_sleep_n_14(magic_sleep_n_14), //INPUT : MAC SLEEP MODE CONTROL
.magic_wakeup_14(magic_wakeup_14), //OUTPUT : MAC WAKE-UP INDICATION
// Channel 15
.rx_carrierdetected_15(pcs_rx_carrierdetected[15]),
.rx_rmfifodatadeleted_15(pcs_rx_rmfifodatadeleted[15]),
.rx_rmfifodatainserted_15(pcs_rx_rmfifodatainserted[15]),
.rx_clkout_15(rx_pcs_clk_c15), //INPUT : Receive Clock
.tx_clkout_15(tx_pcs_clk_c15), //INPUT : Transmit Clock
.rx_kchar_15(pcs_rx_kchar_15), //INPUT : Special Character Indication
.tx_kchar_15(tx_kchar_15), //OUTPUT : Special Character Indication
.rx_frame_15(pcs_rx_frame_15), //INPUT : Frame
.tx_frame_15(tx_frame_15), //OUTPUT : Frame
.sd_loopback_15(sd_loopback_15), //OUTPUT : SERDES Loopback Enable
.powerdown_15(pcs_pwrdn_out_sig[15]), //OUTPUT : Powerdown Enable
.led_col_15(led_col_15), //OUTPUT : Collision Indication
.led_an_15(led_an_15), //OUTPUT : Auto Negotiation Status
.led_char_err_15(led_char_err_gx[15]), //INPUT : Character error
.led_crs_15(led_crs_15), //OUTPUT : Carrier sense
.led_link_15(link_status[15]), //INPUT : Valid link
.mac_rx_clk_15(mac_rx_clk_15), //OUTPUT : Av-ST Rx Clock
.mac_tx_clk_15(mac_tx_clk_15), //OUTPUT : Av-ST Tx Clock
.data_rx_sop_15(data_rx_sop_15), //OUTPUT : Start of Packet
.data_rx_eop_15(data_rx_eop_15), //OUTPUT : End of Packet
.data_rx_data_15(data_rx_data_15), //OUTPUT : Data from FIFO
.data_rx_error_15(data_rx_error_15), //OUTPUT : Receive packet error
.data_rx_valid_15(data_rx_valid_15), //OUTPUT : Data Receive FIFO Valid
.data_rx_ready_15(data_rx_ready_15), //OUTPUT : Data Receive Ready
.pkt_class_data_15(pkt_class_data_15), //OUTPUT : Frame Type Indication
.pkt_class_valid_15(pkt_class_valid_15), //OUTPUT : Frame Type Indication Valid
.data_tx_error_15(data_tx_error_15), //INPUT : Status
.data_tx_data_15(data_tx_data_15), //INPUT : Data from FIFO transmit
.data_tx_valid_15(data_tx_valid_15), //INPUT : Data FIFO transmit Empty
.data_tx_sop_15(data_tx_sop_15), //INPUT : Start of Packet
.data_tx_eop_15(data_tx_eop_15), //INPUT : End of Packet
.data_tx_ready_15(data_tx_ready_15), //OUTPUT : Data FIFO transmit Read Enable
.tx_ff_uflow_15(tx_ff_uflow_15), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
.tx_crc_fwd_15(tx_crc_fwd_15), //INPUT : Forward Current Frame with CRC from Application
.xoff_gen_15(xoff_gen_15), //INPUT : XOFF PAUSE FRAME GENERATE
.xon_gen_15(xon_gen_15), //INPUT : XON PAUSE FRAME GENERATE
.magic_sleep_n_15(magic_sleep_n_15), //INPUT : MAC SLEEP MODE CONTROL
.magic_wakeup_15(magic_wakeup_15), //OUTPUT : MAC WAKE-UP INDICATION
// Channel 16
.rx_carrierdetected_16(pcs_rx_carrierdetected[16]),
.rx_rmfifodatadeleted_16(pcs_rx_rmfifodatadeleted[16]),
.rx_rmfifodatainserted_16(pcs_rx_rmfifodatainserted[16]),
.rx_clkout_16(rx_pcs_clk_c16), //INPUT : Receive Clock
.tx_clkout_16(tx_pcs_clk_c16), //INPUT : Transmit Clock
.rx_kchar_16(pcs_rx_kchar_16), //INPUT : Special Character Indication
.tx_kchar_16(tx_kchar_16), //OUTPUT : Special Character Indication
.rx_frame_16(pcs_rx_frame_16), //INPUT : Frame
.tx_frame_16(tx_frame_16), //OUTPUT : Frame
.sd_loopback_16(sd_loopback_16), //OUTPUT : SERDES Loopback Enable
.powerdown_16(pcs_pwrdn_out_sig[16]), //OUTPUT : Powerdown Enable
.led_col_16(led_col_16), //OUTPUT : Collision Indication
.led_an_16(led_an_16), //OUTPUT : Auto Negotiation Status
.led_char_err_16(led_char_err_gx[16]), //INPUT : Character error
.led_crs_16(led_crs_16), //OUTPUT : Carrier sense
.led_link_16(link_status[16]), //INPUT : Valid link
.mac_rx_clk_16(mac_rx_clk_16), //OUTPUT : Av-ST Rx Clock
.mac_tx_clk_16(mac_tx_clk_16), //OUTPUT : Av-ST Tx Clock
.data_rx_sop_16(data_rx_sop_16), //OUTPUT : Start of Packet
.data_rx_eop_16(data_rx_eop_16), //OUTPUT : End of Packet
.data_rx_data_16(data_rx_data_16), //OUTPUT : Data from FIFO
.data_rx_error_16(data_rx_error_16), //OUTPUT : Receive packet error
.data_rx_valid_16(data_rx_valid_16), //OUTPUT : Data Receive FIFO Valid
.data_rx_ready_16(data_rx_ready_16), //OUTPUT : Data Receive Ready
.pkt_class_data_16(pkt_class_data_16), //OUTPUT : Frame Type Indication
.pkt_class_valid_16(pkt_class_valid_16), //OUTPUT : Frame Type Indication Valid
.data_tx_error_16(data_tx_error_16), //INPUT : Status
.data_tx_data_16(data_tx_data_16), //INPUT : Data from FIFO transmit
.data_tx_valid_16(data_tx_valid_16), //INPUT : Data FIFO transmit Empty
.data_tx_sop_16(data_tx_sop_16), //INPUT : Start of Packet
.data_tx_eop_16(data_tx_eop_16), //INPUT : End of Packet
.data_tx_ready_16(data_tx_ready_16), //OUTPUT : Data FIFO transmit Read Enable
.tx_ff_uflow_16(tx_ff_uflow_16), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
.tx_crc_fwd_16(tx_crc_fwd_16), //INPUT : Forward Current Frame with CRC from Application
.xoff_gen_16(xoff_gen_16), //INPUT : XOFF PAUSE FRAME GENERATE
.xon_gen_16(xon_gen_16), //INPUT : XON PAUSE FRAME GENERATE
.magic_sleep_n_16(magic_sleep_n_16), //INPUT : MAC SLEEP MODE CONTROL
.magic_wakeup_16(magic_wakeup_16), //OUTPUT : MAC WAKE-UP INDICATION
// Channel 17
.rx_carrierdetected_17(pcs_rx_carrierdetected[17]),
.rx_rmfifodatadeleted_17(pcs_rx_rmfifodatadeleted[17]),
.rx_rmfifodatainserted_17(pcs_rx_rmfifodatainserted[17]),
.rx_clkout_17(rx_pcs_clk_c17), //INPUT : Receive Clock
.tx_clkout_17(tx_pcs_clk_c17), //INPUT : Transmit Clock
.rx_kchar_17(pcs_rx_kchar_17), //INPUT : Special Character Indication
.tx_kchar_17(tx_kchar_17), //OUTPUT : Special Character Indication
.rx_frame_17(pcs_rx_frame_17), //INPUT : Frame
.tx_frame_17(tx_frame_17), //OUTPUT : Frame
.sd_loopback_17(sd_loopback_17), //OUTPUT : SERDES Loopback Enable
.powerdown_17(pcs_pwrdn_out_sig[17]), //OUTPUT : Powerdown Enable
.led_col_17(led_col_17), //OUTPUT : Collision Indication
.led_an_17(led_an_17), //OUTPUT : Auto Negotiation Status
.led_char_err_17(led_char_err_gx[17]), //INPUT : Character error
.led_crs_17(led_crs_17), //OUTPUT : Carrier sense
.led_link_17(link_status[17]), //INPUT : Valid link
.mac_rx_clk_17(mac_rx_clk_17), //OUTPUT : Av-ST Rx Clock
.mac_tx_clk_17(mac_tx_clk_17), //OUTPUT : Av-ST Tx Clock
.data_rx_sop_17(data_rx_sop_17), //OUTPUT : Start of Packet
.data_rx_eop_17(data_rx_eop_17), //OUTPUT : End of Packet
.data_rx_data_17(data_rx_data_17), //OUTPUT : Data from FIFO
.data_rx_error_17(data_rx_error_17), //OUTPUT : Receive packet error
.data_rx_valid_17(data_rx_valid_17), //OUTPUT : Data Receive FIFO Valid
.data_rx_ready_17(data_rx_ready_17), //OUTPUT : Data Receive Ready
.pkt_class_data_17(pkt_class_data_17), //OUTPUT : Frame Type Indication
.pkt_class_valid_17(pkt_class_valid_17), //OUTPUT : Frame Type Indication Valid
.data_tx_error_17(data_tx_error_17), //INPUT : Status
.data_tx_data_17(data_tx_data_17), //INPUT : Data from FIFO transmit
.data_tx_valid_17(data_tx_valid_17), //INPUT : Data FIFO transmit Empty
.data_tx_sop_17(data_tx_sop_17), //INPUT : Start of Packet
.data_tx_eop_17(data_tx_eop_17), //INPUT : End of Packet
.data_tx_ready_17(data_tx_ready_17), //OUTPUT : Data FIFO transmit Read Enable
.tx_ff_uflow_17(tx_ff_uflow_17), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
.tx_crc_fwd_17(tx_crc_fwd_17), //INPUT : Forward Current Frame with CRC from Application
.xoff_gen_17(xoff_gen_17), //INPUT : XOFF PAUSE FRAME GENERATE
.xon_gen_17(xon_gen_17), //INPUT : XON PAUSE FRAME GENERATE
.magic_sleep_n_17(magic_sleep_n_17), //INPUT : MAC SLEEP MODE CONTROL
.magic_wakeup_17(magic_wakeup_17), //OUTPUT : MAC WAKE-UP INDICATION
// Channel 18
.rx_carrierdetected_18(pcs_rx_carrierdetected[18]),
.rx_rmfifodatadeleted_18(pcs_rx_rmfifodatadeleted[18]),
.rx_rmfifodatainserted_18(pcs_rx_rmfifodatainserted[18]),
.rx_clkout_18(rx_pcs_clk_c18), //INPUT : Receive Clock
.tx_clkout_18(tx_pcs_clk_c18), //INPUT : Transmit Clock
.rx_kchar_18(pcs_rx_kchar_18), //INPUT : Special Character Indication
.tx_kchar_18(tx_kchar_18), //OUTPUT : Special Character Indication
.rx_frame_18(pcs_rx_frame_18), //INPUT : Frame
.tx_frame_18(tx_frame_18), //OUTPUT : Frame
.sd_loopback_18(sd_loopback_18), //OUTPUT : SERDES Loopback Enable
.powerdown_18(pcs_pwrdn_out_sig[18]), //OUTPUT : Powerdown Enable
.led_col_18(led_col_18), //OUTPUT : Collision Indication
.led_an_18(led_an_18), //OUTPUT : Auto Negotiation Status
.led_char_err_18(led_char_err_gx[18]), //INPUT : Character error
.led_crs_18(led_crs_18), //OUTPUT : Carrier sense
.led_link_18(link_status[18]), //INPUT : Valid link
.mac_rx_clk_18(mac_rx_clk_18), //OUTPUT : Av-ST Rx Clock
.mac_tx_clk_18(mac_tx_clk_18), //OUTPUT : Av-ST Tx Clock
.data_rx_sop_18(data_rx_sop_18), //OUTPUT : Start of Packet
.data_rx_eop_18(data_rx_eop_18), //OUTPUT : End of Packet
.data_rx_data_18(data_rx_data_18), //OUTPUT : Data from FIFO
.data_rx_error_18(data_rx_error_18), //OUTPUT : Receive packet error
.data_rx_valid_18(data_rx_valid_18), //OUTPUT : Data Receive FIFO Valid
.data_rx_ready_18(data_rx_ready_18), //OUTPUT : Data Receive Ready
.pkt_class_data_18(pkt_class_data_18), //OUTPUT : Frame Type Indication
.pkt_class_valid_18(pkt_class_valid_18), //OUTPUT : Frame Type Indication Valid
.data_tx_error_18(data_tx_error_18), //INPUT : Status
.data_tx_data_18(data_tx_data_18), //INPUT : Data from FIFO transmit
.data_tx_valid_18(data_tx_valid_18), //INPUT : Data FIFO transmit Empty
.data_tx_sop_18(data_tx_sop_18), //INPUT : Start of Packet
.data_tx_eop_18(data_tx_eop_18), //INPUT : End of Packet
.data_tx_ready_18(data_tx_ready_18), //OUTPUT : Data FIFO transmit Read Enable
.tx_ff_uflow_18(tx_ff_uflow_18), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
.tx_crc_fwd_18(tx_crc_fwd_18), //INPUT : Forward Current Frame with CRC from Application
.xoff_gen_18(xoff_gen_18), //INPUT : XOFF PAUSE FRAME GENERATE
.xon_gen_18(xon_gen_18), //INPUT : XON PAUSE FRAME GENERATE
.magic_sleep_n_18(magic_sleep_n_18), //INPUT : MAC SLEEP MODE CONTROL
.magic_wakeup_18(magic_wakeup_18), //OUTPUT : MAC WAKE-UP INDICATION
// Channel 19
.rx_carrierdetected_19(pcs_rx_carrierdetected[19]),
.rx_rmfifodatadeleted_19(pcs_rx_rmfifodatadeleted[19]),
.rx_rmfifodatainserted_19(pcs_rx_rmfifodatainserted[19]),
.rx_clkout_19(rx_pcs_clk_c19), //INPUT : Receive Clock
.tx_clkout_19(tx_pcs_clk_c19), //INPUT : Transmit Clock
.rx_kchar_19(pcs_rx_kchar_19), //INPUT : Special Character Indication
.tx_kchar_19(tx_kchar_19), //OUTPUT : Special Character Indication
.rx_frame_19(pcs_rx_frame_19), //INPUT : Frame
.tx_frame_19(tx_frame_19), //OUTPUT : Frame
.sd_loopback_19(sd_loopback_19), //OUTPUT : SERDES Loopback Enable
.powerdown_19(pcs_pwrdn_out_sig[19]), //OUTPUT : Powerdown Enable
.led_col_19(led_col_19), //OUTPUT : Collision Indication
.led_an_19(led_an_19), //OUTPUT : Auto Negotiation Status
.led_char_err_19(led_char_err_gx[19]), //INPUT : Character error
.led_crs_19(led_crs_19), //OUTPUT : Carrier sense
.led_link_19(link_status[19]), //INPUT : Valid link
.mac_rx_clk_19(mac_rx_clk_19), //OUTPUT : Av-ST Rx Clock
.mac_tx_clk_19(mac_tx_clk_19), //OUTPUT : Av-ST Tx Clock
.data_rx_sop_19(data_rx_sop_19), //OUTPUT : Start of Packet
.data_rx_eop_19(data_rx_eop_19), //OUTPUT : End of Packet
.data_rx_data_19(data_rx_data_19), //OUTPUT : Data from FIFO
.data_rx_error_19(data_rx_error_19), //OUTPUT : Receive packet error
.data_rx_valid_19(data_rx_valid_19), //OUTPUT : Data Receive FIFO Valid
.data_rx_ready_19(data_rx_ready_19), //OUTPUT : Data Receive Ready
.pkt_class_data_19(pkt_class_data_19), //OUTPUT : Frame Type Indication
.pkt_class_valid_19(pkt_class_valid_19), //OUTPUT : Frame Type Indication Valid
.data_tx_error_19(data_tx_error_19), //INPUT : Status
.data_tx_data_19(data_tx_data_19), //INPUT : Data from FIFO transmit
.data_tx_valid_19(data_tx_valid_19), //INPUT : Data FIFO transmit Empty
.data_tx_sop_19(data_tx_sop_19), //INPUT : Start of Packet
.data_tx_eop_19(data_tx_eop_19), //INPUT : End of Packet
.data_tx_ready_19(data_tx_ready_19), //OUTPUT : Data FIFO transmit Read Enable
.tx_ff_uflow_19(tx_ff_uflow_19), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
.tx_crc_fwd_19(tx_crc_fwd_19), //INPUT : Forward Current Frame with CRC from Application
.xoff_gen_19(xoff_gen_19), //INPUT : XOFF PAUSE FRAME GENERATE
.xon_gen_19(xon_gen_19), //INPUT : XON PAUSE FRAME GENERATE
.magic_sleep_n_19(magic_sleep_n_19), //INPUT : MAC SLEEP MODE CONTROL
.magic_wakeup_19(magic_wakeup_19), //OUTPUT : MAC WAKE-UP INDICATION
// Channel 20
.rx_carrierdetected_20(pcs_rx_carrierdetected[20]),
.rx_rmfifodatadeleted_20(pcs_rx_rmfifodatadeleted[20]),
.rx_rmfifodatainserted_20(pcs_rx_rmfifodatainserted[20]),
.rx_clkout_20(rx_pcs_clk_c20), //INPUT : Receive Clock
.tx_clkout_20(tx_pcs_clk_c20), //INPUT : Transmit Clock
.rx_kchar_20(pcs_rx_kchar_20), //INPUT : Special Character Indication
.tx_kchar_20(tx_kchar_20), //OUTPUT : Special Character Indication
.rx_frame_20(pcs_rx_frame_20), //INPUT : Frame
.tx_frame_20(tx_frame_20), //OUTPUT : Frame
.sd_loopback_20(sd_loopback_20), //OUTPUT : SERDES Loopback Enable
.powerdown_20(pcs_pwrdn_out_sig[20]), //OUTPUT : Powerdown Enable
.led_col_20(led_col_20), //OUTPUT : Collision Indication
.led_an_20(led_an_20), //OUTPUT : Auto Negotiation Status
.led_char_err_20(led_char_err_gx[20]), //INPUT : Character error
.led_crs_20(led_crs_20), //OUTPUT : Carrier sense
.led_link_20(link_status[20]), //INPUT : Valid link
.mac_rx_clk_20(mac_rx_clk_20), //OUTPUT : Av-ST Rx Clock
.mac_tx_clk_20(mac_tx_clk_20), //OUTPUT : Av-ST Tx Clock
.data_rx_sop_20(data_rx_sop_20), //OUTPUT : Start of Packet
.data_rx_eop_20(data_rx_eop_20), //OUTPUT : End of Packet
.data_rx_data_20(data_rx_data_20), //OUTPUT : Data from FIFO
.data_rx_error_20(data_rx_error_20), //OUTPUT : Receive packet error
.data_rx_valid_20(data_rx_valid_20), //OUTPUT : Data Receive FIFO Valid
.data_rx_ready_20(data_rx_ready_20), //OUTPUT : Data Receive Ready
.pkt_class_data_20(pkt_class_data_20), //OUTPUT : Frame Type Indication
.pkt_class_valid_20(pkt_class_valid_20), //OUTPUT : Frame Type Indication Valid
.data_tx_error_20(data_tx_error_20), //INPUT : Status
.data_tx_data_20(data_tx_data_20), //INPUT : Data from FIFO transmit
.data_tx_valid_20(data_tx_valid_20), //INPUT : Data FIFO transmit Empty
.data_tx_sop_20(data_tx_sop_20), //INPUT : Start of Packet
.data_tx_eop_20(data_tx_eop_20), //INPUT : End of Packet
.data_tx_ready_20(data_tx_ready_20), //OUTPUT : Data FIFO transmit Read Enable
.tx_ff_uflow_20(tx_ff_uflow_20), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
.tx_crc_fwd_20(tx_crc_fwd_20), //INPUT : Forward Current Frame with CRC from Application
.xoff_gen_20(xoff_gen_20), //INPUT : XOFF PAUSE FRAME GENERATE
.xon_gen_20(xon_gen_20), //INPUT : XON PAUSE FRAME GENERATE
.magic_sleep_n_20(magic_sleep_n_20), //INPUT : MAC SLEEP MODE CONTROL
.magic_wakeup_20(magic_wakeup_20), //OUTPUT : MAC WAKE-UP INDICATION
// Channel 21
.rx_carrierdetected_21(pcs_rx_carrierdetected[21]),
.rx_rmfifodatadeleted_21(pcs_rx_rmfifodatadeleted[21]),
.rx_rmfifodatainserted_21(pcs_rx_rmfifodatainserted[21]),
.rx_clkout_21(rx_pcs_clk_c21), //INPUT : Receive Clock
.tx_clkout_21(tx_pcs_clk_c21), //INPUT : Transmit Clock
.rx_kchar_21(pcs_rx_kchar_21), //INPUT : Special Character Indication
.tx_kchar_21(tx_kchar_21), //OUTPUT : Special Character Indication
.rx_frame_21(pcs_rx_frame_21), //INPUT : Frame
.tx_frame_21(tx_frame_21), //OUTPUT : Frame
.sd_loopback_21(sd_loopback_21), //OUTPUT : SERDES Loopback Enable
.powerdown_21(pcs_pwrdn_out_sig[21]), //OUTPUT : Powerdown Enable
.led_col_21(led_col_21), //OUTPUT : Collision Indication
.led_an_21(led_an_21), //OUTPUT : Auto Negotiation Status
.led_char_err_21(led_char_err_gx[21]), //INPUT : Character error
.led_crs_21(led_crs_21), //OUTPUT : Carrier sense
.led_link_21(link_status[21]), //INPUT : Valid link
.mac_rx_clk_21(mac_rx_clk_21), //OUTPUT : Av-ST Rx Clock
.mac_tx_clk_21(mac_tx_clk_21), //OUTPUT : Av-ST Tx Clock
.data_rx_sop_21(data_rx_sop_21), //OUTPUT : Start of Packet
.data_rx_eop_21(data_rx_eop_21), //OUTPUT : End of Packet
.data_rx_data_21(data_rx_data_21), //OUTPUT : Data from FIFO
.data_rx_error_21(data_rx_error_21), //OUTPUT : Receive packet error
.data_rx_valid_21(data_rx_valid_21), //OUTPUT : Data Receive FIFO Valid
.data_rx_ready_21(data_rx_ready_21), //OUTPUT : Data Receive Ready
.pkt_class_data_21(pkt_class_data_21), //OUTPUT : Frame Type Indication
.pkt_class_valid_21(pkt_class_valid_21), //OUTPUT : Frame Type Indication Valid
.data_tx_error_21(data_tx_error_21), //INPUT : Status
.data_tx_data_21(data_tx_data_21), //INPUT : Data from FIFO transmit
.data_tx_valid_21(data_tx_valid_21), //INPUT : Data FIFO transmit Empty
.data_tx_sop_21(data_tx_sop_21), //INPUT : Start of Packet
.data_tx_eop_21(data_tx_eop_21), //INPUT : End of Packet
.data_tx_ready_21(data_tx_ready_21), //OUTPUT : Data FIFO transmit Read Enable
.tx_ff_uflow_21(tx_ff_uflow_21), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
.tx_crc_fwd_21(tx_crc_fwd_21), //INPUT : Forward Current Frame with CRC from Application
.xoff_gen_21(xoff_gen_21), //INPUT : XOFF PAUSE FRAME GENERATE
.xon_gen_21(xon_gen_21), //INPUT : XON PAUSE FRAME GENERATE
.magic_sleep_n_21(magic_sleep_n_21), //INPUT : MAC SLEEP MODE CONTROL
.magic_wakeup_21(magic_wakeup_21), //OUTPUT : MAC WAKE-UP INDICATION
// Channel 22
.rx_carrierdetected_22(pcs_rx_carrierdetected[22]),
.rx_rmfifodatadeleted_22(pcs_rx_rmfifodatadeleted[22]),
.rx_rmfifodatainserted_22(pcs_rx_rmfifodatainserted[22]),
.rx_clkout_22(rx_pcs_clk_c22), //INPUT : Receive Clock
.tx_clkout_22(tx_pcs_clk_c22), //INPUT : Transmit Clock
.rx_kchar_22(pcs_rx_kchar_22), //INPUT : Special Character Indication
.tx_kchar_22(tx_kchar_22), //OUTPUT : Special Character Indication
.rx_frame_22(pcs_rx_frame_22), //INPUT : Frame
.tx_frame_22(tx_frame_22), //OUTPUT : Frame
.sd_loopback_22(sd_loopback_22), //OUTPUT : SERDES Loopback Enable
.powerdown_22(pcs_pwrdn_out_sig[22]), //OUTPUT : Powerdown Enable
.led_col_22(led_col_22), //OUTPUT : Collision Indication
.led_an_22(led_an_22), //OUTPUT : Auto Negotiation Status
.led_char_err_22(led_char_err_gx[22]), //INPUT : Character error
.led_crs_22(led_crs_22), //OUTPUT : Carrier sense
.led_link_22(link_status[22]), //INPUT : Valid link
.mac_rx_clk_22(mac_rx_clk_22), //OUTPUT : Av-ST Rx Clock
.mac_tx_clk_22(mac_tx_clk_22), //OUTPUT : Av-ST Tx Clock
.data_rx_sop_22(data_rx_sop_22), //OUTPUT : Start of Packet
.data_rx_eop_22(data_rx_eop_22), //OUTPUT : End of Packet
.data_rx_data_22(data_rx_data_22), //OUTPUT : Data from FIFO
.data_rx_error_22(data_rx_error_22), //OUTPUT : Receive packet error
.data_rx_valid_22(data_rx_valid_22), //OUTPUT : Data Receive FIFO Valid
.data_rx_ready_22(data_rx_ready_22), //OUTPUT : Data Receive Ready
.pkt_class_data_22(pkt_class_data_22), //OUTPUT : Frame Type Indication
.pkt_class_valid_22(pkt_class_valid_22), //OUTPUT : Frame Type Indication Valid
.data_tx_error_22(data_tx_error_22), //INPUT : Status
.data_tx_data_22(data_tx_data_22), //INPUT : Data from FIFO transmit
.data_tx_valid_22(data_tx_valid_22), //INPUT : Data FIFO transmit Empty
.data_tx_sop_22(data_tx_sop_22), //INPUT : Start of Packet
.data_tx_eop_22(data_tx_eop_22), //INPUT : End of Packet
.data_tx_ready_22(data_tx_ready_22), //OUTPUT : Data FIFO transmit Read Enable
.tx_ff_uflow_22(tx_ff_uflow_22), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
.tx_crc_fwd_22(tx_crc_fwd_22), //INPUT : Forward Current Frame with CRC from Application
.xoff_gen_22(xoff_gen_22), //INPUT : XOFF PAUSE FRAME GENERATE
.xon_gen_22(xon_gen_22), //INPUT : XON PAUSE FRAME GENERATE
.magic_sleep_n_22(magic_sleep_n_22), //INPUT : MAC SLEEP MODE CONTROL
.magic_wakeup_22(magic_wakeup_22), //OUTPUT : MAC WAKE-UP INDICATION
// Channel 23
.rx_carrierdetected_23(pcs_rx_carrierdetected[23]),
.rx_rmfifodatadeleted_23(pcs_rx_rmfifodatadeleted[23]),
.rx_rmfifodatainserted_23(pcs_rx_rmfifodatainserted[23]),
.rx_clkout_23(rx_pcs_clk_c23), //INPUT : Receive Clock
.tx_clkout_23(tx_pcs_clk_c23), //INPUT : Transmit Clock
.rx_kchar_23(pcs_rx_kchar_23), //INPUT : Special Character Indication
.tx_kchar_23(tx_kchar_23), //OUTPUT : Special Character Indication
.rx_frame_23(pcs_rx_frame_23), //INPUT : Frame
.tx_frame_23(tx_frame_23), //OUTPUT : Frame
.sd_loopback_23(sd_loopback_23), //OUTPUT : SERDES Loopback Enable
.powerdown_23(pcs_pwrdn_out_sig[23]), //OUTPUT : Powerdown Enable
.led_col_23(led_col_23), //OUTPUT : Collision Indication
.led_an_23(led_an_23), //OUTPUT : Auto Negotiation Status
.led_char_err_23(led_char_err_gx[23]), //INPUT : Character error
.led_crs_23(led_crs_23), //OUTPUT : Carrier sense
.led_link_23(link_status[23]), //INPUT : Valid link
.mac_rx_clk_23(mac_rx_clk_23), //OUTPUT : Av-ST Rx Clock
.mac_tx_clk_23(mac_tx_clk_23), //OUTPUT : Av-ST Tx Clock
.data_rx_sop_23(data_rx_sop_23), //OUTPUT : Start of Packet
.data_rx_eop_23(data_rx_eop_23), //OUTPUT : End of Packet
.data_rx_data_23(data_rx_data_23), //OUTPUT : Data from FIFO
.data_rx_error_23(data_rx_error_23), //OUTPUT : Receive packet error
.data_rx_valid_23(data_rx_valid_23), //OUTPUT : Data Receive FIFO Valid
.data_rx_ready_23(data_rx_ready_23), //OUTPUT : Data Receive Ready
.pkt_class_data_23(pkt_class_data_23), //OUTPUT : Frame Type Indication
.pkt_class_valid_23(pkt_class_valid_23), //OUTPUT : Frame Type Indication Valid
.data_tx_error_23(data_tx_error_23), //INPUT : Status
.data_tx_data_23(data_tx_data_23), //INPUT : Data from FIFO transmit
.data_tx_valid_23(data_tx_valid_23), //INPUT : Data FIFO transmit Empty
.data_tx_sop_23(data_tx_sop_23), //INPUT : Start of Packet
.data_tx_eop_23(data_tx_eop_23), //INPUT : End of Packet
.data_tx_ready_23(data_tx_ready_23), //OUTPUT : Data FIFO transmit Read Enable
.tx_ff_uflow_23(tx_ff_uflow_23), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
.tx_crc_fwd_23(tx_crc_fwd_23), //INPUT : Forward Current Frame with CRC from Application
.xoff_gen_23(xoff_gen_23), //INPUT : XOFF PAUSE FRAME GENERATE
.xon_gen_23(xon_gen_23), //INPUT : XON PAUSE FRAME GENERATE
.magic_sleep_n_23(magic_sleep_n_23), //INPUT : MAC SLEEP MODE CONTROL
.magic_wakeup_23(magic_wakeup_23)); //OUTPUT : MAC WAKE-UP INDICATION
defparam
U_MULTI_MAC_PCS.USE_SYNC_RESET = USE_SYNC_RESET,
U_MULTI_MAC_PCS.RESET_LEVEL = RESET_LEVEL,
U_MULTI_MAC_PCS.ENABLE_GMII_LOOPBACK = ENABLE_GMII_LOOPBACK,
U_MULTI_MAC_PCS.ENABLE_HD_LOGIC = ENABLE_HD_LOGIC,
U_MULTI_MAC_PCS.ENABLE_SUP_ADDR = ENABLE_SUP_ADDR,
U_MULTI_MAC_PCS.ENA_HASH = ENA_HASH,
U_MULTI_MAC_PCS.STAT_CNT_ENA = STAT_CNT_ENA,
U_MULTI_MAC_PCS.CORE_VERSION = CORE_VERSION,
U_MULTI_MAC_PCS.CUST_VERSION = CUST_VERSION,
U_MULTI_MAC_PCS.REDUCED_INTERFACE_ENA = REDUCED_INTERFACE_ENA,
U_MULTI_MAC_PCS.ENABLE_MDIO = ENABLE_MDIO,
U_MULTI_MAC_PCS.MDIO_CLK_DIV = MDIO_CLK_DIV,
U_MULTI_MAC_PCS.ENABLE_MAGIC_DETECT = ENABLE_MAGIC_DETECT,
U_MULTI_MAC_PCS.ENABLE_PADDING = ENABLE_PADDING,
U_MULTI_MAC_PCS.ENABLE_LGTH_CHECK = ENABLE_LGTH_CHECK,
U_MULTI_MAC_PCS.GBIT_ONLY = GBIT_ONLY,
U_MULTI_MAC_PCS.MBIT_ONLY = MBIT_ONLY,
U_MULTI_MAC_PCS.REDUCED_CONTROL = REDUCED_CONTROL,
U_MULTI_MAC_PCS.CRC32DWIDTH = CRC32DWIDTH,
U_MULTI_MAC_PCS.CRC32GENDELAY = CRC32GENDELAY,
U_MULTI_MAC_PCS.CRC32CHECK16BIT = CRC32CHECK16BIT,
U_MULTI_MAC_PCS.CRC32S1L2_EXTERN = CRC32S1L2_EXTERN,
U_MULTI_MAC_PCS.ENABLE_SHIFT16 = ENABLE_SHIFT16,
U_MULTI_MAC_PCS.ENABLE_MAC_FLOW_CTRL = ENABLE_MAC_FLOW_CTRL,
U_MULTI_MAC_PCS.ENABLE_MAC_TXADDR_SET = ENABLE_MAC_TXADDR_SET,
U_MULTI_MAC_PCS.ENABLE_MAC_RX_VLAN = ENABLE_MAC_RX_VLAN,
U_MULTI_MAC_PCS.ENABLE_MAC_TX_VLAN = ENABLE_MAC_TX_VLAN,
U_MULTI_MAC_PCS.PHY_IDENTIFIER = PHY_IDENTIFIER,
U_MULTI_MAC_PCS.DEV_VERSION = DEV_VERSION,
U_MULTI_MAC_PCS.ENABLE_SGMII = ENABLE_SGMII,
U_MULTI_MAC_PCS.MAX_CHANNELS = MAX_CHANNELS,
U_MULTI_MAC_PCS.CHANNEL_WIDTH = CHANNEL_WIDTH,
U_MULTI_MAC_PCS.ENABLE_RX_FIFO_STATUS = ENABLE_RX_FIFO_STATUS,
U_MULTI_MAC_PCS.ENABLE_EXTENDED_STAT_REG = ENABLE_EXTENDED_STAT_REG,
U_MULTI_MAC_PCS.ENABLE_CLK_SHARING = ENABLE_CLK_SHARING,
U_MULTI_MAC_PCS.ENABLE_REG_SHARING = ENABLE_REG_SHARING;
// #######################################################################
// ############### CHANNEL 0 LOGIC/COMPONENTS ###############
// #######################################################################
// Export powerdown signal or wire it internally
// ---------------------------------------------
reg data_in_0,gxb_pwrdn_in_sig_clk_0;
generate if (EXPORT_PWRDN == 1 && MAX_CHANNELS > 0)
begin
always @(posedge clk or posedge gxb_pwrdn_in_0)
begin
if (gxb_pwrdn_in_0 == 1) begin
data_in_0 <= 1;
gxb_pwrdn_in_sig_clk_0 <= 1;
end else begin
data_in_0 <= 1'b0;
gxb_pwrdn_in_sig_clk_0 <= data_in_0;
end
end
assign gxb_pwrdn_in_sig[0] = gxb_pwrdn_in_0;
assign pcs_pwrdn_out_0 = pcs_pwrdn_out_sig[0];
end
else
begin
assign gxb_pwrdn_in_sig[0] = pcs_pwrdn_out_sig[0];
assign pcs_pwrdn_out_0 = 1'b0;
always@(*) begin
gxb_pwrdn_in_sig_clk_0 = gxb_pwrdn_in_sig[0];
end
end
endgenerate
generate if (MAX_CHANNELS > 0)
begin
wire locked_signal_0;
// ALTGX Reset Sequencer
altera_tse_reset_sequencer altera_tse_reset_sequencer_inst_0(
// User inputs and outputs
.clock(clk),
.reset_all(reset | gxb_pwrdn_in_sig_clk_0),
//.reset_tx_digital(reset_ref_clk),
//.reset_rx_digital(reset_ref_clk),
.powerdown_all(reset_posedge),
.tx_ready(), // output
.rx_ready(), // output
// I/O transceiver and status
.pll_powerdown(pll_powerdown_sqcnr_0),// output
.tx_digitalreset(tx_digitalreset_sqcnr_0),// output
.rx_analogreset(rx_analogreset_sqcnr_0),// output
.rx_digitalreset(rx_digitalreset_sqcnr_0),// output
.gxb_powerdown(gxb_powerdown_sqcnr_0),// output
.pll_is_locked(locked_signal_0),
.rx_is_lockedtodata(rx_freqlocked_0),
.manual_mode(1'b0),
.rx_oc_busy(reconfig_busy_0)
);
assign locked_signal_0 = (reset? 1'b0: pll_locked_0);
// Instantiation of the Alt2gxb and Alt4gxb block as the PMA for Stratix_II_GX ,ArriaGX and Stratix IV devices
// -----------------------------------------------------------------------------------
// Aligned Rx_sync from gxb
// -------------------------------
altera_tse_reset_synchronizer ch_0_reset_sync_0 (
.clk(rx_pcs_clk_c0),
.reset_in(rx_digitalreset_sqcnr_0),
.reset_out(reset_rx_pcs_clk_c0_int)
);
altera_tse_gxb_aligned_rxsync the_altera_tse_gxb_aligned_rxsync_0
(
.clk(rx_pcs_clk_c0),
.reset(reset_rx_pcs_clk_c0_int),
//input (from alt2gxb)
.alt_dataout(rx_frame_0),
.alt_sync(rx_syncstatus[0]),
.alt_disperr(rx_disp_err[0]),
.alt_ctrldetect(rx_kchar_0),
.alt_errdetect(rx_char_err_gx[0]),
.alt_rmfifodatadeleted(rx_rmfifodatadeleted[0]),
.alt_rmfifodatainserted(rx_rmfifodatainserted[0]),
.alt_runlengthviolation(rx_runlengthviolation[0]),
.alt_patterndetect(rx_patterndetect[0]),
.alt_runningdisp(rx_runningdisp[0]),
//output (to PCS)
.altpcs_dataout(pcs_rx_frame_0),
.altpcs_sync(link_status[0]),
.altpcs_disperr(led_disp_err_0),
.altpcs_ctrldetect(pcs_rx_kchar_0),
.altpcs_errdetect(led_char_err_gx[0]),
.altpcs_rmfifodatadeleted(pcs_rx_rmfifodatadeleted[0]),
.altpcs_rmfifodatainserted(pcs_rx_rmfifodatainserted[0]),
.altpcs_carrierdetect(pcs_rx_carrierdetected[0])
) ;
defparam
the_altera_tse_gxb_aligned_rxsync_0.DEVICE_FAMILY = DEVICE_FAMILY;
// Altgxb in GIGE mode
// --------------------
altera_tse_gxb_gige_inst the_altera_tse_gxb_gige_inst_0
(
.cal_blk_clk (gxb_cal_blk_clk),
.gxb_powerdown (gxb_pwrdn_in_sig[0]),
.pll_inclk (ref_clk),
.rx_recovclkout(rx_recovclkout_0),
.reconfig_clk(reconfig_clk_0),
.reconfig_togxb(reconfig_togxb_0),
.reconfig_fromgxb(reconfig_fromgxb_0),
.rx_analogreset (rx_analogreset_sqcnr_0),
.rx_cruclk (ref_clk),
.rx_ctrldetect (rx_kchar_0),
.rx_clkout (rx_pcs_clk_c0),
.rx_datain (rxp_0),
.rx_dataout (rx_frame_0),
.rx_digitalreset (rx_digitalreset_sqcnr_0),
.rx_disperr (rx_disp_err[0]),
.rx_errdetect (rx_char_err_gx[0]),
.rx_patterndetect (rx_patterndetect[0]),
.rx_rlv (rx_runlengthviolation[0]),
.rx_seriallpbken (sd_loopback_0),
.rx_syncstatus (rx_syncstatus[0]),
.tx_clkout (tx_pcs_clk_c0),
.tx_ctrlenable (tx_kchar_0),
.tx_datain (tx_frame_0),
.rx_freqlocked (rx_freqlocked_0),
.tx_dataout (txp_0),
.tx_digitalreset (tx_digitalreset_sqcnr_0),
.rx_rmfifodatadeleted(rx_rmfifodatadeleted[0]),
.rx_rmfifodatainserted(rx_rmfifodatainserted[0]),
.rx_runningdisp(rx_runningdisp[0]),
.pll_powerdown(gxb_pwrdn_in_sig[0]),
.pll_locked(pll_locked_0)
);
defparam
the_altera_tse_gxb_gige_inst_0.ENABLE_ALT_RECONFIG = ENABLE_ALT_RECONFIG,
the_altera_tse_gxb_gige_inst_0.ENABLE_SGMII = ENABLE_SGMII,
the_altera_tse_gxb_gige_inst_0.STARTING_CHANNEL_NUMBER = STARTING_CHANNEL_NUMBER,
the_altera_tse_gxb_gige_inst_0.DEVICE_FAMILY = DEVICE_FAMILY;
end
else
begin
assign reconfig_fromgxb_0 = {17{1'b0}};
assign led_char_err_gx[0] = 1'b0;
assign link_status[0] = 1'b0;
assign led_disp_err_0 = 1'b0;
assign txp_0 = 1'b0;
assign pcs_clk_c0 = 1'b0;
end
endgenerate
// #######################################################################
// ############### CHANNEL 1 LOGIC/COMPONENTS ###############
// #######################################################################
// Export powerdown signal or wire it internally
// ---------------------------------------------
reg data_in_1,gxb_pwrdn_in_sig_clk_1;
generate if (EXPORT_PWRDN == 1 && MAX_CHANNELS > 1)
begin
always @(posedge clk or posedge gxb_pwrdn_in_1)
begin
if (gxb_pwrdn_in_1 == 1) begin
data_in_1 <= 1;
gxb_pwrdn_in_sig_clk_1 <= 1;
end else begin
data_in_1 <= 1'b0;
gxb_pwrdn_in_sig_clk_1 <= data_in_1;
end
end
assign gxb_pwrdn_in_sig[1] = gxb_pwrdn_in_1;
assign pcs_pwrdn_out_1 = pcs_pwrdn_out_sig[1];
end
else
begin
assign gxb_pwrdn_in_sig[1] = pcs_pwrdn_out_sig[1];
assign pcs_pwrdn_out_1 = 1'b0;
always@(*) begin
gxb_pwrdn_in_sig_clk_1 = gxb_pwrdn_in_sig[1];
end
end
endgenerate
generate if (MAX_CHANNELS > 1)
begin
wire locked_signal_1;
// Reset logic used to reset the PMA blocks
// ----------------------------------------
// ALTGX Reset Sequencer
altera_tse_reset_sequencer altera_tse_reset_sequencer_inst_1(
// User inputs and outputs
.clock(clk),
.reset_all(reset | gxb_pwrdn_in_sig_clk_1),
//.reset_tx_digital(reset_ref_clk),
//.reset_rx_digital(reset_ref_clk),
.powerdown_all(reset_posedge),
.tx_ready(), // output
.rx_ready(), // output
// I/O transceiver and status
.pll_powerdown(pll_powerdown_sqcnr_1),// output
.tx_digitalreset(tx_digitalreset_sqcnr_1),// output
.rx_analogreset(rx_analogreset_sqcnr_1),// output
.rx_digitalreset(rx_digitalreset_sqcnr_1),// output
.gxb_powerdown(gxb_powerdown_sqcnr_1),// output
.pll_is_locked(locked_signal_1),
.rx_is_lockedtodata(rx_freqlocked_1),
.manual_mode(1'b0),
.rx_oc_busy(reconfig_busy_1)
);
assign locked_signal_1 = (reset? 1'b0: pll_locked_1);
// Instantiation of the Alt2gxb and Alt4gxb block as the PMA for Stratix_II_GX ,ArriaGX and Stratix IV devices
// -----------------------------------------------------------------------------------
// Aligned Rx_sync from gxb
// -------------------------------
altera_tse_reset_synchronizer ch_1_reset_sync_0 (
.clk(rx_pcs_clk_c1),
.reset_in(rx_digitalreset_sqcnr_1),
.reset_out(reset_rx_pcs_clk_c1_int)
);
altera_tse_gxb_aligned_rxsync the_altera_tse_gxb_aligned_rxsync_1
(
.clk(rx_pcs_clk_c1),
.reset(reset_rx_pcs_clk_c1_int),
//input (from alt2gxb)
.alt_dataout(rx_frame_1),
.alt_sync(rx_syncstatus[1]),
.alt_disperr(rx_disp_err[1]),
.alt_ctrldetect(rx_kchar_1),
.alt_errdetect(rx_char_err_gx[1]),
.alt_rmfifodatadeleted(rx_rmfifodatadeleted[1]),
.alt_rmfifodatainserted(rx_rmfifodatainserted[1]),
.alt_runlengthviolation(rx_runlengthviolation[1]),
.alt_patterndetect(rx_patterndetect[1]),
.alt_runningdisp(rx_runningdisp[1]),
//output (to PCS)
.altpcs_dataout(pcs_rx_frame_1),
.altpcs_sync(link_status[1]),
.altpcs_disperr(led_disp_err_1),
.altpcs_ctrldetect(pcs_rx_kchar_1),
.altpcs_errdetect(led_char_err_gx[1]),
.altpcs_rmfifodatadeleted(pcs_rx_rmfifodatadeleted[1]),
.altpcs_rmfifodatainserted(pcs_rx_rmfifodatainserted[1]),
.altpcs_carrierdetect(pcs_rx_carrierdetected[1])
) ;
defparam
the_altera_tse_gxb_aligned_rxsync_1.DEVICE_FAMILY = DEVICE_FAMILY;
// Altgxb in GIGE mode
// --------------------
altera_tse_gxb_gige_inst the_altera_tse_gxb_gige_inst_1
(
.cal_blk_clk (gxb_cal_blk_clk),
.gxb_powerdown (gxb_pwrdn_in_sig[1]),
.pll_inclk (ref_clk),
.rx_recovclkout(rx_recovclkout_1),
.reconfig_clk(reconfig_clk_1),
.reconfig_togxb(reconfig_togxb_1),
.reconfig_fromgxb(reconfig_fromgxb_1),
.rx_analogreset (rx_analogreset_sqcnr_1),
.rx_cruclk (ref_clk),
.rx_ctrldetect (rx_kchar_1),
.rx_clkout (rx_pcs_clk_c1),
.rx_datain (rxp_1),
.rx_dataout (rx_frame_1),
.rx_digitalreset (rx_digitalreset_sqcnr_1),
.rx_disperr (rx_disp_err[1]),
.rx_errdetect (rx_char_err_gx[1]),
.rx_patterndetect (rx_patterndetect[1]),
.rx_rlv (rx_runlengthviolation[1]),
.rx_seriallpbken (sd_loopback_1),
.rx_syncstatus (rx_syncstatus[1]),
.tx_clkout (tx_pcs_clk_c1),
.tx_ctrlenable (tx_kchar_1),
.tx_datain (tx_frame_1),
.rx_freqlocked (rx_freqlocked_1),
.tx_dataout (txp_1),
.tx_digitalreset (tx_digitalreset_sqcnr_1),
.rx_rmfifodatadeleted(rx_rmfifodatadeleted[1]),
.rx_rmfifodatainserted(rx_rmfifodatainserted[1]),
.rx_runningdisp(rx_runningdisp[1]),
.pll_powerdown(gxb_pwrdn_in_sig[1]),
.pll_locked(pll_locked_1)
);
defparam
the_altera_tse_gxb_gige_inst_1.ENABLE_ALT_RECONFIG = ENABLE_ALT_RECONFIG,
the_altera_tse_gxb_gige_inst_1.ENABLE_SGMII = ENABLE_SGMII,
the_altera_tse_gxb_gige_inst_1.STARTING_CHANNEL_NUMBER = STARTING_CHANNEL_NUMBER + 4,
the_altera_tse_gxb_gige_inst_1.DEVICE_FAMILY = DEVICE_FAMILY;
end
else
begin
assign reconfig_fromgxb_1 = {17{1'b0}};
assign led_char_err_gx[1] = 1'b0;
assign link_status[1] = 1'b0;
assign led_disp_err_1 = 1'b0;
assign txp_1 = 1'b0;
assign pcs_clk_c1 = 1'b0;
end
endgenerate
// #######################################################################
// ############### CHANNEL 2 LOGIC/COMPONENTS ###############
// #######################################################################
// Export powerdown signal or wire it internally
// ---------------------------------------------
reg data_in_2,gxb_pwrdn_in_sig_clk_2;
generate if (EXPORT_PWRDN == 1 && MAX_CHANNELS > 2)
begin
always @(posedge clk or posedge gxb_pwrdn_in_2)
begin
if (gxb_pwrdn_in_2 == 1) begin
data_in_2 <= 1;
gxb_pwrdn_in_sig_clk_2 <= 1;
end else begin
data_in_2 <= 1'b0;
gxb_pwrdn_in_sig_clk_2 <= data_in_2;
end
end
assign gxb_pwrdn_in_sig[2] = gxb_pwrdn_in_2;
assign pcs_pwrdn_out_2 = pcs_pwrdn_out_sig[2];
end
else
begin
assign gxb_pwrdn_in_sig[2] = pcs_pwrdn_out_sig[2];
assign pcs_pwrdn_out_2 = 1'b0;
always@(*) begin
gxb_pwrdn_in_sig_clk_2 = gxb_pwrdn_in_sig[2];
end
end
endgenerate
generate if (MAX_CHANNELS > 2)
begin
wire locked_signal_2;
// Reset logic used to reset the PMA blocks
// ----------------------------------------
// ALTGX Reset Sequencer
altera_tse_reset_sequencer altera_tse_reset_sequencer_inst_2(
// User inputs and outputs
.clock(clk),
.reset_all(reset | gxb_pwrdn_in_sig_clk_2),
//.reset_tx_digital(reset_ref_clk),
//.reset_rx_digital(reset_ref_clk),
.powerdown_all(reset_posedge),
.tx_ready(), // output
.rx_ready(), // output
// I/O transceiver and status
.pll_powerdown(pll_powerdown_sqcnr_2),// output
.tx_digitalreset(tx_digitalreset_sqcnr_2),// output
.rx_analogreset(rx_analogreset_sqcnr_2),// output
.rx_digitalreset(rx_digitalreset_sqcnr_2),// output
.gxb_powerdown(gxb_powerdown_sqcnr_2),// output
.pll_is_locked(locked_signal_2),
.rx_is_lockedtodata(rx_freqlocked_2),
.manual_mode(1'b0),
.rx_oc_busy(reconfig_busy_2)
);
assign locked_signal_2 = (reset? 1'b0: pll_locked_2);
// Instantiation of the Alt2gxb and Alt4gxb block as the PMA for Stratix_II_GX ,ArriaGX and Stratix IV devices
// -----------------------------------------------------------------------------------
// Aligned Rx_sync from gxb
// -------------------------------
altera_tse_reset_synchronizer ch_2_reset_sync_0 (
.clk(rx_pcs_clk_c2),
.reset_in(rx_digitalreset_sqcnr_2),
.reset_out(reset_rx_pcs_clk_c2_int)
);
altera_tse_gxb_aligned_rxsync the_altera_tse_gxb_aligned_rxsync_2
(
.clk(rx_pcs_clk_c2),
.reset(reset_rx_pcs_clk_c2_int),
//input (from alt2gxb)
.alt_dataout(rx_frame_2),
.alt_sync(rx_syncstatus[2]),
.alt_disperr(rx_disp_err[2]),
.alt_ctrldetect(rx_kchar_2),
.alt_errdetect(rx_char_err_gx[2]),
.alt_rmfifodatadeleted(rx_rmfifodatadeleted[2]),
.alt_rmfifodatainserted(rx_rmfifodatainserted[2]),
.alt_runlengthviolation(rx_runlengthviolation[2]),
.alt_patterndetect(rx_patterndetect[2]),
.alt_runningdisp(rx_runningdisp[2]),
//output (to PCS)
.altpcs_dataout(pcs_rx_frame_2),
.altpcs_sync(link_status[2]),
.altpcs_disperr(led_disp_err_2),
.altpcs_ctrldetect(pcs_rx_kchar_2),
.altpcs_errdetect(led_char_err_gx[2]),
.altpcs_rmfifodatadeleted(pcs_rx_rmfifodatadeleted[2]),
.altpcs_rmfifodatainserted(pcs_rx_rmfifodatainserted[2]),
.altpcs_carrierdetect(pcs_rx_carrierdetected[2])
) ;
defparam
the_altera_tse_gxb_aligned_rxsync_2.DEVICE_FAMILY = DEVICE_FAMILY;
// Altgxb in GIGE mode
// --------------------
altera_tse_gxb_gige_inst the_altera_tse_gxb_gige_inst_2
(
.cal_blk_clk (gxb_cal_blk_clk),
.gxb_powerdown (gxb_pwrdn_in_sig[2]),
.pll_inclk (ref_clk),
.rx_recovclkout(rx_recovclkout_2),
.reconfig_clk(reconfig_clk_2),
.reconfig_togxb(reconfig_togxb_2),
.reconfig_fromgxb(reconfig_fromgxb_2),
.rx_analogreset (rx_analogreset_sqcnr_2),
.rx_cruclk (ref_clk),
.rx_ctrldetect (rx_kchar_2),
.rx_clkout (rx_pcs_clk_c2),
.rx_datain (rxp_2),
.rx_dataout (rx_frame_2),
.rx_digitalreset (rx_digitalreset_sqcnr_2),
.rx_disperr (rx_disp_err[2]),
.rx_errdetect (rx_char_err_gx[2]),
.rx_patterndetect (rx_patterndetect[2]),
.rx_rlv (rx_runlengthviolation[2]),
.rx_seriallpbken (sd_loopback_2),
.rx_syncstatus (rx_syncstatus[2]),
.tx_clkout (tx_pcs_clk_c2),
.tx_ctrlenable (tx_kchar_2),
.tx_datain (tx_frame_2),
.rx_freqlocked (rx_freqlocked_2),
.tx_dataout (txp_2),
.tx_digitalreset (tx_digitalreset_sqcnr_2),
.rx_rmfifodatadeleted(rx_rmfifodatadeleted[2]),
.rx_rmfifodatainserted(rx_rmfifodatainserted[2]),
.rx_runningdisp(rx_runningdisp[2]),
.pll_powerdown(gxb_pwrdn_in_sig[2]),
.pll_locked(pll_locked_2)
);
defparam
the_altera_tse_gxb_gige_inst_2.ENABLE_ALT_RECONFIG = ENABLE_ALT_RECONFIG,
the_altera_tse_gxb_gige_inst_2.ENABLE_SGMII = ENABLE_SGMII,
the_altera_tse_gxb_gige_inst_2.STARTING_CHANNEL_NUMBER = STARTING_CHANNEL_NUMBER + 8,
the_altera_tse_gxb_gige_inst_2.DEVICE_FAMILY = DEVICE_FAMILY;
end
else
begin
assign reconfig_fromgxb_2 = {17{1'b0}};
assign led_char_err_gx[2] = 1'b0;
assign link_status[2] = 1'b0;
assign led_disp_err_2 = 1'b0;
assign txp_2 = 1'b0;
assign pcs_clk_c2 = 1'b0;
end
endgenerate
// #######################################################################
// ############### CHANNEL 3 LOGIC/COMPONENTS ###############
// #######################################################################
// Export powerdown signal or wire it internally
// ---------------------------------------------
reg data_in_3,gxb_pwrdn_in_sig_clk_3;
generate if (EXPORT_PWRDN == 1 && MAX_CHANNELS > 3)
begin
always @(posedge clk or posedge gxb_pwrdn_in_3)
begin
if (gxb_pwrdn_in_3 == 1) begin
data_in_3 <= 1;
gxb_pwrdn_in_sig_clk_3 <= 1;
end else begin
data_in_3 <= 1'b0;
gxb_pwrdn_in_sig_clk_3 <= data_in_3;
end
end
assign gxb_pwrdn_in_sig[3] = gxb_pwrdn_in_3;
assign pcs_pwrdn_out_3 = pcs_pwrdn_out_sig[3];
end
else
begin
assign gxb_pwrdn_in_sig[3] = pcs_pwrdn_out_sig[3];
assign pcs_pwrdn_out_3 = 1'b0;
always@(*) begin
gxb_pwrdn_in_sig_clk_3 = gxb_pwrdn_in_sig[3];
end
end
endgenerate
generate if (MAX_CHANNELS > 3)
begin
wire locked_signal_3;
// Reset logic used to reset the PMA blocks
// ----------------------------------------
// ALTGX Reset Sequencer
altera_tse_reset_sequencer altera_tse_reset_sequencer_inst_3(
// User inputs and outputs
.clock(clk),
.reset_all(reset|gxb_pwrdn_in_sig_clk_3),
//.reset_tx_digital(reset_ref_clk),
//.reset_rx_digital(reset_ref_clk),
.powerdown_all(reset_posedge),
.tx_ready(), // output
.rx_ready(), // output
// I/O transceiver and status
.pll_powerdown(pll_powerdown_sqcnr_3),// output
.tx_digitalreset(tx_digitalreset_sqcnr_3),// output
.rx_analogreset(rx_analogreset_sqcnr_3),// output
.rx_digitalreset(rx_digitalreset_sqcnr_3),// output
.gxb_powerdown(gxb_powerdown_sqcnr_3),// output
.pll_is_locked(locked_signal_3),
.rx_is_lockedtodata(rx_freqlocked_3),
.manual_mode(1'b0),
.rx_oc_busy(reconfig_busy_3)
);
assign locked_signal_3 = (reset? 1'b0: pll_locked_3);
// Instantiation of the Alt2gxb and Alt4gxb block as the PMA for Stratix_II_GX ,ArriaGX and Stratix IV devices
// -----------------------------------------------------------------------------------
// Aligned Rx_sync from gxb
// -------------------------------
altera_tse_reset_synchronizer ch_3_reset_sync_0 (
.clk(rx_pcs_clk_c3),
.reset_in(rx_digitalreset_sqcnr_3),
.reset_out(reset_rx_pcs_clk_c3_int)
);
altera_tse_gxb_aligned_rxsync the_altera_tse_gxb_aligned_rxsync_3
(
.clk(rx_pcs_clk_c3),
.reset(reset_rx_pcs_clk_c3_int),
//input (from alt2gxb)
.alt_dataout(rx_frame_3),
.alt_sync(rx_syncstatus[3]),
.alt_disperr(rx_disp_err[3]),
.alt_ctrldetect(rx_kchar_3),
.alt_errdetect(rx_char_err_gx[3]),
.alt_rmfifodatadeleted(rx_rmfifodatadeleted[3]),
.alt_rmfifodatainserted(rx_rmfifodatainserted[3]),
.alt_runlengthviolation(rx_runlengthviolation[3]),
.alt_patterndetect(rx_patterndetect[3]),
.alt_runningdisp(rx_runningdisp[3]),
//output (to PCS)
.altpcs_dataout(pcs_rx_frame_3),
.altpcs_sync(link_status[3]),
.altpcs_disperr(led_disp_err_3),
.altpcs_ctrldetect(pcs_rx_kchar_3),
.altpcs_errdetect(led_char_err_gx[3]),
.altpcs_rmfifodatadeleted(pcs_rx_rmfifodatadeleted[3]),
.altpcs_rmfifodatainserted(pcs_rx_rmfifodatainserted[3]),
.altpcs_carrierdetect(pcs_rx_carrierdetected[3])
) ;
defparam
the_altera_tse_gxb_aligned_rxsync_3.DEVICE_FAMILY = DEVICE_FAMILY;
// Altgxb in GIGE mode
// --------------------
altera_tse_gxb_gige_inst the_altera_tse_gxb_gige_inst_3
(
.cal_blk_clk (gxb_cal_blk_clk),
.gxb_powerdown (gxb_pwrdn_in_sig[3]),
.pll_inclk (ref_clk),
.rx_recovclkout(rx_recovclkout_3),
.reconfig_clk(reconfig_clk_3),
.reconfig_togxb(reconfig_togxb_3),
.reconfig_fromgxb(reconfig_fromgxb_3),
.rx_analogreset (rx_analogreset_sqcnr_3),
.rx_cruclk (ref_clk),
.rx_ctrldetect (rx_kchar_3),
.rx_clkout (rx_pcs_clk_c3),
.rx_datain (rxp_3),
.rx_dataout (rx_frame_3),
.rx_digitalreset (rx_digitalreset_sqcnr_3),
.rx_disperr (rx_disp_err[3]),
.rx_errdetect (rx_char_err_gx[3]),
.rx_patterndetect (rx_patterndetect[3]),
.rx_rlv (rx_runlengthviolation[3]),
.rx_seriallpbken (sd_loopback_3),
.rx_syncstatus (rx_syncstatus[3]),
.tx_clkout (tx_pcs_clk_c3),
.tx_ctrlenable (tx_kchar_3),
.tx_datain (tx_frame_3),
.rx_freqlocked (rx_freqlocked_3),
.tx_dataout (txp_3),
.tx_digitalreset (tx_digitalreset_sqcnr_3),
.rx_rmfifodatadeleted(rx_rmfifodatadeleted[3]),
.rx_rmfifodatainserted(rx_rmfifodatainserted[3]),
.rx_runningdisp(rx_runningdisp[3]),
.pll_powerdown(gxb_pwrdn_in_sig[3]),
.pll_locked(pll_locked_3)
);
defparam
the_altera_tse_gxb_gige_inst_3.ENABLE_ALT_RECONFIG = ENABLE_ALT_RECONFIG,
the_altera_tse_gxb_gige_inst_3.ENABLE_SGMII = ENABLE_SGMII,
the_altera_tse_gxb_gige_inst_3.STARTING_CHANNEL_NUMBER = STARTING_CHANNEL_NUMBER + 12,
the_altera_tse_gxb_gige_inst_3.DEVICE_FAMILY = DEVICE_FAMILY;
end
else
begin
assign reconfig_fromgxb_3 = {17{1'b0}};
assign led_char_err_gx[3] = 1'b0;
assign link_status[3] = 1'b0;
assign led_disp_err_3 = 1'b0;
assign txp_3 = 1'b0;
assign pcs_clk_c3 = 1'b0;
end
endgenerate
// #######################################################################
// ############### CHANNEL 4 LOGIC/COMPONENTS ###############
// #######################################################################
// Export powerdown signal or wire it internally
// ---------------------------------------------
reg data_in_4,gxb_pwrdn_in_sig_clk_4;
generate if (EXPORT_PWRDN == 1 && MAX_CHANNELS > 4)
begin
always @(posedge clk or posedge gxb_pwrdn_in_4)
begin
if (gxb_pwrdn_in_4 == 1) begin
data_in_4 <= 1;
gxb_pwrdn_in_sig_clk_4 <= 1;
end else begin
data_in_4 <= 1'b0;
gxb_pwrdn_in_sig_clk_4 <= data_in_4;
end
end
assign gxb_pwrdn_in_sig[4] = gxb_pwrdn_in_4;
assign pcs_pwrdn_out_4 = pcs_pwrdn_out_sig[4];
end
else
begin
assign gxb_pwrdn_in_sig[4] = pcs_pwrdn_out_sig[4];
assign pcs_pwrdn_out_4 = 1'b0;
always@(*) begin
gxb_pwrdn_in_sig_clk_4 = gxb_pwrdn_in_sig[4];
end
end
endgenerate
generate if (MAX_CHANNELS > 4)
begin
wire locked_signal_4;
// Reset logic used to reset the PMA blocks
// ----------------------------------------
// ALTGX Reset Sequencer
altera_tse_reset_sequencer altera_tse_reset_sequencer_inst_4(
// User inputs and outputs
.clock(clk),
.reset_all(reset|gxb_pwrdn_in_sig_clk_4),
//.reset_tx_digital(reset_ref_clk),
//.reset_rx_digital(reset_ref_clk),
.powerdown_all(reset_posedge),
.tx_ready(), // output
.rx_ready(), // output
// I/O transceiver and status
.pll_powerdown(pll_powerdown_sqcnr_4),// output
.tx_digitalreset(tx_digitalreset_sqcnr_4),// output
.rx_analogreset(rx_analogreset_sqcnr_4),// output
.rx_digitalreset(rx_digitalreset_sqcnr_4),// output
.gxb_powerdown(gxb_powerdown_sqcnr_4),// output
.pll_is_locked(locked_signal_4),
.rx_is_lockedtodata(rx_freqlocked_4),
.manual_mode(1'b0),
.rx_oc_busy(reconfig_busy_4)
);
assign locked_signal_4 = (reset? 1'b0: pll_locked_4);
// Instantiation of the Alt2gxb and Alt4gxb block as the PMA for Stratix_II_GX ,ArriaGX and Stratix IV devices
// -----------------------------------------------------------------------------------
// Aligned Rx_sync from gxb
// -------------------------------
altera_tse_reset_synchronizer ch_4_reset_sync_0 (
.clk(rx_pcs_clk_c4),
.reset_in(rx_digitalreset_sqcnr_4),
.reset_out(reset_rx_pcs_clk_c4_int)
);
altera_tse_gxb_aligned_rxsync the_altera_tse_gxb_aligned_rxsync_4
(
.clk(rx_pcs_clk_c4),
.reset(reset_rx_pcs_clk_c4_int),
//input (from alt2gxb)
.alt_dataout(rx_frame_4),
.alt_sync(rx_syncstatus[4]),
.alt_disperr(rx_disp_err[4]),
.alt_ctrldetect(rx_kchar_4),
.alt_errdetect(rx_char_err_gx[4]),
.alt_rmfifodatadeleted(rx_rmfifodatadeleted[4]),
.alt_rmfifodatainserted(rx_rmfifodatainserted[4]),
.alt_runlengthviolation(rx_runlengthviolation[4]),
.alt_patterndetect(rx_patterndetect[4]),
.alt_runningdisp(rx_runningdisp[4]),
//output (to PCS)
.altpcs_dataout(pcs_rx_frame_4),
.altpcs_sync(link_status[4]),
.altpcs_disperr(led_disp_err_4),
.altpcs_ctrldetect(pcs_rx_kchar_4),
.altpcs_errdetect(led_char_err_gx[4]),
.altpcs_rmfifodatadeleted(pcs_rx_rmfifodatadeleted[4]),
.altpcs_rmfifodatainserted(pcs_rx_rmfifodatainserted[4]),
.altpcs_carrierdetect(pcs_rx_carrierdetected[4])
) ;
defparam
the_altera_tse_gxb_aligned_rxsync_4.DEVICE_FAMILY = DEVICE_FAMILY;
// Altgxb in GIGE mode
// --------------------
altera_tse_gxb_gige_inst the_altera_tse_gxb_gige_inst_4
(
.cal_blk_clk (gxb_cal_blk_clk),
.gxb_powerdown (gxb_pwrdn_in_sig[4]),
.pll_inclk (ref_clk),
.rx_recovclkout(rx_recovclkout_4),
.reconfig_clk(reconfig_clk_4),
.reconfig_togxb(reconfig_togxb_4),
.reconfig_fromgxb(reconfig_fromgxb_4),
.rx_analogreset (rx_analogreset_sqcnr_4),
.rx_cruclk (ref_clk),
.rx_ctrldetect (rx_kchar_4),
.rx_clkout (rx_pcs_clk_c4),
.rx_datain (rxp_4),
.rx_dataout (rx_frame_4),
.rx_digitalreset (rx_digitalreset_sqcnr_4),
.rx_disperr (rx_disp_err[4]),
.rx_errdetect (rx_char_err_gx[4]),
.rx_patterndetect (rx_patterndetect[4]),
.rx_rlv (rx_runlengthviolation[4]),
.rx_seriallpbken (sd_loopback_4),
.rx_syncstatus (rx_syncstatus[4]),
.tx_clkout (tx_pcs_clk_c4),
.tx_ctrlenable (tx_kchar_4),
.tx_datain (tx_frame_4),
.rx_freqlocked (rx_freqlocked_4),
.tx_dataout (txp_4),
.tx_digitalreset (tx_digitalreset_sqcnr_4),
.rx_rmfifodatadeleted(rx_rmfifodatadeleted[4]),
.rx_rmfifodatainserted(rx_rmfifodatainserted[4]),
.rx_runningdisp(rx_runningdisp[4]),
.pll_powerdown(gxb_pwrdn_in_sig[4]),
.pll_locked(pll_locked_4)
);
defparam
the_altera_tse_gxb_gige_inst_4.ENABLE_ALT_RECONFIG = ENABLE_ALT_RECONFIG,
the_altera_tse_gxb_gige_inst_4.ENABLE_SGMII = ENABLE_SGMII,
the_altera_tse_gxb_gige_inst_4.STARTING_CHANNEL_NUMBER = STARTING_CHANNEL_NUMBER + 16,
the_altera_tse_gxb_gige_inst_4.DEVICE_FAMILY = DEVICE_FAMILY;
end
else
begin
assign reconfig_fromgxb_4 = {17{1'b0}};
assign led_char_err_gx[4] = 1'b0;
assign link_status[4] = 1'b0;
assign led_disp_err_4 = 1'b0;
assign txp_4 = 1'b0;
assign pcs_clk_c4 = 1'b0;
end
endgenerate
// #######################################################################
// ############### CHANNEL 5 LOGIC/COMPONENTS ###############
// #######################################################################
// Export powerdown signal or wire it internally
// ---------------------------------------------
reg data_in_5,gxb_pwrdn_in_sig_clk_5;
generate if (EXPORT_PWRDN == 1 && MAX_CHANNELS > 5)
begin
always @(posedge clk or posedge gxb_pwrdn_in_5)
begin
if (gxb_pwrdn_in_5 == 1) begin
data_in_5 <= 1;
gxb_pwrdn_in_sig_clk_5 <= 1;
end else begin
data_in_5 <= 1'b0;
gxb_pwrdn_in_sig_clk_5 <= data_in_5;
end
end
assign gxb_pwrdn_in_sig[5] = gxb_pwrdn_in_5;
assign pcs_pwrdn_out_5 = pcs_pwrdn_out_sig[5];
end
else
begin
assign gxb_pwrdn_in_sig[5] = pcs_pwrdn_out_sig[5];
assign pcs_pwrdn_out_5 = 1'b0;
always@(*) begin
gxb_pwrdn_in_sig_clk_5 = gxb_pwrdn_in_sig[5];
end
end
endgenerate
generate if (MAX_CHANNELS > 5)
begin
wire locked_signal_5;
// Reset logic used to reset the PMA blocks
// ----------------------------------------
// ALTGX Reset Sequencer
altera_tse_reset_sequencer altera_tse_reset_sequencer_inst_5(
// User inputs and outputs
.clock(clk),
.reset_all(reset|gxb_pwrdn_in_sig_clk_5),
//.reset_tx_digital(reset_ref_clk),
//.reset_rx_digital(reset_ref_clk),
.powerdown_all(reset_posedge),
.tx_ready(), // output
.rx_ready(), // output
// I/O transceiver and status
.pll_powerdown(pll_powerdown_sqcnr_5),// output
.tx_digitalreset(tx_digitalreset_sqcnr_5),// output
.rx_analogreset(rx_analogreset_sqcnr_5),// output
.rx_digitalreset(rx_digitalreset_sqcnr_5),// output
.gxb_powerdown(gxb_powerdown_sqcnr_5),// output
.pll_is_locked(locked_signal_5),
.rx_is_lockedtodata(rx_freqlocked_5),
.manual_mode(1'b0),
.rx_oc_busy(reconfig_busy_5)
);
assign locked_signal_5 = (reset? 1'b0: pll_locked_5);
// Instantiation of the Alt2gxb and Alt4gxb block as the PMA for Stratix_II_GX ,ArriaGX and Stratix IV devices
// -----------------------------------------------------------------------------------
// Aligned Rx_sync from gxb
// -------------------------------
altera_tse_reset_synchronizer ch_5_reset_sync_0 (
.clk(rx_pcs_clk_c5),
.reset_in(rx_digitalreset_sqcnr_5),
.reset_out(reset_rx_pcs_clk_c5_int)
);
altera_tse_gxb_aligned_rxsync the_altera_tse_gxb_aligned_rxsync_5
(
.clk(rx_pcs_clk_c5),
.reset(reset_rx_pcs_clk_c5_int),
//input (from alt2gxb)
.alt_dataout(rx_frame_5),
.alt_sync(rx_syncstatus[5]),
.alt_disperr(rx_disp_err[5]),
.alt_ctrldetect(rx_kchar_5),
.alt_errdetect(rx_char_err_gx[5]),
.alt_rmfifodatadeleted(rx_rmfifodatadeleted[5]),
.alt_rmfifodatainserted(rx_rmfifodatainserted[5]),
.alt_runlengthviolation(rx_runlengthviolation[5]),
.alt_patterndetect(rx_patterndetect[5]),
.alt_runningdisp(rx_runningdisp[5]),
//output (to PCS)
.altpcs_dataout(pcs_rx_frame_5),
.altpcs_sync(link_status[5]),
.altpcs_disperr(led_disp_err_5),
.altpcs_ctrldetect(pcs_rx_kchar_5),
.altpcs_errdetect(led_char_err_gx[5]),
.altpcs_rmfifodatadeleted(pcs_rx_rmfifodatadeleted[5]),
.altpcs_rmfifodatainserted(pcs_rx_rmfifodatainserted[5]),
.altpcs_carrierdetect(pcs_rx_carrierdetected[5])
) ;
defparam
the_altera_tse_gxb_aligned_rxsync_5.DEVICE_FAMILY = DEVICE_FAMILY;
// Altgxb in GIGE mode
// --------------------
altera_tse_gxb_gige_inst the_altera_tse_gxb_gige_inst_5
(
.cal_blk_clk (gxb_cal_blk_clk),
.gxb_powerdown (gxb_pwrdn_in_sig[5]),
.pll_inclk (ref_clk),
.rx_recovclkout(rx_recovclkout_5),
.reconfig_clk(reconfig_clk_5),
.reconfig_togxb(reconfig_togxb_5),
.reconfig_fromgxb(reconfig_fromgxb_5),
.rx_analogreset (rx_analogreset_sqcnr_5),
.rx_cruclk (ref_clk),
.rx_ctrldetect (rx_kchar_5),
.rx_clkout (rx_pcs_clk_c5),
.rx_datain (rxp_5),
.rx_dataout (rx_frame_5),
.rx_digitalreset (rx_digitalreset_sqcnr_4),
.rx_disperr (rx_disp_err[5]),
.rx_errdetect (rx_char_err_gx[5]),
.rx_patterndetect (rx_patterndetect[5]),
.rx_rlv (rx_runlengthviolation[5]),
.rx_seriallpbken (sd_loopback_5),
.rx_syncstatus (rx_syncstatus[5]),
.tx_clkout (tx_pcs_clk_c5),
.tx_ctrlenable (tx_kchar_5),
.tx_datain (tx_frame_5),
.rx_freqlocked (rx_freqlocked_5),
.tx_dataout (txp_5),
.tx_digitalreset (tx_digitalreset_sqcnr_5),
.rx_rmfifodatadeleted(rx_rmfifodatadeleted[5]),
.rx_rmfifodatainserted(rx_rmfifodatainserted[5]),
.rx_runningdisp(rx_runningdisp[5]),
.pll_powerdown(gxb_pwrdn_in_sig[5]),
.pll_locked(pll_locked_5)
);
defparam
the_altera_tse_gxb_gige_inst_5.ENABLE_ALT_RECONFIG = ENABLE_ALT_RECONFIG,
the_altera_tse_gxb_gige_inst_5.ENABLE_SGMII = ENABLE_SGMII,
the_altera_tse_gxb_gige_inst_5.STARTING_CHANNEL_NUMBER = STARTING_CHANNEL_NUMBER + 20,
the_altera_tse_gxb_gige_inst_5.DEVICE_FAMILY = DEVICE_FAMILY;
end
else
begin
assign reconfig_fromgxb_5 = {17{1'b0}};
assign led_char_err_gx[5] = 1'b0;
assign link_status[5] = 1'b0;
assign led_disp_err_5 = 1'b0;
assign txp_5 = 1'b0;
assign pcs_clk_c5 = 1'b0;
end
endgenerate
// #######################################################################
// ############### CHANNEL 6 LOGIC/COMPONENTS ###############
// #######################################################################
// Export powerdown signal or wire it internally
// ---------------------------------------------
reg data_in_6,gxb_pwrdn_in_sig_clk_6;
generate if (EXPORT_PWRDN == 1 && MAX_CHANNELS > 6)
begin
always @(posedge clk or posedge gxb_pwrdn_in_6)
begin
if (gxb_pwrdn_in_6 == 1) begin
data_in_6 <= 1;
gxb_pwrdn_in_sig_clk_6 <= 1;
end else begin
data_in_6 <= 1'b0;
gxb_pwrdn_in_sig_clk_6 <= data_in_6;
end
end
assign gxb_pwrdn_in_sig[6] = gxb_pwrdn_in_6;
assign pcs_pwrdn_out_6 = pcs_pwrdn_out_sig[6];
end
else
begin
assign gxb_pwrdn_in_sig[6] = pcs_pwrdn_out_sig[6];
assign pcs_pwrdn_out_6 = 1'b0;
always@(*) begin
gxb_pwrdn_in_sig_clk_6 = gxb_pwrdn_in_sig[6];
end
end
endgenerate
generate if (MAX_CHANNELS > 6)
begin
wire locked_signal_6;
// Reset logic used to reset the PMA blocks
// ----------------------------------------
// ALTGX Reset Sequencer
altera_tse_reset_sequencer altera_tse_reset_sequencer_inst_6(
// User inputs and outputs
.clock(clk),
.reset_all(reset|gxb_pwrdn_in_sig_clk_6),
//.reset_tx_digital(reset_ref_clk),
//.reset_rx_digital(reset_ref_clk),
.powerdown_all(reset_posedge),
.tx_ready(), // output
.rx_ready(), // output
// I/O transceiver and status
.pll_powerdown(pll_powerdown_sqcnr_6),// output
.tx_digitalreset(tx_digitalreset_sqcnr_6),// output
.rx_analogreset(rx_analogreset_sqcnr_6),// output
.rx_digitalreset(rx_digitalreset_sqcnr_6),// output
.gxb_powerdown(gxb_powerdown_sqcnr_6),// output
.pll_is_locked(locked_signal_6),
.rx_is_lockedtodata(rx_freqlocked_6),
.manual_mode(1'b0),
.rx_oc_busy(reconfig_busy_6)
);
assign locked_signal_6 = (reset? 1'b0: pll_locked_6);
// Instantiation of the Alt2gxb and Alt4gxb block as the PMA for Stratix_II_GX ,ArriaGX and Stratix IV devices
// -----------------------------------------------------------------------------------
// Aligned Rx_sync from gxb
// -------------------------------
altera_tse_reset_synchronizer ch_6_reset_sync_0 (
.clk(rx_pcs_clk_c6),
.reset_in(rx_digitalreset_sqcnr_6),
.reset_out(reset_rx_pcs_clk_c6_int)
);
altera_tse_gxb_aligned_rxsync the_altera_tse_gxb_aligned_rxsync_6
(
.clk(rx_pcs_clk_c6),
.reset(reset_rx_pcs_clk_c6_int),
//input (from alt2gxb)
.alt_dataout(rx_frame_6),
.alt_sync(rx_syncstatus[6]),
.alt_disperr(rx_disp_err[6]),
.alt_ctrldetect(rx_kchar_6),
.alt_errdetect(rx_char_err_gx[6]),
.alt_rmfifodatadeleted(rx_rmfifodatadeleted[6]),
.alt_rmfifodatainserted(rx_rmfifodatainserted[6]),
.alt_runlengthviolation(rx_runlengthviolation[6]),
.alt_patterndetect(rx_patterndetect[6]),
.alt_runningdisp(rx_runningdisp[6]),
//output (to PCS)
.altpcs_dataout(pcs_rx_frame_6),
.altpcs_sync(link_status[6]),
.altpcs_disperr(led_disp_err_6),
.altpcs_ctrldetect(pcs_rx_kchar_6),
.altpcs_errdetect(led_char_err_gx[6]),
.altpcs_rmfifodatadeleted(pcs_rx_rmfifodatadeleted[6]),
.altpcs_rmfifodatainserted(pcs_rx_rmfifodatainserted[6]),
.altpcs_carrierdetect(pcs_rx_carrierdetected[6])
) ;
defparam
the_altera_tse_gxb_aligned_rxsync_6.DEVICE_FAMILY = DEVICE_FAMILY;
// Altgxb in GIGE mode
// --------------------
altera_tse_gxb_gige_inst the_altera_tse_gxb_gige_inst_6
(
.cal_blk_clk (gxb_cal_blk_clk),
.gxb_powerdown (gxb_pwrdn_in_sig[6]),
.pll_inclk (ref_clk),
.rx_recovclkout(rx_recovclkout_6),
.reconfig_clk(reconfig_clk_6),
.reconfig_togxb(reconfig_togxb_6),
.reconfig_fromgxb(reconfig_fromgxb_6),
.rx_analogreset (rx_analogreset_sqcnr_6),
.rx_cruclk (ref_clk),
.rx_ctrldetect (rx_kchar_6),
.rx_clkout (rx_pcs_clk_c6),
.rx_datain (rxp_6),
.rx_dataout (rx_frame_6),
.rx_digitalreset (rx_digitalreset_sqcnr_6),
.rx_disperr (rx_disp_err[6]),
.rx_errdetect (rx_char_err_gx[6]),
.rx_patterndetect (rx_patterndetect[6]),
.rx_rlv (rx_runlengthviolation[6]),
.rx_seriallpbken (sd_loopback_6),
.rx_syncstatus (rx_syncstatus[6]),
.tx_clkout (tx_pcs_clk_c6),
.tx_ctrlenable (tx_kchar_6),
.tx_datain (tx_frame_6),
.rx_freqlocked (rx_freqlocked_6),
.tx_dataout (txp_6),
.tx_digitalreset (tx_digitalreset_sqcnr_6),
.rx_rmfifodatadeleted(rx_rmfifodatadeleted[6]),
.rx_rmfifodatainserted(rx_rmfifodatainserted[6]),
.rx_runningdisp(rx_runningdisp[6]),
.pll_powerdown(gxb_pwrdn_in_sig[6]),
.pll_locked(pll_locked_6)
);
defparam
the_altera_tse_gxb_gige_inst_6.ENABLE_ALT_RECONFIG = ENABLE_ALT_RECONFIG,
the_altera_tse_gxb_gige_inst_6.ENABLE_SGMII = ENABLE_SGMII,
the_altera_tse_gxb_gige_inst_6.STARTING_CHANNEL_NUMBER = STARTING_CHANNEL_NUMBER + 24,
the_altera_tse_gxb_gige_inst_6.DEVICE_FAMILY = DEVICE_FAMILY;
end
else
begin
assign reconfig_fromgxb_6 = {17{1'b0}};
assign led_char_err_gx[6] = 1'b0;
assign link_status[6] = 1'b0;
assign led_disp_err_6 = 1'b0;
assign txp_6 = 1'b0;
assign pcs_clk_c6 = 1'b0;
end
endgenerate
// #######################################################################
// ############### CHANNEL 7 LOGIC/COMPONENTS ###############
// #######################################################################
// Export powerdown signal or wire it internally
// ---------------------------------------------
reg data_in_7,gxb_pwrdn_in_sig_clk_7;
generate if (EXPORT_PWRDN == 1 && MAX_CHANNELS > 7)
begin
always @(posedge clk or posedge gxb_pwrdn_in_7)
begin
if (gxb_pwrdn_in_7 == 1) begin
data_in_7 <= 1;
gxb_pwrdn_in_sig_clk_7 <= 1;
end else begin
data_in_7 <= 1'b0;
gxb_pwrdn_in_sig_clk_7 <= data_in_7;
end
end
assign gxb_pwrdn_in_sig[7] = gxb_pwrdn_in_7;
assign pcs_pwrdn_out_7 = pcs_pwrdn_out_sig[7];
end
else
begin
assign gxb_pwrdn_in_sig[7] = pcs_pwrdn_out_sig[7];
assign pcs_pwrdn_out_7 = 1'b0;
always@(*) begin
gxb_pwrdn_in_sig_clk_7 = gxb_pwrdn_in_sig[7];
end
end
endgenerate
generate if (MAX_CHANNELS > 7)
begin
wire locked_signal_7;
// Reset logic used to reset the PMA blocks
// ----------------------------------------
// ALTGX Reset Sequencer
altera_tse_reset_sequencer altera_tse_reset_sequencer_inst_7(
// User inputs and outputs
.clock(clk),
.reset_all(reset|gxb_pwrdn_in_sig_clk_7),
//.reset_tx_digital(reset_ref_clk),
//.reset_rx_digital(reset_ref_clk),
.powerdown_all(reset_posedge),
.tx_ready(), // output
.rx_ready(), // output
// I/O transceiver and status
.pll_powerdown(pll_powerdown_sqcnr_7),// output
.tx_digitalreset(tx_digitalreset_sqcnr_7),// output
.rx_analogreset(rx_analogreset_sqcnr_7),// output
.rx_digitalreset(rx_digitalreset_sqcnr_7),// output
.gxb_powerdown(gxb_powerdown_sqcnr_7),// output
.pll_is_locked(locked_signal_7),
.rx_is_lockedtodata(rx_freqlocked_7),
.manual_mode(1'b0),
.rx_oc_busy(reconfig_busy_7)
);
assign locked_signal_7 = (reset? 1'b0: pll_locked_7);
// Instantiation of the Alt2gxb and Alt4gxb block as the PMA for Stratix_II_GX ,ArriaGX and Stratix IV devices
// -----------------------------------------------------------------------------------
// Aligned Rx_sync from gxb
// -------------------------------
altera_tse_reset_synchronizer ch_7_reset_sync_0 (
.clk(rx_pcs_clk_c7),
.reset_in(rx_digitalreset_sqcnr_7),
.reset_out(reset_rx_pcs_clk_c7_int)
);
altera_tse_gxb_aligned_rxsync the_altera_tse_gxb_aligned_rxsync_7
(
.clk(rx_pcs_clk_c7),
.reset(reset_rx_pcs_clk_c7_int),
//input (from alt2gxb)
.alt_dataout(rx_frame_7),
.alt_sync(rx_syncstatus[7]),
.alt_disperr(rx_disp_err[7]),
.alt_ctrldetect(rx_kchar_7),
.alt_errdetect(rx_char_err_gx[7]),
.alt_rmfifodatadeleted(rx_rmfifodatadeleted[7]),
.alt_rmfifodatainserted(rx_rmfifodatainserted[7]),
.alt_runlengthviolation(rx_runlengthviolation[7]),
.alt_patterndetect(rx_patterndetect[7]),
.alt_runningdisp(rx_runningdisp[7]),
//output (to PCS)
.altpcs_dataout(pcs_rx_frame_7),
.altpcs_sync(link_status[7]),
.altpcs_disperr(led_disp_err_7),
.altpcs_ctrldetect(pcs_rx_kchar_7),
.altpcs_errdetect(led_char_err_gx[7]),
.altpcs_rmfifodatadeleted(pcs_rx_rmfifodatadeleted[7]),
.altpcs_rmfifodatainserted(pcs_rx_rmfifodatainserted[7]),
.altpcs_carrierdetect(pcs_rx_carrierdetected[7])
) ;
defparam
the_altera_tse_gxb_aligned_rxsync_7.DEVICE_FAMILY = DEVICE_FAMILY;
// Altgxb in GIGE mode
// --------------------
altera_tse_gxb_gige_inst the_altera_tse_gxb_gige_inst_7
(
.cal_blk_clk (gxb_cal_blk_clk),
.gxb_powerdown (gxb_pwrdn_in_sig[7]),
.pll_inclk (ref_clk),
.rx_recovclkout(rx_recovclkout_7),
.reconfig_clk(reconfig_clk_7),
.reconfig_togxb(reconfig_togxb_7),
.reconfig_fromgxb(reconfig_fromgxb_7),
.rx_analogreset (rx_analogreset_sqcnr_7),
.rx_cruclk (ref_clk),
.rx_ctrldetect (rx_kchar_7),
.rx_clkout (rx_pcs_clk_c7),
.rx_datain (rxp_7),
.rx_dataout (rx_frame_7),
.rx_digitalreset (rx_digitalreset_sqcnr_7),
.rx_disperr (rx_disp_err[7]),
.rx_errdetect (rx_char_err_gx[7]),
.rx_patterndetect (rx_patterndetect[7]),
.rx_rlv (rx_runlengthviolation[7]),
.rx_seriallpbken (sd_loopback_7),
.rx_syncstatus (rx_syncstatus[7]),
.tx_clkout (tx_pcs_clk_c7),
.tx_ctrlenable (tx_kchar_7),
.tx_datain (tx_frame_7),
.rx_freqlocked (rx_freqlocked_7),
.tx_dataout (txp_7),
.tx_digitalreset (tx_digitalreset_sqcnr_7),
.rx_rmfifodatadeleted(rx_rmfifodatadeleted[7]),
.rx_rmfifodatainserted(rx_rmfifodatainserted[7]),
.rx_runningdisp(rx_runningdisp[7]),
.pll_powerdown(gxb_pwrdn_in_sig[7]),
.pll_locked(pll_locked_7)
);
defparam
the_altera_tse_gxb_gige_inst_7.ENABLE_ALT_RECONFIG = ENABLE_ALT_RECONFIG,
the_altera_tse_gxb_gige_inst_7.ENABLE_SGMII = ENABLE_SGMII,
the_altera_tse_gxb_gige_inst_7.STARTING_CHANNEL_NUMBER = STARTING_CHANNEL_NUMBER + 28,
the_altera_tse_gxb_gige_inst_7.DEVICE_FAMILY = DEVICE_FAMILY;
end
else
begin
assign reconfig_fromgxb_7 = {17{1'b0}};
assign led_char_err_gx[7] = 1'b0;
assign link_status[7] = 1'b0;
assign led_disp_err_7 = 1'b0;
assign txp_7 = 1'b0;
assign pcs_clk_c7 = 1'b0;
end
endgenerate
// #######################################################################
// ############### CHANNEL 8 LOGIC/COMPONENTS ###############
// #######################################################################
// Export powerdown signal or wire it internally
// ---------------------------------------------
reg data_in_8,gxb_pwrdn_in_sig_clk_8;
generate if (EXPORT_PWRDN == 1 && MAX_CHANNELS > 8)
begin
always @(posedge clk or posedge gxb_pwrdn_in_8)
begin
if (gxb_pwrdn_in_8 == 1) begin
data_in_8 <= 1;
gxb_pwrdn_in_sig_clk_8 <= 1;
end else begin
data_in_8 <= 1'b0;
gxb_pwrdn_in_sig_clk_8 <= data_in_8;
end
end
assign gxb_pwrdn_in_sig[8] = gxb_pwrdn_in_8;
assign pcs_pwrdn_out_8 = pcs_pwrdn_out_sig[8];
end
else
begin
assign gxb_pwrdn_in_sig[8] = pcs_pwrdn_out_sig[8];
assign pcs_pwrdn_out_8 = 1'b0;
always@(*) begin
gxb_pwrdn_in_sig_clk_8 = gxb_pwrdn_in_sig[8];
end
end
endgenerate
generate if (MAX_CHANNELS > 8)
begin
wire locked_signal_8;
// Reset logic used to reset the PMA blocks
// ----------------------------------------
// ALTGX Reset Sequencer
altera_tse_reset_sequencer altera_tse_reset_sequencer_inst_8(
// User inputs and outputs
.clock(clk),
.reset_all(reset|gxb_pwrdn_in_sig_clk_8),
//.reset_tx_digital(reset_ref_clk),
//.reset_rx_digital(reset_ref_clk),
.powerdown_all(reset_posedge),
.tx_ready(), // output
.rx_ready(), // output
// I/O transceiver and status
.pll_powerdown(pll_powerdown_sqcnr_8),// output
.tx_digitalreset(tx_digitalreset_sqcnr_8),// output
.rx_analogreset(rx_analogreset_sqcnr_8),// output
.rx_digitalreset(rx_digitalreset_sqcnr_8),// output
.gxb_powerdown(gxb_powerdown_sqcnr_8),// output
.pll_is_locked(locked_signal_8),
.rx_is_lockedtodata(rx_freqlocked_8),
.manual_mode(1'b0),
.rx_oc_busy(reconfig_busy_8)
);
assign locked_signal_8 = (reset? 1'b0: pll_locked_8);
// Instantiation of the Alt2gxb and Alt4gxb block as the PMA for Stratix_II_GX ,ArriaGX and Stratix IV devices
// -----------------------------------------------------------------------------------
// Aligned Rx_sync from gxb
// -------------------------------
altera_tse_reset_synchronizer ch_8_reset_sync_0 (
.clk(rx_pcs_clk_c8),
.reset_in(rx_digitalreset_sqcnr_8),
.reset_out(reset_rx_pcs_clk_c8_int)
);
altera_tse_gxb_aligned_rxsync the_altera_tse_gxb_aligned_rxsync_8
(
.clk(rx_pcs_clk_c8),
.reset(reset_rx_pcs_clk_c8_int),
//input (from alt2gxb)
.alt_dataout(rx_frame_8),
.alt_sync(rx_syncstatus[8]),
.alt_disperr(rx_disp_err[8]),
.alt_ctrldetect(rx_kchar_8),
.alt_errdetect(rx_char_err_gx[8]),
.alt_rmfifodatadeleted(rx_rmfifodatadeleted[8]),
.alt_rmfifodatainserted(rx_rmfifodatainserted[8]),
.alt_runlengthviolation(rx_runlengthviolation[8]),
.alt_patterndetect(rx_patterndetect[8]),
.alt_runningdisp(rx_runningdisp[8]),
//output (to PCS)
.altpcs_dataout(pcs_rx_frame_8),
.altpcs_sync(link_status[8]),
.altpcs_disperr(led_disp_err_8),
.altpcs_ctrldetect(pcs_rx_kchar_8),
.altpcs_errdetect(led_char_err_gx[8]),
.altpcs_rmfifodatadeleted(pcs_rx_rmfifodatadeleted[8]),
.altpcs_rmfifodatainserted(pcs_rx_rmfifodatainserted[8]),
.altpcs_carrierdetect(pcs_rx_carrierdetected[8])
) ;
defparam
the_altera_tse_gxb_aligned_rxsync_8.DEVICE_FAMILY = DEVICE_FAMILY;
// Altgxb in GIGE mode
// --------------------
altera_tse_gxb_gige_inst the_altera_tse_gxb_gige_inst_8
(
.cal_blk_clk (gxb_cal_blk_clk),
.gxb_powerdown (gxb_pwrdn_in_sig[8]),
.pll_inclk (ref_clk),
.rx_recovclkout(rx_recovclkout_8),
.reconfig_clk(reconfig_clk_8),
.reconfig_togxb(reconfig_togxb_8),
.reconfig_fromgxb(reconfig_fromgxb_8),
.rx_analogreset (rx_analogreset_sqcnr_8),
.rx_cruclk (ref_clk),
.rx_ctrldetect (rx_kchar_8),
.rx_clkout (rx_pcs_clk_c8),
.rx_datain (rxp_8),
.rx_dataout (rx_frame_8),
.rx_digitalreset (rx_digitalreset_sqcnr_8),
.rx_disperr (rx_disp_err[8]),
.rx_errdetect (rx_char_err_gx[8]),
.rx_patterndetect (rx_patterndetect[8]),
.rx_rlv (rx_runlengthviolation[8]),
.rx_seriallpbken (sd_loopback_8),
.rx_syncstatus (rx_syncstatus[8]),
.tx_clkout (tx_pcs_clk_c8),
.tx_ctrlenable (tx_kchar_8),
.tx_datain (tx_frame_8),
.rx_freqlocked (rx_freqlocked_8),
.tx_dataout (txp_8),
.tx_digitalreset (tx_digitalreset_sqcnr_8),
.rx_rmfifodatadeleted(rx_rmfifodatadeleted[8]),
.rx_rmfifodatainserted(rx_rmfifodatainserted[8]),
.rx_runningdisp(rx_runningdisp[8]),
.pll_powerdown(gxb_pwrdn_in_sig[8]),
.pll_locked(pll_locked_8)
);
defparam
the_altera_tse_gxb_gige_inst_8.ENABLE_ALT_RECONFIG = ENABLE_ALT_RECONFIG,
the_altera_tse_gxb_gige_inst_8.ENABLE_SGMII = ENABLE_SGMII,
the_altera_tse_gxb_gige_inst_8.STARTING_CHANNEL_NUMBER = STARTING_CHANNEL_NUMBER + 32,
the_altera_tse_gxb_gige_inst_8.DEVICE_FAMILY = DEVICE_FAMILY;
end
else
begin
assign reconfig_fromgxb_8 = {17{1'b0}};
assign led_char_err_gx[8] = 1'b0;
assign link_status[8] = 1'b0;
assign led_disp_err_8 = 1'b0;
assign txp_8 = 1'b0;
assign pcs_clk_c8 = 1'b0;
end
endgenerate
// #######################################################################
// ############### CHANNEL 9 LOGIC/COMPONENTS ###############
// #######################################################################
// Export powerdown signal or wire it internally
// ---------------------------------------------
reg data_in_9,gxb_pwrdn_in_sig_clk_9;
generate if (EXPORT_PWRDN == 1 && MAX_CHANNELS > 9)
begin
always @(posedge clk or posedge gxb_pwrdn_in_9)
begin
if (gxb_pwrdn_in_9 == 1) begin
data_in_9 <= 1;
gxb_pwrdn_in_sig_clk_9 <= 1;
end else begin
data_in_9 <= 1'b0;
gxb_pwrdn_in_sig_clk_9 <= data_in_9;
end
end
assign gxb_pwrdn_in_sig[9] = gxb_pwrdn_in_9;
assign pcs_pwrdn_out_9 = pcs_pwrdn_out_sig[9];
end
else
begin
assign gxb_pwrdn_in_sig[9] = pcs_pwrdn_out_sig[9];
assign pcs_pwrdn_out_9 = 1'b0;
always@(*) begin
gxb_pwrdn_in_sig_clk_9 = gxb_pwrdn_in_sig[9];
end
end
endgenerate
generate if (MAX_CHANNELS > 9)
begin
wire locked_signal_9;
// Reset logic used to reset the PMA blocks
// ----------------------------------------
// ALTGX Reset Sequencer
altera_tse_reset_sequencer altera_tse_reset_sequencer_inst_9(
// User inputs and outputs
.clock(clk),
.reset_all(reset|gxb_pwrdn_in_sig_clk_9),
//.reset_tx_digital(reset_ref_clk),
//.reset_rx_digital(reset_ref_clk),
.powerdown_all(reset_posedge),
.tx_ready(), // output
.rx_ready(), // output
// I/O transceiver and status
.pll_powerdown(pll_powerdown_sqcnr_9),// output
.tx_digitalreset(tx_digitalreset_sqcnr_9),// output
.rx_analogreset(rx_analogreset_sqcnr_9),// output
.rx_digitalreset(rx_digitalreset_sqcnr_9),// output
.gxb_powerdown(gxb_powerdown_sqcnr_9),// output
.pll_is_locked(locked_signal_9),
.rx_is_lockedtodata(rx_freqlocked_9),
.manual_mode(1'b0),
.rx_oc_busy(reconfig_busy_9)
);
assign locked_signal_9 = (reset? 1'b0: pll_locked_9);
// Instantiation of the Alt2gxb and Alt4gxb block as the PMA for Stratix_II_GX ,ArriaGX and Stratix IV devices
// -----------------------------------------------------------------------------------
// Aligned Rx_sync from gxb
// -------------------------------
altera_tse_reset_synchronizer ch_9_reset_sync_0 (
.clk(rx_pcs_clk_c9),
.reset_in(rx_digitalreset_sqcnr_9),
.reset_out(reset_rx_pcs_clk_c9_int)
);
altera_tse_gxb_aligned_rxsync the_altera_tse_gxb_aligned_rxsync_9
(
.clk(rx_pcs_clk_c9),
.reset(reset_rx_pcs_clk_c9_int),
//input (from alt2gxb)
.alt_dataout(rx_frame_9),
.alt_sync(rx_syncstatus[9]),
.alt_disperr(rx_disp_err[9]),
.alt_ctrldetect(rx_kchar_9),
.alt_errdetect(rx_char_err_gx[9]),
.alt_rmfifodatadeleted(rx_rmfifodatadeleted[9]),
.alt_rmfifodatainserted(rx_rmfifodatainserted[9]),
.alt_runlengthviolation(rx_runlengthviolation[9]),
.alt_patterndetect(rx_patterndetect[9]),
.alt_runningdisp(rx_runningdisp[9]),
//output (to PCS)
.altpcs_dataout(pcs_rx_frame_9),
.altpcs_sync(link_status[9]),
.altpcs_disperr(led_disp_err_9),
.altpcs_ctrldetect(pcs_rx_kchar_9),
.altpcs_errdetect(led_char_err_gx[9]),
.altpcs_rmfifodatadeleted(pcs_rx_rmfifodatadeleted[9]),
.altpcs_rmfifodatainserted(pcs_rx_rmfifodatainserted[9]),
.altpcs_carrierdetect(pcs_rx_carrierdetected[9])
) ;
defparam
the_altera_tse_gxb_aligned_rxsync_9.DEVICE_FAMILY = DEVICE_FAMILY;
// Altgxb in GIGE mode
// --------------------
altera_tse_gxb_gige_inst the_altera_tse_gxb_gige_inst_9
(
.cal_blk_clk (gxb_cal_blk_clk),
.gxb_powerdown (gxb_pwrdn_in_sig[9]),
.pll_inclk (ref_clk),
.rx_recovclkout(rx_recovclkout_9),
.reconfig_clk(reconfig_clk_9),
.reconfig_togxb(reconfig_togxb_9),
.reconfig_fromgxb(reconfig_fromgxb_9),
.rx_analogreset (rx_analogreset_sqcnr_9),
.rx_cruclk (ref_clk),
.rx_ctrldetect (rx_kchar_9),
.rx_clkout (rx_pcs_clk_c9),
.rx_datain (rxp_9),
.rx_dataout (rx_frame_9),
.rx_digitalreset (rx_digitalreset_sqcnr_9),
.rx_disperr (rx_disp_err[9]),
.rx_errdetect (rx_char_err_gx[9]),
.rx_patterndetect (rx_patterndetect[9]),
.rx_rlv (rx_runlengthviolation[9]),
.rx_seriallpbken (sd_loopback_9),
.rx_syncstatus (rx_syncstatus[9]),
.tx_clkout (tx_pcs_clk_c9),
.tx_ctrlenable (tx_kchar_9),
.tx_datain (tx_frame_9),
.rx_freqlocked (rx_freqlocked_9),
.tx_dataout (txp_9),
.tx_digitalreset (tx_digitalreset_sqcnr_9),
.rx_rmfifodatadeleted(rx_rmfifodatadeleted[9]),
.rx_rmfifodatainserted(rx_rmfifodatainserted[9]),
.rx_runningdisp(rx_runningdisp[9]),
.pll_powerdown(gxb_pwrdn_in_sig[9]),
.pll_locked(pll_locked_9)
);
defparam
the_altera_tse_gxb_gige_inst_9.ENABLE_ALT_RECONFIG = ENABLE_ALT_RECONFIG,
the_altera_tse_gxb_gige_inst_9.ENABLE_SGMII = ENABLE_SGMII,
the_altera_tse_gxb_gige_inst_9.STARTING_CHANNEL_NUMBER = STARTING_CHANNEL_NUMBER + 36,
the_altera_tse_gxb_gige_inst_9.DEVICE_FAMILY = DEVICE_FAMILY;
end
else
begin
assign reconfig_fromgxb_9 = {17{1'b0}};
assign led_char_err_gx[9] = 1'b0;
assign link_status[9] = 1'b0;
assign led_disp_err_9 = 1'b0;
assign txp_9 = 1'b0;
assign pcs_clk_c9 = 1'b0;
end
endgenerate
// #######################################################################
// ############### CHANNEL 10 LOGIC/COMPONENTS ###############
// #######################################################################
// Export powerdown signal or wire it internally
// ---------------------------------------------
reg data_in_10,gxb_pwrdn_in_sig_clk_10;
generate if (EXPORT_PWRDN == 1 && MAX_CHANNELS > 10)
begin
always @(posedge clk or posedge gxb_pwrdn_in_10)
begin
if (gxb_pwrdn_in_10 == 1) begin
data_in_10 <= 1;
gxb_pwrdn_in_sig_clk_10 <= 1;
end else begin
data_in_10 <= 1'b0;
gxb_pwrdn_in_sig_clk_10 <= data_in_10;
end
end
assign gxb_pwrdn_in_sig[10] = gxb_pwrdn_in_10;
assign pcs_pwrdn_out_10 = pcs_pwrdn_out_sig[10];
end
else
begin
assign gxb_pwrdn_in_sig[10] = pcs_pwrdn_out_sig[10];
assign pcs_pwrdn_out_10 = 1'b0;
always@(*) begin
gxb_pwrdn_in_sig_clk_10 = gxb_pwrdn_in_sig[10];
end
end
endgenerate
generate if (MAX_CHANNELS > 10)
begin
wire locked_signal_10;
// Reset logic used to reset the PMA blocks
// ----------------------------------------
// ALTGX Reset Sequencer
altera_tse_reset_sequencer altera_tse_reset_sequencer_inst_10(
// User inputs and outputs
.clock(clk),
.reset_all(reset|gxb_pwrdn_in_sig_clk_10),
//.reset_tx_digital(reset_ref_clk),
//.reset_rx_digital(reset_ref_clk),
.powerdown_all(reset_posedge),
.tx_ready(), // output
.rx_ready(), // output
// I/O transceiver and status
.pll_powerdown(pll_powerdown_sqcnr_10),// output
.tx_digitalreset(tx_digitalreset_sqcnr_10),// output
.rx_analogreset(rx_analogreset_sqcnr_10),// output
.rx_digitalreset(rx_digitalreset_sqcnr_10),// output
.gxb_powerdown(gxb_powerdown_sqcnr_10),// output
.pll_is_locked(locked_signal_10),
.rx_is_lockedtodata(rx_freqlocked_10),
.manual_mode(1'b0),
.rx_oc_busy(reconfig_busy_10)
);
assign locked_signal_10 = (reset? 1'b0: pll_locked_10);
// Instantiation of the Alt2gxb and Alt4gxb block as the PMA for Stratix_II_GX ,ArriaGX and Stratix IV devices
// -----------------------------------------------------------------------------------
// Aligned Rx_sync from gxb
// -------------------------------
altera_tse_reset_synchronizer ch_10_reset_sync_0 (
.clk(rx_pcs_clk_c10),
.reset_in(rx_digitalreset_sqcnr_10),
.reset_out(reset_rx_pcs_clk_c10_int)
);
altera_tse_gxb_aligned_rxsync the_altera_tse_gxb_aligned_rxsync_10
(
.clk(rx_pcs_clk_c10),
.reset(reset_rx_pcs_clk_c10_int),
//input (from alt2gxb)
.alt_dataout(rx_frame_10),
.alt_sync(rx_syncstatus[10]),
.alt_disperr(rx_disp_err[10]),
.alt_ctrldetect(rx_kchar_10),
.alt_errdetect(rx_char_err_gx[10]),
.alt_rmfifodatadeleted(rx_rmfifodatadeleted[10]),
.alt_rmfifodatainserted(rx_rmfifodatainserted[10]),
.alt_runlengthviolation(rx_runlengthviolation[10]),
.alt_patterndetect(rx_patterndetect[10]),
.alt_runningdisp(rx_runningdisp[10]),
//output (to PCS)
.altpcs_dataout(pcs_rx_frame_10),
.altpcs_sync(link_status[10]),
.altpcs_disperr(led_disp_err_10),
.altpcs_ctrldetect(pcs_rx_kchar_10),
.altpcs_errdetect(led_char_err_gx[10]),
.altpcs_rmfifodatadeleted(pcs_rx_rmfifodatadeleted[10]),
.altpcs_rmfifodatainserted(pcs_rx_rmfifodatainserted[10]),
.altpcs_carrierdetect(pcs_rx_carrierdetected[10])
) ;
defparam
the_altera_tse_gxb_aligned_rxsync_10.DEVICE_FAMILY = DEVICE_FAMILY;
// Altgxb in GIGE mode
// --------------------
altera_tse_gxb_gige_inst the_altera_tse_gxb_gige_inst_10
(
.cal_blk_clk (gxb_cal_blk_clk),
.gxb_powerdown (gxb_pwrdn_in_sig[10]),
.pll_inclk (ref_clk),
.rx_recovclkout(rx_recovclkout_10),
.reconfig_clk(reconfig_clk_10),
.reconfig_togxb(reconfig_togxb_10),
.reconfig_fromgxb(reconfig_fromgxb_10),
.rx_analogreset (rx_analogreset_sqcnr_10),
.rx_cruclk (ref_clk),
.rx_ctrldetect (rx_kchar_10),
.rx_clkout (rx_pcs_clk_c10),
.rx_datain (rxp_10),
.rx_dataout (rx_frame_10),
.rx_digitalreset (rx_digitalreset_sqcnr_10),
.rx_disperr (rx_disp_err[10]),
.rx_errdetect (rx_char_err_gx[10]),
.rx_patterndetect (rx_patterndetect[10]),
.rx_rlv (rx_runlengthviolation[10]),
.rx_seriallpbken (sd_loopback_10),
.rx_syncstatus (rx_syncstatus[10]),
.tx_clkout (tx_pcs_clk_c10),
.tx_ctrlenable (tx_kchar_10),
.tx_datain (tx_frame_10),
.rx_freqlocked (rx_freqlocked_10),
.tx_dataout (txp_10),
.tx_digitalreset (tx_digitalreset_sqcnr_10),
.rx_rmfifodatadeleted(rx_rmfifodatadeleted[10]),
.rx_rmfifodatainserted(rx_rmfifodatainserted[10]),
.rx_runningdisp(rx_runningdisp[10]),
.pll_powerdown(gxb_pwrdn_in_sig[10]),
.pll_locked(pll_locked_10)
);
defparam
the_altera_tse_gxb_gige_inst_10.ENABLE_ALT_RECONFIG = ENABLE_ALT_RECONFIG,
the_altera_tse_gxb_gige_inst_10.ENABLE_SGMII = ENABLE_SGMII,
the_altera_tse_gxb_gige_inst_10.STARTING_CHANNEL_NUMBER = STARTING_CHANNEL_NUMBER + 40,
the_altera_tse_gxb_gige_inst_10.DEVICE_FAMILY = DEVICE_FAMILY;
end
else
begin
assign reconfig_fromgxb_10 = {17{1'b0}};
assign led_char_err_gx[10] = 1'b0;
assign link_status[10] = 1'b0;
assign led_disp_err_10 = 1'b0;
assign txp_10 = 1'b0;
assign pcs_clk_c10 = 1'b0;
end
endgenerate
// #######################################################################
// ############### CHANNEL 11 LOGIC/COMPONENTS ###############
// #######################################################################
// Export powerdown signal or wire it internally
// ---------------------------------------------
reg data_in_11,gxb_pwrdn_in_sig_clk_11;
generate if (EXPORT_PWRDN == 1 && MAX_CHANNELS > 11)
begin
always @(posedge clk or posedge gxb_pwrdn_in_11)
begin
if (gxb_pwrdn_in_11 == 1) begin
data_in_11 <= 1;
gxb_pwrdn_in_sig_clk_11 <= 1;
end else begin
data_in_11 <= 1'b0;
gxb_pwrdn_in_sig_clk_11 <= data_in_11;
end
end
assign gxb_pwrdn_in_sig[11] = gxb_pwrdn_in_11;
assign pcs_pwrdn_out_11 = pcs_pwrdn_out_sig[11];
end
else
begin
assign gxb_pwrdn_in_sig[11] = pcs_pwrdn_out_sig[11];
assign pcs_pwrdn_out_11 = 1'b0;
always@(*) begin
gxb_pwrdn_in_sig_clk_11 = gxb_pwrdn_in_sig[11];
end
end
endgenerate
generate if (MAX_CHANNELS > 11)
begin
wire locked_signal_11;
// Reset logic used to reset the PMA blocks
// ----------------------------------------
// ALTGX Reset Sequencer
altera_tse_reset_sequencer altera_tse_reset_sequencer_inst_11(
// User inputs and outputs
.clock(clk),
.reset_all(reset|gxb_pwrdn_in_sig_clk_11),
//.reset_tx_digital(reset_ref_clk),
//.reset_rx_digital(reset_ref_clk),
.powerdown_all(reset_posedge),
.tx_ready(), // output
.rx_ready(), // output
// I/O transceiver and status
.pll_powerdown(pll_powerdown_sqcnr_11),// output
.tx_digitalreset(tx_digitalreset_sqcnr_11),// output
.rx_analogreset(rx_analogreset_sqcnr_11),// output
.rx_digitalreset(rx_digitalreset_sqcnr_11),// output
.gxb_powerdown(gxb_powerdown_sqcnr_11),// output
.pll_is_locked(locked_signal_11),
.rx_is_lockedtodata(rx_freqlocked_11),
.manual_mode(1'b0),
.rx_oc_busy(reconfig_busy_11)
);
assign locked_signal_11 = (reset? 1'b0: pll_locked_11);
// Instantiation of the Alt2gxb and Alt4gxb block as the PMA for Stratix_II_GX ,ArriaGX and Stratix IV devices
// -----------------------------------------------------------------------------------
// Aligned Rx_sync from gxb
// -------------------------------
altera_tse_reset_synchronizer ch_11_reset_sync_0 (
.clk(rx_pcs_clk_c11),
.reset_in(rx_digitalreset_sqcnr_11),
.reset_out(reset_rx_pcs_clk_c11_int)
);
altera_tse_gxb_aligned_rxsync the_altera_tse_gxb_aligned_rxsync_11
(
.clk(rx_pcs_clk_c11),
.reset(reset_rx_pcs_clk_c11_int),
//input (from alt2gxb)
.alt_dataout(rx_frame_11),
.alt_sync(rx_syncstatus[11]),
.alt_disperr(rx_disp_err[11]),
.alt_ctrldetect(rx_kchar_11),
.alt_errdetect(rx_char_err_gx[11]),
.alt_rmfifodatadeleted(rx_rmfifodatadeleted[11]),
.alt_rmfifodatainserted(rx_rmfifodatainserted[11]),
.alt_runlengthviolation(rx_runlengthviolation[11]),
.alt_patterndetect(rx_patterndetect[11]),
.alt_runningdisp(rx_runningdisp[11]),
//output (to PCS)
.altpcs_dataout(pcs_rx_frame_11),
.altpcs_sync(link_status[11]),
.altpcs_disperr(led_disp_err_11),
.altpcs_ctrldetect(pcs_rx_kchar_11),
.altpcs_errdetect(led_char_err_gx[11]),
.altpcs_rmfifodatadeleted(pcs_rx_rmfifodatadeleted[11]),
.altpcs_rmfifodatainserted(pcs_rx_rmfifodatainserted[11]),
.altpcs_carrierdetect(pcs_rx_carrierdetected[11])
) ;
defparam
the_altera_tse_gxb_aligned_rxsync_11.DEVICE_FAMILY = DEVICE_FAMILY;
// Altgxb in GIGE mode
// --------------------
altera_tse_gxb_gige_inst the_altera_tse_gxb_gige_inst_11
(
.cal_blk_clk (gxb_cal_blk_clk),
.gxb_powerdown (gxb_pwrdn_in_sig[11]),
.pll_inclk (ref_clk),
.rx_recovclkout(rx_recovclkout_11),
.reconfig_clk(reconfig_clk_11),
.reconfig_togxb(reconfig_togxb_11),
.reconfig_fromgxb(reconfig_fromgxb_11),
.rx_analogreset (rx_analogreset_sqcnr_11),
.rx_cruclk (ref_clk),
.rx_ctrldetect (rx_kchar_11),
.rx_clkout (rx_pcs_clk_c11),
.rx_datain (rxp_11),
.rx_dataout (rx_frame_11),
.rx_digitalreset (rx_digitalreset_sqcnr_11),
.rx_disperr (rx_disp_err[11]),
.rx_errdetect (rx_char_err_gx[11]),
.rx_patterndetect (rx_patterndetect[11]),
.rx_rlv (rx_runlengthviolation[11]),
.rx_seriallpbken (sd_loopback_11),
.rx_syncstatus (rx_syncstatus[11]),
.tx_clkout (tx_pcs_clk_c11),
.tx_ctrlenable (tx_kchar_11),
.tx_datain (tx_frame_11),
.rx_freqlocked (rx_freqlocked_11),
.tx_dataout (txp_11),
.tx_digitalreset (tx_digitalreset_sqcnr_11),
.rx_rmfifodatadeleted(rx_rmfifodatadeleted[11]),
.rx_rmfifodatainserted(rx_rmfifodatainserted[11]),
.rx_runningdisp(rx_runningdisp[11]),
.pll_powerdown(gxb_pwrdn_in_sig[11]),
.pll_locked(pll_locked_11)
);
defparam
the_altera_tse_gxb_gige_inst_11.ENABLE_ALT_RECONFIG = ENABLE_ALT_RECONFIG,
the_altera_tse_gxb_gige_inst_11.ENABLE_SGMII = ENABLE_SGMII,
the_altera_tse_gxb_gige_inst_11.STARTING_CHANNEL_NUMBER = STARTING_CHANNEL_NUMBER + 44,
the_altera_tse_gxb_gige_inst_11.DEVICE_FAMILY = DEVICE_FAMILY;
end
else
begin
assign reconfig_fromgxb_11 = {17{1'b0}};
assign led_char_err_gx[11] = 1'b0;
assign link_status[11] = 1'b0;
assign led_disp_err_11 = 1'b0;
assign txp_11 = 1'b0;
assign pcs_clk_c11 = 1'b0;
end
endgenerate
// #######################################################################
// ############### CHANNEL 12 LOGIC/COMPONENTS ###############
// #######################################################################
// Export powerdown signal or wire it internally
// ---------------------------------------------
reg data_in_12,gxb_pwrdn_in_sig_clk_12;
generate if (EXPORT_PWRDN == 1 && MAX_CHANNELS > 12)
begin
always @(posedge clk or posedge gxb_pwrdn_in_12)
begin
if (gxb_pwrdn_in_12 == 1) begin
data_in_12 <= 1;
gxb_pwrdn_in_sig_clk_12 <= 1;
end else begin
data_in_12 <= 1'b0;
gxb_pwrdn_in_sig_clk_12 <= data_in_12;
end
end
assign gxb_pwrdn_in_sig[12] = gxb_pwrdn_in_12;
assign pcs_pwrdn_out_12 = pcs_pwrdn_out_sig[12];
end
else
begin
assign gxb_pwrdn_in_sig[12] = pcs_pwrdn_out_sig[12];
assign pcs_pwrdn_out_12 = 1'b0;
always@(*) begin
gxb_pwrdn_in_sig_clk_12 = gxb_pwrdn_in_sig[12];
end
end
endgenerate
generate if (MAX_CHANNELS > 12)
begin
wire locked_signal_12;
// Reset logic used to reset the PMA blocks
// ----------------------------------------
// ALTGX Reset Sequencer
altera_tse_reset_sequencer altera_tse_reset_sequencer_inst_12(
// User inputs and outputs
.clock(clk),
.reset_all(reset|gxb_pwrdn_in_sig_clk_12),
//.reset_tx_digital(reset_ref_clk),
//.reset_rx_digital(reset_ref_clk),
.powerdown_all(reset_posedge),
.tx_ready(), // output
.rx_ready(), // output
// I/O transceiver and status
.pll_powerdown(pll_powerdown_sqcnr_12),// output
.tx_digitalreset(tx_digitalreset_sqcnr_12),// output
.rx_analogreset(rx_analogreset_sqcnr_12),// output
.rx_digitalreset(rx_digitalreset_sqcnr_12),// output
.gxb_powerdown(gxb_powerdown_sqcnr_12),// output
.pll_is_locked(locked_signal_12),
.rx_is_lockedtodata(rx_freqlocked_12),
.manual_mode(1'b0),
.rx_oc_busy(reconfig_busy_12)
);
assign locked_signal_12 = (reset? 1'b0: pll_locked_12);
// Instantiation of the Alt2gxb and Alt4gxb block as the PMA for Stratix_II_GX ,ArriaGX and Stratix IV devices
// -----------------------------------------------------------------------------------
// Aligned Rx_sync from gxb
// -------------------------------
altera_tse_reset_synchronizer ch_12_reset_sync_0 (
.clk(rx_pcs_clk_c12),
.reset_in(rx_digitalreset_sqcnr_12),
.reset_out(reset_rx_pcs_clk_c12_int)
);
altera_tse_gxb_aligned_rxsync the_altera_tse_gxb_aligned_rxsync_12
(
.clk(rx_pcs_clk_c12),
.reset(reset_rx_pcs_clk_c12_int),
//input (from alt2gxb)
.alt_dataout(rx_frame_12),
.alt_sync(rx_syncstatus[12]),
.alt_disperr(rx_disp_err[12]),
.alt_ctrldetect(rx_kchar_12),
.alt_errdetect(rx_char_err_gx[12]),
.alt_rmfifodatadeleted(rx_rmfifodatadeleted[12]),
.alt_rmfifodatainserted(rx_rmfifodatainserted[12]),
.alt_runlengthviolation(rx_runlengthviolation[12]),
.alt_patterndetect(rx_patterndetect[12]),
.alt_runningdisp(rx_runningdisp[12]),
//output (to PCS)
.altpcs_dataout(pcs_rx_frame_12),
.altpcs_sync(link_status[12]),
.altpcs_disperr(led_disp_err_12),
.altpcs_ctrldetect(pcs_rx_kchar_12),
.altpcs_errdetect(led_char_err_gx[12]),
.altpcs_rmfifodatadeleted(pcs_rx_rmfifodatadeleted[12]),
.altpcs_rmfifodatainserted(pcs_rx_rmfifodatainserted[12]),
.altpcs_carrierdetect(pcs_rx_carrierdetected[12])
) ;
defparam
the_altera_tse_gxb_aligned_rxsync_12.DEVICE_FAMILY = DEVICE_FAMILY;
// Altgxb in GIGE mode
// --------------------
altera_tse_gxb_gige_inst the_altera_tse_gxb_gige_inst_12
(
.cal_blk_clk (gxb_cal_blk_clk),
.gxb_powerdown (gxb_pwrdn_in_sig[12]),
.pll_inclk (ref_clk),
.rx_recovclkout(rx_recovclkout_12),
.reconfig_clk(reconfig_clk_12),
.reconfig_togxb(reconfig_togxb_12),
.reconfig_fromgxb(reconfig_fromgxb_12),
.rx_analogreset (rx_analogreset_sqcnr_12),
.rx_cruclk (ref_clk),
.rx_ctrldetect (rx_kchar_12),
.rx_clkout (rx_pcs_clk_c12),
.rx_datain (rxp_12),
.rx_dataout (rx_frame_12),
.rx_digitalreset (rx_digitalreset_sqcnr_12),
.rx_disperr (rx_disp_err[12]),
.rx_errdetect (rx_char_err_gx[12]),
.rx_patterndetect (rx_patterndetect[12]),
.rx_rlv (rx_runlengthviolation[12]),
.rx_seriallpbken (sd_loopback_12),
.rx_syncstatus (rx_syncstatus[12]),
.tx_clkout (tx_pcs_clk_c12),
.tx_ctrlenable (tx_kchar_12),
.tx_datain (tx_frame_12),
.rx_freqlocked (rx_freqlocked_12),
.tx_dataout (txp_12),
.tx_digitalreset (tx_digitalreset_sqcnr_12),
.rx_rmfifodatadeleted(rx_rmfifodatadeleted[12]),
.rx_rmfifodatainserted(rx_rmfifodatainserted[12]),
.rx_runningdisp(rx_runningdisp[12]),
.pll_powerdown(gxb_pwrdn_in_sig[12]),
.pll_locked(pll_locked_12)
);
defparam
the_altera_tse_gxb_gige_inst_12.ENABLE_ALT_RECONFIG = ENABLE_ALT_RECONFIG,
the_altera_tse_gxb_gige_inst_12.ENABLE_SGMII = ENABLE_SGMII,
the_altera_tse_gxb_gige_inst_12.STARTING_CHANNEL_NUMBER = STARTING_CHANNEL_NUMBER + 48,
the_altera_tse_gxb_gige_inst_12.DEVICE_FAMILY = DEVICE_FAMILY;
end
else
begin
assign reconfig_fromgxb_12 = {17{1'b0}};
assign led_char_err_gx[12] = 1'b0;
assign link_status[12] = 1'b0;
assign led_disp_err_12 = 1'b0;
assign txp_12 = 1'b0;
assign pcs_clk_c12 = 1'b0;
end
endgenerate
// #######################################################################
// ############### CHANNEL 13 LOGIC/COMPONENTS ###############
// #######################################################################
// Export powerdown signal or wire it internally
// ---------------------------------------------
reg data_in_13,gxb_pwrdn_in_sig_clk_13;
generate if (EXPORT_PWRDN == 1 && MAX_CHANNELS > 13)
begin
always @(posedge clk or posedge gxb_pwrdn_in_13)
begin
if (gxb_pwrdn_in_13 == 1) begin
data_in_13 <= 1;
gxb_pwrdn_in_sig_clk_13 <= 1;
end else begin
data_in_13 <= 1'b0;
gxb_pwrdn_in_sig_clk_13 <= data_in_13;
end
end
assign gxb_pwrdn_in_sig[13] = gxb_pwrdn_in_13;
assign pcs_pwrdn_out_13 = pcs_pwrdn_out_sig[13];
end
else
begin
assign gxb_pwrdn_in_sig[13] = pcs_pwrdn_out_sig[13];
assign pcs_pwrdn_out_13 = 1'b0;
always@(*) begin
gxb_pwrdn_in_sig_clk_13 = gxb_pwrdn_in_sig[13];
end
end
endgenerate
generate if (MAX_CHANNELS > 13)
begin
wire locked_signal_13;
// Reset logic used to reset the PMA blocks
// ----------------------------------------
// ALTGX Reset Sequencer
altera_tse_reset_sequencer altera_tse_reset_sequencer_inst_13(
// User inputs and outputs
.clock(clk),
.reset_all(reset|gxb_pwrdn_in_sig_clk_13),
//.reset_tx_digital(reset_ref_clk),
//.reset_rx_digital(reset_ref_clk),
.powerdown_all(reset_posedge),
.tx_ready(), // output
.rx_ready(), // output
// I/O transceiver and status
.pll_powerdown(pll_powerdown_sqcnr_13),// output
.tx_digitalreset(tx_digitalreset_sqcnr_13),// output
.rx_analogreset(rx_analogreset_sqcnr_13),// output
.rx_digitalreset(rx_digitalreset_sqcnr_13),// output
.gxb_powerdown(gxb_powerdown_sqcnr_13),// output
.pll_is_locked(locked_signal_13),
.rx_is_lockedtodata(rx_freqlocked_13),
.manual_mode(1'b0),
.rx_oc_busy(reconfig_busy_13)
);
assign locked_signal_13 = (reset? 1'b0: pll_locked_13);
// Instantiation of the Alt2gxb and Alt4gxb block as the PMA for Stratix_II_GX ,ArriaGX and Stratix IV devices
// -----------------------------------------------------------------------------------
// Aligned Rx_sync from gxb
// -------------------------------
altera_tse_reset_synchronizer ch_13_reset_sync_0 (
.clk(rx_pcs_clk_c13),
.reset_in(rx_digitalreset_sqcnr_13),
.reset_out(reset_rx_pcs_clk_c13_int)
);
altera_tse_gxb_aligned_rxsync the_altera_tse_gxb_aligned_rxsync_13
(
.clk(rx_pcs_clk_c13),
.reset(reset_rx_pcs_clk_c13_int),
//input (from alt2gxb)
.alt_dataout(rx_frame_13),
.alt_sync(rx_syncstatus[13]),
.alt_disperr(rx_disp_err[13]),
.alt_ctrldetect(rx_kchar_13),
.alt_errdetect(rx_char_err_gx[13]),
.alt_rmfifodatadeleted(rx_rmfifodatadeleted[13]),
.alt_rmfifodatainserted(rx_rmfifodatainserted[13]),
.alt_runlengthviolation(rx_runlengthviolation[13]),
.alt_patterndetect(rx_patterndetect[13]),
.alt_runningdisp(rx_runningdisp[13]),
//output (to PCS)
.altpcs_dataout(pcs_rx_frame_13),
.altpcs_sync(link_status[13]),
.altpcs_disperr(led_disp_err_13),
.altpcs_ctrldetect(pcs_rx_kchar_13),
.altpcs_errdetect(led_char_err_gx[13]),
.altpcs_rmfifodatadeleted(pcs_rx_rmfifodatadeleted[13]),
.altpcs_rmfifodatainserted(pcs_rx_rmfifodatainserted[13]),
.altpcs_carrierdetect(pcs_rx_carrierdetected[13])
) ;
defparam
the_altera_tse_gxb_aligned_rxsync_13.DEVICE_FAMILY = DEVICE_FAMILY;
// Altgxb in GIGE mode
// --------------------
altera_tse_gxb_gige_inst the_altera_tse_gxb_gige_inst_13
(
.cal_blk_clk (gxb_cal_blk_clk),
.gxb_powerdown (gxb_pwrdn_in_sig[13]),
.pll_inclk (ref_clk),
.rx_recovclkout(rx_recovclkout_13),
.reconfig_clk(reconfig_clk_13),
.reconfig_togxb(reconfig_togxb_13),
.reconfig_fromgxb(reconfig_fromgxb_13),
.rx_analogreset (rx_analogreset_sqcnr_13),
.rx_cruclk (ref_clk),
.rx_ctrldetect (rx_kchar_13),
.rx_clkout (rx_pcs_clk_c13),
.rx_datain (rxp_13),
.rx_dataout (rx_frame_13),
.rx_digitalreset (rx_digitalreset_sqcnr_13),
.rx_disperr (rx_disp_err[13]),
.rx_errdetect (rx_char_err_gx[13]),
.rx_patterndetect (rx_patterndetect[13]),
.rx_rlv (rx_runlengthviolation[13]),
.rx_seriallpbken (sd_loopback_13),
.rx_syncstatus (rx_syncstatus[13]),
.tx_clkout (tx_pcs_clk_c13),
.tx_ctrlenable (tx_kchar_13),
.tx_datain (tx_frame_13),
.rx_freqlocked (rx_freqlocked_13),
.tx_dataout (txp_13),
.tx_digitalreset (tx_digitalreset_sqcnr_13),
.rx_rmfifodatadeleted(rx_rmfifodatadeleted[13]),
.rx_rmfifodatainserted(rx_rmfifodatainserted[13]),
.rx_runningdisp(rx_runningdisp[13]),
.pll_powerdown(gxb_pwrdn_in_sig[13]),
.pll_locked(pll_locked_13)
);
defparam
the_altera_tse_gxb_gige_inst_13.ENABLE_ALT_RECONFIG = ENABLE_ALT_RECONFIG,
the_altera_tse_gxb_gige_inst_13.ENABLE_SGMII = ENABLE_SGMII,
the_altera_tse_gxb_gige_inst_13.STARTING_CHANNEL_NUMBER = STARTING_CHANNEL_NUMBER + 52,
the_altera_tse_gxb_gige_inst_13.DEVICE_FAMILY = DEVICE_FAMILY;
end
else
begin
assign reconfig_fromgxb_13 = {17{1'b0}};
assign led_char_err_gx[13] = 1'b0;
assign link_status[13] = 1'b0;
assign led_disp_err_13 = 1'b0;
assign txp_13 = 1'b0;
assign pcs_clk_c13 = 1'b0;
end
endgenerate
// #######################################################################
// ############### CHANNEL 14 LOGIC/COMPONENTS ###############
// #######################################################################
// Export powerdown signal or wire it internally
// ---------------------------------------------
reg data_in_14,gxb_pwrdn_in_sig_clk_14;
generate if (EXPORT_PWRDN == 1 && MAX_CHANNELS > 14)
begin
always @(posedge clk or posedge gxb_pwrdn_in_14)
begin
if (gxb_pwrdn_in_14 == 1) begin
data_in_14 <= 1;
gxb_pwrdn_in_sig_clk_14 <= 1;
end else begin
data_in_14 <= 1'b0;
gxb_pwrdn_in_sig_clk_14 <= data_in_14;
end
end
assign gxb_pwrdn_in_sig[14] = gxb_pwrdn_in_14;
assign pcs_pwrdn_out_14 = pcs_pwrdn_out_sig[14];
end
else
begin
assign gxb_pwrdn_in_sig[14] = pcs_pwrdn_out_sig[14];
assign pcs_pwrdn_out_14 = 1'b0;
always@(*) begin
gxb_pwrdn_in_sig_clk_14 = gxb_pwrdn_in_sig[14];
end
end
endgenerate
generate if (MAX_CHANNELS > 14)
begin
wire locked_signal_14;
// Reset logic used to reset the PMA blocks
// ----------------------------------------
// ALTGX Reset Sequencer
altera_tse_reset_sequencer altera_tse_reset_sequencer_inst_14(
// User inputs and outputs
.clock(clk),
.reset_all(reset|gxb_pwrdn_in_sig_clk_14),
//.reset_tx_digital(reset_ref_clk),
//.reset_rx_digital(reset_ref_clk),
.powerdown_all(reset_posedge),
.tx_ready(), // output
.rx_ready(), // output
// I/O transceiver and status
.pll_powerdown(pll_powerdown_sqcnr_14),// output
.tx_digitalreset(tx_digitalreset_sqcnr_14),// output
.rx_analogreset(rx_analogreset_sqcnr_14),// output
.rx_digitalreset(rx_digitalreset_sqcnr_14),// output
.gxb_powerdown(gxb_powerdown_sqcnr_14),// output
.pll_is_locked(locked_signal_14),
.rx_is_lockedtodata(rx_freqlocked_14),
.manual_mode(1'b0),
.rx_oc_busy(reconfig_busy_14)
);
assign locked_signal_14 = (reset? 1'b0: pll_locked_14);
// Instantiation of the Alt2gxb and Alt4gxb block as the PMA for Stratix_II_GX ,ArriaGX and Stratix IV devices
// -----------------------------------------------------------------------------------
// Aligned Rx_sync from gxb
// -------------------------------
altera_tse_reset_synchronizer ch_14_reset_sync_0 (
.clk(rx_pcs_clk_c14),
.reset_in(rx_digitalreset_sqcnr_14),
.reset_out(reset_rx_pcs_clk_c14_int)
);
altera_tse_gxb_aligned_rxsync the_altera_tse_gxb_aligned_rxsync_14
(
.clk(rx_pcs_clk_c14),
.reset(reset_rx_pcs_clk_c14_int),
//input (from alt2gxb)
.alt_dataout(rx_frame_14),
.alt_sync(rx_syncstatus[14]),
.alt_disperr(rx_disp_err[14]),
.alt_ctrldetect(rx_kchar_14),
.alt_errdetect(rx_char_err_gx[14]),
.alt_rmfifodatadeleted(rx_rmfifodatadeleted[14]),
.alt_rmfifodatainserted(rx_rmfifodatainserted[14]),
.alt_runlengthviolation(rx_runlengthviolation[14]),
.alt_patterndetect(rx_patterndetect[14]),
.alt_runningdisp(rx_runningdisp[14]),
//output (to PCS)
.altpcs_dataout(pcs_rx_frame_14),
.altpcs_sync(link_status[14]),
.altpcs_disperr(led_disp_err_14),
.altpcs_ctrldetect(pcs_rx_kchar_14),
.altpcs_errdetect(led_char_err_gx[14]),
.altpcs_rmfifodatadeleted(pcs_rx_rmfifodatadeleted[14]),
.altpcs_rmfifodatainserted(pcs_rx_rmfifodatainserted[14]),
.altpcs_carrierdetect(pcs_rx_carrierdetected[14])
) ;
defparam
the_altera_tse_gxb_aligned_rxsync_14.DEVICE_FAMILY = DEVICE_FAMILY;
// Altgxb in GIGE mode
// --------------------
altera_tse_gxb_gige_inst the_altera_tse_gxb_gige_inst_14
(
.cal_blk_clk (gxb_cal_blk_clk),
.gxb_powerdown (gxb_pwrdn_in_sig[14]),
.pll_inclk (ref_clk),
.rx_recovclkout(rx_recovclkout_14),
.reconfig_clk(reconfig_clk_14),
.reconfig_togxb(reconfig_togxb_14),
.reconfig_fromgxb(reconfig_fromgxb_14),
.rx_analogreset (rx_analogreset_sqcnr_14),
.rx_cruclk (ref_clk),
.rx_ctrldetect (rx_kchar_14),
.rx_clkout (rx_pcs_clk_c14),
.rx_datain (rxp_14),
.rx_dataout (rx_frame_14),
.rx_digitalreset (rx_digitalreset_sqcnr_14),
.rx_disperr (rx_disp_err[14]),
.rx_errdetect (rx_char_err_gx[14]),
.rx_patterndetect (rx_patterndetect[14]),
.rx_rlv (rx_runlengthviolation[14]),
.rx_seriallpbken (sd_loopback_14),
.rx_syncstatus (rx_syncstatus[14]),
.tx_clkout (tx_pcs_clk_c14),
.tx_ctrlenable (tx_kchar_14),
.tx_datain (tx_frame_14),
.rx_freqlocked (rx_freqlocked_14),
.tx_dataout (txp_14),
.tx_digitalreset (tx_digitalreset_sqcnr_14),
.rx_rmfifodatadeleted(rx_rmfifodatadeleted[14]),
.rx_rmfifodatainserted(rx_rmfifodatainserted[14]),
.rx_runningdisp(rx_runningdisp[14]),
.pll_powerdown(gxb_pwrdn_in_sig[14]),
.pll_locked(pll_locked_14)
);
defparam
the_altera_tse_gxb_gige_inst_14.ENABLE_ALT_RECONFIG = ENABLE_ALT_RECONFIG,
the_altera_tse_gxb_gige_inst_14.ENABLE_SGMII = ENABLE_SGMII,
the_altera_tse_gxb_gige_inst_14.STARTING_CHANNEL_NUMBER = STARTING_CHANNEL_NUMBER + 56,
the_altera_tse_gxb_gige_inst_14.DEVICE_FAMILY = DEVICE_FAMILY;
end
else
begin
assign reconfig_fromgxb_14 = {17{1'b0}};
assign led_char_err_gx[14] = 1'b0;
assign link_status[14] = 1'b0;
assign led_disp_err_14 = 1'b0;
assign txp_14 = 1'b0;
assign pcs_clk_c14 = 1'b0;
end
endgenerate
// #######################################################################
// ############### CHANNEL 15 LOGIC/COMPONENTS ###############
// #######################################################################
// Export powerdown signal or wire it internally
// ---------------------------------------------
reg data_in_15,gxb_pwrdn_in_sig_clk_15;
generate if (EXPORT_PWRDN == 1 && MAX_CHANNELS > 15)
begin
always @(posedge clk or posedge gxb_pwrdn_in_15)
begin
if (gxb_pwrdn_in_15 == 1) begin
data_in_15 <= 1;
gxb_pwrdn_in_sig_clk_15 <= 1;
end else begin
data_in_15 <= 1'b0;
gxb_pwrdn_in_sig_clk_15 <= data_in_15;
end
end
assign gxb_pwrdn_in_sig[15] = gxb_pwrdn_in_15;
assign pcs_pwrdn_out_15 = pcs_pwrdn_out_sig[15];
end
else
begin
assign gxb_pwrdn_in_sig[15] = pcs_pwrdn_out_sig[15];
assign pcs_pwrdn_out_15 = 1'b0;
always@(*) begin
gxb_pwrdn_in_sig_clk_15 = gxb_pwrdn_in_sig[15];
end
end
endgenerate
generate if (MAX_CHANNELS > 15)
begin
wire locked_signal_15;
// Reset logic used to reset the PMA blocks
// ----------------------------------------
// ALTGX Reset Sequencer
altera_tse_reset_sequencer altera_tse_reset_sequencer_inst_15(
// User inputs and outputs
.clock(clk),
.reset_all(reset|gxb_pwrdn_in_sig_clk_15),
//.reset_tx_digital(reset_ref_clk),
//.reset_rx_digital(reset_ref_clk),
.powerdown_all(reset_posedge),
.tx_ready(), // output
.rx_ready(), // output
// I/O transceiver and status
.pll_powerdown(pll_powerdown_sqcnr_15),// output
.tx_digitalreset(tx_digitalreset_sqcnr_15),// output
.rx_analogreset(rx_analogreset_sqcnr_15),// output
.rx_digitalreset(rx_digitalreset_sqcnr_15),// output
.gxb_powerdown(gxb_powerdown_sqcnr_15),// output
.pll_is_locked(locked_signal_15),
.rx_is_lockedtodata(rx_freqlocked_15),
.manual_mode(1'b0),
.rx_oc_busy(reconfig_busy_15)
);
assign locked_signal_15 = (reset? 1'b0: pll_locked_15);
// Instantiation of the Alt2gxb and Alt4gxb block as the PMA for Stratix_II_GX ,ArriaGX and Stratix IV devices
// -----------------------------------------------------------------------------------
// Aligned Rx_sync from gxb
// -------------------------------
altera_tse_reset_synchronizer ch_15_reset_sync_0 (
.clk(rx_pcs_clk_c15),
.reset_in(rx_digitalreset_sqcnr_15),
.reset_out(reset_rx_pcs_clk_c15_int)
);
altera_tse_gxb_aligned_rxsync the_altera_tse_gxb_aligned_rxsync_15
(
.clk(rx_pcs_clk_c15),
.reset(reset_rx_pcs_clk_c15_int),
//input (from alt2gxb)
.alt_dataout(rx_frame_15),
.alt_sync(rx_syncstatus[15]),
.alt_disperr(rx_disp_err[15]),
.alt_ctrldetect(rx_kchar_15),
.alt_errdetect(rx_char_err_gx[15]),
.alt_rmfifodatadeleted(rx_rmfifodatadeleted[15]),
.alt_rmfifodatainserted(rx_rmfifodatainserted[15]),
.alt_runlengthviolation(rx_runlengthviolation[15]),
.alt_patterndetect(rx_patterndetect[15]),
.alt_runningdisp(rx_runningdisp[15]),
//output (to PCS)
.altpcs_dataout(pcs_rx_frame_15),
.altpcs_sync(link_status[15]),
.altpcs_disperr(led_disp_err_15),
.altpcs_ctrldetect(pcs_rx_kchar_15),
.altpcs_errdetect(led_char_err_gx[15]),
.altpcs_rmfifodatadeleted(pcs_rx_rmfifodatadeleted[15]),
.altpcs_rmfifodatainserted(pcs_rx_rmfifodatainserted[15]),
.altpcs_carrierdetect(pcs_rx_carrierdetected[15])
) ;
defparam
the_altera_tse_gxb_aligned_rxsync_15.DEVICE_FAMILY = DEVICE_FAMILY;
// Altgxb in GIGE mode
// --------------------
altera_tse_gxb_gige_inst the_altera_tse_gxb_gige_inst_15
(
.cal_blk_clk (gxb_cal_blk_clk),
.gxb_powerdown (gxb_pwrdn_in_sig[15]),
.pll_inclk (ref_clk),
.rx_recovclkout(rx_recovclkout_15),
.reconfig_clk(reconfig_clk_15),
.reconfig_togxb(reconfig_togxb_15),
.reconfig_fromgxb(reconfig_fromgxb_15),
.rx_analogreset (rx_analogreset_sqcnr_15),
.rx_cruclk (ref_clk),
.rx_ctrldetect (rx_kchar_15),
.rx_clkout (rx_pcs_clk_c15),
.rx_datain (rxp_15),
.rx_dataout (rx_frame_15),
.rx_digitalreset (rx_digitalreset_sqcnr_15),
.rx_disperr (rx_disp_err[15]),
.rx_errdetect (rx_char_err_gx[15]),
.rx_patterndetect (rx_patterndetect[15]),
.rx_rlv (rx_runlengthviolation[15]),
.rx_seriallpbken (sd_loopback_15),
.rx_syncstatus (rx_syncstatus[15]),
.tx_clkout (tx_pcs_clk_c15),
.tx_ctrlenable (tx_kchar_15),
.tx_datain (tx_frame_15),
.rx_freqlocked (rx_freqlocked_15),
.tx_dataout (txp_15),
.tx_digitalreset (tx_digitalreset_sqcnr_15),
.rx_rmfifodatadeleted(rx_rmfifodatadeleted[15]),
.rx_rmfifodatainserted(rx_rmfifodatainserted[15]),
.rx_runningdisp(rx_runningdisp[15]),
.pll_powerdown(gxb_pwrdn_in_sig[15]),
.pll_locked(pll_locked_15)
);
defparam
the_altera_tse_gxb_gige_inst_15.ENABLE_ALT_RECONFIG = ENABLE_ALT_RECONFIG,
the_altera_tse_gxb_gige_inst_15.ENABLE_SGMII = ENABLE_SGMII,
the_altera_tse_gxb_gige_inst_15.STARTING_CHANNEL_NUMBER = STARTING_CHANNEL_NUMBER + 60,
the_altera_tse_gxb_gige_inst_15.DEVICE_FAMILY = DEVICE_FAMILY;
end
else
begin
assign reconfig_fromgxb_15 = {17{1'b0}};
assign led_char_err_gx[15] = 1'b0;
assign link_status[15] = 1'b0;
assign led_disp_err_15 = 1'b0;
assign txp_15 = 1'b0;
assign pcs_clk_c15 = 1'b0;
end
endgenerate
// #######################################################################
// ############### CHANNEL 16 LOGIC/COMPONENTS ###############
// #######################################################################
// Export powerdown signal or wire it internally
// ---------------------------------------------
reg data_in_16,gxb_pwrdn_in_sig_clk_16;
generate if (EXPORT_PWRDN == 1 && MAX_CHANNELS > 16)
begin
always @(posedge clk or posedge gxb_pwrdn_in_16)
begin
if (gxb_pwrdn_in_16 == 1) begin
data_in_16 <= 1;
gxb_pwrdn_in_sig_clk_16 <= 1;
end else begin
data_in_16 <= 1'b0;
gxb_pwrdn_in_sig_clk_16 <= data_in_16;
end
end
assign gxb_pwrdn_in_sig[16] = gxb_pwrdn_in_16;
assign pcs_pwrdn_out_16 = pcs_pwrdn_out_sig[16];
end
else
begin
assign gxb_pwrdn_in_sig[16] = pcs_pwrdn_out_sig[16];
assign pcs_pwrdn_out_16 = 1'b0;
always@(*) begin
gxb_pwrdn_in_sig_clk_16 = gxb_pwrdn_in_sig[16];
end
end
endgenerate
generate if (MAX_CHANNELS > 16)
begin
wire locked_signal_16;
// Reset logic used to reset the PMA blocks
// ----------------------------------------
// ALTGX Reset Sequencer
altera_tse_reset_sequencer altera_tse_reset_sequencer_inst_16(
// User inputs and outputs
.clock(clk),
.reset_all(reset|gxb_pwrdn_in_sig_clk_16),
//.reset_tx_digital(reset_ref_clk),
//.reset_rx_digital(reset_ref_clk),
.powerdown_all(reset_posedge),
.tx_ready(), // output
.rx_ready(), // output
// I/O transceiver and status
.pll_powerdown(pll_powerdown_sqcnr_16),// output
.tx_digitalreset(tx_digitalreset_sqcnr_16),// output
.rx_analogreset(rx_analogreset_sqcnr_16),// output
.rx_digitalreset(rx_digitalreset_sqcnr_16),// output
.gxb_powerdown(gxb_powerdown_sqcnr_16),// output
.pll_is_locked(locked_signal_16),
.rx_is_lockedtodata(rx_freqlocked_16),
.manual_mode(1'b0),
.rx_oc_busy(reconfig_busy_16)
);
assign locked_signal_16 = (reset? 1'b0: pll_locked_16);
// Instantiation of the Alt2gxb and Alt4gxb block as the PMA for Stratix_II_GX ,ArriaGX and Stratix IV devices
// -----------------------------------------------------------------------------------
// Aligned Rx_sync from gxb
// -------------------------------
altera_tse_reset_synchronizer ch_16_reset_sync_0 (
.clk(rx_pcs_clk_c16),
.reset_in(rx_digitalreset_sqcnr_16),
.reset_out(reset_rx_pcs_clk_c16_int)
);
altera_tse_gxb_aligned_rxsync the_altera_tse_gxb_aligned_rxsync_16
(
.clk(rx_pcs_clk_c16),
.reset(reset_rx_pcs_clk_c16_int),
//input (from alt2gxb)
.alt_dataout(rx_frame_16),
.alt_sync(rx_syncstatus[16]),
.alt_disperr(rx_disp_err[16]),
.alt_ctrldetect(rx_kchar_16),
.alt_errdetect(rx_char_err_gx[16]),
.alt_rmfifodatadeleted(rx_rmfifodatadeleted[16]),
.alt_rmfifodatainserted(rx_rmfifodatainserted[16]),
.alt_runlengthviolation(rx_runlengthviolation[16]),
.alt_patterndetect(rx_patterndetect[16]),
.alt_runningdisp(rx_runningdisp[16]),
//output (to PCS)
.altpcs_dataout(pcs_rx_frame_16),
.altpcs_sync(link_status[16]),
.altpcs_disperr(led_disp_err_16),
.altpcs_ctrldetect(pcs_rx_kchar_16),
.altpcs_errdetect(led_char_err_gx[16]),
.altpcs_rmfifodatadeleted(pcs_rx_rmfifodatadeleted[16]),
.altpcs_rmfifodatainserted(pcs_rx_rmfifodatainserted[16]),
.altpcs_carrierdetect(pcs_rx_carrierdetected[16])
) ;
defparam
the_altera_tse_gxb_aligned_rxsync_16.DEVICE_FAMILY = DEVICE_FAMILY;
// Altgxb in GIGE mode
// --------------------
altera_tse_gxb_gige_inst the_altera_tse_gxb_gige_inst_16
(
.cal_blk_clk (gxb_cal_blk_clk),
.gxb_powerdown (gxb_pwrdn_in_sig[16]),
.pll_inclk (ref_clk),
.rx_recovclkout(rx_recovclkout_16),
.reconfig_clk(reconfig_clk_16),
.reconfig_togxb(reconfig_togxb_16),
.reconfig_fromgxb(reconfig_fromgxb_16),
.rx_analogreset (rx_analogreset_sqcnr_16),
.rx_cruclk (ref_clk),
.rx_ctrldetect (rx_kchar_16),
.rx_clkout (rx_pcs_clk_c16),
.rx_datain (rxp_16),
.rx_dataout (rx_frame_16),
.rx_digitalreset (rx_digitalreset_sqcnr_16),
.rx_disperr (rx_disp_err[16]),
.rx_errdetect (rx_char_err_gx[16]),
.rx_patterndetect (rx_patterndetect[16]),
.rx_rlv (rx_runlengthviolation[16]),
.rx_seriallpbken (sd_loopback_16),
.rx_syncstatus (rx_syncstatus[16]),
.tx_clkout (tx_pcs_clk_c16),
.tx_ctrlenable (tx_kchar_16),
.tx_datain (tx_frame_16),
.rx_freqlocked (rx_freqlocked_16),
.tx_dataout (txp_16),
.tx_digitalreset (tx_digitalreset_sqcnr_16),
.rx_rmfifodatadeleted(rx_rmfifodatadeleted[16]),
.rx_rmfifodatainserted(rx_rmfifodatainserted[16]),
.rx_runningdisp(rx_runningdisp[16]),
.pll_powerdown(gxb_pwrdn_in_sig[16]),
.pll_locked(pll_locked_16)
);
defparam
the_altera_tse_gxb_gige_inst_16.ENABLE_ALT_RECONFIG = ENABLE_ALT_RECONFIG,
the_altera_tse_gxb_gige_inst_16.ENABLE_SGMII = ENABLE_SGMII,
the_altera_tse_gxb_gige_inst_16.STARTING_CHANNEL_NUMBER = STARTING_CHANNEL_NUMBER + 64,
the_altera_tse_gxb_gige_inst_16.DEVICE_FAMILY = DEVICE_FAMILY;
end
else
begin
assign reconfig_fromgxb_16 = {17{1'b0}};
assign led_char_err_gx[16] = 1'b0;
assign link_status[16] = 1'b0;
assign led_disp_err_16 = 1'b0;
assign txp_16 = 1'b0;
assign pcs_clk_c16 = 1'b0;
end
endgenerate
// #######################################################################
// ############### CHANNEL 17 LOGIC/COMPONENTS ###############
// #######################################################################
// Export powerdown signal or wire it internally
// ---------------------------------------------
reg data_in_17,gxb_pwrdn_in_sig_clk_17;
generate if (EXPORT_PWRDN == 1 && MAX_CHANNELS > 17)
begin
always @(posedge clk or posedge gxb_pwrdn_in_17)
begin
if (gxb_pwrdn_in_17 == 1) begin
data_in_17 <= 1;
gxb_pwrdn_in_sig_clk_17 <= 1;
end else begin
data_in_17 <= 1'b0;
gxb_pwrdn_in_sig_clk_17 <= data_in_17;
end
end
assign gxb_pwrdn_in_sig[17] = gxb_pwrdn_in_17;
assign pcs_pwrdn_out_17 = pcs_pwrdn_out_sig[17];
end
else
begin
assign gxb_pwrdn_in_sig[17] = pcs_pwrdn_out_sig[17];
assign pcs_pwrdn_out_17 = 1'b0;
always@(*) begin
gxb_pwrdn_in_sig_clk_17 = gxb_pwrdn_in_sig[17];
end
end
endgenerate
generate if (MAX_CHANNELS > 17)
begin
wire locked_signal_17;
// Reset logic used to reset the PMA blocks
// ----------------------------------------
// ALTGX Reset Sequencer
altera_tse_reset_sequencer altera_tse_reset_sequencer_inst_17(
// User inputs and outputs
.clock(clk),
.reset_all(reset|gxb_pwrdn_in_sig_clk_17),
//.reset_tx_digital(reset_ref_clk),
//.reset_rx_digital(reset_ref_clk),
.powerdown_all(reset_posedge),
.tx_ready(), // output
.rx_ready(), // output
// I/O transceiver and status
.pll_powerdown(pll_powerdown_sqcnr_17),// output
.tx_digitalreset(tx_digitalreset_sqcnr_17),// output
.rx_analogreset(rx_analogreset_sqcnr_17),// output
.rx_digitalreset(rx_digitalreset_sqcnr_17),// output
.gxb_powerdown(gxb_powerdown_sqcnr_17),// output
.pll_is_locked(locked_signal_17),
.rx_is_lockedtodata(rx_freqlocked_17),
.manual_mode(1'b0),
.rx_oc_busy(reconfig_busy_17)
);
assign locked_signal_17 = (reset? 1'b0: pll_locked_17);
// Instantiation of the Alt2gxb and Alt4gxb block as the PMA for Stratix_II_GX ,ArriaGX and Stratix IV devices
// -----------------------------------------------------------------------------------
// Aligned Rx_sync from gxb
// -------------------------------
altera_tse_reset_synchronizer ch_17_reset_sync_0 (
.clk(rx_pcs_clk_c17),
.reset_in(rx_digitalreset_sqcnr_17),
.reset_out(reset_rx_pcs_clk_c17_int)
);
altera_tse_gxb_aligned_rxsync the_altera_tse_gxb_aligned_rxsync_17
(
.clk(rx_pcs_clk_c17),
.reset(reset_rx_pcs_clk_c17_int),
//input (from alt2gxb)
.alt_dataout(rx_frame_17),
.alt_sync(rx_syncstatus[17]),
.alt_disperr(rx_disp_err[17]),
.alt_ctrldetect(rx_kchar_17),
.alt_errdetect(rx_char_err_gx[17]),
.alt_rmfifodatadeleted(rx_rmfifodatadeleted[17]),
.alt_rmfifodatainserted(rx_rmfifodatainserted[17]),
.alt_runlengthviolation(rx_runlengthviolation[17]),
.alt_patterndetect(rx_patterndetect[17]),
.alt_runningdisp(rx_runningdisp[17]),
//output (to PCS)
.altpcs_dataout(pcs_rx_frame_17),
.altpcs_sync(link_status[17]),
.altpcs_disperr(led_disp_err_17),
.altpcs_ctrldetect(pcs_rx_kchar_17),
.altpcs_errdetect(led_char_err_gx[17]),
.altpcs_rmfifodatadeleted(pcs_rx_rmfifodatadeleted[17]),
.altpcs_rmfifodatainserted(pcs_rx_rmfifodatainserted[17]),
.altpcs_carrierdetect(pcs_rx_carrierdetected[17])
) ;
defparam
the_altera_tse_gxb_aligned_rxsync_17.DEVICE_FAMILY = DEVICE_FAMILY;
// Altgxb in GIGE mode
// --------------------
altera_tse_gxb_gige_inst the_altera_tse_gxb_gige_inst_17
(
.cal_blk_clk (gxb_cal_blk_clk),
.gxb_powerdown (gxb_pwrdn_in_sig[17]),
.pll_inclk (ref_clk),
.rx_recovclkout(rx_recovclkout_17),
.reconfig_clk(reconfig_clk_17),
.reconfig_togxb(reconfig_togxb_17),
.reconfig_fromgxb(reconfig_fromgxb_17),
.rx_analogreset (rx_analogreset_sqcnr_17),
.rx_cruclk (ref_clk),
.rx_ctrldetect (rx_kchar_17),
.rx_clkout (rx_pcs_clk_c17),
.rx_datain (rxp_17),
.rx_dataout (rx_frame_17),
.rx_digitalreset (rx_digitalreset_sqcnr_17),
.rx_disperr (rx_disp_err[17]),
.rx_errdetect (rx_char_err_gx[17]),
.rx_patterndetect (rx_patterndetect[17]),
.rx_rlv (rx_runlengthviolation[17]),
.rx_seriallpbken (sd_loopback_17),
.rx_syncstatus (rx_syncstatus[17]),
.tx_clkout (tx_pcs_clk_c17),
.tx_ctrlenable (tx_kchar_17),
.tx_datain (tx_frame_17),
.rx_freqlocked (rx_freqlocked_17),
.tx_dataout (txp_17),
.tx_digitalreset (tx_digitalreset_sqcnr_17),
.rx_rmfifodatadeleted(rx_rmfifodatadeleted[17]),
.rx_rmfifodatainserted(rx_rmfifodatainserted[17]),
.rx_runningdisp(rx_runningdisp[17]),
.pll_powerdown(gxb_pwrdn_in_sig[17]),
.pll_locked(pll_locked_17)
);
defparam
the_altera_tse_gxb_gige_inst_17.ENABLE_ALT_RECONFIG = ENABLE_ALT_RECONFIG,
the_altera_tse_gxb_gige_inst_17.ENABLE_SGMII = ENABLE_SGMII,
the_altera_tse_gxb_gige_inst_17.STARTING_CHANNEL_NUMBER = STARTING_CHANNEL_NUMBER + 68,
the_altera_tse_gxb_gige_inst_17.DEVICE_FAMILY = DEVICE_FAMILY;
end
else
begin
assign reconfig_fromgxb_17 = {17{1'b0}};
assign led_char_err_gx[17] = 1'b0;
assign link_status[17] = 1'b0;
assign led_disp_err_17 = 1'b0;
assign txp_17 = 1'b0;
assign pcs_clk_c17 = 1'b0;
end
endgenerate
// #######################################################################
// ############### CHANNEL 18 LOGIC/COMPONENTS ###############
// #######################################################################
// Export powerdown signal or wire it internally
// ---------------------------------------------
reg data_in_18,gxb_pwrdn_in_sig_clk_18;
generate if (EXPORT_PWRDN == 1 && MAX_CHANNELS > 18)
begin
always @(posedge clk or posedge gxb_pwrdn_in_18)
begin
if (gxb_pwrdn_in_18 == 1) begin
data_in_18 <= 1;
gxb_pwrdn_in_sig_clk_18 <= 1;
end else begin
data_in_18 <= 1'b0;
gxb_pwrdn_in_sig_clk_18 <= data_in_18;
end
end
assign gxb_pwrdn_in_sig[18] = gxb_pwrdn_in_18;
assign pcs_pwrdn_out_18 = pcs_pwrdn_out_sig[18];
end
else
begin
assign gxb_pwrdn_in_sig[18] = pcs_pwrdn_out_sig[18];
assign pcs_pwrdn_out_18 = 1'b0;
always@(*) begin
gxb_pwrdn_in_sig_clk_18 = gxb_pwrdn_in_sig[18];
end
end
endgenerate
generate if (MAX_CHANNELS > 18)
begin
wire locked_signal_18;
// Reset logic used to reset the PMA blocks
// ----------------------------------------
// ALTGX Reset Sequencer
altera_tse_reset_sequencer altera_tse_reset_sequencer_inst_18(
// User inputs and outputs
.clock(clk),
.reset_all(reset|gxb_pwrdn_in_sig_clk_18),
//.reset_tx_digital(reset_ref_clk),
//.reset_rx_digital(reset_ref_clk),
.powerdown_all(reset_posedge),
.tx_ready(), // output
.rx_ready(), // output
// I/O transceiver and status
.pll_powerdown(pll_powerdown_sqcnr_18),// output
.tx_digitalreset(tx_digitalreset_sqcnr_18),// output
.rx_analogreset(rx_analogreset_sqcnr_18),// output
.rx_digitalreset(rx_digitalreset_sqcnr_18),// output
.gxb_powerdown(gxb_powerdown_sqcnr_18),// output
.pll_is_locked(locked_signal_18),
.rx_is_lockedtodata(rx_freqlocked_18),
.manual_mode(1'b0),
.rx_oc_busy(reconfig_busy_18)
);
assign locked_signal_18 = (reset? 1'b0: pll_locked_18);
// Instantiation of the Alt2gxb and Alt4gxb block as the PMA for Stratix_II_GX ,ArriaGX and Stratix IV devices
// -----------------------------------------------------------------------------------
// Aligned Rx_sync from gxb
// -------------------------------
altera_tse_reset_synchronizer ch_18_reset_sync_0 (
.clk(rx_pcs_clk_c18),
.reset_in(rx_digitalreset_sqcnr_18),
.reset_out(reset_rx_pcs_clk_c18_int)
);
altera_tse_gxb_aligned_rxsync the_altera_tse_gxb_aligned_rxsync_18
(
.clk(rx_pcs_clk_c18),
.reset(reset_rx_pcs_clk_c18_int),
//input (from alt2gxb)
.alt_dataout(rx_frame_18),
.alt_sync(rx_syncstatus[18]),
.alt_disperr(rx_disp_err[18]),
.alt_ctrldetect(rx_kchar_18),
.alt_errdetect(rx_char_err_gx[18]),
.alt_rmfifodatadeleted(rx_rmfifodatadeleted[18]),
.alt_rmfifodatainserted(rx_rmfifodatainserted[18]),
.alt_runlengthviolation(rx_runlengthviolation[18]),
.alt_patterndetect(rx_patterndetect[18]),
.alt_runningdisp(rx_runningdisp[18]),
//output (to PCS)
.altpcs_dataout(pcs_rx_frame_18),
.altpcs_sync(link_status[18]),
.altpcs_disperr(led_disp_err_18),
.altpcs_ctrldetect(pcs_rx_kchar_18),
.altpcs_errdetect(led_char_err_gx[18]),
.altpcs_rmfifodatadeleted(pcs_rx_rmfifodatadeleted[18]),
.altpcs_rmfifodatainserted(pcs_rx_rmfifodatainserted[18]),
.altpcs_carrierdetect(pcs_rx_carrierdetected[18])
) ;
defparam
the_altera_tse_gxb_aligned_rxsync_18.DEVICE_FAMILY = DEVICE_FAMILY;
// Altgxb in GIGE mode
// --------------------
altera_tse_gxb_gige_inst the_altera_tse_gxb_gige_inst_18
(
.cal_blk_clk (gxb_cal_blk_clk),
.gxb_powerdown (gxb_pwrdn_in_sig[18]),
.pll_inclk (ref_clk),
.rx_recovclkout(rx_recovclkout_18),
.reconfig_clk(reconfig_clk_18),
.reconfig_togxb(reconfig_togxb_18),
.reconfig_fromgxb(reconfig_fromgxb_18),
.rx_analogreset (rx_analogreset_sqcnr_18),
.rx_cruclk (ref_clk),
.rx_ctrldetect (rx_kchar_18),
.rx_clkout (rx_pcs_clk_c18),
.rx_datain (rxp_18),
.rx_dataout (rx_frame_18),
.rx_digitalreset (rx_digitalreset_sqcnr_18),
.rx_disperr (rx_disp_err[18]),
.rx_errdetect (rx_char_err_gx[18]),
.rx_patterndetect (rx_patterndetect[18]),
.rx_rlv (rx_runlengthviolation[18]),
.rx_seriallpbken (sd_loopback_18),
.rx_syncstatus (rx_syncstatus[18]),
.tx_clkout (tx_pcs_clk_c18),
.tx_ctrlenable (tx_kchar_18),
.tx_datain (tx_frame_18),
.rx_freqlocked (rx_freqlocked_18),
.tx_dataout (txp_18),
.tx_digitalreset (tx_digitalreset_sqcnr_18),
.rx_rmfifodatadeleted(rx_rmfifodatadeleted[18]),
.rx_rmfifodatainserted(rx_rmfifodatainserted[18]),
.rx_runningdisp(rx_runningdisp[18]),
.pll_powerdown(gxb_pwrdn_in_sig[18]),
.pll_locked(pll_locked_18)
);
defparam
the_altera_tse_gxb_gige_inst_18.ENABLE_ALT_RECONFIG = ENABLE_ALT_RECONFIG,
the_altera_tse_gxb_gige_inst_18.ENABLE_SGMII = ENABLE_SGMII,
the_altera_tse_gxb_gige_inst_18.STARTING_CHANNEL_NUMBER = STARTING_CHANNEL_NUMBER + 72,
the_altera_tse_gxb_gige_inst_18.DEVICE_FAMILY = DEVICE_FAMILY;
end
else
begin
assign reconfig_fromgxb_18 = {17{1'b0}};
assign led_char_err_gx[18] = 1'b0;
assign link_status[18] = 1'b0;
assign led_disp_err_18 = 1'b0;
assign txp_18 = 1'b0;
assign pcs_clk_c18 = 1'b0;
end
endgenerate
// #######################################################################
// ############### CHANNEL 19 LOGIC/COMPONENTS ###############
// #######################################################################
// Export powerdown signal or wire it internally
// ---------------------------------------------
reg data_in_19,gxb_pwrdn_in_sig_clk_19;
generate if (EXPORT_PWRDN == 1 && MAX_CHANNELS > 19)
begin
always @(posedge clk or posedge gxb_pwrdn_in_19)
begin
if (gxb_pwrdn_in_19 == 1) begin
data_in_19 <= 1;
gxb_pwrdn_in_sig_clk_19 <= 1;
end else begin
data_in_19 <= 1'b0;
gxb_pwrdn_in_sig_clk_19 <= data_in_19;
end
end
assign gxb_pwrdn_in_sig[19] = gxb_pwrdn_in_19;
assign pcs_pwrdn_out_19 = pcs_pwrdn_out_sig[19];
end
else
begin
assign gxb_pwrdn_in_sig[19] = pcs_pwrdn_out_sig[19];
assign pcs_pwrdn_out_19 = 1'b0;
always@(*) begin
gxb_pwrdn_in_sig_clk_19 = gxb_pwrdn_in_sig[19];
end
end
endgenerate
generate if (MAX_CHANNELS > 19)
begin
wire locked_signal_19;
// Reset logic used to reset the PMA blocks
// ----------------------------------------
// ALTGX Reset Sequencer
altera_tse_reset_sequencer altera_tse_reset_sequencer_inst_19(
// User inputs and outputs
.clock(clk),
.reset_all(reset|gxb_pwrdn_in_sig_clk_19),
//.reset_tx_digital(reset_ref_clk),
//.reset_rx_digital(reset_ref_clk),
.powerdown_all(reset_posedge),
.tx_ready(), // output
.rx_ready(), // output
// I/O transceiver and status
.pll_powerdown(pll_powerdown_sqcnr_19),// output
.tx_digitalreset(tx_digitalreset_sqcnr_19),// output
.rx_analogreset(rx_analogreset_sqcnr_19),// output
.rx_digitalreset(rx_digitalreset_sqcnr_19),// output
.gxb_powerdown(gxb_powerdown_sqcnr_19),// output
.pll_is_locked(locked_signal_19),
.rx_is_lockedtodata(rx_freqlocked_19),
.manual_mode(1'b0),
.rx_oc_busy(reconfig_busy_19)
);
assign locked_signal_19 = (reset? 1'b0: pll_locked_19);
// Instantiation of the Alt2gxb and Alt4gxb block as the PMA for Stratix_II_GX ,ArriaGX and Stratix IV devices
// -----------------------------------------------------------------------------------
// Aligned Rx_sync from gxb
// -------------------------------
altera_tse_reset_synchronizer ch_19_reset_sync_0 (
.clk(rx_pcs_clk_c19),
.reset_in(rx_digitalreset_sqcnr_19),
.reset_out(reset_rx_pcs_clk_c19_int)
);
altera_tse_gxb_aligned_rxsync the_altera_tse_gxb_aligned_rxsync_19
(
.clk(rx_pcs_clk_c19),
.reset(reset_rx_pcs_clk_c19_int),
//input (from alt2gxb)
.alt_dataout(rx_frame_19),
.alt_sync(rx_syncstatus[19]),
.alt_disperr(rx_disp_err[19]),
.alt_ctrldetect(rx_kchar_19),
.alt_errdetect(rx_char_err_gx[19]),
.alt_rmfifodatadeleted(rx_rmfifodatadeleted[19]),
.alt_rmfifodatainserted(rx_rmfifodatainserted[19]),
.alt_runlengthviolation(rx_runlengthviolation[19]),
.alt_patterndetect(rx_patterndetect[19]),
.alt_runningdisp(rx_runningdisp[19]),
//output (to PCS)
.altpcs_dataout(pcs_rx_frame_19),
.altpcs_sync(link_status[19]),
.altpcs_disperr(led_disp_err_19),
.altpcs_ctrldetect(pcs_rx_kchar_19),
.altpcs_errdetect(led_char_err_gx[19]),
.altpcs_rmfifodatadeleted(pcs_rx_rmfifodatadeleted[19]),
.altpcs_rmfifodatainserted(pcs_rx_rmfifodatainserted[19]),
.altpcs_carrierdetect(pcs_rx_carrierdetected[19])
) ;
defparam
the_altera_tse_gxb_aligned_rxsync_19.DEVICE_FAMILY = DEVICE_FAMILY;
// Altgxb in GIGE mode
// --------------------
altera_tse_gxb_gige_inst the_altera_tse_gxb_gige_inst_19
(
.cal_blk_clk (gxb_cal_blk_clk),
.gxb_powerdown (gxb_pwrdn_in_sig[19]),
.pll_inclk (ref_clk),
.rx_recovclkout(rx_recovclkout_19),
.reconfig_clk(reconfig_clk_19),
.reconfig_togxb(reconfig_togxb_19),
.reconfig_fromgxb(reconfig_fromgxb_19),
.rx_analogreset (rx_analogreset_sqcnr_19),
.rx_cruclk (ref_clk),
.rx_ctrldetect (rx_kchar_19),
.rx_clkout (rx_pcs_clk_c19),
.rx_datain (rxp_19),
.rx_dataout (rx_frame_19),
.rx_digitalreset (rx_digitalreset_sqcnr_19),
.rx_disperr (rx_disp_err[19]),
.rx_errdetect (rx_char_err_gx[19]),
.rx_patterndetect (rx_patterndetect[19]),
.rx_rlv (rx_runlengthviolation[19]),
.rx_seriallpbken (sd_loopback_19),
.rx_syncstatus (rx_syncstatus[19]),
.tx_clkout (tx_pcs_clk_c19),
.tx_ctrlenable (tx_kchar_19),
.tx_datain (tx_frame_19),
.tx_dataout (txp_19),
.rx_freqlocked (rx_freqlocked_19),
.tx_digitalreset (tx_digitalreset_sqcnr_19),
.rx_rmfifodatadeleted(rx_rmfifodatadeleted[19]),
.rx_rmfifodatainserted(rx_rmfifodatainserted[19]),
.rx_runningdisp(rx_runningdisp[19]),
.pll_powerdown(gxb_pwrdn_in_sig[19]),
.pll_locked(pll_locked_19)
);
defparam
the_altera_tse_gxb_gige_inst_19.ENABLE_ALT_RECONFIG = ENABLE_ALT_RECONFIG,
the_altera_tse_gxb_gige_inst_19.ENABLE_SGMII = ENABLE_SGMII,
the_altera_tse_gxb_gige_inst_19.STARTING_CHANNEL_NUMBER = STARTING_CHANNEL_NUMBER + 76,
the_altera_tse_gxb_gige_inst_19.DEVICE_FAMILY = DEVICE_FAMILY;
end
else
begin
assign reconfig_fromgxb_19 = {17{1'b0}};
assign led_char_err_gx[19] = 1'b0;
assign link_status[19] = 1'b0;
assign led_disp_err_19 = 1'b0;
assign txp_19 = 1'b0;
assign pcs_clk_c19 = 1'b0;
end
endgenerate
// #######################################################################
// ############### CHANNEL 20 LOGIC/COMPONENTS ###############
// #######################################################################
// Export powerdown signal or wire it internally
// ---------------------------------------------
reg data_in_20,gxb_pwrdn_in_sig_clk_20;
generate if (EXPORT_PWRDN == 1 && MAX_CHANNELS > 20)
begin
always @(posedge clk or posedge gxb_pwrdn_in_20)
begin
if (gxb_pwrdn_in_20 == 1) begin
data_in_20 <= 1;
gxb_pwrdn_in_sig_clk_20 <= 1;
end else begin
data_in_20 <= 1'b0;
gxb_pwrdn_in_sig_clk_20 <= data_in_20;
end
end
assign gxb_pwrdn_in_sig[20] = gxb_pwrdn_in_20;
assign pcs_pwrdn_out_20 = pcs_pwrdn_out_sig[20];
end
else
begin
assign gxb_pwrdn_in_sig[20] = pcs_pwrdn_out_sig[20];
assign pcs_pwrdn_out_20 = 1'b0;
always@(*) begin
gxb_pwrdn_in_sig_clk_20 = gxb_pwrdn_in_sig[20];
end
end
endgenerate
generate if (MAX_CHANNELS > 20)
begin
wire locked_signal_20;
// Reset logic used to reset the PMA blocks
// ----------------------------------------
// ALTGX Reset Sequencer
altera_tse_reset_sequencer altera_tse_reset_sequencer_inst_20(
// User inputs and outputs
.clock(clk),
.reset_all(reset|gxb_pwrdn_in_sig_clk_20),
//.reset_tx_digital(reset_ref_clk),
//.reset_rx_digital(reset_ref_clk),
.powerdown_all(reset_posedge),
.tx_ready(), // output
.rx_ready(), // output
// I/O transceiver and status
.pll_powerdown(pll_powerdown_sqcnr_20),// output
.tx_digitalreset(tx_digitalreset_sqcnr_20),// output
.rx_analogreset(rx_analogreset_sqcnr_20),// output
.rx_digitalreset(rx_digitalreset_sqcnr_20),// output
.gxb_powerdown(gxb_powerdown_sqcnr_20),// output
.pll_is_locked(locked_signal_20),
.rx_is_lockedtodata(rx_freqlocked_20),
.manual_mode(1'b0),
.rx_oc_busy(reconfig_busy_20)
);
assign locked_signal_20 = (reset? 1'b0: pll_locked_20);
// Instantiation of the Alt2gxb and Alt4gxb block as the PMA for Stratix_II_GX ,ArriaGX and Stratix IV devices
// -----------------------------------------------------------------------------------
// Aligned Rx_sync from gxb
// -------------------------------
altera_tse_reset_synchronizer ch_20_reset_sync_0 (
.clk(rx_pcs_clk_c20),
.reset_in(rx_digitalreset_sqcnr_20),
.reset_out(reset_rx_pcs_clk_c20_int)
);
altera_tse_gxb_aligned_rxsync the_altera_tse_gxb_aligned_rxsync_20
(
.clk(rx_pcs_clk_c20),
.reset(reset_rx_pcs_clk_c20_int),
//input (from alt2gxb)
.alt_dataout(rx_frame_20),
.alt_sync(rx_syncstatus[20]),
.alt_disperr(rx_disp_err[20]),
.alt_ctrldetect(rx_kchar_20),
.alt_errdetect(rx_char_err_gx[20]),
.alt_rmfifodatadeleted(rx_rmfifodatadeleted[20]),
.alt_rmfifodatainserted(rx_rmfifodatainserted[20]),
.alt_runlengthviolation(rx_runlengthviolation[20]),
.alt_patterndetect(rx_patterndetect[20]),
.alt_runningdisp(rx_runningdisp[20]),
//output (to PCS)
.altpcs_dataout(pcs_rx_frame_20),
.altpcs_sync(link_status[20]),
.altpcs_disperr(led_disp_err_20),
.altpcs_ctrldetect(pcs_rx_kchar_20),
.altpcs_errdetect(led_char_err_gx[20]),
.altpcs_rmfifodatadeleted(pcs_rx_rmfifodatadeleted[20]),
.altpcs_rmfifodatainserted(pcs_rx_rmfifodatainserted[20]),
.altpcs_carrierdetect(pcs_rx_carrierdetected[20])
) ;
defparam
the_altera_tse_gxb_aligned_rxsync_20.DEVICE_FAMILY = DEVICE_FAMILY;
// Altgxb in GIGE mode
// --------------------
altera_tse_gxb_gige_inst the_altera_tse_gxb_gige_inst_20
(
.cal_blk_clk (gxb_cal_blk_clk),
.gxb_powerdown (gxb_pwrdn_in_sig[20]),
.pll_inclk (ref_clk),
.rx_recovclkout(rx_recovclkout_20),
.reconfig_clk(reconfig_clk_20),
.reconfig_togxb(reconfig_togxb_20),
.reconfig_fromgxb(reconfig_fromgxb_20),
.rx_analogreset (rx_analogreset_sqcnr_20),
.rx_cruclk (ref_clk),
.rx_ctrldetect (rx_kchar_20),
.rx_clkout (rx_pcs_clk_c20),
.rx_datain (rxp_20),
.rx_dataout (rx_frame_20),
.rx_digitalreset (rx_digitalreset_sqcnr_20),
.rx_disperr (rx_disp_err[20]),
.rx_errdetect (rx_char_err_gx[20]),
.rx_patterndetect (rx_patterndetect[20]),
.rx_rlv (rx_runlengthviolation[20]),
.rx_seriallpbken (sd_loopback_20),
.rx_syncstatus (rx_syncstatus[20]),
.tx_clkout (tx_pcs_clk_c20),
.tx_ctrlenable (tx_kchar_20),
.tx_datain (tx_frame_20),
.rx_freqlocked (rx_freqlocked_20),
.tx_dataout (txp_20),
.tx_digitalreset (tx_digitalreset_sqcnr_20),
.rx_rmfifodatadeleted(rx_rmfifodatadeleted[20]),
.rx_rmfifodatainserted(rx_rmfifodatainserted[20]),
.rx_runningdisp(rx_runningdisp[20]),
.pll_powerdown(gxb_pwrdn_in_sig[20]),
.pll_locked(pll_locked_20)
);
defparam
the_altera_tse_gxb_gige_inst_20.ENABLE_ALT_RECONFIG = ENABLE_ALT_RECONFIG,
the_altera_tse_gxb_gige_inst_20.ENABLE_SGMII = ENABLE_SGMII,
the_altera_tse_gxb_gige_inst_20.STARTING_CHANNEL_NUMBER = STARTING_CHANNEL_NUMBER + 80,
the_altera_tse_gxb_gige_inst_20.DEVICE_FAMILY = DEVICE_FAMILY;
end
else
begin
assign reconfig_fromgxb_20 = {17{1'b0}};
assign led_char_err_gx[20] = 1'b0;
assign link_status[20] = 1'b0;
assign led_disp_err_20 = 1'b0;
assign txp_20 = 1'b0;
assign pcs_clk_c20 = 1'b0;
end
endgenerate
// #######################################################################
// ############### CHANNEL 21 LOGIC/COMPONENTS ###############
// #######################################################################
// Export powerdown signal or wire it internally
// ---------------------------------------------
reg data_in_21,gxb_pwrdn_in_sig_clk_21;
generate if (EXPORT_PWRDN == 1 && MAX_CHANNELS > 21)
begin
always @(posedge clk or posedge gxb_pwrdn_in_21)
begin
if (gxb_pwrdn_in_21 == 1) begin
data_in_21 <= 1;
gxb_pwrdn_in_sig_clk_21 <= 1;
end else begin
data_in_21 <= 1'b0;
gxb_pwrdn_in_sig_clk_21 <= data_in_21;
end
end
assign gxb_pwrdn_in_sig[21] = gxb_pwrdn_in_21;
assign pcs_pwrdn_out_21 = pcs_pwrdn_out_sig[21];
end
else
begin
assign gxb_pwrdn_in_sig[21] = pcs_pwrdn_out_sig[21];
assign pcs_pwrdn_out_21 = 1'b0;
always@(*) begin
gxb_pwrdn_in_sig_clk_21 = gxb_pwrdn_in_sig[21];
end
end
endgenerate
generate if (MAX_CHANNELS > 21)
begin
wire locked_signal_21;
// Reset logic used to reset the PMA blocks
// ----------------------------------------
// ALTGX Reset Sequencer
altera_tse_reset_sequencer altera_tse_reset_sequencer_inst_21(
// User inputs and outputs
.clock(clk),
.reset_all(reset|gxb_pwrdn_in_sig_clk_21),
//.reset_tx_digital(reset_ref_clk),
//.reset_rx_digital(reset_ref_clk),
.powerdown_all(reset_posedge),
.tx_ready(), // output
.rx_ready(), // output
// I/O transceiver and status
.pll_powerdown(pll_powerdown_sqcnr_21),// output
.tx_digitalreset(tx_digitalreset_sqcnr_21),// output
.rx_analogreset(rx_analogreset_sqcnr_21),// output
.rx_digitalreset(rx_digitalreset_sqcnr_21),// output
.gxb_powerdown(gxb_powerdown_sqcnr_21),// output
.pll_is_locked(pll_locked_21),
.rx_is_lockedtodata(rx_freqlocked_21),
.manual_mode(1'b0),
.rx_oc_busy(reconfig_busy_21)
);
assign locked_signal_21 = (reset? 1'b0: pll_locked_21);
// Instantiation of the Alt2gxb and Alt4gxb block as the PMA for Stratix_II_GX ,ArriaGX and Stratix IV devices
// -----------------------------------------------------------------------------------
// Aligned Rx_sync from gxb
// -------------------------------
altera_tse_reset_synchronizer ch_21_reset_sync_0 (
.clk(rx_pcs_clk_c21),
.reset_in(rx_digitalreset_sqcnr_21),
.reset_out(reset_rx_pcs_clk_c21_int)
);
altera_tse_gxb_aligned_rxsync the_altera_tse_gxb_aligned_rxsync_21
(
.clk(rx_pcs_clk_c21),
.reset(reset_rx_pcs_clk_c21_int),
//input (from alt2gxb)
.alt_dataout(rx_frame_21),
.alt_sync(rx_syncstatus[21]),
.alt_disperr(rx_disp_err[21]),
.alt_ctrldetect(rx_kchar_21),
.alt_errdetect(rx_char_err_gx[21]),
.alt_rmfifodatadeleted(rx_rmfifodatadeleted[21]),
.alt_rmfifodatainserted(rx_rmfifodatainserted[21]),
.alt_runlengthviolation(rx_runlengthviolation[21]),
.alt_patterndetect(rx_patterndetect[21]),
.alt_runningdisp(rx_runningdisp[21]),
//output (to PCS)
.altpcs_dataout(pcs_rx_frame_21),
.altpcs_sync(link_status[21]),
.altpcs_disperr(led_disp_err_21),
.altpcs_ctrldetect(pcs_rx_kchar_21),
.altpcs_errdetect(led_char_err_gx[21]),
.altpcs_rmfifodatadeleted(pcs_rx_rmfifodatadeleted[21]),
.altpcs_rmfifodatainserted(pcs_rx_rmfifodatainserted[21]),
.altpcs_carrierdetect(pcs_rx_carrierdetected[21])
) ;
defparam
the_altera_tse_gxb_aligned_rxsync_21.DEVICE_FAMILY = DEVICE_FAMILY;
// Altgxb in GIGE mode
// --------------------
altera_tse_gxb_gige_inst the_altera_tse_gxb_gige_inst_21
(
.cal_blk_clk (gxb_cal_blk_clk),
.gxb_powerdown (gxb_pwrdn_in_sig[21]),
.pll_inclk (ref_clk),
.rx_recovclkout(rx_recovclkout_21),
.reconfig_clk(reconfig_clk_21),
.reconfig_togxb(reconfig_togxb_21),
.reconfig_fromgxb(reconfig_fromgxb_21),
.rx_analogreset (rx_analogreset_sqcnr_21),
.rx_cruclk (ref_clk),
.rx_ctrldetect (rx_kchar_21),
.rx_clkout (rx_pcs_clk_c21),
.rx_datain (rxp_21),
.rx_dataout (rx_frame_21),
.rx_digitalreset (rx_digitalreset_sqcnr_21),
.rx_disperr (rx_disp_err[21]),
.rx_errdetect (rx_char_err_gx[21]),
.rx_patterndetect (rx_patterndetect[21]),
.rx_rlv (rx_runlengthviolation[21]),
.rx_seriallpbken (sd_loopback_21),
.rx_syncstatus (rx_syncstatus[21]),
.tx_clkout (tx_pcs_clk_c21),
.tx_ctrlenable (tx_kchar_21),
.tx_datain (tx_frame_21),
.rx_freqlocked (rx_freqlocked_21),
.tx_dataout (txp_21),
.tx_digitalreset (tx_digitalreset_sqcnr_21),
.rx_rmfifodatadeleted(rx_rmfifodatadeleted[21]),
.rx_rmfifodatainserted(rx_rmfifodatainserted[21]),
.rx_runningdisp(rx_runningdisp[21]),
.pll_powerdown(gxb_pwrdn_in_sig[21]),
.pll_locked(pll_locked_21)
);
defparam
the_altera_tse_gxb_gige_inst_21.ENABLE_ALT_RECONFIG = ENABLE_ALT_RECONFIG,
the_altera_tse_gxb_gige_inst_21.ENABLE_SGMII = ENABLE_SGMII,
the_altera_tse_gxb_gige_inst_21.STARTING_CHANNEL_NUMBER = STARTING_CHANNEL_NUMBER + 84,
the_altera_tse_gxb_gige_inst_21.DEVICE_FAMILY = DEVICE_FAMILY;
end
else
begin
assign reconfig_fromgxb_21 = {17{1'b0}};
assign led_char_err_gx[21] = 1'b0;
assign link_status[21] = 1'b0;
assign led_disp_err_21 = 1'b0;
assign txp_21 = 1'b0;
assign pcs_clk_c21 = 1'b0;
end
endgenerate
// #######################################################################
// ############### CHANNEL 22 LOGIC/COMPONENTS ###############
// #######################################################################
// Export powerdown signal or wire it internally
// ---------------------------------------------
reg data_in_22,gxb_pwrdn_in_sig_clk_22;
generate if (EXPORT_PWRDN == 1 && MAX_CHANNELS > 22)
begin
always @(posedge clk or posedge gxb_pwrdn_in_22)
begin
if (gxb_pwrdn_in_22 == 1) begin
data_in_22 <= 1;
gxb_pwrdn_in_sig_clk_22 <= 1;
end else begin
data_in_22 <= 1'b0;
gxb_pwrdn_in_sig_clk_22 <= data_in_22;
end
end
assign gxb_pwrdn_in_sig[22] = gxb_pwrdn_in_22;
assign pcs_pwrdn_out_22 = pcs_pwrdn_out_sig[22];
end
else
begin
assign gxb_pwrdn_in_sig[22] = pcs_pwrdn_out_sig[22];
assign pcs_pwrdn_out_22 = 1'b0;
always@(*) begin
gxb_pwrdn_in_sig_clk_22 = gxb_pwrdn_in_sig[22];
end
end
endgenerate
generate if (MAX_CHANNELS > 22)
begin
wire locked_signal_22;
// Reset logic used to reset the PMA blocks
// ----------------------------------------
// ALTGX Reset Sequencer
altera_tse_reset_sequencer altera_tse_reset_sequencer_inst_22(
// User inputs and outputs
.clock(clk),
.reset_all(reset|gxb_pwrdn_in_sig_clk_22),
//.reset_tx_digital(reset_ref_clk),
//.reset_rx_digital(reset_ref_clk),
.powerdown_all(reset_posedge),
.tx_ready(), // output
.rx_ready(), // output
// I/O transceiver and status
.pll_powerdown(pll_powerdown_sqcnr_22),// output
.tx_digitalreset(tx_digitalreset_sqcnr_22),// output
.rx_analogreset(rx_analogreset_sqcnr_22),// output
.rx_digitalreset(rx_digitalreset_sqcnr_22),// output
.gxb_powerdown(gxb_powerdown_sqcnr_22),// output
.pll_is_locked(pll_locked_22),
.rx_is_lockedtodata(rx_freqlocked_22),
.manual_mode(1'b0),
.rx_oc_busy(reconfig_busy_22)
);
assign locked_signal_22 = (reset? 1'b0: pll_locked_22);
// Instantiation of the Alt2gxb and Alt4gxb block as the PMA for Stratix_II_GX ,ArriaGX and Stratix IV devices
// -----------------------------------------------------------------------------------
// Aligned Rx_sync from gxb
// -------------------------------
altera_tse_reset_synchronizer ch_22_reset_sync_0 (
.clk(rx_pcs_clk_c22),
.reset_in(rx_digitalreset_sqcnr_22),
.reset_out(reset_rx_pcs_clk_c22_int)
);
altera_tse_gxb_aligned_rxsync the_altera_tse_gxb_aligned_rxsync_22
(
.clk(rx_pcs_clk_c22),
.reset(reset_rx_pcs_clk_c22_int),
//input (from alt2gxb)
.alt_dataout(rx_frame_22),
.alt_sync(rx_syncstatus[22]),
.alt_disperr(rx_disp_err[22]),
.alt_ctrldetect(rx_kchar_22),
.alt_errdetect(rx_char_err_gx[22]),
.alt_rmfifodatadeleted(rx_rmfifodatadeleted[22]),
.alt_rmfifodatainserted(rx_rmfifodatainserted[22]),
.alt_runlengthviolation(rx_runlengthviolation[22]),
.alt_patterndetect(rx_patterndetect[22]),
.alt_runningdisp(rx_runningdisp[22]),
//output (to PCS)
.altpcs_dataout(pcs_rx_frame_22),
.altpcs_sync(link_status[22]),
.altpcs_disperr(led_disp_err_22),
.altpcs_ctrldetect(pcs_rx_kchar_22),
.altpcs_errdetect(led_char_err_gx[22]),
.altpcs_rmfifodatadeleted(pcs_rx_rmfifodatadeleted[22]),
.altpcs_rmfifodatainserted(pcs_rx_rmfifodatainserted[22]),
.altpcs_carrierdetect(pcs_rx_carrierdetected[22])
) ;
defparam
the_altera_tse_gxb_aligned_rxsync_22.DEVICE_FAMILY = DEVICE_FAMILY;
// Altgxb in GIGE mode
// --------------------
altera_tse_gxb_gige_inst the_altera_tse_gxb_gige_inst_22
(
.cal_blk_clk (gxb_cal_blk_clk),
.gxb_powerdown (gxb_pwrdn_in_sig[22]),
.pll_inclk (ref_clk),
.rx_recovclkout(rx_recovclkout_22),
.reconfig_clk(reconfig_clk_22),
.reconfig_togxb(reconfig_togxb_22),
.reconfig_fromgxb(reconfig_fromgxb_22),
.rx_analogreset (rx_analogreset_sqcnr_22),
.rx_cruclk (ref_clk),
.rx_ctrldetect (rx_kchar_22),
.rx_clkout (rx_pcs_clk_c22),
.rx_datain (rxp_22),
.rx_dataout (rx_frame_22),
.rx_digitalreset (rx_digitalreset_sqcnr_22),
.rx_disperr (rx_disp_err[22]),
.rx_errdetect (rx_char_err_gx[22]),
.rx_patterndetect (rx_patterndetect[22]),
.rx_rlv (rx_runlengthviolation[22]),
.rx_seriallpbken (sd_loopback_22),
.rx_syncstatus (rx_syncstatus[22]),
.tx_clkout (tx_pcs_clk_c22),
.tx_ctrlenable (tx_kchar_22),
.tx_datain (tx_frame_22),
.rx_freqlocked (rx_freqlocked_22),
.tx_dataout (txp_22),
.tx_digitalreset (tx_digitalreset_sqcnr_22),
.rx_rmfifodatadeleted(rx_rmfifodatadeleted[22]),
.rx_rmfifodatainserted(rx_rmfifodatainserted[22]),
.rx_runningdisp(rx_runningdisp[22]),
.pll_powerdown(gxb_pwrdn_in_sig[22]),
.pll_locked(pll_locked_22)
);
defparam
the_altera_tse_gxb_gige_inst_22.ENABLE_ALT_RECONFIG = ENABLE_ALT_RECONFIG,
the_altera_tse_gxb_gige_inst_22.ENABLE_SGMII = ENABLE_SGMII,
the_altera_tse_gxb_gige_inst_22.STARTING_CHANNEL_NUMBER = STARTING_CHANNEL_NUMBER + 88,
the_altera_tse_gxb_gige_inst_22.DEVICE_FAMILY = DEVICE_FAMILY;
end
else
begin
assign reconfig_fromgxb_22 = {17{1'b0}};
assign led_char_err_gx[22] = 1'b0;
assign link_status[22] = 1'b0;
assign led_disp_err_22 = 1'b0;
assign txp_22 = 1'b0;
assign pcs_clk_c22 = 1'b0;
end
endgenerate
// #######################################################################
// ############### CHANNEL 23 LOGIC/COMPONENTS ###############
// #######################################################################
// Export powerdown signal or wire it internally
// ---------------------------------------------
reg data_in_23,gxb_pwrdn_in_sig_clk_23;
generate if (EXPORT_PWRDN == 1 && MAX_CHANNELS > 23)
begin
always @(posedge clk or posedge gxb_pwrdn_in_23)
begin
if (gxb_pwrdn_in_23 == 1) begin
data_in_23 <= 1;
gxb_pwrdn_in_sig_clk_23 <= 1;
end else begin
data_in_23 <= 1'b0;
gxb_pwrdn_in_sig_clk_23 <= data_in_23;
end
end
assign gxb_pwrdn_in_sig[23] = gxb_pwrdn_in_23;
assign pcs_pwrdn_out_23 = pcs_pwrdn_out_sig[23];
end
else
begin
assign gxb_pwrdn_in_sig[23] = pcs_pwrdn_out_sig[23];
assign pcs_pwrdn_out_23 = 1'b0;
always@(*) begin
gxb_pwrdn_in_sig_clk_23 = gxb_pwrdn_in_sig[23];
end
end
endgenerate
generate if (MAX_CHANNELS > 23)
begin
wire locked_signal_23;
// Reset logic used to reset the PMA blocks
// ----------------------------------------
// ALTGX Reset Sequencer
altera_tse_reset_sequencer altera_tse_reset_sequencer_inst_23(
// User inputs and outputs
.clock(clk),
.reset_all(reset|gxb_pwrdn_in_sig_clk_23),
//.reset_tx_digital(reset_ref_clk),
//.reset_rx_digital(reset_ref_clk),
.powerdown_all(reset_posedge),
.tx_ready(), // output
.rx_ready(), // output
// I/O transceiver and status
.pll_powerdown(pll_powerdown_sqcnr_23),// output
.tx_digitalreset(tx_digitalreset_sqcnr_23),// output
.rx_analogreset(rx_analogreset_sqcnr_23),// output
.rx_digitalreset(rx_digitalreset_sqcnr_23),// output
.gxb_powerdown(gxb_powerdown_sqcnr_23),// output
.pll_is_locked(locked_signal_23),
.rx_is_lockedtodata(rx_freqlocked_23),
.manual_mode(1'b0),
.rx_oc_busy(reconfig_busy_23)
);
assign locked_signal_23 = (reset? 1'b0: pll_locked_23);
// Instantiation of the Alt2gxb and Alt4gxb block as the PMA for Stratix_II_GX ,ArriaGX and Stratix IV devices
// -----------------------------------------------------------------------------------
// Aligned Rx_sync from gxb
// -------------------------------
altera_tse_reset_synchronizer ch_23_reset_sync_0 (
.clk(rx_pcs_clk_c23),
.reset_in(rx_digitalreset_sqcnr_23),
.reset_out(reset_rx_pcs_clk_c23_int)
);
altera_tse_gxb_aligned_rxsync the_altera_tse_gxb_aligned_rxsync_23
(
.clk(rx_pcs_clk_c23),
.reset(reset_rx_pcs_clk_c23_int),
//input (from alt2gxb)
.alt_dataout(rx_frame_23),
.alt_sync(rx_syncstatus[23]),
.alt_disperr(rx_disp_err[23]),
.alt_ctrldetect(rx_kchar_23),
.alt_errdetect(rx_char_err_gx[23]),
.alt_rmfifodatadeleted(rx_rmfifodatadeleted[23]),
.alt_rmfifodatainserted(rx_rmfifodatainserted[23]),
.alt_runlengthviolation(rx_runlengthviolation[23]),
.alt_patterndetect(rx_patterndetect[23]),
.alt_runningdisp(rx_runningdisp[23]),
//output (to PCS)
.altpcs_dataout(pcs_rx_frame_23),
.altpcs_sync(link_status[23]),
.altpcs_disperr(led_disp_err_23),
.altpcs_ctrldetect(pcs_rx_kchar_23),
.altpcs_errdetect(led_char_err_gx[23]),
.altpcs_rmfifodatadeleted(pcs_rx_rmfifodatadeleted[23]),
.altpcs_rmfifodatainserted(pcs_rx_rmfifodatainserted[23]),
.altpcs_carrierdetect(pcs_rx_carrierdetected[23])
) ;
defparam
the_altera_tse_gxb_aligned_rxsync_23.DEVICE_FAMILY = DEVICE_FAMILY;
// Altgxb in GIGE mode
// --------------------
altera_tse_gxb_gige_inst the_altera_tse_gxb_gige_inst_23
(
.cal_blk_clk (gxb_cal_blk_clk),
.gxb_powerdown (gxb_pwrdn_in_sig[23]),
.pll_inclk (ref_clk),
.rx_recovclkout(rx_recovclkout_23),
.reconfig_clk(reconfig_clk_23),
.reconfig_togxb(reconfig_togxb_23),
.reconfig_fromgxb(reconfig_fromgxb_23),
.rx_analogreset (rx_analogreset_sqcnr_23),
.rx_cruclk (ref_clk),
.rx_ctrldetect (rx_kchar_23),
.rx_clkout (rx_pcs_clk_c23),
.rx_datain (rxp_23),
.rx_dataout (rx_frame_23),
.rx_digitalreset (rx_digitalreset_sqcnr_23),
.rx_disperr (rx_disp_err[23]),
.rx_errdetect (rx_char_err_gx[23]),
.rx_patterndetect (rx_patterndetect[23]),
.rx_rlv (rx_runlengthviolation[23]),
.rx_seriallpbken (sd_loopback_23),
.rx_syncstatus (rx_syncstatus[23]),
.tx_clkout (tx_pcs_clk_c23),
.tx_ctrlenable (tx_kchar_23),
.tx_datain (tx_frame_23),
.rx_freqlocked (rx_freqlocked_23),
.tx_dataout (txp_23),
.tx_digitalreset (tx_digitalreset_sqcnr_23),
.rx_rmfifodatadeleted(rx_rmfifodatadeleted[23]),
.rx_rmfifodatainserted(rx_rmfifodatainserted[23]),
.rx_runningdisp(rx_runningdisp[23]),
.pll_powerdown(gxb_pwrdn_in_sig[23]),
.pll_locked(pll_locked_23)
);
defparam
the_altera_tse_gxb_gige_inst_23.ENABLE_ALT_RECONFIG = ENABLE_ALT_RECONFIG,
the_altera_tse_gxb_gige_inst_23.ENABLE_SGMII = ENABLE_SGMII,
the_altera_tse_gxb_gige_inst_23.STARTING_CHANNEL_NUMBER = STARTING_CHANNEL_NUMBER + 92,
the_altera_tse_gxb_gige_inst_23.DEVICE_FAMILY = DEVICE_FAMILY;
end
else
begin
assign reconfig_fromgxb_23 = {17{1'b0}};
assign led_char_err_gx[23] = 1'b0;
assign link_status[23] = 1'b0;
assign led_disp_err_23 = 1'b0;
assign txp_23 = 1'b0;
assign pcs_clk_c23 = 1'b0;
end
endgenerate
endmodule
|
module csr_cmd_decoder(
input wire [7:0] cmd,
output wire nop,
output wire special,
output wire we,
output wire [7:0] nrep,
output wire target_nkmdprom,
output wire target_csr,
output wire [3:0] addr_high);
assign we = cmd[7];
function [7:0] decode_nrep(
input [1:0] enc);
begin
case (enc)
2'b00: decode_nrep = 8'd0;
2'b01: decode_nrep = 8'd1;
2'b10: decode_nrep = 8'd4;
2'b11: decode_nrep = 8'd16;
endcase
end
endfunction
assign nrep = decode_nrep(cmd[6:5]);
assign nop = cmd[6:5] == 2'b00 && cmd[3:0] != 4'hf;
assign target_nkmdprom = cmd[4] == 1'b1;
assign target_csr = cmd[4] == 1'b0;
assign special = cmd[6:5] == 2'b00 && cmd[3:0] == 4'hf;
assign addr_high = cmd[3:0];
endmodule
|
module csr_spi #(
parameter NUM_CH = 8,
parameter NUM_SPDIF_IN = 3,
parameter NUM_RATE = 5,
parameter VOL_WIDTH = NUM_CH*32,
parameter NKMDDBG_WIDTH = 16*8,
parameter RATE_WIDTH = NUM_SPDIF_IN*NUM_RATE,
parameter UDATA_WIDTH = NUM_SPDIF_IN*192,
parameter CDATA_WIDTH = UDATA_WIDTH
)(
input wire clk,
input wire rst,
// spi access
input wire sck,
output wire miso,
input wire mosi,
input wire ss,
// csr registers access
output wire [(VOL_WIDTH-1):0] vol_o,
output wire nkmd_rst_o,
input wire [(NKMDDBG_WIDTH-1):0] nkmd_dbgout_i,
output wire [(NKMDDBG_WIDTH-1):0] nkmd_dbgin_o,
input wire [(RATE_WIDTH-1):0] rate_i,
input wire [(UDATA_WIDTH-1):0] udata_i,
input wire [(CDATA_WIDTH-1):0] cdata_i,
// nkmd prom
output wire [31:0] prom_addr_o,
output wire [31:0] prom_data_o,
output wire prom_ack_o,
// dram peek/poke
output wire [27:0] dram0_addr_o,
output wire [31:0] dram0_data_o,
output wire dram0_we_o,
output wire dram0_pop_o,
input wire [31:0] dram0_data_i,
input wire dram0_ack_i,
input wire dram0_busy_i);
wire spi_rst;
wire [7:0] spi_data_rx;
wire spi_ack_pop_o;
wire spi_ack_i;
wire [7:0] spi_data_tx;
spi_trx spi_trx(
.clk(clk),
.sck(sck), .miso(miso), .mosi(mosi), .ss(ss),
.rst_o(spi_rst),
.data_o(spi_data_rx), .ack_pop_o(spi_ack_pop_o),
.data_i(spi_data_tx), .ack_i(spi_ack_i));
wire dec_nop;
wire dec_special;
wire dec_we;
wire dec_target_nkmdprom;
wire dec_target_csr;
wire [7:0] dec_nrep;
wire [3:0] dec_addr_high;
csr_cmd_decoder csr_cmd_decoder(
.cmd(spi_data_rx),
.nop(dec_nop),
.special(dec_special),
.we(dec_we),
.nrep(dec_nrep),
.target_nkmdprom(dec_target_nkmdprom), .target_csr(dec_target_csr),
.addr_high(dec_addr_high));
reg cmd_we_ff;
reg [7:0] nrep_ff;
reg [19:0] addr_ff;
reg [31:0] sp_addr_ff;
reg [31:0] rdata_ff;
reg [31:0] wdata_ff;
wire [11:0] csr_addr;
wire csr_ack_i;
wire [7:0] csr_data_o;
reg [15:0] state_ff;
localparam ST_INIT = 0;
localparam ST_SPECIAL = 1;
localparam ST_PENDING_CSR_ADDR = 2;
localparam ST_PENDING_CSR_DATA = 3;
localparam ST_RESPOND_CSR_DATA = 4;
localparam ST_PENDING_NKMDPROM_ADDR_MID = 5;
localparam ST_PENDING_NKMDPROM_ADDR_LOW = 6;
localparam ST_PENDING_NKMDPROM_DATA = 7;
localparam ST_WRITING_NKMDPROM_DATA = 8;
localparam ST_SP_PENDING_ADDR = 9;
localparam ST_SP_WAIT_READY_TO_READ_DATA = 10;
localparam ST_SP_READ_DATA = 11;
localparam ST_SP_READ_WAIT_ACK = 12;
localparam ST_SP_PENDING_DATA = 13;
localparam ST_SP_WRITE_DATA = 14;
reg [1:0] addr_offset_ff; // For 32bit addrs, this reg will keep which sp_addr_ff octet needs to be filled in next
reg [1:0] data_offset_ff; // For 32bit targets, this reg will keep which wdata_ff octet needs to be filled in next
reg [7:0] data_tx_ff;
assign spi_data_tx = data_tx_ff;
reg data_ready_ff;
assign spi_ack_i = data_ready_ff;
always @(posedge clk) begin
if (rst) begin
state_ff <= ST_INIT;
data_tx_ff <= 8'h00;
data_ready_ff <= 0;
cmd_we_ff <= 1'b0;
addr_ff <= 20'b0;
sp_addr_ff <= 32'b0;
wdata_ff <= 32'b0;
data_offset_ff <= 2'h0;
end else begin
case (state_ff)
ST_INIT: begin
if (spi_ack_pop_o) begin
cmd_we_ff <= dec_we;
nrep_ff <= dec_nrep;
addr_ff <= {dec_addr_high, 16'h0};
data_offset_ff <= 2'h0;
data_ready_ff <= 1;
if (dec_nop) begin
data_tx_ff <= 8'h90;
state_ff <= ST_INIT;
end else if (dec_special) begin
data_tx_ff <= 8'h91;
state_ff <= ST_SPECIAL;
end else if (dec_target_csr) begin
data_tx_ff <= 8'hcc;
state_ff <= ST_PENDING_CSR_ADDR;
end else if (dec_target_nkmdprom) begin
data_tx_ff <= 8'hca;
state_ff <= ST_PENDING_NKMDPROM_ADDR_MID;
end else begin
/* NOT REACHED */
data_tx_ff <= 8'h90;
state_ff <= ST_INIT;
end
end else begin
data_ready_ff <= 0;
state_ff <= ST_INIT;
end
end
ST_SPECIAL: begin
if (spi_ack_pop_o) begin
cmd_we_ff <= dec_we;
nrep_ff <= dec_nrep;
addr_offset_ff <= 2'h3;
state_ff <= ST_SP_PENDING_ADDR;
data_tx_ff <= 8'hc0;
data_ready_ff <= 1;
end else begin
state_ff <= ST_SPECIAL;
data_ready_ff <= 0;
end
end
ST_PENDING_CSR_ADDR: begin
if (spi_ack_pop_o) begin
addr_ff <= {addr_ff[19:16], spi_data_rx[7:0], 8'h0};
data_tx_ff <= 8'had;
data_ready_ff <= 1;
state_ff <= ST_PENDING_CSR_DATA;
end else begin
data_ready_ff <= 0;
state_ff <= ST_PENDING_CSR_ADDR;
end
end
ST_PENDING_CSR_DATA: begin
data_ready_ff <= 0;
if (spi_ack_pop_o) begin
state_ff <= ST_RESPOND_CSR_DATA;
end else begin
state_ff <= ST_PENDING_CSR_DATA;
end
end
ST_RESPOND_CSR_DATA: begin
data_tx_ff <= csr_data_o;
data_ready_ff <= 1;
addr_ff[19:8] <= addr_ff[19:8] + 1;
if (nrep_ff != 8'h01) begin
nrep_ff <= nrep_ff - 1;
state_ff <= ST_PENDING_CSR_DATA;
end else begin
state_ff <= ST_INIT;
end
end
ST_PENDING_NKMDPROM_ADDR_MID: begin
if (spi_ack_pop_o) begin
data_tx_ff <= 8'ha0;
data_ready_ff <= 1;
addr_ff <= {addr_ff[19:16], spi_data_rx[7:0], 8'b0};
state_ff <= ST_PENDING_NKMDPROM_ADDR_LOW;
end else begin
data_ready_ff <= 0;
state_ff <= ST_PENDING_NKMDPROM_ADDR_MID;
end
end
ST_PENDING_NKMDPROM_ADDR_LOW: begin
if (spi_ack_pop_o) begin
data_tx_ff <= 8'ha1;
data_ready_ff <= 1;
addr_ff <= {addr_ff[19:16], addr_ff[15:8], spi_data_rx[7:0]};
state_ff <= ST_PENDING_NKMDPROM_DATA;
end else begin
data_ready_ff <= 0;
state_ff <= ST_PENDING_NKMDPROM_ADDR_LOW;
end
end
ST_PENDING_NKMDPROM_DATA: begin
if (spi_ack_pop_o) begin
data_tx_ff <= {4'hd, 2'b00, data_offset_ff};
data_ready_ff <= 1'b1;
wdata_ff <= {wdata_ff[23:0], spi_data_rx[7:0]};
if (data_offset_ff == 2'h3)
state_ff <= ST_WRITING_NKMDPROM_DATA;
else
state_ff <= ST_PENDING_NKMDPROM_DATA;
data_offset_ff <= data_offset_ff + 1;
end else begin
data_ready_ff <= 1'b0;
state_ff <= ST_PENDING_NKMDPROM_DATA;
end
end
ST_WRITING_NKMDPROM_DATA: begin
data_ready_ff <= 1'b0;
addr_ff <= addr_ff + 1;
if (nrep_ff != 8'h01) begin
nrep_ff <= nrep_ff - 1;
state_ff <= ST_PENDING_NKMDPROM_DATA;
end else begin
state_ff <= ST_INIT;
end
end
ST_SP_PENDING_ADDR: begin
if (spi_ack_pop_o) begin
data_tx_ff <= {4'ha, 2'b00, addr_offset_ff};
data_ready_ff <= 1;
sp_addr_ff <= {sp_addr_ff[23:0], spi_data_rx[7:0]};
addr_offset_ff <= addr_offset_ff - 1;
if (addr_offset_ff != 4'h0) begin
state_ff <= ST_SP_PENDING_ADDR;
end else begin
state_ff <= ST_SP_WAIT_READY_TO_READ_DATA;
end
end else begin
data_ready_ff <= 1'b0;
state_ff <= ST_SP_PENDING_ADDR;
end
end
ST_SP_WAIT_READY_TO_READ_DATA: begin
data_ready_ff <= 1'b0;
if (dram0_busy_i)
state_ff <= ST_SP_WAIT_READY_TO_READ_DATA;
else
state_ff <= ST_SP_READ_DATA;
end
ST_SP_READ_DATA: begin
data_ready_ff <= 1'b0;
state_ff <= ST_SP_READ_WAIT_ACK;
end
ST_SP_READ_WAIT_ACK: begin
data_ready_ff <= 1'b0;
if (dram0_ack_i) begin
rdata_ff <= dram0_data_i;
state_ff <= ST_SP_PENDING_DATA;
end else begin
state_ff <= ST_SP_READ_WAIT_ACK;
end
end
ST_SP_PENDING_DATA: begin
if (spi_ack_pop_o) begin
wdata_ff <= {wdata_ff[23:0], spi_data_rx[7:0]};
data_offset_ff <= data_offset_ff + 1;
if (data_offset_ff == 4'h3)
state_ff <= ST_SP_WRITE_DATA;
else
state_ff <= ST_SP_PENDING_DATA;
case (data_offset_ff)
2'h3: data_tx_ff <= rdata_ff[7:0];
2'h2: data_tx_ff <= rdata_ff[15:8];
2'h1: data_tx_ff <= rdata_ff[23:16];
2'h0: data_tx_ff <= rdata_ff[31:24];
endcase
data_ready_ff <= 1;
end else begin
data_ready_ff <= 0;
state_ff <= ST_SP_PENDING_DATA;
end
end
ST_SP_WRITE_DATA: begin
data_ready_ff <= 1'b0;
sp_addr_ff <= sp_addr_ff + 1;
if (nrep_ff != 8'h01) begin
nrep_ff <= nrep_ff - 1;
state_ff <= ST_SP_WAIT_READY_TO_READ_DATA;
end else begin
state_ff <= ST_INIT;
end
end
default: begin
data_ready_ff <= 0;
state_ff <= ST_INIT;
end
endcase
end
end
csr #(.NUM_CH(NUM_CH), .NUM_SPDIF_IN(NUM_SPDIF_IN)) csr(
.clk(clk), .rst(rst),
.addr_i(csr_addr), .ack_i(csr_ack_i), .data_i(spi_data_rx), .data_o(csr_data_o),
.vol_o(vol_o),
.nkmd_rst_o(nkmd_rst_o), .nkmd_dbgout_i(nkmd_dbgout_i), .nkmd_dbgin_o(nkmd_dbgin_o),
.rate_i(rate_i), .udata_i(udata_i), .cdata_i(cdata_i));
assign csr_addr = addr_ff[19:8];
assign csr_ack_i = state_ff == ST_PENDING_CSR_DATA && spi_ack_pop_o == 1'b1 && cmd_we_ff == 1'b1;
assign prom_addr_o = {12'b0, addr_ff[19:0]};
assign prom_data_o = wdata_ff;
assign prom_ack_o = (state_ff == ST_WRITING_NKMDPROM_DATA);
assign dram0_addr_o = sp_addr_ff[27:0];
assign dram0_data_o = wdata_ff;
assign dram0_we_o = (cmd_we_ff == 1'b1 && state_ff == ST_SP_WRITE_DATA) ? 1'b1 : 1'b0;
assign dram0_pop_o = (state_ff == ST_SP_READ_DATA) ? 1'b1 : 1'b0;
endmodule
|
module sky130_fd_sc_lp__bushold (
X ,
RESET
);
inout X ;
input RESET;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
|
module sky130_fd_sc_ls__o22a_2 (
X ,
A1 ,
A2 ,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__o22a base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
|
module sky130_fd_sc_ls__o22a_2 (
X ,
A1,
A2,
B1,
B2
);
output X ;
input A1;
input A2;
input B1;
input B2;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__o22a base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2)
);
endmodule
|
module sky130_fd_sc_ls__decaphetap ();
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
endmodule
|
module sky130_fd_sc_lp__maj3 (
X ,
A ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire or0_out ;
wire and0_out ;
wire and1_out ;
wire or1_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
or or0 (or0_out , B, A );
and and0 (and0_out , or0_out, C );
and and1 (and1_out , A, B );
or or1 (or1_out_X , and1_out, and0_out );
sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, or1_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
|
module sky130_fd_sc_hd__einvp_4 (
Z ,
A ,
TE ,
VPWR,
VGND,
VPB ,
VNB
);
output Z ;
input A ;
input TE ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__einvp base (
.Z(Z),
.A(A),
.TE(TE),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
|
module sky130_fd_sc_hd__einvp_4 (
Z ,
A ,
TE
);
output Z ;
input A ;
input TE;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__einvp base (
.Z(Z),
.A(A),
.TE(TE)
);
endmodule
|
module uart51_tx(
BAUD_CLK,
RESET_N,
TX_DATA,
TX_START,
TX_DONE,
TX_STOP,
TX_WORD,
TX_PAR_DIS,
TX_PARITY,
CTS,
TX_BUFFER
);
input BAUD_CLK;
input RESET_N;
output TX_DATA;
reg TX_DATA;
input TX_START;
output TX_DONE;
reg TX_DONE;
input TX_STOP;
input [1:0] TX_WORD;
input TX_PAR_DIS;
input [1:0] TX_PARITY;
input CTS;
input [7:0] TX_BUFFER;
reg [6:0] STATE;
reg [2:0] BIT;
wire PARITY;
reg TX_START0;
reg TX_START1;
assign PARITY = (~TX_PARITY[1]
& ((TX_BUFFER[0] ^ TX_BUFFER[1])
^ (TX_BUFFER[2] ^ TX_BUFFER[3]))
^ (TX_BUFFER[4]
^ (TX_BUFFER[5] & (TX_WORD != 2'b00)))
^ ((TX_BUFFER[6] & (TX_WORD[1] == 1'b1))
^ (TX_BUFFER[7] & (TX_WORD == 2'b11)))) // clear bit #8 if only 7 bits
^ ~TX_PARITY[0];
always @ (negedge BAUD_CLK or negedge RESET_N)
begin
if(!RESET_N)
begin
STATE <= 7'b0000000;
TX_DATA <= 1'b1;
TX_DONE <= 1'b1;
BIT <= 3'b000;
TX_START0 <= 1'b0;
TX_START1 <= 1'b0;
end
else
begin
TX_START0 <= TX_START;
TX_START1 <= TX_START0;
case (STATE)
7'b0000000:
begin
BIT <= 3'b000;
TX_DATA <= 1'b1;
if(TX_START1 == 1'b1)
begin
TX_DONE <= 1'b0;
STATE <= 7'b0000001;
end
end
7'b0000001: // Start bit
begin
TX_DATA <= 1'b0;
STATE <= 7'b0000010;
end
7'b0010001:
begin
TX_DATA <= TX_BUFFER[BIT];
STATE <= 7'b0010010;
end
7'b0100000:
begin
BIT <= BIT + 1'b1;
if((TX_WORD == 2'b00) && (BIT != 3'b111))
begin
STATE <= 7'b0010001;
end
else
begin
if((TX_WORD == 2'b01) && (BIT != 3'b110))
begin
STATE <= 7'b0010001;
end
else
begin
if((TX_WORD == 2'b10) && (BIT != 3'b101))
begin
STATE <= 7'b0010001;
end
else
begin
if((TX_WORD == 2'b11) && (BIT != 3'b100))
begin
STATE <= 7'b0010001;
end
else
begin
if(!TX_PAR_DIS)
begin
STATE <= 7'b0100001; // do parity
end
else
begin
STATE <= 7'b0110001; // do stop
end
end
end
end
end
end
// Start parity bit
7'b0100001:
begin
TX_DATA <= PARITY;
STATE <= 7'b0100010;
end
// start stop
7'b0110001:
begin
TX_DONE <= 1'b1;
TX_DATA <= 1'b1;
STATE <= 7'b0110010;
end
// end of first stop bit-1
7'b0111111:
begin
if(!TX_STOP)
STATE <= 7'b1001111; // go check for CTS
else
STATE <= 7'b1000000;
end
7'b1001111:
begin
if(!CTS) // this is not correct for a 6551
begin
STATE <= 7'b0000000;
end
end
default: STATE <= STATE + 1'b1;
endcase
end
end
endmodule
|
module sky130_fd_sc_hs__tapvpwrvgnd (
VPWR,
VGND
);
input VPWR;
input VGND;
endmodule
|
module sky130_fd_sc_hs__o311ai (
Y ,
A1 ,
A2 ,
A3 ,
B1 ,
C1 ,
VPWR,
VGND
);
output Y ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input C1 ;
input VPWR;
input VGND;
endmodule
|
module sky130_fd_sc_lp__a21bo (
//# {{data|Data Signals}}
input A1 ,
input A2 ,
input B1_N,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
|
module header
// Internal signals
//
// Generated Signal List
//
wire [7:0] s_port_offset_01;
wire [7:0] s_port_offset_02;
wire [1:0] s_port_offset_02b;
wire test1; // __W_PORT_SIGNAL_MAP_REQ
wire [4:0] test2;
wire [3:0] test3;
//
// End of Generated Signal List
//
// %COMPILER_OPTS%
// Generated Signal Assignments
assign p_mix_test1_go = test1; // __I_O_BIT_PORT
//
// Generated Instances
// wiring ...
// Generated Instances and Port Mappings
// Generated Instance Port Map for inst_aa
ent_aa inst_aa (
.port_1(test1), // Use internally test1
.port_2(test2[0]), // Bus with hole in the middleNeeds input to be happy
.port_3(test3[0]), // Bus combining o.k.
.port_o(s_port_offset_01),
.port_o02[10:3](s_port_offset_02), // __W_PORT// __E_CANNOT_COMBINE_SPLICES
.port_o02[1:0](s_port_offset_02b) // __W_PORT// __E_CANNOT_COMBINE_SPLICES
);
// End of Generated Instance Port Map for inst_aa
// Generated Instance Port Map for inst_ab
ent_ab inst_ab (
.port_2(test2[1]), // Bus with hole in the middleNeeds input to be happy
.port_3(test3[1]), // Bus combining o.k.
.port_ab_1(test1), // Use internally test1
.port_i(s_port_offset_01),
.port_i02[10:3](s_port_offset_02), // __W_PORT// __E_CANNOT_COMBINE_SPLICES
.port_i02[2:1](s_port_offset_02b) // __W_PORT// __E_CANNOT_COMBINE_SPLICES
);
// End of Generated Instance Port Map for inst_ab
// Generated Instance Port Map for inst_ac
ent_ac inst_ac (
.port_2(test2[3]), // Bus with hole in the middleNeeds input to be happy
.port_3(test3[2]) // Bus combining o.k.
);
// End of Generated Instance Port Map for inst_ac
// Generated Instance Port Map for inst_ad
ent_ad inst_ad (
.port_2(test2[4]), // Bus with hole in the middleNeeds input to be happy
.port_3(test3[3]) // Bus combining o.k.
);
// End of Generated Instance Port Map for inst_ad
// Generated Instance Port Map for inst_ae
ent_ae inst_ae (
.port_2(test2), // Bus with hole in the middleNeeds input to be happy
.port_3(test3) // Bus combining o.k.
);
// End of Generated Instance Port Map for inst_ae
endmodule
|
module wb_gpio
#(
parameter n_bits = 32 // bus width, range 1:32
)
(
input wb_clk,
input wb_rst,
input [2:2] wb_adr_i,
input [n_bits-1:0] wb_dat_i,
input wb_we_i,
input wb_cyc_i,
input wb_stb_i,
input [2:0] wb_cti_i,
input [1:0] wb_bte_i,
output reg [n_bits-1:0] wb_dat_o,
output reg wb_ack_o,
output wb_err_o,
output wb_rty_o,
input [n_bits-1:0] gpio_i,
output reg [n_bits-1:0] gpio_o,
output reg [n_bits-1:0] gpio_dir_o
);
// GPIO dir register
always @(posedge wb_clk)
if (wb_rst)
gpio_dir_o <= 0; // All set to in at reset
else if (wb_cyc_i & wb_stb_i & wb_we_i) begin
if (wb_adr_i[2] == 1)
gpio_dir_o <= wb_dat_i[n_bits-1:0];
end
// GPIO data out register
always @(posedge wb_clk)
if (wb_rst)
gpio_o <= 0;
else if (wb_cyc_i & wb_stb_i & wb_we_i) begin
if (wb_adr_i[2] == 0)
gpio_o <= wb_dat_i[n_bits-1:0];
end
// Register the gpio in signal
reg [n_bits-1:0] gpio_i_ff;
always @(posedge wb_clk) begin
// Synchronize gpio_i
// single ff because the second ff only adds enable logic and clk freq is low
gpio_i_ff <= gpio_i;
// Data regs
if (wb_adr_i[2] == 0)
wb_dat_o <= gpio_i_ff;
// Direction regs
if (wb_adr_i[2] == 1)
wb_dat_o <= gpio_dir_o;
end
// Ack generation
always @(posedge wb_clk)
if (wb_rst)
wb_ack_o <= 0;
else if (wb_ack_o)
wb_ack_o <= 0;
else if (wb_cyc_i & wb_stb_i & !wb_ack_o)
wb_ack_o <= 1;
assign wb_err_o = 0;
assign wb_rty_o = 0;
endmodule
|
module sky130_fd_sc_hs__xnor2 (
Y ,
A ,
B ,
VPWR,
VGND
);
output Y ;
input A ;
input B ;
input VPWR;
input VGND;
endmodule
|
module oq_regs_host_iface
#(
parameter SRAM_ADDR_WIDTH = 13,
parameter CTRL_WIDTH = 8,
parameter UDP_REG_SRC_WIDTH = 2,
parameter NUM_OUTPUT_QUEUES = 8,
parameter NUM_OQ_WIDTH = log2(NUM_OUTPUT_QUEUES),
parameter NUM_REGS_USED = 17,
parameter ADDR_WIDTH = log2(NUM_REGS_USED)
)
(
// --- interface to udp_reg_grp
input reg_req_in,
input reg_ack_in,
input reg_rd_wr_L_in,
input [`UDP_REG_ADDR_WIDTH-1:0] reg_addr_in,
input [`CPCI_NF2_DATA_WIDTH-1:0] reg_data_in,
input [UDP_REG_SRC_WIDTH-1:0] reg_src_in,
output reg reg_req_out,
output reg reg_ack_out,
output reg reg_rd_wr_L_out,
output reg [`UDP_REG_ADDR_WIDTH-1:0] reg_addr_out,
output reg [`CPCI_NF2_DATA_WIDTH-1:0] reg_data_out,
output reg [UDP_REG_SRC_WIDTH-1:0] reg_src_out,
// --- interface to oq_regs_process_sm
output reg req_in_progress,
output reg reg_rd_wr_L_held,
output reg [`CPCI_NF2_DATA_WIDTH-1:0] reg_data_held,
output [ADDR_WIDTH-1:0] addr,
output [NUM_OQ_WIDTH-1:0] q_addr,
input result_ready,
input [`CPCI_NF2_DATA_WIDTH-1:0] reg_result,
// --- Misc
input clk,
input reset
);
function integer log2;
input integer number;
begin
log2=0;
while(2**log2<number) begin
log2=log2+1;
end
end
endfunction // log2
// ------------- Wires/reg ------------------
// Register hit/processing signals
wire [`OQ_QUEUE_INST_REG_ADDR_WIDTH - 1:0] local_reg_addr; // Register number
wire [`OQ_REG_ADDR_WIDTH -
`OQ_QUEUE_INST_REG_ADDR_WIDTH - 1:0] local_q_addr; // Queue address/number
wire [`UDP_REG_ADDR_WIDTH -
`OQ_REG_ADDR_WIDTH - 1:0] tag_addr;
wire addr_good;
wire tag_hit;
reg reg_req_held;
reg [`UDP_REG_ADDR_WIDTH-1:0] reg_addr_held;
reg [UDP_REG_SRC_WIDTH-1:0] reg_src_held;
// -------------- Logic ----------------------
assign local_reg_addr = reg_addr_in[`OQ_QUEUE_INST_REG_ADDR_WIDTH-1:0];
assign local_q_addr = reg_addr_in[`OQ_REG_ADDR_WIDTH - 1:`OQ_QUEUE_INST_REG_ADDR_WIDTH];
assign tag_addr = reg_addr_in[`UDP_REG_ADDR_WIDTH - 1:`OQ_REG_ADDR_WIDTH];
assign addr_good = (local_reg_addr<NUM_REGS_USED) && (local_q_addr < NUM_OUTPUT_QUEUES);
assign tag_hit = tag_addr == `OQ_BLOCK_ADDR;
assign addr = reg_addr_held[ADDR_WIDTH-1:0];
assign q_addr = reg_addr_held[`OQ_QUEUE_INST_REG_ADDR_WIDTH + NUM_OQ_WIDTH - 1:`OQ_QUEUE_INST_REG_ADDR_WIDTH];
// Handle register accesses
always @(posedge clk) begin
if (reset) begin
reg_req_out <= 1'b0;
reg_ack_out <= 1'b0;
reg_rd_wr_L_out <= 'h0;
reg_addr_out <= 'h0;
reg_src_out <= 'h0;
reg_req_held <= 1'b0;
reg_rd_wr_L_held <= 'h0;
reg_addr_held <= 'h0;
reg_data_held <= 'h0;
reg_src_held <= 'h0;
req_in_progress <= 1'b0;
end
else begin
if (req_in_progress) begin
if (result_ready) begin
req_in_progress <= 1'b0;
reg_req_out <= reg_req_held;
reg_ack_out <= reg_req_held;
reg_rd_wr_L_out <= reg_rd_wr_L_held;
reg_addr_out <= reg_addr_held;
reg_data_out <= reg_result;
reg_src_out <= reg_src_held;
end
end
else if (reg_req_in && tag_hit && addr_good) begin
req_in_progress <= 1'b1;
reg_req_held <= reg_req_in;
reg_rd_wr_L_held <= reg_rd_wr_L_in;
reg_addr_held <= reg_addr_in;
reg_data_held <= reg_data_in;
reg_src_held <= reg_src_in;
reg_req_out <= 1'b0;
reg_ack_out <= 1'b0;
reg_rd_wr_L_out <= 'h0;
reg_addr_out <= 'h0;
reg_data_out <= 'h0;
reg_src_out <= 'h0;
end
else begin
reg_req_out <= reg_req_in;
reg_ack_out <= reg_ack_in || reg_req_in && tag_hit;
reg_rd_wr_L_out <= reg_rd_wr_L_in;
reg_addr_out <= reg_addr_in;
reg_data_out <= (reg_req_in && tag_hit) ? 32'h dead_beef : reg_data_in;
reg_src_out <= reg_src_in;
end
end
end
endmodule
|
module sky130_fd_sc_ms__fill_8 (
VPWR,
VGND,
VPB ,
VNB
);
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ms__fill base (
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
|
module sky130_fd_sc_ms__fill_8 ();
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__fill base ();
endmodule
|
module sky130_fd_sc_hs__dlymetal6s2s (
VPWR,
VGND,
X ,
A
);
// Module ports
input VPWR;
input VGND;
output X ;
input A ;
// Local signals
wire buf0_out_X ;
wire u_vpwr_vgnd0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X , A );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_X, buf0_out_X, VPWR, VGND);
buf buf1 (X , u_vpwr_vgnd0_out_X );
endmodule
|
module FIFOL20(CLK,
RST,
ENQ,
FULL_N,
DEQ,
EMPTY_N,
CLR
);
input RST;
input CLK;
input ENQ;
input CLR;
input DEQ;
output FULL_N;
output EMPTY_N;
reg empty_reg;
reg full_reg;
assign FULL_N = full_reg || DEQ;
assign EMPTY_N = empty_reg ;
`ifdef BSV_NO_INITIAL_BLOCKS
`else // not BSV_NO_INITIAL_BLOCKS
// synopsys translate_off
initial
begin
empty_reg = 1'b0 ;
full_reg = 1'b1 ;
end // initial begin
// synopsys translate_on
`endif // BSV_NO_INITIAL_BLOCKS
always@(posedge CLK `BSV_ARESET_EDGE_META)
begin
if (RST == `BSV_RESET_VALUE)
begin
empty_reg <= `BSV_ASSIGNMENT_DELAY 1'b0;
full_reg <= `BSV_ASSIGNMENT_DELAY 1'b1;
end // if (RST == `BSV_RESET_VALUE)
else
begin
if (CLR)
begin
empty_reg <= `BSV_ASSIGNMENT_DELAY 1'b0;
full_reg <= `BSV_ASSIGNMENT_DELAY 1'b1;
end
else if (ENQ && !DEQ)
begin
empty_reg <= `BSV_ASSIGNMENT_DELAY 1'b1;
full_reg <= `BSV_ASSIGNMENT_DELAY ! empty_reg;
end
else if (!ENQ && DEQ)
begin
full_reg <= `BSV_ASSIGNMENT_DELAY 1'b1;
empty_reg <= `BSV_ASSIGNMENT_DELAY ! full_reg;
end // if (!ENQ && DEQ)
end // else: !if(RST == `BSV_RESET_VALUE)
end // always@ (posedge CLK or `BSV_RESET_EDGE RST)
// synopsys translate_off
always@(posedge CLK)
begin: error_checks
reg deqerror, enqerror ;
deqerror = 0;
enqerror = 0;
if (RST == ! `BSV_RESET_VALUE)
begin
if ( ! empty_reg && DEQ )
begin
deqerror = 1 ;
$display( "Warning: FIFO20: %m -- Dequeuing from empty fifo" ) ;
end
if ( ! full_reg && ENQ && !DEQ )
begin
enqerror = 1 ;
$display( "Warning: FIFO20: %m -- Enqueuing to a full fifo" ) ;
end
end // if (RST == ! `BSV_RESET_VALUE)
end
// synopsys translate_on
endmodule
|
module ledput
);
// ============================================================================
// SW0 controls IOBUF.I
assign io_i = sw[0];
// SW1 controls IOBUF.T
assign io_t = sw[1];
// SW2 controls OBUF.I (JC.3)
assign jc3 = sw[2];
// LED0 swdicates IOBUF.O
assign led[0] = io_o;
// LED1 is connected to JC.1
assign led[1] = jc1;
// Unused IOs - SW->LED passthrough.
assign led[15:2] = {sw[15:3], 1'd0};
endmodule
|
module pal_sync_generator_progressive (
input wire clk,
input wire wssclk,
input wire [2:0] ri,
input wire [2:0] gi,
input wire [2:0] bi,
output wire [8:0] hcnt,
output wire [8:0] vcnt,
output wire [2:0] ro,
output wire [2:0] go,
output wire [2:0] bo,
output wire csync
);
reg [8:0] hc = 9'h000;
reg [8:0] vc = 9'h000;
reg [8:0] rhcnt = 332; //344; //328;
reg [8:0] rvcnt = 248; // era 250
assign hcnt = rhcnt;
assign vcnt = rvcnt;
always @(posedge clk) begin
if (rhcnt == `END_COUNT_H) begin
rhcnt <= 0;
if (rvcnt == `END_COUNT_V)
rvcnt <= 0;
else
rvcnt <= rvcnt + 1;
end
else
rhcnt <= rhcnt + 1;
end
always @(posedge clk) begin
if (hc == `END_COUNT_H) begin
hc <= 0;
if (vc == `END_COUNT_V)
vc <= 0;
else
vc <= vc + 1;
end
else
hc <= hc + 1;
end
reg rsync = 1;
reg in_visible_region = 1;
assign csync = rsync;
always @(posedge clk) begin
if (hc == `BEGIN_LONG_SYNC1 && (vc == `LINE1 ||
vc == `LINE2 ||
vc == `LINE3 ))
begin
rsync <= 0;
in_visible_region <= 0;
end
else if (hc == `END_LONG_SYNC1 && (vc == `LINE1 ||
vc == `LINE2 ||
vc == `LINE3 ))
begin
rsync <= 1;
in_visible_region <= 0;
end
else if (hc == `BEGIN_LONG_SYNC2 && (vc == `LINE1 ||
vc == `LINE2 ))
begin
rsync <= 0;
in_visible_region <= 0;
end
else if (hc == `END_LONG_SYNC2 && (vc == `LINE1 ||
vc == `LINE2 ))
begin
rsync <= 1;
in_visible_region <= 0;
end
else if (hc == `BEGIN_SHORT_SYNC1 && (vc == `LINE4 ||
vc == `LINE5 ||
vc == `LINE310 ||
vc == `LINE311 ||
vc == `LINE312 ))
begin
rsync <= 0;
in_visible_region <= 0;
end
else if (hc == `END_SHORT_SYNC1 && (vc == `LINE4 ||
vc == `LINE5 ||
vc == `LINE310 ||
vc == `LINE311 ||
vc == `LINE312 ))
begin
rsync <= 1;
in_visible_region <= 0;
end
else if (hc == `BEGIN_SHORT_SYNC2 && (vc == `LINE3 ||
vc == `LINE4 ||
vc == `LINE5 ||
vc == `LINE310 ||
vc == `LINE311 ||
vc == `LINE312 ))
begin
rsync <= 0;
in_visible_region <= 0;
end
else if (hc == `END_SHORT_SYNC2 && (vc == `LINE3 ||
vc == `LINE4 ||
vc == `LINE5 ||
vc == `LINE310 ||
vc == `LINE311 ||
vc == `LINE312 ))
begin
rsync <= 1;
in_visible_region <= 0;
end
else if (vc != `LINE1 &&
vc != `LINE2 &&
vc != `LINE3 &&
vc != `LINE4 &&
vc != `LINE5 &&
vc != `LINE310 &&
vc != `LINE311 &&
vc != `LINE312 ) begin
if (hc == `BEGIN_HBLANK)
in_visible_region <= 0;
else if (hc == `BEGIN_HSYNC)
rsync <= 0;
else if (hc == `END_HSYNC)
rsync <= 1;
else if (hc == `END_HBLANK) begin
in_visible_region <= 1;
end
end
end
// see WSS standard description PDF, by ETSI
// v- Run-in code v- Start code v- Group 1 v- Group 2 v- Group 3 v- Group 4
reg [136:0] wss_data = 137'b11111000111000111000111000111000111100011110000011111000111000111000111111000111000000111000111000111000111000111000111000111000111000111;
reg wss_mstate = 0;
reg [7:0] wss_cnt = 136;
wire wss_output = (wss_mstate == 0)? 0 : wss_data[136];
always @(posedge wssclk) begin
case (wss_mstate)
0: begin
if (vc == `LINE23 && (hc == `BEGIN_WSSDATA || hc == `BEGIN_WSSDATA+1))
wss_mstate <= 1;
end
1: begin
wss_data <= {wss_data[135:0],wss_data[136]};
if (wss_cnt != 0)
wss_cnt <= wss_cnt - 1;
else begin
wss_cnt <= 136;
wss_mstate <= 0;
end
end
endcase
end
assign ro = (wss_mstate == 1)? {wss_output,1'b0,wss_output} : (vc ==`LINE23 || !in_visible_region)? 3'b000 : ri;
assign go = (wss_mstate == 1)? {wss_output,1'b0,wss_output} : (vc ==`LINE23 || !in_visible_region)? 3'b000 : gi;
assign bo = (wss_mstate == 1)? {wss_output,1'b0,wss_output} : (vc ==`LINE23 || !in_visible_region)? 3'b000 : bi;
// (* IOB = "TRUE" *) reg [2:0] rro;
// (* IOB = "TRUE" *) reg [2:0] rgo;
// (* IOB = "TRUE" *) reg [2:0] rbo;
// assign ro = rro;
// assign go = rgo;
// assign bo = rbo;
// always @(posedge clk) begin
// rro <= (wss_mstate == 1)? {wss_output,1'b0,wss_output} : (vc ==`LINE23 || !in_visible_region)? 3'b000 : ri;
// rgo <= (wss_mstate == 1)? {wss_output,1'b0,wss_output} : (vc ==`LINE23 || !in_visible_region)? 3'b000 : gi;
// rbo <= (wss_mstate == 1)? {wss_output,1'b0,wss_output} : (vc ==`LINE23 || !in_visible_region)? 3'b000 : bi;
// end
endmodule
|
module nios_mem_if_ddr2_emif_0_p0_addr_cmd_pads(
reset_n,
reset_n_afi_clk,
pll_afi_clk,
pll_mem_clk,
pll_mem_phy_clk,
pll_afi_phy_clk,
pll_c2p_write_clk,
pll_write_clk,
pll_hr_clk,
phy_ddio_addr_cmd_clk,
phy_ddio_address,
dll_delayctrl_in,
enable_mem_clk,
phy_ddio_bank,
phy_ddio_cs_n,
phy_ddio_cke,
phy_ddio_odt,
phy_ddio_we_n,
phy_ddio_ras_n,
phy_ddio_cas_n,
phy_mem_address,
phy_mem_bank,
phy_mem_cs_n,
phy_mem_cke,
phy_mem_odt,
phy_mem_we_n,
phy_mem_ras_n,
phy_mem_cas_n,
phy_mem_ck,
phy_mem_ck_n
);
parameter DEVICE_FAMILY = "";
parameter MEM_ADDRESS_WIDTH = "";
parameter MEM_BANK_WIDTH = "";
parameter MEM_CHIP_SELECT_WIDTH = "";
parameter MEM_CLK_EN_WIDTH = "";
parameter MEM_CK_WIDTH = "";
parameter MEM_ODT_WIDTH = "";
parameter MEM_CONTROL_WIDTH = "";
parameter AFI_ADDRESS_WIDTH = "";
parameter AFI_BANK_WIDTH = "";
parameter AFI_CHIP_SELECT_WIDTH = "";
parameter AFI_CLK_EN_WIDTH = "";
parameter AFI_ODT_WIDTH = "";
parameter AFI_CONTROL_WIDTH = "";
parameter DLL_WIDTH = "";
parameter REGISTER_C2P = "";
parameter IS_HHP_HPS = "";
input reset_n;
input reset_n_afi_clk;
input pll_afi_clk;
input pll_mem_clk;
input pll_mem_phy_clk;
input pll_afi_phy_clk;
input pll_write_clk;
input pll_hr_clk;
input pll_c2p_write_clk;
input phy_ddio_addr_cmd_clk;
input [DLL_WIDTH-1:0] dll_delayctrl_in;
input [MEM_CK_WIDTH-1:0] enable_mem_clk;
input [AFI_ADDRESS_WIDTH-1:0] phy_ddio_address;
input [AFI_BANK_WIDTH-1:0] phy_ddio_bank;
input [AFI_CHIP_SELECT_WIDTH-1:0] phy_ddio_cs_n;
input [AFI_CLK_EN_WIDTH-1:0] phy_ddio_cke;
input [AFI_ODT_WIDTH-1:0] phy_ddio_odt;
input [AFI_CONTROL_WIDTH-1:0] phy_ddio_ras_n;
input [AFI_CONTROL_WIDTH-1:0] phy_ddio_cas_n;
input [AFI_CONTROL_WIDTH-1:0] phy_ddio_we_n;
output [MEM_ADDRESS_WIDTH-1:0] phy_mem_address;
output [MEM_BANK_WIDTH-1:0] phy_mem_bank;
output [MEM_CHIP_SELECT_WIDTH-1:0] phy_mem_cs_n;
output [MEM_CLK_EN_WIDTH-1:0] phy_mem_cke;
output [MEM_ODT_WIDTH-1:0] phy_mem_odt;
output [MEM_CONTROL_WIDTH-1:0] phy_mem_we_n;
output [MEM_CONTROL_WIDTH-1:0] phy_mem_ras_n;
output [MEM_CONTROL_WIDTH-1:0] phy_mem_cas_n;
output [MEM_CK_WIDTH-1:0] phy_mem_ck;
output [MEM_CK_WIDTH-1:0] phy_mem_ck_n;
wire [MEM_ADDRESS_WIDTH-1:0] address_l;
wire [MEM_ADDRESS_WIDTH-1:0] address_h;
wire adc_ldc_ck;
wire [MEM_CHIP_SELECT_WIDTH-1:0] cs_n_l;
wire [MEM_CHIP_SELECT_WIDTH-1:0] cs_n_h;
wire [MEM_CLK_EN_WIDTH-1:0] cke_l;
wire [MEM_CLK_EN_WIDTH-1:0] cke_h;
reg [AFI_ADDRESS_WIDTH-1:0] phy_ddio_address_hr;
reg [AFI_BANK_WIDTH-1:0] phy_ddio_bank_hr;
reg [AFI_CHIP_SELECT_WIDTH-1:0] phy_ddio_cs_n_hr;
reg [AFI_CLK_EN_WIDTH-1:0] phy_ddio_cke_hr;
reg [AFI_ODT_WIDTH-1:0] phy_ddio_odt_hr;
reg [AFI_CONTROL_WIDTH-1:0] phy_ddio_ras_n_hr;
reg [AFI_CONTROL_WIDTH-1:0] phy_ddio_cas_n_hr;
reg [AFI_CONTROL_WIDTH-1:0] phy_ddio_we_n_hr;
generate
if (REGISTER_C2P == "false") begin
always @(*) begin
phy_ddio_address_hr = phy_ddio_address;
phy_ddio_bank_hr = phy_ddio_bank;
phy_ddio_cs_n_hr = phy_ddio_cs_n;
phy_ddio_cke_hr = phy_ddio_cke;
phy_ddio_odt_hr = phy_ddio_odt;
phy_ddio_ras_n_hr = phy_ddio_ras_n;
phy_ddio_cas_n_hr = phy_ddio_cas_n;
phy_ddio_we_n_hr = phy_ddio_we_n;
end
end else begin
always @(posedge phy_ddio_addr_cmd_clk) begin
phy_ddio_address_hr <= phy_ddio_address;
phy_ddio_bank_hr <= phy_ddio_bank;
phy_ddio_cs_n_hr <= phy_ddio_cs_n;
phy_ddio_cke_hr <= phy_ddio_cke;
phy_ddio_odt_hr <= phy_ddio_odt;
phy_ddio_ras_n_hr <= phy_ddio_ras_n;
phy_ddio_cas_n_hr <= phy_ddio_cas_n;
phy_ddio_we_n_hr <= phy_ddio_we_n;
end
end
endgenerate
wire [MEM_ADDRESS_WIDTH-1:0] phy_ddio_address_l;
wire [MEM_ADDRESS_WIDTH-1:0] phy_ddio_address_h;
wire [MEM_BANK_WIDTH-1:0] phy_ddio_bank_l;
wire [MEM_BANK_WIDTH-1:0] phy_ddio_bank_h;
wire [MEM_CHIP_SELECT_WIDTH-1:0] phy_ddio_cs_n_l;
wire [MEM_CHIP_SELECT_WIDTH-1:0] phy_ddio_cs_n_h;
wire [MEM_CLK_EN_WIDTH-1:0] phy_ddio_cke_l;
wire [MEM_CLK_EN_WIDTH-1:0] phy_ddio_cke_h;
wire [MEM_ODT_WIDTH-1:0] phy_ddio_odt_l;
wire [MEM_ODT_WIDTH-1:0] phy_ddio_odt_h;
wire [MEM_CONTROL_WIDTH-1:0] phy_ddio_ras_n_l;
wire [MEM_CONTROL_WIDTH-1:0] phy_ddio_ras_n_h;
wire [MEM_CONTROL_WIDTH-1:0] phy_ddio_cas_n_l;
wire [MEM_CONTROL_WIDTH-1:0] phy_ddio_cas_n_h;
wire [MEM_CONTROL_WIDTH-1:0] phy_ddio_we_n_l;
wire [MEM_CONTROL_WIDTH-1:0] phy_ddio_we_n_h;
// each signal has a high and a low portion,
// connecting to the high and low inputs of the DDIO_OUT,
// for the purpose of creating double data rate
assign phy_ddio_address_l = phy_ddio_address_hr[MEM_ADDRESS_WIDTH-1:0];
assign phy_ddio_bank_l = phy_ddio_bank_hr[MEM_BANK_WIDTH-1:0];
assign phy_ddio_cke_l = phy_ddio_cke_hr[MEM_CLK_EN_WIDTH-1:0];
assign phy_ddio_odt_l = phy_ddio_odt_hr[MEM_ODT_WIDTH-1:0];
assign phy_ddio_cs_n_l = phy_ddio_cs_n_hr[MEM_CHIP_SELECT_WIDTH-1:0];
assign phy_ddio_we_n_l = phy_ddio_we_n_hr[MEM_CONTROL_WIDTH-1:0];
assign phy_ddio_ras_n_l = phy_ddio_ras_n_hr[MEM_CONTROL_WIDTH-1:0];
assign phy_ddio_cas_n_l = phy_ddio_cas_n_hr[MEM_CONTROL_WIDTH-1:0];
assign phy_ddio_address_h = phy_ddio_address_hr[2*MEM_ADDRESS_WIDTH-1:MEM_ADDRESS_WIDTH];
assign phy_ddio_bank_h = phy_ddio_bank_hr[2*MEM_BANK_WIDTH-1:MEM_BANK_WIDTH];
assign phy_ddio_cke_h = phy_ddio_cke_hr[2*MEM_CLK_EN_WIDTH-1:MEM_CLK_EN_WIDTH];
assign phy_ddio_odt_h = phy_ddio_odt_hr[2*MEM_ODT_WIDTH-1:MEM_ODT_WIDTH];
assign phy_ddio_cs_n_h = phy_ddio_cs_n_hr[2*MEM_CHIP_SELECT_WIDTH-1:MEM_CHIP_SELECT_WIDTH];
assign phy_ddio_we_n_h = phy_ddio_we_n_hr[2*MEM_CONTROL_WIDTH-1:MEM_CONTROL_WIDTH];
assign phy_ddio_ras_n_h = phy_ddio_ras_n_hr[2*MEM_CONTROL_WIDTH-1:MEM_CONTROL_WIDTH];
assign phy_ddio_cas_n_h = phy_ddio_cas_n_hr[2*MEM_CONTROL_WIDTH-1:MEM_CONTROL_WIDTH];
assign address_l = phy_ddio_address_l;
assign address_h = phy_ddio_address_h;
altddio_out uaddress_pad(
.aclr (~reset_n),
.aset (1'b0),
.datain_h (address_l),
.datain_l (address_h),
.dataout (phy_mem_address),
.oe (1'b1),
.outclock (phy_ddio_addr_cmd_clk),
.outclocken (1'b1)
);
defparam
uaddress_pad.extend_oe_disable = "UNUSED",
uaddress_pad.intended_device_family = DEVICE_FAMILY,
uaddress_pad.invert_output = "OFF",
uaddress_pad.lpm_hint = "UNUSED",
uaddress_pad.lpm_type = "altddio_out",
uaddress_pad.oe_reg = "UNUSED",
uaddress_pad.power_up_high = "OFF",
uaddress_pad.width = MEM_ADDRESS_WIDTH;
altddio_out ubank_pad(
.aclr (~reset_n),
.aset (1'b0),
.datain_h (phy_ddio_bank_l),
.datain_l (phy_ddio_bank_h),
.dataout (phy_mem_bank),
.oe (1'b1),
.outclock (phy_ddio_addr_cmd_clk),
.outclocken (1'b1)
);
defparam
ubank_pad.extend_oe_disable = "UNUSED",
ubank_pad.intended_device_family = DEVICE_FAMILY,
ubank_pad.invert_output = "OFF",
ubank_pad.lpm_hint = "UNUSED",
ubank_pad.lpm_type = "altddio_out",
ubank_pad.oe_reg = "UNUSED",
ubank_pad.power_up_high = "OFF",
ubank_pad.width = MEM_BANK_WIDTH;
assign cs_n_l = phy_ddio_cs_n_l;
assign cs_n_h = phy_ddio_cs_n_h;
altddio_out ucs_n_pad(
.aclr (1'b0),
.aset (~reset_n),
.datain_h (cs_n_l),
.datain_l (cs_n_h),
.dataout (phy_mem_cs_n),
.oe (1'b1),
.outclock (phy_ddio_addr_cmd_clk),
.outclocken (1'b1)
);
defparam
ucs_n_pad.extend_oe_disable = "UNUSED",
ucs_n_pad.intended_device_family = DEVICE_FAMILY,
ucs_n_pad.invert_output = "OFF",
ucs_n_pad.lpm_hint = "UNUSED",
ucs_n_pad.lpm_type = "altddio_out",
ucs_n_pad.oe_reg = "UNUSED",
ucs_n_pad.power_up_high = "OFF",
ucs_n_pad.width = MEM_CHIP_SELECT_WIDTH;
assign cke_l = phy_ddio_cke_l;
assign cke_h = phy_ddio_cke_h;
altddio_out ucke_pad(
.aclr (~reset_n),
.aset (1'b0),
.datain_h (cke_l),
.datain_l (cke_h),
.dataout (phy_mem_cke),
.oe (1'b1),
.outclock (phy_ddio_addr_cmd_clk),
.outclocken (1'b1)
);
defparam
ucke_pad.extend_oe_disable = "UNUSED",
ucke_pad.intended_device_family = DEVICE_FAMILY,
ucke_pad.invert_output = "OFF",
ucke_pad.lpm_hint = "UNUSED",
ucke_pad.lpm_type = "altddio_out",
ucke_pad.oe_reg = "UNUSED",
ucke_pad.power_up_high = "OFF",
ucke_pad.width = MEM_CLK_EN_WIDTH;
altddio_out uodt_pad(
.aclr (~reset_n),
.aset (1'b0),
.datain_h (phy_ddio_odt_l),
.datain_l (phy_ddio_odt_h),
.dataout (phy_mem_odt),
.oe (1'b1),
.outclock (phy_ddio_addr_cmd_clk),
.outclocken (1'b1)
);
defparam
uodt_pad.extend_oe_disable = "UNUSED",
uodt_pad.intended_device_family = DEVICE_FAMILY,
uodt_pad.invert_output = "OFF",
uodt_pad.lpm_hint = "UNUSED",
uodt_pad.lpm_type = "altddio_out",
uodt_pad.oe_reg = "UNUSED",
uodt_pad.power_up_high = "OFF",
uodt_pad.width = MEM_ODT_WIDTH;
altddio_out uwe_n_pad(
.aclr (1'b0),
.aset (~reset_n),
.datain_h (phy_ddio_we_n_l),
.datain_l (phy_ddio_we_n_h),
.dataout (phy_mem_we_n),
.oe (1'b1),
.outclock (phy_ddio_addr_cmd_clk),
.outclocken (1'b1)
);
defparam
uwe_n_pad.extend_oe_disable = "UNUSED",
uwe_n_pad.intended_device_family = DEVICE_FAMILY,
uwe_n_pad.invert_output = "OFF",
uwe_n_pad.lpm_hint = "UNUSED",
uwe_n_pad.lpm_type = "altddio_out",
uwe_n_pad.oe_reg = "UNUSED",
uwe_n_pad.power_up_high = "OFF",
uwe_n_pad.width = MEM_CONTROL_WIDTH;
altddio_out uras_n_pad(
.aclr (1'b0),
.aset (~reset_n),
.datain_h (phy_ddio_ras_n_l),
.datain_l (phy_ddio_ras_n_h),
.dataout (phy_mem_ras_n),
.oe (1'b1),
.outclock (phy_ddio_addr_cmd_clk),
.outclocken (1'b1)
);
defparam
uras_n_pad.extend_oe_disable = "UNUSED",
uras_n_pad.intended_device_family = DEVICE_FAMILY,
uras_n_pad.invert_output = "OFF",
uras_n_pad.lpm_hint = "UNUSED",
uras_n_pad.lpm_type = "altddio_out",
uras_n_pad.oe_reg = "UNUSED",
uras_n_pad.power_up_high = "OFF",
uras_n_pad.width = MEM_CONTROL_WIDTH;
altddio_out ucas_n_pad(
.aclr (1'b0),
.aset (~reset_n),
.datain_h (phy_ddio_cas_n_l),
.datain_l (phy_ddio_cas_n_h),
.dataout (phy_mem_cas_n),
.oe (1'b1),
.outclock (phy_ddio_addr_cmd_clk),
.outclocken (1'b1)
);
defparam
ucas_n_pad.extend_oe_disable = "UNUSED",
ucas_n_pad.intended_device_family = DEVICE_FAMILY,
ucas_n_pad.invert_output = "OFF",
ucas_n_pad.lpm_hint = "UNUSED",
ucas_n_pad.lpm_type = "altddio_out",
ucas_n_pad.oe_reg = "UNUSED",
ucas_n_pad.power_up_high = "OFF",
ucas_n_pad.width = MEM_CONTROL_WIDTH;
wire [MEM_CK_WIDTH-1:0] mem_ck_source;
wire [MEM_CK_WIDTH-1:0] mem_ck;
localparam USE_ADDR_CMD_CPS_FOR_MEM_CK = "true";
generate
genvar clock_width;
for (clock_width=0; clock_width<MEM_CK_WIDTH; clock_width=clock_width+1)
begin: clock_gen
if(USE_ADDR_CMD_CPS_FOR_MEM_CK == "true")
begin
nios_mem_if_ddr2_emif_0_p0_acv_ldc # (
.DLL_DELAY_CTRL_WIDTH(DLL_WIDTH),
.ADC_PHASE_SETTING(0),
.ADC_INVERT_PHASE("false"),
.IS_HHP_HPS(IS_HHP_HPS)
) acv_ck_ldc (
.pll_hr_clk(pll_afi_phy_clk),
.pll_dq_clk(pll_write_clk),
.pll_dqs_clk (pll_mem_phy_clk),
.dll_phy_delayctrl (dll_delayctrl_in),
.adc_clk_cps (mem_ck_source[clock_width])
);
end
else
begin
wire [3:0] phy_clk_in;
wire [3:0] phy_clk_out;
assign phy_clk_in = {pll_afi_phy_clk,pll_write_clk,pll_mem_phy_clk,1'b0};
cyclonev_phy_clkbuf phy_clkbuf (
.inclk (phy_clk_in),
.outclk (phy_clk_out)
);
wire [3:0] leveled_dqs_clocks;
cyclonev_leveling_delay_chain leveling_delay_chain_dqs (
.clkin (phy_clk_out[1]),
.delayctrlin (dll_delayctrl_in),
.clkout(leveled_dqs_clocks)
);
defparam leveling_delay_chain_dqs.physical_clock_source = "DQS";
cyclonev_clk_phase_select clk_phase_select_dqs (
`ifndef SIMGEN
.clkin(leveled_dqs_clocks[0]),
`else
.clkin(leveled_dqs_clocks),
`endif
.clkout(mem_ck_source[clock_width])
);
defparam clk_phase_select_dqs.physical_clock_source = "DQS";
defparam clk_phase_select_dqs.use_phasectrlin = "false";
defparam clk_phase_select_dqs.phase_setting = 0;
end
altddio_out umem_ck_pad(
.aclr (1'b0),
.aset (1'b0),
.datain_h (enable_mem_clk[clock_width]),
.datain_l (1'b0),
.dataout (mem_ck[clock_width]),
.oe (1'b1),
.outclock (mem_ck_source[clock_width]),
.outclocken (1'b1)
);
defparam
umem_ck_pad.extend_oe_disable = "UNUSED",
umem_ck_pad.intended_device_family = DEVICE_FAMILY,
umem_ck_pad.invert_output = "OFF",
umem_ck_pad.lpm_hint = "UNUSED",
umem_ck_pad.lpm_type = "altddio_out",
umem_ck_pad.oe_reg = "UNUSED",
umem_ck_pad.power_up_high = "OFF",
umem_ck_pad.width = 1;
wire mem_ck_temp;
assign mem_ck_temp = mem_ck[clock_width];
nios_mem_if_ddr2_emif_0_p0_clock_pair_generator uclk_generator(
.datain (mem_ck_temp),
.dataout (phy_mem_ck[clock_width]),
.dataout_b (phy_mem_ck_n[clock_width])
);
end
endgenerate
endmodule
|
module reconf_fifo (
data,
rdclk,
rdreq,
wrclk,
wrreq,
q,
rdempty,
wrfull);
input [7:0] data;
input rdclk;
input rdreq;
input wrclk;
input wrreq;
output [7:0] q;
output rdempty;
output wrfull;
wire [7:0] sub_wire0;
wire sub_wire1;
wire sub_wire2;
wire [7:0] q = sub_wire0[7:0];
wire rdempty = sub_wire1;
wire wrfull = sub_wire2;
dcfifo dcfifo_component (
.data (data),
.rdclk (rdclk),
.rdreq (rdreq),
.wrclk (wrclk),
.wrreq (wrreq),
.q (sub_wire0),
.rdempty (sub_wire1),
.wrfull (sub_wire2),
.aclr (),
.eccstatus (),
.rdfull (),
.rdusedw (),
.wrempty (),
.wrusedw ());
defparam
dcfifo_component.intended_device_family = "Cyclone 10 LP",
dcfifo_component.lpm_numwords = 4,
dcfifo_component.lpm_showahead = "OFF",
dcfifo_component.lpm_type = "dcfifo",
dcfifo_component.lpm_width = 8,
dcfifo_component.lpm_widthu = 2,
dcfifo_component.overflow_checking = "ON",
dcfifo_component.rdsync_delaypipe = 5,
dcfifo_component.underflow_checking = "ON",
dcfifo_component.use_eab = "OFF",
dcfifo_component.wrsync_delaypipe = 5;
endmodule
|
module MAX6682_SPI_FSM (
input Reset_n_i,
input Clk_i,
input SPI_FSM_Start,
input SPI_Transmission_i,
output reg MAX6682CS_n_o,
output reg SPI_Write_o,
output reg SPI_ReadNext_o,
output reg SPI_FSM_Done,
input [7:0] SPI_Data_i,
output reg [7:0] Byte0,
output reg [7:0] Byte1
);
localparam stIdleSPI = 3'b000;
localparam stWrite1 = 3'b001;
localparam stWrite2 = 3'b010;
localparam stWait = 3'b011;
localparam stRead1 = 3'b100;
localparam stRead2 = 3'b101;
localparam stPause = 3'b110;
reg [2:0] SPI_FSM_State;
reg [2:0] SPI_FSM_NextState;
reg SPI_FSM_Wr1;
reg SPI_FSM_Wr0;
/////////////////////////////////////////////////////////////////////////////
// SPI FSM //////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
always @(negedge Reset_n_i or posedge Clk_i)
begin
if (!Reset_n_i)
begin
SPI_FSM_State <= stIdleSPI;
end
else
begin // rising clock edge
SPI_FSM_State <= SPI_FSM_NextState;
end
end
// Note: There is a possible infinite zero-delay loop between this always-
// block and that of the SensorFSM with SPI_FSM_Start and SPI_FSM_Done.
// Previously (and in the VHDL code) SPI_FSM_Done is set '1' as default
// value and then set to '0' in nearly each case below, e.g. in stIdleSPI.
// In the simulation, this changes the value of that signal each time this
// always-block is executed, which then triggers the below always-block too.
// Therefore this code was changed to set the default value '0' and only set
// the signal '1' in stRead2 and stPause.
always @(SPI_FSM_State, SPI_FSM_Start, SPI_Transmission_i)
begin // process SPI_FSM_CombProc
SPI_FSM_NextState = SPI_FSM_State;
// control signal default values
MAX6682CS_n_o = 1'b1;
SPI_Write_o = 1'b0;
SPI_ReadNext_o = 1'b0;
SPI_FSM_Wr1 = 1'b0;
SPI_FSM_Wr0 = 1'b0;
SPI_FSM_Done = 1'b0;
// next state and output logic
case (SPI_FSM_State)
stIdleSPI: begin
if (SPI_FSM_Start == 1'b1)
begin
SPI_FSM_NextState = stWrite1;
MAX6682CS_n_o = 1'b0;
SPI_Write_o = 1'b1;
end
end
stWrite1: begin
SPI_FSM_NextState = stWrite2;
MAX6682CS_n_o = 1'b0;
SPI_Write_o = 1'b1;
end
stWrite2: begin
SPI_FSM_NextState = stWait;
MAX6682CS_n_o = 1'b0;
end
stWait: begin
MAX6682CS_n_o = 1'b0;
// wait until SPI transmission has finished
if (SPI_Transmission_i == 1'b0) begin
SPI_FSM_NextState = stRead1;
SPI_ReadNext_o = 1'b1;
SPI_FSM_Wr1 = 1'b1;
end
end
stRead1: begin
SPI_FSM_NextState = stRead2;
MAX6682CS_n_o = 1'b0;
SPI_ReadNext_o = 1'b1;
SPI_FSM_Wr0 = 1'b1;
end
stRead2: begin
SPI_FSM_NextState = stPause;
SPI_FSM_Done = 1'b1;
end
stPause: begin
SPI_FSM_NextState = stIdleSPI;
SPI_FSM_Done = 1'b1;
end
default: begin
end
endcase
end
/////////////////////////////////////////////////////////////////////////////
// Byte-wide Memory /////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
always @(negedge Reset_n_i or posedge Clk_i)
begin
if (!Reset_n_i)
begin
Byte0 <= 8'd0;
Byte1 <= 8'd0;
end
else
begin
if (SPI_FSM_Wr0)
begin
Byte0 <= SPI_Data_i;
end
if (SPI_FSM_Wr1)
begin
Byte1 <= SPI_Data_i;
end
end
end
endmodule
|
module MAX6682 (
(* intersynth_port="Reset_n_i" *)
input Reset_n_i,
(* intersynth_port="Clk_i" *)
input Clk_i,
(* intersynth_port="ReconfModuleIn_s", intersynth_conntype="Bit" *)
input Enable_i,
(* intersynth_port="ReconfModuleIRQs_s", intersynth_conntype="Bit" *)
output reg CpuIntr_o,
(* intersynth_port="Outputs_o", intersynth_conntype="Bit" *)
output MAX6682CS_n_o,
(* intersynth_port="SPI_DataOut", intersynth_conntype="Byte" *)
input[7:0] SPI_Data_i,
(* intersynth_port="SPI_Write", intersynth_conntype="Bit" *)
output SPI_Write_o,
(* intersynth_port="SPI_ReadNext", intersynth_conntype="Bit" *)
output SPI_ReadNext_o,
(* intersynth_port="SPI_DataIn", intersynth_conntype="Byte" *)
output [7:0] SPI_Data_o,
(* intersynth_port="SPI_FIFOFull", intersynth_conntype="Bit" *)
input SPI_FIFOFull_i,
(* intersynth_port="SPI_FIFOEmpty", intersynth_conntype="Bit" *)
input SPI_FIFOEmpty_i,
(* intersynth_port="SPI_Transmission", intersynth_conntype="Bit" *)
input SPI_Transmission_i,
(* intersynth_param="PeriodCounterPresetH_i", intersynth_conntype="Word" *)
input[15:0] PeriodCounterPresetH_i,
(* intersynth_param="PeriodCounterPresetL_i", intersynth_conntype="Word" *)
input[15:0] PeriodCounterPresetL_i,
(* intersynth_param="SensorValue_o", intersynth_conntype="Word" *)
output[15:0] SensorValue_o,
(* intersynth_param="Threshold_i", intersynth_conntype="Word" *)
input[15:0] Threshold_i,
(* intersynth_port="SPI_CPOL", intersynth_conntype="Bit" *)
output SPI_CPOL_o,
(* intersynth_port="SPI_CPHA", intersynth_conntype="Bit" *)
output SPI_CPHA_o,
(* intersynth_port="SPI_LSBFE", intersynth_conntype="Bit" *)
output SPI_LSBFE_o
);
/* constant value for dynamic signal */
assign SPI_CPOL_o = 1'b0;
/* constant value for dynamic signal */
assign SPI_CPHA_o = 1'b0;
/* constant value for dynamic signal */
assign SPI_LSBFE_o = 1'b0;
assign SPI_Data_o = 8'b00000000;
reg SPI_FSM_Start;
wire SPI_FSM_Done;
wire [7:0] Byte0;
wire [7:0] Byte1;
MAX6682_SPI_FSM MAX6682_SPI_FSM_1 (
.Reset_n_i (Reset_n_i),
.Clk_i (Clk_i),
.SPI_FSM_Start (SPI_FSM_Start),
.SPI_Transmission_i (SPI_Transmission_i),
.MAX6682CS_n_o (MAX6682CS_n_o),
.SPI_Write_o (SPI_Write_o),
.SPI_ReadNext_o (SPI_ReadNext_o),
.SPI_FSM_Done (SPI_FSM_Done),
.SPI_Data_i (SPI_Data_i),
.Byte0 (Byte0),
.Byte1 (Byte1)
);
/////////////////////////////////////////////////////////////////////////////
// SensorFSM ////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Sensor FSM
localparam stDisabled = 2'b00;
localparam stIdle = 2'b01;
localparam stSPI_Xfer = 2'b10;
localparam stNotify = 2'b11;
reg [1:0] SensorFSM_State;
reg [1:0] SensorFSM_NextState;
wire SensorFSM_TimerOvfl;
reg SensorFSM_TimerPreset;
reg SensorFSM_TimerEnable;
wire SensorFSM_DiffTooLarge;
reg SensorFSM_StoreNewValue;
always @(negedge Reset_n_i or posedge Clk_i)
begin
if (!Reset_n_i)
begin
SensorFSM_State <= stDisabled;
end
else
begin // rising clock edge
// state register
SensorFSM_State <= SensorFSM_NextState;
end
end
always @(SensorFSM_State, Enable_i, SensorFSM_TimerOvfl, SPI_FSM_Done, SensorFSM_DiffTooLarge)
begin // process SensorFSM_CombProc
SensorFSM_NextState = SensorFSM_State;
// control signal default values
SensorFSM_TimerPreset = 1'b1;
SensorFSM_TimerEnable = 1'b0;
SPI_FSM_Start = 1'b0;
SensorFSM_StoreNewValue = 1'b0;
CpuIntr_o = 1'b0;
// next state and output logic
case (SensorFSM_State)
stDisabled: begin
if (Enable_i == 1'b1)
begin
SensorFSM_NextState = stIdle;
SensorFSM_TimerPreset = 1'b0;
SensorFSM_TimerEnable = 1'b1; // start timer
end
end
stIdle: begin
SensorFSM_TimerPreset = 1'b0;
SensorFSM_TimerEnable = 1'b1; // timer running
if (Enable_i == 1'b0)
begin
SensorFSM_NextState = stDisabled;
end
else
if (SensorFSM_TimerOvfl == 1'b1)
begin
SensorFSM_NextState = stSPI_Xfer;
SPI_FSM_Start = 1'b1;
end
end
stSPI_Xfer: begin
if (SPI_FSM_Done == 1'b1)
begin
if (SensorFSM_DiffTooLarge == 1'b1)
begin
SensorFSM_NextState = stNotify;
SensorFSM_TimerPreset = 1'b0;
SensorFSM_TimerEnable = 1'b1; // timer running
SensorFSM_StoreNewValue = 1'b1; // store new value
end
else
begin
SensorFSM_NextState = stIdle;
end
end
end
stNotify: begin
SensorFSM_TimerPreset = 1'b1;
SensorFSM_TimerEnable = 1'b0; // preset timer
SensorFSM_NextState = stIdle;
CpuIntr_o = 1'b1; // notify CPU
end
default: begin
end
endcase
end
/////////////////////////////////////////////////////////////////////////////
// Word Arithmetic //////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
reg [31:0] SensorFSM_Timer;
always @(negedge Reset_n_i or posedge Clk_i)
begin
if (!Reset_n_i)
begin
SensorFSM_Timer <= 32'd0;
end
else
begin
if (SensorFSM_TimerPreset)
begin
SensorFSM_Timer <= {PeriodCounterPresetH_i, PeriodCounterPresetL_i};
end
else if (SensorFSM_TimerEnable)
begin
SensorFSM_Timer <= SensorFSM_Timer - 1'd1;
end
end
end
assign SensorFSM_TimerOvfl = (SensorFSM_Timer == 0) ? 1'b1 : 1'b0;
/////////////////////////////////////////////////////////////////////////////
// Word Arithmetic
// interconnecting signals
wire [15:0] SensorValue;
reg [15:0] Word0;
wire [15:0] AbsDiffResult;
assign SensorValue = { 5'b00000, Byte1, Byte0[7:5] };
always @(negedge Reset_n_i or posedge Clk_i)
begin
if (!Reset_n_i)
begin
Word0 <= 16'd0;
end
else
begin
if (SensorFSM_StoreNewValue)
begin
Word0 <= SensorValue;
end
end
end
wire [16:0] DiffAB;
wire [15:0] DiffBA;
assign DiffAB = {1'b0, SensorValue} - {1'b0, Word0};
assign DiffBA = Word0 - SensorValue;
assign AbsDiffResult = DiffAB[16] ? DiffBA : DiffAB[15:0];
assign SensorFSM_DiffTooLarge = (AbsDiffResult > Threshold_i) ? 1'b1 : 1'b0;
assign SensorValue_o = Word0;
endmodule
|
module bsg_mem_2r1w_sync #( parameter `BSG_INV_PARAM(width_p )
, parameter `BSG_INV_PARAM(els_p )
, parameter read_write_same_addr_p = 0
, parameter addr_width_lp = `BSG_SAFE_CLOG2(els_p)
, parameter harden_p = 0
// NOTE: unused
, parameter substitute_2r1w_p = 0
)
( input clk_i
, input reset_i
, input w_v_i
, input [addr_width_lp-1:0] w_addr_i
, input [width_p-1:0] w_data_i
, input r0_v_i
, input [addr_width_lp-1:0] r0_addr_i
, output logic [width_p-1:0] r0_data_o
, input r1_v_i
, input [addr_width_lp-1:0] r1_addr_i
, output logic [width_p-1:0] r1_data_o
);
wire unused = reset_i;
// TODO: Define more hardened macro configs here
`bsg_mem_2r1w_sync_macro(32,64) else
// no hardened version found
begin : notmacro
initial if (substitute_2r1w_p != 0) $warning("substitute_2r1w_p will have no effect");
bsg_mem_2r1w_sync_synth #(.width_p(width_p), .els_p(els_p), .read_write_same_addr_p(read_write_same_addr_p), .harden_p(harden_p))
synth
(.*);
end // block: notmacro
//synopsys translate_off
always_ff @(posedge clk_i)
if (w_v_i)
begin
assert (w_addr_i < els_p)
else $error("Invalid address %x to %m of size %x\n", w_addr_i, els_p);
assert (~(r0_addr_i == w_addr_i && w_v_i && r0_v_i && !read_write_same_addr_p))
else $error("%m: port 0 Attempt to read and write same address");
assert (~(r1_addr_i == w_addr_i && w_v_i && r1_v_i && !read_write_same_addr_p))
else $error("%m: port 1 Attempt to read and write same address");
end
initial
begin
$display("## %L: instantiating width_p=%d, els_p=%d, read_write_same_addr_p=%d, harden_p=%d (%m)",width_p,els_p,read_write_same_addr_p,harden_p);
end
//synopsys translate_on
endmodule
|
module coe_tlb (
// global
clk ,
rst_n ,
// rec
cover_valid_i ,
cover_value_i ,
// pre
pre_start_i ,
pre_type_i ,
pre_sel_i ,
pre_tl_4x4_x_i ,
pre_tl_4x4_y_i ,
pre_size_i ,
pre_idx_i ,
pre_bank_0_o ,
pre_bank_1_o ,
pre_bank_2_o ,
pre_bank_3_o ,
pre_cbank_o ,
// ec
ec_sel_i ,
ec_addr_i ,
ec_bank_o ,
ec_cbank_o
);
//*** PARAMETER DECLARATION ****************************************************
localparam I_4x4 = 2'b00 ,
I_8x8 = 2'b01 ,
I_16x16 = 2'b10 ,
I_32x32 = 2'b11 ;
localparam INTRA = 0 ,
INTER = 1 ;
//*** IN/OUTPUT DECLARATION ****************************************************
// global
input clk ;
input rst_n ;
// rec
input cover_valid_i ;
input cover_value_i ;
// pre
input pre_start_i ;
input pre_type_i ;
input [1 : 0] pre_sel_i ;
input [3 : 0] pre_tl_4x4_x_i ;
input [3 : 0] pre_tl_4x4_y_i ;
input [1 : 0] pre_size_i ;
input [4 : 0] pre_idx_i ;
output reg [1 : 0] pre_bank_0_o ; // wire in fact
output reg [1 : 0] pre_bank_1_o ; // wire in fact
output reg [1 : 0] pre_bank_2_o ; // wire in fact
output reg [1 : 0] pre_bank_3_o ; // wire in fact
output pre_cbank_o ;
// ec
input [1 : 0] ec_sel_i ;
input [8 : 0] ec_addr_i ;
output [1 : 0] ec_bank_o ;
output ec_cbank_o ;
//*** REG/WIRES DECLARATION ****************************************************
//--- Pointer_R ------------------------
reg [255 : 0] pointer_r ;
reg cover_en ;
reg [4 : 0] rec_cnt_r ;
reg rec_cnt_bd_w ;
reg shifter_r ;
wire [127 : 0] rec_mask_pos_w ;
wire [127 : 0] rec_mask_neg_w ;
wire [127 : 0] rec_mask_bank_w ;
wire [7 : 0] rec_8x8_addr_w ;
wire [2 : 0] rec_8x8_x_w ;
wire [2 : 0] rec_8x8_y_w ;
wire [1 : 0] rec_bank_w ;
wire [1 : 0] pointer_fmr_rec_a_w ;
wire [1 : 0] pointer_fmr_rec_b_w ;
//--- Pre_Bank_O -----------------------
wire [127 : 0] pointer_pre_w ;
wire [1 : 0] pointer_cur_pre_w ;
wire [127 : 0] pointer_ec_w ;
wire [1 : 0] pointer_cur_ec_w ;
wire [1 : 0] pre_bank_0_w ;
wire [1 : 0] pre_bank_1_w ;
wire [1 : 0] pre_bank_2_w ;
wire [1 : 0] pre_bank_3_w ;
wire [1 : 0] pointer_fmr_pre_0_a_w ;
wire [1 : 0] pointer_fmr_pre_0_b_w ;
wire [1 : 0] pointer_fmr_pre_1_a_w ;
wire [1 : 0] pointer_fmr_pre_1_b_w ;
wire [1 : 0] pointer_fmr_pre_2_a_w ;
wire [1 : 0] pointer_fmr_pre_2_b_w ;
wire [1 : 0] pointer_fmr_pre_3_a_w ;
wire [1 : 0] pointer_fmr_pre_3_b_w ;
wire [7 : 0] pre_8x8_addr_w ;
wire [2 : 0] pre_8x8_x_w ;
wire [2 : 0] pre_8x8_y_w ;
//--- Ec_Bank_O ------------------------
wire [127 : 0] ec_pointer_w ;
wire [7 : 0] ec_8x8_addr_w ;
wire ec_sel_w ;
//*** MAIN BODY ****************************************************************
//--- Pointer_R ------------------------
// pointer_r
always @(posedge clk or negedge rst_n) begin
if( !rst_n ) begin
pointer_r[255:128] <= {64{2'b00}} ;
pointer_r[127:000] <= {64{2'b01}} ;
end
else if( cover_en ) begin
if( shifter_r )
pointer_r[127:000] <= ( pointer_r[127:000] & rec_mask_neg_w ) | rec_mask_bank_w ;
else begin
pointer_r[255:128] <= ( pointer_r[255:128] & rec_mask_neg_w ) | rec_mask_bank_w ;
end
end
end
// cover_en
always @(posedge clk or negedge rst_n) begin
if( !rst_n )
cover_en <= 'd0 ;
else if( cover_valid_i & cover_value_i )
cover_en <= 'd1 ;
else if( rec_cnt_bd_w ) begin
cover_en <= 'd0 ;
end
end
// rec_cnt
always @(posedge clk or negedge rst_n) begin
if( !rst_n )
rec_cnt_r <= 'd0 ;
else if( cover_en ) begin
if( rec_cnt_bd_w )
rec_cnt_r <= 'd0 ;
else begin
rec_cnt_r <= rec_cnt_r + 'd1 ;
end
end
end
// rec_cnt_bd_w
always @(*) begin
case( pre_size_i )
I_4x4 : rec_cnt_bd_w = (rec_cnt_r=='d01-'d01) ;
I_8x8 : rec_cnt_bd_w = (rec_cnt_r=='d01-'d01) ;
I_16x16 : rec_cnt_bd_w = (rec_cnt_r=='d04-'d01) ;
I_32x32 : rec_cnt_bd_w = (rec_cnt_r=='d16-'d01) ;
endcase
end
// shifter_r
always @(posedge clk or negedge rst_n) begin
if( !rst_n )
shifter_r <= 1'b0 ;
else if( pre_start_i ) begin
shifter_r <= !shifter_r ;
end
end
// rec_mask_pos_w & rec_mask_neg_w
assign rec_mask_pos_w = 2'b11 << (rec_8x8_addr_w<<1) ;
assign rec_mask_neg_w = ~rec_mask_pos_w ;
assign rec_mask_bank_w = rec_bank_w << (rec_8x8_addr_w<<1) ;
// rec_8x8_addr_w
assign rec_8x8_addr_w = { 1'b0 ,1'b0 ,
rec_8x8_y_w[2] ,rec_8x8_x_w[2] ,
rec_8x8_y_w[1] ,rec_8x8_x_w[1] ,
rec_8x8_y_w[0] ,rec_8x8_x_w[0] } + rec_cnt_r ;
// rec_8x8_x_w & rec_8x8_y_w
assign rec_8x8_x_w = pre_tl_4x4_x_i[3:1] ;
assign rec_8x8_y_w = pre_tl_4x4_y_i[3:1] ;
// rec_bank_w
assign rec_bank_w = 2'b11 - pointer_fmr_rec_a_w - pointer_fmr_rec_b_w ;
// pointer_fmr_rec_a_w & pointer_fmr_rec_b_w
assign pointer_fmr_rec_a_w = pointer_r[255:128] >> (rec_8x8_addr_w<<1) ;
assign pointer_fmr_rec_b_w = pointer_r[127:000] >> (rec_8x8_addr_w<<1) ;
//--- Pre_Bank_O -----------------------
// pre_cbank_o
assign pre_cbank_o = shifter_r ;
// pre_bank_o
always @(*) begin
if( pre_sel_i[1] ) begin
pre_bank_0_o = 2'b11 ;
pre_bank_1_o = 2'b11 ;
pre_bank_2_o = 2'b11 ;
pre_bank_3_o = 2'b11 ;
end
else if( pre_type_i==INTER ) begin
pre_bank_0_o = shifter_r ;
pre_bank_1_o = shifter_r ;
pre_bank_2_o = shifter_r ;
pre_bank_3_o = shifter_r ;
end
else begin
case( pre_size_i )
I_4x4,I_8x8 : begin pre_bank_0_o = pre_bank_0_w ;
pre_bank_1_o = pre_bank_0_w ;
pre_bank_2_o = pre_bank_0_w ;
pre_bank_3_o = pre_bank_0_w ;
end
I_16x16 : begin if( pre_8x8_x_w[1] ) begin
if( pre_idx_i[1] ) begin pre_bank_0_o = pre_bank_0_w ;
pre_bank_1_o = pre_bank_1_w ;
pre_bank_2_o = pre_bank_1_w ;
pre_bank_3_o = pre_bank_0_w ;
end
else begin pre_bank_0_o = pre_bank_1_w ;
pre_bank_1_o = pre_bank_0_w ;
pre_bank_2_o = pre_bank_0_w ;
pre_bank_3_o = pre_bank_1_w ;
end
end
else begin
if( pre_idx_i[1] ) begin pre_bank_0_o = pre_bank_1_w ;
pre_bank_1_o = pre_bank_1_w ;
pre_bank_2_o = pre_bank_0_w ;
pre_bank_3_o = pre_bank_0_w ;
end
else begin pre_bank_0_o = pre_bank_0_w ;
pre_bank_1_o = pre_bank_0_w ;
pre_bank_2_o = pre_bank_1_w ;
pre_bank_3_o = pre_bank_1_w ;
end
end
end
I_32x32 : begin case( pre_idx_i[1:0] )
2'd0 : begin pre_bank_0_o = pre_bank_0_w ;
pre_bank_1_o = pre_bank_2_w ;
pre_bank_2_o = pre_bank_1_w ;
pre_bank_3_o = pre_bank_3_w ;
end
2'd1 : begin pre_bank_0_o = pre_bank_3_w ;
pre_bank_1_o = pre_bank_0_w ;
pre_bank_2_o = pre_bank_2_w ;
pre_bank_3_o = pre_bank_1_w ;
end
2'd2 : begin pre_bank_0_o = pre_bank_1_w ;
pre_bank_1_o = pre_bank_3_w ;
pre_bank_2_o = pre_bank_0_w ;
pre_bank_3_o = pre_bank_2_w ;
end
2'd3 : begin pre_bank_0_o = pre_bank_2_w ;
pre_bank_1_o = pre_bank_1_w ;
pre_bank_2_o = pre_bank_3_w ;
pre_bank_3_o = pre_bank_0_w ;
end
endcase
end
endcase
end
end
// pre_bank_w
assign pre_bank_0_w = (pre_sel_i[1]) ? 2'b11 : (2'b11-pointer_fmr_pre_0_a_w-pointer_fmr_pre_0_b_w) ;
assign pre_bank_1_w = (pre_sel_i[1]) ? 2'b11 : (2'b11-pointer_fmr_pre_1_a_w-pointer_fmr_pre_1_b_w) ;
assign pre_bank_2_w = (pre_sel_i[1]) ? 2'b11 : (2'b11-pointer_fmr_pre_2_a_w-pointer_fmr_pre_2_b_w) ;
assign pre_bank_3_w = (pre_sel_i[1]) ? 2'b11 : (2'b11-pointer_fmr_pre_3_a_w-pointer_fmr_pre_3_b_w) ;
// pointer_fmr_pre_0_w & pointer_fmr_pre_1_w
assign pointer_fmr_pre_0_a_w = pointer_r[255:128] >> ((pre_8x8_addr_w+0)<<1) ;
assign pointer_fmr_pre_0_b_w = pointer_r[127:000] >> ((pre_8x8_addr_w+0)<<1) ;
assign pointer_fmr_pre_1_a_w = pointer_r[255:128] >> ((pre_8x8_addr_w+1)<<1) ;
assign pointer_fmr_pre_1_b_w = pointer_r[127:000] >> ((pre_8x8_addr_w+1)<<1) ;
assign pointer_fmr_pre_2_a_w = pointer_r[255:128] >> ((pre_8x8_addr_w+4)<<1) ;
assign pointer_fmr_pre_2_b_w = pointer_r[127:000] >> ((pre_8x8_addr_w+4)<<1) ;
assign pointer_fmr_pre_3_a_w = pointer_r[255:128] >> ((pre_8x8_addr_w+5)<<1) ;
assign pointer_fmr_pre_3_b_w = pointer_r[127:000] >> ((pre_8x8_addr_w+5)<<1) ;
// pre_8x8_addr_w
assign pre_8x8_addr_w = { 1'b0 ,1'b0 ,
pre_8x8_y_w[2] ,pre_8x8_x_w[2] ,
pre_8x8_y_w[1] ,pre_8x8_x_w[1] ,
pre_8x8_y_w[0] ,pre_8x8_x_w[0] };
// pre_8x8_x_w & pre_8x8_y_w
assign pre_8x8_x_w = pre_tl_4x4_x_i[3:1] ;
assign pre_8x8_y_w = pre_tl_4x4_y_i[3:1] + pre_idx_i[4:3] ;
//--- Ec_Bank_O ------------------------
// ec_cbank_o
assign ec_cbank_o = !shifter_r ;
// ec_bank_o
assign ec_bank_o = ec_sel_w ? 2'b11
: ( (pre_type_i==INTER) ? ( !shifter_r )
: ( ec_pointer_w>>(ec_8x8_addr_w<<1) )
);
// ec_pointer_w
assign ec_pointer_w = shifter_r ? pointer_r[255:128] : pointer_r[127:000] ;
// ec_8x8_addr_w
assign ec_8x8_addr_w = {ec_addr_i[6],ec_addr_i[7],ec_addr_i[4],ec_addr_i[5],ec_addr_i[2],ec_addr_i[3],ec_addr_i[0],ec_addr_i[1]}>>2 ;
// ec_sel_w
assign ec_sel_w = ec_sel_i!=2'b00 ;
endmodule
|
module pll_lock_lookup(
input clk,
input [6:0] divider,
output reg [39:0] value
);
(*rom_style = "block" *) reg [39:0] lookup [0:64];
wire [5:0] addr;
initial
begin
lookup[00]=40'b00110_00110_1111101000_1111101001_0000000001;
lookup[01]=40'b00110_00110_1111101000_1111101001_0000000001;
lookup[02]=40'b01000_01000_1111101000_1111101001_0000000001;
lookup[03]=40'b01011_01011_1111101000_1111101001_0000000001;
lookup[04]=40'b01110_01110_1111101000_1111101001_0000000001;
lookup[05]=40'b10001_10001_1111101000_1111101001_0000000001;
lookup[06]=40'b10011_10011_1111101000_1111101001_0000000001;
lookup[07]=40'b10110_10110_1111101000_1111101001_0000000001;
lookup[08]=40'b11001_11001_1111101000_1111101001_0000000001;
lookup[09]=40'b11100_11100_1111101000_1111101001_0000000001;
lookup[10]=40'b11111_11111_1110000100_1111101001_0000000001;
lookup[11]=40'b11111_11111_1100111001_1111101001_0000000001;
lookup[12]=40'b11111_11111_1011101110_1111101001_0000000001;
lookup[13]=40'b11111_11111_1010111100_1111101001_0000000001;
lookup[14]=40'b11111_11111_1010001010_1111101001_0000000001;
lookup[15]=40'b11111_11111_1001110001_1111101001_0000000001;
lookup[16]=40'b11111_11111_1000111111_1111101001_0000000001;
lookup[17]=40'b11111_11111_1000100110_1111101001_0000000001;
lookup[18]=40'b11111_11111_1000001101_1111101001_0000000001;
lookup[19]=40'b11111_11111_0111110100_1111101001_0000000001;
lookup[20]=40'b11111_11111_0111011011_1111101001_0000000001;
lookup[21]=40'b11111_11111_0111000010_1111101001_0000000001;
lookup[22]=40'b11111_11111_0110101001_1111101001_0000000001;
lookup[23]=40'b11111_11111_0110010000_1111101001_0000000001;
lookup[24]=40'b11111_11111_0110010000_1111101001_0000000001;
lookup[25]=40'b11111_11111_0101110111_1111101001_0000000001;
lookup[26]=40'b11111_11111_0101011110_1111101001_0000000001;
lookup[27]=40'b11111_11111_0101011110_1111101001_0000000001;
lookup[28]=40'b11111_11111_0101000101_1111101001_0000000001;
lookup[29]=40'b11111_11111_0101000101_1111101001_0000000001;
lookup[30]=40'b11111_11111_0100101100_1111101001_0000000001;
lookup[31]=40'b11111_11111_0100101100_1111101001_0000000001;
lookup[32]=40'b11111_11111_0100101100_1111101001_0000000001;
lookup[33]=40'b11111_11111_0100010011_1111101001_0000000001;
lookup[34]=40'b11111_11111_0100010011_1111101001_0000000001;
lookup[35]=40'b11111_11111_0100010011_1111101001_0000000001;
lookup[36]=40'b11111_11111_0011111010_1111101001_0000000001;
lookup[37]=40'b11111_11111_0011111010_1111101001_0000000001;
lookup[38]=40'b11111_11111_0011111010_1111101001_0000000001;
lookup[39]=40'b11111_11111_0011111010_1111101001_0000000001;
lookup[40]=40'b11111_11111_0011111010_1111101001_0000000001;
lookup[41]=40'b11111_11111_0011111010_1111101001_0000000001;
lookup[42]=40'b11111_11111_0011111010_1111101001_0000000001;
lookup[43]=40'b11111_11111_0011111010_1111101001_0000000001;
lookup[44]=40'b11111_11111_0011111010_1111101001_0000000001;
lookup[45]=40'b11111_11111_0011111010_1111101001_0000000001;
lookup[46]=40'b11111_11111_0011111010_1111101001_0000000001;
lookup[47]=40'b11111_11111_0011111010_1111101001_0000000001;
lookup[48]=40'b11111_11111_0011111010_1111101001_0000000001;
lookup[49]=40'b11111_11111_0011111010_1111101001_0000000001;
lookup[50]=40'b11111_11111_0011111010_1111101001_0000000001;
lookup[51]=40'b11111_11111_0011111010_1111101001_0000000001;
lookup[52]=40'b11111_11111_0011111010_1111101001_0000000001;
lookup[53]=40'b11111_11111_0011111010_1111101001_0000000001;
lookup[54]=40'b11111_11111_0011111010_1111101001_0000000001;
lookup[55]=40'b11111_11111_0011111010_1111101001_0000000001;
lookup[56]=40'b11111_11111_0011111010_1111101001_0000000001;
lookup[57]=40'b11111_11111_0011111010_1111101001_0000000001;
lookup[58]=40'b11111_11111_0011111010_1111101001_0000000001;
lookup[59]=40'b11111_11111_0011111010_1111101001_0000000001;
lookup[60]=40'b11111_11111_0011111010_1111101001_0000000001;
lookup[6]=40'b11111_11111_0011111010_1111101001_0000000001;
lookup[00]=40'b11111_11111_0011111010_1111101001_0000000001;
lookup[00]=40'b11111_11111_0011111010_1111101001_0000000001;
end
assign addr = divider - 1;
always @(posedge clk)
begin
value = lookup[addr];
end
endmodule
|
module sky130_fd_sc_ms__clkdlyinv3sd2 (
Y ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
|
module header
// Internal signals
//
// Generated Signal List
//
wire clk_a; // __W_PORT_SIGNAL_MAP_REQ
wire res_a_n; // __W_PORT_SIGNAL_MAP_REQ
wire tie0_1;
wire u11_sync_generic_i_int_upd_w_p;
wire u12_sync_generic_i_int_upd_w_arm_p;
wire u3_sync_generic_i_trans_start_p;
wire u4_sync_rst_i_int_rst_n;
wire upd_w; // __W_PORT_SIGNAL_MAP_REQ
wire upd_w_en; // __W_PORT_SIGNAL_MAP_REQ
//
// End of Generated Signal List
//
// %COMPILER_OPTS%
//
// Generated Signal Assignments
//
assign clk_a = clk_a_i; // __I_I_BIT_PORT
assign res_a_n = res_a_n_i; // __I_I_BIT_PORT
assign tie0_1 = `tie0_1_c;
assign upd_w = upd_w_i; // __I_I_BIT_PORT
assign upd_w_en = upd_w_en_i; // __I_I_BIT_PORT
/* ------------------------------------------------------------
Generator information:
used package Micronas::Reg is version 1.88
this package RegViews.pm is version 1.93
use with RTL libraries (this release or higher):
ip_ocp/0002/ip_ocp_016_21Jan2009
ip_sync/0001/ip_sync_006_23jan2008
------------------------------------------------------------ */
/*
local definitions
*/
`define REG_00_OFFS 0 // reg_0x0
`define REG_04_OFFS 1 // reg_0x4
`define REG_08_OFFS 2 // reg_0x8
`define REG_0C_OFFS 3 // reg_0xC
`define REG_10_OFFS 4 // reg_0x10
`define REG_14_OFFS 5 // reg_0x14
`define REG_18_OFFS 6 // reg_0x18
`define REG_1C_OFFS 7 // reg_0x1C
`define REG_20_OFFS 8 // reg_0x20
`define REG_28_OFFS 10 // reg_0x28
/*
local wire or register declarations
*/
reg [31:0] REG_00;
reg [31:0] REG_04;
reg [31:0] REG_08;
reg [31:0] REG_0C;
reg [31:0] REG_10;
reg [31:0] REG_14;
reg [31:0] REG_18;
reg [31:0] REG_1C;
reg [31:0] REG_20;
wire [3:0] sha_w_test_shdw;
reg [31:0] REG_28;
reg int_upd_w;
reg int_upd_w_en;
wire wr_p;
wire wr_done_p;
wire rd_p;
wire rd_done_p;
wire [3:0] iaddr;
wire addr_overshoot;
wire trans_done_p;
reg ts_del_p;
reg int_trans_done;
reg fwd_txn;
wire [0:0] fwd_decode_vec;
wire fwd_rd_done_p;
wire fwd_wr_done_p;
reg [31:0] mux_rd_data;
reg mux_rd_err;
/*
local wire and output assignments
*/
assign dgatel_par_o[3:0] = cond_slice(P__DGATEL, REG_00[3:0]);
assign dgates_par_o[4:0] = cond_slice(P__DGATES, REG_00[8:4]);
assign dummy_fe_par_o[2:0] = cond_slice(P__DUMMY_FE, REG_00[11:9]);
assign sha_w_test_shdw[3:0] = cond_slice(P__SHA_W_TEST, REG_20[23:20]);
assign w_test_par_o[3:0] = cond_slice(P__W_TEST, REG_20[19:16]);
assign sha_w_test_trg_p_o = int_upd_w;
assign usr_w_test_par_o[3:0] = wr_data_i[3:0];
// clip address to decoded range
assign iaddr = addr_i[5:2];
assign addr_overshoot = |addr_i[13:6];
/*
generate transaction-handling signals
*/
assign trans_done_p = rd_done_p | wr_done_p;
// write txn start pulse
assign
// synopsys translate_off
#0.1
// synopsys translate_on
wr_p = ~rd_wr_i & u3_sync_generic_i_trans_start_p;
// read done pulse
assign rd_done_p = rd_p;
assign fwd_rd_done_p = 0;
assign fwd_wr_done_p = usr_w_test_trans_done_p_i;
assign rd_p = rd_wr_i & ((ts_del_p & ~fwd_txn) | (fwd_rd_done_p & fwd_txn)); // read txn start pulse
assign wr_done_p = ~rd_wr_i & ((ts_del_p & ~fwd_txn) | (fwd_wr_done_p & fwd_txn)); // write done pulse
always @(posedge clk_a_i or negedge u4_sync_rst_i_int_rst_n) begin
if (~u4_sync_rst_i_int_rst_n) begin
int_trans_done <= 0;
ts_del_p <= 0;
end
else begin
ts_del_p <= u3_sync_generic_i_trans_start_p;
if (trans_done_p)
int_trans_done <= ~int_trans_done;
end
end
assign trans_done_o = int_trans_done;
/*
helper function for conditional FFs
*/
// msd parse off
function [31:0] cond_slice(input integer enable, input [31:0] vec);
begin
cond_slice = (enable < 0) ? vec : enable;
end
endfunction
// msd parse on
/*
write process
*/
always @(posedge clk_a_i or negedge u4_sync_rst_i_int_rst_n) begin
if (~u4_sync_rst_i_int_rst_n) begin
REG_00[11:9] <= 'h0;
REG_00[3:0] <= 'h4;
REG_00[8:4] <= 'hc;
REG_20[19:16] <= 'h0;
REG_20[23:20] <= 'h0;
end
else begin
if (wr_p)
case (iaddr)
`REG_00_OFFS: begin
REG_00[11:9] <= wr_data_i[11:9];
REG_00[3:0] <= wr_data_i[3:0];
REG_00[8:4] <= wr_data_i[8:4];
end
`REG_20_OFFS: begin
REG_20[19:16] <= wr_data_i[19:16];
REG_20[23:20] <= wr_data_i[23:20];
end
default: ;
endcase
end
end
/*
txn forwarding process
*/
// decode addresses of USR registers and read/write
assign fwd_decode_vec = {(iaddr == `REG_20_OFFS) & ~rd_wr_i};
always @(posedge clk_a_i or negedge u4_sync_rst_i_int_rst_n) begin
if (~u4_sync_rst_i_int_rst_n) begin
fwd_txn <= 0;
usr_w_test_wr_p_o <= 0;
end
else begin
usr_w_test_wr_p_o <= 0;
if (u3_sync_generic_i_trans_start_p) begin
fwd_txn <= |fwd_decode_vec; // set flag for forwarded txn
usr_w_test_wr_p_o <= fwd_decode_vec[0] & ~rd_wr_i;
end
else if (trans_done_p)
fwd_txn <= 0; // reset flag for forwarded transaction
end
end
/*
shadowing for update signal 'upd_w'
*/
// generate internal update signal
always @(posedge clk_a_i or negedge u4_sync_rst_i_int_rst_n) begin
if (~u4_sync_rst_i_int_rst_n) begin
int_upd_w <= 1;
int_upd_w_en <= 0;
end
else begin
int_upd_w <= (u11_sync_generic_i_int_upd_w_p & int_upd_w_en) | upd_w_force_i;
if (u12_sync_generic_i_int_upd_w_arm_p)
int_upd_w_en <= 1; // arm enable signal
else if(u11_sync_generic_i_int_upd_w_p)
int_upd_w_en <= 0; // reset enable signal after update-event
end
end
// shadow process
always @(posedge clk_a_i or negedge u4_sync_rst_i_int_rst_n) begin
if (~u4_sync_rst_i_int_rst_n) begin
sha_w_test_par_o <= 'h0;
end
else begin
if (int_upd_w) begin
sha_w_test_par_o <= sha_w_test_shdw;
end
end
end
/*
read logic and mux process
*/
assign rd_data_o = mux_rd_data;
assign rd_err_o = mux_rd_err | addr_overshoot;
always @( REG_00 or iaddr or r_test_par_i) begin
mux_rd_err <= 0;
mux_rd_data <= 0;
case (iaddr)
`REG_00_OFFS : begin
mux_rd_data[3:0] <= cond_slice(P__DGATEL, REG_00[3:0]);
mux_rd_data[8:4] <= cond_slice(P__DGATES, REG_00[8:4]);
mux_rd_data[11:9] <= cond_slice(P__DUMMY_FE, REG_00[11:9]);
end
`REG_28_OFFS : begin
mux_rd_data[2:0] <= r_test_par_i;
end
default: begin
mux_rd_err <= 1; // no decode
end
endcase
end
// generate read-notify trigger (combinatorial)
always @(*) begin
r_test_trg_p_o = 0;
case (iaddr)
`REG_28_OFFS: begin
r_test_trg_p_o = rd_p;
end
default: begin
r_test_trg_p_o = 0;
end
endcase
end
/*
checking code
*/
`ifdef ASSERT_ON
// msd parse off
property p_pos_pulse_check (sig); // check for positive pulse
@(posedge clk_a_i) disable iff (~u4_sync_rst_i_int_rst_n)
sig |=> ~sig;
endproperty
assert_usr_w_test_trans_done_p_i_is_a_pulse: assert property(p_pos_pulse_check(usr_w_test_trans_done_p_i));
// all acks for forwarded txns
wire [0:0] fwd_done_vec;
assign fwd_done_vec = {usr_w_test_trans_done_p_i};
assert_fwd_done_onehot: assert property
(
@(posedge clk_a_i) disable iff (~u4_sync_rst_i_int_rst_n)
fwd_done_vec != 0 |-> onehot(fwd_done_vec)
);
assert_fwd_done_only_when_fwd_txn: assert property
(
@(posedge clk_a_i) disable iff (~u4_sync_rst_i_int_rst_n)
fwd_done_vec != 0 |-> fwd_txn
);
function onehot (input [0:0] vec);
integer i,j;
begin
j = 0;
for (i=0; i<1; i=i+1) j = j + vec[i] ? 1 : 0;
onehot = (j==1) ? 1 : 0;
end
endfunction
// msd parse on
`endif
//
// Generated Instances and Port Mappings
//
// Generated Instance Port Map for u11_sync_generic_i
sync_generic #(
.act(1),
.kind(3),
.rstact(0),
.rstval(0),
.sync(1)
) u11_sync_generic_i ( // Synchronizer for update-signal upd_w
.clk_r(clk_a),
.clk_s(tie0_1),
.rcv_o(u11_sync_generic_i_int_upd_w_p),
.rst_r(res_a_n),
.rst_s(tie0_1),
.snd_i(upd_w)
);
// End of Generated Instance Port Map for u11_sync_generic_i
// Generated Instance Port Map for u12_sync_generic_i
sync_generic #(
.act(1),
.kind(3),
.rstact(0),
.rstval(0),
.sync(1)
) u12_sync_generic_i ( // Synchronizer for update-enable signal upd_w_en
.clk_r(clk_a),
.clk_s(tie0_1),
.rcv_o(u12_sync_generic_i_int_upd_w_arm_p),
.rst_r(res_a_n),
.rst_s(tie0_1),
.snd_i(upd_w_en)
);
// End of Generated Instance Port Map for u12_sync_generic_i
// Generated Instance Port Map for u3_sync_generic_i
sync_generic #(
.act(1),
.kind(2),
.rstact(0),
.rstval(0),
.sync(sync)
) u3_sync_generic_i ( // Synchronizer for trans_start signal
.clk_r(clk_a),
.clk_s(tie0_1),
.rcv_o(u3_sync_generic_i_trans_start_p),
.rst_r(res_a_n),
.rst_s(tie0_1),
.snd_i(trans_start_0_i) // __I_USE_PORT trans_start_0_i for signal trans_start_0
);
// End of Generated Instance Port Map for u3_sync_generic_i
// Generated Instance Port Map for u4_sync_rst_i
sync_rst #(
.act(0),
.sync(0)
) u4_sync_rst_i ( // Reset synchronizer (in bypass-mode)
.clk_r(clk_a),
.rst_i(res_a_n),
.rst_o(u4_sync_rst_i_int_rst_n),
.test_i(tie0_1)
);
// End of Generated Instance Port Map for u4_sync_rst_i
endmodule
|
module rxc_engine_classic
#(parameter C_VENDOR = "ALTERA",
parameter C_PCI_DATA_WIDTH = 128,
parameter C_RX_PIPELINE_DEPTH = 10
)
(
// Interface: Clocks
input CLK,
// Interface: Resets
input RST_IN,
// Interface: RX Classic
input [C_PCI_DATA_WIDTH-1:0] RX_TLP,
input RX_TLP_VALID,
input RX_TLP_START_FLAG,
input [`SIG_OFFSET_W-1:0] RX_TLP_START_OFFSET,
input RX_TLP_END_FLAG,
input [`SIG_OFFSET_W-1:0] RX_TLP_END_OFFSET,
input [`SIG_BARDECODE_W-1:0] RX_TLP_BAR_DECODE,
// Interface: RXC Engine
output [C_PCI_DATA_WIDTH-1:0] RXC_DATA,
output RXC_DATA_VALID,
output [(C_PCI_DATA_WIDTH/32)-1:0] RXC_DATA_WORD_ENABLE,
output RXC_DATA_START_FLAG,
output [clog2s(C_PCI_DATA_WIDTH/32)-1:0] RXC_DATA_START_OFFSET,
output RXC_DATA_END_FLAG,
output [clog2s(C_PCI_DATA_WIDTH/32)-1:0] RXC_DATA_END_OFFSET,
output [`SIG_LBE_W-1:0] RXC_META_LDWBE,
output [`SIG_FBE_W-1:0] RXC_META_FDWBE,
output [`SIG_TAG_W-1:0] RXC_META_TAG,
output [`SIG_LOWADDR_W-1:0] RXC_META_ADDR,
output [`SIG_TYPE_W-1:0] RXC_META_TYPE,
output [`SIG_LEN_W-1:0] RXC_META_LENGTH,
output [`SIG_BYTECNT_W-1:0] RXC_META_BYTES_REMAINING,
output [`SIG_CPLID_W-1:0] RXC_META_COMPLETER_ID,
output RXC_META_EP,
// Interface: RX Shift Register
input [(C_RX_PIPELINE_DEPTH+1)*C_PCI_DATA_WIDTH-1:0] RX_SR_DATA,
input [C_RX_PIPELINE_DEPTH:0] RX_SR_EOP,
input [(C_RX_PIPELINE_DEPTH+1)*`SIG_OFFSET_W-1:0] RX_SR_END_OFFSET,
input [C_RX_PIPELINE_DEPTH:0] RX_SR_SOP,
input [C_RX_PIPELINE_DEPTH:0] RX_SR_VALID
);
`include "functions.vh"
/*AUTOWIRE*/
/*AUTOINPUT*/
///*AUTOOUTPUT*/
// End of automatics
localparam C_RX_BE_W = (`SIG_FBE_W+`SIG_LBE_W);
localparam C_RX_INPUT_STAGES = 1;
localparam C_RX_OUTPUT_STAGES = 1; // Must always be at least one
localparam C_RX_COMPUTATION_STAGES = 1;
localparam C_RX_DATA_STAGES = C_RX_COMPUTATION_STAGES;
localparam C_RX_META_STAGES = C_RX_DATA_STAGES - 1;
localparam C_TOTAL_STAGES = C_RX_COMPUTATION_STAGES + C_RX_OUTPUT_STAGES + C_RX_INPUT_STAGES;
// Cycle index in the SOP register when enable is raised
// Computation can begin when the last DW of the header is recieved.
localparam C_RX_COMPUTATION_CYCLE = C_RX_COMPUTATION_STAGES + (`TLP_CPLMETADW2_I/C_PCI_DATA_WIDTH);
// The computation cycle must be at least one cycle before the address is enabled
localparam C_RX_DATA_CYCLE = C_RX_COMPUTATION_CYCLE;
localparam C_RX_METADW0_CYCLE = (`TLP_CPLMETADW0_I/C_PCI_DATA_WIDTH) + C_RX_INPUT_STAGES;
localparam C_RX_METADW1_CYCLE = (`TLP_CPLMETADW1_I/C_PCI_DATA_WIDTH) + C_RX_INPUT_STAGES;
localparam C_RX_METADW2_CYCLE = (`TLP_CPLMETADW2_I/C_PCI_DATA_WIDTH) + C_RX_INPUT_STAGES;
localparam C_RX_METADW0_INDEX = C_PCI_DATA_WIDTH*C_RX_INPUT_STAGES + (`TLP_CPLMETADW0_I%C_PCI_DATA_WIDTH);
localparam C_RX_METADW1_INDEX = C_PCI_DATA_WIDTH*C_RX_INPUT_STAGES + (`TLP_CPLMETADW1_I%C_PCI_DATA_WIDTH);
localparam C_RX_METADW2_INDEX = C_PCI_DATA_WIDTH*C_RX_INPUT_STAGES + (`TLP_CPLMETADW2_I%C_PCI_DATA_WIDTH);
localparam C_OFFSET_WIDTH = clog2s(C_PCI_DATA_WIDTH/32);
localparam C_MAX_ABLANK_WIDTH = 32;
localparam C_MAX_START_OFFSET = (`TLP_MAXHDR_W + C_MAX_ABLANK_WIDTH)/32;
localparam C_STD_START_DELAY = (64/C_PCI_DATA_WIDTH);
wire [`TLP_CPLADDR_W-1:0] wAddr;
wire [`TLP_CPLHDR_W-1:0] wMetadata;
wire [`TLP_TYPE_W-1:0] wType;
wire [`TLP_LEN_W-1:0] wLength;
wire [2:0] wHdrLength;
wire [2:0] wHdrLengthM1;
wire [(C_PCI_DATA_WIDTH/32)-1:0] wEndMask;
wire wEndFlag;
wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0] wEndOffset;
wire [(C_PCI_DATA_WIDTH/32)-1:0] wStartMask;
wire wStartFlag;
wire _wStartFlag;
wire [2:0] wStartOffset;
wire [3:0] wStartFlags;
wire wInsertBlank;
wire [C_PCI_DATA_WIDTH-1:0] wRxcData;
wire [95:0] wRxcMetadata;
wire wRxcDataValid;
wire wRxcDataEndFlag;
wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0] wRxcDataEndOffset;
wire wRxcDataStartFlag;
wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0] wRxcDataStartOffset;
wire [(C_PCI_DATA_WIDTH/32)-1:0] wRxcDataWordEnable;
wire [C_RX_PIPELINE_DEPTH:0] wRxSrSop;
reg rValid,_rValid;
// Calculate the header length (start offset), and header length minus 1 (end offset)
assign wHdrLength = 3'b011;
assign wHdrLengthM1 = 3'b010;
// Determine if the TLP has an inserted blank before the payload
assign wInsertBlank = ~wAddr[2] & (C_VENDOR == "ALTERA");
assign wStartOffset = (wHdrLength + {2'd0,wInsertBlank}); // Start offset in dwords
assign wEndOffset = wHdrLengthM1 + wInsertBlank + wLength; //RX_SR_END_OFFSET[(C_TOTAL_STAGES-1)*`SIG_OFFSET_W +: C_OFFSET_WIDTH];
// Outputs
assign RXC_DATA = RX_SR_DATA[(C_TOTAL_STAGES)*C_PCI_DATA_WIDTH +: C_PCI_DATA_WIDTH];
assign RXC_DATA_VALID = wRxcDataValid;
assign RXC_DATA_END_FLAG = wRxcDataEndFlag;
assign RXC_DATA_END_OFFSET = wRxcDataEndOffset;
assign RXC_DATA_START_FLAG = wRxcDataStartFlag;
assign RXC_DATA_START_OFFSET = wRxcDataStartOffset;
assign RXC_META_LENGTH = wRxcMetadata[`TLP_LEN_R];
//assign RXC_META_TC = wRxcMetadata[`TLP_TC_R];
//assign RXC_META_ATTR = {wRxcMetadata[`TLP_ATTR1_R], wRxcMetadata[`TLP_ATTR0_R]};
assign RXC_META_TYPE = tlp_to_trellis_type({wRxcMetadata[`TLP_FMT_R],wRxcMetadata[`TLP_TYPE_R]});
assign RXC_META_ADDR = wRxcMetadata[`TLP_CPLADDR_R];
assign RXC_META_COMPLETER_ID = wRxcMetadata[`TLP_CPLCPLID_R];
assign RXC_META_BYTES_REMAINING = wRxcMetadata[`TLP_CPLBYTECNT_R];
assign RXC_META_TAG = wRxcMetadata[`TLP_CPLTAG_R];
assign RXC_META_EP = wRxcMetadata[`TLP_EP_R];
assign RXC_META_FDWBE = 0;// TODO: Remove (use addr)
assign RXC_META_LDWBE = 0;// TODO: Remove (use addr)
assign wEndFlag = RX_SR_EOP[C_RX_INPUT_STAGES+1];
assign _wStartFlag = wStartFlags != 0;
generate
if(C_PCI_DATA_WIDTH == 32) begin
assign wStartFlags[3] = 0;
assign wStartFlags[2] = wRxSrSop[C_RX_INPUT_STAGES + 3] & wMetadata[`TLP_PAYBIT_I] & ~rValid; // Any remaining cases
assign wStartFlags[1] = wRxSrSop[C_RX_INPUT_STAGES + 2] & wMetadata[`TLP_PAYBIT_I] & ~wMetadata[`TLP_4DWHBIT_I]; // 3DWH, No Blank
assign wStartFlags[0] = wRxSrSop[C_RX_INPUT_STAGES + 2] & ~wMetadata[`TLP_PAYBIT_I]; // No Payload
end else if(C_PCI_DATA_WIDTH == 64) begin
assign wStartFlags[3] = 0;
assign wStartFlags[2] = wRxSrSop[C_RX_INPUT_STAGES + 2] & wMetadata[`TLP_PAYBIT_I] & ~rValid; // Any remaining cases
if(C_VENDOR == "ALTERA") begin
assign wStartFlags[1] = wRxSrSop[C_RX_INPUT_STAGES + 1] & wMetadata[`TLP_PAYBIT_I] & ~wMetadata[`TLP_4DWHBIT_I] & RX_SR_DATA[C_RX_METADW2_INDEX + 2]; // 3DWH, No Blank
end else begin
assign wStartFlags[1] = wRxSrSop[C_RX_INPUT_STAGES + 1] & wMetadata[`TLP_PAYBIT_I] & ~wMetadata[`TLP_4DWHBIT_I]; // 3DWH, No Blank
end
assign wStartFlags[0] = wRxSrSop[C_RX_INPUT_STAGES + 1] & ~wMetadata[`TLP_PAYBIT_I] & rValid; // No Payload
end else if (C_PCI_DATA_WIDTH == 128) begin
assign wStartFlags[3] = 0;
assign wStartFlags[2] = wRxSrSop[C_RX_INPUT_STAGES + 1] & wMetadata[`TLP_PAYBIT_I] & ~rValid; // Is this correct?
if(C_VENDOR == "ALTERA") begin
assign wStartFlags[1] = wRxSrSop[C_RX_INPUT_STAGES] & RX_SR_DATA[C_RX_METADW0_INDEX + `TLP_PAYBIT_I] & ~RX_SR_DATA[C_RX_METADW0_INDEX + `TLP_4DWHBIT_I] & RX_SR_DATA[C_RX_METADW2_INDEX + 2]; // 3DWH, No Blank
end else begin
assign wStartFlags[1] = wRxSrSop[C_RX_INPUT_STAGES] & RX_SR_DATA[C_RX_METADW0_INDEX + `TLP_PAYBIT_I] & ~RX_SR_DATA[C_RX_METADW0_INDEX + `TLP_4DWHBIT_I];
end
assign wStartFlags[0] = wRxSrSop[C_RX_INPUT_STAGES] & ~RX_SR_DATA[C_RX_METADW0_INDEX + `TLP_PAYBIT_I]; // No Payload
end else begin // 256
assign wStartFlags[3] = 0;
assign wStartFlags[2] = 0;
assign wStartFlags[1] = 0;
assign wStartFlags[0] = wRxSrSop[C_RX_INPUT_STAGES];
end // else: !if(C_PCI_DATA_WIDTH == 128)
endgenerate
always @(*) begin
_rValid = rValid;
if(_wStartFlag) begin
_rValid = 1'b1;
end else if (RX_SR_EOP[C_RX_INPUT_STAGES+1]) begin
_rValid = 1'b0;
end
end
always @(posedge CLK) begin
if(RST_IN) begin
rValid <= 1'b0;
end else begin
rValid <= _rValid;
end
end
register
#(
// Parameters
.C_WIDTH (32))
metadata_DW0_register
(
// Outputs
.RD_DATA (wMetadata[31:0]),
// Inputs
.CLK (CLK),
.RST_IN (RST_IN),
.WR_DATA (RX_SR_DATA[C_RX_METADW0_INDEX +: 32]),
.WR_EN (wRxSrSop[C_RX_METADW0_CYCLE]));
register
#(
// Parameters
.C_WIDTH (32))
meta_DW1_register
(
// Outputs
.RD_DATA (wMetadata[63:32]),
// Inputs
.CLK (CLK),
.RST_IN (RST_IN),
.WR_DATA (RX_SR_DATA[C_RX_METADW1_INDEX +: 32]),
.WR_EN (wRxSrSop[C_RX_METADW1_CYCLE]));
register
#(
// Parameters
.C_WIDTH (32))
meta_DW2_register
(
// Outputs
.RD_DATA (wMetadata[95:64]),
// Inputs
.CLK (CLK),
.RST_IN (RST_IN),
.WR_DATA (RX_SR_DATA[C_RX_METADW2_INDEX +: 32]),
.WR_EN (wRxSrSop[C_RX_METADW2_CYCLE]));
register
#(
// Parameters
.C_WIDTH (`TLP_TYPE_W))
metadata_type_register
(
// Outputs
.RD_DATA (wType),
// Inputs
.CLK (CLK),
.RST_IN (RST_IN),
.WR_DATA (RX_SR_DATA[(`TLP_TYPE_I + C_PCI_DATA_WIDTH*C_RX_INPUT_STAGES) +: `TLP_TYPE_W]),
.WR_EN (wRxSrSop[`TLP_TYPE_I/C_PCI_DATA_WIDTH + C_RX_INPUT_STAGES]));
register
#(
// Parameters
.C_WIDTH (`TLP_LEN_W))
metadata_length_register
(
// Outputs
.RD_DATA (wLength),
// Inputs
.CLK (CLK),
.RST_IN (RST_IN),
.WR_DATA (RX_SR_DATA[((`TLP_LEN_I%C_PCI_DATA_WIDTH) + C_PCI_DATA_WIDTH*C_RX_INPUT_STAGES) +: `TLP_LEN_W]),
.WR_EN (wRxSrSop[`TLP_LEN_I/C_PCI_DATA_WIDTH + C_RX_INPUT_STAGES]));
register
#(
// Parameters
.C_WIDTH (`TLP_CPLADDR_W))
metadata_address_register
(
// Outputs
.RD_DATA (wAddr),
// Inputs
.CLK (CLK),
.RST_IN (RST_IN),
.WR_DATA (RX_SR_DATA[((`TLP_CPLADDR_I%C_PCI_DATA_WIDTH) + C_PCI_DATA_WIDTH*C_RX_INPUT_STAGES) +: `TLP_CPLADDR_W]),
.WR_EN (wRxSrSop[`TLP_CPLADDR_I/C_PCI_DATA_WIDTH + C_RX_INPUT_STAGES]));
register
#(
// Parameters
.C_WIDTH (1),
.C_VALUE (1'b0)
/*AUTOINSTPARAM*/)
start_flag_register
(
// Outputs
.RD_DATA (wStartFlag),
// Inputs
.WR_DATA (_wStartFlag),
.WR_EN (1),
/*AUTOINST*/
// Inputs
.CLK (CLK),
.RST_IN (RST_IN));
assign wStartMask = {C_PCI_DATA_WIDTH/32{1'b1}} << ({C_OFFSET_WIDTH{wStartFlag}}& wStartOffset[C_OFFSET_WIDTH-1:0]);
offset_to_mask
#(// Parameters
.C_MASK_SWAP (0),
.C_MASK_WIDTH (C_PCI_DATA_WIDTH/32)
/*AUTOINSTPARAM*/)
o2m_ef
(
// Outputs
.MASK (wEndMask),
// Inputs
.OFFSET_ENABLE (wEndFlag),
.OFFSET (wEndOffset)
/*AUTOINST*/);
generate
if(C_RX_OUTPUT_STAGES == 0) begin
assign RXC_DATA_WORD_ENABLE = {wEndMask & wStartMask} & {C_PCI_DATA_WIDTH/32{~rValid | ~wMetadata[`TLP_PAYBIT_I]}};
end else begin
register
#(
// Parameters
.C_WIDTH (C_PCI_DATA_WIDTH/32),
.C_VALUE (0)
/*AUTOINSTPARAM*/)
dw_enable
(// Outputs
.RD_DATA (wRxcDataWordEnable),
// Inputs
.RST_IN (~rValid | ~wMetadata[`TLP_PAYBIT_I]),
.WR_DATA (wEndMask & wStartMask),
.WR_EN (1),
/*AUTOINST*/
.CLK (CLK));
pipeline
#(
// Parameters
.C_DEPTH (C_RX_OUTPUT_STAGES-1),
.C_WIDTH (C_PCI_DATA_WIDTH/32),
.C_USE_MEMORY (0)
/*AUTOINSTPARAM*/)
dw_pipeline
(
// Outputs
.WR_DATA_READY (), // Pinned to 1
.RD_DATA (RXC_DATA_WORD_ENABLE),
.RD_DATA_VALID (),
// Inputs
.WR_DATA (wRxcDataWordEnable),
.WR_DATA_VALID (1),
.RD_DATA_READY (1'b1),
/*AUTOINST*/
// Inputs
.CLK (CLK),
.RST_IN (RST_IN));
end
endgenerate
pipeline
#(
// Parameters
.C_DEPTH (C_RX_OUTPUT_STAGES),
.C_WIDTH (`TLP_CPLHDR_W + 2*(clog2s(C_PCI_DATA_WIDTH/32) + 1)),
.C_USE_MEMORY (0)
/*AUTOINSTPARAM*/)
output_pipeline
(
// Outputs
.WR_DATA_READY (), // Pinned to 1
.RD_DATA ({wRxcMetadata,wRxcDataStartFlag,wRxcDataStartOffset,wRxcDataEndFlag,wRxcDataEndOffset}),
.RD_DATA_VALID (wRxcDataValid),
// Inputs
.WR_DATA ({wMetadata, wStartFlag,wStartOffset[C_OFFSET_WIDTH-1:0],wEndFlag,wEndOffset[C_OFFSET_WIDTH-1:0]}),
.WR_DATA_VALID (rValid),
.RD_DATA_READY (1'b1),
/*AUTOINST*/
// Inputs
.CLK (CLK),
.RST_IN (RST_IN));
// Start Flag Shift Register. Data enables are derived from the
// taps on this shift register.
shiftreg
#(
// Parameters
.C_DEPTH (C_RX_PIPELINE_DEPTH),
.C_WIDTH (1'b1)
/*AUTOINSTPARAM*/)
sop_shiftreg_inst
(
// Outputs
.RD_DATA (wRxSrSop),
// Inputs
.WR_DATA (RX_TLP_START_FLAG & RX_TLP_VALID & (RX_SR_DATA[`TLP_TYPE_R] == `TLP_TYPE_CPL)),
/*AUTOINST*/
// Inputs
.CLK (CLK),
.RST_IN (RST_IN));
endmodule
|
module rxc_engine_128
#(parameter C_PCI_DATA_WIDTH = 128,
parameter C_RX_PIPELINE_DEPTH=10
)
(
// Interface: Clocks
input CLK,
// Interface: Resets
input RST_IN,
// Interface: RX Classic
input [C_PCI_DATA_WIDTH-1:0] RX_TLP,
input RX_TLP_VALID,
input RX_TLP_START_FLAG,
input [`SIG_OFFSET_W-1:0] RX_TLP_START_OFFSET,
input RX_TLP_END_FLAG,
input [`SIG_OFFSET_W-1:0] RX_TLP_END_OFFSET,
input [`SIG_BARDECODE_W-1:0] RX_TLP_BAR_DECODE,
// Interface: RXC Engine
output [C_PCI_DATA_WIDTH-1:0] RXC_DATA,
output RXC_DATA_VALID,
output [(C_PCI_DATA_WIDTH/32)-1:0] RXC_DATA_WORD_ENABLE,
output RXC_DATA_START_FLAG,
output [clog2s(C_PCI_DATA_WIDTH/32)-1:0] RXC_DATA_START_OFFSET,
output RXC_DATA_END_FLAG,
output [clog2s(C_PCI_DATA_WIDTH/32)-1:0] RXC_DATA_END_OFFSET,
output [`SIG_LBE_W-1:0] RXC_META_LDWBE,
output [`SIG_FBE_W-1:0] RXC_META_FDWBE,
output [`SIG_TAG_W-1:0] RXC_META_TAG,
output [`SIG_LOWADDR_W-1:0] RXC_META_ADDR,
output [`SIG_TYPE_W-1:0] RXC_META_TYPE,
output [`SIG_LEN_W-1:0] RXC_META_LENGTH,
output [`SIG_BYTECNT_W-1:0] RXC_META_BYTES_REMAINING,
output [`SIG_CPLID_W-1:0] RXC_META_COMPLETER_ID,
output RXC_META_EP,
// Interface: RX Shift Register
input [(C_RX_PIPELINE_DEPTH+1)*C_PCI_DATA_WIDTH-1:0] RX_SR_DATA,
input [C_RX_PIPELINE_DEPTH:0] RX_SR_EOP,
input [(C_RX_PIPELINE_DEPTH+1)*`SIG_OFFSET_W-1:0] RX_SR_END_OFFSET,
input [(C_RX_PIPELINE_DEPTH+1)*`SIG_OFFSET_W-1:0] RX_SR_START_OFFSET,
input [C_RX_PIPELINE_DEPTH:0] RX_SR_SOP,
input [C_RX_PIPELINE_DEPTH:0] RX_SR_VALID
);
`include "functions.vh"
/*AUTOWIRE*/
///*AUTOOUTPUT*/
localparam C_RX_BE_W = (`SIG_FBE_W+`SIG_LBE_W);
localparam C_RX_INPUT_STAGES = 1;
localparam C_RX_OUTPUT_STAGES = 1;
localparam C_RX_COMPUTATION_STAGES = 1;
localparam C_RX_HDR_STAGES = 1; // Specific to the Xilinx 128-bit RXC Engine
localparam C_TOTAL_STAGES = C_RX_COMPUTATION_STAGES + C_RX_OUTPUT_STAGES + C_RX_INPUT_STAGES + C_RX_HDR_STAGES;
localparam C_OFFSET_WIDTH = clog2s(C_PCI_DATA_WIDTH/32);
localparam C_STRADDLE_W = 64;
localparam C_HDR_NOSTRADDLE_I = C_RX_INPUT_STAGES * C_PCI_DATA_WIDTH;
localparam C_OUTPUT_STAGE_WIDTH = (C_PCI_DATA_WIDTH/32) + 2 + clog2s(C_PCI_DATA_WIDTH/32) + 1 + `SIG_TAG_W + `SIG_TYPE_W + `SIG_LOWADDR_W + `SIG_REQID_W + `SIG_LEN_W + `SIG_BYTECNT_W;
// Header Reg Inputs
wire [`SIG_OFFSET_W-1:0] __wRxcStartOffset;
wire [`SIG_OFFSET_W-1:0] __wRxcStraddledStartOffset;
wire [`TLP_MAXHDR_W-1:0] __wRxcHdr;
wire [`TLP_MAXHDR_W-1:0] __wRxcHdrStraddled;
wire [`TLP_MAXHDR_W-1:0] __wRxcHdrNotStraddled;
wire __wRxcHdrStraddle;
wire __wRxcHdrValid;
wire __wRxcHdrSOP;
wire __wRxcHdrSOPStraddle;
// Header Reg Outputs
wire _wRxcHdrValid;
wire _wRxcHdrStraddle;
wire _wRxcHdrSOPStraddle;
wire _wRxcHdrSOP;
wire [`TLP_MAXHDR_W-1:0] _wRxcHdr;
wire _wRxcHdrSF;
wire [2:0] _wRxcHdrDataSoff;
wire _wRxcHdrEF;
wire [1:0] _wRxcHdrDataEoff;
wire _wRxcHdrSCP; // Single Cycle Packet
wire _wRxcHdrMCP; // Multi Cycle Packet
wire _wRxcHdrRegSF;
wire _wRxcHdrRegValid;
wire _wRxcHdrStartFlag;
wire _wRxcHdr3DWHSF;
wire [3:0] _wRxcHdrStartMask;
wire [3:0] _wRxcHdrEndMask;
// Header Reg Outputs
wire [`TLP_MAXHDR_W-1:0] wRxcHdr;
wire wRxcHdrSF;
wire wRxcHdrEF;
wire wRxcHdrValid;
wire [63:0] wRxcMetadata;
wire [`TLP_TYPE_W-1:0] wRxcType;
wire [`TLP_LEN_W-1:0] wRxcLength;
wire [2:0] wRxcHdrLength;// TODO:
wire [`SIG_OFFSET_W-1:0] wRxcHdrStartOffset;// TODO:
wire wRxcHdrSCP; // Single Cycle Packet
wire wRxcHdrMCP; // Multi Cycle Packet
wire [1:0] wRxcHdrDataSoff;
wire [3:0] wRxcHdrStartMask;
wire [3:0] wRxcHdrEndMask;
// Output Register Inputs
wire [C_PCI_DATA_WIDTH-1:0] wRxcData;
wire wRxcDataValid;
wire [(C_PCI_DATA_WIDTH/32)-1:0] wRxcDataWordEnable;
wire wRxcDataStartFlag;
wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0] wRxcDataStartOffset;
wire wRxcDataEndFlag;
wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0] wRxcDataEndOffset;
wire [`SIG_TAG_W-1:0] wRxcMetaTag;
wire [`SIG_TYPE_W-1:0] wRxcMetaType;
wire [`SIG_LOWADDR_W-1:0] wRxcMetaAddr;
wire [`SIG_REQID_W-1:0] wRxcMetaCompleterId;
wire [`SIG_LEN_W-1:0] wRxcMetaLength;
wire wRxcMetaEP;
wire [`SIG_BYTECNT_W-1:0] wRxcMetaBytesRemaining;
reg rStraddledSOP;
reg rStraddledSOPSplit;
// ----- Header Register -----
assign __wRxcHdrSOP = RX_SR_SOP[C_RX_INPUT_STAGES] & ~__wRxcStartOffset[1];
assign __wRxcHdrSOPStraddle = RX_SR_SOP[C_RX_INPUT_STAGES] & __wRxcStraddledStartOffset[1];
assign __wRxcHdrNotStraddled = RX_SR_DATA[C_HDR_NOSTRADDLE_I +: C_PCI_DATA_WIDTH];
assign __wRxcHdrStraddled = {RX_SR_DATA[C_RX_INPUT_STAGES*C_PCI_DATA_WIDTH +: C_STRADDLE_W],
RX_SR_DATA[(C_RX_INPUT_STAGES+1)*C_PCI_DATA_WIDTH + C_STRADDLE_W +: C_STRADDLE_W ]};
assign __wRxcStartOffset = RX_SR_START_OFFSET[`SIG_OFFSET_W*C_RX_INPUT_STAGES +: `SIG_OFFSET_W];
assign __wRxcStraddledStartOffset = RX_SR_START_OFFSET[`SIG_OFFSET_W*(C_RX_INPUT_STAGES) +: `SIG_OFFSET_W];
assign __wRxcHdrValid = __wRxcHdrSOP | ((rStraddledSOP | rStraddledSOPSplit) & RX_SR_VALID[C_RX_INPUT_STAGES]);
assign _wRxcHdrRegSF = RX_SR_SOP[C_RX_INPUT_STAGES + C_RX_HDR_STAGES] & _wRxcHdrValid;
assign _wRxcHdrDataSoff = {1'b0,_wRxcHdrSOPStraddle,1'b0} + 3'd3;
assign _wRxcHdrRegValid = RX_SR_VALID[C_RX_INPUT_STAGES + C_RX_HDR_STAGES];
assign _wRxcHdr3DWHSF = ~_wRxcHdr[`TLP_4DWHBIT_I] & _wRxcHdrSOP;
assign _wRxcHdrSF = (_wRxcHdr3DWHSF | _wRxcHdrSOPStraddle);
assign _wRxcHdrEF = RX_SR_EOP[C_RX_INPUT_STAGES + C_RX_HDR_STAGES];
assign _wRxcHdrDataEoff = RX_SR_END_OFFSET[(C_RX_INPUT_STAGES+C_RX_HDR_STAGES)*`SIG_OFFSET_W +: C_OFFSET_WIDTH];
assign _wRxcHdrSCP = _wRxcHdrSF & _wRxcHdrEF & (_wRxcHdr[`TLP_TYPE_R] == `TLP_TYPE_CPL);
assign _wRxcHdrMCP = (_wRxcHdrSF & ~_wRxcHdrEF & (_wRxcHdr[`TLP_TYPE_R] == `TLP_TYPE_CPL)) |
(wRxcHdrMCP & ~wRxcHdrEF);
assign _wRxcHdrStartMask = 4'hf << (_wRxcHdrSF ? _wRxcHdrDataSoff[1:0] : 0);
assign wRxcDataWordEnable = wRxcHdrEndMask & wRxcHdrStartMask & {4{wRxcDataValid}};
assign wRxcDataValid = wRxcHdrSCP | wRxcHdrMCP;
assign wRxcDataStartFlag = wRxcHdrSF;
assign wRxcDataEndFlag = wRxcHdrEF;
assign wRxcDataStartOffset = wRxcHdrDataSoff;
assign wRxcMetaBytesRemaining = wRxcHdr[`TLP_CPLBYTECNT_R];
assign wRxcMetaTag = wRxcHdr[`TLP_CPLTAG_R];
assign wRxcMetaAddr = wRxcHdr[`TLP_CPLADDR_R];
assign wRxcMetaCompleterId = wRxcHdr[`TLP_REQREQID_R];
assign wRxcMetaLength = wRxcHdr[`TLP_LEN_R];
assign wRxcMetaEP = wRxcHdr[`TLP_EP_R];
assign wRxcMetaType = tlp_to_trellis_type({wRxcHdr[`TLP_FMT_R],wRxcHdr[`TLP_TYPE_R]});
assign RXC_DATA = RX_SR_DATA[C_PCI_DATA_WIDTH*C_TOTAL_STAGES +: C_PCI_DATA_WIDTH];
assign RXC_DATA_END_OFFSET = RX_SR_END_OFFSET[`SIG_OFFSET_W*(C_TOTAL_STAGES) +: C_OFFSET_WIDTH];
always @(posedge CLK) begin
rStraddledSOP <= RX_SR_SOP[C_RX_INPUT_STAGES] & __wRxcStraddledStartOffset[1];
// Set Straddled SOP Split when there is a straddled packet where the
// header is not contiguous. (Not sure if this is ever possible, but
// better safe than sorry assert Straddled SOP Split. See Virtex 6 PCIe
// errata.)
if(__wRxcHdrSOP | RST_IN) begin
rStraddledSOPSplit <=0;
end else begin
rStraddledSOPSplit <= (rStraddledSOP | rStraddledSOPSplit) & ~RX_SR_VALID[C_RX_INPUT_STAGES];
end
end
mux
#(
// Parameters
.C_NUM_INPUTS (2),
.C_CLOG_NUM_INPUTS (1),
.C_WIDTH (`TLP_MAXHDR_W),
.C_MUX_TYPE ("SELECT")
/*AUTOINSTPARAM*/)
hdr_mux
(
// Outputs
.MUX_OUTPUT (__wRxcHdr[`TLP_MAXHDR_W-1:0]),
// Inputs
.MUX_INPUTS ({__wRxcHdrStraddled[`TLP_MAXHDR_W-1:0],
__wRxcHdrNotStraddled[`TLP_MAXHDR_W-1:0]}),
.MUX_SELECT (rStraddledSOP | rStraddledSOPSplit)
/*AUTOINST*/);
register
#(
// Parameters
.C_WIDTH (64 + 1),
.C_VALUE (0)
/*AUTOINSTPARAM*/)
hdr_register_63_0
(
// Outputs
.RD_DATA ({_wRxcHdr[C_STRADDLE_W-1:0], _wRxcHdrValid}),
// Inputs
.WR_DATA ({__wRxcHdr[C_STRADDLE_W-1:0], __wRxcHdrValid}),
.WR_EN (__wRxcHdrSOP | rStraddledSOP),
.RST_IN (RST_IN), // TODO: Remove
/*AUTOINST*/
// Inputs
.CLK (CLK));
register
#(
// Parameters
.C_WIDTH (64),
.C_VALUE (0)
/*AUTOINSTPARAM*/)
hdr_register_127_64
(
// Outputs
.RD_DATA (_wRxcHdr[`TLP_MAXHDR_W-1:C_STRADDLE_W]),
// Inputs
.WR_DATA (__wRxcHdr[`TLP_MAXHDR_W-1:C_STRADDLE_W]),
.WR_EN (__wRxcHdrSOP | rStraddledSOP | rStraddledSOPSplit), // Non straddled start, Straddled, or straddled split
.RST_IN (RST_IN), // TODO: Remove
/*AUTOINST*/
// Inputs
.CLK (CLK));
register
#(
// Parameters
.C_WIDTH (2),
.C_VALUE (0)
/*AUTOINSTPARAM*/)
sf4dwh// TODO: Rename
(
// Outputs
.RD_DATA ({_wRxcHdrSOPStraddle,_wRxcHdrSOP}),
// Inputs
.WR_DATA ({rStraddledSOP,__wRxcHdrSOP}),
.WR_EN (1),
.RST_IN (RST_IN), // TODO: Remove
/*AUTOINST*/
// Inputs
.CLK (CLK));
// ----- Computation Register -----
register
#(
// Parameters
.C_WIDTH (128 + 4),/* TODO: TLP_METADATA_W*/
.C_VALUE (0)
/*AUTOINSTPARAM*/)
metadata
(// Output
.RD_DATA ({wRxcHdr,
wRxcHdrSF, wRxcHdrDataSoff,
wRxcHdrEF}),
// Inputs
.RST_IN (0),
.WR_DATA ({_wRxcHdr,
_wRxcHdrSF, _wRxcHdrDataSoff[1:0],
_wRxcHdrEF}),
.WR_EN (1),
/*AUTOINST*/
// Inputs
.CLK (CLK));
register
#(
// Parameters
.C_WIDTH (3+8),
.C_VALUE (0)
/*AUTOINSTPARAM*/)
metadata_valid
(// Output
.RD_DATA ({wRxcHdrValid,
wRxcHdrSCP, wRxcHdrMCP,
wRxcHdrEndMask, wRxcHdrStartMask}),
// Inputs
.RST_IN (RST_IN),
.WR_DATA ({_wRxcHdrValid,
_wRxcHdrSCP, _wRxcHdrMCP,
_wRxcHdrEndMask, _wRxcHdrStartMask}), // Need to invert the start mask
.WR_EN (1),
/*AUTOINST*/
// Inputs
.CLK (CLK));
offset_to_mask
#(// Parameters
.C_MASK_SWAP (0),
.C_MASK_WIDTH (4)
/*AUTOINSTPARAM*/)
o2m_ef
(
// Outputs
.MASK (_wRxcHdrEndMask),
// Inputs
.OFFSET_ENABLE (_wRxcHdrEF),
.OFFSET (_wRxcHdrDataEoff)
/*AUTOINST*/);
pipeline
#(
// Parameters
.C_DEPTH (C_RX_OUTPUT_STAGES),
.C_WIDTH (C_OUTPUT_STAGE_WIDTH),
.C_USE_MEMORY (0)
/*AUTOINSTPARAM*/)
output_pipeline
(
// Outputs
.WR_DATA_READY (), // Pinned to 1
.RD_DATA ({RXC_DATA_WORD_ENABLE, RXC_DATA_START_FLAG, RXC_DATA_START_OFFSET,
RXC_DATA_END_FLAG, RXC_META_TAG, RXC_META_TYPE,
RXC_META_ADDR, RXC_META_COMPLETER_ID, RXC_META_BYTES_REMAINING,
RXC_META_LENGTH, RXC_META_EP}),
.RD_DATA_VALID (RXC_DATA_VALID),
// Inputs
.WR_DATA ({wRxcDataWordEnable, wRxcDataStartFlag, wRxcDataStartOffset,
wRxcDataEndFlag, wRxcMetaTag, wRxcMetaType,
wRxcMetaAddr, wRxcMetaCompleterId, wRxcMetaBytesRemaining,
wRxcMetaLength, wRxcMetaEP}),
.WR_DATA_VALID (wRxcDataValid),
.RD_DATA_READY (1'b1),
/*AUTOINST*/
// Inputs
.CLK (CLK),
.RST_IN (RST_IN));
endmodule
|
module sky130_fd_sc_hdll__dlrtp (
Q ,
RESET_B,
D ,
GATE
);
// Module ports
output Q ;
input RESET_B;
input D ;
input GATE ;
// Local signals
wire RESET;
wire buf_Q;
// Delay Name Output Other arguments
not not0 (RESET , RESET_B );
sky130_fd_sc_hdll__udp_dlatch$PR `UNIT_DELAY dlatch0 (buf_Q , D, GATE, RESET );
buf buf0 (Q , buf_Q );
endmodule
|
module des_smline_3d
(
input de_clk,
input de_rstn,
input load_actv_3d,
input line_actv_3d,
input nlst_2,
input [15:0] cpx0,
input [15:0] cpy0,
input [15:0] cpx1,
input [15:0] cpy1,
input pipe_busy,
output reg l_pixreq,
output reg l_last_pixel,
output reg l_pc_msk_last,
output reg l_incpat, // Increment the line pattern.
output reg signed [15:0] cpx, // Output Register X
output reg signed [15:0] cpy, // Output Register Y
output reg l_active // Line is active.
);
wire eol;
wire [2:0] dir;
wire eneg;
wire eeqz;
reg dir_maj;
reg [1:0] dir_min;
reg l_delta_x;
reg l_delta_y;
reg signed [15:0] pline_x;
reg signed [15:0] pline_y;
reg signed [15:0] delta_x;
reg signed [15:0] delta_y;
reg signed [15:0] out_x;
reg signed [15:0] out_y;
reg signed [15:0] error_reg;
reg signed [15:0] einc_x;
reg signed [15:0] einc_y;
reg ld_error;
reg l_einc_x;
reg l_einc_y;
reg inc_err;
reg rst_err;
reg l_chgx;
reg l_chgy;
wire l_rht;
wire l_dwn;
reg l_ldmaj;
reg l_ldmin;
reg ld_itr;
reg dec_itr;
reg [15:0] itr_count;
reg l_active_a;
reg go_line_1;
reg go_line;
// e1s <= spac_bus`E1S;
// e2s <= spac_bus`E2S;
// e3s <= spac_bus`E3S;
// ns1 <= spac_bus`NS1;
// ns2 <= spac_bus`NS2;
// Registers/Counter.
always @(posedge de_clk, negedge de_rstn) begin
if(!de_rstn) begin
go_line <= 1'b0;
go_line_1 <= 1'b0;
l_active <= 1'b0;
pline_x <= 16'h0;
pline_y <= 16'h0;
cpx <= 16'h0;
cpy <= 16'h0;
delta_x <= 16'h0;
delta_y <= 16'h0;
dir_maj <= 1'b0;
dir_min <= 2'b00;
error_reg <= 16'h0;
einc_x <= 16'h0;
einc_y <= 16'h0;
itr_count <= 16'h0;
end
else begin
go_line <= (line_actv_3d & go_line_1);
go_line_1 <= load_actv_3d;
l_active <= l_active_a;
pline_x <= out_x;
pline_y <= out_y;
if(l_delta_x) delta_x <= out_x;
if(l_delta_y) delta_y <= out_y;
if(go_line) cpx <= cpx0;
else if(l_rht & l_chgx) cpx <= cpx + 16'h1;
else if(l_chgx) cpx <= cpx - 16'h1;
if(go_line) cpy <= cpy0;
else if(l_dwn & l_chgy) cpy <= cpy + 16'h1;
else if(l_chgy) cpy <= cpy - 16'h1;
if(l_ldmin) dir_min <= {out_y[15], out_x[15]};
if(l_ldmaj) dir_maj <= out_x[15];
if(l_einc_x) einc_x <= out_x;
if(l_einc_y) einc_y <= out_y;
if(ld_error) error_reg <= out_x;
else if(inc_err) error_reg <= error_reg + einc_y;
else if(rst_err) error_reg <= error_reg - einc_x;
if(ld_itr) itr_count <= delta_x;
else if(dec_itr) itr_count <= itr_count - 16'h1;
end
end
assign eneg = error_reg[15];
assign eeqz = ~|error_reg;
assign eol = ~|itr_count;
assign dir = {dir_maj, dir_min};
/****************************************************************/
/* DEFINE PARAMETERS */
/****************************************************************/
/*
`ifdef RTL_SIM
enum {
LWAIT = 4'h0,
L1 = 4'h1,
L2 = 4'h2,
L3 = 4'h3,
L4 = 4'h4,
L5 = 4'h5,
L6 = 4'h6,
L7 = 4'h7,
L8 = 4'h8,
L9 = 4'h9,
LIDLE1 = 4'hA
} l_cs, l_ns;
`else
*/
parameter
LWAIT = 4'h0,
L1 = 4'h1,
L2 = 4'h2,
L3 = 4'h3,
L4 = 4'h4,
L5 = 4'h5,
L6 = 4'h6,
L7 = 4'h7,
L8 = 4'h8,
L9 = 4'h9,
LIDLE1 = 4'hA;
reg [3:0] l_cs, l_ns;
// `endif
parameter
/* define octants */
/* |YMAJ|sign dy|sign dx| */
/* \ | / */
o0=3'b000, /* \ 7 | 6 / */
o1=3'b001, /* \ | / */
o2=3'b010, /* 3 \ | / 2 */
o3=3'b011, /* --------|------- */
o4=3'b100, /* 1 /| \ 0 */
o5=3'b101, /* / | \ */
o6=3'b110, /* / 5 | 4 \ */
o7=3'b111; /* / | \ */
// define internal wires and make assignments
//
always @(posedge de_clk, negedge de_rstn)
if(!de_rstn) l_cs <= LWAIT;
else l_cs <= l_ns;
assign l_rht = ((dir==o0) || (dir==o2) || (dir==o4) || (dir==o6));
assign l_dwn = ((dir==o0) || (dir==o1) || (dir==o4) || (dir==o5));
always @* begin
l_active_a = 1'b1;
l_ldmaj = 1'b0;
l_ldmin = 1'b0;
l_delta_x = 1'b0;
l_delta_y = 1'b0;
l_incpat = 1'b0;
inc_err = 1'b0;
rst_err = 1'b0;
l_einc_x = 1'b0;
l_einc_y = 1'b0;
ld_error = 1'b0;
out_x = 16'h0;
out_y = 16'h0;
ld_itr = 1'b0;
dec_itr = 1'b0;
l_pc_msk_last = 1'b0;
l_last_pixel = 1'b0;
l_chgx = 1'b0;
l_chgy = 1'b0;
l_pixreq = 1'b0;
case(l_cs)
LWAIT: if(go_line) begin
// calculate deltaX and deltaY
// for the direction bits.
out_x = cpx1 - cpx0;
out_y = cpy1 - cpy0;
l_ldmin = 1'b1;
l_ns = L1;
// l_op={dst,src,sub,delta,wrhl};
end
else begin
l_ns= LWAIT;
l_active_a = 1'b0;
end
L1: begin // absolute deltaX and deltaY
out_x = (pline_x[15]) ? ~pline_x + 16'h1 : pline_x;
out_y = (pline_y[15]) ? ~pline_y + 16'h1 : pline_y;
l_delta_x = 1'b1;
l_delta_y = 1'b1;
l_ns = L2;
// l_op={noop,pline,abs,delta,wrhl};
end
// calculate the major axis
// deltaX minus deltaY and save the sign bit in dir[2].
L2: begin
l_ns = L3;
l_ldmaj = 1'b1;
out_x = pline_x - pline_y; // Save only the sign bit in dir_maj.
// l_op={pline,pline,subx,noop,wrno};
end
L3: l_ns = L4;
// If deltaY > deltaX, swap deltaX and deltY. */
L4: begin
l_ns = L5;
if(dir[2]) begin
out_x = delta_y;
out_y = delta_x;
l_delta_x = 1'b1;
l_delta_y = 1'b1;
end
else begin
out_x = delta_x;
out_y = delta_y;
end
end
// fx = (ax * 2) - (ay * 2), fy= (ay * 2)
L5: begin
l_ns =L6;
// l_op={pline,pline,err_inc,einc,wrhl};
out_x = (pline_x << 1) - (pline_y << 1);
out_y = (pline_y << 1);
l_einc_x = 1'b1;
l_einc_y = 1'b1;
ld_itr = 1'b1;
end
// initial error equals (-delta major + 2(delta minor)).
L6: begin
l_ns=L7;
ld_error = 1'b1;
out_x = (~delta_x + 16'h1) + (delta_y << 1);
// l_op={pline,delta,cmp_add,error,wrhi};
end
L7: begin
if(!pipe_busy) begin
// l_op={noop,pline,mov,noop,wrno};
out_x = pline_x;
out_y = pline_y;
l_ns = L9;
end
else begin
l_ns = L8;
// l_pipe_adv=1;
end
end
// End of line with nolast set
// Go to IDLE state.
L8: begin
if(eol && nlst_2) begin
l_ns = LIDLE1;
l_pixreq = 1'b1;
l_last_pixel = 1'b1;
l_pc_msk_last = 1'b1;
// l_op={noop,dst,mov,src,wrhl};
end
// End of line with nolast not set and stop or not stop.
// draw last pixel if pixel cache is not busy.
// Go to IDLE state.
else if(!pipe_busy && eol && !nlst_2) begin
l_ns = LIDLE1;
l_incpat = 1'b1;
// l_op={noop,dst,mov,src,wrhl};
end
// Not end of line draw pixel if pixel cache is not busy.
else if(!pipe_busy && !eol) begin
dec_itr = 1'b1;
l_incpat = 1'b1;
l_ns = L8;
// error > 0 reset error
if(!pipe_busy && (dir==o1 || dir==o3 || dir==o5 || dir==o7) && !eneg && !eeqz) // > 0
rst_err = 1;
// error >= 0 reset error
else if(!pipe_busy && (dir==o0 || dir==o2 || dir==o4 || dir==o6) && !eneg) // >= 0
rst_err = 1;
else if(!pipe_busy) begin
inc_err = 1; // increment error.
end
end
else begin
// l_op={noop,pline,mov,noop,wrno};
l_ns = L8;
end
if(!pipe_busy) begin
if(eol && !nlst_2) begin
l_pixreq = 1'b1;
l_last_pixel = 1'b1;
end
else if(!eol)l_pixreq = 1'b1;
if(!eol && (dir==o1 || dir==o3 || dir==o5 || dir==o7) && !eneg && !eeqz)// > 0
l_chgx = 1'b1;
else if(!eol && (dir==o0 || dir==o2 || dir==o4 || dir==o6) && !eneg) // >= 0
l_chgx = 1'b1;
else if(!eol && (dir==o0 || dir==o1 || dir==o2 || dir==o3))
l_chgx = 1'b1;
if(!eol && (dir==o1 || dir==o3 || dir==o5 || dir==o7) && !eneg && !eeqz)// > 0
l_chgy = 1'b1;
else if(!eol && (dir==o0 || dir==o2 || dir==o4 || dir==o6) && !eneg) // >= 0
l_chgy = 1'b1;
else if(!eol && (dir==o4 || dir==o5 || dir==o6 || dir==o7))
l_chgy = 1'b1;
end
end
L9: begin
l_ns=L8;
out_x = pline_x;
out_y = pline_y;
end
LIDLE1: begin
l_ns = LWAIT;
end
endcase
end
endmodule
|
module ddr3_s4_uniphy_example_if0_p0_qsys_sequencer_sequencer_rom (
// inputs:
address,
byteenable,
chipselect,
clk,
clken,
debugaccess,
reset,
write,
writedata,
// outputs:
readdata
)
;
parameter INIT_FILE = "ddr3_s4_uniphy_example_if0_p0_sequencer_rom.hex";
output [ 31: 0] readdata;
input [ 11: 0] address;
input [ 3: 0] byteenable;
input chipselect;
input clk;
input clken;
input debugaccess;
input reset;
input write;
input [ 31: 0] writedata;
wire [ 31: 0] readdata;
wire wren;
assign wren = chipselect & write & debugaccess;
//s1, which is an e_avalon_slave
//s2, which is an e_avalon_slave
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
altsyncram the_altsyncram
(
.address_a (address),
.byteena_a (byteenable),
.clock0 (clk),
.clocken0 (clken),
.data_a (writedata),
.q_a (readdata),
.wren_a (wren)
);
defparam the_altsyncram.byte_size = 8,
the_altsyncram.init_file = INIT_FILE,
the_altsyncram.lpm_type = "altsyncram",
the_altsyncram.maximum_depth = 4096,
the_altsyncram.numwords_a = 4096,
the_altsyncram.operation_mode = "SINGLE_PORT",
the_altsyncram.outdata_reg_a = "UNREGISTERED",
the_altsyncram.ram_block_type = "AUTO",
the_altsyncram.read_during_write_mode_mixed_ports = "DONT_CARE",
the_altsyncram.width_a = 32,
the_altsyncram.width_byteena_a = 4,
the_altsyncram.widthad_a = 12;
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
//synthesis read_comments_as_HDL on
// altsyncram the_altsyncram
// (
// .address_a (address),
// .byteena_a (byteenable),
// .clock0 (clk),
// .clocken0 (clken),
// .data_a (writedata),
// .q_a (readdata),
// .wren_a (wren)
// );
//
// defparam the_altsyncram.byte_size = 8,
// the_altsyncram.init_file = "ddr3_s4_uniphy_example_if0_p0_sequencer_rom.hex",
// the_altsyncram.lpm_type = "altsyncram",
// the_altsyncram.maximum_depth = 4096,
// the_altsyncram.numwords_a = 4096,
// the_altsyncram.operation_mode = "SINGLE_PORT",
// the_altsyncram.outdata_reg_a = "UNREGISTERED",
// the_altsyncram.ram_block_type = "AUTO",
// the_altsyncram.read_during_write_mode_mixed_ports = "DONT_CARE",
// the_altsyncram.width_a = 32,
// the_altsyncram.width_byteena_a = 4,
// the_altsyncram.widthad_a = 12;
//
//synthesis read_comments_as_HDL off
endmodule
|
module alt_mem_ddrx_ddr3_odt_gen
# (parameter
CFG_DWIDTH_RATIO = 2,
CFG_PORT_WIDTH_OUTPUT_REGD = 1,
CFG_PORT_WIDTH_TCL = 4,
CFG_PORT_WIDTH_CAS_WR_LAT = 4
)
(
ctl_clk,
ctl_reset_n,
cfg_tcl,
cfg_cas_wr_lat,
cfg_output_regd,
bg_do_write,
bg_do_read,
bg_do_burst_chop,
int_odt_l,
int_odt_h,
int_odt_i
);
localparam integer CFG_TCL_PIPE_LENGTH = 2**CFG_PORT_WIDTH_TCL;
//=================================================================================================//
// DDR3 ODT timing parameters //
//=================================================================================================//
localparam integer CFG_ODTH8 = 6; //Indicates No. of cycles ODT signal should stay high
localparam integer CFG_ODTH4 = 4; //Indicates No. of cycles ODT signal should stay high
localparam integer CFG_ODTPIPE_THRESHOLD = CFG_DWIDTH_RATIO/2;
// AL also applies to ODT signal so ODT logic is AL agnostic
// also regdimm because ODT is registered too
// ODTLon = CWL + AL - 2
// ODTLoff = CWL + AL - 2
//=================================================================================================//
// input/output declaration //
//=================================================================================================//
input ctl_clk;
input ctl_reset_n;
input [CFG_PORT_WIDTH_TCL-1:0] cfg_tcl;
input [CFG_PORT_WIDTH_CAS_WR_LAT-1:0] cfg_cas_wr_lat;
input [CFG_PORT_WIDTH_OUTPUT_REGD-1:0] cfg_output_regd;
input bg_do_write;
input bg_do_read;
input bg_do_burst_chop;
output int_odt_l;
output int_odt_h;
output int_odt_i;
//=================================================================================================//
// reg/wire declaration //
//=================================================================================================//
wire bg_do_write;
reg int_do_read;
reg int_do_write_burst_chop;
reg int_do_read_burst_chop;
reg int_do_read_burst_chop_c;
reg do_read_r;
wire [3:0] diff_unreg; // difference between CL and CWL
reg [3:0] diff;
wire [3:0] diff_modulo_unreg;
reg [3:0] diff_modulo;
wire [3:0] sel_do_read_pipe_unreg;
reg [3:0] sel_do_read_pipe;
wire diff_modulo_not_zero;
reg int_odt_l_int;
reg int_odt_l_int_r;
reg premux_odt_h;
reg premux_odt_h_r;
reg int_odt_h_int;
reg int_odt_h_int_r;
reg int_odt_i_int;
reg int_odt_i_int_r;
wire int_odt_l;
wire int_odt_h;
wire int_odt_i;
reg [3:0] doing_write_count;
reg [3:0] doing_read_count;
wire doing_read_count_not_zero;
reg doing_read_count_not_zero_r;
wire [3:0] doing_write_count_limit;
wire [3:0] doing_read_count_limit;
reg [CFG_TCL_PIPE_LENGTH -1:0] do_read_pipe;
reg [CFG_TCL_PIPE_LENGTH -1:0] do_burst_chop_pipe;
//=================================================================================================//
// Define ODT pulse width during READ operation //
//=================================================================================================//
//ODTLon/ODTLoff are calculated based on CWL, Below logic is to compensate for that timing during read, Needs to delay ODT signal by cfg_tcl - cfg_cas_wr_lat
assign diff_unreg = cfg_tcl - cfg_cas_wr_lat;
assign diff_modulo_unreg = (diff % CFG_ODTPIPE_THRESHOLD);
assign sel_do_read_pipe_unreg = (diff / CFG_ODTPIPE_THRESHOLD) + diff_modulo;
assign diff_modulo_not_zero = (|diff_modulo);
//assign sel_do_read_pipe = diff - CFG_ODTPIPE_THRESHOLD;
always @(posedge ctl_clk, negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
diff <= 0;
diff_modulo <= 0;
sel_do_read_pipe <= 0;
end
else
begin
diff <= diff_unreg;
diff_modulo <= diff_modulo_unreg;
sel_do_read_pipe <= sel_do_read_pipe_unreg;
end
end
always @ (*)
begin
int_do_read = (diff < CFG_ODTPIPE_THRESHOLD) ? bg_do_read : do_read_pipe [sel_do_read_pipe] ;
int_do_read_burst_chop_c = (diff < CFG_ODTPIPE_THRESHOLD) ? bg_do_burst_chop : do_burst_chop_pipe [sel_do_read_pipe] ;
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (~ctl_reset_n)
begin
int_do_read_burst_chop <= 1'b0;
end
else
begin
if (int_do_read)
begin
int_do_read_burst_chop <= int_do_read_burst_chop_c;
end
end
end
always @(posedge ctl_clk, negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
do_read_pipe <= 0;
end
else
begin
do_read_pipe[CFG_TCL_PIPE_LENGTH-1:0] <= {do_read_pipe[CFG_TCL_PIPE_LENGTH-2:0],bg_do_read};
end
end
always @(posedge ctl_clk, negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
do_burst_chop_pipe <= 0;
end
else
begin
do_burst_chop_pipe[CFG_TCL_PIPE_LENGTH-1:0] <= {do_burst_chop_pipe[CFG_TCL_PIPE_LENGTH-2:0],bg_do_burst_chop};
end
end
assign doing_read_count_limit = int_do_read_burst_chop ? ((CFG_ODTH4 / (CFG_DWIDTH_RATIO / 2)) - 1) : ((CFG_ODTH8 / (CFG_DWIDTH_RATIO / 2)) - 1);
assign doing_read_count_not_zero = (|doing_read_count);
always @(posedge ctl_clk, negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin doing_read_count <= 0; end
else
begin
if (int_do_read)
begin doing_read_count <= 1; end
else if (doing_read_count >= doing_read_count_limit)
begin doing_read_count <= 0; end
else if (doing_read_count > 0)
begin doing_read_count <= doing_read_count + 1'b1; end
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (~ctl_reset_n)
begin
doing_read_count_not_zero_r <= 1'b0;
end
else
begin
doing_read_count_not_zero_r <= doing_read_count_not_zero;
end
end
//=================================================================================================//
// Define ODT pulse width during WRITE operation //
//=================================================================================================//
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (~ctl_reset_n)
begin
int_do_write_burst_chop <= 1'b0;
end
else
begin
if (bg_do_write)
begin
int_do_write_burst_chop <= bg_do_burst_chop;
end
end
end
assign doing_write_count_limit = int_do_write_burst_chop ? ((CFG_ODTH4 / (CFG_DWIDTH_RATIO / 2)) - 1) : ((CFG_ODTH8 / (CFG_DWIDTH_RATIO / 2)) - 1);
always @(posedge ctl_clk, negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin doing_write_count <= 0; end
else
begin
if (bg_do_write)
begin doing_write_count <= 1; end
else if (doing_write_count >= doing_write_count_limit)
begin doing_write_count <= 0; end
else if (doing_write_count > 0)
begin doing_write_count <= doing_write_count + 1'b1; end
end
end
//=================================================================================================//
// ODT signal generation block //
//=================================================================================================//
always @ (*)
begin
if (bg_do_write || int_do_read)
begin premux_odt_h = 1'b1; end
else if (doing_write_count > 0 || doing_read_count > 0)
begin premux_odt_h = 1'b1; end
else
begin premux_odt_h = 1'b0; end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (~ctl_reset_n)
begin
premux_odt_h_r <= 1'b0;
end
else
begin
premux_odt_h_r <= premux_odt_h;
end
end
always @ (*)
begin
if (diff_modulo_not_zero & (int_do_read|doing_read_count_not_zero_r) )
begin
int_odt_h_int = premux_odt_h_r;
end
else // write, read with normal odt
begin
int_odt_h_int = premux_odt_h;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
int_odt_l_int <= 1'b0;
end
else
begin
if (bg_do_write || int_do_read)
begin int_odt_l_int <= 1'b1; end
else if (doing_write_count > 0 || doing_read_count > 0)
begin int_odt_l_int <= 1'b1; end
else
begin int_odt_l_int <= 1'b0; end
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
int_odt_i_int <= 1'b0;
end
else
begin
if (bg_do_write || int_do_read)
begin int_odt_i_int <= 1'b1; end
else if (doing_write_count > 1 || doing_read_count > 1)
begin int_odt_i_int <= 1'b1; end
else
begin int_odt_i_int <= 1'b0; end
end
end
//Generate registered output
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
int_odt_h_int_r <= 1'b0;
int_odt_l_int_r <= 1'b0;
int_odt_i_int_r <= 1'b0;
end
else
begin
int_odt_h_int_r <= int_odt_h_int;
int_odt_l_int_r <= int_odt_l_int;
int_odt_i_int_r <= int_odt_i_int;
end
end
generate
if (CFG_DWIDTH_RATIO == 2) // full rate
begin
assign int_odt_h = (cfg_output_regd) ? int_odt_h_int_r : int_odt_h_int;
assign int_odt_l = (cfg_output_regd) ? int_odt_h_int_r : int_odt_h_int;
assign int_odt_i = 1'b0;
end
else if (CFG_DWIDTH_RATIO == 4) // half rate
begin
assign int_odt_h = (cfg_output_regd) ? int_odt_h_int_r : int_odt_h_int;
assign int_odt_l = (cfg_output_regd) ? int_odt_l_int_r : int_odt_l_int;
assign int_odt_i = 1'b0;
end
else if (CFG_DWIDTH_RATIO == 8) // quarter rate
begin
assign int_odt_h = (cfg_output_regd) ? int_odt_h_int_r : int_odt_h_int;
assign int_odt_l = (cfg_output_regd) ? int_odt_l_int_r : int_odt_l_int;
assign int_odt_i = (cfg_output_regd) ? int_odt_i_int_r : int_odt_i_int;
end
endgenerate
endmodule
|
module delta_frame #(
parameter COLOR_WIDTH = 10,
parameter FILTER_LENGTH = 20,
parameter CLOG2_FILTER_LENGTH = 5
)(
// Control
input wire clk,
input wire aresetn,
// Moving Average Filter
input wire is_filter,
input wire is_not_blank,
// Saturation Filter
input wire [(COLOR_WIDTH-1):0] threshold,
// Input Data
input wire [(COLOR_WIDTH-1):0] base_frame,
input wire [(COLOR_WIDTH-1):0] curr_frame,
// Output Data
output wire [(COLOR_WIDTH-1):0] delta_frame
);
// Not totally sure if this is the right way, think its safe though
localparam SUM_LENGTH = CLOG2_FILTER_LENGTH + COLOR_WIDTH;
// Internal signals and variables
genvar c;
integer i;
reg [2:0] counter;
reg [(COLOR_WIDTH-1):0] old [FILTER_LENGTH];
reg [(SUM_LENGTH-1):0] sum;
wire [(COLOR_WIDTH-1):0] avg;
reg [(COLOR_WIDTH-1):0] int_delta_frame;
wire [(COLOR_WIDTH-1):0] comp_value;
// Saturation Filter
assign comp_value = is_filter ? avg : int_delta_frame;
assign delta_frame = (comp_value > threshold) ? {COLOR_WIDTH{1'b1}} : {COLOR_WIDTH{1'b0}};
// Delta Frame
always @(posedge clk or negedge aresetn) begin
if (~aresetn) int_delta_frame <= 'd0;
else if (~is_not_blank) int_delta_frame <= 'd0;
else
begin
// Poor man's absolute value
if (curr_frame > base_frame) int_delta_frame <= curr_frame - base_frame;
else int_delta_frame <= base_frame - curr_frame;
end
end
// Moving Average Filter
always @(posedge clk or negedge aresetn) begin
if (~aresetn) counter <= 'd0;
else if (~is_not_blank) counter <= counter;
else if (counter == FILTER_LENGTH) counter <= 'd0;
else counter <= counter + 1;
end
generate
for (c = 0; c < FILTER_LENGTH; c = c + 1) begin: moving_avg_filter
always @(posedge clk or negedge aresetn) begin
if (~aresetn) old[c] <= 'd0;
else if (~is_not_blank) old[c] <= 'd0;
else if (counter == c) old[c] <= int_delta_frame;
else old[c] <= old[c];
end
end
endgenerate
always @* begin
sum = 'd0;
for (i = 0; i < FILTER_LENGTH; i = i + 1)
sum = sum + old[i];
end
assign avg = sum / FILTER_LENGTH;
endmodule
|
module sky130_fd_sc_lp__busdrivernovlp2 (
Z ,
A ,
TE_B
);
// Module ports
output Z ;
input A ;
input TE_B;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Name Output Other arguments
bufif0 bufif00 (Z , A, TE_B );
endmodule
|
module axis_frame_length_adjust #
(
parameter DATA_WIDTH = 1,
parameter KEEP_WIDTH = (DATA_WIDTH/8)
)
(
input wire clk,
input wire rst,
/*
* AXI input
*/
input wire [DATA_WIDTH-1:0] input_axis_tdata,
input wire [KEEP_WIDTH-1:0] input_axis_tkeep,
input wire input_axis_tvalid,
output wire input_axis_tready,
input wire input_axis_tlast,
input wire input_axis_tuser,
/*
* AXI output
*/
output wire [DATA_WIDTH-1:0] output_axis_tdata,
output wire [KEEP_WIDTH-1:0] output_axis_tkeep,
output wire output_axis_tvalid,
input wire output_axis_tready,
output wire output_axis_tlast,
output wire output_axis_tuser,
/*
* Status
*/
output wire status_valid,
input wire status_ready,
output wire status_frame_pad,
output wire status_frame_truncate,
output wire [15:0] status_frame_length,
output wire [15:0] status_frame_original_length,
/*
* Configuration
*/
input wire [15:0] length_min,
input wire [15:0] length_max
);
// bus word width
localparam DATA_WORD_WIDTH = DATA_WIDTH / KEEP_WIDTH;
// bus width assertions
initial begin
if (DATA_WORD_WIDTH * KEEP_WIDTH != DATA_WIDTH) begin
$error("Error: data width not evenly divisble");
$finish;
end
end
// state register
localparam [2:0]
STATE_IDLE = 3'd0,
STATE_TRANSFER = 3'd1,
STATE_PAD = 3'd2,
STATE_TRUNCATE = 3'd3;
reg [2:0] state_reg = STATE_IDLE, state_next;
// datapath control signals
reg store_last_word;
reg [15:0] frame_ptr_reg = 16'd0, frame_ptr_next;
// frame length counters
reg [15:0] short_counter_reg = 16'd0, short_counter_next = 16'd0;
reg [15:0] long_counter_reg = 16'd0, long_counter_next = 16'd0;
reg [DATA_WIDTH-1:0] last_word_data_reg = {DATA_WIDTH{1'b0}};
reg [KEEP_WIDTH-1:0] last_word_keep_reg = {KEEP_WIDTH{1'b0}};
reg last_cycle_tuser_reg = 1'b0, last_cycle_tuser_next;
reg status_valid_reg = 1'b0, status_valid_next;
reg status_frame_pad_reg = 1'b0, status_frame_pad_next;
reg status_frame_truncate_reg = 1'b0, status_frame_truncate_next;
reg [15:0] status_frame_length_reg = 16'd0, status_frame_length_next;
reg [15:0] status_frame_original_length_reg = 16'd0, status_frame_original_length_next;
// internal datapath
reg [DATA_WIDTH-1:0] output_axis_tdata_int;
reg [KEEP_WIDTH-1:0] output_axis_tkeep_int;
reg output_axis_tvalid_int;
reg output_axis_tready_int_reg = 1'b0;
reg output_axis_tlast_int;
reg output_axis_tuser_int;
wire output_axis_tready_int_early;
reg input_axis_tready_reg = 1'b0, input_axis_tready_next;
assign input_axis_tready = input_axis_tready_reg;
assign status_valid = status_valid_reg;
assign status_frame_pad = status_frame_pad_reg;
assign status_frame_truncate = status_frame_truncate_reg;
assign status_frame_length = status_frame_length_reg;
assign status_frame_original_length = status_frame_original_length_reg;
integer i, word_cnt;
always @* begin
state_next = STATE_IDLE;
store_last_word = 1'b0;
frame_ptr_next = frame_ptr_reg;
short_counter_next = short_counter_reg;
long_counter_next = long_counter_reg;
output_axis_tdata_int = {DATA_WIDTH{1'b0}};
output_axis_tkeep_int = {KEEP_WIDTH{1'b0}};
output_axis_tvalid_int = 1'b0;
output_axis_tlast_int = 1'b0;
output_axis_tuser_int = 1'b0;
input_axis_tready_next = 1'b0;
last_cycle_tuser_next = last_cycle_tuser_reg;
status_valid_next = status_valid_reg & ~status_ready;
status_frame_pad_next = status_frame_pad_reg;
status_frame_truncate_next = status_frame_truncate_reg;
status_frame_length_next = status_frame_length_reg;
status_frame_original_length_next = status_frame_original_length_reg;
case (state_reg)
STATE_IDLE: begin
// idle state
// accept data next cycle if output register ready next cycle
input_axis_tready_next = output_axis_tready_int_early & (~status_valid_reg | status_ready);
output_axis_tdata_int = input_axis_tdata;
output_axis_tkeep_int = input_axis_tkeep;
output_axis_tvalid_int = input_axis_tvalid;
output_axis_tlast_int = input_axis_tlast;
output_axis_tuser_int = input_axis_tuser;
short_counter_next = length_min;
long_counter_next = length_max;
if (input_axis_tready & input_axis_tvalid) begin
// transfer through
word_cnt = 0;
for (i = 0; i <= KEEP_WIDTH; i = i + 1) begin
//bit_cnt = bit_cnt + monitor_axis_tkeep[i];
if (input_axis_tkeep == ({KEEP_WIDTH{1'b1}}) >> (KEEP_WIDTH-i)) word_cnt = i;
end
frame_ptr_next = frame_ptr_reg+KEEP_WIDTH;
if (short_counter_reg > KEEP_WIDTH) begin
short_counter_next = short_counter_reg - KEEP_WIDTH;
end else begin
short_counter_next = 16'd0;
end
if (long_counter_reg > KEEP_WIDTH) begin
long_counter_next = long_counter_reg - KEEP_WIDTH;
end else begin
long_counter_next = 16'd0;
end
if (long_counter_reg <= word_cnt) begin
output_axis_tkeep_int = ({KEEP_WIDTH{1'b1}}) >> (KEEP_WIDTH-long_counter_reg);
if (input_axis_tlast) begin
status_valid_next = 1'b1;
status_frame_pad_next = 1'b0;
status_frame_truncate_next = word_cnt > long_counter_reg;
status_frame_length_next = length_max;
status_frame_original_length_next = frame_ptr_reg+word_cnt;
input_axis_tready_next = output_axis_tready_int_early & status_ready;
frame_ptr_next = 16'd0;
short_counter_next = length_min;
long_counter_next = length_max;
state_next = STATE_IDLE;
end else begin
output_axis_tvalid_int = 1'b0;
store_last_word = 1'b1;
state_next = STATE_TRUNCATE;
end
end else begin
if (input_axis_tlast) begin
status_frame_original_length_next = frame_ptr_reg+word_cnt;
if (short_counter_reg > word_cnt) begin
if (short_counter_reg > KEEP_WIDTH) begin
frame_ptr_next = frame_ptr_reg + KEEP_WIDTH;
input_axis_tready_next = 1'b0;
output_axis_tkeep_int = {KEEP_WIDTH{1'b1}};
output_axis_tlast_int = 1'b0;
output_axis_tuser_int = 1'b0;
last_cycle_tuser_next = input_axis_tuser;
state_next = STATE_PAD;
end else begin
status_valid_next = 1'b1;
status_frame_pad_next = 1'b1;
status_frame_truncate_next = 1'b0;
status_frame_length_next = length_min;
input_axis_tready_next = output_axis_tready_int_early & status_ready;
output_axis_tkeep_int = ({KEEP_WIDTH{1'b1}}) >> (KEEP_WIDTH-(length_min - frame_ptr_reg));
frame_ptr_next = 16'd0;
short_counter_next = length_min;
long_counter_next = length_max;
state_next = STATE_IDLE;
end
end else begin
status_valid_next = 1'b1;
status_frame_pad_next = 1'b0;
status_frame_truncate_next = 1'b0;
status_frame_length_next = frame_ptr_reg+word_cnt;
status_frame_original_length_next = frame_ptr_reg+word_cnt;
input_axis_tready_next = output_axis_tready_int_early & status_ready;
frame_ptr_next = 16'd0;
short_counter_next = length_min;
long_counter_next = length_max;
state_next = STATE_IDLE;
end
end else begin
state_next = STATE_TRANSFER;
end
end
end else begin
state_next = STATE_IDLE;
end
end
STATE_TRANSFER: begin
// transfer data
// accept data next cycle if output register ready next cycle
input_axis_tready_next = output_axis_tready_int_early;
output_axis_tdata_int = input_axis_tdata;
output_axis_tkeep_int = input_axis_tkeep;
output_axis_tvalid_int = input_axis_tvalid;
output_axis_tlast_int = input_axis_tlast;
output_axis_tuser_int = input_axis_tuser;
if (input_axis_tready & input_axis_tvalid) begin
// transfer through
word_cnt = 1;
for (i = 1; i <= KEEP_WIDTH; i = i + 1) begin
//bit_cnt = bit_cnt + monitor_axis_tkeep[i];
if (input_axis_tkeep == ({KEEP_WIDTH{1'b1}}) >> (KEEP_WIDTH-i)) word_cnt = i;
end
frame_ptr_next = frame_ptr_reg+KEEP_WIDTH;
if (short_counter_reg > KEEP_WIDTH) begin
short_counter_next = short_counter_reg - KEEP_WIDTH;
end else begin
short_counter_next = 16'd0;
end
if (long_counter_reg > KEEP_WIDTH) begin
long_counter_next = long_counter_reg - KEEP_WIDTH;
end else begin
long_counter_next = 16'd0;
end
if (long_counter_reg <= word_cnt) begin
output_axis_tkeep_int = ({KEEP_WIDTH{1'b1}}) >> (KEEP_WIDTH-long_counter_reg);
if (input_axis_tlast) begin
status_valid_next = 1'b1;
status_frame_pad_next = 1'b0;
status_frame_truncate_next = word_cnt > long_counter_reg;
status_frame_length_next = length_max;
status_frame_original_length_next = frame_ptr_reg+word_cnt;
input_axis_tready_next = output_axis_tready_int_early & status_ready;
frame_ptr_next = 16'd0;
short_counter_next = length_min;
long_counter_next = length_max;
state_next = STATE_IDLE;
end else begin
output_axis_tvalid_int = 1'b0;
store_last_word = 1'b1;
state_next = STATE_TRUNCATE;
end
end else begin
if (input_axis_tlast) begin
status_frame_original_length_next = frame_ptr_reg+word_cnt;
if (short_counter_reg > word_cnt) begin
if (short_counter_reg > KEEP_WIDTH) begin
frame_ptr_next = frame_ptr_reg + KEEP_WIDTH;
input_axis_tready_next = 1'b0;
output_axis_tkeep_int = {KEEP_WIDTH{1'b1}};
output_axis_tlast_int = 1'b0;
output_axis_tuser_int = 1'b0;
last_cycle_tuser_next = input_axis_tuser;
state_next = STATE_PAD;
end else begin
status_valid_next = 1'b1;
status_frame_pad_next = 1'b1;
status_frame_truncate_next = 1'b0;
status_frame_length_next = length_min;
input_axis_tready_next = output_axis_tready_int_early & status_ready;
output_axis_tkeep_int = ({KEEP_WIDTH{1'b1}}) >> (KEEP_WIDTH-short_counter_reg);
frame_ptr_next = 16'd0;
short_counter_next = length_min;
long_counter_next = length_max;
state_next = STATE_IDLE;
end
end else begin
status_valid_next = 1'b1;
status_frame_pad_next = 1'b0;
status_frame_truncate_next = 1'b0;
status_frame_length_next = frame_ptr_reg+word_cnt;
status_frame_original_length_next = frame_ptr_reg+word_cnt;
input_axis_tready_next = output_axis_tready_int_early & status_ready;
frame_ptr_next = 16'd0;
short_counter_next = length_min;
long_counter_next = length_max;
state_next = STATE_IDLE;
end
end else begin
state_next = STATE_TRANSFER;
end
end
end else begin
state_next = STATE_TRANSFER;
end
end
STATE_PAD: begin
// pad to minimum length
input_axis_tready_next = 1'b0;
output_axis_tdata_int = {DATA_WIDTH{1'b0}};
output_axis_tkeep_int = {KEEP_WIDTH{1'b1}};
output_axis_tvalid_int = 1'b1;
output_axis_tlast_int = 1'b0;
output_axis_tuser_int = 1'b0;
if (output_axis_tready_int_reg) begin
frame_ptr_next = frame_ptr_reg + KEEP_WIDTH;
if (short_counter_reg > KEEP_WIDTH) begin
short_counter_next = short_counter_reg - KEEP_WIDTH;
end else begin
short_counter_next = 16'd0;
end
if (long_counter_reg > KEEP_WIDTH) begin
long_counter_next = long_counter_reg - KEEP_WIDTH;
end else begin
long_counter_next = 16'd0;
end
if (short_counter_reg <= KEEP_WIDTH) begin
status_valid_next = 1'b1;
status_frame_pad_next = 1'b1;
status_frame_truncate_next = 1'b0;
status_frame_length_next = length_min;
input_axis_tready_next = output_axis_tready_int_early & status_ready;
output_axis_tkeep_int = ({KEEP_WIDTH{1'b1}}) >> (KEEP_WIDTH-short_counter_reg);
output_axis_tlast_int = 1'b1;
output_axis_tuser_int = last_cycle_tuser_reg;
frame_ptr_next = 16'd0;
short_counter_next = length_min;
long_counter_next = length_max;
state_next = STATE_IDLE;
end else begin
state_next = STATE_PAD;
end
end else begin
state_next = STATE_PAD;
end
end
STATE_TRUNCATE: begin
// drop after maximum length
input_axis_tready_next = output_axis_tready_int_early;
output_axis_tdata_int = last_word_data_reg;
output_axis_tkeep_int = last_word_keep_reg;
output_axis_tvalid_int = input_axis_tvalid & input_axis_tlast;
output_axis_tlast_int = input_axis_tlast;
output_axis_tuser_int = input_axis_tuser;
if (input_axis_tready & input_axis_tvalid) begin
word_cnt = 0;
for (i = 0; i <= KEEP_WIDTH; i = i + 1) begin
//bit_cnt = bit_cnt + monitor_axis_tkeep[i];
if (input_axis_tkeep == ({KEEP_WIDTH{1'b1}}) >> (KEEP_WIDTH-i)) word_cnt = i;
end
frame_ptr_next = frame_ptr_reg+KEEP_WIDTH;
if (input_axis_tlast) begin
status_valid_next = 1'b1;
status_frame_pad_next = 1'b0;
status_frame_truncate_next = 1'b1;
status_frame_length_next = length_max;
status_frame_original_length_next = frame_ptr_reg+word_cnt;
input_axis_tready_next = output_axis_tready_int_early & status_ready;
frame_ptr_next = 16'd0;
short_counter_next = length_min;
long_counter_next = length_max;
state_next = STATE_IDLE;
end else begin
state_next = STATE_TRUNCATE;
end
end else begin
state_next = STATE_TRUNCATE;
end
end
endcase
end
always @(posedge clk) begin
if (rst) begin
state_reg <= STATE_IDLE;
frame_ptr_reg <= 16'd0;
short_counter_reg <= 16'd0;
long_counter_reg <= 16'd0;
input_axis_tready_reg <= 1'b0;
status_valid_reg <= 1'b0;
end else begin
state_reg <= state_next;
frame_ptr_reg <= frame_ptr_next;
short_counter_reg <= short_counter_next;
long_counter_reg <= long_counter_next;
input_axis_tready_reg <= input_axis_tready_next;
status_valid_reg <= status_valid_next;
end
last_cycle_tuser_reg <= last_cycle_tuser_next;
status_frame_pad_reg <= status_frame_pad_next;
status_frame_truncate_reg <= status_frame_truncate_next;
status_frame_length_reg <= status_frame_length_next;
status_frame_original_length_reg <= status_frame_original_length_next;
if (store_last_word) begin
last_word_data_reg <= output_axis_tdata_int;
last_word_keep_reg <= output_axis_tkeep_int;
end
end
// output datapath logic
reg [DATA_WIDTH-1:0] output_axis_tdata_reg = {DATA_WIDTH{1'b0}};
reg [KEEP_WIDTH-1:0] output_axis_tkeep_reg = {KEEP_WIDTH{1'b0}};
reg output_axis_tvalid_reg = 1'b0, output_axis_tvalid_next;
reg output_axis_tlast_reg = 1'b0;
reg output_axis_tuser_reg = 1'b0;
reg [DATA_WIDTH-1:0] temp_axis_tdata_reg = {DATA_WIDTH{1'b0}};
reg [KEEP_WIDTH-1:0] temp_axis_tkeep_reg = {KEEP_WIDTH{1'b0}};
reg temp_axis_tvalid_reg = 1'b0, temp_axis_tvalid_next;
reg temp_axis_tlast_reg = 1'b0;
reg temp_axis_tuser_reg = 1'b0;
// datapath control
reg store_axis_int_to_output;
reg store_axis_int_to_temp;
reg store_axis_temp_to_output;
assign output_axis_tdata = output_axis_tdata_reg;
assign output_axis_tkeep = output_axis_tkeep_reg;
assign output_axis_tvalid = output_axis_tvalid_reg;
assign output_axis_tlast = output_axis_tlast_reg;
assign output_axis_tuser = output_axis_tuser_reg;
// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input)
assign output_axis_tready_int_early = output_axis_tready | (~temp_axis_tvalid_reg & (~output_axis_tvalid_reg | ~output_axis_tvalid_int));
always @* begin
// transfer sink ready state to source
output_axis_tvalid_next = output_axis_tvalid_reg;
temp_axis_tvalid_next = temp_axis_tvalid_reg;
store_axis_int_to_output = 1'b0;
store_axis_int_to_temp = 1'b0;
store_axis_temp_to_output = 1'b0;
if (output_axis_tready_int_reg) begin
// input is ready
if (output_axis_tready | ~output_axis_tvalid_reg) begin
// output is ready or currently not valid, transfer data to output
output_axis_tvalid_next = output_axis_tvalid_int;
store_axis_int_to_output = 1'b1;
end else begin
// output is not ready, store input in temp
temp_axis_tvalid_next = output_axis_tvalid_int;
store_axis_int_to_temp = 1'b1;
end
end else if (output_axis_tready) begin
// input is not ready, but output is ready
output_axis_tvalid_next = temp_axis_tvalid_reg;
temp_axis_tvalid_next = 1'b0;
store_axis_temp_to_output = 1'b1;
end
end
always @(posedge clk) begin
if (rst) begin
output_axis_tvalid_reg <= 1'b0;
output_axis_tready_int_reg <= 1'b0;
temp_axis_tvalid_reg <= 1'b0;
end else begin
output_axis_tvalid_reg <= output_axis_tvalid_next;
output_axis_tready_int_reg <= output_axis_tready_int_early;
temp_axis_tvalid_reg <= temp_axis_tvalid_next;
end
// datapath
if (store_axis_int_to_output) begin
output_axis_tdata_reg <= output_axis_tdata_int;
output_axis_tkeep_reg <= output_axis_tkeep_int;
output_axis_tlast_reg <= output_axis_tlast_int;
output_axis_tuser_reg <= output_axis_tuser_int;
end else if (store_axis_temp_to_output) begin
output_axis_tdata_reg <= temp_axis_tdata_reg;
output_axis_tkeep_reg <= temp_axis_tkeep_reg;
output_axis_tlast_reg <= temp_axis_tlast_reg;
output_axis_tuser_reg <= temp_axis_tuser_reg;
end
if (store_axis_int_to_temp) begin
temp_axis_tdata_reg <= output_axis_tdata_int;
temp_axis_tkeep_reg <= output_axis_tkeep_int;
temp_axis_tlast_reg <= output_axis_tlast_int;
temp_axis_tuser_reg <= output_axis_tuser_int;
end
end
endmodule
|
module RegFileWW(rd1data,rd2data,wrdata,rd1addr,rd2addr,wraddr,
rd1en,rd2en,wren,wrbyteen,clk);
// Definitions for the constants the advanced register file
// parameter PARAM_NAME = VALUE;
// ===============================================================
// Output signals...
/**
* Output data that's read from the 2 ports of the advanced
* register file: data from Port 1 and Port 2
*
* Stay at high impedance state if no read operation is performed
*/
output [127:0] rd1data,rd2data;
// ===============================================================
// Input signals
// Input data coming into the write port of the register file
input [0:127] wrdata;
// Clock signal to facilitate state transitions
input clk;
// Write enable signal to facilitate writing signals; active-high
input wren;
// Read enable signals for two read ports; active-high
input rd1en, rd2en;
/**
* Addresses for write and read operations
*
* wraddr must have valid output data at positive edge of the
* clock when wren is set to logic HIGH
*
* rd?addr should contain valid value when rd?en = HIGH
*/
input [4:0] wraddr, rd1addr, rd2addr;
/**
* Byte-write enable signals: one for each byte of the data
*
* Asserted high when each byte of the address word needs to be
* updated during the write operation
*/
input [15:0] wrbyteen;
// ===============================================================
// Declare "wire" signals:
//wire FSM_OUTPUT;
// ===============================================================
// Declare "reg" signals:
reg [127:0] rd1data,rd2data; // Output signals
/**
* (32 word) depth and (128 bits per word) width
*/
reg [127:0] reg_file [31:0]; // Store the data here
reg [127:0] ones; // 128-bit ones
reg [127:0] result; // ones & operand
reg [7:0] operand; // Write data to operate with
// ===============================================================
always @(posedge clk)
begin
ones=128'd0;
ones=ones-1'd1;
if(wren)
begin
if(wrbyteen==16'h1)
begin
operand=wrdata[0:7];
result = ones & operand;
reg_file[wraddr] <= result;
end
else if(wrbyteen==16'h3)
begin
operand=wrdata[8:15];
result = ones & operand;
reg_file[wraddr] <= result;
end
else if(wrbyteen==16'h7)
begin
operand=wrdata[16:23];
result = ones & operand;
reg_file[wraddr] <= result;
end
else if(wrbyteen==16'hf)
begin
operand=wrdata[24:31];
result = ones & operand;
reg_file[wraddr] <= result;
end
else if(wrbyteen==16'h1f)
begin
operand=wrdata[32:39];
result = ones & operand;
reg_file[wraddr] <= result;
end
else if(wrbyteen==16'h3f)
begin
operand=wrdata[40:47];
result = ones & operand;
reg_file[wraddr] <= result;
end
else if(wrbyteen==16'h7f)
begin
operand=wrdata[48:55];
result = ones & operand;
reg_file[wraddr] <= result;
end
else if(wrbyteen==16'hff)
begin
operand=wrdata[56:63];
result = ones & operand;
reg_file[wraddr] <= result;
end
else if(wrbyteen==16'h1ff)
begin
operand=wrdata[64:71];
result = ones & operand;
reg_file[wraddr] <= result;
end
else if(wrbyteen==16'h3ff)
begin
operand=wrdata[72:79];
result = ones & operand;
reg_file[wraddr] <= result;
end
else if(wrbyteen==16'h7ff)
begin
operand=wrdata[80:87];
result = ones & operand;
reg_file[wraddr] <= result;
end
else if(wrbyteen==16'hfff)
begin
operand=wrdata[88:95];
result = ones & operand;
reg_file[wraddr] <= result;
end
else if(wrbyteen==16'h1fff)
begin
operand=wrdata[96:103];
result = ones & operand;
reg_file[wraddr] <= result;
end
else if(wrbyteen==16'h3fff)
begin
operand=wrdata[104:111];
result = ones & operand;
reg_file[wraddr] <= result;
end
else if(wrbyteen==16'h7fff)
begin
operand=wrdata[112:119];
result = ones & operand;
reg_file[wraddr] <= result;
end
else if(wrbyteen==16'hffff)
begin
operand=wrdata[120:127];
result = ones & operand;
reg_file[wraddr] <= result;
end
end
if(rd1en && (rd1addr!==5'dx) && (rd1addr!==5'dz))
begin
rd1data<=reg_file[rd1addr];
end
else
begin
rd1data=128'dz;
end
if(rd2en && (rd2addr!==5'dx) && (rd2addr!==5'dz))
begin
rd2data<=reg_file[rd2addr];
end
else
begin
rd2data=128'dz;
end
end
endmodule
|
module sky130_fd_sc_lp__srdlstp (
Q ,
SET_B ,
D ,
GATE ,
SLEEP_B
);
output Q ;
input SET_B ;
input D ;
input GATE ;
input SLEEP_B;
// Voltage supply signals
supply1 KAPWR;
supply1 VPWR ;
supply0 VGND ;
supply1 VPB ;
supply0 VNB ;
endmodule
|
module sky130_fd_sc_lp__mux4_2 (
X ,
A0 ,
A1 ,
A2 ,
A3 ,
S0 ,
S1 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A0 ;
input A1 ;
input A2 ;
input A3 ;
input S0 ;
input S1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__mux4 base (
.X(X),
.A0(A0),
.A1(A1),
.A2(A2),
.A3(A3),
.S0(S0),
.S1(S1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
|
module sky130_fd_sc_lp__mux4_2 (
X ,
A0,
A1,
A2,
A3,
S0,
S1
);
output X ;
input A0;
input A1;
input A2;
input A3;
input S0;
input S1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__mux4 base (
.X(X),
.A0(A0),
.A1(A1),
.A2(A2),
.A3(A3),
.S0(S0),
.S1(S1)
);
endmodule
|
module sky130_fd_sc_ls__o22ai (
Y ,
A1 ,
A2 ,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire nor0_out ;
wire nor1_out ;
wire or0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
nor nor0 (nor0_out , B1, B2 );
nor nor1 (nor1_out , A1, A2 );
or or0 (or0_out_Y , nor1_out, nor0_out );
sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, or0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
|
module sky130_fd_sc_hdll__a2bb2oi (
//# {{data|Data Signals}}
input A1_N,
input A2_N,
input B1 ,
input B2 ,
output Y ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
|
module sky130_fd_sc_lp__o2bb2ai (
Y ,
A1_N,
A2_N,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A1_N;
input A2_N;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire nand0_out ;
wire or0_out ;
wire nand1_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
nand nand0 (nand0_out , A2_N, A1_N );
or or0 (or0_out , B2, B1 );
nand nand1 (nand1_out_Y , nand0_out, or0_out );
sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nand1_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
|
module linked_list_fifo(rst, clk, push, push_fifo, pop, pop_fifo, d, q, empty, full, count, almost_full, free_count, empty_check_fifo, empty_check2);
parameter WIDTH = 8;
parameter DEPTH = 32;
parameter FIFOS = 8;
parameter GEN_COUNTERS = 1;
parameter GEN_EMPTY_CHECK = 1;
parameter GEN_OVERFLOW_PROTECTION = 1;
parameter GEN_UNDERFLOW_PROTECTION = 1;
parameter LOG2_FIFOS = log2(FIFOS-1);
parameter LOG2_DEPTH = log2(DEPTH-1);
parameter FIFO_COUNT = FIFOS;
input rst;
input clk;
input push;
input [LOG2_FIFOS-1:0] push_fifo;
input pop;
input [LOG2_FIFOS-1:0] pop_fifo;
input [WIDTH-1:0] d;
output [WIDTH-1:0] q;
output empty;
output full;
//output [(LOG2_DEPTH+1)*(2**FIFOS)-1:0] count;
output [(LOG2_DEPTH)*(FIFOS)-1:0] count;
output reg almost_full;
output reg [LOG2_DEPTH:0] free_count;
input [LOG2_FIFOS - 1:0] empty_check_fifo;
output empty_check2;
wire pop_internal;
wire push_internal;
generate if(GEN_UNDERFLOW_PROTECTION) begin: gen_underflow_protection
assign pop_internal = pop && !empty;
end else begin
assign pop_internal = pop;
end endgenerate
generate if(GEN_OVERFLOW_PROTECTION) begin: gen_overflow_protection
assign push_internal = push && !full;
end else begin
assign push_internal = push;
end endgenerate
reg [LOG2_DEPTH - 1:0] count_internal [0:FIFOS - 1];
genvar g;
integer i;
generate if(GEN_COUNTERS) begin: assign_count0
for(g = 0; g < FIFOS; g = g + 1) begin: assign_count
assign count[(g+1)*LOG2_DEPTH - 1 -:LOG2_DEPTH] = count_internal[g];
end
initial for(i = 0; i < FIFOS; i = i + 1)
count_internal[i] = 0;
always @(posedge clk) begin
if(pop_internal && push_internal && push_fifo == pop_fifo) begin
end else begin
if(pop_internal)
count_internal[pop_fifo] = count_internal[pop_fifo] - 1;
if(push_internal)
count_internal[push_fifo] = count_internal[push_fifo] + 1;
end
end
end else begin
assign count = 0;
end endgenerate
reg [WIDTH-1:0] ram [DEPTH - 1:0];
reg [LOG2_DEPTH:0] linked_ram [DEPTH - 1:0];
reg ram_we;
reg [LOG2_DEPTH-1:0] ram_addr_a, ram_addr_b;
reg [WIDTH-1:0] ram_d, ram_q;
reg [LOG2_DEPTH:0] linked_ram_d;
reg [WIDTH-1:0] r_q;
reg [LOG2_DEPTH-1:0] r_beg [FIFOS-1:0];
reg [LOG2_DEPTH-1:0] r_end [FIFOS-1:0];
reg [LOG2_DEPTH-1:0] beg_next, end_next;
reg c_empty;
reg [LOG2_FIFOS-1:0] beg_ptr, end_ptr;
reg [LOG2_DEPTH:0] free, next_free;
reg beg_we, end_we;
initial for(i = 0; i < DEPTH; i = i + 1) begin
linked_ram[i] = i + 1;
end
initial for(i = 0; i < FIFOS; i = i + 1) begin
r_beg[i] = i;
r_end[i] = i;
end
initial free = FIFOS;
initial free_count = DEPTH - FIFOS;
always @(posedge clk) begin
if(pop_internal & push_internal) begin
end else if(pop_internal) begin
free_count <= free_count + 1;
end else if(push_internal) begin
free_count <= free_count - 1;
end
end
always @*
if(free_count < 2)
almost_full = 1;
else
almost_full = 0;
always @(posedge clk) begin
if(ram_we) begin
ram[ram_addr_a] <= ram_d;
end
ram_q <= ram[ram_addr_b];
end
assign q = ram_q;
always @*
ram_d = d;
always @(posedge clk) begin
if(ram_we) begin
linked_ram[ram_addr_a] <= linked_ram_d;
end
end
wire [LOG2_DEPTH:0] linked_ram_q = linked_ram[ram_addr_b];
always @(posedge clk) begin
if(beg_we)
r_beg[beg_ptr] <= beg_next;
if(end_we)
r_end[end_ptr] <= end_next;
end
wire [LOG2_DEPTH-1:0] beg_curr = r_beg[beg_ptr];
wire [LOG2_DEPTH-1:0] end_curr = r_end[end_ptr];
wire [LOG2_DEPTH-1:0] empty_check = r_end[beg_ptr];
always @* begin
if(empty_check == beg_curr)
c_empty = 1;
else
c_empty = 0;
end
assign empty = c_empty;
always @(posedge clk) begin
free <= next_free;
end
generate if(GEN_EMPTY_CHECK) begin: gen_empty_check
wire [LOG2_DEPTH-1:0] empty_check_2_beg = r_beg[empty_check_fifo];
wire [LOG2_DEPTH-1:0] empty_check_2_end = r_end[empty_check_fifo];
assign empty_check2 = empty_check_2_beg == empty_check_2_end;
end endgenerate
always @* begin
ram_we = 0;
beg_next = 0;
beg_we = 0;
end_we = 0;
end_next = 0;
beg_ptr = pop_fifo;
end_ptr = push_fifo;
next_free = free;
ram_addr_a = end_curr;
ram_addr_b = beg_curr;
linked_ram_d = 0;
if(push_internal && pop_internal) begin
ram_we = 1;
beg_we = 1;
end_we = 1;
ram_addr_a = end_curr;
linked_ram_d = beg_curr;
end_ptr = push_fifo;
beg_ptr = pop_fifo;
end_next = beg_curr;
beg_next = linked_ram_q;
ram_addr_b = beg_curr;
end else if(push_internal) begin
ram_we = 1;
end_we = 1;
ram_addr_a = end_curr;
linked_ram_d = free;
end_ptr = push_fifo;
end_next = free;
ram_addr_b = free;
next_free = linked_ram_q;
end else if(pop_internal) begin
beg_we = 1;
beg_next = linked_ram_q;
ram_addr_b = beg_curr;
ram_addr_a = beg_curr;
next_free = beg_curr;
ram_we = 1;
linked_ram_d = free;
end
end
integer error;
initial error = 0;
assign full = free[LOG2_DEPTH];
`include "log2.vh"
always @(posedge clk) begin
if(push && full) begin
$display("ERROR: Overflow at %m");
//$finish;
end
end
endmodule
|
module KeyEncoder(Columns, Rows, Clock, Reset, OnesDigit, TensDigit, Found);
input [3:0] Columns;
input [3:0] Rows;
input Clock, Reset;
output reg [3:0] OnesDigit;
output reg [3:0] TensDigit;
output reg Found;
parameter NoKey = 9'd0;
parameter key1 = 9'b100000001;
parameter key2 = 9'b100000010;
parameter key3 = 9'b100000011;
parameter key4 = 9'b100000100;
parameter key5 = 9'b100000101;
parameter key6 = 9'b100000110;
parameter key7 = 9'b100000111;
parameter key8 = 9'b100001000;
parameter key9 = 9'b100001001;
parameter keyA = 9'b100010000;
parameter keyB = 9'b100010001;
parameter keyC = 9'b100010010;
parameter keyD = 9'b100010011;
parameter keyStar = 9'b100010100;
parameter key0 = 9'b100010101;
parameter keyPound = 9'b100010110;
always@(posedge Clock or posedge Reset)
if (Reset == 1) {Found, TensDigit, OnesDigit} <= NoKey;
else case ({ Columns, Rows })
8'b01110111: {Found, TensDigit, OnesDigit} <= key1;
8'b10110111: {Found, TensDigit, OnesDigit} <= key2;
8'b11010111: {Found, TensDigit, OnesDigit} <= key3;
8'b01111011: {Found, TensDigit, OnesDigit} <= key4;
8'b10111011: {Found, TensDigit, OnesDigit} <= key5;
8'b11011011: {Found, TensDigit, OnesDigit} <= key6;
8'b01111101: {Found, TensDigit, OnesDigit} <= key7;
8'b10111101: {Found, TensDigit, OnesDigit} <= key8;
8'b11011101: {Found, TensDigit, OnesDigit} <= key9;
8'b11100111: {Found, TensDigit, OnesDigit} <= keyA;
8'b11101011: {Found, TensDigit, OnesDigit} <= keyB;
8'b11101101: {Found, TensDigit, OnesDigit} <= keyC;
8'b11101110: {Found, TensDigit, OnesDigit} <= keyD;
8'b01111110: {Found, TensDigit, OnesDigit} <= keyStar;
8'b10111110: {Found, TensDigit, OnesDigit} <= key0;
8'b11011110: {Found, TensDigit, OnesDigit} <= keyPound;
default: {Found, TensDigit, OnesDigit} <= NoKey;
endcase
endmodule
|
module agnus_copper
(
input clk, // bus clock
input clk7_en,
input reset, // system reset (synchronous)
input ecs, // enable ECS chipset features
output reqdma, // copper requests dma cycle
input ackdma, // agnus dma priority logic grants dma cycle
input enadma, // current slot is not used by any higher priority DMA channel
input sof, // start of frame input
input blit_busy, // blitter busy flag input
input [7:0] vpos, // vertical beam counter
input [8:0] hpos, // horizontal beam counter
input [15:0] data_in, // data bus input
input [8:1] reg_address_in, // register address input
output reg [8:1] reg_address_out, // register address output
output reg [20:1] address_out // chip address output
);
// register names and adresses
parameter COP1LCH = 9'h080;
parameter COP1LCL = 9'h082;
parameter COP2LCH = 9'h084;
parameter COP2LCL = 9'h086;
parameter COPCON = 9'h02e;
parameter COPINS = 9'h08c;
parameter COPJMP1 = 9'h088;
parameter COPJMP2 = 9'h08a;
// copper states
parameter RESET = 3'b000;
parameter FETCH1 = 3'b100;
parameter FETCH2 = 3'b101;
parameter WAITSKIP1 = 3'b111;
parameter WAITSKIP2 = 3'b110;
// local signals
reg [20:16] cop1lch; // copper location register 1
reg [15:1] cop1lcl; // copper location register 1
reg [20:16] cop2lch; // copper location register 2
reg [15:1] cop2lcl; // copper location register 2
reg cdang; // copper danger bit
reg [15:1] ir1; // instruction register 1
reg [15:0] ir2; // instruction register 2
reg [2:0] copper_state; // current state of copper state machine
reg [2:0] copper_next; // next state of copper state machine
reg strobe1; // strobe 1
reg strobe2; // strobe 2
reg strobe;
reg illegalreg; // illegal register (MOVE instruction)
reg skip_flag; // skip move instruction latch
reg selins; // load instruction register (register address out = COPINS)
reg selreg; // load chip register address, when both selins and selreg are active
// a dummy cycle is executed
reg skip; // skip next move instruction (input to skip_flag register)
wire enable; // enables copper fsm and dma slot
reg dma_req;
wire dma_ack;
wire dma_ena;
reg beam_match; // delayed beam match signal
wire beam_match_skip; // beam match signal for SKIP condition check
reg beam_match_wait; // beam match signal for WAIT condition chaeck
wire clk_ena; // enables every other clock cycle for chipset use
reg bus_ena; // enables CCK cycle for copper use
reg bus_blk; // bus blocked by attempting an access in the "unusable" cycle
//--------------------------------------------------------------------------------------
// since Minimig's memory bus runs twice as fast as its real Amiga counterpart
// the chipset is required to use every other memory cycle to run virtually at the same speed
assign clk_ena = hpos[0];
// horizontal counter in Agnus is advanced 4 lores pixels in comparision with the one in Denise
// if the horizontal line contains odd number of CCK cycles (short lines of NTSC mode and all lines of PAL mode)
// there is a place where two cycles usable by the copper are located back to back
// in such a situation the first cycle is not used (but locks the bus if it has a chance)
//write copper location register 1 high and low word
always @(posedge clk)
if (clk7_en) begin
if (reset)
cop1lch[20:16] <= 0;
else if (reg_address_in[8:1]==COP1LCH[8:1])
cop1lch[20:16] <= data_in[4:0];
end
always @(posedge clk)
if (clk7_en) begin
if (reset)
cop1lcl[15:1] <= 0;
else if (reg_address_in[8:1]==COP1LCL[8:1])
cop1lcl[15:1] <= data_in[15:1];
end
//write copper location register 2 high and low word
always @(posedge clk)
if (clk7_en) begin
if (reset)
cop2lch[20:16]<=0;
else if (reg_address_in[8:1]==COP2LCH[8:1])
cop2lch[20:16] <= data_in[4:0];
end
always @(posedge clk)
if (clk7_en) begin
if (reset)
cop2lcl[15:1] <= 0;
else if (reg_address_in[8:1]==COP2LCL[8:1])
cop2lcl[15:1] <= data_in[15:1];
end
//write copcon register (copper danger bit)
always @(posedge clk)
if (clk7_en) begin
if (reset)
cdang <= 0;
else if (reg_address_in[8:1]==COPCON[8:1])
cdang <= data_in[1];
end
//copper instruction registers ir1 and ir2
always @(posedge clk)
if (clk7_en) begin
if (reg_address_in[8:1]==COPINS[8:1])
begin
ir1[15:1] <= ir2[15:1];
ir2[15:0] <= data_in[15:0];
end
end
//--------------------------------------------------------------------------------------
//chip address pointer (or copper program counter) controller
always @(posedge clk)
if (clk7_en) begin
if (dma_ack && strobe1 && copper_state==RESET)//load pointer with location register 1
address_out[20:1] <= {cop1lch[20:16],cop1lcl[15:1]};
else if (dma_ack && strobe2 && copper_state==RESET)//load pointer with location register 2
address_out[20:1] <= {cop2lch[20:16],cop2lcl[15:1]};
else if (dma_ack && (selins || selreg))//increment address pointer (when not dummy cycle)
address_out[20:1] <= address_out[20:1] + 1'b1;
end
//--------------------------------------------------------------------------------------
// regaddress output select
// if selins=1 the address of the copper instruction register
// is sent out (not strictly necessary as we can load copins directly. However, this is
// more according to what happens in a real amiga... I think), else the contents of
// ir2[8:1] is selected
// (if you ask yourself: IR2? is this a bug? then check how ir1/ir2 are loaded in this design)
always @(*)
if (enable & selins) //load our instruction register
reg_address_out[8:1] = COPINS[8:1];
else if (enable & selreg)//load register in move instruction
reg_address_out[8:1] = ir2[8:1];
else
reg_address_out[8:1] = 8'hFF;//during dummy cycle null register address is present
// detect illegal register access
// CDANG = 0 (OCS/ECS) : $080-$1FE allowed
// CDANG = 1 (OCS) : $040-$1FE allowed
// CDANG = 1 (ECS) : $000-$1FE allowed
always @(*)
if (ir2[8:7]==2'b00 && !cdang || ir2[8:6]==3'b000 && !ecs) // illegal access
illegalreg = 1'b1;
else // $080 -> $1FE always allowed
illegalreg = 1'b0;
//--------------------------------------------------------------------------------------
reg copjmp1, copjmp2;
always @(posedge clk)
if (clk7_en) begin
if (reg_address_in[8:1]==COPJMP1[8:1] || sof)
copjmp1 = 1;
else if (clk_ena)
copjmp1 = 0;
end
always @(posedge clk)
if (clk7_en) begin
if (reg_address_in[8:1]==COPJMP2[8:1])
copjmp2 = 1;
else if (clk_ena)
copjmp2 = 0;
end
//strobe1 (also triggered by sof, start of frame)
always @(posedge clk)
if (clk7_en) begin
if (copjmp1 && clk_ena)
strobe1 = 1;
else if (copper_state==RESET && dma_ack)
strobe1 = 0;
end
//strobe2
always @(posedge clk)
if (clk7_en) begin
if (copjmp2 && clk_ena)
strobe2 = 1;
else if (copper_state==RESET && dma_ack)
strobe2 = 0;
end
always @(posedge clk)
if (clk7_en) begin
if (clk_ena)
strobe = copjmp1 | copjmp2;
end
//--------------------------------------------------------------------------------------
//beam compare circuitry
//when the mask for a compare bit is 1, the beamcounter is compared with that bit,
//when the mask is 0, the compare bit is replaced with the corresponding beamcounter bit
//itself, thus the compare is always true.
//the blitter busy flag is also checked if blitter finished disable is false
wire [8:2] horcmp;
wire [7:0] vercmp;
//construct compare value for horizontal beam counter (4 lores pixels resolution)
assign horcmp[2] = (ir2[1]) ? ir1[1] : hpos[2];
assign horcmp[3] = (ir2[2]) ? ir1[2] : hpos[3];
assign horcmp[4] = (ir2[3]) ? ir1[3] : hpos[4];
assign horcmp[5] = (ir2[4]) ? ir1[4] : hpos[5];
assign horcmp[6] = (ir2[5]) ? ir1[5] : hpos[6];
assign horcmp[7] = (ir2[6]) ? ir1[6] : hpos[7];
assign horcmp[8] = (ir2[7]) ? ir1[7] : hpos[8];
//construct compare value for vertical beam counter (1 line resolution)
assign vercmp[0] = (ir2[8]) ? ir1[8] : vpos[0];
assign vercmp[1] = (ir2[9]) ? ir1[9] : vpos[1];
assign vercmp[2] = (ir2[10]) ? ir1[10] : vpos[2];
assign vercmp[3] = (ir2[11]) ? ir1[11] : vpos[3];
assign vercmp[4] = (ir2[12]) ? ir1[12] : vpos[4];
assign vercmp[5] = (ir2[13]) ? ir1[13] : vpos[5];
assign vercmp[6] = (ir2[14]) ? ir1[14] : vpos[6];
assign vercmp[7] = ir1[15];
// actual beam position comparator
always @(posedge clk)
if (clk7_en) begin
if (clk_ena)
if ({vpos[7:0],hpos[8:2]} >= {vercmp[7:0],horcmp[8:2]})
beam_match <= 1'b1;
else
beam_match <= 1'b0;
end
assign beam_match_skip = beam_match & (ir2[15] | ~blit_busy);
always @(posedge clk)
if (clk7_en) begin
if (clk_ena)
beam_match_wait <= beam_match_skip;
end
//--------------------------------------------------------------------------------------
/*
WAIT: first cycle after fetch of second instruction word is a cycle when comparision with beam counter takes place
this comparision is beeing done all the time regardless of the available DMA slot
when the comparision condition is safisfied the FSM goes to wait_wake_up state,
it stays in this state as long as display DMA takes the DMA slots
when display DMA doesn't use even bus cycle the FSM advances to the fetch state (the slot isn't used by the copper, DBR is deasserted)
such a behaviour is caused by dma request pipelining in real Agnus
*/
//--------------------------------------------------------------------------------------
//generate dma request signal (reqdma)
//copper only uses even cycles: hpos[1:0]==2'b01)
//the last cycle of the short line is not usable by the copper
//in PAL mode when the copper wants to access memory bus in cycle $E1 the DBR is activated
//(blocks the blitter and CPU) but actual transfer takes place in the next cycle (DBR still asserted)
always @(posedge clk)
if (clk7_en) begin
if (clk_ena)
if (hpos[8:1]==8'h01)
bus_blk <= 1; //cycle $E1 is blocked
else
bus_blk <= 0;
end
always @(posedge clk)
if (clk7_en) begin
if (clk_ena)
if (bus_blk)
bus_ena <= 1; //cycle $E2 is usable
else
bus_ena <= ~bus_ena;
end
assign enable = ~bus_blk & bus_ena & clk_ena;
assign reqdma = dma_req & bus_ena & clk_ena; //dma is request also during $E1 but output register address is idle
assign dma_ack = ackdma & enable; //dma ack is masked during $E1
assign dma_ena = enadma; //dma slot is empty and can be used by copper
//hint: during vblank copper instruction pointer is reloaded just after the first refresh slot
//there is at least 2 CCK delay between writing COPJMPx register and pointer reload
//copper state machine and skip_flag latch
always @(posedge clk)
if (clk7_en) begin
if (reset || clk_ena && strobe) // on strobe or reset fetch first instruction word
copper_state <= RESET;
else if (enable) // go to next state
copper_state <= copper_next;
end
always @(posedge clk)
if (clk7_en) begin
if (enable)
skip_flag <= skip;
end
always @(*)//(copper_state or ir2 or beam_match_wait or beam_match_skip or illegalreg or skip_flag or dma_ack or dma_ena)
begin
case (copper_state)
//when COPJMPx is written there is 2 cycle delay before data from new location is read to COPINS
//usually first cycle is a read of the next instruction to COPINS or bitplane DMA,
//the second is dma free cycle (it's a dummy cycle requested by copper but not used to transfer data)
//after reset or strobe write an allocated DMA cycle is required to reload instruction pointer from location registers
RESET:
begin
skip = 0;
selins = 0;
selreg = 0;
dma_req = 1; //a DMA access is requested to reload instuction pointer
if (dma_ack)
copper_next = FETCH1;
else
copper_next = RESET;
end
//fetch first instruction word
FETCH1:
begin
skip = skip_flag;
selins = 1;
selreg = 0;
dma_req = 1;
if (dma_ack)
copper_next = FETCH2;
else
copper_next = FETCH1;
end
//fetch second instruction word, skip or do MOVE instruction or halt copper
FETCH2:
begin
if (!ir2[0] && illegalreg) // illegal MOVE instruction, halt copper
begin
skip = 0;
selins = 0;
selreg = 0;
dma_req = 0;
copper_next = FETCH2;
end
else if (!ir2[0] && skip_flag) // skip this MOVE instruction
begin
selins = 1;
selreg = 0;
dma_req = 1;
if (dma_ack)
begin
skip = 0;
copper_next = FETCH1;
end
else
begin
skip = 1;
copper_next = FETCH2;
end
end
else if (!ir2[0]) // MOVE instruction
begin
skip = 0;
selins = 0;
selreg = 1;
dma_req = 1;
if (dma_ack)
copper_next = FETCH1;
else
copper_next = FETCH2;
end
else//fetch second instruction word of WAIT or SKIP instruction
begin
skip = 0;
selins = 1;
selreg = 0;
dma_req = 1;
if (dma_ack)
copper_next = WAITSKIP1;
else
copper_next = FETCH2;
end
end
//both SKIP and WAIT have the same timing when WAIT is immediatelly complete
//both these instructions complete in 4 cycles and these cycles must be allocated dma cycles
//first cycle seems to be dummy
WAITSKIP1:
begin
skip = 0;
selins = 0;
selreg = 0;
dma_req = 0;
if (dma_ena)
copper_next = WAITSKIP2;
else
copper_next = WAITSKIP1;
end
//second cycle of WAIT or SKIP (allocated dma)
//WAIT or SKIP instruction
WAITSKIP2:
begin
if (!ir2[0]) // WAIT instruction
begin
if (beam_match_wait) // wait is over, fetch next instruction
begin
skip = 0;
selins = 0;
selreg = 0;
dma_req = 0;
if (dma_ena)
copper_next = FETCH1;
else
copper_next = WAITSKIP2;
end
else//still waiting
begin
skip = 0;
selins = 0;
selreg = 0;
dma_req = 0;
copper_next = WAITSKIP2;
end
end
else // SKIP instruction
begin
if (beam_match_skip) // compare is true, fetch next instruction and skip it if it's MOVE
begin
skip = 1;
selins = 0;
selreg = 0;
dma_req = 0;
if (dma_ena)
copper_next = FETCH1;
else
copper_next = WAITSKIP2;
end
else//do not skip, fetch next instruction
begin
skip = 0;
selins = 0;
selreg = 0;
dma_req = 0;
if (dma_ena)
copper_next = FETCH1;
else
copper_next = WAITSKIP2;
end
end
end
//default, go back to reset state
default:
begin
skip = 0;
selins = 0;
selreg = 0;
dma_req = 0;
copper_next = FETCH1;
end
endcase
end
//--------------------------------------------------------------------------------------
endmodule
|
module tb_mkmif();
//----------------------------------------------------------------
// Internal constant and parameter definitions.
//----------------------------------------------------------------
parameter DEBUG = 1;
parameter CLK_HALF_PERIOD = 2;
parameter CLK_PERIOD = 2 * CLK_HALF_PERIOD;
localparam ADDR_NAME0 = 8'h00;
localparam ADDR_NAME1 = 8'h01;
localparam ADDR_VERSION = 8'h02;
localparam ADDR_CTRL = 8'h08;
localparam ADDR_STATUS = 8'h09;
localparam ADDR_CONFIG = 8'h0a;
localparam ADDR_EMEM_ADDR = 8'h10;
localparam ADDR_EMEM_DATA = 8'h20;
localparam CORE_NAME0 = 32'h6d6b6d69; // "mkmi"
localparam CORE_NAME1 = 32'h66202020; // "f "
localparam CORE_VERSION = 32'h302e3130; // "0.10"
//----------------------------------------------------------------
// Register and Wire declarations.
//----------------------------------------------------------------
reg [31 : 0] cycle_ctr;
reg [31 : 0] test_ctr;
reg [31 : 0] error_ctr;
reg tb_clk;
reg tb_reset_n;
wire tb_spi_sclk;
wire tb_spi_cs_n;
reg tb_spi_do;
wire tb_spi_di;
reg tb_cs;
reg tb_we;
reg [7 : 0] tb_address;
reg [31 : 0] tb_write_data;
wire [31 : 0] tb_read_data;
reg tb_dump_state;
wire tb_error;
reg [31 : 0] read_data;
//----------------------------------------------------------------
// mkmif device under test.
//----------------------------------------------------------------
mkmif dut(
.clk(tb_clk),
.reset_n(tb_reset_n),
.spi_sclk(tb_spi_sclk),
.spi_cs_n(tb_spi_cs_n),
.spi_do(tb_spi_di),
.spi_di(tb_spi_di),
.cs(tb_cs),
.we(tb_we),
.address(tb_address),
.write_data(tb_write_data),
.read_data(tb_read_data)
);
//----------------------------------------------------------------
// clk_gen
// Clock generator process.
//----------------------------------------------------------------
always
begin : clk_gen
#CLK_HALF_PERIOD tb_clk = !tb_clk;
end // clk_gen
//--------------------------------------------------------------------
// dut_monitor
// Monitor for observing the inputs and outputs to the dut.
// Includes the cycle counter.
//--------------------------------------------------------------------
always @ (posedge tb_clk)
begin : dut_monitor
cycle_ctr = cycle_ctr + 1;
if (DEBUG)
$display("cycle = %8x:", cycle_ctr);
if (tb_dump_state)
dump_state();
end // dut_monitor
//----------------------------------------------------------------
// inc_test_ctr
//----------------------------------------------------------------
task inc_test_ctr;
begin
test_ctr = test_ctr +1;
end
endtask // inc_test_ctr
//----------------------------------------------------------------
// inc_error_ctr
//----------------------------------------------------------------
task inc_error_ctr;
begin
error_ctr = error_ctr +1;
end
endtask // inc_error_ctr
//----------------------------------------------------------------
// dump_state
// Dump the internal MKMIF state to std out.
//----------------------------------------------------------------
task dump_state;
begin
$display("mkmif_core_ctrl_reg: 0x%02x, core ready: 0x%01x, core valid: 0x%01x",
dut.core.mkmif_ctrl_reg, dut.core_ready, dut.core_valid);
$display("sclk: 0x%01x, cs_n: 0x%01x, di: 0x%01x, do: 0x%01x, nxt: 0x%01x",
tb_spi_sclk, tb_spi_cs_n, tb_spi_di, tb_spi_do, dut.core.spi.data_nxt);
$display("spi_ctrl_reg: 0x%01x, spi_clk_ctr: 0x%04x, spi_bit_ctr: 0x%02x",
dut.core.spi.spi_ctrl_reg, dut.core.spi.clk_ctr_reg, dut.core.spi.bit_ctr_reg);
$display("spi length: 0x%02x, spi divisor: 0x%04x, spi set: 0x%01x, spi start: 0x%01x, spi ready: 0x%01x",
dut.core.spi.length_reg, dut.core.spi.divisor_reg, dut.core.spi.set, dut.core.spi.start, dut.core.spi.ready);
$display("read data: 0x%08x, write_data: 0x%014x", dut.core.spi.rd_data, dut.core.spi.wr_data);
$display("spi data reg: 0x%014x", dut.core.spi.data_reg);
$display("");
end
endtask // dump_state
//----------------------------------------------------------------
// tb_init
// Initialize varibles, dut inputs at start.
//----------------------------------------------------------------
task tb_init;
begin
test_ctr = 0;
error_ctr = 0;
cycle_ctr = 0;
tb_clk = 0;
tb_reset_n = 1;
tb_spi_do = 0;
tb_cs = 1'b0;
tb_we = 1'b0;
tb_address = 8'h00;
tb_write_data = 32'h00;
tb_dump_state = 1;
end
endtask // tb_init
//----------------------------------------------------------------
// toggle_reset
// Toggle the reset.
//----------------------------------------------------------------
task toggle_reset;
begin
$display(" --- Toggling reset started.");
dump_state();
#(2 * CLK_PERIOD);
tb_reset_n = 0;
#(10 * CLK_PERIOD);
@(negedge tb_clk)
tb_reset_n = 1;
dump_state();
$display(" --- Toggling of reset done.");
$display("");
end
endtask // toggle_reset
//----------------------------------------------------------------
// read_word()
//
// Read a data word from the given address in the DUT.
// the word read will be available in the global variable
// read_data.
//----------------------------------------------------------------
task read_word(input [7 : 0] address);
begin
tb_address = address;
tb_cs = 1;
tb_we = 0;
#(CLK_PERIOD);
read_data = tb_read_data;
tb_cs = 0;
if (DEBUG)
begin
$display("*** Reading 0x%08x from 0x%02x.", read_data, address);
$display("");
end
end
endtask // read_word
//----------------------------------------------------------------
// write_word()
//
// Write the given word to the DUT using the DUT interface.
//----------------------------------------------------------------
task write_word(input [7 : 0] address,
input [31 : 0] word);
begin
if (DEBUG)
begin
$display("*** Writing 0x%08x to 0x%02x.", word, address);
$display("");
end
tb_address = address;
tb_write_data = word;
tb_cs = 1;
tb_we = 1;
#(CLK_PERIOD);
tb_cs = 0;
tb_we = 0;
end
endtask // write_word
//----------------------------------------------------------------
// wait_ready()
//
// Wait for ready word to be set in the DUT API.
//----------------------------------------------------------------
task wait_ready;
reg ready;
begin
ready = 0;
while (ready == 0)
begin
read_word(ADDR_STATUS);
ready = read_data & 32'h00000001;
end
end
endtask // read_word
//----------------------------------------------------------------
// check_name_version()
//
// Read the name and version from the DUT.
//----------------------------------------------------------------
task check_name_version;
reg [31 : 0] name0;
reg [31 : 0] name1;
reg [31 : 0] version;
begin
inc_test_ctr();
$display(" -- Test of reading name and version started.");
read_word(ADDR_NAME0);
name0 = read_data;
read_word(ADDR_NAME1);
name1 = read_data;
read_word(ADDR_VERSION);
version = read_data;
if ((name0 == CORE_NAME0) && (name1 == CORE_NAME1) && (version == CORE_VERSION))
$display("Correct name and version read from dut.");
else
begin
inc_error_ctr();
$display("Error:");
$display("Got name: %c%c%c%c%c%c%c%c",
name0[31 : 24], name0[23 : 16], name0[15 : 8], name0[7 : 0],
name1[31 : 24], name1[23 : 16], name1[15 : 8], name1[7 : 0]);
$display("Expected name: %c%c%c%c%c%c%c%c",
CORE_NAME0[31 : 24], CORE_NAME0[23 : 16], CORE_NAME0[15 : 8], CORE_NAME0[7 : 0],
CORE_NAME1[31 : 24], CORE_NAME1[23 : 16], CORE_NAME1[15 : 8], CORE_NAME1[7 : 0]);
$display("Got version: %c%c%c%c",
version[31 : 24], version[23 : 16], version[15 : 8], version[7 : 0]);
$display("Expected version: %c%c%c%c",
CORE_VERSION[31 : 24], CORE_VERSION[23 : 16], CORE_VERSION[15 : 8], CORE_VERSION[7 : 0]);
$display(" -- Test of reading name and version done.");
$display("");
end
end
endtask // check_name_version
//----------------------------------------------------------------
// write_test
//
// Try to write a few words of data.
//----------------------------------------------------------------
task write_test;
begin
inc_test_ctr();
$display(" -- Test of writing words to the memory started.");
wait_ready();
$display("Ready has been set. Starting write commands.");
write_word(ADDR_EMEM_ADDR, 16'h0010);
write_word(ADDR_EMEM_DATA, 32'hdeadbeef);
write_word(ADDR_CTRL, 32'h2);
#(10 * CLK_PERIOD);
wait_ready();
read_word(ADDR_EMEM_DATA);
$display("First write completed. Read: 0x%08x", read_data);
write_word(ADDR_EMEM_ADDR, 16'h0020);
write_word(ADDR_EMEM_DATA, 32'haa55aa55);
write_word(ADDR_CTRL, 32'h2);
#(10 * CLK_PERIOD);
wait_ready();
read_word(ADDR_EMEM_DATA);
$display("Second write completed. Read: 0x%08x", read_data);
// write_word(ADDR_EMEM_ADDR, 16'h0100);
// write_word(ADDR_EMEM_DATA, 32'h004488ff);
// write_word(ADDR_CTRL, 32'h2);
// #(1000 * CLK_PERIOD);
// wait_ready();
$display(" -- Test of writing words to the memory done.");
$display("");
end
endtask // write_test
//----------------------------------------------------------------
// read_test
//
// Try to read a few words of data.
//----------------------------------------------------------------
task read_test;
begin
inc_test_ctr();
$display(" -- Test of reading from the memory started.");
// wait_ready();
// $display("Ready has been set. Starting write commands.");
// write_word(ADDR_EMEM_ADDR, 16'h0010);
// write_word(ADDR_EMEM_DATA, 32'hdeadbeef);
// write_word(ADDR_CTRL, 32'h2);
// #(1000 * CLK_PERIOD);
// wait_ready();
// write_word(ADDR_EMEM_ADDR, 16'h0020);
// write_word(ADDR_EMEM_DATA, 32'haa55aa55);
// write_word(ADDR_CTRL, 32'h2);
// #(1000 * CLK_PERIOD);
// wait_ready();
//
// write_word(ADDR_EMEM_ADDR, 16'h0100);
// write_word(ADDR_EMEM_DATA, 32'h004488ff);
// write_word(ADDR_CTRL, 32'h2);
// #(1000 * CLK_PERIOD);
// wait_ready();
$display(" -- Test of reading from the memory done.");
$display("");
end
endtask // read_test
//----------------------------------------------------------------
// mkmif_test
// The main test functionality.
//----------------------------------------------------------------
initial
begin : mkmif_test
$display(" --*** Test of mkmif started ***--");
tb_init();
toggle_reset();
check_name_version();
write_test();
read_test();
$display("");
$display(" --*** Test of mkmif completed ***--");
$display("Tests executed: %04d", test_ctr);
$display("Tests failed: %04d", error_ctr);
$finish;
end // mkmif_test
endmodule
|
module outputs
wire [23 : 0] flash_addr;
wire [15 : 0] user_response_get;
wire RDY_user_request_put,
RDY_user_response_get,
RDY_user_waitBit,
flash_adv_n,
flash_ce_n,
flash_oe_n,
flash_rst_n,
flash_we_n,
flash_wp_n,
user_waitBit;
// inlined wires
wire rseqFsm_abort_wget,
rseqFsm_abort_whas,
rseqFsm_start_reg_2_wget,
rseqFsm_start_reg_2_whas,
rseqFsm_start_wire_wget,
rseqFsm_start_wire_whas,
rseqFsm_state_fired_1_wget,
rseqFsm_state_fired_1_whas,
rseqFsm_state_overlap_pw_whas,
rseqFsm_state_set_pw_whas,
wseqFsm_abort_wget,
wseqFsm_abort_whas,
wseqFsm_start_reg_2_wget,
wseqFsm_start_reg_2_whas,
wseqFsm_start_wire_wget,
wseqFsm_start_wire_whas,
wseqFsm_state_fired_1_wget,
wseqFsm_state_fired_1_whas,
wseqFsm_state_overlap_pw_whas,
wseqFsm_state_set_pw_whas;
// register aReg
reg [23 : 0] aReg;
wire [23 : 0] aReg_D_IN;
wire aReg_EN;
// register ceReg
reg ceReg;
wire ceReg_D_IN, ceReg_EN;
// register isRead
reg isRead;
wire isRead_D_IN, isRead_EN;
// register oeReg
reg oeReg;
wire oeReg_D_IN, oeReg_EN;
// register rseqFsm_jj_delay_count
reg [14 : 0] rseqFsm_jj_delay_count;
wire [14 : 0] rseqFsm_jj_delay_count_D_IN;
wire rseqFsm_jj_delay_count_EN;
// register rseqFsm_start_reg
reg rseqFsm_start_reg;
wire rseqFsm_start_reg_D_IN, rseqFsm_start_reg_EN;
// register rseqFsm_start_reg_1
reg rseqFsm_start_reg_1;
wire rseqFsm_start_reg_1_D_IN, rseqFsm_start_reg_1_EN;
// register rseqFsm_state_can_overlap
reg rseqFsm_state_can_overlap;
wire rseqFsm_state_can_overlap_D_IN, rseqFsm_state_can_overlap_EN;
// register rseqFsm_state_fired
reg rseqFsm_state_fired;
wire rseqFsm_state_fired_D_IN, rseqFsm_state_fired_EN;
// register rseqFsm_state_mkFSMstate
reg [3 : 0] rseqFsm_state_mkFSMstate;
reg [3 : 0] rseqFsm_state_mkFSMstate_D_IN;
wire rseqFsm_state_mkFSMstate_EN;
// register tmpWD
reg [15 : 0] tmpWD;
wire [15 : 0] tmpWD_D_IN;
wire tmpWD_EN;
// register tsOE
reg tsOE;
wire tsOE_D_IN, tsOE_EN;
// register tsWD
reg [15 : 0] tsWD;
wire [15 : 0] tsWD_D_IN;
wire tsWD_EN;
// register waitReg
reg waitReg;
wire waitReg_D_IN, waitReg_EN;
// register wdReg
reg [15 : 0] wdReg;
wire [15 : 0] wdReg_D_IN;
wire wdReg_EN;
// register weReg
reg weReg;
wire weReg_D_IN, weReg_EN;
// register wseqFsm_jj_1_delay_count
reg [6 : 0] wseqFsm_jj_1_delay_count;
wire [6 : 0] wseqFsm_jj_1_delay_count_D_IN;
wire wseqFsm_jj_1_delay_count_EN;
// register wseqFsm_jj_2_delay_count
reg [6 : 0] wseqFsm_jj_2_delay_count;
wire [6 : 0] wseqFsm_jj_2_delay_count_D_IN;
wire wseqFsm_jj_2_delay_count_EN;
// register wseqFsm_jj_delay_count
reg [6 : 0] wseqFsm_jj_delay_count;
wire [6 : 0] wseqFsm_jj_delay_count_D_IN;
wire wseqFsm_jj_delay_count_EN;
// register wseqFsm_start_reg
reg wseqFsm_start_reg;
wire wseqFsm_start_reg_D_IN, wseqFsm_start_reg_EN;
// register wseqFsm_start_reg_1
reg wseqFsm_start_reg_1;
wire wseqFsm_start_reg_1_D_IN, wseqFsm_start_reg_1_EN;
// register wseqFsm_state_can_overlap
reg wseqFsm_state_can_overlap;
wire wseqFsm_state_can_overlap_D_IN, wseqFsm_state_can_overlap_EN;
// register wseqFsm_state_fired
reg wseqFsm_state_fired;
wire wseqFsm_state_fired_D_IN, wseqFsm_state_fired_EN;
// register wseqFsm_state_mkFSMstate
reg [4 : 0] wseqFsm_state_mkFSMstate;
reg [4 : 0] wseqFsm_state_mkFSMstate_D_IN;
wire wseqFsm_state_mkFSMstate_EN;
// ports of submodule reqF
wire [40 : 0] reqF_D_IN, reqF_D_OUT;
wire reqF_CLR, reqF_DEQ, reqF_EMPTY_N, reqF_ENQ, reqF_FULL_N;
// ports of submodule respF
wire [15 : 0] respF_D_IN, respF_D_OUT;
wire respF_CLR, respF_DEQ, respF_EMPTY_N, respF_ENQ, respF_FULL_N;
// ports of submodule tsd
wire [15 : 0] tsd_IO, tsd_O;
// rule scheduling signals
wire WILL_FIRE_RL_nextRequest,
WILL_FIRE_RL_rseqFsm_action_d_init_np,
WILL_FIRE_RL_rseqFsm_action_l60c12,
WILL_FIRE_RL_rseqFsm_action_l61c12,
WILL_FIRE_RL_rseqFsm_action_l63c10,
WILL_FIRE_RL_rseqFsm_action_l64c12,
WILL_FIRE_RL_rseqFsm_action_l65c12,
WILL_FIRE_RL_rseqFsm_action_np,
WILL_FIRE_RL_rseqFsm_fsm_start,
WILL_FIRE_RL_rseqFsm_idle_l59c15,
WILL_FIRE_RL_wseqFsm_action_d_init_np,
WILL_FIRE_RL_wseqFsm_action_d_init_np_1,
WILL_FIRE_RL_wseqFsm_action_d_init_np_2,
WILL_FIRE_RL_wseqFsm_action_l70c12,
WILL_FIRE_RL_wseqFsm_action_l71c12,
WILL_FIRE_RL_wseqFsm_action_l72c12,
WILL_FIRE_RL_wseqFsm_action_l73c12,
WILL_FIRE_RL_wseqFsm_action_l75c12,
WILL_FIRE_RL_wseqFsm_action_l76c12,
WILL_FIRE_RL_wseqFsm_action_l78c12,
WILL_FIRE_RL_wseqFsm_action_l79c12,
WILL_FIRE_RL_wseqFsm_action_l80c12,
WILL_FIRE_RL_wseqFsm_action_l82c12,
WILL_FIRE_RL_wseqFsm_action_l83c12,
WILL_FIRE_RL_wseqFsm_action_l84c12,
WILL_FIRE_RL_wseqFsm_action_l87c12,
WILL_FIRE_RL_wseqFsm_action_l88c12,
WILL_FIRE_RL_wseqFsm_action_l90c12,
WILL_FIRE_RL_wseqFsm_action_l91c12,
WILL_FIRE_RL_wseqFsm_action_np,
WILL_FIRE_RL_wseqFsm_action_np_1,
WILL_FIRE_RL_wseqFsm_action_np_2,
WILL_FIRE_RL_wseqFsm_action_np_3,
WILL_FIRE_RL_wseqFsm_action_np_4,
WILL_FIRE_RL_wseqFsm_fsm_start,
WILL_FIRE_RL_wseqFsm_idle_l69c15;
// inputs to muxes for submodule ports
wire [14 : 0] MUX_rseqFsm_jj_delay_count_write_1__VAL_1;
wire [6 : 0] MUX_wseqFsm_jj_1_delay_count_write_1__VAL_1,
MUX_wseqFsm_jj_2_delay_count_write_1__VAL_1,
MUX_wseqFsm_jj_delay_count_write_1__VAL_1;
wire MUX_ceReg_write_1__SEL_1,
MUX_oeReg_write_1__SEL_1,
MUX_rseqFsm_start_reg_write_1__SEL_1,
MUX_weReg_write_1__SEL_1,
MUX_wseqFsm_start_reg_write_1__SEL_1;
// remaining internal signals
wire IF_reqF_first__11_BIT_40_12_THEN_rseqFsm_abort_ETC___d217,
rseqFsm_abort_whas_AND_rseqFsm_abort_wget_OR_r_ETC___d71,
wseqFsm_abort_whas__7_AND_wseqFsm_abort_wget___ETC___d207;
// value method flash_addr
assign flash_addr = aReg ;
// value method flash_ce_n
assign flash_ce_n = !ceReg ;
// value method flash_oe_n
assign flash_oe_n = !oeReg ;
// value method flash_we_n
assign flash_we_n = !weReg ;
// value method flash_wp_n
assign flash_wp_n = 1'd1 ;
// value method flash_rst_n
assign flash_rst_n = 1'd1 ;
// value method flash_adv_n
assign flash_adv_n = 1'd0 ;
// action method user_request_put
assign RDY_user_request_put = reqF_FULL_N ;
// actionvalue method user_response_get
assign user_response_get = respF_D_OUT ;
assign RDY_user_response_get = respF_EMPTY_N ;
// value method user_waitBit
assign user_waitBit = waitReg ;
assign RDY_user_waitBit = 1'd1 ;
// submodule reqF
FIFO2 #(.width(32'd41), .guarded(32'd1)) reqF(.RST(RST_N),
.CLK(CLK),
.D_IN(reqF_D_IN),
.ENQ(reqF_ENQ),
.DEQ(reqF_DEQ),
.CLR(reqF_CLR),
.D_OUT(reqF_D_OUT),
.FULL_N(reqF_FULL_N),
.EMPTY_N(reqF_EMPTY_N));
// submodule respF
FIFO2 #(.width(32'd16), .guarded(32'd1)) respF(.RST(RST_N),
.CLK(CLK),
.D_IN(respF_D_IN),
.ENQ(respF_ENQ),
.DEQ(respF_DEQ),
.CLR(respF_CLR),
.D_OUT(respF_D_OUT),
.FULL_N(respF_FULL_N),
.EMPTY_N(respF_EMPTY_N));
// submodule tsd
TriState #(.width(32'd16)) tsd(.I(tsWD), .OE(tsOE), .O(tsd_O), .IO(tsd_IO));
// rule RL_rseqFsm_action_l61c12
assign WILL_FIRE_RL_rseqFsm_action_l61c12 =
isRead && rseqFsm_state_mkFSMstate == 4'd1 ;
// rule RL_rseqFsm_action_d_init_np
assign WILL_FIRE_RL_rseqFsm_action_d_init_np =
isRead && rseqFsm_state_mkFSMstate == 4'd2 ;
// rule RL_rseqFsm_action_np
assign WILL_FIRE_RL_rseqFsm_action_np =
isRead && !rseqFsm_jj_delay_count[14] &&
(rseqFsm_state_mkFSMstate == 4'd3 ||
rseqFsm_state_mkFSMstate == 4'd4) ;
// rule RL_rseqFsm_action_l63c10
assign WILL_FIRE_RL_rseqFsm_action_l63c10 =
respF_FULL_N && isRead && rseqFsm_jj_delay_count[14] &&
(rseqFsm_state_mkFSMstate == 4'd3 ||
rseqFsm_state_mkFSMstate == 4'd4) ;
// rule RL_rseqFsm_action_l64c12
assign WILL_FIRE_RL_rseqFsm_action_l64c12 =
isRead && rseqFsm_state_mkFSMstate == 4'd5 ;
// rule RL_rseqFsm_action_l65c12
assign WILL_FIRE_RL_rseqFsm_action_l65c12 =
isRead && rseqFsm_state_mkFSMstate == 4'd6 ;
// rule RL_rseqFsm_fsm_start
assign WILL_FIRE_RL_rseqFsm_fsm_start =
rseqFsm_abort_whas_AND_rseqFsm_abort_wget_OR_r_ETC___d71 &&
rseqFsm_start_reg ;
// rule RL_rseqFsm_action_l60c12
assign WILL_FIRE_RL_rseqFsm_action_l60c12 =
isRead && rseqFsm_start_wire_whas &&
(rseqFsm_state_mkFSMstate == 4'd0 ||
rseqFsm_state_mkFSMstate == 4'd7) ;
// rule RL_rseqFsm_idle_l59c15
assign WILL_FIRE_RL_rseqFsm_idle_l59c15 =
!rseqFsm_start_wire_whas && rseqFsm_state_mkFSMstate == 4'd7 ;
// rule RL_wseqFsm_action_l71c12
assign WILL_FIRE_RL_wseqFsm_action_l71c12 =
!isRead && wseqFsm_state_mkFSMstate == 5'd1 ;
// rule RL_wseqFsm_action_l72c12
assign WILL_FIRE_RL_wseqFsm_action_l72c12 =
!isRead && wseqFsm_state_mkFSMstate == 5'd2 ;
// rule RL_wseqFsm_action_l73c12
assign WILL_FIRE_RL_wseqFsm_action_l73c12 =
!isRead && wseqFsm_state_mkFSMstate == 5'd3 ;
// rule RL_wseqFsm_action_d_init_np
assign WILL_FIRE_RL_wseqFsm_action_d_init_np =
!isRead && wseqFsm_state_mkFSMstate == 5'd4 ;
// rule RL_wseqFsm_action_np
assign WILL_FIRE_RL_wseqFsm_action_np =
!isRead && !wseqFsm_jj_delay_count[6] &&
(wseqFsm_state_mkFSMstate == 5'd5 ||
wseqFsm_state_mkFSMstate == 5'd6) ;
// rule RL_wseqFsm_action_l75c12
assign WILL_FIRE_RL_wseqFsm_action_l75c12 =
!isRead && wseqFsm_jj_delay_count[6] &&
(wseqFsm_state_mkFSMstate == 5'd5 ||
wseqFsm_state_mkFSMstate == 5'd6) ;
// rule RL_wseqFsm_action_l76c12
assign WILL_FIRE_RL_wseqFsm_action_l76c12 =
!isRead && wseqFsm_state_mkFSMstate == 5'd7 ;
// rule RL_wseqFsm_action_np_1
assign WILL_FIRE_RL_wseqFsm_action_np_1 =
!isRead && wseqFsm_state_mkFSMstate == 5'd8 ;
// rule RL_wseqFsm_action_l78c12
assign WILL_FIRE_RL_wseqFsm_action_l78c12 =
!isRead && wseqFsm_state_mkFSMstate == 5'd9 ;
// rule RL_wseqFsm_action_l79c12
assign WILL_FIRE_RL_wseqFsm_action_l79c12 =
!isRead && wseqFsm_state_mkFSMstate == 5'd10 ;
// rule RL_wseqFsm_action_l80c12
assign WILL_FIRE_RL_wseqFsm_action_l80c12 =
!isRead && wseqFsm_state_mkFSMstate == 5'd11 ;
// rule RL_wseqFsm_action_d_init_np_1
assign WILL_FIRE_RL_wseqFsm_action_d_init_np_1 =
!isRead && wseqFsm_state_mkFSMstate == 5'd12 ;
// rule RL_wseqFsm_action_np_2
assign WILL_FIRE_RL_wseqFsm_action_np_2 =
!isRead && !wseqFsm_jj_1_delay_count[6] &&
(wseqFsm_state_mkFSMstate == 5'd13 ||
wseqFsm_state_mkFSMstate == 5'd14) ;
// rule RL_wseqFsm_action_l82c12
assign WILL_FIRE_RL_wseqFsm_action_l82c12 =
!isRead && wseqFsm_jj_1_delay_count[6] &&
(wseqFsm_state_mkFSMstate == 5'd13 ||
wseqFsm_state_mkFSMstate == 5'd14) ;
// rule RL_wseqFsm_action_l83c12
assign WILL_FIRE_RL_wseqFsm_action_l83c12 =
!isRead && wseqFsm_state_mkFSMstate == 5'd15 ;
// rule RL_wseqFsm_action_l84c12
assign WILL_FIRE_RL_wseqFsm_action_l84c12 =
!isRead && wseqFsm_state_mkFSMstate == 5'd16 ;
// rule RL_wseqFsm_action_np_3
assign WILL_FIRE_RL_wseqFsm_action_np_3 =
!isRead && wseqFsm_state_mkFSMstate == 5'd17 ;
// rule RL_wseqFsm_action_l87c12
assign WILL_FIRE_RL_wseqFsm_action_l87c12 =
!isRead && wseqFsm_state_mkFSMstate == 5'd18 ;
// rule RL_wseqFsm_action_l88c12
assign WILL_FIRE_RL_wseqFsm_action_l88c12 =
!isRead && wseqFsm_state_mkFSMstate == 5'd19 ;
// rule RL_wseqFsm_action_d_init_np_2
assign WILL_FIRE_RL_wseqFsm_action_d_init_np_2 =
!isRead && wseqFsm_state_mkFSMstate == 5'd20 ;
// rule RL_wseqFsm_action_np_4
assign WILL_FIRE_RL_wseqFsm_action_np_4 =
!isRead && !wseqFsm_jj_2_delay_count[6] &&
(wseqFsm_state_mkFSMstate == 5'd21 ||
wseqFsm_state_mkFSMstate == 5'd22) ;
// rule RL_wseqFsm_action_l90c12
assign WILL_FIRE_RL_wseqFsm_action_l90c12 =
!isRead && wseqFsm_jj_2_delay_count[6] &&
(wseqFsm_state_mkFSMstate == 5'd21 ||
wseqFsm_state_mkFSMstate == 5'd22) ;
// rule RL_wseqFsm_action_l91c12
assign WILL_FIRE_RL_wseqFsm_action_l91c12 =
!isRead && wseqFsm_state_mkFSMstate == 5'd23 ;
// rule RL_wseqFsm_fsm_start
assign WILL_FIRE_RL_wseqFsm_fsm_start =
wseqFsm_abort_whas__7_AND_wseqFsm_abort_wget___ETC___d207 &&
wseqFsm_start_reg ;
// rule RL_wseqFsm_action_l70c12
assign WILL_FIRE_RL_wseqFsm_action_l70c12 =
!isRead && wseqFsm_start_wire_whas &&
(wseqFsm_state_mkFSMstate == 5'd0 ||
wseqFsm_state_mkFSMstate == 5'd24) ;
// rule RL_nextRequest
assign WILL_FIRE_RL_nextRequest =
reqF_EMPTY_N &&
IF_reqF_first__11_BIT_40_12_THEN_rseqFsm_abort_ETC___d217 &&
rseqFsm_abort_whas_AND_rseqFsm_abort_wget_OR_r_ETC___d71 &&
!rseqFsm_start_reg &&
wseqFsm_abort_whas__7_AND_wseqFsm_abort_wget___ETC___d207 &&
!wseqFsm_start_reg ;
// rule RL_wseqFsm_idle_l69c15
assign WILL_FIRE_RL_wseqFsm_idle_l69c15 =
!wseqFsm_start_wire_whas && wseqFsm_state_mkFSMstate == 5'd24 ;
// inputs to muxes for submodule ports
assign MUX_ceReg_write_1__SEL_1 =
WILL_FIRE_RL_wseqFsm_action_l91c12 ||
WILL_FIRE_RL_wseqFsm_action_l83c12 ||
WILL_FIRE_RL_wseqFsm_action_l76c12 ||
WILL_FIRE_RL_rseqFsm_action_l65c12 ;
assign MUX_oeReg_write_1__SEL_1 =
WILL_FIRE_RL_wseqFsm_action_l90c12 ||
WILL_FIRE_RL_rseqFsm_action_l64c12 ;
assign MUX_rseqFsm_start_reg_write_1__SEL_1 =
WILL_FIRE_RL_nextRequest && reqF_D_OUT[40] ;
assign MUX_weReg_write_1__SEL_1 =
WILL_FIRE_RL_wseqFsm_action_l82c12 ||
WILL_FIRE_RL_wseqFsm_action_l75c12 ;
assign MUX_wseqFsm_start_reg_write_1__SEL_1 =
WILL_FIRE_RL_nextRequest && !reqF_D_OUT[40] ;
assign MUX_rseqFsm_jj_delay_count_write_1__VAL_1 =
{ rseqFsm_jj_delay_count[13:0], 1'd0 } ;
assign MUX_wseqFsm_jj_1_delay_count_write_1__VAL_1 =
{ wseqFsm_jj_1_delay_count[5:0], 1'd0 } ;
assign MUX_wseqFsm_jj_2_delay_count_write_1__VAL_1 =
{ wseqFsm_jj_2_delay_count[5:0], 1'd0 } ;
assign MUX_wseqFsm_jj_delay_count_write_1__VAL_1 =
{ wseqFsm_jj_delay_count[5:0], 1'd0 } ;
// inlined wires
assign rseqFsm_start_wire_wget = 1'd1 ;
assign rseqFsm_start_wire_whas =
WILL_FIRE_RL_rseqFsm_fsm_start ||
rseqFsm_start_reg_1 && !rseqFsm_state_fired ;
assign rseqFsm_start_reg_2_wget = 1'd1 ;
assign rseqFsm_start_reg_2_whas = rseqFsm_start_wire_whas ;
assign rseqFsm_abort_wget = 1'b0 ;
assign rseqFsm_abort_whas = 1'b0 ;
assign rseqFsm_state_fired_1_wget = 1'd1 ;
assign rseqFsm_state_fired_1_whas = rseqFsm_state_set_pw_whas ;
assign wseqFsm_start_wire_wget = 1'd1 ;
assign wseqFsm_start_wire_whas =
WILL_FIRE_RL_wseqFsm_fsm_start ||
wseqFsm_start_reg_1 && !wseqFsm_state_fired ;
assign wseqFsm_start_reg_2_wget = 1'd1 ;
assign wseqFsm_start_reg_2_whas = wseqFsm_start_wire_whas ;
assign wseqFsm_abort_wget = 1'b0 ;
assign wseqFsm_abort_whas = 1'b0 ;
assign wseqFsm_state_fired_1_wget = 1'd1 ;
assign wseqFsm_state_fired_1_whas = wseqFsm_state_set_pw_whas ;
assign rseqFsm_state_set_pw_whas =
WILL_FIRE_RL_rseqFsm_idle_l59c15 ||
WILL_FIRE_RL_rseqFsm_action_l65c12 ||
WILL_FIRE_RL_rseqFsm_action_l64c12 ||
WILL_FIRE_RL_rseqFsm_action_l63c10 ||
WILL_FIRE_RL_rseqFsm_action_np ||
WILL_FIRE_RL_rseqFsm_action_d_init_np ||
WILL_FIRE_RL_rseqFsm_action_l61c12 ||
WILL_FIRE_RL_rseqFsm_action_l60c12 ;
assign rseqFsm_state_overlap_pw_whas = 1'b0 ;
assign wseqFsm_state_set_pw_whas =
WILL_FIRE_RL_wseqFsm_idle_l69c15 ||
WILL_FIRE_RL_wseqFsm_action_l91c12 ||
WILL_FIRE_RL_wseqFsm_action_l90c12 ||
WILL_FIRE_RL_wseqFsm_action_np_4 ||
WILL_FIRE_RL_wseqFsm_action_d_init_np_2 ||
WILL_FIRE_RL_wseqFsm_action_l88c12 ||
WILL_FIRE_RL_wseqFsm_action_l87c12 ||
WILL_FIRE_RL_wseqFsm_action_np_3 ||
WILL_FIRE_RL_wseqFsm_action_l84c12 ||
WILL_FIRE_RL_wseqFsm_action_l83c12 ||
WILL_FIRE_RL_wseqFsm_action_l82c12 ||
WILL_FIRE_RL_wseqFsm_action_np_2 ||
WILL_FIRE_RL_wseqFsm_action_d_init_np_1 ||
WILL_FIRE_RL_wseqFsm_action_l80c12 ||
WILL_FIRE_RL_wseqFsm_action_l79c12 ||
WILL_FIRE_RL_wseqFsm_action_l78c12 ||
WILL_FIRE_RL_wseqFsm_action_np_1 ||
WILL_FIRE_RL_wseqFsm_action_l76c12 ||
WILL_FIRE_RL_wseqFsm_action_l75c12 ||
WILL_FIRE_RL_wseqFsm_action_np ||
WILL_FIRE_RL_wseqFsm_action_d_init_np ||
WILL_FIRE_RL_wseqFsm_action_l73c12 ||
WILL_FIRE_RL_wseqFsm_action_l72c12 ||
WILL_FIRE_RL_wseqFsm_action_l71c12 ||
WILL_FIRE_RL_wseqFsm_action_l70c12 ;
assign wseqFsm_state_overlap_pw_whas = 1'b0 ;
// register aReg
assign aReg_D_IN = reqF_D_OUT[39:16] ;
assign aReg_EN = WILL_FIRE_RL_nextRequest ;
// register ceReg
assign ceReg_D_IN = !MUX_ceReg_write_1__SEL_1 ;
assign ceReg_EN =
WILL_FIRE_RL_wseqFsm_action_l91c12 ||
WILL_FIRE_RL_wseqFsm_action_l83c12 ||
WILL_FIRE_RL_wseqFsm_action_l76c12 ||
WILL_FIRE_RL_rseqFsm_action_l65c12 ||
WILL_FIRE_RL_wseqFsm_action_l87c12 ||
WILL_FIRE_RL_wseqFsm_action_l79c12 ||
WILL_FIRE_RL_wseqFsm_action_l71c12 ||
WILL_FIRE_RL_rseqFsm_action_l60c12 ;
// register isRead
assign isRead_D_IN = reqF_D_OUT[40] ;
assign isRead_EN = WILL_FIRE_RL_nextRequest ;
// register oeReg
assign oeReg_D_IN = !MUX_oeReg_write_1__SEL_1 ;
assign oeReg_EN =
WILL_FIRE_RL_wseqFsm_action_l90c12 ||
WILL_FIRE_RL_rseqFsm_action_l64c12 ||
WILL_FIRE_RL_wseqFsm_action_l88c12 ||
WILL_FIRE_RL_rseqFsm_action_l61c12 ;
// register rseqFsm_jj_delay_count
assign rseqFsm_jj_delay_count_D_IN =
WILL_FIRE_RL_rseqFsm_action_np ?
MUX_rseqFsm_jj_delay_count_write_1__VAL_1 :
15'd1 ;
assign rseqFsm_jj_delay_count_EN =
WILL_FIRE_RL_rseqFsm_action_np ||
WILL_FIRE_RL_rseqFsm_action_d_init_np ;
// register rseqFsm_start_reg
assign rseqFsm_start_reg_D_IN = MUX_rseqFsm_start_reg_write_1__SEL_1 ;
assign rseqFsm_start_reg_EN =
WILL_FIRE_RL_nextRequest && reqF_D_OUT[40] ||
WILL_FIRE_RL_rseqFsm_fsm_start ;
// register rseqFsm_start_reg_1
assign rseqFsm_start_reg_1_D_IN = rseqFsm_start_wire_whas ;
assign rseqFsm_start_reg_1_EN = 1'd1 ;
// register rseqFsm_state_can_overlap
assign rseqFsm_state_can_overlap_D_IN =
rseqFsm_state_set_pw_whas || rseqFsm_state_can_overlap ;
assign rseqFsm_state_can_overlap_EN = 1'd1 ;
// register rseqFsm_state_fired
assign rseqFsm_state_fired_D_IN = rseqFsm_state_set_pw_whas ;
assign rseqFsm_state_fired_EN = 1'd1 ;
// register rseqFsm_state_mkFSMstate
always@(WILL_FIRE_RL_rseqFsm_idle_l59c15 or
WILL_FIRE_RL_rseqFsm_action_l60c12 or
WILL_FIRE_RL_rseqFsm_action_l61c12 or
WILL_FIRE_RL_rseqFsm_action_d_init_np or
WILL_FIRE_RL_rseqFsm_action_np or
WILL_FIRE_RL_rseqFsm_action_l63c10 or
WILL_FIRE_RL_rseqFsm_action_l64c12 or
WILL_FIRE_RL_rseqFsm_action_l65c12)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_rseqFsm_idle_l59c15: rseqFsm_state_mkFSMstate_D_IN = 4'd0;
WILL_FIRE_RL_rseqFsm_action_l60c12:
rseqFsm_state_mkFSMstate_D_IN = 4'd1;
WILL_FIRE_RL_rseqFsm_action_l61c12:
rseqFsm_state_mkFSMstate_D_IN = 4'd2;
WILL_FIRE_RL_rseqFsm_action_d_init_np:
rseqFsm_state_mkFSMstate_D_IN = 4'd3;
WILL_FIRE_RL_rseqFsm_action_np: rseqFsm_state_mkFSMstate_D_IN = 4'd4;
WILL_FIRE_RL_rseqFsm_action_l63c10:
rseqFsm_state_mkFSMstate_D_IN = 4'd5;
WILL_FIRE_RL_rseqFsm_action_l64c12:
rseqFsm_state_mkFSMstate_D_IN = 4'd6;
WILL_FIRE_RL_rseqFsm_action_l65c12:
rseqFsm_state_mkFSMstate_D_IN = 4'd7;
default: rseqFsm_state_mkFSMstate_D_IN =
4'b1010 /* unspecified value */ ;
endcase
end
assign rseqFsm_state_mkFSMstate_EN =
WILL_FIRE_RL_rseqFsm_idle_l59c15 ||
WILL_FIRE_RL_rseqFsm_action_l60c12 ||
WILL_FIRE_RL_rseqFsm_action_l61c12 ||
WILL_FIRE_RL_rseqFsm_action_d_init_np ||
WILL_FIRE_RL_rseqFsm_action_np ||
WILL_FIRE_RL_rseqFsm_action_l63c10 ||
WILL_FIRE_RL_rseqFsm_action_l64c12 ||
WILL_FIRE_RL_rseqFsm_action_l65c12 ;
// register tmpWD
assign tmpWD_D_IN = reqF_D_OUT[15:0] ;
assign tmpWD_EN = WILL_FIRE_RL_nextRequest ;
// register tsOE
assign tsOE_D_IN = !WILL_FIRE_RL_wseqFsm_action_l84c12 ;
assign tsOE_EN =
WILL_FIRE_RL_wseqFsm_action_l84c12 ||
WILL_FIRE_RL_wseqFsm_action_l72c12 ;
// register tsWD
assign tsWD_D_IN = WILL_FIRE_RL_wseqFsm_action_l78c12 ? tmpWD : 16'd64 ;
assign tsWD_EN =
WILL_FIRE_RL_wseqFsm_action_l78c12 ||
WILL_FIRE_RL_wseqFsm_action_l70c12 ;
// register waitReg
assign waitReg_D_IN = flash_fwait_i ;
assign waitReg_EN = 1'd1 ;
// register wdReg
assign wdReg_D_IN = 16'h0 ;
assign wdReg_EN = 1'b0 ;
// register weReg
assign weReg_D_IN = !MUX_weReg_write_1__SEL_1 ;
assign weReg_EN =
WILL_FIRE_RL_wseqFsm_action_l82c12 ||
WILL_FIRE_RL_wseqFsm_action_l75c12 ||
WILL_FIRE_RL_wseqFsm_action_l80c12 ||
WILL_FIRE_RL_wseqFsm_action_l73c12 ;
// register wseqFsm_jj_1_delay_count
assign wseqFsm_jj_1_delay_count_D_IN =
WILL_FIRE_RL_wseqFsm_action_np_2 ?
MUX_wseqFsm_jj_1_delay_count_write_1__VAL_1 :
7'd1 ;
assign wseqFsm_jj_1_delay_count_EN =
WILL_FIRE_RL_wseqFsm_action_np_2 ||
WILL_FIRE_RL_wseqFsm_action_d_init_np_1 ;
// register wseqFsm_jj_2_delay_count
assign wseqFsm_jj_2_delay_count_D_IN =
WILL_FIRE_RL_wseqFsm_action_np_4 ?
MUX_wseqFsm_jj_2_delay_count_write_1__VAL_1 :
7'd1 ;
assign wseqFsm_jj_2_delay_count_EN =
WILL_FIRE_RL_wseqFsm_action_np_4 ||
WILL_FIRE_RL_wseqFsm_action_d_init_np_2 ;
// register wseqFsm_jj_delay_count
assign wseqFsm_jj_delay_count_D_IN =
WILL_FIRE_RL_wseqFsm_action_np ?
MUX_wseqFsm_jj_delay_count_write_1__VAL_1 :
7'd1 ;
assign wseqFsm_jj_delay_count_EN =
WILL_FIRE_RL_wseqFsm_action_np ||
WILL_FIRE_RL_wseqFsm_action_d_init_np ;
// register wseqFsm_start_reg
assign wseqFsm_start_reg_D_IN = MUX_wseqFsm_start_reg_write_1__SEL_1 ;
assign wseqFsm_start_reg_EN =
WILL_FIRE_RL_nextRequest && !reqF_D_OUT[40] ||
WILL_FIRE_RL_wseqFsm_fsm_start ;
// register wseqFsm_start_reg_1
assign wseqFsm_start_reg_1_D_IN = wseqFsm_start_wire_whas ;
assign wseqFsm_start_reg_1_EN = 1'd1 ;
// register wseqFsm_state_can_overlap
assign wseqFsm_state_can_overlap_D_IN =
wseqFsm_state_set_pw_whas || wseqFsm_state_can_overlap ;
assign wseqFsm_state_can_overlap_EN = 1'd1 ;
// register wseqFsm_state_fired
assign wseqFsm_state_fired_D_IN = wseqFsm_state_set_pw_whas ;
assign wseqFsm_state_fired_EN = 1'd1 ;
// register wseqFsm_state_mkFSMstate
always@(WILL_FIRE_RL_wseqFsm_idle_l69c15 or
WILL_FIRE_RL_wseqFsm_action_l70c12 or
WILL_FIRE_RL_wseqFsm_action_l71c12 or
WILL_FIRE_RL_wseqFsm_action_l72c12 or
WILL_FIRE_RL_wseqFsm_action_l73c12 or
WILL_FIRE_RL_wseqFsm_action_d_init_np or
WILL_FIRE_RL_wseqFsm_action_np or
WILL_FIRE_RL_wseqFsm_action_l75c12 or
WILL_FIRE_RL_wseqFsm_action_l76c12 or
WILL_FIRE_RL_wseqFsm_action_np_1 or
WILL_FIRE_RL_wseqFsm_action_l78c12 or
WILL_FIRE_RL_wseqFsm_action_l79c12 or
WILL_FIRE_RL_wseqFsm_action_l80c12 or
WILL_FIRE_RL_wseqFsm_action_d_init_np_1 or
WILL_FIRE_RL_wseqFsm_action_np_2 or
WILL_FIRE_RL_wseqFsm_action_l82c12 or
WILL_FIRE_RL_wseqFsm_action_l83c12 or
WILL_FIRE_RL_wseqFsm_action_l84c12 or
WILL_FIRE_RL_wseqFsm_action_np_3 or
WILL_FIRE_RL_wseqFsm_action_l87c12 or
WILL_FIRE_RL_wseqFsm_action_l88c12 or
WILL_FIRE_RL_wseqFsm_action_d_init_np_2 or
WILL_FIRE_RL_wseqFsm_action_np_4 or
WILL_FIRE_RL_wseqFsm_action_l90c12 or
WILL_FIRE_RL_wseqFsm_action_l91c12)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_wseqFsm_idle_l69c15: wseqFsm_state_mkFSMstate_D_IN = 5'd0;
WILL_FIRE_RL_wseqFsm_action_l70c12:
wseqFsm_state_mkFSMstate_D_IN = 5'd1;
WILL_FIRE_RL_wseqFsm_action_l71c12:
wseqFsm_state_mkFSMstate_D_IN = 5'd2;
WILL_FIRE_RL_wseqFsm_action_l72c12:
wseqFsm_state_mkFSMstate_D_IN = 5'd3;
WILL_FIRE_RL_wseqFsm_action_l73c12:
wseqFsm_state_mkFSMstate_D_IN = 5'd4;
WILL_FIRE_RL_wseqFsm_action_d_init_np:
wseqFsm_state_mkFSMstate_D_IN = 5'd5;
WILL_FIRE_RL_wseqFsm_action_np: wseqFsm_state_mkFSMstate_D_IN = 5'd6;
WILL_FIRE_RL_wseqFsm_action_l75c12:
wseqFsm_state_mkFSMstate_D_IN = 5'd7;
WILL_FIRE_RL_wseqFsm_action_l76c12:
wseqFsm_state_mkFSMstate_D_IN = 5'd8;
WILL_FIRE_RL_wseqFsm_action_np_1: wseqFsm_state_mkFSMstate_D_IN = 5'd9;
WILL_FIRE_RL_wseqFsm_action_l78c12:
wseqFsm_state_mkFSMstate_D_IN = 5'd10;
WILL_FIRE_RL_wseqFsm_action_l79c12:
wseqFsm_state_mkFSMstate_D_IN = 5'd11;
WILL_FIRE_RL_wseqFsm_action_l80c12:
wseqFsm_state_mkFSMstate_D_IN = 5'd12;
WILL_FIRE_RL_wseqFsm_action_d_init_np_1:
wseqFsm_state_mkFSMstate_D_IN = 5'd13;
WILL_FIRE_RL_wseqFsm_action_np_2: wseqFsm_state_mkFSMstate_D_IN = 5'd14;
WILL_FIRE_RL_wseqFsm_action_l82c12:
wseqFsm_state_mkFSMstate_D_IN = 5'd15;
WILL_FIRE_RL_wseqFsm_action_l83c12:
wseqFsm_state_mkFSMstate_D_IN = 5'd16;
WILL_FIRE_RL_wseqFsm_action_l84c12:
wseqFsm_state_mkFSMstate_D_IN = 5'd17;
WILL_FIRE_RL_wseqFsm_action_np_3: wseqFsm_state_mkFSMstate_D_IN = 5'd18;
WILL_FIRE_RL_wseqFsm_action_l87c12:
wseqFsm_state_mkFSMstate_D_IN = 5'd19;
WILL_FIRE_RL_wseqFsm_action_l88c12:
wseqFsm_state_mkFSMstate_D_IN = 5'd20;
WILL_FIRE_RL_wseqFsm_action_d_init_np_2:
wseqFsm_state_mkFSMstate_D_IN = 5'd21;
WILL_FIRE_RL_wseqFsm_action_np_4: wseqFsm_state_mkFSMstate_D_IN = 5'd22;
WILL_FIRE_RL_wseqFsm_action_l90c12:
wseqFsm_state_mkFSMstate_D_IN = 5'd23;
WILL_FIRE_RL_wseqFsm_action_l91c12:
wseqFsm_state_mkFSMstate_D_IN = 5'd24;
default: wseqFsm_state_mkFSMstate_D_IN =
5'b01010 /* unspecified value */ ;
endcase
end
assign wseqFsm_state_mkFSMstate_EN =
WILL_FIRE_RL_wseqFsm_idle_l69c15 ||
WILL_FIRE_RL_wseqFsm_action_l70c12 ||
WILL_FIRE_RL_wseqFsm_action_l71c12 ||
WILL_FIRE_RL_wseqFsm_action_l72c12 ||
WILL_FIRE_RL_wseqFsm_action_l73c12 ||
WILL_FIRE_RL_wseqFsm_action_d_init_np ||
WILL_FIRE_RL_wseqFsm_action_np ||
WILL_FIRE_RL_wseqFsm_action_l75c12 ||
WILL_FIRE_RL_wseqFsm_action_l76c12 ||
WILL_FIRE_RL_wseqFsm_action_np_1 ||
WILL_FIRE_RL_wseqFsm_action_l78c12 ||
WILL_FIRE_RL_wseqFsm_action_l79c12 ||
WILL_FIRE_RL_wseqFsm_action_l80c12 ||
WILL_FIRE_RL_wseqFsm_action_d_init_np_1 ||
WILL_FIRE_RL_wseqFsm_action_np_2 ||
WILL_FIRE_RL_wseqFsm_action_l82c12 ||
WILL_FIRE_RL_wseqFsm_action_l83c12 ||
WILL_FIRE_RL_wseqFsm_action_l84c12 ||
WILL_FIRE_RL_wseqFsm_action_np_3 ||
WILL_FIRE_RL_wseqFsm_action_l87c12 ||
WILL_FIRE_RL_wseqFsm_action_l88c12 ||
WILL_FIRE_RL_wseqFsm_action_d_init_np_2 ||
WILL_FIRE_RL_wseqFsm_action_np_4 ||
WILL_FIRE_RL_wseqFsm_action_l90c12 ||
WILL_FIRE_RL_wseqFsm_action_l91c12 ;
// submodule reqF
assign reqF_D_IN = user_request_put ;
assign reqF_ENQ = EN_user_request_put ;
assign reqF_DEQ = WILL_FIRE_RL_nextRequest ;
assign reqF_CLR = 1'b0 ;
// submodule respF
assign respF_D_IN = tsd_O ;
assign respF_ENQ = WILL_FIRE_RL_rseqFsm_action_l63c10 ;
assign respF_DEQ = EN_user_response_get ;
assign respF_CLR = 1'b0 ;
// remaining internal signals
assign IF_reqF_first__11_BIT_40_12_THEN_rseqFsm_abort_ETC___d217 =
reqF_D_OUT[40] ?
rseqFsm_abort_whas_AND_rseqFsm_abort_wget_OR_r_ETC___d71 &&
!rseqFsm_start_reg :
wseqFsm_abort_whas__7_AND_wseqFsm_abort_wget___ETC___d207 &&
!wseqFsm_start_reg ;
assign rseqFsm_abort_whas_AND_rseqFsm_abort_wget_OR_r_ETC___d71 =
(rseqFsm_state_mkFSMstate == 4'd0 ||
rseqFsm_state_mkFSMstate == 4'd7) &&
(!rseqFsm_start_reg_1 || rseqFsm_state_fired) ;
assign wseqFsm_abort_whas__7_AND_wseqFsm_abort_wget___ETC___d207 =
(wseqFsm_state_mkFSMstate == 5'd0 ||
wseqFsm_state_mkFSMstate == 5'd24) &&
(!wseqFsm_start_reg_1 || wseqFsm_state_fired) ;
// handling of inlined registers
always@(posedge CLK)
begin
if (RST_N == `BSV_RESET_VALUE)
begin
aReg <= `BSV_ASSIGNMENT_DELAY 24'd0;
ceReg <= `BSV_ASSIGNMENT_DELAY 1'd0;
isRead <= `BSV_ASSIGNMENT_DELAY 1'd1;
oeReg <= `BSV_ASSIGNMENT_DELAY 1'd0;
rseqFsm_jj_delay_count <= `BSV_ASSIGNMENT_DELAY 15'd1;
rseqFsm_start_reg <= `BSV_ASSIGNMENT_DELAY 1'd0;
rseqFsm_start_reg_1 <= `BSV_ASSIGNMENT_DELAY 1'd0;
rseqFsm_state_can_overlap <= `BSV_ASSIGNMENT_DELAY 1'd1;
rseqFsm_state_fired <= `BSV_ASSIGNMENT_DELAY 1'd0;
rseqFsm_state_mkFSMstate <= `BSV_ASSIGNMENT_DELAY 4'd0;
tmpWD <= `BSV_ASSIGNMENT_DELAY 16'd0;
tsOE <= `BSV_ASSIGNMENT_DELAY 1'd0;
tsWD <= `BSV_ASSIGNMENT_DELAY 16'd0;
wdReg <= `BSV_ASSIGNMENT_DELAY 16'd0;
weReg <= `BSV_ASSIGNMENT_DELAY 1'd0;
wseqFsm_jj_1_delay_count <= `BSV_ASSIGNMENT_DELAY 7'd1;
wseqFsm_jj_2_delay_count <= `BSV_ASSIGNMENT_DELAY 7'd1;
wseqFsm_jj_delay_count <= `BSV_ASSIGNMENT_DELAY 7'd1;
wseqFsm_start_reg <= `BSV_ASSIGNMENT_DELAY 1'd0;
wseqFsm_start_reg_1 <= `BSV_ASSIGNMENT_DELAY 1'd0;
wseqFsm_state_can_overlap <= `BSV_ASSIGNMENT_DELAY 1'd1;
wseqFsm_state_fired <= `BSV_ASSIGNMENT_DELAY 1'd0;
wseqFsm_state_mkFSMstate <= `BSV_ASSIGNMENT_DELAY 5'd0;
end
else
begin
if (aReg_EN) aReg <= `BSV_ASSIGNMENT_DELAY aReg_D_IN;
if (ceReg_EN) ceReg <= `BSV_ASSIGNMENT_DELAY ceReg_D_IN;
if (isRead_EN) isRead <= `BSV_ASSIGNMENT_DELAY isRead_D_IN;
if (oeReg_EN) oeReg <= `BSV_ASSIGNMENT_DELAY oeReg_D_IN;
if (rseqFsm_jj_delay_count_EN)
rseqFsm_jj_delay_count <= `BSV_ASSIGNMENT_DELAY
rseqFsm_jj_delay_count_D_IN;
if (rseqFsm_start_reg_EN)
rseqFsm_start_reg <= `BSV_ASSIGNMENT_DELAY rseqFsm_start_reg_D_IN;
if (rseqFsm_start_reg_1_EN)
rseqFsm_start_reg_1 <= `BSV_ASSIGNMENT_DELAY
rseqFsm_start_reg_1_D_IN;
if (rseqFsm_state_can_overlap_EN)
rseqFsm_state_can_overlap <= `BSV_ASSIGNMENT_DELAY
rseqFsm_state_can_overlap_D_IN;
if (rseqFsm_state_fired_EN)
rseqFsm_state_fired <= `BSV_ASSIGNMENT_DELAY
rseqFsm_state_fired_D_IN;
if (rseqFsm_state_mkFSMstate_EN)
rseqFsm_state_mkFSMstate <= `BSV_ASSIGNMENT_DELAY
rseqFsm_state_mkFSMstate_D_IN;
if (tmpWD_EN) tmpWD <= `BSV_ASSIGNMENT_DELAY tmpWD_D_IN;
if (tsOE_EN) tsOE <= `BSV_ASSIGNMENT_DELAY tsOE_D_IN;
if (tsWD_EN) tsWD <= `BSV_ASSIGNMENT_DELAY tsWD_D_IN;
if (wdReg_EN) wdReg <= `BSV_ASSIGNMENT_DELAY wdReg_D_IN;
if (weReg_EN) weReg <= `BSV_ASSIGNMENT_DELAY weReg_D_IN;
if (wseqFsm_jj_1_delay_count_EN)
wseqFsm_jj_1_delay_count <= `BSV_ASSIGNMENT_DELAY
wseqFsm_jj_1_delay_count_D_IN;
if (wseqFsm_jj_2_delay_count_EN)
wseqFsm_jj_2_delay_count <= `BSV_ASSIGNMENT_DELAY
wseqFsm_jj_2_delay_count_D_IN;
if (wseqFsm_jj_delay_count_EN)
wseqFsm_jj_delay_count <= `BSV_ASSIGNMENT_DELAY
wseqFsm_jj_delay_count_D_IN;
if (wseqFsm_start_reg_EN)
wseqFsm_start_reg <= `BSV_ASSIGNMENT_DELAY wseqFsm_start_reg_D_IN;
if (wseqFsm_start_reg_1_EN)
wseqFsm_start_reg_1 <= `BSV_ASSIGNMENT_DELAY
wseqFsm_start_reg_1_D_IN;
if (wseqFsm_state_can_overlap_EN)
wseqFsm_state_can_overlap <= `BSV_ASSIGNMENT_DELAY
wseqFsm_state_can_overlap_D_IN;
if (wseqFsm_state_fired_EN)
wseqFsm_state_fired <= `BSV_ASSIGNMENT_DELAY
wseqFsm_state_fired_D_IN;
if (wseqFsm_state_mkFSMstate_EN)
wseqFsm_state_mkFSMstate <= `BSV_ASSIGNMENT_DELAY
wseqFsm_state_mkFSMstate_D_IN;
end
if (waitReg_EN) waitReg <= `BSV_ASSIGNMENT_DELAY waitReg_D_IN;
end
// synopsys translate_off
`ifdef BSV_NO_INITIAL_BLOCKS
`else // not BSV_NO_INITIAL_BLOCKS
initial
begin
aReg = 24'hAAAAAA;
ceReg = 1'h0;
isRead = 1'h0;
oeReg = 1'h0;
rseqFsm_jj_delay_count = 15'h2AAA;
rseqFsm_start_reg = 1'h0;
rseqFsm_start_reg_1 = 1'h0;
rseqFsm_state_can_overlap = 1'h0;
rseqFsm_state_fired = 1'h0;
rseqFsm_state_mkFSMstate = 4'hA;
tmpWD = 16'hAAAA;
tsOE = 1'h0;
tsWD = 16'hAAAA;
waitReg = 1'h0;
wdReg = 16'hAAAA;
weReg = 1'h0;
wseqFsm_jj_1_delay_count = 7'h2A;
wseqFsm_jj_2_delay_count = 7'h2A;
wseqFsm_jj_delay_count = 7'h2A;
wseqFsm_start_reg = 1'h0;
wseqFsm_start_reg_1 = 1'h0;
wseqFsm_state_can_overlap = 1'h0;
wseqFsm_state_fired = 1'h0;
wseqFsm_state_mkFSMstate = 5'h0A;
end
`endif // BSV_NO_INITIAL_BLOCKS
// synopsys translate_on
// handling of system tasks
// synopsys translate_off
always@(negedge CLK)
begin
#0;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rseqFsm_action_l61c12 &&
(WILL_FIRE_RL_rseqFsm_action_d_init_np ||
WILL_FIRE_RL_rseqFsm_action_np ||
WILL_FIRE_RL_rseqFsm_action_l63c10 ||
WILL_FIRE_RL_rseqFsm_action_l64c12 ||
WILL_FIRE_RL_rseqFsm_action_l65c12))
$display("Error: \"bsv/dev/Flash.bsv\", line 61, column 12: (R0001)\n Mutually exclusive rules (from the ME sets [RL_rseqFsm_action_l61c12] and\n [RL_rseqFsm_action_d_init_np, RL_rseqFsm_action_np,\n RL_rseqFsm_action_l63c10, RL_rseqFsm_action_l64c12,\n RL_rseqFsm_action_l65c12] ) fired in the same clock cycle.\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rseqFsm_action_d_init_np &&
(WILL_FIRE_RL_rseqFsm_action_np ||
WILL_FIRE_RL_rseqFsm_action_l63c10 ||
WILL_FIRE_RL_rseqFsm_action_l64c12 ||
WILL_FIRE_RL_rseqFsm_action_l65c12))
$display("Error: \"StmtFSM.bs\", line 41, column 0: (R0001)\n Mutually exclusive rules (from the ME sets [RL_rseqFsm_action_d_init_np] and\n [RL_rseqFsm_action_np, RL_rseqFsm_action_l63c10, RL_rseqFsm_action_l64c12,\n RL_rseqFsm_action_l65c12] ) fired in the same clock cycle.\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rseqFsm_action_np &&
(WILL_FIRE_RL_rseqFsm_action_l63c10 ||
WILL_FIRE_RL_rseqFsm_action_l64c12 ||
WILL_FIRE_RL_rseqFsm_action_l65c12))
$display("Error: \"StmtFSM.bs\", line 41, column 0: (R0001)\n Mutually exclusive rules (from the ME sets [RL_rseqFsm_action_np] and\n [RL_rseqFsm_action_l63c10, RL_rseqFsm_action_l64c12,\n RL_rseqFsm_action_l65c12] ) fired in the same clock cycle.\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rseqFsm_action_l63c10 &&
(WILL_FIRE_RL_rseqFsm_action_l64c12 ||
WILL_FIRE_RL_rseqFsm_action_l65c12))
$display("Error: \"bsv/dev/Flash.bsv\", line 63, column 10: (R0001)\n Mutually exclusive rules (from the ME sets [RL_rseqFsm_action_l63c10] and\n [RL_rseqFsm_action_l64c12, RL_rseqFsm_action_l65c12] ) fired in the same\n clock cycle.\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rseqFsm_action_l64c12 &&
WILL_FIRE_RL_rseqFsm_action_l65c12)
$display("Error: \"bsv/dev/Flash.bsv\", line 64, column 12: (R0001)\n Mutually exclusive rules (from the ME sets [RL_rseqFsm_action_l64c12] and\n [RL_rseqFsm_action_l65c12] ) fired in the same clock cycle.\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rseqFsm_action_l60c12 &&
(WILL_FIRE_RL_rseqFsm_action_l61c12 ||
WILL_FIRE_RL_rseqFsm_action_d_init_np ||
WILL_FIRE_RL_rseqFsm_action_np ||
WILL_FIRE_RL_rseqFsm_action_l63c10 ||
WILL_FIRE_RL_rseqFsm_action_l64c12 ||
WILL_FIRE_RL_rseqFsm_action_l65c12))
$display("Error: \"bsv/dev/Flash.bsv\", line 60, column 12: (R0001)\n Mutually exclusive rules (from the ME sets [RL_rseqFsm_action_l60c12] and\n [RL_rseqFsm_action_l61c12, RL_rseqFsm_action_d_init_np,\n RL_rseqFsm_action_np, RL_rseqFsm_action_l63c10, RL_rseqFsm_action_l64c12,\n RL_rseqFsm_action_l65c12] ) fired in the same clock cycle.\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wseqFsm_action_l71c12 &&
(WILL_FIRE_RL_wseqFsm_action_l72c12 ||
WILL_FIRE_RL_wseqFsm_action_l73c12 ||
WILL_FIRE_RL_wseqFsm_action_d_init_np ||
WILL_FIRE_RL_wseqFsm_action_np ||
WILL_FIRE_RL_wseqFsm_action_l75c12 ||
WILL_FIRE_RL_wseqFsm_action_l76c12 ||
WILL_FIRE_RL_wseqFsm_action_np_1 ||
WILL_FIRE_RL_wseqFsm_action_l78c12 ||
WILL_FIRE_RL_wseqFsm_action_l79c12 ||
WILL_FIRE_RL_wseqFsm_action_l80c12 ||
WILL_FIRE_RL_wseqFsm_action_d_init_np_1 ||
WILL_FIRE_RL_wseqFsm_action_np_2 ||
WILL_FIRE_RL_wseqFsm_action_l82c12 ||
WILL_FIRE_RL_wseqFsm_action_l83c12 ||
WILL_FIRE_RL_wseqFsm_action_l84c12 ||
WILL_FIRE_RL_wseqFsm_action_np_3 ||
WILL_FIRE_RL_wseqFsm_action_l87c12 ||
WILL_FIRE_RL_wseqFsm_action_l88c12 ||
WILL_FIRE_RL_wseqFsm_action_d_init_np_2 ||
WILL_FIRE_RL_wseqFsm_action_np_4 ||
WILL_FIRE_RL_wseqFsm_action_l90c12 ||
WILL_FIRE_RL_wseqFsm_action_l91c12))
$display("Error: \"bsv/dev/Flash.bsv\", line 71, column 12: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wseqFsm_action_l71c12] and\n [RL_wseqFsm_action_l72c12, RL_wseqFsm_action_l73c12,\n RL_wseqFsm_action_d_init_np, RL_wseqFsm_action_np, RL_wseqFsm_action_l75c12,\n RL_wseqFsm_action_l76c12, RL_wseqFsm_action_np_1, RL_wseqFsm_action_l78c12,\n RL_wseqFsm_action_l79c12, RL_wseqFsm_action_l80c12,\n RL_wseqFsm_action_d_init_np_1, RL_wseqFsm_action_np_2,\n RL_wseqFsm_action_l82c12, RL_wseqFsm_action_l83c12,\n RL_wseqFsm_action_l84c12, RL_wseqFsm_action_np_3, RL_wseqFsm_action_l87c12,\n RL_wseqFsm_action_l88c12, RL_wseqFsm_action_d_init_np_2,\n RL_wseqFsm_action_np_4, RL_wseqFsm_action_l90c12, RL_wseqFsm_action_l91c12]\n ) fired in the same clock cycle.\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wseqFsm_action_l72c12 &&
(WILL_FIRE_RL_wseqFsm_action_l73c12 ||
WILL_FIRE_RL_wseqFsm_action_d_init_np ||
WILL_FIRE_RL_wseqFsm_action_np ||
WILL_FIRE_RL_wseqFsm_action_l75c12 ||
WILL_FIRE_RL_wseqFsm_action_l76c12 ||
WILL_FIRE_RL_wseqFsm_action_np_1 ||
WILL_FIRE_RL_wseqFsm_action_l78c12 ||
WILL_FIRE_RL_wseqFsm_action_l79c12 ||
WILL_FIRE_RL_wseqFsm_action_l80c12 ||
WILL_FIRE_RL_wseqFsm_action_d_init_np_1 ||
WILL_FIRE_RL_wseqFsm_action_np_2 ||
WILL_FIRE_RL_wseqFsm_action_l82c12 ||
WILL_FIRE_RL_wseqFsm_action_l83c12 ||
WILL_FIRE_RL_wseqFsm_action_l84c12 ||
WILL_FIRE_RL_wseqFsm_action_np_3 ||
WILL_FIRE_RL_wseqFsm_action_l87c12 ||
WILL_FIRE_RL_wseqFsm_action_l88c12 ||
WILL_FIRE_RL_wseqFsm_action_d_init_np_2 ||
WILL_FIRE_RL_wseqFsm_action_np_4 ||
WILL_FIRE_RL_wseqFsm_action_l90c12 ||
WILL_FIRE_RL_wseqFsm_action_l91c12))
$display("Error: \"bsv/dev/Flash.bsv\", line 72, column 12: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wseqFsm_action_l72c12] and\n [RL_wseqFsm_action_l73c12, RL_wseqFsm_action_d_init_np,\n RL_wseqFsm_action_np, RL_wseqFsm_action_l75c12, RL_wseqFsm_action_l76c12,\n RL_wseqFsm_action_np_1, RL_wseqFsm_action_l78c12, RL_wseqFsm_action_l79c12,\n RL_wseqFsm_action_l80c12, RL_wseqFsm_action_d_init_np_1,\n RL_wseqFsm_action_np_2, RL_wseqFsm_action_l82c12, RL_wseqFsm_action_l83c12,\n RL_wseqFsm_action_l84c12, RL_wseqFsm_action_np_3, RL_wseqFsm_action_l87c12,\n RL_wseqFsm_action_l88c12, RL_wseqFsm_action_d_init_np_2,\n RL_wseqFsm_action_np_4, RL_wseqFsm_action_l90c12, RL_wseqFsm_action_l91c12]\n ) fired in the same clock cycle.\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wseqFsm_action_l73c12 &&
(WILL_FIRE_RL_wseqFsm_action_d_init_np ||
WILL_FIRE_RL_wseqFsm_action_np ||
WILL_FIRE_RL_wseqFsm_action_l75c12 ||
WILL_FIRE_RL_wseqFsm_action_l76c12 ||
WILL_FIRE_RL_wseqFsm_action_np_1 ||
WILL_FIRE_RL_wseqFsm_action_l78c12 ||
WILL_FIRE_RL_wseqFsm_action_l79c12 ||
WILL_FIRE_RL_wseqFsm_action_l80c12 ||
WILL_FIRE_RL_wseqFsm_action_d_init_np_1 ||
WILL_FIRE_RL_wseqFsm_action_np_2 ||
WILL_FIRE_RL_wseqFsm_action_l82c12 ||
WILL_FIRE_RL_wseqFsm_action_l83c12 ||
WILL_FIRE_RL_wseqFsm_action_l84c12 ||
WILL_FIRE_RL_wseqFsm_action_np_3 ||
WILL_FIRE_RL_wseqFsm_action_l87c12 ||
WILL_FIRE_RL_wseqFsm_action_l88c12 ||
WILL_FIRE_RL_wseqFsm_action_d_init_np_2 ||
WILL_FIRE_RL_wseqFsm_action_np_4 ||
WILL_FIRE_RL_wseqFsm_action_l90c12 ||
WILL_FIRE_RL_wseqFsm_action_l91c12))
$display("Error: \"bsv/dev/Flash.bsv\", line 73, column 12: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wseqFsm_action_l73c12] and\n [RL_wseqFsm_action_d_init_np, RL_wseqFsm_action_np,\n RL_wseqFsm_action_l75c12, RL_wseqFsm_action_l76c12, RL_wseqFsm_action_np_1,\n RL_wseqFsm_action_l78c12, RL_wseqFsm_action_l79c12,\n RL_wseqFsm_action_l80c12, RL_wseqFsm_action_d_init_np_1,\n RL_wseqFsm_action_np_2, RL_wseqFsm_action_l82c12, RL_wseqFsm_action_l83c12,\n RL_wseqFsm_action_l84c12, RL_wseqFsm_action_np_3, RL_wseqFsm_action_l87c12,\n RL_wseqFsm_action_l88c12, RL_wseqFsm_action_d_init_np_2,\n RL_wseqFsm_action_np_4, RL_wseqFsm_action_l90c12, RL_wseqFsm_action_l91c12]\n ) fired in the same clock cycle.\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wseqFsm_action_d_init_np &&
(WILL_FIRE_RL_wseqFsm_action_np ||
WILL_FIRE_RL_wseqFsm_action_l75c12 ||
WILL_FIRE_RL_wseqFsm_action_l76c12 ||
WILL_FIRE_RL_wseqFsm_action_np_1 ||
WILL_FIRE_RL_wseqFsm_action_l78c12 ||
WILL_FIRE_RL_wseqFsm_action_l79c12 ||
WILL_FIRE_RL_wseqFsm_action_l80c12 ||
WILL_FIRE_RL_wseqFsm_action_d_init_np_1 ||
WILL_FIRE_RL_wseqFsm_action_np_2 ||
WILL_FIRE_RL_wseqFsm_action_l82c12 ||
WILL_FIRE_RL_wseqFsm_action_l83c12 ||
WILL_FIRE_RL_wseqFsm_action_l84c12 ||
WILL_FIRE_RL_wseqFsm_action_np_3 ||
WILL_FIRE_RL_wseqFsm_action_l87c12 ||
WILL_FIRE_RL_wseqFsm_action_l88c12 ||
WILL_FIRE_RL_wseqFsm_action_d_init_np_2 ||
WILL_FIRE_RL_wseqFsm_action_np_4 ||
WILL_FIRE_RL_wseqFsm_action_l90c12 ||
WILL_FIRE_RL_wseqFsm_action_l91c12))
$display("Error: \"StmtFSM.bs\", line 41, column 0: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wseqFsm_action_d_init_np] and\n [RL_wseqFsm_action_np, RL_wseqFsm_action_l75c12, RL_wseqFsm_action_l76c12,\n RL_wseqFsm_action_np_1, RL_wseqFsm_action_l78c12, RL_wseqFsm_action_l79c12,\n RL_wseqFsm_action_l80c12, RL_wseqFsm_action_d_init_np_1,\n RL_wseqFsm_action_np_2, RL_wseqFsm_action_l82c12, RL_wseqFsm_action_l83c12,\n RL_wseqFsm_action_l84c12, RL_wseqFsm_action_np_3, RL_wseqFsm_action_l87c12,\n RL_wseqFsm_action_l88c12, RL_wseqFsm_action_d_init_np_2,\n RL_wseqFsm_action_np_4, RL_wseqFsm_action_l90c12, RL_wseqFsm_action_l91c12]\n ) fired in the same clock cycle.\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wseqFsm_action_l75c12 &&
(WILL_FIRE_RL_wseqFsm_action_l76c12 ||
WILL_FIRE_RL_wseqFsm_action_np_1 ||
WILL_FIRE_RL_wseqFsm_action_l78c12 ||
WILL_FIRE_RL_wseqFsm_action_l79c12 ||
WILL_FIRE_RL_wseqFsm_action_l80c12 ||
WILL_FIRE_RL_wseqFsm_action_d_init_np_1 ||
WILL_FIRE_RL_wseqFsm_action_np_2 ||
WILL_FIRE_RL_wseqFsm_action_l82c12 ||
WILL_FIRE_RL_wseqFsm_action_l83c12 ||
WILL_FIRE_RL_wseqFsm_action_l84c12 ||
WILL_FIRE_RL_wseqFsm_action_np_3 ||
WILL_FIRE_RL_wseqFsm_action_l87c12 ||
WILL_FIRE_RL_wseqFsm_action_l88c12 ||
WILL_FIRE_RL_wseqFsm_action_d_init_np_2 ||
WILL_FIRE_RL_wseqFsm_action_np_4 ||
WILL_FIRE_RL_wseqFsm_action_l90c12 ||
WILL_FIRE_RL_wseqFsm_action_l91c12))
$display("Error: \"bsv/dev/Flash.bsv\", line 75, column 12: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wseqFsm_action_l75c12] and\n [RL_wseqFsm_action_l76c12, RL_wseqFsm_action_np_1, RL_wseqFsm_action_l78c12,\n RL_wseqFsm_action_l79c12, RL_wseqFsm_action_l80c12,\n RL_wseqFsm_action_d_init_np_1, RL_wseqFsm_action_np_2,\n RL_wseqFsm_action_l82c12, RL_wseqFsm_action_l83c12,\n RL_wseqFsm_action_l84c12, RL_wseqFsm_action_np_3, RL_wseqFsm_action_l87c12,\n RL_wseqFsm_action_l88c12, RL_wseqFsm_action_d_init_np_2,\n RL_wseqFsm_action_np_4, RL_wseqFsm_action_l90c12, RL_wseqFsm_action_l91c12]\n ) fired in the same clock cycle.\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wseqFsm_action_np &&
(WILL_FIRE_RL_wseqFsm_action_l75c12 ||
WILL_FIRE_RL_wseqFsm_action_l76c12 ||
WILL_FIRE_RL_wseqFsm_action_np_1 ||
WILL_FIRE_RL_wseqFsm_action_l78c12 ||
WILL_FIRE_RL_wseqFsm_action_l79c12 ||
WILL_FIRE_RL_wseqFsm_action_l80c12 ||
WILL_FIRE_RL_wseqFsm_action_d_init_np_1 ||
WILL_FIRE_RL_wseqFsm_action_np_2 ||
WILL_FIRE_RL_wseqFsm_action_l82c12 ||
WILL_FIRE_RL_wseqFsm_action_l83c12 ||
WILL_FIRE_RL_wseqFsm_action_l84c12 ||
WILL_FIRE_RL_wseqFsm_action_np_3 ||
WILL_FIRE_RL_wseqFsm_action_l87c12 ||
WILL_FIRE_RL_wseqFsm_action_l88c12 ||
WILL_FIRE_RL_wseqFsm_action_d_init_np_2 ||
WILL_FIRE_RL_wseqFsm_action_np_4 ||
WILL_FIRE_RL_wseqFsm_action_l90c12 ||
WILL_FIRE_RL_wseqFsm_action_l91c12))
$display("Error: \"StmtFSM.bs\", line 41, column 0: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wseqFsm_action_np] and\n [RL_wseqFsm_action_l75c12, RL_wseqFsm_action_l76c12, RL_wseqFsm_action_np_1,\n RL_wseqFsm_action_l78c12, RL_wseqFsm_action_l79c12,\n RL_wseqFsm_action_l80c12, RL_wseqFsm_action_d_init_np_1,\n RL_wseqFsm_action_np_2, RL_wseqFsm_action_l82c12, RL_wseqFsm_action_l83c12,\n RL_wseqFsm_action_l84c12, RL_wseqFsm_action_np_3, RL_wseqFsm_action_l87c12,\n RL_wseqFsm_action_l88c12, RL_wseqFsm_action_d_init_np_2,\n RL_wseqFsm_action_np_4, RL_wseqFsm_action_l90c12, RL_wseqFsm_action_l91c12]\n ) fired in the same clock cycle.\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wseqFsm_action_l76c12 &&
(WILL_FIRE_RL_wseqFsm_action_np_1 ||
WILL_FIRE_RL_wseqFsm_action_l78c12 ||
WILL_FIRE_RL_wseqFsm_action_l79c12 ||
WILL_FIRE_RL_wseqFsm_action_l80c12 ||
WILL_FIRE_RL_wseqFsm_action_d_init_np_1 ||
WILL_FIRE_RL_wseqFsm_action_np_2 ||
WILL_FIRE_RL_wseqFsm_action_l82c12 ||
WILL_FIRE_RL_wseqFsm_action_l83c12 ||
WILL_FIRE_RL_wseqFsm_action_l84c12 ||
WILL_FIRE_RL_wseqFsm_action_np_3 ||
WILL_FIRE_RL_wseqFsm_action_l87c12 ||
WILL_FIRE_RL_wseqFsm_action_l88c12 ||
WILL_FIRE_RL_wseqFsm_action_d_init_np_2 ||
WILL_FIRE_RL_wseqFsm_action_np_4 ||
WILL_FIRE_RL_wseqFsm_action_l90c12 ||
WILL_FIRE_RL_wseqFsm_action_l91c12))
$display("Error: \"bsv/dev/Flash.bsv\", line 76, column 12: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wseqFsm_action_l76c12] and\n [RL_wseqFsm_action_np_1, RL_wseqFsm_action_l78c12, RL_wseqFsm_action_l79c12,\n RL_wseqFsm_action_l80c12, RL_wseqFsm_action_d_init_np_1,\n RL_wseqFsm_action_np_2, RL_wseqFsm_action_l82c12, RL_wseqFsm_action_l83c12,\n RL_wseqFsm_action_l84c12, RL_wseqFsm_action_np_3, RL_wseqFsm_action_l87c12,\n RL_wseqFsm_action_l88c12, RL_wseqFsm_action_d_init_np_2,\n RL_wseqFsm_action_np_4, RL_wseqFsm_action_l90c12, RL_wseqFsm_action_l91c12]\n ) fired in the same clock cycle.\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wseqFsm_action_l78c12 &&
(WILL_FIRE_RL_wseqFsm_action_l79c12 ||
WILL_FIRE_RL_wseqFsm_action_l80c12 ||
WILL_FIRE_RL_wseqFsm_action_d_init_np_1 ||
WILL_FIRE_RL_wseqFsm_action_np_2 ||
WILL_FIRE_RL_wseqFsm_action_l82c12 ||
WILL_FIRE_RL_wseqFsm_action_l83c12 ||
WILL_FIRE_RL_wseqFsm_action_l84c12 ||
WILL_FIRE_RL_wseqFsm_action_np_3 ||
WILL_FIRE_RL_wseqFsm_action_l87c12 ||
WILL_FIRE_RL_wseqFsm_action_l88c12 ||
WILL_FIRE_RL_wseqFsm_action_d_init_np_2 ||
WILL_FIRE_RL_wseqFsm_action_np_4 ||
WILL_FIRE_RL_wseqFsm_action_l90c12 ||
WILL_FIRE_RL_wseqFsm_action_l91c12))
$display("Error: \"bsv/dev/Flash.bsv\", line 78, column 12: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wseqFsm_action_l78c12] and\n [RL_wseqFsm_action_l79c12, RL_wseqFsm_action_l80c12,\n RL_wseqFsm_action_d_init_np_1, RL_wseqFsm_action_np_2,\n RL_wseqFsm_action_l82c12, RL_wseqFsm_action_l83c12,\n RL_wseqFsm_action_l84c12, RL_wseqFsm_action_np_3, RL_wseqFsm_action_l87c12,\n RL_wseqFsm_action_l88c12, RL_wseqFsm_action_d_init_np_2,\n RL_wseqFsm_action_np_4, RL_wseqFsm_action_l90c12, RL_wseqFsm_action_l91c12]\n ) fired in the same clock cycle.\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wseqFsm_action_np_1 &&
(WILL_FIRE_RL_wseqFsm_action_l78c12 ||
WILL_FIRE_RL_wseqFsm_action_l79c12 ||
WILL_FIRE_RL_wseqFsm_action_l80c12 ||
WILL_FIRE_RL_wseqFsm_action_d_init_np_1 ||
WILL_FIRE_RL_wseqFsm_action_np_2 ||
WILL_FIRE_RL_wseqFsm_action_l82c12 ||
WILL_FIRE_RL_wseqFsm_action_l83c12 ||
WILL_FIRE_RL_wseqFsm_action_l84c12 ||
WILL_FIRE_RL_wseqFsm_action_np_3 ||
WILL_FIRE_RL_wseqFsm_action_l87c12 ||
WILL_FIRE_RL_wseqFsm_action_l88c12 ||
WILL_FIRE_RL_wseqFsm_action_d_init_np_2 ||
WILL_FIRE_RL_wseqFsm_action_np_4 ||
WILL_FIRE_RL_wseqFsm_action_l90c12 ||
WILL_FIRE_RL_wseqFsm_action_l91c12))
$display("Error: \"StmtFSM.bs\", line 41, column 0: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wseqFsm_action_np_1] and\n [RL_wseqFsm_action_l78c12, RL_wseqFsm_action_l79c12,\n RL_wseqFsm_action_l80c12, RL_wseqFsm_action_d_init_np_1,\n RL_wseqFsm_action_np_2, RL_wseqFsm_action_l82c12, RL_wseqFsm_action_l83c12,\n RL_wseqFsm_action_l84c12, RL_wseqFsm_action_np_3, RL_wseqFsm_action_l87c12,\n RL_wseqFsm_action_l88c12, RL_wseqFsm_action_d_init_np_2,\n RL_wseqFsm_action_np_4, RL_wseqFsm_action_l90c12, RL_wseqFsm_action_l91c12]\n ) fired in the same clock cycle.\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wseqFsm_action_l79c12 &&
(WILL_FIRE_RL_wseqFsm_action_l80c12 ||
WILL_FIRE_RL_wseqFsm_action_d_init_np_1 ||
WILL_FIRE_RL_wseqFsm_action_np_2 ||
WILL_FIRE_RL_wseqFsm_action_l82c12 ||
WILL_FIRE_RL_wseqFsm_action_l83c12 ||
WILL_FIRE_RL_wseqFsm_action_l84c12 ||
WILL_FIRE_RL_wseqFsm_action_np_3 ||
WILL_FIRE_RL_wseqFsm_action_l87c12 ||
WILL_FIRE_RL_wseqFsm_action_l88c12 ||
WILL_FIRE_RL_wseqFsm_action_d_init_np_2 ||
WILL_FIRE_RL_wseqFsm_action_np_4 ||
WILL_FIRE_RL_wseqFsm_action_l90c12 ||
WILL_FIRE_RL_wseqFsm_action_l91c12))
$display("Error: \"bsv/dev/Flash.bsv\", line 79, column 12: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wseqFsm_action_l79c12] and\n [RL_wseqFsm_action_l80c12, RL_wseqFsm_action_d_init_np_1,\n RL_wseqFsm_action_np_2, RL_wseqFsm_action_l82c12, RL_wseqFsm_action_l83c12,\n RL_wseqFsm_action_l84c12, RL_wseqFsm_action_np_3, RL_wseqFsm_action_l87c12,\n RL_wseqFsm_action_l88c12, RL_wseqFsm_action_d_init_np_2,\n RL_wseqFsm_action_np_4, RL_wseqFsm_action_l90c12, RL_wseqFsm_action_l91c12]\n ) fired in the same clock cycle.\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wseqFsm_action_l80c12 &&
(WILL_FIRE_RL_wseqFsm_action_d_init_np_1 ||
WILL_FIRE_RL_wseqFsm_action_np_2 ||
WILL_FIRE_RL_wseqFsm_action_l82c12 ||
WILL_FIRE_RL_wseqFsm_action_l83c12 ||
WILL_FIRE_RL_wseqFsm_action_l84c12 ||
WILL_FIRE_RL_wseqFsm_action_np_3 ||
WILL_FIRE_RL_wseqFsm_action_l87c12 ||
WILL_FIRE_RL_wseqFsm_action_l88c12 ||
WILL_FIRE_RL_wseqFsm_action_d_init_np_2 ||
WILL_FIRE_RL_wseqFsm_action_np_4 ||
WILL_FIRE_RL_wseqFsm_action_l90c12 ||
WILL_FIRE_RL_wseqFsm_action_l91c12))
$display("Error: \"bsv/dev/Flash.bsv\", line 80, column 12: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wseqFsm_action_l80c12] and\n [RL_wseqFsm_action_d_init_np_1, RL_wseqFsm_action_np_2,\n RL_wseqFsm_action_l82c12, RL_wseqFsm_action_l83c12,\n RL_wseqFsm_action_l84c12, RL_wseqFsm_action_np_3, RL_wseqFsm_action_l87c12,\n RL_wseqFsm_action_l88c12, RL_wseqFsm_action_d_init_np_2,\n RL_wseqFsm_action_np_4, RL_wseqFsm_action_l90c12, RL_wseqFsm_action_l91c12]\n ) fired in the same clock cycle.\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wseqFsm_action_np_2 &&
(WILL_FIRE_RL_wseqFsm_action_l82c12 ||
WILL_FIRE_RL_wseqFsm_action_l83c12 ||
WILL_FIRE_RL_wseqFsm_action_l84c12 ||
WILL_FIRE_RL_wseqFsm_action_np_3 ||
WILL_FIRE_RL_wseqFsm_action_l87c12 ||
WILL_FIRE_RL_wseqFsm_action_l88c12 ||
WILL_FIRE_RL_wseqFsm_action_d_init_np_2 ||
WILL_FIRE_RL_wseqFsm_action_np_4 ||
WILL_FIRE_RL_wseqFsm_action_l90c12 ||
WILL_FIRE_RL_wseqFsm_action_l91c12))
$display("Error: \"StmtFSM.bs\", line 41, column 0: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wseqFsm_action_np_2] and\n [RL_wseqFsm_action_l82c12, RL_wseqFsm_action_l83c12,\n RL_wseqFsm_action_l84c12, RL_wseqFsm_action_np_3, RL_wseqFsm_action_l87c12,\n RL_wseqFsm_action_l88c12, RL_wseqFsm_action_d_init_np_2,\n RL_wseqFsm_action_np_4, RL_wseqFsm_action_l90c12, RL_wseqFsm_action_l91c12]\n ) fired in the same clock cycle.\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wseqFsm_action_d_init_np_1 &&
(WILL_FIRE_RL_wseqFsm_action_np_2 ||
WILL_FIRE_RL_wseqFsm_action_l82c12 ||
WILL_FIRE_RL_wseqFsm_action_l83c12 ||
WILL_FIRE_RL_wseqFsm_action_l84c12 ||
WILL_FIRE_RL_wseqFsm_action_np_3 ||
WILL_FIRE_RL_wseqFsm_action_l87c12 ||
WILL_FIRE_RL_wseqFsm_action_l88c12 ||
WILL_FIRE_RL_wseqFsm_action_d_init_np_2 ||
WILL_FIRE_RL_wseqFsm_action_np_4 ||
WILL_FIRE_RL_wseqFsm_action_l90c12 ||
WILL_FIRE_RL_wseqFsm_action_l91c12))
$display("Error: \"StmtFSM.bs\", line 41, column 0: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wseqFsm_action_d_init_np_1]\n and [RL_wseqFsm_action_np_2, RL_wseqFsm_action_l82c12,\n RL_wseqFsm_action_l83c12, RL_wseqFsm_action_l84c12, RL_wseqFsm_action_np_3,\n RL_wseqFsm_action_l87c12, RL_wseqFsm_action_l88c12,\n RL_wseqFsm_action_d_init_np_2, RL_wseqFsm_action_np_4,\n RL_wseqFsm_action_l90c12, RL_wseqFsm_action_l91c12] ) fired in the same\n clock cycle.\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wseqFsm_action_l82c12 &&
(WILL_FIRE_RL_wseqFsm_action_l83c12 ||
WILL_FIRE_RL_wseqFsm_action_l84c12 ||
WILL_FIRE_RL_wseqFsm_action_np_3 ||
WILL_FIRE_RL_wseqFsm_action_l87c12 ||
WILL_FIRE_RL_wseqFsm_action_l88c12 ||
WILL_FIRE_RL_wseqFsm_action_d_init_np_2 ||
WILL_FIRE_RL_wseqFsm_action_np_4 ||
WILL_FIRE_RL_wseqFsm_action_l90c12 ||
WILL_FIRE_RL_wseqFsm_action_l91c12))
$display("Error: \"bsv/dev/Flash.bsv\", line 82, column 12: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wseqFsm_action_l82c12] and\n [RL_wseqFsm_action_l83c12, RL_wseqFsm_action_l84c12, RL_wseqFsm_action_np_3,\n RL_wseqFsm_action_l87c12, RL_wseqFsm_action_l88c12,\n RL_wseqFsm_action_d_init_np_2, RL_wseqFsm_action_np_4,\n RL_wseqFsm_action_l90c12, RL_wseqFsm_action_l91c12] ) fired in the same\n clock cycle.\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wseqFsm_action_l83c12 &&
(WILL_FIRE_RL_wseqFsm_action_l84c12 ||
WILL_FIRE_RL_wseqFsm_action_np_3 ||
WILL_FIRE_RL_wseqFsm_action_l87c12 ||
WILL_FIRE_RL_wseqFsm_action_l88c12 ||
WILL_FIRE_RL_wseqFsm_action_d_init_np_2 ||
WILL_FIRE_RL_wseqFsm_action_np_4 ||
WILL_FIRE_RL_wseqFsm_action_l90c12 ||
WILL_FIRE_RL_wseqFsm_action_l91c12))
$display("Error: \"bsv/dev/Flash.bsv\", line 83, column 12: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wseqFsm_action_l83c12] and\n [RL_wseqFsm_action_l84c12, RL_wseqFsm_action_np_3, RL_wseqFsm_action_l87c12,\n RL_wseqFsm_action_l88c12, RL_wseqFsm_action_d_init_np_2,\n RL_wseqFsm_action_np_4, RL_wseqFsm_action_l90c12, RL_wseqFsm_action_l91c12]\n ) fired in the same clock cycle.\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wseqFsm_action_np_3 &&
(WILL_FIRE_RL_wseqFsm_action_l87c12 ||
WILL_FIRE_RL_wseqFsm_action_l88c12 ||
WILL_FIRE_RL_wseqFsm_action_d_init_np_2 ||
WILL_FIRE_RL_wseqFsm_action_np_4 ||
WILL_FIRE_RL_wseqFsm_action_l90c12 ||
WILL_FIRE_RL_wseqFsm_action_l91c12))
$display("Error: \"StmtFSM.bs\", line 41, column 0: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wseqFsm_action_np_3] and\n [RL_wseqFsm_action_l87c12, RL_wseqFsm_action_l88c12,\n RL_wseqFsm_action_d_init_np_2, RL_wseqFsm_action_np_4,\n RL_wseqFsm_action_l90c12, RL_wseqFsm_action_l91c12] ) fired in the same\n clock cycle.\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wseqFsm_action_l84c12 &&
(WILL_FIRE_RL_wseqFsm_action_np_3 ||
WILL_FIRE_RL_wseqFsm_action_l87c12 ||
WILL_FIRE_RL_wseqFsm_action_l88c12 ||
WILL_FIRE_RL_wseqFsm_action_d_init_np_2 ||
WILL_FIRE_RL_wseqFsm_action_np_4 ||
WILL_FIRE_RL_wseqFsm_action_l90c12 ||
WILL_FIRE_RL_wseqFsm_action_l91c12))
$display("Error: \"bsv/dev/Flash.bsv\", line 84, column 12: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wseqFsm_action_l84c12] and\n [RL_wseqFsm_action_np_3, RL_wseqFsm_action_l87c12, RL_wseqFsm_action_l88c12,\n RL_wseqFsm_action_d_init_np_2, RL_wseqFsm_action_np_4,\n RL_wseqFsm_action_l90c12, RL_wseqFsm_action_l91c12] ) fired in the same\n clock cycle.\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wseqFsm_action_l87c12 &&
(WILL_FIRE_RL_wseqFsm_action_l88c12 ||
WILL_FIRE_RL_wseqFsm_action_d_init_np_2 ||
WILL_FIRE_RL_wseqFsm_action_np_4 ||
WILL_FIRE_RL_wseqFsm_action_l90c12 ||
WILL_FIRE_RL_wseqFsm_action_l91c12))
$display("Error: \"bsv/dev/Flash.bsv\", line 87, column 12: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wseqFsm_action_l87c12] and\n [RL_wseqFsm_action_l88c12, RL_wseqFsm_action_d_init_np_2,\n RL_wseqFsm_action_np_4, RL_wseqFsm_action_l90c12, RL_wseqFsm_action_l91c12]\n ) fired in the same clock cycle.\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wseqFsm_action_l88c12 &&
(WILL_FIRE_RL_wseqFsm_action_d_init_np_2 ||
WILL_FIRE_RL_wseqFsm_action_np_4 ||
WILL_FIRE_RL_wseqFsm_action_l90c12 ||
WILL_FIRE_RL_wseqFsm_action_l91c12))
$display("Error: \"bsv/dev/Flash.bsv\", line 88, column 12: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wseqFsm_action_l88c12] and\n [RL_wseqFsm_action_d_init_np_2, RL_wseqFsm_action_np_4,\n RL_wseqFsm_action_l90c12, RL_wseqFsm_action_l91c12] ) fired in the same\n clock cycle.\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wseqFsm_action_d_init_np_2 &&
(WILL_FIRE_RL_wseqFsm_action_np_4 ||
WILL_FIRE_RL_wseqFsm_action_l90c12 ||
WILL_FIRE_RL_wseqFsm_action_l91c12))
$display("Error: \"StmtFSM.bs\", line 41, column 0: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wseqFsm_action_d_init_np_2]\n and [RL_wseqFsm_action_np_4, RL_wseqFsm_action_l90c12,\n RL_wseqFsm_action_l91c12] ) fired in the same clock cycle.\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wseqFsm_action_l90c12 &&
WILL_FIRE_RL_wseqFsm_action_l91c12)
$display("Error: \"bsv/dev/Flash.bsv\", line 90, column 12: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wseqFsm_action_l90c12] and\n [RL_wseqFsm_action_l91c12] ) fired in the same clock cycle.\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wseqFsm_action_np_4 &&
(WILL_FIRE_RL_wseqFsm_action_l90c12 ||
WILL_FIRE_RL_wseqFsm_action_l91c12))
$display("Error: \"StmtFSM.bs\", line 41, column 0: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wseqFsm_action_np_4] and\n [RL_wseqFsm_action_l90c12, RL_wseqFsm_action_l91c12] ) fired in the same\n clock cycle.\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wseqFsm_action_l70c12 &&
(WILL_FIRE_RL_wseqFsm_action_l71c12 ||
WILL_FIRE_RL_wseqFsm_action_l72c12 ||
WILL_FIRE_RL_wseqFsm_action_l73c12 ||
WILL_FIRE_RL_wseqFsm_action_d_init_np ||
WILL_FIRE_RL_wseqFsm_action_np ||
WILL_FIRE_RL_wseqFsm_action_l75c12 ||
WILL_FIRE_RL_wseqFsm_action_l76c12 ||
WILL_FIRE_RL_wseqFsm_action_np_1 ||
WILL_FIRE_RL_wseqFsm_action_l78c12 ||
WILL_FIRE_RL_wseqFsm_action_l79c12 ||
WILL_FIRE_RL_wseqFsm_action_l80c12 ||
WILL_FIRE_RL_wseqFsm_action_d_init_np_1 ||
WILL_FIRE_RL_wseqFsm_action_np_2 ||
WILL_FIRE_RL_wseqFsm_action_l82c12 ||
WILL_FIRE_RL_wseqFsm_action_l83c12 ||
WILL_FIRE_RL_wseqFsm_action_l84c12 ||
WILL_FIRE_RL_wseqFsm_action_np_3 ||
WILL_FIRE_RL_wseqFsm_action_l87c12 ||
WILL_FIRE_RL_wseqFsm_action_l88c12 ||
WILL_FIRE_RL_wseqFsm_action_d_init_np_2 ||
WILL_FIRE_RL_wseqFsm_action_np_4 ||
WILL_FIRE_RL_wseqFsm_action_l90c12 ||
WILL_FIRE_RL_wseqFsm_action_l91c12))
$display("Error: \"bsv/dev/Flash.bsv\", line 70, column 12: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wseqFsm_action_l70c12] and\n [RL_wseqFsm_action_l71c12, RL_wseqFsm_action_l72c12,\n RL_wseqFsm_action_l73c12, RL_wseqFsm_action_d_init_np, RL_wseqFsm_action_np,\n RL_wseqFsm_action_l75c12, RL_wseqFsm_action_l76c12, RL_wseqFsm_action_np_1,\n RL_wseqFsm_action_l78c12, RL_wseqFsm_action_l79c12,\n RL_wseqFsm_action_l80c12, RL_wseqFsm_action_d_init_np_1,\n RL_wseqFsm_action_np_2, RL_wseqFsm_action_l82c12, RL_wseqFsm_action_l83c12,\n RL_wseqFsm_action_l84c12, RL_wseqFsm_action_np_3, RL_wseqFsm_action_l87c12,\n RL_wseqFsm_action_l88c12, RL_wseqFsm_action_d_init_np_2,\n RL_wseqFsm_action_np_4, RL_wseqFsm_action_l90c12, RL_wseqFsm_action_l91c12]\n ) fired in the same clock cycle.\n");
end
// synopsys translate_on
endmodule
|
module sky130_fd_sc_hs__einvn (
A ,
TE_B,
Z
);
input A ;
input TE_B;
output Z ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
endmodule
|
module pcie_top (
// Clock and Reset
input wire refclkp,
input wire refclkn,
input wire ext_reset_n, //to reset pcs pipe
input wire rstn,
input wire hdinp0,
input wire hdinn0,
output wire hdoutp0,
output wire hdoutn0,
input wire inta_n,
input wire [7:0] msi,
input wire [15:0] vendor_id ,
input wire [15:0] device_id ,
input wire [7:0] rev_id ,
input wire [23:0] class_code ,
input wire [15:0] subsys_ven_id ,
input wire [15:0] subsys_id ,
input wire load_id ,
input wire force_lsm_active, // Force LSM Status Active
input wire force_rec_ei, // Force Received Electrical Idle
input wire force_phy_status, // Force PHY Connection Status
input wire force_disable_scr,// Force Disable Scrambler to PCS
input wire hl_snd_beacon, // HL req. to Send Beacon
input wire hl_disable_scr, // HL req. to Disable Scrambling bit in TS1/TS2
input wire hl_gto_dis, // HL req a jump to Disable
input wire hl_gto_det, // HL req a jump to detect
input wire hl_gto_hrst, // HL req a jump to Hot reset
input wire hl_gto_l0stx, // HL req a jump to TX L0s
input wire hl_gto_l1, // HL req a jump to L1
input wire hl_gto_l2, // HL req a jump to L2
input wire hl_gto_l0stxfts, // HL req a jump to L0s TX FTS
input wire hl_gto_lbk, // HL req a jump to Loopback
input wire hl_gto_rcvry, // HL req a jump to recovery
input wire hl_gto_cfg, // HL req a jump to CFG
input wire no_pcie_train, // Disable the training process
// Power Management Interface
input wire [1:0] tx_dllp_val, // Req for Sending PM/Vendor type DLLP
input wire [2:0] tx_pmtype, // Power Management Type
input wire [23:0] tx_vsd_data, // Vendor Type DLLP contents
// For VC Inputs
input wire tx_req_vc0, // VC0 Request from User
input wire [15:0] tx_data_vc0, // VC0 Input data from user logic
input wire tx_st_vc0, // VC0 start of pkt from user logic.
input wire tx_end_vc0, // VC0 End of pkt from user logic.
input wire tx_nlfy_vc0, // VC0 End of nullified pkt from user logic.
input wire ph_buf_status_vc0, // VC0 Indicate the Full/alm.Full status of the PH buffers
input wire pd_buf_status_vc0, // VC0 Indicate PD Buffer has got space less than Max Pkt size
input wire nph_buf_status_vc0, // VC0 For NPH
input wire npd_buf_status_vc0, // VC0 For NPD
input wire ph_processed_vc0, // VC0 TL has processed one TLP Header - PH Type
input wire pd_processed_vc0, // VC0 TL has processed one TLP Data - PD TYPE
input wire nph_processed_vc0, // VC0 For NPH
input wire npd_processed_vc0, // VC0 For NPD
input wire [7:0] pd_num_vc0, // VC0 For PD -- No. of Data processed
input wire [7:0] npd_num_vc0, // VC0 For PD
input wire cmpln_tout , // Completion time out.
input wire cmpltr_abort_np , // Completor abort.
input wire cmpltr_abort_p, //
input wire unexp_cmpln , // Unexpexted completion.
input wire ur_np_ext , // UR for NP type.
input wire ur_p_ext , // UR for P type.
input wire np_req_pend , // Non posted request is pending.
input wire pme_status , // PME status to reg 044h.
// Power Management/ Vendor specific DLLP
output wire tx_dllp_sent, // Requested PM DLLP is sent
output wire [2:0] rxdp_pmd_type, // PM DLLP type bits.
output wire [23:0] rxdp_vsd_data , // Vendor specific DLLP data.
output wire [1:0] rxdp_dllp_val, // PM/Vendor specific DLLP valid.
output wire phy_pol_compliance, // Polling compliance
output wire [3:0] phy_ltssm_state, // Indicates the states of the ltssm
output wire [2:0] phy_ltssm_substate, // sub-states of the ltssm_state
output wire tx_rdy_vc0, // VC0 TX ready indicating signal
output wire [8:0] tx_ca_ph_vc0, // VC0 Available credit for Posted Type Headers
output wire [12:0] tx_ca_pd_vc0, // VC0 For Posted - Data
output wire [8:0] tx_ca_nph_vc0, // VC0 For Non-posted - Header
output wire [12:0] tx_ca_npd_vc0, // VC0 For Non-posted - Data
output wire [8:0] tx_ca_cplh_vc0, // VC0 For Completion - Header
output wire [12:0] tx_ca_cpld_vc0, // VC0 For Completion - Data
output wire tx_ca_p_recheck_vc0, //
output wire tx_ca_cpl_recheck_vc0, //
output wire [15:0] rx_data_vc0, // VC0 Receive data
output wire rx_st_vc0, // VC0 Receive data start
output wire rx_end_vc0, // VC0 Receive data end
output wire rx_us_req_vc0 , // VC0 unsupported req received
output wire rx_malf_tlp_vc0 ,// VC0 malformed TLP in received data
output wire [6:0] rx_bar_hit , // Bar hit
output wire [2:0] mm_enable , // Multiple message enable bits of Register
output wire msi_enable , // MSI enable bit of Register
// From Config Registers
output wire [7:0] bus_num , // Bus number
output wire [4:0] dev_num , // Device number
output wire [2:0] func_num , // Function number
output wire [1:0] pm_power_state , // Power state bits of Register at 044h
output wire pme_en , // PME_En at 044h
output wire [5:0] cmd_reg_out , // Bits 10,8,6,2,1,0 From register 004h
output wire [14:0] dev_cntl_out , // Divice control register at 060h
output wire [7:0] lnk_cntl_out , // Link control register at 068h
// To ASPM implementation outside the IP
output wire tx_rbuf_empty, // Transmit retry buffer is empty
output wire tx_dllp_pend, // DLPP is pending to be transmitted
output wire rx_tlp_rcvd, // Received a TLP
// Datal Link Control SM Status
output wire dl_inactive, // Data Link Control SM is in INACTIVE state
output wire dl_init, // INIT state
output wire dl_active, // ACTIVE state
output wire dl_up , // Data Link Layer is UP
output wire sys_clk_125, // 125MHz output clock from core
input wire flip_lanes
);
// =============================================================================
// Define Wires & Regs
// =============================================================================
wire [1:0] power_down;
wire reset_n;
wire tx_detect_rx_lb;
wire phy_status;
wire [7:0] txp_data_ln0;
wire txp_data_k_ln0;
wire txp_elec_idle_ln0;
wire txp_compliance_ln0;
wire [7:0] rxp_data_ln0;
wire rxp_data_k_ln0;
wire rxp_valid_ln0;
wire rxp_polarity_ln0;
wire rxp_elec_idle_ln0;
wire [2:0] rxp_status_ln0;
wire pclk; //250MHz clk from PCS PIPE for 8 bit data
wire phy_l0;
assign phy_l0 = (phy_ltssm_state == 'd3) ;
// =============================================================================
// SERDES/PCS instantiation in PIPE mode
// =============================================================================
pcs_pipe_top u1_pcs_pipe (
.refclkp ( refclkp ),
.refclkn ( refclkn ),
.RESET_n ( ext_reset_n ),
.hdinp0 ( hdinp0 ),
.hdinn0 ( hdinn0 ),
.hdoutp0 ( hdoutp0 ),
.hdoutn0 ( hdoutn0 ),
.TxData_0 ( txp_data_ln0 ),
.TxDataK_0 ( txp_data_k_ln0 ),
.TxCompliance_0 ( txp_compliance_ln0 ),
.TxElecIdle_0 ( txp_elec_idle_ln0 ),
.RxData_0 ( rxp_data_ln0 ),
.RxDataK_0 ( rxp_data_k_ln0 ),
.RxValid_0 ( rxp_valid_ln0 ),
.RxPolarity_0 ( rxp_polarity_ln0 ),
.RxElecIdle_0 ( rxp_elec_idle_ln0 ),
.RxStatus_0 ( rxp_status_ln0 ),
.scisel_0 ( 1'b0 ),
.scien_0 ( 1'b0 ),
.sciwritedata ( 8'h0 ),
.sciaddress ( 6'h0 ),
.scireaddata ( ),
.scienaux ( 1'b0 ),
.sciselaux ( 1'b0 ),
.scird ( 1'b0 ),
.sciwstn ( 1'b0 ),
.ffs_plol ( ),
.ffs_rlol_ch0 ( ),
.flip_lanes ( flip_lanes ),
.PCLK ( pclk ),
.PCLK_by_2 ( sys_clk_125 ),
.TxDetectRx_Loopback ( tx_detect_rx_lb ),
.PhyStatus ( phy_status ),
.PowerDown ( power_down ),
.phy_l0 ( phy_l0 ),
.phy_cfgln ( 4'b0000 ),
.ctc_disable ( 1'b0 )
);
// =============================================================================
// PCI Express Core
// =============================================================================
pcie u1_dut(
// Clock and Reset
.sys_clk_250 ( pclk ) ,
.sys_clk_125 ( sys_clk_125 ) ,
.rst_n ( rstn ),
.inta_n ( inta_n ),
.msi ( msi ),
.vendor_id ( vendor_id ),
.device_id ( device_id ),
.rev_id ( rev_id ),
.class_code ( class_code ),
.subsys_ven_id ( subsys_ven_id ),
.subsys_id ( subsys_id ),
.load_id ( load_id ),
// Inputs
.force_lsm_active ( force_lsm_active ),
.force_rec_ei ( force_rec_ei ),
.force_phy_status ( force_phy_status ),
.force_disable_scr ( force_disable_scr ),
.hl_snd_beacon ( hl_snd_beacon ),
.hl_disable_scr ( hl_disable_scr ),
.hl_gto_dis ( hl_gto_dis ),
.hl_gto_det ( hl_gto_det ),
.hl_gto_hrst ( hl_gto_hrst ),
.hl_gto_l0stx ( hl_gto_l0stx ),
.hl_gto_l1 ( hl_gto_l1 ),
.hl_gto_l2 ( hl_gto_l2 ),
.hl_gto_l0stxfts ( hl_gto_l0stxfts ),
.hl_gto_lbk ( hl_gto_lbk ),
.hl_gto_rcvry ( hl_gto_rcvry ),
.hl_gto_cfg ( hl_gto_cfg ),
.no_pcie_train ( no_pcie_train ),
// Power Management Interface
.tx_dllp_val ( tx_dllp_val ),
.tx_pmtype ( tx_pmtype ),
.tx_vsd_data ( tx_vsd_data ),
.tx_req_vc0 ( tx_req_vc0 ),
.tx_data_vc0 ( tx_data_vc0 ),
.tx_st_vc0 ( tx_st_vc0 ),
.tx_end_vc0 ( tx_end_vc0 ),
.tx_nlfy_vc0 ( tx_nlfy_vc0 ),
.ph_buf_status_vc0 ( ph_buf_status_vc0 ),
.pd_buf_status_vc0 ( pd_buf_status_vc0 ),
.nph_buf_status_vc0 ( nph_buf_status_vc0 ),
.npd_buf_status_vc0 ( npd_buf_status_vc0 ),
.ph_processed_vc0 ( ph_processed_vc0 ),
.pd_processed_vc0 ( pd_processed_vc0 ),
.nph_processed_vc0 ( nph_processed_vc0 ),
.npd_processed_vc0 ( npd_processed_vc0 ),
.pd_num_vc0 ( pd_num_vc0 ),
.npd_num_vc0 ( npd_num_vc0 ),
// From External PHY (PIPE I/F)
.rxp_data ( rxp_data_ln0 ),
.rxp_data_k ( rxp_data_k_ln0 ),
.rxp_valid ( rxp_valid_ln0 ),
.rxp_elec_idle ( rxp_elec_idle_ln0 ),
.rxp_status ( rxp_status_ln0 ),
.phy_status ( phy_status),
// From User logic
.cmpln_tout ( cmpln_tout ),
.cmpltr_abort_np ( cmpltr_abort_np ),
.cmpltr_abort_p ( cmpltr_abort_p),
.unexp_cmpln ( unexp_cmpln ),
.ur_np_ext ( ur_np_ext ) ,
.ur_p_ext ( ur_p_ext ) ,
.np_req_pend ( np_req_pend ),
.pme_status ( pme_status ),
.tx_lbk_data ( 16'd0 ),
.tx_lbk_kcntl ( 2'd0 ),
.tx_lbk_rdy ( ),
.rx_lbk_data ( ),
.rx_lbk_kcntl ( ),
// Power Management
.tx_dllp_sent ( tx_dllp_sent ),
.rxdp_pmd_type ( rxdp_pmd_type ),
.rxdp_vsd_data ( rxdp_vsd_data ),
.rxdp_dllp_val ( rxdp_dllp_val ),
//-------- Outputs
// To External PHY (PIPE I/F)
.txp_data ( txp_data_ln0 ),
.txp_data_k ( txp_data_k_ln0 ),
.txp_elec_idle ( txp_elec_idle_ln0 ),
.txp_compliance ( txp_compliance_ln0 ),
.rxp_polarity ( rxp_polarity_ln0 ),
.txp_detect_rx_lb ( tx_detect_rx_lb ),
.reset_n ( reset_n ),
.power_down ( power_down ),
// From TX User Interface
.phy_ltssm_state ( phy_ltssm_state ),
.phy_ltssm_substate ( phy_ltssm_substate ),
.phy_pol_compliance ( phy_pol_compliance ),
.tx_rdy_vc0 ( tx_rdy_vc0),
.tx_ca_ph_vc0 ( tx_ca_ph_vc0),
.tx_ca_pd_vc0 ( tx_ca_pd_vc0),
.tx_ca_nph_vc0 ( tx_ca_nph_vc0),
.tx_ca_npd_vc0 ( tx_ca_npd_vc0),
.tx_ca_cplh_vc0 ( tx_ca_cplh_vc0),
.tx_ca_cpld_vc0 ( tx_ca_cpld_vc0),
.tx_ca_p_recheck_vc0 ( tx_ca_p_recheck_vc0 ),
.tx_ca_cpl_recheck_vc0 ( tx_ca_cpl_recheck_vc0 ),
.rx_data_vc0 ( rx_data_vc0),
.rx_st_vc0 ( rx_st_vc0),
.rx_end_vc0 ( rx_end_vc0),
.rx_us_req_vc0 ( rx_us_req_vc0 ),
.rx_malf_tlp_vc0 ( rx_malf_tlp_vc0 ),
.rx_bar_hit ( rx_bar_hit ),
.mm_enable ( mm_enable ) ,
.msi_enable ( msi_enable ) ,
// From Config Registers
.bus_num ( bus_num ) ,
.dev_num ( dev_num ) ,
.func_num ( func_num ) ,
.pm_power_state ( pm_power_state ) ,
.pme_en ( pme_en ) ,
.cmd_reg_out ( cmd_reg_out ),
.dev_cntl_out ( dev_cntl_out ),
.lnk_cntl_out ( lnk_cntl_out ),
// To ASPM implementation outside the IP
.tx_rbuf_empty (tx_rbuf_empty ), // Transmit retry buffer is empty
.tx_dllp_pend (tx_dllp_pend ), // DLPP is pending to be transmitted
.rx_tlp_rcvd (rx_tlp_rcvd ), // Received a TLP
// Datal Link Control SM Status
.dl_inactive ( dl_inactive ),
.dl_init ( dl_init ),
.dl_active ( dl_active ),
.dl_up ( dl_up )
);
endmodule
|
module sky130_fd_sc_lp__a32o (
X ,
A1,
A2,
A3,
B1,
B2
);
output X ;
input A1;
input A2;
input A3;
input B1;
input B2;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
|
module top();
// Inputs are registered
reg A;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 VGND = 1'b0;
#60 VNB = 1'b0;
#80 VPB = 1'b0;
#100 VPWR = 1'b0;
#120 A = 1'b1;
#140 VGND = 1'b1;
#160 VNB = 1'b1;
#180 VPB = 1'b1;
#200 VPWR = 1'b1;
#220 A = 1'b0;
#240 VGND = 1'b0;
#260 VNB = 1'b0;
#280 VPB = 1'b0;
#300 VPWR = 1'b0;
#320 VPWR = 1'b1;
#340 VPB = 1'b1;
#360 VNB = 1'b1;
#380 VGND = 1'b1;
#400 A = 1'b1;
#420 VPWR = 1'bx;
#440 VPB = 1'bx;
#460 VNB = 1'bx;
#480 VGND = 1'bx;
#500 A = 1'bx;
end
sky130_fd_sc_lp__dlymetal6s6s dut (.A(A), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .X(X));
endmodule
|
module sky130_fd_sc_hs__clkbuf_8 (
X ,
A ,
VPWR,
VGND
);
output X ;
input A ;
input VPWR;
input VGND;
sky130_fd_sc_hs__clkbuf base (
.X(X),
.A(A),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
|
module sky130_fd_sc_hs__clkbuf_8 (
X,
A
);
output X;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__clkbuf base (
.X(X),
.A(A)
);
endmodule
|
module MIPS_Single_Register(Rs_addr,Rt_addr,Rd_addr,Clk,Rd_write_byte_en,Rd_in,Rs_out,Rt_out)
input Clk;
input [4:0]Rs_addr,Rt_addr,Rd_addr;
input [7:0]Rd_in;
input Rd_write_byte_en;
output [7:0]Rs_out,Rt_out;
reg [7:0]register[31:0];
always @(negedge Clk)
begin
if(Rd_addr!=0 && Rd_write_byte_en)
register[Rd_addr][7:0] <= Rd_in[7:0];
end
assign Rs_out = register[Rs_addr];
assign Rt_out = register[Rt_addr];
endmodule
|
module MIPS_Register(Rs_addr,Rt_addr,Rd_addr,Clk,Rd_write_byte_en,Rd_in,Rs_out,Rt_out);
input Clk;
input [4:0]Rs_addr,Rt_addr,Rd_addr;
input [31:0]Rd_in;
input [3:0]Rd_write_byte_en;
output [31:0]Rs_out,Rt_out;
reg [31:0]register[31:0];
assign Rs_out = register[Rs_addr];
assign Rt_out = register[Rt_addr];
initial
begin
//register[1] = 1;
//register[2] = 100;
//register[3] = 0;
register[0] = 32'h0;
register[1] = 32'h11112345;
register[2] = 32'h2;
register[3] = 32'h3;
register[4] = 32'h4;
register[5] = 32'h55556789;
register[8] = 32'h88;
register[9] = 32'h5467_8932;
register[10] = 32'h3476_8906;
register[11] = 32'hfffa_bcde;
register[12] = 32'h6789_3954;
register[30] = 32'hffff_ffff;
register[31] = 32'h7fff_ffff;
end
always @(negedge Clk)
begin
if(Rd_addr!=0)
begin
case(Rd_write_byte_en)
4'b0001: register[Rd_addr][7:0] <= Rd_in[7:0];
4'b0010: register[Rd_addr][15:8] <= Rd_in[15:8];
4'b0011: register[Rd_addr][15:0] <= Rd_in[15:0];
4'b0100: register[Rd_addr][23:16] <= Rd_in[23:16];
4'b0101: begin register[Rd_addr][23:16] <= Rd_in[23:16]; register[Rd_addr][7:0] <= Rd_in[7:0];end
4'b0110: register[Rd_addr][23:8] <= Rd_in[23:8];
4'b0111: register[Rd_addr][23:0] <= Rd_in[23:0];
4'b1000: register[Rd_addr][31:24] <= Rd_in[31:24];
4'b1001: begin register[Rd_addr][31:24] <= Rd_in[31:24]; register[Rd_addr][7:0] <= Rd_in[7:0];end
4'b1010: begin register[Rd_addr][31:24] <= Rd_in[31:24]; register[Rd_addr][15:8] <= Rd_in[15:8];end
4'b1011: begin register[Rd_addr][31:24] <= Rd_in[31:24]; register[Rd_addr][15:0] <= Rd_in[15:0];end
4'b1100: register[Rd_addr][31:16] <= Rd_in[31:16];
4'b1101: begin register[Rd_addr][31:16] <= Rd_in[31:16]; register[Rd_addr][7:0] <= Rd_in[7:0];end
4'b1110: register[Rd_addr][31:8] <= Rd_in[31:8];
4'b1111: register[Rd_addr] <= Rd_in;
default:;
endcase
end
end
/*
MIPS_Single_Register(Rs_addr,Rt_addr,Rd_addr,Clk,Rd_write_byte_en[0],Rd_in[7:0],Rs_out[7:0],Rt_out[7:0]);
MIPS_Single_Register(Rs_addr,Rt_addr,Rd_addr,Clk,Rd_write_byte_en[1],Rd_in[15:8],Rs_out[15:8],Rt_out[15:8]);
MIPS_Single_Register(Rs_addr,Rt_addr,Rd_addr,Clk,Rd_write_byte_en[2],Rd_in[23:16],Rs_out[23:16],Rt_out[23:16]);
MIPS_Single_Register(Rs_addr,Rt_addr,Rd_addr,Clk,Rd_write_byte_en[3],Rd_in[31:24],Rs_out[31:24],Rt_out[31:24]);
*/
endmodule
|
module sky130_fd_sc_ms__o311a (
//# {{data|Data Signals}}
input A1,
input A2,
input A3,
input B1,
input C1,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
|
module pixel_writer
(
input clk,
input calib_done,
output reg clear_screen_done,
output pixel_wr_done,
input pixel_en,
input [7:0] pixel_rgb,
input [7:0] pixel_x,
input [7:0] pixel_y,
output reg mem_cmd_en,
output wire [2:0] mem_cmd_instr,
output reg [5:0] mem_cmd_bl,
output reg [29:0] mem_cmd_byte_addr,
input mem_cmd_empty,
input mem_cmd_full,
output reg mem_wr_en,
output reg [3:0] mem_wr_mask,
output reg [31:0] mem_wr_data,
input mem_wr_full,
input mem_wr_empty,
input [6:0] mem_wr_count,
input mem_wr_underrun,
input mem_wr_error
);
initial begin
clear_screen_done = 0;
mem_cmd_en = 0;
mem_cmd_bl = 6'b000000;
mem_cmd_byte_addr = { `GRAPHICS_MEM_PREFIX, 16'h0000 };
mem_wr_en = 0;
mem_wr_mask = 4'b0000;
mem_wr_data = 32'h00000000;
end
assign mem_cmd_instr = 3'b000; // write
// The pixel writer will have a state machine to talk to RAM
reg [1:0] state = `STATE_CLEAR_SCREEN_WRITE;
assign pixel_wr_done = `STATE_PIXEL_WRITE == state && !mem_cmd_full && !mem_wr_full;
reg [6:0] word_index = 0;
reg [7:0] line_index = 0;
always @ (posedge clk) begin
mem_cmd_en <= 0;
mem_wr_en <= 0;
if (calib_done) begin
case (state)
`STATE_CLEAR_SCREEN_WRITE: begin
mem_wr_en <= 1;
mem_wr_data <= 32'h00000000;
mem_wr_mask <= 4'b0000;
word_index <= word_index + 1;
if (word_index == 64) begin
word_index <= 0;
mem_wr_en <= 0;
mem_cmd_en <= 1;
mem_cmd_bl <= 6'b111111;
mem_cmd_byte_addr <= {
`GRAPHICS_MEM_PREFIX,
line_index,
8'b00000000
};
state <= `STATE_CLEAR_SCREEN_CMD;
end
end
`STATE_CLEAR_SCREEN_CMD: begin
if (mem_wr_empty) begin
if (line_index == 191) begin
clear_screen_done <= 1;
state <= `STATE_PIXEL_WRITE;
end else begin
line_index <= line_index + 1;
state <= `STATE_CLEAR_SCREEN_WRITE;
end
end
end
`STATE_PIXEL_WRITE: begin
if (pixel_en && pixel_wr_done) begin
mem_wr_en <= 1;
mem_wr_data <= {4{pixel_rgb}};
mem_wr_mask <= 0 == pixel_x[1:0] ? 4'b1110 :
1 == pixel_x[1:0] ? 4'b1101 :
2 == pixel_x[1:0] ? 4'b1011 : 4'b0111;
mem_cmd_byte_addr <= {
`GRAPHICS_MEM_PREFIX,
pixel_y, pixel_x[7:2], 2'b00
};
state <= `STATE_PIXEL_CMD;
end
end
`STATE_PIXEL_CMD: begin
mem_cmd_bl <= 6'b000000;
mem_cmd_en <= 1;
state <= `STATE_PIXEL_WRITE;
end
endcase
end
end
endmodule
|
module MULTIPLEXER_4_TO_1 #(
parameter BUS_WIDTH = 32
) (
input [BUS_WIDTH - 1 : 0] IN1 ,
input [BUS_WIDTH - 1 : 0] IN2 ,
input [BUS_WIDTH - 1 : 0] IN3 ,
input [BUS_WIDTH - 1 : 0] IN4 ,
input [1 : 0] SELECT ,
output [BUS_WIDTH - 1 : 0] OUT
);
reg [BUS_WIDTH - 1 : 0] out_reg;
always@(*)
begin
case(SELECT)
2'b00:
begin
out_reg = IN1;
end
2'b01:
begin
out_reg = IN2;
end
2'b10:
begin
out_reg = IN3;
end
2'b11:
begin
out_reg = IN4;
end
endcase
end
assign OUT = out_reg;
endmodule
|
module TemperatureMonitor_exdes(
DADDR_IN, // Address bus for the dynamic reconfiguration port
DCLK_IN, // Clock input for the dynamic reconfiguration port
DEN_IN, // Enable Signal for the dynamic reconfiguration port
DI_IN, // Input data bus for the dynamic reconfiguration port
DWE_IN, // Write Enable for the dynamic reconfiguration port
DO_OUT, // Output data bus for dynamic reconfiguration port
DRDY_OUT, // Data ready signal for the dynamic reconfiguration port
VP_IN, // Dedicated Analog Input Pair
VN_IN);
input VP_IN;
input VN_IN;
input [6:0] DADDR_IN;
input DCLK_IN;
input DEN_IN;
input [15:0] DI_IN;
input DWE_IN;
output [15:0] DO_OUT;
output DRDY_OUT;
wire GND_BIT;
wire [2:0] GND_BUS3;
wire FLOAT_VCCAUX;
wire FLOAT_VCCINT;
wire FLOAT_USER_TEMP_ALARM;
assign GND_BIT = 0;
TemperatureMonitor
sysmon_wiz_inst (
.DADDR_IN(DADDR_IN[6:0]),
.DCLK_IN(DCLK_IN),
.DEN_IN(DEN_IN),
.DI_IN(DI_IN[15:0]),
.DWE_IN(DWE_IN),
.DO_OUT(DO_OUT[15:0]),
.DRDY_OUT(DRDY_OUT),
.VP_IN(VP_IN),
.VN_IN(VN_IN)
);
endmodule
|
module top (input clk, stb, di, output do);
localparam integer DIN_N = 256;
localparam integer DOUT_N = 256;
reg [DIN_N-1:0] din;
wire [DOUT_N-1:0] dout;
reg [DIN_N-1:0] din_shr;
reg [DOUT_N-1:0] dout_shr;
always @(posedge clk) begin
din_shr <= {din_shr, di};
dout_shr <= {dout_shr, din_shr[DIN_N-1]};
if (stb) begin
din <= din_shr;
dout_shr <= dout;
end
end
assign do = dout_shr[DOUT_N-1];
roi roi (
.ci(din[0]),
.s0(din[1]),
.o0(dout[0])
);
endmodule
|
module roi (input ci, input s0, output o0);
wire [7:0] o, passthru_co, passthru_carry8_single_co;
(* LOC="SLICE_X67Y332", DONT_TOUCH *)
CARRY8 #(.CARRY_TYPE("DUAL_CY4"))
carry8_dual_inst (
.CI_TOP(passthru_carry8_single_co[7]),
.CI(1'b0),
.DI(4'b00000000),
.S({7'b0000000, s0}),
.O(o)
);
(* LOC="SLICE_X67Y331", DONT_TOUCH *)
CARRY8 #(.CARRY_TYPE("SINGLE_CY8"))
carry8_inst (
.CI(passthru_co[7]),
.CI_TOP(1'b0),
.DI(4'b00000000),
.S({7'b0000000, s0}),
.CO(passthru_carry8_single_co)
);
(* LOC="SLICE_X67Y330", DONT_TOUCH *)
CARRY8 #(.CARRY_TYPE("SINGLE_CY8"))
carry8_passthru (
.CI(1'b1),
.CI_TOP(1'b0),
.DI({ci, 7'b0000000}),
.S(8'b00000000),
.CO(passthru_co)
);
assign o0 = o;
endmodule
|
module sky130_fd_sc_hdll__tapvpwrvgnd ();
// No contents.
endmodule
|
module axi_traffic_gen_v2_0_7_static_top #
(
parameter C_S_AXI_DATA_WIDTH = 32 ,
parameter C_S_AXI_ID_WIDTH = 1 ,
parameter C_M_AXI_THREAD_ID_WIDTH = 1 ,
parameter C_M_AXI_AWUSER_WIDTH = 1 ,
parameter C_M_AXI_ARUSER_WIDTH = 1 ,
parameter C_M_AXI_DATA_WIDTH = 32 ,
parameter C_M_AXI_ADDR_WIDTH = 32 ,
parameter C_ATG_STATIC_WR_ADDRESS = 32'h12A0_0000 ,
parameter C_ATG_STATIC_RD_ADDRESS = 32'h13A0_0000 ,
parameter C_ATG_STATIC_WR_HIGH_ADDRESS = 32'h12A0_0FFF,
parameter C_ATG_STATIC_RD_HIGH_ADDRESS = 32'h13A0_0FFF,
parameter C_ATG_STATIC_INCR = 0 ,
parameter C_ATG_STATIC_EN_READ = 1 ,
parameter C_ATG_STATIC_EN_WRITE = 1 ,
parameter C_ATG_STATIC_FREE_RUN = 1 ,
parameter C_ATG_STATIC_TRANGAP = 32'd255 ,
parameter C_ATG_STATIC_RD_PIPELINE = 1 ,
parameter C_ATG_STATIC_WR_PIPELINE = 1 ,
parameter C_ATG_HLTP_MODE = 0 , //0-Custom,1-High Level Traffic.
parameter C_ATG_STATIC_LENGTH = 8'h3
) (
// system
input Clk ,
input rst_l ,
input core_global_start,
input core_global_stop ,
//Slave
input [C_S_AXI_ID_WIDTH-1:0] awid_s ,
input [31:0] awaddr_s ,
input awvalid_s ,
output awready_s ,
input wlast_s ,
input [C_S_AXI_DATA_WIDTH-1:0] wdata_s ,
input [C_S_AXI_DATA_WIDTH/8-1:0] wstrb_s ,
input wvalid_s ,
output wready_s ,
output [C_S_AXI_ID_WIDTH-1:0] bid_s ,
output [1:0] bresp_s ,
output bvalid_s ,
input bready_s ,
input [C_S_AXI_ID_WIDTH-1:0] arid_s ,
input [31:0] araddr_s ,
input arvalid_s ,
output arready_s ,
output [C_S_AXI_ID_WIDTH-1:0] rid_s ,
output rlast_s ,
output [C_S_AXI_DATA_WIDTH-1:0] rdata_s ,
output [1:0] rresp_s ,
output rvalid_s ,
input rready_s ,
//Master-write
output [C_M_AXI_THREAD_ID_WIDTH-1:0] awid_m ,
output [C_M_AXI_ADDR_WIDTH-1:0] awaddr_m ,
output [7:0] awlen_m ,
output [2:0] awsize_m ,
output [1:0] awburst_m ,
output [0:0] awlock_m ,
output [3:0] awcache_m ,
output [2:0] awprot_m ,
output [3:0] awqos_m ,
output [C_M_AXI_AWUSER_WIDTH-1:0] awuser_m ,
output awvalid_m ,
input awready_m ,
output wlast_m ,
output [C_M_AXI_DATA_WIDTH-1:0] wdata_m ,
output [C_M_AXI_DATA_WIDTH/8-1:0] wstrb_m ,
output wvalid_m ,
input wready_m ,
input [C_M_AXI_THREAD_ID_WIDTH-1:0] bid_m ,
input [1:0] bresp_m ,
input bvalid_m ,
output bready_m ,
//Master-read
output [C_M_AXI_THREAD_ID_WIDTH-1:0] arid_m ,
output [C_M_AXI_ADDR_WIDTH-1:0] araddr_m ,
output [7:0] arlen_m ,
output [2:0] arsize_m ,
output [1:0] arburst_m ,
output [0:0] arlock_m ,
output [3:0] arcache_m ,
output [2:0] arprot_m ,
output [3:0] arqos_m ,
output [C_M_AXI_ARUSER_WIDTH-1:0] aruser_m ,
output arvalid_m ,
input arready_m ,
//r
input [C_M_AXI_THREAD_ID_WIDTH-1:0] rid_m ,
input rlast_m ,
input [C_M_AXI_DATA_WIDTH-1:0] rdata_m ,
input [1:0] rresp_m ,
input rvalid_m ,
output rready_m
);
wire reg0_m_enable_ff ;
wire static_ctl_en ;
wire reg1_done ;
wire reset_reg1_done ;
wire reset_reg1_en ;
wire static_ctl_en_pulse ;
wire [31:0] static_mr_tran_cnt ;
wire [31:0] static_mw_tran_cnt ;
wire [31:0] reg5_glcnt ;
wire [7:0] static_len ;
wire reg2_length_req ;
wire reg0_m_enable_3ff ;
wire [127:0] cmd_out_mw ;
wire [127:0] cmd_out_mr ;
wire [C_M_AXI_DATA_WIDTH-1:0] mram_out ;
axi_traffic_gen_v2_0_7_static_regblk #(
.C_S_AXI_DATA_WIDTH (C_S_AXI_DATA_WIDTH ) ,
.C_ATG_STATIC_LENGTH(C_ATG_STATIC_LENGTH) ,
.C_S_AXI_ID_WIDTH (C_S_AXI_ID_WIDTH )
) static_regblk (
.Clk (Clk ),
.rst_l (rst_l ),
.core_global_start (core_global_start ),
.core_global_stop (core_global_stop ),
.awid_s (awid_s ),
.awaddr_s (awaddr_s ),
.awvalid_s (awvalid_s ),
.awready_s (awready_s ),
.wlast_s (wlast_s ),
.wdata_s (wdata_s ),
.wstrb_s (wstrb_s ),
.wvalid_s (wvalid_s ),
.wready_s (wready_s ),
.bid_s (bid_s ),
.bresp_s (bresp_s ),
.bvalid_s (bvalid_s ),
.bready_s (bready_s ),
.arid_s (arid_s ),
.araddr_s (araddr_s ),
.arvalid_s (arvalid_s ),
.arready_s (arready_s ),
.rid_s (rid_s ),
.rlast_s (rlast_s ),
.rdata_s (rdata_s ),
.rresp_s (rresp_s ),
.rvalid_s (rvalid_s ),
.rready_s (rready_s ),
.reg0_m_enable_ff (reg0_m_enable_ff ),
.static_ctl_en (static_ctl_en ),
.reg1_done (reg1_done ),
.reset_reg1_done (reset_reg1_done ),
.reset_reg1_en (reset_reg1_en ),
.static_ctl_en_pulse(static_ctl_en_pulse),
.static_mw_tran_cnt (static_mw_tran_cnt ),
.static_mr_tran_cnt (static_mr_tran_cnt ),
.static_len (static_len ),
.reg5_glbcnt (reg5_glcnt ),
.reg2_length_req (reg2_length_req ),
.reg0_m_enable_3ff (reg0_m_enable_3ff )
);
//New ST_CODE
axi_traffic_gen_v2_0_7_static_mrdwr #
(
.C_M_AXI_THREAD_ID_WIDTH ( C_M_AXI_THREAD_ID_WIDTH ),
.C_M_AXI_AWUSER_WIDTH ( C_M_AXI_AWUSER_WIDTH ),
.C_M_AXI_ARUSER_WIDTH ( C_M_AXI_ARUSER_WIDTH ),
.C_M_AXI_ADDR_WIDTH ( C_M_AXI_ADDR_WIDTH ),
.C_ATG_STATIC_RD_ADDRESS ( C_ATG_STATIC_RD_ADDRESS ),
.C_ATG_STATIC_WR_ADDRESS ( C_ATG_STATIC_WR_ADDRESS ),
.C_ATG_STATIC_WR_HIGH_ADDRESS(C_ATG_STATIC_WR_HIGH_ADDRESS),
.C_ATG_STATIC_RD_HIGH_ADDRESS(C_ATG_STATIC_RD_HIGH_ADDRESS),
.C_ATG_STATIC_INCR (C_ATG_STATIC_INCR ),
.C_ATG_STATIC_EN_READ ( C_ATG_STATIC_EN_READ ),
.C_ATG_STATIC_EN_WRITE ( C_ATG_STATIC_EN_WRITE ),
.C_ATG_STATIC_LENGTH ( C_ATG_STATIC_LENGTH ),
.C_ATG_STATIC_RD_PIPELINE( C_ATG_STATIC_RD_PIPELINE),
.C_ATG_STATIC_WR_PIPELINE( C_ATG_STATIC_WR_PIPELINE),
.C_ATG_STATIC_FREE_RUN ( C_ATG_STATIC_FREE_RUN ),
.C_ATG_STATIC_TRANGAP ( C_ATG_STATIC_TRANGAP ),
.C_ATG_HLTP_MODE (C_ATG_HLTP_MODE ),
.C_M_AXI_DATA_WIDTH ( C_M_AXI_DATA_WIDTH )
) static_mrdwr (
.Clk (Clk ),
.rst_l (rst_l ),
.awid_m (awid_m ),
.awaddr_m (awaddr_m ),
.awlen_m (awlen_m ),
.awsize_m (awsize_m ),
.awburst_m (awburst_m ),
.awlock_m (awlock_m ),
.awcache_m (awcache_m ),
.awprot_m (awprot_m ),
.awqos_m (awqos_m ),
.awuser_m (awuser_m ),
.awvalid_m (awvalid_m ),
.awready_m (awready_m ),
.wlast_m (wlast_m ),
.wdata_m (wdata_m ),
.wstrb_m (wstrb_m ),
.wvalid_m (wvalid_m ),
.wready_m (wready_m ),
.bid_m (bid_m ),
.bresp_m (bresp_m ),
.bvalid_m (bvalid_m ),
.bready_m (bready_m ),
.arid_m (arid_m ),
.araddr_m (araddr_m ),
.arlen_m (arlen_m ),
.arsize_m (arsize_m ),
.arburst_m (arburst_m ),
.arlock_m (arlock_m ),
.arcache_m (arcache_m ),
.arprot_m (arprot_m ),
.arqos_m (arqos_m ),
.aruser_m (aruser_m ),
.arvalid_m (arvalid_m ),
.arready_m (arready_m ),
.rid_m (rid_m ),
.rlast_m (rlast_m ),
.rdata_m (rdata_m ),
.rresp_m (rresp_m ),
.rvalid_m (rvalid_m ),
.rready_m (rready_m ),
.reg1_st_enable (static_ctl_en ),
.reg1_done (reg1_done ),
.reset_reg1_done (reset_reg1_done ),
.reset_reg1_en (reset_reg1_en ),
.reg2_length (static_len ),
.reg2_length_req(reg2_length_req),
.reg3_rdcnt (static_mr_tran_cnt),
.reg4_wrcnt (static_mw_tran_cnt ),
.reg5_glcnt (reg5_glcnt )
);
//New ST_CODE
//axi_traffic_gen_v2_0_7_static_cmdgen # (
// .C_ATG_STATIC_ADDRESS(C_ATG_STATIC_ADDRESS),
// .C_M_AXI_DATA_WIDTH (C_M_AXI_DATA_WIDTH ),
// .C_ATG_STATIC_LENGTH (C_ATG_STATIC_LENGTH )
//) static_cmdgen (
// .Clk (Clk ),
// .rst_l (rst_l ),
// .static_ctl_en(static_ctl_en),
// .static_len (static_len ),
// .cmd_out_mw (cmd_out_mw ),
// .cmd_data (mram_out ),
// .cmd_out_mr (cmd_out_mr )
//);
//
//
//axi_traffic_gen_v2_0_7_static_mw # (
// .C_M_AXI_THREAD_ID_WIDTH(C_M_AXI_THREAD_ID_WIDTH),
// .C_M_AXI_AWUSER_WIDTH (C_M_AXI_AWUSER_WIDTH ),
// .C_M_AXI_DATA_WIDTH (C_M_AXI_DATA_WIDTH )
//) static_mw (
// .Clk (Clk ),
// .rst_l (rst_l ),
// .awid_m (awid_m ),
// .awaddr_m (awaddr_m ),
// .awlen_m (awlen_m ),
// .awsize_m (awsize_m ),
// .awburst_m (awburst_m ),
// .awlock_m (awlock_m ),
// .awcache_m (awcache_m ),
// .awprot_m (awprot_m ),
// .awqos_m (awqos_m ),
// .awuser_m (awuser_m ),
// .awvalid_m (awvalid_m ),
// .awready_m (awready_m ),
// .wlast_m (wlast_m ),
// .wdata_m (wdata_m ),
// .wstrb_m (wstrb_m ),
// .wvalid_m (wvalid_m ),
// .wready_m (wready_m ),
// .bid_m (bid_m ),
// .bresp_m (bresp_m ),
// .bvalid_m (bvalid_m ),
// .bready_m (bready_m ),
// .mram_out (mram_out ),
// .reg0_m_enable_ff (reg0_m_enable_ff ),
// .reg0_m_enable_3ff (reg0_m_enable_3ff ),
// .static_ctl_en_pulse(static_ctl_en_pulse),
// .static_mw_tran_cnt (static_mw_tran_cnt ),
// .cmd_out_mw (cmd_out_mw )
//);
//
//axi_traffic_gen_v2_0_7_static_mr #
//(
// .C_M_AXI_THREAD_ID_WIDTH(C_M_AXI_THREAD_ID_WIDTH),
// .C_M_AXI_ARUSER_WIDTH (C_M_AXI_ARUSER_WIDTH ),
// .C_M_AXI_DATA_WIDTH (C_M_AXI_DATA_WIDTH )
//) static_mr (
// .Clk (Clk ),
// .rst_l (rst_l ),
// .arid_m (arid_m ),
// .araddr_m (araddr_m ),
// .arlen_m (arlen_m ),
// .arsize_m (arsize_m ),
// .arburst_m (arburst_m ),
// .arlock_m (arlock_m ),
// .arcache_m (arcache_m ),
// .arprot_m (arprot_m ),
// .arqos_m (arqos_m ),
// .aruser_m (aruser_m ),
// .arvalid_m (arvalid_m ),
// .arready_m (arready_m ),
// .rid_m (rid_m ),
// .rlast_m (rlast_m ),
// .rdata_m (rdata_m ),
// .rresp_m (rresp_m ),
// .rvalid_m (rvalid_m ),
// .rready_m (rready_m ),
// .reg0_m_enable_ff (reg0_m_enable_ff ),
// .reg0_m_enable_3ff (reg0_m_enable_3ff ),
// .static_ctl_en_pulse(static_ctl_en_pulse),
// .static_mr_tran_cnt (static_mr_tran_cnt ),
// .cmd_out_mr (cmd_out_mr )
//);
endmodule
|
module cx4_mul (
clk, p, a, b
)/* synthesis syn_black_box syn_noprune=1 */;
input clk;
output [47 : 0] p;
input [23 : 0] a;
input [23 : 0] b;
// synthesis translate_off
wire \blk00000001/sig000001fc ;
wire \blk00000001/sig000001fb ;
wire \blk00000001/sig000001fa ;
wire \blk00000001/sig000001f9 ;
wire \blk00000001/sig000001f8 ;
wire \blk00000001/sig000001f7 ;
wire \blk00000001/sig000001f6 ;
wire \blk00000001/sig000001f5 ;
wire \blk00000001/sig000001f4 ;
wire \blk00000001/sig000001f3 ;
wire \blk00000001/sig000001f2 ;
wire \blk00000001/sig000001f1 ;
wire \blk00000001/sig000001f0 ;
wire \blk00000001/sig000001ef ;
wire \blk00000001/sig000001ee ;
wire \blk00000001/sig000001ed ;
wire \blk00000001/sig000001ec ;
wire \blk00000001/sig000001eb ;
wire \blk00000001/sig000001ea ;
wire \blk00000001/sig000001e9 ;
wire \blk00000001/sig000001e8 ;
wire \blk00000001/sig000001e7 ;
wire \blk00000001/sig000001e6 ;
wire \blk00000001/sig000001e5 ;
wire \blk00000001/sig000001e4 ;
wire \blk00000001/sig000001e3 ;
wire \blk00000001/sig000001e2 ;
wire \blk00000001/sig000001e1 ;
wire \blk00000001/sig000001e0 ;
wire \blk00000001/sig000001df ;
wire \blk00000001/sig000001de ;
wire \blk00000001/sig000001dd ;
wire \blk00000001/sig000001dc ;
wire \blk00000001/sig000001db ;
wire \blk00000001/sig000001da ;
wire \blk00000001/sig000001d9 ;
wire \blk00000001/sig000001d8 ;
wire \blk00000001/sig000001d7 ;
wire \blk00000001/sig000001d6 ;
wire \blk00000001/sig000001d5 ;
wire \blk00000001/sig000001d4 ;
wire \blk00000001/sig000001d3 ;
wire \blk00000001/sig000001d2 ;
wire \blk00000001/sig000001d1 ;
wire \blk00000001/sig000001d0 ;
wire \blk00000001/sig000001cf ;
wire \blk00000001/sig000001ce ;
wire \blk00000001/sig000001cd ;
wire \blk00000001/sig000001cc ;
wire \blk00000001/sig000001cb ;
wire \blk00000001/sig000001ca ;
wire \blk00000001/sig000001c9 ;
wire \blk00000001/sig000001c8 ;
wire \blk00000001/sig000001c7 ;
wire \blk00000001/sig000001c6 ;
wire \blk00000001/sig000001c5 ;
wire \blk00000001/sig000001c4 ;
wire \blk00000001/sig000001c3 ;
wire \blk00000001/sig000001c2 ;
wire \blk00000001/sig000001c1 ;
wire \blk00000001/sig000001c0 ;
wire \blk00000001/sig000001bf ;
wire \blk00000001/sig000001be ;
wire \blk00000001/sig000001bd ;
wire \blk00000001/sig000001bc ;
wire \blk00000001/sig000001bb ;
wire \blk00000001/sig000001ba ;
wire \blk00000001/sig000001b9 ;
wire \blk00000001/sig000001b8 ;
wire \blk00000001/sig000001b7 ;
wire \blk00000001/sig000001b6 ;
wire \blk00000001/sig000001b5 ;
wire \blk00000001/sig000001b4 ;
wire \blk00000001/sig000001b3 ;
wire \blk00000001/sig000001b2 ;
wire \blk00000001/sig000001b1 ;
wire \blk00000001/sig000001b0 ;
wire \blk00000001/sig000001af ;
wire \blk00000001/sig000001ae ;
wire \blk00000001/sig000001ad ;
wire \blk00000001/sig000001ac ;
wire \blk00000001/sig000001ab ;
wire \blk00000001/sig000001aa ;
wire \blk00000001/sig000001a9 ;
wire \blk00000001/sig000001a8 ;
wire \blk00000001/sig000001a7 ;
wire \blk00000001/sig000001a6 ;
wire \blk00000001/sig000001a5 ;
wire \blk00000001/sig000001a4 ;
wire \blk00000001/sig000001a3 ;
wire \blk00000001/sig000001a2 ;
wire \blk00000001/sig000001a1 ;
wire \blk00000001/sig000001a0 ;
wire \blk00000001/sig0000019f ;
wire \blk00000001/sig0000019e ;
wire \blk00000001/sig0000019d ;
wire \blk00000001/sig0000019c ;
wire \blk00000001/sig0000019b ;
wire \blk00000001/sig0000019a ;
wire \blk00000001/sig00000199 ;
wire \blk00000001/sig00000198 ;
wire \blk00000001/sig00000197 ;
wire \blk00000001/sig00000196 ;
wire \blk00000001/sig00000195 ;
wire \blk00000001/sig00000194 ;
wire \blk00000001/sig00000193 ;
wire \blk00000001/sig00000192 ;
wire \blk00000001/sig00000191 ;
wire \blk00000001/sig00000190 ;
wire \blk00000001/sig0000018f ;
wire \blk00000001/sig0000018e ;
wire \blk00000001/sig0000018d ;
wire \blk00000001/sig0000018c ;
wire \blk00000001/sig0000018b ;
wire \blk00000001/sig0000018a ;
wire \blk00000001/sig00000189 ;
wire \blk00000001/sig00000188 ;
wire \blk00000001/sig00000187 ;
wire \blk00000001/sig00000186 ;
wire \blk00000001/sig00000185 ;
wire \blk00000001/sig00000184 ;
wire \blk00000001/sig00000183 ;
wire \blk00000001/sig00000182 ;
wire \blk00000001/sig00000181 ;
wire \blk00000001/sig00000180 ;
wire \blk00000001/sig0000017f ;
wire \blk00000001/sig0000017e ;
wire \blk00000001/sig0000017d ;
wire \blk00000001/sig0000017c ;
wire \blk00000001/sig0000017b ;
wire \blk00000001/sig0000017a ;
wire \blk00000001/sig00000179 ;
wire \blk00000001/sig00000178 ;
wire \blk00000001/sig00000177 ;
wire \blk00000001/sig00000176 ;
wire \blk00000001/sig00000175 ;
wire \blk00000001/sig00000174 ;
wire \blk00000001/sig00000173 ;
wire \blk00000001/sig00000172 ;
wire \blk00000001/sig00000171 ;
wire \blk00000001/sig00000170 ;
wire \blk00000001/sig0000016f ;
wire \blk00000001/sig0000016e ;
wire \blk00000001/sig0000016d ;
wire \blk00000001/sig0000016c ;
wire \blk00000001/sig0000016b ;
wire \blk00000001/sig0000016a ;
wire \blk00000001/sig00000169 ;
wire \blk00000001/sig00000168 ;
wire \blk00000001/sig00000167 ;
wire \blk00000001/sig00000166 ;
wire \blk00000001/sig00000165 ;
wire \blk00000001/sig00000164 ;
wire \blk00000001/sig00000163 ;
wire \blk00000001/sig00000162 ;
wire \blk00000001/sig00000161 ;
wire \blk00000001/sig00000160 ;
wire \blk00000001/sig0000015f ;
wire \blk00000001/sig0000015e ;
wire \blk00000001/sig0000015d ;
wire \blk00000001/sig0000015c ;
wire \blk00000001/sig0000015b ;
wire \blk00000001/sig0000015a ;
wire \blk00000001/sig00000159 ;
wire \blk00000001/sig00000158 ;
wire \blk00000001/sig00000157 ;
wire \blk00000001/sig00000156 ;
wire \blk00000001/sig00000155 ;
wire \blk00000001/sig00000154 ;
wire \blk00000001/sig00000153 ;
wire \blk00000001/sig00000152 ;
wire \blk00000001/sig00000151 ;
wire \blk00000001/sig00000150 ;
wire \blk00000001/sig0000014f ;
wire \blk00000001/sig0000014e ;
wire \blk00000001/sig0000014d ;
wire \blk00000001/sig0000014c ;
wire \blk00000001/sig0000014b ;
wire \blk00000001/sig0000014a ;
wire \blk00000001/sig00000149 ;
wire \blk00000001/sig00000148 ;
wire \blk00000001/sig00000147 ;
wire \blk00000001/sig00000146 ;
wire \blk00000001/sig00000145 ;
wire \blk00000001/sig00000144 ;
wire \blk00000001/sig00000143 ;
wire \blk00000001/sig00000142 ;
wire \blk00000001/sig00000141 ;
wire \blk00000001/sig00000140 ;
wire \blk00000001/sig0000013f ;
wire \blk00000001/sig0000013e ;
wire \blk00000001/sig0000013d ;
wire \blk00000001/sig0000013c ;
wire \blk00000001/sig0000013b ;
wire \blk00000001/sig0000013a ;
wire \blk00000001/sig00000139 ;
wire \blk00000001/sig00000138 ;
wire \blk00000001/sig00000137 ;
wire \blk00000001/sig00000136 ;
wire \blk00000001/sig00000135 ;
wire \blk00000001/sig00000134 ;
wire \blk00000001/sig00000133 ;
wire \blk00000001/sig00000132 ;
wire \blk00000001/sig00000131 ;
wire \blk00000001/sig00000130 ;
wire \blk00000001/sig0000012f ;
wire \blk00000001/sig0000012e ;
wire \blk00000001/sig0000012d ;
wire \blk00000001/sig0000012c ;
wire \blk00000001/sig0000012b ;
wire \blk00000001/sig0000012a ;
wire \blk00000001/sig00000129 ;
wire \blk00000001/sig00000128 ;
wire \blk00000001/sig00000127 ;
wire \blk00000001/sig00000126 ;
wire \blk00000001/sig00000125 ;
wire \blk00000001/sig00000124 ;
wire \blk00000001/sig00000123 ;
wire \blk00000001/sig00000122 ;
wire \blk00000001/sig00000121 ;
wire \blk00000001/sig00000120 ;
wire \blk00000001/sig0000011f ;
wire \blk00000001/sig0000011e ;
wire \blk00000001/sig0000011d ;
wire \blk00000001/sig0000011c ;
wire \blk00000001/sig0000011b ;
wire \blk00000001/sig0000011a ;
wire \blk00000001/sig00000119 ;
wire \blk00000001/sig00000118 ;
wire \blk00000001/sig00000117 ;
wire \blk00000001/sig00000116 ;
wire \blk00000001/sig00000115 ;
wire \blk00000001/sig00000114 ;
wire \blk00000001/sig00000113 ;
wire \blk00000001/sig00000112 ;
wire \blk00000001/sig00000111 ;
wire \blk00000001/sig00000110 ;
wire \blk00000001/sig0000010f ;
wire \blk00000001/sig0000010e ;
wire \blk00000001/sig0000010d ;
wire \blk00000001/sig0000010c ;
wire \blk00000001/sig0000010b ;
wire \blk00000001/sig0000010a ;
wire \blk00000001/sig00000109 ;
wire \blk00000001/sig00000108 ;
wire \blk00000001/sig00000107 ;
wire \blk00000001/sig00000106 ;
wire \blk00000001/sig00000105 ;
wire \blk00000001/sig00000104 ;
wire \blk00000001/sig00000103 ;
wire \blk00000001/sig00000102 ;
wire \blk00000001/sig00000101 ;
wire \blk00000001/sig00000100 ;
wire \blk00000001/sig000000ff ;
wire \blk00000001/sig000000fe ;
wire \blk00000001/sig000000fd ;
wire \blk00000001/sig000000fc ;
wire \blk00000001/sig000000fb ;
wire \blk00000001/sig000000fa ;
wire \blk00000001/sig000000f9 ;
wire \blk00000001/sig000000f8 ;
wire \blk00000001/sig000000f7 ;
wire \blk00000001/sig000000f6 ;
wire \blk00000001/sig000000f5 ;
wire \blk00000001/sig000000f4 ;
wire \blk00000001/sig000000f3 ;
wire \blk00000001/sig000000f2 ;
wire \blk00000001/sig000000f1 ;
wire \blk00000001/sig000000f0 ;
wire \blk00000001/sig000000ef ;
wire \blk00000001/sig000000ee ;
wire \blk00000001/sig000000ed ;
wire \blk00000001/sig000000ec ;
wire \blk00000001/sig000000eb ;
wire \blk00000001/sig000000ea ;
wire \blk00000001/sig000000e9 ;
wire \blk00000001/sig000000e8 ;
wire \blk00000001/sig000000e7 ;
wire \blk00000001/sig000000e6 ;
wire \blk00000001/sig000000e5 ;
wire \blk00000001/sig000000e4 ;
wire \blk00000001/sig000000e3 ;
wire \blk00000001/sig000000e2 ;
wire \blk00000001/sig000000e1 ;
wire \blk00000001/sig000000e0 ;
wire \blk00000001/sig000000df ;
wire \blk00000001/sig000000de ;
wire \blk00000001/sig000000dd ;
wire \blk00000001/sig000000dc ;
wire \blk00000001/sig000000db ;
wire \blk00000001/sig000000da ;
wire \blk00000001/sig000000d9 ;
wire \blk00000001/sig000000d8 ;
wire \blk00000001/sig000000d7 ;
wire \blk00000001/sig000000d6 ;
wire \blk00000001/sig000000d5 ;
wire \blk00000001/sig000000d4 ;
wire \blk00000001/sig000000d3 ;
wire \blk00000001/sig000000d2 ;
wire \blk00000001/sig000000d1 ;
wire \blk00000001/sig000000d0 ;
wire \blk00000001/sig000000cf ;
wire \blk00000001/sig000000ce ;
wire \blk00000001/sig000000cd ;
wire \blk00000001/sig000000cc ;
wire \blk00000001/sig000000cb ;
wire \blk00000001/sig000000ca ;
wire \blk00000001/sig000000c9 ;
wire \blk00000001/sig000000c8 ;
wire \blk00000001/sig000000c7 ;
wire \blk00000001/sig000000c6 ;
wire \blk00000001/sig000000c5 ;
wire \blk00000001/sig000000c4 ;
wire \blk00000001/sig000000c3 ;
wire \blk00000001/sig000000c2 ;
wire \blk00000001/sig000000c1 ;
wire \blk00000001/sig000000c0 ;
wire \blk00000001/sig000000bf ;
wire \blk00000001/sig000000be ;
wire \blk00000001/sig000000bd ;
wire \blk00000001/sig000000bc ;
wire \blk00000001/sig000000bb ;
wire \blk00000001/sig000000ba ;
wire \blk00000001/sig000000b9 ;
wire \blk00000001/sig000000b8 ;
wire \blk00000001/sig000000b7 ;
wire \blk00000001/sig000000b6 ;
wire \blk00000001/sig000000b5 ;
wire \blk00000001/sig000000b4 ;
wire \blk00000001/sig000000b3 ;
wire \blk00000001/sig000000b2 ;
wire \blk00000001/sig000000b1 ;
wire \blk00000001/sig000000b0 ;
wire \blk00000001/sig000000af ;
wire \blk00000001/sig000000ae ;
wire \blk00000001/sig000000ad ;
wire \blk00000001/sig000000ac ;
wire \blk00000001/sig000000ab ;
wire \blk00000001/sig000000aa ;
wire \blk00000001/sig000000a9 ;
wire \blk00000001/sig000000a8 ;
wire \blk00000001/sig000000a7 ;
wire \blk00000001/sig000000a6 ;
wire \blk00000001/sig000000a5 ;
wire \blk00000001/sig000000a4 ;
wire \blk00000001/sig000000a3 ;
wire \blk00000001/sig000000a2 ;
wire \blk00000001/sig000000a1 ;
wire \blk00000001/sig000000a0 ;
wire \blk00000001/sig0000009f ;
wire \blk00000001/sig0000009e ;
wire \blk00000001/sig0000009d ;
wire \blk00000001/sig0000009c ;
wire \blk00000001/sig0000009b ;
wire \blk00000001/sig0000009a ;
wire \blk00000001/sig00000099 ;
wire \blk00000001/sig00000098 ;
wire \blk00000001/sig00000097 ;
wire \blk00000001/sig00000096 ;
wire \blk00000001/sig00000095 ;
wire \blk00000001/sig00000094 ;
wire \blk00000001/sig00000093 ;
wire \blk00000001/sig00000092 ;
wire \blk00000001/sig00000091 ;
wire \blk00000001/sig00000090 ;
wire \blk00000001/sig0000008f ;
wire \blk00000001/sig0000008e ;
wire \blk00000001/sig0000008d ;
wire \blk00000001/sig0000008c ;
wire \blk00000001/sig0000008b ;
wire \blk00000001/sig0000008a ;
wire \blk00000001/sig00000089 ;
wire \blk00000001/sig00000088 ;
wire \blk00000001/sig00000087 ;
wire \blk00000001/sig00000086 ;
wire \blk00000001/sig00000085 ;
wire \blk00000001/sig00000084 ;
wire \blk00000001/sig00000083 ;
wire \blk00000001/sig00000082 ;
wire \blk00000001/sig00000081 ;
wire \blk00000001/sig00000080 ;
wire \blk00000001/sig0000007f ;
wire \blk00000001/sig0000007e ;
wire \blk00000001/sig0000007d ;
wire \blk00000001/sig0000007c ;
wire \blk00000001/sig0000007b ;
wire \blk00000001/sig0000007a ;
wire \blk00000001/sig00000079 ;
wire \blk00000001/sig00000078 ;
wire \blk00000001/sig00000077 ;
wire \blk00000001/sig00000076 ;
wire \blk00000001/sig00000075 ;
wire \blk00000001/sig00000074 ;
wire \blk00000001/sig00000073 ;
wire \blk00000001/sig00000072 ;
wire \blk00000001/sig00000071 ;
wire \blk00000001/sig00000070 ;
wire \blk00000001/sig0000006f ;
wire \blk00000001/sig0000006e ;
wire \blk00000001/sig0000006d ;
wire \blk00000001/sig0000006c ;
wire \blk00000001/sig0000006b ;
wire \blk00000001/sig0000006a ;
wire \blk00000001/sig00000069 ;
wire \blk00000001/sig00000068 ;
wire \blk00000001/sig00000067 ;
wire \blk00000001/sig00000066 ;
wire \blk00000001/sig00000065 ;
wire \blk00000001/sig00000064 ;
wire \blk00000001/sig00000063 ;
wire \blk00000001/sig00000062 ;
wire \blk00000001/sig00000061 ;
wire \blk00000001/sig00000060 ;
wire \blk00000001/sig0000005f ;
wire \blk00000001/sig0000005e ;
wire \blk00000001/sig0000005d ;
wire \blk00000001/sig0000005c ;
wire \blk00000001/sig0000005b ;
wire \blk00000001/sig0000005a ;
wire \blk00000001/sig00000059 ;
wire \blk00000001/sig00000058 ;
wire \blk00000001/sig00000057 ;
wire \blk00000001/sig00000056 ;
wire \blk00000001/sig00000055 ;
wire \blk00000001/sig00000054 ;
wire \blk00000001/sig00000053 ;
wire \blk00000001/sig00000052 ;
wire \blk00000001/sig00000051 ;
wire \blk00000001/sig00000050 ;
wire \blk00000001/sig0000004f ;
wire \blk00000001/sig0000004e ;
wire \blk00000001/sig0000004d ;
wire \blk00000001/sig0000004c ;
wire \blk00000001/sig0000004b ;
wire \blk00000001/sig0000004a ;
wire \blk00000001/sig00000049 ;
wire \blk00000001/sig00000048 ;
wire \blk00000001/sig00000047 ;
wire \blk00000001/sig00000046 ;
wire \blk00000001/sig00000045 ;
wire \blk00000001/sig00000044 ;
wire \blk00000001/sig00000043 ;
wire \blk00000001/sig00000042 ;
wire \blk00000001/sig00000041 ;
wire \blk00000001/sig00000040 ;
wire \blk00000001/sig0000003f ;
wire \blk00000001/sig0000003e ;
wire \blk00000001/sig0000003d ;
wire \blk00000001/sig0000003c ;
wire \blk00000001/sig0000003b ;
wire \blk00000001/sig0000003a ;
wire \blk00000001/sig00000039 ;
wire \blk00000001/sig00000038 ;
wire \blk00000001/sig00000037 ;
wire \blk00000001/sig00000036 ;
wire \blk00000001/sig00000035 ;
wire \blk00000001/sig00000034 ;
wire \blk00000001/sig00000033 ;
wire \blk00000001/sig00000032 ;
wire \NLW_blk00000001/blk00000007_P<35>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000006_P<35>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000006_P<34>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000006_P<33>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000006_P<32>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000006_P<31>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000006_P<30>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000006_P<29>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000006_P<28>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000006_P<27>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000006_P<26>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000006_P<25>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000006_P<24>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000005_P<35>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000005_P<34>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000005_P<33>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000005_P<32>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000005_P<31>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000005_P<30>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000005_P<29>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000005_P<28>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000005_P<27>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000005_P<26>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000005_P<25>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000005_P<24>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000004_P<35>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000004_P<34>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000004_P<33>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000004_P<32>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000004_P<31>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000004_P<30>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000004_P<29>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000004_P<28>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000004_P<27>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000004_P<26>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000004_P<25>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000004_P<24>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000004_P<23>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000004_P<22>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000004_P<21>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000004_P<20>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000004_P<19>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000004_P<18>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000004_P<17>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000004_P<16>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000004_P<15>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000004_P<14>_UNCONNECTED ;
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk0000019f (
.C(clk),
.D(\blk00000001/sig000000d0 ),
.Q(\blk00000001/sig000000e1 )
);
SRL16 #(
.INIT ( 16'h0000 ))
\blk00000001/blk0000019e (
.A0(\blk00000001/sig00000043 ),
.A1(\blk00000001/sig00000043 ),
.A2(\blk00000001/sig00000043 ),
.A3(\blk00000001/sig00000043 ),
.CLK(clk),
.D(\blk00000001/sig0000012d ),
.Q(\blk00000001/sig000000d0 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk0000019d (
.C(clk),
.D(\blk00000001/sig000000d1 ),
.Q(\blk00000001/sig000000e2 )
);
SRL16 #(
.INIT ( 16'h0000 ))
\blk00000001/blk0000019c (
.A0(\blk00000001/sig00000043 ),
.A1(\blk00000001/sig00000043 ),
.A2(\blk00000001/sig00000043 ),
.A3(\blk00000001/sig00000043 ),
.CLK(clk),
.D(\blk00000001/sig00000138 ),
.Q(\blk00000001/sig000000d1 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk0000019b (
.C(clk),
.D(\blk00000001/sig000000d9 ),
.Q(\blk00000001/sig000000ea )
);
SRL16 #(
.INIT ( 16'h0000 ))
\blk00000001/blk0000019a (
.A0(\blk00000001/sig00000043 ),
.A1(\blk00000001/sig00000043 ),
.A2(\blk00000001/sig00000043 ),
.A3(\blk00000001/sig00000043 ),
.CLK(clk),
.D(\blk00000001/sig0000013d ),
.Q(\blk00000001/sig000000d9 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000199 (
.C(clk),
.D(\blk00000001/sig000000da ),
.Q(\blk00000001/sig000000eb )
);
SRL16 #(
.INIT ( 16'h0000 ))
\blk00000001/blk00000198 (
.A0(\blk00000001/sig00000043 ),
.A1(\blk00000001/sig00000043 ),
.A2(\blk00000001/sig00000043 ),
.A3(\blk00000001/sig00000043 ),
.CLK(clk),
.D(\blk00000001/sig0000013e ),
.Q(\blk00000001/sig000000da )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000197 (
.C(clk),
.D(\blk00000001/sig000000db ),
.Q(\blk00000001/sig000000ec )
);
SRL16 #(
.INIT ( 16'h0000 ))
\blk00000001/blk00000196 (
.A0(\blk00000001/sig00000043 ),
.A1(\blk00000001/sig00000043 ),
.A2(\blk00000001/sig00000043 ),
.A3(\blk00000001/sig00000043 ),
.CLK(clk),
.D(\blk00000001/sig0000013f ),
.Q(\blk00000001/sig000000db )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000195 (
.C(clk),
.D(\blk00000001/sig000000dc ),
.Q(\blk00000001/sig000000ed )
);
SRL16 #(
.INIT ( 16'h0000 ))
\blk00000001/blk00000194 (
.A0(\blk00000001/sig00000043 ),
.A1(\blk00000001/sig00000043 ),
.A2(\blk00000001/sig00000043 ),
.A3(\blk00000001/sig00000043 ),
.CLK(clk),
.D(\blk00000001/sig00000140 ),
.Q(\blk00000001/sig000000dc )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000193 (
.C(clk),
.D(\blk00000001/sig000000dd ),
.Q(\blk00000001/sig000000ee )
);
SRL16 #(
.INIT ( 16'h0000 ))
\blk00000001/blk00000192 (
.A0(\blk00000001/sig00000043 ),
.A1(\blk00000001/sig00000043 ),
.A2(\blk00000001/sig00000043 ),
.A3(\blk00000001/sig00000043 ),
.CLK(clk),
.D(\blk00000001/sig00000141 ),
.Q(\blk00000001/sig000000dd )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000191 (
.C(clk),
.D(\blk00000001/sig000000de ),
.Q(\blk00000001/sig000000ef )
);
SRL16 #(
.INIT ( 16'h0000 ))
\blk00000001/blk00000190 (
.A0(\blk00000001/sig00000043 ),
.A1(\blk00000001/sig00000043 ),
.A2(\blk00000001/sig00000043 ),
.A3(\blk00000001/sig00000043 ),
.CLK(clk),
.D(\blk00000001/sig00000142 ),
.Q(\blk00000001/sig000000de )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk0000018f (
.C(clk),
.D(\blk00000001/sig000000df ),
.Q(\blk00000001/sig000000f0 )
);
SRL16 #(
.INIT ( 16'h0000 ))
\blk00000001/blk0000018e (
.A0(\blk00000001/sig00000043 ),
.A1(\blk00000001/sig00000043 ),
.A2(\blk00000001/sig00000043 ),
.A3(\blk00000001/sig00000043 ),
.CLK(clk),
.D(\blk00000001/sig00000143 ),
.Q(\blk00000001/sig000000df )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk0000018d (
.C(clk),
.D(\blk00000001/sig000000e0 ),
.Q(\blk00000001/sig000000f1 )
);
SRL16 #(
.INIT ( 16'h0000 ))
\blk00000001/blk0000018c (
.A0(\blk00000001/sig00000043 ),
.A1(\blk00000001/sig00000043 ),
.A2(\blk00000001/sig00000043 ),
.A3(\blk00000001/sig00000043 ),
.CLK(clk),
.D(\blk00000001/sig00000144 ),
.Q(\blk00000001/sig000000e0 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk0000018b (
.C(clk),
.D(\blk00000001/sig000000d2 ),
.Q(\blk00000001/sig000000e3 )
);
SRL16 #(
.INIT ( 16'h0000 ))
\blk00000001/blk0000018a (
.A0(\blk00000001/sig00000043 ),
.A1(\blk00000001/sig00000043 ),
.A2(\blk00000001/sig00000043 ),
.A3(\blk00000001/sig00000043 ),
.CLK(clk),
.D(\blk00000001/sig0000012e ),
.Q(\blk00000001/sig000000d2 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000189 (
.C(clk),
.D(\blk00000001/sig000000d3 ),
.Q(\blk00000001/sig000000e4 )
);
SRL16 #(
.INIT ( 16'h0000 ))
\blk00000001/blk00000188 (
.A0(\blk00000001/sig00000043 ),
.A1(\blk00000001/sig00000043 ),
.A2(\blk00000001/sig00000043 ),
.A3(\blk00000001/sig00000043 ),
.CLK(clk),
.D(\blk00000001/sig0000012f ),
.Q(\blk00000001/sig000000d3 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000187 (
.C(clk),
.D(\blk00000001/sig000000d4 ),
.Q(\blk00000001/sig000000e5 )
);
SRL16 #(
.INIT ( 16'h0000 ))
\blk00000001/blk00000186 (
.A0(\blk00000001/sig00000043 ),
.A1(\blk00000001/sig00000043 ),
.A2(\blk00000001/sig00000043 ),
.A3(\blk00000001/sig00000043 ),
.CLK(clk),
.D(\blk00000001/sig00000130 ),
.Q(\blk00000001/sig000000d4 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000185 (
.C(clk),
.D(\blk00000001/sig000000d5 ),
.Q(\blk00000001/sig000000e6 )
);
SRL16 #(
.INIT ( 16'h0000 ))
\blk00000001/blk00000184 (
.A0(\blk00000001/sig00000043 ),
.A1(\blk00000001/sig00000043 ),
.A2(\blk00000001/sig00000043 ),
.A3(\blk00000001/sig00000043 ),
.CLK(clk),
.D(\blk00000001/sig00000131 ),
.Q(\blk00000001/sig000000d5 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000183 (
.C(clk),
.D(\blk00000001/sig000000d7 ),
.Q(\blk00000001/sig000000e8 )
);
SRL16 #(
.INIT ( 16'h0000 ))
\blk00000001/blk00000182 (
.A0(\blk00000001/sig00000043 ),
.A1(\blk00000001/sig00000043 ),
.A2(\blk00000001/sig00000043 ),
.A3(\blk00000001/sig00000043 ),
.CLK(clk),
.D(\blk00000001/sig00000133 ),
.Q(\blk00000001/sig000000d7 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000181 (
.C(clk),
.D(\blk00000001/sig000000d8 ),
.Q(\blk00000001/sig000000e9 )
);
SRL16 #(
.INIT ( 16'h0000 ))
\blk00000001/blk00000180 (
.A0(\blk00000001/sig00000043 ),
.A1(\blk00000001/sig00000043 ),
.A2(\blk00000001/sig00000043 ),
.A3(\blk00000001/sig00000043 ),
.CLK(clk),
.D(\blk00000001/sig00000134 ),
.Q(\blk00000001/sig000000d8 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk0000017f (
.C(clk),
.D(\blk00000001/sig000000d6 ),
.Q(\blk00000001/sig000000e7 )
);
SRL16 #(
.INIT ( 16'h0000 ))
\blk00000001/blk0000017e (
.A0(\blk00000001/sig00000043 ),
.A1(\blk00000001/sig00000043 ),
.A2(\blk00000001/sig00000043 ),
.A3(\blk00000001/sig00000043 ),
.CLK(clk),
.D(\blk00000001/sig00000132 ),
.Q(\blk00000001/sig000000d6 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk0000017d (
.C(clk),
.D(\blk00000001/sig00000032 ),
.Q(p[0])
);
SRL16 #(
.INIT ( 16'h0000 ))
\blk00000001/blk0000017c (
.A0(\blk00000001/sig00000044 ),
.A1(\blk00000001/sig00000043 ),
.A2(\blk00000001/sig00000043 ),
.A3(\blk00000001/sig00000043 ),
.CLK(clk),
.D(\blk00000001/sig000000f2 ),
.Q(\blk00000001/sig00000032 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk0000017b (
.C(clk),
.D(\blk00000001/sig00000033 ),
.Q(p[1])
);
SRL16 #(
.INIT ( 16'h0000 ))
\blk00000001/blk0000017a (
.A0(\blk00000001/sig00000044 ),
.A1(\blk00000001/sig00000043 ),
.A2(\blk00000001/sig00000043 ),
.A3(\blk00000001/sig00000043 ),
.CLK(clk),
.D(\blk00000001/sig000000fd ),
.Q(\blk00000001/sig00000033 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000179 (
.C(clk),
.D(\blk00000001/sig0000003b ),
.Q(p[2])
);
SRL16 #(
.INIT ( 16'h0000 ))
\blk00000001/blk00000178 (
.A0(\blk00000001/sig00000044 ),
.A1(\blk00000001/sig00000043 ),
.A2(\blk00000001/sig00000043 ),
.A3(\blk00000001/sig00000043 ),
.CLK(clk),
.D(\blk00000001/sig00000108 ),
.Q(\blk00000001/sig0000003b )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000177 (
.C(clk),
.D(\blk00000001/sig0000003c ),
.Q(p[3])
);
SRL16 #(
.INIT ( 16'h0000 ))
\blk00000001/blk00000176 (
.A0(\blk00000001/sig00000044 ),
.A1(\blk00000001/sig00000043 ),
.A2(\blk00000001/sig00000043 ),
.A3(\blk00000001/sig00000043 ),
.CLK(clk),
.D(\blk00000001/sig0000010e ),
.Q(\blk00000001/sig0000003c )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000175 (
.C(clk),
.D(\blk00000001/sig0000003d ),
.Q(p[4])
);
SRL16 #(
.INIT ( 16'h0000 ))
\blk00000001/blk00000174 (
.A0(\blk00000001/sig00000044 ),
.A1(\blk00000001/sig00000043 ),
.A2(\blk00000001/sig00000043 ),
.A3(\blk00000001/sig00000043 ),
.CLK(clk),
.D(\blk00000001/sig0000010f ),
.Q(\blk00000001/sig0000003d )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000173 (
.C(clk),
.D(\blk00000001/sig0000003e ),
.Q(p[5])
);
SRL16 #(
.INIT ( 16'h0000 ))
\blk00000001/blk00000172 (
.A0(\blk00000001/sig00000044 ),
.A1(\blk00000001/sig00000043 ),
.A2(\blk00000001/sig00000043 ),
.A3(\blk00000001/sig00000043 ),
.CLK(clk),
.D(\blk00000001/sig00000110 ),
.Q(\blk00000001/sig0000003e )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000171 (
.C(clk),
.D(\blk00000001/sig0000003f ),
.Q(p[6])
);
SRL16 #(
.INIT ( 16'h0000 ))
\blk00000001/blk00000170 (
.A0(\blk00000001/sig00000044 ),
.A1(\blk00000001/sig00000043 ),
.A2(\blk00000001/sig00000043 ),
.A3(\blk00000001/sig00000043 ),
.CLK(clk),
.D(\blk00000001/sig00000111 ),
.Q(\blk00000001/sig0000003f )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk0000016f (
.C(clk),
.D(\blk00000001/sig00000040 ),
.Q(p[7])
);
SRL16 #(
.INIT ( 16'h0000 ))
\blk00000001/blk0000016e (
.A0(\blk00000001/sig00000044 ),
.A1(\blk00000001/sig00000043 ),
.A2(\blk00000001/sig00000043 ),
.A3(\blk00000001/sig00000043 ),
.CLK(clk),
.D(\blk00000001/sig00000112 ),
.Q(\blk00000001/sig00000040 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk0000016d (
.C(clk),
.D(\blk00000001/sig00000041 ),
.Q(p[8])
);
SRL16 #(
.INIT ( 16'h0000 ))
\blk00000001/blk0000016c (
.A0(\blk00000001/sig00000044 ),
.A1(\blk00000001/sig00000043 ),
.A2(\blk00000001/sig00000043 ),
.A3(\blk00000001/sig00000043 ),
.CLK(clk),
.D(\blk00000001/sig00000113 ),
.Q(\blk00000001/sig00000041 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk0000016b (
.C(clk),
.D(\blk00000001/sig00000042 ),
.Q(p[9])
);
SRL16 #(
.INIT ( 16'h0000 ))
\blk00000001/blk0000016a (
.A0(\blk00000001/sig00000044 ),
.A1(\blk00000001/sig00000043 ),
.A2(\blk00000001/sig00000043 ),
.A3(\blk00000001/sig00000043 ),
.CLK(clk),
.D(\blk00000001/sig00000114 ),
.Q(\blk00000001/sig00000042 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000169 (
.C(clk),
.D(\blk00000001/sig00000034 ),
.Q(p[10])
);
SRL16 #(
.INIT ( 16'h0000 ))
\blk00000001/blk00000168 (
.A0(\blk00000001/sig00000044 ),
.A1(\blk00000001/sig00000043 ),
.A2(\blk00000001/sig00000043 ),
.A3(\blk00000001/sig00000043 ),
.CLK(clk),
.D(\blk00000001/sig000000f3 ),
.Q(\blk00000001/sig00000034 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000167 (
.C(clk),
.D(\blk00000001/sig00000035 ),
.Q(p[11])
);
SRL16 #(
.INIT ( 16'h0000 ))
\blk00000001/blk00000166 (
.A0(\blk00000001/sig00000044 ),
.A1(\blk00000001/sig00000043 ),
.A2(\blk00000001/sig00000043 ),
.A3(\blk00000001/sig00000043 ),
.CLK(clk),
.D(\blk00000001/sig000000f4 ),
.Q(\blk00000001/sig00000035 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000165 (
.C(clk),
.D(\blk00000001/sig00000036 ),
.Q(p[12])
);
SRL16 #(
.INIT ( 16'h0000 ))
\blk00000001/blk00000164 (
.A0(\blk00000001/sig00000044 ),
.A1(\blk00000001/sig00000043 ),
.A2(\blk00000001/sig00000043 ),
.A3(\blk00000001/sig00000043 ),
.CLK(clk),
.D(\blk00000001/sig000000f5 ),
.Q(\blk00000001/sig00000036 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000163 (
.C(clk),
.D(\blk00000001/sig00000037 ),
.Q(p[13])
);
SRL16 #(
.INIT ( 16'h0000 ))
\blk00000001/blk00000162 (
.A0(\blk00000001/sig00000044 ),
.A1(\blk00000001/sig00000043 ),
.A2(\blk00000001/sig00000043 ),
.A3(\blk00000001/sig00000043 ),
.CLK(clk),
.D(\blk00000001/sig000000f6 ),
.Q(\blk00000001/sig00000037 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000161 (
.C(clk),
.D(\blk00000001/sig00000039 ),
.Q(p[15])
);
SRL16 #(
.INIT ( 16'h0000 ))
\blk00000001/blk00000160 (
.A0(\blk00000001/sig00000044 ),
.A1(\blk00000001/sig00000043 ),
.A2(\blk00000001/sig00000043 ),
.A3(\blk00000001/sig00000043 ),
.CLK(clk),
.D(\blk00000001/sig000000f8 ),
.Q(\blk00000001/sig00000039 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk0000015f (
.C(clk),
.D(\blk00000001/sig0000003a ),
.Q(p[16])
);
SRL16 #(
.INIT ( 16'h0000 ))
\blk00000001/blk0000015e (
.A0(\blk00000001/sig00000044 ),
.A1(\blk00000001/sig00000043 ),
.A2(\blk00000001/sig00000043 ),
.A3(\blk00000001/sig00000043 ),
.CLK(clk),
.D(\blk00000001/sig000000f9 ),
.Q(\blk00000001/sig0000003a )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk0000015d (
.C(clk),
.D(\blk00000001/sig00000038 ),
.Q(p[14])
);
SRL16 #(
.INIT ( 16'h0000 ))
\blk00000001/blk0000015c (
.A0(\blk00000001/sig00000044 ),
.A1(\blk00000001/sig00000043 ),
.A2(\blk00000001/sig00000043 ),
.A3(\blk00000001/sig00000043 ),
.CLK(clk),
.D(\blk00000001/sig000000f7 ),
.Q(\blk00000001/sig00000038 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk0000015b (
.C(clk),
.D(\blk00000001/sig000000fa ),
.Q(\blk00000001/sig00000153 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk0000015a (
.C(clk),
.D(\blk00000001/sig000000fb ),
.Q(\blk00000001/sig00000154 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000159 (
.C(clk),
.D(\blk00000001/sig000000fc ),
.Q(\blk00000001/sig00000155 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000158 (
.C(clk),
.D(\blk00000001/sig000000fe ),
.Q(\blk00000001/sig00000156 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000157 (
.C(clk),
.D(\blk00000001/sig000000ff ),
.Q(\blk00000001/sig00000157 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000156 (
.C(clk),
.D(\blk00000001/sig00000100 ),
.Q(\blk00000001/sig00000158 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000155 (
.C(clk),
.D(\blk00000001/sig00000101 ),
.Q(\blk00000001/sig00000159 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000154 (
.C(clk),
.D(\blk00000001/sig00000102 ),
.Q(\blk00000001/sig0000015a )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000153 (
.C(clk),
.D(\blk00000001/sig00000103 ),
.Q(\blk00000001/sig0000015b )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000152 (
.C(clk),
.D(\blk00000001/sig00000104 ),
.Q(\blk00000001/sig0000015c )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000151 (
.C(clk),
.D(\blk00000001/sig00000105 ),
.Q(\blk00000001/sig0000015d )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000150 (
.C(clk),
.D(\blk00000001/sig00000106 ),
.Q(\blk00000001/sig0000015e )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk0000014f (
.C(clk),
.D(\blk00000001/sig00000107 ),
.Q(\blk00000001/sig0000015f )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk0000014e (
.C(clk),
.D(\blk00000001/sig00000109 ),
.Q(\blk00000001/sig00000160 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk0000014d (
.C(clk),
.D(\blk00000001/sig0000010a ),
.Q(\blk00000001/sig00000161 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk0000014c (
.C(clk),
.D(\blk00000001/sig0000010b ),
.Q(\blk00000001/sig00000162 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk0000014b (
.C(clk),
.D(\blk00000001/sig0000010c ),
.Q(\blk00000001/sig00000163 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk0000014a (
.C(clk),
.D(\blk00000001/sig0000010d ),
.Q(\blk00000001/sig00000164 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000149 (
.C(clk),
.D(\blk00000001/sig00000115 ),
.Q(\blk00000001/sig00000165 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000148 (
.C(clk),
.D(\blk00000001/sig00000120 ),
.Q(\blk00000001/sig00000166 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000147 (
.C(clk),
.D(\blk00000001/sig00000125 ),
.Q(\blk00000001/sig00000171 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000146 (
.C(clk),
.D(\blk00000001/sig00000126 ),
.Q(\blk00000001/sig00000176 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000145 (
.C(clk),
.D(\blk00000001/sig00000127 ),
.Q(\blk00000001/sig00000177 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000144 (
.C(clk),
.D(\blk00000001/sig00000128 ),
.Q(\blk00000001/sig00000178 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000143 (
.C(clk),
.D(\blk00000001/sig00000129 ),
.Q(\blk00000001/sig00000179 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000142 (
.C(clk),
.D(\blk00000001/sig0000012a ),
.Q(\blk00000001/sig0000017a )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000141 (
.C(clk),
.D(\blk00000001/sig0000012b ),
.Q(\blk00000001/sig0000017b )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000140 (
.C(clk),
.D(\blk00000001/sig0000012c ),
.Q(\blk00000001/sig0000017c )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk0000013f (
.C(clk),
.D(\blk00000001/sig00000116 ),
.Q(\blk00000001/sig00000167 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk0000013e (
.C(clk),
.D(\blk00000001/sig00000117 ),
.Q(\blk00000001/sig00000168 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk0000013d (
.C(clk),
.D(\blk00000001/sig00000118 ),
.Q(\blk00000001/sig00000169 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk0000013c (
.C(clk),
.D(\blk00000001/sig00000119 ),
.Q(\blk00000001/sig0000016a )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk0000013b (
.C(clk),
.D(\blk00000001/sig0000011a ),
.Q(\blk00000001/sig0000016b )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk0000013a (
.C(clk),
.D(\blk00000001/sig0000011b ),
.Q(\blk00000001/sig0000016c )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000139 (
.C(clk),
.D(\blk00000001/sig0000011c ),
.Q(\blk00000001/sig0000016d )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000138 (
.C(clk),
.D(\blk00000001/sig0000011d ),
.Q(\blk00000001/sig0000016e )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000137 (
.C(clk),
.D(\blk00000001/sig0000011e ),
.Q(\blk00000001/sig0000016f )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000136 (
.C(clk),
.D(\blk00000001/sig0000011f ),
.Q(\blk00000001/sig00000170 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000135 (
.C(clk),
.D(\blk00000001/sig00000121 ),
.Q(\blk00000001/sig00000172 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000134 (
.C(clk),
.D(\blk00000001/sig00000122 ),
.Q(\blk00000001/sig00000173 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000133 (
.C(clk),
.D(\blk00000001/sig00000123 ),
.Q(\blk00000001/sig00000174 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000132 (
.C(clk),
.D(\blk00000001/sig00000124 ),
.Q(\blk00000001/sig00000175 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000131 (
.C(clk),
.D(\blk00000001/sig00000135 ),
.Q(\blk00000001/sig0000017d )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000130 (
.C(clk),
.D(\blk00000001/sig00000136 ),
.Q(\blk00000001/sig0000017e )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk0000012f (
.C(clk),
.D(\blk00000001/sig00000137 ),
.Q(\blk00000001/sig0000017f )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk0000012e (
.C(clk),
.D(\blk00000001/sig00000139 ),
.Q(\blk00000001/sig00000180 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk0000012d (
.C(clk),
.D(\blk00000001/sig0000013a ),
.Q(\blk00000001/sig00000181 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk0000012c (
.C(clk),
.D(\blk00000001/sig0000013b ),
.Q(\blk00000001/sig00000182 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk0000012b (
.C(clk),
.D(\blk00000001/sig0000013c ),
.Q(\blk00000001/sig00000183 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk0000012a (
.C(clk),
.D(\blk00000001/sig00000145 ),
.Q(\blk00000001/sig00000184 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000129 (
.C(clk),
.D(\blk00000001/sig0000014a ),
.Q(\blk00000001/sig00000185 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000128 (
.C(clk),
.D(\blk00000001/sig0000014b ),
.Q(\blk00000001/sig0000018a )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000127 (
.C(clk),
.D(\blk00000001/sig0000014c ),
.Q(\blk00000001/sig0000018b )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000126 (
.C(clk),
.D(\blk00000001/sig0000014d ),
.Q(\blk00000001/sig0000018c )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000125 (
.C(clk),
.D(\blk00000001/sig0000014e ),
.Q(\blk00000001/sig0000018d )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000124 (
.C(clk),
.D(\blk00000001/sig0000014f ),
.Q(\blk00000001/sig0000018e )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000123 (
.C(clk),
.D(\blk00000001/sig00000150 ),
.Q(\blk00000001/sig0000018f )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000122 (
.C(clk),
.D(\blk00000001/sig00000151 ),
.Q(\blk00000001/sig00000190 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000121 (
.C(clk),
.D(\blk00000001/sig00000152 ),
.Q(\blk00000001/sig00000191 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000120 (
.C(clk),
.D(\blk00000001/sig00000146 ),
.Q(\blk00000001/sig00000186 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk0000011f (
.C(clk),
.D(\blk00000001/sig00000147 ),
.Q(\blk00000001/sig00000187 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk0000011e (
.C(clk),
.D(\blk00000001/sig00000148 ),
.Q(\blk00000001/sig00000188 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk0000011d (
.C(clk),
.D(\blk00000001/sig00000149 ),
.Q(\blk00000001/sig00000189 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk0000011c (
.C(clk),
.D(\blk00000001/sig000001c2 ),
.Q(\blk00000001/sig000001d0 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk0000011b (
.C(clk),
.D(\blk00000001/sig000001c7 ),
.Q(\blk00000001/sig000001d1 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk0000011a (
.C(clk),
.D(\blk00000001/sig000001c8 ),
.Q(\blk00000001/sig000001d6 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000119 (
.C(clk),
.D(\blk00000001/sig000001c9 ),
.Q(\blk00000001/sig000001d7 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000118 (
.C(clk),
.D(\blk00000001/sig000001ca ),
.Q(\blk00000001/sig000001d8 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000117 (
.C(clk),
.D(\blk00000001/sig000001cb ),
.Q(\blk00000001/sig000001d9 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000116 (
.C(clk),
.D(\blk00000001/sig000001cc ),
.Q(\blk00000001/sig000001da )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000115 (
.C(clk),
.D(\blk00000001/sig000001cd ),
.Q(\blk00000001/sig000001db )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000114 (
.C(clk),
.D(\blk00000001/sig000001ce ),
.Q(\blk00000001/sig000001dc )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000113 (
.C(clk),
.D(\blk00000001/sig000001cf ),
.Q(\blk00000001/sig000001dd )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000112 (
.C(clk),
.D(\blk00000001/sig000001c3 ),
.Q(\blk00000001/sig000001d2 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000111 (
.C(clk),
.D(\blk00000001/sig000001c4 ),
.Q(\blk00000001/sig000001d3 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000110 (
.C(clk),
.D(\blk00000001/sig000001c5 ),
.Q(\blk00000001/sig000001d4 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk0000010f (
.C(clk),
.D(\blk00000001/sig000001c6 ),
.Q(\blk00000001/sig000001d5 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk0000010e (
.C(clk),
.D(\blk00000001/sig00000192 ),
.Q(\blk00000001/sig000001aa )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk0000010d (
.C(clk),
.D(\blk00000001/sig0000019d ),
.Q(\blk00000001/sig000001ab )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk0000010c (
.C(clk),
.D(\blk00000001/sig000001a2 ),
.Q(\blk00000001/sig000001b6 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk0000010b (
.C(clk),
.D(\blk00000001/sig000001a3 ),
.Q(\blk00000001/sig000001bb )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk0000010a (
.C(clk),
.D(\blk00000001/sig000001a4 ),
.Q(\blk00000001/sig000001bc )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000109 (
.C(clk),
.D(\blk00000001/sig000001a5 ),
.Q(\blk00000001/sig000001bd )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000108 (
.C(clk),
.D(\blk00000001/sig000001a6 ),
.Q(\blk00000001/sig000001be )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000107 (
.C(clk),
.D(\blk00000001/sig000001a7 ),
.Q(\blk00000001/sig000001bf )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000106 (
.C(clk),
.D(\blk00000001/sig000001a8 ),
.Q(\blk00000001/sig000001c0 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000105 (
.C(clk),
.D(\blk00000001/sig000001a9 ),
.Q(\blk00000001/sig000001c1 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000104 (
.C(clk),
.D(\blk00000001/sig00000193 ),
.Q(\blk00000001/sig000001ac )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000103 (
.C(clk),
.D(\blk00000001/sig00000194 ),
.Q(\blk00000001/sig000001ad )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000102 (
.C(clk),
.D(\blk00000001/sig00000195 ),
.Q(\blk00000001/sig000001ae )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000101 (
.C(clk),
.D(\blk00000001/sig00000196 ),
.Q(\blk00000001/sig000001af )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000100 (
.C(clk),
.D(\blk00000001/sig00000197 ),
.Q(\blk00000001/sig000001b0 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk000000ff (
.C(clk),
.D(\blk00000001/sig00000198 ),
.Q(\blk00000001/sig000001b1 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk000000fe (
.C(clk),
.D(\blk00000001/sig00000199 ),
.Q(\blk00000001/sig000001b2 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk000000fd (
.C(clk),
.D(\blk00000001/sig0000019a ),
.Q(\blk00000001/sig000001b3 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk000000fc (
.C(clk),
.D(\blk00000001/sig0000019b ),
.Q(\blk00000001/sig000001b4 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk000000fb (
.C(clk),
.D(\blk00000001/sig0000019c ),
.Q(\blk00000001/sig000001b5 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk000000fa (
.C(clk),
.D(\blk00000001/sig0000019e ),
.Q(\blk00000001/sig000001b7 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk000000f9 (
.C(clk),
.D(\blk00000001/sig0000019f ),
.Q(\blk00000001/sig000001b8 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk000000f8 (
.C(clk),
.D(\blk00000001/sig000001a0 ),
.Q(\blk00000001/sig000001b9 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk000000f7 (
.C(clk),
.D(\blk00000001/sig000001a1 ),
.Q(\blk00000001/sig000001ba )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk000000f6 (
.C(clk),
.D(\blk00000001/sig000001de ),
.Q(p[17])
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk000000f5 (
.C(clk),
.D(\blk00000001/sig000001e9 ),
.Q(p[18])
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk000000f4 (
.C(clk),
.D(\blk00000001/sig000001f4 ),
.Q(p[19])
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk000000f3 (
.C(clk),
.D(\blk00000001/sig000001f5 ),
.Q(p[20])
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk000000f2 (
.C(clk),
.D(\blk00000001/sig000001f6 ),
.Q(p[21])
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk000000f1 (
.C(clk),
.D(\blk00000001/sig000001f8 ),
.Q(p[22])
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk000000f0 (
.C(clk),
.D(\blk00000001/sig000001f9 ),
.Q(p[23])
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk000000ef (
.C(clk),
.D(\blk00000001/sig000001fa ),
.Q(p[24])
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk000000ee (
.C(clk),
.D(\blk00000001/sig000001fb ),
.Q(p[25])
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk000000ed (
.C(clk),
.D(\blk00000001/sig000001fc ),
.Q(p[26])
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk000000ec (
.C(clk),
.D(\blk00000001/sig000001df ),
.Q(p[27])
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk000000eb (
.C(clk),
.D(\blk00000001/sig000001e0 ),
.Q(p[28])
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk000000ea (
.C(clk),
.D(\blk00000001/sig000001e1 ),
.Q(p[29])
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk000000e9 (
.C(clk),
.D(\blk00000001/sig000001e2 ),
.Q(p[30])
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk000000e8 (
.C(clk),
.D(\blk00000001/sig000001e3 ),
.Q(p[31])
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk000000e7 (
.C(clk),
.D(\blk00000001/sig000001e4 ),
.Q(p[32])
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk000000e6 (
.C(clk),
.D(\blk00000001/sig000001e5 ),
.Q(p[33])
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk000000e5 (
.C(clk),
.D(\blk00000001/sig000001e6 ),
.Q(p[34])
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk000000e4 (
.C(clk),
.D(\blk00000001/sig000001e7 ),
.Q(p[35])
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk000000e3 (
.C(clk),
.D(\blk00000001/sig000001e8 ),
.Q(p[36])
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk000000e2 (
.C(clk),
.D(\blk00000001/sig000001ea ),
.Q(p[37])
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk000000e1 (
.C(clk),
.D(\blk00000001/sig000001eb ),
.Q(p[38])
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk000000e0 (
.C(clk),
.D(\blk00000001/sig000001ec ),
.Q(p[39])
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk000000df (
.C(clk),
.D(\blk00000001/sig000001ed ),
.Q(p[40])
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk000000de (
.C(clk),
.D(\blk00000001/sig000001ee ),
.Q(p[41])
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk000000dd (
.C(clk),
.D(\blk00000001/sig000001ef ),
.Q(p[42])
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk000000dc (
.C(clk),
.D(\blk00000001/sig000001f0 ),
.Q(p[43])
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk000000db (
.C(clk),
.D(\blk00000001/sig000001f1 ),
.Q(p[44])
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk000000da (
.C(clk),
.D(\blk00000001/sig000001f2 ),
.Q(p[45])
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk000000d9 (
.C(clk),
.D(\blk00000001/sig000001f3 ),
.Q(p[46])
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk000000d8 (
.C(clk),
.D(\blk00000001/sig000001f7 ),
.Q(p[47])
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk000000d7 (
.I0(\blk00000001/sig0000017d ),
.I1(\blk00000001/sig00000184 ),
.O(\blk00000001/sig00000081 )
);
MUXCY \blk00000001/blk000000d6 (
.CI(\blk00000001/sig00000043 ),
.DI(\blk00000001/sig0000017d ),
.S(\blk00000001/sig00000081 ),
.O(\blk00000001/sig00000074 )
);
XORCY \blk00000001/blk000000d5 (
.CI(\blk00000001/sig00000043 ),
.LI(\blk00000001/sig00000081 ),
.O(\blk00000001/sig000001c2 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk000000d4 (
.I0(\blk00000001/sig0000017e ),
.I1(\blk00000001/sig00000185 ),
.O(\blk00000001/sig00000086 )
);
MUXCY \blk00000001/blk000000d3 (
.CI(\blk00000001/sig00000074 ),
.DI(\blk00000001/sig0000017e ),
.S(\blk00000001/sig00000086 ),
.O(\blk00000001/sig00000078 )
);
XORCY \blk00000001/blk000000d2 (
.CI(\blk00000001/sig00000074 ),
.LI(\blk00000001/sig00000086 ),
.O(\blk00000001/sig000001c7 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk000000d1 (
.I0(\blk00000001/sig0000017f ),
.I1(\blk00000001/sig0000018a ),
.O(\blk00000001/sig00000087 )
);
MUXCY \blk00000001/blk000000d0 (
.CI(\blk00000001/sig00000078 ),
.DI(\blk00000001/sig0000017f ),
.S(\blk00000001/sig00000087 ),
.O(\blk00000001/sig00000079 )
);
XORCY \blk00000001/blk000000cf (
.CI(\blk00000001/sig00000078 ),
.LI(\blk00000001/sig00000087 ),
.O(\blk00000001/sig000001c8 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk000000ce (
.I0(\blk00000001/sig00000180 ),
.I1(\blk00000001/sig0000018b ),
.O(\blk00000001/sig00000088 )
);
MUXCY \blk00000001/blk000000cd (
.CI(\blk00000001/sig00000079 ),
.DI(\blk00000001/sig00000180 ),
.S(\blk00000001/sig00000088 ),
.O(\blk00000001/sig0000007a )
);
XORCY \blk00000001/blk000000cc (
.CI(\blk00000001/sig00000079 ),
.LI(\blk00000001/sig00000088 ),
.O(\blk00000001/sig000001c9 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk000000cb (
.I0(\blk00000001/sig00000181 ),
.I1(\blk00000001/sig0000018c ),
.O(\blk00000001/sig00000089 )
);
MUXCY \blk00000001/blk000000ca (
.CI(\blk00000001/sig0000007a ),
.DI(\blk00000001/sig00000181 ),
.S(\blk00000001/sig00000089 ),
.O(\blk00000001/sig0000007b )
);
XORCY \blk00000001/blk000000c9 (
.CI(\blk00000001/sig0000007a ),
.LI(\blk00000001/sig00000089 ),
.O(\blk00000001/sig000001ca )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk000000c8 (
.I0(\blk00000001/sig00000182 ),
.I1(\blk00000001/sig0000018d ),
.O(\blk00000001/sig0000008a )
);
MUXCY \blk00000001/blk000000c7 (
.CI(\blk00000001/sig0000007b ),
.DI(\blk00000001/sig00000182 ),
.S(\blk00000001/sig0000008a ),
.O(\blk00000001/sig0000007c )
);
XORCY \blk00000001/blk000000c6 (
.CI(\blk00000001/sig0000007b ),
.LI(\blk00000001/sig0000008a ),
.O(\blk00000001/sig000001cb )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk000000c5 (
.I0(\blk00000001/sig00000183 ),
.I1(\blk00000001/sig0000018e ),
.O(\blk00000001/sig0000008b )
);
MUXCY \blk00000001/blk000000c4 (
.CI(\blk00000001/sig0000007c ),
.DI(\blk00000001/sig00000183 ),
.S(\blk00000001/sig0000008b ),
.O(\blk00000001/sig0000007d )
);
XORCY \blk00000001/blk000000c3 (
.CI(\blk00000001/sig0000007c ),
.LI(\blk00000001/sig0000008b ),
.O(\blk00000001/sig000001cc )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk000000c2 (
.I0(\blk00000001/sig00000183 ),
.I1(\blk00000001/sig0000018f ),
.O(\blk00000001/sig0000008c )
);
MUXCY \blk00000001/blk000000c1 (
.CI(\blk00000001/sig0000007d ),
.DI(\blk00000001/sig00000183 ),
.S(\blk00000001/sig0000008c ),
.O(\blk00000001/sig0000007e )
);
XORCY \blk00000001/blk000000c0 (
.CI(\blk00000001/sig0000007d ),
.LI(\blk00000001/sig0000008c ),
.O(\blk00000001/sig000001cd )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk000000bf (
.I0(\blk00000001/sig00000183 ),
.I1(\blk00000001/sig00000190 ),
.O(\blk00000001/sig0000008d )
);
MUXCY \blk00000001/blk000000be (
.CI(\blk00000001/sig0000007e ),
.DI(\blk00000001/sig00000183 ),
.S(\blk00000001/sig0000008d ),
.O(\blk00000001/sig0000007f )
);
XORCY \blk00000001/blk000000bd (
.CI(\blk00000001/sig0000007e ),
.LI(\blk00000001/sig0000008d ),
.O(\blk00000001/sig000001ce )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk000000bc (
.I0(\blk00000001/sig00000183 ),
.I1(\blk00000001/sig00000191 ),
.O(\blk00000001/sig0000008e )
);
MUXCY \blk00000001/blk000000bb (
.CI(\blk00000001/sig0000007f ),
.DI(\blk00000001/sig00000183 ),
.S(\blk00000001/sig0000008e ),
.O(\blk00000001/sig00000080 )
);
XORCY \blk00000001/blk000000ba (
.CI(\blk00000001/sig0000007f ),
.LI(\blk00000001/sig0000008e ),
.O(\blk00000001/sig000001cf )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk000000b9 (
.I0(\blk00000001/sig00000183 ),
.I1(\blk00000001/sig00000186 ),
.O(\blk00000001/sig00000082 )
);
MUXCY \blk00000001/blk000000b8 (
.CI(\blk00000001/sig00000080 ),
.DI(\blk00000001/sig00000183 ),
.S(\blk00000001/sig00000082 ),
.O(\blk00000001/sig00000075 )
);
XORCY \blk00000001/blk000000b7 (
.CI(\blk00000001/sig00000080 ),
.LI(\blk00000001/sig00000082 ),
.O(\blk00000001/sig000001c3 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk000000b6 (
.I0(\blk00000001/sig00000183 ),
.I1(\blk00000001/sig00000187 ),
.O(\blk00000001/sig00000083 )
);
MUXCY \blk00000001/blk000000b5 (
.CI(\blk00000001/sig00000075 ),
.DI(\blk00000001/sig00000183 ),
.S(\blk00000001/sig00000083 ),
.O(\blk00000001/sig00000076 )
);
XORCY \blk00000001/blk000000b4 (
.CI(\blk00000001/sig00000075 ),
.LI(\blk00000001/sig00000083 ),
.O(\blk00000001/sig000001c4 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk000000b3 (
.I0(\blk00000001/sig00000183 ),
.I1(\blk00000001/sig00000188 ),
.O(\blk00000001/sig00000084 )
);
MUXCY \blk00000001/blk000000b2 (
.CI(\blk00000001/sig00000076 ),
.DI(\blk00000001/sig00000183 ),
.S(\blk00000001/sig00000084 ),
.O(\blk00000001/sig00000077 )
);
XORCY \blk00000001/blk000000b1 (
.CI(\blk00000001/sig00000076 ),
.LI(\blk00000001/sig00000084 ),
.O(\blk00000001/sig000001c5 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk000000b0 (
.I0(\blk00000001/sig00000183 ),
.I1(\blk00000001/sig00000189 ),
.O(\blk00000001/sig00000085 )
);
XORCY \blk00000001/blk000000af (
.CI(\blk00000001/sig00000077 ),
.LI(\blk00000001/sig00000085 ),
.O(\blk00000001/sig000001c6 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk000000ae (
.I0(\blk00000001/sig00000153 ),
.I1(\blk00000001/sig00000165 ),
.O(\blk00000001/sig0000005c )
);
MUXCY \blk00000001/blk000000ad (
.CI(\blk00000001/sig00000043 ),
.DI(\blk00000001/sig00000153 ),
.S(\blk00000001/sig0000005c ),
.O(\blk00000001/sig00000045 )
);
XORCY \blk00000001/blk000000ac (
.CI(\blk00000001/sig00000043 ),
.LI(\blk00000001/sig0000005c ),
.O(\blk00000001/sig00000192 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk000000ab (
.I0(\blk00000001/sig00000154 ),
.I1(\blk00000001/sig00000166 ),
.O(\blk00000001/sig00000067 )
);
MUXCY \blk00000001/blk000000aa (
.CI(\blk00000001/sig00000045 ),
.DI(\blk00000001/sig00000154 ),
.S(\blk00000001/sig00000067 ),
.O(\blk00000001/sig00000050 )
);
XORCY \blk00000001/blk000000a9 (
.CI(\blk00000001/sig00000045 ),
.LI(\blk00000001/sig00000067 ),
.O(\blk00000001/sig0000019d )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk000000a8 (
.I0(\blk00000001/sig00000155 ),
.I1(\blk00000001/sig00000171 ),
.O(\blk00000001/sig0000006c )
);
MUXCY \blk00000001/blk000000a7 (
.CI(\blk00000001/sig00000050 ),
.DI(\blk00000001/sig00000155 ),
.S(\blk00000001/sig0000006c ),
.O(\blk00000001/sig00000054 )
);
XORCY \blk00000001/blk000000a6 (
.CI(\blk00000001/sig00000050 ),
.LI(\blk00000001/sig0000006c ),
.O(\blk00000001/sig000001a2 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk000000a5 (
.I0(\blk00000001/sig00000156 ),
.I1(\blk00000001/sig00000176 ),
.O(\blk00000001/sig0000006d )
);
MUXCY \blk00000001/blk000000a4 (
.CI(\blk00000001/sig00000054 ),
.DI(\blk00000001/sig00000156 ),
.S(\blk00000001/sig0000006d ),
.O(\blk00000001/sig00000055 )
);
XORCY \blk00000001/blk000000a3 (
.CI(\blk00000001/sig00000054 ),
.LI(\blk00000001/sig0000006d ),
.O(\blk00000001/sig000001a3 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk000000a2 (
.I0(\blk00000001/sig00000157 ),
.I1(\blk00000001/sig00000177 ),
.O(\blk00000001/sig0000006e )
);
MUXCY \blk00000001/blk000000a1 (
.CI(\blk00000001/sig00000055 ),
.DI(\blk00000001/sig00000157 ),
.S(\blk00000001/sig0000006e ),
.O(\blk00000001/sig00000056 )
);
XORCY \blk00000001/blk000000a0 (
.CI(\blk00000001/sig00000055 ),
.LI(\blk00000001/sig0000006e ),
.O(\blk00000001/sig000001a4 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk0000009f (
.I0(\blk00000001/sig00000158 ),
.I1(\blk00000001/sig00000178 ),
.O(\blk00000001/sig0000006f )
);
MUXCY \blk00000001/blk0000009e (
.CI(\blk00000001/sig00000056 ),
.DI(\blk00000001/sig00000158 ),
.S(\blk00000001/sig0000006f ),
.O(\blk00000001/sig00000057 )
);
XORCY \blk00000001/blk0000009d (
.CI(\blk00000001/sig00000056 ),
.LI(\blk00000001/sig0000006f ),
.O(\blk00000001/sig000001a5 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk0000009c (
.I0(\blk00000001/sig00000159 ),
.I1(\blk00000001/sig00000179 ),
.O(\blk00000001/sig00000070 )
);
MUXCY \blk00000001/blk0000009b (
.CI(\blk00000001/sig00000057 ),
.DI(\blk00000001/sig00000159 ),
.S(\blk00000001/sig00000070 ),
.O(\blk00000001/sig00000058 )
);
XORCY \blk00000001/blk0000009a (
.CI(\blk00000001/sig00000057 ),
.LI(\blk00000001/sig00000070 ),
.O(\blk00000001/sig000001a6 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000099 (
.I0(\blk00000001/sig0000015a ),
.I1(\blk00000001/sig0000017a ),
.O(\blk00000001/sig00000071 )
);
MUXCY \blk00000001/blk00000098 (
.CI(\blk00000001/sig00000058 ),
.DI(\blk00000001/sig0000015a ),
.S(\blk00000001/sig00000071 ),
.O(\blk00000001/sig00000059 )
);
XORCY \blk00000001/blk00000097 (
.CI(\blk00000001/sig00000058 ),
.LI(\blk00000001/sig00000071 ),
.O(\blk00000001/sig000001a7 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000096 (
.I0(\blk00000001/sig0000015b ),
.I1(\blk00000001/sig0000017b ),
.O(\blk00000001/sig00000072 )
);
MUXCY \blk00000001/blk00000095 (
.CI(\blk00000001/sig00000059 ),
.DI(\blk00000001/sig0000015b ),
.S(\blk00000001/sig00000072 ),
.O(\blk00000001/sig0000005a )
);
XORCY \blk00000001/blk00000094 (
.CI(\blk00000001/sig00000059 ),
.LI(\blk00000001/sig00000072 ),
.O(\blk00000001/sig000001a8 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000093 (
.I0(\blk00000001/sig0000015c ),
.I1(\blk00000001/sig0000017c ),
.O(\blk00000001/sig00000073 )
);
MUXCY \blk00000001/blk00000092 (
.CI(\blk00000001/sig0000005a ),
.DI(\blk00000001/sig0000015c ),
.S(\blk00000001/sig00000073 ),
.O(\blk00000001/sig0000005b )
);
XORCY \blk00000001/blk00000091 (
.CI(\blk00000001/sig0000005a ),
.LI(\blk00000001/sig00000073 ),
.O(\blk00000001/sig000001a9 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000090 (
.I0(\blk00000001/sig0000015d ),
.I1(\blk00000001/sig00000167 ),
.O(\blk00000001/sig0000005d )
);
MUXCY \blk00000001/blk0000008f (
.CI(\blk00000001/sig0000005b ),
.DI(\blk00000001/sig0000015d ),
.S(\blk00000001/sig0000005d ),
.O(\blk00000001/sig00000046 )
);
XORCY \blk00000001/blk0000008e (
.CI(\blk00000001/sig0000005b ),
.LI(\blk00000001/sig0000005d ),
.O(\blk00000001/sig00000193 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk0000008d (
.I0(\blk00000001/sig0000015e ),
.I1(\blk00000001/sig00000168 ),
.O(\blk00000001/sig0000005e )
);
MUXCY \blk00000001/blk0000008c (
.CI(\blk00000001/sig00000046 ),
.DI(\blk00000001/sig0000015e ),
.S(\blk00000001/sig0000005e ),
.O(\blk00000001/sig00000047 )
);
XORCY \blk00000001/blk0000008b (
.CI(\blk00000001/sig00000046 ),
.LI(\blk00000001/sig0000005e ),
.O(\blk00000001/sig00000194 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk0000008a (
.I0(\blk00000001/sig0000015f ),
.I1(\blk00000001/sig00000169 ),
.O(\blk00000001/sig0000005f )
);
MUXCY \blk00000001/blk00000089 (
.CI(\blk00000001/sig00000047 ),
.DI(\blk00000001/sig0000015f ),
.S(\blk00000001/sig0000005f ),
.O(\blk00000001/sig00000048 )
);
XORCY \blk00000001/blk00000088 (
.CI(\blk00000001/sig00000047 ),
.LI(\blk00000001/sig0000005f ),
.O(\blk00000001/sig00000195 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000087 (
.I0(\blk00000001/sig00000160 ),
.I1(\blk00000001/sig0000016a ),
.O(\blk00000001/sig00000060 )
);
MUXCY \blk00000001/blk00000086 (
.CI(\blk00000001/sig00000048 ),
.DI(\blk00000001/sig00000160 ),
.S(\blk00000001/sig00000060 ),
.O(\blk00000001/sig00000049 )
);
XORCY \blk00000001/blk00000085 (
.CI(\blk00000001/sig00000048 ),
.LI(\blk00000001/sig00000060 ),
.O(\blk00000001/sig00000196 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000084 (
.I0(\blk00000001/sig00000161 ),
.I1(\blk00000001/sig0000016b ),
.O(\blk00000001/sig00000061 )
);
MUXCY \blk00000001/blk00000083 (
.CI(\blk00000001/sig00000049 ),
.DI(\blk00000001/sig00000161 ),
.S(\blk00000001/sig00000061 ),
.O(\blk00000001/sig0000004a )
);
XORCY \blk00000001/blk00000082 (
.CI(\blk00000001/sig00000049 ),
.LI(\blk00000001/sig00000061 ),
.O(\blk00000001/sig00000197 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000081 (
.I0(\blk00000001/sig00000162 ),
.I1(\blk00000001/sig0000016c ),
.O(\blk00000001/sig00000062 )
);
MUXCY \blk00000001/blk00000080 (
.CI(\blk00000001/sig0000004a ),
.DI(\blk00000001/sig00000162 ),
.S(\blk00000001/sig00000062 ),
.O(\blk00000001/sig0000004b )
);
XORCY \blk00000001/blk0000007f (
.CI(\blk00000001/sig0000004a ),
.LI(\blk00000001/sig00000062 ),
.O(\blk00000001/sig00000198 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk0000007e (
.I0(\blk00000001/sig00000163 ),
.I1(\blk00000001/sig0000016d ),
.O(\blk00000001/sig00000063 )
);
MUXCY \blk00000001/blk0000007d (
.CI(\blk00000001/sig0000004b ),
.DI(\blk00000001/sig00000163 ),
.S(\blk00000001/sig00000063 ),
.O(\blk00000001/sig0000004c )
);
XORCY \blk00000001/blk0000007c (
.CI(\blk00000001/sig0000004b ),
.LI(\blk00000001/sig00000063 ),
.O(\blk00000001/sig00000199 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk0000007b (
.I0(\blk00000001/sig00000164 ),
.I1(\blk00000001/sig0000016e ),
.O(\blk00000001/sig00000064 )
);
MUXCY \blk00000001/blk0000007a (
.CI(\blk00000001/sig0000004c ),
.DI(\blk00000001/sig00000164 ),
.S(\blk00000001/sig00000064 ),
.O(\blk00000001/sig0000004d )
);
XORCY \blk00000001/blk00000079 (
.CI(\blk00000001/sig0000004c ),
.LI(\blk00000001/sig00000064 ),
.O(\blk00000001/sig0000019a )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000078 (
.I0(\blk00000001/sig00000164 ),
.I1(\blk00000001/sig0000016f ),
.O(\blk00000001/sig00000065 )
);
MUXCY \blk00000001/blk00000077 (
.CI(\blk00000001/sig0000004d ),
.DI(\blk00000001/sig00000164 ),
.S(\blk00000001/sig00000065 ),
.O(\blk00000001/sig0000004e )
);
XORCY \blk00000001/blk00000076 (
.CI(\blk00000001/sig0000004d ),
.LI(\blk00000001/sig00000065 ),
.O(\blk00000001/sig0000019b )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000075 (
.I0(\blk00000001/sig00000164 ),
.I1(\blk00000001/sig00000170 ),
.O(\blk00000001/sig00000066 )
);
MUXCY \blk00000001/blk00000074 (
.CI(\blk00000001/sig0000004e ),
.DI(\blk00000001/sig00000164 ),
.S(\blk00000001/sig00000066 ),
.O(\blk00000001/sig0000004f )
);
XORCY \blk00000001/blk00000073 (
.CI(\blk00000001/sig0000004e ),
.LI(\blk00000001/sig00000066 ),
.O(\blk00000001/sig0000019c )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000072 (
.I0(\blk00000001/sig00000164 ),
.I1(\blk00000001/sig00000172 ),
.O(\blk00000001/sig00000068 )
);
MUXCY \blk00000001/blk00000071 (
.CI(\blk00000001/sig0000004f ),
.DI(\blk00000001/sig00000164 ),
.S(\blk00000001/sig00000068 ),
.O(\blk00000001/sig00000051 )
);
XORCY \blk00000001/blk00000070 (
.CI(\blk00000001/sig0000004f ),
.LI(\blk00000001/sig00000068 ),
.O(\blk00000001/sig0000019e )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk0000006f (
.I0(\blk00000001/sig00000164 ),
.I1(\blk00000001/sig00000173 ),
.O(\blk00000001/sig00000069 )
);
MUXCY \blk00000001/blk0000006e (
.CI(\blk00000001/sig00000051 ),
.DI(\blk00000001/sig00000164 ),
.S(\blk00000001/sig00000069 ),
.O(\blk00000001/sig00000052 )
);
XORCY \blk00000001/blk0000006d (
.CI(\blk00000001/sig00000051 ),
.LI(\blk00000001/sig00000069 ),
.O(\blk00000001/sig0000019f )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk0000006c (
.I0(\blk00000001/sig00000164 ),
.I1(\blk00000001/sig00000174 ),
.O(\blk00000001/sig0000006a )
);
MUXCY \blk00000001/blk0000006b (
.CI(\blk00000001/sig00000052 ),
.DI(\blk00000001/sig00000164 ),
.S(\blk00000001/sig0000006a ),
.O(\blk00000001/sig00000053 )
);
XORCY \blk00000001/blk0000006a (
.CI(\blk00000001/sig00000052 ),
.LI(\blk00000001/sig0000006a ),
.O(\blk00000001/sig000001a0 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000069 (
.I0(\blk00000001/sig00000164 ),
.I1(\blk00000001/sig00000175 ),
.O(\blk00000001/sig0000006b )
);
XORCY \blk00000001/blk00000068 (
.CI(\blk00000001/sig00000053 ),
.LI(\blk00000001/sig0000006b ),
.O(\blk00000001/sig000001a1 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000067 (
.I0(\blk00000001/sig000001aa ),
.I1(\blk00000001/sig000000e1 ),
.O(\blk00000001/sig000000af )
);
MUXCY \blk00000001/blk00000066 (
.CI(\blk00000001/sig00000043 ),
.DI(\blk00000001/sig000001aa ),
.S(\blk00000001/sig000000af ),
.O(\blk00000001/sig0000008f )
);
XORCY \blk00000001/blk00000065 (
.CI(\blk00000001/sig00000043 ),
.LI(\blk00000001/sig000000af ),
.O(\blk00000001/sig000001de )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000064 (
.I0(\blk00000001/sig000001ab ),
.I1(\blk00000001/sig000000e2 ),
.O(\blk00000001/sig000000ba )
);
MUXCY \blk00000001/blk00000063 (
.CI(\blk00000001/sig0000008f ),
.DI(\blk00000001/sig000001ab ),
.S(\blk00000001/sig000000ba ),
.O(\blk00000001/sig0000009a )
);
XORCY \blk00000001/blk00000062 (
.CI(\blk00000001/sig0000008f ),
.LI(\blk00000001/sig000000ba ),
.O(\blk00000001/sig000001e9 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000061 (
.I0(\blk00000001/sig000001b6 ),
.I1(\blk00000001/sig000000ea ),
.O(\blk00000001/sig000000c5 )
);
MUXCY \blk00000001/blk00000060 (
.CI(\blk00000001/sig0000009a ),
.DI(\blk00000001/sig000001b6 ),
.S(\blk00000001/sig000000c5 ),
.O(\blk00000001/sig000000a5 )
);
XORCY \blk00000001/blk0000005f (
.CI(\blk00000001/sig0000009a ),
.LI(\blk00000001/sig000000c5 ),
.O(\blk00000001/sig000001f4 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk0000005e (
.I0(\blk00000001/sig000001bb ),
.I1(\blk00000001/sig000000eb ),
.O(\blk00000001/sig000000c9 )
);
MUXCY \blk00000001/blk0000005d (
.CI(\blk00000001/sig000000a5 ),
.DI(\blk00000001/sig000001bb ),
.S(\blk00000001/sig000000c9 ),
.O(\blk00000001/sig000000a8 )
);
XORCY \blk00000001/blk0000005c (
.CI(\blk00000001/sig000000a5 ),
.LI(\blk00000001/sig000000c9 ),
.O(\blk00000001/sig000001f5 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk0000005b (
.I0(\blk00000001/sig000001bc ),
.I1(\blk00000001/sig000000ec ),
.O(\blk00000001/sig000000ca )
);
MUXCY \blk00000001/blk0000005a (
.CI(\blk00000001/sig000000a8 ),
.DI(\blk00000001/sig000001bc ),
.S(\blk00000001/sig000000ca ),
.O(\blk00000001/sig000000a9 )
);
XORCY \blk00000001/blk00000059 (
.CI(\blk00000001/sig000000a8 ),
.LI(\blk00000001/sig000000ca ),
.O(\blk00000001/sig000001f6 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000058 (
.I0(\blk00000001/sig000001bd ),
.I1(\blk00000001/sig000000ed ),
.O(\blk00000001/sig000000cb )
);
MUXCY \blk00000001/blk00000057 (
.CI(\blk00000001/sig000000a9 ),
.DI(\blk00000001/sig000001bd ),
.S(\blk00000001/sig000000cb ),
.O(\blk00000001/sig000000aa )
);
XORCY \blk00000001/blk00000056 (
.CI(\blk00000001/sig000000a9 ),
.LI(\blk00000001/sig000000cb ),
.O(\blk00000001/sig000001f8 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000055 (
.I0(\blk00000001/sig000001be ),
.I1(\blk00000001/sig000000ee ),
.O(\blk00000001/sig000000cc )
);
MUXCY \blk00000001/blk00000054 (
.CI(\blk00000001/sig000000aa ),
.DI(\blk00000001/sig000001be ),
.S(\blk00000001/sig000000cc ),
.O(\blk00000001/sig000000ab )
);
XORCY \blk00000001/blk00000053 (
.CI(\blk00000001/sig000000aa ),
.LI(\blk00000001/sig000000cc ),
.O(\blk00000001/sig000001f9 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000052 (
.I0(\blk00000001/sig000001bf ),
.I1(\blk00000001/sig000000ef ),
.O(\blk00000001/sig000000cd )
);
MUXCY \blk00000001/blk00000051 (
.CI(\blk00000001/sig000000ab ),
.DI(\blk00000001/sig000001bf ),
.S(\blk00000001/sig000000cd ),
.O(\blk00000001/sig000000ac )
);
XORCY \blk00000001/blk00000050 (
.CI(\blk00000001/sig000000ab ),
.LI(\blk00000001/sig000000cd ),
.O(\blk00000001/sig000001fa )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk0000004f (
.I0(\blk00000001/sig000001c0 ),
.I1(\blk00000001/sig000000f0 ),
.O(\blk00000001/sig000000ce )
);
MUXCY \blk00000001/blk0000004e (
.CI(\blk00000001/sig000000ac ),
.DI(\blk00000001/sig000001c0 ),
.S(\blk00000001/sig000000ce ),
.O(\blk00000001/sig000000ad )
);
XORCY \blk00000001/blk0000004d (
.CI(\blk00000001/sig000000ac ),
.LI(\blk00000001/sig000000ce ),
.O(\blk00000001/sig000001fb )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk0000004c (
.I0(\blk00000001/sig000001c1 ),
.I1(\blk00000001/sig000000f1 ),
.O(\blk00000001/sig000000cf )
);
MUXCY \blk00000001/blk0000004b (
.CI(\blk00000001/sig000000ad ),
.DI(\blk00000001/sig000001c1 ),
.S(\blk00000001/sig000000cf ),
.O(\blk00000001/sig000000ae )
);
XORCY \blk00000001/blk0000004a (
.CI(\blk00000001/sig000000ad ),
.LI(\blk00000001/sig000000cf ),
.O(\blk00000001/sig000001fc )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000049 (
.I0(\blk00000001/sig000001ac ),
.I1(\blk00000001/sig000000e3 ),
.O(\blk00000001/sig000000b0 )
);
MUXCY \blk00000001/blk00000048 (
.CI(\blk00000001/sig000000ae ),
.DI(\blk00000001/sig000001ac ),
.S(\blk00000001/sig000000b0 ),
.O(\blk00000001/sig00000090 )
);
XORCY \blk00000001/blk00000047 (
.CI(\blk00000001/sig000000ae ),
.LI(\blk00000001/sig000000b0 ),
.O(\blk00000001/sig000001df )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000046 (
.I0(\blk00000001/sig000001ad ),
.I1(\blk00000001/sig000000e4 ),
.O(\blk00000001/sig000000b1 )
);
MUXCY \blk00000001/blk00000045 (
.CI(\blk00000001/sig00000090 ),
.DI(\blk00000001/sig000001ad ),
.S(\blk00000001/sig000000b1 ),
.O(\blk00000001/sig00000091 )
);
XORCY \blk00000001/blk00000044 (
.CI(\blk00000001/sig00000090 ),
.LI(\blk00000001/sig000000b1 ),
.O(\blk00000001/sig000001e0 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000043 (
.I0(\blk00000001/sig000001ae ),
.I1(\blk00000001/sig000000e5 ),
.O(\blk00000001/sig000000b2 )
);
MUXCY \blk00000001/blk00000042 (
.CI(\blk00000001/sig00000091 ),
.DI(\blk00000001/sig000001ae ),
.S(\blk00000001/sig000000b2 ),
.O(\blk00000001/sig00000092 )
);
XORCY \blk00000001/blk00000041 (
.CI(\blk00000001/sig00000091 ),
.LI(\blk00000001/sig000000b2 ),
.O(\blk00000001/sig000001e1 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000040 (
.I0(\blk00000001/sig000001af ),
.I1(\blk00000001/sig000000e6 ),
.O(\blk00000001/sig000000b3 )
);
MUXCY \blk00000001/blk0000003f (
.CI(\blk00000001/sig00000092 ),
.DI(\blk00000001/sig000001af ),
.S(\blk00000001/sig000000b3 ),
.O(\blk00000001/sig00000093 )
);
XORCY \blk00000001/blk0000003e (
.CI(\blk00000001/sig00000092 ),
.LI(\blk00000001/sig000000b3 ),
.O(\blk00000001/sig000001e2 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk0000003d (
.I0(\blk00000001/sig000001b0 ),
.I1(\blk00000001/sig000000e7 ),
.O(\blk00000001/sig000000b4 )
);
MUXCY \blk00000001/blk0000003c (
.CI(\blk00000001/sig00000093 ),
.DI(\blk00000001/sig000001b0 ),
.S(\blk00000001/sig000000b4 ),
.O(\blk00000001/sig00000094 )
);
XORCY \blk00000001/blk0000003b (
.CI(\blk00000001/sig00000093 ),
.LI(\blk00000001/sig000000b4 ),
.O(\blk00000001/sig000001e3 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk0000003a (
.I0(\blk00000001/sig000001b1 ),
.I1(\blk00000001/sig000000e8 ),
.O(\blk00000001/sig000000b5 )
);
MUXCY \blk00000001/blk00000039 (
.CI(\blk00000001/sig00000094 ),
.DI(\blk00000001/sig000001b1 ),
.S(\blk00000001/sig000000b5 ),
.O(\blk00000001/sig00000095 )
);
XORCY \blk00000001/blk00000038 (
.CI(\blk00000001/sig00000094 ),
.LI(\blk00000001/sig000000b5 ),
.O(\blk00000001/sig000001e4 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000037 (
.I0(\blk00000001/sig000001b2 ),
.I1(\blk00000001/sig000000e9 ),
.O(\blk00000001/sig000000b6 )
);
MUXCY \blk00000001/blk00000036 (
.CI(\blk00000001/sig00000095 ),
.DI(\blk00000001/sig000001b2 ),
.S(\blk00000001/sig000000b6 ),
.O(\blk00000001/sig00000096 )
);
XORCY \blk00000001/blk00000035 (
.CI(\blk00000001/sig00000095 ),
.LI(\blk00000001/sig000000b6 ),
.O(\blk00000001/sig000001e5 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000034 (
.I0(\blk00000001/sig000001b3 ),
.I1(\blk00000001/sig000001d0 ),
.O(\blk00000001/sig000000b7 )
);
MUXCY \blk00000001/blk00000033 (
.CI(\blk00000001/sig00000096 ),
.DI(\blk00000001/sig000001b3 ),
.S(\blk00000001/sig000000b7 ),
.O(\blk00000001/sig00000097 )
);
XORCY \blk00000001/blk00000032 (
.CI(\blk00000001/sig00000096 ),
.LI(\blk00000001/sig000000b7 ),
.O(\blk00000001/sig000001e6 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000031 (
.I0(\blk00000001/sig000001b4 ),
.I1(\blk00000001/sig000001d1 ),
.O(\blk00000001/sig000000b8 )
);
MUXCY \blk00000001/blk00000030 (
.CI(\blk00000001/sig00000097 ),
.DI(\blk00000001/sig000001b4 ),
.S(\blk00000001/sig000000b8 ),
.O(\blk00000001/sig00000098 )
);
XORCY \blk00000001/blk0000002f (
.CI(\blk00000001/sig00000097 ),
.LI(\blk00000001/sig000000b8 ),
.O(\blk00000001/sig000001e7 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk0000002e (
.I0(\blk00000001/sig000001b5 ),
.I1(\blk00000001/sig000001d6 ),
.O(\blk00000001/sig000000b9 )
);
MUXCY \blk00000001/blk0000002d (
.CI(\blk00000001/sig00000098 ),
.DI(\blk00000001/sig000001b5 ),
.S(\blk00000001/sig000000b9 ),
.O(\blk00000001/sig00000099 )
);
XORCY \blk00000001/blk0000002c (
.CI(\blk00000001/sig00000098 ),
.LI(\blk00000001/sig000000b9 ),
.O(\blk00000001/sig000001e8 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk0000002b (
.I0(\blk00000001/sig000001b7 ),
.I1(\blk00000001/sig000001d7 ),
.O(\blk00000001/sig000000bb )
);
MUXCY \blk00000001/blk0000002a (
.CI(\blk00000001/sig00000099 ),
.DI(\blk00000001/sig000001b7 ),
.S(\blk00000001/sig000000bb ),
.O(\blk00000001/sig0000009b )
);
XORCY \blk00000001/blk00000029 (
.CI(\blk00000001/sig00000099 ),
.LI(\blk00000001/sig000000bb ),
.O(\blk00000001/sig000001ea )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000028 (
.I0(\blk00000001/sig000001b8 ),
.I1(\blk00000001/sig000001d8 ),
.O(\blk00000001/sig000000bc )
);
MUXCY \blk00000001/blk00000027 (
.CI(\blk00000001/sig0000009b ),
.DI(\blk00000001/sig000001b8 ),
.S(\blk00000001/sig000000bc ),
.O(\blk00000001/sig0000009c )
);
XORCY \blk00000001/blk00000026 (
.CI(\blk00000001/sig0000009b ),
.LI(\blk00000001/sig000000bc ),
.O(\blk00000001/sig000001eb )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000025 (
.I0(\blk00000001/sig000001b9 ),
.I1(\blk00000001/sig000001d9 ),
.O(\blk00000001/sig000000bd )
);
MUXCY \blk00000001/blk00000024 (
.CI(\blk00000001/sig0000009c ),
.DI(\blk00000001/sig000001b9 ),
.S(\blk00000001/sig000000bd ),
.O(\blk00000001/sig0000009d )
);
XORCY \blk00000001/blk00000023 (
.CI(\blk00000001/sig0000009c ),
.LI(\blk00000001/sig000000bd ),
.O(\blk00000001/sig000001ec )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000022 (
.I0(\blk00000001/sig000001da ),
.I1(\blk00000001/sig000001ba ),
.O(\blk00000001/sig000000be )
);
MUXCY \blk00000001/blk00000021 (
.CI(\blk00000001/sig0000009d ),
.DI(\blk00000001/sig000001ba ),
.S(\blk00000001/sig000000be ),
.O(\blk00000001/sig0000009e )
);
XORCY \blk00000001/blk00000020 (
.CI(\blk00000001/sig0000009d ),
.LI(\blk00000001/sig000000be ),
.O(\blk00000001/sig000001ed )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk0000001f (
.I0(\blk00000001/sig000001ba ),
.I1(\blk00000001/sig000001db ),
.O(\blk00000001/sig000000bf )
);
MUXCY \blk00000001/blk0000001e (
.CI(\blk00000001/sig0000009e ),
.DI(\blk00000001/sig000001ba ),
.S(\blk00000001/sig000000bf ),
.O(\blk00000001/sig0000009f )
);
XORCY \blk00000001/blk0000001d (
.CI(\blk00000001/sig0000009e ),
.LI(\blk00000001/sig000000bf ),
.O(\blk00000001/sig000001ee )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk0000001c (
.I0(\blk00000001/sig000001ba ),
.I1(\blk00000001/sig000001dc ),
.O(\blk00000001/sig000000c0 )
);
MUXCY \blk00000001/blk0000001b (
.CI(\blk00000001/sig0000009f ),
.DI(\blk00000001/sig000001ba ),
.S(\blk00000001/sig000000c0 ),
.O(\blk00000001/sig000000a0 )
);
XORCY \blk00000001/blk0000001a (
.CI(\blk00000001/sig0000009f ),
.LI(\blk00000001/sig000000c0 ),
.O(\blk00000001/sig000001ef )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000019 (
.I0(\blk00000001/sig000001ba ),
.I1(\blk00000001/sig000001dd ),
.O(\blk00000001/sig000000c1 )
);
MUXCY \blk00000001/blk00000018 (
.CI(\blk00000001/sig000000a0 ),
.DI(\blk00000001/sig000001ba ),
.S(\blk00000001/sig000000c1 ),
.O(\blk00000001/sig000000a1 )
);
XORCY \blk00000001/blk00000017 (
.CI(\blk00000001/sig000000a0 ),
.LI(\blk00000001/sig000000c1 ),
.O(\blk00000001/sig000001f0 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000016 (
.I0(\blk00000001/sig000001ba ),
.I1(\blk00000001/sig000001d2 ),
.O(\blk00000001/sig000000c2 )
);
MUXCY \blk00000001/blk00000015 (
.CI(\blk00000001/sig000000a1 ),
.DI(\blk00000001/sig000001ba ),
.S(\blk00000001/sig000000c2 ),
.O(\blk00000001/sig000000a2 )
);
XORCY \blk00000001/blk00000014 (
.CI(\blk00000001/sig000000a1 ),
.LI(\blk00000001/sig000000c2 ),
.O(\blk00000001/sig000001f1 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000013 (
.I0(\blk00000001/sig000001ba ),
.I1(\blk00000001/sig000001d3 ),
.O(\blk00000001/sig000000c3 )
);
MUXCY \blk00000001/blk00000012 (
.CI(\blk00000001/sig000000a2 ),
.DI(\blk00000001/sig000001ba ),
.S(\blk00000001/sig000000c3 ),
.O(\blk00000001/sig000000a3 )
);
XORCY \blk00000001/blk00000011 (
.CI(\blk00000001/sig000000a2 ),
.LI(\blk00000001/sig000000c3 ),
.O(\blk00000001/sig000001f2 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000010 (
.I0(\blk00000001/sig000001ba ),
.I1(\blk00000001/sig000001d4 ),
.O(\blk00000001/sig000000c4 )
);
MUXCY \blk00000001/blk0000000f (
.CI(\blk00000001/sig000000a3 ),
.DI(\blk00000001/sig000001ba ),
.S(\blk00000001/sig000000c4 ),
.O(\blk00000001/sig000000a4 )
);
XORCY \blk00000001/blk0000000e (
.CI(\blk00000001/sig000000a3 ),
.LI(\blk00000001/sig000000c4 ),
.O(\blk00000001/sig000001f3 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk0000000d (
.I0(\blk00000001/sig000001ba ),
.I1(\blk00000001/sig000001d5 ),
.O(\blk00000001/sig000000c6 )
);
MUXCY \blk00000001/blk0000000c (
.CI(\blk00000001/sig000000a4 ),
.DI(\blk00000001/sig000001ba ),
.S(\blk00000001/sig000000c6 ),
.O(\blk00000001/sig000000a6 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk0000000b (
.I0(\blk00000001/sig000001ba ),
.I1(\blk00000001/sig000001d5 ),
.O(\blk00000001/sig000000c7 )
);
MUXCY \blk00000001/blk0000000a (
.CI(\blk00000001/sig000000a6 ),
.DI(\blk00000001/sig000001ba ),
.S(\blk00000001/sig000000c7 ),
.O(\blk00000001/sig000000a7 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000009 (
.I0(\blk00000001/sig000001ba ),
.I1(\blk00000001/sig000001d5 ),
.O(\blk00000001/sig000000c8 )
);
XORCY \blk00000001/blk00000008 (
.CI(\blk00000001/sig000000a7 ),
.LI(\blk00000001/sig000000c8 ),
.O(\blk00000001/sig000001f7 )
);
MULT18X18S \blk00000001/blk00000007 (
.C(clk),
.CE(\blk00000001/sig00000044 ),
.R(\blk00000001/sig00000043 ),
.A({\blk00000001/sig00000043 , a[16], a[15], a[14], a[13], a[12], a[11], a[10], a[9], a[8], a[7], a[6], a[5], a[4], a[3], a[2], a[1], a[0]}),
.B({\blk00000001/sig00000043 , b[16], b[15], b[14], b[13], b[12], b[11], b[10], b[9], b[8], b[7], b[6], b[5], b[4], b[3], b[2], b[1], b[0]}),
.P({\NLW_blk00000001/blk00000007_P<35>_UNCONNECTED , \blk00000001/sig0000010d , \blk00000001/sig0000010c , \blk00000001/sig0000010b ,
\blk00000001/sig0000010a , \blk00000001/sig00000109 , \blk00000001/sig00000107 , \blk00000001/sig00000106 , \blk00000001/sig00000105 ,
\blk00000001/sig00000104 , \blk00000001/sig00000103 , \blk00000001/sig00000102 , \blk00000001/sig00000101 , \blk00000001/sig00000100 ,
\blk00000001/sig000000ff , \blk00000001/sig000000fe , \blk00000001/sig000000fc , \blk00000001/sig000000fb , \blk00000001/sig000000fa ,
\blk00000001/sig000000f9 , \blk00000001/sig000000f8 , \blk00000001/sig000000f7 , \blk00000001/sig000000f6 , \blk00000001/sig000000f5 ,
\blk00000001/sig000000f4 , \blk00000001/sig000000f3 , \blk00000001/sig00000114 , \blk00000001/sig00000113 , \blk00000001/sig00000112 ,
\blk00000001/sig00000111 , \blk00000001/sig00000110 , \blk00000001/sig0000010f , \blk00000001/sig0000010e , \blk00000001/sig00000108 ,
\blk00000001/sig000000fd , \blk00000001/sig000000f2 })
);
MULT18X18S \blk00000001/blk00000006 (
.C(clk),
.CE(\blk00000001/sig00000044 ),
.R(\blk00000001/sig00000043 ),
.A({\blk00000001/sig00000043 , a[16], a[15], a[14], a[13], a[12], a[11], a[10], a[9], a[8], a[7], a[6], a[5], a[4], a[3], a[2], a[1], a[0]}),
.B({b[23], b[23], b[23], b[23], b[23], b[23], b[23], b[23], b[23], b[23], b[23], b[23], b[22], b[21], b[20], b[19], b[18], b[17]}),
.P({\NLW_blk00000001/blk00000006_P<35>_UNCONNECTED , \NLW_blk00000001/blk00000006_P<34>_UNCONNECTED ,
\NLW_blk00000001/blk00000006_P<33>_UNCONNECTED , \NLW_blk00000001/blk00000006_P<32>_UNCONNECTED , \NLW_blk00000001/blk00000006_P<31>_UNCONNECTED ,
\NLW_blk00000001/blk00000006_P<30>_UNCONNECTED , \NLW_blk00000001/blk00000006_P<29>_UNCONNECTED , \NLW_blk00000001/blk00000006_P<28>_UNCONNECTED ,
\NLW_blk00000001/blk00000006_P<27>_UNCONNECTED , \NLW_blk00000001/blk00000006_P<26>_UNCONNECTED , \NLW_blk00000001/blk00000006_P<25>_UNCONNECTED ,
\NLW_blk00000001/blk00000006_P<24>_UNCONNECTED , \blk00000001/sig00000124 , \blk00000001/sig00000123 , \blk00000001/sig00000122 ,
\blk00000001/sig00000121 , \blk00000001/sig0000011f , \blk00000001/sig0000011e , \blk00000001/sig0000011d , \blk00000001/sig0000011c ,
\blk00000001/sig0000011b , \blk00000001/sig0000011a , \blk00000001/sig00000119 , \blk00000001/sig00000118 , \blk00000001/sig00000117 ,
\blk00000001/sig00000116 , \blk00000001/sig0000012c , \blk00000001/sig0000012b , \blk00000001/sig0000012a , \blk00000001/sig00000129 ,
\blk00000001/sig00000128 , \blk00000001/sig00000127 , \blk00000001/sig00000126 , \blk00000001/sig00000125 , \blk00000001/sig00000120 ,
\blk00000001/sig00000115 })
);
MULT18X18S \blk00000001/blk00000005 (
.C(clk),
.CE(\blk00000001/sig00000044 ),
.R(\blk00000001/sig00000043 ),
.A({a[23], a[23], a[23], a[23], a[23], a[23], a[23], a[23], a[23], a[23], a[23], a[23], a[22], a[21], a[20], a[19], a[18], a[17]}),
.B({\blk00000001/sig00000043 , b[16], b[15], b[14], b[13], b[12], b[11], b[10], b[9], b[8], b[7], b[6], b[5], b[4], b[3], b[2], b[1], b[0]}),
.P({\NLW_blk00000001/blk00000005_P<35>_UNCONNECTED , \NLW_blk00000001/blk00000005_P<34>_UNCONNECTED ,
\NLW_blk00000001/blk00000005_P<33>_UNCONNECTED , \NLW_blk00000001/blk00000005_P<32>_UNCONNECTED , \NLW_blk00000001/blk00000005_P<31>_UNCONNECTED ,
\NLW_blk00000001/blk00000005_P<30>_UNCONNECTED , \NLW_blk00000001/blk00000005_P<29>_UNCONNECTED , \NLW_blk00000001/blk00000005_P<28>_UNCONNECTED ,
\NLW_blk00000001/blk00000005_P<27>_UNCONNECTED , \NLW_blk00000001/blk00000005_P<26>_UNCONNECTED , \NLW_blk00000001/blk00000005_P<25>_UNCONNECTED ,
\NLW_blk00000001/blk00000005_P<24>_UNCONNECTED , \blk00000001/sig0000013c , \blk00000001/sig0000013b , \blk00000001/sig0000013a ,
\blk00000001/sig00000139 , \blk00000001/sig00000137 , \blk00000001/sig00000136 , \blk00000001/sig00000135 , \blk00000001/sig00000134 ,
\blk00000001/sig00000133 , \blk00000001/sig00000132 , \blk00000001/sig00000131 , \blk00000001/sig00000130 , \blk00000001/sig0000012f ,
\blk00000001/sig0000012e , \blk00000001/sig00000144 , \blk00000001/sig00000143 , \blk00000001/sig00000142 , \blk00000001/sig00000141 ,
\blk00000001/sig00000140 , \blk00000001/sig0000013f , \blk00000001/sig0000013e , \blk00000001/sig0000013d , \blk00000001/sig00000138 ,
\blk00000001/sig0000012d })
);
MULT18X18S \blk00000001/blk00000004 (
.C(clk),
.CE(\blk00000001/sig00000044 ),
.R(\blk00000001/sig00000043 ),
.A({a[23], a[23], a[23], a[23], a[23], a[23], a[23], a[23], a[23], a[23], a[23], a[23], a[22], a[21], a[20], a[19], a[18], a[17]}),
.B({b[23], b[23], b[23], b[23], b[23], b[23], b[23], b[23], b[23], b[23], b[23], b[23], b[22], b[21], b[20], b[19], b[18], b[17]}),
.P({\NLW_blk00000001/blk00000004_P<35>_UNCONNECTED , \NLW_blk00000001/blk00000004_P<34>_UNCONNECTED ,
\NLW_blk00000001/blk00000004_P<33>_UNCONNECTED , \NLW_blk00000001/blk00000004_P<32>_UNCONNECTED , \NLW_blk00000001/blk00000004_P<31>_UNCONNECTED ,
\NLW_blk00000001/blk00000004_P<30>_UNCONNECTED , \NLW_blk00000001/blk00000004_P<29>_UNCONNECTED , \NLW_blk00000001/blk00000004_P<28>_UNCONNECTED ,
\NLW_blk00000001/blk00000004_P<27>_UNCONNECTED , \NLW_blk00000001/blk00000004_P<26>_UNCONNECTED , \NLW_blk00000001/blk00000004_P<25>_UNCONNECTED ,
\NLW_blk00000001/blk00000004_P<24>_UNCONNECTED , \NLW_blk00000001/blk00000004_P<23>_UNCONNECTED , \NLW_blk00000001/blk00000004_P<22>_UNCONNECTED ,
\NLW_blk00000001/blk00000004_P<21>_UNCONNECTED , \NLW_blk00000001/blk00000004_P<20>_UNCONNECTED , \NLW_blk00000001/blk00000004_P<19>_UNCONNECTED ,
\NLW_blk00000001/blk00000004_P<18>_UNCONNECTED , \NLW_blk00000001/blk00000004_P<17>_UNCONNECTED , \NLW_blk00000001/blk00000004_P<16>_UNCONNECTED ,
\NLW_blk00000001/blk00000004_P<15>_UNCONNECTED , \NLW_blk00000001/blk00000004_P<14>_UNCONNECTED , \blk00000001/sig00000149 , \blk00000001/sig00000148
, \blk00000001/sig00000147 , \blk00000001/sig00000146 , \blk00000001/sig00000152 , \blk00000001/sig00000151 , \blk00000001/sig00000150 ,
\blk00000001/sig0000014f , \blk00000001/sig0000014e , \blk00000001/sig0000014d , \blk00000001/sig0000014c , \blk00000001/sig0000014b ,
\blk00000001/sig0000014a , \blk00000001/sig00000145 })
);
VCC \blk00000001/blk00000003 (
.P(\blk00000001/sig00000044 )
);
GND \blk00000001/blk00000002 (
.G(\blk00000001/sig00000043 )
);
// synthesis translate_on
endmodule
|
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
|
module top(input clk, stb, di, output do);
localparam integer DIN_N = 256;
localparam integer DOUT_N = 256;
reg [DIN_N-1:0] din;
wire [DOUT_N-1:0] dout;
reg [DIN_N-1:0] din_shr;
reg [DOUT_N-1:0] dout_shr;
always @(posedge clk) begin
din_shr <= {din_shr, di};
dout_shr <= {dout_shr, din_shr[DIN_N-1]};
if (stb) begin
din <= din_shr;
dout_shr <= dout;
end
end
assign do = dout_shr[DOUT_N-1];
roi roi (
.clk(clk),
.din(din),
.dout(dout)
);
endmodule
|
module roi(input clk, input [255:0] din, output [255:0] dout);
`define ALL1
`ifdef ALL1
//ok
my_NDI1MUX_NMC31 #(.LOC("SLICE_X8Y100"))
my_NDI1MUX_NMC31(.clk(clk), .din(din[ 0 +: 8]), .dout(dout[ 0 +: 8]));
/*
//Can't find a valid solution
my_NDI1MUX_NDI1 #(.LOC("SLICE_X8Y101"))
my_NDI1MUX_NDI1(.clk(clk), .din(din[ 8 +: 32]), .dout(dout[ 8 +: 8]));
*/
my_NDI1MUX_NI #(.LOC("SLICE_X8Y102"))
my_NDI1MUX_NI(.clk(clk), .din(din[ 40 +: 8]), .dout(dout[ 40 +: 8]));
`endif
`define SINGLE1
`ifdef SINGLE1
//ok
my_ADI1MUX_BMC31 #(.LOC("SLICE_X10Y100"))
my_ADI1MUX_BMC31(.clk(clk), .din(din[ 64 +: 8]), .dout(dout[ 64 +: 8]));
//ok
my_ADI1MUX_AI #(.LOC("SLICE_X10Y101"))
my_ADI1MUX_AI(.clk(clk), .din(din[ 72 +: 8]), .dout(dout[ 72 +: 8]));
/*
//bad
my_ADI1MUX_BDI1 #(.LOC("SLICE_X10Y102"))
my_ADI1MUX_BDI1(.clk(clk), .din(din[ 80 +: 16]), .dout(dout[ 80 +: 16]));
*/
my_BDI1MUX_DI #(.LOC("SLICE_X10Y103"))
my_BDI1MUX_DI(.clk(clk), .din(din[ 96 +: 16]), .dout(dout[ 96 +: 16]));
`endif
endmodule
|
module my_NDI1MUX_NMC31 (input clk, input [7:0] din, output [7:0] dout);
parameter LOC = "SLICE_X6Y100";
wire [3:0] q31;
(* LOC=LOC, BEL="D6LUT" *)
SRLC32E #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0)
) lutd (
.Q(dout[0]),
.Q31(q31[3]),
.A(din[4:0]),
.CE(din[5]),
.CLK(din[6]),
.D(din[7]));
(* LOC=LOC, BEL="C6LUT" *)
SRLC32E #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0)
) lutc (
.Q(dout[1]),
.Q31(q31[2]),
.A(din[4:0]),
.CE(din[5]),
.CLK(din[6]),
//.D(din[7]));
.D(q31[3]));
(* LOC=LOC, BEL="B6LUT" *)
SRLC32E #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0)
) lutb (
.Q(dout[2]),
.Q31(q31[1]),
.A(din[4:0]),
.CE(din[5]),
.CLK(din[6]),
//.D(din[7]));
.D(q31[2]));
(* LOC=LOC, BEL="A6LUT" *)
SRLC32E #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0)
) luta (
.Q(dout[3]),
.Q31(q31[0]),
.A(din[4:0]),
.CE(din[5]),
.CLK(din[6]),
//.D(din[7]));
.D(q31[1]));
endmodule
|
module my_NDI1MUX_NDI1 (input clk, input [31:0] din, output [7:0] dout);
parameter LOC = "SLICE_X6Y100";
wire [3:0] q31;
(* LOC=LOC, BEL="D6LUT" *)
SRLC32E #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0)
) lutd (
.Q(dout[0]),
.Q31(q31[3]),
.A(din[4:0]),
.CE(din[5]),
.CLK(din[6]),
.D(din[7]));
(* LOC=LOC, BEL="C6LUT" *)
SRLC32E #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0)
) lutc (
.Q(dout[1]),
.Q31(q31[2]),
.A(din[12:8]),
.CE(din[5]),
.CLK(din[6]),
.D(din[15]));
(* LOC=LOC, BEL="B6LUT" *)
SRLC32E #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0)
) lutb (
.Q(dout[2]),
.Q31(q31[1]),
.A(din[20:16]),
.CE(din[5]),
.CLK(din[6]),
//.D(din[23]));
.D(q31[2]));
(* LOC=LOC, BEL="A6LUT" *)
SRLC32E #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0)
) luta (
.Q(dout[3]),
.Q31(q31[0]),
.A(din[28:24]),
.CE(din[5]),
.CLK(din[6]),
//.D(din[31]));
.D(q31[2]));
endmodule
|
module my_NDI1MUX_NI (input clk, input [7:0] din, output [7:0] dout);
parameter LOC = "SLICE_X6Y100";
(* LOC=LOC, BEL="D6LUT" *)
SRLC32E #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0)
) lutd (
.Q(dout[0]),
.Q31(),
.A(din[4:0]),
.CE(din[5]),
.CLK(din[6]),
.D(din[7]));
(* LOC=LOC, BEL="C6LUT" *)
SRLC32E #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0)
) lutc (
.Q(dout[1]),
.Q31(),
.A(din[4:0]),
.CE(din[5]),
.CLK(din[6]),
.D(din[7]));
(* LOC=LOC, BEL="B6LUT" *)
SRLC32E #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0)
) lutb (
.Q(dout[2]),
.Q31(),
.A(din[4:0]),
.CE(din[5]),
.CLK(din[6]),
.D(din[7]));
(* LOC=LOC, BEL="A6LUT" *)
SRLC32E #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0)
) luta (
.Q(dout[3]),
.Q31(),
.A(din[4:0]),
.CE(din[5]),
.CLK(din[6]),
.D(din[7]));
endmodule
|
module my_ADI1MUX_AI (input clk, input [7:0] din, output [7:0] dout);
parameter LOC = "";
parameter BEL="A6LUT";
wire mc31c;
(* LOC=LOC, BEL=BEL *)
SRLC32E #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0)
) lut (
.Q(dout[0]),
.Q31(mc31c),
.A(din[4:0]),
.CE(din[5]),
.CLK(din[6]),
.D(din[7]));
endmodule
|
module my_ADI1MUX_BMC31 (input clk, input [7:0] din, output [7:0] dout);
parameter LOC = "";
parameter BELO="B6LUT";
parameter BELI="A6LUT";
wire mc31b;
(* LOC=LOC, BEL=BELO *)
SRLC32E #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0)
) lutb (
.Q(dout[0]),
.Q31(mc31b),
.A(din[4:0]),
.CE(din[5]),
.CLK(din[6]),
.D(din[7]));
(* LOC=LOC, BEL=BELI *)
SRLC32E #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0)
) luta (
.Q(dout[1]),
.Q31(dout[2]),
.A(din[4:0]),
.CE(din[5]),
.CLK(din[6]),
.D(mc31b));
endmodule
|
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