module_content
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1.05M
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module my_ADI1MUX_BDI1 (input clk, input [15:0] din, output [15:0] dout);
parameter LOC = "";
parameter BELO="C6LUT";
parameter BELI="A6LUT";
wire mc31c;
//wire da = din[6];
(* LOC=LOC, BEL=BELO *)
SRLC32E #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0)
) lutb (
.Q(dout[0]),
.Q31(mc31c),
.A(din[4:0]),
.CE(din[5]),
.CLK(din[6]),
.D(din[7]));
(* LOC=LOC, BEL=BELI *)
SRLC32E #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0)
) luta (
.Q(dout[1]),
.Q31(dout[2]),
.A(din[4:0]),
.CE(din[5]),
.CLK(din[6]),
.D(mc31c));
endmodule
|
module my_BDI1MUX_DI (input clk, input [7:0] din, output [7:0] dout);
parameter LOC = "SLICE_X6Y100";
wire di = din[7];
wire wemux = din[5];
(* LOC=LOC, BEL="D6LUT" *)
SRLC32E #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0)
) lutd (
.Q(dout[0]),
.Q31(),
.A(din[4:0]),
.CE(wemux),
.CLK(clk),
.D(di));
(* LOC=LOC, BEL="C6LUT" *)
SRLC32E #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0)
) lutc (
.Q(dout[1]),
.Q31(),
.A(din[4:0]),
.CE(wemux),
.CLK(clk),
.D(din[7]));
(* LOC=LOC, BEL="B6LUT" *)
SRLC32E #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0)
) lutb (
.Q(dout[2]),
.Q31(),
.A(din[4:0]),
.CE(wemux),
.CLK(clk),
.D(di));
(* LOC=LOC, BEL="A6LUT" *)
SRLC32E #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0)
) luta (
.Q(dout[3]),
.Q31(),
.A(din[4:0]),
.CE(wemux),
.CLK(clk),
.D(din[7]));
endmodule
|
module _2bit_up_counter_with_synch_load_enable_clear_tb(
);
reg Clock, Clear, Enable, Load;
wire [1:0] Q;
_2bit_up_counter_with_synch_load_enable_clear DUT (.Clock(Clock), .Clear(Clear), .Enable(Enable), .Load(Load), .Q(Q));
initial begin
#300 $finish;
end
initial begin
Clock = 0; Clear = 0; Enable = 0; Load = 0;
#5 Clock = 1;
#5 Clock = 0; // 10ns
#5 Clock = 1;
#5 Clock = 0; Enable = 1;
#5 Clock = 1;
#5 Clock = 0;
#5 Clock = 1;
#5 Clock = 0; Clear = 1;
#5 Clock = 1;
#5 Clock = 0; // 50ns
#5 Clock = 1;
#5 Clock = 0; Clear = 0;
#5 Clock = 1;
#5 Clock = 0;
#5 Clock = 1;
#5 Clock = 0; Load = 1;
#5 Clock = 1;
#5 Clock = 0; Load = 0; // 90ns
#5 Clock = 1;
#5 Clock = 0; // 100ns
#5 Clock = 1;
#5 Clock = 0; // 110ns
#5 Clock = 1;
#5 Clock = 0;
#5 Clock = 1;
#5 Clock = 0;
#5 Clock = 1;
#5 Clock = 0;
#5 Clock = 1;
#5 Clock = 0; // 150ns
#5 Clock = 1;
#5 Clock = 0;
#5 Clock = 1;
#5 Clock = 0; Enable = 0;
#5 Clock = 1;
#5 Clock = 0;
#5 Clock = 1;
#5 Clock = 0; // 190ns
#5 Clock = 1;
#5 Clock = 0; // 200ns
#5 Clock = 1;
#5 Clock = 0; Enable = 1; // 210ns
#5 Clock = 1;
#5 Clock = 0;
#5 Clock = 1;
#5 Clock = 0;
#5 Clock = 1;
#5 Clock = 0;
#5 Clock = 1;
#5 Clock = 0; // 250ns
#5 Clock = 1;
#5 Clock = 0;
#5 Clock = 1;
#5 Clock = 0;
#5 Clock = 1;
#5 Clock = 0;
#5 Clock = 1;
#5 Clock = 0; // 290ns
#5 Clock = 1;
#5 Clock = 0; // 300ns
end
endmodule
|
module sky130_fd_sc_hs__nand4bb (
Y ,
A_N,
B_N,
C ,
D
);
output Y ;
input A_N;
input B_N;
input C ;
input D ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
endmodule
|
module `AUTOTB_TOP;
parameter AUTOTB_TRANSACTION_NUM = 5;
parameter PROGRESS_TIMEOUT = 10000000;
parameter LATENCY_ESTIMATION = -1;
parameter LENGTH_a = 1;
parameter LENGTH_b = 1;
parameter LENGTH_pResult = 1;
task read_token;
input integer fp;
output reg [191 : 0] token;
integer ret;
begin
token = "";
ret = 0;
ret = $fscanf(fp,"%s",token);
end
endtask
reg AESL_clock;
reg rst;
reg start;
reg ce;
reg tb_continue;
wire AESL_start;
wire AESL_reset;
wire AESL_ce;
wire AESL_ready;
wire AESL_idle;
wire AESL_continue;
wire AESL_done;
reg AESL_done_delay = 0;
reg AESL_done_delay2 = 0;
reg AESL_ready_delay = 0;
wire ready;
wire ready_wire;
wire [5 : 0] gcd_bus_AWADDR;
wire gcd_bus_AWVALID;
wire gcd_bus_AWREADY;
wire gcd_bus_WVALID;
wire gcd_bus_WREADY;
wire [31 : 0] gcd_bus_WDATA;
wire [3 : 0] gcd_bus_WSTRB;
wire [5 : 0] gcd_bus_ARADDR;
wire gcd_bus_ARVALID;
wire gcd_bus_ARREADY;
wire gcd_bus_RVALID;
wire gcd_bus_RREADY;
wire [31 : 0] gcd_bus_RDATA;
wire [1 : 0] gcd_bus_RRESP;
wire gcd_bus_BVALID;
wire gcd_bus_BREADY;
wire [1 : 0] gcd_bus_BRESP;
wire gcd_bus_INTERRUPT;
integer done_cnt = 0;
integer AESL_ready_cnt = 0;
integer ready_cnt = 0;
reg ready_initial;
reg ready_initial_n;
reg ready_last_n;
reg ready_delay_last_n;
reg done_delay_last_n;
reg interface_done = 0;
wire gcd_bus_read_data_finish;
wire gcd_bus_write_data_finish;
wire AESL_slave_start;
reg AESL_slave_start_lock = 0;
wire AESL_slave_write_start_in;
wire AESL_slave_write_start_finish;
reg AESL_slave_ready;
wire AESL_slave_output_done;
wire AESL_slave_done;
reg ready_rise = 0;
reg start_rise = 0;
reg slave_start_status = 0;
reg slave_done_status = 0;
reg ap_done_lock = 0;
wire ap_clk;
wire ap_rst_n;
wire ap_rst_n_n;
`AUTOTB_DUT `AUTOTB_DUT_INST(
.s_axi_gcd_bus_AWADDR(gcd_bus_AWADDR),
.s_axi_gcd_bus_AWVALID(gcd_bus_AWVALID),
.s_axi_gcd_bus_AWREADY(gcd_bus_AWREADY),
.s_axi_gcd_bus_WVALID(gcd_bus_WVALID),
.s_axi_gcd_bus_WREADY(gcd_bus_WREADY),
.s_axi_gcd_bus_WDATA(gcd_bus_WDATA),
.s_axi_gcd_bus_WSTRB(gcd_bus_WSTRB),
.s_axi_gcd_bus_ARADDR(gcd_bus_ARADDR),
.s_axi_gcd_bus_ARVALID(gcd_bus_ARVALID),
.s_axi_gcd_bus_ARREADY(gcd_bus_ARREADY),
.s_axi_gcd_bus_RVALID(gcd_bus_RVALID),
.s_axi_gcd_bus_RREADY(gcd_bus_RREADY),
.s_axi_gcd_bus_RDATA(gcd_bus_RDATA),
.s_axi_gcd_bus_RRESP(gcd_bus_RRESP),
.s_axi_gcd_bus_BVALID(gcd_bus_BVALID),
.s_axi_gcd_bus_BREADY(gcd_bus_BREADY),
.s_axi_gcd_bus_BRESP(gcd_bus_BRESP),
.interrupt(gcd_bus_INTERRUPT),
.ap_clk(ap_clk),
.ap_rst_n(ap_rst_n));
// Assignment for control signal
assign ap_clk = AESL_clock;
assign ap_rst_n = AESL_reset;
assign ap_rst_n_n = ~AESL_reset;
assign AESL_reset = rst;
assign AESL_start = start;
assign AESL_ce = ce;
assign AESL_continue = tb_continue;
assign AESL_slave_write_start_in = slave_start_status & gcd_bus_write_data_finish;
assign AESL_slave_start = AESL_slave_write_start_finish;
assign AESL_done = slave_done_status & gcd_bus_read_data_finish;
always @(posedge AESL_clock)
begin
if(AESL_reset === 0)
begin
slave_start_status <= 1;
end
else begin
if (AESL_start == 1 ) begin
start_rise = 1;
end
if (start_rise == 1 && AESL_done == 1 ) begin
slave_start_status <= 1;
end
if (AESL_slave_write_start_in == 1 && AESL_done == 0) begin
slave_start_status <= 0;
start_rise = 0;
end
end
end
always @(posedge AESL_clock)
begin
if(AESL_reset === 0)
begin
AESL_slave_ready <= 0;
ready_rise = 0;
end
else begin
if (AESL_ready == 1 ) begin
ready_rise = 1;
end
if (ready_rise == 1 && AESL_done_delay == 1 ) begin
AESL_slave_ready <= 1;
end
if (AESL_slave_ready == 1) begin
AESL_slave_ready <= 0;
ready_rise = 0;
end
end
end
always @ (posedge AESL_clock)
begin
if (AESL_done == 1) begin
slave_done_status <= 0;
end
else if (AESL_slave_output_done == 1 ) begin
slave_done_status <= 1;
end
end
AESL_axi_slave_gcd_bus AESL_AXI_SLAVE_gcd_bus(
.clk (AESL_clock),
.reset (AESL_reset),
.TRAN_s_axi_gcd_bus_AWADDR (gcd_bus_AWADDR),
.TRAN_s_axi_gcd_bus_AWVALID (gcd_bus_AWVALID),
.TRAN_s_axi_gcd_bus_AWREADY (gcd_bus_AWREADY),
.TRAN_s_axi_gcd_bus_WVALID (gcd_bus_WVALID),
.TRAN_s_axi_gcd_bus_WREADY (gcd_bus_WREADY),
.TRAN_s_axi_gcd_bus_WDATA (gcd_bus_WDATA),
.TRAN_s_axi_gcd_bus_WSTRB (gcd_bus_WSTRB),
.TRAN_s_axi_gcd_bus_ARADDR (gcd_bus_ARADDR),
.TRAN_s_axi_gcd_bus_ARVALID (gcd_bus_ARVALID),
.TRAN_s_axi_gcd_bus_ARREADY (gcd_bus_ARREADY),
.TRAN_s_axi_gcd_bus_RVALID (gcd_bus_RVALID),
.TRAN_s_axi_gcd_bus_RREADY (gcd_bus_RREADY),
.TRAN_s_axi_gcd_bus_RDATA (gcd_bus_RDATA),
.TRAN_s_axi_gcd_bus_RRESP (gcd_bus_RRESP),
.TRAN_s_axi_gcd_bus_BVALID (gcd_bus_BVALID),
.TRAN_s_axi_gcd_bus_BREADY (gcd_bus_BREADY),
.TRAN_s_axi_gcd_bus_BRESP (gcd_bus_BRESP),
.TRAN_gcd_bus_interrupt (gcd_bus_INTERRUPT),
.TRAN_gcd_bus_read_data_finish(gcd_bus_read_data_finish),
.TRAN_gcd_bus_write_data_finish(gcd_bus_write_data_finish),
.TRAN_gcd_bus_ready_out (AESL_ready),
.TRAN_gcd_bus_ready_in (AESL_slave_ready),
.TRAN_gcd_bus_done_out (AESL_slave_output_done),
.TRAN_gcd_bus_idle_out (AESL_idle),
.TRAN_gcd_bus_write_start_in (AESL_slave_write_start_in),
.TRAN_gcd_bus_write_start_finish (AESL_slave_write_start_finish),
.TRAN_gcd_bus_transaction_done_in (AESL_done_delay),
.TRAN_gcd_bus_start_in (AESL_slave_start)
);
initial begin : generate_AESL_ready_cnt_proc
AESL_ready_cnt = 0;
wait(AESL_reset === 1);
while(AESL_ready_cnt != AUTOTB_TRANSACTION_NUM) begin
while(AESL_ready !== 1) begin
@(posedge AESL_clock);
# 0.4;
end
@(negedge AESL_clock);
AESL_ready_cnt = AESL_ready_cnt + 1;
@(posedge AESL_clock);
# 0.4;
end
end
event next_trigger_ready_cnt;
initial begin : gen_ready_cnt
ready_cnt = 0;
wait (AESL_reset === 1);
forever begin
@ (posedge AESL_clock);
if (ready == 1) begin
if (ready_cnt < AUTOTB_TRANSACTION_NUM) begin
ready_cnt = ready_cnt + 1;
end
end
-> next_trigger_ready_cnt;
end
end
wire all_finish = (done_cnt == AUTOTB_TRANSACTION_NUM);
// done_cnt
always @ (posedge AESL_clock) begin
if (~AESL_reset) begin
done_cnt <= 0;
end else begin
if (AESL_done == 1) begin
if (done_cnt < AUTOTB_TRANSACTION_NUM) begin
done_cnt <= done_cnt + 1;
end
end
end
end
initial begin : finish_simulation
wait (all_finish == 1);
// last transaction is saved at negedge right after last done
@ (posedge AESL_clock);
@ (posedge AESL_clock);
@ (posedge AESL_clock);
@ (posedge AESL_clock);
$finish;
end
initial begin
AESL_clock = 0;
forever #`AUTOTB_CLOCK_PERIOD_DIV2 AESL_clock = ~AESL_clock;
end
reg end_a;
reg [31:0] size_a;
reg [31:0] size_a_backup;
reg end_b;
reg [31:0] size_b;
reg [31:0] size_b_backup;
reg end_pResult;
reg [31:0] size_pResult;
reg [31:0] size_pResult_backup;
initial begin : initial_process
integer proc_rand;
rst = 0;
# 100;
repeat(3) @ (posedge AESL_clock);
rst = 1;
end
initial begin : start_process
integer proc_rand;
reg [31:0] start_cnt;
ce = 1;
start = 0;
start_cnt = 0;
wait (AESL_reset === 1);
@ (posedge AESL_clock);
#0 start = 1;
start_cnt = start_cnt + 1;
forever begin
@ (posedge AESL_clock);
if (start_cnt >= AUTOTB_TRANSACTION_NUM) begin
// keep pushing garbage in
#0 start = 1;
end
if (AESL_ready) begin
start_cnt = start_cnt + 1;
end
end
end
always @(AESL_done)
begin
tb_continue = AESL_done;
end
initial begin : ready_initial_process
ready_initial = 0;
wait (AESL_start === 1);
ready_initial = 1;
@(posedge AESL_clock);
ready_initial = 0;
end
always @(posedge AESL_clock)
begin
if(AESL_reset === 0)
AESL_ready_delay = 0;
else
AESL_ready_delay = AESL_ready;
end
initial begin : ready_last_n_process
ready_last_n = 1;
wait(ready_cnt == AUTOTB_TRANSACTION_NUM)
@(posedge AESL_clock);
ready_last_n <= 0;
end
always @(posedge AESL_clock)
begin
if(AESL_reset === 0)
ready_delay_last_n = 0;
else
ready_delay_last_n <= ready_last_n;
end
assign ready = (ready_initial | AESL_ready_delay);
assign ready_wire = ready_initial | AESL_ready_delay;
initial begin : done_delay_last_n_process
done_delay_last_n = 1;
while(done_cnt < AUTOTB_TRANSACTION_NUM)
@(posedge AESL_clock);
# 0.1;
done_delay_last_n = 0;
end
always @(posedge AESL_clock)
begin
if(AESL_reset === 0)
begin
AESL_done_delay <= 0;
AESL_done_delay2 <= 0;
end
else begin
AESL_done_delay <= AESL_done & done_delay_last_n;
AESL_done_delay2 <= AESL_done_delay;
end
end
always @(posedge AESL_clock)
begin
if(AESL_reset === 0)
interface_done = 0;
else begin
# 0.01;
if(ready === 1 && ready_cnt > 0 && ready_cnt < AUTOTB_TRANSACTION_NUM)
interface_done = 1;
else if(AESL_done_delay === 1 && done_cnt == AUTOTB_TRANSACTION_NUM)
interface_done = 1;
else
interface_done = 0;
end
end
reg dump_tvout_finish_pResult;
initial begin : dump_tvout_runtime_sign_pResult
integer fp;
dump_tvout_finish_pResult = 0;
fp = $fopen(`AUTOTB_TVOUT_pResult_out_wrapc, "w");
if (fp == 0) begin
$display("Failed to open file \"%s\"!", `AUTOTB_TVOUT_pResult_out_wrapc);
$display("ERROR: Simulation using HLS TB failed.");
$finish;
end
$fdisplay(fp,"[[[runtime]]]");
$fclose(fp);
wait (done_cnt == AUTOTB_TRANSACTION_NUM);
// last transaction is saved at negedge right after last done
@ (posedge AESL_clock);
@ (posedge AESL_clock);
@ (posedge AESL_clock);
fp = $fopen(`AUTOTB_TVOUT_pResult_out_wrapc, "a");
if (fp == 0) begin
$display("Failed to open file \"%s\"!", `AUTOTB_TVOUT_pResult_out_wrapc);
$display("ERROR: Simulation using HLS TB failed.");
$finish;
end
$fdisplay(fp,"[[[/runtime]]]");
$fclose(fp);
dump_tvout_finish_pResult = 1;
end
////////////////////////////////////////////
// progress and performance
////////////////////////////////////////////
task wait_start();
while (~AESL_start) begin
@ (posedge AESL_clock);
end
endtask
reg [31:0] clk_cnt = 0;
reg AESL_ready_p1;
reg AESL_start_p1;
always @ (posedge AESL_clock) begin
clk_cnt <= clk_cnt + 1;
AESL_ready_p1 <= AESL_ready;
AESL_start_p1 <= AESL_start;
end
reg [31:0] start_timestamp [0:AUTOTB_TRANSACTION_NUM - 1];
reg [31:0] start_cnt;
reg [31:0] ready_timestamp [0:AUTOTB_TRANSACTION_NUM - 1];
reg [31:0] ap_ready_cnt;
reg [31:0] finish_timestamp [0:AUTOTB_TRANSACTION_NUM - 1];
reg [31:0] finish_cnt;
event report_progress;
initial begin
start_cnt = 0;
finish_cnt = 0;
ap_ready_cnt = 0;
wait (AESL_reset == 1);
wait_start();
start_timestamp[start_cnt] = clk_cnt;
start_cnt = start_cnt + 1;
if (AESL_done) begin
finish_timestamp[finish_cnt] = clk_cnt;
finish_cnt = finish_cnt + 1;
end
-> report_progress;
forever begin
@ (posedge AESL_clock);
if (start_cnt < AUTOTB_TRANSACTION_NUM) begin
if ((AESL_start && AESL_ready_p1)||(AESL_start && ~AESL_start_p1)) begin
start_timestamp[start_cnt] = clk_cnt;
start_cnt = start_cnt + 1;
end
end
if (ap_ready_cnt < AUTOTB_TRANSACTION_NUM) begin
if (AESL_start_p1 && AESL_ready_p1) begin
ready_timestamp[ap_ready_cnt] = clk_cnt;
ap_ready_cnt = ap_ready_cnt + 1;
end
end
if (finish_cnt < AUTOTB_TRANSACTION_NUM) begin
if (AESL_done) begin
finish_timestamp[finish_cnt] = clk_cnt;
finish_cnt = finish_cnt + 1;
end
end
-> report_progress;
end
end
reg [31:0] progress_timeout;
initial begin : simulation_progress
real intra_progress;
wait (AESL_reset == 1);
progress_timeout = PROGRESS_TIMEOUT;
$display("////////////////////////////////////////////////////////////////////////////////////");
$display("// Inter-Transaction Progress: Completed Transaction / Total Transaction");
$display("// Intra-Transaction Progress: Measured Latency / Latency Estimation * 100%%");
$display("//");
$display("// RTL Simulation : \"Inter-Transaction Progress\" [\"Intra-Transaction Progress\"] @ \"Simulation Time\"");
$display("////////////////////////////////////////////////////////////////////////////////////");
print_progress();
while (finish_cnt < AUTOTB_TRANSACTION_NUM) begin
@ (report_progress);
if (finish_cnt < AUTOTB_TRANSACTION_NUM) begin
if (AESL_done) begin
print_progress();
progress_timeout = PROGRESS_TIMEOUT;
end else begin
if (progress_timeout == 0) begin
print_progress();
progress_timeout = PROGRESS_TIMEOUT;
end else begin
progress_timeout = progress_timeout - 1;
end
end
end
end
print_progress();
$display("////////////////////////////////////////////////////////////////////////////////////");
calculate_performance();
end
task get_intra_progress(output real intra_progress);
begin
if (start_cnt > finish_cnt) begin
intra_progress = clk_cnt - start_timestamp[finish_cnt];
end else if(finish_cnt > 0) begin
intra_progress = LATENCY_ESTIMATION;
end else begin
intra_progress = 0;
end
intra_progress = intra_progress / LATENCY_ESTIMATION;
end
endtask
task print_progress();
real intra_progress;
begin
if (LATENCY_ESTIMATION > 0) begin
get_intra_progress(intra_progress);
$display("// RTL Simulation : %0d / %0d [%2.2f%%] @ \"%0t\"", finish_cnt, AUTOTB_TRANSACTION_NUM, intra_progress * 100, $time);
end else begin
$display("// RTL Simulation : %0d / %0d [n/a] @ \"%0t\"", finish_cnt, AUTOTB_TRANSACTION_NUM, $time);
end
end
endtask
task calculate_performance();
integer i;
integer fp;
reg [31:0] latency [0:AUTOTB_TRANSACTION_NUM - 1];
reg [31:0] latency_min;
reg [31:0] latency_max;
reg [31:0] latency_total;
reg [31:0] latency_average;
reg [31:0] interval [0:AUTOTB_TRANSACTION_NUM - 2];
reg [31:0] interval_min;
reg [31:0] interval_max;
reg [31:0] interval_total;
reg [31:0] interval_average;
begin
latency_min = -1;
latency_max = 0;
latency_total = 0;
interval_min = -1;
interval_max = 0;
interval_total = 0;
for (i = 0; i < AUTOTB_TRANSACTION_NUM; i = i + 1) begin
// calculate latency
latency[i] = finish_timestamp[i] - start_timestamp[i];
if (latency[i] > latency_max) latency_max = latency[i];
if (latency[i] < latency_min) latency_min = latency[i];
latency_total = latency_total + latency[i];
// calculate interval
if (AUTOTB_TRANSACTION_NUM == 1) begin
interval[i] = 0;
interval_max = 0;
interval_min = 0;
interval_total = 0;
end else if (i < AUTOTB_TRANSACTION_NUM - 1) begin
interval[i] = finish_timestamp[i] - start_timestamp[i]+1;
if (interval[i] > interval_max) interval_max = interval[i];
if (interval[i] < interval_min) interval_min = interval[i];
interval_total = interval_total + interval[i];
end
end
latency_average = latency_total / AUTOTB_TRANSACTION_NUM;
if (AUTOTB_TRANSACTION_NUM == 1) begin
interval_average = 0;
end else begin
interval_average = interval_total / (AUTOTB_TRANSACTION_NUM - 1);
end
fp = $fopen(`AUTOTB_LAT_RESULT_FILE, "w");
$fdisplay(fp, "$MAX_LATENCY = \"%0d\"", latency_max);
$fdisplay(fp, "$MIN_LATENCY = \"%0d\"", latency_min);
$fdisplay(fp, "$AVER_LATENCY = \"%0d\"", latency_average);
$fdisplay(fp, "$MAX_THROUGHPUT = \"%0d\"", interval_max);
$fdisplay(fp, "$MIN_THROUGHPUT = \"%0d\"", interval_min);
$fdisplay(fp, "$AVER_THROUGHPUT = \"%0d\"", interval_average);
$fclose(fp);
fp = $fopen(`AUTOTB_PER_RESULT_TRANS_FILE, "w");
$fdisplay(fp, "%20s%16s%16s", "", "latency", "interval");
if (AUTOTB_TRANSACTION_NUM == 1) begin
i = 0;
$fdisplay(fp, "transaction%8d:%16d%16d", i, latency[i], interval[i]);
end else begin
for (i = 0; i < AUTOTB_TRANSACTION_NUM; i = i + 1) begin
if (i < AUTOTB_TRANSACTION_NUM - 1) begin
$fdisplay(fp, "transaction%8d:%16d%16d", i, latency[i], interval[i]);
end else begin
$fdisplay(fp, "transaction%8d:%16d x", i, latency[i]);
end
end
end
$fclose(fp);
end
endtask
////////////////////////////////////////////
// Dependence Check
////////////////////////////////////////////
`ifndef POST_SYN
`endif
endmodule
|
module ddr3_controller (
input clk,
input rst,
//Memory Controller Interface
input [27:0] write_address,
input write_en, //set high to initiate a write transaction
//this will not finish until everything in the PPFIFO is empty
input [27:0] read_address,
input read_en, //set high to start populating the read FIFO, set low to end immediately
//PPFIFO Interface
input if_write_strobe,
input [31:0] if_write_data,
output [1:0] if_write_ready,
input [1:0] if_write_activate,
output [23:0] if_write_fifo_size,
output if_starved,
input of_read_strobe,
output of_read_ready,
input of_read_activate,
output [23:0] of_read_size,
output [31:0] of_read_data,
//Local Registers/Wires
output reg cmd_en, //Command is strobed into controller
output reg [2:0] cmd_instr, //Instruction
output reg [5:0] cmd_bl, //Burst Length
output reg [27:0] cmd_word_addr,//Word Address
input cmd_empty, //Command FIFO empty
input cmd_full, //Command FIFO full
output reg wr_en, //Write Data strobe
output reg [3:0] wr_mask, //Write Strobe Mask (Not used, always set to 0)
output [31:0] wr_data, //Data to write into memory
input wr_full, //Write FIFO is full
input wr_empty, //Write FIFO is empty
input [6:0] wr_count, //Number of words in the write FIFO, this is slow to respond
input wr_underrun, //There isn't enough data to fullfill the memory transaction
input wr_error, //FIFO pointers are unsynchronized a reset is the only way to recover
output rd_en, //Enable a read from memory FIFO
input [31:0] rd_data, //data read from FIFO
input rd_full, //FIFO is full
input rd_empty, //FIFO is empty
input [6:0] rd_count, //Number of elements inside the FIFO (This is slow to respond, so don't use it as a clock to clock estimate of how much data is available
input rd_overflow, //the FIFO is overflowed and data is lost
input rd_error //FIFO pointers are out of sync and a reset is required
);
//Local Parameters
localparam CMD_WRITE = 3'b000;
localparam CMD_READ = 3'b001;
localparam CMD_WRITE_PC = 3'b010;
localparam CMD_READ_PC = 3'b011;
localparam CMD_REFRESH = 3'b100;
localparam IDLE = 4'h0;
localparam WRITE_READY = 4'h1;
localparam WRITE_DATA = 4'h2;
localparam WRITE_COMMAND = 4'h3;
localparam READ_READY = 4'h4;
localparam READ_COMMAND = 4'h5;
localparam READ_DATA = 4'h6;
//Registers/Wires
//Write path
reg [3:0] state;
reg [27:0] local_address;
wire if_fifo_idle;
reg if_read_strobe;
wire if_read_ready;
reg if_read_activate;
wire [23:0] if_read_size;
wire [31:0] if_read_data;
wire if_inactive;
reg [23:0] if_read_count;
//Read Path
wire of_starved;
reg of_fifo_reset = 0;
//Read Signals
wire [1:0] of_write_ready;
reg [1:0] of_write_activate;
wire [23:0] of_write_size;
wire of_write_strobe;
wire of_inactive;
reg [23:0] of_write_count;
reg read_request;
reg read_request_count;
reg [31:0] data;
//Submodules
//to_ddr3_fifo
ppfifo#(
.DATA_WIDTH (32 ),
.ADDRESS_WIDTH (6 )
)user_2_mem(
.reset (rst ),
//Write
.write_clock (clk ),
.write_ready (if_write_ready ),
.write_activate (if_write_activate ),
.write_fifo_size (if_write_fifo_size ),
.write_strobe (if_write_strobe ),
.write_data (if_write_data ),
.starved (if_starved ),
//Read
.read_clock (clk ),
.read_strobe (if_read_strobe ),
.read_ready (if_read_ready ),
.read_activate (if_read_activate ),
.read_count (if_read_size ),
.read_data (if_read_data ),
.inactive (if_inactive )
);
ppfifo#(
.DATA_WIDTH (32 ),
.ADDRESS_WIDTH (6 )
)mem_2_user(
.reset (rst || of_fifo_reset ),
//.reset (rst || !read_en ),
//Write
.write_clock (clk ),
.write_ready (of_write_ready ),
.write_activate (of_write_activate ),
.write_fifo_size (of_write_size ),
.write_strobe (of_write_strobe ),
.write_data (rd_data ),
//.write_data (32'h01234567 ),
.starved (of_starved ),
//Read
.read_clock (clk ),
.read_strobe (of_read_strobe ),
.read_ready (of_read_ready ),
.read_activate (of_read_activate ),
.read_count (of_read_size ),
.read_data (of_read_data ),
.inactive (of_inactive )
);
//Asynchronous Logic
assign rd_en = (read_request & !rd_empty);
assign of_write_strobe = rd_en;
assign wr_data = if_read_data;
//Synchronous Logic
always @ (posedge clk) begin
if (rst) begin
state <= IDLE;
cmd_en <= 0;
cmd_instr <= 0;
cmd_bl <= 0;
cmd_word_addr <= 0;
wr_en <= 0; //Strobe data into the write FIFO
//wr_data <= 0; //Data to be sent into the wirte FIFO
wr_mask <= 0;
//rd_en <= 0; //Read Strobe
read_request <= 0;
read_request_count<= 0;
if_read_strobe <= 0;
if_read_activate <= 0;
if_read_count <= 0;
of_fifo_reset <= 0;
of_write_activate <= 0;
of_write_count <= 0;
//data <= 0;
local_address <= 0;
end
else begin
//Strobes
cmd_en <= 0;
wr_en <= 0;
//rd_en <= 0;
read_request <= 0;
if_read_strobe <= 0;
of_fifo_reset <= 0;
//Get an incomming FIFO when available
if (if_read_ready && !if_read_activate) begin
if_read_count <= 0;
if_read_activate <= 1;
end
//Get an outgoing FIFO when available
if ((state == READ_READY) && (of_write_ready > 0) && (of_write_activate == 0)) begin
of_write_count <= 0;
if (of_write_ready[0]) begin
of_write_activate[0] <= 1;
end
else begin
of_write_activate[1] <= 1;
end
end
case (state)
IDLE: begin
if (write_en) begin
state <= WRITE_READY;
local_address <= write_address;
end
else if (read_en) begin
state <= READ_READY;
local_address <= read_address;
end
end
WRITE_READY: begin
//Wait for a FIFO to become ready
if (if_read_activate) begin
state <= WRITE_DATA;
end
else if (!write_en && if_inactive) begin //XXX: There might be an error where data can possible get through when inactive
//For example writing one piece of data as the last piece
state <= IDLE;
end
end
WRITE_DATA: begin
//Since the maximum amount of data can only be 64 we can only fill up the write FIFO
//After we sent out all the data o to write command to issue a command to take care of this
if (if_read_count < if_read_size) begin
//if (!wr_full) begin
if (wr_count < 6'h3F) begin
//data <= if_read_data;
//wr_data <= if_read_data;
wr_en <= 1;
if_read_count <= if_read_count + 24'h1;
if_read_strobe <= 1;
end
else begin
$display ("FIFO Full, attempting to write: %h", if_read_data);
end
end
else begin
state <= WRITE_COMMAND;
end
end
WRITE_COMMAND: begin
if (!cmd_full) begin
cmd_instr <= CMD_WRITE_PC;
cmd_bl <= if_read_count - 24'h1;
cmd_word_addr <= local_address;
cmd_en <= 1;
if_read_activate <= 0;
state <= WRITE_READY;
local_address <= local_address + if_read_count;
end
end
READ_READY: begin
if (read_en) begin
if (of_write_activate > 0) begin
state <= READ_COMMAND;
end
end
else begin
state <= IDLE;
of_fifo_reset <= 1;
end
end
READ_COMMAND: begin
//Send the read command
if(!cmd_full) begin
cmd_instr <= CMD_READ_PC;
cmd_bl <= of_write_size - 24'h1;
cmd_word_addr <= local_address;
cmd_en <= 1;
local_address <= local_address + of_write_size;
state <= READ_DATA;
end
end
READ_DATA: begin
if ((of_write_activate > 0) && (of_write_count < of_write_size)) begin
//if (!rd_empty) begin
read_request <= 1;
if (rd_en) begin
//Srobe the data into the PPFIFO
//rd_en <= 1;
of_write_count <= of_write_count + 24'h1;
end
end
else begin
state <= READ_READY;
if ((of_write_activate > 0) && (of_write_count > 0) && (!of_write_strobe)) begin
of_write_activate <= 0;
end
end
end
default: begin
//XXX: Error Message
state <= 0;
end
endcase
end
end
endmodule
|
module sky130_fd_sc_hdll__o21ba (
X ,
A1 ,
A2 ,
B1_N,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A1 ;
input A2 ;
input B1_N;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire nor0_out ;
wire nor1_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
nor nor0 (nor0_out , A1, A2 );
nor nor1 (nor1_out_X , B1_N, nor0_out );
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, nor1_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
|
module dcm_delay
(// Clock in ports
input clk133,
input CLKFB_IN,
// Clock out ports
output clk133out,
output clk133_p90,
output clk133_p180,
output clk133_p270,
output CLKFB_OUT,
// Status and control signals
input RESET,
output LOCKED
);
// Input buffering
//------------------------------------
assign clkin1 = clk133;
// Clocking primitive
//------------------------------------
// Instantiation of the DCM primitive
// * Unused inputs are tied off
// * Unused outputs are labeled unused
wire psdone_unused;
wire locked_int;
wire [7:0] status_int;
wire clk0;
wire clk90;
wire clk180;
wire clk270;
DCM_SP
#(.CLKDV_DIVIDE (2.000),
.CLKFX_DIVIDE (1),
.CLKFX_MULTIPLY (4),
.CLKIN_DIVIDE_BY_2 ("FALSE"),
.CLKIN_PERIOD (7.518),
.CLKOUT_PHASE_SHIFT ("NONE"),
.CLK_FEEDBACK ("1X"),
.DESKEW_ADJUST ("SYSTEM_SYNCHRONOUS"),
.PHASE_SHIFT (0),
.STARTUP_WAIT ("FALSE"))
dcm_sp_inst
// Input clock
(.CLKIN (clkin1),
.CLKFB (CLKFB_IN),
// Output clocks
.CLK0 (clk0),
.CLK90 (clk90),
.CLK180 (clk180),
.CLK270 (clk270),
.CLK2X (),
.CLK2X180 (),
.CLKFX (),
.CLKFX180 (),
.CLKDV (),
// Ports for dynamic phase shift
.PSCLK (1'b0),
.PSEN (1'b0),
.PSINCDEC (1'b0),
.PSDONE (),
// Other control and status signals
.LOCKED (locked_int),
.STATUS (status_int),
.RST (RESET),
// Unused pin- tie low
.DSSEN (1'b0));
assign LOCKED = locked_int;
// Output buffering
//-----------------------------------
assign CLKFB_OUT = clk0;
BUFG clkout1_buf
(.O (clk133out),
.I (clk0));
BUFG clkout2_buf
(.O (clk133_p90),
.I (clk90));
BUFG clkout3_buf
(.O (clk133_p180),
.I (clk180));
BUFG clkout4_buf
(.O (clk133_p270),
.I (clk270));
endmodule
|
module pcie_core # (
parameter ALLOW_X8_GEN2 = "FALSE",
parameter BAR0 = 32'hFFFFFC0C,
parameter BAR1 = 32'hFFFFFFFF,
parameter BAR2 = 32'hFFF0000C,
parameter BAR3 = 32'hFFFFFFFF,
parameter BAR4 = 32'hFFF8000C,
parameter BAR5 = 32'hFFFFFFFF,
parameter CARDBUS_CIS_POINTER = 32'h00000000,
parameter CLASS_CODE = 24'h050000,
parameter CMD_INTX_IMPLEMENTED = "TRUE",
parameter CPL_TIMEOUT_DISABLE_SUPPORTED = "FALSE",
parameter CPL_TIMEOUT_RANGES_SUPPORTED = 4'h2,
parameter DEV_CAP_ENDPOINT_L0S_LATENCY = 0,
parameter DEV_CAP_ENDPOINT_L1_LATENCY = 7,
parameter DEV_CAP_EXT_TAG_SUPPORTED = "FALSE",
parameter DEV_CAP_MAX_PAYLOAD_SUPPORTED = 2,
parameter DEV_CAP_PHANTOM_FUNCTIONS_SUPPORT = 0,
parameter DEVICE_ID = 16'h6014,
parameter DISABLE_LANE_REVERSAL = "TRUE",
parameter DISABLE_SCRAMBLING = "FALSE",
parameter DSN_BASE_PTR = 12'h100,
parameter DSN_CAP_NEXTPTR = 12'h000,
parameter DSN_CAP_ON = "TRUE",
parameter ENABLE_MSG_ROUTE = 11'b00000000000,
parameter ENABLE_RX_TD_ECRC_TRIM = "TRUE",
parameter EXPANSION_ROM = 32'h00000000,
parameter EXT_CFG_CAP_PTR = 6'h3F,
parameter EXT_CFG_XP_CAP_PTR = 10'h3FF,
parameter HEADER_TYPE = 8'h00,
parameter INTERRUPT_PIN = 8'h1,
parameter LINK_CAP_DLL_LINK_ACTIVE_REPORTING_CAP = "FALSE",
parameter LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP = "FALSE",
parameter LINK_CAP_MAX_LINK_SPEED = 4'h1,
parameter LINK_CAP_MAX_LINK_WIDTH = 6'h04,
parameter LINK_CAP_SURPRISE_DOWN_ERROR_CAPABLE = "FALSE",
parameter LINK_CTRL2_DEEMPHASIS = "FALSE",
parameter LINK_CTRL2_HW_AUTONOMOUS_SPEED_DISABLE = "FALSE",
parameter LINK_CTRL2_TARGET_LINK_SPEED = 4'h0,
parameter LINK_STATUS_SLOT_CLOCK_CONFIG = "TRUE",
parameter LL_ACK_TIMEOUT = 15'h0000,
parameter LL_ACK_TIMEOUT_EN = "FALSE",
parameter LL_ACK_TIMEOUT_FUNC = 0,
parameter LL_REPLAY_TIMEOUT = 15'h0026,
parameter LL_REPLAY_TIMEOUT_EN = "TRUE",
parameter LL_REPLAY_TIMEOUT_FUNC = 1,
parameter LTSSM_MAX_LINK_WIDTH = 6'h04,
parameter MSI_CAP_MULTIMSGCAP = 0,
parameter MSI_CAP_MULTIMSG_EXTENSION = 0,
parameter MSI_CAP_ON = "TRUE",
parameter MSI_CAP_PER_VECTOR_MASKING_CAPABLE = "FALSE",
parameter MSI_CAP_64_BIT_ADDR_CAPABLE = "TRUE",
parameter MSIX_CAP_ON = "FALSE",
parameter MSIX_CAP_PBA_BIR = 0,
parameter MSIX_CAP_PBA_OFFSET = 29'h0,
parameter MSIX_CAP_TABLE_BIR = 0,
parameter MSIX_CAP_TABLE_OFFSET = 29'h0,
parameter MSIX_CAP_TABLE_SIZE = 11'h0,
parameter PCIE_CAP_DEVICE_PORT_TYPE = 4'b0000,
parameter PCIE_CAP_INT_MSG_NUM = 5'h1,
parameter PCIE_CAP_NEXTPTR = 8'h00,
parameter PCIE_DRP_ENABLE = "FALSE",
parameter PIPE_PIPELINE_STAGES = 0, // 0 - 0 stages, 1 - 1 stage, 2 - 2 stages
parameter PM_CAP_DSI = "FALSE",
parameter PM_CAP_D1SUPPORT = "FALSE",
parameter PM_CAP_D2SUPPORT = "FALSE",
parameter PM_CAP_NEXTPTR = 8'h48,
parameter PM_CAP_PMESUPPORT = 5'h0F,
parameter PM_CSR_NOSOFTRST = "TRUE",
parameter PM_DATA_SCALE0 = 2'h0,
parameter PM_DATA_SCALE1 = 2'h0,
parameter PM_DATA_SCALE2 = 2'h0,
parameter PM_DATA_SCALE3 = 2'h0,
parameter PM_DATA_SCALE4 = 2'h0,
parameter PM_DATA_SCALE5 = 2'h0,
parameter PM_DATA_SCALE6 = 2'h0,
parameter PM_DATA_SCALE7 = 2'h0,
parameter PM_DATA0 = 8'h00,
parameter PM_DATA1 = 8'h00,
parameter PM_DATA2 = 8'h00,
parameter PM_DATA3 = 8'h00,
parameter PM_DATA4 = 8'h00,
parameter PM_DATA5 = 8'h00,
parameter PM_DATA6 = 8'h00,
parameter PM_DATA7 = 8'h00,
parameter REF_CLK_FREQ = 0, // 0 - 100 MHz, 1 - 125 MHz, 2 - 250 MHz
parameter REVISION_ID = 8'h00,
parameter SPARE_BIT0 = 0,
parameter SUBSYSTEM_ID = 16'h0007,
parameter SUBSYSTEM_VENDOR_ID = 16'h10EE,
parameter TL_RX_RAM_RADDR_LATENCY = 1,
parameter TL_RX_RAM_RDATA_LATENCY = 3,
parameter TL_RX_RAM_WRITE_LATENCY = 1,
parameter TL_TX_RAM_RADDR_LATENCY = 1,
parameter TL_TX_RAM_RDATA_LATENCY = 3,
parameter TL_TX_RAM_WRITE_LATENCY = 1,
parameter UPCONFIG_CAPABLE = "TRUE",
parameter USER_CLK_FREQ = 2,
parameter VC_BASE_PTR = 12'h0,
parameter VC_CAP_NEXTPTR = 12'h000,
parameter VC_CAP_ON = "FALSE",
parameter VC_CAP_REJECT_SNOOP_TRANSACTIONS = "FALSE",
parameter VC0_CPL_INFINITE = "TRUE",
parameter VC0_RX_RAM_LIMIT = 13'h7FF,
parameter VC0_TOTAL_CREDITS_CD = 308,
parameter VC0_TOTAL_CREDITS_CH = 36,
parameter VC0_TOTAL_CREDITS_NPH = 12,
parameter VC0_TOTAL_CREDITS_PD = 308,
parameter VC0_TOTAL_CREDITS_PH = 32,
parameter VC0_TX_LASTPACKET = 29,
parameter VENDOR_ID = 16'h10EE,
parameter VSEC_BASE_PTR = 12'h0,
parameter VSEC_CAP_NEXTPTR = 12'h000,
parameter VSEC_CAP_ON = "FALSE",
parameter AER_BASE_PTR = 12'h128,
parameter AER_CAP_ECRC_CHECK_CAPABLE = "FALSE",
parameter AER_CAP_ECRC_GEN_CAPABLE = "FALSE",
parameter AER_CAP_ID = 16'h0001,
parameter AER_CAP_INT_MSG_NUM_MSI = 5'h0a,
parameter AER_CAP_INT_MSG_NUM_MSIX = 5'h15,
parameter AER_CAP_NEXTPTR = 12'h160,
parameter AER_CAP_ON = "FALSE",
parameter AER_CAP_PERMIT_ROOTERR_UPDATE = "TRUE",
parameter AER_CAP_VERSION = 4'h1,
parameter CAPABILITIES_PTR = 8'h40,
parameter CRM_MODULE_RSTS = 7'h00,
parameter DEV_CAP_ENABLE_SLOT_PWR_LIMIT_SCALE = "TRUE",
parameter DEV_CAP_ENABLE_SLOT_PWR_LIMIT_VALUE = "TRUE",
parameter DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE = "FALSE",
parameter DEV_CAP_ROLE_BASED_ERROR = "TRUE",
parameter DEV_CAP_RSVD_14_12 = 0,
parameter DEV_CAP_RSVD_17_16 = 0,
parameter DEV_CAP_RSVD_31_29 = 0,
parameter DEV_CONTROL_AUX_POWER_SUPPORTED = "FALSE",
parameter DISABLE_ASPM_L1_TIMER = "FALSE",
parameter DISABLE_BAR_FILTERING = "FALSE",
parameter DISABLE_ID_CHECK = "FALSE",
parameter DISABLE_RX_TC_FILTER = "FALSE",
parameter DNSTREAM_LINK_NUM = 8'h00,
parameter DSN_CAP_ID = 16'h0003,
parameter DSN_CAP_VERSION = 4'h1,
parameter ENTER_RVRY_EI_L0 = "TRUE",
parameter INFER_EI = 5'h0c,
parameter IS_SWITCH = "FALSE",
parameter LAST_CONFIG_DWORD = 10'h3FF,
parameter LINK_CAP_ASPM_SUPPORT = 1,
parameter LINK_CAP_CLOCK_POWER_MANAGEMENT = "FALSE",
parameter LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1 = 7,
parameter LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2 = 7,
parameter LINK_CAP_L0S_EXIT_LATENCY_GEN1 = 7,
parameter LINK_CAP_L0S_EXIT_LATENCY_GEN2 = 7,
parameter LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1 = 7,
parameter LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2 = 7,
parameter LINK_CAP_L1_EXIT_LATENCY_GEN1 = 7,
parameter LINK_CAP_L1_EXIT_LATENCY_GEN2 = 7,
parameter LINK_CAP_RSVD_23_22 = 0,
parameter LINK_CONTROL_RCB = 0,
parameter MSI_BASE_PTR = 8'h48,
parameter MSI_CAP_ID = 8'h05,
parameter MSI_CAP_NEXTPTR = 8'h60,
parameter MSIX_BASE_PTR = 8'h9c,
parameter MSIX_CAP_ID = 8'h11,
parameter MSIX_CAP_NEXTPTR = 8'h00,
parameter N_FTS_COMCLK_GEN1 = 255,
parameter N_FTS_COMCLK_GEN2 = 254,
parameter N_FTS_GEN1 = 255,
parameter N_FTS_GEN2 = 255,
parameter PCIE_BASE_PTR = 8'h60,
parameter PCIE_CAP_CAPABILITY_ID = 8'h10,
parameter PCIE_CAP_CAPABILITY_VERSION = 4'h2,
parameter PCIE_CAP_ON = "TRUE",
parameter PCIE_CAP_RSVD_15_14 = 0,
parameter PCIE_CAP_SLOT_IMPLEMENTED = "FALSE",
parameter PCIE_REVISION = 2,
parameter PGL0_LANE = 0,
parameter PGL1_LANE = 1,
parameter PGL2_LANE = 2,
parameter PGL3_LANE = 3,
parameter PGL4_LANE = 4,
parameter PGL5_LANE = 5,
parameter PGL6_LANE = 6,
parameter PGL7_LANE = 7,
parameter PL_AUTO_CONFIG = 0,
parameter PL_FAST_TRAIN = "FALSE",
parameter PM_BASE_PTR = 8'h40,
parameter PM_CAP_AUXCURRENT = 0,
parameter PM_CAP_ID = 8'h01,
parameter PM_CAP_ON = "TRUE",
parameter PM_CAP_PME_CLOCK = "FALSE",
parameter PM_CAP_RSVD_04 = 0,
parameter PM_CAP_VERSION = 3,
parameter PM_CSR_BPCCEN = "FALSE",
parameter PM_CSR_B2B3 = "FALSE",
parameter RECRC_CHK = 0,
parameter RECRC_CHK_TRIM = "FALSE",
parameter ROOT_CAP_CRS_SW_VISIBILITY = "FALSE",
parameter SELECT_DLL_IF = "FALSE",
parameter SLOT_CAP_ATT_BUTTON_PRESENT = "FALSE",
parameter SLOT_CAP_ATT_INDICATOR_PRESENT = "FALSE",
parameter SLOT_CAP_ELEC_INTERLOCK_PRESENT = "FALSE",
parameter SLOT_CAP_HOTPLUG_CAPABLE = "FALSE",
parameter SLOT_CAP_HOTPLUG_SURPRISE = "FALSE",
parameter SLOT_CAP_MRL_SENSOR_PRESENT = "FALSE",
parameter SLOT_CAP_NO_CMD_COMPLETED_SUPPORT = "FALSE",
parameter SLOT_CAP_PHYSICAL_SLOT_NUM = 13'h0000,
parameter SLOT_CAP_POWER_CONTROLLER_PRESENT = "FALSE",
parameter SLOT_CAP_POWER_INDICATOR_PRESENT = "FALSE",
parameter SLOT_CAP_SLOT_POWER_LIMIT_SCALE = 0,
parameter SLOT_CAP_SLOT_POWER_LIMIT_VALUE = 8'h00,
parameter SPARE_BIT1 = 0,
parameter SPARE_BIT2 = 0,
parameter SPARE_BIT3 = 0,
parameter SPARE_BIT4 = 0,
parameter SPARE_BIT5 = 0,
parameter SPARE_BIT6 = 0,
parameter SPARE_BIT7 = 0,
parameter SPARE_BIT8 = 0,
parameter SPARE_BYTE0 = 8'h00,
parameter SPARE_BYTE1 = 8'h00,
parameter SPARE_BYTE2 = 8'h00,
parameter SPARE_BYTE3 = 8'h00,
parameter SPARE_WORD0 = 32'h00000000,
parameter SPARE_WORD1 = 32'h00000000,
parameter SPARE_WORD2 = 32'h00000000,
parameter SPARE_WORD3 = 32'h00000000,
parameter TL_RBYPASS = "FALSE",
parameter TL_TFC_DISABLE = "FALSE",
parameter TL_TX_CHECKS_DISABLE = "FALSE",
parameter EXIT_LOOPBACK_ON_EI = "TRUE",
parameter UPSTREAM_FACING = "TRUE",
parameter UR_INV_REQ = "TRUE",
parameter VC_CAP_ID = 16'h0002,
parameter VC_CAP_VERSION = 4'h1,
parameter VSEC_CAP_HDR_ID = 16'h1234,
parameter VSEC_CAP_HDR_LENGTH = 12'h018,
parameter VSEC_CAP_HDR_REVISION = 4'h1,
parameter VSEC_CAP_ID = 16'h000b,
parameter VSEC_CAP_IS_LINK_VISIBLE = "TRUE",
parameter VSEC_CAP_VERSION = 4'h1
)
(
//-------------------------------------------------------
// 1. PCI Express (pci_exp) Interface
//-------------------------------------------------------
// Tx
output [(LINK_CAP_MAX_LINK_WIDTH - 1):0] pci_exp_txp,
output [(LINK_CAP_MAX_LINK_WIDTH - 1):0] pci_exp_txn,
// Rx
input [(LINK_CAP_MAX_LINK_WIDTH - 1):0] pci_exp_rxp,
input [(LINK_CAP_MAX_LINK_WIDTH - 1):0] pci_exp_rxn,
//-------------------------------------------------------
// 2. AXI-S Interface
//-------------------------------------------------------
// Common
output user_clk_out,
output user_reset_out,
output user_lnk_up,
// Tx
output [5:0] tx_buf_av,
output tx_err_drop,
output tx_cfg_req,
output s_axis_tx_tready,
input [63:0] s_axis_tx_tdata,
input [7:0] s_axis_tx_tkeep,
input [3:0] s_axis_tx_tuser,
input s_axis_tx_tlast,
input s_axis_tx_tvalid,
input tx_cfg_gnt,
// Rx
output [63:0] m_axis_rx_tdata,
output [7:0] m_axis_rx_tkeep,
output m_axis_rx_tlast,
output m_axis_rx_tvalid,
input m_axis_rx_tready,
output [21:0] m_axis_rx_tuser,
input rx_np_ok,
// Flow Control
output [11:0] fc_cpld,
output [7:0] fc_cplh,
output [11:0] fc_npd,
output [7:0] fc_nph,
output [11:0] fc_pd,
output [7:0] fc_ph,
input [2:0] fc_sel,
//-------------------------------------------------------
// 3. Configuration (CFG) Interface
//-------------------------------------------------------
output [31:0] cfg_do,
output cfg_rd_wr_done,
input [31:0] cfg_di,
input [3:0] cfg_byte_en,
input [9:0] cfg_dwaddr,
input cfg_wr_en,
input cfg_rd_en,
input cfg_err_cor,
input cfg_err_ur,
input cfg_err_ecrc,
input cfg_err_cpl_timeout,
input cfg_err_cpl_abort,
input cfg_err_cpl_unexpect,
input cfg_err_posted,
input cfg_err_locked,
input [47:0] cfg_err_tlp_cpl_header,
output cfg_err_cpl_rdy,
input cfg_interrupt,
output cfg_interrupt_rdy,
input cfg_interrupt_assert,
input [7:0] cfg_interrupt_di,
output [7:0] cfg_interrupt_do,
output [2:0] cfg_interrupt_mmenable,
output cfg_interrupt_msienable,
output cfg_interrupt_msixenable,
output cfg_interrupt_msixfm,
input cfg_turnoff_ok,
output cfg_to_turnoff,
input cfg_trn_pending,
input cfg_pm_wake,
output [7:0] cfg_bus_number,
output [4:0] cfg_device_number,
output [2:0] cfg_function_number,
output [15:0] cfg_status,
output [15:0] cfg_command,
output [15:0] cfg_dstatus,
output [15:0] cfg_dcommand,
output [15:0] cfg_lstatus,
output [15:0] cfg_lcommand,
output [15:0] cfg_dcommand2,
output [2:0] cfg_pcie_link_state,
input [63:0] cfg_dsn,
output cfg_pmcsr_pme_en,
output cfg_pmcsr_pme_status,
output [1:0] cfg_pmcsr_powerstate,
//-------------------------------------------------------
// 4. Physical Layer Control and Status (PL) Interface
//-------------------------------------------------------
output [2:0] pl_initial_link_width,
output [1:0] pl_lane_reversal_mode,
output pl_link_gen2_capable,
output pl_link_partner_gen2_supported,
output pl_link_upcfg_capable,
output [5:0] pl_ltssm_state,
output pl_received_hot_rst,
output pl_sel_link_rate,
output [1:0] pl_sel_link_width,
input pl_directed_link_auton,
input [1:0] pl_directed_link_change,
input pl_directed_link_speed,
input [1:0] pl_directed_link_width,
input pl_upstream_prefer_deemph,
//-------------------------------------------------------
// 5. System (SYS) Interface
//-------------------------------------------------------
input sys_clk,
input sys_reset
);
wire [63:0] trn_td;
wire trn_trem;
wire trn_tsof;
wire trn_teof;
wire trn_tsrc_rdy;
wire trn_tdst_rdy_n;
wire trn_terr_drop_n;
wire trn_tsrc_dsc;
wire trn_terrfwd;
wire trn_tstr;
wire trn_tecrc_gen;
wire [63:0] trn_rd;
wire trn_rrem_n;
wire trn_rsof_n;
wire trn_reof_n;
wire trn_rsrc_rdy_n;
wire trn_rdst_rdy;
wire trn_rsrc_dsc_n;
wire trn_rerrfwd_n;
wire [6:0] trn_rbar_hit_n;
wire trn_tcfg_gnt;
wire [31:0] trn_rdllp_data;
wire trn_rdllp_src_rdy_n;
wire rx_func_level_reset_n;
wire cfg_msg_received;
wire cfg_msg_received_pme_to;
wire cfg_cmd_bme;
wire cfg_cmd_intdis;
wire cfg_cmd_io_en;
wire cfg_cmd_mem_en;
wire cfg_cmd_serr_en;
wire cfg_dev_control_aux_power_en ;
wire cfg_dev_control_corr_err_reporting_en ;
wire cfg_dev_control_enable_relaxed_order ;
wire cfg_dev_control_ext_tag_en ;
wire cfg_dev_control_fatal_err_reporting_en ;
wire [2:0] cfg_dev_control_maxpayload ;
wire [2:0] cfg_dev_control_max_read_req ;
wire cfg_dev_control_non_fatal_reporting_en ;
wire cfg_dev_control_nosnoop_en ;
wire cfg_dev_control_phantom_en ;
wire cfg_dev_control_ur_err_reporting_en ;
wire cfg_dev_control2_cpltimeout_dis ;
wire [3:0] cfg_dev_control2_cpltimeout_val ;
wire cfg_dev_status_corr_err_detected ;
wire cfg_dev_status_fatal_err_detected ;
wire cfg_dev_status_nonfatal_err_detected ;
wire cfg_dev_status_ur_detected ;
wire cfg_link_control_auto_bandwidth_int_en ;
wire cfg_link_control_bandwidth_int_en ;
wire cfg_link_control_hw_auto_width_dis ;
wire cfg_link_control_clock_pm_en ;
wire cfg_link_control_extended_sync ;
wire cfg_link_control_common_clock ;
wire cfg_link_control_retrain_link ;
wire cfg_link_control_linkdisable ;
wire cfg_link_control_rcb ;
wire [1:0] cfg_link_control_aspm_control ;
wire cfg_link_status_autobandwidth_status ;
wire cfg_link_status_bandwidth_status ;
wire cfg_link_status_dll_active ;
wire cfg_link_status_link_training ;
wire [3:0] cfg_link_status_negotiated_link_width ;
wire [1:0] cfg_link_status_current_speed ;
wire [15:0] cfg_msg_data;
wire sys_reset_n_d;
wire phy_rdy_n;
wire trn_lnk_up_n_int;
wire trn_lnk_up_n_int1;
wire trn_reset_n_int;
wire trn_reset_n_int1;
wire TxOutClk;
wire TxOutClk_bufg;
reg [7:0] cfg_bus_number_d;
reg [4:0] cfg_device_number_d;
reg [2:0] cfg_function_number_d;
wire cfg_rd_wr_done_n;
wire cfg_interrupt_rdy_n;
wire cfg_turnoff_ok_w;
wire trn_recrc_err_n;
wire cfg_err_cpl_rdy_n;
wire trn_tcfg_req_n;
// Inversion logic
assign cfg_rd_wr_done = !cfg_rd_wr_done_n ;
wire [3:0] cfg_byte_en_n = ~cfg_byte_en ;
wire cfg_wr_en_n = !cfg_wr_en ;
wire cfg_rd_en_n = !cfg_rd_en ;
wire cfg_trn_pending_n = !cfg_trn_pending ;
wire cfg_turnoff_ok_n = !cfg_turnoff_ok_w ;
wire cfg_pm_wake_n = !cfg_pm_wake ;
wire cfg_interrupt_n = !cfg_interrupt ;
assign cfg_interrupt_rdy = !cfg_interrupt_rdy_n ;
wire cfg_interrupt_assert_n = !cfg_interrupt_assert ;
wire cfg_err_ecrc_n = !cfg_err_ecrc ;
wire cfg_err_ur_n = !cfg_err_ur ;
wire cfg_err_cpl_timeout_n = !cfg_err_cpl_timeout ;
wire cfg_err_cpl_unexpect_n = !cfg_err_cpl_unexpect ;
wire cfg_err_cpl_abort_n = !cfg_err_cpl_abort ;
wire cfg_err_posted_n = !cfg_err_posted ;
wire cfg_err_cor_n = !cfg_err_cor ;
assign cfg_err_cpl_rdy = !cfg_err_cpl_rdy_n ;
wire cfg_err_locked_n = !cfg_err_locked ;
wire trn_recrc_err = !trn_recrc_err_n;
assign tx_err_drop = !trn_terr_drop_n;
assign tx_cfg_req = !trn_tcfg_req_n;
// assigns to outputs
assign cfg_to_turnoff = cfg_msg_received_pme_to;
assign cfg_status = {16'b0};
assign cfg_command = {5'b0,
cfg_cmd_intdis,
1'b0,
cfg_cmd_serr_en,
5'b0,
cfg_cmd_bme,
cfg_cmd_mem_en,
cfg_cmd_io_en};
assign cfg_dstatus = {10'h0,
cfg_trn_pending,
1'b0,
cfg_dev_status_ur_detected,
cfg_dev_status_fatal_err_detected,
cfg_dev_status_nonfatal_err_detected,
cfg_dev_status_corr_err_detected};
assign cfg_dcommand = {1'b0,
cfg_dev_control_max_read_req,
cfg_dev_control_nosnoop_en,
cfg_dev_control_aux_power_en,
cfg_dev_control_phantom_en,
cfg_dev_control_ext_tag_en,
cfg_dev_control_maxpayload,
cfg_dev_control_enable_relaxed_order,
cfg_dev_control_ur_err_reporting_en,
cfg_dev_control_fatal_err_reporting_en,
cfg_dev_control_non_fatal_reporting_en,
cfg_dev_control_corr_err_reporting_en };
assign cfg_lstatus = {cfg_link_status_autobandwidth_status,
cfg_link_status_bandwidth_status,
cfg_link_status_dll_active,
(LINK_STATUS_SLOT_CLOCK_CONFIG == "TRUE") ? 1'b1 : 1'b0,
cfg_link_status_link_training,
1'b0,
{2'b00, cfg_link_status_negotiated_link_width},
{2'b00, cfg_link_status_current_speed} };
assign cfg_lcommand = {4'b0,
cfg_link_control_auto_bandwidth_int_en,
cfg_link_control_bandwidth_int_en,
cfg_link_control_hw_auto_width_dis,
cfg_link_control_clock_pm_en,
cfg_link_control_extended_sync,
cfg_link_control_common_clock,
cfg_link_control_retrain_link,
cfg_link_control_linkdisable,
cfg_link_control_rcb,
1'b0,
cfg_link_control_aspm_control };
assign cfg_bus_number = cfg_bus_number_d;
assign cfg_device_number = cfg_device_number_d;
assign cfg_function_number = cfg_function_number_d;
assign cfg_dcommand2 = {11'b0,
cfg_dev_control2_cpltimeout_dis,
cfg_dev_control2_cpltimeout_val};
// Capture Bus/Device/Function number
always @(posedge user_clk_out) begin
if (!user_lnk_up) cfg_bus_number_d <= 8'b0;
else if (~cfg_msg_received) cfg_bus_number_d <= cfg_msg_data[15:8];
end
always @(posedge user_clk_out) begin
if (!user_lnk_up) cfg_device_number_d <= 5'b0;
else if (~cfg_msg_received) cfg_device_number_d <= cfg_msg_data[7:3];
end
always @(posedge user_clk_out) begin
if (!user_lnk_up) cfg_function_number_d <= 3'b0;
else if (~cfg_msg_received) cfg_function_number_d <= cfg_msg_data[2:0];
end
// Generate user_lnk_up
FDCP #(
.INIT(1'b0)
) trn_lnk_up_n_i (
.Q (user_lnk_up),
.D (!trn_lnk_up_n_int1),
.C (user_clk_out),
.CLR (1'b0),
.PRE (1'b0)
);
FDCP #(
.INIT(1'b1)
) trn_lnk_up_n_int_i (
.Q (trn_lnk_up_n_int1),
.D (trn_lnk_up_n_int),
.C (user_clk_out),
.CLR (1'b0),
.PRE (1'b0)
);
// Generate user_reset_out
FDCP #(
.INIT(1'b1)
) trn_reset_n_i (
.Q (user_reset_out),
.D (!(trn_reset_n_int1 & ~phy_rdy_n)),
.C (user_clk_out),
.CLR (~sys_reset_n_d),
.PRE (1'b0)
);
FDCP #(
.INIT(1'b0)
) trn_reset_n_int_i (
.Q (trn_reset_n_int1 ),
.D (trn_reset_n_int & ~phy_rdy_n),
.C (user_clk_out),
.CLR (~sys_reset_n_d),
.PRE (1'b0)
);
// AXI Basic Bridge
// Converts between TRN and AXI
axi_basic_top #(
.C_DATA_WIDTH (64), // RX/TX interface data width
.C_FAMILY ("V6"), // Targeted FPGA family
.C_ROOT_PORT ("FALSE"), // PCIe block is in root port mode
.C_PM_PRIORITY ("FALSE") // Disable TX packet boundary thrtl
) axi_basic_top (
//---------------------------------------------//
// User Design I/O //
//---------------------------------------------//
// AXI TX
//-----------
.s_axis_tx_tdata (s_axis_tx_tdata), // input
.s_axis_tx_tvalid (s_axis_tx_tvalid), // input
.s_axis_tx_tready (s_axis_tx_tready), // output
.s_axis_tx_tkeep (s_axis_tx_tkeep), // input
.s_axis_tx_tlast (s_axis_tx_tlast), // input
.s_axis_tx_tuser (s_axis_tx_tuser), // input
// AXI RX
//-----------
.m_axis_rx_tdata (m_axis_rx_tdata), // output
.m_axis_rx_tvalid (m_axis_rx_tvalid), // output
.m_axis_rx_tready (m_axis_rx_tready), // input
.m_axis_rx_tkeep (m_axis_rx_tkeep), // output
.m_axis_rx_tlast (m_axis_rx_tlast), // output
.m_axis_rx_tuser (m_axis_rx_tuser), // output
// User Misc.
//-----------
.user_turnoff_ok (cfg_turnoff_ok), // input
.user_tcfg_gnt (tx_cfg_gnt), // input
//---------------------------------------------//
// PCIe Block I/O //
//---------------------------------------------//
// TRN TX
//-----------
.trn_td (trn_td), // output
.trn_tsof (trn_tsof), // output
.trn_teof (trn_teof), // output
.trn_tsrc_rdy (trn_tsrc_rdy), // output
.trn_tdst_rdy (!trn_tdst_rdy_n), // input
.trn_tsrc_dsc (trn_tsrc_dsc), // output
.trn_trem (trn_trem), // output
.trn_terrfwd (trn_terrfwd), // output
.trn_tstr (trn_tstr), // output
.trn_tbuf_av (tx_buf_av), // input
.trn_tecrc_gen (trn_tecrc_gen), // output
// TRN RX
//-----------
.trn_rd (trn_rd), // input
.trn_rsof (!trn_rsof_n), // input
.trn_reof (!trn_reof_n), // input
.trn_rsrc_rdy (!trn_rsrc_rdy_n), // input
.trn_rdst_rdy (trn_rdst_rdy), // output
.trn_rsrc_dsc (!trn_rsrc_dsc_n), // input
.trn_rrem (~trn_rrem_n), // input
.trn_rerrfwd (!trn_rerrfwd_n), // input
.trn_rbar_hit (~trn_rbar_hit_n), // input
.trn_recrc_err (trn_recrc_err), // input
// TRN Misc.
//-----------
.trn_tcfg_req (tx_cfg_req), // input
.trn_tcfg_gnt (trn_tcfg_gnt), // output
.trn_lnk_up (user_lnk_up), // input
// Artix/Kintex/Virtex PM
//-----------
.cfg_pcie_link_state (cfg_pcie_link_state), // input
// Virtex6 PM
//-----------
.cfg_pm_send_pme_to (1'b0), // input NOT USED FOR EP
.cfg_pmcsr_powerstate (cfg_pmcsr_powerstate), // input
.trn_rdllp_data (trn_rdllp_data), // input
.trn_rdllp_src_rdy (!trn_rdllp_src_rdy_n), // input
// Power Mgmt for S6/V6
//-----------
.cfg_to_turnoff (cfg_to_turnoff), // input
.cfg_turnoff_ok (cfg_turnoff_ok_w), // output
// System
//-----------
.user_clk (user_clk_out), // input
.user_rst (user_reset_out), // input
.np_counter () // output
);
//-------------------------------------------------------
// PCI Express Reset Delay Module
//-------------------------------------------------------
pcie_reset_delay_v6 #(
.PL_FAST_TRAIN ( PL_FAST_TRAIN ),
.REF_CLK_FREQ ( REF_CLK_FREQ )
)
pcie_reset_delay_i (
.ref_clk ( TxOutClk_bufg ),
.sys_reset_n ( !sys_reset ),
.delayed_sys_reset_n ( sys_reset_n_d )
);
//-------------------------------------------------------
// PCI Express Clocking Module
//-------------------------------------------------------
pcie_clocking_v6 #(
.CAP_LINK_WIDTH(LINK_CAP_MAX_LINK_WIDTH),
.CAP_LINK_SPEED(LINK_CAP_MAX_LINK_SPEED),
.REF_CLK_FREQ(REF_CLK_FREQ),
.USER_CLK_FREQ(USER_CLK_FREQ)
)
pcie_clocking_i (
.sys_clk ( TxOutClk ),
.gt_pll_lock ( gt_pll_lock ),
.sel_lnk_rate ( pl_sel_link_rate ),
.sel_lnk_width ( pl_sel_link_width ),
.sys_clk_bufg ( TxOutClk_bufg ),
.pipe_clk ( pipe_clk ),
.user_clk ( user_clk_out ),
.block_clk ( block_clk ),
.drp_clk ( drp_clk ),
.clock_locked ( clock_locked )
);
//-------------------------------------------------------
// Virtex6 PCI Express Block Module
//-------------------------------------------------------
pcie_2_0_v6 #(
.REF_CLK_FREQ ( REF_CLK_FREQ ),
.PIPE_PIPELINE_STAGES ( PIPE_PIPELINE_STAGES ),
.AER_BASE_PTR ( AER_BASE_PTR ),
.AER_CAP_ECRC_CHECK_CAPABLE ( AER_CAP_ECRC_CHECK_CAPABLE ),
.AER_CAP_ECRC_GEN_CAPABLE ( AER_CAP_ECRC_GEN_CAPABLE ),
.AER_CAP_ID ( AER_CAP_ID ),
.AER_CAP_INT_MSG_NUM_MSI ( AER_CAP_INT_MSG_NUM_MSI ),
.AER_CAP_INT_MSG_NUM_MSIX ( AER_CAP_INT_MSG_NUM_MSIX ),
.AER_CAP_NEXTPTR ( AER_CAP_NEXTPTR ),
.AER_CAP_ON ( AER_CAP_ON ),
.AER_CAP_PERMIT_ROOTERR_UPDATE ( AER_CAP_PERMIT_ROOTERR_UPDATE ),
.AER_CAP_VERSION ( AER_CAP_VERSION ),
.ALLOW_X8_GEN2 ( ALLOW_X8_GEN2 ),
.BAR0 ( BAR0 ),
.BAR1 ( BAR1 ),
.BAR2 ( BAR2 ),
.BAR3 ( BAR3 ),
.BAR4 ( BAR4 ),
.BAR5 ( BAR5 ),
.CAPABILITIES_PTR ( CAPABILITIES_PTR ),
.CARDBUS_CIS_POINTER ( CARDBUS_CIS_POINTER ),
.CLASS_CODE ( CLASS_CODE ),
.CMD_INTX_IMPLEMENTED ( CMD_INTX_IMPLEMENTED ),
.CPL_TIMEOUT_DISABLE_SUPPORTED ( CPL_TIMEOUT_DISABLE_SUPPORTED ),
.CPL_TIMEOUT_RANGES_SUPPORTED ( CPL_TIMEOUT_RANGES_SUPPORTED ),
.CRM_MODULE_RSTS ( CRM_MODULE_RSTS ),
.DEV_CAP_ENABLE_SLOT_PWR_LIMIT_SCALE ( DEV_CAP_ENABLE_SLOT_PWR_LIMIT_SCALE ),
.DEV_CAP_ENABLE_SLOT_PWR_LIMIT_VALUE ( DEV_CAP_ENABLE_SLOT_PWR_LIMIT_VALUE ),
.DEV_CAP_ENDPOINT_L0S_LATENCY ( DEV_CAP_ENDPOINT_L0S_LATENCY ),
.DEV_CAP_ENDPOINT_L1_LATENCY ( DEV_CAP_ENDPOINT_L1_LATENCY ),
.DEV_CAP_EXT_TAG_SUPPORTED ( DEV_CAP_EXT_TAG_SUPPORTED ),
.DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE ( DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE ),
.DEV_CAP_MAX_PAYLOAD_SUPPORTED ( DEV_CAP_MAX_PAYLOAD_SUPPORTED ),
.DEV_CAP_PHANTOM_FUNCTIONS_SUPPORT ( DEV_CAP_PHANTOM_FUNCTIONS_SUPPORT ),
.DEV_CAP_ROLE_BASED_ERROR ( DEV_CAP_ROLE_BASED_ERROR ),
.DEV_CAP_RSVD_14_12 ( DEV_CAP_RSVD_14_12 ),
.DEV_CAP_RSVD_17_16 ( DEV_CAP_RSVD_17_16 ),
.DEV_CAP_RSVD_31_29 ( DEV_CAP_RSVD_31_29 ),
.DEV_CONTROL_AUX_POWER_SUPPORTED ( DEV_CONTROL_AUX_POWER_SUPPORTED ),
.DEVICE_ID ( DEVICE_ID ),
.DISABLE_ASPM_L1_TIMER ( DISABLE_ASPM_L1_TIMER ),
.DISABLE_BAR_FILTERING ( DISABLE_BAR_FILTERING ),
.DISABLE_ID_CHECK ( DISABLE_ID_CHECK ),
.DISABLE_LANE_REVERSAL ( DISABLE_LANE_REVERSAL ),
.DISABLE_RX_TC_FILTER ( DISABLE_RX_TC_FILTER ),
.DISABLE_SCRAMBLING ( DISABLE_SCRAMBLING ),
.DNSTREAM_LINK_NUM ( DNSTREAM_LINK_NUM ),
.DSN_BASE_PTR ( DSN_BASE_PTR ),
.DSN_CAP_ID ( DSN_CAP_ID ),
.DSN_CAP_NEXTPTR ( DSN_CAP_NEXTPTR ),
.DSN_CAP_ON ( DSN_CAP_ON ),
.DSN_CAP_VERSION ( DSN_CAP_VERSION ),
.ENABLE_MSG_ROUTE ( ENABLE_MSG_ROUTE ),
.ENABLE_RX_TD_ECRC_TRIM ( ENABLE_RX_TD_ECRC_TRIM ),
.ENTER_RVRY_EI_L0 ( ENTER_RVRY_EI_L0 ),
.EXPANSION_ROM ( EXPANSION_ROM ),
.EXT_CFG_CAP_PTR ( EXT_CFG_CAP_PTR ),
.EXT_CFG_XP_CAP_PTR ( EXT_CFG_XP_CAP_PTR ),
.HEADER_TYPE ( HEADER_TYPE ),
.INFER_EI ( INFER_EI ),
.INTERRUPT_PIN ( INTERRUPT_PIN ),
.IS_SWITCH ( IS_SWITCH ),
.LAST_CONFIG_DWORD ( LAST_CONFIG_DWORD ),
.LINK_CAP_ASPM_SUPPORT ( LINK_CAP_ASPM_SUPPORT ),
.LINK_CAP_CLOCK_POWER_MANAGEMENT ( LINK_CAP_CLOCK_POWER_MANAGEMENT ),
.LINK_CAP_DLL_LINK_ACTIVE_REPORTING_CAP ( LINK_CAP_DLL_LINK_ACTIVE_REPORTING_CAP ),
.LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP ( LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP ),
.LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1 ( LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1 ),
.LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2 ( LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2 ),
.LINK_CAP_L0S_EXIT_LATENCY_GEN1 ( LINK_CAP_L0S_EXIT_LATENCY_GEN1 ),
.LINK_CAP_L0S_EXIT_LATENCY_GEN2 ( LINK_CAP_L0S_EXIT_LATENCY_GEN2 ),
.LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1 ( LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1 ),
.LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2 ( LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2 ),
.LINK_CAP_L1_EXIT_LATENCY_GEN1 ( LINK_CAP_L1_EXIT_LATENCY_GEN1 ),
.LINK_CAP_L1_EXIT_LATENCY_GEN2 ( LINK_CAP_L1_EXIT_LATENCY_GEN2 ),
.LINK_CAP_MAX_LINK_SPEED ( LINK_CAP_MAX_LINK_SPEED ),
.LINK_CAP_MAX_LINK_WIDTH ( LINK_CAP_MAX_LINK_WIDTH ),
.LINK_CAP_RSVD_23_22 ( LINK_CAP_RSVD_23_22 ),
.LINK_CAP_SURPRISE_DOWN_ERROR_CAPABLE ( LINK_CAP_SURPRISE_DOWN_ERROR_CAPABLE ),
.LINK_CONTROL_RCB ( LINK_CONTROL_RCB ),
.LINK_CTRL2_DEEMPHASIS ( LINK_CTRL2_DEEMPHASIS ),
.LINK_CTRL2_HW_AUTONOMOUS_SPEED_DISABLE ( LINK_CTRL2_HW_AUTONOMOUS_SPEED_DISABLE ),
.LINK_CTRL2_TARGET_LINK_SPEED ( LINK_CTRL2_TARGET_LINK_SPEED ),
.LINK_STATUS_SLOT_CLOCK_CONFIG ( LINK_STATUS_SLOT_CLOCK_CONFIG ),
.LL_ACK_TIMEOUT ( LL_ACK_TIMEOUT ),
.LL_ACK_TIMEOUT_EN ( LL_ACK_TIMEOUT_EN ),
.LL_ACK_TIMEOUT_FUNC ( LL_ACK_TIMEOUT_FUNC ),
.LL_REPLAY_TIMEOUT ( LL_REPLAY_TIMEOUT ),
.LL_REPLAY_TIMEOUT_EN ( LL_REPLAY_TIMEOUT_EN ),
.LL_REPLAY_TIMEOUT_FUNC ( LL_REPLAY_TIMEOUT_FUNC ),
.LTSSM_MAX_LINK_WIDTH ( LTSSM_MAX_LINK_WIDTH ),
.MSI_BASE_PTR ( MSI_BASE_PTR ),
.MSI_CAP_ID ( MSI_CAP_ID ),
.MSI_CAP_MULTIMSGCAP ( MSI_CAP_MULTIMSGCAP ),
.MSI_CAP_MULTIMSG_EXTENSION ( MSI_CAP_MULTIMSG_EXTENSION ),
.MSI_CAP_NEXTPTR ( MSI_CAP_NEXTPTR ),
.MSI_CAP_ON ( MSI_CAP_ON ),
.MSI_CAP_PER_VECTOR_MASKING_CAPABLE ( MSI_CAP_PER_VECTOR_MASKING_CAPABLE ),
.MSI_CAP_64_BIT_ADDR_CAPABLE ( MSI_CAP_64_BIT_ADDR_CAPABLE ),
.MSIX_BASE_PTR ( MSIX_BASE_PTR ),
.MSIX_CAP_ID ( MSIX_CAP_ID ),
.MSIX_CAP_NEXTPTR ( MSIX_CAP_NEXTPTR ),
.MSIX_CAP_ON ( MSIX_CAP_ON ),
.MSIX_CAP_PBA_BIR ( MSIX_CAP_PBA_BIR ),
.MSIX_CAP_PBA_OFFSET ( MSIX_CAP_PBA_OFFSET ),
.MSIX_CAP_TABLE_BIR ( MSIX_CAP_TABLE_BIR ),
.MSIX_CAP_TABLE_OFFSET ( MSIX_CAP_TABLE_OFFSET ),
.MSIX_CAP_TABLE_SIZE ( MSIX_CAP_TABLE_SIZE ),
.N_FTS_COMCLK_GEN1 ( N_FTS_COMCLK_GEN1 ),
.N_FTS_COMCLK_GEN2 ( N_FTS_COMCLK_GEN2 ),
.N_FTS_GEN1 ( N_FTS_GEN1 ),
.N_FTS_GEN2 ( N_FTS_GEN2 ),
.PCIE_BASE_PTR ( PCIE_BASE_PTR ),
.PCIE_CAP_CAPABILITY_ID ( PCIE_CAP_CAPABILITY_ID ),
.PCIE_CAP_CAPABILITY_VERSION ( PCIE_CAP_CAPABILITY_VERSION ),
.PCIE_CAP_DEVICE_PORT_TYPE ( PCIE_CAP_DEVICE_PORT_TYPE ),
.PCIE_CAP_INT_MSG_NUM ( PCIE_CAP_INT_MSG_NUM ),
.PCIE_CAP_NEXTPTR ( PCIE_CAP_NEXTPTR ),
.PCIE_CAP_ON ( PCIE_CAP_ON ),
.PCIE_CAP_RSVD_15_14 ( PCIE_CAP_RSVD_15_14 ),
.PCIE_CAP_SLOT_IMPLEMENTED ( PCIE_CAP_SLOT_IMPLEMENTED ),
.PCIE_REVISION ( PCIE_REVISION ),
.PGL0_LANE ( PGL0_LANE ),
.PGL1_LANE ( PGL1_LANE ),
.PGL2_LANE ( PGL2_LANE ),
.PGL3_LANE ( PGL3_LANE ),
.PGL4_LANE ( PGL4_LANE ),
.PGL5_LANE ( PGL5_LANE ),
.PGL6_LANE ( PGL6_LANE ),
.PGL7_LANE ( PGL7_LANE ),
.PL_AUTO_CONFIG ( PL_AUTO_CONFIG ),
.PL_FAST_TRAIN ( PL_FAST_TRAIN ),
.PM_BASE_PTR ( PM_BASE_PTR ),
.PM_CAP_AUXCURRENT ( PM_CAP_AUXCURRENT ),
.PM_CAP_DSI ( PM_CAP_DSI ),
.PM_CAP_D1SUPPORT ( PM_CAP_D1SUPPORT ),
.PM_CAP_D2SUPPORT ( PM_CAP_D2SUPPORT ),
.PM_CAP_ID ( PM_CAP_ID ),
.PM_CAP_NEXTPTR ( PM_CAP_NEXTPTR ),
.PM_CAP_ON ( PM_CAP_ON ),
.PM_CAP_PME_CLOCK ( PM_CAP_PME_CLOCK ),
.PM_CAP_PMESUPPORT ( PM_CAP_PMESUPPORT ),
.PM_CAP_RSVD_04 ( PM_CAP_RSVD_04 ),
.PM_CAP_VERSION ( PM_CAP_VERSION ),
.PM_CSR_BPCCEN ( PM_CSR_BPCCEN ),
.PM_CSR_B2B3 ( PM_CSR_B2B3 ),
.PM_CSR_NOSOFTRST ( PM_CSR_NOSOFTRST ),
.PM_DATA_SCALE0 ( PM_DATA_SCALE0 ),
.PM_DATA_SCALE1 ( PM_DATA_SCALE1 ),
.PM_DATA_SCALE2 ( PM_DATA_SCALE2 ),
.PM_DATA_SCALE3 ( PM_DATA_SCALE3 ),
.PM_DATA_SCALE4 ( PM_DATA_SCALE4 ),
.PM_DATA_SCALE5 ( PM_DATA_SCALE5 ),
.PM_DATA_SCALE6 ( PM_DATA_SCALE6 ),
.PM_DATA_SCALE7 ( PM_DATA_SCALE7 ),
.PM_DATA0 ( PM_DATA0 ),
.PM_DATA1 ( PM_DATA1 ),
.PM_DATA2 ( PM_DATA2 ),
.PM_DATA3 ( PM_DATA3 ),
.PM_DATA4 ( PM_DATA4 ),
.PM_DATA5 ( PM_DATA5 ),
.PM_DATA6 ( PM_DATA6 ),
.PM_DATA7 ( PM_DATA7 ),
.RECRC_CHK ( RECRC_CHK ),
.RECRC_CHK_TRIM ( RECRC_CHK_TRIM ),
.REVISION_ID ( REVISION_ID ),
.ROOT_CAP_CRS_SW_VISIBILITY ( ROOT_CAP_CRS_SW_VISIBILITY ),
.SELECT_DLL_IF ( SELECT_DLL_IF ),
.SLOT_CAP_ATT_BUTTON_PRESENT ( SLOT_CAP_ATT_BUTTON_PRESENT ),
.SLOT_CAP_ATT_INDICATOR_PRESENT ( SLOT_CAP_ATT_INDICATOR_PRESENT ),
.SLOT_CAP_ELEC_INTERLOCK_PRESENT ( SLOT_CAP_ELEC_INTERLOCK_PRESENT ),
.SLOT_CAP_HOTPLUG_CAPABLE ( SLOT_CAP_HOTPLUG_CAPABLE ),
.SLOT_CAP_HOTPLUG_SURPRISE ( SLOT_CAP_HOTPLUG_SURPRISE ),
.SLOT_CAP_MRL_SENSOR_PRESENT ( SLOT_CAP_MRL_SENSOR_PRESENT ),
.SLOT_CAP_NO_CMD_COMPLETED_SUPPORT ( SLOT_CAP_NO_CMD_COMPLETED_SUPPORT ),
.SLOT_CAP_PHYSICAL_SLOT_NUM ( SLOT_CAP_PHYSICAL_SLOT_NUM ),
.SLOT_CAP_POWER_CONTROLLER_PRESENT ( SLOT_CAP_POWER_CONTROLLER_PRESENT ),
.SLOT_CAP_POWER_INDICATOR_PRESENT ( SLOT_CAP_POWER_INDICATOR_PRESENT ),
.SLOT_CAP_SLOT_POWER_LIMIT_SCALE ( SLOT_CAP_SLOT_POWER_LIMIT_SCALE ),
.SLOT_CAP_SLOT_POWER_LIMIT_VALUE ( SLOT_CAP_SLOT_POWER_LIMIT_VALUE ),
.SPARE_BIT0 ( SPARE_BIT0 ),
.SPARE_BIT1 ( SPARE_BIT1 ),
.SPARE_BIT2 ( SPARE_BIT2 ),
.SPARE_BIT3 ( SPARE_BIT3 ),
.SPARE_BIT4 ( SPARE_BIT4 ),
.SPARE_BIT5 ( SPARE_BIT5 ),
.SPARE_BIT6 ( SPARE_BIT6 ),
.SPARE_BIT7 ( SPARE_BIT7 ),
.SPARE_BIT8 ( SPARE_BIT8 ),
.SPARE_BYTE0 ( SPARE_BYTE0 ),
.SPARE_BYTE1 ( SPARE_BYTE1 ),
.SPARE_BYTE2 ( SPARE_BYTE2 ),
.SPARE_BYTE3 ( SPARE_BYTE3 ),
.SPARE_WORD0 ( SPARE_WORD0 ),
.SPARE_WORD1 ( SPARE_WORD1 ),
.SPARE_WORD2 ( SPARE_WORD2 ),
.SPARE_WORD3 ( SPARE_WORD3 ),
.SUBSYSTEM_ID ( SUBSYSTEM_ID ),
.SUBSYSTEM_VENDOR_ID ( SUBSYSTEM_VENDOR_ID ),
.TL_RBYPASS ( TL_RBYPASS ),
.TL_RX_RAM_RADDR_LATENCY ( TL_RX_RAM_RADDR_LATENCY ),
.TL_RX_RAM_RDATA_LATENCY ( TL_RX_RAM_RDATA_LATENCY ),
.TL_RX_RAM_WRITE_LATENCY ( TL_RX_RAM_WRITE_LATENCY ),
.TL_TFC_DISABLE ( TL_TFC_DISABLE ),
.TL_TX_CHECKS_DISABLE ( TL_TX_CHECKS_DISABLE ),
.TL_TX_RAM_RADDR_LATENCY ( TL_TX_RAM_RADDR_LATENCY ),
.TL_TX_RAM_RDATA_LATENCY ( TL_TX_RAM_RDATA_LATENCY ),
.TL_TX_RAM_WRITE_LATENCY ( TL_TX_RAM_WRITE_LATENCY ),
.UPCONFIG_CAPABLE ( UPCONFIG_CAPABLE ),
.UPSTREAM_FACING ( UPSTREAM_FACING ),
.EXIT_LOOPBACK_ON_EI ( EXIT_LOOPBACK_ON_EI ),
.UR_INV_REQ ( UR_INV_REQ ),
.USER_CLK_FREQ ( USER_CLK_FREQ ),
.VC_BASE_PTR ( VC_BASE_PTR ),
.VC_CAP_ID ( VC_CAP_ID ),
.VC_CAP_NEXTPTR ( VC_CAP_NEXTPTR ),
.VC_CAP_ON ( VC_CAP_ON ),
.VC_CAP_REJECT_SNOOP_TRANSACTIONS ( VC_CAP_REJECT_SNOOP_TRANSACTIONS ),
.VC_CAP_VERSION ( VC_CAP_VERSION ),
.VC0_CPL_INFINITE ( VC0_CPL_INFINITE ),
.VC0_RX_RAM_LIMIT ( VC0_RX_RAM_LIMIT ),
.VC0_TOTAL_CREDITS_CD ( VC0_TOTAL_CREDITS_CD ),
.VC0_TOTAL_CREDITS_CH ( VC0_TOTAL_CREDITS_CH ),
.VC0_TOTAL_CREDITS_NPH ( VC0_TOTAL_CREDITS_NPH ),
.VC0_TOTAL_CREDITS_PD ( VC0_TOTAL_CREDITS_PD ),
.VC0_TOTAL_CREDITS_PH ( VC0_TOTAL_CREDITS_PH ),
.VC0_TX_LASTPACKET ( VC0_TX_LASTPACKET ),
.VENDOR_ID ( VENDOR_ID ),
.VSEC_BASE_PTR ( VSEC_BASE_PTR ),
.VSEC_CAP_HDR_ID ( VSEC_CAP_HDR_ID ),
.VSEC_CAP_HDR_LENGTH ( VSEC_CAP_HDR_LENGTH ),
.VSEC_CAP_HDR_REVISION ( VSEC_CAP_HDR_REVISION ),
.VSEC_CAP_ID ( VSEC_CAP_ID ),
.VSEC_CAP_IS_LINK_VISIBLE ( VSEC_CAP_IS_LINK_VISIBLE ),
.VSEC_CAP_NEXTPTR ( VSEC_CAP_NEXTPTR ),
.VSEC_CAP_ON ( VSEC_CAP_ON ),
.VSEC_CAP_VERSION ( VSEC_CAP_VERSION )
)
pcie_2_0_i (
.PCIEXPRXN( pci_exp_rxn ),
.PCIEXPRXP( pci_exp_rxp ),
.PCIEXPTXN( pci_exp_txn ),
.PCIEXPTXP( pci_exp_txp ),
.SYSCLK( sys_clk ),
.TRNLNKUPN( trn_lnk_up_n_int ),
.FUNDRSTN (sys_reset_n_d),
.PHYRDYN( phy_rdy_n ),
.LNKCLKEN ( ),
.USERRSTN( trn_reset_n_int ),
.RECEIVEDFUNCLVLRSTN( rx_func_level_reset_n ),
.SYSRSTN( ~phy_rdy_n ),
.PLRSTN( 1'b1 ),
.DLRSTN( 1'b1 ),
.TLRSTN( 1'b1 ),
.FUNCLVLRSTN( 1'b1 ),
.CMRSTN( 1'b1 ),
.CMSTICKYRSTN( 1'b1 ),
.TRNRBARHITN( trn_rbar_hit_n ),
.TRNRD( trn_rd ),
.TRNRECRCERRN( trn_recrc_err_n ),
.TRNREOFN( trn_reof_n ),
.TRNRERRFWDN( trn_rerrfwd_n ),
.TRNRREMN( trn_rrem_n ),
.TRNRSOFN( trn_rsof_n ),
.TRNRSRCDSCN( trn_rsrc_dsc_n ),
.TRNRSRCRDYN( trn_rsrc_rdy_n ),
.TRNRDSTRDYN( !trn_rdst_rdy ),
.TRNRNPOKN( !rx_np_ok ),
.TRNTBUFAV( tx_buf_av ),
.TRNTCFGREQN( trn_tcfg_req_n ),
.TRNTDLLPDSTRDYN( ),
.TRNTDSTRDYN( trn_tdst_rdy_n ),
.TRNTERRDROPN( trn_terr_drop_n ),
.TRNTCFGGNTN( !trn_tcfg_gnt ),
.TRNTD( trn_td ),
.TRNTDLLPDATA( 32'b0 ),
.TRNTDLLPSRCRDYN( 1'b1 ),
.TRNTECRCGENN( 1'b1 ),
.TRNTEOFN( !trn_teof ),
.TRNTERRFWDN( !trn_terrfwd ),
.TRNTREMN( ~trn_trem ),
.TRNTSOFN( !trn_tsof ),
.TRNTSRCDSCN( !trn_tsrc_dsc ),
.TRNTSRCRDYN( !trn_tsrc_rdy ),
.TRNTSTRN( !trn_tstr ),
.TRNFCCPLD( fc_cpld ),
.TRNFCCPLH( fc_cplh ),
.TRNFCNPD( fc_npd ),
.TRNFCNPH( fc_nph ),
.TRNFCPD( fc_pd ),
.TRNFCPH( fc_ph ),
.TRNFCSEL( fc_sel ),
.CFGAERECRCCHECKEN(),
.CFGAERECRCGENEN(),
.CFGCOMMANDBUSMASTERENABLE( cfg_cmd_bme ),
.CFGCOMMANDINTERRUPTDISABLE( cfg_cmd_intdis ),
.CFGCOMMANDIOENABLE( cfg_cmd_io_en ),
.CFGCOMMANDMEMENABLE( cfg_cmd_mem_en ),
.CFGCOMMANDSERREN( cfg_cmd_serr_en ),
.CFGDEVCONTROLAUXPOWEREN( cfg_dev_control_aux_power_en ),
.CFGDEVCONTROLCORRERRREPORTINGEN( cfg_dev_control_corr_err_reporting_en ),
.CFGDEVCONTROLENABLERO( cfg_dev_control_enable_relaxed_order ),
.CFGDEVCONTROLEXTTAGEN( cfg_dev_control_ext_tag_en ),
.CFGDEVCONTROLFATALERRREPORTINGEN( cfg_dev_control_fatal_err_reporting_en ),
.CFGDEVCONTROLMAXPAYLOAD( cfg_dev_control_maxpayload ),
.CFGDEVCONTROLMAXREADREQ( cfg_dev_control_max_read_req ),
.CFGDEVCONTROLNONFATALREPORTINGEN( cfg_dev_control_non_fatal_reporting_en ),
.CFGDEVCONTROLNOSNOOPEN( cfg_dev_control_nosnoop_en ),
.CFGDEVCONTROLPHANTOMEN( cfg_dev_control_phantom_en ),
.CFGDEVCONTROLURERRREPORTINGEN( cfg_dev_control_ur_err_reporting_en ),
.CFGDEVCONTROL2CPLTIMEOUTDIS( cfg_dev_control2_cpltimeout_dis ),
.CFGDEVCONTROL2CPLTIMEOUTVAL( cfg_dev_control2_cpltimeout_val ),
.CFGDEVSTATUSCORRERRDETECTED( cfg_dev_status_corr_err_detected ),
.CFGDEVSTATUSFATALERRDETECTED( cfg_dev_status_fatal_err_detected ),
.CFGDEVSTATUSNONFATALERRDETECTED( cfg_dev_status_nonfatal_err_detected ),
.CFGDEVSTATUSURDETECTED( cfg_dev_status_ur_detected ),
.CFGDO( cfg_do ),
.CFGERRAERHEADERLOGSETN(),
.CFGERRCPLRDYN( cfg_err_cpl_rdy_n ),
.CFGINTERRUPTDO( cfg_interrupt_do ),
.CFGINTERRUPTMMENABLE( cfg_interrupt_mmenable ),
.CFGINTERRUPTMSIENABLE( cfg_interrupt_msienable ),
.CFGINTERRUPTMSIXENABLE( cfg_interrupt_msixenable ),
.CFGINTERRUPTMSIXFM( cfg_interrupt_msixfm ),
.CFGINTERRUPTRDYN( cfg_interrupt_rdy_n ),
.CFGLINKCONTROLRCB( cfg_link_control_rcb ),
.CFGLINKCONTROLASPMCONTROL( cfg_link_control_aspm_control ),
.CFGLINKCONTROLAUTOBANDWIDTHINTEN( cfg_link_control_auto_bandwidth_int_en ),
.CFGLINKCONTROLBANDWIDTHINTEN( cfg_link_control_bandwidth_int_en ),
.CFGLINKCONTROLCLOCKPMEN( cfg_link_control_clock_pm_en ),
.CFGLINKCONTROLCOMMONCLOCK( cfg_link_control_common_clock ),
.CFGLINKCONTROLEXTENDEDSYNC( cfg_link_control_extended_sync ),
.CFGLINKCONTROLHWAUTOWIDTHDIS( cfg_link_control_hw_auto_width_dis ),
.CFGLINKCONTROLLINKDISABLE( cfg_link_control_linkdisable ),
.CFGLINKCONTROLRETRAINLINK( cfg_link_control_retrain_link ),
.CFGLINKSTATUSAUTOBANDWIDTHSTATUS( cfg_link_status_autobandwidth_status ),
.CFGLINKSTATUSBANDWITHSTATUS( cfg_link_status_bandwidth_status ),
.CFGLINKSTATUSCURRENTSPEED( cfg_link_status_current_speed ),
.CFGLINKSTATUSDLLACTIVE( cfg_link_status_dll_active ),
.CFGLINKSTATUSLINKTRAINING( cfg_link_status_link_training ),
.CFGLINKSTATUSNEGOTIATEDWIDTH( cfg_link_status_negotiated_link_width ),
.CFGMSGDATA( cfg_msg_data ),
.CFGMSGRECEIVED( cfg_msg_received ),
.CFGMSGRECEIVEDASSERTINTA(),
.CFGMSGRECEIVEDASSERTINTB(),
.CFGMSGRECEIVEDASSERTINTC(),
.CFGMSGRECEIVEDASSERTINTD(),
.CFGMSGRECEIVEDDEASSERTINTA(),
.CFGMSGRECEIVEDDEASSERTINTB(),
.CFGMSGRECEIVEDDEASSERTINTC(),
.CFGMSGRECEIVEDDEASSERTINTD(),
.CFGMSGRECEIVEDERRCOR(),
.CFGMSGRECEIVEDERRFATAL(),
.CFGMSGRECEIVEDERRNONFATAL(),
.CFGMSGRECEIVEDPMASNAK(),
.CFGMSGRECEIVEDPMETO( cfg_msg_received_pme_to ),
.CFGMSGRECEIVEDPMETOACK(),
.CFGMSGRECEIVEDPMPME(),
.CFGMSGRECEIVEDSETSLOTPOWERLIMIT(),
.CFGMSGRECEIVEDUNLOCK(),
.CFGPCIELINKSTATE( cfg_pcie_link_state ),
.CFGPMCSRPMEEN ( cfg_pmcsr_pme_en ),
.CFGPMCSRPMESTATUS ( cfg_pmcsr_pme_status ),
.CFGPMCSRPOWERSTATE ( cfg_pmcsr_powerstate ),
.CFGPMRCVASREQL1N(),
.CFGPMRCVENTERL1N(),
.CFGPMRCVENTERL23N(),
.CFGPMRCVREQACKN(),
.CFGRDWRDONEN( cfg_rd_wr_done_n ),
.CFGSLOTCONTROLELECTROMECHILCTLPULSE(),
.CFGTRANSACTION(),
.CFGTRANSACTIONADDR(),
.CFGTRANSACTIONTYPE(),
.CFGVCTCVCMAP(),
.CFGBYTEENN( cfg_byte_en_n ),
.CFGDI( cfg_di ),
.CFGDSBUSNUMBER( 8'b0 ),
.CFGDSDEVICENUMBER( 5'b0 ),
.CFGDSFUNCTIONNUMBER( 3'b0 ),
.CFGDSN( cfg_dsn ),
.CFGDWADDR( cfg_dwaddr ),
.CFGERRACSN( 1'b1 ),
.CFGERRAERHEADERLOG( 128'h0 ),
.CFGERRCORN( cfg_err_cor_n ),
.CFGERRCPLABORTN( cfg_err_cpl_abort_n ),
.CFGERRCPLTIMEOUTN( cfg_err_cpl_timeout_n ),
.CFGERRCPLUNEXPECTN( cfg_err_cpl_unexpect_n ),
.CFGERRECRCN( cfg_err_ecrc_n ),
.CFGERRLOCKEDN( cfg_err_locked_n ),
.CFGERRPOSTEDN( cfg_err_posted_n ),
.CFGERRTLPCPLHEADER( cfg_err_tlp_cpl_header ),
.CFGERRURN( cfg_err_ur_n ),
.CFGINTERRUPTASSERTN( cfg_interrupt_assert_n ),
.CFGINTERRUPTDI( cfg_interrupt_di ),
.CFGINTERRUPTN( cfg_interrupt_n ),
.CFGPMDIRECTASPML1N( 1'b1 ),
.CFGPMSENDPMACKN( 1'b1 ),
.CFGPMSENDPMETON( 1'b1 ),
.CFGPMSENDPMNAKN( 1'b1 ),
.CFGPMTURNOFFOKN( cfg_turnoff_ok_n ),
.CFGPMWAKEN( cfg_pm_wake_n ),
.CFGPORTNUMBER( 8'h0 ),
.CFGRDENN( cfg_rd_en_n ),
.CFGTRNPENDINGN( cfg_trn_pending_n ),
.CFGWRENN( cfg_wr_en_n ),
.CFGWRREADONLYN( 1'b1 ),
.CFGWRRW1CASRWN( 1'b1 ),
.PLINITIALLINKWIDTH( pl_initial_link_width ),
.PLLANEREVERSALMODE( pl_lane_reversal_mode ),
.PLLINKGEN2CAP( pl_link_gen2_capable ),
.PLLINKPARTNERGEN2SUPPORTED( pl_link_partner_gen2_supported ),
.PLLINKUPCFGCAP( pl_link_upcfg_capable ),
.PLLTSSMSTATE( pl_ltssm_state ),
.PLPHYLNKUPN( ), // Debug
.PLRECEIVEDHOTRST( pl_received_hot_rst ),
.PLRXPMSTATE(), // Debug
.PLSELLNKRATE( pl_sel_link_rate ),
.PLSELLNKWIDTH( pl_sel_link_width ),
.PLTXPMSTATE(), // Debug
.PLDIRECTEDLINKAUTON( pl_directed_link_auton ),
.PLDIRECTEDLINKCHANGE( pl_directed_link_change ),
.PLDIRECTEDLINKSPEED( pl_directed_link_speed ),
.PLDIRECTEDLINKWIDTH( pl_directed_link_width ),
.PLDOWNSTREAMDEEMPHSOURCE( 1'b1 ),
.PLUPSTREAMPREFERDEEMPH( pl_upstream_prefer_deemph ),
.PLTRANSMITHOTRST( 1'b0 ),
.DBGSCLRA(),
.DBGSCLRB(),
.DBGSCLRC(),
.DBGSCLRD(),
.DBGSCLRE(),
.DBGSCLRF(),
.DBGSCLRG(),
.DBGSCLRH(),
.DBGSCLRI(),
.DBGSCLRJ(),
.DBGSCLRK(),
.DBGVECA(),
.DBGVECB(),
.DBGVECC(),
.PLDBGVEC(),
.DBGMODE( 2'b0 ),
.DBGSUBMODE( 1'b0 ),
.PLDBGMODE( 3'b0 ),
.PCIEDRPDO(),
.PCIEDRPDRDY(),
.PCIEDRPCLK(1'b0),
.PCIEDRPDADDR(9'b0),
.PCIEDRPDEN(1'b0),
.PCIEDRPDI(16'b0),
.PCIEDRPDWE(1'b0),
.GTPLLLOCK( gt_pll_lock ),
.PIPECLK( pipe_clk ),
.USERCLK( user_clk_out ),
.DRPCLK(drp_clk),
.CLOCKLOCKED( clock_locked ),
.TxOutClk(TxOutClk),
.TRNRDLLPDATA(trn_rdllp_data),
.TRNRDLLPSRCRDYN(trn_rdllp_src_rdy_n)
);
endmodule
|
module sky130_fd_sc_ls__a2bb2o (
//# {{data|Data Signals}}
input A1_N,
input A2_N,
input B1 ,
input B2 ,
output X ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
|
module sky130_fd_sc_ms__sedfxtp (
Q ,
CLK ,
D ,
DE ,
SCD ,
SCE ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Q ;
input CLK ;
input D ;
input DE ;
input SCD ;
input SCE ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire buf_Q ;
wire mux_out;
wire de_d ;
// Delay Name Output Other arguments
sky130_fd_sc_ms__udp_mux_2to1 mux_2to10 (mux_out, de_d, SCD, SCE );
sky130_fd_sc_ms__udp_mux_2to1 mux_2to11 (de_d , buf_Q, D, DE );
sky130_fd_sc_ms__udp_dff$P_pp$PG$N `UNIT_DELAY dff0 (buf_Q , mux_out, CLK, , VPWR, VGND);
buf buf0 (Q , buf_Q );
endmodule
|
module sky130_fd_sc_hdll__o2bb2a_2 (
X ,
A1_N,
A2_N,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1_N;
input A2_N;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hdll__o2bb2a base (
.X(X),
.A1_N(A1_N),
.A2_N(A2_N),
.B1(B1),
.B2(B2),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
|
module sky130_fd_sc_hdll__o2bb2a_2 (
X ,
A1_N,
A2_N,
B1 ,
B2
);
output X ;
input A1_N;
input A2_N;
input B1 ;
input B2 ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hdll__o2bb2a base (
.X(X),
.A1_N(A1_N),
.A2_N(A2_N),
.B1(B1),
.B2(B2)
);
endmodule
|
module altera_tse_multi_mac_pcs_pma_gige_phyip
#(
parameter USE_SYNC_RESET = 0, // Use Synchronized Reset Inputs
parameter RESET_LEVEL = 1'b 1 , // Reset Active Level
parameter ENABLE_GMII_LOOPBACK = 1, // GMII_LOOPBACK_ENA : Enable GMII Loopback Logic
parameter ENABLE_HD_LOGIC = 1, // HD_LOGIC_ENA : Enable Half Duplex Logic
parameter ENABLE_SUP_ADDR = 1, // SUP_ADDR_ENA : Enable Supplemental Addresses
parameter ENA_HASH = 1, // ENA_HASH Enable Hash Table
parameter STAT_CNT_ENA = 1, // STAT_CNT_ENA Enable Statistic Counters
parameter MDIO_CLK_DIV = 40 , // Host Clock Division - MDC Generation
parameter CORE_VERSION = 16'h3, // ALTERA Core Version
parameter CUST_VERSION = 1 , // Customer Core Version
parameter REDUCED_INTERFACE_ENA = 0, // Enable the RGMII Interface
parameter ENABLE_MDIO = 1, // Enable the MDIO Interface
parameter ENABLE_MAGIC_DETECT = 1, // Enable magic packet detection
parameter ENABLE_PADDING = 1, // Enable padding operation.
parameter ENABLE_LGTH_CHECK = 1, // Enable frame length checking.
parameter GBIT_ONLY = 1, // Enable Gigabit only operation.
parameter MBIT_ONLY = 1, // Enable Megabit (10/100) only operation.
parameter REDUCED_CONTROL = 0, // Reduced control for MAC LITE
parameter CRC32DWIDTH = 4'b 1000, // input data width (informal, not for change)
parameter CRC32GENDELAY = 3'b 110, // when the data from the generator is valid
parameter CRC32CHECK16BIT = 1'b 0, // 1 compare two times 16 bit of the CRC (adds one pipeline step)
parameter CRC32S1L2_EXTERN = 1'b0, // false: merge enable
parameter ENABLE_SHIFT16 = 0, // Enable byte stuffing at packet header
parameter ENABLE_MAC_FLOW_CTRL = 1'b1, // Option to enable flow control
parameter ENABLE_MAC_TXADDR_SET = 1'b1, // Option to enable MAC address insertion onto 'to-be-transmitted' Ethernet frames on MAC TX data path
parameter ENABLE_MAC_RX_VLAN = 1'b1, // Option to enable VLAN tagged Ethernet frames on MAC RX data path
parameter ENABLE_MAC_TX_VLAN = 1'b1, // Option to enable VLAN tagged Ethernet frames on MAC TX data path
parameter PHY_IDENTIFIER = 32'h 00000000, // PHY Identifier
parameter DEV_VERSION = 16'h 0001 , // Customer Phy's Core Version
parameter ENABLE_SGMII = 1, // Enable SGMII logic for synthesis
parameter ENABLE_CLK_SHARING = 1, // Option to share clock for multiple channels (Clocks are rate-matched).
parameter ENABLE_REG_SHARING = 0, // Option to share register space. Uses certain hard-coded values from input.
parameter ENABLE_EXTENDED_STAT_REG = 0, // Enable a few extended statistic registers
parameter MAX_CHANNELS = 1, // The number of channels in Multi-TSE component
parameter ENABLE_PKT_CLASS = 1, // Enable Packet Classification Av-ST Interface
parameter ENABLE_RX_FIFO_STATUS = 1, // Enable Receive FIFO Almost Full status interface
parameter CHANNEL_WIDTH = 1, // The width of the channel interface
parameter EXPORT_PWRDN = 1'b0, // Option to export the Alt2gxb powerdown signal
parameter DEVICE_FAMILY = "ARRIAGX", // The device family the the core is targetted for.
parameter TRANSCEIVER_OPTION = 1'b0, // Option to select transceiver block for MAC PCS PMA Instantiation. Valid Values are 0 and 1: 0 - GXB (GIGE Mode) 1 - LVDS IO
parameter ENABLE_ALT_RECONFIG = 0, // Option to expose the altreconfig ports
parameter SYNCHRONIZER_DEPTH = 3, // Number of synchronizer
// Internal parameters
parameter STARTING_CHANNEL_NUMBER = 0,
parameter ADDR_WIDTH = (MAX_CHANNELS > 16)? 13 :
(MAX_CHANNELS > 8)? 12 :
(MAX_CHANNELS > 4)? 11 :
(MAX_CHANNELS > 2)? 10 :
(MAX_CHANNELS > 1)? 9 : 8
)
// Port List
(
// RESET / MAC REG IF / MDIO
input wire reset, // Asynchronous Reset - clk Domain
input wire clk, // 25MHz Host Interface Clock
input wire read, // Register Read Strobe
input wire write, // Register Write Strobe
input wire [ADDR_WIDTH-1:0] address, // Register Address
input wire [31:0] writedata, // Write Data for Host Bus
output wire [31:0] readdata, // Read Data to Host Bus
output wire waitrequest, // Interface Busy
output wire mdc, // 2.5MHz Inteface
input wire mdio_in, // MDIO Input
output wire mdio_out, // MDIO Output
output wire mdio_oen, // MDIO Output Enable
// DEVICE SPECIFIC SIGNALS
input wire gxb_cal_blk_clk, // GXB Calibration Clock
input wire ref_clk, // Rference Clock
// SHARED CLK SIGNALS
output wire mac_rx_clk, // Av-ST Receive Clock
output wire mac_tx_clk, // Av-ST Transmit Clock
// SHARED RX STATUS
input wire rx_afull_clk, // Almost full clk
input wire [1:0] rx_afull_data, // Almost full data
input wire rx_afull_valid, // Almost full valid
input wire [CHANNEL_WIDTH-1:0] rx_afull_channel, // Almost full channel
// CHANNEL 0
// PCS SIGNALS TO PHY
input wire rxp_0, // Differential Receive Data
output wire txp_0, // Differential Transmit Data
output wire rx_recovclkout_0, // Receiver Recovered Clock
output wire led_crs_0, // Carrier Sense
output wire led_link_0, // Valid Link
output wire led_col_0, // Collision Indication
output wire led_an_0, // Auto-Negotiation Status
output wire led_char_err_0, // Character Error
output wire led_disp_err_0, // Disparity Error
// AV-ST TX & RX
output wire mac_rx_clk_0, // Av-ST Receive Clock
output wire mac_tx_clk_0, // Av-ST Transmit Clock
output wire data_rx_sop_0, // Start of Packet
output wire data_rx_eop_0, // End of Packet
output wire [7:0] data_rx_data_0, // Data from FIFO
output wire [4:0] data_rx_error_0, // Receive packet error
output wire data_rx_valid_0, // Data Receive FIFO Valid
input wire data_rx_ready_0, // Data Receive Ready
output wire [4:0] pkt_class_data_0, // Frame Type Indication
output wire pkt_class_valid_0, // Frame Type Indication Valid
input wire data_tx_error_0, // STATUS FIFO (Tx frame Error from Apps)
input wire [7:0] data_tx_data_0, // Data from FIFO transmit
input wire data_tx_valid_0, // Data FIFO transmit Empty
input wire data_tx_sop_0, // Start of Packet
input wire data_tx_eop_0, // END of Packet
output wire data_tx_ready_0, // Data FIFO transmit Read Enable
// STAND_ALONE CONDUITS
output wire tx_ff_uflow_0, // TX FIFO underflow occured (Synchronous with tx_clk)
input wire tx_crc_fwd_0, // Forward Current Frame with CRC from Application
input wire xoff_gen_0, // Xoff Pause frame generate
input wire xon_gen_0, // Xon Pause frame generate
input wire magic_sleep_n_0, // Enable Sleep Mode
output wire magic_wakeup_0, // Wake Up Request
// RECONFIG BLOCK SIGNALS
input wire [139:0] reconfig_togxb_0, // Signals from the reconfig block to the GXB block
output wire [91:0] reconfig_fromgxb_0, // Signals from the gxb block to the reconfig block
input wire [8:0]phy_mgmt_address_0, // address to PHYIP management interface
input wire phy_mgmt_read_0, // read to PHYIP management interface
output wire [31:0]phy_mgmt_readdata_0, // readdata from PHYIP management interface
output wire phy_mgmt_waitrequest_0, // waitrequest from PHYIP management interface
input wire phy_mgmt_write_0, // write to PHYIP management interface
input wire [31:0]phy_mgmt_writedata_0,// writedata to PHYIP management interface
// CHANNEL 1
// PCS SIGNALS TO PHY
input wire rxp_1, // Differential Receive Data
output wire txp_1, // Differential Transmit Data
output wire rx_recovclkout_1, // Receiver Recovered Clock
output wire led_crs_1, // Carrier Sense
output wire led_link_1, // Valid Link
output wire led_col_1, // Collision Indication
output wire led_an_1, // Auto-Negotiation Status
output wire led_char_err_1, // Character Error
output wire led_disp_err_1, // Disparity Error
// AV-ST TX & RX
output wire mac_rx_clk_1, // Av-ST Receive Clock
output wire mac_tx_clk_1, // Av-ST Transmit Clock
output wire data_rx_sop_1, // Start of Packet
output wire data_rx_eop_1, // End of Packet
output wire [7:0] data_rx_data_1, // Data from FIFO
output wire [4:0] data_rx_error_1, // Receive packet error
output wire data_rx_valid_1, // Data Receive FIFO Valid
input wire data_rx_ready_1, // Data Receive Ready
output wire [4:0] pkt_class_data_1, // Frame Type Indication
output wire pkt_class_valid_1, // Frame Type Indication Valid
input wire data_tx_error_1, // STATUS FIFO (Tx frame Error from Apps)
input wire [7:0] data_tx_data_1, // Data from FIFO transmit
input wire data_tx_valid_1, // Data FIFO transmit Empty
input wire data_tx_sop_1, // Start of Packet
input wire data_tx_eop_1, // END of Packet
output wire data_tx_ready_1, // Data FIFO transmit Read Enable
// STAND_ALONE CONDUITS
output wire tx_ff_uflow_1, // TX FIFO underflow occured (Synchronous with tx_clk)
input wire tx_crc_fwd_1, // Forward Current Frame with CRC from Application
input wire xoff_gen_1, // Xoff Pause frame generate
input wire xon_gen_1, // Xon Pause frame generate
input wire magic_sleep_n_1, // Enable Sleep Mode
output wire magic_wakeup_1, // Wake Up Request
// RECONFIG BLOCK SIGNALS
input wire [139:0] reconfig_togxb_1, // Signals from the reconfig block to the GXB block
output wire [91:0] reconfig_fromgxb_1, // Signals from the gxb block to the reconfig block
input wire [8:0]phy_mgmt_address_1, // address to PHYIP management interface
input wire phy_mgmt_read_1, // read to PHYIP management interface
output wire [31:0]phy_mgmt_readdata_1, // readdata from PHYIP management interface
output wire phy_mgmt_waitrequest_1, // waitrequest from PHYIP management interface
input wire phy_mgmt_write_1, // write to PHYIP management interface
input wire [31:0]phy_mgmt_writedata_1,// writedata to PHYIP management interface
// CHANNEL 2
// PCS SIGNALS TO PHY
input wire rxp_2, // Differential Receive Data
output wire txp_2, // Differential Transmit Data
output wire rx_recovclkout_2, // Receiver Recovered Clock
output wire led_crs_2, // Carrier Sense
output wire led_link_2, // Valid Link
output wire led_col_2, // Collision Indication
output wire led_an_2, // Auto-Negotiation Status
output wire led_char_err_2, // Character Error
output wire led_disp_err_2, // Disparity Error
// AV-ST TX & RX
output wire mac_rx_clk_2, // Av-ST Receive Clock
output wire mac_tx_clk_2, // Av-ST Transmit Clock
output wire data_rx_sop_2, // Start of Packet
output wire data_rx_eop_2, // End of Packet
output wire [7:0] data_rx_data_2, // Data from FIFO
output wire [4:0] data_rx_error_2, // Receive packet error
output wire data_rx_valid_2, // Data Receive FIFO Valid
input wire data_rx_ready_2, // Data Receive Ready
output wire [4:0] pkt_class_data_2, // Frame Type Indication
output wire pkt_class_valid_2, // Frame Type Indication Valid
input wire data_tx_error_2, // STATUS FIFO (Tx frame Error from Apps)
input wire [7:0] data_tx_data_2, // Data from FIFO transmit
input wire data_tx_valid_2, // Data FIFO transmit Empty
input wire data_tx_sop_2, // Start of Packet
input wire data_tx_eop_2, // END of Packet
output wire data_tx_ready_2, // Data FIFO transmit Read Enable
// STAND_ALONE CONDUITS
output wire tx_ff_uflow_2, // TX FIFO underflow occured (Synchronous with tx_clk)
input wire tx_crc_fwd_2, // Forward Current Frame with CRC from Application
input wire xoff_gen_2, // Xoff Pause frame generate
input wire xon_gen_2, // Xon Pause frame generate
input wire magic_sleep_n_2, // Enable Sleep Mode
output wire magic_wakeup_2, // Wake Up Request
// RECONFIG BLOCK SIGNALS
input wire [139:0] reconfig_togxb_2, // Signals from the reconfig block to the GXB block
output wire [91:0] reconfig_fromgxb_2, // Signals from the gxb block to the reconfig block
input wire [8:0]phy_mgmt_address_2, // address to PHYIP management interface
input wire phy_mgmt_read_2, // read to PHYIP management interface
output wire [31:0]phy_mgmt_readdata_2, // readdata from PHYIP management interface
output wire phy_mgmt_waitrequest_2, // waitrequest from PHYIP management interface
input wire phy_mgmt_write_2, // write to PHYIP management interface
input wire [31:0]phy_mgmt_writedata_2,// writedata to PHYIP management interface
// CHANNEL 3
// PCS SIGNALS TO PHY
input wire rxp_3, // Differential Receive Data
output wire txp_3, // Differential Transmit Data
output wire rx_recovclkout_3, // Receiver Recovered Clock
output wire led_crs_3, // Carrier Sense
output wire led_link_3, // Valid Link
output wire led_col_3, // Collision Indication
output wire led_an_3, // Auto-Negotiation Status
output wire led_char_err_3, // Character Error
output wire led_disp_err_3, // Disparity Error
// AV-ST TX & RX
output wire mac_rx_clk_3, // Av-ST Receive Clock
output wire mac_tx_clk_3, // Av-ST Transmit Clock
output wire data_rx_sop_3, // Start of Packet
output wire data_rx_eop_3, // End of Packet
output wire [7:0] data_rx_data_3, // Data from FIFO
output wire [4:0] data_rx_error_3, // Receive packet error
output wire data_rx_valid_3, // Data Receive FIFO Valid
input wire data_rx_ready_3, // Data Receive Ready
output wire [4:0] pkt_class_data_3, // Frame Type Indication
output wire pkt_class_valid_3, // Frame Type Indication Valid
input wire data_tx_error_3, // STATUS FIFO (Tx frame Error from Apps)
input wire [7:0] data_tx_data_3, // Data from FIFO transmit
input wire data_tx_valid_3, // Data FIFO transmit Empty
input wire data_tx_sop_3, // Start of Packet
input wire data_tx_eop_3, // END of Packet
output wire data_tx_ready_3, // Data FIFO transmit Read Enable
// STAND_ALONE CONDUITS
output wire tx_ff_uflow_3, // TX FIFO underflow occured (Synchronous with tx_clk)
input wire tx_crc_fwd_3, // Forward Current Frame with CRC from Application
input wire xoff_gen_3, // Xoff Pause frame generate
input wire xon_gen_3, // Xon Pause frame generate
input wire magic_sleep_n_3, // Enable Sleep Mode
output wire magic_wakeup_3, // Wake Up Request
// RECONFIG BLOCK SIGNALS
input wire [139:0] reconfig_togxb_3, // Signals from the reconfig block to the GXB block
output wire [91:0] reconfig_fromgxb_3, // Signals from the gxb block to the reconfig block
input wire [8:0]phy_mgmt_address_3, // address to PHYIP management interface
input wire phy_mgmt_read_3, // read to PHYIP management interface
output wire [31:0]phy_mgmt_readdata_3, // readdata from PHYIP management interface
output wire phy_mgmt_waitrequest_3, // waitrequest from PHYIP management interface
input wire phy_mgmt_write_3, // write to PHYIP management interface
input wire [31:0]phy_mgmt_writedata_3,// writedata to PHYIP management interface
// CHANNEL 4
// PCS SIGNALS TO PHY
input wire rxp_4, // Differential Receive Data
output wire txp_4, // Differential Transmit Data
output wire rx_recovclkout_4, // Receiver Recovered Clock
output wire led_crs_4, // Carrier Sense
output wire led_link_4, // Valid Link
output wire led_col_4, // Collision Indication
output wire led_an_4, // Auto-Negotiation Status
output wire led_char_err_4, // Character Error
output wire led_disp_err_4, // Disparity Error
// AV-ST TX & RX
output wire mac_rx_clk_4, // Av-ST Receive Clock
output wire mac_tx_clk_4, // Av-ST Transmit Clock
output wire data_rx_sop_4, // Start of Packet
output wire data_rx_eop_4, // End of Packet
output wire [7:0] data_rx_data_4, // Data from FIFO
output wire [4:0] data_rx_error_4, // Receive packet error
output wire data_rx_valid_4, // Data Receive FIFO Valid
input wire data_rx_ready_4, // Data Receive Ready
output wire [4:0] pkt_class_data_4, // Frame Type Indication
output wire pkt_class_valid_4, // Frame Type Indication Valid
input wire data_tx_error_4, // STATUS FIFO (Tx frame Error from Apps)
input wire [7:0] data_tx_data_4, // Data from FIFO transmit
input wire data_tx_valid_4, // Data FIFO transmit Empty
input wire data_tx_sop_4, // Start of Packet
input wire data_tx_eop_4, // END of Packet
output wire data_tx_ready_4, // Data FIFO transmit Read Enable
// STAND_ALONE CONDUITS
output wire tx_ff_uflow_4, // TX FIFO underflow occured (Synchronous with tx_clk)
input wire tx_crc_fwd_4, // Forward Current Frame with CRC from Application
input wire xoff_gen_4, // Xoff Pause frame generate
input wire xon_gen_4, // Xon Pause frame generate
input wire magic_sleep_n_4, // Enable Sleep Mode
output wire magic_wakeup_4, // Wake Up Request
// RECONFIG BLOCK SIGNALS
input wire [139:0] reconfig_togxb_4, // Signals from the reconfig block to the GXB block
output wire [91:0] reconfig_fromgxb_4, // Signals from the gxb block to the reconfig block
input wire [8:0]phy_mgmt_address_4, // address to PHYIP management interface
input wire phy_mgmt_read_4, // read to PHYIP management interface
output wire [31:0]phy_mgmt_readdata_4, // readdata from PHYIP management interface
output wire phy_mgmt_waitrequest_4, // waitrequest from PHYIP management interface
input wire phy_mgmt_write_4, // write to PHYIP management interface
input wire [31:0]phy_mgmt_writedata_4,// writedata to PHYIP management interface
// CHANNEL 5
// PCS SIGNALS TO PHY
input wire rxp_5, // Differential Receive Data
output wire txp_5, // Differential Transmit Data
output wire rx_recovclkout_5, // Receiver Recovered Clock
output wire led_crs_5, // Carrier Sense
output wire led_link_5, // Valid Link
output wire led_col_5, // Collision Indication
output wire led_an_5, // Auto-Negotiation Status
output wire led_char_err_5, // Character Error
output wire led_disp_err_5, // Disparity Error
// AV-ST TX & RX
output wire mac_rx_clk_5, // Av-ST Receive Clock
output wire mac_tx_clk_5, // Av-ST Transmit Clock
output wire data_rx_sop_5, // Start of Packet
output wire data_rx_eop_5, // End of Packet
output wire [7:0] data_rx_data_5, // Data from FIFO
output wire [4:0] data_rx_error_5, // Receive packet error
output wire data_rx_valid_5, // Data Receive FIFO Valid
input wire data_rx_ready_5, // Data Receive Ready
output wire [4:0] pkt_class_data_5, // Frame Type Indication
output wire pkt_class_valid_5, // Frame Type Indication Valid
input wire data_tx_error_5, // STATUS FIFO (Tx frame Error from Apps)
input wire [7:0] data_tx_data_5, // Data from FIFO transmit
input wire data_tx_valid_5, // Data FIFO transmit Empty
input wire data_tx_sop_5, // Start of Packet
input wire data_tx_eop_5, // END of Packet
output wire data_tx_ready_5, // Data FIFO transmit Read Enable
// STAND_ALONE CONDUITS
output wire tx_ff_uflow_5, // TX FIFO underflow occured (Synchronous with tx_clk)
input wire tx_crc_fwd_5, // Forward Current Frame with CRC from Application
input wire xoff_gen_5, // Xoff Pause frame generate
input wire xon_gen_5, // Xon Pause frame generate
input wire magic_sleep_n_5, // Enable Sleep Mode
output wire magic_wakeup_5, // Wake Up Request
// RECONFIG BLOCK SIGNALS
input wire [139:0] reconfig_togxb_5, // Signals from the reconfig block to the GXB block
output wire [91:0] reconfig_fromgxb_5, // Signals from the gxb block to the reconfig block
input wire [8:0]phy_mgmt_address_5, // address to PHYIP management interface
input wire phy_mgmt_read_5, // read to PHYIP management interface
output wire [31:0]phy_mgmt_readdata_5, // readdata from PHYIP management interface
output wire phy_mgmt_waitrequest_5, // waitrequest from PHYIP management interface
input wire phy_mgmt_write_5, // write to PHYIP management interface
input wire [31:0]phy_mgmt_writedata_5,// writedata to PHYIP management interface
// CHANNEL 6
// PCS SIGNALS TO PHY
input wire rxp_6, // Differential Receive Data
output wire txp_6, // Differential Transmit Data
output wire rx_recovclkout_6, // Receiver Recovered Clock
output wire led_crs_6, // Carrier Sense
output wire led_link_6, // Valid Link
output wire led_col_6, // Collision Indication
output wire led_an_6, // Auto-Negotiation Status
output wire led_char_err_6, // Character Error
output wire led_disp_err_6, // Disparity Error
// AV-ST TX & RX
output wire mac_rx_clk_6, // Av-ST Receive Clock
output wire mac_tx_clk_6, // Av-ST Transmit Clock
output wire data_rx_sop_6, // Start of Packet
output wire data_rx_eop_6, // End of Packet
output wire [7:0] data_rx_data_6, // Data from FIFO
output wire [4:0] data_rx_error_6, // Receive packet error
output wire data_rx_valid_6, // Data Receive FIFO Valid
input wire data_rx_ready_6, // Data Receive Ready
output wire [4:0] pkt_class_data_6, // Frame Type Indication
output wire pkt_class_valid_6, // Frame Type Indication Valid
input wire data_tx_error_6, // STATUS FIFO (Tx frame Error from Apps)
input wire [7:0] data_tx_data_6, // Data from FIFO transmit
input wire data_tx_valid_6, // Data FIFO transmit Empty
input wire data_tx_sop_6, // Start of Packet
input wire data_tx_eop_6, // END of Packet
output wire data_tx_ready_6, // Data FIFO transmit Read Enable
// STAND_ALONE CONDUITS
output wire tx_ff_uflow_6, // TX FIFO underflow occured (Synchronous with tx_clk)
input wire tx_crc_fwd_6, // Forward Current Frame with CRC from Application
input wire xoff_gen_6, // Xoff Pause frame generate
input wire xon_gen_6, // Xon Pause frame generate
input wire magic_sleep_n_6, // Enable Sleep Mode
output wire magic_wakeup_6, // Wake Up Request
// RECONFIG BLOCK SIGNALS
input wire [139:0] reconfig_togxb_6, // Signals from the reconfig block to the GXB block
output wire [91:0] reconfig_fromgxb_6, // Signals from the gxb block to the reconfig block
input wire [8:0]phy_mgmt_address_6, // address to PHYIP management interface
input wire phy_mgmt_read_6, // read to PHYIP management interface
output wire [31:0]phy_mgmt_readdata_6, // readdata from PHYIP management interface
output wire phy_mgmt_waitrequest_6, // waitrequest from PHYIP management interface
input wire phy_mgmt_write_6, // write to PHYIP management interface
input wire [31:0]phy_mgmt_writedata_6,// writedata to PHYIP management interface
// CHANNEL 7
// PCS SIGNALS TO PHY
input wire rxp_7, // Differential Receive Data
output wire txp_7, // Differential Transmit Data
output wire rx_recovclkout_7, // Receiver Recovered Clock
output wire led_crs_7, // Carrier Sense
output wire led_link_7, // Valid Link
output wire led_col_7, // Collision Indication
output wire led_an_7, // Auto-Negotiation Status
output wire led_char_err_7, // Character Error
output wire led_disp_err_7, // Disparity Error
// AV-ST TX & RX
output wire mac_rx_clk_7, // Av-ST Receive Clock
output wire mac_tx_clk_7, // Av-ST Transmit Clock
output wire data_rx_sop_7, // Start of Packet
output wire data_rx_eop_7, // End of Packet
output wire [7:0] data_rx_data_7, // Data from FIFO
output wire [4:0] data_rx_error_7, // Receive packet error
output wire data_rx_valid_7, // Data Receive FIFO Valid
input wire data_rx_ready_7, // Data Receive Ready
output wire [4:0] pkt_class_data_7, // Frame Type Indication
output wire pkt_class_valid_7, // Frame Type Indication Valid
input wire data_tx_error_7, // STATUS FIFO (Tx frame Error from Apps)
input wire [7:0] data_tx_data_7, // Data from FIFO transmit
input wire data_tx_valid_7, // Data FIFO transmit Empty
input wire data_tx_sop_7, // Start of Packet
input wire data_tx_eop_7, // END of Packet
output wire data_tx_ready_7, // Data FIFO transmit Read Enable
// STAND_ALONE CONDUITS
output wire tx_ff_uflow_7, // TX FIFO underflow occured (Synchronous with tx_clk)
input wire tx_crc_fwd_7, // Forward Current Frame with CRC from Application
input wire xoff_gen_7, // Xoff Pause frame generate
input wire xon_gen_7, // Xon Pause frame generate
input wire magic_sleep_n_7, // Enable Sleep Mode
output wire magic_wakeup_7, // Wake Up Request
// RECONFIG BLOCK SIGNALS
input wire [139:0] reconfig_togxb_7, // Signals from the reconfig block to the GXB block
output wire [91:0] reconfig_fromgxb_7, // Signals from the gxb block to the reconfig block
input wire [8:0]phy_mgmt_address_7, // address to PHYIP management interface
input wire phy_mgmt_read_7, // read to PHYIP management interface
output wire [31:0]phy_mgmt_readdata_7, // readdata from PHYIP management interface
output wire phy_mgmt_waitrequest_7, // waitrequest from PHYIP management interface
input wire phy_mgmt_write_7, // write to PHYIP management interface
input wire [31:0]phy_mgmt_writedata_7,// writedata to PHYIP management interface
// CHANNEL 8
// PCS SIGNALS TO PHY
input wire rxp_8, // Differential Receive Data
output wire txp_8, // Differential Transmit Data
output wire rx_recovclkout_8, // Receiver Recovered Clock
output wire led_crs_8, // Carrier Sense
output wire led_link_8, // Valid Link
output wire led_col_8, // Collision Indication
output wire led_an_8, // Auto-Negotiation Status
output wire led_char_err_8, // Character Error
output wire led_disp_err_8, // Disparity Error
// AV-ST TX & RX
output wire mac_rx_clk_8, // Av-ST Receive Clock
output wire mac_tx_clk_8, // Av-ST Transmit Clock
output wire data_rx_sop_8, // Start of Packet
output wire data_rx_eop_8, // End of Packet
output wire [7:0] data_rx_data_8, // Data from FIFO
output wire [4:0] data_rx_error_8, // Receive packet error
output wire data_rx_valid_8, // Data Receive FIFO Valid
input wire data_rx_ready_8, // Data Receive Ready
output wire [4:0] pkt_class_data_8, // Frame Type Indication
output wire pkt_class_valid_8, // Frame Type Indication Valid
input wire data_tx_error_8, // STATUS FIFO (Tx frame Error from Apps)
input wire [7:0] data_tx_data_8, // Data from FIFO transmit
input wire data_tx_valid_8, // Data FIFO transmit Empty
input wire data_tx_sop_8, // Start of Packet
input wire data_tx_eop_8, // END of Packet
output wire data_tx_ready_8, // Data FIFO transmit Read Enable
// STAND_ALONE CONDUITS
output wire tx_ff_uflow_8, // TX FIFO underflow occured (Synchronous with tx_clk)
input wire tx_crc_fwd_8, // Forward Current Frame with CRC from Application
input wire xoff_gen_8, // Xoff Pause frame generate
input wire xon_gen_8, // Xon Pause frame generate
input wire magic_sleep_n_8, // Enable Sleep Mode
output wire magic_wakeup_8, // Wake Up Request
// RECONFIG BLOCK SIGNALS
input wire [139:0] reconfig_togxb_8, // Signals from the reconfig block to the GXB block
output wire [91:0] reconfig_fromgxb_8, // Signals from the gxb block to the reconfig block
input wire [8:0]phy_mgmt_address_8, // address to PHYIP management interface
input wire phy_mgmt_read_8, // read to PHYIP management interface
output wire [31:0]phy_mgmt_readdata_8, // readdata from PHYIP management interface
output wire phy_mgmt_waitrequest_8, // waitrequest from PHYIP management interface
input wire phy_mgmt_write_8, // write to PHYIP management interface
input wire [31:0]phy_mgmt_writedata_8,// writedata to PHYIP management interface
// CHANNEL 9
// PCS SIGNALS TO PHY
input wire rxp_9, // Differential Receive Data
output wire txp_9, // Differential Transmit Data
output wire rx_recovclkout_9, // Receiver Recovered Clock
output wire led_crs_9, // Carrier Sense
output wire led_link_9, // Valid Link
output wire led_col_9, // Collision Indication
output wire led_an_9, // Auto-Negotiation Status
output wire led_char_err_9, // Character Error
output wire led_disp_err_9, // Disparity Error
// AV-ST TX & RX
output wire mac_rx_clk_9, // Av-ST Receive Clock
output wire mac_tx_clk_9, // Av-ST Transmit Clock
output wire data_rx_sop_9, // Start of Packet
output wire data_rx_eop_9, // End of Packet
output wire [7:0] data_rx_data_9, // Data from FIFO
output wire [4:0] data_rx_error_9, // Receive packet error
output wire data_rx_valid_9, // Data Receive FIFO Valid
input wire data_rx_ready_9, // Data Receive Ready
output wire [4:0] pkt_class_data_9, // Frame Type Indication
output wire pkt_class_valid_9, // Frame Type Indication Valid
input wire data_tx_error_9, // STATUS FIFO (Tx frame Error from Apps)
input wire [7:0] data_tx_data_9, // Data from FIFO transmit
input wire data_tx_valid_9, // Data FIFO transmit Empty
input wire data_tx_sop_9, // Start of Packet
input wire data_tx_eop_9, // END of Packet
output wire data_tx_ready_9, // Data FIFO transmit Read Enable
// STAND_ALONE CONDUITS
output wire tx_ff_uflow_9, // TX FIFO underflow occured (Synchronous with tx_clk)
input wire tx_crc_fwd_9, // Forward Current Frame with CRC from Application
input wire xoff_gen_9, // Xoff Pause frame generate
input wire xon_gen_9, // Xon Pause frame generate
input wire magic_sleep_n_9, // Enable Sleep Mode
output wire magic_wakeup_9, // Wake Up Request
// RECONFIG BLOCK SIGNALS
input wire [139:0] reconfig_togxb_9, // Signals from the reconfig block to the GXB block
output wire [91:0] reconfig_fromgxb_9, // Signals from the gxb block to the reconfig block
input wire [8:0]phy_mgmt_address_9, // address to PHYIP management interface
input wire phy_mgmt_read_9, // read to PHYIP management interface
output wire [31:0]phy_mgmt_readdata_9, // readdata from PHYIP management interface
output wire phy_mgmt_waitrequest_9, // waitrequest from PHYIP management interface
input wire phy_mgmt_write_9, // write to PHYIP management interface
input wire [31:0]phy_mgmt_writedata_9,// writedata to PHYIP management interface
// CHANNEL 10
// PCS SIGNALS TO PHY
input wire rxp_10, // Differential Receive Data
output wire txp_10, // Differential Transmit Data
output wire rx_recovclkout_10, // Receiver Recovered Clock
output wire led_crs_10, // Carrier Sense
output wire led_link_10, // Valid Link
output wire led_col_10, // Collision Indication
output wire led_an_10, // Auto-Negotiation Status
output wire led_char_err_10, // Character Error
output wire led_disp_err_10, // Disparity Error
// AV-ST TX & RX
output wire mac_rx_clk_10, // Av-ST Receive Clock
output wire mac_tx_clk_10, // Av-ST Transmit Clock
output wire data_rx_sop_10, // Start of Packet
output wire data_rx_eop_10, // End of Packet
output wire [7:0] data_rx_data_10, // Data from FIFO
output wire [4:0] data_rx_error_10, // Receive packet error
output wire data_rx_valid_10, // Data Receive FIFO Valid
input wire data_rx_ready_10, // Data Receive Ready
output wire [4:0] pkt_class_data_10, // Frame Type Indication
output wire pkt_class_valid_10, // Frame Type Indication Valid
input wire data_tx_error_10, // STATUS FIFO (Tx frame Error from Apps)
input wire [7:0] data_tx_data_10, // Data from FIFO transmit
input wire data_tx_valid_10, // Data FIFO transmit Empty
input wire data_tx_sop_10, // Start of Packet
input wire data_tx_eop_10, // END of Packet
output wire data_tx_ready_10, // Data FIFO transmit Read Enable
// STAND_ALONE CONDUITS
output wire tx_ff_uflow_10, // TX FIFO underflow occured (Synchronous with tx_clk)
input wire tx_crc_fwd_10, // Forward Current Frame with CRC from Application
input wire xoff_gen_10, // Xoff Pause frame generate
input wire xon_gen_10, // Xon Pause frame generate
input wire magic_sleep_n_10, // Enable Sleep Mode
output wire magic_wakeup_10, // Wake Up Request
// RECONFIG BLOCK SIGNALS
input wire [139:0] reconfig_togxb_10, // Signals from the reconfig block to the GXB block
output wire [91:0] reconfig_fromgxb_10, // Signals from the gxb block to the reconfig block
input wire [8:0]phy_mgmt_address_10, // address to PHYIP management interface
input wire phy_mgmt_read_10, // read to PHYIP management interface
output wire [31:0]phy_mgmt_readdata_10, // readdata from PHYIP management interface
output wire phy_mgmt_waitrequest_10, // waitrequest from PHYIP management interface
input wire phy_mgmt_write_10, // write to PHYIP management interface
input wire [31:0]phy_mgmt_writedata_10,// writedata to PHYIP management interface
// CHANNEL 11
// PCS SIGNALS TO PHY
input wire rxp_11, // Differential Receive Data
output wire txp_11, // Differential Transmit Data
output wire rx_recovclkout_11, // Receiver Recovered Clock
output wire led_crs_11, // Carrier Sense
output wire led_link_11, // Valid Link
output wire led_col_11, // Collision Indication
output wire led_an_11, // Auto-Negotiation Status
output wire led_char_err_11, // Character Error
output wire led_disp_err_11, // Disparity Error
// AV-ST TX & RX
output wire mac_rx_clk_11, // Av-ST Receive Clock
output wire mac_tx_clk_11, // Av-ST Transmit Clock
output wire data_rx_sop_11, // Start of Packet
output wire data_rx_eop_11, // End of Packet
output wire [7:0] data_rx_data_11, // Data from FIFO
output wire [4:0] data_rx_error_11, // Receive packet error
output wire data_rx_valid_11, // Data Receive FIFO Valid
input wire data_rx_ready_11, // Data Receive Ready
output wire [4:0] pkt_class_data_11, // Frame Type Indication
output wire pkt_class_valid_11, // Frame Type Indication Valid
input wire data_tx_error_11, // STATUS FIFO (Tx frame Error from Apps)
input wire [7:0] data_tx_data_11, // Data from FIFO transmit
input wire data_tx_valid_11, // Data FIFO transmit Empty
input wire data_tx_sop_11, // Start of Packet
input wire data_tx_eop_11, // END of Packet
output wire data_tx_ready_11, // Data FIFO transmit Read Enable
// STAND_ALONE CONDUITS
output wire tx_ff_uflow_11, // TX FIFO underflow occured (Synchronous with tx_clk)
input wire tx_crc_fwd_11, // Forward Current Frame with CRC from Application
input wire xoff_gen_11, // Xoff Pause frame generate
input wire xon_gen_11, // Xon Pause frame generate
input wire magic_sleep_n_11, // Enable Sleep Mode
output wire magic_wakeup_11, // Wake Up Request
// RECONFIG BLOCK SIGNALS
input wire [139:0] reconfig_togxb_11, // Signals from the reconfig block to the GXB block
output wire [91:0] reconfig_fromgxb_11, // Signals from the gxb block to the reconfig block
input wire [8:0]phy_mgmt_address_11, // address to PHYIP management interface
input wire phy_mgmt_read_11, // read to PHYIP management interface
output wire [31:0]phy_mgmt_readdata_11, // readdata from PHYIP management interface
output wire phy_mgmt_waitrequest_11, // waitrequest from PHYIP management interface
input wire phy_mgmt_write_11, // write to PHYIP management interface
input wire [31:0]phy_mgmt_writedata_11,// writedata to PHYIP management interface
// CHANNEL 12
// PCS SIGNALS TO PHY
input wire rxp_12, // Differential Receive Data
output wire txp_12, // Differential Transmit Data
output wire rx_recovclkout_12, // Receiver Recovered Clock
output wire led_crs_12, // Carrier Sense
output wire led_link_12, // Valid Link
output wire led_col_12, // Collision Indication
output wire led_an_12, // Auto-Negotiation Status
output wire led_char_err_12, // Character Error
output wire led_disp_err_12, // Disparity Error
// AV-ST TX & RX
output wire mac_rx_clk_12, // Av-ST Receive Clock
output wire mac_tx_clk_12, // Av-ST Transmit Clock
output wire data_rx_sop_12, // Start of Packet
output wire data_rx_eop_12, // End of Packet
output wire [7:0] data_rx_data_12, // Data from FIFO
output wire [4:0] data_rx_error_12, // Receive packet error
output wire data_rx_valid_12, // Data Receive FIFO Valid
input wire data_rx_ready_12, // Data Receive Ready
output wire [4:0] pkt_class_data_12, // Frame Type Indication
output wire pkt_class_valid_12, // Frame Type Indication Valid
input wire data_tx_error_12, // STATUS FIFO (Tx frame Error from Apps)
input wire [7:0] data_tx_data_12, // Data from FIFO transmit
input wire data_tx_valid_12, // Data FIFO transmit Empty
input wire data_tx_sop_12, // Start of Packet
input wire data_tx_eop_12, // END of Packet
output wire data_tx_ready_12, // Data FIFO transmit Read Enable
// STAND_ALONE CONDUITS
output wire tx_ff_uflow_12, // TX FIFO underflow occured (Synchronous with tx_clk)
input wire tx_crc_fwd_12, // Forward Current Frame with CRC from Application
input wire xoff_gen_12, // Xoff Pause frame generate
input wire xon_gen_12, // Xon Pause frame generate
input wire magic_sleep_n_12, // Enable Sleep Mode
output wire magic_wakeup_12, // Wake Up Request
// RECONFIG BLOCK SIGNALS
input wire [139:0] reconfig_togxb_12, // Signals from the reconfig block to the GXB block
output wire [91:0] reconfig_fromgxb_12, // Signals from the gxb block to the reconfig block
input wire [8:0]phy_mgmt_address_12, // address to PHYIP management interface
input wire phy_mgmt_read_12, // read to PHYIP management interface
output wire [31:0]phy_mgmt_readdata_12, // readdata from PHYIP management interface
output wire phy_mgmt_waitrequest_12, // waitrequest from PHYIP management interface
input wire phy_mgmt_write_12, // write to PHYIP management interface
input wire [31:0]phy_mgmt_writedata_12,// writedata to PHYIP management interface
// CHANNEL 13
// PCS SIGNALS TO PHY
input wire rxp_13, // Differential Receive Data
output wire txp_13, // Differential Transmit Data
output wire rx_recovclkout_13, // Receiver Recovered Clock
output wire led_crs_13, // Carrier Sense
output wire led_link_13, // Valid Link
output wire led_col_13, // Collision Indication
output wire led_an_13, // Auto-Negotiation Status
output wire led_char_err_13, // Character Error
output wire led_disp_err_13, // Disparity Error
// AV-ST TX & RX
output wire mac_rx_clk_13, // Av-ST Receive Clock
output wire mac_tx_clk_13, // Av-ST Transmit Clock
output wire data_rx_sop_13, // Start of Packet
output wire data_rx_eop_13, // End of Packet
output wire [7:0] data_rx_data_13, // Data from FIFO
output wire [4:0] data_rx_error_13, // Receive packet error
output wire data_rx_valid_13, // Data Receive FIFO Valid
input wire data_rx_ready_13, // Data Receive Ready
output wire [4:0] pkt_class_data_13, // Frame Type Indication
output wire pkt_class_valid_13, // Frame Type Indication Valid
input wire data_tx_error_13, // STATUS FIFO (Tx frame Error from Apps)
input wire [7:0] data_tx_data_13, // Data from FIFO transmit
input wire data_tx_valid_13, // Data FIFO transmit Empty
input wire data_tx_sop_13, // Start of Packet
input wire data_tx_eop_13, // END of Packet
output wire data_tx_ready_13, // Data FIFO transmit Read Enable
// STAND_ALONE CONDUITS
output wire tx_ff_uflow_13, // TX FIFO underflow occured (Synchronous with tx_clk)
input wire tx_crc_fwd_13, // Forward Current Frame with CRC from Application
input wire xoff_gen_13, // Xoff Pause frame generate
input wire xon_gen_13, // Xon Pause frame generate
input wire magic_sleep_n_13, // Enable Sleep Mode
output wire magic_wakeup_13, // Wake Up Request
// RECONFIG BLOCK SIGNALS
input wire [139:0] reconfig_togxb_13, // Signals from the reconfig block to the GXB block
output wire [91:0] reconfig_fromgxb_13, // Signals from the gxb block to the reconfig block
input wire [8:0]phy_mgmt_address_13, // address to PHYIP management interface
input wire phy_mgmt_read_13, // read to PHYIP management interface
output wire [31:0]phy_mgmt_readdata_13, // readdata from PHYIP management interface
output wire phy_mgmt_waitrequest_13, // waitrequest from PHYIP management interface
input wire phy_mgmt_write_13, // write to PHYIP management interface
input wire [31:0]phy_mgmt_writedata_13,// writedata to PHYIP management interface
// CHANNEL 14
// PCS SIGNALS TO PHY
input wire rxp_14, // Differential Receive Data
output wire txp_14, // Differential Transmit Data
output wire rx_recovclkout_14, // Receiver Recovered Clock
output wire led_crs_14, // Carrier Sense
output wire led_link_14, // Valid Link
output wire led_col_14, // Collision Indication
output wire led_an_14, // Auto-Negotiation Status
output wire led_char_err_14, // Character Error
output wire led_disp_err_14, // Disparity Error
// AV-ST TX & RX
output wire mac_rx_clk_14, // Av-ST Receive Clock
output wire mac_tx_clk_14, // Av-ST Transmit Clock
output wire data_rx_sop_14, // Start of Packet
output wire data_rx_eop_14, // End of Packet
output wire [7:0] data_rx_data_14, // Data from FIFO
output wire [4:0] data_rx_error_14, // Receive packet error
output wire data_rx_valid_14, // Data Receive FIFO Valid
input wire data_rx_ready_14, // Data Receive Ready
output wire [4:0] pkt_class_data_14, // Frame Type Indication
output wire pkt_class_valid_14, // Frame Type Indication Valid
input wire data_tx_error_14, // STATUS FIFO (Tx frame Error from Apps)
input wire [7:0] data_tx_data_14, // Data from FIFO transmit
input wire data_tx_valid_14, // Data FIFO transmit Empty
input wire data_tx_sop_14, // Start of Packet
input wire data_tx_eop_14, // END of Packet
output wire data_tx_ready_14, // Data FIFO transmit Read Enable
// STAND_ALONE CONDUITS
output wire tx_ff_uflow_14, // TX FIFO underflow occured (Synchronous with tx_clk)
input wire tx_crc_fwd_14, // Forward Current Frame with CRC from Application
input wire xoff_gen_14, // Xoff Pause frame generate
input wire xon_gen_14, // Xon Pause frame generate
input wire magic_sleep_n_14, // Enable Sleep Mode
output wire magic_wakeup_14, // Wake Up Request
// RECONFIG BLOCK SIGNALS
input wire [139:0] reconfig_togxb_14, // Signals from the reconfig block to the GXB block
output wire [91:0] reconfig_fromgxb_14, // Signals from the gxb block to the reconfig block
input wire [8:0]phy_mgmt_address_14, // address to PHYIP management interface
input wire phy_mgmt_read_14, // read to PHYIP management interface
output wire [31:0]phy_mgmt_readdata_14, // readdata from PHYIP management interface
output wire phy_mgmt_waitrequest_14, // waitrequest from PHYIP management interface
input wire phy_mgmt_write_14, // write to PHYIP management interface
input wire [31:0]phy_mgmt_writedata_14,// writedata to PHYIP management interface
// CHANNEL 15
// PCS SIGNALS TO PHY
input wire rxp_15, // Differential Receive Data
output wire txp_15, // Differential Transmit Data
output wire rx_recovclkout_15, // Receiver Recovered Clock
output wire led_crs_15, // Carrier Sense
output wire led_link_15, // Valid Link
output wire led_col_15, // Collision Indication
output wire led_an_15, // Auto-Negotiation Status
output wire led_char_err_15, // Character Error
output wire led_disp_err_15, // Disparity Error
// AV-ST TX & RX
output wire mac_rx_clk_15, // Av-ST Receive Clock
output wire mac_tx_clk_15, // Av-ST Transmit Clock
output wire data_rx_sop_15, // Start of Packet
output wire data_rx_eop_15, // End of Packet
output wire [7:0] data_rx_data_15, // Data from FIFO
output wire [4:0] data_rx_error_15, // Receive packet error
output wire data_rx_valid_15, // Data Receive FIFO Valid
input wire data_rx_ready_15, // Data Receive Ready
output wire [4:0] pkt_class_data_15, // Frame Type Indication
output wire pkt_class_valid_15, // Frame Type Indication Valid
input wire data_tx_error_15, // STATUS FIFO (Tx frame Error from Apps)
input wire [7:0] data_tx_data_15, // Data from FIFO transmit
input wire data_tx_valid_15, // Data FIFO transmit Empty
input wire data_tx_sop_15, // Start of Packet
input wire data_tx_eop_15, // END of Packet
output wire data_tx_ready_15, // Data FIFO transmit Read Enable
// STAND_ALONE CONDUITS
output wire tx_ff_uflow_15, // TX FIFO underflow occured (Synchronous with tx_clk)
input wire tx_crc_fwd_15, // Forward Current Frame with CRC from Application
input wire xoff_gen_15, // Xoff Pause frame generate
input wire xon_gen_15, // Xon Pause frame generate
input wire magic_sleep_n_15, // Enable Sleep Mode
output wire magic_wakeup_15, // Wake Up Request
// RECONFIG BLOCK SIGNALS
input wire [139:0] reconfig_togxb_15, // Signals from the reconfig block to the GXB block
output wire [91:0] reconfig_fromgxb_15, // Signals from the gxb block to the reconfig block
input wire [8:0]phy_mgmt_address_15, // address to PHYIP management interface
input wire phy_mgmt_read_15, // read to PHYIP management interface
output wire [31:0]phy_mgmt_readdata_15, // readdata from PHYIP management interface
output wire phy_mgmt_waitrequest_15, // waitrequest from PHYIP management interface
input wire phy_mgmt_write_15, // write to PHYIP management interface
input wire [31:0]phy_mgmt_writedata_15,// writedata to PHYIP management interface
// CHANNEL 16
// PCS SIGNALS TO PHY
input wire rxp_16, // Differential Receive Data
output wire txp_16, // Differential Transmit Data
output wire rx_recovclkout_16, // Receiver Recovered Clock
output wire led_crs_16, // Carrier Sense
output wire led_link_16, // Valid Link
output wire led_col_16, // Collision Indication
output wire led_an_16, // Auto-Negotiation Status
output wire led_char_err_16, // Character Error
output wire led_disp_err_16, // Disparity Error
// AV-ST TX & RX
output wire mac_rx_clk_16, // Av-ST Receive Clock
output wire mac_tx_clk_16, // Av-ST Transmit Clock
output wire data_rx_sop_16, // Start of Packet
output wire data_rx_eop_16, // End of Packet
output wire [7:0] data_rx_data_16, // Data from FIFO
output wire [4:0] data_rx_error_16, // Receive packet error
output wire data_rx_valid_16, // Data Receive FIFO Valid
input wire data_rx_ready_16, // Data Receive Ready
output wire [4:0] pkt_class_data_16, // Frame Type Indication
output wire pkt_class_valid_16, // Frame Type Indication Valid
input wire data_tx_error_16, // STATUS FIFO (Tx frame Error from Apps)
input wire [7:0] data_tx_data_16, // Data from FIFO transmit
input wire data_tx_valid_16, // Data FIFO transmit Empty
input wire data_tx_sop_16, // Start of Packet
input wire data_tx_eop_16, // END of Packet
output wire data_tx_ready_16, // Data FIFO transmit Read Enable
// STAND_ALONE CONDUITS
output wire tx_ff_uflow_16, // TX FIFO underflow occured (Synchronous with tx_clk)
input wire tx_crc_fwd_16, // Forward Current Frame with CRC from Application
input wire xoff_gen_16, // Xoff Pause frame generate
input wire xon_gen_16, // Xon Pause frame generate
input wire magic_sleep_n_16, // Enable Sleep Mode
output wire magic_wakeup_16, // Wake Up Request
// RECONFIG BLOCK SIGNALS
input wire [139:0] reconfig_togxb_16, // Signals from the reconfig block to the GXB block
output wire [91:0] reconfig_fromgxb_16, // Signals from the gxb block to the reconfig block
input wire [8:0]phy_mgmt_address_16, // address to PHYIP management interface
input wire phy_mgmt_read_16, // read to PHYIP management interface
output wire [31:0]phy_mgmt_readdata_16, // readdata from PHYIP management interface
output wire phy_mgmt_waitrequest_16, // waitrequest from PHYIP management interface
input wire phy_mgmt_write_16, // write to PHYIP management interface
input wire [31:0]phy_mgmt_writedata_16,// writedata to PHYIP management interface
// CHANNEL 17
// PCS SIGNALS TO PHY
input wire rxp_17, // Differential Receive Data
output wire txp_17, // Differential Transmit Data
output wire rx_recovclkout_17, // Receiver Recovered Clock
output wire led_crs_17, // Carrier Sense
output wire led_link_17, // Valid Link
output wire led_col_17, // Collision Indication
output wire led_an_17, // Auto-Negotiation Status
output wire led_char_err_17, // Character Error
output wire led_disp_err_17, // Disparity Error
// AV-ST TX & RX
output wire mac_rx_clk_17, // Av-ST Receive Clock
output wire mac_tx_clk_17, // Av-ST Transmit Clock
output wire data_rx_sop_17, // Start of Packet
output wire data_rx_eop_17, // End of Packet
output wire [7:0] data_rx_data_17, // Data from FIFO
output wire [4:0] data_rx_error_17, // Receive packet error
output wire data_rx_valid_17, // Data Receive FIFO Valid
input wire data_rx_ready_17, // Data Receive Ready
output wire [4:0] pkt_class_data_17, // Frame Type Indication
output wire pkt_class_valid_17, // Frame Type Indication Valid
input wire data_tx_error_17, // STATUS FIFO (Tx frame Error from Apps)
input wire [7:0] data_tx_data_17, // Data from FIFO transmit
input wire data_tx_valid_17, // Data FIFO transmit Empty
input wire data_tx_sop_17, // Start of Packet
input wire data_tx_eop_17, // END of Packet
output wire data_tx_ready_17, // Data FIFO transmit Read Enable
// STAND_ALONE CONDUITS
output wire tx_ff_uflow_17, // TX FIFO underflow occured (Synchronous with tx_clk)
input wire tx_crc_fwd_17, // Forward Current Frame with CRC from Application
input wire xoff_gen_17, // Xoff Pause frame generate
input wire xon_gen_17, // Xon Pause frame generate
input wire magic_sleep_n_17, // Enable Sleep Mode
output wire magic_wakeup_17, // Wake Up Request
// RECONFIG BLOCK SIGNALS
input wire [139:0] reconfig_togxb_17, // Signals from the reconfig block to the GXB block
output wire [91:0] reconfig_fromgxb_17, // Signals from the gxb block to the reconfig block
input wire [8:0]phy_mgmt_address_17, // address to PHYIP management interface
input wire phy_mgmt_read_17, // read to PHYIP management interface
output wire [31:0]phy_mgmt_readdata_17, // readdata from PHYIP management interface
output wire phy_mgmt_waitrequest_17, // waitrequest from PHYIP management interface
input wire phy_mgmt_write_17, // write to PHYIP management interface
input wire [31:0]phy_mgmt_writedata_17,// writedata to PHYIP management interface
// CHANNEL 18
// PCS SIGNALS TO PHY
input wire rxp_18, // Differential Receive Data
output wire txp_18, // Differential Transmit Data
output wire rx_recovclkout_18, // Receiver Recovered Clock
output wire led_crs_18, // Carrier Sense
output wire led_link_18, // Valid Link
output wire led_col_18, // Collision Indication
output wire led_an_18, // Auto-Negotiation Status
output wire led_char_err_18, // Character Error
output wire led_disp_err_18, // Disparity Error
// AV-ST TX & RX
output wire mac_rx_clk_18, // Av-ST Receive Clock
output wire mac_tx_clk_18, // Av-ST Transmit Clock
output wire data_rx_sop_18, // Start of Packet
output wire data_rx_eop_18, // End of Packet
output wire [7:0] data_rx_data_18, // Data from FIFO
output wire [4:0] data_rx_error_18, // Receive packet error
output wire data_rx_valid_18, // Data Receive FIFO Valid
input wire data_rx_ready_18, // Data Receive Ready
output wire [4:0] pkt_class_data_18, // Frame Type Indication
output wire pkt_class_valid_18, // Frame Type Indication Valid
input wire data_tx_error_18, // STATUS FIFO (Tx frame Error from Apps)
input wire [7:0] data_tx_data_18, // Data from FIFO transmit
input wire data_tx_valid_18, // Data FIFO transmit Empty
input wire data_tx_sop_18, // Start of Packet
input wire data_tx_eop_18, // END of Packet
output wire data_tx_ready_18, // Data FIFO transmit Read Enable
// STAND_ALONE CONDUITS
output wire tx_ff_uflow_18, // TX FIFO underflow occured (Synchronous with tx_clk)
input wire tx_crc_fwd_18, // Forward Current Frame with CRC from Application
input wire xoff_gen_18, // Xoff Pause frame generate
input wire xon_gen_18, // Xon Pause frame generate
input wire magic_sleep_n_18, // Enable Sleep Mode
output wire magic_wakeup_18, // Wake Up Request
// RECONFIG BLOCK SIGNALS
input wire [139:0] reconfig_togxb_18, // Signals from the reconfig block to the GXB block
output wire [91:0] reconfig_fromgxb_18, // Signals from the gxb block to the reconfig block
input wire [8:0]phy_mgmt_address_18, // address to PHYIP management interface
input wire phy_mgmt_read_18, // read to PHYIP management interface
output wire [31:0]phy_mgmt_readdata_18, // readdata from PHYIP management interface
output wire phy_mgmt_waitrequest_18, // waitrequest from PHYIP management interface
input wire phy_mgmt_write_18, // write to PHYIP management interface
input wire [31:0]phy_mgmt_writedata_18,// writedata to PHYIP management interface
// CHANNEL 19
// PCS SIGNALS TO PHY
input wire rxp_19, // Differential Receive Data
output wire txp_19, // Differential Transmit Data
output wire rx_recovclkout_19, // Receiver Recovered Clock
output wire led_crs_19, // Carrier Sense
output wire led_link_19, // Valid Link
output wire led_col_19, // Collision Indication
output wire led_an_19, // Auto-Negotiation Status
output wire led_char_err_19, // Character Error
output wire led_disp_err_19, // Disparity Error
// AV-ST TX & RX
output wire mac_rx_clk_19, // Av-ST Receive Clock
output wire mac_tx_clk_19, // Av-ST Transmit Clock
output wire data_rx_sop_19, // Start of Packet
output wire data_rx_eop_19, // End of Packet
output wire [7:0] data_rx_data_19, // Data from FIFO
output wire [4:0] data_rx_error_19, // Receive packet error
output wire data_rx_valid_19, // Data Receive FIFO Valid
input wire data_rx_ready_19, // Data Receive Ready
output wire [4:0] pkt_class_data_19, // Frame Type Indication
output wire pkt_class_valid_19, // Frame Type Indication Valid
input wire data_tx_error_19, // STATUS FIFO (Tx frame Error from Apps)
input wire [7:0] data_tx_data_19, // Data from FIFO transmit
input wire data_tx_valid_19, // Data FIFO transmit Empty
input wire data_tx_sop_19, // Start of Packet
input wire data_tx_eop_19, // END of Packet
output wire data_tx_ready_19, // Data FIFO transmit Read Enable
// STAND_ALONE CONDUITS
output wire tx_ff_uflow_19, // TX FIFO underflow occured (Synchronous with tx_clk)
input wire tx_crc_fwd_19, // Forward Current Frame with CRC from Application
input wire xoff_gen_19, // Xoff Pause frame generate
input wire xon_gen_19, // Xon Pause frame generate
input wire magic_sleep_n_19, // Enable Sleep Mode
output wire magic_wakeup_19, // Wake Up Request
// RECONFIG BLOCK SIGNALS
input wire [139:0] reconfig_togxb_19, // Signals from the reconfig block to the GXB block
output wire [91:0] reconfig_fromgxb_19, // Signals from the gxb block to the reconfig block
input wire [8:0]phy_mgmt_address_19, // address to PHYIP management interface
input wire phy_mgmt_read_19, // read to PHYIP management interface
output wire [31:0]phy_mgmt_readdata_19, // readdata from PHYIP management interface
output wire phy_mgmt_waitrequest_19, // waitrequest from PHYIP management interface
input wire phy_mgmt_write_19, // write to PHYIP management interface
input wire [31:0]phy_mgmt_writedata_19,// writedata to PHYIP management interface
// CHANNEL 20
// PCS SIGNALS TO PHY
input wire rxp_20, // Differential Receive Data
output wire txp_20, // Differential Transmit Data
output wire rx_recovclkout_20, // Receiver Recovered Clock
output wire led_crs_20, // Carrier Sense
output wire led_link_20, // Valid Link
output wire led_col_20, // Collision Indication
output wire led_an_20, // Auto-Negotiation Status
output wire led_char_err_20, // Character Error
output wire led_disp_err_20, // Disparity Error
// AV-ST TX & RX
output wire mac_rx_clk_20, // Av-ST Receive Clock
output wire mac_tx_clk_20, // Av-ST Transmit Clock
output wire data_rx_sop_20, // Start of Packet
output wire data_rx_eop_20, // End of Packet
output wire [7:0] data_rx_data_20, // Data from FIFO
output wire [4:0] data_rx_error_20, // Receive packet error
output wire data_rx_valid_20, // Data Receive FIFO Valid
input wire data_rx_ready_20, // Data Receive Ready
output wire [4:0] pkt_class_data_20, // Frame Type Indication
output wire pkt_class_valid_20, // Frame Type Indication Valid
input wire data_tx_error_20, // STATUS FIFO (Tx frame Error from Apps)
input wire [7:0] data_tx_data_20, // Data from FIFO transmit
input wire data_tx_valid_20, // Data FIFO transmit Empty
input wire data_tx_sop_20, // Start of Packet
input wire data_tx_eop_20, // END of Packet
output wire data_tx_ready_20, // Data FIFO transmit Read Enable
// STAND_ALONE CONDUITS
output wire tx_ff_uflow_20, // TX FIFO underflow occured (Synchronous with tx_clk)
input wire tx_crc_fwd_20, // Forward Current Frame with CRC from Application
input wire xoff_gen_20, // Xoff Pause frame generate
input wire xon_gen_20, // Xon Pause frame generate
input wire magic_sleep_n_20, // Enable Sleep Mode
output wire magic_wakeup_20, // Wake Up Request
// RECONFIG BLOCK SIGNALS
input wire [139:0] reconfig_togxb_20, // Signals from the reconfig block to the GXB block
output wire [91:0] reconfig_fromgxb_20, // Signals from the gxb block to the reconfig block
input wire [8:0]phy_mgmt_address_20, // address to PHYIP management interface
input wire phy_mgmt_read_20, // read to PHYIP management interface
output wire [31:0]phy_mgmt_readdata_20, // readdata from PHYIP management interface
output wire phy_mgmt_waitrequest_20, // waitrequest from PHYIP management interface
input wire phy_mgmt_write_20, // write to PHYIP management interface
input wire [31:0]phy_mgmt_writedata_20,// writedata to PHYIP management interface
// CHANNEL 21
// PCS SIGNALS TO PHY
input wire rxp_21, // Differential Receive Data
output wire txp_21, // Differential Transmit Data
output wire rx_recovclkout_21, // Receiver Recovered Clock
output wire led_crs_21, // Carrier Sense
output wire led_link_21, // Valid Link
output wire led_col_21, // Collision Indication
output wire led_an_21, // Auto-Negotiation Status
output wire led_char_err_21, // Character Error
output wire led_disp_err_21, // Disparity Error
// AV-ST TX & RX
output wire mac_rx_clk_21, // Av-ST Receive Clock
output wire mac_tx_clk_21, // Av-ST Transmit Clock
output wire data_rx_sop_21, // Start of Packet
output wire data_rx_eop_21, // End of Packet
output wire [7:0] data_rx_data_21, // Data from FIFO
output wire [4:0] data_rx_error_21, // Receive packet error
output wire data_rx_valid_21, // Data Receive FIFO Valid
input wire data_rx_ready_21, // Data Receive Ready
output wire [4:0] pkt_class_data_21, // Frame Type Indication
output wire pkt_class_valid_21, // Frame Type Indication Valid
input wire data_tx_error_21, // STATUS FIFO (Tx frame Error from Apps)
input wire [7:0] data_tx_data_21, // Data from FIFO transmit
input wire data_tx_valid_21, // Data FIFO transmit Empty
input wire data_tx_sop_21, // Start of Packet
input wire data_tx_eop_21, // END of Packet
output wire data_tx_ready_21, // Data FIFO transmit Read Enable
// STAND_ALONE CONDUITS
output wire tx_ff_uflow_21, // TX FIFO underflow occured (Synchronous with tx_clk)
input wire tx_crc_fwd_21, // Forward Current Frame with CRC from Application
input wire xoff_gen_21, // Xoff Pause frame generate
input wire xon_gen_21, // Xon Pause frame generate
input wire magic_sleep_n_21, // Enable Sleep Mode
output wire magic_wakeup_21, // Wake Up Request
// RECONFIG BLOCK SIGNALS
input wire [139:0] reconfig_togxb_21, // Signals from the reconfig block to the GXB block
output wire [91:0] reconfig_fromgxb_21, // Signals from the gxb block to the reconfig block
input wire [8:0]phy_mgmt_address_21, // address to PHYIP management interface
input wire phy_mgmt_read_21, // read to PHYIP management interface
output wire [31:0]phy_mgmt_readdata_21, // readdata from PHYIP management interface
output wire phy_mgmt_waitrequest_21, // waitrequest from PHYIP management interface
input wire phy_mgmt_write_21, // write to PHYIP management interface
input wire [31:0]phy_mgmt_writedata_21,// writedata to PHYIP management interface
// CHANNEL 22
// PCS SIGNALS TO PHY
input wire rxp_22, // Differential Receive Data
output wire txp_22, // Differential Transmit Data
output wire rx_recovclkout_22, // Receiver Recovered Clock
output wire led_crs_22, // Carrier Sense
output wire led_link_22, // Valid Link
output wire led_col_22, // Collision Indication
output wire led_an_22, // Auto-Negotiation Status
output wire led_char_err_22, // Character Error
output wire led_disp_err_22, // Disparity Error
// AV-ST TX & RX
output wire mac_rx_clk_22, // Av-ST Receive Clock
output wire mac_tx_clk_22, // Av-ST Transmit Clock
output wire data_rx_sop_22, // Start of Packet
output wire data_rx_eop_22, // End of Packet
output wire [7:0] data_rx_data_22, // Data from FIFO
output wire [4:0] data_rx_error_22, // Receive packet error
output wire data_rx_valid_22, // Data Receive FIFO Valid
input wire data_rx_ready_22, // Data Receive Ready
output wire [4:0] pkt_class_data_22, // Frame Type Indication
output wire pkt_class_valid_22, // Frame Type Indication Valid
input wire data_tx_error_22, // STATUS FIFO (Tx frame Error from Apps)
input wire [7:0] data_tx_data_22, // Data from FIFO transmit
input wire data_tx_valid_22, // Data FIFO transmit Empty
input wire data_tx_sop_22, // Start of Packet
input wire data_tx_eop_22, // END of Packet
output wire data_tx_ready_22, // Data FIFO transmit Read Enable
// STAND_ALONE CONDUITS
output wire tx_ff_uflow_22, // TX FIFO underflow occured (Synchronous with tx_clk)
input wire tx_crc_fwd_22, // Forward Current Frame with CRC from Application
input wire xoff_gen_22, // Xoff Pause frame generate
input wire xon_gen_22, // Xon Pause frame generate
input wire magic_sleep_n_22, // Enable Sleep Mode
output wire magic_wakeup_22, // Wake Up Request
// RECONFIG BLOCK SIGNALS
input wire [139:0] reconfig_togxb_22, // Signals from the reconfig block to the GXB block
output wire [91:0] reconfig_fromgxb_22, // Signals from the gxb block to the reconfig block
input wire [8:0]phy_mgmt_address_22, // address to PHYIP management interface
input wire phy_mgmt_read_22, // read to PHYIP management interface
output wire [31:0]phy_mgmt_readdata_22, // readdata from PHYIP management interface
output wire phy_mgmt_waitrequest_22, // waitrequest from PHYIP management interface
input wire phy_mgmt_write_22, // write to PHYIP management interface
input wire [31:0]phy_mgmt_writedata_22,// writedata to PHYIP management interface
// CHANNEL 23
// PCS SIGNALS TO PHY
input wire rxp_23, // Differential Receive Data
output wire txp_23, // Differential Transmit Data
output wire rx_recovclkout_23, // Receiver Recovered Clock
output wire led_crs_23, // Carrier Sense
output wire led_link_23, // Valid Link
output wire led_col_23, // Collision Indication
output wire led_an_23, // Auto-Negotiation Status
output wire led_char_err_23, // Character Error
output wire led_disp_err_23, // Disparity Error
// AV-ST TX & RX
output wire mac_rx_clk_23, // Av-ST Receive Clock
output wire mac_tx_clk_23, // Av-ST Transmit Clock
output wire data_rx_sop_23, // Start of Packet
output wire data_rx_eop_23, // End of Packet
output wire [7:0] data_rx_data_23, // Data from FIFO
output wire [4:0] data_rx_error_23, // Receive packet error
output wire data_rx_valid_23, // Data Receive FIFO Valid
input wire data_rx_ready_23, // Data Receive Ready
output wire [4:0] pkt_class_data_23, // Frame Type Indication
output wire pkt_class_valid_23, // Frame Type Indication Valid
input wire data_tx_error_23, // STATUS FIFO (Tx frame Error from Apps)
input wire [7:0] data_tx_data_23, // Data from FIFO transmit
input wire data_tx_valid_23, // Data FIFO transmit Empty
input wire data_tx_sop_23, // Start of Packet
input wire data_tx_eop_23, // END of Packet
output wire data_tx_ready_23, // Data FIFO transmit Read Enable
// STAND_ALONE CONDUITS
output wire tx_ff_uflow_23, // TX FIFO underflow occured (Synchronous with tx_clk)
input wire tx_crc_fwd_23, // Forward Current Frame with CRC from Application
input wire xoff_gen_23, // Xoff Pause frame generate
input wire xon_gen_23, // Xon Pause frame generate
input wire magic_sleep_n_23, // Enable Sleep Mode
output wire magic_wakeup_23, // Wake Up Request
// RECONFIG BLOCK SIGNALS
input wire [139:0] reconfig_togxb_23, // Signals from the reconfig block to the GXB block
output wire [91:0] reconfig_fromgxb_23, // Signals from the gxb block to the reconfig block
input wire [8:0]phy_mgmt_address_23, // address to PHYIP management interface
input wire phy_mgmt_read_23, // read to PHYIP management interface
output wire [31:0]phy_mgmt_readdata_23, // readdata from PHYIP management interface
output wire phy_mgmt_waitrequest_23, // waitrequest from PHYIP management interface
input wire phy_mgmt_write_23, // write to PHYIP management interface
input wire [31:0]phy_mgmt_writedata_23);// writedata to PHYIP management interface
wire MAC_PCS_reset;
wire [23:0] pcs_pwrdn_out_sig;
wire [23:0] gxb_pwrdn_in_sig;
wire gige_pma_reset;
wire [23:0] led_char_err_gx;
wire [23:0] link_status;
//wire [23:0] pcs_clk;
wire tx_pcs_clk_c0;
wire tx_pcs_clk_c1;
wire tx_pcs_clk_c2;
wire tx_pcs_clk_c3;
wire tx_pcs_clk_c4;
wire tx_pcs_clk_c5;
wire tx_pcs_clk_c6;
wire tx_pcs_clk_c7;
wire tx_pcs_clk_c8;
wire tx_pcs_clk_c9;
wire tx_pcs_clk_c10;
wire tx_pcs_clk_c11;
wire tx_pcs_clk_c12;
wire tx_pcs_clk_c13;
wire tx_pcs_clk_c14;
wire tx_pcs_clk_c15;
wire tx_pcs_clk_c16;
wire tx_pcs_clk_c17;
wire tx_pcs_clk_c18;
wire tx_pcs_clk_c19;
wire tx_pcs_clk_c20;
wire tx_pcs_clk_c21;
wire tx_pcs_clk_c22;
wire tx_pcs_clk_c23;
wire rx_pcs_clk_c0;
wire rx_pcs_clk_c1;
wire rx_pcs_clk_c2;
wire rx_pcs_clk_c3;
wire rx_pcs_clk_c4;
wire rx_pcs_clk_c5;
wire rx_pcs_clk_c6;
wire rx_pcs_clk_c7;
wire rx_pcs_clk_c8;
wire rx_pcs_clk_c9;
wire rx_pcs_clk_c10;
wire rx_pcs_clk_c11;
wire rx_pcs_clk_c12;
wire rx_pcs_clk_c13;
wire rx_pcs_clk_c14;
wire rx_pcs_clk_c15;
wire rx_pcs_clk_c16;
wire rx_pcs_clk_c17;
wire rx_pcs_clk_c18;
wire rx_pcs_clk_c19;
wire rx_pcs_clk_c20;
wire rx_pcs_clk_c21;
wire rx_pcs_clk_c22;
wire rx_pcs_clk_c23;
wire [23:0] rx_char_err_gx;
wire [23:0] rx_disp_err;
wire [23:0] rx_syncstatus;
wire [23:0] rx_runlengthviolation;
wire [23:0] rx_patterndetect;
wire [23:0] rx_runningdisp;
wire [23:0] rx_rmfifodatadeleted;
wire [23:0] rx_rmfifodatainserted;
wire [23:0] pcs_rx_rmfifodatadeleted;
wire [23:0] pcs_rx_rmfifodatainserted;
wire [23:0] pcs_rx_carrierdetected;
wire rx_kchar_0;
wire [7:0] rx_frame_0;
wire pcs_rx_kchar_0;
wire [7:0] pcs_rx_frame_0;
wire tx_kchar_0;
wire [7:0] tx_frame_0;
wire rx_kchar_1;
wire [7:0] rx_frame_1;
wire pcs_rx_kchar_1;
wire [7:0] pcs_rx_frame_1;
wire tx_kchar_1;
wire [7:0] tx_frame_1;
wire rx_kchar_2;
wire [7:0] rx_frame_2;
wire pcs_rx_kchar_2;
wire [7:0] pcs_rx_frame_2;
wire tx_kchar_2;
wire [7:0] tx_frame_2;
wire rx_kchar_3;
wire [7:0] rx_frame_3;
wire pcs_rx_kchar_3;
wire [7:0] pcs_rx_frame_3;
wire tx_kchar_3;
wire [7:0] tx_frame_3;
wire rx_kchar_4;
wire [7:0] rx_frame_4;
wire pcs_rx_kchar_4;
wire [7:0] pcs_rx_frame_4;
wire tx_kchar_4;
wire [7:0] tx_frame_4;
wire rx_kchar_5;
wire [7:0] rx_frame_5;
wire pcs_rx_kchar_5;
wire [7:0] pcs_rx_frame_5;
wire tx_kchar_5;
wire [7:0] tx_frame_5;
wire rx_kchar_6;
wire [7:0] rx_frame_6;
wire pcs_rx_kchar_6;
wire [7:0] pcs_rx_frame_6;
wire tx_kchar_6;
wire [7:0] tx_frame_6;
wire rx_kchar_7;
wire [7:0] rx_frame_7;
wire pcs_rx_kchar_7;
wire [7:0] pcs_rx_frame_7;
wire tx_kchar_7;
wire [7:0] tx_frame_7;
wire rx_kchar_8;
wire [7:0] rx_frame_8;
wire pcs_rx_kchar_8;
wire [7:0] pcs_rx_frame_8;
wire tx_kchar_8;
wire [7:0] tx_frame_8;
wire rx_kchar_9;
wire [7:0] rx_frame_9;
wire pcs_rx_kchar_9;
wire [7:0] pcs_rx_frame_9;
wire tx_kchar_9;
wire [7:0] tx_frame_9;
wire rx_kchar_10;
wire [7:0] rx_frame_10;
wire pcs_rx_kchar_10;
wire [7:0] pcs_rx_frame_10;
wire tx_kchar_10;
wire [7:0] tx_frame_10;
wire rx_kchar_11;
wire [7:0] rx_frame_11;
wire pcs_rx_kchar_11;
wire [7:0] pcs_rx_frame_11;
wire tx_kchar_11;
wire [7:0] tx_frame_11;
wire rx_kchar_12;
wire [7:0] rx_frame_12;
wire pcs_rx_kchar_12;
wire [7:0] pcs_rx_frame_12;
wire tx_kchar_12;
wire [7:0] tx_frame_12;
wire rx_kchar_13;
wire [7:0] rx_frame_13;
wire pcs_rx_kchar_13;
wire [7:0] pcs_rx_frame_13;
wire tx_kchar_13;
wire [7:0] tx_frame_13;
wire rx_kchar_14;
wire [7:0] rx_frame_14;
wire pcs_rx_kchar_14;
wire [7:0] pcs_rx_frame_14;
wire tx_kchar_14;
wire [7:0] tx_frame_14;
wire rx_kchar_15;
wire [7:0] rx_frame_15;
wire pcs_rx_kchar_15;
wire [7:0] pcs_rx_frame_15;
wire tx_kchar_15;
wire [7:0] tx_frame_15;
wire rx_kchar_16;
wire [7:0] rx_frame_16;
wire pcs_rx_kchar_16;
wire [7:0] pcs_rx_frame_16;
wire tx_kchar_16;
wire [7:0] tx_frame_16;
wire rx_kchar_17;
wire [7:0] rx_frame_17;
wire pcs_rx_kchar_17;
wire [7:0] pcs_rx_frame_17;
wire tx_kchar_17;
wire [7:0] tx_frame_17;
wire rx_kchar_18;
wire [7:0] rx_frame_18;
wire pcs_rx_kchar_18;
wire [7:0] pcs_rx_frame_18;
wire tx_kchar_18;
wire [7:0] tx_frame_18;
wire rx_kchar_19;
wire [7:0] rx_frame_19;
wire pcs_rx_kchar_19;
wire [7:0] pcs_rx_frame_19;
wire tx_kchar_19;
wire [7:0] tx_frame_19;
wire rx_kchar_20;
wire [7:0] rx_frame_20;
wire pcs_rx_kchar_20;
wire [7:0] pcs_rx_frame_20;
wire tx_kchar_20;
wire [7:0] tx_frame_20;
wire rx_kchar_21;
wire [7:0] rx_frame_21;
wire pcs_rx_kchar_21;
wire [7:0] pcs_rx_frame_21;
wire tx_kchar_21;
wire [7:0] tx_frame_21;
wire rx_kchar_22;
wire [7:0] rx_frame_22;
wire pcs_rx_kchar_22;
wire [7:0] pcs_rx_frame_22;
wire tx_kchar_22;
wire [7:0] tx_frame_22;
wire rx_kchar_23;
wire [7:0] rx_frame_23;
wire pcs_rx_kchar_23;
wire [7:0] pcs_rx_frame_23;
wire tx_kchar_23;
wire [7:0] tx_frame_23;
wire sd_loopback_0;
wire sd_loopback_1;
wire sd_loopback_2;
wire sd_loopback_3;
wire sd_loopback_4;
wire sd_loopback_5;
wire sd_loopback_6;
wire sd_loopback_7;
wire sd_loopback_8;
wire sd_loopback_9;
wire sd_loopback_10;
wire sd_loopback_11;
wire sd_loopback_12;
wire sd_loopback_13;
wire sd_loopback_14;
wire sd_loopback_15;
wire sd_loopback_16;
wire sd_loopback_17;
wire sd_loopback_18;
wire sd_loopback_19;
wire sd_loopback_20;
wire sd_loopback_21;
wire sd_loopback_22;
wire sd_loopback_23;
wire reset_rx_pcs_clk_c0_int;
wire reset_rx_pcs_clk_c1_int;
wire reset_rx_pcs_clk_c2_int;
wire reset_rx_pcs_clk_c3_int;
wire reset_rx_pcs_clk_c4_int;
wire reset_rx_pcs_clk_c5_int;
wire reset_rx_pcs_clk_c6_int;
wire reset_rx_pcs_clk_c7_int;
wire reset_rx_pcs_clk_c8_int;
wire reset_rx_pcs_clk_c9_int;
wire reset_rx_pcs_clk_c10_int;
wire reset_rx_pcs_clk_c11_int;
wire reset_rx_pcs_clk_c12_int;
wire reset_rx_pcs_clk_c13_int;
wire reset_rx_pcs_clk_c14_int;
wire reset_rx_pcs_clk_c15_int;
wire reset_rx_pcs_clk_c16_int;
wire reset_rx_pcs_clk_c17_int;
wire reset_rx_pcs_clk_c18_int;
wire reset_rx_pcs_clk_c19_int;
wire reset_rx_pcs_clk_c20_int;
wire reset_rx_pcs_clk_c21_int;
wire reset_rx_pcs_clk_c22_int;
wire reset_rx_pcs_clk_c23_int;
//assign pcs_clk = {pcs_clk_c23,pcs_clk_c22,pcs_clk_c21,pcs_clk_c20,pcs_clk_c19,pcs_clk_c18,pcs_clk_c17,pcs_clk_c16,pcs_clk_c15,pcs_clk_c14,pcs_clk_c13,pcs_clk_c12,pcs_clk_c11,pcs_clk_c10,pcs_clk_c9,pcs_clk_c8,pcs_clk_c7,pcs_clk_c6,pcs_clk_c5,pcs_clk_c4,pcs_clk_c3,pcs_clk_c2,pcs_clk_c1,pcs_clk_c0};
// Assign the character error and link status to top level leds
// ------------------------------------------------------------
assign led_char_err_0 = led_char_err_gx[0];
assign led_link_0 = link_status[0];
assign led_char_err_1 = led_char_err_gx[1];
assign led_link_1 = link_status[1];
assign led_char_err_2 = led_char_err_gx[2];
assign led_link_2 = link_status[2];
assign led_char_err_3 = led_char_err_gx[3];
assign led_link_3 = link_status[3];
assign led_char_err_4 = led_char_err_gx[4];
assign led_link_4 = link_status[4];
assign led_char_err_5 = led_char_err_gx[5];
assign led_link_5 = link_status[5];
assign led_char_err_6 = led_char_err_gx[6];
assign led_link_6 = link_status[6];
assign led_char_err_7 = led_char_err_gx[7];
assign led_link_7 = link_status[7];
assign led_char_err_8 = led_char_err_gx[8];
assign led_link_8 = link_status[8];
assign led_char_err_9 = led_char_err_gx[9];
assign led_link_9 = link_status[9];
assign led_char_err_10 = led_char_err_gx[10];
assign led_link_10 = link_status[10];
assign led_char_err_11 = led_char_err_gx[11];
assign led_link_11 = link_status[11];
assign led_char_err_12 = led_char_err_gx[12];
assign led_link_12 = link_status[12];
assign led_char_err_13 = led_char_err_gx[13];
assign led_link_13 = link_status[13];
assign led_char_err_14 = led_char_err_gx[14];
assign led_link_14 = link_status[14];
assign led_char_err_15 = led_char_err_gx[15];
assign led_link_15 = link_status[15];
assign led_char_err_16 = led_char_err_gx[16];
assign led_link_16 = link_status[16];
assign led_char_err_17 = led_char_err_gx[17];
assign led_link_17 = link_status[17];
assign led_char_err_18 = led_char_err_gx[18];
assign led_link_18 = link_status[18];
assign led_char_err_19 = led_char_err_gx[19];
assign led_link_19 = link_status[19];
assign led_char_err_20 = led_char_err_gx[20];
assign led_link_20 = link_status[20];
assign led_char_err_21 = led_char_err_gx[21];
assign led_link_21 = link_status[21];
assign led_char_err_22 = led_char_err_gx[22];
assign led_link_22 = link_status[22];
assign led_char_err_23 = led_char_err_gx[23];
assign led_link_23 = link_status[23];
// Instantiation of the MAC_PCS core that connects to a PMA
// --------------------------------------------------------
altera_tse_top_multi_mac_pcs_gige U_MULTI_MAC_PCS(
.reset(reset), //INPUT : ASYNCHRONOUS RESET - clk DOMAIN
.clk(clk), //INPUT : CLOCK
.read(read), //INPUT : REGISTER READ TRANSACTION
.ref_clk(ref_clk), //INPUT : REFERENCE CLOCK
.write(write), //INPUT : REGISTER WRITE TRANSACTION
.address(address), //INPUT : REGISTER ADDRESS
.writedata(writedata), //INPUT : REGISTER WRITE DATA
.readdata(readdata), //OUTPUT : REGISTER READ DATA
.waitrequest(waitrequest), //OUTPUT : TRANSACTION BUSY, ACTIVE LOW
.mdc(mdc), //OUTPUT : MDIO Clock
.mdio_out(mdio_out), //OUTPUT : Outgoing MDIO DATA
.mdio_in(mdio_in), //INPUT : Incoming MDIO DATA
.mdio_oen(mdio_oen), //OUTPUT : MDIO Output Enable
.mac_rx_clk(mac_rx_clk), //OUTPUT : Av-ST Rx Clock
.mac_tx_clk(mac_tx_clk), //OUTPUT : Av-ST Tx Clock
.rx_afull_clk(rx_afull_clk), //INPUT : AFull Status Clock
.rx_afull_data(rx_afull_data), //INPUT : AFull Status Data
.rx_afull_valid(rx_afull_valid), //INPUT : AFull Status Valid
.rx_afull_channel(rx_afull_channel), //INPUT : AFull Status Channel
// Channel 0
.rx_carrierdetected_0(pcs_rx_carrierdetected[0]),
.rx_rmfifodatadeleted_0(pcs_rx_rmfifodatadeleted[0]),
.rx_rmfifodatainserted_0(pcs_rx_rmfifodatainserted[0]),
.rx_clkout_0(rx_pcs_clk_c0), //INPUT : Receive Clock
.tx_clkout_0(tx_pcs_clk_c0), //INPUT : Transmit Clock
.rx_kchar_0(pcs_rx_kchar_0), //INPUT : Special Character Indication
.tx_kchar_0(tx_kchar_0), //OUTPUT : Special Character Indication
.rx_frame_0(pcs_rx_frame_0), //INPUT : Frame
.tx_frame_0(tx_frame_0), //OUTPUT : Frame
.sd_loopback_0(sd_loopback_0), //OUTPUT : SERDES Loopback Enable
.powerdown_0(pcs_pwrdn_out_sig[0]), //OUTPUT : Powerdown Enable
.led_col_0(led_col_0), //OUTPUT : Collision Indication
.led_an_0(led_an_0), //OUTPUT : Auto Negotiation Status
.led_char_err_0(led_char_err_gx[0]), //INPUT : Character error
.led_crs_0(led_crs_0), //OUTPUT : Carrier sense
.led_link_0(link_status[0]), //INPUT : Valid link
.mac_rx_clk_0(mac_rx_clk_0), //OUTPUT : Av-ST Rx Clock
.mac_tx_clk_0(mac_tx_clk_0), //OUTPUT : Av-ST Tx Clock
.data_rx_sop_0(data_rx_sop_0), //OUTPUT : Start of Packet
.data_rx_eop_0(data_rx_eop_0), //OUTPUT : End of Packet
.data_rx_data_0(data_rx_data_0), //OUTPUT : Data from FIFO
.data_rx_error_0(data_rx_error_0), //OUTPUT : Receive packet error
.data_rx_valid_0(data_rx_valid_0), //OUTPUT : Data Receive FIFO Valid
.data_rx_ready_0(data_rx_ready_0), //OUTPUT : Data Receive Ready
.pkt_class_data_0(pkt_class_data_0), //OUTPUT : Frame Type Indication
.pkt_class_valid_0(pkt_class_valid_0), //OUTPUT : Frame Type Indication Valid
.data_tx_error_0(data_tx_error_0), //INPUT : Status
.data_tx_data_0(data_tx_data_0), //INPUT : Data from FIFO transmit
.data_tx_valid_0(data_tx_valid_0), //INPUT : Data FIFO transmit Empty
.data_tx_sop_0(data_tx_sop_0), //INPUT : Start of Packet
.data_tx_eop_0(data_tx_eop_0), //INPUT : End of Packet
.data_tx_ready_0(data_tx_ready_0), //OUTPUT : Data FIFO transmit Read Enable
.tx_ff_uflow_0(tx_ff_uflow_0), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
.tx_crc_fwd_0(tx_crc_fwd_0), //INPUT : Forward Current Frame with CRC from Application
.xoff_gen_0(xoff_gen_0), //INPUT : XOFF PAUSE FRAME GENERATE
.xon_gen_0(xon_gen_0), //INPUT : XON PAUSE FRAME GENERATE
.magic_sleep_n_0(magic_sleep_n_0), //INPUT : MAC SLEEP MODE CONTROL
.magic_wakeup_0(magic_wakeup_0), //OUTPUT : MAC WAKE-UP INDICATION
// Channel 1
.rx_carrierdetected_1(pcs_rx_carrierdetected[1]),
.rx_rmfifodatadeleted_1(pcs_rx_rmfifodatadeleted[1]),
.rx_rmfifodatainserted_1(pcs_rx_rmfifodatainserted[1]),
.rx_clkout_1(rx_pcs_clk_c1), //INPUT : Receive Clock
.tx_clkout_1(tx_pcs_clk_c1), //INPUT : Transmit Clock
.rx_kchar_1(pcs_rx_kchar_1), //INPUT : Special Character Indication
.tx_kchar_1(tx_kchar_1), //OUTPUT : Special Character Indication
.rx_frame_1(pcs_rx_frame_1), //INPUT : Frame
.tx_frame_1(tx_frame_1), //OUTPUT : Frame
.sd_loopback_1(sd_loopback_1), //OUTPUT : SERDES Loopback Enable
.powerdown_1(pcs_pwrdn_out_sig[1]), //OUTPUT : Powerdown Enable
.led_col_1(led_col_1), //OUTPUT : Collision Indication
.led_an_1(led_an_1), //OUTPUT : Auto Negotiation Status
.led_char_err_1(led_char_err_gx[1]), //INPUT : Character error
.led_crs_1(led_crs_1), //OUTPUT : Carrier sense
.led_link_1(link_status[1]), //INPUT : Valid link
.mac_rx_clk_1(mac_rx_clk_1), //OUTPUT : Av-ST Rx Clock
.mac_tx_clk_1(mac_tx_clk_1), //OUTPUT : Av-ST Tx Clock
.data_rx_sop_1(data_rx_sop_1), //OUTPUT : Start of Packet
.data_rx_eop_1(data_rx_eop_1), //OUTPUT : End of Packet
.data_rx_data_1(data_rx_data_1), //OUTPUT : Data from FIFO
.data_rx_error_1(data_rx_error_1), //OUTPUT : Receive packet error
.data_rx_valid_1(data_rx_valid_1), //OUTPUT : Data Receive FIFO Valid
.data_rx_ready_1(data_rx_ready_1), //OUTPUT : Data Receive Ready
.pkt_class_data_1(pkt_class_data_1), //OUTPUT : Frame Type Indication
.pkt_class_valid_1(pkt_class_valid_1), //OUTPUT : Frame Type Indication Valid
.data_tx_error_1(data_tx_error_1), //INPUT : Status
.data_tx_data_1(data_tx_data_1), //INPUT : Data from FIFO transmit
.data_tx_valid_1(data_tx_valid_1), //INPUT : Data FIFO transmit Empty
.data_tx_sop_1(data_tx_sop_1), //INPUT : Start of Packet
.data_tx_eop_1(data_tx_eop_1), //INPUT : End of Packet
.data_tx_ready_1(data_tx_ready_1), //OUTPUT : Data FIFO transmit Read Enable
.tx_ff_uflow_1(tx_ff_uflow_1), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
.tx_crc_fwd_1(tx_crc_fwd_1), //INPUT : Forward Current Frame with CRC from Application
.xoff_gen_1(xoff_gen_1), //INPUT : XOFF PAUSE FRAME GENERATE
.xon_gen_1(xon_gen_1), //INPUT : XON PAUSE FRAME GENERATE
.magic_sleep_n_1(magic_sleep_n_1), //INPUT : MAC SLEEP MODE CONTROL
.magic_wakeup_1(magic_wakeup_1), //OUTPUT : MAC WAKE-UP INDICATION
// Channel 2
.rx_carrierdetected_2(pcs_rx_carrierdetected[2]),
.rx_rmfifodatadeleted_2(pcs_rx_rmfifodatadeleted[2]),
.rx_rmfifodatainserted_2(pcs_rx_rmfifodatainserted[2]),
.rx_clkout_2(rx_pcs_clk_c2), //INPUT : Receive Clock
.tx_clkout_2(tx_pcs_clk_c2), //INPUT : Transmit Clock
.rx_kchar_2(pcs_rx_kchar_2), //INPUT : Special Character Indication
.tx_kchar_2(tx_kchar_2), //OUTPUT : Special Character Indication
.rx_frame_2(pcs_rx_frame_2), //INPUT : Frame
.tx_frame_2(tx_frame_2), //OUTPUT : Frame
.sd_loopback_2(sd_loopback_2), //OUTPUT : SERDES Loopback Enable
.powerdown_2(pcs_pwrdn_out_sig[2]), //OUTPUT : Powerdown Enable
.led_col_2(led_col_2), //OUTPUT : Collision Indication
.led_an_2(led_an_2), //OUTPUT : Auto Negotiation Status
.led_char_err_2(led_char_err_gx[2]), //INPUT : Character error
.led_crs_2(led_crs_2), //OUTPUT : Carrier sense
.led_link_2(link_status[2]), //INPUT : Valid link
.mac_rx_clk_2(mac_rx_clk_2), //OUTPUT : Av-ST Rx Clock
.mac_tx_clk_2(mac_tx_clk_2), //OUTPUT : Av-ST Tx Clock
.data_rx_sop_2(data_rx_sop_2), //OUTPUT : Start of Packet
.data_rx_eop_2(data_rx_eop_2), //OUTPUT : End of Packet
.data_rx_data_2(data_rx_data_2), //OUTPUT : Data from FIFO
.data_rx_error_2(data_rx_error_2), //OUTPUT : Receive packet error
.data_rx_valid_2(data_rx_valid_2), //OUTPUT : Data Receive FIFO Valid
.data_rx_ready_2(data_rx_ready_2), //OUTPUT : Data Receive Ready
.pkt_class_data_2(pkt_class_data_2), //OUTPUT : Frame Type Indication
.pkt_class_valid_2(pkt_class_valid_2), //OUTPUT : Frame Type Indication Valid
.data_tx_error_2(data_tx_error_2), //INPUT : Status
.data_tx_data_2(data_tx_data_2), //INPUT : Data from FIFO transmit
.data_tx_valid_2(data_tx_valid_2), //INPUT : Data FIFO transmit Empty
.data_tx_sop_2(data_tx_sop_2), //INPUT : Start of Packet
.data_tx_eop_2(data_tx_eop_2), //INPUT : End of Packet
.data_tx_ready_2(data_tx_ready_2), //OUTPUT : Data FIFO transmit Read Enable
.tx_ff_uflow_2(tx_ff_uflow_2), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
.tx_crc_fwd_2(tx_crc_fwd_2), //INPUT : Forward Current Frame with CRC from Application
.xoff_gen_2(xoff_gen_2), //INPUT : XOFF PAUSE FRAME GENERATE
.xon_gen_2(xon_gen_2), //INPUT : XON PAUSE FRAME GENERATE
.magic_sleep_n_2(magic_sleep_n_2), //INPUT : MAC SLEEP MODE CONTROL
.magic_wakeup_2(magic_wakeup_2), //OUTPUT : MAC WAKE-UP INDICATION
// Channel 3
.rx_carrierdetected_3(pcs_rx_carrierdetected[3]),
.rx_rmfifodatadeleted_3(pcs_rx_rmfifodatadeleted[3]),
.rx_rmfifodatainserted_3(pcs_rx_rmfifodatainserted[3]),
.rx_clkout_3(rx_pcs_clk_c3), //INPUT : Receive Clock
.tx_clkout_3(tx_pcs_clk_c3), //INPUT : Transmit Clock
.rx_kchar_3(pcs_rx_kchar_3), //INPUT : Special Character Indication
.tx_kchar_3(tx_kchar_3), //OUTPUT : Special Character Indication
.rx_frame_3(pcs_rx_frame_3), //INPUT : Frame
.tx_frame_3(tx_frame_3), //OUTPUT : Frame
.sd_loopback_3(sd_loopback_3), //OUTPUT : SERDES Loopback Enable
.powerdown_3(pcs_pwrdn_out_sig[3]), //OUTPUT : Powerdown Enable
.led_col_3(led_col_3), //OUTPUT : Collision Indication
.led_an_3(led_an_3), //OUTPUT : Auto Negotiation Status
.led_char_err_3(led_char_err_gx[3]), //INPUT : Character error
.led_crs_3(led_crs_3), //OUTPUT : Carrier sense
.led_link_3(link_status[3]), //INPUT : Valid link
.mac_rx_clk_3(mac_rx_clk_3), //OUTPUT : Av-ST Rx Clock
.mac_tx_clk_3(mac_tx_clk_3), //OUTPUT : Av-ST Tx Clock
.data_rx_sop_3(data_rx_sop_3), //OUTPUT : Start of Packet
.data_rx_eop_3(data_rx_eop_3), //OUTPUT : End of Packet
.data_rx_data_3(data_rx_data_3), //OUTPUT : Data from FIFO
.data_rx_error_3(data_rx_error_3), //OUTPUT : Receive packet error
.data_rx_valid_3(data_rx_valid_3), //OUTPUT : Data Receive FIFO Valid
.data_rx_ready_3(data_rx_ready_3), //OUTPUT : Data Receive Ready
.pkt_class_data_3(pkt_class_data_3), //OUTPUT : Frame Type Indication
.pkt_class_valid_3(pkt_class_valid_3), //OUTPUT : Frame Type Indication Valid
.data_tx_error_3(data_tx_error_3), //INPUT : Status
.data_tx_data_3(data_tx_data_3), //INPUT : Data from FIFO transmit
.data_tx_valid_3(data_tx_valid_3), //INPUT : Data FIFO transmit Empty
.data_tx_sop_3(data_tx_sop_3), //INPUT : Start of Packet
.data_tx_eop_3(data_tx_eop_3), //INPUT : End of Packet
.data_tx_ready_3(data_tx_ready_3), //OUTPUT : Data FIFO transmit Read Enable
.tx_ff_uflow_3(tx_ff_uflow_3), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
.tx_crc_fwd_3(tx_crc_fwd_3), //INPUT : Forward Current Frame with CRC from Application
.xoff_gen_3(xoff_gen_3), //INPUT : XOFF PAUSE FRAME GENERATE
.xon_gen_3(xon_gen_3), //INPUT : XON PAUSE FRAME GENERATE
.magic_sleep_n_3(magic_sleep_n_3), //INPUT : MAC SLEEP MODE CONTROL
.magic_wakeup_3(magic_wakeup_3), //OUTPUT : MAC WAKE-UP INDICATION
// Channel 4
.rx_carrierdetected_4(pcs_rx_carrierdetected[4]),
.rx_rmfifodatadeleted_4(pcs_rx_rmfifodatadeleted[4]),
.rx_rmfifodatainserted_4(pcs_rx_rmfifodatainserted[4]),
.rx_clkout_4(rx_pcs_clk_c4), //INPUT : Receive Clock
.tx_clkout_4(tx_pcs_clk_c4), //INPUT : Transmit Clock
.rx_kchar_4(pcs_rx_kchar_4), //INPUT : Special Character Indication
.tx_kchar_4(tx_kchar_4), //OUTPUT : Special Character Indication
.rx_frame_4(pcs_rx_frame_4), //INPUT : Frame
.tx_frame_4(tx_frame_4), //OUTPUT : Frame
.sd_loopback_4(sd_loopback_4), //OUTPUT : SERDES Loopback Enable
.powerdown_4(pcs_pwrdn_out_sig[4]), //OUTPUT : Powerdown Enable
.led_col_4(led_col_4), //OUTPUT : Collision Indication
.led_an_4(led_an_4), //OUTPUT : Auto Negotiation Status
.led_char_err_4(led_char_err_gx[4]), //INPUT : Character error
.led_crs_4(led_crs_4), //OUTPUT : Carrier sense
.led_link_4(link_status[4]), //INPUT : Valid link
.mac_rx_clk_4(mac_rx_clk_4), //OUTPUT : Av-ST Rx Clock
.mac_tx_clk_4(mac_tx_clk_4), //OUTPUT : Av-ST Tx Clock
.data_rx_sop_4(data_rx_sop_4), //OUTPUT : Start of Packet
.data_rx_eop_4(data_rx_eop_4), //OUTPUT : End of Packet
.data_rx_data_4(data_rx_data_4), //OUTPUT : Data from FIFO
.data_rx_error_4(data_rx_error_4), //OUTPUT : Receive packet error
.data_rx_valid_4(data_rx_valid_4), //OUTPUT : Data Receive FIFO Valid
.data_rx_ready_4(data_rx_ready_4), //OUTPUT : Data Receive Ready
.pkt_class_data_4(pkt_class_data_4), //OUTPUT : Frame Type Indication
.pkt_class_valid_4(pkt_class_valid_4), //OUTPUT : Frame Type Indication Valid
.data_tx_error_4(data_tx_error_4), //INPUT : Status
.data_tx_data_4(data_tx_data_4), //INPUT : Data from FIFO transmit
.data_tx_valid_4(data_tx_valid_4), //INPUT : Data FIFO transmit Empty
.data_tx_sop_4(data_tx_sop_4), //INPUT : Start of Packet
.data_tx_eop_4(data_tx_eop_4), //INPUT : End of Packet
.data_tx_ready_4(data_tx_ready_4), //OUTPUT : Data FIFO transmit Read Enable
.tx_ff_uflow_4(tx_ff_uflow_4), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
.tx_crc_fwd_4(tx_crc_fwd_4), //INPUT : Forward Current Frame with CRC from Application
.xoff_gen_4(xoff_gen_4), //INPUT : XOFF PAUSE FRAME GENERATE
.xon_gen_4(xon_gen_4), //INPUT : XON PAUSE FRAME GENERATE
.magic_sleep_n_4(magic_sleep_n_4), //INPUT : MAC SLEEP MODE CONTROL
.magic_wakeup_4(magic_wakeup_4), //OUTPUT : MAC WAKE-UP INDICATION
// Channel 5
.rx_carrierdetected_5(pcs_rx_carrierdetected[5]),
.rx_rmfifodatadeleted_5(pcs_rx_rmfifodatadeleted[5]),
.rx_rmfifodatainserted_5(pcs_rx_rmfifodatainserted[5]),
.rx_clkout_5(rx_pcs_clk_c5), //INPUT : Receive Clock
.tx_clkout_5(tx_pcs_clk_c5), //INPUT : Transmit Clock
.rx_kchar_5(pcs_rx_kchar_5), //INPUT : Special Character Indication
.tx_kchar_5(tx_kchar_5), //OUTPUT : Special Character Indication
.rx_frame_5(pcs_rx_frame_5), //INPUT : Frame
.tx_frame_5(tx_frame_5), //OUTPUT : Frame
.sd_loopback_5(sd_loopback_5), //OUTPUT : SERDES Loopback Enable
.powerdown_5(pcs_pwrdn_out_sig[5]), //OUTPUT : Powerdown Enable
.led_col_5(led_col_5), //OUTPUT : Collision Indication
.led_an_5(led_an_5), //OUTPUT : Auto Negotiation Status
.led_char_err_5(led_char_err_gx[5]), //INPUT : Character error
.led_crs_5(led_crs_5), //OUTPUT : Carrier sense
.led_link_5(link_status[5]), //INPUT : Valid link
.mac_rx_clk_5(mac_rx_clk_5), //OUTPUT : Av-ST Rx Clock
.mac_tx_clk_5(mac_tx_clk_5), //OUTPUT : Av-ST Tx Clock
.data_rx_sop_5(data_rx_sop_5), //OUTPUT : Start of Packet
.data_rx_eop_5(data_rx_eop_5), //OUTPUT : End of Packet
.data_rx_data_5(data_rx_data_5), //OUTPUT : Data from FIFO
.data_rx_error_5(data_rx_error_5), //OUTPUT : Receive packet error
.data_rx_valid_5(data_rx_valid_5), //OUTPUT : Data Receive FIFO Valid
.data_rx_ready_5(data_rx_ready_5), //OUTPUT : Data Receive Ready
.pkt_class_data_5(pkt_class_data_5), //OUTPUT : Frame Type Indication
.pkt_class_valid_5(pkt_class_valid_5), //OUTPUT : Frame Type Indication Valid
.data_tx_error_5(data_tx_error_5), //INPUT : Status
.data_tx_data_5(data_tx_data_5), //INPUT : Data from FIFO transmit
.data_tx_valid_5(data_tx_valid_5), //INPUT : Data FIFO transmit Empty
.data_tx_sop_5(data_tx_sop_5), //INPUT : Start of Packet
.data_tx_eop_5(data_tx_eop_5), //INPUT : End of Packet
.data_tx_ready_5(data_tx_ready_5), //OUTPUT : Data FIFO transmit Read Enable
.tx_ff_uflow_5(tx_ff_uflow_5), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
.tx_crc_fwd_5(tx_crc_fwd_5), //INPUT : Forward Current Frame with CRC from Application
.xoff_gen_5(xoff_gen_5), //INPUT : XOFF PAUSE FRAME GENERATE
.xon_gen_5(xon_gen_5), //INPUT : XON PAUSE FRAME GENERATE
.magic_sleep_n_5(magic_sleep_n_5), //INPUT : MAC SLEEP MODE CONTROL
.magic_wakeup_5(magic_wakeup_5), //OUTPUT : MAC WAKE-UP INDICATION
// Channel 6
.rx_carrierdetected_6(pcs_rx_carrierdetected[6]),
.rx_rmfifodatadeleted_6(pcs_rx_rmfifodatadeleted[6]),
.rx_rmfifodatainserted_6(pcs_rx_rmfifodatainserted[6]),
.rx_clkout_6(rx_pcs_clk_c6), //INPUT : Receive Clock
.tx_clkout_6(tx_pcs_clk_c6), //INPUT : Transmit Clock
.rx_kchar_6(pcs_rx_kchar_6), //INPUT : Special Character Indication
.tx_kchar_6(tx_kchar_6), //OUTPUT : Special Character Indication
.rx_frame_6(pcs_rx_frame_6), //INPUT : Frame
.tx_frame_6(tx_frame_6), //OUTPUT : Frame
.sd_loopback_6(sd_loopback_6), //OUTPUT : SERDES Loopback Enable
.powerdown_6(pcs_pwrdn_out_sig[6]), //OUTPUT : Powerdown Enable
.led_col_6(led_col_6), //OUTPUT : Collision Indication
.led_an_6(led_an_6), //OUTPUT : Auto Negotiation Status
.led_char_err_6(led_char_err_gx[6]), //INPUT : Character error
.led_crs_6(led_crs_6), //OUTPUT : Carrier sense
.led_link_6(link_status[6]), //INPUT : Valid link
.mac_rx_clk_6(mac_rx_clk_6), //OUTPUT : Av-ST Rx Clock
.mac_tx_clk_6(mac_tx_clk_6), //OUTPUT : Av-ST Tx Clock
.data_rx_sop_6(data_rx_sop_6), //OUTPUT : Start of Packet
.data_rx_eop_6(data_rx_eop_6), //OUTPUT : End of Packet
.data_rx_data_6(data_rx_data_6), //OUTPUT : Data from FIFO
.data_rx_error_6(data_rx_error_6), //OUTPUT : Receive packet error
.data_rx_valid_6(data_rx_valid_6), //OUTPUT : Data Receive FIFO Valid
.data_rx_ready_6(data_rx_ready_6), //OUTPUT : Data Receive Ready
.pkt_class_data_6(pkt_class_data_6), //OUTPUT : Frame Type Indication
.pkt_class_valid_6(pkt_class_valid_6), //OUTPUT : Frame Type Indication Valid
.data_tx_error_6(data_tx_error_6), //INPUT : Status
.data_tx_data_6(data_tx_data_6), //INPUT : Data from FIFO transmit
.data_tx_valid_6(data_tx_valid_6), //INPUT : Data FIFO transmit Empty
.data_tx_sop_6(data_tx_sop_6), //INPUT : Start of Packet
.data_tx_eop_6(data_tx_eop_6), //INPUT : End of Packet
.data_tx_ready_6(data_tx_ready_6), //OUTPUT : Data FIFO transmit Read Enable
.tx_ff_uflow_6(tx_ff_uflow_6), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
.tx_crc_fwd_6(tx_crc_fwd_6), //INPUT : Forward Current Frame with CRC from Application
.xoff_gen_6(xoff_gen_6), //INPUT : XOFF PAUSE FRAME GENERATE
.xon_gen_6(xon_gen_6), //INPUT : XON PAUSE FRAME GENERATE
.magic_sleep_n_6(magic_sleep_n_6), //INPUT : MAC SLEEP MODE CONTROL
.magic_wakeup_6(magic_wakeup_6), //OUTPUT : MAC WAKE-UP INDICATION
// Channel 7
.rx_carrierdetected_7(pcs_rx_carrierdetected[7]),
.rx_rmfifodatadeleted_7(pcs_rx_rmfifodatadeleted[7]),
.rx_rmfifodatainserted_7(pcs_rx_rmfifodatainserted[7]),
.rx_clkout_7(rx_pcs_clk_c7), //INPUT : Receive Clock
.tx_clkout_7(tx_pcs_clk_c7), //INPUT : Transmit Clock
.rx_kchar_7(pcs_rx_kchar_7), //INPUT : Special Character Indication
.tx_kchar_7(tx_kchar_7), //OUTPUT : Special Character Indication
.rx_frame_7(pcs_rx_frame_7), //INPUT : Frame
.tx_frame_7(tx_frame_7), //OUTPUT : Frame
.sd_loopback_7(sd_loopback_7), //OUTPUT : SERDES Loopback Enable
.powerdown_7(pcs_pwrdn_out_sig[7]), //OUTPUT : Powerdown Enable
.led_col_7(led_col_7), //OUTPUT : Collision Indication
.led_an_7(led_an_7), //OUTPUT : Auto Negotiation Status
.led_char_err_7(led_char_err_gx[7]), //INPUT : Character error
.led_crs_7(led_crs_7), //OUTPUT : Carrier sense
.led_link_7(link_status[7]), //INPUT : Valid link
.mac_rx_clk_7(mac_rx_clk_7), //OUTPUT : Av-ST Rx Clock
.mac_tx_clk_7(mac_tx_clk_7), //OUTPUT : Av-ST Tx Clock
.data_rx_sop_7(data_rx_sop_7), //OUTPUT : Start of Packet
.data_rx_eop_7(data_rx_eop_7), //OUTPUT : End of Packet
.data_rx_data_7(data_rx_data_7), //OUTPUT : Data from FIFO
.data_rx_error_7(data_rx_error_7), //OUTPUT : Receive packet error
.data_rx_valid_7(data_rx_valid_7), //OUTPUT : Data Receive FIFO Valid
.data_rx_ready_7(data_rx_ready_7), //OUTPUT : Data Receive Ready
.pkt_class_data_7(pkt_class_data_7), //OUTPUT : Frame Type Indication
.pkt_class_valid_7(pkt_class_valid_7), //OUTPUT : Frame Type Indication Valid
.data_tx_error_7(data_tx_error_7), //INPUT : Status
.data_tx_data_7(data_tx_data_7), //INPUT : Data from FIFO transmit
.data_tx_valid_7(data_tx_valid_7), //INPUT : Data FIFO transmit Empty
.data_tx_sop_7(data_tx_sop_7), //INPUT : Start of Packet
.data_tx_eop_7(data_tx_eop_7), //INPUT : End of Packet
.data_tx_ready_7(data_tx_ready_7), //OUTPUT : Data FIFO transmit Read Enable
.tx_ff_uflow_7(tx_ff_uflow_7), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
.tx_crc_fwd_7(tx_crc_fwd_7), //INPUT : Forward Current Frame with CRC from Application
.xoff_gen_7(xoff_gen_7), //INPUT : XOFF PAUSE FRAME GENERATE
.xon_gen_7(xon_gen_7), //INPUT : XON PAUSE FRAME GENERATE
.magic_sleep_n_7(magic_sleep_n_7), //INPUT : MAC SLEEP MODE CONTROL
.magic_wakeup_7(magic_wakeup_7), //OUTPUT : MAC WAKE-UP INDICATION
// Channel 8
.rx_carrierdetected_8(pcs_rx_carrierdetected[8]),
.rx_rmfifodatadeleted_8(pcs_rx_rmfifodatadeleted[8]),
.rx_rmfifodatainserted_8(pcs_rx_rmfifodatainserted[8]),
.rx_clkout_8(rx_pcs_clk_c8), //INPUT : Receive Clock
.tx_clkout_8(tx_pcs_clk_c8), //INPUT : Transmit Clock
.rx_kchar_8(pcs_rx_kchar_8), //INPUT : Special Character Indication
.tx_kchar_8(tx_kchar_8), //OUTPUT : Special Character Indication
.rx_frame_8(pcs_rx_frame_8), //INPUT : Frame
.tx_frame_8(tx_frame_8), //OUTPUT : Frame
.sd_loopback_8(sd_loopback_8), //OUTPUT : SERDES Loopback Enable
.powerdown_8(pcs_pwrdn_out_sig[8]), //OUTPUT : Powerdown Enable
.led_col_8(led_col_8), //OUTPUT : Collision Indication
.led_an_8(led_an_8), //OUTPUT : Auto Negotiation Status
.led_char_err_8(led_char_err_gx[8]), //INPUT : Character error
.led_crs_8(led_crs_8), //OUTPUT : Carrier sense
.led_link_8(link_status[8]), //INPUT : Valid link
.mac_rx_clk_8(mac_rx_clk_8), //OUTPUT : Av-ST Rx Clock
.mac_tx_clk_8(mac_tx_clk_8), //OUTPUT : Av-ST Tx Clock
.data_rx_sop_8(data_rx_sop_8), //OUTPUT : Start of Packet
.data_rx_eop_8(data_rx_eop_8), //OUTPUT : End of Packet
.data_rx_data_8(data_rx_data_8), //OUTPUT : Data from FIFO
.data_rx_error_8(data_rx_error_8), //OUTPUT : Receive packet error
.data_rx_valid_8(data_rx_valid_8), //OUTPUT : Data Receive FIFO Valid
.data_rx_ready_8(data_rx_ready_8), //OUTPUT : Data Receive Ready
.pkt_class_data_8(pkt_class_data_8), //OUTPUT : Frame Type Indication
.pkt_class_valid_8(pkt_class_valid_8), //OUTPUT : Frame Type Indication Valid
.data_tx_error_8(data_tx_error_8), //INPUT : Status
.data_tx_data_8(data_tx_data_8), //INPUT : Data from FIFO transmit
.data_tx_valid_8(data_tx_valid_8), //INPUT : Data FIFO transmit Empty
.data_tx_sop_8(data_tx_sop_8), //INPUT : Start of Packet
.data_tx_eop_8(data_tx_eop_8), //INPUT : End of Packet
.data_tx_ready_8(data_tx_ready_8), //OUTPUT : Data FIFO transmit Read Enable
.tx_ff_uflow_8(tx_ff_uflow_8), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
.tx_crc_fwd_8(tx_crc_fwd_8), //INPUT : Forward Current Frame with CRC from Application
.xoff_gen_8(xoff_gen_8), //INPUT : XOFF PAUSE FRAME GENERATE
.xon_gen_8(xon_gen_8), //INPUT : XON PAUSE FRAME GENERATE
.magic_sleep_n_8(magic_sleep_n_8), //INPUT : MAC SLEEP MODE CONTROL
.magic_wakeup_8(magic_wakeup_8), //OUTPUT : MAC WAKE-UP INDICATION
// Channel 9
.rx_carrierdetected_9(pcs_rx_carrierdetected[9]),
.rx_rmfifodatadeleted_9(pcs_rx_rmfifodatadeleted[9]),
.rx_rmfifodatainserted_9(pcs_rx_rmfifodatainserted[9]),
.rx_clkout_9(rx_pcs_clk_c9), //INPUT : Receive Clock
.tx_clkout_9(tx_pcs_clk_c9), //INPUT : Transmit Clock
.rx_kchar_9(pcs_rx_kchar_9), //INPUT : Special Character Indication
.tx_kchar_9(tx_kchar_9), //OUTPUT : Special Character Indication
.rx_frame_9(pcs_rx_frame_9), //INPUT : Frame
.tx_frame_9(tx_frame_9), //OUTPUT : Frame
.sd_loopback_9(sd_loopback_9), //OUTPUT : SERDES Loopback Enable
.powerdown_9(pcs_pwrdn_out_sig[9]), //OUTPUT : Powerdown Enable
.led_col_9(led_col_9), //OUTPUT : Collision Indication
.led_an_9(led_an_9), //OUTPUT : Auto Negotiation Status
.led_char_err_9(led_char_err_gx[9]), //INPUT : Character error
.led_crs_9(led_crs_9), //OUTPUT : Carrier sense
.led_link_9(link_status[9]), //INPUT : Valid link
.mac_rx_clk_9(mac_rx_clk_9), //OUTPUT : Av-ST Rx Clock
.mac_tx_clk_9(mac_tx_clk_9), //OUTPUT : Av-ST Tx Clock
.data_rx_sop_9(data_rx_sop_9), //OUTPUT : Start of Packet
.data_rx_eop_9(data_rx_eop_9), //OUTPUT : End of Packet
.data_rx_data_9(data_rx_data_9), //OUTPUT : Data from FIFO
.data_rx_error_9(data_rx_error_9), //OUTPUT : Receive packet error
.data_rx_valid_9(data_rx_valid_9), //OUTPUT : Data Receive FIFO Valid
.data_rx_ready_9(data_rx_ready_9), //OUTPUT : Data Receive Ready
.pkt_class_data_9(pkt_class_data_9), //OUTPUT : Frame Type Indication
.pkt_class_valid_9(pkt_class_valid_9), //OUTPUT : Frame Type Indication Valid
.data_tx_error_9(data_tx_error_9), //INPUT : Status
.data_tx_data_9(data_tx_data_9), //INPUT : Data from FIFO transmit
.data_tx_valid_9(data_tx_valid_9), //INPUT : Data FIFO transmit Empty
.data_tx_sop_9(data_tx_sop_9), //INPUT : Start of Packet
.data_tx_eop_9(data_tx_eop_9), //INPUT : End of Packet
.data_tx_ready_9(data_tx_ready_9), //OUTPUT : Data FIFO transmit Read Enable
.tx_ff_uflow_9(tx_ff_uflow_9), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
.tx_crc_fwd_9(tx_crc_fwd_9), //INPUT : Forward Current Frame with CRC from Application
.xoff_gen_9(xoff_gen_9), //INPUT : XOFF PAUSE FRAME GENERATE
.xon_gen_9(xon_gen_9), //INPUT : XON PAUSE FRAME GENERATE
.magic_sleep_n_9(magic_sleep_n_9), //INPUT : MAC SLEEP MODE CONTROL
.magic_wakeup_9(magic_wakeup_9), //OUTPUT : MAC WAKE-UP INDICATION
// Channel 10
.rx_carrierdetected_10(pcs_rx_carrierdetected[10]),
.rx_rmfifodatadeleted_10(pcs_rx_rmfifodatadeleted[10]),
.rx_rmfifodatainserted_10(pcs_rx_rmfifodatainserted[10]),
.rx_clkout_10(rx_pcs_clk_c10), //INPUT : Receive Clock
.tx_clkout_10(tx_pcs_clk_c10), //INPUT : Transmit Clock
.rx_kchar_10(pcs_rx_kchar_10), //INPUT : Special Character Indication
.tx_kchar_10(tx_kchar_10), //OUTPUT : Special Character Indication
.rx_frame_10(pcs_rx_frame_10), //INPUT : Frame
.tx_frame_10(tx_frame_10), //OUTPUT : Frame
.sd_loopback_10(sd_loopback_10), //OUTPUT : SERDES Loopback Enable
.powerdown_10(pcs_pwrdn_out_sig[10]), //OUTPUT : Powerdown Enable
.led_col_10(led_col_10), //OUTPUT : Collision Indication
.led_an_10(led_an_10), //OUTPUT : Auto Negotiation Status
.led_char_err_10(led_char_err_gx[10]), //INPUT : Character error
.led_crs_10(led_crs_10), //OUTPUT : Carrier sense
.led_link_10(link_status[10]), //INPUT : Valid link
.mac_rx_clk_10(mac_rx_clk_10), //OUTPUT : Av-ST Rx Clock
.mac_tx_clk_10(mac_tx_clk_10), //OUTPUT : Av-ST Tx Clock
.data_rx_sop_10(data_rx_sop_10), //OUTPUT : Start of Packet
.data_rx_eop_10(data_rx_eop_10), //OUTPUT : End of Packet
.data_rx_data_10(data_rx_data_10), //OUTPUT : Data from FIFO
.data_rx_error_10(data_rx_error_10), //OUTPUT : Receive packet error
.data_rx_valid_10(data_rx_valid_10), //OUTPUT : Data Receive FIFO Valid
.data_rx_ready_10(data_rx_ready_10), //OUTPUT : Data Receive Ready
.pkt_class_data_10(pkt_class_data_10), //OUTPUT : Frame Type Indication
.pkt_class_valid_10(pkt_class_valid_10), //OUTPUT : Frame Type Indication Valid
.data_tx_error_10(data_tx_error_10), //INPUT : Status
.data_tx_data_10(data_tx_data_10), //INPUT : Data from FIFO transmit
.data_tx_valid_10(data_tx_valid_10), //INPUT : Data FIFO transmit Empty
.data_tx_sop_10(data_tx_sop_10), //INPUT : Start of Packet
.data_tx_eop_10(data_tx_eop_10), //INPUT : End of Packet
.data_tx_ready_10(data_tx_ready_10), //OUTPUT : Data FIFO transmit Read Enable
.tx_ff_uflow_10(tx_ff_uflow_10), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
.tx_crc_fwd_10(tx_crc_fwd_10), //INPUT : Forward Current Frame with CRC from Application
.xoff_gen_10(xoff_gen_10), //INPUT : XOFF PAUSE FRAME GENERATE
.xon_gen_10(xon_gen_10), //INPUT : XON PAUSE FRAME GENERATE
.magic_sleep_n_10(magic_sleep_n_10), //INPUT : MAC SLEEP MODE CONTROL
.magic_wakeup_10(magic_wakeup_10), //OUTPUT : MAC WAKE-UP INDICATION
// Channel 11
.rx_carrierdetected_11(pcs_rx_carrierdetected[11]),
.rx_rmfifodatadeleted_11(pcs_rx_rmfifodatadeleted[11]),
.rx_rmfifodatainserted_11(pcs_rx_rmfifodatainserted[11]),
.rx_clkout_11(rx_pcs_clk_c11), //INPUT : Receive Clock
.tx_clkout_11(tx_pcs_clk_c11), //INPUT : Transmit Clock
.rx_kchar_11(pcs_rx_kchar_11), //INPUT : Special Character Indication
.tx_kchar_11(tx_kchar_11), //OUTPUT : Special Character Indication
.rx_frame_11(pcs_rx_frame_11), //INPUT : Frame
.tx_frame_11(tx_frame_11), //OUTPUT : Frame
.sd_loopback_11(sd_loopback_11), //OUTPUT : SERDES Loopback Enable
.powerdown_11(pcs_pwrdn_out_sig[11]), //OUTPUT : Powerdown Enable
.led_col_11(led_col_11), //OUTPUT : Collision Indication
.led_an_11(led_an_11), //OUTPUT : Auto Negotiation Status
.led_char_err_11(led_char_err_gx[11]), //INPUT : Character error
.led_crs_11(led_crs_11), //OUTPUT : Carrier sense
.led_link_11(link_status[11]), //INPUT : Valid link
.mac_rx_clk_11(mac_rx_clk_11), //OUTPUT : Av-ST Rx Clock
.mac_tx_clk_11(mac_tx_clk_11), //OUTPUT : Av-ST Tx Clock
.data_rx_sop_11(data_rx_sop_11), //OUTPUT : Start of Packet
.data_rx_eop_11(data_rx_eop_11), //OUTPUT : End of Packet
.data_rx_data_11(data_rx_data_11), //OUTPUT : Data from FIFO
.data_rx_error_11(data_rx_error_11), //OUTPUT : Receive packet error
.data_rx_valid_11(data_rx_valid_11), //OUTPUT : Data Receive FIFO Valid
.data_rx_ready_11(data_rx_ready_11), //OUTPUT : Data Receive Ready
.pkt_class_data_11(pkt_class_data_11), //OUTPUT : Frame Type Indication
.pkt_class_valid_11(pkt_class_valid_11), //OUTPUT : Frame Type Indication Valid
.data_tx_error_11(data_tx_error_11), //INPUT : Status
.data_tx_data_11(data_tx_data_11), //INPUT : Data from FIFO transmit
.data_tx_valid_11(data_tx_valid_11), //INPUT : Data FIFO transmit Empty
.data_tx_sop_11(data_tx_sop_11), //INPUT : Start of Packet
.data_tx_eop_11(data_tx_eop_11), //INPUT : End of Packet
.data_tx_ready_11(data_tx_ready_11), //OUTPUT : Data FIFO transmit Read Enable
.tx_ff_uflow_11(tx_ff_uflow_11), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
.tx_crc_fwd_11(tx_crc_fwd_11), //INPUT : Forward Current Frame with CRC from Application
.xoff_gen_11(xoff_gen_11), //INPUT : XOFF PAUSE FRAME GENERATE
.xon_gen_11(xon_gen_11), //INPUT : XON PAUSE FRAME GENERATE
.magic_sleep_n_11(magic_sleep_n_11), //INPUT : MAC SLEEP MODE CONTROL
.magic_wakeup_11(magic_wakeup_11), //OUTPUT : MAC WAKE-UP INDICATION
// Channel 12
.rx_carrierdetected_12(pcs_rx_carrierdetected[12]),
.rx_rmfifodatadeleted_12(pcs_rx_rmfifodatadeleted[12]),
.rx_rmfifodatainserted_12(pcs_rx_rmfifodatainserted[12]),
.rx_clkout_12(rx_pcs_clk_c12), //INPUT : Receive Clock
.tx_clkout_12(tx_pcs_clk_c12), //INPUT : Transmit Clock
.rx_kchar_12(pcs_rx_kchar_12), //INPUT : Special Character Indication
.tx_kchar_12(tx_kchar_12), //OUTPUT : Special Character Indication
.rx_frame_12(pcs_rx_frame_12), //INPUT : Frame
.tx_frame_12(tx_frame_12), //OUTPUT : Frame
.sd_loopback_12(sd_loopback_12), //OUTPUT : SERDES Loopback Enable
.powerdown_12(pcs_pwrdn_out_sig[12]), //OUTPUT : Powerdown Enable
.led_col_12(led_col_12), //OUTPUT : Collision Indication
.led_an_12(led_an_12), //OUTPUT : Auto Negotiation Status
.led_char_err_12(led_char_err_gx[12]), //INPUT : Character error
.led_crs_12(led_crs_12), //OUTPUT : Carrier sense
.led_link_12(link_status[12]), //INPUT : Valid link
.mac_rx_clk_12(mac_rx_clk_12), //OUTPUT : Av-ST Rx Clock
.mac_tx_clk_12(mac_tx_clk_12), //OUTPUT : Av-ST Tx Clock
.data_rx_sop_12(data_rx_sop_12), //OUTPUT : Start of Packet
.data_rx_eop_12(data_rx_eop_12), //OUTPUT : End of Packet
.data_rx_data_12(data_rx_data_12), //OUTPUT : Data from FIFO
.data_rx_error_12(data_rx_error_12), //OUTPUT : Receive packet error
.data_rx_valid_12(data_rx_valid_12), //OUTPUT : Data Receive FIFO Valid
.data_rx_ready_12(data_rx_ready_12), //OUTPUT : Data Receive Ready
.pkt_class_data_12(pkt_class_data_12), //OUTPUT : Frame Type Indication
.pkt_class_valid_12(pkt_class_valid_12), //OUTPUT : Frame Type Indication Valid
.data_tx_error_12(data_tx_error_12), //INPUT : Status
.data_tx_data_12(data_tx_data_12), //INPUT : Data from FIFO transmit
.data_tx_valid_12(data_tx_valid_12), //INPUT : Data FIFO transmit Empty
.data_tx_sop_12(data_tx_sop_12), //INPUT : Start of Packet
.data_tx_eop_12(data_tx_eop_12), //INPUT : End of Packet
.data_tx_ready_12(data_tx_ready_12), //OUTPUT : Data FIFO transmit Read Enable
.tx_ff_uflow_12(tx_ff_uflow_12), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
.tx_crc_fwd_12(tx_crc_fwd_12), //INPUT : Forward Current Frame with CRC from Application
.xoff_gen_12(xoff_gen_12), //INPUT : XOFF PAUSE FRAME GENERATE
.xon_gen_12(xon_gen_12), //INPUT : XON PAUSE FRAME GENERATE
.magic_sleep_n_12(magic_sleep_n_12), //INPUT : MAC SLEEP MODE CONTROL
.magic_wakeup_12(magic_wakeup_12), //OUTPUT : MAC WAKE-UP INDICATION
// Channel 13
.rx_carrierdetected_13(pcs_rx_carrierdetected[13]),
.rx_rmfifodatadeleted_13(pcs_rx_rmfifodatadeleted[13]),
.rx_rmfifodatainserted_13(pcs_rx_rmfifodatainserted[13]),
.rx_clkout_13(rx_pcs_clk_c13), //INPUT : Receive Clock
.tx_clkout_13(tx_pcs_clk_c13), //INPUT : Transmit Clock
.rx_kchar_13(pcs_rx_kchar_13), //INPUT : Special Character Indication
.tx_kchar_13(tx_kchar_13), //OUTPUT : Special Character Indication
.rx_frame_13(pcs_rx_frame_13), //INPUT : Frame
.tx_frame_13(tx_frame_13), //OUTPUT : Frame
.sd_loopback_13(sd_loopback_13), //OUTPUT : SERDES Loopback Enable
.powerdown_13(pcs_pwrdn_out_sig[13]), //OUTPUT : Powerdown Enable
.led_col_13(led_col_13), //OUTPUT : Collision Indication
.led_an_13(led_an_13), //OUTPUT : Auto Negotiation Status
.led_char_err_13(led_char_err_gx[13]), //INPUT : Character error
.led_crs_13(led_crs_13), //OUTPUT : Carrier sense
.led_link_13(link_status[13]), //INPUT : Valid link
.mac_rx_clk_13(mac_rx_clk_13), //OUTPUT : Av-ST Rx Clock
.mac_tx_clk_13(mac_tx_clk_13), //OUTPUT : Av-ST Tx Clock
.data_rx_sop_13(data_rx_sop_13), //OUTPUT : Start of Packet
.data_rx_eop_13(data_rx_eop_13), //OUTPUT : End of Packet
.data_rx_data_13(data_rx_data_13), //OUTPUT : Data from FIFO
.data_rx_error_13(data_rx_error_13), //OUTPUT : Receive packet error
.data_rx_valid_13(data_rx_valid_13), //OUTPUT : Data Receive FIFO Valid
.data_rx_ready_13(data_rx_ready_13), //OUTPUT : Data Receive Ready
.pkt_class_data_13(pkt_class_data_13), //OUTPUT : Frame Type Indication
.pkt_class_valid_13(pkt_class_valid_13), //OUTPUT : Frame Type Indication Valid
.data_tx_error_13(data_tx_error_13), //INPUT : Status
.data_tx_data_13(data_tx_data_13), //INPUT : Data from FIFO transmit
.data_tx_valid_13(data_tx_valid_13), //INPUT : Data FIFO transmit Empty
.data_tx_sop_13(data_tx_sop_13), //INPUT : Start of Packet
.data_tx_eop_13(data_tx_eop_13), //INPUT : End of Packet
.data_tx_ready_13(data_tx_ready_13), //OUTPUT : Data FIFO transmit Read Enable
.tx_ff_uflow_13(tx_ff_uflow_13), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
.tx_crc_fwd_13(tx_crc_fwd_13), //INPUT : Forward Current Frame with CRC from Application
.xoff_gen_13(xoff_gen_13), //INPUT : XOFF PAUSE FRAME GENERATE
.xon_gen_13(xon_gen_13), //INPUT : XON PAUSE FRAME GENERATE
.magic_sleep_n_13(magic_sleep_n_13), //INPUT : MAC SLEEP MODE CONTROL
.magic_wakeup_13(magic_wakeup_13), //OUTPUT : MAC WAKE-UP INDICATION
// Channel 14
.rx_carrierdetected_14(pcs_rx_carrierdetected[14]),
.rx_rmfifodatadeleted_14(pcs_rx_rmfifodatadeleted[14]),
.rx_rmfifodatainserted_14(pcs_rx_rmfifodatainserted[14]),
.rx_clkout_14(rx_pcs_clk_c14), //INPUT : Receive Clock
.tx_clkout_14(tx_pcs_clk_c14), //INPUT : Transmit Clock
.rx_kchar_14(pcs_rx_kchar_14), //INPUT : Special Character Indication
.tx_kchar_14(tx_kchar_14), //OUTPUT : Special Character Indication
.rx_frame_14(pcs_rx_frame_14), //INPUT : Frame
.tx_frame_14(tx_frame_14), //OUTPUT : Frame
.sd_loopback_14(sd_loopback_14), //OUTPUT : SERDES Loopback Enable
.powerdown_14(pcs_pwrdn_out_sig[14]), //OUTPUT : Powerdown Enable
.led_col_14(led_col_14), //OUTPUT : Collision Indication
.led_an_14(led_an_14), //OUTPUT : Auto Negotiation Status
.led_char_err_14(led_char_err_gx[14]), //INPUT : Character error
.led_crs_14(led_crs_14), //OUTPUT : Carrier sense
.led_link_14(link_status[14]), //INPUT : Valid link
.mac_rx_clk_14(mac_rx_clk_14), //OUTPUT : Av-ST Rx Clock
.mac_tx_clk_14(mac_tx_clk_14), //OUTPUT : Av-ST Tx Clock
.data_rx_sop_14(data_rx_sop_14), //OUTPUT : Start of Packet
.data_rx_eop_14(data_rx_eop_14), //OUTPUT : End of Packet
.data_rx_data_14(data_rx_data_14), //OUTPUT : Data from FIFO
.data_rx_error_14(data_rx_error_14), //OUTPUT : Receive packet error
.data_rx_valid_14(data_rx_valid_14), //OUTPUT : Data Receive FIFO Valid
.data_rx_ready_14(data_rx_ready_14), //OUTPUT : Data Receive Ready
.pkt_class_data_14(pkt_class_data_14), //OUTPUT : Frame Type Indication
.pkt_class_valid_14(pkt_class_valid_14), //OUTPUT : Frame Type Indication Valid
.data_tx_error_14(data_tx_error_14), //INPUT : Status
.data_tx_data_14(data_tx_data_14), //INPUT : Data from FIFO transmit
.data_tx_valid_14(data_tx_valid_14), //INPUT : Data FIFO transmit Empty
.data_tx_sop_14(data_tx_sop_14), //INPUT : Start of Packet
.data_tx_eop_14(data_tx_eop_14), //INPUT : End of Packet
.data_tx_ready_14(data_tx_ready_14), //OUTPUT : Data FIFO transmit Read Enable
.tx_ff_uflow_14(tx_ff_uflow_14), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
.tx_crc_fwd_14(tx_crc_fwd_14), //INPUT : Forward Current Frame with CRC from Application
.xoff_gen_14(xoff_gen_14), //INPUT : XOFF PAUSE FRAME GENERATE
.xon_gen_14(xon_gen_14), //INPUT : XON PAUSE FRAME GENERATE
.magic_sleep_n_14(magic_sleep_n_14), //INPUT : MAC SLEEP MODE CONTROL
.magic_wakeup_14(magic_wakeup_14), //OUTPUT : MAC WAKE-UP INDICATION
// Channel 15
.rx_carrierdetected_15(pcs_rx_carrierdetected[15]),
.rx_rmfifodatadeleted_15(pcs_rx_rmfifodatadeleted[15]),
.rx_rmfifodatainserted_15(pcs_rx_rmfifodatainserted[15]),
.rx_clkout_15(rx_pcs_clk_c15), //INPUT : Receive Clock
.tx_clkout_15(tx_pcs_clk_c15), //INPUT : Transmit Clock
.rx_kchar_15(pcs_rx_kchar_15), //INPUT : Special Character Indication
.tx_kchar_15(tx_kchar_15), //OUTPUT : Special Character Indication
.rx_frame_15(pcs_rx_frame_15), //INPUT : Frame
.tx_frame_15(tx_frame_15), //OUTPUT : Frame
.sd_loopback_15(sd_loopback_15), //OUTPUT : SERDES Loopback Enable
.powerdown_15(pcs_pwrdn_out_sig[15]), //OUTPUT : Powerdown Enable
.led_col_15(led_col_15), //OUTPUT : Collision Indication
.led_an_15(led_an_15), //OUTPUT : Auto Negotiation Status
.led_char_err_15(led_char_err_gx[15]), //INPUT : Character error
.led_crs_15(led_crs_15), //OUTPUT : Carrier sense
.led_link_15(link_status[15]), //INPUT : Valid link
.mac_rx_clk_15(mac_rx_clk_15), //OUTPUT : Av-ST Rx Clock
.mac_tx_clk_15(mac_tx_clk_15), //OUTPUT : Av-ST Tx Clock
.data_rx_sop_15(data_rx_sop_15), //OUTPUT : Start of Packet
.data_rx_eop_15(data_rx_eop_15), //OUTPUT : End of Packet
.data_rx_data_15(data_rx_data_15), //OUTPUT : Data from FIFO
.data_rx_error_15(data_rx_error_15), //OUTPUT : Receive packet error
.data_rx_valid_15(data_rx_valid_15), //OUTPUT : Data Receive FIFO Valid
.data_rx_ready_15(data_rx_ready_15), //OUTPUT : Data Receive Ready
.pkt_class_data_15(pkt_class_data_15), //OUTPUT : Frame Type Indication
.pkt_class_valid_15(pkt_class_valid_15), //OUTPUT : Frame Type Indication Valid
.data_tx_error_15(data_tx_error_15), //INPUT : Status
.data_tx_data_15(data_tx_data_15), //INPUT : Data from FIFO transmit
.data_tx_valid_15(data_tx_valid_15), //INPUT : Data FIFO transmit Empty
.data_tx_sop_15(data_tx_sop_15), //INPUT : Start of Packet
.data_tx_eop_15(data_tx_eop_15), //INPUT : End of Packet
.data_tx_ready_15(data_tx_ready_15), //OUTPUT : Data FIFO transmit Read Enable
.tx_ff_uflow_15(tx_ff_uflow_15), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
.tx_crc_fwd_15(tx_crc_fwd_15), //INPUT : Forward Current Frame with CRC from Application
.xoff_gen_15(xoff_gen_15), //INPUT : XOFF PAUSE FRAME GENERATE
.xon_gen_15(xon_gen_15), //INPUT : XON PAUSE FRAME GENERATE
.magic_sleep_n_15(magic_sleep_n_15), //INPUT : MAC SLEEP MODE CONTROL
.magic_wakeup_15(magic_wakeup_15), //OUTPUT : MAC WAKE-UP INDICATION
// Channel 16
.rx_carrierdetected_16(pcs_rx_carrierdetected[16]),
.rx_rmfifodatadeleted_16(pcs_rx_rmfifodatadeleted[16]),
.rx_rmfifodatainserted_16(pcs_rx_rmfifodatainserted[16]),
.rx_clkout_16(rx_pcs_clk_c16), //INPUT : Receive Clock
.tx_clkout_16(tx_pcs_clk_c16), //INPUT : Transmit Clock
.rx_kchar_16(pcs_rx_kchar_16), //INPUT : Special Character Indication
.tx_kchar_16(tx_kchar_16), //OUTPUT : Special Character Indication
.rx_frame_16(pcs_rx_frame_16), //INPUT : Frame
.tx_frame_16(tx_frame_16), //OUTPUT : Frame
.sd_loopback_16(sd_loopback_16), //OUTPUT : SERDES Loopback Enable
.powerdown_16(pcs_pwrdn_out_sig[16]), //OUTPUT : Powerdown Enable
.led_col_16(led_col_16), //OUTPUT : Collision Indication
.led_an_16(led_an_16), //OUTPUT : Auto Negotiation Status
.led_char_err_16(led_char_err_gx[16]), //INPUT : Character error
.led_crs_16(led_crs_16), //OUTPUT : Carrier sense
.led_link_16(link_status[16]), //INPUT : Valid link
.mac_rx_clk_16(mac_rx_clk_16), //OUTPUT : Av-ST Rx Clock
.mac_tx_clk_16(mac_tx_clk_16), //OUTPUT : Av-ST Tx Clock
.data_rx_sop_16(data_rx_sop_16), //OUTPUT : Start of Packet
.data_rx_eop_16(data_rx_eop_16), //OUTPUT : End of Packet
.data_rx_data_16(data_rx_data_16), //OUTPUT : Data from FIFO
.data_rx_error_16(data_rx_error_16), //OUTPUT : Receive packet error
.data_rx_valid_16(data_rx_valid_16), //OUTPUT : Data Receive FIFO Valid
.data_rx_ready_16(data_rx_ready_16), //OUTPUT : Data Receive Ready
.pkt_class_data_16(pkt_class_data_16), //OUTPUT : Frame Type Indication
.pkt_class_valid_16(pkt_class_valid_16), //OUTPUT : Frame Type Indication Valid
.data_tx_error_16(data_tx_error_16), //INPUT : Status
.data_tx_data_16(data_tx_data_16), //INPUT : Data from FIFO transmit
.data_tx_valid_16(data_tx_valid_16), //INPUT : Data FIFO transmit Empty
.data_tx_sop_16(data_tx_sop_16), //INPUT : Start of Packet
.data_tx_eop_16(data_tx_eop_16), //INPUT : End of Packet
.data_tx_ready_16(data_tx_ready_16), //OUTPUT : Data FIFO transmit Read Enable
.tx_ff_uflow_16(tx_ff_uflow_16), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
.tx_crc_fwd_16(tx_crc_fwd_16), //INPUT : Forward Current Frame with CRC from Application
.xoff_gen_16(xoff_gen_16), //INPUT : XOFF PAUSE FRAME GENERATE
.xon_gen_16(xon_gen_16), //INPUT : XON PAUSE FRAME GENERATE
.magic_sleep_n_16(magic_sleep_n_16), //INPUT : MAC SLEEP MODE CONTROL
.magic_wakeup_16(magic_wakeup_16), //OUTPUT : MAC WAKE-UP INDICATION
// Channel 17
.rx_carrierdetected_17(pcs_rx_carrierdetected[17]),
.rx_rmfifodatadeleted_17(pcs_rx_rmfifodatadeleted[17]),
.rx_rmfifodatainserted_17(pcs_rx_rmfifodatainserted[17]),
.rx_clkout_17(rx_pcs_clk_c17), //INPUT : Receive Clock
.tx_clkout_17(tx_pcs_clk_c17), //INPUT : Transmit Clock
.rx_kchar_17(pcs_rx_kchar_17), //INPUT : Special Character Indication
.tx_kchar_17(tx_kchar_17), //OUTPUT : Special Character Indication
.rx_frame_17(pcs_rx_frame_17), //INPUT : Frame
.tx_frame_17(tx_frame_17), //OUTPUT : Frame
.sd_loopback_17(sd_loopback_17), //OUTPUT : SERDES Loopback Enable
.powerdown_17(pcs_pwrdn_out_sig[17]), //OUTPUT : Powerdown Enable
.led_col_17(led_col_17), //OUTPUT : Collision Indication
.led_an_17(led_an_17), //OUTPUT : Auto Negotiation Status
.led_char_err_17(led_char_err_gx[17]), //INPUT : Character error
.led_crs_17(led_crs_17), //OUTPUT : Carrier sense
.led_link_17(link_status[17]), //INPUT : Valid link
.mac_rx_clk_17(mac_rx_clk_17), //OUTPUT : Av-ST Rx Clock
.mac_tx_clk_17(mac_tx_clk_17), //OUTPUT : Av-ST Tx Clock
.data_rx_sop_17(data_rx_sop_17), //OUTPUT : Start of Packet
.data_rx_eop_17(data_rx_eop_17), //OUTPUT : End of Packet
.data_rx_data_17(data_rx_data_17), //OUTPUT : Data from FIFO
.data_rx_error_17(data_rx_error_17), //OUTPUT : Receive packet error
.data_rx_valid_17(data_rx_valid_17), //OUTPUT : Data Receive FIFO Valid
.data_rx_ready_17(data_rx_ready_17), //OUTPUT : Data Receive Ready
.pkt_class_data_17(pkt_class_data_17), //OUTPUT : Frame Type Indication
.pkt_class_valid_17(pkt_class_valid_17), //OUTPUT : Frame Type Indication Valid
.data_tx_error_17(data_tx_error_17), //INPUT : Status
.data_tx_data_17(data_tx_data_17), //INPUT : Data from FIFO transmit
.data_tx_valid_17(data_tx_valid_17), //INPUT : Data FIFO transmit Empty
.data_tx_sop_17(data_tx_sop_17), //INPUT : Start of Packet
.data_tx_eop_17(data_tx_eop_17), //INPUT : End of Packet
.data_tx_ready_17(data_tx_ready_17), //OUTPUT : Data FIFO transmit Read Enable
.tx_ff_uflow_17(tx_ff_uflow_17), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
.tx_crc_fwd_17(tx_crc_fwd_17), //INPUT : Forward Current Frame with CRC from Application
.xoff_gen_17(xoff_gen_17), //INPUT : XOFF PAUSE FRAME GENERATE
.xon_gen_17(xon_gen_17), //INPUT : XON PAUSE FRAME GENERATE
.magic_sleep_n_17(magic_sleep_n_17), //INPUT : MAC SLEEP MODE CONTROL
.magic_wakeup_17(magic_wakeup_17), //OUTPUT : MAC WAKE-UP INDICATION
// Channel 18
.rx_carrierdetected_18(pcs_rx_carrierdetected[18]),
.rx_rmfifodatadeleted_18(pcs_rx_rmfifodatadeleted[18]),
.rx_rmfifodatainserted_18(pcs_rx_rmfifodatainserted[18]),
.rx_clkout_18(rx_pcs_clk_c18), //INPUT : Receive Clock
.tx_clkout_18(tx_pcs_clk_c18), //INPUT : Transmit Clock
.rx_kchar_18(pcs_rx_kchar_18), //INPUT : Special Character Indication
.tx_kchar_18(tx_kchar_18), //OUTPUT : Special Character Indication
.rx_frame_18(pcs_rx_frame_18), //INPUT : Frame
.tx_frame_18(tx_frame_18), //OUTPUT : Frame
.sd_loopback_18(sd_loopback_18), //OUTPUT : SERDES Loopback Enable
.powerdown_18(pcs_pwrdn_out_sig[18]), //OUTPUT : Powerdown Enable
.led_col_18(led_col_18), //OUTPUT : Collision Indication
.led_an_18(led_an_18), //OUTPUT : Auto Negotiation Status
.led_char_err_18(led_char_err_gx[18]), //INPUT : Character error
.led_crs_18(led_crs_18), //OUTPUT : Carrier sense
.led_link_18(link_status[18]), //INPUT : Valid link
.mac_rx_clk_18(mac_rx_clk_18), //OUTPUT : Av-ST Rx Clock
.mac_tx_clk_18(mac_tx_clk_18), //OUTPUT : Av-ST Tx Clock
.data_rx_sop_18(data_rx_sop_18), //OUTPUT : Start of Packet
.data_rx_eop_18(data_rx_eop_18), //OUTPUT : End of Packet
.data_rx_data_18(data_rx_data_18), //OUTPUT : Data from FIFO
.data_rx_error_18(data_rx_error_18), //OUTPUT : Receive packet error
.data_rx_valid_18(data_rx_valid_18), //OUTPUT : Data Receive FIFO Valid
.data_rx_ready_18(data_rx_ready_18), //OUTPUT : Data Receive Ready
.pkt_class_data_18(pkt_class_data_18), //OUTPUT : Frame Type Indication
.pkt_class_valid_18(pkt_class_valid_18), //OUTPUT : Frame Type Indication Valid
.data_tx_error_18(data_tx_error_18), //INPUT : Status
.data_tx_data_18(data_tx_data_18), //INPUT : Data from FIFO transmit
.data_tx_valid_18(data_tx_valid_18), //INPUT : Data FIFO transmit Empty
.data_tx_sop_18(data_tx_sop_18), //INPUT : Start of Packet
.data_tx_eop_18(data_tx_eop_18), //INPUT : End of Packet
.data_tx_ready_18(data_tx_ready_18), //OUTPUT : Data FIFO transmit Read Enable
.tx_ff_uflow_18(tx_ff_uflow_18), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
.tx_crc_fwd_18(tx_crc_fwd_18), //INPUT : Forward Current Frame with CRC from Application
.xoff_gen_18(xoff_gen_18), //INPUT : XOFF PAUSE FRAME GENERATE
.xon_gen_18(xon_gen_18), //INPUT : XON PAUSE FRAME GENERATE
.magic_sleep_n_18(magic_sleep_n_18), //INPUT : MAC SLEEP MODE CONTROL
.magic_wakeup_18(magic_wakeup_18), //OUTPUT : MAC WAKE-UP INDICATION
// Channel 19
.rx_carrierdetected_19(pcs_rx_carrierdetected[19]),
.rx_rmfifodatadeleted_19(pcs_rx_rmfifodatadeleted[19]),
.rx_rmfifodatainserted_19(pcs_rx_rmfifodatainserted[19]),
.rx_clkout_19(rx_pcs_clk_c19), //INPUT : Receive Clock
.tx_clkout_19(tx_pcs_clk_c19), //INPUT : Transmit Clock
.rx_kchar_19(pcs_rx_kchar_19), //INPUT : Special Character Indication
.tx_kchar_19(tx_kchar_19), //OUTPUT : Special Character Indication
.rx_frame_19(pcs_rx_frame_19), //INPUT : Frame
.tx_frame_19(tx_frame_19), //OUTPUT : Frame
.sd_loopback_19(sd_loopback_19), //OUTPUT : SERDES Loopback Enable
.powerdown_19(pcs_pwrdn_out_sig[19]), //OUTPUT : Powerdown Enable
.led_col_19(led_col_19), //OUTPUT : Collision Indication
.led_an_19(led_an_19), //OUTPUT : Auto Negotiation Status
.led_char_err_19(led_char_err_gx[19]), //INPUT : Character error
.led_crs_19(led_crs_19), //OUTPUT : Carrier sense
.led_link_19(link_status[19]), //INPUT : Valid link
.mac_rx_clk_19(mac_rx_clk_19), //OUTPUT : Av-ST Rx Clock
.mac_tx_clk_19(mac_tx_clk_19), //OUTPUT : Av-ST Tx Clock
.data_rx_sop_19(data_rx_sop_19), //OUTPUT : Start of Packet
.data_rx_eop_19(data_rx_eop_19), //OUTPUT : End of Packet
.data_rx_data_19(data_rx_data_19), //OUTPUT : Data from FIFO
.data_rx_error_19(data_rx_error_19), //OUTPUT : Receive packet error
.data_rx_valid_19(data_rx_valid_19), //OUTPUT : Data Receive FIFO Valid
.data_rx_ready_19(data_rx_ready_19), //OUTPUT : Data Receive Ready
.pkt_class_data_19(pkt_class_data_19), //OUTPUT : Frame Type Indication
.pkt_class_valid_19(pkt_class_valid_19), //OUTPUT : Frame Type Indication Valid
.data_tx_error_19(data_tx_error_19), //INPUT : Status
.data_tx_data_19(data_tx_data_19), //INPUT : Data from FIFO transmit
.data_tx_valid_19(data_tx_valid_19), //INPUT : Data FIFO transmit Empty
.data_tx_sop_19(data_tx_sop_19), //INPUT : Start of Packet
.data_tx_eop_19(data_tx_eop_19), //INPUT : End of Packet
.data_tx_ready_19(data_tx_ready_19), //OUTPUT : Data FIFO transmit Read Enable
.tx_ff_uflow_19(tx_ff_uflow_19), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
.tx_crc_fwd_19(tx_crc_fwd_19), //INPUT : Forward Current Frame with CRC from Application
.xoff_gen_19(xoff_gen_19), //INPUT : XOFF PAUSE FRAME GENERATE
.xon_gen_19(xon_gen_19), //INPUT : XON PAUSE FRAME GENERATE
.magic_sleep_n_19(magic_sleep_n_19), //INPUT : MAC SLEEP MODE CONTROL
.magic_wakeup_19(magic_wakeup_19), //OUTPUT : MAC WAKE-UP INDICATION
// Channel 20
.rx_carrierdetected_20(pcs_rx_carrierdetected[20]),
.rx_rmfifodatadeleted_20(pcs_rx_rmfifodatadeleted[20]),
.rx_rmfifodatainserted_20(pcs_rx_rmfifodatainserted[20]),
.rx_clkout_20(rx_pcs_clk_c20), //INPUT : Receive Clock
.tx_clkout_20(tx_pcs_clk_c20), //INPUT : Transmit Clock
.rx_kchar_20(pcs_rx_kchar_20), //INPUT : Special Character Indication
.tx_kchar_20(tx_kchar_20), //OUTPUT : Special Character Indication
.rx_frame_20(pcs_rx_frame_20), //INPUT : Frame
.tx_frame_20(tx_frame_20), //OUTPUT : Frame
.sd_loopback_20(sd_loopback_20), //OUTPUT : SERDES Loopback Enable
.powerdown_20(pcs_pwrdn_out_sig[20]), //OUTPUT : Powerdown Enable
.led_col_20(led_col_20), //OUTPUT : Collision Indication
.led_an_20(led_an_20), //OUTPUT : Auto Negotiation Status
.led_char_err_20(led_char_err_gx[20]), //INPUT : Character error
.led_crs_20(led_crs_20), //OUTPUT : Carrier sense
.led_link_20(link_status[20]), //INPUT : Valid link
.mac_rx_clk_20(mac_rx_clk_20), //OUTPUT : Av-ST Rx Clock
.mac_tx_clk_20(mac_tx_clk_20), //OUTPUT : Av-ST Tx Clock
.data_rx_sop_20(data_rx_sop_20), //OUTPUT : Start of Packet
.data_rx_eop_20(data_rx_eop_20), //OUTPUT : End of Packet
.data_rx_data_20(data_rx_data_20), //OUTPUT : Data from FIFO
.data_rx_error_20(data_rx_error_20), //OUTPUT : Receive packet error
.data_rx_valid_20(data_rx_valid_20), //OUTPUT : Data Receive FIFO Valid
.data_rx_ready_20(data_rx_ready_20), //OUTPUT : Data Receive Ready
.pkt_class_data_20(pkt_class_data_20), //OUTPUT : Frame Type Indication
.pkt_class_valid_20(pkt_class_valid_20), //OUTPUT : Frame Type Indication Valid
.data_tx_error_20(data_tx_error_20), //INPUT : Status
.data_tx_data_20(data_tx_data_20), //INPUT : Data from FIFO transmit
.data_tx_valid_20(data_tx_valid_20), //INPUT : Data FIFO transmit Empty
.data_tx_sop_20(data_tx_sop_20), //INPUT : Start of Packet
.data_tx_eop_20(data_tx_eop_20), //INPUT : End of Packet
.data_tx_ready_20(data_tx_ready_20), //OUTPUT : Data FIFO transmit Read Enable
.tx_ff_uflow_20(tx_ff_uflow_20), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
.tx_crc_fwd_20(tx_crc_fwd_20), //INPUT : Forward Current Frame with CRC from Application
.xoff_gen_20(xoff_gen_20), //INPUT : XOFF PAUSE FRAME GENERATE
.xon_gen_20(xon_gen_20), //INPUT : XON PAUSE FRAME GENERATE
.magic_sleep_n_20(magic_sleep_n_20), //INPUT : MAC SLEEP MODE CONTROL
.magic_wakeup_20(magic_wakeup_20), //OUTPUT : MAC WAKE-UP INDICATION
// Channel 21
.rx_carrierdetected_21(pcs_rx_carrierdetected[21]),
.rx_rmfifodatadeleted_21(pcs_rx_rmfifodatadeleted[21]),
.rx_rmfifodatainserted_21(pcs_rx_rmfifodatainserted[21]),
.rx_clkout_21(rx_pcs_clk_c21), //INPUT : Receive Clock
.tx_clkout_21(tx_pcs_clk_c21), //INPUT : Transmit Clock
.rx_kchar_21(pcs_rx_kchar_21), //INPUT : Special Character Indication
.tx_kchar_21(tx_kchar_21), //OUTPUT : Special Character Indication
.rx_frame_21(pcs_rx_frame_21), //INPUT : Frame
.tx_frame_21(tx_frame_21), //OUTPUT : Frame
.sd_loopback_21(sd_loopback_21), //OUTPUT : SERDES Loopback Enable
.powerdown_21(pcs_pwrdn_out_sig[21]), //OUTPUT : Powerdown Enable
.led_col_21(led_col_21), //OUTPUT : Collision Indication
.led_an_21(led_an_21), //OUTPUT : Auto Negotiation Status
.led_char_err_21(led_char_err_gx[21]), //INPUT : Character error
.led_crs_21(led_crs_21), //OUTPUT : Carrier sense
.led_link_21(link_status[21]), //INPUT : Valid link
.mac_rx_clk_21(mac_rx_clk_21), //OUTPUT : Av-ST Rx Clock
.mac_tx_clk_21(mac_tx_clk_21), //OUTPUT : Av-ST Tx Clock
.data_rx_sop_21(data_rx_sop_21), //OUTPUT : Start of Packet
.data_rx_eop_21(data_rx_eop_21), //OUTPUT : End of Packet
.data_rx_data_21(data_rx_data_21), //OUTPUT : Data from FIFO
.data_rx_error_21(data_rx_error_21), //OUTPUT : Receive packet error
.data_rx_valid_21(data_rx_valid_21), //OUTPUT : Data Receive FIFO Valid
.data_rx_ready_21(data_rx_ready_21), //OUTPUT : Data Receive Ready
.pkt_class_data_21(pkt_class_data_21), //OUTPUT : Frame Type Indication
.pkt_class_valid_21(pkt_class_valid_21), //OUTPUT : Frame Type Indication Valid
.data_tx_error_21(data_tx_error_21), //INPUT : Status
.data_tx_data_21(data_tx_data_21), //INPUT : Data from FIFO transmit
.data_tx_valid_21(data_tx_valid_21), //INPUT : Data FIFO transmit Empty
.data_tx_sop_21(data_tx_sop_21), //INPUT : Start of Packet
.data_tx_eop_21(data_tx_eop_21), //INPUT : End of Packet
.data_tx_ready_21(data_tx_ready_21), //OUTPUT : Data FIFO transmit Read Enable
.tx_ff_uflow_21(tx_ff_uflow_21), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
.tx_crc_fwd_21(tx_crc_fwd_21), //INPUT : Forward Current Frame with CRC from Application
.xoff_gen_21(xoff_gen_21), //INPUT : XOFF PAUSE FRAME GENERATE
.xon_gen_21(xon_gen_21), //INPUT : XON PAUSE FRAME GENERATE
.magic_sleep_n_21(magic_sleep_n_21), //INPUT : MAC SLEEP MODE CONTROL
.magic_wakeup_21(magic_wakeup_21), //OUTPUT : MAC WAKE-UP INDICATION
// Channel 22
.rx_carrierdetected_22(pcs_rx_carrierdetected[22]),
.rx_rmfifodatadeleted_22(pcs_rx_rmfifodatadeleted[22]),
.rx_rmfifodatainserted_22(pcs_rx_rmfifodatainserted[22]),
.rx_clkout_22(rx_pcs_clk_c22), //INPUT : Receive Clock
.tx_clkout_22(tx_pcs_clk_c22), //INPUT : Transmit Clock
.rx_kchar_22(pcs_rx_kchar_22), //INPUT : Special Character Indication
.tx_kchar_22(tx_kchar_22), //OUTPUT : Special Character Indication
.rx_frame_22(pcs_rx_frame_22), //INPUT : Frame
.tx_frame_22(tx_frame_22), //OUTPUT : Frame
.sd_loopback_22(sd_loopback_22), //OUTPUT : SERDES Loopback Enable
.powerdown_22(pcs_pwrdn_out_sig[22]), //OUTPUT : Powerdown Enable
.led_col_22(led_col_22), //OUTPUT : Collision Indication
.led_an_22(led_an_22), //OUTPUT : Auto Negotiation Status
.led_char_err_22(led_char_err_gx[22]), //INPUT : Character error
.led_crs_22(led_crs_22), //OUTPUT : Carrier sense
.led_link_22(link_status[22]), //INPUT : Valid link
.mac_rx_clk_22(mac_rx_clk_22), //OUTPUT : Av-ST Rx Clock
.mac_tx_clk_22(mac_tx_clk_22), //OUTPUT : Av-ST Tx Clock
.data_rx_sop_22(data_rx_sop_22), //OUTPUT : Start of Packet
.data_rx_eop_22(data_rx_eop_22), //OUTPUT : End of Packet
.data_rx_data_22(data_rx_data_22), //OUTPUT : Data from FIFO
.data_rx_error_22(data_rx_error_22), //OUTPUT : Receive packet error
.data_rx_valid_22(data_rx_valid_22), //OUTPUT : Data Receive FIFO Valid
.data_rx_ready_22(data_rx_ready_22), //OUTPUT : Data Receive Ready
.pkt_class_data_22(pkt_class_data_22), //OUTPUT : Frame Type Indication
.pkt_class_valid_22(pkt_class_valid_22), //OUTPUT : Frame Type Indication Valid
.data_tx_error_22(data_tx_error_22), //INPUT : Status
.data_tx_data_22(data_tx_data_22), //INPUT : Data from FIFO transmit
.data_tx_valid_22(data_tx_valid_22), //INPUT : Data FIFO transmit Empty
.data_tx_sop_22(data_tx_sop_22), //INPUT : Start of Packet
.data_tx_eop_22(data_tx_eop_22), //INPUT : End of Packet
.data_tx_ready_22(data_tx_ready_22), //OUTPUT : Data FIFO transmit Read Enable
.tx_ff_uflow_22(tx_ff_uflow_22), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
.tx_crc_fwd_22(tx_crc_fwd_22), //INPUT : Forward Current Frame with CRC from Application
.xoff_gen_22(xoff_gen_22), //INPUT : XOFF PAUSE FRAME GENERATE
.xon_gen_22(xon_gen_22), //INPUT : XON PAUSE FRAME GENERATE
.magic_sleep_n_22(magic_sleep_n_22), //INPUT : MAC SLEEP MODE CONTROL
.magic_wakeup_22(magic_wakeup_22), //OUTPUT : MAC WAKE-UP INDICATION
// Channel 23
.rx_carrierdetected_23(pcs_rx_carrierdetected[23]),
.rx_rmfifodatadeleted_23(pcs_rx_rmfifodatadeleted[23]),
.rx_rmfifodatainserted_23(pcs_rx_rmfifodatainserted[23]),
.rx_clkout_23(rx_pcs_clk_c23), //INPUT : Receive Clock
.tx_clkout_23(tx_pcs_clk_c23), //INPUT : Transmit Clock
.rx_kchar_23(pcs_rx_kchar_23), //INPUT : Special Character Indication
.tx_kchar_23(tx_kchar_23), //OUTPUT : Special Character Indication
.rx_frame_23(pcs_rx_frame_23), //INPUT : Frame
.tx_frame_23(tx_frame_23), //OUTPUT : Frame
.sd_loopback_23(sd_loopback_23), //OUTPUT : SERDES Loopback Enable
.powerdown_23(pcs_pwrdn_out_sig[23]), //OUTPUT : Powerdown Enable
.led_col_23(led_col_23), //OUTPUT : Collision Indication
.led_an_23(led_an_23), //OUTPUT : Auto Negotiation Status
.led_char_err_23(led_char_err_gx[23]), //INPUT : Character error
.led_crs_23(led_crs_23), //OUTPUT : Carrier sense
.led_link_23(link_status[23]), //INPUT : Valid link
.mac_rx_clk_23(mac_rx_clk_23), //OUTPUT : Av-ST Rx Clock
.mac_tx_clk_23(mac_tx_clk_23), //OUTPUT : Av-ST Tx Clock
.data_rx_sop_23(data_rx_sop_23), //OUTPUT : Start of Packet
.data_rx_eop_23(data_rx_eop_23), //OUTPUT : End of Packet
.data_rx_data_23(data_rx_data_23), //OUTPUT : Data from FIFO
.data_rx_error_23(data_rx_error_23), //OUTPUT : Receive packet error
.data_rx_valid_23(data_rx_valid_23), //OUTPUT : Data Receive FIFO Valid
.data_rx_ready_23(data_rx_ready_23), //OUTPUT : Data Receive Ready
.pkt_class_data_23(pkt_class_data_23), //OUTPUT : Frame Type Indication
.pkt_class_valid_23(pkt_class_valid_23), //OUTPUT : Frame Type Indication Valid
.data_tx_error_23(data_tx_error_23), //INPUT : Status
.data_tx_data_23(data_tx_data_23), //INPUT : Data from FIFO transmit
.data_tx_valid_23(data_tx_valid_23), //INPUT : Data FIFO transmit Empty
.data_tx_sop_23(data_tx_sop_23), //INPUT : Start of Packet
.data_tx_eop_23(data_tx_eop_23), //INPUT : End of Packet
.data_tx_ready_23(data_tx_ready_23), //OUTPUT : Data FIFO transmit Read Enable
.tx_ff_uflow_23(tx_ff_uflow_23), //OUTPUT : TX FIFO underflow occured (Synchronous with tx_clk)
.tx_crc_fwd_23(tx_crc_fwd_23), //INPUT : Forward Current Frame with CRC from Application
.xoff_gen_23(xoff_gen_23), //INPUT : XOFF PAUSE FRAME GENERATE
.xon_gen_23(xon_gen_23), //INPUT : XON PAUSE FRAME GENERATE
.magic_sleep_n_23(magic_sleep_n_23), //INPUT : MAC SLEEP MODE CONTROL
.magic_wakeup_23(magic_wakeup_23)); //OUTPUT : MAC WAKE-UP INDICATION
defparam
U_MULTI_MAC_PCS.USE_SYNC_RESET = USE_SYNC_RESET,
U_MULTI_MAC_PCS.RESET_LEVEL = RESET_LEVEL,
U_MULTI_MAC_PCS.ENABLE_GMII_LOOPBACK = ENABLE_GMII_LOOPBACK,
U_MULTI_MAC_PCS.ENABLE_HD_LOGIC = ENABLE_HD_LOGIC,
U_MULTI_MAC_PCS.ENABLE_SUP_ADDR = ENABLE_SUP_ADDR,
U_MULTI_MAC_PCS.ENA_HASH = ENA_HASH,
U_MULTI_MAC_PCS.STAT_CNT_ENA = STAT_CNT_ENA,
U_MULTI_MAC_PCS.CORE_VERSION = CORE_VERSION,
U_MULTI_MAC_PCS.CUST_VERSION = CUST_VERSION,
U_MULTI_MAC_PCS.REDUCED_INTERFACE_ENA = REDUCED_INTERFACE_ENA,
U_MULTI_MAC_PCS.ENABLE_MDIO = ENABLE_MDIO,
U_MULTI_MAC_PCS.MDIO_CLK_DIV = MDIO_CLK_DIV,
U_MULTI_MAC_PCS.ENABLE_MAGIC_DETECT = ENABLE_MAGIC_DETECT,
U_MULTI_MAC_PCS.ENABLE_PADDING = ENABLE_PADDING,
U_MULTI_MAC_PCS.ENABLE_LGTH_CHECK = ENABLE_LGTH_CHECK,
U_MULTI_MAC_PCS.GBIT_ONLY = GBIT_ONLY,
U_MULTI_MAC_PCS.MBIT_ONLY = MBIT_ONLY,
U_MULTI_MAC_PCS.REDUCED_CONTROL = REDUCED_CONTROL,
U_MULTI_MAC_PCS.CRC32DWIDTH = CRC32DWIDTH,
U_MULTI_MAC_PCS.CRC32GENDELAY = CRC32GENDELAY,
U_MULTI_MAC_PCS.CRC32CHECK16BIT = CRC32CHECK16BIT,
U_MULTI_MAC_PCS.CRC32S1L2_EXTERN = CRC32S1L2_EXTERN,
U_MULTI_MAC_PCS.ENABLE_SHIFT16 = ENABLE_SHIFT16,
U_MULTI_MAC_PCS.ENABLE_MAC_FLOW_CTRL = ENABLE_MAC_FLOW_CTRL,
U_MULTI_MAC_PCS.ENABLE_MAC_TXADDR_SET = ENABLE_MAC_TXADDR_SET,
U_MULTI_MAC_PCS.ENABLE_MAC_RX_VLAN = ENABLE_MAC_RX_VLAN,
U_MULTI_MAC_PCS.ENABLE_MAC_TX_VLAN = ENABLE_MAC_TX_VLAN,
U_MULTI_MAC_PCS.PHY_IDENTIFIER = PHY_IDENTIFIER,
U_MULTI_MAC_PCS.DEV_VERSION = DEV_VERSION,
U_MULTI_MAC_PCS.ENABLE_SGMII = ENABLE_SGMII,
U_MULTI_MAC_PCS.MAX_CHANNELS = MAX_CHANNELS,
U_MULTI_MAC_PCS.CHANNEL_WIDTH = CHANNEL_WIDTH,
U_MULTI_MAC_PCS.ENABLE_RX_FIFO_STATUS = ENABLE_RX_FIFO_STATUS,
U_MULTI_MAC_PCS.ENABLE_EXTENDED_STAT_REG = ENABLE_EXTENDED_STAT_REG,
U_MULTI_MAC_PCS.ENABLE_CLK_SHARING = ENABLE_CLK_SHARING,
U_MULTI_MAC_PCS.ENABLE_REG_SHARING = ENABLE_REG_SHARING;
// #######################################################################
// ############### CHANNEL 0 LOGIC/COMPONENTS ###############
// #######################################################################
generate if (MAX_CHANNELS > 0)
begin
// Instantiation of the Alt2gxb and Alt4gxb block as the PMA for Stratix_II_GX ,ArriaGX and Stratix IV devices
// -----------------------------------------------------------------------------------
// Aligned Rx_sync from gxb
// -------------------------------
altera_tse_reset_synchronizer ch0_reset_sync_0(
.clk(ref_clk),
.reset_in(reset),
.reset_out(reset_rx_pcs_clk_c0_int)
);
altera_tse_gxb_aligned_rxsync the_altera_tse_gxb_aligned_rxsync_0
(
.clk(rx_pcs_clk_c0),
.reset(reset_rx_pcs_clk_c0_int),
//input (from alt2gxb)
.alt_dataout(rx_frame_0),
.alt_sync(rx_syncstatus[0]),
.alt_disperr(rx_disp_err[0]),
.alt_ctrldetect(rx_kchar_0),
.alt_errdetect(rx_char_err_gx[0]),
.alt_rmfifodatadeleted(rx_rmfifodatadeleted[0]),
.alt_rmfifodatainserted(rx_rmfifodatainserted[0]),
.alt_runlengthviolation(rx_runlengthviolation[0]),
.alt_patterndetect(rx_patterndetect[0]),
.alt_runningdisp(rx_runningdisp[0]),
//output (to PCS)
.altpcs_dataout(pcs_rx_frame_0),
.altpcs_sync(link_status[0]),
.altpcs_disperr(led_disp_err_0),
.altpcs_ctrldetect(pcs_rx_kchar_0),
.altpcs_errdetect(led_char_err_gx[0]),
.altpcs_rmfifodatadeleted(pcs_rx_rmfifodatadeleted[0]),
.altpcs_rmfifodatainserted(pcs_rx_rmfifodatainserted[0]),
.altpcs_carrierdetect(pcs_rx_carrierdetected[0])
) ;
defparam
the_altera_tse_gxb_aligned_rxsync_0.DEVICE_FAMILY = DEVICE_FAMILY;
// Altgxb in GIGE mode
// --------------------
altera_tse_gxb_gige_phyip_inst the_altera_tse_gxb_gige_phyip_inst_0
(
.phy_mgmt_clk(clk),
.phy_mgmt_clk_reset(reset),
.phy_mgmt_address(phy_mgmt_address_0),
.phy_mgmt_read(phy_mgmt_read_0),
.phy_mgmt_readdata(phy_mgmt_readdata_0),
.phy_mgmt_waitrequest(phy_mgmt_waitrequest_0),
.phy_mgmt_write(phy_mgmt_write_0),
.phy_mgmt_writedata(phy_mgmt_writedata_0),
.tx_ready(),
.rx_ready(),
.pll_ref_clk(ref_clk),
.pll_locked(),
.tx_serial_data(txp_0),
.rx_serial_data(rxp_0),
.rx_runningdisp(rx_runningdisp[0]),
.rx_disperr(rx_disp_err[0]),
.rx_errdetect(rx_char_err_gx[0]),
.rx_patterndetect(rx_patterndetect[0]),
.rx_syncstatus(rx_syncstatus[0]),
.tx_clkout(tx_pcs_clk_c0),
.rx_clkout(rx_pcs_clk_c0),
.tx_parallel_data(tx_frame_0),
.tx_datak(tx_kchar_0),
.rx_parallel_data(rx_frame_0),
.rx_datak(rx_kchar_0),
.rx_rlv(rx_runlengthviolation[0]),
.rx_recovclkout(rx_recovclkout_0),
.rx_rmfifodatadeleted(rx_rmfifodatadeleted[0]),
.rx_rmfifodatainserted(rx_rmfifodatainserted[0]),
.reconfig_togxb(reconfig_togxb_0),
.reconfig_fromgxb(reconfig_fromgxb_0)
);
defparam
the_altera_tse_gxb_gige_phyip_inst_0.ENABLE_ALT_RECONFIG = ENABLE_ALT_RECONFIG,
the_altera_tse_gxb_gige_phyip_inst_0.ENABLE_SGMII = ENABLE_SGMII,
the_altera_tse_gxb_gige_phyip_inst_0.DEVICE_FAMILY = DEVICE_FAMILY;
end
else
begin
assign reconfig_fromgxb_0 = {92{1'b0}};
assign led_char_err_gx[0] = 1'b0;
assign link_status[0] = 1'b0;
assign led_disp_err_0 = 1'b0;
assign txp_0 = 1'b0;
assign rx_recovclkout_0= 1'b0;
assign phy_mgmt_readdata_0 = 32'b0;
assign phy_mgmt_waitrequest_0 = 1'b0;
end
endgenerate
// #######################################################################
// ############### CHANNEL 1 LOGIC/COMPONENTS ###############
// #######################################################################
generate if (MAX_CHANNELS > 1)
begin
// Instantiation of the Alt2gxb and Alt4gxb block as the PMA for Stratix_II_GX ,ArriaGX and Stratix IV devices
// -----------------------------------------------------------------------------------
// Aligned Rx_sync from gxb
// -------------------------------
altera_tse_reset_synchronizer ch1_reset_sync_0(
.clk(ref_clk),
.reset_in(reset),
.reset_out(reset_rx_pcs_clk_c1_int)
);
altera_tse_gxb_aligned_rxsync the_altera_tse_gxb_aligned_rxsync_1
(
.clk(rx_pcs_clk_c1),
.reset(reset_rx_pcs_clk_c1_int),
//input (from alt2gxb)
.alt_dataout(rx_frame_1),
.alt_sync(rx_syncstatus[1]),
.alt_disperr(rx_disp_err[1]),
.alt_ctrldetect(rx_kchar_1),
.alt_errdetect(rx_char_err_gx[1]),
.alt_rmfifodatadeleted(rx_rmfifodatadeleted[1]),
.alt_rmfifodatainserted(rx_rmfifodatainserted[1]),
.alt_runlengthviolation(rx_runlengthviolation[1]),
.alt_patterndetect(rx_patterndetect[1]),
.alt_runningdisp(rx_runningdisp[1]),
//output (to PCS)
.altpcs_dataout(pcs_rx_frame_1),
.altpcs_sync(link_status[1]),
.altpcs_disperr(led_disp_err_1),
.altpcs_ctrldetect(pcs_rx_kchar_1),
.altpcs_errdetect(led_char_err_gx[1]),
.altpcs_rmfifodatadeleted(pcs_rx_rmfifodatadeleted[1]),
.altpcs_rmfifodatainserted(pcs_rx_rmfifodatainserted[1]),
.altpcs_carrierdetect(pcs_rx_carrierdetected[1])
) ;
defparam
the_altera_tse_gxb_aligned_rxsync_1.DEVICE_FAMILY = DEVICE_FAMILY;
// Altgxb in GIGE mode
// --------------------
altera_tse_gxb_gige_phyip_inst the_altera_tse_gxb_gige_phyip_inst_1
(
.phy_mgmt_clk(clk),
.phy_mgmt_clk_reset(reset),
.phy_mgmt_address(phy_mgmt_address_1),
.phy_mgmt_read(phy_mgmt_read_1),
.phy_mgmt_readdata(phy_mgmt_readdata_1),
.phy_mgmt_waitrequest(phy_mgmt_waitrequest_1),
.phy_mgmt_write(phy_mgmt_write_1),
.phy_mgmt_writedata(phy_mgmt_writedata_1),
.tx_ready(),
.rx_ready(),
.pll_ref_clk(ref_clk),
.pll_locked(),
.tx_serial_data(txp_1),
.rx_serial_data(rxp_1),
.rx_runningdisp(rx_runningdisp[1]),
.rx_disperr(rx_disp_err[1]),
.rx_errdetect(rx_char_err_gx[1]),
.rx_patterndetect(rx_patterndetect[1]),
.rx_syncstatus(rx_syncstatus[1]),
.tx_clkout(tx_pcs_clk_c1),
.rx_clkout(rx_pcs_clk_c1),
.tx_parallel_data(tx_frame_1),
.tx_datak(tx_kchar_1),
.rx_parallel_data(rx_frame_1),
.rx_datak(rx_kchar_1),
.rx_rlv(rx_runlengthviolation[1]),
.rx_recovclkout(rx_recovclkout_1),
.rx_rmfifodatadeleted(rx_rmfifodatadeleted[1]),
.rx_rmfifodatainserted(rx_rmfifodatainserted[1]),
.reconfig_togxb(reconfig_togxb_1),
.reconfig_fromgxb(reconfig_fromgxb_1)
);
defparam
the_altera_tse_gxb_gige_phyip_inst_1.ENABLE_ALT_RECONFIG = ENABLE_ALT_RECONFIG,
the_altera_tse_gxb_gige_phyip_inst_1.ENABLE_SGMII = ENABLE_SGMII,
the_altera_tse_gxb_gige_phyip_inst_1.DEVICE_FAMILY = DEVICE_FAMILY;
end
else
begin
assign reconfig_fromgxb_1 = {92{1'b0}};
assign led_char_err_gx[1] = 1'b0;
assign link_status[1] = 1'b0;
assign led_disp_err_1 = 1'b0;
assign txp_1 = 1'b0;
assign rx_recovclkout_1= 1'b0;
assign phy_mgmt_readdata_1 = 32'b0;
assign phy_mgmt_waitrequest_1 = 1'b0;
end
endgenerate
// #######################################################################
// ############### CHANNEL 2 LOGIC/COMPONENTS ###############
// #######################################################################
generate if (MAX_CHANNELS > 2)
begin
// Instantiation of the Alt2gxb and Alt4gxb block as the PMA for Stratix_II_GX ,ArriaGX and Stratix IV devices
// -----------------------------------------------------------------------------------
// Aligned Rx_sync from gxb
// -------------------------------
altera_tse_reset_synchronizer ch2_reset_sync_0(
.clk(ref_clk),
.reset_in(reset),
.reset_out(reset_rx_pcs_clk_c2_int)
);
altera_tse_gxb_aligned_rxsync the_altera_tse_gxb_aligned_rxsync_2
(
.clk(rx_pcs_clk_c2),
.reset(reset_rx_pcs_clk_c2_int),
//input (from alt2gxb)
.alt_dataout(rx_frame_2),
.alt_sync(rx_syncstatus[2]),
.alt_disperr(rx_disp_err[2]),
.alt_ctrldetect(rx_kchar_2),
.alt_errdetect(rx_char_err_gx[2]),
.alt_rmfifodatadeleted(rx_rmfifodatadeleted[2]),
.alt_rmfifodatainserted(rx_rmfifodatainserted[2]),
.alt_runlengthviolation(rx_runlengthviolation[2]),
.alt_patterndetect(rx_patterndetect[2]),
.alt_runningdisp(rx_runningdisp[2]),
//output (to PCS)
.altpcs_dataout(pcs_rx_frame_2),
.altpcs_sync(link_status[2]),
.altpcs_disperr(led_disp_err_2),
.altpcs_ctrldetect(pcs_rx_kchar_2),
.altpcs_errdetect(led_char_err_gx[2]),
.altpcs_rmfifodatadeleted(pcs_rx_rmfifodatadeleted[2]),
.altpcs_rmfifodatainserted(pcs_rx_rmfifodatainserted[2]),
.altpcs_carrierdetect(pcs_rx_carrierdetected[2])
) ;
defparam
the_altera_tse_gxb_aligned_rxsync_2.DEVICE_FAMILY = DEVICE_FAMILY;
// Altgxb in GIGE mode
// --------------------
altera_tse_gxb_gige_phyip_inst the_altera_tse_gxb_gige_phyip_inst_2
(
.phy_mgmt_clk(clk),
.phy_mgmt_clk_reset(reset),
.phy_mgmt_address(phy_mgmt_address_2),
.phy_mgmt_read(phy_mgmt_read_2),
.phy_mgmt_readdata(phy_mgmt_readdata_2),
.phy_mgmt_waitrequest(phy_mgmt_waitrequest_2),
.phy_mgmt_write(phy_mgmt_write_2),
.phy_mgmt_writedata(phy_mgmt_writedata_2),
.tx_ready(),
.rx_ready(),
.pll_ref_clk(ref_clk),
.pll_locked(),
.tx_serial_data(txp_2),
.rx_serial_data(rxp_2),
.rx_runningdisp(rx_runningdisp[2]),
.rx_disperr(rx_disp_err[2]),
.rx_errdetect(rx_char_err_gx[2]),
.rx_patterndetect(rx_patterndetect[2]),
.rx_syncstatus(rx_syncstatus[2]),
.tx_clkout(tx_pcs_clk_c2),
.rx_clkout(rx_pcs_clk_c2),
.tx_parallel_data(tx_frame_2),
.tx_datak(tx_kchar_2),
.rx_parallel_data(rx_frame_2),
.rx_datak(rx_kchar_2),
.rx_rlv(rx_runlengthviolation[2]),
.rx_recovclkout(rx_recovclkout_2),
.rx_rmfifodatadeleted(rx_rmfifodatadeleted[2]),
.rx_rmfifodatainserted(rx_rmfifodatainserted[2]),
.reconfig_togxb(reconfig_togxb_2),
.reconfig_fromgxb(reconfig_fromgxb_2)
);
defparam
the_altera_tse_gxb_gige_phyip_inst_2.ENABLE_ALT_RECONFIG = ENABLE_ALT_RECONFIG,
the_altera_tse_gxb_gige_phyip_inst_2.ENABLE_SGMII = ENABLE_SGMII,
the_altera_tse_gxb_gige_phyip_inst_2.DEVICE_FAMILY = DEVICE_FAMILY;
end
else
begin
assign reconfig_fromgxb_2 = {92{1'b0}};
assign led_char_err_gx[2] = 1'b0;
assign link_status[2] = 1'b0;
assign led_disp_err_2 = 1'b0;
assign txp_2 = 1'b0;
assign rx_recovclkout_2= 1'b0;
assign phy_mgmt_readdata_2 = 32'b0;
assign phy_mgmt_waitrequest_2 = 1'b0;
end
endgenerate
// #######################################################################
// ############### CHANNEL 3 LOGIC/COMPONENTS ###############
// #######################################################################
generate if (MAX_CHANNELS > 3)
begin
// Instantiation of the Alt2gxb and Alt4gxb block as the PMA for Stratix_II_GX ,ArriaGX and Stratix IV devices
// -----------------------------------------------------------------------------------
// Aligned Rx_sync from gxb
// -------------------------------
altera_tse_reset_synchronizer ch3_reset_sync_0(
.clk(ref_clk),
.reset_in(reset),
.reset_out(reset_rx_pcs_clk_c3_int)
);
altera_tse_gxb_aligned_rxsync the_altera_tse_gxb_aligned_rxsync_3
(
.clk(rx_pcs_clk_c3),
.reset(reset_rx_pcs_clk_c3_int),
//input (from alt2gxb)
.alt_dataout(rx_frame_3),
.alt_sync(rx_syncstatus[3]),
.alt_disperr(rx_disp_err[3]),
.alt_ctrldetect(rx_kchar_3),
.alt_errdetect(rx_char_err_gx[3]),
.alt_rmfifodatadeleted(rx_rmfifodatadeleted[3]),
.alt_rmfifodatainserted(rx_rmfifodatainserted[3]),
.alt_runlengthviolation(rx_runlengthviolation[3]),
.alt_patterndetect(rx_patterndetect[3]),
.alt_runningdisp(rx_runningdisp[3]),
//output (to PCS)
.altpcs_dataout(pcs_rx_frame_3),
.altpcs_sync(link_status[3]),
.altpcs_disperr(led_disp_err_3),
.altpcs_ctrldetect(pcs_rx_kchar_3),
.altpcs_errdetect(led_char_err_gx[3]),
.altpcs_rmfifodatadeleted(pcs_rx_rmfifodatadeleted[3]),
.altpcs_rmfifodatainserted(pcs_rx_rmfifodatainserted[3]),
.altpcs_carrierdetect(pcs_rx_carrierdetected[3])
) ;
defparam
the_altera_tse_gxb_aligned_rxsync_3.DEVICE_FAMILY = DEVICE_FAMILY;
// Altgxb in GIGE mode
// --------------------
altera_tse_gxb_gige_phyip_inst the_altera_tse_gxb_gige_phyip_inst_3
(
.phy_mgmt_clk(clk),
.phy_mgmt_clk_reset(reset),
.phy_mgmt_address(phy_mgmt_address_3),
.phy_mgmt_read(phy_mgmt_read_3),
.phy_mgmt_readdata(phy_mgmt_readdata_3),
.phy_mgmt_waitrequest(phy_mgmt_waitrequest_3),
.phy_mgmt_write(phy_mgmt_write_3),
.phy_mgmt_writedata(phy_mgmt_writedata_3),
.tx_ready(),
.rx_ready(),
.pll_ref_clk(ref_clk),
.pll_locked(),
.tx_serial_data(txp_3),
.rx_serial_data(rxp_3),
.rx_runningdisp(rx_runningdisp[3]),
.rx_disperr(rx_disp_err[3]),
.rx_errdetect(rx_char_err_gx[3]),
.rx_patterndetect(rx_patterndetect[3]),
.rx_syncstatus(rx_syncstatus[3]),
.tx_clkout(tx_pcs_clk_c3),
.rx_clkout(rx_pcs_clk_c3),
.tx_parallel_data(tx_frame_3),
.tx_datak(tx_kchar_3),
.rx_parallel_data(rx_frame_3),
.rx_datak(rx_kchar_3),
.rx_rlv(rx_runlengthviolation[3]),
.rx_recovclkout(rx_recovclkout_3),
.rx_rmfifodatadeleted(rx_rmfifodatadeleted[3]),
.rx_rmfifodatainserted(rx_rmfifodatainserted[3]),
.reconfig_togxb(reconfig_togxb_3),
.reconfig_fromgxb(reconfig_fromgxb_3)
);
defparam
the_altera_tse_gxb_gige_phyip_inst_3.ENABLE_ALT_RECONFIG = ENABLE_ALT_RECONFIG,
the_altera_tse_gxb_gige_phyip_inst_3.ENABLE_SGMII = ENABLE_SGMII,
the_altera_tse_gxb_gige_phyip_inst_3.DEVICE_FAMILY = DEVICE_FAMILY;
end
else
begin
assign reconfig_fromgxb_3 = {92{1'b0}};
assign led_char_err_gx[3] = 1'b0;
assign link_status[3] = 1'b0;
assign led_disp_err_3 = 1'b0;
assign txp_3 = 1'b0;
assign rx_recovclkout_3= 1'b0;
assign phy_mgmt_readdata_3 = 32'b0;
assign phy_mgmt_waitrequest_3 = 1'b0;
end
endgenerate
// #######################################################################
// ############### CHANNEL 4 LOGIC/COMPONENTS ###############
// #######################################################################
generate if (MAX_CHANNELS > 4)
begin
// Instantiation of the Alt2gxb and Alt4gxb block as the PMA for Stratix_II_GX ,ArriaGX and Stratix IV devices
// -----------------------------------------------------------------------------------
// Aligned Rx_sync from gxb
// -------------------------------
altera_tse_reset_synchronizer ch4_reset_sync_0(
.clk(ref_clk),
.reset_in(reset),
.reset_out(reset_rx_pcs_clk_c4_int)
);
altera_tse_gxb_aligned_rxsync the_altera_tse_gxb_aligned_rxsync_4
(
.clk(rx_pcs_clk_c4),
.reset(reset_rx_pcs_clk_c4_int),
//input (from alt2gxb)
.alt_dataout(rx_frame_4),
.alt_sync(rx_syncstatus[4]),
.alt_disperr(rx_disp_err[4]),
.alt_ctrldetect(rx_kchar_4),
.alt_errdetect(rx_char_err_gx[4]),
.alt_rmfifodatadeleted(rx_rmfifodatadeleted[4]),
.alt_rmfifodatainserted(rx_rmfifodatainserted[4]),
.alt_runlengthviolation(rx_runlengthviolation[4]),
.alt_patterndetect(rx_patterndetect[4]),
.alt_runningdisp(rx_runningdisp[4]),
//output (to PCS)
.altpcs_dataout(pcs_rx_frame_4),
.altpcs_sync(link_status[4]),
.altpcs_disperr(led_disp_err_4),
.altpcs_ctrldetect(pcs_rx_kchar_4),
.altpcs_errdetect(led_char_err_gx[4]),
.altpcs_rmfifodatadeleted(pcs_rx_rmfifodatadeleted[4]),
.altpcs_rmfifodatainserted(pcs_rx_rmfifodatainserted[4]),
.altpcs_carrierdetect(pcs_rx_carrierdetected[4])
) ;
defparam
the_altera_tse_gxb_aligned_rxsync_4.DEVICE_FAMILY = DEVICE_FAMILY;
// Altgxb in GIGE mode
// --------------------
altera_tse_gxb_gige_phyip_inst the_altera_tse_gxb_gige_phyip_inst_4
(
.phy_mgmt_clk(clk),
.phy_mgmt_clk_reset(reset),
.phy_mgmt_address(phy_mgmt_address_4),
.phy_mgmt_read(phy_mgmt_read_4),
.phy_mgmt_readdata(phy_mgmt_readdata_4),
.phy_mgmt_waitrequest(phy_mgmt_waitrequest_4),
.phy_mgmt_write(phy_mgmt_write_4),
.phy_mgmt_writedata(phy_mgmt_writedata_4),
.tx_ready(),
.rx_ready(),
.pll_ref_clk(ref_clk),
.pll_locked(),
.tx_serial_data(txp_4),
.rx_serial_data(rxp_4),
.rx_runningdisp(rx_runningdisp[4]),
.rx_disperr(rx_disp_err[4]),
.rx_errdetect(rx_char_err_gx[4]),
.rx_patterndetect(rx_patterndetect[4]),
.rx_syncstatus(rx_syncstatus[4]),
.tx_clkout(tx_pcs_clk_c4),
.rx_clkout(rx_pcs_clk_c4),
.tx_parallel_data(tx_frame_4),
.tx_datak(tx_kchar_4),
.rx_parallel_data(rx_frame_4),
.rx_datak(rx_kchar_4),
.rx_rlv(rx_runlengthviolation[4]),
.rx_recovclkout(rx_recovclkout_4),
.rx_rmfifodatadeleted(rx_rmfifodatadeleted[4]),
.rx_rmfifodatainserted(rx_rmfifodatainserted[4]),
.reconfig_togxb(reconfig_togxb_4),
.reconfig_fromgxb(reconfig_fromgxb_4)
);
defparam
the_altera_tse_gxb_gige_phyip_inst_4.ENABLE_ALT_RECONFIG = ENABLE_ALT_RECONFIG,
the_altera_tse_gxb_gige_phyip_inst_4.ENABLE_SGMII = ENABLE_SGMII,
the_altera_tse_gxb_gige_phyip_inst_4.DEVICE_FAMILY = DEVICE_FAMILY;
end
else
begin
assign reconfig_fromgxb_4 = {92{1'b0}};
assign led_char_err_gx[4] = 1'b0;
assign link_status[4] = 1'b0;
assign led_disp_err_4 = 1'b0;
assign txp_4 = 1'b0;
assign rx_recovclkout_4= 1'b0;
assign phy_mgmt_readdata_4 = 32'b0;
assign phy_mgmt_waitrequest_4 = 1'b0;
end
endgenerate
// #######################################################################
// ############### CHANNEL 5 LOGIC/COMPONENTS ###############
// #######################################################################
generate if (MAX_CHANNELS > 5)
begin
// Instantiation of the Alt2gxb and Alt4gxb block as the PMA for Stratix_II_GX ,ArriaGX and Stratix IV devices
// -----------------------------------------------------------------------------------
// Aligned Rx_sync from gxb
// -------------------------------
altera_tse_reset_synchronizer ch5_reset_sync_0(
.clk(ref_clk),
.reset_in(reset),
.reset_out(reset_rx_pcs_clk_c5_int)
);
altera_tse_gxb_aligned_rxsync the_altera_tse_gxb_aligned_rxsync_5
(
.clk(rx_pcs_clk_c5),
.reset(reset_rx_pcs_clk_c5_int),
//input (from alt2gxb)
.alt_dataout(rx_frame_5),
.alt_sync(rx_syncstatus[5]),
.alt_disperr(rx_disp_err[5]),
.alt_ctrldetect(rx_kchar_5),
.alt_errdetect(rx_char_err_gx[5]),
.alt_rmfifodatadeleted(rx_rmfifodatadeleted[5]),
.alt_rmfifodatainserted(rx_rmfifodatainserted[5]),
.alt_runlengthviolation(rx_runlengthviolation[5]),
.alt_patterndetect(rx_patterndetect[5]),
.alt_runningdisp(rx_runningdisp[5]),
//output (to PCS)
.altpcs_dataout(pcs_rx_frame_5),
.altpcs_sync(link_status[5]),
.altpcs_disperr(led_disp_err_5),
.altpcs_ctrldetect(pcs_rx_kchar_5),
.altpcs_errdetect(led_char_err_gx[5]),
.altpcs_rmfifodatadeleted(pcs_rx_rmfifodatadeleted[5]),
.altpcs_rmfifodatainserted(pcs_rx_rmfifodatainserted[5]),
.altpcs_carrierdetect(pcs_rx_carrierdetected[5])
) ;
defparam
the_altera_tse_gxb_aligned_rxsync_5.DEVICE_FAMILY = DEVICE_FAMILY;
// Altgxb in GIGE mode
// --------------------
altera_tse_gxb_gige_phyip_inst the_altera_tse_gxb_gige_phyip_inst_5
(
.phy_mgmt_clk(clk),
.phy_mgmt_clk_reset(reset),
.phy_mgmt_address(phy_mgmt_address_5),
.phy_mgmt_read(phy_mgmt_read_5),
.phy_mgmt_readdata(phy_mgmt_readdata_5),
.phy_mgmt_waitrequest(phy_mgmt_waitrequest_5),
.phy_mgmt_write(phy_mgmt_write_5),
.phy_mgmt_writedata(phy_mgmt_writedata_5),
.tx_ready(),
.rx_ready(),
.pll_ref_clk(ref_clk),
.pll_locked(),
.tx_serial_data(txp_5),
.rx_serial_data(rxp_5),
.rx_runningdisp(rx_runningdisp[5]),
.rx_disperr(rx_disp_err[5]),
.rx_errdetect(rx_char_err_gx[5]),
.rx_patterndetect(rx_patterndetect[5]),
.rx_syncstatus(rx_syncstatus[5]),
.tx_clkout(tx_pcs_clk_c5),
.rx_clkout(rx_pcs_clk_c5),
.tx_parallel_data(tx_frame_5),
.tx_datak(tx_kchar_5),
.rx_parallel_data(rx_frame_5),
.rx_datak(rx_kchar_5),
.rx_rlv(rx_runlengthviolation[5]),
.rx_recovclkout(rx_recovclkout_5),
.rx_rmfifodatadeleted(rx_rmfifodatadeleted[5]),
.rx_rmfifodatainserted(rx_rmfifodatainserted[5]),
.reconfig_togxb(reconfig_togxb_5),
.reconfig_fromgxb(reconfig_fromgxb_5)
);
defparam
the_altera_tse_gxb_gige_phyip_inst_5.ENABLE_ALT_RECONFIG = ENABLE_ALT_RECONFIG,
the_altera_tse_gxb_gige_phyip_inst_5.ENABLE_SGMII = ENABLE_SGMII,
the_altera_tse_gxb_gige_phyip_inst_5.DEVICE_FAMILY = DEVICE_FAMILY;
end
else
begin
assign reconfig_fromgxb_5 = {92{1'b0}};
assign led_char_err_gx[5] = 1'b0;
assign link_status[5] = 1'b0;
assign led_disp_err_5 = 1'b0;
assign txp_5 = 1'b0;
assign rx_recovclkout_5= 1'b0;
assign phy_mgmt_readdata_5 = 32'b0;
assign phy_mgmt_waitrequest_5 = 1'b0;
end
endgenerate
// #######################################################################
// ############### CHANNEL 6 LOGIC/COMPONENTS ###############
// #######################################################################
generate if (MAX_CHANNELS > 6)
begin
// Instantiation of the Alt2gxb and Alt4gxb block as the PMA for Stratix_II_GX ,ArriaGX and Stratix IV devices
// -----------------------------------------------------------------------------------
// Aligned Rx_sync from gxb
// -------------------------------
altera_tse_reset_synchronizer ch6_reset_sync_0(
.clk(ref_clk),
.reset_in(reset),
.reset_out(reset_rx_pcs_clk_c6_int)
);
altera_tse_gxb_aligned_rxsync the_altera_tse_gxb_aligned_rxsync_6
(
.clk(rx_pcs_clk_c6),
.reset(reset_rx_pcs_clk_c6_int),
//input (from alt2gxb)
.alt_dataout(rx_frame_6),
.alt_sync(rx_syncstatus[6]),
.alt_disperr(rx_disp_err[6]),
.alt_ctrldetect(rx_kchar_6),
.alt_errdetect(rx_char_err_gx[6]),
.alt_rmfifodatadeleted(rx_rmfifodatadeleted[6]),
.alt_rmfifodatainserted(rx_rmfifodatainserted[6]),
.alt_runlengthviolation(rx_runlengthviolation[6]),
.alt_patterndetect(rx_patterndetect[6]),
.alt_runningdisp(rx_runningdisp[6]),
//output (to PCS)
.altpcs_dataout(pcs_rx_frame_6),
.altpcs_sync(link_status[6]),
.altpcs_disperr(led_disp_err_6),
.altpcs_ctrldetect(pcs_rx_kchar_6),
.altpcs_errdetect(led_char_err_gx[6]),
.altpcs_rmfifodatadeleted(pcs_rx_rmfifodatadeleted[6]),
.altpcs_rmfifodatainserted(pcs_rx_rmfifodatainserted[6]),
.altpcs_carrierdetect(pcs_rx_carrierdetected[6])
) ;
defparam
the_altera_tse_gxb_aligned_rxsync_6.DEVICE_FAMILY = DEVICE_FAMILY;
// Altgxb in GIGE mode
// --------------------
altera_tse_gxb_gige_phyip_inst the_altera_tse_gxb_gige_phyip_inst_6
(
.phy_mgmt_clk(clk),
.phy_mgmt_clk_reset(reset),
.phy_mgmt_address(phy_mgmt_address_6),
.phy_mgmt_read(phy_mgmt_read_6),
.phy_mgmt_readdata(phy_mgmt_readdata_6),
.phy_mgmt_waitrequest(phy_mgmt_waitrequest_6),
.phy_mgmt_write(phy_mgmt_write_6),
.phy_mgmt_writedata(phy_mgmt_writedata_6),
.tx_ready(),
.rx_ready(),
.pll_ref_clk(ref_clk),
.pll_locked(),
.tx_serial_data(txp_6),
.rx_serial_data(rxp_6),
.rx_runningdisp(rx_runningdisp[6]),
.rx_disperr(rx_disp_err[6]),
.rx_errdetect(rx_char_err_gx[6]),
.rx_patterndetect(rx_patterndetect[6]),
.rx_syncstatus(rx_syncstatus[6]),
.tx_clkout(tx_pcs_clk_c6),
.rx_clkout(rx_pcs_clk_c6),
.tx_parallel_data(tx_frame_6),
.tx_datak(tx_kchar_6),
.rx_parallel_data(rx_frame_6),
.rx_datak(rx_kchar_6),
.rx_rlv(rx_runlengthviolation[6]),
.rx_recovclkout(rx_recovclkout_6),
.rx_rmfifodatadeleted(rx_rmfifodatadeleted[6]),
.rx_rmfifodatainserted(rx_rmfifodatainserted[6]),
.reconfig_togxb(reconfig_togxb_6),
.reconfig_fromgxb(reconfig_fromgxb_6)
);
defparam
the_altera_tse_gxb_gige_phyip_inst_6.ENABLE_ALT_RECONFIG = ENABLE_ALT_RECONFIG,
the_altera_tse_gxb_gige_phyip_inst_6.ENABLE_SGMII = ENABLE_SGMII,
the_altera_tse_gxb_gige_phyip_inst_6.DEVICE_FAMILY = DEVICE_FAMILY;
end
else
begin
assign reconfig_fromgxb_6 = {92{1'b0}};
assign led_char_err_gx[6] = 1'b0;
assign link_status[6] = 1'b0;
assign led_disp_err_6 = 1'b0;
assign txp_6 = 1'b0;
assign rx_recovclkout_6= 1'b0;
assign phy_mgmt_readdata_6 = 32'b0;
assign phy_mgmt_waitrequest_6 = 1'b0;
end
endgenerate
// #######################################################################
// ############### CHANNEL 7 LOGIC/COMPONENTS ###############
// #######################################################################
generate if (MAX_CHANNELS > 7)
begin
// Instantiation of the Alt2gxb and Alt4gxb block as the PMA for Stratix_II_GX ,ArriaGX and Stratix IV devices
// -----------------------------------------------------------------------------------
// Aligned Rx_sync from gxb
// -------------------------------
altera_tse_reset_synchronizer ch7_reset_sync_0(
.clk(ref_clk),
.reset_in(reset),
.reset_out(reset_rx_pcs_clk_c7_int)
);
altera_tse_gxb_aligned_rxsync the_altera_tse_gxb_aligned_rxsync_7
(
.clk(rx_pcs_clk_c7),
.reset(reset_rx_pcs_clk_c7_int),
//input (from alt2gxb)
.alt_dataout(rx_frame_7),
.alt_sync(rx_syncstatus[7]),
.alt_disperr(rx_disp_err[7]),
.alt_ctrldetect(rx_kchar_7),
.alt_errdetect(rx_char_err_gx[7]),
.alt_rmfifodatadeleted(rx_rmfifodatadeleted[7]),
.alt_rmfifodatainserted(rx_rmfifodatainserted[7]),
.alt_runlengthviolation(rx_runlengthviolation[7]),
.alt_patterndetect(rx_patterndetect[7]),
.alt_runningdisp(rx_runningdisp[7]),
//output (to PCS)
.altpcs_dataout(pcs_rx_frame_7),
.altpcs_sync(link_status[7]),
.altpcs_disperr(led_disp_err_7),
.altpcs_ctrldetect(pcs_rx_kchar_7),
.altpcs_errdetect(led_char_err_gx[7]),
.altpcs_rmfifodatadeleted(pcs_rx_rmfifodatadeleted[7]),
.altpcs_rmfifodatainserted(pcs_rx_rmfifodatainserted[7]),
.altpcs_carrierdetect(pcs_rx_carrierdetected[7])
) ;
defparam
the_altera_tse_gxb_aligned_rxsync_7.DEVICE_FAMILY = DEVICE_FAMILY;
// Altgxb in GIGE mode
// --------------------
altera_tse_gxb_gige_phyip_inst the_altera_tse_gxb_gige_phyip_inst_7
(
.phy_mgmt_clk(clk),
.phy_mgmt_clk_reset(reset),
.phy_mgmt_address(phy_mgmt_address_7),
.phy_mgmt_read(phy_mgmt_read_7),
.phy_mgmt_readdata(phy_mgmt_readdata_7),
.phy_mgmt_waitrequest(phy_mgmt_waitrequest_7),
.phy_mgmt_write(phy_mgmt_write_7),
.phy_mgmt_writedata(phy_mgmt_writedata_7),
.tx_ready(),
.rx_ready(),
.pll_ref_clk(ref_clk),
.pll_locked(),
.tx_serial_data(txp_7),
.rx_serial_data(rxp_7),
.rx_runningdisp(rx_runningdisp[7]),
.rx_disperr(rx_disp_err[7]),
.rx_errdetect(rx_char_err_gx[7]),
.rx_patterndetect(rx_patterndetect[7]),
.rx_syncstatus(rx_syncstatus[7]),
.tx_clkout(tx_pcs_clk_c7),
.rx_clkout(rx_pcs_clk_c7),
.tx_parallel_data(tx_frame_7),
.tx_datak(tx_kchar_7),
.rx_parallel_data(rx_frame_7),
.rx_datak(rx_kchar_7),
.rx_rlv(rx_runlengthviolation[7]),
.rx_recovclkout(rx_recovclkout_7),
.rx_rmfifodatadeleted(rx_rmfifodatadeleted[7]),
.rx_rmfifodatainserted(rx_rmfifodatainserted[7]),
.reconfig_togxb(reconfig_togxb_7),
.reconfig_fromgxb(reconfig_fromgxb_7)
);
defparam
the_altera_tse_gxb_gige_phyip_inst_7.ENABLE_ALT_RECONFIG = ENABLE_ALT_RECONFIG,
the_altera_tse_gxb_gige_phyip_inst_7.ENABLE_SGMII = ENABLE_SGMII,
the_altera_tse_gxb_gige_phyip_inst_7.DEVICE_FAMILY = DEVICE_FAMILY;
end
else
begin
assign reconfig_fromgxb_7 = {92{1'b0}};
assign led_char_err_gx[7] = 1'b0;
assign link_status[7] = 1'b0;
assign led_disp_err_7 = 1'b0;
assign txp_7 = 1'b0;
assign rx_recovclkout_7= 1'b0;
assign phy_mgmt_readdata_7 = 32'b0;
assign phy_mgmt_waitrequest_7 = 1'b0;
end
endgenerate
// #######################################################################
// ############### CHANNEL 8 LOGIC/COMPONENTS ###############
// #######################################################################
generate if (MAX_CHANNELS > 8)
begin
// Instantiation of the Alt2gxb and Alt4gxb block as the PMA for Stratix_II_GX ,ArriaGX and Stratix IV devices
// -----------------------------------------------------------------------------------
// Aligned Rx_sync from gxb
// -------------------------------
altera_tse_reset_synchronizer ch8_reset_sync_0(
.clk(ref_clk),
.reset_in(reset),
.reset_out(reset_rx_pcs_clk_c8_int)
);
altera_tse_gxb_aligned_rxsync the_altera_tse_gxb_aligned_rxsync_8
(
.clk(rx_pcs_clk_c8),
.reset(reset_rx_pcs_clk_c8_int),
//input (from alt2gxb)
.alt_dataout(rx_frame_8),
.alt_sync(rx_syncstatus[8]),
.alt_disperr(rx_disp_err[8]),
.alt_ctrldetect(rx_kchar_8),
.alt_errdetect(rx_char_err_gx[8]),
.alt_rmfifodatadeleted(rx_rmfifodatadeleted[8]),
.alt_rmfifodatainserted(rx_rmfifodatainserted[8]),
.alt_runlengthviolation(rx_runlengthviolation[8]),
.alt_patterndetect(rx_patterndetect[8]),
.alt_runningdisp(rx_runningdisp[8]),
//output (to PCS)
.altpcs_dataout(pcs_rx_frame_8),
.altpcs_sync(link_status[8]),
.altpcs_disperr(led_disp_err_8),
.altpcs_ctrldetect(pcs_rx_kchar_8),
.altpcs_errdetect(led_char_err_gx[8]),
.altpcs_rmfifodatadeleted(pcs_rx_rmfifodatadeleted[8]),
.altpcs_rmfifodatainserted(pcs_rx_rmfifodatainserted[8]),
.altpcs_carrierdetect(pcs_rx_carrierdetected[8])
) ;
defparam
the_altera_tse_gxb_aligned_rxsync_8.DEVICE_FAMILY = DEVICE_FAMILY;
// Altgxb in GIGE mode
// --------------------
altera_tse_gxb_gige_phyip_inst the_altera_tse_gxb_gige_phyip_inst_8
(
.phy_mgmt_clk(clk),
.phy_mgmt_clk_reset(reset),
.phy_mgmt_address(phy_mgmt_address_8),
.phy_mgmt_read(phy_mgmt_read_8),
.phy_mgmt_readdata(phy_mgmt_readdata_8),
.phy_mgmt_waitrequest(phy_mgmt_waitrequest_8),
.phy_mgmt_write(phy_mgmt_write_8),
.phy_mgmt_writedata(phy_mgmt_writedata_8),
.tx_ready(),
.rx_ready(),
.pll_ref_clk(ref_clk),
.pll_locked(),
.tx_serial_data(txp_8),
.rx_serial_data(rxp_8),
.rx_runningdisp(rx_runningdisp[8]),
.rx_disperr(rx_disp_err[8]),
.rx_errdetect(rx_char_err_gx[8]),
.rx_patterndetect(rx_patterndetect[8]),
.rx_syncstatus(rx_syncstatus[8]),
.tx_clkout(tx_pcs_clk_c8),
.rx_clkout(rx_pcs_clk_c8),
.tx_parallel_data(tx_frame_8),
.tx_datak(tx_kchar_8),
.rx_parallel_data(rx_frame_8),
.rx_datak(rx_kchar_8),
.rx_rlv(rx_runlengthviolation[8]),
.rx_recovclkout(rx_recovclkout_8),
.rx_rmfifodatadeleted(rx_rmfifodatadeleted[8]),
.rx_rmfifodatainserted(rx_rmfifodatainserted[8]),
.reconfig_togxb(reconfig_togxb_8),
.reconfig_fromgxb(reconfig_fromgxb_8)
);
defparam
the_altera_tse_gxb_gige_phyip_inst_8.ENABLE_ALT_RECONFIG = ENABLE_ALT_RECONFIG,
the_altera_tse_gxb_gige_phyip_inst_8.ENABLE_SGMII = ENABLE_SGMII,
the_altera_tse_gxb_gige_phyip_inst_8.DEVICE_FAMILY = DEVICE_FAMILY;
end
else
begin
assign reconfig_fromgxb_8 = {92{1'b0}};
assign led_char_err_gx[8] = 1'b0;
assign link_status[8] = 1'b0;
assign led_disp_err_8 = 1'b0;
assign txp_8 = 1'b0;
assign rx_recovclkout_8= 1'b0;
assign phy_mgmt_readdata_8 = 32'b0;
assign phy_mgmt_waitrequest_8 = 1'b0;
end
endgenerate
// #######################################################################
// ############### CHANNEL 9 LOGIC/COMPONENTS ###############
// #######################################################################
generate if (MAX_CHANNELS > 9)
begin
// Instantiation of the Alt2gxb and Alt4gxb block as the PMA for Stratix_II_GX ,ArriaGX and Stratix IV devices
// -----------------------------------------------------------------------------------
// Aligned Rx_sync from gxb
// -------------------------------
altera_tse_reset_synchronizer ch9_reset_sync_0(
.clk(ref_clk),
.reset_in(reset),
.reset_out(reset_rx_pcs_clk_c9_int)
);
altera_tse_gxb_aligned_rxsync the_altera_tse_gxb_aligned_rxsync_9
(
.clk(rx_pcs_clk_c9),
.reset(reset_rx_pcs_clk_c9_int),
//input (from alt2gxb)
.alt_dataout(rx_frame_9),
.alt_sync(rx_syncstatus[9]),
.alt_disperr(rx_disp_err[9]),
.alt_ctrldetect(rx_kchar_9),
.alt_errdetect(rx_char_err_gx[9]),
.alt_rmfifodatadeleted(rx_rmfifodatadeleted[9]),
.alt_rmfifodatainserted(rx_rmfifodatainserted[9]),
.alt_runlengthviolation(rx_runlengthviolation[9]),
.alt_patterndetect(rx_patterndetect[9]),
.alt_runningdisp(rx_runningdisp[9]),
//output (to PCS)
.altpcs_dataout(pcs_rx_frame_9),
.altpcs_sync(link_status[9]),
.altpcs_disperr(led_disp_err_9),
.altpcs_ctrldetect(pcs_rx_kchar_9),
.altpcs_errdetect(led_char_err_gx[9]),
.altpcs_rmfifodatadeleted(pcs_rx_rmfifodatadeleted[9]),
.altpcs_rmfifodatainserted(pcs_rx_rmfifodatainserted[9]),
.altpcs_carrierdetect(pcs_rx_carrierdetected[9])
) ;
defparam
the_altera_tse_gxb_aligned_rxsync_9.DEVICE_FAMILY = DEVICE_FAMILY;
// Altgxb in GIGE mode
// --------------------
altera_tse_gxb_gige_phyip_inst the_altera_tse_gxb_gige_phyip_inst_9
(
.phy_mgmt_clk(clk),
.phy_mgmt_clk_reset(reset),
.phy_mgmt_address(phy_mgmt_address_9),
.phy_mgmt_read(phy_mgmt_read_9),
.phy_mgmt_readdata(phy_mgmt_readdata_9),
.phy_mgmt_waitrequest(phy_mgmt_waitrequest_9),
.phy_mgmt_write(phy_mgmt_write_9),
.phy_mgmt_writedata(phy_mgmt_writedata_9),
.tx_ready(),
.rx_ready(),
.pll_ref_clk(ref_clk),
.pll_locked(),
.tx_serial_data(txp_9),
.rx_serial_data(rxp_9),
.rx_runningdisp(rx_runningdisp[9]),
.rx_disperr(rx_disp_err[9]),
.rx_errdetect(rx_char_err_gx[9]),
.rx_patterndetect(rx_patterndetect[9]),
.rx_syncstatus(rx_syncstatus[9]),
.tx_clkout(tx_pcs_clk_c9),
.rx_clkout(rx_pcs_clk_c9),
.tx_parallel_data(tx_frame_9),
.tx_datak(tx_kchar_9),
.rx_parallel_data(rx_frame_9),
.rx_datak(rx_kchar_9),
.rx_rlv(rx_runlengthviolation[9]),
.rx_recovclkout(rx_recovclkout_9),
.rx_rmfifodatadeleted(rx_rmfifodatadeleted[9]),
.rx_rmfifodatainserted(rx_rmfifodatainserted[9]),
.reconfig_togxb(reconfig_togxb_9),
.reconfig_fromgxb(reconfig_fromgxb_9)
);
defparam
the_altera_tse_gxb_gige_phyip_inst_9.ENABLE_ALT_RECONFIG = ENABLE_ALT_RECONFIG,
the_altera_tse_gxb_gige_phyip_inst_9.ENABLE_SGMII = ENABLE_SGMII,
the_altera_tse_gxb_gige_phyip_inst_9.DEVICE_FAMILY = DEVICE_FAMILY;
end
else
begin
assign reconfig_fromgxb_9 = {92{1'b0}};
assign led_char_err_gx[9] = 1'b0;
assign link_status[9] = 1'b0;
assign led_disp_err_9 = 1'b0;
assign txp_9 = 1'b0;
assign rx_recovclkout_9= 1'b0;
assign phy_mgmt_readdata_9 = 32'b0;
assign phy_mgmt_waitrequest_9 = 1'b0;
end
endgenerate
// #######################################################################
// ############### CHANNEL 10 LOGIC/COMPONENTS ###############
// #######################################################################
generate if (MAX_CHANNELS > 10)
begin
// Instantiation of the Alt2gxb and Alt4gxb block as the PMA for Stratix_II_GX ,ArriaGX and Stratix IV devices
// -----------------------------------------------------------------------------------
// Aligned Rx_sync from gxb
// -------------------------------
altera_tse_reset_synchronizer ch10_reset_sync_0(
.clk(ref_clk),
.reset_in(reset),
.reset_out(reset_rx_pcs_clk_c10_int)
);
altera_tse_gxb_aligned_rxsync the_altera_tse_gxb_aligned_rxsync_10
(
.clk(rx_pcs_clk_c10),
.reset(reset_rx_pcs_clk_c10_int),
//input (from alt2gxb)
.alt_dataout(rx_frame_10),
.alt_sync(rx_syncstatus[10]),
.alt_disperr(rx_disp_err[10]),
.alt_ctrldetect(rx_kchar_10),
.alt_errdetect(rx_char_err_gx[10]),
.alt_rmfifodatadeleted(rx_rmfifodatadeleted[10]),
.alt_rmfifodatainserted(rx_rmfifodatainserted[10]),
.alt_runlengthviolation(rx_runlengthviolation[10]),
.alt_patterndetect(rx_patterndetect[10]),
.alt_runningdisp(rx_runningdisp[10]),
//output (to PCS)
.altpcs_dataout(pcs_rx_frame_10),
.altpcs_sync(link_status[10]),
.altpcs_disperr(led_disp_err_10),
.altpcs_ctrldetect(pcs_rx_kchar_10),
.altpcs_errdetect(led_char_err_gx[10]),
.altpcs_rmfifodatadeleted(pcs_rx_rmfifodatadeleted[10]),
.altpcs_rmfifodatainserted(pcs_rx_rmfifodatainserted[10]),
.altpcs_carrierdetect(pcs_rx_carrierdetected[10])
) ;
defparam
the_altera_tse_gxb_aligned_rxsync_10.DEVICE_FAMILY = DEVICE_FAMILY;
// Altgxb in GIGE mode
// --------------------
altera_tse_gxb_gige_phyip_inst the_altera_tse_gxb_gige_phyip_inst_10
(
.phy_mgmt_clk(clk),
.phy_mgmt_clk_reset(reset),
.phy_mgmt_address(phy_mgmt_address_10),
.phy_mgmt_read(phy_mgmt_read_10),
.phy_mgmt_readdata(phy_mgmt_readdata_10),
.phy_mgmt_waitrequest(phy_mgmt_waitrequest_10),
.phy_mgmt_write(phy_mgmt_write_10),
.phy_mgmt_writedata(phy_mgmt_writedata_10),
.tx_ready(),
.rx_ready(),
.pll_ref_clk(ref_clk),
.pll_locked(),
.tx_serial_data(txp_10),
.rx_serial_data(rxp_10),
.rx_runningdisp(rx_runningdisp[10]),
.rx_disperr(rx_disp_err[10]),
.rx_errdetect(rx_char_err_gx[10]),
.rx_patterndetect(rx_patterndetect[10]),
.rx_syncstatus(rx_syncstatus[10]),
.tx_clkout(tx_pcs_clk_c10),
.rx_clkout(rx_pcs_clk_c10),
.tx_parallel_data(tx_frame_10),
.tx_datak(tx_kchar_10),
.rx_parallel_data(rx_frame_10),
.rx_datak(rx_kchar_10),
.rx_rlv(rx_runlengthviolation[10]),
.rx_recovclkout(rx_recovclkout_10),
.rx_rmfifodatadeleted(rx_rmfifodatadeleted[10]),
.rx_rmfifodatainserted(rx_rmfifodatainserted[10]),
.reconfig_togxb(reconfig_togxb_10),
.reconfig_fromgxb(reconfig_fromgxb_10)
);
defparam
the_altera_tse_gxb_gige_phyip_inst_10.ENABLE_ALT_RECONFIG = ENABLE_ALT_RECONFIG,
the_altera_tse_gxb_gige_phyip_inst_10.ENABLE_SGMII = ENABLE_SGMII,
the_altera_tse_gxb_gige_phyip_inst_10.DEVICE_FAMILY = DEVICE_FAMILY;
end
else
begin
assign reconfig_fromgxb_10 = {92{1'b0}};
assign led_char_err_gx[10] = 1'b0;
assign link_status[10] = 1'b0;
assign led_disp_err_10 = 1'b0;
assign txp_10 = 1'b0;
assign rx_recovclkout_10= 1'b0;
assign phy_mgmt_readdata_10 = 32'b0;
assign phy_mgmt_waitrequest_10 = 1'b0;
end
endgenerate
// #######################################################################
// ############### CHANNEL 11 LOGIC/COMPONENTS ###############
// #######################################################################
generate if (MAX_CHANNELS > 11)
begin
// Instantiation of the Alt2gxb and Alt4gxb block as the PMA for Stratix_II_GX ,ArriaGX and Stratix IV devices
// -----------------------------------------------------------------------------------
// Aligned Rx_sync from gxb
// -------------------------------
altera_tse_reset_synchronizer ch11_reset_sync_0(
.clk(ref_clk),
.reset_in(reset),
.reset_out(reset_rx_pcs_clk_c11_int)
);
altera_tse_gxb_aligned_rxsync the_altera_tse_gxb_aligned_rxsync_11
(
.clk(rx_pcs_clk_c11),
.reset(reset_rx_pcs_clk_c11_int),
//input (from alt2gxb)
.alt_dataout(rx_frame_11),
.alt_sync(rx_syncstatus[11]),
.alt_disperr(rx_disp_err[11]),
.alt_ctrldetect(rx_kchar_11),
.alt_errdetect(rx_char_err_gx[11]),
.alt_rmfifodatadeleted(rx_rmfifodatadeleted[11]),
.alt_rmfifodatainserted(rx_rmfifodatainserted[11]),
.alt_runlengthviolation(rx_runlengthviolation[11]),
.alt_patterndetect(rx_patterndetect[11]),
.alt_runningdisp(rx_runningdisp[11]),
//output (to PCS)
.altpcs_dataout(pcs_rx_frame_11),
.altpcs_sync(link_status[11]),
.altpcs_disperr(led_disp_err_11),
.altpcs_ctrldetect(pcs_rx_kchar_11),
.altpcs_errdetect(led_char_err_gx[11]),
.altpcs_rmfifodatadeleted(pcs_rx_rmfifodatadeleted[11]),
.altpcs_rmfifodatainserted(pcs_rx_rmfifodatainserted[11]),
.altpcs_carrierdetect(pcs_rx_carrierdetected[11])
) ;
defparam
the_altera_tse_gxb_aligned_rxsync_11.DEVICE_FAMILY = DEVICE_FAMILY;
// Altgxb in GIGE mode
// --------------------
altera_tse_gxb_gige_phyip_inst the_altera_tse_gxb_gige_phyip_inst_11
(
.phy_mgmt_clk(clk),
.phy_mgmt_clk_reset(reset),
.phy_mgmt_address(phy_mgmt_address_11),
.phy_mgmt_read(phy_mgmt_read_11),
.phy_mgmt_readdata(phy_mgmt_readdata_11),
.phy_mgmt_waitrequest(phy_mgmt_waitrequest_11),
.phy_mgmt_write(phy_mgmt_write_11),
.phy_mgmt_writedata(phy_mgmt_writedata_11),
.tx_ready(),
.rx_ready(),
.pll_ref_clk(ref_clk),
.pll_locked(),
.tx_serial_data(txp_11),
.rx_serial_data(rxp_11),
.rx_runningdisp(rx_runningdisp[11]),
.rx_disperr(rx_disp_err[11]),
.rx_errdetect(rx_char_err_gx[11]),
.rx_patterndetect(rx_patterndetect[11]),
.rx_syncstatus(rx_syncstatus[11]),
.tx_clkout(tx_pcs_clk_c11),
.rx_clkout(rx_pcs_clk_c11),
.tx_parallel_data(tx_frame_11),
.tx_datak(tx_kchar_11),
.rx_parallel_data(rx_frame_11),
.rx_datak(rx_kchar_11),
.rx_rlv(rx_runlengthviolation[11]),
.rx_recovclkout(rx_recovclkout_11),
.rx_rmfifodatadeleted(rx_rmfifodatadeleted[11]),
.rx_rmfifodatainserted(rx_rmfifodatainserted[11]),
.reconfig_togxb(reconfig_togxb_11),
.reconfig_fromgxb(reconfig_fromgxb_11)
);
defparam
the_altera_tse_gxb_gige_phyip_inst_11.ENABLE_ALT_RECONFIG = ENABLE_ALT_RECONFIG,
the_altera_tse_gxb_gige_phyip_inst_11.ENABLE_SGMII = ENABLE_SGMII,
the_altera_tse_gxb_gige_phyip_inst_11.DEVICE_FAMILY = DEVICE_FAMILY;
end
else
begin
assign reconfig_fromgxb_11 = {92{1'b0}};
assign led_char_err_gx[11] = 1'b0;
assign link_status[11] = 1'b0;
assign led_disp_err_11 = 1'b0;
assign txp_11 = 1'b0;
assign rx_recovclkout_11= 1'b0;
assign phy_mgmt_readdata_11 = 32'b0;
assign phy_mgmt_waitrequest_11 = 1'b0;
end
endgenerate
// #######################################################################
// ############### CHANNEL 12 LOGIC/COMPONENTS ###############
// #######################################################################
generate if (MAX_CHANNELS > 12)
begin
// Instantiation of the Alt2gxb and Alt4gxb block as the PMA for Stratix_II_GX ,ArriaGX and Stratix IV devices
// -----------------------------------------------------------------------------------
// Aligned Rx_sync from gxb
// -------------------------------
altera_tse_reset_synchronizer ch12_reset_sync_0(
.clk(ref_clk),
.reset_in(reset),
.reset_out(reset_rx_pcs_clk_c12_int)
);
altera_tse_gxb_aligned_rxsync the_altera_tse_gxb_aligned_rxsync_12
(
.clk(rx_pcs_clk_c12),
.reset(reset_rx_pcs_clk_c12_int),
//input (from alt2gxb)
.alt_dataout(rx_frame_12),
.alt_sync(rx_syncstatus[12]),
.alt_disperr(rx_disp_err[12]),
.alt_ctrldetect(rx_kchar_12),
.alt_errdetect(rx_char_err_gx[12]),
.alt_rmfifodatadeleted(rx_rmfifodatadeleted[12]),
.alt_rmfifodatainserted(rx_rmfifodatainserted[12]),
.alt_runlengthviolation(rx_runlengthviolation[12]),
.alt_patterndetect(rx_patterndetect[12]),
.alt_runningdisp(rx_runningdisp[12]),
//output (to PCS)
.altpcs_dataout(pcs_rx_frame_12),
.altpcs_sync(link_status[12]),
.altpcs_disperr(led_disp_err_12),
.altpcs_ctrldetect(pcs_rx_kchar_12),
.altpcs_errdetect(led_char_err_gx[12]),
.altpcs_rmfifodatadeleted(pcs_rx_rmfifodatadeleted[12]),
.altpcs_rmfifodatainserted(pcs_rx_rmfifodatainserted[12]),
.altpcs_carrierdetect(pcs_rx_carrierdetected[12])
) ;
defparam
the_altera_tse_gxb_aligned_rxsync_12.DEVICE_FAMILY = DEVICE_FAMILY;
// Altgxb in GIGE mode
// --------------------
altera_tse_gxb_gige_phyip_inst the_altera_tse_gxb_gige_phyip_inst_12
(
.phy_mgmt_clk(clk),
.phy_mgmt_clk_reset(reset),
.phy_mgmt_address(phy_mgmt_address_12),
.phy_mgmt_read(phy_mgmt_read_12),
.phy_mgmt_readdata(phy_mgmt_readdata_12),
.phy_mgmt_waitrequest(phy_mgmt_waitrequest_12),
.phy_mgmt_write(phy_mgmt_write_12),
.phy_mgmt_writedata(phy_mgmt_writedata_12),
.tx_ready(),
.rx_ready(),
.pll_ref_clk(ref_clk),
.pll_locked(),
.tx_serial_data(txp_12),
.rx_serial_data(rxp_12),
.rx_runningdisp(rx_runningdisp[12]),
.rx_disperr(rx_disp_err[12]),
.rx_errdetect(rx_char_err_gx[12]),
.rx_patterndetect(rx_patterndetect[12]),
.rx_syncstatus(rx_syncstatus[12]),
.tx_clkout(tx_pcs_clk_c12),
.rx_clkout(rx_pcs_clk_c12),
.tx_parallel_data(tx_frame_12),
.tx_datak(tx_kchar_12),
.rx_parallel_data(rx_frame_12),
.rx_datak(rx_kchar_12),
.rx_rlv(rx_runlengthviolation[12]),
.rx_recovclkout(rx_recovclkout_12),
.rx_rmfifodatadeleted(rx_rmfifodatadeleted[12]),
.rx_rmfifodatainserted(rx_rmfifodatainserted[12]),
.reconfig_togxb(reconfig_togxb_12),
.reconfig_fromgxb(reconfig_fromgxb_12)
);
defparam
the_altera_tse_gxb_gige_phyip_inst_12.ENABLE_ALT_RECONFIG = ENABLE_ALT_RECONFIG,
the_altera_tse_gxb_gige_phyip_inst_12.ENABLE_SGMII = ENABLE_SGMII,
the_altera_tse_gxb_gige_phyip_inst_12.DEVICE_FAMILY = DEVICE_FAMILY;
end
else
begin
assign reconfig_fromgxb_12 = {92{1'b0}};
assign led_char_err_gx[12] = 1'b0;
assign link_status[12] = 1'b0;
assign led_disp_err_12 = 1'b0;
assign txp_12 = 1'b0;
assign rx_recovclkout_12= 1'b0;
assign phy_mgmt_readdata_12 = 32'b0;
assign phy_mgmt_waitrequest_12 = 1'b0;
end
endgenerate
// #######################################################################
// ############### CHANNEL 13 LOGIC/COMPONENTS ###############
// #######################################################################
generate if (MAX_CHANNELS > 13)
begin
// Instantiation of the Alt2gxb and Alt4gxb block as the PMA for Stratix_II_GX ,ArriaGX and Stratix IV devices
// -----------------------------------------------------------------------------------
// Aligned Rx_sync from gxb
// -------------------------------
altera_tse_reset_synchronizer ch13_reset_sync_0(
.clk(ref_clk),
.reset_in(reset),
.reset_out(reset_rx_pcs_clk_c13_int)
);
altera_tse_gxb_aligned_rxsync the_altera_tse_gxb_aligned_rxsync_13
(
.clk(rx_pcs_clk_c13),
.reset(reset_rx_pcs_clk_c13_int),
//input (from alt2gxb)
.alt_dataout(rx_frame_13),
.alt_sync(rx_syncstatus[13]),
.alt_disperr(rx_disp_err[13]),
.alt_ctrldetect(rx_kchar_13),
.alt_errdetect(rx_char_err_gx[13]),
.alt_rmfifodatadeleted(rx_rmfifodatadeleted[13]),
.alt_rmfifodatainserted(rx_rmfifodatainserted[13]),
.alt_runlengthviolation(rx_runlengthviolation[13]),
.alt_patterndetect(rx_patterndetect[13]),
.alt_runningdisp(rx_runningdisp[13]),
//output (to PCS)
.altpcs_dataout(pcs_rx_frame_13),
.altpcs_sync(link_status[13]),
.altpcs_disperr(led_disp_err_13),
.altpcs_ctrldetect(pcs_rx_kchar_13),
.altpcs_errdetect(led_char_err_gx[13]),
.altpcs_rmfifodatadeleted(pcs_rx_rmfifodatadeleted[13]),
.altpcs_rmfifodatainserted(pcs_rx_rmfifodatainserted[13]),
.altpcs_carrierdetect(pcs_rx_carrierdetected[13])
) ;
defparam
the_altera_tse_gxb_aligned_rxsync_13.DEVICE_FAMILY = DEVICE_FAMILY;
// Altgxb in GIGE mode
// --------------------
altera_tse_gxb_gige_phyip_inst the_altera_tse_gxb_gige_phyip_inst_13
(
.phy_mgmt_clk(clk),
.phy_mgmt_clk_reset(reset),
.phy_mgmt_address(phy_mgmt_address_13),
.phy_mgmt_read(phy_mgmt_read_13),
.phy_mgmt_readdata(phy_mgmt_readdata_13),
.phy_mgmt_waitrequest(phy_mgmt_waitrequest_13),
.phy_mgmt_write(phy_mgmt_write_13),
.phy_mgmt_writedata(phy_mgmt_writedata_13),
.tx_ready(),
.rx_ready(),
.pll_ref_clk(ref_clk),
.pll_locked(),
.tx_serial_data(txp_13),
.rx_serial_data(rxp_13),
.rx_runningdisp(rx_runningdisp[13]),
.rx_disperr(rx_disp_err[13]),
.rx_errdetect(rx_char_err_gx[13]),
.rx_patterndetect(rx_patterndetect[13]),
.rx_syncstatus(rx_syncstatus[13]),
.tx_clkout(tx_pcs_clk_c13),
.rx_clkout(rx_pcs_clk_c13),
.tx_parallel_data(tx_frame_13),
.tx_datak(tx_kchar_13),
.rx_parallel_data(rx_frame_13),
.rx_datak(rx_kchar_13),
.rx_rlv(rx_runlengthviolation[13]),
.rx_recovclkout(rx_recovclkout_13),
.rx_rmfifodatadeleted(rx_rmfifodatadeleted[13]),
.rx_rmfifodatainserted(rx_rmfifodatainserted[13]),
.reconfig_togxb(reconfig_togxb_13),
.reconfig_fromgxb(reconfig_fromgxb_13)
);
defparam
the_altera_tse_gxb_gige_phyip_inst_13.ENABLE_ALT_RECONFIG = ENABLE_ALT_RECONFIG,
the_altera_tse_gxb_gige_phyip_inst_13.ENABLE_SGMII = ENABLE_SGMII,
the_altera_tse_gxb_gige_phyip_inst_13.DEVICE_FAMILY = DEVICE_FAMILY;
end
else
begin
assign reconfig_fromgxb_13 = {92{1'b0}};
assign led_char_err_gx[13] = 1'b0;
assign link_status[13] = 1'b0;
assign led_disp_err_13 = 1'b0;
assign txp_13 = 1'b0;
assign rx_recovclkout_13= 1'b0;
assign phy_mgmt_readdata_13 = 32'b0;
assign phy_mgmt_waitrequest_13 = 1'b0;
end
endgenerate
// #######################################################################
// ############### CHANNEL 14 LOGIC/COMPONENTS ###############
// #######################################################################
generate if (MAX_CHANNELS > 14)
begin
// Instantiation of the Alt2gxb and Alt4gxb block as the PMA for Stratix_II_GX ,ArriaGX and Stratix IV devices
// -----------------------------------------------------------------------------------
// Aligned Rx_sync from gxb
// -------------------------------
altera_tse_reset_synchronizer ch14_reset_sync_0(
.clk(ref_clk),
.reset_in(reset),
.reset_out(reset_rx_pcs_clk_c14_int)
);
altera_tse_gxb_aligned_rxsync the_altera_tse_gxb_aligned_rxsync_14
(
.clk(rx_pcs_clk_c14),
.reset(reset_rx_pcs_clk_c14_int),
//input (from alt2gxb)
.alt_dataout(rx_frame_14),
.alt_sync(rx_syncstatus[14]),
.alt_disperr(rx_disp_err[14]),
.alt_ctrldetect(rx_kchar_14),
.alt_errdetect(rx_char_err_gx[14]),
.alt_rmfifodatadeleted(rx_rmfifodatadeleted[14]),
.alt_rmfifodatainserted(rx_rmfifodatainserted[14]),
.alt_runlengthviolation(rx_runlengthviolation[14]),
.alt_patterndetect(rx_patterndetect[14]),
.alt_runningdisp(rx_runningdisp[14]),
//output (to PCS)
.altpcs_dataout(pcs_rx_frame_14),
.altpcs_sync(link_status[14]),
.altpcs_disperr(led_disp_err_14),
.altpcs_ctrldetect(pcs_rx_kchar_14),
.altpcs_errdetect(led_char_err_gx[14]),
.altpcs_rmfifodatadeleted(pcs_rx_rmfifodatadeleted[14]),
.altpcs_rmfifodatainserted(pcs_rx_rmfifodatainserted[14]),
.altpcs_carrierdetect(pcs_rx_carrierdetected[14])
) ;
defparam
the_altera_tse_gxb_aligned_rxsync_14.DEVICE_FAMILY = DEVICE_FAMILY;
// Altgxb in GIGE mode
// --------------------
altera_tse_gxb_gige_phyip_inst the_altera_tse_gxb_gige_phyip_inst_14
(
.phy_mgmt_clk(clk),
.phy_mgmt_clk_reset(reset),
.phy_mgmt_address(phy_mgmt_address_14),
.phy_mgmt_read(phy_mgmt_read_14),
.phy_mgmt_readdata(phy_mgmt_readdata_14),
.phy_mgmt_waitrequest(phy_mgmt_waitrequest_14),
.phy_mgmt_write(phy_mgmt_write_14),
.phy_mgmt_writedata(phy_mgmt_writedata_14),
.tx_ready(),
.rx_ready(),
.pll_ref_clk(ref_clk),
.pll_locked(),
.tx_serial_data(txp_14),
.rx_serial_data(rxp_14),
.rx_runningdisp(rx_runningdisp[14]),
.rx_disperr(rx_disp_err[14]),
.rx_errdetect(rx_char_err_gx[14]),
.rx_patterndetect(rx_patterndetect[14]),
.rx_syncstatus(rx_syncstatus[14]),
.tx_clkout(tx_pcs_clk_c14),
.rx_clkout(rx_pcs_clk_c14),
.tx_parallel_data(tx_frame_14),
.tx_datak(tx_kchar_14),
.rx_parallel_data(rx_frame_14),
.rx_datak(rx_kchar_14),
.rx_rlv(rx_runlengthviolation[14]),
.rx_recovclkout(rx_recovclkout_14),
.rx_rmfifodatadeleted(rx_rmfifodatadeleted[14]),
.rx_rmfifodatainserted(rx_rmfifodatainserted[14]),
.reconfig_togxb(reconfig_togxb_14),
.reconfig_fromgxb(reconfig_fromgxb_14)
);
defparam
the_altera_tse_gxb_gige_phyip_inst_14.ENABLE_ALT_RECONFIG = ENABLE_ALT_RECONFIG,
the_altera_tse_gxb_gige_phyip_inst_14.ENABLE_SGMII = ENABLE_SGMII,
the_altera_tse_gxb_gige_phyip_inst_14.DEVICE_FAMILY = DEVICE_FAMILY;
end
else
begin
assign reconfig_fromgxb_14 = {92{1'b0}};
assign led_char_err_gx[14] = 1'b0;
assign link_status[14] = 1'b0;
assign led_disp_err_14 = 1'b0;
assign txp_14 = 1'b0;
assign rx_recovclkout_14= 1'b0;
assign phy_mgmt_readdata_14 = 32'b0;
assign phy_mgmt_waitrequest_14 = 1'b0;
end
endgenerate
// #######################################################################
// ############### CHANNEL 15 LOGIC/COMPONENTS ###############
// #######################################################################
generate if (MAX_CHANNELS > 15)
begin
// Instantiation of the Alt2gxb and Alt4gxb block as the PMA for Stratix_II_GX ,ArriaGX and Stratix IV devices
// -----------------------------------------------------------------------------------
// Aligned Rx_sync from gxb
// -------------------------------
altera_tse_reset_synchronizer ch15_reset_sync_0(
.clk(ref_clk),
.reset_in(reset),
.reset_out(reset_rx_pcs_clk_c15_int)
);
altera_tse_gxb_aligned_rxsync the_altera_tse_gxb_aligned_rxsync_15
(
.clk(rx_pcs_clk_c15),
.reset(reset_rx_pcs_clk_c15_int),
//input (from alt2gxb)
.alt_dataout(rx_frame_15),
.alt_sync(rx_syncstatus[15]),
.alt_disperr(rx_disp_err[15]),
.alt_ctrldetect(rx_kchar_15),
.alt_errdetect(rx_char_err_gx[15]),
.alt_rmfifodatadeleted(rx_rmfifodatadeleted[15]),
.alt_rmfifodatainserted(rx_rmfifodatainserted[15]),
.alt_runlengthviolation(rx_runlengthviolation[15]),
.alt_patterndetect(rx_patterndetect[15]),
.alt_runningdisp(rx_runningdisp[15]),
//output (to PCS)
.altpcs_dataout(pcs_rx_frame_15),
.altpcs_sync(link_status[15]),
.altpcs_disperr(led_disp_err_15),
.altpcs_ctrldetect(pcs_rx_kchar_15),
.altpcs_errdetect(led_char_err_gx[15]),
.altpcs_rmfifodatadeleted(pcs_rx_rmfifodatadeleted[15]),
.altpcs_rmfifodatainserted(pcs_rx_rmfifodatainserted[15]),
.altpcs_carrierdetect(pcs_rx_carrierdetected[15])
) ;
defparam
the_altera_tse_gxb_aligned_rxsync_15.DEVICE_FAMILY = DEVICE_FAMILY;
// Altgxb in GIGE mode
// --------------------
altera_tse_gxb_gige_phyip_inst the_altera_tse_gxb_gige_phyip_inst_15
(
.phy_mgmt_clk(clk),
.phy_mgmt_clk_reset(reset),
.phy_mgmt_address(phy_mgmt_address_15),
.phy_mgmt_read(phy_mgmt_read_15),
.phy_mgmt_readdata(phy_mgmt_readdata_15),
.phy_mgmt_waitrequest(phy_mgmt_waitrequest_15),
.phy_mgmt_write(phy_mgmt_write_15),
.phy_mgmt_writedata(phy_mgmt_writedata_15),
.tx_ready(),
.rx_ready(),
.pll_ref_clk(ref_clk),
.pll_locked(),
.tx_serial_data(txp_15),
.rx_serial_data(rxp_15),
.rx_runningdisp(rx_runningdisp[15]),
.rx_disperr(rx_disp_err[15]),
.rx_errdetect(rx_char_err_gx[15]),
.rx_patterndetect(rx_patterndetect[15]),
.rx_syncstatus(rx_syncstatus[15]),
.tx_clkout(tx_pcs_clk_c15),
.rx_clkout(rx_pcs_clk_c15),
.tx_parallel_data(tx_frame_15),
.tx_datak(tx_kchar_15),
.rx_parallel_data(rx_frame_15),
.rx_datak(rx_kchar_15),
.rx_rlv(rx_runlengthviolation[15]),
.rx_recovclkout(rx_recovclkout_15),
.rx_rmfifodatadeleted(rx_rmfifodatadeleted[15]),
.rx_rmfifodatainserted(rx_rmfifodatainserted[15]),
.reconfig_togxb(reconfig_togxb_15),
.reconfig_fromgxb(reconfig_fromgxb_15)
);
defparam
the_altera_tse_gxb_gige_phyip_inst_15.ENABLE_ALT_RECONFIG = ENABLE_ALT_RECONFIG,
the_altera_tse_gxb_gige_phyip_inst_15.ENABLE_SGMII = ENABLE_SGMII,
the_altera_tse_gxb_gige_phyip_inst_15.DEVICE_FAMILY = DEVICE_FAMILY;
end
else
begin
assign reconfig_fromgxb_15 = {92{1'b0}};
assign led_char_err_gx[15] = 1'b0;
assign link_status[15] = 1'b0;
assign led_disp_err_15 = 1'b0;
assign txp_15 = 1'b0;
assign rx_recovclkout_15= 1'b0;
assign phy_mgmt_readdata_15 = 32'b0;
assign phy_mgmt_waitrequest_15 = 1'b0;
end
endgenerate
// #######################################################################
// ############### CHANNEL 16 LOGIC/COMPONENTS ###############
// #######################################################################
generate if (MAX_CHANNELS > 16)
begin
// Instantiation of the Alt2gxb and Alt4gxb block as the PMA for Stratix_II_GX ,ArriaGX and Stratix IV devices
// -----------------------------------------------------------------------------------
// Aligned Rx_sync from gxb
// -------------------------------
altera_tse_reset_synchronizer ch16_reset_sync_0(
.clk(ref_clk),
.reset_in(reset),
.reset_out(reset_rx_pcs_clk_c16_int)
);
altera_tse_gxb_aligned_rxsync the_altera_tse_gxb_aligned_rxsync_16
(
.clk(rx_pcs_clk_c16),
.reset(reset_rx_pcs_clk_c16_int),
//input (from alt2gxb)
.alt_dataout(rx_frame_16),
.alt_sync(rx_syncstatus[16]),
.alt_disperr(rx_disp_err[16]),
.alt_ctrldetect(rx_kchar_16),
.alt_errdetect(rx_char_err_gx[16]),
.alt_rmfifodatadeleted(rx_rmfifodatadeleted[16]),
.alt_rmfifodatainserted(rx_rmfifodatainserted[16]),
.alt_runlengthviolation(rx_runlengthviolation[16]),
.alt_patterndetect(rx_patterndetect[16]),
.alt_runningdisp(rx_runningdisp[16]),
//output (to PCS)
.altpcs_dataout(pcs_rx_frame_16),
.altpcs_sync(link_status[16]),
.altpcs_disperr(led_disp_err_16),
.altpcs_ctrldetect(pcs_rx_kchar_16),
.altpcs_errdetect(led_char_err_gx[16]),
.altpcs_rmfifodatadeleted(pcs_rx_rmfifodatadeleted[16]),
.altpcs_rmfifodatainserted(pcs_rx_rmfifodatainserted[16]),
.altpcs_carrierdetect(pcs_rx_carrierdetected[16])
) ;
defparam
the_altera_tse_gxb_aligned_rxsync_16.DEVICE_FAMILY = DEVICE_FAMILY;
// Altgxb in GIGE mode
// --------------------
altera_tse_gxb_gige_phyip_inst the_altera_tse_gxb_gige_phyip_inst_16
(
.phy_mgmt_clk(clk),
.phy_mgmt_clk_reset(reset),
.phy_mgmt_address(phy_mgmt_address_16),
.phy_mgmt_read(phy_mgmt_read_16),
.phy_mgmt_readdata(phy_mgmt_readdata_16),
.phy_mgmt_waitrequest(phy_mgmt_waitrequest_16),
.phy_mgmt_write(phy_mgmt_write_16),
.phy_mgmt_writedata(phy_mgmt_writedata_16),
.tx_ready(),
.rx_ready(),
.pll_ref_clk(ref_clk),
.pll_locked(),
.tx_serial_data(txp_16),
.rx_serial_data(rxp_16),
.rx_runningdisp(rx_runningdisp[16]),
.rx_disperr(rx_disp_err[16]),
.rx_errdetect(rx_char_err_gx[16]),
.rx_patterndetect(rx_patterndetect[16]),
.rx_syncstatus(rx_syncstatus[16]),
.tx_clkout(tx_pcs_clk_c16),
.rx_clkout(rx_pcs_clk_c16),
.tx_parallel_data(tx_frame_16),
.tx_datak(tx_kchar_16),
.rx_parallel_data(rx_frame_16),
.rx_datak(rx_kchar_16),
.rx_rlv(rx_runlengthviolation[16]),
.rx_recovclkout(rx_recovclkout_16),
.rx_rmfifodatadeleted(rx_rmfifodatadeleted[16]),
.rx_rmfifodatainserted(rx_rmfifodatainserted[16]),
.reconfig_togxb(reconfig_togxb_16),
.reconfig_fromgxb(reconfig_fromgxb_16)
);
defparam
the_altera_tse_gxb_gige_phyip_inst_16.ENABLE_ALT_RECONFIG = ENABLE_ALT_RECONFIG,
the_altera_tse_gxb_gige_phyip_inst_16.ENABLE_SGMII = ENABLE_SGMII,
the_altera_tse_gxb_gige_phyip_inst_16.DEVICE_FAMILY = DEVICE_FAMILY;
end
else
begin
assign reconfig_fromgxb_16 = {92{1'b0}};
assign led_char_err_gx[16] = 1'b0;
assign link_status[16] = 1'b0;
assign led_disp_err_16 = 1'b0;
assign txp_16 = 1'b0;
assign rx_recovclkout_16= 1'b0;
assign phy_mgmt_readdata_16 = 32'b0;
assign phy_mgmt_waitrequest_16 = 1'b0;
end
endgenerate
// #######################################################################
// ############### CHANNEL 17 LOGIC/COMPONENTS ###############
// #######################################################################
generate if (MAX_CHANNELS > 17)
begin
// Instantiation of the Alt2gxb and Alt4gxb block as the PMA for Stratix_II_GX ,ArriaGX and Stratix IV devices
// -----------------------------------------------------------------------------------
// Aligned Rx_sync from gxb
// -------------------------------
altera_tse_reset_synchronizer ch17_reset_sync_0(
.clk(ref_clk),
.reset_in(reset),
.reset_out(reset_rx_pcs_clk_c17_int)
);
altera_tse_gxb_aligned_rxsync the_altera_tse_gxb_aligned_rxsync_17
(
.clk(rx_pcs_clk_c17),
.reset(reset_rx_pcs_clk_c17_int),
//input (from alt2gxb)
.alt_dataout(rx_frame_17),
.alt_sync(rx_syncstatus[17]),
.alt_disperr(rx_disp_err[17]),
.alt_ctrldetect(rx_kchar_17),
.alt_errdetect(rx_char_err_gx[17]),
.alt_rmfifodatadeleted(rx_rmfifodatadeleted[17]),
.alt_rmfifodatainserted(rx_rmfifodatainserted[17]),
.alt_runlengthviolation(rx_runlengthviolation[17]),
.alt_patterndetect(rx_patterndetect[17]),
.alt_runningdisp(rx_runningdisp[17]),
//output (to PCS)
.altpcs_dataout(pcs_rx_frame_17),
.altpcs_sync(link_status[17]),
.altpcs_disperr(led_disp_err_17),
.altpcs_ctrldetect(pcs_rx_kchar_17),
.altpcs_errdetect(led_char_err_gx[17]),
.altpcs_rmfifodatadeleted(pcs_rx_rmfifodatadeleted[17]),
.altpcs_rmfifodatainserted(pcs_rx_rmfifodatainserted[17]),
.altpcs_carrierdetect(pcs_rx_carrierdetected[17])
) ;
defparam
the_altera_tse_gxb_aligned_rxsync_17.DEVICE_FAMILY = DEVICE_FAMILY;
// Altgxb in GIGE mode
// --------------------
altera_tse_gxb_gige_phyip_inst the_altera_tse_gxb_gige_phyip_inst_17
(
.phy_mgmt_clk(clk),
.phy_mgmt_clk_reset(reset),
.phy_mgmt_address(phy_mgmt_address_17),
.phy_mgmt_read(phy_mgmt_read_17),
.phy_mgmt_readdata(phy_mgmt_readdata_17),
.phy_mgmt_waitrequest(phy_mgmt_waitrequest_17),
.phy_mgmt_write(phy_mgmt_write_17),
.phy_mgmt_writedata(phy_mgmt_writedata_17),
.tx_ready(),
.rx_ready(),
.pll_ref_clk(ref_clk),
.pll_locked(),
.tx_serial_data(txp_17),
.rx_serial_data(rxp_17),
.rx_runningdisp(rx_runningdisp[17]),
.rx_disperr(rx_disp_err[17]),
.rx_errdetect(rx_char_err_gx[17]),
.rx_patterndetect(rx_patterndetect[17]),
.rx_syncstatus(rx_syncstatus[17]),
.tx_clkout(tx_pcs_clk_c17),
.rx_clkout(rx_pcs_clk_c17),
.tx_parallel_data(tx_frame_17),
.tx_datak(tx_kchar_17),
.rx_parallel_data(rx_frame_17),
.rx_datak(rx_kchar_17),
.rx_rlv(rx_runlengthviolation[17]),
.rx_recovclkout(rx_recovclkout_17),
.rx_rmfifodatadeleted(rx_rmfifodatadeleted[17]),
.rx_rmfifodatainserted(rx_rmfifodatainserted[17]),
.reconfig_togxb(reconfig_togxb_17),
.reconfig_fromgxb(reconfig_fromgxb_17)
);
defparam
the_altera_tse_gxb_gige_phyip_inst_17.ENABLE_ALT_RECONFIG = ENABLE_ALT_RECONFIG,
the_altera_tse_gxb_gige_phyip_inst_17.ENABLE_SGMII = ENABLE_SGMII,
the_altera_tse_gxb_gige_phyip_inst_17.DEVICE_FAMILY = DEVICE_FAMILY;
end
else
begin
assign reconfig_fromgxb_17 = {92{1'b0}};
assign led_char_err_gx[17] = 1'b0;
assign link_status[17] = 1'b0;
assign led_disp_err_17 = 1'b0;
assign txp_17 = 1'b0;
assign rx_recovclkout_17= 1'b0;
assign phy_mgmt_readdata_17 = 32'b0;
assign phy_mgmt_waitrequest_17 = 1'b0;
end
endgenerate
// #######################################################################
// ############### CHANNEL 18 LOGIC/COMPONENTS ###############
// #######################################################################
generate if (MAX_CHANNELS > 18)
begin
// Instantiation of the Alt2gxb and Alt4gxb block as the PMA for Stratix_II_GX ,ArriaGX and Stratix IV devices
// -----------------------------------------------------------------------------------
// Aligned Rx_sync from gxb
// -------------------------------
altera_tse_reset_synchronizer ch18_reset_sync_0(
.clk(ref_clk),
.reset_in(reset),
.reset_out(reset_rx_pcs_clk_c18_int)
);
altera_tse_gxb_aligned_rxsync the_altera_tse_gxb_aligned_rxsync_18
(
.clk(rx_pcs_clk_c18),
.reset(reset_rx_pcs_clk_c18_int),
//input (from alt2gxb)
.alt_dataout(rx_frame_18),
.alt_sync(rx_syncstatus[18]),
.alt_disperr(rx_disp_err[18]),
.alt_ctrldetect(rx_kchar_18),
.alt_errdetect(rx_char_err_gx[18]),
.alt_rmfifodatadeleted(rx_rmfifodatadeleted[18]),
.alt_rmfifodatainserted(rx_rmfifodatainserted[18]),
.alt_runlengthviolation(rx_runlengthviolation[18]),
.alt_patterndetect(rx_patterndetect[18]),
.alt_runningdisp(rx_runningdisp[18]),
//output (to PCS)
.altpcs_dataout(pcs_rx_frame_18),
.altpcs_sync(link_status[18]),
.altpcs_disperr(led_disp_err_18),
.altpcs_ctrldetect(pcs_rx_kchar_18),
.altpcs_errdetect(led_char_err_gx[18]),
.altpcs_rmfifodatadeleted(pcs_rx_rmfifodatadeleted[18]),
.altpcs_rmfifodatainserted(pcs_rx_rmfifodatainserted[18]),
.altpcs_carrierdetect(pcs_rx_carrierdetected[18])
) ;
defparam
the_altera_tse_gxb_aligned_rxsync_18.DEVICE_FAMILY = DEVICE_FAMILY;
// Altgxb in GIGE mode
// --------------------
altera_tse_gxb_gige_phyip_inst the_altera_tse_gxb_gige_phyip_inst_18
(
.phy_mgmt_clk(clk),
.phy_mgmt_clk_reset(reset),
.phy_mgmt_address(phy_mgmt_address_18),
.phy_mgmt_read(phy_mgmt_read_18),
.phy_mgmt_readdata(phy_mgmt_readdata_18),
.phy_mgmt_waitrequest(phy_mgmt_waitrequest_18),
.phy_mgmt_write(phy_mgmt_write_18),
.phy_mgmt_writedata(phy_mgmt_writedata_18),
.tx_ready(),
.rx_ready(),
.pll_ref_clk(ref_clk),
.pll_locked(),
.tx_serial_data(txp_18),
.rx_serial_data(rxp_18),
.rx_runningdisp(rx_runningdisp[18]),
.rx_disperr(rx_disp_err[18]),
.rx_errdetect(rx_char_err_gx[18]),
.rx_patterndetect(rx_patterndetect[18]),
.rx_syncstatus(rx_syncstatus[18]),
.tx_clkout(tx_pcs_clk_c18),
.rx_clkout(rx_pcs_clk_c18),
.tx_parallel_data(tx_frame_18),
.tx_datak(tx_kchar_18),
.rx_parallel_data(rx_frame_18),
.rx_datak(rx_kchar_18),
.rx_rlv(rx_runlengthviolation[18]),
.rx_recovclkout(rx_recovclkout_18),
.rx_rmfifodatadeleted(rx_rmfifodatadeleted[18]),
.rx_rmfifodatainserted(rx_rmfifodatainserted[18]),
.reconfig_togxb(reconfig_togxb_18),
.reconfig_fromgxb(reconfig_fromgxb_18)
);
defparam
the_altera_tse_gxb_gige_phyip_inst_18.ENABLE_ALT_RECONFIG = ENABLE_ALT_RECONFIG,
the_altera_tse_gxb_gige_phyip_inst_18.ENABLE_SGMII = ENABLE_SGMII,
the_altera_tse_gxb_gige_phyip_inst_18.DEVICE_FAMILY = DEVICE_FAMILY;
end
else
begin
assign reconfig_fromgxb_18 = {92{1'b0}};
assign led_char_err_gx[18] = 1'b0;
assign link_status[18] = 1'b0;
assign led_disp_err_18 = 1'b0;
assign txp_18 = 1'b0;
assign rx_recovclkout_18= 1'b0;
assign phy_mgmt_readdata_18 = 32'b0;
assign phy_mgmt_waitrequest_18 = 1'b0;
end
endgenerate
// #######################################################################
// ############### CHANNEL 19 LOGIC/COMPONENTS ###############
// #######################################################################
generate if (MAX_CHANNELS > 19)
begin
// Instantiation of the Alt2gxb and Alt4gxb block as the PMA for Stratix_II_GX ,ArriaGX and Stratix IV devices
// -----------------------------------------------------------------------------------
// Aligned Rx_sync from gxb
// -------------------------------
altera_tse_reset_synchronizer ch19_reset_sync_0(
.clk(ref_clk),
.reset_in(reset),
.reset_out(reset_rx_pcs_clk_c19_int)
);
altera_tse_gxb_aligned_rxsync the_altera_tse_gxb_aligned_rxsync_19
(
.clk(rx_pcs_clk_c19),
.reset(reset_rx_pcs_clk_c19_int),
//input (from alt2gxb)
.alt_dataout(rx_frame_19),
.alt_sync(rx_syncstatus[19]),
.alt_disperr(rx_disp_err[19]),
.alt_ctrldetect(rx_kchar_19),
.alt_errdetect(rx_char_err_gx[19]),
.alt_rmfifodatadeleted(rx_rmfifodatadeleted[19]),
.alt_rmfifodatainserted(rx_rmfifodatainserted[19]),
.alt_runlengthviolation(rx_runlengthviolation[19]),
.alt_patterndetect(rx_patterndetect[19]),
.alt_runningdisp(rx_runningdisp[19]),
//output (to PCS)
.altpcs_dataout(pcs_rx_frame_19),
.altpcs_sync(link_status[19]),
.altpcs_disperr(led_disp_err_19),
.altpcs_ctrldetect(pcs_rx_kchar_19),
.altpcs_errdetect(led_char_err_gx[19]),
.altpcs_rmfifodatadeleted(pcs_rx_rmfifodatadeleted[19]),
.altpcs_rmfifodatainserted(pcs_rx_rmfifodatainserted[19]),
.altpcs_carrierdetect(pcs_rx_carrierdetected[19])
) ;
defparam
the_altera_tse_gxb_aligned_rxsync_19.DEVICE_FAMILY = DEVICE_FAMILY;
// Altgxb in GIGE mode
// --------------------
altera_tse_gxb_gige_phyip_inst the_altera_tse_gxb_gige_phyip_inst_19
(
.phy_mgmt_clk(clk),
.phy_mgmt_clk_reset(reset),
.phy_mgmt_address(phy_mgmt_address_19),
.phy_mgmt_read(phy_mgmt_read_19),
.phy_mgmt_readdata(phy_mgmt_readdata_19),
.phy_mgmt_waitrequest(phy_mgmt_waitrequest_19),
.phy_mgmt_write(phy_mgmt_write_19),
.phy_mgmt_writedata(phy_mgmt_writedata_19),
.tx_ready(),
.rx_ready(),
.pll_ref_clk(ref_clk),
.pll_locked(),
.tx_serial_data(txp_19),
.rx_serial_data(rxp_19),
.rx_runningdisp(rx_runningdisp[19]),
.rx_disperr(rx_disp_err[19]),
.rx_errdetect(rx_char_err_gx[19]),
.rx_patterndetect(rx_patterndetect[19]),
.rx_syncstatus(rx_syncstatus[19]),
.tx_clkout(tx_pcs_clk_c19),
.rx_clkout(rx_pcs_clk_c19),
.tx_parallel_data(tx_frame_19),
.tx_datak(tx_kchar_19),
.rx_parallel_data(rx_frame_19),
.rx_datak(rx_kchar_19),
.rx_rlv(rx_runlengthviolation[19]),
.rx_recovclkout(rx_recovclkout_19),
.rx_rmfifodatadeleted(rx_rmfifodatadeleted[19]),
.rx_rmfifodatainserted(rx_rmfifodatainserted[19]),
.reconfig_togxb(reconfig_togxb_19),
.reconfig_fromgxb(reconfig_fromgxb_19)
);
defparam
the_altera_tse_gxb_gige_phyip_inst_19.ENABLE_ALT_RECONFIG = ENABLE_ALT_RECONFIG,
the_altera_tse_gxb_gige_phyip_inst_19.ENABLE_SGMII = ENABLE_SGMII,
the_altera_tse_gxb_gige_phyip_inst_19.DEVICE_FAMILY = DEVICE_FAMILY;
end
else
begin
assign reconfig_fromgxb_19 = {92{1'b0}};
assign led_char_err_gx[19] = 1'b0;
assign link_status[19] = 1'b0;
assign led_disp_err_19 = 1'b0;
assign txp_19 = 1'b0;
assign rx_recovclkout_19= 1'b0;
assign phy_mgmt_readdata_19 = 32'b0;
assign phy_mgmt_waitrequest_19 = 1'b0;
end
endgenerate
// #######################################################################
// ############### CHANNEL 20 LOGIC/COMPONENTS ###############
// #######################################################################
generate if (MAX_CHANNELS > 20)
begin
// Instantiation of the Alt2gxb and Alt4gxb block as the PMA for Stratix_II_GX ,ArriaGX and Stratix IV devices
// -----------------------------------------------------------------------------------
// Aligned Rx_sync from gxb
// -------------------------------
altera_tse_reset_synchronizer ch20_reset_sync_0(
.clk(ref_clk),
.reset_in(reset),
.reset_out(reset_rx_pcs_clk_c20_int)
);
altera_tse_gxb_aligned_rxsync the_altera_tse_gxb_aligned_rxsync_20
(
.clk(rx_pcs_clk_c20),
.reset(reset_rx_pcs_clk_c20_int),
//input (from alt2gxb)
.alt_dataout(rx_frame_20),
.alt_sync(rx_syncstatus[20]),
.alt_disperr(rx_disp_err[20]),
.alt_ctrldetect(rx_kchar_20),
.alt_errdetect(rx_char_err_gx[20]),
.alt_rmfifodatadeleted(rx_rmfifodatadeleted[20]),
.alt_rmfifodatainserted(rx_rmfifodatainserted[20]),
.alt_runlengthviolation(rx_runlengthviolation[20]),
.alt_patterndetect(rx_patterndetect[20]),
.alt_runningdisp(rx_runningdisp[20]),
//output (to PCS)
.altpcs_dataout(pcs_rx_frame_20),
.altpcs_sync(link_status[20]),
.altpcs_disperr(led_disp_err_20),
.altpcs_ctrldetect(pcs_rx_kchar_20),
.altpcs_errdetect(led_char_err_gx[20]),
.altpcs_rmfifodatadeleted(pcs_rx_rmfifodatadeleted[20]),
.altpcs_rmfifodatainserted(pcs_rx_rmfifodatainserted[20]),
.altpcs_carrierdetect(pcs_rx_carrierdetected[20])
) ;
defparam
the_altera_tse_gxb_aligned_rxsync_20.DEVICE_FAMILY = DEVICE_FAMILY;
// Altgxb in GIGE mode
// --------------------
altera_tse_gxb_gige_phyip_inst the_altera_tse_gxb_gige_phyip_inst_20
(
.phy_mgmt_clk(clk),
.phy_mgmt_clk_reset(reset),
.phy_mgmt_address(phy_mgmt_address_20),
.phy_mgmt_read(phy_mgmt_read_20),
.phy_mgmt_readdata(phy_mgmt_readdata_20),
.phy_mgmt_waitrequest(phy_mgmt_waitrequest_20),
.phy_mgmt_write(phy_mgmt_write_20),
.phy_mgmt_writedata(phy_mgmt_writedata_20),
.tx_ready(),
.rx_ready(),
.pll_ref_clk(ref_clk),
.pll_locked(),
.tx_serial_data(txp_20),
.rx_serial_data(rxp_20),
.rx_runningdisp(rx_runningdisp[20]),
.rx_disperr(rx_disp_err[20]),
.rx_errdetect(rx_char_err_gx[20]),
.rx_patterndetect(rx_patterndetect[20]),
.rx_syncstatus(rx_syncstatus[20]),
.tx_clkout(tx_pcs_clk_c20),
.rx_clkout(rx_pcs_clk_c20),
.tx_parallel_data(tx_frame_20),
.tx_datak(tx_kchar_20),
.rx_parallel_data(rx_frame_20),
.rx_datak(rx_kchar_20),
.rx_rlv(rx_runlengthviolation[20]),
.rx_recovclkout(rx_recovclkout_20),
.rx_rmfifodatadeleted(rx_rmfifodatadeleted[20]),
.rx_rmfifodatainserted(rx_rmfifodatainserted[20]),
.reconfig_togxb(reconfig_togxb_20),
.reconfig_fromgxb(reconfig_fromgxb_20)
);
defparam
the_altera_tse_gxb_gige_phyip_inst_20.ENABLE_ALT_RECONFIG = ENABLE_ALT_RECONFIG,
the_altera_tse_gxb_gige_phyip_inst_20.ENABLE_SGMII = ENABLE_SGMII,
the_altera_tse_gxb_gige_phyip_inst_20.DEVICE_FAMILY = DEVICE_FAMILY;
end
else
begin
assign reconfig_fromgxb_20 = {92{1'b0}};
assign led_char_err_gx[20] = 1'b0;
assign link_status[20] = 1'b0;
assign led_disp_err_20 = 1'b0;
assign txp_20 = 1'b0;
assign rx_recovclkout_20= 1'b0;
assign phy_mgmt_readdata_20 = 32'b0;
assign phy_mgmt_waitrequest_20 = 1'b0;
end
endgenerate
// #######################################################################
// ############### CHANNEL 21 LOGIC/COMPONENTS ###############
// #######################################################################
generate if (MAX_CHANNELS > 21)
begin
// Instantiation of the Alt2gxb and Alt4gxb block as the PMA for Stratix_II_GX ,ArriaGX and Stratix IV devices
// -----------------------------------------------------------------------------------
// Aligned Rx_sync from gxb
// -------------------------------
altera_tse_reset_synchronizer ch21_reset_sync_0(
.clk(ref_clk),
.reset_in(reset),
.reset_out(reset_rx_pcs_clk_c21_int)
);
altera_tse_gxb_aligned_rxsync the_altera_tse_gxb_aligned_rxsync_21
(
.clk(rx_pcs_clk_c21),
.reset(reset_rx_pcs_clk_c21_int),
//input (from alt2gxb)
.alt_dataout(rx_frame_21),
.alt_sync(rx_syncstatus[21]),
.alt_disperr(rx_disp_err[21]),
.alt_ctrldetect(rx_kchar_21),
.alt_errdetect(rx_char_err_gx[21]),
.alt_rmfifodatadeleted(rx_rmfifodatadeleted[21]),
.alt_rmfifodatainserted(rx_rmfifodatainserted[21]),
.alt_runlengthviolation(rx_runlengthviolation[21]),
.alt_patterndetect(rx_patterndetect[21]),
.alt_runningdisp(rx_runningdisp[21]),
//output (to PCS)
.altpcs_dataout(pcs_rx_frame_21),
.altpcs_sync(link_status[21]),
.altpcs_disperr(led_disp_err_21),
.altpcs_ctrldetect(pcs_rx_kchar_21),
.altpcs_errdetect(led_char_err_gx[21]),
.altpcs_rmfifodatadeleted(pcs_rx_rmfifodatadeleted[21]),
.altpcs_rmfifodatainserted(pcs_rx_rmfifodatainserted[21]),
.altpcs_carrierdetect(pcs_rx_carrierdetected[21])
) ;
defparam
the_altera_tse_gxb_aligned_rxsync_21.DEVICE_FAMILY = DEVICE_FAMILY;
// Altgxb in GIGE mode
// --------------------
altera_tse_gxb_gige_phyip_inst the_altera_tse_gxb_gige_phyip_inst_21
(
.phy_mgmt_clk(clk),
.phy_mgmt_clk_reset(reset),
.phy_mgmt_address(phy_mgmt_address_21),
.phy_mgmt_read(phy_mgmt_read_21),
.phy_mgmt_readdata(phy_mgmt_readdata_21),
.phy_mgmt_waitrequest(phy_mgmt_waitrequest_21),
.phy_mgmt_write(phy_mgmt_write_21),
.phy_mgmt_writedata(phy_mgmt_writedata_21),
.tx_ready(),
.rx_ready(),
.pll_ref_clk(ref_clk),
.pll_locked(),
.tx_serial_data(txp_21),
.rx_serial_data(rxp_21),
.rx_runningdisp(rx_runningdisp[21]),
.rx_disperr(rx_disp_err[21]),
.rx_errdetect(rx_char_err_gx[21]),
.rx_patterndetect(rx_patterndetect[21]),
.rx_syncstatus(rx_syncstatus[21]),
.tx_clkout(tx_pcs_clk_c21),
.rx_clkout(rx_pcs_clk_c21),
.tx_parallel_data(tx_frame_21),
.tx_datak(tx_kchar_21),
.rx_parallel_data(rx_frame_21),
.rx_datak(rx_kchar_21),
.rx_rlv(rx_runlengthviolation[21]),
.rx_recovclkout(rx_recovclkout_21),
.rx_rmfifodatadeleted(rx_rmfifodatadeleted[21]),
.rx_rmfifodatainserted(rx_rmfifodatainserted[21]),
.reconfig_togxb(reconfig_togxb_21),
.reconfig_fromgxb(reconfig_fromgxb_21)
);
defparam
the_altera_tse_gxb_gige_phyip_inst_21.ENABLE_ALT_RECONFIG = ENABLE_ALT_RECONFIG,
the_altera_tse_gxb_gige_phyip_inst_21.ENABLE_SGMII = ENABLE_SGMII,
the_altera_tse_gxb_gige_phyip_inst_21.DEVICE_FAMILY = DEVICE_FAMILY;
end
else
begin
assign reconfig_fromgxb_21 = {92{1'b0}};
assign led_char_err_gx[21] = 1'b0;
assign link_status[21] = 1'b0;
assign led_disp_err_21 = 1'b0;
assign txp_21 = 1'b0;
assign rx_recovclkout_21= 1'b0;
assign phy_mgmt_readdata_21 = 32'b0;
assign phy_mgmt_waitrequest_21 = 1'b0;
end
endgenerate
// #######################################################################
// ############### CHANNEL 22 LOGIC/COMPONENTS ###############
// #######################################################################
generate if (MAX_CHANNELS > 22)
begin
// Instantiation of the Alt2gxb and Alt4gxb block as the PMA for Stratix_II_GX ,ArriaGX and Stratix IV devices
// -----------------------------------------------------------------------------------
// Aligned Rx_sync from gxb
// -------------------------------
altera_tse_reset_synchronizer ch22_reset_sync_0(
.clk(ref_clk),
.reset_in(reset),
.reset_out(reset_rx_pcs_clk_c22_int)
);
altera_tse_gxb_aligned_rxsync the_altera_tse_gxb_aligned_rxsync_22
(
.clk(rx_pcs_clk_c22),
.reset(reset_rx_pcs_clk_c22_int),
//input (from alt2gxb)
.alt_dataout(rx_frame_22),
.alt_sync(rx_syncstatus[22]),
.alt_disperr(rx_disp_err[22]),
.alt_ctrldetect(rx_kchar_22),
.alt_errdetect(rx_char_err_gx[22]),
.alt_rmfifodatadeleted(rx_rmfifodatadeleted[22]),
.alt_rmfifodatainserted(rx_rmfifodatainserted[22]),
.alt_runlengthviolation(rx_runlengthviolation[22]),
.alt_patterndetect(rx_patterndetect[22]),
.alt_runningdisp(rx_runningdisp[22]),
//output (to PCS)
.altpcs_dataout(pcs_rx_frame_22),
.altpcs_sync(link_status[22]),
.altpcs_disperr(led_disp_err_22),
.altpcs_ctrldetect(pcs_rx_kchar_22),
.altpcs_errdetect(led_char_err_gx[22]),
.altpcs_rmfifodatadeleted(pcs_rx_rmfifodatadeleted[22]),
.altpcs_rmfifodatainserted(pcs_rx_rmfifodatainserted[22]),
.altpcs_carrierdetect(pcs_rx_carrierdetected[22])
) ;
defparam
the_altera_tse_gxb_aligned_rxsync_22.DEVICE_FAMILY = DEVICE_FAMILY;
// Altgxb in GIGE mode
// --------------------
altera_tse_gxb_gige_phyip_inst the_altera_tse_gxb_gige_phyip_inst_22
(
.phy_mgmt_clk(clk),
.phy_mgmt_clk_reset(reset),
.phy_mgmt_address(phy_mgmt_address_22),
.phy_mgmt_read(phy_mgmt_read_22),
.phy_mgmt_readdata(phy_mgmt_readdata_22),
.phy_mgmt_waitrequest(phy_mgmt_waitrequest_22),
.phy_mgmt_write(phy_mgmt_write_22),
.phy_mgmt_writedata(phy_mgmt_writedata_22),
.tx_ready(),
.rx_ready(),
.pll_ref_clk(ref_clk),
.pll_locked(),
.tx_serial_data(txp_22),
.rx_serial_data(rxp_22),
.rx_runningdisp(rx_runningdisp[22]),
.rx_disperr(rx_disp_err[22]),
.rx_errdetect(rx_char_err_gx[22]),
.rx_patterndetect(rx_patterndetect[22]),
.rx_syncstatus(rx_syncstatus[22]),
.tx_clkout(tx_pcs_clk_c22),
.rx_clkout(rx_pcs_clk_c22),
.tx_parallel_data(tx_frame_22),
.tx_datak(tx_kchar_22),
.rx_parallel_data(rx_frame_22),
.rx_datak(rx_kchar_22),
.rx_rlv(rx_runlengthviolation[22]),
.rx_recovclkout(rx_recovclkout_22),
.rx_rmfifodatadeleted(rx_rmfifodatadeleted[22]),
.rx_rmfifodatainserted(rx_rmfifodatainserted[22]),
.reconfig_togxb(reconfig_togxb_22),
.reconfig_fromgxb(reconfig_fromgxb_22)
);
defparam
the_altera_tse_gxb_gige_phyip_inst_22.ENABLE_ALT_RECONFIG = ENABLE_ALT_RECONFIG,
the_altera_tse_gxb_gige_phyip_inst_22.ENABLE_SGMII = ENABLE_SGMII,
the_altera_tse_gxb_gige_phyip_inst_22.DEVICE_FAMILY = DEVICE_FAMILY;
end
else
begin
assign reconfig_fromgxb_22 = {92{1'b0}};
assign led_char_err_gx[22] = 1'b0;
assign link_status[22] = 1'b0;
assign led_disp_err_22 = 1'b0;
assign txp_22 = 1'b0;
assign rx_recovclkout_22= 1'b0;
assign phy_mgmt_readdata_22 = 32'b0;
assign phy_mgmt_waitrequest_22 = 1'b0;
end
endgenerate
// #######################################################################
// ############### CHANNEL 23 LOGIC/COMPONENTS ###############
// #######################################################################
generate if (MAX_CHANNELS > 23)
begin
// Instantiation of the Alt2gxb and Alt4gxb block as the PMA for Stratix_II_GX ,ArriaGX and Stratix IV devices
// -----------------------------------------------------------------------------------
// Aligned Rx_sync from gxb
// -------------------------------
altera_tse_reset_synchronizer ch23_reset_sync_0(
.clk(ref_clk),
.reset_in(reset),
.reset_out(reset_rx_pcs_clk_c23_int)
);
altera_tse_gxb_aligned_rxsync the_altera_tse_gxb_aligned_rxsync_23
(
.clk(rx_pcs_clk_c23),
.reset(reset_rx_pcs_clk_c23_int),
//input (from alt2gxb)
.alt_dataout(rx_frame_23),
.alt_sync(rx_syncstatus[23]),
.alt_disperr(rx_disp_err[23]),
.alt_ctrldetect(rx_kchar_23),
.alt_errdetect(rx_char_err_gx[23]),
.alt_rmfifodatadeleted(rx_rmfifodatadeleted[23]),
.alt_rmfifodatainserted(rx_rmfifodatainserted[23]),
.alt_runlengthviolation(rx_runlengthviolation[23]),
.alt_patterndetect(rx_patterndetect[23]),
.alt_runningdisp(rx_runningdisp[23]),
//output (to PCS)
.altpcs_dataout(pcs_rx_frame_23),
.altpcs_sync(link_status[23]),
.altpcs_disperr(led_disp_err_23),
.altpcs_ctrldetect(pcs_rx_kchar_23),
.altpcs_errdetect(led_char_err_gx[23]),
.altpcs_rmfifodatadeleted(pcs_rx_rmfifodatadeleted[23]),
.altpcs_rmfifodatainserted(pcs_rx_rmfifodatainserted[23]),
.altpcs_carrierdetect(pcs_rx_carrierdetected[23])
) ;
defparam
the_altera_tse_gxb_aligned_rxsync_23.DEVICE_FAMILY = DEVICE_FAMILY;
// Altgxb in GIGE mode
// --------------------
altera_tse_gxb_gige_phyip_inst the_altera_tse_gxb_gige_phyip_inst_23
(
.phy_mgmt_clk(clk),
.phy_mgmt_clk_reset(reset),
.phy_mgmt_address(phy_mgmt_address_23),
.phy_mgmt_read(phy_mgmt_read_23),
.phy_mgmt_readdata(phy_mgmt_readdata_23),
.phy_mgmt_waitrequest(phy_mgmt_waitrequest_23),
.phy_mgmt_write(phy_mgmt_write_23),
.phy_mgmt_writedata(phy_mgmt_writedata_23),
.tx_ready(),
.rx_ready(),
.pll_ref_clk(ref_clk),
.pll_locked(),
.tx_serial_data(txp_23),
.rx_serial_data(rxp_23),
.rx_runningdisp(rx_runningdisp[23]),
.rx_disperr(rx_disp_err[23]),
.rx_errdetect(rx_char_err_gx[23]),
.rx_patterndetect(rx_patterndetect[23]),
.rx_syncstatus(rx_syncstatus[23]),
.tx_clkout(tx_pcs_clk_c23),
.rx_clkout(rx_pcs_clk_c23),
.tx_parallel_data(tx_frame_23),
.tx_datak(tx_kchar_23),
.rx_parallel_data(rx_frame_23),
.rx_datak(rx_kchar_23),
.rx_rlv(rx_runlengthviolation[23]),
.rx_recovclkout(rx_recovclkout_23),
.rx_rmfifodatadeleted(rx_rmfifodatadeleted[23]),
.rx_rmfifodatainserted(rx_rmfifodatainserted[23]),
.reconfig_togxb(reconfig_togxb_23),
.reconfig_fromgxb(reconfig_fromgxb_23)
);
defparam
the_altera_tse_gxb_gige_phyip_inst_23.ENABLE_ALT_RECONFIG = ENABLE_ALT_RECONFIG,
the_altera_tse_gxb_gige_phyip_inst_23.ENABLE_SGMII = ENABLE_SGMII,
the_altera_tse_gxb_gige_phyip_inst_23.DEVICE_FAMILY = DEVICE_FAMILY;
end
else
begin
assign reconfig_fromgxb_23 = {92{1'b0}};
assign led_char_err_gx[23] = 1'b0;
assign link_status[23] = 1'b0;
assign led_disp_err_23 = 1'b0;
assign txp_23 = 1'b0;
assign rx_recovclkout_23= 1'b0;
assign phy_mgmt_readdata_23 = 32'b0;
assign phy_mgmt_waitrequest_23 = 1'b0;
end
endgenerate
endmodule
|
module sky130_fd_sc_lp__udp_dff$PS_pp$PKG$sN (
Q ,
D ,
CLK ,
SET ,
SLEEP_B ,
NOTIFIER,
KAPWR ,
VGND ,
VPWR
);
output Q ;
input D ;
input CLK ;
input SET ;
input SLEEP_B ;
input NOTIFIER;
input KAPWR ;
input VGND ;
input VPWR ;
endmodule
|
module vga_demo
(
CLOCK_PIXEL,
RESET,
VGA_RED,
VGA_GREEN,
VGA_BLUE,
VGA_HS,
VGA_VS
);
input CLOCK_PIXEL;
input RESET;
output VGA_RED;
output VGA_GREEN;
output VGA_BLUE;
output VGA_HS;
output VGA_VS;
/* Internal registers for horizontal signal timing */
reg [10:0] hor_reg; // to count up to 975
reg hor_sync;
wire hor_max = (hor_reg == 975); // to tell when a line is full
/* Internal registers for vertical signal timing */
reg [9:0] ver_reg; // to count up to 527
reg ver_sync;
reg red, green, blue;
wire ver_max = (ver_reg == 527); // to tell when a line is full
// Code
/* Running through line */
always @ (posedge CLOCK_PIXEL or posedge RESET) begin
if (RESET) begin
hor_reg <= 0;
ver_reg <= 0;
end
else if (hor_max) begin
hor_reg <= 0;
/* Running through frame */
if (ver_max)
ver_reg <= 0;
else
ver_reg <= ver_reg + 1;
end else
hor_reg <= hor_reg + 1;
end
always @ (posedge CLOCK_PIXEL or posedge RESET) begin
if (RESET) begin
hor_sync <= 0;
ver_sync <= 0;
red <= 0;
green <= 0;
blue <= 0;
end
else begin
/* Generating the horizontal sync signal */
if (hor_reg == 840) // video (800) + front porch (40)
hor_sync <= 1; // turn on horizontal sync pulse
else if (hor_reg == 928) // video (800) + front porch (40) + Sync Pulse (88)
hor_sync <= 0; // turn off horizontal sync pulse
/* Generating the vertical sync signal */
if (ver_reg == 493) // LINES: video (480) + front porch (13)
ver_sync <= 1; // turn on vertical sync pulse
else if (ver_reg == 496) // LINES: video (480) + front porch (13) + Sync Pulse (3)
ver_sync <= 0; // turn off vertical sync pulse
// black during the porches
if (ver_reg > 480 || hor_reg > 800) begin
red <= 0;
green <= 0;
blue <= 0;
end
else begin
// Draw a single square.
if (hor_reg >= 100 && hor_reg <= 200 && ver_reg >= 100 && ver_reg <= 200) begin
red <= 1;
green <= 1;
blue <= 1;
end
// top border
else if (ver_reg == 0 ) begin
red <= 0;
green <= 1;
blue <= 0;
end
// bottom border
else if (ver_reg == 478 ) begin // Not quite 480 visable
red <= 0;
green <= 1;
blue <= 0;
end
// left border
else if (hor_reg == 0 ) begin
red <= 1;
green <= 0;
blue <= 0;
end
// right border
else if (hor_reg == 780 ) begin // Not quite 800 visable
red <= 1;
green <= 0;
blue <= 0;
end
else begin
red <= 0;
green <= 0;
blue <= 1;
end
end
end
end
// Send the sync signals to the outputh.
// this doc says pulse is positive http://tinyvga.com/vga-timing/800x600@72Hz
assign VGA_HS = hor_sync;
assign VGA_VS = ver_sync;
assign VGA_RED = red;
assign VGA_GREEN = green;
assign VGA_BLUE = blue;
endmodule
|
module DataPath(input clk, reset, ir_write, B_write, pc_src, pc_write, mem_src, mem_write, stack_src, tos, push, pop, output reg z, output [2:0] inst_op);
//pc & inst Memory
reg [4:0] pc, next_pc;
reg [7:0] IR, B_reg;
assign inst_op = IR[7:5];
//data memory
reg [4:0] mem_addr;
reg [7:0] mem_write_data;
wire [7:0] mem_out_data;
//stack
reg [7:0] stack_in;
wire [7:0] stack_out;
//ALU
reg [7:0] alu_A, alu_B;
wire [7:0] alu_out;
reg [7:0] alu_reg;
//Modules
DataMem data_mem (clk, mem_write, mem_addr , mem_write_data, mem_out_data);
Stack stack(clk, tos, push,pop, stack_in, stack_out);
ALU alu(inst_op , alu_A, alu_B, alu_out);
always @(*) begin //calculate the new pc
//PC
case(pc_src)
1'b0: next_pc <= IR[4:0];
1'b1: next_pc <= pc + 1;
endcase
//Stack
case(stack_src)
1'b0: stack_in <= mem_out_data;
1'b1: stack_in <= alu_reg;
endcase
//z
if(stack_out == 8'b0)
z = 1'b1;
else z = 1'b0;
//ALU
alu_A <= stack_out;
alu_B <= B_reg;
//Data Memory
case(mem_src)
1'b0: mem_addr <= IR[4:0];
1'b1: mem_addr <= pc;
endcase
mem_write_data <= stack_out;
end
always @(posedge clk)begin //set new values to registers
if(reset == 1'b0)
begin
if(pc_write)
pc = next_pc;
if(ir_write)
IR <= mem_out_data;
B_reg <= stack_out;
alu_reg <= alu_out;
end
else begin
{pc,IR, B_reg} = 0;
alu_reg = 8'b0;
end
end
endmodule
|
module sky130_fd_sc_hd__or3b (
X ,
A ,
B ,
C_N ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B ;
input C_N ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
|
module
// Credit: http://www.johnloomis.org/digitallab/ps2lab1/ps2lab1.html
keyboard keybd(
.keyboard_clk(PS2_CLK),
.keyboard_data(PS2_DAT),
.clock50(CLOCK_50),
.reset(0),
.read(read),
.scan_ready(scan_ready),
.scan_code(scan_code)
);
// Module to regulate keyboard input
// Credit: http://www.johnloomis.org/digitallab/ps2lab1/ps2lab1.html
oneshot pulser(
.pulse_out(read),
.trigger_in(scan_ready),
.clk(CLOCK_50)
);
// Module to output info to the seven-segment displays
sevenseg ss(
.seg0(HEX0),
.seg1(HEX1),
.seg2(HEX2),
.seg3(HEX3),
.seg4(HEX4),
.seg5(HEX5),
.seg6(HEX6),
.seg7(HEX7),
.score_p1(p1_score),
.score_p2(p2_score),
.winner(winner)
);
endmodule
|
module graphics(
clk,
candraw,
x,
y,
p1_y,
p2_y,
ball_on,
ball_x,
ball_y,
red,
green,
blue,
vga_blank
);
input clk;
input candraw;
input ball_on;
input [10:0] x, y, p1_y, p2_y, ball_x, ball_y;
output reg [9:0] red, green, blue;
output vga_blank;
reg n_vga_blank;
assign vga_blank = !n_vga_blank;
always @(posedge clk) begin
if (candraw) begin
n_vga_blank <= 1'b0;
// draw P1 (left) bat
if (x < `batwidth && y > p1_y && y < p1_y + `batheight) begin
// white bat
red <= 10'b1111111111;
green <= 10'b1111111111;
blue <= 10'b1111111111;
end
// draw P2 (right) bat
else if (x > `hc - `batwidth && y > p2_y && y < p2_y + `batheight) begin
// white bat
red <= 10'b1111111111;
green <= 10'b1111111111;
blue <= 10'b1111111111;
end
// draw ball
else if (ball_on && x > ball_x && x < ball_x + `ballsize && y > ball_y && y < ball_y + `ballsize) begin
// white ball
red <= 10'b1111111111;
green <= 10'b1111111111;
blue <= 10'b1111111111;
end
// black background
else begin
red <= 10'b0000000000;
green <= 10'b0000000000;
blue <= 10'b0000000000;
end
end else begin
// if we are not in the visible area, we must set the screen blank
n_vga_blank <= 1'b1;
end
end
endmodule
|
module vga(
clk,
vsync,
hsync,
x,
y,
can_draw,
start_of_frame
);
input clk;
output vsync, hsync;
output [10:0] x, y;
output can_draw;
output start_of_frame;
assign x = h - `ha - `hb;
assign y = v - `va - `vb;
assign can_draw = (h >= (`ha + `hb)) && (h < (`ha + `hb + `hc))
&& (v >= (`va + `vb)) && (v < (`va + `vb + `vc));
assign vsync = vga_vsync;
assign hsync = vga_hsync;
assign start_of_frame = startframe;
// horizontal and vertical counts
reg [10:0] h;
reg [10:0] v;
reg vga_vsync;
reg vga_hsync;
reg startframe;
always @(posedge clk) begin
// if we are not at the end of a row, increment h
if (h < (`ha + `hb + `hc + `hd)) begin
h <= h + 11'd1;
// otherwise set h = 0 and increment v (unless we are at the bottom of the screen)
end else begin
h <= 11'd0;
v <= (v < (`va + `vb + `vc + `vd)) ? v + 11'd1 : 11'd0;
end
vga_hsync <= h > `ha;
vga_vsync <= v > `va;
startframe <= (h == 11'd0) && (v == 11'd0);
end
endmodule
|
module batpos(
clk,
up,
down,
reset,
speed,
value
);
input clk;
input up, down; // signal for counting up/down
input [4:0] speed; // # of px to increment bats by
input reset;
output [10:0] value; // max value is 1024 (px), 11 bits wide
reg [10:0] value;
initial begin
value <= `vc / 2;
end
always @ (posedge clk or posedge reset) begin
if (reset) begin
// go back to the middle
value <= `vc / 2;
end
else begin
if (up) begin
// prevent bat from going beyond upper bound of the screen
if ((value - speed) > `va) begin
// move bat up the screen
value <= value - speed;
end
end
else if (down) begin
// prevent bat from going beyond lower bound of the screen
if ((value + speed) < (`vc - `batheight)) begin
// move bat down the screen
value <= value + speed;
end
end
end
end
endmodule
|
module ballpos(
clk,
reset,
speed,
dir_x, // 0 = LEFT, 1 = RIGHT
dir_y, // 0 = UP, 1 = DOWN
value_x,
value_y
);
input clk;
input [4:0] speed; // # of px to increment bat by
input reset;
input dir_x, dir_y;
output [10:0] value_x, value_y; // max value is 1024 (px), 11 bits wide
reg [10:0] value_x, value_y;
// the initial position of the ball is at the top of the screen, in the middle,
initial begin
value_x <= `hc / 2 - (`ballsize / 2);
value_y <= `va + 7;
end
always @ (posedge clk or posedge reset) begin
if (reset) begin
value_x <= `hc / 2 - (`ballsize / 2);
value_y <= `va + 7;
end
else begin
// increment x
if (dir_x) begin
// right
value_x <= value_x + speed;
end
else begin
// left
value_x <= value_x - speed;
end
// increment y
if (dir_y) begin
// down
value_y <= value_y + speed;
end
else begin
// up
value_y <= value_y - speed;
end
end
end
endmodule
|
module ballcollisions(
clk,
reset,
p1_y,
p2_y,
ball_x,
ball_y,
dir_x,
dir_y,
oob // whether ball is out of bounds
);
input clk, reset;
input [10:0] p1_y, p2_y, ball_x, ball_y;
output dir_x, dir_y, oob;
reg dir_x, dir_y, oob;
initial begin
dir_x <= 0;
dir_y <= 1;
oob <= 0;
end
always @ (posedge clk) begin
if (reset) begin
dir_x <= ~dir_x; // alternate starting direction every round
dir_y <= 1;
oob <= 0;
end
else begin
// out of bounds (i.e. one of the players missed the ball)
if (ball_x <= 0 || ball_x >= `hc) begin
oob = 1;
end
else begin
oob = 0;
end
// collision with top & bottom walls
if (ball_y <= `va + 5) begin
dir_y = 1;
end
if (ball_y >= `vc - `ballsize) begin
dir_y = 0;
end
// collision with P1 bat
if (ball_x <= `batwidth && ball_y + `ballsize >= p1_y && ball_y <= p1_y + `batheight) begin
dir_x = 1; // reverse direction
if (ball_y + `ballsize <= p1_y + (`batheight / 2)) begin
// collision with top half of p1 bat, go up
dir_y = 0;
end
else begin
// collision with bottom half of p1 bat, go down
dir_y = 1;
end
end
// collision with P2 bat
else if (ball_x >= `hc - `batwidth -`ballsize && ball_y + `ballsize <= p2_y + `batheight && ball_y >= p2_y) begin
dir_x = 0; // reverse direction
if (ball_y + `ballsize <= p2_y + (`batheight / 2)) begin
// collision with top half of p1 bat, go up
dir_y = 0;
end
else begin
// collision with bottom half of p1 bat, go down
dir_y = 1;
end
end
end
end
endmodule
|
module
ballcollisions bcs (
.clk(video_clock && start && ball_on),
.reset(reset || newround),
.p1_y(p1_y),
.p2_y(p2_y),
.ball_x(ball_x),
.ball_y(ball_y),
.dir_x(dir_x),
.dir_y(dir_y),
.oob(outofbounds)
);
// Module with counters that determining the ball position
ballpos bp (
.clk(video_clock && start && ball_on),
.reset(reset || newround || (winner > 0)),
.speed(`ballspeed),
.dir_x(dir_x),
.dir_y(dir_y),
.value_x(ball_x),
.value_y(ball_y)
);
endmodule
|
module sevenseg(seg0, seg1, seg2, seg3, seg4, seg5, seg6, seg7, score_p1, score_p2, winner);
input [3:0] score_p1, score_p2;
input [1:0] winner; // 0 = none, 1 = P1, 2 = P2
output [6:0] seg0, seg1, seg2, seg3, seg4, seg5, seg6, seg7;
reg [6:0] seg0, seg1, seg2, seg3, seg4, seg5, seg6, seg7;
always @ (score_p1 or winner) begin
if (winner > 0) begin
// Show the winner on HEX7 and HEX6 (i.e. P1 or P2)
seg7 = 7'b0001100; // P
case (winner)
2'h1: seg6 = 7'b1111001; // 1
2'h2: seg6 = 7'b0100100; // 2
default: seg6 = 7'b1111111;
endcase
end
else begin
seg7 = 7'b1111111;
case (score_p1)
4'h0: seg6 = 7'b1000000;
4'h1: seg6 = 7'b1111001;
4'h2: seg6 = 7'b0100100;
4'h3: seg6 = 7'b0110000;
4'h4: seg6 = 7'b0011001;
4'h5: seg6 = 7'b0010010;
4'h6: seg6 = 7'b0000010;
4'h7: seg6 = 7'b1111000;
4'h8: seg6 = 7'b0000000;
4'h9: seg6 = 7'b0011000;
default: seg6 = 7'b1111111;
endcase
end
end
always @ (score_p2 or winner) begin
if (winner > 0) begin
// Unused; blank out
seg5 = 7'b1111111;
seg4 = 7'b1111111;
end
else begin
seg5 = 7'b1111111;
case (score_p2)
4'h0: seg4 = 7'b1000000;
4'h1: seg4 = 7'b1111001;
4'h2: seg4 = 7'b0100100;
4'h3: seg4 = 7'b0110000;
4'h4: seg4 = 7'b0011001;
4'h5: seg4 = 7'b0010010;
4'h6: seg4 = 7'b0000010;
4'h7: seg4 = 7'b1111000;
4'h8: seg4 = 7'b0000000;
4'h9: seg4 = 7'b0011000;
default: seg4 = 7'b1111111;
endcase
end
end
// Blank out unused displays
always begin
seg3 = 7'b1111111;
seg2 = 7'b1111111;
seg1 = 7'b1111111;
seg0 = 7'b1111111;
end
endmodule
|
module altera_mem_if_ddr3_phy_0001_qsys_sequencer_cpu_inst_jtag_debug_module_sysclk (
// inputs:
clk,
ir_in,
sr,
vs_udr,
vs_uir,
// outputs:
jdo,
take_action_break_a,
take_action_break_b,
take_action_break_c,
take_action_ocimem_a,
take_action_ocimem_b,
take_action_tracectrl,
take_action_tracemem_a,
take_action_tracemem_b,
take_no_action_break_a,
take_no_action_break_b,
take_no_action_break_c,
take_no_action_ocimem_a,
take_no_action_tracemem_a
)
;
output [ 37: 0] jdo;
output take_action_break_a;
output take_action_break_b;
output take_action_break_c;
output take_action_ocimem_a;
output take_action_ocimem_b;
output take_action_tracectrl;
output take_action_tracemem_a;
output take_action_tracemem_b;
output take_no_action_break_a;
output take_no_action_break_b;
output take_no_action_break_c;
output take_no_action_ocimem_a;
output take_no_action_tracemem_a;
input clk;
input [ 1: 0] ir_in;
input [ 37: 0] sr;
input vs_udr;
input vs_uir;
reg enable_action_strobe /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */;
reg [ 1: 0] ir /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */;
reg [ 37: 0] jdo /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */;
reg jxuir /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */;
reg sync2_udr /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */;
reg sync2_uir /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */;
wire sync_udr;
wire sync_uir;
wire take_action_break_a;
wire take_action_break_b;
wire take_action_break_c;
wire take_action_ocimem_a;
wire take_action_ocimem_b;
wire take_action_tracectrl;
wire take_action_tracemem_a;
wire take_action_tracemem_b;
wire take_no_action_break_a;
wire take_no_action_break_b;
wire take_no_action_break_c;
wire take_no_action_ocimem_a;
wire take_no_action_tracemem_a;
wire unxunused_resetxx2;
wire unxunused_resetxx3;
reg update_jdo_strobe /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */;
assign unxunused_resetxx2 = 1'b1;
altera_std_synchronizer the_altera_std_synchronizer2
(
.clk (clk),
.din (vs_udr),
.dout (sync_udr),
.reset_n (unxunused_resetxx2)
);
defparam the_altera_std_synchronizer2.depth = 2;
assign unxunused_resetxx3 = 1'b1;
altera_std_synchronizer the_altera_std_synchronizer3
(
.clk (clk),
.din (vs_uir),
.dout (sync_uir),
.reset_n (unxunused_resetxx3)
);
defparam the_altera_std_synchronizer3.depth = 2;
always @(posedge clk)
begin
sync2_udr <= sync_udr;
update_jdo_strobe <= sync_udr & ~sync2_udr;
enable_action_strobe <= update_jdo_strobe;
sync2_uir <= sync_uir;
jxuir <= sync_uir & ~sync2_uir;
end
assign take_action_ocimem_a = enable_action_strobe && (ir == 2'b00) &&
~jdo[35] && jdo[34];
assign take_no_action_ocimem_a = enable_action_strobe && (ir == 2'b00) &&
~jdo[35] && ~jdo[34];
assign take_action_ocimem_b = enable_action_strobe && (ir == 2'b00) &&
jdo[35];
assign take_action_tracemem_a = enable_action_strobe && (ir == 2'b01) &&
~jdo[37] &&
jdo[36];
assign take_no_action_tracemem_a = enable_action_strobe && (ir == 2'b01) &&
~jdo[37] &&
~jdo[36];
assign take_action_tracemem_b = enable_action_strobe && (ir == 2'b01) &&
jdo[37];
assign take_action_break_a = enable_action_strobe && (ir == 2'b10) &&
~jdo[36] &&
jdo[37];
assign take_no_action_break_a = enable_action_strobe && (ir == 2'b10) &&
~jdo[36] &&
~jdo[37];
assign take_action_break_b = enable_action_strobe && (ir == 2'b10) &&
jdo[36] && ~jdo[35] &&
jdo[37];
assign take_no_action_break_b = enable_action_strobe && (ir == 2'b10) &&
jdo[36] && ~jdo[35] &&
~jdo[37];
assign take_action_break_c = enable_action_strobe && (ir == 2'b10) &&
jdo[36] && jdo[35] &&
jdo[37];
assign take_no_action_break_c = enable_action_strobe && (ir == 2'b10) &&
jdo[36] && jdo[35] &&
~jdo[37];
assign take_action_tracectrl = enable_action_strobe && (ir == 2'b11) &&
jdo[15];
always @(posedge clk)
begin
if (jxuir)
ir <= ir_in;
if (update_jdo_strobe)
jdo <= sr;
end
endmodule
|
module gpac_adc_rx_core #(
parameter ABUSWIDTH = 16,
parameter [1:0] ADC_ID = 0,
parameter [0:0] HEADER_ID = 0
) (
input wire ADC_ENC,
input wire [13:0] ADC_IN,
input wire ADC_SYNC,
input wire ADC_TRIGGER,
input wire FIFO_READ,
output wire FIFO_EMPTY,
output wire [31:0] FIFO_DATA,
input wire BUS_CLK,
input wire [ABUSWIDTH-1:0] BUS_ADD,
input wire [7:0] BUS_DATA_IN,
output reg [7:0] BUS_DATA_OUT,
input wire BUS_RST,
input wire BUS_WR,
input wire BUS_RD,
output wire LOST_ERROR
);
localparam VERSION = 1;
// 0 - soft reset
// 1 - start/status
//TODO:
// - external trigger /rising falling
wire SOFT_RST;
assign SOFT_RST = (BUS_ADD==0 && BUS_WR);
wire RST;
assign RST = BUS_RST | SOFT_RST;
reg [7:0] status_regs [15:0];
always @(posedge BUS_CLK) begin
if(RST) begin
status_regs[0] <= 0;
status_regs[1] <= 0;
status_regs[2] <= 8'b0000_0000; // CONF_START_WITH_SYNC = TRUE
status_regs[3] <= 0;
status_regs[4] <= 0;
status_regs[5] <= 0;
status_regs[6] <= 1;
status_regs[7] <= 0;
status_regs[8] <= 0;
end
else if(BUS_WR && BUS_ADD < 16)
status_regs[BUS_ADD[3:0]] <= BUS_DATA_IN;
end
wire START;
assign START = (BUS_ADD==1 && BUS_WR);
wire CONF_START_WITH_SYNC;
assign CONF_START_WITH_SYNC = status_regs[2][0];
wire CONF_EN_EX_TRIGGER;
assign CONF_EN_EX_TRIGGER = status_regs[2][1];
wire CONF_SINGLE_DATA;
assign CONF_SINGLE_DATA = status_regs[2][2];
wire [23:0] CONF_DATA_CNT;
assign CONF_DATA_CNT = {status_regs[5], status_regs[4], status_regs[3]};
wire [7:0] CONF_SAMPLE_SKIP = status_regs[6];
wire [7:0] CONF_SAMPEL_DLY = status_regs[7];
reg [7:0] CONF_ERROR_LOST;
assign LOST_ERROR = CONF_ERROR_LOST != 0;
reg CONF_DONE;
wire [7:0] BUS_STATUS_OUT;
assign BUS_STATUS_OUT = status_regs[BUS_ADD[3:0]];
always @(posedge BUS_CLK) begin
if(BUS_RD) begin
if(BUS_ADD == 0)
BUS_DATA_OUT <= VERSION;
else if(BUS_ADD == 1)
BUS_DATA_OUT <= {7'b0, CONF_DONE};
else if(BUS_ADD == 8)
BUS_DATA_OUT <= CONF_ERROR_LOST;
else if(BUS_ADD < 16)
BUS_DATA_OUT <= BUS_STATUS_OUT;
end
end
wire rst_adc_sync;
cdc_reset_sync isync_rst (.clk_in(BUS_CLK), .pulse_in(RST), .clk_out(ADC_ENC), .pulse_out(rst_adc_sync));
wire start_adc_sync;
cdc_pulse_sync istart_rst (.clk_in(BUS_CLK), .pulse_in(START), .clk_out(ADC_ENC), .pulse_out(start_adc_sync));
wire adc_sync_pulse;
pulse_gen_rising pulse_adc_sync (.clk_in(ADC_ENC), .in(ADC_SYNC), .out(adc_sync_pulse));
//long reset is needed
reg [7:0] sync_cnt;
always @(posedge BUS_CLK) begin
if(RST)
sync_cnt <= 120;
else if(sync_cnt != 100)
sync_cnt <= sync_cnt +1;
end
wire RST_LONG;
assign RST_LONG = sync_cnt[7];
/*
reg [7:0] align_cnt;
always @(posedge ADC_ENC) begin
if(adc_sync_pulse)
align_cnt <= 0;
else if(align_cnt == (CONF_SAMPLE_SKIP - 1))
align_cnt <= 0;
else
align_cnt <= align_cnt + 1;
end
*/
reg adc_sync_wait;
always @(posedge ADC_ENC) begin
if(rst_adc_sync)
adc_sync_wait <= 0;
else if(start_adc_sync)
adc_sync_wait <= 1;
else if (adc_sync_pulse)
adc_sync_wait <= 0;
end
wire start_data_count;
assign start_data_count = (CONF_START_WITH_SYNC ? (adc_sync_wait && adc_sync_pulse) : start_adc_sync) || ( CONF_EN_EX_TRIGGER && ADC_TRIGGER);
reg [23:0] rec_cnt;
always @(posedge ADC_ENC) begin
if(rst_adc_sync)
rec_cnt <= 0;
else if(start_data_count && (rec_cnt > CONF_DATA_CNT || rec_cnt == 0))
rec_cnt <= 1;
else if(rec_cnt != 24'hff_ffff && rec_cnt > 0 && CONF_DATA_CNT != 0)
rec_cnt <= rec_cnt + 1;
end
wire DONE;
assign DONE = rec_cnt > CONF_DATA_CNT;
reg cdc_fifo_write_single;
always @(*) begin
if(CONF_DATA_CNT==0 && rec_cnt>=1) //forever
cdc_fifo_write_single = 1;
else if(rec_cnt>=1 && rec_cnt <= CONF_DATA_CNT) //to CONF_DATA_CNT
cdc_fifo_write_single = 1;
else
cdc_fifo_write_single = 0;
end
reg [13:0] prev_data;
reg prev_sync;
reg prev_ready;
always @(posedge ADC_ENC) begin
if(rst_adc_sync || start_adc_sync)
prev_ready <= 0;
else
prev_ready <= !prev_ready;
end
//
reg [13:0] ADC_IN_DLY, adc_dly_mem;
reg [13:0] dly_mem [255:0];
reg [7:0] dly_addr_read, dly_addr_write;
always @(posedge ADC_ENC)
if(rst_adc_sync)
dly_addr_write <= 0;
else
dly_addr_write <= dly_addr_write + 1;
always @(posedge ADC_ENC)
dly_mem[dly_addr_write] <= ADC_IN;
always @(posedge ADC_ENC)
adc_dly_mem <= dly_mem[dly_addr_read];
always @(*) begin
dly_addr_read = dly_addr_write - CONF_SAMPEL_DLY;
ADC_IN_DLY = CONF_SAMPEL_DLY == 0 ? ADC_IN : adc_dly_mem;
end
//
always @(posedge ADC_ENC) begin
prev_data <= ADC_IN_DLY;
prev_sync <= ADC_SYNC;
end
wire fifo_full, cdc_fifo_empty, cdc_fifo_write_double;
assign cdc_fifo_write_double = cdc_fifo_write_single && prev_ready; //write every second
wire wfull;
reg cdc_fifo_write;
always @(posedge ADC_ENC) begin
if(rst_adc_sync)
CONF_ERROR_LOST <= 0;
else if (CONF_ERROR_LOST!=8'hff && wfull && cdc_fifo_write)
CONF_ERROR_LOST <= CONF_ERROR_LOST +1;
end
reg [31:0] data_to_fifo;
always @(*) begin
if(CONF_SINGLE_DATA)
data_to_fifo = {HEADER_ID, ADC_ID, CONF_EN_EX_TRIGGER ? rec_cnt == 1 : ADC_SYNC, 14'b0, ADC_IN_DLY};
else
data_to_fifo = {HEADER_ID, ADC_ID, prev_sync, prev_data, ADC_IN_DLY};
if(CONF_SINGLE_DATA)
cdc_fifo_write = cdc_fifo_write_single;
else
cdc_fifo_write = cdc_fifo_write_double;
end
wire [31:0] cdc_data_out;
cdc_syncfifo #(
.DSIZE(32),
.ASIZE(3)
) cdc_syncfifo_i (
.rdata(cdc_data_out),
.wfull(wfull),
.rempty(cdc_fifo_empty),
.wdata(data_to_fifo), //.wdata({ADC_SYNC,2'd0,ADC_SYNC,14'd0,adc_des}),
.winc(cdc_fifo_write),
.wclk(ADC_ENC),
.wrst(RST_LONG),
.rinc(!fifo_full),
.rclk(BUS_CLK),
.rrst(RST_LONG)
);
gerneric_fifo #(
.DATA_SIZE(32),
.DEPTH(1024)
) fifo_i (
.clk(BUS_CLK),
.reset(RST_LONG | BUS_RST),
.write(!cdc_fifo_empty),
.read(FIFO_READ),
.data_in(cdc_data_out),
.full(fifo_full),
.empty(FIFO_EMPTY),
.data_out(FIFO_DATA[31:0]),
.size()
);
//assign FIFO_DATA[31:30] = 0;
wire DONE_SYNC;
cdc_pulse_sync done_pulse_sync (.clk_in(ADC_ENC), .pulse_in(DONE), .clk_out(BUS_CLK), .pulse_out(DONE_SYNC));
always @(posedge BUS_CLK)
if(RST)
CONF_DONE <= 1;
else if(START)
CONF_DONE <= 0;
else if(DONE_SYNC)
CONF_DONE <= 1;
endmodule
|
module control_test();
reg power, start, weight_ch, mode_ch, clk;
wire [2:0]state, nextstate, weight_ch_light;
wire start_pause_light, water_in_light,
parameter TIME = 1000, DELAY = 10;
controler CONTROLER (
.power(power),
.start_pause(start),
.weight_ch(weight_ch),
.mode_ch(mode_ch),
.weight_ch(weight_ch),
.clk(clk),
.start_pause_light(start_pause_light),
.weight_ch_light(weight_ch_light),
.water_in_light(water_in_light),
.water_out_light(water_out_light),
.washing_light(washing_light),
.rinsing_light(rinsing_light),
.dewatering_light(dewatering_light),
.buzzer_lamp(dewatering_light),
.state(state),
.nextstate(nextstate)
);
initial begin
clk = 0; w_r_d_end = 0;
#TIME $finish;
end
always begin
power = 1; w_r_d = 1; reset = 0; start = 0;
#50 w_r_d = 2;
#50 w_r_d = 3;
#50 w_r_d = 4;
#50 w_r_d = 6;
#3 start = 1;
// #50 w_r_d = 7;
#100 w_r_d_end[2] = 1;
#100 w_r_d_end[1] = 1;
// #100 w_r_d_end[0] = 1;
#100 w_r_d_end = 0;
end
always begin
#DELAY clk = ~clk;
end
endmodule
|
module alu8b (input wire [7:0] A_in,
input wire [7:0] B_in,
input wire C_in,
input wire [2:0] Opcode_in,
output wire [7:0] Result_out,
output wire C_out);
reg [7:0] reg_result;
reg reg_cout;
wire [7:0] temp_sum;
wire temp_cout;
assign Result_out = reg_result;
assign C_out = reg_cout;
assign {temp_cout, temp_sum} = A_in + B_in + C_in;
always @ ( * ) begin
reg_cout = 1'b0; //default carry out
case (Opcode_in)
3'b000: // A+B+Cin
begin
reg_cout = temp_cout;
reg_result = temp_sum;
end
3'b001: // A-B
reg_result = A_in - B_in;
3'b010: // A & B
reg_result = A_in & B_in;
3'b011: // A|B
reg_result = A_in | B_in;
3'b100: // A % B
reg_result = A_in % B_in;
default:
reg_result = 8'b0;
endcase
end
endmodule
|
module ex_pipe_reg
(
input wire clk,
input wire reset,
input wire clr,
input wire valid_ex_pipe_reg_i,
// Inputs from the instr decoder
input wire[2:0] funct3_ex_pipe_reg_i,
input wire[6:0] op_ex_pipe_reg_i,
input wire[4:0] rs1_ex_pipe_reg_i,
input wire[4:0] rs2_ex_pipe_reg_i,
input wire[4:0] rd_ex_pipe_reg_i,
input wire is_r_type_ex_pipe_reg_i,
input wire is_i_type_ex_pipe_reg_i,
input wire is_s_type_ex_pipe_reg_i,
input wire is_b_type_ex_pipe_reg_i,
input wire is_u_type_ex_pipe_reg_i,
input wire is_j_type_ex_pipe_reg_i,
// Inputs from the control unit
input wire[1:0] pc_sel_ex_pipe_reg_i,
input wire op1sel_ex_pipe_reg_i,
input wire[1:0] op2sel_ex_pipe_reg_i,
input wire[1:0] wb_sel_ex_pipe_reg_i,
input wire pc4_sel_ex_pipe_reg_i,
input wire mem_wr_ex_pipe_reg_i,
input wire cpr_en_ex_pipe_reg_i,
input wire wa_sel_ex_pipe_reg_i,
input wire rf_en_ex_pipe_reg_i,
input wire[5:0] alu_fun_ex_pipe_reg_i,
// PC related inputs from issue stage
input wire[31:0] next_seq_pc_ex_pipe_reg_i,
input wire[31:0] curr_pc_ex_pipe_reg_i,
input wire[31:0] next_brn_pc_ex_pipe_reg_i,
input wire[31:0] next_pred_pc_ex_pipe_reg_i,
// Inputs from sign extend units
input wire[31:0] sext_imm_ex_pipe_reg_i,
// Inputs from register file
input wire[31:0] r_data_p1_ex_pipe_reg_i,
input wire[31:0] r_data_p2_ex_pipe_reg_i,
// Inputs from the issue stage
input wire jump_ex_pipe_reg_i,
input wire brn_pred_ex_pipe_reg_i,
// Register outputs
output wire valid_ex_pipe_reg_o,
output wire[2:0] funct3_ex_pipe_reg_o,
output wire[6:0] op_ex_pipe_reg_o,
output wire[4:0] rs1_ex_pipe_reg_o,
output wire[4:0] rs2_ex_pipe_reg_o,
output wire[4:0] rd_ex_pipe_reg_o,
output wire is_r_type_ex_pipe_reg_o,
output wire is_i_type_ex_pipe_reg_o,
output wire is_s_type_ex_pipe_reg_o,
output wire is_b_type_ex_pipe_reg_o,
output wire is_u_type_ex_pipe_reg_o,
output wire is_j_type_ex_pipe_reg_o,
output wire[1:0] pc_sel_ex_pipe_reg_o,
output wire op1sel_ex_pipe_reg_o,
output wire[1:0] op2sel_ex_pipe_reg_o,
output wire[1:0] wb_sel_ex_pipe_reg_o,
output wire pc4_sel_ex_pipe_reg_o,
output wire mem_wr_ex_pipe_reg_o,
output wire cpr_en_ex_pipe_reg_o,
output wire wa_sel_ex_pipe_reg_o,
output wire rf_en_ex_pipe_reg_o,
output wire[5:0] alu_fun_ex_pipe_reg_o,
output wire[31:0] next_seq_pc_ex_pipe_reg_o,
output wire[31:0] curr_pc_ex_pipe_reg_o,
output wire[31:0] next_brn_pc_ex_pipe_reg_o,
output wire[31:0] next_pred_pc_ex_pipe_reg_o,
output wire[31:0] sext_imm_ex_pipe_reg_o,
output wire[31:0] r_data_p1_ex_pipe_reg_o,
output wire[31:0] r_data_p2_ex_pipe_reg_o,
output wire jump_ex_pipe_reg_o,
output wire brn_pred_ex_pipe_reg_o
);
reg valid_ex_pipe_reg;
reg[2:0] funct3_ex_pipe_reg;
reg[6:0] op_ex_pipe_reg;
reg[4:0] rs1_ex_pipe_reg;
reg[4:0] rs2_ex_pipe_reg;
reg[4:0] rd_ex_pipe_reg;
reg is_r_type_ex_pipe_reg;
reg is_i_type_ex_pipe_reg;
reg is_s_type_ex_pipe_reg;
reg is_b_type_ex_pipe_reg;
reg is_u_type_ex_pipe_reg;
reg is_j_type_ex_pipe_reg;
reg[1:0] pc_sel_ex_pipe_reg;
reg op1sel_ex_pipe_reg;
reg[1:0] op2sel_ex_pipe_reg;
reg[1:0] wb_sel_ex_pipe_reg;
reg pc4_sel_ex_pipe_reg;
reg mem_wr_ex_pipe_reg;
reg cpr_en_ex_pipe_reg;
reg wa_sel_ex_pipe_reg;
reg rf_en_ex_pipe_reg;
reg[5:0] alu_fun_ex_pipe_reg;
reg[31:0] next_seq_pc_ex_pipe_reg;
reg[31:0] curr_pc_ex_pipe_reg;
reg[31:0] next_brn_pc_ex_pipe_reg;
reg[31:0] next_pred_pc_ex_pipe_reg;
reg[31:0] sext_imm_ex_pipe_reg;
reg[31:0] r_data_p1_ex_pipe_reg;
reg[31:0] r_data_p2_ex_pipe_reg;
reg jump_ex_pipe_reg;
reg brn_pred_ex_pipe_reg;
assign valid_ex_pipe_reg_o = valid_ex_pipe_reg;
assign funct3_ex_pipe_reg_o = funct3_ex_pipe_reg;
assign op_ex_pipe_reg_o = op_ex_pipe_reg;
assign rs1_ex_pipe_reg_o = rs1_ex_pipe_reg;
assign rs2_ex_pipe_reg_o = rs2_ex_pipe_reg;
assign rd_ex_pipe_reg_o = rd_ex_pipe_reg;
assign is_r_type_ex_pipe_reg_o = is_r_type_ex_pipe_reg;
assign is_i_type_ex_pipe_reg_o = is_i_type_ex_pipe_reg;
assign is_s_type_ex_pipe_reg_o = is_s_type_ex_pipe_reg;
assign is_b_type_ex_pipe_reg_o = is_b_type_ex_pipe_reg;
assign is_u_type_ex_pipe_reg_o = is_u_type_ex_pipe_reg;
assign is_j_type_ex_pipe_reg_o = is_j_type_ex_pipe_reg;
assign pc_sel_ex_pipe_reg_o = pc_sel_ex_pipe_reg;
assign op1sel_ex_pipe_reg_o = op1sel_ex_pipe_reg;
assign op2sel_ex_pipe_reg_o = op2sel_ex_pipe_reg;
assign wb_sel_ex_pipe_reg_o = wb_sel_ex_pipe_reg;
assign pc4_sel_ex_pipe_reg_o = pc4_sel_ex_pipe_reg;
assign mem_wr_ex_pipe_reg_o = mem_wr_ex_pipe_reg;
assign cpr_en_ex_pipe_reg_o = cpr_en_ex_pipe_reg;
assign wa_sel_ex_pipe_reg_o = wa_sel_ex_pipe_reg;
assign rf_en_ex_pipe_reg_o = rf_en_ex_pipe_reg;
assign alu_fun_ex_pipe_reg_o = alu_fun_ex_pipe_reg;
assign next_seq_pc_ex_pipe_reg_o = next_seq_pc_ex_pipe_reg;
assign curr_pc_ex_pipe_reg_o = curr_pc_ex_pipe_reg;
assign next_brn_pc_ex_pipe_reg_o = next_brn_pc_ex_pipe_reg;
assign next_pred_pc_ex_pipe_reg_o = next_pred_pc_ex_pipe_reg;
assign sext_imm_ex_pipe_reg_o = sext_imm_ex_pipe_reg;
assign r_data_p1_ex_pipe_reg_o = r_data_p1_ex_pipe_reg;
assign r_data_p2_ex_pipe_reg_o = r_data_p2_ex_pipe_reg;
assign jump_ex_pipe_reg_o = jump_ex_pipe_reg;
assign brn_pred_ex_pipe_reg_o = brn_pred_ex_pipe_reg;
always @ (posedge clk)
if (reset | clr)
begin
valid_ex_pipe_reg <= 1'b0;
funct3_ex_pipe_reg <= 3'b0;
op_ex_pipe_reg <= 7'b0;
rs1_ex_pipe_reg <= 4'b0;
rs2_ex_pipe_reg <= 4'b0;
rd_ex_pipe_reg <= 4'b0;
is_r_type_ex_pipe_reg <= 1'b0;
is_i_type_ex_pipe_reg <= 1'b0;
is_s_type_ex_pipe_reg <= 1'b0;
is_b_type_ex_pipe_reg <= 1'b0;
is_u_type_ex_pipe_reg <= 1'b0;
is_j_type_ex_pipe_reg <= 1'b0;
pc_sel_ex_pipe_reg <= 2'b0;
op1sel_ex_pipe_reg <= 1'b0;
op2sel_ex_pipe_reg <= 2'b0;
wb_sel_ex_pipe_reg <= 2'b0;
pc4_sel_ex_pipe_reg <= 1'b0;
mem_wr_ex_pipe_reg <= 1'b0;
cpr_en_ex_pipe_reg <= 1'b0;
wa_sel_ex_pipe_reg <= 1'b0;
rf_en_ex_pipe_reg <= 1'b0;
alu_fun_ex_pipe_reg <= 6'b0;
next_seq_pc_ex_pipe_reg <= 31'b0;
curr_pc_ex_pipe_reg <= 31'b0;
next_brn_pc_ex_pipe_reg <= 31'b0;
next_pred_pc_ex_pipe_reg <= 31'b0;
sext_imm_ex_pipe_reg <= 31'b0;
r_data_p1_ex_pipe_reg <= 31'b0;
r_data_p2_ex_pipe_reg <= 31'b0;
jump_ex_pipe_reg <= 1'b0;
brn_pred_ex_pipe_reg <= 1'b0;
end
else
begin
valid_ex_pipe_reg <= valid_ex_pipe_reg_i;
funct3_ex_pipe_reg <= funct3_ex_pipe_reg_i;
op_ex_pipe_reg <= op_ex_pipe_reg_i;
rs1_ex_pipe_reg <= rs1_ex_pipe_reg_i;
rs2_ex_pipe_reg <= rs2_ex_pipe_reg_i;
rd_ex_pipe_reg <= rd_ex_pipe_reg_i;
is_r_type_ex_pipe_reg <= is_r_type_ex_pipe_reg_i;
is_i_type_ex_pipe_reg <= is_i_type_ex_pipe_reg_i;
is_s_type_ex_pipe_reg <= is_s_type_ex_pipe_reg_i;
is_b_type_ex_pipe_reg <= is_b_type_ex_pipe_reg_i;
is_u_type_ex_pipe_reg <= is_u_type_ex_pipe_reg_i;
is_j_type_ex_pipe_reg <= is_j_type_ex_pipe_reg_i;
pc_sel_ex_pipe_reg <= pc_sel_ex_pipe_reg_i;
op1sel_ex_pipe_reg <= op1sel_ex_pipe_reg_i;
op2sel_ex_pipe_reg <= op2sel_ex_pipe_reg_i;
wb_sel_ex_pipe_reg <= wb_sel_ex_pipe_reg_i;
pc4_sel_ex_pipe_reg <= pc4_sel_ex_pipe_reg_i;
mem_wr_ex_pipe_reg <= mem_wr_ex_pipe_reg_i;
cpr_en_ex_pipe_reg <= cpr_en_ex_pipe_reg_i;
wa_sel_ex_pipe_reg <= wa_sel_ex_pipe_reg_i;
rf_en_ex_pipe_reg <= rf_en_ex_pipe_reg_i;
alu_fun_ex_pipe_reg <= alu_fun_ex_pipe_reg_i;
next_seq_pc_ex_pipe_reg <= next_seq_pc_ex_pipe_reg_i;
curr_pc_ex_pipe_reg <= curr_pc_ex_pipe_reg_i;
next_brn_pc_ex_pipe_reg <= next_brn_pc_ex_pipe_reg_i;
next_pred_pc_ex_pipe_reg <= next_pred_pc_ex_pipe_reg_i;
sext_imm_ex_pipe_reg <= sext_imm_ex_pipe_reg_i;
r_data_p1_ex_pipe_reg <= r_data_p1_ex_pipe_reg_i;
r_data_p2_ex_pipe_reg <= r_data_p2_ex_pipe_reg_i;
jump_ex_pipe_reg <= jump_ex_pipe_reg_i;
brn_pred_ex_pipe_reg <= brn_pred_ex_pipe_reg_i;
end
endmodule
|
module regfileparam_test;
// Inputs
reg [3:0] ra;
reg [3:0] rb;
reg [3:0] rw;
reg [15:0] wdat;
reg wren;
reg clk;
reg rst;
// Outputs
wire [15:0] adat, adat2;
wire [15:0] bdat, bdat2;
wire [15:0] acompare;
wire [15:0] bcompare;
assign acompare = adat ^ adat2;
assign bcompare = bdat ^ bdat2;
// Instantiate the Unit Under Test (UUT)
regfileparam #(.BITSIZE(16), .ADDSIZE(4)) uut (
.adat(adat),
.bdat(bdat),
.ra(ra),
.rb(rb),
.rw(rw),
.wdat(wdat),
.wren(wren),
.clk(clk),
.rst(rst)
);
// Instantiate the Unit Under Test (UUT)
regfileparam_behav #(.BITSIZE(16), .ADDSIZE(4)) uut2 (
.adat(adat2),
.bdat(bdat2),
.ra(ra),
.rb(rb),
.rw(rw),
.wdat(wdat),
.wren(wren),
.clk(clk),
.rst(rst)
);
integer i;
always begin
clk = 1;
#10;
clk = 0;
#10;
end
initial begin
// Initialize Inputs
$display($time,,,"Simulation is started.");
ra = 0;
rb = 0;
rw = 0;
wdat = 0;
wren = 0;
rst = 0;
#10 rst = 1;
$display($time,,,"Reset is Asserted");
#15;
// First read from each location.
for(i=0; i<16; i=i+1) begin
ra = i; rb = i; wren = 0;
#20; // Progress time.
$display($time,,,"Port A: Read Address = %d, Read Value = %d \n\t Port B: Read Address = %d, Read Value = %d \n\t Compare Port A: %b, Compare Port B: %b", ra, adat, rb, bdat, acompare, bcompare);
end
$display($time,,,"Now we will write to each register location some random data.");
#20;
// Write to each location.
for(i=0; i<16; i=i+1) begin
rw = i; wren = 1; wdat = $random;
#20; // Progress time.
$display($time,,,"Write Address = %d, Written Value = %d", rw, wdat);
end
$display($time,,,"Now we will read from each register location the data that we have written from each port.");
#20;
// Now Read Again From Each Location.
for(i=0; i<16; i=i+1) begin
ra = i; rb = i; wren = 0;
#20; // Progress time.
$display($time,,,"Port A: Read Address = %d, Read Value = %d \n\t Port B: Read Address = %d, Read Value = %d \n\t Compare Port A: %b, Compare Port B: %b", ra, adat, rb, bdat, acompare, bcompare);
end
$display($time,,,"End of Simulation.");
#20;
end
endmodule
|
module top();
// Inputs are registered
reg A0;
reg A1;
reg A2;
reg A3;
reg S0;
reg S1;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A0 = 1'bX;
A1 = 1'bX;
A2 = 1'bX;
A3 = 1'bX;
S0 = 1'bX;
S1 = 1'bX;
#20 A0 = 1'b0;
#40 A1 = 1'b0;
#60 A2 = 1'b0;
#80 A3 = 1'b0;
#100 S0 = 1'b0;
#120 S1 = 1'b0;
#140 A0 = 1'b1;
#160 A1 = 1'b1;
#180 A2 = 1'b1;
#200 A3 = 1'b1;
#220 S0 = 1'b1;
#240 S1 = 1'b1;
#260 A0 = 1'b0;
#280 A1 = 1'b0;
#300 A2 = 1'b0;
#320 A3 = 1'b0;
#340 S0 = 1'b0;
#360 S1 = 1'b0;
#380 S1 = 1'b1;
#400 S0 = 1'b1;
#420 A3 = 1'b1;
#440 A2 = 1'b1;
#460 A1 = 1'b1;
#480 A0 = 1'b1;
#500 S1 = 1'bx;
#520 S0 = 1'bx;
#540 A3 = 1'bx;
#560 A2 = 1'bx;
#580 A1 = 1'bx;
#600 A0 = 1'bx;
end
sky130_fd_sc_hs__udp_mux_4to2 dut (.A0(A0), .A1(A1), .A2(A2), .A3(A3), .S0(S0), .S1(S1), .X(X));
endmodule
|
module blake2_G(
input wire [63 : 0] a,
input wire [63 : 0] b,
input wire [63 : 0] c,
input wire [63 : 0] d,
input wire [63 : 0] m0,
input wire [63 : 0] m1,
output wire [63 : 0] a_prim,
output wire [63 : 0] b_prim,
output wire [63 : 0] c_prim,
output wire [63 : 0] d_prim
);
//----------------------------------------------------------------
// Wires.
//----------------------------------------------------------------
reg [63 : 0] internal_a_prim;
reg [63 : 0] internal_b_prim;
reg [63 : 0] internal_c_prim;
reg [63 : 0] internal_d_prim;
//----------------------------------------------------------------
// Concurrent connectivity for ports.
//----------------------------------------------------------------
assign a_prim = internal_a_prim;
assign b_prim = internal_b_prim;
assign c_prim = internal_c_prim;
assign d_prim = internal_d_prim;
//----------------------------------------------------------------
// G
//
// The actual G function.
//----------------------------------------------------------------
always @*
begin : G
reg [63 : 0] a0;
reg [63 : 0] a1;
reg [63 : 0] b0;
reg [63 : 0] b1;
reg [63 : 0] b2;
reg [63 : 0] b3;
reg [63 : 0] c0;
reg [63 : 0] c1;
reg [63 : 0] d0;
reg [63 : 0] d1;
reg [63 : 0] d2;
reg [63 : 0] d3;
a0 = a + b + m0;
d0 = d ^ a0;
d1 = {d0[31 : 0], d0[63 : 32]};
c0 = c + d1;
b0 = b ^ c0;
b1 = {b0[23 : 0], b0[63 : 24]};
a1 = a0 + b1 + m1;
d2 = d1 ^ a1;
d3 = {d2[15 : 0], d2[63 : 16]};
c1 = c0 + d3;
b2 = b1 ^ c1;
b3 = {b2[62 : 0], b2[63]};
internal_a_prim = a1;
internal_b_prim = b3;
internal_c_prim = c1;
internal_d_prim = d3;
end // G
endmodule
|
module system_zybo_hdmi_0_0(clk_125, clk_25, hsync, vsync, active, rgb, tmds,
tmdsb, hdmi_cec, hdmi_hpd, hdmi_out_en)
/* synthesis syn_black_box black_box_pad_pin="clk_125,clk_25,hsync,vsync,active,rgb[23:0],tmds[3:0],tmdsb[3:0],hdmi_cec,hdmi_hpd,hdmi_out_en" */;
input clk_125;
input clk_25;
input hsync;
input vsync;
input active;
input [23:0]rgb;
output [3:0]tmds;
output [3:0]tmdsb;
input hdmi_cec;
input hdmi_hpd;
output hdmi_out_en;
endmodule
|
module stage_X(input wire clock
,input wire restart // for synci
,input wire [31:0] restart_pc // for synci
,input wire d_valid
,input wire [31:0] d_instr
,input wire [31:0] d_pc
,input wire [31:0] d_npc
,input wire [ 5:0] d_opcode
,input wire [ 5:0] d_fn
,input wire [ 4:0] d_rd
,input wire [ 5:0] d_rs
,input wire [ 5:0] d_rt
,input wire [ 4:0] d_sa
,input wire [31:0] d_target
,input wire [ 5:0] d_wbr
,input wire d_has_delay_slot
,input wire [31:0] d_op1_val
,input wire [31:0] d_op2_val
,input wire [31:0] d_rt_val
,input wire [31:0] d_simm
,input wire d_restart
,input wire [31:0] d_restart_pc
,input wire d_load_use_hazard
,input wire m_valid
,input wire [ 5:0] m_wbr
,output reg x_valid = 0
,output reg [31:0] x_instr = 0 // XXX for debugging only
,output reg x_is_delay_slot = 0
,output reg [31:0] x_pc = 0
,output reg [ 5:0] x_opcode = 0
,output reg [31:0] x_op1_val = 0 // XXX
,output reg [ 5:0] x_rt = 0
,output reg [31:0] x_rt_val = 0 // for stores only
,output reg [ 5:0] x_wbr = 0
,output reg [31:0] x_res
,output reg x_synci = 0
,output reg [31:0] x_synci_a = 0
,output reg x_restart = 0
,output reg [31:0] x_restart_pc = 0
,output reg x_flush_D = 0
,output reg [31:0] perf_branch_hazard = 0
,input wire [31:0] perf_dcache_misses
,input wire [31:0] perf_delay_slot_bubble
,output reg [31:0] perf_div_hazard = 0
,input wire [31:0] perf_icache_misses
,input wire [31:0] perf_io_load_busy
,input wire [31:0] perf_io_store_busy
,input wire [31:0] perf_load_hit_store_hazard
,output reg [31:0] perf_load_use_hazard = 0
,output reg [31:0] perf_mult_hazard = 0
,input wire [47:0] perf_retired_inst
,input wire [31:0] perf_sb_full
);
parameter FREQ = 0;
parameter debug = 0;
`include "config.h"
reg [31:0] x_op2_val = 0;
reg [ 5:0] x_fn = 0;
reg [ 4:0] x_sa = 0;
wire [31:0] perf_frequency = FREQ / 1000; // Given in Hz, reported in kHz
wire d_ops_eq = d_op1_val == d_op2_val;
reg x_negate_op2 = 0;
always @(posedge clock)
x_negate_op2 <= d_opcode == `SLTI ||
d_opcode == `SLTIU ||
d_opcode == `REG && (d_fn == `SLT ||
d_fn == `SLTU ||
d_fn == `SUB ||
d_fn == `SUBU);
wire [31:0] x_sum;
wire x_carry_flag;
wire [31:0] x_op2_neg = {32{x_negate_op2}} ^ x_op2_val;
assign {x_carry_flag,x_sum} = x_op1_val + x_op2_neg + x_negate_op2;
wire x_sign_flag = x_sum[31];
wire x_overflow_flag = x_op1_val[31] == x_op2_neg[31] &&
x_op1_val[31] != x_sum[31];
wire [4:0] x_shift_dist = x_fn[2] ? x_op1_val[4:0] : x_sa;
// XXX BUG These architectural registers must live in ME or later
// as ME can flush the pipe rendering an update of state in EX
// premature. Of course this leads to headaches with forwarding and
// hazards on instruction depending on these... Sigh.
reg mult_busy = 0;
reg [63:0] mult_a = 0;
`ifdef MULT_RADIX_4
reg [63:0] mult_3a = 0;
`endif
reg [31:0] mult_b = 0;
reg mult_neg = 0;
reg [31:0] mult_lo = 0;
reg [31:0] mult_hi = 0;
reg div_busy = 0, div_neg_res, div_neg_rem;
reg [31:0] divisor = 0, div_hi = 0, div_lo = 0;
wire [64:0] div_shifted = {div_hi, div_lo, 1'd0};
wire [32:0] div_diff = div_shifted[64:32] - divisor;
reg [ 6:0] div_n = 0;
`ifdef LATER
reg [31:0] cp0_status = 0, // XXX -- " --
cp0_epc = 0,
cp0_errorepc = 0,
cp0_cause = 0;
`endif
reg x_has_delay_slot = 0;
reg [35:0] tsc = 0; // Free running counter
reg branch_event = 0;
reg [31:0] x_special = 0; // A value that can be precomputed
always @(posedge clock)
case (d_opcode)
`REG: x_special <= d_npc + 4;
`REGIMM: x_special <= d_npc + 4;
`JAL: x_special <= d_npc + 4;
`RDHWR:
case (d_rd)
0: x_special <= 0; // # of processors-1
1: x_special <= 4 << IC_WORD_INDEX_BITS;
2: x_special <= tsc[35:4]; // @40 MHz 28 min before rollover
3: x_special <= 1 << 4; // TSC scaling factor
4: x_special <= tsc[31:0]; // Unscaled, but truncated TSC (local hack)
endcase
`LUI: x_special <= {d_simm[15: 0], 16'd0};
`CP2:
case (d_rd)
`PERF_BRANCH_HAZARD: x_special <= perf_branch_hazard;
`PERF_DCACHE_MISSES: x_special <= perf_dcache_misses;
`PERF_DELAY_SLOT_BUBBLE: x_special <= perf_delay_slot_bubble;
`PERF_DIV_HAZARD: x_special <= perf_div_hazard;
`PERF_FREQUENCY: x_special <= perf_frequency;
`PERF_ICACHE_MISSES: x_special <= perf_icache_misses;
`PERF_IO_LOAD_BUSY: x_special <= perf_io_load_busy;
`PERF_IO_STORE_BUSY: x_special <= perf_io_store_busy;
`PERF_LOAD_HIT_STORE_HAZARD: x_special <= perf_load_hit_store_hazard;
`PERF_LOAD_USE_HAZARD: x_special <= perf_load_use_hazard;
`PERF_MULT_HAZARD: x_special <= perf_mult_hazard;
// Count 16 retired instructions. @40 MHz 1 CPI, it takes 28 min to roll over
`PERF_RETIRED_INST: x_special <= perf_retired_inst[35:4];
`PERF_SB_FULL: x_special <= perf_sb_full;
endcase
endcase
/*
* The ALU
*/
always @* begin
x_res = 32'hXXXXXXXX;
case (x_opcode)
`REG:
case (x_fn)
`SLL : x_res = x_op2_val << x_shift_dist;
`SRL : x_res = x_op2_val >> x_shift_dist;
`SRA : x_res = $signed(x_op2_val) >>> x_shift_dist;
`SLLV: x_res = x_op2_val << x_shift_dist;
`SRLV: x_res = x_op2_val >> x_shift_dist;
`SRAV: x_res = $signed(x_op2_val) >>> x_shift_dist;
`JALR: x_res = x_special;
// XXX BUG See the comment above with mult_lo and mult_hi
`MFHI: x_res = mult_hi;
`MFLO: x_res = mult_lo;
// XXX BUG Trap on overflow for ADD, ADDI and SUB
`ADD: x_res = x_sum;
`ADDU: x_res = x_sum;
`SUB: x_res = x_sum;
`SUBU: x_res = x_sum;
`AND: x_res = x_op1_val & x_op2_val;
`OR: x_res = x_op1_val | x_op2_val;
`XOR: x_res = x_op1_val ^ x_op2_val;
`NOR: x_res = ~(x_op1_val | x_op2_val);
`SLT: x_res = {{31{1'b0}}, x_sign_flag ^ x_overflow_flag};
`SLTU: x_res = {{31{1'b0}}, ~x_carry_flag};
default: x_res = 32'hXXXXXXXX;
endcase
`REGIMM: x_res = x_special;// BLTZ, BGEZ, BLTZAL, BGEZAL
`JAL: x_res = x_special;
`ADDI: x_res = x_sum;
`ADDIU: x_res = x_sum;
`SLTI: x_res = {{31{1'b0}}, x_sign_flag ^ x_overflow_flag};
`SLTIU: x_res = {{31{1'b0}}, ~x_carry_flag};
`ANDI: x_res = {16'b0, x_op1_val[15:0] & x_op2_val[15:0]};
`ORI: x_res = {x_op1_val[31:16], x_op1_val[15:0] | x_op2_val[15:0]};
`XORI: x_res = {x_op1_val[31:16], x_op1_val[15:0] ^ x_op2_val[15:0]};
`LUI: x_res = x_special;
//`CP1:
`RDHWR: x_res = x_special;
`CP2: x_res = x_special;
default: x_res = 32'hXXXXXXXX;
endcase
end
always @(posedge clock) begin
tsc <= tsc + 1;
x_valid <= d_valid;
x_instr <= d_instr;
x_pc <= d_pc;
x_opcode <= d_opcode;
x_fn <= d_fn;
x_sa <= d_sa;
x_op1_val <= d_op1_val;
x_op2_val <= d_op2_val;
x_rt <= d_rt;
x_rt_val <= d_rt_val;
x_wbr <= d_wbr;
x_has_delay_slot <= d_has_delay_slot & d_valid;
x_is_delay_slot <= x_has_delay_slot & x_valid;
x_restart <= 0;
x_restart_pc <= d_target;
x_flush_D <= 0;
x_synci <= 0;
/* Stat counts aren't critical, so I delay them to keep them out
of the critical path */
if (branch_event)
perf_branch_hazard <= perf_branch_hazard + 1;
branch_event <= 0;
//`define MULT_RADIX_4 1
`ifdef MULT_RADIX_4
// Radix-2 Multiplication Machine (this is not the best way to do this)
if (mult_busy) begin
$display("MULT[U] %x * %x + %x", mult_a, mult_b, {mult_hi,mult_lo});
case (mult_b[1:0])
1: {mult_hi,mult_lo} <= {mult_hi,mult_lo} + mult_a;
2: {mult_hi,mult_lo} <= {mult_hi,mult_lo} + (mult_a << 1);
3: {mult_hi,mult_lo} <= {mult_hi,mult_lo} + mult_3a;
endcase
mult_a <= mult_a << 2;
mult_3a <= mult_3a << 2;
mult_b <= mult_b >> 2;
if (mult_b == 0) begin
if (mult_neg) begin
{mult_hi,mult_lo} <= 64'd0 - {mult_hi,mult_lo};
mult_neg <= 0;
end else
mult_busy <= 0;
$display("MULT[U] = %x", mult_a + {mult_hi,mult_lo});
end
end
`else
// Radix-2 Multiplication Machine (this is not the best way to do this)
if (mult_busy) begin
$display("MULT[U] %x * %x + %x", mult_a, mult_b, {mult_hi,mult_lo});
if (mult_b[0])
{mult_hi,mult_lo} <= {mult_hi,mult_lo} + mult_a;
mult_a <= mult_a << 1;
mult_b <= mult_b >> 1;
if (mult_b == 0) begin
if (mult_neg) begin
{mult_hi,mult_lo} <= 64'd0 - {mult_hi,mult_lo};
mult_neg <= 0;
end else
mult_busy <= 0;
$display("MULT[U] = %x", mult_a + {mult_hi,mult_lo});
end
end
`endif
/*
* Division uses a simple algorithm:
* for 1 .. 32:
* divident = divident << 1
* if (divident >= (divisor << 32)):
* divident = divident - (divisor << 32) + 1
* result = divisor & 0xFFFF_FFFF
*/
if (!div_n[6]) begin
{div_hi,div_lo} <= div_shifted[63:0];
if (!div_diff[32]) begin
div_hi <= div_diff[31:0];
div_lo[0] <= 1'd1;
end
div_n <= div_n - 1'd1;
end else if (div_busy) begin
div_busy <= 0;
mult_lo <= div_neg_res ? -div_lo : div_lo; // result
mult_hi <= div_neg_rem ? -div_hi : div_hi; // remainder
$display("DIV = hi %d lo %d",
div_neg_rem ? -div_hi : div_hi,
div_neg_res ? -div_lo : div_lo);
end
case (d_opcode)
`REG:
case (d_fn)
`JALR:
if (d_valid) begin
$display("JAL: d_npc = %x", d_npc);
x_restart <= 1;
x_restart_pc <= d_op1_val;
branch_event <= 1;
end
`JR:
if (d_valid) begin
x_restart <= 1;
x_restart_pc <= d_op1_val;
branch_event <= 1;
end
// XXX BUG See the comment above with mult_lo and mult_hi
`MFHI:
if ((mult_busy | div_busy) && d_valid) begin
x_flush_D <= 1;
x_valid <= 0;
x_restart_pc <= d_pc - {x_has_delay_slot,2'd0};
x_restart <= 1;
if (mult_busy)
perf_mult_hazard <= perf_mult_hazard + 1;
else
perf_div_hazard <= perf_div_hazard + 1;
end
`MFLO:
if ((mult_busy | div_busy) && d_valid) begin
x_flush_D <= 1;
x_valid <= 0;
x_restart_pc <= d_pc - {x_has_delay_slot,2'd0};
x_restart <= 1;
if (mult_busy)
perf_mult_hazard <= perf_mult_hazard + 1;
else
perf_div_hazard <= perf_div_hazard + 1;
end
`MTHI:
if (d_valid) begin
if (mult_busy | div_busy) begin
x_flush_D <= 1;
x_valid <= 0;
x_restart_pc <= d_pc - {x_has_delay_slot,2'd0};
x_restart <= 1;
if (mult_busy)
perf_mult_hazard <= perf_mult_hazard + 1;
else
perf_div_hazard <= perf_div_hazard + 1;
end else
mult_hi <= d_op1_val;
end
`MTLO:
if (d_valid) begin
if (mult_busy | div_busy) begin
x_flush_D <= 1;
x_valid <= 0;
x_restart_pc <= d_pc - {x_has_delay_slot,2'd0};
x_restart <= 1;
if (mult_busy)
perf_mult_hazard <= perf_mult_hazard + 1;
else
perf_div_hazard <= perf_div_hazard + 1;
end else
mult_lo <= d_op1_val;
end
`DIV:
if (d_valid)
if (mult_busy | div_busy) begin
x_flush_D <= 1;
x_valid <= 0;
x_restart_pc <= d_pc - {x_has_delay_slot,2'd0};
x_restart <= 1;
if (mult_busy)
perf_mult_hazard <= perf_mult_hazard + 1;
else
perf_div_hazard <= perf_div_hazard + 1;
end else begin
div_busy <= 1;
div_hi <= 0;
div_lo <= d_op1_val[31] ? -d_op1_val : d_op1_val;
divisor <= d_op2_val[31] ? -d_op2_val : d_op2_val;
div_neg_res <= d_op1_val[31] ^ d_op2_val[31];
// res = a/b, rem = a - b*(a/b)
// thus the rem sign follows a only
div_neg_rem <= d_op1_val[31];
div_n <= 31;
$display("%05dc EX: %d / %d", $time, d_op1_val, d_op2_val);
end
`DIVU:
if (d_valid)
if (mult_busy | div_busy) begin
x_flush_D <= 1;
x_valid <= 0;
x_restart_pc <= d_pc - {x_has_delay_slot,2'd0};
x_restart <= 1;
if (mult_busy)
perf_mult_hazard <= perf_mult_hazard + 1;
else
perf_div_hazard <= perf_div_hazard + 1;
end else begin
div_busy <= 1;
div_hi <= 0;
div_lo <= d_op1_val;
divisor <= d_op2_val;
div_neg_res <= 0;
div_neg_rem <= 0;
div_n <= 31;
$display("%05dc EX: %d /U %d", $time, d_op1_val, d_op2_val);
end
`MULTU:
if (d_valid)
if (mult_busy | div_busy) begin
x_flush_D <= 1;
x_valid <= 0;
x_restart_pc <= d_pc - {x_has_delay_slot,2'd0};
x_restart <= 1;
if (mult_busy)
perf_mult_hazard <= perf_mult_hazard + 1;
else
perf_div_hazard <= perf_div_hazard + 1;
end else begin
$display("MULTU %x * %x", d_op1_val, d_op2_val);
mult_busy <= 1;
mult_hi <= 0;
mult_lo <= 0;
mult_a <= d_op1_val;
mult_b <= d_op2_val;
`ifdef MULT_RADIX_4
mult_3a <= 3 * d_op1_val;
`endif
mult_neg <= 0;
$display("%05dc EX: %dU * %dU", $time, d_op1_val, d_op2_val);
end
`MULT:
if (d_valid)
if (mult_busy | div_busy) begin
x_flush_D <= 1;
x_valid <= 0;
x_restart_pc <= d_pc - {x_has_delay_slot,2'd0};
x_restart <= 1;
if (mult_busy)
perf_mult_hazard <= perf_mult_hazard + 1;
else
perf_div_hazard <= perf_div_hazard + 1;
end else begin
$display("MULT %x * %x", d_op1_val, d_op2_val);
mult_busy <= 1;
mult_hi <= 0;
mult_lo <= 0;
mult_neg <= d_op1_val[31] ^ d_op2_val[31];
mult_a <= d_op1_val[31] ? {32'd0,32'd0 - d_op1_val} : d_op1_val;
`ifdef MULT_RADIX_4
mult_3a <= d_op1_val[31] ? 3 * {32'd0,32'd0-d_op1_val} : 3 * d_op1_val;
`endif
mult_b <= d_op2_val[31] ? 32'd0 - d_op2_val : d_op2_val;
$display("%05dc EX: %d * %d", $time, d_op1_val, d_op2_val);
end
`BREAK:
if (d_valid) begin
x_restart <= 1;
x_restart_pc <= 'hBFC00380;
x_flush_D <= 1;
`ifdef LATER
cp0_status[`CP0_STATUS_EXL] <= 1;
//cp0_cause.exc_code = EXC_BP;
cp0_cause <= 9 << 2;
// cp0_cause.bd = branch_delay_slot; // XXX DELAY SLOT HANDLING!
cp0_epc <= d_pc; // XXX DELAY SLOT HANDLING!
`endif
end
endcase
`REGIMM: // BLTZ, BGEZ, BLTZAL, BGEZAL
if (d_valid)
if (d_rt[4:0] == `SYNCI) begin
x_restart <= 1;
x_restart_pc <= x_restart ? restart_pc : d_npc;
x_flush_D <= 1;
$display("synci restart at %x (d_restart = %d, d_restart_pc = %x, d_npc = %x)",
d_restart ? d_restart_pc : d_npc,
d_restart, d_restart_pc, d_npc);
x_synci <= 1;
x_synci_a <= d_op1_val + d_simm;
end else begin
x_restart <= d_rt[0] ^ d_op1_val[31];
branch_event <= 1;
end
`JAL:
if (d_valid) begin
x_restart <= 1;
branch_event <= 1;
end
`J: if (d_valid) x_restart <= 1;
`BEQ:
if (d_valid) begin
x_restart <= d_ops_eq;
branch_event <= d_ops_eq;
$display("%05d BEQ %8x == %8x (%1d)", $time,
d_op1_val, d_op2_val, d_ops_eq);
end
`BNE:
if (d_valid) begin
x_restart <= ~d_ops_eq;
branch_event <= ~d_ops_eq;
$display("%05d BNE %8x != %8x (%1d) target %8x", $time,
d_op1_val, d_op2_val, !d_ops_eq, d_target);
end
`BLEZ:
if (d_valid) begin
x_restart <= d_op1_val[31] || d_op1_val == 0;
branch_event <= (d_op1_val[31] || d_op1_val == 0);
end
`BGTZ:
// XXX Share logic
if (d_valid) begin
x_restart <= !d_op1_val[31] && d_op1_val != 0;
branch_event <= (!d_op1_val[31] && d_op1_val != 0);
end
`CP2: begin
`ifdef SIMULATE_MAIN
if (d_valid && !d_rs[4] && 0) begin
if (mult_lo == 32'h87654321)
$display("TEST SUCCEEDED!");
else
$display("%05d TEST FAILED WITH %x (%1d:%8x:%8x)", $time, mult_lo,
d_valid, d_pc, d_instr);
$finish; // XXX do something more interesting for real hw.
end else
`endif
if (~d_rs[4])
if (d_rs[2])
$display("MTCP2 r%d <- %x (ignored)", d_rd, d_op2_val);
else
$display("MFCP2 r%d", d_rd);
end
/*
* XXX Comment out the CP0 handling for now. I want to handle
* that in a way that doesn't affect the performance of the
* regular instructions
*/
`ifdef LATER
`CP0: if (d_valid) begin
/* Two possible formats */
if (d_rs[4]) begin
if (d_fn == `C0_ERET) begin
/* Exception Return */
x_restart <= 1;
x_flush_D <= 1; // XXX BUG? Check that ERET doesn't have a delay slot!
if (cp0_status[`CP0_STATUS_ERL]) begin
x_restart_pc <= cp0_errorepc;
cp0_status[`CP0_STATUS_ERL] <= 0;
`ifdef SIMULATE_MAIN
$display("ERET ERROREPC %x", cp0_errorepc);
`endif
end else begin
x_restart_pc <= cp0_epc;
cp0_status[`CP0_STATUS_EXL] <= 0;
`ifdef SIMULATE_MAIN
$display("ERET EPC %x", cp0_epc);
`endif
end
end
`ifdef SIMULATE_MAIN
else
/* C1 format */
$display("Unhandled CP0 command %s\n",
d_fn == `C0_TLBR ? "tlbr" :
d_fn == `C0_TLBWI ? "tlbwi" :
d_fn == `C0_TLBWR ? "tlbwr" :
d_fn == `C0_TLBP ? "tlbp" :
d_fn == `C0_ERET ? "eret" :
d_fn == `C0_DERET ? "deret" :
d_fn == `C0_WAIT ? "wait" :
"???");
`endif
end else begin
`ifdef SIMULATE_MAIN
if (d_rs[2])
$display("MTCP0 r%d <- %x", d_rd, d_op2_val);
else
$display("MFCP0 r%d", d_rd);
if (d_fn != 0) $display("d_fn == %x", d_fn);
`endif
if (d_rs[2]) begin
x_wbr <= 0; // XXX BUG?
// cp0regs[i.r.rd] = t;
case (d_rd)
`CP0_STATUS:
begin
cp0_status <= d_op2_val;
$display("STATUS <= %x", d_op2_val);
end
`CP0_CAUSE:
begin
cp0_cause <= d_op2_val;
$display("CAUSE <= %x", d_op2_val);
end
`CP0_EPC:
begin
cp0_epc <= d_op2_val;
$display("EPC <= %x", d_op2_val);
end
`CP0_ERROREPC:
begin
cp0_errorepc <= d_op2_val;
$display("ERROREPC <= %x", d_op2_val);
end
/*
cp0_status.raw = t;
cp0_status.res1 = cp0_status.res2 = 0;
printf("Operating mode %s\n",
cp0_status.ksu == 0 ? "kernel" :
cp0_status.ksu == 1 ? "supervisor" :
cp0_status.ksu == 2 ? "user" : "??");
printf("Exception level %d\n", cp0_status.exl);
printf("Error level %d\n", cp0_status.erl);
printf("Interrupts %sabled\n", cp0_status.ie ? "en" : "dis");
break;
*/
default:
$display("Setting an unknown CP0 register %d", d_rd);
//case CP0_CAUSE:
endcase
end
end
end
`endif
endcase
if (d_load_use_hazard)
perf_load_use_hazard <= perf_load_use_hazard + 1;
end
endmodule
|
module execute_branch(
input wire [31:0] iDATA_0,
input wire [31:0] iDATA_1,
input wire [31:0] iPC,
input wire [4:0] iFLAG,
input wire [3:0] iCC,
input wire [4:0] iCMD,
output wire [31:0] oBRANCH_ADDR,
output wire oJUMP_VALID,
output wire oNOT_JUMP_VALID,
output wire oIB_VALID,
output wire oIDTS_VALID,
output wire oHALT_VALID
);
assign oBRANCH_ADDR = func_branch_addr(
iCMD,
iPC,
iDATA_1
);
function [31:0] func_branch_addr;
input [4:0] func_cmd;
input [31:0] func_pc;
input [31:0] func_source1;
begin
case(func_cmd)
`EXE_BRANCH_BUR:
begin
func_branch_addr = func_source1 + func_pc;
end
`EXE_BRANCH_BR:
begin
func_branch_addr = func_source1 + func_pc;
end
`EXE_BRANCH_B:
begin
func_branch_addr = func_source1;
end
`EXE_BRANCH_INTB:
begin
func_branch_addr = 32'h0;
end
`EXE_BRANCH_IDTS:
begin
func_branch_addr = func_pc + 32'h0000004;
end
default:
begin
func_branch_addr = 32'h0;
end
endcase
end
endfunction
assign oJUMP_VALID = (iCMD != `EXE_BRANCH_INTB && iCMD != `EXE_BRANCH_IDTS)? func_ex_branch_check(iCC, iFLAG) : 1'b0;
assign oNOT_JUMP_VALID = (iCMD != `EXE_BRANCH_INTB && iCMD != `EXE_BRANCH_IDTS)? !func_ex_branch_check(iCC, iFLAG) : 1'b0;
assign oIB_VALID = (iCMD == `EXE_BRANCH_INTB)? 1'b1 : 1'b0;
assign oIDTS_VALID = (iCMD == `EXE_BRANCH_IDTS)? 1'b1 : 1'b0;
assign oHALT_VALID = (iCMD == `EXE_BRANCH_HALT)? 1'b1 : 1'b0;
function func_ex_branch_check;
input [3:0] func_ex_branch_check_cc;
input [4:0] func_ex_branch_check_flag;
begin
case(func_ex_branch_check_cc)
`CC_AL : func_ex_branch_check = 1'b1;
`CC_EQ :
begin
if(func_ex_branch_check_flag[`FLAGS_ZF])begin
func_ex_branch_check = 1'b1;
end
else begin
func_ex_branch_check = 1'b0;
end
end
`CC_NEQ :
begin
if(!func_ex_branch_check_flag[`FLAGS_ZF])begin
func_ex_branch_check = 1'b1;
end
else begin
func_ex_branch_check = 1'b0;
end
end
`CC_MI :
begin
func_ex_branch_check = func_ex_branch_check_flag[`FLAGS_SF];
end
`CC_PL :
begin
func_ex_branch_check = !func_ex_branch_check_flag[`FLAGS_SF];
end
`CC_EN :
begin
if(!func_ex_branch_check_flag[`FLAGS_PF])begin
func_ex_branch_check = 1'b1;
end
else begin
func_ex_branch_check = 1'b0;
end
end
`CC_ON :
begin
if(func_ex_branch_check_flag[`FLAGS_PF])begin
func_ex_branch_check = 1'b1;
end
else begin
func_ex_branch_check = 1'b0;
end
end
`CC_OVF :
begin
if(func_ex_branch_check_flag[`FLAGS_OF])begin
func_ex_branch_check = 1'b1;
end
else begin
func_ex_branch_check = 1'b0;
end
end
`CC_UEO :
begin
func_ex_branch_check = func_ex_branch_check_flag[`FLAGS_CF];
end
`CC_UU :
begin
func_ex_branch_check = !func_ex_branch_check_flag[`FLAGS_CF];
end
`CC_UO :
begin
func_ex_branch_check = func_ex_branch_check_flag[`FLAGS_CF] && !func_ex_branch_check_flag[`FLAGS_ZF];
end
`CC_UEU :
begin
func_ex_branch_check = !func_ex_branch_check_flag[`FLAGS_CF] || func_ex_branch_check_flag[`FLAGS_ZF];
end
`CC_SEO :
begin
func_ex_branch_check = (func_ex_branch_check_flag[`FLAGS_SF] && func_ex_branch_check_flag[`FLAGS_OF]) || (!func_ex_branch_check_flag[`FLAGS_SF] && !func_ex_branch_check_flag[`FLAGS_OF]);
end
`CC_SU :
begin
func_ex_branch_check = (func_ex_branch_check_flag[`FLAGS_SF] && !func_ex_branch_check_flag[`FLAGS_OF]) || (!func_ex_branch_check_flag[`FLAGS_SF] && func_ex_branch_check_flag[`FLAGS_OF]);
end
`CC_SO :
begin
func_ex_branch_check = !((func_ex_branch_check_flag[`FLAGS_SF] ^ func_ex_branch_check_flag[`FLAGS_OF]) || func_ex_branch_check_flag[`FLAGS_ZF]);
end
`CC_SEU :
begin
func_ex_branch_check = (func_ex_branch_check_flag[`FLAGS_SF] ^ func_ex_branch_check_flag[`FLAGS_OF]) || func_ex_branch_check_flag[`FLAGS_ZF];
end
default : func_ex_branch_check = 1'b1;
endcase
end
endfunction
endmodule
|
module ReadWrite#
(
parameter[ 3 : 0 ]ReadState = 0, // read raw data operation
parameter[ 3 : 0 ]ProcessState = 1, // color correction
parameter[ 3 : 0 ]WriteState = 2
)
(
input Clock,
input Reset,
input[ `size_char - 1 : 0 ]R,
input[ `size_char - 1 : 0 ]G,
input[ `size_char - 1 : 0 ]B,
output reg[ `size_char - 1 : 0 ]R_out,
output reg[ `size_char - 1 : 0 ]G_out,
output reg[ `size_char - 1 : 0 ]B_out
);
reg[ `size_int - 1 : 0 ]ScaleR[ 0 : `SumPixel - 1 ];
reg[ `size_int - 1 : 0 ]ScaleG[ 0 : `SumPixel - 1 ];
reg[ `size_int - 1 : 0 ]ScaleB[ 0 : `SumPixel - 1 ];
reg[ 3 : 0 ]StateNow;
reg[ 3 : 0 ]StateNext;
integer ReadIndex;
integer WriteIndex;
always@( posedge Clock )
begin
if( Reset == 1'b1 )
begin
ReadIndex = 0;
WriteIndex = 0;
StateNext = ReadState;
end
end
always@( StateNext )
StateNow = StateNext;
always@( posedge Clock )
begin
if( StateNow == ReadState )
begin
////////////////
// read raw data
ScaleR[ ReadIndex ] = R << `ScaleBit;
ScaleG[ ReadIndex ] = G << `ScaleBit;
ScaleB[ ReadIndex ] = B << `ScaleBit;
ReadIndex = ReadIndex + 1;
if( ReadIndex == `SumPixel )
StateNext = ProcessState;
end
else if( StateNow == WriteState )
begin
if( WriteIndex < `SumPixel )
begin
R_out = ScaleR[ WriteIndex ] >> `ScaleBit;
G_out = ScaleG[ WriteIndex ] >> `ScaleBit;
B_out = ScaleB[ WriteIndex ] >> `ScaleBit;
WriteIndex = WriteIndex + 1;
end
end
end
always@( StateNow )
begin
case( StateNow )
ProcessState:
begin
//
// work here
//
StateNext = WriteState;
end
endcase
end
endmodule
|
module ReadWrite_testbench;
// Signal declaration
reg Clock;
reg Reset;
reg[ `size_char - 1 : 0 ]R;
reg[ `size_char - 1 : 0 ]G;
reg[ `size_char - 1 : 0 ]B;
wire[ `size_char - 1 : 0 ]R_out;
wire[ `size_char - 1 : 0 ]G_out;
wire[ `size_char - 1 : 0 ]B_out;
reg[ `size_char - 1 : 0 ]RBlock[ 0 : `SumPixel - 1 ];
reg[ `size_char - 1 : 0 ]GBlock[ 0 : `SumPixel - 1 ];
reg[ `size_char - 1 : 0 ]BBlock[ 0 : `SumPixel - 1 ];
integer i;
integer RFile;
integer GFile;
integer BFile;
ReadWrite ReadWrite_test
(
Clock,
Reset,
R,
G,
B,
R_out,
G_out,
B_out
);
initial
begin
#2
begin
// open test data file
$readmemh( "data/IM000565_RAW_20x15R.dat", RBlock );
$readmemh( "data/IM000565_RAW_20x15G.dat", GBlock );
$readmemh( "data/IM000565_RAW_20x15B.dat", BBlock );
end
#2 Reset = 1'b1;
// Apply Stimulus
for( i = 0; i < `SumPixel; i = i + 1 )
begin
#2
begin
// initialization, start to read data into buffer
Reset = 1'b0;
R = RBlock[ i ];
G = GBlock[ i ];
B = BBlock[ i ];
end
end
#2
begin
RFile = $fopen( "data/R.dat" );
GFile = $fopen( "data/G.dat" );
BFile = $fopen( "data/B.dat" );
end
for( i = 0; i < `SumPixel; i = i + 1 )
begin
#2
begin
// display information on the screen
//$display( "R = %d, G = %d, B = %d\t\tR = %d, G = %d, B = %d",
// RBlock[ i ], GBlock[ i ], BBlock[ i ], R_out, G_out, B_out );
if( i % 16 == 0 )
begin
$fwrite( RFile, "\n" );
$fwrite( GFile, "\n" );
$fwrite( BFile, "\n" );
end
$fwrite( RFile, "%X ", R_out );
$fwrite( GFile, "%X ", G_out );
$fwrite( BFile, "%X ", B_out );
end
end
$fclose( RFile );
$fclose( GFile );
$fclose( BFile );
#100000 $stop;
#100000 $finish;
end
initial Clock = 0;
always #1 Clock = ~Clock; //Toggle Clock
endmodule
|
module soc_system_button_pio (
// inputs:
address,
chipselect,
clk,
in_port,
reset_n,
write_n,
writedata,
// outputs:
irq,
readdata
)
;
output irq;
output [ 31: 0] readdata;
input [ 1: 0] address;
input chipselect;
input clk;
input [ 1: 0] in_port;
input reset_n;
input write_n;
input [ 31: 0] writedata;
wire clk_en;
reg [ 1: 0] d1_data_in;
reg [ 1: 0] d2_data_in;
wire [ 1: 0] data_in;
reg [ 1: 0] edge_capture;
wire edge_capture_wr_strobe;
wire [ 1: 0] edge_detect;
wire irq;
reg [ 1: 0] irq_mask;
wire [ 1: 0] read_mux_out;
reg [ 31: 0] readdata;
assign clk_en = 1;
//s1, which is an e_avalon_slave
assign read_mux_out = ({2 {(address == 0)}} & data_in) |
({2 {(address == 2)}} & irq_mask) |
({2 {(address == 3)}} & edge_capture);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
readdata <= 0;
else if (clk_en)
readdata <= {32'b0 | read_mux_out};
end
assign data_in = in_port;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
irq_mask <= 0;
else if (chipselect && ~write_n && (address == 2))
irq_mask <= writedata[1 : 0];
end
assign irq = |(edge_capture & irq_mask);
assign edge_capture_wr_strobe = chipselect && ~write_n && (address == 3);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
edge_capture[0] <= 0;
else if (clk_en)
if (edge_capture_wr_strobe && writedata[0])
edge_capture[0] <= 0;
else if (edge_detect[0])
edge_capture[0] <= -1;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
edge_capture[1] <= 0;
else if (clk_en)
if (edge_capture_wr_strobe && writedata[1])
edge_capture[1] <= 0;
else if (edge_detect[1])
edge_capture[1] <= -1;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
d1_data_in <= 0;
d2_data_in <= 0;
end
else if (clk_en)
begin
d1_data_in <= data_in;
d2_data_in <= d1_data_in;
end
end
assign edge_detect = ~d1_data_in & d2_data_in;
endmodule
|
module testbench();
`include "bsg_noc_links.vh"
import bsg_noc_pkg::*;
// Sync with trace gen
localparam hdr_width_p = 32;
localparam cord_width_p = 2;
localparam len_width_p = 3;
localparam flit_width_p = 8;
localparam pr_data_width_p = 16;
localparam wh_hdr_width_p = cord_width_p + len_width_p;
localparam pr_hdr_width_p = hdr_width_p - wh_hdr_width_p;
localparam hdr_flits_p = hdr_width_p / flit_width_p;
localparam data_width_p = flit_width_p*(2**len_width_p-hdr_flits_p+1);
localparam data_flits_p = data_width_p / flit_width_p;
localparam ring_width_p = 1+`BSG_MAX(`BSG_MAX(hdr_width_p, pr_data_width_p), flit_width_p);
localparam rom_data_width_p = 4 + ring_width_p;
localparam rom_addr_width_p = 32;
logic clk;
bsg_nonsynth_clock_gen #(
.cycle_time_p(1000)
) clock_gen (
.o(clk)
);
logic reset;
bsg_nonsynth_reset_gen #(
.num_clocks_p(1)
,.reset_cycles_lo_p(4)
,.reset_cycles_hi_p(4)
) reset_gen (
.clk_i(clk)
,.async_reset_o(reset)
);
`declare_bsg_ready_and_link_sif_s(flit_width_p, bsg_ready_and_link_sif_s);
bsg_ready_and_link_sif_s link_lo, link_li;
bsg_ready_and_link_sif_s out_link_lo, out_link_li;
`declare_bsg_ready_and_link_sif_s(flit_width_p/4, bsg_narrow_link_sif_s);
bsg_narrow_link_sif_s narrow_link_li, narrow_link_lo;
logic [3:0] backpressure_cnt;
always_ff @(posedge clk)
if (reset)
backpressure_cnt <= '0;
else
backpressure_cnt <= backpressure_cnt + 1'b1;
wire backpressure = backpressure_cnt[0];
bsg_parallel_in_serial_out_passthrough
#(.width_p(flit_width_p/4), .els_p(4))
pisop
(.clk_i(clk)
,.reset_i(reset)
,.data_i(link_li.data)
,.v_i(link_li.v)
,.ready_and_o(link_lo.ready_and_rev)
,.data_o(narrow_link_lo.data)
,.v_o(narrow_link_lo.v)
,.ready_and_i(narrow_link_li.ready_and_rev & ~backpressure)
);
bsg_serial_in_parallel_out_passthrough
#(.width_p(flit_width_p/4), .els_p(4))
sipop
(.clk_i(clk)
,.reset_i(reset)
,.data_i(narrow_link_lo.data)
,.v_i(narrow_link_lo.v & ~backpressure)
,.ready_and_o(narrow_link_li.ready_and_rev)
,.data_o(out_link_li.data)
,.v_o(out_link_li.v)
,.ready_and_i(out_link_lo.ready_and_rev)
);
// TODO: Actually set
assign out_link_lo.ready_and_rev = 1'b1;
logic [63:0] counter;
always_ff @(posedge clk)
if (reset)
counter <= '0;
else
counter <= counter + 1'b1;
wire select_top = (counter % 68 == 0);
wire select_bot = (counter % 87 == 0);
wire select_left = (counter % 44 == 0);
wire select_right = (counter % 73 == 0);
logic [flit_width_p-1:0] left_data_li;
logic left_yumi_lo;
wire left_v_li = select_left;
initial
begin
left_data_li = '0;
for (integer i = 70; i < 170; i+=0)
begin
left_data_li = i << (cord_width_p);
@(left_yumi_lo);
@(negedge clk);
i += 1'b1;
end
end
logic [flit_width_p-1:0] right_data_li;
logic right_yumi_lo;
wire right_v_li = select_right;
initial
begin
right_data_li = '0;
for (integer i = 10; i < 110; i+=0)
begin
right_data_li = i << (cord_width_p);
@(right_yumi_lo);
@(negedge clk);
i += 1'b1;
end
end
logic [flit_width_p-1:0] top_data_li;
logic top_yumi_lo;
wire top_v_li = select_top;
initial
begin
top_data_li = '0;
for (integer i = 25; i < 125; i+=0)
begin
top_data_li = i << (cord_width_p);
@(top_yumi_lo);
@(negedge clk);
i += 1'b1;
end
end
logic [flit_width_p-1:0] bot_data_li;
logic bot_yumi_lo;
wire bot_v_li = select_bot;
initial
begin
bot_data_li = '0;
for (integer i = 50; i < 150; i+=0)
begin
bot_data_li = i << (cord_width_p);
@(bot_yumi_lo);
@(negedge clk);
i += 1'b1;
end
end
bsg_ready_and_link_sif_s [S:P] router_link_li, router_link_lo;
bsg_mesh_router_buffered
#(.width_p(flit_width_p)
,.x_cord_width_p(1)
,.y_cord_width_p(cord_width_p-1)
,.dirs_lp(5)
)
router
(.clk_i(clk)
,.reset_i(reset)
,.link_i(router_link_li)
,.link_o(router_link_lo)
,.my_x_i('0)
,.my_y_i('0)
);
assign router_link_li[S].data = bot_data_li;
assign router_link_li[N].data = top_data_li;
assign router_link_li[E].data = right_data_li;
assign router_link_li[W].data = left_data_li;
assign router_link_li[P].data = '0;
assign router_link_li[S].v = bot_v_li;
assign router_link_li[N].v = top_v_li;
assign router_link_li[E].v = right_v_li;
assign router_link_li[W].v = left_v_li;
assign router_link_li[P].v = '0;
assign router_link_li[S].ready_and_rev ='0;
assign router_link_li[N].ready_and_rev ='0;
assign router_link_li[E].ready_and_rev ='0;
assign router_link_li[W].ready_and_rev ='0;
assign router_link_li[P].ready_and_rev = link_lo.ready_and_rev;
assign bot_yumi_lo = router_link_lo[S].ready_and_rev & router_link_li[S].v;
assign top_yumi_lo = router_link_lo[N].ready_and_rev & router_link_li[N].v;
assign right_yumi_lo = router_link_lo[E].ready_and_rev & router_link_li[E].v;
assign left_yumi_lo = router_link_lo[W].ready_and_rev & router_link_li[W].v;
assign link_li.data = router_link_lo[P].data;
assign link_li.v = router_link_lo[P].v;
initial
begin
$assertoff();
@(posedge clk)
@(negedge reset)
$asserton();
end
endmodule
|
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(LEDs_out, s00_axi_awaddr, s00_axi_awprot,
s00_axi_awvalid, s00_axi_awready, s00_axi_wdata, s00_axi_wstrb, s00_axi_wvalid,
s00_axi_wready, s00_axi_bresp, s00_axi_bvalid, s00_axi_bready, s00_axi_araddr,
s00_axi_arprot, s00_axi_arvalid, s00_axi_arready, s00_axi_rdata, s00_axi_rresp,
s00_axi_rvalid, s00_axi_rready, s00_axi_aclk, s00_axi_aresetn)
/* synthesis syn_black_box black_box_pad_pin="LEDs_out[7:0],s00_axi_awaddr[3:0],s00_axi_awprot[2:0],s00_axi_awvalid,s00_axi_awready,s00_axi_wdata[31:0],s00_axi_wstrb[3:0],s00_axi_wvalid,s00_axi_wready,s00_axi_bresp[1:0],s00_axi_bvalid,s00_axi_bready,s00_axi_araddr[3:0],s00_axi_arprot[2:0],s00_axi_arvalid,s00_axi_arready,s00_axi_rdata[31:0],s00_axi_rresp[1:0],s00_axi_rvalid,s00_axi_rready,s00_axi_aclk,s00_axi_aresetn" */;
output [7:0]LEDs_out;
input [3:0]s00_axi_awaddr;
input [2:0]s00_axi_awprot;
input s00_axi_awvalid;
output s00_axi_awready;
input [31:0]s00_axi_wdata;
input [3:0]s00_axi_wstrb;
input s00_axi_wvalid;
output s00_axi_wready;
output [1:0]s00_axi_bresp;
output s00_axi_bvalid;
input s00_axi_bready;
input [3:0]s00_axi_araddr;
input [2:0]s00_axi_arprot;
input s00_axi_arvalid;
output s00_axi_arready;
output [31:0]s00_axi_rdata;
output [1:0]s00_axi_rresp;
output s00_axi_rvalid;
input s00_axi_rready;
input s00_axi_aclk;
input s00_axi_aresetn;
endmodule
|
module sky130_fd_sc_hdll__einvp (
Z ,
A ,
TE
);
// Module ports
output Z ;
input A ;
input TE;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Name Output Other arguments
notif1 notif10 (Z , A, TE );
endmodule
|
module
//The map generator acts as a datapath for the static objects in the game
always @(posedge clk_vga) begin
//Starting castle
if(mapX == 3 && mapY == 5)
mColor[7:0] <= startCastle[7:0];
//Central hallway
else if(mapX == 3 && mapY == 6)
mColor[7:0] <= hallwayTop[7:0];
//Right hallway
else if(mapX == 4 && mapY == 6)
mColor[7:0] <= hallwayRight[7:0];
//Black key room
else if(mapX == 4 && mapY == 7)
mColor[7:0] <= blackKeyRoom[7:0];
//Left hallway
else if(mapX == 2 && mapY == 6)
mColor[7:0] <= hallwayLeft;
//South Center Maze
else if(mapX == 1 && mapY == 6)
mColor[7:0] <= sCenterMaze;
//South West Maze
else if(mapX == 2 && mapY == 4)
mColor[7:0] <= swMaze;
//East Center Maze
else if(mapX == 2 && mapY == 5)
mColor[7:0] <= eCenterMaze;
//Center Maze
else if(mapX == 1 && mapY == 5)
mColor[7:0] <= centerMaze;
//North Center Maze
else if(mapX == 1 && mapY == 4)
mColor[7:0] <= nCenterMaze;
//Black Castle
else if(mapX == 1 && mapY == 3)
mColor[7:0] <= castle;
//Challice Room
else if(mapX == 1 && mapY == 2)
mColor[7:0] <= startCastle;
//No map found
else begin
mColor[7:0] <= 8'b00000000;
end
end
assign mapData[7:0] = mColor[7:0];
endmodule
|
module sky130_fd_sc_ms__einvn_8 (
Z ,
A ,
TE_B,
VPWR,
VGND,
VPB ,
VNB
);
output Z ;
input A ;
input TE_B;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ms__einvn base (
.Z(Z),
.A(A),
.TE_B(TE_B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
|
module sky130_fd_sc_ms__einvn_8 (
Z ,
A ,
TE_B
);
output Z ;
input A ;
input TE_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__einvn base (
.Z(Z),
.A(A),
.TE_B(TE_B)
);
endmodule
|
module processing_system7_0 (
ENET0_PTP_DELAY_REQ_RX,
ENET0_PTP_DELAY_REQ_TX,
ENET0_PTP_PDELAY_REQ_RX,
ENET0_PTP_PDELAY_REQ_TX,
ENET0_PTP_PDELAY_RESP_RX,
ENET0_PTP_PDELAY_RESP_TX,
ENET0_PTP_SYNC_FRAME_RX,
ENET0_PTP_SYNC_FRAME_TX,
ENET0_SOF_RX,
ENET0_SOF_TX,
GPIO_I,
GPIO_O,
GPIO_T,
I2C0_SDA_I,
I2C0_SDA_O,
I2C0_SDA_T,
I2C0_SCL_I,
I2C0_SCL_O,
I2C0_SCL_T,
USB0_PORT_INDCTL,
USB0_VBUS_PWRSELECT,
USB0_VBUS_PWRFAULT,
USB1_PORT_INDCTL,
USB1_VBUS_PWRSELECT,
USB1_VBUS_PWRFAULT,
M_AXI_GP1_ARVALID,
M_AXI_GP1_AWVALID,
M_AXI_GP1_BREADY,
M_AXI_GP1_RREADY,
M_AXI_GP1_WLAST,
M_AXI_GP1_WVALID,
M_AXI_GP1_ARID,
M_AXI_GP1_AWID,
M_AXI_GP1_WID,
M_AXI_GP1_ARBURST,
M_AXI_GP1_ARLOCK,
M_AXI_GP1_ARSIZE,
M_AXI_GP1_AWBURST,
M_AXI_GP1_AWLOCK,
M_AXI_GP1_AWSIZE,
M_AXI_GP1_ARPROT,
M_AXI_GP1_AWPROT,
M_AXI_GP1_ARADDR,
M_AXI_GP1_AWADDR,
M_AXI_GP1_WDATA,
M_AXI_GP1_ARCACHE,
M_AXI_GP1_ARLEN,
M_AXI_GP1_ARQOS,
M_AXI_GP1_AWCACHE,
M_AXI_GP1_AWLEN,
M_AXI_GP1_AWQOS,
M_AXI_GP1_WSTRB,
M_AXI_GP1_ACLK,
M_AXI_GP1_ARREADY,
M_AXI_GP1_AWREADY,
M_AXI_GP1_BVALID,
M_AXI_GP1_RLAST,
M_AXI_GP1_RVALID,
M_AXI_GP1_WREADY,
M_AXI_GP1_BID,
M_AXI_GP1_RID,
M_AXI_GP1_BRESP,
M_AXI_GP1_RRESP,
M_AXI_GP1_RDATA,
S_AXI_HP1_ARREADY,
S_AXI_HP1_AWREADY,
S_AXI_HP1_BVALID,
S_AXI_HP1_RLAST,
S_AXI_HP1_RVALID,
S_AXI_HP1_WREADY,
S_AXI_HP1_BRESP,
S_AXI_HP1_RRESP,
S_AXI_HP1_BID,
S_AXI_HP1_RID,
S_AXI_HP1_RDATA,
S_AXI_HP1_RCOUNT,
S_AXI_HP1_WCOUNT,
S_AXI_HP1_RACOUNT,
S_AXI_HP1_WACOUNT,
S_AXI_HP1_ACLK,
S_AXI_HP1_ARVALID,
S_AXI_HP1_AWVALID,
S_AXI_HP1_BREADY,
S_AXI_HP1_RDISSUECAP1_EN,
S_AXI_HP1_RREADY,
S_AXI_HP1_WLAST,
S_AXI_HP1_WRISSUECAP1_EN,
S_AXI_HP1_WVALID,
S_AXI_HP1_ARBURST,
S_AXI_HP1_ARLOCK,
S_AXI_HP1_ARSIZE,
S_AXI_HP1_AWBURST,
S_AXI_HP1_AWLOCK,
S_AXI_HP1_AWSIZE,
S_AXI_HP1_ARPROT,
S_AXI_HP1_AWPROT,
S_AXI_HP1_ARADDR,
S_AXI_HP1_AWADDR,
S_AXI_HP1_ARCACHE,
S_AXI_HP1_ARLEN,
S_AXI_HP1_ARQOS,
S_AXI_HP1_AWCACHE,
S_AXI_HP1_AWLEN,
S_AXI_HP1_AWQOS,
S_AXI_HP1_ARID,
S_AXI_HP1_AWID,
S_AXI_HP1_WID,
S_AXI_HP1_WDATA,
S_AXI_HP1_WSTRB,
FCLK_CLK0,
FCLK_CLK3,
FCLK_RESET0_N,
MIO,
DDR_CAS_n,
DDR_CKE,
DDR_Clk_n,
DDR_Clk,
DDR_CS_n,
DDR_DRSTB,
DDR_ODT,
DDR_RAS_n,
DDR_WEB,
DDR_BankAddr,
DDR_Addr,
DDR_VRN,
DDR_VRP,
DDR_DM,
DDR_DQ,
DDR_DQS_n,
DDR_DQS,
PS_SRSTB,
PS_CLK,
PS_PORB
);
output ENET0_PTP_DELAY_REQ_RX;
output ENET0_PTP_DELAY_REQ_TX;
output ENET0_PTP_PDELAY_REQ_RX;
output ENET0_PTP_PDELAY_REQ_TX;
output ENET0_PTP_PDELAY_RESP_RX;
output ENET0_PTP_PDELAY_RESP_TX;
output ENET0_PTP_SYNC_FRAME_RX;
output ENET0_PTP_SYNC_FRAME_TX;
output ENET0_SOF_RX;
output ENET0_SOF_TX;
input [47 : 0] GPIO_I;
output [47 : 0] GPIO_O;
output [47 : 0] GPIO_T;
input I2C0_SDA_I;
output I2C0_SDA_O;
output I2C0_SDA_T;
input I2C0_SCL_I;
output I2C0_SCL_O;
output I2C0_SCL_T;
output [1 : 0] USB0_PORT_INDCTL;
output USB0_VBUS_PWRSELECT;
input USB0_VBUS_PWRFAULT;
output [1 : 0] USB1_PORT_INDCTL;
output USB1_VBUS_PWRSELECT;
input USB1_VBUS_PWRFAULT;
output M_AXI_GP1_ARVALID;
output M_AXI_GP1_AWVALID;
output M_AXI_GP1_BREADY;
output M_AXI_GP1_RREADY;
output M_AXI_GP1_WLAST;
output M_AXI_GP1_WVALID;
output [11 : 0] M_AXI_GP1_ARID;
output [11 : 0] M_AXI_GP1_AWID;
output [11 : 0] M_AXI_GP1_WID;
output [1 : 0] M_AXI_GP1_ARBURST;
output [1 : 0] M_AXI_GP1_ARLOCK;
output [2 : 0] M_AXI_GP1_ARSIZE;
output [1 : 0] M_AXI_GP1_AWBURST;
output [1 : 0] M_AXI_GP1_AWLOCK;
output [2 : 0] M_AXI_GP1_AWSIZE;
output [2 : 0] M_AXI_GP1_ARPROT;
output [2 : 0] M_AXI_GP1_AWPROT;
output [31 : 0] M_AXI_GP1_ARADDR;
output [31 : 0] M_AXI_GP1_AWADDR;
output [31 : 0] M_AXI_GP1_WDATA;
output [3 : 0] M_AXI_GP1_ARCACHE;
output [3 : 0] M_AXI_GP1_ARLEN;
output [3 : 0] M_AXI_GP1_ARQOS;
output [3 : 0] M_AXI_GP1_AWCACHE;
output [3 : 0] M_AXI_GP1_AWLEN;
output [3 : 0] M_AXI_GP1_AWQOS;
output [3 : 0] M_AXI_GP1_WSTRB;
input M_AXI_GP1_ACLK;
input M_AXI_GP1_ARREADY;
input M_AXI_GP1_AWREADY;
input M_AXI_GP1_BVALID;
input M_AXI_GP1_RLAST;
input M_AXI_GP1_RVALID;
input M_AXI_GP1_WREADY;
input [11 : 0] M_AXI_GP1_BID;
input [11 : 0] M_AXI_GP1_RID;
input [1 : 0] M_AXI_GP1_BRESP;
input [1 : 0] M_AXI_GP1_RRESP;
input [31 : 0] M_AXI_GP1_RDATA;
output S_AXI_HP1_ARREADY;
output S_AXI_HP1_AWREADY;
output S_AXI_HP1_BVALID;
output S_AXI_HP1_RLAST;
output S_AXI_HP1_RVALID;
output S_AXI_HP1_WREADY;
output [1 : 0] S_AXI_HP1_BRESP;
output [1 : 0] S_AXI_HP1_RRESP;
output [5 : 0] S_AXI_HP1_BID;
output [5 : 0] S_AXI_HP1_RID;
output [63 : 0] S_AXI_HP1_RDATA;
output [7 : 0] S_AXI_HP1_RCOUNT;
output [7 : 0] S_AXI_HP1_WCOUNT;
output [2 : 0] S_AXI_HP1_RACOUNT;
output [5 : 0] S_AXI_HP1_WACOUNT;
input S_AXI_HP1_ACLK;
input S_AXI_HP1_ARVALID;
input S_AXI_HP1_AWVALID;
input S_AXI_HP1_BREADY;
input S_AXI_HP1_RDISSUECAP1_EN;
input S_AXI_HP1_RREADY;
input S_AXI_HP1_WLAST;
input S_AXI_HP1_WRISSUECAP1_EN;
input S_AXI_HP1_WVALID;
input [1 : 0] S_AXI_HP1_ARBURST;
input [1 : 0] S_AXI_HP1_ARLOCK;
input [2 : 0] S_AXI_HP1_ARSIZE;
input [1 : 0] S_AXI_HP1_AWBURST;
input [1 : 0] S_AXI_HP1_AWLOCK;
input [2 : 0] S_AXI_HP1_AWSIZE;
input [2 : 0] S_AXI_HP1_ARPROT;
input [2 : 0] S_AXI_HP1_AWPROT;
input [31 : 0] S_AXI_HP1_ARADDR;
input [31 : 0] S_AXI_HP1_AWADDR;
input [3 : 0] S_AXI_HP1_ARCACHE;
input [3 : 0] S_AXI_HP1_ARLEN;
input [3 : 0] S_AXI_HP1_ARQOS;
input [3 : 0] S_AXI_HP1_AWCACHE;
input [3 : 0] S_AXI_HP1_AWLEN;
input [3 : 0] S_AXI_HP1_AWQOS;
input [5 : 0] S_AXI_HP1_ARID;
input [5 : 0] S_AXI_HP1_AWID;
input [5 : 0] S_AXI_HP1_WID;
input [63 : 0] S_AXI_HP1_WDATA;
input [7 : 0] S_AXI_HP1_WSTRB;
output FCLK_CLK0;
output FCLK_CLK3;
output FCLK_RESET0_N;
input [53 : 0] MIO;
input DDR_CAS_n;
input DDR_CKE;
input DDR_Clk_n;
input DDR_Clk;
input DDR_CS_n;
input DDR_DRSTB;
input DDR_ODT;
input DDR_RAS_n;
input DDR_WEB;
input [2 : 0] DDR_BankAddr;
input [14 : 0] DDR_Addr;
input DDR_VRN;
input DDR_VRP;
input [3 : 0] DDR_DM;
input [31 : 0] DDR_DQ;
input [3 : 0] DDR_DQS_n;
input [3 : 0] DDR_DQS;
input PS_SRSTB;
input PS_CLK;
input PS_PORB;
processing_system7_bfm_v2_0_processing_system7_bfm #(
.C_USE_M_AXI_GP0(0),
.C_USE_M_AXI_GP1(1),
.C_USE_S_AXI_ACP(0),
.C_USE_S_AXI_GP0(0),
.C_USE_S_AXI_GP1(0),
.C_USE_S_AXI_HP0(0),
.C_USE_S_AXI_HP1(1),
.C_USE_S_AXI_HP2(0),
.C_USE_S_AXI_HP3(0),
.C_S_AXI_HP0_DATA_WIDTH(32),
.C_S_AXI_HP1_DATA_WIDTH(64),
.C_S_AXI_HP2_DATA_WIDTH(64),
.C_S_AXI_HP3_DATA_WIDTH(64),
.C_HIGH_OCM_EN(0),
.C_FCLK_CLK0_FREQ(100),
.C_FCLK_CLK1_FREQ(200),
.C_FCLK_CLK2_FREQ(200),
.C_FCLK_CLK3_FREQ(40),
.C_M_AXI_GP0_ENABLE_STATIC_REMAP(0),
.C_M_AXI_GP1_ENABLE_STATIC_REMAP(0),
.C_M_AXI_GP0_THREAD_ID_WIDTH (12),
.C_M_AXI_GP1_THREAD_ID_WIDTH (12)
) inst (
.M_AXI_GP0_ARVALID(),
.M_AXI_GP0_AWVALID(),
.M_AXI_GP0_BREADY(),
.M_AXI_GP0_RREADY(),
.M_AXI_GP0_WLAST(),
.M_AXI_GP0_WVALID(),
.M_AXI_GP0_ARID(),
.M_AXI_GP0_AWID(),
.M_AXI_GP0_WID(),
.M_AXI_GP0_ARBURST(),
.M_AXI_GP0_ARLOCK(),
.M_AXI_GP0_ARSIZE(),
.M_AXI_GP0_AWBURST(),
.M_AXI_GP0_AWLOCK(),
.M_AXI_GP0_AWSIZE(),
.M_AXI_GP0_ARPROT(),
.M_AXI_GP0_AWPROT(),
.M_AXI_GP0_ARADDR(),
.M_AXI_GP0_AWADDR(),
.M_AXI_GP0_WDATA(),
.M_AXI_GP0_ARCACHE(),
.M_AXI_GP0_ARLEN(),
.M_AXI_GP0_ARQOS(),
.M_AXI_GP0_AWCACHE(),
.M_AXI_GP0_AWLEN(),
.M_AXI_GP0_AWQOS(),
.M_AXI_GP0_WSTRB(),
.M_AXI_GP0_ACLK(1'B0),
.M_AXI_GP0_ARREADY(1'B0),
.M_AXI_GP0_AWREADY(1'B0),
.M_AXI_GP0_BVALID(1'B0),
.M_AXI_GP0_RLAST(1'B0),
.M_AXI_GP0_RVALID(1'B0),
.M_AXI_GP0_WREADY(1'B0),
.M_AXI_GP0_BID(12'B0),
.M_AXI_GP0_RID(12'B0),
.M_AXI_GP0_BRESP(2'B0),
.M_AXI_GP0_RRESP(2'B0),
.M_AXI_GP0_RDATA(32'B0),
.M_AXI_GP1_ARVALID(M_AXI_GP1_ARVALID),
.M_AXI_GP1_AWVALID(M_AXI_GP1_AWVALID),
.M_AXI_GP1_BREADY(M_AXI_GP1_BREADY),
.M_AXI_GP1_RREADY(M_AXI_GP1_RREADY),
.M_AXI_GP1_WLAST(M_AXI_GP1_WLAST),
.M_AXI_GP1_WVALID(M_AXI_GP1_WVALID),
.M_AXI_GP1_ARID(M_AXI_GP1_ARID),
.M_AXI_GP1_AWID(M_AXI_GP1_AWID),
.M_AXI_GP1_WID(M_AXI_GP1_WID),
.M_AXI_GP1_ARBURST(M_AXI_GP1_ARBURST),
.M_AXI_GP1_ARLOCK(M_AXI_GP1_ARLOCK),
.M_AXI_GP1_ARSIZE(M_AXI_GP1_ARSIZE),
.M_AXI_GP1_AWBURST(M_AXI_GP1_AWBURST),
.M_AXI_GP1_AWLOCK(M_AXI_GP1_AWLOCK),
.M_AXI_GP1_AWSIZE(M_AXI_GP1_AWSIZE),
.M_AXI_GP1_ARPROT(M_AXI_GP1_ARPROT),
.M_AXI_GP1_AWPROT(M_AXI_GP1_AWPROT),
.M_AXI_GP1_ARADDR(M_AXI_GP1_ARADDR),
.M_AXI_GP1_AWADDR(M_AXI_GP1_AWADDR),
.M_AXI_GP1_WDATA(M_AXI_GP1_WDATA),
.M_AXI_GP1_ARCACHE(M_AXI_GP1_ARCACHE),
.M_AXI_GP1_ARLEN(M_AXI_GP1_ARLEN),
.M_AXI_GP1_ARQOS(M_AXI_GP1_ARQOS),
.M_AXI_GP1_AWCACHE(M_AXI_GP1_AWCACHE),
.M_AXI_GP1_AWLEN(M_AXI_GP1_AWLEN),
.M_AXI_GP1_AWQOS(M_AXI_GP1_AWQOS),
.M_AXI_GP1_WSTRB(M_AXI_GP1_WSTRB),
.M_AXI_GP1_ACLK(M_AXI_GP1_ACLK),
.M_AXI_GP1_ARREADY(M_AXI_GP1_ARREADY),
.M_AXI_GP1_AWREADY(M_AXI_GP1_AWREADY),
.M_AXI_GP1_BVALID(M_AXI_GP1_BVALID),
.M_AXI_GP1_RLAST(M_AXI_GP1_RLAST),
.M_AXI_GP1_RVALID(M_AXI_GP1_RVALID),
.M_AXI_GP1_WREADY(M_AXI_GP1_WREADY),
.M_AXI_GP1_BID(M_AXI_GP1_BID),
.M_AXI_GP1_RID(M_AXI_GP1_RID),
.M_AXI_GP1_BRESP(M_AXI_GP1_BRESP),
.M_AXI_GP1_RRESP(M_AXI_GP1_RRESP),
.M_AXI_GP1_RDATA(M_AXI_GP1_RDATA),
.S_AXI_GP0_ARREADY(),
.S_AXI_GP0_AWREADY(),
.S_AXI_GP0_BVALID(),
.S_AXI_GP0_RLAST(),
.S_AXI_GP0_RVALID(),
.S_AXI_GP0_WREADY(),
.S_AXI_GP0_BRESP(),
.S_AXI_GP0_RRESP(),
.S_AXI_GP0_RDATA(),
.S_AXI_GP0_BID(),
.S_AXI_GP0_RID(),
.S_AXI_GP0_ACLK(1'B0),
.S_AXI_GP0_ARVALID(1'B0),
.S_AXI_GP0_AWVALID(1'B0),
.S_AXI_GP0_BREADY(1'B0),
.S_AXI_GP0_RREADY(1'B0),
.S_AXI_GP0_WLAST(1'B0),
.S_AXI_GP0_WVALID(1'B0),
.S_AXI_GP0_ARBURST(2'B0),
.S_AXI_GP0_ARLOCK(2'B0),
.S_AXI_GP0_ARSIZE(3'B0),
.S_AXI_GP0_AWBURST(2'B0),
.S_AXI_GP0_AWLOCK(2'B0),
.S_AXI_GP0_AWSIZE(3'B0),
.S_AXI_GP0_ARPROT(3'B0),
.S_AXI_GP0_AWPROT(3'B0),
.S_AXI_GP0_ARADDR(32'B0),
.S_AXI_GP0_AWADDR(32'B0),
.S_AXI_GP0_WDATA(32'B0),
.S_AXI_GP0_ARCACHE(4'B0),
.S_AXI_GP0_ARLEN(4'B0),
.S_AXI_GP0_ARQOS(4'B0),
.S_AXI_GP0_AWCACHE(4'B0),
.S_AXI_GP0_AWLEN(4'B0),
.S_AXI_GP0_AWQOS(4'B0),
.S_AXI_GP0_WSTRB(4'B0),
.S_AXI_GP0_ARID(6'B0),
.S_AXI_GP0_AWID(6'B0),
.S_AXI_GP0_WID(6'B0),
.S_AXI_GP1_ARREADY(),
.S_AXI_GP1_AWREADY(),
.S_AXI_GP1_BVALID(),
.S_AXI_GP1_RLAST(),
.S_AXI_GP1_RVALID(),
.S_AXI_GP1_WREADY(),
.S_AXI_GP1_BRESP(),
.S_AXI_GP1_RRESP(),
.S_AXI_GP1_RDATA(),
.S_AXI_GP1_BID(),
.S_AXI_GP1_RID(),
.S_AXI_GP1_ACLK(1'B0),
.S_AXI_GP1_ARVALID(1'B0),
.S_AXI_GP1_AWVALID(1'B0),
.S_AXI_GP1_BREADY(1'B0),
.S_AXI_GP1_RREADY(1'B0),
.S_AXI_GP1_WLAST(1'B0),
.S_AXI_GP1_WVALID(1'B0),
.S_AXI_GP1_ARBURST(2'B0),
.S_AXI_GP1_ARLOCK(2'B0),
.S_AXI_GP1_ARSIZE(3'B0),
.S_AXI_GP1_AWBURST(2'B0),
.S_AXI_GP1_AWLOCK(2'B0),
.S_AXI_GP1_AWSIZE(3'B0),
.S_AXI_GP1_ARPROT(3'B0),
.S_AXI_GP1_AWPROT(3'B0),
.S_AXI_GP1_ARADDR(32'B0),
.S_AXI_GP1_AWADDR(32'B0),
.S_AXI_GP1_WDATA(32'B0),
.S_AXI_GP1_ARCACHE(4'B0),
.S_AXI_GP1_ARLEN(4'B0),
.S_AXI_GP1_ARQOS(4'B0),
.S_AXI_GP1_AWCACHE(4'B0),
.S_AXI_GP1_AWLEN(4'B0),
.S_AXI_GP1_AWQOS(4'B0),
.S_AXI_GP1_WSTRB(4'B0),
.S_AXI_GP1_ARID(6'B0),
.S_AXI_GP1_AWID(6'B0),
.S_AXI_GP1_WID(6'B0),
.S_AXI_ACP_ARREADY(),
.S_AXI_ACP_AWREADY(),
.S_AXI_ACP_BVALID(),
.S_AXI_ACP_RLAST(),
.S_AXI_ACP_RVALID(),
.S_AXI_ACP_WREADY(),
.S_AXI_ACP_BRESP(),
.S_AXI_ACP_RRESP(),
.S_AXI_ACP_BID(),
.S_AXI_ACP_RID(),
.S_AXI_ACP_RDATA(),
.S_AXI_ACP_ACLK(1'B0),
.S_AXI_ACP_ARVALID(1'B0),
.S_AXI_ACP_AWVALID(1'B0),
.S_AXI_ACP_BREADY(1'B0),
.S_AXI_ACP_RREADY(1'B0),
.S_AXI_ACP_WLAST(1'B0),
.S_AXI_ACP_WVALID(1'B0),
.S_AXI_ACP_ARID(3'B0),
.S_AXI_ACP_ARPROT(3'B0),
.S_AXI_ACP_AWID(3'B0),
.S_AXI_ACP_AWPROT(3'B0),
.S_AXI_ACP_WID(3'B0),
.S_AXI_ACP_ARADDR(32'B0),
.S_AXI_ACP_AWADDR(32'B0),
.S_AXI_ACP_ARCACHE(4'B0),
.S_AXI_ACP_ARLEN(4'B0),
.S_AXI_ACP_ARQOS(4'B0),
.S_AXI_ACP_AWCACHE(4'B0),
.S_AXI_ACP_AWLEN(4'B0),
.S_AXI_ACP_AWQOS(4'B0),
.S_AXI_ACP_ARBURST(2'B0),
.S_AXI_ACP_ARLOCK(2'B0),
.S_AXI_ACP_ARSIZE(3'B0),
.S_AXI_ACP_AWBURST(2'B0),
.S_AXI_ACP_AWLOCK(2'B0),
.S_AXI_ACP_AWSIZE(3'B0),
.S_AXI_ACP_ARUSER(5'B0),
.S_AXI_ACP_AWUSER(5'B0),
.S_AXI_ACP_WDATA(64'B0),
.S_AXI_ACP_WSTRB(8'B0),
.S_AXI_HP0_ARREADY(),
.S_AXI_HP0_AWREADY(),
.S_AXI_HP0_BVALID(),
.S_AXI_HP0_RLAST(),
.S_AXI_HP0_RVALID(),
.S_AXI_HP0_WREADY(),
.S_AXI_HP0_BRESP(),
.S_AXI_HP0_RRESP(),
.S_AXI_HP0_BID(),
.S_AXI_HP0_RID(),
.S_AXI_HP0_RDATA(),
.S_AXI_HP0_ACLK(1'B0),
.S_AXI_HP0_ARVALID(1'B0),
.S_AXI_HP0_AWVALID(1'B0),
.S_AXI_HP0_BREADY(1'B0),
.S_AXI_HP0_RREADY(1'B0),
.S_AXI_HP0_WLAST(1'B0),
.S_AXI_HP0_WVALID(1'B0),
.S_AXI_HP0_ARBURST(2'B0),
.S_AXI_HP0_ARLOCK(2'B0),
.S_AXI_HP0_ARSIZE(3'B0),
.S_AXI_HP0_AWBURST(2'B0),
.S_AXI_HP0_AWLOCK(2'B0),
.S_AXI_HP0_AWSIZE(3'B0),
.S_AXI_HP0_ARPROT(3'B0),
.S_AXI_HP0_AWPROT(3'B0),
.S_AXI_HP0_ARADDR(32'B0),
.S_AXI_HP0_AWADDR(32'B0),
.S_AXI_HP0_ARCACHE(4'B0),
.S_AXI_HP0_ARLEN(4'B0),
.S_AXI_HP0_ARQOS(4'B0),
.S_AXI_HP0_AWCACHE(4'B0),
.S_AXI_HP0_AWLEN(4'B0),
.S_AXI_HP0_AWQOS(4'B0),
.S_AXI_HP0_ARID(6'B0),
.S_AXI_HP0_AWID(6'B0),
.S_AXI_HP0_WID(6'B0),
.S_AXI_HP0_WDATA(32'B0),
.S_AXI_HP0_WSTRB(4'B0),
.S_AXI_HP1_ARREADY(S_AXI_HP1_ARREADY),
.S_AXI_HP1_AWREADY(S_AXI_HP1_AWREADY),
.S_AXI_HP1_BVALID(S_AXI_HP1_BVALID),
.S_AXI_HP1_RLAST(S_AXI_HP1_RLAST),
.S_AXI_HP1_RVALID(S_AXI_HP1_RVALID),
.S_AXI_HP1_WREADY(S_AXI_HP1_WREADY),
.S_AXI_HP1_BRESP(S_AXI_HP1_BRESP),
.S_AXI_HP1_RRESP(S_AXI_HP1_RRESP),
.S_AXI_HP1_BID(S_AXI_HP1_BID),
.S_AXI_HP1_RID(S_AXI_HP1_RID),
.S_AXI_HP1_RDATA(S_AXI_HP1_RDATA),
.S_AXI_HP1_ACLK(S_AXI_HP1_ACLK),
.S_AXI_HP1_ARVALID(S_AXI_HP1_ARVALID),
.S_AXI_HP1_AWVALID(S_AXI_HP1_AWVALID),
.S_AXI_HP1_BREADY(S_AXI_HP1_BREADY),
.S_AXI_HP1_RREADY(S_AXI_HP1_RREADY),
.S_AXI_HP1_WLAST(S_AXI_HP1_WLAST),
.S_AXI_HP1_WVALID(S_AXI_HP1_WVALID),
.S_AXI_HP1_ARBURST(S_AXI_HP1_ARBURST),
.S_AXI_HP1_ARLOCK(S_AXI_HP1_ARLOCK),
.S_AXI_HP1_ARSIZE(S_AXI_HP1_ARSIZE),
.S_AXI_HP1_AWBURST(S_AXI_HP1_AWBURST),
.S_AXI_HP1_AWLOCK(S_AXI_HP1_AWLOCK),
.S_AXI_HP1_AWSIZE(S_AXI_HP1_AWSIZE),
.S_AXI_HP1_ARPROT(S_AXI_HP1_ARPROT),
.S_AXI_HP1_AWPROT(S_AXI_HP1_AWPROT),
.S_AXI_HP1_ARADDR(S_AXI_HP1_ARADDR),
.S_AXI_HP1_AWADDR(S_AXI_HP1_AWADDR),
.S_AXI_HP1_ARCACHE(S_AXI_HP1_ARCACHE),
.S_AXI_HP1_ARLEN(S_AXI_HP1_ARLEN),
.S_AXI_HP1_ARQOS(S_AXI_HP1_ARQOS),
.S_AXI_HP1_AWCACHE(S_AXI_HP1_AWCACHE),
.S_AXI_HP1_AWLEN(S_AXI_HP1_AWLEN),
.S_AXI_HP1_AWQOS(S_AXI_HP1_AWQOS),
.S_AXI_HP1_ARID(S_AXI_HP1_ARID),
.S_AXI_HP1_AWID(S_AXI_HP1_AWID),
.S_AXI_HP1_WID(S_AXI_HP1_WID),
.S_AXI_HP1_WDATA(S_AXI_HP1_WDATA),
.S_AXI_HP1_WSTRB(S_AXI_HP1_WSTRB),
.S_AXI_HP2_ARREADY(),
.S_AXI_HP2_AWREADY(),
.S_AXI_HP2_BVALID(),
.S_AXI_HP2_RLAST(),
.S_AXI_HP2_RVALID(),
.S_AXI_HP2_WREADY(),
.S_AXI_HP2_BRESP(),
.S_AXI_HP2_RRESP(),
.S_AXI_HP2_BID(),
.S_AXI_HP2_RID(),
.S_AXI_HP2_RDATA(),
.S_AXI_HP2_ACLK(1'B0),
.S_AXI_HP2_ARVALID(1'B0),
.S_AXI_HP2_AWVALID(1'B0),
.S_AXI_HP2_BREADY(1'B0),
.S_AXI_HP2_RREADY(1'B0),
.S_AXI_HP2_WLAST(1'B0),
.S_AXI_HP2_WVALID(1'B0),
.S_AXI_HP2_ARBURST(2'B0),
.S_AXI_HP2_ARLOCK(2'B0),
.S_AXI_HP2_ARSIZE(3'B0),
.S_AXI_HP2_AWBURST(2'B0),
.S_AXI_HP2_AWLOCK(2'B0),
.S_AXI_HP2_AWSIZE(3'B0),
.S_AXI_HP2_ARPROT(3'B0),
.S_AXI_HP2_AWPROT(3'B0),
.S_AXI_HP2_ARADDR(32'B0),
.S_AXI_HP2_AWADDR(32'B0),
.S_AXI_HP2_ARCACHE(4'B0),
.S_AXI_HP2_ARLEN(4'B0),
.S_AXI_HP2_ARQOS(4'B0),
.S_AXI_HP2_AWCACHE(4'B0),
.S_AXI_HP2_AWLEN(4'B0),
.S_AXI_HP2_AWQOS(4'B0),
.S_AXI_HP2_ARID(6'B0),
.S_AXI_HP2_AWID(6'B0),
.S_AXI_HP2_WID(6'B0),
.S_AXI_HP2_WDATA(64'B0),
.S_AXI_HP2_WSTRB(8'B0),
.S_AXI_HP3_ARREADY(),
.S_AXI_HP3_AWREADY(),
.S_AXI_HP3_BVALID(),
.S_AXI_HP3_RLAST(),
.S_AXI_HP3_RVALID(),
.S_AXI_HP3_WREADY(),
.S_AXI_HP3_BRESP(),
.S_AXI_HP3_RRESP(),
.S_AXI_HP3_BID(),
.S_AXI_HP3_RID(),
.S_AXI_HP3_RDATA(),
.S_AXI_HP3_ACLK(1'B0),
.S_AXI_HP3_ARVALID(1'B0),
.S_AXI_HP3_AWVALID(1'B0),
.S_AXI_HP3_BREADY(1'B0),
.S_AXI_HP3_RREADY(1'B0),
.S_AXI_HP3_WLAST(1'B0),
.S_AXI_HP3_WVALID(1'B0),
.S_AXI_HP3_ARBURST(2'B0),
.S_AXI_HP3_ARLOCK(2'B0),
.S_AXI_HP3_ARSIZE(3'B0),
.S_AXI_HP3_AWBURST(2'B0),
.S_AXI_HP3_AWLOCK(2'B0),
.S_AXI_HP3_AWSIZE(3'B0),
.S_AXI_HP3_ARPROT(3'B0),
.S_AXI_HP3_AWPROT(3'B0),
.S_AXI_HP3_ARADDR(32'B0),
.S_AXI_HP3_AWADDR(32'B0),
.S_AXI_HP3_ARCACHE(4'B0),
.S_AXI_HP3_ARLEN(4'B0),
.S_AXI_HP3_ARQOS(4'B0),
.S_AXI_HP3_AWCACHE(4'B0),
.S_AXI_HP3_AWLEN(4'B0),
.S_AXI_HP3_AWQOS(4'B0),
.S_AXI_HP3_ARID(6'B0),
.S_AXI_HP3_AWID(6'B0),
.S_AXI_HP3_WID(6'B0),
.S_AXI_HP3_WDATA(64'B0),
.S_AXI_HP3_WSTRB(8'B0),
.FCLK_CLK0(FCLK_CLK0),
.FCLK_CLK1(),
.FCLK_CLK2(),
.FCLK_CLK3(FCLK_CLK3),
.FCLK_RESET0_N(FCLK_RESET0_N),
.FCLK_RESET1_N(),
.FCLK_RESET2_N(),
.FCLK_RESET3_N(),
.IRQ_F2P(16'B0),
.PS_SRSTB(PS_SRSTB),
.PS_CLK(PS_CLK),
.PS_PORB(PS_PORB)
);
endmodule
|
module pcie_recv_fifo (
clk,
srst,
din,
wr_en,
rd_en,
dout,
full,
empty
);
input wire clk;
input wire srst;
(* X_INTERFACE_INFO = "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE WR_DATA" *)
input wire [255 : 0] din;
(* X_INTERFACE_INFO = "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE WR_EN" *)
input wire wr_en;
(* X_INTERFACE_INFO = "xilinx.com:interface:fifo_read:1.0 FIFO_READ RD_EN" *)
input wire rd_en;
(* X_INTERFACE_INFO = "xilinx.com:interface:fifo_read:1.0 FIFO_READ RD_DATA" *)
output wire [255 : 0] dout;
(* X_INTERFACE_INFO = "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE FULL" *)
output wire full;
(* X_INTERFACE_INFO = "xilinx.com:interface:fifo_read:1.0 FIFO_READ EMPTY" *)
output wire empty;
fifo_generator_v12_0 #(
.C_COMMON_CLOCK(1),
.C_COUNT_TYPE(0),
.C_DATA_COUNT_WIDTH(8),
.C_DEFAULT_VALUE("BlankString"),
.C_DIN_WIDTH(256),
.C_DOUT_RST_VAL("0"),
.C_DOUT_WIDTH(256),
.C_ENABLE_RLOCS(0),
.C_FAMILY("virtex7"),
.C_FULL_FLAGS_RST_VAL(0),
.C_HAS_ALMOST_EMPTY(0),
.C_HAS_ALMOST_FULL(0),
.C_HAS_BACKUP(0),
.C_HAS_DATA_COUNT(0),
.C_HAS_INT_CLK(0),
.C_HAS_MEMINIT_FILE(0),
.C_HAS_OVERFLOW(0),
.C_HAS_RD_DATA_COUNT(0),
.C_HAS_RD_RST(0),
.C_HAS_RST(0),
.C_HAS_SRST(1),
.C_HAS_UNDERFLOW(0),
.C_HAS_VALID(0),
.C_HAS_WR_ACK(0),
.C_HAS_WR_DATA_COUNT(0),
.C_HAS_WR_RST(0),
.C_IMPLEMENTATION_TYPE(0),
.C_INIT_WR_PNTR_VAL(0),
.C_MEMORY_TYPE(1),
.C_MIF_FILE_NAME("BlankString"),
.C_OPTIMIZATION_MODE(0),
.C_OVERFLOW_LOW(0),
.C_PRELOAD_LATENCY(0),
.C_PRELOAD_REGS(1),
.C_PRIM_FIFO_TYPE("512x72"),
.C_PROG_EMPTY_THRESH_ASSERT_VAL(4),
.C_PROG_EMPTY_THRESH_NEGATE_VAL(5),
.C_PROG_EMPTY_TYPE(0),
.C_PROG_FULL_THRESH_ASSERT_VAL(127),
.C_PROG_FULL_THRESH_NEGATE_VAL(126),
.C_PROG_FULL_TYPE(0),
.C_RD_DATA_COUNT_WIDTH(8),
.C_RD_DEPTH(128),
.C_RD_FREQ(1),
.C_RD_PNTR_WIDTH(7),
.C_UNDERFLOW_LOW(0),
.C_USE_DOUT_RST(1),
.C_USE_ECC(0),
.C_USE_EMBEDDED_REG(0),
.C_USE_PIPELINE_REG(0),
.C_POWER_SAVING_MODE(0),
.C_USE_FIFO16_FLAGS(0),
.C_USE_FWFT_DATA_COUNT(1),
.C_VALID_LOW(0),
.C_WR_ACK_LOW(0),
.C_WR_DATA_COUNT_WIDTH(8),
.C_WR_DEPTH(128),
.C_WR_FREQ(1),
.C_WR_PNTR_WIDTH(7),
.C_WR_RESPONSE_LATENCY(1),
.C_MSGON_VAL(1),
.C_ENABLE_RST_SYNC(1),
.C_ERROR_INJECTION_TYPE(0),
.C_SYNCHRONIZER_STAGE(2),
.C_INTERFACE_TYPE(0),
.C_AXI_TYPE(1),
.C_HAS_AXI_WR_CHANNEL(1),
.C_HAS_AXI_RD_CHANNEL(1),
.C_HAS_SLAVE_CE(0),
.C_HAS_MASTER_CE(0),
.C_ADD_NGC_CONSTRAINT(0),
.C_USE_COMMON_OVERFLOW(0),
.C_USE_COMMON_UNDERFLOW(0),
.C_USE_DEFAULT_SETTINGS(0),
.C_AXI_ID_WIDTH(1),
.C_AXI_ADDR_WIDTH(32),
.C_AXI_DATA_WIDTH(64),
.C_AXI_LEN_WIDTH(8),
.C_AXI_LOCK_WIDTH(1),
.C_HAS_AXI_ID(0),
.C_HAS_AXI_AWUSER(0),
.C_HAS_AXI_WUSER(0),
.C_HAS_AXI_BUSER(0),
.C_HAS_AXI_ARUSER(0),
.C_HAS_AXI_RUSER(0),
.C_AXI_ARUSER_WIDTH(1),
.C_AXI_AWUSER_WIDTH(1),
.C_AXI_WUSER_WIDTH(1),
.C_AXI_BUSER_WIDTH(1),
.C_AXI_RUSER_WIDTH(1),
.C_HAS_AXIS_TDATA(1),
.C_HAS_AXIS_TID(0),
.C_HAS_AXIS_TDEST(0),
.C_HAS_AXIS_TUSER(1),
.C_HAS_AXIS_TREADY(1),
.C_HAS_AXIS_TLAST(0),
.C_HAS_AXIS_TSTRB(0),
.C_HAS_AXIS_TKEEP(0),
.C_AXIS_TDATA_WIDTH(8),
.C_AXIS_TID_WIDTH(1),
.C_AXIS_TDEST_WIDTH(1),
.C_AXIS_TUSER_WIDTH(4),
.C_AXIS_TSTRB_WIDTH(1),
.C_AXIS_TKEEP_WIDTH(1),
.C_WACH_TYPE(0),
.C_WDCH_TYPE(0),
.C_WRCH_TYPE(0),
.C_RACH_TYPE(0),
.C_RDCH_TYPE(0),
.C_AXIS_TYPE(0),
.C_IMPLEMENTATION_TYPE_WACH(1),
.C_IMPLEMENTATION_TYPE_WDCH(1),
.C_IMPLEMENTATION_TYPE_WRCH(1),
.C_IMPLEMENTATION_TYPE_RACH(1),
.C_IMPLEMENTATION_TYPE_RDCH(1),
.C_IMPLEMENTATION_TYPE_AXIS(1),
.C_APPLICATION_TYPE_WACH(0),
.C_APPLICATION_TYPE_WDCH(0),
.C_APPLICATION_TYPE_WRCH(0),
.C_APPLICATION_TYPE_RACH(0),
.C_APPLICATION_TYPE_RDCH(0),
.C_APPLICATION_TYPE_AXIS(0),
.C_PRIM_FIFO_TYPE_WACH("512x36"),
.C_PRIM_FIFO_TYPE_WDCH("1kx36"),
.C_PRIM_FIFO_TYPE_WRCH("512x36"),
.C_PRIM_FIFO_TYPE_RACH("512x36"),
.C_PRIM_FIFO_TYPE_RDCH("1kx36"),
.C_PRIM_FIFO_TYPE_AXIS("1kx18"),
.C_USE_ECC_WACH(0),
.C_USE_ECC_WDCH(0),
.C_USE_ECC_WRCH(0),
.C_USE_ECC_RACH(0),
.C_USE_ECC_RDCH(0),
.C_USE_ECC_AXIS(0),
.C_ERROR_INJECTION_TYPE_WACH(0),
.C_ERROR_INJECTION_TYPE_WDCH(0),
.C_ERROR_INJECTION_TYPE_WRCH(0),
.C_ERROR_INJECTION_TYPE_RACH(0),
.C_ERROR_INJECTION_TYPE_RDCH(0),
.C_ERROR_INJECTION_TYPE_AXIS(0),
.C_DIN_WIDTH_WACH(32),
.C_DIN_WIDTH_WDCH(64),
.C_DIN_WIDTH_WRCH(2),
.C_DIN_WIDTH_RACH(32),
.C_DIN_WIDTH_RDCH(64),
.C_DIN_WIDTH_AXIS(1),
.C_WR_DEPTH_WACH(16),
.C_WR_DEPTH_WDCH(1024),
.C_WR_DEPTH_WRCH(16),
.C_WR_DEPTH_RACH(16),
.C_WR_DEPTH_RDCH(1024),
.C_WR_DEPTH_AXIS(1024),
.C_WR_PNTR_WIDTH_WACH(4),
.C_WR_PNTR_WIDTH_WDCH(10),
.C_WR_PNTR_WIDTH_WRCH(4),
.C_WR_PNTR_WIDTH_RACH(4),
.C_WR_PNTR_WIDTH_RDCH(10),
.C_WR_PNTR_WIDTH_AXIS(10),
.C_HAS_DATA_COUNTS_WACH(0),
.C_HAS_DATA_COUNTS_WDCH(0),
.C_HAS_DATA_COUNTS_WRCH(0),
.C_HAS_DATA_COUNTS_RACH(0),
.C_HAS_DATA_COUNTS_RDCH(0),
.C_HAS_DATA_COUNTS_AXIS(0),
.C_HAS_PROG_FLAGS_WACH(0),
.C_HAS_PROG_FLAGS_WDCH(0),
.C_HAS_PROG_FLAGS_WRCH(0),
.C_HAS_PROG_FLAGS_RACH(0),
.C_HAS_PROG_FLAGS_RDCH(0),
.C_HAS_PROG_FLAGS_AXIS(0),
.C_PROG_FULL_TYPE_WACH(0),
.C_PROG_FULL_TYPE_WDCH(0),
.C_PROG_FULL_TYPE_WRCH(0),
.C_PROG_FULL_TYPE_RACH(0),
.C_PROG_FULL_TYPE_RDCH(0),
.C_PROG_FULL_TYPE_AXIS(0),
.C_PROG_FULL_THRESH_ASSERT_VAL_WACH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_WDCH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_WRCH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_RACH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_RDCH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_AXIS(1023),
.C_PROG_EMPTY_TYPE_WACH(0),
.C_PROG_EMPTY_TYPE_WDCH(0),
.C_PROG_EMPTY_TYPE_WRCH(0),
.C_PROG_EMPTY_TYPE_RACH(0),
.C_PROG_EMPTY_TYPE_RDCH(0),
.C_PROG_EMPTY_TYPE_AXIS(0),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS(1022),
.C_REG_SLICE_MODE_WACH(0),
.C_REG_SLICE_MODE_WDCH(0),
.C_REG_SLICE_MODE_WRCH(0),
.C_REG_SLICE_MODE_RACH(0),
.C_REG_SLICE_MODE_RDCH(0),
.C_REG_SLICE_MODE_AXIS(0)
) inst (
.backup(1'D0),
.backup_marker(1'D0),
.clk(clk),
.rst(1'D0),
.srst(srst),
.wr_clk(1'D0),
.wr_rst(1'D0),
.rd_clk(1'D0),
.rd_rst(1'D0),
.din(din),
.wr_en(wr_en),
.rd_en(rd_en),
.prog_empty_thresh(7'B0),
.prog_empty_thresh_assert(7'B0),
.prog_empty_thresh_negate(7'B0),
.prog_full_thresh(7'B0),
.prog_full_thresh_assert(7'B0),
.prog_full_thresh_negate(7'B0),
.int_clk(1'D0),
.injectdbiterr(1'D0),
.injectsbiterr(1'D0),
.sleep(1'D0),
.dout(dout),
.full(full),
.almost_full(),
.wr_ack(),
.overflow(),
.empty(empty),
.almost_empty(),
.valid(),
.underflow(),
.data_count(),
.rd_data_count(),
.wr_data_count(),
.prog_full(),
.prog_empty(),
.sbiterr(),
.dbiterr(),
.wr_rst_busy(),
.rd_rst_busy(),
.m_aclk(1'D0),
.s_aclk(1'D0),
.s_aresetn(1'D0),
.m_aclk_en(1'D0),
.s_aclk_en(1'D0),
.s_axi_awid(1'B0),
.s_axi_awaddr(32'B0),
.s_axi_awlen(8'B0),
.s_axi_awsize(3'B0),
.s_axi_awburst(2'B0),
.s_axi_awlock(1'B0),
.s_axi_awcache(4'B0),
.s_axi_awprot(3'B0),
.s_axi_awqos(4'B0),
.s_axi_awregion(4'B0),
.s_axi_awuser(1'B0),
.s_axi_awvalid(1'D0),
.s_axi_awready(),
.s_axi_wid(1'B0),
.s_axi_wdata(64'B0),
.s_axi_wstrb(8'B0),
.s_axi_wlast(1'D0),
.s_axi_wuser(1'B0),
.s_axi_wvalid(1'D0),
.s_axi_wready(),
.s_axi_bid(),
.s_axi_bresp(),
.s_axi_buser(),
.s_axi_bvalid(),
.s_axi_bready(1'D0),
.m_axi_awid(),
.m_axi_awaddr(),
.m_axi_awlen(),
.m_axi_awsize(),
.m_axi_awburst(),
.m_axi_awlock(),
.m_axi_awcache(),
.m_axi_awprot(),
.m_axi_awqos(),
.m_axi_awregion(),
.m_axi_awuser(),
.m_axi_awvalid(),
.m_axi_awready(1'D0),
.m_axi_wid(),
.m_axi_wdata(),
.m_axi_wstrb(),
.m_axi_wlast(),
.m_axi_wuser(),
.m_axi_wvalid(),
.m_axi_wready(1'D0),
.m_axi_bid(1'B0),
.m_axi_bresp(2'B0),
.m_axi_buser(1'B0),
.m_axi_bvalid(1'D0),
.m_axi_bready(),
.s_axi_arid(1'B0),
.s_axi_araddr(32'B0),
.s_axi_arlen(8'B0),
.s_axi_arsize(3'B0),
.s_axi_arburst(2'B0),
.s_axi_arlock(1'B0),
.s_axi_arcache(4'B0),
.s_axi_arprot(3'B0),
.s_axi_arqos(4'B0),
.s_axi_arregion(4'B0),
.s_axi_aruser(1'B0),
.s_axi_arvalid(1'D0),
.s_axi_arready(),
.s_axi_rid(),
.s_axi_rdata(),
.s_axi_rresp(),
.s_axi_rlast(),
.s_axi_ruser(),
.s_axi_rvalid(),
.s_axi_rready(1'D0),
.m_axi_arid(),
.m_axi_araddr(),
.m_axi_arlen(),
.m_axi_arsize(),
.m_axi_arburst(),
.m_axi_arlock(),
.m_axi_arcache(),
.m_axi_arprot(),
.m_axi_arqos(),
.m_axi_arregion(),
.m_axi_aruser(),
.m_axi_arvalid(),
.m_axi_arready(1'D0),
.m_axi_rid(1'B0),
.m_axi_rdata(64'B0),
.m_axi_rresp(2'B0),
.m_axi_rlast(1'D0),
.m_axi_ruser(1'B0),
.m_axi_rvalid(1'D0),
.m_axi_rready(),
.s_axis_tvalid(1'D0),
.s_axis_tready(),
.s_axis_tdata(8'B0),
.s_axis_tstrb(1'B0),
.s_axis_tkeep(1'B0),
.s_axis_tlast(1'D0),
.s_axis_tid(1'B0),
.s_axis_tdest(1'B0),
.s_axis_tuser(4'B0),
.m_axis_tvalid(),
.m_axis_tready(1'D0),
.m_axis_tdata(),
.m_axis_tstrb(),
.m_axis_tkeep(),
.m_axis_tlast(),
.m_axis_tid(),
.m_axis_tdest(),
.m_axis_tuser(),
.axi_aw_injectsbiterr(1'D0),
.axi_aw_injectdbiterr(1'D0),
.axi_aw_prog_full_thresh(4'B0),
.axi_aw_prog_empty_thresh(4'B0),
.axi_aw_data_count(),
.axi_aw_wr_data_count(),
.axi_aw_rd_data_count(),
.axi_aw_sbiterr(),
.axi_aw_dbiterr(),
.axi_aw_overflow(),
.axi_aw_underflow(),
.axi_aw_prog_full(),
.axi_aw_prog_empty(),
.axi_w_injectsbiterr(1'D0),
.axi_w_injectdbiterr(1'D0),
.axi_w_prog_full_thresh(10'B0),
.axi_w_prog_empty_thresh(10'B0),
.axi_w_data_count(),
.axi_w_wr_data_count(),
.axi_w_rd_data_count(),
.axi_w_sbiterr(),
.axi_w_dbiterr(),
.axi_w_overflow(),
.axi_w_underflow(),
.axi_w_prog_full(),
.axi_w_prog_empty(),
.axi_b_injectsbiterr(1'D0),
.axi_b_injectdbiterr(1'D0),
.axi_b_prog_full_thresh(4'B0),
.axi_b_prog_empty_thresh(4'B0),
.axi_b_data_count(),
.axi_b_wr_data_count(),
.axi_b_rd_data_count(),
.axi_b_sbiterr(),
.axi_b_dbiterr(),
.axi_b_overflow(),
.axi_b_underflow(),
.axi_b_prog_full(),
.axi_b_prog_empty(),
.axi_ar_injectsbiterr(1'D0),
.axi_ar_injectdbiterr(1'D0),
.axi_ar_prog_full_thresh(4'B0),
.axi_ar_prog_empty_thresh(4'B0),
.axi_ar_data_count(),
.axi_ar_wr_data_count(),
.axi_ar_rd_data_count(),
.axi_ar_sbiterr(),
.axi_ar_dbiterr(),
.axi_ar_overflow(),
.axi_ar_underflow(),
.axi_ar_prog_full(),
.axi_ar_prog_empty(),
.axi_r_injectsbiterr(1'D0),
.axi_r_injectdbiterr(1'D0),
.axi_r_prog_full_thresh(10'B0),
.axi_r_prog_empty_thresh(10'B0),
.axi_r_data_count(),
.axi_r_wr_data_count(),
.axi_r_rd_data_count(),
.axi_r_sbiterr(),
.axi_r_dbiterr(),
.axi_r_overflow(),
.axi_r_underflow(),
.axi_r_prog_full(),
.axi_r_prog_empty(),
.axis_injectsbiterr(1'D0),
.axis_injectdbiterr(1'D0),
.axis_prog_full_thresh(10'B0),
.axis_prog_empty_thresh(10'B0),
.axis_data_count(),
.axis_wr_data_count(),
.axis_rd_data_count(),
.axis_sbiterr(),
.axis_dbiterr(),
.axis_overflow(),
.axis_underflow(),
.axis_prog_full(),
.axis_prog_empty()
);
endmodule
|
module contadorprueba (
input [7:0] cantidad,
input entrada,
input ENABLE,
input clk,
input reset,
output [3:0] an,
output [6:0] seg,
output pulse
);
wire [7:0] count;
wire [3:0] centenas;
wire [3:0] decenas;
wire [3:0] unidades;
wire [1:0] mostrar;
wire [3:0] digito;
cantidadecho cantidadecho0 (
.cantidad ( cantidad ),
.entrada ( entrada ),
.CLKOUT ( CLKOUT ),
.reset ( reset ),
.ECHO ( ECHO )
);
contador contador0 (
.count ( count ),
.pulse ( pulse ),
.calculate ( calculate ),
.ECHO ( ECHO ),
.ENABLE ( ENABLE ),
.CLKOUT ( CLKOUT ),
.reset ( reset )
);
divisorfrec divisorfrec0 (
.clk ( clk ),
.CLKOUT ( CLKOUT )
);
anteconmutador anteconmutador0 (
.clk ( clk ),
.count ( count ),
.calculate ( calculate ),
.centenas ( centenas ),
.decenas ( decenas ),
.unidades ( unidades ),
.C ( C ),
.De ( De ),
.U ( U )
);
conmutacion conmutacion0 (
.centenas ( centenas ),
.decenas ( decenas ),
.unidades ( unidades ),
.C ( C ),
.De ( De ),
.U ( U ),
.CLKOUTseg ( CLKOUTseg ),
.mostrar ( mostrar ),
.digito ( digito )
);
display display0 (
.mostrar ( mostrar ),
.digito ( digito ),
.an ( an ),
.seg ( seg )
);
divisorfrecdisp divisorfrecdisp0 (
.clk ( clk ),
.CLKOUTseg ( CLKOUTseg )
);
endmodule
|
module Altera_UP_PS2_Data_In (
// Inputs
clk,
reset,
wait_for_incoming_data,
start_receiving_data,
ps2_clk_posedge,
ps2_clk_negedge,
ps2_data,
// Bidirectionals
// Outputs
received_data,
received_data_en // If 1 - new data has been received
);
/*****************************************************************************
* Parameter Declarations *
*****************************************************************************/
/*****************************************************************************
* Port Declarations *
*****************************************************************************/
// Inputs
input clk;
input reset;
input wait_for_incoming_data;
input start_receiving_data;
input ps2_clk_posedge;
input ps2_clk_negedge;
input ps2_data;
// Bidirectionals
// Outputs
output reg [7:0] received_data;
output reg received_data_en;
/*****************************************************************************
* Constant Declarations *
*****************************************************************************/
// states
localparam PS2_STATE_0_IDLE = 3'h0,
PS2_STATE_1_WAIT_FOR_DATA = 3'h1,
PS2_STATE_2_DATA_IN = 3'h2,
PS2_STATE_3_PARITY_IN = 3'h3,
PS2_STATE_4_STOP_IN = 3'h4;
/*****************************************************************************
* Internal wires and registers Declarations *
*****************************************************************************/
// Internal Wires
reg [3:0] data_count;
reg [7:0] data_shift_reg;
// State Machine Registers
reg [2:0] ns_ps2_receiver;
reg [2:0] s_ps2_receiver;
/*****************************************************************************
* Finite State Machine(s) *
*****************************************************************************/
always @(posedge clk)
begin
if (reset == 1'b1)
s_ps2_receiver <= PS2_STATE_0_IDLE;
else
s_ps2_receiver <= ns_ps2_receiver;
end
always @(*)
begin
// Defaults
ns_ps2_receiver = PS2_STATE_0_IDLE;
case (s_ps2_receiver)
PS2_STATE_0_IDLE:
begin
if ((wait_for_incoming_data == 1'b1) &&
(received_data_en == 1'b0))
ns_ps2_receiver = PS2_STATE_1_WAIT_FOR_DATA;
else if ((start_receiving_data == 1'b1) &&
(received_data_en == 1'b0))
ns_ps2_receiver = PS2_STATE_2_DATA_IN;
else
ns_ps2_receiver = PS2_STATE_0_IDLE;
end
PS2_STATE_1_WAIT_FOR_DATA:
begin
if ((ps2_data == 1'b0) && (ps2_clk_posedge == 1'b1))
ns_ps2_receiver = PS2_STATE_2_DATA_IN;
else if (wait_for_incoming_data == 1'b0)
ns_ps2_receiver = PS2_STATE_0_IDLE;
else
ns_ps2_receiver = PS2_STATE_1_WAIT_FOR_DATA;
end
PS2_STATE_2_DATA_IN:
begin
if ((data_count == 3'h7) && (ps2_clk_posedge == 1'b1))
ns_ps2_receiver = PS2_STATE_3_PARITY_IN;
else
ns_ps2_receiver = PS2_STATE_2_DATA_IN;
end
PS2_STATE_3_PARITY_IN:
begin
if (ps2_clk_posedge == 1'b1)
ns_ps2_receiver = PS2_STATE_4_STOP_IN;
else
ns_ps2_receiver = PS2_STATE_3_PARITY_IN;
end
PS2_STATE_4_STOP_IN:
begin
if (ps2_clk_posedge == 1'b1)
ns_ps2_receiver = PS2_STATE_0_IDLE;
else
ns_ps2_receiver = PS2_STATE_4_STOP_IN;
end
default:
begin
ns_ps2_receiver = PS2_STATE_0_IDLE;
end
endcase
end
/*****************************************************************************
* Sequential logic *
*****************************************************************************/
always @(posedge clk)
begin
if (reset == 1'b1)
data_count <= 3'h0;
else if ((s_ps2_receiver == PS2_STATE_2_DATA_IN) &&
(ps2_clk_posedge == 1'b1))
data_count <= data_count + 3'h1;
else if (s_ps2_receiver != PS2_STATE_2_DATA_IN)
data_count <= 3'h0;
end
always @(posedge clk)
begin
if (reset == 1'b1)
data_shift_reg <= 8'h00;
else if ((s_ps2_receiver == PS2_STATE_2_DATA_IN) &&
(ps2_clk_posedge == 1'b1))
data_shift_reg <= {ps2_data, data_shift_reg[7:1]};
end
always @(posedge clk)
begin
if (reset == 1'b1)
received_data <= 8'h00;
else if (s_ps2_receiver == PS2_STATE_4_STOP_IN)
received_data <= data_shift_reg;
end
always @(posedge clk)
begin
if (reset == 1'b1)
received_data_en <= 1'b0;
else if ((s_ps2_receiver == PS2_STATE_4_STOP_IN) &&
(ps2_clk_posedge == 1'b1))
received_data_en <= 1'b1;
else
received_data_en <= 1'b0;
end
/*****************************************************************************
* Combinational logic *
*****************************************************************************/
/*****************************************************************************
* Internal Modules *
*****************************************************************************/
endmodule
|
module wb_ram #
(
parameter DATA_WIDTH = 32, // width of data bus in bits (8, 16, 32, or 64)
parameter ADDR_WIDTH = 32, // width of address bus in bits
parameter SELECT_WIDTH = (DATA_WIDTH/8) // width of word select bus (1, 2, 4, or 8)
)
(
input wire clk,
input wire [ADDR_WIDTH-1:0] adr_i, // ADR_I() address
input wire [DATA_WIDTH-1:0] dat_i, // DAT_I() data in
output wire [DATA_WIDTH-1:0] dat_o, // DAT_O() data out
input wire we_i, // WE_I write enable input
input wire [SELECT_WIDTH-1:0] sel_i, // SEL_I() select input
input wire stb_i, // STB_I strobe input
output wire ack_o, // ACK_O acknowledge output
input wire cyc_i // CYC_I cycle input
);
// for interfaces that are more than one word wide, disable address lines
parameter VALID_ADDR_WIDTH = ADDR_WIDTH - $clog2(SELECT_WIDTH);
// width of data port in words (1, 2, 4, or 8)
parameter WORD_WIDTH = SELECT_WIDTH;
// size of words (8, 16, 32, or 64 bits)
parameter WORD_SIZE = DATA_WIDTH/WORD_WIDTH;
reg [DATA_WIDTH-1:0] dat_o_reg = {DATA_WIDTH{1'b0}};
reg ack_o_reg = 1'b0;
// (* RAM_STYLE="BLOCK" *)
reg [DATA_WIDTH-1:0] mem[(2**VALID_ADDR_WIDTH)-1:0];
wire [VALID_ADDR_WIDTH-1:0] adr_i_valid = adr_i >> (ADDR_WIDTH - VALID_ADDR_WIDTH);
assign dat_o = dat_o_reg;
assign ack_o = ack_o_reg;
integer i;
initial begin
for (i = 0; i < 2**VALID_ADDR_WIDTH; i = i + 1) begin
mem[i] = 0;
end
end
always @(posedge clk) begin
ack_o_reg <= 1'b0;
for (i = 0; i < WORD_WIDTH; i = i + 1) begin
if (cyc_i & stb_i & ~ack_o) begin
if (we_i & sel_i[i]) begin
mem[adr_i_valid][WORD_SIZE*i +: WORD_SIZE] <= dat_i[WORD_SIZE*i +: WORD_SIZE];
end
dat_o_reg[WORD_SIZE*i +: WORD_SIZE] <= mem[adr_i_valid][WORD_SIZE*i +: WORD_SIZE];
ack_o_reg <= 1'b1;
end
end
end
endmodule
|
module mult_descale_pipeline(
input [31:0] a_multiplicand,
input [31:0] b_multiplier,
input [31:0] z_scale,
input [7:0] InsTagScaleOut,
input ScaleValid,
input NatLogFlagScaleOut,
input reset,
input clock,
output [31:0] FinalProduct,
output done,
output [7:0] InsTagDescale,
output [31:0] z_out
);
wire idle_Special, idle_Multiply, idle_NormaliseProd;
wire [32:0] aout_Special,bout_Special;
wire [32:0] zout_Special,zout_Multiply,zout_NormaliseProd;
wire [49:0] productout_Multiply, productout_NormaliseProd;
wire [7:0] InsTagSpecial,InsTagMultiply,InsTagNormaliseProd;
wire ScaleValidSpecial,ScaleValidMultiply,ScaleValidNormaliseProd;
wire [31:0] z_Special,z_Multiply,z_NormaliseProd;
SpecialMultDescale Mult1 (
.ain_Special(a_multiplicand),
.bin_Special(b_multiplier),
.InsTagScaleOut(InsTagScaleOut),
.ScaleValid(ScaleValid),
.NatLogFlagScaleOut(NatLogFlagScaleOut),
.z_scale(z_scale),
.reset(reset),
.clock(clock),
.idle_Special(idle_Special),
.aout_Special(aout_Special),
.bout_Special(bout_Special),
.zout_Special(zout_Special),
.InsTagSpecial(InsTagSpecial),
.ScaleValidSpecial(ScaleValidSpecial),
.z_Special(z_Special)
);
MultiplyMultDescale Mult2 (
.aout_Special(aout_Special),
.bout_Special(bout_Special),
.zout_Special(zout_Special),
.idle_Special(idle_Special),
.InsTagSpecial(InsTagSpecial),
.ScaleValidSpecial(ScaleValidSpecial),
.z_Special(z_Special),
.clock(clock),
.idle_Multiply(idle_Multiply),
.zout_Multiply(zout_Multiply),
.productout_Multiply(productout_Multiply),
.InsTagMultiply(InsTagMultiply),
.ScaleValidMultiply(ScaleValidMultiply),
.z_Multiply(z_Multiply)
);
NormaliseProdMultDescale Mult3 (
.zout_Multiply(zout_Multiply),
.productout_Multiply(productout_Multiply),
.InsTagMultiply(InsTagMultiply),
.ScaleValidMultiply(ScaleValidMultiply),
.z_Multiply(z_Multiply),
.clock(clock),
.idle_Multiply(idle_Multiply),
.idle_NormaliseProd(idle_NormaliseProd),
.zout_NormaliseProd(zout_NormaliseProd),
.productout_NormaliseProd(productout_NormaliseProd),
.InsTagNormaliseProd(InsTagNormaliseProd),
.ScaleValidNormaliseProd(ScaleValidNormaliseProd),
.z_NormaliseProd(z_NormaliseProd)
);
Pack_z_descale Mult4 (
.idle_NormaliseProd(idle_NormaliseProd),
.zout_NormaliseProd(zout_NormaliseProd),
.productout_NormaliseProd(productout_NormaliseProd),
.InsTagNormaliseProd(InsTagNormaliseProd),
.ScaleValidNormaliseProd(ScaleValidNormaliseProd),
.z_NormaliseProd(z_NormaliseProd),
.reset(reset),
.clock(clock),
.done(done),
.FinalProduct(FinalProduct),
.InsTagPack(InsTagDescale),
.z_Descale(z_out)
);
endmodule
|
module be tested as is.
reset = 0;
end
endmodule
|
module axi_traffic_gen_v2_0_7_id_track
#(
parameter ID_WIDTH = 1
) (
input Clk ,
input rst_l ,
input [ID_WIDTH-1:0] in_push_id ,
input in_push ,
input [ID_WIDTH-1:0] in_search_id ,
input [3:0] in_clear_pos ,
input in_only_entry0,
output [3:0] out_push_pos ,
output [3:0] out_search_hit,
output [3:0] out_free
);
reg [ID_WIDTH:0] id_arr0_ff, id_arr1_ff, id_arr2_ff, id_arr3_ff;
reg [3:0] push_pos_ff, push_pos_2ff;
reg [3:0] in_clear_pos_ff;
wire [ID_WIDTH:0] push_id = { 1'b1, in_push_id[ID_WIDTH-1:0] };
wire [3:0] push_search = { (push_id[ID_WIDTH:0] == id_arr3_ff[ID_WIDTH:0]),
(push_id[ID_WIDTH:0] == id_arr2_ff[ID_WIDTH:0]),
(push_id[ID_WIDTH:0] == id_arr1_ff[ID_WIDTH:0]),
(push_id[ID_WIDTH:0] == id_arr0_ff[ID_WIDTH:0]) };
wire [3:0] free_pre = { ~id_arr3_ff[ID_WIDTH], ~id_arr2_ff[ID_WIDTH],
~id_arr1_ff[ID_WIDTH], ~id_arr0_ff[ID_WIDTH] };
wire [3:0] free = (in_only_entry0) ? { 3'b000, free_pre[0] } : free_pre[3:0];
wire [3:0] first_free = (free[0]) ? 4'h1 :
(free[1]) ? 4'h2 :
(free[2]) ? 4'h4 :
(free[3]) ? 4'h8 : 4'h0;
wire [3:0] push_pos = (in_push == 1'b0) ? 4'h0 :
(push_search[3:0] != 4'h0) ? push_search[3:0] :
first_free[3:0];
wire [ID_WIDTH:0] search_id = { 1'b1, in_search_id[ID_WIDTH-1:0] };
wire [3:0] search_pos = { (search_id[ID_WIDTH:0] == id_arr3_ff[ID_WIDTH:0]),
(search_id[ID_WIDTH:0] == id_arr2_ff[ID_WIDTH:0]),
(search_id[ID_WIDTH:0] == id_arr1_ff[ID_WIDTH:0]),
(search_id[ID_WIDTH:0] == id_arr0_ff[ID_WIDTH:0]) };
wire [3:0] do_clear = ~push_pos_ff[3:0] & ~push_pos_2ff[3:0] &
in_clear_pos_ff[3:0];
wire [ID_WIDTH:0] id_arr0 = (push_pos[0]) ? push_id[ID_WIDTH:0] :
{ (do_clear[0]) ? 1'b0:id_arr0_ff[ID_WIDTH], id_arr0_ff[ID_WIDTH-1:0] };
wire [ID_WIDTH:0] id_arr1 = (push_pos[1]) ? push_id[ID_WIDTH:0] :
{ (do_clear[1]) ? 1'b0:id_arr1_ff[ID_WIDTH], id_arr1_ff[ID_WIDTH-1:0] };
wire [ID_WIDTH:0] id_arr2 = (push_pos[2]) ? push_id[ID_WIDTH:0] :
{ (do_clear[2]) ? 1'b0:id_arr2_ff[ID_WIDTH], id_arr2_ff[ID_WIDTH-1:0] };
wire [ID_WIDTH:0] id_arr3 = (push_pos[3]) ? push_id[ID_WIDTH:0] :
{ (do_clear[3]) ? 1'b0:id_arr3_ff[ID_WIDTH], id_arr3_ff[ID_WIDTH-1:0] };
always @(posedge Clk) begin
id_arr0_ff[ID_WIDTH:0] <= (rst_l) ? id_arr0[ID_WIDTH:0] : 1'b0;
id_arr1_ff[ID_WIDTH:0] <= (rst_l) ? id_arr1[ID_WIDTH:0] : 1'b0;
id_arr2_ff[ID_WIDTH:0] <= (rst_l) ? id_arr2[ID_WIDTH:0] : 1'b0;
id_arr3_ff[ID_WIDTH:0] <= (rst_l) ? id_arr3[ID_WIDTH:0] : 1'b0;
push_pos_ff[3:0] <= (rst_l) ? push_pos[3:0] : 4'h0;
push_pos_2ff[3:0] <= (rst_l) ? push_pos_ff[3:0] : 4'h0;
in_clear_pos_ff[3:0] <= (rst_l) ? in_clear_pos[3:0] : 4'h0;
end
assign out_search_hit[3:0] = search_pos[3:0];
assign out_push_pos[3:0] = push_pos[3:0];
assign out_free[3:0] = free[3:0];
endmodule
|
module for actual values.
parameter BANK_WIDTH = 2,
parameter CKE_WIDTH = 1,
parameter CLK_WIDTH = 1,
parameter COL_WIDTH = 10,
parameter CS_BITS = 0,
parameter CS_NUM = 1,
parameter CS_WIDTH = 1,
parameter USE_DM_PORT = 1,
parameter DM_WIDTH = 9,
parameter DQ_WIDTH = 72,
parameter DQ_BITS = 7,
parameter DQ_PER_DQS = 8,
parameter DQS_BITS = 4,
parameter DQS_WIDTH = 9,
parameter HIGH_PERFORMANCE_MODE = "TRUE",
parameter IODELAY_GRP = "IODELAY_MIG",
parameter ODT_WIDTH = 1,
parameter ROW_WIDTH = 14,
parameter APPDATA_WIDTH = 144,
parameter ADDITIVE_LAT = 0,
parameter BURST_LEN = 4,
parameter BURST_TYPE = 0,
parameter CAS_LAT = 5,
parameter ECC_ENABLE = 0,
parameter MULTI_BANK_EN = 1,
parameter TWO_T_TIME_EN = 0,
parameter ODT_TYPE = 1,
parameter DDR_TYPE = 1,
parameter REDUCE_DRV = 0,
parameter REG_ENABLE = 1,
parameter TREFI_NS = 7800,
parameter TRAS = 40000,
parameter TRCD = 15000,
parameter TRFC = 105000,
parameter TRP = 15000,
parameter TRTP = 7500,
parameter TWR = 15000,
parameter TWTR = 10000,
parameter CLK_PERIOD = 3000,
parameter SIM_ONLY = 0,
parameter DEBUG_EN = 0,
parameter FPGA_SPEED_GRADE = 2
)
(
input clk0,
input usr_clk, // jb
input clk90,
input clkdiv0,
input rst0,
input rst90,
input rstdiv0,
input [2:0] app_af_cmd,
input [30:0] app_af_addr,
input app_af_wren,
input app_wdf_wren,
input [APPDATA_WIDTH-1:0] app_wdf_data,
input [(APPDATA_WIDTH/8)-1:0] app_wdf_mask_data,
output [1:0] rd_ecc_error,
output app_af_afull,
output app_wdf_afull,
output rd_data_valid,
output [APPDATA_WIDTH-1:0] rd_data_fifo_out,
output phy_init_done,
output [CLK_WIDTH-1:0] ddr_ck,
output [CLK_WIDTH-1:0] ddr_ck_n,
output [ROW_WIDTH-1:0] ddr_addr,
output [BANK_WIDTH-1:0] ddr_ba,
output ddr_ras_n,
output ddr_cas_n,
output ddr_we_n,
output [CS_WIDTH-1:0] ddr_cs_n,
output [CKE_WIDTH-1:0] ddr_cke,
output [ODT_WIDTH-1:0] ddr_odt,
output [DM_WIDTH-1:0] ddr_dm,
inout [DQS_WIDTH-1:0] ddr_dqs,
inout [DQS_WIDTH-1:0] ddr_dqs_n,
inout [DQ_WIDTH-1:0] ddr_dq,
// Debug signals (optional use)
input dbg_idel_up_all,
input dbg_idel_down_all,
input dbg_idel_up_dq,
input dbg_idel_down_dq,
input dbg_idel_up_dqs,
input dbg_idel_down_dqs,
input dbg_idel_up_gate,
input dbg_idel_down_gate,
input [DQ_BITS-1:0] dbg_sel_idel_dq,
input dbg_sel_all_idel_dq,
input [DQS_BITS:0] dbg_sel_idel_dqs,
input dbg_sel_all_idel_dqs,
input [DQS_BITS:0] dbg_sel_idel_gate,
input dbg_sel_all_idel_gate,
output [3:0] dbg_calib_done,
output [3:0] dbg_calib_err,
output [(6*DQ_WIDTH)-1:0] dbg_calib_dq_tap_cnt,
output [(6*DQS_WIDTH)-1:0] dbg_calib_dqs_tap_cnt,
output [(6*DQS_WIDTH)-1:0] dbg_calib_gate_tap_cnt,
output [DQS_WIDTH-1:0] dbg_calib_rd_data_sel,
output [(5*DQS_WIDTH)-1:0] dbg_calib_rden_dly,
output [(5*DQS_WIDTH)-1:0] dbg_calib_gate_dly
, input sp_refresh_disable
);
wire [30:0] af_addr;
wire [2:0] af_cmd;
wire af_empty;
wire [ROW_WIDTH-1:0] ctrl_addr;
wire ctrl_af_rden;
wire [BANK_WIDTH-1:0] ctrl_ba;
wire ctrl_cas_n;
wire [CS_NUM-1:0] ctrl_cs_n;
wire ctrl_ras_n;
wire ctrl_rden;
wire ctrl_ref_flag;
wire ctrl_we_n;
wire ctrl_wren;
wire [DQS_WIDTH-1:0] phy_calib_rden;
wire [DQS_WIDTH-1:0] phy_calib_rden_sel;
wire [DQ_WIDTH-1:0] rd_data_fall;
wire [DQ_WIDTH-1:0] rd_data_rise;
wire [(2*DQ_WIDTH)-1:0] wdf_data;
wire [((2*DQ_WIDTH)/8)-1:0] wdf_mask_data;
wire wdf_rden;
//***************************************************************************
ddr2_phy_top #
(
.BANK_WIDTH (BANK_WIDTH),
.CKE_WIDTH (CKE_WIDTH),
.CLK_WIDTH (CLK_WIDTH),
.COL_WIDTH (COL_WIDTH),
.CS_BITS (CS_BITS),
.CS_NUM (CS_NUM),
.CS_WIDTH (CS_WIDTH),
.USE_DM_PORT (USE_DM_PORT),
.DM_WIDTH (DM_WIDTH),
.DQ_WIDTH (DQ_WIDTH),
.DQ_BITS (DQ_BITS),
.DQ_PER_DQS (DQ_PER_DQS),
.DQS_BITS (DQS_BITS),
.DQS_WIDTH (DQS_WIDTH),
.HIGH_PERFORMANCE_MODE (HIGH_PERFORMANCE_MODE),
.IODELAY_GRP (IODELAY_GRP),
.ODT_WIDTH (ODT_WIDTH),
.ROW_WIDTH (ROW_WIDTH),
.TWO_T_TIME_EN (TWO_T_TIME_EN),
.ADDITIVE_LAT (ADDITIVE_LAT),
.BURST_LEN (BURST_LEN),
.BURST_TYPE (BURST_TYPE),
.CAS_LAT (CAS_LAT),
.ECC_ENABLE (ECC_ENABLE),
.ODT_TYPE (ODT_TYPE),
.DDR_TYPE (DDR_TYPE),
.REDUCE_DRV (REDUCE_DRV),
.REG_ENABLE (REG_ENABLE),
.TWR (TWR),
.CLK_PERIOD (CLK_PERIOD),
.SIM_ONLY (SIM_ONLY),
.DEBUG_EN (DEBUG_EN),
.FPGA_SPEED_GRADE (FPGA_SPEED_GRADE)
)
u_phy_top
(
.clk0 (clk0),
.clk90 (clk90),
.clkdiv0 (clkdiv0),
.rst0 (rst0),
.rst90 (rst90),
.rstdiv0 (rstdiv0),
.ctrl_wren (ctrl_wren),
.ctrl_addr (ctrl_addr),
.ctrl_ba (ctrl_ba),
.ctrl_ras_n (ctrl_ras_n),
.ctrl_cas_n (ctrl_cas_n),
.ctrl_we_n (ctrl_we_n),
.ctrl_cs_n (ctrl_cs_n),
.ctrl_rden (ctrl_rden),
.ctrl_ref_flag (ctrl_ref_flag),
.wdf_data (wdf_data),
.wdf_mask_data (wdf_mask_data),
.wdf_rden (wdf_rden),
.phy_init_done (phy_init_done),
.phy_calib_rden (phy_calib_rden),
.phy_calib_rden_sel (phy_calib_rden_sel),
.rd_data_rise (rd_data_rise),
.rd_data_fall (rd_data_fall),
.ddr_ck (ddr_ck),
.ddr_ck_n (ddr_ck_n),
.ddr_addr (ddr_addr),
.ddr_ba (ddr_ba),
.ddr_ras_n (ddr_ras_n),
.ddr_cas_n (ddr_cas_n),
.ddr_we_n (ddr_we_n),
.ddr_cs_n (ddr_cs_n),
.ddr_cke (ddr_cke),
.ddr_odt (ddr_odt),
.ddr_dm (ddr_dm),
.ddr_dqs (ddr_dqs),
.ddr_dqs_n (ddr_dqs_n),
.ddr_dq (ddr_dq),
.dbg_idel_up_all (dbg_idel_up_all),
.dbg_idel_down_all (dbg_idel_down_all),
.dbg_idel_up_dq (dbg_idel_up_dq),
.dbg_idel_down_dq (dbg_idel_down_dq),
.dbg_idel_up_dqs (dbg_idel_up_dqs),
.dbg_idel_down_dqs (dbg_idel_down_dqs),
.dbg_idel_up_gate (dbg_idel_up_gate),
.dbg_idel_down_gate (dbg_idel_down_gate),
.dbg_sel_idel_dq (dbg_sel_idel_dq),
.dbg_sel_all_idel_dq (dbg_sel_all_idel_dq),
.dbg_sel_idel_dqs (dbg_sel_idel_dqs),
.dbg_sel_all_idel_dqs (dbg_sel_all_idel_dqs),
.dbg_sel_idel_gate (dbg_sel_idel_gate),
.dbg_sel_all_idel_gate (dbg_sel_all_idel_gate),
.dbg_calib_done (dbg_calib_done),
.dbg_calib_err (dbg_calib_err),
.dbg_calib_dq_tap_cnt (dbg_calib_dq_tap_cnt),
.dbg_calib_dqs_tap_cnt (dbg_calib_dqs_tap_cnt),
.dbg_calib_gate_tap_cnt (dbg_calib_gate_tap_cnt),
.dbg_calib_rd_data_sel (dbg_calib_rd_data_sel),
.dbg_calib_rden_dly (dbg_calib_rden_dly),
.dbg_calib_gate_dly (dbg_calib_gate_dly)
);
ddr2_usr_top #
(
.BANK_WIDTH (BANK_WIDTH),
.COL_WIDTH (COL_WIDTH),
.CS_BITS (CS_BITS),
.DQ_WIDTH (DQ_WIDTH),
.DQ_PER_DQS (DQ_PER_DQS),
.DQS_WIDTH (DQS_WIDTH),
.APPDATA_WIDTH (APPDATA_WIDTH),
.ECC_ENABLE (ECC_ENABLE),
.ROW_WIDTH (ROW_WIDTH)
)
u_usr_top
(
.clk0 (clk0),
.usr_clk (usr_clk), //jb
.clk90 (clk90),
.rst0 (rst0),
.rd_data_in_rise (rd_data_rise),
.rd_data_in_fall (rd_data_fall),
.phy_calib_rden (phy_calib_rden),
.phy_calib_rden_sel(phy_calib_rden_sel),
.rd_data_valid (rd_data_valid),
.rd_ecc_error (rd_ecc_error),
.rd_data_fifo_out (rd_data_fifo_out),
.app_af_cmd (app_af_cmd),
.app_af_addr (app_af_addr),
.app_af_wren (app_af_wren),
.ctrl_af_rden (ctrl_af_rden),
.af_cmd (af_cmd),
.af_addr (af_addr),
.af_empty (af_empty),
.app_af_afull (app_af_afull),
.app_wdf_wren (app_wdf_wren),
.app_wdf_data (app_wdf_data),
.app_wdf_mask_data (app_wdf_mask_data),
.wdf_rden (wdf_rden),
.app_wdf_afull (app_wdf_afull),
.wdf_data (wdf_data),
.wdf_mask_data (wdf_mask_data)
);
ddr2_ctrl #
(
.BANK_WIDTH (BANK_WIDTH),
.COL_WIDTH (COL_WIDTH),
.CS_BITS (CS_BITS),
.CS_NUM (CS_NUM),
.ROW_WIDTH (ROW_WIDTH),
.ADDITIVE_LAT (ADDITIVE_LAT),
.BURST_LEN (BURST_LEN),
.CAS_LAT (CAS_LAT),
.ECC_ENABLE (ECC_ENABLE),
.REG_ENABLE (REG_ENABLE),
.MULTI_BANK_EN (MULTI_BANK_EN),
.TWO_T_TIME_EN (TWO_T_TIME_EN),
.TREFI_NS (TREFI_NS),
.TRAS (TRAS),
.TRCD (TRCD),
.TRFC (TRFC),
.TRP (TRP),
.TRTP (TRTP),
.TWR (TWR),
.TWTR (TWTR),
.CLK_PERIOD (CLK_PERIOD),
.DDR_TYPE (DDR_TYPE)
)
u_ctrl
(
.clk (clk0),
.rst (rst0),
.af_cmd (af_cmd),
.af_addr (af_addr),
.af_empty (af_empty),
.phy_init_done (phy_init_done),
.ctrl_ref_flag (ctrl_ref_flag),
.ctrl_af_rden (ctrl_af_rden),
.ctrl_wren (ctrl_wren),
.ctrl_rden (ctrl_rden),
.ctrl_addr (ctrl_addr),
.ctrl_ba (ctrl_ba),
.ctrl_ras_n (ctrl_ras_n),
.ctrl_cas_n (ctrl_cas_n),
.ctrl_we_n (ctrl_we_n),
.ctrl_cs_n (ctrl_cs_n)
, .sp_refresh_disable(sp_refresh_disable)
);
endmodule
|
module tb_ArtyA7;
reg sim_end;
reg RST_N;
reg CLK;
wire uart_txd_in;
wire uart_rxd_out;
wire [3:0] led;
initial begin
sim_end = 1'b0;
RST_N = 1'b0;
CLK = 1'b0;
force u_ArtyA7.u_fmrv32im_artya7_wrapper.fmrv32im_artya7_i.High_dout = 1'b0;
/*
`ifdef MOD_OSRAM
force u_ArtyA7.u_fmrv32im_artya7_wrapper.u_fmrv32im_core.u_fmrv32im_cache.i_base = 32'h2000_0000;
force u_ArtyA7.u_fmrv32im_artya7_wrapper.u_fmrv32im_core.u_fmrv32im_cache.d_base = 32'h2000_0000;
`endif
*/
#100;
@(posedge CLK);
RST_N = 1'b1;
force u_ArtyA7.u_fmrv32im_artya7_wrapper.fmrv32im_artya7_i.High_dout = 1'b1;
/*
`ifdef MOD_OSRAM
release u_ArtyA7.u_fmrv32im_artya7_wrapper.u_fmrv32im_core.u_fmrv32im_cache.i_base;
release u_ArtyA7.u_fmrv32im_artya7_wrapper.u_fmrv32im_core.u_fmrv32im_cache.d_base;
`endif
*/
$display("============================================================");
$display("Simulatin Start");
$display("============================================================");
end
// Clock
localparam CLK100M = 10;
always begin
#(CLK100M/2) CLK <= ~CLK;
end
reg [31:0] rslt;
/*
always @(posedge CLK) begin
if((u_ArtyA7.u_fmrv32im_artya7_wrapper.u_fmrv32im_core.dbus_addr == 32'h0000_0800) &
(u_ArtyA7.u_fmrv32im_artya7_wrapper.u_fmrv32im_core.dbus_wstb == 4'hF))
begin
rslt <= u_ArtyA7.u_fmrv32im_artya7_wrapper.u_fmrv32im_core.dbus_wdata;
end
end
*/
// Sinario
initial begin
wait(CLK);
@(posedge CLK);
$display("============================================================");
$display("Process Start");
$display("============================================================");
/*
wait((u_ArtyA7.u_fmrv32im_artya7_wrapper.u_fmrv32im_core.dbus_addr == 32'h0000_0800) &
(u_ArtyA7.u_fmrv32im_artya7_wrapper.u_fmrv32im_core.dbus_wstb == 4'hF));
*/
#(2000000);
u_task_uart.write("e");
u_task_uart.write("c");
u_task_uart.write("h");
u_task_uart.write("o");
u_task_uart.write("b");
u_task_uart.write("a");
u_task_uart.write("c");
u_task_uart.write("k");
u_task_uart.write("\r");
u_task_uart.write("\n");
wait(led==4'hF);
repeat(10) @(posedge CLK);
sim_end = 1;
end
integer iena_count;
initial begin
wait(sim_end);
$display("============================================================");
$display("Simulatin Finish");
$display("============================================================");
$display("Result: %8x", rslt);
$display("Inst Count: %d", iena_count);
$finish();
end
// initial $readmemh("../../../../src/imem.hex", u_fmrv32im_core.u_fmrv32im_cache.imem);
// initial $readmemh("../../../../src/imem.hex", u_fmrv32im_core.u_fmrv32im_cache.dmem);
ArtyA7
#(
.MEM_FILE ("../../../../src/imem.hex")
)
u_ArtyA7
(
.CLK100MHZ (CLK),
.uart_txd_in (uart_txd_in),
.uart_rxd_out (uart_rxd_out),
.led (led)
);
/*
always @(posedge CLK) begin
if(!RST_N) begin
iena_count <= 0;
end else begin
if(u_ArtyA7.u_fmrv32im_artya7_wrapper.u_fmrv32im_core.ibus_ena) begin
iena_count <= iena_count +1;
end
end
end
*/
task_uart u_task_uart(
.tx(uart_txd_in),
.rx(uart_rxd_out)
);
endmodule
|
module task_uart(
tx,
rx
);
output tx;
input rx;
reg tx;
reg clk, clk2;
reg [7:0] rdata;
reg rx_valid;
wire [7:0] rx_char;
initial begin
clk <= 1'b0;
clk2 <= 1'b0;
tx <= 1'b1;
end
always begin
#(1000000000/115200/2) clk <= ~clk;
end
always begin
#(1000000000/115200/2/2) clk2 <= ~clk2;
end
task write;
input [7:0] data;
begin
@(posedge clk);
tx <= 1'b1;
@(posedge clk);
tx <= 1'b0;
@(posedge clk);
tx <= data[0];
@(posedge clk);
tx <= data[1];
@(posedge clk);
tx <= data[2];
@(posedge clk);
tx <= data[3];
@(posedge clk);
tx <= data[4];
@(posedge clk);
tx <= data[5];
@(posedge clk);
tx <= data[6];
@(posedge clk);
tx <= data[7];
@(posedge clk);
tx <= 1'b1;
@(posedge clk);
tx <= 1'b1;
@(posedge clk);
end
endtask
// Receive
always begin
rx_valid <= 0;
@(posedge clk2);
if(rx == 1'b0) begin
repeat (2) @(posedge clk2);
rdata[0] <= rx;
repeat (2) @(posedge clk2);
rdata[1] <= rx;
repeat (2) @(posedge clk2);
rdata[2] <= rx;
repeat (2) @(posedge clk2);
rdata[3] <= rx;
repeat (2) @(posedge clk2);
rdata[4] <= rx;
repeat (2) @(posedge clk2);
rdata[5] <= rx;
repeat (2) @(posedge clk2);
rdata[6] <= rx;
repeat (2) @(posedge clk2);
rdata[7] <= rx;
repeat (2) @(posedge clk2);
if(rx == 1'b1) begin
// $display("%s", rdata[7:0]);
rx_valid <= 1;
$write("%s", rdata[7:0]);
end
repeat (2) @(posedge clk2);
end
end
assign rx_char = (rx_valid)?rdata:8'd0;
endmodule
|
module sky130_fd_sc_hd__sedfxtp (
Q ,
CLK ,
D ,
DE ,
SCD ,
SCE ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Q ;
input CLK ;
input D ;
input DE ;
input SCD ;
input SCE ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire buf_Q ;
wire mux_out;
wire de_d ;
// Delay Name Output Other arguments
sky130_fd_sc_hd__udp_mux_2to1 mux_2to10 (mux_out, de_d, SCD, SCE );
sky130_fd_sc_hd__udp_mux_2to1 mux_2to11 (de_d , buf_Q, D, DE );
sky130_fd_sc_hd__udp_dff$P_pp$PG$N `UNIT_DELAY dff0 (buf_Q , mux_out, CLK, , VPWR, VGND);
buf buf0 (Q , buf_Q );
endmodule
|
module omega_network_ff_tb;
parameter WIDTH = 8;
parameter IN_PORTS = 8;
parameter OUT_PORTS = IN_PORTS;
parameter ADDR_WIDTH_PORTS = log2(OUT_PORTS-1);
reg clk;
reg [0:IN_PORTS-1] push;
reg [IN_PORTS*WIDTH-1:0] d_in;
wire [0:OUT_PORTS-1] valid;
wire [OUT_PORTS*WIDTH-1:0] d_out;
reg [ADDR_WIDTH_PORTS-1:0] control;
omega_network_ff dut(clk, push, d_in, valid, d_out, control);
initial begin
clk = 0;
forever #5 clk=~clk;
end
reg rst;
integer i, j;
integer si;
reg [WIDTH-1:0] d_in_2d [0:IN_PORTS];
reg [WIDTH-1:0] d_out_2d [0:IN_PORTS];
always @* begin
for(i = 0; i < IN_PORTS; i = i + 1) begin
d_in[(i+1)*WIDTH-1 -: WIDTH] = d_in_2d[i];
d_out_2d[i] = d_out[(i+1)*WIDTH-1 -: WIDTH];
end
end
reg count_rst;
reg [ADDR_WIDTH_PORTS-1:0] count[0:2*ADDR_WIDTH_PORTS];
initial begin
push = 0;
rst = 1;
for(i = 0; i < IN_PORTS; i = i + 1) begin
d_in_2d[i] = i;
end
count_rst = 1;
//TODO: wait correct amount of time
#101 rst = 0;
push = -1;
#10 push = 0;
#1000 count_rst = 0;
#10 push = -1;
for(si = 0; si < IN_PORTS; si = si + 1) begin
$display("here");
#10;
end
push = 0;
#1000 $display("NO ERRORS");
$finish;
end
always @(posedge clk) begin
for(j = 0; j < ADDR_WIDTH_PORTS; j = j + 1) begin
control[ADDR_WIDTH_PORTS-j-1] = count[j*2][j];
end
end
always @(posedge clk) begin
if(!rst) begin
for(i = 0; i < IN_PORTS; i = i + 1) begin
if(valid[i]) begin
$display("port: %d data: %d", i, d_out_2d[i]);
end
end
end
end
always @(posedge clk) begin
if(count_rst)
count[0] <= 0;
else
count[0] <= count[0] + 1;
for(i = 0; i < 2*ADDR_WIDTH_PORTS; i = i + 1)
count[i+1] <= count[i];
end
`include "log2.vh"
endmodule
|
module vga_noise(clk, color, pause, vsync, hsync, style, test, audio_l, audio_r);
input clk;
output [7:0] color;
input pause;
input vsync, hsync;
input style;
input test;
output audio_l, audio_r;
reg [1:0] audio_data;
reg [7:0] latch;
reg [7:0] sr;
reg [12:0] divider;
wire noise_bit;
noise_generator gen (
.clk(clk),
.reset(pause&vsync),// reset the LFSR on vsync to give 'paused' noise effect
.random_bit(noise_bit)
);
// handy line-synchronised counter
always @(negedge clk)
begin
if(hsync)
divider <= 0;
else
divider <= divider + 1;
end
// divider[2] is a clock at pixel frequency
always @(posedge divider[2])
begin
latch <= sr;// latch shift register each complete byte (every 8 clock cycles)
end
// audio noise can be at a much lower rate
always @(posedge divider[12])
begin
if(!test && !pause)// turn off sound when noise is 'paused'
begin
audio_data <= sr[1:0];
end
end
always @(posedge clk)
begin
if(style)// colour
begin
if(test)
begin
// display test pattern (colour vertical stripes)
sr <= {divider[9],divider[9],divider[9],divider[8],divider[8],divider[8],divider[7],divider[7]};
end
else
begin
// add noise bits to shift register (8-bit 'colour' noise)
sr[7:1] <= sr[6:0];
sr[0] <= noise_bit;
end
end
else // monochrome
begin
if(test)
begin
// display test pattern (monochrome vertical stripes)
sr <= {divider[5],divider[5],divider[5],divider[5],divider[5],divider[5],divider[5],divider[5]};
end
else
begin
// load shift register with current noise bit value (monochrome noise)
sr <= {noise_bit,noise_bit,noise_bit,noise_bit,noise_bit,noise_bit,noise_bit,noise_bit};
end
end
end
assign color = latch;
// stereo noise!
assign audio_l = audio_data[0];
assign audio_r = audio_data[1];
endmodule
|
module sirv_AsyncResetRegVec_129(
input clock,
input reset,
input [19:0] io_d,
output [19:0] io_q,
input io_en
);
wire reg_0_rst;
wire reg_0_clk;
wire reg_0_en;
wire reg_0_q;
wire reg_0_d;
wire reg_1_rst;
wire reg_1_clk;
wire reg_1_en;
wire reg_1_q;
wire reg_1_d;
wire reg_2_rst;
wire reg_2_clk;
wire reg_2_en;
wire reg_2_q;
wire reg_2_d;
wire reg_3_rst;
wire reg_3_clk;
wire reg_3_en;
wire reg_3_q;
wire reg_3_d;
wire reg_4_rst;
wire reg_4_clk;
wire reg_4_en;
wire reg_4_q;
wire reg_4_d;
wire reg_5_rst;
wire reg_5_clk;
wire reg_5_en;
wire reg_5_q;
wire reg_5_d;
wire reg_6_rst;
wire reg_6_clk;
wire reg_6_en;
wire reg_6_q;
wire reg_6_d;
wire reg_7_rst;
wire reg_7_clk;
wire reg_7_en;
wire reg_7_q;
wire reg_7_d;
wire reg_8_rst;
wire reg_8_clk;
wire reg_8_en;
wire reg_8_q;
wire reg_8_d;
wire reg_9_rst;
wire reg_9_clk;
wire reg_9_en;
wire reg_9_q;
wire reg_9_d;
wire reg_10_rst;
wire reg_10_clk;
wire reg_10_en;
wire reg_10_q;
wire reg_10_d;
wire reg_11_rst;
wire reg_11_clk;
wire reg_11_en;
wire reg_11_q;
wire reg_11_d;
wire reg_12_rst;
wire reg_12_clk;
wire reg_12_en;
wire reg_12_q;
wire reg_12_d;
wire reg_13_rst;
wire reg_13_clk;
wire reg_13_en;
wire reg_13_q;
wire reg_13_d;
wire reg_14_rst;
wire reg_14_clk;
wire reg_14_en;
wire reg_14_q;
wire reg_14_d;
wire reg_15_rst;
wire reg_15_clk;
wire reg_15_en;
wire reg_15_q;
wire reg_15_d;
wire reg_16_rst;
wire reg_16_clk;
wire reg_16_en;
wire reg_16_q;
wire reg_16_d;
wire reg_17_rst;
wire reg_17_clk;
wire reg_17_en;
wire reg_17_q;
wire reg_17_d;
wire reg_18_rst;
wire reg_18_clk;
wire reg_18_en;
wire reg_18_q;
wire reg_18_d;
wire reg_19_rst;
wire reg_19_clk;
wire reg_19_en;
wire reg_19_q;
wire reg_19_d;
wire T_8;
wire T_9;
wire T_10;
wire T_11;
wire T_12;
wire T_13;
wire T_14;
wire T_15;
wire T_16;
wire T_17;
wire T_18;
wire T_19;
wire T_20;
wire T_21;
wire T_22;
wire T_23;
wire T_24;
wire T_25;
wire T_26;
wire T_27;
wire [1:0] T_28;
wire [1:0] T_29;
wire [2:0] T_30;
wire [4:0] T_31;
wire [1:0] T_32;
wire [1:0] T_33;
wire [2:0] T_34;
wire [4:0] T_35;
wire [9:0] T_36;
wire [1:0] T_37;
wire [1:0] T_38;
wire [2:0] T_39;
wire [4:0] T_40;
wire [1:0] T_41;
wire [1:0] T_42;
wire [2:0] T_43;
wire [4:0] T_44;
wire [9:0] T_45;
wire [19:0] T_46;
sirv_AsyncResetReg reg_0 (
.rst(reg_0_rst),
.clk(reg_0_clk),
.en(reg_0_en),
.q(reg_0_q),
.d(reg_0_d)
);
sirv_AsyncResetReg reg_1 (
.rst(reg_1_rst),
.clk(reg_1_clk),
.en(reg_1_en),
.q(reg_1_q),
.d(reg_1_d)
);
sirv_AsyncResetReg reg_2 (
.rst(reg_2_rst),
.clk(reg_2_clk),
.en(reg_2_en),
.q(reg_2_q),
.d(reg_2_d)
);
sirv_AsyncResetReg reg_3 (
.rst(reg_3_rst),
.clk(reg_3_clk),
.en(reg_3_en),
.q(reg_3_q),
.d(reg_3_d)
);
sirv_AsyncResetReg reg_4 (
.rst(reg_4_rst),
.clk(reg_4_clk),
.en(reg_4_en),
.q(reg_4_q),
.d(reg_4_d)
);
sirv_AsyncResetReg reg_5 (
.rst(reg_5_rst),
.clk(reg_5_clk),
.en(reg_5_en),
.q(reg_5_q),
.d(reg_5_d)
);
sirv_AsyncResetReg reg_6 (
.rst(reg_6_rst),
.clk(reg_6_clk),
.en(reg_6_en),
.q(reg_6_q),
.d(reg_6_d)
);
sirv_AsyncResetReg reg_7 (
.rst(reg_7_rst),
.clk(reg_7_clk),
.en(reg_7_en),
.q(reg_7_q),
.d(reg_7_d)
);
sirv_AsyncResetReg reg_8 (
.rst(reg_8_rst),
.clk(reg_8_clk),
.en(reg_8_en),
.q(reg_8_q),
.d(reg_8_d)
);
sirv_AsyncResetReg reg_9 (
.rst(reg_9_rst),
.clk(reg_9_clk),
.en(reg_9_en),
.q(reg_9_q),
.d(reg_9_d)
);
sirv_AsyncResetReg reg_10 (
.rst(reg_10_rst),
.clk(reg_10_clk),
.en(reg_10_en),
.q(reg_10_q),
.d(reg_10_d)
);
sirv_AsyncResetReg reg_11 (
.rst(reg_11_rst),
.clk(reg_11_clk),
.en(reg_11_en),
.q(reg_11_q),
.d(reg_11_d)
);
sirv_AsyncResetReg reg_12 (
.rst(reg_12_rst),
.clk(reg_12_clk),
.en(reg_12_en),
.q(reg_12_q),
.d(reg_12_d)
);
sirv_AsyncResetReg reg_13 (
.rst(reg_13_rst),
.clk(reg_13_clk),
.en(reg_13_en),
.q(reg_13_q),
.d(reg_13_d)
);
sirv_AsyncResetReg reg_14 (
.rst(reg_14_rst),
.clk(reg_14_clk),
.en(reg_14_en),
.q(reg_14_q),
.d(reg_14_d)
);
sirv_AsyncResetReg reg_15 (
.rst(reg_15_rst),
.clk(reg_15_clk),
.en(reg_15_en),
.q(reg_15_q),
.d(reg_15_d)
);
sirv_AsyncResetReg reg_16 (
.rst(reg_16_rst),
.clk(reg_16_clk),
.en(reg_16_en),
.q(reg_16_q),
.d(reg_16_d)
);
sirv_AsyncResetReg reg_17 (
.rst(reg_17_rst),
.clk(reg_17_clk),
.en(reg_17_en),
.q(reg_17_q),
.d(reg_17_d)
);
sirv_AsyncResetReg reg_18 (
.rst(reg_18_rst),
.clk(reg_18_clk),
.en(reg_18_en),
.q(reg_18_q),
.d(reg_18_d)
);
sirv_AsyncResetReg reg_19 (
.rst(reg_19_rst),
.clk(reg_19_clk),
.en(reg_19_en),
.q(reg_19_q),
.d(reg_19_d)
);
assign io_q = T_46;
assign reg_0_rst = reset;
assign reg_0_clk = clock;
assign reg_0_en = io_en;
assign reg_0_d = T_8;
assign reg_1_rst = reset;
assign reg_1_clk = clock;
assign reg_1_en = io_en;
assign reg_1_d = T_9;
assign reg_2_rst = reset;
assign reg_2_clk = clock;
assign reg_2_en = io_en;
assign reg_2_d = T_10;
assign reg_3_rst = reset;
assign reg_3_clk = clock;
assign reg_3_en = io_en;
assign reg_3_d = T_11;
assign reg_4_rst = reset;
assign reg_4_clk = clock;
assign reg_4_en = io_en;
assign reg_4_d = T_12;
assign reg_5_rst = reset;
assign reg_5_clk = clock;
assign reg_5_en = io_en;
assign reg_5_d = T_13;
assign reg_6_rst = reset;
assign reg_6_clk = clock;
assign reg_6_en = io_en;
assign reg_6_d = T_14;
assign reg_7_rst = reset;
assign reg_7_clk = clock;
assign reg_7_en = io_en;
assign reg_7_d = T_15;
assign reg_8_rst = reset;
assign reg_8_clk = clock;
assign reg_8_en = io_en;
assign reg_8_d = T_16;
assign reg_9_rst = reset;
assign reg_9_clk = clock;
assign reg_9_en = io_en;
assign reg_9_d = T_17;
assign reg_10_rst = reset;
assign reg_10_clk = clock;
assign reg_10_en = io_en;
assign reg_10_d = T_18;
assign reg_11_rst = reset;
assign reg_11_clk = clock;
assign reg_11_en = io_en;
assign reg_11_d = T_19;
assign reg_12_rst = reset;
assign reg_12_clk = clock;
assign reg_12_en = io_en;
assign reg_12_d = T_20;
assign reg_13_rst = reset;
assign reg_13_clk = clock;
assign reg_13_en = io_en;
assign reg_13_d = T_21;
assign reg_14_rst = reset;
assign reg_14_clk = clock;
assign reg_14_en = io_en;
assign reg_14_d = T_22;
assign reg_15_rst = reset;
assign reg_15_clk = clock;
assign reg_15_en = io_en;
assign reg_15_d = T_23;
assign reg_16_rst = reset;
assign reg_16_clk = clock;
assign reg_16_en = io_en;
assign reg_16_d = T_24;
assign reg_17_rst = reset;
assign reg_17_clk = clock;
assign reg_17_en = io_en;
assign reg_17_d = T_25;
assign reg_18_rst = reset;
assign reg_18_clk = clock;
assign reg_18_en = io_en;
assign reg_18_d = T_26;
assign reg_19_rst = reset;
assign reg_19_clk = clock;
assign reg_19_en = io_en;
assign reg_19_d = T_27;
assign T_8 = io_d[0];
assign T_9 = io_d[1];
assign T_10 = io_d[2];
assign T_11 = io_d[3];
assign T_12 = io_d[4];
assign T_13 = io_d[5];
assign T_14 = io_d[6];
assign T_15 = io_d[7];
assign T_16 = io_d[8];
assign T_17 = io_d[9];
assign T_18 = io_d[10];
assign T_19 = io_d[11];
assign T_20 = io_d[12];
assign T_21 = io_d[13];
assign T_22 = io_d[14];
assign T_23 = io_d[15];
assign T_24 = io_d[16];
assign T_25 = io_d[17];
assign T_26 = io_d[18];
assign T_27 = io_d[19];
assign T_28 = {reg_1_q,reg_0_q};
assign T_29 = {reg_4_q,reg_3_q};
assign T_30 = {T_29,reg_2_q};
assign T_31 = {T_30,T_28};
assign T_32 = {reg_6_q,reg_5_q};
assign T_33 = {reg_9_q,reg_8_q};
assign T_34 = {T_33,reg_7_q};
assign T_35 = {T_34,T_32};
assign T_36 = {T_35,T_31};
assign T_37 = {reg_11_q,reg_10_q};
assign T_38 = {reg_14_q,reg_13_q};
assign T_39 = {T_38,reg_12_q};
assign T_40 = {T_39,T_37};
assign T_41 = {reg_16_q,reg_15_q};
assign T_42 = {reg_19_q,reg_18_q};
assign T_43 = {T_42,reg_17_q};
assign T_44 = {T_43,T_41};
assign T_45 = {T_44,T_40};
assign T_46 = {T_45,T_36};
endmodule
|
module SoC (
input wire clk_clk, // clk.clk
input wire reset_reset_n // reset.reset_n
);
wire nios_data_master_waitrequest; // NIOS_data_master_translator:av_waitrequest -> NIOS:d_waitrequest
wire [31:0] nios_data_master_writedata; // NIOS:d_writedata -> NIOS_data_master_translator:av_writedata
wire [18:0] nios_data_master_address; // NIOS:d_address -> NIOS_data_master_translator:av_address
wire nios_data_master_write; // NIOS:d_write -> NIOS_data_master_translator:av_write
wire nios_data_master_read; // NIOS:d_read -> NIOS_data_master_translator:av_read
wire [31:0] nios_data_master_readdata; // NIOS_data_master_translator:av_readdata -> NIOS:d_readdata
wire nios_data_master_debugaccess; // NIOS:jtag_debug_module_debugaccess_to_roms -> NIOS_data_master_translator:av_debugaccess
wire [3:0] nios_data_master_byteenable; // NIOS:d_byteenable -> NIOS_data_master_translator:av_byteenable
wire nios_instruction_master_waitrequest; // NIOS_instruction_master_translator:av_waitrequest -> NIOS:i_waitrequest
wire [18:0] nios_instruction_master_address; // NIOS:i_address -> NIOS_instruction_master_translator:av_address
wire nios_instruction_master_read; // NIOS:i_read -> NIOS_instruction_master_translator:av_read
wire [31:0] nios_instruction_master_readdata; // NIOS_instruction_master_translator:av_readdata -> NIOS:i_readdata
wire nios_instruction_master_readdatavalid; // NIOS_instruction_master_translator:av_readdatavalid -> NIOS:i_readdatavalid
wire [31:0] ram_s1_translator_avalon_anti_slave_0_writedata; // RAM_s1_translator:av_writedata -> RAM:writedata
wire [14:0] ram_s1_translator_avalon_anti_slave_0_address; // RAM_s1_translator:av_address -> RAM:address
wire ram_s1_translator_avalon_anti_slave_0_chipselect; // RAM_s1_translator:av_chipselect -> RAM:chipselect
wire ram_s1_translator_avalon_anti_slave_0_clken; // RAM_s1_translator:av_clken -> RAM:clken
wire ram_s1_translator_avalon_anti_slave_0_write; // RAM_s1_translator:av_write -> RAM:write
wire [31:0] ram_s1_translator_avalon_anti_slave_0_readdata; // RAM:readdata -> RAM_s1_translator:av_readdata
wire [3:0] ram_s1_translator_avalon_anti_slave_0_byteenable; // RAM_s1_translator:av_byteenable -> RAM:byteenable
wire jtag_uart_0_avalon_jtag_slave_translator_avalon_anti_slave_0_waitrequest; // jtag_uart_0:av_waitrequest -> jtag_uart_0_avalon_jtag_slave_translator:av_waitrequest
wire [31:0] jtag_uart_0_avalon_jtag_slave_translator_avalon_anti_slave_0_writedata; // jtag_uart_0_avalon_jtag_slave_translator:av_writedata -> jtag_uart_0:av_writedata
wire [0:0] jtag_uart_0_avalon_jtag_slave_translator_avalon_anti_slave_0_address; // jtag_uart_0_avalon_jtag_slave_translator:av_address -> jtag_uart_0:av_address
wire jtag_uart_0_avalon_jtag_slave_translator_avalon_anti_slave_0_chipselect; // jtag_uart_0_avalon_jtag_slave_translator:av_chipselect -> jtag_uart_0:av_chipselect
wire jtag_uart_0_avalon_jtag_slave_translator_avalon_anti_slave_0_write; // jtag_uart_0_avalon_jtag_slave_translator:av_write -> jtag_uart_0:av_write_n
wire jtag_uart_0_avalon_jtag_slave_translator_avalon_anti_slave_0_read; // jtag_uart_0_avalon_jtag_slave_translator:av_read -> jtag_uart_0:av_read_n
wire [31:0] jtag_uart_0_avalon_jtag_slave_translator_avalon_anti_slave_0_readdata; // jtag_uart_0:av_readdata -> jtag_uart_0_avalon_jtag_slave_translator:av_readdata
wire [0:0] sysid_qsys_0_control_slave_translator_avalon_anti_slave_0_address; // sysid_qsys_0_control_slave_translator:av_address -> sysid_qsys_0:address
wire [31:0] sysid_qsys_0_control_slave_translator_avalon_anti_slave_0_readdata; // sysid_qsys_0:readdata -> sysid_qsys_0_control_slave_translator:av_readdata
wire nios_jtag_debug_module_translator_avalon_anti_slave_0_waitrequest; // NIOS:jtag_debug_module_waitrequest -> NIOS_jtag_debug_module_translator:av_waitrequest
wire [31:0] nios_jtag_debug_module_translator_avalon_anti_slave_0_writedata; // NIOS_jtag_debug_module_translator:av_writedata -> NIOS:jtag_debug_module_writedata
wire [8:0] nios_jtag_debug_module_translator_avalon_anti_slave_0_address; // NIOS_jtag_debug_module_translator:av_address -> NIOS:jtag_debug_module_address
wire nios_jtag_debug_module_translator_avalon_anti_slave_0_write; // NIOS_jtag_debug_module_translator:av_write -> NIOS:jtag_debug_module_write
wire nios_jtag_debug_module_translator_avalon_anti_slave_0_read; // NIOS_jtag_debug_module_translator:av_read -> NIOS:jtag_debug_module_read
wire [31:0] nios_jtag_debug_module_translator_avalon_anti_slave_0_readdata; // NIOS:jtag_debug_module_readdata -> NIOS_jtag_debug_module_translator:av_readdata
wire nios_jtag_debug_module_translator_avalon_anti_slave_0_debugaccess; // NIOS_jtag_debug_module_translator:av_debugaccess -> NIOS:jtag_debug_module_debugaccess
wire [3:0] nios_jtag_debug_module_translator_avalon_anti_slave_0_byteenable; // NIOS_jtag_debug_module_translator:av_byteenable -> NIOS:jtag_debug_module_byteenable
wire [31:0] hw_ann_0_avalon_slave_0_translator_avalon_anti_slave_0_writedata; // hw_ann_0_avalon_slave_0_translator:av_writedata -> hw_ann_0:writedata
wire [8:0] hw_ann_0_avalon_slave_0_translator_avalon_anti_slave_0_address; // hw_ann_0_avalon_slave_0_translator:av_address -> hw_ann_0:address
wire hw_ann_0_avalon_slave_0_translator_avalon_anti_slave_0_write; // hw_ann_0_avalon_slave_0_translator:av_write -> hw_ann_0:write
wire hw_ann_0_avalon_slave_0_translator_avalon_anti_slave_0_read; // hw_ann_0_avalon_slave_0_translator:av_read -> hw_ann_0:read
wire [31:0] hw_ann_0_avalon_slave_0_translator_avalon_anti_slave_0_readdata; // hw_ann_0:readdata -> hw_ann_0_avalon_slave_0_translator:av_readdata
wire lfsr_0_avalon_slave_0_translator_avalon_anti_slave_0_read; // lfsr_0_avalon_slave_0_translator:av_read -> lfsr_0:read
wire [31:0] lfsr_0_avalon_slave_0_translator_avalon_anti_slave_0_readdata; // lfsr_0:read_data -> lfsr_0_avalon_slave_0_translator:av_readdata
wire nios_data_master_translator_avalon_universal_master_0_waitrequest; // NIOS_data_master_translator_avalon_universal_master_0_agent:av_waitrequest -> NIOS_data_master_translator:uav_waitrequest
wire [2:0] nios_data_master_translator_avalon_universal_master_0_burstcount; // NIOS_data_master_translator:uav_burstcount -> NIOS_data_master_translator_avalon_universal_master_0_agent:av_burstcount
wire [31:0] nios_data_master_translator_avalon_universal_master_0_writedata; // NIOS_data_master_translator:uav_writedata -> NIOS_data_master_translator_avalon_universal_master_0_agent:av_writedata
wire [18:0] nios_data_master_translator_avalon_universal_master_0_address; // NIOS_data_master_translator:uav_address -> NIOS_data_master_translator_avalon_universal_master_0_agent:av_address
wire nios_data_master_translator_avalon_universal_master_0_lock; // NIOS_data_master_translator:uav_lock -> NIOS_data_master_translator_avalon_universal_master_0_agent:av_lock
wire nios_data_master_translator_avalon_universal_master_0_write; // NIOS_data_master_translator:uav_write -> NIOS_data_master_translator_avalon_universal_master_0_agent:av_write
wire nios_data_master_translator_avalon_universal_master_0_read; // NIOS_data_master_translator:uav_read -> NIOS_data_master_translator_avalon_universal_master_0_agent:av_read
wire [31:0] nios_data_master_translator_avalon_universal_master_0_readdata; // NIOS_data_master_translator_avalon_universal_master_0_agent:av_readdata -> NIOS_data_master_translator:uav_readdata
wire nios_data_master_translator_avalon_universal_master_0_debugaccess; // NIOS_data_master_translator:uav_debugaccess -> NIOS_data_master_translator_avalon_universal_master_0_agent:av_debugaccess
wire [3:0] nios_data_master_translator_avalon_universal_master_0_byteenable; // NIOS_data_master_translator:uav_byteenable -> NIOS_data_master_translator_avalon_universal_master_0_agent:av_byteenable
wire nios_data_master_translator_avalon_universal_master_0_readdatavalid; // NIOS_data_master_translator_avalon_universal_master_0_agent:av_readdatavalid -> NIOS_data_master_translator:uav_readdatavalid
wire nios_instruction_master_translator_avalon_universal_master_0_waitrequest; // NIOS_instruction_master_translator_avalon_universal_master_0_agent:av_waitrequest -> NIOS_instruction_master_translator:uav_waitrequest
wire [2:0] nios_instruction_master_translator_avalon_universal_master_0_burstcount; // NIOS_instruction_master_translator:uav_burstcount -> NIOS_instruction_master_translator_avalon_universal_master_0_agent:av_burstcount
wire [31:0] nios_instruction_master_translator_avalon_universal_master_0_writedata; // NIOS_instruction_master_translator:uav_writedata -> NIOS_instruction_master_translator_avalon_universal_master_0_agent:av_writedata
wire [18:0] nios_instruction_master_translator_avalon_universal_master_0_address; // NIOS_instruction_master_translator:uav_address -> NIOS_instruction_master_translator_avalon_universal_master_0_agent:av_address
wire nios_instruction_master_translator_avalon_universal_master_0_lock; // NIOS_instruction_master_translator:uav_lock -> NIOS_instruction_master_translator_avalon_universal_master_0_agent:av_lock
wire nios_instruction_master_translator_avalon_universal_master_0_write; // NIOS_instruction_master_translator:uav_write -> NIOS_instruction_master_translator_avalon_universal_master_0_agent:av_write
wire nios_instruction_master_translator_avalon_universal_master_0_read; // NIOS_instruction_master_translator:uav_read -> NIOS_instruction_master_translator_avalon_universal_master_0_agent:av_read
wire [31:0] nios_instruction_master_translator_avalon_universal_master_0_readdata; // NIOS_instruction_master_translator_avalon_universal_master_0_agent:av_readdata -> NIOS_instruction_master_translator:uav_readdata
wire nios_instruction_master_translator_avalon_universal_master_0_debugaccess; // NIOS_instruction_master_translator:uav_debugaccess -> NIOS_instruction_master_translator_avalon_universal_master_0_agent:av_debugaccess
wire [3:0] nios_instruction_master_translator_avalon_universal_master_0_byteenable; // NIOS_instruction_master_translator:uav_byteenable -> NIOS_instruction_master_translator_avalon_universal_master_0_agent:av_byteenable
wire nios_instruction_master_translator_avalon_universal_master_0_readdatavalid; // NIOS_instruction_master_translator_avalon_universal_master_0_agent:av_readdatavalid -> NIOS_instruction_master_translator:uav_readdatavalid
wire ram_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest; // RAM_s1_translator:uav_waitrequest -> RAM_s1_translator_avalon_universal_slave_0_agent:m0_waitrequest
wire [2:0] ram_s1_translator_avalon_universal_slave_0_agent_m0_burstcount; // RAM_s1_translator_avalon_universal_slave_0_agent:m0_burstcount -> RAM_s1_translator:uav_burstcount
wire [31:0] ram_s1_translator_avalon_universal_slave_0_agent_m0_writedata; // RAM_s1_translator_avalon_universal_slave_0_agent:m0_writedata -> RAM_s1_translator:uav_writedata
wire [18:0] ram_s1_translator_avalon_universal_slave_0_agent_m0_address; // RAM_s1_translator_avalon_universal_slave_0_agent:m0_address -> RAM_s1_translator:uav_address
wire ram_s1_translator_avalon_universal_slave_0_agent_m0_write; // RAM_s1_translator_avalon_universal_slave_0_agent:m0_write -> RAM_s1_translator:uav_write
wire ram_s1_translator_avalon_universal_slave_0_agent_m0_lock; // RAM_s1_translator_avalon_universal_slave_0_agent:m0_lock -> RAM_s1_translator:uav_lock
wire ram_s1_translator_avalon_universal_slave_0_agent_m0_read; // RAM_s1_translator_avalon_universal_slave_0_agent:m0_read -> RAM_s1_translator:uav_read
wire [31:0] ram_s1_translator_avalon_universal_slave_0_agent_m0_readdata; // RAM_s1_translator:uav_readdata -> RAM_s1_translator_avalon_universal_slave_0_agent:m0_readdata
wire ram_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid; // RAM_s1_translator:uav_readdatavalid -> RAM_s1_translator_avalon_universal_slave_0_agent:m0_readdatavalid
wire ram_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess; // RAM_s1_translator_avalon_universal_slave_0_agent:m0_debugaccess -> RAM_s1_translator:uav_debugaccess
wire [3:0] ram_s1_translator_avalon_universal_slave_0_agent_m0_byteenable; // RAM_s1_translator_avalon_universal_slave_0_agent:m0_byteenable -> RAM_s1_translator:uav_byteenable
wire ram_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket; // RAM_s1_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> RAM_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket
wire ram_s1_translator_avalon_universal_slave_0_agent_rf_source_valid; // RAM_s1_translator_avalon_universal_slave_0_agent:rf_source_valid -> RAM_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid
wire ram_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket; // RAM_s1_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> RAM_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket
wire [92:0] ram_s1_translator_avalon_universal_slave_0_agent_rf_source_data; // RAM_s1_translator_avalon_universal_slave_0_agent:rf_source_data -> RAM_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data
wire ram_s1_translator_avalon_universal_slave_0_agent_rf_source_ready; // RAM_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> RAM_s1_translator_avalon_universal_slave_0_agent:rf_source_ready
wire ram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket; // RAM_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> RAM_s1_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket
wire ram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid; // RAM_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> RAM_s1_translator_avalon_universal_slave_0_agent:rf_sink_valid
wire ram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket; // RAM_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> RAM_s1_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket
wire [92:0] ram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data; // RAM_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> RAM_s1_translator_avalon_universal_slave_0_agent:rf_sink_data
wire ram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready; // RAM_s1_translator_avalon_universal_slave_0_agent:rf_sink_ready -> RAM_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready
wire ram_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid; // RAM_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> RAM_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid
wire [33:0] ram_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data; // RAM_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> RAM_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data
wire ram_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready; // RAM_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> RAM_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready
wire jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_waitrequest; // jtag_uart_0_avalon_jtag_slave_translator:uav_waitrequest -> jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:m0_waitrequest
wire [2:0] jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_burstcount; // jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:m0_burstcount -> jtag_uart_0_avalon_jtag_slave_translator:uav_burstcount
wire [31:0] jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_writedata; // jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:m0_writedata -> jtag_uart_0_avalon_jtag_slave_translator:uav_writedata
wire [18:0] jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_address; // jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:m0_address -> jtag_uart_0_avalon_jtag_slave_translator:uav_address
wire jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_write; // jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:m0_write -> jtag_uart_0_avalon_jtag_slave_translator:uav_write
wire jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_lock; // jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:m0_lock -> jtag_uart_0_avalon_jtag_slave_translator:uav_lock
wire jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_read; // jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:m0_read -> jtag_uart_0_avalon_jtag_slave_translator:uav_read
wire [31:0] jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_readdata; // jtag_uart_0_avalon_jtag_slave_translator:uav_readdata -> jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:m0_readdata
wire jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_readdatavalid; // jtag_uart_0_avalon_jtag_slave_translator:uav_readdatavalid -> jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:m0_readdatavalid
wire jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_debugaccess; // jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:m0_debugaccess -> jtag_uart_0_avalon_jtag_slave_translator:uav_debugaccess
wire [3:0] jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_byteenable; // jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:m0_byteenable -> jtag_uart_0_avalon_jtag_slave_translator:uav_byteenable
wire jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rf_source_endofpacket; // jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket
wire jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rf_source_valid; // jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rf_source_valid -> jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid
wire jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rf_source_startofpacket; // jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket
wire [92:0] jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rf_source_data; // jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rf_source_data -> jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data
wire jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rf_source_ready; // jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rf_source_ready
wire jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket; // jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket
wire jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid; // jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rf_sink_valid
wire jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket; // jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket
wire [92:0] jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data; // jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rf_sink_data
wire jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready; // jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rf_sink_ready -> jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready
wire jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid; // jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid
wire [33:0] jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data; // jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data
wire jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready; // jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready
wire sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_waitrequest; // sysid_qsys_0_control_slave_translator:uav_waitrequest -> sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:m0_waitrequest
wire [2:0] sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_burstcount; // sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:m0_burstcount -> sysid_qsys_0_control_slave_translator:uav_burstcount
wire [31:0] sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_writedata; // sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:m0_writedata -> sysid_qsys_0_control_slave_translator:uav_writedata
wire [18:0] sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_address; // sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:m0_address -> sysid_qsys_0_control_slave_translator:uav_address
wire sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_write; // sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:m0_write -> sysid_qsys_0_control_slave_translator:uav_write
wire sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_lock; // sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:m0_lock -> sysid_qsys_0_control_slave_translator:uav_lock
wire sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_read; // sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:m0_read -> sysid_qsys_0_control_slave_translator:uav_read
wire [31:0] sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_readdata; // sysid_qsys_0_control_slave_translator:uav_readdata -> sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:m0_readdata
wire sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_readdatavalid; // sysid_qsys_0_control_slave_translator:uav_readdatavalid -> sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:m0_readdatavalid
wire sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_debugaccess; // sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:m0_debugaccess -> sysid_qsys_0_control_slave_translator:uav_debugaccess
wire [3:0] sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_byteenable; // sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:m0_byteenable -> sysid_qsys_0_control_slave_translator:uav_byteenable
wire sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rf_source_endofpacket; // sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket
wire sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rf_source_valid; // sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:rf_source_valid -> sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid
wire sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rf_source_startofpacket; // sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket
wire [92:0] sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rf_source_data; // sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:rf_source_data -> sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data
wire sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rf_source_ready; // sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:rf_source_ready
wire sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket; // sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket
wire sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid; // sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:rf_sink_valid
wire sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket; // sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket
wire [92:0] sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data; // sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:rf_sink_data
wire sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready; // sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:rf_sink_ready -> sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready
wire sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid; // sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid
wire [33:0] sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data; // sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data
wire sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready; // sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready
wire nios_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_waitrequest; // NIOS_jtag_debug_module_translator:uav_waitrequest -> NIOS_jtag_debug_module_translator_avalon_universal_slave_0_agent:m0_waitrequest
wire [2:0] nios_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_burstcount; // NIOS_jtag_debug_module_translator_avalon_universal_slave_0_agent:m0_burstcount -> NIOS_jtag_debug_module_translator:uav_burstcount
wire [31:0] nios_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_writedata; // NIOS_jtag_debug_module_translator_avalon_universal_slave_0_agent:m0_writedata -> NIOS_jtag_debug_module_translator:uav_writedata
wire [18:0] nios_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_address; // NIOS_jtag_debug_module_translator_avalon_universal_slave_0_agent:m0_address -> NIOS_jtag_debug_module_translator:uav_address
wire nios_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_write; // NIOS_jtag_debug_module_translator_avalon_universal_slave_0_agent:m0_write -> NIOS_jtag_debug_module_translator:uav_write
wire nios_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_lock; // NIOS_jtag_debug_module_translator_avalon_universal_slave_0_agent:m0_lock -> NIOS_jtag_debug_module_translator:uav_lock
wire nios_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_read; // NIOS_jtag_debug_module_translator_avalon_universal_slave_0_agent:m0_read -> NIOS_jtag_debug_module_translator:uav_read
wire [31:0] nios_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_readdata; // NIOS_jtag_debug_module_translator:uav_readdata -> NIOS_jtag_debug_module_translator_avalon_universal_slave_0_agent:m0_readdata
wire nios_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_readdatavalid; // NIOS_jtag_debug_module_translator:uav_readdatavalid -> NIOS_jtag_debug_module_translator_avalon_universal_slave_0_agent:m0_readdatavalid
wire nios_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_debugaccess; // NIOS_jtag_debug_module_translator_avalon_universal_slave_0_agent:m0_debugaccess -> NIOS_jtag_debug_module_translator:uav_debugaccess
wire [3:0] nios_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_byteenable; // NIOS_jtag_debug_module_translator_avalon_universal_slave_0_agent:m0_byteenable -> NIOS_jtag_debug_module_translator:uav_byteenable
wire nios_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_endofpacket; // NIOS_jtag_debug_module_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> NIOS_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket
wire nios_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_valid; // NIOS_jtag_debug_module_translator_avalon_universal_slave_0_agent:rf_source_valid -> NIOS_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid
wire nios_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_startofpacket; // NIOS_jtag_debug_module_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> NIOS_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket
wire [92:0] nios_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_data; // NIOS_jtag_debug_module_translator_avalon_universal_slave_0_agent:rf_source_data -> NIOS_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data
wire nios_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_ready; // NIOS_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> NIOS_jtag_debug_module_translator_avalon_universal_slave_0_agent:rf_source_ready
wire nios_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket; // NIOS_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> NIOS_jtag_debug_module_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket
wire nios_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid; // NIOS_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> NIOS_jtag_debug_module_translator_avalon_universal_slave_0_agent:rf_sink_valid
wire nios_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket; // NIOS_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> NIOS_jtag_debug_module_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket
wire [92:0] nios_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data; // NIOS_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> NIOS_jtag_debug_module_translator_avalon_universal_slave_0_agent:rf_sink_data
wire nios_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready; // NIOS_jtag_debug_module_translator_avalon_universal_slave_0_agent:rf_sink_ready -> NIOS_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready
wire nios_jtag_debug_module_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid; // NIOS_jtag_debug_module_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> NIOS_jtag_debug_module_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid
wire [33:0] nios_jtag_debug_module_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data; // NIOS_jtag_debug_module_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> NIOS_jtag_debug_module_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data
wire nios_jtag_debug_module_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready; // NIOS_jtag_debug_module_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> NIOS_jtag_debug_module_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready
wire hw_ann_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_waitrequest; // hw_ann_0_avalon_slave_0_translator:uav_waitrequest -> hw_ann_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:m0_waitrequest
wire [2:0] hw_ann_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_burstcount; // hw_ann_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:m0_burstcount -> hw_ann_0_avalon_slave_0_translator:uav_burstcount
wire [31:0] hw_ann_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_writedata; // hw_ann_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:m0_writedata -> hw_ann_0_avalon_slave_0_translator:uav_writedata
wire [18:0] hw_ann_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_address; // hw_ann_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:m0_address -> hw_ann_0_avalon_slave_0_translator:uav_address
wire hw_ann_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_write; // hw_ann_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:m0_write -> hw_ann_0_avalon_slave_0_translator:uav_write
wire hw_ann_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_lock; // hw_ann_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:m0_lock -> hw_ann_0_avalon_slave_0_translator:uav_lock
wire hw_ann_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_read; // hw_ann_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:m0_read -> hw_ann_0_avalon_slave_0_translator:uav_read
wire [31:0] hw_ann_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_readdata; // hw_ann_0_avalon_slave_0_translator:uav_readdata -> hw_ann_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:m0_readdata
wire hw_ann_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_readdatavalid; // hw_ann_0_avalon_slave_0_translator:uav_readdatavalid -> hw_ann_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:m0_readdatavalid
wire hw_ann_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_debugaccess; // hw_ann_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:m0_debugaccess -> hw_ann_0_avalon_slave_0_translator:uav_debugaccess
wire [3:0] hw_ann_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_byteenable; // hw_ann_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:m0_byteenable -> hw_ann_0_avalon_slave_0_translator:uav_byteenable
wire hw_ann_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_endofpacket; // hw_ann_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> hw_ann_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket
wire hw_ann_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_valid; // hw_ann_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rf_source_valid -> hw_ann_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid
wire hw_ann_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_startofpacket; // hw_ann_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> hw_ann_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket
wire [92:0] hw_ann_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_data; // hw_ann_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rf_source_data -> hw_ann_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data
wire hw_ann_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_ready; // hw_ann_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> hw_ann_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rf_source_ready
wire hw_ann_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket; // hw_ann_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> hw_ann_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket
wire hw_ann_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid; // hw_ann_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> hw_ann_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rf_sink_valid
wire hw_ann_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket; // hw_ann_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> hw_ann_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket
wire [92:0] hw_ann_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data; // hw_ann_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> hw_ann_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rf_sink_data
wire hw_ann_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready; // hw_ann_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rf_sink_ready -> hw_ann_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready
wire hw_ann_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid; // hw_ann_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> hw_ann_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid
wire [33:0] hw_ann_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data; // hw_ann_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> hw_ann_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data
wire hw_ann_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready; // hw_ann_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> hw_ann_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready
wire lfsr_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_waitrequest; // lfsr_0_avalon_slave_0_translator:uav_waitrequest -> lfsr_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:m0_waitrequest
wire [2:0] lfsr_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_burstcount; // lfsr_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:m0_burstcount -> lfsr_0_avalon_slave_0_translator:uav_burstcount
wire [31:0] lfsr_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_writedata; // lfsr_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:m0_writedata -> lfsr_0_avalon_slave_0_translator:uav_writedata
wire [18:0] lfsr_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_address; // lfsr_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:m0_address -> lfsr_0_avalon_slave_0_translator:uav_address
wire lfsr_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_write; // lfsr_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:m0_write -> lfsr_0_avalon_slave_0_translator:uav_write
wire lfsr_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_lock; // lfsr_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:m0_lock -> lfsr_0_avalon_slave_0_translator:uav_lock
wire lfsr_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_read; // lfsr_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:m0_read -> lfsr_0_avalon_slave_0_translator:uav_read
wire [31:0] lfsr_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_readdata; // lfsr_0_avalon_slave_0_translator:uav_readdata -> lfsr_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:m0_readdata
wire lfsr_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_readdatavalid; // lfsr_0_avalon_slave_0_translator:uav_readdatavalid -> lfsr_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:m0_readdatavalid
wire lfsr_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_debugaccess; // lfsr_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:m0_debugaccess -> lfsr_0_avalon_slave_0_translator:uav_debugaccess
wire [3:0] lfsr_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_byteenable; // lfsr_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:m0_byteenable -> lfsr_0_avalon_slave_0_translator:uav_byteenable
wire lfsr_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_endofpacket; // lfsr_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> lfsr_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket
wire lfsr_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_valid; // lfsr_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rf_source_valid -> lfsr_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid
wire lfsr_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_startofpacket; // lfsr_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> lfsr_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket
wire [92:0] lfsr_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_data; // lfsr_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rf_source_data -> lfsr_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data
wire lfsr_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_ready; // lfsr_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> lfsr_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rf_source_ready
wire lfsr_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket; // lfsr_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> lfsr_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket
wire lfsr_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid; // lfsr_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> lfsr_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rf_sink_valid
wire lfsr_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket; // lfsr_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> lfsr_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket
wire [92:0] lfsr_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data; // lfsr_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> lfsr_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rf_sink_data
wire lfsr_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready; // lfsr_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rf_sink_ready -> lfsr_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready
wire lfsr_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid; // lfsr_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> lfsr_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid
wire [33:0] lfsr_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data; // lfsr_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> lfsr_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data
wire lfsr_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready; // lfsr_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> lfsr_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready
wire nios_data_master_translator_avalon_universal_master_0_agent_cp_endofpacket; // NIOS_data_master_translator_avalon_universal_master_0_agent:cp_endofpacket -> addr_router:sink_endofpacket
wire nios_data_master_translator_avalon_universal_master_0_agent_cp_valid; // NIOS_data_master_translator_avalon_universal_master_0_agent:cp_valid -> addr_router:sink_valid
wire nios_data_master_translator_avalon_universal_master_0_agent_cp_startofpacket; // NIOS_data_master_translator_avalon_universal_master_0_agent:cp_startofpacket -> addr_router:sink_startofpacket
wire [91:0] nios_data_master_translator_avalon_universal_master_0_agent_cp_data; // NIOS_data_master_translator_avalon_universal_master_0_agent:cp_data -> addr_router:sink_data
wire nios_data_master_translator_avalon_universal_master_0_agent_cp_ready; // addr_router:sink_ready -> NIOS_data_master_translator_avalon_universal_master_0_agent:cp_ready
wire nios_instruction_master_translator_avalon_universal_master_0_agent_cp_endofpacket; // NIOS_instruction_master_translator_avalon_universal_master_0_agent:cp_endofpacket -> addr_router_001:sink_endofpacket
wire nios_instruction_master_translator_avalon_universal_master_0_agent_cp_valid; // NIOS_instruction_master_translator_avalon_universal_master_0_agent:cp_valid -> addr_router_001:sink_valid
wire nios_instruction_master_translator_avalon_universal_master_0_agent_cp_startofpacket; // NIOS_instruction_master_translator_avalon_universal_master_0_agent:cp_startofpacket -> addr_router_001:sink_startofpacket
wire [91:0] nios_instruction_master_translator_avalon_universal_master_0_agent_cp_data; // NIOS_instruction_master_translator_avalon_universal_master_0_agent:cp_data -> addr_router_001:sink_data
wire nios_instruction_master_translator_avalon_universal_master_0_agent_cp_ready; // addr_router_001:sink_ready -> NIOS_instruction_master_translator_avalon_universal_master_0_agent:cp_ready
wire ram_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket; // RAM_s1_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router:sink_endofpacket
wire ram_s1_translator_avalon_universal_slave_0_agent_rp_valid; // RAM_s1_translator_avalon_universal_slave_0_agent:rp_valid -> id_router:sink_valid
wire ram_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket; // RAM_s1_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router:sink_startofpacket
wire [91:0] ram_s1_translator_avalon_universal_slave_0_agent_rp_data; // RAM_s1_translator_avalon_universal_slave_0_agent:rp_data -> id_router:sink_data
wire ram_s1_translator_avalon_universal_slave_0_agent_rp_ready; // id_router:sink_ready -> RAM_s1_translator_avalon_universal_slave_0_agent:rp_ready
wire jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rp_endofpacket; // jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_001:sink_endofpacket
wire jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rp_valid; // jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_001:sink_valid
wire jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rp_startofpacket; // jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_001:sink_startofpacket
wire [91:0] jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rp_data; // jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rp_data -> id_router_001:sink_data
wire jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rp_ready; // id_router_001:sink_ready -> jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rp_ready
wire sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rp_endofpacket; // sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_002:sink_endofpacket
wire sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rp_valid; // sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_002:sink_valid
wire sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rp_startofpacket; // sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_002:sink_startofpacket
wire [91:0] sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rp_data; // sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:rp_data -> id_router_002:sink_data
wire sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rp_ready; // id_router_002:sink_ready -> sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:rp_ready
wire nios_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_endofpacket; // NIOS_jtag_debug_module_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_003:sink_endofpacket
wire nios_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_valid; // NIOS_jtag_debug_module_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_003:sink_valid
wire nios_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_startofpacket; // NIOS_jtag_debug_module_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_003:sink_startofpacket
wire [91:0] nios_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_data; // NIOS_jtag_debug_module_translator_avalon_universal_slave_0_agent:rp_data -> id_router_003:sink_data
wire nios_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_ready; // id_router_003:sink_ready -> NIOS_jtag_debug_module_translator_avalon_universal_slave_0_agent:rp_ready
wire hw_ann_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_endofpacket; // hw_ann_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_004:sink_endofpacket
wire hw_ann_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_valid; // hw_ann_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_004:sink_valid
wire hw_ann_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_startofpacket; // hw_ann_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_004:sink_startofpacket
wire [91:0] hw_ann_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_data; // hw_ann_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rp_data -> id_router_004:sink_data
wire hw_ann_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_ready; // id_router_004:sink_ready -> hw_ann_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rp_ready
wire lfsr_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_endofpacket; // lfsr_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_005:sink_endofpacket
wire lfsr_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_valid; // lfsr_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_005:sink_valid
wire lfsr_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_startofpacket; // lfsr_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_005:sink_startofpacket
wire [91:0] lfsr_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_data; // lfsr_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rp_data -> id_router_005:sink_data
wire lfsr_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_ready; // id_router_005:sink_ready -> lfsr_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:rp_ready
wire addr_router_001_src_endofpacket; // addr_router_001:src_endofpacket -> limiter:cmd_sink_endofpacket
wire addr_router_001_src_valid; // addr_router_001:src_valid -> limiter:cmd_sink_valid
wire addr_router_001_src_startofpacket; // addr_router_001:src_startofpacket -> limiter:cmd_sink_startofpacket
wire [91:0] addr_router_001_src_data; // addr_router_001:src_data -> limiter:cmd_sink_data
wire [5:0] addr_router_001_src_channel; // addr_router_001:src_channel -> limiter:cmd_sink_channel
wire addr_router_001_src_ready; // limiter:cmd_sink_ready -> addr_router_001:src_ready
wire limiter_rsp_src_endofpacket; // limiter:rsp_src_endofpacket -> NIOS_instruction_master_translator_avalon_universal_master_0_agent:rp_endofpacket
wire limiter_rsp_src_valid; // limiter:rsp_src_valid -> NIOS_instruction_master_translator_avalon_universal_master_0_agent:rp_valid
wire limiter_rsp_src_startofpacket; // limiter:rsp_src_startofpacket -> NIOS_instruction_master_translator_avalon_universal_master_0_agent:rp_startofpacket
wire [91:0] limiter_rsp_src_data; // limiter:rsp_src_data -> NIOS_instruction_master_translator_avalon_universal_master_0_agent:rp_data
wire [5:0] limiter_rsp_src_channel; // limiter:rsp_src_channel -> NIOS_instruction_master_translator_avalon_universal_master_0_agent:rp_channel
wire limiter_rsp_src_ready; // NIOS_instruction_master_translator_avalon_universal_master_0_agent:rp_ready -> limiter:rsp_src_ready
wire rst_controller_reset_out_reset; // rst_controller:reset_out -> [NIOS:reset_n, NIOS_data_master_translator:reset, NIOS_data_master_translator_avalon_universal_master_0_agent:reset, NIOS_instruction_master_translator:reset, NIOS_instruction_master_translator_avalon_universal_master_0_agent:reset, NIOS_jtag_debug_module_translator:reset, NIOS_jtag_debug_module_translator_avalon_universal_slave_0_agent:reset, NIOS_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, RAM:reset, RAM_s1_translator:reset, RAM_s1_translator_avalon_universal_slave_0_agent:reset, RAM_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, addr_router:reset, addr_router_001:reset, cmd_xbar_demux:reset, cmd_xbar_demux_001:reset, cmd_xbar_mux:reset, cmd_xbar_mux_003:reset, cmd_xbar_mux_004:reset, cmd_xbar_mux_005:reset, hw_ann_0:MasterReset, hw_ann_0_avalon_slave_0_translator:reset, hw_ann_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:reset, hw_ann_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, id_router:reset, id_router_001:reset, id_router_002:reset, id_router_003:reset, id_router_004:reset, id_router_005:reset, irq_mapper:reset, jtag_uart_0:rst_n, jtag_uart_0_avalon_jtag_slave_translator:reset, jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:reset, jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, lfsr_0:rst, lfsr_0_avalon_slave_0_translator:reset, lfsr_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:reset, lfsr_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, limiter:reset, rsp_xbar_demux:reset, rsp_xbar_demux_001:reset, rsp_xbar_demux_002:reset, rsp_xbar_demux_003:reset, rsp_xbar_demux_004:reset, rsp_xbar_demux_005:reset, rsp_xbar_mux:reset, rsp_xbar_mux_001:reset, sysid_qsys_0:reset_n, sysid_qsys_0_control_slave_translator:reset, sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:reset, sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:reset]
wire rst_controller_reset_out_reset_req; // rst_controller:reset_req -> RAM:reset_req
wire cmd_xbar_demux_src0_endofpacket; // cmd_xbar_demux:src0_endofpacket -> cmd_xbar_mux:sink0_endofpacket
wire cmd_xbar_demux_src0_valid; // cmd_xbar_demux:src0_valid -> cmd_xbar_mux:sink0_valid
wire cmd_xbar_demux_src0_startofpacket; // cmd_xbar_demux:src0_startofpacket -> cmd_xbar_mux:sink0_startofpacket
wire [91:0] cmd_xbar_demux_src0_data; // cmd_xbar_demux:src0_data -> cmd_xbar_mux:sink0_data
wire [5:0] cmd_xbar_demux_src0_channel; // cmd_xbar_demux:src0_channel -> cmd_xbar_mux:sink0_channel
wire cmd_xbar_demux_src0_ready; // cmd_xbar_mux:sink0_ready -> cmd_xbar_demux:src0_ready
wire cmd_xbar_demux_src1_endofpacket; // cmd_xbar_demux:src1_endofpacket -> jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:cp_endofpacket
wire cmd_xbar_demux_src1_valid; // cmd_xbar_demux:src1_valid -> jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:cp_valid
wire cmd_xbar_demux_src1_startofpacket; // cmd_xbar_demux:src1_startofpacket -> jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:cp_startofpacket
wire [91:0] cmd_xbar_demux_src1_data; // cmd_xbar_demux:src1_data -> jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:cp_data
wire [5:0] cmd_xbar_demux_src1_channel; // cmd_xbar_demux:src1_channel -> jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:cp_channel
wire cmd_xbar_demux_src2_endofpacket; // cmd_xbar_demux:src2_endofpacket -> sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:cp_endofpacket
wire cmd_xbar_demux_src2_valid; // cmd_xbar_demux:src2_valid -> sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:cp_valid
wire cmd_xbar_demux_src2_startofpacket; // cmd_xbar_demux:src2_startofpacket -> sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:cp_startofpacket
wire [91:0] cmd_xbar_demux_src2_data; // cmd_xbar_demux:src2_data -> sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:cp_data
wire [5:0] cmd_xbar_demux_src2_channel; // cmd_xbar_demux:src2_channel -> sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:cp_channel
wire cmd_xbar_demux_src3_endofpacket; // cmd_xbar_demux:src3_endofpacket -> cmd_xbar_mux_003:sink0_endofpacket
wire cmd_xbar_demux_src3_valid; // cmd_xbar_demux:src3_valid -> cmd_xbar_mux_003:sink0_valid
wire cmd_xbar_demux_src3_startofpacket; // cmd_xbar_demux:src3_startofpacket -> cmd_xbar_mux_003:sink0_startofpacket
wire [91:0] cmd_xbar_demux_src3_data; // cmd_xbar_demux:src3_data -> cmd_xbar_mux_003:sink0_data
wire [5:0] cmd_xbar_demux_src3_channel; // cmd_xbar_demux:src3_channel -> cmd_xbar_mux_003:sink0_channel
wire cmd_xbar_demux_src3_ready; // cmd_xbar_mux_003:sink0_ready -> cmd_xbar_demux:src3_ready
wire cmd_xbar_demux_src4_endofpacket; // cmd_xbar_demux:src4_endofpacket -> cmd_xbar_mux_004:sink0_endofpacket
wire cmd_xbar_demux_src4_valid; // cmd_xbar_demux:src4_valid -> cmd_xbar_mux_004:sink0_valid
wire cmd_xbar_demux_src4_startofpacket; // cmd_xbar_demux:src4_startofpacket -> cmd_xbar_mux_004:sink0_startofpacket
wire [91:0] cmd_xbar_demux_src4_data; // cmd_xbar_demux:src4_data -> cmd_xbar_mux_004:sink0_data
wire [5:0] cmd_xbar_demux_src4_channel; // cmd_xbar_demux:src4_channel -> cmd_xbar_mux_004:sink0_channel
wire cmd_xbar_demux_src4_ready; // cmd_xbar_mux_004:sink0_ready -> cmd_xbar_demux:src4_ready
wire cmd_xbar_demux_src5_endofpacket; // cmd_xbar_demux:src5_endofpacket -> cmd_xbar_mux_005:sink0_endofpacket
wire cmd_xbar_demux_src5_valid; // cmd_xbar_demux:src5_valid -> cmd_xbar_mux_005:sink0_valid
wire cmd_xbar_demux_src5_startofpacket; // cmd_xbar_demux:src5_startofpacket -> cmd_xbar_mux_005:sink0_startofpacket
wire [91:0] cmd_xbar_demux_src5_data; // cmd_xbar_demux:src5_data -> cmd_xbar_mux_005:sink0_data
wire [5:0] cmd_xbar_demux_src5_channel; // cmd_xbar_demux:src5_channel -> cmd_xbar_mux_005:sink0_channel
wire cmd_xbar_demux_src5_ready; // cmd_xbar_mux_005:sink0_ready -> cmd_xbar_demux:src5_ready
wire cmd_xbar_demux_001_src0_endofpacket; // cmd_xbar_demux_001:src0_endofpacket -> cmd_xbar_mux:sink1_endofpacket
wire cmd_xbar_demux_001_src0_valid; // cmd_xbar_demux_001:src0_valid -> cmd_xbar_mux:sink1_valid
wire cmd_xbar_demux_001_src0_startofpacket; // cmd_xbar_demux_001:src0_startofpacket -> cmd_xbar_mux:sink1_startofpacket
wire [91:0] cmd_xbar_demux_001_src0_data; // cmd_xbar_demux_001:src0_data -> cmd_xbar_mux:sink1_data
wire [5:0] cmd_xbar_demux_001_src0_channel; // cmd_xbar_demux_001:src0_channel -> cmd_xbar_mux:sink1_channel
wire cmd_xbar_demux_001_src0_ready; // cmd_xbar_mux:sink1_ready -> cmd_xbar_demux_001:src0_ready
wire cmd_xbar_demux_001_src1_endofpacket; // cmd_xbar_demux_001:src1_endofpacket -> cmd_xbar_mux_003:sink1_endofpacket
wire cmd_xbar_demux_001_src1_valid; // cmd_xbar_demux_001:src1_valid -> cmd_xbar_mux_003:sink1_valid
wire cmd_xbar_demux_001_src1_startofpacket; // cmd_xbar_demux_001:src1_startofpacket -> cmd_xbar_mux_003:sink1_startofpacket
wire [91:0] cmd_xbar_demux_001_src1_data; // cmd_xbar_demux_001:src1_data -> cmd_xbar_mux_003:sink1_data
wire [5:0] cmd_xbar_demux_001_src1_channel; // cmd_xbar_demux_001:src1_channel -> cmd_xbar_mux_003:sink1_channel
wire cmd_xbar_demux_001_src1_ready; // cmd_xbar_mux_003:sink1_ready -> cmd_xbar_demux_001:src1_ready
wire cmd_xbar_demux_001_src2_endofpacket; // cmd_xbar_demux_001:src2_endofpacket -> cmd_xbar_mux_004:sink1_endofpacket
wire cmd_xbar_demux_001_src2_valid; // cmd_xbar_demux_001:src2_valid -> cmd_xbar_mux_004:sink1_valid
wire cmd_xbar_demux_001_src2_startofpacket; // cmd_xbar_demux_001:src2_startofpacket -> cmd_xbar_mux_004:sink1_startofpacket
wire [91:0] cmd_xbar_demux_001_src2_data; // cmd_xbar_demux_001:src2_data -> cmd_xbar_mux_004:sink1_data
wire [5:0] cmd_xbar_demux_001_src2_channel; // cmd_xbar_demux_001:src2_channel -> cmd_xbar_mux_004:sink1_channel
wire cmd_xbar_demux_001_src2_ready; // cmd_xbar_mux_004:sink1_ready -> cmd_xbar_demux_001:src2_ready
wire cmd_xbar_demux_001_src3_endofpacket; // cmd_xbar_demux_001:src3_endofpacket -> cmd_xbar_mux_005:sink1_endofpacket
wire cmd_xbar_demux_001_src3_valid; // cmd_xbar_demux_001:src3_valid -> cmd_xbar_mux_005:sink1_valid
wire cmd_xbar_demux_001_src3_startofpacket; // cmd_xbar_demux_001:src3_startofpacket -> cmd_xbar_mux_005:sink1_startofpacket
wire [91:0] cmd_xbar_demux_001_src3_data; // cmd_xbar_demux_001:src3_data -> cmd_xbar_mux_005:sink1_data
wire [5:0] cmd_xbar_demux_001_src3_channel; // cmd_xbar_demux_001:src3_channel -> cmd_xbar_mux_005:sink1_channel
wire cmd_xbar_demux_001_src3_ready; // cmd_xbar_mux_005:sink1_ready -> cmd_xbar_demux_001:src3_ready
wire rsp_xbar_demux_src0_endofpacket; // rsp_xbar_demux:src0_endofpacket -> rsp_xbar_mux:sink0_endofpacket
wire rsp_xbar_demux_src0_valid; // rsp_xbar_demux:src0_valid -> rsp_xbar_mux:sink0_valid
wire rsp_xbar_demux_src0_startofpacket; // rsp_xbar_demux:src0_startofpacket -> rsp_xbar_mux:sink0_startofpacket
wire [91:0] rsp_xbar_demux_src0_data; // rsp_xbar_demux:src0_data -> rsp_xbar_mux:sink0_data
wire [5:0] rsp_xbar_demux_src0_channel; // rsp_xbar_demux:src0_channel -> rsp_xbar_mux:sink0_channel
wire rsp_xbar_demux_src0_ready; // rsp_xbar_mux:sink0_ready -> rsp_xbar_demux:src0_ready
wire rsp_xbar_demux_src1_endofpacket; // rsp_xbar_demux:src1_endofpacket -> rsp_xbar_mux_001:sink0_endofpacket
wire rsp_xbar_demux_src1_valid; // rsp_xbar_demux:src1_valid -> rsp_xbar_mux_001:sink0_valid
wire rsp_xbar_demux_src1_startofpacket; // rsp_xbar_demux:src1_startofpacket -> rsp_xbar_mux_001:sink0_startofpacket
wire [91:0] rsp_xbar_demux_src1_data; // rsp_xbar_demux:src1_data -> rsp_xbar_mux_001:sink0_data
wire [5:0] rsp_xbar_demux_src1_channel; // rsp_xbar_demux:src1_channel -> rsp_xbar_mux_001:sink0_channel
wire rsp_xbar_demux_src1_ready; // rsp_xbar_mux_001:sink0_ready -> rsp_xbar_demux:src1_ready
wire rsp_xbar_demux_001_src0_endofpacket; // rsp_xbar_demux_001:src0_endofpacket -> rsp_xbar_mux:sink1_endofpacket
wire rsp_xbar_demux_001_src0_valid; // rsp_xbar_demux_001:src0_valid -> rsp_xbar_mux:sink1_valid
wire rsp_xbar_demux_001_src0_startofpacket; // rsp_xbar_demux_001:src0_startofpacket -> rsp_xbar_mux:sink1_startofpacket
wire [91:0] rsp_xbar_demux_001_src0_data; // rsp_xbar_demux_001:src0_data -> rsp_xbar_mux:sink1_data
wire [5:0] rsp_xbar_demux_001_src0_channel; // rsp_xbar_demux_001:src0_channel -> rsp_xbar_mux:sink1_channel
wire rsp_xbar_demux_001_src0_ready; // rsp_xbar_mux:sink1_ready -> rsp_xbar_demux_001:src0_ready
wire rsp_xbar_demux_002_src0_endofpacket; // rsp_xbar_demux_002:src0_endofpacket -> rsp_xbar_mux:sink2_endofpacket
wire rsp_xbar_demux_002_src0_valid; // rsp_xbar_demux_002:src0_valid -> rsp_xbar_mux:sink2_valid
wire rsp_xbar_demux_002_src0_startofpacket; // rsp_xbar_demux_002:src0_startofpacket -> rsp_xbar_mux:sink2_startofpacket
wire [91:0] rsp_xbar_demux_002_src0_data; // rsp_xbar_demux_002:src0_data -> rsp_xbar_mux:sink2_data
wire [5:0] rsp_xbar_demux_002_src0_channel; // rsp_xbar_demux_002:src0_channel -> rsp_xbar_mux:sink2_channel
wire rsp_xbar_demux_002_src0_ready; // rsp_xbar_mux:sink2_ready -> rsp_xbar_demux_002:src0_ready
wire rsp_xbar_demux_003_src0_endofpacket; // rsp_xbar_demux_003:src0_endofpacket -> rsp_xbar_mux:sink3_endofpacket
wire rsp_xbar_demux_003_src0_valid; // rsp_xbar_demux_003:src0_valid -> rsp_xbar_mux:sink3_valid
wire rsp_xbar_demux_003_src0_startofpacket; // rsp_xbar_demux_003:src0_startofpacket -> rsp_xbar_mux:sink3_startofpacket
wire [91:0] rsp_xbar_demux_003_src0_data; // rsp_xbar_demux_003:src0_data -> rsp_xbar_mux:sink3_data
wire [5:0] rsp_xbar_demux_003_src0_channel; // rsp_xbar_demux_003:src0_channel -> rsp_xbar_mux:sink3_channel
wire rsp_xbar_demux_003_src0_ready; // rsp_xbar_mux:sink3_ready -> rsp_xbar_demux_003:src0_ready
wire rsp_xbar_demux_003_src1_endofpacket; // rsp_xbar_demux_003:src1_endofpacket -> rsp_xbar_mux_001:sink1_endofpacket
wire rsp_xbar_demux_003_src1_valid; // rsp_xbar_demux_003:src1_valid -> rsp_xbar_mux_001:sink1_valid
wire rsp_xbar_demux_003_src1_startofpacket; // rsp_xbar_demux_003:src1_startofpacket -> rsp_xbar_mux_001:sink1_startofpacket
wire [91:0] rsp_xbar_demux_003_src1_data; // rsp_xbar_demux_003:src1_data -> rsp_xbar_mux_001:sink1_data
wire [5:0] rsp_xbar_demux_003_src1_channel; // rsp_xbar_demux_003:src1_channel -> rsp_xbar_mux_001:sink1_channel
wire rsp_xbar_demux_003_src1_ready; // rsp_xbar_mux_001:sink1_ready -> rsp_xbar_demux_003:src1_ready
wire rsp_xbar_demux_004_src0_endofpacket; // rsp_xbar_demux_004:src0_endofpacket -> rsp_xbar_mux:sink4_endofpacket
wire rsp_xbar_demux_004_src0_valid; // rsp_xbar_demux_004:src0_valid -> rsp_xbar_mux:sink4_valid
wire rsp_xbar_demux_004_src0_startofpacket; // rsp_xbar_demux_004:src0_startofpacket -> rsp_xbar_mux:sink4_startofpacket
wire [91:0] rsp_xbar_demux_004_src0_data; // rsp_xbar_demux_004:src0_data -> rsp_xbar_mux:sink4_data
wire [5:0] rsp_xbar_demux_004_src0_channel; // rsp_xbar_demux_004:src0_channel -> rsp_xbar_mux:sink4_channel
wire rsp_xbar_demux_004_src0_ready; // rsp_xbar_mux:sink4_ready -> rsp_xbar_demux_004:src0_ready
wire rsp_xbar_demux_004_src1_endofpacket; // rsp_xbar_demux_004:src1_endofpacket -> rsp_xbar_mux_001:sink2_endofpacket
wire rsp_xbar_demux_004_src1_valid; // rsp_xbar_demux_004:src1_valid -> rsp_xbar_mux_001:sink2_valid
wire rsp_xbar_demux_004_src1_startofpacket; // rsp_xbar_demux_004:src1_startofpacket -> rsp_xbar_mux_001:sink2_startofpacket
wire [91:0] rsp_xbar_demux_004_src1_data; // rsp_xbar_demux_004:src1_data -> rsp_xbar_mux_001:sink2_data
wire [5:0] rsp_xbar_demux_004_src1_channel; // rsp_xbar_demux_004:src1_channel -> rsp_xbar_mux_001:sink2_channel
wire rsp_xbar_demux_004_src1_ready; // rsp_xbar_mux_001:sink2_ready -> rsp_xbar_demux_004:src1_ready
wire rsp_xbar_demux_005_src0_endofpacket; // rsp_xbar_demux_005:src0_endofpacket -> rsp_xbar_mux:sink5_endofpacket
wire rsp_xbar_demux_005_src0_valid; // rsp_xbar_demux_005:src0_valid -> rsp_xbar_mux:sink5_valid
wire rsp_xbar_demux_005_src0_startofpacket; // rsp_xbar_demux_005:src0_startofpacket -> rsp_xbar_mux:sink5_startofpacket
wire [91:0] rsp_xbar_demux_005_src0_data; // rsp_xbar_demux_005:src0_data -> rsp_xbar_mux:sink5_data
wire [5:0] rsp_xbar_demux_005_src0_channel; // rsp_xbar_demux_005:src0_channel -> rsp_xbar_mux:sink5_channel
wire rsp_xbar_demux_005_src0_ready; // rsp_xbar_mux:sink5_ready -> rsp_xbar_demux_005:src0_ready
wire rsp_xbar_demux_005_src1_endofpacket; // rsp_xbar_demux_005:src1_endofpacket -> rsp_xbar_mux_001:sink3_endofpacket
wire rsp_xbar_demux_005_src1_valid; // rsp_xbar_demux_005:src1_valid -> rsp_xbar_mux_001:sink3_valid
wire rsp_xbar_demux_005_src1_startofpacket; // rsp_xbar_demux_005:src1_startofpacket -> rsp_xbar_mux_001:sink3_startofpacket
wire [91:0] rsp_xbar_demux_005_src1_data; // rsp_xbar_demux_005:src1_data -> rsp_xbar_mux_001:sink3_data
wire [5:0] rsp_xbar_demux_005_src1_channel; // rsp_xbar_demux_005:src1_channel -> rsp_xbar_mux_001:sink3_channel
wire rsp_xbar_demux_005_src1_ready; // rsp_xbar_mux_001:sink3_ready -> rsp_xbar_demux_005:src1_ready
wire addr_router_src_endofpacket; // addr_router:src_endofpacket -> cmd_xbar_demux:sink_endofpacket
wire addr_router_src_valid; // addr_router:src_valid -> cmd_xbar_demux:sink_valid
wire addr_router_src_startofpacket; // addr_router:src_startofpacket -> cmd_xbar_demux:sink_startofpacket
wire [91:0] addr_router_src_data; // addr_router:src_data -> cmd_xbar_demux:sink_data
wire [5:0] addr_router_src_channel; // addr_router:src_channel -> cmd_xbar_demux:sink_channel
wire addr_router_src_ready; // cmd_xbar_demux:sink_ready -> addr_router:src_ready
wire rsp_xbar_mux_src_endofpacket; // rsp_xbar_mux:src_endofpacket -> NIOS_data_master_translator_avalon_universal_master_0_agent:rp_endofpacket
wire rsp_xbar_mux_src_valid; // rsp_xbar_mux:src_valid -> NIOS_data_master_translator_avalon_universal_master_0_agent:rp_valid
wire rsp_xbar_mux_src_startofpacket; // rsp_xbar_mux:src_startofpacket -> NIOS_data_master_translator_avalon_universal_master_0_agent:rp_startofpacket
wire [91:0] rsp_xbar_mux_src_data; // rsp_xbar_mux:src_data -> NIOS_data_master_translator_avalon_universal_master_0_agent:rp_data
wire [5:0] rsp_xbar_mux_src_channel; // rsp_xbar_mux:src_channel -> NIOS_data_master_translator_avalon_universal_master_0_agent:rp_channel
wire rsp_xbar_mux_src_ready; // NIOS_data_master_translator_avalon_universal_master_0_agent:rp_ready -> rsp_xbar_mux:src_ready
wire limiter_cmd_src_endofpacket; // limiter:cmd_src_endofpacket -> cmd_xbar_demux_001:sink_endofpacket
wire limiter_cmd_src_startofpacket; // limiter:cmd_src_startofpacket -> cmd_xbar_demux_001:sink_startofpacket
wire [91:0] limiter_cmd_src_data; // limiter:cmd_src_data -> cmd_xbar_demux_001:sink_data
wire [5:0] limiter_cmd_src_channel; // limiter:cmd_src_channel -> cmd_xbar_demux_001:sink_channel
wire limiter_cmd_src_ready; // cmd_xbar_demux_001:sink_ready -> limiter:cmd_src_ready
wire rsp_xbar_mux_001_src_endofpacket; // rsp_xbar_mux_001:src_endofpacket -> limiter:rsp_sink_endofpacket
wire rsp_xbar_mux_001_src_valid; // rsp_xbar_mux_001:src_valid -> limiter:rsp_sink_valid
wire rsp_xbar_mux_001_src_startofpacket; // rsp_xbar_mux_001:src_startofpacket -> limiter:rsp_sink_startofpacket
wire [91:0] rsp_xbar_mux_001_src_data; // rsp_xbar_mux_001:src_data -> limiter:rsp_sink_data
wire [5:0] rsp_xbar_mux_001_src_channel; // rsp_xbar_mux_001:src_channel -> limiter:rsp_sink_channel
wire rsp_xbar_mux_001_src_ready; // limiter:rsp_sink_ready -> rsp_xbar_mux_001:src_ready
wire cmd_xbar_mux_src_endofpacket; // cmd_xbar_mux:src_endofpacket -> RAM_s1_translator_avalon_universal_slave_0_agent:cp_endofpacket
wire cmd_xbar_mux_src_valid; // cmd_xbar_mux:src_valid -> RAM_s1_translator_avalon_universal_slave_0_agent:cp_valid
wire cmd_xbar_mux_src_startofpacket; // cmd_xbar_mux:src_startofpacket -> RAM_s1_translator_avalon_universal_slave_0_agent:cp_startofpacket
wire [91:0] cmd_xbar_mux_src_data; // cmd_xbar_mux:src_data -> RAM_s1_translator_avalon_universal_slave_0_agent:cp_data
wire [5:0] cmd_xbar_mux_src_channel; // cmd_xbar_mux:src_channel -> RAM_s1_translator_avalon_universal_slave_0_agent:cp_channel
wire cmd_xbar_mux_src_ready; // RAM_s1_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_mux:src_ready
wire id_router_src_endofpacket; // id_router:src_endofpacket -> rsp_xbar_demux:sink_endofpacket
wire id_router_src_valid; // id_router:src_valid -> rsp_xbar_demux:sink_valid
wire id_router_src_startofpacket; // id_router:src_startofpacket -> rsp_xbar_demux:sink_startofpacket
wire [91:0] id_router_src_data; // id_router:src_data -> rsp_xbar_demux:sink_data
wire [5:0] id_router_src_channel; // id_router:src_channel -> rsp_xbar_demux:sink_channel
wire id_router_src_ready; // rsp_xbar_demux:sink_ready -> id_router:src_ready
wire cmd_xbar_demux_src1_ready; // jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_demux:src1_ready
wire id_router_001_src_endofpacket; // id_router_001:src_endofpacket -> rsp_xbar_demux_001:sink_endofpacket
wire id_router_001_src_valid; // id_router_001:src_valid -> rsp_xbar_demux_001:sink_valid
wire id_router_001_src_startofpacket; // id_router_001:src_startofpacket -> rsp_xbar_demux_001:sink_startofpacket
wire [91:0] id_router_001_src_data; // id_router_001:src_data -> rsp_xbar_demux_001:sink_data
wire [5:0] id_router_001_src_channel; // id_router_001:src_channel -> rsp_xbar_demux_001:sink_channel
wire id_router_001_src_ready; // rsp_xbar_demux_001:sink_ready -> id_router_001:src_ready
wire cmd_xbar_demux_src2_ready; // sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_demux:src2_ready
wire id_router_002_src_endofpacket; // id_router_002:src_endofpacket -> rsp_xbar_demux_002:sink_endofpacket
wire id_router_002_src_valid; // id_router_002:src_valid -> rsp_xbar_demux_002:sink_valid
wire id_router_002_src_startofpacket; // id_router_002:src_startofpacket -> rsp_xbar_demux_002:sink_startofpacket
wire [91:0] id_router_002_src_data; // id_router_002:src_data -> rsp_xbar_demux_002:sink_data
wire [5:0] id_router_002_src_channel; // id_router_002:src_channel -> rsp_xbar_demux_002:sink_channel
wire id_router_002_src_ready; // rsp_xbar_demux_002:sink_ready -> id_router_002:src_ready
wire cmd_xbar_mux_003_src_endofpacket; // cmd_xbar_mux_003:src_endofpacket -> NIOS_jtag_debug_module_translator_avalon_universal_slave_0_agent:cp_endofpacket
wire cmd_xbar_mux_003_src_valid; // cmd_xbar_mux_003:src_valid -> NIOS_jtag_debug_module_translator_avalon_universal_slave_0_agent:cp_valid
wire cmd_xbar_mux_003_src_startofpacket; // cmd_xbar_mux_003:src_startofpacket -> NIOS_jtag_debug_module_translator_avalon_universal_slave_0_agent:cp_startofpacket
wire [91:0] cmd_xbar_mux_003_src_data; // cmd_xbar_mux_003:src_data -> NIOS_jtag_debug_module_translator_avalon_universal_slave_0_agent:cp_data
wire [5:0] cmd_xbar_mux_003_src_channel; // cmd_xbar_mux_003:src_channel -> NIOS_jtag_debug_module_translator_avalon_universal_slave_0_agent:cp_channel
wire cmd_xbar_mux_003_src_ready; // NIOS_jtag_debug_module_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_mux_003:src_ready
wire id_router_003_src_endofpacket; // id_router_003:src_endofpacket -> rsp_xbar_demux_003:sink_endofpacket
wire id_router_003_src_valid; // id_router_003:src_valid -> rsp_xbar_demux_003:sink_valid
wire id_router_003_src_startofpacket; // id_router_003:src_startofpacket -> rsp_xbar_demux_003:sink_startofpacket
wire [91:0] id_router_003_src_data; // id_router_003:src_data -> rsp_xbar_demux_003:sink_data
wire [5:0] id_router_003_src_channel; // id_router_003:src_channel -> rsp_xbar_demux_003:sink_channel
wire id_router_003_src_ready; // rsp_xbar_demux_003:sink_ready -> id_router_003:src_ready
wire cmd_xbar_mux_004_src_endofpacket; // cmd_xbar_mux_004:src_endofpacket -> hw_ann_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:cp_endofpacket
wire cmd_xbar_mux_004_src_valid; // cmd_xbar_mux_004:src_valid -> hw_ann_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:cp_valid
wire cmd_xbar_mux_004_src_startofpacket; // cmd_xbar_mux_004:src_startofpacket -> hw_ann_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:cp_startofpacket
wire [91:0] cmd_xbar_mux_004_src_data; // cmd_xbar_mux_004:src_data -> hw_ann_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:cp_data
wire [5:0] cmd_xbar_mux_004_src_channel; // cmd_xbar_mux_004:src_channel -> hw_ann_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:cp_channel
wire cmd_xbar_mux_004_src_ready; // hw_ann_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_mux_004:src_ready
wire id_router_004_src_endofpacket; // id_router_004:src_endofpacket -> rsp_xbar_demux_004:sink_endofpacket
wire id_router_004_src_valid; // id_router_004:src_valid -> rsp_xbar_demux_004:sink_valid
wire id_router_004_src_startofpacket; // id_router_004:src_startofpacket -> rsp_xbar_demux_004:sink_startofpacket
wire [91:0] id_router_004_src_data; // id_router_004:src_data -> rsp_xbar_demux_004:sink_data
wire [5:0] id_router_004_src_channel; // id_router_004:src_channel -> rsp_xbar_demux_004:sink_channel
wire id_router_004_src_ready; // rsp_xbar_demux_004:sink_ready -> id_router_004:src_ready
wire cmd_xbar_mux_005_src_endofpacket; // cmd_xbar_mux_005:src_endofpacket -> lfsr_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:cp_endofpacket
wire cmd_xbar_mux_005_src_valid; // cmd_xbar_mux_005:src_valid -> lfsr_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:cp_valid
wire cmd_xbar_mux_005_src_startofpacket; // cmd_xbar_mux_005:src_startofpacket -> lfsr_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:cp_startofpacket
wire [91:0] cmd_xbar_mux_005_src_data; // cmd_xbar_mux_005:src_data -> lfsr_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:cp_data
wire [5:0] cmd_xbar_mux_005_src_channel; // cmd_xbar_mux_005:src_channel -> lfsr_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:cp_channel
wire cmd_xbar_mux_005_src_ready; // lfsr_0_avalon_slave_0_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_mux_005:src_ready
wire id_router_005_src_endofpacket; // id_router_005:src_endofpacket -> rsp_xbar_demux_005:sink_endofpacket
wire id_router_005_src_valid; // id_router_005:src_valid -> rsp_xbar_demux_005:sink_valid
wire id_router_005_src_startofpacket; // id_router_005:src_startofpacket -> rsp_xbar_demux_005:sink_startofpacket
wire [91:0] id_router_005_src_data; // id_router_005:src_data -> rsp_xbar_demux_005:sink_data
wire [5:0] id_router_005_src_channel; // id_router_005:src_channel -> rsp_xbar_demux_005:sink_channel
wire id_router_005_src_ready; // rsp_xbar_demux_005:sink_ready -> id_router_005:src_ready
wire [5:0] limiter_cmd_valid_data; // limiter:cmd_src_valid -> cmd_xbar_demux_001:sink_valid
wire irq_mapper_receiver0_irq; // jtag_uart_0:av_irq -> irq_mapper:receiver0_irq
wire [31:0] nios_d_irq_irq; // irq_mapper:sender_irq -> NIOS:d_irq
SoC_RAM ram (
.clk (clk_clk), // clk1.clk
.address (ram_s1_translator_avalon_anti_slave_0_address), // s1.address
.clken (ram_s1_translator_avalon_anti_slave_0_clken), // .clken
.chipselect (ram_s1_translator_avalon_anti_slave_0_chipselect), // .chipselect
.write (ram_s1_translator_avalon_anti_slave_0_write), // .write
.readdata (ram_s1_translator_avalon_anti_slave_0_readdata), // .readdata
.writedata (ram_s1_translator_avalon_anti_slave_0_writedata), // .writedata
.byteenable (ram_s1_translator_avalon_anti_slave_0_byteenable), // .byteenable
.reset (rst_controller_reset_out_reset), // reset1.reset
.reset_req (rst_controller_reset_out_reset_req) // .reset_req
);
SoC_jtag_uart_0 jtag_uart_0 (
.clk (clk_clk), // clk.clk
.rst_n (~rst_controller_reset_out_reset), // reset.reset_n
.av_chipselect (jtag_uart_0_avalon_jtag_slave_translator_avalon_anti_slave_0_chipselect), // avalon_jtag_slave.chipselect
.av_address (jtag_uart_0_avalon_jtag_slave_translator_avalon_anti_slave_0_address), // .address
.av_read_n (~jtag_uart_0_avalon_jtag_slave_translator_avalon_anti_slave_0_read), // .read_n
.av_readdata (jtag_uart_0_avalon_jtag_slave_translator_avalon_anti_slave_0_readdata), // .readdata
.av_write_n (~jtag_uart_0_avalon_jtag_slave_translator_avalon_anti_slave_0_write), // .write_n
.av_writedata (jtag_uart_0_avalon_jtag_slave_translator_avalon_anti_slave_0_writedata), // .writedata
.av_waitrequest (jtag_uart_0_avalon_jtag_slave_translator_avalon_anti_slave_0_waitrequest), // .waitrequest
.av_irq (irq_mapper_receiver0_irq) // irq.irq
);
SoC_sysid_qsys_0 sysid_qsys_0 (
.clock (clk_clk), // clk.clk
.reset_n (~rst_controller_reset_out_reset), // reset.reset_n
.readdata (sysid_qsys_0_control_slave_translator_avalon_anti_slave_0_readdata), // control_slave.readdata
.address (sysid_qsys_0_control_slave_translator_avalon_anti_slave_0_address) // .address
);
SoC_NIOS nios (
.clk (clk_clk), // clk.clk
.reset_n (~rst_controller_reset_out_reset), // reset_n.reset_n
.d_address (nios_data_master_address), // data_master.address
.d_byteenable (nios_data_master_byteenable), // .byteenable
.d_read (nios_data_master_read), // .read
.d_readdata (nios_data_master_readdata), // .readdata
.d_waitrequest (nios_data_master_waitrequest), // .waitrequest
.d_write (nios_data_master_write), // .write
.d_writedata (nios_data_master_writedata), // .writedata
.jtag_debug_module_debugaccess_to_roms (nios_data_master_debugaccess), // .debugaccess
.i_address (nios_instruction_master_address), // instruction_master.address
.i_read (nios_instruction_master_read), // .read
.i_readdata (nios_instruction_master_readdata), // .readdata
.i_waitrequest (nios_instruction_master_waitrequest), // .waitrequest
.i_readdatavalid (nios_instruction_master_readdatavalid), // .readdatavalid
.d_irq (nios_d_irq_irq), // d_irq.irq
.jtag_debug_module_resetrequest (), // jtag_debug_module_reset.reset
.jtag_debug_module_address (nios_jtag_debug_module_translator_avalon_anti_slave_0_address), // jtag_debug_module.address
.jtag_debug_module_byteenable (nios_jtag_debug_module_translator_avalon_anti_slave_0_byteenable), // .byteenable
.jtag_debug_module_debugaccess (nios_jtag_debug_module_translator_avalon_anti_slave_0_debugaccess), // .debugaccess
.jtag_debug_module_read (nios_jtag_debug_module_translator_avalon_anti_slave_0_read), // .read
.jtag_debug_module_readdata (nios_jtag_debug_module_translator_avalon_anti_slave_0_readdata), // .readdata
.jtag_debug_module_waitrequest (nios_jtag_debug_module_translator_avalon_anti_slave_0_waitrequest), // .waitrequest
.jtag_debug_module_write (nios_jtag_debug_module_translator_avalon_anti_slave_0_write), // .write
.jtag_debug_module_writedata (nios_jtag_debug_module_translator_avalon_anti_slave_0_writedata), // .writedata
.no_ci_readra () // custom_instruction_master.readra
);
MainProyectoFinal #(
.Width (32),
.ConLimitador (0),
.Magnitud (7),
.Precision (24),
.Signo (1)
) hw_ann_0 (
.CLK (clk_clk), // clock.clk
.write (hw_ann_0_avalon_slave_0_translator_avalon_anti_slave_0_write), // avalon_slave_0.write
.read (hw_ann_0_avalon_slave_0_translator_avalon_anti_slave_0_read), // .read
.address (hw_ann_0_avalon_slave_0_translator_avalon_anti_slave_0_address), // .address
.writedata (hw_ann_0_avalon_slave_0_translator_avalon_anti_slave_0_writedata), // .writedata
.readdata (hw_ann_0_avalon_slave_0_translator_avalon_anti_slave_0_readdata), // .readdata
.MasterReset (~rst_controller_reset_out_reset) // reset_sink.reset_n
);
lfsr lfsr_0 (
.clk (clk_clk), // clock.clk
.read (lfsr_0_avalon_slave_0_translator_avalon_anti_slave_0_read), // avalon_slave_0.read
.read_data (lfsr_0_avalon_slave_0_translator_avalon_anti_slave_0_readdata), // .readdata
.rst (rst_controller_reset_out_reset) // reset_sink.reset
);
altera_merlin_master_translator #(
.AV_ADDRESS_W (19),
.AV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (19),
.UAV_BURSTCOUNT_W (3),
.USE_READ (1),
.USE_WRITE (1),
.USE_BEGINBURSTTRANSFER (0),
.USE_BEGINTRANSFER (0),
.USE_CHIPSELECT (0),
.USE_BURSTCOUNT (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (1),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_LINEWRAPBURSTS (0),
.AV_REGISTERINCOMINGSIGNALS (0)
) nios_data_master_translator (
.clk (clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // reset.reset
.uav_address (nios_data_master_translator_avalon_universal_master_0_address), // avalon_universal_master_0.address
.uav_burstcount (nios_data_master_translator_avalon_universal_master_0_burstcount), // .burstcount
.uav_read (nios_data_master_translator_avalon_universal_master_0_read), // .read
.uav_write (nios_data_master_translator_avalon_universal_master_0_write), // .write
.uav_waitrequest (nios_data_master_translator_avalon_universal_master_0_waitrequest), // .waitrequest
.uav_readdatavalid (nios_data_master_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
.uav_byteenable (nios_data_master_translator_avalon_universal_master_0_byteenable), // .byteenable
.uav_readdata (nios_data_master_translator_avalon_universal_master_0_readdata), // .readdata
.uav_writedata (nios_data_master_translator_avalon_universal_master_0_writedata), // .writedata
.uav_lock (nios_data_master_translator_avalon_universal_master_0_lock), // .lock
.uav_debugaccess (nios_data_master_translator_avalon_universal_master_0_debugaccess), // .debugaccess
.av_address (nios_data_master_address), // avalon_anti_master_0.address
.av_waitrequest (nios_data_master_waitrequest), // .waitrequest
.av_byteenable (nios_data_master_byteenable), // .byteenable
.av_read (nios_data_master_read), // .read
.av_readdata (nios_data_master_readdata), // .readdata
.av_write (nios_data_master_write), // .write
.av_writedata (nios_data_master_writedata), // .writedata
.av_debugaccess (nios_data_master_debugaccess), // .debugaccess
.av_burstcount (1'b1), // (terminated)
.av_beginbursttransfer (1'b0), // (terminated)
.av_begintransfer (1'b0), // (terminated)
.av_chipselect (1'b0), // (terminated)
.av_readdatavalid (), // (terminated)
.av_lock (1'b0), // (terminated)
.uav_clken (), // (terminated)
.av_clken (1'b1), // (terminated)
.uav_response (2'b00), // (terminated)
.av_response (), // (terminated)
.uav_writeresponserequest (), // (terminated)
.uav_writeresponsevalid (1'b0), // (terminated)
.av_writeresponserequest (1'b0), // (terminated)
.av_writeresponsevalid () // (terminated)
);
altera_merlin_master_translator #(
.AV_ADDRESS_W (19),
.AV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (19),
.UAV_BURSTCOUNT_W (3),
.USE_READ (1),
.USE_WRITE (0),
.USE_BEGINBURSTTRANSFER (0),
.USE_BEGINTRANSFER (0),
.USE_CHIPSELECT (0),
.USE_BURSTCOUNT (0),
.USE_READDATAVALID (1),
.USE_WAITREQUEST (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (1),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_LINEWRAPBURSTS (1),
.AV_REGISTERINCOMINGSIGNALS (0)
) nios_instruction_master_translator (
.clk (clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // reset.reset
.uav_address (nios_instruction_master_translator_avalon_universal_master_0_address), // avalon_universal_master_0.address
.uav_burstcount (nios_instruction_master_translator_avalon_universal_master_0_burstcount), // .burstcount
.uav_read (nios_instruction_master_translator_avalon_universal_master_0_read), // .read
.uav_write (nios_instruction_master_translator_avalon_universal_master_0_write), // .write
.uav_waitrequest (nios_instruction_master_translator_avalon_universal_master_0_waitrequest), // .waitrequest
.uav_readdatavalid (nios_instruction_master_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
.uav_byteenable (nios_instruction_master_translator_avalon_universal_master_0_byteenable), // .byteenable
.uav_readdata (nios_instruction_master_translator_avalon_universal_master_0_readdata), // .readdata
.uav_writedata (nios_instruction_master_translator_avalon_universal_master_0_writedata), // .writedata
.uav_lock (nios_instruction_master_translator_avalon_universal_master_0_lock), // .lock
.uav_debugaccess (nios_instruction_master_translator_avalon_universal_master_0_debugaccess), // .debugaccess
.av_address (nios_instruction_master_address), // avalon_anti_master_0.address
.av_waitrequest (nios_instruction_master_waitrequest), // .waitrequest
.av_read (nios_instruction_master_read), // .read
.av_readdata (nios_instruction_master_readdata), // .readdata
.av_readdatavalid (nios_instruction_master_readdatavalid), // .readdatavalid
.av_burstcount (1'b1), // (terminated)
.av_byteenable (4'b1111), // (terminated)
.av_beginbursttransfer (1'b0), // (terminated)
.av_begintransfer (1'b0), // (terminated)
.av_chipselect (1'b0), // (terminated)
.av_write (1'b0), // (terminated)
.av_writedata (32'b00000000000000000000000000000000), // (terminated)
.av_lock (1'b0), // (terminated)
.av_debugaccess (1'b0), // (terminated)
.uav_clken (), // (terminated)
.av_clken (1'b1), // (terminated)
.uav_response (2'b00), // (terminated)
.av_response (), // (terminated)
.uav_writeresponserequest (), // (terminated)
.uav_writeresponsevalid (1'b0), // (terminated)
.av_writeresponserequest (1'b0), // (terminated)
.av_writeresponsevalid () // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (15),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (19),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (1),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (0),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (0),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) ram_s1_translator (
.clk (clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // reset.reset
.uav_address (ram_s1_translator_avalon_universal_slave_0_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (ram_s1_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount
.uav_read (ram_s1_translator_avalon_universal_slave_0_agent_m0_read), // .read
.uav_write (ram_s1_translator_avalon_universal_slave_0_agent_m0_write), // .write
.uav_waitrequest (ram_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (ram_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (ram_s1_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable
.uav_readdata (ram_s1_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata
.uav_writedata (ram_s1_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata
.uav_lock (ram_s1_translator_avalon_universal_slave_0_agent_m0_lock), // .lock
.uav_debugaccess (ram_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess
.av_address (ram_s1_translator_avalon_anti_slave_0_address), // avalon_anti_slave_0.address
.av_write (ram_s1_translator_avalon_anti_slave_0_write), // .write
.av_readdata (ram_s1_translator_avalon_anti_slave_0_readdata), // .readdata
.av_writedata (ram_s1_translator_avalon_anti_slave_0_writedata), // .writedata
.av_byteenable (ram_s1_translator_avalon_anti_slave_0_byteenable), // .byteenable
.av_chipselect (ram_s1_translator_avalon_anti_slave_0_chipselect), // .chipselect
.av_clken (ram_s1_translator_avalon_anti_slave_0_clken), // .clken
.av_read (), // (terminated)
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_waitrequest (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponserequest (1'b0), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponserequest (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (1),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (1),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (19),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (1),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) jtag_uart_0_avalon_jtag_slave_translator (
.clk (clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // reset.reset
.uav_address (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount
.uav_read (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_read), // .read
.uav_write (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_write), // .write
.uav_waitrequest (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable
.uav_readdata (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata
.uav_writedata (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata
.uav_lock (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_lock), // .lock
.uav_debugaccess (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess
.av_address (jtag_uart_0_avalon_jtag_slave_translator_avalon_anti_slave_0_address), // avalon_anti_slave_0.address
.av_write (jtag_uart_0_avalon_jtag_slave_translator_avalon_anti_slave_0_write), // .write
.av_read (jtag_uart_0_avalon_jtag_slave_translator_avalon_anti_slave_0_read), // .read
.av_readdata (jtag_uart_0_avalon_jtag_slave_translator_avalon_anti_slave_0_readdata), // .readdata
.av_writedata (jtag_uart_0_avalon_jtag_slave_translator_avalon_anti_slave_0_writedata), // .writedata
.av_waitrequest (jtag_uart_0_avalon_jtag_slave_translator_avalon_anti_slave_0_waitrequest), // .waitrequest
.av_chipselect (jtag_uart_0_avalon_jtag_slave_translator_avalon_anti_slave_0_chipselect), // .chipselect
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_byteenable (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponserequest (1'b0), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponserequest (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (1),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (19),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (0),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) sysid_qsys_0_control_slave_translator (
.clk (clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // reset.reset
.uav_address (sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount
.uav_read (sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_read), // .read
.uav_write (sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_write), // .write
.uav_waitrequest (sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable
.uav_readdata (sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata
.uav_writedata (sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata
.uav_lock (sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_lock), // .lock
.uav_debugaccess (sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess
.av_address (sysid_qsys_0_control_slave_translator_avalon_anti_slave_0_address), // avalon_anti_slave_0.address
.av_readdata (sysid_qsys_0_control_slave_translator_avalon_anti_slave_0_readdata), // .readdata
.av_write (), // (terminated)
.av_read (), // (terminated)
.av_writedata (), // (terminated)
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_byteenable (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_waitrequest (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_chipselect (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponserequest (1'b0), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponserequest (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (9),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (19),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (1),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) nios_jtag_debug_module_translator (
.clk (clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // reset.reset
.uav_address (nios_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (nios_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount
.uav_read (nios_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_read), // .read
.uav_write (nios_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_write), // .write
.uav_waitrequest (nios_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (nios_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (nios_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable
.uav_readdata (nios_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata
.uav_writedata (nios_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata
.uav_lock (nios_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_lock), // .lock
.uav_debugaccess (nios_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess
.av_address (nios_jtag_debug_module_translator_avalon_anti_slave_0_address), // avalon_anti_slave_0.address
.av_write (nios_jtag_debug_module_translator_avalon_anti_slave_0_write), // .write
.av_read (nios_jtag_debug_module_translator_avalon_anti_slave_0_read), // .read
.av_readdata (nios_jtag_debug_module_translator_avalon_anti_slave_0_readdata), // .readdata
.av_writedata (nios_jtag_debug_module_translator_avalon_anti_slave_0_writedata), // .writedata
.av_byteenable (nios_jtag_debug_module_translator_avalon_anti_slave_0_byteenable), // .byteenable
.av_waitrequest (nios_jtag_debug_module_translator_avalon_anti_slave_0_waitrequest), // .waitrequest
.av_debugaccess (nios_jtag_debug_module_translator_avalon_anti_slave_0_debugaccess), // .debugaccess
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_chipselect (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponserequest (1'b0), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponserequest (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (9),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (19),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (0),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) hw_ann_0_avalon_slave_0_translator (
.clk (clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // reset.reset
.uav_address (hw_ann_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (hw_ann_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount
.uav_read (hw_ann_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_read), // .read
.uav_write (hw_ann_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_write), // .write
.uav_waitrequest (hw_ann_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (hw_ann_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (hw_ann_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable
.uav_readdata (hw_ann_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata
.uav_writedata (hw_ann_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata
.uav_lock (hw_ann_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_lock), // .lock
.uav_debugaccess (hw_ann_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess
.av_address (hw_ann_0_avalon_slave_0_translator_avalon_anti_slave_0_address), // avalon_anti_slave_0.address
.av_write (hw_ann_0_avalon_slave_0_translator_avalon_anti_slave_0_write), // .write
.av_read (hw_ann_0_avalon_slave_0_translator_avalon_anti_slave_0_read), // .read
.av_readdata (hw_ann_0_avalon_slave_0_translator_avalon_anti_slave_0_readdata), // .readdata
.av_writedata (hw_ann_0_avalon_slave_0_translator_avalon_anti_slave_0_writedata), // .writedata
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_byteenable (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_waitrequest (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_chipselect (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponserequest (1'b0), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponserequest (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (1),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (19),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (0),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) lfsr_0_avalon_slave_0_translator (
.clk (clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // reset.reset
.uav_address (lfsr_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (lfsr_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount
.uav_read (lfsr_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_read), // .read
.uav_write (lfsr_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_write), // .write
.uav_waitrequest (lfsr_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (lfsr_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (lfsr_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable
.uav_readdata (lfsr_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata
.uav_writedata (lfsr_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata
.uav_lock (lfsr_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_lock), // .lock
.uav_debugaccess (lfsr_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess
.av_read (lfsr_0_avalon_slave_0_translator_avalon_anti_slave_0_read), // avalon_anti_slave_0.read
.av_readdata (lfsr_0_avalon_slave_0_translator_avalon_anti_slave_0_readdata), // .readdata
.av_address (), // (terminated)
.av_write (), // (terminated)
.av_writedata (), // (terminated)
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_byteenable (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_waitrequest (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_chipselect (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponserequest (1'b0), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponserequest (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_master_agent #(
.PKT_PROTECTION_H (85),
.PKT_PROTECTION_L (83),
.PKT_BEGIN_BURST (74),
.PKT_BURSTWRAP_H (66),
.PKT_BURSTWRAP_L (64),
.PKT_BURST_SIZE_H (69),
.PKT_BURST_SIZE_L (67),
.PKT_BURST_TYPE_H (71),
.PKT_BURST_TYPE_L (70),
.PKT_BYTE_CNT_H (63),
.PKT_BYTE_CNT_L (61),
.PKT_ADDR_H (54),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (55),
.PKT_TRANS_POSTED (56),
.PKT_TRANS_WRITE (57),
.PKT_TRANS_READ (58),
.PKT_TRANS_LOCK (59),
.PKT_TRANS_EXCLUSIVE (60),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (78),
.PKT_SRC_ID_L (76),
.PKT_DEST_ID_H (81),
.PKT_DEST_ID_L (79),
.PKT_THREAD_ID_H (82),
.PKT_THREAD_ID_L (82),
.PKT_CACHE_H (89),
.PKT_CACHE_L (86),
.PKT_DATA_SIDEBAND_H (73),
.PKT_DATA_SIDEBAND_L (73),
.PKT_QOS_H (75),
.PKT_QOS_L (75),
.PKT_ADDR_SIDEBAND_H (72),
.PKT_ADDR_SIDEBAND_L (72),
.PKT_RESPONSE_STATUS_H (91),
.PKT_RESPONSE_STATUS_L (90),
.ST_DATA_W (92),
.ST_CHANNEL_W (6),
.AV_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_RSP (0),
.ID (0),
.BURSTWRAP_VALUE (7),
.CACHE_VALUE (0),
.SECURE_ACCESS_BIT (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) nios_data_master_translator_avalon_universal_master_0_agent (
.clk (clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.av_address (nios_data_master_translator_avalon_universal_master_0_address), // av.address
.av_write (nios_data_master_translator_avalon_universal_master_0_write), // .write
.av_read (nios_data_master_translator_avalon_universal_master_0_read), // .read
.av_writedata (nios_data_master_translator_avalon_universal_master_0_writedata), // .writedata
.av_readdata (nios_data_master_translator_avalon_universal_master_0_readdata), // .readdata
.av_waitrequest (nios_data_master_translator_avalon_universal_master_0_waitrequest), // .waitrequest
.av_readdatavalid (nios_data_master_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
.av_byteenable (nios_data_master_translator_avalon_universal_master_0_byteenable), // .byteenable
.av_burstcount (nios_data_master_translator_avalon_universal_master_0_burstcount), // .burstcount
.av_debugaccess (nios_data_master_translator_avalon_universal_master_0_debugaccess), // .debugaccess
.av_lock (nios_data_master_translator_avalon_universal_master_0_lock), // .lock
.cp_valid (nios_data_master_translator_avalon_universal_master_0_agent_cp_valid), // cp.valid
.cp_data (nios_data_master_translator_avalon_universal_master_0_agent_cp_data), // .data
.cp_startofpacket (nios_data_master_translator_avalon_universal_master_0_agent_cp_startofpacket), // .startofpacket
.cp_endofpacket (nios_data_master_translator_avalon_universal_master_0_agent_cp_endofpacket), // .endofpacket
.cp_ready (nios_data_master_translator_avalon_universal_master_0_agent_cp_ready), // .ready
.rp_valid (rsp_xbar_mux_src_valid), // rp.valid
.rp_data (rsp_xbar_mux_src_data), // .data
.rp_channel (rsp_xbar_mux_src_channel), // .channel
.rp_startofpacket (rsp_xbar_mux_src_startofpacket), // .startofpacket
.rp_endofpacket (rsp_xbar_mux_src_endofpacket), // .endofpacket
.rp_ready (rsp_xbar_mux_src_ready), // .ready
.av_response (), // (terminated)
.av_writeresponserequest (1'b0), // (terminated)
.av_writeresponsevalid () // (terminated)
);
altera_merlin_master_agent #(
.PKT_PROTECTION_H (85),
.PKT_PROTECTION_L (83),
.PKT_BEGIN_BURST (74),
.PKT_BURSTWRAP_H (66),
.PKT_BURSTWRAP_L (64),
.PKT_BURST_SIZE_H (69),
.PKT_BURST_SIZE_L (67),
.PKT_BURST_TYPE_H (71),
.PKT_BURST_TYPE_L (70),
.PKT_BYTE_CNT_H (63),
.PKT_BYTE_CNT_L (61),
.PKT_ADDR_H (54),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (55),
.PKT_TRANS_POSTED (56),
.PKT_TRANS_WRITE (57),
.PKT_TRANS_READ (58),
.PKT_TRANS_LOCK (59),
.PKT_TRANS_EXCLUSIVE (60),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (78),
.PKT_SRC_ID_L (76),
.PKT_DEST_ID_H (81),
.PKT_DEST_ID_L (79),
.PKT_THREAD_ID_H (82),
.PKT_THREAD_ID_L (82),
.PKT_CACHE_H (89),
.PKT_CACHE_L (86),
.PKT_DATA_SIDEBAND_H (73),
.PKT_DATA_SIDEBAND_L (73),
.PKT_QOS_H (75),
.PKT_QOS_L (75),
.PKT_ADDR_SIDEBAND_H (72),
.PKT_ADDR_SIDEBAND_L (72),
.PKT_RESPONSE_STATUS_H (91),
.PKT_RESPONSE_STATUS_L (90),
.ST_DATA_W (92),
.ST_CHANNEL_W (6),
.AV_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_RSP (0),
.ID (1),
.BURSTWRAP_VALUE (3),
.CACHE_VALUE (0),
.SECURE_ACCESS_BIT (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) nios_instruction_master_translator_avalon_universal_master_0_agent (
.clk (clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.av_address (nios_instruction_master_translator_avalon_universal_master_0_address), // av.address
.av_write (nios_instruction_master_translator_avalon_universal_master_0_write), // .write
.av_read (nios_instruction_master_translator_avalon_universal_master_0_read), // .read
.av_writedata (nios_instruction_master_translator_avalon_universal_master_0_writedata), // .writedata
.av_readdata (nios_instruction_master_translator_avalon_universal_master_0_readdata), // .readdata
.av_waitrequest (nios_instruction_master_translator_avalon_universal_master_0_waitrequest), // .waitrequest
.av_readdatavalid (nios_instruction_master_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
.av_byteenable (nios_instruction_master_translator_avalon_universal_master_0_byteenable), // .byteenable
.av_burstcount (nios_instruction_master_translator_avalon_universal_master_0_burstcount), // .burstcount
.av_debugaccess (nios_instruction_master_translator_avalon_universal_master_0_debugaccess), // .debugaccess
.av_lock (nios_instruction_master_translator_avalon_universal_master_0_lock), // .lock
.cp_valid (nios_instruction_master_translator_avalon_universal_master_0_agent_cp_valid), // cp.valid
.cp_data (nios_instruction_master_translator_avalon_universal_master_0_agent_cp_data), // .data
.cp_startofpacket (nios_instruction_master_translator_avalon_universal_master_0_agent_cp_startofpacket), // .startofpacket
.cp_endofpacket (nios_instruction_master_translator_avalon_universal_master_0_agent_cp_endofpacket), // .endofpacket
.cp_ready (nios_instruction_master_translator_avalon_universal_master_0_agent_cp_ready), // .ready
.rp_valid (limiter_rsp_src_valid), // rp.valid
.rp_data (limiter_rsp_src_data), // .data
.rp_channel (limiter_rsp_src_channel), // .channel
.rp_startofpacket (limiter_rsp_src_startofpacket), // .startofpacket
.rp_endofpacket (limiter_rsp_src_endofpacket), // .endofpacket
.rp_ready (limiter_rsp_src_ready), // .ready
.av_response (), // (terminated)
.av_writeresponserequest (1'b0), // (terminated)
.av_writeresponsevalid () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BEGIN_BURST (74),
.PKT_SYMBOL_W (8),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_ADDR_H (54),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (55),
.PKT_TRANS_POSTED (56),
.PKT_TRANS_WRITE (57),
.PKT_TRANS_READ (58),
.PKT_TRANS_LOCK (59),
.PKT_SRC_ID_H (78),
.PKT_SRC_ID_L (76),
.PKT_DEST_ID_H (81),
.PKT_DEST_ID_L (79),
.PKT_BURSTWRAP_H (66),
.PKT_BURSTWRAP_L (64),
.PKT_BYTE_CNT_H (63),
.PKT_BYTE_CNT_L (61),
.PKT_PROTECTION_H (85),
.PKT_PROTECTION_L (83),
.PKT_RESPONSE_STATUS_H (91),
.PKT_RESPONSE_STATUS_L (90),
.PKT_BURST_SIZE_H (69),
.PKT_BURST_SIZE_L (67),
.ST_CHANNEL_W (6),
.ST_DATA_W (92),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) ram_s1_translator_avalon_universal_slave_0_agent (
.clk (clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.m0_address (ram_s1_translator_avalon_universal_slave_0_agent_m0_address), // m0.address
.m0_burstcount (ram_s1_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount
.m0_byteenable (ram_s1_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable
.m0_debugaccess (ram_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess
.m0_lock (ram_s1_translator_avalon_universal_slave_0_agent_m0_lock), // .lock
.m0_readdata (ram_s1_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata
.m0_readdatavalid (ram_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid
.m0_read (ram_s1_translator_avalon_universal_slave_0_agent_m0_read), // .read
.m0_waitrequest (ram_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest
.m0_writedata (ram_s1_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata
.m0_write (ram_s1_translator_avalon_universal_slave_0_agent_m0_write), // .write
.rp_endofpacket (ram_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (ram_s1_translator_avalon_universal_slave_0_agent_rp_ready), // .ready
.rp_valid (ram_s1_translator_avalon_universal_slave_0_agent_rp_valid), // .valid
.rp_data (ram_s1_translator_avalon_universal_slave_0_agent_rp_data), // .data
.rp_startofpacket (ram_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_xbar_mux_src_ready), // cp.ready
.cp_valid (cmd_xbar_mux_src_valid), // .valid
.cp_data (cmd_xbar_mux_src_data), // .data
.cp_startofpacket (cmd_xbar_mux_src_startofpacket), // .startofpacket
.cp_endofpacket (cmd_xbar_mux_src_endofpacket), // .endofpacket
.cp_channel (cmd_xbar_mux_src_channel), // .channel
.rf_sink_ready (ram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (ram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (ram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (ram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (ram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // .data
.rf_source_ready (ram_s1_translator_avalon_universal_slave_0_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (ram_s1_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid
.rf_source_startofpacket (ram_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (ram_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (ram_s1_translator_avalon_universal_slave_0_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (ram_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (ram_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_sink_data (ram_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // .data
.rdata_fifo_src_ready (ram_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (ram_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (ram_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponserequest (), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (93),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) ram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo (
.clk (clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.in_data (ram_s1_translator_avalon_universal_slave_0_agent_rf_source_data), // in.data
.in_valid (ram_s1_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid
.in_ready (ram_s1_translator_avalon_universal_slave_0_agent_rf_source_ready), // .ready
.in_startofpacket (ram_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (ram_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket
.out_data (ram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // out.data
.out_valid (ram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid
.out_ready (ram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (ram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (ram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BEGIN_BURST (74),
.PKT_SYMBOL_W (8),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_ADDR_H (54),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (55),
.PKT_TRANS_POSTED (56),
.PKT_TRANS_WRITE (57),
.PKT_TRANS_READ (58),
.PKT_TRANS_LOCK (59),
.PKT_SRC_ID_H (78),
.PKT_SRC_ID_L (76),
.PKT_DEST_ID_H (81),
.PKT_DEST_ID_L (79),
.PKT_BURSTWRAP_H (66),
.PKT_BURSTWRAP_L (64),
.PKT_BYTE_CNT_H (63),
.PKT_BYTE_CNT_L (61),
.PKT_PROTECTION_H (85),
.PKT_PROTECTION_L (83),
.PKT_RESPONSE_STATUS_H (91),
.PKT_RESPONSE_STATUS_L (90),
.PKT_BURST_SIZE_H (69),
.PKT_BURST_SIZE_L (67),
.ST_CHANNEL_W (6),
.ST_DATA_W (92),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent (
.clk (clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.m0_address (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_address), // m0.address
.m0_burstcount (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount
.m0_byteenable (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable
.m0_debugaccess (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess
.m0_lock (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_lock), // .lock
.m0_readdata (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata
.m0_readdatavalid (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid
.m0_read (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_read), // .read
.m0_waitrequest (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest
.m0_writedata (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata
.m0_write (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_write), // .write
.rp_endofpacket (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rp_ready), // .ready
.rp_valid (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rp_valid), // .valid
.rp_data (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rp_data), // .data
.rp_startofpacket (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_xbar_demux_src1_ready), // cp.ready
.cp_valid (cmd_xbar_demux_src1_valid), // .valid
.cp_data (cmd_xbar_demux_src1_data), // .data
.cp_startofpacket (cmd_xbar_demux_src1_startofpacket), // .startofpacket
.cp_endofpacket (cmd_xbar_demux_src1_endofpacket), // .endofpacket
.cp_channel (cmd_xbar_demux_src1_channel), // .channel
.rf_sink_ready (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // .data
.rf_source_ready (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid
.rf_source_startofpacket (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_sink_data (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // .data
.rdata_fifo_src_ready (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponserequest (), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (93),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo (
.clk (clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.in_data (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rf_source_data), // in.data
.in_valid (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid
.in_ready (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rf_source_ready), // .ready
.in_startofpacket (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket
.out_data (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // out.data
.out_valid (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid
.out_ready (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BEGIN_BURST (74),
.PKT_SYMBOL_W (8),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_ADDR_H (54),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (55),
.PKT_TRANS_POSTED (56),
.PKT_TRANS_WRITE (57),
.PKT_TRANS_READ (58),
.PKT_TRANS_LOCK (59),
.PKT_SRC_ID_H (78),
.PKT_SRC_ID_L (76),
.PKT_DEST_ID_H (81),
.PKT_DEST_ID_L (79),
.PKT_BURSTWRAP_H (66),
.PKT_BURSTWRAP_L (64),
.PKT_BYTE_CNT_H (63),
.PKT_BYTE_CNT_L (61),
.PKT_PROTECTION_H (85),
.PKT_PROTECTION_L (83),
.PKT_RESPONSE_STATUS_H (91),
.PKT_RESPONSE_STATUS_L (90),
.PKT_BURST_SIZE_H (69),
.PKT_BURST_SIZE_L (67),
.ST_CHANNEL_W (6),
.ST_DATA_W (92),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent (
.clk (clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.m0_address (sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_address), // m0.address
.m0_burstcount (sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount
.m0_byteenable (sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable
.m0_debugaccess (sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess
.m0_lock (sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_lock), // .lock
.m0_readdata (sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata
.m0_readdatavalid (sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid
.m0_read (sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_read), // .read
.m0_waitrequest (sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest
.m0_writedata (sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata
.m0_write (sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_write), // .write
.rp_endofpacket (sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rp_ready), // .ready
.rp_valid (sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rp_valid), // .valid
.rp_data (sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rp_data), // .data
.rp_startofpacket (sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_xbar_demux_src2_ready), // cp.ready
.cp_valid (cmd_xbar_demux_src2_valid), // .valid
.cp_data (cmd_xbar_demux_src2_data), // .data
.cp_startofpacket (cmd_xbar_demux_src2_startofpacket), // .startofpacket
.cp_endofpacket (cmd_xbar_demux_src2_endofpacket), // .endofpacket
.cp_channel (cmd_xbar_demux_src2_channel), // .channel
.rf_sink_ready (sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // .data
.rf_source_ready (sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid
.rf_source_startofpacket (sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_sink_data (sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // .data
.rdata_fifo_src_ready (sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponserequest (), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (93),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo (
.clk (clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.in_data (sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rf_source_data), // in.data
.in_valid (sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid
.in_ready (sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rf_source_ready), // .ready
.in_startofpacket (sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket
.out_data (sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // out.data
.out_valid (sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid
.out_ready (sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BEGIN_BURST (74),
.PKT_SYMBOL_W (8),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_ADDR_H (54),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (55),
.PKT_TRANS_POSTED (56),
.PKT_TRANS_WRITE (57),
.PKT_TRANS_READ (58),
.PKT_TRANS_LOCK (59),
.PKT_SRC_ID_H (78),
.PKT_SRC_ID_L (76),
.PKT_DEST_ID_H (81),
.PKT_DEST_ID_L (79),
.PKT_BURSTWRAP_H (66),
.PKT_BURSTWRAP_L (64),
.PKT_BYTE_CNT_H (63),
.PKT_BYTE_CNT_L (61),
.PKT_PROTECTION_H (85),
.PKT_PROTECTION_L (83),
.PKT_RESPONSE_STATUS_H (91),
.PKT_RESPONSE_STATUS_L (90),
.PKT_BURST_SIZE_H (69),
.PKT_BURST_SIZE_L (67),
.ST_CHANNEL_W (6),
.ST_DATA_W (92),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) nios_jtag_debug_module_translator_avalon_universal_slave_0_agent (
.clk (clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.m0_address (nios_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_address), // m0.address
.m0_burstcount (nios_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount
.m0_byteenable (nios_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable
.m0_debugaccess (nios_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess
.m0_lock (nios_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_lock), // .lock
.m0_readdata (nios_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata
.m0_readdatavalid (nios_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid
.m0_read (nios_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_read), // .read
.m0_waitrequest (nios_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest
.m0_writedata (nios_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata
.m0_write (nios_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_write), // .write
.rp_endofpacket (nios_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (nios_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_ready), // .ready
.rp_valid (nios_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_valid), // .valid
.rp_data (nios_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_data), // .data
.rp_startofpacket (nios_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_xbar_mux_003_src_ready), // cp.ready
.cp_valid (cmd_xbar_mux_003_src_valid), // .valid
.cp_data (cmd_xbar_mux_003_src_data), // .data
.cp_startofpacket (cmd_xbar_mux_003_src_startofpacket), // .startofpacket
.cp_endofpacket (cmd_xbar_mux_003_src_endofpacket), // .endofpacket
.cp_channel (cmd_xbar_mux_003_src_channel), // .channel
.rf_sink_ready (nios_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (nios_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (nios_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (nios_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (nios_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // .data
.rf_source_ready (nios_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (nios_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid
.rf_source_startofpacket (nios_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (nios_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (nios_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (nios_jtag_debug_module_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (nios_jtag_debug_module_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_sink_data (nios_jtag_debug_module_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // .data
.rdata_fifo_src_ready (nios_jtag_debug_module_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (nios_jtag_debug_module_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (nios_jtag_debug_module_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponserequest (), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (93),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) nios_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo (
.clk (clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.in_data (nios_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_data), // in.data
.in_valid (nios_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid
.in_ready (nios_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_ready), // .ready
.in_startofpacket (nios_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (nios_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket
.out_data (nios_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // out.data
.out_valid (nios_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid
.out_ready (nios_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (nios_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (nios_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BEGIN_BURST (74),
.PKT_SYMBOL_W (8),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_ADDR_H (54),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (55),
.PKT_TRANS_POSTED (56),
.PKT_TRANS_WRITE (57),
.PKT_TRANS_READ (58),
.PKT_TRANS_LOCK (59),
.PKT_SRC_ID_H (78),
.PKT_SRC_ID_L (76),
.PKT_DEST_ID_H (81),
.PKT_DEST_ID_L (79),
.PKT_BURSTWRAP_H (66),
.PKT_BURSTWRAP_L (64),
.PKT_BYTE_CNT_H (63),
.PKT_BYTE_CNT_L (61),
.PKT_PROTECTION_H (85),
.PKT_PROTECTION_L (83),
.PKT_RESPONSE_STATUS_H (91),
.PKT_RESPONSE_STATUS_L (90),
.PKT_BURST_SIZE_H (69),
.PKT_BURST_SIZE_L (67),
.ST_CHANNEL_W (6),
.ST_DATA_W (92),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) hw_ann_0_avalon_slave_0_translator_avalon_universal_slave_0_agent (
.clk (clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.m0_address (hw_ann_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_address), // m0.address
.m0_burstcount (hw_ann_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount
.m0_byteenable (hw_ann_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable
.m0_debugaccess (hw_ann_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess
.m0_lock (hw_ann_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_lock), // .lock
.m0_readdata (hw_ann_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata
.m0_readdatavalid (hw_ann_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid
.m0_read (hw_ann_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_read), // .read
.m0_waitrequest (hw_ann_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest
.m0_writedata (hw_ann_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata
.m0_write (hw_ann_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_write), // .write
.rp_endofpacket (hw_ann_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (hw_ann_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_ready), // .ready
.rp_valid (hw_ann_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_valid), // .valid
.rp_data (hw_ann_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_data), // .data
.rp_startofpacket (hw_ann_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_xbar_mux_004_src_ready), // cp.ready
.cp_valid (cmd_xbar_mux_004_src_valid), // .valid
.cp_data (cmd_xbar_mux_004_src_data), // .data
.cp_startofpacket (cmd_xbar_mux_004_src_startofpacket), // .startofpacket
.cp_endofpacket (cmd_xbar_mux_004_src_endofpacket), // .endofpacket
.cp_channel (cmd_xbar_mux_004_src_channel), // .channel
.rf_sink_ready (hw_ann_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (hw_ann_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (hw_ann_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (hw_ann_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (hw_ann_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // .data
.rf_source_ready (hw_ann_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (hw_ann_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid
.rf_source_startofpacket (hw_ann_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (hw_ann_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (hw_ann_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (hw_ann_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (hw_ann_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_sink_data (hw_ann_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // .data
.rdata_fifo_src_ready (hw_ann_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (hw_ann_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (hw_ann_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponserequest (), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (93),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) hw_ann_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo (
.clk (clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.in_data (hw_ann_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_data), // in.data
.in_valid (hw_ann_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid
.in_ready (hw_ann_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_ready), // .ready
.in_startofpacket (hw_ann_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (hw_ann_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket
.out_data (hw_ann_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // out.data
.out_valid (hw_ann_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid
.out_ready (hw_ann_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (hw_ann_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (hw_ann_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BEGIN_BURST (74),
.PKT_SYMBOL_W (8),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_ADDR_H (54),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (55),
.PKT_TRANS_POSTED (56),
.PKT_TRANS_WRITE (57),
.PKT_TRANS_READ (58),
.PKT_TRANS_LOCK (59),
.PKT_SRC_ID_H (78),
.PKT_SRC_ID_L (76),
.PKT_DEST_ID_H (81),
.PKT_DEST_ID_L (79),
.PKT_BURSTWRAP_H (66),
.PKT_BURSTWRAP_L (64),
.PKT_BYTE_CNT_H (63),
.PKT_BYTE_CNT_L (61),
.PKT_PROTECTION_H (85),
.PKT_PROTECTION_L (83),
.PKT_RESPONSE_STATUS_H (91),
.PKT_RESPONSE_STATUS_L (90),
.PKT_BURST_SIZE_H (69),
.PKT_BURST_SIZE_L (67),
.ST_CHANNEL_W (6),
.ST_DATA_W (92),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) lfsr_0_avalon_slave_0_translator_avalon_universal_slave_0_agent (
.clk (clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.m0_address (lfsr_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_address), // m0.address
.m0_burstcount (lfsr_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount
.m0_byteenable (lfsr_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable
.m0_debugaccess (lfsr_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess
.m0_lock (lfsr_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_lock), // .lock
.m0_readdata (lfsr_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata
.m0_readdatavalid (lfsr_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid
.m0_read (lfsr_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_read), // .read
.m0_waitrequest (lfsr_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest
.m0_writedata (lfsr_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata
.m0_write (lfsr_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_m0_write), // .write
.rp_endofpacket (lfsr_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (lfsr_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_ready), // .ready
.rp_valid (lfsr_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_valid), // .valid
.rp_data (lfsr_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_data), // .data
.rp_startofpacket (lfsr_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_xbar_mux_005_src_ready), // cp.ready
.cp_valid (cmd_xbar_mux_005_src_valid), // .valid
.cp_data (cmd_xbar_mux_005_src_data), // .data
.cp_startofpacket (cmd_xbar_mux_005_src_startofpacket), // .startofpacket
.cp_endofpacket (cmd_xbar_mux_005_src_endofpacket), // .endofpacket
.cp_channel (cmd_xbar_mux_005_src_channel), // .channel
.rf_sink_ready (lfsr_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (lfsr_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (lfsr_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (lfsr_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (lfsr_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // .data
.rf_source_ready (lfsr_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (lfsr_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid
.rf_source_startofpacket (lfsr_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (lfsr_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (lfsr_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (lfsr_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (lfsr_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_sink_data (lfsr_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // .data
.rdata_fifo_src_ready (lfsr_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (lfsr_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (lfsr_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponserequest (), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (93),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) lfsr_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo (
.clk (clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.in_data (lfsr_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_data), // in.data
.in_valid (lfsr_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid
.in_ready (lfsr_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_ready), // .ready
.in_startofpacket (lfsr_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (lfsr_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket
.out_data (lfsr_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // out.data
.out_valid (lfsr_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid
.out_ready (lfsr_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (lfsr_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (lfsr_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
SoC_addr_router addr_router (
.sink_ready (nios_data_master_translator_avalon_universal_master_0_agent_cp_ready), // sink.ready
.sink_valid (nios_data_master_translator_avalon_universal_master_0_agent_cp_valid), // .valid
.sink_data (nios_data_master_translator_avalon_universal_master_0_agent_cp_data), // .data
.sink_startofpacket (nios_data_master_translator_avalon_universal_master_0_agent_cp_startofpacket), // .startofpacket
.sink_endofpacket (nios_data_master_translator_avalon_universal_master_0_agent_cp_endofpacket), // .endofpacket
.clk (clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.src_ready (addr_router_src_ready), // src.ready
.src_valid (addr_router_src_valid), // .valid
.src_data (addr_router_src_data), // .data
.src_channel (addr_router_src_channel), // .channel
.src_startofpacket (addr_router_src_startofpacket), // .startofpacket
.src_endofpacket (addr_router_src_endofpacket) // .endofpacket
);
SoC_addr_router_001 addr_router_001 (
.sink_ready (nios_instruction_master_translator_avalon_universal_master_0_agent_cp_ready), // sink.ready
.sink_valid (nios_instruction_master_translator_avalon_universal_master_0_agent_cp_valid), // .valid
.sink_data (nios_instruction_master_translator_avalon_universal_master_0_agent_cp_data), // .data
.sink_startofpacket (nios_instruction_master_translator_avalon_universal_master_0_agent_cp_startofpacket), // .startofpacket
.sink_endofpacket (nios_instruction_master_translator_avalon_universal_master_0_agent_cp_endofpacket), // .endofpacket
.clk (clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.src_ready (addr_router_001_src_ready), // src.ready
.src_valid (addr_router_001_src_valid), // .valid
.src_data (addr_router_001_src_data), // .data
.src_channel (addr_router_001_src_channel), // .channel
.src_startofpacket (addr_router_001_src_startofpacket), // .startofpacket
.src_endofpacket (addr_router_001_src_endofpacket) // .endofpacket
);
SoC_id_router id_router (
.sink_ready (ram_s1_translator_avalon_universal_slave_0_agent_rp_ready), // sink.ready
.sink_valid (ram_s1_translator_avalon_universal_slave_0_agent_rp_valid), // .valid
.sink_data (ram_s1_translator_avalon_universal_slave_0_agent_rp_data), // .data
.sink_startofpacket (ram_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (ram_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket), // .endofpacket
.clk (clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.src_ready (id_router_src_ready), // src.ready
.src_valid (id_router_src_valid), // .valid
.src_data (id_router_src_data), // .data
.src_channel (id_router_src_channel), // .channel
.src_startofpacket (id_router_src_startofpacket), // .startofpacket
.src_endofpacket (id_router_src_endofpacket) // .endofpacket
);
SoC_id_router_001 id_router_001 (
.sink_ready (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rp_ready), // sink.ready
.sink_valid (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rp_valid), // .valid
.sink_data (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rp_data), // .data
.sink_startofpacket (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rp_endofpacket), // .endofpacket
.clk (clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.src_ready (id_router_001_src_ready), // src.ready
.src_valid (id_router_001_src_valid), // .valid
.src_data (id_router_001_src_data), // .data
.src_channel (id_router_001_src_channel), // .channel
.src_startofpacket (id_router_001_src_startofpacket), // .startofpacket
.src_endofpacket (id_router_001_src_endofpacket) // .endofpacket
);
SoC_id_router_001 id_router_002 (
.sink_ready (sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rp_ready), // sink.ready
.sink_valid (sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rp_valid), // .valid
.sink_data (sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rp_data), // .data
.sink_startofpacket (sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rp_endofpacket), // .endofpacket
.clk (clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.src_ready (id_router_002_src_ready), // src.ready
.src_valid (id_router_002_src_valid), // .valid
.src_data (id_router_002_src_data), // .data
.src_channel (id_router_002_src_channel), // .channel
.src_startofpacket (id_router_002_src_startofpacket), // .startofpacket
.src_endofpacket (id_router_002_src_endofpacket) // .endofpacket
);
SoC_id_router id_router_003 (
.sink_ready (nios_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_ready), // sink.ready
.sink_valid (nios_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_valid), // .valid
.sink_data (nios_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_data), // .data
.sink_startofpacket (nios_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (nios_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_endofpacket), // .endofpacket
.clk (clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.src_ready (id_router_003_src_ready), // src.ready
.src_valid (id_router_003_src_valid), // .valid
.src_data (id_router_003_src_data), // .data
.src_channel (id_router_003_src_channel), // .channel
.src_startofpacket (id_router_003_src_startofpacket), // .startofpacket
.src_endofpacket (id_router_003_src_endofpacket) // .endofpacket
);
SoC_id_router id_router_004 (
.sink_ready (hw_ann_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_ready), // sink.ready
.sink_valid (hw_ann_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_valid), // .valid
.sink_data (hw_ann_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_data), // .data
.sink_startofpacket (hw_ann_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (hw_ann_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_endofpacket), // .endofpacket
.clk (clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.src_ready (id_router_004_src_ready), // src.ready
.src_valid (id_router_004_src_valid), // .valid
.src_data (id_router_004_src_data), // .data
.src_channel (id_router_004_src_channel), // .channel
.src_startofpacket (id_router_004_src_startofpacket), // .startofpacket
.src_endofpacket (id_router_004_src_endofpacket) // .endofpacket
);
SoC_id_router id_router_005 (
.sink_ready (lfsr_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_ready), // sink.ready
.sink_valid (lfsr_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_valid), // .valid
.sink_data (lfsr_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_data), // .data
.sink_startofpacket (lfsr_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (lfsr_0_avalon_slave_0_translator_avalon_universal_slave_0_agent_rp_endofpacket), // .endofpacket
.clk (clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.src_ready (id_router_005_src_ready), // src.ready
.src_valid (id_router_005_src_valid), // .valid
.src_data (id_router_005_src_data), // .data
.src_channel (id_router_005_src_channel), // .channel
.src_startofpacket (id_router_005_src_startofpacket), // .startofpacket
.src_endofpacket (id_router_005_src_endofpacket) // .endofpacket
);
altera_merlin_traffic_limiter #(
.PKT_DEST_ID_H (81),
.PKT_DEST_ID_L (79),
.PKT_TRANS_POSTED (56),
.PKT_TRANS_WRITE (57),
.MAX_OUTSTANDING_RESPONSES (1),
.PIPELINED (0),
.ST_DATA_W (92),
.ST_CHANNEL_W (6),
.VALID_WIDTH (6),
.ENFORCE_ORDER (1),
.PREVENT_HAZARDS (0),
.PKT_BYTE_CNT_H (63),
.PKT_BYTE_CNT_L (61),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32)
) limiter (
.clk (clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.cmd_sink_ready (addr_router_001_src_ready), // cmd_sink.ready
.cmd_sink_valid (addr_router_001_src_valid), // .valid
.cmd_sink_data (addr_router_001_src_data), // .data
.cmd_sink_channel (addr_router_001_src_channel), // .channel
.cmd_sink_startofpacket (addr_router_001_src_startofpacket), // .startofpacket
.cmd_sink_endofpacket (addr_router_001_src_endofpacket), // .endofpacket
.cmd_src_ready (limiter_cmd_src_ready), // cmd_src.ready
.cmd_src_data (limiter_cmd_src_data), // .data
.cmd_src_channel (limiter_cmd_src_channel), // .channel
.cmd_src_startofpacket (limiter_cmd_src_startofpacket), // .startofpacket
.cmd_src_endofpacket (limiter_cmd_src_endofpacket), // .endofpacket
.rsp_sink_ready (rsp_xbar_mux_001_src_ready), // rsp_sink.ready
.rsp_sink_valid (rsp_xbar_mux_001_src_valid), // .valid
.rsp_sink_channel (rsp_xbar_mux_001_src_channel), // .channel
.rsp_sink_data (rsp_xbar_mux_001_src_data), // .data
.rsp_sink_startofpacket (rsp_xbar_mux_001_src_startofpacket), // .startofpacket
.rsp_sink_endofpacket (rsp_xbar_mux_001_src_endofpacket), // .endofpacket
.rsp_src_ready (limiter_rsp_src_ready), // rsp_src.ready
.rsp_src_valid (limiter_rsp_src_valid), // .valid
.rsp_src_data (limiter_rsp_src_data), // .data
.rsp_src_channel (limiter_rsp_src_channel), // .channel
.rsp_src_startofpacket (limiter_rsp_src_startofpacket), // .startofpacket
.rsp_src_endofpacket (limiter_rsp_src_endofpacket), // .endofpacket
.cmd_src_valid (limiter_cmd_valid_data) // cmd_valid.data
);
altera_reset_controller #(
.NUM_RESET_INPUTS (1),
.OUTPUT_RESET_SYNC_EDGES ("deassert"),
.SYNC_DEPTH (2),
.RESET_REQUEST_PRESENT (1)
) rst_controller (
.reset_in0 (~reset_reset_n), // reset_in0.reset
.clk (clk_clk), // clk.clk
.reset_out (rst_controller_reset_out_reset), // reset_out.reset
.reset_req (rst_controller_reset_out_reset_req), // .reset_req
.reset_in1 (1'b0), // (terminated)
.reset_in2 (1'b0), // (terminated)
.reset_in3 (1'b0), // (terminated)
.reset_in4 (1'b0), // (terminated)
.reset_in5 (1'b0), // (terminated)
.reset_in6 (1'b0), // (terminated)
.reset_in7 (1'b0), // (terminated)
.reset_in8 (1'b0), // (terminated)
.reset_in9 (1'b0), // (terminated)
.reset_in10 (1'b0), // (terminated)
.reset_in11 (1'b0), // (terminated)
.reset_in12 (1'b0), // (terminated)
.reset_in13 (1'b0), // (terminated)
.reset_in14 (1'b0), // (terminated)
.reset_in15 (1'b0) // (terminated)
);
SoC_cmd_xbar_demux cmd_xbar_demux (
.clk (clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.sink_ready (addr_router_src_ready), // sink.ready
.sink_channel (addr_router_src_channel), // .channel
.sink_data (addr_router_src_data), // .data
.sink_startofpacket (addr_router_src_startofpacket), // .startofpacket
.sink_endofpacket (addr_router_src_endofpacket), // .endofpacket
.sink_valid (addr_router_src_valid), // .valid
.src0_ready (cmd_xbar_demux_src0_ready), // src0.ready
.src0_valid (cmd_xbar_demux_src0_valid), // .valid
.src0_data (cmd_xbar_demux_src0_data), // .data
.src0_channel (cmd_xbar_demux_src0_channel), // .channel
.src0_startofpacket (cmd_xbar_demux_src0_startofpacket), // .startofpacket
.src0_endofpacket (cmd_xbar_demux_src0_endofpacket), // .endofpacket
.src1_ready (cmd_xbar_demux_src1_ready), // src1.ready
.src1_valid (cmd_xbar_demux_src1_valid), // .valid
.src1_data (cmd_xbar_demux_src1_data), // .data
.src1_channel (cmd_xbar_demux_src1_channel), // .channel
.src1_startofpacket (cmd_xbar_demux_src1_startofpacket), // .startofpacket
.src1_endofpacket (cmd_xbar_demux_src1_endofpacket), // .endofpacket
.src2_ready (cmd_xbar_demux_src2_ready), // src2.ready
.src2_valid (cmd_xbar_demux_src2_valid), // .valid
.src2_data (cmd_xbar_demux_src2_data), // .data
.src2_channel (cmd_xbar_demux_src2_channel), // .channel
.src2_startofpacket (cmd_xbar_demux_src2_startofpacket), // .startofpacket
.src2_endofpacket (cmd_xbar_demux_src2_endofpacket), // .endofpacket
.src3_ready (cmd_xbar_demux_src3_ready), // src3.ready
.src3_valid (cmd_xbar_demux_src3_valid), // .valid
.src3_data (cmd_xbar_demux_src3_data), // .data
.src3_channel (cmd_xbar_demux_src3_channel), // .channel
.src3_startofpacket (cmd_xbar_demux_src3_startofpacket), // .startofpacket
.src3_endofpacket (cmd_xbar_demux_src3_endofpacket), // .endofpacket
.src4_ready (cmd_xbar_demux_src4_ready), // src4.ready
.src4_valid (cmd_xbar_demux_src4_valid), // .valid
.src4_data (cmd_xbar_demux_src4_data), // .data
.src4_channel (cmd_xbar_demux_src4_channel), // .channel
.src4_startofpacket (cmd_xbar_demux_src4_startofpacket), // .startofpacket
.src4_endofpacket (cmd_xbar_demux_src4_endofpacket), // .endofpacket
.src5_ready (cmd_xbar_demux_src5_ready), // src5.ready
.src5_valid (cmd_xbar_demux_src5_valid), // .valid
.src5_data (cmd_xbar_demux_src5_data), // .data
.src5_channel (cmd_xbar_demux_src5_channel), // .channel
.src5_startofpacket (cmd_xbar_demux_src5_startofpacket), // .startofpacket
.src5_endofpacket (cmd_xbar_demux_src5_endofpacket) // .endofpacket
);
SoC_cmd_xbar_demux_001 cmd_xbar_demux_001 (
.clk (clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.sink_ready (limiter_cmd_src_ready), // sink.ready
.sink_channel (limiter_cmd_src_channel), // .channel
.sink_data (limiter_cmd_src_data), // .data
.sink_startofpacket (limiter_cmd_src_startofpacket), // .startofpacket
.sink_endofpacket (limiter_cmd_src_endofpacket), // .endofpacket
.sink_valid (limiter_cmd_valid_data), // sink_valid.data
.src0_ready (cmd_xbar_demux_001_src0_ready), // src0.ready
.src0_valid (cmd_xbar_demux_001_src0_valid), // .valid
.src0_data (cmd_xbar_demux_001_src0_data), // .data
.src0_channel (cmd_xbar_demux_001_src0_channel), // .channel
.src0_startofpacket (cmd_xbar_demux_001_src0_startofpacket), // .startofpacket
.src0_endofpacket (cmd_xbar_demux_001_src0_endofpacket), // .endofpacket
.src1_ready (cmd_xbar_demux_001_src1_ready), // src1.ready
.src1_valid (cmd_xbar_demux_001_src1_valid), // .valid
.src1_data (cmd_xbar_demux_001_src1_data), // .data
.src1_channel (cmd_xbar_demux_001_src1_channel), // .channel
.src1_startofpacket (cmd_xbar_demux_001_src1_startofpacket), // .startofpacket
.src1_endofpacket (cmd_xbar_demux_001_src1_endofpacket), // .endofpacket
.src2_ready (cmd_xbar_demux_001_src2_ready), // src2.ready
.src2_valid (cmd_xbar_demux_001_src2_valid), // .valid
.src2_data (cmd_xbar_demux_001_src2_data), // .data
.src2_channel (cmd_xbar_demux_001_src2_channel), // .channel
.src2_startofpacket (cmd_xbar_demux_001_src2_startofpacket), // .startofpacket
.src2_endofpacket (cmd_xbar_demux_001_src2_endofpacket), // .endofpacket
.src3_ready (cmd_xbar_demux_001_src3_ready), // src3.ready
.src3_valid (cmd_xbar_demux_001_src3_valid), // .valid
.src3_data (cmd_xbar_demux_001_src3_data), // .data
.src3_channel (cmd_xbar_demux_001_src3_channel), // .channel
.src3_startofpacket (cmd_xbar_demux_001_src3_startofpacket), // .startofpacket
.src3_endofpacket (cmd_xbar_demux_001_src3_endofpacket) // .endofpacket
);
SoC_cmd_xbar_mux cmd_xbar_mux (
.clk (clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.src_ready (cmd_xbar_mux_src_ready), // src.ready
.src_valid (cmd_xbar_mux_src_valid), // .valid
.src_data (cmd_xbar_mux_src_data), // .data
.src_channel (cmd_xbar_mux_src_channel), // .channel
.src_startofpacket (cmd_xbar_mux_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_xbar_mux_src_endofpacket), // .endofpacket
.sink0_ready (cmd_xbar_demux_src0_ready), // sink0.ready
.sink0_valid (cmd_xbar_demux_src0_valid), // .valid
.sink0_channel (cmd_xbar_demux_src0_channel), // .channel
.sink0_data (cmd_xbar_demux_src0_data), // .data
.sink0_startofpacket (cmd_xbar_demux_src0_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_xbar_demux_src0_endofpacket), // .endofpacket
.sink1_ready (cmd_xbar_demux_001_src0_ready), // sink1.ready
.sink1_valid (cmd_xbar_demux_001_src0_valid), // .valid
.sink1_channel (cmd_xbar_demux_001_src0_channel), // .channel
.sink1_data (cmd_xbar_demux_001_src0_data), // .data
.sink1_startofpacket (cmd_xbar_demux_001_src0_startofpacket), // .startofpacket
.sink1_endofpacket (cmd_xbar_demux_001_src0_endofpacket) // .endofpacket
);
SoC_cmd_xbar_mux cmd_xbar_mux_003 (
.clk (clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.src_ready (cmd_xbar_mux_003_src_ready), // src.ready
.src_valid (cmd_xbar_mux_003_src_valid), // .valid
.src_data (cmd_xbar_mux_003_src_data), // .data
.src_channel (cmd_xbar_mux_003_src_channel), // .channel
.src_startofpacket (cmd_xbar_mux_003_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_xbar_mux_003_src_endofpacket), // .endofpacket
.sink0_ready (cmd_xbar_demux_src3_ready), // sink0.ready
.sink0_valid (cmd_xbar_demux_src3_valid), // .valid
.sink0_channel (cmd_xbar_demux_src3_channel), // .channel
.sink0_data (cmd_xbar_demux_src3_data), // .data
.sink0_startofpacket (cmd_xbar_demux_src3_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_xbar_demux_src3_endofpacket), // .endofpacket
.sink1_ready (cmd_xbar_demux_001_src1_ready), // sink1.ready
.sink1_valid (cmd_xbar_demux_001_src1_valid), // .valid
.sink1_channel (cmd_xbar_demux_001_src1_channel), // .channel
.sink1_data (cmd_xbar_demux_001_src1_data), // .data
.sink1_startofpacket (cmd_xbar_demux_001_src1_startofpacket), // .startofpacket
.sink1_endofpacket (cmd_xbar_demux_001_src1_endofpacket) // .endofpacket
);
SoC_cmd_xbar_mux cmd_xbar_mux_004 (
.clk (clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.src_ready (cmd_xbar_mux_004_src_ready), // src.ready
.src_valid (cmd_xbar_mux_004_src_valid), // .valid
.src_data (cmd_xbar_mux_004_src_data), // .data
.src_channel (cmd_xbar_mux_004_src_channel), // .channel
.src_startofpacket (cmd_xbar_mux_004_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_xbar_mux_004_src_endofpacket), // .endofpacket
.sink0_ready (cmd_xbar_demux_src4_ready), // sink0.ready
.sink0_valid (cmd_xbar_demux_src4_valid), // .valid
.sink0_channel (cmd_xbar_demux_src4_channel), // .channel
.sink0_data (cmd_xbar_demux_src4_data), // .data
.sink0_startofpacket (cmd_xbar_demux_src4_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_xbar_demux_src4_endofpacket), // .endofpacket
.sink1_ready (cmd_xbar_demux_001_src2_ready), // sink1.ready
.sink1_valid (cmd_xbar_demux_001_src2_valid), // .valid
.sink1_channel (cmd_xbar_demux_001_src2_channel), // .channel
.sink1_data (cmd_xbar_demux_001_src2_data), // .data
.sink1_startofpacket (cmd_xbar_demux_001_src2_startofpacket), // .startofpacket
.sink1_endofpacket (cmd_xbar_demux_001_src2_endofpacket) // .endofpacket
);
SoC_cmd_xbar_mux cmd_xbar_mux_005 (
.clk (clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.src_ready (cmd_xbar_mux_005_src_ready), // src.ready
.src_valid (cmd_xbar_mux_005_src_valid), // .valid
.src_data (cmd_xbar_mux_005_src_data), // .data
.src_channel (cmd_xbar_mux_005_src_channel), // .channel
.src_startofpacket (cmd_xbar_mux_005_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_xbar_mux_005_src_endofpacket), // .endofpacket
.sink0_ready (cmd_xbar_demux_src5_ready), // sink0.ready
.sink0_valid (cmd_xbar_demux_src5_valid), // .valid
.sink0_channel (cmd_xbar_demux_src5_channel), // .channel
.sink0_data (cmd_xbar_demux_src5_data), // .data
.sink0_startofpacket (cmd_xbar_demux_src5_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_xbar_demux_src5_endofpacket), // .endofpacket
.sink1_ready (cmd_xbar_demux_001_src3_ready), // sink1.ready
.sink1_valid (cmd_xbar_demux_001_src3_valid), // .valid
.sink1_channel (cmd_xbar_demux_001_src3_channel), // .channel
.sink1_data (cmd_xbar_demux_001_src3_data), // .data
.sink1_startofpacket (cmd_xbar_demux_001_src3_startofpacket), // .startofpacket
.sink1_endofpacket (cmd_xbar_demux_001_src3_endofpacket) // .endofpacket
);
SoC_rsp_xbar_demux rsp_xbar_demux (
.clk (clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.sink_ready (id_router_src_ready), // sink.ready
.sink_channel (id_router_src_channel), // .channel
.sink_data (id_router_src_data), // .data
.sink_startofpacket (id_router_src_startofpacket), // .startofpacket
.sink_endofpacket (id_router_src_endofpacket), // .endofpacket
.sink_valid (id_router_src_valid), // .valid
.src0_ready (rsp_xbar_demux_src0_ready), // src0.ready
.src0_valid (rsp_xbar_demux_src0_valid), // .valid
.src0_data (rsp_xbar_demux_src0_data), // .data
.src0_channel (rsp_xbar_demux_src0_channel), // .channel
.src0_startofpacket (rsp_xbar_demux_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_xbar_demux_src0_endofpacket), // .endofpacket
.src1_ready (rsp_xbar_demux_src1_ready), // src1.ready
.src1_valid (rsp_xbar_demux_src1_valid), // .valid
.src1_data (rsp_xbar_demux_src1_data), // .data
.src1_channel (rsp_xbar_demux_src1_channel), // .channel
.src1_startofpacket (rsp_xbar_demux_src1_startofpacket), // .startofpacket
.src1_endofpacket (rsp_xbar_demux_src1_endofpacket) // .endofpacket
);
SoC_rsp_xbar_demux_001 rsp_xbar_demux_001 (
.clk (clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.sink_ready (id_router_001_src_ready), // sink.ready
.sink_channel (id_router_001_src_channel), // .channel
.sink_data (id_router_001_src_data), // .data
.sink_startofpacket (id_router_001_src_startofpacket), // .startofpacket
.sink_endofpacket (id_router_001_src_endofpacket), // .endofpacket
.sink_valid (id_router_001_src_valid), // .valid
.src0_ready (rsp_xbar_demux_001_src0_ready), // src0.ready
.src0_valid (rsp_xbar_demux_001_src0_valid), // .valid
.src0_data (rsp_xbar_demux_001_src0_data), // .data
.src0_channel (rsp_xbar_demux_001_src0_channel), // .channel
.src0_startofpacket (rsp_xbar_demux_001_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_xbar_demux_001_src0_endofpacket) // .endofpacket
);
SoC_rsp_xbar_demux_001 rsp_xbar_demux_002 (
.clk (clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.sink_ready (id_router_002_src_ready), // sink.ready
.sink_channel (id_router_002_src_channel), // .channel
.sink_data (id_router_002_src_data), // .data
.sink_startofpacket (id_router_002_src_startofpacket), // .startofpacket
.sink_endofpacket (id_router_002_src_endofpacket), // .endofpacket
.sink_valid (id_router_002_src_valid), // .valid
.src0_ready (rsp_xbar_demux_002_src0_ready), // src0.ready
.src0_valid (rsp_xbar_demux_002_src0_valid), // .valid
.src0_data (rsp_xbar_demux_002_src0_data), // .data
.src0_channel (rsp_xbar_demux_002_src0_channel), // .channel
.src0_startofpacket (rsp_xbar_demux_002_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_xbar_demux_002_src0_endofpacket) // .endofpacket
);
SoC_rsp_xbar_demux rsp_xbar_demux_003 (
.clk (clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.sink_ready (id_router_003_src_ready), // sink.ready
.sink_channel (id_router_003_src_channel), // .channel
.sink_data (id_router_003_src_data), // .data
.sink_startofpacket (id_router_003_src_startofpacket), // .startofpacket
.sink_endofpacket (id_router_003_src_endofpacket), // .endofpacket
.sink_valid (id_router_003_src_valid), // .valid
.src0_ready (rsp_xbar_demux_003_src0_ready), // src0.ready
.src0_valid (rsp_xbar_demux_003_src0_valid), // .valid
.src0_data (rsp_xbar_demux_003_src0_data), // .data
.src0_channel (rsp_xbar_demux_003_src0_channel), // .channel
.src0_startofpacket (rsp_xbar_demux_003_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_xbar_demux_003_src0_endofpacket), // .endofpacket
.src1_ready (rsp_xbar_demux_003_src1_ready), // src1.ready
.src1_valid (rsp_xbar_demux_003_src1_valid), // .valid
.src1_data (rsp_xbar_demux_003_src1_data), // .data
.src1_channel (rsp_xbar_demux_003_src1_channel), // .channel
.src1_startofpacket (rsp_xbar_demux_003_src1_startofpacket), // .startofpacket
.src1_endofpacket (rsp_xbar_demux_003_src1_endofpacket) // .endofpacket
);
SoC_rsp_xbar_demux rsp_xbar_demux_004 (
.clk (clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.sink_ready (id_router_004_src_ready), // sink.ready
.sink_channel (id_router_004_src_channel), // .channel
.sink_data (id_router_004_src_data), // .data
.sink_startofpacket (id_router_004_src_startofpacket), // .startofpacket
.sink_endofpacket (id_router_004_src_endofpacket), // .endofpacket
.sink_valid (id_router_004_src_valid), // .valid
.src0_ready (rsp_xbar_demux_004_src0_ready), // src0.ready
.src0_valid (rsp_xbar_demux_004_src0_valid), // .valid
.src0_data (rsp_xbar_demux_004_src0_data), // .data
.src0_channel (rsp_xbar_demux_004_src0_channel), // .channel
.src0_startofpacket (rsp_xbar_demux_004_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_xbar_demux_004_src0_endofpacket), // .endofpacket
.src1_ready (rsp_xbar_demux_004_src1_ready), // src1.ready
.src1_valid (rsp_xbar_demux_004_src1_valid), // .valid
.src1_data (rsp_xbar_demux_004_src1_data), // .data
.src1_channel (rsp_xbar_demux_004_src1_channel), // .channel
.src1_startofpacket (rsp_xbar_demux_004_src1_startofpacket), // .startofpacket
.src1_endofpacket (rsp_xbar_demux_004_src1_endofpacket) // .endofpacket
);
SoC_rsp_xbar_demux rsp_xbar_demux_005 (
.clk (clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.sink_ready (id_router_005_src_ready), // sink.ready
.sink_channel (id_router_005_src_channel), // .channel
.sink_data (id_router_005_src_data), // .data
.sink_startofpacket (id_router_005_src_startofpacket), // .startofpacket
.sink_endofpacket (id_router_005_src_endofpacket), // .endofpacket
.sink_valid (id_router_005_src_valid), // .valid
.src0_ready (rsp_xbar_demux_005_src0_ready), // src0.ready
.src0_valid (rsp_xbar_demux_005_src0_valid), // .valid
.src0_data (rsp_xbar_demux_005_src0_data), // .data
.src0_channel (rsp_xbar_demux_005_src0_channel), // .channel
.src0_startofpacket (rsp_xbar_demux_005_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_xbar_demux_005_src0_endofpacket), // .endofpacket
.src1_ready (rsp_xbar_demux_005_src1_ready), // src1.ready
.src1_valid (rsp_xbar_demux_005_src1_valid), // .valid
.src1_data (rsp_xbar_demux_005_src1_data), // .data
.src1_channel (rsp_xbar_demux_005_src1_channel), // .channel
.src1_startofpacket (rsp_xbar_demux_005_src1_startofpacket), // .startofpacket
.src1_endofpacket (rsp_xbar_demux_005_src1_endofpacket) // .endofpacket
);
SoC_rsp_xbar_mux rsp_xbar_mux (
.clk (clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.src_ready (rsp_xbar_mux_src_ready), // src.ready
.src_valid (rsp_xbar_mux_src_valid), // .valid
.src_data (rsp_xbar_mux_src_data), // .data
.src_channel (rsp_xbar_mux_src_channel), // .channel
.src_startofpacket (rsp_xbar_mux_src_startofpacket), // .startofpacket
.src_endofpacket (rsp_xbar_mux_src_endofpacket), // .endofpacket
.sink0_ready (rsp_xbar_demux_src0_ready), // sink0.ready
.sink0_valid (rsp_xbar_demux_src0_valid), // .valid
.sink0_channel (rsp_xbar_demux_src0_channel), // .channel
.sink0_data (rsp_xbar_demux_src0_data), // .data
.sink0_startofpacket (rsp_xbar_demux_src0_startofpacket), // .startofpacket
.sink0_endofpacket (rsp_xbar_demux_src0_endofpacket), // .endofpacket
.sink1_ready (rsp_xbar_demux_001_src0_ready), // sink1.ready
.sink1_valid (rsp_xbar_demux_001_src0_valid), // .valid
.sink1_channel (rsp_xbar_demux_001_src0_channel), // .channel
.sink1_data (rsp_xbar_demux_001_src0_data), // .data
.sink1_startofpacket (rsp_xbar_demux_001_src0_startofpacket), // .startofpacket
.sink1_endofpacket (rsp_xbar_demux_001_src0_endofpacket), // .endofpacket
.sink2_ready (rsp_xbar_demux_002_src0_ready), // sink2.ready
.sink2_valid (rsp_xbar_demux_002_src0_valid), // .valid
.sink2_channel (rsp_xbar_demux_002_src0_channel), // .channel
.sink2_data (rsp_xbar_demux_002_src0_data), // .data
.sink2_startofpacket (rsp_xbar_demux_002_src0_startofpacket), // .startofpacket
.sink2_endofpacket (rsp_xbar_demux_002_src0_endofpacket), // .endofpacket
.sink3_ready (rsp_xbar_demux_003_src0_ready), // sink3.ready
.sink3_valid (rsp_xbar_demux_003_src0_valid), // .valid
.sink3_channel (rsp_xbar_demux_003_src0_channel), // .channel
.sink3_data (rsp_xbar_demux_003_src0_data), // .data
.sink3_startofpacket (rsp_xbar_demux_003_src0_startofpacket), // .startofpacket
.sink3_endofpacket (rsp_xbar_demux_003_src0_endofpacket), // .endofpacket
.sink4_ready (rsp_xbar_demux_004_src0_ready), // sink4.ready
.sink4_valid (rsp_xbar_demux_004_src0_valid), // .valid
.sink4_channel (rsp_xbar_demux_004_src0_channel), // .channel
.sink4_data (rsp_xbar_demux_004_src0_data), // .data
.sink4_startofpacket (rsp_xbar_demux_004_src0_startofpacket), // .startofpacket
.sink4_endofpacket (rsp_xbar_demux_004_src0_endofpacket), // .endofpacket
.sink5_ready (rsp_xbar_demux_005_src0_ready), // sink5.ready
.sink5_valid (rsp_xbar_demux_005_src0_valid), // .valid
.sink5_channel (rsp_xbar_demux_005_src0_channel), // .channel
.sink5_data (rsp_xbar_demux_005_src0_data), // .data
.sink5_startofpacket (rsp_xbar_demux_005_src0_startofpacket), // .startofpacket
.sink5_endofpacket (rsp_xbar_demux_005_src0_endofpacket) // .endofpacket
);
SoC_rsp_xbar_mux_001 rsp_xbar_mux_001 (
.clk (clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.src_ready (rsp_xbar_mux_001_src_ready), // src.ready
.src_valid (rsp_xbar_mux_001_src_valid), // .valid
.src_data (rsp_xbar_mux_001_src_data), // .data
.src_channel (rsp_xbar_mux_001_src_channel), // .channel
.src_startofpacket (rsp_xbar_mux_001_src_startofpacket), // .startofpacket
.src_endofpacket (rsp_xbar_mux_001_src_endofpacket), // .endofpacket
.sink0_ready (rsp_xbar_demux_src1_ready), // sink0.ready
.sink0_valid (rsp_xbar_demux_src1_valid), // .valid
.sink0_channel (rsp_xbar_demux_src1_channel), // .channel
.sink0_data (rsp_xbar_demux_src1_data), // .data
.sink0_startofpacket (rsp_xbar_demux_src1_startofpacket), // .startofpacket
.sink0_endofpacket (rsp_xbar_demux_src1_endofpacket), // .endofpacket
.sink1_ready (rsp_xbar_demux_003_src1_ready), // sink1.ready
.sink1_valid (rsp_xbar_demux_003_src1_valid), // .valid
.sink1_channel (rsp_xbar_demux_003_src1_channel), // .channel
.sink1_data (rsp_xbar_demux_003_src1_data), // .data
.sink1_startofpacket (rsp_xbar_demux_003_src1_startofpacket), // .startofpacket
.sink1_endofpacket (rsp_xbar_demux_003_src1_endofpacket), // .endofpacket
.sink2_ready (rsp_xbar_demux_004_src1_ready), // sink2.ready
.sink2_valid (rsp_xbar_demux_004_src1_valid), // .valid
.sink2_channel (rsp_xbar_demux_004_src1_channel), // .channel
.sink2_data (rsp_xbar_demux_004_src1_data), // .data
.sink2_startofpacket (rsp_xbar_demux_004_src1_startofpacket), // .startofpacket
.sink2_endofpacket (rsp_xbar_demux_004_src1_endofpacket), // .endofpacket
.sink3_ready (rsp_xbar_demux_005_src1_ready), // sink3.ready
.sink3_valid (rsp_xbar_demux_005_src1_valid), // .valid
.sink3_channel (rsp_xbar_demux_005_src1_channel), // .channel
.sink3_data (rsp_xbar_demux_005_src1_data), // .data
.sink3_startofpacket (rsp_xbar_demux_005_src1_startofpacket), // .startofpacket
.sink3_endofpacket (rsp_xbar_demux_005_src1_endofpacket) // .endofpacket
);
SoC_irq_mapper irq_mapper (
.clk (clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.receiver0_irq (irq_mapper_receiver0_irq), // receiver0.irq
.sender_irq (nios_d_irq_irq) // sender.irq
);
endmodule
|
module outputs
wire [63 : 0] from_master_rdata,
to_slave_araddr,
to_slave_awaddr,
to_slave_wdata;
wire [7 : 0] to_slave_arlen, to_slave_awlen, to_slave_wstrb;
wire [3 : 0] from_master_bid,
from_master_rid,
to_slave_arcache,
to_slave_arid,
to_slave_arqos,
to_slave_arregion,
to_slave_awcache,
to_slave_awid,
to_slave_awqos,
to_slave_awregion;
wire [2 : 0] to_slave_arprot,
to_slave_arsize,
to_slave_awprot,
to_slave_awsize;
wire [1 : 0] from_master_bresp,
from_master_rresp,
to_slave_arburst,
to_slave_awburst;
wire RDY_reset,
from_master_arready,
from_master_awready,
from_master_bvalid,
from_master_rlast,
from_master_rvalid,
from_master_wready,
to_slave_arlock,
to_slave_arvalid,
to_slave_awlock,
to_slave_awvalid,
to_slave_bready,
to_slave_rready,
to_slave_wlast,
to_slave_wvalid;
// register m_rg_ar_beat_count
reg [7 : 0] m_rg_ar_beat_count;
wire [7 : 0] m_rg_ar_beat_count$D_IN;
wire m_rg_ar_beat_count$EN;
// register m_rg_b_beat_count
reg [7 : 0] m_rg_b_beat_count;
wire [7 : 0] m_rg_b_beat_count$D_IN;
wire m_rg_b_beat_count$EN;
// register m_rg_b_resp
reg [1 : 0] m_rg_b_resp;
wire [1 : 0] m_rg_b_resp$D_IN;
wire m_rg_b_resp$EN;
// register m_rg_last_beat_raddr
reg [63 : 0] m_rg_last_beat_raddr;
wire [63 : 0] m_rg_last_beat_raddr$D_IN;
wire m_rg_last_beat_raddr$EN;
// register m_rg_last_beat_waddr
reg [63 : 0] m_rg_last_beat_waddr;
wire [63 : 0] m_rg_last_beat_waddr$D_IN;
wire m_rg_last_beat_waddr$EN;
// register m_rg_r_beat_count
reg [7 : 0] m_rg_r_beat_count;
wire [7 : 0] m_rg_r_beat_count$D_IN;
wire m_rg_r_beat_count$EN;
// register m_rg_reset
reg m_rg_reset;
wire m_rg_reset$D_IN, m_rg_reset$EN;
// register m_rg_w_beat_count
reg [7 : 0] m_rg_w_beat_count;
wire [7 : 0] m_rg_w_beat_count$D_IN;
wire m_rg_w_beat_count$EN;
// ports of submodule m_f_r_arlen
wire [7 : 0] m_f_r_arlen$D_IN, m_f_r_arlen$D_OUT;
wire m_f_r_arlen$CLR,
m_f_r_arlen$DEQ,
m_f_r_arlen$EMPTY_N,
m_f_r_arlen$ENQ,
m_f_r_arlen$FULL_N;
// ports of submodule m_f_w_awlen
wire [7 : 0] m_f_w_awlen$D_IN, m_f_w_awlen$D_OUT;
wire m_f_w_awlen$CLR,
m_f_w_awlen$DEQ,
m_f_w_awlen$EMPTY_N,
m_f_w_awlen$ENQ,
m_f_w_awlen$FULL_N;
// ports of submodule m_xactor_from_master_f_rd_addr
wire [96 : 0] m_xactor_from_master_f_rd_addr$D_IN,
m_xactor_from_master_f_rd_addr$D_OUT;
wire m_xactor_from_master_f_rd_addr$CLR,
m_xactor_from_master_f_rd_addr$DEQ,
m_xactor_from_master_f_rd_addr$EMPTY_N,
m_xactor_from_master_f_rd_addr$ENQ,
m_xactor_from_master_f_rd_addr$FULL_N;
// ports of submodule m_xactor_from_master_f_rd_data
wire [70 : 0] m_xactor_from_master_f_rd_data$D_IN,
m_xactor_from_master_f_rd_data$D_OUT;
wire m_xactor_from_master_f_rd_data$CLR,
m_xactor_from_master_f_rd_data$DEQ,
m_xactor_from_master_f_rd_data$EMPTY_N,
m_xactor_from_master_f_rd_data$ENQ,
m_xactor_from_master_f_rd_data$FULL_N;
// ports of submodule m_xactor_from_master_f_wr_addr
wire [96 : 0] m_xactor_from_master_f_wr_addr$D_IN,
m_xactor_from_master_f_wr_addr$D_OUT;
wire m_xactor_from_master_f_wr_addr$CLR,
m_xactor_from_master_f_wr_addr$DEQ,
m_xactor_from_master_f_wr_addr$EMPTY_N,
m_xactor_from_master_f_wr_addr$ENQ,
m_xactor_from_master_f_wr_addr$FULL_N;
// ports of submodule m_xactor_from_master_f_wr_data
wire [72 : 0] m_xactor_from_master_f_wr_data$D_IN,
m_xactor_from_master_f_wr_data$D_OUT;
wire m_xactor_from_master_f_wr_data$CLR,
m_xactor_from_master_f_wr_data$DEQ,
m_xactor_from_master_f_wr_data$EMPTY_N,
m_xactor_from_master_f_wr_data$ENQ,
m_xactor_from_master_f_wr_data$FULL_N;
// ports of submodule m_xactor_from_master_f_wr_resp
wire [5 : 0] m_xactor_from_master_f_wr_resp$D_IN,
m_xactor_from_master_f_wr_resp$D_OUT;
wire m_xactor_from_master_f_wr_resp$CLR,
m_xactor_from_master_f_wr_resp$DEQ,
m_xactor_from_master_f_wr_resp$EMPTY_N,
m_xactor_from_master_f_wr_resp$ENQ,
m_xactor_from_master_f_wr_resp$FULL_N;
// ports of submodule m_xactor_to_slave_f_rd_addr
wire [96 : 0] m_xactor_to_slave_f_rd_addr$D_IN,
m_xactor_to_slave_f_rd_addr$D_OUT;
wire m_xactor_to_slave_f_rd_addr$CLR,
m_xactor_to_slave_f_rd_addr$DEQ,
m_xactor_to_slave_f_rd_addr$EMPTY_N,
m_xactor_to_slave_f_rd_addr$ENQ,
m_xactor_to_slave_f_rd_addr$FULL_N;
// ports of submodule m_xactor_to_slave_f_rd_data
wire [70 : 0] m_xactor_to_slave_f_rd_data$D_IN,
m_xactor_to_slave_f_rd_data$D_OUT;
wire m_xactor_to_slave_f_rd_data$CLR,
m_xactor_to_slave_f_rd_data$DEQ,
m_xactor_to_slave_f_rd_data$EMPTY_N,
m_xactor_to_slave_f_rd_data$ENQ,
m_xactor_to_slave_f_rd_data$FULL_N;
// ports of submodule m_xactor_to_slave_f_wr_addr
wire [96 : 0] m_xactor_to_slave_f_wr_addr$D_IN,
m_xactor_to_slave_f_wr_addr$D_OUT;
wire m_xactor_to_slave_f_wr_addr$CLR,
m_xactor_to_slave_f_wr_addr$DEQ,
m_xactor_to_slave_f_wr_addr$EMPTY_N,
m_xactor_to_slave_f_wr_addr$ENQ,
m_xactor_to_slave_f_wr_addr$FULL_N;
// ports of submodule m_xactor_to_slave_f_wr_data
wire [72 : 0] m_xactor_to_slave_f_wr_data$D_IN,
m_xactor_to_slave_f_wr_data$D_OUT;
wire m_xactor_to_slave_f_wr_data$CLR,
m_xactor_to_slave_f_wr_data$DEQ,
m_xactor_to_slave_f_wr_data$EMPTY_N,
m_xactor_to_slave_f_wr_data$ENQ,
m_xactor_to_slave_f_wr_data$FULL_N;
// ports of submodule m_xactor_to_slave_f_wr_resp
wire [5 : 0] m_xactor_to_slave_f_wr_resp$D_IN,
m_xactor_to_slave_f_wr_resp$D_OUT;
wire m_xactor_to_slave_f_wr_resp$CLR,
m_xactor_to_slave_f_wr_resp$DEQ,
m_xactor_to_slave_f_wr_resp$EMPTY_N,
m_xactor_to_slave_f_wr_resp$ENQ,
m_xactor_to_slave_f_wr_resp$FULL_N;
// rule scheduling signals
wire CAN_FIRE_RL_m_rl_rd_resp_slave_to_master,
CAN_FIRE_RL_m_rl_rd_xaction_master_to_slave,
CAN_FIRE_RL_m_rl_reset,
CAN_FIRE_RL_m_rl_wr_resp_slave_to_master,
CAN_FIRE_RL_m_rl_wr_xaction_master_to_slave,
CAN_FIRE_from_master_m_arvalid,
CAN_FIRE_from_master_m_awvalid,
CAN_FIRE_from_master_m_bready,
CAN_FIRE_from_master_m_rready,
CAN_FIRE_from_master_m_wvalid,
CAN_FIRE_reset,
CAN_FIRE_to_slave_m_arready,
CAN_FIRE_to_slave_m_awready,
CAN_FIRE_to_slave_m_bvalid,
CAN_FIRE_to_slave_m_rvalid,
CAN_FIRE_to_slave_m_wready,
WILL_FIRE_RL_m_rl_rd_resp_slave_to_master,
WILL_FIRE_RL_m_rl_rd_xaction_master_to_slave,
WILL_FIRE_RL_m_rl_reset,
WILL_FIRE_RL_m_rl_wr_resp_slave_to_master,
WILL_FIRE_RL_m_rl_wr_xaction_master_to_slave,
WILL_FIRE_from_master_m_arvalid,
WILL_FIRE_from_master_m_awvalid,
WILL_FIRE_from_master_m_bready,
WILL_FIRE_from_master_m_rready,
WILL_FIRE_from_master_m_wvalid,
WILL_FIRE_reset,
WILL_FIRE_to_slave_m_arready,
WILL_FIRE_to_slave_m_awready,
WILL_FIRE_to_slave_m_bvalid,
WILL_FIRE_to_slave_m_rvalid,
WILL_FIRE_to_slave_m_wready;
// inputs to muxes for submodule ports
wire [7 : 0] MUX_m_rg_ar_beat_count$write_1__VAL_2,
MUX_m_rg_b_beat_count$write_1__VAL_2,
MUX_m_rg_r_beat_count$write_1__VAL_2,
MUX_m_rg_w_beat_count$write_1__VAL_2;
wire [1 : 0] MUX_m_rg_b_resp$write_1__VAL_2;
wire MUX_m_rg_b_resp$write_1__SEL_2;
// declarations used by system tasks
// synopsys translate_off
reg [31 : 0] v__h2464;
reg [31 : 0] v__h2458;
// synopsys translate_on
// remaining internal signals
wire [63 : 0] a_out_araddr__h3025,
a_out_awaddr__h1941,
addr___1__h2035,
addr___1__h3119,
addr__h2023,
addr__h3107,
burst_len__h2024,
burst_len__h3108,
wrap_mask__h2025,
wrap_mask__h3109,
x__h2047,
x__h3131,
y__h2048,
y__h2049,
y__h3132,
y__h3133;
wire [7 : 0] x__h2322, x__h2829, x__h3316, x__h3535;
wire m_rg_ar_beat_count_9_ULT_m_xactor_from_master__ETC___d110,
m_rg_b_beat_count_5_ULT_m_f_w_awlen_first__6___d57,
m_rg_r_beat_count_19_ULT_m_f_r_arlen_first__20___d121,
m_rg_w_beat_count_ULT_m_xactor_from_master_f_w_ETC___d42;
// action method reset
assign RDY_reset = !m_rg_reset ;
assign CAN_FIRE_reset = !m_rg_reset ;
assign WILL_FIRE_reset = EN_reset ;
// action method from_master_m_awvalid
assign CAN_FIRE_from_master_m_awvalid = 1'd1 ;
assign WILL_FIRE_from_master_m_awvalid = 1'd1 ;
// value method from_master_m_awready
assign from_master_awready = m_xactor_from_master_f_wr_addr$FULL_N ;
// action method from_master_m_wvalid
assign CAN_FIRE_from_master_m_wvalid = 1'd1 ;
assign WILL_FIRE_from_master_m_wvalid = 1'd1 ;
// value method from_master_m_wready
assign from_master_wready = m_xactor_from_master_f_wr_data$FULL_N ;
// value method from_master_m_bvalid
assign from_master_bvalid = m_xactor_from_master_f_wr_resp$EMPTY_N ;
// value method from_master_m_bid
assign from_master_bid = m_xactor_from_master_f_wr_resp$D_OUT[5:2] ;
// value method from_master_m_bresp
assign from_master_bresp = m_xactor_from_master_f_wr_resp$D_OUT[1:0] ;
// action method from_master_m_bready
assign CAN_FIRE_from_master_m_bready = 1'd1 ;
assign WILL_FIRE_from_master_m_bready = 1'd1 ;
// action method from_master_m_arvalid
assign CAN_FIRE_from_master_m_arvalid = 1'd1 ;
assign WILL_FIRE_from_master_m_arvalid = 1'd1 ;
// value method from_master_m_arready
assign from_master_arready = m_xactor_from_master_f_rd_addr$FULL_N ;
// value method from_master_m_rvalid
assign from_master_rvalid = m_xactor_from_master_f_rd_data$EMPTY_N ;
// value method from_master_m_rid
assign from_master_rid = m_xactor_from_master_f_rd_data$D_OUT[70:67] ;
// value method from_master_m_rdata
assign from_master_rdata = m_xactor_from_master_f_rd_data$D_OUT[66:3] ;
// value method from_master_m_rresp
assign from_master_rresp = m_xactor_from_master_f_rd_data$D_OUT[2:1] ;
// value method from_master_m_rlast
assign from_master_rlast = m_xactor_from_master_f_rd_data$D_OUT[0] ;
// action method from_master_m_rready
assign CAN_FIRE_from_master_m_rready = 1'd1 ;
assign WILL_FIRE_from_master_m_rready = 1'd1 ;
// value method to_slave_m_awvalid
assign to_slave_awvalid = m_xactor_to_slave_f_wr_addr$EMPTY_N ;
// value method to_slave_m_awid
assign to_slave_awid = m_xactor_to_slave_f_wr_addr$D_OUT[96:93] ;
// value method to_slave_m_awaddr
assign to_slave_awaddr = m_xactor_to_slave_f_wr_addr$D_OUT[92:29] ;
// value method to_slave_m_awlen
assign to_slave_awlen = m_xactor_to_slave_f_wr_addr$D_OUT[28:21] ;
// value method to_slave_m_awsize
assign to_slave_awsize = m_xactor_to_slave_f_wr_addr$D_OUT[20:18] ;
// value method to_slave_m_awburst
assign to_slave_awburst = m_xactor_to_slave_f_wr_addr$D_OUT[17:16] ;
// value method to_slave_m_awlock
assign to_slave_awlock = m_xactor_to_slave_f_wr_addr$D_OUT[15] ;
// value method to_slave_m_awcache
assign to_slave_awcache = m_xactor_to_slave_f_wr_addr$D_OUT[14:11] ;
// value method to_slave_m_awprot
assign to_slave_awprot = m_xactor_to_slave_f_wr_addr$D_OUT[10:8] ;
// value method to_slave_m_awqos
assign to_slave_awqos = m_xactor_to_slave_f_wr_addr$D_OUT[7:4] ;
// value method to_slave_m_awregion
assign to_slave_awregion = m_xactor_to_slave_f_wr_addr$D_OUT[3:0] ;
// action method to_slave_m_awready
assign CAN_FIRE_to_slave_m_awready = 1'd1 ;
assign WILL_FIRE_to_slave_m_awready = 1'd1 ;
// value method to_slave_m_wvalid
assign to_slave_wvalid = m_xactor_to_slave_f_wr_data$EMPTY_N ;
// value method to_slave_m_wdata
assign to_slave_wdata = m_xactor_to_slave_f_wr_data$D_OUT[72:9] ;
// value method to_slave_m_wstrb
assign to_slave_wstrb = m_xactor_to_slave_f_wr_data$D_OUT[8:1] ;
// value method to_slave_m_wlast
assign to_slave_wlast = m_xactor_to_slave_f_wr_data$D_OUT[0] ;
// action method to_slave_m_wready
assign CAN_FIRE_to_slave_m_wready = 1'd1 ;
assign WILL_FIRE_to_slave_m_wready = 1'd1 ;
// action method to_slave_m_bvalid
assign CAN_FIRE_to_slave_m_bvalid = 1'd1 ;
assign WILL_FIRE_to_slave_m_bvalid = 1'd1 ;
// value method to_slave_m_bready
assign to_slave_bready = m_xactor_to_slave_f_wr_resp$FULL_N ;
// value method to_slave_m_arvalid
assign to_slave_arvalid = m_xactor_to_slave_f_rd_addr$EMPTY_N ;
// value method to_slave_m_arid
assign to_slave_arid = m_xactor_to_slave_f_rd_addr$D_OUT[96:93] ;
// value method to_slave_m_araddr
assign to_slave_araddr = m_xactor_to_slave_f_rd_addr$D_OUT[92:29] ;
// value method to_slave_m_arlen
assign to_slave_arlen = m_xactor_to_slave_f_rd_addr$D_OUT[28:21] ;
// value method to_slave_m_arsize
assign to_slave_arsize = m_xactor_to_slave_f_rd_addr$D_OUT[20:18] ;
// value method to_slave_m_arburst
assign to_slave_arburst = m_xactor_to_slave_f_rd_addr$D_OUT[17:16] ;
// value method to_slave_m_arlock
assign to_slave_arlock = m_xactor_to_slave_f_rd_addr$D_OUT[15] ;
// value method to_slave_m_arcache
assign to_slave_arcache = m_xactor_to_slave_f_rd_addr$D_OUT[14:11] ;
// value method to_slave_m_arprot
assign to_slave_arprot = m_xactor_to_slave_f_rd_addr$D_OUT[10:8] ;
// value method to_slave_m_arqos
assign to_slave_arqos = m_xactor_to_slave_f_rd_addr$D_OUT[7:4] ;
// value method to_slave_m_arregion
assign to_slave_arregion = m_xactor_to_slave_f_rd_addr$D_OUT[3:0] ;
// action method to_slave_m_arready
assign CAN_FIRE_to_slave_m_arready = 1'd1 ;
assign WILL_FIRE_to_slave_m_arready = 1'd1 ;
// action method to_slave_m_rvalid
assign CAN_FIRE_to_slave_m_rvalid = 1'd1 ;
assign WILL_FIRE_to_slave_m_rvalid = 1'd1 ;
// value method to_slave_m_rready
assign to_slave_rready = m_xactor_to_slave_f_rd_data$FULL_N ;
// submodule m_f_r_arlen
SizedFIFO #(.p1width(32'd8),
.p2depth(32'd4),
.p3cntr_width(32'd2),
.guarded(1'd1)) m_f_r_arlen(.RST(RST_N),
.CLK(CLK),
.D_IN(m_f_r_arlen$D_IN),
.ENQ(m_f_r_arlen$ENQ),
.DEQ(m_f_r_arlen$DEQ),
.CLR(m_f_r_arlen$CLR),
.D_OUT(m_f_r_arlen$D_OUT),
.FULL_N(m_f_r_arlen$FULL_N),
.EMPTY_N(m_f_r_arlen$EMPTY_N));
// submodule m_f_w_awlen
SizedFIFO #(.p1width(32'd8),
.p2depth(32'd4),
.p3cntr_width(32'd2),
.guarded(1'd1)) m_f_w_awlen(.RST(RST_N),
.CLK(CLK),
.D_IN(m_f_w_awlen$D_IN),
.ENQ(m_f_w_awlen$ENQ),
.DEQ(m_f_w_awlen$DEQ),
.CLR(m_f_w_awlen$CLR),
.D_OUT(m_f_w_awlen$D_OUT),
.FULL_N(m_f_w_awlen$FULL_N),
.EMPTY_N(m_f_w_awlen$EMPTY_N));
// submodule m_xactor_from_master_f_rd_addr
FIFO2 #(.width(32'd97),
.guarded(1'd1)) m_xactor_from_master_f_rd_addr(.RST(RST_N),
.CLK(CLK),
.D_IN(m_xactor_from_master_f_rd_addr$D_IN),
.ENQ(m_xactor_from_master_f_rd_addr$ENQ),
.DEQ(m_xactor_from_master_f_rd_addr$DEQ),
.CLR(m_xactor_from_master_f_rd_addr$CLR),
.D_OUT(m_xactor_from_master_f_rd_addr$D_OUT),
.FULL_N(m_xactor_from_master_f_rd_addr$FULL_N),
.EMPTY_N(m_xactor_from_master_f_rd_addr$EMPTY_N));
// submodule m_xactor_from_master_f_rd_data
FIFO2 #(.width(32'd71),
.guarded(1'd1)) m_xactor_from_master_f_rd_data(.RST(RST_N),
.CLK(CLK),
.D_IN(m_xactor_from_master_f_rd_data$D_IN),
.ENQ(m_xactor_from_master_f_rd_data$ENQ),
.DEQ(m_xactor_from_master_f_rd_data$DEQ),
.CLR(m_xactor_from_master_f_rd_data$CLR),
.D_OUT(m_xactor_from_master_f_rd_data$D_OUT),
.FULL_N(m_xactor_from_master_f_rd_data$FULL_N),
.EMPTY_N(m_xactor_from_master_f_rd_data$EMPTY_N));
// submodule m_xactor_from_master_f_wr_addr
FIFO2 #(.width(32'd97),
.guarded(1'd1)) m_xactor_from_master_f_wr_addr(.RST(RST_N),
.CLK(CLK),
.D_IN(m_xactor_from_master_f_wr_addr$D_IN),
.ENQ(m_xactor_from_master_f_wr_addr$ENQ),
.DEQ(m_xactor_from_master_f_wr_addr$DEQ),
.CLR(m_xactor_from_master_f_wr_addr$CLR),
.D_OUT(m_xactor_from_master_f_wr_addr$D_OUT),
.FULL_N(m_xactor_from_master_f_wr_addr$FULL_N),
.EMPTY_N(m_xactor_from_master_f_wr_addr$EMPTY_N));
// submodule m_xactor_from_master_f_wr_data
FIFO2 #(.width(32'd73),
.guarded(1'd1)) m_xactor_from_master_f_wr_data(.RST(RST_N),
.CLK(CLK),
.D_IN(m_xactor_from_master_f_wr_data$D_IN),
.ENQ(m_xactor_from_master_f_wr_data$ENQ),
.DEQ(m_xactor_from_master_f_wr_data$DEQ),
.CLR(m_xactor_from_master_f_wr_data$CLR),
.D_OUT(m_xactor_from_master_f_wr_data$D_OUT),
.FULL_N(m_xactor_from_master_f_wr_data$FULL_N),
.EMPTY_N(m_xactor_from_master_f_wr_data$EMPTY_N));
// submodule m_xactor_from_master_f_wr_resp
FIFO2 #(.width(32'd6),
.guarded(1'd1)) m_xactor_from_master_f_wr_resp(.RST(RST_N),
.CLK(CLK),
.D_IN(m_xactor_from_master_f_wr_resp$D_IN),
.ENQ(m_xactor_from_master_f_wr_resp$ENQ),
.DEQ(m_xactor_from_master_f_wr_resp$DEQ),
.CLR(m_xactor_from_master_f_wr_resp$CLR),
.D_OUT(m_xactor_from_master_f_wr_resp$D_OUT),
.FULL_N(m_xactor_from_master_f_wr_resp$FULL_N),
.EMPTY_N(m_xactor_from_master_f_wr_resp$EMPTY_N));
// submodule m_xactor_to_slave_f_rd_addr
FIFO2 #(.width(32'd97),
.guarded(1'd1)) m_xactor_to_slave_f_rd_addr(.RST(RST_N),
.CLK(CLK),
.D_IN(m_xactor_to_slave_f_rd_addr$D_IN),
.ENQ(m_xactor_to_slave_f_rd_addr$ENQ),
.DEQ(m_xactor_to_slave_f_rd_addr$DEQ),
.CLR(m_xactor_to_slave_f_rd_addr$CLR),
.D_OUT(m_xactor_to_slave_f_rd_addr$D_OUT),
.FULL_N(m_xactor_to_slave_f_rd_addr$FULL_N),
.EMPTY_N(m_xactor_to_slave_f_rd_addr$EMPTY_N));
// submodule m_xactor_to_slave_f_rd_data
FIFO2 #(.width(32'd71),
.guarded(1'd1)) m_xactor_to_slave_f_rd_data(.RST(RST_N),
.CLK(CLK),
.D_IN(m_xactor_to_slave_f_rd_data$D_IN),
.ENQ(m_xactor_to_slave_f_rd_data$ENQ),
.DEQ(m_xactor_to_slave_f_rd_data$DEQ),
.CLR(m_xactor_to_slave_f_rd_data$CLR),
.D_OUT(m_xactor_to_slave_f_rd_data$D_OUT),
.FULL_N(m_xactor_to_slave_f_rd_data$FULL_N),
.EMPTY_N(m_xactor_to_slave_f_rd_data$EMPTY_N));
// submodule m_xactor_to_slave_f_wr_addr
FIFO2 #(.width(32'd97),
.guarded(1'd1)) m_xactor_to_slave_f_wr_addr(.RST(RST_N),
.CLK(CLK),
.D_IN(m_xactor_to_slave_f_wr_addr$D_IN),
.ENQ(m_xactor_to_slave_f_wr_addr$ENQ),
.DEQ(m_xactor_to_slave_f_wr_addr$DEQ),
.CLR(m_xactor_to_slave_f_wr_addr$CLR),
.D_OUT(m_xactor_to_slave_f_wr_addr$D_OUT),
.FULL_N(m_xactor_to_slave_f_wr_addr$FULL_N),
.EMPTY_N(m_xactor_to_slave_f_wr_addr$EMPTY_N));
// submodule m_xactor_to_slave_f_wr_data
FIFO2 #(.width(32'd73),
.guarded(1'd1)) m_xactor_to_slave_f_wr_data(.RST(RST_N),
.CLK(CLK),
.D_IN(m_xactor_to_slave_f_wr_data$D_IN),
.ENQ(m_xactor_to_slave_f_wr_data$ENQ),
.DEQ(m_xactor_to_slave_f_wr_data$DEQ),
.CLR(m_xactor_to_slave_f_wr_data$CLR),
.D_OUT(m_xactor_to_slave_f_wr_data$D_OUT),
.FULL_N(m_xactor_to_slave_f_wr_data$FULL_N),
.EMPTY_N(m_xactor_to_slave_f_wr_data$EMPTY_N));
// submodule m_xactor_to_slave_f_wr_resp
FIFO2 #(.width(32'd6),
.guarded(1'd1)) m_xactor_to_slave_f_wr_resp(.RST(RST_N),
.CLK(CLK),
.D_IN(m_xactor_to_slave_f_wr_resp$D_IN),
.ENQ(m_xactor_to_slave_f_wr_resp$ENQ),
.DEQ(m_xactor_to_slave_f_wr_resp$DEQ),
.CLR(m_xactor_to_slave_f_wr_resp$CLR),
.D_OUT(m_xactor_to_slave_f_wr_resp$D_OUT),
.FULL_N(m_xactor_to_slave_f_wr_resp$FULL_N),
.EMPTY_N(m_xactor_to_slave_f_wr_resp$EMPTY_N));
// rule RL_m_rl_wr_xaction_master_to_slave
assign CAN_FIRE_RL_m_rl_wr_xaction_master_to_slave =
m_xactor_to_slave_f_wr_addr$FULL_N &&
m_xactor_from_master_f_wr_addr$EMPTY_N &&
m_xactor_to_slave_f_wr_data$FULL_N &&
m_xactor_from_master_f_wr_data$EMPTY_N &&
(m_rg_w_beat_count != 8'd0 || m_f_w_awlen$FULL_N) ;
assign WILL_FIRE_RL_m_rl_wr_xaction_master_to_slave =
CAN_FIRE_RL_m_rl_wr_xaction_master_to_slave ;
// rule RL_m_rl_wr_resp_slave_to_master
assign CAN_FIRE_RL_m_rl_wr_resp_slave_to_master =
m_xactor_to_slave_f_wr_resp$EMPTY_N && m_f_w_awlen$EMPTY_N &&
(m_rg_b_beat_count_5_ULT_m_f_w_awlen_first__6___d57 ||
m_xactor_from_master_f_wr_resp$FULL_N) ;
assign WILL_FIRE_RL_m_rl_wr_resp_slave_to_master =
CAN_FIRE_RL_m_rl_wr_resp_slave_to_master ;
// rule RL_m_rl_rd_xaction_master_to_slave
assign CAN_FIRE_RL_m_rl_rd_xaction_master_to_slave =
m_xactor_to_slave_f_rd_addr$FULL_N &&
m_xactor_from_master_f_rd_addr$EMPTY_N &&
(m_rg_ar_beat_count != 8'd0 || m_f_r_arlen$FULL_N) ;
assign WILL_FIRE_RL_m_rl_rd_xaction_master_to_slave =
CAN_FIRE_RL_m_rl_rd_xaction_master_to_slave ;
// rule RL_m_rl_rd_resp_slave_to_master
assign CAN_FIRE_RL_m_rl_rd_resp_slave_to_master =
m_xactor_to_slave_f_rd_data$EMPTY_N && m_f_r_arlen$EMPTY_N &&
m_xactor_from_master_f_rd_data$FULL_N ;
assign WILL_FIRE_RL_m_rl_rd_resp_slave_to_master =
CAN_FIRE_RL_m_rl_rd_resp_slave_to_master ;
// rule RL_m_rl_reset
assign CAN_FIRE_RL_m_rl_reset = m_rg_reset ;
assign WILL_FIRE_RL_m_rl_reset = m_rg_reset ;
// inputs to muxes for submodule ports
assign MUX_m_rg_b_resp$write_1__SEL_2 =
WILL_FIRE_RL_m_rl_wr_resp_slave_to_master &&
(m_rg_b_resp == 2'b0 &&
m_xactor_to_slave_f_wr_resp$D_OUT[1:0] != 2'b0 ||
!m_rg_b_beat_count_5_ULT_m_f_w_awlen_first__6___d57) ;
assign MUX_m_rg_ar_beat_count$write_1__VAL_2 =
m_rg_ar_beat_count_9_ULT_m_xactor_from_master__ETC___d110 ?
x__h3316 :
8'd0 ;
assign MUX_m_rg_b_beat_count$write_1__VAL_2 =
m_rg_b_beat_count_5_ULT_m_f_w_awlen_first__6___d57 ?
x__h2829 :
8'd0 ;
assign MUX_m_rg_b_resp$write_1__VAL_2 =
m_rg_b_beat_count_5_ULT_m_f_w_awlen_first__6___d57 ?
m_xactor_to_slave_f_wr_resp$D_OUT[1:0] :
2'b0 ;
assign MUX_m_rg_r_beat_count$write_1__VAL_2 =
m_rg_r_beat_count_19_ULT_m_f_r_arlen_first__20___d121 ?
x__h3535 :
8'd0 ;
assign MUX_m_rg_w_beat_count$write_1__VAL_2 =
m_rg_w_beat_count_ULT_m_xactor_from_master_f_w_ETC___d42 ?
x__h2322 :
8'd0 ;
// register m_rg_ar_beat_count
assign m_rg_ar_beat_count$D_IN =
m_rg_reset ? 8'd0 : MUX_m_rg_ar_beat_count$write_1__VAL_2 ;
assign m_rg_ar_beat_count$EN =
WILL_FIRE_RL_m_rl_rd_xaction_master_to_slave || m_rg_reset ;
// register m_rg_b_beat_count
assign m_rg_b_beat_count$D_IN =
m_rg_reset ? 8'd0 : MUX_m_rg_b_beat_count$write_1__VAL_2 ;
assign m_rg_b_beat_count$EN =
WILL_FIRE_RL_m_rl_wr_resp_slave_to_master || m_rg_reset ;
// register m_rg_b_resp
assign m_rg_b_resp$D_IN =
m_rg_reset ? 2'b0 : MUX_m_rg_b_resp$write_1__VAL_2 ;
assign m_rg_b_resp$EN = MUX_m_rg_b_resp$write_1__SEL_2 || m_rg_reset ;
// register m_rg_last_beat_raddr
assign m_rg_last_beat_raddr$D_IN = a_out_araddr__h3025 ;
assign m_rg_last_beat_raddr$EN =
CAN_FIRE_RL_m_rl_rd_xaction_master_to_slave ;
// register m_rg_last_beat_waddr
assign m_rg_last_beat_waddr$D_IN = a_out_awaddr__h1941 ;
assign m_rg_last_beat_waddr$EN =
CAN_FIRE_RL_m_rl_wr_xaction_master_to_slave ;
// register m_rg_r_beat_count
assign m_rg_r_beat_count$D_IN =
m_rg_reset ? 8'd0 : MUX_m_rg_r_beat_count$write_1__VAL_2 ;
assign m_rg_r_beat_count$EN =
WILL_FIRE_RL_m_rl_rd_resp_slave_to_master || m_rg_reset ;
// register m_rg_reset
assign m_rg_reset$D_IN = !m_rg_reset ;
assign m_rg_reset$EN = m_rg_reset || EN_reset ;
// register m_rg_w_beat_count
assign m_rg_w_beat_count$D_IN =
m_rg_reset ? 8'd0 : MUX_m_rg_w_beat_count$write_1__VAL_2 ;
assign m_rg_w_beat_count$EN =
WILL_FIRE_RL_m_rl_wr_xaction_master_to_slave || m_rg_reset ;
// submodule m_f_r_arlen
assign m_f_r_arlen$D_IN = m_xactor_from_master_f_rd_addr$D_OUT[28:21] ;
assign m_f_r_arlen$ENQ =
WILL_FIRE_RL_m_rl_rd_xaction_master_to_slave &&
m_rg_ar_beat_count == 8'd0 ;
assign m_f_r_arlen$DEQ =
WILL_FIRE_RL_m_rl_rd_resp_slave_to_master &&
!m_rg_r_beat_count_19_ULT_m_f_r_arlen_first__20___d121 ;
assign m_f_r_arlen$CLR = m_rg_reset ;
// submodule m_f_w_awlen
assign m_f_w_awlen$D_IN = m_xactor_from_master_f_wr_addr$D_OUT[28:21] ;
assign m_f_w_awlen$ENQ =
WILL_FIRE_RL_m_rl_wr_xaction_master_to_slave &&
m_rg_w_beat_count == 8'd0 ;
assign m_f_w_awlen$DEQ =
WILL_FIRE_RL_m_rl_wr_resp_slave_to_master &&
!m_rg_b_beat_count_5_ULT_m_f_w_awlen_first__6___d57 ;
assign m_f_w_awlen$CLR = m_rg_reset ;
// submodule m_xactor_from_master_f_rd_addr
assign m_xactor_from_master_f_rd_addr$D_IN =
{ from_master_arid,
from_master_araddr,
from_master_arlen,
from_master_arsize,
from_master_arburst,
from_master_arlock,
from_master_arcache,
from_master_arprot,
from_master_arqos,
from_master_arregion } ;
assign m_xactor_from_master_f_rd_addr$ENQ =
from_master_arvalid && m_xactor_from_master_f_rd_addr$FULL_N ;
assign m_xactor_from_master_f_rd_addr$DEQ =
WILL_FIRE_RL_m_rl_rd_xaction_master_to_slave &&
!m_rg_ar_beat_count_9_ULT_m_xactor_from_master__ETC___d110 ;
assign m_xactor_from_master_f_rd_addr$CLR = m_rg_reset ;
// submodule m_xactor_from_master_f_rd_data
assign m_xactor_from_master_f_rd_data$D_IN =
{ m_xactor_to_slave_f_rd_data$D_OUT[70:1],
!m_rg_r_beat_count_19_ULT_m_f_r_arlen_first__20___d121 } ;
assign m_xactor_from_master_f_rd_data$ENQ =
CAN_FIRE_RL_m_rl_rd_resp_slave_to_master ;
assign m_xactor_from_master_f_rd_data$DEQ =
from_master_rready && m_xactor_from_master_f_rd_data$EMPTY_N ;
assign m_xactor_from_master_f_rd_data$CLR = m_rg_reset ;
// submodule m_xactor_from_master_f_wr_addr
assign m_xactor_from_master_f_wr_addr$D_IN =
{ from_master_awid,
from_master_awaddr,
from_master_awlen,
from_master_awsize,
from_master_awburst,
from_master_awlock,
from_master_awcache,
from_master_awprot,
from_master_awqos,
from_master_awregion } ;
assign m_xactor_from_master_f_wr_addr$ENQ =
from_master_awvalid && m_xactor_from_master_f_wr_addr$FULL_N ;
assign m_xactor_from_master_f_wr_addr$DEQ =
WILL_FIRE_RL_m_rl_wr_xaction_master_to_slave &&
!m_rg_w_beat_count_ULT_m_xactor_from_master_f_w_ETC___d42 ;
assign m_xactor_from_master_f_wr_addr$CLR = m_rg_reset ;
// submodule m_xactor_from_master_f_wr_data
assign m_xactor_from_master_f_wr_data$D_IN =
{ from_master_wdata, from_master_wstrb, from_master_wlast } ;
assign m_xactor_from_master_f_wr_data$ENQ =
from_master_wvalid && m_xactor_from_master_f_wr_data$FULL_N ;
assign m_xactor_from_master_f_wr_data$DEQ =
CAN_FIRE_RL_m_rl_wr_xaction_master_to_slave ;
assign m_xactor_from_master_f_wr_data$CLR = m_rg_reset ;
// submodule m_xactor_from_master_f_wr_resp
assign m_xactor_from_master_f_wr_resp$D_IN =
{ m_xactor_to_slave_f_wr_resp$D_OUT[5:2],
(m_rg_b_resp == 2'b0) ?
m_xactor_to_slave_f_wr_resp$D_OUT[1:0] :
m_rg_b_resp } ;
assign m_xactor_from_master_f_wr_resp$ENQ =
WILL_FIRE_RL_m_rl_wr_resp_slave_to_master &&
!m_rg_b_beat_count_5_ULT_m_f_w_awlen_first__6___d57 ;
assign m_xactor_from_master_f_wr_resp$DEQ =
from_master_bready && m_xactor_from_master_f_wr_resp$EMPTY_N ;
assign m_xactor_from_master_f_wr_resp$CLR = m_rg_reset ;
// submodule m_xactor_to_slave_f_rd_addr
assign m_xactor_to_slave_f_rd_addr$D_IN =
{ m_xactor_from_master_f_rd_addr$D_OUT[96:93],
a_out_araddr__h3025,
8'd0,
m_xactor_from_master_f_rd_addr$D_OUT[20:18],
2'b0,
m_xactor_from_master_f_rd_addr$D_OUT[15:0] } ;
assign m_xactor_to_slave_f_rd_addr$ENQ =
CAN_FIRE_RL_m_rl_rd_xaction_master_to_slave ;
assign m_xactor_to_slave_f_rd_addr$DEQ =
m_xactor_to_slave_f_rd_addr$EMPTY_N && to_slave_arready ;
assign m_xactor_to_slave_f_rd_addr$CLR = m_rg_reset ;
// submodule m_xactor_to_slave_f_rd_data
assign m_xactor_to_slave_f_rd_data$D_IN =
{ to_slave_rid,
to_slave_rdata,
to_slave_rresp,
to_slave_rlast } ;
assign m_xactor_to_slave_f_rd_data$ENQ =
to_slave_rvalid && m_xactor_to_slave_f_rd_data$FULL_N ;
assign m_xactor_to_slave_f_rd_data$DEQ =
CAN_FIRE_RL_m_rl_rd_resp_slave_to_master ;
assign m_xactor_to_slave_f_rd_data$CLR = m_rg_reset ;
// submodule m_xactor_to_slave_f_wr_addr
assign m_xactor_to_slave_f_wr_addr$D_IN =
{ m_xactor_from_master_f_wr_addr$D_OUT[96:93],
a_out_awaddr__h1941,
8'd0,
m_xactor_from_master_f_wr_addr$D_OUT[20:18],
2'b0,
m_xactor_from_master_f_wr_addr$D_OUT[15:0] } ;
assign m_xactor_to_slave_f_wr_addr$ENQ =
CAN_FIRE_RL_m_rl_wr_xaction_master_to_slave ;
assign m_xactor_to_slave_f_wr_addr$DEQ =
m_xactor_to_slave_f_wr_addr$EMPTY_N && to_slave_awready ;
assign m_xactor_to_slave_f_wr_addr$CLR = m_rg_reset ;
// submodule m_xactor_to_slave_f_wr_data
assign m_xactor_to_slave_f_wr_data$D_IN =
{ m_xactor_from_master_f_wr_data$D_OUT[72:1], 1'd1 } ;
assign m_xactor_to_slave_f_wr_data$ENQ =
CAN_FIRE_RL_m_rl_wr_xaction_master_to_slave ;
assign m_xactor_to_slave_f_wr_data$DEQ =
m_xactor_to_slave_f_wr_data$EMPTY_N && to_slave_wready ;
assign m_xactor_to_slave_f_wr_data$CLR = m_rg_reset ;
// submodule m_xactor_to_slave_f_wr_resp
assign m_xactor_to_slave_f_wr_resp$D_IN = { to_slave_bid, to_slave_bresp } ;
assign m_xactor_to_slave_f_wr_resp$ENQ =
to_slave_bvalid && m_xactor_to_slave_f_wr_resp$FULL_N ;
assign m_xactor_to_slave_f_wr_resp$DEQ =
CAN_FIRE_RL_m_rl_wr_resp_slave_to_master ;
assign m_xactor_to_slave_f_wr_resp$CLR = m_rg_reset ;
// remaining internal signals
assign a_out_araddr__h3025 =
(m_rg_ar_beat_count == 8'd0) ?
m_xactor_from_master_f_rd_addr$D_OUT[92:29] :
((m_xactor_from_master_f_rd_addr$D_OUT[17:16] == 2'b10) ?
addr___1__h3119 :
addr__h3107) ;
assign a_out_awaddr__h1941 =
(m_rg_w_beat_count == 8'd0) ?
m_xactor_from_master_f_wr_addr$D_OUT[92:29] :
((m_xactor_from_master_f_wr_addr$D_OUT[17:16] == 2'b10) ?
addr___1__h2035 :
addr__h2023) ;
assign addr___1__h2035 = x__h2047 | y__h2048 ;
assign addr___1__h3119 = x__h3131 | y__h3132 ;
assign addr__h2023 =
m_rg_last_beat_waddr +
(64'd1 << m_xactor_from_master_f_wr_addr$D_OUT[20:18]) ;
assign addr__h3107 =
m_rg_last_beat_raddr +
(64'd1 << m_xactor_from_master_f_rd_addr$D_OUT[20:18]) ;
assign burst_len__h2024 =
{ 56'd0, m_xactor_from_master_f_wr_addr$D_OUT[28:21] } + 64'd1 ;
assign burst_len__h3108 =
{ 56'd0, m_xactor_from_master_f_rd_addr$D_OUT[28:21] } + 64'd1 ;
assign m_rg_ar_beat_count_9_ULT_m_xactor_from_master__ETC___d110 =
m_rg_ar_beat_count <
m_xactor_from_master_f_rd_addr$D_OUT[28:21] ;
assign m_rg_b_beat_count_5_ULT_m_f_w_awlen_first__6___d57 =
m_rg_b_beat_count < m_f_w_awlen$D_OUT ;
assign m_rg_r_beat_count_19_ULT_m_f_r_arlen_first__20___d121 =
m_rg_r_beat_count < m_f_r_arlen$D_OUT ;
assign m_rg_w_beat_count_ULT_m_xactor_from_master_f_w_ETC___d42 =
m_rg_w_beat_count < m_xactor_from_master_f_wr_addr$D_OUT[28:21] ;
assign wrap_mask__h2025 =
(burst_len__h2024 <<
m_xactor_from_master_f_wr_addr$D_OUT[20:18]) -
64'd1 ;
assign wrap_mask__h3109 =
(burst_len__h3108 <<
m_xactor_from_master_f_rd_addr$D_OUT[20:18]) -
64'd1 ;
assign x__h2047 = m_rg_last_beat_waddr & y__h2049 ;
assign x__h2322 = m_rg_w_beat_count + 8'd1 ;
assign x__h2829 = m_rg_b_beat_count + 8'd1 ;
assign x__h3131 = m_rg_last_beat_raddr & y__h3133 ;
assign x__h3316 = m_rg_ar_beat_count + 8'd1 ;
assign x__h3535 = m_rg_r_beat_count + 8'd1 ;
assign y__h2048 = addr__h2023 & wrap_mask__h2025 ;
assign y__h2049 = ~wrap_mask__h2025 ;
assign y__h3132 = addr__h3107 & wrap_mask__h3109 ;
assign y__h3133 = ~wrap_mask__h3109 ;
// handling of inlined registers
always@(posedge CLK)
begin
if (RST_N == `BSV_RESET_VALUE)
begin
m_rg_ar_beat_count <= `BSV_ASSIGNMENT_DELAY 8'd0;
m_rg_b_beat_count <= `BSV_ASSIGNMENT_DELAY 8'd0;
m_rg_b_resp <= `BSV_ASSIGNMENT_DELAY 2'b0;
m_rg_r_beat_count <= `BSV_ASSIGNMENT_DELAY 8'd0;
m_rg_reset <= `BSV_ASSIGNMENT_DELAY 1'd1;
m_rg_w_beat_count <= `BSV_ASSIGNMENT_DELAY 8'd0;
end
else
begin
if (m_rg_ar_beat_count$EN)
m_rg_ar_beat_count <= `BSV_ASSIGNMENT_DELAY m_rg_ar_beat_count$D_IN;
if (m_rg_b_beat_count$EN)
m_rg_b_beat_count <= `BSV_ASSIGNMENT_DELAY m_rg_b_beat_count$D_IN;
if (m_rg_b_resp$EN)
m_rg_b_resp <= `BSV_ASSIGNMENT_DELAY m_rg_b_resp$D_IN;
if (m_rg_r_beat_count$EN)
m_rg_r_beat_count <= `BSV_ASSIGNMENT_DELAY m_rg_r_beat_count$D_IN;
if (m_rg_reset$EN)
m_rg_reset <= `BSV_ASSIGNMENT_DELAY m_rg_reset$D_IN;
if (m_rg_w_beat_count$EN)
m_rg_w_beat_count <= `BSV_ASSIGNMENT_DELAY m_rg_w_beat_count$D_IN;
end
if (m_rg_last_beat_raddr$EN)
m_rg_last_beat_raddr <= `BSV_ASSIGNMENT_DELAY m_rg_last_beat_raddr$D_IN;
if (m_rg_last_beat_waddr$EN)
m_rg_last_beat_waddr <= `BSV_ASSIGNMENT_DELAY m_rg_last_beat_waddr$D_IN;
end
// synopsys translate_off
`ifdef BSV_NO_INITIAL_BLOCKS
`else // not BSV_NO_INITIAL_BLOCKS
initial
begin
m_rg_ar_beat_count = 8'hAA;
m_rg_b_beat_count = 8'hAA;
m_rg_b_resp = 2'h2;
m_rg_last_beat_raddr = 64'hAAAAAAAAAAAAAAAA;
m_rg_last_beat_waddr = 64'hAAAAAAAAAAAAAAAA;
m_rg_r_beat_count = 8'hAA;
m_rg_reset = 1'h0;
m_rg_w_beat_count = 8'hAA;
end
`endif // BSV_NO_INITIAL_BLOCKS
// synopsys translate_on
// handling of system tasks
// synopsys translate_off
always@(negedge CLK)
begin
#0;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_wr_xaction_master_to_slave &&
!m_rg_w_beat_count_ULT_m_xactor_from_master_f_w_ETC___d42 &&
!m_xactor_from_master_f_wr_data$D_OUT[0])
begin
v__h2464 = $stime;
#0;
end
v__h2458 = v__h2464 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_wr_xaction_master_to_slave &&
!m_rg_w_beat_count_ULT_m_xactor_from_master_f_w_ETC___d42 &&
!m_xactor_from_master_f_wr_data$D_OUT[0])
$display("%0d: ERROR: %m::AXI4_Deburster.rl_wr_xaction_master_to_slave: m -> s",
v__h2458);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_wr_xaction_master_to_slave &&
!m_rg_w_beat_count_ULT_m_xactor_from_master_f_w_ETC___d42 &&
!m_xactor_from_master_f_wr_data$D_OUT[0])
$display(" WLAST not set on last data beat (awlen = %0d)",
m_xactor_from_master_f_wr_addr$D_OUT[28:21]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_wr_xaction_master_to_slave &&
!m_rg_w_beat_count_ULT_m_xactor_from_master_f_w_ETC___d42 &&
!m_xactor_from_master_f_wr_data$D_OUT[0])
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_wr_xaction_master_to_slave &&
!m_rg_w_beat_count_ULT_m_xactor_from_master_f_w_ETC___d42 &&
!m_xactor_from_master_f_wr_data$D_OUT[0])
$write("AXI4_Wr_Data { ", "wdata: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_wr_xaction_master_to_slave &&
!m_rg_w_beat_count_ULT_m_xactor_from_master_f_w_ETC___d42 &&
!m_xactor_from_master_f_wr_data$D_OUT[0])
$write("'h%h", m_xactor_from_master_f_wr_data$D_OUT[72:9]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_wr_xaction_master_to_slave &&
!m_rg_w_beat_count_ULT_m_xactor_from_master_f_w_ETC___d42 &&
!m_xactor_from_master_f_wr_data$D_OUT[0])
$write(", ", "wstrb: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_wr_xaction_master_to_slave &&
!m_rg_w_beat_count_ULT_m_xactor_from_master_f_w_ETC___d42 &&
!m_xactor_from_master_f_wr_data$D_OUT[0])
$write("'h%h", m_xactor_from_master_f_wr_data$D_OUT[8:1]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_wr_xaction_master_to_slave &&
!m_rg_w_beat_count_ULT_m_xactor_from_master_f_w_ETC___d42 &&
!m_xactor_from_master_f_wr_data$D_OUT[0])
$write(", ", "wlast: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_wr_xaction_master_to_slave &&
!m_rg_w_beat_count_ULT_m_xactor_from_master_f_w_ETC___d42 &&
!m_xactor_from_master_f_wr_data$D_OUT[0])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_wr_xaction_master_to_slave &&
!m_rg_w_beat_count_ULT_m_xactor_from_master_f_w_ETC___d42 &&
!m_xactor_from_master_f_wr_data$D_OUT[0])
$write(", ", "wuser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_wr_xaction_master_to_slave &&
!m_rg_w_beat_count_ULT_m_xactor_from_master_f_w_ETC___d42 &&
!m_xactor_from_master_f_wr_data$D_OUT[0])
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_m_rl_wr_xaction_master_to_slave &&
!m_rg_w_beat_count_ULT_m_xactor_from_master_f_w_ETC___d42 &&
!m_xactor_from_master_f_wr_data$D_OUT[0])
$write("\n");
end
// synopsys translate_on
endmodule
|
module apu_envelope_generator
(
input clk_in, // system clock signal
input rst_in, // reset signal
input eg_pulse_in, // 1 clk pulse for every env gen update
input [5:0] env_in, // envelope value (e.g., via $4000)
input env_wr_in, // envelope value write
input env_restart, // envelope restart
output [3:0] env_out // output volume
);
reg [5:0] q_reg;
wire [5:0] d_reg;
reg [3:0] q_cnt, d_cnt;
reg q_start_flag, d_start_flag;
always @(posedge clk_in)
begin
if (rst_in)
begin
q_reg <= 6'h00;
q_cnt <= 4'h0;
q_start_flag <= 1'b0;
end
else
begin
q_reg <= d_reg;
q_cnt <= d_cnt;
q_start_flag <= d_start_flag;
end
end
reg divider_pulse_in;
reg divider_reload;
wire divider_pulse_out;
apu_div #(.PERIOD_BITS(4)) divider(
.clk_in(clk_in),
.rst_in(rst_in),
.pulse_in(divider_pulse_in),
.reload_in(divider_reload),
.period_in(q_reg[3:0]),
.pulse_out(divider_pulse_out)
);
always @*
begin
d_cnt = q_cnt;
d_start_flag = q_start_flag;
divider_pulse_in = 1'b0;
divider_reload = 1'b0;
// When the divider outputs a clock, one of two actions occurs: If the counter is non-zero, it
// is decremented, otherwise if the loop flag is set, the counter is loaded with 15.
if (divider_pulse_out)
begin
divider_reload = 1'b1;
if (q_cnt != 4'h0)
d_cnt = q_cnt - 4'h1;
else if (q_reg[5])
d_cnt = 4'hF;
end
// When clocked by the frame counter, one of two actions occurs: if the start flag is clear,
// the divider is clocked, otherwise the start flag is cleared, the counter is loaded with 15,
// and the divider's period is immediately reloaded.
if (eg_pulse_in)
begin
if (q_start_flag == 1'b0)
begin
divider_pulse_in = 1'b1;
end
else
begin
d_start_flag = 1'b0;
d_cnt = 4'hF;
end
end
if (env_restart)
d_start_flag = 1'b1;
end
assign d_reg = (env_wr_in) ? env_in : q_reg;
// The envelope unit's volume output depends on the constant volume flag: if set, the envelope
// parameter directly sets the volume, otherwise the counter's value is the current volume.
assign env_out = (q_reg[4]) ? q_reg[3:0] : q_cnt;
endmodule
|
module csubRecursiveKOA
//#(parameter SW = 24, parameter precision = 0)
#(parameter SW = 8)
(
// input wire clk,
input wire [SW-1:0] Data_A_i,
input wire [SW-1:0] Data_B_i,
output wire [2*SW-1:0] Data_S_o
);
localparam integer STOP_CONT = `STOP_CONT;
generate
//assign i = Stop_I;
if (SW <= STOP_CONT) begin : GENSTOP
cmult #(.SW(SW))
inst_cmult (
// .clk(clk),
.Data_A_i(Data_A_i),
.Data_B_i(Data_B_i),
.Data_S_o(Data_S_o)
);
end else begin : RECURSIVE
reg [2*SW-1:0] sgf_result_o;
///////////////////////////////////////////////////////////
wire [1:0] zero1;
wire [3:0] zero2;
assign zero1 = 2'b00;
assign zero2 = 4'b0000;
///////////////////////////////////////////////////////////
wire [SW/2-1:0] rightside1;
wire [SW/2:0] rightside2;
//Modificacion: Leftside signals are added. They are created as zero fillings as preparation for the final adder.
wire [SW/2-3:0] leftside1;
wire [SW/2-4:0] leftside2;
reg [4*(SW/2)+2:0] Result;
reg [4*(SW/2)-1:0] sgf_r;
localparam half = SW/2;
assign rightside1 = {(SW/2){1'b0}};
assign rightside2 = {(SW/2+1){1'b0}};
assign leftside1 = {(SW/2-4){1'b0}}; //Se le quitan dos bits con respecto al right side, esto porque al sumar, se agregan bits, esos hacen que sea diferente
assign leftside2 = {(SW/2-5){1'b0}};
case (SW%2)
0:begin : EVEN1
reg [SW/2:0] result_A_adder;
reg [SW/2:0] result_B_adder;
reg [SW-1:0] Q_left;
reg [SW-1:0] Q_right;
reg [SW+1:0] Q_middle;
reg [2*(SW/2+2)-1:0] S_A;
reg [SW+1:0] S_B; //SW+2
always @* begin : EVEN11
result_A_adder <= (Data_A_i[((SW/2)-1):0] + Data_A_i[(SW-1) -: SW/2]);
result_B_adder <= (Data_B_i[((SW/2)-1):0] + Data_B_i[(SW-1) -: SW/2]);
S_B <= (Q_middle - Q_left - Q_right);
sgf_result_o <= {leftside1,S_B,rightside1} + {Q_left,Q_right};
end
csubRecursiveKOA #(.SW(SW/2)) left(
// .clk(clk),
.Data_A_i(Data_A_i[SW-1:SW-SW/2]),
.Data_B_i(Data_B_i[SW-1:SW-SW/2]),
.Data_S_o(Q_left)
);
csubRecursiveKOA #(.SW(SW/2)) right(
// .clk(clk),
.Data_A_i(Data_A_i[SW-SW/2-1:0]),
.Data_B_i(Data_B_i[SW-SW/2-1:0]),
.Data_S_o(Q_right)
);
csubRecursiveKOA #(.SW((SW/2)+1)) middle (
// .clk(clk),
.Data_A_i(result_A_adder),
.Data_B_i(result_B_adder),
.Data_S_o(Q_middle)
);
assign Data_S_o = sgf_result_o;
end
1:begin : ODD1
reg [SW/2+1:0] result_A_adder;
reg [SW/2+1:0] result_B_adder;
reg [2*(SW/2)-1:0] Q_left;
reg [2*(SW/2+1)-1:0] Q_right;
reg [2*(SW/2+2)-1:0] Q_middle;
reg [2*(SW/2+2)-1:0] S_A;
reg [SW+4-1:0] S_B;
always @* begin : ODD11
result_A_adder <= (Data_A_i[SW-SW/2-1:0] + Data_A_i[SW-1:SW-SW/2]);
result_B_adder <= Data_B_i[SW-SW/2-1:0] + Data_B_i[SW-1:SW-SW/2];
S_B <= (Q_middle - Q_left - Q_right);
sgf_result_o<= {leftside2,S_B,rightside2} + {Q_left,Q_right};
//sgf_result_o <= Result[2*SW-1:0];
end
assign Data_S_o = sgf_result_o;
csubRecursiveKOA #(.SW(SW/2)) left(
// .clk(clk),
.Data_A_i(Data_A_i[SW-1:SW-SW/2]),
.Data_B_i(Data_B_i[SW-1:SW-SW/2]),
.Data_S_o(Q_left)
);
csubRecursiveKOA #(.SW((SW/2)+1)) right(
// .clk(clk),
.Data_A_i(Data_A_i[SW-SW/2-1:0]),
.Data_B_i(Data_B_i[SW-SW/2-1:0]),
.Data_S_o(Q_right)
);
csubRecursiveKOA #(.SW((SW/2)+2)) middle (
// .clk(clk),
.Data_A_i(result_A_adder),
.Data_B_i(result_B_adder),
.Data_S_o(Q_middle)
);
end
endcase
end
endgenerate
endmodule
|
module top();
// Inputs are registered
reg A;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 VGND = 1'b0;
#60 VNB = 1'b0;
#80 VPB = 1'b0;
#100 VPWR = 1'b0;
#120 A = 1'b1;
#140 VGND = 1'b1;
#160 VNB = 1'b1;
#180 VPB = 1'b1;
#200 VPWR = 1'b1;
#220 A = 1'b0;
#240 VGND = 1'b0;
#260 VNB = 1'b0;
#280 VPB = 1'b0;
#300 VPWR = 1'b0;
#320 VPWR = 1'b1;
#340 VPB = 1'b1;
#360 VNB = 1'b1;
#380 VGND = 1'b1;
#400 A = 1'b1;
#420 VPWR = 1'bx;
#440 VPB = 1'bx;
#460 VNB = 1'bx;
#480 VGND = 1'bx;
#500 A = 1'bx;
end
sky130_fd_sc_hd__clkdlybuf4s18 dut (.A(A), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .X(X));
endmodule
|
module sky130_fd_sc_ls__tapvgnd2 ();
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
|
module system_vga_hessian_0_0
(clk_x16,
active,
rst,
x_addr,
y_addr,
g_in,
hessian_out);
input clk_x16;
input active;
(* x_interface_info = "xilinx.com:signal:reset:1.0 rst RST" *) input rst;
input [9:0]x_addr;
input [9:0]y_addr;
input [7:0]g_in;
output [31:0]hessian_out;
wire active;
wire clk_x16;
wire [7:0]g_in;
wire [31:0]hessian_out;
wire rst;
wire [9:0]x_addr;
wire [9:0]y_addr;
system_vga_hessian_0_0_vga_hessian U0
(.active(active),
.clk_x16(clk_x16),
.g_in(g_in),
.hessian_out(hessian_out),
.rst(rst),
.x_addr(x_addr),
.y_addr(y_addr));
endmodule
|
module system_vga_hessian_0_0_blk_mem_gen_0
(clka,
ena,
wea,
addra,
dina,
douta,
clkb,
enb,
web,
addrb,
dinb,
doutb);
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK" *) input clka;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA EN" *) input ena;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA WE" *) input [0:0]wea;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR" *) input [13:0]addra;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN" *) input [15:0]dina;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT" *) output [15:0]douta;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTB CLK" *) input clkb;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTB EN" *) input enb;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTB WE" *) input [0:0]web;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTB ADDR" *) input [13:0]addrb;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTB DIN" *) input [15:0]dinb;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTB DOUT" *) output [15:0]doutb;
wire [13:0]addra;
wire [13:0]addrb;
wire clka;
wire clkb;
wire [15:0]dina;
wire [15:0]dinb;
wire [15:0]douta;
wire [15:0]doutb;
wire ena;
wire enb;
wire [0:0]wea;
wire [0:0]web;
wire NLW_U0_dbiterr_UNCONNECTED;
wire NLW_U0_rsta_busy_UNCONNECTED;
wire NLW_U0_rstb_busy_UNCONNECTED;
wire NLW_U0_s_axi_arready_UNCONNECTED;
wire NLW_U0_s_axi_awready_UNCONNECTED;
wire NLW_U0_s_axi_bvalid_UNCONNECTED;
wire NLW_U0_s_axi_dbiterr_UNCONNECTED;
wire NLW_U0_s_axi_rlast_UNCONNECTED;
wire NLW_U0_s_axi_rvalid_UNCONNECTED;
wire NLW_U0_s_axi_sbiterr_UNCONNECTED;
wire NLW_U0_s_axi_wready_UNCONNECTED;
wire NLW_U0_sbiterr_UNCONNECTED;
wire [13:0]NLW_U0_rdaddrecc_UNCONNECTED;
wire [3:0]NLW_U0_s_axi_bid_UNCONNECTED;
wire [1:0]NLW_U0_s_axi_bresp_UNCONNECTED;
wire [13:0]NLW_U0_s_axi_rdaddrecc_UNCONNECTED;
wire [15:0]NLW_U0_s_axi_rdata_UNCONNECTED;
wire [3:0]NLW_U0_s_axi_rid_UNCONNECTED;
wire [1:0]NLW_U0_s_axi_rresp_UNCONNECTED;
(* C_ADDRA_WIDTH = "14" *)
(* C_ADDRB_WIDTH = "14" *)
(* C_ALGORITHM = "1" *)
(* C_AXI_ID_WIDTH = "4" *)
(* C_AXI_SLAVE_TYPE = "0" *)
(* C_AXI_TYPE = "1" *)
(* C_BYTE_SIZE = "9" *)
(* C_COMMON_CLK = "0" *)
(* C_COUNT_18K_BRAM = "1" *)
(* C_COUNT_36K_BRAM = "7" *)
(* C_CTRL_ECC_ALGO = "NONE" *)
(* C_DEFAULT_DATA = "0" *)
(* C_DISABLE_WARN_BHV_COLL = "0" *)
(* C_DISABLE_WARN_BHV_RANGE = "0" *)
(* C_ELABORATION_DIR = "./" *)
(* C_ENABLE_32BIT_ADDRESS = "0" *)
(* C_EN_DEEPSLEEP_PIN = "0" *)
(* C_EN_ECC_PIPE = "0" *)
(* C_EN_RDADDRA_CHG = "0" *)
(* C_EN_RDADDRB_CHG = "0" *)
(* C_EN_SAFETY_CKT = "0" *)
(* C_EN_SHUTDOWN_PIN = "0" *)
(* C_EN_SLEEP_PIN = "0" *)
(* C_EST_POWER_SUMMARY = "Estimated Power for IP : 22.1485 mW" *)
(* C_FAMILY = "zynq" *)
(* C_HAS_AXI_ID = "0" *)
(* C_HAS_ENA = "1" *)
(* C_HAS_ENB = "1" *)
(* C_HAS_INJECTERR = "0" *)
(* C_HAS_MEM_OUTPUT_REGS_A = "1" *)
(* C_HAS_MEM_OUTPUT_REGS_B = "1" *)
(* C_HAS_MUX_OUTPUT_REGS_A = "0" *)
(* C_HAS_MUX_OUTPUT_REGS_B = "0" *)
(* C_HAS_REGCEA = "0" *)
(* C_HAS_REGCEB = "0" *)
(* C_HAS_RSTA = "0" *)
(* C_HAS_RSTB = "0" *)
(* C_HAS_SOFTECC_INPUT_REGS_A = "0" *)
(* C_HAS_SOFTECC_OUTPUT_REGS_B = "0" *)
(* C_INITA_VAL = "0" *)
(* C_INITB_VAL = "0" *)
(* C_INIT_FILE = "blk_mem_gen_0.mem" *)
(* C_INIT_FILE_NAME = "no_coe_file_loaded" *)
(* C_INTERFACE_TYPE = "0" *)
(* C_LOAD_INIT_FILE = "0" *)
(* C_MEM_TYPE = "2" *)
(* C_MUX_PIPELINE_STAGES = "0" *)
(* C_PRIM_TYPE = "1" *)
(* C_READ_DEPTH_A = "16384" *)
(* C_READ_DEPTH_B = "16384" *)
(* C_READ_WIDTH_A = "16" *)
(* C_READ_WIDTH_B = "16" *)
(* C_RSTRAM_A = "0" *)
(* C_RSTRAM_B = "0" *)
(* C_RST_PRIORITY_A = "CE" *)
(* C_RST_PRIORITY_B = "CE" *)
(* C_SIM_COLLISION_CHECK = "ALL" *)
(* C_USE_BRAM_BLOCK = "0" *)
(* C_USE_BYTE_WEA = "0" *)
(* C_USE_BYTE_WEB = "0" *)
(* C_USE_DEFAULT_DATA = "0" *)
(* C_USE_ECC = "0" *)
(* C_USE_SOFTECC = "0" *)
(* C_USE_URAM = "0" *)
(* C_WEA_WIDTH = "1" *)
(* C_WEB_WIDTH = "1" *)
(* C_WRITE_DEPTH_A = "16384" *)
(* C_WRITE_DEPTH_B = "16384" *)
(* C_WRITE_MODE_A = "WRITE_FIRST" *)
(* C_WRITE_MODE_B = "WRITE_FIRST" *)
(* C_WRITE_WIDTH_A = "16" *)
(* C_WRITE_WIDTH_B = "16" *)
(* C_XDEVICEFAMILY = "zynq" *)
(* downgradeipidentifiedwarnings = "yes" *)
system_vga_hessian_0_0_blk_mem_gen_v8_3_5 U0
(.addra(addra),
.addrb(addrb),
.clka(clka),
.clkb(clkb),
.dbiterr(NLW_U0_dbiterr_UNCONNECTED),
.deepsleep(1'b0),
.dina(dina),
.dinb(dinb),
.douta(douta),
.doutb(doutb),
.eccpipece(1'b0),
.ena(ena),
.enb(enb),
.injectdbiterr(1'b0),
.injectsbiterr(1'b0),
.rdaddrecc(NLW_U0_rdaddrecc_UNCONNECTED[13:0]),
.regcea(1'b0),
.regceb(1'b0),
.rsta(1'b0),
.rsta_busy(NLW_U0_rsta_busy_UNCONNECTED),
.rstb(1'b0),
.rstb_busy(NLW_U0_rstb_busy_UNCONNECTED),
.s_aclk(1'b0),
.s_aresetn(1'b0),
.s_axi_araddr({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_arburst({1'b0,1'b0}),
.s_axi_arid({1'b0,1'b0,1'b0,1'b0}),
.s_axi_arlen({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_arready(NLW_U0_s_axi_arready_UNCONNECTED),
.s_axi_arsize({1'b0,1'b0,1'b0}),
.s_axi_arvalid(1'b0),
.s_axi_awaddr({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_awburst({1'b0,1'b0}),
.s_axi_awid({1'b0,1'b0,1'b0,1'b0}),
.s_axi_awlen({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_awready(NLW_U0_s_axi_awready_UNCONNECTED),
.s_axi_awsize({1'b0,1'b0,1'b0}),
.s_axi_awvalid(1'b0),
.s_axi_bid(NLW_U0_s_axi_bid_UNCONNECTED[3:0]),
.s_axi_bready(1'b0),
.s_axi_bresp(NLW_U0_s_axi_bresp_UNCONNECTED[1:0]),
.s_axi_bvalid(NLW_U0_s_axi_bvalid_UNCONNECTED),
.s_axi_dbiterr(NLW_U0_s_axi_dbiterr_UNCONNECTED),
.s_axi_injectdbiterr(1'b0),
.s_axi_injectsbiterr(1'b0),
.s_axi_rdaddrecc(NLW_U0_s_axi_rdaddrecc_UNCONNECTED[13:0]),
.s_axi_rdata(NLW_U0_s_axi_rdata_UNCONNECTED[15:0]),
.s_axi_rid(NLW_U0_s_axi_rid_UNCONNECTED[3:0]),
.s_axi_rlast(NLW_U0_s_axi_rlast_UNCONNECTED),
.s_axi_rready(1'b0),
.s_axi_rresp(NLW_U0_s_axi_rresp_UNCONNECTED[1:0]),
.s_axi_rvalid(NLW_U0_s_axi_rvalid_UNCONNECTED),
.s_axi_sbiterr(NLW_U0_s_axi_sbiterr_UNCONNECTED),
.s_axi_wdata({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_wlast(1'b0),
.s_axi_wready(NLW_U0_s_axi_wready_UNCONNECTED),
.s_axi_wstrb(1'b0),
.s_axi_wvalid(1'b0),
.sbiterr(NLW_U0_sbiterr_UNCONNECTED),
.shutdown(1'b0),
.sleep(1'b0),
.wea(wea),
.web(web));
endmodule
|
module system_vga_hessian_0_0_vga_hessian
(hessian_out,
clk_x16,
rst,
active,
x_addr,
y_addr,
g_in);
output [31:0]hessian_out;
input clk_x16;
input rst;
input active;
input [9:0]x_addr;
input [9:0]y_addr;
input [7:0]g_in;
wire [15:0]A;
wire [15:0]B;
wire Lxx;
wire Lxx0_carry__0_i_1_n_0;
wire Lxx0_carry__0_i_2_n_0;
wire Lxx0_carry__0_i_3_n_0;
wire Lxx0_carry__0_i_4_n_0;
wire Lxx0_carry__0_i_5_n_0;
wire Lxx0_carry__0_i_6_n_0;
wire Lxx0_carry__0_i_7_n_0;
wire Lxx0_carry__0_i_8_n_0;
wire Lxx0_carry__0_n_0;
wire Lxx0_carry__0_n_1;
wire Lxx0_carry__0_n_2;
wire Lxx0_carry__0_n_3;
wire Lxx0_carry__1_i_1_n_0;
wire Lxx0_carry__1_i_2_n_0;
wire Lxx0_carry__1_i_3_n_0;
wire Lxx0_carry__1_i_4_n_0;
wire Lxx0_carry__1_i_5_n_0;
wire Lxx0_carry__1_i_6_n_0;
wire Lxx0_carry__1_i_7_n_0;
wire Lxx0_carry__1_i_8_n_0;
wire Lxx0_carry__1_n_0;
wire Lxx0_carry__1_n_1;
wire Lxx0_carry__1_n_2;
wire Lxx0_carry__1_n_3;
wire Lxx0_carry__2_i_1_n_0;
wire Lxx0_carry__2_i_2_n_0;
wire Lxx0_carry__2_i_3_n_0;
wire Lxx0_carry__2_i_4_n_0;
wire Lxx0_carry__2_i_5_n_0;
wire Lxx0_carry__2_i_6_n_0;
wire Lxx0_carry__2_i_7_n_0;
wire Lxx0_carry__2_n_1;
wire Lxx0_carry__2_n_2;
wire Lxx0_carry__2_n_3;
wire Lxx0_carry_i_1_n_0;
wire Lxx0_carry_i_2_n_0;
wire Lxx0_carry_i_3_n_0;
wire Lxx0_carry_i_4_n_0;
wire Lxx0_carry_i_5_n_0;
wire Lxx0_carry_i_6_n_0;
wire Lxx0_carry_n_0;
wire Lxx0_carry_n_1;
wire Lxx0_carry_n_2;
wire Lxx0_carry_n_3;
wire [15:0]Lxx_0;
wire [15:0]Lxx_00;
wire Lxx_00__1_carry__0_i_10_n_0;
wire Lxx_00__1_carry__0_i_11_n_0;
wire Lxx_00__1_carry__0_i_12_n_0;
wire Lxx_00__1_carry__0_i_1_n_0;
wire Lxx_00__1_carry__0_i_2_n_0;
wire Lxx_00__1_carry__0_i_3_n_0;
wire Lxx_00__1_carry__0_i_4_n_0;
wire Lxx_00__1_carry__0_i_5_n_0;
wire Lxx_00__1_carry__0_i_6_n_0;
wire Lxx_00__1_carry__0_i_7_n_0;
wire Lxx_00__1_carry__0_i_8_n_0;
wire Lxx_00__1_carry__0_i_9_n_0;
wire Lxx_00__1_carry__0_n_0;
wire Lxx_00__1_carry__0_n_1;
wire Lxx_00__1_carry__0_n_2;
wire Lxx_00__1_carry__0_n_3;
wire Lxx_00__1_carry__1_i_10_n_0;
wire Lxx_00__1_carry__1_i_11_n_0;
wire Lxx_00__1_carry__1_i_12_n_0;
wire Lxx_00__1_carry__1_i_1_n_0;
wire Lxx_00__1_carry__1_i_2_n_0;
wire Lxx_00__1_carry__1_i_3_n_0;
wire Lxx_00__1_carry__1_i_4_n_0;
wire Lxx_00__1_carry__1_i_5_n_0;
wire Lxx_00__1_carry__1_i_6_n_0;
wire Lxx_00__1_carry__1_i_7_n_0;
wire Lxx_00__1_carry__1_i_8_n_0;
wire Lxx_00__1_carry__1_i_9_n_0;
wire Lxx_00__1_carry__1_n_0;
wire Lxx_00__1_carry__1_n_1;
wire Lxx_00__1_carry__1_n_2;
wire Lxx_00__1_carry__1_n_3;
wire Lxx_00__1_carry__2_i_10_n_0;
wire Lxx_00__1_carry__2_i_11_n_0;
wire Lxx_00__1_carry__2_i_12_n_0;
wire Lxx_00__1_carry__2_i_1_n_0;
wire Lxx_00__1_carry__2_i_2_n_0;
wire Lxx_00__1_carry__2_i_3_n_0;
wire Lxx_00__1_carry__2_i_4_n_0;
wire Lxx_00__1_carry__2_i_5_n_0;
wire Lxx_00__1_carry__2_i_6_n_0;
wire Lxx_00__1_carry__2_i_7_n_0;
wire Lxx_00__1_carry__2_i_8_n_0;
wire Lxx_00__1_carry__2_i_9_n_0;
wire Lxx_00__1_carry__2_n_1;
wire Lxx_00__1_carry__2_n_2;
wire Lxx_00__1_carry__2_n_3;
wire Lxx_00__1_carry_i_1_n_0;
wire Lxx_00__1_carry_i_2_n_0;
wire Lxx_00__1_carry_i_3_n_0;
wire Lxx_00__1_carry_i_4_n_0;
wire Lxx_00__1_carry_i_5_n_0;
wire Lxx_00__1_carry_i_6_n_0;
wire Lxx_00__1_carry_i_7_n_0;
wire Lxx_00__1_carry_i_8_n_0;
wire Lxx_00__1_carry_i_9_n_0;
wire Lxx_00__1_carry_n_0;
wire Lxx_00__1_carry_n_1;
wire Lxx_00__1_carry_n_2;
wire Lxx_00__1_carry_n_3;
wire [15:1]Lxx_1;
wire [15:0]Lxx_11;
wire Lxx_11__1_carry__0_i_10_n_0;
wire Lxx_11__1_carry__0_i_11_n_0;
wire Lxx_11__1_carry__0_i_12_n_0;
wire Lxx_11__1_carry__0_i_1_n_0;
wire Lxx_11__1_carry__0_i_2_n_0;
wire Lxx_11__1_carry__0_i_3_n_0;
wire Lxx_11__1_carry__0_i_4_n_0;
wire Lxx_11__1_carry__0_i_5_n_0;
wire Lxx_11__1_carry__0_i_6_n_0;
wire Lxx_11__1_carry__0_i_7_n_0;
wire Lxx_11__1_carry__0_i_8_n_0;
wire Lxx_11__1_carry__0_i_9_n_0;
wire Lxx_11__1_carry__0_n_0;
wire Lxx_11__1_carry__0_n_1;
wire Lxx_11__1_carry__0_n_2;
wire Lxx_11__1_carry__0_n_3;
wire Lxx_11__1_carry__1_i_10_n_0;
wire Lxx_11__1_carry__1_i_11_n_0;
wire Lxx_11__1_carry__1_i_12_n_0;
wire Lxx_11__1_carry__1_i_1_n_0;
wire Lxx_11__1_carry__1_i_2_n_0;
wire Lxx_11__1_carry__1_i_3_n_0;
wire Lxx_11__1_carry__1_i_4_n_0;
wire Lxx_11__1_carry__1_i_5_n_0;
wire Lxx_11__1_carry__1_i_6_n_0;
wire Lxx_11__1_carry__1_i_7_n_0;
wire Lxx_11__1_carry__1_i_8_n_0;
wire Lxx_11__1_carry__1_i_9_n_0;
wire Lxx_11__1_carry__1_n_0;
wire Lxx_11__1_carry__1_n_1;
wire Lxx_11__1_carry__1_n_2;
wire Lxx_11__1_carry__1_n_3;
wire Lxx_11__1_carry__2_i_10_n_0;
wire Lxx_11__1_carry__2_i_11_n_0;
wire Lxx_11__1_carry__2_i_12_n_0;
wire Lxx_11__1_carry__2_i_1_n_0;
wire Lxx_11__1_carry__2_i_2_n_0;
wire Lxx_11__1_carry__2_i_3_n_0;
wire Lxx_11__1_carry__2_i_4_n_0;
wire Lxx_11__1_carry__2_i_5_n_0;
wire Lxx_11__1_carry__2_i_6_n_0;
wire Lxx_11__1_carry__2_i_7_n_0;
wire Lxx_11__1_carry__2_i_8_n_0;
wire Lxx_11__1_carry__2_i_9_n_0;
wire Lxx_11__1_carry__2_n_1;
wire Lxx_11__1_carry__2_n_2;
wire Lxx_11__1_carry__2_n_3;
wire Lxx_11__1_carry_i_1_n_0;
wire Lxx_11__1_carry_i_2_n_0;
wire Lxx_11__1_carry_i_3_n_0;
wire Lxx_11__1_carry_i_4_n_0;
wire Lxx_11__1_carry_i_5_n_0;
wire Lxx_11__1_carry_i_6_n_0;
wire Lxx_11__1_carry_i_7_n_0;
wire Lxx_11__1_carry_i_8_n_0;
wire Lxx_11__1_carry_i_9_n_0;
wire Lxx_11__1_carry_n_0;
wire Lxx_11__1_carry_n_1;
wire Lxx_11__1_carry_n_2;
wire Lxx_11__1_carry_n_3;
wire \Lxx_2[15]_i_1_n_0 ;
wire \Lxx_2_reg_n_0_[0] ;
wire \Lxx_2_reg_n_0_[10] ;
wire \Lxx_2_reg_n_0_[11] ;
wire \Lxx_2_reg_n_0_[12] ;
wire \Lxx_2_reg_n_0_[13] ;
wire \Lxx_2_reg_n_0_[14] ;
wire \Lxx_2_reg_n_0_[15] ;
wire \Lxx_2_reg_n_0_[1] ;
wire \Lxx_2_reg_n_0_[2] ;
wire \Lxx_2_reg_n_0_[3] ;
wire \Lxx_2_reg_n_0_[4] ;
wire \Lxx_2_reg_n_0_[5] ;
wire \Lxx_2_reg_n_0_[6] ;
wire \Lxx_2_reg_n_0_[7] ;
wire \Lxx_2_reg_n_0_[8] ;
wire \Lxx_2_reg_n_0_[9] ;
wire Lxy0__1_carry__0_i_10_n_0;
wire Lxy0__1_carry__0_i_11_n_0;
wire Lxy0__1_carry__0_i_12_n_0;
wire Lxy0__1_carry__0_i_1_n_0;
wire Lxy0__1_carry__0_i_2_n_0;
wire Lxy0__1_carry__0_i_3_n_0;
wire Lxy0__1_carry__0_i_4_n_0;
wire Lxy0__1_carry__0_i_5_n_0;
wire Lxy0__1_carry__0_i_6_n_0;
wire Lxy0__1_carry__0_i_7_n_0;
wire Lxy0__1_carry__0_i_8_n_0;
wire Lxy0__1_carry__0_i_9_n_0;
wire Lxy0__1_carry__0_n_0;
wire Lxy0__1_carry__0_n_1;
wire Lxy0__1_carry__0_n_2;
wire Lxy0__1_carry__0_n_3;
wire Lxy0__1_carry__0_n_4;
wire Lxy0__1_carry__0_n_5;
wire Lxy0__1_carry__0_n_6;
wire Lxy0__1_carry__0_n_7;
wire Lxy0__1_carry__1_i_10_n_0;
wire Lxy0__1_carry__1_i_11_n_0;
wire Lxy0__1_carry__1_i_12_n_0;
wire Lxy0__1_carry__1_i_1_n_0;
wire Lxy0__1_carry__1_i_2_n_0;
wire Lxy0__1_carry__1_i_3_n_0;
wire Lxy0__1_carry__1_i_4_n_0;
wire Lxy0__1_carry__1_i_5_n_0;
wire Lxy0__1_carry__1_i_6_n_0;
wire Lxy0__1_carry__1_i_7_n_0;
wire Lxy0__1_carry__1_i_8_n_0;
wire Lxy0__1_carry__1_i_9_n_0;
wire Lxy0__1_carry__1_n_0;
wire Lxy0__1_carry__1_n_1;
wire Lxy0__1_carry__1_n_2;
wire Lxy0__1_carry__1_n_3;
wire Lxy0__1_carry__1_n_4;
wire Lxy0__1_carry__1_n_5;
wire Lxy0__1_carry__1_n_6;
wire Lxy0__1_carry__1_n_7;
wire Lxy0__1_carry__2_i_10_n_0;
wire Lxy0__1_carry__2_i_11_n_0;
wire Lxy0__1_carry__2_i_12_n_0;
wire Lxy0__1_carry__2_i_1_n_0;
wire Lxy0__1_carry__2_i_2_n_0;
wire Lxy0__1_carry__2_i_3_n_0;
wire Lxy0__1_carry__2_i_4_n_0;
wire Lxy0__1_carry__2_i_5_n_0;
wire Lxy0__1_carry__2_i_6_n_0;
wire Lxy0__1_carry__2_i_7_n_0;
wire Lxy0__1_carry__2_i_8_n_0;
wire Lxy0__1_carry__2_i_9_n_0;
wire Lxy0__1_carry__2_n_1;
wire Lxy0__1_carry__2_n_2;
wire Lxy0__1_carry__2_n_3;
wire Lxy0__1_carry__2_n_4;
wire Lxy0__1_carry__2_n_5;
wire Lxy0__1_carry__2_n_6;
wire Lxy0__1_carry__2_n_7;
wire Lxy0__1_carry_i_10_n_0;
wire Lxy0__1_carry_i_1_n_0;
wire Lxy0__1_carry_i_2_n_0;
wire Lxy0__1_carry_i_3_n_0;
wire Lxy0__1_carry_i_4_n_0;
wire Lxy0__1_carry_i_5_n_0;
wire Lxy0__1_carry_i_6_n_0;
wire Lxy0__1_carry_i_7_n_0;
wire Lxy0__1_carry_i_8_n_0;
wire Lxy0__1_carry_i_9_n_0;
wire Lxy0__1_carry_n_0;
wire Lxy0__1_carry_n_1;
wire Lxy0__1_carry_n_2;
wire Lxy0__1_carry_n_3;
wire Lxy0__1_carry_n_4;
wire Lxy0__1_carry_n_5;
wire Lxy0__1_carry_n_6;
wire Lxy0__1_carry_n_7;
wire \Lxy_0[15]_i_1_n_0 ;
wire \Lxy_0_reg_n_0_[0] ;
wire \Lxy_0_reg_n_0_[10] ;
wire \Lxy_0_reg_n_0_[11] ;
wire \Lxy_0_reg_n_0_[12] ;
wire \Lxy_0_reg_n_0_[13] ;
wire \Lxy_0_reg_n_0_[14] ;
wire \Lxy_0_reg_n_0_[15] ;
wire \Lxy_0_reg_n_0_[1] ;
wire \Lxy_0_reg_n_0_[2] ;
wire \Lxy_0_reg_n_0_[3] ;
wire \Lxy_0_reg_n_0_[4] ;
wire \Lxy_0_reg_n_0_[5] ;
wire \Lxy_0_reg_n_0_[6] ;
wire \Lxy_0_reg_n_0_[7] ;
wire \Lxy_0_reg_n_0_[8] ;
wire \Lxy_0_reg_n_0_[9] ;
wire Lxy_1;
wire \Lxy_1_reg_n_0_[0] ;
wire \Lxy_1_reg_n_0_[10] ;
wire \Lxy_1_reg_n_0_[11] ;
wire \Lxy_1_reg_n_0_[12] ;
wire \Lxy_1_reg_n_0_[13] ;
wire \Lxy_1_reg_n_0_[14] ;
wire \Lxy_1_reg_n_0_[15] ;
wire \Lxy_1_reg_n_0_[1] ;
wire \Lxy_1_reg_n_0_[2] ;
wire \Lxy_1_reg_n_0_[3] ;
wire \Lxy_1_reg_n_0_[4] ;
wire \Lxy_1_reg_n_0_[5] ;
wire \Lxy_1_reg_n_0_[6] ;
wire \Lxy_1_reg_n_0_[7] ;
wire \Lxy_1_reg_n_0_[8] ;
wire \Lxy_1_reg_n_0_[9] ;
wire [15:0]Lxy_2;
wire [15:0]Lxy_3;
wire Lyy0_carry__0_i_1_n_0;
wire Lyy0_carry__0_i_2_n_0;
wire Lyy0_carry__0_i_3_n_0;
wire Lyy0_carry__0_i_4_n_0;
wire Lyy0_carry__0_i_5_n_0;
wire Lyy0_carry__0_i_6_n_0;
wire Lyy0_carry__0_i_7_n_0;
wire Lyy0_carry__0_i_8_n_0;
wire Lyy0_carry__0_n_0;
wire Lyy0_carry__0_n_1;
wire Lyy0_carry__0_n_2;
wire Lyy0_carry__0_n_3;
wire Lyy0_carry__1_i_1_n_0;
wire Lyy0_carry__1_i_2_n_0;
wire Lyy0_carry__1_i_3_n_0;
wire Lyy0_carry__1_i_4_n_0;
wire Lyy0_carry__1_i_5_n_0;
wire Lyy0_carry__1_i_6_n_0;
wire Lyy0_carry__1_i_7_n_0;
wire Lyy0_carry__1_i_8_n_0;
wire Lyy0_carry__1_n_0;
wire Lyy0_carry__1_n_1;
wire Lyy0_carry__1_n_2;
wire Lyy0_carry__1_n_3;
wire Lyy0_carry__2_i_1_n_0;
wire Lyy0_carry__2_i_2_n_0;
wire Lyy0_carry__2_i_3_n_0;
wire Lyy0_carry__2_i_4_n_0;
wire Lyy0_carry__2_i_5_n_0;
wire Lyy0_carry__2_i_6_n_0;
wire Lyy0_carry__2_i_7_n_0;
wire Lyy0_carry__2_n_1;
wire Lyy0_carry__2_n_2;
wire Lyy0_carry__2_n_3;
wire Lyy0_carry_i_1_n_0;
wire Lyy0_carry_i_2_n_0;
wire Lyy0_carry_i_3_n_0;
wire Lyy0_carry_i_4_n_0;
wire Lyy0_carry_i_5_n_0;
wire Lyy0_carry_i_6_n_0;
wire Lyy0_carry_n_0;
wire Lyy0_carry_n_1;
wire Lyy0_carry_n_2;
wire Lyy0_carry_n_3;
wire Lyy_0;
wire \Lyy_0_reg_n_0_[0] ;
wire \Lyy_0_reg_n_0_[10] ;
wire \Lyy_0_reg_n_0_[11] ;
wire \Lyy_0_reg_n_0_[12] ;
wire \Lyy_0_reg_n_0_[13] ;
wire \Lyy_0_reg_n_0_[14] ;
wire \Lyy_0_reg_n_0_[15] ;
wire \Lyy_0_reg_n_0_[1] ;
wire \Lyy_0_reg_n_0_[2] ;
wire \Lyy_0_reg_n_0_[3] ;
wire \Lyy_0_reg_n_0_[4] ;
wire \Lyy_0_reg_n_0_[5] ;
wire \Lyy_0_reg_n_0_[6] ;
wire \Lyy_0_reg_n_0_[7] ;
wire \Lyy_0_reg_n_0_[8] ;
wire \Lyy_0_reg_n_0_[9] ;
wire [15:1]Lyy_1;
wire [15:0]Lyy_20;
wire Lyy_20__1_carry__0_i_10_n_0;
wire Lyy_20__1_carry__0_i_11_n_0;
wire Lyy_20__1_carry__0_i_12_n_0;
wire Lyy_20__1_carry__0_i_1_n_0;
wire Lyy_20__1_carry__0_i_2_n_0;
wire Lyy_20__1_carry__0_i_3_n_0;
wire Lyy_20__1_carry__0_i_4_n_0;
wire Lyy_20__1_carry__0_i_5_n_0;
wire Lyy_20__1_carry__0_i_6_n_0;
wire Lyy_20__1_carry__0_i_7_n_0;
wire Lyy_20__1_carry__0_i_8_n_0;
wire Lyy_20__1_carry__0_i_9_n_0;
wire Lyy_20__1_carry__0_n_0;
wire Lyy_20__1_carry__0_n_1;
wire Lyy_20__1_carry__0_n_2;
wire Lyy_20__1_carry__0_n_3;
wire Lyy_20__1_carry__1_i_10_n_0;
wire Lyy_20__1_carry__1_i_11_n_0;
wire Lyy_20__1_carry__1_i_12_n_0;
wire Lyy_20__1_carry__1_i_1_n_0;
wire Lyy_20__1_carry__1_i_2_n_0;
wire Lyy_20__1_carry__1_i_3_n_0;
wire Lyy_20__1_carry__1_i_4_n_0;
wire Lyy_20__1_carry__1_i_5_n_0;
wire Lyy_20__1_carry__1_i_6_n_0;
wire Lyy_20__1_carry__1_i_7_n_0;
wire Lyy_20__1_carry__1_i_8_n_0;
wire Lyy_20__1_carry__1_i_9_n_0;
wire Lyy_20__1_carry__1_n_0;
wire Lyy_20__1_carry__1_n_1;
wire Lyy_20__1_carry__1_n_2;
wire Lyy_20__1_carry__1_n_3;
wire Lyy_20__1_carry__2_i_10_n_0;
wire Lyy_20__1_carry__2_i_11_n_0;
wire Lyy_20__1_carry__2_i_1_n_0;
wire Lyy_20__1_carry__2_i_2_n_0;
wire Lyy_20__1_carry__2_i_3_n_0;
wire Lyy_20__1_carry__2_i_4_n_0;
wire Lyy_20__1_carry__2_i_5_n_0;
wire Lyy_20__1_carry__2_i_6_n_0;
wire Lyy_20__1_carry__2_i_7_n_0;
wire Lyy_20__1_carry__2_i_8_n_0;
wire Lyy_20__1_carry__2_i_9_n_0;
wire Lyy_20__1_carry__2_n_1;
wire Lyy_20__1_carry__2_n_2;
wire Lyy_20__1_carry__2_n_3;
wire Lyy_20__1_carry_i_1_n_0;
wire Lyy_20__1_carry_i_2_n_0;
wire Lyy_20__1_carry_i_3_n_0;
wire Lyy_20__1_carry_i_4_n_0;
wire Lyy_20__1_carry_i_5_n_0;
wire Lyy_20__1_carry_i_6_n_0;
wire Lyy_20__1_carry_i_7_n_0;
wire Lyy_20__1_carry_i_8_n_0;
wire Lyy_20__1_carry_i_9_n_0;
wire Lyy_20__1_carry_n_0;
wire Lyy_20__1_carry_n_1;
wire Lyy_20__1_carry_n_2;
wire Lyy_20__1_carry_n_3;
wire \Lyy_2[15]_i_1_n_0 ;
wire [15:0]Lyy_2_bottom_left;
wire [15:0]Lyy_2_bottom_right;
wire [15:0]Lyy_2_bottom_right01_out;
wire Lyy_2_bottom_right0__0_carry__0_i_10_n_0;
wire Lyy_2_bottom_right0__0_carry__0_i_11_n_0;
wire Lyy_2_bottom_right0__0_carry__0_i_12_n_0;
wire Lyy_2_bottom_right0__0_carry__0_i_1_n_0;
wire Lyy_2_bottom_right0__0_carry__0_i_2_n_0;
wire Lyy_2_bottom_right0__0_carry__0_i_3_n_0;
wire Lyy_2_bottom_right0__0_carry__0_i_4_n_0;
wire Lyy_2_bottom_right0__0_carry__0_i_5_n_0;
wire Lyy_2_bottom_right0__0_carry__0_i_6_n_0;
wire Lyy_2_bottom_right0__0_carry__0_i_7_n_0;
wire Lyy_2_bottom_right0__0_carry__0_i_8_n_0;
wire Lyy_2_bottom_right0__0_carry__0_i_9_n_0;
wire Lyy_2_bottom_right0__0_carry__0_n_0;
wire Lyy_2_bottom_right0__0_carry__0_n_1;
wire Lyy_2_bottom_right0__0_carry__0_n_2;
wire Lyy_2_bottom_right0__0_carry__0_n_3;
wire Lyy_2_bottom_right0__0_carry__1_i_10_n_0;
wire Lyy_2_bottom_right0__0_carry__1_i_11_n_0;
wire Lyy_2_bottom_right0__0_carry__1_i_12_n_0;
wire Lyy_2_bottom_right0__0_carry__1_i_1_n_0;
wire Lyy_2_bottom_right0__0_carry__1_i_2_n_0;
wire Lyy_2_bottom_right0__0_carry__1_i_3_n_0;
wire Lyy_2_bottom_right0__0_carry__1_i_4_n_0;
wire Lyy_2_bottom_right0__0_carry__1_i_5_n_0;
wire Lyy_2_bottom_right0__0_carry__1_i_6_n_0;
wire Lyy_2_bottom_right0__0_carry__1_i_7_n_0;
wire Lyy_2_bottom_right0__0_carry__1_i_8_n_0;
wire Lyy_2_bottom_right0__0_carry__1_i_9_n_0;
wire Lyy_2_bottom_right0__0_carry__1_n_0;
wire Lyy_2_bottom_right0__0_carry__1_n_1;
wire Lyy_2_bottom_right0__0_carry__1_n_2;
wire Lyy_2_bottom_right0__0_carry__1_n_3;
wire Lyy_2_bottom_right0__0_carry__2_i_10_n_0;
wire Lyy_2_bottom_right0__0_carry__2_i_11_n_0;
wire Lyy_2_bottom_right0__0_carry__2_i_12_n_0;
wire Lyy_2_bottom_right0__0_carry__2_i_1_n_0;
wire Lyy_2_bottom_right0__0_carry__2_i_2_n_0;
wire Lyy_2_bottom_right0__0_carry__2_i_3_n_0;
wire Lyy_2_bottom_right0__0_carry__2_i_4_n_0;
wire Lyy_2_bottom_right0__0_carry__2_i_5_n_0;
wire Lyy_2_bottom_right0__0_carry__2_i_6_n_0;
wire Lyy_2_bottom_right0__0_carry__2_i_7_n_0;
wire Lyy_2_bottom_right0__0_carry__2_i_8_n_0;
wire Lyy_2_bottom_right0__0_carry__2_i_9_n_0;
wire Lyy_2_bottom_right0__0_carry__2_n_1;
wire Lyy_2_bottom_right0__0_carry__2_n_2;
wire Lyy_2_bottom_right0__0_carry__2_n_3;
wire Lyy_2_bottom_right0__0_carry_i_10_n_0;
wire Lyy_2_bottom_right0__0_carry_i_11_n_0;
wire Lyy_2_bottom_right0__0_carry_i_1_n_0;
wire Lyy_2_bottom_right0__0_carry_i_2_n_0;
wire Lyy_2_bottom_right0__0_carry_i_3_n_0;
wire Lyy_2_bottom_right0__0_carry_i_4_n_0;
wire Lyy_2_bottom_right0__0_carry_i_5_n_0;
wire Lyy_2_bottom_right0__0_carry_i_6_n_0;
wire Lyy_2_bottom_right0__0_carry_i_7_n_0;
wire Lyy_2_bottom_right0__0_carry_i_8_n_0;
wire Lyy_2_bottom_right0__0_carry_i_9_n_0;
wire Lyy_2_bottom_right0__0_carry_n_0;
wire Lyy_2_bottom_right0__0_carry_n_1;
wire Lyy_2_bottom_right0__0_carry_n_2;
wire Lyy_2_bottom_right0__0_carry_n_3;
wire \Lyy_2_reg_n_0_[0] ;
wire \Lyy_2_reg_n_0_[10] ;
wire \Lyy_2_reg_n_0_[11] ;
wire \Lyy_2_reg_n_0_[12] ;
wire \Lyy_2_reg_n_0_[13] ;
wire \Lyy_2_reg_n_0_[14] ;
wire \Lyy_2_reg_n_0_[15] ;
wire \Lyy_2_reg_n_0_[1] ;
wire \Lyy_2_reg_n_0_[2] ;
wire \Lyy_2_reg_n_0_[3] ;
wire \Lyy_2_reg_n_0_[4] ;
wire \Lyy_2_reg_n_0_[5] ;
wire \Lyy_2_reg_n_0_[6] ;
wire \Lyy_2_reg_n_0_[7] ;
wire \Lyy_2_reg_n_0_[8] ;
wire \Lyy_2_reg_n_0_[9] ;
wire [15:0]Lyy_2_top_left;
wire [15:0]Lyy_2_top_right;
wire active;
wire addr_0;
wire \addr_0[0]_i_1_n_0 ;
wire \addr_0[10]_i_1_n_0 ;
wire \addr_0[11]_i_1_n_0 ;
wire \addr_0[12]_i_1_n_0 ;
wire \addr_0[13]_i_2_n_0 ;
wire \addr_0[1]_i_1_n_0 ;
wire \addr_0[2]_i_1_n_0 ;
wire \addr_0[3]_i_1_n_0 ;
wire \addr_0[4]_i_1_n_0 ;
wire \addr_0[5]_i_1_n_0 ;
wire \addr_0[6]_i_1_n_0 ;
wire \addr_0[7]_i_1_n_0 ;
wire \addr_0[8]_i_1_n_0 ;
wire \addr_0[9]_i_1_n_0 ;
wire \addr_0_reg_n_0_[0] ;
wire \addr_0_reg_n_0_[10] ;
wire \addr_0_reg_n_0_[11] ;
wire \addr_0_reg_n_0_[12] ;
wire \addr_0_reg_n_0_[13] ;
wire \addr_0_reg_n_0_[1] ;
wire \addr_0_reg_n_0_[2] ;
wire \addr_0_reg_n_0_[3] ;
wire \addr_0_reg_n_0_[4] ;
wire \addr_0_reg_n_0_[5] ;
wire \addr_0_reg_n_0_[6] ;
wire \addr_0_reg_n_0_[7] ;
wire \addr_0_reg_n_0_[8] ;
wire \addr_0_reg_n_0_[9] ;
wire [13:0]addr_1;
wire \addr_1[0]_i_1_n_0 ;
wire \addr_1[10]_i_1_n_0 ;
wire \addr_1[11]_i_1_n_0 ;
wire \addr_1[12]_i_1_n_0 ;
wire \addr_1[13]_i_1_n_0 ;
wire \addr_1[1]_i_1_n_0 ;
wire \addr_1[2]_i_1_n_0 ;
wire \addr_1[3]_i_1_n_0 ;
wire \addr_1[4]_i_1_n_0 ;
wire \addr_1[5]_i_1_n_0 ;
wire \addr_1[6]_i_1_n_0 ;
wire \addr_1[7]_i_1_n_0 ;
wire \addr_1[8]_i_1_n_0 ;
wire \addr_1[9]_i_1_n_0 ;
wire bottom_left_0;
wire \bottom_left_0_reg_n_0_[0] ;
wire \bottom_left_0_reg_n_0_[10] ;
wire \bottom_left_0_reg_n_0_[11] ;
wire \bottom_left_0_reg_n_0_[12] ;
wire \bottom_left_0_reg_n_0_[13] ;
wire \bottom_left_0_reg_n_0_[14] ;
wire \bottom_left_0_reg_n_0_[15] ;
wire \bottom_left_0_reg_n_0_[1] ;
wire \bottom_left_0_reg_n_0_[2] ;
wire \bottom_left_0_reg_n_0_[3] ;
wire \bottom_left_0_reg_n_0_[4] ;
wire \bottom_left_0_reg_n_0_[5] ;
wire \bottom_left_0_reg_n_0_[6] ;
wire \bottom_left_0_reg_n_0_[7] ;
wire \bottom_left_0_reg_n_0_[8] ;
wire \bottom_left_0_reg_n_0_[9] ;
wire [15:0]bottom_left_1;
wire \bottom_right_0[0]_i_2_n_0 ;
wire \bottom_right_0[10]_i_2_n_0 ;
wire \bottom_right_0[11]_i_2_n_0 ;
wire \bottom_right_0[12]_i_2_n_0 ;
wire \bottom_right_0[13]_i_2_n_0 ;
wire \bottom_right_0[14]_i_2_n_0 ;
wire \bottom_right_0[15]_i_1_n_0 ;
wire \bottom_right_0[15]_i_3_n_0 ;
wire \bottom_right_0[15]_i_4_n_0 ;
wire \bottom_right_0[15]_i_5_n_0 ;
wire \bottom_right_0[1]_i_2_n_0 ;
wire \bottom_right_0[2]_i_2_n_0 ;
wire \bottom_right_0[3]_i_2_n_0 ;
wire \bottom_right_0[4]_i_2_n_0 ;
wire \bottom_right_0[5]_i_2_n_0 ;
wire \bottom_right_0[6]_i_2_n_0 ;
wire \bottom_right_0[7]_i_2_n_0 ;
wire \bottom_right_0[8]_i_2_n_0 ;
wire \bottom_right_0[9]_i_2_n_0 ;
wire \bottom_right_0_reg_n_0_[0] ;
wire \bottom_right_0_reg_n_0_[10] ;
wire \bottom_right_0_reg_n_0_[11] ;
wire \bottom_right_0_reg_n_0_[12] ;
wire \bottom_right_0_reg_n_0_[13] ;
wire \bottom_right_0_reg_n_0_[14] ;
wire \bottom_right_0_reg_n_0_[15] ;
wire \bottom_right_0_reg_n_0_[1] ;
wire \bottom_right_0_reg_n_0_[2] ;
wire \bottom_right_0_reg_n_0_[3] ;
wire \bottom_right_0_reg_n_0_[4] ;
wire \bottom_right_0_reg_n_0_[5] ;
wire \bottom_right_0_reg_n_0_[6] ;
wire \bottom_right_0_reg_n_0_[7] ;
wire \bottom_right_0_reg_n_0_[8] ;
wire \bottom_right_0_reg_n_0_[9] ;
wire bottom_right_1;
wire \bottom_right_1[0]_i_1_n_0 ;
wire \bottom_right_1[10]_i_1_n_0 ;
wire \bottom_right_1[11]_i_1_n_0 ;
wire \bottom_right_1[12]_i_1_n_0 ;
wire \bottom_right_1[13]_i_1_n_0 ;
wire \bottom_right_1[14]_i_1_n_0 ;
wire \bottom_right_1[15]_i_1_n_0 ;
wire \bottom_right_1[1]_i_1_n_0 ;
wire \bottom_right_1[2]_i_1_n_0 ;
wire \bottom_right_1[3]_i_1_n_0 ;
wire \bottom_right_1[4]_i_1_n_0 ;
wire \bottom_right_1[5]_i_1_n_0 ;
wire \bottom_right_1[6]_i_1_n_0 ;
wire \bottom_right_1[7]_i_1_n_0 ;
wire \bottom_right_1[8]_i_1_n_0 ;
wire \bottom_right_1[9]_i_1_n_0 ;
wire \bottom_right_1_reg_n_0_[0] ;
wire \bottom_right_1_reg_n_0_[10] ;
wire \bottom_right_1_reg_n_0_[11] ;
wire \bottom_right_1_reg_n_0_[12] ;
wire \bottom_right_1_reg_n_0_[13] ;
wire \bottom_right_1_reg_n_0_[14] ;
wire \bottom_right_1_reg_n_0_[15] ;
wire \bottom_right_1_reg_n_0_[1] ;
wire \bottom_right_1_reg_n_0_[2] ;
wire \bottom_right_1_reg_n_0_[3] ;
wire \bottom_right_1_reg_n_0_[4] ;
wire \bottom_right_1_reg_n_0_[5] ;
wire \bottom_right_1_reg_n_0_[6] ;
wire \bottom_right_1_reg_n_0_[7] ;
wire \bottom_right_1_reg_n_0_[8] ;
wire \bottom_right_1_reg_n_0_[9] ;
wire \cache[10]_5 ;
wire \cache[9][15]_i_1_n_0 ;
wire [15:0]\cache_reg[0]_4 ;
wire [15:0]\cache_reg[10]_3 ;
wire \cache_reg[2][0]_srl2___U0_cache_reg_r_0_n_0 ;
wire \cache_reg[2][10]_srl2___U0_cache_reg_r_0_n_0 ;
wire \cache_reg[2][11]_srl2___U0_cache_reg_r_0_n_0 ;
wire \cache_reg[2][12]_srl2___U0_cache_reg_r_0_n_0 ;
wire \cache_reg[2][13]_srl2___U0_cache_reg_r_0_n_0 ;
wire \cache_reg[2][14]_srl2___U0_cache_reg_r_0_n_0 ;
wire \cache_reg[2][15]_srl2___U0_cache_reg_r_0_n_0 ;
wire \cache_reg[2][1]_srl2___U0_cache_reg_r_0_n_0 ;
wire \cache_reg[2][2]_srl2___U0_cache_reg_r_0_n_0 ;
wire \cache_reg[2][3]_srl2___U0_cache_reg_r_0_n_0 ;
wire \cache_reg[2][4]_srl2___U0_cache_reg_r_0_n_0 ;
wire \cache_reg[2][5]_srl2___U0_cache_reg_r_0_n_0 ;
wire \cache_reg[2][6]_srl2___U0_cache_reg_r_0_n_0 ;
wire \cache_reg[2][7]_srl2___U0_cache_reg_r_0_n_0 ;
wire \cache_reg[2][8]_srl2___U0_cache_reg_r_0_n_0 ;
wire \cache_reg[2][9]_srl2___U0_cache_reg_r_0_n_0 ;
wire \cache_reg[3][0]_U0_cache_reg_r_1_n_0 ;
wire \cache_reg[3][10]_U0_cache_reg_r_1_n_0 ;
wire \cache_reg[3][11]_U0_cache_reg_r_1_n_0 ;
wire \cache_reg[3][12]_U0_cache_reg_r_1_n_0 ;
wire \cache_reg[3][13]_U0_cache_reg_r_1_n_0 ;
wire \cache_reg[3][14]_U0_cache_reg_r_1_n_0 ;
wire \cache_reg[3][15]_U0_cache_reg_r_1_n_0 ;
wire \cache_reg[3][1]_U0_cache_reg_r_1_n_0 ;
wire \cache_reg[3][2]_U0_cache_reg_r_1_n_0 ;
wire \cache_reg[3][3]_U0_cache_reg_r_1_n_0 ;
wire \cache_reg[3][4]_U0_cache_reg_r_1_n_0 ;
wire \cache_reg[3][5]_U0_cache_reg_r_1_n_0 ;
wire \cache_reg[3][6]_U0_cache_reg_r_1_n_0 ;
wire \cache_reg[3][7]_U0_cache_reg_r_1_n_0 ;
wire \cache_reg[3][8]_U0_cache_reg_r_1_n_0 ;
wire \cache_reg[3][9]_U0_cache_reg_r_1_n_0 ;
wire [15:0]\cache_reg[4]_0 ;
wire \cache_reg[6][0]_srl2___U0_cache_reg_r_0_n_0 ;
wire \cache_reg[6][10]_srl2___U0_cache_reg_r_0_n_0 ;
wire \cache_reg[6][11]_srl2___U0_cache_reg_r_0_n_0 ;
wire \cache_reg[6][12]_srl2___U0_cache_reg_r_0_n_0 ;
wire \cache_reg[6][13]_srl2___U0_cache_reg_r_0_n_0 ;
wire \cache_reg[6][14]_srl2___U0_cache_reg_r_0_n_0 ;
wire \cache_reg[6][15]_srl2___U0_cache_reg_r_0_n_0 ;
wire \cache_reg[6][1]_srl2___U0_cache_reg_r_0_n_0 ;
wire \cache_reg[6][2]_srl2___U0_cache_reg_r_0_n_0 ;
wire \cache_reg[6][3]_srl2___U0_cache_reg_r_0_n_0 ;
wire \cache_reg[6][4]_srl2___U0_cache_reg_r_0_n_0 ;
wire \cache_reg[6][5]_srl2___U0_cache_reg_r_0_n_0 ;
wire \cache_reg[6][6]_srl2___U0_cache_reg_r_0_n_0 ;
wire \cache_reg[6][7]_srl2___U0_cache_reg_r_0_n_0 ;
wire \cache_reg[6][8]_srl2___U0_cache_reg_r_0_n_0 ;
wire \cache_reg[6][9]_srl2___U0_cache_reg_r_0_n_0 ;
wire \cache_reg[7][0]_U0_cache_reg_r_1_n_0 ;
wire \cache_reg[7][10]_U0_cache_reg_r_1_n_0 ;
wire \cache_reg[7][11]_U0_cache_reg_r_1_n_0 ;
wire \cache_reg[7][12]_U0_cache_reg_r_1_n_0 ;
wire \cache_reg[7][13]_U0_cache_reg_r_1_n_0 ;
wire \cache_reg[7][14]_U0_cache_reg_r_1_n_0 ;
wire \cache_reg[7][15]_U0_cache_reg_r_1_n_0 ;
wire \cache_reg[7][1]_U0_cache_reg_r_1_n_0 ;
wire \cache_reg[7][2]_U0_cache_reg_r_1_n_0 ;
wire \cache_reg[7][3]_U0_cache_reg_r_1_n_0 ;
wire \cache_reg[7][4]_U0_cache_reg_r_1_n_0 ;
wire \cache_reg[7][5]_U0_cache_reg_r_1_n_0 ;
wire \cache_reg[7][6]_U0_cache_reg_r_1_n_0 ;
wire \cache_reg[7][7]_U0_cache_reg_r_1_n_0 ;
wire \cache_reg[7][8]_U0_cache_reg_r_1_n_0 ;
wire \cache_reg[7][9]_U0_cache_reg_r_1_n_0 ;
wire [15:0]\cache_reg[8]_1 ;
wire [15:0]\cache_reg[9]_2 ;
wire cache_reg_gate__0_n_0;
wire cache_reg_gate__10_n_0;
wire cache_reg_gate__11_n_0;
wire cache_reg_gate__12_n_0;
wire cache_reg_gate__13_n_0;
wire cache_reg_gate__14_n_0;
wire cache_reg_gate__15_n_0;
wire cache_reg_gate__16_n_0;
wire cache_reg_gate__17_n_0;
wire cache_reg_gate__18_n_0;
wire cache_reg_gate__19_n_0;
wire cache_reg_gate__1_n_0;
wire cache_reg_gate__20_n_0;
wire cache_reg_gate__21_n_0;
wire cache_reg_gate__22_n_0;
wire cache_reg_gate__23_n_0;
wire cache_reg_gate__24_n_0;
wire cache_reg_gate__25_n_0;
wire cache_reg_gate__26_n_0;
wire cache_reg_gate__27_n_0;
wire cache_reg_gate__28_n_0;
wire cache_reg_gate__29_n_0;
wire cache_reg_gate__2_n_0;
wire cache_reg_gate__30_n_0;
wire cache_reg_gate__3_n_0;
wire cache_reg_gate__4_n_0;
wire cache_reg_gate__5_n_0;
wire cache_reg_gate__6_n_0;
wire cache_reg_gate__7_n_0;
wire cache_reg_gate__8_n_0;
wire cache_reg_gate__9_n_0;
wire cache_reg_gate_n_0;
wire cache_reg_r_0_n_0;
wire cache_reg_r_1_n_0;
wire cache_reg_r_n_0;
wire clk_x16;
wire compute_addr_0;
wire \compute_addr_0[0]_i_1_n_0 ;
wire \compute_addr_0[10]_i_1_n_0 ;
wire \compute_addr_0[10]_i_2_n_0 ;
wire \compute_addr_0[11]_i_1_n_0 ;
wire \compute_addr_0[11]_i_2_n_0 ;
wire \compute_addr_0[11]_i_3_n_0 ;
wire \compute_addr_0[12]_i_1_n_0 ;
wire \compute_addr_0[12]_i_2_n_0 ;
wire \compute_addr_0[13]_i_2_n_0 ;
wire \compute_addr_0[13]_i_3_n_0 ;
wire \compute_addr_0[1]_i_1_n_0 ;
wire \compute_addr_0[2]_i_1_n_0 ;
wire \compute_addr_0[3]_i_1_n_0 ;
wire \compute_addr_0[4]_i_1_n_0 ;
wire \compute_addr_0[5]_i_1_n_0 ;
wire \compute_addr_0[6]_i_1_n_0 ;
wire \compute_addr_0[7]_i_1_n_0 ;
wire \compute_addr_0[8]_i_1_n_0 ;
wire \compute_addr_0[9]_i_1_n_0 ;
wire \compute_addr_0_reg_n_0_[0] ;
wire \compute_addr_0_reg_n_0_[10] ;
wire \compute_addr_0_reg_n_0_[11] ;
wire \compute_addr_0_reg_n_0_[12] ;
wire \compute_addr_0_reg_n_0_[13] ;
wire \compute_addr_0_reg_n_0_[1] ;
wire \compute_addr_0_reg_n_0_[2] ;
wire \compute_addr_0_reg_n_0_[3] ;
wire \compute_addr_0_reg_n_0_[4] ;
wire \compute_addr_0_reg_n_0_[5] ;
wire \compute_addr_0_reg_n_0_[6] ;
wire \compute_addr_0_reg_n_0_[7] ;
wire \compute_addr_0_reg_n_0_[8] ;
wire \compute_addr_0_reg_n_0_[9] ;
wire [13:0]compute_addr_1;
wire \compute_addr_1[0]_i_1_n_0 ;
wire \compute_addr_1[10]_i_1_n_0 ;
wire \compute_addr_1[10]_i_2_n_0 ;
wire \compute_addr_1[11]_i_1_n_0 ;
wire \compute_addr_1[11]_i_2_n_0 ;
wire \compute_addr_1[12]_i_1_n_0 ;
wire \compute_addr_1[12]_i_2_n_0 ;
wire \compute_addr_1[13]_i_1_n_0 ;
wire \compute_addr_1[13]_i_2_n_0 ;
wire \compute_addr_1[1]_i_1_n_0 ;
wire \compute_addr_1[2]_i_1_n_0 ;
wire \compute_addr_1[3]_i_1_n_0 ;
wire \compute_addr_1[4]_i_1_n_0 ;
wire \compute_addr_1[5]_i_1_n_0 ;
wire \compute_addr_1[6]_i_1_n_0 ;
wire \compute_addr_1[7]_i_1_n_0 ;
wire \compute_addr_1[8]_i_1_n_0 ;
wire \compute_addr_1[9]_i_1_n_0 ;
wire compute_addr_2;
wire \compute_addr_2[10]_i_1_n_0 ;
wire \compute_addr_2[10]_i_2_n_0 ;
wire \compute_addr_2[11]_i_1_n_0 ;
wire \compute_addr_2[11]_i_2_n_0 ;
wire \compute_addr_2[12]_i_1_n_0 ;
wire \compute_addr_2[12]_i_2_n_0 ;
wire \compute_addr_2[13]_i_2_n_0 ;
wire \compute_addr_2[13]_i_3_n_0 ;
wire \compute_addr_2[13]_i_4_n_0 ;
wire \compute_addr_2_reg_n_0_[0] ;
wire \compute_addr_2_reg_n_0_[10] ;
wire \compute_addr_2_reg_n_0_[11] ;
wire \compute_addr_2_reg_n_0_[12] ;
wire \compute_addr_2_reg_n_0_[13] ;
wire \compute_addr_2_reg_n_0_[1] ;
wire \compute_addr_2_reg_n_0_[2] ;
wire \compute_addr_2_reg_n_0_[3] ;
wire \compute_addr_2_reg_n_0_[4] ;
wire \compute_addr_2_reg_n_0_[5] ;
wire \compute_addr_2_reg_n_0_[6] ;
wire \compute_addr_2_reg_n_0_[7] ;
wire \compute_addr_2_reg_n_0_[8] ;
wire \compute_addr_2_reg_n_0_[9] ;
wire [13:0]compute_addr_3;
wire \compute_addr_3[0]_i_1_n_0 ;
wire \compute_addr_3[10]_i_1_n_0 ;
wire \compute_addr_3[10]_i_2_n_0 ;
wire \compute_addr_3[11]_i_1_n_0 ;
wire \compute_addr_3[11]_i_2_n_0 ;
wire \compute_addr_3[12]_i_1_n_0 ;
wire \compute_addr_3[12]_i_2_n_0 ;
wire \compute_addr_3[13]_i_1_n_0 ;
wire \compute_addr_3[13]_i_2_n_0 ;
wire \compute_addr_3[1]_i_1_n_0 ;
wire \compute_addr_3[2]_i_1_n_0 ;
wire \compute_addr_3[3]_i_1_n_0 ;
wire \compute_addr_3[4]_i_1_n_0 ;
wire \compute_addr_3[5]_i_1_n_0 ;
wire \compute_addr_3[6]_i_1_n_0 ;
wire \compute_addr_3[7]_i_1_n_0 ;
wire \compute_addr_3[8]_i_1_n_0 ;
wire \compute_addr_3[9]_i_1_n_0 ;
wire corner;
wire \corner_reg_n_0_[0] ;
wire \corner_reg_n_0_[10] ;
wire \corner_reg_n_0_[11] ;
wire \corner_reg_n_0_[12] ;
wire \corner_reg_n_0_[13] ;
wire \corner_reg_n_0_[14] ;
wire \corner_reg_n_0_[15] ;
wire \corner_reg_n_0_[1] ;
wire \corner_reg_n_0_[2] ;
wire \corner_reg_n_0_[3] ;
wire \corner_reg_n_0_[4] ;
wire \corner_reg_n_0_[5] ;
wire \corner_reg_n_0_[6] ;
wire \corner_reg_n_0_[7] ;
wire \corner_reg_n_0_[8] ;
wire \corner_reg_n_0_[9] ;
wire [3:0]cycle;
wire \cycle[0]_i_1_n_0 ;
wire \cycle[0]_rep_i_1_n_0 ;
wire \cycle[1]_i_1_n_0 ;
wire \cycle[1]_rep_i_1__0_n_0 ;
wire \cycle[1]_rep_i_1_n_0 ;
wire \cycle[2]_i_1_n_0 ;
wire \cycle[2]_rep_i_1_n_0 ;
wire \cycle[3]_i_1_n_0 ;
wire \cycle[3]_i_2_n_0 ;
wire \cycle_reg[0]_rep_n_0 ;
wire \cycle_reg[1]_rep__0_n_0 ;
wire \cycle_reg[1]_rep_n_0 ;
wire \cycle_reg[2]_rep_n_0 ;
wire [13:0]data1;
wire [13:0]data2;
wire [13:10]data5;
wire det_0;
wire det_0_reg_i_2_n_0;
wire det_0_reg_n_106;
wire det_0_reg_n_107;
wire det_0_reg_n_108;
wire det_0_reg_n_109;
wire det_0_reg_n_110;
wire det_0_reg_n_111;
wire det_0_reg_n_112;
wire det_0_reg_n_113;
wire det_0_reg_n_114;
wire det_0_reg_n_115;
wire det_0_reg_n_116;
wire det_0_reg_n_117;
wire det_0_reg_n_118;
wire det_0_reg_n_119;
wire det_0_reg_n_120;
wire det_0_reg_n_121;
wire det_0_reg_n_122;
wire det_0_reg_n_123;
wire det_0_reg_n_124;
wire det_0_reg_n_125;
wire det_0_reg_n_126;
wire det_0_reg_n_127;
wire det_0_reg_n_128;
wire det_0_reg_n_129;
wire det_0_reg_n_130;
wire det_0_reg_n_131;
wire det_0_reg_n_132;
wire det_0_reg_n_133;
wire det_0_reg_n_134;
wire det_0_reg_n_135;
wire det_0_reg_n_136;
wire det_0_reg_n_137;
wire det_0_reg_n_138;
wire det_0_reg_n_139;
wire det_0_reg_n_140;
wire det_0_reg_n_141;
wire det_0_reg_n_142;
wire det_0_reg_n_143;
wire det_0_reg_n_144;
wire det_0_reg_n_145;
wire det_0_reg_n_146;
wire det_0_reg_n_147;
wire det_0_reg_n_148;
wire det_0_reg_n_149;
wire det_0_reg_n_150;
wire det_0_reg_n_151;
wire det_0_reg_n_152;
wire det_0_reg_n_153;
wire [31:0]det_abs;
wire [31:1]det_abs0;
wire \det_abs[10]_i_1_n_0 ;
wire \det_abs[11]_i_1_n_0 ;
wire \det_abs[12]_i_1_n_0 ;
wire \det_abs[12]_i_3_n_0 ;
wire \det_abs[12]_i_4_n_0 ;
wire \det_abs[12]_i_5_n_0 ;
wire \det_abs[12]_i_6_n_0 ;
wire \det_abs[13]_i_1_n_0 ;
wire \det_abs[14]_i_1_n_0 ;
wire \det_abs[15]_i_1_n_0 ;
wire \det_abs[16]_i_1_n_0 ;
wire \det_abs[16]_i_3_n_0 ;
wire \det_abs[16]_i_4_n_0 ;
wire \det_abs[16]_i_5_n_0 ;
wire \det_abs[16]_i_6_n_0 ;
wire \det_abs[17]_i_1_n_0 ;
wire \det_abs[18]_i_1_n_0 ;
wire \det_abs[19]_i_1_n_0 ;
wire \det_abs[1]_i_1_n_0 ;
wire \det_abs[20]_i_1_n_0 ;
wire \det_abs[20]_i_3_n_0 ;
wire \det_abs[20]_i_4_n_0 ;
wire \det_abs[20]_i_5_n_0 ;
wire \det_abs[20]_i_6_n_0 ;
wire \det_abs[21]_i_1_n_0 ;
wire \det_abs[22]_i_1_n_0 ;
wire \det_abs[23]_i_1_n_0 ;
wire \det_abs[24]_i_1_n_0 ;
wire \det_abs[24]_i_3_n_0 ;
wire \det_abs[24]_i_4_n_0 ;
wire \det_abs[24]_i_5_n_0 ;
wire \det_abs[24]_i_6_n_0 ;
wire \det_abs[25]_i_1_n_0 ;
wire \det_abs[26]_i_1_n_0 ;
wire \det_abs[27]_i_1_n_0 ;
wire \det_abs[28]_i_1_n_0 ;
wire \det_abs[28]_i_3_n_0 ;
wire \det_abs[28]_i_4_n_0 ;
wire \det_abs[28]_i_5_n_0 ;
wire \det_abs[28]_i_6_n_0 ;
wire \det_abs[29]_i_1_n_0 ;
wire \det_abs[2]_i_1_n_0 ;
wire \det_abs[30]_i_1_n_0 ;
wire \det_abs[31]_i_1_n_0 ;
wire \det_abs[31]_i_3_n_0 ;
wire \det_abs[31]_i_4_n_0 ;
wire \det_abs[31]_i_5_n_0 ;
wire \det_abs[3]_i_1_n_0 ;
wire \det_abs[4]_i_1_n_0 ;
wire \det_abs[4]_i_3_n_0 ;
wire \det_abs[4]_i_4_n_0 ;
wire \det_abs[4]_i_5_n_0 ;
wire \det_abs[4]_i_6_n_0 ;
wire \det_abs[4]_i_7_n_0 ;
wire \det_abs[5]_i_1_n_0 ;
wire \det_abs[6]_i_1_n_0 ;
wire \det_abs[7]_i_1_n_0 ;
wire \det_abs[8]_i_1_n_0 ;
wire \det_abs[8]_i_3_n_0 ;
wire \det_abs[8]_i_4_n_0 ;
wire \det_abs[8]_i_5_n_0 ;
wire \det_abs[8]_i_6_n_0 ;
wire \det_abs[9]_i_1_n_0 ;
wire \det_abs_reg[12]_i_2_n_0 ;
wire \det_abs_reg[12]_i_2_n_1 ;
wire \det_abs_reg[12]_i_2_n_2 ;
wire \det_abs_reg[12]_i_2_n_3 ;
wire \det_abs_reg[16]_i_2_n_0 ;
wire \det_abs_reg[16]_i_2_n_1 ;
wire \det_abs_reg[16]_i_2_n_2 ;
wire \det_abs_reg[16]_i_2_n_3 ;
wire \det_abs_reg[20]_i_2_n_0 ;
wire \det_abs_reg[20]_i_2_n_1 ;
wire \det_abs_reg[20]_i_2_n_2 ;
wire \det_abs_reg[20]_i_2_n_3 ;
wire \det_abs_reg[24]_i_2_n_0 ;
wire \det_abs_reg[24]_i_2_n_1 ;
wire \det_abs_reg[24]_i_2_n_2 ;
wire \det_abs_reg[24]_i_2_n_3 ;
wire \det_abs_reg[28]_i_2_n_0 ;
wire \det_abs_reg[28]_i_2_n_1 ;
wire \det_abs_reg[28]_i_2_n_2 ;
wire \det_abs_reg[28]_i_2_n_3 ;
wire \det_abs_reg[31]_i_2_n_2 ;
wire \det_abs_reg[31]_i_2_n_3 ;
wire \det_abs_reg[4]_i_2_n_0 ;
wire \det_abs_reg[4]_i_2_n_1 ;
wire \det_abs_reg[4]_i_2_n_2 ;
wire \det_abs_reg[4]_i_2_n_3 ;
wire \det_abs_reg[8]_i_2_n_0 ;
wire \det_abs_reg[8]_i_2_n_1 ;
wire \det_abs_reg[8]_i_2_n_2 ;
wire \det_abs_reg[8]_i_2_n_3 ;
wire det_reg_n_100;
wire det_reg_n_101;
wire det_reg_n_102;
wire det_reg_n_103;
wire det_reg_n_104;
wire det_reg_n_105;
wire det_reg_n_74;
wire det_reg_n_75;
wire det_reg_n_76;
wire det_reg_n_77;
wire det_reg_n_78;
wire det_reg_n_79;
wire det_reg_n_80;
wire det_reg_n_81;
wire det_reg_n_82;
wire det_reg_n_83;
wire det_reg_n_84;
wire det_reg_n_85;
wire det_reg_n_86;
wire det_reg_n_87;
wire det_reg_n_88;
wire det_reg_n_89;
wire det_reg_n_90;
wire det_reg_n_91;
wire det_reg_n_92;
wire det_reg_n_93;
wire det_reg_n_94;
wire det_reg_n_95;
wire det_reg_n_96;
wire det_reg_n_97;
wire det_reg_n_98;
wire det_reg_n_99;
wire \din_reg_n_0_[0] ;
wire \din_reg_n_0_[10] ;
wire \din_reg_n_0_[11] ;
wire \din_reg_n_0_[12] ;
wire \din_reg_n_0_[13] ;
wire \din_reg_n_0_[14] ;
wire \din_reg_n_0_[15] ;
wire \din_reg_n_0_[1] ;
wire \din_reg_n_0_[2] ;
wire \din_reg_n_0_[3] ;
wire \din_reg_n_0_[4] ;
wire \din_reg_n_0_[5] ;
wire \din_reg_n_0_[6] ;
wire \din_reg_n_0_[7] ;
wire \din_reg_n_0_[8] ;
wire \din_reg_n_0_[9] ;
wire [15:0]dout_0;
wire [15:0]dout_1;
wire [7:0]g_in;
wire [31:0]hessian_out;
wire i__carry__0_i_1_n_0;
wire i__carry__0_i_2_n_0;
wire i__carry__0_i_3_n_0;
wire i__carry__0_i_4_n_0;
wire i__carry__0_i_5_n_0;
wire i__carry__1_i_1_n_0;
wire i__carry__1_i_2_n_0;
wire i__carry_i_1_n_0;
wire i__carry_i_2_n_0;
wire i__carry_i_3_n_0;
wire i__carry_i_4_n_0;
wire [7:0]last_value;
wire left;
wire \left[15]_i_2_n_0 ;
wire \left[15]_i_3_n_0 ;
wire \left_reg_n_0_[0] ;
wire \left_reg_n_0_[10] ;
wire \left_reg_n_0_[11] ;
wire \left_reg_n_0_[12] ;
wire \left_reg_n_0_[13] ;
wire \left_reg_n_0_[14] ;
wire \left_reg_n_0_[15] ;
wire \left_reg_n_0_[1] ;
wire \left_reg_n_0_[2] ;
wire \left_reg_n_0_[3] ;
wire \left_reg_n_0_[4] ;
wire \left_reg_n_0_[5] ;
wire \left_reg_n_0_[6] ;
wire \left_reg_n_0_[7] ;
wire \left_reg_n_0_[8] ;
wire \left_reg_n_0_[9] ;
wire [15:0]p_0_out;
wire \plusOp_inferred__0/i__carry__0_n_0 ;
wire \plusOp_inferred__0/i__carry__0_n_1 ;
wire \plusOp_inferred__0/i__carry__0_n_2 ;
wire \plusOp_inferred__0/i__carry__0_n_3 ;
wire \plusOp_inferred__0/i__carry__0_n_4 ;
wire \plusOp_inferred__0/i__carry__0_n_5 ;
wire \plusOp_inferred__0/i__carry__0_n_6 ;
wire \plusOp_inferred__0/i__carry__0_n_7 ;
wire \plusOp_inferred__0/i__carry__1_n_3 ;
wire \plusOp_inferred__0/i__carry__1_n_6 ;
wire \plusOp_inferred__0/i__carry__1_n_7 ;
wire \plusOp_inferred__0/i__carry_n_0 ;
wire \plusOp_inferred__0/i__carry_n_1 ;
wire \plusOp_inferred__0/i__carry_n_2 ;
wire \plusOp_inferred__0/i__carry_n_3 ;
wire \plusOp_inferred__0/i__carry_n_4 ;
wire \plusOp_inferred__0/i__carry_n_5 ;
wire \plusOp_inferred__0/i__carry_n_6 ;
wire \plusOp_inferred__0/i__carry_n_7 ;
wire rst;
wire top;
wire \top[15]_i_2_n_0 ;
wire top_left_0;
wire \top_left_0[0]_i_1_n_0 ;
wire \top_left_0[10]_i_1_n_0 ;
wire \top_left_0[11]_i_1_n_0 ;
wire \top_left_0[12]_i_1_n_0 ;
wire \top_left_0[13]_i_1_n_0 ;
wire \top_left_0[14]_i_1_n_0 ;
wire \top_left_0[15]_i_2_n_0 ;
wire \top_left_0[1]_i_1_n_0 ;
wire \top_left_0[2]_i_1_n_0 ;
wire \top_left_0[3]_i_1_n_0 ;
wire \top_left_0[4]_i_1_n_0 ;
wire \top_left_0[5]_i_1_n_0 ;
wire \top_left_0[6]_i_1_n_0 ;
wire \top_left_0[7]_i_1_n_0 ;
wire \top_left_0[8]_i_1_n_0 ;
wire \top_left_0[9]_i_1_n_0 ;
wire \top_left_0_reg_n_0_[0] ;
wire \top_left_0_reg_n_0_[10] ;
wire \top_left_0_reg_n_0_[11] ;
wire \top_left_0_reg_n_0_[12] ;
wire \top_left_0_reg_n_0_[13] ;
wire \top_left_0_reg_n_0_[14] ;
wire \top_left_0_reg_n_0_[15] ;
wire \top_left_0_reg_n_0_[1] ;
wire \top_left_0_reg_n_0_[2] ;
wire \top_left_0_reg_n_0_[3] ;
wire \top_left_0_reg_n_0_[4] ;
wire \top_left_0_reg_n_0_[5] ;
wire \top_left_0_reg_n_0_[6] ;
wire \top_left_0_reg_n_0_[7] ;
wire \top_left_0_reg_n_0_[8] ;
wire \top_left_0_reg_n_0_[9] ;
wire [15:0]top_left_1;
wire \top_left_1[0]_i_1_n_0 ;
wire \top_left_1[10]_i_1_n_0 ;
wire \top_left_1[11]_i_1_n_0 ;
wire \top_left_1[12]_i_1_n_0 ;
wire \top_left_1[13]_i_1_n_0 ;
wire \top_left_1[14]_i_1_n_0 ;
wire \top_left_1[15]_i_2_n_0 ;
wire \top_left_1[1]_i_1_n_0 ;
wire \top_left_1[2]_i_1_n_0 ;
wire \top_left_1[3]_i_1_n_0 ;
wire \top_left_1[4]_i_1_n_0 ;
wire \top_left_1[5]_i_1_n_0 ;
wire \top_left_1[6]_i_1_n_0 ;
wire \top_left_1[7]_i_1_n_0 ;
wire \top_left_1[8]_i_1_n_0 ;
wire \top_left_1[9]_i_1_n_0 ;
wire \top_reg_n_0_[0] ;
wire \top_reg_n_0_[10] ;
wire \top_reg_n_0_[11] ;
wire \top_reg_n_0_[12] ;
wire \top_reg_n_0_[13] ;
wire \top_reg_n_0_[14] ;
wire \top_reg_n_0_[15] ;
wire \top_reg_n_0_[1] ;
wire \top_reg_n_0_[2] ;
wire \top_reg_n_0_[3] ;
wire \top_reg_n_0_[4] ;
wire \top_reg_n_0_[5] ;
wire \top_reg_n_0_[6] ;
wire \top_reg_n_0_[7] ;
wire \top_reg_n_0_[8] ;
wire \top_reg_n_0_[9] ;
wire top_right_0;
wire \top_right_0[0]_i_1_n_0 ;
wire \top_right_0[10]_i_1_n_0 ;
wire \top_right_0[11]_i_1_n_0 ;
wire \top_right_0[12]_i_1_n_0 ;
wire \top_right_0[13]_i_1_n_0 ;
wire \top_right_0[14]_i_1_n_0 ;
wire \top_right_0[15]_i_2_n_0 ;
wire \top_right_0[1]_i_1_n_0 ;
wire \top_right_0[2]_i_1_n_0 ;
wire \top_right_0[3]_i_1_n_0 ;
wire \top_right_0[4]_i_1_n_0 ;
wire \top_right_0[5]_i_1_n_0 ;
wire \top_right_0[6]_i_1_n_0 ;
wire \top_right_0[7]_i_1_n_0 ;
wire \top_right_0[8]_i_1_n_0 ;
wire \top_right_0[9]_i_1_n_0 ;
wire \top_right_0_reg_n_0_[0] ;
wire \top_right_0_reg_n_0_[10] ;
wire \top_right_0_reg_n_0_[11] ;
wire \top_right_0_reg_n_0_[12] ;
wire \top_right_0_reg_n_0_[13] ;
wire \top_right_0_reg_n_0_[14] ;
wire \top_right_0_reg_n_0_[15] ;
wire \top_right_0_reg_n_0_[1] ;
wire \top_right_0_reg_n_0_[2] ;
wire \top_right_0_reg_n_0_[3] ;
wire \top_right_0_reg_n_0_[4] ;
wire \top_right_0_reg_n_0_[5] ;
wire \top_right_0_reg_n_0_[6] ;
wire \top_right_0_reg_n_0_[7] ;
wire \top_right_0_reg_n_0_[8] ;
wire \top_right_0_reg_n_0_[9] ;
wire top_right_1;
wire \top_right_1[0]_i_1_n_0 ;
wire \top_right_1[10]_i_1_n_0 ;
wire \top_right_1[11]_i_1_n_0 ;
wire \top_right_1[12]_i_1_n_0 ;
wire \top_right_1[13]_i_1_n_0 ;
wire \top_right_1[14]_i_1_n_0 ;
wire \top_right_1[15]_i_1_n_0 ;
wire \top_right_1[15]_i_2_n_0 ;
wire \top_right_1[1]_i_1_n_0 ;
wire \top_right_1[2]_i_1_n_0 ;
wire \top_right_1[3]_i_1_n_0 ;
wire \top_right_1[4]_i_1_n_0 ;
wire \top_right_1[5]_i_1_n_0 ;
wire \top_right_1[6]_i_1_n_0 ;
wire \top_right_1[7]_i_1_n_0 ;
wire \top_right_1[8]_i_1_n_0 ;
wire \top_right_1[9]_i_1_n_0 ;
wire \top_right_1_reg_n_0_[0] ;
wire \top_right_1_reg_n_0_[10] ;
wire \top_right_1_reg_n_0_[11] ;
wire \top_right_1_reg_n_0_[12] ;
wire \top_right_1_reg_n_0_[13] ;
wire \top_right_1_reg_n_0_[14] ;
wire \top_right_1_reg_n_0_[15] ;
wire \top_right_1_reg_n_0_[1] ;
wire \top_right_1_reg_n_0_[2] ;
wire \top_right_1_reg_n_0_[3] ;
wire \top_right_1_reg_n_0_[4] ;
wire \top_right_1_reg_n_0_[5] ;
wire \top_right_1_reg_n_0_[6] ;
wire \top_right_1_reg_n_0_[7] ;
wire \top_right_1_reg_n_0_[8] ;
wire \top_right_1_reg_n_0_[9] ;
wire \value_reg_n_0_[0] ;
wire \value_reg_n_0_[1] ;
wire \value_reg_n_0_[2] ;
wire \value_reg_n_0_[3] ;
wire \value_reg_n_0_[4] ;
wire \value_reg_n_0_[5] ;
wire \value_reg_n_0_[6] ;
wire \value_reg_n_0_[7] ;
wire wen_i_1_n_0;
wire wen_i_2_n_0;
wire wen_reg_n_0;
wire x;
wire \x0[0]_i_2_n_0 ;
wire \x0[0]_i_3_n_0 ;
wire \x0[1]_i_2_n_0 ;
wire \x0[1]_i_3_n_0 ;
wire \x0[1]_i_4_n_0 ;
wire \x0[2]_i_1_n_0 ;
wire \x0[2]_i_2_n_0 ;
wire \x0[2]_i_3_n_0 ;
wire \x0[2]_i_4_n_0 ;
wire \x0[2]_i_5_n_0 ;
wire \x0[3]_i_1_n_0 ;
wire \x0[3]_i_2_n_0 ;
wire \x0[3]_i_3_n_0 ;
wire \x0[3]_i_4_n_0 ;
wire \x0[3]_i_5_n_0 ;
wire \x0[3]_i_6_n_0 ;
wire \x0[4]_i_1_n_0 ;
wire \x0[4]_i_2_n_0 ;
wire \x0[4]_i_3_n_0 ;
wire \x0[4]_i_4_n_0 ;
wire \x0[4]_i_5_n_0 ;
wire \x0[5]_i_1_n_0 ;
wire \x0[5]_i_2_n_0 ;
wire \x0[5]_i_3_n_0 ;
wire \x0[5]_i_4_n_0 ;
wire \x0[5]_i_5_n_0 ;
wire \x0[6]_i_1_n_0 ;
wire \x0[6]_i_2_n_0 ;
wire \x0[6]_i_3_n_0 ;
wire \x0[6]_i_4_n_0 ;
wire \x0[6]_i_5_n_0 ;
wire \x0[7]_i_1_n_0 ;
wire \x0[7]_i_2_n_0 ;
wire \x0[7]_i_3_n_0 ;
wire \x0[7]_i_4_n_0 ;
wire \x0[7]_i_5_n_0 ;
wire \x0[7]_i_6_n_0 ;
wire \x0[7]_i_7_n_0 ;
wire \x0[8]_i_1_n_0 ;
wire \x0[8]_i_2_n_0 ;
wire \x0[8]_i_3_n_0 ;
wire \x0[8]_i_4_n_0 ;
wire \x0[8]_i_5_n_0 ;
wire \x0[8]_i_6_n_0 ;
wire \x0[8]_i_7_n_0 ;
wire \x0[9]_i_1_n_0 ;
wire \x0[9]_i_2_n_0 ;
wire \x0[9]_i_3_n_0 ;
wire \x0[9]_i_4_n_0 ;
wire \x0[9]_i_5_n_0 ;
wire \x0[9]_i_6_n_0 ;
wire \x0[9]_i_7_n_0 ;
wire \x0_reg[0]_i_1_n_0 ;
wire \x0_reg[1]_i_1_n_0 ;
wire x1;
wire \x1[0]_i_1_n_0 ;
wire \x1[1]_i_1_n_0 ;
wire \x1[2]_i_1_n_0 ;
wire \x1[2]_i_2_n_0 ;
wire \x1[2]_i_3_n_0 ;
wire \x1[3]_i_1_n_0 ;
wire \x1[3]_i_2_n_0 ;
wire \x1[3]_i_3_n_0 ;
wire \x1[3]_i_4_n_0 ;
wire \x1[4]_i_1_n_0 ;
wire \x1[4]_i_2_n_0 ;
wire \x1[4]_i_3_n_0 ;
wire \x1[4]_i_4_n_0 ;
wire \x1[4]_i_5_n_0 ;
wire \x1[5]_i_1_n_0 ;
wire \x1[5]_i_2_n_0 ;
wire \x1[5]_i_3_n_0 ;
wire \x1[5]_i_4_n_0 ;
wire \x1[5]_i_5_n_0 ;
wire \x1[6]_i_1_n_0 ;
wire \x1[6]_i_2_n_0 ;
wire \x1[6]_i_3_n_0 ;
wire \x1[6]_i_4_n_0 ;
wire \x1[6]_i_5_n_0 ;
wire \x1[6]_i_6_n_0 ;
wire \x1[6]_i_7_n_0 ;
wire \x1[6]_i_8_n_0 ;
wire \x1[7]_i_1_n_0 ;
wire \x1[7]_i_2_n_0 ;
wire \x1[7]_i_3_n_0 ;
wire \x1[7]_i_4_n_0 ;
wire \x1[7]_i_5_n_0 ;
wire \x1[8]_i_1_n_0 ;
wire \x1[8]_i_2_n_0 ;
wire \x1[8]_i_3_n_0 ;
wire \x1[8]_i_4_n_0 ;
wire \x1[8]_i_5_n_0 ;
wire \x1[8]_i_6_n_0 ;
wire \x1[9]_i_2_n_0 ;
wire \x1[9]_i_3_n_0 ;
wire \x1[9]_i_4_n_0 ;
wire \x1[9]_i_5_n_0 ;
wire \x1[9]_i_6_n_0 ;
wire \x1[9]_i_7_n_0 ;
wire \x1[9]_i_8_n_0 ;
wire [9:0]x_addr;
wire \x_reg_n_0_[0] ;
wire \x_reg_n_0_[1] ;
wire \x_reg_n_0_[2] ;
wire \x_reg_n_0_[3] ;
wire \x_reg_n_0_[4] ;
wire \x_reg_n_0_[5] ;
wire \x_reg_n_0_[6] ;
wire \x_reg_n_0_[7] ;
wire \x_reg_n_0_[8] ;
wire \x_reg_n_0_[9] ;
wire y1;
wire \y1[2]_i_1_n_0 ;
wire \y1[3]_i_1_n_0 ;
wire \y1_reg_n_0_[0] ;
wire \y1_reg_n_0_[1] ;
wire \y1_reg_n_0_[2] ;
wire \y1_reg_n_0_[3] ;
wire y2;
wire \y2[1]_i_1_n_0 ;
wire \y2[2]_i_1_n_0 ;
wire \y2[3]_i_1_n_0 ;
wire \y2_reg_n_0_[0] ;
wire \y2_reg_n_0_[1] ;
wire \y2_reg_n_0_[2] ;
wire \y2_reg_n_0_[3] ;
wire y3;
wire \y3[1]_i_1_n_0 ;
wire \y3[2]_i_1_n_0 ;
wire \y3[3]_i_1_n_0 ;
wire \y3_reg_n_0_[0] ;
wire \y3_reg_n_0_[1] ;
wire \y3_reg_n_0_[2] ;
wire \y3_reg_n_0_[3] ;
wire \y4[2]_i_1_n_0 ;
wire \y4[3]_i_1_n_0 ;
wire y5;
wire \y5[0]_i_1_n_0 ;
wire \y5[1]_i_1_n_0 ;
wire \y5[2]_i_1_n_0 ;
wire \y5[3]_i_1_n_0 ;
wire y6;
wire \y6[2]_i_1_n_0 ;
wire \y6[3]_i_1_n_0 ;
wire \y6_reg_n_0_[0] ;
wire \y6_reg_n_0_[1] ;
wire \y6_reg_n_0_[2] ;
wire \y6_reg_n_0_[3] ;
wire [3:0]y7;
wire \y7[2]_i_1_n_0 ;
wire \y7[3]_i_1_n_0 ;
wire [3:0]y8;
wire \y8[3]_i_1_n_0 ;
wire y9;
wire \y9[3]_i_1_n_0 ;
wire \y_actual_reg_n_0_[0] ;
wire \y_actual_reg_n_0_[1] ;
wire \y_actual_reg_n_0_[2] ;
wire \y_actual_reg_n_0_[3] ;
wire \y_actual_reg_n_0_[4] ;
wire \y_actual_reg_n_0_[5] ;
wire \y_actual_reg_n_0_[6] ;
wire \y_actual_reg_n_0_[7] ;
wire \y_actual_reg_n_0_[8] ;
wire \y_actual_reg_n_0_[9] ;
wire [9:0]y_addr;
wire [3:3]NLW_Lxx0_carry__2_CO_UNCONNECTED;
wire [3:3]NLW_Lxx_00__1_carry__2_CO_UNCONNECTED;
wire [3:3]NLW_Lxx_11__1_carry__2_CO_UNCONNECTED;
wire [3:3]NLW_Lxy0__1_carry__2_CO_UNCONNECTED;
wire [3:3]NLW_Lyy0_carry__2_CO_UNCONNECTED;
wire [3:3]NLW_Lyy_20__1_carry__2_CO_UNCONNECTED;
wire [3:3]NLW_Lyy_2_bottom_right0__0_carry__2_CO_UNCONNECTED;
wire NLW_det_0_reg_CARRYCASCOUT_UNCONNECTED;
wire NLW_det_0_reg_MULTSIGNOUT_UNCONNECTED;
wire NLW_det_0_reg_OVERFLOW_UNCONNECTED;
wire NLW_det_0_reg_PATTERNBDETECT_UNCONNECTED;
wire NLW_det_0_reg_PATTERNDETECT_UNCONNECTED;
wire NLW_det_0_reg_UNDERFLOW_UNCONNECTED;
wire [29:0]NLW_det_0_reg_ACOUT_UNCONNECTED;
wire [17:0]NLW_det_0_reg_BCOUT_UNCONNECTED;
wire [3:0]NLW_det_0_reg_CARRYOUT_UNCONNECTED;
wire [47:0]NLW_det_0_reg_P_UNCONNECTED;
wire [3:2]\NLW_det_abs_reg[31]_i_2_CO_UNCONNECTED ;
wire [3:3]\NLW_det_abs_reg[31]_i_2_O_UNCONNECTED ;
wire NLW_det_reg_CARRYCASCOUT_UNCONNECTED;
wire NLW_det_reg_MULTSIGNOUT_UNCONNECTED;
wire NLW_det_reg_OVERFLOW_UNCONNECTED;
wire NLW_det_reg_PATTERNBDETECT_UNCONNECTED;
wire NLW_det_reg_PATTERNDETECT_UNCONNECTED;
wire NLW_det_reg_UNDERFLOW_UNCONNECTED;
wire [29:0]NLW_det_reg_ACOUT_UNCONNECTED;
wire [17:0]NLW_det_reg_BCOUT_UNCONNECTED;
wire [3:0]NLW_det_reg_CARRYOUT_UNCONNECTED;
wire [47:32]NLW_det_reg_P_UNCONNECTED;
wire [47:0]NLW_det_reg_PCOUT_UNCONNECTED;
wire [3:1]\NLW_plusOp_inferred__0/i__carry__1_CO_UNCONNECTED ;
wire [3:2]\NLW_plusOp_inferred__0/i__carry__1_O_UNCONNECTED ;
CARRY4 Lxx0_carry
(.CI(1'b0),
.CO({Lxx0_carry_n_0,Lxx0_carry_n_1,Lxx0_carry_n_2,Lxx0_carry_n_3}),
.CYINIT(1'b0),
.DI({Lxx0_carry_i_1_n_0,Lxx0_carry_i_2_n_0,1'b1,\Lxx_2_reg_n_0_[0] }),
.O(A[3:0]),
.S({Lxx0_carry_i_3_n_0,Lxx0_carry_i_4_n_0,Lxx0_carry_i_5_n_0,Lxx0_carry_i_6_n_0}));
CARRY4 Lxx0_carry__0
(.CI(Lxx0_carry_n_0),
.CO({Lxx0_carry__0_n_0,Lxx0_carry__0_n_1,Lxx0_carry__0_n_2,Lxx0_carry__0_n_3}),
.CYINIT(1'b0),
.DI({Lxx0_carry__0_i_1_n_0,Lxx0_carry__0_i_2_n_0,Lxx0_carry__0_i_3_n_0,Lxx0_carry__0_i_4_n_0}),
.O(A[7:4]),
.S({Lxx0_carry__0_i_5_n_0,Lxx0_carry__0_i_6_n_0,Lxx0_carry__0_i_7_n_0,Lxx0_carry__0_i_8_n_0}));
(* HLUTNM = "lutpair4" *)
LUT3 #(
.INIT(8'hD4))
Lxx0_carry__0_i_1
(.I0(Lxx_1[6]),
.I1(\Lxx_2_reg_n_0_[6] ),
.I2(Lxx_0[6]),
.O(Lxx0_carry__0_i_1_n_0));
(* HLUTNM = "lutpair3" *)
LUT3 #(
.INIT(8'hD4))
Lxx0_carry__0_i_2
(.I0(Lxx_1[5]),
.I1(\Lxx_2_reg_n_0_[5] ),
.I2(Lxx_0[5]),
.O(Lxx0_carry__0_i_2_n_0));
(* HLUTNM = "lutpair2" *)
LUT3 #(
.INIT(8'hD4))
Lxx0_carry__0_i_3
(.I0(Lxx_1[4]),
.I1(\Lxx_2_reg_n_0_[4] ),
.I2(Lxx_0[4]),
.O(Lxx0_carry__0_i_3_n_0));
(* HLUTNM = "lutpair1" *)
LUT3 #(
.INIT(8'hD4))
Lxx0_carry__0_i_4
(.I0(Lxx_1[3]),
.I1(\Lxx_2_reg_n_0_[3] ),
.I2(Lxx_0[3]),
.O(Lxx0_carry__0_i_4_n_0));
(* HLUTNM = "lutpair5" *)
LUT4 #(
.INIT(16'h9669))
Lxx0_carry__0_i_5
(.I0(Lxx_1[7]),
.I1(\Lxx_2_reg_n_0_[7] ),
.I2(Lxx_0[7]),
.I3(Lxx0_carry__0_i_1_n_0),
.O(Lxx0_carry__0_i_5_n_0));
(* HLUTNM = "lutpair4" *)
LUT4 #(
.INIT(16'h9669))
Lxx0_carry__0_i_6
(.I0(Lxx_1[6]),
.I1(\Lxx_2_reg_n_0_[6] ),
.I2(Lxx_0[6]),
.I3(Lxx0_carry__0_i_2_n_0),
.O(Lxx0_carry__0_i_6_n_0));
(* HLUTNM = "lutpair3" *)
LUT4 #(
.INIT(16'h9669))
Lxx0_carry__0_i_7
(.I0(Lxx_1[5]),
.I1(\Lxx_2_reg_n_0_[5] ),
.I2(Lxx_0[5]),
.I3(Lxx0_carry__0_i_3_n_0),
.O(Lxx0_carry__0_i_7_n_0));
(* HLUTNM = "lutpair2" *)
LUT4 #(
.INIT(16'h9669))
Lxx0_carry__0_i_8
(.I0(Lxx_1[4]),
.I1(\Lxx_2_reg_n_0_[4] ),
.I2(Lxx_0[4]),
.I3(Lxx0_carry__0_i_4_n_0),
.O(Lxx0_carry__0_i_8_n_0));
CARRY4 Lxx0_carry__1
(.CI(Lxx0_carry__0_n_0),
.CO({Lxx0_carry__1_n_0,Lxx0_carry__1_n_1,Lxx0_carry__1_n_2,Lxx0_carry__1_n_3}),
.CYINIT(1'b0),
.DI({Lxx0_carry__1_i_1_n_0,Lxx0_carry__1_i_2_n_0,Lxx0_carry__1_i_3_n_0,Lxx0_carry__1_i_4_n_0}),
.O(A[11:8]),
.S({Lxx0_carry__1_i_5_n_0,Lxx0_carry__1_i_6_n_0,Lxx0_carry__1_i_7_n_0,Lxx0_carry__1_i_8_n_0}));
(* HLUTNM = "lutpair8" *)
LUT3 #(
.INIT(8'hD4))
Lxx0_carry__1_i_1
(.I0(Lxx_1[10]),
.I1(\Lxx_2_reg_n_0_[10] ),
.I2(Lxx_0[10]),
.O(Lxx0_carry__1_i_1_n_0));
(* HLUTNM = "lutpair7" *)
LUT3 #(
.INIT(8'hD4))
Lxx0_carry__1_i_2
(.I0(Lxx_1[9]),
.I1(\Lxx_2_reg_n_0_[9] ),
.I2(Lxx_0[9]),
.O(Lxx0_carry__1_i_2_n_0));
(* HLUTNM = "lutpair6" *)
LUT3 #(
.INIT(8'hD4))
Lxx0_carry__1_i_3
(.I0(Lxx_1[8]),
.I1(\Lxx_2_reg_n_0_[8] ),
.I2(Lxx_0[8]),
.O(Lxx0_carry__1_i_3_n_0));
(* HLUTNM = "lutpair5" *)
LUT3 #(
.INIT(8'hD4))
Lxx0_carry__1_i_4
(.I0(Lxx_1[7]),
.I1(\Lxx_2_reg_n_0_[7] ),
.I2(Lxx_0[7]),
.O(Lxx0_carry__1_i_4_n_0));
(* HLUTNM = "lutpair9" *)
LUT4 #(
.INIT(16'h9669))
Lxx0_carry__1_i_5
(.I0(Lxx_1[11]),
.I1(\Lxx_2_reg_n_0_[11] ),
.I2(Lxx_0[11]),
.I3(Lxx0_carry__1_i_1_n_0),
.O(Lxx0_carry__1_i_5_n_0));
(* HLUTNM = "lutpair8" *)
LUT4 #(
.INIT(16'h9669))
Lxx0_carry__1_i_6
(.I0(Lxx_1[10]),
.I1(\Lxx_2_reg_n_0_[10] ),
.I2(Lxx_0[10]),
.I3(Lxx0_carry__1_i_2_n_0),
.O(Lxx0_carry__1_i_6_n_0));
(* HLUTNM = "lutpair7" *)
LUT4 #(
.INIT(16'h9669))
Lxx0_carry__1_i_7
(.I0(Lxx_1[9]),
.I1(\Lxx_2_reg_n_0_[9] ),
.I2(Lxx_0[9]),
.I3(Lxx0_carry__1_i_3_n_0),
.O(Lxx0_carry__1_i_7_n_0));
(* HLUTNM = "lutpair6" *)
LUT4 #(
.INIT(16'h9669))
Lxx0_carry__1_i_8
(.I0(Lxx_1[8]),
.I1(\Lxx_2_reg_n_0_[8] ),
.I2(Lxx_0[8]),
.I3(Lxx0_carry__1_i_4_n_0),
.O(Lxx0_carry__1_i_8_n_0));
CARRY4 Lxx0_carry__2
(.CI(Lxx0_carry__1_n_0),
.CO({NLW_Lxx0_carry__2_CO_UNCONNECTED[3],Lxx0_carry__2_n_1,Lxx0_carry__2_n_2,Lxx0_carry__2_n_3}),
.CYINIT(1'b0),
.DI({1'b0,Lxx0_carry__2_i_1_n_0,Lxx0_carry__2_i_2_n_0,Lxx0_carry__2_i_3_n_0}),
.O(A[15:12]),
.S({Lxx0_carry__2_i_4_n_0,Lxx0_carry__2_i_5_n_0,Lxx0_carry__2_i_6_n_0,Lxx0_carry__2_i_7_n_0}));
(* HLUTNM = "lutpair11" *)
LUT3 #(
.INIT(8'hD4))
Lxx0_carry__2_i_1
(.I0(Lxx_1[13]),
.I1(\Lxx_2_reg_n_0_[13] ),
.I2(Lxx_0[13]),
.O(Lxx0_carry__2_i_1_n_0));
(* HLUTNM = "lutpair10" *)
LUT3 #(
.INIT(8'hD4))
Lxx0_carry__2_i_2
(.I0(Lxx_1[12]),
.I1(\Lxx_2_reg_n_0_[12] ),
.I2(Lxx_0[12]),
.O(Lxx0_carry__2_i_2_n_0));
(* HLUTNM = "lutpair9" *)
LUT3 #(
.INIT(8'hD4))
Lxx0_carry__2_i_3
(.I0(Lxx_1[11]),
.I1(\Lxx_2_reg_n_0_[11] ),
.I2(Lxx_0[11]),
.O(Lxx0_carry__2_i_3_n_0));
LUT6 #(
.INIT(64'h8E71718E718E8E71))
Lxx0_carry__2_i_4
(.I0(Lxx_0[14]),
.I1(\Lxx_2_reg_n_0_[14] ),
.I2(Lxx_1[14]),
.I3(\Lxx_2_reg_n_0_[15] ),
.I4(Lxx_1[15]),
.I5(Lxx_0[15]),
.O(Lxx0_carry__2_i_4_n_0));
LUT4 #(
.INIT(16'h9669))
Lxx0_carry__2_i_5
(.I0(Lxx0_carry__2_i_1_n_0),
.I1(\Lxx_2_reg_n_0_[14] ),
.I2(Lxx_1[14]),
.I3(Lxx_0[14]),
.O(Lxx0_carry__2_i_5_n_0));
(* HLUTNM = "lutpair11" *)
LUT4 #(
.INIT(16'h9669))
Lxx0_carry__2_i_6
(.I0(Lxx_1[13]),
.I1(\Lxx_2_reg_n_0_[13] ),
.I2(Lxx_0[13]),
.I3(Lxx0_carry__2_i_2_n_0),
.O(Lxx0_carry__2_i_6_n_0));
(* HLUTNM = "lutpair10" *)
LUT4 #(
.INIT(16'h9669))
Lxx0_carry__2_i_7
(.I0(Lxx_1[12]),
.I1(\Lxx_2_reg_n_0_[12] ),
.I2(Lxx_0[12]),
.I3(Lxx0_carry__2_i_3_n_0),
.O(Lxx0_carry__2_i_7_n_0));
(* HLUTNM = "lutpair0" *)
LUT3 #(
.INIT(8'hD4))
Lxx0_carry_i_1
(.I0(Lxx_1[2]),
.I1(\Lxx_2_reg_n_0_[2] ),
.I2(Lxx_0[2]),
.O(Lxx0_carry_i_1_n_0));
(* HLUTNM = "lutpair24" *)
LUT3 #(
.INIT(8'hD4))
Lxx0_carry_i_2
(.I0(Lxx_1[1]),
.I1(\Lxx_2_reg_n_0_[1] ),
.I2(Lxx_0[1]),
.O(Lxx0_carry_i_2_n_0));
(* HLUTNM = "lutpair1" *)
LUT4 #(
.INIT(16'h9669))
Lxx0_carry_i_3
(.I0(Lxx_1[3]),
.I1(\Lxx_2_reg_n_0_[3] ),
.I2(Lxx_0[3]),
.I3(Lxx0_carry_i_1_n_0),
.O(Lxx0_carry_i_3_n_0));
(* HLUTNM = "lutpair0" *)
LUT4 #(
.INIT(16'h9669))
Lxx0_carry_i_4
(.I0(Lxx_1[2]),
.I1(\Lxx_2_reg_n_0_[2] ),
.I2(Lxx_0[2]),
.I3(Lxx0_carry_i_2_n_0),
.O(Lxx0_carry_i_4_n_0));
(* HLUTNM = "lutpair24" *)
LUT3 #(
.INIT(8'h96))
Lxx0_carry_i_5
(.I0(Lxx_1[1]),
.I1(\Lxx_2_reg_n_0_[1] ),
.I2(Lxx_0[1]),
.O(Lxx0_carry_i_5_n_0));
LUT2 #(
.INIT(4'h6))
Lxx0_carry_i_6
(.I0(\Lxx_2_reg_n_0_[0] ),
.I1(Lxx_0[0]),
.O(Lxx0_carry_i_6_n_0));
CARRY4 Lxx_00__1_carry
(.CI(1'b0),
.CO({Lxx_00__1_carry_n_0,Lxx_00__1_carry_n_1,Lxx_00__1_carry_n_2,Lxx_00__1_carry_n_3}),
.CYINIT(1'b0),
.DI({Lxx_00__1_carry_i_1_n_0,Lxx_00__1_carry_i_2_n_0,Lxx_00__1_carry_i_3_n_0,\bottom_right_0_reg_n_0_[0] }),
.O(Lxx_00[3:0]),
.S({Lxx_00__1_carry_i_4_n_0,Lxx_00__1_carry_i_5_n_0,Lxx_00__1_carry_i_6_n_0,Lxx_00__1_carry_i_7_n_0}));
CARRY4 Lxx_00__1_carry__0
(.CI(Lxx_00__1_carry_n_0),
.CO({Lxx_00__1_carry__0_n_0,Lxx_00__1_carry__0_n_1,Lxx_00__1_carry__0_n_2,Lxx_00__1_carry__0_n_3}),
.CYINIT(1'b0),
.DI({Lxx_00__1_carry__0_i_1_n_0,Lxx_00__1_carry__0_i_2_n_0,Lxx_00__1_carry__0_i_3_n_0,Lxx_00__1_carry__0_i_4_n_0}),
.O(Lxx_00[7:4]),
.S({Lxx_00__1_carry__0_i_5_n_0,Lxx_00__1_carry__0_i_6_n_0,Lxx_00__1_carry__0_i_7_n_0,Lxx_00__1_carry__0_i_8_n_0}));
LUT5 #(
.INIT(32'h88E8E8EE))
Lxx_00__1_carry__0_i_1
(.I0(\bottom_right_0_reg_n_0_[6] ),
.I1(Lxx_00__1_carry__0_i_9_n_0),
.I2(\top_left_0_reg_n_0_[5] ),
.I3(\top_right_0_reg_n_0_[5] ),
.I4(\bottom_left_0_reg_n_0_[5] ),
.O(Lxx_00__1_carry__0_i_1_n_0));
LUT3 #(
.INIT(8'h96))
Lxx_00__1_carry__0_i_10
(.I0(\bottom_left_0_reg_n_0_[5] ),
.I1(\top_right_0_reg_n_0_[5] ),
.I2(\top_left_0_reg_n_0_[5] ),
.O(Lxx_00__1_carry__0_i_10_n_0));
LUT3 #(
.INIT(8'h96))
Lxx_00__1_carry__0_i_11
(.I0(\bottom_left_0_reg_n_0_[4] ),
.I1(\top_right_0_reg_n_0_[4] ),
.I2(\top_left_0_reg_n_0_[4] ),
.O(Lxx_00__1_carry__0_i_11_n_0));
LUT3 #(
.INIT(8'h96))
Lxx_00__1_carry__0_i_12
(.I0(\bottom_left_0_reg_n_0_[7] ),
.I1(\top_right_0_reg_n_0_[7] ),
.I2(\top_left_0_reg_n_0_[7] ),
.O(Lxx_00__1_carry__0_i_12_n_0));
LUT5 #(
.INIT(32'h88E8E8EE))
Lxx_00__1_carry__0_i_2
(.I0(\bottom_right_0_reg_n_0_[5] ),
.I1(Lxx_00__1_carry__0_i_10_n_0),
.I2(\top_left_0_reg_n_0_[4] ),
.I3(\top_right_0_reg_n_0_[4] ),
.I4(\bottom_left_0_reg_n_0_[4] ),
.O(Lxx_00__1_carry__0_i_2_n_0));
LUT5 #(
.INIT(32'h88E8E8EE))
Lxx_00__1_carry__0_i_3
(.I0(\bottom_right_0_reg_n_0_[4] ),
.I1(Lxx_00__1_carry__0_i_11_n_0),
.I2(\top_left_0_reg_n_0_[3] ),
.I3(\top_right_0_reg_n_0_[3] ),
.I4(\bottom_left_0_reg_n_0_[3] ),
.O(Lxx_00__1_carry__0_i_3_n_0));
LUT5 #(
.INIT(32'h88E8E8EE))
Lxx_00__1_carry__0_i_4
(.I0(\bottom_right_0_reg_n_0_[3] ),
.I1(Lxx_00__1_carry_i_8_n_0),
.I2(\top_left_0_reg_n_0_[2] ),
.I3(\top_right_0_reg_n_0_[2] ),
.I4(\bottom_left_0_reg_n_0_[2] ),
.O(Lxx_00__1_carry__0_i_4_n_0));
LUT6 #(
.INIT(64'hA665599A599AA665))
Lxx_00__1_carry__0_i_5
(.I0(Lxx_00__1_carry__0_i_1_n_0),
.I1(\top_left_0_reg_n_0_[6] ),
.I2(\top_right_0_reg_n_0_[6] ),
.I3(\bottom_left_0_reg_n_0_[6] ),
.I4(\bottom_right_0_reg_n_0_[7] ),
.I5(Lxx_00__1_carry__0_i_12_n_0),
.O(Lxx_00__1_carry__0_i_5_n_0));
LUT6 #(
.INIT(64'hA665599A599AA665))
Lxx_00__1_carry__0_i_6
(.I0(Lxx_00__1_carry__0_i_2_n_0),
.I1(\top_left_0_reg_n_0_[5] ),
.I2(\top_right_0_reg_n_0_[5] ),
.I3(\bottom_left_0_reg_n_0_[5] ),
.I4(\bottom_right_0_reg_n_0_[6] ),
.I5(Lxx_00__1_carry__0_i_9_n_0),
.O(Lxx_00__1_carry__0_i_6_n_0));
LUT6 #(
.INIT(64'hA665599A599AA665))
Lxx_00__1_carry__0_i_7
(.I0(Lxx_00__1_carry__0_i_3_n_0),
.I1(\top_left_0_reg_n_0_[4] ),
.I2(\top_right_0_reg_n_0_[4] ),
.I3(\bottom_left_0_reg_n_0_[4] ),
.I4(\bottom_right_0_reg_n_0_[5] ),
.I5(Lxx_00__1_carry__0_i_10_n_0),
.O(Lxx_00__1_carry__0_i_7_n_0));
LUT6 #(
.INIT(64'hA665599A599AA665))
Lxx_00__1_carry__0_i_8
(.I0(Lxx_00__1_carry__0_i_4_n_0),
.I1(\top_left_0_reg_n_0_[3] ),
.I2(\top_right_0_reg_n_0_[3] ),
.I3(\bottom_left_0_reg_n_0_[3] ),
.I4(\bottom_right_0_reg_n_0_[4] ),
.I5(Lxx_00__1_carry__0_i_11_n_0),
.O(Lxx_00__1_carry__0_i_8_n_0));
LUT3 #(
.INIT(8'h96))
Lxx_00__1_carry__0_i_9
(.I0(\bottom_left_0_reg_n_0_[6] ),
.I1(\top_right_0_reg_n_0_[6] ),
.I2(\top_left_0_reg_n_0_[6] ),
.O(Lxx_00__1_carry__0_i_9_n_0));
CARRY4 Lxx_00__1_carry__1
(.CI(Lxx_00__1_carry__0_n_0),
.CO({Lxx_00__1_carry__1_n_0,Lxx_00__1_carry__1_n_1,Lxx_00__1_carry__1_n_2,Lxx_00__1_carry__1_n_3}),
.CYINIT(1'b0),
.DI({Lxx_00__1_carry__1_i_1_n_0,Lxx_00__1_carry__1_i_2_n_0,Lxx_00__1_carry__1_i_3_n_0,Lxx_00__1_carry__1_i_4_n_0}),
.O(Lxx_00[11:8]),
.S({Lxx_00__1_carry__1_i_5_n_0,Lxx_00__1_carry__1_i_6_n_0,Lxx_00__1_carry__1_i_7_n_0,Lxx_00__1_carry__1_i_8_n_0}));
LUT5 #(
.INIT(32'h88E8E8EE))
Lxx_00__1_carry__1_i_1
(.I0(\bottom_right_0_reg_n_0_[10] ),
.I1(Lxx_00__1_carry__1_i_9_n_0),
.I2(\top_left_0_reg_n_0_[9] ),
.I3(\top_right_0_reg_n_0_[9] ),
.I4(\bottom_left_0_reg_n_0_[9] ),
.O(Lxx_00__1_carry__1_i_1_n_0));
LUT3 #(
.INIT(8'h96))
Lxx_00__1_carry__1_i_10
(.I0(\bottom_left_0_reg_n_0_[9] ),
.I1(\top_right_0_reg_n_0_[9] ),
.I2(\top_left_0_reg_n_0_[9] ),
.O(Lxx_00__1_carry__1_i_10_n_0));
LUT3 #(
.INIT(8'h96))
Lxx_00__1_carry__1_i_11
(.I0(\bottom_left_0_reg_n_0_[8] ),
.I1(\top_right_0_reg_n_0_[8] ),
.I2(\top_left_0_reg_n_0_[8] ),
.O(Lxx_00__1_carry__1_i_11_n_0));
LUT3 #(
.INIT(8'h96))
Lxx_00__1_carry__1_i_12
(.I0(\bottom_left_0_reg_n_0_[11] ),
.I1(\top_right_0_reg_n_0_[11] ),
.I2(\top_left_0_reg_n_0_[11] ),
.O(Lxx_00__1_carry__1_i_12_n_0));
LUT5 #(
.INIT(32'h88E8E8EE))
Lxx_00__1_carry__1_i_2
(.I0(\bottom_right_0_reg_n_0_[9] ),
.I1(Lxx_00__1_carry__1_i_10_n_0),
.I2(\top_left_0_reg_n_0_[8] ),
.I3(\top_right_0_reg_n_0_[8] ),
.I4(\bottom_left_0_reg_n_0_[8] ),
.O(Lxx_00__1_carry__1_i_2_n_0));
LUT5 #(
.INIT(32'h88E8E8EE))
Lxx_00__1_carry__1_i_3
(.I0(\bottom_right_0_reg_n_0_[8] ),
.I1(Lxx_00__1_carry__1_i_11_n_0),
.I2(\top_left_0_reg_n_0_[7] ),
.I3(\top_right_0_reg_n_0_[7] ),
.I4(\bottom_left_0_reg_n_0_[7] ),
.O(Lxx_00__1_carry__1_i_3_n_0));
LUT5 #(
.INIT(32'h88E8E8EE))
Lxx_00__1_carry__1_i_4
(.I0(\bottom_right_0_reg_n_0_[7] ),
.I1(Lxx_00__1_carry__0_i_12_n_0),
.I2(\top_left_0_reg_n_0_[6] ),
.I3(\top_right_0_reg_n_0_[6] ),
.I4(\bottom_left_0_reg_n_0_[6] ),
.O(Lxx_00__1_carry__1_i_4_n_0));
LUT6 #(
.INIT(64'hA665599A599AA665))
Lxx_00__1_carry__1_i_5
(.I0(Lxx_00__1_carry__1_i_1_n_0),
.I1(\top_left_0_reg_n_0_[10] ),
.I2(\top_right_0_reg_n_0_[10] ),
.I3(\bottom_left_0_reg_n_0_[10] ),
.I4(\bottom_right_0_reg_n_0_[11] ),
.I5(Lxx_00__1_carry__1_i_12_n_0),
.O(Lxx_00__1_carry__1_i_5_n_0));
LUT6 #(
.INIT(64'hA665599A599AA665))
Lxx_00__1_carry__1_i_6
(.I0(Lxx_00__1_carry__1_i_2_n_0),
.I1(\top_left_0_reg_n_0_[9] ),
.I2(\top_right_0_reg_n_0_[9] ),
.I3(\bottom_left_0_reg_n_0_[9] ),
.I4(\bottom_right_0_reg_n_0_[10] ),
.I5(Lxx_00__1_carry__1_i_9_n_0),
.O(Lxx_00__1_carry__1_i_6_n_0));
LUT6 #(
.INIT(64'hA665599A599AA665))
Lxx_00__1_carry__1_i_7
(.I0(Lxx_00__1_carry__1_i_3_n_0),
.I1(\top_left_0_reg_n_0_[8] ),
.I2(\top_right_0_reg_n_0_[8] ),
.I3(\bottom_left_0_reg_n_0_[8] ),
.I4(\bottom_right_0_reg_n_0_[9] ),
.I5(Lxx_00__1_carry__1_i_10_n_0),
.O(Lxx_00__1_carry__1_i_7_n_0));
LUT6 #(
.INIT(64'hA665599A599AA665))
Lxx_00__1_carry__1_i_8
(.I0(Lxx_00__1_carry__1_i_4_n_0),
.I1(\top_left_0_reg_n_0_[7] ),
.I2(\top_right_0_reg_n_0_[7] ),
.I3(\bottom_left_0_reg_n_0_[7] ),
.I4(\bottom_right_0_reg_n_0_[8] ),
.I5(Lxx_00__1_carry__1_i_11_n_0),
.O(Lxx_00__1_carry__1_i_8_n_0));
LUT3 #(
.INIT(8'h96))
Lxx_00__1_carry__1_i_9
(.I0(\bottom_left_0_reg_n_0_[10] ),
.I1(\top_right_0_reg_n_0_[10] ),
.I2(\top_left_0_reg_n_0_[10] ),
.O(Lxx_00__1_carry__1_i_9_n_0));
CARRY4 Lxx_00__1_carry__2
(.CI(Lxx_00__1_carry__1_n_0),
.CO({NLW_Lxx_00__1_carry__2_CO_UNCONNECTED[3],Lxx_00__1_carry__2_n_1,Lxx_00__1_carry__2_n_2,Lxx_00__1_carry__2_n_3}),
.CYINIT(1'b0),
.DI({1'b0,Lxx_00__1_carry__2_i_1_n_0,Lxx_00__1_carry__2_i_2_n_0,Lxx_00__1_carry__2_i_3_n_0}),
.O(Lxx_00[15:12]),
.S({Lxx_00__1_carry__2_i_4_n_0,Lxx_00__1_carry__2_i_5_n_0,Lxx_00__1_carry__2_i_6_n_0,Lxx_00__1_carry__2_i_7_n_0}));
LUT5 #(
.INIT(32'h88E8E8EE))
Lxx_00__1_carry__2_i_1
(.I0(\bottom_right_0_reg_n_0_[13] ),
.I1(Lxx_00__1_carry__2_i_8_n_0),
.I2(\top_left_0_reg_n_0_[12] ),
.I3(\top_right_0_reg_n_0_[12] ),
.I4(\bottom_left_0_reg_n_0_[12] ),
.O(Lxx_00__1_carry__2_i_1_n_0));
(* SOFT_HLUTNM = "soft_lutpair24" *)
LUT3 #(
.INIT(8'h2B))
Lxx_00__1_carry__2_i_10
(.I0(\top_left_0_reg_n_0_[13] ),
.I1(\top_right_0_reg_n_0_[13] ),
.I2(\bottom_left_0_reg_n_0_[13] ),
.O(Lxx_00__1_carry__2_i_10_n_0));
LUT4 #(
.INIT(16'h6996))
Lxx_00__1_carry__2_i_11
(.I0(\top_right_0_reg_n_0_[15] ),
.I1(\bottom_left_0_reg_n_0_[15] ),
.I2(\bottom_right_0_reg_n_0_[15] ),
.I3(\top_left_0_reg_n_0_[15] ),
.O(Lxx_00__1_carry__2_i_11_n_0));
LUT3 #(
.INIT(8'h96))
Lxx_00__1_carry__2_i_12
(.I0(\bottom_left_0_reg_n_0_[14] ),
.I1(\top_right_0_reg_n_0_[14] ),
.I2(\top_left_0_reg_n_0_[14] ),
.O(Lxx_00__1_carry__2_i_12_n_0));
LUT5 #(
.INIT(32'h88E8E8EE))
Lxx_00__1_carry__2_i_2
(.I0(\bottom_right_0_reg_n_0_[12] ),
.I1(Lxx_00__1_carry__2_i_9_n_0),
.I2(\top_left_0_reg_n_0_[11] ),
.I3(\top_right_0_reg_n_0_[11] ),
.I4(\bottom_left_0_reg_n_0_[11] ),
.O(Lxx_00__1_carry__2_i_2_n_0));
LUT5 #(
.INIT(32'h88E8E8EE))
Lxx_00__1_carry__2_i_3
(.I0(\bottom_right_0_reg_n_0_[11] ),
.I1(Lxx_00__1_carry__1_i_12_n_0),
.I2(\top_left_0_reg_n_0_[10] ),
.I3(\top_right_0_reg_n_0_[10] ),
.I4(\bottom_left_0_reg_n_0_[10] ),
.O(Lxx_00__1_carry__2_i_3_n_0));
LUT6 #(
.INIT(64'h178181E8E87E7E17))
Lxx_00__1_carry__2_i_4
(.I0(Lxx_00__1_carry__2_i_10_n_0),
.I1(\bottom_right_0_reg_n_0_[14] ),
.I2(\top_left_0_reg_n_0_[14] ),
.I3(\top_right_0_reg_n_0_[14] ),
.I4(\bottom_left_0_reg_n_0_[14] ),
.I5(Lxx_00__1_carry__2_i_11_n_0),
.O(Lxx_00__1_carry__2_i_4_n_0));
LUT6 #(
.INIT(64'hA665599A599AA665))
Lxx_00__1_carry__2_i_5
(.I0(Lxx_00__1_carry__2_i_1_n_0),
.I1(\top_left_0_reg_n_0_[13] ),
.I2(\top_right_0_reg_n_0_[13] ),
.I3(\bottom_left_0_reg_n_0_[13] ),
.I4(\bottom_right_0_reg_n_0_[14] ),
.I5(Lxx_00__1_carry__2_i_12_n_0),
.O(Lxx_00__1_carry__2_i_5_n_0));
LUT6 #(
.INIT(64'hA665599A599AA665))
Lxx_00__1_carry__2_i_6
(.I0(Lxx_00__1_carry__2_i_2_n_0),
.I1(\top_left_0_reg_n_0_[12] ),
.I2(\top_right_0_reg_n_0_[12] ),
.I3(\bottom_left_0_reg_n_0_[12] ),
.I4(\bottom_right_0_reg_n_0_[13] ),
.I5(Lxx_00__1_carry__2_i_8_n_0),
.O(Lxx_00__1_carry__2_i_6_n_0));
LUT6 #(
.INIT(64'hA665599A599AA665))
Lxx_00__1_carry__2_i_7
(.I0(Lxx_00__1_carry__2_i_3_n_0),
.I1(\top_left_0_reg_n_0_[11] ),
.I2(\top_right_0_reg_n_0_[11] ),
.I3(\bottom_left_0_reg_n_0_[11] ),
.I4(\bottom_right_0_reg_n_0_[12] ),
.I5(Lxx_00__1_carry__2_i_9_n_0),
.O(Lxx_00__1_carry__2_i_7_n_0));
(* SOFT_HLUTNM = "soft_lutpair24" *)
LUT3 #(
.INIT(8'h96))
Lxx_00__1_carry__2_i_8
(.I0(\bottom_left_0_reg_n_0_[13] ),
.I1(\top_right_0_reg_n_0_[13] ),
.I2(\top_left_0_reg_n_0_[13] ),
.O(Lxx_00__1_carry__2_i_8_n_0));
LUT3 #(
.INIT(8'h96))
Lxx_00__1_carry__2_i_9
(.I0(\bottom_left_0_reg_n_0_[12] ),
.I1(\top_right_0_reg_n_0_[12] ),
.I2(\top_left_0_reg_n_0_[12] ),
.O(Lxx_00__1_carry__2_i_9_n_0));
LUT6 #(
.INIT(64'h8228EBBEEBBEEBBE))
Lxx_00__1_carry_i_1
(.I0(\bottom_right_0_reg_n_0_[2] ),
.I1(\top_left_0_reg_n_0_[2] ),
.I2(\top_right_0_reg_n_0_[2] ),
.I3(\bottom_left_0_reg_n_0_[2] ),
.I4(\bottom_left_0_reg_n_0_[1] ),
.I5(\top_right_0_reg_n_0_[1] ),
.O(Lxx_00__1_carry_i_1_n_0));
LUT4 #(
.INIT(16'hF990))
Lxx_00__1_carry_i_2
(.I0(\bottom_left_0_reg_n_0_[1] ),
.I1(\top_right_0_reg_n_0_[1] ),
.I2(\top_left_0_reg_n_0_[1] ),
.I3(\bottom_right_0_reg_n_0_[1] ),
.O(Lxx_00__1_carry_i_2_n_0));
LUT4 #(
.INIT(16'h9669))
Lxx_00__1_carry_i_3
(.I0(\top_right_0_reg_n_0_[1] ),
.I1(\bottom_left_0_reg_n_0_[1] ),
.I2(\bottom_right_0_reg_n_0_[1] ),
.I3(\top_left_0_reg_n_0_[1] ),
.O(Lxx_00__1_carry_i_3_n_0));
LUT6 #(
.INIT(64'hA665599A599AA665))
Lxx_00__1_carry_i_4
(.I0(Lxx_00__1_carry_i_1_n_0),
.I1(\top_left_0_reg_n_0_[2] ),
.I2(\top_right_0_reg_n_0_[2] ),
.I3(\bottom_left_0_reg_n_0_[2] ),
.I4(\bottom_right_0_reg_n_0_[3] ),
.I5(Lxx_00__1_carry_i_8_n_0),
.O(Lxx_00__1_carry_i_4_n_0));
LUT5 #(
.INIT(32'h96696969))
Lxx_00__1_carry_i_5
(.I0(Lxx_00__1_carry_i_2_n_0),
.I1(\bottom_right_0_reg_n_0_[2] ),
.I2(Lxx_00__1_carry_i_9_n_0),
.I3(\bottom_left_0_reg_n_0_[1] ),
.I4(\top_right_0_reg_n_0_[1] ),
.O(Lxx_00__1_carry_i_5_n_0));
LUT4 #(
.INIT(16'hA665))
Lxx_00__1_carry_i_6
(.I0(Lxx_00__1_carry_i_3_n_0),
.I1(\top_left_0_reg_n_0_[0] ),
.I2(\top_right_0_reg_n_0_[0] ),
.I3(\bottom_left_0_reg_n_0_[0] ),
.O(Lxx_00__1_carry_i_6_n_0));
LUT4 #(
.INIT(16'h6996))
Lxx_00__1_carry_i_7
(.I0(\bottom_left_0_reg_n_0_[0] ),
.I1(\top_right_0_reg_n_0_[0] ),
.I2(\top_left_0_reg_n_0_[0] ),
.I3(\bottom_right_0_reg_n_0_[0] ),
.O(Lxx_00__1_carry_i_7_n_0));
LUT3 #(
.INIT(8'h96))
Lxx_00__1_carry_i_8
(.I0(\bottom_left_0_reg_n_0_[3] ),
.I1(\top_right_0_reg_n_0_[3] ),
.I2(\top_left_0_reg_n_0_[3] ),
.O(Lxx_00__1_carry_i_8_n_0));
LUT3 #(
.INIT(8'h96))
Lxx_00__1_carry_i_9
(.I0(\bottom_left_0_reg_n_0_[2] ),
.I1(\top_right_0_reg_n_0_[2] ),
.I2(\top_left_0_reg_n_0_[2] ),
.O(Lxx_00__1_carry_i_9_n_0));
FDRE #(
.INIT(1'b0))
\Lxx_0_reg[0]
(.C(clk_x16),
.CE(x),
.D(Lxx_00[0]),
.Q(Lxx_0[0]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lxx_0_reg[10]
(.C(clk_x16),
.CE(x),
.D(Lxx_00[10]),
.Q(Lxx_0[10]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lxx_0_reg[11]
(.C(clk_x16),
.CE(x),
.D(Lxx_00[11]),
.Q(Lxx_0[11]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lxx_0_reg[12]
(.C(clk_x16),
.CE(x),
.D(Lxx_00[12]),
.Q(Lxx_0[12]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lxx_0_reg[13]
(.C(clk_x16),
.CE(x),
.D(Lxx_00[13]),
.Q(Lxx_0[13]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lxx_0_reg[14]
(.C(clk_x16),
.CE(x),
.D(Lxx_00[14]),
.Q(Lxx_0[14]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lxx_0_reg[15]
(.C(clk_x16),
.CE(x),
.D(Lxx_00[15]),
.Q(Lxx_0[15]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lxx_0_reg[1]
(.C(clk_x16),
.CE(x),
.D(Lxx_00[1]),
.Q(Lxx_0[1]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lxx_0_reg[2]
(.C(clk_x16),
.CE(x),
.D(Lxx_00[2]),
.Q(Lxx_0[2]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lxx_0_reg[3]
(.C(clk_x16),
.CE(x),
.D(Lxx_00[3]),
.Q(Lxx_0[3]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lxx_0_reg[4]
(.C(clk_x16),
.CE(x),
.D(Lxx_00[4]),
.Q(Lxx_0[4]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lxx_0_reg[5]
(.C(clk_x16),
.CE(x),
.D(Lxx_00[5]),
.Q(Lxx_0[5]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lxx_0_reg[6]
(.C(clk_x16),
.CE(x),
.D(Lxx_00[6]),
.Q(Lxx_0[6]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lxx_0_reg[7]
(.C(clk_x16),
.CE(x),
.D(Lxx_00[7]),
.Q(Lxx_0[7]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lxx_0_reg[8]
(.C(clk_x16),
.CE(x),
.D(Lxx_00[8]),
.Q(Lxx_0[8]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lxx_0_reg[9]
(.C(clk_x16),
.CE(x),
.D(Lxx_00[9]),
.Q(Lxx_0[9]),
.R(1'b0));
CARRY4 Lxx_11__1_carry
(.CI(1'b0),
.CO({Lxx_11__1_carry_n_0,Lxx_11__1_carry_n_1,Lxx_11__1_carry_n_2,Lxx_11__1_carry_n_3}),
.CYINIT(1'b0),
.DI({Lxx_11__1_carry_i_1_n_0,Lxx_11__1_carry_i_2_n_0,Lxx_11__1_carry_i_3_n_0,\bottom_right_1_reg_n_0_[0] }),
.O(Lxx_11[3:0]),
.S({Lxx_11__1_carry_i_4_n_0,Lxx_11__1_carry_i_5_n_0,Lxx_11__1_carry_i_6_n_0,Lxx_11__1_carry_i_7_n_0}));
CARRY4 Lxx_11__1_carry__0
(.CI(Lxx_11__1_carry_n_0),
.CO({Lxx_11__1_carry__0_n_0,Lxx_11__1_carry__0_n_1,Lxx_11__1_carry__0_n_2,Lxx_11__1_carry__0_n_3}),
.CYINIT(1'b0),
.DI({Lxx_11__1_carry__0_i_1_n_0,Lxx_11__1_carry__0_i_2_n_0,Lxx_11__1_carry__0_i_3_n_0,Lxx_11__1_carry__0_i_4_n_0}),
.O(Lxx_11[7:4]),
.S({Lxx_11__1_carry__0_i_5_n_0,Lxx_11__1_carry__0_i_6_n_0,Lxx_11__1_carry__0_i_7_n_0,Lxx_11__1_carry__0_i_8_n_0}));
LUT5 #(
.INIT(32'h88E8E8EE))
Lxx_11__1_carry__0_i_1
(.I0(\bottom_right_1_reg_n_0_[6] ),
.I1(Lxx_11__1_carry__0_i_9_n_0),
.I2(top_left_1[5]),
.I3(\top_right_1_reg_n_0_[5] ),
.I4(bottom_left_1[5]),
.O(Lxx_11__1_carry__0_i_1_n_0));
LUT3 #(
.INIT(8'h96))
Lxx_11__1_carry__0_i_10
(.I0(bottom_left_1[5]),
.I1(\top_right_1_reg_n_0_[5] ),
.I2(top_left_1[5]),
.O(Lxx_11__1_carry__0_i_10_n_0));
LUT3 #(
.INIT(8'h96))
Lxx_11__1_carry__0_i_11
(.I0(bottom_left_1[4]),
.I1(\top_right_1_reg_n_0_[4] ),
.I2(top_left_1[4]),
.O(Lxx_11__1_carry__0_i_11_n_0));
LUT3 #(
.INIT(8'h96))
Lxx_11__1_carry__0_i_12
(.I0(bottom_left_1[7]),
.I1(\top_right_1_reg_n_0_[7] ),
.I2(top_left_1[7]),
.O(Lxx_11__1_carry__0_i_12_n_0));
LUT5 #(
.INIT(32'h88E8E8EE))
Lxx_11__1_carry__0_i_2
(.I0(\bottom_right_1_reg_n_0_[5] ),
.I1(Lxx_11__1_carry__0_i_10_n_0),
.I2(top_left_1[4]),
.I3(\top_right_1_reg_n_0_[4] ),
.I4(bottom_left_1[4]),
.O(Lxx_11__1_carry__0_i_2_n_0));
LUT5 #(
.INIT(32'h88E8E8EE))
Lxx_11__1_carry__0_i_3
(.I0(\bottom_right_1_reg_n_0_[4] ),
.I1(Lxx_11__1_carry__0_i_11_n_0),
.I2(top_left_1[3]),
.I3(\top_right_1_reg_n_0_[3] ),
.I4(bottom_left_1[3]),
.O(Lxx_11__1_carry__0_i_3_n_0));
LUT5 #(
.INIT(32'h88E8E8EE))
Lxx_11__1_carry__0_i_4
(.I0(\bottom_right_1_reg_n_0_[3] ),
.I1(Lxx_11__1_carry_i_8_n_0),
.I2(top_left_1[2]),
.I3(\top_right_1_reg_n_0_[2] ),
.I4(bottom_left_1[2]),
.O(Lxx_11__1_carry__0_i_4_n_0));
LUT6 #(
.INIT(64'hA665599A599AA665))
Lxx_11__1_carry__0_i_5
(.I0(Lxx_11__1_carry__0_i_1_n_0),
.I1(top_left_1[6]),
.I2(\top_right_1_reg_n_0_[6] ),
.I3(bottom_left_1[6]),
.I4(\bottom_right_1_reg_n_0_[7] ),
.I5(Lxx_11__1_carry__0_i_12_n_0),
.O(Lxx_11__1_carry__0_i_5_n_0));
LUT6 #(
.INIT(64'hA665599A599AA665))
Lxx_11__1_carry__0_i_6
(.I0(Lxx_11__1_carry__0_i_2_n_0),
.I1(top_left_1[5]),
.I2(\top_right_1_reg_n_0_[5] ),
.I3(bottom_left_1[5]),
.I4(\bottom_right_1_reg_n_0_[6] ),
.I5(Lxx_11__1_carry__0_i_9_n_0),
.O(Lxx_11__1_carry__0_i_6_n_0));
LUT6 #(
.INIT(64'hA665599A599AA665))
Lxx_11__1_carry__0_i_7
(.I0(Lxx_11__1_carry__0_i_3_n_0),
.I1(top_left_1[4]),
.I2(\top_right_1_reg_n_0_[4] ),
.I3(bottom_left_1[4]),
.I4(\bottom_right_1_reg_n_0_[5] ),
.I5(Lxx_11__1_carry__0_i_10_n_0),
.O(Lxx_11__1_carry__0_i_7_n_0));
LUT6 #(
.INIT(64'hA665599A599AA665))
Lxx_11__1_carry__0_i_8
(.I0(Lxx_11__1_carry__0_i_4_n_0),
.I1(top_left_1[3]),
.I2(\top_right_1_reg_n_0_[3] ),
.I3(bottom_left_1[3]),
.I4(\bottom_right_1_reg_n_0_[4] ),
.I5(Lxx_11__1_carry__0_i_11_n_0),
.O(Lxx_11__1_carry__0_i_8_n_0));
LUT3 #(
.INIT(8'h96))
Lxx_11__1_carry__0_i_9
(.I0(bottom_left_1[6]),
.I1(\top_right_1_reg_n_0_[6] ),
.I2(top_left_1[6]),
.O(Lxx_11__1_carry__0_i_9_n_0));
CARRY4 Lxx_11__1_carry__1
(.CI(Lxx_11__1_carry__0_n_0),
.CO({Lxx_11__1_carry__1_n_0,Lxx_11__1_carry__1_n_1,Lxx_11__1_carry__1_n_2,Lxx_11__1_carry__1_n_3}),
.CYINIT(1'b0),
.DI({Lxx_11__1_carry__1_i_1_n_0,Lxx_11__1_carry__1_i_2_n_0,Lxx_11__1_carry__1_i_3_n_0,Lxx_11__1_carry__1_i_4_n_0}),
.O(Lxx_11[11:8]),
.S({Lxx_11__1_carry__1_i_5_n_0,Lxx_11__1_carry__1_i_6_n_0,Lxx_11__1_carry__1_i_7_n_0,Lxx_11__1_carry__1_i_8_n_0}));
LUT5 #(
.INIT(32'h88E8E8EE))
Lxx_11__1_carry__1_i_1
(.I0(\bottom_right_1_reg_n_0_[10] ),
.I1(Lxx_11__1_carry__1_i_9_n_0),
.I2(top_left_1[9]),
.I3(\top_right_1_reg_n_0_[9] ),
.I4(bottom_left_1[9]),
.O(Lxx_11__1_carry__1_i_1_n_0));
LUT3 #(
.INIT(8'h96))
Lxx_11__1_carry__1_i_10
(.I0(bottom_left_1[9]),
.I1(\top_right_1_reg_n_0_[9] ),
.I2(top_left_1[9]),
.O(Lxx_11__1_carry__1_i_10_n_0));
LUT3 #(
.INIT(8'h96))
Lxx_11__1_carry__1_i_11
(.I0(bottom_left_1[8]),
.I1(\top_right_1_reg_n_0_[8] ),
.I2(top_left_1[8]),
.O(Lxx_11__1_carry__1_i_11_n_0));
LUT3 #(
.INIT(8'h96))
Lxx_11__1_carry__1_i_12
(.I0(bottom_left_1[11]),
.I1(\top_right_1_reg_n_0_[11] ),
.I2(top_left_1[11]),
.O(Lxx_11__1_carry__1_i_12_n_0));
LUT5 #(
.INIT(32'h88E8E8EE))
Lxx_11__1_carry__1_i_2
(.I0(\bottom_right_1_reg_n_0_[9] ),
.I1(Lxx_11__1_carry__1_i_10_n_0),
.I2(top_left_1[8]),
.I3(\top_right_1_reg_n_0_[8] ),
.I4(bottom_left_1[8]),
.O(Lxx_11__1_carry__1_i_2_n_0));
LUT5 #(
.INIT(32'h88E8E8EE))
Lxx_11__1_carry__1_i_3
(.I0(\bottom_right_1_reg_n_0_[8] ),
.I1(Lxx_11__1_carry__1_i_11_n_0),
.I2(top_left_1[7]),
.I3(\top_right_1_reg_n_0_[7] ),
.I4(bottom_left_1[7]),
.O(Lxx_11__1_carry__1_i_3_n_0));
LUT5 #(
.INIT(32'h88E8E8EE))
Lxx_11__1_carry__1_i_4
(.I0(\bottom_right_1_reg_n_0_[7] ),
.I1(Lxx_11__1_carry__0_i_12_n_0),
.I2(top_left_1[6]),
.I3(\top_right_1_reg_n_0_[6] ),
.I4(bottom_left_1[6]),
.O(Lxx_11__1_carry__1_i_4_n_0));
LUT6 #(
.INIT(64'hA665599A599AA665))
Lxx_11__1_carry__1_i_5
(.I0(Lxx_11__1_carry__1_i_1_n_0),
.I1(top_left_1[10]),
.I2(\top_right_1_reg_n_0_[10] ),
.I3(bottom_left_1[10]),
.I4(\bottom_right_1_reg_n_0_[11] ),
.I5(Lxx_11__1_carry__1_i_12_n_0),
.O(Lxx_11__1_carry__1_i_5_n_0));
LUT6 #(
.INIT(64'hA665599A599AA665))
Lxx_11__1_carry__1_i_6
(.I0(Lxx_11__1_carry__1_i_2_n_0),
.I1(top_left_1[9]),
.I2(\top_right_1_reg_n_0_[9] ),
.I3(bottom_left_1[9]),
.I4(\bottom_right_1_reg_n_0_[10] ),
.I5(Lxx_11__1_carry__1_i_9_n_0),
.O(Lxx_11__1_carry__1_i_6_n_0));
LUT6 #(
.INIT(64'hA665599A599AA665))
Lxx_11__1_carry__1_i_7
(.I0(Lxx_11__1_carry__1_i_3_n_0),
.I1(top_left_1[8]),
.I2(\top_right_1_reg_n_0_[8] ),
.I3(bottom_left_1[8]),
.I4(\bottom_right_1_reg_n_0_[9] ),
.I5(Lxx_11__1_carry__1_i_10_n_0),
.O(Lxx_11__1_carry__1_i_7_n_0));
LUT6 #(
.INIT(64'hA665599A599AA665))
Lxx_11__1_carry__1_i_8
(.I0(Lxx_11__1_carry__1_i_4_n_0),
.I1(top_left_1[7]),
.I2(\top_right_1_reg_n_0_[7] ),
.I3(bottom_left_1[7]),
.I4(\bottom_right_1_reg_n_0_[8] ),
.I5(Lxx_11__1_carry__1_i_11_n_0),
.O(Lxx_11__1_carry__1_i_8_n_0));
LUT3 #(
.INIT(8'h96))
Lxx_11__1_carry__1_i_9
(.I0(bottom_left_1[10]),
.I1(\top_right_1_reg_n_0_[10] ),
.I2(top_left_1[10]),
.O(Lxx_11__1_carry__1_i_9_n_0));
CARRY4 Lxx_11__1_carry__2
(.CI(Lxx_11__1_carry__1_n_0),
.CO({NLW_Lxx_11__1_carry__2_CO_UNCONNECTED[3],Lxx_11__1_carry__2_n_1,Lxx_11__1_carry__2_n_2,Lxx_11__1_carry__2_n_3}),
.CYINIT(1'b0),
.DI({1'b0,Lxx_11__1_carry__2_i_1_n_0,Lxx_11__1_carry__2_i_2_n_0,Lxx_11__1_carry__2_i_3_n_0}),
.O(Lxx_11[15:12]),
.S({Lxx_11__1_carry__2_i_4_n_0,Lxx_11__1_carry__2_i_5_n_0,Lxx_11__1_carry__2_i_6_n_0,Lxx_11__1_carry__2_i_7_n_0}));
LUT5 #(
.INIT(32'h88E8E8EE))
Lxx_11__1_carry__2_i_1
(.I0(\bottom_right_1_reg_n_0_[13] ),
.I1(Lxx_11__1_carry__2_i_8_n_0),
.I2(top_left_1[12]),
.I3(\top_right_1_reg_n_0_[12] ),
.I4(bottom_left_1[12]),
.O(Lxx_11__1_carry__2_i_1_n_0));
(* SOFT_HLUTNM = "soft_lutpair25" *)
LUT3 #(
.INIT(8'h2B))
Lxx_11__1_carry__2_i_10
(.I0(top_left_1[13]),
.I1(\top_right_1_reg_n_0_[13] ),
.I2(bottom_left_1[13]),
.O(Lxx_11__1_carry__2_i_10_n_0));
LUT4 #(
.INIT(16'h6996))
Lxx_11__1_carry__2_i_11
(.I0(\top_right_1_reg_n_0_[15] ),
.I1(bottom_left_1[15]),
.I2(\bottom_right_1_reg_n_0_[15] ),
.I3(top_left_1[15]),
.O(Lxx_11__1_carry__2_i_11_n_0));
LUT3 #(
.INIT(8'h96))
Lxx_11__1_carry__2_i_12
(.I0(bottom_left_1[14]),
.I1(\top_right_1_reg_n_0_[14] ),
.I2(top_left_1[14]),
.O(Lxx_11__1_carry__2_i_12_n_0));
LUT5 #(
.INIT(32'h88E8E8EE))
Lxx_11__1_carry__2_i_2
(.I0(\bottom_right_1_reg_n_0_[12] ),
.I1(Lxx_11__1_carry__2_i_9_n_0),
.I2(top_left_1[11]),
.I3(\top_right_1_reg_n_0_[11] ),
.I4(bottom_left_1[11]),
.O(Lxx_11__1_carry__2_i_2_n_0));
LUT5 #(
.INIT(32'h88E8E8EE))
Lxx_11__1_carry__2_i_3
(.I0(\bottom_right_1_reg_n_0_[11] ),
.I1(Lxx_11__1_carry__1_i_12_n_0),
.I2(top_left_1[10]),
.I3(\top_right_1_reg_n_0_[10] ),
.I4(bottom_left_1[10]),
.O(Lxx_11__1_carry__2_i_3_n_0));
LUT6 #(
.INIT(64'h178181E8E87E7E17))
Lxx_11__1_carry__2_i_4
(.I0(Lxx_11__1_carry__2_i_10_n_0),
.I1(\bottom_right_1_reg_n_0_[14] ),
.I2(top_left_1[14]),
.I3(\top_right_1_reg_n_0_[14] ),
.I4(bottom_left_1[14]),
.I5(Lxx_11__1_carry__2_i_11_n_0),
.O(Lxx_11__1_carry__2_i_4_n_0));
LUT6 #(
.INIT(64'hA665599A599AA665))
Lxx_11__1_carry__2_i_5
(.I0(Lxx_11__1_carry__2_i_1_n_0),
.I1(top_left_1[13]),
.I2(\top_right_1_reg_n_0_[13] ),
.I3(bottom_left_1[13]),
.I4(\bottom_right_1_reg_n_0_[14] ),
.I5(Lxx_11__1_carry__2_i_12_n_0),
.O(Lxx_11__1_carry__2_i_5_n_0));
LUT6 #(
.INIT(64'hA665599A599AA665))
Lxx_11__1_carry__2_i_6
(.I0(Lxx_11__1_carry__2_i_2_n_0),
.I1(top_left_1[12]),
.I2(\top_right_1_reg_n_0_[12] ),
.I3(bottom_left_1[12]),
.I4(\bottom_right_1_reg_n_0_[13] ),
.I5(Lxx_11__1_carry__2_i_8_n_0),
.O(Lxx_11__1_carry__2_i_6_n_0));
LUT6 #(
.INIT(64'hA665599A599AA665))
Lxx_11__1_carry__2_i_7
(.I0(Lxx_11__1_carry__2_i_3_n_0),
.I1(top_left_1[11]),
.I2(\top_right_1_reg_n_0_[11] ),
.I3(bottom_left_1[11]),
.I4(\bottom_right_1_reg_n_0_[12] ),
.I5(Lxx_11__1_carry__2_i_9_n_0),
.O(Lxx_11__1_carry__2_i_7_n_0));
(* SOFT_HLUTNM = "soft_lutpair25" *)
LUT3 #(
.INIT(8'h96))
Lxx_11__1_carry__2_i_8
(.I0(bottom_left_1[13]),
.I1(\top_right_1_reg_n_0_[13] ),
.I2(top_left_1[13]),
.O(Lxx_11__1_carry__2_i_8_n_0));
LUT3 #(
.INIT(8'h96))
Lxx_11__1_carry__2_i_9
(.I0(bottom_left_1[12]),
.I1(\top_right_1_reg_n_0_[12] ),
.I2(top_left_1[12]),
.O(Lxx_11__1_carry__2_i_9_n_0));
LUT6 #(
.INIT(64'h8228EBBEEBBEEBBE))
Lxx_11__1_carry_i_1
(.I0(\bottom_right_1_reg_n_0_[2] ),
.I1(top_left_1[2]),
.I2(\top_right_1_reg_n_0_[2] ),
.I3(bottom_left_1[2]),
.I4(bottom_left_1[1]),
.I5(\top_right_1_reg_n_0_[1] ),
.O(Lxx_11__1_carry_i_1_n_0));
LUT4 #(
.INIT(16'hF990))
Lxx_11__1_carry_i_2
(.I0(bottom_left_1[1]),
.I1(\top_right_1_reg_n_0_[1] ),
.I2(top_left_1[1]),
.I3(\bottom_right_1_reg_n_0_[1] ),
.O(Lxx_11__1_carry_i_2_n_0));
LUT4 #(
.INIT(16'h9669))
Lxx_11__1_carry_i_3
(.I0(\top_right_1_reg_n_0_[1] ),
.I1(bottom_left_1[1]),
.I2(\bottom_right_1_reg_n_0_[1] ),
.I3(top_left_1[1]),
.O(Lxx_11__1_carry_i_3_n_0));
LUT6 #(
.INIT(64'hA665599A599AA665))
Lxx_11__1_carry_i_4
(.I0(Lxx_11__1_carry_i_1_n_0),
.I1(top_left_1[2]),
.I2(\top_right_1_reg_n_0_[2] ),
.I3(bottom_left_1[2]),
.I4(\bottom_right_1_reg_n_0_[3] ),
.I5(Lxx_11__1_carry_i_8_n_0),
.O(Lxx_11__1_carry_i_4_n_0));
LUT5 #(
.INIT(32'h96696969))
Lxx_11__1_carry_i_5
(.I0(Lxx_11__1_carry_i_2_n_0),
.I1(\bottom_right_1_reg_n_0_[2] ),
.I2(Lxx_11__1_carry_i_9_n_0),
.I3(bottom_left_1[1]),
.I4(\top_right_1_reg_n_0_[1] ),
.O(Lxx_11__1_carry_i_5_n_0));
LUT4 #(
.INIT(16'hA665))
Lxx_11__1_carry_i_6
(.I0(Lxx_11__1_carry_i_3_n_0),
.I1(top_left_1[0]),
.I2(\top_right_1_reg_n_0_[0] ),
.I3(bottom_left_1[0]),
.O(Lxx_11__1_carry_i_6_n_0));
LUT4 #(
.INIT(16'h6996))
Lxx_11__1_carry_i_7
(.I0(bottom_left_1[0]),
.I1(\top_right_1_reg_n_0_[0] ),
.I2(top_left_1[0]),
.I3(\bottom_right_1_reg_n_0_[0] ),
.O(Lxx_11__1_carry_i_7_n_0));
LUT3 #(
.INIT(8'h96))
Lxx_11__1_carry_i_8
(.I0(bottom_left_1[3]),
.I1(\top_right_1_reg_n_0_[3] ),
.I2(top_left_1[3]),
.O(Lxx_11__1_carry_i_8_n_0));
LUT3 #(
.INIT(8'h96))
Lxx_11__1_carry_i_9
(.I0(bottom_left_1[2]),
.I1(\top_right_1_reg_n_0_[2] ),
.I2(top_left_1[2]),
.O(Lxx_11__1_carry_i_9_n_0));
FDRE #(
.INIT(1'b0))
\Lxx_1_reg[10]
(.C(clk_x16),
.CE(y5),
.D(Lxx_11[9]),
.Q(Lxx_1[10]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lxx_1_reg[11]
(.C(clk_x16),
.CE(y5),
.D(Lxx_11[10]),
.Q(Lxx_1[11]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lxx_1_reg[12]
(.C(clk_x16),
.CE(y5),
.D(Lxx_11[11]),
.Q(Lxx_1[12]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lxx_1_reg[13]
(.C(clk_x16),
.CE(y5),
.D(Lxx_11[12]),
.Q(Lxx_1[13]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lxx_1_reg[14]
(.C(clk_x16),
.CE(y5),
.D(Lxx_11[13]),
.Q(Lxx_1[14]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lxx_1_reg[15]
(.C(clk_x16),
.CE(y5),
.D(Lxx_11[14]),
.Q(Lxx_1[15]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lxx_1_reg[1]
(.C(clk_x16),
.CE(y5),
.D(Lxx_11[0]),
.Q(Lxx_1[1]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lxx_1_reg[2]
(.C(clk_x16),
.CE(y5),
.D(Lxx_11[1]),
.Q(Lxx_1[2]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lxx_1_reg[3]
(.C(clk_x16),
.CE(y5),
.D(Lxx_11[2]),
.Q(Lxx_1[3]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lxx_1_reg[4]
(.C(clk_x16),
.CE(y5),
.D(Lxx_11[3]),
.Q(Lxx_1[4]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lxx_1_reg[5]
(.C(clk_x16),
.CE(y5),
.D(Lxx_11[4]),
.Q(Lxx_1[5]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lxx_1_reg[6]
(.C(clk_x16),
.CE(y5),
.D(Lxx_11[5]),
.Q(Lxx_1[6]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lxx_1_reg[7]
(.C(clk_x16),
.CE(y5),
.D(Lxx_11[6]),
.Q(Lxx_1[7]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lxx_1_reg[8]
(.C(clk_x16),
.CE(y5),
.D(Lxx_11[7]),
.Q(Lxx_1[8]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lxx_1_reg[9]
(.C(clk_x16),
.CE(y5),
.D(Lxx_11[8]),
.Q(Lxx_1[9]),
.R(1'b0));
LUT6 #(
.INIT(64'h0010000000000000))
\Lxx_2[15]_i_1
(.I0(cycle[3]),
.I1(\cycle_reg[0]_rep_n_0 ),
.I2(\cycle_reg[1]_rep_n_0 ),
.I3(cycle[2]),
.I4(rst),
.I5(active),
.O(\Lxx_2[15]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\Lxx_2_reg[0]
(.C(clk_x16),
.CE(\Lxx_2[15]_i_1_n_0 ),
.D(Lxx_00[0]),
.Q(\Lxx_2_reg_n_0_[0] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lxx_2_reg[10]
(.C(clk_x16),
.CE(\Lxx_2[15]_i_1_n_0 ),
.D(Lxx_00[10]),
.Q(\Lxx_2_reg_n_0_[10] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lxx_2_reg[11]
(.C(clk_x16),
.CE(\Lxx_2[15]_i_1_n_0 ),
.D(Lxx_00[11]),
.Q(\Lxx_2_reg_n_0_[11] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lxx_2_reg[12]
(.C(clk_x16),
.CE(\Lxx_2[15]_i_1_n_0 ),
.D(Lxx_00[12]),
.Q(\Lxx_2_reg_n_0_[12] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lxx_2_reg[13]
(.C(clk_x16),
.CE(\Lxx_2[15]_i_1_n_0 ),
.D(Lxx_00[13]),
.Q(\Lxx_2_reg_n_0_[13] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lxx_2_reg[14]
(.C(clk_x16),
.CE(\Lxx_2[15]_i_1_n_0 ),
.D(Lxx_00[14]),
.Q(\Lxx_2_reg_n_0_[14] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lxx_2_reg[15]
(.C(clk_x16),
.CE(\Lxx_2[15]_i_1_n_0 ),
.D(Lxx_00[15]),
.Q(\Lxx_2_reg_n_0_[15] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lxx_2_reg[1]
(.C(clk_x16),
.CE(\Lxx_2[15]_i_1_n_0 ),
.D(Lxx_00[1]),
.Q(\Lxx_2_reg_n_0_[1] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lxx_2_reg[2]
(.C(clk_x16),
.CE(\Lxx_2[15]_i_1_n_0 ),
.D(Lxx_00[2]),
.Q(\Lxx_2_reg_n_0_[2] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lxx_2_reg[3]
(.C(clk_x16),
.CE(\Lxx_2[15]_i_1_n_0 ),
.D(Lxx_00[3]),
.Q(\Lxx_2_reg_n_0_[3] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lxx_2_reg[4]
(.C(clk_x16),
.CE(\Lxx_2[15]_i_1_n_0 ),
.D(Lxx_00[4]),
.Q(\Lxx_2_reg_n_0_[4] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lxx_2_reg[5]
(.C(clk_x16),
.CE(\Lxx_2[15]_i_1_n_0 ),
.D(Lxx_00[5]),
.Q(\Lxx_2_reg_n_0_[5] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lxx_2_reg[6]
(.C(clk_x16),
.CE(\Lxx_2[15]_i_1_n_0 ),
.D(Lxx_00[6]),
.Q(\Lxx_2_reg_n_0_[6] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lxx_2_reg[7]
(.C(clk_x16),
.CE(\Lxx_2[15]_i_1_n_0 ),
.D(Lxx_00[7]),
.Q(\Lxx_2_reg_n_0_[7] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lxx_2_reg[8]
(.C(clk_x16),
.CE(\Lxx_2[15]_i_1_n_0 ),
.D(Lxx_00[8]),
.Q(\Lxx_2_reg_n_0_[8] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lxx_2_reg[9]
(.C(clk_x16),
.CE(\Lxx_2[15]_i_1_n_0 ),
.D(Lxx_00[9]),
.Q(\Lxx_2_reg_n_0_[9] ),
.R(1'b0));
CARRY4 Lxy0__1_carry
(.CI(1'b0),
.CO({Lxy0__1_carry_n_0,Lxy0__1_carry_n_1,Lxy0__1_carry_n_2,Lxy0__1_carry_n_3}),
.CYINIT(1'b0),
.DI({Lxy0__1_carry_i_1_n_0,Lxy0__1_carry_i_2_n_0,Lxy0__1_carry_i_3_n_0,\Lxy_0_reg_n_0_[0] }),
.O({Lxy0__1_carry_n_4,Lxy0__1_carry_n_5,Lxy0__1_carry_n_6,Lxy0__1_carry_n_7}),
.S({Lxy0__1_carry_i_4_n_0,Lxy0__1_carry_i_5_n_0,Lxy0__1_carry_i_6_n_0,Lxy0__1_carry_i_7_n_0}));
CARRY4 Lxy0__1_carry__0
(.CI(Lxy0__1_carry_n_0),
.CO({Lxy0__1_carry__0_n_0,Lxy0__1_carry__0_n_1,Lxy0__1_carry__0_n_2,Lxy0__1_carry__0_n_3}),
.CYINIT(1'b0),
.DI({Lxy0__1_carry__0_i_1_n_0,Lxy0__1_carry__0_i_2_n_0,Lxy0__1_carry__0_i_3_n_0,Lxy0__1_carry__0_i_4_n_0}),
.O({Lxy0__1_carry__0_n_4,Lxy0__1_carry__0_n_5,Lxy0__1_carry__0_n_6,Lxy0__1_carry__0_n_7}),
.S({Lxy0__1_carry__0_i_5_n_0,Lxy0__1_carry__0_i_6_n_0,Lxy0__1_carry__0_i_7_n_0,Lxy0__1_carry__0_i_8_n_0}));
LUT5 #(
.INIT(32'h8E88EE8E))
Lxy0__1_carry__0_i_1
(.I0(\Lxy_0_reg_n_0_[6] ),
.I1(Lxy0__1_carry__0_i_9_n_0),
.I2(Lxy_3[5]),
.I3(Lxy_2[5]),
.I4(\Lxy_1_reg_n_0_[5] ),
.O(Lxy0__1_carry__0_i_1_n_0));
LUT3 #(
.INIT(8'h96))
Lxy0__1_carry__0_i_10
(.I0(Lxy_3[5]),
.I1(\Lxy_1_reg_n_0_[5] ),
.I2(Lxy_2[5]),
.O(Lxy0__1_carry__0_i_10_n_0));
LUT3 #(
.INIT(8'h96))
Lxy0__1_carry__0_i_11
(.I0(Lxy_3[4]),
.I1(\Lxy_1_reg_n_0_[4] ),
.I2(Lxy_2[4]),
.O(Lxy0__1_carry__0_i_11_n_0));
LUT3 #(
.INIT(8'h96))
Lxy0__1_carry__0_i_12
(.I0(Lxy_3[7]),
.I1(\Lxy_1_reg_n_0_[7] ),
.I2(Lxy_2[7]),
.O(Lxy0__1_carry__0_i_12_n_0));
LUT5 #(
.INIT(32'h8E88EE8E))
Lxy0__1_carry__0_i_2
(.I0(\Lxy_0_reg_n_0_[5] ),
.I1(Lxy0__1_carry__0_i_10_n_0),
.I2(Lxy_3[4]),
.I3(Lxy_2[4]),
.I4(\Lxy_1_reg_n_0_[4] ),
.O(Lxy0__1_carry__0_i_2_n_0));
LUT5 #(
.INIT(32'h8E88EE8E))
Lxy0__1_carry__0_i_3
(.I0(\Lxy_0_reg_n_0_[4] ),
.I1(Lxy0__1_carry__0_i_11_n_0),
.I2(Lxy_3[3]),
.I3(Lxy_2[3]),
.I4(\Lxy_1_reg_n_0_[3] ),
.O(Lxy0__1_carry__0_i_3_n_0));
LUT5 #(
.INIT(32'h8E88EE8E))
Lxy0__1_carry__0_i_4
(.I0(\Lxy_0_reg_n_0_[3] ),
.I1(Lxy0__1_carry_i_8_n_0),
.I2(Lxy_3[2]),
.I3(Lxy_2[2]),
.I4(\Lxy_1_reg_n_0_[2] ),
.O(Lxy0__1_carry__0_i_4_n_0));
LUT6 #(
.INIT(64'h9669969669699669))
Lxy0__1_carry__0_i_5
(.I0(Lxy0__1_carry__0_i_1_n_0),
.I1(Lxy0__1_carry__0_i_12_n_0),
.I2(\Lxy_0_reg_n_0_[7] ),
.I3(\Lxy_1_reg_n_0_[6] ),
.I4(Lxy_2[6]),
.I5(Lxy_3[6]),
.O(Lxy0__1_carry__0_i_5_n_0));
LUT6 #(
.INIT(64'h9669969669699669))
Lxy0__1_carry__0_i_6
(.I0(Lxy0__1_carry__0_i_2_n_0),
.I1(Lxy0__1_carry__0_i_9_n_0),
.I2(\Lxy_0_reg_n_0_[6] ),
.I3(\Lxy_1_reg_n_0_[5] ),
.I4(Lxy_2[5]),
.I5(Lxy_3[5]),
.O(Lxy0__1_carry__0_i_6_n_0));
LUT6 #(
.INIT(64'h9669969669699669))
Lxy0__1_carry__0_i_7
(.I0(Lxy0__1_carry__0_i_3_n_0),
.I1(Lxy0__1_carry__0_i_10_n_0),
.I2(\Lxy_0_reg_n_0_[5] ),
.I3(\Lxy_1_reg_n_0_[4] ),
.I4(Lxy_2[4]),
.I5(Lxy_3[4]),
.O(Lxy0__1_carry__0_i_7_n_0));
LUT6 #(
.INIT(64'h9669969669699669))
Lxy0__1_carry__0_i_8
(.I0(Lxy0__1_carry__0_i_4_n_0),
.I1(Lxy0__1_carry__0_i_11_n_0),
.I2(\Lxy_0_reg_n_0_[4] ),
.I3(\Lxy_1_reg_n_0_[3] ),
.I4(Lxy_2[3]),
.I5(Lxy_3[3]),
.O(Lxy0__1_carry__0_i_8_n_0));
LUT3 #(
.INIT(8'h96))
Lxy0__1_carry__0_i_9
(.I0(Lxy_3[6]),
.I1(\Lxy_1_reg_n_0_[6] ),
.I2(Lxy_2[6]),
.O(Lxy0__1_carry__0_i_9_n_0));
CARRY4 Lxy0__1_carry__1
(.CI(Lxy0__1_carry__0_n_0),
.CO({Lxy0__1_carry__1_n_0,Lxy0__1_carry__1_n_1,Lxy0__1_carry__1_n_2,Lxy0__1_carry__1_n_3}),
.CYINIT(1'b0),
.DI({Lxy0__1_carry__1_i_1_n_0,Lxy0__1_carry__1_i_2_n_0,Lxy0__1_carry__1_i_3_n_0,Lxy0__1_carry__1_i_4_n_0}),
.O({Lxy0__1_carry__1_n_4,Lxy0__1_carry__1_n_5,Lxy0__1_carry__1_n_6,Lxy0__1_carry__1_n_7}),
.S({Lxy0__1_carry__1_i_5_n_0,Lxy0__1_carry__1_i_6_n_0,Lxy0__1_carry__1_i_7_n_0,Lxy0__1_carry__1_i_8_n_0}));
LUT5 #(
.INIT(32'h8E88EE8E))
Lxy0__1_carry__1_i_1
(.I0(\Lxy_0_reg_n_0_[10] ),
.I1(Lxy0__1_carry__1_i_9_n_0),
.I2(Lxy_3[9]),
.I3(Lxy_2[9]),
.I4(\Lxy_1_reg_n_0_[9] ),
.O(Lxy0__1_carry__1_i_1_n_0));
LUT3 #(
.INIT(8'h96))
Lxy0__1_carry__1_i_10
(.I0(Lxy_3[9]),
.I1(\Lxy_1_reg_n_0_[9] ),
.I2(Lxy_2[9]),
.O(Lxy0__1_carry__1_i_10_n_0));
LUT3 #(
.INIT(8'h96))
Lxy0__1_carry__1_i_11
(.I0(Lxy_3[8]),
.I1(\Lxy_1_reg_n_0_[8] ),
.I2(Lxy_2[8]),
.O(Lxy0__1_carry__1_i_11_n_0));
LUT3 #(
.INIT(8'h96))
Lxy0__1_carry__1_i_12
(.I0(Lxy_3[11]),
.I1(\Lxy_1_reg_n_0_[11] ),
.I2(Lxy_2[11]),
.O(Lxy0__1_carry__1_i_12_n_0));
LUT5 #(
.INIT(32'h8E88EE8E))
Lxy0__1_carry__1_i_2
(.I0(\Lxy_0_reg_n_0_[9] ),
.I1(Lxy0__1_carry__1_i_10_n_0),
.I2(Lxy_3[8]),
.I3(Lxy_2[8]),
.I4(\Lxy_1_reg_n_0_[8] ),
.O(Lxy0__1_carry__1_i_2_n_0));
LUT5 #(
.INIT(32'h8E88EE8E))
Lxy0__1_carry__1_i_3
(.I0(\Lxy_0_reg_n_0_[8] ),
.I1(Lxy0__1_carry__1_i_11_n_0),
.I2(Lxy_3[7]),
.I3(Lxy_2[7]),
.I4(\Lxy_1_reg_n_0_[7] ),
.O(Lxy0__1_carry__1_i_3_n_0));
LUT5 #(
.INIT(32'h8E88EE8E))
Lxy0__1_carry__1_i_4
(.I0(\Lxy_0_reg_n_0_[7] ),
.I1(Lxy0__1_carry__0_i_12_n_0),
.I2(Lxy_3[6]),
.I3(Lxy_2[6]),
.I4(\Lxy_1_reg_n_0_[6] ),
.O(Lxy0__1_carry__1_i_4_n_0));
LUT6 #(
.INIT(64'h9669969669699669))
Lxy0__1_carry__1_i_5
(.I0(Lxy0__1_carry__1_i_1_n_0),
.I1(Lxy0__1_carry__1_i_12_n_0),
.I2(\Lxy_0_reg_n_0_[11] ),
.I3(\Lxy_1_reg_n_0_[10] ),
.I4(Lxy_2[10]),
.I5(Lxy_3[10]),
.O(Lxy0__1_carry__1_i_5_n_0));
LUT6 #(
.INIT(64'h9669969669699669))
Lxy0__1_carry__1_i_6
(.I0(Lxy0__1_carry__1_i_2_n_0),
.I1(Lxy0__1_carry__1_i_9_n_0),
.I2(\Lxy_0_reg_n_0_[10] ),
.I3(\Lxy_1_reg_n_0_[9] ),
.I4(Lxy_2[9]),
.I5(Lxy_3[9]),
.O(Lxy0__1_carry__1_i_6_n_0));
LUT6 #(
.INIT(64'h9669969669699669))
Lxy0__1_carry__1_i_7
(.I0(Lxy0__1_carry__1_i_3_n_0),
.I1(Lxy0__1_carry__1_i_10_n_0),
.I2(\Lxy_0_reg_n_0_[9] ),
.I3(\Lxy_1_reg_n_0_[8] ),
.I4(Lxy_2[8]),
.I5(Lxy_3[8]),
.O(Lxy0__1_carry__1_i_7_n_0));
LUT6 #(
.INIT(64'h9669969669699669))
Lxy0__1_carry__1_i_8
(.I0(Lxy0__1_carry__1_i_4_n_0),
.I1(Lxy0__1_carry__1_i_11_n_0),
.I2(\Lxy_0_reg_n_0_[8] ),
.I3(\Lxy_1_reg_n_0_[7] ),
.I4(Lxy_2[7]),
.I5(Lxy_3[7]),
.O(Lxy0__1_carry__1_i_8_n_0));
LUT3 #(
.INIT(8'h96))
Lxy0__1_carry__1_i_9
(.I0(Lxy_3[10]),
.I1(\Lxy_1_reg_n_0_[10] ),
.I2(Lxy_2[10]),
.O(Lxy0__1_carry__1_i_9_n_0));
CARRY4 Lxy0__1_carry__2
(.CI(Lxy0__1_carry__1_n_0),
.CO({NLW_Lxy0__1_carry__2_CO_UNCONNECTED[3],Lxy0__1_carry__2_n_1,Lxy0__1_carry__2_n_2,Lxy0__1_carry__2_n_3}),
.CYINIT(1'b0),
.DI({1'b0,Lxy0__1_carry__2_i_1_n_0,Lxy0__1_carry__2_i_2_n_0,Lxy0__1_carry__2_i_3_n_0}),
.O({Lxy0__1_carry__2_n_4,Lxy0__1_carry__2_n_5,Lxy0__1_carry__2_n_6,Lxy0__1_carry__2_n_7}),
.S({Lxy0__1_carry__2_i_4_n_0,Lxy0__1_carry__2_i_5_n_0,Lxy0__1_carry__2_i_6_n_0,Lxy0__1_carry__2_i_7_n_0}));
LUT5 #(
.INIT(32'h8E88EE8E))
Lxy0__1_carry__2_i_1
(.I0(\Lxy_0_reg_n_0_[13] ),
.I1(Lxy0__1_carry__2_i_8_n_0),
.I2(Lxy_3[12]),
.I3(Lxy_2[12]),
.I4(\Lxy_1_reg_n_0_[12] ),
.O(Lxy0__1_carry__2_i_1_n_0));
(* SOFT_HLUTNM = "soft_lutpair32" *)
LUT3 #(
.INIT(8'h4D))
Lxy0__1_carry__2_i_10
(.I0(\Lxy_1_reg_n_0_[13] ),
.I1(Lxy_2[13]),
.I2(Lxy_3[13]),
.O(Lxy0__1_carry__2_i_10_n_0));
LUT4 #(
.INIT(16'h6996))
Lxy0__1_carry__2_i_11
(.I0(Lxy_2[15]),
.I1(\Lxy_1_reg_n_0_[15] ),
.I2(Lxy_3[15]),
.I3(\Lxy_0_reg_n_0_[15] ),
.O(Lxy0__1_carry__2_i_11_n_0));
LUT3 #(
.INIT(8'h96))
Lxy0__1_carry__2_i_12
(.I0(Lxy_3[14]),
.I1(\Lxy_1_reg_n_0_[14] ),
.I2(Lxy_2[14]),
.O(Lxy0__1_carry__2_i_12_n_0));
LUT5 #(
.INIT(32'h8E88EE8E))
Lxy0__1_carry__2_i_2
(.I0(\Lxy_0_reg_n_0_[12] ),
.I1(Lxy0__1_carry__2_i_9_n_0),
.I2(Lxy_3[11]),
.I3(Lxy_2[11]),
.I4(\Lxy_1_reg_n_0_[11] ),
.O(Lxy0__1_carry__2_i_2_n_0));
LUT5 #(
.INIT(32'h8E88EE8E))
Lxy0__1_carry__2_i_3
(.I0(\Lxy_0_reg_n_0_[11] ),
.I1(Lxy0__1_carry__1_i_12_n_0),
.I2(Lxy_3[10]),
.I3(Lxy_2[10]),
.I4(\Lxy_1_reg_n_0_[10] ),
.O(Lxy0__1_carry__2_i_3_n_0));
LUT6 #(
.INIT(64'h1E87781E87E11E87))
Lxy0__1_carry__2_i_4
(.I0(Lxy0__1_carry__2_i_10_n_0),
.I1(\Lxy_0_reg_n_0_[14] ),
.I2(Lxy0__1_carry__2_i_11_n_0),
.I3(\Lxy_1_reg_n_0_[14] ),
.I4(Lxy_2[14]),
.I5(Lxy_3[14]),
.O(Lxy0__1_carry__2_i_4_n_0));
LUT6 #(
.INIT(64'h9669969669699669))
Lxy0__1_carry__2_i_5
(.I0(Lxy0__1_carry__2_i_1_n_0),
.I1(Lxy0__1_carry__2_i_12_n_0),
.I2(\Lxy_0_reg_n_0_[14] ),
.I3(\Lxy_1_reg_n_0_[13] ),
.I4(Lxy_2[13]),
.I5(Lxy_3[13]),
.O(Lxy0__1_carry__2_i_5_n_0));
LUT6 #(
.INIT(64'h9669969669699669))
Lxy0__1_carry__2_i_6
(.I0(Lxy0__1_carry__2_i_2_n_0),
.I1(Lxy0__1_carry__2_i_8_n_0),
.I2(\Lxy_0_reg_n_0_[13] ),
.I3(\Lxy_1_reg_n_0_[12] ),
.I4(Lxy_2[12]),
.I5(Lxy_3[12]),
.O(Lxy0__1_carry__2_i_6_n_0));
LUT6 #(
.INIT(64'h9669969669699669))
Lxy0__1_carry__2_i_7
(.I0(Lxy0__1_carry__2_i_3_n_0),
.I1(Lxy0__1_carry__2_i_9_n_0),
.I2(\Lxy_0_reg_n_0_[12] ),
.I3(\Lxy_1_reg_n_0_[11] ),
.I4(Lxy_2[11]),
.I5(Lxy_3[11]),
.O(Lxy0__1_carry__2_i_7_n_0));
(* SOFT_HLUTNM = "soft_lutpair32" *)
LUT3 #(
.INIT(8'h96))
Lxy0__1_carry__2_i_8
(.I0(Lxy_3[13]),
.I1(\Lxy_1_reg_n_0_[13] ),
.I2(Lxy_2[13]),
.O(Lxy0__1_carry__2_i_8_n_0));
LUT3 #(
.INIT(8'h96))
Lxy0__1_carry__2_i_9
(.I0(Lxy_3[12]),
.I1(\Lxy_1_reg_n_0_[12] ),
.I2(Lxy_2[12]),
.O(Lxy0__1_carry__2_i_9_n_0));
LUT6 #(
.INIT(64'hEBBEEBBE8228EBBE))
Lxy0__1_carry_i_1
(.I0(\Lxy_0_reg_n_0_[2] ),
.I1(Lxy_2[2]),
.I2(\Lxy_1_reg_n_0_[2] ),
.I3(Lxy_3[2]),
.I4(\Lxy_1_reg_n_0_[1] ),
.I5(Lxy_2[1]),
.O(Lxy0__1_carry_i_1_n_0));
LUT2 #(
.INIT(4'h9))
Lxy0__1_carry_i_10
(.I0(Lxy_2[1]),
.I1(\Lxy_1_reg_n_0_[1] ),
.O(Lxy0__1_carry_i_10_n_0));
LUT4 #(
.INIT(16'h4DD4))
Lxy0__1_carry_i_2
(.I0(Lxy_3[1]),
.I1(\Lxy_0_reg_n_0_[1] ),
.I2(\Lxy_1_reg_n_0_[1] ),
.I3(Lxy_2[1]),
.O(Lxy0__1_carry_i_2_n_0));
LUT4 #(
.INIT(16'h9669))
Lxy0__1_carry_i_3
(.I0(\Lxy_1_reg_n_0_[1] ),
.I1(Lxy_2[1]),
.I2(Lxy_3[1]),
.I3(\Lxy_0_reg_n_0_[1] ),
.O(Lxy0__1_carry_i_3_n_0));
LUT6 #(
.INIT(64'h9669969669699669))
Lxy0__1_carry_i_4
(.I0(Lxy0__1_carry_i_1_n_0),
.I1(Lxy0__1_carry_i_8_n_0),
.I2(\Lxy_0_reg_n_0_[3] ),
.I3(\Lxy_1_reg_n_0_[2] ),
.I4(Lxy_2[2]),
.I5(Lxy_3[2]),
.O(Lxy0__1_carry_i_4_n_0));
LUT5 #(
.INIT(32'h69966969))
Lxy0__1_carry_i_5
(.I0(Lxy0__1_carry_i_2_n_0),
.I1(Lxy0__1_carry_i_9_n_0),
.I2(\Lxy_0_reg_n_0_[2] ),
.I3(Lxy_2[1]),
.I4(\Lxy_1_reg_n_0_[1] ),
.O(Lxy0__1_carry_i_5_n_0));
LUT6 #(
.INIT(64'h9669969669699669))
Lxy0__1_carry_i_6
(.I0(\Lxy_0_reg_n_0_[1] ),
.I1(Lxy_3[1]),
.I2(Lxy0__1_carry_i_10_n_0),
.I3(Lxy_3[0]),
.I4(Lxy_2[0]),
.I5(\Lxy_1_reg_n_0_[0] ),
.O(Lxy0__1_carry_i_6_n_0));
LUT4 #(
.INIT(16'h6996))
Lxy0__1_carry_i_7
(.I0(Lxy_2[0]),
.I1(\Lxy_1_reg_n_0_[0] ),
.I2(Lxy_3[0]),
.I3(\Lxy_0_reg_n_0_[0] ),
.O(Lxy0__1_carry_i_7_n_0));
LUT3 #(
.INIT(8'h96))
Lxy0__1_carry_i_8
(.I0(Lxy_3[3]),
.I1(\Lxy_1_reg_n_0_[3] ),
.I2(Lxy_2[3]),
.O(Lxy0__1_carry_i_8_n_0));
LUT3 #(
.INIT(8'h96))
Lxy0__1_carry_i_9
(.I0(Lxy_3[2]),
.I1(\Lxy_1_reg_n_0_[2] ),
.I2(Lxy_2[2]),
.O(Lxy0__1_carry_i_9_n_0));
LUT6 #(
.INIT(64'h0000000000004000))
\Lxy_0[15]_i_1
(.I0(\cycle_reg[0]_rep_n_0 ),
.I1(cycle[3]),
.I2(active),
.I3(rst),
.I4(\cycle_reg[1]_rep_n_0 ),
.I5(cycle[2]),
.O(\Lxy_0[15]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\Lxy_0_reg[0]
(.C(clk_x16),
.CE(\Lxy_0[15]_i_1_n_0 ),
.D(Lxx_00[0]),
.Q(\Lxy_0_reg_n_0_[0] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lxy_0_reg[10]
(.C(clk_x16),
.CE(\Lxy_0[15]_i_1_n_0 ),
.D(Lxx_00[10]),
.Q(\Lxy_0_reg_n_0_[10] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lxy_0_reg[11]
(.C(clk_x16),
.CE(\Lxy_0[15]_i_1_n_0 ),
.D(Lxx_00[11]),
.Q(\Lxy_0_reg_n_0_[11] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lxy_0_reg[12]
(.C(clk_x16),
.CE(\Lxy_0[15]_i_1_n_0 ),
.D(Lxx_00[12]),
.Q(\Lxy_0_reg_n_0_[12] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lxy_0_reg[13]
(.C(clk_x16),
.CE(\Lxy_0[15]_i_1_n_0 ),
.D(Lxx_00[13]),
.Q(\Lxy_0_reg_n_0_[13] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lxy_0_reg[14]
(.C(clk_x16),
.CE(\Lxy_0[15]_i_1_n_0 ),
.D(Lxx_00[14]),
.Q(\Lxy_0_reg_n_0_[14] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lxy_0_reg[15]
(.C(clk_x16),
.CE(\Lxy_0[15]_i_1_n_0 ),
.D(Lxx_00[15]),
.Q(\Lxy_0_reg_n_0_[15] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lxy_0_reg[1]
(.C(clk_x16),
.CE(\Lxy_0[15]_i_1_n_0 ),
.D(Lxx_00[1]),
.Q(\Lxy_0_reg_n_0_[1] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lxy_0_reg[2]
(.C(clk_x16),
.CE(\Lxy_0[15]_i_1_n_0 ),
.D(Lxx_00[2]),
.Q(\Lxy_0_reg_n_0_[2] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lxy_0_reg[3]
(.C(clk_x16),
.CE(\Lxy_0[15]_i_1_n_0 ),
.D(Lxx_00[3]),
.Q(\Lxy_0_reg_n_0_[3] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lxy_0_reg[4]
(.C(clk_x16),
.CE(\Lxy_0[15]_i_1_n_0 ),
.D(Lxx_00[4]),
.Q(\Lxy_0_reg_n_0_[4] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lxy_0_reg[5]
(.C(clk_x16),
.CE(\Lxy_0[15]_i_1_n_0 ),
.D(Lxx_00[5]),
.Q(\Lxy_0_reg_n_0_[5] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lxy_0_reg[6]
(.C(clk_x16),
.CE(\Lxy_0[15]_i_1_n_0 ),
.D(Lxx_00[6]),
.Q(\Lxy_0_reg_n_0_[6] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lxy_0_reg[7]
(.C(clk_x16),
.CE(\Lxy_0[15]_i_1_n_0 ),
.D(Lxx_00[7]),
.Q(\Lxy_0_reg_n_0_[7] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lxy_0_reg[8]
(.C(clk_x16),
.CE(\Lxy_0[15]_i_1_n_0 ),
.D(Lxx_00[8]),
.Q(\Lxy_0_reg_n_0_[8] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lxy_0_reg[9]
(.C(clk_x16),
.CE(\Lxy_0[15]_i_1_n_0 ),
.D(Lxx_00[9]),
.Q(\Lxy_0_reg_n_0_[9] ),
.R(1'b0));
LUT6 #(
.INIT(64'h0000400000000000))
\Lxy_1[15]_i_1
(.I0(\cycle_reg[0]_rep_n_0 ),
.I1(cycle[3]),
.I2(active),
.I3(rst),
.I4(cycle[2]),
.I5(\cycle_reg[1]_rep_n_0 ),
.O(Lxy_1));
FDRE #(
.INIT(1'b0))
\Lxy_1_reg[0]
(.C(clk_x16),
.CE(Lxy_1),
.D(Lxx_11[0]),
.Q(\Lxy_1_reg_n_0_[0] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lxy_1_reg[10]
(.C(clk_x16),
.CE(Lxy_1),
.D(Lxx_11[10]),
.Q(\Lxy_1_reg_n_0_[10] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lxy_1_reg[11]
(.C(clk_x16),
.CE(Lxy_1),
.D(Lxx_11[11]),
.Q(\Lxy_1_reg_n_0_[11] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lxy_1_reg[12]
(.C(clk_x16),
.CE(Lxy_1),
.D(Lxx_11[12]),
.Q(\Lxy_1_reg_n_0_[12] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lxy_1_reg[13]
(.C(clk_x16),
.CE(Lxy_1),
.D(Lxx_11[13]),
.Q(\Lxy_1_reg_n_0_[13] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lxy_1_reg[14]
(.C(clk_x16),
.CE(Lxy_1),
.D(Lxx_11[14]),
.Q(\Lxy_1_reg_n_0_[14] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lxy_1_reg[15]
(.C(clk_x16),
.CE(Lxy_1),
.D(Lxx_11[15]),
.Q(\Lxy_1_reg_n_0_[15] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lxy_1_reg[1]
(.C(clk_x16),
.CE(Lxy_1),
.D(Lxx_11[1]),
.Q(\Lxy_1_reg_n_0_[1] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lxy_1_reg[2]
(.C(clk_x16),
.CE(Lxy_1),
.D(Lxx_11[2]),
.Q(\Lxy_1_reg_n_0_[2] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lxy_1_reg[3]
(.C(clk_x16),
.CE(Lxy_1),
.D(Lxx_11[3]),
.Q(\Lxy_1_reg_n_0_[3] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lxy_1_reg[4]
(.C(clk_x16),
.CE(Lxy_1),
.D(Lxx_11[4]),
.Q(\Lxy_1_reg_n_0_[4] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lxy_1_reg[5]
(.C(clk_x16),
.CE(Lxy_1),
.D(Lxx_11[5]),
.Q(\Lxy_1_reg_n_0_[5] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lxy_1_reg[6]
(.C(clk_x16),
.CE(Lxy_1),
.D(Lxx_11[6]),
.Q(\Lxy_1_reg_n_0_[6] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lxy_1_reg[7]
(.C(clk_x16),
.CE(Lxy_1),
.D(Lxx_11[7]),
.Q(\Lxy_1_reg_n_0_[7] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lxy_1_reg[8]
(.C(clk_x16),
.CE(Lxy_1),
.D(Lxx_11[8]),
.Q(\Lxy_1_reg_n_0_[8] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lxy_1_reg[9]
(.C(clk_x16),
.CE(Lxy_1),
.D(Lxx_11[9]),
.Q(\Lxy_1_reg_n_0_[9] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lxy_2_reg[0]
(.C(clk_x16),
.CE(det_0),
.D(Lxx_00[0]),
.Q(Lxy_2[0]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lxy_2_reg[10]
(.C(clk_x16),
.CE(det_0),
.D(Lxx_00[10]),
.Q(Lxy_2[10]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lxy_2_reg[11]
(.C(clk_x16),
.CE(det_0),
.D(Lxx_00[11]),
.Q(Lxy_2[11]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lxy_2_reg[12]
(.C(clk_x16),
.CE(det_0),
.D(Lxx_00[12]),
.Q(Lxy_2[12]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lxy_2_reg[13]
(.C(clk_x16),
.CE(det_0),
.D(Lxx_00[13]),
.Q(Lxy_2[13]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lxy_2_reg[14]
(.C(clk_x16),
.CE(det_0),
.D(Lxx_00[14]),
.Q(Lxy_2[14]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lxy_2_reg[15]
(.C(clk_x16),
.CE(det_0),
.D(Lxx_00[15]),
.Q(Lxy_2[15]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lxy_2_reg[1]
(.C(clk_x16),
.CE(det_0),
.D(Lxx_00[1]),
.Q(Lxy_2[1]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lxy_2_reg[2]
(.C(clk_x16),
.CE(det_0),
.D(Lxx_00[2]),
.Q(Lxy_2[2]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lxy_2_reg[3]
(.C(clk_x16),
.CE(det_0),
.D(Lxx_00[3]),
.Q(Lxy_2[3]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lxy_2_reg[4]
(.C(clk_x16),
.CE(det_0),
.D(Lxx_00[4]),
.Q(Lxy_2[4]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lxy_2_reg[5]
(.C(clk_x16),
.CE(det_0),
.D(Lxx_00[5]),
.Q(Lxy_2[5]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lxy_2_reg[6]
(.C(clk_x16),
.CE(det_0),
.D(Lxx_00[6]),
.Q(Lxy_2[6]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lxy_2_reg[7]
(.C(clk_x16),
.CE(det_0),
.D(Lxx_00[7]),
.Q(Lxy_2[7]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lxy_2_reg[8]
(.C(clk_x16),
.CE(det_0),
.D(Lxx_00[8]),
.Q(Lxy_2[8]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lxy_2_reg[9]
(.C(clk_x16),
.CE(det_0),
.D(Lxx_00[9]),
.Q(Lxy_2[9]),
.R(1'b0));
LUT6 #(
.INIT(64'h4000000000000000))
\Lxy_3[15]_i_1
(.I0(cycle[0]),
.I1(active),
.I2(rst),
.I3(\cycle_reg[2]_rep_n_0 ),
.I4(\cycle_reg[1]_rep__0_n_0 ),
.I5(cycle[3]),
.O(y6));
FDRE #(
.INIT(1'b0))
\Lxy_3_reg[0]
(.C(clk_x16),
.CE(y6),
.D(Lxx_11[0]),
.Q(Lxy_3[0]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lxy_3_reg[10]
(.C(clk_x16),
.CE(y6),
.D(Lxx_11[10]),
.Q(Lxy_3[10]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lxy_3_reg[11]
(.C(clk_x16),
.CE(y6),
.D(Lxx_11[11]),
.Q(Lxy_3[11]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lxy_3_reg[12]
(.C(clk_x16),
.CE(y6),
.D(Lxx_11[12]),
.Q(Lxy_3[12]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lxy_3_reg[13]
(.C(clk_x16),
.CE(y6),
.D(Lxx_11[13]),
.Q(Lxy_3[13]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lxy_3_reg[14]
(.C(clk_x16),
.CE(y6),
.D(Lxx_11[14]),
.Q(Lxy_3[14]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lxy_3_reg[15]
(.C(clk_x16),
.CE(y6),
.D(Lxx_11[15]),
.Q(Lxy_3[15]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lxy_3_reg[1]
(.C(clk_x16),
.CE(y6),
.D(Lxx_11[1]),
.Q(Lxy_3[1]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lxy_3_reg[2]
(.C(clk_x16),
.CE(y6),
.D(Lxx_11[2]),
.Q(Lxy_3[2]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lxy_3_reg[3]
(.C(clk_x16),
.CE(y6),
.D(Lxx_11[3]),
.Q(Lxy_3[3]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lxy_3_reg[4]
(.C(clk_x16),
.CE(y6),
.D(Lxx_11[4]),
.Q(Lxy_3[4]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lxy_3_reg[5]
(.C(clk_x16),
.CE(y6),
.D(Lxx_11[5]),
.Q(Lxy_3[5]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lxy_3_reg[6]
(.C(clk_x16),
.CE(y6),
.D(Lxx_11[6]),
.Q(Lxy_3[6]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lxy_3_reg[7]
(.C(clk_x16),
.CE(y6),
.D(Lxx_11[7]),
.Q(Lxy_3[7]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lxy_3_reg[8]
(.C(clk_x16),
.CE(y6),
.D(Lxx_11[8]),
.Q(Lxy_3[8]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lxy_3_reg[9]
(.C(clk_x16),
.CE(y6),
.D(Lxx_11[9]),
.Q(Lxy_3[9]),
.R(1'b0));
CARRY4 Lyy0_carry
(.CI(1'b0),
.CO({Lyy0_carry_n_0,Lyy0_carry_n_1,Lyy0_carry_n_2,Lyy0_carry_n_3}),
.CYINIT(1'b0),
.DI({Lyy0_carry_i_1_n_0,Lyy0_carry_i_2_n_0,1'b1,\Lyy_2_reg_n_0_[0] }),
.O(B[3:0]),
.S({Lyy0_carry_i_3_n_0,Lyy0_carry_i_4_n_0,Lyy0_carry_i_5_n_0,Lyy0_carry_i_6_n_0}));
CARRY4 Lyy0_carry__0
(.CI(Lyy0_carry_n_0),
.CO({Lyy0_carry__0_n_0,Lyy0_carry__0_n_1,Lyy0_carry__0_n_2,Lyy0_carry__0_n_3}),
.CYINIT(1'b0),
.DI({Lyy0_carry__0_i_1_n_0,Lyy0_carry__0_i_2_n_0,Lyy0_carry__0_i_3_n_0,Lyy0_carry__0_i_4_n_0}),
.O(B[7:4]),
.S({Lyy0_carry__0_i_5_n_0,Lyy0_carry__0_i_6_n_0,Lyy0_carry__0_i_7_n_0,Lyy0_carry__0_i_8_n_0}));
(* HLUTNM = "lutpair16" *)
LUT3 #(
.INIT(8'hD4))
Lyy0_carry__0_i_1
(.I0(Lyy_1[6]),
.I1(\Lyy_2_reg_n_0_[6] ),
.I2(\Lyy_0_reg_n_0_[6] ),
.O(Lyy0_carry__0_i_1_n_0));
(* HLUTNM = "lutpair15" *)
LUT3 #(
.INIT(8'hD4))
Lyy0_carry__0_i_2
(.I0(Lyy_1[5]),
.I1(\Lyy_2_reg_n_0_[5] ),
.I2(\Lyy_0_reg_n_0_[5] ),
.O(Lyy0_carry__0_i_2_n_0));
(* HLUTNM = "lutpair14" *)
LUT3 #(
.INIT(8'hD4))
Lyy0_carry__0_i_3
(.I0(Lyy_1[4]),
.I1(\Lyy_2_reg_n_0_[4] ),
.I2(\Lyy_0_reg_n_0_[4] ),
.O(Lyy0_carry__0_i_3_n_0));
(* HLUTNM = "lutpair13" *)
LUT3 #(
.INIT(8'hD4))
Lyy0_carry__0_i_4
(.I0(Lyy_1[3]),
.I1(\Lyy_2_reg_n_0_[3] ),
.I2(\Lyy_0_reg_n_0_[3] ),
.O(Lyy0_carry__0_i_4_n_0));
(* HLUTNM = "lutpair17" *)
LUT4 #(
.INIT(16'h9669))
Lyy0_carry__0_i_5
(.I0(Lyy_1[7]),
.I1(\Lyy_2_reg_n_0_[7] ),
.I2(\Lyy_0_reg_n_0_[7] ),
.I3(Lyy0_carry__0_i_1_n_0),
.O(Lyy0_carry__0_i_5_n_0));
(* HLUTNM = "lutpair16" *)
LUT4 #(
.INIT(16'h9669))
Lyy0_carry__0_i_6
(.I0(Lyy_1[6]),
.I1(\Lyy_2_reg_n_0_[6] ),
.I2(\Lyy_0_reg_n_0_[6] ),
.I3(Lyy0_carry__0_i_2_n_0),
.O(Lyy0_carry__0_i_6_n_0));
(* HLUTNM = "lutpair15" *)
LUT4 #(
.INIT(16'h9669))
Lyy0_carry__0_i_7
(.I0(Lyy_1[5]),
.I1(\Lyy_2_reg_n_0_[5] ),
.I2(\Lyy_0_reg_n_0_[5] ),
.I3(Lyy0_carry__0_i_3_n_0),
.O(Lyy0_carry__0_i_7_n_0));
(* HLUTNM = "lutpair14" *)
LUT4 #(
.INIT(16'h9669))
Lyy0_carry__0_i_8
(.I0(Lyy_1[4]),
.I1(\Lyy_2_reg_n_0_[4] ),
.I2(\Lyy_0_reg_n_0_[4] ),
.I3(Lyy0_carry__0_i_4_n_0),
.O(Lyy0_carry__0_i_8_n_0));
CARRY4 Lyy0_carry__1
(.CI(Lyy0_carry__0_n_0),
.CO({Lyy0_carry__1_n_0,Lyy0_carry__1_n_1,Lyy0_carry__1_n_2,Lyy0_carry__1_n_3}),
.CYINIT(1'b0),
.DI({Lyy0_carry__1_i_1_n_0,Lyy0_carry__1_i_2_n_0,Lyy0_carry__1_i_3_n_0,Lyy0_carry__1_i_4_n_0}),
.O(B[11:8]),
.S({Lyy0_carry__1_i_5_n_0,Lyy0_carry__1_i_6_n_0,Lyy0_carry__1_i_7_n_0,Lyy0_carry__1_i_8_n_0}));
(* HLUTNM = "lutpair20" *)
LUT3 #(
.INIT(8'hD4))
Lyy0_carry__1_i_1
(.I0(Lyy_1[10]),
.I1(\Lyy_2_reg_n_0_[10] ),
.I2(\Lyy_0_reg_n_0_[10] ),
.O(Lyy0_carry__1_i_1_n_0));
(* HLUTNM = "lutpair19" *)
LUT3 #(
.INIT(8'hD4))
Lyy0_carry__1_i_2
(.I0(Lyy_1[9]),
.I1(\Lyy_2_reg_n_0_[9] ),
.I2(\Lyy_0_reg_n_0_[9] ),
.O(Lyy0_carry__1_i_2_n_0));
(* HLUTNM = "lutpair18" *)
LUT3 #(
.INIT(8'hD4))
Lyy0_carry__1_i_3
(.I0(Lyy_1[8]),
.I1(\Lyy_2_reg_n_0_[8] ),
.I2(\Lyy_0_reg_n_0_[8] ),
.O(Lyy0_carry__1_i_3_n_0));
(* HLUTNM = "lutpair17" *)
LUT3 #(
.INIT(8'hD4))
Lyy0_carry__1_i_4
(.I0(Lyy_1[7]),
.I1(\Lyy_2_reg_n_0_[7] ),
.I2(\Lyy_0_reg_n_0_[7] ),
.O(Lyy0_carry__1_i_4_n_0));
(* HLUTNM = "lutpair21" *)
LUT4 #(
.INIT(16'h9669))
Lyy0_carry__1_i_5
(.I0(Lyy_1[11]),
.I1(\Lyy_2_reg_n_0_[11] ),
.I2(\Lyy_0_reg_n_0_[11] ),
.I3(Lyy0_carry__1_i_1_n_0),
.O(Lyy0_carry__1_i_5_n_0));
(* HLUTNM = "lutpair20" *)
LUT4 #(
.INIT(16'h9669))
Lyy0_carry__1_i_6
(.I0(Lyy_1[10]),
.I1(\Lyy_2_reg_n_0_[10] ),
.I2(\Lyy_0_reg_n_0_[10] ),
.I3(Lyy0_carry__1_i_2_n_0),
.O(Lyy0_carry__1_i_6_n_0));
(* HLUTNM = "lutpair19" *)
LUT4 #(
.INIT(16'h9669))
Lyy0_carry__1_i_7
(.I0(Lyy_1[9]),
.I1(\Lyy_2_reg_n_0_[9] ),
.I2(\Lyy_0_reg_n_0_[9] ),
.I3(Lyy0_carry__1_i_3_n_0),
.O(Lyy0_carry__1_i_7_n_0));
(* HLUTNM = "lutpair18" *)
LUT4 #(
.INIT(16'h9669))
Lyy0_carry__1_i_8
(.I0(Lyy_1[8]),
.I1(\Lyy_2_reg_n_0_[8] ),
.I2(\Lyy_0_reg_n_0_[8] ),
.I3(Lyy0_carry__1_i_4_n_0),
.O(Lyy0_carry__1_i_8_n_0));
CARRY4 Lyy0_carry__2
(.CI(Lyy0_carry__1_n_0),
.CO({NLW_Lyy0_carry__2_CO_UNCONNECTED[3],Lyy0_carry__2_n_1,Lyy0_carry__2_n_2,Lyy0_carry__2_n_3}),
.CYINIT(1'b0),
.DI({1'b0,Lyy0_carry__2_i_1_n_0,Lyy0_carry__2_i_2_n_0,Lyy0_carry__2_i_3_n_0}),
.O(B[15:12]),
.S({Lyy0_carry__2_i_4_n_0,Lyy0_carry__2_i_5_n_0,Lyy0_carry__2_i_6_n_0,Lyy0_carry__2_i_7_n_0}));
(* HLUTNM = "lutpair23" *)
LUT3 #(
.INIT(8'hD4))
Lyy0_carry__2_i_1
(.I0(Lyy_1[13]),
.I1(\Lyy_2_reg_n_0_[13] ),
.I2(\Lyy_0_reg_n_0_[13] ),
.O(Lyy0_carry__2_i_1_n_0));
(* HLUTNM = "lutpair22" *)
LUT3 #(
.INIT(8'hD4))
Lyy0_carry__2_i_2
(.I0(Lyy_1[12]),
.I1(\Lyy_2_reg_n_0_[12] ),
.I2(\Lyy_0_reg_n_0_[12] ),
.O(Lyy0_carry__2_i_2_n_0));
(* HLUTNM = "lutpair21" *)
LUT3 #(
.INIT(8'hD4))
Lyy0_carry__2_i_3
(.I0(Lyy_1[11]),
.I1(\Lyy_2_reg_n_0_[11] ),
.I2(\Lyy_0_reg_n_0_[11] ),
.O(Lyy0_carry__2_i_3_n_0));
LUT6 #(
.INIT(64'h8E71718E718E8E71))
Lyy0_carry__2_i_4
(.I0(\Lyy_0_reg_n_0_[14] ),
.I1(\Lyy_2_reg_n_0_[14] ),
.I2(Lyy_1[14]),
.I3(\Lyy_2_reg_n_0_[15] ),
.I4(Lyy_1[15]),
.I5(\Lyy_0_reg_n_0_[15] ),
.O(Lyy0_carry__2_i_4_n_0));
LUT4 #(
.INIT(16'h9669))
Lyy0_carry__2_i_5
(.I0(Lyy0_carry__2_i_1_n_0),
.I1(\Lyy_2_reg_n_0_[14] ),
.I2(Lyy_1[14]),
.I3(\Lyy_0_reg_n_0_[14] ),
.O(Lyy0_carry__2_i_5_n_0));
(* HLUTNM = "lutpair23" *)
LUT4 #(
.INIT(16'h9669))
Lyy0_carry__2_i_6
(.I0(Lyy_1[13]),
.I1(\Lyy_2_reg_n_0_[13] ),
.I2(\Lyy_0_reg_n_0_[13] ),
.I3(Lyy0_carry__2_i_2_n_0),
.O(Lyy0_carry__2_i_6_n_0));
(* HLUTNM = "lutpair22" *)
LUT4 #(
.INIT(16'h9669))
Lyy0_carry__2_i_7
(.I0(Lyy_1[12]),
.I1(\Lyy_2_reg_n_0_[12] ),
.I2(\Lyy_0_reg_n_0_[12] ),
.I3(Lyy0_carry__2_i_3_n_0),
.O(Lyy0_carry__2_i_7_n_0));
(* HLUTNM = "lutpair12" *)
LUT3 #(
.INIT(8'hD4))
Lyy0_carry_i_1
(.I0(Lyy_1[2]),
.I1(\Lyy_2_reg_n_0_[2] ),
.I2(\Lyy_0_reg_n_0_[2] ),
.O(Lyy0_carry_i_1_n_0));
(* HLUTNM = "lutpair25" *)
LUT3 #(
.INIT(8'hD4))
Lyy0_carry_i_2
(.I0(Lyy_1[1]),
.I1(\Lyy_2_reg_n_0_[1] ),
.I2(\Lyy_0_reg_n_0_[1] ),
.O(Lyy0_carry_i_2_n_0));
(* HLUTNM = "lutpair13" *)
LUT4 #(
.INIT(16'h9669))
Lyy0_carry_i_3
(.I0(Lyy_1[3]),
.I1(\Lyy_2_reg_n_0_[3] ),
.I2(\Lyy_0_reg_n_0_[3] ),
.I3(Lyy0_carry_i_1_n_0),
.O(Lyy0_carry_i_3_n_0));
(* HLUTNM = "lutpair12" *)
LUT4 #(
.INIT(16'h9669))
Lyy0_carry_i_4
(.I0(Lyy_1[2]),
.I1(\Lyy_2_reg_n_0_[2] ),
.I2(\Lyy_0_reg_n_0_[2] ),
.I3(Lyy0_carry_i_2_n_0),
.O(Lyy0_carry_i_4_n_0));
(* HLUTNM = "lutpair25" *)
LUT3 #(
.INIT(8'h96))
Lyy0_carry_i_5
(.I0(Lyy_1[1]),
.I1(\Lyy_2_reg_n_0_[1] ),
.I2(\Lyy_0_reg_n_0_[1] ),
.O(Lyy0_carry_i_5_n_0));
LUT2 #(
.INIT(4'h6))
Lyy0_carry_i_6
(.I0(\Lyy_2_reg_n_0_[0] ),
.I1(\Lyy_0_reg_n_0_[0] ),
.O(Lyy0_carry_i_6_n_0));
LUT6 #(
.INIT(64'h0000000000000080))
\Lyy_0[15]_i_1
(.I0(rst),
.I1(active),
.I2(cycle[2]),
.I3(\cycle_reg[1]_rep_n_0 ),
.I4(cycle[3]),
.I5(\cycle_reg[0]_rep_n_0 ),
.O(Lyy_0));
FDRE #(
.INIT(1'b0))
\Lyy_0_reg[0]
(.C(clk_x16),
.CE(Lyy_0),
.D(Lxx_00[0]),
.Q(\Lyy_0_reg_n_0_[0] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lyy_0_reg[10]
(.C(clk_x16),
.CE(Lyy_0),
.D(Lxx_00[10]),
.Q(\Lyy_0_reg_n_0_[10] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lyy_0_reg[11]
(.C(clk_x16),
.CE(Lyy_0),
.D(Lxx_00[11]),
.Q(\Lyy_0_reg_n_0_[11] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lyy_0_reg[12]
(.C(clk_x16),
.CE(Lyy_0),
.D(Lxx_00[12]),
.Q(\Lyy_0_reg_n_0_[12] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lyy_0_reg[13]
(.C(clk_x16),
.CE(Lyy_0),
.D(Lxx_00[13]),
.Q(\Lyy_0_reg_n_0_[13] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lyy_0_reg[14]
(.C(clk_x16),
.CE(Lyy_0),
.D(Lxx_00[14]),
.Q(\Lyy_0_reg_n_0_[14] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lyy_0_reg[15]
(.C(clk_x16),
.CE(Lyy_0),
.D(Lxx_00[15]),
.Q(\Lyy_0_reg_n_0_[15] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lyy_0_reg[1]
(.C(clk_x16),
.CE(Lyy_0),
.D(Lxx_00[1]),
.Q(\Lyy_0_reg_n_0_[1] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lyy_0_reg[2]
(.C(clk_x16),
.CE(Lyy_0),
.D(Lxx_00[2]),
.Q(\Lyy_0_reg_n_0_[2] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lyy_0_reg[3]
(.C(clk_x16),
.CE(Lyy_0),
.D(Lxx_00[3]),
.Q(\Lyy_0_reg_n_0_[3] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lyy_0_reg[4]
(.C(clk_x16),
.CE(Lyy_0),
.D(Lxx_00[4]),
.Q(\Lyy_0_reg_n_0_[4] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lyy_0_reg[5]
(.C(clk_x16),
.CE(Lyy_0),
.D(Lxx_00[5]),
.Q(\Lyy_0_reg_n_0_[5] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lyy_0_reg[6]
(.C(clk_x16),
.CE(Lyy_0),
.D(Lxx_00[6]),
.Q(\Lyy_0_reg_n_0_[6] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lyy_0_reg[7]
(.C(clk_x16),
.CE(Lyy_0),
.D(Lxx_00[7]),
.Q(\Lyy_0_reg_n_0_[7] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lyy_0_reg[8]
(.C(clk_x16),
.CE(Lyy_0),
.D(Lxx_00[8]),
.Q(\Lyy_0_reg_n_0_[8] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lyy_0_reg[9]
(.C(clk_x16),
.CE(Lyy_0),
.D(Lxx_00[9]),
.Q(\Lyy_0_reg_n_0_[9] ),
.R(1'b0));
LUT6 #(
.INIT(64'h0000000040000000))
\Lyy_1[15]_i_1
(.I0(cycle[3]),
.I1(\cycle_reg[2]_rep_n_0 ),
.I2(rst),
.I3(active),
.I4(cycle[0]),
.I5(\cycle_reg[1]_rep__0_n_0 ),
.O(y1));
FDRE #(
.INIT(1'b0))
\Lyy_1_reg[10]
(.C(clk_x16),
.CE(y1),
.D(Lxx_11[9]),
.Q(Lyy_1[10]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lyy_1_reg[11]
(.C(clk_x16),
.CE(y1),
.D(Lxx_11[10]),
.Q(Lyy_1[11]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lyy_1_reg[12]
(.C(clk_x16),
.CE(y1),
.D(Lxx_11[11]),
.Q(Lyy_1[12]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lyy_1_reg[13]
(.C(clk_x16),
.CE(y1),
.D(Lxx_11[12]),
.Q(Lyy_1[13]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lyy_1_reg[14]
(.C(clk_x16),
.CE(y1),
.D(Lxx_11[13]),
.Q(Lyy_1[14]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lyy_1_reg[15]
(.C(clk_x16),
.CE(y1),
.D(Lxx_11[14]),
.Q(Lyy_1[15]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lyy_1_reg[1]
(.C(clk_x16),
.CE(y1),
.D(Lxx_11[0]),
.Q(Lyy_1[1]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lyy_1_reg[2]
(.C(clk_x16),
.CE(y1),
.D(Lxx_11[1]),
.Q(Lyy_1[2]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lyy_1_reg[3]
(.C(clk_x16),
.CE(y1),
.D(Lxx_11[2]),
.Q(Lyy_1[3]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lyy_1_reg[4]
(.C(clk_x16),
.CE(y1),
.D(Lxx_11[3]),
.Q(Lyy_1[4]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lyy_1_reg[5]
(.C(clk_x16),
.CE(y1),
.D(Lxx_11[4]),
.Q(Lyy_1[5]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lyy_1_reg[6]
(.C(clk_x16),
.CE(y1),
.D(Lxx_11[5]),
.Q(Lyy_1[6]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lyy_1_reg[7]
(.C(clk_x16),
.CE(y1),
.D(Lxx_11[6]),
.Q(Lyy_1[7]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lyy_1_reg[8]
(.C(clk_x16),
.CE(y1),
.D(Lxx_11[7]),
.Q(Lyy_1[8]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lyy_1_reg[9]
(.C(clk_x16),
.CE(y1),
.D(Lxx_11[8]),
.Q(Lyy_1[9]),
.R(1'b0));
CARRY4 Lyy_20__1_carry
(.CI(1'b0),
.CO({Lyy_20__1_carry_n_0,Lyy_20__1_carry_n_1,Lyy_20__1_carry_n_2,Lyy_20__1_carry_n_3}),
.CYINIT(1'b0),
.DI({Lyy_20__1_carry_i_1_n_0,Lyy_20__1_carry_i_2_n_0,Lyy_20__1_carry_i_3_n_0,Lyy_2_bottom_right[0]}),
.O(Lyy_20[3:0]),
.S({Lyy_20__1_carry_i_4_n_0,Lyy_20__1_carry_i_5_n_0,Lyy_20__1_carry_i_6_n_0,Lyy_20__1_carry_i_7_n_0}));
CARRY4 Lyy_20__1_carry__0
(.CI(Lyy_20__1_carry_n_0),
.CO({Lyy_20__1_carry__0_n_0,Lyy_20__1_carry__0_n_1,Lyy_20__1_carry__0_n_2,Lyy_20__1_carry__0_n_3}),
.CYINIT(1'b0),
.DI({Lyy_20__1_carry__0_i_1_n_0,Lyy_20__1_carry__0_i_2_n_0,Lyy_20__1_carry__0_i_3_n_0,Lyy_20__1_carry__0_i_4_n_0}),
.O(Lyy_20[7:4]),
.S({Lyy_20__1_carry__0_i_5_n_0,Lyy_20__1_carry__0_i_6_n_0,Lyy_20__1_carry__0_i_7_n_0,Lyy_20__1_carry__0_i_8_n_0}));
LUT5 #(
.INIT(32'hFF969600))
Lyy_20__1_carry__0_i_1
(.I0(Lyy_2_top_left[6]),
.I1(Lyy_2_bottom_left[6]),
.I2(Lyy_2_top_right[6]),
.I3(Lyy_20__1_carry__0_i_9_n_0),
.I4(Lyy_2_bottom_right[6]),
.O(Lyy_20__1_carry__0_i_1_n_0));
(* SOFT_HLUTNM = "soft_lutpair51" *)
LUT3 #(
.INIT(8'h96))
Lyy_20__1_carry__0_i_10
(.I0(Lyy_2_top_left[5]),
.I1(Lyy_2_bottom_left[5]),
.I2(Lyy_2_top_right[5]),
.O(Lyy_20__1_carry__0_i_10_n_0));
(* SOFT_HLUTNM = "soft_lutpair52" *)
LUT3 #(
.INIT(8'h4D))
Lyy_20__1_carry__0_i_11
(.I0(Lyy_2_top_right[3]),
.I1(Lyy_2_top_left[3]),
.I2(Lyy_2_bottom_left[3]),
.O(Lyy_20__1_carry__0_i_11_n_0));
LUT3 #(
.INIT(8'h96))
Lyy_20__1_carry__0_i_12
(.I0(Lyy_2_top_left[7]),
.I1(Lyy_2_bottom_left[7]),
.I2(Lyy_2_top_right[7]),
.O(Lyy_20__1_carry__0_i_12_n_0));
LUT5 #(
.INIT(32'hBAFB20A2))
Lyy_20__1_carry__0_i_2
(.I0(Lyy_2_bottom_right[5]),
.I1(Lyy_2_bottom_left[4]),
.I2(Lyy_2_top_left[4]),
.I3(Lyy_2_top_right[4]),
.I4(Lyy_20__1_carry__0_i_10_n_0),
.O(Lyy_20__1_carry__0_i_2_n_0));
LUT5 #(
.INIT(32'hFF969600))
Lyy_20__1_carry__0_i_3
(.I0(Lyy_2_top_left[4]),
.I1(Lyy_2_bottom_left[4]),
.I2(Lyy_2_top_right[4]),
.I3(Lyy_20__1_carry__0_i_11_n_0),
.I4(Lyy_2_bottom_right[4]),
.O(Lyy_20__1_carry__0_i_3_n_0));
LUT5 #(
.INIT(32'hBAFB20A2))
Lyy_20__1_carry__0_i_4
(.I0(Lyy_2_bottom_right[3]),
.I1(Lyy_2_bottom_left[2]),
.I2(Lyy_2_top_left[2]),
.I3(Lyy_2_top_right[2]),
.I4(Lyy_20__1_carry_i_8_n_0),
.O(Lyy_20__1_carry__0_i_4_n_0));
LUT6 #(
.INIT(64'h9669969669699669))
Lyy_20__1_carry__0_i_5
(.I0(Lyy_20__1_carry__0_i_1_n_0),
.I1(Lyy_20__1_carry__0_i_12_n_0),
.I2(Lyy_2_bottom_right[7]),
.I3(Lyy_2_top_right[6]),
.I4(Lyy_2_top_left[6]),
.I5(Lyy_2_bottom_left[6]),
.O(Lyy_20__1_carry__0_i_5_n_0));
LUT6 #(
.INIT(64'h6996966996696996))
Lyy_20__1_carry__0_i_6
(.I0(Lyy_20__1_carry__0_i_2_n_0),
.I1(Lyy_2_top_right[6]),
.I2(Lyy_2_bottom_left[6]),
.I3(Lyy_2_top_left[6]),
.I4(Lyy_2_bottom_right[6]),
.I5(Lyy_20__1_carry__0_i_9_n_0),
.O(Lyy_20__1_carry__0_i_6_n_0));
LUT6 #(
.INIT(64'h9669969669699669))
Lyy_20__1_carry__0_i_7
(.I0(Lyy_20__1_carry__0_i_3_n_0),
.I1(Lyy_20__1_carry__0_i_10_n_0),
.I2(Lyy_2_bottom_right[5]),
.I3(Lyy_2_top_right[4]),
.I4(Lyy_2_top_left[4]),
.I5(Lyy_2_bottom_left[4]),
.O(Lyy_20__1_carry__0_i_7_n_0));
LUT6 #(
.INIT(64'h6996966996696996))
Lyy_20__1_carry__0_i_8
(.I0(Lyy_20__1_carry__0_i_4_n_0),
.I1(Lyy_2_top_right[4]),
.I2(Lyy_2_bottom_left[4]),
.I3(Lyy_2_top_left[4]),
.I4(Lyy_2_bottom_right[4]),
.I5(Lyy_20__1_carry__0_i_11_n_0),
.O(Lyy_20__1_carry__0_i_8_n_0));
(* SOFT_HLUTNM = "soft_lutpair51" *)
LUT3 #(
.INIT(8'h4D))
Lyy_20__1_carry__0_i_9
(.I0(Lyy_2_top_right[5]),
.I1(Lyy_2_top_left[5]),
.I2(Lyy_2_bottom_left[5]),
.O(Lyy_20__1_carry__0_i_9_n_0));
CARRY4 Lyy_20__1_carry__1
(.CI(Lyy_20__1_carry__0_n_0),
.CO({Lyy_20__1_carry__1_n_0,Lyy_20__1_carry__1_n_1,Lyy_20__1_carry__1_n_2,Lyy_20__1_carry__1_n_3}),
.CYINIT(1'b0),
.DI({Lyy_20__1_carry__1_i_1_n_0,Lyy_20__1_carry__1_i_2_n_0,Lyy_20__1_carry__1_i_3_n_0,Lyy_20__1_carry__1_i_4_n_0}),
.O(Lyy_20[11:8]),
.S({Lyy_20__1_carry__1_i_5_n_0,Lyy_20__1_carry__1_i_6_n_0,Lyy_20__1_carry__1_i_7_n_0,Lyy_20__1_carry__1_i_8_n_0}));
LUT5 #(
.INIT(32'hFF969600))
Lyy_20__1_carry__1_i_1
(.I0(Lyy_2_top_left[10]),
.I1(Lyy_2_bottom_left[10]),
.I2(Lyy_2_top_right[10]),
.I3(Lyy_20__1_carry__1_i_9_n_0),
.I4(Lyy_2_bottom_right[10]),
.O(Lyy_20__1_carry__1_i_1_n_0));
(* SOFT_HLUTNM = "soft_lutpair50" *)
LUT3 #(
.INIT(8'h96))
Lyy_20__1_carry__1_i_10
(.I0(Lyy_2_top_left[9]),
.I1(Lyy_2_bottom_left[9]),
.I2(Lyy_2_top_right[9]),
.O(Lyy_20__1_carry__1_i_10_n_0));
LUT3 #(
.INIT(8'h96))
Lyy_20__1_carry__1_i_11
(.I0(Lyy_2_top_left[8]),
.I1(Lyy_2_bottom_left[8]),
.I2(Lyy_2_top_right[8]),
.O(Lyy_20__1_carry__1_i_11_n_0));
LUT3 #(
.INIT(8'h4D))
Lyy_20__1_carry__1_i_12
(.I0(Lyy_2_top_right[10]),
.I1(Lyy_2_top_left[10]),
.I2(Lyy_2_bottom_left[10]),
.O(Lyy_20__1_carry__1_i_12_n_0));
LUT5 #(
.INIT(32'hBAFB20A2))
Lyy_20__1_carry__1_i_2
(.I0(Lyy_2_bottom_right[9]),
.I1(Lyy_2_bottom_left[8]),
.I2(Lyy_2_top_left[8]),
.I3(Lyy_2_top_right[8]),
.I4(Lyy_20__1_carry__1_i_10_n_0),
.O(Lyy_20__1_carry__1_i_2_n_0));
LUT5 #(
.INIT(32'hBAFB20A2))
Lyy_20__1_carry__1_i_3
(.I0(Lyy_2_bottom_right[8]),
.I1(Lyy_2_bottom_left[7]),
.I2(Lyy_2_top_left[7]),
.I3(Lyy_2_top_right[7]),
.I4(Lyy_20__1_carry__1_i_11_n_0),
.O(Lyy_20__1_carry__1_i_3_n_0));
LUT5 #(
.INIT(32'hBAFB20A2))
Lyy_20__1_carry__1_i_4
(.I0(Lyy_2_bottom_right[7]),
.I1(Lyy_2_bottom_left[6]),
.I2(Lyy_2_top_left[6]),
.I3(Lyy_2_top_right[6]),
.I4(Lyy_20__1_carry__0_i_12_n_0),
.O(Lyy_20__1_carry__1_i_4_n_0));
LUT6 #(
.INIT(64'h6996966996696996))
Lyy_20__1_carry__1_i_5
(.I0(Lyy_20__1_carry__1_i_1_n_0),
.I1(Lyy_2_top_right[11]),
.I2(Lyy_2_bottom_left[11]),
.I3(Lyy_2_top_left[11]),
.I4(Lyy_2_bottom_right[11]),
.I5(Lyy_20__1_carry__1_i_12_n_0),
.O(Lyy_20__1_carry__1_i_5_n_0));
LUT6 #(
.INIT(64'h6996966996696996))
Lyy_20__1_carry__1_i_6
(.I0(Lyy_20__1_carry__1_i_2_n_0),
.I1(Lyy_2_top_right[10]),
.I2(Lyy_2_bottom_left[10]),
.I3(Lyy_2_top_left[10]),
.I4(Lyy_2_bottom_right[10]),
.I5(Lyy_20__1_carry__1_i_9_n_0),
.O(Lyy_20__1_carry__1_i_6_n_0));
LUT6 #(
.INIT(64'h9669969669699669))
Lyy_20__1_carry__1_i_7
(.I0(Lyy_20__1_carry__1_i_3_n_0),
.I1(Lyy_20__1_carry__1_i_10_n_0),
.I2(Lyy_2_bottom_right[9]),
.I3(Lyy_2_top_right[8]),
.I4(Lyy_2_top_left[8]),
.I5(Lyy_2_bottom_left[8]),
.O(Lyy_20__1_carry__1_i_7_n_0));
LUT6 #(
.INIT(64'h9669969669699669))
Lyy_20__1_carry__1_i_8
(.I0(Lyy_20__1_carry__1_i_4_n_0),
.I1(Lyy_20__1_carry__1_i_11_n_0),
.I2(Lyy_2_bottom_right[8]),
.I3(Lyy_2_top_right[7]),
.I4(Lyy_2_top_left[7]),
.I5(Lyy_2_bottom_left[7]),
.O(Lyy_20__1_carry__1_i_8_n_0));
(* SOFT_HLUTNM = "soft_lutpair50" *)
LUT3 #(
.INIT(8'h4D))
Lyy_20__1_carry__1_i_9
(.I0(Lyy_2_top_right[9]),
.I1(Lyy_2_top_left[9]),
.I2(Lyy_2_bottom_left[9]),
.O(Lyy_20__1_carry__1_i_9_n_0));
CARRY4 Lyy_20__1_carry__2
(.CI(Lyy_20__1_carry__1_n_0),
.CO({NLW_Lyy_20__1_carry__2_CO_UNCONNECTED[3],Lyy_20__1_carry__2_n_1,Lyy_20__1_carry__2_n_2,Lyy_20__1_carry__2_n_3}),
.CYINIT(1'b0),
.DI({1'b0,Lyy_20__1_carry__2_i_1_n_0,Lyy_20__1_carry__2_i_2_n_0,Lyy_20__1_carry__2_i_3_n_0}),
.O(Lyy_20[15:12]),
.S({Lyy_20__1_carry__2_i_4_n_0,Lyy_20__1_carry__2_i_5_n_0,Lyy_20__1_carry__2_i_6_n_0,Lyy_20__1_carry__2_i_7_n_0}));
LUT5 #(
.INIT(32'hBAFB20A2))
Lyy_20__1_carry__2_i_1
(.I0(Lyy_2_bottom_right[13]),
.I1(Lyy_2_top_right[12]),
.I2(Lyy_2_top_left[12]),
.I3(Lyy_2_bottom_left[12]),
.I4(Lyy_20__1_carry__2_i_8_n_0),
.O(Lyy_20__1_carry__2_i_1_n_0));
(* SOFT_HLUTNM = "soft_lutpair49" *)
LUT3 #(
.INIT(8'h2B))
Lyy_20__1_carry__2_i_10
(.I0(Lyy_2_top_left[13]),
.I1(Lyy_2_bottom_left[13]),
.I2(Lyy_2_top_right[13]),
.O(Lyy_20__1_carry__2_i_10_n_0));
LUT4 #(
.INIT(16'h6996))
Lyy_20__1_carry__2_i_11
(.I0(Lyy_2_top_right[15]),
.I1(Lyy_2_bottom_left[15]),
.I2(Lyy_2_top_left[15]),
.I3(Lyy_2_bottom_right[15]),
.O(Lyy_20__1_carry__2_i_11_n_0));
LUT5 #(
.INIT(32'hBAFB20A2))
Lyy_20__1_carry__2_i_2
(.I0(Lyy_2_bottom_right[12]),
.I1(Lyy_2_bottom_left[11]),
.I2(Lyy_2_top_left[11]),
.I3(Lyy_2_top_right[11]),
.I4(Lyy_20__1_carry__2_i_9_n_0),
.O(Lyy_20__1_carry__2_i_2_n_0));
LUT5 #(
.INIT(32'hFF969600))
Lyy_20__1_carry__2_i_3
(.I0(Lyy_2_top_left[11]),
.I1(Lyy_2_bottom_left[11]),
.I2(Lyy_2_top_right[11]),
.I3(Lyy_20__1_carry__1_i_12_n_0),
.I4(Lyy_2_bottom_right[11]),
.O(Lyy_20__1_carry__2_i_3_n_0));
LUT6 #(
.INIT(64'h1E78871E871EE187))
Lyy_20__1_carry__2_i_4
(.I0(Lyy_2_bottom_right[14]),
.I1(Lyy_20__1_carry__2_i_10_n_0),
.I2(Lyy_20__1_carry__2_i_11_n_0),
.I3(Lyy_2_top_left[14]),
.I4(Lyy_2_bottom_left[14]),
.I5(Lyy_2_top_right[14]),
.O(Lyy_20__1_carry__2_i_4_n_0));
LUT6 #(
.INIT(64'h6996966996696996))
Lyy_20__1_carry__2_i_5
(.I0(Lyy_20__1_carry__2_i_1_n_0),
.I1(Lyy_2_top_right[14]),
.I2(Lyy_2_bottom_left[14]),
.I3(Lyy_2_top_left[14]),
.I4(Lyy_2_bottom_right[14]),
.I5(Lyy_20__1_carry__2_i_10_n_0),
.O(Lyy_20__1_carry__2_i_5_n_0));
LUT6 #(
.INIT(64'h9669969669699669))
Lyy_20__1_carry__2_i_6
(.I0(Lyy_20__1_carry__2_i_2_n_0),
.I1(Lyy_20__1_carry__2_i_8_n_0),
.I2(Lyy_2_bottom_right[13]),
.I3(Lyy_2_bottom_left[12]),
.I4(Lyy_2_top_left[12]),
.I5(Lyy_2_top_right[12]),
.O(Lyy_20__1_carry__2_i_6_n_0));
LUT6 #(
.INIT(64'h9669969669699669))
Lyy_20__1_carry__2_i_7
(.I0(Lyy_20__1_carry__2_i_3_n_0),
.I1(Lyy_20__1_carry__2_i_9_n_0),
.I2(Lyy_2_bottom_right[12]),
.I3(Lyy_2_top_right[11]),
.I4(Lyy_2_top_left[11]),
.I5(Lyy_2_bottom_left[11]),
.O(Lyy_20__1_carry__2_i_7_n_0));
(* SOFT_HLUTNM = "soft_lutpair49" *)
LUT3 #(
.INIT(8'h96))
Lyy_20__1_carry__2_i_8
(.I0(Lyy_2_top_left[13]),
.I1(Lyy_2_bottom_left[13]),
.I2(Lyy_2_top_right[13]),
.O(Lyy_20__1_carry__2_i_8_n_0));
LUT3 #(
.INIT(8'h96))
Lyy_20__1_carry__2_i_9
(.I0(Lyy_2_top_left[12]),
.I1(Lyy_2_bottom_left[12]),
.I2(Lyy_2_top_right[12]),
.O(Lyy_20__1_carry__2_i_9_n_0));
LUT6 #(
.INIT(64'h96FFFFFF00969696))
Lyy_20__1_carry_i_1
(.I0(Lyy_2_top_left[2]),
.I1(Lyy_2_bottom_left[2]),
.I2(Lyy_2_top_right[2]),
.I3(Lyy_2_top_right[1]),
.I4(Lyy_2_bottom_left[1]),
.I5(Lyy_2_bottom_right[2]),
.O(Lyy_20__1_carry_i_1_n_0));
LUT4 #(
.INIT(16'hF990))
Lyy_20__1_carry_i_2
(.I0(Lyy_2_top_right[1]),
.I1(Lyy_2_bottom_left[1]),
.I2(Lyy_2_top_left[1]),
.I3(Lyy_2_bottom_right[1]),
.O(Lyy_20__1_carry_i_2_n_0));
LUT4 #(
.INIT(16'h9669))
Lyy_20__1_carry_i_3
(.I0(Lyy_2_bottom_left[1]),
.I1(Lyy_2_top_right[1]),
.I2(Lyy_2_top_left[1]),
.I3(Lyy_2_bottom_right[1]),
.O(Lyy_20__1_carry_i_3_n_0));
LUT6 #(
.INIT(64'h9669969669699669))
Lyy_20__1_carry_i_4
(.I0(Lyy_20__1_carry_i_1_n_0),
.I1(Lyy_20__1_carry_i_8_n_0),
.I2(Lyy_2_bottom_right[3]),
.I3(Lyy_2_top_right[2]),
.I4(Lyy_2_top_left[2]),
.I5(Lyy_2_bottom_left[2]),
.O(Lyy_20__1_carry_i_4_n_0));
LUT6 #(
.INIT(64'h6996966996696996))
Lyy_20__1_carry_i_5
(.I0(Lyy_20__1_carry_i_2_n_0),
.I1(Lyy_2_top_right[2]),
.I2(Lyy_2_bottom_left[2]),
.I3(Lyy_2_top_left[2]),
.I4(Lyy_2_bottom_right[2]),
.I5(Lyy_20__1_carry_i_9_n_0),
.O(Lyy_20__1_carry_i_5_n_0));
LUT4 #(
.INIT(16'h9A59))
Lyy_20__1_carry_i_6
(.I0(Lyy_20__1_carry_i_3_n_0),
.I1(Lyy_2_bottom_left[0]),
.I2(Lyy_2_top_left[0]),
.I3(Lyy_2_top_right[0]),
.O(Lyy_20__1_carry_i_6_n_0));
LUT4 #(
.INIT(16'h6996))
Lyy_20__1_carry_i_7
(.I0(Lyy_2_top_right[0]),
.I1(Lyy_2_bottom_left[0]),
.I2(Lyy_2_top_left[0]),
.I3(Lyy_2_bottom_right[0]),
.O(Lyy_20__1_carry_i_7_n_0));
(* SOFT_HLUTNM = "soft_lutpair52" *)
LUT3 #(
.INIT(8'h96))
Lyy_20__1_carry_i_8
(.I0(Lyy_2_top_left[3]),
.I1(Lyy_2_bottom_left[3]),
.I2(Lyy_2_top_right[3]),
.O(Lyy_20__1_carry_i_8_n_0));
LUT2 #(
.INIT(4'h7))
Lyy_20__1_carry_i_9
(.I0(Lyy_2_bottom_left[1]),
.I1(Lyy_2_top_right[1]),
.O(Lyy_20__1_carry_i_9_n_0));
LUT6 #(
.INIT(64'h0020000000000000))
\Lyy_2[15]_i_1
(.I0(\cycle_reg[1]_rep_n_0 ),
.I1(\cycle_reg[0]_rep_n_0 ),
.I2(cycle[2]),
.I3(cycle[3]),
.I4(rst),
.I5(active),
.O(\Lyy_2[15]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\Lyy_2_bottom_left_reg[0]
(.C(clk_x16),
.CE(y5),
.D(\cache_reg[4]_0 [0]),
.Q(Lyy_2_bottom_left[0]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lyy_2_bottom_left_reg[10]
(.C(clk_x16),
.CE(y5),
.D(\cache_reg[4]_0 [10]),
.Q(Lyy_2_bottom_left[10]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lyy_2_bottom_left_reg[11]
(.C(clk_x16),
.CE(y5),
.D(\cache_reg[4]_0 [11]),
.Q(Lyy_2_bottom_left[11]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lyy_2_bottom_left_reg[12]
(.C(clk_x16),
.CE(y5),
.D(\cache_reg[4]_0 [12]),
.Q(Lyy_2_bottom_left[12]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lyy_2_bottom_left_reg[13]
(.C(clk_x16),
.CE(y5),
.D(\cache_reg[4]_0 [13]),
.Q(Lyy_2_bottom_left[13]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lyy_2_bottom_left_reg[14]
(.C(clk_x16),
.CE(y5),
.D(\cache_reg[4]_0 [14]),
.Q(Lyy_2_bottom_left[14]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lyy_2_bottom_left_reg[15]
(.C(clk_x16),
.CE(y5),
.D(\cache_reg[4]_0 [15]),
.Q(Lyy_2_bottom_left[15]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lyy_2_bottom_left_reg[1]
(.C(clk_x16),
.CE(y5),
.D(\cache_reg[4]_0 [1]),
.Q(Lyy_2_bottom_left[1]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lyy_2_bottom_left_reg[2]
(.C(clk_x16),
.CE(y5),
.D(\cache_reg[4]_0 [2]),
.Q(Lyy_2_bottom_left[2]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lyy_2_bottom_left_reg[3]
(.C(clk_x16),
.CE(y5),
.D(\cache_reg[4]_0 [3]),
.Q(Lyy_2_bottom_left[3]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lyy_2_bottom_left_reg[4]
(.C(clk_x16),
.CE(y5),
.D(\cache_reg[4]_0 [4]),
.Q(Lyy_2_bottom_left[4]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lyy_2_bottom_left_reg[5]
(.C(clk_x16),
.CE(y5),
.D(\cache_reg[4]_0 [5]),
.Q(Lyy_2_bottom_left[5]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lyy_2_bottom_left_reg[6]
(.C(clk_x16),
.CE(y5),
.D(\cache_reg[4]_0 [6]),
.Q(Lyy_2_bottom_left[6]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lyy_2_bottom_left_reg[7]
(.C(clk_x16),
.CE(y5),
.D(\cache_reg[4]_0 [7]),
.Q(Lyy_2_bottom_left[7]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lyy_2_bottom_left_reg[8]
(.C(clk_x16),
.CE(y5),
.D(\cache_reg[4]_0 [8]),
.Q(Lyy_2_bottom_left[8]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lyy_2_bottom_left_reg[9]
(.C(clk_x16),
.CE(y5),
.D(\cache_reg[4]_0 [9]),
.Q(Lyy_2_bottom_left[9]),
.R(1'b0));
CARRY4 Lyy_2_bottom_right0__0_carry
(.CI(1'b0),
.CO({Lyy_2_bottom_right0__0_carry_n_0,Lyy_2_bottom_right0__0_carry_n_1,Lyy_2_bottom_right0__0_carry_n_2,Lyy_2_bottom_right0__0_carry_n_3}),
.CYINIT(1'b0),
.DI({Lyy_2_bottom_right0__0_carry_i_1_n_0,Lyy_2_bottom_right0__0_carry_i_2_n_0,Lyy_2_bottom_right0__0_carry_i_3_n_0,Lyy_2_bottom_right0__0_carry_i_4_n_0}),
.O(Lyy_2_bottom_right01_out[3:0]),
.S({Lyy_2_bottom_right0__0_carry_i_5_n_0,Lyy_2_bottom_right0__0_carry_i_6_n_0,Lyy_2_bottom_right0__0_carry_i_7_n_0,Lyy_2_bottom_right0__0_carry_i_8_n_0}));
CARRY4 Lyy_2_bottom_right0__0_carry__0
(.CI(Lyy_2_bottom_right0__0_carry_n_0),
.CO({Lyy_2_bottom_right0__0_carry__0_n_0,Lyy_2_bottom_right0__0_carry__0_n_1,Lyy_2_bottom_right0__0_carry__0_n_2,Lyy_2_bottom_right0__0_carry__0_n_3}),
.CYINIT(1'b0),
.DI({Lyy_2_bottom_right0__0_carry__0_i_1_n_0,Lyy_2_bottom_right0__0_carry__0_i_2_n_0,Lyy_2_bottom_right0__0_carry__0_i_3_n_0,Lyy_2_bottom_right0__0_carry__0_i_4_n_0}),
.O(Lyy_2_bottom_right01_out[7:4]),
.S({Lyy_2_bottom_right0__0_carry__0_i_5_n_0,Lyy_2_bottom_right0__0_carry__0_i_6_n_0,Lyy_2_bottom_right0__0_carry__0_i_7_n_0,Lyy_2_bottom_right0__0_carry__0_i_8_n_0}));
LUT5 #(
.INIT(32'hEE8E8E88))
Lyy_2_bottom_right0__0_carry__0_i_1
(.I0(last_value[6]),
.I1(Lyy_2_bottom_right0__0_carry__0_i_9_n_0),
.I2(\corner_reg_n_0_[5] ),
.I3(\top_reg_n_0_[5] ),
.I4(\left_reg_n_0_[5] ),
.O(Lyy_2_bottom_right0__0_carry__0_i_1_n_0));
LUT3 #(
.INIT(8'h69))
Lyy_2_bottom_right0__0_carry__0_i_10
(.I0(\corner_reg_n_0_[5] ),
.I1(\left_reg_n_0_[5] ),
.I2(\top_reg_n_0_[5] ),
.O(Lyy_2_bottom_right0__0_carry__0_i_10_n_0));
LUT3 #(
.INIT(8'h69))
Lyy_2_bottom_right0__0_carry__0_i_11
(.I0(\corner_reg_n_0_[4] ),
.I1(\left_reg_n_0_[4] ),
.I2(\top_reg_n_0_[4] ),
.O(Lyy_2_bottom_right0__0_carry__0_i_11_n_0));
LUT3 #(
.INIT(8'h69))
Lyy_2_bottom_right0__0_carry__0_i_12
(.I0(\corner_reg_n_0_[7] ),
.I1(\left_reg_n_0_[7] ),
.I2(\top_reg_n_0_[7] ),
.O(Lyy_2_bottom_right0__0_carry__0_i_12_n_0));
LUT5 #(
.INIT(32'hEE8E8E88))
Lyy_2_bottom_right0__0_carry__0_i_2
(.I0(last_value[5]),
.I1(Lyy_2_bottom_right0__0_carry__0_i_10_n_0),
.I2(\corner_reg_n_0_[4] ),
.I3(\top_reg_n_0_[4] ),
.I4(\left_reg_n_0_[4] ),
.O(Lyy_2_bottom_right0__0_carry__0_i_2_n_0));
LUT5 #(
.INIT(32'hEE8E8E88))
Lyy_2_bottom_right0__0_carry__0_i_3
(.I0(last_value[4]),
.I1(Lyy_2_bottom_right0__0_carry__0_i_11_n_0),
.I2(\corner_reg_n_0_[3] ),
.I3(\top_reg_n_0_[3] ),
.I4(\left_reg_n_0_[3] ),
.O(Lyy_2_bottom_right0__0_carry__0_i_3_n_0));
LUT5 #(
.INIT(32'hEE8E8E88))
Lyy_2_bottom_right0__0_carry__0_i_4
(.I0(last_value[3]),
.I1(Lyy_2_bottom_right0__0_carry_i_10_n_0),
.I2(\corner_reg_n_0_[2] ),
.I3(\top_reg_n_0_[2] ),
.I4(\left_reg_n_0_[2] ),
.O(Lyy_2_bottom_right0__0_carry__0_i_4_n_0));
LUT6 #(
.INIT(64'h6996969669696996))
Lyy_2_bottom_right0__0_carry__0_i_5
(.I0(Lyy_2_bottom_right0__0_carry__0_i_1_n_0),
.I1(Lyy_2_bottom_right0__0_carry__0_i_12_n_0),
.I2(last_value[7]),
.I3(\left_reg_n_0_[6] ),
.I4(\top_reg_n_0_[6] ),
.I5(\corner_reg_n_0_[6] ),
.O(Lyy_2_bottom_right0__0_carry__0_i_5_n_0));
LUT6 #(
.INIT(64'h6996969669696996))
Lyy_2_bottom_right0__0_carry__0_i_6
(.I0(Lyy_2_bottom_right0__0_carry__0_i_2_n_0),
.I1(Lyy_2_bottom_right0__0_carry__0_i_9_n_0),
.I2(last_value[6]),
.I3(\left_reg_n_0_[5] ),
.I4(\top_reg_n_0_[5] ),
.I5(\corner_reg_n_0_[5] ),
.O(Lyy_2_bottom_right0__0_carry__0_i_6_n_0));
LUT6 #(
.INIT(64'h6996969669696996))
Lyy_2_bottom_right0__0_carry__0_i_7
(.I0(Lyy_2_bottom_right0__0_carry__0_i_3_n_0),
.I1(Lyy_2_bottom_right0__0_carry__0_i_10_n_0),
.I2(last_value[5]),
.I3(\left_reg_n_0_[4] ),
.I4(\top_reg_n_0_[4] ),
.I5(\corner_reg_n_0_[4] ),
.O(Lyy_2_bottom_right0__0_carry__0_i_7_n_0));
LUT6 #(
.INIT(64'h6996969669696996))
Lyy_2_bottom_right0__0_carry__0_i_8
(.I0(Lyy_2_bottom_right0__0_carry__0_i_4_n_0),
.I1(Lyy_2_bottom_right0__0_carry__0_i_11_n_0),
.I2(last_value[4]),
.I3(\left_reg_n_0_[3] ),
.I4(\top_reg_n_0_[3] ),
.I5(\corner_reg_n_0_[3] ),
.O(Lyy_2_bottom_right0__0_carry__0_i_8_n_0));
LUT3 #(
.INIT(8'h69))
Lyy_2_bottom_right0__0_carry__0_i_9
(.I0(\corner_reg_n_0_[6] ),
.I1(\left_reg_n_0_[6] ),
.I2(\top_reg_n_0_[6] ),
.O(Lyy_2_bottom_right0__0_carry__0_i_9_n_0));
CARRY4 Lyy_2_bottom_right0__0_carry__1
(.CI(Lyy_2_bottom_right0__0_carry__0_n_0),
.CO({Lyy_2_bottom_right0__0_carry__1_n_0,Lyy_2_bottom_right0__0_carry__1_n_1,Lyy_2_bottom_right0__0_carry__1_n_2,Lyy_2_bottom_right0__0_carry__1_n_3}),
.CYINIT(1'b0),
.DI({Lyy_2_bottom_right0__0_carry__1_i_1_n_0,Lyy_2_bottom_right0__0_carry__1_i_2_n_0,Lyy_2_bottom_right0__0_carry__1_i_3_n_0,Lyy_2_bottom_right0__0_carry__1_i_4_n_0}),
.O(Lyy_2_bottom_right01_out[11:8]),
.S({Lyy_2_bottom_right0__0_carry__1_i_5_n_0,Lyy_2_bottom_right0__0_carry__1_i_6_n_0,Lyy_2_bottom_right0__0_carry__1_i_7_n_0,Lyy_2_bottom_right0__0_carry__1_i_8_n_0}));
LUT6 #(
.INIT(64'h6969006900690000))
Lyy_2_bottom_right0__0_carry__1_i_1
(.I0(\top_reg_n_0_[10] ),
.I1(\left_reg_n_0_[10] ),
.I2(\corner_reg_n_0_[10] ),
.I3(\corner_reg_n_0_[9] ),
.I4(\top_reg_n_0_[9] ),
.I5(\left_reg_n_0_[9] ),
.O(Lyy_2_bottom_right0__0_carry__1_i_1_n_0));
LUT3 #(
.INIT(8'h69))
Lyy_2_bottom_right0__0_carry__1_i_10
(.I0(\corner_reg_n_0_[10] ),
.I1(\left_reg_n_0_[10] ),
.I2(\top_reg_n_0_[10] ),
.O(Lyy_2_bottom_right0__0_carry__1_i_10_n_0));
LUT3 #(
.INIT(8'h69))
Lyy_2_bottom_right0__0_carry__1_i_11
(.I0(\corner_reg_n_0_[9] ),
.I1(\left_reg_n_0_[9] ),
.I2(\top_reg_n_0_[9] ),
.O(Lyy_2_bottom_right0__0_carry__1_i_11_n_0));
LUT3 #(
.INIT(8'h69))
Lyy_2_bottom_right0__0_carry__1_i_12
(.I0(\corner_reg_n_0_[8] ),
.I1(\left_reg_n_0_[8] ),
.I2(\top_reg_n_0_[8] ),
.O(Lyy_2_bottom_right0__0_carry__1_i_12_n_0));
LUT6 #(
.INIT(64'h6969006900690000))
Lyy_2_bottom_right0__0_carry__1_i_2
(.I0(\top_reg_n_0_[9] ),
.I1(\left_reg_n_0_[9] ),
.I2(\corner_reg_n_0_[9] ),
.I3(\corner_reg_n_0_[8] ),
.I4(\top_reg_n_0_[8] ),
.I5(\left_reg_n_0_[8] ),
.O(Lyy_2_bottom_right0__0_carry__1_i_2_n_0));
LUT6 #(
.INIT(64'h6969006900690000))
Lyy_2_bottom_right0__0_carry__1_i_3
(.I0(\top_reg_n_0_[8] ),
.I1(\left_reg_n_0_[8] ),
.I2(\corner_reg_n_0_[8] ),
.I3(\corner_reg_n_0_[7] ),
.I4(\top_reg_n_0_[7] ),
.I5(\left_reg_n_0_[7] ),
.O(Lyy_2_bottom_right0__0_carry__1_i_3_n_0));
LUT5 #(
.INIT(32'hEE8E8E88))
Lyy_2_bottom_right0__0_carry__1_i_4
(.I0(last_value[7]),
.I1(Lyy_2_bottom_right0__0_carry__0_i_12_n_0),
.I2(\corner_reg_n_0_[6] ),
.I3(\top_reg_n_0_[6] ),
.I4(\left_reg_n_0_[6] ),
.O(Lyy_2_bottom_right0__0_carry__1_i_4_n_0));
LUT5 #(
.INIT(32'h96669996))
Lyy_2_bottom_right0__0_carry__1_i_5
(.I0(Lyy_2_bottom_right0__0_carry__1_i_1_n_0),
.I1(Lyy_2_bottom_right0__0_carry__1_i_9_n_0),
.I2(\left_reg_n_0_[10] ),
.I3(\top_reg_n_0_[10] ),
.I4(\corner_reg_n_0_[10] ),
.O(Lyy_2_bottom_right0__0_carry__1_i_5_n_0));
LUT5 #(
.INIT(32'h96669996))
Lyy_2_bottom_right0__0_carry__1_i_6
(.I0(Lyy_2_bottom_right0__0_carry__1_i_2_n_0),
.I1(Lyy_2_bottom_right0__0_carry__1_i_10_n_0),
.I2(\left_reg_n_0_[9] ),
.I3(\top_reg_n_0_[9] ),
.I4(\corner_reg_n_0_[9] ),
.O(Lyy_2_bottom_right0__0_carry__1_i_6_n_0));
LUT5 #(
.INIT(32'h96669996))
Lyy_2_bottom_right0__0_carry__1_i_7
(.I0(Lyy_2_bottom_right0__0_carry__1_i_3_n_0),
.I1(Lyy_2_bottom_right0__0_carry__1_i_11_n_0),
.I2(\left_reg_n_0_[8] ),
.I3(\top_reg_n_0_[8] ),
.I4(\corner_reg_n_0_[8] ),
.O(Lyy_2_bottom_right0__0_carry__1_i_7_n_0));
LUT5 #(
.INIT(32'h96669996))
Lyy_2_bottom_right0__0_carry__1_i_8
(.I0(Lyy_2_bottom_right0__0_carry__1_i_4_n_0),
.I1(Lyy_2_bottom_right0__0_carry__1_i_12_n_0),
.I2(\left_reg_n_0_[7] ),
.I3(\top_reg_n_0_[7] ),
.I4(\corner_reg_n_0_[7] ),
.O(Lyy_2_bottom_right0__0_carry__1_i_8_n_0));
LUT3 #(
.INIT(8'h69))
Lyy_2_bottom_right0__0_carry__1_i_9
(.I0(\corner_reg_n_0_[11] ),
.I1(\left_reg_n_0_[11] ),
.I2(\top_reg_n_0_[11] ),
.O(Lyy_2_bottom_right0__0_carry__1_i_9_n_0));
CARRY4 Lyy_2_bottom_right0__0_carry__2
(.CI(Lyy_2_bottom_right0__0_carry__1_n_0),
.CO({NLW_Lyy_2_bottom_right0__0_carry__2_CO_UNCONNECTED[3],Lyy_2_bottom_right0__0_carry__2_n_1,Lyy_2_bottom_right0__0_carry__2_n_2,Lyy_2_bottom_right0__0_carry__2_n_3}),
.CYINIT(1'b0),
.DI({1'b0,Lyy_2_bottom_right0__0_carry__2_i_1_n_0,Lyy_2_bottom_right0__0_carry__2_i_2_n_0,Lyy_2_bottom_right0__0_carry__2_i_3_n_0}),
.O(Lyy_2_bottom_right01_out[15:12]),
.S({Lyy_2_bottom_right0__0_carry__2_i_4_n_0,Lyy_2_bottom_right0__0_carry__2_i_5_n_0,Lyy_2_bottom_right0__0_carry__2_i_6_n_0,Lyy_2_bottom_right0__0_carry__2_i_7_n_0}));
LUT6 #(
.INIT(64'h6969006900690000))
Lyy_2_bottom_right0__0_carry__2_i_1
(.I0(\top_reg_n_0_[13] ),
.I1(\left_reg_n_0_[13] ),
.I2(\corner_reg_n_0_[13] ),
.I3(\corner_reg_n_0_[12] ),
.I4(\top_reg_n_0_[12] ),
.I5(\left_reg_n_0_[12] ),
.O(Lyy_2_bottom_right0__0_carry__2_i_1_n_0));
LUT3 #(
.INIT(8'h69))
Lyy_2_bottom_right0__0_carry__2_i_10
(.I0(\corner_reg_n_0_[14] ),
.I1(\left_reg_n_0_[14] ),
.I2(\top_reg_n_0_[14] ),
.O(Lyy_2_bottom_right0__0_carry__2_i_10_n_0));
(* SOFT_HLUTNM = "soft_lutpair33" *)
LUT3 #(
.INIT(8'h69))
Lyy_2_bottom_right0__0_carry__2_i_11
(.I0(\corner_reg_n_0_[13] ),
.I1(\left_reg_n_0_[13] ),
.I2(\top_reg_n_0_[13] ),
.O(Lyy_2_bottom_right0__0_carry__2_i_11_n_0));
LUT3 #(
.INIT(8'h69))
Lyy_2_bottom_right0__0_carry__2_i_12
(.I0(\corner_reg_n_0_[12] ),
.I1(\left_reg_n_0_[12] ),
.I2(\top_reg_n_0_[12] ),
.O(Lyy_2_bottom_right0__0_carry__2_i_12_n_0));
LUT6 #(
.INIT(64'h6969006900690000))
Lyy_2_bottom_right0__0_carry__2_i_2
(.I0(\top_reg_n_0_[12] ),
.I1(\left_reg_n_0_[12] ),
.I2(\corner_reg_n_0_[12] ),
.I3(\corner_reg_n_0_[11] ),
.I4(\top_reg_n_0_[11] ),
.I5(\left_reg_n_0_[11] ),
.O(Lyy_2_bottom_right0__0_carry__2_i_2_n_0));
LUT6 #(
.INIT(64'h6969006900690000))
Lyy_2_bottom_right0__0_carry__2_i_3
(.I0(\top_reg_n_0_[11] ),
.I1(\left_reg_n_0_[11] ),
.I2(\corner_reg_n_0_[11] ),
.I3(\corner_reg_n_0_[10] ),
.I4(\top_reg_n_0_[10] ),
.I5(\left_reg_n_0_[10] ),
.O(Lyy_2_bottom_right0__0_carry__2_i_3_n_0));
LUT5 #(
.INIT(32'hD77D2882))
Lyy_2_bottom_right0__0_carry__2_i_4
(.I0(Lyy_2_bottom_right0__0_carry__2_i_8_n_0),
.I1(\corner_reg_n_0_[14] ),
.I2(\left_reg_n_0_[14] ),
.I3(\top_reg_n_0_[14] ),
.I4(Lyy_2_bottom_right0__0_carry__2_i_9_n_0),
.O(Lyy_2_bottom_right0__0_carry__2_i_4_n_0));
LUT5 #(
.INIT(32'h96669996))
Lyy_2_bottom_right0__0_carry__2_i_5
(.I0(Lyy_2_bottom_right0__0_carry__2_i_1_n_0),
.I1(Lyy_2_bottom_right0__0_carry__2_i_10_n_0),
.I2(\left_reg_n_0_[13] ),
.I3(\top_reg_n_0_[13] ),
.I4(\corner_reg_n_0_[13] ),
.O(Lyy_2_bottom_right0__0_carry__2_i_5_n_0));
LUT5 #(
.INIT(32'h96669996))
Lyy_2_bottom_right0__0_carry__2_i_6
(.I0(Lyy_2_bottom_right0__0_carry__2_i_2_n_0),
.I1(Lyy_2_bottom_right0__0_carry__2_i_11_n_0),
.I2(\left_reg_n_0_[12] ),
.I3(\top_reg_n_0_[12] ),
.I4(\corner_reg_n_0_[12] ),
.O(Lyy_2_bottom_right0__0_carry__2_i_6_n_0));
LUT5 #(
.INIT(32'h96669996))
Lyy_2_bottom_right0__0_carry__2_i_7
(.I0(Lyy_2_bottom_right0__0_carry__2_i_3_n_0),
.I1(Lyy_2_bottom_right0__0_carry__2_i_12_n_0),
.I2(\left_reg_n_0_[11] ),
.I3(\top_reg_n_0_[11] ),
.I4(\corner_reg_n_0_[11] ),
.O(Lyy_2_bottom_right0__0_carry__2_i_7_n_0));
(* SOFT_HLUTNM = "soft_lutpair33" *)
LUT3 #(
.INIT(8'h8E))
Lyy_2_bottom_right0__0_carry__2_i_8
(.I0(\left_reg_n_0_[13] ),
.I1(\top_reg_n_0_[13] ),
.I2(\corner_reg_n_0_[13] ),
.O(Lyy_2_bottom_right0__0_carry__2_i_8_n_0));
LUT6 #(
.INIT(64'hD42B2BD42BD4D42B))
Lyy_2_bottom_right0__0_carry__2_i_9
(.I0(\corner_reg_n_0_[14] ),
.I1(\top_reg_n_0_[14] ),
.I2(\left_reg_n_0_[14] ),
.I3(\top_reg_n_0_[15] ),
.I4(\left_reg_n_0_[15] ),
.I5(\corner_reg_n_0_[15] ),
.O(Lyy_2_bottom_right0__0_carry__2_i_9_n_0));
LUT5 #(
.INIT(32'hEE8E8E88))
Lyy_2_bottom_right0__0_carry_i_1
(.I0(last_value[2]),
.I1(Lyy_2_bottom_right0__0_carry_i_9_n_0),
.I2(\corner_reg_n_0_[1] ),
.I3(\top_reg_n_0_[1] ),
.I4(\left_reg_n_0_[1] ),
.O(Lyy_2_bottom_right0__0_carry_i_1_n_0));
LUT3 #(
.INIT(8'h69))
Lyy_2_bottom_right0__0_carry_i_10
(.I0(\corner_reg_n_0_[3] ),
.I1(\left_reg_n_0_[3] ),
.I2(\top_reg_n_0_[3] ),
.O(Lyy_2_bottom_right0__0_carry_i_10_n_0));
LUT3 #(
.INIT(8'h69))
Lyy_2_bottom_right0__0_carry_i_11
(.I0(\corner_reg_n_0_[1] ),
.I1(\left_reg_n_0_[1] ),
.I2(\top_reg_n_0_[1] ),
.O(Lyy_2_bottom_right0__0_carry_i_11_n_0));
LUT6 #(
.INIT(64'h20BABA20BA2020BA))
Lyy_2_bottom_right0__0_carry_i_2
(.I0(last_value[1]),
.I1(\corner_reg_n_0_[0] ),
.I2(last_value[0]),
.I3(\top_reg_n_0_[1] ),
.I4(\left_reg_n_0_[1] ),
.I5(\corner_reg_n_0_[1] ),
.O(Lyy_2_bottom_right0__0_carry_i_2_n_0));
LUT6 #(
.INIT(64'h9669966969969669))
Lyy_2_bottom_right0__0_carry_i_3
(.I0(\top_reg_n_0_[1] ),
.I1(\left_reg_n_0_[1] ),
.I2(\corner_reg_n_0_[1] ),
.I3(last_value[1]),
.I4(last_value[0]),
.I5(\corner_reg_n_0_[0] ),
.O(Lyy_2_bottom_right0__0_carry_i_3_n_0));
LUT2 #(
.INIT(4'h9))
Lyy_2_bottom_right0__0_carry_i_4
(.I0(\left_reg_n_0_[0] ),
.I1(\top_reg_n_0_[0] ),
.O(Lyy_2_bottom_right0__0_carry_i_4_n_0));
LUT6 #(
.INIT(64'h6996969669696996))
Lyy_2_bottom_right0__0_carry_i_5
(.I0(Lyy_2_bottom_right0__0_carry_i_1_n_0),
.I1(Lyy_2_bottom_right0__0_carry_i_10_n_0),
.I2(last_value[3]),
.I3(\left_reg_n_0_[2] ),
.I4(\top_reg_n_0_[2] ),
.I5(\corner_reg_n_0_[2] ),
.O(Lyy_2_bottom_right0__0_carry_i_5_n_0));
LUT6 #(
.INIT(64'h6996969669696996))
Lyy_2_bottom_right0__0_carry_i_6
(.I0(Lyy_2_bottom_right0__0_carry_i_2_n_0),
.I1(Lyy_2_bottom_right0__0_carry_i_9_n_0),
.I2(last_value[2]),
.I3(\left_reg_n_0_[1] ),
.I4(\top_reg_n_0_[1] ),
.I5(\corner_reg_n_0_[1] ),
.O(Lyy_2_bottom_right0__0_carry_i_6_n_0));
LUT6 #(
.INIT(64'hB44BB44BB44B4BB4))
Lyy_2_bottom_right0__0_carry_i_7
(.I0(\corner_reg_n_0_[0] ),
.I1(last_value[0]),
.I2(last_value[1]),
.I3(Lyy_2_bottom_right0__0_carry_i_11_n_0),
.I4(\left_reg_n_0_[0] ),
.I5(\top_reg_n_0_[0] ),
.O(Lyy_2_bottom_right0__0_carry_i_7_n_0));
LUT4 #(
.INIT(16'h6996))
Lyy_2_bottom_right0__0_carry_i_8
(.I0(\left_reg_n_0_[0] ),
.I1(\top_reg_n_0_[0] ),
.I2(\corner_reg_n_0_[0] ),
.I3(last_value[0]),
.O(Lyy_2_bottom_right0__0_carry_i_8_n_0));
LUT3 #(
.INIT(8'h69))
Lyy_2_bottom_right0__0_carry_i_9
(.I0(\corner_reg_n_0_[2] ),
.I1(\left_reg_n_0_[2] ),
.I2(\top_reg_n_0_[2] ),
.O(Lyy_2_bottom_right0__0_carry_i_9_n_0));
LUT6 #(
.INIT(64'h0000000000000080))
\Lyy_2_bottom_right[15]_i_1
(.I0(cycle[0]),
.I1(active),
.I2(rst),
.I3(\cycle_reg[1]_rep_n_0 ),
.I4(cycle[3]),
.I5(cycle[2]),
.O(y5));
FDRE #(
.INIT(1'b0))
\Lyy_2_bottom_right_reg[0]
(.C(clk_x16),
.CE(y5),
.D(Lyy_2_bottom_right01_out[0]),
.Q(Lyy_2_bottom_right[0]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lyy_2_bottom_right_reg[10]
(.C(clk_x16),
.CE(y5),
.D(Lyy_2_bottom_right01_out[10]),
.Q(Lyy_2_bottom_right[10]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lyy_2_bottom_right_reg[11]
(.C(clk_x16),
.CE(y5),
.D(Lyy_2_bottom_right01_out[11]),
.Q(Lyy_2_bottom_right[11]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lyy_2_bottom_right_reg[12]
(.C(clk_x16),
.CE(y5),
.D(Lyy_2_bottom_right01_out[12]),
.Q(Lyy_2_bottom_right[12]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lyy_2_bottom_right_reg[13]
(.C(clk_x16),
.CE(y5),
.D(Lyy_2_bottom_right01_out[13]),
.Q(Lyy_2_bottom_right[13]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lyy_2_bottom_right_reg[14]
(.C(clk_x16),
.CE(y5),
.D(Lyy_2_bottom_right01_out[14]),
.Q(Lyy_2_bottom_right[14]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lyy_2_bottom_right_reg[15]
(.C(clk_x16),
.CE(y5),
.D(Lyy_2_bottom_right01_out[15]),
.Q(Lyy_2_bottom_right[15]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lyy_2_bottom_right_reg[1]
(.C(clk_x16),
.CE(y5),
.D(Lyy_2_bottom_right01_out[1]),
.Q(Lyy_2_bottom_right[1]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lyy_2_bottom_right_reg[2]
(.C(clk_x16),
.CE(y5),
.D(Lyy_2_bottom_right01_out[2]),
.Q(Lyy_2_bottom_right[2]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lyy_2_bottom_right_reg[3]
(.C(clk_x16),
.CE(y5),
.D(Lyy_2_bottom_right01_out[3]),
.Q(Lyy_2_bottom_right[3]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lyy_2_bottom_right_reg[4]
(.C(clk_x16),
.CE(y5),
.D(Lyy_2_bottom_right01_out[4]),
.Q(Lyy_2_bottom_right[4]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lyy_2_bottom_right_reg[5]
(.C(clk_x16),
.CE(y5),
.D(Lyy_2_bottom_right01_out[5]),
.Q(Lyy_2_bottom_right[5]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lyy_2_bottom_right_reg[6]
(.C(clk_x16),
.CE(y5),
.D(Lyy_2_bottom_right01_out[6]),
.Q(Lyy_2_bottom_right[6]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lyy_2_bottom_right_reg[7]
(.C(clk_x16),
.CE(y5),
.D(Lyy_2_bottom_right01_out[7]),
.Q(Lyy_2_bottom_right[7]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lyy_2_bottom_right_reg[8]
(.C(clk_x16),
.CE(y5),
.D(Lyy_2_bottom_right01_out[8]),
.Q(Lyy_2_bottom_right[8]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lyy_2_bottom_right_reg[9]
(.C(clk_x16),
.CE(y5),
.D(Lyy_2_bottom_right01_out[9]),
.Q(Lyy_2_bottom_right[9]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lyy_2_reg[0]
(.C(clk_x16),
.CE(\Lyy_2[15]_i_1_n_0 ),
.D(Lyy_20[0]),
.Q(\Lyy_2_reg_n_0_[0] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lyy_2_reg[10]
(.C(clk_x16),
.CE(\Lyy_2[15]_i_1_n_0 ),
.D(Lyy_20[10]),
.Q(\Lyy_2_reg_n_0_[10] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lyy_2_reg[11]
(.C(clk_x16),
.CE(\Lyy_2[15]_i_1_n_0 ),
.D(Lyy_20[11]),
.Q(\Lyy_2_reg_n_0_[11] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lyy_2_reg[12]
(.C(clk_x16),
.CE(\Lyy_2[15]_i_1_n_0 ),
.D(Lyy_20[12]),
.Q(\Lyy_2_reg_n_0_[12] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lyy_2_reg[13]
(.C(clk_x16),
.CE(\Lyy_2[15]_i_1_n_0 ),
.D(Lyy_20[13]),
.Q(\Lyy_2_reg_n_0_[13] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lyy_2_reg[14]
(.C(clk_x16),
.CE(\Lyy_2[15]_i_1_n_0 ),
.D(Lyy_20[14]),
.Q(\Lyy_2_reg_n_0_[14] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lyy_2_reg[15]
(.C(clk_x16),
.CE(\Lyy_2[15]_i_1_n_0 ),
.D(Lyy_20[15]),
.Q(\Lyy_2_reg_n_0_[15] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lyy_2_reg[1]
(.C(clk_x16),
.CE(\Lyy_2[15]_i_1_n_0 ),
.D(Lyy_20[1]),
.Q(\Lyy_2_reg_n_0_[1] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lyy_2_reg[2]
(.C(clk_x16),
.CE(\Lyy_2[15]_i_1_n_0 ),
.D(Lyy_20[2]),
.Q(\Lyy_2_reg_n_0_[2] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lyy_2_reg[3]
(.C(clk_x16),
.CE(\Lyy_2[15]_i_1_n_0 ),
.D(Lyy_20[3]),
.Q(\Lyy_2_reg_n_0_[3] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lyy_2_reg[4]
(.C(clk_x16),
.CE(\Lyy_2[15]_i_1_n_0 ),
.D(Lyy_20[4]),
.Q(\Lyy_2_reg_n_0_[4] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lyy_2_reg[5]
(.C(clk_x16),
.CE(\Lyy_2[15]_i_1_n_0 ),
.D(Lyy_20[5]),
.Q(\Lyy_2_reg_n_0_[5] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lyy_2_reg[6]
(.C(clk_x16),
.CE(\Lyy_2[15]_i_1_n_0 ),
.D(Lyy_20[6]),
.Q(\Lyy_2_reg_n_0_[6] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lyy_2_reg[7]
(.C(clk_x16),
.CE(\Lyy_2[15]_i_1_n_0 ),
.D(Lyy_20[7]),
.Q(\Lyy_2_reg_n_0_[7] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lyy_2_reg[8]
(.C(clk_x16),
.CE(\Lyy_2[15]_i_1_n_0 ),
.D(Lyy_20[8]),
.Q(\Lyy_2_reg_n_0_[8] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lyy_2_reg[9]
(.C(clk_x16),
.CE(\Lyy_2[15]_i_1_n_0 ),
.D(Lyy_20[9]),
.Q(\Lyy_2_reg_n_0_[9] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lyy_2_top_left_reg[0]
(.C(clk_x16),
.CE(y1),
.D(bottom_left_1[0]),
.Q(Lyy_2_top_left[0]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lyy_2_top_left_reg[10]
(.C(clk_x16),
.CE(y1),
.D(bottom_left_1[10]),
.Q(Lyy_2_top_left[10]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lyy_2_top_left_reg[11]
(.C(clk_x16),
.CE(y1),
.D(bottom_left_1[11]),
.Q(Lyy_2_top_left[11]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lyy_2_top_left_reg[12]
(.C(clk_x16),
.CE(y1),
.D(bottom_left_1[12]),
.Q(Lyy_2_top_left[12]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lyy_2_top_left_reg[13]
(.C(clk_x16),
.CE(y1),
.D(bottom_left_1[13]),
.Q(Lyy_2_top_left[13]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lyy_2_top_left_reg[14]
(.C(clk_x16),
.CE(y1),
.D(bottom_left_1[14]),
.Q(Lyy_2_top_left[14]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lyy_2_top_left_reg[15]
(.C(clk_x16),
.CE(y1),
.D(bottom_left_1[15]),
.Q(Lyy_2_top_left[15]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lyy_2_top_left_reg[1]
(.C(clk_x16),
.CE(y1),
.D(bottom_left_1[1]),
.Q(Lyy_2_top_left[1]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lyy_2_top_left_reg[2]
(.C(clk_x16),
.CE(y1),
.D(bottom_left_1[2]),
.Q(Lyy_2_top_left[2]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lyy_2_top_left_reg[3]
(.C(clk_x16),
.CE(y1),
.D(bottom_left_1[3]),
.Q(Lyy_2_top_left[3]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lyy_2_top_left_reg[4]
(.C(clk_x16),
.CE(y1),
.D(bottom_left_1[4]),
.Q(Lyy_2_top_left[4]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lyy_2_top_left_reg[5]
(.C(clk_x16),
.CE(y1),
.D(bottom_left_1[5]),
.Q(Lyy_2_top_left[5]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lyy_2_top_left_reg[6]
(.C(clk_x16),
.CE(y1),
.D(bottom_left_1[6]),
.Q(Lyy_2_top_left[6]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lyy_2_top_left_reg[7]
(.C(clk_x16),
.CE(y1),
.D(bottom_left_1[7]),
.Q(Lyy_2_top_left[7]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lyy_2_top_left_reg[8]
(.C(clk_x16),
.CE(y1),
.D(bottom_left_1[8]),
.Q(Lyy_2_top_left[8]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lyy_2_top_left_reg[9]
(.C(clk_x16),
.CE(y1),
.D(bottom_left_1[9]),
.Q(Lyy_2_top_left[9]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lyy_2_top_right_reg[0]
(.C(clk_x16),
.CE(y1),
.D(\bottom_right_1_reg_n_0_[0] ),
.Q(Lyy_2_top_right[0]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lyy_2_top_right_reg[10]
(.C(clk_x16),
.CE(y1),
.D(\bottom_right_1_reg_n_0_[10] ),
.Q(Lyy_2_top_right[10]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lyy_2_top_right_reg[11]
(.C(clk_x16),
.CE(y1),
.D(\bottom_right_1_reg_n_0_[11] ),
.Q(Lyy_2_top_right[11]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lyy_2_top_right_reg[12]
(.C(clk_x16),
.CE(y1),
.D(\bottom_right_1_reg_n_0_[12] ),
.Q(Lyy_2_top_right[12]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lyy_2_top_right_reg[13]
(.C(clk_x16),
.CE(y1),
.D(\bottom_right_1_reg_n_0_[13] ),
.Q(Lyy_2_top_right[13]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lyy_2_top_right_reg[14]
(.C(clk_x16),
.CE(y1),
.D(\bottom_right_1_reg_n_0_[14] ),
.Q(Lyy_2_top_right[14]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lyy_2_top_right_reg[15]
(.C(clk_x16),
.CE(y1),
.D(\bottom_right_1_reg_n_0_[15] ),
.Q(Lyy_2_top_right[15]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lyy_2_top_right_reg[1]
(.C(clk_x16),
.CE(y1),
.D(\bottom_right_1_reg_n_0_[1] ),
.Q(Lyy_2_top_right[1]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lyy_2_top_right_reg[2]
(.C(clk_x16),
.CE(y1),
.D(\bottom_right_1_reg_n_0_[2] ),
.Q(Lyy_2_top_right[2]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lyy_2_top_right_reg[3]
(.C(clk_x16),
.CE(y1),
.D(\bottom_right_1_reg_n_0_[3] ),
.Q(Lyy_2_top_right[3]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lyy_2_top_right_reg[4]
(.C(clk_x16),
.CE(y1),
.D(\bottom_right_1_reg_n_0_[4] ),
.Q(Lyy_2_top_right[4]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lyy_2_top_right_reg[5]
(.C(clk_x16),
.CE(y1),
.D(\bottom_right_1_reg_n_0_[5] ),
.Q(Lyy_2_top_right[5]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lyy_2_top_right_reg[6]
(.C(clk_x16),
.CE(y1),
.D(\bottom_right_1_reg_n_0_[6] ),
.Q(Lyy_2_top_right[6]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lyy_2_top_right_reg[7]
(.C(clk_x16),
.CE(y1),
.D(\bottom_right_1_reg_n_0_[7] ),
.Q(Lyy_2_top_right[7]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lyy_2_top_right_reg[8]
(.C(clk_x16),
.CE(y1),
.D(\bottom_right_1_reg_n_0_[8] ),
.Q(Lyy_2_top_right[8]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Lyy_2_top_right_reg[9]
(.C(clk_x16),
.CE(y1),
.D(\bottom_right_1_reg_n_0_[9] ),
.Q(Lyy_2_top_right[9]),
.R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair60" *)
LUT3 #(
.INIT(8'hB8))
\addr_0[0]_i_1
(.I0(\compute_addr_0_reg_n_0_[0] ),
.I1(\cycle_reg[0]_rep_n_0 ),
.I2(\compute_addr_2_reg_n_0_[0] ),
.O(\addr_0[0]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair53" *)
LUT3 #(
.INIT(8'hB8))
\addr_0[10]_i_1
(.I0(\compute_addr_0_reg_n_0_[10] ),
.I1(\cycle_reg[0]_rep_n_0 ),
.I2(\compute_addr_2_reg_n_0_[10] ),
.O(\addr_0[10]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair39" *)
LUT3 #(
.INIT(8'hB8))
\addr_0[11]_i_1
(.I0(\compute_addr_0_reg_n_0_[11] ),
.I1(\cycle_reg[0]_rep_n_0 ),
.I2(\compute_addr_2_reg_n_0_[11] ),
.O(\addr_0[11]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair37" *)
LUT3 #(
.INIT(8'hB8))
\addr_0[12]_i_1
(.I0(\compute_addr_0_reg_n_0_[12] ),
.I1(\cycle_reg[0]_rep_n_0 ),
.I2(\compute_addr_2_reg_n_0_[12] ),
.O(\addr_0[12]_i_1_n_0 ));
LUT6 #(
.INIT(64'h8888888888808888))
\addr_0[13]_i_1
(.I0(rst),
.I1(active),
.I2(cycle[3]),
.I3(\cycle_reg[0]_rep_n_0 ),
.I4(\cycle_reg[1]_rep_n_0 ),
.I5(cycle[2]),
.O(addr_0));
(* SOFT_HLUTNM = "soft_lutpair36" *)
LUT3 #(
.INIT(8'hB8))
\addr_0[13]_i_2
(.I0(\compute_addr_0_reg_n_0_[13] ),
.I1(\cycle_reg[0]_rep_n_0 ),
.I2(\compute_addr_2_reg_n_0_[13] ),
.O(\addr_0[13]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair56" *)
LUT3 #(
.INIT(8'hB8))
\addr_0[1]_i_1
(.I0(\compute_addr_0_reg_n_0_[1] ),
.I1(\cycle_reg[0]_rep_n_0 ),
.I2(\compute_addr_2_reg_n_0_[1] ),
.O(\addr_0[1]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair39" *)
LUT3 #(
.INIT(8'hB8))
\addr_0[2]_i_1
(.I0(\compute_addr_0_reg_n_0_[2] ),
.I1(\cycle_reg[0]_rep_n_0 ),
.I2(\compute_addr_2_reg_n_0_[2] ),
.O(\addr_0[2]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair36" *)
LUT3 #(
.INIT(8'hB8))
\addr_0[3]_i_1
(.I0(\compute_addr_0_reg_n_0_[3] ),
.I1(\cycle_reg[0]_rep_n_0 ),
.I2(\compute_addr_2_reg_n_0_[3] ),
.O(\addr_0[3]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair37" *)
LUT3 #(
.INIT(8'hB8))
\addr_0[4]_i_1
(.I0(\compute_addr_0_reg_n_0_[4] ),
.I1(\cycle_reg[0]_rep_n_0 ),
.I2(\compute_addr_2_reg_n_0_[4] ),
.O(\addr_0[4]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair53" *)
LUT3 #(
.INIT(8'hB8))
\addr_0[5]_i_1
(.I0(\compute_addr_0_reg_n_0_[5] ),
.I1(\cycle_reg[0]_rep_n_0 ),
.I2(\compute_addr_2_reg_n_0_[5] ),
.O(\addr_0[5]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair60" *)
LUT3 #(
.INIT(8'hB8))
\addr_0[6]_i_1
(.I0(\compute_addr_0_reg_n_0_[6] ),
.I1(\cycle_reg[0]_rep_n_0 ),
.I2(\compute_addr_2_reg_n_0_[6] ),
.O(\addr_0[6]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair59" *)
LUT3 #(
.INIT(8'hB8))
\addr_0[7]_i_1
(.I0(\compute_addr_0_reg_n_0_[7] ),
.I1(\cycle_reg[0]_rep_n_0 ),
.I2(\compute_addr_2_reg_n_0_[7] ),
.O(\addr_0[7]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair59" *)
LUT3 #(
.INIT(8'hB8))
\addr_0[8]_i_1
(.I0(\compute_addr_0_reg_n_0_[8] ),
.I1(\cycle_reg[0]_rep_n_0 ),
.I2(\compute_addr_2_reg_n_0_[8] ),
.O(\addr_0[8]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair56" *)
LUT3 #(
.INIT(8'hB8))
\addr_0[9]_i_1
(.I0(\compute_addr_0_reg_n_0_[9] ),
.I1(\cycle_reg[0]_rep_n_0 ),
.I2(\compute_addr_2_reg_n_0_[9] ),
.O(\addr_0[9]_i_1_n_0 ));
FDRE \addr_0_reg[0]
(.C(clk_x16),
.CE(addr_0),
.D(\addr_0[0]_i_1_n_0 ),
.Q(\addr_0_reg_n_0_[0] ),
.R(1'b0));
FDRE \addr_0_reg[10]
(.C(clk_x16),
.CE(addr_0),
.D(\addr_0[10]_i_1_n_0 ),
.Q(\addr_0_reg_n_0_[10] ),
.R(1'b0));
FDRE \addr_0_reg[11]
(.C(clk_x16),
.CE(addr_0),
.D(\addr_0[11]_i_1_n_0 ),
.Q(\addr_0_reg_n_0_[11] ),
.R(1'b0));
FDRE \addr_0_reg[12]
(.C(clk_x16),
.CE(addr_0),
.D(\addr_0[12]_i_1_n_0 ),
.Q(\addr_0_reg_n_0_[12] ),
.R(1'b0));
FDRE \addr_0_reg[13]
(.C(clk_x16),
.CE(addr_0),
.D(\addr_0[13]_i_2_n_0 ),
.Q(\addr_0_reg_n_0_[13] ),
.R(1'b0));
FDRE \addr_0_reg[1]
(.C(clk_x16),
.CE(addr_0),
.D(\addr_0[1]_i_1_n_0 ),
.Q(\addr_0_reg_n_0_[1] ),
.R(1'b0));
FDRE \addr_0_reg[2]
(.C(clk_x16),
.CE(addr_0),
.D(\addr_0[2]_i_1_n_0 ),
.Q(\addr_0_reg_n_0_[2] ),
.R(1'b0));
FDRE \addr_0_reg[3]
(.C(clk_x16),
.CE(addr_0),
.D(\addr_0[3]_i_1_n_0 ),
.Q(\addr_0_reg_n_0_[3] ),
.R(1'b0));
FDRE \addr_0_reg[4]
(.C(clk_x16),
.CE(addr_0),
.D(\addr_0[4]_i_1_n_0 ),
.Q(\addr_0_reg_n_0_[4] ),
.R(1'b0));
FDRE \addr_0_reg[5]
(.C(clk_x16),
.CE(addr_0),
.D(\addr_0[5]_i_1_n_0 ),
.Q(\addr_0_reg_n_0_[5] ),
.R(1'b0));
FDRE \addr_0_reg[6]
(.C(clk_x16),
.CE(addr_0),
.D(\addr_0[6]_i_1_n_0 ),
.Q(\addr_0_reg_n_0_[6] ),
.R(1'b0));
FDRE \addr_0_reg[7]
(.C(clk_x16),
.CE(addr_0),
.D(\addr_0[7]_i_1_n_0 ),
.Q(\addr_0_reg_n_0_[7] ),
.R(1'b0));
FDRE \addr_0_reg[8]
(.C(clk_x16),
.CE(addr_0),
.D(\addr_0[8]_i_1_n_0 ),
.Q(\addr_0_reg_n_0_[8] ),
.R(1'b0));
FDRE \addr_0_reg[9]
(.C(clk_x16),
.CE(addr_0),
.D(\addr_0[9]_i_1_n_0 ),
.Q(\addr_0_reg_n_0_[9] ),
.R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair63" *)
LUT3 #(
.INIT(8'hB8))
\addr_1[0]_i_1
(.I0(compute_addr_1[0]),
.I1(\cycle_reg[0]_rep_n_0 ),
.I2(compute_addr_3[0]),
.O(\addr_1[0]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair62" *)
LUT3 #(
.INIT(8'hB8))
\addr_1[10]_i_1
(.I0(compute_addr_1[10]),
.I1(\cycle_reg[0]_rep_n_0 ),
.I2(compute_addr_3[10]),
.O(\addr_1[10]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair61" *)
LUT3 #(
.INIT(8'hB8))
\addr_1[11]_i_1
(.I0(compute_addr_1[11]),
.I1(\cycle_reg[0]_rep_n_0 ),
.I2(compute_addr_3[11]),
.O(\addr_1[11]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair62" *)
LUT3 #(
.INIT(8'hB8))
\addr_1[12]_i_1
(.I0(compute_addr_1[12]),
.I1(\cycle_reg[0]_rep_n_0 ),
.I2(compute_addr_3[12]),
.O(\addr_1[12]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair61" *)
LUT3 #(
.INIT(8'hB8))
\addr_1[13]_i_1
(.I0(compute_addr_1[13]),
.I1(\cycle_reg[0]_rep_n_0 ),
.I2(compute_addr_3[13]),
.O(\addr_1[13]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair64" *)
LUT3 #(
.INIT(8'hB8))
\addr_1[1]_i_1
(.I0(compute_addr_1[1]),
.I1(\cycle_reg[0]_rep_n_0 ),
.I2(compute_addr_3[1]),
.O(\addr_1[1]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair65" *)
LUT3 #(
.INIT(8'hB8))
\addr_1[2]_i_1
(.I0(compute_addr_1[2]),
.I1(\cycle_reg[0]_rep_n_0 ),
.I2(compute_addr_3[2]),
.O(\addr_1[2]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair69" *)
LUT3 #(
.INIT(8'hB8))
\addr_1[3]_i_1
(.I0(compute_addr_1[3]),
.I1(\cycle_reg[0]_rep_n_0 ),
.I2(compute_addr_3[3]),
.O(\addr_1[3]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair69" *)
LUT3 #(
.INIT(8'hB8))
\addr_1[4]_i_1
(.I0(compute_addr_1[4]),
.I1(\cycle_reg[0]_rep_n_0 ),
.I2(compute_addr_3[4]),
.O(\addr_1[4]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair68" *)
LUT3 #(
.INIT(8'hB8))
\addr_1[5]_i_1
(.I0(compute_addr_1[5]),
.I1(\cycle_reg[0]_rep_n_0 ),
.I2(compute_addr_3[5]),
.O(\addr_1[5]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair68" *)
LUT3 #(
.INIT(8'hB8))
\addr_1[6]_i_1
(.I0(compute_addr_1[6]),
.I1(\cycle_reg[0]_rep_n_0 ),
.I2(compute_addr_3[6]),
.O(\addr_1[6]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair65" *)
LUT3 #(
.INIT(8'hB8))
\addr_1[7]_i_1
(.I0(compute_addr_1[7]),
.I1(\cycle_reg[0]_rep_n_0 ),
.I2(compute_addr_3[7]),
.O(\addr_1[7]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair64" *)
LUT3 #(
.INIT(8'hB8))
\addr_1[8]_i_1
(.I0(compute_addr_1[8]),
.I1(\cycle_reg[0]_rep_n_0 ),
.I2(compute_addr_3[8]),
.O(\addr_1[8]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair63" *)
LUT3 #(
.INIT(8'hB8))
\addr_1[9]_i_1
(.I0(compute_addr_1[9]),
.I1(\cycle_reg[0]_rep_n_0 ),
.I2(compute_addr_3[9]),
.O(\addr_1[9]_i_1_n_0 ));
FDRE \addr_1_reg[0]
(.C(clk_x16),
.CE(addr_0),
.D(\addr_1[0]_i_1_n_0 ),
.Q(addr_1[0]),
.R(1'b0));
FDRE \addr_1_reg[10]
(.C(clk_x16),
.CE(addr_0),
.D(\addr_1[10]_i_1_n_0 ),
.Q(addr_1[10]),
.R(1'b0));
FDRE \addr_1_reg[11]
(.C(clk_x16),
.CE(addr_0),
.D(\addr_1[11]_i_1_n_0 ),
.Q(addr_1[11]),
.R(1'b0));
FDRE \addr_1_reg[12]
(.C(clk_x16),
.CE(addr_0),
.D(\addr_1[12]_i_1_n_0 ),
.Q(addr_1[12]),
.R(1'b0));
FDRE \addr_1_reg[13]
(.C(clk_x16),
.CE(addr_0),
.D(\addr_1[13]_i_1_n_0 ),
.Q(addr_1[13]),
.R(1'b0));
FDRE \addr_1_reg[1]
(.C(clk_x16),
.CE(addr_0),
.D(\addr_1[1]_i_1_n_0 ),
.Q(addr_1[1]),
.R(1'b0));
FDRE \addr_1_reg[2]
(.C(clk_x16),
.CE(addr_0),
.D(\addr_1[2]_i_1_n_0 ),
.Q(addr_1[2]),
.R(1'b0));
FDRE \addr_1_reg[3]
(.C(clk_x16),
.CE(addr_0),
.D(\addr_1[3]_i_1_n_0 ),
.Q(addr_1[3]),
.R(1'b0));
FDRE \addr_1_reg[4]
(.C(clk_x16),
.CE(addr_0),
.D(\addr_1[4]_i_1_n_0 ),
.Q(addr_1[4]),
.R(1'b0));
FDRE \addr_1_reg[5]
(.C(clk_x16),
.CE(addr_0),
.D(\addr_1[5]_i_1_n_0 ),
.Q(addr_1[5]),
.R(1'b0));
FDRE \addr_1_reg[6]
(.C(clk_x16),
.CE(addr_0),
.D(\addr_1[6]_i_1_n_0 ),
.Q(addr_1[6]),
.R(1'b0));
FDRE \addr_1_reg[7]
(.C(clk_x16),
.CE(addr_0),
.D(\addr_1[7]_i_1_n_0 ),
.Q(addr_1[7]),
.R(1'b0));
FDRE \addr_1_reg[8]
(.C(clk_x16),
.CE(addr_0),
.D(\addr_1[8]_i_1_n_0 ),
.Q(addr_1[8]),
.R(1'b0));
FDRE \addr_1_reg[9]
(.C(clk_x16),
.CE(addr_0),
.D(\addr_1[9]_i_1_n_0 ),
.Q(addr_1[9]),
.R(1'b0));
LUT6 #(
.INIT(64'h8800880000000800))
\bottom_left_0[15]_i_1
(.I0(rst),
.I1(active),
.I2(cycle[2]),
.I3(\cycle_reg[0]_rep_n_0 ),
.I4(cycle[3]),
.I5(\cycle_reg[1]_rep_n_0 ),
.O(bottom_left_0));
FDRE #(
.INIT(1'b0))
\bottom_left_0_reg[0]
(.C(clk_x16),
.CE(bottom_left_0),
.D(dout_0[0]),
.Q(\bottom_left_0_reg_n_0_[0] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\bottom_left_0_reg[10]
(.C(clk_x16),
.CE(bottom_left_0),
.D(dout_0[10]),
.Q(\bottom_left_0_reg_n_0_[10] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\bottom_left_0_reg[11]
(.C(clk_x16),
.CE(bottom_left_0),
.D(dout_0[11]),
.Q(\bottom_left_0_reg_n_0_[11] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\bottom_left_0_reg[12]
(.C(clk_x16),
.CE(bottom_left_0),
.D(dout_0[12]),
.Q(\bottom_left_0_reg_n_0_[12] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\bottom_left_0_reg[13]
(.C(clk_x16),
.CE(bottom_left_0),
.D(dout_0[13]),
.Q(\bottom_left_0_reg_n_0_[13] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\bottom_left_0_reg[14]
(.C(clk_x16),
.CE(bottom_left_0),
.D(dout_0[14]),
.Q(\bottom_left_0_reg_n_0_[14] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\bottom_left_0_reg[15]
(.C(clk_x16),
.CE(bottom_left_0),
.D(dout_0[15]),
.Q(\bottom_left_0_reg_n_0_[15] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\bottom_left_0_reg[1]
(.C(clk_x16),
.CE(bottom_left_0),
.D(dout_0[1]),
.Q(\bottom_left_0_reg_n_0_[1] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\bottom_left_0_reg[2]
(.C(clk_x16),
.CE(bottom_left_0),
.D(dout_0[2]),
.Q(\bottom_left_0_reg_n_0_[2] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\bottom_left_0_reg[3]
(.C(clk_x16),
.CE(bottom_left_0),
.D(dout_0[3]),
.Q(\bottom_left_0_reg_n_0_[3] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\bottom_left_0_reg[4]
(.C(clk_x16),
.CE(bottom_left_0),
.D(dout_0[4]),
.Q(\bottom_left_0_reg_n_0_[4] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\bottom_left_0_reg[5]
(.C(clk_x16),
.CE(bottom_left_0),
.D(dout_0[5]),
.Q(\bottom_left_0_reg_n_0_[5] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\bottom_left_0_reg[6]
(.C(clk_x16),
.CE(bottom_left_0),
.D(dout_0[6]),
.Q(\bottom_left_0_reg_n_0_[6] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\bottom_left_0_reg[7]
(.C(clk_x16),
.CE(bottom_left_0),
.D(dout_0[7]),
.Q(\bottom_left_0_reg_n_0_[7] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\bottom_left_0_reg[8]
(.C(clk_x16),
.CE(bottom_left_0),
.D(dout_0[8]),
.Q(\bottom_left_0_reg_n_0_[8] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\bottom_left_0_reg[9]
(.C(clk_x16),
.CE(bottom_left_0),
.D(dout_0[9]),
.Q(\bottom_left_0_reg_n_0_[9] ),
.R(1'b0));
LUT5 #(
.INIT(32'h40000040))
\bottom_left_1[15]_i_1
(.I0(\cycle_reg[1]_rep_n_0 ),
.I1(active),
.I2(rst),
.I3(\cycle_reg[0]_rep_n_0 ),
.I4(cycle[3]),
.O(top_right_1));
FDRE #(
.INIT(1'b0))
\bottom_left_1_reg[0]
(.C(clk_x16),
.CE(top_right_1),
.D(dout_0[0]),
.Q(bottom_left_1[0]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\bottom_left_1_reg[10]
(.C(clk_x16),
.CE(top_right_1),
.D(dout_0[10]),
.Q(bottom_left_1[10]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\bottom_left_1_reg[11]
(.C(clk_x16),
.CE(top_right_1),
.D(dout_0[11]),
.Q(bottom_left_1[11]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\bottom_left_1_reg[12]
(.C(clk_x16),
.CE(top_right_1),
.D(dout_0[12]),
.Q(bottom_left_1[12]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\bottom_left_1_reg[13]
(.C(clk_x16),
.CE(top_right_1),
.D(dout_0[13]),
.Q(bottom_left_1[13]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\bottom_left_1_reg[14]
(.C(clk_x16),
.CE(top_right_1),
.D(dout_0[14]),
.Q(bottom_left_1[14]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\bottom_left_1_reg[15]
(.C(clk_x16),
.CE(top_right_1),
.D(dout_0[15]),
.Q(bottom_left_1[15]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\bottom_left_1_reg[1]
(.C(clk_x16),
.CE(top_right_1),
.D(dout_0[1]),
.Q(bottom_left_1[1]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\bottom_left_1_reg[2]
(.C(clk_x16),
.CE(top_right_1),
.D(dout_0[2]),
.Q(bottom_left_1[2]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\bottom_left_1_reg[3]
(.C(clk_x16),
.CE(top_right_1),
.D(dout_0[3]),
.Q(bottom_left_1[3]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\bottom_left_1_reg[4]
(.C(clk_x16),
.CE(top_right_1),
.D(dout_0[4]),
.Q(bottom_left_1[4]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\bottom_left_1_reg[5]
(.C(clk_x16),
.CE(top_right_1),
.D(dout_0[5]),
.Q(bottom_left_1[5]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\bottom_left_1_reg[6]
(.C(clk_x16),
.CE(top_right_1),
.D(dout_0[6]),
.Q(bottom_left_1[6]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\bottom_left_1_reg[7]
(.C(clk_x16),
.CE(top_right_1),
.D(dout_0[7]),
.Q(bottom_left_1[7]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\bottom_left_1_reg[8]
(.C(clk_x16),
.CE(top_right_1),
.D(dout_0[8]),
.Q(bottom_left_1[8]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\bottom_left_1_reg[9]
(.C(clk_x16),
.CE(top_right_1),
.D(dout_0[9]),
.Q(bottom_left_1[9]),
.R(1'b0));
LUT6 #(
.INIT(64'hFFF0CC880F00CC88))
\bottom_right_0[0]_i_1
(.I0(\bottom_right_0[15]_i_3_n_0 ),
.I1(\bottom_right_0[0]_i_2_n_0 ),
.I2(\bottom_right_0[15]_i_5_n_0 ),
.I3(dout_0[0]),
.I4(cycle[3]),
.I5(\cache_reg[8]_1 [0]),
.O(p_0_out[0]));
(* SOFT_HLUTNM = "soft_lutpair12" *)
LUT5 #(
.INIT(32'hFFE2FFFF))
\bottom_right_0[0]_i_2
(.I0(bottom_left_1[0]),
.I1(\cycle_reg[1]_rep_n_0 ),
.I2(dout_1[0]),
.I3(cycle[2]),
.I4(cycle[0]),
.O(\bottom_right_0[0]_i_2_n_0 ));
LUT6 #(
.INIT(64'hFFF0CC880F00CC88))
\bottom_right_0[10]_i_1
(.I0(\bottom_right_0[15]_i_3_n_0 ),
.I1(\bottom_right_0[10]_i_2_n_0 ),
.I2(\bottom_right_0[15]_i_5_n_0 ),
.I3(dout_0[10]),
.I4(cycle[3]),
.I5(\cache_reg[8]_1 [10]),
.O(p_0_out[10]));
LUT5 #(
.INIT(32'hFFE2FFFF))
\bottom_right_0[10]_i_2
(.I0(bottom_left_1[10]),
.I1(\cycle_reg[1]_rep_n_0 ),
.I2(dout_1[10]),
.I3(cycle[2]),
.I4(\cycle_reg[0]_rep_n_0 ),
.O(\bottom_right_0[10]_i_2_n_0 ));
LUT6 #(
.INIT(64'hFFF0CC880F00CC88))
\bottom_right_0[11]_i_1
(.I0(\bottom_right_0[15]_i_3_n_0 ),
.I1(\bottom_right_0[11]_i_2_n_0 ),
.I2(\bottom_right_0[15]_i_5_n_0 ),
.I3(dout_0[11]),
.I4(cycle[3]),
.I5(\cache_reg[8]_1 [11]),
.O(p_0_out[11]));
LUT5 #(
.INIT(32'hFFE2FFFF))
\bottom_right_0[11]_i_2
(.I0(bottom_left_1[11]),
.I1(\cycle_reg[1]_rep_n_0 ),
.I2(dout_1[11]),
.I3(cycle[2]),
.I4(\cycle_reg[0]_rep_n_0 ),
.O(\bottom_right_0[11]_i_2_n_0 ));
LUT6 #(
.INIT(64'hFFF0CC880F00CC88))
\bottom_right_0[12]_i_1
(.I0(\bottom_right_0[15]_i_3_n_0 ),
.I1(\bottom_right_0[12]_i_2_n_0 ),
.I2(\bottom_right_0[15]_i_5_n_0 ),
.I3(dout_0[12]),
.I4(cycle[3]),
.I5(\cache_reg[8]_1 [12]),
.O(p_0_out[12]));
LUT5 #(
.INIT(32'hFFE2FFFF))
\bottom_right_0[12]_i_2
(.I0(bottom_left_1[12]),
.I1(\cycle_reg[1]_rep_n_0 ),
.I2(dout_1[12]),
.I3(cycle[2]),
.I4(\cycle_reg[0]_rep_n_0 ),
.O(\bottom_right_0[12]_i_2_n_0 ));
LUT6 #(
.INIT(64'hFFF0CC880F00CC88))
\bottom_right_0[13]_i_1
(.I0(\bottom_right_0[15]_i_3_n_0 ),
.I1(\bottom_right_0[13]_i_2_n_0 ),
.I2(\bottom_right_0[15]_i_5_n_0 ),
.I3(dout_0[13]),
.I4(cycle[3]),
.I5(\cache_reg[8]_1 [13]),
.O(p_0_out[13]));
LUT5 #(
.INIT(32'hFFE2FFFF))
\bottom_right_0[13]_i_2
(.I0(bottom_left_1[13]),
.I1(\cycle_reg[1]_rep_n_0 ),
.I2(dout_1[13]),
.I3(cycle[2]),
.I4(\cycle_reg[0]_rep_n_0 ),
.O(\bottom_right_0[13]_i_2_n_0 ));
LUT6 #(
.INIT(64'hFFF0CC880F00CC88))
\bottom_right_0[14]_i_1
(.I0(\bottom_right_0[15]_i_3_n_0 ),
.I1(\bottom_right_0[14]_i_2_n_0 ),
.I2(\bottom_right_0[15]_i_5_n_0 ),
.I3(dout_0[14]),
.I4(cycle[3]),
.I5(\cache_reg[8]_1 [14]),
.O(p_0_out[14]));
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT5 #(
.INIT(32'hFFE2FFFF))
\bottom_right_0[14]_i_2
(.I0(bottom_left_1[14]),
.I1(\cycle_reg[1]_rep_n_0 ),
.I2(dout_1[14]),
.I3(cycle[2]),
.I4(\cycle_reg[0]_rep_n_0 ),
.O(\bottom_right_0[14]_i_2_n_0 ));
LUT6 #(
.INIT(64'h444A000000000000))
\bottom_right_0[15]_i_1
(.I0(cycle[0]),
.I1(\cycle_reg[1]_rep_n_0 ),
.I2(cycle[2]),
.I3(cycle[3]),
.I4(rst),
.I5(active),
.O(\bottom_right_0[15]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFFF0CC880F00CC88))
\bottom_right_0[15]_i_2
(.I0(\bottom_right_0[15]_i_3_n_0 ),
.I1(\bottom_right_0[15]_i_4_n_0 ),
.I2(\bottom_right_0[15]_i_5_n_0 ),
.I3(dout_0[15]),
.I4(cycle[3]),
.I5(\cache_reg[8]_1 [15]),
.O(p_0_out[15]));
(* SOFT_HLUTNM = "soft_lutpair5" *)
LUT2 #(
.INIT(4'h2))
\bottom_right_0[15]_i_3
(.I0(\cycle_reg[0]_rep_n_0 ),
.I1(cycle[2]),
.O(\bottom_right_0[15]_i_3_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair5" *)
LUT5 #(
.INIT(32'hFFE2FFFF))
\bottom_right_0[15]_i_4
(.I0(bottom_left_1[15]),
.I1(\cycle_reg[1]_rep_n_0 ),
.I2(dout_1[15]),
.I3(cycle[2]),
.I4(\cycle_reg[0]_rep_n_0 ),
.O(\bottom_right_0[15]_i_4_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair12" *)
LUT3 #(
.INIT(8'h04))
\bottom_right_0[15]_i_5
(.I0(cycle[2]),
.I1(\cycle_reg[1]_rep_n_0 ),
.I2(cycle[0]),
.O(\bottom_right_0[15]_i_5_n_0 ));
LUT6 #(
.INIT(64'hFFF0CC880F00CC88))
\bottom_right_0[1]_i_1
(.I0(\bottom_right_0[15]_i_3_n_0 ),
.I1(\bottom_right_0[1]_i_2_n_0 ),
.I2(\bottom_right_0[15]_i_5_n_0 ),
.I3(dout_0[1]),
.I4(cycle[3]),
.I5(\cache_reg[8]_1 [1]),
.O(p_0_out[1]));
LUT5 #(
.INIT(32'hFFE2FFFF))
\bottom_right_0[1]_i_2
(.I0(bottom_left_1[1]),
.I1(\cycle_reg[1]_rep_n_0 ),
.I2(dout_1[1]),
.I3(cycle[2]),
.I4(cycle[0]),
.O(\bottom_right_0[1]_i_2_n_0 ));
LUT6 #(
.INIT(64'hFFF0CC880F00CC88))
\bottom_right_0[2]_i_1
(.I0(\bottom_right_0[15]_i_3_n_0 ),
.I1(\bottom_right_0[2]_i_2_n_0 ),
.I2(\bottom_right_0[15]_i_5_n_0 ),
.I3(dout_0[2]),
.I4(cycle[3]),
.I5(\cache_reg[8]_1 [2]),
.O(p_0_out[2]));
LUT5 #(
.INIT(32'hFFE2FFFF))
\bottom_right_0[2]_i_2
(.I0(bottom_left_1[2]),
.I1(\cycle_reg[1]_rep_n_0 ),
.I2(dout_1[2]),
.I3(cycle[2]),
.I4(cycle[0]),
.O(\bottom_right_0[2]_i_2_n_0 ));
LUT6 #(
.INIT(64'hFFF0CC880F00CC88))
\bottom_right_0[3]_i_1
(.I0(\bottom_right_0[15]_i_3_n_0 ),
.I1(\bottom_right_0[3]_i_2_n_0 ),
.I2(\bottom_right_0[15]_i_5_n_0 ),
.I3(dout_0[3]),
.I4(cycle[3]),
.I5(\cache_reg[8]_1 [3]),
.O(p_0_out[3]));
LUT5 #(
.INIT(32'hFFE2FFFF))
\bottom_right_0[3]_i_2
(.I0(bottom_left_1[3]),
.I1(\cycle_reg[1]_rep_n_0 ),
.I2(dout_1[3]),
.I3(cycle[2]),
.I4(\cycle_reg[0]_rep_n_0 ),
.O(\bottom_right_0[3]_i_2_n_0 ));
LUT6 #(
.INIT(64'hFFF0CC880F00CC88))
\bottom_right_0[4]_i_1
(.I0(\bottom_right_0[15]_i_3_n_0 ),
.I1(\bottom_right_0[4]_i_2_n_0 ),
.I2(\bottom_right_0[15]_i_5_n_0 ),
.I3(dout_0[4]),
.I4(cycle[3]),
.I5(\cache_reg[8]_1 [4]),
.O(p_0_out[4]));
LUT5 #(
.INIT(32'hFFE2FFFF))
\bottom_right_0[4]_i_2
(.I0(bottom_left_1[4]),
.I1(\cycle_reg[1]_rep_n_0 ),
.I2(dout_1[4]),
.I3(cycle[2]),
.I4(\cycle_reg[0]_rep_n_0 ),
.O(\bottom_right_0[4]_i_2_n_0 ));
LUT6 #(
.INIT(64'hFFF0CC880F00CC88))
\bottom_right_0[5]_i_1
(.I0(\bottom_right_0[15]_i_3_n_0 ),
.I1(\bottom_right_0[5]_i_2_n_0 ),
.I2(\bottom_right_0[15]_i_5_n_0 ),
.I3(dout_0[5]),
.I4(cycle[3]),
.I5(\cache_reg[8]_1 [5]),
.O(p_0_out[5]));
LUT5 #(
.INIT(32'hFFE2FFFF))
\bottom_right_0[5]_i_2
(.I0(bottom_left_1[5]),
.I1(\cycle_reg[1]_rep_n_0 ),
.I2(dout_1[5]),
.I3(cycle[2]),
.I4(\cycle_reg[0]_rep_n_0 ),
.O(\bottom_right_0[5]_i_2_n_0 ));
LUT6 #(
.INIT(64'hFFF0CC880F00CC88))
\bottom_right_0[6]_i_1
(.I0(\bottom_right_0[15]_i_3_n_0 ),
.I1(\bottom_right_0[6]_i_2_n_0 ),
.I2(\bottom_right_0[15]_i_5_n_0 ),
.I3(dout_0[6]),
.I4(cycle[3]),
.I5(\cache_reg[8]_1 [6]),
.O(p_0_out[6]));
LUT5 #(
.INIT(32'hFFE2FFFF))
\bottom_right_0[6]_i_2
(.I0(bottom_left_1[6]),
.I1(\cycle_reg[1]_rep_n_0 ),
.I2(dout_1[6]),
.I3(cycle[2]),
.I4(\cycle_reg[0]_rep_n_0 ),
.O(\bottom_right_0[6]_i_2_n_0 ));
LUT6 #(
.INIT(64'hFFF0CC880F00CC88))
\bottom_right_0[7]_i_1
(.I0(\bottom_right_0[15]_i_3_n_0 ),
.I1(\bottom_right_0[7]_i_2_n_0 ),
.I2(\bottom_right_0[15]_i_5_n_0 ),
.I3(dout_0[7]),
.I4(cycle[3]),
.I5(\cache_reg[8]_1 [7]),
.O(p_0_out[7]));
LUT5 #(
.INIT(32'hFFE2FFFF))
\bottom_right_0[7]_i_2
(.I0(bottom_left_1[7]),
.I1(\cycle_reg[1]_rep_n_0 ),
.I2(dout_1[7]),
.I3(cycle[2]),
.I4(\cycle_reg[0]_rep_n_0 ),
.O(\bottom_right_0[7]_i_2_n_0 ));
LUT6 #(
.INIT(64'hFFF0CC880F00CC88))
\bottom_right_0[8]_i_1
(.I0(\bottom_right_0[15]_i_3_n_0 ),
.I1(\bottom_right_0[8]_i_2_n_0 ),
.I2(\bottom_right_0[15]_i_5_n_0 ),
.I3(dout_0[8]),
.I4(cycle[3]),
.I5(\cache_reg[8]_1 [8]),
.O(p_0_out[8]));
LUT5 #(
.INIT(32'hFFE2FFFF))
\bottom_right_0[8]_i_2
(.I0(bottom_left_1[8]),
.I1(\cycle_reg[1]_rep_n_0 ),
.I2(dout_1[8]),
.I3(cycle[2]),
.I4(\cycle_reg[0]_rep_n_0 ),
.O(\bottom_right_0[8]_i_2_n_0 ));
LUT6 #(
.INIT(64'hFFF0CC880F00CC88))
\bottom_right_0[9]_i_1
(.I0(\bottom_right_0[15]_i_3_n_0 ),
.I1(\bottom_right_0[9]_i_2_n_0 ),
.I2(\bottom_right_0[15]_i_5_n_0 ),
.I3(dout_0[9]),
.I4(cycle[3]),
.I5(\cache_reg[8]_1 [9]),
.O(p_0_out[9]));
LUT5 #(
.INIT(32'hFFE2FFFF))
\bottom_right_0[9]_i_2
(.I0(bottom_left_1[9]),
.I1(\cycle_reg[1]_rep_n_0 ),
.I2(dout_1[9]),
.I3(cycle[2]),
.I4(\cycle_reg[0]_rep_n_0 ),
.O(\bottom_right_0[9]_i_2_n_0 ));
FDRE #(
.INIT(1'b0))
\bottom_right_0_reg[0]
(.C(clk_x16),
.CE(\bottom_right_0[15]_i_1_n_0 ),
.D(p_0_out[0]),
.Q(\bottom_right_0_reg_n_0_[0] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\bottom_right_0_reg[10]
(.C(clk_x16),
.CE(\bottom_right_0[15]_i_1_n_0 ),
.D(p_0_out[10]),
.Q(\bottom_right_0_reg_n_0_[10] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\bottom_right_0_reg[11]
(.C(clk_x16),
.CE(\bottom_right_0[15]_i_1_n_0 ),
.D(p_0_out[11]),
.Q(\bottom_right_0_reg_n_0_[11] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\bottom_right_0_reg[12]
(.C(clk_x16),
.CE(\bottom_right_0[15]_i_1_n_0 ),
.D(p_0_out[12]),
.Q(\bottom_right_0_reg_n_0_[12] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\bottom_right_0_reg[13]
(.C(clk_x16),
.CE(\bottom_right_0[15]_i_1_n_0 ),
.D(p_0_out[13]),
.Q(\bottom_right_0_reg_n_0_[13] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\bottom_right_0_reg[14]
(.C(clk_x16),
.CE(\bottom_right_0[15]_i_1_n_0 ),
.D(p_0_out[14]),
.Q(\bottom_right_0_reg_n_0_[14] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\bottom_right_0_reg[15]
(.C(clk_x16),
.CE(\bottom_right_0[15]_i_1_n_0 ),
.D(p_0_out[15]),
.Q(\bottom_right_0_reg_n_0_[15] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\bottom_right_0_reg[1]
(.C(clk_x16),
.CE(\bottom_right_0[15]_i_1_n_0 ),
.D(p_0_out[1]),
.Q(\bottom_right_0_reg_n_0_[1] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\bottom_right_0_reg[2]
(.C(clk_x16),
.CE(\bottom_right_0[15]_i_1_n_0 ),
.D(p_0_out[2]),
.Q(\bottom_right_0_reg_n_0_[2] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\bottom_right_0_reg[3]
(.C(clk_x16),
.CE(\bottom_right_0[15]_i_1_n_0 ),
.D(p_0_out[3]),
.Q(\bottom_right_0_reg_n_0_[3] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\bottom_right_0_reg[4]
(.C(clk_x16),
.CE(\bottom_right_0[15]_i_1_n_0 ),
.D(p_0_out[4]),
.Q(\bottom_right_0_reg_n_0_[4] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\bottom_right_0_reg[5]
(.C(clk_x16),
.CE(\bottom_right_0[15]_i_1_n_0 ),
.D(p_0_out[5]),
.Q(\bottom_right_0_reg_n_0_[5] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\bottom_right_0_reg[6]
(.C(clk_x16),
.CE(\bottom_right_0[15]_i_1_n_0 ),
.D(p_0_out[6]),
.Q(\bottom_right_0_reg_n_0_[6] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\bottom_right_0_reg[7]
(.C(clk_x16),
.CE(\bottom_right_0[15]_i_1_n_0 ),
.D(p_0_out[7]),
.Q(\bottom_right_0_reg_n_0_[7] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\bottom_right_0_reg[8]
(.C(clk_x16),
.CE(\bottom_right_0[15]_i_1_n_0 ),
.D(p_0_out[8]),
.Q(\bottom_right_0_reg_n_0_[8] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\bottom_right_0_reg[9]
(.C(clk_x16),
.CE(\bottom_right_0[15]_i_1_n_0 ),
.D(p_0_out[9]),
.Q(\bottom_right_0_reg_n_0_[9] ),
.R(1'b0));
LUT5 #(
.INIT(32'hB8BBB888))
\bottom_right_1[0]_i_1
(.I0(dout_0[0]),
.I1(\top_right_1[15]_i_2_n_0 ),
.I2(dout_1[0]),
.I3(\cycle_reg[2]_rep_n_0 ),
.I4(\bottom_left_0_reg_n_0_[0] ),
.O(\bottom_right_1[0]_i_1_n_0 ));
LUT5 #(
.INIT(32'hB8BBB888))
\bottom_right_1[10]_i_1
(.I0(dout_0[10]),
.I1(\top_right_1[15]_i_2_n_0 ),
.I2(dout_1[10]),
.I3(\cycle_reg[2]_rep_n_0 ),
.I4(\bottom_left_0_reg_n_0_[10] ),
.O(\bottom_right_1[10]_i_1_n_0 ));
LUT5 #(
.INIT(32'hB8BBB888))
\bottom_right_1[11]_i_1
(.I0(dout_0[11]),
.I1(\top_right_1[15]_i_2_n_0 ),
.I2(dout_1[11]),
.I3(\cycle_reg[2]_rep_n_0 ),
.I4(\bottom_left_0_reg_n_0_[11] ),
.O(\bottom_right_1[11]_i_1_n_0 ));
LUT5 #(
.INIT(32'hB8BBB888))
\bottom_right_1[12]_i_1
(.I0(dout_0[12]),
.I1(\top_right_1[15]_i_2_n_0 ),
.I2(dout_1[12]),
.I3(\cycle_reg[2]_rep_n_0 ),
.I4(\bottom_left_0_reg_n_0_[12] ),
.O(\bottom_right_1[12]_i_1_n_0 ));
LUT5 #(
.INIT(32'hB8BBB888))
\bottom_right_1[13]_i_1
(.I0(dout_0[13]),
.I1(\top_right_1[15]_i_2_n_0 ),
.I2(dout_1[13]),
.I3(\cycle_reg[2]_rep_n_0 ),
.I4(\bottom_left_0_reg_n_0_[13] ),
.O(\bottom_right_1[13]_i_1_n_0 ));
LUT5 #(
.INIT(32'hB8BBB888))
\bottom_right_1[14]_i_1
(.I0(dout_0[14]),
.I1(\top_right_1[15]_i_2_n_0 ),
.I2(dout_1[14]),
.I3(\cycle_reg[2]_rep_n_0 ),
.I4(\bottom_left_0_reg_n_0_[14] ),
.O(\bottom_right_1[14]_i_1_n_0 ));
LUT5 #(
.INIT(32'hB8BBB888))
\bottom_right_1[15]_i_1
(.I0(dout_0[15]),
.I1(\top_right_1[15]_i_2_n_0 ),
.I2(dout_1[15]),
.I3(\cycle_reg[2]_rep_n_0 ),
.I4(\bottom_left_0_reg_n_0_[15] ),
.O(\bottom_right_1[15]_i_1_n_0 ));
LUT5 #(
.INIT(32'hB8BBB888))
\bottom_right_1[1]_i_1
(.I0(dout_0[1]),
.I1(\top_right_1[15]_i_2_n_0 ),
.I2(dout_1[1]),
.I3(\cycle_reg[2]_rep_n_0 ),
.I4(\bottom_left_0_reg_n_0_[1] ),
.O(\bottom_right_1[1]_i_1_n_0 ));
LUT5 #(
.INIT(32'hB8BBB888))
\bottom_right_1[2]_i_1
(.I0(dout_0[2]),
.I1(\top_right_1[15]_i_2_n_0 ),
.I2(dout_1[2]),
.I3(\cycle_reg[2]_rep_n_0 ),
.I4(\bottom_left_0_reg_n_0_[2] ),
.O(\bottom_right_1[2]_i_1_n_0 ));
LUT5 #(
.INIT(32'hB8BBB888))
\bottom_right_1[3]_i_1
(.I0(dout_0[3]),
.I1(\top_right_1[15]_i_2_n_0 ),
.I2(dout_1[3]),
.I3(\cycle_reg[2]_rep_n_0 ),
.I4(\bottom_left_0_reg_n_0_[3] ),
.O(\bottom_right_1[3]_i_1_n_0 ));
LUT5 #(
.INIT(32'hB8BBB888))
\bottom_right_1[4]_i_1
(.I0(dout_0[4]),
.I1(\top_right_1[15]_i_2_n_0 ),
.I2(dout_1[4]),
.I3(\cycle_reg[2]_rep_n_0 ),
.I4(\bottom_left_0_reg_n_0_[4] ),
.O(\bottom_right_1[4]_i_1_n_0 ));
LUT5 #(
.INIT(32'hB8BBB888))
\bottom_right_1[5]_i_1
(.I0(dout_0[5]),
.I1(\top_right_1[15]_i_2_n_0 ),
.I2(dout_1[5]),
.I3(\cycle_reg[2]_rep_n_0 ),
.I4(\bottom_left_0_reg_n_0_[5] ),
.O(\bottom_right_1[5]_i_1_n_0 ));
LUT5 #(
.INIT(32'hB8BBB888))
\bottom_right_1[6]_i_1
(.I0(dout_0[6]),
.I1(\top_right_1[15]_i_2_n_0 ),
.I2(dout_1[6]),
.I3(\cycle_reg[2]_rep_n_0 ),
.I4(\bottom_left_0_reg_n_0_[6] ),
.O(\bottom_right_1[6]_i_1_n_0 ));
LUT5 #(
.INIT(32'hB8BBB888))
\bottom_right_1[7]_i_1
(.I0(dout_0[7]),
.I1(\top_right_1[15]_i_2_n_0 ),
.I2(dout_1[7]),
.I3(\cycle_reg[2]_rep_n_0 ),
.I4(\bottom_left_0_reg_n_0_[7] ),
.O(\bottom_right_1[7]_i_1_n_0 ));
LUT5 #(
.INIT(32'hB8BBB888))
\bottom_right_1[8]_i_1
(.I0(dout_0[8]),
.I1(\top_right_1[15]_i_2_n_0 ),
.I2(dout_1[8]),
.I3(\cycle_reg[2]_rep_n_0 ),
.I4(\bottom_left_0_reg_n_0_[8] ),
.O(\bottom_right_1[8]_i_1_n_0 ));
LUT5 #(
.INIT(32'hB8BBB888))
\bottom_right_1[9]_i_1
(.I0(dout_0[9]),
.I1(\top_right_1[15]_i_2_n_0 ),
.I2(dout_1[9]),
.I3(\cycle_reg[2]_rep_n_0 ),
.I4(\bottom_left_0_reg_n_0_[9] ),
.O(\bottom_right_1[9]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\bottom_right_1_reg[0]
(.C(clk_x16),
.CE(bottom_right_1),
.D(\bottom_right_1[0]_i_1_n_0 ),
.Q(\bottom_right_1_reg_n_0_[0] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\bottom_right_1_reg[10]
(.C(clk_x16),
.CE(bottom_right_1),
.D(\bottom_right_1[10]_i_1_n_0 ),
.Q(\bottom_right_1_reg_n_0_[10] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\bottom_right_1_reg[11]
(.C(clk_x16),
.CE(bottom_right_1),
.D(\bottom_right_1[11]_i_1_n_0 ),
.Q(\bottom_right_1_reg_n_0_[11] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\bottom_right_1_reg[12]
(.C(clk_x16),
.CE(bottom_right_1),
.D(\bottom_right_1[12]_i_1_n_0 ),
.Q(\bottom_right_1_reg_n_0_[12] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\bottom_right_1_reg[13]
(.C(clk_x16),
.CE(bottom_right_1),
.D(\bottom_right_1[13]_i_1_n_0 ),
.Q(\bottom_right_1_reg_n_0_[13] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\bottom_right_1_reg[14]
(.C(clk_x16),
.CE(bottom_right_1),
.D(\bottom_right_1[14]_i_1_n_0 ),
.Q(\bottom_right_1_reg_n_0_[14] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\bottom_right_1_reg[15]
(.C(clk_x16),
.CE(bottom_right_1),
.D(\bottom_right_1[15]_i_1_n_0 ),
.Q(\bottom_right_1_reg_n_0_[15] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\bottom_right_1_reg[1]
(.C(clk_x16),
.CE(bottom_right_1),
.D(\bottom_right_1[1]_i_1_n_0 ),
.Q(\bottom_right_1_reg_n_0_[1] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\bottom_right_1_reg[2]
(.C(clk_x16),
.CE(bottom_right_1),
.D(\bottom_right_1[2]_i_1_n_0 ),
.Q(\bottom_right_1_reg_n_0_[2] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\bottom_right_1_reg[3]
(.C(clk_x16),
.CE(bottom_right_1),
.D(\bottom_right_1[3]_i_1_n_0 ),
.Q(\bottom_right_1_reg_n_0_[3] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\bottom_right_1_reg[4]
(.C(clk_x16),
.CE(bottom_right_1),
.D(\bottom_right_1[4]_i_1_n_0 ),
.Q(\bottom_right_1_reg_n_0_[4] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\bottom_right_1_reg[5]
(.C(clk_x16),
.CE(bottom_right_1),
.D(\bottom_right_1[5]_i_1_n_0 ),
.Q(\bottom_right_1_reg_n_0_[5] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\bottom_right_1_reg[6]
(.C(clk_x16),
.CE(bottom_right_1),
.D(\bottom_right_1[6]_i_1_n_0 ),
.Q(\bottom_right_1_reg_n_0_[6] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\bottom_right_1_reg[7]
(.C(clk_x16),
.CE(bottom_right_1),
.D(\bottom_right_1[7]_i_1_n_0 ),
.Q(\bottom_right_1_reg_n_0_[7] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\bottom_right_1_reg[8]
(.C(clk_x16),
.CE(bottom_right_1),
.D(\bottom_right_1[8]_i_1_n_0 ),
.Q(\bottom_right_1_reg_n_0_[8] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\bottom_right_1_reg[9]
(.C(clk_x16),
.CE(bottom_right_1),
.D(\bottom_right_1[9]_i_1_n_0 ),
.Q(\bottom_right_1_reg_n_0_[9] ),
.R(1'b0));
(* CHECK_LICENSE_TYPE = "blk_mem_gen_0,blk_mem_gen_v8_3_5,{}" *)
(* downgradeipidentifiedwarnings = "yes" *)
(* x_core_info = "blk_mem_gen_v8_3_5,Vivado 2016.4" *)
system_vga_hessian_0_0_blk_mem_gen_0 bram_0
(.addra({\addr_0_reg_n_0_[13] ,\addr_0_reg_n_0_[12] ,\addr_0_reg_n_0_[11] ,\addr_0_reg_n_0_[10] ,\addr_0_reg_n_0_[9] ,\addr_0_reg_n_0_[8] ,\addr_0_reg_n_0_[7] ,\addr_0_reg_n_0_[6] ,\addr_0_reg_n_0_[5] ,\addr_0_reg_n_0_[4] ,\addr_0_reg_n_0_[3] ,\addr_0_reg_n_0_[2] ,\addr_0_reg_n_0_[1] ,\addr_0_reg_n_0_[0] }),
.addrb(addr_1),
.clka(clk_x16),
.clkb(clk_x16),
.dina({\din_reg_n_0_[15] ,\din_reg_n_0_[14] ,\din_reg_n_0_[13] ,\din_reg_n_0_[12] ,\din_reg_n_0_[11] ,\din_reg_n_0_[10] ,\din_reg_n_0_[9] ,\din_reg_n_0_[8] ,\din_reg_n_0_[7] ,\din_reg_n_0_[6] ,\din_reg_n_0_[5] ,\din_reg_n_0_[4] ,\din_reg_n_0_[3] ,\din_reg_n_0_[2] ,\din_reg_n_0_[1] ,\din_reg_n_0_[0] }),
.dinb({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.douta(dout_0),
.doutb(dout_1),
.ena(1'b1),
.enb(1'b1),
.wea(wen_reg_n_0),
.web(1'b0));
LUT1 #(
.INIT(2'h1))
\cache[9][15]_i_1
(.I0(rst),
.O(\cache[9][15]_i_1_n_0 ));
LUT5 #(
.INIT(32'h08000000))
\cache[9][15]_i_2
(.I0(active),
.I1(cycle[2]),
.I2(cycle[3]),
.I3(\cycle_reg[1]_rep_n_0 ),
.I4(\cycle_reg[0]_rep_n_0 ),
.O(\cache[10]_5 ));
FDRE #(
.INIT(1'b0))
\cache_reg[0][0]
(.C(clk_x16),
.CE(\cache[10]_5 ),
.D(Lyy_2_bottom_right[0]),
.Q(\cache_reg[0]_4 [0]),
.R(\cache[9][15]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\cache_reg[0][10]
(.C(clk_x16),
.CE(\cache[10]_5 ),
.D(Lyy_2_bottom_right[10]),
.Q(\cache_reg[0]_4 [10]),
.R(\cache[9][15]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\cache_reg[0][11]
(.C(clk_x16),
.CE(\cache[10]_5 ),
.D(Lyy_2_bottom_right[11]),
.Q(\cache_reg[0]_4 [11]),
.R(\cache[9][15]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\cache_reg[0][12]
(.C(clk_x16),
.CE(\cache[10]_5 ),
.D(Lyy_2_bottom_right[12]),
.Q(\cache_reg[0]_4 [12]),
.R(\cache[9][15]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\cache_reg[0][13]
(.C(clk_x16),
.CE(\cache[10]_5 ),
.D(Lyy_2_bottom_right[13]),
.Q(\cache_reg[0]_4 [13]),
.R(\cache[9][15]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\cache_reg[0][14]
(.C(clk_x16),
.CE(\cache[10]_5 ),
.D(Lyy_2_bottom_right[14]),
.Q(\cache_reg[0]_4 [14]),
.R(\cache[9][15]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\cache_reg[0][15]
(.C(clk_x16),
.CE(\cache[10]_5 ),
.D(Lyy_2_bottom_right[15]),
.Q(\cache_reg[0]_4 [15]),
.R(\cache[9][15]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\cache_reg[0][1]
(.C(clk_x16),
.CE(\cache[10]_5 ),
.D(Lyy_2_bottom_right[1]),
.Q(\cache_reg[0]_4 [1]),
.R(\cache[9][15]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\cache_reg[0][2]
(.C(clk_x16),
.CE(\cache[10]_5 ),
.D(Lyy_2_bottom_right[2]),
.Q(\cache_reg[0]_4 [2]),
.R(\cache[9][15]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\cache_reg[0][3]
(.C(clk_x16),
.CE(\cache[10]_5 ),
.D(Lyy_2_bottom_right[3]),
.Q(\cache_reg[0]_4 [3]),
.R(\cache[9][15]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\cache_reg[0][4]
(.C(clk_x16),
.CE(\cache[10]_5 ),
.D(Lyy_2_bottom_right[4]),
.Q(\cache_reg[0]_4 [4]),
.R(\cache[9][15]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\cache_reg[0][5]
(.C(clk_x16),
.CE(\cache[10]_5 ),
.D(Lyy_2_bottom_right[5]),
.Q(\cache_reg[0]_4 [5]),
.R(\cache[9][15]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\cache_reg[0][6]
(.C(clk_x16),
.CE(\cache[10]_5 ),
.D(Lyy_2_bottom_right[6]),
.Q(\cache_reg[0]_4 [6]),
.R(\cache[9][15]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\cache_reg[0][7]
(.C(clk_x16),
.CE(\cache[10]_5 ),
.D(Lyy_2_bottom_right[7]),
.Q(\cache_reg[0]_4 [7]),
.R(\cache[9][15]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\cache_reg[0][8]
(.C(clk_x16),
.CE(\cache[10]_5 ),
.D(Lyy_2_bottom_right[8]),
.Q(\cache_reg[0]_4 [8]),
.R(\cache[9][15]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\cache_reg[0][9]
(.C(clk_x16),
.CE(\cache[10]_5 ),
.D(Lyy_2_bottom_right[9]),
.Q(\cache_reg[0]_4 [9]),
.R(\cache[9][15]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\cache_reg[10][0]
(.C(clk_x16),
.CE(\cache[10]_5 ),
.D(\cache_reg[9]_2 [0]),
.Q(\cache_reg[10]_3 [0]),
.R(\cache[9][15]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\cache_reg[10][10]
(.C(clk_x16),
.CE(\cache[10]_5 ),
.D(\cache_reg[9]_2 [10]),
.Q(\cache_reg[10]_3 [10]),
.R(\cache[9][15]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\cache_reg[10][11]
(.C(clk_x16),
.CE(\cache[10]_5 ),
.D(\cache_reg[9]_2 [11]),
.Q(\cache_reg[10]_3 [11]),
.R(\cache[9][15]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\cache_reg[10][12]
(.C(clk_x16),
.CE(\cache[10]_5 ),
.D(\cache_reg[9]_2 [12]),
.Q(\cache_reg[10]_3 [12]),
.R(\cache[9][15]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\cache_reg[10][13]
(.C(clk_x16),
.CE(\cache[10]_5 ),
.D(\cache_reg[9]_2 [13]),
.Q(\cache_reg[10]_3 [13]),
.R(\cache[9][15]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\cache_reg[10][14]
(.C(clk_x16),
.CE(\cache[10]_5 ),
.D(\cache_reg[9]_2 [14]),
.Q(\cache_reg[10]_3 [14]),
.R(\cache[9][15]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\cache_reg[10][15]
(.C(clk_x16),
.CE(\cache[10]_5 ),
.D(\cache_reg[9]_2 [15]),
.Q(\cache_reg[10]_3 [15]),
.R(\cache[9][15]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\cache_reg[10][1]
(.C(clk_x16),
.CE(\cache[10]_5 ),
.D(\cache_reg[9]_2 [1]),
.Q(\cache_reg[10]_3 [1]),
.R(\cache[9][15]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\cache_reg[10][2]
(.C(clk_x16),
.CE(\cache[10]_5 ),
.D(\cache_reg[9]_2 [2]),
.Q(\cache_reg[10]_3 [2]),
.R(\cache[9][15]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\cache_reg[10][3]
(.C(clk_x16),
.CE(\cache[10]_5 ),
.D(\cache_reg[9]_2 [3]),
.Q(\cache_reg[10]_3 [3]),
.R(\cache[9][15]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\cache_reg[10][4]
(.C(clk_x16),
.CE(\cache[10]_5 ),
.D(\cache_reg[9]_2 [4]),
.Q(\cache_reg[10]_3 [4]),
.R(\cache[9][15]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\cache_reg[10][5]
(.C(clk_x16),
.CE(\cache[10]_5 ),
.D(\cache_reg[9]_2 [5]),
.Q(\cache_reg[10]_3 [5]),
.R(\cache[9][15]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\cache_reg[10][6]
(.C(clk_x16),
.CE(\cache[10]_5 ),
.D(\cache_reg[9]_2 [6]),
.Q(\cache_reg[10]_3 [6]),
.R(\cache[9][15]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\cache_reg[10][7]
(.C(clk_x16),
.CE(\cache[10]_5 ),
.D(\cache_reg[9]_2 [7]),
.Q(\cache_reg[10]_3 [7]),
.R(\cache[9][15]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\cache_reg[10][8]
(.C(clk_x16),
.CE(\cache[10]_5 ),
.D(\cache_reg[9]_2 [8]),
.Q(\cache_reg[10]_3 [8]),
.R(\cache[9][15]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\cache_reg[10][9]
(.C(clk_x16),
.CE(\cache[10]_5 ),
.D(\cache_reg[9]_2 [9]),
.Q(\cache_reg[10]_3 [9]),
.R(\cache[9][15]_i_1_n_0 ));
(* srl_bus_name = "\U0/cache_reg[2] " *)
(* srl_name = "\U0/cache_reg[2][0]_srl2___U0_cache_reg_r_0 " *)
SRL16E #(
.INIT(16'h0000))
\cache_reg[2][0]_srl2___U0_cache_reg_r_0
(.A0(1'b1),
.A1(1'b0),
.A2(1'b0),
.A3(1'b0),
.CE(\cache[10]_5 ),
.CLK(clk_x16),
.D(\cache_reg[0]_4 [0]),
.Q(\cache_reg[2][0]_srl2___U0_cache_reg_r_0_n_0 ));
(* srl_bus_name = "\U0/cache_reg[2] " *)
(* srl_name = "\U0/cache_reg[2][10]_srl2___U0_cache_reg_r_0 " *)
SRL16E #(
.INIT(16'h0000))
\cache_reg[2][10]_srl2___U0_cache_reg_r_0
(.A0(1'b1),
.A1(1'b0),
.A2(1'b0),
.A3(1'b0),
.CE(\cache[10]_5 ),
.CLK(clk_x16),
.D(\cache_reg[0]_4 [10]),
.Q(\cache_reg[2][10]_srl2___U0_cache_reg_r_0_n_0 ));
(* srl_bus_name = "\U0/cache_reg[2] " *)
(* srl_name = "\U0/cache_reg[2][11]_srl2___U0_cache_reg_r_0 " *)
SRL16E #(
.INIT(16'h0000))
\cache_reg[2][11]_srl2___U0_cache_reg_r_0
(.A0(1'b1),
.A1(1'b0),
.A2(1'b0),
.A3(1'b0),
.CE(\cache[10]_5 ),
.CLK(clk_x16),
.D(\cache_reg[0]_4 [11]),
.Q(\cache_reg[2][11]_srl2___U0_cache_reg_r_0_n_0 ));
(* srl_bus_name = "\U0/cache_reg[2] " *)
(* srl_name = "\U0/cache_reg[2][12]_srl2___U0_cache_reg_r_0 " *)
SRL16E #(
.INIT(16'h0000))
\cache_reg[2][12]_srl2___U0_cache_reg_r_0
(.A0(1'b1),
.A1(1'b0),
.A2(1'b0),
.A3(1'b0),
.CE(\cache[10]_5 ),
.CLK(clk_x16),
.D(\cache_reg[0]_4 [12]),
.Q(\cache_reg[2][12]_srl2___U0_cache_reg_r_0_n_0 ));
(* srl_bus_name = "\U0/cache_reg[2] " *)
(* srl_name = "\U0/cache_reg[2][13]_srl2___U0_cache_reg_r_0 " *)
SRL16E #(
.INIT(16'h0000))
\cache_reg[2][13]_srl2___U0_cache_reg_r_0
(.A0(1'b1),
.A1(1'b0),
.A2(1'b0),
.A3(1'b0),
.CE(\cache[10]_5 ),
.CLK(clk_x16),
.D(\cache_reg[0]_4 [13]),
.Q(\cache_reg[2][13]_srl2___U0_cache_reg_r_0_n_0 ));
(* srl_bus_name = "\U0/cache_reg[2] " *)
(* srl_name = "\U0/cache_reg[2][14]_srl2___U0_cache_reg_r_0 " *)
SRL16E #(
.INIT(16'h0000))
\cache_reg[2][14]_srl2___U0_cache_reg_r_0
(.A0(1'b1),
.A1(1'b0),
.A2(1'b0),
.A3(1'b0),
.CE(\cache[10]_5 ),
.CLK(clk_x16),
.D(\cache_reg[0]_4 [14]),
.Q(\cache_reg[2][14]_srl2___U0_cache_reg_r_0_n_0 ));
(* srl_bus_name = "\U0/cache_reg[2] " *)
(* srl_name = "\U0/cache_reg[2][15]_srl2___U0_cache_reg_r_0 " *)
SRL16E #(
.INIT(16'h0000))
\cache_reg[2][15]_srl2___U0_cache_reg_r_0
(.A0(1'b1),
.A1(1'b0),
.A2(1'b0),
.A3(1'b0),
.CE(\cache[10]_5 ),
.CLK(clk_x16),
.D(\cache_reg[0]_4 [15]),
.Q(\cache_reg[2][15]_srl2___U0_cache_reg_r_0_n_0 ));
(* srl_bus_name = "\U0/cache_reg[2] " *)
(* srl_name = "\U0/cache_reg[2][1]_srl2___U0_cache_reg_r_0 " *)
SRL16E #(
.INIT(16'h0000))
\cache_reg[2][1]_srl2___U0_cache_reg_r_0
(.A0(1'b1),
.A1(1'b0),
.A2(1'b0),
.A3(1'b0),
.CE(\cache[10]_5 ),
.CLK(clk_x16),
.D(\cache_reg[0]_4 [1]),
.Q(\cache_reg[2][1]_srl2___U0_cache_reg_r_0_n_0 ));
(* srl_bus_name = "\U0/cache_reg[2] " *)
(* srl_name = "\U0/cache_reg[2][2]_srl2___U0_cache_reg_r_0 " *)
SRL16E #(
.INIT(16'h0000))
\cache_reg[2][2]_srl2___U0_cache_reg_r_0
(.A0(1'b1),
.A1(1'b0),
.A2(1'b0),
.A3(1'b0),
.CE(\cache[10]_5 ),
.CLK(clk_x16),
.D(\cache_reg[0]_4 [2]),
.Q(\cache_reg[2][2]_srl2___U0_cache_reg_r_0_n_0 ));
(* srl_bus_name = "\U0/cache_reg[2] " *)
(* srl_name = "\U0/cache_reg[2][3]_srl2___U0_cache_reg_r_0 " *)
SRL16E #(
.INIT(16'h0000))
\cache_reg[2][3]_srl2___U0_cache_reg_r_0
(.A0(1'b1),
.A1(1'b0),
.A2(1'b0),
.A3(1'b0),
.CE(\cache[10]_5 ),
.CLK(clk_x16),
.D(\cache_reg[0]_4 [3]),
.Q(\cache_reg[2][3]_srl2___U0_cache_reg_r_0_n_0 ));
(* srl_bus_name = "\U0/cache_reg[2] " *)
(* srl_name = "\U0/cache_reg[2][4]_srl2___U0_cache_reg_r_0 " *)
SRL16E #(
.INIT(16'h0000))
\cache_reg[2][4]_srl2___U0_cache_reg_r_0
(.A0(1'b1),
.A1(1'b0),
.A2(1'b0),
.A3(1'b0),
.CE(\cache[10]_5 ),
.CLK(clk_x16),
.D(\cache_reg[0]_4 [4]),
.Q(\cache_reg[2][4]_srl2___U0_cache_reg_r_0_n_0 ));
(* srl_bus_name = "\U0/cache_reg[2] " *)
(* srl_name = "\U0/cache_reg[2][5]_srl2___U0_cache_reg_r_0 " *)
SRL16E #(
.INIT(16'h0000))
\cache_reg[2][5]_srl2___U0_cache_reg_r_0
(.A0(1'b1),
.A1(1'b0),
.A2(1'b0),
.A3(1'b0),
.CE(\cache[10]_5 ),
.CLK(clk_x16),
.D(\cache_reg[0]_4 [5]),
.Q(\cache_reg[2][5]_srl2___U0_cache_reg_r_0_n_0 ));
(* srl_bus_name = "\U0/cache_reg[2] " *)
(* srl_name = "\U0/cache_reg[2][6]_srl2___U0_cache_reg_r_0 " *)
SRL16E #(
.INIT(16'h0000))
\cache_reg[2][6]_srl2___U0_cache_reg_r_0
(.A0(1'b1),
.A1(1'b0),
.A2(1'b0),
.A3(1'b0),
.CE(\cache[10]_5 ),
.CLK(clk_x16),
.D(\cache_reg[0]_4 [6]),
.Q(\cache_reg[2][6]_srl2___U0_cache_reg_r_0_n_0 ));
(* srl_bus_name = "\U0/cache_reg[2] " *)
(* srl_name = "\U0/cache_reg[2][7]_srl2___U0_cache_reg_r_0 " *)
SRL16E #(
.INIT(16'h0000))
\cache_reg[2][7]_srl2___U0_cache_reg_r_0
(.A0(1'b1),
.A1(1'b0),
.A2(1'b0),
.A3(1'b0),
.CE(\cache[10]_5 ),
.CLK(clk_x16),
.D(\cache_reg[0]_4 [7]),
.Q(\cache_reg[2][7]_srl2___U0_cache_reg_r_0_n_0 ));
(* srl_bus_name = "\U0/cache_reg[2] " *)
(* srl_name = "\U0/cache_reg[2][8]_srl2___U0_cache_reg_r_0 " *)
SRL16E #(
.INIT(16'h0000))
\cache_reg[2][8]_srl2___U0_cache_reg_r_0
(.A0(1'b1),
.A1(1'b0),
.A2(1'b0),
.A3(1'b0),
.CE(\cache[10]_5 ),
.CLK(clk_x16),
.D(\cache_reg[0]_4 [8]),
.Q(\cache_reg[2][8]_srl2___U0_cache_reg_r_0_n_0 ));
(* srl_bus_name = "\U0/cache_reg[2] " *)
(* srl_name = "\U0/cache_reg[2][9]_srl2___U0_cache_reg_r_0 " *)
SRL16E #(
.INIT(16'h0000))
\cache_reg[2][9]_srl2___U0_cache_reg_r_0
(.A0(1'b1),
.A1(1'b0),
.A2(1'b0),
.A3(1'b0),
.CE(\cache[10]_5 ),
.CLK(clk_x16),
.D(\cache_reg[0]_4 [9]),
.Q(\cache_reg[2][9]_srl2___U0_cache_reg_r_0_n_0 ));
FDRE \cache_reg[3][0]_U0_cache_reg_r_1
(.C(clk_x16),
.CE(\cache[10]_5 ),
.D(\cache_reg[2][0]_srl2___U0_cache_reg_r_0_n_0 ),
.Q(\cache_reg[3][0]_U0_cache_reg_r_1_n_0 ),
.R(1'b0));
FDRE \cache_reg[3][10]_U0_cache_reg_r_1
(.C(clk_x16),
.CE(\cache[10]_5 ),
.D(\cache_reg[2][10]_srl2___U0_cache_reg_r_0_n_0 ),
.Q(\cache_reg[3][10]_U0_cache_reg_r_1_n_0 ),
.R(1'b0));
FDRE \cache_reg[3][11]_U0_cache_reg_r_1
(.C(clk_x16),
.CE(\cache[10]_5 ),
.D(\cache_reg[2][11]_srl2___U0_cache_reg_r_0_n_0 ),
.Q(\cache_reg[3][11]_U0_cache_reg_r_1_n_0 ),
.R(1'b0));
FDRE \cache_reg[3][12]_U0_cache_reg_r_1
(.C(clk_x16),
.CE(\cache[10]_5 ),
.D(\cache_reg[2][12]_srl2___U0_cache_reg_r_0_n_0 ),
.Q(\cache_reg[3][12]_U0_cache_reg_r_1_n_0 ),
.R(1'b0));
FDRE \cache_reg[3][13]_U0_cache_reg_r_1
(.C(clk_x16),
.CE(\cache[10]_5 ),
.D(\cache_reg[2][13]_srl2___U0_cache_reg_r_0_n_0 ),
.Q(\cache_reg[3][13]_U0_cache_reg_r_1_n_0 ),
.R(1'b0));
FDRE \cache_reg[3][14]_U0_cache_reg_r_1
(.C(clk_x16),
.CE(\cache[10]_5 ),
.D(\cache_reg[2][14]_srl2___U0_cache_reg_r_0_n_0 ),
.Q(\cache_reg[3][14]_U0_cache_reg_r_1_n_0 ),
.R(1'b0));
FDRE \cache_reg[3][15]_U0_cache_reg_r_1
(.C(clk_x16),
.CE(\cache[10]_5 ),
.D(\cache_reg[2][15]_srl2___U0_cache_reg_r_0_n_0 ),
.Q(\cache_reg[3][15]_U0_cache_reg_r_1_n_0 ),
.R(1'b0));
FDRE \cache_reg[3][1]_U0_cache_reg_r_1
(.C(clk_x16),
.CE(\cache[10]_5 ),
.D(\cache_reg[2][1]_srl2___U0_cache_reg_r_0_n_0 ),
.Q(\cache_reg[3][1]_U0_cache_reg_r_1_n_0 ),
.R(1'b0));
FDRE \cache_reg[3][2]_U0_cache_reg_r_1
(.C(clk_x16),
.CE(\cache[10]_5 ),
.D(\cache_reg[2][2]_srl2___U0_cache_reg_r_0_n_0 ),
.Q(\cache_reg[3][2]_U0_cache_reg_r_1_n_0 ),
.R(1'b0));
FDRE \cache_reg[3][3]_U0_cache_reg_r_1
(.C(clk_x16),
.CE(\cache[10]_5 ),
.D(\cache_reg[2][3]_srl2___U0_cache_reg_r_0_n_0 ),
.Q(\cache_reg[3][3]_U0_cache_reg_r_1_n_0 ),
.R(1'b0));
FDRE \cache_reg[3][4]_U0_cache_reg_r_1
(.C(clk_x16),
.CE(\cache[10]_5 ),
.D(\cache_reg[2][4]_srl2___U0_cache_reg_r_0_n_0 ),
.Q(\cache_reg[3][4]_U0_cache_reg_r_1_n_0 ),
.R(1'b0));
FDRE \cache_reg[3][5]_U0_cache_reg_r_1
(.C(clk_x16),
.CE(\cache[10]_5 ),
.D(\cache_reg[2][5]_srl2___U0_cache_reg_r_0_n_0 ),
.Q(\cache_reg[3][5]_U0_cache_reg_r_1_n_0 ),
.R(1'b0));
FDRE \cache_reg[3][6]_U0_cache_reg_r_1
(.C(clk_x16),
.CE(\cache[10]_5 ),
.D(\cache_reg[2][6]_srl2___U0_cache_reg_r_0_n_0 ),
.Q(\cache_reg[3][6]_U0_cache_reg_r_1_n_0 ),
.R(1'b0));
FDRE \cache_reg[3][7]_U0_cache_reg_r_1
(.C(clk_x16),
.CE(\cache[10]_5 ),
.D(\cache_reg[2][7]_srl2___U0_cache_reg_r_0_n_0 ),
.Q(\cache_reg[3][7]_U0_cache_reg_r_1_n_0 ),
.R(1'b0));
FDRE \cache_reg[3][8]_U0_cache_reg_r_1
(.C(clk_x16),
.CE(\cache[10]_5 ),
.D(\cache_reg[2][8]_srl2___U0_cache_reg_r_0_n_0 ),
.Q(\cache_reg[3][8]_U0_cache_reg_r_1_n_0 ),
.R(1'b0));
FDRE \cache_reg[3][9]_U0_cache_reg_r_1
(.C(clk_x16),
.CE(\cache[10]_5 ),
.D(\cache_reg[2][9]_srl2___U0_cache_reg_r_0_n_0 ),
.Q(\cache_reg[3][9]_U0_cache_reg_r_1_n_0 ),
.R(1'b0));
FDRE \cache_reg[4][0]
(.C(clk_x16),
.CE(\cache[10]_5 ),
.D(cache_reg_gate__14_n_0),
.Q(\cache_reg[4]_0 [0]),
.R(\cache[9][15]_i_1_n_0 ));
FDRE \cache_reg[4][10]
(.C(clk_x16),
.CE(\cache[10]_5 ),
.D(cache_reg_gate__4_n_0),
.Q(\cache_reg[4]_0 [10]),
.R(\cache[9][15]_i_1_n_0 ));
FDRE \cache_reg[4][11]
(.C(clk_x16),
.CE(\cache[10]_5 ),
.D(cache_reg_gate__3_n_0),
.Q(\cache_reg[4]_0 [11]),
.R(\cache[9][15]_i_1_n_0 ));
FDRE \cache_reg[4][12]
(.C(clk_x16),
.CE(\cache[10]_5 ),
.D(cache_reg_gate__2_n_0),
.Q(\cache_reg[4]_0 [12]),
.R(\cache[9][15]_i_1_n_0 ));
FDRE \cache_reg[4][13]
(.C(clk_x16),
.CE(\cache[10]_5 ),
.D(cache_reg_gate__1_n_0),
.Q(\cache_reg[4]_0 [13]),
.R(\cache[9][15]_i_1_n_0 ));
FDRE \cache_reg[4][14]
(.C(clk_x16),
.CE(\cache[10]_5 ),
.D(cache_reg_gate__0_n_0),
.Q(\cache_reg[4]_0 [14]),
.R(\cache[9][15]_i_1_n_0 ));
FDRE \cache_reg[4][15]
(.C(clk_x16),
.CE(\cache[10]_5 ),
.D(cache_reg_gate_n_0),
.Q(\cache_reg[4]_0 [15]),
.R(\cache[9][15]_i_1_n_0 ));
FDRE \cache_reg[4][1]
(.C(clk_x16),
.CE(\cache[10]_5 ),
.D(cache_reg_gate__13_n_0),
.Q(\cache_reg[4]_0 [1]),
.R(\cache[9][15]_i_1_n_0 ));
FDRE \cache_reg[4][2]
(.C(clk_x16),
.CE(\cache[10]_5 ),
.D(cache_reg_gate__12_n_0),
.Q(\cache_reg[4]_0 [2]),
.R(\cache[9][15]_i_1_n_0 ));
FDRE \cache_reg[4][3]
(.C(clk_x16),
.CE(\cache[10]_5 ),
.D(cache_reg_gate__11_n_0),
.Q(\cache_reg[4]_0 [3]),
.R(\cache[9][15]_i_1_n_0 ));
FDRE \cache_reg[4][4]
(.C(clk_x16),
.CE(\cache[10]_5 ),
.D(cache_reg_gate__10_n_0),
.Q(\cache_reg[4]_0 [4]),
.R(\cache[9][15]_i_1_n_0 ));
FDRE \cache_reg[4][5]
(.C(clk_x16),
.CE(\cache[10]_5 ),
.D(cache_reg_gate__9_n_0),
.Q(\cache_reg[4]_0 [5]),
.R(\cache[9][15]_i_1_n_0 ));
FDRE \cache_reg[4][6]
(.C(clk_x16),
.CE(\cache[10]_5 ),
.D(cache_reg_gate__8_n_0),
.Q(\cache_reg[4]_0 [6]),
.R(\cache[9][15]_i_1_n_0 ));
FDRE \cache_reg[4][7]
(.C(clk_x16),
.CE(\cache[10]_5 ),
.D(cache_reg_gate__7_n_0),
.Q(\cache_reg[4]_0 [7]),
.R(\cache[9][15]_i_1_n_0 ));
FDRE \cache_reg[4][8]
(.C(clk_x16),
.CE(\cache[10]_5 ),
.D(cache_reg_gate__6_n_0),
.Q(\cache_reg[4]_0 [8]),
.R(\cache[9][15]_i_1_n_0 ));
FDRE \cache_reg[4][9]
(.C(clk_x16),
.CE(\cache[10]_5 ),
.D(cache_reg_gate__5_n_0),
.Q(\cache_reg[4]_0 [9]),
.R(\cache[9][15]_i_1_n_0 ));
(* srl_bus_name = "\U0/cache_reg[6] " *)
(* srl_name = "\U0/cache_reg[6][0]_srl2___U0_cache_reg_r_0 " *)
SRL16E #(
.INIT(16'h0000))
\cache_reg[6][0]_srl2___U0_cache_reg_r_0
(.A0(1'b1),
.A1(1'b0),
.A2(1'b0),
.A3(1'b0),
.CE(\cache[10]_5 ),
.CLK(clk_x16),
.D(\cache_reg[4]_0 [0]),
.Q(\cache_reg[6][0]_srl2___U0_cache_reg_r_0_n_0 ));
(* srl_bus_name = "\U0/cache_reg[6] " *)
(* srl_name = "\U0/cache_reg[6][10]_srl2___U0_cache_reg_r_0 " *)
SRL16E #(
.INIT(16'h0000))
\cache_reg[6][10]_srl2___U0_cache_reg_r_0
(.A0(1'b1),
.A1(1'b0),
.A2(1'b0),
.A3(1'b0),
.CE(\cache[10]_5 ),
.CLK(clk_x16),
.D(\cache_reg[4]_0 [10]),
.Q(\cache_reg[6][10]_srl2___U0_cache_reg_r_0_n_0 ));
(* srl_bus_name = "\U0/cache_reg[6] " *)
(* srl_name = "\U0/cache_reg[6][11]_srl2___U0_cache_reg_r_0 " *)
SRL16E #(
.INIT(16'h0000))
\cache_reg[6][11]_srl2___U0_cache_reg_r_0
(.A0(1'b1),
.A1(1'b0),
.A2(1'b0),
.A3(1'b0),
.CE(\cache[10]_5 ),
.CLK(clk_x16),
.D(\cache_reg[4]_0 [11]),
.Q(\cache_reg[6][11]_srl2___U0_cache_reg_r_0_n_0 ));
(* srl_bus_name = "\U0/cache_reg[6] " *)
(* srl_name = "\U0/cache_reg[6][12]_srl2___U0_cache_reg_r_0 " *)
SRL16E #(
.INIT(16'h0000))
\cache_reg[6][12]_srl2___U0_cache_reg_r_0
(.A0(1'b1),
.A1(1'b0),
.A2(1'b0),
.A3(1'b0),
.CE(\cache[10]_5 ),
.CLK(clk_x16),
.D(\cache_reg[4]_0 [12]),
.Q(\cache_reg[6][12]_srl2___U0_cache_reg_r_0_n_0 ));
(* srl_bus_name = "\U0/cache_reg[6] " *)
(* srl_name = "\U0/cache_reg[6][13]_srl2___U0_cache_reg_r_0 " *)
SRL16E #(
.INIT(16'h0000))
\cache_reg[6][13]_srl2___U0_cache_reg_r_0
(.A0(1'b1),
.A1(1'b0),
.A2(1'b0),
.A3(1'b0),
.CE(\cache[10]_5 ),
.CLK(clk_x16),
.D(\cache_reg[4]_0 [13]),
.Q(\cache_reg[6][13]_srl2___U0_cache_reg_r_0_n_0 ));
(* srl_bus_name = "\U0/cache_reg[6] " *)
(* srl_name = "\U0/cache_reg[6][14]_srl2___U0_cache_reg_r_0 " *)
SRL16E #(
.INIT(16'h0000))
\cache_reg[6][14]_srl2___U0_cache_reg_r_0
(.A0(1'b1),
.A1(1'b0),
.A2(1'b0),
.A3(1'b0),
.CE(\cache[10]_5 ),
.CLK(clk_x16),
.D(\cache_reg[4]_0 [14]),
.Q(\cache_reg[6][14]_srl2___U0_cache_reg_r_0_n_0 ));
(* srl_bus_name = "\U0/cache_reg[6] " *)
(* srl_name = "\U0/cache_reg[6][15]_srl2___U0_cache_reg_r_0 " *)
SRL16E #(
.INIT(16'h0000))
\cache_reg[6][15]_srl2___U0_cache_reg_r_0
(.A0(1'b1),
.A1(1'b0),
.A2(1'b0),
.A3(1'b0),
.CE(\cache[10]_5 ),
.CLK(clk_x16),
.D(\cache_reg[4]_0 [15]),
.Q(\cache_reg[6][15]_srl2___U0_cache_reg_r_0_n_0 ));
(* srl_bus_name = "\U0/cache_reg[6] " *)
(* srl_name = "\U0/cache_reg[6][1]_srl2___U0_cache_reg_r_0 " *)
SRL16E #(
.INIT(16'h0000))
\cache_reg[6][1]_srl2___U0_cache_reg_r_0
(.A0(1'b1),
.A1(1'b0),
.A2(1'b0),
.A3(1'b0),
.CE(\cache[10]_5 ),
.CLK(clk_x16),
.D(\cache_reg[4]_0 [1]),
.Q(\cache_reg[6][1]_srl2___U0_cache_reg_r_0_n_0 ));
(* srl_bus_name = "\U0/cache_reg[6] " *)
(* srl_name = "\U0/cache_reg[6][2]_srl2___U0_cache_reg_r_0 " *)
SRL16E #(
.INIT(16'h0000))
\cache_reg[6][2]_srl2___U0_cache_reg_r_0
(.A0(1'b1),
.A1(1'b0),
.A2(1'b0),
.A3(1'b0),
.CE(\cache[10]_5 ),
.CLK(clk_x16),
.D(\cache_reg[4]_0 [2]),
.Q(\cache_reg[6][2]_srl2___U0_cache_reg_r_0_n_0 ));
(* srl_bus_name = "\U0/cache_reg[6] " *)
(* srl_name = "\U0/cache_reg[6][3]_srl2___U0_cache_reg_r_0 " *)
SRL16E #(
.INIT(16'h0000))
\cache_reg[6][3]_srl2___U0_cache_reg_r_0
(.A0(1'b1),
.A1(1'b0),
.A2(1'b0),
.A3(1'b0),
.CE(\cache[10]_5 ),
.CLK(clk_x16),
.D(\cache_reg[4]_0 [3]),
.Q(\cache_reg[6][3]_srl2___U0_cache_reg_r_0_n_0 ));
(* srl_bus_name = "\U0/cache_reg[6] " *)
(* srl_name = "\U0/cache_reg[6][4]_srl2___U0_cache_reg_r_0 " *)
SRL16E #(
.INIT(16'h0000))
\cache_reg[6][4]_srl2___U0_cache_reg_r_0
(.A0(1'b1),
.A1(1'b0),
.A2(1'b0),
.A3(1'b0),
.CE(\cache[10]_5 ),
.CLK(clk_x16),
.D(\cache_reg[4]_0 [4]),
.Q(\cache_reg[6][4]_srl2___U0_cache_reg_r_0_n_0 ));
(* srl_bus_name = "\U0/cache_reg[6] " *)
(* srl_name = "\U0/cache_reg[6][5]_srl2___U0_cache_reg_r_0 " *)
SRL16E #(
.INIT(16'h0000))
\cache_reg[6][5]_srl2___U0_cache_reg_r_0
(.A0(1'b1),
.A1(1'b0),
.A2(1'b0),
.A3(1'b0),
.CE(\cache[10]_5 ),
.CLK(clk_x16),
.D(\cache_reg[4]_0 [5]),
.Q(\cache_reg[6][5]_srl2___U0_cache_reg_r_0_n_0 ));
(* srl_bus_name = "\U0/cache_reg[6] " *)
(* srl_name = "\U0/cache_reg[6][6]_srl2___U0_cache_reg_r_0 " *)
SRL16E #(
.INIT(16'h0000))
\cache_reg[6][6]_srl2___U0_cache_reg_r_0
(.A0(1'b1),
.A1(1'b0),
.A2(1'b0),
.A3(1'b0),
.CE(\cache[10]_5 ),
.CLK(clk_x16),
.D(\cache_reg[4]_0 [6]),
.Q(\cache_reg[6][6]_srl2___U0_cache_reg_r_0_n_0 ));
(* srl_bus_name = "\U0/cache_reg[6] " *)
(* srl_name = "\U0/cache_reg[6][7]_srl2___U0_cache_reg_r_0 " *)
SRL16E #(
.INIT(16'h0000))
\cache_reg[6][7]_srl2___U0_cache_reg_r_0
(.A0(1'b1),
.A1(1'b0),
.A2(1'b0),
.A3(1'b0),
.CE(\cache[10]_5 ),
.CLK(clk_x16),
.D(\cache_reg[4]_0 [7]),
.Q(\cache_reg[6][7]_srl2___U0_cache_reg_r_0_n_0 ));
(* srl_bus_name = "\U0/cache_reg[6] " *)
(* srl_name = "\U0/cache_reg[6][8]_srl2___U0_cache_reg_r_0 " *)
SRL16E #(
.INIT(16'h0000))
\cache_reg[6][8]_srl2___U0_cache_reg_r_0
(.A0(1'b1),
.A1(1'b0),
.A2(1'b0),
.A3(1'b0),
.CE(\cache[10]_5 ),
.CLK(clk_x16),
.D(\cache_reg[4]_0 [8]),
.Q(\cache_reg[6][8]_srl2___U0_cache_reg_r_0_n_0 ));
(* srl_bus_name = "\U0/cache_reg[6] " *)
(* srl_name = "\U0/cache_reg[6][9]_srl2___U0_cache_reg_r_0 " *)
SRL16E #(
.INIT(16'h0000))
\cache_reg[6][9]_srl2___U0_cache_reg_r_0
(.A0(1'b1),
.A1(1'b0),
.A2(1'b0),
.A3(1'b0),
.CE(\cache[10]_5 ),
.CLK(clk_x16),
.D(\cache_reg[4]_0 [9]),
.Q(\cache_reg[6][9]_srl2___U0_cache_reg_r_0_n_0 ));
FDRE \cache_reg[7][0]_U0_cache_reg_r_1
(.C(clk_x16),
.CE(\cache[10]_5 ),
.D(\cache_reg[6][0]_srl2___U0_cache_reg_r_0_n_0 ),
.Q(\cache_reg[7][0]_U0_cache_reg_r_1_n_0 ),
.R(1'b0));
FDRE \cache_reg[7][10]_U0_cache_reg_r_1
(.C(clk_x16),
.CE(\cache[10]_5 ),
.D(\cache_reg[6][10]_srl2___U0_cache_reg_r_0_n_0 ),
.Q(\cache_reg[7][10]_U0_cache_reg_r_1_n_0 ),
.R(1'b0));
FDRE \cache_reg[7][11]_U0_cache_reg_r_1
(.C(clk_x16),
.CE(\cache[10]_5 ),
.D(\cache_reg[6][11]_srl2___U0_cache_reg_r_0_n_0 ),
.Q(\cache_reg[7][11]_U0_cache_reg_r_1_n_0 ),
.R(1'b0));
FDRE \cache_reg[7][12]_U0_cache_reg_r_1
(.C(clk_x16),
.CE(\cache[10]_5 ),
.D(\cache_reg[6][12]_srl2___U0_cache_reg_r_0_n_0 ),
.Q(\cache_reg[7][12]_U0_cache_reg_r_1_n_0 ),
.R(1'b0));
FDRE \cache_reg[7][13]_U0_cache_reg_r_1
(.C(clk_x16),
.CE(\cache[10]_5 ),
.D(\cache_reg[6][13]_srl2___U0_cache_reg_r_0_n_0 ),
.Q(\cache_reg[7][13]_U0_cache_reg_r_1_n_0 ),
.R(1'b0));
FDRE \cache_reg[7][14]_U0_cache_reg_r_1
(.C(clk_x16),
.CE(\cache[10]_5 ),
.D(\cache_reg[6][14]_srl2___U0_cache_reg_r_0_n_0 ),
.Q(\cache_reg[7][14]_U0_cache_reg_r_1_n_0 ),
.R(1'b0));
FDRE \cache_reg[7][15]_U0_cache_reg_r_1
(.C(clk_x16),
.CE(\cache[10]_5 ),
.D(\cache_reg[6][15]_srl2___U0_cache_reg_r_0_n_0 ),
.Q(\cache_reg[7][15]_U0_cache_reg_r_1_n_0 ),
.R(1'b0));
FDRE \cache_reg[7][1]_U0_cache_reg_r_1
(.C(clk_x16),
.CE(\cache[10]_5 ),
.D(\cache_reg[6][1]_srl2___U0_cache_reg_r_0_n_0 ),
.Q(\cache_reg[7][1]_U0_cache_reg_r_1_n_0 ),
.R(1'b0));
FDRE \cache_reg[7][2]_U0_cache_reg_r_1
(.C(clk_x16),
.CE(\cache[10]_5 ),
.D(\cache_reg[6][2]_srl2___U0_cache_reg_r_0_n_0 ),
.Q(\cache_reg[7][2]_U0_cache_reg_r_1_n_0 ),
.R(1'b0));
FDRE \cache_reg[7][3]_U0_cache_reg_r_1
(.C(clk_x16),
.CE(\cache[10]_5 ),
.D(\cache_reg[6][3]_srl2___U0_cache_reg_r_0_n_0 ),
.Q(\cache_reg[7][3]_U0_cache_reg_r_1_n_0 ),
.R(1'b0));
FDRE \cache_reg[7][4]_U0_cache_reg_r_1
(.C(clk_x16),
.CE(\cache[10]_5 ),
.D(\cache_reg[6][4]_srl2___U0_cache_reg_r_0_n_0 ),
.Q(\cache_reg[7][4]_U0_cache_reg_r_1_n_0 ),
.R(1'b0));
FDRE \cache_reg[7][5]_U0_cache_reg_r_1
(.C(clk_x16),
.CE(\cache[10]_5 ),
.D(\cache_reg[6][5]_srl2___U0_cache_reg_r_0_n_0 ),
.Q(\cache_reg[7][5]_U0_cache_reg_r_1_n_0 ),
.R(1'b0));
FDRE \cache_reg[7][6]_U0_cache_reg_r_1
(.C(clk_x16),
.CE(\cache[10]_5 ),
.D(\cache_reg[6][6]_srl2___U0_cache_reg_r_0_n_0 ),
.Q(\cache_reg[7][6]_U0_cache_reg_r_1_n_0 ),
.R(1'b0));
FDRE \cache_reg[7][7]_U0_cache_reg_r_1
(.C(clk_x16),
.CE(\cache[10]_5 ),
.D(\cache_reg[6][7]_srl2___U0_cache_reg_r_0_n_0 ),
.Q(\cache_reg[7][7]_U0_cache_reg_r_1_n_0 ),
.R(1'b0));
FDRE \cache_reg[7][8]_U0_cache_reg_r_1
(.C(clk_x16),
.CE(\cache[10]_5 ),
.D(\cache_reg[6][8]_srl2___U0_cache_reg_r_0_n_0 ),
.Q(\cache_reg[7][8]_U0_cache_reg_r_1_n_0 ),
.R(1'b0));
FDRE \cache_reg[7][9]_U0_cache_reg_r_1
(.C(clk_x16),
.CE(\cache[10]_5 ),
.D(\cache_reg[6][9]_srl2___U0_cache_reg_r_0_n_0 ),
.Q(\cache_reg[7][9]_U0_cache_reg_r_1_n_0 ),
.R(1'b0));
FDRE \cache_reg[8][0]
(.C(clk_x16),
.CE(\cache[10]_5 ),
.D(cache_reg_gate__30_n_0),
.Q(\cache_reg[8]_1 [0]),
.R(\cache[9][15]_i_1_n_0 ));
FDRE \cache_reg[8][10]
(.C(clk_x16),
.CE(\cache[10]_5 ),
.D(cache_reg_gate__20_n_0),
.Q(\cache_reg[8]_1 [10]),
.R(\cache[9][15]_i_1_n_0 ));
FDRE \cache_reg[8][11]
(.C(clk_x16),
.CE(\cache[10]_5 ),
.D(cache_reg_gate__19_n_0),
.Q(\cache_reg[8]_1 [11]),
.R(\cache[9][15]_i_1_n_0 ));
FDRE \cache_reg[8][12]
(.C(clk_x16),
.CE(\cache[10]_5 ),
.D(cache_reg_gate__18_n_0),
.Q(\cache_reg[8]_1 [12]),
.R(\cache[9][15]_i_1_n_0 ));
FDRE \cache_reg[8][13]
(.C(clk_x16),
.CE(\cache[10]_5 ),
.D(cache_reg_gate__17_n_0),
.Q(\cache_reg[8]_1 [13]),
.R(\cache[9][15]_i_1_n_0 ));
FDRE \cache_reg[8][14]
(.C(clk_x16),
.CE(\cache[10]_5 ),
.D(cache_reg_gate__16_n_0),
.Q(\cache_reg[8]_1 [14]),
.R(\cache[9][15]_i_1_n_0 ));
FDRE \cache_reg[8][15]
(.C(clk_x16),
.CE(\cache[10]_5 ),
.D(cache_reg_gate__15_n_0),
.Q(\cache_reg[8]_1 [15]),
.R(\cache[9][15]_i_1_n_0 ));
FDRE \cache_reg[8][1]
(.C(clk_x16),
.CE(\cache[10]_5 ),
.D(cache_reg_gate__29_n_0),
.Q(\cache_reg[8]_1 [1]),
.R(\cache[9][15]_i_1_n_0 ));
FDRE \cache_reg[8][2]
(.C(clk_x16),
.CE(\cache[10]_5 ),
.D(cache_reg_gate__28_n_0),
.Q(\cache_reg[8]_1 [2]),
.R(\cache[9][15]_i_1_n_0 ));
FDRE \cache_reg[8][3]
(.C(clk_x16),
.CE(\cache[10]_5 ),
.D(cache_reg_gate__27_n_0),
.Q(\cache_reg[8]_1 [3]),
.R(\cache[9][15]_i_1_n_0 ));
FDRE \cache_reg[8][4]
(.C(clk_x16),
.CE(\cache[10]_5 ),
.D(cache_reg_gate__26_n_0),
.Q(\cache_reg[8]_1 [4]),
.R(\cache[9][15]_i_1_n_0 ));
FDRE \cache_reg[8][5]
(.C(clk_x16),
.CE(\cache[10]_5 ),
.D(cache_reg_gate__25_n_0),
.Q(\cache_reg[8]_1 [5]),
.R(\cache[9][15]_i_1_n_0 ));
FDRE \cache_reg[8][6]
(.C(clk_x16),
.CE(\cache[10]_5 ),
.D(cache_reg_gate__24_n_0),
.Q(\cache_reg[8]_1 [6]),
.R(\cache[9][15]_i_1_n_0 ));
FDRE \cache_reg[8][7]
(.C(clk_x16),
.CE(\cache[10]_5 ),
.D(cache_reg_gate__23_n_0),
.Q(\cache_reg[8]_1 [7]),
.R(\cache[9][15]_i_1_n_0 ));
FDRE \cache_reg[8][8]
(.C(clk_x16),
.CE(\cache[10]_5 ),
.D(cache_reg_gate__22_n_0),
.Q(\cache_reg[8]_1 [8]),
.R(\cache[9][15]_i_1_n_0 ));
FDRE \cache_reg[8][9]
(.C(clk_x16),
.CE(\cache[10]_5 ),
.D(cache_reg_gate__21_n_0),
.Q(\cache_reg[8]_1 [9]),
.R(\cache[9][15]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\cache_reg[9][0]
(.C(clk_x16),
.CE(\cache[10]_5 ),
.D(\cache_reg[8]_1 [0]),
.Q(\cache_reg[9]_2 [0]),
.R(\cache[9][15]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\cache_reg[9][10]
(.C(clk_x16),
.CE(\cache[10]_5 ),
.D(\cache_reg[8]_1 [10]),
.Q(\cache_reg[9]_2 [10]),
.R(\cache[9][15]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\cache_reg[9][11]
(.C(clk_x16),
.CE(\cache[10]_5 ),
.D(\cache_reg[8]_1 [11]),
.Q(\cache_reg[9]_2 [11]),
.R(\cache[9][15]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\cache_reg[9][12]
(.C(clk_x16),
.CE(\cache[10]_5 ),
.D(\cache_reg[8]_1 [12]),
.Q(\cache_reg[9]_2 [12]),
.R(\cache[9][15]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\cache_reg[9][13]
(.C(clk_x16),
.CE(\cache[10]_5 ),
.D(\cache_reg[8]_1 [13]),
.Q(\cache_reg[9]_2 [13]),
.R(\cache[9][15]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\cache_reg[9][14]
(.C(clk_x16),
.CE(\cache[10]_5 ),
.D(\cache_reg[8]_1 [14]),
.Q(\cache_reg[9]_2 [14]),
.R(\cache[9][15]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\cache_reg[9][15]
(.C(clk_x16),
.CE(\cache[10]_5 ),
.D(\cache_reg[8]_1 [15]),
.Q(\cache_reg[9]_2 [15]),
.R(\cache[9][15]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\cache_reg[9][1]
(.C(clk_x16),
.CE(\cache[10]_5 ),
.D(\cache_reg[8]_1 [1]),
.Q(\cache_reg[9]_2 [1]),
.R(\cache[9][15]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\cache_reg[9][2]
(.C(clk_x16),
.CE(\cache[10]_5 ),
.D(\cache_reg[8]_1 [2]),
.Q(\cache_reg[9]_2 [2]),
.R(\cache[9][15]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\cache_reg[9][3]
(.C(clk_x16),
.CE(\cache[10]_5 ),
.D(\cache_reg[8]_1 [3]),
.Q(\cache_reg[9]_2 [3]),
.R(\cache[9][15]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\cache_reg[9][4]
(.C(clk_x16),
.CE(\cache[10]_5 ),
.D(\cache_reg[8]_1 [4]),
.Q(\cache_reg[9]_2 [4]),
.R(\cache[9][15]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\cache_reg[9][5]
(.C(clk_x16),
.CE(\cache[10]_5 ),
.D(\cache_reg[8]_1 [5]),
.Q(\cache_reg[9]_2 [5]),
.R(\cache[9][15]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\cache_reg[9][6]
(.C(clk_x16),
.CE(\cache[10]_5 ),
.D(\cache_reg[8]_1 [6]),
.Q(\cache_reg[9]_2 [6]),
.R(\cache[9][15]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\cache_reg[9][7]
(.C(clk_x16),
.CE(\cache[10]_5 ),
.D(\cache_reg[8]_1 [7]),
.Q(\cache_reg[9]_2 [7]),
.R(\cache[9][15]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\cache_reg[9][8]
(.C(clk_x16),
.CE(\cache[10]_5 ),
.D(\cache_reg[8]_1 [8]),
.Q(\cache_reg[9]_2 [8]),
.R(\cache[9][15]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\cache_reg[9][9]
(.C(clk_x16),
.CE(\cache[10]_5 ),
.D(\cache_reg[8]_1 [9]),
.Q(\cache_reg[9]_2 [9]),
.R(\cache[9][15]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair70" *)
LUT2 #(
.INIT(4'h8))
cache_reg_gate
(.I0(\cache_reg[3][15]_U0_cache_reg_r_1_n_0 ),
.I1(cache_reg_r_1_n_0),
.O(cache_reg_gate_n_0));
(* SOFT_HLUTNM = "soft_lutpair71" *)
LUT2 #(
.INIT(4'h8))
cache_reg_gate__0
(.I0(\cache_reg[3][14]_U0_cache_reg_r_1_n_0 ),
.I1(cache_reg_r_1_n_0),
.O(cache_reg_gate__0_n_0));
(* SOFT_HLUTNM = "soft_lutpair72" *)
LUT2 #(
.INIT(4'h8))
cache_reg_gate__1
(.I0(\cache_reg[3][13]_U0_cache_reg_r_1_n_0 ),
.I1(cache_reg_r_1_n_0),
.O(cache_reg_gate__1_n_0));
(* SOFT_HLUTNM = "soft_lutpair75" *)
LUT2 #(
.INIT(4'h8))
cache_reg_gate__10
(.I0(\cache_reg[3][4]_U0_cache_reg_r_1_n_0 ),
.I1(cache_reg_r_1_n_0),
.O(cache_reg_gate__10_n_0));
(* SOFT_HLUTNM = "soft_lutpair76" *)
LUT2 #(
.INIT(4'h8))
cache_reg_gate__11
(.I0(\cache_reg[3][3]_U0_cache_reg_r_1_n_0 ),
.I1(cache_reg_r_1_n_0),
.O(cache_reg_gate__11_n_0));
(* SOFT_HLUTNM = "soft_lutpair76" *)
LUT2 #(
.INIT(4'h8))
cache_reg_gate__12
(.I0(\cache_reg[3][2]_U0_cache_reg_r_1_n_0 ),
.I1(cache_reg_r_1_n_0),
.O(cache_reg_gate__12_n_0));
(* SOFT_HLUTNM = "soft_lutpair77" *)
LUT2 #(
.INIT(4'h8))
cache_reg_gate__13
(.I0(\cache_reg[3][1]_U0_cache_reg_r_1_n_0 ),
.I1(cache_reg_r_1_n_0),
.O(cache_reg_gate__13_n_0));
(* SOFT_HLUTNM = "soft_lutpair77" *)
LUT2 #(
.INIT(4'h8))
cache_reg_gate__14
(.I0(\cache_reg[3][0]_U0_cache_reg_r_1_n_0 ),
.I1(cache_reg_r_1_n_0),
.O(cache_reg_gate__14_n_0));
(* SOFT_HLUTNM = "soft_lutpair78" *)
LUT2 #(
.INIT(4'h8))
cache_reg_gate__15
(.I0(\cache_reg[7][15]_U0_cache_reg_r_1_n_0 ),
.I1(cache_reg_r_1_n_0),
.O(cache_reg_gate__15_n_0));
(* SOFT_HLUTNM = "soft_lutpair78" *)
LUT2 #(
.INIT(4'h8))
cache_reg_gate__16
(.I0(\cache_reg[7][14]_U0_cache_reg_r_1_n_0 ),
.I1(cache_reg_r_1_n_0),
.O(cache_reg_gate__16_n_0));
(* SOFT_HLUTNM = "soft_lutpair79" *)
LUT2 #(
.INIT(4'h8))
cache_reg_gate__17
(.I0(\cache_reg[7][13]_U0_cache_reg_r_1_n_0 ),
.I1(cache_reg_r_1_n_0),
.O(cache_reg_gate__17_n_0));
(* SOFT_HLUTNM = "soft_lutpair79" *)
LUT2 #(
.INIT(4'h8))
cache_reg_gate__18
(.I0(\cache_reg[7][12]_U0_cache_reg_r_1_n_0 ),
.I1(cache_reg_r_1_n_0),
.O(cache_reg_gate__18_n_0));
(* SOFT_HLUTNM = "soft_lutpair80" *)
LUT2 #(
.INIT(4'h8))
cache_reg_gate__19
(.I0(\cache_reg[7][11]_U0_cache_reg_r_1_n_0 ),
.I1(cache_reg_r_1_n_0),
.O(cache_reg_gate__19_n_0));
(* SOFT_HLUTNM = "soft_lutpair73" *)
LUT2 #(
.INIT(4'h8))
cache_reg_gate__2
(.I0(\cache_reg[3][12]_U0_cache_reg_r_1_n_0 ),
.I1(cache_reg_r_1_n_0),
.O(cache_reg_gate__2_n_0));
(* SOFT_HLUTNM = "soft_lutpair80" *)
LUT2 #(
.INIT(4'h8))
cache_reg_gate__20
(.I0(\cache_reg[7][10]_U0_cache_reg_r_1_n_0 ),
.I1(cache_reg_r_1_n_0),
.O(cache_reg_gate__20_n_0));
(* SOFT_HLUTNM = "soft_lutpair81" *)
LUT2 #(
.INIT(4'h8))
cache_reg_gate__21
(.I0(\cache_reg[7][9]_U0_cache_reg_r_1_n_0 ),
.I1(cache_reg_r_1_n_0),
.O(cache_reg_gate__21_n_0));
(* SOFT_HLUTNM = "soft_lutpair81" *)
LUT2 #(
.INIT(4'h8))
cache_reg_gate__22
(.I0(\cache_reg[7][8]_U0_cache_reg_r_1_n_0 ),
.I1(cache_reg_r_1_n_0),
.O(cache_reg_gate__22_n_0));
(* SOFT_HLUTNM = "soft_lutpair82" *)
LUT2 #(
.INIT(4'h8))
cache_reg_gate__23
(.I0(\cache_reg[7][7]_U0_cache_reg_r_1_n_0 ),
.I1(cache_reg_r_1_n_0),
.O(cache_reg_gate__23_n_0));
(* SOFT_HLUTNM = "soft_lutpair82" *)
LUT2 #(
.INIT(4'h8))
cache_reg_gate__24
(.I0(\cache_reg[7][6]_U0_cache_reg_r_1_n_0 ),
.I1(cache_reg_r_1_n_0),
.O(cache_reg_gate__24_n_0));
(* SOFT_HLUTNM = "soft_lutpair83" *)
LUT2 #(
.INIT(4'h8))
cache_reg_gate__25
(.I0(\cache_reg[7][5]_U0_cache_reg_r_1_n_0 ),
.I1(cache_reg_r_1_n_0),
.O(cache_reg_gate__25_n_0));
(* SOFT_HLUTNM = "soft_lutpair83" *)
LUT2 #(
.INIT(4'h8))
cache_reg_gate__26
(.I0(\cache_reg[7][4]_U0_cache_reg_r_1_n_0 ),
.I1(cache_reg_r_1_n_0),
.O(cache_reg_gate__26_n_0));
(* SOFT_HLUTNM = "soft_lutpair84" *)
LUT2 #(
.INIT(4'h8))
cache_reg_gate__27
(.I0(\cache_reg[7][3]_U0_cache_reg_r_1_n_0 ),
.I1(cache_reg_r_1_n_0),
.O(cache_reg_gate__27_n_0));
(* SOFT_HLUTNM = "soft_lutpair84" *)
LUT2 #(
.INIT(4'h8))
cache_reg_gate__28
(.I0(\cache_reg[7][2]_U0_cache_reg_r_1_n_0 ),
.I1(cache_reg_r_1_n_0),
.O(cache_reg_gate__28_n_0));
(* SOFT_HLUTNM = "soft_lutpair85" *)
LUT2 #(
.INIT(4'h8))
cache_reg_gate__29
(.I0(\cache_reg[7][1]_U0_cache_reg_r_1_n_0 ),
.I1(cache_reg_r_1_n_0),
.O(cache_reg_gate__29_n_0));
(* SOFT_HLUTNM = "soft_lutpair74" *)
LUT2 #(
.INIT(4'h8))
cache_reg_gate__3
(.I0(\cache_reg[3][11]_U0_cache_reg_r_1_n_0 ),
.I1(cache_reg_r_1_n_0),
.O(cache_reg_gate__3_n_0));
(* SOFT_HLUTNM = "soft_lutpair85" *)
LUT2 #(
.INIT(4'h8))
cache_reg_gate__30
(.I0(\cache_reg[7][0]_U0_cache_reg_r_1_n_0 ),
.I1(cache_reg_r_1_n_0),
.O(cache_reg_gate__30_n_0));
(* SOFT_HLUTNM = "soft_lutpair73" *)
LUT2 #(
.INIT(4'h8))
cache_reg_gate__4
(.I0(\cache_reg[3][10]_U0_cache_reg_r_1_n_0 ),
.I1(cache_reg_r_1_n_0),
.O(cache_reg_gate__4_n_0));
(* SOFT_HLUTNM = "soft_lutpair74" *)
LUT2 #(
.INIT(4'h8))
cache_reg_gate__5
(.I0(\cache_reg[3][9]_U0_cache_reg_r_1_n_0 ),
.I1(cache_reg_r_1_n_0),
.O(cache_reg_gate__5_n_0));
(* SOFT_HLUTNM = "soft_lutpair70" *)
LUT2 #(
.INIT(4'h8))
cache_reg_gate__6
(.I0(\cache_reg[3][8]_U0_cache_reg_r_1_n_0 ),
.I1(cache_reg_r_1_n_0),
.O(cache_reg_gate__6_n_0));
(* SOFT_HLUTNM = "soft_lutpair71" *)
LUT2 #(
.INIT(4'h8))
cache_reg_gate__7
(.I0(\cache_reg[3][7]_U0_cache_reg_r_1_n_0 ),
.I1(cache_reg_r_1_n_0),
.O(cache_reg_gate__7_n_0));
(* SOFT_HLUTNM = "soft_lutpair72" *)
LUT2 #(
.INIT(4'h8))
cache_reg_gate__8
(.I0(\cache_reg[3][6]_U0_cache_reg_r_1_n_0 ),
.I1(cache_reg_r_1_n_0),
.O(cache_reg_gate__8_n_0));
(* SOFT_HLUTNM = "soft_lutpair75" *)
LUT2 #(
.INIT(4'h8))
cache_reg_gate__9
(.I0(\cache_reg[3][5]_U0_cache_reg_r_1_n_0 ),
.I1(cache_reg_r_1_n_0),
.O(cache_reg_gate__9_n_0));
FDRE cache_reg_r
(.C(clk_x16),
.CE(\cache[10]_5 ),
.D(1'b1),
.Q(cache_reg_r_n_0),
.R(\cache[9][15]_i_1_n_0 ));
FDRE cache_reg_r_0
(.C(clk_x16),
.CE(\cache[10]_5 ),
.D(cache_reg_r_n_0),
.Q(cache_reg_r_0_n_0),
.R(\cache[9][15]_i_1_n_0 ));
FDRE cache_reg_r_1
(.C(clk_x16),
.CE(\cache[10]_5 ),
.D(cache_reg_r_0_n_0),
.Q(cache_reg_r_1_n_0),
.R(\cache[9][15]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFFEFFFFF00200000))
\compute_addr_0[0]_i_1
(.I0(\x_reg_n_0_[0] ),
.I1(cycle[3]),
.I2(\cycle_reg[2]_rep_n_0 ),
.I3(cycle[0]),
.I4(\cycle_reg[1]_rep__0_n_0 ),
.I5(data1[0]),
.O(\compute_addr_0[0]_i_1_n_0 ));
LUT6 #(
.INIT(64'hBBBBBBBB88B8B888))
\compute_addr_0[10]_i_1
(.I0(data5[10]),
.I1(cycle[0]),
.I2(\compute_addr_2[10]_i_2_n_0 ),
.I3(cycle[2]),
.I4(\cycle_reg[1]_rep_n_0 ),
.I5(\compute_addr_0[10]_i_2_n_0 ),
.O(\compute_addr_0[10]_i_1_n_0 ));
LUT6 #(
.INIT(64'hCFC000000000FA0A))
\compute_addr_0[10]_i_2
(.I0(\y3_reg_n_0_[0] ),
.I1(data5[10]),
.I2(cycle[3]),
.I3(\y1_reg_n_0_[0] ),
.I4(cycle[2]),
.I5(\cycle_reg[1]_rep_n_0 ),
.O(\compute_addr_0[10]_i_2_n_0 ));
LUT6 #(
.INIT(64'hDDDDDDDDCDC88888))
\compute_addr_0[11]_i_1
(.I0(cycle[0]),
.I1(data5[11]),
.I2(cycle[3]),
.I3(\y1_reg_n_0_[1] ),
.I4(\compute_addr_0[11]_i_2_n_0 ),
.I5(\compute_addr_0[11]_i_3_n_0 ),
.O(\compute_addr_0[11]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT2 #(
.INIT(4'h8))
\compute_addr_0[11]_i_2
(.I0(cycle[2]),
.I1(\cycle_reg[1]_rep_n_0 ),
.O(\compute_addr_0[11]_i_2_n_0 ));
LUT6 #(
.INIT(64'h0000AAAAAAAACFC0))
\compute_addr_0[11]_i_3
(.I0(\compute_addr_2[11]_i_2_n_0 ),
.I1(\y1_reg_n_0_[1] ),
.I2(cycle[3]),
.I3(\y3_reg_n_0_[1] ),
.I4(cycle[2]),
.I5(\cycle_reg[1]_rep_n_0 ),
.O(\compute_addr_0[11]_i_3_n_0 ));
LUT6 #(
.INIT(64'hBBBBBBBB88B8B888))
\compute_addr_0[12]_i_1
(.I0(data5[12]),
.I1(cycle[0]),
.I2(\compute_addr_2[12]_i_2_n_0 ),
.I3(cycle[2]),
.I4(\cycle_reg[1]_rep_n_0 ),
.I5(\compute_addr_0[12]_i_2_n_0 ),
.O(\compute_addr_0[12]_i_1_n_0 ));
LUT6 #(
.INIT(64'hCFC000000000FA0A))
\compute_addr_0[12]_i_2
(.I0(\y3_reg_n_0_[2] ),
.I1(data5[12]),
.I2(cycle[3]),
.I3(\y1_reg_n_0_[2] ),
.I4(cycle[2]),
.I5(\cycle_reg[1]_rep_n_0 ),
.O(\compute_addr_0[12]_i_2_n_0 ));
LUT3 #(
.INIT(8'h08))
\compute_addr_0[13]_i_1
(.I0(rst),
.I1(active),
.I2(cycle[0]),
.O(compute_addr_0));
LUT6 #(
.INIT(64'hBBBBBBBB88B8B888))
\compute_addr_0[13]_i_2
(.I0(data5[13]),
.I1(cycle[0]),
.I2(\compute_addr_2[13]_i_4_n_0 ),
.I3(cycle[2]),
.I4(\cycle_reg[1]_rep_n_0 ),
.I5(\compute_addr_0[13]_i_3_n_0 ),
.O(\compute_addr_0[13]_i_2_n_0 ));
LUT6 #(
.INIT(64'hCFC000000000FA0A))
\compute_addr_0[13]_i_3
(.I0(\y3_reg_n_0_[3] ),
.I1(data5[13]),
.I2(cycle[3]),
.I3(\y1_reg_n_0_[3] ),
.I4(cycle[2]),
.I5(\cycle_reg[1]_rep_n_0 ),
.O(\compute_addr_0[13]_i_3_n_0 ));
LUT6 #(
.INIT(64'hFFEFFFFF00200000))
\compute_addr_0[1]_i_1
(.I0(\x_reg_n_0_[1] ),
.I1(cycle[3]),
.I2(\cycle_reg[2]_rep_n_0 ),
.I3(cycle[0]),
.I4(\cycle_reg[1]_rep__0_n_0 ),
.I5(data1[1]),
.O(\compute_addr_0[1]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFFEFFFFF00200000))
\compute_addr_0[2]_i_1
(.I0(\x_reg_n_0_[2] ),
.I1(cycle[3]),
.I2(\cycle_reg[2]_rep_n_0 ),
.I3(cycle[0]),
.I4(\cycle_reg[1]_rep__0_n_0 ),
.I5(data1[2]),
.O(\compute_addr_0[2]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFFEFFFFF00200000))
\compute_addr_0[3]_i_1
(.I0(\x_reg_n_0_[3] ),
.I1(cycle[3]),
.I2(\cycle_reg[2]_rep_n_0 ),
.I3(cycle[0]),
.I4(\cycle_reg[1]_rep__0_n_0 ),
.I5(data1[3]),
.O(\compute_addr_0[3]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFFEFFFFF00200000))
\compute_addr_0[4]_i_1
(.I0(\x_reg_n_0_[4] ),
.I1(cycle[3]),
.I2(\cycle_reg[2]_rep_n_0 ),
.I3(cycle[0]),
.I4(\cycle_reg[1]_rep__0_n_0 ),
.I5(data1[4]),
.O(\compute_addr_0[4]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFFEFFFFF00200000))
\compute_addr_0[5]_i_1
(.I0(\x_reg_n_0_[5] ),
.I1(cycle[3]),
.I2(\cycle_reg[2]_rep_n_0 ),
.I3(cycle[0]),
.I4(\cycle_reg[1]_rep__0_n_0 ),
.I5(data1[5]),
.O(\compute_addr_0[5]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFFEFFFFF00200000))
\compute_addr_0[6]_i_1
(.I0(\x_reg_n_0_[6] ),
.I1(cycle[3]),
.I2(\cycle_reg[2]_rep_n_0 ),
.I3(cycle[0]),
.I4(\cycle_reg[1]_rep__0_n_0 ),
.I5(data1[6]),
.O(\compute_addr_0[6]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFFEFFFFF00200000))
\compute_addr_0[7]_i_1
(.I0(\x_reg_n_0_[7] ),
.I1(cycle[3]),
.I2(\cycle_reg[2]_rep_n_0 ),
.I3(cycle[0]),
.I4(\cycle_reg[1]_rep__0_n_0 ),
.I5(data1[7]),
.O(\compute_addr_0[7]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFFEFFFFF00200000))
\compute_addr_0[8]_i_1
(.I0(\x_reg_n_0_[8] ),
.I1(cycle[3]),
.I2(\cycle_reg[2]_rep_n_0 ),
.I3(cycle[0]),
.I4(\cycle_reg[1]_rep__0_n_0 ),
.I5(data1[8]),
.O(\compute_addr_0[8]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFFEFFFFF00200000))
\compute_addr_0[9]_i_1
(.I0(\x_reg_n_0_[9] ),
.I1(cycle[3]),
.I2(\cycle_reg[2]_rep_n_0 ),
.I3(cycle[0]),
.I4(\cycle_reg[1]_rep_n_0 ),
.I5(data1[9]),
.O(\compute_addr_0[9]_i_1_n_0 ));
FDRE \compute_addr_0_reg[0]
(.C(clk_x16),
.CE(compute_addr_0),
.D(\compute_addr_0[0]_i_1_n_0 ),
.Q(\compute_addr_0_reg_n_0_[0] ),
.R(1'b0));
FDRE \compute_addr_0_reg[10]
(.C(clk_x16),
.CE(compute_addr_0),
.D(\compute_addr_0[10]_i_1_n_0 ),
.Q(\compute_addr_0_reg_n_0_[10] ),
.R(1'b0));
FDRE \compute_addr_0_reg[11]
(.C(clk_x16),
.CE(compute_addr_0),
.D(\compute_addr_0[11]_i_1_n_0 ),
.Q(\compute_addr_0_reg_n_0_[11] ),
.R(1'b0));
FDRE \compute_addr_0_reg[12]
(.C(clk_x16),
.CE(compute_addr_0),
.D(\compute_addr_0[12]_i_1_n_0 ),
.Q(\compute_addr_0_reg_n_0_[12] ),
.R(1'b0));
FDRE \compute_addr_0_reg[13]
(.C(clk_x16),
.CE(compute_addr_0),
.D(\compute_addr_0[13]_i_2_n_0 ),
.Q(\compute_addr_0_reg_n_0_[13] ),
.R(1'b0));
FDRE \compute_addr_0_reg[1]
(.C(clk_x16),
.CE(compute_addr_0),
.D(\compute_addr_0[1]_i_1_n_0 ),
.Q(\compute_addr_0_reg_n_0_[1] ),
.R(1'b0));
FDRE \compute_addr_0_reg[2]
(.C(clk_x16),
.CE(compute_addr_0),
.D(\compute_addr_0[2]_i_1_n_0 ),
.Q(\compute_addr_0_reg_n_0_[2] ),
.R(1'b0));
FDRE \compute_addr_0_reg[3]
(.C(clk_x16),
.CE(compute_addr_0),
.D(\compute_addr_0[3]_i_1_n_0 ),
.Q(\compute_addr_0_reg_n_0_[3] ),
.R(1'b0));
FDRE \compute_addr_0_reg[4]
(.C(clk_x16),
.CE(compute_addr_0),
.D(\compute_addr_0[4]_i_1_n_0 ),
.Q(\compute_addr_0_reg_n_0_[4] ),
.R(1'b0));
FDRE \compute_addr_0_reg[5]
(.C(clk_x16),
.CE(compute_addr_0),
.D(\compute_addr_0[5]_i_1_n_0 ),
.Q(\compute_addr_0_reg_n_0_[5] ),
.R(1'b0));
FDRE \compute_addr_0_reg[6]
(.C(clk_x16),
.CE(compute_addr_0),
.D(\compute_addr_0[6]_i_1_n_0 ),
.Q(\compute_addr_0_reg_n_0_[6] ),
.R(1'b0));
FDRE \compute_addr_0_reg[7]
(.C(clk_x16),
.CE(compute_addr_0),
.D(\compute_addr_0[7]_i_1_n_0 ),
.Q(\compute_addr_0_reg_n_0_[7] ),
.R(1'b0));
FDRE \compute_addr_0_reg[8]
(.C(clk_x16),
.CE(compute_addr_0),
.D(\compute_addr_0[8]_i_1_n_0 ),
.Q(\compute_addr_0_reg_n_0_[8] ),
.R(1'b0));
FDRE \compute_addr_0_reg[9]
(.C(clk_x16),
.CE(compute_addr_0),
.D(\compute_addr_0[9]_i_1_n_0 ),
.Q(\compute_addr_0_reg_n_0_[9] ),
.R(1'b0));
LUT6 #(
.INIT(64'hFFFFEBFF00002800))
\compute_addr_1[0]_i_1
(.I0(data1[0]),
.I1(\cycle_reg[1]_rep_n_0 ),
.I2(cycle[2]),
.I3(cycle[3]),
.I4(cycle[0]),
.I5(data2[0]),
.O(\compute_addr_1[0]_i_1_n_0 ));
LUT6 #(
.INIT(64'hBBBBBBBB88B8B888))
\compute_addr_1[10]_i_1
(.I0(data5[10]),
.I1(cycle[0]),
.I2(\compute_addr_3[10]_i_2_n_0 ),
.I3(cycle[2]),
.I4(\cycle_reg[1]_rep_n_0 ),
.I5(\compute_addr_1[10]_i_2_n_0 ),
.O(\compute_addr_1[10]_i_1_n_0 ));
LUT6 #(
.INIT(64'hACAC00000000CFC0))
\compute_addr_1[10]_i_2
(.I0(data5[10]),
.I1(data2[10]),
.I2(cycle[3]),
.I3(\y3_reg_n_0_[0] ),
.I4(cycle[2]),
.I5(\cycle_reg[1]_rep_n_0 ),
.O(\compute_addr_1[10]_i_2_n_0 ));
LUT6 #(
.INIT(64'hBBBBBBBB88B8B888))
\compute_addr_1[11]_i_1
(.I0(data5[11]),
.I1(cycle[0]),
.I2(\compute_addr_3[11]_i_2_n_0 ),
.I3(cycle[2]),
.I4(\cycle_reg[1]_rep_n_0 ),
.I5(\compute_addr_1[11]_i_2_n_0 ),
.O(\compute_addr_1[11]_i_1_n_0 ));
LUT6 #(
.INIT(64'hACAC00000000CFC0))
\compute_addr_1[11]_i_2
(.I0(data5[11]),
.I1(data2[11]),
.I2(cycle[3]),
.I3(\y3_reg_n_0_[1] ),
.I4(cycle[2]),
.I5(\cycle_reg[1]_rep_n_0 ),
.O(\compute_addr_1[11]_i_2_n_0 ));
LUT6 #(
.INIT(64'hBBBBBBBB88B8B888))
\compute_addr_1[12]_i_1
(.I0(data5[12]),
.I1(cycle[0]),
.I2(\compute_addr_3[12]_i_2_n_0 ),
.I3(cycle[2]),
.I4(\cycle_reg[1]_rep_n_0 ),
.I5(\compute_addr_1[12]_i_2_n_0 ),
.O(\compute_addr_1[12]_i_1_n_0 ));
LUT6 #(
.INIT(64'hACAC00000000CFC0))
\compute_addr_1[12]_i_2
(.I0(data5[12]),
.I1(data2[12]),
.I2(cycle[3]),
.I3(\y3_reg_n_0_[2] ),
.I4(cycle[2]),
.I5(\cycle_reg[1]_rep_n_0 ),
.O(\compute_addr_1[12]_i_2_n_0 ));
LUT6 #(
.INIT(64'hBBBBBBBB88B8B888))
\compute_addr_1[13]_i_1
(.I0(data5[13]),
.I1(cycle[0]),
.I2(\compute_addr_3[13]_i_2_n_0 ),
.I3(cycle[2]),
.I4(\cycle_reg[1]_rep_n_0 ),
.I5(\compute_addr_1[13]_i_2_n_0 ),
.O(\compute_addr_1[13]_i_1_n_0 ));
LUT6 #(
.INIT(64'hCFC000000000FA0A))
\compute_addr_1[13]_i_2
(.I0(\y3_reg_n_0_[3] ),
.I1(data5[13]),
.I2(cycle[3]),
.I3(data2[13]),
.I4(cycle[2]),
.I5(\cycle_reg[1]_rep_n_0 ),
.O(\compute_addr_1[13]_i_2_n_0 ));
LUT6 #(
.INIT(64'hFFFFEBFF00002800))
\compute_addr_1[1]_i_1
(.I0(data1[1]),
.I1(\cycle_reg[1]_rep_n_0 ),
.I2(cycle[2]),
.I3(cycle[3]),
.I4(cycle[0]),
.I5(data2[1]),
.O(\compute_addr_1[1]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFFFFEBFF00002800))
\compute_addr_1[2]_i_1
(.I0(data1[2]),
.I1(\cycle_reg[1]_rep_n_0 ),
.I2(cycle[2]),
.I3(cycle[3]),
.I4(cycle[0]),
.I5(data2[2]),
.O(\compute_addr_1[2]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFFFFEBFF00002800))
\compute_addr_1[3]_i_1
(.I0(data1[3]),
.I1(\cycle_reg[1]_rep_n_0 ),
.I2(cycle[2]),
.I3(cycle[3]),
.I4(cycle[0]),
.I5(data2[3]),
.O(\compute_addr_1[3]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFFFFEBFF00002800))
\compute_addr_1[4]_i_1
(.I0(data1[4]),
.I1(\cycle_reg[1]_rep_n_0 ),
.I2(cycle[2]),
.I3(cycle[3]),
.I4(cycle[0]),
.I5(data2[4]),
.O(\compute_addr_1[4]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFFFFEBFF00002800))
\compute_addr_1[5]_i_1
(.I0(data1[5]),
.I1(\cycle_reg[1]_rep_n_0 ),
.I2(cycle[2]),
.I3(cycle[3]),
.I4(cycle[0]),
.I5(data2[5]),
.O(\compute_addr_1[5]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFFFFEBFF00002800))
\compute_addr_1[6]_i_1
(.I0(data1[6]),
.I1(\cycle_reg[1]_rep_n_0 ),
.I2(cycle[2]),
.I3(cycle[3]),
.I4(cycle[0]),
.I5(data2[6]),
.O(\compute_addr_1[6]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFFFFEBFF00002800))
\compute_addr_1[7]_i_1
(.I0(data1[7]),
.I1(\cycle_reg[1]_rep_n_0 ),
.I2(cycle[2]),
.I3(cycle[3]),
.I4(cycle[0]),
.I5(data2[7]),
.O(\compute_addr_1[7]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFFFFEBFF00002800))
\compute_addr_1[8]_i_1
(.I0(data1[8]),
.I1(\cycle_reg[1]_rep_n_0 ),
.I2(cycle[2]),
.I3(cycle[3]),
.I4(cycle[0]),
.I5(data2[8]),
.O(\compute_addr_1[8]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFFFFEBFF00002800))
\compute_addr_1[9]_i_1
(.I0(data1[9]),
.I1(\cycle_reg[1]_rep_n_0 ),
.I2(cycle[2]),
.I3(cycle[3]),
.I4(cycle[0]),
.I5(data2[9]),
.O(\compute_addr_1[9]_i_1_n_0 ));
FDRE \compute_addr_1_reg[0]
(.C(clk_x16),
.CE(compute_addr_0),
.D(\compute_addr_1[0]_i_1_n_0 ),
.Q(compute_addr_1[0]),
.R(1'b0));
FDRE \compute_addr_1_reg[10]
(.C(clk_x16),
.CE(compute_addr_0),
.D(\compute_addr_1[10]_i_1_n_0 ),
.Q(compute_addr_1[10]),
.R(1'b0));
FDRE \compute_addr_1_reg[11]
(.C(clk_x16),
.CE(compute_addr_0),
.D(\compute_addr_1[11]_i_1_n_0 ),
.Q(compute_addr_1[11]),
.R(1'b0));
FDRE \compute_addr_1_reg[12]
(.C(clk_x16),
.CE(compute_addr_0),
.D(\compute_addr_1[12]_i_1_n_0 ),
.Q(compute_addr_1[12]),
.R(1'b0));
FDRE \compute_addr_1_reg[13]
(.C(clk_x16),
.CE(compute_addr_0),
.D(\compute_addr_1[13]_i_1_n_0 ),
.Q(compute_addr_1[13]),
.R(1'b0));
FDRE \compute_addr_1_reg[1]
(.C(clk_x16),
.CE(compute_addr_0),
.D(\compute_addr_1[1]_i_1_n_0 ),
.Q(compute_addr_1[1]),
.R(1'b0));
FDRE \compute_addr_1_reg[2]
(.C(clk_x16),
.CE(compute_addr_0),
.D(\compute_addr_1[2]_i_1_n_0 ),
.Q(compute_addr_1[2]),
.R(1'b0));
FDRE \compute_addr_1_reg[3]
(.C(clk_x16),
.CE(compute_addr_0),
.D(\compute_addr_1[3]_i_1_n_0 ),
.Q(compute_addr_1[3]),
.R(1'b0));
FDRE \compute_addr_1_reg[4]
(.C(clk_x16),
.CE(compute_addr_0),
.D(\compute_addr_1[4]_i_1_n_0 ),
.Q(compute_addr_1[4]),
.R(1'b0));
FDRE \compute_addr_1_reg[5]
(.C(clk_x16),
.CE(compute_addr_0),
.D(\compute_addr_1[5]_i_1_n_0 ),
.Q(compute_addr_1[5]),
.R(1'b0));
FDRE \compute_addr_1_reg[6]
(.C(clk_x16),
.CE(compute_addr_0),
.D(\compute_addr_1[6]_i_1_n_0 ),
.Q(compute_addr_1[6]),
.R(1'b0));
FDRE \compute_addr_1_reg[7]
(.C(clk_x16),
.CE(compute_addr_0),
.D(\compute_addr_1[7]_i_1_n_0 ),
.Q(compute_addr_1[7]),
.R(1'b0));
FDRE \compute_addr_1_reg[8]
(.C(clk_x16),
.CE(compute_addr_0),
.D(\compute_addr_1[8]_i_1_n_0 ),
.Q(compute_addr_1[8]),
.R(1'b0));
FDRE \compute_addr_1_reg[9]
(.C(clk_x16),
.CE(compute_addr_0),
.D(\compute_addr_1[9]_i_1_n_0 ),
.Q(compute_addr_1[9]),
.R(1'b0));
LUT6 #(
.INIT(64'hBBB8B8BB88B8B888))
\compute_addr_2[10]_i_1
(.I0(\y6_reg_n_0_[0] ),
.I1(\compute_addr_2[13]_i_3_n_0 ),
.I2(\compute_addr_2[10]_i_2_n_0 ),
.I3(cycle[2]),
.I4(\cycle_reg[1]_rep_n_0 ),
.I5(\y1_reg_n_0_[0] ),
.O(\compute_addr_2[10]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair58" *)
LUT3 #(
.INIT(8'hB8))
\compute_addr_2[10]_i_2
(.I0(\y2_reg_n_0_[0] ),
.I1(cycle[3]),
.I2(data1[10]),
.O(\compute_addr_2[10]_i_2_n_0 ));
LUT6 #(
.INIT(64'hBBB8B8BB88B8B888))
\compute_addr_2[11]_i_1
(.I0(\y6_reg_n_0_[1] ),
.I1(\compute_addr_2[13]_i_3_n_0 ),
.I2(\compute_addr_2[11]_i_2_n_0 ),
.I3(cycle[2]),
.I4(\cycle_reg[1]_rep_n_0 ),
.I5(\y1_reg_n_0_[1] ),
.O(\compute_addr_2[11]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair58" *)
LUT3 #(
.INIT(8'hB8))
\compute_addr_2[11]_i_2
(.I0(\y2_reg_n_0_[1] ),
.I1(cycle[3]),
.I2(data1[11]),
.O(\compute_addr_2[11]_i_2_n_0 ));
LUT6 #(
.INIT(64'hBBB8B8BB88B8B888))
\compute_addr_2[12]_i_1
(.I0(\y6_reg_n_0_[2] ),
.I1(\compute_addr_2[13]_i_3_n_0 ),
.I2(\compute_addr_2[12]_i_2_n_0 ),
.I3(cycle[2]),
.I4(\cycle_reg[1]_rep_n_0 ),
.I5(\y1_reg_n_0_[2] ),
.O(\compute_addr_2[12]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair57" *)
LUT3 #(
.INIT(8'hB8))
\compute_addr_2[12]_i_2
(.I0(\y2_reg_n_0_[2] ),
.I1(cycle[3]),
.I2(data1[12]),
.O(\compute_addr_2[12]_i_2_n_0 ));
LUT6 #(
.INIT(64'h8080808080808000))
\compute_addr_2[13]_i_1
(.I0(\cycle_reg[0]_rep_n_0 ),
.I1(active),
.I2(rst),
.I3(\cycle_reg[1]_rep_n_0 ),
.I4(cycle[3]),
.I5(cycle[2]),
.O(compute_addr_2));
LUT6 #(
.INIT(64'hBBB8B8BB88B8B888))
\compute_addr_2[13]_i_2
(.I0(\y6_reg_n_0_[3] ),
.I1(\compute_addr_2[13]_i_3_n_0 ),
.I2(\compute_addr_2[13]_i_4_n_0 ),
.I3(cycle[2]),
.I4(\cycle_reg[1]_rep_n_0 ),
.I5(\y1_reg_n_0_[3] ),
.O(\compute_addr_2[13]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair15" *)
LUT4 #(
.INIT(16'h81FF))
\compute_addr_2[13]_i_3
(.I0(cycle[3]),
.I1(cycle[2]),
.I2(\cycle_reg[1]_rep_n_0 ),
.I3(\cycle_reg[0]_rep_n_0 ),
.O(\compute_addr_2[13]_i_3_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair57" *)
LUT3 #(
.INIT(8'hB8))
\compute_addr_2[13]_i_4
(.I0(\y2_reg_n_0_[3] ),
.I1(cycle[3]),
.I2(data1[13]),
.O(\compute_addr_2[13]_i_4_n_0 ));
FDRE \compute_addr_2_reg[0]
(.C(clk_x16),
.CE(compute_addr_2),
.D(data1[0]),
.Q(\compute_addr_2_reg_n_0_[0] ),
.R(1'b0));
FDRE \compute_addr_2_reg[10]
(.C(clk_x16),
.CE(compute_addr_2),
.D(\compute_addr_2[10]_i_1_n_0 ),
.Q(\compute_addr_2_reg_n_0_[10] ),
.R(1'b0));
FDRE \compute_addr_2_reg[11]
(.C(clk_x16),
.CE(compute_addr_2),
.D(\compute_addr_2[11]_i_1_n_0 ),
.Q(\compute_addr_2_reg_n_0_[11] ),
.R(1'b0));
FDRE \compute_addr_2_reg[12]
(.C(clk_x16),
.CE(compute_addr_2),
.D(\compute_addr_2[12]_i_1_n_0 ),
.Q(\compute_addr_2_reg_n_0_[12] ),
.R(1'b0));
FDRE \compute_addr_2_reg[13]
(.C(clk_x16),
.CE(compute_addr_2),
.D(\compute_addr_2[13]_i_2_n_0 ),
.Q(\compute_addr_2_reg_n_0_[13] ),
.R(1'b0));
FDRE \compute_addr_2_reg[1]
(.C(clk_x16),
.CE(compute_addr_2),
.D(data1[1]),
.Q(\compute_addr_2_reg_n_0_[1] ),
.R(1'b0));
FDRE \compute_addr_2_reg[2]
(.C(clk_x16),
.CE(compute_addr_2),
.D(data1[2]),
.Q(\compute_addr_2_reg_n_0_[2] ),
.R(1'b0));
FDRE \compute_addr_2_reg[3]
(.C(clk_x16),
.CE(compute_addr_2),
.D(data1[3]),
.Q(\compute_addr_2_reg_n_0_[3] ),
.R(1'b0));
FDRE \compute_addr_2_reg[4]
(.C(clk_x16),
.CE(compute_addr_2),
.D(data1[4]),
.Q(\compute_addr_2_reg_n_0_[4] ),
.R(1'b0));
FDRE \compute_addr_2_reg[5]
(.C(clk_x16),
.CE(compute_addr_2),
.D(data1[5]),
.Q(\compute_addr_2_reg_n_0_[5] ),
.R(1'b0));
FDRE \compute_addr_2_reg[6]
(.C(clk_x16),
.CE(compute_addr_2),
.D(data1[6]),
.Q(\compute_addr_2_reg_n_0_[6] ),
.R(1'b0));
FDRE \compute_addr_2_reg[7]
(.C(clk_x16),
.CE(compute_addr_2),
.D(data1[7]),
.Q(\compute_addr_2_reg_n_0_[7] ),
.R(1'b0));
FDRE \compute_addr_2_reg[8]
(.C(clk_x16),
.CE(compute_addr_2),
.D(data1[8]),
.Q(\compute_addr_2_reg_n_0_[8] ),
.R(1'b0));
FDRE \compute_addr_2_reg[9]
(.C(clk_x16),
.CE(compute_addr_2),
.D(data1[9]),
.Q(\compute_addr_2_reg_n_0_[9] ),
.R(1'b0));
LUT6 #(
.INIT(64'hFFBFBFFF00808000))
\compute_addr_3[0]_i_1
(.I0(data1[0]),
.I1(\cycle_reg[0]_rep_n_0 ),
.I2(cycle[3]),
.I3(\cycle_reg[1]_rep_n_0 ),
.I4(cycle[2]),
.I5(data2[0]),
.O(\compute_addr_3[0]_i_1_n_0 ));
LUT6 #(
.INIT(64'hBBB8B8BB88B8B888))
\compute_addr_3[10]_i_1
(.I0(\y6_reg_n_0_[0] ),
.I1(\compute_addr_2[13]_i_3_n_0 ),
.I2(\compute_addr_3[10]_i_2_n_0 ),
.I3(cycle[2]),
.I4(\cycle_reg[1]_rep_n_0 ),
.I5(data2[10]),
.O(\compute_addr_3[10]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair67" *)
LUT3 #(
.INIT(8'hB8))
\compute_addr_3[10]_i_2
(.I0(y7[0]),
.I1(cycle[3]),
.I2(y8[0]),
.O(\compute_addr_3[10]_i_2_n_0 ));
LUT6 #(
.INIT(64'hBBB8B8BB88B8B888))
\compute_addr_3[11]_i_1
(.I0(\y6_reg_n_0_[1] ),
.I1(\compute_addr_2[13]_i_3_n_0 ),
.I2(\compute_addr_3[11]_i_2_n_0 ),
.I3(cycle[2]),
.I4(\cycle_reg[1]_rep_n_0 ),
.I5(data2[11]),
.O(\compute_addr_3[11]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair67" *)
LUT3 #(
.INIT(8'hB8))
\compute_addr_3[11]_i_2
(.I0(y7[1]),
.I1(cycle[3]),
.I2(y8[1]),
.O(\compute_addr_3[11]_i_2_n_0 ));
LUT6 #(
.INIT(64'hBBB8B8BB88B8B888))
\compute_addr_3[12]_i_1
(.I0(\y6_reg_n_0_[2] ),
.I1(\compute_addr_2[13]_i_3_n_0 ),
.I2(\compute_addr_3[12]_i_2_n_0 ),
.I3(cycle[2]),
.I4(\cycle_reg[1]_rep_n_0 ),
.I5(data2[12]),
.O(\compute_addr_3[12]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair66" *)
LUT3 #(
.INIT(8'hB8))
\compute_addr_3[12]_i_2
(.I0(y7[2]),
.I1(cycle[3]),
.I2(y8[2]),
.O(\compute_addr_3[12]_i_2_n_0 ));
LUT6 #(
.INIT(64'hBBB8B8BB88B8B888))
\compute_addr_3[13]_i_1
(.I0(\y6_reg_n_0_[3] ),
.I1(\compute_addr_2[13]_i_3_n_0 ),
.I2(\compute_addr_3[13]_i_2_n_0 ),
.I3(cycle[2]),
.I4(\cycle_reg[1]_rep_n_0 ),
.I5(data2[13]),
.O(\compute_addr_3[13]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair66" *)
LUT3 #(
.INIT(8'hB8))
\compute_addr_3[13]_i_2
(.I0(y7[3]),
.I1(cycle[3]),
.I2(y8[3]),
.O(\compute_addr_3[13]_i_2_n_0 ));
LUT6 #(
.INIT(64'hFFBFBFFF00808000))
\compute_addr_3[1]_i_1
(.I0(data1[1]),
.I1(\cycle_reg[0]_rep_n_0 ),
.I2(cycle[3]),
.I3(\cycle_reg[1]_rep_n_0 ),
.I4(cycle[2]),
.I5(data2[1]),
.O(\compute_addr_3[1]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFFBFBFFF00808000))
\compute_addr_3[2]_i_1
(.I0(data1[2]),
.I1(\cycle_reg[0]_rep_n_0 ),
.I2(cycle[3]),
.I3(\cycle_reg[1]_rep_n_0 ),
.I4(cycle[2]),
.I5(data2[2]),
.O(\compute_addr_3[2]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFFBFBFFF00808000))
\compute_addr_3[3]_i_1
(.I0(data1[3]),
.I1(\cycle_reg[0]_rep_n_0 ),
.I2(cycle[3]),
.I3(\cycle_reg[1]_rep_n_0 ),
.I4(cycle[2]),
.I5(data2[3]),
.O(\compute_addr_3[3]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFFBFBFFF00808000))
\compute_addr_3[4]_i_1
(.I0(data1[4]),
.I1(\cycle_reg[0]_rep_n_0 ),
.I2(cycle[3]),
.I3(\cycle_reg[1]_rep_n_0 ),
.I4(cycle[2]),
.I5(data2[4]),
.O(\compute_addr_3[4]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFFBFBFFF00808000))
\compute_addr_3[5]_i_1
(.I0(data1[5]),
.I1(\cycle_reg[0]_rep_n_0 ),
.I2(cycle[3]),
.I3(\cycle_reg[1]_rep_n_0 ),
.I4(cycle[2]),
.I5(data2[5]),
.O(\compute_addr_3[5]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFFBFBFFF00808000))
\compute_addr_3[6]_i_1
(.I0(data1[6]),
.I1(\cycle_reg[0]_rep_n_0 ),
.I2(cycle[3]),
.I3(\cycle_reg[1]_rep_n_0 ),
.I4(cycle[2]),
.I5(data2[6]),
.O(\compute_addr_3[6]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFFBFBFFF00808000))
\compute_addr_3[7]_i_1
(.I0(data1[7]),
.I1(\cycle_reg[0]_rep_n_0 ),
.I2(cycle[3]),
.I3(\cycle_reg[1]_rep_n_0 ),
.I4(cycle[2]),
.I5(data2[7]),
.O(\compute_addr_3[7]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFFBFBFFF00808000))
\compute_addr_3[8]_i_1
(.I0(data1[8]),
.I1(\cycle_reg[0]_rep_n_0 ),
.I2(cycle[3]),
.I3(\cycle_reg[1]_rep_n_0 ),
.I4(cycle[2]),
.I5(data2[8]),
.O(\compute_addr_3[8]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFFBFBFFF00808000))
\compute_addr_3[9]_i_1
(.I0(data1[9]),
.I1(\cycle_reg[0]_rep_n_0 ),
.I2(cycle[3]),
.I3(\cycle_reg[1]_rep_n_0 ),
.I4(cycle[2]),
.I5(data2[9]),
.O(\compute_addr_3[9]_i_1_n_0 ));
FDRE \compute_addr_3_reg[0]
(.C(clk_x16),
.CE(compute_addr_2),
.D(\compute_addr_3[0]_i_1_n_0 ),
.Q(compute_addr_3[0]),
.R(1'b0));
FDRE \compute_addr_3_reg[10]
(.C(clk_x16),
.CE(compute_addr_2),
.D(\compute_addr_3[10]_i_1_n_0 ),
.Q(compute_addr_3[10]),
.R(1'b0));
FDRE \compute_addr_3_reg[11]
(.C(clk_x16),
.CE(compute_addr_2),
.D(\compute_addr_3[11]_i_1_n_0 ),
.Q(compute_addr_3[11]),
.R(1'b0));
FDRE \compute_addr_3_reg[12]
(.C(clk_x16),
.CE(compute_addr_2),
.D(\compute_addr_3[12]_i_1_n_0 ),
.Q(compute_addr_3[12]),
.R(1'b0));
FDRE \compute_addr_3_reg[13]
(.C(clk_x16),
.CE(compute_addr_2),
.D(\compute_addr_3[13]_i_1_n_0 ),
.Q(compute_addr_3[13]),
.R(1'b0));
FDRE \compute_addr_3_reg[1]
(.C(clk_x16),
.CE(compute_addr_2),
.D(\compute_addr_3[1]_i_1_n_0 ),
.Q(compute_addr_3[1]),
.R(1'b0));
FDRE \compute_addr_3_reg[2]
(.C(clk_x16),
.CE(compute_addr_2),
.D(\compute_addr_3[2]_i_1_n_0 ),
.Q(compute_addr_3[2]),
.R(1'b0));
FDRE \compute_addr_3_reg[3]
(.C(clk_x16),
.CE(compute_addr_2),
.D(\compute_addr_3[3]_i_1_n_0 ),
.Q(compute_addr_3[3]),
.R(1'b0));
FDRE \compute_addr_3_reg[4]
(.C(clk_x16),
.CE(compute_addr_2),
.D(\compute_addr_3[4]_i_1_n_0 ),
.Q(compute_addr_3[4]),
.R(1'b0));
FDRE \compute_addr_3_reg[5]
(.C(clk_x16),
.CE(compute_addr_2),
.D(\compute_addr_3[5]_i_1_n_0 ),
.Q(compute_addr_3[5]),
.R(1'b0));
FDRE \compute_addr_3_reg[6]
(.C(clk_x16),
.CE(compute_addr_2),
.D(\compute_addr_3[6]_i_1_n_0 ),
.Q(compute_addr_3[6]),
.R(1'b0));
FDRE \compute_addr_3_reg[7]
(.C(clk_x16),
.CE(compute_addr_2),
.D(\compute_addr_3[7]_i_1_n_0 ),
.Q(compute_addr_3[7]),
.R(1'b0));
FDRE \compute_addr_3_reg[8]
(.C(clk_x16),
.CE(compute_addr_2),
.D(\compute_addr_3[8]_i_1_n_0 ),
.Q(compute_addr_3[8]),
.R(1'b0));
FDRE \compute_addr_3_reg[9]
(.C(clk_x16),
.CE(compute_addr_2),
.D(\compute_addr_3[9]_i_1_n_0 ),
.Q(compute_addr_3[9]),
.R(1'b0));
LUT6 #(
.INIT(64'hFFFFFFFF00000008))
\corner[15]_i_1
(.I0(\left[15]_i_2_n_0 ),
.I1(x),
.I2(\x_reg_n_0_[0] ),
.I3(\x_reg_n_0_[9] ),
.I4(\x_reg_n_0_[8] ),
.I5(top),
.O(corner));
FDRE #(
.INIT(1'b0))
\corner_reg[0]
(.C(clk_x16),
.CE(x),
.D(\cache_reg[10]_3 [0]),
.Q(\corner_reg_n_0_[0] ),
.R(corner));
FDRE #(
.INIT(1'b0))
\corner_reg[10]
(.C(clk_x16),
.CE(x),
.D(\cache_reg[10]_3 [10]),
.Q(\corner_reg_n_0_[10] ),
.R(corner));
FDRE #(
.INIT(1'b0))
\corner_reg[11]
(.C(clk_x16),
.CE(x),
.D(\cache_reg[10]_3 [11]),
.Q(\corner_reg_n_0_[11] ),
.R(corner));
FDRE #(
.INIT(1'b0))
\corner_reg[12]
(.C(clk_x16),
.CE(x),
.D(\cache_reg[10]_3 [12]),
.Q(\corner_reg_n_0_[12] ),
.R(corner));
FDRE #(
.INIT(1'b0))
\corner_reg[13]
(.C(clk_x16),
.CE(x),
.D(\cache_reg[10]_3 [13]),
.Q(\corner_reg_n_0_[13] ),
.R(corner));
FDRE #(
.INIT(1'b0))
\corner_reg[14]
(.C(clk_x16),
.CE(x),
.D(\cache_reg[10]_3 [14]),
.Q(\corner_reg_n_0_[14] ),
.R(corner));
FDRE #(
.INIT(1'b0))
\corner_reg[15]
(.C(clk_x16),
.CE(x),
.D(\cache_reg[10]_3 [15]),
.Q(\corner_reg_n_0_[15] ),
.R(corner));
FDRE #(
.INIT(1'b0))
\corner_reg[1]
(.C(clk_x16),
.CE(x),
.D(\cache_reg[10]_3 [1]),
.Q(\corner_reg_n_0_[1] ),
.R(corner));
FDRE #(
.INIT(1'b0))
\corner_reg[2]
(.C(clk_x16),
.CE(x),
.D(\cache_reg[10]_3 [2]),
.Q(\corner_reg_n_0_[2] ),
.R(corner));
FDRE #(
.INIT(1'b0))
\corner_reg[3]
(.C(clk_x16),
.CE(x),
.D(\cache_reg[10]_3 [3]),
.Q(\corner_reg_n_0_[3] ),
.R(corner));
FDRE #(
.INIT(1'b0))
\corner_reg[4]
(.C(clk_x16),
.CE(x),
.D(\cache_reg[10]_3 [4]),
.Q(\corner_reg_n_0_[4] ),
.R(corner));
FDRE #(
.INIT(1'b0))
\corner_reg[5]
(.C(clk_x16),
.CE(x),
.D(\cache_reg[10]_3 [5]),
.Q(\corner_reg_n_0_[5] ),
.R(corner));
FDRE #(
.INIT(1'b0))
\corner_reg[6]
(.C(clk_x16),
.CE(x),
.D(\cache_reg[10]_3 [6]),
.Q(\corner_reg_n_0_[6] ),
.R(corner));
FDRE #(
.INIT(1'b0))
\corner_reg[7]
(.C(clk_x16),
.CE(x),
.D(\cache_reg[10]_3 [7]),
.Q(\corner_reg_n_0_[7] ),
.R(corner));
FDRE #(
.INIT(1'b0))
\corner_reg[8]
(.C(clk_x16),
.CE(x),
.D(\cache_reg[10]_3 [8]),
.Q(\corner_reg_n_0_[8] ),
.R(corner));
FDRE #(
.INIT(1'b0))
\corner_reg[9]
(.C(clk_x16),
.CE(x),
.D(\cache_reg[10]_3 [9]),
.Q(\corner_reg_n_0_[9] ),
.R(corner));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT1 #(
.INIT(2'h1))
\cycle[0]_i_1
(.I0(cycle[0]),
.O(\cycle[0]_i_1_n_0 ));
LUT1 #(
.INIT(2'h1))
\cycle[0]_rep_i_1
(.I0(cycle[0]),
.O(\cycle[0]_rep_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair31" *)
LUT2 #(
.INIT(4'h6))
\cycle[1]_i_1
(.I0(cycle[1]),
.I1(cycle[0]),
.O(\cycle[1]_i_1_n_0 ));
LUT2 #(
.INIT(4'h6))
\cycle[1]_rep_i_1
(.I0(cycle[1]),
.I1(cycle[0]),
.O(\cycle[1]_rep_i_1_n_0 ));
LUT2 #(
.INIT(4'h6))
\cycle[1]_rep_i_1__0
(.I0(cycle[1]),
.I1(cycle[0]),
.O(\cycle[1]_rep_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair31" *)
LUT3 #(
.INIT(8'h78))
\cycle[2]_i_1
(.I0(cycle[1]),
.I1(\cycle_reg[0]_rep_n_0 ),
.I2(cycle[2]),
.O(\cycle[2]_i_1_n_0 ));
LUT3 #(
.INIT(8'h78))
\cycle[2]_rep_i_1
(.I0(\cycle_reg[1]_rep_n_0 ),
.I1(cycle[0]),
.I2(cycle[2]),
.O(\cycle[2]_rep_i_1_n_0 ));
LUT2 #(
.INIT(4'h7))
\cycle[3]_i_1
(.I0(rst),
.I1(active),
.O(\cycle[3]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair15" *)
LUT4 #(
.INIT(16'h6AAA))
\cycle[3]_i_2
(.I0(cycle[3]),
.I1(cycle[2]),
.I2(cycle[1]),
.I3(\cycle_reg[0]_rep_n_0 ),
.O(\cycle[3]_i_2_n_0 ));
(* ORIG_CELL_NAME = "cycle_reg[0]" *)
FDRE #(
.INIT(1'b0))
\cycle_reg[0]
(.C(clk_x16),
.CE(1'b1),
.D(\cycle[0]_i_1_n_0 ),
.Q(cycle[0]),
.R(\cycle[3]_i_1_n_0 ));
(* ORIG_CELL_NAME = "cycle_reg[0]" *)
FDRE #(
.INIT(1'b0))
\cycle_reg[0]_rep
(.C(clk_x16),
.CE(1'b1),
.D(\cycle[0]_rep_i_1_n_0 ),
.Q(\cycle_reg[0]_rep_n_0 ),
.R(\cycle[3]_i_1_n_0 ));
(* ORIG_CELL_NAME = "cycle_reg[1]" *)
FDRE #(
.INIT(1'b0))
\cycle_reg[1]
(.C(clk_x16),
.CE(1'b1),
.D(\cycle[1]_i_1_n_0 ),
.Q(cycle[1]),
.R(\cycle[3]_i_1_n_0 ));
(* ORIG_CELL_NAME = "cycle_reg[1]" *)
FDRE #(
.INIT(1'b0))
\cycle_reg[1]_rep
(.C(clk_x16),
.CE(1'b1),
.D(\cycle[1]_rep_i_1_n_0 ),
.Q(\cycle_reg[1]_rep_n_0 ),
.R(\cycle[3]_i_1_n_0 ));
(* ORIG_CELL_NAME = "cycle_reg[1]" *)
FDRE #(
.INIT(1'b0))
\cycle_reg[1]_rep__0
(.C(clk_x16),
.CE(1'b1),
.D(\cycle[1]_rep_i_1__0_n_0 ),
.Q(\cycle_reg[1]_rep__0_n_0 ),
.R(\cycle[3]_i_1_n_0 ));
(* ORIG_CELL_NAME = "cycle_reg[2]" *)
FDRE #(
.INIT(1'b0))
\cycle_reg[2]
(.C(clk_x16),
.CE(1'b1),
.D(\cycle[2]_i_1_n_0 ),
.Q(cycle[2]),
.R(\cycle[3]_i_1_n_0 ));
(* ORIG_CELL_NAME = "cycle_reg[2]" *)
FDRE #(
.INIT(1'b0))
\cycle_reg[2]_rep
(.C(clk_x16),
.CE(1'b1),
.D(\cycle[2]_rep_i_1_n_0 ),
.Q(\cycle_reg[2]_rep_n_0 ),
.R(\cycle[3]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\cycle_reg[3]
(.C(clk_x16),
.CE(1'b1),
.D(\cycle[3]_i_2_n_0 ),
.Q(cycle[3]),
.R(\cycle[3]_i_1_n_0 ));
DSP48E1 #(
.ACASCREG(1),
.ADREG(1),
.ALUMODEREG(0),
.AREG(1),
.AUTORESET_PATDET("NO_RESET"),
.A_INPUT("DIRECT"),
.BCASCREG(1),
.BREG(1),
.B_INPUT("DIRECT"),
.CARRYINREG(0),
.CARRYINSELREG(0),
.CREG(1),
.DREG(1),
.INMODEREG(0),
.MASK(48'h3FFFFFFFFFFF),
.MREG(1),
.OPMODEREG(0),
.PATTERN(48'h000000000000),
.PREG(0),
.SEL_MASK("MASK"),
.SEL_PATTERN("PATTERN"),
.USE_DPORT("FALSE"),
.USE_MULT("MULTIPLY"),
.USE_PATTERN_DETECT("NO_PATDET"),
.USE_SIMD("ONE48"))
det_0_reg
(.A({A[15],A[15],A[15],A[15],A[15],A[15],A[15],A[15],A[15],A[15],A[15],A[15],A[15],A[15],A}),
.ACIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.ACOUT(NLW_det_0_reg_ACOUT_UNCONNECTED[29:0]),
.ALUMODE({1'b0,1'b0,1'b0,1'b0}),
.B({B[15],B[15],B}),
.BCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.BCOUT(NLW_det_0_reg_BCOUT_UNCONNECTED[17:0]),
.C({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
.CARRYCASCIN(1'b0),
.CARRYCASCOUT(NLW_det_0_reg_CARRYCASCOUT_UNCONNECTED),
.CARRYIN(1'b0),
.CARRYINSEL({1'b0,1'b0,1'b0}),
.CARRYOUT(NLW_det_0_reg_CARRYOUT_UNCONNECTED[3:0]),
.CEA1(1'b0),
.CEA2(Lxx),
.CEAD(1'b0),
.CEALUMODE(1'b0),
.CEB1(1'b0),
.CEB2(det_0_reg_i_2_n_0),
.CEC(1'b0),
.CECARRYIN(1'b0),
.CECTRL(1'b0),
.CED(1'b0),
.CEINMODE(1'b0),
.CEM(det_0),
.CEP(1'b0),
.CLK(clk_x16),
.D({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.INMODE({1'b0,1'b0,1'b0,1'b0,1'b0}),
.MULTSIGNIN(1'b0),
.MULTSIGNOUT(NLW_det_0_reg_MULTSIGNOUT_UNCONNECTED),
.OPMODE({1'b0,1'b0,1'b0,1'b0,1'b1,1'b0,1'b1}),
.OVERFLOW(NLW_det_0_reg_OVERFLOW_UNCONNECTED),
.P(NLW_det_0_reg_P_UNCONNECTED[47:0]),
.PATTERNBDETECT(NLW_det_0_reg_PATTERNBDETECT_UNCONNECTED),
.PATTERNDETECT(NLW_det_0_reg_PATTERNDETECT_UNCONNECTED),
.PCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.PCOUT({det_0_reg_n_106,det_0_reg_n_107,det_0_reg_n_108,det_0_reg_n_109,det_0_reg_n_110,det_0_reg_n_111,det_0_reg_n_112,det_0_reg_n_113,det_0_reg_n_114,det_0_reg_n_115,det_0_reg_n_116,det_0_reg_n_117,det_0_reg_n_118,det_0_reg_n_119,det_0_reg_n_120,det_0_reg_n_121,det_0_reg_n_122,det_0_reg_n_123,det_0_reg_n_124,det_0_reg_n_125,det_0_reg_n_126,det_0_reg_n_127,det_0_reg_n_128,det_0_reg_n_129,det_0_reg_n_130,det_0_reg_n_131,det_0_reg_n_132,det_0_reg_n_133,det_0_reg_n_134,det_0_reg_n_135,det_0_reg_n_136,det_0_reg_n_137,det_0_reg_n_138,det_0_reg_n_139,det_0_reg_n_140,det_0_reg_n_141,det_0_reg_n_142,det_0_reg_n_143,det_0_reg_n_144,det_0_reg_n_145,det_0_reg_n_146,det_0_reg_n_147,det_0_reg_n_148,det_0_reg_n_149,det_0_reg_n_150,det_0_reg_n_151,det_0_reg_n_152,det_0_reg_n_153}),
.RSTA(1'b0),
.RSTALLCARRYIN(1'b0),
.RSTALUMODE(1'b0),
.RSTB(1'b0),
.RSTC(1'b0),
.RSTCTRL(1'b0),
.RSTD(1'b0),
.RSTINMODE(1'b0),
.RSTM(1'b0),
.RSTP(1'b0),
.UNDERFLOW(NLW_det_0_reg_UNDERFLOW_UNCONNECTED));
LUT6 #(
.INIT(64'h0000000000008000))
det_0_reg_i_1
(.I0(\cycle_reg[0]_rep_n_0 ),
.I1(active),
.I2(rst),
.I3(\cycle_reg[1]_rep__0_n_0 ),
.I4(cycle[2]),
.I5(cycle[3]),
.O(Lxx));
LUT6 #(
.INIT(64'h2000000000000000))
det_0_reg_i_2
(.I0(cycle[2]),
.I1(cycle[3]),
.I2(\cycle_reg[1]_rep__0_n_0 ),
.I3(\cycle_reg[0]_rep_n_0 ),
.I4(rst),
.I5(active),
.O(det_0_reg_i_2_n_0));
LUT6 #(
.INIT(64'h0000000008000000))
det_0_reg_i_3
(.I0(cycle[2]),
.I1(cycle[3]),
.I2(cycle[1]),
.I3(rst),
.I4(active),
.I5(\cycle_reg[0]_rep_n_0 ),
.O(det_0));
(* SOFT_HLUTNM = "soft_lutpair44" *)
LUT3 #(
.INIT(8'hAC))
\det_abs[10]_i_1
(.I0(det_abs0[10]),
.I1(det_reg_n_95),
.I2(det_reg_n_74),
.O(\det_abs[10]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair45" *)
LUT3 #(
.INIT(8'hAC))
\det_abs[11]_i_1
(.I0(det_abs0[11]),
.I1(det_reg_n_94),
.I2(det_reg_n_74),
.O(\det_abs[11]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair46" *)
LUT3 #(
.INIT(8'hAC))
\det_abs[12]_i_1
(.I0(det_abs0[12]),
.I1(det_reg_n_93),
.I2(det_reg_n_74),
.O(\det_abs[12]_i_1_n_0 ));
LUT1 #(
.INIT(2'h1))
\det_abs[12]_i_3
(.I0(det_reg_n_93),
.O(\det_abs[12]_i_3_n_0 ));
LUT1 #(
.INIT(2'h1))
\det_abs[12]_i_4
(.I0(det_reg_n_94),
.O(\det_abs[12]_i_4_n_0 ));
LUT1 #(
.INIT(2'h1))
\det_abs[12]_i_5
(.I0(det_reg_n_95),
.O(\det_abs[12]_i_5_n_0 ));
LUT1 #(
.INIT(2'h1))
\det_abs[12]_i_6
(.I0(det_reg_n_96),
.O(\det_abs[12]_i_6_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair47" *)
LUT3 #(
.INIT(8'hAC))
\det_abs[13]_i_1
(.I0(det_abs0[13]),
.I1(det_reg_n_92),
.I2(det_reg_n_74),
.O(\det_abs[13]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair48" *)
LUT3 #(
.INIT(8'hAC))
\det_abs[14]_i_1
(.I0(det_abs0[14]),
.I1(det_reg_n_91),
.I2(det_reg_n_74),
.O(\det_abs[14]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair47" *)
LUT3 #(
.INIT(8'hAC))
\det_abs[15]_i_1
(.I0(det_abs0[15]),
.I1(det_reg_n_90),
.I2(det_reg_n_74),
.O(\det_abs[15]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair46" *)
LUT3 #(
.INIT(8'hAC))
\det_abs[16]_i_1
(.I0(det_abs0[16]),
.I1(det_reg_n_89),
.I2(det_reg_n_74),
.O(\det_abs[16]_i_1_n_0 ));
LUT1 #(
.INIT(2'h1))
\det_abs[16]_i_3
(.I0(det_reg_n_89),
.O(\det_abs[16]_i_3_n_0 ));
LUT1 #(
.INIT(2'h1))
\det_abs[16]_i_4
(.I0(det_reg_n_90),
.O(\det_abs[16]_i_4_n_0 ));
LUT1 #(
.INIT(2'h1))
\det_abs[16]_i_5
(.I0(det_reg_n_91),
.O(\det_abs[16]_i_5_n_0 ));
LUT1 #(
.INIT(2'h1))
\det_abs[16]_i_6
(.I0(det_reg_n_92),
.O(\det_abs[16]_i_6_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair45" *)
LUT3 #(
.INIT(8'hAC))
\det_abs[17]_i_1
(.I0(det_abs0[17]),
.I1(det_reg_n_88),
.I2(det_reg_n_74),
.O(\det_abs[17]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair44" *)
LUT3 #(
.INIT(8'hAC))
\det_abs[18]_i_1
(.I0(det_abs0[18]),
.I1(det_reg_n_87),
.I2(det_reg_n_74),
.O(\det_abs[18]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair43" *)
LUT3 #(
.INIT(8'hAC))
\det_abs[19]_i_1
(.I0(det_abs0[19]),
.I1(det_reg_n_86),
.I2(det_reg_n_74),
.O(\det_abs[19]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair27" *)
LUT3 #(
.INIT(8'hAC))
\det_abs[1]_i_1
(.I0(det_abs0[1]),
.I1(det_reg_n_104),
.I2(det_reg_n_74),
.O(\det_abs[1]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair42" *)
LUT3 #(
.INIT(8'hAC))
\det_abs[20]_i_1
(.I0(det_abs0[20]),
.I1(det_reg_n_85),
.I2(det_reg_n_74),
.O(\det_abs[20]_i_1_n_0 ));
LUT1 #(
.INIT(2'h1))
\det_abs[20]_i_3
(.I0(det_reg_n_85),
.O(\det_abs[20]_i_3_n_0 ));
LUT1 #(
.INIT(2'h1))
\det_abs[20]_i_4
(.I0(det_reg_n_86),
.O(\det_abs[20]_i_4_n_0 ));
LUT1 #(
.INIT(2'h1))
\det_abs[20]_i_5
(.I0(det_reg_n_87),
.O(\det_abs[20]_i_5_n_0 ));
LUT1 #(
.INIT(2'h1))
\det_abs[20]_i_6
(.I0(det_reg_n_88),
.O(\det_abs[20]_i_6_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair41" *)
LUT3 #(
.INIT(8'hAC))
\det_abs[21]_i_1
(.I0(det_abs0[21]),
.I1(det_reg_n_84),
.I2(det_reg_n_74),
.O(\det_abs[21]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair40" *)
LUT3 #(
.INIT(8'hAC))
\det_abs[22]_i_1
(.I0(det_abs0[22]),
.I1(det_reg_n_83),
.I2(det_reg_n_74),
.O(\det_abs[22]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair38" *)
LUT3 #(
.INIT(8'hAC))
\det_abs[23]_i_1
(.I0(det_abs0[23]),
.I1(det_reg_n_82),
.I2(det_reg_n_74),
.O(\det_abs[23]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair35" *)
LUT3 #(
.INIT(8'hAC))
\det_abs[24]_i_1
(.I0(det_abs0[24]),
.I1(det_reg_n_81),
.I2(det_reg_n_74),
.O(\det_abs[24]_i_1_n_0 ));
LUT1 #(
.INIT(2'h1))
\det_abs[24]_i_3
(.I0(det_reg_n_81),
.O(\det_abs[24]_i_3_n_0 ));
LUT1 #(
.INIT(2'h1))
\det_abs[24]_i_4
(.I0(det_reg_n_82),
.O(\det_abs[24]_i_4_n_0 ));
LUT1 #(
.INIT(2'h1))
\det_abs[24]_i_5
(.I0(det_reg_n_83),
.O(\det_abs[24]_i_5_n_0 ));
LUT1 #(
.INIT(2'h1))
\det_abs[24]_i_6
(.I0(det_reg_n_84),
.O(\det_abs[24]_i_6_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair48" *)
LUT3 #(
.INIT(8'hAC))
\det_abs[25]_i_1
(.I0(det_abs0[25]),
.I1(det_reg_n_80),
.I2(det_reg_n_74),
.O(\det_abs[25]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair29" *)
LUT3 #(
.INIT(8'hAC))
\det_abs[26]_i_1
(.I0(det_abs0[26]),
.I1(det_reg_n_79),
.I2(det_reg_n_74),
.O(\det_abs[26]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair27" *)
LUT3 #(
.INIT(8'hAC))
\det_abs[27]_i_1
(.I0(det_abs0[27]),
.I1(det_reg_n_78),
.I2(det_reg_n_74),
.O(\det_abs[27]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair26" *)
LUT3 #(
.INIT(8'hAC))
\det_abs[28]_i_1
(.I0(det_abs0[28]),
.I1(det_reg_n_77),
.I2(det_reg_n_74),
.O(\det_abs[28]_i_1_n_0 ));
LUT1 #(
.INIT(2'h1))
\det_abs[28]_i_3
(.I0(det_reg_n_77),
.O(\det_abs[28]_i_3_n_0 ));
LUT1 #(
.INIT(2'h1))
\det_abs[28]_i_4
(.I0(det_reg_n_78),
.O(\det_abs[28]_i_4_n_0 ));
LUT1 #(
.INIT(2'h1))
\det_abs[28]_i_5
(.I0(det_reg_n_79),
.O(\det_abs[28]_i_5_n_0 ));
LUT1 #(
.INIT(2'h1))
\det_abs[28]_i_6
(.I0(det_reg_n_80),
.O(\det_abs[28]_i_6_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair30" *)
LUT3 #(
.INIT(8'hAC))
\det_abs[29]_i_1
(.I0(det_abs0[29]),
.I1(det_reg_n_76),
.I2(det_reg_n_74),
.O(\det_abs[29]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair29" *)
LUT3 #(
.INIT(8'hAC))
\det_abs[2]_i_1
(.I0(det_abs0[2]),
.I1(det_reg_n_103),
.I2(det_reg_n_74),
.O(\det_abs[2]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair26" *)
LUT3 #(
.INIT(8'hAC))
\det_abs[30]_i_1
(.I0(det_abs0[30]),
.I1(det_reg_n_75),
.I2(det_reg_n_74),
.O(\det_abs[30]_i_1_n_0 ));
LUT2 #(
.INIT(4'h8))
\det_abs[31]_i_1
(.I0(det_abs0[31]),
.I1(det_reg_n_74),
.O(\det_abs[31]_i_1_n_0 ));
LUT1 #(
.INIT(2'h1))
\det_abs[31]_i_3
(.I0(det_reg_n_74),
.O(\det_abs[31]_i_3_n_0 ));
LUT1 #(
.INIT(2'h1))
\det_abs[31]_i_4
(.I0(det_reg_n_75),
.O(\det_abs[31]_i_4_n_0 ));
LUT1 #(
.INIT(2'h1))
\det_abs[31]_i_5
(.I0(det_reg_n_76),
.O(\det_abs[31]_i_5_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair30" *)
LUT3 #(
.INIT(8'hAC))
\det_abs[3]_i_1
(.I0(det_abs0[3]),
.I1(det_reg_n_102),
.I2(det_reg_n_74),
.O(\det_abs[3]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair35" *)
LUT3 #(
.INIT(8'hAC))
\det_abs[4]_i_1
(.I0(det_abs0[4]),
.I1(det_reg_n_101),
.I2(det_reg_n_74),
.O(\det_abs[4]_i_1_n_0 ));
LUT1 #(
.INIT(2'h1))
\det_abs[4]_i_3
(.I0(det_reg_n_105),
.O(\det_abs[4]_i_3_n_0 ));
LUT1 #(
.INIT(2'h1))
\det_abs[4]_i_4
(.I0(det_reg_n_101),
.O(\det_abs[4]_i_4_n_0 ));
LUT1 #(
.INIT(2'h1))
\det_abs[4]_i_5
(.I0(det_reg_n_102),
.O(\det_abs[4]_i_5_n_0 ));
LUT1 #(
.INIT(2'h1))
\det_abs[4]_i_6
(.I0(det_reg_n_103),
.O(\det_abs[4]_i_6_n_0 ));
LUT1 #(
.INIT(2'h1))
\det_abs[4]_i_7
(.I0(det_reg_n_104),
.O(\det_abs[4]_i_7_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair38" *)
LUT3 #(
.INIT(8'hAC))
\det_abs[5]_i_1
(.I0(det_abs0[5]),
.I1(det_reg_n_100),
.I2(det_reg_n_74),
.O(\det_abs[5]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair40" *)
LUT3 #(
.INIT(8'hAC))
\det_abs[6]_i_1
(.I0(det_abs0[6]),
.I1(det_reg_n_99),
.I2(det_reg_n_74),
.O(\det_abs[6]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair41" *)
LUT3 #(
.INIT(8'hAC))
\det_abs[7]_i_1
(.I0(det_abs0[7]),
.I1(det_reg_n_98),
.I2(det_reg_n_74),
.O(\det_abs[7]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair42" *)
LUT3 #(
.INIT(8'hAC))
\det_abs[8]_i_1
(.I0(det_abs0[8]),
.I1(det_reg_n_97),
.I2(det_reg_n_74),
.O(\det_abs[8]_i_1_n_0 ));
LUT1 #(
.INIT(2'h1))
\det_abs[8]_i_3
(.I0(det_reg_n_97),
.O(\det_abs[8]_i_3_n_0 ));
LUT1 #(
.INIT(2'h1))
\det_abs[8]_i_4
(.I0(det_reg_n_98),
.O(\det_abs[8]_i_4_n_0 ));
LUT1 #(
.INIT(2'h1))
\det_abs[8]_i_5
(.I0(det_reg_n_99),
.O(\det_abs[8]_i_5_n_0 ));
LUT1 #(
.INIT(2'h1))
\det_abs[8]_i_6
(.I0(det_reg_n_100),
.O(\det_abs[8]_i_6_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair43" *)
LUT3 #(
.INIT(8'hAC))
\det_abs[9]_i_1
(.I0(det_abs0[9]),
.I1(det_reg_n_96),
.I2(det_reg_n_74),
.O(\det_abs[9]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\det_abs_reg[0]
(.C(clk_x16),
.CE(y6),
.D(det_reg_n_105),
.Q(det_abs[0]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\det_abs_reg[10]
(.C(clk_x16),
.CE(y6),
.D(\det_abs[10]_i_1_n_0 ),
.Q(det_abs[10]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\det_abs_reg[11]
(.C(clk_x16),
.CE(y6),
.D(\det_abs[11]_i_1_n_0 ),
.Q(det_abs[11]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\det_abs_reg[12]
(.C(clk_x16),
.CE(y6),
.D(\det_abs[12]_i_1_n_0 ),
.Q(det_abs[12]),
.R(1'b0));
CARRY4 \det_abs_reg[12]_i_2
(.CI(\det_abs_reg[8]_i_2_n_0 ),
.CO({\det_abs_reg[12]_i_2_n_0 ,\det_abs_reg[12]_i_2_n_1 ,\det_abs_reg[12]_i_2_n_2 ,\det_abs_reg[12]_i_2_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(det_abs0[12:9]),
.S({\det_abs[12]_i_3_n_0 ,\det_abs[12]_i_4_n_0 ,\det_abs[12]_i_5_n_0 ,\det_abs[12]_i_6_n_0 }));
FDRE #(
.INIT(1'b0))
\det_abs_reg[13]
(.C(clk_x16),
.CE(y6),
.D(\det_abs[13]_i_1_n_0 ),
.Q(det_abs[13]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\det_abs_reg[14]
(.C(clk_x16),
.CE(y6),
.D(\det_abs[14]_i_1_n_0 ),
.Q(det_abs[14]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\det_abs_reg[15]
(.C(clk_x16),
.CE(y6),
.D(\det_abs[15]_i_1_n_0 ),
.Q(det_abs[15]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\det_abs_reg[16]
(.C(clk_x16),
.CE(y6),
.D(\det_abs[16]_i_1_n_0 ),
.Q(det_abs[16]),
.R(1'b0));
CARRY4 \det_abs_reg[16]_i_2
(.CI(\det_abs_reg[12]_i_2_n_0 ),
.CO({\det_abs_reg[16]_i_2_n_0 ,\det_abs_reg[16]_i_2_n_1 ,\det_abs_reg[16]_i_2_n_2 ,\det_abs_reg[16]_i_2_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(det_abs0[16:13]),
.S({\det_abs[16]_i_3_n_0 ,\det_abs[16]_i_4_n_0 ,\det_abs[16]_i_5_n_0 ,\det_abs[16]_i_6_n_0 }));
FDRE #(
.INIT(1'b0))
\det_abs_reg[17]
(.C(clk_x16),
.CE(y6),
.D(\det_abs[17]_i_1_n_0 ),
.Q(det_abs[17]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\det_abs_reg[18]
(.C(clk_x16),
.CE(y6),
.D(\det_abs[18]_i_1_n_0 ),
.Q(det_abs[18]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\det_abs_reg[19]
(.C(clk_x16),
.CE(y6),
.D(\det_abs[19]_i_1_n_0 ),
.Q(det_abs[19]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\det_abs_reg[1]
(.C(clk_x16),
.CE(y6),
.D(\det_abs[1]_i_1_n_0 ),
.Q(det_abs[1]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\det_abs_reg[20]
(.C(clk_x16),
.CE(y6),
.D(\det_abs[20]_i_1_n_0 ),
.Q(det_abs[20]),
.R(1'b0));
CARRY4 \det_abs_reg[20]_i_2
(.CI(\det_abs_reg[16]_i_2_n_0 ),
.CO({\det_abs_reg[20]_i_2_n_0 ,\det_abs_reg[20]_i_2_n_1 ,\det_abs_reg[20]_i_2_n_2 ,\det_abs_reg[20]_i_2_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(det_abs0[20:17]),
.S({\det_abs[20]_i_3_n_0 ,\det_abs[20]_i_4_n_0 ,\det_abs[20]_i_5_n_0 ,\det_abs[20]_i_6_n_0 }));
FDRE #(
.INIT(1'b0))
\det_abs_reg[21]
(.C(clk_x16),
.CE(y6),
.D(\det_abs[21]_i_1_n_0 ),
.Q(det_abs[21]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\det_abs_reg[22]
(.C(clk_x16),
.CE(y6),
.D(\det_abs[22]_i_1_n_0 ),
.Q(det_abs[22]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\det_abs_reg[23]
(.C(clk_x16),
.CE(y6),
.D(\det_abs[23]_i_1_n_0 ),
.Q(det_abs[23]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\det_abs_reg[24]
(.C(clk_x16),
.CE(y6),
.D(\det_abs[24]_i_1_n_0 ),
.Q(det_abs[24]),
.R(1'b0));
CARRY4 \det_abs_reg[24]_i_2
(.CI(\det_abs_reg[20]_i_2_n_0 ),
.CO({\det_abs_reg[24]_i_2_n_0 ,\det_abs_reg[24]_i_2_n_1 ,\det_abs_reg[24]_i_2_n_2 ,\det_abs_reg[24]_i_2_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(det_abs0[24:21]),
.S({\det_abs[24]_i_3_n_0 ,\det_abs[24]_i_4_n_0 ,\det_abs[24]_i_5_n_0 ,\det_abs[24]_i_6_n_0 }));
FDRE #(
.INIT(1'b0))
\det_abs_reg[25]
(.C(clk_x16),
.CE(y6),
.D(\det_abs[25]_i_1_n_0 ),
.Q(det_abs[25]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\det_abs_reg[26]
(.C(clk_x16),
.CE(y6),
.D(\det_abs[26]_i_1_n_0 ),
.Q(det_abs[26]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\det_abs_reg[27]
(.C(clk_x16),
.CE(y6),
.D(\det_abs[27]_i_1_n_0 ),
.Q(det_abs[27]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\det_abs_reg[28]
(.C(clk_x16),
.CE(y6),
.D(\det_abs[28]_i_1_n_0 ),
.Q(det_abs[28]),
.R(1'b0));
CARRY4 \det_abs_reg[28]_i_2
(.CI(\det_abs_reg[24]_i_2_n_0 ),
.CO({\det_abs_reg[28]_i_2_n_0 ,\det_abs_reg[28]_i_2_n_1 ,\det_abs_reg[28]_i_2_n_2 ,\det_abs_reg[28]_i_2_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(det_abs0[28:25]),
.S({\det_abs[28]_i_3_n_0 ,\det_abs[28]_i_4_n_0 ,\det_abs[28]_i_5_n_0 ,\det_abs[28]_i_6_n_0 }));
FDRE #(
.INIT(1'b0))
\det_abs_reg[29]
(.C(clk_x16),
.CE(y6),
.D(\det_abs[29]_i_1_n_0 ),
.Q(det_abs[29]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\det_abs_reg[2]
(.C(clk_x16),
.CE(y6),
.D(\det_abs[2]_i_1_n_0 ),
.Q(det_abs[2]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\det_abs_reg[30]
(.C(clk_x16),
.CE(y6),
.D(\det_abs[30]_i_1_n_0 ),
.Q(det_abs[30]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\det_abs_reg[31]
(.C(clk_x16),
.CE(y6),
.D(\det_abs[31]_i_1_n_0 ),
.Q(det_abs[31]),
.R(1'b0));
CARRY4 \det_abs_reg[31]_i_2
(.CI(\det_abs_reg[28]_i_2_n_0 ),
.CO({\NLW_det_abs_reg[31]_i_2_CO_UNCONNECTED [3:2],\det_abs_reg[31]_i_2_n_2 ,\det_abs_reg[31]_i_2_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O({\NLW_det_abs_reg[31]_i_2_O_UNCONNECTED [3],det_abs0[31:29]}),
.S({1'b0,\det_abs[31]_i_3_n_0 ,\det_abs[31]_i_4_n_0 ,\det_abs[31]_i_5_n_0 }));
FDRE #(
.INIT(1'b0))
\det_abs_reg[3]
(.C(clk_x16),
.CE(y6),
.D(\det_abs[3]_i_1_n_0 ),
.Q(det_abs[3]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\det_abs_reg[4]
(.C(clk_x16),
.CE(y6),
.D(\det_abs[4]_i_1_n_0 ),
.Q(det_abs[4]),
.R(1'b0));
CARRY4 \det_abs_reg[4]_i_2
(.CI(1'b0),
.CO({\det_abs_reg[4]_i_2_n_0 ,\det_abs_reg[4]_i_2_n_1 ,\det_abs_reg[4]_i_2_n_2 ,\det_abs_reg[4]_i_2_n_3 }),
.CYINIT(\det_abs[4]_i_3_n_0 ),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(det_abs0[4:1]),
.S({\det_abs[4]_i_4_n_0 ,\det_abs[4]_i_5_n_0 ,\det_abs[4]_i_6_n_0 ,\det_abs[4]_i_7_n_0 }));
FDRE #(
.INIT(1'b0))
\det_abs_reg[5]
(.C(clk_x16),
.CE(y6),
.D(\det_abs[5]_i_1_n_0 ),
.Q(det_abs[5]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\det_abs_reg[6]
(.C(clk_x16),
.CE(y6),
.D(\det_abs[6]_i_1_n_0 ),
.Q(det_abs[6]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\det_abs_reg[7]
(.C(clk_x16),
.CE(y6),
.D(\det_abs[7]_i_1_n_0 ),
.Q(det_abs[7]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\det_abs_reg[8]
(.C(clk_x16),
.CE(y6),
.D(\det_abs[8]_i_1_n_0 ),
.Q(det_abs[8]),
.R(1'b0));
CARRY4 \det_abs_reg[8]_i_2
(.CI(\det_abs_reg[4]_i_2_n_0 ),
.CO({\det_abs_reg[8]_i_2_n_0 ,\det_abs_reg[8]_i_2_n_1 ,\det_abs_reg[8]_i_2_n_2 ,\det_abs_reg[8]_i_2_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(det_abs0[8:5]),
.S({\det_abs[8]_i_3_n_0 ,\det_abs[8]_i_4_n_0 ,\det_abs[8]_i_5_n_0 ,\det_abs[8]_i_6_n_0 }));
FDRE #(
.INIT(1'b0))
\det_abs_reg[9]
(.C(clk_x16),
.CE(y6),
.D(\det_abs[9]_i_1_n_0 ),
.Q(det_abs[9]),
.R(1'b0));
DSP48E1 #(
.ACASCREG(1),
.ADREG(1),
.ALUMODEREG(0),
.AREG(1),
.AUTORESET_PATDET("NO_RESET"),
.A_INPUT("DIRECT"),
.BCASCREG(1),
.BREG(1),
.B_INPUT("DIRECT"),
.CARRYINREG(0),
.CARRYINSELREG(0),
.CREG(1),
.DREG(1),
.INMODEREG(0),
.MASK(48'h3FFFFFFFFFFF),
.MREG(1),
.OPMODEREG(0),
.PATTERN(48'h000000000000),
.PREG(1),
.SEL_MASK("MASK"),
.SEL_PATTERN("PATTERN"),
.USE_DPORT("FALSE"),
.USE_MULT("MULTIPLY"),
.USE_PATTERN_DETECT("NO_PATDET"),
.USE_SIMD("ONE48"))
det_reg
(.A({Lxy0__1_carry__2_n_4,Lxy0__1_carry__2_n_4,Lxy0__1_carry__2_n_4,Lxy0__1_carry__2_n_4,Lxy0__1_carry__2_n_4,Lxy0__1_carry__2_n_4,Lxy0__1_carry__2_n_4,Lxy0__1_carry__2_n_4,Lxy0__1_carry__2_n_4,Lxy0__1_carry__2_n_4,Lxy0__1_carry__2_n_4,Lxy0__1_carry__2_n_4,Lxy0__1_carry__2_n_4,Lxy0__1_carry__2_n_4,Lxy0__1_carry__2_n_4,Lxy0__1_carry__2_n_5,Lxy0__1_carry__2_n_6,Lxy0__1_carry__2_n_7,Lxy0__1_carry__1_n_4,Lxy0__1_carry__1_n_5,Lxy0__1_carry__1_n_6,Lxy0__1_carry__1_n_7,Lxy0__1_carry__0_n_4,Lxy0__1_carry__0_n_5,Lxy0__1_carry__0_n_6,Lxy0__1_carry__0_n_7,Lxy0__1_carry_n_4,Lxy0__1_carry_n_5,Lxy0__1_carry_n_6,Lxy0__1_carry_n_7}),
.ACIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.ACOUT(NLW_det_reg_ACOUT_UNCONNECTED[29:0]),
.ALUMODE({1'b0,1'b0,1'b1,1'b1}),
.B({Lxy0__1_carry__2_n_4,Lxy0__1_carry__2_n_4,Lxy0__1_carry__2_n_4,Lxy0__1_carry__2_n_5,Lxy0__1_carry__2_n_6,Lxy0__1_carry__2_n_7,Lxy0__1_carry__1_n_4,Lxy0__1_carry__1_n_5,Lxy0__1_carry__1_n_6,Lxy0__1_carry__1_n_7,Lxy0__1_carry__0_n_4,Lxy0__1_carry__0_n_5,Lxy0__1_carry__0_n_6,Lxy0__1_carry__0_n_7,Lxy0__1_carry_n_4,Lxy0__1_carry_n_5,Lxy0__1_carry_n_6,Lxy0__1_carry_n_7}),
.BCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.BCOUT(NLW_det_reg_BCOUT_UNCONNECTED[17:0]),
.C({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
.CARRYCASCIN(1'b0),
.CARRYCASCOUT(NLW_det_reg_CARRYCASCOUT_UNCONNECTED),
.CARRYIN(1'b0),
.CARRYINSEL({1'b0,1'b0,1'b0}),
.CARRYOUT(NLW_det_reg_CARRYOUT_UNCONNECTED[3:0]),
.CEA1(1'b0),
.CEA2(y3),
.CEAD(1'b0),
.CEALUMODE(1'b0),
.CEB1(1'b0),
.CEB2(y3),
.CEC(1'b0),
.CECARRYIN(1'b0),
.CECTRL(1'b0),
.CED(1'b0),
.CEINMODE(1'b0),
.CEM(y2),
.CEP(y9),
.CLK(clk_x16),
.D({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.INMODE({1'b0,1'b0,1'b0,1'b0,1'b0}),
.MULTSIGNIN(1'b0),
.MULTSIGNOUT(NLW_det_reg_MULTSIGNOUT_UNCONNECTED),
.OPMODE({1'b0,1'b0,1'b1,1'b0,1'b1,1'b0,1'b1}),
.OVERFLOW(NLW_det_reg_OVERFLOW_UNCONNECTED),
.P({NLW_det_reg_P_UNCONNECTED[47:32],det_reg_n_74,det_reg_n_75,det_reg_n_76,det_reg_n_77,det_reg_n_78,det_reg_n_79,det_reg_n_80,det_reg_n_81,det_reg_n_82,det_reg_n_83,det_reg_n_84,det_reg_n_85,det_reg_n_86,det_reg_n_87,det_reg_n_88,det_reg_n_89,det_reg_n_90,det_reg_n_91,det_reg_n_92,det_reg_n_93,det_reg_n_94,det_reg_n_95,det_reg_n_96,det_reg_n_97,det_reg_n_98,det_reg_n_99,det_reg_n_100,det_reg_n_101,det_reg_n_102,det_reg_n_103,det_reg_n_104,det_reg_n_105}),
.PATTERNBDETECT(NLW_det_reg_PATTERNBDETECT_UNCONNECTED),
.PATTERNDETECT(NLW_det_reg_PATTERNDETECT_UNCONNECTED),
.PCIN({det_0_reg_n_106,det_0_reg_n_107,det_0_reg_n_108,det_0_reg_n_109,det_0_reg_n_110,det_0_reg_n_111,det_0_reg_n_112,det_0_reg_n_113,det_0_reg_n_114,det_0_reg_n_115,det_0_reg_n_116,det_0_reg_n_117,det_0_reg_n_118,det_0_reg_n_119,det_0_reg_n_120,det_0_reg_n_121,det_0_reg_n_122,det_0_reg_n_123,det_0_reg_n_124,det_0_reg_n_125,det_0_reg_n_126,det_0_reg_n_127,det_0_reg_n_128,det_0_reg_n_129,det_0_reg_n_130,det_0_reg_n_131,det_0_reg_n_132,det_0_reg_n_133,det_0_reg_n_134,det_0_reg_n_135,det_0_reg_n_136,det_0_reg_n_137,det_0_reg_n_138,det_0_reg_n_139,det_0_reg_n_140,det_0_reg_n_141,det_0_reg_n_142,det_0_reg_n_143,det_0_reg_n_144,det_0_reg_n_145,det_0_reg_n_146,det_0_reg_n_147,det_0_reg_n_148,det_0_reg_n_149,det_0_reg_n_150,det_0_reg_n_151,det_0_reg_n_152,det_0_reg_n_153}),
.PCOUT(NLW_det_reg_PCOUT_UNCONNECTED[47:0]),
.RSTA(1'b0),
.RSTALLCARRYIN(1'b0),
.RSTALUMODE(1'b0),
.RSTB(1'b0),
.RSTC(1'b0),
.RSTCTRL(1'b0),
.RSTD(1'b0),
.RSTINMODE(1'b0),
.RSTM(1'b0),
.RSTP(1'b0),
.UNDERFLOW(NLW_det_reg_UNDERFLOW_UNCONNECTED));
LUT6 #(
.INIT(64'h0000000040000000))
det_reg_i_1
(.I0(\cycle_reg[2]_rep_n_0 ),
.I1(cycle[3]),
.I2(rst),
.I3(active),
.I4(\cycle_reg[0]_rep_n_0 ),
.I5(\cycle_reg[1]_rep__0_n_0 ),
.O(y2));
LUT6 #(
.INIT(64'h0000000080000000))
det_reg_i_2
(.I0(\cycle_reg[2]_rep_n_0 ),
.I1(cycle[3]),
.I2(rst),
.I3(active),
.I4(\cycle_reg[0]_rep_n_0 ),
.I5(\cycle_reg[1]_rep__0_n_0 ),
.O(y9));
FDRE #(
.INIT(1'b0))
\din_reg[0]
(.C(clk_x16),
.CE(det_0_reg_i_2_n_0),
.D(\cache_reg[8]_1 [0]),
.Q(\din_reg_n_0_[0] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\din_reg[10]
(.C(clk_x16),
.CE(det_0_reg_i_2_n_0),
.D(\cache_reg[8]_1 [10]),
.Q(\din_reg_n_0_[10] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\din_reg[11]
(.C(clk_x16),
.CE(det_0_reg_i_2_n_0),
.D(\cache_reg[8]_1 [11]),
.Q(\din_reg_n_0_[11] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\din_reg[12]
(.C(clk_x16),
.CE(det_0_reg_i_2_n_0),
.D(\cache_reg[8]_1 [12]),
.Q(\din_reg_n_0_[12] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\din_reg[13]
(.C(clk_x16),
.CE(det_0_reg_i_2_n_0),
.D(\cache_reg[8]_1 [13]),
.Q(\din_reg_n_0_[13] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\din_reg[14]
(.C(clk_x16),
.CE(det_0_reg_i_2_n_0),
.D(\cache_reg[8]_1 [14]),
.Q(\din_reg_n_0_[14] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\din_reg[15]
(.C(clk_x16),
.CE(det_0_reg_i_2_n_0),
.D(\cache_reg[8]_1 [15]),
.Q(\din_reg_n_0_[15] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\din_reg[1]
(.C(clk_x16),
.CE(det_0_reg_i_2_n_0),
.D(\cache_reg[8]_1 [1]),
.Q(\din_reg_n_0_[1] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\din_reg[2]
(.C(clk_x16),
.CE(det_0_reg_i_2_n_0),
.D(\cache_reg[8]_1 [2]),
.Q(\din_reg_n_0_[2] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\din_reg[3]
(.C(clk_x16),
.CE(det_0_reg_i_2_n_0),
.D(\cache_reg[8]_1 [3]),
.Q(\din_reg_n_0_[3] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\din_reg[4]
(.C(clk_x16),
.CE(det_0_reg_i_2_n_0),
.D(\cache_reg[8]_1 [4]),
.Q(\din_reg_n_0_[4] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\din_reg[5]
(.C(clk_x16),
.CE(det_0_reg_i_2_n_0),
.D(\cache_reg[8]_1 [5]),
.Q(\din_reg_n_0_[5] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\din_reg[6]
(.C(clk_x16),
.CE(det_0_reg_i_2_n_0),
.D(\cache_reg[8]_1 [6]),
.Q(\din_reg_n_0_[6] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\din_reg[7]
(.C(clk_x16),
.CE(det_0_reg_i_2_n_0),
.D(\cache_reg[8]_1 [7]),
.Q(\din_reg_n_0_[7] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\din_reg[8]
(.C(clk_x16),
.CE(det_0_reg_i_2_n_0),
.D(\cache_reg[8]_1 [8]),
.Q(\din_reg_n_0_[8] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\din_reg[9]
(.C(clk_x16),
.CE(det_0_reg_i_2_n_0),
.D(\cache_reg[8]_1 [9]),
.Q(\din_reg_n_0_[9] ),
.R(1'b0));
LUT6 #(
.INIT(64'h8000000000000000))
\hessian_out[31]_i_1
(.I0(rst),
.I1(active),
.I2(cycle[3]),
.I3(cycle[0]),
.I4(\cycle_reg[2]_rep_n_0 ),
.I5(\cycle_reg[1]_rep__0_n_0 ),
.O(y3));
FDRE \hessian_out_reg[0]
(.C(clk_x16),
.CE(y3),
.D(det_abs[0]),
.Q(hessian_out[0]),
.R(1'b0));
FDRE \hessian_out_reg[10]
(.C(clk_x16),
.CE(y3),
.D(det_abs[10]),
.Q(hessian_out[10]),
.R(1'b0));
FDRE \hessian_out_reg[11]
(.C(clk_x16),
.CE(y3),
.D(det_abs[11]),
.Q(hessian_out[11]),
.R(1'b0));
FDRE \hessian_out_reg[12]
(.C(clk_x16),
.CE(y3),
.D(det_abs[12]),
.Q(hessian_out[12]),
.R(1'b0));
FDRE \hessian_out_reg[13]
(.C(clk_x16),
.CE(y3),
.D(det_abs[13]),
.Q(hessian_out[13]),
.R(1'b0));
FDRE \hessian_out_reg[14]
(.C(clk_x16),
.CE(y3),
.D(det_abs[14]),
.Q(hessian_out[14]),
.R(1'b0));
FDRE \hessian_out_reg[15]
(.C(clk_x16),
.CE(y3),
.D(det_abs[15]),
.Q(hessian_out[15]),
.R(1'b0));
FDRE \hessian_out_reg[16]
(.C(clk_x16),
.CE(y3),
.D(det_abs[16]),
.Q(hessian_out[16]),
.R(1'b0));
FDRE \hessian_out_reg[17]
(.C(clk_x16),
.CE(y3),
.D(det_abs[17]),
.Q(hessian_out[17]),
.R(1'b0));
FDRE \hessian_out_reg[18]
(.C(clk_x16),
.CE(y3),
.D(det_abs[18]),
.Q(hessian_out[18]),
.R(1'b0));
FDRE \hessian_out_reg[19]
(.C(clk_x16),
.CE(y3),
.D(det_abs[19]),
.Q(hessian_out[19]),
.R(1'b0));
FDRE \hessian_out_reg[1]
(.C(clk_x16),
.CE(y3),
.D(det_abs[1]),
.Q(hessian_out[1]),
.R(1'b0));
FDRE \hessian_out_reg[20]
(.C(clk_x16),
.CE(y3),
.D(det_abs[20]),
.Q(hessian_out[20]),
.R(1'b0));
FDRE \hessian_out_reg[21]
(.C(clk_x16),
.CE(y3),
.D(det_abs[21]),
.Q(hessian_out[21]),
.R(1'b0));
FDRE \hessian_out_reg[22]
(.C(clk_x16),
.CE(y3),
.D(det_abs[22]),
.Q(hessian_out[22]),
.R(1'b0));
FDRE \hessian_out_reg[23]
(.C(clk_x16),
.CE(y3),
.D(det_abs[23]),
.Q(hessian_out[23]),
.R(1'b0));
FDRE \hessian_out_reg[24]
(.C(clk_x16),
.CE(y3),
.D(det_abs[24]),
.Q(hessian_out[24]),
.R(1'b0));
FDRE \hessian_out_reg[25]
(.C(clk_x16),
.CE(y3),
.D(det_abs[25]),
.Q(hessian_out[25]),
.R(1'b0));
FDRE \hessian_out_reg[26]
(.C(clk_x16),
.CE(y3),
.D(det_abs[26]),
.Q(hessian_out[26]),
.R(1'b0));
FDRE \hessian_out_reg[27]
(.C(clk_x16),
.CE(y3),
.D(det_abs[27]),
.Q(hessian_out[27]),
.R(1'b0));
FDRE \hessian_out_reg[28]
(.C(clk_x16),
.CE(y3),
.D(det_abs[28]),
.Q(hessian_out[28]),
.R(1'b0));
FDRE \hessian_out_reg[29]
(.C(clk_x16),
.CE(y3),
.D(det_abs[29]),
.Q(hessian_out[29]),
.R(1'b0));
FDRE \hessian_out_reg[2]
(.C(clk_x16),
.CE(y3),
.D(det_abs[2]),
.Q(hessian_out[2]),
.R(1'b0));
FDRE \hessian_out_reg[30]
(.C(clk_x16),
.CE(y3),
.D(det_abs[30]),
.Q(hessian_out[30]),
.R(1'b0));
FDRE \hessian_out_reg[31]
(.C(clk_x16),
.CE(y3),
.D(det_abs[31]),
.Q(hessian_out[31]),
.R(1'b0));
FDRE \hessian_out_reg[3]
(.C(clk_x16),
.CE(y3),
.D(det_abs[3]),
.Q(hessian_out[3]),
.R(1'b0));
FDRE \hessian_out_reg[4]
(.C(clk_x16),
.CE(y3),
.D(det_abs[4]),
.Q(hessian_out[4]),
.R(1'b0));
FDRE \hessian_out_reg[5]
(.C(clk_x16),
.CE(y3),
.D(det_abs[5]),
.Q(hessian_out[5]),
.R(1'b0));
FDRE \hessian_out_reg[6]
(.C(clk_x16),
.CE(y3),
.D(det_abs[6]),
.Q(hessian_out[6]),
.R(1'b0));
FDRE \hessian_out_reg[7]
(.C(clk_x16),
.CE(y3),
.D(det_abs[7]),
.Q(hessian_out[7]),
.R(1'b0));
FDRE \hessian_out_reg[8]
(.C(clk_x16),
.CE(y3),
.D(det_abs[8]),
.Q(hessian_out[8]),
.R(1'b0));
FDRE \hessian_out_reg[9]
(.C(clk_x16),
.CE(y3),
.D(det_abs[9]),
.Q(hessian_out[9]),
.R(1'b0));
LUT4 #(
.INIT(16'h0400))
i__carry__0_i_1
(.I0(\cycle_reg[1]_rep__0_n_0 ),
.I1(cycle[0]),
.I2(\cycle_reg[2]_rep_n_0 ),
.I3(cycle[3]),
.O(i__carry__0_i_1_n_0));
LUT2 #(
.INIT(4'h9))
i__carry__0_i_2
(.I0(\x_reg_n_0_[6] ),
.I1(\x_reg_n_0_[7] ),
.O(i__carry__0_i_2_n_0));
LUT2 #(
.INIT(4'h9))
i__carry__0_i_3
(.I0(\x_reg_n_0_[5] ),
.I1(\x_reg_n_0_[6] ),
.O(i__carry__0_i_3_n_0));
LUT2 #(
.INIT(4'h9))
i__carry__0_i_4
(.I0(\x_reg_n_0_[4] ),
.I1(\x_reg_n_0_[5] ),
.O(i__carry__0_i_4_n_0));
LUT5 #(
.INIT(32'h0020FFDF))
i__carry__0_i_5
(.I0(cycle[3]),
.I1(\cycle_reg[2]_rep_n_0 ),
.I2(cycle[0]),
.I3(\cycle_reg[1]_rep__0_n_0 ),
.I4(\x_reg_n_0_[4] ),
.O(i__carry__0_i_5_n_0));
LUT2 #(
.INIT(4'h9))
i__carry__1_i_1
(.I0(\x_reg_n_0_[8] ),
.I1(\x_reg_n_0_[9] ),
.O(i__carry__1_i_1_n_0));
LUT2 #(
.INIT(4'h9))
i__carry__1_i_2
(.I0(\x_reg_n_0_[7] ),
.I1(\x_reg_n_0_[8] ),
.O(i__carry__1_i_2_n_0));
LUT5 #(
.INIT(32'h0020FFDF))
i__carry_i_1
(.I0(cycle[3]),
.I1(\cycle_reg[2]_rep_n_0 ),
.I2(cycle[0]),
.I3(\cycle_reg[1]_rep__0_n_0 ),
.I4(\x_reg_n_0_[3] ),
.O(i__carry_i_1_n_0));
LUT4 #(
.INIT(16'hAA6A))
i__carry_i_2
(.I0(\x_reg_n_0_[2] ),
.I1(cycle[3]),
.I2(\cycle_reg[1]_rep__0_n_0 ),
.I3(\cycle_reg[2]_rep_n_0 ),
.O(i__carry_i_2_n_0));
LUT5 #(
.INIT(32'h55599555))
i__carry_i_3
(.I0(\x_reg_n_0_[1] ),
.I1(cycle[3]),
.I2(cycle[0]),
.I3(\cycle_reg[1]_rep__0_n_0 ),
.I4(\cycle_reg[2]_rep_n_0 ),
.O(i__carry_i_3_n_0));
LUT4 #(
.INIT(16'h5595))
i__carry_i_4
(.I0(\x_reg_n_0_[0] ),
.I1(cycle[3]),
.I2(cycle[0]),
.I3(\cycle_reg[2]_rep_n_0 ),
.O(i__carry_i_4_n_0));
FDRE #(
.INIT(1'b0))
\last_value_reg[0]
(.C(clk_x16),
.CE(x),
.D(\value_reg_n_0_[0] ),
.Q(last_value[0]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\last_value_reg[1]
(.C(clk_x16),
.CE(x),
.D(\value_reg_n_0_[1] ),
.Q(last_value[1]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\last_value_reg[2]
(.C(clk_x16),
.CE(x),
.D(\value_reg_n_0_[2] ),
.Q(last_value[2]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\last_value_reg[3]
(.C(clk_x16),
.CE(x),
.D(\value_reg_n_0_[3] ),
.Q(last_value[3]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\last_value_reg[4]
(.C(clk_x16),
.CE(x),
.D(\value_reg_n_0_[4] ),
.Q(last_value[4]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\last_value_reg[5]
(.C(clk_x16),
.CE(x),
.D(\value_reg_n_0_[5] ),
.Q(last_value[5]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\last_value_reg[6]
(.C(clk_x16),
.CE(x),
.D(\value_reg_n_0_[6] ),
.Q(last_value[6]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\last_value_reg[7]
(.C(clk_x16),
.CE(x),
.D(\value_reg_n_0_[7] ),
.Q(last_value[7]),
.R(1'b0));
LUT5 #(
.INIT(32'h00000008))
\left[15]_i_1
(.I0(\left[15]_i_2_n_0 ),
.I1(x),
.I2(\x_reg_n_0_[0] ),
.I3(\x_reg_n_0_[9] ),
.I4(\x_reg_n_0_[8] ),
.O(left));
(* SOFT_HLUTNM = "soft_lutpair17" *)
LUT4 #(
.INIT(16'h0001))
\left[15]_i_2
(.I0(\x_reg_n_0_[7] ),
.I1(\x_reg_n_0_[5] ),
.I2(\x_reg_n_0_[6] ),
.I3(\left[15]_i_3_n_0 ),
.O(\left[15]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair13" *)
LUT4 #(
.INIT(16'hFFFE))
\left[15]_i_3
(.I0(\x_reg_n_0_[4] ),
.I1(\x_reg_n_0_[1] ),
.I2(\x_reg_n_0_[2] ),
.I3(\x_reg_n_0_[3] ),
.O(\left[15]_i_3_n_0 ));
FDRE #(
.INIT(1'b0))
\left_reg[0]
(.C(clk_x16),
.CE(x),
.D(\cache_reg[0]_4 [0]),
.Q(\left_reg_n_0_[0] ),
.R(left));
FDRE #(
.INIT(1'b0))
\left_reg[10]
(.C(clk_x16),
.CE(x),
.D(\cache_reg[0]_4 [10]),
.Q(\left_reg_n_0_[10] ),
.R(left));
FDRE #(
.INIT(1'b0))
\left_reg[11]
(.C(clk_x16),
.CE(x),
.D(\cache_reg[0]_4 [11]),
.Q(\left_reg_n_0_[11] ),
.R(left));
FDRE #(
.INIT(1'b0))
\left_reg[12]
(.C(clk_x16),
.CE(x),
.D(\cache_reg[0]_4 [12]),
.Q(\left_reg_n_0_[12] ),
.R(left));
FDRE #(
.INIT(1'b0))
\left_reg[13]
(.C(clk_x16),
.CE(x),
.D(\cache_reg[0]_4 [13]),
.Q(\left_reg_n_0_[13] ),
.R(left));
FDRE #(
.INIT(1'b0))
\left_reg[14]
(.C(clk_x16),
.CE(x),
.D(\cache_reg[0]_4 [14]),
.Q(\left_reg_n_0_[14] ),
.R(left));
FDRE #(
.INIT(1'b0))
\left_reg[15]
(.C(clk_x16),
.CE(x),
.D(\cache_reg[0]_4 [15]),
.Q(\left_reg_n_0_[15] ),
.R(left));
FDRE #(
.INIT(1'b0))
\left_reg[1]
(.C(clk_x16),
.CE(x),
.D(\cache_reg[0]_4 [1]),
.Q(\left_reg_n_0_[1] ),
.R(left));
FDRE #(
.INIT(1'b0))
\left_reg[2]
(.C(clk_x16),
.CE(x),
.D(\cache_reg[0]_4 [2]),
.Q(\left_reg_n_0_[2] ),
.R(left));
FDRE #(
.INIT(1'b0))
\left_reg[3]
(.C(clk_x16),
.CE(x),
.D(\cache_reg[0]_4 [3]),
.Q(\left_reg_n_0_[3] ),
.R(left));
FDRE #(
.INIT(1'b0))
\left_reg[4]
(.C(clk_x16),
.CE(x),
.D(\cache_reg[0]_4 [4]),
.Q(\left_reg_n_0_[4] ),
.R(left));
FDRE #(
.INIT(1'b0))
\left_reg[5]
(.C(clk_x16),
.CE(x),
.D(\cache_reg[0]_4 [5]),
.Q(\left_reg_n_0_[5] ),
.R(left));
FDRE #(
.INIT(1'b0))
\left_reg[6]
(.C(clk_x16),
.CE(x),
.D(\cache_reg[0]_4 [6]),
.Q(\left_reg_n_0_[6] ),
.R(left));
FDRE #(
.INIT(1'b0))
\left_reg[7]
(.C(clk_x16),
.CE(x),
.D(\cache_reg[0]_4 [7]),
.Q(\left_reg_n_0_[7] ),
.R(left));
FDRE #(
.INIT(1'b0))
\left_reg[8]
(.C(clk_x16),
.CE(x),
.D(\cache_reg[0]_4 [8]),
.Q(\left_reg_n_0_[8] ),
.R(left));
FDRE #(
.INIT(1'b0))
\left_reg[9]
(.C(clk_x16),
.CE(x),
.D(\cache_reg[0]_4 [9]),
.Q(\left_reg_n_0_[9] ),
.R(left));
CARRY4 \plusOp_inferred__0/i__carry
(.CI(1'b0),
.CO({\plusOp_inferred__0/i__carry_n_0 ,\plusOp_inferred__0/i__carry_n_1 ,\plusOp_inferred__0/i__carry_n_2 ,\plusOp_inferred__0/i__carry_n_3 }),
.CYINIT(1'b0),
.DI({\x_reg_n_0_[3] ,\x_reg_n_0_[2] ,\x_reg_n_0_[1] ,\x_reg_n_0_[0] }),
.O({\plusOp_inferred__0/i__carry_n_4 ,\plusOp_inferred__0/i__carry_n_5 ,\plusOp_inferred__0/i__carry_n_6 ,\plusOp_inferred__0/i__carry_n_7 }),
.S({i__carry_i_1_n_0,i__carry_i_2_n_0,i__carry_i_3_n_0,i__carry_i_4_n_0}));
CARRY4 \plusOp_inferred__0/i__carry__0
(.CI(\plusOp_inferred__0/i__carry_n_0 ),
.CO({\plusOp_inferred__0/i__carry__0_n_0 ,\plusOp_inferred__0/i__carry__0_n_1 ,\plusOp_inferred__0/i__carry__0_n_2 ,\plusOp_inferred__0/i__carry__0_n_3 }),
.CYINIT(1'b0),
.DI({\x_reg_n_0_[6] ,\x_reg_n_0_[5] ,\x_reg_n_0_[4] ,i__carry__0_i_1_n_0}),
.O({\plusOp_inferred__0/i__carry__0_n_4 ,\plusOp_inferred__0/i__carry__0_n_5 ,\plusOp_inferred__0/i__carry__0_n_6 ,\plusOp_inferred__0/i__carry__0_n_7 }),
.S({i__carry__0_i_2_n_0,i__carry__0_i_3_n_0,i__carry__0_i_4_n_0,i__carry__0_i_5_n_0}));
CARRY4 \plusOp_inferred__0/i__carry__1
(.CI(\plusOp_inferred__0/i__carry__0_n_0 ),
.CO({\NLW_plusOp_inferred__0/i__carry__1_CO_UNCONNECTED [3:1],\plusOp_inferred__0/i__carry__1_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,\x_reg_n_0_[7] }),
.O({\NLW_plusOp_inferred__0/i__carry__1_O_UNCONNECTED [3:2],\plusOp_inferred__0/i__carry__1_n_6 ,\plusOp_inferred__0/i__carry__1_n_7 }),
.S({1'b0,1'b0,i__carry__1_i_1_n_0,i__carry__1_i_2_n_0}));
LUT6 #(
.INIT(64'h0000000000000002))
\top[15]_i_1
(.I0(x),
.I1(\top[15]_i_2_n_0 ),
.I2(\y_actual_reg_n_0_[3] ),
.I3(\y_actual_reg_n_0_[0] ),
.I4(\y_actual_reg_n_0_[1] ),
.I5(\y_actual_reg_n_0_[2] ),
.O(top));
LUT6 #(
.INIT(64'hFFFFFFFFFFFFFFFE))
\top[15]_i_2
(.I0(\y_actual_reg_n_0_[8] ),
.I1(\y_actual_reg_n_0_[9] ),
.I2(\y_actual_reg_n_0_[6] ),
.I3(\y_actual_reg_n_0_[7] ),
.I4(\y_actual_reg_n_0_[4] ),
.I5(\y_actual_reg_n_0_[5] ),
.O(\top[15]_i_2_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFEF00000020))
\top_left_0[0]_i_1
(.I0(dout_0[0]),
.I1(cycle[2]),
.I2(\cycle_reg[1]_rep_n_0 ),
.I3(\cycle_reg[0]_rep_n_0 ),
.I4(cycle[3]),
.I5(dout_1[0]),
.O(\top_left_0[0]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFEF00000020))
\top_left_0[10]_i_1
(.I0(dout_0[10]),
.I1(cycle[2]),
.I2(\cycle_reg[1]_rep_n_0 ),
.I3(\cycle_reg[0]_rep_n_0 ),
.I4(cycle[3]),
.I5(dout_1[10]),
.O(\top_left_0[10]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFEF00000020))
\top_left_0[11]_i_1
(.I0(dout_0[11]),
.I1(cycle[2]),
.I2(\cycle_reg[1]_rep_n_0 ),
.I3(\cycle_reg[0]_rep_n_0 ),
.I4(cycle[3]),
.I5(dout_1[11]),
.O(\top_left_0[11]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFEF00000020))
\top_left_0[12]_i_1
(.I0(dout_0[12]),
.I1(cycle[2]),
.I2(\cycle_reg[1]_rep_n_0 ),
.I3(\cycle_reg[0]_rep_n_0 ),
.I4(cycle[3]),
.I5(dout_1[12]),
.O(\top_left_0[12]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFEF00000020))
\top_left_0[13]_i_1
(.I0(dout_0[13]),
.I1(cycle[2]),
.I2(\cycle_reg[1]_rep_n_0 ),
.I3(\cycle_reg[0]_rep_n_0 ),
.I4(cycle[3]),
.I5(dout_1[13]),
.O(\top_left_0[13]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFEF00000020))
\top_left_0[14]_i_1
(.I0(dout_0[14]),
.I1(cycle[2]),
.I2(\cycle_reg[1]_rep_n_0 ),
.I3(\cycle_reg[0]_rep_n_0 ),
.I4(cycle[3]),
.I5(dout_1[14]),
.O(\top_left_0[14]_i_1_n_0 ));
LUT6 #(
.INIT(64'h8000700010000000))
\top_left_0[15]_i_1
(.I0(cycle[2]),
.I1(cycle[3]),
.I2(rst),
.I3(active),
.I4(\cycle_reg[0]_rep_n_0 ),
.I5(\cycle_reg[1]_rep_n_0 ),
.O(top_left_0));
LUT6 #(
.INIT(64'hFFFFFFEF00000020))
\top_left_0[15]_i_2
(.I0(dout_0[15]),
.I1(cycle[2]),
.I2(\cycle_reg[1]_rep_n_0 ),
.I3(\cycle_reg[0]_rep_n_0 ),
.I4(cycle[3]),
.I5(dout_1[15]),
.O(\top_left_0[15]_i_2_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFEF00000020))
\top_left_0[1]_i_1
(.I0(dout_0[1]),
.I1(cycle[2]),
.I2(\cycle_reg[1]_rep_n_0 ),
.I3(\cycle_reg[0]_rep_n_0 ),
.I4(cycle[3]),
.I5(dout_1[1]),
.O(\top_left_0[1]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFEF00000020))
\top_left_0[2]_i_1
(.I0(dout_0[2]),
.I1(cycle[2]),
.I2(\cycle_reg[1]_rep_n_0 ),
.I3(\cycle_reg[0]_rep_n_0 ),
.I4(cycle[3]),
.I5(dout_1[2]),
.O(\top_left_0[2]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFEF00000020))
\top_left_0[3]_i_1
(.I0(dout_0[3]),
.I1(cycle[2]),
.I2(\cycle_reg[1]_rep_n_0 ),
.I3(\cycle_reg[0]_rep_n_0 ),
.I4(cycle[3]),
.I5(dout_1[3]),
.O(\top_left_0[3]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFEF00000020))
\top_left_0[4]_i_1
(.I0(dout_0[4]),
.I1(cycle[2]),
.I2(\cycle_reg[1]_rep_n_0 ),
.I3(\cycle_reg[0]_rep_n_0 ),
.I4(cycle[3]),
.I5(dout_1[4]),
.O(\top_left_0[4]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFEF00000020))
\top_left_0[5]_i_1
(.I0(dout_0[5]),
.I1(cycle[2]),
.I2(\cycle_reg[1]_rep_n_0 ),
.I3(\cycle_reg[0]_rep_n_0 ),
.I4(cycle[3]),
.I5(dout_1[5]),
.O(\top_left_0[5]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFEF00000020))
\top_left_0[6]_i_1
(.I0(dout_0[6]),
.I1(cycle[2]),
.I2(\cycle_reg[1]_rep_n_0 ),
.I3(\cycle_reg[0]_rep_n_0 ),
.I4(cycle[3]),
.I5(dout_1[6]),
.O(\top_left_0[6]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFEF00000020))
\top_left_0[7]_i_1
(.I0(dout_0[7]),
.I1(cycle[2]),
.I2(\cycle_reg[1]_rep_n_0 ),
.I3(\cycle_reg[0]_rep_n_0 ),
.I4(cycle[3]),
.I5(dout_1[7]),
.O(\top_left_0[7]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFEF00000020))
\top_left_0[8]_i_1
(.I0(dout_0[8]),
.I1(cycle[2]),
.I2(\cycle_reg[1]_rep_n_0 ),
.I3(\cycle_reg[0]_rep_n_0 ),
.I4(cycle[3]),
.I5(dout_1[8]),
.O(\top_left_0[8]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFEF00000020))
\top_left_0[9]_i_1
(.I0(dout_0[9]),
.I1(cycle[2]),
.I2(\cycle_reg[1]_rep_n_0 ),
.I3(\cycle_reg[0]_rep_n_0 ),
.I4(cycle[3]),
.I5(dout_1[9]),
.O(\top_left_0[9]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\top_left_0_reg[0]
(.C(clk_x16),
.CE(top_left_0),
.D(\top_left_0[0]_i_1_n_0 ),
.Q(\top_left_0_reg_n_0_[0] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\top_left_0_reg[10]
(.C(clk_x16),
.CE(top_left_0),
.D(\top_left_0[10]_i_1_n_0 ),
.Q(\top_left_0_reg_n_0_[10] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\top_left_0_reg[11]
(.C(clk_x16),
.CE(top_left_0),
.D(\top_left_0[11]_i_1_n_0 ),
.Q(\top_left_0_reg_n_0_[11] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\top_left_0_reg[12]
(.C(clk_x16),
.CE(top_left_0),
.D(\top_left_0[12]_i_1_n_0 ),
.Q(\top_left_0_reg_n_0_[12] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\top_left_0_reg[13]
(.C(clk_x16),
.CE(top_left_0),
.D(\top_left_0[13]_i_1_n_0 ),
.Q(\top_left_0_reg_n_0_[13] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\top_left_0_reg[14]
(.C(clk_x16),
.CE(top_left_0),
.D(\top_left_0[14]_i_1_n_0 ),
.Q(\top_left_0_reg_n_0_[14] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\top_left_0_reg[15]
(.C(clk_x16),
.CE(top_left_0),
.D(\top_left_0[15]_i_2_n_0 ),
.Q(\top_left_0_reg_n_0_[15] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\top_left_0_reg[1]
(.C(clk_x16),
.CE(top_left_0),
.D(\top_left_0[1]_i_1_n_0 ),
.Q(\top_left_0_reg_n_0_[1] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\top_left_0_reg[2]
(.C(clk_x16),
.CE(top_left_0),
.D(\top_left_0[2]_i_1_n_0 ),
.Q(\top_left_0_reg_n_0_[2] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\top_left_0_reg[3]
(.C(clk_x16),
.CE(top_left_0),
.D(\top_left_0[3]_i_1_n_0 ),
.Q(\top_left_0_reg_n_0_[3] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\top_left_0_reg[4]
(.C(clk_x16),
.CE(top_left_0),
.D(\top_left_0[4]_i_1_n_0 ),
.Q(\top_left_0_reg_n_0_[4] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\top_left_0_reg[5]
(.C(clk_x16),
.CE(top_left_0),
.D(\top_left_0[5]_i_1_n_0 ),
.Q(\top_left_0_reg_n_0_[5] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\top_left_0_reg[6]
(.C(clk_x16),
.CE(top_left_0),
.D(\top_left_0[6]_i_1_n_0 ),
.Q(\top_left_0_reg_n_0_[6] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\top_left_0_reg[7]
(.C(clk_x16),
.CE(top_left_0),
.D(\top_left_0[7]_i_1_n_0 ),
.Q(\top_left_0_reg_n_0_[7] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\top_left_0_reg[8]
(.C(clk_x16),
.CE(top_left_0),
.D(\top_left_0[8]_i_1_n_0 ),
.Q(\top_left_0_reg_n_0_[8] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\top_left_0_reg[9]
(.C(clk_x16),
.CE(top_left_0),
.D(\top_left_0[9]_i_1_n_0 ),
.Q(\top_left_0_reg_n_0_[9] ),
.R(1'b0));
LUT6 #(
.INIT(64'hAAABAAAAAAA8AAAA))
\top_left_1[0]_i_1
(.I0(dout_1[0]),
.I1(\cycle_reg[0]_rep_n_0 ),
.I2(cycle[3]),
.I3(\cycle_reg[1]_rep__0_n_0 ),
.I4(cycle[2]),
.I5(\bottom_left_0_reg_n_0_[0] ),
.O(\top_left_1[0]_i_1_n_0 ));
LUT6 #(
.INIT(64'hAAABAAAAAAA8AAAA))
\top_left_1[10]_i_1
(.I0(dout_1[10]),
.I1(\cycle_reg[0]_rep_n_0 ),
.I2(cycle[3]),
.I3(\cycle_reg[1]_rep__0_n_0 ),
.I4(cycle[2]),
.I5(\bottom_left_0_reg_n_0_[10] ),
.O(\top_left_1[10]_i_1_n_0 ));
LUT6 #(
.INIT(64'hAAABAAAAAAA8AAAA))
\top_left_1[11]_i_1
(.I0(dout_1[11]),
.I1(\cycle_reg[0]_rep_n_0 ),
.I2(cycle[3]),
.I3(\cycle_reg[1]_rep__0_n_0 ),
.I4(cycle[2]),
.I5(\bottom_left_0_reg_n_0_[11] ),
.O(\top_left_1[11]_i_1_n_0 ));
LUT6 #(
.INIT(64'hAAABAAAAAAA8AAAA))
\top_left_1[12]_i_1
(.I0(dout_1[12]),
.I1(\cycle_reg[0]_rep_n_0 ),
.I2(cycle[3]),
.I3(\cycle_reg[1]_rep__0_n_0 ),
.I4(\cycle_reg[2]_rep_n_0 ),
.I5(\bottom_left_0_reg_n_0_[12] ),
.O(\top_left_1[12]_i_1_n_0 ));
LUT6 #(
.INIT(64'hAAABAAAAAAA8AAAA))
\top_left_1[13]_i_1
(.I0(dout_1[13]),
.I1(\cycle_reg[0]_rep_n_0 ),
.I2(cycle[3]),
.I3(\cycle_reg[1]_rep__0_n_0 ),
.I4(\cycle_reg[2]_rep_n_0 ),
.I5(\bottom_left_0_reg_n_0_[13] ),
.O(\top_left_1[13]_i_1_n_0 ));
LUT6 #(
.INIT(64'hAAABAAAAAAA8AAAA))
\top_left_1[14]_i_1
(.I0(dout_1[14]),
.I1(\cycle_reg[0]_rep_n_0 ),
.I2(cycle[3]),
.I3(\cycle_reg[1]_rep__0_n_0 ),
.I4(\cycle_reg[2]_rep_n_0 ),
.I5(\bottom_left_0_reg_n_0_[14] ),
.O(\top_left_1[14]_i_1_n_0 ));
LUT4 #(
.INIT(16'h0040))
\top_left_1[15]_i_1
(.I0(\cycle_reg[0]_rep_n_0 ),
.I1(active),
.I2(rst),
.I3(\cycle_reg[1]_rep__0_n_0 ),
.O(bottom_right_1));
LUT6 #(
.INIT(64'hAAABAAAAAAA8AAAA))
\top_left_1[15]_i_2
(.I0(dout_1[15]),
.I1(\cycle_reg[0]_rep_n_0 ),
.I2(cycle[3]),
.I3(\cycle_reg[1]_rep__0_n_0 ),
.I4(\cycle_reg[2]_rep_n_0 ),
.I5(\bottom_left_0_reg_n_0_[15] ),
.O(\top_left_1[15]_i_2_n_0 ));
LUT6 #(
.INIT(64'hAAABAAAAAAA8AAAA))
\top_left_1[1]_i_1
(.I0(dout_1[1]),
.I1(\cycle_reg[0]_rep_n_0 ),
.I2(cycle[3]),
.I3(\cycle_reg[1]_rep__0_n_0 ),
.I4(cycle[2]),
.I5(\bottom_left_0_reg_n_0_[1] ),
.O(\top_left_1[1]_i_1_n_0 ));
LUT6 #(
.INIT(64'hAAABAAAAAAA8AAAA))
\top_left_1[2]_i_1
(.I0(dout_1[2]),
.I1(\cycle_reg[0]_rep_n_0 ),
.I2(cycle[3]),
.I3(\cycle_reg[1]_rep__0_n_0 ),
.I4(cycle[2]),
.I5(\bottom_left_0_reg_n_0_[2] ),
.O(\top_left_1[2]_i_1_n_0 ));
LUT6 #(
.INIT(64'hAAABAAAAAAA8AAAA))
\top_left_1[3]_i_1
(.I0(dout_1[3]),
.I1(\cycle_reg[0]_rep_n_0 ),
.I2(cycle[3]),
.I3(\cycle_reg[1]_rep__0_n_0 ),
.I4(cycle[2]),
.I5(\bottom_left_0_reg_n_0_[3] ),
.O(\top_left_1[3]_i_1_n_0 ));
LUT6 #(
.INIT(64'hAAABAAAAAAA8AAAA))
\top_left_1[4]_i_1
(.I0(dout_1[4]),
.I1(\cycle_reg[0]_rep_n_0 ),
.I2(cycle[3]),
.I3(\cycle_reg[1]_rep__0_n_0 ),
.I4(cycle[2]),
.I5(\bottom_left_0_reg_n_0_[4] ),
.O(\top_left_1[4]_i_1_n_0 ));
LUT6 #(
.INIT(64'hAAABAAAAAAA8AAAA))
\top_left_1[5]_i_1
(.I0(dout_1[5]),
.I1(\cycle_reg[0]_rep_n_0 ),
.I2(cycle[3]),
.I3(\cycle_reg[1]_rep__0_n_0 ),
.I4(cycle[2]),
.I5(\bottom_left_0_reg_n_0_[5] ),
.O(\top_left_1[5]_i_1_n_0 ));
LUT6 #(
.INIT(64'hAAABAAAAAAA8AAAA))
\top_left_1[6]_i_1
(.I0(dout_1[6]),
.I1(\cycle_reg[0]_rep_n_0 ),
.I2(cycle[3]),
.I3(\cycle_reg[1]_rep__0_n_0 ),
.I4(cycle[2]),
.I5(\bottom_left_0_reg_n_0_[6] ),
.O(\top_left_1[6]_i_1_n_0 ));
LUT6 #(
.INIT(64'hAAABAAAAAAA8AAAA))
\top_left_1[7]_i_1
(.I0(dout_1[7]),
.I1(\cycle_reg[0]_rep_n_0 ),
.I2(cycle[3]),
.I3(\cycle_reg[1]_rep__0_n_0 ),
.I4(cycle[2]),
.I5(\bottom_left_0_reg_n_0_[7] ),
.O(\top_left_1[7]_i_1_n_0 ));
LUT6 #(
.INIT(64'hAAABAAAAAAA8AAAA))
\top_left_1[8]_i_1
(.I0(dout_1[8]),
.I1(\cycle_reg[0]_rep_n_0 ),
.I2(cycle[3]),
.I3(\cycle_reg[1]_rep__0_n_0 ),
.I4(cycle[2]),
.I5(\bottom_left_0_reg_n_0_[8] ),
.O(\top_left_1[8]_i_1_n_0 ));
LUT6 #(
.INIT(64'hAAABAAAAAAA8AAAA))
\top_left_1[9]_i_1
(.I0(dout_1[9]),
.I1(\cycle_reg[0]_rep_n_0 ),
.I2(cycle[3]),
.I3(\cycle_reg[1]_rep__0_n_0 ),
.I4(cycle[2]),
.I5(\bottom_left_0_reg_n_0_[9] ),
.O(\top_left_1[9]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\top_left_1_reg[0]
(.C(clk_x16),
.CE(bottom_right_1),
.D(\top_left_1[0]_i_1_n_0 ),
.Q(top_left_1[0]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\top_left_1_reg[10]
(.C(clk_x16),
.CE(bottom_right_1),
.D(\top_left_1[10]_i_1_n_0 ),
.Q(top_left_1[10]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\top_left_1_reg[11]
(.C(clk_x16),
.CE(bottom_right_1),
.D(\top_left_1[11]_i_1_n_0 ),
.Q(top_left_1[11]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\top_left_1_reg[12]
(.C(clk_x16),
.CE(bottom_right_1),
.D(\top_left_1[12]_i_1_n_0 ),
.Q(top_left_1[12]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\top_left_1_reg[13]
(.C(clk_x16),
.CE(bottom_right_1),
.D(\top_left_1[13]_i_1_n_0 ),
.Q(top_left_1[13]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\top_left_1_reg[14]
(.C(clk_x16),
.CE(bottom_right_1),
.D(\top_left_1[14]_i_1_n_0 ),
.Q(top_left_1[14]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\top_left_1_reg[15]
(.C(clk_x16),
.CE(bottom_right_1),
.D(\top_left_1[15]_i_2_n_0 ),
.Q(top_left_1[15]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\top_left_1_reg[1]
(.C(clk_x16),
.CE(bottom_right_1),
.D(\top_left_1[1]_i_1_n_0 ),
.Q(top_left_1[1]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\top_left_1_reg[2]
(.C(clk_x16),
.CE(bottom_right_1),
.D(\top_left_1[2]_i_1_n_0 ),
.Q(top_left_1[2]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\top_left_1_reg[3]
(.C(clk_x16),
.CE(bottom_right_1),
.D(\top_left_1[3]_i_1_n_0 ),
.Q(top_left_1[3]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\top_left_1_reg[4]
(.C(clk_x16),
.CE(bottom_right_1),
.D(\top_left_1[4]_i_1_n_0 ),
.Q(top_left_1[4]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\top_left_1_reg[5]
(.C(clk_x16),
.CE(bottom_right_1),
.D(\top_left_1[5]_i_1_n_0 ),
.Q(top_left_1[5]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\top_left_1_reg[6]
(.C(clk_x16),
.CE(bottom_right_1),
.D(\top_left_1[6]_i_1_n_0 ),
.Q(top_left_1[6]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\top_left_1_reg[7]
(.C(clk_x16),
.CE(bottom_right_1),
.D(\top_left_1[7]_i_1_n_0 ),
.Q(top_left_1[7]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\top_left_1_reg[8]
(.C(clk_x16),
.CE(bottom_right_1),
.D(\top_left_1[8]_i_1_n_0 ),
.Q(top_left_1[8]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\top_left_1_reg[9]
(.C(clk_x16),
.CE(bottom_right_1),
.D(\top_left_1[9]_i_1_n_0 ),
.Q(top_left_1[9]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\top_reg[0]
(.C(clk_x16),
.CE(x),
.D(\cache_reg[9]_2 [0]),
.Q(\top_reg_n_0_[0] ),
.R(top));
FDRE #(
.INIT(1'b0))
\top_reg[10]
(.C(clk_x16),
.CE(x),
.D(\cache_reg[9]_2 [10]),
.Q(\top_reg_n_0_[10] ),
.R(top));
FDRE #(
.INIT(1'b0))
\top_reg[11]
(.C(clk_x16),
.CE(x),
.D(\cache_reg[9]_2 [11]),
.Q(\top_reg_n_0_[11] ),
.R(top));
FDRE #(
.INIT(1'b0))
\top_reg[12]
(.C(clk_x16),
.CE(x),
.D(\cache_reg[9]_2 [12]),
.Q(\top_reg_n_0_[12] ),
.R(top));
FDRE #(
.INIT(1'b0))
\top_reg[13]
(.C(clk_x16),
.CE(x),
.D(\cache_reg[9]_2 [13]),
.Q(\top_reg_n_0_[13] ),
.R(top));
FDRE #(
.INIT(1'b0))
\top_reg[14]
(.C(clk_x16),
.CE(x),
.D(\cache_reg[9]_2 [14]),
.Q(\top_reg_n_0_[14] ),
.R(top));
FDRE #(
.INIT(1'b0))
\top_reg[15]
(.C(clk_x16),
.CE(x),
.D(\cache_reg[9]_2 [15]),
.Q(\top_reg_n_0_[15] ),
.R(top));
FDRE #(
.INIT(1'b0))
\top_reg[1]
(.C(clk_x16),
.CE(x),
.D(\cache_reg[9]_2 [1]),
.Q(\top_reg_n_0_[1] ),
.R(top));
FDRE #(
.INIT(1'b0))
\top_reg[2]
(.C(clk_x16),
.CE(x),
.D(\cache_reg[9]_2 [2]),
.Q(\top_reg_n_0_[2] ),
.R(top));
FDRE #(
.INIT(1'b0))
\top_reg[3]
(.C(clk_x16),
.CE(x),
.D(\cache_reg[9]_2 [3]),
.Q(\top_reg_n_0_[3] ),
.R(top));
FDRE #(
.INIT(1'b0))
\top_reg[4]
(.C(clk_x16),
.CE(x),
.D(\cache_reg[9]_2 [4]),
.Q(\top_reg_n_0_[4] ),
.R(top));
FDRE #(
.INIT(1'b0))
\top_reg[5]
(.C(clk_x16),
.CE(x),
.D(\cache_reg[9]_2 [5]),
.Q(\top_reg_n_0_[5] ),
.R(top));
FDRE #(
.INIT(1'b0))
\top_reg[6]
(.C(clk_x16),
.CE(x),
.D(\cache_reg[9]_2 [6]),
.Q(\top_reg_n_0_[6] ),
.R(top));
FDRE #(
.INIT(1'b0))
\top_reg[7]
(.C(clk_x16),
.CE(x),
.D(\cache_reg[9]_2 [7]),
.Q(\top_reg_n_0_[7] ),
.R(top));
FDRE #(
.INIT(1'b0))
\top_reg[8]
(.C(clk_x16),
.CE(x),
.D(\cache_reg[9]_2 [8]),
.Q(\top_reg_n_0_[8] ),
.R(top));
FDRE #(
.INIT(1'b0))
\top_reg[9]
(.C(clk_x16),
.CE(x),
.D(\cache_reg[9]_2 [9]),
.Q(\top_reg_n_0_[9] ),
.R(top));
LUT6 #(
.INIT(64'hFFFFFFEF00000020))
\top_right_0[0]_i_1
(.I0(top_left_1[0]),
.I1(\cycle_reg[1]_rep__0_n_0 ),
.I2(cycle[0]),
.I3(\cycle_reg[2]_rep_n_0 ),
.I4(cycle[3]),
.I5(dout_1[0]),
.O(\top_right_0[0]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFEF00000020))
\top_right_0[10]_i_1
(.I0(top_left_1[10]),
.I1(\cycle_reg[1]_rep__0_n_0 ),
.I2(cycle[0]),
.I3(\cycle_reg[2]_rep_n_0 ),
.I4(cycle[3]),
.I5(dout_1[10]),
.O(\top_right_0[10]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFEF00000020))
\top_right_0[11]_i_1
(.I0(top_left_1[11]),
.I1(\cycle_reg[1]_rep__0_n_0 ),
.I2(cycle[0]),
.I3(\cycle_reg[2]_rep_n_0 ),
.I4(cycle[3]),
.I5(dout_1[11]),
.O(\top_right_0[11]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFEF00000020))
\top_right_0[12]_i_1
(.I0(top_left_1[12]),
.I1(\cycle_reg[1]_rep__0_n_0 ),
.I2(cycle[0]),
.I3(\cycle_reg[2]_rep_n_0 ),
.I4(cycle[3]),
.I5(dout_1[12]),
.O(\top_right_0[12]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFEF00000020))
\top_right_0[13]_i_1
(.I0(top_left_1[13]),
.I1(\cycle_reg[1]_rep__0_n_0 ),
.I2(cycle[0]),
.I3(\cycle_reg[2]_rep_n_0 ),
.I4(cycle[3]),
.I5(dout_1[13]),
.O(\top_right_0[13]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFEF00000020))
\top_right_0[14]_i_1
(.I0(top_left_1[14]),
.I1(\cycle_reg[1]_rep__0_n_0 ),
.I2(cycle[0]),
.I3(\cycle_reg[2]_rep_n_0 ),
.I4(cycle[3]),
.I5(dout_1[14]),
.O(\top_right_0[14]_i_1_n_0 ));
LUT6 #(
.INIT(64'h0880000080080800))
\top_right_0[15]_i_1
(.I0(rst),
.I1(active),
.I2(cycle[3]),
.I3(cycle[0]),
.I4(\cycle_reg[1]_rep__0_n_0 ),
.I5(\cycle_reg[2]_rep_n_0 ),
.O(top_right_0));
LUT6 #(
.INIT(64'hFFFFFFEF00000020))
\top_right_0[15]_i_2
(.I0(top_left_1[15]),
.I1(\cycle_reg[1]_rep__0_n_0 ),
.I2(cycle[0]),
.I3(\cycle_reg[2]_rep_n_0 ),
.I4(cycle[3]),
.I5(dout_1[15]),
.O(\top_right_0[15]_i_2_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFEF00000020))
\top_right_0[1]_i_1
(.I0(top_left_1[1]),
.I1(\cycle_reg[1]_rep__0_n_0 ),
.I2(cycle[0]),
.I3(\cycle_reg[2]_rep_n_0 ),
.I4(cycle[3]),
.I5(dout_1[1]),
.O(\top_right_0[1]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFEF00000020))
\top_right_0[2]_i_1
(.I0(top_left_1[2]),
.I1(\cycle_reg[1]_rep__0_n_0 ),
.I2(cycle[0]),
.I3(\cycle_reg[2]_rep_n_0 ),
.I4(cycle[3]),
.I5(dout_1[2]),
.O(\top_right_0[2]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFEF00000020))
\top_right_0[3]_i_1
(.I0(top_left_1[3]),
.I1(\cycle_reg[1]_rep__0_n_0 ),
.I2(cycle[0]),
.I3(\cycle_reg[2]_rep_n_0 ),
.I4(cycle[3]),
.I5(dout_1[3]),
.O(\top_right_0[3]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFEF00000020))
\top_right_0[4]_i_1
(.I0(top_left_1[4]),
.I1(\cycle_reg[1]_rep__0_n_0 ),
.I2(cycle[0]),
.I3(\cycle_reg[2]_rep_n_0 ),
.I4(cycle[3]),
.I5(dout_1[4]),
.O(\top_right_0[4]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFEF00000020))
\top_right_0[5]_i_1
(.I0(top_left_1[5]),
.I1(\cycle_reg[1]_rep__0_n_0 ),
.I2(cycle[0]),
.I3(\cycle_reg[2]_rep_n_0 ),
.I4(cycle[3]),
.I5(dout_1[5]),
.O(\top_right_0[5]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFEF00000020))
\top_right_0[6]_i_1
(.I0(top_left_1[6]),
.I1(\cycle_reg[1]_rep__0_n_0 ),
.I2(cycle[0]),
.I3(\cycle_reg[2]_rep_n_0 ),
.I4(cycle[3]),
.I5(dout_1[6]),
.O(\top_right_0[6]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFEF00000020))
\top_right_0[7]_i_1
(.I0(top_left_1[7]),
.I1(\cycle_reg[1]_rep__0_n_0 ),
.I2(cycle[0]),
.I3(\cycle_reg[2]_rep_n_0 ),
.I4(cycle[3]),
.I5(dout_1[7]),
.O(\top_right_0[7]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFEF00000020))
\top_right_0[8]_i_1
(.I0(top_left_1[8]),
.I1(\cycle_reg[1]_rep__0_n_0 ),
.I2(cycle[0]),
.I3(\cycle_reg[2]_rep_n_0 ),
.I4(cycle[3]),
.I5(dout_1[8]),
.O(\top_right_0[8]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFEF00000020))
\top_right_0[9]_i_1
(.I0(top_left_1[9]),
.I1(\cycle_reg[1]_rep__0_n_0 ),
.I2(cycle[0]),
.I3(\cycle_reg[2]_rep_n_0 ),
.I4(cycle[3]),
.I5(dout_1[9]),
.O(\top_right_0[9]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\top_right_0_reg[0]
(.C(clk_x16),
.CE(top_right_0),
.D(\top_right_0[0]_i_1_n_0 ),
.Q(\top_right_0_reg_n_0_[0] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\top_right_0_reg[10]
(.C(clk_x16),
.CE(top_right_0),
.D(\top_right_0[10]_i_1_n_0 ),
.Q(\top_right_0_reg_n_0_[10] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\top_right_0_reg[11]
(.C(clk_x16),
.CE(top_right_0),
.D(\top_right_0[11]_i_1_n_0 ),
.Q(\top_right_0_reg_n_0_[11] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\top_right_0_reg[12]
(.C(clk_x16),
.CE(top_right_0),
.D(\top_right_0[12]_i_1_n_0 ),
.Q(\top_right_0_reg_n_0_[12] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\top_right_0_reg[13]
(.C(clk_x16),
.CE(top_right_0),
.D(\top_right_0[13]_i_1_n_0 ),
.Q(\top_right_0_reg_n_0_[13] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\top_right_0_reg[14]
(.C(clk_x16),
.CE(top_right_0),
.D(\top_right_0[14]_i_1_n_0 ),
.Q(\top_right_0_reg_n_0_[14] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\top_right_0_reg[15]
(.C(clk_x16),
.CE(top_right_0),
.D(\top_right_0[15]_i_2_n_0 ),
.Q(\top_right_0_reg_n_0_[15] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\top_right_0_reg[1]
(.C(clk_x16),
.CE(top_right_0),
.D(\top_right_0[1]_i_1_n_0 ),
.Q(\top_right_0_reg_n_0_[1] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\top_right_0_reg[2]
(.C(clk_x16),
.CE(top_right_0),
.D(\top_right_0[2]_i_1_n_0 ),
.Q(\top_right_0_reg_n_0_[2] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\top_right_0_reg[3]
(.C(clk_x16),
.CE(top_right_0),
.D(\top_right_0[3]_i_1_n_0 ),
.Q(\top_right_0_reg_n_0_[3] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\top_right_0_reg[4]
(.C(clk_x16),
.CE(top_right_0),
.D(\top_right_0[4]_i_1_n_0 ),
.Q(\top_right_0_reg_n_0_[4] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\top_right_0_reg[5]
(.C(clk_x16),
.CE(top_right_0),
.D(\top_right_0[5]_i_1_n_0 ),
.Q(\top_right_0_reg_n_0_[5] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\top_right_0_reg[6]
(.C(clk_x16),
.CE(top_right_0),
.D(\top_right_0[6]_i_1_n_0 ),
.Q(\top_right_0_reg_n_0_[6] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\top_right_0_reg[7]
(.C(clk_x16),
.CE(top_right_0),
.D(\top_right_0[7]_i_1_n_0 ),
.Q(\top_right_0_reg_n_0_[7] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\top_right_0_reg[8]
(.C(clk_x16),
.CE(top_right_0),
.D(\top_right_0[8]_i_1_n_0 ),
.Q(\top_right_0_reg_n_0_[8] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\top_right_0_reg[9]
(.C(clk_x16),
.CE(top_right_0),
.D(\top_right_0[9]_i_1_n_0 ),
.Q(\top_right_0_reg_n_0_[9] ),
.R(1'b0));
LUT5 #(
.INIT(32'hB8BBB888))
\top_right_1[0]_i_1
(.I0(dout_1[0]),
.I1(\top_right_1[15]_i_2_n_0 ),
.I2(\bottom_right_0_reg_n_0_[0] ),
.I3(\cycle_reg[2]_rep_n_0 ),
.I4(\top_left_0_reg_n_0_[0] ),
.O(\top_right_1[0]_i_1_n_0 ));
LUT5 #(
.INIT(32'hB8BBB888))
\top_right_1[10]_i_1
(.I0(dout_1[10]),
.I1(\top_right_1[15]_i_2_n_0 ),
.I2(\bottom_right_0_reg_n_0_[10] ),
.I3(\cycle_reg[2]_rep_n_0 ),
.I4(\top_left_0_reg_n_0_[10] ),
.O(\top_right_1[10]_i_1_n_0 ));
LUT5 #(
.INIT(32'hB8BBB888))
\top_right_1[11]_i_1
(.I0(dout_1[11]),
.I1(\top_right_1[15]_i_2_n_0 ),
.I2(\bottom_right_0_reg_n_0_[11] ),
.I3(\cycle_reg[2]_rep_n_0 ),
.I4(\top_left_0_reg_n_0_[11] ),
.O(\top_right_1[11]_i_1_n_0 ));
LUT5 #(
.INIT(32'hB8BBB888))
\top_right_1[12]_i_1
(.I0(dout_1[12]),
.I1(\top_right_1[15]_i_2_n_0 ),
.I2(\bottom_right_0_reg_n_0_[12] ),
.I3(\cycle_reg[2]_rep_n_0 ),
.I4(\top_left_0_reg_n_0_[12] ),
.O(\top_right_1[12]_i_1_n_0 ));
LUT5 #(
.INIT(32'hB8BBB888))
\top_right_1[13]_i_1
(.I0(dout_1[13]),
.I1(\top_right_1[15]_i_2_n_0 ),
.I2(\bottom_right_0_reg_n_0_[13] ),
.I3(\cycle_reg[2]_rep_n_0 ),
.I4(\top_left_0_reg_n_0_[13] ),
.O(\top_right_1[13]_i_1_n_0 ));
LUT5 #(
.INIT(32'hB8BBB888))
\top_right_1[14]_i_1
(.I0(dout_1[14]),
.I1(\top_right_1[15]_i_2_n_0 ),
.I2(\bottom_right_0_reg_n_0_[14] ),
.I3(\cycle_reg[2]_rep_n_0 ),
.I4(\top_left_0_reg_n_0_[14] ),
.O(\top_right_1[14]_i_1_n_0 ));
LUT5 #(
.INIT(32'hB8BBB888))
\top_right_1[15]_i_1
(.I0(dout_1[15]),
.I1(\top_right_1[15]_i_2_n_0 ),
.I2(\bottom_right_0_reg_n_0_[15] ),
.I3(\cycle_reg[2]_rep_n_0 ),
.I4(\top_left_0_reg_n_0_[15] ),
.O(\top_right_1[15]_i_1_n_0 ));
LUT3 #(
.INIT(8'hFE))
\top_right_1[15]_i_2
(.I0(cycle[3]),
.I1(cycle[0]),
.I2(\cycle_reg[1]_rep__0_n_0 ),
.O(\top_right_1[15]_i_2_n_0 ));
LUT5 #(
.INIT(32'hB8BBB888))
\top_right_1[1]_i_1
(.I0(dout_1[1]),
.I1(\top_right_1[15]_i_2_n_0 ),
.I2(\bottom_right_0_reg_n_0_[1] ),
.I3(\cycle_reg[2]_rep_n_0 ),
.I4(\top_left_0_reg_n_0_[1] ),
.O(\top_right_1[1]_i_1_n_0 ));
LUT5 #(
.INIT(32'hB8BBB888))
\top_right_1[2]_i_1
(.I0(dout_1[2]),
.I1(\top_right_1[15]_i_2_n_0 ),
.I2(\bottom_right_0_reg_n_0_[2] ),
.I3(\cycle_reg[2]_rep_n_0 ),
.I4(\top_left_0_reg_n_0_[2] ),
.O(\top_right_1[2]_i_1_n_0 ));
LUT5 #(
.INIT(32'hB8BBB888))
\top_right_1[3]_i_1
(.I0(dout_1[3]),
.I1(\top_right_1[15]_i_2_n_0 ),
.I2(\bottom_right_0_reg_n_0_[3] ),
.I3(\cycle_reg[2]_rep_n_0 ),
.I4(\top_left_0_reg_n_0_[3] ),
.O(\top_right_1[3]_i_1_n_0 ));
LUT5 #(
.INIT(32'hB8BBB888))
\top_right_1[4]_i_1
(.I0(dout_1[4]),
.I1(\top_right_1[15]_i_2_n_0 ),
.I2(\bottom_right_0_reg_n_0_[4] ),
.I3(\cycle_reg[2]_rep_n_0 ),
.I4(\top_left_0_reg_n_0_[4] ),
.O(\top_right_1[4]_i_1_n_0 ));
LUT5 #(
.INIT(32'hB8BBB888))
\top_right_1[5]_i_1
(.I0(dout_1[5]),
.I1(\top_right_1[15]_i_2_n_0 ),
.I2(\bottom_right_0_reg_n_0_[5] ),
.I3(\cycle_reg[2]_rep_n_0 ),
.I4(\top_left_0_reg_n_0_[5] ),
.O(\top_right_1[5]_i_1_n_0 ));
LUT5 #(
.INIT(32'hB8BBB888))
\top_right_1[6]_i_1
(.I0(dout_1[6]),
.I1(\top_right_1[15]_i_2_n_0 ),
.I2(\bottom_right_0_reg_n_0_[6] ),
.I3(\cycle_reg[2]_rep_n_0 ),
.I4(\top_left_0_reg_n_0_[6] ),
.O(\top_right_1[6]_i_1_n_0 ));
LUT5 #(
.INIT(32'hB8BBB888))
\top_right_1[7]_i_1
(.I0(dout_1[7]),
.I1(\top_right_1[15]_i_2_n_0 ),
.I2(\bottom_right_0_reg_n_0_[7] ),
.I3(\cycle_reg[2]_rep_n_0 ),
.I4(\top_left_0_reg_n_0_[7] ),
.O(\top_right_1[7]_i_1_n_0 ));
LUT5 #(
.INIT(32'hB8BBB888))
\top_right_1[8]_i_1
(.I0(dout_1[8]),
.I1(\top_right_1[15]_i_2_n_0 ),
.I2(\bottom_right_0_reg_n_0_[8] ),
.I3(\cycle_reg[2]_rep_n_0 ),
.I4(\top_left_0_reg_n_0_[8] ),
.O(\top_right_1[8]_i_1_n_0 ));
LUT5 #(
.INIT(32'hB8BBB888))
\top_right_1[9]_i_1
(.I0(dout_1[9]),
.I1(\top_right_1[15]_i_2_n_0 ),
.I2(\bottom_right_0_reg_n_0_[9] ),
.I3(\cycle_reg[2]_rep_n_0 ),
.I4(\top_left_0_reg_n_0_[9] ),
.O(\top_right_1[9]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\top_right_1_reg[0]
(.C(clk_x16),
.CE(top_right_1),
.D(\top_right_1[0]_i_1_n_0 ),
.Q(\top_right_1_reg_n_0_[0] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\top_right_1_reg[10]
(.C(clk_x16),
.CE(top_right_1),
.D(\top_right_1[10]_i_1_n_0 ),
.Q(\top_right_1_reg_n_0_[10] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\top_right_1_reg[11]
(.C(clk_x16),
.CE(top_right_1),
.D(\top_right_1[11]_i_1_n_0 ),
.Q(\top_right_1_reg_n_0_[11] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\top_right_1_reg[12]
(.C(clk_x16),
.CE(top_right_1),
.D(\top_right_1[12]_i_1_n_0 ),
.Q(\top_right_1_reg_n_0_[12] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\top_right_1_reg[13]
(.C(clk_x16),
.CE(top_right_1),
.D(\top_right_1[13]_i_1_n_0 ),
.Q(\top_right_1_reg_n_0_[13] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\top_right_1_reg[14]
(.C(clk_x16),
.CE(top_right_1),
.D(\top_right_1[14]_i_1_n_0 ),
.Q(\top_right_1_reg_n_0_[14] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\top_right_1_reg[15]
(.C(clk_x16),
.CE(top_right_1),
.D(\top_right_1[15]_i_1_n_0 ),
.Q(\top_right_1_reg_n_0_[15] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\top_right_1_reg[1]
(.C(clk_x16),
.CE(top_right_1),
.D(\top_right_1[1]_i_1_n_0 ),
.Q(\top_right_1_reg_n_0_[1] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\top_right_1_reg[2]
(.C(clk_x16),
.CE(top_right_1),
.D(\top_right_1[2]_i_1_n_0 ),
.Q(\top_right_1_reg_n_0_[2] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\top_right_1_reg[3]
(.C(clk_x16),
.CE(top_right_1),
.D(\top_right_1[3]_i_1_n_0 ),
.Q(\top_right_1_reg_n_0_[3] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\top_right_1_reg[4]
(.C(clk_x16),
.CE(top_right_1),
.D(\top_right_1[4]_i_1_n_0 ),
.Q(\top_right_1_reg_n_0_[4] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\top_right_1_reg[5]
(.C(clk_x16),
.CE(top_right_1),
.D(\top_right_1[5]_i_1_n_0 ),
.Q(\top_right_1_reg_n_0_[5] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\top_right_1_reg[6]
(.C(clk_x16),
.CE(top_right_1),
.D(\top_right_1[6]_i_1_n_0 ),
.Q(\top_right_1_reg_n_0_[6] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\top_right_1_reg[7]
(.C(clk_x16),
.CE(top_right_1),
.D(\top_right_1[7]_i_1_n_0 ),
.Q(\top_right_1_reg_n_0_[7] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\top_right_1_reg[8]
(.C(clk_x16),
.CE(top_right_1),
.D(\top_right_1[8]_i_1_n_0 ),
.Q(\top_right_1_reg_n_0_[8] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\top_right_1_reg[9]
(.C(clk_x16),
.CE(top_right_1),
.D(\top_right_1[9]_i_1_n_0 ),
.Q(\top_right_1_reg_n_0_[9] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\value_reg[0]
(.C(clk_x16),
.CE(x),
.D(g_in[0]),
.Q(\value_reg_n_0_[0] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\value_reg[1]
(.C(clk_x16),
.CE(x),
.D(g_in[1]),
.Q(\value_reg_n_0_[1] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\value_reg[2]
(.C(clk_x16),
.CE(x),
.D(g_in[2]),
.Q(\value_reg_n_0_[2] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\value_reg[3]
(.C(clk_x16),
.CE(x),
.D(g_in[3]),
.Q(\value_reg_n_0_[3] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\value_reg[4]
(.C(clk_x16),
.CE(x),
.D(g_in[4]),
.Q(\value_reg_n_0_[4] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\value_reg[5]
(.C(clk_x16),
.CE(x),
.D(g_in[5]),
.Q(\value_reg_n_0_[5] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\value_reg[6]
(.C(clk_x16),
.CE(x),
.D(g_in[6]),
.Q(\value_reg_n_0_[6] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\value_reg[7]
(.C(clk_x16),
.CE(x),
.D(g_in[7]),
.Q(\value_reg_n_0_[7] ),
.R(1'b0));
LUT6 #(
.INIT(64'hAAAAEAAAAAA2AAAA))
wen_i_1
(.I0(wen_reg_n_0),
.I1(wen_i_2_n_0),
.I2(\cycle_reg[0]_rep_n_0 ),
.I3(\cycle_reg[1]_rep_n_0 ),
.I4(cycle[3]),
.I5(cycle[2]),
.O(wen_i_1_n_0));
LUT2 #(
.INIT(4'h8))
wen_i_2
(.I0(active),
.I1(rst),
.O(wen_i_2_n_0));
FDRE #(
.INIT(1'b0))
wen_reg
(.C(clk_x16),
.CE(1'b1),
.D(wen_i_1_n_0),
.Q(wen_reg_n_0),
.R(1'b0));
LUT6 #(
.INIT(64'h3B01FFC53A00FEC4))
\x0[0]_i_2
(.I0(\cycle_reg[2]_rep_n_0 ),
.I1(cycle[0]),
.I2(\cycle_reg[1]_rep__0_n_0 ),
.I3(data2[0]),
.I4(\x_reg_n_0_[0] ),
.I5(\plusOp_inferred__0/i__carry_n_7 ),
.O(\x0[0]_i_2_n_0 ));
LUT5 #(
.INIT(32'hFFFE0002))
\x0[0]_i_3
(.I0(data2[0]),
.I1(cycle[0]),
.I2(\cycle_reg[2]_rep_n_0 ),
.I3(\cycle_reg[1]_rep__0_n_0 ),
.I4(\plusOp_inferred__0/i__carry_n_7 ),
.O(\x0[0]_i_3_n_0 ));
LUT6 #(
.INIT(64'hCCEECCEEEEEECCFC))
\x0[1]_i_2
(.I0(data2[1]),
.I1(\x0[1]_i_4_n_0 ),
.I2(\plusOp_inferred__0/i__carry_n_6 ),
.I3(cycle[0]),
.I4(\cycle_reg[2]_rep_n_0 ),
.I5(\cycle_reg[1]_rep__0_n_0 ),
.O(\x0[1]_i_2_n_0 ));
LUT5 #(
.INIT(32'hFFFE0002))
\x0[1]_i_3
(.I0(data2[1]),
.I1(cycle[0]),
.I2(\cycle_reg[2]_rep_n_0 ),
.I3(\cycle_reg[1]_rep__0_n_0 ),
.I4(\plusOp_inferred__0/i__carry_n_6 ),
.O(\x0[1]_i_3_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair6" *)
LUT5 #(
.INIT(32'h60600060))
\x0[1]_i_4
(.I0(\x_reg_n_0_[1] ),
.I1(\x_reg_n_0_[0] ),
.I2(cycle[0]),
.I3(\cycle_reg[2]_rep_n_0 ),
.I4(\cycle_reg[1]_rep__0_n_0 ),
.O(\x0[1]_i_4_n_0 ));
LUT6 #(
.INIT(64'hFBBBFBBBFFBBBBBB))
\x0[2]_i_1
(.I0(\x0[2]_i_2_n_0 ),
.I1(\x0[2]_i_3_n_0 ),
.I2(data2[2]),
.I3(cycle[3]),
.I4(\plusOp_inferred__0/i__carry_n_5 ),
.I5(\x1[5]_i_3_n_0 ),
.O(\x0[2]_i_1_n_0 ));
LUT6 #(
.INIT(64'h88AA22A0880022A0))
\x0[2]_i_2
(.I0(\x0[7]_i_4_n_0 ),
.I1(\x0[2]_i_4_n_0 ),
.I2(\plusOp_inferred__0/i__carry_n_5 ),
.I3(cycle[0]),
.I4(\cycle_reg[1]_rep__0_n_0 ),
.I5(data2[2]),
.O(\x0[2]_i_2_n_0 ));
LUT6 #(
.INIT(64'h3FF3F3F377777777))
\x0[2]_i_3
(.I0(data2[2]),
.I1(\x0[2]_i_5_n_0 ),
.I2(\x_reg_n_0_[2] ),
.I3(\x_reg_n_0_[1] ),
.I4(\x_reg_n_0_[0] ),
.I5(\x1[6]_i_8_n_0 ),
.O(\x0[2]_i_3_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair55" *)
LUT3 #(
.INIT(8'h6A))
\x0[2]_i_4
(.I0(\x_reg_n_0_[2] ),
.I1(\x_reg_n_0_[1] ),
.I2(\x_reg_n_0_[0] ),
.O(\x0[2]_i_4_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT2 #(
.INIT(4'h2))
\x0[2]_i_5
(.I0(\cycle_reg[2]_rep_n_0 ),
.I1(cycle[3]),
.O(\x0[2]_i_5_n_0 ));
LUT5 #(
.INIT(32'hFFF100F1))
\x0[3]_i_1
(.I0(\x0[3]_i_2_n_0 ),
.I1(\cycle_reg[2]_rep_n_0 ),
.I2(\x0[3]_i_3_n_0 ),
.I3(cycle[3]),
.I4(\x0[3]_i_4_n_0 ),
.O(\x0[3]_i_1_n_0 ));
LUT6 #(
.INIT(64'h660FFF00660FFFFF))
\x0[3]_i_2
(.I0(\x_reg_n_0_[3] ),
.I1(\x0[3]_i_5_n_0 ),
.I2(data2[3]),
.I3(cycle[0]),
.I4(\cycle_reg[1]_rep__0_n_0 ),
.I5(\plusOp_inferred__0/i__carry_n_4 ),
.O(\x0[3]_i_2_n_0 ));
LUT6 #(
.INIT(64'h90F0F9F090000900))
\x0[3]_i_3
(.I0(\x_reg_n_0_[3] ),
.I1(\x0[3]_i_6_n_0 ),
.I2(\cycle_reg[2]_rep_n_0 ),
.I3(cycle[0]),
.I4(\cycle_reg[1]_rep__0_n_0 ),
.I5(data2[3]),
.O(\x0[3]_i_3_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair9" *)
LUT5 #(
.INIT(32'hFFFE0002))
\x0[3]_i_4
(.I0(data2[3]),
.I1(cycle[0]),
.I2(\cycle_reg[2]_rep_n_0 ),
.I3(\cycle_reg[1]_rep__0_n_0 ),
.I4(\plusOp_inferred__0/i__carry_n_4 ),
.O(\x0[3]_i_4_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair55" *)
LUT3 #(
.INIT(8'h7F))
\x0[3]_i_5
(.I0(\x_reg_n_0_[2] ),
.I1(\x_reg_n_0_[1] ),
.I2(\x_reg_n_0_[0] ),
.O(\x0[3]_i_5_n_0 ));
LUT3 #(
.INIT(8'hEA))
\x0[3]_i_6
(.I0(\x_reg_n_0_[2] ),
.I1(\x_reg_n_0_[1] ),
.I2(\x_reg_n_0_[0] ),
.O(\x0[3]_i_6_n_0 ));
LUT6 #(
.INIT(64'hFCDDFCDDFFDDCCDD))
\x0[4]_i_1
(.I0(\x0[4]_i_2_n_0 ),
.I1(\x0[4]_i_3_n_0 ),
.I2(data2[4]),
.I3(cycle[3]),
.I4(\plusOp_inferred__0/i__carry__0_n_7 ),
.I5(\x1[5]_i_3_n_0 ),
.O(\x0[4]_i_1_n_0 ));
LUT6 #(
.INIT(64'h3C555555FFFF3CFF))
\x0[4]_i_2
(.I0(data2[4]),
.I1(\x_reg_n_0_[4] ),
.I2(\x0[4]_i_4_n_0 ),
.I3(cycle[0]),
.I4(\cycle_reg[1]_rep__0_n_0 ),
.I5(\cycle_reg[2]_rep_n_0 ),
.O(\x0[4]_i_2_n_0 ));
LUT6 #(
.INIT(64'h008A0080A08AA080))
\x0[4]_i_3
(.I0(\x0[7]_i_4_n_0 ),
.I1(data2[4]),
.I2(\cycle_reg[1]_rep__0_n_0 ),
.I3(cycle[0]),
.I4(\plusOp_inferred__0/i__carry__0_n_7 ),
.I5(\x0[4]_i_5_n_0 ),
.O(\x0[4]_i_3_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair16" *)
LUT4 #(
.INIT(16'hFFEA))
\x0[4]_i_4
(.I0(\x_reg_n_0_[3] ),
.I1(\x_reg_n_0_[0] ),
.I2(\x_reg_n_0_[1] ),
.I3(\x_reg_n_0_[2] ),
.O(\x0[4]_i_4_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair4" *)
LUT5 #(
.INIT(32'h95555555))
\x0[4]_i_5
(.I0(\x_reg_n_0_[4] ),
.I1(\x_reg_n_0_[3] ),
.I2(\x_reg_n_0_[2] ),
.I3(\x_reg_n_0_[1] ),
.I4(\x_reg_n_0_[0] ),
.O(\x0[4]_i_5_n_0 ));
LUT6 #(
.INIT(64'hFCDDFCDDFFDDCCDD))
\x0[5]_i_1
(.I0(\x0[5]_i_2_n_0 ),
.I1(\x0[5]_i_3_n_0 ),
.I2(data2[5]),
.I3(cycle[3]),
.I4(\plusOp_inferred__0/i__carry__0_n_6 ),
.I5(\x1[5]_i_3_n_0 ),
.O(\x0[5]_i_1_n_0 ));
LUT6 #(
.INIT(64'h3C555555FFFF3CFF))
\x0[5]_i_2
(.I0(data2[5]),
.I1(\x_reg_n_0_[5] ),
.I2(\x0[8]_i_7_n_0 ),
.I3(cycle[0]),
.I4(\cycle_reg[1]_rep__0_n_0 ),
.I5(\cycle_reg[2]_rep_n_0 ),
.O(\x0[5]_i_2_n_0 ));
LUT6 #(
.INIT(64'h00A80008AAAAAAAA))
\x0[5]_i_3
(.I0(\x0[7]_i_4_n_0 ),
.I1(\plusOp_inferred__0/i__carry__0_n_6 ),
.I2(\cycle_reg[1]_rep__0_n_0 ),
.I3(cycle[0]),
.I4(data2[5]),
.I5(\x0[5]_i_4_n_0 ),
.O(\x0[5]_i_3_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair14" *)
LUT5 #(
.INIT(32'h2DFFFFFF))
\x0[5]_i_4
(.I0(\x_reg_n_0_[4] ),
.I1(\x0[5]_i_5_n_0 ),
.I2(\x_reg_n_0_[5] ),
.I3(\cycle_reg[1]_rep__0_n_0 ),
.I4(cycle[0]),
.O(\x0[5]_i_4_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair16" *)
LUT4 #(
.INIT(16'h7FFF))
\x0[5]_i_5
(.I0(\x_reg_n_0_[0] ),
.I1(\x_reg_n_0_[1] ),
.I2(\x_reg_n_0_[2] ),
.I3(\x_reg_n_0_[3] ),
.O(\x0[5]_i_5_n_0 ));
LUT5 #(
.INIT(32'hFFFF0507))
\x0[6]_i_1
(.I0(\x0[6]_i_2_n_0 ),
.I1(\cycle_reg[2]_rep_n_0 ),
.I2(cycle[3]),
.I3(\x0[6]_i_3_n_0 ),
.I4(\x0[6]_i_4_n_0 ),
.O(\x0[6]_i_1_n_0 ));
LUT6 #(
.INIT(64'h0707077077777777))
\x0[6]_i_2
(.I0(\x1[9]_i_7_n_0 ),
.I1(data2[6]),
.I2(\x_reg_n_0_[6] ),
.I3(\x0[8]_i_7_n_0 ),
.I4(\x_reg_n_0_[5] ),
.I5(\x0[8]_i_5_n_0 ),
.O(\x0[6]_i_2_n_0 ));
LUT6 #(
.INIT(64'h6600FF0F66FFFF0F))
\x0[6]_i_3
(.I0(\x_reg_n_0_[6] ),
.I1(\x0[6]_i_5_n_0 ),
.I2(\plusOp_inferred__0/i__carry__0_n_5 ),
.I3(cycle[0]),
.I4(\cycle_reg[1]_rep__0_n_0 ),
.I5(data2[6]),
.O(\x0[6]_i_3_n_0 ));
LUT6 #(
.INIT(64'hC0C0C0C0C0C0C088))
\x0[6]_i_4
(.I0(data2[6]),
.I1(cycle[3]),
.I2(\plusOp_inferred__0/i__carry__0_n_5 ),
.I3(cycle[0]),
.I4(\cycle_reg[2]_rep_n_0 ),
.I5(\cycle_reg[1]_rep__0_n_0 ),
.O(\x0[6]_i_4_n_0 ));
LUT6 #(
.INIT(64'h7FFFFFFFFFFFFFFF))
\x0[6]_i_5
(.I0(\x_reg_n_0_[4] ),
.I1(\x_reg_n_0_[0] ),
.I2(\x_reg_n_0_[1] ),
.I3(\x_reg_n_0_[2] ),
.I4(\x_reg_n_0_[3] ),
.I5(\x_reg_n_0_[5] ),
.O(\x0[6]_i_5_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFFFF020000))
\x0[7]_i_1
(.I0(cycle[0]),
.I1(\cycle_reg[1]_rep__0_n_0 ),
.I2(\x0[7]_i_2_n_0 ),
.I3(\x0[7]_i_3_n_0 ),
.I4(\x0[7]_i_4_n_0 ),
.I5(\x0[7]_i_5_n_0 ),
.O(\x0[7]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT4 #(
.INIT(16'h5556))
\x0[7]_i_2
(.I0(\x_reg_n_0_[7] ),
.I1(\x0[8]_i_7_n_0 ),
.I2(\x_reg_n_0_[5] ),
.I3(\x_reg_n_0_[6] ),
.O(\x0[7]_i_2_n_0 ));
LUT6 #(
.INIT(64'h99F000FF99F00000))
\x0[7]_i_3
(.I0(\x_reg_n_0_[7] ),
.I1(\x0[7]_i_6_n_0 ),
.I2(data2[7]),
.I3(cycle[0]),
.I4(\cycle_reg[1]_rep__0_n_0 ),
.I5(\plusOp_inferred__0/i__carry__0_n_4 ),
.O(\x0[7]_i_3_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair8" *)
LUT2 #(
.INIT(4'h1))
\x0[7]_i_4
(.I0(cycle[3]),
.I1(\cycle_reg[2]_rep_n_0 ),
.O(\x0[7]_i_4_n_0 ));
LUT6 #(
.INIT(64'hFF0FEECCF000EECC))
\x0[7]_i_5
(.I0(\x1[9]_i_7_n_0 ),
.I1(\x0[7]_i_7_n_0 ),
.I2(\x1[5]_i_3_n_0 ),
.I3(data2[7]),
.I4(cycle[3]),
.I5(\plusOp_inferred__0/i__carry__0_n_4 ),
.O(\x0[7]_i_5_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair17" *)
LUT2 #(
.INIT(4'hB))
\x0[7]_i_6
(.I0(\x0[6]_i_5_n_0 ),
.I1(\x_reg_n_0_[6] ),
.O(\x0[7]_i_6_n_0 ));
LUT6 #(
.INIT(64'h8888888000000008))
\x0[7]_i_7
(.I0(\cycle_reg[2]_rep_n_0 ),
.I1(\x1[6]_i_8_n_0 ),
.I2(\x_reg_n_0_[6] ),
.I3(\x_reg_n_0_[5] ),
.I4(\x0[8]_i_7_n_0 ),
.I5(\x_reg_n_0_[7] ),
.O(\x0[7]_i_7_n_0 ));
LUT6 #(
.INIT(64'hF0F0F0F0FFF1F1F1))
\x0[8]_i_1
(.I0(\x0[8]_i_2_n_0 ),
.I1(\cycle_reg[2]_rep_n_0 ),
.I2(\x0[8]_i_3_n_0 ),
.I3(\x0[8]_i_4_n_0 ),
.I4(\x0[8]_i_5_n_0 ),
.I5(cycle[3]),
.O(\x0[8]_i_1_n_0 ));
LUT6 #(
.INIT(64'h990FFF00990FFFFF))
\x0[8]_i_2
(.I0(\x_reg_n_0_[8] ),
.I1(\x0[8]_i_6_n_0 ),
.I2(data2[8]),
.I3(cycle[0]),
.I4(\cycle_reg[1]_rep__0_n_0 ),
.I5(\plusOp_inferred__0/i__carry__1_n_7 ),
.O(\x0[8]_i_2_n_0 ));
LUT6 #(
.INIT(64'h8888B888B888B8C0))
\x0[8]_i_3
(.I0(\plusOp_inferred__0/i__carry__1_n_7 ),
.I1(cycle[3]),
.I2(data2[8]),
.I3(\cycle_reg[2]_rep_n_0 ),
.I4(cycle[0]),
.I5(\cycle_reg[1]_rep__0_n_0 ),
.O(\x0[8]_i_3_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT5 #(
.INIT(32'hAAAAAAA9))
\x0[8]_i_4
(.I0(\x_reg_n_0_[8] ),
.I1(\x_reg_n_0_[6] ),
.I2(\x_reg_n_0_[5] ),
.I3(\x0[8]_i_7_n_0 ),
.I4(\x_reg_n_0_[7] ),
.O(\x0[8]_i_4_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair11" *)
LUT3 #(
.INIT(8'h82))
\x0[8]_i_5
(.I0(cycle[0]),
.I1(\cycle_reg[1]_rep__0_n_0 ),
.I2(\cycle_reg[2]_rep_n_0 ),
.O(\x0[8]_i_5_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair7" *)
LUT3 #(
.INIT(8'h08))
\x0[8]_i_6
(.I0(\x_reg_n_0_[7] ),
.I1(\x_reg_n_0_[6] ),
.I2(\x0[6]_i_5_n_0 ),
.O(\x0[8]_i_6_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair4" *)
LUT5 #(
.INIT(32'hFFFFFEEE))
\x0[8]_i_7
(.I0(\x_reg_n_0_[4] ),
.I1(\x_reg_n_0_[2] ),
.I2(\x_reg_n_0_[1] ),
.I3(\x_reg_n_0_[0] ),
.I4(\x_reg_n_0_[3] ),
.O(\x0[8]_i_7_n_0 ));
LUT6 #(
.INIT(64'h77FE000000000000))
\x0[9]_i_1
(.I0(\cycle_reg[2]_rep_n_0 ),
.I1(cycle[3]),
.I2(cycle[0]),
.I3(\cycle_reg[1]_rep__0_n_0 ),
.I4(active),
.I5(rst),
.O(\x0[9]_i_1_n_0 ));
LUT5 #(
.INIT(32'h01FF0101))
\x0[9]_i_2
(.I0(\x0[9]_i_3_n_0 ),
.I1(cycle[3]),
.I2(cycle[2]),
.I3(\x0[9]_i_4_n_0 ),
.I4(\x0[9]_i_5_n_0 ),
.O(\x0[9]_i_2_n_0 ));
LUT6 #(
.INIT(64'hAF03AFF3A003A0F3))
\x0[9]_i_3
(.I0(\x0[9]_i_6_n_0 ),
.I1(\plusOp_inferred__0/i__carry__1_n_6 ),
.I2(\cycle_reg[1]_rep_n_0 ),
.I3(\cycle_reg[0]_rep_n_0 ),
.I4(data2[9]),
.I5(\x0[9]_i_7_n_0 ),
.O(\x0[9]_i_3_n_0 ));
LUT6 #(
.INIT(64'h0C0C0C0C0C0C0C44))
\x0[9]_i_4
(.I0(data2[9]),
.I1(cycle[3]),
.I2(\plusOp_inferred__0/i__carry__1_n_6 ),
.I3(\cycle_reg[0]_rep_n_0 ),
.I4(cycle[2]),
.I5(\cycle_reg[1]_rep_n_0 ),
.O(\x0[9]_i_4_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFF5CCC0000))
\x0[9]_i_5
(.I0(\x0[9]_i_7_n_0 ),
.I1(data2[9]),
.I2(\cycle_reg[1]_rep_n_0 ),
.I3(\cycle_reg[0]_rep_n_0 ),
.I4(cycle[2]),
.I5(cycle[3]),
.O(\x0[9]_i_5_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair7" *)
LUT5 #(
.INIT(32'h55559555))
\x0[9]_i_6
(.I0(\x_reg_n_0_[9] ),
.I1(\x_reg_n_0_[8] ),
.I2(\x_reg_n_0_[7] ),
.I3(\x_reg_n_0_[6] ),
.I4(\x0[6]_i_5_n_0 ),
.O(\x0[9]_i_6_n_0 ));
LUT6 #(
.INIT(64'h5555555555555556))
\x0[9]_i_7
(.I0(\x_reg_n_0_[9] ),
.I1(\x_reg_n_0_[8] ),
.I2(\x_reg_n_0_[7] ),
.I3(\x0[8]_i_7_n_0 ),
.I4(\x_reg_n_0_[5] ),
.I5(\x_reg_n_0_[6] ),
.O(\x0[9]_i_7_n_0 ));
FDRE \x0_reg[0]
(.C(clk_x16),
.CE(\x0[9]_i_1_n_0 ),
.D(\x0_reg[0]_i_1_n_0 ),
.Q(data1[0]),
.R(1'b0));
MUXF7 \x0_reg[0]_i_1
(.I0(\x0[0]_i_2_n_0 ),
.I1(\x0[0]_i_3_n_0 ),
.O(\x0_reg[0]_i_1_n_0 ),
.S(cycle[3]));
FDRE \x0_reg[1]
(.C(clk_x16),
.CE(\x0[9]_i_1_n_0 ),
.D(\x0_reg[1]_i_1_n_0 ),
.Q(data1[1]),
.R(1'b0));
MUXF7 \x0_reg[1]_i_1
(.I0(\x0[1]_i_2_n_0 ),
.I1(\x0[1]_i_3_n_0 ),
.O(\x0_reg[1]_i_1_n_0 ),
.S(cycle[3]));
FDRE \x0_reg[2]
(.C(clk_x16),
.CE(\x0[9]_i_1_n_0 ),
.D(\x0[2]_i_1_n_0 ),
.Q(data1[2]),
.R(1'b0));
FDRE \x0_reg[3]
(.C(clk_x16),
.CE(\x0[9]_i_1_n_0 ),
.D(\x0[3]_i_1_n_0 ),
.Q(data1[3]),
.R(1'b0));
FDRE \x0_reg[4]
(.C(clk_x16),
.CE(\x0[9]_i_1_n_0 ),
.D(\x0[4]_i_1_n_0 ),
.Q(data1[4]),
.R(1'b0));
FDRE \x0_reg[5]
(.C(clk_x16),
.CE(\x0[9]_i_1_n_0 ),
.D(\x0[5]_i_1_n_0 ),
.Q(data1[5]),
.R(1'b0));
FDRE \x0_reg[6]
(.C(clk_x16),
.CE(\x0[9]_i_1_n_0 ),
.D(\x0[6]_i_1_n_0 ),
.Q(data1[6]),
.R(1'b0));
FDRE \x0_reg[7]
(.C(clk_x16),
.CE(\x0[9]_i_1_n_0 ),
.D(\x0[7]_i_1_n_0 ),
.Q(data1[7]),
.R(1'b0));
FDRE \x0_reg[8]
(.C(clk_x16),
.CE(\x0[9]_i_1_n_0 ),
.D(\x0[8]_i_1_n_0 ),
.Q(data1[8]),
.R(1'b0));
FDRE \x0_reg[9]
(.C(clk_x16),
.CE(\x0[9]_i_1_n_0 ),
.D(\x0[9]_i_2_n_0 ),
.Q(data1[9]),
.R(1'b0));
LUT6 #(
.INIT(64'hFF01FF4EFE00B100))
\x1[0]_i_1
(.I0(\cycle_reg[1]_rep__0_n_0 ),
.I1(\cycle_reg[2]_rep_n_0 ),
.I2(cycle[0]),
.I3(\x_reg_n_0_[0] ),
.I4(cycle[3]),
.I5(data1[0]),
.O(\x1[0]_i_1_n_0 ));
LUT6 #(
.INIT(64'hAFEFAAA955565010))
\x1[1]_i_1
(.I0(cycle[3]),
.I1(\cycle_reg[2]_rep_n_0 ),
.I2(cycle[0]),
.I3(\cycle_reg[1]_rep__0_n_0 ),
.I4(data1[1]),
.I5(\x_reg_n_0_[1] ),
.O(\x1[1]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFEFEFEAEAEAEFEAE))
\x1[2]_i_1
(.I0(\x1[2]_i_2_n_0 ),
.I1(\x1[2]_i_3_n_0 ),
.I2(cycle[3]),
.I3(\x_reg_n_0_[2] ),
.I4(\x1[5]_i_3_n_0 ),
.I5(data1[2]),
.O(\x1[2]_i_1_n_0 ));
LUT6 #(
.INIT(64'h8A2A288880202888))
\x1[2]_i_2
(.I0(\x0[7]_i_4_n_0 ),
.I1(\x_reg_n_0_[2] ),
.I2(cycle[0]),
.I3(\x_reg_n_0_[1] ),
.I4(\cycle_reg[1]_rep__0_n_0 ),
.I5(data1[2]),
.O(\x1[2]_i_2_n_0 ));
LUT6 #(
.INIT(64'h3CAAAAAA00000000))
\x1[2]_i_3
(.I0(data1[2]),
.I1(\x_reg_n_0_[1] ),
.I2(\x_reg_n_0_[2] ),
.I3(cycle[0]),
.I4(\cycle_reg[1]_rep__0_n_0 ),
.I5(\cycle_reg[2]_rep_n_0 ),
.O(\x1[2]_i_3_n_0 ));
LUT6 #(
.INIT(64'hFCDDFCDDFFDDCCDD))
\x1[3]_i_1
(.I0(\x1[3]_i_2_n_0 ),
.I1(\x1[3]_i_3_n_0 ),
.I2(data1[3]),
.I3(cycle[3]),
.I4(\x_reg_n_0_[3] ),
.I5(\x1[5]_i_3_n_0 ),
.O(\x1[3]_i_1_n_0 ));
LUT6 #(
.INIT(64'h0770707077777777))
\x1[3]_i_2
(.I0(\x1[9]_i_7_n_0 ),
.I1(data1[3]),
.I2(\x_reg_n_0_[3] ),
.I3(\x_reg_n_0_[2] ),
.I4(\x_reg_n_0_[1] ),
.I5(\x0[8]_i_5_n_0 ),
.O(\x1[3]_i_2_n_0 ));
LUT6 #(
.INIT(64'hA08A0080008AA080))
\x1[3]_i_3
(.I0(\x0[7]_i_4_n_0 ),
.I1(data1[3]),
.I2(\cycle_reg[1]_rep__0_n_0 ),
.I3(cycle[0]),
.I4(\x_reg_n_0_[3] ),
.I5(\x1[3]_i_4_n_0 ),
.O(\x1[3]_i_3_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair54" *)
LUT2 #(
.INIT(4'hE))
\x1[3]_i_4
(.I0(\x_reg_n_0_[1] ),
.I1(\x_reg_n_0_[2] ),
.O(\x1[3]_i_4_n_0 ));
LUT6 #(
.INIT(64'hFCDDFCDDFFDDCCDD))
\x1[4]_i_1
(.I0(\x1[4]_i_2_n_0 ),
.I1(\x1[4]_i_3_n_0 ),
.I2(data1[4]),
.I3(cycle[3]),
.I4(\x_reg_n_0_[4] ),
.I5(\x1[5]_i_3_n_0 ),
.O(\x1[4]_i_1_n_0 ));
LUT6 #(
.INIT(64'h3C555555FFFF3CFF))
\x1[4]_i_2
(.I0(data1[4]),
.I1(\x_reg_n_0_[4] ),
.I2(\x1[4]_i_4_n_0 ),
.I3(cycle[0]),
.I4(\cycle_reg[1]_rep__0_n_0 ),
.I5(\cycle_reg[2]_rep_n_0 ),
.O(\x1[4]_i_2_n_0 ));
LUT6 #(
.INIT(64'hA08A0080008AA080))
\x1[4]_i_3
(.I0(\x0[7]_i_4_n_0 ),
.I1(data1[4]),
.I2(\cycle_reg[1]_rep__0_n_0 ),
.I3(cycle[0]),
.I4(\x_reg_n_0_[4] ),
.I5(\x1[4]_i_5_n_0 ),
.O(\x1[4]_i_3_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair54" *)
LUT3 #(
.INIT(8'hEA))
\x1[4]_i_4
(.I0(\x_reg_n_0_[3] ),
.I1(\x_reg_n_0_[2] ),
.I2(\x_reg_n_0_[1] ),
.O(\x1[4]_i_4_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair21" *)
LUT3 #(
.INIT(8'hFE))
\x1[4]_i_5
(.I0(\x_reg_n_0_[3] ),
.I1(\x_reg_n_0_[2] ),
.I2(\x_reg_n_0_[1] ),
.O(\x1[4]_i_5_n_0 ));
LUT5 #(
.INIT(32'h8A80AAAA))
\x1[5]_i_1
(.I0(\x1[5]_i_2_n_0 ),
.I1(data1[5]),
.I2(\x1[5]_i_3_n_0 ),
.I3(\x_reg_n_0_[5] ),
.I4(cycle[3]),
.O(\x1[5]_i_1_n_0 ));
LUT6 #(
.INIT(64'hCDFDCDCDFDFDFDCD))
\x1[5]_i_2
(.I0(\x1[5]_i_4_n_0 ),
.I1(cycle[3]),
.I2(\cycle_reg[2]_rep_n_0 ),
.I3(\x1[6]_i_8_n_0 ),
.I4(data1[5]),
.I5(\x1[5]_i_5_n_0 ),
.O(\x1[5]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair10" *)
LUT3 #(
.INIT(8'h01))
\x1[5]_i_3
(.I0(\cycle_reg[1]_rep__0_n_0 ),
.I1(\cycle_reg[2]_rep_n_0 ),
.I2(cycle[0]),
.O(\x1[5]_i_3_n_0 ));
LUT6 #(
.INIT(64'h0530FA3FF5300A3F))
\x1[5]_i_4
(.I0(\x1[6]_i_7_n_0 ),
.I1(data1[5]),
.I2(\cycle_reg[1]_rep__0_n_0 ),
.I3(cycle[0]),
.I4(\x_reg_n_0_[5] ),
.I5(\left[15]_i_3_n_0 ),
.O(\x1[5]_i_4_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair13" *)
LUT5 #(
.INIT(32'h55555666))
\x1[5]_i_5
(.I0(\x_reg_n_0_[5] ),
.I1(\x_reg_n_0_[3] ),
.I2(\x_reg_n_0_[2] ),
.I3(\x_reg_n_0_[1] ),
.I4(\x_reg_n_0_[4] ),
.O(\x1[5]_i_5_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT5 #(
.INIT(32'hFFF100F1))
\x1[6]_i_1
(.I0(\x1[6]_i_2_n_0 ),
.I1(\cycle_reg[2]_rep_n_0 ),
.I2(\x1[6]_i_3_n_0 ),
.I3(cycle[3]),
.I4(\x1[6]_i_4_n_0 ),
.O(\x1[6]_i_1_n_0 ));
LUT6 #(
.INIT(64'hCFC05050CFC05F5F))
\x1[6]_i_2
(.I0(data1[6]),
.I1(\x1[6]_i_5_n_0 ),
.I2(\cycle_reg[1]_rep__0_n_0 ),
.I3(\x1[6]_i_6_n_0 ),
.I4(cycle[0]),
.I5(\x_reg_n_0_[6] ),
.O(\x1[6]_i_2_n_0 ));
LUT6 #(
.INIT(64'hA900FF00A9000000))
\x1[6]_i_3
(.I0(\x_reg_n_0_[6] ),
.I1(\x1[6]_i_7_n_0 ),
.I2(\x_reg_n_0_[5] ),
.I3(\cycle_reg[2]_rep_n_0 ),
.I4(\x1[6]_i_8_n_0 ),
.I5(data1[6]),
.O(\x1[6]_i_3_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair10" *)
LUT5 #(
.INIT(32'hFFFE0002))
\x1[6]_i_4
(.I0(data1[6]),
.I1(cycle[0]),
.I2(\cycle_reg[2]_rep_n_0 ),
.I3(\cycle_reg[1]_rep__0_n_0 ),
.I4(\x_reg_n_0_[6] ),
.O(\x1[6]_i_4_n_0 ));
LUT6 #(
.INIT(64'h5555555555555556))
\x1[6]_i_5
(.I0(\x_reg_n_0_[6] ),
.I1(\x_reg_n_0_[4] ),
.I2(\x_reg_n_0_[1] ),
.I3(\x_reg_n_0_[2] ),
.I4(\x_reg_n_0_[3] ),
.I5(\x_reg_n_0_[5] ),
.O(\x1[6]_i_5_n_0 ));
LUT6 #(
.INIT(64'h5555555555555666))
\x1[6]_i_6
(.I0(\x_reg_n_0_[6] ),
.I1(\x_reg_n_0_[4] ),
.I2(\x_reg_n_0_[1] ),
.I3(\x_reg_n_0_[2] ),
.I4(\x_reg_n_0_[3] ),
.I5(\x_reg_n_0_[5] ),
.O(\x1[6]_i_6_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair21" *)
LUT4 #(
.INIT(16'hFFEA))
\x1[6]_i_7
(.I0(\x_reg_n_0_[4] ),
.I1(\x_reg_n_0_[1] ),
.I2(\x_reg_n_0_[2] ),
.I3(\x_reg_n_0_[3] ),
.O(\x1[6]_i_7_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair14" *)
LUT2 #(
.INIT(4'h8))
\x1[6]_i_8
(.I0(\cycle_reg[1]_rep__0_n_0 ),
.I1(cycle[0]),
.O(\x1[6]_i_8_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair8" *)
LUT5 #(
.INIT(32'hFFF100F1))
\x1[7]_i_1
(.I0(\x1[7]_i_2_n_0 ),
.I1(\cycle_reg[2]_rep_n_0 ),
.I2(\x1[7]_i_3_n_0 ),
.I3(cycle[3]),
.I4(\x1[7]_i_4_n_0 ),
.O(\x1[7]_i_1_n_0 ));
LUT6 #(
.INIT(64'h303F5050CFC05F5F))
\x1[7]_i_2
(.I0(data1[7]),
.I1(\x1[7]_i_5_n_0 ),
.I2(\cycle_reg[1]_rep__0_n_0 ),
.I3(\x1[9]_i_6_n_0 ),
.I4(cycle[0]),
.I5(\x_reg_n_0_[7] ),
.O(\x1[7]_i_2_n_0 ));
LUT6 #(
.INIT(64'h90F0F0F090000000))
\x1[7]_i_3
(.I0(\x_reg_n_0_[7] ),
.I1(\x1[9]_i_6_n_0 ),
.I2(\cycle_reg[2]_rep_n_0 ),
.I3(cycle[0]),
.I4(\cycle_reg[1]_rep__0_n_0 ),
.I5(data1[7]),
.O(\x1[7]_i_3_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair11" *)
LUT5 #(
.INIT(32'hFFFE0002))
\x1[7]_i_4
(.I0(data1[7]),
.I1(cycle[0]),
.I2(\cycle_reg[2]_rep_n_0 ),
.I3(\cycle_reg[1]_rep__0_n_0 ),
.I4(\x_reg_n_0_[7] ),
.O(\x1[7]_i_4_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFFFFFFFFFE))
\x1[7]_i_5
(.I0(\x_reg_n_0_[3] ),
.I1(\x_reg_n_0_[2] ),
.I2(\x_reg_n_0_[1] ),
.I3(\x_reg_n_0_[4] ),
.I4(\x_reg_n_0_[6] ),
.I5(\x_reg_n_0_[5] ),
.O(\x1[7]_i_5_n_0 ));
LUT4 #(
.INIT(16'hFF01))
\x1[8]_i_1
(.I0(\x1[8]_i_2_n_0 ),
.I1(cycle[3]),
.I2(\cycle_reg[2]_rep_n_0 ),
.I3(\x1[8]_i_3_n_0 ),
.O(\x1[8]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFA300A3F0A30FA3F))
\x1[8]_i_2
(.I0(\x1[8]_i_4_n_0 ),
.I1(data1[8]),
.I2(\cycle_reg[1]_rep__0_n_0 ),
.I3(cycle[0]),
.I4(\x_reg_n_0_[8] ),
.I5(\left[15]_i_2_n_0 ),
.O(\x1[8]_i_2_n_0 ));
LUT6 #(
.INIT(64'hFF0FEECCF000EECC))
\x1[8]_i_3
(.I0(\x1[9]_i_7_n_0 ),
.I1(\x1[8]_i_5_n_0 ),
.I2(\x1[5]_i_3_n_0 ),
.I3(data1[8]),
.I4(cycle[3]),
.I5(\x_reg_n_0_[8] ),
.O(\x1[8]_i_3_n_0 ));
LUT5 #(
.INIT(32'h55555556))
\x1[8]_i_4
(.I0(\x_reg_n_0_[8] ),
.I1(\x_reg_n_0_[6] ),
.I2(\x_reg_n_0_[5] ),
.I3(\x1[6]_i_7_n_0 ),
.I4(\x_reg_n_0_[7] ),
.O(\x1[8]_i_4_n_0 ));
LUT6 #(
.INIT(64'hAAAAAAA800000002))
\x1[8]_i_5
(.I0(\x1[8]_i_6_n_0 ),
.I1(\x_reg_n_0_[7] ),
.I2(\x1[6]_i_7_n_0 ),
.I3(\x_reg_n_0_[5] ),
.I4(\x_reg_n_0_[6] ),
.I5(\x_reg_n_0_[8] ),
.O(\x1[8]_i_5_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair6" *)
LUT3 #(
.INIT(8'h80))
\x1[8]_i_6
(.I0(cycle[0]),
.I1(\cycle_reg[1]_rep__0_n_0 ),
.I2(\cycle_reg[2]_rep_n_0 ),
.O(\x1[8]_i_6_n_0 ));
LUT6 #(
.INIT(64'h0088008880880880))
\x1[9]_i_1
(.I0(active),
.I1(rst),
.I2(cycle[0]),
.I3(cycle[3]),
.I4(\cycle_reg[2]_rep_n_0 ),
.I5(\cycle_reg[1]_rep__0_n_0 ),
.O(x1));
LUT6 #(
.INIT(64'hFFFFFFFF00000047))
\x1[9]_i_2
(.I0(\x1[9]_i_3_n_0 ),
.I1(\cycle_reg[1]_rep__0_n_0 ),
.I2(\x1[9]_i_4_n_0 ),
.I3(cycle[3]),
.I4(\cycle_reg[2]_rep_n_0 ),
.I5(\x1[9]_i_5_n_0 ),
.O(\x1[9]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT5 #(
.INIT(32'h3C335555))
\x1[9]_i_3
(.I0(data1[9]),
.I1(\x_reg_n_0_[9] ),
.I2(\x_reg_n_0_[8] ),
.I3(\left[15]_i_2_n_0 ),
.I4(cycle[0]),
.O(\x1[9]_i_3_n_0 ));
LUT5 #(
.INIT(32'h0100FEFF))
\x1[9]_i_4
(.I0(\x_reg_n_0_[8] ),
.I1(\x_reg_n_0_[7] ),
.I2(\x1[9]_i_6_n_0 ),
.I3(cycle[0]),
.I4(\x_reg_n_0_[9] ),
.O(\x1[9]_i_4_n_0 ));
LUT6 #(
.INIT(64'hFF0FEECCF000EECC))
\x1[9]_i_5
(.I0(\x1[9]_i_7_n_0 ),
.I1(\x1[9]_i_8_n_0 ),
.I2(\x1[5]_i_3_n_0 ),
.I3(data1[9]),
.I4(cycle[3]),
.I5(\x_reg_n_0_[9] ),
.O(\x1[9]_i_5_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFFFFFEFEFE))
\x1[9]_i_6
(.I0(\x_reg_n_0_[6] ),
.I1(\x_reg_n_0_[5] ),
.I2(\x_reg_n_0_[3] ),
.I3(\x_reg_n_0_[2] ),
.I4(\x_reg_n_0_[1] ),
.I5(\x_reg_n_0_[4] ),
.O(\x1[9]_i_6_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair9" *)
LUT3 #(
.INIT(8'h2A))
\x1[9]_i_7
(.I0(\cycle_reg[2]_rep_n_0 ),
.I1(cycle[0]),
.I2(\cycle_reg[1]_rep__0_n_0 ),
.O(\x1[9]_i_7_n_0 ));
LUT6 #(
.INIT(64'h8888888000000008))
\x1[9]_i_8
(.I0(\cycle_reg[2]_rep_n_0 ),
.I1(\x1[6]_i_8_n_0 ),
.I2(\x1[9]_i_6_n_0 ),
.I3(\x_reg_n_0_[7] ),
.I4(\x_reg_n_0_[8] ),
.I5(\x_reg_n_0_[9] ),
.O(\x1[9]_i_8_n_0 ));
FDRE \x1_reg[0]
(.C(clk_x16),
.CE(x1),
.D(\x1[0]_i_1_n_0 ),
.Q(data2[0]),
.R(1'b0));
FDRE \x1_reg[1]
(.C(clk_x16),
.CE(x1),
.D(\x1[1]_i_1_n_0 ),
.Q(data2[1]),
.R(1'b0));
FDRE \x1_reg[2]
(.C(clk_x16),
.CE(x1),
.D(\x1[2]_i_1_n_0 ),
.Q(data2[2]),
.R(1'b0));
FDRE \x1_reg[3]
(.C(clk_x16),
.CE(x1),
.D(\x1[3]_i_1_n_0 ),
.Q(data2[3]),
.R(1'b0));
FDRE \x1_reg[4]
(.C(clk_x16),
.CE(x1),
.D(\x1[4]_i_1_n_0 ),
.Q(data2[4]),
.R(1'b0));
FDRE \x1_reg[5]
(.C(clk_x16),
.CE(x1),
.D(\x1[5]_i_1_n_0 ),
.Q(data2[5]),
.R(1'b0));
FDRE \x1_reg[6]
(.C(clk_x16),
.CE(x1),
.D(\x1[6]_i_1_n_0 ),
.Q(data2[6]),
.R(1'b0));
FDRE \x1_reg[7]
(.C(clk_x16),
.CE(x1),
.D(\x1[7]_i_1_n_0 ),
.Q(data2[7]),
.R(1'b0));
FDRE \x1_reg[8]
(.C(clk_x16),
.CE(x1),
.D(\x1[8]_i_1_n_0 ),
.Q(data2[8]),
.R(1'b0));
FDRE \x1_reg[9]
(.C(clk_x16),
.CE(x1),
.D(\x1[9]_i_2_n_0 ),
.Q(data2[9]),
.R(1'b0));
LUT6 #(
.INIT(64'h0000000000000040))
\x[9]_i_1
(.I0(cycle[0]),
.I1(active),
.I2(rst),
.I3(\cycle_reg[1]_rep_n_0 ),
.I4(cycle[3]),
.I5(cycle[2]),
.O(x));
FDRE \x_reg[0]
(.C(clk_x16),
.CE(x),
.D(x_addr[0]),
.Q(\x_reg_n_0_[0] ),
.R(1'b0));
FDRE \x_reg[1]
(.C(clk_x16),
.CE(x),
.D(x_addr[1]),
.Q(\x_reg_n_0_[1] ),
.R(1'b0));
FDRE \x_reg[2]
(.C(clk_x16),
.CE(x),
.D(x_addr[2]),
.Q(\x_reg_n_0_[2] ),
.R(1'b0));
FDRE \x_reg[3]
(.C(clk_x16),
.CE(x),
.D(x_addr[3]),
.Q(\x_reg_n_0_[3] ),
.R(1'b0));
FDRE \x_reg[4]
(.C(clk_x16),
.CE(x),
.D(x_addr[4]),
.Q(\x_reg_n_0_[4] ),
.R(1'b0));
FDRE \x_reg[5]
(.C(clk_x16),
.CE(x),
.D(x_addr[5]),
.Q(\x_reg_n_0_[5] ),
.R(1'b0));
FDRE \x_reg[6]
(.C(clk_x16),
.CE(x),
.D(x_addr[6]),
.Q(\x_reg_n_0_[6] ),
.R(1'b0));
FDRE \x_reg[7]
(.C(clk_x16),
.CE(x),
.D(x_addr[7]),
.Q(\x_reg_n_0_[7] ),
.R(1'b0));
FDRE \x_reg[8]
(.C(clk_x16),
.CE(x),
.D(x_addr[8]),
.Q(\x_reg_n_0_[8] ),
.R(1'b0));
FDRE \x_reg[9]
(.C(clk_x16),
.CE(x),
.D(x_addr[9]),
.Q(\x_reg_n_0_[9] ),
.R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair20" *)
LUT3 #(
.INIT(8'hE1))
\y1[2]_i_1
(.I0(\y_actual_reg_n_0_[0] ),
.I1(\y_actual_reg_n_0_[1] ),
.I2(\y_actual_reg_n_0_[2] ),
.O(\y1[2]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair23" *)
LUT4 #(
.INIT(16'hFE01))
\y1[3]_i_1
(.I0(\y_actual_reg_n_0_[2] ),
.I1(\y_actual_reg_n_0_[1] ),
.I2(\y_actual_reg_n_0_[0] ),
.I3(\y_actual_reg_n_0_[3] ),
.O(\y1[3]_i_1_n_0 ));
FDRE \y1_reg[0]
(.C(clk_x16),
.CE(y1),
.D(\y5[0]_i_1_n_0 ),
.Q(\y1_reg_n_0_[0] ),
.R(1'b0));
FDRE \y1_reg[1]
(.C(clk_x16),
.CE(y1),
.D(\y5[1]_i_1_n_0 ),
.Q(\y1_reg_n_0_[1] ),
.R(1'b0));
FDRE \y1_reg[2]
(.C(clk_x16),
.CE(y1),
.D(\y1[2]_i_1_n_0 ),
.Q(\y1_reg_n_0_[2] ),
.R(1'b0));
FDRE \y1_reg[3]
(.C(clk_x16),
.CE(y1),
.D(\y1[3]_i_1_n_0 ),
.Q(\y1_reg_n_0_[3] ),
.R(1'b0));
LUT1 #(
.INIT(2'h1))
\y2[1]_i_1
(.I0(\y_actual_reg_n_0_[1] ),
.O(\y2[1]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair28" *)
LUT2 #(
.INIT(4'h9))
\y2[2]_i_1
(.I0(\y_actual_reg_n_0_[2] ),
.I1(\y_actual_reg_n_0_[1] ),
.O(\y2[2]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair19" *)
LUT3 #(
.INIT(8'hA9))
\y2[3]_i_1
(.I0(\y_actual_reg_n_0_[3] ),
.I1(\y_actual_reg_n_0_[2] ),
.I2(\y_actual_reg_n_0_[1] ),
.O(\y2[3]_i_1_n_0 ));
FDRE \y2_reg[0]
(.C(clk_x16),
.CE(y2),
.D(\y_actual_reg_n_0_[0] ),
.Q(\y2_reg_n_0_[0] ),
.R(1'b0));
FDRE \y2_reg[1]
(.C(clk_x16),
.CE(y2),
.D(\y2[1]_i_1_n_0 ),
.Q(\y2_reg_n_0_[1] ),
.R(1'b0));
FDRE \y2_reg[2]
(.C(clk_x16),
.CE(y2),
.D(\y2[2]_i_1_n_0 ),
.Q(\y2_reg_n_0_[2] ),
.R(1'b0));
FDRE \y2_reg[3]
(.C(clk_x16),
.CE(y2),
.D(\y2[3]_i_1_n_0 ),
.Q(\y2_reg_n_0_[3] ),
.R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair87" *)
LUT2 #(
.INIT(4'h6))
\y3[1]_i_1
(.I0(\y_actual_reg_n_0_[0] ),
.I1(\y_actual_reg_n_0_[1] ),
.O(\y3[1]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair22" *)
LUT3 #(
.INIT(8'h87))
\y3[2]_i_1
(.I0(\y_actual_reg_n_0_[0] ),
.I1(\y_actual_reg_n_0_[1] ),
.I2(\y_actual_reg_n_0_[2] ),
.O(\y3[2]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair22" *)
LUT4 #(
.INIT(16'hAA95))
\y3[3]_i_1
(.I0(\y_actual_reg_n_0_[3] ),
.I1(\y_actual_reg_n_0_[0] ),
.I2(\y_actual_reg_n_0_[1] ),
.I3(\y_actual_reg_n_0_[2] ),
.O(\y3[3]_i_1_n_0 ));
FDRE \y3_reg[0]
(.C(clk_x16),
.CE(y3),
.D(\y5[0]_i_1_n_0 ),
.Q(\y3_reg_n_0_[0] ),
.R(1'b0));
FDRE \y3_reg[1]
(.C(clk_x16),
.CE(y3),
.D(\y3[1]_i_1_n_0 ),
.Q(\y3_reg_n_0_[1] ),
.R(1'b0));
FDRE \y3_reg[2]
(.C(clk_x16),
.CE(y3),
.D(\y3[2]_i_1_n_0 ),
.Q(\y3_reg_n_0_[2] ),
.R(1'b0));
FDRE \y3_reg[3]
(.C(clk_x16),
.CE(y3),
.D(\y3[3]_i_1_n_0 ),
.Q(\y3_reg_n_0_[3] ),
.R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair86" *)
LUT1 #(
.INIT(2'h1))
\y4[2]_i_1
(.I0(\y_actual_reg_n_0_[2] ),
.O(\y4[2]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair86" *)
LUT2 #(
.INIT(4'h9))
\y4[3]_i_1
(.I0(\y_actual_reg_n_0_[3] ),
.I1(\y_actual_reg_n_0_[2] ),
.O(\y4[3]_i_1_n_0 ));
FDRE \y4_reg[0]
(.C(clk_x16),
.CE(y1),
.D(\y_actual_reg_n_0_[0] ),
.Q(data2[10]),
.R(1'b0));
FDRE \y4_reg[1]
(.C(clk_x16),
.CE(y1),
.D(\y_actual_reg_n_0_[1] ),
.Q(data2[11]),
.R(1'b0));
FDRE \y4_reg[2]
(.C(clk_x16),
.CE(y1),
.D(\y4[2]_i_1_n_0 ),
.Q(data2[12]),
.R(1'b0));
FDRE \y4_reg[3]
(.C(clk_x16),
.CE(y1),
.D(\y4[3]_i_1_n_0 ),
.Q(data2[13]),
.R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair87" *)
LUT1 #(
.INIT(2'h1))
\y5[0]_i_1
(.I0(\y_actual_reg_n_0_[0] ),
.O(\y5[0]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair23" *)
LUT2 #(
.INIT(4'h9))
\y5[1]_i_1
(.I0(\y_actual_reg_n_0_[1] ),
.I1(\y_actual_reg_n_0_[0] ),
.O(\y5[1]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair18" *)
LUT3 #(
.INIT(8'h56))
\y5[2]_i_1
(.I0(\y_actual_reg_n_0_[2] ),
.I1(\y_actual_reg_n_0_[1] ),
.I2(\y_actual_reg_n_0_[0] ),
.O(\y5[2]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair18" *)
LUT4 #(
.INIT(16'hA955))
\y5[3]_i_1
(.I0(\y_actual_reg_n_0_[3] ),
.I1(\y_actual_reg_n_0_[0] ),
.I2(\y_actual_reg_n_0_[1] ),
.I3(\y_actual_reg_n_0_[2] ),
.O(\y5[3]_i_1_n_0 ));
FDRE \y5_reg[0]
(.C(clk_x16),
.CE(y5),
.D(\y5[0]_i_1_n_0 ),
.Q(data1[10]),
.R(1'b0));
FDRE \y5_reg[1]
(.C(clk_x16),
.CE(y5),
.D(\y5[1]_i_1_n_0 ),
.Q(data1[11]),
.R(1'b0));
FDRE \y5_reg[2]
(.C(clk_x16),
.CE(y5),
.D(\y5[2]_i_1_n_0 ),
.Q(data1[12]),
.R(1'b0));
FDRE \y5_reg[3]
(.C(clk_x16),
.CE(y5),
.D(\y5[3]_i_1_n_0 ),
.Q(data1[13]),
.R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair34" *)
LUT2 #(
.INIT(4'h6))
\y6[2]_i_1
(.I0(\y_actual_reg_n_0_[1] ),
.I1(\y_actual_reg_n_0_[2] ),
.O(\y6[2]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair34" *)
LUT3 #(
.INIT(8'h95))
\y6[3]_i_1
(.I0(\y_actual_reg_n_0_[3] ),
.I1(\y_actual_reg_n_0_[2] ),
.I2(\y_actual_reg_n_0_[1] ),
.O(\y6[3]_i_1_n_0 ));
FDRE \y6_reg[0]
(.C(clk_x16),
.CE(y6),
.D(\y_actual_reg_n_0_[0] ),
.Q(\y6_reg_n_0_[0] ),
.R(1'b0));
FDRE \y6_reg[1]
(.C(clk_x16),
.CE(y6),
.D(\y2[1]_i_1_n_0 ),
.Q(\y6_reg_n_0_[1] ),
.R(1'b0));
FDRE \y6_reg[2]
(.C(clk_x16),
.CE(y6),
.D(\y6[2]_i_1_n_0 ),
.Q(\y6_reg_n_0_[2] ),
.R(1'b0));
FDRE \y6_reg[3]
(.C(clk_x16),
.CE(y6),
.D(\y6[3]_i_1_n_0 ),
.Q(\y6_reg_n_0_[3] ),
.R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair28" *)
LUT3 #(
.INIT(8'h6A))
\y7[2]_i_1
(.I0(\y_actual_reg_n_0_[2] ),
.I1(\y_actual_reg_n_0_[1] ),
.I2(\y_actual_reg_n_0_[0] ),
.O(\y7[2]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair19" *)
LUT4 #(
.INIT(16'h9555))
\y7[3]_i_1
(.I0(\y_actual_reg_n_0_[3] ),
.I1(\y_actual_reg_n_0_[0] ),
.I2(\y_actual_reg_n_0_[1] ),
.I3(\y_actual_reg_n_0_[2] ),
.O(\y7[3]_i_1_n_0 ));
FDRE \y7_reg[0]
(.C(clk_x16),
.CE(y2),
.D(\y5[0]_i_1_n_0 ),
.Q(y7[0]),
.R(1'b0));
FDRE \y7_reg[1]
(.C(clk_x16),
.CE(y2),
.D(\y3[1]_i_1_n_0 ),
.Q(y7[1]),
.R(1'b0));
FDRE \y7_reg[2]
(.C(clk_x16),
.CE(y2),
.D(\y7[2]_i_1_n_0 ),
.Q(y7[2]),
.R(1'b0));
FDRE \y7_reg[3]
(.C(clk_x16),
.CE(y2),
.D(\y7[3]_i_1_n_0 ),
.Q(y7[3]),
.R(1'b0));
LUT1 #(
.INIT(2'h1))
\y8[3]_i_1
(.I0(\y_actual_reg_n_0_[3] ),
.O(\y8[3]_i_1_n_0 ));
FDRE \y8_reg[0]
(.C(clk_x16),
.CE(y5),
.D(\y_actual_reg_n_0_[0] ),
.Q(y8[0]),
.R(1'b0));
FDRE \y8_reg[1]
(.C(clk_x16),
.CE(y5),
.D(\y_actual_reg_n_0_[1] ),
.Q(y8[1]),
.R(1'b0));
FDRE \y8_reg[2]
(.C(clk_x16),
.CE(y5),
.D(\y_actual_reg_n_0_[2] ),
.Q(y8[2]),
.R(1'b0));
FDRE \y8_reg[3]
(.C(clk_x16),
.CE(y5),
.D(\y8[3]_i_1_n_0 ),
.Q(y8[3]),
.R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair20" *)
LUT4 #(
.INIT(16'h5556))
\y9[3]_i_1
(.I0(\y_actual_reg_n_0_[3] ),
.I1(\y_actual_reg_n_0_[0] ),
.I2(\y_actual_reg_n_0_[1] ),
.I3(\y_actual_reg_n_0_[2] ),
.O(\y9[3]_i_1_n_0 ));
FDRE \y9_reg[0]
(.C(clk_x16),
.CE(y9),
.D(\y5[0]_i_1_n_0 ),
.Q(data5[10]),
.R(1'b0));
FDRE \y9_reg[1]
(.C(clk_x16),
.CE(y9),
.D(\y5[1]_i_1_n_0 ),
.Q(data5[11]),
.R(1'b0));
FDRE \y9_reg[2]
(.C(clk_x16),
.CE(y9),
.D(\y1[2]_i_1_n_0 ),
.Q(data5[12]),
.R(1'b0));
FDRE \y9_reg[3]
(.C(clk_x16),
.CE(y9),
.D(\y9[3]_i_1_n_0 ),
.Q(data5[13]),
.R(1'b0));
FDRE \y_actual_reg[0]
(.C(clk_x16),
.CE(x),
.D(y_addr[0]),
.Q(\y_actual_reg_n_0_[0] ),
.R(1'b0));
FDRE \y_actual_reg[1]
(.C(clk_x16),
.CE(x),
.D(y_addr[1]),
.Q(\y_actual_reg_n_0_[1] ),
.R(1'b0));
FDRE \y_actual_reg[2]
(.C(clk_x16),
.CE(x),
.D(y_addr[2]),
.Q(\y_actual_reg_n_0_[2] ),
.R(1'b0));
FDRE \y_actual_reg[3]
(.C(clk_x16),
.CE(x),
.D(y_addr[3]),
.Q(\y_actual_reg_n_0_[3] ),
.R(1'b0));
FDRE \y_actual_reg[4]
(.C(clk_x16),
.CE(x),
.D(y_addr[4]),
.Q(\y_actual_reg_n_0_[4] ),
.R(1'b0));
FDRE \y_actual_reg[5]
(.C(clk_x16),
.CE(x),
.D(y_addr[5]),
.Q(\y_actual_reg_n_0_[5] ),
.R(1'b0));
FDRE \y_actual_reg[6]
(.C(clk_x16),
.CE(x),
.D(y_addr[6]),
.Q(\y_actual_reg_n_0_[6] ),
.R(1'b0));
FDRE \y_actual_reg[7]
(.C(clk_x16),
.CE(x),
.D(y_addr[7]),
.Q(\y_actual_reg_n_0_[7] ),
.R(1'b0));
FDRE \y_actual_reg[8]
(.C(clk_x16),
.CE(x),
.D(y_addr[8]),
.Q(\y_actual_reg_n_0_[8] ),
.R(1'b0));
FDRE \y_actual_reg[9]
(.C(clk_x16),
.CE(x),
.D(y_addr[9]),
.Q(\y_actual_reg_n_0_[9] ),
.R(1'b0));
endmodule
|
module system_vga_hessian_0_0_bindec
(ena_array,
ena,
addra);
output [2:0]ena_array;
input ena;
input [1:0]addra;
wire [1:0]addra;
wire ena;
wire [2:0]ena_array;
LUT3 #(
.INIT(8'h02))
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_i_1
(.I0(ena),
.I1(addra[0]),
.I2(addra[1]),
.O(ena_array[0]));
LUT3 #(
.INIT(8'h40))
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_i_1__0
(.I0(addra[1]),
.I1(addra[0]),
.I2(ena),
.O(ena_array[1]));
LUT3 #(
.INIT(8'h40))
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_i_1__1
(.I0(addra[0]),
.I1(ena),
.I2(addra[1]),
.O(ena_array[2]));
endmodule
|
module system_vga_hessian_0_0_bindec_0
(enb_array,
enb,
addrb);
output [2:0]enb_array;
input enb;
input [1:0]addrb;
wire [1:0]addrb;
wire enb;
wire [2:0]enb_array;
LUT3 #(
.INIT(8'h02))
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_i_2
(.I0(enb),
.I1(addrb[0]),
.I2(addrb[1]),
.O(enb_array[0]));
LUT3 #(
.INIT(8'h40))
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_i_2__0
(.I0(addrb[1]),
.I1(addrb[0]),
.I2(enb),
.O(enb_array[1]));
LUT3 #(
.INIT(8'h40))
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_i_2__1
(.I0(addrb[0]),
.I1(enb),
.I2(addrb[1]),
.O(enb_array[2]));
endmodule
|
module system_vga_hessian_0_0_blk_mem_gen_generic_cstr
(douta,
doutb,
addra,
ena,
addrb,
enb,
clka,
clkb,
dina,
dinb,
wea,
web);
output [15:0]douta;
output [15:0]doutb;
input [13:0]addra;
input ena;
input [13:0]addrb;
input enb;
input clka;
input clkb;
input [15:0]dina;
input [15:0]dinb;
input [0:0]wea;
input [0:0]web;
wire [13:0]addra;
wire [13:0]addrb;
wire clka;
wire clkb;
wire [15:0]dina;
wire [15:0]dinb;
wire [15:0]douta;
wire [15:0]doutb;
wire ena;
wire [2:0]ena_array;
wire enb;
wire [2:0]enb_array;
wire \ramloop[4].ram.r_n_0 ;
wire \ramloop[4].ram.r_n_1 ;
wire \ramloop[4].ram.r_n_10 ;
wire \ramloop[4].ram.r_n_11 ;
wire \ramloop[4].ram.r_n_12 ;
wire \ramloop[4].ram.r_n_13 ;
wire \ramloop[4].ram.r_n_14 ;
wire \ramloop[4].ram.r_n_15 ;
wire \ramloop[4].ram.r_n_16 ;
wire \ramloop[4].ram.r_n_17 ;
wire \ramloop[4].ram.r_n_2 ;
wire \ramloop[4].ram.r_n_3 ;
wire \ramloop[4].ram.r_n_4 ;
wire \ramloop[4].ram.r_n_5 ;
wire \ramloop[4].ram.r_n_6 ;
wire \ramloop[4].ram.r_n_7 ;
wire \ramloop[4].ram.r_n_8 ;
wire \ramloop[4].ram.r_n_9 ;
wire \ramloop[5].ram.r_n_0 ;
wire \ramloop[5].ram.r_n_1 ;
wire \ramloop[5].ram.r_n_10 ;
wire \ramloop[5].ram.r_n_11 ;
wire \ramloop[5].ram.r_n_12 ;
wire \ramloop[5].ram.r_n_13 ;
wire \ramloop[5].ram.r_n_14 ;
wire \ramloop[5].ram.r_n_15 ;
wire \ramloop[5].ram.r_n_16 ;
wire \ramloop[5].ram.r_n_17 ;
wire \ramloop[5].ram.r_n_2 ;
wire \ramloop[5].ram.r_n_3 ;
wire \ramloop[5].ram.r_n_4 ;
wire \ramloop[5].ram.r_n_5 ;
wire \ramloop[5].ram.r_n_6 ;
wire \ramloop[5].ram.r_n_7 ;
wire \ramloop[5].ram.r_n_8 ;
wire \ramloop[5].ram.r_n_9 ;
wire \ramloop[6].ram.r_n_0 ;
wire \ramloop[6].ram.r_n_1 ;
wire \ramloop[6].ram.r_n_10 ;
wire \ramloop[6].ram.r_n_11 ;
wire \ramloop[6].ram.r_n_12 ;
wire \ramloop[6].ram.r_n_13 ;
wire \ramloop[6].ram.r_n_14 ;
wire \ramloop[6].ram.r_n_15 ;
wire \ramloop[6].ram.r_n_16 ;
wire \ramloop[6].ram.r_n_17 ;
wire \ramloop[6].ram.r_n_2 ;
wire \ramloop[6].ram.r_n_3 ;
wire \ramloop[6].ram.r_n_4 ;
wire \ramloop[6].ram.r_n_5 ;
wire \ramloop[6].ram.r_n_6 ;
wire \ramloop[6].ram.r_n_7 ;
wire \ramloop[6].ram.r_n_8 ;
wire \ramloop[6].ram.r_n_9 ;
wire \ramloop[7].ram.r_n_0 ;
wire \ramloop[7].ram.r_n_1 ;
wire \ramloop[7].ram.r_n_10 ;
wire \ramloop[7].ram.r_n_11 ;
wire \ramloop[7].ram.r_n_12 ;
wire \ramloop[7].ram.r_n_13 ;
wire \ramloop[7].ram.r_n_14 ;
wire \ramloop[7].ram.r_n_15 ;
wire \ramloop[7].ram.r_n_16 ;
wire \ramloop[7].ram.r_n_17 ;
wire \ramloop[7].ram.r_n_2 ;
wire \ramloop[7].ram.r_n_3 ;
wire \ramloop[7].ram.r_n_4 ;
wire \ramloop[7].ram.r_n_5 ;
wire \ramloop[7].ram.r_n_6 ;
wire \ramloop[7].ram.r_n_7 ;
wire \ramloop[7].ram.r_n_8 ;
wire \ramloop[7].ram.r_n_9 ;
wire [0:0]wea;
wire [0:0]web;
system_vga_hessian_0_0_bindec \bindec_a.bindec_inst_a
(.addra(addra[13:12]),
.ena(ena),
.ena_array(ena_array));
system_vga_hessian_0_0_bindec_0 \bindec_b.bindec_inst_b
(.addrb(addrb[13:12]),
.enb(enb),
.enb_array(enb_array));
system_vga_hessian_0_0_blk_mem_gen_mux \has_mux_a.A
(.\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram ({\ramloop[5].ram.r_n_0 ,\ramloop[5].ram.r_n_1 ,\ramloop[5].ram.r_n_2 ,\ramloop[5].ram.r_n_3 ,\ramloop[5].ram.r_n_4 ,\ramloop[5].ram.r_n_5 ,\ramloop[5].ram.r_n_6 ,\ramloop[5].ram.r_n_7 }),
.\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0 ({\ramloop[6].ram.r_n_0 ,\ramloop[6].ram.r_n_1 ,\ramloop[6].ram.r_n_2 ,\ramloop[6].ram.r_n_3 ,\ramloop[6].ram.r_n_4 ,\ramloop[6].ram.r_n_5 ,\ramloop[6].ram.r_n_6 ,\ramloop[6].ram.r_n_7 }),
.\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1 ({\ramloop[4].ram.r_n_0 ,\ramloop[4].ram.r_n_1 ,\ramloop[4].ram.r_n_2 ,\ramloop[4].ram.r_n_3 ,\ramloop[4].ram.r_n_4 ,\ramloop[4].ram.r_n_5 ,\ramloop[4].ram.r_n_6 ,\ramloop[4].ram.r_n_7 }),
.\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_2 (\ramloop[5].ram.r_n_16 ),
.\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_3 (\ramloop[6].ram.r_n_16 ),
.\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_4 (\ramloop[4].ram.r_n_16 ),
.DOADO({\ramloop[7].ram.r_n_0 ,\ramloop[7].ram.r_n_1 ,\ramloop[7].ram.r_n_2 ,\ramloop[7].ram.r_n_3 ,\ramloop[7].ram.r_n_4 ,\ramloop[7].ram.r_n_5 ,\ramloop[7].ram.r_n_6 ,\ramloop[7].ram.r_n_7 }),
.DOPADOP(\ramloop[7].ram.r_n_16 ),
.addra(addra[13:12]),
.clka(clka),
.douta(douta[15:7]),
.ena(ena));
system_vga_hessian_0_0_blk_mem_gen_mux__parameterized0 \has_mux_b.B
(.\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram ({\ramloop[5].ram.r_n_8 ,\ramloop[5].ram.r_n_9 ,\ramloop[5].ram.r_n_10 ,\ramloop[5].ram.r_n_11 ,\ramloop[5].ram.r_n_12 ,\ramloop[5].ram.r_n_13 ,\ramloop[5].ram.r_n_14 ,\ramloop[5].ram.r_n_15 }),
.\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0 ({\ramloop[6].ram.r_n_8 ,\ramloop[6].ram.r_n_9 ,\ramloop[6].ram.r_n_10 ,\ramloop[6].ram.r_n_11 ,\ramloop[6].ram.r_n_12 ,\ramloop[6].ram.r_n_13 ,\ramloop[6].ram.r_n_14 ,\ramloop[6].ram.r_n_15 }),
.\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1 ({\ramloop[4].ram.r_n_8 ,\ramloop[4].ram.r_n_9 ,\ramloop[4].ram.r_n_10 ,\ramloop[4].ram.r_n_11 ,\ramloop[4].ram.r_n_12 ,\ramloop[4].ram.r_n_13 ,\ramloop[4].ram.r_n_14 ,\ramloop[4].ram.r_n_15 }),
.\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_2 (\ramloop[5].ram.r_n_17 ),
.\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_3 (\ramloop[6].ram.r_n_17 ),
.\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_4 (\ramloop[4].ram.r_n_17 ),
.DOBDO({\ramloop[7].ram.r_n_8 ,\ramloop[7].ram.r_n_9 ,\ramloop[7].ram.r_n_10 ,\ramloop[7].ram.r_n_11 ,\ramloop[7].ram.r_n_12 ,\ramloop[7].ram.r_n_13 ,\ramloop[7].ram.r_n_14 ,\ramloop[7].ram.r_n_15 }),
.DOPBDOP(\ramloop[7].ram.r_n_17 ),
.addrb(addrb[13:12]),
.clkb(clkb),
.doutb(doutb[15:7]),
.enb(enb));
system_vga_hessian_0_0_blk_mem_gen_prim_width \ramloop[0].ram.r
(.addra(addra),
.addrb(addrb),
.clka(clka),
.clkb(clkb),
.dina(dina[0]),
.dinb(dinb[0]),
.douta(douta[0]),
.doutb(doutb[0]),
.ena(ena),
.enb(enb),
.wea(wea),
.web(web));
system_vga_hessian_0_0_blk_mem_gen_prim_width__parameterized0 \ramloop[1].ram.r
(.addra(addra),
.addrb(addrb),
.clka(clka),
.clkb(clkb),
.dina(dina[2:1]),
.dinb(dinb[2:1]),
.douta(douta[2:1]),
.doutb(doutb[2:1]),
.ena(ena),
.enb(enb),
.wea(wea),
.web(web));
system_vga_hessian_0_0_blk_mem_gen_prim_width__parameterized1 \ramloop[2].ram.r
(.addra(addra),
.addrb(addrb),
.clka(clka),
.clkb(clkb),
.dina(dina[4:3]),
.dinb(dinb[4:3]),
.douta(douta[4:3]),
.doutb(doutb[4:3]),
.ena(ena),
.enb(enb),
.wea(wea),
.web(web));
system_vga_hessian_0_0_blk_mem_gen_prim_width__parameterized2 \ramloop[3].ram.r
(.addra(addra),
.addrb(addrb),
.clka(clka),
.clkb(clkb),
.dina(dina[6:5]),
.dinb(dinb[6:5]),
.douta(douta[6:5]),
.doutb(doutb[6:5]),
.ena(ena),
.enb(enb),
.wea(wea),
.web(web));
system_vga_hessian_0_0_blk_mem_gen_prim_width__parameterized3 \ramloop[4].ram.r
(.addra(addra[11:0]),
.addrb(addrb[11:0]),
.\bottom_left_0_reg[14] ({\ramloop[4].ram.r_n_0 ,\ramloop[4].ram.r_n_1 ,\ramloop[4].ram.r_n_2 ,\ramloop[4].ram.r_n_3 ,\ramloop[4].ram.r_n_4 ,\ramloop[4].ram.r_n_5 ,\ramloop[4].ram.r_n_6 ,\ramloop[4].ram.r_n_7 }),
.\bottom_left_0_reg[15] (\ramloop[4].ram.r_n_16 ),
.clka(clka),
.clkb(clkb),
.dina(dina[15:7]),
.dinb(dinb[15:7]),
.ena(ena),
.ena_array(ena_array[0]),
.enb(enb),
.enb_array(enb_array[0]),
.\top_right_1_reg[14] ({\ramloop[4].ram.r_n_8 ,\ramloop[4].ram.r_n_9 ,\ramloop[4].ram.r_n_10 ,\ramloop[4].ram.r_n_11 ,\ramloop[4].ram.r_n_12 ,\ramloop[4].ram.r_n_13 ,\ramloop[4].ram.r_n_14 ,\ramloop[4].ram.r_n_15 }),
.\top_right_1_reg[15] (\ramloop[4].ram.r_n_17 ),
.wea(wea),
.web(web));
system_vga_hessian_0_0_blk_mem_gen_prim_width__parameterized4 \ramloop[5].ram.r
(.addra(addra[11:0]),
.addrb(addrb[11:0]),
.\bottom_left_0_reg[14] ({\ramloop[5].ram.r_n_0 ,\ramloop[5].ram.r_n_1 ,\ramloop[5].ram.r_n_2 ,\ramloop[5].ram.r_n_3 ,\ramloop[5].ram.r_n_4 ,\ramloop[5].ram.r_n_5 ,\ramloop[5].ram.r_n_6 ,\ramloop[5].ram.r_n_7 }),
.\bottom_left_0_reg[15] (\ramloop[5].ram.r_n_16 ),
.clka(clka),
.clkb(clkb),
.dina(dina[15:7]),
.dinb(dinb[15:7]),
.ena(ena),
.ena_array(ena_array[1]),
.enb(enb),
.enb_array(enb_array[1]),
.\top_right_1_reg[14] ({\ramloop[5].ram.r_n_8 ,\ramloop[5].ram.r_n_9 ,\ramloop[5].ram.r_n_10 ,\ramloop[5].ram.r_n_11 ,\ramloop[5].ram.r_n_12 ,\ramloop[5].ram.r_n_13 ,\ramloop[5].ram.r_n_14 ,\ramloop[5].ram.r_n_15 }),
.\top_right_1_reg[15] (\ramloop[5].ram.r_n_17 ),
.wea(wea),
.web(web));
system_vga_hessian_0_0_blk_mem_gen_prim_width__parameterized5 \ramloop[6].ram.r
(.addra(addra[11:0]),
.addrb(addrb[11:0]),
.\bottom_left_0_reg[14] ({\ramloop[6].ram.r_n_0 ,\ramloop[6].ram.r_n_1 ,\ramloop[6].ram.r_n_2 ,\ramloop[6].ram.r_n_3 ,\ramloop[6].ram.r_n_4 ,\ramloop[6].ram.r_n_5 ,\ramloop[6].ram.r_n_6 ,\ramloop[6].ram.r_n_7 }),
.\bottom_left_0_reg[15] (\ramloop[6].ram.r_n_16 ),
.clka(clka),
.clkb(clkb),
.dina(dina[15:7]),
.dinb(dinb[15:7]),
.ena(ena),
.ena_array(ena_array[2]),
.enb(enb),
.enb_array(enb_array[2]),
.\top_right_1_reg[14] ({\ramloop[6].ram.r_n_8 ,\ramloop[6].ram.r_n_9 ,\ramloop[6].ram.r_n_10 ,\ramloop[6].ram.r_n_11 ,\ramloop[6].ram.r_n_12 ,\ramloop[6].ram.r_n_13 ,\ramloop[6].ram.r_n_14 ,\ramloop[6].ram.r_n_15 }),
.\top_right_1_reg[15] (\ramloop[6].ram.r_n_17 ),
.wea(wea),
.web(web));
system_vga_hessian_0_0_blk_mem_gen_prim_width__parameterized6 \ramloop[7].ram.r
(.DOADO({\ramloop[7].ram.r_n_0 ,\ramloop[7].ram.r_n_1 ,\ramloop[7].ram.r_n_2 ,\ramloop[7].ram.r_n_3 ,\ramloop[7].ram.r_n_4 ,\ramloop[7].ram.r_n_5 ,\ramloop[7].ram.r_n_6 ,\ramloop[7].ram.r_n_7 }),
.DOBDO({\ramloop[7].ram.r_n_8 ,\ramloop[7].ram.r_n_9 ,\ramloop[7].ram.r_n_10 ,\ramloop[7].ram.r_n_11 ,\ramloop[7].ram.r_n_12 ,\ramloop[7].ram.r_n_13 ,\ramloop[7].ram.r_n_14 ,\ramloop[7].ram.r_n_15 }),
.DOPADOP(\ramloop[7].ram.r_n_16 ),
.DOPBDOP(\ramloop[7].ram.r_n_17 ),
.addra(addra),
.addrb(addrb),
.clka(clka),
.clkb(clkb),
.dina(dina[15:7]),
.dinb(dinb[15:7]),
.ena(ena),
.enb(enb),
.wea(wea),
.web(web));
endmodule
|
module system_vga_hessian_0_0_blk_mem_gen_mux
(douta,
ena,
addra,
clka,
DOADO,
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram ,
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0 ,
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1 ,
DOPADOP,
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_2 ,
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_3 ,
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_4 );
output [8:0]douta;
input ena;
input [1:0]addra;
input clka;
input [7:0]DOADO;
input [7:0]\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram ;
input [7:0]\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0 ;
input [7:0]\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1 ;
input [0:0]DOPADOP;
input [0:0]\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_2 ;
input [0:0]\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_3 ;
input [0:0]\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_4 ;
wire [7:0]\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram ;
wire [7:0]\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0 ;
wire [7:0]\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1 ;
wire [0:0]\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_2 ;
wire [0:0]\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_3 ;
wire [0:0]\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_4 ;
wire [7:0]DOADO;
wire [0:0]DOPADOP;
wire [1:0]addra;
wire clka;
wire [8:0]douta;
wire ena;
wire [1:0]sel_pipe;
wire [1:0]sel_pipe_d1;
LUT6 #(
.INIT(64'hAACCAACCF0FFF000))
\douta[10]_INST_0
(.I0(DOADO[3]),
.I1(\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram [3]),
.I2(\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0 [3]),
.I3(sel_pipe_d1[1]),
.I4(\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1 [3]),
.I5(sel_pipe_d1[0]),
.O(douta[3]));
LUT6 #(
.INIT(64'hAACCAACCF0FFF000))
\douta[11]_INST_0
(.I0(DOADO[4]),
.I1(\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram [4]),
.I2(\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0 [4]),
.I3(sel_pipe_d1[1]),
.I4(\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1 [4]),
.I5(sel_pipe_d1[0]),
.O(douta[4]));
LUT6 #(
.INIT(64'hAACCAACCF0FFF000))
\douta[12]_INST_0
(.I0(DOADO[5]),
.I1(\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram [5]),
.I2(\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0 [5]),
.I3(sel_pipe_d1[1]),
.I4(\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1 [5]),
.I5(sel_pipe_d1[0]),
.O(douta[5]));
LUT6 #(
.INIT(64'hAACCAACCF0FFF000))
\douta[13]_INST_0
(.I0(DOADO[6]),
.I1(\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram [6]),
.I2(\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0 [6]),
.I3(sel_pipe_d1[1]),
.I4(\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1 [6]),
.I5(sel_pipe_d1[0]),
.O(douta[6]));
LUT6 #(
.INIT(64'hAACCAACCF0FFF000))
\douta[14]_INST_0
(.I0(DOADO[7]),
.I1(\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram [7]),
.I2(\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0 [7]),
.I3(sel_pipe_d1[1]),
.I4(\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1 [7]),
.I5(sel_pipe_d1[0]),
.O(douta[7]));
LUT6 #(
.INIT(64'hAACCAACCF0FFF000))
\douta[15]_INST_0
(.I0(DOPADOP),
.I1(\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_2 ),
.I2(\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_3 ),
.I3(sel_pipe_d1[1]),
.I4(\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_4 ),
.I5(sel_pipe_d1[0]),
.O(douta[8]));
LUT6 #(
.INIT(64'hAACCAACCF0FFF000))
\douta[7]_INST_0
(.I0(DOADO[0]),
.I1(\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram [0]),
.I2(\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0 [0]),
.I3(sel_pipe_d1[1]),
.I4(\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1 [0]),
.I5(sel_pipe_d1[0]),
.O(douta[0]));
LUT6 #(
.INIT(64'hAACCAACCF0FFF000))
\douta[8]_INST_0
(.I0(DOADO[1]),
.I1(\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram [1]),
.I2(\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0 [1]),
.I3(sel_pipe_d1[1]),
.I4(\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1 [1]),
.I5(sel_pipe_d1[0]),
.O(douta[1]));
LUT6 #(
.INIT(64'hAACCAACCF0FFF000))
\douta[9]_INST_0
(.I0(DOADO[2]),
.I1(\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram [2]),
.I2(\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0 [2]),
.I3(sel_pipe_d1[1]),
.I4(\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1 [2]),
.I5(sel_pipe_d1[0]),
.O(douta[2]));
FDRE #(
.INIT(1'b0))
\no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg[0]
(.C(clka),
.CE(ena),
.D(sel_pipe[0]),
.Q(sel_pipe_d1[0]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg[1]
(.C(clka),
.CE(ena),
.D(sel_pipe[1]),
.Q(sel_pipe_d1[1]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\no_softecc_sel_reg.ce_pri.sel_pipe_reg[0]
(.C(clka),
.CE(ena),
.D(addra[0]),
.Q(sel_pipe[0]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\no_softecc_sel_reg.ce_pri.sel_pipe_reg[1]
(.C(clka),
.CE(ena),
.D(addra[1]),
.Q(sel_pipe[1]),
.R(1'b0));
endmodule
|
module system_vga_hessian_0_0_blk_mem_gen_mux__parameterized0
(doutb,
enb,
addrb,
clkb,
DOBDO,
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram ,
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0 ,
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1 ,
DOPBDOP,
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_2 ,
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_3 ,
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_4 );
output [8:0]doutb;
input enb;
input [1:0]addrb;
input clkb;
input [7:0]DOBDO;
input [7:0]\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram ;
input [7:0]\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0 ;
input [7:0]\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1 ;
input [0:0]DOPBDOP;
input [0:0]\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_2 ;
input [0:0]\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_3 ;
input [0:0]\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_4 ;
wire [7:0]\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram ;
wire [7:0]\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0 ;
wire [7:0]\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1 ;
wire [0:0]\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_2 ;
wire [0:0]\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_3 ;
wire [0:0]\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_4 ;
wire [7:0]DOBDO;
wire [0:0]DOPBDOP;
wire [1:0]addrb;
wire clkb;
wire [8:0]doutb;
wire enb;
wire \no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg_n_0_[0] ;
wire \no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg_n_0_[1] ;
wire \no_softecc_sel_reg.ce_pri.sel_pipe_reg_n_0_[0] ;
wire \no_softecc_sel_reg.ce_pri.sel_pipe_reg_n_0_[1] ;
LUT6 #(
.INIT(64'hAACCAACCF0FFF000))
\doutb[10]_INST_0
(.I0(DOBDO[3]),
.I1(\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram [3]),
.I2(\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0 [3]),
.I3(\no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg_n_0_[1] ),
.I4(\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1 [3]),
.I5(\no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg_n_0_[0] ),
.O(doutb[3]));
LUT6 #(
.INIT(64'hAACCAACCF0FFF000))
\doutb[11]_INST_0
(.I0(DOBDO[4]),
.I1(\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram [4]),
.I2(\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0 [4]),
.I3(\no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg_n_0_[1] ),
.I4(\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1 [4]),
.I5(\no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg_n_0_[0] ),
.O(doutb[4]));
LUT6 #(
.INIT(64'hAACCAACCF0FFF000))
\doutb[12]_INST_0
(.I0(DOBDO[5]),
.I1(\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram [5]),
.I2(\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0 [5]),
.I3(\no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg_n_0_[1] ),
.I4(\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1 [5]),
.I5(\no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg_n_0_[0] ),
.O(doutb[5]));
LUT6 #(
.INIT(64'hAACCAACCF0FFF000))
\doutb[13]_INST_0
(.I0(DOBDO[6]),
.I1(\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram [6]),
.I2(\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0 [6]),
.I3(\no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg_n_0_[1] ),
.I4(\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1 [6]),
.I5(\no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg_n_0_[0] ),
.O(doutb[6]));
LUT6 #(
.INIT(64'hAACCAACCF0FFF000))
\doutb[14]_INST_0
(.I0(DOBDO[7]),
.I1(\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram [7]),
.I2(\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0 [7]),
.I3(\no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg_n_0_[1] ),
.I4(\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1 [7]),
.I5(\no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg_n_0_[0] ),
.O(doutb[7]));
LUT6 #(
.INIT(64'hAACCAACCF0FFF000))
\doutb[15]_INST_0
(.I0(DOPBDOP),
.I1(\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_2 ),
.I2(\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_3 ),
.I3(\no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg_n_0_[1] ),
.I4(\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_4 ),
.I5(\no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg_n_0_[0] ),
.O(doutb[8]));
LUT6 #(
.INIT(64'hAACCAACCF0FFF000))
\doutb[7]_INST_0
(.I0(DOBDO[0]),
.I1(\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram [0]),
.I2(\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0 [0]),
.I3(\no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg_n_0_[1] ),
.I4(\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1 [0]),
.I5(\no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg_n_0_[0] ),
.O(doutb[0]));
LUT6 #(
.INIT(64'hAACCAACCF0FFF000))
\doutb[8]_INST_0
(.I0(DOBDO[1]),
.I1(\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram [1]),
.I2(\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0 [1]),
.I3(\no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg_n_0_[1] ),
.I4(\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1 [1]),
.I5(\no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg_n_0_[0] ),
.O(doutb[1]));
LUT6 #(
.INIT(64'hAACCAACCF0FFF000))
\doutb[9]_INST_0
(.I0(DOBDO[2]),
.I1(\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram [2]),
.I2(\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0 [2]),
.I3(\no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg_n_0_[1] ),
.I4(\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_1 [2]),
.I5(\no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg_n_0_[0] ),
.O(doutb[2]));
FDRE #(
.INIT(1'b0))
\no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg[0]
(.C(clkb),
.CE(enb),
.D(\no_softecc_sel_reg.ce_pri.sel_pipe_reg_n_0_[0] ),
.Q(\no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg_n_0_[0] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg[1]
(.C(clkb),
.CE(enb),
.D(\no_softecc_sel_reg.ce_pri.sel_pipe_reg_n_0_[1] ),
.Q(\no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg_n_0_[1] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\no_softecc_sel_reg.ce_pri.sel_pipe_reg[0]
(.C(clkb),
.CE(enb),
.D(addrb[0]),
.Q(\no_softecc_sel_reg.ce_pri.sel_pipe_reg_n_0_[0] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\no_softecc_sel_reg.ce_pri.sel_pipe_reg[1]
(.C(clkb),
.CE(enb),
.D(addrb[1]),
.Q(\no_softecc_sel_reg.ce_pri.sel_pipe_reg_n_0_[1] ),
.R(1'b0));
endmodule
|
module system_vga_hessian_0_0_blk_mem_gen_prim_width
(douta,
doutb,
clka,
clkb,
ena,
enb,
addra,
addrb,
dina,
dinb,
wea,
web);
output [0:0]douta;
output [0:0]doutb;
input clka;
input clkb;
input ena;
input enb;
input [13:0]addra;
input [13:0]addrb;
input [0:0]dina;
input [0:0]dinb;
input [0:0]wea;
input [0:0]web;
wire [13:0]addra;
wire [13:0]addrb;
wire clka;
wire clkb;
wire [0:0]dina;
wire [0:0]dinb;
wire [0:0]douta;
wire [0:0]doutb;
wire ena;
wire enb;
wire [0:0]wea;
wire [0:0]web;
system_vga_hessian_0_0_blk_mem_gen_prim_wrapper \prim_noinit.ram
(.addra(addra),
.addrb(addrb),
.clka(clka),
.clkb(clkb),
.dina(dina),
.dinb(dinb),
.douta(douta),
.doutb(doutb),
.ena(ena),
.enb(enb),
.wea(wea),
.web(web));
endmodule
|
module system_vga_hessian_0_0_blk_mem_gen_prim_width__parameterized0
(douta,
doutb,
clka,
clkb,
ena,
enb,
addra,
addrb,
dina,
dinb,
wea,
web);
output [1:0]douta;
output [1:0]doutb;
input clka;
input clkb;
input ena;
input enb;
input [13:0]addra;
input [13:0]addrb;
input [1:0]dina;
input [1:0]dinb;
input [0:0]wea;
input [0:0]web;
wire [13:0]addra;
wire [13:0]addrb;
wire clka;
wire clkb;
wire [1:0]dina;
wire [1:0]dinb;
wire [1:0]douta;
wire [1:0]doutb;
wire ena;
wire enb;
wire [0:0]wea;
wire [0:0]web;
system_vga_hessian_0_0_blk_mem_gen_prim_wrapper__parameterized0 \prim_noinit.ram
(.addra(addra),
.addrb(addrb),
.clka(clka),
.clkb(clkb),
.dina(dina),
.dinb(dinb),
.douta(douta),
.doutb(doutb),
.ena(ena),
.enb(enb),
.wea(wea),
.web(web));
endmodule
|
module system_vga_hessian_0_0_blk_mem_gen_prim_width__parameterized1
(douta,
doutb,
clka,
clkb,
ena,
enb,
addra,
addrb,
dina,
dinb,
wea,
web);
output [1:0]douta;
output [1:0]doutb;
input clka;
input clkb;
input ena;
input enb;
input [13:0]addra;
input [13:0]addrb;
input [1:0]dina;
input [1:0]dinb;
input [0:0]wea;
input [0:0]web;
wire [13:0]addra;
wire [13:0]addrb;
wire clka;
wire clkb;
wire [1:0]dina;
wire [1:0]dinb;
wire [1:0]douta;
wire [1:0]doutb;
wire ena;
wire enb;
wire [0:0]wea;
wire [0:0]web;
system_vga_hessian_0_0_blk_mem_gen_prim_wrapper__parameterized1 \prim_noinit.ram
(.addra(addra),
.addrb(addrb),
.clka(clka),
.clkb(clkb),
.dina(dina),
.dinb(dinb),
.douta(douta),
.doutb(doutb),
.ena(ena),
.enb(enb),
.wea(wea),
.web(web));
endmodule
|
module system_vga_hessian_0_0_blk_mem_gen_prim_width__parameterized2
(douta,
doutb,
clka,
clkb,
ena,
enb,
addra,
addrb,
dina,
dinb,
wea,
web);
output [1:0]douta;
output [1:0]doutb;
input clka;
input clkb;
input ena;
input enb;
input [13:0]addra;
input [13:0]addrb;
input [1:0]dina;
input [1:0]dinb;
input [0:0]wea;
input [0:0]web;
wire [13:0]addra;
wire [13:0]addrb;
wire clka;
wire clkb;
wire [1:0]dina;
wire [1:0]dinb;
wire [1:0]douta;
wire [1:0]doutb;
wire ena;
wire enb;
wire [0:0]wea;
wire [0:0]web;
system_vga_hessian_0_0_blk_mem_gen_prim_wrapper__parameterized2 \prim_noinit.ram
(.addra(addra),
.addrb(addrb),
.clka(clka),
.clkb(clkb),
.dina(dina),
.dinb(dinb),
.douta(douta),
.doutb(doutb),
.ena(ena),
.enb(enb),
.wea(wea),
.web(web));
endmodule
|
module system_vga_hessian_0_0_blk_mem_gen_prim_width__parameterized3
(\bottom_left_0_reg[14] ,
\top_right_1_reg[14] ,
\bottom_left_0_reg[15] ,
\top_right_1_reg[15] ,
clka,
clkb,
ena_array,
enb_array,
ena,
enb,
addra,
addrb,
dina,
dinb,
wea,
web);
output [7:0]\bottom_left_0_reg[14] ;
output [7:0]\top_right_1_reg[14] ;
output [0:0]\bottom_left_0_reg[15] ;
output [0:0]\top_right_1_reg[15] ;
input clka;
input clkb;
input [0:0]ena_array;
input [0:0]enb_array;
input ena;
input enb;
input [11:0]addra;
input [11:0]addrb;
input [8:0]dina;
input [8:0]dinb;
input [0:0]wea;
input [0:0]web;
wire [11:0]addra;
wire [11:0]addrb;
wire [7:0]\bottom_left_0_reg[14] ;
wire [0:0]\bottom_left_0_reg[15] ;
wire clka;
wire clkb;
wire [8:0]dina;
wire [8:0]dinb;
wire ena;
wire [0:0]ena_array;
wire enb;
wire [0:0]enb_array;
wire [7:0]\top_right_1_reg[14] ;
wire [0:0]\top_right_1_reg[15] ;
wire [0:0]wea;
wire [0:0]web;
system_vga_hessian_0_0_blk_mem_gen_prim_wrapper__parameterized3 \prim_noinit.ram
(.addra(addra),
.addrb(addrb),
.\bottom_left_0_reg[14] (\bottom_left_0_reg[14] ),
.\bottom_left_0_reg[15] (\bottom_left_0_reg[15] ),
.clka(clka),
.clkb(clkb),
.dina(dina),
.dinb(dinb),
.ena(ena),
.ena_array(ena_array),
.enb(enb),
.enb_array(enb_array),
.\top_right_1_reg[14] (\top_right_1_reg[14] ),
.\top_right_1_reg[15] (\top_right_1_reg[15] ),
.wea(wea),
.web(web));
endmodule
|
module system_vga_hessian_0_0_blk_mem_gen_prim_width__parameterized4
(\bottom_left_0_reg[14] ,
\top_right_1_reg[14] ,
\bottom_left_0_reg[15] ,
\top_right_1_reg[15] ,
clka,
clkb,
ena_array,
enb_array,
ena,
enb,
addra,
addrb,
dina,
dinb,
wea,
web);
output [7:0]\bottom_left_0_reg[14] ;
output [7:0]\top_right_1_reg[14] ;
output [0:0]\bottom_left_0_reg[15] ;
output [0:0]\top_right_1_reg[15] ;
input clka;
input clkb;
input [0:0]ena_array;
input [0:0]enb_array;
input ena;
input enb;
input [11:0]addra;
input [11:0]addrb;
input [8:0]dina;
input [8:0]dinb;
input [0:0]wea;
input [0:0]web;
wire [11:0]addra;
wire [11:0]addrb;
wire [7:0]\bottom_left_0_reg[14] ;
wire [0:0]\bottom_left_0_reg[15] ;
wire clka;
wire clkb;
wire [8:0]dina;
wire [8:0]dinb;
wire ena;
wire [0:0]ena_array;
wire enb;
wire [0:0]enb_array;
wire [7:0]\top_right_1_reg[14] ;
wire [0:0]\top_right_1_reg[15] ;
wire [0:0]wea;
wire [0:0]web;
system_vga_hessian_0_0_blk_mem_gen_prim_wrapper__parameterized4 \prim_noinit.ram
(.addra(addra),
.addrb(addrb),
.\bottom_left_0_reg[14] (\bottom_left_0_reg[14] ),
.\bottom_left_0_reg[15] (\bottom_left_0_reg[15] ),
.clka(clka),
.clkb(clkb),
.dina(dina),
.dinb(dinb),
.ena(ena),
.ena_array(ena_array),
.enb(enb),
.enb_array(enb_array),
.\top_right_1_reg[14] (\top_right_1_reg[14] ),
.\top_right_1_reg[15] (\top_right_1_reg[15] ),
.wea(wea),
.web(web));
endmodule
|
module system_vga_hessian_0_0_blk_mem_gen_prim_width__parameterized5
(\bottom_left_0_reg[14] ,
\top_right_1_reg[14] ,
\bottom_left_0_reg[15] ,
\top_right_1_reg[15] ,
clka,
clkb,
ena_array,
enb_array,
ena,
enb,
addra,
addrb,
dina,
dinb,
wea,
web);
output [7:0]\bottom_left_0_reg[14] ;
output [7:0]\top_right_1_reg[14] ;
output [0:0]\bottom_left_0_reg[15] ;
output [0:0]\top_right_1_reg[15] ;
input clka;
input clkb;
input [0:0]ena_array;
input [0:0]enb_array;
input ena;
input enb;
input [11:0]addra;
input [11:0]addrb;
input [8:0]dina;
input [8:0]dinb;
input [0:0]wea;
input [0:0]web;
wire [11:0]addra;
wire [11:0]addrb;
wire [7:0]\bottom_left_0_reg[14] ;
wire [0:0]\bottom_left_0_reg[15] ;
wire clka;
wire clkb;
wire [8:0]dina;
wire [8:0]dinb;
wire ena;
wire [0:0]ena_array;
wire enb;
wire [0:0]enb_array;
wire [7:0]\top_right_1_reg[14] ;
wire [0:0]\top_right_1_reg[15] ;
wire [0:0]wea;
wire [0:0]web;
system_vga_hessian_0_0_blk_mem_gen_prim_wrapper__parameterized5 \prim_noinit.ram
(.addra(addra),
.addrb(addrb),
.\bottom_left_0_reg[14] (\bottom_left_0_reg[14] ),
.\bottom_left_0_reg[15] (\bottom_left_0_reg[15] ),
.clka(clka),
.clkb(clkb),
.dina(dina),
.dinb(dinb),
.ena(ena),
.ena_array(ena_array),
.enb(enb),
.enb_array(enb_array),
.\top_right_1_reg[14] (\top_right_1_reg[14] ),
.\top_right_1_reg[15] (\top_right_1_reg[15] ),
.wea(wea),
.web(web));
endmodule
|
module system_vga_hessian_0_0_blk_mem_gen_prim_width__parameterized6
(DOADO,
DOBDO,
DOPADOP,
DOPBDOP,
clka,
clkb,
ena,
enb,
addra,
addrb,
dina,
dinb,
wea,
web);
output [7:0]DOADO;
output [7:0]DOBDO;
output [0:0]DOPADOP;
output [0:0]DOPBDOP;
input clka;
input clkb;
input ena;
input enb;
input [13:0]addra;
input [13:0]addrb;
input [8:0]dina;
input [8:0]dinb;
input [0:0]wea;
input [0:0]web;
wire [7:0]DOADO;
wire [7:0]DOBDO;
wire [0:0]DOPADOP;
wire [0:0]DOPBDOP;
wire [13:0]addra;
wire [13:0]addrb;
wire clka;
wire clkb;
wire [8:0]dina;
wire [8:0]dinb;
wire ena;
wire enb;
wire [0:0]wea;
wire [0:0]web;
system_vga_hessian_0_0_blk_mem_gen_prim_wrapper__parameterized6 \prim_noinit.ram
(.DOADO(DOADO),
.DOBDO(DOBDO),
.DOPADOP(DOPADOP),
.DOPBDOP(DOPBDOP),
.addra(addra),
.addrb(addrb),
.clka(clka),
.clkb(clkb),
.dina(dina),
.dinb(dinb),
.ena(ena),
.enb(enb),
.wea(wea),
.web(web));
endmodule
|
module system_vga_hessian_0_0_blk_mem_gen_prim_wrapper
(douta,
doutb,
clka,
clkb,
ena,
enb,
addra,
addrb,
dina,
dinb,
wea,
web);
output [0:0]douta;
output [0:0]doutb;
input clka;
input clkb;
input ena;
input enb;
input [13:0]addra;
input [13:0]addrb;
input [0:0]dina;
input [0:0]dinb;
input [0:0]wea;
input [0:0]web;
wire [13:0]addra;
wire [13:0]addrb;
wire clka;
wire clkb;
wire [0:0]dina;
wire [0:0]dinb;
wire [0:0]douta;
wire [0:0]doutb;
wire ena;
wire enb;
wire [0:0]wea;
wire [0:0]web;
wire [15:1]\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram_DOADO_UNCONNECTED ;
wire [15:1]\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram_DOBDO_UNCONNECTED ;
wire [1:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram_DOPADOP_UNCONNECTED ;
wire [1:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram_DOPBDOP_UNCONNECTED ;
(* CLOCK_DOMAINS = "COMMON" *)
(* box_type = "PRIMITIVE" *)
RAMB18E1 #(
.DOA_REG(1),
.DOB_REG(1),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(18'h00000),
.INIT_B(18'h00000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
.READ_WIDTH_A(1),
.READ_WIDTH_B(1),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(18'h00000),
.SRVAL_B(18'h00000),
.WRITE_MODE_A("WRITE_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(1),
.WRITE_WIDTH_B(1))
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram
(.ADDRARDADDR(addra),
.ADDRBWRADDR(addrb),
.CLKARDCLK(clka),
.CLKBWRCLK(clkb),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,dina}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,dinb}),
.DIPADIP({1'b0,1'b0}),
.DIPBDIP({1'b0,1'b0}),
.DOADO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram_DOADO_UNCONNECTED [15:1],douta}),
.DOBDO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram_DOBDO_UNCONNECTED [15:1],doutb}),
.DOPADOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram_DOPADOP_UNCONNECTED [1:0]),
.DOPBDOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram_DOPBDOP_UNCONNECTED [1:0]),
.ENARDEN(ena),
.ENBWREN(enb),
.REGCEAREGCE(ena),
.REGCEB(enb),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.WEA({wea,wea}),
.WEBWE({1'b0,1'b0,web,web}));
endmodule
|
module system_vga_hessian_0_0_blk_mem_gen_prim_wrapper__parameterized0
(douta,
doutb,
clka,
clkb,
ena,
enb,
addra,
addrb,
dina,
dinb,
wea,
web);
output [1:0]douta;
output [1:0]doutb;
input clka;
input clkb;
input ena;
input enb;
input [13:0]addra;
input [13:0]addrb;
input [1:0]dina;
input [1:0]dinb;
input [0:0]wea;
input [0:0]web;
wire [13:0]addra;
wire [13:0]addrb;
wire clka;
wire clkb;
wire [1:0]dina;
wire [1:0]dinb;
wire [1:0]douta;
wire [1:0]doutb;
wire ena;
wire enb;
wire [0:0]wea;
wire [0:0]web;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;
wire [31:2]\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED ;
wire [31:2]\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;
(* CLOCK_DOMAINS = "COMMON" *)
(* box_type = "PRIMITIVE" *)
RAMB36E1 #(
.DOA_REG(1),
.DOB_REG(1),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
.READ_WIDTH_A(2),
.READ_WIDTH_B(2),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("WRITE_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(2),
.WRITE_WIDTH_B(2))
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram
(.ADDRARDADDR({1'b1,addra,1'b1}),
.ADDRBWRADDR({1'b1,addrb,1'b1}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(clka),
.CLKBWRCLK(clkb),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,dina}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,dinb}),
.DIPADIP({1'b0,1'b0,1'b0,1'b0}),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED [31:2],douta}),
.DOBDO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:2],doutb}),
.DOPADOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED [3:0]),
.DOPBDOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:0]),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(ena),
.ENBWREN(enb),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(ena),
.REGCEB(enb),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),
.WEA({wea,wea,wea,wea}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,web,web,web,web}));
endmodule
|
module system_vga_hessian_0_0_blk_mem_gen_prim_wrapper__parameterized1
(douta,
doutb,
clka,
clkb,
ena,
enb,
addra,
addrb,
dina,
dinb,
wea,
web);
output [1:0]douta;
output [1:0]doutb;
input clka;
input clkb;
input ena;
input enb;
input [13:0]addra;
input [13:0]addrb;
input [1:0]dina;
input [1:0]dinb;
input [0:0]wea;
input [0:0]web;
wire [13:0]addra;
wire [13:0]addrb;
wire clka;
wire clkb;
wire [1:0]dina;
wire [1:0]dinb;
wire [1:0]douta;
wire [1:0]doutb;
wire ena;
wire enb;
wire [0:0]wea;
wire [0:0]web;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;
wire [31:2]\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED ;
wire [31:2]\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;
(* CLOCK_DOMAINS = "COMMON" *)
(* box_type = "PRIMITIVE" *)
RAMB36E1 #(
.DOA_REG(1),
.DOB_REG(1),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
.READ_WIDTH_A(2),
.READ_WIDTH_B(2),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("WRITE_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(2),
.WRITE_WIDTH_B(2))
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram
(.ADDRARDADDR({1'b1,addra,1'b1}),
.ADDRBWRADDR({1'b1,addrb,1'b1}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(clka),
.CLKBWRCLK(clkb),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,dina}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,dinb}),
.DIPADIP({1'b0,1'b0,1'b0,1'b0}),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED [31:2],douta}),
.DOBDO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:2],doutb}),
.DOPADOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED [3:0]),
.DOPBDOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:0]),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(ena),
.ENBWREN(enb),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(ena),
.REGCEB(enb),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),
.WEA({wea,wea,wea,wea}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,web,web,web,web}));
endmodule
|
module system_vga_hessian_0_0_blk_mem_gen_prim_wrapper__parameterized2
(douta,
doutb,
clka,
clkb,
ena,
enb,
addra,
addrb,
dina,
dinb,
wea,
web);
output [1:0]douta;
output [1:0]doutb;
input clka;
input clkb;
input ena;
input enb;
input [13:0]addra;
input [13:0]addrb;
input [1:0]dina;
input [1:0]dinb;
input [0:0]wea;
input [0:0]web;
wire [13:0]addra;
wire [13:0]addrb;
wire clka;
wire clkb;
wire [1:0]dina;
wire [1:0]dinb;
wire [1:0]douta;
wire [1:0]doutb;
wire ena;
wire enb;
wire [0:0]wea;
wire [0:0]web;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;
wire [31:2]\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED ;
wire [31:2]\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;
(* CLOCK_DOMAINS = "COMMON" *)
(* box_type = "PRIMITIVE" *)
RAMB36E1 #(
.DOA_REG(1),
.DOB_REG(1),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
.READ_WIDTH_A(2),
.READ_WIDTH_B(2),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("WRITE_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(2),
.WRITE_WIDTH_B(2))
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram
(.ADDRARDADDR({1'b1,addra,1'b1}),
.ADDRBWRADDR({1'b1,addrb,1'b1}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(clka),
.CLKBWRCLK(clkb),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,dina}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,dinb}),
.DIPADIP({1'b0,1'b0,1'b0,1'b0}),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED [31:2],douta}),
.DOBDO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:2],doutb}),
.DOPADOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED [3:0]),
.DOPBDOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:0]),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(ena),
.ENBWREN(enb),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(ena),
.REGCEB(enb),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),
.WEA({wea,wea,wea,wea}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,web,web,web,web}));
endmodule
|
module system_vga_hessian_0_0_blk_mem_gen_prim_wrapper__parameterized3
(\bottom_left_0_reg[14] ,
\top_right_1_reg[14] ,
\bottom_left_0_reg[15] ,
\top_right_1_reg[15] ,
clka,
clkb,
ena_array,
enb_array,
ena,
enb,
addra,
addrb,
dina,
dinb,
wea,
web);
output [7:0]\bottom_left_0_reg[14] ;
output [7:0]\top_right_1_reg[14] ;
output [0:0]\bottom_left_0_reg[15] ;
output [0:0]\top_right_1_reg[15] ;
input clka;
input clkb;
input [0:0]ena_array;
input [0:0]enb_array;
input ena;
input enb;
input [11:0]addra;
input [11:0]addrb;
input [8:0]dina;
input [8:0]dinb;
input [0:0]wea;
input [0:0]web;
wire [11:0]addra;
wire [11:0]addrb;
wire [7:0]\bottom_left_0_reg[14] ;
wire [0:0]\bottom_left_0_reg[15] ;
wire clka;
wire clkb;
wire [8:0]dina;
wire [8:0]dinb;
wire ena;
wire [0:0]ena_array;
wire enb;
wire [0:0]enb_array;
wire [7:0]\top_right_1_reg[14] ;
wire [0:0]\top_right_1_reg[15] ;
wire [0:0]wea;
wire [0:0]web;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;
wire [31:8]\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED ;
wire [31:8]\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ;
wire [3:1]\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED ;
wire [3:1]\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;
(* CLOCK_DOMAINS = "COMMON" *)
(* box_type = "PRIMITIVE" *)
RAMB36E1 #(
.DOA_REG(1),
.DOB_REG(1),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
.READ_WIDTH_A(9),
.READ_WIDTH_B(9),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("WRITE_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(9),
.WRITE_WIDTH_B(9))
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram
(.ADDRARDADDR({1'b1,addra,1'b1,1'b1,1'b1}),
.ADDRBWRADDR({1'b1,addrb,1'b1,1'b1,1'b1}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(clka),
.CLKBWRCLK(clkb),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,dina[7:0]}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,dinb[7:0]}),
.DIPADIP({1'b0,1'b0,1'b0,dina[8]}),
.DIPBDIP({1'b0,1'b0,1'b0,dinb[8]}),
.DOADO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED [31:8],\bottom_left_0_reg[14] }),
.DOBDO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:8],\top_right_1_reg[14] }),
.DOPADOP({\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED [3:1],\bottom_left_0_reg[15] }),
.DOPBDOP({\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:1],\top_right_1_reg[15] }),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(ena_array),
.ENBWREN(enb_array),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(ena),
.REGCEB(enb),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),
.WEA({wea,wea,wea,wea}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,web,web,web,web}));
endmodule
|
module system_vga_hessian_0_0_blk_mem_gen_prim_wrapper__parameterized4
(\bottom_left_0_reg[14] ,
\top_right_1_reg[14] ,
\bottom_left_0_reg[15] ,
\top_right_1_reg[15] ,
clka,
clkb,
ena_array,
enb_array,
ena,
enb,
addra,
addrb,
dina,
dinb,
wea,
web);
output [7:0]\bottom_left_0_reg[14] ;
output [7:0]\top_right_1_reg[14] ;
output [0:0]\bottom_left_0_reg[15] ;
output [0:0]\top_right_1_reg[15] ;
input clka;
input clkb;
input [0:0]ena_array;
input [0:0]enb_array;
input ena;
input enb;
input [11:0]addra;
input [11:0]addrb;
input [8:0]dina;
input [8:0]dinb;
input [0:0]wea;
input [0:0]web;
wire [11:0]addra;
wire [11:0]addrb;
wire [7:0]\bottom_left_0_reg[14] ;
wire [0:0]\bottom_left_0_reg[15] ;
wire clka;
wire clkb;
wire [8:0]dina;
wire [8:0]dinb;
wire ena;
wire [0:0]ena_array;
wire enb;
wire [0:0]enb_array;
wire [7:0]\top_right_1_reg[14] ;
wire [0:0]\top_right_1_reg[15] ;
wire [0:0]wea;
wire [0:0]web;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;
wire [31:8]\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED ;
wire [31:8]\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ;
wire [3:1]\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED ;
wire [3:1]\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;
(* CLOCK_DOMAINS = "COMMON" *)
(* box_type = "PRIMITIVE" *)
RAMB36E1 #(
.DOA_REG(1),
.DOB_REG(1),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
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.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
.READ_WIDTH_A(9),
.READ_WIDTH_B(9),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("WRITE_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(9),
.WRITE_WIDTH_B(9))
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram
(.ADDRARDADDR({1'b1,addra,1'b1,1'b1,1'b1}),
.ADDRBWRADDR({1'b1,addrb,1'b1,1'b1,1'b1}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(clka),
.CLKBWRCLK(clkb),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,dina[7:0]}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,dinb[7:0]}),
.DIPADIP({1'b0,1'b0,1'b0,dina[8]}),
.DIPBDIP({1'b0,1'b0,1'b0,dinb[8]}),
.DOADO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED [31:8],\bottom_left_0_reg[14] }),
.DOBDO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:8],\top_right_1_reg[14] }),
.DOPADOP({\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED [3:1],\bottom_left_0_reg[15] }),
.DOPBDOP({\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:1],\top_right_1_reg[15] }),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(ena_array),
.ENBWREN(enb_array),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(ena),
.REGCEB(enb),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),
.WEA({wea,wea,wea,wea}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,web,web,web,web}));
endmodule
|
module system_vga_hessian_0_0_blk_mem_gen_prim_wrapper__parameterized5
(\bottom_left_0_reg[14] ,
\top_right_1_reg[14] ,
\bottom_left_0_reg[15] ,
\top_right_1_reg[15] ,
clka,
clkb,
ena_array,
enb_array,
ena,
enb,
addra,
addrb,
dina,
dinb,
wea,
web);
output [7:0]\bottom_left_0_reg[14] ;
output [7:0]\top_right_1_reg[14] ;
output [0:0]\bottom_left_0_reg[15] ;
output [0:0]\top_right_1_reg[15] ;
input clka;
input clkb;
input [0:0]ena_array;
input [0:0]enb_array;
input ena;
input enb;
input [11:0]addra;
input [11:0]addrb;
input [8:0]dina;
input [8:0]dinb;
input [0:0]wea;
input [0:0]web;
wire [11:0]addra;
wire [11:0]addrb;
wire [7:0]\bottom_left_0_reg[14] ;
wire [0:0]\bottom_left_0_reg[15] ;
wire clka;
wire clkb;
wire [8:0]dina;
wire [8:0]dinb;
wire ena;
wire [0:0]ena_array;
wire enb;
wire [0:0]enb_array;
wire [7:0]\top_right_1_reg[14] ;
wire [0:0]\top_right_1_reg[15] ;
wire [0:0]wea;
wire [0:0]web;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;
wire [31:8]\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED ;
wire [31:8]\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ;
wire [3:1]\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED ;
wire [3:1]\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;
(* CLOCK_DOMAINS = "COMMON" *)
(* box_type = "PRIMITIVE" *)
RAMB36E1 #(
.DOA_REG(1),
.DOB_REG(1),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
.READ_WIDTH_A(9),
.READ_WIDTH_B(9),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("WRITE_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(9),
.WRITE_WIDTH_B(9))
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram
(.ADDRARDADDR({1'b1,addra,1'b1,1'b1,1'b1}),
.ADDRBWRADDR({1'b1,addrb,1'b1,1'b1,1'b1}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(clka),
.CLKBWRCLK(clkb),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,dina[7:0]}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,dinb[7:0]}),
.DIPADIP({1'b0,1'b0,1'b0,dina[8]}),
.DIPBDIP({1'b0,1'b0,1'b0,dinb[8]}),
.DOADO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED [31:8],\bottom_left_0_reg[14] }),
.DOBDO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:8],\top_right_1_reg[14] }),
.DOPADOP({\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED [3:1],\bottom_left_0_reg[15] }),
.DOPBDOP({\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:1],\top_right_1_reg[15] }),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(ena_array),
.ENBWREN(enb_array),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(ena),
.REGCEB(enb),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),
.WEA({wea,wea,wea,wea}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,web,web,web,web}));
endmodule
|
module system_vga_hessian_0_0_blk_mem_gen_prim_wrapper__parameterized6
(DOADO,
DOBDO,
DOPADOP,
DOPBDOP,
clka,
clkb,
ena,
enb,
addra,
addrb,
dina,
dinb,
wea,
web);
output [7:0]DOADO;
output [7:0]DOBDO;
output [0:0]DOPADOP;
output [0:0]DOPBDOP;
input clka;
input clkb;
input ena;
input enb;
input [13:0]addra;
input [13:0]addrb;
input [8:0]dina;
input [8:0]dinb;
input [0:0]wea;
input [0:0]web;
wire \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_i_1_n_0 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_i_2_n_0 ;
wire [7:0]DOADO;
wire [7:0]DOBDO;
wire [0:0]DOPADOP;
wire [0:0]DOPBDOP;
wire [13:0]addra;
wire [13:0]addrb;
wire clka;
wire clkb;
wire [8:0]dina;
wire [8:0]dinb;
wire ena;
wire enb;
wire [0:0]wea;
wire [0:0]web;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;
wire [31:8]\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED ;
wire [31:8]\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ;
wire [3:1]\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED ;
wire [3:1]\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;
(* CLOCK_DOMAINS = "COMMON" *)
(* box_type = "PRIMITIVE" *)
RAMB36E1 #(
.DOA_REG(1),
.DOB_REG(1),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
.READ_WIDTH_A(9),
.READ_WIDTH_B(9),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("WRITE_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(9),
.WRITE_WIDTH_B(9))
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram
(.ADDRARDADDR({1'b1,addra[11:0],1'b1,1'b1,1'b1}),
.ADDRBWRADDR({1'b1,addrb[11:0],1'b1,1'b1,1'b1}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(clka),
.CLKBWRCLK(clkb),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,dina[7:0]}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,dinb[7:0]}),
.DIPADIP({1'b0,1'b0,1'b0,dina[8]}),
.DIPBDIP({1'b0,1'b0,1'b0,dinb[8]}),
.DOADO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED [31:8],DOADO}),
.DOBDO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:8],DOBDO}),
.DOPADOP({\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED [3:1],DOPADOP}),
.DOPBDOP({\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:1],DOPBDOP}),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_i_1_n_0 ),
.ENBWREN(\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_i_2_n_0 ),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(ena),
.REGCEB(enb),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),
.WEA({wea,wea,wea,wea}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,web,web,web,web}));
LUT3 #(
.INIT(8'h80))
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_i_1
(.I0(addra[13]),
.I1(addra[12]),
.I2(ena),
.O(\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_i_1_n_0 ));
LUT3 #(
.INIT(8'h80))
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_i_2
(.I0(addrb[13]),
.I1(addrb[12]),
.I2(enb),
.O(\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_i_2_n_0 ));
endmodule
|
module system_vga_hessian_0_0_blk_mem_gen_top
(douta,
doutb,
addra,
ena,
addrb,
enb,
clka,
clkb,
dina,
dinb,
wea,
web);
output [15:0]douta;
output [15:0]doutb;
input [13:0]addra;
input ena;
input [13:0]addrb;
input enb;
input clka;
input clkb;
input [15:0]dina;
input [15:0]dinb;
input [0:0]wea;
input [0:0]web;
wire [13:0]addra;
wire [13:0]addrb;
wire clka;
wire clkb;
wire [15:0]dina;
wire [15:0]dinb;
wire [15:0]douta;
wire [15:0]doutb;
wire ena;
wire enb;
wire [0:0]wea;
wire [0:0]web;
system_vga_hessian_0_0_blk_mem_gen_generic_cstr \valid.cstr
(.addra(addra),
.addrb(addrb),
.clka(clka),
.clkb(clkb),
.dina(dina),
.dinb(dinb),
.douta(douta),
.doutb(doutb),
.ena(ena),
.enb(enb),
.wea(wea),
.web(web));
endmodule
|
module system_vga_hessian_0_0_blk_mem_gen_v8_3_5
(clka,
rsta,
ena,
regcea,
wea,
addra,
dina,
douta,
clkb,
rstb,
enb,
regceb,
web,
addrb,
dinb,
doutb,
injectsbiterr,
injectdbiterr,
eccpipece,
sbiterr,
dbiterr,
rdaddrecc,
sleep,
deepsleep,
shutdown,
rsta_busy,
rstb_busy,
s_aclk,
s_aresetn,
s_axi_awid,
s_axi_awaddr,
s_axi_awlen,
s_axi_awsize,
s_axi_awburst,
s_axi_awvalid,
s_axi_awready,
s_axi_wdata,
s_axi_wstrb,
s_axi_wlast,
s_axi_wvalid,
s_axi_wready,
s_axi_bid,
s_axi_bresp,
s_axi_bvalid,
s_axi_bready,
s_axi_arid,
s_axi_araddr,
s_axi_arlen,
s_axi_arsize,
s_axi_arburst,
s_axi_arvalid,
s_axi_arready,
s_axi_rid,
s_axi_rdata,
s_axi_rresp,
s_axi_rlast,
s_axi_rvalid,
s_axi_rready,
s_axi_injectsbiterr,
s_axi_injectdbiterr,
s_axi_sbiterr,
s_axi_dbiterr,
s_axi_rdaddrecc);
input clka;
input rsta;
input ena;
input regcea;
input [0:0]wea;
input [13:0]addra;
input [15:0]dina;
output [15:0]douta;
input clkb;
input rstb;
input enb;
input regceb;
input [0:0]web;
input [13:0]addrb;
input [15:0]dinb;
output [15:0]doutb;
input injectsbiterr;
input injectdbiterr;
input eccpipece;
output sbiterr;
output dbiterr;
output [13:0]rdaddrecc;
input sleep;
input deepsleep;
input shutdown;
output rsta_busy;
output rstb_busy;
input s_aclk;
input s_aresetn;
input [3:0]s_axi_awid;
input [31:0]s_axi_awaddr;
input [7:0]s_axi_awlen;
input [2:0]s_axi_awsize;
input [1:0]s_axi_awburst;
input s_axi_awvalid;
output s_axi_awready;
input [15:0]s_axi_wdata;
input [0:0]s_axi_wstrb;
input s_axi_wlast;
input s_axi_wvalid;
output s_axi_wready;
output [3:0]s_axi_bid;
output [1:0]s_axi_bresp;
output s_axi_bvalid;
input s_axi_bready;
input [3:0]s_axi_arid;
input [31:0]s_axi_araddr;
input [7:0]s_axi_arlen;
input [2:0]s_axi_arsize;
input [1:0]s_axi_arburst;
input s_axi_arvalid;
output s_axi_arready;
output [3:0]s_axi_rid;
output [15:0]s_axi_rdata;
output [1:0]s_axi_rresp;
output s_axi_rlast;
output s_axi_rvalid;
input s_axi_rready;
input s_axi_injectsbiterr;
input s_axi_injectdbiterr;
output s_axi_sbiterr;
output s_axi_dbiterr;
output [13:0]s_axi_rdaddrecc;
wire \<const0> ;
wire [13:0]addra;
wire [13:0]addrb;
wire clka;
wire clkb;
wire [15:0]dina;
wire [15:0]dinb;
wire [15:0]douta;
wire [15:0]doutb;
wire ena;
wire enb;
wire [0:0]wea;
wire [0:0]web;
assign dbiterr = \<const0> ;
assign rdaddrecc[13] = \<const0> ;
assign rdaddrecc[12] = \<const0> ;
assign rdaddrecc[11] = \<const0> ;
assign rdaddrecc[10] = \<const0> ;
assign rdaddrecc[9] = \<const0> ;
assign rdaddrecc[8] = \<const0> ;
assign rdaddrecc[7] = \<const0> ;
assign rdaddrecc[6] = \<const0> ;
assign rdaddrecc[5] = \<const0> ;
assign rdaddrecc[4] = \<const0> ;
assign rdaddrecc[3] = \<const0> ;
assign rdaddrecc[2] = \<const0> ;
assign rdaddrecc[1] = \<const0> ;
assign rdaddrecc[0] = \<const0> ;
assign rsta_busy = \<const0> ;
assign rstb_busy = \<const0> ;
assign s_axi_arready = \<const0> ;
assign s_axi_awready = \<const0> ;
assign s_axi_bid[3] = \<const0> ;
assign s_axi_bid[2] = \<const0> ;
assign s_axi_bid[1] = \<const0> ;
assign s_axi_bid[0] = \<const0> ;
assign s_axi_bresp[1] = \<const0> ;
assign s_axi_bresp[0] = \<const0> ;
assign s_axi_bvalid = \<const0> ;
assign s_axi_dbiterr = \<const0> ;
assign s_axi_rdaddrecc[13] = \<const0> ;
assign s_axi_rdaddrecc[12] = \<const0> ;
assign s_axi_rdaddrecc[11] = \<const0> ;
assign s_axi_rdaddrecc[10] = \<const0> ;
assign s_axi_rdaddrecc[9] = \<const0> ;
assign s_axi_rdaddrecc[8] = \<const0> ;
assign s_axi_rdaddrecc[7] = \<const0> ;
assign s_axi_rdaddrecc[6] = \<const0> ;
assign s_axi_rdaddrecc[5] = \<const0> ;
assign s_axi_rdaddrecc[4] = \<const0> ;
assign s_axi_rdaddrecc[3] = \<const0> ;
assign s_axi_rdaddrecc[2] = \<const0> ;
assign s_axi_rdaddrecc[1] = \<const0> ;
assign s_axi_rdaddrecc[0] = \<const0> ;
assign s_axi_rdata[15] = \<const0> ;
assign s_axi_rdata[14] = \<const0> ;
assign s_axi_rdata[13] = \<const0> ;
assign s_axi_rdata[12] = \<const0> ;
assign s_axi_rdata[11] = \<const0> ;
assign s_axi_rdata[10] = \<const0> ;
assign s_axi_rdata[9] = \<const0> ;
assign s_axi_rdata[8] = \<const0> ;
assign s_axi_rdata[7] = \<const0> ;
assign s_axi_rdata[6] = \<const0> ;
assign s_axi_rdata[5] = \<const0> ;
assign s_axi_rdata[4] = \<const0> ;
assign s_axi_rdata[3] = \<const0> ;
assign s_axi_rdata[2] = \<const0> ;
assign s_axi_rdata[1] = \<const0> ;
assign s_axi_rdata[0] = \<const0> ;
assign s_axi_rid[3] = \<const0> ;
assign s_axi_rid[2] = \<const0> ;
assign s_axi_rid[1] = \<const0> ;
assign s_axi_rid[0] = \<const0> ;
assign s_axi_rlast = \<const0> ;
assign s_axi_rresp[1] = \<const0> ;
assign s_axi_rresp[0] = \<const0> ;
assign s_axi_rvalid = \<const0> ;
assign s_axi_sbiterr = \<const0> ;
assign s_axi_wready = \<const0> ;
assign sbiterr = \<const0> ;
GND GND
(.G(\<const0> ));
system_vga_hessian_0_0_blk_mem_gen_v8_3_5_synth inst_blk_mem_gen
(.addra(addra),
.addrb(addrb),
.clka(clka),
.clkb(clkb),
.dina(dina),
.dinb(dinb),
.douta(douta),
.doutb(doutb),
.ena(ena),
.enb(enb),
.wea(wea),
.web(web));
endmodule
|
module system_vga_hessian_0_0_blk_mem_gen_v8_3_5_synth
(douta,
doutb,
addra,
ena,
addrb,
enb,
clka,
clkb,
dina,
dinb,
wea,
web);
output [15:0]douta;
output [15:0]doutb;
input [13:0]addra;
input ena;
input [13:0]addrb;
input enb;
input clka;
input clkb;
input [15:0]dina;
input [15:0]dinb;
input [0:0]wea;
input [0:0]web;
wire [13:0]addra;
wire [13:0]addrb;
wire clka;
wire clkb;
wire [15:0]dina;
wire [15:0]dinb;
wire [15:0]douta;
wire [15:0]doutb;
wire ena;
wire enb;
wire [0:0]wea;
wire [0:0]web;
system_vga_hessian_0_0_blk_mem_gen_top \gnbram.gnativebmg.native_blk_mem_gen
(.addra(addra),
.addrb(addrb),
.clka(clka),
.clkb(clkb),
.dina(dina),
.dinb(dinb),
.douta(douta),
.doutb(doutb),
.ena(ena),
.enb(enb),
.wea(wea),
.web(web));
endmodule
|
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
|
module UART_v2_30_0 (
rx_clk,
rx_data,
tx_clk,
tx_data,
rx_interrupt,
tx_interrupt,
tx,
tx_en,
rts_n,
reset,
cts_n,
clock,
rx);
output rx_clk;
output rx_data;
output tx_clk;
output tx_data;
output rx_interrupt;
output tx_interrupt;
output tx;
output tx_en;
output rts_n;
input reset;
input cts_n;
input clock;
input rx;
parameter Address1 = 0;
parameter Address2 = 0;
parameter EnIntRXInterrupt = 0;
parameter EnIntTXInterrupt = 0;
parameter FlowControl = 0;
parameter HalfDuplexEn = 0;
parameter HwTXEnSignal = 1;
parameter NumDataBits = 8;
parameter NumStopBits = 1;
parameter ParityType = 0;
parameter RXEnable = 1;
parameter TXEnable = 0;
wire Net_289;
wire Net_61;
wire Net_9;
cy_clock_v1_0
#(.id("b0162966-0060-4af5-82d1-fcb491ad7619/be0a0e37-ad17-42ca-b5a1-1a654d736358"),
.source_clock_id(""),
.divisor(0),
.period("104166666666.667"),
.is_direct(0),
.is_digital(1))
IntClock
(.clock_out(Net_9));
// VirtualMux_1 (cy_virtualmux_v1_0)
assign Net_61 = Net_9;
B_UART_v2_30 BUART (
.cts_n(cts_n),
.tx(tx),
.rts_n(rts_n),
.tx_en(tx_en),
.clock(Net_61),
.reset(reset),
.rx(rx),
.tx_interrupt(tx_interrupt),
.rx_interrupt(rx_interrupt),
.tx_data(tx_data),
.tx_clk(tx_clk),
.rx_data(rx_data),
.rx_clk(rx_clk));
defparam BUART.Address1 = 0;
defparam BUART.Address2 = 0;
defparam BUART.BreakBitsRX = 13;
defparam BUART.BreakBitsTX = 13;
defparam BUART.BreakDetect = 0;
defparam BUART.CRCoutputsEn = 0;
defparam BUART.FlowControl = 0;
defparam BUART.HalfDuplexEn = 0;
defparam BUART.HwTXEnSignal = 1;
defparam BUART.NumDataBits = 8;
defparam BUART.NumStopBits = 1;
defparam BUART.OverSampleCount = 8;
defparam BUART.ParityType = 0;
defparam BUART.ParityTypeSw = 0;
defparam BUART.RXAddressMode = 0;
defparam BUART.RXEnable = 1;
defparam BUART.RXStatusIntEnable = 1;
defparam BUART.TXBitClkGenDP = 1;
defparam BUART.TXEnable = 0;
defparam BUART.Use23Polling = 1;
endmodule
|
module UART_v2_30_1 (
rx_clk,
rx_data,
tx_clk,
tx_data,
rx_interrupt,
tx_interrupt,
tx,
tx_en,
rts_n,
reset,
cts_n,
clock,
rx);
output rx_clk;
output rx_data;
output tx_clk;
output tx_data;
output rx_interrupt;
output tx_interrupt;
output tx;
output tx_en;
output rts_n;
input reset;
input cts_n;
input clock;
input rx;
parameter Address1 = 0;
parameter Address2 = 0;
parameter EnIntRXInterrupt = 0;
parameter EnIntTXInterrupt = 0;
parameter FlowControl = 0;
parameter HalfDuplexEn = 0;
parameter HwTXEnSignal = 1;
parameter NumDataBits = 8;
parameter NumStopBits = 1;
parameter ParityType = 0;
parameter RXEnable = 1;
parameter TXEnable = 0;
wire Net_289;
wire Net_61;
wire Net_9;
cy_clock_v1_0
#(.id("cdcc95c5-960c-4c98-bdc1-3ae892f46451/be0a0e37-ad17-42ca-b5a1-1a654d736358"),
.source_clock_id(""),
.divisor(0),
.period("13020833333.3333"),
.is_direct(0),
.is_digital(1))
IntClock
(.clock_out(Net_9));
// VirtualMux_1 (cy_virtualmux_v1_0)
assign Net_61 = Net_9;
B_UART_v2_30 BUART (
.cts_n(cts_n),
.tx(tx),
.rts_n(rts_n),
.tx_en(tx_en),
.clock(Net_61),
.reset(reset),
.rx(rx),
.tx_interrupt(tx_interrupt),
.rx_interrupt(rx_interrupt),
.tx_data(tx_data),
.tx_clk(tx_clk),
.rx_data(rx_data),
.rx_clk(rx_clk));
defparam BUART.Address1 = 0;
defparam BUART.Address2 = 0;
defparam BUART.BreakBitsRX = 13;
defparam BUART.BreakBitsTX = 13;
defparam BUART.BreakDetect = 0;
defparam BUART.CRCoutputsEn = 0;
defparam BUART.FlowControl = 0;
defparam BUART.HalfDuplexEn = 0;
defparam BUART.HwTXEnSignal = 1;
defparam BUART.NumDataBits = 8;
defparam BUART.NumStopBits = 1;
defparam BUART.OverSampleCount = 8;
defparam BUART.ParityType = 0;
defparam BUART.ParityTypeSw = 0;
defparam BUART.RXAddressMode = 0;
defparam BUART.RXEnable = 1;
defparam BUART.RXStatusIntEnable = 1;
defparam BUART.TXBitClkGenDP = 1;
defparam BUART.TXEnable = 0;
defparam BUART.Use23Polling = 1;
endmodule
|
module UART_v2_30_2 (
rx_clk,
rx_data,
tx_clk,
tx_data,
rx_interrupt,
tx_interrupt,
tx,
tx_en,
rts_n,
reset,
cts_n,
clock,
rx);
output rx_clk;
output rx_data;
output tx_clk;
output tx_data;
output rx_interrupt;
output tx_interrupt;
output tx;
output tx_en;
output rts_n;
input reset;
input cts_n;
input clock;
input rx;
parameter Address1 = 0;
parameter Address2 = 0;
parameter EnIntRXInterrupt = 0;
parameter EnIntTXInterrupt = 0;
parameter FlowControl = 0;
parameter HalfDuplexEn = 0;
parameter HwTXEnSignal = 0;
parameter NumDataBits = 8;
parameter NumStopBits = 1;
parameter ParityType = 0;
parameter RXEnable = 1;
parameter TXEnable = 1;
wire Net_289;
wire Net_61;
wire Net_9;
cy_clock_v1_0
#(.id("42a3c2ea-f0b8-4d0c-bf50-a43bc1e1db6a/b12b385d-9eab-45ad-ad40-c0cf3437ebe3/be0a0e37-ad17-42ca-b5a1-1a654d736358"),
.source_clock_id(""),
.divisor(0),
.period("1085069444.44444"),
.is_direct(0),
.is_digital(1))
IntClock
(.clock_out(Net_9));
// VirtualMux_1 (cy_virtualmux_v1_0)
assign Net_61 = Net_9;
B_UART_v2_30 BUART (
.cts_n(cts_n),
.tx(tx),
.rts_n(rts_n),
.tx_en(tx_en),
.clock(Net_61),
.reset(reset),
.rx(rx),
.tx_interrupt(tx_interrupt),
.rx_interrupt(rx_interrupt),
.tx_data(tx_data),
.tx_clk(tx_clk),
.rx_data(rx_data),
.rx_clk(rx_clk));
defparam BUART.Address1 = 0;
defparam BUART.Address2 = 0;
defparam BUART.BreakBitsRX = 13;
defparam BUART.BreakBitsTX = 13;
defparam BUART.BreakDetect = 0;
defparam BUART.CRCoutputsEn = 0;
defparam BUART.FlowControl = 0;
defparam BUART.HalfDuplexEn = 0;
defparam BUART.HwTXEnSignal = 0;
defparam BUART.NumDataBits = 8;
defparam BUART.NumStopBits = 1;
defparam BUART.OverSampleCount = 8;
defparam BUART.ParityType = 0;
defparam BUART.ParityTypeSw = 0;
defparam BUART.RXAddressMode = 0;
defparam BUART.RXEnable = 1;
defparam BUART.RXStatusIntEnable = 1;
defparam BUART.TXBitClkGenDP = 1;
defparam BUART.TXEnable = 1;
defparam BUART.Use23Polling = 1;
endmodule
|
module I2C_v3_30_3 (
sda_o,
scl_o,
sda_i,
scl_i,
iclk,
bclk,
reset,
clock,
scl,
sda,
itclk);
output sda_o;
output scl_o;
input sda_i;
input scl_i;
output iclk;
output bclk;
input reset;
input clock;
inout scl;
inout sda;
output itclk;
wire sda_x_wire;
wire sda_yfb;
wire udb_clk;
wire Net_975;
wire Net_974;
wire Net_973;
wire bus_clk;
wire Net_972;
wire Net_968;
wire scl_yfb;
wire Net_969;
wire Net_971;
wire Net_970;
wire timeout_clk;
wire Net_697;
wire Net_1045;
wire [1:0] Net_1109;
wire [5:0] Net_643;
wire scl_x_wire;
// Vmux_sda_out (cy_virtualmux_v1_0)
assign sda_x_wire = Net_643[1];
cy_isr_v1_0
#(.int_type(2'b00))
I2C_IRQ
(.int_signal(Net_697));
cy_psoc3_i2c_v1_0 I2C_FF (
.clock(bus_clk),
.scl_in(Net_1109[0]),
.sda_in(Net_1109[1]),
.scl_out(Net_643[0]),
.sda_out(Net_643[1]),
.interrupt(Net_643[2]));
defparam I2C_FF.use_wakeup = 0;
// Vmux_interrupt (cy_virtualmux_v1_0)
assign Net_697 = Net_643[2];
// Vmux_scl_out (cy_virtualmux_v1_0)
assign scl_x_wire = Net_643[0];
OneTerminal OneTerminal_1 (
.o(Net_969));
OneTerminal OneTerminal_2 (
.o(Net_968));
// Vmux_clock (cy_virtualmux_v1_0)
assign udb_clk = clock;
cy_clock_v1_0
#(.id("42a3c2ea-f0b8-4d0c-bf50-a43bc1e1db6a/966ec24e-f954-4ab8-95f3-fa8b01a2dc28/5ece924d-20ba-480e-9102-bc082dcdd926"),
.source_clock_id("75C2148C-3656-4d8a-846D-0CAE99AB6FF7"),
.divisor(0),
.period("0"),
.is_direct(1),
.is_digital(1))
BusClock
(.clock_out(bus_clk));
assign bclk = bus_clk | Net_973;
ZeroTerminal ZeroTerminal_1 (
.z(Net_973));
assign iclk = udb_clk | Net_974;
ZeroTerminal ZeroTerminal_2 (
.z(Net_974));
// Vmux_scl_in (cy_virtualmux_v1_0)
assign Net_1109[0] = scl_yfb;
// Vmux_sda_in (cy_virtualmux_v1_0)
assign Net_1109[1] = sda_yfb;
wire [0:0] tmpOE__Bufoe_scl_net;
cy_bufoe
Bufoe_scl
(.x(scl_x_wire),
.y(scl),
.oe(tmpOE__Bufoe_scl_net),
.yfb(scl_yfb));
assign tmpOE__Bufoe_scl_net = (`CYDEV_CHIP_MEMBER_USED == `CYDEV_CHIP_MEMBER_3A && `CYDEV_CHIP_REVISION_USED < `CYDEV_CHIP_REVISION_3A_ES3) ? ~{Net_969} : {Net_969};
wire [0:0] tmpOE__Bufoe_sda_net;
cy_bufoe
Bufoe_sda
(.x(sda_x_wire),
.y(sda),
.oe(tmpOE__Bufoe_sda_net),
.yfb(sda_yfb));
assign tmpOE__Bufoe_sda_net = (`CYDEV_CHIP_MEMBER_USED == `CYDEV_CHIP_MEMBER_3A && `CYDEV_CHIP_REVISION_USED < `CYDEV_CHIP_REVISION_3A_ES3) ? ~{Net_968} : {Net_968};
// Vmux_timeout_clock (cy_virtualmux_v1_0)
assign timeout_clk = clock;
assign itclk = timeout_clk | Net_975;
ZeroTerminal ZeroTerminal_3 (
.z(Net_975));
assign scl_o = scl_x_wire;
assign sda_o = sda_x_wire;
endmodule
|
module Counter_v2_40_4 (
clock,
comp,
tc,
reset,
interrupt,
enable,
capture,
upCnt,
downCnt,
up_ndown,
count);
input clock;
output comp;
output tc;
input reset;
output interrupt;
input enable;
input capture;
input upCnt;
input downCnt;
input up_ndown;
input count;
parameter CaptureMode = 0;
parameter ClockMode = 3;
parameter CompareMode = 1;
parameter CompareStatusEdgeSense = 1;
parameter EnableMode = 0;
parameter ReloadOnCapture = 0;
parameter ReloadOnCompare = 0;
parameter ReloadOnOverUnder = 1;
parameter ReloadOnReset = 1;
parameter Resolution = 16;
parameter RunMode = 0;
parameter UseInterrupt = 1;
wire Net_47;
wire Net_102;
wire Net_95;
wire Net_82;
wire Net_91;
wire Net_89;
wire Net_49;
wire Net_48;
wire Net_42;
wire Net_43;
cy_psoc3_timer_v1_0 CounterHW (
.timer_reset(reset),
.capture(capture),
.enable(Net_91),
.kill(Net_82),
.clock(clock),
.tc(Net_48),
.compare(Net_47),
.interrupt(Net_42));
// int_vm (cy_virtualmux_v1_0)
assign interrupt = Net_42;
// TC_vm (cy_virtualmux_v1_0)
assign tc = Net_48;
ZeroTerminal ZeroTerminal_1 (
.z(Net_82));
// VirtualMux_1 (cy_virtualmux_v1_0)
assign Net_89 = Net_95;
ZeroTerminal ZeroTerminal_2 (
.z(Net_95));
// vmEnableMode (cy_virtualmux_v1_0)
assign Net_91 = enable;
OneTerminal OneTerminal_1 (
.o(Net_102));
endmodule
|
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