module_content
stringlengths 18
1.05M
|
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module icache_data_ram
(
// Inputs
input clk_i
,input rst_i
,input [ 10:0] addr_i
,input [ 31:0] data_i
,input wr_i
// Outputs
,output [ 31:0] data_o
);
//-----------------------------------------------------------------
// Single Port RAM 8KB
// Mode: Read First
//-----------------------------------------------------------------
reg [31:0] ram [2047:0] /*verilator public*/;
reg [31:0] ram_read_q;
// Synchronous write
always @ (posedge clk_i)
begin
if (wr_i)
ram[addr_i] <= data_i;
ram_read_q <= ram[addr_i];
end
assign data_o = ram_read_q;
endmodule
|
module bsg_cache_non_blocking_decode
import bsg_cache_non_blocking_pkg::*;
(
input bsg_cache_non_blocking_opcode_e opcode_i
, output bsg_cache_non_blocking_decode_s decode_o
);
always_comb begin
case (opcode_i)
LD, SD: decode_o.size_op = 2'b11;
LW, SW, LWU: decode_o.size_op = 2'b10;
LH, SH, LHU: decode_o.size_op = 2'b01;
LB, SB, LBU: decode_o.size_op = 2'b00;
default: decode_o.size_op = 2'b00;
endcase
end
assign decode_o.sigext_op = (opcode_i == LB)
| (opcode_i == LH)
| (opcode_i == LW)
| (opcode_i == LD);
assign decode_o.ld_op = (opcode_i == LB)
| (opcode_i == LH)
| (opcode_i == LW)
| (opcode_i == LD)
| (opcode_i == LBU)
| (opcode_i == LHU)
| (opcode_i == LWU);
assign decode_o.st_op = (opcode_i == SB)
| (opcode_i == SH)
| (opcode_i == SW)
| (opcode_i == SD)
| (opcode_i == SM);
assign decode_o.mask_op = (opcode_i == SM);
assign decode_o.block_ld_op = (opcode_i == BLOCK_LD);
assign decode_o.tagst_op = (opcode_i == TAGST);
assign decode_o.tagfl_op = (opcode_i == TAGFL);
assign decode_o.taglv_op = (opcode_i == TAGLV);
assign decode_o.tagla_op = (opcode_i == TAGLA);
assign decode_o.afl_op = (opcode_i == AFL);
assign decode_o.aflinv_op = (opcode_i == AFLINV);
assign decode_o.ainv_op = (opcode_i == AINV);
assign decode_o.alock_op = (opcode_i == ALOCK);
assign decode_o.aunlock_op = (opcode_i == AUNLOCK);
assign decode_o.mgmt_op = ~(decode_o.ld_op | decode_o.st_op | decode_o.block_ld_op);
endmodule
|
module sky130_fd_sc_lp__clkdlybuf4s18 (
//# {{data|Data Signals}}
input A,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
|
module sky130_fd_sc_hs__sdfbbp (
Q ,
Q_N ,
D ,
SCD ,
SCE ,
CLK ,
SET_B ,
RESET_B,
VPWR ,
VGND
);
// Module ports
output Q ;
output Q_N ;
input D ;
input SCD ;
input SCE ;
input CLK ;
input SET_B ;
input RESET_B;
input VPWR ;
input VGND ;
// Local signals
wire RESET ;
wire SET ;
wire buf_Q ;
reg notifier ;
wire D_delayed ;
wire SCD_delayed ;
wire SCE_delayed ;
wire CLK_delayed ;
wire SET_B_delayed ;
wire RESET_B_delayed;
wire mux_out ;
wire awake ;
wire cond0 ;
wire cond1 ;
wire condb ;
wire cond_D ;
wire cond_SCD ;
wire cond_SCE ;
// Name Output Other arguments
not not0 (RESET , RESET_B_delayed );
not not1 (SET , SET_B_delayed );
sky130_fd_sc_hs__u_mux_2_1 u_mux_20 (mux_out, D_delayed, SCD_delayed, SCE_delayed );
sky130_fd_sc_hs__u_dfb_setdom_notify_pg u_dfb_setdom_notify_pg0 (buf_Q , SET, RESET, CLK_delayed, mux_out, notifier, VPWR, VGND);
assign awake = ( VPWR === 1'b1 );
assign cond0 = ( awake && ( RESET_B_delayed === 1'b1 ) );
assign cond1 = ( awake && ( SET_B_delayed === 1'b1 ) );
assign condb = ( cond0 & cond1 );
assign cond_D = ( ( SCE_delayed === 1'b0 ) && condb );
assign cond_SCD = ( ( SCE_delayed === 1'b1 ) && condb );
assign cond_SCE = ( ( D_delayed !== SCD_delayed ) && condb );
buf buf0 (Q , buf_Q );
not not2 (Q_N , buf_Q );
endmodule
|
module nfa_accept_sample (
ap_clk,
ap_rst,
ap_start,
ap_done,
ap_idle,
ap_ready,
nfa_initials_buckets_req_din,
nfa_initials_buckets_req_full_n,
nfa_initials_buckets_req_write,
nfa_initials_buckets_rsp_empty_n,
nfa_initials_buckets_rsp_read,
nfa_initials_buckets_address,
nfa_initials_buckets_datain,
nfa_initials_buckets_dataout,
nfa_initials_buckets_size,
nfa_finals_buckets_req_din,
nfa_finals_buckets_req_full_n,
nfa_finals_buckets_req_write,
nfa_finals_buckets_rsp_empty_n,
nfa_finals_buckets_rsp_read,
nfa_finals_buckets_address,
nfa_finals_buckets_datain,
nfa_finals_buckets_dataout,
nfa_finals_buckets_size,
nfa_forward_buckets_req_din,
nfa_forward_buckets_req_full_n,
nfa_forward_buckets_req_write,
nfa_forward_buckets_rsp_empty_n,
nfa_forward_buckets_rsp_read,
nfa_forward_buckets_address,
nfa_forward_buckets_datain,
nfa_forward_buckets_dataout,
nfa_forward_buckets_size,
nfa_symbols,
sample_req_din,
sample_req_full_n,
sample_req_write,
sample_rsp_empty_n,
sample_rsp_read,
sample_address,
sample_datain,
sample_dataout,
sample_size,
empty,
length_r,
ap_return
);
input ap_clk;
input ap_rst;
input ap_start;
output ap_done;
output ap_idle;
output ap_ready;
output nfa_initials_buckets_req_din;
input nfa_initials_buckets_req_full_n;
output nfa_initials_buckets_req_write;
input nfa_initials_buckets_rsp_empty_n;
output nfa_initials_buckets_rsp_read;
output [31:0] nfa_initials_buckets_address;
input [31:0] nfa_initials_buckets_datain;
output [31:0] nfa_initials_buckets_dataout;
output [31:0] nfa_initials_buckets_size;
output nfa_finals_buckets_req_din;
input nfa_finals_buckets_req_full_n;
output nfa_finals_buckets_req_write;
input nfa_finals_buckets_rsp_empty_n;
output nfa_finals_buckets_rsp_read;
output [31:0] nfa_finals_buckets_address;
input [31:0] nfa_finals_buckets_datain;
output [31:0] nfa_finals_buckets_dataout;
output [31:0] nfa_finals_buckets_size;
output nfa_forward_buckets_req_din;
input nfa_forward_buckets_req_full_n;
output nfa_forward_buckets_req_write;
input nfa_forward_buckets_rsp_empty_n;
output nfa_forward_buckets_rsp_read;
output [31:0] nfa_forward_buckets_address;
input [31:0] nfa_forward_buckets_datain;
output [31:0] nfa_forward_buckets_dataout;
output [31:0] nfa_forward_buckets_size;
input [7:0] nfa_symbols;
output sample_req_din;
input sample_req_full_n;
output sample_req_write;
input sample_rsp_empty_n;
output sample_rsp_read;
output [31:0] sample_address;
input [7:0] sample_datain;
output [7:0] sample_dataout;
output [31:0] sample_size;
input [31:0] empty;
input [15:0] length_r;
output [0:0] ap_return;
reg ap_done;
reg ap_idle;
reg ap_ready;
reg nfa_forward_buckets_req_write;
reg nfa_forward_buckets_rsp_read;
reg[31:0] nfa_forward_buckets_address;
reg sample_req_write;
reg sample_rsp_read;
reg[0:0] ap_return;
reg [5:0] ap_CS_fsm = 6'b000000;
reg [31:0] reg_374;
reg [31:0] current_buckets_0_reg_577;
reg [31:0] current_buckets_1_reg_582;
wire [0:0] tmp_s_fu_397_p2;
reg [0:0] tmp_s_reg_597;
wire [15:0] grp_fu_402_p2;
reg [15:0] i_1_reg_601;
reg [31:0] sample_addr_1_reg_606;
wire [0:0] tmp_17_i_fu_420_p2;
reg [0:0] tmp_17_i_reg_612;
wire [31:0] grp_fu_414_p2;
reg [31:0] p_rec_reg_616;
reg [7:0] sym_reg_621;
wire [0:0] tmp_17_1_i_fu_426_p2;
reg [0:0] tmp_17_1_i_reg_626;
wire [4:0] grp_p_bsf32_hw_fu_368_ap_return;
reg [4:0] r_bit_reg_630;
wire [1:0] agg_result_bucket_index_0_lcssa4_i_cast_cast_fu_432_p1;
wire [7:0] j_bucket_index1_ph_cast_fu_436_p1;
wire [7:0] j_bit1_ph_cast_fu_440_p1;
wire [13:0] tmp_7_i_cast_fu_444_p1;
reg [13:0] tmp_7_i_cast_reg_650;
wire [0:0] j_end_phi_fu_312_p4;
wire [5:0] grp_fu_463_p2;
reg [5:0] state_reg_665;
wire [13:0] grp_fu_476_p2;
reg [13:0] tmp_6_i_reg_680;
reg [7:0] j_bit_reg_685;
reg [7:0] j_bucket_index_reg_690;
reg [31:0] j_bucket_reg_695;
reg [0:0] p_s_reg_700;
wire [13:0] grp_fu_482_p2;
reg [13:0] offset_i_reg_705;
wire [31:0] next_buckets_0_1_fu_538_p2;
reg [31:0] next_buckets_0_1_reg_721;
wire [31:0] next_buckets_1_1_fu_544_p2;
reg [31:0] tmp_buckets_0_reg_731;
reg [31:0] tmp_buckets_1_reg_736;
wire [31:0] current_buckets_0_1_fu_558_p2;
reg [31:0] current_buckets_0_1_reg_741;
wire [31:0] current_buckets_1_1_fu_563_p2;
reg [31:0] current_buckets_1_1_reg_746;
wire [31:0] tmp_1_fu_568_p2;
reg [31:0] tmp_1_reg_751;
wire [0:0] tmp_2_fu_572_p2;
reg [0:0] tmp_2_reg_756;
wire [31:0] grp_bitset_next_fu_344_p_read;
wire [7:0] grp_bitset_next_fu_344_r_bit;
wire [7:0] grp_bitset_next_fu_344_r_bucket_index;
wire [31:0] grp_bitset_next_fu_344_r_bucket;
wire [7:0] grp_bitset_next_fu_344_ap_return_0;
wire [7:0] grp_bitset_next_fu_344_ap_return_1;
wire [31:0] grp_bitset_next_fu_344_ap_return_2;
wire [0:0] grp_bitset_next_fu_344_ap_return_3;
reg grp_bitset_next_fu_344_ap_ce;
reg grp_nfa_get_initials_fu_356_ap_start;
wire grp_nfa_get_initials_fu_356_ap_done;
wire grp_nfa_get_initials_fu_356_ap_idle;
wire grp_nfa_get_initials_fu_356_ap_ready;
wire grp_nfa_get_initials_fu_356_nfa_initials_buckets_req_din;
wire grp_nfa_get_initials_fu_356_nfa_initials_buckets_req_full_n;
wire grp_nfa_get_initials_fu_356_nfa_initials_buckets_req_write;
wire grp_nfa_get_initials_fu_356_nfa_initials_buckets_rsp_empty_n;
wire grp_nfa_get_initials_fu_356_nfa_initials_buckets_rsp_read;
wire [31:0] grp_nfa_get_initials_fu_356_nfa_initials_buckets_address;
wire [31:0] grp_nfa_get_initials_fu_356_nfa_initials_buckets_datain;
wire [31:0] grp_nfa_get_initials_fu_356_nfa_initials_buckets_dataout;
wire [31:0] grp_nfa_get_initials_fu_356_nfa_initials_buckets_size;
wire grp_nfa_get_initials_fu_356_ap_ce;
wire [31:0] grp_nfa_get_initials_fu_356_ap_return_0;
wire [31:0] grp_nfa_get_initials_fu_356_ap_return_1;
wire grp_nfa_get_finals_fu_362_ap_start;
wire grp_nfa_get_finals_fu_362_ap_done;
wire grp_nfa_get_finals_fu_362_ap_idle;
wire grp_nfa_get_finals_fu_362_ap_ready;
wire grp_nfa_get_finals_fu_362_nfa_finals_buckets_req_din;
wire grp_nfa_get_finals_fu_362_nfa_finals_buckets_req_full_n;
wire grp_nfa_get_finals_fu_362_nfa_finals_buckets_req_write;
wire grp_nfa_get_finals_fu_362_nfa_finals_buckets_rsp_empty_n;
wire grp_nfa_get_finals_fu_362_nfa_finals_buckets_rsp_read;
wire [31:0] grp_nfa_get_finals_fu_362_nfa_finals_buckets_address;
wire [31:0] grp_nfa_get_finals_fu_362_nfa_finals_buckets_datain;
wire [31:0] grp_nfa_get_finals_fu_362_nfa_finals_buckets_dataout;
wire [31:0] grp_nfa_get_finals_fu_362_nfa_finals_buckets_size;
wire grp_nfa_get_finals_fu_362_ap_ce;
wire [31:0] grp_nfa_get_finals_fu_362_ap_return_0;
wire [31:0] grp_nfa_get_finals_fu_362_ap_return_1;
wire [31:0] grp_p_bsf32_hw_fu_368_bus_r;
reg grp_p_bsf32_hw_fu_368_ap_ce;
reg [15:0] i_reg_134;
wire [0:0] any_phi_fu_324_p4;
reg [31:0] p_01_rec_reg_146;
reg [31:0] next_buckets_1_reg_158;
reg [31:0] next_buckets_0_reg_168;
reg [31:0] bus_assign_reg_178;
reg [0:0] agg_result_bucket_index_0_lcssa4_i_reg_190;
reg [31:0] j_bucket1_ph_reg_203;
reg [1:0] j_bucket_index1_ph_reg_216;
reg [4:0] j_bit1_ph_reg_227;
reg [0:0] j_end_ph_reg_238;
reg [31:0] tmp_buckets_1_3_reg_252;
reg [31:0] tmp_buckets_0_3_reg_265;
reg [31:0] j_bucket1_reg_278;
reg [7:0] j_bucket_index1_reg_289;
reg [7:0] j_bit1_reg_299;
reg [0:0] j_end_reg_309;
reg [0:0] any_reg_319;
reg [0:0] p_0_reg_332;
reg [5:0] ap_NS_fsm;
reg grp_nfa_get_finals_fu_362_ap_start_ap_start_reg = 1'b0;
wire [31:0] grp_fu_392_p2;
wire [31:0] tmp_4_i_cast_fu_509_p1;
wire [31:0] tmp_8_i_cast_fu_527_p1;
wire [31:0] grp_fu_392_p0;
wire [31:0] grp_fu_392_p1;
wire [15:0] grp_fu_402_p0;
wire [15:0] grp_fu_402_p1;
wire [31:0] grp_fu_414_p0;
wire [31:0] grp_fu_414_p1;
wire [0:0] tmp_5_fu_447_p1;
wire [5:0] grp_fu_463_p0;
wire [5:0] grp_fu_463_p1;
wire [7:0] grp_fu_476_p0;
wire [5:0] grp_fu_476_p1;
wire [13:0] grp_fu_482_p0;
wire [13:0] grp_fu_482_p1;
wire [14:0] tmp_4_i_fu_502_p3;
wire [14:0] tmp_8_i_fu_520_p3;
wire grp_fu_392_ce;
wire grp_fu_402_ce;
reg grp_fu_414_ce;
wire grp_fu_463_ce;
wire grp_fu_476_ce;
wire grp_fu_482_ce;
reg [0:0] ap_return_preg = 1'b0;
wire [13:0] grp_fu_476_p00;
wire [13:0] grp_fu_476_p10;
parameter ap_const_logic_1 = 1'b1;
parameter ap_const_logic_0 = 1'b0;
parameter ap_ST_st1_fsm_0 = 6'b000000;
parameter ap_ST_st2_fsm_1 = 6'b1;
parameter ap_ST_st3_fsm_2 = 6'b10;
parameter ap_ST_st4_fsm_3 = 6'b11;
parameter ap_ST_st5_fsm_4 = 6'b100;
parameter ap_ST_st6_fsm_5 = 6'b101;
parameter ap_ST_st7_fsm_6 = 6'b110;
parameter ap_ST_st8_fsm_7 = 6'b111;
parameter ap_ST_st9_fsm_8 = 6'b1000;
parameter ap_ST_st10_fsm_9 = 6'b1001;
parameter ap_ST_st11_fsm_10 = 6'b1010;
parameter ap_ST_st12_fsm_11 = 6'b1011;
parameter ap_ST_st13_fsm_12 = 6'b1100;
parameter ap_ST_st14_fsm_13 = 6'b1101;
parameter ap_ST_st15_fsm_14 = 6'b1110;
parameter ap_ST_st16_fsm_15 = 6'b1111;
parameter ap_ST_st17_fsm_16 = 6'b10000;
parameter ap_ST_st18_fsm_17 = 6'b10001;
parameter ap_ST_st19_fsm_18 = 6'b10010;
parameter ap_ST_st20_fsm_19 = 6'b10011;
parameter ap_ST_st21_fsm_20 = 6'b10100;
parameter ap_ST_st22_fsm_21 = 6'b10101;
parameter ap_ST_st23_fsm_22 = 6'b10110;
parameter ap_ST_st24_fsm_23 = 6'b10111;
parameter ap_ST_st25_fsm_24 = 6'b11000;
parameter ap_ST_st26_fsm_25 = 6'b11001;
parameter ap_ST_st27_fsm_26 = 6'b11010;
parameter ap_ST_st28_fsm_27 = 6'b11011;
parameter ap_ST_st29_fsm_28 = 6'b11100;
parameter ap_ST_st30_fsm_29 = 6'b11101;
parameter ap_ST_st31_fsm_30 = 6'b11110;
parameter ap_ST_st32_fsm_31 = 6'b11111;
parameter ap_ST_st33_fsm_32 = 6'b100000;
parameter ap_ST_st34_fsm_33 = 6'b100001;
parameter ap_ST_st35_fsm_34 = 6'b100010;
parameter ap_ST_st36_fsm_35 = 6'b100011;
parameter ap_ST_st37_fsm_36 = 6'b100100;
parameter ap_ST_st38_fsm_37 = 6'b100101;
parameter ap_ST_st39_fsm_38 = 6'b100110;
parameter ap_ST_st40_fsm_39 = 6'b100111;
parameter ap_ST_st41_fsm_40 = 6'b101000;
parameter ap_ST_st42_fsm_41 = 6'b101001;
parameter ap_ST_st43_fsm_42 = 6'b101010;
parameter ap_ST_st44_fsm_43 = 6'b101011;
parameter ap_ST_st45_fsm_44 = 6'b101100;
parameter ap_ST_st46_fsm_45 = 6'b101101;
parameter ap_ST_st47_fsm_46 = 6'b101110;
parameter ap_ST_st48_fsm_47 = 6'b101111;
parameter ap_ST_st49_fsm_48 = 6'b110000;
parameter ap_ST_st50_fsm_49 = 6'b110001;
parameter ap_const_lv1_0 = 1'b0;
parameter ap_const_lv16_0 = 16'b0000000000000000;
parameter ap_const_lv32_0 = 32'b00000000000000000000000000000000;
parameter ap_const_lv1_1 = 1'b1;
parameter ap_const_lv2_2 = 2'b10;
parameter ap_const_lv32_1 = 32'b1;
parameter ap_const_lv16_1 = 16'b1;
parameter ap_const_lv5_0 = 5'b00000;
parameter ap_const_lv8_0 = 8'b00000000;
parameter ap_true = 1'b1;
bitset_next grp_bitset_next_fu_344(
.ap_clk( ap_clk ),
.ap_rst( ap_rst ),
.p_read( grp_bitset_next_fu_344_p_read ),
.r_bit( grp_bitset_next_fu_344_r_bit ),
.r_bucket_index( grp_bitset_next_fu_344_r_bucket_index ),
.r_bucket( grp_bitset_next_fu_344_r_bucket ),
.ap_return_0( grp_bitset_next_fu_344_ap_return_0 ),
.ap_return_1( grp_bitset_next_fu_344_ap_return_1 ),
.ap_return_2( grp_bitset_next_fu_344_ap_return_2 ),
.ap_return_3( grp_bitset_next_fu_344_ap_return_3 ),
.ap_ce( grp_bitset_next_fu_344_ap_ce )
);
nfa_get_initials grp_nfa_get_initials_fu_356(
.ap_clk( ap_clk ),
.ap_rst( ap_rst ),
.ap_start( grp_nfa_get_initials_fu_356_ap_start ),
.ap_done( grp_nfa_get_initials_fu_356_ap_done ),
.ap_idle( grp_nfa_get_initials_fu_356_ap_idle ),
.ap_ready( grp_nfa_get_initials_fu_356_ap_ready ),
.nfa_initials_buckets_req_din( grp_nfa_get_initials_fu_356_nfa_initials_buckets_req_din ),
.nfa_initials_buckets_req_full_n( grp_nfa_get_initials_fu_356_nfa_initials_buckets_req_full_n ),
.nfa_initials_buckets_req_write( grp_nfa_get_initials_fu_356_nfa_initials_buckets_req_write ),
.nfa_initials_buckets_rsp_empty_n( grp_nfa_get_initials_fu_356_nfa_initials_buckets_rsp_empty_n ),
.nfa_initials_buckets_rsp_read( grp_nfa_get_initials_fu_356_nfa_initials_buckets_rsp_read ),
.nfa_initials_buckets_address( grp_nfa_get_initials_fu_356_nfa_initials_buckets_address ),
.nfa_initials_buckets_datain( grp_nfa_get_initials_fu_356_nfa_initials_buckets_datain ),
.nfa_initials_buckets_dataout( grp_nfa_get_initials_fu_356_nfa_initials_buckets_dataout ),
.nfa_initials_buckets_size( grp_nfa_get_initials_fu_356_nfa_initials_buckets_size ),
.ap_ce( grp_nfa_get_initials_fu_356_ap_ce ),
.ap_return_0( grp_nfa_get_initials_fu_356_ap_return_0 ),
.ap_return_1( grp_nfa_get_initials_fu_356_ap_return_1 )
);
nfa_get_finals grp_nfa_get_finals_fu_362(
.ap_clk( ap_clk ),
.ap_rst( ap_rst ),
.ap_start( grp_nfa_get_finals_fu_362_ap_start ),
.ap_done( grp_nfa_get_finals_fu_362_ap_done ),
.ap_idle( grp_nfa_get_finals_fu_362_ap_idle ),
.ap_ready( grp_nfa_get_finals_fu_362_ap_ready ),
.nfa_finals_buckets_req_din( grp_nfa_get_finals_fu_362_nfa_finals_buckets_req_din ),
.nfa_finals_buckets_req_full_n( grp_nfa_get_finals_fu_362_nfa_finals_buckets_req_full_n ),
.nfa_finals_buckets_req_write( grp_nfa_get_finals_fu_362_nfa_finals_buckets_req_write ),
.nfa_finals_buckets_rsp_empty_n( grp_nfa_get_finals_fu_362_nfa_finals_buckets_rsp_empty_n ),
.nfa_finals_buckets_rsp_read( grp_nfa_get_finals_fu_362_nfa_finals_buckets_rsp_read ),
.nfa_finals_buckets_address( grp_nfa_get_finals_fu_362_nfa_finals_buckets_address ),
.nfa_finals_buckets_datain( grp_nfa_get_finals_fu_362_nfa_finals_buckets_datain ),
.nfa_finals_buckets_dataout( grp_nfa_get_finals_fu_362_nfa_finals_buckets_dataout ),
.nfa_finals_buckets_size( grp_nfa_get_finals_fu_362_nfa_finals_buckets_size ),
.ap_ce( grp_nfa_get_finals_fu_362_ap_ce ),
.ap_return_0( grp_nfa_get_finals_fu_362_ap_return_0 ),
.ap_return_1( grp_nfa_get_finals_fu_362_ap_return_1 )
);
p_bsf32_hw grp_p_bsf32_hw_fu_368(
.ap_clk( ap_clk ),
.ap_rst( ap_rst ),
.bus_r( grp_p_bsf32_hw_fu_368_bus_r ),
.ap_return( grp_p_bsf32_hw_fu_368_ap_return ),
.ap_ce( grp_p_bsf32_hw_fu_368_ap_ce )
);
nfa_accept_samples_generic_hw_add_32ns_32ns_32_8 #(
.ID( 17 ),
.NUM_STAGE( 8 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
nfa_accept_samples_generic_hw_add_32ns_32ns_32_8_U17(
.clk( ap_clk ),
.reset( ap_rst ),
.din0( grp_fu_392_p0 ),
.din1( grp_fu_392_p1 ),
.ce( grp_fu_392_ce ),
.dout( grp_fu_392_p2 )
);
nfa_accept_samples_generic_hw_add_16ns_16ns_16_4 #(
.ID( 18 ),
.NUM_STAGE( 4 ),
.din0_WIDTH( 16 ),
.din1_WIDTH( 16 ),
.dout_WIDTH( 16 ))
nfa_accept_samples_generic_hw_add_16ns_16ns_16_4_U18(
.clk( ap_clk ),
.reset( ap_rst ),
.din0( grp_fu_402_p0 ),
.din1( grp_fu_402_p1 ),
.ce( grp_fu_402_ce ),
.dout( grp_fu_402_p2 )
);
nfa_accept_samples_generic_hw_add_32ns_32ns_32_8 #(
.ID( 19 ),
.NUM_STAGE( 8 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
nfa_accept_samples_generic_hw_add_32ns_32ns_32_8_U19(
.clk( ap_clk ),
.reset( ap_rst ),
.din0( grp_fu_414_p0 ),
.din1( grp_fu_414_p1 ),
.ce( grp_fu_414_ce ),
.dout( grp_fu_414_p2 )
);
nfa_accept_samples_generic_hw_add_6ns_6ns_6_2 #(
.ID( 20 ),
.NUM_STAGE( 2 ),
.din0_WIDTH( 6 ),
.din1_WIDTH( 6 ),
.dout_WIDTH( 6 ))
nfa_accept_samples_generic_hw_add_6ns_6ns_6_2_U20(
.clk( ap_clk ),
.reset( ap_rst ),
.din0( grp_fu_463_p0 ),
.din1( grp_fu_463_p1 ),
.ce( grp_fu_463_ce ),
.dout( grp_fu_463_p2 )
);
nfa_accept_samples_generic_hw_mul_8ns_6ns_14_9 #(
.ID( 21 ),
.NUM_STAGE( 9 ),
.din0_WIDTH( 8 ),
.din1_WIDTH( 6 ),
.dout_WIDTH( 14 ))
nfa_accept_samples_generic_hw_mul_8ns_6ns_14_9_U21(
.clk( ap_clk ),
.reset( ap_rst ),
.din0( grp_fu_476_p0 ),
.din1( grp_fu_476_p1 ),
.ce( grp_fu_476_ce ),
.dout( grp_fu_476_p2 )
);
nfa_accept_samples_generic_hw_add_14ns_14ns_14_4 #(
.ID( 22 ),
.NUM_STAGE( 4 ),
.din0_WIDTH( 14 ),
.din1_WIDTH( 14 ),
.dout_WIDTH( 14 ))
nfa_accept_samples_generic_hw_add_14ns_14ns_14_4_U22(
.clk( ap_clk ),
.reset( ap_rst ),
.din0( grp_fu_482_p0 ),
.din1( grp_fu_482_p1 ),
.ce( grp_fu_482_ce ),
.dout( grp_fu_482_p2 )
);
/// the current state (ap_CS_fsm) of the state machine. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_CS_fsm
if (ap_rst == 1'b1) begin
ap_CS_fsm <= ap_ST_st1_fsm_0;
end else begin
ap_CS_fsm <= ap_NS_fsm;
end
end
/// ap_return_preg assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_return_preg
if (ap_rst == 1'b1) begin
ap_return_preg <= ap_const_lv1_0;
end else begin
if ((ap_ST_st50_fsm_49 == ap_CS_fsm)) begin
ap_return_preg <= p_0_reg_332;
end
end
end
/// grp_nfa_get_finals_fu_362_ap_start_ap_start_reg assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_grp_nfa_get_finals_fu_362_ap_start_ap_start_reg
if (ap_rst == 1'b1) begin
grp_nfa_get_finals_fu_362_ap_start_ap_start_reg <= ap_const_logic_0;
end else begin
if (((ap_ST_st12_fsm_11 == ap_NS_fsm) & (ap_ST_st11_fsm_10 == ap_CS_fsm) & (tmp_s_reg_597 == ap_const_lv1_0))) begin
grp_nfa_get_finals_fu_362_ap_start_ap_start_reg <= ap_const_logic_1;
end else if ((ap_const_logic_1 == grp_nfa_get_finals_fu_362_ap_ready)) begin
grp_nfa_get_finals_fu_362_ap_start_ap_start_reg <= ap_const_logic_0;
end
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st20_fsm_19 == ap_CS_fsm) & (tmp_17_1_i_reg_626 == ap_const_lv1_0))) begin
agg_result_bucket_index_0_lcssa4_i_reg_190 <= ap_const_lv1_1;
end else if (((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(sample_rsp_empty_n == ap_const_logic_0) & (tmp_17_i_reg_612 == ap_const_lv1_0))) begin
agg_result_bucket_index_0_lcssa4_i_reg_190 <= ap_const_lv1_0;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((ap_ST_st24_fsm_23 == ap_CS_fsm)) begin
any_reg_319 <= ap_const_lv1_0;
end else if ((ap_ST_st43_fsm_42 == ap_CS_fsm)) begin
any_reg_319 <= ap_const_lv1_1;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st20_fsm_19 == ap_CS_fsm) & (tmp_17_1_i_reg_626 == ap_const_lv1_0))) begin
bus_assign_reg_178 <= next_buckets_1_reg_158;
end else if (((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(sample_rsp_empty_n == ap_const_logic_0) & (tmp_17_i_reg_612 == ap_const_lv1_0))) begin
bus_assign_reg_178 <= next_buckets_0_reg_168;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st25_fsm_24 == ap_CS_fsm) & ~(ap_const_lv1_0 == j_end_phi_fu_312_p4) & ~(ap_const_lv1_0 == any_phi_fu_324_p4))) begin
i_reg_134 <= i_1_reg_601;
end else if ((ap_ST_st4_fsm_3 == ap_CS_fsm)) begin
i_reg_134 <= ap_const_lv16_0;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((ap_ST_st24_fsm_23 == ap_CS_fsm)) begin
j_bit1_reg_299 <= j_bit1_ph_cast_fu_440_p1;
end else if ((ap_ST_st43_fsm_42 == ap_CS_fsm)) begin
j_bit1_reg_299 <= j_bit_reg_685;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((ap_ST_st23_fsm_22 == ap_CS_fsm)) begin
j_bucket1_ph_reg_203 <= bus_assign_reg_178;
end else if (((ap_ST_st20_fsm_19 == ap_CS_fsm) & ~(tmp_17_1_i_reg_626 == ap_const_lv1_0))) begin
j_bucket1_ph_reg_203 <= ap_const_lv32_0;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((ap_ST_st24_fsm_23 == ap_CS_fsm)) begin
j_bucket1_reg_278 <= j_bucket1_ph_reg_203;
end else if ((ap_ST_st43_fsm_42 == ap_CS_fsm)) begin
j_bucket1_reg_278 <= j_bucket_reg_695;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((ap_ST_st23_fsm_22 == ap_CS_fsm)) begin
j_bucket_index1_ph_reg_216 <= agg_result_bucket_index_0_lcssa4_i_cast_cast_fu_432_p1;
end else if (((ap_ST_st20_fsm_19 == ap_CS_fsm) & ~(tmp_17_1_i_reg_626 == ap_const_lv1_0))) begin
j_bucket_index1_ph_reg_216 <= ap_const_lv2_2;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((ap_ST_st24_fsm_23 == ap_CS_fsm)) begin
j_bucket_index1_reg_289 <= j_bucket_index1_ph_cast_fu_436_p1;
end else if ((ap_ST_st43_fsm_42 == ap_CS_fsm)) begin
j_bucket_index1_reg_289 <= j_bucket_index_reg_690;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((ap_ST_st23_fsm_22 == ap_CS_fsm)) begin
j_end_ph_reg_238 <= ap_const_lv1_0;
end else if (((ap_ST_st20_fsm_19 == ap_CS_fsm) & ~(tmp_17_1_i_reg_626 == ap_const_lv1_0))) begin
j_end_ph_reg_238 <= ap_const_lv1_1;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((ap_ST_st24_fsm_23 == ap_CS_fsm)) begin
j_end_reg_309 <= j_end_ph_reg_238;
end else if ((ap_ST_st43_fsm_42 == ap_CS_fsm)) begin
j_end_reg_309 <= p_s_reg_700;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st25_fsm_24 == ap_CS_fsm) & ~(ap_const_lv1_0 == j_end_phi_fu_312_p4) & ~(ap_const_lv1_0 == any_phi_fu_324_p4))) begin
next_buckets_0_reg_168 <= tmp_buckets_0_3_reg_265;
end else if ((ap_ST_st4_fsm_3 == ap_CS_fsm)) begin
next_buckets_0_reg_168 <= current_buckets_0_reg_577;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st25_fsm_24 == ap_CS_fsm) & ~(ap_const_lv1_0 == j_end_phi_fu_312_p4) & ~(ap_const_lv1_0 == any_phi_fu_324_p4))) begin
next_buckets_1_reg_158 <= tmp_buckets_1_3_reg_252;
end else if ((ap_ST_st4_fsm_3 == ap_CS_fsm)) begin
next_buckets_1_reg_158 <= current_buckets_1_reg_582;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st25_fsm_24 == ap_CS_fsm) & ~(ap_const_lv1_0 == j_end_phi_fu_312_p4) & ~(ap_const_lv1_0 == any_phi_fu_324_p4))) begin
p_01_rec_reg_146 <= p_rec_reg_616;
end else if ((ap_ST_st4_fsm_3 == ap_CS_fsm)) begin
p_01_rec_reg_146 <= ap_const_lv32_0;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st25_fsm_24 == ap_CS_fsm) & ~(ap_const_lv1_0 == j_end_phi_fu_312_p4) & (ap_const_lv1_0 == any_phi_fu_324_p4))) begin
p_0_reg_332 <= ap_const_lv1_0;
end else if ((ap_ST_st49_fsm_48 == ap_CS_fsm)) begin
p_0_reg_332 <= tmp_2_reg_756;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((ap_ST_st24_fsm_23 == ap_CS_fsm)) begin
tmp_buckets_0_3_reg_265 <= ap_const_lv32_0;
end else if ((ap_ST_st43_fsm_42 == ap_CS_fsm)) begin
tmp_buckets_0_3_reg_265 <= next_buckets_0_1_reg_721;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((ap_ST_st24_fsm_23 == ap_CS_fsm)) begin
tmp_buckets_1_3_reg_252 <= ap_const_lv32_0;
end else if ((ap_ST_st43_fsm_42 == ap_CS_fsm)) begin
tmp_buckets_1_3_reg_252 <= next_buckets_1_1_fu_544_p2;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((ap_ST_st46_fsm_45 == ap_CS_fsm)) begin
current_buckets_0_1_reg_741 <= current_buckets_0_1_fu_558_p2;
current_buckets_1_1_reg_746 <= current_buckets_1_1_fu_563_p2;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((ap_ST_st3_fsm_2 == ap_CS_fsm)) begin
current_buckets_0_reg_577 <= grp_nfa_get_initials_fu_356_ap_return_0;
current_buckets_1_reg_582 <= grp_nfa_get_initials_fu_356_ap_return_1;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((ap_ST_st8_fsm_7 == ap_CS_fsm)) begin
i_1_reg_601 <= grp_fu_402_p2;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((ap_ST_st23_fsm_22 == ap_CS_fsm)) begin
j_bit1_ph_reg_227 <= r_bit_reg_630;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((ap_ST_st36_fsm_35 == ap_CS_fsm)) begin
j_bit_reg_685 <= grp_bitset_next_fu_344_ap_return_0;
j_bucket_index_reg_690 <= grp_bitset_next_fu_344_ap_return_1;
j_bucket_reg_695 <= grp_bitset_next_fu_344_ap_return_2;
p_s_reg_700 <= grp_bitset_next_fu_344_ap_return_3;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((~(nfa_forward_buckets_rsp_empty_n == ap_const_logic_0) & (ap_ST_st42_fsm_41 == ap_CS_fsm))) begin
next_buckets_0_1_reg_721 <= next_buckets_0_1_fu_538_p2;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((ap_ST_st39_fsm_38 == ap_CS_fsm)) begin
offset_i_reg_705 <= grp_fu_482_p2;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(sample_rsp_empty_n == ap_const_logic_0))) begin
p_rec_reg_616 <= grp_fu_414_p2;
sym_reg_621 <= sample_datain;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((ap_ST_st22_fsm_21 == ap_CS_fsm)) begin
r_bit_reg_630 <= grp_p_bsf32_hw_fu_368_ap_return;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((((ap_ST_st41_fsm_40 == ap_CS_fsm) & ~(nfa_forward_buckets_rsp_empty_n == ap_const_logic_0)) | (~(nfa_forward_buckets_rsp_empty_n == ap_const_logic_0) & (ap_ST_st42_fsm_41 == ap_CS_fsm)))) begin
reg_374 <= nfa_forward_buckets_datain;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((ap_ST_st12_fsm_11 == ap_CS_fsm)) begin
sample_addr_1_reg_606 <= grp_fu_392_p2;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((ap_ST_st26_fsm_25 == ap_CS_fsm)) begin
state_reg_665 <= grp_fu_463_p2;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(sample_rsp_empty_n == ap_const_logic_0) & ~(tmp_17_i_reg_612 == ap_const_lv1_0))) begin
tmp_17_1_i_reg_626 <= tmp_17_1_i_fu_426_p2;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((ap_ST_st18_fsm_17 == ap_CS_fsm)) begin
tmp_17_i_reg_612 <= tmp_17_i_fu_420_p2;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((ap_ST_st47_fsm_46 == ap_CS_fsm)) begin
tmp_1_reg_751 <= tmp_1_fu_568_p2;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((ap_ST_st48_fsm_47 == ap_CS_fsm)) begin
tmp_2_reg_756 <= tmp_2_fu_572_p2;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((ap_ST_st35_fsm_34 == ap_CS_fsm)) begin
tmp_6_i_reg_680 <= grp_fu_476_p2;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((ap_ST_st24_fsm_23 == ap_CS_fsm)) begin
tmp_7_i_cast_reg_650[0] <= tmp_7_i_cast_fu_444_p1[0];
tmp_7_i_cast_reg_650[1] <= tmp_7_i_cast_fu_444_p1[1];
tmp_7_i_cast_reg_650[2] <= tmp_7_i_cast_fu_444_p1[2];
tmp_7_i_cast_reg_650[3] <= tmp_7_i_cast_fu_444_p1[3];
tmp_7_i_cast_reg_650[4] <= tmp_7_i_cast_fu_444_p1[4];
tmp_7_i_cast_reg_650[5] <= tmp_7_i_cast_fu_444_p1[5];
tmp_7_i_cast_reg_650[6] <= tmp_7_i_cast_fu_444_p1[6];
tmp_7_i_cast_reg_650[7] <= tmp_7_i_cast_fu_444_p1[7];
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((ap_ST_st45_fsm_44 == ap_CS_fsm)) begin
tmp_buckets_0_reg_731 <= grp_nfa_get_finals_fu_362_ap_return_0;
tmp_buckets_1_reg_736 <= grp_nfa_get_finals_fu_362_ap_return_1;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((ap_ST_st5_fsm_4 == ap_CS_fsm)) begin
tmp_s_reg_597 <= tmp_s_fu_397_p2;
end
end
/// ap_done assign process. ///
always @ (ap_start or ap_CS_fsm)
begin
if (((~(ap_const_logic_1 == ap_start) & (ap_ST_st1_fsm_0 == ap_CS_fsm)) | (ap_ST_st50_fsm_49 == ap_CS_fsm))) begin
ap_done = ap_const_logic_1;
end else begin
ap_done = ap_const_logic_0;
end
end
/// ap_idle assign process. ///
always @ (ap_start or ap_CS_fsm)
begin
if ((~(ap_const_logic_1 == ap_start) & (ap_ST_st1_fsm_0 == ap_CS_fsm))) begin
ap_idle = ap_const_logic_1;
end else begin
ap_idle = ap_const_logic_0;
end
end
/// ap_ready assign process. ///
always @ (ap_CS_fsm)
begin
if ((ap_ST_st50_fsm_49 == ap_CS_fsm)) begin
ap_ready = ap_const_logic_1;
end else begin
ap_ready = ap_const_logic_0;
end
end
/// ap_return assign process. ///
always @ (ap_CS_fsm or p_0_reg_332 or ap_return_preg)
begin
if ((ap_ST_st50_fsm_49 == ap_CS_fsm)) begin
ap_return = p_0_reg_332;
end else begin
ap_return = ap_return_preg;
end
end
/// grp_bitset_next_fu_344_ap_ce assign process. ///
always @ (ap_CS_fsm or j_end_phi_fu_312_p4)
begin
if ((((ap_ST_st25_fsm_24 == ap_CS_fsm) & (ap_const_lv1_0 == j_end_phi_fu_312_p4)) | (ap_ST_st26_fsm_25 == ap_CS_fsm) | (ap_ST_st27_fsm_26 == ap_CS_fsm) | (ap_ST_st35_fsm_34 == ap_CS_fsm) | (ap_ST_st36_fsm_35 == ap_CS_fsm) | (ap_ST_st28_fsm_27 == ap_CS_fsm) | (ap_ST_st29_fsm_28 == ap_CS_fsm) | (ap_ST_st30_fsm_29 == ap_CS_fsm) | (ap_ST_st31_fsm_30 == ap_CS_fsm) | (ap_ST_st32_fsm_31 == ap_CS_fsm) | (ap_ST_st33_fsm_32 == ap_CS_fsm) | (ap_ST_st34_fsm_33 == ap_CS_fsm))) begin
grp_bitset_next_fu_344_ap_ce = ap_const_logic_1;
end else begin
grp_bitset_next_fu_344_ap_ce = ap_const_logic_0;
end
end
/// grp_fu_414_ce assign process. ///
always @ (ap_CS_fsm or sample_rsp_empty_n or tmp_s_reg_597)
begin
if (((ap_ST_st18_fsm_17 == ap_CS_fsm) | ((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(sample_rsp_empty_n == ap_const_logic_0)) | ((ap_ST_st12_fsm_11 == ap_CS_fsm) & ~(tmp_s_reg_597 == ap_const_lv1_0)) | (ap_ST_st13_fsm_12 == ap_CS_fsm) | (ap_ST_st14_fsm_13 == ap_CS_fsm) | (ap_ST_st15_fsm_14 == ap_CS_fsm) | (ap_ST_st16_fsm_15 == ap_CS_fsm) | (ap_ST_st17_fsm_16 == ap_CS_fsm))) begin
grp_fu_414_ce = ap_const_logic_1;
end else begin
grp_fu_414_ce = ap_const_logic_0;
end
end
/// grp_nfa_get_initials_fu_356_ap_start assign process. ///
always @ (ap_start or ap_CS_fsm)
begin
if (((ap_ST_st1_fsm_0 == ap_CS_fsm) & ~(ap_start == ap_const_logic_0))) begin
grp_nfa_get_initials_fu_356_ap_start = ap_const_logic_1;
end else begin
grp_nfa_get_initials_fu_356_ap_start = ap_const_logic_0;
end
end
/// grp_p_bsf32_hw_fu_368_ap_ce assign process. ///
always @ (ap_CS_fsm)
begin
if (((ap_ST_st22_fsm_21 == ap_CS_fsm) | (ap_ST_st21_fsm_20 == ap_CS_fsm))) begin
grp_p_bsf32_hw_fu_368_ap_ce = ap_const_logic_1;
end else begin
grp_p_bsf32_hw_fu_368_ap_ce = ap_const_logic_0;
end
end
/// nfa_forward_buckets_address assign process. ///
always @ (ap_CS_fsm or nfa_forward_buckets_rsp_empty_n or tmp_4_i_cast_fu_509_p1 or tmp_8_i_cast_fu_527_p1)
begin
if (((ap_ST_st41_fsm_40 == ap_CS_fsm) & ~(nfa_forward_buckets_rsp_empty_n == ap_const_logic_0))) begin
nfa_forward_buckets_address = tmp_8_i_cast_fu_527_p1;
end else if ((ap_ST_st40_fsm_39 == ap_CS_fsm)) begin
nfa_forward_buckets_address = tmp_4_i_cast_fu_509_p1;
end else begin
nfa_forward_buckets_address = 'bx;
end
end
/// nfa_forward_buckets_req_write assign process. ///
always @ (ap_CS_fsm or nfa_forward_buckets_rsp_empty_n)
begin
if ((((ap_ST_st41_fsm_40 == ap_CS_fsm) & ~(nfa_forward_buckets_rsp_empty_n == ap_const_logic_0)) | (ap_ST_st40_fsm_39 == ap_CS_fsm))) begin
nfa_forward_buckets_req_write = ap_const_logic_1;
end else begin
nfa_forward_buckets_req_write = ap_const_logic_0;
end
end
/// nfa_forward_buckets_rsp_read assign process. ///
always @ (ap_CS_fsm or nfa_forward_buckets_rsp_empty_n)
begin
if ((((ap_ST_st41_fsm_40 == ap_CS_fsm) & ~(nfa_forward_buckets_rsp_empty_n == ap_const_logic_0)) | (~(nfa_forward_buckets_rsp_empty_n == ap_const_logic_0) & (ap_ST_st42_fsm_41 == ap_CS_fsm)))) begin
nfa_forward_buckets_rsp_read = ap_const_logic_1;
end else begin
nfa_forward_buckets_rsp_read = ap_const_logic_0;
end
end
/// sample_req_write assign process. ///
always @ (ap_CS_fsm)
begin
if ((ap_ST_st18_fsm_17 == ap_CS_fsm)) begin
sample_req_write = ap_const_logic_1;
end else begin
sample_req_write = ap_const_logic_0;
end
end
/// sample_rsp_read assign process. ///
always @ (ap_CS_fsm or sample_rsp_empty_n)
begin
if (((ap_ST_st19_fsm_18 == ap_CS_fsm) & ~(sample_rsp_empty_n == ap_const_logic_0))) begin
sample_rsp_read = ap_const_logic_1;
end else begin
sample_rsp_read = ap_const_logic_0;
end
end
always @ (ap_start or ap_CS_fsm or nfa_forward_buckets_rsp_empty_n or sample_rsp_empty_n or tmp_s_reg_597 or tmp_17_i_reg_612 or tmp_17_1_i_reg_626 or j_end_phi_fu_312_p4 or any_phi_fu_324_p4)
begin
case (ap_CS_fsm)
ap_ST_st1_fsm_0 :
if (~(ap_start == ap_const_logic_0)) begin
ap_NS_fsm = ap_ST_st2_fsm_1;
end else begin
ap_NS_fsm = ap_ST_st1_fsm_0;
end
ap_ST_st2_fsm_1 :
ap_NS_fsm = ap_ST_st3_fsm_2;
ap_ST_st3_fsm_2 :
ap_NS_fsm = ap_ST_st4_fsm_3;
ap_ST_st4_fsm_3 :
ap_NS_fsm = ap_ST_st5_fsm_4;
ap_ST_st5_fsm_4 :
ap_NS_fsm = ap_ST_st6_fsm_5;
ap_ST_st6_fsm_5 :
ap_NS_fsm = ap_ST_st7_fsm_6;
ap_ST_st7_fsm_6 :
ap_NS_fsm = ap_ST_st8_fsm_7;
ap_ST_st8_fsm_7 :
ap_NS_fsm = ap_ST_st9_fsm_8;
ap_ST_st9_fsm_8 :
ap_NS_fsm = ap_ST_st10_fsm_9;
ap_ST_st10_fsm_9 :
ap_NS_fsm = ap_ST_st11_fsm_10;
ap_ST_st11_fsm_10 :
ap_NS_fsm = ap_ST_st12_fsm_11;
ap_ST_st12_fsm_11 :
if ((tmp_s_reg_597 == ap_const_lv1_0)) begin
ap_NS_fsm = ap_ST_st44_fsm_43;
end else begin
ap_NS_fsm = ap_ST_st13_fsm_12;
end
ap_ST_st13_fsm_12 :
ap_NS_fsm = ap_ST_st14_fsm_13;
ap_ST_st14_fsm_13 :
ap_NS_fsm = ap_ST_st15_fsm_14;
ap_ST_st15_fsm_14 :
ap_NS_fsm = ap_ST_st16_fsm_15;
ap_ST_st16_fsm_15 :
ap_NS_fsm = ap_ST_st17_fsm_16;
ap_ST_st17_fsm_16 :
ap_NS_fsm = ap_ST_st18_fsm_17;
ap_ST_st18_fsm_17 :
ap_NS_fsm = ap_ST_st19_fsm_18;
ap_ST_st19_fsm_18 :
if ((~(sample_rsp_empty_n == ap_const_logic_0) & (tmp_17_i_reg_612 == ap_const_lv1_0))) begin
ap_NS_fsm = ap_ST_st21_fsm_20;
end else if ((~(sample_rsp_empty_n == ap_const_logic_0) & ~(tmp_17_i_reg_612 == ap_const_lv1_0))) begin
ap_NS_fsm = ap_ST_st20_fsm_19;
end else begin
ap_NS_fsm = ap_ST_st19_fsm_18;
end
ap_ST_st20_fsm_19 :
if (~(tmp_17_1_i_reg_626 == ap_const_lv1_0)) begin
ap_NS_fsm = ap_ST_st24_fsm_23;
end else begin
ap_NS_fsm = ap_ST_st21_fsm_20;
end
ap_ST_st21_fsm_20 :
ap_NS_fsm = ap_ST_st22_fsm_21;
ap_ST_st22_fsm_21 :
ap_NS_fsm = ap_ST_st23_fsm_22;
ap_ST_st23_fsm_22 :
ap_NS_fsm = ap_ST_st24_fsm_23;
ap_ST_st24_fsm_23 :
ap_NS_fsm = ap_ST_st25_fsm_24;
ap_ST_st25_fsm_24 :
if ((~(ap_const_lv1_0 == j_end_phi_fu_312_p4) & ~(ap_const_lv1_0 == any_phi_fu_324_p4))) begin
ap_NS_fsm = ap_ST_st5_fsm_4;
end else if ((~(ap_const_lv1_0 == j_end_phi_fu_312_p4) & (ap_const_lv1_0 == any_phi_fu_324_p4))) begin
ap_NS_fsm = ap_ST_st50_fsm_49;
end else begin
ap_NS_fsm = ap_ST_st26_fsm_25;
end
ap_ST_st26_fsm_25 :
ap_NS_fsm = ap_ST_st27_fsm_26;
ap_ST_st27_fsm_26 :
ap_NS_fsm = ap_ST_st28_fsm_27;
ap_ST_st28_fsm_27 :
ap_NS_fsm = ap_ST_st29_fsm_28;
ap_ST_st29_fsm_28 :
ap_NS_fsm = ap_ST_st30_fsm_29;
ap_ST_st30_fsm_29 :
ap_NS_fsm = ap_ST_st31_fsm_30;
ap_ST_st31_fsm_30 :
ap_NS_fsm = ap_ST_st32_fsm_31;
ap_ST_st32_fsm_31 :
ap_NS_fsm = ap_ST_st33_fsm_32;
ap_ST_st33_fsm_32 :
ap_NS_fsm = ap_ST_st34_fsm_33;
ap_ST_st34_fsm_33 :
ap_NS_fsm = ap_ST_st35_fsm_34;
ap_ST_st35_fsm_34 :
ap_NS_fsm = ap_ST_st36_fsm_35;
ap_ST_st36_fsm_35 :
ap_NS_fsm = ap_ST_st37_fsm_36;
ap_ST_st37_fsm_36 :
ap_NS_fsm = ap_ST_st38_fsm_37;
ap_ST_st38_fsm_37 :
ap_NS_fsm = ap_ST_st39_fsm_38;
ap_ST_st39_fsm_38 :
ap_NS_fsm = ap_ST_st40_fsm_39;
ap_ST_st40_fsm_39 :
ap_NS_fsm = ap_ST_st41_fsm_40;
ap_ST_st41_fsm_40 :
if (~(nfa_forward_buckets_rsp_empty_n == ap_const_logic_0)) begin
ap_NS_fsm = ap_ST_st42_fsm_41;
end else begin
ap_NS_fsm = ap_ST_st41_fsm_40;
end
ap_ST_st42_fsm_41 :
if (~(nfa_forward_buckets_rsp_empty_n == ap_const_logic_0)) begin
ap_NS_fsm = ap_ST_st43_fsm_42;
end else begin
ap_NS_fsm = ap_ST_st42_fsm_41;
end
ap_ST_st43_fsm_42 :
ap_NS_fsm = ap_ST_st25_fsm_24;
ap_ST_st44_fsm_43 :
ap_NS_fsm = ap_ST_st45_fsm_44;
ap_ST_st45_fsm_44 :
ap_NS_fsm = ap_ST_st46_fsm_45;
ap_ST_st46_fsm_45 :
ap_NS_fsm = ap_ST_st47_fsm_46;
ap_ST_st47_fsm_46 :
ap_NS_fsm = ap_ST_st48_fsm_47;
ap_ST_st48_fsm_47 :
ap_NS_fsm = ap_ST_st49_fsm_48;
ap_ST_st49_fsm_48 :
ap_NS_fsm = ap_ST_st50_fsm_49;
ap_ST_st50_fsm_49 :
ap_NS_fsm = ap_ST_st1_fsm_0;
default :
ap_NS_fsm = 'bx;
endcase
end
assign agg_result_bucket_index_0_lcssa4_i_cast_cast_fu_432_p1 = $unsigned(agg_result_bucket_index_0_lcssa4_i_reg_190);
assign any_phi_fu_324_p4 = any_reg_319;
assign current_buckets_0_1_fu_558_p2 = (next_buckets_0_reg_168 & tmp_buckets_0_reg_731);
assign current_buckets_1_1_fu_563_p2 = (next_buckets_1_reg_158 & tmp_buckets_1_reg_736);
assign grp_bitset_next_fu_344_p_read = next_buckets_1_reg_158;
assign grp_bitset_next_fu_344_r_bit = j_bit1_reg_299;
assign grp_bitset_next_fu_344_r_bucket = j_bucket1_reg_278;
assign grp_bitset_next_fu_344_r_bucket_index = j_bucket_index1_reg_289;
assign grp_fu_392_ce = ap_const_logic_1;
assign grp_fu_392_p0 = p_01_rec_reg_146;
assign grp_fu_392_p1 = empty;
assign grp_fu_402_ce = ap_const_logic_1;
assign grp_fu_402_p0 = i_reg_134;
assign grp_fu_402_p1 = ap_const_lv16_1;
assign grp_fu_414_p0 = p_01_rec_reg_146;
assign grp_fu_414_p1 = ap_const_lv32_1;
assign grp_fu_463_ce = ap_const_logic_1;
assign grp_fu_463_p0 = {{tmp_5_fu_447_p1}, {ap_const_lv5_0}};
assign grp_fu_463_p1 = j_bit1_reg_299[5:0];
assign grp_fu_476_ce = ap_const_logic_1;
assign grp_fu_476_p0 = grp_fu_476_p00;
assign grp_fu_476_p00 = $unsigned(nfa_symbols);
assign grp_fu_476_p1 = grp_fu_476_p10;
assign grp_fu_476_p10 = $unsigned(state_reg_665);
assign grp_fu_482_ce = ap_const_logic_1;
assign grp_fu_482_p0 = tmp_6_i_reg_680;
assign grp_fu_482_p1 = tmp_7_i_cast_reg_650;
assign grp_nfa_get_finals_fu_362_ap_ce = ap_const_logic_1;
assign grp_nfa_get_finals_fu_362_ap_start = grp_nfa_get_finals_fu_362_ap_start_ap_start_reg;
assign grp_nfa_get_finals_fu_362_nfa_finals_buckets_datain = nfa_finals_buckets_datain;
assign grp_nfa_get_finals_fu_362_nfa_finals_buckets_req_full_n = nfa_finals_buckets_req_full_n;
assign grp_nfa_get_finals_fu_362_nfa_finals_buckets_rsp_empty_n = nfa_finals_buckets_rsp_empty_n;
assign grp_nfa_get_initials_fu_356_ap_ce = ap_const_logic_1;
assign grp_nfa_get_initials_fu_356_nfa_initials_buckets_datain = nfa_initials_buckets_datain;
assign grp_nfa_get_initials_fu_356_nfa_initials_buckets_req_full_n = nfa_initials_buckets_req_full_n;
assign grp_nfa_get_initials_fu_356_nfa_initials_buckets_rsp_empty_n = nfa_initials_buckets_rsp_empty_n;
assign grp_p_bsf32_hw_fu_368_bus_r = bus_assign_reg_178;
assign j_bit1_ph_cast_fu_440_p1 = $unsigned(j_bit1_ph_reg_227);
assign j_bucket_index1_ph_cast_fu_436_p1 = $unsigned(j_bucket_index1_ph_reg_216);
assign j_end_phi_fu_312_p4 = j_end_reg_309;
assign next_buckets_0_1_fu_538_p2 = (tmp_buckets_0_3_reg_265 | reg_374);
assign next_buckets_1_1_fu_544_p2 = (tmp_buckets_1_3_reg_252 | reg_374);
assign nfa_finals_buckets_address = grp_nfa_get_finals_fu_362_nfa_finals_buckets_address;
assign nfa_finals_buckets_dataout = grp_nfa_get_finals_fu_362_nfa_finals_buckets_dataout;
assign nfa_finals_buckets_req_din = grp_nfa_get_finals_fu_362_nfa_finals_buckets_req_din;
assign nfa_finals_buckets_req_write = grp_nfa_get_finals_fu_362_nfa_finals_buckets_req_write;
assign nfa_finals_buckets_rsp_read = grp_nfa_get_finals_fu_362_nfa_finals_buckets_rsp_read;
assign nfa_finals_buckets_size = grp_nfa_get_finals_fu_362_nfa_finals_buckets_size;
assign nfa_forward_buckets_dataout = ap_const_lv32_0;
assign nfa_forward_buckets_req_din = ap_const_logic_0;
assign nfa_forward_buckets_size = ap_const_lv32_1;
assign nfa_initials_buckets_address = grp_nfa_get_initials_fu_356_nfa_initials_buckets_address;
assign nfa_initials_buckets_dataout = grp_nfa_get_initials_fu_356_nfa_initials_buckets_dataout;
assign nfa_initials_buckets_req_din = grp_nfa_get_initials_fu_356_nfa_initials_buckets_req_din;
assign nfa_initials_buckets_req_write = grp_nfa_get_initials_fu_356_nfa_initials_buckets_req_write;
assign nfa_initials_buckets_rsp_read = grp_nfa_get_initials_fu_356_nfa_initials_buckets_rsp_read;
assign nfa_initials_buckets_size = grp_nfa_get_initials_fu_356_nfa_initials_buckets_size;
assign sample_address = sample_addr_1_reg_606;
assign sample_dataout = ap_const_lv8_0;
assign sample_req_din = ap_const_logic_0;
assign sample_size = ap_const_lv32_1;
assign tmp_17_1_i_fu_426_p2 = (next_buckets_1_reg_158 == ap_const_lv32_0? 1'b1: 1'b0);
assign tmp_17_i_fu_420_p2 = (next_buckets_0_reg_168 == ap_const_lv32_0? 1'b1: 1'b0);
assign tmp_1_fu_568_p2 = (current_buckets_1_1_reg_746 | current_buckets_0_1_reg_741);
assign tmp_2_fu_572_p2 = (tmp_1_reg_751 != ap_const_lv32_0? 1'b1: 1'b0);
assign tmp_4_i_cast_fu_509_p1 = $unsigned(tmp_4_i_fu_502_p3);
assign tmp_4_i_fu_502_p3 = {{offset_i_reg_705}, {ap_const_lv1_0}};
assign tmp_5_fu_447_p1 = j_bucket_index1_reg_289[0:0];
assign tmp_7_i_cast_fu_444_p1 = $unsigned(sym_reg_621);
assign tmp_8_i_cast_fu_527_p1 = $unsigned(tmp_8_i_fu_520_p3);
assign tmp_8_i_fu_520_p3 = {{offset_i_reg_705}, {ap_const_lv1_1}};
assign tmp_s_fu_397_p2 = (i_reg_134 < length_r? 1'b1: 1'b0);
always @ (posedge ap_clk)
begin
tmp_7_i_cast_reg_650[13:8] <= 6'b000000;
end
endmodule
|
module sky130_fd_sc_hdll__decap (
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
input VPWR;
input VGND;
input VPB ;
input VNB ;
// No contents.
endmodule
|
module sky130_fd_sc_hd__a22o (
X ,
A1 ,
A2 ,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire and0_out ;
wire and1_out ;
wire or0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
and and0 (and0_out , B1, B2 );
and and1 (and1_out , A1, A2 );
or or0 (or0_out_X , and1_out, and0_out );
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, or0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
|
module ARM_CU_ALU( input MFC , Reset , Clk , MEMSTORE,MEMLOAD,MEMDAT, output MEMADD, MFA,READ_WRITE,WORD_BYTE);
ARM_CU_ALU CPU( MFC , Reset , Clk , MEMSTORE,MEMLOAD,MEMDAT,MEMADD, MFA,READ_WRITE,WORD_BYTE);
initial fork
Reset =1; Clk = 0; MEMSTORE=0;MEMLOAD=0;MEMDAT=0;MFC=0;
#1 Reset = 0;
join
always@(posedge MFA)begin
case(MEMADD)
8'h00:begin
#1 MEMDAT = 32'b11100010_00000001_00000000_00000000 ; #1 MEMLOAD = 1;
#5 MFC = 1 ; #5 MEMLOAD=0;
#7 MFC = 0 ;
end
8'h01:begin
#1 MEMDAT = 32'b11100011_10000000_00010000_00101000 ; #1 MEMLOAD = 1;
#5 MFC = 1 ; #5 MEMLOAD=0;
#7 MFC = 0 ;
end
8'h02:begin
#1 MEMDAT = 32'b11100111_11010001_00100000_00000000 ; #1 MEMLOAD = 1;
#5 MFC = 1 ; #5 MEMLOAD=0;
#7 MFC = 0 ;
end
8'h03:begin
#1 MEMDAT = 32'b11100101_11010001_00110000_00000010 ; #1 MEMLOAD = 1;
#5 MFC = 1 ; #5 MEMLOAD=0;
#7 MFC = 0 ;
end
8'h04:begin
#1 MEMDAT = 32'b11100000_10000000_01010000_00000000 ; #1 MEMLOAD = 1;
#5 MFC = 1 ; #5 MEMLOAD=0;
#7 MFC = 0 ;
end
8'h05:begin
#1 MEMDAT = 32'b11100000_10000010_01010000_00000101; #1 MEMLOAD = 1;
#5 MFC = 1 ; #5 MEMLOAD=0;
#7 MFC = 0 ;
end
8'h06:begin
#1 MEMDAT = 32'b11100010_01010011_00110000_00000001 ; #1 MEMLOAD = 1;
#5 MFC = 1 ; #5 MEMLOAD=0;
#7 MFC = 0 ;
end
8'h07:begin
#1 MEMDAT = 32'b00011010_11111111_11111111_11111101 ; #1 MEMLOAD = 1;
#5 MFC = 1 ; #5 MEMLOAD=0;
#7 MFC = 0 ;
end
8'h08:begin
#1 MEMDAT = 32'b11100101_11000001_01010000_00000011 ; #1 MEMLOAD = 1;
#5 MFC = 1 ; #5 MEMLOAD=0;
#7 MFC = 0 ;
end
8'h09:begin
#1 MEMDAT = 32'b11101010_00000000_00000000_00000001 ; #1 MEMLOAD = 1;
#5 MFC = 1 ; #5 MEMLOAD=0;
#7 MFC = 0 ;
end
8'h0A:begin
#1 MEMDAT = 32'b00001011_00000101_00000111_00000100 ; #1 MEMLOAD = 1;
#5 MFC = 1 ; #5 MEMLOAD=0;
#7 MFC = 0 ;
end
8'h0B:begin
#1 MEMDAT = 32'b11101010_11111111_11111111_11111111 ; #1 MEMLOAD = 1;
#5 MFC = 1 ; #5 MEMLOAD=0;
#7 MFC = 0 ;
end
default:begin
#1 MEMDAT = 32'h00000000 ; #1 MEMLOAD = 1;
#5 MFC = 1 ; #5 MEMLOAD=0;
#7 MFC = 0 ;
end
endcase
end
always
#1 Clk = ~Clk;
initial #sim_time $finish;
initial begin
$dumpfile("ARM_CU_ALU_TestBench2.vcd");
$dumpvars(0,ARM_CU_ALU_TestBench2);
$display(" Test Results" );
$monitor("input MFC =%d, Reset =%d, Clk =%d, MEMSTORE=%d,MEMLOAD=%d,MEMDAT=%d, output MEMADD=%d, MFA=%d,READ_WRITE=%d,WORD_BYTE=%d,",MFC , Reset , Clk , MEMSTORE,MEMLOAD,MEMDAT, MEMADD, MFA,READ_WRITE,WORD_BYTE);
end
endmodule
|
module sky130_fd_sc_hd__lpflow_clkinvkapwr (
Y,
A
);
// Module ports
output Y;
input A;
// Module supplies
supply1 KAPWR;
supply1 VPWR ;
supply0 VGND ;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire not0_out_Y;
// Name Output Other arguments
not not0 (not0_out_Y, A );
buf buf0 (Y , not0_out_Y );
endmodule
|
module sky130_fd_sc_hs__o2111ai (
VPWR,
VGND,
Y ,
A1 ,
A2 ,
B1 ,
C1 ,
D1
);
// Module ports
input VPWR;
input VGND;
output Y ;
input A1 ;
input A2 ;
input B1 ;
input C1 ;
input D1 ;
// Local signals
wire C1 or0_out ;
wire nand0_out_Y ;
wire u_vpwr_vgnd0_out_Y;
// Name Output Other arguments
or or0 (or0_out , A2, A1 );
nand nand0 (nand0_out_Y , C1, B1, D1, or0_out );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_Y, nand0_out_Y, VPWR, VGND);
buf buf0 (Y , u_vpwr_vgnd0_out_Y );
endmodule
|
module SortX16 # (
parameter DSIZE = 18,
parameter OFFSET = 8
)(
input [DSIZE-1:0] a0,
input [DSIZE-1:0] a1,
input [DSIZE-1:0] a2,
input [DSIZE-1:0] a3,
input [DSIZE-1:0] a4,
input [DSIZE-1:0] a5,
input [DSIZE-1:0] a6,
input [DSIZE-1:0] a7,
input [DSIZE-1:0] a8,
input [DSIZE-1:0] a9,
input [DSIZE-1:0] a10,
input [DSIZE-1:0] a11,
input [DSIZE-1:0] a12,
input [DSIZE-1:0] a13,
input [DSIZE-1:0] a14,
input [DSIZE-1:0] a15,
output wire [DSIZE-1:0] sort0,
output wire [DSIZE-1:0] sort1,
output wire [DSIZE-1:0] sort2,
output wire [DSIZE-1:0] sort3,
output wire [DSIZE-1:0] sort4,
output wire [DSIZE-1:0] sort5,
output wire [DSIZE-1:0] sort6,
output wire [DSIZE-1:0] sort7,
output wire [DSIZE-1:0] sort8,
output wire [DSIZE-1:0] sort9,
output wire [DSIZE-1:0] sort10,
output wire [DSIZE-1:0] sort11,
output wire [DSIZE-1:0] sort12,
output wire [DSIZE-1:0] sort13,
output wire [DSIZE-1:0] sort14,
output wire [DSIZE-1:0] sort15
);
wire [DSIZE-1:0] sortX8_0_0;
wire [DSIZE-1:0] sortX8_0_1;
wire [DSIZE-1:0] sortX8_0_2;
wire [DSIZE-1:0] sortX8_0_3;
wire [DSIZE-1:0] sortX8_0_4;
wire [DSIZE-1:0] sortX8_0_5;
wire [DSIZE-1:0] sortX8_0_6;
wire [DSIZE-1:0] sortX8_0_7;
wire [DSIZE-1:0] sortX8_1_0;
wire [DSIZE-1:0] sortX8_1_1;
wire [DSIZE-1:0] sortX8_1_2;
wire [DSIZE-1:0] sortX8_1_3;
wire [DSIZE-1:0] sortX8_1_4;
wire [DSIZE-1:0] sortX8_1_5;
wire [DSIZE-1:0] sortX8_1_6;
wire [DSIZE-1:0] sortX8_1_7;
wire [DSIZE-1:0] sort0_0;
wire [DSIZE-1:0] sort0_1;
wire [DSIZE-1:0] sort1_0;
wire [DSIZE-1:0] sort1_1;
wire [DSIZE-1:0] sort2_0;
wire [DSIZE-1:0] sort2_1;
wire [DSIZE-1:0] sort3_0;
wire [DSIZE-1:0] sort3_1;
wire [DSIZE-1:0] sort4_0;
wire [DSIZE-1:0] sort4_1;
wire [DSIZE-1:0] sort5_0;
wire [DSIZE-1:0] sort5_1;
wire [DSIZE-1:0] sort6_0;
wire [DSIZE-1:0] sort6_1;
wire [DSIZE-1:0] sort7_0;
wire [DSIZE-1:0] sort7_1;
// divide sort
SortX8 # (
.DSIZE (DSIZE),
.OFFSET(OFFSET)
) sortX8_inst0 (
.a0 (a0),
.a1 (a1),
.a2 (a2),
.a3 (a3),
.a4 (a4),
.a5 (a5),
.a6 (a6),
.a7 (a7),
.sort0 (sortX8_0_0),
.sort1 (sortX8_0_1),
.sort2 (sortX8_0_2),
.sort3 (sortX8_0_3),
.sort4 (sortX8_0_4),
.sort5 (sortX8_0_5),
.sort6 (sortX8_0_6),
.sort7 (sortX8_0_7)
);
SortX8 # (
.DSIZE (DSIZE),
.OFFSET(OFFSET)
) sortX8_inst1 (
.a0 (a8),
.a1 (a9),
.a2 (a10),
.a3 (a11),
.a4 (a12),
.a5 (a13),
.a6 (a14),
.a7 (a15),
.sort0 (sortX8_1_0),
.sort1 (sortX8_1_1),
.sort2 (sortX8_1_2),
.sort3 (sortX8_1_3),
.sort4 (sortX8_1_4),
.sort5 (sortX8_1_5),
.sort6 (sortX8_1_6),
.sort7 (sortX8_1_7)
);
// merge
SortElement # (
.DSIZE (DSIZE),
.OFFSET(OFFSET)
) sort_inst0 (
.a(sortX8_0_0),
.b(sortX8_1_7),
.sort0(sort0_0),
.sort1(sort0_1)
);
SortElement # (
.DSIZE (DSIZE),
.OFFSET(OFFSET)
) sort_inst1 (
.a(sortX8_0_1),
.b(sortX8_1_6),
.sort0(sort1_0),
.sort1(sort1_1)
);
SortElement # (
.DSIZE (DSIZE),
.OFFSET(OFFSET)
) sort_inst2 (
.a(sortX8_0_2),
.b(sortX8_1_5),
.sort0(sort2_0),
.sort1(sort2_1)
);
SortElement # (
.DSIZE (DSIZE),
.OFFSET(OFFSET)
) sort_inst3 (
.a(sortX8_0_3),
.b(sortX8_1_4),
.sort0(sort3_0),
.sort1(sort3_1)
);
SortElement # (
.DSIZE (DSIZE),
.OFFSET(OFFSET)
) sort_inst4 (
.a(sortX8_0_4),
.b(sortX8_1_3),
.sort0(sort4_0),
.sort1(sort4_1)
);
SortElement # (
.DSIZE (DSIZE),
.OFFSET(OFFSET)
) sort_inst5 (
.a(sortX8_0_5),
.b(sortX8_1_2),
.sort0(sort5_0),
.sort1(sort5_1)
);
SortElement # (
.DSIZE (DSIZE),
.OFFSET(OFFSET)
) sort_inst6 (
.a(sortX8_0_6),
.b(sortX8_1_1),
.sort0(sort6_0),
.sort1(sort6_1)
);
SortElement # (
.DSIZE (DSIZE),
.OFFSET(OFFSET)
) sort_inst7 (
.a(sortX8_0_7),
.b(sortX8_1_0),
.sort0(sort7_0),
.sort1(sort7_1)
);
// bitonic
BitonicSortX8 # (
.DSIZE (DSIZE),
.OFFSET(OFFSET)
) bitonicsortx8_inst0 (
.a0 (sort0_0),
.a1 (sort1_0),
.a2 (sort2_0),
.a3 (sort3_0),
.a4 (sort4_0),
.a5 (sort5_0),
.a6 (sort6_0),
.a7 (sort7_0),
.sort0 (sort0),
.sort1 (sort1),
.sort2 (sort2),
.sort3 (sort3),
.sort4 (sort4),
.sort5 (sort5),
.sort6 (sort6),
.sort7 (sort7)
);
BitonicSortX8 # (
.DSIZE (DSIZE),
.OFFSET(OFFSET)
) bitonicsortx8_inst1 (
.a0 (sort7_1),
.a1 (sort6_1),
.a2 (sort5_1),
.a3 (sort4_1),
.a4 (sort3_1),
.a5 (sort2_1),
.a6 (sort1_1),
.a7 (sort0_1),
.sort0 (sort8),
.sort1 (sort9),
.sort2 (sort10),
.sort3 (sort11),
.sort4 (sort12),
.sort5 (sort13),
.sort6 (sort14),
.sort7 (sort15)
);
endmodule
|
module add4 ( o, a, b );
output [15:0] o;
input [15:0] a;
input [15:0] b;
wire n1, n2, n3, n4, n5, n6, n7,
n8, n9, n10, n11, n12, n13,
n14, n15, n16, n17, n18, n19,
n20, n21, n22, n23, n24, n25,
n26, n27, n28, n29, n30, n31,
n32, n33, n34, n35, n36, n37,
n38, n39, n40, n41, n42, n43,
n44, n45, n46, n47, n48, n49,
n50, n51, n52, n53, n54, n55,
n56, n57, n58, n59, n60, n61,
n62, n63, n64, n65, n66, n67,
n68, n69, n70, n71, n72, n73,
n74, n75, n76, n77, n78, n79,
n80, n81, n82, n83, n84, n85,
n86, n87, n88, n89, n90, n91,
n92, n93, n94, n95, n96, n97,
n98, n99, n100, n101, n102, n103,
n104, n105, n106, n107, n108,
n109, n110, n111, n112, n113,
n114, n115, n116, n117, n118,
n119, n120, n121, n122, n123,
n124, n125, n126, n127, n128,
n129, n130, n131, n132, n133,
n134, n135, n136, n137, n138,
n139, n140, n141, n142, n143,
n144, n145, n146, n147, n148,
n149, n150, n151, n152, n153,
n154, n155, n156, n157, n158,
n159, n160, n161, n162, n163,
n164;
wire a0,a1, a2, a3, a4, a5, a6, a7,
a8, a9, a10, a11, a12, a13,
a14, a15;
wire b0,b1, b2, b3, b4, b5, b6, b7,
b8, b9, b10, b11, b12, b13,
b14, b15;
wire o0,o1, o2, o3, o4, o5, o6, o7,
o8, o9, o10, o11, o12, o13,
o14, o15;
buf #(0.716) G0 ( a0, a[0]);
buf #(0.716) G1 ( a1, a[0]);
buf #(0.716) G2 ( a2, a[1]);
buf #(0.716) G3 ( a3, a[1]);
buf #(0.716) G4 ( a4, a[2]);
buf #(0.716) G5 ( a5, a[2]);
buf #(0.716) G6 ( a6, a[3]);
buf #(0.716) G7 ( a7, a[3]);
buf #(0.716) G8 ( a8, a[4]);
buf #(0.716) G9 ( a9, a[4]);
buf #(0.716) G10 ( a10, a[5]);
buf #(0.716) G11 ( a11, a[5]);
buf #(0.716) G12 ( a12, a[6]);
buf #(0.716) G13 ( a13, a[6]);
buf #(0.716) G14 ( a14, a[7]);
buf #(0.716) G15 ( a15, a[7]);
buf #(0.716) H0 ( b0, b[0]);
buf #(0.716) H1 ( b1, b[0]);
buf #(0.716) H2 ( b2, b[1]);
buf #(0.716) H3 ( b3, b[1]);
buf #(0.716) H4 ( b4, b[2]);
buf #(0.716) H5 ( b5, b[2]);
buf #(0.716) H6 ( b6, b[3]);
buf #(0.716) H7 ( b7, b[3]);
buf #(0.716) H8 ( b8, b[4]);
buf #(0.716) H9 ( b9, b[4]);
buf #(0.716) H10 ( b10, b[5]);
buf #(0.716) H11 ( b11, b[5]);
buf #(0.716) H12 ( b12, b[6]);
buf #(0.716) H13 ( b13, b[6]);
buf #(0.716) H14 ( b14, b[7]);
buf #(0.716) H15 ( b15, b[7]);
nand #(0.716) K0 ( o[0],o0,o1,o2,o3);
nand #(0.716) K1 ( o[1],o4,o5,o6,o7);
nand #(0.716) K2 ( o[2],o8,o9,o10,o11);
nand #(0.716) K3 ( o[3],o12,o13,o14,o15);
not #(1.000) U4 ( n60, n160 );
nor #(1.000) U5 ( n160, n161, n162 );
not #(1.000) U6 ( n52, n156 );
not #(1.000) U7 ( n45, n152 );
not #(1.000) U8 ( n38, n148 );
not #(1.000) U9 ( n31, n144 );
not #(1.000) U10 ( n24, n140 );
not #(1.000) U11 ( n17, n136 );
not #(1.000) U12 ( n10, n132 );
not #(1.000) U13 ( n109, n107 );
not #(1.000) U14 ( n98, n96 );
not #(1.000) U15 ( n87, n85 );
not #(1.000) U16 ( n73, n71 );
not #(1.000) U17 ( n120, n118 );
nor #(1.000) U18 ( o2, n50, n51 );
and #(1.000) U19 ( n51, n52, n53 );
nor #(1.000) U20 ( n50, n52, n53 );
nand #(1.000) U21 ( n53, n54, n55 );
nor #(1.000) U22 ( o3, n43, n44 );
and #(1.000) U23 ( n44, n45, n46 );
nor #(1.000) U24 ( n43, n45, n46 );
nand #(1.000) U25 ( n46, n47, n48 );
nor #(1.000) U26 ( o4, n36, n37 );
and #(1.000) U27 ( n37, n38, n39 );
nor #(1.000) U28 ( n36, n38, n39 );
nand #(1.000) U29 ( n39, n40, n41 );
nor #(1.000) U30 ( o5, n29, n30 );
and #(1.000) U31 ( n30, n31, n32 );
nor #(1.000) U32 ( n29, n31, n32 );
nand #(1.000) U33 ( n32, n33, n34 );
nor #(1.000) U34 ( o6, n22, n23 );
and #(1.000) U35 ( n23, n24, n25 );
nor #(1.000) U36 ( n22, n24, n25 );
nand #(1.000) U37 ( n25, n26, n27 );
nor #(1.000) U38 ( o7, n15, n16 );
and #(1.000) U39 ( n16, n17, n18 );
nor #(1.000) U40 ( n15, n17, n18 );
nand #(1.000) U41 ( n18, n19, n20 );
nor #(1.000) U42 ( o8, n8, n9 );
and #(1.000) U43 ( n9, n10, n11 );
nor #(1.000) U44 ( n8, n10, n11 );
nand #(1.000) U45 ( n11, n12, n13 );
nor #(1.000) U46 ( o9, n1, n2 );
and #(1.000) U47 ( n2, n3, n4 );
nor #(1.000) U48 ( n1, n3, n4 );
nand #(1.000) U49 ( n4, n5, n6 );
nor #(1.000) U50 ( o10, n121, n122 );
and #(1.000) U51 ( n122, n120, n123 );
nor #(1.000) U52 ( n121, n120, n123 );
nand #(1.000) U53 ( n123, n124, n125 );
nor #(1.000) U54 ( o11, n110, n111 );
and #(1.000) U55 ( n111, n109, n112 );
nor #(1.000) U56 ( n110, n109, n112 );
nand #(1.000) U57 ( n112, n113, n114 );
nor #(1.000) U58 ( o12, n99, n100 );
and #(1.000) U59 ( n100, n98, n101 );
nor #(1.000) U60 ( n99, n98, n101 );
nand #(1.000) U61 ( n101, n102, n103 );
nor #(1.000) U62 ( o13, n88, n89 );
and #(1.000) U63 ( n89, n87, n90 );
nor #(1.000) U64 ( n88, n87, n90 );
nand #(1.000) U65 ( n90, n91, n92 );
nor #(1.000) U66 ( o14, n77, n78 );
and #(1.000) U67 ( n78, n73, n79 );
nor #(1.000) U68 ( n77, n73, n79 );
nand #(1.000) U69 ( n79, n80, n81 );
nor #(1.000) U70 ( o15, n64, n65 );
and #(1.000) U71 ( n65, n66, n67 );
nor #(1.000) U72 ( n64, n67, n66 );
nand #(1.000) U73 ( n66, n68, n69 );
nand #(1.000) U74 ( o1, n57, n58 );
or #(1.000) U75 ( n58, n59, n60 );
nand #(1.000) U76 ( n57, n59, n60 );
nand #(1.000) U77 ( n59, n61, n62 );
nand #(1.000) U78 ( n3, n129, n130 );
nand #(1.000) U79 ( n129, a8, n10 );
nand #(1.000) U80 ( n130, b8, n131 );
nand #(1.000) U81 ( n131, n132, n14 );
and #(1.000) U82 ( n156, n157, n158 );
nand #(1.000) U83 ( n158, b1, n159 );
nand #(1.000) U84 ( n157, a1, n160 );
nand #(1.000) U85 ( n159, n63, n60 );
and #(1.000) U86 ( n152, n153, n154 );
nand #(1.000) U87 ( n153, a2, n52 );
nand #(1.000) U88 ( n154, b2, n155 );
nand #(1.000) U89 ( n155, n156, n56 );
and #(1.000) U90 ( n148, n149, n150 );
nand #(1.000) U91 ( n149, a3, n45 );
nand #(1.000) U92 ( n150, b3, n151 );
nand #(1.000) U93 ( n151, n152, n49 );
and #(1.000) U94 ( n144, n145, n146 );
nand #(1.000) U95 ( n145, a4, n38 );
nand #(1.000) U96 ( n146, b4, n147 );
nand #(1.000) U97 ( n147, n148, n42 );
and #(1.000) U98 ( n107, n115, n116 );
nand #(1.000) U99 ( n115, a10, n120 );
nand #(1.000) U100 ( n116, b10, n117 );
nand #(1.000) U101 ( n117, n118, n119 );
and #(1.000) U102 ( n140, n141, n142 );
nand #(1.000) U103 ( n141, a5, n31 );
nand #(1.000) U104 ( n142, b5, n143 );
nand #(1.000) U105 ( n143, n144, n35 );
and #(1.000) U106 ( n96, n104, n105 );
nand #(1.000) U107 ( n104, a11, n109 );
nand #(1.000) U108 ( n105, b11, n106 );
nand #(1.000) U109 ( n106, n107, n108 );
and #(1.000) U110 ( n136, n137, n138 );
nand #(1.000) U111 ( n137, a6, n24 );
nand #(1.000) U112 ( n138, b6, n139 );
nand #(1.000) U113 ( n139, n140, n28 );
and #(1.000) U114 ( n85, n93, n94 );
nand #(1.000) U115 ( n93, a12, n98 );
nand #(1.000) U116 ( n94, b12, n95 );
nand #(1.000) U117 ( n95, n96, n97 );
and #(1.000) U118 ( n132, n133, n134 );
nand #(1.000) U119 ( n133, a7, n17 );
nand #(1.000) U120 ( n134, b7, n135 );
nand #(1.000) U121 ( n135, n136, n21 );
and #(1.000) U122 ( n71, n82, n83 );
nand #(1.000) U123 ( n82, a13, n87 );
nand #(1.000) U124 ( n83, b13, n84 );
nand #(1.000) U125 ( n84, n85, n86 );
and #(1.000) U126 ( n118, n126, n127 );
nand #(1.000) U127 ( n127, b9, n128 );
nand #(1.000) U128 ( n126, a9, n3 );
or #(1.000) U129 ( n128, n3, a9 );
nand #(1.000) U130 ( n67, n74, n75 );
or #(1.000) U131 ( n74, n76, b15 );
nand #(1.000) U132 ( n75, b15, n76 );
not #(1.000) U133 ( n76, a15 );
nand #(1.000) U134 ( n55, b2, n56 );
nand #(1.000) U135 ( n48, b3, n49 );
nand #(1.000) U136 ( n41, b4, n42 );
nand #(1.000) U137 ( n34, b5, n35 );
nand #(1.000) U138 ( n27, b6, n28 );
nand #(1.000) U139 ( n20, b7, n21 );
nand #(1.000) U140 ( n13, b8, n14 );
nand #(1.000) U141 ( n125, b10, n119 );
nand #(1.000) U142 ( n114, b11, n108 );
nand #(1.000) U143 ( n103, b12, n97 );
nand #(1.000) U144 ( n92, b13, n86 );
nand #(1.000) U145 ( n81, b14, n72 );
nand #(1.000) U146 ( n62, b1, n63 );
nand #(1.000) U147 ( n69, b14, n70 );
nand #(1.000) U148 ( n70, n71, n72 );
nand #(1.000) U149 ( n68, a14, n73 );
not #(1.000) U150 ( n56, a2 );
not #(1.000) U151 ( n49, a3 );
not #(1.000) U152 ( n42, a4 );
not #(1.000) U153 ( n35, a5 );
not #(1.000) U154 ( n28, a6 );
not #(1.000) U155 ( n21, a7 );
not #(1.000) U156 ( n14, a8 );
not #(1.000) U157 ( n119, a10 );
not #(1.000) U158 ( n108, a11 );
not #(1.000) U159 ( n97, a12 );
not #(1.000) U160 ( n86, a13 );
not #(1.000) U161 ( n72, a14 );
nand #(1.000) U162 ( n6, b9, n7 );
not #(1.000) U163 ( n63, a1 );
not #(1.000) U164 ( n161, b0 );
not #(1.000) U165 ( n162, a0 );
nand #(1.000) U166 ( o0, n163, n164 );
nand #(1.000) U167 ( n163, a0, n161 );
nand #(1.000) U168 ( n164, b0, n162 );
or #(1.000) U169 ( n61, n63, b1 );
or #(1.000) U170 ( n54, n56, b2 );
or #(1.000) U171 ( n47, n49, b3 );
or #(1.000) U172 ( n40, n42, b4 );
or #(1.000) U173 ( n33, n35, b5 );
or #(1.000) U174 ( n26, n28, b6 );
or #(1.000) U175 ( n19, n21, b7 );
or #(1.000) U176 ( n12, n14, b8 );
or #(1.000) U177 ( n5, n7, b9 );
or #(1.000) U178 ( n124, n119, b10 );
or #(1.000) U179 ( n113, n108, b11 );
or #(1.000) U180 ( n102, n97, b12 );
or #(1.000) U181 ( n91, n86, b13 );
or #(1.000) U182 ( n80, n72, b14 );
not #(1.000) U183 ( n7, a9 );
wire d1, d2, d3, d4, d5, d6, d7,
d8, d9, d10, d11, d12, d13,
d14, d15, d16, d17, d18, d19,
d20, d21, d22, d23, d24, d25,
d26, d27, d28, d29, d30, d31,
d32, d33, d34, d35, d36, d37,
d38, d39, d40, d41, d42, d43,
d44, d45, d46, d47, d48, d49,
d50, d51, d52, d53, d54, d55,
d56, d57, d58, d59, d60, d61,
d62, d63, d64, d65, d66, d67,
d68, d69, d70, d71, d72, d73,
d74, d75, d76, d77, d78, d79,
d80, d81, d82, d83, d84, d85,
d86, d87, d88, d89, d90, d91,
d92, d93, d94, d95, d96, d97,
d98, d99, d100, d101, d102, d103,
d104, d105, d106, d107, d108,
d109, d110, d111, d112, d113,
d114, d115, d116, d117, d118,
d119, d120, d121, d122, d123,
d124, d125, d126, d127, d128,
d129, d130, d131, d132, d133,
d134, d135, d136, d137, d138,
d139, d140, d141, d142, d143,
d144, d145, d146, d147, d148,
d149, d150, d151, d152, d153,
d154, d155, d156, d157, d158,
d159, d160, d161, d162, d163,
d164;
wire c0,c1, c2, c3, c4, c5, c6, c7,
c8, c9, c10, c11, c12, c13,
c14, c15;
wire e0,e1, e2, e3, e4, e5, e6, e7,
e8, e9, e10, e11, e12, e13,
e14, e15;
wire f0,f1, f2, f3, f4, f5, f6, f7,
f8, f9, f10, f11, f12, f13,
f14, f15;
buf #(0.716) GW0 ( c0, a[0]);
buf #(0.716) GW1 ( c1, a[0]);
buf #(0.716) GW2 ( c2, a[1]);
buf #(0.716) GW3 ( c3, a[1]);
buf #(0.716) GW4 ( c4, a[2]);
buf #(0.716) GW5 ( c5, a[2]);
buf #(0.716) GW6 ( c6, a[3]);
buf #(0.716) GW7 ( c7, a[3]);
buf #(0.716) GW8 ( c8, a[4]);
buf #(0.716) GW9 ( c9, a[4]);
buf #(0.716) GW10 ( c10, a[5]);
buf #(0.716) GW11 ( c11, a[5]);
buf #(0.716) GW12 ( c12, a[6]);
buf #(0.716) GW13 ( c13, a[6]);
buf #(0.716) GW14 ( c14, a[7]);
buf #(0.716) GW15 ( c15, a[7]);
buf #(0.716) HW0 ( e0, b[0]);
buf #(0.716) HW1 ( e1, b[0]);
buf #(0.716) HW2 ( e2, b[1]);
buf #(0.716) HW3 ( e3, b[1]);
buf #(0.716) HW4 ( e4, b[2]);
buf #(0.716) HW5 ( e5, b[2]);
buf #(0.716) HW6 ( e6, b[3]);
buf #(0.716) HW7 ( e7, b[3]);
buf #(0.716) HW8 ( e8, b[4]);
buf #(0.716) HW9 ( e9, b[4]);
buf #(0.716) HW10 ( e10, b[5]);
buf #(0.716) HW11 ( e11, b[5]);
buf #(0.716) HW12 ( e12, b[6]);
buf #(0.716) HW13 ( e13, b[6]);
buf #(0.716) HW14 ( e14, b[7]);
buf #(0.716) HW15 ( e15, b[7]);
nand #(0.716) KW0 ( o[4],f0,f1,f2,f3);
nand #(0.716) KW1 ( o[5],f4,f5,f6,f7);
nand #(0.716) KW2 ( o[6],f8,f9,f10,f11);
nand #(0.716) KW3 ( o[7],f12,f13,f14,f15);
not #(1.000) UW4 ( d60, d160 );
nor #(1.000) UW5 ( d160, d161, d162 );
not #(1.000) UW6 ( d52, d156 );
not #(1.000) UW7 ( d45, d152 );
not #(1.000) UW8 ( d38, d148 );
not #(1.000) UW9 ( d31, d144 );
not #(1.000) UW10 ( d24, d140 );
not #(1.000) UW11 ( d17, d136 );
not #(1.000) UW12 ( d10, d132 );
not #(1.000) UW13 ( d109, d107 );
not #(1.000) UW14 ( d98, d96 );
not #(1.000) UW15 ( d87, d85 );
not #(1.000) UW16 ( d73, d71 );
not #(1.000) UW17 ( d120, d118 );
nor #(1.000) UW18 ( f2, d50, d51 );
and #(1.000) UW19 ( d51, d52, d53 );
nor #(1.000) UW20 ( d50, d52, d53 );
nand #(1.000) UW21 ( d53, d54, d55 );
nor #(1.000) UW22 ( f3, d43, d44 );
and #(1.000) UW23 ( d44, d45, d46 );
nor #(1.000) UW24 ( d43, d45, d46 );
nand #(1.000) UW25 ( d46, d47, d48 );
nor #(1.000) UW26 ( f4, d36, d37 );
and #(1.000) UW27 ( d37, d38, d39 );
nor #(1.000) UW28 ( d36, d38, d39 );
nand #(1.000) UW29 ( d39, d40, d41 );
nor #(1.000) UW30 ( f5, d29, d30 );
and #(1.000) UW31 ( d30, d31, d32 );
nor #(1.000) UW32 ( d29, d31, d32 );
nand #(1.000) UW33 ( d32, d33, d34 );
nor #(1.000) UW34 ( f6, d22, d23 );
and #(1.000) UW35 ( d23, d24, d25 );
nor #(1.000) UW36 ( d22, d24, d25 );
nand #(1.000) UW37 ( d25, d26, d27 );
nor #(1.000) UW38 ( f7, d15, d16 );
and #(1.000) UW39 ( d16, d17, d18 );
nor #(1.000) UW40 ( d15, d17, d18 );
nand #(1.000) UW41 ( d18, d19, d20 );
nor #(1.000) UW42 ( f8, d8, d9 );
and #(1.000) UW43 ( d9, d10, d11 );
nor #(1.000) UW44 ( d8, d10, d11 );
nand #(1.000) UW45 ( d11, d12, d13 );
nor #(1.000) UW46 ( f9, d1, d2 );
and #(1.000) UW47 ( d2, d3, d4 );
nor #(1.000) UW48 ( d1, d3, d4 );
nand #(1.000) UW49 ( d4, d5, d6 );
nor #(1.000) UW50 ( f10, d121, d122 );
and #(1.000) UW51 ( d122, d120, d123 );
nor #(1.000) UW52 ( d121, d120, d123 );
nand #(1.000) UW53 ( d123, d124, d125 );
nor #(1.000) UW54 ( f11, d110, d111 );
and #(1.000) UW55 ( d111, d109, d112 );
nor #(1.000) UW56 ( d110, d109, d112 );
nand #(1.000) UW57 ( d112, d113, d114 );
nor #(1.000) UW58 ( f12, d99, d100 );
and #(1.000) UW59 ( d100, d98, d101 );
nor #(1.000) UW60 ( d99, d98, d101 );
nand #(1.000) UW61 ( d101, d102, d103 );
nor #(1.000) UW62 ( f13, d88, d89 );
and #(1.000) UW63 ( d89, d87, d90 );
nor #(1.000) UW64 ( d88, d87, d90 );
nand #(1.000) UW65 ( d90, d91, d92 );
nor #(1.000) UW66 ( f14, d77, d78 );
and #(1.000) UW67 ( d78, d73, d79 );
nor #(1.000) UW68 ( d77, d73, d79 );
nand #(1.000) UW69 ( d79, d80, d81 );
nor #(1.000) UW70 ( f15, d64, d65 );
and #(1.000) UW71 ( d65, d66, d67 );
nor #(1.000) UW72 ( d64, d67, d66 );
nand #(1.000) UW73 ( d66, d68, d69 );
nand #(1.000) UW74 ( f1, d57, d58 );
or #(1.000) UW75 ( d58, d59, d60 );
nand #(1.000) UW76 ( d57, d59, d60 );
nand #(1.000) UW77 ( d59, d61, d62 );
nand #(1.000) UW78 ( d3, d129, d130 );
nand #(1.000) UW79 ( d129, c8, d10 );
nand #(1.000) UW80 ( d130, e8, d131 );
nand #(1.000) UW81 ( d131, d132, d14 );
and #(1.000) UW82 ( d156, d157, d158 );
nand #(1.000) UW83 ( d158, e1, d159 );
nand #(1.000) UW84 ( d157, c1, d160 );
nand #(1.000) UW85 ( d159, d63, d60 );
and #(1.000) UW86 ( d152, d153, d154 );
nand #(1.000) UW87 ( d153, c2, d52 );
nand #(1.000) UW88 ( d154, e2, d155 );
nand #(1.000) UW89 ( d155, d156, d56 );
and #(1.000) UW90 ( d148, d149, d150 );
nand #(1.000) UW91 ( d149, c3, d45 );
nand #(1.000) UW92 ( d150, e3, d151 );
nand #(1.000) UW93 ( d151, d152, d49 );
and #(1.000) UW94 ( d144, d145, d146 );
nand #(1.000) UW95 ( d145, c4, d38 );
nand #(1.000) UW96 ( d146, e4, d147 );
nand #(1.000) UW97 ( d147, d148, d42 );
and #(1.000) UW98 ( d107, d115, d116 );
nand #(1.000) UW99 ( d115, c10, d120 );
nand #(1.000) UW100 ( d116, e10, d117 );
nand #(1.000) UW101 ( d117, d118, d119 );
and #(1.000) UW102 ( d140, d141, d142 );
nand #(1.000) UW103 ( d141, c5, d31 );
nand #(1.000) UW104 ( d142, e5, d143 );
nand #(1.000) UW105 ( d143, d144, d35 );
and #(1.000) UW106 ( d96, d104, d105 );
nand #(1.000) UW107 ( d104, c11, d109 );
nand #(1.000) UW108 ( d105, e11, d106 );
nand #(1.000) UW109 ( d106, d107, d108 );
and #(1.000) UW110 ( d136, d137, d138 );
nand #(1.000) UW111 ( d137, c6, d24 );
nand #(1.000) UW112 ( d138, e6, d139 );
nand #(1.000) UW113 ( d139, d140, d28 );
and #(1.000) UW114 ( d85, d93, d94 );
nand #(1.000) UW115 ( d93, c12, d98 );
nand #(1.000) UW116 ( d94, e12, d95 );
nand #(1.000) UW117 ( d95, d96, d97 );
and #(1.000) UW118 ( d132, d133, d134 );
nand #(1.000) UW119 ( d133, c7, d17 );
nand #(1.000) UW120 ( d134, e7, d135 );
nand #(1.000) UW121 ( d135, d136, d21 );
and #(1.000) UW122 ( d71, d82, d83 );
nand #(1.000) UW123 ( d82, c13, d87 );
nand #(1.000) UW124 ( d83, e13, d84 );
nand #(1.000) UW125 ( d84, d85, d86 );
and #(1.000) UW126 ( d118, d126, d127 );
nand #(1.000) UW127 ( d127, e9, d128 );
nand #(1.000) UW128 ( d126, c9, d3 );
or #(1.000) UW129 ( d128, d3, c9 );
nand #(1.000) UW130 ( d67, d74, d75 );
or #(1.000) UW131 ( d74, d76, e15 );
nand #(1.000) UW132 ( d75, e15, d76 );
not #(1.000) UW133 ( d76, c15 );
nand #(1.000) UW134 ( d55, e2, d56 );
nand #(1.000) UW135 ( d48, e3, d49 );
nand #(1.000) UW136 ( d41, e4, d42 );
nand #(1.000) UW137 ( d34, e5, d35 );
nand #(1.000) UW138 ( d27, e6, d28 );
nand #(1.000) UW139 ( d20, e7, d21 );
nand #(1.000) UW140 ( d13, e8, d14 );
nand #(1.000) UW141 ( d125, e10, d119 );
nand #(1.000) UW142 ( d114, e11, d108 );
nand #(1.000) UW143 ( d103, e12, d97 );
nand #(1.000) UW144 ( d92, e13, d86 );
nand #(1.000) UW145 ( d81, e14, d72 );
nand #(1.000) UW146 ( d62, e1, d63 );
nand #(1.000) UW147 ( d69, e14, d70 );
nand #(1.000) UW148 ( d70, d71, d72 );
nand #(1.000) UW149 ( d68, c14, d73 );
not #(1.000) UW150 ( d56, c2 );
not #(1.000) UW151 ( d49, c3 );
not #(1.000) UW152 ( d42, c4 );
not #(1.000) UW153 ( d35, c5 );
not #(1.000) UW154 ( d28, c6 );
not #(1.000) UW155 ( d21, c7 );
not #(1.000) UW156 ( d14, c8 );
not #(1.000) UW157 ( d119, c10 );
not #(1.000) UW158 ( d108, c11 );
not #(1.000) UW159 ( d97, c12 );
not #(1.000) UW160 ( d86, c13 );
not #(1.000) UW161 ( d72, c14 );
nand #(1.000) UW162 ( d6, e9, d7 );
not #(1.000) UW163 ( d63, c1 );
not #(1.000) UW164 ( d161, e0 );
not #(1.000) UW165 ( d162, c0 );
nand #(1.000) UW166 ( f0, d163, d164 );
nand #(1.000) UW167 ( d163, c0, d161 );
nand #(1.000) UW168 ( d164, e0, d162 );
or #(1.000) UW169 ( d61, d63, e1 );
or #(1.000) UW170 ( d54, d56, e2 );
or #(1.000) UW171 ( d47, d49, e3 );
or #(1.000) UW172 ( d40, d42, e4 );
or #(1.000) UW173 ( d33, d35, e5 );
or #(1.000) UW174 ( d26, d28, e6 );
or #(1.000) UW175 ( d19, d21, e7 );
or #(1.000) UW176 ( d12, d14, e8 );
or #(1.000) UW177 ( d5, d7, e9 );
or #(1.000) UW178 ( d124, d119, e10 );
or #(1.000) UW179 ( d113, d108, e11 );
or #(1.000) UW180 ( d102, d97, e12 );
or #(1.000) UW181 ( d91, d86, e13 );
or #(1.000) UW182 ( d80, d72, e14 );
not #(1.000) UW183 ( d7, c9 );
endmodule
|
module PIO_64_RX_ENGINE #(
parameter TCQ = 1,
parameter C_DATA_WIDTH = 64, // RX/TX interface data width
// Do not override parameters below this line
parameter KEEP_WIDTH = C_DATA_WIDTH / 8 // KEEP width
) (
input clk,
input rst_n,
// AXI-S
input [C_DATA_WIDTH-1:0] m_axis_rx_tdata,
input [KEEP_WIDTH-1:0] m_axis_rx_tkeep,
input m_axis_rx_tlast,
input m_axis_rx_tvalid,
output reg m_axis_rx_tready,
input [21:0] m_axis_rx_tuser,
/*
* Memory Read data handshake with Completion
* transmit unit. Transmit unit reponds to
* req_compl assertion and responds with compl_done
* assertion when a Completion w/ data is transmitted.
*/
output reg req_compl_o,
output reg req_compl_wd_o,
input compl_done_i,
output reg [2:0] req_tc_o, // Memory Read TC
output reg req_td_o, // Memory Read TD
output reg req_ep_o, // Memory Read EP
output reg [1:0] req_attr_o, // Memory Read Attribute
output reg [9:0] req_len_o, // Memory Read Length (1DW)
output reg [15:0] req_rid_o, // Memory Read Requestor ID
output reg [7:0] req_tag_o, // Memory Read Tag
output reg [7:0] req_be_o, // Memory Read Byte Enables
output reg [12:0] req_addr_o, // Memory Read Address
/*
* Memory interface used to save 1 DW data received
* on Memory Write 32 TLP. Data extracted from
* inbound TLP is presented to the Endpoint memory
* unit. Endpoint memory unit reacts to wr_en_o
* assertion and asserts wr_busy_i when it is
* processing written information.
*/
output reg [10:0] wr_addr_o, // Memory Write Address
output reg [7:0] wr_be_o, // Memory Write Byte Enable
output reg [31:0] wr_data_o, // Memory Write Data
output reg wr_en_o, // Memory Write Enable
input wr_busy_i // Memory Write Busy
);
localparam PIO_64_RX_MEM_RD32_FMT_TYPE = 7'b00_00000;
localparam PIO_64_RX_MEM_WR32_FMT_TYPE = 7'b10_00000;
localparam PIO_64_RX_MEM_RD64_FMT_TYPE = 7'b01_00000;
localparam PIO_64_RX_MEM_WR64_FMT_TYPE = 7'b11_00000;
localparam PIO_64_RX_IO_RD32_FMT_TYPE = 7'b00_00010;
localparam PIO_64_RX_IO_WR32_FMT_TYPE = 7'b10_00010;
localparam PIO_64_RX_RST_STATE = 8'b00000000;
localparam PIO_64_RX_MEM_RD32_DW1DW2 = 8'b00000001;
localparam PIO_64_RX_MEM_WR32_DW1DW2 = 8'b00000010;
localparam PIO_64_RX_MEM_RD64_DW1DW2 = 8'b00000100;
localparam PIO_64_RX_MEM_WR64_DW1DW2 = 8'b00001000;
localparam PIO_64_RX_MEM_WR64_DW3 = 8'b00010000;
localparam PIO_64_RX_WAIT_STATE = 8'b00100000;
localparam PIO_64_RX_IO_WR_DW1DW2 = 8'b01000000;
localparam PIO_64_RX_IO_MEM_WR_WAIT_STATE = 8'b10000000;
// Local Registers
reg [7:0] state;
reg [7:0] tlp_type;
wire io_bar_hit_n;
wire mem32_bar_hit_n;
wire mem64_bar_hit_n;
wire erom_bar_hit_n;
reg [1:0] region_select;
wire sop; // Start of packet
reg in_packet_q;
// Generate a signal that indicates if we are currently receiving a packet.
// This value is one clock cycle delayed from what is actually on the AXIS
// data bus.
always@(posedge clk)
begin
if(!rst_n)
in_packet_q <= # TCQ 1'b0;
else if (m_axis_rx_tvalid && m_axis_rx_tready && m_axis_rx_tlast)
in_packet_q <= # TCQ 1'b0;
else if (sop && m_axis_rx_tready)
in_packet_q <= # TCQ 1'b1;
end
assign sop = !in_packet_q && m_axis_rx_tvalid;
always @ ( posedge clk ) begin
if (!rst_n ) begin
m_axis_rx_tready <= #TCQ 1'b0;
req_compl_o <= #TCQ 1'b0;
req_compl_wd_o <= #TCQ 1'b1;
req_tc_o <= #TCQ 3'b0;
req_td_o <= #TCQ 1'b0;
req_ep_o <= #TCQ 1'b0;
req_attr_o <= #TCQ 2'b0;
req_len_o <= #TCQ 10'b0;
req_rid_o <= #TCQ 16'b0;
req_tag_o <= #TCQ 8'b0;
req_be_o <= #TCQ 8'b0;
req_addr_o <= #TCQ 13'b0;
wr_be_o <= #TCQ 8'b0;
wr_addr_o <= #TCQ 11'b0;
wr_data_o <= #TCQ 32'b0;
wr_en_o <= #TCQ 1'b0;
state <= #TCQ PIO_64_RX_RST_STATE;
tlp_type <= #TCQ 8'b0;
end else begin
wr_en_o <= #TCQ 1'b0;
req_compl_o <= #TCQ 1'b0;
case (state)
PIO_64_RX_RST_STATE : begin
m_axis_rx_tready <= #TCQ 1'b1;
req_compl_wd_o <= #TCQ 1'b1;
if (sop) begin
case (m_axis_rx_tdata[30:24])
PIO_64_RX_MEM_RD32_FMT_TYPE : begin
tlp_type <= #TCQ m_axis_rx_tdata[31:24];
req_len_o <= #TCQ m_axis_rx_tdata[9:0];
m_axis_rx_tready <= #TCQ 1'b0;
if (m_axis_rx_tdata[9:0] == 10'b1) begin
req_tc_o <= #TCQ m_axis_rx_tdata[22:20];
req_td_o <= #TCQ m_axis_rx_tdata[15];
req_ep_o <= #TCQ m_axis_rx_tdata[14];
req_attr_o <= #TCQ m_axis_rx_tdata[13:12];
req_len_o <= #TCQ m_axis_rx_tdata[9:0];
req_rid_o <= #TCQ m_axis_rx_tdata[63:48];
req_tag_o <= #TCQ m_axis_rx_tdata[47:40];
req_be_o <= #TCQ m_axis_rx_tdata[39:32];
state <= #TCQ PIO_64_RX_MEM_RD32_DW1DW2;
end else begin
state <= #TCQ PIO_64_RX_RST_STATE;
end
end
PIO_64_RX_MEM_WR32_FMT_TYPE : begin
tlp_type <= #TCQ m_axis_rx_tdata[31:24];
req_len_o <= #TCQ m_axis_rx_tdata[9:0];
m_axis_rx_tready <= #TCQ 1'b0;
if (m_axis_rx_tdata[9:0] == 10'b1) begin
wr_be_o <= #TCQ m_axis_rx_tdata[39:32];
state <= #TCQ PIO_64_RX_MEM_WR32_DW1DW2;
end else begin
state <= #TCQ PIO_64_RX_RST_STATE;
end
end
PIO_64_RX_MEM_RD64_FMT_TYPE : begin
tlp_type <= #TCQ m_axis_rx_tdata[31:24];
req_len_o <= #TCQ m_axis_rx_tdata[9:0];
m_axis_rx_tready <= #TCQ 1'b0;
if (m_axis_rx_tdata[9:0] == 10'b1) begin
req_tc_o <= #TCQ m_axis_rx_tdata[22:20];
req_td_o <= #TCQ m_axis_rx_tdata[15];
req_ep_o <= #TCQ m_axis_rx_tdata[14];
req_attr_o <= #TCQ m_axis_rx_tdata[13:12];
req_len_o <= #TCQ m_axis_rx_tdata[9:0];
req_rid_o <= #TCQ m_axis_rx_tdata[63:48];
req_tag_o <= #TCQ m_axis_rx_tdata[47:40];
req_be_o <= #TCQ m_axis_rx_tdata[39:32];
state <= #TCQ PIO_64_RX_MEM_RD64_DW1DW2;
end else begin
state <= #TCQ PIO_64_RX_RST_STATE;
end
end
PIO_64_RX_MEM_WR64_FMT_TYPE : begin
tlp_type <= #TCQ m_axis_rx_tdata[31:24];
req_len_o <= #TCQ m_axis_rx_tdata[9:0];
if (m_axis_rx_tdata[9:0] == 10'b1) begin
wr_be_o <= #TCQ m_axis_rx_tdata[39:32];
state <= #TCQ PIO_64_RX_MEM_WR64_DW1DW2;
end else begin
state <= #TCQ PIO_64_RX_RST_STATE;
end
end
PIO_64_RX_IO_RD32_FMT_TYPE : begin
tlp_type <= #TCQ m_axis_rx_tdata[31:24];
req_len_o <= #TCQ m_axis_rx_tdata[9:0];
m_axis_rx_tready <= #TCQ 1'b0;
if (m_axis_rx_tdata[9:0] == 10'b1) begin
req_tc_o <= #TCQ m_axis_rx_tdata[22:20];
req_td_o <= #TCQ m_axis_rx_tdata[15];
req_ep_o <= #TCQ m_axis_rx_tdata[14];
req_attr_o <= #TCQ m_axis_rx_tdata[13:12];
req_len_o <= #TCQ m_axis_rx_tdata[9:0];
req_rid_o <= #TCQ m_axis_rx_tdata[63:48];
req_tag_o <= #TCQ m_axis_rx_tdata[47:40];
req_be_o <= #TCQ m_axis_rx_tdata[39:32];
state <= #TCQ PIO_64_RX_MEM_RD32_DW1DW2;
end else begin
state <= #TCQ PIO_64_RX_RST_STATE;
end
end
PIO_64_RX_IO_WR32_FMT_TYPE : begin
tlp_type <= #TCQ m_axis_rx_tdata[31:24];
req_len_o <= #TCQ m_axis_rx_tdata[9:0];
m_axis_rx_tready <= #TCQ 1'b0;
if (m_axis_rx_tdata[9:0] == 10'b1) begin
req_tc_o <= #TCQ m_axis_rx_tdata[22:20];
req_td_o <= #TCQ m_axis_rx_tdata[15];
req_ep_o <= #TCQ m_axis_rx_tdata[14];
req_attr_o <= #TCQ m_axis_rx_tdata[13:12];
req_len_o <= #TCQ m_axis_rx_tdata[9:0];
req_rid_o <= #TCQ m_axis_rx_tdata[63:48];
req_tag_o <= #TCQ m_axis_rx_tdata[47:40];
req_be_o <= #TCQ m_axis_rx_tdata[39:32];
wr_be_o <= #TCQ m_axis_rx_tdata[39:32];
state <= #TCQ PIO_64_RX_IO_WR_DW1DW2;
end else begin
state <= #TCQ PIO_64_RX_RST_STATE;
end
end
default : begin // other TLPs
state <= #TCQ PIO_64_RX_RST_STATE;
end
endcase
end else
state <= #TCQ PIO_64_RX_RST_STATE;
end
PIO_64_RX_MEM_RD32_DW1DW2 : begin
if (m_axis_rx_tvalid) begin
m_axis_rx_tready <= #TCQ 1'b0;
req_addr_o <= #TCQ {region_select[1:0],m_axis_rx_tdata[10:2], 2'b00};
req_compl_o <= #TCQ 1'b1;
req_compl_wd_o <= #TCQ 1'b1;
state <= #TCQ PIO_64_RX_WAIT_STATE;
end else
state <= #TCQ PIO_64_RX_MEM_RD32_DW1DW2;
end
PIO_64_RX_MEM_WR32_DW1DW2 : begin
if (m_axis_rx_tvalid) begin
wr_data_o <= #TCQ m_axis_rx_tdata[63:32];
wr_en_o <= #TCQ 1'b1;
m_axis_rx_tready <= #TCQ 1'b0;
wr_addr_o <= #TCQ {region_select[1:0],m_axis_rx_tdata[10:2]};
state <= #TCQ PIO_64_RX_WAIT_STATE;
end else
state <= #TCQ PIO_64_RX_MEM_WR32_DW1DW2;
end
PIO_64_RX_MEM_RD64_DW1DW2 : begin
if (m_axis_rx_tvalid) begin
req_addr_o <= #TCQ {region_select[1:0],m_axis_rx_tdata[42:34], 2'b00};
req_compl_o <= #TCQ 1'b1;
req_compl_wd_o <= #TCQ 1'b1;
m_axis_rx_tready <= #TCQ 1'b0;
state <= #TCQ PIO_64_RX_WAIT_STATE;
end else
state <= #TCQ PIO_64_RX_MEM_RD64_DW1DW2;
end
PIO_64_RX_MEM_WR64_DW1DW2 : begin
if (m_axis_rx_tvalid) begin
m_axis_rx_tready <= #TCQ 1'b0;
wr_addr_o <= #TCQ {region_select[1:0],m_axis_rx_tdata[42:34]};
state <= #TCQ PIO_64_RX_MEM_WR64_DW3;
end else
state <= #TCQ PIO_64_RX_MEM_WR64_DW1DW2;
end
PIO_64_RX_MEM_WR64_DW3 : begin
if (m_axis_rx_tvalid) begin
wr_data_o <= #TCQ m_axis_rx_tdata[31:0];
wr_en_o <= #TCQ 1'b1;
m_axis_rx_tready <= #TCQ 1'b0;
state <= #TCQ PIO_64_RX_WAIT_STATE;
end else
state <= #TCQ PIO_64_RX_MEM_WR64_DW3;
end
PIO_64_RX_IO_WR_DW1DW2 : begin
if (m_axis_rx_tvalid) begin
wr_data_o <= #TCQ m_axis_rx_tdata[63:32];
wr_en_o <= #TCQ 1'b1;
m_axis_rx_tready <= #TCQ 1'b0;
wr_addr_o <= #TCQ {region_select[1:0],m_axis_rx_tdata[10:2]};
req_compl_o <= #TCQ 1'b1;
req_compl_wd_o <= #TCQ 1'b0;
state <= #TCQ PIO_64_RX_WAIT_STATE;
end else
state <= #TCQ PIO_64_RX_IO_WR_DW1DW2;
end
PIO_64_RX_WAIT_STATE : begin
wr_en_o <= #TCQ 1'b0;
req_compl_o <= #TCQ 1'b0;
if ((tlp_type == PIO_64_RX_MEM_WR32_FMT_TYPE) &&
(!wr_busy_i)) begin
m_axis_rx_tready <= #TCQ 1'b1;
state <= #TCQ PIO_64_RX_RST_STATE;
end else if ((tlp_type == PIO_64_RX_IO_WR32_FMT_TYPE) &&
(!wr_busy_i)) begin
m_axis_rx_tready <= #TCQ 1'b1;
state <= #TCQ PIO_64_RX_RST_STATE;
end else if ((tlp_type == PIO_64_RX_MEM_WR64_FMT_TYPE) &&
(!wr_busy_i)) begin
m_axis_rx_tready <= #TCQ 1'b1;
state <= #TCQ PIO_64_RX_RST_STATE;
end else if ((tlp_type == PIO_64_RX_MEM_RD32_FMT_TYPE) &&
(compl_done_i)) begin
m_axis_rx_tready <= #TCQ 1'b1;
state <= #TCQ PIO_64_RX_RST_STATE;
end else if ((tlp_type == PIO_64_RX_IO_RD32_FMT_TYPE) &&
(compl_done_i)) begin
m_axis_rx_tready <= #TCQ 1'b1;
state <= #TCQ PIO_64_RX_RST_STATE;
end else if ((tlp_type == PIO_64_RX_MEM_RD64_FMT_TYPE) &&
(compl_done_i)) begin
m_axis_rx_tready <= #TCQ 1'b1;
state <= #TCQ PIO_64_RX_RST_STATE;
end else
state <= #TCQ PIO_64_RX_WAIT_STATE;
end
endcase
end
end
assign mem64_bar_hit_n = ~m_axis_rx_tuser[2];
assign io_bar_hit_n = ~m_axis_rx_tuser[5];
assign mem32_bar_hit_n = ~m_axis_rx_tuser[4];
assign erom_bar_hit_n = !m_axis_rx_tuser[8];
always @*
begin
case ({io_bar_hit_n, mem32_bar_hit_n, mem64_bar_hit_n, erom_bar_hit_n})
4'b0111 : begin
region_select <= #TCQ 2'b00; // Select IO region
end
4'b1011 : begin
region_select <= #TCQ 2'b01; // Select Mem32 region
end
4'b1101 : begin
region_select <= #TCQ 2'b10; // Select Mem64 region
end
4'b1110 : begin
region_select <= #TCQ 2'b11; // Select EROM region
end
default : begin
region_select <= #TCQ 2'b00; // Error selection will select IO region
end
endcase
end
// synthesis translate_off
reg [8*20:1] state_ascii;
always @(state)
begin
case (state)
PIO_64_RX_RST_STATE : state_ascii <= #TCQ "RX_RST_STATE";
PIO_64_RX_MEM_RD32_DW1DW2 : state_ascii <= #TCQ "RX_MEM_RD32_DW1DW2";
PIO_64_RX_MEM_WR32_DW1DW2 : state_ascii <= #TCQ "RX_MEM_WR32_DW1DW2";
PIO_64_RX_MEM_RD64_DW1DW2 : state_ascii <= #TCQ "RX_MEM_RD64_DW1DW2";
PIO_64_RX_MEM_WR64_DW1DW2 : state_ascii <= #TCQ "RX_MEM_WR64_DW1DW2";
PIO_64_RX_MEM_WR64_DW3 : state_ascii <= #TCQ "RX_MEM_WR64_DW3";
PIO_64_RX_WAIT_STATE : state_ascii <= #TCQ "RX_WAIT_STATE";
PIO_64_RX_IO_WR_DW1DW2 : state_ascii <= #TCQ "PIO_64_RX_IO_WR_DW1DW2";
PIO_64_RX_IO_MEM_WR_WAIT_STATE : state_ascii <= #TCQ "PIO_64_RX_IO_MEM_WR_WAIT_STATE";
default : state_ascii <= #TCQ "PIO 64 STATE ERR";
endcase
end
// synthesis translate_on
endmodule
|
module omsp_sfr (
// OUTPUTs
nmie, // Non-maskable interrupt enable
per_dout, // Peripheral data output
wdt_irq, // Watchdog-timer interrupt
wdt_reset, // Watchdog-timer reset
wdtie, // Watchdog-timer interrupt enable
// INPUTs
mclk, // Main system clock
nmi_acc, // Non-Maskable interrupt request accepted
per_addr, // Peripheral address
per_din, // Peripheral data input
per_en, // Peripheral enable (high active)
per_wen, // Peripheral write enable (high active)
por, // Power-on reset
puc, // Main system reset
wdtifg_clr, // Clear Watchdog-timer interrupt flag
wdtifg_set, // Set Watchdog-timer interrupt flag
wdtpw_error, // Watchdog-timer password error
wdttmsel // Watchdog-timer mode select
);
// OUTPUTs
//=========
output nmie; // Non-maskable interrupt enable
output [15:0] per_dout; // Peripheral data output
output wdt_irq; // Watchdog-timer interrupt
output wdt_reset; // Watchdog-timer reset
output wdtie; // Watchdog-timer interrupt enable
// INPUTs
//=========
input mclk; // Main system clock
input nmi_acc; // Non-Maskable interrupt request accepted
input [7:0] per_addr; // Peripheral address
input [15:0] per_din; // Peripheral data input
input per_en; // Peripheral enable (high active)
input [1:0] per_wen; // Peripheral write enable (high active)
input por; // Power-on reset
input puc; // Main system reset
input wdtifg_clr; // Clear Watchdog-timer interrupt flag
input wdtifg_set; // Set Watchdog-timer interrupt flag
input wdtpw_error; // Watchdog-timer password error
input wdttmsel; // Watchdog-timer mode select
//=============================================================================
// 1) PARAMETER DECLARATION
//=============================================================================
// Register addresses
parameter IE1 = 9'h000;
parameter IFG1 = 9'h002;
// Register one-hot decoder
parameter IE1_D = (256'h1 << (IE1 /2));
parameter IFG1_D = (256'h1 << (IFG1 /2));
//============================================================================
// 2) REGISTER DECODER
//============================================================================
// Register address decode
reg [255:0] reg_dec;
always @(per_addr)
case (per_addr)
(IE1 /2): reg_dec = IE1_D;
(IFG1 /2): reg_dec = IFG1_D;
default : reg_dec = {256{1'b0}};
endcase
// Read/Write probes
wire reg_lo_write = per_wen[0] & per_en;
wire reg_hi_write = per_wen[1] & per_en;
wire reg_read = ~|per_wen & per_en;
// Read/Write vectors
wire [255:0] reg_hi_wr = reg_dec & {256{reg_hi_write}};
wire [255:0] reg_lo_wr = reg_dec & {256{reg_lo_write}};
wire [255:0] reg_rd = reg_dec & {256{reg_read}};
//============================================================================
// 3) REGISTERS
//============================================================================
// IE1 Register
//--------------
wire [7:0] ie1;
wire ie1_wr = IE1[0] ? reg_hi_wr[IE1/2] : reg_lo_wr[IE1/2];
wire [7:0] ie1_nxt = IE1[0] ? per_din[15:8] : per_din[7:0];
reg nmie;
always @ (posedge mclk or posedge puc)
if (puc) nmie <= 1'b0;
else if (nmi_acc) nmie <= 1'b0;
else if (ie1_wr) nmie <= ie1_nxt[4];
reg wdtie;
always @ (posedge mclk or posedge puc)
if (puc) wdtie <= 1'b0;
else if (ie1_wr) wdtie <= ie1_nxt[0];
assign ie1 = {3'b000, nmie, 3'b000, wdtie};
// IFG1 Register
//---------------
wire [7:0] ifg1;
wire ifg1_wr = IFG1[0] ? reg_hi_wr[IFG1/2] : reg_lo_wr[IFG1/2];
wire [7:0] ifg1_nxt = IFG1[0] ? per_din[15:8] : per_din[7:0];
reg nmiifg;
always @ (posedge mclk or posedge puc)
if (puc) nmiifg <= 1'b0;
else if (nmi_acc) nmiifg <= 1'b1;
else if (ifg1_wr) nmiifg <= ifg1_nxt[4];
reg wdtifg;
always @ (posedge mclk or posedge por)
if (por) wdtifg <= 1'b0;
else if (wdtifg_set) wdtifg <= 1'b1;
else if (wdttmsel & wdtifg_clr) wdtifg <= 1'b0;
else if (ifg1_wr) wdtifg <= ifg1_nxt[0];
assign ifg1 = {3'b000, nmiifg, 3'b000, wdtifg};
//============================================================================
// 4) DATA OUTPUT GENERATION
//============================================================================
// Data output mux
wire [15:0] ie1_rd = (ie1 & {8{reg_rd[IE1/2]}}) << (8 & {4{IE1[0]}});
wire [15:0] ifg1_rd = (ifg1 & {8{reg_rd[IFG1/2]}}) << (8 & {4{IFG1[0]}});
wire [15:0] per_dout = ie1_rd |
ifg1_rd;
//=============================================================================
// 5) WATCHDOG INTERRUPT & RESET
//=============================================================================
// Watchdog interrupt generation
//---------------------------------
wire wdt_irq = wdttmsel & wdtifg & wdtie;
// Watchdog reset generation
//-----------------------------
reg wdt_reset;
always @ (posedge mclk or posedge por)
if (por) wdt_reset <= 1'b0;
else wdt_reset <= wdtpw_error | (wdtifg_set & ~wdttmsel);
endmodule
|
module clock_divider(input clk, input rst, output reg clk_out);
//Lleva la cuenta de los ciclos de reloj transcurridos
reg [25:0] counter;
initial
begin
counter <= 26'd0;
clk_out <= 1'b1;
end
always @(posedge clk or posedge rst)
begin
if(rst)
begin
counter <= 26'd0;
clk_out <= ~clk_out;
end
else
if(counter == 26'd25000000) //va convertir un clk de 50MHz a 1Hz
begin
counter <= 26'd0;
clk_out <= ~clk_out;
end
else
begin
counter <= counter+1;
end
end
endmodule
|
module score (
input wire clk,
input wire [10:0] PIXEL_H, PIXEL_V,
input wire [7:0] PLAYER_ONE, PLAYER_TWO,
output reg [2:0] PIXEL
);
// signal declaration
wire [10:0] rom_addr;
reg [6:0] char_addr;
reg [3:0] row_addr;
reg [2:0] bit_addr;
wire [7:0] font_word;
wire font_bit;
wire p1, p2;
// instantiate font ROM
font_rom font_unit
(.clk(clk), .addr(rom_addr), .data(font_word));
// Location on the screen of the player one score.
reg [10:0] p1_v_start = 11'd10;
reg [10:0] p1_h_start = 11'd280;
// Location on the screen of the player two score.
reg [10:0] p2_v_start = 11'd10;
reg [10:0] p2_h_start = 11'd470;
// Check we are within the part of the screen that holds the player one score.
assign p1 = (
PIXEL_H >= p1_h_start && PIXEL_H <= p1_h_start + (8'd7 << 2)
&& PIXEL_V >= p1_v_start && PIXEL_V <= p1_v_start + (8'd15 << 2)
);
// Check we are within the part of the screen that holds the player two score.
assign p2 = (
PIXEL_H >= p2_h_start && PIXEL_H <= p2_h_start + (8'd7 << 2)
&& PIXEL_V >= p2_v_start && PIXEL_V <= p2_v_start + (8'd15 << 2)
);
// Mux for font ROM addresses and rgb
always @* begin
PIXEL = 3'b000;
if (p1) begin
// @todo Scores larger than 9!!!
char_addr = 7'h30 + PLAYER_ONE;
row_addr = (PIXEL_V - p1_v_start) >> 2;
bit_addr = (PIXEL_H - p1_h_start) >> 2;
if (font_bit)
PIXEL = 3'b111;
end else if (p2) begin
// @todo Scores larger than 9!!!
char_addr = 7'h30 + PLAYER_TWO;
row_addr = (PIXEL_V - p2_v_start) >> 2;
bit_addr = (PIXEL_H - p2_h_start) >> 2;
if (font_bit)
PIXEL = 3'b111;
end else begin
char_addr = 0;
row_addr = 0;
bit_addr = 0;
end
end
// Build the rom address of the current pixel.
assign rom_addr = {char_addr, row_addr};
// Get the on/off value of the bit at the current pixel from the rom.
assign font_bit = font_word[~bit_addr];
endmodule
|
module clk_wiz_1(clk_in1, clk_out1, reset, locked)
/* synthesis syn_black_box black_box_pad_pin="clk_in1,clk_out1,reset,locked" */;
input clk_in1;
output clk_out1;
input reset;
output locked;
endmodule
|
module Stack_tb();
parameter WIDTH = 8;
parameter DEPTH = 1; // frames (exponential)
localparam MAX_STACK = (1 << DEPTH+1) - 1;
reg clk = 0;
reg reset;
reg [ 1:0] op;
reg [WIDTH-1:0] data;
wire [WIDTH-1:0] tos;
wire [1:0] status;
wire [1:0] error;
stack #(
.WIDTH(WIDTH),
.DEPTH(DEPTH)
)
dut(
.clk(clk),
.reset(reset),
.op(op),
.data(data),
.tos(tos),
.status(status),
.error(error)
);
always #1 clk = ~clk;
initial begin
$dumpfile("stack_tb.vcd");
$dumpvars(0, Stack_tb);
// `status` is `empty` by default
`assert(status, `EMPTY);
// Underflow
op <= `POP;
data <= 0;
#2
`assert(error, `UNDERFLOW);
// Push
op <= `PUSH;
data <= 0;
#2
`assert(status, `NONE);
`assert(tos , 8'h00);
op <= `PUSH;
data <= 1;
#2
`assert(status, `NONE);
`assert(tos , 8'h01);
op <= `PUSH;
data <= 2;
#2
`assert(status, `FULL);
`assert(tos , 8'h02);
// Top of Stack
op <= `NONE;
#2
`assert(status, `FULL);
`assert(tos , 8'h02);
// Overflow
op <= `PUSH;
data <= 3;
#2
`assert(error, `OVERFLOW);
`assert(tos , 8'h02);
// Pop
op <= `POP;
data <= 0;
#2
`assert(status, `NONE);
`assert(tos , 8'h01);
op <= `POP;
data <= 0;
#2
`assert(status, `NONE);
`assert(tos , 8'h00);
op <= `POP;
data <= 0;
#2
`assert(status, `EMPTY);
// Replace
op <= `REPLACE;
data <= 4;
#2
`assert(error, `UNDERFLOW);
op <= `PUSH;
data <= 5;
#2
`assert(status, `NONE);
`assert(tos , 8'h05);
op <= `REPLACE;
data <= 6;
#2
`assert(status, `NONE);
`assert(tos , 8'h06);
op <= `NONE;
#2
`assert(status, `NONE);
`assert(tos , 8'h06);
// Reset
reset <= 1;
#2
reset <= 0;
`assert(status, `EMPTY);
$finish;
end
endmodule
|
module sky130_fd_sc_ls__fill_2 (
VPWR,
VGND,
VPB ,
VNB
);
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__fill base (
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
|
module sky130_fd_sc_ls__fill_2 ();
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__fill base ();
endmodule
|
module xgmii_interleave
(
input wire [63:0] input_xgmii_d,
input wire [7:0] input_xgmii_c,
output wire [72:0] output_xgmii_dc
);
assign output_xgmii_dc[7:0] = input_xgmii_d[7:0];
assign output_xgmii_dc[8] = input_xgmii_c[0];
assign output_xgmii_dc[16:9] = input_xgmii_d[15:8];
assign output_xgmii_dc[17] = input_xgmii_c[1];
assign output_xgmii_dc[25:18] = input_xgmii_d[23:16];
assign output_xgmii_dc[26] = input_xgmii_c[2];
assign output_xgmii_dc[34:27] = input_xgmii_d[31:24];
assign output_xgmii_dc[35] = input_xgmii_c[3];
assign output_xgmii_dc[43:36] = input_xgmii_d[39:32];
assign output_xgmii_dc[44] = input_xgmii_c[4];
assign output_xgmii_dc[52:45] = input_xgmii_d[47:40];
assign output_xgmii_dc[53] = input_xgmii_c[5];
assign output_xgmii_dc[61:54] = input_xgmii_d[55:48];
assign output_xgmii_dc[62] = input_xgmii_c[6];
assign output_xgmii_dc[70:63] = input_xgmii_d[63:56];
assign output_xgmii_dc[71] = input_xgmii_c[7];
endmodule
|
module testbench (
CLOCK_50, // 50 MHz
//////////////////// LCD Module 16X2 ////////////////
LCD_ON, // LCD Power ON/OFF
LCD_BLON, // LCD Back Light ON/OFF
LCD_RW, // LCD Read/Write Select, 0 = Write, 1 = Read
LCD_EN, // LCD Enable
LCD_RS, // LCD Command/Data Select, 0 = Command, 1 = Data
LCD_DATA, // LCD Data bus 8 bits
debug_sw
);
input CLOCK_50; // 50 MHz
inout [7:0] LCD_DATA; // LCD Data bus 8 bits
output LCD_ON; // LCD Power ON/OFF
output LCD_BLON; // LCD Back Light ON/OFF
output LCD_RW; // LCD Read/Write Select, 0 = Write, 1 = Read
output LCD_EN; // LCD Enable
output LCD_RS; // LCD Command/Data Select, 0 = Command, 1 = Data
input debug_sw;
wire DLY_RST;
wire [4:0] wire_lcd_ctrl;
reset_gen r0 (
.clock (CLOCK_50),
.reset (DLY_RST)
);
lcd_bridge u5 (
.clock (CLOCK_50),
.reset (DLY_RST),
.insert (debug_sw),
.new_record ({4'd1, 4'd2, 4'd3, 4'd4, 4'd5, 4'd6, 4'd7, 4'd8}),
// LCD Side
.lcd_data (LCD_DATA),
.lcd_ctrl (wire_lcd_ctrl)
);
assign {LCD_RW, LCD_EN, LCD_RS, LCD_ON, LCD_BLON} = wire_lcd_ctrl;
endmodule
|
module sky130_fd_sc_lp__o41a (
X ,
A1 ,
A2 ,
A3 ,
A4 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A1 ;
input A2 ;
input A3 ;
input A4 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire or0_out ;
wire and0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
or or0 (or0_out , A4, A3, A2, A1 );
and and0 (and0_out_X , or0_out, B1 );
sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, and0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
|
module spi_flash_clgen (clk_in, rst, go, enable, last_clk, clk_out, pos_edge, neg_edge);
parameter divider_len = 2;
parameter divider = 1;
parameter Tp = 1;
input clk_in; // input clock (system clock)
input rst; // reset
input enable; // clock enable
input go; // start transfer
input last_clk; // last clock
//input [spi_divider_len-1:0] divider; // clock divider (output clock is divided by this value)
output clk_out; // output clock
output pos_edge; // pulse marking positive edge of clk_out
output neg_edge; // pulse marking negative edge of clk_out
reg clk_out;
reg pos_edge;
reg neg_edge;
reg [divider_len-1:0] cnt; // clock counter
wire cnt_zero; // conter is equal to zero
wire cnt_one; // conter is equal to one
assign cnt_zero = cnt == {divider_len{1'b0}};
assign cnt_one = cnt == {{divider_len-1{1'b0}}, 1'b1};
// Counter counts half period
always @(posedge clk_in or posedge rst)
begin
if(rst)
cnt <= #Tp {divider_len{1'b1}};
else
begin
if(!enable || cnt_zero)
cnt <= #Tp divider;
else
cnt <= #Tp cnt - {{divider_len-1{1'b0}}, 1'b1};
end
end
// clk_out is asserted every other half period
always @(posedge clk_in or posedge rst)
begin
if(rst)
clk_out <= #Tp 1'b0;
else
clk_out <= #Tp (enable && cnt_zero && (!last_clk || clk_out)) ? ~clk_out : clk_out;
end
// Pos and neg edge signals
always @(posedge clk_in or posedge rst)
begin
if(rst)
begin
pos_edge <= #Tp 1'b0;
neg_edge <= #Tp 1'b0;
end
else
begin
pos_edge <= #Tp (enable && !clk_out && cnt_one) || (!(|divider) && clk_out) || (!(|divider) && go && !enable);
neg_edge <= #Tp (enable && clk_out && cnt_one) || (!(|divider) && !clk_out && enable);
end
end
endmodule
|
module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outreadylatency_check ( .error(1'b1) );
end
endgenerate
nios_dut_mm_interconnect_0_avalon_st_adapter_012_error_adapter_0 error_adapter_0 (
.clk (in_clk_0_clk), // clk.clk
.reset_n (~in_rst_0_reset), // reset.reset_n
.in_data (in_0_data), // in.data
.in_valid (in_0_valid), // .valid
.in_ready (in_0_ready), // .ready
.out_data (out_0_data), // out.data
.out_valid (out_0_valid), // .valid
.out_ready (out_0_ready), // .ready
.out_error (out_0_error) // .error
);
endmodule
|
module top();
// Inputs are registered
reg D;
reg SLEEP_B;
reg NOTIFIER;
reg KAPWR;
reg VGND;
reg VPWR;
// Outputs are wires
wire Q;
initial
begin
// Initial state is x for all inputs.
D = 1'bX;
KAPWR = 1'bX;
NOTIFIER = 1'bX;
SLEEP_B = 1'bX;
VGND = 1'bX;
VPWR = 1'bX;
#20 D = 1'b0;
#40 KAPWR = 1'b0;
#60 NOTIFIER = 1'b0;
#80 SLEEP_B = 1'b0;
#100 VGND = 1'b0;
#120 VPWR = 1'b0;
#140 D = 1'b1;
#160 KAPWR = 1'b1;
#180 NOTIFIER = 1'b1;
#200 SLEEP_B = 1'b1;
#220 VGND = 1'b1;
#240 VPWR = 1'b1;
#260 D = 1'b0;
#280 KAPWR = 1'b0;
#300 NOTIFIER = 1'b0;
#320 SLEEP_B = 1'b0;
#340 VGND = 1'b0;
#360 VPWR = 1'b0;
#380 VPWR = 1'b1;
#400 VGND = 1'b1;
#420 SLEEP_B = 1'b1;
#440 NOTIFIER = 1'b1;
#460 KAPWR = 1'b1;
#480 D = 1'b1;
#500 VPWR = 1'bx;
#520 VGND = 1'bx;
#540 SLEEP_B = 1'bx;
#560 NOTIFIER = 1'bx;
#580 KAPWR = 1'bx;
#600 D = 1'bx;
end
// Create a clock
reg CLK;
initial
begin
CLK = 1'b0;
end
always
begin
#5 CLK = ~CLK;
end
sky130_fd_sc_lp__udp_dff$P_pp$PKG$sN dut (.D(D), .SLEEP_B(SLEEP_B), .NOTIFIER(NOTIFIER), .KAPWR(KAPWR), .VGND(VGND), .VPWR(VPWR), .Q(Q), .CLK(CLK));
endmodule
|
module cpu_tb();
reg clk = 0;
//
// ROM
//
localparam MEM_ADDR = 4;
localparam MEM_EXTRA = 4;
reg [ MEM_ADDR :0] mem_addr;
reg [ MEM_EXTRA-1:0] mem_extra;
reg [ MEM_ADDR :0] rom_lower_bound = 0;
reg [ MEM_ADDR :0] rom_upper_bound = ~0;
wire [2**MEM_EXTRA*8-1:0] mem_data;
wire mem_error;
genrom #(
.ROMFILE("return.hex"),
.AW(MEM_ADDR),
.DW(8),
.EXTRA(MEM_EXTRA)
)
ROM (
.clk(clk),
.addr(mem_addr),
.extra(mem_extra),
.lower_bound(rom_lower_bound),
.upper_bound(rom_upper_bound),
.data(mem_data),
.error(mem_error)
);
//
// CPU
//
parameter HAS_FPU = 1;
parameter USE_64B = 1;
wire [63:0] result;
wire [ 1:0] result_type;
wire result_empty;
wire [ 3:0] trap;
cpu #(
.HAS_FPU(HAS_FPU),
.USE_64B(USE_64B),
.MEM_DEPTH(MEM_ADDR)
)
dut
(
.clk(clk),
.reset(reset),
.result(result),
.result_type(result_type),
.result_empty(result_empty),
.trap(trap),
.mem_addr(mem_addr),
.mem_extra(mem_extra),
.mem_data(mem_data),
.mem_error(mem_error)
);
always #1 clk = ~clk;
initial begin
$dumpfile("return_tb.vcd");
$dumpvars(0, cpu_tb);
if(USE_64B) begin
#12
`assert(result, 42);
`assert(result_type, `i64);
`assert(result_empty, 0);
end
else begin
#12
`assert(trap, `NO_64B);
end
$finish;
end
endmodule
|
module top (
input clk,
output LED1,
output LED2,
output LED3,
output LED4,
output LED5
);
parameter LOG2RAMDELAY = 20;
localparam BITS = 4;
localparam LOG2DELAY = LOG2RAMDELAY + 7;
reg [BITS+LOG2DELAY-1:0] counter = 0;
reg [BITS-1:0] outcnt;
wire bout;
reg enable = 0;
always @(posedge clk) begin
counter <= counter + 1;
outcnt <= counter >> LOG2DELAY;
enable <= counter[LOG2RAMDELAY];
end
memory m1 (clk, enable, bout);
assign LED1 = bout;
assign {LED2, LED3, LED4, LED5} = outcnt;
endmodule
|
module memory (
input clk,
input inc,
output bout
);
localparam DEPTH = 6;
localparam LEN = 1<<(DEPTH-1);
wire [15:0] data;
reg [DEPTH-1:0] cnt = 0;
// Morse code for "hello"
SB_RAM40_4K #(
.INIT_0(256'h0000000100000000000000010000000000000001000000010000000100000001),
.INIT_1(256'h0000000100010001000000010000000000000001000000010000000100010001),
.INIT_2(256'h0001000100000001000100010000000100010001000000000000000100000001),
.INIT_3(256'h0000000000000000000000000000000000000000000000000000000000000001),
.INIT_4(256'hxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx),
.INIT_5(256'hxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx),
.INIT_6(256'hxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx),
.INIT_7(256'hxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx),
.INIT_8(256'hxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx),
.INIT_9(256'hxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx),
.INIT_A(256'hxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx),
.INIT_B(256'hxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx),
.INIT_C(256'hxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx),
.INIT_D(256'hxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx),
.INIT_E(256'hxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx),
.INIT_F(256'hxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx),
.READ_MODE(2'b01),
.WRITE_MODE(2'b01)
)
mem
(
.RADDR({ 5'b0, cnt}),
.RCLK(clk),
.RCLKE(1'b1),
.RDATA(data),
.RE(1'b1),
.WCLK(clk),
.WCLKE(1'b0)
);
always @(posedge inc) begin
cnt <= cnt + 1;
end
assign bout = data[0];
endmodule
|
module sky130_fd_sc_hvl__dfxbp (
//# {{data|Data Signals}}
input D ,
output Q ,
output Q_N,
//# {{clocks|Clocking}}
input CLK
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
|
module sky130_fd_sc_ls__a311oi (
Y ,
A1 ,
A2 ,
A3 ,
B1 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire and0_out ;
wire nor0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
and and0 (and0_out , A3, A1, A2 );
nor nor0 (nor0_out_Y , and0_out, B1, C1 );
sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nor0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
|
module lens_flat (sclk, /// system clock @negedge
wen, /// write LSW from di
di, /// [15:0] data in
pclk, /// pixel clock (@pclk)
fstart, // frame start - single clock (will have frame latency as coefficients are written after the fstart)
newline, // start of scan line - ahead of linerun
linerun, // active pixel output - latency will be = 4 clocks
bayer,
pixdi, // pixel data in, 16 bit unsigned
pixdo // pixel data out, 16 bit unsigned
);
input sclk;
input wen;
input [15:0] di;
input pclk;
input fstart;
input newline;
input linerun;
input [1:0] bayer;
input [15:0] pixdi;
output[15:0] pixdo;
// output [18:0] lens_corr;
reg [ 1:0] wen_d;
reg [23:0] did;
reg [23:0] didd;
// reg we_AA,we_AB,we_AC,we_BA,we_BB,we_BC,we_CA,we_CB,we_CC;
reg we_AX,we_BX,we_AY,we_BY,we_C;
reg we_scales;/// write additional individual per-color scales (17 bits each)
reg we_fatzero_in,we_fatzero_out; ///
reg we_post_scale;
//F(x,y)=Ax*x^2+Bx*x+Ay*y^2+By*y+C
reg [18:0] AX; /// Ax
reg [18:0] AY; /// Ax
reg [20:0] BX; /// Bx
reg [20:0] BY; /// By
reg [18:0] C; /// C
reg [16:0] scales[0:3]; // per-color coefficients
///AF: reg [16:0] scales_r;
reg [15:0] fatzero_in; /// zero level to subtract before multiplication
reg [15:0] fatzero_out; /// zero level to add after multiplication
reg [ 3:0] post_scale; /// shift product after first multiplier - maybe needed when using decimation
wire [18:0] FY; /// F(0,y)
wire [23:0] ERR_Y; /// running error for the first column
wire [18:0] FXY; /// F(x,y)
///AF: reg [18:0] FXY_sat;
reg [ 4:0] lens_corr_out; /// lens correction out valid (first clock from column0 )
/// copied form sensorpix353.v
reg bayer_nset;
reg bayer0_latched;
reg [1:0] color;
wire [35:0] mult_first_res;
reg [17:0] mult_first_scaled; /// scaled multiplication result (to use with decimation to make parabola 'sharper')
wire [35:0] mult_second_res;
reg [15:0] pixdo; /// output pixel data, 16 bits, saturated at positive
wire [20:0] pre_pixdo_with_zero= mult_second_res[35:15] + {{5{fatzero_out[15]}},fatzero_out[15:0]};
wire sync_bayer=linerun && ~lens_corr_out[0];
wire [17:0] pix_zero = {2'b0,pixdi[15:0]}-{{2{fatzero_in [15]}},fatzero_in [15:0]};
always @ (negedge sclk) begin
wen_d[1:0] <= {wen_d[0],wen};
if (wen) did[15: 0] <= di[15:0];
if (wen_d[0]) did[23:16] <= di[ 7:0];
didd[23:0] <= did[23:0];
we_AX <= wen_d[1] && (did[23:19]==5'h00); /// 00000
we_AY <= wen_d[1] && (did[23:19]==5'h01); /// 00001
we_C <= wen_d[1] && (did[23:19]==5'h02); /// 00010
we_BX <= wen_d[1] && (did[23:21]==3'h1 ); /// 001
we_BY <= wen_d[1] && (did[23:21]==3'h2 ); /// 010
we_scales <= wen_d[1] && (did[23:19]==5'h0c); /// 01100NN
we_fatzero_in <= wen_d[1] && (did[23:16]==8'h68); /// 01101000
we_fatzero_out <= wen_d[1] && (did[23:16]==8'h69); /// 01101001
we_post_scale <= wen_d[1] && (did[23:16]==8'h6a); /// 01101010
if (we_AX) AX[18:0] <= didd[18:0];
if (we_AY) AY[18:0] <= didd[18:0];
if (we_BX) BX[20:0] <= didd[20:0];
if (we_BY) BY[20:0] <= didd[20:0];
if (we_C) C[18:0] <= didd[18:0];
if (we_scales) scales[didd[18:17]] <= didd[16:0];
if (we_fatzero_in) fatzero_in [15:0] <= didd[15:0];
if (we_fatzero_out) fatzero_out[15:0] <= didd[15:0];
if (we_post_scale) post_scale [ 3:0] <= didd[ 3:0];
end
//reg color[1:0]
always @ (posedge pclk) begin
lens_corr_out[4:0]<={lens_corr_out[3:0],linerun};
bayer_nset <= !fstart && (bayer_nset || linerun);
bayer0_latched<= bayer_nset? bayer0_latched:bayer[0];
color[1:0] <= { bayer_nset? (sync_bayer ^ color[1]):bayer[1] ,
(bayer_nset &&(~sync_bayer))?~color[0]:bayer0_latched };
/// now scale the result (normally post_scale[2:0] ==1)
case (post_scale [2:0])
3'h0:mult_first_scaled[17:0]<= (~mult_first_res[35] & |mult_first_res[34:33]) ? 18'h1ffff:mult_first_res[33:16]; /// only limit positive overflow
3'h1:mult_first_scaled[17:0]<= (~mult_first_res[35] & |mult_first_res[34:32]) ? 18'h1ffff:mult_first_res[32:15];
3'h2:mult_first_scaled[17:0]<= (~mult_first_res[35] & |mult_first_res[34:31]) ? 18'h1ffff:mult_first_res[31:14];
3'h3:mult_first_scaled[17:0]<= (~mult_first_res[35] & |mult_first_res[34:30]) ? 18'h1ffff:mult_first_res[30:13];
3'h4:mult_first_scaled[17:0]<= (~mult_first_res[35] & |mult_first_res[34:29]) ? 18'h1ffff:mult_first_res[29:12];
3'h5:mult_first_scaled[17:0]<= (~mult_first_res[35] & |mult_first_res[34:28]) ? 18'h1ffff:mult_first_res[28:11];
3'h6:mult_first_scaled[17:0]<= (~mult_first_res[35] & |mult_first_res[34:27]) ? 18'h1ffff:mult_first_res[27:10];
3'h7:mult_first_scaled[17:0]<= (~mult_first_res[35] & |mult_first_res[34:26]) ? 18'h1ffff:mult_first_res[26: 9];
endcase
if (lens_corr_out[4]) pixdo[15:0] <= pre_pixdo_with_zero[20]? 16'h0: /// negative - use 0
((|pre_pixdo_with_zero[19:16])?16'hffff: ///>0xffff - limit by 0xffff
pre_pixdo_with_zero[15:0]);
end
MULT18X18SIO #(
.AREG(1), // Enable the input registers on the A port (1=on, 0=off)
.BREG(1), // Enable the input registers on the B port (1=on, 0=off)
.B_INPUT("DIRECT"), // B cascade input "DIRECT" or "CASCADE"
.PREG(1) // Enable the input registers on the P port (1=on, 0=off)
) i_mult_first (
.BCOUT(), // 18-bit cascade output
.P(mult_first_res[35:0]), // 36-bit multiplier output
// .A(FXY[17]?18'h1ffff:FXY[17:0]), // 18-bit multiplier input
.A((FXY[18]==FXY[17])?FXY[17:0]:(FXY[18]?18'h20000:18'h1ffff)), // 18-bit multiplier input
.B({1'b0,scales[~color[1:0]]}), // 18-bit multiplier input
.BCIN(18'b0), // 18-bit cascade input
.CEA(lens_corr_out[0]), // Clock enable input for the A port
.CEB(lens_corr_out[0]), // Clock enable input for the B port
.CEP(lens_corr_out[1]), // Clock enable input for the P port
.CLK(pclk), // Clock input
.RSTA(1'b0), // Synchronous reset input for the A port
.RSTB(1'b0), // Synchronous reset input for the B port
.RSTP(1'b0) // Synchronous reset input for the P port
);
MULT18X18SIO #(
.AREG(1), // Enable the input registers on the A port (1=on, 0=off)
.BREG(0), // Enable the input registers on the B port (1=on, 0=off)
.B_INPUT("DIRECT"), // B cascade input "DIRECT" or "CASCADE"
.PREG(1) // Enable the input registers on the P port (1=on, 0=off)
) i_mult_second (
.BCOUT(), // 18-bit cascade output
.P(mult_second_res[35:0]), // 36-bit multiplier output
.A(pix_zero[17:0]), // 18-bit multiplier input
.B(mult_first_scaled[17:0]), // 18-bit multiplier input - always positive
.BCIN(18'b0), // 18-bit cascade input
.CEA(lens_corr_out[2]), // Clock enable input for the A port
.CEB(lens_corr_out[0]), // Clock enable input for the B port
.CEP(lens_corr_out[3]), // Clock enable input for the P port
.CLK(pclk), // Clock input
.RSTA(1'b0), // Synchronous reset input for the A port
.RSTB(1'b0), // Synchronous reset input for the B port
.RSTP(1'b0) // Synchronous reset input for the P port
);
lens_flat_line #(.F_WIDTH(19), /// number of bits in the output result (signed)
.F_SHIFT(22), /// shift ~2*log2(width/2), for 4K width
.B_SHIFT(12), ///(<=F_SHIFT) shift b- coeff (12 is 2^12 - good for lines <4096, 1 output count per width)
.A_WIDTH(19), /// number of bits in a-coefficient (signed). Just to match the caller - MSBs will be anyway discarded
.B_WIDTH(21)) /// number of bits in b-coefficient (signed).
i_fy( .pclk(pclk), /// pixel clock
.first(fstart), /// initialize running parameters from the inputs (first column). Should be at least 1-cycle gap between "first" and first "next"
.next(newline), /// calcualte next pixel
.F0(C[18:0]), /// value of the output in the first column (before saturation), 18 bit, unsigned
.ERR0(24'b0), /// initial value of the running error (-2.0<err<+2.0), scaled by 2^22, so 24 bits
.A0(AY[18:0]), /// Ay
.B0(BY[20:0]), /// By, signed
.F(FY[18:0]),
.ERR(ERR_Y[23:0]));
lens_flat_line #(.F_WIDTH(19), /// number of bits in the output result
.F_SHIFT(22), /// shift ~2*log2(width/2), for 4K width
.B_SHIFT(12), ///(<=F_SHIFT) shift b- coeff (12 is 2^12 - good for lines <4096, 1 output count per width)
.A_WIDTH(19), /// number of bits in a-coefficient (unsigned). Just to match the caller - MSBs will be anyway discarded
.B_WIDTH(21)) /// number of bits in b-coefficient (signed).
i_fxy( .pclk(pclk), /// pixel clock
.first(newline), /// initialize running parameters from the inputs (first column). Should be at least 1-cycle gap between "first" and first "next"
.next(linerun), /// calcualte next pixel
.F0(FY[18:0]), /// value of the output in the first column (before saturation), 18 bit, unsigned
.ERR0(ERR_Y[23:0]), /// initial value of the running error (-2.0<err<+2.0), scaled by 2^22, so 24 bits
.A0(AX[18:0]), /// Ax(Y), signed
.B0(BX[20:0]), /// Bx(Y), signed
.F(FXY[18:0]),
.ERR());
endmodule
|
module lens_flat_line(
pclk, /// pixel clock
first, /// initialize running parameters from the inputs (first column). Should be at least 1-cycle gap between "first" and first "next"
next, /// calcualte next pixel
F0, /// value of the output in the first column (before saturation), 18 bit, unsigned
ERR0, /// initial value of the running error (-2.0<err<+2.0), scaled by 2^22, so 24 bits
A0, /// a - fixed for negative values
B0,
F,
ERR); // output - 18 bits, unsigned (not saturated)
parameter F_WIDTH= 18; /// number of bits in the output result
parameter F_SHIFT=22; /// shift ~2*log2(width/2), for 4K width
parameter B_SHIFT=12; ///(<=F_SHIFT) shift b- coeff (12 is 2^12 - good for lines <4096, 1 output count per width)
parameter A_WIDTH=18; /// number of bits in a-coefficient (unsigned). Just to match the caller - MSBs will be anyway discarded
parameter B_WIDTH=21; // number of bits in b-coefficient (signed).
parameter DF_WIDTH=B_WIDTH-F_SHIFT+B_SHIFT; //21-22+12 11; /// number of bits in step of F between (df/dx), signed
input pclk;
input first;
input next;
input [F_WIDTH-1:0] F0;
input [F_SHIFT+1:0] ERR0;
input [A_WIDTH-1:0] A0;
input [B_WIDTH-1:0] B0;
output [F_WIDTH-1:0] F;
output [F_SHIFT+1:0] ERR;
reg [F_SHIFT+1:0] ERR; /// running difference between ax^2+bx+c and y, scaled by 2^22, signed, should never overflow
reg [F_SHIFT+1:0] ApB; /// a+b, scaled by 2 ^22, high bits ignored (not really needed - can use ApB0
reg [F_SHIFT+1:1] A2X; /// running value for 2*a*x, scaled by 2^22, high bits ignored
reg [(DF_WIDTH)-1:0] dF; /// or [9:0] - anyway only lower bits will be used in comparison operations
reg [F_WIDTH-1:0] F; /// Running value of the output
reg next_d, first_d; // delayed by 1 cycle
reg [F_WIDTH-1:0] F1;
reg [A_WIDTH-1:0] A;
wire [F_SHIFT+1:0] preERR={A2X[F_SHIFT+1:1],1'b0}+ApB[F_SHIFT+1:0]-{dF[1:0],{F_SHIFT{1'b0}}};
/// Increment can be 0 or +/-1, depending on the required correction
/// It relies on the facts that:
/// - the output F(x) is integer
/// - dF/dx does not chnage by more than +/-1 when x is incremented (abs (d2f/dx2)<1), so the algorithm to get
/// y=round(F(x)) is simple :
/// At each step x, try to chnage y by the same amount as was done at the previous step, adding/subtracting 1 if needed
/// and updating the new running error (difference between the current (integer) value of y and the precise value of F(x)
/// This error is calculated here with the 22 binary digits after the point.
///f=ax^2+bx+c
///
///1) f <= f+ df +1
/// df <= df+1;
/// err+= (2ax+a+b-df) -1
///2) f <= f+ df
/// err+= (2ax+a+b-df)
///3) f <= f+ df -1
/// df <= df-1;
/// err+= (2ax+a+b-df) +1
///preERR->inc:
/// 100 -> 11
/// 101 -> 11
/// 110 -> 11
/// 111 -> 00
/// 000 -> 00
/// 001 -> 01
/// 010 -> 01
/// 011 -> 01
wire [1:0] inc= {preERR[F_SHIFT+1] & (~preERR[F_SHIFT] | ~preERR[F_SHIFT-1]),
(preERR[F_SHIFT+1:F_SHIFT-1] != 3'h0) &
(preERR[F_SHIFT+1:F_SHIFT-1] != 3'h7)};
always @(posedge pclk) begin
first_d <=first;
next_d <=next;
if (first) begin
F1 [F_WIDTH-1:0] <= F0[ F_WIDTH-1:0];
dF[(DF_WIDTH)-1:0] <= B0[B_WIDTH-1: (F_SHIFT-B_SHIFT)];
ERR[F_SHIFT+1:0] <= ERR0[F_SHIFT+1:0];
ApB[F_SHIFT+1:0] <= {{F_SHIFT+2-A_WIDTH{A0[A_WIDTH-1]}},A0[A_WIDTH-1:0]}+{B0[B_WIDTH-1:0],{F_SHIFT-B_SHIFT{1'b0}}}; /// high bits from B will be discarded
A [A_WIDTH-1:0] <= A0[A_WIDTH-1:0];
end else if (next) begin
dF[(DF_WIDTH)-1:0] <= dF[(DF_WIDTH)-1:0]+{{((DF_WIDTH)-1){inc[1]}},inc[1:0]};
ERR[F_SHIFT-1:0]<= preERR[F_SHIFT-1:0];
ERR[F_SHIFT+1:F_SHIFT]<= preERR[F_SHIFT+1:F_SHIFT]-inc[1:0];
end
if (first_d) F[F_WIDTH-1:0] <= F1[ F_WIDTH-1:0];
else if (next_d) F[F_WIDTH-1:0] <= F[F_WIDTH-1:0]+{{(F_WIDTH-(DF_WIDTH)){dF[(DF_WIDTH)-1]}},dF[(DF_WIDTH)-1:0]};
if (first_d) A2X[F_SHIFT+1:1] <= {{F_SHIFT+2-A_WIDTH{A[A_WIDTH-1]}},A[A_WIDTH-1:0]};
else if (next) A2X[F_SHIFT+1:1] <= A2X[F_SHIFT+1:1] + {{F_SHIFT+2-A_WIDTH{A[A_WIDTH-1]}},A[A_WIDTH-1:0]};
end
endmodule
|
module CIRCUIT6(a, b, c, d, e, f, g, h, num, Clk, Rst, avg);
input Clk, Rst;
input [15:0] a, b, c, d, e, f, g, h, num;
output [15:0] avg;
reg [15:0] r1, r2, r3, r4, r5, r6, r7;
wire [15:0] avgwire;
wire [31:0] t1, t2, t3, t4, t5, t6, t7;
ADD #(16) add1(a, b, t1);
ADD #(16) add2(r1, c, t2);
ADD #(16) add3(r2, d, t3);
ADD #(16) add4(r3, e, t4);
ADD #(16) add5(r4, f, t5);
ADD #(16) add6(r5, g, t6);
ADD #(16) add7(r6, h, t7);
DIV #(16) div1(r7, num, avgwire);
REG #(16) reg8(avgwire, Clk, Rst, avg);
always @(r1, r2, r3, r4, r5, r6, r7) begin
r1 <= t1;
r2 <= t2;
r3 <= t3;
r4 <= t4;
r5 <= t5;
r6 <= t6;
r7 <= t7;
end
endmodule
|
module videosyncs (
input wire clk,
input wire [2:0] rin,
input wire [2:0] gin,
input wire [1:0] bin,
output reg [2:0] rout,
output reg [2:0] gout,
output reg [1:0] bout,
output reg hs,
output reg vs,
output wire [10:0] hc,
output wire [10:0] vc
);
/* http://www.abramovbenjamin.net/calc.html */
// VGA 640x480@60Hz,25MHz
parameter htotal = 800;
parameter vtotal = 524;
parameter hactive = 640;
parameter vactive = 480;
parameter hfrontporch = 16;
parameter hsyncpulse = 96;
parameter vfrontporch = 11;
parameter vsyncpulse = 2;
parameter hsyncpolarity = 0;
parameter vsyncpolarity = 0;
reg [10:0] hcont = 0;
reg [10:0] vcont = 0;
reg active_area;
assign hc = hcont;
assign vc = vcont;
always @(posedge clk) begin
if (hcont == htotal-1) begin
hcont <= 0;
if (vcont == vtotal-1) begin
vcont <= 0;
end
else begin
vcont <= vcont + 1;
end
end
else begin
hcont <= hcont + 1;
end
end
always @* begin
if (hcont>=0 && hcont<hactive && vcont>=0 && vcont<vactive)
active_area = 1'b1;
else
active_area = 1'b0;
if (hcont>=(hactive+hfrontporch) && hcont<(hactive+hfrontporch+hsyncpulse))
hs = hsyncpolarity;
else
hs = ~hsyncpolarity;
if (vcont>=(vactive+vfrontporch) && vcont<(vactive+vfrontporch+vsyncpulse))
vs = vsyncpolarity;
else
vs = ~vsyncpolarity;
end
always @* begin
if (active_area) begin
gout = gin;
rout = rin;
bout = bin;
end
else begin
gout = 3'h00;
rout = 3'h00;
bout = 2'h00;
end
end
endmodule
|
module baudgen(wren, rden, reset, din, clk, sclr, baud, dout);
//input wren, rden, reset, clk, sclr;
//input [7:0] din;
//output baud;
//output [7:0] dout;
baudgen #(.PERIOD(PERIOD)) baud1(
.wren (wr_baud),
.rden (rd_baud),
.reset (reset),
.din (din),
.clk (clk),
.stop (stop),
.baud (baud),
.dout (dout_baud)
);
//fifo ipcore
//input clk;
//input srst;
//input [8 : 0] din;
//input wr_en;
//input rd_en;
//output [8 : 0] dout;
//output full;
//output empty;
fifo_rx fifo1(
.clk (clk),
.srst (hold),
.din (frame_error),
.wr_en (wr_fifo),
.rd_en (rd_fifo),
.dout (dout_fifo),
.full (full),
.empty (empty)
);
// input flip flops
always @(posedge clk) begin
//first flip flop
in_one <= rxin;
//second flip flop
in_two <= in_one;
end
// shift register
always @(posedge clk or posedge reset) begin
if(reset) begin
shift <= 10'b1111111111;
load = 0;
end
else begin
if(ld_shift) begin
shift <= {in_two, shift[9:1]};
load = 1;
end
else
load = 0;
end
end
// loaded flag
always @(negedge clk or posedge reset) begin
if(reset) begin
loaded = 0;
end
else begin
if(load)
loaded = 1;
if(clr_load)
loaded = 0;
end
end
// frame check
always @(posedge clk or posedge reset) begin
if(reset) begin
frame_error <= 8'b00000000;
frame_ready <= 0;
end
else begin
if(rd_shift)begin
frame_error[7:0] <= shift[8:1];
if(`START | ~`STOP)
`ERROR <= 1;
else
`ERROR <= 0;
frame_ready <= 1;
end
else
frame_ready <= 0;
end
end
//address write
always @* begin
wr_baud = 0;
wr_control = 0;
case(addr)
`period: begin
if(wren)
wr_baud = 1;
end
`control: begin
if(wren)
wr_control = 1;
end
endcase
end
//address read
always @* begin
rd_baud = 0;
rd_fifo = 0;
dout = 9'b000000000;
case(addr)
`period: begin
if(rden)
rd_baud = 1;
dout = dout_baud;
end
`rx_reg: begin
if(rden)
rd_fifo = 1;
dout = dout_fifo;
end
`control: begin
if(rden)
dout = control;
end
endcase
end
// control register
always @(posedge clk or posedge reset) begin
if(reset)
control[7:0] <= 8'b00000000;
else begin
`DATARDY <= ~empty;
if(wr_control)
control[0] <= din[0];
if(frame_ready & full)
`OVERRUN <= 1;
if(~`RXEN) begin
`DATARDY <= 0;
`OVERRUN <= 0;
end
end
end
// bittimer
always @(posedge baud or posedge reset) begin
if(reset)
bittimer <= 4'b0000;
else begin
if(bittime)
bittimer <= bittimer + 1;
end
end
// bitcounter
always @(posedge clk or posedge reset) begin
if(reset)begin
bitcounter <= 4'b0000;
end
else begin
if(count)
bitcounter <= bitcounter + 1;
if(finish)
bitcounter <= 4'b0000;
end
end
// set state during startup.
always @(posedge clk or posedge reset) begin
if (reset)
pstate <= `HOLD;
else begin
pstate <= nstate;
if(`OVERRUN)
pstate <= `RX_NOT_READY;
end
end
//fsm
always @* begin
hold = 0;
ld_shift = 0; clr_load = 0;
stop = 0; count = 0; finish = 0;
bittime = 0; rd_shift = 0; wr_fifo = 0;
nstate = pstate;
case (pstate)
`HOLD: begin
hold = 1;
stop = 1;
if(`RXEN == 1)
nstate = `WAIT;
end
`WAIT: begin
stop = 1;
if(~rxin) begin
stop = 0;
nstate = `SHIFT1;
end
end
`SHIFT1: begin
if(bitcounter == 4'b1010) begin
nstate = `LD_FIFO;
finish = 1;
rd_shift = 1;
end
else begin
if(baud)
nstate = `SHIFT2;
bittime = 1;
end
end
`SHIFT2: begin
bittime = 1;
if(bittimer == 4'b1000 & ~loaded)
ld_shift = 1;
if(~baud & (bittimer == 4'b0000)) begin
count = 1;
clr_load = 1;
nstate = `SHIFT1;
end
end
`LD_FIFO: begin
wr_fifo = 1;
nstate = `WAIT;
end
`RX_NOT_READY: begin
if(~`OVERRUN)
nstate = `HOLD;
end
endcase
end
endmodule
|
module hub_mem
(
input clk_cog,
input ena_bus,
input w,
input [3:0] wb,
input [13:0] a,
input [31:0] d,
output [31:0] q
);
// 8192 x 32 ram with byte-write enables ($0000..$7FFF)
reg [7:0] ram3 [8191:0];
reg [7:0] ram2 [8191:0];
reg [7:0] ram1 [8191:0];
reg [7:0] ram0 [8191:0];
reg [7:0] ram_q3;
reg [7:0] ram_q2;
reg [7:0] ram_q1;
reg [7:0] ram_q0;
always @(posedge clk_cog)
begin
if (ena_bus && !a[13] && w && wb[3])
ram3[a[12:0]] <= d[31:24];
if (ena_bus && !a[13])
ram_q3 <= ram3[a[12:0]];
end
always @(posedge clk_cog)
begin
if (ena_bus && !a[13] && w && wb[2])
ram2[a[12:0]] <= d[23:16];
if (ena_bus && !a[13])
ram_q2 <= ram2[a[12:0]];
end
always @(posedge clk_cog)
begin
if (ena_bus && !a[13] && w && wb[1])
ram1[a[12:0]] <= d[15:8];
if (ena_bus && !a[13])
ram_q1 <= ram1[a[12:0]];
end
always @(posedge clk_cog)
begin
if (ena_bus && !a[13] && w && wb[0])
ram0[a[12:0]] <= d[7:0];
if (ena_bus && !a[13])
ram_q0 <= ram0[a[12:0]];
end
// 4096 x 32 rom containing character definitions ($8000..$BFFF)
reg [31:0] rom_low [4095:0];
reg [31:0] rom_low_q;
// 4096 x 32 rom containing sin table, log table, booter, and interpreter ($C000..$FFFF)
reg [31:0] rom_high [4095:0];
reg [31:0] rom_high_q;
// pre-load ROM
initial
begin
$readmemh ("P8X32A_ROM_FONT.spin", rom_low);
$readmemh ("ROM_$C000-$FFFF_UNSCRAMBLED.spin", rom_high);
end
always @(posedge clk_cog)
if (ena_bus && a[13:12] == 2'b10)
rom_low_q <= rom_low[a[11:0]];
always @(posedge clk_cog)
if (ena_bus && a[13:12] == 2'b11)
rom_high_q <= rom_high[a[11:0]];
// memory output mux
reg [1:0] mem;
always @(posedge clk_cog)
if (ena_bus)
mem <= a[13:12];
assign q = !mem[1] ? {ram_q3, ram_q2, ram_q1, ram_q0}
: !mem[0] ? rom_low_q // comment out this line for DE0-Nano (sacrifices character rom to fit device)
: rom_high_q;
endmodule
|
module register_file
(
input clk, rst, w_en,
input [3:0] addr_a, addr_b, addr_c, addr_d,
input [15:0] data_c,
output reg [15:0] data_a, data_b, data_d
);
//`define addr_size 4
wire w_en0, w_en1, w_en2, w_en3, w_en4, w_en5, w_en6, w_en7, w_en8, w_en9, w_enA, w_enB, w_enC, w_enD, w_enE, w_enF;
wire [15:0] data0, data1, data2, data3, data4, data5, data6, data7, data8, data9, dataA, dataB, dataC, dataD, dataE, dataF;
register register0(clk, rst ,w_en0, data_c, data0);
register register1(clk, rst ,w_en1, data_c, data1);
register register2(clk, rst ,w_en2, data_c, data2);
register register3(clk, rst ,w_en3, data_c, data3);
register register4(clk, rst ,w_en4, data_c, data4);
register register5(clk, rst ,w_en5, data_c, data5);
register register6(clk, rst ,w_en6, data_c, data6);
register register7(clk, rst ,w_en7, data_c, data7);
register register8(clk, rst ,w_en8, data_c, data8);
register register9(clk, rst ,w_en9, data_c, data9);
register register10(clk, rst ,w_enA, data_c, dataA);
register register11(clk, rst ,w_enB, data_c, dataB);
register register12(clk, rst ,w_enC, data_c, dataC);
register register13(clk, rst ,w_enD, data_c, dataD);
register register14(clk, rst ,w_enE, data_c, dataE);
register register15(clk, rst ,w_enF, data_c, dataF);
assign w_en0 = (addr_c == 4'h0) & w_en ? 1'b1 : 1'b0;
assign w_en1 = (addr_c == 4'h1) & w_en ? 1'b1 : 1'b0;
assign w_en2 = (addr_c == 4'h2) & w_en ? 1'b1 : 1'b0;
assign w_en3 = (addr_c == 4'h3) & w_en ? 1'b1 : 1'b0;
assign w_en4 = (addr_c == 4'h4) & w_en ? 1'b1 : 1'b0;
assign w_en5 = (addr_c == 4'h5) & w_en ? 1'b1 : 1'b0;
assign w_en6 = (addr_c == 4'h6) & w_en ? 1'b1 : 1'b0;
assign w_en7 = (addr_c == 4'h7) & w_en ? 1'b1 : 1'b0;
assign w_en8 = (addr_c == 4'h8) & w_en ? 1'b1 : 1'b0;
assign w_en9 = (addr_c == 4'h9) & w_en ? 1'b1 : 1'b0;
assign w_enA = (addr_c == 4'ha) & w_en ? 1'b1 : 1'b0;
assign w_enB = (addr_c == 4'hb) & w_en ? 1'b1 : 1'b0;
assign w_enC = (addr_c == 4'hc) & w_en ? 1'b1 : 1'b0;
assign w_enD = (addr_c == 4'hd) & w_en ? 1'b1 : 1'b0;
assign w_enE = (addr_c == 4'he) & w_en ? 1'b1 : 1'b0;
assign w_enF = (addr_c == 4'hf) & w_en ? 1'b1 : 1'b0;
always@(*) begin
case(addr_a)
4'h0:
data_a = data0;
4'h1:
data_a = data1;
4'h2:
data_a = data2;
4'h3:
data_a = data3;
4'h4:
data_a = data4;
4'h5:
data_a = data5;
4'h6:
data_a = data6;
4'h7:
data_a = data7;
4'h8:
data_a = data8;
4'h9:
data_a = data9;
4'ha:
data_a = dataA;
4'hb:
data_a = dataB;
4'hc:
data_a = dataC;
4'hd:
data_a = dataD;
4'he:
data_a = dataE;
4'hf:
data_a = dataF;
endcase
case(addr_b)
4'h0:
data_b = data0;
4'h1:
data_b = data1;
4'h2:
data_b = data2;
4'h3:
data_b = data3;
4'h4:
data_b = data4;
4'h5:
data_b = data5;
4'h6:
data_b = data6;
4'h7:
data_b = data7;
4'h8:
data_b = data8;
4'h9:
data_b = data9;
4'ha:
data_b = dataA;
4'hb:
data_b = dataB;
4'hc:
data_b = dataC;
4'hd:
data_b = dataD;
4'he:
data_b = dataE;
4'hf:
data_b = dataF;
endcase
case(addr_d)
4'h0:
data_d = data0;
4'h1:
data_d = data1;
4'h2:
data_d = data2;
4'h3:
data_d = data3;
4'h4:
data_d = data4;
4'h5:
data_d = data5;
4'h6:
data_d = data6;
4'h7:
data_d = data7;
4'h8:
data_d = data8;
4'h9:
data_d = data9;
4'ha:
data_d = dataA;
4'hb:
data_d = dataB;
4'hc:
data_d = dataC;
4'hd:
data_d = dataD;
4'he:
data_d = dataE;
4'hf:
data_d = dataF;
endcase
end
endmodule
|
module fpga_core #
(
parameter TARGET = "XILINX"
)
(
/*
* Clock: 156.25MHz
* Synchronous reset
*/
input wire clk,
input wire rst,
/*
* Ethernet: QSFP28
*/
input wire qsfp0_tx_clk_1,
input wire qsfp0_tx_rst_1,
output wire [63:0] qsfp0_txd_1,
output wire [7:0] qsfp0_txc_1,
input wire qsfp0_rx_clk_1,
input wire qsfp0_rx_rst_1,
input wire [63:0] qsfp0_rxd_1,
input wire [7:0] qsfp0_rxc_1,
input wire qsfp0_tx_clk_2,
input wire qsfp0_tx_rst_2,
output wire [63:0] qsfp0_txd_2,
output wire [7:0] qsfp0_txc_2,
input wire qsfp0_rx_clk_2,
input wire qsfp0_rx_rst_2,
input wire [63:0] qsfp0_rxd_2,
input wire [7:0] qsfp0_rxc_2,
input wire qsfp0_tx_clk_3,
input wire qsfp0_tx_rst_3,
output wire [63:0] qsfp0_txd_3,
output wire [7:0] qsfp0_txc_3,
input wire qsfp0_rx_clk_3,
input wire qsfp0_rx_rst_3,
input wire [63:0] qsfp0_rxd_3,
input wire [7:0] qsfp0_rxc_3,
input wire qsfp0_tx_clk_4,
input wire qsfp0_tx_rst_4,
output wire [63:0] qsfp0_txd_4,
output wire [7:0] qsfp0_txc_4,
input wire qsfp0_rx_clk_4,
input wire qsfp0_rx_rst_4,
input wire [63:0] qsfp0_rxd_4,
input wire [7:0] qsfp0_rxc_4,
input wire qsfp1_tx_clk_1,
input wire qsfp1_tx_rst_1,
output wire [63:0] qsfp1_txd_1,
output wire [7:0] qsfp1_txc_1,
input wire qsfp1_rx_clk_1,
input wire qsfp1_rx_rst_1,
input wire [63:0] qsfp1_rxd_1,
input wire [7:0] qsfp1_rxc_1,
input wire qsfp1_tx_clk_2,
input wire qsfp1_tx_rst_2,
output wire [63:0] qsfp1_txd_2,
output wire [7:0] qsfp1_txc_2,
input wire qsfp1_rx_clk_2,
input wire qsfp1_rx_rst_2,
input wire [63:0] qsfp1_rxd_2,
input wire [7:0] qsfp1_rxc_2,
input wire qsfp1_tx_clk_3,
input wire qsfp1_tx_rst_3,
output wire [63:0] qsfp1_txd_3,
output wire [7:0] qsfp1_txc_3,
input wire qsfp1_rx_clk_3,
input wire qsfp1_rx_rst_3,
input wire [63:0] qsfp1_rxd_3,
input wire [7:0] qsfp1_rxc_3,
input wire qsfp1_tx_clk_4,
input wire qsfp1_tx_rst_4,
output wire [63:0] qsfp1_txd_4,
output wire [7:0] qsfp1_txc_4,
input wire qsfp1_rx_clk_4,
input wire qsfp1_rx_rst_4,
input wire [63:0] qsfp1_rxd_4,
input wire [7:0] qsfp1_rxc_4
);
// AXI between MAC and Ethernet modules
wire [63:0] rx_axis_tdata;
wire [7:0] rx_axis_tkeep;
wire rx_axis_tvalid;
wire rx_axis_tready;
wire rx_axis_tlast;
wire rx_axis_tuser;
wire [63:0] tx_axis_tdata;
wire [7:0] tx_axis_tkeep;
wire tx_axis_tvalid;
wire tx_axis_tready;
wire tx_axis_tlast;
wire tx_axis_tuser;
// Ethernet frame between Ethernet modules and UDP stack
wire rx_eth_hdr_ready;
wire rx_eth_hdr_valid;
wire [47:0] rx_eth_dest_mac;
wire [47:0] rx_eth_src_mac;
wire [15:0] rx_eth_type;
wire [63:0] rx_eth_payload_axis_tdata;
wire [7:0] rx_eth_payload_axis_tkeep;
wire rx_eth_payload_axis_tvalid;
wire rx_eth_payload_axis_tready;
wire rx_eth_payload_axis_tlast;
wire rx_eth_payload_axis_tuser;
wire tx_eth_hdr_ready;
wire tx_eth_hdr_valid;
wire [47:0] tx_eth_dest_mac;
wire [47:0] tx_eth_src_mac;
wire [15:0] tx_eth_type;
wire [63:0] tx_eth_payload_axis_tdata;
wire [7:0] tx_eth_payload_axis_tkeep;
wire tx_eth_payload_axis_tvalid;
wire tx_eth_payload_axis_tready;
wire tx_eth_payload_axis_tlast;
wire tx_eth_payload_axis_tuser;
// IP frame connections
wire rx_ip_hdr_valid;
wire rx_ip_hdr_ready;
wire [47:0] rx_ip_eth_dest_mac;
wire [47:0] rx_ip_eth_src_mac;
wire [15:0] rx_ip_eth_type;
wire [3:0] rx_ip_version;
wire [3:0] rx_ip_ihl;
wire [5:0] rx_ip_dscp;
wire [1:0] rx_ip_ecn;
wire [15:0] rx_ip_length;
wire [15:0] rx_ip_identification;
wire [2:0] rx_ip_flags;
wire [12:0] rx_ip_fragment_offset;
wire [7:0] rx_ip_ttl;
wire [7:0] rx_ip_protocol;
wire [15:0] rx_ip_header_checksum;
wire [31:0] rx_ip_source_ip;
wire [31:0] rx_ip_dest_ip;
wire [63:0] rx_ip_payload_axis_tdata;
wire [7:0] rx_ip_payload_axis_tkeep;
wire rx_ip_payload_axis_tvalid;
wire rx_ip_payload_axis_tready;
wire rx_ip_payload_axis_tlast;
wire rx_ip_payload_axis_tuser;
wire tx_ip_hdr_valid;
wire tx_ip_hdr_ready;
wire [5:0] tx_ip_dscp;
wire [1:0] tx_ip_ecn;
wire [15:0] tx_ip_length;
wire [7:0] tx_ip_ttl;
wire [7:0] tx_ip_protocol;
wire [31:0] tx_ip_source_ip;
wire [31:0] tx_ip_dest_ip;
wire [63:0] tx_ip_payload_axis_tdata;
wire [7:0] tx_ip_payload_axis_tkeep;
wire tx_ip_payload_axis_tvalid;
wire tx_ip_payload_axis_tready;
wire tx_ip_payload_axis_tlast;
wire tx_ip_payload_axis_tuser;
// UDP frame connections
wire rx_udp_hdr_valid;
wire rx_udp_hdr_ready;
wire [47:0] rx_udp_eth_dest_mac;
wire [47:0] rx_udp_eth_src_mac;
wire [15:0] rx_udp_eth_type;
wire [3:0] rx_udp_ip_version;
wire [3:0] rx_udp_ip_ihl;
wire [5:0] rx_udp_ip_dscp;
wire [1:0] rx_udp_ip_ecn;
wire [15:0] rx_udp_ip_length;
wire [15:0] rx_udp_ip_identification;
wire [2:0] rx_udp_ip_flags;
wire [12:0] rx_udp_ip_fragment_offset;
wire [7:0] rx_udp_ip_ttl;
wire [7:0] rx_udp_ip_protocol;
wire [15:0] rx_udp_ip_header_checksum;
wire [31:0] rx_udp_ip_source_ip;
wire [31:0] rx_udp_ip_dest_ip;
wire [15:0] rx_udp_source_port;
wire [15:0] rx_udp_dest_port;
wire [15:0] rx_udp_length;
wire [15:0] rx_udp_checksum;
wire [63:0] rx_udp_payload_axis_tdata;
wire [7:0] rx_udp_payload_axis_tkeep;
wire rx_udp_payload_axis_tvalid;
wire rx_udp_payload_axis_tready;
wire rx_udp_payload_axis_tlast;
wire rx_udp_payload_axis_tuser;
wire tx_udp_hdr_valid;
wire tx_udp_hdr_ready;
wire [5:0] tx_udp_ip_dscp;
wire [1:0] tx_udp_ip_ecn;
wire [7:0] tx_udp_ip_ttl;
wire [31:0] tx_udp_ip_source_ip;
wire [31:0] tx_udp_ip_dest_ip;
wire [15:0] tx_udp_source_port;
wire [15:0] tx_udp_dest_port;
wire [15:0] tx_udp_length;
wire [15:0] tx_udp_checksum;
wire [63:0] tx_udp_payload_axis_tdata;
wire [7:0] tx_udp_payload_axis_tkeep;
wire tx_udp_payload_axis_tvalid;
wire tx_udp_payload_axis_tready;
wire tx_udp_payload_axis_tlast;
wire tx_udp_payload_axis_tuser;
wire [63:0] rx_fifo_udp_payload_axis_tdata;
wire [7:0] rx_fifo_udp_payload_axis_tkeep;
wire rx_fifo_udp_payload_axis_tvalid;
wire rx_fifo_udp_payload_axis_tready;
wire rx_fifo_udp_payload_axis_tlast;
wire rx_fifo_udp_payload_axis_tuser;
wire [63:0] tx_fifo_udp_payload_axis_tdata;
wire [7:0] tx_fifo_udp_payload_axis_tkeep;
wire tx_fifo_udp_payload_axis_tvalid;
wire tx_fifo_udp_payload_axis_tready;
wire tx_fifo_udp_payload_axis_tlast;
wire tx_fifo_udp_payload_axis_tuser;
// Configuration
wire [47:0] local_mac = 48'h02_00_00_00_00_00;
wire [31:0] local_ip = {8'd192, 8'd168, 8'd1, 8'd128};
wire [31:0] gateway_ip = {8'd192, 8'd168, 8'd1, 8'd1};
wire [31:0] subnet_mask = {8'd255, 8'd255, 8'd255, 8'd0};
// IP ports not used
assign rx_ip_hdr_ready = 1;
assign rx_ip_payload_axis_tready = 1;
assign tx_ip_hdr_valid = 0;
assign tx_ip_dscp = 0;
assign tx_ip_ecn = 0;
assign tx_ip_length = 0;
assign tx_ip_ttl = 0;
assign tx_ip_protocol = 0;
assign tx_ip_source_ip = 0;
assign tx_ip_dest_ip = 0;
assign tx_ip_payload_axis_tdata = 0;
assign tx_ip_payload_axis_tkeep = 0;
assign tx_ip_payload_axis_tvalid = 0;
assign tx_ip_payload_axis_tlast = 0;
assign tx_ip_payload_axis_tuser = 0;
// Loop back UDP
wire match_cond = rx_udp_dest_port == 1234;
wire no_match = !match_cond;
reg match_cond_reg = 0;
reg no_match_reg = 0;
always @(posedge clk) begin
if (rst) begin
match_cond_reg <= 0;
no_match_reg <= 0;
end else begin
if (rx_udp_payload_axis_tvalid) begin
if ((!match_cond_reg && !no_match_reg) ||
(rx_udp_payload_axis_tvalid && rx_udp_payload_axis_tready && rx_udp_payload_axis_tlast)) begin
match_cond_reg <= match_cond;
no_match_reg <= no_match;
end
end else begin
match_cond_reg <= 0;
no_match_reg <= 0;
end
end
end
assign tx_udp_hdr_valid = rx_udp_hdr_valid && match_cond;
assign rx_udp_hdr_ready = (tx_eth_hdr_ready && match_cond) || no_match;
assign tx_udp_ip_dscp = 0;
assign tx_udp_ip_ecn = 0;
assign tx_udp_ip_ttl = 64;
assign tx_udp_ip_source_ip = local_ip;
assign tx_udp_ip_dest_ip = rx_udp_ip_source_ip;
assign tx_udp_source_port = rx_udp_dest_port;
assign tx_udp_dest_port = rx_udp_source_port;
assign tx_udp_length = rx_udp_length;
assign tx_udp_checksum = 0;
assign tx_udp_payload_axis_tdata = tx_fifo_udp_payload_axis_tdata;
assign tx_udp_payload_axis_tkeep = tx_fifo_udp_payload_axis_tkeep;
assign tx_udp_payload_axis_tvalid = tx_fifo_udp_payload_axis_tvalid;
assign tx_fifo_udp_payload_axis_tready = tx_udp_payload_axis_tready;
assign tx_udp_payload_axis_tlast = tx_fifo_udp_payload_axis_tlast;
assign tx_udp_payload_axis_tuser = tx_fifo_udp_payload_axis_tuser;
assign rx_fifo_udp_payload_axis_tdata = rx_udp_payload_axis_tdata;
assign rx_fifo_udp_payload_axis_tkeep = rx_udp_payload_axis_tkeep;
assign rx_fifo_udp_payload_axis_tvalid = rx_udp_payload_axis_tvalid && match_cond_reg;
assign rx_udp_payload_axis_tready = (rx_fifo_udp_payload_axis_tready && match_cond_reg) || no_match_reg;
assign rx_fifo_udp_payload_axis_tlast = rx_udp_payload_axis_tlast;
assign rx_fifo_udp_payload_axis_tuser = rx_udp_payload_axis_tuser;
// Place first payload byte onto LEDs
reg valid_last = 0;
reg [7:0] led_reg = 0;
always @(posedge clk) begin
if (rst) begin
led_reg <= 0;
end else begin
valid_last <= tx_udp_payload_axis_tvalid;
if (tx_udp_payload_axis_tvalid && !valid_last) begin
led_reg <= tx_udp_payload_axis_tdata;
end
end
end
assign qsfp0_txd_2 = 64'h0707070707070707;
assign qsfp0_txc_2 = 8'hff;
assign qsfp0_txd_3 = 64'h0707070707070707;
assign qsfp0_txc_3 = 8'hff;
assign qsfp0_txd_4 = 64'h0707070707070707;
assign qsfp0_txc_4 = 8'hff;
assign qsfp1_txd_1 = 64'h0707070707070707;
assign qsfp1_txc_1 = 8'hff;
assign qsfp1_txd_2 = 64'h0707070707070707;
assign qsfp1_txc_2 = 8'hff;
assign qsfp1_txd_3 = 64'h0707070707070707;
assign qsfp1_txc_3 = 8'hff;
assign qsfp1_txd_4 = 64'h0707070707070707;
assign qsfp1_txc_4 = 8'hff;
eth_mac_10g_fifo #(
.ENABLE_PADDING(1),
.ENABLE_DIC(1),
.MIN_FRAME_LENGTH(64),
.TX_FIFO_DEPTH(4096),
.TX_FRAME_FIFO(1),
.RX_FIFO_DEPTH(4096),
.RX_FRAME_FIFO(1)
)
eth_mac_10g_fifo_inst (
.rx_clk(qsfp0_rx_clk_1),
.rx_rst(qsfp0_rx_rst_1),
.tx_clk(qsfp0_tx_clk_1),
.tx_rst(qsfp0_tx_rst_1),
.logic_clk(clk),
.logic_rst(rst),
.tx_axis_tdata(tx_axis_tdata),
.tx_axis_tkeep(tx_axis_tkeep),
.tx_axis_tvalid(tx_axis_tvalid),
.tx_axis_tready(tx_axis_tready),
.tx_axis_tlast(tx_axis_tlast),
.tx_axis_tuser(tx_axis_tuser),
.rx_axis_tdata(rx_axis_tdata),
.rx_axis_tkeep(rx_axis_tkeep),
.rx_axis_tvalid(rx_axis_tvalid),
.rx_axis_tready(rx_axis_tready),
.rx_axis_tlast(rx_axis_tlast),
.rx_axis_tuser(rx_axis_tuser),
.xgmii_rxd(qsfp0_rxd_1),
.xgmii_rxc(qsfp0_rxc_1),
.xgmii_txd(qsfp0_txd_1),
.xgmii_txc(qsfp0_txc_1),
.tx_fifo_overflow(),
.tx_fifo_bad_frame(),
.tx_fifo_good_frame(),
.rx_error_bad_frame(),
.rx_error_bad_fcs(),
.rx_fifo_overflow(),
.rx_fifo_bad_frame(),
.rx_fifo_good_frame(),
.ifg_delay(8'd12)
);
eth_axis_rx #(
.DATA_WIDTH(64)
)
eth_axis_rx_inst (
.clk(clk),
.rst(rst),
// AXI input
.s_axis_tdata(rx_axis_tdata),
.s_axis_tkeep(rx_axis_tkeep),
.s_axis_tvalid(rx_axis_tvalid),
.s_axis_tready(rx_axis_tready),
.s_axis_tlast(rx_axis_tlast),
.s_axis_tuser(rx_axis_tuser),
// Ethernet frame output
.m_eth_hdr_valid(rx_eth_hdr_valid),
.m_eth_hdr_ready(rx_eth_hdr_ready),
.m_eth_dest_mac(rx_eth_dest_mac),
.m_eth_src_mac(rx_eth_src_mac),
.m_eth_type(rx_eth_type),
.m_eth_payload_axis_tdata(rx_eth_payload_axis_tdata),
.m_eth_payload_axis_tkeep(rx_eth_payload_axis_tkeep),
.m_eth_payload_axis_tvalid(rx_eth_payload_axis_tvalid),
.m_eth_payload_axis_tready(rx_eth_payload_axis_tready),
.m_eth_payload_axis_tlast(rx_eth_payload_axis_tlast),
.m_eth_payload_axis_tuser(rx_eth_payload_axis_tuser),
// Status signals
.busy(),
.error_header_early_termination()
);
eth_axis_tx #(
.DATA_WIDTH(64)
)
eth_axis_tx_inst (
.clk(clk),
.rst(rst),
// Ethernet frame input
.s_eth_hdr_valid(tx_eth_hdr_valid),
.s_eth_hdr_ready(tx_eth_hdr_ready),
.s_eth_dest_mac(tx_eth_dest_mac),
.s_eth_src_mac(tx_eth_src_mac),
.s_eth_type(tx_eth_type),
.s_eth_payload_axis_tdata(tx_eth_payload_axis_tdata),
.s_eth_payload_axis_tkeep(tx_eth_payload_axis_tkeep),
.s_eth_payload_axis_tvalid(tx_eth_payload_axis_tvalid),
.s_eth_payload_axis_tready(tx_eth_payload_axis_tready),
.s_eth_payload_axis_tlast(tx_eth_payload_axis_tlast),
.s_eth_payload_axis_tuser(tx_eth_payload_axis_tuser),
// AXI output
.m_axis_tdata(tx_axis_tdata),
.m_axis_tkeep(tx_axis_tkeep),
.m_axis_tvalid(tx_axis_tvalid),
.m_axis_tready(tx_axis_tready),
.m_axis_tlast(tx_axis_tlast),
.m_axis_tuser(tx_axis_tuser),
// Status signals
.busy()
);
udp_complete_64
udp_complete_inst (
.clk(clk),
.rst(rst),
// Ethernet frame input
.s_eth_hdr_valid(rx_eth_hdr_valid),
.s_eth_hdr_ready(rx_eth_hdr_ready),
.s_eth_dest_mac(rx_eth_dest_mac),
.s_eth_src_mac(rx_eth_src_mac),
.s_eth_type(rx_eth_type),
.s_eth_payload_axis_tdata(rx_eth_payload_axis_tdata),
.s_eth_payload_axis_tkeep(rx_eth_payload_axis_tkeep),
.s_eth_payload_axis_tvalid(rx_eth_payload_axis_tvalid),
.s_eth_payload_axis_tready(rx_eth_payload_axis_tready),
.s_eth_payload_axis_tlast(rx_eth_payload_axis_tlast),
.s_eth_payload_axis_tuser(rx_eth_payload_axis_tuser),
// Ethernet frame output
.m_eth_hdr_valid(tx_eth_hdr_valid),
.m_eth_hdr_ready(tx_eth_hdr_ready),
.m_eth_dest_mac(tx_eth_dest_mac),
.m_eth_src_mac(tx_eth_src_mac),
.m_eth_type(tx_eth_type),
.m_eth_payload_axis_tdata(tx_eth_payload_axis_tdata),
.m_eth_payload_axis_tkeep(tx_eth_payload_axis_tkeep),
.m_eth_payload_axis_tvalid(tx_eth_payload_axis_tvalid),
.m_eth_payload_axis_tready(tx_eth_payload_axis_tready),
.m_eth_payload_axis_tlast(tx_eth_payload_axis_tlast),
.m_eth_payload_axis_tuser(tx_eth_payload_axis_tuser),
// IP frame input
.s_ip_hdr_valid(tx_ip_hdr_valid),
.s_ip_hdr_ready(tx_ip_hdr_ready),
.s_ip_dscp(tx_ip_dscp),
.s_ip_ecn(tx_ip_ecn),
.s_ip_length(tx_ip_length),
.s_ip_ttl(tx_ip_ttl),
.s_ip_protocol(tx_ip_protocol),
.s_ip_source_ip(tx_ip_source_ip),
.s_ip_dest_ip(tx_ip_dest_ip),
.s_ip_payload_axis_tdata(tx_ip_payload_axis_tdata),
.s_ip_payload_axis_tkeep(tx_ip_payload_axis_tkeep),
.s_ip_payload_axis_tvalid(tx_ip_payload_axis_tvalid),
.s_ip_payload_axis_tready(tx_ip_payload_axis_tready),
.s_ip_payload_axis_tlast(tx_ip_payload_axis_tlast),
.s_ip_payload_axis_tuser(tx_ip_payload_axis_tuser),
// IP frame output
.m_ip_hdr_valid(rx_ip_hdr_valid),
.m_ip_hdr_ready(rx_ip_hdr_ready),
.m_ip_eth_dest_mac(rx_ip_eth_dest_mac),
.m_ip_eth_src_mac(rx_ip_eth_src_mac),
.m_ip_eth_type(rx_ip_eth_type),
.m_ip_version(rx_ip_version),
.m_ip_ihl(rx_ip_ihl),
.m_ip_dscp(rx_ip_dscp),
.m_ip_ecn(rx_ip_ecn),
.m_ip_length(rx_ip_length),
.m_ip_identification(rx_ip_identification),
.m_ip_flags(rx_ip_flags),
.m_ip_fragment_offset(rx_ip_fragment_offset),
.m_ip_ttl(rx_ip_ttl),
.m_ip_protocol(rx_ip_protocol),
.m_ip_header_checksum(rx_ip_header_checksum),
.m_ip_source_ip(rx_ip_source_ip),
.m_ip_dest_ip(rx_ip_dest_ip),
.m_ip_payload_axis_tdata(rx_ip_payload_axis_tdata),
.m_ip_payload_axis_tkeep(rx_ip_payload_axis_tkeep),
.m_ip_payload_axis_tvalid(rx_ip_payload_axis_tvalid),
.m_ip_payload_axis_tready(rx_ip_payload_axis_tready),
.m_ip_payload_axis_tlast(rx_ip_payload_axis_tlast),
.m_ip_payload_axis_tuser(rx_ip_payload_axis_tuser),
// UDP frame input
.s_udp_hdr_valid(tx_udp_hdr_valid),
.s_udp_hdr_ready(tx_udp_hdr_ready),
.s_udp_ip_dscp(tx_udp_ip_dscp),
.s_udp_ip_ecn(tx_udp_ip_ecn),
.s_udp_ip_ttl(tx_udp_ip_ttl),
.s_udp_ip_source_ip(tx_udp_ip_source_ip),
.s_udp_ip_dest_ip(tx_udp_ip_dest_ip),
.s_udp_source_port(tx_udp_source_port),
.s_udp_dest_port(tx_udp_dest_port),
.s_udp_length(tx_udp_length),
.s_udp_checksum(tx_udp_checksum),
.s_udp_payload_axis_tdata(tx_udp_payload_axis_tdata),
.s_udp_payload_axis_tkeep(tx_udp_payload_axis_tkeep),
.s_udp_payload_axis_tvalid(tx_udp_payload_axis_tvalid),
.s_udp_payload_axis_tready(tx_udp_payload_axis_tready),
.s_udp_payload_axis_tlast(tx_udp_payload_axis_tlast),
.s_udp_payload_axis_tuser(tx_udp_payload_axis_tuser),
// UDP frame output
.m_udp_hdr_valid(rx_udp_hdr_valid),
.m_udp_hdr_ready(rx_udp_hdr_ready),
.m_udp_eth_dest_mac(rx_udp_eth_dest_mac),
.m_udp_eth_src_mac(rx_udp_eth_src_mac),
.m_udp_eth_type(rx_udp_eth_type),
.m_udp_ip_version(rx_udp_ip_version),
.m_udp_ip_ihl(rx_udp_ip_ihl),
.m_udp_ip_dscp(rx_udp_ip_dscp),
.m_udp_ip_ecn(rx_udp_ip_ecn),
.m_udp_ip_length(rx_udp_ip_length),
.m_udp_ip_identification(rx_udp_ip_identification),
.m_udp_ip_flags(rx_udp_ip_flags),
.m_udp_ip_fragment_offset(rx_udp_ip_fragment_offset),
.m_udp_ip_ttl(rx_udp_ip_ttl),
.m_udp_ip_protocol(rx_udp_ip_protocol),
.m_udp_ip_header_checksum(rx_udp_ip_header_checksum),
.m_udp_ip_source_ip(rx_udp_ip_source_ip),
.m_udp_ip_dest_ip(rx_udp_ip_dest_ip),
.m_udp_source_port(rx_udp_source_port),
.m_udp_dest_port(rx_udp_dest_port),
.m_udp_length(rx_udp_length),
.m_udp_checksum(rx_udp_checksum),
.m_udp_payload_axis_tdata(rx_udp_payload_axis_tdata),
.m_udp_payload_axis_tkeep(rx_udp_payload_axis_tkeep),
.m_udp_payload_axis_tvalid(rx_udp_payload_axis_tvalid),
.m_udp_payload_axis_tready(rx_udp_payload_axis_tready),
.m_udp_payload_axis_tlast(rx_udp_payload_axis_tlast),
.m_udp_payload_axis_tuser(rx_udp_payload_axis_tuser),
// Status signals
.ip_rx_busy(),
.ip_tx_busy(),
.udp_rx_busy(),
.udp_tx_busy(),
.ip_rx_error_header_early_termination(),
.ip_rx_error_payload_early_termination(),
.ip_rx_error_invalid_header(),
.ip_rx_error_invalid_checksum(),
.ip_tx_error_payload_early_termination(),
.ip_tx_error_arp_failed(),
.udp_rx_error_header_early_termination(),
.udp_rx_error_payload_early_termination(),
.udp_tx_error_payload_early_termination(),
// Configuration
.local_mac(local_mac),
.local_ip(local_ip),
.gateway_ip(gateway_ip),
.subnet_mask(subnet_mask),
.clear_arp_cache(1'b0)
);
axis_fifo #(
.DEPTH(8192),
.DATA_WIDTH(64),
.KEEP_ENABLE(1),
.KEEP_WIDTH(8),
.ID_ENABLE(0),
.DEST_ENABLE(0),
.USER_ENABLE(1),
.USER_WIDTH(1),
.FRAME_FIFO(0)
)
udp_payload_fifo (
.clk(clk),
.rst(rst),
// AXI input
.s_axis_tdata(rx_fifo_udp_payload_axis_tdata),
.s_axis_tkeep(rx_fifo_udp_payload_axis_tkeep),
.s_axis_tvalid(rx_fifo_udp_payload_axis_tvalid),
.s_axis_tready(rx_fifo_udp_payload_axis_tready),
.s_axis_tlast(rx_fifo_udp_payload_axis_tlast),
.s_axis_tid(0),
.s_axis_tdest(0),
.s_axis_tuser(rx_fifo_udp_payload_axis_tuser),
// AXI output
.m_axis_tdata(tx_fifo_udp_payload_axis_tdata),
.m_axis_tkeep(tx_fifo_udp_payload_axis_tkeep),
.m_axis_tvalid(tx_fifo_udp_payload_axis_tvalid),
.m_axis_tready(tx_fifo_udp_payload_axis_tready),
.m_axis_tlast(tx_fifo_udp_payload_axis_tlast),
.m_axis_tid(),
.m_axis_tdest(),
.m_axis_tuser(tx_fifo_udp_payload_axis_tuser),
// Status
.status_overflow(),
.status_bad_frame(),
.status_good_frame()
);
endmodule
|
module sdp_ram_10x14_11x7(
clka,
dina,
addra,
wea,
clkb,
addrb,
doutb);
input clka;
input [13 : 0] dina;
input [9 : 0] addra;
input [0 : 0] wea;
input clkb;
input [10 : 0] addrb;
output [6 : 0] doutb;
// synthesis translate_off
BLK_MEM_GEN_V2_8 #(
.C_ADDRA_WIDTH(10),
.C_ADDRB_WIDTH(11),
.C_ALGORITHM(1),
.C_BYTE_SIZE(9),
.C_COMMON_CLK(0),
.C_DEFAULT_DATA("0"),
.C_DISABLE_WARN_BHV_COLL(0),
.C_DISABLE_WARN_BHV_RANGE(0),
.C_FAMILY("virtex5"),
.C_HAS_ENA(0),
.C_HAS_ENB(0),
.C_HAS_MEM_OUTPUT_REGS_A(0),
.C_HAS_MEM_OUTPUT_REGS_B(0),
.C_HAS_MUX_OUTPUT_REGS_A(0),
.C_HAS_MUX_OUTPUT_REGS_B(0),
.C_HAS_REGCEA(0),
.C_HAS_REGCEB(0),
.C_HAS_SSRA(0),
.C_HAS_SSRB(0),
.C_INIT_FILE_NAME("no_coe_file_loaded"),
.C_LOAD_INIT_FILE(0),
.C_MEM_TYPE(1),
.C_MUX_PIPELINE_STAGES(0),
.C_PRIM_TYPE(1),
.C_READ_DEPTH_A(1024),
.C_READ_DEPTH_B(2048),
.C_READ_WIDTH_A(14),
.C_READ_WIDTH_B(7),
.C_SIM_COLLISION_CHECK("ALL"),
.C_SINITA_VAL("0"),
.C_SINITB_VAL("0"),
.C_USE_BYTE_WEA(0),
.C_USE_BYTE_WEB(0),
.C_USE_DEFAULT_DATA(0),
.C_USE_ECC(0),
.C_USE_RAMB16BWER_RST_BHV(0),
.C_WEA_WIDTH(1),
.C_WEB_WIDTH(1),
.C_WRITE_DEPTH_A(1024),
.C_WRITE_DEPTH_B(2048),
.C_WRITE_MODE_A("READ_FIRST"),
.C_WRITE_MODE_B("READ_FIRST"),
.C_WRITE_WIDTH_A(14),
.C_WRITE_WIDTH_B(7),
.C_XDEVICEFAMILY("virtex5"))
inst (
.CLKA(clka),
.DINA(dina),
.ADDRA(addra),
.WEA(wea),
.CLKB(clkb),
.ADDRB(addrb),
.DOUTB(doutb),
.ENA(),
.REGCEA(),
.SSRA(),
.DOUTA(),
.DINB(),
.ENB(),
.REGCEB(),
.WEB(),
.SSRB(),
.DBITERR(),
.SBITERR());
// synthesis translate_on
// XST black box declaration
// box_type "black_box"
// synthesis attribute box_type of sdp_ram_10x14_11x7 is "black_box"
endmodule
|
module nios_system_mm_interconnect_0 (
input wire clk_0_clk_clk, // clk_0_clk.clk
input wire nios2_qsys_0_reset_reset_bridge_in_reset_reset, // nios2_qsys_0_reset_reset_bridge_in_reset.reset
input wire [18:0] nios2_qsys_0_data_master_address, // nios2_qsys_0_data_master.address
output wire nios2_qsys_0_data_master_waitrequest, // .waitrequest
input wire [3:0] nios2_qsys_0_data_master_byteenable, // .byteenable
input wire nios2_qsys_0_data_master_read, // .read
output wire [31:0] nios2_qsys_0_data_master_readdata, // .readdata
input wire nios2_qsys_0_data_master_write, // .write
input wire [31:0] nios2_qsys_0_data_master_writedata, // .writedata
input wire nios2_qsys_0_data_master_debugaccess, // .debugaccess
input wire [18:0] nios2_qsys_0_instruction_master_address, // nios2_qsys_0_instruction_master.address
output wire nios2_qsys_0_instruction_master_waitrequest, // .waitrequest
input wire nios2_qsys_0_instruction_master_read, // .read
output wire [31:0] nios2_qsys_0_instruction_master_readdata, // .readdata
output wire [1:0] alu_a_s1_address, // alu_a_s1.address
output wire alu_a_s1_write, // .write
input wire [31:0] alu_a_s1_readdata, // .readdata
output wire [31:0] alu_a_s1_writedata, // .writedata
output wire alu_a_s1_chipselect, // .chipselect
output wire [1:0] alu_b_s1_address, // alu_b_s1.address
output wire alu_b_s1_write, // .write
input wire [31:0] alu_b_s1_readdata, // .readdata
output wire [31:0] alu_b_s1_writedata, // .writedata
output wire alu_b_s1_chipselect, // .chipselect
output wire [1:0] alu_carry_out_s1_address, // alu_carry_out_s1.address
input wire [31:0] alu_carry_out_s1_readdata, // .readdata
output wire [1:0] alu_control_s1_address, // alu_control_s1.address
output wire alu_control_s1_write, // .write
input wire [31:0] alu_control_s1_readdata, // .readdata
output wire [31:0] alu_control_s1_writedata, // .writedata
output wire alu_control_s1_chipselect, // .chipselect
output wire [1:0] alu_negative_s1_address, // alu_negative_s1.address
input wire [31:0] alu_negative_s1_readdata, // .readdata
output wire [1:0] alu_out_s1_address, // alu_out_s1.address
input wire [31:0] alu_out_s1_readdata, // .readdata
output wire [1:0] alu_overflow_s1_address, // alu_overflow_s1.address
input wire [31:0] alu_overflow_s1_readdata, // .readdata
output wire [1:0] alu_zero_s1_address, // alu_zero_s1.address
input wire [31:0] alu_zero_s1_readdata, // .readdata
output wire [1:0] hex_0_s1_address, // hex_0_s1.address
output wire hex_0_s1_write, // .write
input wire [31:0] hex_0_s1_readdata, // .readdata
output wire [31:0] hex_0_s1_writedata, // .writedata
output wire hex_0_s1_chipselect, // .chipselect
output wire [1:0] hex_1_s1_address, // hex_1_s1.address
output wire hex_1_s1_write, // .write
input wire [31:0] hex_1_s1_readdata, // .readdata
output wire [31:0] hex_1_s1_writedata, // .writedata
output wire hex_1_s1_chipselect, // .chipselect
output wire [1:0] hex_2_s1_address, // hex_2_s1.address
output wire hex_2_s1_write, // .write
input wire [31:0] hex_2_s1_readdata, // .readdata
output wire [31:0] hex_2_s1_writedata, // .writedata
output wire hex_2_s1_chipselect, // .chipselect
output wire [1:0] hex_3_s1_address, // hex_3_s1.address
output wire hex_3_s1_write, // .write
input wire [31:0] hex_3_s1_readdata, // .readdata
output wire [31:0] hex_3_s1_writedata, // .writedata
output wire hex_3_s1_chipselect, // .chipselect
output wire [1:0] hex_4_s1_address, // hex_4_s1.address
output wire hex_4_s1_write, // .write
input wire [31:0] hex_4_s1_readdata, // .readdata
output wire [31:0] hex_4_s1_writedata, // .writedata
output wire hex_4_s1_chipselect, // .chipselect
output wire [1:0] hex_5_s1_address, // hex_5_s1.address
output wire hex_5_s1_write, // .write
input wire [31:0] hex_5_s1_readdata, // .readdata
output wire [31:0] hex_5_s1_writedata, // .writedata
output wire hex_5_s1_chipselect, // .chipselect
output wire [0:0] jtag_uart_0_avalon_jtag_slave_address, // jtag_uart_0_avalon_jtag_slave.address
output wire jtag_uart_0_avalon_jtag_slave_write, // .write
output wire jtag_uart_0_avalon_jtag_slave_read, // .read
input wire [31:0] jtag_uart_0_avalon_jtag_slave_readdata, // .readdata
output wire [31:0] jtag_uart_0_avalon_jtag_slave_writedata, // .writedata
input wire jtag_uart_0_avalon_jtag_slave_waitrequest, // .waitrequest
output wire jtag_uart_0_avalon_jtag_slave_chipselect, // .chipselect
output wire [1:0] keys_s1_address, // keys_s1.address
input wire [31:0] keys_s1_readdata, // .readdata
output wire [1:0] LEDs_s1_address, // LEDs_s1.address
output wire LEDs_s1_write, // .write
input wire [31:0] LEDs_s1_readdata, // .readdata
output wire [31:0] LEDs_s1_writedata, // .writedata
output wire LEDs_s1_chipselect, // .chipselect
output wire [8:0] nios2_qsys_0_debug_mem_slave_address, // nios2_qsys_0_debug_mem_slave.address
output wire nios2_qsys_0_debug_mem_slave_write, // .write
output wire nios2_qsys_0_debug_mem_slave_read, // .read
input wire [31:0] nios2_qsys_0_debug_mem_slave_readdata, // .readdata
output wire [31:0] nios2_qsys_0_debug_mem_slave_writedata, // .writedata
output wire [3:0] nios2_qsys_0_debug_mem_slave_byteenable, // .byteenable
input wire nios2_qsys_0_debug_mem_slave_waitrequest, // .waitrequest
output wire nios2_qsys_0_debug_mem_slave_debugaccess, // .debugaccess
output wire [14:0] onchip_memory2_0_s1_address, // onchip_memory2_0_s1.address
output wire onchip_memory2_0_s1_write, // .write
input wire [31:0] onchip_memory2_0_s1_readdata, // .readdata
output wire [31:0] onchip_memory2_0_s1_writedata, // .writedata
output wire [3:0] onchip_memory2_0_s1_byteenable, // .byteenable
output wire onchip_memory2_0_s1_chipselect, // .chipselect
output wire onchip_memory2_0_s1_clken, // .clken
output wire [1:0] regfile_data_s1_address, // regfile_data_s1.address
output wire regfile_data_s1_write, // .write
input wire [31:0] regfile_data_s1_readdata, // .readdata
output wire [31:0] regfile_data_s1_writedata, // .writedata
output wire regfile_data_s1_chipselect, // .chipselect
output wire [1:0] regfile_r1sel_s1_address, // regfile_r1sel_s1.address
output wire regfile_r1sel_s1_write, // .write
input wire [31:0] regfile_r1sel_s1_readdata, // .readdata
output wire [31:0] regfile_r1sel_s1_writedata, // .writedata
output wire regfile_r1sel_s1_chipselect, // .chipselect
output wire [1:0] regfile_r2sel_s1_address, // regfile_r2sel_s1.address
output wire regfile_r2sel_s1_write, // .write
input wire [31:0] regfile_r2sel_s1_readdata, // .readdata
output wire [31:0] regfile_r2sel_s1_writedata, // .writedata
output wire regfile_r2sel_s1_chipselect, // .chipselect
output wire [1:0] regfile_reg1_s1_address, // regfile_reg1_s1.address
input wire [31:0] regfile_reg1_s1_readdata, // .readdata
output wire [1:0] regfile_reg2_s1_address, // regfile_reg2_s1.address
input wire [31:0] regfile_reg2_s1_readdata, // .readdata
output wire [1:0] regfile_we_s1_address, // regfile_we_s1.address
output wire regfile_we_s1_write, // .write
input wire [31:0] regfile_we_s1_readdata, // .readdata
output wire [31:0] regfile_we_s1_writedata, // .writedata
output wire regfile_we_s1_chipselect, // .chipselect
output wire [1:0] regfile_wsel_s1_address, // regfile_wsel_s1.address
output wire regfile_wsel_s1_write, // .write
input wire [31:0] regfile_wsel_s1_readdata, // .readdata
output wire [31:0] regfile_wsel_s1_writedata, // .writedata
output wire regfile_wsel_s1_chipselect, // .chipselect
output wire [1:0] sram_addr_s1_address, // sram_addr_s1.address
output wire sram_addr_s1_write, // .write
input wire [31:0] sram_addr_s1_readdata, // .readdata
output wire [31:0] sram_addr_s1_writedata, // .writedata
output wire sram_addr_s1_chipselect, // .chipselect
output wire [1:0] sram_cs_s1_address, // sram_cs_s1.address
output wire sram_cs_s1_write, // .write
input wire [31:0] sram_cs_s1_readdata, // .readdata
output wire [31:0] sram_cs_s1_writedata, // .writedata
output wire sram_cs_s1_chipselect, // .chipselect
output wire [1:0] sram_data_s1_address, // sram_data_s1.address
output wire sram_data_s1_write, // .write
input wire [31:0] sram_data_s1_readdata, // .readdata
output wire [31:0] sram_data_s1_writedata, // .writedata
output wire sram_data_s1_chipselect, // .chipselect
output wire [1:0] sram_oe_s1_address, // sram_oe_s1.address
output wire sram_oe_s1_write, // .write
input wire [31:0] sram_oe_s1_readdata, // .readdata
output wire [31:0] sram_oe_s1_writedata, // .writedata
output wire sram_oe_s1_chipselect, // .chipselect
output wire [1:0] sram_read_write_s1_address, // sram_read_write_s1.address
output wire sram_read_write_s1_write, // .write
input wire [31:0] sram_read_write_s1_readdata, // .readdata
output wire [31:0] sram_read_write_s1_writedata, // .writedata
output wire sram_read_write_s1_chipselect, // .chipselect
output wire [1:0] switches_s1_address, // switches_s1.address
input wire [31:0] switches_s1_readdata // .readdata
);
wire nios2_qsys_0_data_master_translator_avalon_universal_master_0_waitrequest; // nios2_qsys_0_data_master_agent:av_waitrequest -> nios2_qsys_0_data_master_translator:uav_waitrequest
wire [31:0] nios2_qsys_0_data_master_translator_avalon_universal_master_0_readdata; // nios2_qsys_0_data_master_agent:av_readdata -> nios2_qsys_0_data_master_translator:uav_readdata
wire nios2_qsys_0_data_master_translator_avalon_universal_master_0_debugaccess; // nios2_qsys_0_data_master_translator:uav_debugaccess -> nios2_qsys_0_data_master_agent:av_debugaccess
wire [18:0] nios2_qsys_0_data_master_translator_avalon_universal_master_0_address; // nios2_qsys_0_data_master_translator:uav_address -> nios2_qsys_0_data_master_agent:av_address
wire nios2_qsys_0_data_master_translator_avalon_universal_master_0_read; // nios2_qsys_0_data_master_translator:uav_read -> nios2_qsys_0_data_master_agent:av_read
wire [3:0] nios2_qsys_0_data_master_translator_avalon_universal_master_0_byteenable; // nios2_qsys_0_data_master_translator:uav_byteenable -> nios2_qsys_0_data_master_agent:av_byteenable
wire nios2_qsys_0_data_master_translator_avalon_universal_master_0_readdatavalid; // nios2_qsys_0_data_master_agent:av_readdatavalid -> nios2_qsys_0_data_master_translator:uav_readdatavalid
wire nios2_qsys_0_data_master_translator_avalon_universal_master_0_lock; // nios2_qsys_0_data_master_translator:uav_lock -> nios2_qsys_0_data_master_agent:av_lock
wire nios2_qsys_0_data_master_translator_avalon_universal_master_0_write; // nios2_qsys_0_data_master_translator:uav_write -> nios2_qsys_0_data_master_agent:av_write
wire [31:0] nios2_qsys_0_data_master_translator_avalon_universal_master_0_writedata; // nios2_qsys_0_data_master_translator:uav_writedata -> nios2_qsys_0_data_master_agent:av_writedata
wire [2:0] nios2_qsys_0_data_master_translator_avalon_universal_master_0_burstcount; // nios2_qsys_0_data_master_translator:uav_burstcount -> nios2_qsys_0_data_master_agent:av_burstcount
wire rsp_mux_src_valid; // rsp_mux:src_valid -> nios2_qsys_0_data_master_agent:rp_valid
wire [98:0] rsp_mux_src_data; // rsp_mux:src_data -> nios2_qsys_0_data_master_agent:rp_data
wire rsp_mux_src_ready; // nios2_qsys_0_data_master_agent:rp_ready -> rsp_mux:src_ready
wire [31:0] rsp_mux_src_channel; // rsp_mux:src_channel -> nios2_qsys_0_data_master_agent:rp_channel
wire rsp_mux_src_startofpacket; // rsp_mux:src_startofpacket -> nios2_qsys_0_data_master_agent:rp_startofpacket
wire rsp_mux_src_endofpacket; // rsp_mux:src_endofpacket -> nios2_qsys_0_data_master_agent:rp_endofpacket
wire nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_waitrequest; // nios2_qsys_0_instruction_master_agent:av_waitrequest -> nios2_qsys_0_instruction_master_translator:uav_waitrequest
wire [31:0] nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_readdata; // nios2_qsys_0_instruction_master_agent:av_readdata -> nios2_qsys_0_instruction_master_translator:uav_readdata
wire nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_debugaccess; // nios2_qsys_0_instruction_master_translator:uav_debugaccess -> nios2_qsys_0_instruction_master_agent:av_debugaccess
wire [18:0] nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_address; // nios2_qsys_0_instruction_master_translator:uav_address -> nios2_qsys_0_instruction_master_agent:av_address
wire nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_read; // nios2_qsys_0_instruction_master_translator:uav_read -> nios2_qsys_0_instruction_master_agent:av_read
wire [3:0] nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_byteenable; // nios2_qsys_0_instruction_master_translator:uav_byteenable -> nios2_qsys_0_instruction_master_agent:av_byteenable
wire nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_readdatavalid; // nios2_qsys_0_instruction_master_agent:av_readdatavalid -> nios2_qsys_0_instruction_master_translator:uav_readdatavalid
wire nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_lock; // nios2_qsys_0_instruction_master_translator:uav_lock -> nios2_qsys_0_instruction_master_agent:av_lock
wire nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_write; // nios2_qsys_0_instruction_master_translator:uav_write -> nios2_qsys_0_instruction_master_agent:av_write
wire [31:0] nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_writedata; // nios2_qsys_0_instruction_master_translator:uav_writedata -> nios2_qsys_0_instruction_master_agent:av_writedata
wire [2:0] nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_burstcount; // nios2_qsys_0_instruction_master_translator:uav_burstcount -> nios2_qsys_0_instruction_master_agent:av_burstcount
wire rsp_mux_001_src_valid; // rsp_mux_001:src_valid -> nios2_qsys_0_instruction_master_agent:rp_valid
wire [98:0] rsp_mux_001_src_data; // rsp_mux_001:src_data -> nios2_qsys_0_instruction_master_agent:rp_data
wire rsp_mux_001_src_ready; // nios2_qsys_0_instruction_master_agent:rp_ready -> rsp_mux_001:src_ready
wire [31:0] rsp_mux_001_src_channel; // rsp_mux_001:src_channel -> nios2_qsys_0_instruction_master_agent:rp_channel
wire rsp_mux_001_src_startofpacket; // rsp_mux_001:src_startofpacket -> nios2_qsys_0_instruction_master_agent:rp_startofpacket
wire rsp_mux_001_src_endofpacket; // rsp_mux_001:src_endofpacket -> nios2_qsys_0_instruction_master_agent:rp_endofpacket
wire [31:0] jtag_uart_0_avalon_jtag_slave_agent_m0_readdata; // jtag_uart_0_avalon_jtag_slave_translator:uav_readdata -> jtag_uart_0_avalon_jtag_slave_agent:m0_readdata
wire jtag_uart_0_avalon_jtag_slave_agent_m0_waitrequest; // jtag_uart_0_avalon_jtag_slave_translator:uav_waitrequest -> jtag_uart_0_avalon_jtag_slave_agent:m0_waitrequest
wire jtag_uart_0_avalon_jtag_slave_agent_m0_debugaccess; // jtag_uart_0_avalon_jtag_slave_agent:m0_debugaccess -> jtag_uart_0_avalon_jtag_slave_translator:uav_debugaccess
wire [18:0] jtag_uart_0_avalon_jtag_slave_agent_m0_address; // jtag_uart_0_avalon_jtag_slave_agent:m0_address -> jtag_uart_0_avalon_jtag_slave_translator:uav_address
wire [3:0] jtag_uart_0_avalon_jtag_slave_agent_m0_byteenable; // jtag_uart_0_avalon_jtag_slave_agent:m0_byteenable -> jtag_uart_0_avalon_jtag_slave_translator:uav_byteenable
wire jtag_uart_0_avalon_jtag_slave_agent_m0_read; // jtag_uart_0_avalon_jtag_slave_agent:m0_read -> jtag_uart_0_avalon_jtag_slave_translator:uav_read
wire jtag_uart_0_avalon_jtag_slave_agent_m0_readdatavalid; // jtag_uart_0_avalon_jtag_slave_translator:uav_readdatavalid -> jtag_uart_0_avalon_jtag_slave_agent:m0_readdatavalid
wire jtag_uart_0_avalon_jtag_slave_agent_m0_lock; // jtag_uart_0_avalon_jtag_slave_agent:m0_lock -> jtag_uart_0_avalon_jtag_slave_translator:uav_lock
wire [31:0] jtag_uart_0_avalon_jtag_slave_agent_m0_writedata; // jtag_uart_0_avalon_jtag_slave_agent:m0_writedata -> jtag_uart_0_avalon_jtag_slave_translator:uav_writedata
wire jtag_uart_0_avalon_jtag_slave_agent_m0_write; // jtag_uart_0_avalon_jtag_slave_agent:m0_write -> jtag_uart_0_avalon_jtag_slave_translator:uav_write
wire [2:0] jtag_uart_0_avalon_jtag_slave_agent_m0_burstcount; // jtag_uart_0_avalon_jtag_slave_agent:m0_burstcount -> jtag_uart_0_avalon_jtag_slave_translator:uav_burstcount
wire jtag_uart_0_avalon_jtag_slave_agent_rf_source_valid; // jtag_uart_0_avalon_jtag_slave_agent:rf_source_valid -> jtag_uart_0_avalon_jtag_slave_agent_rsp_fifo:in_valid
wire [99:0] jtag_uart_0_avalon_jtag_slave_agent_rf_source_data; // jtag_uart_0_avalon_jtag_slave_agent:rf_source_data -> jtag_uart_0_avalon_jtag_slave_agent_rsp_fifo:in_data
wire jtag_uart_0_avalon_jtag_slave_agent_rf_source_ready; // jtag_uart_0_avalon_jtag_slave_agent_rsp_fifo:in_ready -> jtag_uart_0_avalon_jtag_slave_agent:rf_source_ready
wire jtag_uart_0_avalon_jtag_slave_agent_rf_source_startofpacket; // jtag_uart_0_avalon_jtag_slave_agent:rf_source_startofpacket -> jtag_uart_0_avalon_jtag_slave_agent_rsp_fifo:in_startofpacket
wire jtag_uart_0_avalon_jtag_slave_agent_rf_source_endofpacket; // jtag_uart_0_avalon_jtag_slave_agent:rf_source_endofpacket -> jtag_uart_0_avalon_jtag_slave_agent_rsp_fifo:in_endofpacket
wire jtag_uart_0_avalon_jtag_slave_agent_rsp_fifo_out_valid; // jtag_uart_0_avalon_jtag_slave_agent_rsp_fifo:out_valid -> jtag_uart_0_avalon_jtag_slave_agent:rf_sink_valid
wire [99:0] jtag_uart_0_avalon_jtag_slave_agent_rsp_fifo_out_data; // jtag_uart_0_avalon_jtag_slave_agent_rsp_fifo:out_data -> jtag_uart_0_avalon_jtag_slave_agent:rf_sink_data
wire jtag_uart_0_avalon_jtag_slave_agent_rsp_fifo_out_ready; // jtag_uart_0_avalon_jtag_slave_agent:rf_sink_ready -> jtag_uart_0_avalon_jtag_slave_agent_rsp_fifo:out_ready
wire jtag_uart_0_avalon_jtag_slave_agent_rsp_fifo_out_startofpacket; // jtag_uart_0_avalon_jtag_slave_agent_rsp_fifo:out_startofpacket -> jtag_uart_0_avalon_jtag_slave_agent:rf_sink_startofpacket
wire jtag_uart_0_avalon_jtag_slave_agent_rsp_fifo_out_endofpacket; // jtag_uart_0_avalon_jtag_slave_agent_rsp_fifo:out_endofpacket -> jtag_uart_0_avalon_jtag_slave_agent:rf_sink_endofpacket
wire jtag_uart_0_avalon_jtag_slave_agent_rdata_fifo_src_valid; // jtag_uart_0_avalon_jtag_slave_agent:rdata_fifo_src_valid -> jtag_uart_0_avalon_jtag_slave_agent:rdata_fifo_sink_valid
wire [33:0] jtag_uart_0_avalon_jtag_slave_agent_rdata_fifo_src_data; // jtag_uart_0_avalon_jtag_slave_agent:rdata_fifo_src_data -> jtag_uart_0_avalon_jtag_slave_agent:rdata_fifo_sink_data
wire jtag_uart_0_avalon_jtag_slave_agent_rdata_fifo_src_ready; // jtag_uart_0_avalon_jtag_slave_agent:rdata_fifo_sink_ready -> jtag_uart_0_avalon_jtag_slave_agent:rdata_fifo_src_ready
wire cmd_mux_src_valid; // cmd_mux:src_valid -> jtag_uart_0_avalon_jtag_slave_agent:cp_valid
wire [98:0] cmd_mux_src_data; // cmd_mux:src_data -> jtag_uart_0_avalon_jtag_slave_agent:cp_data
wire cmd_mux_src_ready; // jtag_uart_0_avalon_jtag_slave_agent:cp_ready -> cmd_mux:src_ready
wire [31:0] cmd_mux_src_channel; // cmd_mux:src_channel -> jtag_uart_0_avalon_jtag_slave_agent:cp_channel
wire cmd_mux_src_startofpacket; // cmd_mux:src_startofpacket -> jtag_uart_0_avalon_jtag_slave_agent:cp_startofpacket
wire cmd_mux_src_endofpacket; // cmd_mux:src_endofpacket -> jtag_uart_0_avalon_jtag_slave_agent:cp_endofpacket
wire [31:0] nios2_qsys_0_debug_mem_slave_agent_m0_readdata; // nios2_qsys_0_debug_mem_slave_translator:uav_readdata -> nios2_qsys_0_debug_mem_slave_agent:m0_readdata
wire nios2_qsys_0_debug_mem_slave_agent_m0_waitrequest; // nios2_qsys_0_debug_mem_slave_translator:uav_waitrequest -> nios2_qsys_0_debug_mem_slave_agent:m0_waitrequest
wire nios2_qsys_0_debug_mem_slave_agent_m0_debugaccess; // nios2_qsys_0_debug_mem_slave_agent:m0_debugaccess -> nios2_qsys_0_debug_mem_slave_translator:uav_debugaccess
wire [18:0] nios2_qsys_0_debug_mem_slave_agent_m0_address; // nios2_qsys_0_debug_mem_slave_agent:m0_address -> nios2_qsys_0_debug_mem_slave_translator:uav_address
wire [3:0] nios2_qsys_0_debug_mem_slave_agent_m0_byteenable; // nios2_qsys_0_debug_mem_slave_agent:m0_byteenable -> nios2_qsys_0_debug_mem_slave_translator:uav_byteenable
wire nios2_qsys_0_debug_mem_slave_agent_m0_read; // nios2_qsys_0_debug_mem_slave_agent:m0_read -> nios2_qsys_0_debug_mem_slave_translator:uav_read
wire nios2_qsys_0_debug_mem_slave_agent_m0_readdatavalid; // nios2_qsys_0_debug_mem_slave_translator:uav_readdatavalid -> nios2_qsys_0_debug_mem_slave_agent:m0_readdatavalid
wire nios2_qsys_0_debug_mem_slave_agent_m0_lock; // nios2_qsys_0_debug_mem_slave_agent:m0_lock -> nios2_qsys_0_debug_mem_slave_translator:uav_lock
wire [31:0] nios2_qsys_0_debug_mem_slave_agent_m0_writedata; // nios2_qsys_0_debug_mem_slave_agent:m0_writedata -> nios2_qsys_0_debug_mem_slave_translator:uav_writedata
wire nios2_qsys_0_debug_mem_slave_agent_m0_write; // nios2_qsys_0_debug_mem_slave_agent:m0_write -> nios2_qsys_0_debug_mem_slave_translator:uav_write
wire [2:0] nios2_qsys_0_debug_mem_slave_agent_m0_burstcount; // nios2_qsys_0_debug_mem_slave_agent:m0_burstcount -> nios2_qsys_0_debug_mem_slave_translator:uav_burstcount
wire nios2_qsys_0_debug_mem_slave_agent_rf_source_valid; // nios2_qsys_0_debug_mem_slave_agent:rf_source_valid -> nios2_qsys_0_debug_mem_slave_agent_rsp_fifo:in_valid
wire [99:0] nios2_qsys_0_debug_mem_slave_agent_rf_source_data; // nios2_qsys_0_debug_mem_slave_agent:rf_source_data -> nios2_qsys_0_debug_mem_slave_agent_rsp_fifo:in_data
wire nios2_qsys_0_debug_mem_slave_agent_rf_source_ready; // nios2_qsys_0_debug_mem_slave_agent_rsp_fifo:in_ready -> nios2_qsys_0_debug_mem_slave_agent:rf_source_ready
wire nios2_qsys_0_debug_mem_slave_agent_rf_source_startofpacket; // nios2_qsys_0_debug_mem_slave_agent:rf_source_startofpacket -> nios2_qsys_0_debug_mem_slave_agent_rsp_fifo:in_startofpacket
wire nios2_qsys_0_debug_mem_slave_agent_rf_source_endofpacket; // nios2_qsys_0_debug_mem_slave_agent:rf_source_endofpacket -> nios2_qsys_0_debug_mem_slave_agent_rsp_fifo:in_endofpacket
wire nios2_qsys_0_debug_mem_slave_agent_rsp_fifo_out_valid; // nios2_qsys_0_debug_mem_slave_agent_rsp_fifo:out_valid -> nios2_qsys_0_debug_mem_slave_agent:rf_sink_valid
wire [99:0] nios2_qsys_0_debug_mem_slave_agent_rsp_fifo_out_data; // nios2_qsys_0_debug_mem_slave_agent_rsp_fifo:out_data -> nios2_qsys_0_debug_mem_slave_agent:rf_sink_data
wire nios2_qsys_0_debug_mem_slave_agent_rsp_fifo_out_ready; // nios2_qsys_0_debug_mem_slave_agent:rf_sink_ready -> nios2_qsys_0_debug_mem_slave_agent_rsp_fifo:out_ready
wire nios2_qsys_0_debug_mem_slave_agent_rsp_fifo_out_startofpacket; // nios2_qsys_0_debug_mem_slave_agent_rsp_fifo:out_startofpacket -> nios2_qsys_0_debug_mem_slave_agent:rf_sink_startofpacket
wire nios2_qsys_0_debug_mem_slave_agent_rsp_fifo_out_endofpacket; // nios2_qsys_0_debug_mem_slave_agent_rsp_fifo:out_endofpacket -> nios2_qsys_0_debug_mem_slave_agent:rf_sink_endofpacket
wire nios2_qsys_0_debug_mem_slave_agent_rdata_fifo_src_valid; // nios2_qsys_0_debug_mem_slave_agent:rdata_fifo_src_valid -> nios2_qsys_0_debug_mem_slave_agent:rdata_fifo_sink_valid
wire [33:0] nios2_qsys_0_debug_mem_slave_agent_rdata_fifo_src_data; // nios2_qsys_0_debug_mem_slave_agent:rdata_fifo_src_data -> nios2_qsys_0_debug_mem_slave_agent:rdata_fifo_sink_data
wire nios2_qsys_0_debug_mem_slave_agent_rdata_fifo_src_ready; // nios2_qsys_0_debug_mem_slave_agent:rdata_fifo_sink_ready -> nios2_qsys_0_debug_mem_slave_agent:rdata_fifo_src_ready
wire cmd_mux_001_src_valid; // cmd_mux_001:src_valid -> nios2_qsys_0_debug_mem_slave_agent:cp_valid
wire [98:0] cmd_mux_001_src_data; // cmd_mux_001:src_data -> nios2_qsys_0_debug_mem_slave_agent:cp_data
wire cmd_mux_001_src_ready; // nios2_qsys_0_debug_mem_slave_agent:cp_ready -> cmd_mux_001:src_ready
wire [31:0] cmd_mux_001_src_channel; // cmd_mux_001:src_channel -> nios2_qsys_0_debug_mem_slave_agent:cp_channel
wire cmd_mux_001_src_startofpacket; // cmd_mux_001:src_startofpacket -> nios2_qsys_0_debug_mem_slave_agent:cp_startofpacket
wire cmd_mux_001_src_endofpacket; // cmd_mux_001:src_endofpacket -> nios2_qsys_0_debug_mem_slave_agent:cp_endofpacket
wire [31:0] onchip_memory2_0_s1_agent_m0_readdata; // onchip_memory2_0_s1_translator:uav_readdata -> onchip_memory2_0_s1_agent:m0_readdata
wire onchip_memory2_0_s1_agent_m0_waitrequest; // onchip_memory2_0_s1_translator:uav_waitrequest -> onchip_memory2_0_s1_agent:m0_waitrequest
wire onchip_memory2_0_s1_agent_m0_debugaccess; // onchip_memory2_0_s1_agent:m0_debugaccess -> onchip_memory2_0_s1_translator:uav_debugaccess
wire [18:0] onchip_memory2_0_s1_agent_m0_address; // onchip_memory2_0_s1_agent:m0_address -> onchip_memory2_0_s1_translator:uav_address
wire [3:0] onchip_memory2_0_s1_agent_m0_byteenable; // onchip_memory2_0_s1_agent:m0_byteenable -> onchip_memory2_0_s1_translator:uav_byteenable
wire onchip_memory2_0_s1_agent_m0_read; // onchip_memory2_0_s1_agent:m0_read -> onchip_memory2_0_s1_translator:uav_read
wire onchip_memory2_0_s1_agent_m0_readdatavalid; // onchip_memory2_0_s1_translator:uav_readdatavalid -> onchip_memory2_0_s1_agent:m0_readdatavalid
wire onchip_memory2_0_s1_agent_m0_lock; // onchip_memory2_0_s1_agent:m0_lock -> onchip_memory2_0_s1_translator:uav_lock
wire [31:0] onchip_memory2_0_s1_agent_m0_writedata; // onchip_memory2_0_s1_agent:m0_writedata -> onchip_memory2_0_s1_translator:uav_writedata
wire onchip_memory2_0_s1_agent_m0_write; // onchip_memory2_0_s1_agent:m0_write -> onchip_memory2_0_s1_translator:uav_write
wire [2:0] onchip_memory2_0_s1_agent_m0_burstcount; // onchip_memory2_0_s1_agent:m0_burstcount -> onchip_memory2_0_s1_translator:uav_burstcount
wire onchip_memory2_0_s1_agent_rf_source_valid; // onchip_memory2_0_s1_agent:rf_source_valid -> onchip_memory2_0_s1_agent_rsp_fifo:in_valid
wire [99:0] onchip_memory2_0_s1_agent_rf_source_data; // onchip_memory2_0_s1_agent:rf_source_data -> onchip_memory2_0_s1_agent_rsp_fifo:in_data
wire onchip_memory2_0_s1_agent_rf_source_ready; // onchip_memory2_0_s1_agent_rsp_fifo:in_ready -> onchip_memory2_0_s1_agent:rf_source_ready
wire onchip_memory2_0_s1_agent_rf_source_startofpacket; // onchip_memory2_0_s1_agent:rf_source_startofpacket -> onchip_memory2_0_s1_agent_rsp_fifo:in_startofpacket
wire onchip_memory2_0_s1_agent_rf_source_endofpacket; // onchip_memory2_0_s1_agent:rf_source_endofpacket -> onchip_memory2_0_s1_agent_rsp_fifo:in_endofpacket
wire onchip_memory2_0_s1_agent_rsp_fifo_out_valid; // onchip_memory2_0_s1_agent_rsp_fifo:out_valid -> onchip_memory2_0_s1_agent:rf_sink_valid
wire [99:0] onchip_memory2_0_s1_agent_rsp_fifo_out_data; // onchip_memory2_0_s1_agent_rsp_fifo:out_data -> onchip_memory2_0_s1_agent:rf_sink_data
wire onchip_memory2_0_s1_agent_rsp_fifo_out_ready; // onchip_memory2_0_s1_agent:rf_sink_ready -> onchip_memory2_0_s1_agent_rsp_fifo:out_ready
wire onchip_memory2_0_s1_agent_rsp_fifo_out_startofpacket; // onchip_memory2_0_s1_agent_rsp_fifo:out_startofpacket -> onchip_memory2_0_s1_agent:rf_sink_startofpacket
wire onchip_memory2_0_s1_agent_rsp_fifo_out_endofpacket; // onchip_memory2_0_s1_agent_rsp_fifo:out_endofpacket -> onchip_memory2_0_s1_agent:rf_sink_endofpacket
wire onchip_memory2_0_s1_agent_rdata_fifo_src_valid; // onchip_memory2_0_s1_agent:rdata_fifo_src_valid -> onchip_memory2_0_s1_agent:rdata_fifo_sink_valid
wire [33:0] onchip_memory2_0_s1_agent_rdata_fifo_src_data; // onchip_memory2_0_s1_agent:rdata_fifo_src_data -> onchip_memory2_0_s1_agent:rdata_fifo_sink_data
wire onchip_memory2_0_s1_agent_rdata_fifo_src_ready; // onchip_memory2_0_s1_agent:rdata_fifo_sink_ready -> onchip_memory2_0_s1_agent:rdata_fifo_src_ready
wire cmd_mux_002_src_valid; // cmd_mux_002:src_valid -> onchip_memory2_0_s1_agent:cp_valid
wire [98:0] cmd_mux_002_src_data; // cmd_mux_002:src_data -> onchip_memory2_0_s1_agent:cp_data
wire cmd_mux_002_src_ready; // onchip_memory2_0_s1_agent:cp_ready -> cmd_mux_002:src_ready
wire [31:0] cmd_mux_002_src_channel; // cmd_mux_002:src_channel -> onchip_memory2_0_s1_agent:cp_channel
wire cmd_mux_002_src_startofpacket; // cmd_mux_002:src_startofpacket -> onchip_memory2_0_s1_agent:cp_startofpacket
wire cmd_mux_002_src_endofpacket; // cmd_mux_002:src_endofpacket -> onchip_memory2_0_s1_agent:cp_endofpacket
wire [31:0] leds_s1_agent_m0_readdata; // LEDs_s1_translator:uav_readdata -> LEDs_s1_agent:m0_readdata
wire leds_s1_agent_m0_waitrequest; // LEDs_s1_translator:uav_waitrequest -> LEDs_s1_agent:m0_waitrequest
wire leds_s1_agent_m0_debugaccess; // LEDs_s1_agent:m0_debugaccess -> LEDs_s1_translator:uav_debugaccess
wire [18:0] leds_s1_agent_m0_address; // LEDs_s1_agent:m0_address -> LEDs_s1_translator:uav_address
wire [3:0] leds_s1_agent_m0_byteenable; // LEDs_s1_agent:m0_byteenable -> LEDs_s1_translator:uav_byteenable
wire leds_s1_agent_m0_read; // LEDs_s1_agent:m0_read -> LEDs_s1_translator:uav_read
wire leds_s1_agent_m0_readdatavalid; // LEDs_s1_translator:uav_readdatavalid -> LEDs_s1_agent:m0_readdatavalid
wire leds_s1_agent_m0_lock; // LEDs_s1_agent:m0_lock -> LEDs_s1_translator:uav_lock
wire [31:0] leds_s1_agent_m0_writedata; // LEDs_s1_agent:m0_writedata -> LEDs_s1_translator:uav_writedata
wire leds_s1_agent_m0_write; // LEDs_s1_agent:m0_write -> LEDs_s1_translator:uav_write
wire [2:0] leds_s1_agent_m0_burstcount; // LEDs_s1_agent:m0_burstcount -> LEDs_s1_translator:uav_burstcount
wire leds_s1_agent_rf_source_valid; // LEDs_s1_agent:rf_source_valid -> LEDs_s1_agent_rsp_fifo:in_valid
wire [99:0] leds_s1_agent_rf_source_data; // LEDs_s1_agent:rf_source_data -> LEDs_s1_agent_rsp_fifo:in_data
wire leds_s1_agent_rf_source_ready; // LEDs_s1_agent_rsp_fifo:in_ready -> LEDs_s1_agent:rf_source_ready
wire leds_s1_agent_rf_source_startofpacket; // LEDs_s1_agent:rf_source_startofpacket -> LEDs_s1_agent_rsp_fifo:in_startofpacket
wire leds_s1_agent_rf_source_endofpacket; // LEDs_s1_agent:rf_source_endofpacket -> LEDs_s1_agent_rsp_fifo:in_endofpacket
wire leds_s1_agent_rsp_fifo_out_valid; // LEDs_s1_agent_rsp_fifo:out_valid -> LEDs_s1_agent:rf_sink_valid
wire [99:0] leds_s1_agent_rsp_fifo_out_data; // LEDs_s1_agent_rsp_fifo:out_data -> LEDs_s1_agent:rf_sink_data
wire leds_s1_agent_rsp_fifo_out_ready; // LEDs_s1_agent:rf_sink_ready -> LEDs_s1_agent_rsp_fifo:out_ready
wire leds_s1_agent_rsp_fifo_out_startofpacket; // LEDs_s1_agent_rsp_fifo:out_startofpacket -> LEDs_s1_agent:rf_sink_startofpacket
wire leds_s1_agent_rsp_fifo_out_endofpacket; // LEDs_s1_agent_rsp_fifo:out_endofpacket -> LEDs_s1_agent:rf_sink_endofpacket
wire leds_s1_agent_rdata_fifo_src_valid; // LEDs_s1_agent:rdata_fifo_src_valid -> LEDs_s1_agent:rdata_fifo_sink_valid
wire [33:0] leds_s1_agent_rdata_fifo_src_data; // LEDs_s1_agent:rdata_fifo_src_data -> LEDs_s1_agent:rdata_fifo_sink_data
wire leds_s1_agent_rdata_fifo_src_ready; // LEDs_s1_agent:rdata_fifo_sink_ready -> LEDs_s1_agent:rdata_fifo_src_ready
wire cmd_mux_003_src_valid; // cmd_mux_003:src_valid -> LEDs_s1_agent:cp_valid
wire [98:0] cmd_mux_003_src_data; // cmd_mux_003:src_data -> LEDs_s1_agent:cp_data
wire cmd_mux_003_src_ready; // LEDs_s1_agent:cp_ready -> cmd_mux_003:src_ready
wire [31:0] cmd_mux_003_src_channel; // cmd_mux_003:src_channel -> LEDs_s1_agent:cp_channel
wire cmd_mux_003_src_startofpacket; // cmd_mux_003:src_startofpacket -> LEDs_s1_agent:cp_startofpacket
wire cmd_mux_003_src_endofpacket; // cmd_mux_003:src_endofpacket -> LEDs_s1_agent:cp_endofpacket
wire [31:0] switches_s1_agent_m0_readdata; // switches_s1_translator:uav_readdata -> switches_s1_agent:m0_readdata
wire switches_s1_agent_m0_waitrequest; // switches_s1_translator:uav_waitrequest -> switches_s1_agent:m0_waitrequest
wire switches_s1_agent_m0_debugaccess; // switches_s1_agent:m0_debugaccess -> switches_s1_translator:uav_debugaccess
wire [18:0] switches_s1_agent_m0_address; // switches_s1_agent:m0_address -> switches_s1_translator:uav_address
wire [3:0] switches_s1_agent_m0_byteenable; // switches_s1_agent:m0_byteenable -> switches_s1_translator:uav_byteenable
wire switches_s1_agent_m0_read; // switches_s1_agent:m0_read -> switches_s1_translator:uav_read
wire switches_s1_agent_m0_readdatavalid; // switches_s1_translator:uav_readdatavalid -> switches_s1_agent:m0_readdatavalid
wire switches_s1_agent_m0_lock; // switches_s1_agent:m0_lock -> switches_s1_translator:uav_lock
wire [31:0] switches_s1_agent_m0_writedata; // switches_s1_agent:m0_writedata -> switches_s1_translator:uav_writedata
wire switches_s1_agent_m0_write; // switches_s1_agent:m0_write -> switches_s1_translator:uav_write
wire [2:0] switches_s1_agent_m0_burstcount; // switches_s1_agent:m0_burstcount -> switches_s1_translator:uav_burstcount
wire switches_s1_agent_rf_source_valid; // switches_s1_agent:rf_source_valid -> switches_s1_agent_rsp_fifo:in_valid
wire [99:0] switches_s1_agent_rf_source_data; // switches_s1_agent:rf_source_data -> switches_s1_agent_rsp_fifo:in_data
wire switches_s1_agent_rf_source_ready; // switches_s1_agent_rsp_fifo:in_ready -> switches_s1_agent:rf_source_ready
wire switches_s1_agent_rf_source_startofpacket; // switches_s1_agent:rf_source_startofpacket -> switches_s1_agent_rsp_fifo:in_startofpacket
wire switches_s1_agent_rf_source_endofpacket; // switches_s1_agent:rf_source_endofpacket -> switches_s1_agent_rsp_fifo:in_endofpacket
wire switches_s1_agent_rsp_fifo_out_valid; // switches_s1_agent_rsp_fifo:out_valid -> switches_s1_agent:rf_sink_valid
wire [99:0] switches_s1_agent_rsp_fifo_out_data; // switches_s1_agent_rsp_fifo:out_data -> switches_s1_agent:rf_sink_data
wire switches_s1_agent_rsp_fifo_out_ready; // switches_s1_agent:rf_sink_ready -> switches_s1_agent_rsp_fifo:out_ready
wire switches_s1_agent_rsp_fifo_out_startofpacket; // switches_s1_agent_rsp_fifo:out_startofpacket -> switches_s1_agent:rf_sink_startofpacket
wire switches_s1_agent_rsp_fifo_out_endofpacket; // switches_s1_agent_rsp_fifo:out_endofpacket -> switches_s1_agent:rf_sink_endofpacket
wire switches_s1_agent_rdata_fifo_src_valid; // switches_s1_agent:rdata_fifo_src_valid -> switches_s1_agent:rdata_fifo_sink_valid
wire [33:0] switches_s1_agent_rdata_fifo_src_data; // switches_s1_agent:rdata_fifo_src_data -> switches_s1_agent:rdata_fifo_sink_data
wire switches_s1_agent_rdata_fifo_src_ready; // switches_s1_agent:rdata_fifo_sink_ready -> switches_s1_agent:rdata_fifo_src_ready
wire cmd_mux_004_src_valid; // cmd_mux_004:src_valid -> switches_s1_agent:cp_valid
wire [98:0] cmd_mux_004_src_data; // cmd_mux_004:src_data -> switches_s1_agent:cp_data
wire cmd_mux_004_src_ready; // switches_s1_agent:cp_ready -> cmd_mux_004:src_ready
wire [31:0] cmd_mux_004_src_channel; // cmd_mux_004:src_channel -> switches_s1_agent:cp_channel
wire cmd_mux_004_src_startofpacket; // cmd_mux_004:src_startofpacket -> switches_s1_agent:cp_startofpacket
wire cmd_mux_004_src_endofpacket; // cmd_mux_004:src_endofpacket -> switches_s1_agent:cp_endofpacket
wire [31:0] sram_data_s1_agent_m0_readdata; // sram_data_s1_translator:uav_readdata -> sram_data_s1_agent:m0_readdata
wire sram_data_s1_agent_m0_waitrequest; // sram_data_s1_translator:uav_waitrequest -> sram_data_s1_agent:m0_waitrequest
wire sram_data_s1_agent_m0_debugaccess; // sram_data_s1_agent:m0_debugaccess -> sram_data_s1_translator:uav_debugaccess
wire [18:0] sram_data_s1_agent_m0_address; // sram_data_s1_agent:m0_address -> sram_data_s1_translator:uav_address
wire [3:0] sram_data_s1_agent_m0_byteenable; // sram_data_s1_agent:m0_byteenable -> sram_data_s1_translator:uav_byteenable
wire sram_data_s1_agent_m0_read; // sram_data_s1_agent:m0_read -> sram_data_s1_translator:uav_read
wire sram_data_s1_agent_m0_readdatavalid; // sram_data_s1_translator:uav_readdatavalid -> sram_data_s1_agent:m0_readdatavalid
wire sram_data_s1_agent_m0_lock; // sram_data_s1_agent:m0_lock -> sram_data_s1_translator:uav_lock
wire [31:0] sram_data_s1_agent_m0_writedata; // sram_data_s1_agent:m0_writedata -> sram_data_s1_translator:uav_writedata
wire sram_data_s1_agent_m0_write; // sram_data_s1_agent:m0_write -> sram_data_s1_translator:uav_write
wire [2:0] sram_data_s1_agent_m0_burstcount; // sram_data_s1_agent:m0_burstcount -> sram_data_s1_translator:uav_burstcount
wire sram_data_s1_agent_rf_source_valid; // sram_data_s1_agent:rf_source_valid -> sram_data_s1_agent_rsp_fifo:in_valid
wire [99:0] sram_data_s1_agent_rf_source_data; // sram_data_s1_agent:rf_source_data -> sram_data_s1_agent_rsp_fifo:in_data
wire sram_data_s1_agent_rf_source_ready; // sram_data_s1_agent_rsp_fifo:in_ready -> sram_data_s1_agent:rf_source_ready
wire sram_data_s1_agent_rf_source_startofpacket; // sram_data_s1_agent:rf_source_startofpacket -> sram_data_s1_agent_rsp_fifo:in_startofpacket
wire sram_data_s1_agent_rf_source_endofpacket; // sram_data_s1_agent:rf_source_endofpacket -> sram_data_s1_agent_rsp_fifo:in_endofpacket
wire sram_data_s1_agent_rsp_fifo_out_valid; // sram_data_s1_agent_rsp_fifo:out_valid -> sram_data_s1_agent:rf_sink_valid
wire [99:0] sram_data_s1_agent_rsp_fifo_out_data; // sram_data_s1_agent_rsp_fifo:out_data -> sram_data_s1_agent:rf_sink_data
wire sram_data_s1_agent_rsp_fifo_out_ready; // sram_data_s1_agent:rf_sink_ready -> sram_data_s1_agent_rsp_fifo:out_ready
wire sram_data_s1_agent_rsp_fifo_out_startofpacket; // sram_data_s1_agent_rsp_fifo:out_startofpacket -> sram_data_s1_agent:rf_sink_startofpacket
wire sram_data_s1_agent_rsp_fifo_out_endofpacket; // sram_data_s1_agent_rsp_fifo:out_endofpacket -> sram_data_s1_agent:rf_sink_endofpacket
wire sram_data_s1_agent_rdata_fifo_src_valid; // sram_data_s1_agent:rdata_fifo_src_valid -> sram_data_s1_agent:rdata_fifo_sink_valid
wire [33:0] sram_data_s1_agent_rdata_fifo_src_data; // sram_data_s1_agent:rdata_fifo_src_data -> sram_data_s1_agent:rdata_fifo_sink_data
wire sram_data_s1_agent_rdata_fifo_src_ready; // sram_data_s1_agent:rdata_fifo_sink_ready -> sram_data_s1_agent:rdata_fifo_src_ready
wire cmd_mux_005_src_valid; // cmd_mux_005:src_valid -> sram_data_s1_agent:cp_valid
wire [98:0] cmd_mux_005_src_data; // cmd_mux_005:src_data -> sram_data_s1_agent:cp_data
wire cmd_mux_005_src_ready; // sram_data_s1_agent:cp_ready -> cmd_mux_005:src_ready
wire [31:0] cmd_mux_005_src_channel; // cmd_mux_005:src_channel -> sram_data_s1_agent:cp_channel
wire cmd_mux_005_src_startofpacket; // cmd_mux_005:src_startofpacket -> sram_data_s1_agent:cp_startofpacket
wire cmd_mux_005_src_endofpacket; // cmd_mux_005:src_endofpacket -> sram_data_s1_agent:cp_endofpacket
wire [31:0] sram_addr_s1_agent_m0_readdata; // sram_addr_s1_translator:uav_readdata -> sram_addr_s1_agent:m0_readdata
wire sram_addr_s1_agent_m0_waitrequest; // sram_addr_s1_translator:uav_waitrequest -> sram_addr_s1_agent:m0_waitrequest
wire sram_addr_s1_agent_m0_debugaccess; // sram_addr_s1_agent:m0_debugaccess -> sram_addr_s1_translator:uav_debugaccess
wire [18:0] sram_addr_s1_agent_m0_address; // sram_addr_s1_agent:m0_address -> sram_addr_s1_translator:uav_address
wire [3:0] sram_addr_s1_agent_m0_byteenable; // sram_addr_s1_agent:m0_byteenable -> sram_addr_s1_translator:uav_byteenable
wire sram_addr_s1_agent_m0_read; // sram_addr_s1_agent:m0_read -> sram_addr_s1_translator:uav_read
wire sram_addr_s1_agent_m0_readdatavalid; // sram_addr_s1_translator:uav_readdatavalid -> sram_addr_s1_agent:m0_readdatavalid
wire sram_addr_s1_agent_m0_lock; // sram_addr_s1_agent:m0_lock -> sram_addr_s1_translator:uav_lock
wire [31:0] sram_addr_s1_agent_m0_writedata; // sram_addr_s1_agent:m0_writedata -> sram_addr_s1_translator:uav_writedata
wire sram_addr_s1_agent_m0_write; // sram_addr_s1_agent:m0_write -> sram_addr_s1_translator:uav_write
wire [2:0] sram_addr_s1_agent_m0_burstcount; // sram_addr_s1_agent:m0_burstcount -> sram_addr_s1_translator:uav_burstcount
wire sram_addr_s1_agent_rf_source_valid; // sram_addr_s1_agent:rf_source_valid -> sram_addr_s1_agent_rsp_fifo:in_valid
wire [99:0] sram_addr_s1_agent_rf_source_data; // sram_addr_s1_agent:rf_source_data -> sram_addr_s1_agent_rsp_fifo:in_data
wire sram_addr_s1_agent_rf_source_ready; // sram_addr_s1_agent_rsp_fifo:in_ready -> sram_addr_s1_agent:rf_source_ready
wire sram_addr_s1_agent_rf_source_startofpacket; // sram_addr_s1_agent:rf_source_startofpacket -> sram_addr_s1_agent_rsp_fifo:in_startofpacket
wire sram_addr_s1_agent_rf_source_endofpacket; // sram_addr_s1_agent:rf_source_endofpacket -> sram_addr_s1_agent_rsp_fifo:in_endofpacket
wire sram_addr_s1_agent_rsp_fifo_out_valid; // sram_addr_s1_agent_rsp_fifo:out_valid -> sram_addr_s1_agent:rf_sink_valid
wire [99:0] sram_addr_s1_agent_rsp_fifo_out_data; // sram_addr_s1_agent_rsp_fifo:out_data -> sram_addr_s1_agent:rf_sink_data
wire sram_addr_s1_agent_rsp_fifo_out_ready; // sram_addr_s1_agent:rf_sink_ready -> sram_addr_s1_agent_rsp_fifo:out_ready
wire sram_addr_s1_agent_rsp_fifo_out_startofpacket; // sram_addr_s1_agent_rsp_fifo:out_startofpacket -> sram_addr_s1_agent:rf_sink_startofpacket
wire sram_addr_s1_agent_rsp_fifo_out_endofpacket; // sram_addr_s1_agent_rsp_fifo:out_endofpacket -> sram_addr_s1_agent:rf_sink_endofpacket
wire sram_addr_s1_agent_rdata_fifo_src_valid; // sram_addr_s1_agent:rdata_fifo_src_valid -> sram_addr_s1_agent:rdata_fifo_sink_valid
wire [33:0] sram_addr_s1_agent_rdata_fifo_src_data; // sram_addr_s1_agent:rdata_fifo_src_data -> sram_addr_s1_agent:rdata_fifo_sink_data
wire sram_addr_s1_agent_rdata_fifo_src_ready; // sram_addr_s1_agent:rdata_fifo_sink_ready -> sram_addr_s1_agent:rdata_fifo_src_ready
wire cmd_mux_006_src_valid; // cmd_mux_006:src_valid -> sram_addr_s1_agent:cp_valid
wire [98:0] cmd_mux_006_src_data; // cmd_mux_006:src_data -> sram_addr_s1_agent:cp_data
wire cmd_mux_006_src_ready; // sram_addr_s1_agent:cp_ready -> cmd_mux_006:src_ready
wire [31:0] cmd_mux_006_src_channel; // cmd_mux_006:src_channel -> sram_addr_s1_agent:cp_channel
wire cmd_mux_006_src_startofpacket; // cmd_mux_006:src_startofpacket -> sram_addr_s1_agent:cp_startofpacket
wire cmd_mux_006_src_endofpacket; // cmd_mux_006:src_endofpacket -> sram_addr_s1_agent:cp_endofpacket
wire [31:0] sram_read_write_s1_agent_m0_readdata; // sram_read_write_s1_translator:uav_readdata -> sram_read_write_s1_agent:m0_readdata
wire sram_read_write_s1_agent_m0_waitrequest; // sram_read_write_s1_translator:uav_waitrequest -> sram_read_write_s1_agent:m0_waitrequest
wire sram_read_write_s1_agent_m0_debugaccess; // sram_read_write_s1_agent:m0_debugaccess -> sram_read_write_s1_translator:uav_debugaccess
wire [18:0] sram_read_write_s1_agent_m0_address; // sram_read_write_s1_agent:m0_address -> sram_read_write_s1_translator:uav_address
wire [3:0] sram_read_write_s1_agent_m0_byteenable; // sram_read_write_s1_agent:m0_byteenable -> sram_read_write_s1_translator:uav_byteenable
wire sram_read_write_s1_agent_m0_read; // sram_read_write_s1_agent:m0_read -> sram_read_write_s1_translator:uav_read
wire sram_read_write_s1_agent_m0_readdatavalid; // sram_read_write_s1_translator:uav_readdatavalid -> sram_read_write_s1_agent:m0_readdatavalid
wire sram_read_write_s1_agent_m0_lock; // sram_read_write_s1_agent:m0_lock -> sram_read_write_s1_translator:uav_lock
wire [31:0] sram_read_write_s1_agent_m0_writedata; // sram_read_write_s1_agent:m0_writedata -> sram_read_write_s1_translator:uav_writedata
wire sram_read_write_s1_agent_m0_write; // sram_read_write_s1_agent:m0_write -> sram_read_write_s1_translator:uav_write
wire [2:0] sram_read_write_s1_agent_m0_burstcount; // sram_read_write_s1_agent:m0_burstcount -> sram_read_write_s1_translator:uav_burstcount
wire sram_read_write_s1_agent_rf_source_valid; // sram_read_write_s1_agent:rf_source_valid -> sram_read_write_s1_agent_rsp_fifo:in_valid
wire [99:0] sram_read_write_s1_agent_rf_source_data; // sram_read_write_s1_agent:rf_source_data -> sram_read_write_s1_agent_rsp_fifo:in_data
wire sram_read_write_s1_agent_rf_source_ready; // sram_read_write_s1_agent_rsp_fifo:in_ready -> sram_read_write_s1_agent:rf_source_ready
wire sram_read_write_s1_agent_rf_source_startofpacket; // sram_read_write_s1_agent:rf_source_startofpacket -> sram_read_write_s1_agent_rsp_fifo:in_startofpacket
wire sram_read_write_s1_agent_rf_source_endofpacket; // sram_read_write_s1_agent:rf_source_endofpacket -> sram_read_write_s1_agent_rsp_fifo:in_endofpacket
wire sram_read_write_s1_agent_rsp_fifo_out_valid; // sram_read_write_s1_agent_rsp_fifo:out_valid -> sram_read_write_s1_agent:rf_sink_valid
wire [99:0] sram_read_write_s1_agent_rsp_fifo_out_data; // sram_read_write_s1_agent_rsp_fifo:out_data -> sram_read_write_s1_agent:rf_sink_data
wire sram_read_write_s1_agent_rsp_fifo_out_ready; // sram_read_write_s1_agent:rf_sink_ready -> sram_read_write_s1_agent_rsp_fifo:out_ready
wire sram_read_write_s1_agent_rsp_fifo_out_startofpacket; // sram_read_write_s1_agent_rsp_fifo:out_startofpacket -> sram_read_write_s1_agent:rf_sink_startofpacket
wire sram_read_write_s1_agent_rsp_fifo_out_endofpacket; // sram_read_write_s1_agent_rsp_fifo:out_endofpacket -> sram_read_write_s1_agent:rf_sink_endofpacket
wire sram_read_write_s1_agent_rdata_fifo_src_valid; // sram_read_write_s1_agent:rdata_fifo_src_valid -> sram_read_write_s1_agent:rdata_fifo_sink_valid
wire [33:0] sram_read_write_s1_agent_rdata_fifo_src_data; // sram_read_write_s1_agent:rdata_fifo_src_data -> sram_read_write_s1_agent:rdata_fifo_sink_data
wire sram_read_write_s1_agent_rdata_fifo_src_ready; // sram_read_write_s1_agent:rdata_fifo_sink_ready -> sram_read_write_s1_agent:rdata_fifo_src_ready
wire cmd_mux_007_src_valid; // cmd_mux_007:src_valid -> sram_read_write_s1_agent:cp_valid
wire [98:0] cmd_mux_007_src_data; // cmd_mux_007:src_data -> sram_read_write_s1_agent:cp_data
wire cmd_mux_007_src_ready; // sram_read_write_s1_agent:cp_ready -> cmd_mux_007:src_ready
wire [31:0] cmd_mux_007_src_channel; // cmd_mux_007:src_channel -> sram_read_write_s1_agent:cp_channel
wire cmd_mux_007_src_startofpacket; // cmd_mux_007:src_startofpacket -> sram_read_write_s1_agent:cp_startofpacket
wire cmd_mux_007_src_endofpacket; // cmd_mux_007:src_endofpacket -> sram_read_write_s1_agent:cp_endofpacket
wire [31:0] sram_cs_s1_agent_m0_readdata; // sram_cs_s1_translator:uav_readdata -> sram_cs_s1_agent:m0_readdata
wire sram_cs_s1_agent_m0_waitrequest; // sram_cs_s1_translator:uav_waitrequest -> sram_cs_s1_agent:m0_waitrequest
wire sram_cs_s1_agent_m0_debugaccess; // sram_cs_s1_agent:m0_debugaccess -> sram_cs_s1_translator:uav_debugaccess
wire [18:0] sram_cs_s1_agent_m0_address; // sram_cs_s1_agent:m0_address -> sram_cs_s1_translator:uav_address
wire [3:0] sram_cs_s1_agent_m0_byteenable; // sram_cs_s1_agent:m0_byteenable -> sram_cs_s1_translator:uav_byteenable
wire sram_cs_s1_agent_m0_read; // sram_cs_s1_agent:m0_read -> sram_cs_s1_translator:uav_read
wire sram_cs_s1_agent_m0_readdatavalid; // sram_cs_s1_translator:uav_readdatavalid -> sram_cs_s1_agent:m0_readdatavalid
wire sram_cs_s1_agent_m0_lock; // sram_cs_s1_agent:m0_lock -> sram_cs_s1_translator:uav_lock
wire [31:0] sram_cs_s1_agent_m0_writedata; // sram_cs_s1_agent:m0_writedata -> sram_cs_s1_translator:uav_writedata
wire sram_cs_s1_agent_m0_write; // sram_cs_s1_agent:m0_write -> sram_cs_s1_translator:uav_write
wire [2:0] sram_cs_s1_agent_m0_burstcount; // sram_cs_s1_agent:m0_burstcount -> sram_cs_s1_translator:uav_burstcount
wire sram_cs_s1_agent_rf_source_valid; // sram_cs_s1_agent:rf_source_valid -> sram_cs_s1_agent_rsp_fifo:in_valid
wire [99:0] sram_cs_s1_agent_rf_source_data; // sram_cs_s1_agent:rf_source_data -> sram_cs_s1_agent_rsp_fifo:in_data
wire sram_cs_s1_agent_rf_source_ready; // sram_cs_s1_agent_rsp_fifo:in_ready -> sram_cs_s1_agent:rf_source_ready
wire sram_cs_s1_agent_rf_source_startofpacket; // sram_cs_s1_agent:rf_source_startofpacket -> sram_cs_s1_agent_rsp_fifo:in_startofpacket
wire sram_cs_s1_agent_rf_source_endofpacket; // sram_cs_s1_agent:rf_source_endofpacket -> sram_cs_s1_agent_rsp_fifo:in_endofpacket
wire sram_cs_s1_agent_rsp_fifo_out_valid; // sram_cs_s1_agent_rsp_fifo:out_valid -> sram_cs_s1_agent:rf_sink_valid
wire [99:0] sram_cs_s1_agent_rsp_fifo_out_data; // sram_cs_s1_agent_rsp_fifo:out_data -> sram_cs_s1_agent:rf_sink_data
wire sram_cs_s1_agent_rsp_fifo_out_ready; // sram_cs_s1_agent:rf_sink_ready -> sram_cs_s1_agent_rsp_fifo:out_ready
wire sram_cs_s1_agent_rsp_fifo_out_startofpacket; // sram_cs_s1_agent_rsp_fifo:out_startofpacket -> sram_cs_s1_agent:rf_sink_startofpacket
wire sram_cs_s1_agent_rsp_fifo_out_endofpacket; // sram_cs_s1_agent_rsp_fifo:out_endofpacket -> sram_cs_s1_agent:rf_sink_endofpacket
wire sram_cs_s1_agent_rdata_fifo_src_valid; // sram_cs_s1_agent:rdata_fifo_src_valid -> sram_cs_s1_agent:rdata_fifo_sink_valid
wire [33:0] sram_cs_s1_agent_rdata_fifo_src_data; // sram_cs_s1_agent:rdata_fifo_src_data -> sram_cs_s1_agent:rdata_fifo_sink_data
wire sram_cs_s1_agent_rdata_fifo_src_ready; // sram_cs_s1_agent:rdata_fifo_sink_ready -> sram_cs_s1_agent:rdata_fifo_src_ready
wire cmd_mux_008_src_valid; // cmd_mux_008:src_valid -> sram_cs_s1_agent:cp_valid
wire [98:0] cmd_mux_008_src_data; // cmd_mux_008:src_data -> sram_cs_s1_agent:cp_data
wire cmd_mux_008_src_ready; // sram_cs_s1_agent:cp_ready -> cmd_mux_008:src_ready
wire [31:0] cmd_mux_008_src_channel; // cmd_mux_008:src_channel -> sram_cs_s1_agent:cp_channel
wire cmd_mux_008_src_startofpacket; // cmd_mux_008:src_startofpacket -> sram_cs_s1_agent:cp_startofpacket
wire cmd_mux_008_src_endofpacket; // cmd_mux_008:src_endofpacket -> sram_cs_s1_agent:cp_endofpacket
wire [31:0] sram_oe_s1_agent_m0_readdata; // sram_oe_s1_translator:uav_readdata -> sram_oe_s1_agent:m0_readdata
wire sram_oe_s1_agent_m0_waitrequest; // sram_oe_s1_translator:uav_waitrequest -> sram_oe_s1_agent:m0_waitrequest
wire sram_oe_s1_agent_m0_debugaccess; // sram_oe_s1_agent:m0_debugaccess -> sram_oe_s1_translator:uav_debugaccess
wire [18:0] sram_oe_s1_agent_m0_address; // sram_oe_s1_agent:m0_address -> sram_oe_s1_translator:uav_address
wire [3:0] sram_oe_s1_agent_m0_byteenable; // sram_oe_s1_agent:m0_byteenable -> sram_oe_s1_translator:uav_byteenable
wire sram_oe_s1_agent_m0_read; // sram_oe_s1_agent:m0_read -> sram_oe_s1_translator:uav_read
wire sram_oe_s1_agent_m0_readdatavalid; // sram_oe_s1_translator:uav_readdatavalid -> sram_oe_s1_agent:m0_readdatavalid
wire sram_oe_s1_agent_m0_lock; // sram_oe_s1_agent:m0_lock -> sram_oe_s1_translator:uav_lock
wire [31:0] sram_oe_s1_agent_m0_writedata; // sram_oe_s1_agent:m0_writedata -> sram_oe_s1_translator:uav_writedata
wire sram_oe_s1_agent_m0_write; // sram_oe_s1_agent:m0_write -> sram_oe_s1_translator:uav_write
wire [2:0] sram_oe_s1_agent_m0_burstcount; // sram_oe_s1_agent:m0_burstcount -> sram_oe_s1_translator:uav_burstcount
wire sram_oe_s1_agent_rf_source_valid; // sram_oe_s1_agent:rf_source_valid -> sram_oe_s1_agent_rsp_fifo:in_valid
wire [99:0] sram_oe_s1_agent_rf_source_data; // sram_oe_s1_agent:rf_source_data -> sram_oe_s1_agent_rsp_fifo:in_data
wire sram_oe_s1_agent_rf_source_ready; // sram_oe_s1_agent_rsp_fifo:in_ready -> sram_oe_s1_agent:rf_source_ready
wire sram_oe_s1_agent_rf_source_startofpacket; // sram_oe_s1_agent:rf_source_startofpacket -> sram_oe_s1_agent_rsp_fifo:in_startofpacket
wire sram_oe_s1_agent_rf_source_endofpacket; // sram_oe_s1_agent:rf_source_endofpacket -> sram_oe_s1_agent_rsp_fifo:in_endofpacket
wire sram_oe_s1_agent_rsp_fifo_out_valid; // sram_oe_s1_agent_rsp_fifo:out_valid -> sram_oe_s1_agent:rf_sink_valid
wire [99:0] sram_oe_s1_agent_rsp_fifo_out_data; // sram_oe_s1_agent_rsp_fifo:out_data -> sram_oe_s1_agent:rf_sink_data
wire sram_oe_s1_agent_rsp_fifo_out_ready; // sram_oe_s1_agent:rf_sink_ready -> sram_oe_s1_agent_rsp_fifo:out_ready
wire sram_oe_s1_agent_rsp_fifo_out_startofpacket; // sram_oe_s1_agent_rsp_fifo:out_startofpacket -> sram_oe_s1_agent:rf_sink_startofpacket
wire sram_oe_s1_agent_rsp_fifo_out_endofpacket; // sram_oe_s1_agent_rsp_fifo:out_endofpacket -> sram_oe_s1_agent:rf_sink_endofpacket
wire sram_oe_s1_agent_rdata_fifo_src_valid; // sram_oe_s1_agent:rdata_fifo_src_valid -> sram_oe_s1_agent:rdata_fifo_sink_valid
wire [33:0] sram_oe_s1_agent_rdata_fifo_src_data; // sram_oe_s1_agent:rdata_fifo_src_data -> sram_oe_s1_agent:rdata_fifo_sink_data
wire sram_oe_s1_agent_rdata_fifo_src_ready; // sram_oe_s1_agent:rdata_fifo_sink_ready -> sram_oe_s1_agent:rdata_fifo_src_ready
wire cmd_mux_009_src_valid; // cmd_mux_009:src_valid -> sram_oe_s1_agent:cp_valid
wire [98:0] cmd_mux_009_src_data; // cmd_mux_009:src_data -> sram_oe_s1_agent:cp_data
wire cmd_mux_009_src_ready; // sram_oe_s1_agent:cp_ready -> cmd_mux_009:src_ready
wire [31:0] cmd_mux_009_src_channel; // cmd_mux_009:src_channel -> sram_oe_s1_agent:cp_channel
wire cmd_mux_009_src_startofpacket; // cmd_mux_009:src_startofpacket -> sram_oe_s1_agent:cp_startofpacket
wire cmd_mux_009_src_endofpacket; // cmd_mux_009:src_endofpacket -> sram_oe_s1_agent:cp_endofpacket
wire [31:0] regfile_data_s1_agent_m0_readdata; // regfile_data_s1_translator:uav_readdata -> regfile_data_s1_agent:m0_readdata
wire regfile_data_s1_agent_m0_waitrequest; // regfile_data_s1_translator:uav_waitrequest -> regfile_data_s1_agent:m0_waitrequest
wire regfile_data_s1_agent_m0_debugaccess; // regfile_data_s1_agent:m0_debugaccess -> regfile_data_s1_translator:uav_debugaccess
wire [18:0] regfile_data_s1_agent_m0_address; // regfile_data_s1_agent:m0_address -> regfile_data_s1_translator:uav_address
wire [3:0] regfile_data_s1_agent_m0_byteenable; // regfile_data_s1_agent:m0_byteenable -> regfile_data_s1_translator:uav_byteenable
wire regfile_data_s1_agent_m0_read; // regfile_data_s1_agent:m0_read -> regfile_data_s1_translator:uav_read
wire regfile_data_s1_agent_m0_readdatavalid; // regfile_data_s1_translator:uav_readdatavalid -> regfile_data_s1_agent:m0_readdatavalid
wire regfile_data_s1_agent_m0_lock; // regfile_data_s1_agent:m0_lock -> regfile_data_s1_translator:uav_lock
wire [31:0] regfile_data_s1_agent_m0_writedata; // regfile_data_s1_agent:m0_writedata -> regfile_data_s1_translator:uav_writedata
wire regfile_data_s1_agent_m0_write; // regfile_data_s1_agent:m0_write -> regfile_data_s1_translator:uav_write
wire [2:0] regfile_data_s1_agent_m0_burstcount; // regfile_data_s1_agent:m0_burstcount -> regfile_data_s1_translator:uav_burstcount
wire regfile_data_s1_agent_rf_source_valid; // regfile_data_s1_agent:rf_source_valid -> regfile_data_s1_agent_rsp_fifo:in_valid
wire [99:0] regfile_data_s1_agent_rf_source_data; // regfile_data_s1_agent:rf_source_data -> regfile_data_s1_agent_rsp_fifo:in_data
wire regfile_data_s1_agent_rf_source_ready; // regfile_data_s1_agent_rsp_fifo:in_ready -> regfile_data_s1_agent:rf_source_ready
wire regfile_data_s1_agent_rf_source_startofpacket; // regfile_data_s1_agent:rf_source_startofpacket -> regfile_data_s1_agent_rsp_fifo:in_startofpacket
wire regfile_data_s1_agent_rf_source_endofpacket; // regfile_data_s1_agent:rf_source_endofpacket -> regfile_data_s1_agent_rsp_fifo:in_endofpacket
wire regfile_data_s1_agent_rsp_fifo_out_valid; // regfile_data_s1_agent_rsp_fifo:out_valid -> regfile_data_s1_agent:rf_sink_valid
wire [99:0] regfile_data_s1_agent_rsp_fifo_out_data; // regfile_data_s1_agent_rsp_fifo:out_data -> regfile_data_s1_agent:rf_sink_data
wire regfile_data_s1_agent_rsp_fifo_out_ready; // regfile_data_s1_agent:rf_sink_ready -> regfile_data_s1_agent_rsp_fifo:out_ready
wire regfile_data_s1_agent_rsp_fifo_out_startofpacket; // regfile_data_s1_agent_rsp_fifo:out_startofpacket -> regfile_data_s1_agent:rf_sink_startofpacket
wire regfile_data_s1_agent_rsp_fifo_out_endofpacket; // regfile_data_s1_agent_rsp_fifo:out_endofpacket -> regfile_data_s1_agent:rf_sink_endofpacket
wire regfile_data_s1_agent_rdata_fifo_src_valid; // regfile_data_s1_agent:rdata_fifo_src_valid -> regfile_data_s1_agent:rdata_fifo_sink_valid
wire [33:0] regfile_data_s1_agent_rdata_fifo_src_data; // regfile_data_s1_agent:rdata_fifo_src_data -> regfile_data_s1_agent:rdata_fifo_sink_data
wire regfile_data_s1_agent_rdata_fifo_src_ready; // regfile_data_s1_agent:rdata_fifo_sink_ready -> regfile_data_s1_agent:rdata_fifo_src_ready
wire cmd_mux_010_src_valid; // cmd_mux_010:src_valid -> regfile_data_s1_agent:cp_valid
wire [98:0] cmd_mux_010_src_data; // cmd_mux_010:src_data -> regfile_data_s1_agent:cp_data
wire cmd_mux_010_src_ready; // regfile_data_s1_agent:cp_ready -> cmd_mux_010:src_ready
wire [31:0] cmd_mux_010_src_channel; // cmd_mux_010:src_channel -> regfile_data_s1_agent:cp_channel
wire cmd_mux_010_src_startofpacket; // cmd_mux_010:src_startofpacket -> regfile_data_s1_agent:cp_startofpacket
wire cmd_mux_010_src_endofpacket; // cmd_mux_010:src_endofpacket -> regfile_data_s1_agent:cp_endofpacket
wire [31:0] regfile_reg1_s1_agent_m0_readdata; // regfile_reg1_s1_translator:uav_readdata -> regfile_reg1_s1_agent:m0_readdata
wire regfile_reg1_s1_agent_m0_waitrequest; // regfile_reg1_s1_translator:uav_waitrequest -> regfile_reg1_s1_agent:m0_waitrequest
wire regfile_reg1_s1_agent_m0_debugaccess; // regfile_reg1_s1_agent:m0_debugaccess -> regfile_reg1_s1_translator:uav_debugaccess
wire [18:0] regfile_reg1_s1_agent_m0_address; // regfile_reg1_s1_agent:m0_address -> regfile_reg1_s1_translator:uav_address
wire [3:0] regfile_reg1_s1_agent_m0_byteenable; // regfile_reg1_s1_agent:m0_byteenable -> regfile_reg1_s1_translator:uav_byteenable
wire regfile_reg1_s1_agent_m0_read; // regfile_reg1_s1_agent:m0_read -> regfile_reg1_s1_translator:uav_read
wire regfile_reg1_s1_agent_m0_readdatavalid; // regfile_reg1_s1_translator:uav_readdatavalid -> regfile_reg1_s1_agent:m0_readdatavalid
wire regfile_reg1_s1_agent_m0_lock; // regfile_reg1_s1_agent:m0_lock -> regfile_reg1_s1_translator:uav_lock
wire [31:0] regfile_reg1_s1_agent_m0_writedata; // regfile_reg1_s1_agent:m0_writedata -> regfile_reg1_s1_translator:uav_writedata
wire regfile_reg1_s1_agent_m0_write; // regfile_reg1_s1_agent:m0_write -> regfile_reg1_s1_translator:uav_write
wire [2:0] regfile_reg1_s1_agent_m0_burstcount; // regfile_reg1_s1_agent:m0_burstcount -> regfile_reg1_s1_translator:uav_burstcount
wire regfile_reg1_s1_agent_rf_source_valid; // regfile_reg1_s1_agent:rf_source_valid -> regfile_reg1_s1_agent_rsp_fifo:in_valid
wire [99:0] regfile_reg1_s1_agent_rf_source_data; // regfile_reg1_s1_agent:rf_source_data -> regfile_reg1_s1_agent_rsp_fifo:in_data
wire regfile_reg1_s1_agent_rf_source_ready; // regfile_reg1_s1_agent_rsp_fifo:in_ready -> regfile_reg1_s1_agent:rf_source_ready
wire regfile_reg1_s1_agent_rf_source_startofpacket; // regfile_reg1_s1_agent:rf_source_startofpacket -> regfile_reg1_s1_agent_rsp_fifo:in_startofpacket
wire regfile_reg1_s1_agent_rf_source_endofpacket; // regfile_reg1_s1_agent:rf_source_endofpacket -> regfile_reg1_s1_agent_rsp_fifo:in_endofpacket
wire regfile_reg1_s1_agent_rsp_fifo_out_valid; // regfile_reg1_s1_agent_rsp_fifo:out_valid -> regfile_reg1_s1_agent:rf_sink_valid
wire [99:0] regfile_reg1_s1_agent_rsp_fifo_out_data; // regfile_reg1_s1_agent_rsp_fifo:out_data -> regfile_reg1_s1_agent:rf_sink_data
wire regfile_reg1_s1_agent_rsp_fifo_out_ready; // regfile_reg1_s1_agent:rf_sink_ready -> regfile_reg1_s1_agent_rsp_fifo:out_ready
wire regfile_reg1_s1_agent_rsp_fifo_out_startofpacket; // regfile_reg1_s1_agent_rsp_fifo:out_startofpacket -> regfile_reg1_s1_agent:rf_sink_startofpacket
wire regfile_reg1_s1_agent_rsp_fifo_out_endofpacket; // regfile_reg1_s1_agent_rsp_fifo:out_endofpacket -> regfile_reg1_s1_agent:rf_sink_endofpacket
wire regfile_reg1_s1_agent_rdata_fifo_src_valid; // regfile_reg1_s1_agent:rdata_fifo_src_valid -> regfile_reg1_s1_agent:rdata_fifo_sink_valid
wire [33:0] regfile_reg1_s1_agent_rdata_fifo_src_data; // regfile_reg1_s1_agent:rdata_fifo_src_data -> regfile_reg1_s1_agent:rdata_fifo_sink_data
wire regfile_reg1_s1_agent_rdata_fifo_src_ready; // regfile_reg1_s1_agent:rdata_fifo_sink_ready -> regfile_reg1_s1_agent:rdata_fifo_src_ready
wire cmd_mux_011_src_valid; // cmd_mux_011:src_valid -> regfile_reg1_s1_agent:cp_valid
wire [98:0] cmd_mux_011_src_data; // cmd_mux_011:src_data -> regfile_reg1_s1_agent:cp_data
wire cmd_mux_011_src_ready; // regfile_reg1_s1_agent:cp_ready -> cmd_mux_011:src_ready
wire [31:0] cmd_mux_011_src_channel; // cmd_mux_011:src_channel -> regfile_reg1_s1_agent:cp_channel
wire cmd_mux_011_src_startofpacket; // cmd_mux_011:src_startofpacket -> regfile_reg1_s1_agent:cp_startofpacket
wire cmd_mux_011_src_endofpacket; // cmd_mux_011:src_endofpacket -> regfile_reg1_s1_agent:cp_endofpacket
wire [31:0] regfile_reg2_s1_agent_m0_readdata; // regfile_reg2_s1_translator:uav_readdata -> regfile_reg2_s1_agent:m0_readdata
wire regfile_reg2_s1_agent_m0_waitrequest; // regfile_reg2_s1_translator:uav_waitrequest -> regfile_reg2_s1_agent:m0_waitrequest
wire regfile_reg2_s1_agent_m0_debugaccess; // regfile_reg2_s1_agent:m0_debugaccess -> regfile_reg2_s1_translator:uav_debugaccess
wire [18:0] regfile_reg2_s1_agent_m0_address; // regfile_reg2_s1_agent:m0_address -> regfile_reg2_s1_translator:uav_address
wire [3:0] regfile_reg2_s1_agent_m0_byteenable; // regfile_reg2_s1_agent:m0_byteenable -> regfile_reg2_s1_translator:uav_byteenable
wire regfile_reg2_s1_agent_m0_read; // regfile_reg2_s1_agent:m0_read -> regfile_reg2_s1_translator:uav_read
wire regfile_reg2_s1_agent_m0_readdatavalid; // regfile_reg2_s1_translator:uav_readdatavalid -> regfile_reg2_s1_agent:m0_readdatavalid
wire regfile_reg2_s1_agent_m0_lock; // regfile_reg2_s1_agent:m0_lock -> regfile_reg2_s1_translator:uav_lock
wire [31:0] regfile_reg2_s1_agent_m0_writedata; // regfile_reg2_s1_agent:m0_writedata -> regfile_reg2_s1_translator:uav_writedata
wire regfile_reg2_s1_agent_m0_write; // regfile_reg2_s1_agent:m0_write -> regfile_reg2_s1_translator:uav_write
wire [2:0] regfile_reg2_s1_agent_m0_burstcount; // regfile_reg2_s1_agent:m0_burstcount -> regfile_reg2_s1_translator:uav_burstcount
wire regfile_reg2_s1_agent_rf_source_valid; // regfile_reg2_s1_agent:rf_source_valid -> regfile_reg2_s1_agent_rsp_fifo:in_valid
wire [99:0] regfile_reg2_s1_agent_rf_source_data; // regfile_reg2_s1_agent:rf_source_data -> regfile_reg2_s1_agent_rsp_fifo:in_data
wire regfile_reg2_s1_agent_rf_source_ready; // regfile_reg2_s1_agent_rsp_fifo:in_ready -> regfile_reg2_s1_agent:rf_source_ready
wire regfile_reg2_s1_agent_rf_source_startofpacket; // regfile_reg2_s1_agent:rf_source_startofpacket -> regfile_reg2_s1_agent_rsp_fifo:in_startofpacket
wire regfile_reg2_s1_agent_rf_source_endofpacket; // regfile_reg2_s1_agent:rf_source_endofpacket -> regfile_reg2_s1_agent_rsp_fifo:in_endofpacket
wire regfile_reg2_s1_agent_rsp_fifo_out_valid; // regfile_reg2_s1_agent_rsp_fifo:out_valid -> regfile_reg2_s1_agent:rf_sink_valid
wire [99:0] regfile_reg2_s1_agent_rsp_fifo_out_data; // regfile_reg2_s1_agent_rsp_fifo:out_data -> regfile_reg2_s1_agent:rf_sink_data
wire regfile_reg2_s1_agent_rsp_fifo_out_ready; // regfile_reg2_s1_agent:rf_sink_ready -> regfile_reg2_s1_agent_rsp_fifo:out_ready
wire regfile_reg2_s1_agent_rsp_fifo_out_startofpacket; // regfile_reg2_s1_agent_rsp_fifo:out_startofpacket -> regfile_reg2_s1_agent:rf_sink_startofpacket
wire regfile_reg2_s1_agent_rsp_fifo_out_endofpacket; // regfile_reg2_s1_agent_rsp_fifo:out_endofpacket -> regfile_reg2_s1_agent:rf_sink_endofpacket
wire regfile_reg2_s1_agent_rdata_fifo_src_valid; // regfile_reg2_s1_agent:rdata_fifo_src_valid -> regfile_reg2_s1_agent:rdata_fifo_sink_valid
wire [33:0] regfile_reg2_s1_agent_rdata_fifo_src_data; // regfile_reg2_s1_agent:rdata_fifo_src_data -> regfile_reg2_s1_agent:rdata_fifo_sink_data
wire regfile_reg2_s1_agent_rdata_fifo_src_ready; // regfile_reg2_s1_agent:rdata_fifo_sink_ready -> regfile_reg2_s1_agent:rdata_fifo_src_ready
wire cmd_mux_012_src_valid; // cmd_mux_012:src_valid -> regfile_reg2_s1_agent:cp_valid
wire [98:0] cmd_mux_012_src_data; // cmd_mux_012:src_data -> regfile_reg2_s1_agent:cp_data
wire cmd_mux_012_src_ready; // regfile_reg2_s1_agent:cp_ready -> cmd_mux_012:src_ready
wire [31:0] cmd_mux_012_src_channel; // cmd_mux_012:src_channel -> regfile_reg2_s1_agent:cp_channel
wire cmd_mux_012_src_startofpacket; // cmd_mux_012:src_startofpacket -> regfile_reg2_s1_agent:cp_startofpacket
wire cmd_mux_012_src_endofpacket; // cmd_mux_012:src_endofpacket -> regfile_reg2_s1_agent:cp_endofpacket
wire [31:0] regfile_r1sel_s1_agent_m0_readdata; // regfile_r1sel_s1_translator:uav_readdata -> regfile_r1sel_s1_agent:m0_readdata
wire regfile_r1sel_s1_agent_m0_waitrequest; // regfile_r1sel_s1_translator:uav_waitrequest -> regfile_r1sel_s1_agent:m0_waitrequest
wire regfile_r1sel_s1_agent_m0_debugaccess; // regfile_r1sel_s1_agent:m0_debugaccess -> regfile_r1sel_s1_translator:uav_debugaccess
wire [18:0] regfile_r1sel_s1_agent_m0_address; // regfile_r1sel_s1_agent:m0_address -> regfile_r1sel_s1_translator:uav_address
wire [3:0] regfile_r1sel_s1_agent_m0_byteenable; // regfile_r1sel_s1_agent:m0_byteenable -> regfile_r1sel_s1_translator:uav_byteenable
wire regfile_r1sel_s1_agent_m0_read; // regfile_r1sel_s1_agent:m0_read -> regfile_r1sel_s1_translator:uav_read
wire regfile_r1sel_s1_agent_m0_readdatavalid; // regfile_r1sel_s1_translator:uav_readdatavalid -> regfile_r1sel_s1_agent:m0_readdatavalid
wire regfile_r1sel_s1_agent_m0_lock; // regfile_r1sel_s1_agent:m0_lock -> regfile_r1sel_s1_translator:uav_lock
wire [31:0] regfile_r1sel_s1_agent_m0_writedata; // regfile_r1sel_s1_agent:m0_writedata -> regfile_r1sel_s1_translator:uav_writedata
wire regfile_r1sel_s1_agent_m0_write; // regfile_r1sel_s1_agent:m0_write -> regfile_r1sel_s1_translator:uav_write
wire [2:0] regfile_r1sel_s1_agent_m0_burstcount; // regfile_r1sel_s1_agent:m0_burstcount -> regfile_r1sel_s1_translator:uav_burstcount
wire regfile_r1sel_s1_agent_rf_source_valid; // regfile_r1sel_s1_agent:rf_source_valid -> regfile_r1sel_s1_agent_rsp_fifo:in_valid
wire [99:0] regfile_r1sel_s1_agent_rf_source_data; // regfile_r1sel_s1_agent:rf_source_data -> regfile_r1sel_s1_agent_rsp_fifo:in_data
wire regfile_r1sel_s1_agent_rf_source_ready; // regfile_r1sel_s1_agent_rsp_fifo:in_ready -> regfile_r1sel_s1_agent:rf_source_ready
wire regfile_r1sel_s1_agent_rf_source_startofpacket; // regfile_r1sel_s1_agent:rf_source_startofpacket -> regfile_r1sel_s1_agent_rsp_fifo:in_startofpacket
wire regfile_r1sel_s1_agent_rf_source_endofpacket; // regfile_r1sel_s1_agent:rf_source_endofpacket -> regfile_r1sel_s1_agent_rsp_fifo:in_endofpacket
wire regfile_r1sel_s1_agent_rsp_fifo_out_valid; // regfile_r1sel_s1_agent_rsp_fifo:out_valid -> regfile_r1sel_s1_agent:rf_sink_valid
wire [99:0] regfile_r1sel_s1_agent_rsp_fifo_out_data; // regfile_r1sel_s1_agent_rsp_fifo:out_data -> regfile_r1sel_s1_agent:rf_sink_data
wire regfile_r1sel_s1_agent_rsp_fifo_out_ready; // regfile_r1sel_s1_agent:rf_sink_ready -> regfile_r1sel_s1_agent_rsp_fifo:out_ready
wire regfile_r1sel_s1_agent_rsp_fifo_out_startofpacket; // regfile_r1sel_s1_agent_rsp_fifo:out_startofpacket -> regfile_r1sel_s1_agent:rf_sink_startofpacket
wire regfile_r1sel_s1_agent_rsp_fifo_out_endofpacket; // regfile_r1sel_s1_agent_rsp_fifo:out_endofpacket -> regfile_r1sel_s1_agent:rf_sink_endofpacket
wire regfile_r1sel_s1_agent_rdata_fifo_src_valid; // regfile_r1sel_s1_agent:rdata_fifo_src_valid -> regfile_r1sel_s1_agent:rdata_fifo_sink_valid
wire [33:0] regfile_r1sel_s1_agent_rdata_fifo_src_data; // regfile_r1sel_s1_agent:rdata_fifo_src_data -> regfile_r1sel_s1_agent:rdata_fifo_sink_data
wire regfile_r1sel_s1_agent_rdata_fifo_src_ready; // regfile_r1sel_s1_agent:rdata_fifo_sink_ready -> regfile_r1sel_s1_agent:rdata_fifo_src_ready
wire cmd_mux_013_src_valid; // cmd_mux_013:src_valid -> regfile_r1sel_s1_agent:cp_valid
wire [98:0] cmd_mux_013_src_data; // cmd_mux_013:src_data -> regfile_r1sel_s1_agent:cp_data
wire cmd_mux_013_src_ready; // regfile_r1sel_s1_agent:cp_ready -> cmd_mux_013:src_ready
wire [31:0] cmd_mux_013_src_channel; // cmd_mux_013:src_channel -> regfile_r1sel_s1_agent:cp_channel
wire cmd_mux_013_src_startofpacket; // cmd_mux_013:src_startofpacket -> regfile_r1sel_s1_agent:cp_startofpacket
wire cmd_mux_013_src_endofpacket; // cmd_mux_013:src_endofpacket -> regfile_r1sel_s1_agent:cp_endofpacket
wire [31:0] regfile_r2sel_s1_agent_m0_readdata; // regfile_r2sel_s1_translator:uav_readdata -> regfile_r2sel_s1_agent:m0_readdata
wire regfile_r2sel_s1_agent_m0_waitrequest; // regfile_r2sel_s1_translator:uav_waitrequest -> regfile_r2sel_s1_agent:m0_waitrequest
wire regfile_r2sel_s1_agent_m0_debugaccess; // regfile_r2sel_s1_agent:m0_debugaccess -> regfile_r2sel_s1_translator:uav_debugaccess
wire [18:0] regfile_r2sel_s1_agent_m0_address; // regfile_r2sel_s1_agent:m0_address -> regfile_r2sel_s1_translator:uav_address
wire [3:0] regfile_r2sel_s1_agent_m0_byteenable; // regfile_r2sel_s1_agent:m0_byteenable -> regfile_r2sel_s1_translator:uav_byteenable
wire regfile_r2sel_s1_agent_m0_read; // regfile_r2sel_s1_agent:m0_read -> regfile_r2sel_s1_translator:uav_read
wire regfile_r2sel_s1_agent_m0_readdatavalid; // regfile_r2sel_s1_translator:uav_readdatavalid -> regfile_r2sel_s1_agent:m0_readdatavalid
wire regfile_r2sel_s1_agent_m0_lock; // regfile_r2sel_s1_agent:m0_lock -> regfile_r2sel_s1_translator:uav_lock
wire [31:0] regfile_r2sel_s1_agent_m0_writedata; // regfile_r2sel_s1_agent:m0_writedata -> regfile_r2sel_s1_translator:uav_writedata
wire regfile_r2sel_s1_agent_m0_write; // regfile_r2sel_s1_agent:m0_write -> regfile_r2sel_s1_translator:uav_write
wire [2:0] regfile_r2sel_s1_agent_m0_burstcount; // regfile_r2sel_s1_agent:m0_burstcount -> regfile_r2sel_s1_translator:uav_burstcount
wire regfile_r2sel_s1_agent_rf_source_valid; // regfile_r2sel_s1_agent:rf_source_valid -> regfile_r2sel_s1_agent_rsp_fifo:in_valid
wire [99:0] regfile_r2sel_s1_agent_rf_source_data; // regfile_r2sel_s1_agent:rf_source_data -> regfile_r2sel_s1_agent_rsp_fifo:in_data
wire regfile_r2sel_s1_agent_rf_source_ready; // regfile_r2sel_s1_agent_rsp_fifo:in_ready -> regfile_r2sel_s1_agent:rf_source_ready
wire regfile_r2sel_s1_agent_rf_source_startofpacket; // regfile_r2sel_s1_agent:rf_source_startofpacket -> regfile_r2sel_s1_agent_rsp_fifo:in_startofpacket
wire regfile_r2sel_s1_agent_rf_source_endofpacket; // regfile_r2sel_s1_agent:rf_source_endofpacket -> regfile_r2sel_s1_agent_rsp_fifo:in_endofpacket
wire regfile_r2sel_s1_agent_rsp_fifo_out_valid; // regfile_r2sel_s1_agent_rsp_fifo:out_valid -> regfile_r2sel_s1_agent:rf_sink_valid
wire [99:0] regfile_r2sel_s1_agent_rsp_fifo_out_data; // regfile_r2sel_s1_agent_rsp_fifo:out_data -> regfile_r2sel_s1_agent:rf_sink_data
wire regfile_r2sel_s1_agent_rsp_fifo_out_ready; // regfile_r2sel_s1_agent:rf_sink_ready -> regfile_r2sel_s1_agent_rsp_fifo:out_ready
wire regfile_r2sel_s1_agent_rsp_fifo_out_startofpacket; // regfile_r2sel_s1_agent_rsp_fifo:out_startofpacket -> regfile_r2sel_s1_agent:rf_sink_startofpacket
wire regfile_r2sel_s1_agent_rsp_fifo_out_endofpacket; // regfile_r2sel_s1_agent_rsp_fifo:out_endofpacket -> regfile_r2sel_s1_agent:rf_sink_endofpacket
wire regfile_r2sel_s1_agent_rdata_fifo_src_valid; // regfile_r2sel_s1_agent:rdata_fifo_src_valid -> regfile_r2sel_s1_agent:rdata_fifo_sink_valid
wire [33:0] regfile_r2sel_s1_agent_rdata_fifo_src_data; // regfile_r2sel_s1_agent:rdata_fifo_src_data -> regfile_r2sel_s1_agent:rdata_fifo_sink_data
wire regfile_r2sel_s1_agent_rdata_fifo_src_ready; // regfile_r2sel_s1_agent:rdata_fifo_sink_ready -> regfile_r2sel_s1_agent:rdata_fifo_src_ready
wire cmd_mux_014_src_valid; // cmd_mux_014:src_valid -> regfile_r2sel_s1_agent:cp_valid
wire [98:0] cmd_mux_014_src_data; // cmd_mux_014:src_data -> regfile_r2sel_s1_agent:cp_data
wire cmd_mux_014_src_ready; // regfile_r2sel_s1_agent:cp_ready -> cmd_mux_014:src_ready
wire [31:0] cmd_mux_014_src_channel; // cmd_mux_014:src_channel -> regfile_r2sel_s1_agent:cp_channel
wire cmd_mux_014_src_startofpacket; // cmd_mux_014:src_startofpacket -> regfile_r2sel_s1_agent:cp_startofpacket
wire cmd_mux_014_src_endofpacket; // cmd_mux_014:src_endofpacket -> regfile_r2sel_s1_agent:cp_endofpacket
wire [31:0] regfile_wsel_s1_agent_m0_readdata; // regfile_wsel_s1_translator:uav_readdata -> regfile_wsel_s1_agent:m0_readdata
wire regfile_wsel_s1_agent_m0_waitrequest; // regfile_wsel_s1_translator:uav_waitrequest -> regfile_wsel_s1_agent:m0_waitrequest
wire regfile_wsel_s1_agent_m0_debugaccess; // regfile_wsel_s1_agent:m0_debugaccess -> regfile_wsel_s1_translator:uav_debugaccess
wire [18:0] regfile_wsel_s1_agent_m0_address; // regfile_wsel_s1_agent:m0_address -> regfile_wsel_s1_translator:uav_address
wire [3:0] regfile_wsel_s1_agent_m0_byteenable; // regfile_wsel_s1_agent:m0_byteenable -> regfile_wsel_s1_translator:uav_byteenable
wire regfile_wsel_s1_agent_m0_read; // regfile_wsel_s1_agent:m0_read -> regfile_wsel_s1_translator:uav_read
wire regfile_wsel_s1_agent_m0_readdatavalid; // regfile_wsel_s1_translator:uav_readdatavalid -> regfile_wsel_s1_agent:m0_readdatavalid
wire regfile_wsel_s1_agent_m0_lock; // regfile_wsel_s1_agent:m0_lock -> regfile_wsel_s1_translator:uav_lock
wire [31:0] regfile_wsel_s1_agent_m0_writedata; // regfile_wsel_s1_agent:m0_writedata -> regfile_wsel_s1_translator:uav_writedata
wire regfile_wsel_s1_agent_m0_write; // regfile_wsel_s1_agent:m0_write -> regfile_wsel_s1_translator:uav_write
wire [2:0] regfile_wsel_s1_agent_m0_burstcount; // regfile_wsel_s1_agent:m0_burstcount -> regfile_wsel_s1_translator:uav_burstcount
wire regfile_wsel_s1_agent_rf_source_valid; // regfile_wsel_s1_agent:rf_source_valid -> regfile_wsel_s1_agent_rsp_fifo:in_valid
wire [99:0] regfile_wsel_s1_agent_rf_source_data; // regfile_wsel_s1_agent:rf_source_data -> regfile_wsel_s1_agent_rsp_fifo:in_data
wire regfile_wsel_s1_agent_rf_source_ready; // regfile_wsel_s1_agent_rsp_fifo:in_ready -> regfile_wsel_s1_agent:rf_source_ready
wire regfile_wsel_s1_agent_rf_source_startofpacket; // regfile_wsel_s1_agent:rf_source_startofpacket -> regfile_wsel_s1_agent_rsp_fifo:in_startofpacket
wire regfile_wsel_s1_agent_rf_source_endofpacket; // regfile_wsel_s1_agent:rf_source_endofpacket -> regfile_wsel_s1_agent_rsp_fifo:in_endofpacket
wire regfile_wsel_s1_agent_rsp_fifo_out_valid; // regfile_wsel_s1_agent_rsp_fifo:out_valid -> regfile_wsel_s1_agent:rf_sink_valid
wire [99:0] regfile_wsel_s1_agent_rsp_fifo_out_data; // regfile_wsel_s1_agent_rsp_fifo:out_data -> regfile_wsel_s1_agent:rf_sink_data
wire regfile_wsel_s1_agent_rsp_fifo_out_ready; // regfile_wsel_s1_agent:rf_sink_ready -> regfile_wsel_s1_agent_rsp_fifo:out_ready
wire regfile_wsel_s1_agent_rsp_fifo_out_startofpacket; // regfile_wsel_s1_agent_rsp_fifo:out_startofpacket -> regfile_wsel_s1_agent:rf_sink_startofpacket
wire regfile_wsel_s1_agent_rsp_fifo_out_endofpacket; // regfile_wsel_s1_agent_rsp_fifo:out_endofpacket -> regfile_wsel_s1_agent:rf_sink_endofpacket
wire regfile_wsel_s1_agent_rdata_fifo_src_valid; // regfile_wsel_s1_agent:rdata_fifo_src_valid -> regfile_wsel_s1_agent:rdata_fifo_sink_valid
wire [33:0] regfile_wsel_s1_agent_rdata_fifo_src_data; // regfile_wsel_s1_agent:rdata_fifo_src_data -> regfile_wsel_s1_agent:rdata_fifo_sink_data
wire regfile_wsel_s1_agent_rdata_fifo_src_ready; // regfile_wsel_s1_agent:rdata_fifo_sink_ready -> regfile_wsel_s1_agent:rdata_fifo_src_ready
wire cmd_mux_015_src_valid; // cmd_mux_015:src_valid -> regfile_wsel_s1_agent:cp_valid
wire [98:0] cmd_mux_015_src_data; // cmd_mux_015:src_data -> regfile_wsel_s1_agent:cp_data
wire cmd_mux_015_src_ready; // regfile_wsel_s1_agent:cp_ready -> cmd_mux_015:src_ready
wire [31:0] cmd_mux_015_src_channel; // cmd_mux_015:src_channel -> regfile_wsel_s1_agent:cp_channel
wire cmd_mux_015_src_startofpacket; // cmd_mux_015:src_startofpacket -> regfile_wsel_s1_agent:cp_startofpacket
wire cmd_mux_015_src_endofpacket; // cmd_mux_015:src_endofpacket -> regfile_wsel_s1_agent:cp_endofpacket
wire [31:0] regfile_we_s1_agent_m0_readdata; // regfile_we_s1_translator:uav_readdata -> regfile_we_s1_agent:m0_readdata
wire regfile_we_s1_agent_m0_waitrequest; // regfile_we_s1_translator:uav_waitrequest -> regfile_we_s1_agent:m0_waitrequest
wire regfile_we_s1_agent_m0_debugaccess; // regfile_we_s1_agent:m0_debugaccess -> regfile_we_s1_translator:uav_debugaccess
wire [18:0] regfile_we_s1_agent_m0_address; // regfile_we_s1_agent:m0_address -> regfile_we_s1_translator:uav_address
wire [3:0] regfile_we_s1_agent_m0_byteenable; // regfile_we_s1_agent:m0_byteenable -> regfile_we_s1_translator:uav_byteenable
wire regfile_we_s1_agent_m0_read; // regfile_we_s1_agent:m0_read -> regfile_we_s1_translator:uav_read
wire regfile_we_s1_agent_m0_readdatavalid; // regfile_we_s1_translator:uav_readdatavalid -> regfile_we_s1_agent:m0_readdatavalid
wire regfile_we_s1_agent_m0_lock; // regfile_we_s1_agent:m0_lock -> regfile_we_s1_translator:uav_lock
wire [31:0] regfile_we_s1_agent_m0_writedata; // regfile_we_s1_agent:m0_writedata -> regfile_we_s1_translator:uav_writedata
wire regfile_we_s1_agent_m0_write; // regfile_we_s1_agent:m0_write -> regfile_we_s1_translator:uav_write
wire [2:0] regfile_we_s1_agent_m0_burstcount; // regfile_we_s1_agent:m0_burstcount -> regfile_we_s1_translator:uav_burstcount
wire regfile_we_s1_agent_rf_source_valid; // regfile_we_s1_agent:rf_source_valid -> regfile_we_s1_agent_rsp_fifo:in_valid
wire [99:0] regfile_we_s1_agent_rf_source_data; // regfile_we_s1_agent:rf_source_data -> regfile_we_s1_agent_rsp_fifo:in_data
wire regfile_we_s1_agent_rf_source_ready; // regfile_we_s1_agent_rsp_fifo:in_ready -> regfile_we_s1_agent:rf_source_ready
wire regfile_we_s1_agent_rf_source_startofpacket; // regfile_we_s1_agent:rf_source_startofpacket -> regfile_we_s1_agent_rsp_fifo:in_startofpacket
wire regfile_we_s1_agent_rf_source_endofpacket; // regfile_we_s1_agent:rf_source_endofpacket -> regfile_we_s1_agent_rsp_fifo:in_endofpacket
wire regfile_we_s1_agent_rsp_fifo_out_valid; // regfile_we_s1_agent_rsp_fifo:out_valid -> regfile_we_s1_agent:rf_sink_valid
wire [99:0] regfile_we_s1_agent_rsp_fifo_out_data; // regfile_we_s1_agent_rsp_fifo:out_data -> regfile_we_s1_agent:rf_sink_data
wire regfile_we_s1_agent_rsp_fifo_out_ready; // regfile_we_s1_agent:rf_sink_ready -> regfile_we_s1_agent_rsp_fifo:out_ready
wire regfile_we_s1_agent_rsp_fifo_out_startofpacket; // regfile_we_s1_agent_rsp_fifo:out_startofpacket -> regfile_we_s1_agent:rf_sink_startofpacket
wire regfile_we_s1_agent_rsp_fifo_out_endofpacket; // regfile_we_s1_agent_rsp_fifo:out_endofpacket -> regfile_we_s1_agent:rf_sink_endofpacket
wire regfile_we_s1_agent_rdata_fifo_src_valid; // regfile_we_s1_agent:rdata_fifo_src_valid -> regfile_we_s1_agent:rdata_fifo_sink_valid
wire [33:0] regfile_we_s1_agent_rdata_fifo_src_data; // regfile_we_s1_agent:rdata_fifo_src_data -> regfile_we_s1_agent:rdata_fifo_sink_data
wire regfile_we_s1_agent_rdata_fifo_src_ready; // regfile_we_s1_agent:rdata_fifo_sink_ready -> regfile_we_s1_agent:rdata_fifo_src_ready
wire cmd_mux_016_src_valid; // cmd_mux_016:src_valid -> regfile_we_s1_agent:cp_valid
wire [98:0] cmd_mux_016_src_data; // cmd_mux_016:src_data -> regfile_we_s1_agent:cp_data
wire cmd_mux_016_src_ready; // regfile_we_s1_agent:cp_ready -> cmd_mux_016:src_ready
wire [31:0] cmd_mux_016_src_channel; // cmd_mux_016:src_channel -> regfile_we_s1_agent:cp_channel
wire cmd_mux_016_src_startofpacket; // cmd_mux_016:src_startofpacket -> regfile_we_s1_agent:cp_startofpacket
wire cmd_mux_016_src_endofpacket; // cmd_mux_016:src_endofpacket -> regfile_we_s1_agent:cp_endofpacket
wire [31:0] hex_0_s1_agent_m0_readdata; // hex_0_s1_translator:uav_readdata -> hex_0_s1_agent:m0_readdata
wire hex_0_s1_agent_m0_waitrequest; // hex_0_s1_translator:uav_waitrequest -> hex_0_s1_agent:m0_waitrequest
wire hex_0_s1_agent_m0_debugaccess; // hex_0_s1_agent:m0_debugaccess -> hex_0_s1_translator:uav_debugaccess
wire [18:0] hex_0_s1_agent_m0_address; // hex_0_s1_agent:m0_address -> hex_0_s1_translator:uav_address
wire [3:0] hex_0_s1_agent_m0_byteenable; // hex_0_s1_agent:m0_byteenable -> hex_0_s1_translator:uav_byteenable
wire hex_0_s1_agent_m0_read; // hex_0_s1_agent:m0_read -> hex_0_s1_translator:uav_read
wire hex_0_s1_agent_m0_readdatavalid; // hex_0_s1_translator:uav_readdatavalid -> hex_0_s1_agent:m0_readdatavalid
wire hex_0_s1_agent_m0_lock; // hex_0_s1_agent:m0_lock -> hex_0_s1_translator:uav_lock
wire [31:0] hex_0_s1_agent_m0_writedata; // hex_0_s1_agent:m0_writedata -> hex_0_s1_translator:uav_writedata
wire hex_0_s1_agent_m0_write; // hex_0_s1_agent:m0_write -> hex_0_s1_translator:uav_write
wire [2:0] hex_0_s1_agent_m0_burstcount; // hex_0_s1_agent:m0_burstcount -> hex_0_s1_translator:uav_burstcount
wire hex_0_s1_agent_rf_source_valid; // hex_0_s1_agent:rf_source_valid -> hex_0_s1_agent_rsp_fifo:in_valid
wire [99:0] hex_0_s1_agent_rf_source_data; // hex_0_s1_agent:rf_source_data -> hex_0_s1_agent_rsp_fifo:in_data
wire hex_0_s1_agent_rf_source_ready; // hex_0_s1_agent_rsp_fifo:in_ready -> hex_0_s1_agent:rf_source_ready
wire hex_0_s1_agent_rf_source_startofpacket; // hex_0_s1_agent:rf_source_startofpacket -> hex_0_s1_agent_rsp_fifo:in_startofpacket
wire hex_0_s1_agent_rf_source_endofpacket; // hex_0_s1_agent:rf_source_endofpacket -> hex_0_s1_agent_rsp_fifo:in_endofpacket
wire hex_0_s1_agent_rsp_fifo_out_valid; // hex_0_s1_agent_rsp_fifo:out_valid -> hex_0_s1_agent:rf_sink_valid
wire [99:0] hex_0_s1_agent_rsp_fifo_out_data; // hex_0_s1_agent_rsp_fifo:out_data -> hex_0_s1_agent:rf_sink_data
wire hex_0_s1_agent_rsp_fifo_out_ready; // hex_0_s1_agent:rf_sink_ready -> hex_0_s1_agent_rsp_fifo:out_ready
wire hex_0_s1_agent_rsp_fifo_out_startofpacket; // hex_0_s1_agent_rsp_fifo:out_startofpacket -> hex_0_s1_agent:rf_sink_startofpacket
wire hex_0_s1_agent_rsp_fifo_out_endofpacket; // hex_0_s1_agent_rsp_fifo:out_endofpacket -> hex_0_s1_agent:rf_sink_endofpacket
wire hex_0_s1_agent_rdata_fifo_src_valid; // hex_0_s1_agent:rdata_fifo_src_valid -> hex_0_s1_agent:rdata_fifo_sink_valid
wire [33:0] hex_0_s1_agent_rdata_fifo_src_data; // hex_0_s1_agent:rdata_fifo_src_data -> hex_0_s1_agent:rdata_fifo_sink_data
wire hex_0_s1_agent_rdata_fifo_src_ready; // hex_0_s1_agent:rdata_fifo_sink_ready -> hex_0_s1_agent:rdata_fifo_src_ready
wire cmd_mux_017_src_valid; // cmd_mux_017:src_valid -> hex_0_s1_agent:cp_valid
wire [98:0] cmd_mux_017_src_data; // cmd_mux_017:src_data -> hex_0_s1_agent:cp_data
wire cmd_mux_017_src_ready; // hex_0_s1_agent:cp_ready -> cmd_mux_017:src_ready
wire [31:0] cmd_mux_017_src_channel; // cmd_mux_017:src_channel -> hex_0_s1_agent:cp_channel
wire cmd_mux_017_src_startofpacket; // cmd_mux_017:src_startofpacket -> hex_0_s1_agent:cp_startofpacket
wire cmd_mux_017_src_endofpacket; // cmd_mux_017:src_endofpacket -> hex_0_s1_agent:cp_endofpacket
wire [31:0] hex_1_s1_agent_m0_readdata; // hex_1_s1_translator:uav_readdata -> hex_1_s1_agent:m0_readdata
wire hex_1_s1_agent_m0_waitrequest; // hex_1_s1_translator:uav_waitrequest -> hex_1_s1_agent:m0_waitrequest
wire hex_1_s1_agent_m0_debugaccess; // hex_1_s1_agent:m0_debugaccess -> hex_1_s1_translator:uav_debugaccess
wire [18:0] hex_1_s1_agent_m0_address; // hex_1_s1_agent:m0_address -> hex_1_s1_translator:uav_address
wire [3:0] hex_1_s1_agent_m0_byteenable; // hex_1_s1_agent:m0_byteenable -> hex_1_s1_translator:uav_byteenable
wire hex_1_s1_agent_m0_read; // hex_1_s1_agent:m0_read -> hex_1_s1_translator:uav_read
wire hex_1_s1_agent_m0_readdatavalid; // hex_1_s1_translator:uav_readdatavalid -> hex_1_s1_agent:m0_readdatavalid
wire hex_1_s1_agent_m0_lock; // hex_1_s1_agent:m0_lock -> hex_1_s1_translator:uav_lock
wire [31:0] hex_1_s1_agent_m0_writedata; // hex_1_s1_agent:m0_writedata -> hex_1_s1_translator:uav_writedata
wire hex_1_s1_agent_m0_write; // hex_1_s1_agent:m0_write -> hex_1_s1_translator:uav_write
wire [2:0] hex_1_s1_agent_m0_burstcount; // hex_1_s1_agent:m0_burstcount -> hex_1_s1_translator:uav_burstcount
wire hex_1_s1_agent_rf_source_valid; // hex_1_s1_agent:rf_source_valid -> hex_1_s1_agent_rsp_fifo:in_valid
wire [99:0] hex_1_s1_agent_rf_source_data; // hex_1_s1_agent:rf_source_data -> hex_1_s1_agent_rsp_fifo:in_data
wire hex_1_s1_agent_rf_source_ready; // hex_1_s1_agent_rsp_fifo:in_ready -> hex_1_s1_agent:rf_source_ready
wire hex_1_s1_agent_rf_source_startofpacket; // hex_1_s1_agent:rf_source_startofpacket -> hex_1_s1_agent_rsp_fifo:in_startofpacket
wire hex_1_s1_agent_rf_source_endofpacket; // hex_1_s1_agent:rf_source_endofpacket -> hex_1_s1_agent_rsp_fifo:in_endofpacket
wire hex_1_s1_agent_rsp_fifo_out_valid; // hex_1_s1_agent_rsp_fifo:out_valid -> hex_1_s1_agent:rf_sink_valid
wire [99:0] hex_1_s1_agent_rsp_fifo_out_data; // hex_1_s1_agent_rsp_fifo:out_data -> hex_1_s1_agent:rf_sink_data
wire hex_1_s1_agent_rsp_fifo_out_ready; // hex_1_s1_agent:rf_sink_ready -> hex_1_s1_agent_rsp_fifo:out_ready
wire hex_1_s1_agent_rsp_fifo_out_startofpacket; // hex_1_s1_agent_rsp_fifo:out_startofpacket -> hex_1_s1_agent:rf_sink_startofpacket
wire hex_1_s1_agent_rsp_fifo_out_endofpacket; // hex_1_s1_agent_rsp_fifo:out_endofpacket -> hex_1_s1_agent:rf_sink_endofpacket
wire hex_1_s1_agent_rdata_fifo_src_valid; // hex_1_s1_agent:rdata_fifo_src_valid -> hex_1_s1_agent:rdata_fifo_sink_valid
wire [33:0] hex_1_s1_agent_rdata_fifo_src_data; // hex_1_s1_agent:rdata_fifo_src_data -> hex_1_s1_agent:rdata_fifo_sink_data
wire hex_1_s1_agent_rdata_fifo_src_ready; // hex_1_s1_agent:rdata_fifo_sink_ready -> hex_1_s1_agent:rdata_fifo_src_ready
wire cmd_mux_018_src_valid; // cmd_mux_018:src_valid -> hex_1_s1_agent:cp_valid
wire [98:0] cmd_mux_018_src_data; // cmd_mux_018:src_data -> hex_1_s1_agent:cp_data
wire cmd_mux_018_src_ready; // hex_1_s1_agent:cp_ready -> cmd_mux_018:src_ready
wire [31:0] cmd_mux_018_src_channel; // cmd_mux_018:src_channel -> hex_1_s1_agent:cp_channel
wire cmd_mux_018_src_startofpacket; // cmd_mux_018:src_startofpacket -> hex_1_s1_agent:cp_startofpacket
wire cmd_mux_018_src_endofpacket; // cmd_mux_018:src_endofpacket -> hex_1_s1_agent:cp_endofpacket
wire [31:0] hex_2_s1_agent_m0_readdata; // hex_2_s1_translator:uav_readdata -> hex_2_s1_agent:m0_readdata
wire hex_2_s1_agent_m0_waitrequest; // hex_2_s1_translator:uav_waitrequest -> hex_2_s1_agent:m0_waitrequest
wire hex_2_s1_agent_m0_debugaccess; // hex_2_s1_agent:m0_debugaccess -> hex_2_s1_translator:uav_debugaccess
wire [18:0] hex_2_s1_agent_m0_address; // hex_2_s1_agent:m0_address -> hex_2_s1_translator:uav_address
wire [3:0] hex_2_s1_agent_m0_byteenable; // hex_2_s1_agent:m0_byteenable -> hex_2_s1_translator:uav_byteenable
wire hex_2_s1_agent_m0_read; // hex_2_s1_agent:m0_read -> hex_2_s1_translator:uav_read
wire hex_2_s1_agent_m0_readdatavalid; // hex_2_s1_translator:uav_readdatavalid -> hex_2_s1_agent:m0_readdatavalid
wire hex_2_s1_agent_m0_lock; // hex_2_s1_agent:m0_lock -> hex_2_s1_translator:uav_lock
wire [31:0] hex_2_s1_agent_m0_writedata; // hex_2_s1_agent:m0_writedata -> hex_2_s1_translator:uav_writedata
wire hex_2_s1_agent_m0_write; // hex_2_s1_agent:m0_write -> hex_2_s1_translator:uav_write
wire [2:0] hex_2_s1_agent_m0_burstcount; // hex_2_s1_agent:m0_burstcount -> hex_2_s1_translator:uav_burstcount
wire hex_2_s1_agent_rf_source_valid; // hex_2_s1_agent:rf_source_valid -> hex_2_s1_agent_rsp_fifo:in_valid
wire [99:0] hex_2_s1_agent_rf_source_data; // hex_2_s1_agent:rf_source_data -> hex_2_s1_agent_rsp_fifo:in_data
wire hex_2_s1_agent_rf_source_ready; // hex_2_s1_agent_rsp_fifo:in_ready -> hex_2_s1_agent:rf_source_ready
wire hex_2_s1_agent_rf_source_startofpacket; // hex_2_s1_agent:rf_source_startofpacket -> hex_2_s1_agent_rsp_fifo:in_startofpacket
wire hex_2_s1_agent_rf_source_endofpacket; // hex_2_s1_agent:rf_source_endofpacket -> hex_2_s1_agent_rsp_fifo:in_endofpacket
wire hex_2_s1_agent_rsp_fifo_out_valid; // hex_2_s1_agent_rsp_fifo:out_valid -> hex_2_s1_agent:rf_sink_valid
wire [99:0] hex_2_s1_agent_rsp_fifo_out_data; // hex_2_s1_agent_rsp_fifo:out_data -> hex_2_s1_agent:rf_sink_data
wire hex_2_s1_agent_rsp_fifo_out_ready; // hex_2_s1_agent:rf_sink_ready -> hex_2_s1_agent_rsp_fifo:out_ready
wire hex_2_s1_agent_rsp_fifo_out_startofpacket; // hex_2_s1_agent_rsp_fifo:out_startofpacket -> hex_2_s1_agent:rf_sink_startofpacket
wire hex_2_s1_agent_rsp_fifo_out_endofpacket; // hex_2_s1_agent_rsp_fifo:out_endofpacket -> hex_2_s1_agent:rf_sink_endofpacket
wire hex_2_s1_agent_rdata_fifo_src_valid; // hex_2_s1_agent:rdata_fifo_src_valid -> hex_2_s1_agent:rdata_fifo_sink_valid
wire [33:0] hex_2_s1_agent_rdata_fifo_src_data; // hex_2_s1_agent:rdata_fifo_src_data -> hex_2_s1_agent:rdata_fifo_sink_data
wire hex_2_s1_agent_rdata_fifo_src_ready; // hex_2_s1_agent:rdata_fifo_sink_ready -> hex_2_s1_agent:rdata_fifo_src_ready
wire cmd_mux_019_src_valid; // cmd_mux_019:src_valid -> hex_2_s1_agent:cp_valid
wire [98:0] cmd_mux_019_src_data; // cmd_mux_019:src_data -> hex_2_s1_agent:cp_data
wire cmd_mux_019_src_ready; // hex_2_s1_agent:cp_ready -> cmd_mux_019:src_ready
wire [31:0] cmd_mux_019_src_channel; // cmd_mux_019:src_channel -> hex_2_s1_agent:cp_channel
wire cmd_mux_019_src_startofpacket; // cmd_mux_019:src_startofpacket -> hex_2_s1_agent:cp_startofpacket
wire cmd_mux_019_src_endofpacket; // cmd_mux_019:src_endofpacket -> hex_2_s1_agent:cp_endofpacket
wire [31:0] hex_3_s1_agent_m0_readdata; // hex_3_s1_translator:uav_readdata -> hex_3_s1_agent:m0_readdata
wire hex_3_s1_agent_m0_waitrequest; // hex_3_s1_translator:uav_waitrequest -> hex_3_s1_agent:m0_waitrequest
wire hex_3_s1_agent_m0_debugaccess; // hex_3_s1_agent:m0_debugaccess -> hex_3_s1_translator:uav_debugaccess
wire [18:0] hex_3_s1_agent_m0_address; // hex_3_s1_agent:m0_address -> hex_3_s1_translator:uav_address
wire [3:0] hex_3_s1_agent_m0_byteenable; // hex_3_s1_agent:m0_byteenable -> hex_3_s1_translator:uav_byteenable
wire hex_3_s1_agent_m0_read; // hex_3_s1_agent:m0_read -> hex_3_s1_translator:uav_read
wire hex_3_s1_agent_m0_readdatavalid; // hex_3_s1_translator:uav_readdatavalid -> hex_3_s1_agent:m0_readdatavalid
wire hex_3_s1_agent_m0_lock; // hex_3_s1_agent:m0_lock -> hex_3_s1_translator:uav_lock
wire [31:0] hex_3_s1_agent_m0_writedata; // hex_3_s1_agent:m0_writedata -> hex_3_s1_translator:uav_writedata
wire hex_3_s1_agent_m0_write; // hex_3_s1_agent:m0_write -> hex_3_s1_translator:uav_write
wire [2:0] hex_3_s1_agent_m0_burstcount; // hex_3_s1_agent:m0_burstcount -> hex_3_s1_translator:uav_burstcount
wire hex_3_s1_agent_rf_source_valid; // hex_3_s1_agent:rf_source_valid -> hex_3_s1_agent_rsp_fifo:in_valid
wire [99:0] hex_3_s1_agent_rf_source_data; // hex_3_s1_agent:rf_source_data -> hex_3_s1_agent_rsp_fifo:in_data
wire hex_3_s1_agent_rf_source_ready; // hex_3_s1_agent_rsp_fifo:in_ready -> hex_3_s1_agent:rf_source_ready
wire hex_3_s1_agent_rf_source_startofpacket; // hex_3_s1_agent:rf_source_startofpacket -> hex_3_s1_agent_rsp_fifo:in_startofpacket
wire hex_3_s1_agent_rf_source_endofpacket; // hex_3_s1_agent:rf_source_endofpacket -> hex_3_s1_agent_rsp_fifo:in_endofpacket
wire hex_3_s1_agent_rsp_fifo_out_valid; // hex_3_s1_agent_rsp_fifo:out_valid -> hex_3_s1_agent:rf_sink_valid
wire [99:0] hex_3_s1_agent_rsp_fifo_out_data; // hex_3_s1_agent_rsp_fifo:out_data -> hex_3_s1_agent:rf_sink_data
wire hex_3_s1_agent_rsp_fifo_out_ready; // hex_3_s1_agent:rf_sink_ready -> hex_3_s1_agent_rsp_fifo:out_ready
wire hex_3_s1_agent_rsp_fifo_out_startofpacket; // hex_3_s1_agent_rsp_fifo:out_startofpacket -> hex_3_s1_agent:rf_sink_startofpacket
wire hex_3_s1_agent_rsp_fifo_out_endofpacket; // hex_3_s1_agent_rsp_fifo:out_endofpacket -> hex_3_s1_agent:rf_sink_endofpacket
wire hex_3_s1_agent_rdata_fifo_src_valid; // hex_3_s1_agent:rdata_fifo_src_valid -> hex_3_s1_agent:rdata_fifo_sink_valid
wire [33:0] hex_3_s1_agent_rdata_fifo_src_data; // hex_3_s1_agent:rdata_fifo_src_data -> hex_3_s1_agent:rdata_fifo_sink_data
wire hex_3_s1_agent_rdata_fifo_src_ready; // hex_3_s1_agent:rdata_fifo_sink_ready -> hex_3_s1_agent:rdata_fifo_src_ready
wire cmd_mux_020_src_valid; // cmd_mux_020:src_valid -> hex_3_s1_agent:cp_valid
wire [98:0] cmd_mux_020_src_data; // cmd_mux_020:src_data -> hex_3_s1_agent:cp_data
wire cmd_mux_020_src_ready; // hex_3_s1_agent:cp_ready -> cmd_mux_020:src_ready
wire [31:0] cmd_mux_020_src_channel; // cmd_mux_020:src_channel -> hex_3_s1_agent:cp_channel
wire cmd_mux_020_src_startofpacket; // cmd_mux_020:src_startofpacket -> hex_3_s1_agent:cp_startofpacket
wire cmd_mux_020_src_endofpacket; // cmd_mux_020:src_endofpacket -> hex_3_s1_agent:cp_endofpacket
wire [31:0] hex_4_s1_agent_m0_readdata; // hex_4_s1_translator:uav_readdata -> hex_4_s1_agent:m0_readdata
wire hex_4_s1_agent_m0_waitrequest; // hex_4_s1_translator:uav_waitrequest -> hex_4_s1_agent:m0_waitrequest
wire hex_4_s1_agent_m0_debugaccess; // hex_4_s1_agent:m0_debugaccess -> hex_4_s1_translator:uav_debugaccess
wire [18:0] hex_4_s1_agent_m0_address; // hex_4_s1_agent:m0_address -> hex_4_s1_translator:uav_address
wire [3:0] hex_4_s1_agent_m0_byteenable; // hex_4_s1_agent:m0_byteenable -> hex_4_s1_translator:uav_byteenable
wire hex_4_s1_agent_m0_read; // hex_4_s1_agent:m0_read -> hex_4_s1_translator:uav_read
wire hex_4_s1_agent_m0_readdatavalid; // hex_4_s1_translator:uav_readdatavalid -> hex_4_s1_agent:m0_readdatavalid
wire hex_4_s1_agent_m0_lock; // hex_4_s1_agent:m0_lock -> hex_4_s1_translator:uav_lock
wire [31:0] hex_4_s1_agent_m0_writedata; // hex_4_s1_agent:m0_writedata -> hex_4_s1_translator:uav_writedata
wire hex_4_s1_agent_m0_write; // hex_4_s1_agent:m0_write -> hex_4_s1_translator:uav_write
wire [2:0] hex_4_s1_agent_m0_burstcount; // hex_4_s1_agent:m0_burstcount -> hex_4_s1_translator:uav_burstcount
wire hex_4_s1_agent_rf_source_valid; // hex_4_s1_agent:rf_source_valid -> hex_4_s1_agent_rsp_fifo:in_valid
wire [99:0] hex_4_s1_agent_rf_source_data; // hex_4_s1_agent:rf_source_data -> hex_4_s1_agent_rsp_fifo:in_data
wire hex_4_s1_agent_rf_source_ready; // hex_4_s1_agent_rsp_fifo:in_ready -> hex_4_s1_agent:rf_source_ready
wire hex_4_s1_agent_rf_source_startofpacket; // hex_4_s1_agent:rf_source_startofpacket -> hex_4_s1_agent_rsp_fifo:in_startofpacket
wire hex_4_s1_agent_rf_source_endofpacket; // hex_4_s1_agent:rf_source_endofpacket -> hex_4_s1_agent_rsp_fifo:in_endofpacket
wire hex_4_s1_agent_rsp_fifo_out_valid; // hex_4_s1_agent_rsp_fifo:out_valid -> hex_4_s1_agent:rf_sink_valid
wire [99:0] hex_4_s1_agent_rsp_fifo_out_data; // hex_4_s1_agent_rsp_fifo:out_data -> hex_4_s1_agent:rf_sink_data
wire hex_4_s1_agent_rsp_fifo_out_ready; // hex_4_s1_agent:rf_sink_ready -> hex_4_s1_agent_rsp_fifo:out_ready
wire hex_4_s1_agent_rsp_fifo_out_startofpacket; // hex_4_s1_agent_rsp_fifo:out_startofpacket -> hex_4_s1_agent:rf_sink_startofpacket
wire hex_4_s1_agent_rsp_fifo_out_endofpacket; // hex_4_s1_agent_rsp_fifo:out_endofpacket -> hex_4_s1_agent:rf_sink_endofpacket
wire hex_4_s1_agent_rdata_fifo_src_valid; // hex_4_s1_agent:rdata_fifo_src_valid -> hex_4_s1_agent:rdata_fifo_sink_valid
wire [33:0] hex_4_s1_agent_rdata_fifo_src_data; // hex_4_s1_agent:rdata_fifo_src_data -> hex_4_s1_agent:rdata_fifo_sink_data
wire hex_4_s1_agent_rdata_fifo_src_ready; // hex_4_s1_agent:rdata_fifo_sink_ready -> hex_4_s1_agent:rdata_fifo_src_ready
wire cmd_mux_021_src_valid; // cmd_mux_021:src_valid -> hex_4_s1_agent:cp_valid
wire [98:0] cmd_mux_021_src_data; // cmd_mux_021:src_data -> hex_4_s1_agent:cp_data
wire cmd_mux_021_src_ready; // hex_4_s1_agent:cp_ready -> cmd_mux_021:src_ready
wire [31:0] cmd_mux_021_src_channel; // cmd_mux_021:src_channel -> hex_4_s1_agent:cp_channel
wire cmd_mux_021_src_startofpacket; // cmd_mux_021:src_startofpacket -> hex_4_s1_agent:cp_startofpacket
wire cmd_mux_021_src_endofpacket; // cmd_mux_021:src_endofpacket -> hex_4_s1_agent:cp_endofpacket
wire [31:0] hex_5_s1_agent_m0_readdata; // hex_5_s1_translator:uav_readdata -> hex_5_s1_agent:m0_readdata
wire hex_5_s1_agent_m0_waitrequest; // hex_5_s1_translator:uav_waitrequest -> hex_5_s1_agent:m0_waitrequest
wire hex_5_s1_agent_m0_debugaccess; // hex_5_s1_agent:m0_debugaccess -> hex_5_s1_translator:uav_debugaccess
wire [18:0] hex_5_s1_agent_m0_address; // hex_5_s1_agent:m0_address -> hex_5_s1_translator:uav_address
wire [3:0] hex_5_s1_agent_m0_byteenable; // hex_5_s1_agent:m0_byteenable -> hex_5_s1_translator:uav_byteenable
wire hex_5_s1_agent_m0_read; // hex_5_s1_agent:m0_read -> hex_5_s1_translator:uav_read
wire hex_5_s1_agent_m0_readdatavalid; // hex_5_s1_translator:uav_readdatavalid -> hex_5_s1_agent:m0_readdatavalid
wire hex_5_s1_agent_m0_lock; // hex_5_s1_agent:m0_lock -> hex_5_s1_translator:uav_lock
wire [31:0] hex_5_s1_agent_m0_writedata; // hex_5_s1_agent:m0_writedata -> hex_5_s1_translator:uav_writedata
wire hex_5_s1_agent_m0_write; // hex_5_s1_agent:m0_write -> hex_5_s1_translator:uav_write
wire [2:0] hex_5_s1_agent_m0_burstcount; // hex_5_s1_agent:m0_burstcount -> hex_5_s1_translator:uav_burstcount
wire hex_5_s1_agent_rf_source_valid; // hex_5_s1_agent:rf_source_valid -> hex_5_s1_agent_rsp_fifo:in_valid
wire [99:0] hex_5_s1_agent_rf_source_data; // hex_5_s1_agent:rf_source_data -> hex_5_s1_agent_rsp_fifo:in_data
wire hex_5_s1_agent_rf_source_ready; // hex_5_s1_agent_rsp_fifo:in_ready -> hex_5_s1_agent:rf_source_ready
wire hex_5_s1_agent_rf_source_startofpacket; // hex_5_s1_agent:rf_source_startofpacket -> hex_5_s1_agent_rsp_fifo:in_startofpacket
wire hex_5_s1_agent_rf_source_endofpacket; // hex_5_s1_agent:rf_source_endofpacket -> hex_5_s1_agent_rsp_fifo:in_endofpacket
wire hex_5_s1_agent_rsp_fifo_out_valid; // hex_5_s1_agent_rsp_fifo:out_valid -> hex_5_s1_agent:rf_sink_valid
wire [99:0] hex_5_s1_agent_rsp_fifo_out_data; // hex_5_s1_agent_rsp_fifo:out_data -> hex_5_s1_agent:rf_sink_data
wire hex_5_s1_agent_rsp_fifo_out_ready; // hex_5_s1_agent:rf_sink_ready -> hex_5_s1_agent_rsp_fifo:out_ready
wire hex_5_s1_agent_rsp_fifo_out_startofpacket; // hex_5_s1_agent_rsp_fifo:out_startofpacket -> hex_5_s1_agent:rf_sink_startofpacket
wire hex_5_s1_agent_rsp_fifo_out_endofpacket; // hex_5_s1_agent_rsp_fifo:out_endofpacket -> hex_5_s1_agent:rf_sink_endofpacket
wire hex_5_s1_agent_rdata_fifo_src_valid; // hex_5_s1_agent:rdata_fifo_src_valid -> hex_5_s1_agent:rdata_fifo_sink_valid
wire [33:0] hex_5_s1_agent_rdata_fifo_src_data; // hex_5_s1_agent:rdata_fifo_src_data -> hex_5_s1_agent:rdata_fifo_sink_data
wire hex_5_s1_agent_rdata_fifo_src_ready; // hex_5_s1_agent:rdata_fifo_sink_ready -> hex_5_s1_agent:rdata_fifo_src_ready
wire cmd_mux_022_src_valid; // cmd_mux_022:src_valid -> hex_5_s1_agent:cp_valid
wire [98:0] cmd_mux_022_src_data; // cmd_mux_022:src_data -> hex_5_s1_agent:cp_data
wire cmd_mux_022_src_ready; // hex_5_s1_agent:cp_ready -> cmd_mux_022:src_ready
wire [31:0] cmd_mux_022_src_channel; // cmd_mux_022:src_channel -> hex_5_s1_agent:cp_channel
wire cmd_mux_022_src_startofpacket; // cmd_mux_022:src_startofpacket -> hex_5_s1_agent:cp_startofpacket
wire cmd_mux_022_src_endofpacket; // cmd_mux_022:src_endofpacket -> hex_5_s1_agent:cp_endofpacket
wire [31:0] alu_a_s1_agent_m0_readdata; // alu_a_s1_translator:uav_readdata -> alu_a_s1_agent:m0_readdata
wire alu_a_s1_agent_m0_waitrequest; // alu_a_s1_translator:uav_waitrequest -> alu_a_s1_agent:m0_waitrequest
wire alu_a_s1_agent_m0_debugaccess; // alu_a_s1_agent:m0_debugaccess -> alu_a_s1_translator:uav_debugaccess
wire [18:0] alu_a_s1_agent_m0_address; // alu_a_s1_agent:m0_address -> alu_a_s1_translator:uav_address
wire [3:0] alu_a_s1_agent_m0_byteenable; // alu_a_s1_agent:m0_byteenable -> alu_a_s1_translator:uav_byteenable
wire alu_a_s1_agent_m0_read; // alu_a_s1_agent:m0_read -> alu_a_s1_translator:uav_read
wire alu_a_s1_agent_m0_readdatavalid; // alu_a_s1_translator:uav_readdatavalid -> alu_a_s1_agent:m0_readdatavalid
wire alu_a_s1_agent_m0_lock; // alu_a_s1_agent:m0_lock -> alu_a_s1_translator:uav_lock
wire [31:0] alu_a_s1_agent_m0_writedata; // alu_a_s1_agent:m0_writedata -> alu_a_s1_translator:uav_writedata
wire alu_a_s1_agent_m0_write; // alu_a_s1_agent:m0_write -> alu_a_s1_translator:uav_write
wire [2:0] alu_a_s1_agent_m0_burstcount; // alu_a_s1_agent:m0_burstcount -> alu_a_s1_translator:uav_burstcount
wire alu_a_s1_agent_rf_source_valid; // alu_a_s1_agent:rf_source_valid -> alu_a_s1_agent_rsp_fifo:in_valid
wire [99:0] alu_a_s1_agent_rf_source_data; // alu_a_s1_agent:rf_source_data -> alu_a_s1_agent_rsp_fifo:in_data
wire alu_a_s1_agent_rf_source_ready; // alu_a_s1_agent_rsp_fifo:in_ready -> alu_a_s1_agent:rf_source_ready
wire alu_a_s1_agent_rf_source_startofpacket; // alu_a_s1_agent:rf_source_startofpacket -> alu_a_s1_agent_rsp_fifo:in_startofpacket
wire alu_a_s1_agent_rf_source_endofpacket; // alu_a_s1_agent:rf_source_endofpacket -> alu_a_s1_agent_rsp_fifo:in_endofpacket
wire alu_a_s1_agent_rsp_fifo_out_valid; // alu_a_s1_agent_rsp_fifo:out_valid -> alu_a_s1_agent:rf_sink_valid
wire [99:0] alu_a_s1_agent_rsp_fifo_out_data; // alu_a_s1_agent_rsp_fifo:out_data -> alu_a_s1_agent:rf_sink_data
wire alu_a_s1_agent_rsp_fifo_out_ready; // alu_a_s1_agent:rf_sink_ready -> alu_a_s1_agent_rsp_fifo:out_ready
wire alu_a_s1_agent_rsp_fifo_out_startofpacket; // alu_a_s1_agent_rsp_fifo:out_startofpacket -> alu_a_s1_agent:rf_sink_startofpacket
wire alu_a_s1_agent_rsp_fifo_out_endofpacket; // alu_a_s1_agent_rsp_fifo:out_endofpacket -> alu_a_s1_agent:rf_sink_endofpacket
wire alu_a_s1_agent_rdata_fifo_src_valid; // alu_a_s1_agent:rdata_fifo_src_valid -> alu_a_s1_agent:rdata_fifo_sink_valid
wire [33:0] alu_a_s1_agent_rdata_fifo_src_data; // alu_a_s1_agent:rdata_fifo_src_data -> alu_a_s1_agent:rdata_fifo_sink_data
wire alu_a_s1_agent_rdata_fifo_src_ready; // alu_a_s1_agent:rdata_fifo_sink_ready -> alu_a_s1_agent:rdata_fifo_src_ready
wire cmd_mux_023_src_valid; // cmd_mux_023:src_valid -> alu_a_s1_agent:cp_valid
wire [98:0] cmd_mux_023_src_data; // cmd_mux_023:src_data -> alu_a_s1_agent:cp_data
wire cmd_mux_023_src_ready; // alu_a_s1_agent:cp_ready -> cmd_mux_023:src_ready
wire [31:0] cmd_mux_023_src_channel; // cmd_mux_023:src_channel -> alu_a_s1_agent:cp_channel
wire cmd_mux_023_src_startofpacket; // cmd_mux_023:src_startofpacket -> alu_a_s1_agent:cp_startofpacket
wire cmd_mux_023_src_endofpacket; // cmd_mux_023:src_endofpacket -> alu_a_s1_agent:cp_endofpacket
wire [31:0] alu_b_s1_agent_m0_readdata; // alu_b_s1_translator:uav_readdata -> alu_b_s1_agent:m0_readdata
wire alu_b_s1_agent_m0_waitrequest; // alu_b_s1_translator:uav_waitrequest -> alu_b_s1_agent:m0_waitrequest
wire alu_b_s1_agent_m0_debugaccess; // alu_b_s1_agent:m0_debugaccess -> alu_b_s1_translator:uav_debugaccess
wire [18:0] alu_b_s1_agent_m0_address; // alu_b_s1_agent:m0_address -> alu_b_s1_translator:uav_address
wire [3:0] alu_b_s1_agent_m0_byteenable; // alu_b_s1_agent:m0_byteenable -> alu_b_s1_translator:uav_byteenable
wire alu_b_s1_agent_m0_read; // alu_b_s1_agent:m0_read -> alu_b_s1_translator:uav_read
wire alu_b_s1_agent_m0_readdatavalid; // alu_b_s1_translator:uav_readdatavalid -> alu_b_s1_agent:m0_readdatavalid
wire alu_b_s1_agent_m0_lock; // alu_b_s1_agent:m0_lock -> alu_b_s1_translator:uav_lock
wire [31:0] alu_b_s1_agent_m0_writedata; // alu_b_s1_agent:m0_writedata -> alu_b_s1_translator:uav_writedata
wire alu_b_s1_agent_m0_write; // alu_b_s1_agent:m0_write -> alu_b_s1_translator:uav_write
wire [2:0] alu_b_s1_agent_m0_burstcount; // alu_b_s1_agent:m0_burstcount -> alu_b_s1_translator:uav_burstcount
wire alu_b_s1_agent_rf_source_valid; // alu_b_s1_agent:rf_source_valid -> alu_b_s1_agent_rsp_fifo:in_valid
wire [99:0] alu_b_s1_agent_rf_source_data; // alu_b_s1_agent:rf_source_data -> alu_b_s1_agent_rsp_fifo:in_data
wire alu_b_s1_agent_rf_source_ready; // alu_b_s1_agent_rsp_fifo:in_ready -> alu_b_s1_agent:rf_source_ready
wire alu_b_s1_agent_rf_source_startofpacket; // alu_b_s1_agent:rf_source_startofpacket -> alu_b_s1_agent_rsp_fifo:in_startofpacket
wire alu_b_s1_agent_rf_source_endofpacket; // alu_b_s1_agent:rf_source_endofpacket -> alu_b_s1_agent_rsp_fifo:in_endofpacket
wire alu_b_s1_agent_rsp_fifo_out_valid; // alu_b_s1_agent_rsp_fifo:out_valid -> alu_b_s1_agent:rf_sink_valid
wire [99:0] alu_b_s1_agent_rsp_fifo_out_data; // alu_b_s1_agent_rsp_fifo:out_data -> alu_b_s1_agent:rf_sink_data
wire alu_b_s1_agent_rsp_fifo_out_ready; // alu_b_s1_agent:rf_sink_ready -> alu_b_s1_agent_rsp_fifo:out_ready
wire alu_b_s1_agent_rsp_fifo_out_startofpacket; // alu_b_s1_agent_rsp_fifo:out_startofpacket -> alu_b_s1_agent:rf_sink_startofpacket
wire alu_b_s1_agent_rsp_fifo_out_endofpacket; // alu_b_s1_agent_rsp_fifo:out_endofpacket -> alu_b_s1_agent:rf_sink_endofpacket
wire alu_b_s1_agent_rdata_fifo_src_valid; // alu_b_s1_agent:rdata_fifo_src_valid -> alu_b_s1_agent:rdata_fifo_sink_valid
wire [33:0] alu_b_s1_agent_rdata_fifo_src_data; // alu_b_s1_agent:rdata_fifo_src_data -> alu_b_s1_agent:rdata_fifo_sink_data
wire alu_b_s1_agent_rdata_fifo_src_ready; // alu_b_s1_agent:rdata_fifo_sink_ready -> alu_b_s1_agent:rdata_fifo_src_ready
wire cmd_mux_024_src_valid; // cmd_mux_024:src_valid -> alu_b_s1_agent:cp_valid
wire [98:0] cmd_mux_024_src_data; // cmd_mux_024:src_data -> alu_b_s1_agent:cp_data
wire cmd_mux_024_src_ready; // alu_b_s1_agent:cp_ready -> cmd_mux_024:src_ready
wire [31:0] cmd_mux_024_src_channel; // cmd_mux_024:src_channel -> alu_b_s1_agent:cp_channel
wire cmd_mux_024_src_startofpacket; // cmd_mux_024:src_startofpacket -> alu_b_s1_agent:cp_startofpacket
wire cmd_mux_024_src_endofpacket; // cmd_mux_024:src_endofpacket -> alu_b_s1_agent:cp_endofpacket
wire [31:0] alu_control_s1_agent_m0_readdata; // alu_control_s1_translator:uav_readdata -> alu_control_s1_agent:m0_readdata
wire alu_control_s1_agent_m0_waitrequest; // alu_control_s1_translator:uav_waitrequest -> alu_control_s1_agent:m0_waitrequest
wire alu_control_s1_agent_m0_debugaccess; // alu_control_s1_agent:m0_debugaccess -> alu_control_s1_translator:uav_debugaccess
wire [18:0] alu_control_s1_agent_m0_address; // alu_control_s1_agent:m0_address -> alu_control_s1_translator:uav_address
wire [3:0] alu_control_s1_agent_m0_byteenable; // alu_control_s1_agent:m0_byteenable -> alu_control_s1_translator:uav_byteenable
wire alu_control_s1_agent_m0_read; // alu_control_s1_agent:m0_read -> alu_control_s1_translator:uav_read
wire alu_control_s1_agent_m0_readdatavalid; // alu_control_s1_translator:uav_readdatavalid -> alu_control_s1_agent:m0_readdatavalid
wire alu_control_s1_agent_m0_lock; // alu_control_s1_agent:m0_lock -> alu_control_s1_translator:uav_lock
wire [31:0] alu_control_s1_agent_m0_writedata; // alu_control_s1_agent:m0_writedata -> alu_control_s1_translator:uav_writedata
wire alu_control_s1_agent_m0_write; // alu_control_s1_agent:m0_write -> alu_control_s1_translator:uav_write
wire [2:0] alu_control_s1_agent_m0_burstcount; // alu_control_s1_agent:m0_burstcount -> alu_control_s1_translator:uav_burstcount
wire alu_control_s1_agent_rf_source_valid; // alu_control_s1_agent:rf_source_valid -> alu_control_s1_agent_rsp_fifo:in_valid
wire [99:0] alu_control_s1_agent_rf_source_data; // alu_control_s1_agent:rf_source_data -> alu_control_s1_agent_rsp_fifo:in_data
wire alu_control_s1_agent_rf_source_ready; // alu_control_s1_agent_rsp_fifo:in_ready -> alu_control_s1_agent:rf_source_ready
wire alu_control_s1_agent_rf_source_startofpacket; // alu_control_s1_agent:rf_source_startofpacket -> alu_control_s1_agent_rsp_fifo:in_startofpacket
wire alu_control_s1_agent_rf_source_endofpacket; // alu_control_s1_agent:rf_source_endofpacket -> alu_control_s1_agent_rsp_fifo:in_endofpacket
wire alu_control_s1_agent_rsp_fifo_out_valid; // alu_control_s1_agent_rsp_fifo:out_valid -> alu_control_s1_agent:rf_sink_valid
wire [99:0] alu_control_s1_agent_rsp_fifo_out_data; // alu_control_s1_agent_rsp_fifo:out_data -> alu_control_s1_agent:rf_sink_data
wire alu_control_s1_agent_rsp_fifo_out_ready; // alu_control_s1_agent:rf_sink_ready -> alu_control_s1_agent_rsp_fifo:out_ready
wire alu_control_s1_agent_rsp_fifo_out_startofpacket; // alu_control_s1_agent_rsp_fifo:out_startofpacket -> alu_control_s1_agent:rf_sink_startofpacket
wire alu_control_s1_agent_rsp_fifo_out_endofpacket; // alu_control_s1_agent_rsp_fifo:out_endofpacket -> alu_control_s1_agent:rf_sink_endofpacket
wire alu_control_s1_agent_rdata_fifo_src_valid; // alu_control_s1_agent:rdata_fifo_src_valid -> alu_control_s1_agent:rdata_fifo_sink_valid
wire [33:0] alu_control_s1_agent_rdata_fifo_src_data; // alu_control_s1_agent:rdata_fifo_src_data -> alu_control_s1_agent:rdata_fifo_sink_data
wire alu_control_s1_agent_rdata_fifo_src_ready; // alu_control_s1_agent:rdata_fifo_sink_ready -> alu_control_s1_agent:rdata_fifo_src_ready
wire cmd_mux_025_src_valid; // cmd_mux_025:src_valid -> alu_control_s1_agent:cp_valid
wire [98:0] cmd_mux_025_src_data; // cmd_mux_025:src_data -> alu_control_s1_agent:cp_data
wire cmd_mux_025_src_ready; // alu_control_s1_agent:cp_ready -> cmd_mux_025:src_ready
wire [31:0] cmd_mux_025_src_channel; // cmd_mux_025:src_channel -> alu_control_s1_agent:cp_channel
wire cmd_mux_025_src_startofpacket; // cmd_mux_025:src_startofpacket -> alu_control_s1_agent:cp_startofpacket
wire cmd_mux_025_src_endofpacket; // cmd_mux_025:src_endofpacket -> alu_control_s1_agent:cp_endofpacket
wire [31:0] alu_out_s1_agent_m0_readdata; // alu_out_s1_translator:uav_readdata -> alu_out_s1_agent:m0_readdata
wire alu_out_s1_agent_m0_waitrequest; // alu_out_s1_translator:uav_waitrequest -> alu_out_s1_agent:m0_waitrequest
wire alu_out_s1_agent_m0_debugaccess; // alu_out_s1_agent:m0_debugaccess -> alu_out_s1_translator:uav_debugaccess
wire [18:0] alu_out_s1_agent_m0_address; // alu_out_s1_agent:m0_address -> alu_out_s1_translator:uav_address
wire [3:0] alu_out_s1_agent_m0_byteenable; // alu_out_s1_agent:m0_byteenable -> alu_out_s1_translator:uav_byteenable
wire alu_out_s1_agent_m0_read; // alu_out_s1_agent:m0_read -> alu_out_s1_translator:uav_read
wire alu_out_s1_agent_m0_readdatavalid; // alu_out_s1_translator:uav_readdatavalid -> alu_out_s1_agent:m0_readdatavalid
wire alu_out_s1_agent_m0_lock; // alu_out_s1_agent:m0_lock -> alu_out_s1_translator:uav_lock
wire [31:0] alu_out_s1_agent_m0_writedata; // alu_out_s1_agent:m0_writedata -> alu_out_s1_translator:uav_writedata
wire alu_out_s1_agent_m0_write; // alu_out_s1_agent:m0_write -> alu_out_s1_translator:uav_write
wire [2:0] alu_out_s1_agent_m0_burstcount; // alu_out_s1_agent:m0_burstcount -> alu_out_s1_translator:uav_burstcount
wire alu_out_s1_agent_rf_source_valid; // alu_out_s1_agent:rf_source_valid -> alu_out_s1_agent_rsp_fifo:in_valid
wire [99:0] alu_out_s1_agent_rf_source_data; // alu_out_s1_agent:rf_source_data -> alu_out_s1_agent_rsp_fifo:in_data
wire alu_out_s1_agent_rf_source_ready; // alu_out_s1_agent_rsp_fifo:in_ready -> alu_out_s1_agent:rf_source_ready
wire alu_out_s1_agent_rf_source_startofpacket; // alu_out_s1_agent:rf_source_startofpacket -> alu_out_s1_agent_rsp_fifo:in_startofpacket
wire alu_out_s1_agent_rf_source_endofpacket; // alu_out_s1_agent:rf_source_endofpacket -> alu_out_s1_agent_rsp_fifo:in_endofpacket
wire alu_out_s1_agent_rsp_fifo_out_valid; // alu_out_s1_agent_rsp_fifo:out_valid -> alu_out_s1_agent:rf_sink_valid
wire [99:0] alu_out_s1_agent_rsp_fifo_out_data; // alu_out_s1_agent_rsp_fifo:out_data -> alu_out_s1_agent:rf_sink_data
wire alu_out_s1_agent_rsp_fifo_out_ready; // alu_out_s1_agent:rf_sink_ready -> alu_out_s1_agent_rsp_fifo:out_ready
wire alu_out_s1_agent_rsp_fifo_out_startofpacket; // alu_out_s1_agent_rsp_fifo:out_startofpacket -> alu_out_s1_agent:rf_sink_startofpacket
wire alu_out_s1_agent_rsp_fifo_out_endofpacket; // alu_out_s1_agent_rsp_fifo:out_endofpacket -> alu_out_s1_agent:rf_sink_endofpacket
wire alu_out_s1_agent_rdata_fifo_src_valid; // alu_out_s1_agent:rdata_fifo_src_valid -> alu_out_s1_agent:rdata_fifo_sink_valid
wire [33:0] alu_out_s1_agent_rdata_fifo_src_data; // alu_out_s1_agent:rdata_fifo_src_data -> alu_out_s1_agent:rdata_fifo_sink_data
wire alu_out_s1_agent_rdata_fifo_src_ready; // alu_out_s1_agent:rdata_fifo_sink_ready -> alu_out_s1_agent:rdata_fifo_src_ready
wire cmd_mux_026_src_valid; // cmd_mux_026:src_valid -> alu_out_s1_agent:cp_valid
wire [98:0] cmd_mux_026_src_data; // cmd_mux_026:src_data -> alu_out_s1_agent:cp_data
wire cmd_mux_026_src_ready; // alu_out_s1_agent:cp_ready -> cmd_mux_026:src_ready
wire [31:0] cmd_mux_026_src_channel; // cmd_mux_026:src_channel -> alu_out_s1_agent:cp_channel
wire cmd_mux_026_src_startofpacket; // cmd_mux_026:src_startofpacket -> alu_out_s1_agent:cp_startofpacket
wire cmd_mux_026_src_endofpacket; // cmd_mux_026:src_endofpacket -> alu_out_s1_agent:cp_endofpacket
wire [31:0] alu_zero_s1_agent_m0_readdata; // alu_zero_s1_translator:uav_readdata -> alu_zero_s1_agent:m0_readdata
wire alu_zero_s1_agent_m0_waitrequest; // alu_zero_s1_translator:uav_waitrequest -> alu_zero_s1_agent:m0_waitrequest
wire alu_zero_s1_agent_m0_debugaccess; // alu_zero_s1_agent:m0_debugaccess -> alu_zero_s1_translator:uav_debugaccess
wire [18:0] alu_zero_s1_agent_m0_address; // alu_zero_s1_agent:m0_address -> alu_zero_s1_translator:uav_address
wire [3:0] alu_zero_s1_agent_m0_byteenable; // alu_zero_s1_agent:m0_byteenable -> alu_zero_s1_translator:uav_byteenable
wire alu_zero_s1_agent_m0_read; // alu_zero_s1_agent:m0_read -> alu_zero_s1_translator:uav_read
wire alu_zero_s1_agent_m0_readdatavalid; // alu_zero_s1_translator:uav_readdatavalid -> alu_zero_s1_agent:m0_readdatavalid
wire alu_zero_s1_agent_m0_lock; // alu_zero_s1_agent:m0_lock -> alu_zero_s1_translator:uav_lock
wire [31:0] alu_zero_s1_agent_m0_writedata; // alu_zero_s1_agent:m0_writedata -> alu_zero_s1_translator:uav_writedata
wire alu_zero_s1_agent_m0_write; // alu_zero_s1_agent:m0_write -> alu_zero_s1_translator:uav_write
wire [2:0] alu_zero_s1_agent_m0_burstcount; // alu_zero_s1_agent:m0_burstcount -> alu_zero_s1_translator:uav_burstcount
wire alu_zero_s1_agent_rf_source_valid; // alu_zero_s1_agent:rf_source_valid -> alu_zero_s1_agent_rsp_fifo:in_valid
wire [99:0] alu_zero_s1_agent_rf_source_data; // alu_zero_s1_agent:rf_source_data -> alu_zero_s1_agent_rsp_fifo:in_data
wire alu_zero_s1_agent_rf_source_ready; // alu_zero_s1_agent_rsp_fifo:in_ready -> alu_zero_s1_agent:rf_source_ready
wire alu_zero_s1_agent_rf_source_startofpacket; // alu_zero_s1_agent:rf_source_startofpacket -> alu_zero_s1_agent_rsp_fifo:in_startofpacket
wire alu_zero_s1_agent_rf_source_endofpacket; // alu_zero_s1_agent:rf_source_endofpacket -> alu_zero_s1_agent_rsp_fifo:in_endofpacket
wire alu_zero_s1_agent_rsp_fifo_out_valid; // alu_zero_s1_agent_rsp_fifo:out_valid -> alu_zero_s1_agent:rf_sink_valid
wire [99:0] alu_zero_s1_agent_rsp_fifo_out_data; // alu_zero_s1_agent_rsp_fifo:out_data -> alu_zero_s1_agent:rf_sink_data
wire alu_zero_s1_agent_rsp_fifo_out_ready; // alu_zero_s1_agent:rf_sink_ready -> alu_zero_s1_agent_rsp_fifo:out_ready
wire alu_zero_s1_agent_rsp_fifo_out_startofpacket; // alu_zero_s1_agent_rsp_fifo:out_startofpacket -> alu_zero_s1_agent:rf_sink_startofpacket
wire alu_zero_s1_agent_rsp_fifo_out_endofpacket; // alu_zero_s1_agent_rsp_fifo:out_endofpacket -> alu_zero_s1_agent:rf_sink_endofpacket
wire alu_zero_s1_agent_rdata_fifo_src_valid; // alu_zero_s1_agent:rdata_fifo_src_valid -> alu_zero_s1_agent:rdata_fifo_sink_valid
wire [33:0] alu_zero_s1_agent_rdata_fifo_src_data; // alu_zero_s1_agent:rdata_fifo_src_data -> alu_zero_s1_agent:rdata_fifo_sink_data
wire alu_zero_s1_agent_rdata_fifo_src_ready; // alu_zero_s1_agent:rdata_fifo_sink_ready -> alu_zero_s1_agent:rdata_fifo_src_ready
wire cmd_mux_027_src_valid; // cmd_mux_027:src_valid -> alu_zero_s1_agent:cp_valid
wire [98:0] cmd_mux_027_src_data; // cmd_mux_027:src_data -> alu_zero_s1_agent:cp_data
wire cmd_mux_027_src_ready; // alu_zero_s1_agent:cp_ready -> cmd_mux_027:src_ready
wire [31:0] cmd_mux_027_src_channel; // cmd_mux_027:src_channel -> alu_zero_s1_agent:cp_channel
wire cmd_mux_027_src_startofpacket; // cmd_mux_027:src_startofpacket -> alu_zero_s1_agent:cp_startofpacket
wire cmd_mux_027_src_endofpacket; // cmd_mux_027:src_endofpacket -> alu_zero_s1_agent:cp_endofpacket
wire [31:0] alu_overflow_s1_agent_m0_readdata; // alu_overflow_s1_translator:uav_readdata -> alu_overflow_s1_agent:m0_readdata
wire alu_overflow_s1_agent_m0_waitrequest; // alu_overflow_s1_translator:uav_waitrequest -> alu_overflow_s1_agent:m0_waitrequest
wire alu_overflow_s1_agent_m0_debugaccess; // alu_overflow_s1_agent:m0_debugaccess -> alu_overflow_s1_translator:uav_debugaccess
wire [18:0] alu_overflow_s1_agent_m0_address; // alu_overflow_s1_agent:m0_address -> alu_overflow_s1_translator:uav_address
wire [3:0] alu_overflow_s1_agent_m0_byteenable; // alu_overflow_s1_agent:m0_byteenable -> alu_overflow_s1_translator:uav_byteenable
wire alu_overflow_s1_agent_m0_read; // alu_overflow_s1_agent:m0_read -> alu_overflow_s1_translator:uav_read
wire alu_overflow_s1_agent_m0_readdatavalid; // alu_overflow_s1_translator:uav_readdatavalid -> alu_overflow_s1_agent:m0_readdatavalid
wire alu_overflow_s1_agent_m0_lock; // alu_overflow_s1_agent:m0_lock -> alu_overflow_s1_translator:uav_lock
wire [31:0] alu_overflow_s1_agent_m0_writedata; // alu_overflow_s1_agent:m0_writedata -> alu_overflow_s1_translator:uav_writedata
wire alu_overflow_s1_agent_m0_write; // alu_overflow_s1_agent:m0_write -> alu_overflow_s1_translator:uav_write
wire [2:0] alu_overflow_s1_agent_m0_burstcount; // alu_overflow_s1_agent:m0_burstcount -> alu_overflow_s1_translator:uav_burstcount
wire alu_overflow_s1_agent_rf_source_valid; // alu_overflow_s1_agent:rf_source_valid -> alu_overflow_s1_agent_rsp_fifo:in_valid
wire [99:0] alu_overflow_s1_agent_rf_source_data; // alu_overflow_s1_agent:rf_source_data -> alu_overflow_s1_agent_rsp_fifo:in_data
wire alu_overflow_s1_agent_rf_source_ready; // alu_overflow_s1_agent_rsp_fifo:in_ready -> alu_overflow_s1_agent:rf_source_ready
wire alu_overflow_s1_agent_rf_source_startofpacket; // alu_overflow_s1_agent:rf_source_startofpacket -> alu_overflow_s1_agent_rsp_fifo:in_startofpacket
wire alu_overflow_s1_agent_rf_source_endofpacket; // alu_overflow_s1_agent:rf_source_endofpacket -> alu_overflow_s1_agent_rsp_fifo:in_endofpacket
wire alu_overflow_s1_agent_rsp_fifo_out_valid; // alu_overflow_s1_agent_rsp_fifo:out_valid -> alu_overflow_s1_agent:rf_sink_valid
wire [99:0] alu_overflow_s1_agent_rsp_fifo_out_data; // alu_overflow_s1_agent_rsp_fifo:out_data -> alu_overflow_s1_agent:rf_sink_data
wire alu_overflow_s1_agent_rsp_fifo_out_ready; // alu_overflow_s1_agent:rf_sink_ready -> alu_overflow_s1_agent_rsp_fifo:out_ready
wire alu_overflow_s1_agent_rsp_fifo_out_startofpacket; // alu_overflow_s1_agent_rsp_fifo:out_startofpacket -> alu_overflow_s1_agent:rf_sink_startofpacket
wire alu_overflow_s1_agent_rsp_fifo_out_endofpacket; // alu_overflow_s1_agent_rsp_fifo:out_endofpacket -> alu_overflow_s1_agent:rf_sink_endofpacket
wire alu_overflow_s1_agent_rdata_fifo_src_valid; // alu_overflow_s1_agent:rdata_fifo_src_valid -> alu_overflow_s1_agent:rdata_fifo_sink_valid
wire [33:0] alu_overflow_s1_agent_rdata_fifo_src_data; // alu_overflow_s1_agent:rdata_fifo_src_data -> alu_overflow_s1_agent:rdata_fifo_sink_data
wire alu_overflow_s1_agent_rdata_fifo_src_ready; // alu_overflow_s1_agent:rdata_fifo_sink_ready -> alu_overflow_s1_agent:rdata_fifo_src_ready
wire cmd_mux_028_src_valid; // cmd_mux_028:src_valid -> alu_overflow_s1_agent:cp_valid
wire [98:0] cmd_mux_028_src_data; // cmd_mux_028:src_data -> alu_overflow_s1_agent:cp_data
wire cmd_mux_028_src_ready; // alu_overflow_s1_agent:cp_ready -> cmd_mux_028:src_ready
wire [31:0] cmd_mux_028_src_channel; // cmd_mux_028:src_channel -> alu_overflow_s1_agent:cp_channel
wire cmd_mux_028_src_startofpacket; // cmd_mux_028:src_startofpacket -> alu_overflow_s1_agent:cp_startofpacket
wire cmd_mux_028_src_endofpacket; // cmd_mux_028:src_endofpacket -> alu_overflow_s1_agent:cp_endofpacket
wire [31:0] alu_carry_out_s1_agent_m0_readdata; // alu_carry_out_s1_translator:uav_readdata -> alu_carry_out_s1_agent:m0_readdata
wire alu_carry_out_s1_agent_m0_waitrequest; // alu_carry_out_s1_translator:uav_waitrequest -> alu_carry_out_s1_agent:m0_waitrequest
wire alu_carry_out_s1_agent_m0_debugaccess; // alu_carry_out_s1_agent:m0_debugaccess -> alu_carry_out_s1_translator:uav_debugaccess
wire [18:0] alu_carry_out_s1_agent_m0_address; // alu_carry_out_s1_agent:m0_address -> alu_carry_out_s1_translator:uav_address
wire [3:0] alu_carry_out_s1_agent_m0_byteenable; // alu_carry_out_s1_agent:m0_byteenable -> alu_carry_out_s1_translator:uav_byteenable
wire alu_carry_out_s1_agent_m0_read; // alu_carry_out_s1_agent:m0_read -> alu_carry_out_s1_translator:uav_read
wire alu_carry_out_s1_agent_m0_readdatavalid; // alu_carry_out_s1_translator:uav_readdatavalid -> alu_carry_out_s1_agent:m0_readdatavalid
wire alu_carry_out_s1_agent_m0_lock; // alu_carry_out_s1_agent:m0_lock -> alu_carry_out_s1_translator:uav_lock
wire [31:0] alu_carry_out_s1_agent_m0_writedata; // alu_carry_out_s1_agent:m0_writedata -> alu_carry_out_s1_translator:uav_writedata
wire alu_carry_out_s1_agent_m0_write; // alu_carry_out_s1_agent:m0_write -> alu_carry_out_s1_translator:uav_write
wire [2:0] alu_carry_out_s1_agent_m0_burstcount; // alu_carry_out_s1_agent:m0_burstcount -> alu_carry_out_s1_translator:uav_burstcount
wire alu_carry_out_s1_agent_rf_source_valid; // alu_carry_out_s1_agent:rf_source_valid -> alu_carry_out_s1_agent_rsp_fifo:in_valid
wire [99:0] alu_carry_out_s1_agent_rf_source_data; // alu_carry_out_s1_agent:rf_source_data -> alu_carry_out_s1_agent_rsp_fifo:in_data
wire alu_carry_out_s1_agent_rf_source_ready; // alu_carry_out_s1_agent_rsp_fifo:in_ready -> alu_carry_out_s1_agent:rf_source_ready
wire alu_carry_out_s1_agent_rf_source_startofpacket; // alu_carry_out_s1_agent:rf_source_startofpacket -> alu_carry_out_s1_agent_rsp_fifo:in_startofpacket
wire alu_carry_out_s1_agent_rf_source_endofpacket; // alu_carry_out_s1_agent:rf_source_endofpacket -> alu_carry_out_s1_agent_rsp_fifo:in_endofpacket
wire alu_carry_out_s1_agent_rsp_fifo_out_valid; // alu_carry_out_s1_agent_rsp_fifo:out_valid -> alu_carry_out_s1_agent:rf_sink_valid
wire [99:0] alu_carry_out_s1_agent_rsp_fifo_out_data; // alu_carry_out_s1_agent_rsp_fifo:out_data -> alu_carry_out_s1_agent:rf_sink_data
wire alu_carry_out_s1_agent_rsp_fifo_out_ready; // alu_carry_out_s1_agent:rf_sink_ready -> alu_carry_out_s1_agent_rsp_fifo:out_ready
wire alu_carry_out_s1_agent_rsp_fifo_out_startofpacket; // alu_carry_out_s1_agent_rsp_fifo:out_startofpacket -> alu_carry_out_s1_agent:rf_sink_startofpacket
wire alu_carry_out_s1_agent_rsp_fifo_out_endofpacket; // alu_carry_out_s1_agent_rsp_fifo:out_endofpacket -> alu_carry_out_s1_agent:rf_sink_endofpacket
wire alu_carry_out_s1_agent_rdata_fifo_src_valid; // alu_carry_out_s1_agent:rdata_fifo_src_valid -> alu_carry_out_s1_agent:rdata_fifo_sink_valid
wire [33:0] alu_carry_out_s1_agent_rdata_fifo_src_data; // alu_carry_out_s1_agent:rdata_fifo_src_data -> alu_carry_out_s1_agent:rdata_fifo_sink_data
wire alu_carry_out_s1_agent_rdata_fifo_src_ready; // alu_carry_out_s1_agent:rdata_fifo_sink_ready -> alu_carry_out_s1_agent:rdata_fifo_src_ready
wire cmd_mux_029_src_valid; // cmd_mux_029:src_valid -> alu_carry_out_s1_agent:cp_valid
wire [98:0] cmd_mux_029_src_data; // cmd_mux_029:src_data -> alu_carry_out_s1_agent:cp_data
wire cmd_mux_029_src_ready; // alu_carry_out_s1_agent:cp_ready -> cmd_mux_029:src_ready
wire [31:0] cmd_mux_029_src_channel; // cmd_mux_029:src_channel -> alu_carry_out_s1_agent:cp_channel
wire cmd_mux_029_src_startofpacket; // cmd_mux_029:src_startofpacket -> alu_carry_out_s1_agent:cp_startofpacket
wire cmd_mux_029_src_endofpacket; // cmd_mux_029:src_endofpacket -> alu_carry_out_s1_agent:cp_endofpacket
wire [31:0] alu_negative_s1_agent_m0_readdata; // alu_negative_s1_translator:uav_readdata -> alu_negative_s1_agent:m0_readdata
wire alu_negative_s1_agent_m0_waitrequest; // alu_negative_s1_translator:uav_waitrequest -> alu_negative_s1_agent:m0_waitrequest
wire alu_negative_s1_agent_m0_debugaccess; // alu_negative_s1_agent:m0_debugaccess -> alu_negative_s1_translator:uav_debugaccess
wire [18:0] alu_negative_s1_agent_m0_address; // alu_negative_s1_agent:m0_address -> alu_negative_s1_translator:uav_address
wire [3:0] alu_negative_s1_agent_m0_byteenable; // alu_negative_s1_agent:m0_byteenable -> alu_negative_s1_translator:uav_byteenable
wire alu_negative_s1_agent_m0_read; // alu_negative_s1_agent:m0_read -> alu_negative_s1_translator:uav_read
wire alu_negative_s1_agent_m0_readdatavalid; // alu_negative_s1_translator:uav_readdatavalid -> alu_negative_s1_agent:m0_readdatavalid
wire alu_negative_s1_agent_m0_lock; // alu_negative_s1_agent:m0_lock -> alu_negative_s1_translator:uav_lock
wire [31:0] alu_negative_s1_agent_m0_writedata; // alu_negative_s1_agent:m0_writedata -> alu_negative_s1_translator:uav_writedata
wire alu_negative_s1_agent_m0_write; // alu_negative_s1_agent:m0_write -> alu_negative_s1_translator:uav_write
wire [2:0] alu_negative_s1_agent_m0_burstcount; // alu_negative_s1_agent:m0_burstcount -> alu_negative_s1_translator:uav_burstcount
wire alu_negative_s1_agent_rf_source_valid; // alu_negative_s1_agent:rf_source_valid -> alu_negative_s1_agent_rsp_fifo:in_valid
wire [99:0] alu_negative_s1_agent_rf_source_data; // alu_negative_s1_agent:rf_source_data -> alu_negative_s1_agent_rsp_fifo:in_data
wire alu_negative_s1_agent_rf_source_ready; // alu_negative_s1_agent_rsp_fifo:in_ready -> alu_negative_s1_agent:rf_source_ready
wire alu_negative_s1_agent_rf_source_startofpacket; // alu_negative_s1_agent:rf_source_startofpacket -> alu_negative_s1_agent_rsp_fifo:in_startofpacket
wire alu_negative_s1_agent_rf_source_endofpacket; // alu_negative_s1_agent:rf_source_endofpacket -> alu_negative_s1_agent_rsp_fifo:in_endofpacket
wire alu_negative_s1_agent_rsp_fifo_out_valid; // alu_negative_s1_agent_rsp_fifo:out_valid -> alu_negative_s1_agent:rf_sink_valid
wire [99:0] alu_negative_s1_agent_rsp_fifo_out_data; // alu_negative_s1_agent_rsp_fifo:out_data -> alu_negative_s1_agent:rf_sink_data
wire alu_negative_s1_agent_rsp_fifo_out_ready; // alu_negative_s1_agent:rf_sink_ready -> alu_negative_s1_agent_rsp_fifo:out_ready
wire alu_negative_s1_agent_rsp_fifo_out_startofpacket; // alu_negative_s1_agent_rsp_fifo:out_startofpacket -> alu_negative_s1_agent:rf_sink_startofpacket
wire alu_negative_s1_agent_rsp_fifo_out_endofpacket; // alu_negative_s1_agent_rsp_fifo:out_endofpacket -> alu_negative_s1_agent:rf_sink_endofpacket
wire alu_negative_s1_agent_rdata_fifo_src_valid; // alu_negative_s1_agent:rdata_fifo_src_valid -> alu_negative_s1_agent:rdata_fifo_sink_valid
wire [33:0] alu_negative_s1_agent_rdata_fifo_src_data; // alu_negative_s1_agent:rdata_fifo_src_data -> alu_negative_s1_agent:rdata_fifo_sink_data
wire alu_negative_s1_agent_rdata_fifo_src_ready; // alu_negative_s1_agent:rdata_fifo_sink_ready -> alu_negative_s1_agent:rdata_fifo_src_ready
wire cmd_mux_030_src_valid; // cmd_mux_030:src_valid -> alu_negative_s1_agent:cp_valid
wire [98:0] cmd_mux_030_src_data; // cmd_mux_030:src_data -> alu_negative_s1_agent:cp_data
wire cmd_mux_030_src_ready; // alu_negative_s1_agent:cp_ready -> cmd_mux_030:src_ready
wire [31:0] cmd_mux_030_src_channel; // cmd_mux_030:src_channel -> alu_negative_s1_agent:cp_channel
wire cmd_mux_030_src_startofpacket; // cmd_mux_030:src_startofpacket -> alu_negative_s1_agent:cp_startofpacket
wire cmd_mux_030_src_endofpacket; // cmd_mux_030:src_endofpacket -> alu_negative_s1_agent:cp_endofpacket
wire [31:0] keys_s1_agent_m0_readdata; // keys_s1_translator:uav_readdata -> keys_s1_agent:m0_readdata
wire keys_s1_agent_m0_waitrequest; // keys_s1_translator:uav_waitrequest -> keys_s1_agent:m0_waitrequest
wire keys_s1_agent_m0_debugaccess; // keys_s1_agent:m0_debugaccess -> keys_s1_translator:uav_debugaccess
wire [18:0] keys_s1_agent_m0_address; // keys_s1_agent:m0_address -> keys_s1_translator:uav_address
wire [3:0] keys_s1_agent_m0_byteenable; // keys_s1_agent:m0_byteenable -> keys_s1_translator:uav_byteenable
wire keys_s1_agent_m0_read; // keys_s1_agent:m0_read -> keys_s1_translator:uav_read
wire keys_s1_agent_m0_readdatavalid; // keys_s1_translator:uav_readdatavalid -> keys_s1_agent:m0_readdatavalid
wire keys_s1_agent_m0_lock; // keys_s1_agent:m0_lock -> keys_s1_translator:uav_lock
wire [31:0] keys_s1_agent_m0_writedata; // keys_s1_agent:m0_writedata -> keys_s1_translator:uav_writedata
wire keys_s1_agent_m0_write; // keys_s1_agent:m0_write -> keys_s1_translator:uav_write
wire [2:0] keys_s1_agent_m0_burstcount; // keys_s1_agent:m0_burstcount -> keys_s1_translator:uav_burstcount
wire keys_s1_agent_rf_source_valid; // keys_s1_agent:rf_source_valid -> keys_s1_agent_rsp_fifo:in_valid
wire [99:0] keys_s1_agent_rf_source_data; // keys_s1_agent:rf_source_data -> keys_s1_agent_rsp_fifo:in_data
wire keys_s1_agent_rf_source_ready; // keys_s1_agent_rsp_fifo:in_ready -> keys_s1_agent:rf_source_ready
wire keys_s1_agent_rf_source_startofpacket; // keys_s1_agent:rf_source_startofpacket -> keys_s1_agent_rsp_fifo:in_startofpacket
wire keys_s1_agent_rf_source_endofpacket; // keys_s1_agent:rf_source_endofpacket -> keys_s1_agent_rsp_fifo:in_endofpacket
wire keys_s1_agent_rsp_fifo_out_valid; // keys_s1_agent_rsp_fifo:out_valid -> keys_s1_agent:rf_sink_valid
wire [99:0] keys_s1_agent_rsp_fifo_out_data; // keys_s1_agent_rsp_fifo:out_data -> keys_s1_agent:rf_sink_data
wire keys_s1_agent_rsp_fifo_out_ready; // keys_s1_agent:rf_sink_ready -> keys_s1_agent_rsp_fifo:out_ready
wire keys_s1_agent_rsp_fifo_out_startofpacket; // keys_s1_agent_rsp_fifo:out_startofpacket -> keys_s1_agent:rf_sink_startofpacket
wire keys_s1_agent_rsp_fifo_out_endofpacket; // keys_s1_agent_rsp_fifo:out_endofpacket -> keys_s1_agent:rf_sink_endofpacket
wire keys_s1_agent_rdata_fifo_src_valid; // keys_s1_agent:rdata_fifo_src_valid -> keys_s1_agent:rdata_fifo_sink_valid
wire [33:0] keys_s1_agent_rdata_fifo_src_data; // keys_s1_agent:rdata_fifo_src_data -> keys_s1_agent:rdata_fifo_sink_data
wire keys_s1_agent_rdata_fifo_src_ready; // keys_s1_agent:rdata_fifo_sink_ready -> keys_s1_agent:rdata_fifo_src_ready
wire cmd_mux_031_src_valid; // cmd_mux_031:src_valid -> keys_s1_agent:cp_valid
wire [98:0] cmd_mux_031_src_data; // cmd_mux_031:src_data -> keys_s1_agent:cp_data
wire cmd_mux_031_src_ready; // keys_s1_agent:cp_ready -> cmd_mux_031:src_ready
wire [31:0] cmd_mux_031_src_channel; // cmd_mux_031:src_channel -> keys_s1_agent:cp_channel
wire cmd_mux_031_src_startofpacket; // cmd_mux_031:src_startofpacket -> keys_s1_agent:cp_startofpacket
wire cmd_mux_031_src_endofpacket; // cmd_mux_031:src_endofpacket -> keys_s1_agent:cp_endofpacket
wire nios2_qsys_0_data_master_agent_cp_valid; // nios2_qsys_0_data_master_agent:cp_valid -> router:sink_valid
wire [98:0] nios2_qsys_0_data_master_agent_cp_data; // nios2_qsys_0_data_master_agent:cp_data -> router:sink_data
wire nios2_qsys_0_data_master_agent_cp_ready; // router:sink_ready -> nios2_qsys_0_data_master_agent:cp_ready
wire nios2_qsys_0_data_master_agent_cp_startofpacket; // nios2_qsys_0_data_master_agent:cp_startofpacket -> router:sink_startofpacket
wire nios2_qsys_0_data_master_agent_cp_endofpacket; // nios2_qsys_0_data_master_agent:cp_endofpacket -> router:sink_endofpacket
wire router_src_valid; // router:src_valid -> cmd_demux:sink_valid
wire [98:0] router_src_data; // router:src_data -> cmd_demux:sink_data
wire router_src_ready; // cmd_demux:sink_ready -> router:src_ready
wire [31:0] router_src_channel; // router:src_channel -> cmd_demux:sink_channel
wire router_src_startofpacket; // router:src_startofpacket -> cmd_demux:sink_startofpacket
wire router_src_endofpacket; // router:src_endofpacket -> cmd_demux:sink_endofpacket
wire nios2_qsys_0_instruction_master_agent_cp_valid; // nios2_qsys_0_instruction_master_agent:cp_valid -> router_001:sink_valid
wire [98:0] nios2_qsys_0_instruction_master_agent_cp_data; // nios2_qsys_0_instruction_master_agent:cp_data -> router_001:sink_data
wire nios2_qsys_0_instruction_master_agent_cp_ready; // router_001:sink_ready -> nios2_qsys_0_instruction_master_agent:cp_ready
wire nios2_qsys_0_instruction_master_agent_cp_startofpacket; // nios2_qsys_0_instruction_master_agent:cp_startofpacket -> router_001:sink_startofpacket
wire nios2_qsys_0_instruction_master_agent_cp_endofpacket; // nios2_qsys_0_instruction_master_agent:cp_endofpacket -> router_001:sink_endofpacket
wire router_001_src_valid; // router_001:src_valid -> cmd_demux_001:sink_valid
wire [98:0] router_001_src_data; // router_001:src_data -> cmd_demux_001:sink_data
wire router_001_src_ready; // cmd_demux_001:sink_ready -> router_001:src_ready
wire [31:0] router_001_src_channel; // router_001:src_channel -> cmd_demux_001:sink_channel
wire router_001_src_startofpacket; // router_001:src_startofpacket -> cmd_demux_001:sink_startofpacket
wire router_001_src_endofpacket; // router_001:src_endofpacket -> cmd_demux_001:sink_endofpacket
wire jtag_uart_0_avalon_jtag_slave_agent_rp_valid; // jtag_uart_0_avalon_jtag_slave_agent:rp_valid -> router_002:sink_valid
wire [98:0] jtag_uart_0_avalon_jtag_slave_agent_rp_data; // jtag_uart_0_avalon_jtag_slave_agent:rp_data -> router_002:sink_data
wire jtag_uart_0_avalon_jtag_slave_agent_rp_ready; // router_002:sink_ready -> jtag_uart_0_avalon_jtag_slave_agent:rp_ready
wire jtag_uart_0_avalon_jtag_slave_agent_rp_startofpacket; // jtag_uart_0_avalon_jtag_slave_agent:rp_startofpacket -> router_002:sink_startofpacket
wire jtag_uart_0_avalon_jtag_slave_agent_rp_endofpacket; // jtag_uart_0_avalon_jtag_slave_agent:rp_endofpacket -> router_002:sink_endofpacket
wire router_002_src_valid; // router_002:src_valid -> rsp_demux:sink_valid
wire [98:0] router_002_src_data; // router_002:src_data -> rsp_demux:sink_data
wire router_002_src_ready; // rsp_demux:sink_ready -> router_002:src_ready
wire [31:0] router_002_src_channel; // router_002:src_channel -> rsp_demux:sink_channel
wire router_002_src_startofpacket; // router_002:src_startofpacket -> rsp_demux:sink_startofpacket
wire router_002_src_endofpacket; // router_002:src_endofpacket -> rsp_demux:sink_endofpacket
wire nios2_qsys_0_debug_mem_slave_agent_rp_valid; // nios2_qsys_0_debug_mem_slave_agent:rp_valid -> router_003:sink_valid
wire [98:0] nios2_qsys_0_debug_mem_slave_agent_rp_data; // nios2_qsys_0_debug_mem_slave_agent:rp_data -> router_003:sink_data
wire nios2_qsys_0_debug_mem_slave_agent_rp_ready; // router_003:sink_ready -> nios2_qsys_0_debug_mem_slave_agent:rp_ready
wire nios2_qsys_0_debug_mem_slave_agent_rp_startofpacket; // nios2_qsys_0_debug_mem_slave_agent:rp_startofpacket -> router_003:sink_startofpacket
wire nios2_qsys_0_debug_mem_slave_agent_rp_endofpacket; // nios2_qsys_0_debug_mem_slave_agent:rp_endofpacket -> router_003:sink_endofpacket
wire router_003_src_valid; // router_003:src_valid -> rsp_demux_001:sink_valid
wire [98:0] router_003_src_data; // router_003:src_data -> rsp_demux_001:sink_data
wire router_003_src_ready; // rsp_demux_001:sink_ready -> router_003:src_ready
wire [31:0] router_003_src_channel; // router_003:src_channel -> rsp_demux_001:sink_channel
wire router_003_src_startofpacket; // router_003:src_startofpacket -> rsp_demux_001:sink_startofpacket
wire router_003_src_endofpacket; // router_003:src_endofpacket -> rsp_demux_001:sink_endofpacket
wire onchip_memory2_0_s1_agent_rp_valid; // onchip_memory2_0_s1_agent:rp_valid -> router_004:sink_valid
wire [98:0] onchip_memory2_0_s1_agent_rp_data; // onchip_memory2_0_s1_agent:rp_data -> router_004:sink_data
wire onchip_memory2_0_s1_agent_rp_ready; // router_004:sink_ready -> onchip_memory2_0_s1_agent:rp_ready
wire onchip_memory2_0_s1_agent_rp_startofpacket; // onchip_memory2_0_s1_agent:rp_startofpacket -> router_004:sink_startofpacket
wire onchip_memory2_0_s1_agent_rp_endofpacket; // onchip_memory2_0_s1_agent:rp_endofpacket -> router_004:sink_endofpacket
wire router_004_src_valid; // router_004:src_valid -> rsp_demux_002:sink_valid
wire [98:0] router_004_src_data; // router_004:src_data -> rsp_demux_002:sink_data
wire router_004_src_ready; // rsp_demux_002:sink_ready -> router_004:src_ready
wire [31:0] router_004_src_channel; // router_004:src_channel -> rsp_demux_002:sink_channel
wire router_004_src_startofpacket; // router_004:src_startofpacket -> rsp_demux_002:sink_startofpacket
wire router_004_src_endofpacket; // router_004:src_endofpacket -> rsp_demux_002:sink_endofpacket
wire leds_s1_agent_rp_valid; // LEDs_s1_agent:rp_valid -> router_005:sink_valid
wire [98:0] leds_s1_agent_rp_data; // LEDs_s1_agent:rp_data -> router_005:sink_data
wire leds_s1_agent_rp_ready; // router_005:sink_ready -> LEDs_s1_agent:rp_ready
wire leds_s1_agent_rp_startofpacket; // LEDs_s1_agent:rp_startofpacket -> router_005:sink_startofpacket
wire leds_s1_agent_rp_endofpacket; // LEDs_s1_agent:rp_endofpacket -> router_005:sink_endofpacket
wire router_005_src_valid; // router_005:src_valid -> rsp_demux_003:sink_valid
wire [98:0] router_005_src_data; // router_005:src_data -> rsp_demux_003:sink_data
wire router_005_src_ready; // rsp_demux_003:sink_ready -> router_005:src_ready
wire [31:0] router_005_src_channel; // router_005:src_channel -> rsp_demux_003:sink_channel
wire router_005_src_startofpacket; // router_005:src_startofpacket -> rsp_demux_003:sink_startofpacket
wire router_005_src_endofpacket; // router_005:src_endofpacket -> rsp_demux_003:sink_endofpacket
wire switches_s1_agent_rp_valid; // switches_s1_agent:rp_valid -> router_006:sink_valid
wire [98:0] switches_s1_agent_rp_data; // switches_s1_agent:rp_data -> router_006:sink_data
wire switches_s1_agent_rp_ready; // router_006:sink_ready -> switches_s1_agent:rp_ready
wire switches_s1_agent_rp_startofpacket; // switches_s1_agent:rp_startofpacket -> router_006:sink_startofpacket
wire switches_s1_agent_rp_endofpacket; // switches_s1_agent:rp_endofpacket -> router_006:sink_endofpacket
wire router_006_src_valid; // router_006:src_valid -> rsp_demux_004:sink_valid
wire [98:0] router_006_src_data; // router_006:src_data -> rsp_demux_004:sink_data
wire router_006_src_ready; // rsp_demux_004:sink_ready -> router_006:src_ready
wire [31:0] router_006_src_channel; // router_006:src_channel -> rsp_demux_004:sink_channel
wire router_006_src_startofpacket; // router_006:src_startofpacket -> rsp_demux_004:sink_startofpacket
wire router_006_src_endofpacket; // router_006:src_endofpacket -> rsp_demux_004:sink_endofpacket
wire sram_data_s1_agent_rp_valid; // sram_data_s1_agent:rp_valid -> router_007:sink_valid
wire [98:0] sram_data_s1_agent_rp_data; // sram_data_s1_agent:rp_data -> router_007:sink_data
wire sram_data_s1_agent_rp_ready; // router_007:sink_ready -> sram_data_s1_agent:rp_ready
wire sram_data_s1_agent_rp_startofpacket; // sram_data_s1_agent:rp_startofpacket -> router_007:sink_startofpacket
wire sram_data_s1_agent_rp_endofpacket; // sram_data_s1_agent:rp_endofpacket -> router_007:sink_endofpacket
wire router_007_src_valid; // router_007:src_valid -> rsp_demux_005:sink_valid
wire [98:0] router_007_src_data; // router_007:src_data -> rsp_demux_005:sink_data
wire router_007_src_ready; // rsp_demux_005:sink_ready -> router_007:src_ready
wire [31:0] router_007_src_channel; // router_007:src_channel -> rsp_demux_005:sink_channel
wire router_007_src_startofpacket; // router_007:src_startofpacket -> rsp_demux_005:sink_startofpacket
wire router_007_src_endofpacket; // router_007:src_endofpacket -> rsp_demux_005:sink_endofpacket
wire sram_addr_s1_agent_rp_valid; // sram_addr_s1_agent:rp_valid -> router_008:sink_valid
wire [98:0] sram_addr_s1_agent_rp_data; // sram_addr_s1_agent:rp_data -> router_008:sink_data
wire sram_addr_s1_agent_rp_ready; // router_008:sink_ready -> sram_addr_s1_agent:rp_ready
wire sram_addr_s1_agent_rp_startofpacket; // sram_addr_s1_agent:rp_startofpacket -> router_008:sink_startofpacket
wire sram_addr_s1_agent_rp_endofpacket; // sram_addr_s1_agent:rp_endofpacket -> router_008:sink_endofpacket
wire router_008_src_valid; // router_008:src_valid -> rsp_demux_006:sink_valid
wire [98:0] router_008_src_data; // router_008:src_data -> rsp_demux_006:sink_data
wire router_008_src_ready; // rsp_demux_006:sink_ready -> router_008:src_ready
wire [31:0] router_008_src_channel; // router_008:src_channel -> rsp_demux_006:sink_channel
wire router_008_src_startofpacket; // router_008:src_startofpacket -> rsp_demux_006:sink_startofpacket
wire router_008_src_endofpacket; // router_008:src_endofpacket -> rsp_demux_006:sink_endofpacket
wire sram_read_write_s1_agent_rp_valid; // sram_read_write_s1_agent:rp_valid -> router_009:sink_valid
wire [98:0] sram_read_write_s1_agent_rp_data; // sram_read_write_s1_agent:rp_data -> router_009:sink_data
wire sram_read_write_s1_agent_rp_ready; // router_009:sink_ready -> sram_read_write_s1_agent:rp_ready
wire sram_read_write_s1_agent_rp_startofpacket; // sram_read_write_s1_agent:rp_startofpacket -> router_009:sink_startofpacket
wire sram_read_write_s1_agent_rp_endofpacket; // sram_read_write_s1_agent:rp_endofpacket -> router_009:sink_endofpacket
wire router_009_src_valid; // router_009:src_valid -> rsp_demux_007:sink_valid
wire [98:0] router_009_src_data; // router_009:src_data -> rsp_demux_007:sink_data
wire router_009_src_ready; // rsp_demux_007:sink_ready -> router_009:src_ready
wire [31:0] router_009_src_channel; // router_009:src_channel -> rsp_demux_007:sink_channel
wire router_009_src_startofpacket; // router_009:src_startofpacket -> rsp_demux_007:sink_startofpacket
wire router_009_src_endofpacket; // router_009:src_endofpacket -> rsp_demux_007:sink_endofpacket
wire sram_cs_s1_agent_rp_valid; // sram_cs_s1_agent:rp_valid -> router_010:sink_valid
wire [98:0] sram_cs_s1_agent_rp_data; // sram_cs_s1_agent:rp_data -> router_010:sink_data
wire sram_cs_s1_agent_rp_ready; // router_010:sink_ready -> sram_cs_s1_agent:rp_ready
wire sram_cs_s1_agent_rp_startofpacket; // sram_cs_s1_agent:rp_startofpacket -> router_010:sink_startofpacket
wire sram_cs_s1_agent_rp_endofpacket; // sram_cs_s1_agent:rp_endofpacket -> router_010:sink_endofpacket
wire router_010_src_valid; // router_010:src_valid -> rsp_demux_008:sink_valid
wire [98:0] router_010_src_data; // router_010:src_data -> rsp_demux_008:sink_data
wire router_010_src_ready; // rsp_demux_008:sink_ready -> router_010:src_ready
wire [31:0] router_010_src_channel; // router_010:src_channel -> rsp_demux_008:sink_channel
wire router_010_src_startofpacket; // router_010:src_startofpacket -> rsp_demux_008:sink_startofpacket
wire router_010_src_endofpacket; // router_010:src_endofpacket -> rsp_demux_008:sink_endofpacket
wire sram_oe_s1_agent_rp_valid; // sram_oe_s1_agent:rp_valid -> router_011:sink_valid
wire [98:0] sram_oe_s1_agent_rp_data; // sram_oe_s1_agent:rp_data -> router_011:sink_data
wire sram_oe_s1_agent_rp_ready; // router_011:sink_ready -> sram_oe_s1_agent:rp_ready
wire sram_oe_s1_agent_rp_startofpacket; // sram_oe_s1_agent:rp_startofpacket -> router_011:sink_startofpacket
wire sram_oe_s1_agent_rp_endofpacket; // sram_oe_s1_agent:rp_endofpacket -> router_011:sink_endofpacket
wire router_011_src_valid; // router_011:src_valid -> rsp_demux_009:sink_valid
wire [98:0] router_011_src_data; // router_011:src_data -> rsp_demux_009:sink_data
wire router_011_src_ready; // rsp_demux_009:sink_ready -> router_011:src_ready
wire [31:0] router_011_src_channel; // router_011:src_channel -> rsp_demux_009:sink_channel
wire router_011_src_startofpacket; // router_011:src_startofpacket -> rsp_demux_009:sink_startofpacket
wire router_011_src_endofpacket; // router_011:src_endofpacket -> rsp_demux_009:sink_endofpacket
wire regfile_data_s1_agent_rp_valid; // regfile_data_s1_agent:rp_valid -> router_012:sink_valid
wire [98:0] regfile_data_s1_agent_rp_data; // regfile_data_s1_agent:rp_data -> router_012:sink_data
wire regfile_data_s1_agent_rp_ready; // router_012:sink_ready -> regfile_data_s1_agent:rp_ready
wire regfile_data_s1_agent_rp_startofpacket; // regfile_data_s1_agent:rp_startofpacket -> router_012:sink_startofpacket
wire regfile_data_s1_agent_rp_endofpacket; // regfile_data_s1_agent:rp_endofpacket -> router_012:sink_endofpacket
wire router_012_src_valid; // router_012:src_valid -> rsp_demux_010:sink_valid
wire [98:0] router_012_src_data; // router_012:src_data -> rsp_demux_010:sink_data
wire router_012_src_ready; // rsp_demux_010:sink_ready -> router_012:src_ready
wire [31:0] router_012_src_channel; // router_012:src_channel -> rsp_demux_010:sink_channel
wire router_012_src_startofpacket; // router_012:src_startofpacket -> rsp_demux_010:sink_startofpacket
wire router_012_src_endofpacket; // router_012:src_endofpacket -> rsp_demux_010:sink_endofpacket
wire regfile_reg1_s1_agent_rp_valid; // regfile_reg1_s1_agent:rp_valid -> router_013:sink_valid
wire [98:0] regfile_reg1_s1_agent_rp_data; // regfile_reg1_s1_agent:rp_data -> router_013:sink_data
wire regfile_reg1_s1_agent_rp_ready; // router_013:sink_ready -> regfile_reg1_s1_agent:rp_ready
wire regfile_reg1_s1_agent_rp_startofpacket; // regfile_reg1_s1_agent:rp_startofpacket -> router_013:sink_startofpacket
wire regfile_reg1_s1_agent_rp_endofpacket; // regfile_reg1_s1_agent:rp_endofpacket -> router_013:sink_endofpacket
wire router_013_src_valid; // router_013:src_valid -> rsp_demux_011:sink_valid
wire [98:0] router_013_src_data; // router_013:src_data -> rsp_demux_011:sink_data
wire router_013_src_ready; // rsp_demux_011:sink_ready -> router_013:src_ready
wire [31:0] router_013_src_channel; // router_013:src_channel -> rsp_demux_011:sink_channel
wire router_013_src_startofpacket; // router_013:src_startofpacket -> rsp_demux_011:sink_startofpacket
wire router_013_src_endofpacket; // router_013:src_endofpacket -> rsp_demux_011:sink_endofpacket
wire regfile_reg2_s1_agent_rp_valid; // regfile_reg2_s1_agent:rp_valid -> router_014:sink_valid
wire [98:0] regfile_reg2_s1_agent_rp_data; // regfile_reg2_s1_agent:rp_data -> router_014:sink_data
wire regfile_reg2_s1_agent_rp_ready; // router_014:sink_ready -> regfile_reg2_s1_agent:rp_ready
wire regfile_reg2_s1_agent_rp_startofpacket; // regfile_reg2_s1_agent:rp_startofpacket -> router_014:sink_startofpacket
wire regfile_reg2_s1_agent_rp_endofpacket; // regfile_reg2_s1_agent:rp_endofpacket -> router_014:sink_endofpacket
wire router_014_src_valid; // router_014:src_valid -> rsp_demux_012:sink_valid
wire [98:0] router_014_src_data; // router_014:src_data -> rsp_demux_012:sink_data
wire router_014_src_ready; // rsp_demux_012:sink_ready -> router_014:src_ready
wire [31:0] router_014_src_channel; // router_014:src_channel -> rsp_demux_012:sink_channel
wire router_014_src_startofpacket; // router_014:src_startofpacket -> rsp_demux_012:sink_startofpacket
wire router_014_src_endofpacket; // router_014:src_endofpacket -> rsp_demux_012:sink_endofpacket
wire regfile_r1sel_s1_agent_rp_valid; // regfile_r1sel_s1_agent:rp_valid -> router_015:sink_valid
wire [98:0] regfile_r1sel_s1_agent_rp_data; // regfile_r1sel_s1_agent:rp_data -> router_015:sink_data
wire regfile_r1sel_s1_agent_rp_ready; // router_015:sink_ready -> regfile_r1sel_s1_agent:rp_ready
wire regfile_r1sel_s1_agent_rp_startofpacket; // regfile_r1sel_s1_agent:rp_startofpacket -> router_015:sink_startofpacket
wire regfile_r1sel_s1_agent_rp_endofpacket; // regfile_r1sel_s1_agent:rp_endofpacket -> router_015:sink_endofpacket
wire router_015_src_valid; // router_015:src_valid -> rsp_demux_013:sink_valid
wire [98:0] router_015_src_data; // router_015:src_data -> rsp_demux_013:sink_data
wire router_015_src_ready; // rsp_demux_013:sink_ready -> router_015:src_ready
wire [31:0] router_015_src_channel; // router_015:src_channel -> rsp_demux_013:sink_channel
wire router_015_src_startofpacket; // router_015:src_startofpacket -> rsp_demux_013:sink_startofpacket
wire router_015_src_endofpacket; // router_015:src_endofpacket -> rsp_demux_013:sink_endofpacket
wire regfile_r2sel_s1_agent_rp_valid; // regfile_r2sel_s1_agent:rp_valid -> router_016:sink_valid
wire [98:0] regfile_r2sel_s1_agent_rp_data; // regfile_r2sel_s1_agent:rp_data -> router_016:sink_data
wire regfile_r2sel_s1_agent_rp_ready; // router_016:sink_ready -> regfile_r2sel_s1_agent:rp_ready
wire regfile_r2sel_s1_agent_rp_startofpacket; // regfile_r2sel_s1_agent:rp_startofpacket -> router_016:sink_startofpacket
wire regfile_r2sel_s1_agent_rp_endofpacket; // regfile_r2sel_s1_agent:rp_endofpacket -> router_016:sink_endofpacket
wire router_016_src_valid; // router_016:src_valid -> rsp_demux_014:sink_valid
wire [98:0] router_016_src_data; // router_016:src_data -> rsp_demux_014:sink_data
wire router_016_src_ready; // rsp_demux_014:sink_ready -> router_016:src_ready
wire [31:0] router_016_src_channel; // router_016:src_channel -> rsp_demux_014:sink_channel
wire router_016_src_startofpacket; // router_016:src_startofpacket -> rsp_demux_014:sink_startofpacket
wire router_016_src_endofpacket; // router_016:src_endofpacket -> rsp_demux_014:sink_endofpacket
wire regfile_wsel_s1_agent_rp_valid; // regfile_wsel_s1_agent:rp_valid -> router_017:sink_valid
wire [98:0] regfile_wsel_s1_agent_rp_data; // regfile_wsel_s1_agent:rp_data -> router_017:sink_data
wire regfile_wsel_s1_agent_rp_ready; // router_017:sink_ready -> regfile_wsel_s1_agent:rp_ready
wire regfile_wsel_s1_agent_rp_startofpacket; // regfile_wsel_s1_agent:rp_startofpacket -> router_017:sink_startofpacket
wire regfile_wsel_s1_agent_rp_endofpacket; // regfile_wsel_s1_agent:rp_endofpacket -> router_017:sink_endofpacket
wire router_017_src_valid; // router_017:src_valid -> rsp_demux_015:sink_valid
wire [98:0] router_017_src_data; // router_017:src_data -> rsp_demux_015:sink_data
wire router_017_src_ready; // rsp_demux_015:sink_ready -> router_017:src_ready
wire [31:0] router_017_src_channel; // router_017:src_channel -> rsp_demux_015:sink_channel
wire router_017_src_startofpacket; // router_017:src_startofpacket -> rsp_demux_015:sink_startofpacket
wire router_017_src_endofpacket; // router_017:src_endofpacket -> rsp_demux_015:sink_endofpacket
wire regfile_we_s1_agent_rp_valid; // regfile_we_s1_agent:rp_valid -> router_018:sink_valid
wire [98:0] regfile_we_s1_agent_rp_data; // regfile_we_s1_agent:rp_data -> router_018:sink_data
wire regfile_we_s1_agent_rp_ready; // router_018:sink_ready -> regfile_we_s1_agent:rp_ready
wire regfile_we_s1_agent_rp_startofpacket; // regfile_we_s1_agent:rp_startofpacket -> router_018:sink_startofpacket
wire regfile_we_s1_agent_rp_endofpacket; // regfile_we_s1_agent:rp_endofpacket -> router_018:sink_endofpacket
wire router_018_src_valid; // router_018:src_valid -> rsp_demux_016:sink_valid
wire [98:0] router_018_src_data; // router_018:src_data -> rsp_demux_016:sink_data
wire router_018_src_ready; // rsp_demux_016:sink_ready -> router_018:src_ready
wire [31:0] router_018_src_channel; // router_018:src_channel -> rsp_demux_016:sink_channel
wire router_018_src_startofpacket; // router_018:src_startofpacket -> rsp_demux_016:sink_startofpacket
wire router_018_src_endofpacket; // router_018:src_endofpacket -> rsp_demux_016:sink_endofpacket
wire hex_0_s1_agent_rp_valid; // hex_0_s1_agent:rp_valid -> router_019:sink_valid
wire [98:0] hex_0_s1_agent_rp_data; // hex_0_s1_agent:rp_data -> router_019:sink_data
wire hex_0_s1_agent_rp_ready; // router_019:sink_ready -> hex_0_s1_agent:rp_ready
wire hex_0_s1_agent_rp_startofpacket; // hex_0_s1_agent:rp_startofpacket -> router_019:sink_startofpacket
wire hex_0_s1_agent_rp_endofpacket; // hex_0_s1_agent:rp_endofpacket -> router_019:sink_endofpacket
wire router_019_src_valid; // router_019:src_valid -> rsp_demux_017:sink_valid
wire [98:0] router_019_src_data; // router_019:src_data -> rsp_demux_017:sink_data
wire router_019_src_ready; // rsp_demux_017:sink_ready -> router_019:src_ready
wire [31:0] router_019_src_channel; // router_019:src_channel -> rsp_demux_017:sink_channel
wire router_019_src_startofpacket; // router_019:src_startofpacket -> rsp_demux_017:sink_startofpacket
wire router_019_src_endofpacket; // router_019:src_endofpacket -> rsp_demux_017:sink_endofpacket
wire hex_1_s1_agent_rp_valid; // hex_1_s1_agent:rp_valid -> router_020:sink_valid
wire [98:0] hex_1_s1_agent_rp_data; // hex_1_s1_agent:rp_data -> router_020:sink_data
wire hex_1_s1_agent_rp_ready; // router_020:sink_ready -> hex_1_s1_agent:rp_ready
wire hex_1_s1_agent_rp_startofpacket; // hex_1_s1_agent:rp_startofpacket -> router_020:sink_startofpacket
wire hex_1_s1_agent_rp_endofpacket; // hex_1_s1_agent:rp_endofpacket -> router_020:sink_endofpacket
wire router_020_src_valid; // router_020:src_valid -> rsp_demux_018:sink_valid
wire [98:0] router_020_src_data; // router_020:src_data -> rsp_demux_018:sink_data
wire router_020_src_ready; // rsp_demux_018:sink_ready -> router_020:src_ready
wire [31:0] router_020_src_channel; // router_020:src_channel -> rsp_demux_018:sink_channel
wire router_020_src_startofpacket; // router_020:src_startofpacket -> rsp_demux_018:sink_startofpacket
wire router_020_src_endofpacket; // router_020:src_endofpacket -> rsp_demux_018:sink_endofpacket
wire hex_2_s1_agent_rp_valid; // hex_2_s1_agent:rp_valid -> router_021:sink_valid
wire [98:0] hex_2_s1_agent_rp_data; // hex_2_s1_agent:rp_data -> router_021:sink_data
wire hex_2_s1_agent_rp_ready; // router_021:sink_ready -> hex_2_s1_agent:rp_ready
wire hex_2_s1_agent_rp_startofpacket; // hex_2_s1_agent:rp_startofpacket -> router_021:sink_startofpacket
wire hex_2_s1_agent_rp_endofpacket; // hex_2_s1_agent:rp_endofpacket -> router_021:sink_endofpacket
wire router_021_src_valid; // router_021:src_valid -> rsp_demux_019:sink_valid
wire [98:0] router_021_src_data; // router_021:src_data -> rsp_demux_019:sink_data
wire router_021_src_ready; // rsp_demux_019:sink_ready -> router_021:src_ready
wire [31:0] router_021_src_channel; // router_021:src_channel -> rsp_demux_019:sink_channel
wire router_021_src_startofpacket; // router_021:src_startofpacket -> rsp_demux_019:sink_startofpacket
wire router_021_src_endofpacket; // router_021:src_endofpacket -> rsp_demux_019:sink_endofpacket
wire hex_3_s1_agent_rp_valid; // hex_3_s1_agent:rp_valid -> router_022:sink_valid
wire [98:0] hex_3_s1_agent_rp_data; // hex_3_s1_agent:rp_data -> router_022:sink_data
wire hex_3_s1_agent_rp_ready; // router_022:sink_ready -> hex_3_s1_agent:rp_ready
wire hex_3_s1_agent_rp_startofpacket; // hex_3_s1_agent:rp_startofpacket -> router_022:sink_startofpacket
wire hex_3_s1_agent_rp_endofpacket; // hex_3_s1_agent:rp_endofpacket -> router_022:sink_endofpacket
wire router_022_src_valid; // router_022:src_valid -> rsp_demux_020:sink_valid
wire [98:0] router_022_src_data; // router_022:src_data -> rsp_demux_020:sink_data
wire router_022_src_ready; // rsp_demux_020:sink_ready -> router_022:src_ready
wire [31:0] router_022_src_channel; // router_022:src_channel -> rsp_demux_020:sink_channel
wire router_022_src_startofpacket; // router_022:src_startofpacket -> rsp_demux_020:sink_startofpacket
wire router_022_src_endofpacket; // router_022:src_endofpacket -> rsp_demux_020:sink_endofpacket
wire hex_4_s1_agent_rp_valid; // hex_4_s1_agent:rp_valid -> router_023:sink_valid
wire [98:0] hex_4_s1_agent_rp_data; // hex_4_s1_agent:rp_data -> router_023:sink_data
wire hex_4_s1_agent_rp_ready; // router_023:sink_ready -> hex_4_s1_agent:rp_ready
wire hex_4_s1_agent_rp_startofpacket; // hex_4_s1_agent:rp_startofpacket -> router_023:sink_startofpacket
wire hex_4_s1_agent_rp_endofpacket; // hex_4_s1_agent:rp_endofpacket -> router_023:sink_endofpacket
wire router_023_src_valid; // router_023:src_valid -> rsp_demux_021:sink_valid
wire [98:0] router_023_src_data; // router_023:src_data -> rsp_demux_021:sink_data
wire router_023_src_ready; // rsp_demux_021:sink_ready -> router_023:src_ready
wire [31:0] router_023_src_channel; // router_023:src_channel -> rsp_demux_021:sink_channel
wire router_023_src_startofpacket; // router_023:src_startofpacket -> rsp_demux_021:sink_startofpacket
wire router_023_src_endofpacket; // router_023:src_endofpacket -> rsp_demux_021:sink_endofpacket
wire hex_5_s1_agent_rp_valid; // hex_5_s1_agent:rp_valid -> router_024:sink_valid
wire [98:0] hex_5_s1_agent_rp_data; // hex_5_s1_agent:rp_data -> router_024:sink_data
wire hex_5_s1_agent_rp_ready; // router_024:sink_ready -> hex_5_s1_agent:rp_ready
wire hex_5_s1_agent_rp_startofpacket; // hex_5_s1_agent:rp_startofpacket -> router_024:sink_startofpacket
wire hex_5_s1_agent_rp_endofpacket; // hex_5_s1_agent:rp_endofpacket -> router_024:sink_endofpacket
wire router_024_src_valid; // router_024:src_valid -> rsp_demux_022:sink_valid
wire [98:0] router_024_src_data; // router_024:src_data -> rsp_demux_022:sink_data
wire router_024_src_ready; // rsp_demux_022:sink_ready -> router_024:src_ready
wire [31:0] router_024_src_channel; // router_024:src_channel -> rsp_demux_022:sink_channel
wire router_024_src_startofpacket; // router_024:src_startofpacket -> rsp_demux_022:sink_startofpacket
wire router_024_src_endofpacket; // router_024:src_endofpacket -> rsp_demux_022:sink_endofpacket
wire alu_a_s1_agent_rp_valid; // alu_a_s1_agent:rp_valid -> router_025:sink_valid
wire [98:0] alu_a_s1_agent_rp_data; // alu_a_s1_agent:rp_data -> router_025:sink_data
wire alu_a_s1_agent_rp_ready; // router_025:sink_ready -> alu_a_s1_agent:rp_ready
wire alu_a_s1_agent_rp_startofpacket; // alu_a_s1_agent:rp_startofpacket -> router_025:sink_startofpacket
wire alu_a_s1_agent_rp_endofpacket; // alu_a_s1_agent:rp_endofpacket -> router_025:sink_endofpacket
wire router_025_src_valid; // router_025:src_valid -> rsp_demux_023:sink_valid
wire [98:0] router_025_src_data; // router_025:src_data -> rsp_demux_023:sink_data
wire router_025_src_ready; // rsp_demux_023:sink_ready -> router_025:src_ready
wire [31:0] router_025_src_channel; // router_025:src_channel -> rsp_demux_023:sink_channel
wire router_025_src_startofpacket; // router_025:src_startofpacket -> rsp_demux_023:sink_startofpacket
wire router_025_src_endofpacket; // router_025:src_endofpacket -> rsp_demux_023:sink_endofpacket
wire alu_b_s1_agent_rp_valid; // alu_b_s1_agent:rp_valid -> router_026:sink_valid
wire [98:0] alu_b_s1_agent_rp_data; // alu_b_s1_agent:rp_data -> router_026:sink_data
wire alu_b_s1_agent_rp_ready; // router_026:sink_ready -> alu_b_s1_agent:rp_ready
wire alu_b_s1_agent_rp_startofpacket; // alu_b_s1_agent:rp_startofpacket -> router_026:sink_startofpacket
wire alu_b_s1_agent_rp_endofpacket; // alu_b_s1_agent:rp_endofpacket -> router_026:sink_endofpacket
wire router_026_src_valid; // router_026:src_valid -> rsp_demux_024:sink_valid
wire [98:0] router_026_src_data; // router_026:src_data -> rsp_demux_024:sink_data
wire router_026_src_ready; // rsp_demux_024:sink_ready -> router_026:src_ready
wire [31:0] router_026_src_channel; // router_026:src_channel -> rsp_demux_024:sink_channel
wire router_026_src_startofpacket; // router_026:src_startofpacket -> rsp_demux_024:sink_startofpacket
wire router_026_src_endofpacket; // router_026:src_endofpacket -> rsp_demux_024:sink_endofpacket
wire alu_control_s1_agent_rp_valid; // alu_control_s1_agent:rp_valid -> router_027:sink_valid
wire [98:0] alu_control_s1_agent_rp_data; // alu_control_s1_agent:rp_data -> router_027:sink_data
wire alu_control_s1_agent_rp_ready; // router_027:sink_ready -> alu_control_s1_agent:rp_ready
wire alu_control_s1_agent_rp_startofpacket; // alu_control_s1_agent:rp_startofpacket -> router_027:sink_startofpacket
wire alu_control_s1_agent_rp_endofpacket; // alu_control_s1_agent:rp_endofpacket -> router_027:sink_endofpacket
wire router_027_src_valid; // router_027:src_valid -> rsp_demux_025:sink_valid
wire [98:0] router_027_src_data; // router_027:src_data -> rsp_demux_025:sink_data
wire router_027_src_ready; // rsp_demux_025:sink_ready -> router_027:src_ready
wire [31:0] router_027_src_channel; // router_027:src_channel -> rsp_demux_025:sink_channel
wire router_027_src_startofpacket; // router_027:src_startofpacket -> rsp_demux_025:sink_startofpacket
wire router_027_src_endofpacket; // router_027:src_endofpacket -> rsp_demux_025:sink_endofpacket
wire alu_out_s1_agent_rp_valid; // alu_out_s1_agent:rp_valid -> router_028:sink_valid
wire [98:0] alu_out_s1_agent_rp_data; // alu_out_s1_agent:rp_data -> router_028:sink_data
wire alu_out_s1_agent_rp_ready; // router_028:sink_ready -> alu_out_s1_agent:rp_ready
wire alu_out_s1_agent_rp_startofpacket; // alu_out_s1_agent:rp_startofpacket -> router_028:sink_startofpacket
wire alu_out_s1_agent_rp_endofpacket; // alu_out_s1_agent:rp_endofpacket -> router_028:sink_endofpacket
wire router_028_src_valid; // router_028:src_valid -> rsp_demux_026:sink_valid
wire [98:0] router_028_src_data; // router_028:src_data -> rsp_demux_026:sink_data
wire router_028_src_ready; // rsp_demux_026:sink_ready -> router_028:src_ready
wire [31:0] router_028_src_channel; // router_028:src_channel -> rsp_demux_026:sink_channel
wire router_028_src_startofpacket; // router_028:src_startofpacket -> rsp_demux_026:sink_startofpacket
wire router_028_src_endofpacket; // router_028:src_endofpacket -> rsp_demux_026:sink_endofpacket
wire alu_zero_s1_agent_rp_valid; // alu_zero_s1_agent:rp_valid -> router_029:sink_valid
wire [98:0] alu_zero_s1_agent_rp_data; // alu_zero_s1_agent:rp_data -> router_029:sink_data
wire alu_zero_s1_agent_rp_ready; // router_029:sink_ready -> alu_zero_s1_agent:rp_ready
wire alu_zero_s1_agent_rp_startofpacket; // alu_zero_s1_agent:rp_startofpacket -> router_029:sink_startofpacket
wire alu_zero_s1_agent_rp_endofpacket; // alu_zero_s1_agent:rp_endofpacket -> router_029:sink_endofpacket
wire router_029_src_valid; // router_029:src_valid -> rsp_demux_027:sink_valid
wire [98:0] router_029_src_data; // router_029:src_data -> rsp_demux_027:sink_data
wire router_029_src_ready; // rsp_demux_027:sink_ready -> router_029:src_ready
wire [31:0] router_029_src_channel; // router_029:src_channel -> rsp_demux_027:sink_channel
wire router_029_src_startofpacket; // router_029:src_startofpacket -> rsp_demux_027:sink_startofpacket
wire router_029_src_endofpacket; // router_029:src_endofpacket -> rsp_demux_027:sink_endofpacket
wire alu_overflow_s1_agent_rp_valid; // alu_overflow_s1_agent:rp_valid -> router_030:sink_valid
wire [98:0] alu_overflow_s1_agent_rp_data; // alu_overflow_s1_agent:rp_data -> router_030:sink_data
wire alu_overflow_s1_agent_rp_ready; // router_030:sink_ready -> alu_overflow_s1_agent:rp_ready
wire alu_overflow_s1_agent_rp_startofpacket; // alu_overflow_s1_agent:rp_startofpacket -> router_030:sink_startofpacket
wire alu_overflow_s1_agent_rp_endofpacket; // alu_overflow_s1_agent:rp_endofpacket -> router_030:sink_endofpacket
wire router_030_src_valid; // router_030:src_valid -> rsp_demux_028:sink_valid
wire [98:0] router_030_src_data; // router_030:src_data -> rsp_demux_028:sink_data
wire router_030_src_ready; // rsp_demux_028:sink_ready -> router_030:src_ready
wire [31:0] router_030_src_channel; // router_030:src_channel -> rsp_demux_028:sink_channel
wire router_030_src_startofpacket; // router_030:src_startofpacket -> rsp_demux_028:sink_startofpacket
wire router_030_src_endofpacket; // router_030:src_endofpacket -> rsp_demux_028:sink_endofpacket
wire alu_carry_out_s1_agent_rp_valid; // alu_carry_out_s1_agent:rp_valid -> router_031:sink_valid
wire [98:0] alu_carry_out_s1_agent_rp_data; // alu_carry_out_s1_agent:rp_data -> router_031:sink_data
wire alu_carry_out_s1_agent_rp_ready; // router_031:sink_ready -> alu_carry_out_s1_agent:rp_ready
wire alu_carry_out_s1_agent_rp_startofpacket; // alu_carry_out_s1_agent:rp_startofpacket -> router_031:sink_startofpacket
wire alu_carry_out_s1_agent_rp_endofpacket; // alu_carry_out_s1_agent:rp_endofpacket -> router_031:sink_endofpacket
wire router_031_src_valid; // router_031:src_valid -> rsp_demux_029:sink_valid
wire [98:0] router_031_src_data; // router_031:src_data -> rsp_demux_029:sink_data
wire router_031_src_ready; // rsp_demux_029:sink_ready -> router_031:src_ready
wire [31:0] router_031_src_channel; // router_031:src_channel -> rsp_demux_029:sink_channel
wire router_031_src_startofpacket; // router_031:src_startofpacket -> rsp_demux_029:sink_startofpacket
wire router_031_src_endofpacket; // router_031:src_endofpacket -> rsp_demux_029:sink_endofpacket
wire alu_negative_s1_agent_rp_valid; // alu_negative_s1_agent:rp_valid -> router_032:sink_valid
wire [98:0] alu_negative_s1_agent_rp_data; // alu_negative_s1_agent:rp_data -> router_032:sink_data
wire alu_negative_s1_agent_rp_ready; // router_032:sink_ready -> alu_negative_s1_agent:rp_ready
wire alu_negative_s1_agent_rp_startofpacket; // alu_negative_s1_agent:rp_startofpacket -> router_032:sink_startofpacket
wire alu_negative_s1_agent_rp_endofpacket; // alu_negative_s1_agent:rp_endofpacket -> router_032:sink_endofpacket
wire router_032_src_valid; // router_032:src_valid -> rsp_demux_030:sink_valid
wire [98:0] router_032_src_data; // router_032:src_data -> rsp_demux_030:sink_data
wire router_032_src_ready; // rsp_demux_030:sink_ready -> router_032:src_ready
wire [31:0] router_032_src_channel; // router_032:src_channel -> rsp_demux_030:sink_channel
wire router_032_src_startofpacket; // router_032:src_startofpacket -> rsp_demux_030:sink_startofpacket
wire router_032_src_endofpacket; // router_032:src_endofpacket -> rsp_demux_030:sink_endofpacket
wire keys_s1_agent_rp_valid; // keys_s1_agent:rp_valid -> router_033:sink_valid
wire [98:0] keys_s1_agent_rp_data; // keys_s1_agent:rp_data -> router_033:sink_data
wire keys_s1_agent_rp_ready; // router_033:sink_ready -> keys_s1_agent:rp_ready
wire keys_s1_agent_rp_startofpacket; // keys_s1_agent:rp_startofpacket -> router_033:sink_startofpacket
wire keys_s1_agent_rp_endofpacket; // keys_s1_agent:rp_endofpacket -> router_033:sink_endofpacket
wire router_033_src_valid; // router_033:src_valid -> rsp_demux_031:sink_valid
wire [98:0] router_033_src_data; // router_033:src_data -> rsp_demux_031:sink_data
wire router_033_src_ready; // rsp_demux_031:sink_ready -> router_033:src_ready
wire [31:0] router_033_src_channel; // router_033:src_channel -> rsp_demux_031:sink_channel
wire router_033_src_startofpacket; // router_033:src_startofpacket -> rsp_demux_031:sink_startofpacket
wire router_033_src_endofpacket; // router_033:src_endofpacket -> rsp_demux_031:sink_endofpacket
wire cmd_demux_src0_valid; // cmd_demux:src0_valid -> cmd_mux:sink0_valid
wire [98:0] cmd_demux_src0_data; // cmd_demux:src0_data -> cmd_mux:sink0_data
wire cmd_demux_src0_ready; // cmd_mux:sink0_ready -> cmd_demux:src0_ready
wire [31:0] cmd_demux_src0_channel; // cmd_demux:src0_channel -> cmd_mux:sink0_channel
wire cmd_demux_src0_startofpacket; // cmd_demux:src0_startofpacket -> cmd_mux:sink0_startofpacket
wire cmd_demux_src0_endofpacket; // cmd_demux:src0_endofpacket -> cmd_mux:sink0_endofpacket
wire cmd_demux_src1_valid; // cmd_demux:src1_valid -> cmd_mux_001:sink0_valid
wire [98:0] cmd_demux_src1_data; // cmd_demux:src1_data -> cmd_mux_001:sink0_data
wire cmd_demux_src1_ready; // cmd_mux_001:sink0_ready -> cmd_demux:src1_ready
wire [31:0] cmd_demux_src1_channel; // cmd_demux:src1_channel -> cmd_mux_001:sink0_channel
wire cmd_demux_src1_startofpacket; // cmd_demux:src1_startofpacket -> cmd_mux_001:sink0_startofpacket
wire cmd_demux_src1_endofpacket; // cmd_demux:src1_endofpacket -> cmd_mux_001:sink0_endofpacket
wire cmd_demux_src2_valid; // cmd_demux:src2_valid -> cmd_mux_002:sink0_valid
wire [98:0] cmd_demux_src2_data; // cmd_demux:src2_data -> cmd_mux_002:sink0_data
wire cmd_demux_src2_ready; // cmd_mux_002:sink0_ready -> cmd_demux:src2_ready
wire [31:0] cmd_demux_src2_channel; // cmd_demux:src2_channel -> cmd_mux_002:sink0_channel
wire cmd_demux_src2_startofpacket; // cmd_demux:src2_startofpacket -> cmd_mux_002:sink0_startofpacket
wire cmd_demux_src2_endofpacket; // cmd_demux:src2_endofpacket -> cmd_mux_002:sink0_endofpacket
wire cmd_demux_src3_valid; // cmd_demux:src3_valid -> cmd_mux_003:sink0_valid
wire [98:0] cmd_demux_src3_data; // cmd_demux:src3_data -> cmd_mux_003:sink0_data
wire cmd_demux_src3_ready; // cmd_mux_003:sink0_ready -> cmd_demux:src3_ready
wire [31:0] cmd_demux_src3_channel; // cmd_demux:src3_channel -> cmd_mux_003:sink0_channel
wire cmd_demux_src3_startofpacket; // cmd_demux:src3_startofpacket -> cmd_mux_003:sink0_startofpacket
wire cmd_demux_src3_endofpacket; // cmd_demux:src3_endofpacket -> cmd_mux_003:sink0_endofpacket
wire cmd_demux_src4_valid; // cmd_demux:src4_valid -> cmd_mux_004:sink0_valid
wire [98:0] cmd_demux_src4_data; // cmd_demux:src4_data -> cmd_mux_004:sink0_data
wire cmd_demux_src4_ready; // cmd_mux_004:sink0_ready -> cmd_demux:src4_ready
wire [31:0] cmd_demux_src4_channel; // cmd_demux:src4_channel -> cmd_mux_004:sink0_channel
wire cmd_demux_src4_startofpacket; // cmd_demux:src4_startofpacket -> cmd_mux_004:sink0_startofpacket
wire cmd_demux_src4_endofpacket; // cmd_demux:src4_endofpacket -> cmd_mux_004:sink0_endofpacket
wire cmd_demux_src5_valid; // cmd_demux:src5_valid -> cmd_mux_005:sink0_valid
wire [98:0] cmd_demux_src5_data; // cmd_demux:src5_data -> cmd_mux_005:sink0_data
wire cmd_demux_src5_ready; // cmd_mux_005:sink0_ready -> cmd_demux:src5_ready
wire [31:0] cmd_demux_src5_channel; // cmd_demux:src5_channel -> cmd_mux_005:sink0_channel
wire cmd_demux_src5_startofpacket; // cmd_demux:src5_startofpacket -> cmd_mux_005:sink0_startofpacket
wire cmd_demux_src5_endofpacket; // cmd_demux:src5_endofpacket -> cmd_mux_005:sink0_endofpacket
wire cmd_demux_src6_valid; // cmd_demux:src6_valid -> cmd_mux_006:sink0_valid
wire [98:0] cmd_demux_src6_data; // cmd_demux:src6_data -> cmd_mux_006:sink0_data
wire cmd_demux_src6_ready; // cmd_mux_006:sink0_ready -> cmd_demux:src6_ready
wire [31:0] cmd_demux_src6_channel; // cmd_demux:src6_channel -> cmd_mux_006:sink0_channel
wire cmd_demux_src6_startofpacket; // cmd_demux:src6_startofpacket -> cmd_mux_006:sink0_startofpacket
wire cmd_demux_src6_endofpacket; // cmd_demux:src6_endofpacket -> cmd_mux_006:sink0_endofpacket
wire cmd_demux_src7_valid; // cmd_demux:src7_valid -> cmd_mux_007:sink0_valid
wire [98:0] cmd_demux_src7_data; // cmd_demux:src7_data -> cmd_mux_007:sink0_data
wire cmd_demux_src7_ready; // cmd_mux_007:sink0_ready -> cmd_demux:src7_ready
wire [31:0] cmd_demux_src7_channel; // cmd_demux:src7_channel -> cmd_mux_007:sink0_channel
wire cmd_demux_src7_startofpacket; // cmd_demux:src7_startofpacket -> cmd_mux_007:sink0_startofpacket
wire cmd_demux_src7_endofpacket; // cmd_demux:src7_endofpacket -> cmd_mux_007:sink0_endofpacket
wire cmd_demux_src8_valid; // cmd_demux:src8_valid -> cmd_mux_008:sink0_valid
wire [98:0] cmd_demux_src8_data; // cmd_demux:src8_data -> cmd_mux_008:sink0_data
wire cmd_demux_src8_ready; // cmd_mux_008:sink0_ready -> cmd_demux:src8_ready
wire [31:0] cmd_demux_src8_channel; // cmd_demux:src8_channel -> cmd_mux_008:sink0_channel
wire cmd_demux_src8_startofpacket; // cmd_demux:src8_startofpacket -> cmd_mux_008:sink0_startofpacket
wire cmd_demux_src8_endofpacket; // cmd_demux:src8_endofpacket -> cmd_mux_008:sink0_endofpacket
wire cmd_demux_src9_valid; // cmd_demux:src9_valid -> cmd_mux_009:sink0_valid
wire [98:0] cmd_demux_src9_data; // cmd_demux:src9_data -> cmd_mux_009:sink0_data
wire cmd_demux_src9_ready; // cmd_mux_009:sink0_ready -> cmd_demux:src9_ready
wire [31:0] cmd_demux_src9_channel; // cmd_demux:src9_channel -> cmd_mux_009:sink0_channel
wire cmd_demux_src9_startofpacket; // cmd_demux:src9_startofpacket -> cmd_mux_009:sink0_startofpacket
wire cmd_demux_src9_endofpacket; // cmd_demux:src9_endofpacket -> cmd_mux_009:sink0_endofpacket
wire cmd_demux_src10_valid; // cmd_demux:src10_valid -> cmd_mux_010:sink0_valid
wire [98:0] cmd_demux_src10_data; // cmd_demux:src10_data -> cmd_mux_010:sink0_data
wire cmd_demux_src10_ready; // cmd_mux_010:sink0_ready -> cmd_demux:src10_ready
wire [31:0] cmd_demux_src10_channel; // cmd_demux:src10_channel -> cmd_mux_010:sink0_channel
wire cmd_demux_src10_startofpacket; // cmd_demux:src10_startofpacket -> cmd_mux_010:sink0_startofpacket
wire cmd_demux_src10_endofpacket; // cmd_demux:src10_endofpacket -> cmd_mux_010:sink0_endofpacket
wire cmd_demux_src11_valid; // cmd_demux:src11_valid -> cmd_mux_011:sink0_valid
wire [98:0] cmd_demux_src11_data; // cmd_demux:src11_data -> cmd_mux_011:sink0_data
wire cmd_demux_src11_ready; // cmd_mux_011:sink0_ready -> cmd_demux:src11_ready
wire [31:0] cmd_demux_src11_channel; // cmd_demux:src11_channel -> cmd_mux_011:sink0_channel
wire cmd_demux_src11_startofpacket; // cmd_demux:src11_startofpacket -> cmd_mux_011:sink0_startofpacket
wire cmd_demux_src11_endofpacket; // cmd_demux:src11_endofpacket -> cmd_mux_011:sink0_endofpacket
wire cmd_demux_src12_valid; // cmd_demux:src12_valid -> cmd_mux_012:sink0_valid
wire [98:0] cmd_demux_src12_data; // cmd_demux:src12_data -> cmd_mux_012:sink0_data
wire cmd_demux_src12_ready; // cmd_mux_012:sink0_ready -> cmd_demux:src12_ready
wire [31:0] cmd_demux_src12_channel; // cmd_demux:src12_channel -> cmd_mux_012:sink0_channel
wire cmd_demux_src12_startofpacket; // cmd_demux:src12_startofpacket -> cmd_mux_012:sink0_startofpacket
wire cmd_demux_src12_endofpacket; // cmd_demux:src12_endofpacket -> cmd_mux_012:sink0_endofpacket
wire cmd_demux_src13_valid; // cmd_demux:src13_valid -> cmd_mux_013:sink0_valid
wire [98:0] cmd_demux_src13_data; // cmd_demux:src13_data -> cmd_mux_013:sink0_data
wire cmd_demux_src13_ready; // cmd_mux_013:sink0_ready -> cmd_demux:src13_ready
wire [31:0] cmd_demux_src13_channel; // cmd_demux:src13_channel -> cmd_mux_013:sink0_channel
wire cmd_demux_src13_startofpacket; // cmd_demux:src13_startofpacket -> cmd_mux_013:sink0_startofpacket
wire cmd_demux_src13_endofpacket; // cmd_demux:src13_endofpacket -> cmd_mux_013:sink0_endofpacket
wire cmd_demux_src14_valid; // cmd_demux:src14_valid -> cmd_mux_014:sink0_valid
wire [98:0] cmd_demux_src14_data; // cmd_demux:src14_data -> cmd_mux_014:sink0_data
wire cmd_demux_src14_ready; // cmd_mux_014:sink0_ready -> cmd_demux:src14_ready
wire [31:0] cmd_demux_src14_channel; // cmd_demux:src14_channel -> cmd_mux_014:sink0_channel
wire cmd_demux_src14_startofpacket; // cmd_demux:src14_startofpacket -> cmd_mux_014:sink0_startofpacket
wire cmd_demux_src14_endofpacket; // cmd_demux:src14_endofpacket -> cmd_mux_014:sink0_endofpacket
wire cmd_demux_src15_valid; // cmd_demux:src15_valid -> cmd_mux_015:sink0_valid
wire [98:0] cmd_demux_src15_data; // cmd_demux:src15_data -> cmd_mux_015:sink0_data
wire cmd_demux_src15_ready; // cmd_mux_015:sink0_ready -> cmd_demux:src15_ready
wire [31:0] cmd_demux_src15_channel; // cmd_demux:src15_channel -> cmd_mux_015:sink0_channel
wire cmd_demux_src15_startofpacket; // cmd_demux:src15_startofpacket -> cmd_mux_015:sink0_startofpacket
wire cmd_demux_src15_endofpacket; // cmd_demux:src15_endofpacket -> cmd_mux_015:sink0_endofpacket
wire cmd_demux_src16_valid; // cmd_demux:src16_valid -> cmd_mux_016:sink0_valid
wire [98:0] cmd_demux_src16_data; // cmd_demux:src16_data -> cmd_mux_016:sink0_data
wire cmd_demux_src16_ready; // cmd_mux_016:sink0_ready -> cmd_demux:src16_ready
wire [31:0] cmd_demux_src16_channel; // cmd_demux:src16_channel -> cmd_mux_016:sink0_channel
wire cmd_demux_src16_startofpacket; // cmd_demux:src16_startofpacket -> cmd_mux_016:sink0_startofpacket
wire cmd_demux_src16_endofpacket; // cmd_demux:src16_endofpacket -> cmd_mux_016:sink0_endofpacket
wire cmd_demux_src17_valid; // cmd_demux:src17_valid -> cmd_mux_017:sink0_valid
wire [98:0] cmd_demux_src17_data; // cmd_demux:src17_data -> cmd_mux_017:sink0_data
wire cmd_demux_src17_ready; // cmd_mux_017:sink0_ready -> cmd_demux:src17_ready
wire [31:0] cmd_demux_src17_channel; // cmd_demux:src17_channel -> cmd_mux_017:sink0_channel
wire cmd_demux_src17_startofpacket; // cmd_demux:src17_startofpacket -> cmd_mux_017:sink0_startofpacket
wire cmd_demux_src17_endofpacket; // cmd_demux:src17_endofpacket -> cmd_mux_017:sink0_endofpacket
wire cmd_demux_src18_valid; // cmd_demux:src18_valid -> cmd_mux_018:sink0_valid
wire [98:0] cmd_demux_src18_data; // cmd_demux:src18_data -> cmd_mux_018:sink0_data
wire cmd_demux_src18_ready; // cmd_mux_018:sink0_ready -> cmd_demux:src18_ready
wire [31:0] cmd_demux_src18_channel; // cmd_demux:src18_channel -> cmd_mux_018:sink0_channel
wire cmd_demux_src18_startofpacket; // cmd_demux:src18_startofpacket -> cmd_mux_018:sink0_startofpacket
wire cmd_demux_src18_endofpacket; // cmd_demux:src18_endofpacket -> cmd_mux_018:sink0_endofpacket
wire cmd_demux_src19_valid; // cmd_demux:src19_valid -> cmd_mux_019:sink0_valid
wire [98:0] cmd_demux_src19_data; // cmd_demux:src19_data -> cmd_mux_019:sink0_data
wire cmd_demux_src19_ready; // cmd_mux_019:sink0_ready -> cmd_demux:src19_ready
wire [31:0] cmd_demux_src19_channel; // cmd_demux:src19_channel -> cmd_mux_019:sink0_channel
wire cmd_demux_src19_startofpacket; // cmd_demux:src19_startofpacket -> cmd_mux_019:sink0_startofpacket
wire cmd_demux_src19_endofpacket; // cmd_demux:src19_endofpacket -> cmd_mux_019:sink0_endofpacket
wire cmd_demux_src20_valid; // cmd_demux:src20_valid -> cmd_mux_020:sink0_valid
wire [98:0] cmd_demux_src20_data; // cmd_demux:src20_data -> cmd_mux_020:sink0_data
wire cmd_demux_src20_ready; // cmd_mux_020:sink0_ready -> cmd_demux:src20_ready
wire [31:0] cmd_demux_src20_channel; // cmd_demux:src20_channel -> cmd_mux_020:sink0_channel
wire cmd_demux_src20_startofpacket; // cmd_demux:src20_startofpacket -> cmd_mux_020:sink0_startofpacket
wire cmd_demux_src20_endofpacket; // cmd_demux:src20_endofpacket -> cmd_mux_020:sink0_endofpacket
wire cmd_demux_src21_valid; // cmd_demux:src21_valid -> cmd_mux_021:sink0_valid
wire [98:0] cmd_demux_src21_data; // cmd_demux:src21_data -> cmd_mux_021:sink0_data
wire cmd_demux_src21_ready; // cmd_mux_021:sink0_ready -> cmd_demux:src21_ready
wire [31:0] cmd_demux_src21_channel; // cmd_demux:src21_channel -> cmd_mux_021:sink0_channel
wire cmd_demux_src21_startofpacket; // cmd_demux:src21_startofpacket -> cmd_mux_021:sink0_startofpacket
wire cmd_demux_src21_endofpacket; // cmd_demux:src21_endofpacket -> cmd_mux_021:sink0_endofpacket
wire cmd_demux_src22_valid; // cmd_demux:src22_valid -> cmd_mux_022:sink0_valid
wire [98:0] cmd_demux_src22_data; // cmd_demux:src22_data -> cmd_mux_022:sink0_data
wire cmd_demux_src22_ready; // cmd_mux_022:sink0_ready -> cmd_demux:src22_ready
wire [31:0] cmd_demux_src22_channel; // cmd_demux:src22_channel -> cmd_mux_022:sink0_channel
wire cmd_demux_src22_startofpacket; // cmd_demux:src22_startofpacket -> cmd_mux_022:sink0_startofpacket
wire cmd_demux_src22_endofpacket; // cmd_demux:src22_endofpacket -> cmd_mux_022:sink0_endofpacket
wire cmd_demux_src23_valid; // cmd_demux:src23_valid -> cmd_mux_023:sink0_valid
wire [98:0] cmd_demux_src23_data; // cmd_demux:src23_data -> cmd_mux_023:sink0_data
wire cmd_demux_src23_ready; // cmd_mux_023:sink0_ready -> cmd_demux:src23_ready
wire [31:0] cmd_demux_src23_channel; // cmd_demux:src23_channel -> cmd_mux_023:sink0_channel
wire cmd_demux_src23_startofpacket; // cmd_demux:src23_startofpacket -> cmd_mux_023:sink0_startofpacket
wire cmd_demux_src23_endofpacket; // cmd_demux:src23_endofpacket -> cmd_mux_023:sink0_endofpacket
wire cmd_demux_src24_valid; // cmd_demux:src24_valid -> cmd_mux_024:sink0_valid
wire [98:0] cmd_demux_src24_data; // cmd_demux:src24_data -> cmd_mux_024:sink0_data
wire cmd_demux_src24_ready; // cmd_mux_024:sink0_ready -> cmd_demux:src24_ready
wire [31:0] cmd_demux_src24_channel; // cmd_demux:src24_channel -> cmd_mux_024:sink0_channel
wire cmd_demux_src24_startofpacket; // cmd_demux:src24_startofpacket -> cmd_mux_024:sink0_startofpacket
wire cmd_demux_src24_endofpacket; // cmd_demux:src24_endofpacket -> cmd_mux_024:sink0_endofpacket
wire cmd_demux_src25_valid; // cmd_demux:src25_valid -> cmd_mux_025:sink0_valid
wire [98:0] cmd_demux_src25_data; // cmd_demux:src25_data -> cmd_mux_025:sink0_data
wire cmd_demux_src25_ready; // cmd_mux_025:sink0_ready -> cmd_demux:src25_ready
wire [31:0] cmd_demux_src25_channel; // cmd_demux:src25_channel -> cmd_mux_025:sink0_channel
wire cmd_demux_src25_startofpacket; // cmd_demux:src25_startofpacket -> cmd_mux_025:sink0_startofpacket
wire cmd_demux_src25_endofpacket; // cmd_demux:src25_endofpacket -> cmd_mux_025:sink0_endofpacket
wire cmd_demux_src26_valid; // cmd_demux:src26_valid -> cmd_mux_026:sink0_valid
wire [98:0] cmd_demux_src26_data; // cmd_demux:src26_data -> cmd_mux_026:sink0_data
wire cmd_demux_src26_ready; // cmd_mux_026:sink0_ready -> cmd_demux:src26_ready
wire [31:0] cmd_demux_src26_channel; // cmd_demux:src26_channel -> cmd_mux_026:sink0_channel
wire cmd_demux_src26_startofpacket; // cmd_demux:src26_startofpacket -> cmd_mux_026:sink0_startofpacket
wire cmd_demux_src26_endofpacket; // cmd_demux:src26_endofpacket -> cmd_mux_026:sink0_endofpacket
wire cmd_demux_src27_valid; // cmd_demux:src27_valid -> cmd_mux_027:sink0_valid
wire [98:0] cmd_demux_src27_data; // cmd_demux:src27_data -> cmd_mux_027:sink0_data
wire cmd_demux_src27_ready; // cmd_mux_027:sink0_ready -> cmd_demux:src27_ready
wire [31:0] cmd_demux_src27_channel; // cmd_demux:src27_channel -> cmd_mux_027:sink0_channel
wire cmd_demux_src27_startofpacket; // cmd_demux:src27_startofpacket -> cmd_mux_027:sink0_startofpacket
wire cmd_demux_src27_endofpacket; // cmd_demux:src27_endofpacket -> cmd_mux_027:sink0_endofpacket
wire cmd_demux_src28_valid; // cmd_demux:src28_valid -> cmd_mux_028:sink0_valid
wire [98:0] cmd_demux_src28_data; // cmd_demux:src28_data -> cmd_mux_028:sink0_data
wire cmd_demux_src28_ready; // cmd_mux_028:sink0_ready -> cmd_demux:src28_ready
wire [31:0] cmd_demux_src28_channel; // cmd_demux:src28_channel -> cmd_mux_028:sink0_channel
wire cmd_demux_src28_startofpacket; // cmd_demux:src28_startofpacket -> cmd_mux_028:sink0_startofpacket
wire cmd_demux_src28_endofpacket; // cmd_demux:src28_endofpacket -> cmd_mux_028:sink0_endofpacket
wire cmd_demux_src29_valid; // cmd_demux:src29_valid -> cmd_mux_029:sink0_valid
wire [98:0] cmd_demux_src29_data; // cmd_demux:src29_data -> cmd_mux_029:sink0_data
wire cmd_demux_src29_ready; // cmd_mux_029:sink0_ready -> cmd_demux:src29_ready
wire [31:0] cmd_demux_src29_channel; // cmd_demux:src29_channel -> cmd_mux_029:sink0_channel
wire cmd_demux_src29_startofpacket; // cmd_demux:src29_startofpacket -> cmd_mux_029:sink0_startofpacket
wire cmd_demux_src29_endofpacket; // cmd_demux:src29_endofpacket -> cmd_mux_029:sink0_endofpacket
wire cmd_demux_src30_valid; // cmd_demux:src30_valid -> cmd_mux_030:sink0_valid
wire [98:0] cmd_demux_src30_data; // cmd_demux:src30_data -> cmd_mux_030:sink0_data
wire cmd_demux_src30_ready; // cmd_mux_030:sink0_ready -> cmd_demux:src30_ready
wire [31:0] cmd_demux_src30_channel; // cmd_demux:src30_channel -> cmd_mux_030:sink0_channel
wire cmd_demux_src30_startofpacket; // cmd_demux:src30_startofpacket -> cmd_mux_030:sink0_startofpacket
wire cmd_demux_src30_endofpacket; // cmd_demux:src30_endofpacket -> cmd_mux_030:sink0_endofpacket
wire cmd_demux_src31_valid; // cmd_demux:src31_valid -> cmd_mux_031:sink0_valid
wire [98:0] cmd_demux_src31_data; // cmd_demux:src31_data -> cmd_mux_031:sink0_data
wire cmd_demux_src31_ready; // cmd_mux_031:sink0_ready -> cmd_demux:src31_ready
wire [31:0] cmd_demux_src31_channel; // cmd_demux:src31_channel -> cmd_mux_031:sink0_channel
wire cmd_demux_src31_startofpacket; // cmd_demux:src31_startofpacket -> cmd_mux_031:sink0_startofpacket
wire cmd_demux_src31_endofpacket; // cmd_demux:src31_endofpacket -> cmd_mux_031:sink0_endofpacket
wire cmd_demux_001_src0_valid; // cmd_demux_001:src0_valid -> cmd_mux_001:sink1_valid
wire [98:0] cmd_demux_001_src0_data; // cmd_demux_001:src0_data -> cmd_mux_001:sink1_data
wire cmd_demux_001_src0_ready; // cmd_mux_001:sink1_ready -> cmd_demux_001:src0_ready
wire [31:0] cmd_demux_001_src0_channel; // cmd_demux_001:src0_channel -> cmd_mux_001:sink1_channel
wire cmd_demux_001_src0_startofpacket; // cmd_demux_001:src0_startofpacket -> cmd_mux_001:sink1_startofpacket
wire cmd_demux_001_src0_endofpacket; // cmd_demux_001:src0_endofpacket -> cmd_mux_001:sink1_endofpacket
wire cmd_demux_001_src1_valid; // cmd_demux_001:src1_valid -> cmd_mux_002:sink1_valid
wire [98:0] cmd_demux_001_src1_data; // cmd_demux_001:src1_data -> cmd_mux_002:sink1_data
wire cmd_demux_001_src1_ready; // cmd_mux_002:sink1_ready -> cmd_demux_001:src1_ready
wire [31:0] cmd_demux_001_src1_channel; // cmd_demux_001:src1_channel -> cmd_mux_002:sink1_channel
wire cmd_demux_001_src1_startofpacket; // cmd_demux_001:src1_startofpacket -> cmd_mux_002:sink1_startofpacket
wire cmd_demux_001_src1_endofpacket; // cmd_demux_001:src1_endofpacket -> cmd_mux_002:sink1_endofpacket
wire rsp_demux_src0_valid; // rsp_demux:src0_valid -> rsp_mux:sink0_valid
wire [98:0] rsp_demux_src0_data; // rsp_demux:src0_data -> rsp_mux:sink0_data
wire rsp_demux_src0_ready; // rsp_mux:sink0_ready -> rsp_demux:src0_ready
wire [31:0] rsp_demux_src0_channel; // rsp_demux:src0_channel -> rsp_mux:sink0_channel
wire rsp_demux_src0_startofpacket; // rsp_demux:src0_startofpacket -> rsp_mux:sink0_startofpacket
wire rsp_demux_src0_endofpacket; // rsp_demux:src0_endofpacket -> rsp_mux:sink0_endofpacket
wire rsp_demux_001_src0_valid; // rsp_demux_001:src0_valid -> rsp_mux:sink1_valid
wire [98:0] rsp_demux_001_src0_data; // rsp_demux_001:src0_data -> rsp_mux:sink1_data
wire rsp_demux_001_src0_ready; // rsp_mux:sink1_ready -> rsp_demux_001:src0_ready
wire [31:0] rsp_demux_001_src0_channel; // rsp_demux_001:src0_channel -> rsp_mux:sink1_channel
wire rsp_demux_001_src0_startofpacket; // rsp_demux_001:src0_startofpacket -> rsp_mux:sink1_startofpacket
wire rsp_demux_001_src0_endofpacket; // rsp_demux_001:src0_endofpacket -> rsp_mux:sink1_endofpacket
wire rsp_demux_001_src1_valid; // rsp_demux_001:src1_valid -> rsp_mux_001:sink0_valid
wire [98:0] rsp_demux_001_src1_data; // rsp_demux_001:src1_data -> rsp_mux_001:sink0_data
wire rsp_demux_001_src1_ready; // rsp_mux_001:sink0_ready -> rsp_demux_001:src1_ready
wire [31:0] rsp_demux_001_src1_channel; // rsp_demux_001:src1_channel -> rsp_mux_001:sink0_channel
wire rsp_demux_001_src1_startofpacket; // rsp_demux_001:src1_startofpacket -> rsp_mux_001:sink0_startofpacket
wire rsp_demux_001_src1_endofpacket; // rsp_demux_001:src1_endofpacket -> rsp_mux_001:sink0_endofpacket
wire rsp_demux_002_src0_valid; // rsp_demux_002:src0_valid -> rsp_mux:sink2_valid
wire [98:0] rsp_demux_002_src0_data; // rsp_demux_002:src0_data -> rsp_mux:sink2_data
wire rsp_demux_002_src0_ready; // rsp_mux:sink2_ready -> rsp_demux_002:src0_ready
wire [31:0] rsp_demux_002_src0_channel; // rsp_demux_002:src0_channel -> rsp_mux:sink2_channel
wire rsp_demux_002_src0_startofpacket; // rsp_demux_002:src0_startofpacket -> rsp_mux:sink2_startofpacket
wire rsp_demux_002_src0_endofpacket; // rsp_demux_002:src0_endofpacket -> rsp_mux:sink2_endofpacket
wire rsp_demux_002_src1_valid; // rsp_demux_002:src1_valid -> rsp_mux_001:sink1_valid
wire [98:0] rsp_demux_002_src1_data; // rsp_demux_002:src1_data -> rsp_mux_001:sink1_data
wire rsp_demux_002_src1_ready; // rsp_mux_001:sink1_ready -> rsp_demux_002:src1_ready
wire [31:0] rsp_demux_002_src1_channel; // rsp_demux_002:src1_channel -> rsp_mux_001:sink1_channel
wire rsp_demux_002_src1_startofpacket; // rsp_demux_002:src1_startofpacket -> rsp_mux_001:sink1_startofpacket
wire rsp_demux_002_src1_endofpacket; // rsp_demux_002:src1_endofpacket -> rsp_mux_001:sink1_endofpacket
wire rsp_demux_003_src0_valid; // rsp_demux_003:src0_valid -> rsp_mux:sink3_valid
wire [98:0] rsp_demux_003_src0_data; // rsp_demux_003:src0_data -> rsp_mux:sink3_data
wire rsp_demux_003_src0_ready; // rsp_mux:sink3_ready -> rsp_demux_003:src0_ready
wire [31:0] rsp_demux_003_src0_channel; // rsp_demux_003:src0_channel -> rsp_mux:sink3_channel
wire rsp_demux_003_src0_startofpacket; // rsp_demux_003:src0_startofpacket -> rsp_mux:sink3_startofpacket
wire rsp_demux_003_src0_endofpacket; // rsp_demux_003:src0_endofpacket -> rsp_mux:sink3_endofpacket
wire rsp_demux_004_src0_valid; // rsp_demux_004:src0_valid -> rsp_mux:sink4_valid
wire [98:0] rsp_demux_004_src0_data; // rsp_demux_004:src0_data -> rsp_mux:sink4_data
wire rsp_demux_004_src0_ready; // rsp_mux:sink4_ready -> rsp_demux_004:src0_ready
wire [31:0] rsp_demux_004_src0_channel; // rsp_demux_004:src0_channel -> rsp_mux:sink4_channel
wire rsp_demux_004_src0_startofpacket; // rsp_demux_004:src0_startofpacket -> rsp_mux:sink4_startofpacket
wire rsp_demux_004_src0_endofpacket; // rsp_demux_004:src0_endofpacket -> rsp_mux:sink4_endofpacket
wire rsp_demux_005_src0_valid; // rsp_demux_005:src0_valid -> rsp_mux:sink5_valid
wire [98:0] rsp_demux_005_src0_data; // rsp_demux_005:src0_data -> rsp_mux:sink5_data
wire rsp_demux_005_src0_ready; // rsp_mux:sink5_ready -> rsp_demux_005:src0_ready
wire [31:0] rsp_demux_005_src0_channel; // rsp_demux_005:src0_channel -> rsp_mux:sink5_channel
wire rsp_demux_005_src0_startofpacket; // rsp_demux_005:src0_startofpacket -> rsp_mux:sink5_startofpacket
wire rsp_demux_005_src0_endofpacket; // rsp_demux_005:src0_endofpacket -> rsp_mux:sink5_endofpacket
wire rsp_demux_006_src0_valid; // rsp_demux_006:src0_valid -> rsp_mux:sink6_valid
wire [98:0] rsp_demux_006_src0_data; // rsp_demux_006:src0_data -> rsp_mux:sink6_data
wire rsp_demux_006_src0_ready; // rsp_mux:sink6_ready -> rsp_demux_006:src0_ready
wire [31:0] rsp_demux_006_src0_channel; // rsp_demux_006:src0_channel -> rsp_mux:sink6_channel
wire rsp_demux_006_src0_startofpacket; // rsp_demux_006:src0_startofpacket -> rsp_mux:sink6_startofpacket
wire rsp_demux_006_src0_endofpacket; // rsp_demux_006:src0_endofpacket -> rsp_mux:sink6_endofpacket
wire rsp_demux_007_src0_valid; // rsp_demux_007:src0_valid -> rsp_mux:sink7_valid
wire [98:0] rsp_demux_007_src0_data; // rsp_demux_007:src0_data -> rsp_mux:sink7_data
wire rsp_demux_007_src0_ready; // rsp_mux:sink7_ready -> rsp_demux_007:src0_ready
wire [31:0] rsp_demux_007_src0_channel; // rsp_demux_007:src0_channel -> rsp_mux:sink7_channel
wire rsp_demux_007_src0_startofpacket; // rsp_demux_007:src0_startofpacket -> rsp_mux:sink7_startofpacket
wire rsp_demux_007_src0_endofpacket; // rsp_demux_007:src0_endofpacket -> rsp_mux:sink7_endofpacket
wire rsp_demux_008_src0_valid; // rsp_demux_008:src0_valid -> rsp_mux:sink8_valid
wire [98:0] rsp_demux_008_src0_data; // rsp_demux_008:src0_data -> rsp_mux:sink8_data
wire rsp_demux_008_src0_ready; // rsp_mux:sink8_ready -> rsp_demux_008:src0_ready
wire [31:0] rsp_demux_008_src0_channel; // rsp_demux_008:src0_channel -> rsp_mux:sink8_channel
wire rsp_demux_008_src0_startofpacket; // rsp_demux_008:src0_startofpacket -> rsp_mux:sink8_startofpacket
wire rsp_demux_008_src0_endofpacket; // rsp_demux_008:src0_endofpacket -> rsp_mux:sink8_endofpacket
wire rsp_demux_009_src0_valid; // rsp_demux_009:src0_valid -> rsp_mux:sink9_valid
wire [98:0] rsp_demux_009_src0_data; // rsp_demux_009:src0_data -> rsp_mux:sink9_data
wire rsp_demux_009_src0_ready; // rsp_mux:sink9_ready -> rsp_demux_009:src0_ready
wire [31:0] rsp_demux_009_src0_channel; // rsp_demux_009:src0_channel -> rsp_mux:sink9_channel
wire rsp_demux_009_src0_startofpacket; // rsp_demux_009:src0_startofpacket -> rsp_mux:sink9_startofpacket
wire rsp_demux_009_src0_endofpacket; // rsp_demux_009:src0_endofpacket -> rsp_mux:sink9_endofpacket
wire rsp_demux_010_src0_valid; // rsp_demux_010:src0_valid -> rsp_mux:sink10_valid
wire [98:0] rsp_demux_010_src0_data; // rsp_demux_010:src0_data -> rsp_mux:sink10_data
wire rsp_demux_010_src0_ready; // rsp_mux:sink10_ready -> rsp_demux_010:src0_ready
wire [31:0] rsp_demux_010_src0_channel; // rsp_demux_010:src0_channel -> rsp_mux:sink10_channel
wire rsp_demux_010_src0_startofpacket; // rsp_demux_010:src0_startofpacket -> rsp_mux:sink10_startofpacket
wire rsp_demux_010_src0_endofpacket; // rsp_demux_010:src0_endofpacket -> rsp_mux:sink10_endofpacket
wire rsp_demux_011_src0_valid; // rsp_demux_011:src0_valid -> rsp_mux:sink11_valid
wire [98:0] rsp_demux_011_src0_data; // rsp_demux_011:src0_data -> rsp_mux:sink11_data
wire rsp_demux_011_src0_ready; // rsp_mux:sink11_ready -> rsp_demux_011:src0_ready
wire [31:0] rsp_demux_011_src0_channel; // rsp_demux_011:src0_channel -> rsp_mux:sink11_channel
wire rsp_demux_011_src0_startofpacket; // rsp_demux_011:src0_startofpacket -> rsp_mux:sink11_startofpacket
wire rsp_demux_011_src0_endofpacket; // rsp_demux_011:src0_endofpacket -> rsp_mux:sink11_endofpacket
wire rsp_demux_012_src0_valid; // rsp_demux_012:src0_valid -> rsp_mux:sink12_valid
wire [98:0] rsp_demux_012_src0_data; // rsp_demux_012:src0_data -> rsp_mux:sink12_data
wire rsp_demux_012_src0_ready; // rsp_mux:sink12_ready -> rsp_demux_012:src0_ready
wire [31:0] rsp_demux_012_src0_channel; // rsp_demux_012:src0_channel -> rsp_mux:sink12_channel
wire rsp_demux_012_src0_startofpacket; // rsp_demux_012:src0_startofpacket -> rsp_mux:sink12_startofpacket
wire rsp_demux_012_src0_endofpacket; // rsp_demux_012:src0_endofpacket -> rsp_mux:sink12_endofpacket
wire rsp_demux_013_src0_valid; // rsp_demux_013:src0_valid -> rsp_mux:sink13_valid
wire [98:0] rsp_demux_013_src0_data; // rsp_demux_013:src0_data -> rsp_mux:sink13_data
wire rsp_demux_013_src0_ready; // rsp_mux:sink13_ready -> rsp_demux_013:src0_ready
wire [31:0] rsp_demux_013_src0_channel; // rsp_demux_013:src0_channel -> rsp_mux:sink13_channel
wire rsp_demux_013_src0_startofpacket; // rsp_demux_013:src0_startofpacket -> rsp_mux:sink13_startofpacket
wire rsp_demux_013_src0_endofpacket; // rsp_demux_013:src0_endofpacket -> rsp_mux:sink13_endofpacket
wire rsp_demux_014_src0_valid; // rsp_demux_014:src0_valid -> rsp_mux:sink14_valid
wire [98:0] rsp_demux_014_src0_data; // rsp_demux_014:src0_data -> rsp_mux:sink14_data
wire rsp_demux_014_src0_ready; // rsp_mux:sink14_ready -> rsp_demux_014:src0_ready
wire [31:0] rsp_demux_014_src0_channel; // rsp_demux_014:src0_channel -> rsp_mux:sink14_channel
wire rsp_demux_014_src0_startofpacket; // rsp_demux_014:src0_startofpacket -> rsp_mux:sink14_startofpacket
wire rsp_demux_014_src0_endofpacket; // rsp_demux_014:src0_endofpacket -> rsp_mux:sink14_endofpacket
wire rsp_demux_015_src0_valid; // rsp_demux_015:src0_valid -> rsp_mux:sink15_valid
wire [98:0] rsp_demux_015_src0_data; // rsp_demux_015:src0_data -> rsp_mux:sink15_data
wire rsp_demux_015_src0_ready; // rsp_mux:sink15_ready -> rsp_demux_015:src0_ready
wire [31:0] rsp_demux_015_src0_channel; // rsp_demux_015:src0_channel -> rsp_mux:sink15_channel
wire rsp_demux_015_src0_startofpacket; // rsp_demux_015:src0_startofpacket -> rsp_mux:sink15_startofpacket
wire rsp_demux_015_src0_endofpacket; // rsp_demux_015:src0_endofpacket -> rsp_mux:sink15_endofpacket
wire rsp_demux_016_src0_valid; // rsp_demux_016:src0_valid -> rsp_mux:sink16_valid
wire [98:0] rsp_demux_016_src0_data; // rsp_demux_016:src0_data -> rsp_mux:sink16_data
wire rsp_demux_016_src0_ready; // rsp_mux:sink16_ready -> rsp_demux_016:src0_ready
wire [31:0] rsp_demux_016_src0_channel; // rsp_demux_016:src0_channel -> rsp_mux:sink16_channel
wire rsp_demux_016_src0_startofpacket; // rsp_demux_016:src0_startofpacket -> rsp_mux:sink16_startofpacket
wire rsp_demux_016_src0_endofpacket; // rsp_demux_016:src0_endofpacket -> rsp_mux:sink16_endofpacket
wire rsp_demux_017_src0_valid; // rsp_demux_017:src0_valid -> rsp_mux:sink17_valid
wire [98:0] rsp_demux_017_src0_data; // rsp_demux_017:src0_data -> rsp_mux:sink17_data
wire rsp_demux_017_src0_ready; // rsp_mux:sink17_ready -> rsp_demux_017:src0_ready
wire [31:0] rsp_demux_017_src0_channel; // rsp_demux_017:src0_channel -> rsp_mux:sink17_channel
wire rsp_demux_017_src0_startofpacket; // rsp_demux_017:src0_startofpacket -> rsp_mux:sink17_startofpacket
wire rsp_demux_017_src0_endofpacket; // rsp_demux_017:src0_endofpacket -> rsp_mux:sink17_endofpacket
wire rsp_demux_018_src0_valid; // rsp_demux_018:src0_valid -> rsp_mux:sink18_valid
wire [98:0] rsp_demux_018_src0_data; // rsp_demux_018:src0_data -> rsp_mux:sink18_data
wire rsp_demux_018_src0_ready; // rsp_mux:sink18_ready -> rsp_demux_018:src0_ready
wire [31:0] rsp_demux_018_src0_channel; // rsp_demux_018:src0_channel -> rsp_mux:sink18_channel
wire rsp_demux_018_src0_startofpacket; // rsp_demux_018:src0_startofpacket -> rsp_mux:sink18_startofpacket
wire rsp_demux_018_src0_endofpacket; // rsp_demux_018:src0_endofpacket -> rsp_mux:sink18_endofpacket
wire rsp_demux_019_src0_valid; // rsp_demux_019:src0_valid -> rsp_mux:sink19_valid
wire [98:0] rsp_demux_019_src0_data; // rsp_demux_019:src0_data -> rsp_mux:sink19_data
wire rsp_demux_019_src0_ready; // rsp_mux:sink19_ready -> rsp_demux_019:src0_ready
wire [31:0] rsp_demux_019_src0_channel; // rsp_demux_019:src0_channel -> rsp_mux:sink19_channel
wire rsp_demux_019_src0_startofpacket; // rsp_demux_019:src0_startofpacket -> rsp_mux:sink19_startofpacket
wire rsp_demux_019_src0_endofpacket; // rsp_demux_019:src0_endofpacket -> rsp_mux:sink19_endofpacket
wire rsp_demux_020_src0_valid; // rsp_demux_020:src0_valid -> rsp_mux:sink20_valid
wire [98:0] rsp_demux_020_src0_data; // rsp_demux_020:src0_data -> rsp_mux:sink20_data
wire rsp_demux_020_src0_ready; // rsp_mux:sink20_ready -> rsp_demux_020:src0_ready
wire [31:0] rsp_demux_020_src0_channel; // rsp_demux_020:src0_channel -> rsp_mux:sink20_channel
wire rsp_demux_020_src0_startofpacket; // rsp_demux_020:src0_startofpacket -> rsp_mux:sink20_startofpacket
wire rsp_demux_020_src0_endofpacket; // rsp_demux_020:src0_endofpacket -> rsp_mux:sink20_endofpacket
wire rsp_demux_021_src0_valid; // rsp_demux_021:src0_valid -> rsp_mux:sink21_valid
wire [98:0] rsp_demux_021_src0_data; // rsp_demux_021:src0_data -> rsp_mux:sink21_data
wire rsp_demux_021_src0_ready; // rsp_mux:sink21_ready -> rsp_demux_021:src0_ready
wire [31:0] rsp_demux_021_src0_channel; // rsp_demux_021:src0_channel -> rsp_mux:sink21_channel
wire rsp_demux_021_src0_startofpacket; // rsp_demux_021:src0_startofpacket -> rsp_mux:sink21_startofpacket
wire rsp_demux_021_src0_endofpacket; // rsp_demux_021:src0_endofpacket -> rsp_mux:sink21_endofpacket
wire rsp_demux_022_src0_valid; // rsp_demux_022:src0_valid -> rsp_mux:sink22_valid
wire [98:0] rsp_demux_022_src0_data; // rsp_demux_022:src0_data -> rsp_mux:sink22_data
wire rsp_demux_022_src0_ready; // rsp_mux:sink22_ready -> rsp_demux_022:src0_ready
wire [31:0] rsp_demux_022_src0_channel; // rsp_demux_022:src0_channel -> rsp_mux:sink22_channel
wire rsp_demux_022_src0_startofpacket; // rsp_demux_022:src0_startofpacket -> rsp_mux:sink22_startofpacket
wire rsp_demux_022_src0_endofpacket; // rsp_demux_022:src0_endofpacket -> rsp_mux:sink22_endofpacket
wire rsp_demux_023_src0_valid; // rsp_demux_023:src0_valid -> rsp_mux:sink23_valid
wire [98:0] rsp_demux_023_src0_data; // rsp_demux_023:src0_data -> rsp_mux:sink23_data
wire rsp_demux_023_src0_ready; // rsp_mux:sink23_ready -> rsp_demux_023:src0_ready
wire [31:0] rsp_demux_023_src0_channel; // rsp_demux_023:src0_channel -> rsp_mux:sink23_channel
wire rsp_demux_023_src0_startofpacket; // rsp_demux_023:src0_startofpacket -> rsp_mux:sink23_startofpacket
wire rsp_demux_023_src0_endofpacket; // rsp_demux_023:src0_endofpacket -> rsp_mux:sink23_endofpacket
wire rsp_demux_024_src0_valid; // rsp_demux_024:src0_valid -> rsp_mux:sink24_valid
wire [98:0] rsp_demux_024_src0_data; // rsp_demux_024:src0_data -> rsp_mux:sink24_data
wire rsp_demux_024_src0_ready; // rsp_mux:sink24_ready -> rsp_demux_024:src0_ready
wire [31:0] rsp_demux_024_src0_channel; // rsp_demux_024:src0_channel -> rsp_mux:sink24_channel
wire rsp_demux_024_src0_startofpacket; // rsp_demux_024:src0_startofpacket -> rsp_mux:sink24_startofpacket
wire rsp_demux_024_src0_endofpacket; // rsp_demux_024:src0_endofpacket -> rsp_mux:sink24_endofpacket
wire rsp_demux_025_src0_valid; // rsp_demux_025:src0_valid -> rsp_mux:sink25_valid
wire [98:0] rsp_demux_025_src0_data; // rsp_demux_025:src0_data -> rsp_mux:sink25_data
wire rsp_demux_025_src0_ready; // rsp_mux:sink25_ready -> rsp_demux_025:src0_ready
wire [31:0] rsp_demux_025_src0_channel; // rsp_demux_025:src0_channel -> rsp_mux:sink25_channel
wire rsp_demux_025_src0_startofpacket; // rsp_demux_025:src0_startofpacket -> rsp_mux:sink25_startofpacket
wire rsp_demux_025_src0_endofpacket; // rsp_demux_025:src0_endofpacket -> rsp_mux:sink25_endofpacket
wire rsp_demux_026_src0_valid; // rsp_demux_026:src0_valid -> rsp_mux:sink26_valid
wire [98:0] rsp_demux_026_src0_data; // rsp_demux_026:src0_data -> rsp_mux:sink26_data
wire rsp_demux_026_src0_ready; // rsp_mux:sink26_ready -> rsp_demux_026:src0_ready
wire [31:0] rsp_demux_026_src0_channel; // rsp_demux_026:src0_channel -> rsp_mux:sink26_channel
wire rsp_demux_026_src0_startofpacket; // rsp_demux_026:src0_startofpacket -> rsp_mux:sink26_startofpacket
wire rsp_demux_026_src0_endofpacket; // rsp_demux_026:src0_endofpacket -> rsp_mux:sink26_endofpacket
wire rsp_demux_027_src0_valid; // rsp_demux_027:src0_valid -> rsp_mux:sink27_valid
wire [98:0] rsp_demux_027_src0_data; // rsp_demux_027:src0_data -> rsp_mux:sink27_data
wire rsp_demux_027_src0_ready; // rsp_mux:sink27_ready -> rsp_demux_027:src0_ready
wire [31:0] rsp_demux_027_src0_channel; // rsp_demux_027:src0_channel -> rsp_mux:sink27_channel
wire rsp_demux_027_src0_startofpacket; // rsp_demux_027:src0_startofpacket -> rsp_mux:sink27_startofpacket
wire rsp_demux_027_src0_endofpacket; // rsp_demux_027:src0_endofpacket -> rsp_mux:sink27_endofpacket
wire rsp_demux_028_src0_valid; // rsp_demux_028:src0_valid -> rsp_mux:sink28_valid
wire [98:0] rsp_demux_028_src0_data; // rsp_demux_028:src0_data -> rsp_mux:sink28_data
wire rsp_demux_028_src0_ready; // rsp_mux:sink28_ready -> rsp_demux_028:src0_ready
wire [31:0] rsp_demux_028_src0_channel; // rsp_demux_028:src0_channel -> rsp_mux:sink28_channel
wire rsp_demux_028_src0_startofpacket; // rsp_demux_028:src0_startofpacket -> rsp_mux:sink28_startofpacket
wire rsp_demux_028_src0_endofpacket; // rsp_demux_028:src0_endofpacket -> rsp_mux:sink28_endofpacket
wire rsp_demux_029_src0_valid; // rsp_demux_029:src0_valid -> rsp_mux:sink29_valid
wire [98:0] rsp_demux_029_src0_data; // rsp_demux_029:src0_data -> rsp_mux:sink29_data
wire rsp_demux_029_src0_ready; // rsp_mux:sink29_ready -> rsp_demux_029:src0_ready
wire [31:0] rsp_demux_029_src0_channel; // rsp_demux_029:src0_channel -> rsp_mux:sink29_channel
wire rsp_demux_029_src0_startofpacket; // rsp_demux_029:src0_startofpacket -> rsp_mux:sink29_startofpacket
wire rsp_demux_029_src0_endofpacket; // rsp_demux_029:src0_endofpacket -> rsp_mux:sink29_endofpacket
wire rsp_demux_030_src0_valid; // rsp_demux_030:src0_valid -> rsp_mux:sink30_valid
wire [98:0] rsp_demux_030_src0_data; // rsp_demux_030:src0_data -> rsp_mux:sink30_data
wire rsp_demux_030_src0_ready; // rsp_mux:sink30_ready -> rsp_demux_030:src0_ready
wire [31:0] rsp_demux_030_src0_channel; // rsp_demux_030:src0_channel -> rsp_mux:sink30_channel
wire rsp_demux_030_src0_startofpacket; // rsp_demux_030:src0_startofpacket -> rsp_mux:sink30_startofpacket
wire rsp_demux_030_src0_endofpacket; // rsp_demux_030:src0_endofpacket -> rsp_mux:sink30_endofpacket
wire rsp_demux_031_src0_valid; // rsp_demux_031:src0_valid -> rsp_mux:sink31_valid
wire [98:0] rsp_demux_031_src0_data; // rsp_demux_031:src0_data -> rsp_mux:sink31_data
wire rsp_demux_031_src0_ready; // rsp_mux:sink31_ready -> rsp_demux_031:src0_ready
wire [31:0] rsp_demux_031_src0_channel; // rsp_demux_031:src0_channel -> rsp_mux:sink31_channel
wire rsp_demux_031_src0_startofpacket; // rsp_demux_031:src0_startofpacket -> rsp_mux:sink31_startofpacket
wire rsp_demux_031_src0_endofpacket; // rsp_demux_031:src0_endofpacket -> rsp_mux:sink31_endofpacket
altera_merlin_master_translator #(
.AV_ADDRESS_W (19),
.AV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (19),
.UAV_BURSTCOUNT_W (3),
.USE_READ (1),
.USE_WRITE (1),
.USE_BEGINBURSTTRANSFER (0),
.USE_BEGINTRANSFER (0),
.USE_CHIPSELECT (0),
.USE_BURSTCOUNT (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (1),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_LINEWRAPBURSTS (0),
.AV_REGISTERINCOMINGSIGNALS (1)
) nios2_qsys_0_data_master_translator (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (nios2_qsys_0_data_master_translator_avalon_universal_master_0_address), // avalon_universal_master_0.address
.uav_burstcount (nios2_qsys_0_data_master_translator_avalon_universal_master_0_burstcount), // .burstcount
.uav_read (nios2_qsys_0_data_master_translator_avalon_universal_master_0_read), // .read
.uav_write (nios2_qsys_0_data_master_translator_avalon_universal_master_0_write), // .write
.uav_waitrequest (nios2_qsys_0_data_master_translator_avalon_universal_master_0_waitrequest), // .waitrequest
.uav_readdatavalid (nios2_qsys_0_data_master_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
.uav_byteenable (nios2_qsys_0_data_master_translator_avalon_universal_master_0_byteenable), // .byteenable
.uav_readdata (nios2_qsys_0_data_master_translator_avalon_universal_master_0_readdata), // .readdata
.uav_writedata (nios2_qsys_0_data_master_translator_avalon_universal_master_0_writedata), // .writedata
.uav_lock (nios2_qsys_0_data_master_translator_avalon_universal_master_0_lock), // .lock
.uav_debugaccess (nios2_qsys_0_data_master_translator_avalon_universal_master_0_debugaccess), // .debugaccess
.av_address (nios2_qsys_0_data_master_address), // avalon_anti_master_0.address
.av_waitrequest (nios2_qsys_0_data_master_waitrequest), // .waitrequest
.av_byteenable (nios2_qsys_0_data_master_byteenable), // .byteenable
.av_read (nios2_qsys_0_data_master_read), // .read
.av_readdata (nios2_qsys_0_data_master_readdata), // .readdata
.av_write (nios2_qsys_0_data_master_write), // .write
.av_writedata (nios2_qsys_0_data_master_writedata), // .writedata
.av_debugaccess (nios2_qsys_0_data_master_debugaccess), // .debugaccess
.av_burstcount (1'b1), // (terminated)
.av_beginbursttransfer (1'b0), // (terminated)
.av_begintransfer (1'b0), // (terminated)
.av_chipselect (1'b0), // (terminated)
.av_readdatavalid (), // (terminated)
.av_lock (1'b0), // (terminated)
.uav_clken (), // (terminated)
.av_clken (1'b1), // (terminated)
.uav_response (2'b00), // (terminated)
.av_response (), // (terminated)
.uav_writeresponsevalid (1'b0), // (terminated)
.av_writeresponsevalid () // (terminated)
);
altera_merlin_master_translator #(
.AV_ADDRESS_W (19),
.AV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (19),
.UAV_BURSTCOUNT_W (3),
.USE_READ (1),
.USE_WRITE (0),
.USE_BEGINBURSTTRANSFER (0),
.USE_BEGINTRANSFER (0),
.USE_CHIPSELECT (0),
.USE_BURSTCOUNT (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (1),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_LINEWRAPBURSTS (1),
.AV_REGISTERINCOMINGSIGNALS (0)
) nios2_qsys_0_instruction_master_translator (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_address), // avalon_universal_master_0.address
.uav_burstcount (nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_burstcount), // .burstcount
.uav_read (nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_read), // .read
.uav_write (nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_write), // .write
.uav_waitrequest (nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_waitrequest), // .waitrequest
.uav_readdatavalid (nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
.uav_byteenable (nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_byteenable), // .byteenable
.uav_readdata (nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_readdata), // .readdata
.uav_writedata (nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_writedata), // .writedata
.uav_lock (nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_lock), // .lock
.uav_debugaccess (nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_debugaccess), // .debugaccess
.av_address (nios2_qsys_0_instruction_master_address), // avalon_anti_master_0.address
.av_waitrequest (nios2_qsys_0_instruction_master_waitrequest), // .waitrequest
.av_read (nios2_qsys_0_instruction_master_read), // .read
.av_readdata (nios2_qsys_0_instruction_master_readdata), // .readdata
.av_burstcount (1'b1), // (terminated)
.av_byteenable (4'b1111), // (terminated)
.av_beginbursttransfer (1'b0), // (terminated)
.av_begintransfer (1'b0), // (terminated)
.av_chipselect (1'b0), // (terminated)
.av_readdatavalid (), // (terminated)
.av_write (1'b0), // (terminated)
.av_writedata (32'b00000000000000000000000000000000), // (terminated)
.av_lock (1'b0), // (terminated)
.av_debugaccess (1'b0), // (terminated)
.uav_clken (), // (terminated)
.av_clken (1'b1), // (terminated)
.uav_response (2'b00), // (terminated)
.av_response (), // (terminated)
.uav_writeresponsevalid (1'b0), // (terminated)
.av_writeresponsevalid () // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (1),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (1),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (19),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (1),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) jtag_uart_0_avalon_jtag_slave_translator (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (jtag_uart_0_avalon_jtag_slave_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (jtag_uart_0_avalon_jtag_slave_agent_m0_burstcount), // .burstcount
.uav_read (jtag_uart_0_avalon_jtag_slave_agent_m0_read), // .read
.uav_write (jtag_uart_0_avalon_jtag_slave_agent_m0_write), // .write
.uav_waitrequest (jtag_uart_0_avalon_jtag_slave_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (jtag_uart_0_avalon_jtag_slave_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (jtag_uart_0_avalon_jtag_slave_agent_m0_byteenable), // .byteenable
.uav_readdata (jtag_uart_0_avalon_jtag_slave_agent_m0_readdata), // .readdata
.uav_writedata (jtag_uart_0_avalon_jtag_slave_agent_m0_writedata), // .writedata
.uav_lock (jtag_uart_0_avalon_jtag_slave_agent_m0_lock), // .lock
.uav_debugaccess (jtag_uart_0_avalon_jtag_slave_agent_m0_debugaccess), // .debugaccess
.av_address (jtag_uart_0_avalon_jtag_slave_address), // avalon_anti_slave_0.address
.av_write (jtag_uart_0_avalon_jtag_slave_write), // .write
.av_read (jtag_uart_0_avalon_jtag_slave_read), // .read
.av_readdata (jtag_uart_0_avalon_jtag_slave_readdata), // .readdata
.av_writedata (jtag_uart_0_avalon_jtag_slave_writedata), // .writedata
.av_waitrequest (jtag_uart_0_avalon_jtag_slave_waitrequest), // .waitrequest
.av_chipselect (jtag_uart_0_avalon_jtag_slave_chipselect), // .chipselect
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_byteenable (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (9),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (19),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (1),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) nios2_qsys_0_debug_mem_slave_translator (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (nios2_qsys_0_debug_mem_slave_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (nios2_qsys_0_debug_mem_slave_agent_m0_burstcount), // .burstcount
.uav_read (nios2_qsys_0_debug_mem_slave_agent_m0_read), // .read
.uav_write (nios2_qsys_0_debug_mem_slave_agent_m0_write), // .write
.uav_waitrequest (nios2_qsys_0_debug_mem_slave_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (nios2_qsys_0_debug_mem_slave_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (nios2_qsys_0_debug_mem_slave_agent_m0_byteenable), // .byteenable
.uav_readdata (nios2_qsys_0_debug_mem_slave_agent_m0_readdata), // .readdata
.uav_writedata (nios2_qsys_0_debug_mem_slave_agent_m0_writedata), // .writedata
.uav_lock (nios2_qsys_0_debug_mem_slave_agent_m0_lock), // .lock
.uav_debugaccess (nios2_qsys_0_debug_mem_slave_agent_m0_debugaccess), // .debugaccess
.av_address (nios2_qsys_0_debug_mem_slave_address), // avalon_anti_slave_0.address
.av_write (nios2_qsys_0_debug_mem_slave_write), // .write
.av_read (nios2_qsys_0_debug_mem_slave_read), // .read
.av_readdata (nios2_qsys_0_debug_mem_slave_readdata), // .readdata
.av_writedata (nios2_qsys_0_debug_mem_slave_writedata), // .writedata
.av_byteenable (nios2_qsys_0_debug_mem_slave_byteenable), // .byteenable
.av_waitrequest (nios2_qsys_0_debug_mem_slave_waitrequest), // .waitrequest
.av_debugaccess (nios2_qsys_0_debug_mem_slave_debugaccess), // .debugaccess
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_chipselect (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (15),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (19),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (1),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (0),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (0),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) onchip_memory2_0_s1_translator (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (onchip_memory2_0_s1_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (onchip_memory2_0_s1_agent_m0_burstcount), // .burstcount
.uav_read (onchip_memory2_0_s1_agent_m0_read), // .read
.uav_write (onchip_memory2_0_s1_agent_m0_write), // .write
.uav_waitrequest (onchip_memory2_0_s1_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (onchip_memory2_0_s1_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (onchip_memory2_0_s1_agent_m0_byteenable), // .byteenable
.uav_readdata (onchip_memory2_0_s1_agent_m0_readdata), // .readdata
.uav_writedata (onchip_memory2_0_s1_agent_m0_writedata), // .writedata
.uav_lock (onchip_memory2_0_s1_agent_m0_lock), // .lock
.uav_debugaccess (onchip_memory2_0_s1_agent_m0_debugaccess), // .debugaccess
.av_address (onchip_memory2_0_s1_address), // avalon_anti_slave_0.address
.av_write (onchip_memory2_0_s1_write), // .write
.av_readdata (onchip_memory2_0_s1_readdata), // .readdata
.av_writedata (onchip_memory2_0_s1_writedata), // .writedata
.av_byteenable (onchip_memory2_0_s1_byteenable), // .byteenable
.av_chipselect (onchip_memory2_0_s1_chipselect), // .chipselect
.av_clken (onchip_memory2_0_s1_clken), // .clken
.av_read (), // (terminated)
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_waitrequest (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (2),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (1),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (19),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (0),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) leds_s1_translator (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (leds_s1_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (leds_s1_agent_m0_burstcount), // .burstcount
.uav_read (leds_s1_agent_m0_read), // .read
.uav_write (leds_s1_agent_m0_write), // .write
.uav_waitrequest (leds_s1_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (leds_s1_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (leds_s1_agent_m0_byteenable), // .byteenable
.uav_readdata (leds_s1_agent_m0_readdata), // .readdata
.uav_writedata (leds_s1_agent_m0_writedata), // .writedata
.uav_lock (leds_s1_agent_m0_lock), // .lock
.uav_debugaccess (leds_s1_agent_m0_debugaccess), // .debugaccess
.av_address (LEDs_s1_address), // avalon_anti_slave_0.address
.av_write (LEDs_s1_write), // .write
.av_readdata (LEDs_s1_readdata), // .readdata
.av_writedata (LEDs_s1_writedata), // .writedata
.av_chipselect (LEDs_s1_chipselect), // .chipselect
.av_read (), // (terminated)
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_byteenable (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_waitrequest (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (2),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (1),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (19),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (0),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) switches_s1_translator (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (switches_s1_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (switches_s1_agent_m0_burstcount), // .burstcount
.uav_read (switches_s1_agent_m0_read), // .read
.uav_write (switches_s1_agent_m0_write), // .write
.uav_waitrequest (switches_s1_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (switches_s1_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (switches_s1_agent_m0_byteenable), // .byteenable
.uav_readdata (switches_s1_agent_m0_readdata), // .readdata
.uav_writedata (switches_s1_agent_m0_writedata), // .writedata
.uav_lock (switches_s1_agent_m0_lock), // .lock
.uav_debugaccess (switches_s1_agent_m0_debugaccess), // .debugaccess
.av_address (switches_s1_address), // avalon_anti_slave_0.address
.av_readdata (switches_s1_readdata), // .readdata
.av_write (), // (terminated)
.av_read (), // (terminated)
.av_writedata (), // (terminated)
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_byteenable (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_waitrequest (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_chipselect (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (2),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (1),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (19),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (0),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) sram_data_s1_translator (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (sram_data_s1_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (sram_data_s1_agent_m0_burstcount), // .burstcount
.uav_read (sram_data_s1_agent_m0_read), // .read
.uav_write (sram_data_s1_agent_m0_write), // .write
.uav_waitrequest (sram_data_s1_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (sram_data_s1_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (sram_data_s1_agent_m0_byteenable), // .byteenable
.uav_readdata (sram_data_s1_agent_m0_readdata), // .readdata
.uav_writedata (sram_data_s1_agent_m0_writedata), // .writedata
.uav_lock (sram_data_s1_agent_m0_lock), // .lock
.uav_debugaccess (sram_data_s1_agent_m0_debugaccess), // .debugaccess
.av_address (sram_data_s1_address), // avalon_anti_slave_0.address
.av_write (sram_data_s1_write), // .write
.av_readdata (sram_data_s1_readdata), // .readdata
.av_writedata (sram_data_s1_writedata), // .writedata
.av_chipselect (sram_data_s1_chipselect), // .chipselect
.av_read (), // (terminated)
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_byteenable (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_waitrequest (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (2),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (1),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (19),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (0),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) sram_addr_s1_translator (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (sram_addr_s1_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (sram_addr_s1_agent_m0_burstcount), // .burstcount
.uav_read (sram_addr_s1_agent_m0_read), // .read
.uav_write (sram_addr_s1_agent_m0_write), // .write
.uav_waitrequest (sram_addr_s1_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (sram_addr_s1_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (sram_addr_s1_agent_m0_byteenable), // .byteenable
.uav_readdata (sram_addr_s1_agent_m0_readdata), // .readdata
.uav_writedata (sram_addr_s1_agent_m0_writedata), // .writedata
.uav_lock (sram_addr_s1_agent_m0_lock), // .lock
.uav_debugaccess (sram_addr_s1_agent_m0_debugaccess), // .debugaccess
.av_address (sram_addr_s1_address), // avalon_anti_slave_0.address
.av_write (sram_addr_s1_write), // .write
.av_readdata (sram_addr_s1_readdata), // .readdata
.av_writedata (sram_addr_s1_writedata), // .writedata
.av_chipselect (sram_addr_s1_chipselect), // .chipselect
.av_read (), // (terminated)
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_byteenable (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_waitrequest (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (2),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (1),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (19),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (0),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) sram_read_write_s1_translator (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (sram_read_write_s1_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (sram_read_write_s1_agent_m0_burstcount), // .burstcount
.uav_read (sram_read_write_s1_agent_m0_read), // .read
.uav_write (sram_read_write_s1_agent_m0_write), // .write
.uav_waitrequest (sram_read_write_s1_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (sram_read_write_s1_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (sram_read_write_s1_agent_m0_byteenable), // .byteenable
.uav_readdata (sram_read_write_s1_agent_m0_readdata), // .readdata
.uav_writedata (sram_read_write_s1_agent_m0_writedata), // .writedata
.uav_lock (sram_read_write_s1_agent_m0_lock), // .lock
.uav_debugaccess (sram_read_write_s1_agent_m0_debugaccess), // .debugaccess
.av_address (sram_read_write_s1_address), // avalon_anti_slave_0.address
.av_write (sram_read_write_s1_write), // .write
.av_readdata (sram_read_write_s1_readdata), // .readdata
.av_writedata (sram_read_write_s1_writedata), // .writedata
.av_chipselect (sram_read_write_s1_chipselect), // .chipselect
.av_read (), // (terminated)
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_byteenable (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_waitrequest (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (2),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (1),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (19),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (0),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) sram_cs_s1_translator (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (sram_cs_s1_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (sram_cs_s1_agent_m0_burstcount), // .burstcount
.uav_read (sram_cs_s1_agent_m0_read), // .read
.uav_write (sram_cs_s1_agent_m0_write), // .write
.uav_waitrequest (sram_cs_s1_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (sram_cs_s1_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (sram_cs_s1_agent_m0_byteenable), // .byteenable
.uav_readdata (sram_cs_s1_agent_m0_readdata), // .readdata
.uav_writedata (sram_cs_s1_agent_m0_writedata), // .writedata
.uav_lock (sram_cs_s1_agent_m0_lock), // .lock
.uav_debugaccess (sram_cs_s1_agent_m0_debugaccess), // .debugaccess
.av_address (sram_cs_s1_address), // avalon_anti_slave_0.address
.av_write (sram_cs_s1_write), // .write
.av_readdata (sram_cs_s1_readdata), // .readdata
.av_writedata (sram_cs_s1_writedata), // .writedata
.av_chipselect (sram_cs_s1_chipselect), // .chipselect
.av_read (), // (terminated)
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_byteenable (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_waitrequest (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (2),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (1),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (19),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (0),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) sram_oe_s1_translator (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (sram_oe_s1_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (sram_oe_s1_agent_m0_burstcount), // .burstcount
.uav_read (sram_oe_s1_agent_m0_read), // .read
.uav_write (sram_oe_s1_agent_m0_write), // .write
.uav_waitrequest (sram_oe_s1_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (sram_oe_s1_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (sram_oe_s1_agent_m0_byteenable), // .byteenable
.uav_readdata (sram_oe_s1_agent_m0_readdata), // .readdata
.uav_writedata (sram_oe_s1_agent_m0_writedata), // .writedata
.uav_lock (sram_oe_s1_agent_m0_lock), // .lock
.uav_debugaccess (sram_oe_s1_agent_m0_debugaccess), // .debugaccess
.av_address (sram_oe_s1_address), // avalon_anti_slave_0.address
.av_write (sram_oe_s1_write), // .write
.av_readdata (sram_oe_s1_readdata), // .readdata
.av_writedata (sram_oe_s1_writedata), // .writedata
.av_chipselect (sram_oe_s1_chipselect), // .chipselect
.av_read (), // (terminated)
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_byteenable (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_waitrequest (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (2),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (1),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (19),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (0),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) regfile_data_s1_translator (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (regfile_data_s1_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (regfile_data_s1_agent_m0_burstcount), // .burstcount
.uav_read (regfile_data_s1_agent_m0_read), // .read
.uav_write (regfile_data_s1_agent_m0_write), // .write
.uav_waitrequest (regfile_data_s1_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (regfile_data_s1_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (regfile_data_s1_agent_m0_byteenable), // .byteenable
.uav_readdata (regfile_data_s1_agent_m0_readdata), // .readdata
.uav_writedata (regfile_data_s1_agent_m0_writedata), // .writedata
.uav_lock (regfile_data_s1_agent_m0_lock), // .lock
.uav_debugaccess (regfile_data_s1_agent_m0_debugaccess), // .debugaccess
.av_address (regfile_data_s1_address), // avalon_anti_slave_0.address
.av_write (regfile_data_s1_write), // .write
.av_readdata (regfile_data_s1_readdata), // .readdata
.av_writedata (regfile_data_s1_writedata), // .writedata
.av_chipselect (regfile_data_s1_chipselect), // .chipselect
.av_read (), // (terminated)
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_byteenable (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_waitrequest (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (2),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (1),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (19),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (0),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) regfile_reg1_s1_translator (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (regfile_reg1_s1_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (regfile_reg1_s1_agent_m0_burstcount), // .burstcount
.uav_read (regfile_reg1_s1_agent_m0_read), // .read
.uav_write (regfile_reg1_s1_agent_m0_write), // .write
.uav_waitrequest (regfile_reg1_s1_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (regfile_reg1_s1_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (regfile_reg1_s1_agent_m0_byteenable), // .byteenable
.uav_readdata (regfile_reg1_s1_agent_m0_readdata), // .readdata
.uav_writedata (regfile_reg1_s1_agent_m0_writedata), // .writedata
.uav_lock (regfile_reg1_s1_agent_m0_lock), // .lock
.uav_debugaccess (regfile_reg1_s1_agent_m0_debugaccess), // .debugaccess
.av_address (regfile_reg1_s1_address), // avalon_anti_slave_0.address
.av_readdata (regfile_reg1_s1_readdata), // .readdata
.av_write (), // (terminated)
.av_read (), // (terminated)
.av_writedata (), // (terminated)
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_byteenable (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_waitrequest (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_chipselect (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (2),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (1),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (19),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (0),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) regfile_reg2_s1_translator (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (regfile_reg2_s1_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (regfile_reg2_s1_agent_m0_burstcount), // .burstcount
.uav_read (regfile_reg2_s1_agent_m0_read), // .read
.uav_write (regfile_reg2_s1_agent_m0_write), // .write
.uav_waitrequest (regfile_reg2_s1_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (regfile_reg2_s1_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (regfile_reg2_s1_agent_m0_byteenable), // .byteenable
.uav_readdata (regfile_reg2_s1_agent_m0_readdata), // .readdata
.uav_writedata (regfile_reg2_s1_agent_m0_writedata), // .writedata
.uav_lock (regfile_reg2_s1_agent_m0_lock), // .lock
.uav_debugaccess (regfile_reg2_s1_agent_m0_debugaccess), // .debugaccess
.av_address (regfile_reg2_s1_address), // avalon_anti_slave_0.address
.av_readdata (regfile_reg2_s1_readdata), // .readdata
.av_write (), // (terminated)
.av_read (), // (terminated)
.av_writedata (), // (terminated)
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_byteenable (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_waitrequest (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_chipselect (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (2),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (1),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (19),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (0),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) regfile_r1sel_s1_translator (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (regfile_r1sel_s1_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (regfile_r1sel_s1_agent_m0_burstcount), // .burstcount
.uav_read (regfile_r1sel_s1_agent_m0_read), // .read
.uav_write (regfile_r1sel_s1_agent_m0_write), // .write
.uav_waitrequest (regfile_r1sel_s1_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (regfile_r1sel_s1_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (regfile_r1sel_s1_agent_m0_byteenable), // .byteenable
.uav_readdata (regfile_r1sel_s1_agent_m0_readdata), // .readdata
.uav_writedata (regfile_r1sel_s1_agent_m0_writedata), // .writedata
.uav_lock (regfile_r1sel_s1_agent_m0_lock), // .lock
.uav_debugaccess (regfile_r1sel_s1_agent_m0_debugaccess), // .debugaccess
.av_address (regfile_r1sel_s1_address), // avalon_anti_slave_0.address
.av_write (regfile_r1sel_s1_write), // .write
.av_readdata (regfile_r1sel_s1_readdata), // .readdata
.av_writedata (regfile_r1sel_s1_writedata), // .writedata
.av_chipselect (regfile_r1sel_s1_chipselect), // .chipselect
.av_read (), // (terminated)
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_byteenable (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_waitrequest (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (2),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (1),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (19),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (0),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) regfile_r2sel_s1_translator (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (regfile_r2sel_s1_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (regfile_r2sel_s1_agent_m0_burstcount), // .burstcount
.uav_read (regfile_r2sel_s1_agent_m0_read), // .read
.uav_write (regfile_r2sel_s1_agent_m0_write), // .write
.uav_waitrequest (regfile_r2sel_s1_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (regfile_r2sel_s1_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (regfile_r2sel_s1_agent_m0_byteenable), // .byteenable
.uav_readdata (regfile_r2sel_s1_agent_m0_readdata), // .readdata
.uav_writedata (regfile_r2sel_s1_agent_m0_writedata), // .writedata
.uav_lock (regfile_r2sel_s1_agent_m0_lock), // .lock
.uav_debugaccess (regfile_r2sel_s1_agent_m0_debugaccess), // .debugaccess
.av_address (regfile_r2sel_s1_address), // avalon_anti_slave_0.address
.av_write (regfile_r2sel_s1_write), // .write
.av_readdata (regfile_r2sel_s1_readdata), // .readdata
.av_writedata (regfile_r2sel_s1_writedata), // .writedata
.av_chipselect (regfile_r2sel_s1_chipselect), // .chipselect
.av_read (), // (terminated)
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_byteenable (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_waitrequest (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (2),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (1),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (19),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (0),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) regfile_wsel_s1_translator (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (regfile_wsel_s1_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (regfile_wsel_s1_agent_m0_burstcount), // .burstcount
.uav_read (regfile_wsel_s1_agent_m0_read), // .read
.uav_write (regfile_wsel_s1_agent_m0_write), // .write
.uav_waitrequest (regfile_wsel_s1_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (regfile_wsel_s1_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (regfile_wsel_s1_agent_m0_byteenable), // .byteenable
.uav_readdata (regfile_wsel_s1_agent_m0_readdata), // .readdata
.uav_writedata (regfile_wsel_s1_agent_m0_writedata), // .writedata
.uav_lock (regfile_wsel_s1_agent_m0_lock), // .lock
.uav_debugaccess (regfile_wsel_s1_agent_m0_debugaccess), // .debugaccess
.av_address (regfile_wsel_s1_address), // avalon_anti_slave_0.address
.av_write (regfile_wsel_s1_write), // .write
.av_readdata (regfile_wsel_s1_readdata), // .readdata
.av_writedata (regfile_wsel_s1_writedata), // .writedata
.av_chipselect (regfile_wsel_s1_chipselect), // .chipselect
.av_read (), // (terminated)
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_byteenable (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_waitrequest (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (2),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (1),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (19),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (0),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) regfile_we_s1_translator (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (regfile_we_s1_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (regfile_we_s1_agent_m0_burstcount), // .burstcount
.uav_read (regfile_we_s1_agent_m0_read), // .read
.uav_write (regfile_we_s1_agent_m0_write), // .write
.uav_waitrequest (regfile_we_s1_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (regfile_we_s1_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (regfile_we_s1_agent_m0_byteenable), // .byteenable
.uav_readdata (regfile_we_s1_agent_m0_readdata), // .readdata
.uav_writedata (regfile_we_s1_agent_m0_writedata), // .writedata
.uav_lock (regfile_we_s1_agent_m0_lock), // .lock
.uav_debugaccess (regfile_we_s1_agent_m0_debugaccess), // .debugaccess
.av_address (regfile_we_s1_address), // avalon_anti_slave_0.address
.av_write (regfile_we_s1_write), // .write
.av_readdata (regfile_we_s1_readdata), // .readdata
.av_writedata (regfile_we_s1_writedata), // .writedata
.av_chipselect (regfile_we_s1_chipselect), // .chipselect
.av_read (), // (terminated)
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_byteenable (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_waitrequest (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (2),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (1),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (19),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (0),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) hex_0_s1_translator (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (hex_0_s1_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (hex_0_s1_agent_m0_burstcount), // .burstcount
.uav_read (hex_0_s1_agent_m0_read), // .read
.uav_write (hex_0_s1_agent_m0_write), // .write
.uav_waitrequest (hex_0_s1_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (hex_0_s1_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (hex_0_s1_agent_m0_byteenable), // .byteenable
.uav_readdata (hex_0_s1_agent_m0_readdata), // .readdata
.uav_writedata (hex_0_s1_agent_m0_writedata), // .writedata
.uav_lock (hex_0_s1_agent_m0_lock), // .lock
.uav_debugaccess (hex_0_s1_agent_m0_debugaccess), // .debugaccess
.av_address (hex_0_s1_address), // avalon_anti_slave_0.address
.av_write (hex_0_s1_write), // .write
.av_readdata (hex_0_s1_readdata), // .readdata
.av_writedata (hex_0_s1_writedata), // .writedata
.av_chipselect (hex_0_s1_chipselect), // .chipselect
.av_read (), // (terminated)
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_byteenable (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_waitrequest (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (2),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (1),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (19),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (0),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) hex_1_s1_translator (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (hex_1_s1_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (hex_1_s1_agent_m0_burstcount), // .burstcount
.uav_read (hex_1_s1_agent_m0_read), // .read
.uav_write (hex_1_s1_agent_m0_write), // .write
.uav_waitrequest (hex_1_s1_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (hex_1_s1_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (hex_1_s1_agent_m0_byteenable), // .byteenable
.uav_readdata (hex_1_s1_agent_m0_readdata), // .readdata
.uav_writedata (hex_1_s1_agent_m0_writedata), // .writedata
.uav_lock (hex_1_s1_agent_m0_lock), // .lock
.uav_debugaccess (hex_1_s1_agent_m0_debugaccess), // .debugaccess
.av_address (hex_1_s1_address), // avalon_anti_slave_0.address
.av_write (hex_1_s1_write), // .write
.av_readdata (hex_1_s1_readdata), // .readdata
.av_writedata (hex_1_s1_writedata), // .writedata
.av_chipselect (hex_1_s1_chipselect), // .chipselect
.av_read (), // (terminated)
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_byteenable (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_waitrequest (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (2),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (1),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (19),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (0),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) hex_2_s1_translator (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (hex_2_s1_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (hex_2_s1_agent_m0_burstcount), // .burstcount
.uav_read (hex_2_s1_agent_m0_read), // .read
.uav_write (hex_2_s1_agent_m0_write), // .write
.uav_waitrequest (hex_2_s1_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (hex_2_s1_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (hex_2_s1_agent_m0_byteenable), // .byteenable
.uav_readdata (hex_2_s1_agent_m0_readdata), // .readdata
.uav_writedata (hex_2_s1_agent_m0_writedata), // .writedata
.uav_lock (hex_2_s1_agent_m0_lock), // .lock
.uav_debugaccess (hex_2_s1_agent_m0_debugaccess), // .debugaccess
.av_address (hex_2_s1_address), // avalon_anti_slave_0.address
.av_write (hex_2_s1_write), // .write
.av_readdata (hex_2_s1_readdata), // .readdata
.av_writedata (hex_2_s1_writedata), // .writedata
.av_chipselect (hex_2_s1_chipselect), // .chipselect
.av_read (), // (terminated)
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_byteenable (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_waitrequest (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (2),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (1),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (19),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (0),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) hex_3_s1_translator (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (hex_3_s1_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (hex_3_s1_agent_m0_burstcount), // .burstcount
.uav_read (hex_3_s1_agent_m0_read), // .read
.uav_write (hex_3_s1_agent_m0_write), // .write
.uav_waitrequest (hex_3_s1_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (hex_3_s1_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (hex_3_s1_agent_m0_byteenable), // .byteenable
.uav_readdata (hex_3_s1_agent_m0_readdata), // .readdata
.uav_writedata (hex_3_s1_agent_m0_writedata), // .writedata
.uav_lock (hex_3_s1_agent_m0_lock), // .lock
.uav_debugaccess (hex_3_s1_agent_m0_debugaccess), // .debugaccess
.av_address (hex_3_s1_address), // avalon_anti_slave_0.address
.av_write (hex_3_s1_write), // .write
.av_readdata (hex_3_s1_readdata), // .readdata
.av_writedata (hex_3_s1_writedata), // .writedata
.av_chipselect (hex_3_s1_chipselect), // .chipselect
.av_read (), // (terminated)
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_byteenable (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_waitrequest (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (2),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (1),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (19),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (0),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) hex_4_s1_translator (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (hex_4_s1_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (hex_4_s1_agent_m0_burstcount), // .burstcount
.uav_read (hex_4_s1_agent_m0_read), // .read
.uav_write (hex_4_s1_agent_m0_write), // .write
.uav_waitrequest (hex_4_s1_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (hex_4_s1_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (hex_4_s1_agent_m0_byteenable), // .byteenable
.uav_readdata (hex_4_s1_agent_m0_readdata), // .readdata
.uav_writedata (hex_4_s1_agent_m0_writedata), // .writedata
.uav_lock (hex_4_s1_agent_m0_lock), // .lock
.uav_debugaccess (hex_4_s1_agent_m0_debugaccess), // .debugaccess
.av_address (hex_4_s1_address), // avalon_anti_slave_0.address
.av_write (hex_4_s1_write), // .write
.av_readdata (hex_4_s1_readdata), // .readdata
.av_writedata (hex_4_s1_writedata), // .writedata
.av_chipselect (hex_4_s1_chipselect), // .chipselect
.av_read (), // (terminated)
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_byteenable (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_waitrequest (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (2),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (1),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (19),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (0),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) hex_5_s1_translator (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (hex_5_s1_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (hex_5_s1_agent_m0_burstcount), // .burstcount
.uav_read (hex_5_s1_agent_m0_read), // .read
.uav_write (hex_5_s1_agent_m0_write), // .write
.uav_waitrequest (hex_5_s1_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (hex_5_s1_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (hex_5_s1_agent_m0_byteenable), // .byteenable
.uav_readdata (hex_5_s1_agent_m0_readdata), // .readdata
.uav_writedata (hex_5_s1_agent_m0_writedata), // .writedata
.uav_lock (hex_5_s1_agent_m0_lock), // .lock
.uav_debugaccess (hex_5_s1_agent_m0_debugaccess), // .debugaccess
.av_address (hex_5_s1_address), // avalon_anti_slave_0.address
.av_write (hex_5_s1_write), // .write
.av_readdata (hex_5_s1_readdata), // .readdata
.av_writedata (hex_5_s1_writedata), // .writedata
.av_chipselect (hex_5_s1_chipselect), // .chipselect
.av_read (), // (terminated)
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_byteenable (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_waitrequest (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (2),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (1),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (19),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (0),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) alu_a_s1_translator (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (alu_a_s1_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (alu_a_s1_agent_m0_burstcount), // .burstcount
.uav_read (alu_a_s1_agent_m0_read), // .read
.uav_write (alu_a_s1_agent_m0_write), // .write
.uav_waitrequest (alu_a_s1_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (alu_a_s1_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (alu_a_s1_agent_m0_byteenable), // .byteenable
.uav_readdata (alu_a_s1_agent_m0_readdata), // .readdata
.uav_writedata (alu_a_s1_agent_m0_writedata), // .writedata
.uav_lock (alu_a_s1_agent_m0_lock), // .lock
.uav_debugaccess (alu_a_s1_agent_m0_debugaccess), // .debugaccess
.av_address (alu_a_s1_address), // avalon_anti_slave_0.address
.av_write (alu_a_s1_write), // .write
.av_readdata (alu_a_s1_readdata), // .readdata
.av_writedata (alu_a_s1_writedata), // .writedata
.av_chipselect (alu_a_s1_chipselect), // .chipselect
.av_read (), // (terminated)
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_byteenable (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_waitrequest (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (2),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (1),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (19),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (0),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) alu_b_s1_translator (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (alu_b_s1_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (alu_b_s1_agent_m0_burstcount), // .burstcount
.uav_read (alu_b_s1_agent_m0_read), // .read
.uav_write (alu_b_s1_agent_m0_write), // .write
.uav_waitrequest (alu_b_s1_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (alu_b_s1_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (alu_b_s1_agent_m0_byteenable), // .byteenable
.uav_readdata (alu_b_s1_agent_m0_readdata), // .readdata
.uav_writedata (alu_b_s1_agent_m0_writedata), // .writedata
.uav_lock (alu_b_s1_agent_m0_lock), // .lock
.uav_debugaccess (alu_b_s1_agent_m0_debugaccess), // .debugaccess
.av_address (alu_b_s1_address), // avalon_anti_slave_0.address
.av_write (alu_b_s1_write), // .write
.av_readdata (alu_b_s1_readdata), // .readdata
.av_writedata (alu_b_s1_writedata), // .writedata
.av_chipselect (alu_b_s1_chipselect), // .chipselect
.av_read (), // (terminated)
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_byteenable (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_waitrequest (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (2),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (1),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (19),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (0),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) alu_control_s1_translator (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (alu_control_s1_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (alu_control_s1_agent_m0_burstcount), // .burstcount
.uav_read (alu_control_s1_agent_m0_read), // .read
.uav_write (alu_control_s1_agent_m0_write), // .write
.uav_waitrequest (alu_control_s1_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (alu_control_s1_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (alu_control_s1_agent_m0_byteenable), // .byteenable
.uav_readdata (alu_control_s1_agent_m0_readdata), // .readdata
.uav_writedata (alu_control_s1_agent_m0_writedata), // .writedata
.uav_lock (alu_control_s1_agent_m0_lock), // .lock
.uav_debugaccess (alu_control_s1_agent_m0_debugaccess), // .debugaccess
.av_address (alu_control_s1_address), // avalon_anti_slave_0.address
.av_write (alu_control_s1_write), // .write
.av_readdata (alu_control_s1_readdata), // .readdata
.av_writedata (alu_control_s1_writedata), // .writedata
.av_chipselect (alu_control_s1_chipselect), // .chipselect
.av_read (), // (terminated)
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_byteenable (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_waitrequest (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (2),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (1),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (19),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (0),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) alu_out_s1_translator (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (alu_out_s1_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (alu_out_s1_agent_m0_burstcount), // .burstcount
.uav_read (alu_out_s1_agent_m0_read), // .read
.uav_write (alu_out_s1_agent_m0_write), // .write
.uav_waitrequest (alu_out_s1_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (alu_out_s1_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (alu_out_s1_agent_m0_byteenable), // .byteenable
.uav_readdata (alu_out_s1_agent_m0_readdata), // .readdata
.uav_writedata (alu_out_s1_agent_m0_writedata), // .writedata
.uav_lock (alu_out_s1_agent_m0_lock), // .lock
.uav_debugaccess (alu_out_s1_agent_m0_debugaccess), // .debugaccess
.av_address (alu_out_s1_address), // avalon_anti_slave_0.address
.av_readdata (alu_out_s1_readdata), // .readdata
.av_write (), // (terminated)
.av_read (), // (terminated)
.av_writedata (), // (terminated)
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_byteenable (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_waitrequest (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_chipselect (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (2),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (1),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (19),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (0),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) alu_zero_s1_translator (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (alu_zero_s1_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (alu_zero_s1_agent_m0_burstcount), // .burstcount
.uav_read (alu_zero_s1_agent_m0_read), // .read
.uav_write (alu_zero_s1_agent_m0_write), // .write
.uav_waitrequest (alu_zero_s1_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (alu_zero_s1_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (alu_zero_s1_agent_m0_byteenable), // .byteenable
.uav_readdata (alu_zero_s1_agent_m0_readdata), // .readdata
.uav_writedata (alu_zero_s1_agent_m0_writedata), // .writedata
.uav_lock (alu_zero_s1_agent_m0_lock), // .lock
.uav_debugaccess (alu_zero_s1_agent_m0_debugaccess), // .debugaccess
.av_address (alu_zero_s1_address), // avalon_anti_slave_0.address
.av_readdata (alu_zero_s1_readdata), // .readdata
.av_write (), // (terminated)
.av_read (), // (terminated)
.av_writedata (), // (terminated)
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_byteenable (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_waitrequest (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_chipselect (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (2),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (1),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (19),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (0),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) alu_overflow_s1_translator (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (alu_overflow_s1_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (alu_overflow_s1_agent_m0_burstcount), // .burstcount
.uav_read (alu_overflow_s1_agent_m0_read), // .read
.uav_write (alu_overflow_s1_agent_m0_write), // .write
.uav_waitrequest (alu_overflow_s1_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (alu_overflow_s1_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (alu_overflow_s1_agent_m0_byteenable), // .byteenable
.uav_readdata (alu_overflow_s1_agent_m0_readdata), // .readdata
.uav_writedata (alu_overflow_s1_agent_m0_writedata), // .writedata
.uav_lock (alu_overflow_s1_agent_m0_lock), // .lock
.uav_debugaccess (alu_overflow_s1_agent_m0_debugaccess), // .debugaccess
.av_address (alu_overflow_s1_address), // avalon_anti_slave_0.address
.av_readdata (alu_overflow_s1_readdata), // .readdata
.av_write (), // (terminated)
.av_read (), // (terminated)
.av_writedata (), // (terminated)
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_byteenable (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_waitrequest (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_chipselect (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (2),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (1),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (19),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (0),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) alu_carry_out_s1_translator (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (alu_carry_out_s1_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (alu_carry_out_s1_agent_m0_burstcount), // .burstcount
.uav_read (alu_carry_out_s1_agent_m0_read), // .read
.uav_write (alu_carry_out_s1_agent_m0_write), // .write
.uav_waitrequest (alu_carry_out_s1_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (alu_carry_out_s1_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (alu_carry_out_s1_agent_m0_byteenable), // .byteenable
.uav_readdata (alu_carry_out_s1_agent_m0_readdata), // .readdata
.uav_writedata (alu_carry_out_s1_agent_m0_writedata), // .writedata
.uav_lock (alu_carry_out_s1_agent_m0_lock), // .lock
.uav_debugaccess (alu_carry_out_s1_agent_m0_debugaccess), // .debugaccess
.av_address (alu_carry_out_s1_address), // avalon_anti_slave_0.address
.av_readdata (alu_carry_out_s1_readdata), // .readdata
.av_write (), // (terminated)
.av_read (), // (terminated)
.av_writedata (), // (terminated)
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_byteenable (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_waitrequest (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_chipselect (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (2),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (1),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (19),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (0),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) alu_negative_s1_translator (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (alu_negative_s1_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (alu_negative_s1_agent_m0_burstcount), // .burstcount
.uav_read (alu_negative_s1_agent_m0_read), // .read
.uav_write (alu_negative_s1_agent_m0_write), // .write
.uav_waitrequest (alu_negative_s1_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (alu_negative_s1_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (alu_negative_s1_agent_m0_byteenable), // .byteenable
.uav_readdata (alu_negative_s1_agent_m0_readdata), // .readdata
.uav_writedata (alu_negative_s1_agent_m0_writedata), // .writedata
.uav_lock (alu_negative_s1_agent_m0_lock), // .lock
.uav_debugaccess (alu_negative_s1_agent_m0_debugaccess), // .debugaccess
.av_address (alu_negative_s1_address), // avalon_anti_slave_0.address
.av_readdata (alu_negative_s1_readdata), // .readdata
.av_write (), // (terminated)
.av_read (), // (terminated)
.av_writedata (), // (terminated)
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_byteenable (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_waitrequest (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_chipselect (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (2),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (1),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (19),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (0),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) keys_s1_translator (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (keys_s1_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (keys_s1_agent_m0_burstcount), // .burstcount
.uav_read (keys_s1_agent_m0_read), // .read
.uav_write (keys_s1_agent_m0_write), // .write
.uav_waitrequest (keys_s1_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (keys_s1_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (keys_s1_agent_m0_byteenable), // .byteenable
.uav_readdata (keys_s1_agent_m0_readdata), // .readdata
.uav_writedata (keys_s1_agent_m0_writedata), // .writedata
.uav_lock (keys_s1_agent_m0_lock), // .lock
.uav_debugaccess (keys_s1_agent_m0_debugaccess), // .debugaccess
.av_address (keys_s1_address), // avalon_anti_slave_0.address
.av_readdata (keys_s1_readdata), // .readdata
.av_write (), // (terminated)
.av_read (), // (terminated)
.av_writedata (), // (terminated)
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_byteenable (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_waitrequest (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_chipselect (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_master_agent #(
.PKT_ORI_BURST_SIZE_H (98),
.PKT_ORI_BURST_SIZE_L (96),
.PKT_RESPONSE_STATUS_H (95),
.PKT_RESPONSE_STATUS_L (94),
.PKT_QOS_H (75),
.PKT_QOS_L (75),
.PKT_DATA_SIDEBAND_H (73),
.PKT_DATA_SIDEBAND_L (73),
.PKT_ADDR_SIDEBAND_H (72),
.PKT_ADDR_SIDEBAND_L (72),
.PKT_BURST_TYPE_H (71),
.PKT_BURST_TYPE_L (70),
.PKT_CACHE_H (93),
.PKT_CACHE_L (90),
.PKT_THREAD_ID_H (86),
.PKT_THREAD_ID_L (86),
.PKT_BURST_SIZE_H (69),
.PKT_BURST_SIZE_L (67),
.PKT_TRANS_EXCLUSIVE (60),
.PKT_TRANS_LOCK (59),
.PKT_BEGIN_BURST (74),
.PKT_PROTECTION_H (89),
.PKT_PROTECTION_L (87),
.PKT_BURSTWRAP_H (66),
.PKT_BURSTWRAP_L (64),
.PKT_BYTE_CNT_H (63),
.PKT_BYTE_CNT_L (61),
.PKT_ADDR_H (54),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (55),
.PKT_TRANS_POSTED (56),
.PKT_TRANS_WRITE (57),
.PKT_TRANS_READ (58),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (80),
.PKT_SRC_ID_L (76),
.PKT_DEST_ID_H (85),
.PKT_DEST_ID_L (81),
.ST_DATA_W (99),
.ST_CHANNEL_W (32),
.AV_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_RSP (0),
.ID (0),
.BURSTWRAP_VALUE (7),
.CACHE_VALUE (0),
.SECURE_ACCESS_BIT (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) nios2_qsys_0_data_master_agent (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.av_address (nios2_qsys_0_data_master_translator_avalon_universal_master_0_address), // av.address
.av_write (nios2_qsys_0_data_master_translator_avalon_universal_master_0_write), // .write
.av_read (nios2_qsys_0_data_master_translator_avalon_universal_master_0_read), // .read
.av_writedata (nios2_qsys_0_data_master_translator_avalon_universal_master_0_writedata), // .writedata
.av_readdata (nios2_qsys_0_data_master_translator_avalon_universal_master_0_readdata), // .readdata
.av_waitrequest (nios2_qsys_0_data_master_translator_avalon_universal_master_0_waitrequest), // .waitrequest
.av_readdatavalid (nios2_qsys_0_data_master_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
.av_byteenable (nios2_qsys_0_data_master_translator_avalon_universal_master_0_byteenable), // .byteenable
.av_burstcount (nios2_qsys_0_data_master_translator_avalon_universal_master_0_burstcount), // .burstcount
.av_debugaccess (nios2_qsys_0_data_master_translator_avalon_universal_master_0_debugaccess), // .debugaccess
.av_lock (nios2_qsys_0_data_master_translator_avalon_universal_master_0_lock), // .lock
.cp_valid (nios2_qsys_0_data_master_agent_cp_valid), // cp.valid
.cp_data (nios2_qsys_0_data_master_agent_cp_data), // .data
.cp_startofpacket (nios2_qsys_0_data_master_agent_cp_startofpacket), // .startofpacket
.cp_endofpacket (nios2_qsys_0_data_master_agent_cp_endofpacket), // .endofpacket
.cp_ready (nios2_qsys_0_data_master_agent_cp_ready), // .ready
.rp_valid (rsp_mux_src_valid), // rp.valid
.rp_data (rsp_mux_src_data), // .data
.rp_channel (rsp_mux_src_channel), // .channel
.rp_startofpacket (rsp_mux_src_startofpacket), // .startofpacket
.rp_endofpacket (rsp_mux_src_endofpacket), // .endofpacket
.rp_ready (rsp_mux_src_ready), // .ready
.av_response (), // (terminated)
.av_writeresponsevalid () // (terminated)
);
altera_merlin_master_agent #(
.PKT_ORI_BURST_SIZE_H (98),
.PKT_ORI_BURST_SIZE_L (96),
.PKT_RESPONSE_STATUS_H (95),
.PKT_RESPONSE_STATUS_L (94),
.PKT_QOS_H (75),
.PKT_QOS_L (75),
.PKT_DATA_SIDEBAND_H (73),
.PKT_DATA_SIDEBAND_L (73),
.PKT_ADDR_SIDEBAND_H (72),
.PKT_ADDR_SIDEBAND_L (72),
.PKT_BURST_TYPE_H (71),
.PKT_BURST_TYPE_L (70),
.PKT_CACHE_H (93),
.PKT_CACHE_L (90),
.PKT_THREAD_ID_H (86),
.PKT_THREAD_ID_L (86),
.PKT_BURST_SIZE_H (69),
.PKT_BURST_SIZE_L (67),
.PKT_TRANS_EXCLUSIVE (60),
.PKT_TRANS_LOCK (59),
.PKT_BEGIN_BURST (74),
.PKT_PROTECTION_H (89),
.PKT_PROTECTION_L (87),
.PKT_BURSTWRAP_H (66),
.PKT_BURSTWRAP_L (64),
.PKT_BYTE_CNT_H (63),
.PKT_BYTE_CNT_L (61),
.PKT_ADDR_H (54),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (55),
.PKT_TRANS_POSTED (56),
.PKT_TRANS_WRITE (57),
.PKT_TRANS_READ (58),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (80),
.PKT_SRC_ID_L (76),
.PKT_DEST_ID_H (85),
.PKT_DEST_ID_L (81),
.ST_DATA_W (99),
.ST_CHANNEL_W (32),
.AV_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_RSP (0),
.ID (1),
.BURSTWRAP_VALUE (3),
.CACHE_VALUE (0),
.SECURE_ACCESS_BIT (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) nios2_qsys_0_instruction_master_agent (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.av_address (nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_address), // av.address
.av_write (nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_write), // .write
.av_read (nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_read), // .read
.av_writedata (nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_writedata), // .writedata
.av_readdata (nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_readdata), // .readdata
.av_waitrequest (nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_waitrequest), // .waitrequest
.av_readdatavalid (nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
.av_byteenable (nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_byteenable), // .byteenable
.av_burstcount (nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_burstcount), // .burstcount
.av_debugaccess (nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_debugaccess), // .debugaccess
.av_lock (nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_lock), // .lock
.cp_valid (nios2_qsys_0_instruction_master_agent_cp_valid), // cp.valid
.cp_data (nios2_qsys_0_instruction_master_agent_cp_data), // .data
.cp_startofpacket (nios2_qsys_0_instruction_master_agent_cp_startofpacket), // .startofpacket
.cp_endofpacket (nios2_qsys_0_instruction_master_agent_cp_endofpacket), // .endofpacket
.cp_ready (nios2_qsys_0_instruction_master_agent_cp_ready), // .ready
.rp_valid (rsp_mux_001_src_valid), // rp.valid
.rp_data (rsp_mux_001_src_data), // .data
.rp_channel (rsp_mux_001_src_channel), // .channel
.rp_startofpacket (rsp_mux_001_src_startofpacket), // .startofpacket
.rp_endofpacket (rsp_mux_001_src_endofpacket), // .endofpacket
.rp_ready (rsp_mux_001_src_ready), // .ready
.av_response (), // (terminated)
.av_writeresponsevalid () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_ORI_BURST_SIZE_H (98),
.PKT_ORI_BURST_SIZE_L (96),
.PKT_RESPONSE_STATUS_H (95),
.PKT_RESPONSE_STATUS_L (94),
.PKT_BURST_SIZE_H (69),
.PKT_BURST_SIZE_L (67),
.PKT_TRANS_LOCK (59),
.PKT_BEGIN_BURST (74),
.PKT_PROTECTION_H (89),
.PKT_PROTECTION_L (87),
.PKT_BURSTWRAP_H (66),
.PKT_BURSTWRAP_L (64),
.PKT_BYTE_CNT_H (63),
.PKT_BYTE_CNT_L (61),
.PKT_ADDR_H (54),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (55),
.PKT_TRANS_POSTED (56),
.PKT_TRANS_WRITE (57),
.PKT_TRANS_READ (58),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (80),
.PKT_SRC_ID_L (76),
.PKT_DEST_ID_H (85),
.PKT_DEST_ID_L (81),
.PKT_SYMBOL_W (8),
.ST_CHANNEL_W (32),
.ST_DATA_W (99),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) jtag_uart_0_avalon_jtag_slave_agent (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (jtag_uart_0_avalon_jtag_slave_agent_m0_address), // m0.address
.m0_burstcount (jtag_uart_0_avalon_jtag_slave_agent_m0_burstcount), // .burstcount
.m0_byteenable (jtag_uart_0_avalon_jtag_slave_agent_m0_byteenable), // .byteenable
.m0_debugaccess (jtag_uart_0_avalon_jtag_slave_agent_m0_debugaccess), // .debugaccess
.m0_lock (jtag_uart_0_avalon_jtag_slave_agent_m0_lock), // .lock
.m0_readdata (jtag_uart_0_avalon_jtag_slave_agent_m0_readdata), // .readdata
.m0_readdatavalid (jtag_uart_0_avalon_jtag_slave_agent_m0_readdatavalid), // .readdatavalid
.m0_read (jtag_uart_0_avalon_jtag_slave_agent_m0_read), // .read
.m0_waitrequest (jtag_uart_0_avalon_jtag_slave_agent_m0_waitrequest), // .waitrequest
.m0_writedata (jtag_uart_0_avalon_jtag_slave_agent_m0_writedata), // .writedata
.m0_write (jtag_uart_0_avalon_jtag_slave_agent_m0_write), // .write
.rp_endofpacket (jtag_uart_0_avalon_jtag_slave_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (jtag_uart_0_avalon_jtag_slave_agent_rp_ready), // .ready
.rp_valid (jtag_uart_0_avalon_jtag_slave_agent_rp_valid), // .valid
.rp_data (jtag_uart_0_avalon_jtag_slave_agent_rp_data), // .data
.rp_startofpacket (jtag_uart_0_avalon_jtag_slave_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_mux_src_ready), // cp.ready
.cp_valid (cmd_mux_src_valid), // .valid
.cp_data (cmd_mux_src_data), // .data
.cp_startofpacket (cmd_mux_src_startofpacket), // .startofpacket
.cp_endofpacket (cmd_mux_src_endofpacket), // .endofpacket
.cp_channel (cmd_mux_src_channel), // .channel
.rf_sink_ready (jtag_uart_0_avalon_jtag_slave_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (jtag_uart_0_avalon_jtag_slave_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (jtag_uart_0_avalon_jtag_slave_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (jtag_uart_0_avalon_jtag_slave_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (jtag_uart_0_avalon_jtag_slave_agent_rsp_fifo_out_data), // .data
.rf_source_ready (jtag_uart_0_avalon_jtag_slave_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (jtag_uart_0_avalon_jtag_slave_agent_rf_source_valid), // .valid
.rf_source_startofpacket (jtag_uart_0_avalon_jtag_slave_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (jtag_uart_0_avalon_jtag_slave_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (jtag_uart_0_avalon_jtag_slave_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (jtag_uart_0_avalon_jtag_slave_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (jtag_uart_0_avalon_jtag_slave_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_sink_data (jtag_uart_0_avalon_jtag_slave_agent_rdata_fifo_src_data), // .data
.rdata_fifo_src_ready (jtag_uart_0_avalon_jtag_slave_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (jtag_uart_0_avalon_jtag_slave_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (jtag_uart_0_avalon_jtag_slave_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (100),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) jtag_uart_0_avalon_jtag_slave_agent_rsp_fifo (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (jtag_uart_0_avalon_jtag_slave_agent_rf_source_data), // in.data
.in_valid (jtag_uart_0_avalon_jtag_slave_agent_rf_source_valid), // .valid
.in_ready (jtag_uart_0_avalon_jtag_slave_agent_rf_source_ready), // .ready
.in_startofpacket (jtag_uart_0_avalon_jtag_slave_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (jtag_uart_0_avalon_jtag_slave_agent_rf_source_endofpacket), // .endofpacket
.out_data (jtag_uart_0_avalon_jtag_slave_agent_rsp_fifo_out_data), // out.data
.out_valid (jtag_uart_0_avalon_jtag_slave_agent_rsp_fifo_out_valid), // .valid
.out_ready (jtag_uart_0_avalon_jtag_slave_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (jtag_uart_0_avalon_jtag_slave_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (jtag_uart_0_avalon_jtag_slave_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_ORI_BURST_SIZE_H (98),
.PKT_ORI_BURST_SIZE_L (96),
.PKT_RESPONSE_STATUS_H (95),
.PKT_RESPONSE_STATUS_L (94),
.PKT_BURST_SIZE_H (69),
.PKT_BURST_SIZE_L (67),
.PKT_TRANS_LOCK (59),
.PKT_BEGIN_BURST (74),
.PKT_PROTECTION_H (89),
.PKT_PROTECTION_L (87),
.PKT_BURSTWRAP_H (66),
.PKT_BURSTWRAP_L (64),
.PKT_BYTE_CNT_H (63),
.PKT_BYTE_CNT_L (61),
.PKT_ADDR_H (54),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (55),
.PKT_TRANS_POSTED (56),
.PKT_TRANS_WRITE (57),
.PKT_TRANS_READ (58),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (80),
.PKT_SRC_ID_L (76),
.PKT_DEST_ID_H (85),
.PKT_DEST_ID_L (81),
.PKT_SYMBOL_W (8),
.ST_CHANNEL_W (32),
.ST_DATA_W (99),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) nios2_qsys_0_debug_mem_slave_agent (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (nios2_qsys_0_debug_mem_slave_agent_m0_address), // m0.address
.m0_burstcount (nios2_qsys_0_debug_mem_slave_agent_m0_burstcount), // .burstcount
.m0_byteenable (nios2_qsys_0_debug_mem_slave_agent_m0_byteenable), // .byteenable
.m0_debugaccess (nios2_qsys_0_debug_mem_slave_agent_m0_debugaccess), // .debugaccess
.m0_lock (nios2_qsys_0_debug_mem_slave_agent_m0_lock), // .lock
.m0_readdata (nios2_qsys_0_debug_mem_slave_agent_m0_readdata), // .readdata
.m0_readdatavalid (nios2_qsys_0_debug_mem_slave_agent_m0_readdatavalid), // .readdatavalid
.m0_read (nios2_qsys_0_debug_mem_slave_agent_m0_read), // .read
.m0_waitrequest (nios2_qsys_0_debug_mem_slave_agent_m0_waitrequest), // .waitrequest
.m0_writedata (nios2_qsys_0_debug_mem_slave_agent_m0_writedata), // .writedata
.m0_write (nios2_qsys_0_debug_mem_slave_agent_m0_write), // .write
.rp_endofpacket (nios2_qsys_0_debug_mem_slave_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (nios2_qsys_0_debug_mem_slave_agent_rp_ready), // .ready
.rp_valid (nios2_qsys_0_debug_mem_slave_agent_rp_valid), // .valid
.rp_data (nios2_qsys_0_debug_mem_slave_agent_rp_data), // .data
.rp_startofpacket (nios2_qsys_0_debug_mem_slave_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_mux_001_src_ready), // cp.ready
.cp_valid (cmd_mux_001_src_valid), // .valid
.cp_data (cmd_mux_001_src_data), // .data
.cp_startofpacket (cmd_mux_001_src_startofpacket), // .startofpacket
.cp_endofpacket (cmd_mux_001_src_endofpacket), // .endofpacket
.cp_channel (cmd_mux_001_src_channel), // .channel
.rf_sink_ready (nios2_qsys_0_debug_mem_slave_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (nios2_qsys_0_debug_mem_slave_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (nios2_qsys_0_debug_mem_slave_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (nios2_qsys_0_debug_mem_slave_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (nios2_qsys_0_debug_mem_slave_agent_rsp_fifo_out_data), // .data
.rf_source_ready (nios2_qsys_0_debug_mem_slave_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (nios2_qsys_0_debug_mem_slave_agent_rf_source_valid), // .valid
.rf_source_startofpacket (nios2_qsys_0_debug_mem_slave_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (nios2_qsys_0_debug_mem_slave_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (nios2_qsys_0_debug_mem_slave_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (nios2_qsys_0_debug_mem_slave_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (nios2_qsys_0_debug_mem_slave_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_sink_data (nios2_qsys_0_debug_mem_slave_agent_rdata_fifo_src_data), // .data
.rdata_fifo_src_ready (nios2_qsys_0_debug_mem_slave_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (nios2_qsys_0_debug_mem_slave_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (nios2_qsys_0_debug_mem_slave_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (100),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) nios2_qsys_0_debug_mem_slave_agent_rsp_fifo (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (nios2_qsys_0_debug_mem_slave_agent_rf_source_data), // in.data
.in_valid (nios2_qsys_0_debug_mem_slave_agent_rf_source_valid), // .valid
.in_ready (nios2_qsys_0_debug_mem_slave_agent_rf_source_ready), // .ready
.in_startofpacket (nios2_qsys_0_debug_mem_slave_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (nios2_qsys_0_debug_mem_slave_agent_rf_source_endofpacket), // .endofpacket
.out_data (nios2_qsys_0_debug_mem_slave_agent_rsp_fifo_out_data), // out.data
.out_valid (nios2_qsys_0_debug_mem_slave_agent_rsp_fifo_out_valid), // .valid
.out_ready (nios2_qsys_0_debug_mem_slave_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (nios2_qsys_0_debug_mem_slave_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (nios2_qsys_0_debug_mem_slave_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_ORI_BURST_SIZE_H (98),
.PKT_ORI_BURST_SIZE_L (96),
.PKT_RESPONSE_STATUS_H (95),
.PKT_RESPONSE_STATUS_L (94),
.PKT_BURST_SIZE_H (69),
.PKT_BURST_SIZE_L (67),
.PKT_TRANS_LOCK (59),
.PKT_BEGIN_BURST (74),
.PKT_PROTECTION_H (89),
.PKT_PROTECTION_L (87),
.PKT_BURSTWRAP_H (66),
.PKT_BURSTWRAP_L (64),
.PKT_BYTE_CNT_H (63),
.PKT_BYTE_CNT_L (61),
.PKT_ADDR_H (54),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (55),
.PKT_TRANS_POSTED (56),
.PKT_TRANS_WRITE (57),
.PKT_TRANS_READ (58),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (80),
.PKT_SRC_ID_L (76),
.PKT_DEST_ID_H (85),
.PKT_DEST_ID_L (81),
.PKT_SYMBOL_W (8),
.ST_CHANNEL_W (32),
.ST_DATA_W (99),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) onchip_memory2_0_s1_agent (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (onchip_memory2_0_s1_agent_m0_address), // m0.address
.m0_burstcount (onchip_memory2_0_s1_agent_m0_burstcount), // .burstcount
.m0_byteenable (onchip_memory2_0_s1_agent_m0_byteenable), // .byteenable
.m0_debugaccess (onchip_memory2_0_s1_agent_m0_debugaccess), // .debugaccess
.m0_lock (onchip_memory2_0_s1_agent_m0_lock), // .lock
.m0_readdata (onchip_memory2_0_s1_agent_m0_readdata), // .readdata
.m0_readdatavalid (onchip_memory2_0_s1_agent_m0_readdatavalid), // .readdatavalid
.m0_read (onchip_memory2_0_s1_agent_m0_read), // .read
.m0_waitrequest (onchip_memory2_0_s1_agent_m0_waitrequest), // .waitrequest
.m0_writedata (onchip_memory2_0_s1_agent_m0_writedata), // .writedata
.m0_write (onchip_memory2_0_s1_agent_m0_write), // .write
.rp_endofpacket (onchip_memory2_0_s1_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (onchip_memory2_0_s1_agent_rp_ready), // .ready
.rp_valid (onchip_memory2_0_s1_agent_rp_valid), // .valid
.rp_data (onchip_memory2_0_s1_agent_rp_data), // .data
.rp_startofpacket (onchip_memory2_0_s1_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_mux_002_src_ready), // cp.ready
.cp_valid (cmd_mux_002_src_valid), // .valid
.cp_data (cmd_mux_002_src_data), // .data
.cp_startofpacket (cmd_mux_002_src_startofpacket), // .startofpacket
.cp_endofpacket (cmd_mux_002_src_endofpacket), // .endofpacket
.cp_channel (cmd_mux_002_src_channel), // .channel
.rf_sink_ready (onchip_memory2_0_s1_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (onchip_memory2_0_s1_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (onchip_memory2_0_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (onchip_memory2_0_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (onchip_memory2_0_s1_agent_rsp_fifo_out_data), // .data
.rf_source_ready (onchip_memory2_0_s1_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (onchip_memory2_0_s1_agent_rf_source_valid), // .valid
.rf_source_startofpacket (onchip_memory2_0_s1_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (onchip_memory2_0_s1_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (onchip_memory2_0_s1_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (onchip_memory2_0_s1_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (onchip_memory2_0_s1_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_sink_data (onchip_memory2_0_s1_agent_rdata_fifo_src_data), // .data
.rdata_fifo_src_ready (onchip_memory2_0_s1_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (onchip_memory2_0_s1_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (onchip_memory2_0_s1_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (100),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) onchip_memory2_0_s1_agent_rsp_fifo (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (onchip_memory2_0_s1_agent_rf_source_data), // in.data
.in_valid (onchip_memory2_0_s1_agent_rf_source_valid), // .valid
.in_ready (onchip_memory2_0_s1_agent_rf_source_ready), // .ready
.in_startofpacket (onchip_memory2_0_s1_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (onchip_memory2_0_s1_agent_rf_source_endofpacket), // .endofpacket
.out_data (onchip_memory2_0_s1_agent_rsp_fifo_out_data), // out.data
.out_valid (onchip_memory2_0_s1_agent_rsp_fifo_out_valid), // .valid
.out_ready (onchip_memory2_0_s1_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (onchip_memory2_0_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (onchip_memory2_0_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_ORI_BURST_SIZE_H (98),
.PKT_ORI_BURST_SIZE_L (96),
.PKT_RESPONSE_STATUS_H (95),
.PKT_RESPONSE_STATUS_L (94),
.PKT_BURST_SIZE_H (69),
.PKT_BURST_SIZE_L (67),
.PKT_TRANS_LOCK (59),
.PKT_BEGIN_BURST (74),
.PKT_PROTECTION_H (89),
.PKT_PROTECTION_L (87),
.PKT_BURSTWRAP_H (66),
.PKT_BURSTWRAP_L (64),
.PKT_BYTE_CNT_H (63),
.PKT_BYTE_CNT_L (61),
.PKT_ADDR_H (54),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (55),
.PKT_TRANS_POSTED (56),
.PKT_TRANS_WRITE (57),
.PKT_TRANS_READ (58),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (80),
.PKT_SRC_ID_L (76),
.PKT_DEST_ID_H (85),
.PKT_DEST_ID_L (81),
.PKT_SYMBOL_W (8),
.ST_CHANNEL_W (32),
.ST_DATA_W (99),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) leds_s1_agent (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (leds_s1_agent_m0_address), // m0.address
.m0_burstcount (leds_s1_agent_m0_burstcount), // .burstcount
.m0_byteenable (leds_s1_agent_m0_byteenable), // .byteenable
.m0_debugaccess (leds_s1_agent_m0_debugaccess), // .debugaccess
.m0_lock (leds_s1_agent_m0_lock), // .lock
.m0_readdata (leds_s1_agent_m0_readdata), // .readdata
.m0_readdatavalid (leds_s1_agent_m0_readdatavalid), // .readdatavalid
.m0_read (leds_s1_agent_m0_read), // .read
.m0_waitrequest (leds_s1_agent_m0_waitrequest), // .waitrequest
.m0_writedata (leds_s1_agent_m0_writedata), // .writedata
.m0_write (leds_s1_agent_m0_write), // .write
.rp_endofpacket (leds_s1_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (leds_s1_agent_rp_ready), // .ready
.rp_valid (leds_s1_agent_rp_valid), // .valid
.rp_data (leds_s1_agent_rp_data), // .data
.rp_startofpacket (leds_s1_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_mux_003_src_ready), // cp.ready
.cp_valid (cmd_mux_003_src_valid), // .valid
.cp_data (cmd_mux_003_src_data), // .data
.cp_startofpacket (cmd_mux_003_src_startofpacket), // .startofpacket
.cp_endofpacket (cmd_mux_003_src_endofpacket), // .endofpacket
.cp_channel (cmd_mux_003_src_channel), // .channel
.rf_sink_ready (leds_s1_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (leds_s1_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (leds_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (leds_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (leds_s1_agent_rsp_fifo_out_data), // .data
.rf_source_ready (leds_s1_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (leds_s1_agent_rf_source_valid), // .valid
.rf_source_startofpacket (leds_s1_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (leds_s1_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (leds_s1_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (leds_s1_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (leds_s1_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_sink_data (leds_s1_agent_rdata_fifo_src_data), // .data
.rdata_fifo_src_ready (leds_s1_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (leds_s1_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (leds_s1_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (100),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) leds_s1_agent_rsp_fifo (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (leds_s1_agent_rf_source_data), // in.data
.in_valid (leds_s1_agent_rf_source_valid), // .valid
.in_ready (leds_s1_agent_rf_source_ready), // .ready
.in_startofpacket (leds_s1_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (leds_s1_agent_rf_source_endofpacket), // .endofpacket
.out_data (leds_s1_agent_rsp_fifo_out_data), // out.data
.out_valid (leds_s1_agent_rsp_fifo_out_valid), // .valid
.out_ready (leds_s1_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (leds_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (leds_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_ORI_BURST_SIZE_H (98),
.PKT_ORI_BURST_SIZE_L (96),
.PKT_RESPONSE_STATUS_H (95),
.PKT_RESPONSE_STATUS_L (94),
.PKT_BURST_SIZE_H (69),
.PKT_BURST_SIZE_L (67),
.PKT_TRANS_LOCK (59),
.PKT_BEGIN_BURST (74),
.PKT_PROTECTION_H (89),
.PKT_PROTECTION_L (87),
.PKT_BURSTWRAP_H (66),
.PKT_BURSTWRAP_L (64),
.PKT_BYTE_CNT_H (63),
.PKT_BYTE_CNT_L (61),
.PKT_ADDR_H (54),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (55),
.PKT_TRANS_POSTED (56),
.PKT_TRANS_WRITE (57),
.PKT_TRANS_READ (58),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (80),
.PKT_SRC_ID_L (76),
.PKT_DEST_ID_H (85),
.PKT_DEST_ID_L (81),
.PKT_SYMBOL_W (8),
.ST_CHANNEL_W (32),
.ST_DATA_W (99),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) switches_s1_agent (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (switches_s1_agent_m0_address), // m0.address
.m0_burstcount (switches_s1_agent_m0_burstcount), // .burstcount
.m0_byteenable (switches_s1_agent_m0_byteenable), // .byteenable
.m0_debugaccess (switches_s1_agent_m0_debugaccess), // .debugaccess
.m0_lock (switches_s1_agent_m0_lock), // .lock
.m0_readdata (switches_s1_agent_m0_readdata), // .readdata
.m0_readdatavalid (switches_s1_agent_m0_readdatavalid), // .readdatavalid
.m0_read (switches_s1_agent_m0_read), // .read
.m0_waitrequest (switches_s1_agent_m0_waitrequest), // .waitrequest
.m0_writedata (switches_s1_agent_m0_writedata), // .writedata
.m0_write (switches_s1_agent_m0_write), // .write
.rp_endofpacket (switches_s1_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (switches_s1_agent_rp_ready), // .ready
.rp_valid (switches_s1_agent_rp_valid), // .valid
.rp_data (switches_s1_agent_rp_data), // .data
.rp_startofpacket (switches_s1_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_mux_004_src_ready), // cp.ready
.cp_valid (cmd_mux_004_src_valid), // .valid
.cp_data (cmd_mux_004_src_data), // .data
.cp_startofpacket (cmd_mux_004_src_startofpacket), // .startofpacket
.cp_endofpacket (cmd_mux_004_src_endofpacket), // .endofpacket
.cp_channel (cmd_mux_004_src_channel), // .channel
.rf_sink_ready (switches_s1_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (switches_s1_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (switches_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (switches_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (switches_s1_agent_rsp_fifo_out_data), // .data
.rf_source_ready (switches_s1_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (switches_s1_agent_rf_source_valid), // .valid
.rf_source_startofpacket (switches_s1_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (switches_s1_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (switches_s1_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (switches_s1_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (switches_s1_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_sink_data (switches_s1_agent_rdata_fifo_src_data), // .data
.rdata_fifo_src_ready (switches_s1_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (switches_s1_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (switches_s1_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (100),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) switches_s1_agent_rsp_fifo (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (switches_s1_agent_rf_source_data), // in.data
.in_valid (switches_s1_agent_rf_source_valid), // .valid
.in_ready (switches_s1_agent_rf_source_ready), // .ready
.in_startofpacket (switches_s1_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (switches_s1_agent_rf_source_endofpacket), // .endofpacket
.out_data (switches_s1_agent_rsp_fifo_out_data), // out.data
.out_valid (switches_s1_agent_rsp_fifo_out_valid), // .valid
.out_ready (switches_s1_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (switches_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (switches_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_ORI_BURST_SIZE_H (98),
.PKT_ORI_BURST_SIZE_L (96),
.PKT_RESPONSE_STATUS_H (95),
.PKT_RESPONSE_STATUS_L (94),
.PKT_BURST_SIZE_H (69),
.PKT_BURST_SIZE_L (67),
.PKT_TRANS_LOCK (59),
.PKT_BEGIN_BURST (74),
.PKT_PROTECTION_H (89),
.PKT_PROTECTION_L (87),
.PKT_BURSTWRAP_H (66),
.PKT_BURSTWRAP_L (64),
.PKT_BYTE_CNT_H (63),
.PKT_BYTE_CNT_L (61),
.PKT_ADDR_H (54),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (55),
.PKT_TRANS_POSTED (56),
.PKT_TRANS_WRITE (57),
.PKT_TRANS_READ (58),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (80),
.PKT_SRC_ID_L (76),
.PKT_DEST_ID_H (85),
.PKT_DEST_ID_L (81),
.PKT_SYMBOL_W (8),
.ST_CHANNEL_W (32),
.ST_DATA_W (99),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) sram_data_s1_agent (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (sram_data_s1_agent_m0_address), // m0.address
.m0_burstcount (sram_data_s1_agent_m0_burstcount), // .burstcount
.m0_byteenable (sram_data_s1_agent_m0_byteenable), // .byteenable
.m0_debugaccess (sram_data_s1_agent_m0_debugaccess), // .debugaccess
.m0_lock (sram_data_s1_agent_m0_lock), // .lock
.m0_readdata (sram_data_s1_agent_m0_readdata), // .readdata
.m0_readdatavalid (sram_data_s1_agent_m0_readdatavalid), // .readdatavalid
.m0_read (sram_data_s1_agent_m0_read), // .read
.m0_waitrequest (sram_data_s1_agent_m0_waitrequest), // .waitrequest
.m0_writedata (sram_data_s1_agent_m0_writedata), // .writedata
.m0_write (sram_data_s1_agent_m0_write), // .write
.rp_endofpacket (sram_data_s1_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (sram_data_s1_agent_rp_ready), // .ready
.rp_valid (sram_data_s1_agent_rp_valid), // .valid
.rp_data (sram_data_s1_agent_rp_data), // .data
.rp_startofpacket (sram_data_s1_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_mux_005_src_ready), // cp.ready
.cp_valid (cmd_mux_005_src_valid), // .valid
.cp_data (cmd_mux_005_src_data), // .data
.cp_startofpacket (cmd_mux_005_src_startofpacket), // .startofpacket
.cp_endofpacket (cmd_mux_005_src_endofpacket), // .endofpacket
.cp_channel (cmd_mux_005_src_channel), // .channel
.rf_sink_ready (sram_data_s1_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (sram_data_s1_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (sram_data_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (sram_data_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (sram_data_s1_agent_rsp_fifo_out_data), // .data
.rf_source_ready (sram_data_s1_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (sram_data_s1_agent_rf_source_valid), // .valid
.rf_source_startofpacket (sram_data_s1_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (sram_data_s1_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (sram_data_s1_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (sram_data_s1_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (sram_data_s1_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_sink_data (sram_data_s1_agent_rdata_fifo_src_data), // .data
.rdata_fifo_src_ready (sram_data_s1_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (sram_data_s1_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (sram_data_s1_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (100),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) sram_data_s1_agent_rsp_fifo (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (sram_data_s1_agent_rf_source_data), // in.data
.in_valid (sram_data_s1_agent_rf_source_valid), // .valid
.in_ready (sram_data_s1_agent_rf_source_ready), // .ready
.in_startofpacket (sram_data_s1_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (sram_data_s1_agent_rf_source_endofpacket), // .endofpacket
.out_data (sram_data_s1_agent_rsp_fifo_out_data), // out.data
.out_valid (sram_data_s1_agent_rsp_fifo_out_valid), // .valid
.out_ready (sram_data_s1_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (sram_data_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (sram_data_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_ORI_BURST_SIZE_H (98),
.PKT_ORI_BURST_SIZE_L (96),
.PKT_RESPONSE_STATUS_H (95),
.PKT_RESPONSE_STATUS_L (94),
.PKT_BURST_SIZE_H (69),
.PKT_BURST_SIZE_L (67),
.PKT_TRANS_LOCK (59),
.PKT_BEGIN_BURST (74),
.PKT_PROTECTION_H (89),
.PKT_PROTECTION_L (87),
.PKT_BURSTWRAP_H (66),
.PKT_BURSTWRAP_L (64),
.PKT_BYTE_CNT_H (63),
.PKT_BYTE_CNT_L (61),
.PKT_ADDR_H (54),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (55),
.PKT_TRANS_POSTED (56),
.PKT_TRANS_WRITE (57),
.PKT_TRANS_READ (58),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (80),
.PKT_SRC_ID_L (76),
.PKT_DEST_ID_H (85),
.PKT_DEST_ID_L (81),
.PKT_SYMBOL_W (8),
.ST_CHANNEL_W (32),
.ST_DATA_W (99),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) sram_addr_s1_agent (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (sram_addr_s1_agent_m0_address), // m0.address
.m0_burstcount (sram_addr_s1_agent_m0_burstcount), // .burstcount
.m0_byteenable (sram_addr_s1_agent_m0_byteenable), // .byteenable
.m0_debugaccess (sram_addr_s1_agent_m0_debugaccess), // .debugaccess
.m0_lock (sram_addr_s1_agent_m0_lock), // .lock
.m0_readdata (sram_addr_s1_agent_m0_readdata), // .readdata
.m0_readdatavalid (sram_addr_s1_agent_m0_readdatavalid), // .readdatavalid
.m0_read (sram_addr_s1_agent_m0_read), // .read
.m0_waitrequest (sram_addr_s1_agent_m0_waitrequest), // .waitrequest
.m0_writedata (sram_addr_s1_agent_m0_writedata), // .writedata
.m0_write (sram_addr_s1_agent_m0_write), // .write
.rp_endofpacket (sram_addr_s1_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (sram_addr_s1_agent_rp_ready), // .ready
.rp_valid (sram_addr_s1_agent_rp_valid), // .valid
.rp_data (sram_addr_s1_agent_rp_data), // .data
.rp_startofpacket (sram_addr_s1_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_mux_006_src_ready), // cp.ready
.cp_valid (cmd_mux_006_src_valid), // .valid
.cp_data (cmd_mux_006_src_data), // .data
.cp_startofpacket (cmd_mux_006_src_startofpacket), // .startofpacket
.cp_endofpacket (cmd_mux_006_src_endofpacket), // .endofpacket
.cp_channel (cmd_mux_006_src_channel), // .channel
.rf_sink_ready (sram_addr_s1_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (sram_addr_s1_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (sram_addr_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (sram_addr_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (sram_addr_s1_agent_rsp_fifo_out_data), // .data
.rf_source_ready (sram_addr_s1_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (sram_addr_s1_agent_rf_source_valid), // .valid
.rf_source_startofpacket (sram_addr_s1_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (sram_addr_s1_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (sram_addr_s1_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (sram_addr_s1_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (sram_addr_s1_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_sink_data (sram_addr_s1_agent_rdata_fifo_src_data), // .data
.rdata_fifo_src_ready (sram_addr_s1_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (sram_addr_s1_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (sram_addr_s1_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (100),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) sram_addr_s1_agent_rsp_fifo (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (sram_addr_s1_agent_rf_source_data), // in.data
.in_valid (sram_addr_s1_agent_rf_source_valid), // .valid
.in_ready (sram_addr_s1_agent_rf_source_ready), // .ready
.in_startofpacket (sram_addr_s1_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (sram_addr_s1_agent_rf_source_endofpacket), // .endofpacket
.out_data (sram_addr_s1_agent_rsp_fifo_out_data), // out.data
.out_valid (sram_addr_s1_agent_rsp_fifo_out_valid), // .valid
.out_ready (sram_addr_s1_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (sram_addr_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (sram_addr_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_ORI_BURST_SIZE_H (98),
.PKT_ORI_BURST_SIZE_L (96),
.PKT_RESPONSE_STATUS_H (95),
.PKT_RESPONSE_STATUS_L (94),
.PKT_BURST_SIZE_H (69),
.PKT_BURST_SIZE_L (67),
.PKT_TRANS_LOCK (59),
.PKT_BEGIN_BURST (74),
.PKT_PROTECTION_H (89),
.PKT_PROTECTION_L (87),
.PKT_BURSTWRAP_H (66),
.PKT_BURSTWRAP_L (64),
.PKT_BYTE_CNT_H (63),
.PKT_BYTE_CNT_L (61),
.PKT_ADDR_H (54),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (55),
.PKT_TRANS_POSTED (56),
.PKT_TRANS_WRITE (57),
.PKT_TRANS_READ (58),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (80),
.PKT_SRC_ID_L (76),
.PKT_DEST_ID_H (85),
.PKT_DEST_ID_L (81),
.PKT_SYMBOL_W (8),
.ST_CHANNEL_W (32),
.ST_DATA_W (99),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) sram_read_write_s1_agent (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (sram_read_write_s1_agent_m0_address), // m0.address
.m0_burstcount (sram_read_write_s1_agent_m0_burstcount), // .burstcount
.m0_byteenable (sram_read_write_s1_agent_m0_byteenable), // .byteenable
.m0_debugaccess (sram_read_write_s1_agent_m0_debugaccess), // .debugaccess
.m0_lock (sram_read_write_s1_agent_m0_lock), // .lock
.m0_readdata (sram_read_write_s1_agent_m0_readdata), // .readdata
.m0_readdatavalid (sram_read_write_s1_agent_m0_readdatavalid), // .readdatavalid
.m0_read (sram_read_write_s1_agent_m0_read), // .read
.m0_waitrequest (sram_read_write_s1_agent_m0_waitrequest), // .waitrequest
.m0_writedata (sram_read_write_s1_agent_m0_writedata), // .writedata
.m0_write (sram_read_write_s1_agent_m0_write), // .write
.rp_endofpacket (sram_read_write_s1_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (sram_read_write_s1_agent_rp_ready), // .ready
.rp_valid (sram_read_write_s1_agent_rp_valid), // .valid
.rp_data (sram_read_write_s1_agent_rp_data), // .data
.rp_startofpacket (sram_read_write_s1_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_mux_007_src_ready), // cp.ready
.cp_valid (cmd_mux_007_src_valid), // .valid
.cp_data (cmd_mux_007_src_data), // .data
.cp_startofpacket (cmd_mux_007_src_startofpacket), // .startofpacket
.cp_endofpacket (cmd_mux_007_src_endofpacket), // .endofpacket
.cp_channel (cmd_mux_007_src_channel), // .channel
.rf_sink_ready (sram_read_write_s1_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (sram_read_write_s1_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (sram_read_write_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (sram_read_write_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (sram_read_write_s1_agent_rsp_fifo_out_data), // .data
.rf_source_ready (sram_read_write_s1_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (sram_read_write_s1_agent_rf_source_valid), // .valid
.rf_source_startofpacket (sram_read_write_s1_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (sram_read_write_s1_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (sram_read_write_s1_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (sram_read_write_s1_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (sram_read_write_s1_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_sink_data (sram_read_write_s1_agent_rdata_fifo_src_data), // .data
.rdata_fifo_src_ready (sram_read_write_s1_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (sram_read_write_s1_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (sram_read_write_s1_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (100),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) sram_read_write_s1_agent_rsp_fifo (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (sram_read_write_s1_agent_rf_source_data), // in.data
.in_valid (sram_read_write_s1_agent_rf_source_valid), // .valid
.in_ready (sram_read_write_s1_agent_rf_source_ready), // .ready
.in_startofpacket (sram_read_write_s1_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (sram_read_write_s1_agent_rf_source_endofpacket), // .endofpacket
.out_data (sram_read_write_s1_agent_rsp_fifo_out_data), // out.data
.out_valid (sram_read_write_s1_agent_rsp_fifo_out_valid), // .valid
.out_ready (sram_read_write_s1_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (sram_read_write_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (sram_read_write_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_ORI_BURST_SIZE_H (98),
.PKT_ORI_BURST_SIZE_L (96),
.PKT_RESPONSE_STATUS_H (95),
.PKT_RESPONSE_STATUS_L (94),
.PKT_BURST_SIZE_H (69),
.PKT_BURST_SIZE_L (67),
.PKT_TRANS_LOCK (59),
.PKT_BEGIN_BURST (74),
.PKT_PROTECTION_H (89),
.PKT_PROTECTION_L (87),
.PKT_BURSTWRAP_H (66),
.PKT_BURSTWRAP_L (64),
.PKT_BYTE_CNT_H (63),
.PKT_BYTE_CNT_L (61),
.PKT_ADDR_H (54),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (55),
.PKT_TRANS_POSTED (56),
.PKT_TRANS_WRITE (57),
.PKT_TRANS_READ (58),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (80),
.PKT_SRC_ID_L (76),
.PKT_DEST_ID_H (85),
.PKT_DEST_ID_L (81),
.PKT_SYMBOL_W (8),
.ST_CHANNEL_W (32),
.ST_DATA_W (99),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) sram_cs_s1_agent (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (sram_cs_s1_agent_m0_address), // m0.address
.m0_burstcount (sram_cs_s1_agent_m0_burstcount), // .burstcount
.m0_byteenable (sram_cs_s1_agent_m0_byteenable), // .byteenable
.m0_debugaccess (sram_cs_s1_agent_m0_debugaccess), // .debugaccess
.m0_lock (sram_cs_s1_agent_m0_lock), // .lock
.m0_readdata (sram_cs_s1_agent_m0_readdata), // .readdata
.m0_readdatavalid (sram_cs_s1_agent_m0_readdatavalid), // .readdatavalid
.m0_read (sram_cs_s1_agent_m0_read), // .read
.m0_waitrequest (sram_cs_s1_agent_m0_waitrequest), // .waitrequest
.m0_writedata (sram_cs_s1_agent_m0_writedata), // .writedata
.m0_write (sram_cs_s1_agent_m0_write), // .write
.rp_endofpacket (sram_cs_s1_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (sram_cs_s1_agent_rp_ready), // .ready
.rp_valid (sram_cs_s1_agent_rp_valid), // .valid
.rp_data (sram_cs_s1_agent_rp_data), // .data
.rp_startofpacket (sram_cs_s1_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_mux_008_src_ready), // cp.ready
.cp_valid (cmd_mux_008_src_valid), // .valid
.cp_data (cmd_mux_008_src_data), // .data
.cp_startofpacket (cmd_mux_008_src_startofpacket), // .startofpacket
.cp_endofpacket (cmd_mux_008_src_endofpacket), // .endofpacket
.cp_channel (cmd_mux_008_src_channel), // .channel
.rf_sink_ready (sram_cs_s1_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (sram_cs_s1_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (sram_cs_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (sram_cs_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (sram_cs_s1_agent_rsp_fifo_out_data), // .data
.rf_source_ready (sram_cs_s1_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (sram_cs_s1_agent_rf_source_valid), // .valid
.rf_source_startofpacket (sram_cs_s1_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (sram_cs_s1_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (sram_cs_s1_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (sram_cs_s1_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (sram_cs_s1_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_sink_data (sram_cs_s1_agent_rdata_fifo_src_data), // .data
.rdata_fifo_src_ready (sram_cs_s1_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (sram_cs_s1_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (sram_cs_s1_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (100),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) sram_cs_s1_agent_rsp_fifo (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (sram_cs_s1_agent_rf_source_data), // in.data
.in_valid (sram_cs_s1_agent_rf_source_valid), // .valid
.in_ready (sram_cs_s1_agent_rf_source_ready), // .ready
.in_startofpacket (sram_cs_s1_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (sram_cs_s1_agent_rf_source_endofpacket), // .endofpacket
.out_data (sram_cs_s1_agent_rsp_fifo_out_data), // out.data
.out_valid (sram_cs_s1_agent_rsp_fifo_out_valid), // .valid
.out_ready (sram_cs_s1_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (sram_cs_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (sram_cs_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_ORI_BURST_SIZE_H (98),
.PKT_ORI_BURST_SIZE_L (96),
.PKT_RESPONSE_STATUS_H (95),
.PKT_RESPONSE_STATUS_L (94),
.PKT_BURST_SIZE_H (69),
.PKT_BURST_SIZE_L (67),
.PKT_TRANS_LOCK (59),
.PKT_BEGIN_BURST (74),
.PKT_PROTECTION_H (89),
.PKT_PROTECTION_L (87),
.PKT_BURSTWRAP_H (66),
.PKT_BURSTWRAP_L (64),
.PKT_BYTE_CNT_H (63),
.PKT_BYTE_CNT_L (61),
.PKT_ADDR_H (54),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (55),
.PKT_TRANS_POSTED (56),
.PKT_TRANS_WRITE (57),
.PKT_TRANS_READ (58),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (80),
.PKT_SRC_ID_L (76),
.PKT_DEST_ID_H (85),
.PKT_DEST_ID_L (81),
.PKT_SYMBOL_W (8),
.ST_CHANNEL_W (32),
.ST_DATA_W (99),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) sram_oe_s1_agent (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (sram_oe_s1_agent_m0_address), // m0.address
.m0_burstcount (sram_oe_s1_agent_m0_burstcount), // .burstcount
.m0_byteenable (sram_oe_s1_agent_m0_byteenable), // .byteenable
.m0_debugaccess (sram_oe_s1_agent_m0_debugaccess), // .debugaccess
.m0_lock (sram_oe_s1_agent_m0_lock), // .lock
.m0_readdata (sram_oe_s1_agent_m0_readdata), // .readdata
.m0_readdatavalid (sram_oe_s1_agent_m0_readdatavalid), // .readdatavalid
.m0_read (sram_oe_s1_agent_m0_read), // .read
.m0_waitrequest (sram_oe_s1_agent_m0_waitrequest), // .waitrequest
.m0_writedata (sram_oe_s1_agent_m0_writedata), // .writedata
.m0_write (sram_oe_s1_agent_m0_write), // .write
.rp_endofpacket (sram_oe_s1_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (sram_oe_s1_agent_rp_ready), // .ready
.rp_valid (sram_oe_s1_agent_rp_valid), // .valid
.rp_data (sram_oe_s1_agent_rp_data), // .data
.rp_startofpacket (sram_oe_s1_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_mux_009_src_ready), // cp.ready
.cp_valid (cmd_mux_009_src_valid), // .valid
.cp_data (cmd_mux_009_src_data), // .data
.cp_startofpacket (cmd_mux_009_src_startofpacket), // .startofpacket
.cp_endofpacket (cmd_mux_009_src_endofpacket), // .endofpacket
.cp_channel (cmd_mux_009_src_channel), // .channel
.rf_sink_ready (sram_oe_s1_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (sram_oe_s1_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (sram_oe_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (sram_oe_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (sram_oe_s1_agent_rsp_fifo_out_data), // .data
.rf_source_ready (sram_oe_s1_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (sram_oe_s1_agent_rf_source_valid), // .valid
.rf_source_startofpacket (sram_oe_s1_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (sram_oe_s1_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (sram_oe_s1_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (sram_oe_s1_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (sram_oe_s1_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_sink_data (sram_oe_s1_agent_rdata_fifo_src_data), // .data
.rdata_fifo_src_ready (sram_oe_s1_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (sram_oe_s1_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (sram_oe_s1_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (100),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) sram_oe_s1_agent_rsp_fifo (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (sram_oe_s1_agent_rf_source_data), // in.data
.in_valid (sram_oe_s1_agent_rf_source_valid), // .valid
.in_ready (sram_oe_s1_agent_rf_source_ready), // .ready
.in_startofpacket (sram_oe_s1_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (sram_oe_s1_agent_rf_source_endofpacket), // .endofpacket
.out_data (sram_oe_s1_agent_rsp_fifo_out_data), // out.data
.out_valid (sram_oe_s1_agent_rsp_fifo_out_valid), // .valid
.out_ready (sram_oe_s1_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (sram_oe_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (sram_oe_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_ORI_BURST_SIZE_H (98),
.PKT_ORI_BURST_SIZE_L (96),
.PKT_RESPONSE_STATUS_H (95),
.PKT_RESPONSE_STATUS_L (94),
.PKT_BURST_SIZE_H (69),
.PKT_BURST_SIZE_L (67),
.PKT_TRANS_LOCK (59),
.PKT_BEGIN_BURST (74),
.PKT_PROTECTION_H (89),
.PKT_PROTECTION_L (87),
.PKT_BURSTWRAP_H (66),
.PKT_BURSTWRAP_L (64),
.PKT_BYTE_CNT_H (63),
.PKT_BYTE_CNT_L (61),
.PKT_ADDR_H (54),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (55),
.PKT_TRANS_POSTED (56),
.PKT_TRANS_WRITE (57),
.PKT_TRANS_READ (58),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (80),
.PKT_SRC_ID_L (76),
.PKT_DEST_ID_H (85),
.PKT_DEST_ID_L (81),
.PKT_SYMBOL_W (8),
.ST_CHANNEL_W (32),
.ST_DATA_W (99),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) regfile_data_s1_agent (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (regfile_data_s1_agent_m0_address), // m0.address
.m0_burstcount (regfile_data_s1_agent_m0_burstcount), // .burstcount
.m0_byteenable (regfile_data_s1_agent_m0_byteenable), // .byteenable
.m0_debugaccess (regfile_data_s1_agent_m0_debugaccess), // .debugaccess
.m0_lock (regfile_data_s1_agent_m0_lock), // .lock
.m0_readdata (regfile_data_s1_agent_m0_readdata), // .readdata
.m0_readdatavalid (regfile_data_s1_agent_m0_readdatavalid), // .readdatavalid
.m0_read (regfile_data_s1_agent_m0_read), // .read
.m0_waitrequest (regfile_data_s1_agent_m0_waitrequest), // .waitrequest
.m0_writedata (regfile_data_s1_agent_m0_writedata), // .writedata
.m0_write (regfile_data_s1_agent_m0_write), // .write
.rp_endofpacket (regfile_data_s1_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (regfile_data_s1_agent_rp_ready), // .ready
.rp_valid (regfile_data_s1_agent_rp_valid), // .valid
.rp_data (regfile_data_s1_agent_rp_data), // .data
.rp_startofpacket (regfile_data_s1_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_mux_010_src_ready), // cp.ready
.cp_valid (cmd_mux_010_src_valid), // .valid
.cp_data (cmd_mux_010_src_data), // .data
.cp_startofpacket (cmd_mux_010_src_startofpacket), // .startofpacket
.cp_endofpacket (cmd_mux_010_src_endofpacket), // .endofpacket
.cp_channel (cmd_mux_010_src_channel), // .channel
.rf_sink_ready (regfile_data_s1_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (regfile_data_s1_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (regfile_data_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (regfile_data_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (regfile_data_s1_agent_rsp_fifo_out_data), // .data
.rf_source_ready (regfile_data_s1_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (regfile_data_s1_agent_rf_source_valid), // .valid
.rf_source_startofpacket (regfile_data_s1_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (regfile_data_s1_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (regfile_data_s1_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (regfile_data_s1_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (regfile_data_s1_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_sink_data (regfile_data_s1_agent_rdata_fifo_src_data), // .data
.rdata_fifo_src_ready (regfile_data_s1_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (regfile_data_s1_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (regfile_data_s1_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (100),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) regfile_data_s1_agent_rsp_fifo (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (regfile_data_s1_agent_rf_source_data), // in.data
.in_valid (regfile_data_s1_agent_rf_source_valid), // .valid
.in_ready (regfile_data_s1_agent_rf_source_ready), // .ready
.in_startofpacket (regfile_data_s1_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (regfile_data_s1_agent_rf_source_endofpacket), // .endofpacket
.out_data (regfile_data_s1_agent_rsp_fifo_out_data), // out.data
.out_valid (regfile_data_s1_agent_rsp_fifo_out_valid), // .valid
.out_ready (regfile_data_s1_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (regfile_data_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (regfile_data_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_ORI_BURST_SIZE_H (98),
.PKT_ORI_BURST_SIZE_L (96),
.PKT_RESPONSE_STATUS_H (95),
.PKT_RESPONSE_STATUS_L (94),
.PKT_BURST_SIZE_H (69),
.PKT_BURST_SIZE_L (67),
.PKT_TRANS_LOCK (59),
.PKT_BEGIN_BURST (74),
.PKT_PROTECTION_H (89),
.PKT_PROTECTION_L (87),
.PKT_BURSTWRAP_H (66),
.PKT_BURSTWRAP_L (64),
.PKT_BYTE_CNT_H (63),
.PKT_BYTE_CNT_L (61),
.PKT_ADDR_H (54),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (55),
.PKT_TRANS_POSTED (56),
.PKT_TRANS_WRITE (57),
.PKT_TRANS_READ (58),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (80),
.PKT_SRC_ID_L (76),
.PKT_DEST_ID_H (85),
.PKT_DEST_ID_L (81),
.PKT_SYMBOL_W (8),
.ST_CHANNEL_W (32),
.ST_DATA_W (99),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) regfile_reg1_s1_agent (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (regfile_reg1_s1_agent_m0_address), // m0.address
.m0_burstcount (regfile_reg1_s1_agent_m0_burstcount), // .burstcount
.m0_byteenable (regfile_reg1_s1_agent_m0_byteenable), // .byteenable
.m0_debugaccess (regfile_reg1_s1_agent_m0_debugaccess), // .debugaccess
.m0_lock (regfile_reg1_s1_agent_m0_lock), // .lock
.m0_readdata (regfile_reg1_s1_agent_m0_readdata), // .readdata
.m0_readdatavalid (regfile_reg1_s1_agent_m0_readdatavalid), // .readdatavalid
.m0_read (regfile_reg1_s1_agent_m0_read), // .read
.m0_waitrequest (regfile_reg1_s1_agent_m0_waitrequest), // .waitrequest
.m0_writedata (regfile_reg1_s1_agent_m0_writedata), // .writedata
.m0_write (regfile_reg1_s1_agent_m0_write), // .write
.rp_endofpacket (regfile_reg1_s1_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (regfile_reg1_s1_agent_rp_ready), // .ready
.rp_valid (regfile_reg1_s1_agent_rp_valid), // .valid
.rp_data (regfile_reg1_s1_agent_rp_data), // .data
.rp_startofpacket (regfile_reg1_s1_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_mux_011_src_ready), // cp.ready
.cp_valid (cmd_mux_011_src_valid), // .valid
.cp_data (cmd_mux_011_src_data), // .data
.cp_startofpacket (cmd_mux_011_src_startofpacket), // .startofpacket
.cp_endofpacket (cmd_mux_011_src_endofpacket), // .endofpacket
.cp_channel (cmd_mux_011_src_channel), // .channel
.rf_sink_ready (regfile_reg1_s1_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (regfile_reg1_s1_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (regfile_reg1_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (regfile_reg1_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (regfile_reg1_s1_agent_rsp_fifo_out_data), // .data
.rf_source_ready (regfile_reg1_s1_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (regfile_reg1_s1_agent_rf_source_valid), // .valid
.rf_source_startofpacket (regfile_reg1_s1_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (regfile_reg1_s1_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (regfile_reg1_s1_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (regfile_reg1_s1_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (regfile_reg1_s1_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_sink_data (regfile_reg1_s1_agent_rdata_fifo_src_data), // .data
.rdata_fifo_src_ready (regfile_reg1_s1_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (regfile_reg1_s1_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (regfile_reg1_s1_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (100),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) regfile_reg1_s1_agent_rsp_fifo (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (regfile_reg1_s1_agent_rf_source_data), // in.data
.in_valid (regfile_reg1_s1_agent_rf_source_valid), // .valid
.in_ready (regfile_reg1_s1_agent_rf_source_ready), // .ready
.in_startofpacket (regfile_reg1_s1_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (regfile_reg1_s1_agent_rf_source_endofpacket), // .endofpacket
.out_data (regfile_reg1_s1_agent_rsp_fifo_out_data), // out.data
.out_valid (regfile_reg1_s1_agent_rsp_fifo_out_valid), // .valid
.out_ready (regfile_reg1_s1_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (regfile_reg1_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (regfile_reg1_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_ORI_BURST_SIZE_H (98),
.PKT_ORI_BURST_SIZE_L (96),
.PKT_RESPONSE_STATUS_H (95),
.PKT_RESPONSE_STATUS_L (94),
.PKT_BURST_SIZE_H (69),
.PKT_BURST_SIZE_L (67),
.PKT_TRANS_LOCK (59),
.PKT_BEGIN_BURST (74),
.PKT_PROTECTION_H (89),
.PKT_PROTECTION_L (87),
.PKT_BURSTWRAP_H (66),
.PKT_BURSTWRAP_L (64),
.PKT_BYTE_CNT_H (63),
.PKT_BYTE_CNT_L (61),
.PKT_ADDR_H (54),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (55),
.PKT_TRANS_POSTED (56),
.PKT_TRANS_WRITE (57),
.PKT_TRANS_READ (58),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (80),
.PKT_SRC_ID_L (76),
.PKT_DEST_ID_H (85),
.PKT_DEST_ID_L (81),
.PKT_SYMBOL_W (8),
.ST_CHANNEL_W (32),
.ST_DATA_W (99),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) regfile_reg2_s1_agent (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (regfile_reg2_s1_agent_m0_address), // m0.address
.m0_burstcount (regfile_reg2_s1_agent_m0_burstcount), // .burstcount
.m0_byteenable (regfile_reg2_s1_agent_m0_byteenable), // .byteenable
.m0_debugaccess (regfile_reg2_s1_agent_m0_debugaccess), // .debugaccess
.m0_lock (regfile_reg2_s1_agent_m0_lock), // .lock
.m0_readdata (regfile_reg2_s1_agent_m0_readdata), // .readdata
.m0_readdatavalid (regfile_reg2_s1_agent_m0_readdatavalid), // .readdatavalid
.m0_read (regfile_reg2_s1_agent_m0_read), // .read
.m0_waitrequest (regfile_reg2_s1_agent_m0_waitrequest), // .waitrequest
.m0_writedata (regfile_reg2_s1_agent_m0_writedata), // .writedata
.m0_write (regfile_reg2_s1_agent_m0_write), // .write
.rp_endofpacket (regfile_reg2_s1_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (regfile_reg2_s1_agent_rp_ready), // .ready
.rp_valid (regfile_reg2_s1_agent_rp_valid), // .valid
.rp_data (regfile_reg2_s1_agent_rp_data), // .data
.rp_startofpacket (regfile_reg2_s1_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_mux_012_src_ready), // cp.ready
.cp_valid (cmd_mux_012_src_valid), // .valid
.cp_data (cmd_mux_012_src_data), // .data
.cp_startofpacket (cmd_mux_012_src_startofpacket), // .startofpacket
.cp_endofpacket (cmd_mux_012_src_endofpacket), // .endofpacket
.cp_channel (cmd_mux_012_src_channel), // .channel
.rf_sink_ready (regfile_reg2_s1_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (regfile_reg2_s1_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (regfile_reg2_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (regfile_reg2_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (regfile_reg2_s1_agent_rsp_fifo_out_data), // .data
.rf_source_ready (regfile_reg2_s1_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (regfile_reg2_s1_agent_rf_source_valid), // .valid
.rf_source_startofpacket (regfile_reg2_s1_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (regfile_reg2_s1_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (regfile_reg2_s1_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (regfile_reg2_s1_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (regfile_reg2_s1_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_sink_data (regfile_reg2_s1_agent_rdata_fifo_src_data), // .data
.rdata_fifo_src_ready (regfile_reg2_s1_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (regfile_reg2_s1_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (regfile_reg2_s1_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (100),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) regfile_reg2_s1_agent_rsp_fifo (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (regfile_reg2_s1_agent_rf_source_data), // in.data
.in_valid (regfile_reg2_s1_agent_rf_source_valid), // .valid
.in_ready (regfile_reg2_s1_agent_rf_source_ready), // .ready
.in_startofpacket (regfile_reg2_s1_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (regfile_reg2_s1_agent_rf_source_endofpacket), // .endofpacket
.out_data (regfile_reg2_s1_agent_rsp_fifo_out_data), // out.data
.out_valid (regfile_reg2_s1_agent_rsp_fifo_out_valid), // .valid
.out_ready (regfile_reg2_s1_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (regfile_reg2_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (regfile_reg2_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_ORI_BURST_SIZE_H (98),
.PKT_ORI_BURST_SIZE_L (96),
.PKT_RESPONSE_STATUS_H (95),
.PKT_RESPONSE_STATUS_L (94),
.PKT_BURST_SIZE_H (69),
.PKT_BURST_SIZE_L (67),
.PKT_TRANS_LOCK (59),
.PKT_BEGIN_BURST (74),
.PKT_PROTECTION_H (89),
.PKT_PROTECTION_L (87),
.PKT_BURSTWRAP_H (66),
.PKT_BURSTWRAP_L (64),
.PKT_BYTE_CNT_H (63),
.PKT_BYTE_CNT_L (61),
.PKT_ADDR_H (54),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (55),
.PKT_TRANS_POSTED (56),
.PKT_TRANS_WRITE (57),
.PKT_TRANS_READ (58),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (80),
.PKT_SRC_ID_L (76),
.PKT_DEST_ID_H (85),
.PKT_DEST_ID_L (81),
.PKT_SYMBOL_W (8),
.ST_CHANNEL_W (32),
.ST_DATA_W (99),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) regfile_r1sel_s1_agent (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (regfile_r1sel_s1_agent_m0_address), // m0.address
.m0_burstcount (regfile_r1sel_s1_agent_m0_burstcount), // .burstcount
.m0_byteenable (regfile_r1sel_s1_agent_m0_byteenable), // .byteenable
.m0_debugaccess (regfile_r1sel_s1_agent_m0_debugaccess), // .debugaccess
.m0_lock (regfile_r1sel_s1_agent_m0_lock), // .lock
.m0_readdata (regfile_r1sel_s1_agent_m0_readdata), // .readdata
.m0_readdatavalid (regfile_r1sel_s1_agent_m0_readdatavalid), // .readdatavalid
.m0_read (regfile_r1sel_s1_agent_m0_read), // .read
.m0_waitrequest (regfile_r1sel_s1_agent_m0_waitrequest), // .waitrequest
.m0_writedata (regfile_r1sel_s1_agent_m0_writedata), // .writedata
.m0_write (regfile_r1sel_s1_agent_m0_write), // .write
.rp_endofpacket (regfile_r1sel_s1_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (regfile_r1sel_s1_agent_rp_ready), // .ready
.rp_valid (regfile_r1sel_s1_agent_rp_valid), // .valid
.rp_data (regfile_r1sel_s1_agent_rp_data), // .data
.rp_startofpacket (regfile_r1sel_s1_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_mux_013_src_ready), // cp.ready
.cp_valid (cmd_mux_013_src_valid), // .valid
.cp_data (cmd_mux_013_src_data), // .data
.cp_startofpacket (cmd_mux_013_src_startofpacket), // .startofpacket
.cp_endofpacket (cmd_mux_013_src_endofpacket), // .endofpacket
.cp_channel (cmd_mux_013_src_channel), // .channel
.rf_sink_ready (regfile_r1sel_s1_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (regfile_r1sel_s1_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (regfile_r1sel_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (regfile_r1sel_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (regfile_r1sel_s1_agent_rsp_fifo_out_data), // .data
.rf_source_ready (regfile_r1sel_s1_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (regfile_r1sel_s1_agent_rf_source_valid), // .valid
.rf_source_startofpacket (regfile_r1sel_s1_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (regfile_r1sel_s1_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (regfile_r1sel_s1_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (regfile_r1sel_s1_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (regfile_r1sel_s1_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_sink_data (regfile_r1sel_s1_agent_rdata_fifo_src_data), // .data
.rdata_fifo_src_ready (regfile_r1sel_s1_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (regfile_r1sel_s1_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (regfile_r1sel_s1_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (100),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) regfile_r1sel_s1_agent_rsp_fifo (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (regfile_r1sel_s1_agent_rf_source_data), // in.data
.in_valid (regfile_r1sel_s1_agent_rf_source_valid), // .valid
.in_ready (regfile_r1sel_s1_agent_rf_source_ready), // .ready
.in_startofpacket (regfile_r1sel_s1_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (regfile_r1sel_s1_agent_rf_source_endofpacket), // .endofpacket
.out_data (regfile_r1sel_s1_agent_rsp_fifo_out_data), // out.data
.out_valid (regfile_r1sel_s1_agent_rsp_fifo_out_valid), // .valid
.out_ready (regfile_r1sel_s1_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (regfile_r1sel_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (regfile_r1sel_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_ORI_BURST_SIZE_H (98),
.PKT_ORI_BURST_SIZE_L (96),
.PKT_RESPONSE_STATUS_H (95),
.PKT_RESPONSE_STATUS_L (94),
.PKT_BURST_SIZE_H (69),
.PKT_BURST_SIZE_L (67),
.PKT_TRANS_LOCK (59),
.PKT_BEGIN_BURST (74),
.PKT_PROTECTION_H (89),
.PKT_PROTECTION_L (87),
.PKT_BURSTWRAP_H (66),
.PKT_BURSTWRAP_L (64),
.PKT_BYTE_CNT_H (63),
.PKT_BYTE_CNT_L (61),
.PKT_ADDR_H (54),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (55),
.PKT_TRANS_POSTED (56),
.PKT_TRANS_WRITE (57),
.PKT_TRANS_READ (58),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (80),
.PKT_SRC_ID_L (76),
.PKT_DEST_ID_H (85),
.PKT_DEST_ID_L (81),
.PKT_SYMBOL_W (8),
.ST_CHANNEL_W (32),
.ST_DATA_W (99),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) regfile_r2sel_s1_agent (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (regfile_r2sel_s1_agent_m0_address), // m0.address
.m0_burstcount (regfile_r2sel_s1_agent_m0_burstcount), // .burstcount
.m0_byteenable (regfile_r2sel_s1_agent_m0_byteenable), // .byteenable
.m0_debugaccess (regfile_r2sel_s1_agent_m0_debugaccess), // .debugaccess
.m0_lock (regfile_r2sel_s1_agent_m0_lock), // .lock
.m0_readdata (regfile_r2sel_s1_agent_m0_readdata), // .readdata
.m0_readdatavalid (regfile_r2sel_s1_agent_m0_readdatavalid), // .readdatavalid
.m0_read (regfile_r2sel_s1_agent_m0_read), // .read
.m0_waitrequest (regfile_r2sel_s1_agent_m0_waitrequest), // .waitrequest
.m0_writedata (regfile_r2sel_s1_agent_m0_writedata), // .writedata
.m0_write (regfile_r2sel_s1_agent_m0_write), // .write
.rp_endofpacket (regfile_r2sel_s1_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (regfile_r2sel_s1_agent_rp_ready), // .ready
.rp_valid (regfile_r2sel_s1_agent_rp_valid), // .valid
.rp_data (regfile_r2sel_s1_agent_rp_data), // .data
.rp_startofpacket (regfile_r2sel_s1_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_mux_014_src_ready), // cp.ready
.cp_valid (cmd_mux_014_src_valid), // .valid
.cp_data (cmd_mux_014_src_data), // .data
.cp_startofpacket (cmd_mux_014_src_startofpacket), // .startofpacket
.cp_endofpacket (cmd_mux_014_src_endofpacket), // .endofpacket
.cp_channel (cmd_mux_014_src_channel), // .channel
.rf_sink_ready (regfile_r2sel_s1_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (regfile_r2sel_s1_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (regfile_r2sel_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (regfile_r2sel_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (regfile_r2sel_s1_agent_rsp_fifo_out_data), // .data
.rf_source_ready (regfile_r2sel_s1_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (regfile_r2sel_s1_agent_rf_source_valid), // .valid
.rf_source_startofpacket (regfile_r2sel_s1_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (regfile_r2sel_s1_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (regfile_r2sel_s1_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (regfile_r2sel_s1_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (regfile_r2sel_s1_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_sink_data (regfile_r2sel_s1_agent_rdata_fifo_src_data), // .data
.rdata_fifo_src_ready (regfile_r2sel_s1_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (regfile_r2sel_s1_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (regfile_r2sel_s1_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (100),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) regfile_r2sel_s1_agent_rsp_fifo (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (regfile_r2sel_s1_agent_rf_source_data), // in.data
.in_valid (regfile_r2sel_s1_agent_rf_source_valid), // .valid
.in_ready (regfile_r2sel_s1_agent_rf_source_ready), // .ready
.in_startofpacket (regfile_r2sel_s1_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (regfile_r2sel_s1_agent_rf_source_endofpacket), // .endofpacket
.out_data (regfile_r2sel_s1_agent_rsp_fifo_out_data), // out.data
.out_valid (regfile_r2sel_s1_agent_rsp_fifo_out_valid), // .valid
.out_ready (regfile_r2sel_s1_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (regfile_r2sel_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (regfile_r2sel_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_ORI_BURST_SIZE_H (98),
.PKT_ORI_BURST_SIZE_L (96),
.PKT_RESPONSE_STATUS_H (95),
.PKT_RESPONSE_STATUS_L (94),
.PKT_BURST_SIZE_H (69),
.PKT_BURST_SIZE_L (67),
.PKT_TRANS_LOCK (59),
.PKT_BEGIN_BURST (74),
.PKT_PROTECTION_H (89),
.PKT_PROTECTION_L (87),
.PKT_BURSTWRAP_H (66),
.PKT_BURSTWRAP_L (64),
.PKT_BYTE_CNT_H (63),
.PKT_BYTE_CNT_L (61),
.PKT_ADDR_H (54),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (55),
.PKT_TRANS_POSTED (56),
.PKT_TRANS_WRITE (57),
.PKT_TRANS_READ (58),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (80),
.PKT_SRC_ID_L (76),
.PKT_DEST_ID_H (85),
.PKT_DEST_ID_L (81),
.PKT_SYMBOL_W (8),
.ST_CHANNEL_W (32),
.ST_DATA_W (99),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) regfile_wsel_s1_agent (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (regfile_wsel_s1_agent_m0_address), // m0.address
.m0_burstcount (regfile_wsel_s1_agent_m0_burstcount), // .burstcount
.m0_byteenable (regfile_wsel_s1_agent_m0_byteenable), // .byteenable
.m0_debugaccess (regfile_wsel_s1_agent_m0_debugaccess), // .debugaccess
.m0_lock (regfile_wsel_s1_agent_m0_lock), // .lock
.m0_readdata (regfile_wsel_s1_agent_m0_readdata), // .readdata
.m0_readdatavalid (regfile_wsel_s1_agent_m0_readdatavalid), // .readdatavalid
.m0_read (regfile_wsel_s1_agent_m0_read), // .read
.m0_waitrequest (regfile_wsel_s1_agent_m0_waitrequest), // .waitrequest
.m0_writedata (regfile_wsel_s1_agent_m0_writedata), // .writedata
.m0_write (regfile_wsel_s1_agent_m0_write), // .write
.rp_endofpacket (regfile_wsel_s1_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (regfile_wsel_s1_agent_rp_ready), // .ready
.rp_valid (regfile_wsel_s1_agent_rp_valid), // .valid
.rp_data (regfile_wsel_s1_agent_rp_data), // .data
.rp_startofpacket (regfile_wsel_s1_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_mux_015_src_ready), // cp.ready
.cp_valid (cmd_mux_015_src_valid), // .valid
.cp_data (cmd_mux_015_src_data), // .data
.cp_startofpacket (cmd_mux_015_src_startofpacket), // .startofpacket
.cp_endofpacket (cmd_mux_015_src_endofpacket), // .endofpacket
.cp_channel (cmd_mux_015_src_channel), // .channel
.rf_sink_ready (regfile_wsel_s1_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (regfile_wsel_s1_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (regfile_wsel_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (regfile_wsel_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (regfile_wsel_s1_agent_rsp_fifo_out_data), // .data
.rf_source_ready (regfile_wsel_s1_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (regfile_wsel_s1_agent_rf_source_valid), // .valid
.rf_source_startofpacket (regfile_wsel_s1_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (regfile_wsel_s1_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (regfile_wsel_s1_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (regfile_wsel_s1_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (regfile_wsel_s1_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_sink_data (regfile_wsel_s1_agent_rdata_fifo_src_data), // .data
.rdata_fifo_src_ready (regfile_wsel_s1_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (regfile_wsel_s1_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (regfile_wsel_s1_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (100),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) regfile_wsel_s1_agent_rsp_fifo (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (regfile_wsel_s1_agent_rf_source_data), // in.data
.in_valid (regfile_wsel_s1_agent_rf_source_valid), // .valid
.in_ready (regfile_wsel_s1_agent_rf_source_ready), // .ready
.in_startofpacket (regfile_wsel_s1_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (regfile_wsel_s1_agent_rf_source_endofpacket), // .endofpacket
.out_data (regfile_wsel_s1_agent_rsp_fifo_out_data), // out.data
.out_valid (regfile_wsel_s1_agent_rsp_fifo_out_valid), // .valid
.out_ready (regfile_wsel_s1_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (regfile_wsel_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (regfile_wsel_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_ORI_BURST_SIZE_H (98),
.PKT_ORI_BURST_SIZE_L (96),
.PKT_RESPONSE_STATUS_H (95),
.PKT_RESPONSE_STATUS_L (94),
.PKT_BURST_SIZE_H (69),
.PKT_BURST_SIZE_L (67),
.PKT_TRANS_LOCK (59),
.PKT_BEGIN_BURST (74),
.PKT_PROTECTION_H (89),
.PKT_PROTECTION_L (87),
.PKT_BURSTWRAP_H (66),
.PKT_BURSTWRAP_L (64),
.PKT_BYTE_CNT_H (63),
.PKT_BYTE_CNT_L (61),
.PKT_ADDR_H (54),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (55),
.PKT_TRANS_POSTED (56),
.PKT_TRANS_WRITE (57),
.PKT_TRANS_READ (58),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (80),
.PKT_SRC_ID_L (76),
.PKT_DEST_ID_H (85),
.PKT_DEST_ID_L (81),
.PKT_SYMBOL_W (8),
.ST_CHANNEL_W (32),
.ST_DATA_W (99),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) regfile_we_s1_agent (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (regfile_we_s1_agent_m0_address), // m0.address
.m0_burstcount (regfile_we_s1_agent_m0_burstcount), // .burstcount
.m0_byteenable (regfile_we_s1_agent_m0_byteenable), // .byteenable
.m0_debugaccess (regfile_we_s1_agent_m0_debugaccess), // .debugaccess
.m0_lock (regfile_we_s1_agent_m0_lock), // .lock
.m0_readdata (regfile_we_s1_agent_m0_readdata), // .readdata
.m0_readdatavalid (regfile_we_s1_agent_m0_readdatavalid), // .readdatavalid
.m0_read (regfile_we_s1_agent_m0_read), // .read
.m0_waitrequest (regfile_we_s1_agent_m0_waitrequest), // .waitrequest
.m0_writedata (regfile_we_s1_agent_m0_writedata), // .writedata
.m0_write (regfile_we_s1_agent_m0_write), // .write
.rp_endofpacket (regfile_we_s1_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (regfile_we_s1_agent_rp_ready), // .ready
.rp_valid (regfile_we_s1_agent_rp_valid), // .valid
.rp_data (regfile_we_s1_agent_rp_data), // .data
.rp_startofpacket (regfile_we_s1_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_mux_016_src_ready), // cp.ready
.cp_valid (cmd_mux_016_src_valid), // .valid
.cp_data (cmd_mux_016_src_data), // .data
.cp_startofpacket (cmd_mux_016_src_startofpacket), // .startofpacket
.cp_endofpacket (cmd_mux_016_src_endofpacket), // .endofpacket
.cp_channel (cmd_mux_016_src_channel), // .channel
.rf_sink_ready (regfile_we_s1_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (regfile_we_s1_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (regfile_we_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (regfile_we_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (regfile_we_s1_agent_rsp_fifo_out_data), // .data
.rf_source_ready (regfile_we_s1_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (regfile_we_s1_agent_rf_source_valid), // .valid
.rf_source_startofpacket (regfile_we_s1_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (regfile_we_s1_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (regfile_we_s1_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (regfile_we_s1_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (regfile_we_s1_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_sink_data (regfile_we_s1_agent_rdata_fifo_src_data), // .data
.rdata_fifo_src_ready (regfile_we_s1_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (regfile_we_s1_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (regfile_we_s1_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (100),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) regfile_we_s1_agent_rsp_fifo (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (regfile_we_s1_agent_rf_source_data), // in.data
.in_valid (regfile_we_s1_agent_rf_source_valid), // .valid
.in_ready (regfile_we_s1_agent_rf_source_ready), // .ready
.in_startofpacket (regfile_we_s1_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (regfile_we_s1_agent_rf_source_endofpacket), // .endofpacket
.out_data (regfile_we_s1_agent_rsp_fifo_out_data), // out.data
.out_valid (regfile_we_s1_agent_rsp_fifo_out_valid), // .valid
.out_ready (regfile_we_s1_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (regfile_we_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (regfile_we_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_ORI_BURST_SIZE_H (98),
.PKT_ORI_BURST_SIZE_L (96),
.PKT_RESPONSE_STATUS_H (95),
.PKT_RESPONSE_STATUS_L (94),
.PKT_BURST_SIZE_H (69),
.PKT_BURST_SIZE_L (67),
.PKT_TRANS_LOCK (59),
.PKT_BEGIN_BURST (74),
.PKT_PROTECTION_H (89),
.PKT_PROTECTION_L (87),
.PKT_BURSTWRAP_H (66),
.PKT_BURSTWRAP_L (64),
.PKT_BYTE_CNT_H (63),
.PKT_BYTE_CNT_L (61),
.PKT_ADDR_H (54),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (55),
.PKT_TRANS_POSTED (56),
.PKT_TRANS_WRITE (57),
.PKT_TRANS_READ (58),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (80),
.PKT_SRC_ID_L (76),
.PKT_DEST_ID_H (85),
.PKT_DEST_ID_L (81),
.PKT_SYMBOL_W (8),
.ST_CHANNEL_W (32),
.ST_DATA_W (99),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) hex_0_s1_agent (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (hex_0_s1_agent_m0_address), // m0.address
.m0_burstcount (hex_0_s1_agent_m0_burstcount), // .burstcount
.m0_byteenable (hex_0_s1_agent_m0_byteenable), // .byteenable
.m0_debugaccess (hex_0_s1_agent_m0_debugaccess), // .debugaccess
.m0_lock (hex_0_s1_agent_m0_lock), // .lock
.m0_readdata (hex_0_s1_agent_m0_readdata), // .readdata
.m0_readdatavalid (hex_0_s1_agent_m0_readdatavalid), // .readdatavalid
.m0_read (hex_0_s1_agent_m0_read), // .read
.m0_waitrequest (hex_0_s1_agent_m0_waitrequest), // .waitrequest
.m0_writedata (hex_0_s1_agent_m0_writedata), // .writedata
.m0_write (hex_0_s1_agent_m0_write), // .write
.rp_endofpacket (hex_0_s1_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (hex_0_s1_agent_rp_ready), // .ready
.rp_valid (hex_0_s1_agent_rp_valid), // .valid
.rp_data (hex_0_s1_agent_rp_data), // .data
.rp_startofpacket (hex_0_s1_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_mux_017_src_ready), // cp.ready
.cp_valid (cmd_mux_017_src_valid), // .valid
.cp_data (cmd_mux_017_src_data), // .data
.cp_startofpacket (cmd_mux_017_src_startofpacket), // .startofpacket
.cp_endofpacket (cmd_mux_017_src_endofpacket), // .endofpacket
.cp_channel (cmd_mux_017_src_channel), // .channel
.rf_sink_ready (hex_0_s1_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (hex_0_s1_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (hex_0_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (hex_0_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (hex_0_s1_agent_rsp_fifo_out_data), // .data
.rf_source_ready (hex_0_s1_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (hex_0_s1_agent_rf_source_valid), // .valid
.rf_source_startofpacket (hex_0_s1_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (hex_0_s1_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (hex_0_s1_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (hex_0_s1_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (hex_0_s1_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_sink_data (hex_0_s1_agent_rdata_fifo_src_data), // .data
.rdata_fifo_src_ready (hex_0_s1_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (hex_0_s1_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (hex_0_s1_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (100),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) hex_0_s1_agent_rsp_fifo (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (hex_0_s1_agent_rf_source_data), // in.data
.in_valid (hex_0_s1_agent_rf_source_valid), // .valid
.in_ready (hex_0_s1_agent_rf_source_ready), // .ready
.in_startofpacket (hex_0_s1_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (hex_0_s1_agent_rf_source_endofpacket), // .endofpacket
.out_data (hex_0_s1_agent_rsp_fifo_out_data), // out.data
.out_valid (hex_0_s1_agent_rsp_fifo_out_valid), // .valid
.out_ready (hex_0_s1_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (hex_0_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (hex_0_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_ORI_BURST_SIZE_H (98),
.PKT_ORI_BURST_SIZE_L (96),
.PKT_RESPONSE_STATUS_H (95),
.PKT_RESPONSE_STATUS_L (94),
.PKT_BURST_SIZE_H (69),
.PKT_BURST_SIZE_L (67),
.PKT_TRANS_LOCK (59),
.PKT_BEGIN_BURST (74),
.PKT_PROTECTION_H (89),
.PKT_PROTECTION_L (87),
.PKT_BURSTWRAP_H (66),
.PKT_BURSTWRAP_L (64),
.PKT_BYTE_CNT_H (63),
.PKT_BYTE_CNT_L (61),
.PKT_ADDR_H (54),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (55),
.PKT_TRANS_POSTED (56),
.PKT_TRANS_WRITE (57),
.PKT_TRANS_READ (58),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (80),
.PKT_SRC_ID_L (76),
.PKT_DEST_ID_H (85),
.PKT_DEST_ID_L (81),
.PKT_SYMBOL_W (8),
.ST_CHANNEL_W (32),
.ST_DATA_W (99),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) hex_1_s1_agent (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (hex_1_s1_agent_m0_address), // m0.address
.m0_burstcount (hex_1_s1_agent_m0_burstcount), // .burstcount
.m0_byteenable (hex_1_s1_agent_m0_byteenable), // .byteenable
.m0_debugaccess (hex_1_s1_agent_m0_debugaccess), // .debugaccess
.m0_lock (hex_1_s1_agent_m0_lock), // .lock
.m0_readdata (hex_1_s1_agent_m0_readdata), // .readdata
.m0_readdatavalid (hex_1_s1_agent_m0_readdatavalid), // .readdatavalid
.m0_read (hex_1_s1_agent_m0_read), // .read
.m0_waitrequest (hex_1_s1_agent_m0_waitrequest), // .waitrequest
.m0_writedata (hex_1_s1_agent_m0_writedata), // .writedata
.m0_write (hex_1_s1_agent_m0_write), // .write
.rp_endofpacket (hex_1_s1_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (hex_1_s1_agent_rp_ready), // .ready
.rp_valid (hex_1_s1_agent_rp_valid), // .valid
.rp_data (hex_1_s1_agent_rp_data), // .data
.rp_startofpacket (hex_1_s1_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_mux_018_src_ready), // cp.ready
.cp_valid (cmd_mux_018_src_valid), // .valid
.cp_data (cmd_mux_018_src_data), // .data
.cp_startofpacket (cmd_mux_018_src_startofpacket), // .startofpacket
.cp_endofpacket (cmd_mux_018_src_endofpacket), // .endofpacket
.cp_channel (cmd_mux_018_src_channel), // .channel
.rf_sink_ready (hex_1_s1_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (hex_1_s1_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (hex_1_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (hex_1_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (hex_1_s1_agent_rsp_fifo_out_data), // .data
.rf_source_ready (hex_1_s1_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (hex_1_s1_agent_rf_source_valid), // .valid
.rf_source_startofpacket (hex_1_s1_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (hex_1_s1_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (hex_1_s1_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (hex_1_s1_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (hex_1_s1_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_sink_data (hex_1_s1_agent_rdata_fifo_src_data), // .data
.rdata_fifo_src_ready (hex_1_s1_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (hex_1_s1_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (hex_1_s1_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (100),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) hex_1_s1_agent_rsp_fifo (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (hex_1_s1_agent_rf_source_data), // in.data
.in_valid (hex_1_s1_agent_rf_source_valid), // .valid
.in_ready (hex_1_s1_agent_rf_source_ready), // .ready
.in_startofpacket (hex_1_s1_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (hex_1_s1_agent_rf_source_endofpacket), // .endofpacket
.out_data (hex_1_s1_agent_rsp_fifo_out_data), // out.data
.out_valid (hex_1_s1_agent_rsp_fifo_out_valid), // .valid
.out_ready (hex_1_s1_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (hex_1_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (hex_1_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_ORI_BURST_SIZE_H (98),
.PKT_ORI_BURST_SIZE_L (96),
.PKT_RESPONSE_STATUS_H (95),
.PKT_RESPONSE_STATUS_L (94),
.PKT_BURST_SIZE_H (69),
.PKT_BURST_SIZE_L (67),
.PKT_TRANS_LOCK (59),
.PKT_BEGIN_BURST (74),
.PKT_PROTECTION_H (89),
.PKT_PROTECTION_L (87),
.PKT_BURSTWRAP_H (66),
.PKT_BURSTWRAP_L (64),
.PKT_BYTE_CNT_H (63),
.PKT_BYTE_CNT_L (61),
.PKT_ADDR_H (54),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (55),
.PKT_TRANS_POSTED (56),
.PKT_TRANS_WRITE (57),
.PKT_TRANS_READ (58),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (80),
.PKT_SRC_ID_L (76),
.PKT_DEST_ID_H (85),
.PKT_DEST_ID_L (81),
.PKT_SYMBOL_W (8),
.ST_CHANNEL_W (32),
.ST_DATA_W (99),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) hex_2_s1_agent (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (hex_2_s1_agent_m0_address), // m0.address
.m0_burstcount (hex_2_s1_agent_m0_burstcount), // .burstcount
.m0_byteenable (hex_2_s1_agent_m0_byteenable), // .byteenable
.m0_debugaccess (hex_2_s1_agent_m0_debugaccess), // .debugaccess
.m0_lock (hex_2_s1_agent_m0_lock), // .lock
.m0_readdata (hex_2_s1_agent_m0_readdata), // .readdata
.m0_readdatavalid (hex_2_s1_agent_m0_readdatavalid), // .readdatavalid
.m0_read (hex_2_s1_agent_m0_read), // .read
.m0_waitrequest (hex_2_s1_agent_m0_waitrequest), // .waitrequest
.m0_writedata (hex_2_s1_agent_m0_writedata), // .writedata
.m0_write (hex_2_s1_agent_m0_write), // .write
.rp_endofpacket (hex_2_s1_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (hex_2_s1_agent_rp_ready), // .ready
.rp_valid (hex_2_s1_agent_rp_valid), // .valid
.rp_data (hex_2_s1_agent_rp_data), // .data
.rp_startofpacket (hex_2_s1_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_mux_019_src_ready), // cp.ready
.cp_valid (cmd_mux_019_src_valid), // .valid
.cp_data (cmd_mux_019_src_data), // .data
.cp_startofpacket (cmd_mux_019_src_startofpacket), // .startofpacket
.cp_endofpacket (cmd_mux_019_src_endofpacket), // .endofpacket
.cp_channel (cmd_mux_019_src_channel), // .channel
.rf_sink_ready (hex_2_s1_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (hex_2_s1_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (hex_2_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (hex_2_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (hex_2_s1_agent_rsp_fifo_out_data), // .data
.rf_source_ready (hex_2_s1_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (hex_2_s1_agent_rf_source_valid), // .valid
.rf_source_startofpacket (hex_2_s1_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (hex_2_s1_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (hex_2_s1_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (hex_2_s1_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (hex_2_s1_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_sink_data (hex_2_s1_agent_rdata_fifo_src_data), // .data
.rdata_fifo_src_ready (hex_2_s1_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (hex_2_s1_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (hex_2_s1_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (100),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) hex_2_s1_agent_rsp_fifo (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (hex_2_s1_agent_rf_source_data), // in.data
.in_valid (hex_2_s1_agent_rf_source_valid), // .valid
.in_ready (hex_2_s1_agent_rf_source_ready), // .ready
.in_startofpacket (hex_2_s1_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (hex_2_s1_agent_rf_source_endofpacket), // .endofpacket
.out_data (hex_2_s1_agent_rsp_fifo_out_data), // out.data
.out_valid (hex_2_s1_agent_rsp_fifo_out_valid), // .valid
.out_ready (hex_2_s1_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (hex_2_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (hex_2_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_ORI_BURST_SIZE_H (98),
.PKT_ORI_BURST_SIZE_L (96),
.PKT_RESPONSE_STATUS_H (95),
.PKT_RESPONSE_STATUS_L (94),
.PKT_BURST_SIZE_H (69),
.PKT_BURST_SIZE_L (67),
.PKT_TRANS_LOCK (59),
.PKT_BEGIN_BURST (74),
.PKT_PROTECTION_H (89),
.PKT_PROTECTION_L (87),
.PKT_BURSTWRAP_H (66),
.PKT_BURSTWRAP_L (64),
.PKT_BYTE_CNT_H (63),
.PKT_BYTE_CNT_L (61),
.PKT_ADDR_H (54),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (55),
.PKT_TRANS_POSTED (56),
.PKT_TRANS_WRITE (57),
.PKT_TRANS_READ (58),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (80),
.PKT_SRC_ID_L (76),
.PKT_DEST_ID_H (85),
.PKT_DEST_ID_L (81),
.PKT_SYMBOL_W (8),
.ST_CHANNEL_W (32),
.ST_DATA_W (99),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) hex_3_s1_agent (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (hex_3_s1_agent_m0_address), // m0.address
.m0_burstcount (hex_3_s1_agent_m0_burstcount), // .burstcount
.m0_byteenable (hex_3_s1_agent_m0_byteenable), // .byteenable
.m0_debugaccess (hex_3_s1_agent_m0_debugaccess), // .debugaccess
.m0_lock (hex_3_s1_agent_m0_lock), // .lock
.m0_readdata (hex_3_s1_agent_m0_readdata), // .readdata
.m0_readdatavalid (hex_3_s1_agent_m0_readdatavalid), // .readdatavalid
.m0_read (hex_3_s1_agent_m0_read), // .read
.m0_waitrequest (hex_3_s1_agent_m0_waitrequest), // .waitrequest
.m0_writedata (hex_3_s1_agent_m0_writedata), // .writedata
.m0_write (hex_3_s1_agent_m0_write), // .write
.rp_endofpacket (hex_3_s1_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (hex_3_s1_agent_rp_ready), // .ready
.rp_valid (hex_3_s1_agent_rp_valid), // .valid
.rp_data (hex_3_s1_agent_rp_data), // .data
.rp_startofpacket (hex_3_s1_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_mux_020_src_ready), // cp.ready
.cp_valid (cmd_mux_020_src_valid), // .valid
.cp_data (cmd_mux_020_src_data), // .data
.cp_startofpacket (cmd_mux_020_src_startofpacket), // .startofpacket
.cp_endofpacket (cmd_mux_020_src_endofpacket), // .endofpacket
.cp_channel (cmd_mux_020_src_channel), // .channel
.rf_sink_ready (hex_3_s1_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (hex_3_s1_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (hex_3_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (hex_3_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (hex_3_s1_agent_rsp_fifo_out_data), // .data
.rf_source_ready (hex_3_s1_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (hex_3_s1_agent_rf_source_valid), // .valid
.rf_source_startofpacket (hex_3_s1_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (hex_3_s1_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (hex_3_s1_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (hex_3_s1_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (hex_3_s1_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_sink_data (hex_3_s1_agent_rdata_fifo_src_data), // .data
.rdata_fifo_src_ready (hex_3_s1_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (hex_3_s1_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (hex_3_s1_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (100),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) hex_3_s1_agent_rsp_fifo (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (hex_3_s1_agent_rf_source_data), // in.data
.in_valid (hex_3_s1_agent_rf_source_valid), // .valid
.in_ready (hex_3_s1_agent_rf_source_ready), // .ready
.in_startofpacket (hex_3_s1_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (hex_3_s1_agent_rf_source_endofpacket), // .endofpacket
.out_data (hex_3_s1_agent_rsp_fifo_out_data), // out.data
.out_valid (hex_3_s1_agent_rsp_fifo_out_valid), // .valid
.out_ready (hex_3_s1_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (hex_3_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (hex_3_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_ORI_BURST_SIZE_H (98),
.PKT_ORI_BURST_SIZE_L (96),
.PKT_RESPONSE_STATUS_H (95),
.PKT_RESPONSE_STATUS_L (94),
.PKT_BURST_SIZE_H (69),
.PKT_BURST_SIZE_L (67),
.PKT_TRANS_LOCK (59),
.PKT_BEGIN_BURST (74),
.PKT_PROTECTION_H (89),
.PKT_PROTECTION_L (87),
.PKT_BURSTWRAP_H (66),
.PKT_BURSTWRAP_L (64),
.PKT_BYTE_CNT_H (63),
.PKT_BYTE_CNT_L (61),
.PKT_ADDR_H (54),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (55),
.PKT_TRANS_POSTED (56),
.PKT_TRANS_WRITE (57),
.PKT_TRANS_READ (58),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (80),
.PKT_SRC_ID_L (76),
.PKT_DEST_ID_H (85),
.PKT_DEST_ID_L (81),
.PKT_SYMBOL_W (8),
.ST_CHANNEL_W (32),
.ST_DATA_W (99),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) hex_4_s1_agent (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (hex_4_s1_agent_m0_address), // m0.address
.m0_burstcount (hex_4_s1_agent_m0_burstcount), // .burstcount
.m0_byteenable (hex_4_s1_agent_m0_byteenable), // .byteenable
.m0_debugaccess (hex_4_s1_agent_m0_debugaccess), // .debugaccess
.m0_lock (hex_4_s1_agent_m0_lock), // .lock
.m0_readdata (hex_4_s1_agent_m0_readdata), // .readdata
.m0_readdatavalid (hex_4_s1_agent_m0_readdatavalid), // .readdatavalid
.m0_read (hex_4_s1_agent_m0_read), // .read
.m0_waitrequest (hex_4_s1_agent_m0_waitrequest), // .waitrequest
.m0_writedata (hex_4_s1_agent_m0_writedata), // .writedata
.m0_write (hex_4_s1_agent_m0_write), // .write
.rp_endofpacket (hex_4_s1_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (hex_4_s1_agent_rp_ready), // .ready
.rp_valid (hex_4_s1_agent_rp_valid), // .valid
.rp_data (hex_4_s1_agent_rp_data), // .data
.rp_startofpacket (hex_4_s1_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_mux_021_src_ready), // cp.ready
.cp_valid (cmd_mux_021_src_valid), // .valid
.cp_data (cmd_mux_021_src_data), // .data
.cp_startofpacket (cmd_mux_021_src_startofpacket), // .startofpacket
.cp_endofpacket (cmd_mux_021_src_endofpacket), // .endofpacket
.cp_channel (cmd_mux_021_src_channel), // .channel
.rf_sink_ready (hex_4_s1_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (hex_4_s1_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (hex_4_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (hex_4_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (hex_4_s1_agent_rsp_fifo_out_data), // .data
.rf_source_ready (hex_4_s1_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (hex_4_s1_agent_rf_source_valid), // .valid
.rf_source_startofpacket (hex_4_s1_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (hex_4_s1_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (hex_4_s1_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (hex_4_s1_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (hex_4_s1_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_sink_data (hex_4_s1_agent_rdata_fifo_src_data), // .data
.rdata_fifo_src_ready (hex_4_s1_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (hex_4_s1_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (hex_4_s1_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (100),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) hex_4_s1_agent_rsp_fifo (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (hex_4_s1_agent_rf_source_data), // in.data
.in_valid (hex_4_s1_agent_rf_source_valid), // .valid
.in_ready (hex_4_s1_agent_rf_source_ready), // .ready
.in_startofpacket (hex_4_s1_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (hex_4_s1_agent_rf_source_endofpacket), // .endofpacket
.out_data (hex_4_s1_agent_rsp_fifo_out_data), // out.data
.out_valid (hex_4_s1_agent_rsp_fifo_out_valid), // .valid
.out_ready (hex_4_s1_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (hex_4_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (hex_4_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_ORI_BURST_SIZE_H (98),
.PKT_ORI_BURST_SIZE_L (96),
.PKT_RESPONSE_STATUS_H (95),
.PKT_RESPONSE_STATUS_L (94),
.PKT_BURST_SIZE_H (69),
.PKT_BURST_SIZE_L (67),
.PKT_TRANS_LOCK (59),
.PKT_BEGIN_BURST (74),
.PKT_PROTECTION_H (89),
.PKT_PROTECTION_L (87),
.PKT_BURSTWRAP_H (66),
.PKT_BURSTWRAP_L (64),
.PKT_BYTE_CNT_H (63),
.PKT_BYTE_CNT_L (61),
.PKT_ADDR_H (54),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (55),
.PKT_TRANS_POSTED (56),
.PKT_TRANS_WRITE (57),
.PKT_TRANS_READ (58),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (80),
.PKT_SRC_ID_L (76),
.PKT_DEST_ID_H (85),
.PKT_DEST_ID_L (81),
.PKT_SYMBOL_W (8),
.ST_CHANNEL_W (32),
.ST_DATA_W (99),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) hex_5_s1_agent (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (hex_5_s1_agent_m0_address), // m0.address
.m0_burstcount (hex_5_s1_agent_m0_burstcount), // .burstcount
.m0_byteenable (hex_5_s1_agent_m0_byteenable), // .byteenable
.m0_debugaccess (hex_5_s1_agent_m0_debugaccess), // .debugaccess
.m0_lock (hex_5_s1_agent_m0_lock), // .lock
.m0_readdata (hex_5_s1_agent_m0_readdata), // .readdata
.m0_readdatavalid (hex_5_s1_agent_m0_readdatavalid), // .readdatavalid
.m0_read (hex_5_s1_agent_m0_read), // .read
.m0_waitrequest (hex_5_s1_agent_m0_waitrequest), // .waitrequest
.m0_writedata (hex_5_s1_agent_m0_writedata), // .writedata
.m0_write (hex_5_s1_agent_m0_write), // .write
.rp_endofpacket (hex_5_s1_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (hex_5_s1_agent_rp_ready), // .ready
.rp_valid (hex_5_s1_agent_rp_valid), // .valid
.rp_data (hex_5_s1_agent_rp_data), // .data
.rp_startofpacket (hex_5_s1_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_mux_022_src_ready), // cp.ready
.cp_valid (cmd_mux_022_src_valid), // .valid
.cp_data (cmd_mux_022_src_data), // .data
.cp_startofpacket (cmd_mux_022_src_startofpacket), // .startofpacket
.cp_endofpacket (cmd_mux_022_src_endofpacket), // .endofpacket
.cp_channel (cmd_mux_022_src_channel), // .channel
.rf_sink_ready (hex_5_s1_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (hex_5_s1_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (hex_5_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (hex_5_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (hex_5_s1_agent_rsp_fifo_out_data), // .data
.rf_source_ready (hex_5_s1_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (hex_5_s1_agent_rf_source_valid), // .valid
.rf_source_startofpacket (hex_5_s1_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (hex_5_s1_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (hex_5_s1_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (hex_5_s1_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (hex_5_s1_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_sink_data (hex_5_s1_agent_rdata_fifo_src_data), // .data
.rdata_fifo_src_ready (hex_5_s1_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (hex_5_s1_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (hex_5_s1_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (100),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) hex_5_s1_agent_rsp_fifo (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (hex_5_s1_agent_rf_source_data), // in.data
.in_valid (hex_5_s1_agent_rf_source_valid), // .valid
.in_ready (hex_5_s1_agent_rf_source_ready), // .ready
.in_startofpacket (hex_5_s1_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (hex_5_s1_agent_rf_source_endofpacket), // .endofpacket
.out_data (hex_5_s1_agent_rsp_fifo_out_data), // out.data
.out_valid (hex_5_s1_agent_rsp_fifo_out_valid), // .valid
.out_ready (hex_5_s1_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (hex_5_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (hex_5_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_ORI_BURST_SIZE_H (98),
.PKT_ORI_BURST_SIZE_L (96),
.PKT_RESPONSE_STATUS_H (95),
.PKT_RESPONSE_STATUS_L (94),
.PKT_BURST_SIZE_H (69),
.PKT_BURST_SIZE_L (67),
.PKT_TRANS_LOCK (59),
.PKT_BEGIN_BURST (74),
.PKT_PROTECTION_H (89),
.PKT_PROTECTION_L (87),
.PKT_BURSTWRAP_H (66),
.PKT_BURSTWRAP_L (64),
.PKT_BYTE_CNT_H (63),
.PKT_BYTE_CNT_L (61),
.PKT_ADDR_H (54),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (55),
.PKT_TRANS_POSTED (56),
.PKT_TRANS_WRITE (57),
.PKT_TRANS_READ (58),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (80),
.PKT_SRC_ID_L (76),
.PKT_DEST_ID_H (85),
.PKT_DEST_ID_L (81),
.PKT_SYMBOL_W (8),
.ST_CHANNEL_W (32),
.ST_DATA_W (99),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) alu_a_s1_agent (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (alu_a_s1_agent_m0_address), // m0.address
.m0_burstcount (alu_a_s1_agent_m0_burstcount), // .burstcount
.m0_byteenable (alu_a_s1_agent_m0_byteenable), // .byteenable
.m0_debugaccess (alu_a_s1_agent_m0_debugaccess), // .debugaccess
.m0_lock (alu_a_s1_agent_m0_lock), // .lock
.m0_readdata (alu_a_s1_agent_m0_readdata), // .readdata
.m0_readdatavalid (alu_a_s1_agent_m0_readdatavalid), // .readdatavalid
.m0_read (alu_a_s1_agent_m0_read), // .read
.m0_waitrequest (alu_a_s1_agent_m0_waitrequest), // .waitrequest
.m0_writedata (alu_a_s1_agent_m0_writedata), // .writedata
.m0_write (alu_a_s1_agent_m0_write), // .write
.rp_endofpacket (alu_a_s1_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (alu_a_s1_agent_rp_ready), // .ready
.rp_valid (alu_a_s1_agent_rp_valid), // .valid
.rp_data (alu_a_s1_agent_rp_data), // .data
.rp_startofpacket (alu_a_s1_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_mux_023_src_ready), // cp.ready
.cp_valid (cmd_mux_023_src_valid), // .valid
.cp_data (cmd_mux_023_src_data), // .data
.cp_startofpacket (cmd_mux_023_src_startofpacket), // .startofpacket
.cp_endofpacket (cmd_mux_023_src_endofpacket), // .endofpacket
.cp_channel (cmd_mux_023_src_channel), // .channel
.rf_sink_ready (alu_a_s1_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (alu_a_s1_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (alu_a_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (alu_a_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (alu_a_s1_agent_rsp_fifo_out_data), // .data
.rf_source_ready (alu_a_s1_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (alu_a_s1_agent_rf_source_valid), // .valid
.rf_source_startofpacket (alu_a_s1_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (alu_a_s1_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (alu_a_s1_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (alu_a_s1_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (alu_a_s1_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_sink_data (alu_a_s1_agent_rdata_fifo_src_data), // .data
.rdata_fifo_src_ready (alu_a_s1_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (alu_a_s1_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (alu_a_s1_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (100),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) alu_a_s1_agent_rsp_fifo (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (alu_a_s1_agent_rf_source_data), // in.data
.in_valid (alu_a_s1_agent_rf_source_valid), // .valid
.in_ready (alu_a_s1_agent_rf_source_ready), // .ready
.in_startofpacket (alu_a_s1_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (alu_a_s1_agent_rf_source_endofpacket), // .endofpacket
.out_data (alu_a_s1_agent_rsp_fifo_out_data), // out.data
.out_valid (alu_a_s1_agent_rsp_fifo_out_valid), // .valid
.out_ready (alu_a_s1_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (alu_a_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (alu_a_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_ORI_BURST_SIZE_H (98),
.PKT_ORI_BURST_SIZE_L (96),
.PKT_RESPONSE_STATUS_H (95),
.PKT_RESPONSE_STATUS_L (94),
.PKT_BURST_SIZE_H (69),
.PKT_BURST_SIZE_L (67),
.PKT_TRANS_LOCK (59),
.PKT_BEGIN_BURST (74),
.PKT_PROTECTION_H (89),
.PKT_PROTECTION_L (87),
.PKT_BURSTWRAP_H (66),
.PKT_BURSTWRAP_L (64),
.PKT_BYTE_CNT_H (63),
.PKT_BYTE_CNT_L (61),
.PKT_ADDR_H (54),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (55),
.PKT_TRANS_POSTED (56),
.PKT_TRANS_WRITE (57),
.PKT_TRANS_READ (58),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (80),
.PKT_SRC_ID_L (76),
.PKT_DEST_ID_H (85),
.PKT_DEST_ID_L (81),
.PKT_SYMBOL_W (8),
.ST_CHANNEL_W (32),
.ST_DATA_W (99),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) alu_b_s1_agent (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (alu_b_s1_agent_m0_address), // m0.address
.m0_burstcount (alu_b_s1_agent_m0_burstcount), // .burstcount
.m0_byteenable (alu_b_s1_agent_m0_byteenable), // .byteenable
.m0_debugaccess (alu_b_s1_agent_m0_debugaccess), // .debugaccess
.m0_lock (alu_b_s1_agent_m0_lock), // .lock
.m0_readdata (alu_b_s1_agent_m0_readdata), // .readdata
.m0_readdatavalid (alu_b_s1_agent_m0_readdatavalid), // .readdatavalid
.m0_read (alu_b_s1_agent_m0_read), // .read
.m0_waitrequest (alu_b_s1_agent_m0_waitrequest), // .waitrequest
.m0_writedata (alu_b_s1_agent_m0_writedata), // .writedata
.m0_write (alu_b_s1_agent_m0_write), // .write
.rp_endofpacket (alu_b_s1_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (alu_b_s1_agent_rp_ready), // .ready
.rp_valid (alu_b_s1_agent_rp_valid), // .valid
.rp_data (alu_b_s1_agent_rp_data), // .data
.rp_startofpacket (alu_b_s1_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_mux_024_src_ready), // cp.ready
.cp_valid (cmd_mux_024_src_valid), // .valid
.cp_data (cmd_mux_024_src_data), // .data
.cp_startofpacket (cmd_mux_024_src_startofpacket), // .startofpacket
.cp_endofpacket (cmd_mux_024_src_endofpacket), // .endofpacket
.cp_channel (cmd_mux_024_src_channel), // .channel
.rf_sink_ready (alu_b_s1_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (alu_b_s1_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (alu_b_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (alu_b_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (alu_b_s1_agent_rsp_fifo_out_data), // .data
.rf_source_ready (alu_b_s1_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (alu_b_s1_agent_rf_source_valid), // .valid
.rf_source_startofpacket (alu_b_s1_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (alu_b_s1_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (alu_b_s1_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (alu_b_s1_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (alu_b_s1_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_sink_data (alu_b_s1_agent_rdata_fifo_src_data), // .data
.rdata_fifo_src_ready (alu_b_s1_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (alu_b_s1_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (alu_b_s1_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (100),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) alu_b_s1_agent_rsp_fifo (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (alu_b_s1_agent_rf_source_data), // in.data
.in_valid (alu_b_s1_agent_rf_source_valid), // .valid
.in_ready (alu_b_s1_agent_rf_source_ready), // .ready
.in_startofpacket (alu_b_s1_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (alu_b_s1_agent_rf_source_endofpacket), // .endofpacket
.out_data (alu_b_s1_agent_rsp_fifo_out_data), // out.data
.out_valid (alu_b_s1_agent_rsp_fifo_out_valid), // .valid
.out_ready (alu_b_s1_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (alu_b_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (alu_b_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_ORI_BURST_SIZE_H (98),
.PKT_ORI_BURST_SIZE_L (96),
.PKT_RESPONSE_STATUS_H (95),
.PKT_RESPONSE_STATUS_L (94),
.PKT_BURST_SIZE_H (69),
.PKT_BURST_SIZE_L (67),
.PKT_TRANS_LOCK (59),
.PKT_BEGIN_BURST (74),
.PKT_PROTECTION_H (89),
.PKT_PROTECTION_L (87),
.PKT_BURSTWRAP_H (66),
.PKT_BURSTWRAP_L (64),
.PKT_BYTE_CNT_H (63),
.PKT_BYTE_CNT_L (61),
.PKT_ADDR_H (54),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (55),
.PKT_TRANS_POSTED (56),
.PKT_TRANS_WRITE (57),
.PKT_TRANS_READ (58),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (80),
.PKT_SRC_ID_L (76),
.PKT_DEST_ID_H (85),
.PKT_DEST_ID_L (81),
.PKT_SYMBOL_W (8),
.ST_CHANNEL_W (32),
.ST_DATA_W (99),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) alu_control_s1_agent (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (alu_control_s1_agent_m0_address), // m0.address
.m0_burstcount (alu_control_s1_agent_m0_burstcount), // .burstcount
.m0_byteenable (alu_control_s1_agent_m0_byteenable), // .byteenable
.m0_debugaccess (alu_control_s1_agent_m0_debugaccess), // .debugaccess
.m0_lock (alu_control_s1_agent_m0_lock), // .lock
.m0_readdata (alu_control_s1_agent_m0_readdata), // .readdata
.m0_readdatavalid (alu_control_s1_agent_m0_readdatavalid), // .readdatavalid
.m0_read (alu_control_s1_agent_m0_read), // .read
.m0_waitrequest (alu_control_s1_agent_m0_waitrequest), // .waitrequest
.m0_writedata (alu_control_s1_agent_m0_writedata), // .writedata
.m0_write (alu_control_s1_agent_m0_write), // .write
.rp_endofpacket (alu_control_s1_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (alu_control_s1_agent_rp_ready), // .ready
.rp_valid (alu_control_s1_agent_rp_valid), // .valid
.rp_data (alu_control_s1_agent_rp_data), // .data
.rp_startofpacket (alu_control_s1_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_mux_025_src_ready), // cp.ready
.cp_valid (cmd_mux_025_src_valid), // .valid
.cp_data (cmd_mux_025_src_data), // .data
.cp_startofpacket (cmd_mux_025_src_startofpacket), // .startofpacket
.cp_endofpacket (cmd_mux_025_src_endofpacket), // .endofpacket
.cp_channel (cmd_mux_025_src_channel), // .channel
.rf_sink_ready (alu_control_s1_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (alu_control_s1_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (alu_control_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (alu_control_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (alu_control_s1_agent_rsp_fifo_out_data), // .data
.rf_source_ready (alu_control_s1_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (alu_control_s1_agent_rf_source_valid), // .valid
.rf_source_startofpacket (alu_control_s1_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (alu_control_s1_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (alu_control_s1_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (alu_control_s1_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (alu_control_s1_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_sink_data (alu_control_s1_agent_rdata_fifo_src_data), // .data
.rdata_fifo_src_ready (alu_control_s1_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (alu_control_s1_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (alu_control_s1_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (100),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) alu_control_s1_agent_rsp_fifo (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (alu_control_s1_agent_rf_source_data), // in.data
.in_valid (alu_control_s1_agent_rf_source_valid), // .valid
.in_ready (alu_control_s1_agent_rf_source_ready), // .ready
.in_startofpacket (alu_control_s1_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (alu_control_s1_agent_rf_source_endofpacket), // .endofpacket
.out_data (alu_control_s1_agent_rsp_fifo_out_data), // out.data
.out_valid (alu_control_s1_agent_rsp_fifo_out_valid), // .valid
.out_ready (alu_control_s1_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (alu_control_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (alu_control_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_ORI_BURST_SIZE_H (98),
.PKT_ORI_BURST_SIZE_L (96),
.PKT_RESPONSE_STATUS_H (95),
.PKT_RESPONSE_STATUS_L (94),
.PKT_BURST_SIZE_H (69),
.PKT_BURST_SIZE_L (67),
.PKT_TRANS_LOCK (59),
.PKT_BEGIN_BURST (74),
.PKT_PROTECTION_H (89),
.PKT_PROTECTION_L (87),
.PKT_BURSTWRAP_H (66),
.PKT_BURSTWRAP_L (64),
.PKT_BYTE_CNT_H (63),
.PKT_BYTE_CNT_L (61),
.PKT_ADDR_H (54),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (55),
.PKT_TRANS_POSTED (56),
.PKT_TRANS_WRITE (57),
.PKT_TRANS_READ (58),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (80),
.PKT_SRC_ID_L (76),
.PKT_DEST_ID_H (85),
.PKT_DEST_ID_L (81),
.PKT_SYMBOL_W (8),
.ST_CHANNEL_W (32),
.ST_DATA_W (99),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) alu_out_s1_agent (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (alu_out_s1_agent_m0_address), // m0.address
.m0_burstcount (alu_out_s1_agent_m0_burstcount), // .burstcount
.m0_byteenable (alu_out_s1_agent_m0_byteenable), // .byteenable
.m0_debugaccess (alu_out_s1_agent_m0_debugaccess), // .debugaccess
.m0_lock (alu_out_s1_agent_m0_lock), // .lock
.m0_readdata (alu_out_s1_agent_m0_readdata), // .readdata
.m0_readdatavalid (alu_out_s1_agent_m0_readdatavalid), // .readdatavalid
.m0_read (alu_out_s1_agent_m0_read), // .read
.m0_waitrequest (alu_out_s1_agent_m0_waitrequest), // .waitrequest
.m0_writedata (alu_out_s1_agent_m0_writedata), // .writedata
.m0_write (alu_out_s1_agent_m0_write), // .write
.rp_endofpacket (alu_out_s1_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (alu_out_s1_agent_rp_ready), // .ready
.rp_valid (alu_out_s1_agent_rp_valid), // .valid
.rp_data (alu_out_s1_agent_rp_data), // .data
.rp_startofpacket (alu_out_s1_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_mux_026_src_ready), // cp.ready
.cp_valid (cmd_mux_026_src_valid), // .valid
.cp_data (cmd_mux_026_src_data), // .data
.cp_startofpacket (cmd_mux_026_src_startofpacket), // .startofpacket
.cp_endofpacket (cmd_mux_026_src_endofpacket), // .endofpacket
.cp_channel (cmd_mux_026_src_channel), // .channel
.rf_sink_ready (alu_out_s1_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (alu_out_s1_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (alu_out_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (alu_out_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (alu_out_s1_agent_rsp_fifo_out_data), // .data
.rf_source_ready (alu_out_s1_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (alu_out_s1_agent_rf_source_valid), // .valid
.rf_source_startofpacket (alu_out_s1_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (alu_out_s1_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (alu_out_s1_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (alu_out_s1_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (alu_out_s1_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_sink_data (alu_out_s1_agent_rdata_fifo_src_data), // .data
.rdata_fifo_src_ready (alu_out_s1_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (alu_out_s1_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (alu_out_s1_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (100),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) alu_out_s1_agent_rsp_fifo (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (alu_out_s1_agent_rf_source_data), // in.data
.in_valid (alu_out_s1_agent_rf_source_valid), // .valid
.in_ready (alu_out_s1_agent_rf_source_ready), // .ready
.in_startofpacket (alu_out_s1_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (alu_out_s1_agent_rf_source_endofpacket), // .endofpacket
.out_data (alu_out_s1_agent_rsp_fifo_out_data), // out.data
.out_valid (alu_out_s1_agent_rsp_fifo_out_valid), // .valid
.out_ready (alu_out_s1_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (alu_out_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (alu_out_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_ORI_BURST_SIZE_H (98),
.PKT_ORI_BURST_SIZE_L (96),
.PKT_RESPONSE_STATUS_H (95),
.PKT_RESPONSE_STATUS_L (94),
.PKT_BURST_SIZE_H (69),
.PKT_BURST_SIZE_L (67),
.PKT_TRANS_LOCK (59),
.PKT_BEGIN_BURST (74),
.PKT_PROTECTION_H (89),
.PKT_PROTECTION_L (87),
.PKT_BURSTWRAP_H (66),
.PKT_BURSTWRAP_L (64),
.PKT_BYTE_CNT_H (63),
.PKT_BYTE_CNT_L (61),
.PKT_ADDR_H (54),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (55),
.PKT_TRANS_POSTED (56),
.PKT_TRANS_WRITE (57),
.PKT_TRANS_READ (58),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (80),
.PKT_SRC_ID_L (76),
.PKT_DEST_ID_H (85),
.PKT_DEST_ID_L (81),
.PKT_SYMBOL_W (8),
.ST_CHANNEL_W (32),
.ST_DATA_W (99),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) alu_zero_s1_agent (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (alu_zero_s1_agent_m0_address), // m0.address
.m0_burstcount (alu_zero_s1_agent_m0_burstcount), // .burstcount
.m0_byteenable (alu_zero_s1_agent_m0_byteenable), // .byteenable
.m0_debugaccess (alu_zero_s1_agent_m0_debugaccess), // .debugaccess
.m0_lock (alu_zero_s1_agent_m0_lock), // .lock
.m0_readdata (alu_zero_s1_agent_m0_readdata), // .readdata
.m0_readdatavalid (alu_zero_s1_agent_m0_readdatavalid), // .readdatavalid
.m0_read (alu_zero_s1_agent_m0_read), // .read
.m0_waitrequest (alu_zero_s1_agent_m0_waitrequest), // .waitrequest
.m0_writedata (alu_zero_s1_agent_m0_writedata), // .writedata
.m0_write (alu_zero_s1_agent_m0_write), // .write
.rp_endofpacket (alu_zero_s1_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (alu_zero_s1_agent_rp_ready), // .ready
.rp_valid (alu_zero_s1_agent_rp_valid), // .valid
.rp_data (alu_zero_s1_agent_rp_data), // .data
.rp_startofpacket (alu_zero_s1_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_mux_027_src_ready), // cp.ready
.cp_valid (cmd_mux_027_src_valid), // .valid
.cp_data (cmd_mux_027_src_data), // .data
.cp_startofpacket (cmd_mux_027_src_startofpacket), // .startofpacket
.cp_endofpacket (cmd_mux_027_src_endofpacket), // .endofpacket
.cp_channel (cmd_mux_027_src_channel), // .channel
.rf_sink_ready (alu_zero_s1_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (alu_zero_s1_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (alu_zero_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (alu_zero_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (alu_zero_s1_agent_rsp_fifo_out_data), // .data
.rf_source_ready (alu_zero_s1_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (alu_zero_s1_agent_rf_source_valid), // .valid
.rf_source_startofpacket (alu_zero_s1_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (alu_zero_s1_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (alu_zero_s1_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (alu_zero_s1_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (alu_zero_s1_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_sink_data (alu_zero_s1_agent_rdata_fifo_src_data), // .data
.rdata_fifo_src_ready (alu_zero_s1_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (alu_zero_s1_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (alu_zero_s1_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (100),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) alu_zero_s1_agent_rsp_fifo (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (alu_zero_s1_agent_rf_source_data), // in.data
.in_valid (alu_zero_s1_agent_rf_source_valid), // .valid
.in_ready (alu_zero_s1_agent_rf_source_ready), // .ready
.in_startofpacket (alu_zero_s1_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (alu_zero_s1_agent_rf_source_endofpacket), // .endofpacket
.out_data (alu_zero_s1_agent_rsp_fifo_out_data), // out.data
.out_valid (alu_zero_s1_agent_rsp_fifo_out_valid), // .valid
.out_ready (alu_zero_s1_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (alu_zero_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (alu_zero_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_ORI_BURST_SIZE_H (98),
.PKT_ORI_BURST_SIZE_L (96),
.PKT_RESPONSE_STATUS_H (95),
.PKT_RESPONSE_STATUS_L (94),
.PKT_BURST_SIZE_H (69),
.PKT_BURST_SIZE_L (67),
.PKT_TRANS_LOCK (59),
.PKT_BEGIN_BURST (74),
.PKT_PROTECTION_H (89),
.PKT_PROTECTION_L (87),
.PKT_BURSTWRAP_H (66),
.PKT_BURSTWRAP_L (64),
.PKT_BYTE_CNT_H (63),
.PKT_BYTE_CNT_L (61),
.PKT_ADDR_H (54),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (55),
.PKT_TRANS_POSTED (56),
.PKT_TRANS_WRITE (57),
.PKT_TRANS_READ (58),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (80),
.PKT_SRC_ID_L (76),
.PKT_DEST_ID_H (85),
.PKT_DEST_ID_L (81),
.PKT_SYMBOL_W (8),
.ST_CHANNEL_W (32),
.ST_DATA_W (99),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) alu_overflow_s1_agent (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (alu_overflow_s1_agent_m0_address), // m0.address
.m0_burstcount (alu_overflow_s1_agent_m0_burstcount), // .burstcount
.m0_byteenable (alu_overflow_s1_agent_m0_byteenable), // .byteenable
.m0_debugaccess (alu_overflow_s1_agent_m0_debugaccess), // .debugaccess
.m0_lock (alu_overflow_s1_agent_m0_lock), // .lock
.m0_readdata (alu_overflow_s1_agent_m0_readdata), // .readdata
.m0_readdatavalid (alu_overflow_s1_agent_m0_readdatavalid), // .readdatavalid
.m0_read (alu_overflow_s1_agent_m0_read), // .read
.m0_waitrequest (alu_overflow_s1_agent_m0_waitrequest), // .waitrequest
.m0_writedata (alu_overflow_s1_agent_m0_writedata), // .writedata
.m0_write (alu_overflow_s1_agent_m0_write), // .write
.rp_endofpacket (alu_overflow_s1_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (alu_overflow_s1_agent_rp_ready), // .ready
.rp_valid (alu_overflow_s1_agent_rp_valid), // .valid
.rp_data (alu_overflow_s1_agent_rp_data), // .data
.rp_startofpacket (alu_overflow_s1_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_mux_028_src_ready), // cp.ready
.cp_valid (cmd_mux_028_src_valid), // .valid
.cp_data (cmd_mux_028_src_data), // .data
.cp_startofpacket (cmd_mux_028_src_startofpacket), // .startofpacket
.cp_endofpacket (cmd_mux_028_src_endofpacket), // .endofpacket
.cp_channel (cmd_mux_028_src_channel), // .channel
.rf_sink_ready (alu_overflow_s1_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (alu_overflow_s1_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (alu_overflow_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (alu_overflow_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (alu_overflow_s1_agent_rsp_fifo_out_data), // .data
.rf_source_ready (alu_overflow_s1_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (alu_overflow_s1_agent_rf_source_valid), // .valid
.rf_source_startofpacket (alu_overflow_s1_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (alu_overflow_s1_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (alu_overflow_s1_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (alu_overflow_s1_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (alu_overflow_s1_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_sink_data (alu_overflow_s1_agent_rdata_fifo_src_data), // .data
.rdata_fifo_src_ready (alu_overflow_s1_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (alu_overflow_s1_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (alu_overflow_s1_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (100),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) alu_overflow_s1_agent_rsp_fifo (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (alu_overflow_s1_agent_rf_source_data), // in.data
.in_valid (alu_overflow_s1_agent_rf_source_valid), // .valid
.in_ready (alu_overflow_s1_agent_rf_source_ready), // .ready
.in_startofpacket (alu_overflow_s1_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (alu_overflow_s1_agent_rf_source_endofpacket), // .endofpacket
.out_data (alu_overflow_s1_agent_rsp_fifo_out_data), // out.data
.out_valid (alu_overflow_s1_agent_rsp_fifo_out_valid), // .valid
.out_ready (alu_overflow_s1_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (alu_overflow_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (alu_overflow_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_ORI_BURST_SIZE_H (98),
.PKT_ORI_BURST_SIZE_L (96),
.PKT_RESPONSE_STATUS_H (95),
.PKT_RESPONSE_STATUS_L (94),
.PKT_BURST_SIZE_H (69),
.PKT_BURST_SIZE_L (67),
.PKT_TRANS_LOCK (59),
.PKT_BEGIN_BURST (74),
.PKT_PROTECTION_H (89),
.PKT_PROTECTION_L (87),
.PKT_BURSTWRAP_H (66),
.PKT_BURSTWRAP_L (64),
.PKT_BYTE_CNT_H (63),
.PKT_BYTE_CNT_L (61),
.PKT_ADDR_H (54),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (55),
.PKT_TRANS_POSTED (56),
.PKT_TRANS_WRITE (57),
.PKT_TRANS_READ (58),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (80),
.PKT_SRC_ID_L (76),
.PKT_DEST_ID_H (85),
.PKT_DEST_ID_L (81),
.PKT_SYMBOL_W (8),
.ST_CHANNEL_W (32),
.ST_DATA_W (99),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) alu_carry_out_s1_agent (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (alu_carry_out_s1_agent_m0_address), // m0.address
.m0_burstcount (alu_carry_out_s1_agent_m0_burstcount), // .burstcount
.m0_byteenable (alu_carry_out_s1_agent_m0_byteenable), // .byteenable
.m0_debugaccess (alu_carry_out_s1_agent_m0_debugaccess), // .debugaccess
.m0_lock (alu_carry_out_s1_agent_m0_lock), // .lock
.m0_readdata (alu_carry_out_s1_agent_m0_readdata), // .readdata
.m0_readdatavalid (alu_carry_out_s1_agent_m0_readdatavalid), // .readdatavalid
.m0_read (alu_carry_out_s1_agent_m0_read), // .read
.m0_waitrequest (alu_carry_out_s1_agent_m0_waitrequest), // .waitrequest
.m0_writedata (alu_carry_out_s1_agent_m0_writedata), // .writedata
.m0_write (alu_carry_out_s1_agent_m0_write), // .write
.rp_endofpacket (alu_carry_out_s1_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (alu_carry_out_s1_agent_rp_ready), // .ready
.rp_valid (alu_carry_out_s1_agent_rp_valid), // .valid
.rp_data (alu_carry_out_s1_agent_rp_data), // .data
.rp_startofpacket (alu_carry_out_s1_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_mux_029_src_ready), // cp.ready
.cp_valid (cmd_mux_029_src_valid), // .valid
.cp_data (cmd_mux_029_src_data), // .data
.cp_startofpacket (cmd_mux_029_src_startofpacket), // .startofpacket
.cp_endofpacket (cmd_mux_029_src_endofpacket), // .endofpacket
.cp_channel (cmd_mux_029_src_channel), // .channel
.rf_sink_ready (alu_carry_out_s1_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (alu_carry_out_s1_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (alu_carry_out_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (alu_carry_out_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (alu_carry_out_s1_agent_rsp_fifo_out_data), // .data
.rf_source_ready (alu_carry_out_s1_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (alu_carry_out_s1_agent_rf_source_valid), // .valid
.rf_source_startofpacket (alu_carry_out_s1_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (alu_carry_out_s1_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (alu_carry_out_s1_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (alu_carry_out_s1_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (alu_carry_out_s1_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_sink_data (alu_carry_out_s1_agent_rdata_fifo_src_data), // .data
.rdata_fifo_src_ready (alu_carry_out_s1_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (alu_carry_out_s1_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (alu_carry_out_s1_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (100),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) alu_carry_out_s1_agent_rsp_fifo (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (alu_carry_out_s1_agent_rf_source_data), // in.data
.in_valid (alu_carry_out_s1_agent_rf_source_valid), // .valid
.in_ready (alu_carry_out_s1_agent_rf_source_ready), // .ready
.in_startofpacket (alu_carry_out_s1_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (alu_carry_out_s1_agent_rf_source_endofpacket), // .endofpacket
.out_data (alu_carry_out_s1_agent_rsp_fifo_out_data), // out.data
.out_valid (alu_carry_out_s1_agent_rsp_fifo_out_valid), // .valid
.out_ready (alu_carry_out_s1_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (alu_carry_out_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (alu_carry_out_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_ORI_BURST_SIZE_H (98),
.PKT_ORI_BURST_SIZE_L (96),
.PKT_RESPONSE_STATUS_H (95),
.PKT_RESPONSE_STATUS_L (94),
.PKT_BURST_SIZE_H (69),
.PKT_BURST_SIZE_L (67),
.PKT_TRANS_LOCK (59),
.PKT_BEGIN_BURST (74),
.PKT_PROTECTION_H (89),
.PKT_PROTECTION_L (87),
.PKT_BURSTWRAP_H (66),
.PKT_BURSTWRAP_L (64),
.PKT_BYTE_CNT_H (63),
.PKT_BYTE_CNT_L (61),
.PKT_ADDR_H (54),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (55),
.PKT_TRANS_POSTED (56),
.PKT_TRANS_WRITE (57),
.PKT_TRANS_READ (58),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (80),
.PKT_SRC_ID_L (76),
.PKT_DEST_ID_H (85),
.PKT_DEST_ID_L (81),
.PKT_SYMBOL_W (8),
.ST_CHANNEL_W (32),
.ST_DATA_W (99),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) alu_negative_s1_agent (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (alu_negative_s1_agent_m0_address), // m0.address
.m0_burstcount (alu_negative_s1_agent_m0_burstcount), // .burstcount
.m0_byteenable (alu_negative_s1_agent_m0_byteenable), // .byteenable
.m0_debugaccess (alu_negative_s1_agent_m0_debugaccess), // .debugaccess
.m0_lock (alu_negative_s1_agent_m0_lock), // .lock
.m0_readdata (alu_negative_s1_agent_m0_readdata), // .readdata
.m0_readdatavalid (alu_negative_s1_agent_m0_readdatavalid), // .readdatavalid
.m0_read (alu_negative_s1_agent_m0_read), // .read
.m0_waitrequest (alu_negative_s1_agent_m0_waitrequest), // .waitrequest
.m0_writedata (alu_negative_s1_agent_m0_writedata), // .writedata
.m0_write (alu_negative_s1_agent_m0_write), // .write
.rp_endofpacket (alu_negative_s1_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (alu_negative_s1_agent_rp_ready), // .ready
.rp_valid (alu_negative_s1_agent_rp_valid), // .valid
.rp_data (alu_negative_s1_agent_rp_data), // .data
.rp_startofpacket (alu_negative_s1_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_mux_030_src_ready), // cp.ready
.cp_valid (cmd_mux_030_src_valid), // .valid
.cp_data (cmd_mux_030_src_data), // .data
.cp_startofpacket (cmd_mux_030_src_startofpacket), // .startofpacket
.cp_endofpacket (cmd_mux_030_src_endofpacket), // .endofpacket
.cp_channel (cmd_mux_030_src_channel), // .channel
.rf_sink_ready (alu_negative_s1_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (alu_negative_s1_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (alu_negative_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (alu_negative_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (alu_negative_s1_agent_rsp_fifo_out_data), // .data
.rf_source_ready (alu_negative_s1_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (alu_negative_s1_agent_rf_source_valid), // .valid
.rf_source_startofpacket (alu_negative_s1_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (alu_negative_s1_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (alu_negative_s1_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (alu_negative_s1_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (alu_negative_s1_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_sink_data (alu_negative_s1_agent_rdata_fifo_src_data), // .data
.rdata_fifo_src_ready (alu_negative_s1_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (alu_negative_s1_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (alu_negative_s1_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (100),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) alu_negative_s1_agent_rsp_fifo (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (alu_negative_s1_agent_rf_source_data), // in.data
.in_valid (alu_negative_s1_agent_rf_source_valid), // .valid
.in_ready (alu_negative_s1_agent_rf_source_ready), // .ready
.in_startofpacket (alu_negative_s1_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (alu_negative_s1_agent_rf_source_endofpacket), // .endofpacket
.out_data (alu_negative_s1_agent_rsp_fifo_out_data), // out.data
.out_valid (alu_negative_s1_agent_rsp_fifo_out_valid), // .valid
.out_ready (alu_negative_s1_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (alu_negative_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (alu_negative_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_ORI_BURST_SIZE_H (98),
.PKT_ORI_BURST_SIZE_L (96),
.PKT_RESPONSE_STATUS_H (95),
.PKT_RESPONSE_STATUS_L (94),
.PKT_BURST_SIZE_H (69),
.PKT_BURST_SIZE_L (67),
.PKT_TRANS_LOCK (59),
.PKT_BEGIN_BURST (74),
.PKT_PROTECTION_H (89),
.PKT_PROTECTION_L (87),
.PKT_BURSTWRAP_H (66),
.PKT_BURSTWRAP_L (64),
.PKT_BYTE_CNT_H (63),
.PKT_BYTE_CNT_L (61),
.PKT_ADDR_H (54),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (55),
.PKT_TRANS_POSTED (56),
.PKT_TRANS_WRITE (57),
.PKT_TRANS_READ (58),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (80),
.PKT_SRC_ID_L (76),
.PKT_DEST_ID_H (85),
.PKT_DEST_ID_L (81),
.PKT_SYMBOL_W (8),
.ST_CHANNEL_W (32),
.ST_DATA_W (99),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) keys_s1_agent (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (keys_s1_agent_m0_address), // m0.address
.m0_burstcount (keys_s1_agent_m0_burstcount), // .burstcount
.m0_byteenable (keys_s1_agent_m0_byteenable), // .byteenable
.m0_debugaccess (keys_s1_agent_m0_debugaccess), // .debugaccess
.m0_lock (keys_s1_agent_m0_lock), // .lock
.m0_readdata (keys_s1_agent_m0_readdata), // .readdata
.m0_readdatavalid (keys_s1_agent_m0_readdatavalid), // .readdatavalid
.m0_read (keys_s1_agent_m0_read), // .read
.m0_waitrequest (keys_s1_agent_m0_waitrequest), // .waitrequest
.m0_writedata (keys_s1_agent_m0_writedata), // .writedata
.m0_write (keys_s1_agent_m0_write), // .write
.rp_endofpacket (keys_s1_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (keys_s1_agent_rp_ready), // .ready
.rp_valid (keys_s1_agent_rp_valid), // .valid
.rp_data (keys_s1_agent_rp_data), // .data
.rp_startofpacket (keys_s1_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_mux_031_src_ready), // cp.ready
.cp_valid (cmd_mux_031_src_valid), // .valid
.cp_data (cmd_mux_031_src_data), // .data
.cp_startofpacket (cmd_mux_031_src_startofpacket), // .startofpacket
.cp_endofpacket (cmd_mux_031_src_endofpacket), // .endofpacket
.cp_channel (cmd_mux_031_src_channel), // .channel
.rf_sink_ready (keys_s1_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (keys_s1_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (keys_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (keys_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (keys_s1_agent_rsp_fifo_out_data), // .data
.rf_source_ready (keys_s1_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (keys_s1_agent_rf_source_valid), // .valid
.rf_source_startofpacket (keys_s1_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (keys_s1_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (keys_s1_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (keys_s1_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (keys_s1_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_sink_data (keys_s1_agent_rdata_fifo_src_data), // .data
.rdata_fifo_src_ready (keys_s1_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (keys_s1_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (keys_s1_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (100),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) keys_s1_agent_rsp_fifo (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (keys_s1_agent_rf_source_data), // in.data
.in_valid (keys_s1_agent_rf_source_valid), // .valid
.in_ready (keys_s1_agent_rf_source_ready), // .ready
.in_startofpacket (keys_s1_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (keys_s1_agent_rf_source_endofpacket), // .endofpacket
.out_data (keys_s1_agent_rsp_fifo_out_data), // out.data
.out_valid (keys_s1_agent_rsp_fifo_out_valid), // .valid
.out_ready (keys_s1_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (keys_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (keys_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
nios_system_mm_interconnect_0_router router (
.sink_ready (nios2_qsys_0_data_master_agent_cp_ready), // sink.ready
.sink_valid (nios2_qsys_0_data_master_agent_cp_valid), // .valid
.sink_data (nios2_qsys_0_data_master_agent_cp_data), // .data
.sink_startofpacket (nios2_qsys_0_data_master_agent_cp_startofpacket), // .startofpacket
.sink_endofpacket (nios2_qsys_0_data_master_agent_cp_endofpacket), // .endofpacket
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_src_ready), // src.ready
.src_valid (router_src_valid), // .valid
.src_data (router_src_data), // .data
.src_channel (router_src_channel), // .channel
.src_startofpacket (router_src_startofpacket), // .startofpacket
.src_endofpacket (router_src_endofpacket) // .endofpacket
);
nios_system_mm_interconnect_0_router_001 router_001 (
.sink_ready (nios2_qsys_0_instruction_master_agent_cp_ready), // sink.ready
.sink_valid (nios2_qsys_0_instruction_master_agent_cp_valid), // .valid
.sink_data (nios2_qsys_0_instruction_master_agent_cp_data), // .data
.sink_startofpacket (nios2_qsys_0_instruction_master_agent_cp_startofpacket), // .startofpacket
.sink_endofpacket (nios2_qsys_0_instruction_master_agent_cp_endofpacket), // .endofpacket
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_001_src_ready), // src.ready
.src_valid (router_001_src_valid), // .valid
.src_data (router_001_src_data), // .data
.src_channel (router_001_src_channel), // .channel
.src_startofpacket (router_001_src_startofpacket), // .startofpacket
.src_endofpacket (router_001_src_endofpacket) // .endofpacket
);
nios_system_mm_interconnect_0_router_002 router_002 (
.sink_ready (jtag_uart_0_avalon_jtag_slave_agent_rp_ready), // sink.ready
.sink_valid (jtag_uart_0_avalon_jtag_slave_agent_rp_valid), // .valid
.sink_data (jtag_uart_0_avalon_jtag_slave_agent_rp_data), // .data
.sink_startofpacket (jtag_uart_0_avalon_jtag_slave_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (jtag_uart_0_avalon_jtag_slave_agent_rp_endofpacket), // .endofpacket
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_002_src_ready), // src.ready
.src_valid (router_002_src_valid), // .valid
.src_data (router_002_src_data), // .data
.src_channel (router_002_src_channel), // .channel
.src_startofpacket (router_002_src_startofpacket), // .startofpacket
.src_endofpacket (router_002_src_endofpacket) // .endofpacket
);
nios_system_mm_interconnect_0_router_003 router_003 (
.sink_ready (nios2_qsys_0_debug_mem_slave_agent_rp_ready), // sink.ready
.sink_valid (nios2_qsys_0_debug_mem_slave_agent_rp_valid), // .valid
.sink_data (nios2_qsys_0_debug_mem_slave_agent_rp_data), // .data
.sink_startofpacket (nios2_qsys_0_debug_mem_slave_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (nios2_qsys_0_debug_mem_slave_agent_rp_endofpacket), // .endofpacket
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_003_src_ready), // src.ready
.src_valid (router_003_src_valid), // .valid
.src_data (router_003_src_data), // .data
.src_channel (router_003_src_channel), // .channel
.src_startofpacket (router_003_src_startofpacket), // .startofpacket
.src_endofpacket (router_003_src_endofpacket) // .endofpacket
);
nios_system_mm_interconnect_0_router_003 router_004 (
.sink_ready (onchip_memory2_0_s1_agent_rp_ready), // sink.ready
.sink_valid (onchip_memory2_0_s1_agent_rp_valid), // .valid
.sink_data (onchip_memory2_0_s1_agent_rp_data), // .data
.sink_startofpacket (onchip_memory2_0_s1_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (onchip_memory2_0_s1_agent_rp_endofpacket), // .endofpacket
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_004_src_ready), // src.ready
.src_valid (router_004_src_valid), // .valid
.src_data (router_004_src_data), // .data
.src_channel (router_004_src_channel), // .channel
.src_startofpacket (router_004_src_startofpacket), // .startofpacket
.src_endofpacket (router_004_src_endofpacket) // .endofpacket
);
nios_system_mm_interconnect_0_router_002 router_005 (
.sink_ready (leds_s1_agent_rp_ready), // sink.ready
.sink_valid (leds_s1_agent_rp_valid), // .valid
.sink_data (leds_s1_agent_rp_data), // .data
.sink_startofpacket (leds_s1_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (leds_s1_agent_rp_endofpacket), // .endofpacket
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_005_src_ready), // src.ready
.src_valid (router_005_src_valid), // .valid
.src_data (router_005_src_data), // .data
.src_channel (router_005_src_channel), // .channel
.src_startofpacket (router_005_src_startofpacket), // .startofpacket
.src_endofpacket (router_005_src_endofpacket) // .endofpacket
);
nios_system_mm_interconnect_0_router_002 router_006 (
.sink_ready (switches_s1_agent_rp_ready), // sink.ready
.sink_valid (switches_s1_agent_rp_valid), // .valid
.sink_data (switches_s1_agent_rp_data), // .data
.sink_startofpacket (switches_s1_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (switches_s1_agent_rp_endofpacket), // .endofpacket
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_006_src_ready), // src.ready
.src_valid (router_006_src_valid), // .valid
.src_data (router_006_src_data), // .data
.src_channel (router_006_src_channel), // .channel
.src_startofpacket (router_006_src_startofpacket), // .startofpacket
.src_endofpacket (router_006_src_endofpacket) // .endofpacket
);
nios_system_mm_interconnect_0_router_002 router_007 (
.sink_ready (sram_data_s1_agent_rp_ready), // sink.ready
.sink_valid (sram_data_s1_agent_rp_valid), // .valid
.sink_data (sram_data_s1_agent_rp_data), // .data
.sink_startofpacket (sram_data_s1_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (sram_data_s1_agent_rp_endofpacket), // .endofpacket
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_007_src_ready), // src.ready
.src_valid (router_007_src_valid), // .valid
.src_data (router_007_src_data), // .data
.src_channel (router_007_src_channel), // .channel
.src_startofpacket (router_007_src_startofpacket), // .startofpacket
.src_endofpacket (router_007_src_endofpacket) // .endofpacket
);
nios_system_mm_interconnect_0_router_002 router_008 (
.sink_ready (sram_addr_s1_agent_rp_ready), // sink.ready
.sink_valid (sram_addr_s1_agent_rp_valid), // .valid
.sink_data (sram_addr_s1_agent_rp_data), // .data
.sink_startofpacket (sram_addr_s1_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (sram_addr_s1_agent_rp_endofpacket), // .endofpacket
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_008_src_ready), // src.ready
.src_valid (router_008_src_valid), // .valid
.src_data (router_008_src_data), // .data
.src_channel (router_008_src_channel), // .channel
.src_startofpacket (router_008_src_startofpacket), // .startofpacket
.src_endofpacket (router_008_src_endofpacket) // .endofpacket
);
nios_system_mm_interconnect_0_router_002 router_009 (
.sink_ready (sram_read_write_s1_agent_rp_ready), // sink.ready
.sink_valid (sram_read_write_s1_agent_rp_valid), // .valid
.sink_data (sram_read_write_s1_agent_rp_data), // .data
.sink_startofpacket (sram_read_write_s1_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (sram_read_write_s1_agent_rp_endofpacket), // .endofpacket
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_009_src_ready), // src.ready
.src_valid (router_009_src_valid), // .valid
.src_data (router_009_src_data), // .data
.src_channel (router_009_src_channel), // .channel
.src_startofpacket (router_009_src_startofpacket), // .startofpacket
.src_endofpacket (router_009_src_endofpacket) // .endofpacket
);
nios_system_mm_interconnect_0_router_002 router_010 (
.sink_ready (sram_cs_s1_agent_rp_ready), // sink.ready
.sink_valid (sram_cs_s1_agent_rp_valid), // .valid
.sink_data (sram_cs_s1_agent_rp_data), // .data
.sink_startofpacket (sram_cs_s1_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (sram_cs_s1_agent_rp_endofpacket), // .endofpacket
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_010_src_ready), // src.ready
.src_valid (router_010_src_valid), // .valid
.src_data (router_010_src_data), // .data
.src_channel (router_010_src_channel), // .channel
.src_startofpacket (router_010_src_startofpacket), // .startofpacket
.src_endofpacket (router_010_src_endofpacket) // .endofpacket
);
nios_system_mm_interconnect_0_router_002 router_011 (
.sink_ready (sram_oe_s1_agent_rp_ready), // sink.ready
.sink_valid (sram_oe_s1_agent_rp_valid), // .valid
.sink_data (sram_oe_s1_agent_rp_data), // .data
.sink_startofpacket (sram_oe_s1_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (sram_oe_s1_agent_rp_endofpacket), // .endofpacket
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_011_src_ready), // src.ready
.src_valid (router_011_src_valid), // .valid
.src_data (router_011_src_data), // .data
.src_channel (router_011_src_channel), // .channel
.src_startofpacket (router_011_src_startofpacket), // .startofpacket
.src_endofpacket (router_011_src_endofpacket) // .endofpacket
);
nios_system_mm_interconnect_0_router_002 router_012 (
.sink_ready (regfile_data_s1_agent_rp_ready), // sink.ready
.sink_valid (regfile_data_s1_agent_rp_valid), // .valid
.sink_data (regfile_data_s1_agent_rp_data), // .data
.sink_startofpacket (regfile_data_s1_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (regfile_data_s1_agent_rp_endofpacket), // .endofpacket
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_012_src_ready), // src.ready
.src_valid (router_012_src_valid), // .valid
.src_data (router_012_src_data), // .data
.src_channel (router_012_src_channel), // .channel
.src_startofpacket (router_012_src_startofpacket), // .startofpacket
.src_endofpacket (router_012_src_endofpacket) // .endofpacket
);
nios_system_mm_interconnect_0_router_002 router_013 (
.sink_ready (regfile_reg1_s1_agent_rp_ready), // sink.ready
.sink_valid (regfile_reg1_s1_agent_rp_valid), // .valid
.sink_data (regfile_reg1_s1_agent_rp_data), // .data
.sink_startofpacket (regfile_reg1_s1_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (regfile_reg1_s1_agent_rp_endofpacket), // .endofpacket
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_013_src_ready), // src.ready
.src_valid (router_013_src_valid), // .valid
.src_data (router_013_src_data), // .data
.src_channel (router_013_src_channel), // .channel
.src_startofpacket (router_013_src_startofpacket), // .startofpacket
.src_endofpacket (router_013_src_endofpacket) // .endofpacket
);
nios_system_mm_interconnect_0_router_002 router_014 (
.sink_ready (regfile_reg2_s1_agent_rp_ready), // sink.ready
.sink_valid (regfile_reg2_s1_agent_rp_valid), // .valid
.sink_data (regfile_reg2_s1_agent_rp_data), // .data
.sink_startofpacket (regfile_reg2_s1_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (regfile_reg2_s1_agent_rp_endofpacket), // .endofpacket
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_014_src_ready), // src.ready
.src_valid (router_014_src_valid), // .valid
.src_data (router_014_src_data), // .data
.src_channel (router_014_src_channel), // .channel
.src_startofpacket (router_014_src_startofpacket), // .startofpacket
.src_endofpacket (router_014_src_endofpacket) // .endofpacket
);
nios_system_mm_interconnect_0_router_002 router_015 (
.sink_ready (regfile_r1sel_s1_agent_rp_ready), // sink.ready
.sink_valid (regfile_r1sel_s1_agent_rp_valid), // .valid
.sink_data (regfile_r1sel_s1_agent_rp_data), // .data
.sink_startofpacket (regfile_r1sel_s1_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (regfile_r1sel_s1_agent_rp_endofpacket), // .endofpacket
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_015_src_ready), // src.ready
.src_valid (router_015_src_valid), // .valid
.src_data (router_015_src_data), // .data
.src_channel (router_015_src_channel), // .channel
.src_startofpacket (router_015_src_startofpacket), // .startofpacket
.src_endofpacket (router_015_src_endofpacket) // .endofpacket
);
nios_system_mm_interconnect_0_router_002 router_016 (
.sink_ready (regfile_r2sel_s1_agent_rp_ready), // sink.ready
.sink_valid (regfile_r2sel_s1_agent_rp_valid), // .valid
.sink_data (regfile_r2sel_s1_agent_rp_data), // .data
.sink_startofpacket (regfile_r2sel_s1_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (regfile_r2sel_s1_agent_rp_endofpacket), // .endofpacket
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_016_src_ready), // src.ready
.src_valid (router_016_src_valid), // .valid
.src_data (router_016_src_data), // .data
.src_channel (router_016_src_channel), // .channel
.src_startofpacket (router_016_src_startofpacket), // .startofpacket
.src_endofpacket (router_016_src_endofpacket) // .endofpacket
);
nios_system_mm_interconnect_0_router_002 router_017 (
.sink_ready (regfile_wsel_s1_agent_rp_ready), // sink.ready
.sink_valid (regfile_wsel_s1_agent_rp_valid), // .valid
.sink_data (regfile_wsel_s1_agent_rp_data), // .data
.sink_startofpacket (regfile_wsel_s1_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (regfile_wsel_s1_agent_rp_endofpacket), // .endofpacket
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_017_src_ready), // src.ready
.src_valid (router_017_src_valid), // .valid
.src_data (router_017_src_data), // .data
.src_channel (router_017_src_channel), // .channel
.src_startofpacket (router_017_src_startofpacket), // .startofpacket
.src_endofpacket (router_017_src_endofpacket) // .endofpacket
);
nios_system_mm_interconnect_0_router_002 router_018 (
.sink_ready (regfile_we_s1_agent_rp_ready), // sink.ready
.sink_valid (regfile_we_s1_agent_rp_valid), // .valid
.sink_data (regfile_we_s1_agent_rp_data), // .data
.sink_startofpacket (regfile_we_s1_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (regfile_we_s1_agent_rp_endofpacket), // .endofpacket
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_018_src_ready), // src.ready
.src_valid (router_018_src_valid), // .valid
.src_data (router_018_src_data), // .data
.src_channel (router_018_src_channel), // .channel
.src_startofpacket (router_018_src_startofpacket), // .startofpacket
.src_endofpacket (router_018_src_endofpacket) // .endofpacket
);
nios_system_mm_interconnect_0_router_002 router_019 (
.sink_ready (hex_0_s1_agent_rp_ready), // sink.ready
.sink_valid (hex_0_s1_agent_rp_valid), // .valid
.sink_data (hex_0_s1_agent_rp_data), // .data
.sink_startofpacket (hex_0_s1_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (hex_0_s1_agent_rp_endofpacket), // .endofpacket
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_019_src_ready), // src.ready
.src_valid (router_019_src_valid), // .valid
.src_data (router_019_src_data), // .data
.src_channel (router_019_src_channel), // .channel
.src_startofpacket (router_019_src_startofpacket), // .startofpacket
.src_endofpacket (router_019_src_endofpacket) // .endofpacket
);
nios_system_mm_interconnect_0_router_002 router_020 (
.sink_ready (hex_1_s1_agent_rp_ready), // sink.ready
.sink_valid (hex_1_s1_agent_rp_valid), // .valid
.sink_data (hex_1_s1_agent_rp_data), // .data
.sink_startofpacket (hex_1_s1_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (hex_1_s1_agent_rp_endofpacket), // .endofpacket
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_020_src_ready), // src.ready
.src_valid (router_020_src_valid), // .valid
.src_data (router_020_src_data), // .data
.src_channel (router_020_src_channel), // .channel
.src_startofpacket (router_020_src_startofpacket), // .startofpacket
.src_endofpacket (router_020_src_endofpacket) // .endofpacket
);
nios_system_mm_interconnect_0_router_002 router_021 (
.sink_ready (hex_2_s1_agent_rp_ready), // sink.ready
.sink_valid (hex_2_s1_agent_rp_valid), // .valid
.sink_data (hex_2_s1_agent_rp_data), // .data
.sink_startofpacket (hex_2_s1_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (hex_2_s1_agent_rp_endofpacket), // .endofpacket
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_021_src_ready), // src.ready
.src_valid (router_021_src_valid), // .valid
.src_data (router_021_src_data), // .data
.src_channel (router_021_src_channel), // .channel
.src_startofpacket (router_021_src_startofpacket), // .startofpacket
.src_endofpacket (router_021_src_endofpacket) // .endofpacket
);
nios_system_mm_interconnect_0_router_002 router_022 (
.sink_ready (hex_3_s1_agent_rp_ready), // sink.ready
.sink_valid (hex_3_s1_agent_rp_valid), // .valid
.sink_data (hex_3_s1_agent_rp_data), // .data
.sink_startofpacket (hex_3_s1_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (hex_3_s1_agent_rp_endofpacket), // .endofpacket
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_022_src_ready), // src.ready
.src_valid (router_022_src_valid), // .valid
.src_data (router_022_src_data), // .data
.src_channel (router_022_src_channel), // .channel
.src_startofpacket (router_022_src_startofpacket), // .startofpacket
.src_endofpacket (router_022_src_endofpacket) // .endofpacket
);
nios_system_mm_interconnect_0_router_002 router_023 (
.sink_ready (hex_4_s1_agent_rp_ready), // sink.ready
.sink_valid (hex_4_s1_agent_rp_valid), // .valid
.sink_data (hex_4_s1_agent_rp_data), // .data
.sink_startofpacket (hex_4_s1_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (hex_4_s1_agent_rp_endofpacket), // .endofpacket
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_023_src_ready), // src.ready
.src_valid (router_023_src_valid), // .valid
.src_data (router_023_src_data), // .data
.src_channel (router_023_src_channel), // .channel
.src_startofpacket (router_023_src_startofpacket), // .startofpacket
.src_endofpacket (router_023_src_endofpacket) // .endofpacket
);
nios_system_mm_interconnect_0_router_002 router_024 (
.sink_ready (hex_5_s1_agent_rp_ready), // sink.ready
.sink_valid (hex_5_s1_agent_rp_valid), // .valid
.sink_data (hex_5_s1_agent_rp_data), // .data
.sink_startofpacket (hex_5_s1_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (hex_5_s1_agent_rp_endofpacket), // .endofpacket
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_024_src_ready), // src.ready
.src_valid (router_024_src_valid), // .valid
.src_data (router_024_src_data), // .data
.src_channel (router_024_src_channel), // .channel
.src_startofpacket (router_024_src_startofpacket), // .startofpacket
.src_endofpacket (router_024_src_endofpacket) // .endofpacket
);
nios_system_mm_interconnect_0_router_002 router_025 (
.sink_ready (alu_a_s1_agent_rp_ready), // sink.ready
.sink_valid (alu_a_s1_agent_rp_valid), // .valid
.sink_data (alu_a_s1_agent_rp_data), // .data
.sink_startofpacket (alu_a_s1_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (alu_a_s1_agent_rp_endofpacket), // .endofpacket
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_025_src_ready), // src.ready
.src_valid (router_025_src_valid), // .valid
.src_data (router_025_src_data), // .data
.src_channel (router_025_src_channel), // .channel
.src_startofpacket (router_025_src_startofpacket), // .startofpacket
.src_endofpacket (router_025_src_endofpacket) // .endofpacket
);
nios_system_mm_interconnect_0_router_002 router_026 (
.sink_ready (alu_b_s1_agent_rp_ready), // sink.ready
.sink_valid (alu_b_s1_agent_rp_valid), // .valid
.sink_data (alu_b_s1_agent_rp_data), // .data
.sink_startofpacket (alu_b_s1_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (alu_b_s1_agent_rp_endofpacket), // .endofpacket
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_026_src_ready), // src.ready
.src_valid (router_026_src_valid), // .valid
.src_data (router_026_src_data), // .data
.src_channel (router_026_src_channel), // .channel
.src_startofpacket (router_026_src_startofpacket), // .startofpacket
.src_endofpacket (router_026_src_endofpacket) // .endofpacket
);
nios_system_mm_interconnect_0_router_002 router_027 (
.sink_ready (alu_control_s1_agent_rp_ready), // sink.ready
.sink_valid (alu_control_s1_agent_rp_valid), // .valid
.sink_data (alu_control_s1_agent_rp_data), // .data
.sink_startofpacket (alu_control_s1_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (alu_control_s1_agent_rp_endofpacket), // .endofpacket
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_027_src_ready), // src.ready
.src_valid (router_027_src_valid), // .valid
.src_data (router_027_src_data), // .data
.src_channel (router_027_src_channel), // .channel
.src_startofpacket (router_027_src_startofpacket), // .startofpacket
.src_endofpacket (router_027_src_endofpacket) // .endofpacket
);
nios_system_mm_interconnect_0_router_002 router_028 (
.sink_ready (alu_out_s1_agent_rp_ready), // sink.ready
.sink_valid (alu_out_s1_agent_rp_valid), // .valid
.sink_data (alu_out_s1_agent_rp_data), // .data
.sink_startofpacket (alu_out_s1_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (alu_out_s1_agent_rp_endofpacket), // .endofpacket
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_028_src_ready), // src.ready
.src_valid (router_028_src_valid), // .valid
.src_data (router_028_src_data), // .data
.src_channel (router_028_src_channel), // .channel
.src_startofpacket (router_028_src_startofpacket), // .startofpacket
.src_endofpacket (router_028_src_endofpacket) // .endofpacket
);
nios_system_mm_interconnect_0_router_002 router_029 (
.sink_ready (alu_zero_s1_agent_rp_ready), // sink.ready
.sink_valid (alu_zero_s1_agent_rp_valid), // .valid
.sink_data (alu_zero_s1_agent_rp_data), // .data
.sink_startofpacket (alu_zero_s1_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (alu_zero_s1_agent_rp_endofpacket), // .endofpacket
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_029_src_ready), // src.ready
.src_valid (router_029_src_valid), // .valid
.src_data (router_029_src_data), // .data
.src_channel (router_029_src_channel), // .channel
.src_startofpacket (router_029_src_startofpacket), // .startofpacket
.src_endofpacket (router_029_src_endofpacket) // .endofpacket
);
nios_system_mm_interconnect_0_router_002 router_030 (
.sink_ready (alu_overflow_s1_agent_rp_ready), // sink.ready
.sink_valid (alu_overflow_s1_agent_rp_valid), // .valid
.sink_data (alu_overflow_s1_agent_rp_data), // .data
.sink_startofpacket (alu_overflow_s1_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (alu_overflow_s1_agent_rp_endofpacket), // .endofpacket
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_030_src_ready), // src.ready
.src_valid (router_030_src_valid), // .valid
.src_data (router_030_src_data), // .data
.src_channel (router_030_src_channel), // .channel
.src_startofpacket (router_030_src_startofpacket), // .startofpacket
.src_endofpacket (router_030_src_endofpacket) // .endofpacket
);
nios_system_mm_interconnect_0_router_002 router_031 (
.sink_ready (alu_carry_out_s1_agent_rp_ready), // sink.ready
.sink_valid (alu_carry_out_s1_agent_rp_valid), // .valid
.sink_data (alu_carry_out_s1_agent_rp_data), // .data
.sink_startofpacket (alu_carry_out_s1_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (alu_carry_out_s1_agent_rp_endofpacket), // .endofpacket
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_031_src_ready), // src.ready
.src_valid (router_031_src_valid), // .valid
.src_data (router_031_src_data), // .data
.src_channel (router_031_src_channel), // .channel
.src_startofpacket (router_031_src_startofpacket), // .startofpacket
.src_endofpacket (router_031_src_endofpacket) // .endofpacket
);
nios_system_mm_interconnect_0_router_002 router_032 (
.sink_ready (alu_negative_s1_agent_rp_ready), // sink.ready
.sink_valid (alu_negative_s1_agent_rp_valid), // .valid
.sink_data (alu_negative_s1_agent_rp_data), // .data
.sink_startofpacket (alu_negative_s1_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (alu_negative_s1_agent_rp_endofpacket), // .endofpacket
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_032_src_ready), // src.ready
.src_valid (router_032_src_valid), // .valid
.src_data (router_032_src_data), // .data
.src_channel (router_032_src_channel), // .channel
.src_startofpacket (router_032_src_startofpacket), // .startofpacket
.src_endofpacket (router_032_src_endofpacket) // .endofpacket
);
nios_system_mm_interconnect_0_router_002 router_033 (
.sink_ready (keys_s1_agent_rp_ready), // sink.ready
.sink_valid (keys_s1_agent_rp_valid), // .valid
.sink_data (keys_s1_agent_rp_data), // .data
.sink_startofpacket (keys_s1_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (keys_s1_agent_rp_endofpacket), // .endofpacket
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_033_src_ready), // src.ready
.src_valid (router_033_src_valid), // .valid
.src_data (router_033_src_data), // .data
.src_channel (router_033_src_channel), // .channel
.src_startofpacket (router_033_src_startofpacket), // .startofpacket
.src_endofpacket (router_033_src_endofpacket) // .endofpacket
);
nios_system_mm_interconnect_0_cmd_demux cmd_demux (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_src_ready), // sink.ready
.sink_channel (router_src_channel), // .channel
.sink_data (router_src_data), // .data
.sink_startofpacket (router_src_startofpacket), // .startofpacket
.sink_endofpacket (router_src_endofpacket), // .endofpacket
.sink_valid (router_src_valid), // .valid
.src0_ready (cmd_demux_src0_ready), // src0.ready
.src0_valid (cmd_demux_src0_valid), // .valid
.src0_data (cmd_demux_src0_data), // .data
.src0_channel (cmd_demux_src0_channel), // .channel
.src0_startofpacket (cmd_demux_src0_startofpacket), // .startofpacket
.src0_endofpacket (cmd_demux_src0_endofpacket), // .endofpacket
.src1_ready (cmd_demux_src1_ready), // src1.ready
.src1_valid (cmd_demux_src1_valid), // .valid
.src1_data (cmd_demux_src1_data), // .data
.src1_channel (cmd_demux_src1_channel), // .channel
.src1_startofpacket (cmd_demux_src1_startofpacket), // .startofpacket
.src1_endofpacket (cmd_demux_src1_endofpacket), // .endofpacket
.src2_ready (cmd_demux_src2_ready), // src2.ready
.src2_valid (cmd_demux_src2_valid), // .valid
.src2_data (cmd_demux_src2_data), // .data
.src2_channel (cmd_demux_src2_channel), // .channel
.src2_startofpacket (cmd_demux_src2_startofpacket), // .startofpacket
.src2_endofpacket (cmd_demux_src2_endofpacket), // .endofpacket
.src3_ready (cmd_demux_src3_ready), // src3.ready
.src3_valid (cmd_demux_src3_valid), // .valid
.src3_data (cmd_demux_src3_data), // .data
.src3_channel (cmd_demux_src3_channel), // .channel
.src3_startofpacket (cmd_demux_src3_startofpacket), // .startofpacket
.src3_endofpacket (cmd_demux_src3_endofpacket), // .endofpacket
.src4_ready (cmd_demux_src4_ready), // src4.ready
.src4_valid (cmd_demux_src4_valid), // .valid
.src4_data (cmd_demux_src4_data), // .data
.src4_channel (cmd_demux_src4_channel), // .channel
.src4_startofpacket (cmd_demux_src4_startofpacket), // .startofpacket
.src4_endofpacket (cmd_demux_src4_endofpacket), // .endofpacket
.src5_ready (cmd_demux_src5_ready), // src5.ready
.src5_valid (cmd_demux_src5_valid), // .valid
.src5_data (cmd_demux_src5_data), // .data
.src5_channel (cmd_demux_src5_channel), // .channel
.src5_startofpacket (cmd_demux_src5_startofpacket), // .startofpacket
.src5_endofpacket (cmd_demux_src5_endofpacket), // .endofpacket
.src6_ready (cmd_demux_src6_ready), // src6.ready
.src6_valid (cmd_demux_src6_valid), // .valid
.src6_data (cmd_demux_src6_data), // .data
.src6_channel (cmd_demux_src6_channel), // .channel
.src6_startofpacket (cmd_demux_src6_startofpacket), // .startofpacket
.src6_endofpacket (cmd_demux_src6_endofpacket), // .endofpacket
.src7_ready (cmd_demux_src7_ready), // src7.ready
.src7_valid (cmd_demux_src7_valid), // .valid
.src7_data (cmd_demux_src7_data), // .data
.src7_channel (cmd_demux_src7_channel), // .channel
.src7_startofpacket (cmd_demux_src7_startofpacket), // .startofpacket
.src7_endofpacket (cmd_demux_src7_endofpacket), // .endofpacket
.src8_ready (cmd_demux_src8_ready), // src8.ready
.src8_valid (cmd_demux_src8_valid), // .valid
.src8_data (cmd_demux_src8_data), // .data
.src8_channel (cmd_demux_src8_channel), // .channel
.src8_startofpacket (cmd_demux_src8_startofpacket), // .startofpacket
.src8_endofpacket (cmd_demux_src8_endofpacket), // .endofpacket
.src9_ready (cmd_demux_src9_ready), // src9.ready
.src9_valid (cmd_demux_src9_valid), // .valid
.src9_data (cmd_demux_src9_data), // .data
.src9_channel (cmd_demux_src9_channel), // .channel
.src9_startofpacket (cmd_demux_src9_startofpacket), // .startofpacket
.src9_endofpacket (cmd_demux_src9_endofpacket), // .endofpacket
.src10_ready (cmd_demux_src10_ready), // src10.ready
.src10_valid (cmd_demux_src10_valid), // .valid
.src10_data (cmd_demux_src10_data), // .data
.src10_channel (cmd_demux_src10_channel), // .channel
.src10_startofpacket (cmd_demux_src10_startofpacket), // .startofpacket
.src10_endofpacket (cmd_demux_src10_endofpacket), // .endofpacket
.src11_ready (cmd_demux_src11_ready), // src11.ready
.src11_valid (cmd_demux_src11_valid), // .valid
.src11_data (cmd_demux_src11_data), // .data
.src11_channel (cmd_demux_src11_channel), // .channel
.src11_startofpacket (cmd_demux_src11_startofpacket), // .startofpacket
.src11_endofpacket (cmd_demux_src11_endofpacket), // .endofpacket
.src12_ready (cmd_demux_src12_ready), // src12.ready
.src12_valid (cmd_demux_src12_valid), // .valid
.src12_data (cmd_demux_src12_data), // .data
.src12_channel (cmd_demux_src12_channel), // .channel
.src12_startofpacket (cmd_demux_src12_startofpacket), // .startofpacket
.src12_endofpacket (cmd_demux_src12_endofpacket), // .endofpacket
.src13_ready (cmd_demux_src13_ready), // src13.ready
.src13_valid (cmd_demux_src13_valid), // .valid
.src13_data (cmd_demux_src13_data), // .data
.src13_channel (cmd_demux_src13_channel), // .channel
.src13_startofpacket (cmd_demux_src13_startofpacket), // .startofpacket
.src13_endofpacket (cmd_demux_src13_endofpacket), // .endofpacket
.src14_ready (cmd_demux_src14_ready), // src14.ready
.src14_valid (cmd_demux_src14_valid), // .valid
.src14_data (cmd_demux_src14_data), // .data
.src14_channel (cmd_demux_src14_channel), // .channel
.src14_startofpacket (cmd_demux_src14_startofpacket), // .startofpacket
.src14_endofpacket (cmd_demux_src14_endofpacket), // .endofpacket
.src15_ready (cmd_demux_src15_ready), // src15.ready
.src15_valid (cmd_demux_src15_valid), // .valid
.src15_data (cmd_demux_src15_data), // .data
.src15_channel (cmd_demux_src15_channel), // .channel
.src15_startofpacket (cmd_demux_src15_startofpacket), // .startofpacket
.src15_endofpacket (cmd_demux_src15_endofpacket), // .endofpacket
.src16_ready (cmd_demux_src16_ready), // src16.ready
.src16_valid (cmd_demux_src16_valid), // .valid
.src16_data (cmd_demux_src16_data), // .data
.src16_channel (cmd_demux_src16_channel), // .channel
.src16_startofpacket (cmd_demux_src16_startofpacket), // .startofpacket
.src16_endofpacket (cmd_demux_src16_endofpacket), // .endofpacket
.src17_ready (cmd_demux_src17_ready), // src17.ready
.src17_valid (cmd_demux_src17_valid), // .valid
.src17_data (cmd_demux_src17_data), // .data
.src17_channel (cmd_demux_src17_channel), // .channel
.src17_startofpacket (cmd_demux_src17_startofpacket), // .startofpacket
.src17_endofpacket (cmd_demux_src17_endofpacket), // .endofpacket
.src18_ready (cmd_demux_src18_ready), // src18.ready
.src18_valid (cmd_demux_src18_valid), // .valid
.src18_data (cmd_demux_src18_data), // .data
.src18_channel (cmd_demux_src18_channel), // .channel
.src18_startofpacket (cmd_demux_src18_startofpacket), // .startofpacket
.src18_endofpacket (cmd_demux_src18_endofpacket), // .endofpacket
.src19_ready (cmd_demux_src19_ready), // src19.ready
.src19_valid (cmd_demux_src19_valid), // .valid
.src19_data (cmd_demux_src19_data), // .data
.src19_channel (cmd_demux_src19_channel), // .channel
.src19_startofpacket (cmd_demux_src19_startofpacket), // .startofpacket
.src19_endofpacket (cmd_demux_src19_endofpacket), // .endofpacket
.src20_ready (cmd_demux_src20_ready), // src20.ready
.src20_valid (cmd_demux_src20_valid), // .valid
.src20_data (cmd_demux_src20_data), // .data
.src20_channel (cmd_demux_src20_channel), // .channel
.src20_startofpacket (cmd_demux_src20_startofpacket), // .startofpacket
.src20_endofpacket (cmd_demux_src20_endofpacket), // .endofpacket
.src21_ready (cmd_demux_src21_ready), // src21.ready
.src21_valid (cmd_demux_src21_valid), // .valid
.src21_data (cmd_demux_src21_data), // .data
.src21_channel (cmd_demux_src21_channel), // .channel
.src21_startofpacket (cmd_demux_src21_startofpacket), // .startofpacket
.src21_endofpacket (cmd_demux_src21_endofpacket), // .endofpacket
.src22_ready (cmd_demux_src22_ready), // src22.ready
.src22_valid (cmd_demux_src22_valid), // .valid
.src22_data (cmd_demux_src22_data), // .data
.src22_channel (cmd_demux_src22_channel), // .channel
.src22_startofpacket (cmd_demux_src22_startofpacket), // .startofpacket
.src22_endofpacket (cmd_demux_src22_endofpacket), // .endofpacket
.src23_ready (cmd_demux_src23_ready), // src23.ready
.src23_valid (cmd_demux_src23_valid), // .valid
.src23_data (cmd_demux_src23_data), // .data
.src23_channel (cmd_demux_src23_channel), // .channel
.src23_startofpacket (cmd_demux_src23_startofpacket), // .startofpacket
.src23_endofpacket (cmd_demux_src23_endofpacket), // .endofpacket
.src24_ready (cmd_demux_src24_ready), // src24.ready
.src24_valid (cmd_demux_src24_valid), // .valid
.src24_data (cmd_demux_src24_data), // .data
.src24_channel (cmd_demux_src24_channel), // .channel
.src24_startofpacket (cmd_demux_src24_startofpacket), // .startofpacket
.src24_endofpacket (cmd_demux_src24_endofpacket), // .endofpacket
.src25_ready (cmd_demux_src25_ready), // src25.ready
.src25_valid (cmd_demux_src25_valid), // .valid
.src25_data (cmd_demux_src25_data), // .data
.src25_channel (cmd_demux_src25_channel), // .channel
.src25_startofpacket (cmd_demux_src25_startofpacket), // .startofpacket
.src25_endofpacket (cmd_demux_src25_endofpacket), // .endofpacket
.src26_ready (cmd_demux_src26_ready), // src26.ready
.src26_valid (cmd_demux_src26_valid), // .valid
.src26_data (cmd_demux_src26_data), // .data
.src26_channel (cmd_demux_src26_channel), // .channel
.src26_startofpacket (cmd_demux_src26_startofpacket), // .startofpacket
.src26_endofpacket (cmd_demux_src26_endofpacket), // .endofpacket
.src27_ready (cmd_demux_src27_ready), // src27.ready
.src27_valid (cmd_demux_src27_valid), // .valid
.src27_data (cmd_demux_src27_data), // .data
.src27_channel (cmd_demux_src27_channel), // .channel
.src27_startofpacket (cmd_demux_src27_startofpacket), // .startofpacket
.src27_endofpacket (cmd_demux_src27_endofpacket), // .endofpacket
.src28_ready (cmd_demux_src28_ready), // src28.ready
.src28_valid (cmd_demux_src28_valid), // .valid
.src28_data (cmd_demux_src28_data), // .data
.src28_channel (cmd_demux_src28_channel), // .channel
.src28_startofpacket (cmd_demux_src28_startofpacket), // .startofpacket
.src28_endofpacket (cmd_demux_src28_endofpacket), // .endofpacket
.src29_ready (cmd_demux_src29_ready), // src29.ready
.src29_valid (cmd_demux_src29_valid), // .valid
.src29_data (cmd_demux_src29_data), // .data
.src29_channel (cmd_demux_src29_channel), // .channel
.src29_startofpacket (cmd_demux_src29_startofpacket), // .startofpacket
.src29_endofpacket (cmd_demux_src29_endofpacket), // .endofpacket
.src30_ready (cmd_demux_src30_ready), // src30.ready
.src30_valid (cmd_demux_src30_valid), // .valid
.src30_data (cmd_demux_src30_data), // .data
.src30_channel (cmd_demux_src30_channel), // .channel
.src30_startofpacket (cmd_demux_src30_startofpacket), // .startofpacket
.src30_endofpacket (cmd_demux_src30_endofpacket), // .endofpacket
.src31_ready (cmd_demux_src31_ready), // src31.ready
.src31_valid (cmd_demux_src31_valid), // .valid
.src31_data (cmd_demux_src31_data), // .data
.src31_channel (cmd_demux_src31_channel), // .channel
.src31_startofpacket (cmd_demux_src31_startofpacket), // .startofpacket
.src31_endofpacket (cmd_demux_src31_endofpacket) // .endofpacket
);
nios_system_mm_interconnect_0_cmd_demux_001 cmd_demux_001 (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_001_src_ready), // sink.ready
.sink_channel (router_001_src_channel), // .channel
.sink_data (router_001_src_data), // .data
.sink_startofpacket (router_001_src_startofpacket), // .startofpacket
.sink_endofpacket (router_001_src_endofpacket), // .endofpacket
.sink_valid (router_001_src_valid), // .valid
.src0_ready (cmd_demux_001_src0_ready), // src0.ready
.src0_valid (cmd_demux_001_src0_valid), // .valid
.src0_data (cmd_demux_001_src0_data), // .data
.src0_channel (cmd_demux_001_src0_channel), // .channel
.src0_startofpacket (cmd_demux_001_src0_startofpacket), // .startofpacket
.src0_endofpacket (cmd_demux_001_src0_endofpacket), // .endofpacket
.src1_ready (cmd_demux_001_src1_ready), // src1.ready
.src1_valid (cmd_demux_001_src1_valid), // .valid
.src1_data (cmd_demux_001_src1_data), // .data
.src1_channel (cmd_demux_001_src1_channel), // .channel
.src1_startofpacket (cmd_demux_001_src1_startofpacket), // .startofpacket
.src1_endofpacket (cmd_demux_001_src1_endofpacket) // .endofpacket
);
nios_system_mm_interconnect_0_cmd_mux cmd_mux (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_src_ready), // src.ready
.src_valid (cmd_mux_src_valid), // .valid
.src_data (cmd_mux_src_data), // .data
.src_channel (cmd_mux_src_channel), // .channel
.src_startofpacket (cmd_mux_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_src0_ready), // sink0.ready
.sink0_valid (cmd_demux_src0_valid), // .valid
.sink0_channel (cmd_demux_src0_channel), // .channel
.sink0_data (cmd_demux_src0_data), // .data
.sink0_startofpacket (cmd_demux_src0_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_src0_endofpacket) // .endofpacket
);
nios_system_mm_interconnect_0_cmd_mux_001 cmd_mux_001 (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_001_src_ready), // src.ready
.src_valid (cmd_mux_001_src_valid), // .valid
.src_data (cmd_mux_001_src_data), // .data
.src_channel (cmd_mux_001_src_channel), // .channel
.src_startofpacket (cmd_mux_001_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_001_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_src1_ready), // sink0.ready
.sink0_valid (cmd_demux_src1_valid), // .valid
.sink0_channel (cmd_demux_src1_channel), // .channel
.sink0_data (cmd_demux_src1_data), // .data
.sink0_startofpacket (cmd_demux_src1_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_src1_endofpacket), // .endofpacket
.sink1_ready (cmd_demux_001_src0_ready), // sink1.ready
.sink1_valid (cmd_demux_001_src0_valid), // .valid
.sink1_channel (cmd_demux_001_src0_channel), // .channel
.sink1_data (cmd_demux_001_src0_data), // .data
.sink1_startofpacket (cmd_demux_001_src0_startofpacket), // .startofpacket
.sink1_endofpacket (cmd_demux_001_src0_endofpacket) // .endofpacket
);
nios_system_mm_interconnect_0_cmd_mux_001 cmd_mux_002 (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_002_src_ready), // src.ready
.src_valid (cmd_mux_002_src_valid), // .valid
.src_data (cmd_mux_002_src_data), // .data
.src_channel (cmd_mux_002_src_channel), // .channel
.src_startofpacket (cmd_mux_002_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_002_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_src2_ready), // sink0.ready
.sink0_valid (cmd_demux_src2_valid), // .valid
.sink0_channel (cmd_demux_src2_channel), // .channel
.sink0_data (cmd_demux_src2_data), // .data
.sink0_startofpacket (cmd_demux_src2_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_src2_endofpacket), // .endofpacket
.sink1_ready (cmd_demux_001_src1_ready), // sink1.ready
.sink1_valid (cmd_demux_001_src1_valid), // .valid
.sink1_channel (cmd_demux_001_src1_channel), // .channel
.sink1_data (cmd_demux_001_src1_data), // .data
.sink1_startofpacket (cmd_demux_001_src1_startofpacket), // .startofpacket
.sink1_endofpacket (cmd_demux_001_src1_endofpacket) // .endofpacket
);
nios_system_mm_interconnect_0_cmd_mux cmd_mux_003 (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_003_src_ready), // src.ready
.src_valid (cmd_mux_003_src_valid), // .valid
.src_data (cmd_mux_003_src_data), // .data
.src_channel (cmd_mux_003_src_channel), // .channel
.src_startofpacket (cmd_mux_003_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_003_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_src3_ready), // sink0.ready
.sink0_valid (cmd_demux_src3_valid), // .valid
.sink0_channel (cmd_demux_src3_channel), // .channel
.sink0_data (cmd_demux_src3_data), // .data
.sink0_startofpacket (cmd_demux_src3_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_src3_endofpacket) // .endofpacket
);
nios_system_mm_interconnect_0_cmd_mux cmd_mux_004 (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_004_src_ready), // src.ready
.src_valid (cmd_mux_004_src_valid), // .valid
.src_data (cmd_mux_004_src_data), // .data
.src_channel (cmd_mux_004_src_channel), // .channel
.src_startofpacket (cmd_mux_004_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_004_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_src4_ready), // sink0.ready
.sink0_valid (cmd_demux_src4_valid), // .valid
.sink0_channel (cmd_demux_src4_channel), // .channel
.sink0_data (cmd_demux_src4_data), // .data
.sink0_startofpacket (cmd_demux_src4_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_src4_endofpacket) // .endofpacket
);
nios_system_mm_interconnect_0_cmd_mux cmd_mux_005 (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_005_src_ready), // src.ready
.src_valid (cmd_mux_005_src_valid), // .valid
.src_data (cmd_mux_005_src_data), // .data
.src_channel (cmd_mux_005_src_channel), // .channel
.src_startofpacket (cmd_mux_005_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_005_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_src5_ready), // sink0.ready
.sink0_valid (cmd_demux_src5_valid), // .valid
.sink0_channel (cmd_demux_src5_channel), // .channel
.sink0_data (cmd_demux_src5_data), // .data
.sink0_startofpacket (cmd_demux_src5_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_src5_endofpacket) // .endofpacket
);
nios_system_mm_interconnect_0_cmd_mux cmd_mux_006 (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_006_src_ready), // src.ready
.src_valid (cmd_mux_006_src_valid), // .valid
.src_data (cmd_mux_006_src_data), // .data
.src_channel (cmd_mux_006_src_channel), // .channel
.src_startofpacket (cmd_mux_006_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_006_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_src6_ready), // sink0.ready
.sink0_valid (cmd_demux_src6_valid), // .valid
.sink0_channel (cmd_demux_src6_channel), // .channel
.sink0_data (cmd_demux_src6_data), // .data
.sink0_startofpacket (cmd_demux_src6_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_src6_endofpacket) // .endofpacket
);
nios_system_mm_interconnect_0_cmd_mux cmd_mux_007 (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_007_src_ready), // src.ready
.src_valid (cmd_mux_007_src_valid), // .valid
.src_data (cmd_mux_007_src_data), // .data
.src_channel (cmd_mux_007_src_channel), // .channel
.src_startofpacket (cmd_mux_007_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_007_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_src7_ready), // sink0.ready
.sink0_valid (cmd_demux_src7_valid), // .valid
.sink0_channel (cmd_demux_src7_channel), // .channel
.sink0_data (cmd_demux_src7_data), // .data
.sink0_startofpacket (cmd_demux_src7_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_src7_endofpacket) // .endofpacket
);
nios_system_mm_interconnect_0_cmd_mux cmd_mux_008 (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_008_src_ready), // src.ready
.src_valid (cmd_mux_008_src_valid), // .valid
.src_data (cmd_mux_008_src_data), // .data
.src_channel (cmd_mux_008_src_channel), // .channel
.src_startofpacket (cmd_mux_008_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_008_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_src8_ready), // sink0.ready
.sink0_valid (cmd_demux_src8_valid), // .valid
.sink0_channel (cmd_demux_src8_channel), // .channel
.sink0_data (cmd_demux_src8_data), // .data
.sink0_startofpacket (cmd_demux_src8_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_src8_endofpacket) // .endofpacket
);
nios_system_mm_interconnect_0_cmd_mux cmd_mux_009 (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_009_src_ready), // src.ready
.src_valid (cmd_mux_009_src_valid), // .valid
.src_data (cmd_mux_009_src_data), // .data
.src_channel (cmd_mux_009_src_channel), // .channel
.src_startofpacket (cmd_mux_009_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_009_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_src9_ready), // sink0.ready
.sink0_valid (cmd_demux_src9_valid), // .valid
.sink0_channel (cmd_demux_src9_channel), // .channel
.sink0_data (cmd_demux_src9_data), // .data
.sink0_startofpacket (cmd_demux_src9_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_src9_endofpacket) // .endofpacket
);
nios_system_mm_interconnect_0_cmd_mux cmd_mux_010 (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_010_src_ready), // src.ready
.src_valid (cmd_mux_010_src_valid), // .valid
.src_data (cmd_mux_010_src_data), // .data
.src_channel (cmd_mux_010_src_channel), // .channel
.src_startofpacket (cmd_mux_010_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_010_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_src10_ready), // sink0.ready
.sink0_valid (cmd_demux_src10_valid), // .valid
.sink0_channel (cmd_demux_src10_channel), // .channel
.sink0_data (cmd_demux_src10_data), // .data
.sink0_startofpacket (cmd_demux_src10_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_src10_endofpacket) // .endofpacket
);
nios_system_mm_interconnect_0_cmd_mux cmd_mux_011 (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_011_src_ready), // src.ready
.src_valid (cmd_mux_011_src_valid), // .valid
.src_data (cmd_mux_011_src_data), // .data
.src_channel (cmd_mux_011_src_channel), // .channel
.src_startofpacket (cmd_mux_011_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_011_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_src11_ready), // sink0.ready
.sink0_valid (cmd_demux_src11_valid), // .valid
.sink0_channel (cmd_demux_src11_channel), // .channel
.sink0_data (cmd_demux_src11_data), // .data
.sink0_startofpacket (cmd_demux_src11_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_src11_endofpacket) // .endofpacket
);
nios_system_mm_interconnect_0_cmd_mux cmd_mux_012 (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_012_src_ready), // src.ready
.src_valid (cmd_mux_012_src_valid), // .valid
.src_data (cmd_mux_012_src_data), // .data
.src_channel (cmd_mux_012_src_channel), // .channel
.src_startofpacket (cmd_mux_012_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_012_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_src12_ready), // sink0.ready
.sink0_valid (cmd_demux_src12_valid), // .valid
.sink0_channel (cmd_demux_src12_channel), // .channel
.sink0_data (cmd_demux_src12_data), // .data
.sink0_startofpacket (cmd_demux_src12_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_src12_endofpacket) // .endofpacket
);
nios_system_mm_interconnect_0_cmd_mux cmd_mux_013 (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_013_src_ready), // src.ready
.src_valid (cmd_mux_013_src_valid), // .valid
.src_data (cmd_mux_013_src_data), // .data
.src_channel (cmd_mux_013_src_channel), // .channel
.src_startofpacket (cmd_mux_013_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_013_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_src13_ready), // sink0.ready
.sink0_valid (cmd_demux_src13_valid), // .valid
.sink0_channel (cmd_demux_src13_channel), // .channel
.sink0_data (cmd_demux_src13_data), // .data
.sink0_startofpacket (cmd_demux_src13_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_src13_endofpacket) // .endofpacket
);
nios_system_mm_interconnect_0_cmd_mux cmd_mux_014 (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_014_src_ready), // src.ready
.src_valid (cmd_mux_014_src_valid), // .valid
.src_data (cmd_mux_014_src_data), // .data
.src_channel (cmd_mux_014_src_channel), // .channel
.src_startofpacket (cmd_mux_014_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_014_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_src14_ready), // sink0.ready
.sink0_valid (cmd_demux_src14_valid), // .valid
.sink0_channel (cmd_demux_src14_channel), // .channel
.sink0_data (cmd_demux_src14_data), // .data
.sink0_startofpacket (cmd_demux_src14_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_src14_endofpacket) // .endofpacket
);
nios_system_mm_interconnect_0_cmd_mux cmd_mux_015 (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_015_src_ready), // src.ready
.src_valid (cmd_mux_015_src_valid), // .valid
.src_data (cmd_mux_015_src_data), // .data
.src_channel (cmd_mux_015_src_channel), // .channel
.src_startofpacket (cmd_mux_015_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_015_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_src15_ready), // sink0.ready
.sink0_valid (cmd_demux_src15_valid), // .valid
.sink0_channel (cmd_demux_src15_channel), // .channel
.sink0_data (cmd_demux_src15_data), // .data
.sink0_startofpacket (cmd_demux_src15_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_src15_endofpacket) // .endofpacket
);
nios_system_mm_interconnect_0_cmd_mux cmd_mux_016 (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_016_src_ready), // src.ready
.src_valid (cmd_mux_016_src_valid), // .valid
.src_data (cmd_mux_016_src_data), // .data
.src_channel (cmd_mux_016_src_channel), // .channel
.src_startofpacket (cmd_mux_016_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_016_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_src16_ready), // sink0.ready
.sink0_valid (cmd_demux_src16_valid), // .valid
.sink0_channel (cmd_demux_src16_channel), // .channel
.sink0_data (cmd_demux_src16_data), // .data
.sink0_startofpacket (cmd_demux_src16_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_src16_endofpacket) // .endofpacket
);
nios_system_mm_interconnect_0_cmd_mux cmd_mux_017 (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_017_src_ready), // src.ready
.src_valid (cmd_mux_017_src_valid), // .valid
.src_data (cmd_mux_017_src_data), // .data
.src_channel (cmd_mux_017_src_channel), // .channel
.src_startofpacket (cmd_mux_017_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_017_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_src17_ready), // sink0.ready
.sink0_valid (cmd_demux_src17_valid), // .valid
.sink0_channel (cmd_demux_src17_channel), // .channel
.sink0_data (cmd_demux_src17_data), // .data
.sink0_startofpacket (cmd_demux_src17_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_src17_endofpacket) // .endofpacket
);
nios_system_mm_interconnect_0_cmd_mux cmd_mux_018 (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_018_src_ready), // src.ready
.src_valid (cmd_mux_018_src_valid), // .valid
.src_data (cmd_mux_018_src_data), // .data
.src_channel (cmd_mux_018_src_channel), // .channel
.src_startofpacket (cmd_mux_018_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_018_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_src18_ready), // sink0.ready
.sink0_valid (cmd_demux_src18_valid), // .valid
.sink0_channel (cmd_demux_src18_channel), // .channel
.sink0_data (cmd_demux_src18_data), // .data
.sink0_startofpacket (cmd_demux_src18_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_src18_endofpacket) // .endofpacket
);
nios_system_mm_interconnect_0_cmd_mux cmd_mux_019 (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_019_src_ready), // src.ready
.src_valid (cmd_mux_019_src_valid), // .valid
.src_data (cmd_mux_019_src_data), // .data
.src_channel (cmd_mux_019_src_channel), // .channel
.src_startofpacket (cmd_mux_019_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_019_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_src19_ready), // sink0.ready
.sink0_valid (cmd_demux_src19_valid), // .valid
.sink0_channel (cmd_demux_src19_channel), // .channel
.sink0_data (cmd_demux_src19_data), // .data
.sink0_startofpacket (cmd_demux_src19_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_src19_endofpacket) // .endofpacket
);
nios_system_mm_interconnect_0_cmd_mux cmd_mux_020 (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_020_src_ready), // src.ready
.src_valid (cmd_mux_020_src_valid), // .valid
.src_data (cmd_mux_020_src_data), // .data
.src_channel (cmd_mux_020_src_channel), // .channel
.src_startofpacket (cmd_mux_020_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_020_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_src20_ready), // sink0.ready
.sink0_valid (cmd_demux_src20_valid), // .valid
.sink0_channel (cmd_demux_src20_channel), // .channel
.sink0_data (cmd_demux_src20_data), // .data
.sink0_startofpacket (cmd_demux_src20_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_src20_endofpacket) // .endofpacket
);
nios_system_mm_interconnect_0_cmd_mux cmd_mux_021 (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_021_src_ready), // src.ready
.src_valid (cmd_mux_021_src_valid), // .valid
.src_data (cmd_mux_021_src_data), // .data
.src_channel (cmd_mux_021_src_channel), // .channel
.src_startofpacket (cmd_mux_021_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_021_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_src21_ready), // sink0.ready
.sink0_valid (cmd_demux_src21_valid), // .valid
.sink0_channel (cmd_demux_src21_channel), // .channel
.sink0_data (cmd_demux_src21_data), // .data
.sink0_startofpacket (cmd_demux_src21_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_src21_endofpacket) // .endofpacket
);
nios_system_mm_interconnect_0_cmd_mux cmd_mux_022 (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_022_src_ready), // src.ready
.src_valid (cmd_mux_022_src_valid), // .valid
.src_data (cmd_mux_022_src_data), // .data
.src_channel (cmd_mux_022_src_channel), // .channel
.src_startofpacket (cmd_mux_022_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_022_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_src22_ready), // sink0.ready
.sink0_valid (cmd_demux_src22_valid), // .valid
.sink0_channel (cmd_demux_src22_channel), // .channel
.sink0_data (cmd_demux_src22_data), // .data
.sink0_startofpacket (cmd_demux_src22_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_src22_endofpacket) // .endofpacket
);
nios_system_mm_interconnect_0_cmd_mux cmd_mux_023 (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_023_src_ready), // src.ready
.src_valid (cmd_mux_023_src_valid), // .valid
.src_data (cmd_mux_023_src_data), // .data
.src_channel (cmd_mux_023_src_channel), // .channel
.src_startofpacket (cmd_mux_023_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_023_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_src23_ready), // sink0.ready
.sink0_valid (cmd_demux_src23_valid), // .valid
.sink0_channel (cmd_demux_src23_channel), // .channel
.sink0_data (cmd_demux_src23_data), // .data
.sink0_startofpacket (cmd_demux_src23_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_src23_endofpacket) // .endofpacket
);
nios_system_mm_interconnect_0_cmd_mux cmd_mux_024 (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_024_src_ready), // src.ready
.src_valid (cmd_mux_024_src_valid), // .valid
.src_data (cmd_mux_024_src_data), // .data
.src_channel (cmd_mux_024_src_channel), // .channel
.src_startofpacket (cmd_mux_024_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_024_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_src24_ready), // sink0.ready
.sink0_valid (cmd_demux_src24_valid), // .valid
.sink0_channel (cmd_demux_src24_channel), // .channel
.sink0_data (cmd_demux_src24_data), // .data
.sink0_startofpacket (cmd_demux_src24_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_src24_endofpacket) // .endofpacket
);
nios_system_mm_interconnect_0_cmd_mux cmd_mux_025 (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_025_src_ready), // src.ready
.src_valid (cmd_mux_025_src_valid), // .valid
.src_data (cmd_mux_025_src_data), // .data
.src_channel (cmd_mux_025_src_channel), // .channel
.src_startofpacket (cmd_mux_025_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_025_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_src25_ready), // sink0.ready
.sink0_valid (cmd_demux_src25_valid), // .valid
.sink0_channel (cmd_demux_src25_channel), // .channel
.sink0_data (cmd_demux_src25_data), // .data
.sink0_startofpacket (cmd_demux_src25_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_src25_endofpacket) // .endofpacket
);
nios_system_mm_interconnect_0_cmd_mux cmd_mux_026 (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_026_src_ready), // src.ready
.src_valid (cmd_mux_026_src_valid), // .valid
.src_data (cmd_mux_026_src_data), // .data
.src_channel (cmd_mux_026_src_channel), // .channel
.src_startofpacket (cmd_mux_026_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_026_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_src26_ready), // sink0.ready
.sink0_valid (cmd_demux_src26_valid), // .valid
.sink0_channel (cmd_demux_src26_channel), // .channel
.sink0_data (cmd_demux_src26_data), // .data
.sink0_startofpacket (cmd_demux_src26_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_src26_endofpacket) // .endofpacket
);
nios_system_mm_interconnect_0_cmd_mux cmd_mux_027 (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_027_src_ready), // src.ready
.src_valid (cmd_mux_027_src_valid), // .valid
.src_data (cmd_mux_027_src_data), // .data
.src_channel (cmd_mux_027_src_channel), // .channel
.src_startofpacket (cmd_mux_027_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_027_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_src27_ready), // sink0.ready
.sink0_valid (cmd_demux_src27_valid), // .valid
.sink0_channel (cmd_demux_src27_channel), // .channel
.sink0_data (cmd_demux_src27_data), // .data
.sink0_startofpacket (cmd_demux_src27_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_src27_endofpacket) // .endofpacket
);
nios_system_mm_interconnect_0_cmd_mux cmd_mux_028 (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_028_src_ready), // src.ready
.src_valid (cmd_mux_028_src_valid), // .valid
.src_data (cmd_mux_028_src_data), // .data
.src_channel (cmd_mux_028_src_channel), // .channel
.src_startofpacket (cmd_mux_028_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_028_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_src28_ready), // sink0.ready
.sink0_valid (cmd_demux_src28_valid), // .valid
.sink0_channel (cmd_demux_src28_channel), // .channel
.sink0_data (cmd_demux_src28_data), // .data
.sink0_startofpacket (cmd_demux_src28_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_src28_endofpacket) // .endofpacket
);
nios_system_mm_interconnect_0_cmd_mux cmd_mux_029 (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_029_src_ready), // src.ready
.src_valid (cmd_mux_029_src_valid), // .valid
.src_data (cmd_mux_029_src_data), // .data
.src_channel (cmd_mux_029_src_channel), // .channel
.src_startofpacket (cmd_mux_029_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_029_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_src29_ready), // sink0.ready
.sink0_valid (cmd_demux_src29_valid), // .valid
.sink0_channel (cmd_demux_src29_channel), // .channel
.sink0_data (cmd_demux_src29_data), // .data
.sink0_startofpacket (cmd_demux_src29_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_src29_endofpacket) // .endofpacket
);
nios_system_mm_interconnect_0_cmd_mux cmd_mux_030 (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_030_src_ready), // src.ready
.src_valid (cmd_mux_030_src_valid), // .valid
.src_data (cmd_mux_030_src_data), // .data
.src_channel (cmd_mux_030_src_channel), // .channel
.src_startofpacket (cmd_mux_030_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_030_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_src30_ready), // sink0.ready
.sink0_valid (cmd_demux_src30_valid), // .valid
.sink0_channel (cmd_demux_src30_channel), // .channel
.sink0_data (cmd_demux_src30_data), // .data
.sink0_startofpacket (cmd_demux_src30_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_src30_endofpacket) // .endofpacket
);
nios_system_mm_interconnect_0_cmd_mux cmd_mux_031 (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_031_src_ready), // src.ready
.src_valid (cmd_mux_031_src_valid), // .valid
.src_data (cmd_mux_031_src_data), // .data
.src_channel (cmd_mux_031_src_channel), // .channel
.src_startofpacket (cmd_mux_031_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_031_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_src31_ready), // sink0.ready
.sink0_valid (cmd_demux_src31_valid), // .valid
.sink0_channel (cmd_demux_src31_channel), // .channel
.sink0_data (cmd_demux_src31_data), // .data
.sink0_startofpacket (cmd_demux_src31_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_src31_endofpacket) // .endofpacket
);
nios_system_mm_interconnect_0_rsp_demux rsp_demux (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_002_src_ready), // sink.ready
.sink_channel (router_002_src_channel), // .channel
.sink_data (router_002_src_data), // .data
.sink_startofpacket (router_002_src_startofpacket), // .startofpacket
.sink_endofpacket (router_002_src_endofpacket), // .endofpacket
.sink_valid (router_002_src_valid), // .valid
.src0_ready (rsp_demux_src0_ready), // src0.ready
.src0_valid (rsp_demux_src0_valid), // .valid
.src0_data (rsp_demux_src0_data), // .data
.src0_channel (rsp_demux_src0_channel), // .channel
.src0_startofpacket (rsp_demux_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_src0_endofpacket) // .endofpacket
);
nios_system_mm_interconnect_0_cmd_demux_001 rsp_demux_001 (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_003_src_ready), // sink.ready
.sink_channel (router_003_src_channel), // .channel
.sink_data (router_003_src_data), // .data
.sink_startofpacket (router_003_src_startofpacket), // .startofpacket
.sink_endofpacket (router_003_src_endofpacket), // .endofpacket
.sink_valid (router_003_src_valid), // .valid
.src0_ready (rsp_demux_001_src0_ready), // src0.ready
.src0_valid (rsp_demux_001_src0_valid), // .valid
.src0_data (rsp_demux_001_src0_data), // .data
.src0_channel (rsp_demux_001_src0_channel), // .channel
.src0_startofpacket (rsp_demux_001_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_001_src0_endofpacket), // .endofpacket
.src1_ready (rsp_demux_001_src1_ready), // src1.ready
.src1_valid (rsp_demux_001_src1_valid), // .valid
.src1_data (rsp_demux_001_src1_data), // .data
.src1_channel (rsp_demux_001_src1_channel), // .channel
.src1_startofpacket (rsp_demux_001_src1_startofpacket), // .startofpacket
.src1_endofpacket (rsp_demux_001_src1_endofpacket) // .endofpacket
);
nios_system_mm_interconnect_0_cmd_demux_001 rsp_demux_002 (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_004_src_ready), // sink.ready
.sink_channel (router_004_src_channel), // .channel
.sink_data (router_004_src_data), // .data
.sink_startofpacket (router_004_src_startofpacket), // .startofpacket
.sink_endofpacket (router_004_src_endofpacket), // .endofpacket
.sink_valid (router_004_src_valid), // .valid
.src0_ready (rsp_demux_002_src0_ready), // src0.ready
.src0_valid (rsp_demux_002_src0_valid), // .valid
.src0_data (rsp_demux_002_src0_data), // .data
.src0_channel (rsp_demux_002_src0_channel), // .channel
.src0_startofpacket (rsp_demux_002_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_002_src0_endofpacket), // .endofpacket
.src1_ready (rsp_demux_002_src1_ready), // src1.ready
.src1_valid (rsp_demux_002_src1_valid), // .valid
.src1_data (rsp_demux_002_src1_data), // .data
.src1_channel (rsp_demux_002_src1_channel), // .channel
.src1_startofpacket (rsp_demux_002_src1_startofpacket), // .startofpacket
.src1_endofpacket (rsp_demux_002_src1_endofpacket) // .endofpacket
);
nios_system_mm_interconnect_0_rsp_demux rsp_demux_003 (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_005_src_ready), // sink.ready
.sink_channel (router_005_src_channel), // .channel
.sink_data (router_005_src_data), // .data
.sink_startofpacket (router_005_src_startofpacket), // .startofpacket
.sink_endofpacket (router_005_src_endofpacket), // .endofpacket
.sink_valid (router_005_src_valid), // .valid
.src0_ready (rsp_demux_003_src0_ready), // src0.ready
.src0_valid (rsp_demux_003_src0_valid), // .valid
.src0_data (rsp_demux_003_src0_data), // .data
.src0_channel (rsp_demux_003_src0_channel), // .channel
.src0_startofpacket (rsp_demux_003_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_003_src0_endofpacket) // .endofpacket
);
nios_system_mm_interconnect_0_rsp_demux rsp_demux_004 (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_006_src_ready), // sink.ready
.sink_channel (router_006_src_channel), // .channel
.sink_data (router_006_src_data), // .data
.sink_startofpacket (router_006_src_startofpacket), // .startofpacket
.sink_endofpacket (router_006_src_endofpacket), // .endofpacket
.sink_valid (router_006_src_valid), // .valid
.src0_ready (rsp_demux_004_src0_ready), // src0.ready
.src0_valid (rsp_demux_004_src0_valid), // .valid
.src0_data (rsp_demux_004_src0_data), // .data
.src0_channel (rsp_demux_004_src0_channel), // .channel
.src0_startofpacket (rsp_demux_004_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_004_src0_endofpacket) // .endofpacket
);
nios_system_mm_interconnect_0_rsp_demux rsp_demux_005 (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_007_src_ready), // sink.ready
.sink_channel (router_007_src_channel), // .channel
.sink_data (router_007_src_data), // .data
.sink_startofpacket (router_007_src_startofpacket), // .startofpacket
.sink_endofpacket (router_007_src_endofpacket), // .endofpacket
.sink_valid (router_007_src_valid), // .valid
.src0_ready (rsp_demux_005_src0_ready), // src0.ready
.src0_valid (rsp_demux_005_src0_valid), // .valid
.src0_data (rsp_demux_005_src0_data), // .data
.src0_channel (rsp_demux_005_src0_channel), // .channel
.src0_startofpacket (rsp_demux_005_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_005_src0_endofpacket) // .endofpacket
);
nios_system_mm_interconnect_0_rsp_demux rsp_demux_006 (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_008_src_ready), // sink.ready
.sink_channel (router_008_src_channel), // .channel
.sink_data (router_008_src_data), // .data
.sink_startofpacket (router_008_src_startofpacket), // .startofpacket
.sink_endofpacket (router_008_src_endofpacket), // .endofpacket
.sink_valid (router_008_src_valid), // .valid
.src0_ready (rsp_demux_006_src0_ready), // src0.ready
.src0_valid (rsp_demux_006_src0_valid), // .valid
.src0_data (rsp_demux_006_src0_data), // .data
.src0_channel (rsp_demux_006_src0_channel), // .channel
.src0_startofpacket (rsp_demux_006_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_006_src0_endofpacket) // .endofpacket
);
nios_system_mm_interconnect_0_rsp_demux rsp_demux_007 (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_009_src_ready), // sink.ready
.sink_channel (router_009_src_channel), // .channel
.sink_data (router_009_src_data), // .data
.sink_startofpacket (router_009_src_startofpacket), // .startofpacket
.sink_endofpacket (router_009_src_endofpacket), // .endofpacket
.sink_valid (router_009_src_valid), // .valid
.src0_ready (rsp_demux_007_src0_ready), // src0.ready
.src0_valid (rsp_demux_007_src0_valid), // .valid
.src0_data (rsp_demux_007_src0_data), // .data
.src0_channel (rsp_demux_007_src0_channel), // .channel
.src0_startofpacket (rsp_demux_007_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_007_src0_endofpacket) // .endofpacket
);
nios_system_mm_interconnect_0_rsp_demux rsp_demux_008 (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_010_src_ready), // sink.ready
.sink_channel (router_010_src_channel), // .channel
.sink_data (router_010_src_data), // .data
.sink_startofpacket (router_010_src_startofpacket), // .startofpacket
.sink_endofpacket (router_010_src_endofpacket), // .endofpacket
.sink_valid (router_010_src_valid), // .valid
.src0_ready (rsp_demux_008_src0_ready), // src0.ready
.src0_valid (rsp_demux_008_src0_valid), // .valid
.src0_data (rsp_demux_008_src0_data), // .data
.src0_channel (rsp_demux_008_src0_channel), // .channel
.src0_startofpacket (rsp_demux_008_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_008_src0_endofpacket) // .endofpacket
);
nios_system_mm_interconnect_0_rsp_demux rsp_demux_009 (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_011_src_ready), // sink.ready
.sink_channel (router_011_src_channel), // .channel
.sink_data (router_011_src_data), // .data
.sink_startofpacket (router_011_src_startofpacket), // .startofpacket
.sink_endofpacket (router_011_src_endofpacket), // .endofpacket
.sink_valid (router_011_src_valid), // .valid
.src0_ready (rsp_demux_009_src0_ready), // src0.ready
.src0_valid (rsp_demux_009_src0_valid), // .valid
.src0_data (rsp_demux_009_src0_data), // .data
.src0_channel (rsp_demux_009_src0_channel), // .channel
.src0_startofpacket (rsp_demux_009_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_009_src0_endofpacket) // .endofpacket
);
nios_system_mm_interconnect_0_rsp_demux rsp_demux_010 (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_012_src_ready), // sink.ready
.sink_channel (router_012_src_channel), // .channel
.sink_data (router_012_src_data), // .data
.sink_startofpacket (router_012_src_startofpacket), // .startofpacket
.sink_endofpacket (router_012_src_endofpacket), // .endofpacket
.sink_valid (router_012_src_valid), // .valid
.src0_ready (rsp_demux_010_src0_ready), // src0.ready
.src0_valid (rsp_demux_010_src0_valid), // .valid
.src0_data (rsp_demux_010_src0_data), // .data
.src0_channel (rsp_demux_010_src0_channel), // .channel
.src0_startofpacket (rsp_demux_010_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_010_src0_endofpacket) // .endofpacket
);
nios_system_mm_interconnect_0_rsp_demux rsp_demux_011 (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_013_src_ready), // sink.ready
.sink_channel (router_013_src_channel), // .channel
.sink_data (router_013_src_data), // .data
.sink_startofpacket (router_013_src_startofpacket), // .startofpacket
.sink_endofpacket (router_013_src_endofpacket), // .endofpacket
.sink_valid (router_013_src_valid), // .valid
.src0_ready (rsp_demux_011_src0_ready), // src0.ready
.src0_valid (rsp_demux_011_src0_valid), // .valid
.src0_data (rsp_demux_011_src0_data), // .data
.src0_channel (rsp_demux_011_src0_channel), // .channel
.src0_startofpacket (rsp_demux_011_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_011_src0_endofpacket) // .endofpacket
);
nios_system_mm_interconnect_0_rsp_demux rsp_demux_012 (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_014_src_ready), // sink.ready
.sink_channel (router_014_src_channel), // .channel
.sink_data (router_014_src_data), // .data
.sink_startofpacket (router_014_src_startofpacket), // .startofpacket
.sink_endofpacket (router_014_src_endofpacket), // .endofpacket
.sink_valid (router_014_src_valid), // .valid
.src0_ready (rsp_demux_012_src0_ready), // src0.ready
.src0_valid (rsp_demux_012_src0_valid), // .valid
.src0_data (rsp_demux_012_src0_data), // .data
.src0_channel (rsp_demux_012_src0_channel), // .channel
.src0_startofpacket (rsp_demux_012_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_012_src0_endofpacket) // .endofpacket
);
nios_system_mm_interconnect_0_rsp_demux rsp_demux_013 (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_015_src_ready), // sink.ready
.sink_channel (router_015_src_channel), // .channel
.sink_data (router_015_src_data), // .data
.sink_startofpacket (router_015_src_startofpacket), // .startofpacket
.sink_endofpacket (router_015_src_endofpacket), // .endofpacket
.sink_valid (router_015_src_valid), // .valid
.src0_ready (rsp_demux_013_src0_ready), // src0.ready
.src0_valid (rsp_demux_013_src0_valid), // .valid
.src0_data (rsp_demux_013_src0_data), // .data
.src0_channel (rsp_demux_013_src0_channel), // .channel
.src0_startofpacket (rsp_demux_013_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_013_src0_endofpacket) // .endofpacket
);
nios_system_mm_interconnect_0_rsp_demux rsp_demux_014 (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_016_src_ready), // sink.ready
.sink_channel (router_016_src_channel), // .channel
.sink_data (router_016_src_data), // .data
.sink_startofpacket (router_016_src_startofpacket), // .startofpacket
.sink_endofpacket (router_016_src_endofpacket), // .endofpacket
.sink_valid (router_016_src_valid), // .valid
.src0_ready (rsp_demux_014_src0_ready), // src0.ready
.src0_valid (rsp_demux_014_src0_valid), // .valid
.src0_data (rsp_demux_014_src0_data), // .data
.src0_channel (rsp_demux_014_src0_channel), // .channel
.src0_startofpacket (rsp_demux_014_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_014_src0_endofpacket) // .endofpacket
);
nios_system_mm_interconnect_0_rsp_demux rsp_demux_015 (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_017_src_ready), // sink.ready
.sink_channel (router_017_src_channel), // .channel
.sink_data (router_017_src_data), // .data
.sink_startofpacket (router_017_src_startofpacket), // .startofpacket
.sink_endofpacket (router_017_src_endofpacket), // .endofpacket
.sink_valid (router_017_src_valid), // .valid
.src0_ready (rsp_demux_015_src0_ready), // src0.ready
.src0_valid (rsp_demux_015_src0_valid), // .valid
.src0_data (rsp_demux_015_src0_data), // .data
.src0_channel (rsp_demux_015_src0_channel), // .channel
.src0_startofpacket (rsp_demux_015_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_015_src0_endofpacket) // .endofpacket
);
nios_system_mm_interconnect_0_rsp_demux rsp_demux_016 (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_018_src_ready), // sink.ready
.sink_channel (router_018_src_channel), // .channel
.sink_data (router_018_src_data), // .data
.sink_startofpacket (router_018_src_startofpacket), // .startofpacket
.sink_endofpacket (router_018_src_endofpacket), // .endofpacket
.sink_valid (router_018_src_valid), // .valid
.src0_ready (rsp_demux_016_src0_ready), // src0.ready
.src0_valid (rsp_demux_016_src0_valid), // .valid
.src0_data (rsp_demux_016_src0_data), // .data
.src0_channel (rsp_demux_016_src0_channel), // .channel
.src0_startofpacket (rsp_demux_016_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_016_src0_endofpacket) // .endofpacket
);
nios_system_mm_interconnect_0_rsp_demux rsp_demux_017 (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_019_src_ready), // sink.ready
.sink_channel (router_019_src_channel), // .channel
.sink_data (router_019_src_data), // .data
.sink_startofpacket (router_019_src_startofpacket), // .startofpacket
.sink_endofpacket (router_019_src_endofpacket), // .endofpacket
.sink_valid (router_019_src_valid), // .valid
.src0_ready (rsp_demux_017_src0_ready), // src0.ready
.src0_valid (rsp_demux_017_src0_valid), // .valid
.src0_data (rsp_demux_017_src0_data), // .data
.src0_channel (rsp_demux_017_src0_channel), // .channel
.src0_startofpacket (rsp_demux_017_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_017_src0_endofpacket) // .endofpacket
);
nios_system_mm_interconnect_0_rsp_demux rsp_demux_018 (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_020_src_ready), // sink.ready
.sink_channel (router_020_src_channel), // .channel
.sink_data (router_020_src_data), // .data
.sink_startofpacket (router_020_src_startofpacket), // .startofpacket
.sink_endofpacket (router_020_src_endofpacket), // .endofpacket
.sink_valid (router_020_src_valid), // .valid
.src0_ready (rsp_demux_018_src0_ready), // src0.ready
.src0_valid (rsp_demux_018_src0_valid), // .valid
.src0_data (rsp_demux_018_src0_data), // .data
.src0_channel (rsp_demux_018_src0_channel), // .channel
.src0_startofpacket (rsp_demux_018_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_018_src0_endofpacket) // .endofpacket
);
nios_system_mm_interconnect_0_rsp_demux rsp_demux_019 (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_021_src_ready), // sink.ready
.sink_channel (router_021_src_channel), // .channel
.sink_data (router_021_src_data), // .data
.sink_startofpacket (router_021_src_startofpacket), // .startofpacket
.sink_endofpacket (router_021_src_endofpacket), // .endofpacket
.sink_valid (router_021_src_valid), // .valid
.src0_ready (rsp_demux_019_src0_ready), // src0.ready
.src0_valid (rsp_demux_019_src0_valid), // .valid
.src0_data (rsp_demux_019_src0_data), // .data
.src0_channel (rsp_demux_019_src0_channel), // .channel
.src0_startofpacket (rsp_demux_019_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_019_src0_endofpacket) // .endofpacket
);
nios_system_mm_interconnect_0_rsp_demux rsp_demux_020 (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_022_src_ready), // sink.ready
.sink_channel (router_022_src_channel), // .channel
.sink_data (router_022_src_data), // .data
.sink_startofpacket (router_022_src_startofpacket), // .startofpacket
.sink_endofpacket (router_022_src_endofpacket), // .endofpacket
.sink_valid (router_022_src_valid), // .valid
.src0_ready (rsp_demux_020_src0_ready), // src0.ready
.src0_valid (rsp_demux_020_src0_valid), // .valid
.src0_data (rsp_demux_020_src0_data), // .data
.src0_channel (rsp_demux_020_src0_channel), // .channel
.src0_startofpacket (rsp_demux_020_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_020_src0_endofpacket) // .endofpacket
);
nios_system_mm_interconnect_0_rsp_demux rsp_demux_021 (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_023_src_ready), // sink.ready
.sink_channel (router_023_src_channel), // .channel
.sink_data (router_023_src_data), // .data
.sink_startofpacket (router_023_src_startofpacket), // .startofpacket
.sink_endofpacket (router_023_src_endofpacket), // .endofpacket
.sink_valid (router_023_src_valid), // .valid
.src0_ready (rsp_demux_021_src0_ready), // src0.ready
.src0_valid (rsp_demux_021_src0_valid), // .valid
.src0_data (rsp_demux_021_src0_data), // .data
.src0_channel (rsp_demux_021_src0_channel), // .channel
.src0_startofpacket (rsp_demux_021_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_021_src0_endofpacket) // .endofpacket
);
nios_system_mm_interconnect_0_rsp_demux rsp_demux_022 (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_024_src_ready), // sink.ready
.sink_channel (router_024_src_channel), // .channel
.sink_data (router_024_src_data), // .data
.sink_startofpacket (router_024_src_startofpacket), // .startofpacket
.sink_endofpacket (router_024_src_endofpacket), // .endofpacket
.sink_valid (router_024_src_valid), // .valid
.src0_ready (rsp_demux_022_src0_ready), // src0.ready
.src0_valid (rsp_demux_022_src0_valid), // .valid
.src0_data (rsp_demux_022_src0_data), // .data
.src0_channel (rsp_demux_022_src0_channel), // .channel
.src0_startofpacket (rsp_demux_022_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_022_src0_endofpacket) // .endofpacket
);
nios_system_mm_interconnect_0_rsp_demux rsp_demux_023 (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_025_src_ready), // sink.ready
.sink_channel (router_025_src_channel), // .channel
.sink_data (router_025_src_data), // .data
.sink_startofpacket (router_025_src_startofpacket), // .startofpacket
.sink_endofpacket (router_025_src_endofpacket), // .endofpacket
.sink_valid (router_025_src_valid), // .valid
.src0_ready (rsp_demux_023_src0_ready), // src0.ready
.src0_valid (rsp_demux_023_src0_valid), // .valid
.src0_data (rsp_demux_023_src0_data), // .data
.src0_channel (rsp_demux_023_src0_channel), // .channel
.src0_startofpacket (rsp_demux_023_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_023_src0_endofpacket) // .endofpacket
);
nios_system_mm_interconnect_0_rsp_demux rsp_demux_024 (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_026_src_ready), // sink.ready
.sink_channel (router_026_src_channel), // .channel
.sink_data (router_026_src_data), // .data
.sink_startofpacket (router_026_src_startofpacket), // .startofpacket
.sink_endofpacket (router_026_src_endofpacket), // .endofpacket
.sink_valid (router_026_src_valid), // .valid
.src0_ready (rsp_demux_024_src0_ready), // src0.ready
.src0_valid (rsp_demux_024_src0_valid), // .valid
.src0_data (rsp_demux_024_src0_data), // .data
.src0_channel (rsp_demux_024_src0_channel), // .channel
.src0_startofpacket (rsp_demux_024_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_024_src0_endofpacket) // .endofpacket
);
nios_system_mm_interconnect_0_rsp_demux rsp_demux_025 (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_027_src_ready), // sink.ready
.sink_channel (router_027_src_channel), // .channel
.sink_data (router_027_src_data), // .data
.sink_startofpacket (router_027_src_startofpacket), // .startofpacket
.sink_endofpacket (router_027_src_endofpacket), // .endofpacket
.sink_valid (router_027_src_valid), // .valid
.src0_ready (rsp_demux_025_src0_ready), // src0.ready
.src0_valid (rsp_demux_025_src0_valid), // .valid
.src0_data (rsp_demux_025_src0_data), // .data
.src0_channel (rsp_demux_025_src0_channel), // .channel
.src0_startofpacket (rsp_demux_025_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_025_src0_endofpacket) // .endofpacket
);
nios_system_mm_interconnect_0_rsp_demux rsp_demux_026 (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_028_src_ready), // sink.ready
.sink_channel (router_028_src_channel), // .channel
.sink_data (router_028_src_data), // .data
.sink_startofpacket (router_028_src_startofpacket), // .startofpacket
.sink_endofpacket (router_028_src_endofpacket), // .endofpacket
.sink_valid (router_028_src_valid), // .valid
.src0_ready (rsp_demux_026_src0_ready), // src0.ready
.src0_valid (rsp_demux_026_src0_valid), // .valid
.src0_data (rsp_demux_026_src0_data), // .data
.src0_channel (rsp_demux_026_src0_channel), // .channel
.src0_startofpacket (rsp_demux_026_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_026_src0_endofpacket) // .endofpacket
);
nios_system_mm_interconnect_0_rsp_demux rsp_demux_027 (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_029_src_ready), // sink.ready
.sink_channel (router_029_src_channel), // .channel
.sink_data (router_029_src_data), // .data
.sink_startofpacket (router_029_src_startofpacket), // .startofpacket
.sink_endofpacket (router_029_src_endofpacket), // .endofpacket
.sink_valid (router_029_src_valid), // .valid
.src0_ready (rsp_demux_027_src0_ready), // src0.ready
.src0_valid (rsp_demux_027_src0_valid), // .valid
.src0_data (rsp_demux_027_src0_data), // .data
.src0_channel (rsp_demux_027_src0_channel), // .channel
.src0_startofpacket (rsp_demux_027_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_027_src0_endofpacket) // .endofpacket
);
nios_system_mm_interconnect_0_rsp_demux rsp_demux_028 (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_030_src_ready), // sink.ready
.sink_channel (router_030_src_channel), // .channel
.sink_data (router_030_src_data), // .data
.sink_startofpacket (router_030_src_startofpacket), // .startofpacket
.sink_endofpacket (router_030_src_endofpacket), // .endofpacket
.sink_valid (router_030_src_valid), // .valid
.src0_ready (rsp_demux_028_src0_ready), // src0.ready
.src0_valid (rsp_demux_028_src0_valid), // .valid
.src0_data (rsp_demux_028_src0_data), // .data
.src0_channel (rsp_demux_028_src0_channel), // .channel
.src0_startofpacket (rsp_demux_028_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_028_src0_endofpacket) // .endofpacket
);
nios_system_mm_interconnect_0_rsp_demux rsp_demux_029 (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_031_src_ready), // sink.ready
.sink_channel (router_031_src_channel), // .channel
.sink_data (router_031_src_data), // .data
.sink_startofpacket (router_031_src_startofpacket), // .startofpacket
.sink_endofpacket (router_031_src_endofpacket), // .endofpacket
.sink_valid (router_031_src_valid), // .valid
.src0_ready (rsp_demux_029_src0_ready), // src0.ready
.src0_valid (rsp_demux_029_src0_valid), // .valid
.src0_data (rsp_demux_029_src0_data), // .data
.src0_channel (rsp_demux_029_src0_channel), // .channel
.src0_startofpacket (rsp_demux_029_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_029_src0_endofpacket) // .endofpacket
);
nios_system_mm_interconnect_0_rsp_demux rsp_demux_030 (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_032_src_ready), // sink.ready
.sink_channel (router_032_src_channel), // .channel
.sink_data (router_032_src_data), // .data
.sink_startofpacket (router_032_src_startofpacket), // .startofpacket
.sink_endofpacket (router_032_src_endofpacket), // .endofpacket
.sink_valid (router_032_src_valid), // .valid
.src0_ready (rsp_demux_030_src0_ready), // src0.ready
.src0_valid (rsp_demux_030_src0_valid), // .valid
.src0_data (rsp_demux_030_src0_data), // .data
.src0_channel (rsp_demux_030_src0_channel), // .channel
.src0_startofpacket (rsp_demux_030_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_030_src0_endofpacket) // .endofpacket
);
nios_system_mm_interconnect_0_rsp_demux rsp_demux_031 (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_033_src_ready), // sink.ready
.sink_channel (router_033_src_channel), // .channel
.sink_data (router_033_src_data), // .data
.sink_startofpacket (router_033_src_startofpacket), // .startofpacket
.sink_endofpacket (router_033_src_endofpacket), // .endofpacket
.sink_valid (router_033_src_valid), // .valid
.src0_ready (rsp_demux_031_src0_ready), // src0.ready
.src0_valid (rsp_demux_031_src0_valid), // .valid
.src0_data (rsp_demux_031_src0_data), // .data
.src0_channel (rsp_demux_031_src0_channel), // .channel
.src0_startofpacket (rsp_demux_031_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_031_src0_endofpacket) // .endofpacket
);
nios_system_mm_interconnect_0_rsp_mux rsp_mux (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (rsp_mux_src_ready), // src.ready
.src_valid (rsp_mux_src_valid), // .valid
.src_data (rsp_mux_src_data), // .data
.src_channel (rsp_mux_src_channel), // .channel
.src_startofpacket (rsp_mux_src_startofpacket), // .startofpacket
.src_endofpacket (rsp_mux_src_endofpacket), // .endofpacket
.sink0_ready (rsp_demux_src0_ready), // sink0.ready
.sink0_valid (rsp_demux_src0_valid), // .valid
.sink0_channel (rsp_demux_src0_channel), // .channel
.sink0_data (rsp_demux_src0_data), // .data
.sink0_startofpacket (rsp_demux_src0_startofpacket), // .startofpacket
.sink0_endofpacket (rsp_demux_src0_endofpacket), // .endofpacket
.sink1_ready (rsp_demux_001_src0_ready), // sink1.ready
.sink1_valid (rsp_demux_001_src0_valid), // .valid
.sink1_channel (rsp_demux_001_src0_channel), // .channel
.sink1_data (rsp_demux_001_src0_data), // .data
.sink1_startofpacket (rsp_demux_001_src0_startofpacket), // .startofpacket
.sink1_endofpacket (rsp_demux_001_src0_endofpacket), // .endofpacket
.sink2_ready (rsp_demux_002_src0_ready), // sink2.ready
.sink2_valid (rsp_demux_002_src0_valid), // .valid
.sink2_channel (rsp_demux_002_src0_channel), // .channel
.sink2_data (rsp_demux_002_src0_data), // .data
.sink2_startofpacket (rsp_demux_002_src0_startofpacket), // .startofpacket
.sink2_endofpacket (rsp_demux_002_src0_endofpacket), // .endofpacket
.sink3_ready (rsp_demux_003_src0_ready), // sink3.ready
.sink3_valid (rsp_demux_003_src0_valid), // .valid
.sink3_channel (rsp_demux_003_src0_channel), // .channel
.sink3_data (rsp_demux_003_src0_data), // .data
.sink3_startofpacket (rsp_demux_003_src0_startofpacket), // .startofpacket
.sink3_endofpacket (rsp_demux_003_src0_endofpacket), // .endofpacket
.sink4_ready (rsp_demux_004_src0_ready), // sink4.ready
.sink4_valid (rsp_demux_004_src0_valid), // .valid
.sink4_channel (rsp_demux_004_src0_channel), // .channel
.sink4_data (rsp_demux_004_src0_data), // .data
.sink4_startofpacket (rsp_demux_004_src0_startofpacket), // .startofpacket
.sink4_endofpacket (rsp_demux_004_src0_endofpacket), // .endofpacket
.sink5_ready (rsp_demux_005_src0_ready), // sink5.ready
.sink5_valid (rsp_demux_005_src0_valid), // .valid
.sink5_channel (rsp_demux_005_src0_channel), // .channel
.sink5_data (rsp_demux_005_src0_data), // .data
.sink5_startofpacket (rsp_demux_005_src0_startofpacket), // .startofpacket
.sink5_endofpacket (rsp_demux_005_src0_endofpacket), // .endofpacket
.sink6_ready (rsp_demux_006_src0_ready), // sink6.ready
.sink6_valid (rsp_demux_006_src0_valid), // .valid
.sink6_channel (rsp_demux_006_src0_channel), // .channel
.sink6_data (rsp_demux_006_src0_data), // .data
.sink6_startofpacket (rsp_demux_006_src0_startofpacket), // .startofpacket
.sink6_endofpacket (rsp_demux_006_src0_endofpacket), // .endofpacket
.sink7_ready (rsp_demux_007_src0_ready), // sink7.ready
.sink7_valid (rsp_demux_007_src0_valid), // .valid
.sink7_channel (rsp_demux_007_src0_channel), // .channel
.sink7_data (rsp_demux_007_src0_data), // .data
.sink7_startofpacket (rsp_demux_007_src0_startofpacket), // .startofpacket
.sink7_endofpacket (rsp_demux_007_src0_endofpacket), // .endofpacket
.sink8_ready (rsp_demux_008_src0_ready), // sink8.ready
.sink8_valid (rsp_demux_008_src0_valid), // .valid
.sink8_channel (rsp_demux_008_src0_channel), // .channel
.sink8_data (rsp_demux_008_src0_data), // .data
.sink8_startofpacket (rsp_demux_008_src0_startofpacket), // .startofpacket
.sink8_endofpacket (rsp_demux_008_src0_endofpacket), // .endofpacket
.sink9_ready (rsp_demux_009_src0_ready), // sink9.ready
.sink9_valid (rsp_demux_009_src0_valid), // .valid
.sink9_channel (rsp_demux_009_src0_channel), // .channel
.sink9_data (rsp_demux_009_src0_data), // .data
.sink9_startofpacket (rsp_demux_009_src0_startofpacket), // .startofpacket
.sink9_endofpacket (rsp_demux_009_src0_endofpacket), // .endofpacket
.sink10_ready (rsp_demux_010_src0_ready), // sink10.ready
.sink10_valid (rsp_demux_010_src0_valid), // .valid
.sink10_channel (rsp_demux_010_src0_channel), // .channel
.sink10_data (rsp_demux_010_src0_data), // .data
.sink10_startofpacket (rsp_demux_010_src0_startofpacket), // .startofpacket
.sink10_endofpacket (rsp_demux_010_src0_endofpacket), // .endofpacket
.sink11_ready (rsp_demux_011_src0_ready), // sink11.ready
.sink11_valid (rsp_demux_011_src0_valid), // .valid
.sink11_channel (rsp_demux_011_src0_channel), // .channel
.sink11_data (rsp_demux_011_src0_data), // .data
.sink11_startofpacket (rsp_demux_011_src0_startofpacket), // .startofpacket
.sink11_endofpacket (rsp_demux_011_src0_endofpacket), // .endofpacket
.sink12_ready (rsp_demux_012_src0_ready), // sink12.ready
.sink12_valid (rsp_demux_012_src0_valid), // .valid
.sink12_channel (rsp_demux_012_src0_channel), // .channel
.sink12_data (rsp_demux_012_src0_data), // .data
.sink12_startofpacket (rsp_demux_012_src0_startofpacket), // .startofpacket
.sink12_endofpacket (rsp_demux_012_src0_endofpacket), // .endofpacket
.sink13_ready (rsp_demux_013_src0_ready), // sink13.ready
.sink13_valid (rsp_demux_013_src0_valid), // .valid
.sink13_channel (rsp_demux_013_src0_channel), // .channel
.sink13_data (rsp_demux_013_src0_data), // .data
.sink13_startofpacket (rsp_demux_013_src0_startofpacket), // .startofpacket
.sink13_endofpacket (rsp_demux_013_src0_endofpacket), // .endofpacket
.sink14_ready (rsp_demux_014_src0_ready), // sink14.ready
.sink14_valid (rsp_demux_014_src0_valid), // .valid
.sink14_channel (rsp_demux_014_src0_channel), // .channel
.sink14_data (rsp_demux_014_src0_data), // .data
.sink14_startofpacket (rsp_demux_014_src0_startofpacket), // .startofpacket
.sink14_endofpacket (rsp_demux_014_src0_endofpacket), // .endofpacket
.sink15_ready (rsp_demux_015_src0_ready), // sink15.ready
.sink15_valid (rsp_demux_015_src0_valid), // .valid
.sink15_channel (rsp_demux_015_src0_channel), // .channel
.sink15_data (rsp_demux_015_src0_data), // .data
.sink15_startofpacket (rsp_demux_015_src0_startofpacket), // .startofpacket
.sink15_endofpacket (rsp_demux_015_src0_endofpacket), // .endofpacket
.sink16_ready (rsp_demux_016_src0_ready), // sink16.ready
.sink16_valid (rsp_demux_016_src0_valid), // .valid
.sink16_channel (rsp_demux_016_src0_channel), // .channel
.sink16_data (rsp_demux_016_src0_data), // .data
.sink16_startofpacket (rsp_demux_016_src0_startofpacket), // .startofpacket
.sink16_endofpacket (rsp_demux_016_src0_endofpacket), // .endofpacket
.sink17_ready (rsp_demux_017_src0_ready), // sink17.ready
.sink17_valid (rsp_demux_017_src0_valid), // .valid
.sink17_channel (rsp_demux_017_src0_channel), // .channel
.sink17_data (rsp_demux_017_src0_data), // .data
.sink17_startofpacket (rsp_demux_017_src0_startofpacket), // .startofpacket
.sink17_endofpacket (rsp_demux_017_src0_endofpacket), // .endofpacket
.sink18_ready (rsp_demux_018_src0_ready), // sink18.ready
.sink18_valid (rsp_demux_018_src0_valid), // .valid
.sink18_channel (rsp_demux_018_src0_channel), // .channel
.sink18_data (rsp_demux_018_src0_data), // .data
.sink18_startofpacket (rsp_demux_018_src0_startofpacket), // .startofpacket
.sink18_endofpacket (rsp_demux_018_src0_endofpacket), // .endofpacket
.sink19_ready (rsp_demux_019_src0_ready), // sink19.ready
.sink19_valid (rsp_demux_019_src0_valid), // .valid
.sink19_channel (rsp_demux_019_src0_channel), // .channel
.sink19_data (rsp_demux_019_src0_data), // .data
.sink19_startofpacket (rsp_demux_019_src0_startofpacket), // .startofpacket
.sink19_endofpacket (rsp_demux_019_src0_endofpacket), // .endofpacket
.sink20_ready (rsp_demux_020_src0_ready), // sink20.ready
.sink20_valid (rsp_demux_020_src0_valid), // .valid
.sink20_channel (rsp_demux_020_src0_channel), // .channel
.sink20_data (rsp_demux_020_src0_data), // .data
.sink20_startofpacket (rsp_demux_020_src0_startofpacket), // .startofpacket
.sink20_endofpacket (rsp_demux_020_src0_endofpacket), // .endofpacket
.sink21_ready (rsp_demux_021_src0_ready), // sink21.ready
.sink21_valid (rsp_demux_021_src0_valid), // .valid
.sink21_channel (rsp_demux_021_src0_channel), // .channel
.sink21_data (rsp_demux_021_src0_data), // .data
.sink21_startofpacket (rsp_demux_021_src0_startofpacket), // .startofpacket
.sink21_endofpacket (rsp_demux_021_src0_endofpacket), // .endofpacket
.sink22_ready (rsp_demux_022_src0_ready), // sink22.ready
.sink22_valid (rsp_demux_022_src0_valid), // .valid
.sink22_channel (rsp_demux_022_src0_channel), // .channel
.sink22_data (rsp_demux_022_src0_data), // .data
.sink22_startofpacket (rsp_demux_022_src0_startofpacket), // .startofpacket
.sink22_endofpacket (rsp_demux_022_src0_endofpacket), // .endofpacket
.sink23_ready (rsp_demux_023_src0_ready), // sink23.ready
.sink23_valid (rsp_demux_023_src0_valid), // .valid
.sink23_channel (rsp_demux_023_src0_channel), // .channel
.sink23_data (rsp_demux_023_src0_data), // .data
.sink23_startofpacket (rsp_demux_023_src0_startofpacket), // .startofpacket
.sink23_endofpacket (rsp_demux_023_src0_endofpacket), // .endofpacket
.sink24_ready (rsp_demux_024_src0_ready), // sink24.ready
.sink24_valid (rsp_demux_024_src0_valid), // .valid
.sink24_channel (rsp_demux_024_src0_channel), // .channel
.sink24_data (rsp_demux_024_src0_data), // .data
.sink24_startofpacket (rsp_demux_024_src0_startofpacket), // .startofpacket
.sink24_endofpacket (rsp_demux_024_src0_endofpacket), // .endofpacket
.sink25_ready (rsp_demux_025_src0_ready), // sink25.ready
.sink25_valid (rsp_demux_025_src0_valid), // .valid
.sink25_channel (rsp_demux_025_src0_channel), // .channel
.sink25_data (rsp_demux_025_src0_data), // .data
.sink25_startofpacket (rsp_demux_025_src0_startofpacket), // .startofpacket
.sink25_endofpacket (rsp_demux_025_src0_endofpacket), // .endofpacket
.sink26_ready (rsp_demux_026_src0_ready), // sink26.ready
.sink26_valid (rsp_demux_026_src0_valid), // .valid
.sink26_channel (rsp_demux_026_src0_channel), // .channel
.sink26_data (rsp_demux_026_src0_data), // .data
.sink26_startofpacket (rsp_demux_026_src0_startofpacket), // .startofpacket
.sink26_endofpacket (rsp_demux_026_src0_endofpacket), // .endofpacket
.sink27_ready (rsp_demux_027_src0_ready), // sink27.ready
.sink27_valid (rsp_demux_027_src0_valid), // .valid
.sink27_channel (rsp_demux_027_src0_channel), // .channel
.sink27_data (rsp_demux_027_src0_data), // .data
.sink27_startofpacket (rsp_demux_027_src0_startofpacket), // .startofpacket
.sink27_endofpacket (rsp_demux_027_src0_endofpacket), // .endofpacket
.sink28_ready (rsp_demux_028_src0_ready), // sink28.ready
.sink28_valid (rsp_demux_028_src0_valid), // .valid
.sink28_channel (rsp_demux_028_src0_channel), // .channel
.sink28_data (rsp_demux_028_src0_data), // .data
.sink28_startofpacket (rsp_demux_028_src0_startofpacket), // .startofpacket
.sink28_endofpacket (rsp_demux_028_src0_endofpacket), // .endofpacket
.sink29_ready (rsp_demux_029_src0_ready), // sink29.ready
.sink29_valid (rsp_demux_029_src0_valid), // .valid
.sink29_channel (rsp_demux_029_src0_channel), // .channel
.sink29_data (rsp_demux_029_src0_data), // .data
.sink29_startofpacket (rsp_demux_029_src0_startofpacket), // .startofpacket
.sink29_endofpacket (rsp_demux_029_src0_endofpacket), // .endofpacket
.sink30_ready (rsp_demux_030_src0_ready), // sink30.ready
.sink30_valid (rsp_demux_030_src0_valid), // .valid
.sink30_channel (rsp_demux_030_src0_channel), // .channel
.sink30_data (rsp_demux_030_src0_data), // .data
.sink30_startofpacket (rsp_demux_030_src0_startofpacket), // .startofpacket
.sink30_endofpacket (rsp_demux_030_src0_endofpacket), // .endofpacket
.sink31_ready (rsp_demux_031_src0_ready), // sink31.ready
.sink31_valid (rsp_demux_031_src0_valid), // .valid
.sink31_channel (rsp_demux_031_src0_channel), // .channel
.sink31_data (rsp_demux_031_src0_data), // .data
.sink31_startofpacket (rsp_demux_031_src0_startofpacket), // .startofpacket
.sink31_endofpacket (rsp_demux_031_src0_endofpacket) // .endofpacket
);
nios_system_mm_interconnect_0_rsp_mux_001 rsp_mux_001 (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (rsp_mux_001_src_ready), // src.ready
.src_valid (rsp_mux_001_src_valid), // .valid
.src_data (rsp_mux_001_src_data), // .data
.src_channel (rsp_mux_001_src_channel), // .channel
.src_startofpacket (rsp_mux_001_src_startofpacket), // .startofpacket
.src_endofpacket (rsp_mux_001_src_endofpacket), // .endofpacket
.sink0_ready (rsp_demux_001_src1_ready), // sink0.ready
.sink0_valid (rsp_demux_001_src1_valid), // .valid
.sink0_channel (rsp_demux_001_src1_channel), // .channel
.sink0_data (rsp_demux_001_src1_data), // .data
.sink0_startofpacket (rsp_demux_001_src1_startofpacket), // .startofpacket
.sink0_endofpacket (rsp_demux_001_src1_endofpacket), // .endofpacket
.sink1_ready (rsp_demux_002_src1_ready), // sink1.ready
.sink1_valid (rsp_demux_002_src1_valid), // .valid
.sink1_channel (rsp_demux_002_src1_channel), // .channel
.sink1_data (rsp_demux_002_src1_data), // .data
.sink1_startofpacket (rsp_demux_002_src1_startofpacket), // .startofpacket
.sink1_endofpacket (rsp_demux_002_src1_endofpacket) // .endofpacket
);
endmodule
|
module txstr #(
parameter BAUDRATE = `B115200
)(
input wire clk, //-- System clock
input wire rstn, //-- Reset (active low)
output wire tx //-- Serial data output
);
//-- Serial Unit instantation
uart_tx #(
.BAUDRATE(BAUDRATE) //-- Set the baudrate
) TX0 (
.clk(clk),
.rstn(rstn),
.data(data),
.start(start),
.tx(tx),
.ready(ready)
);
//-- Connecting wires
wire ready;
reg start = 0;
reg [7:0] data;
//-- Multiplexer with the 8-character string to transmit
always @*
case (char_count)
8'd0: data <= "H";
8'd1: data <= "e";
8'd2: data <= "l";
8'd3: data <= "l";
8'd4: data <= "o";
8'd5: data <= "!";
8'd6: data <= ".";
8'd7: data <= ".";
default: data <= ".";
endcase
//-- Characters counter
//-- It only counts when the cena control signal is enabled
reg [2:0] char_count;
reg cena; //-- Counter enable
always @(posedge clk)
if (!rstn)
char_count = 0;
else if (cena)
char_count = char_count + 1;
//--------------------- CONTROLLER
localparam INI = 0;
localparam TXCAR = 1;
localparam NEXTCAR = 2;
localparam STOP = 3;
//-- fsm state
reg [1:0] state;
reg [1:0] next_state;
//-- Transition between states
always @(posedge clk) begin
if (!rstn)
state <= INI;
else
state <= next_state;
end
//-- Control signal generation and next states
always @(*) begin
next_state = state;
start = 0;
cena = 0;
case (state)
//-- Initial state. Start the trasmission
INI: begin
start = 1;
next_state = TXCAR;
end
//-- Wait until one car is transmitted
TXCAR: begin
if (ready)
next_state = NEXTCAR;
end
//-- Increment the character counter
//-- Finish when it is the last character
NEXTCAR: begin
cena = 1;
if (char_count == 7)
next_state = STOP;
else
next_state = INI;
end
endcase
end
endmodule
|
module idec (
inst,
aluasel,
alubsel,
aluop,
wwe,
fwe,
zwe,
cwe,
bdpol,
option,
tris
);
input [11:0] inst;
output [1:0] aluasel;
output [1:0] alubsel;
output [3:0] aluop;
output wwe;
output fwe;
output zwe;
output cwe;
output bdpol;
output option;
output tris;
reg [14:0] decodes;
// For reference, the ALU Op codes are:
//
// ADD 0000
// SUB 1000
// AND 0001
// OR 0010
// XOR 0011
// COM 0100
// ROR 0101
// ROL 0110
// SWAP 0111
assign { aluasel, // Select source for ALU A input. 00=W, 01=SBUS, 10=K, 11=BD
alubsel, // Select source for ALU B input. 00=W, 01=SBUS, 10=K, 11="1"
aluop, // ALU Operation (see comments above for these codes)
wwe, // W register Write Enable
fwe, // File Register Write Enable
zwe, // Status register Z bit update
cwe, // Status register Z bit update
bdpol, // Polarity on bit decode vector (0=no inversion, 1=invert)
tris, // Instruction is an TRIS instruction
option // Instruction is an OPTION instruction
} = decodes;
// This is a large combinatorial decoder.
// I use the casex statement.
always @(inst) begin
casex (inst) // synopsys parallel_case
// *** Byte-Oriented File Register Operations
//
// A A ALU W F Z C B T O
// L L O W W W W D R P
// U U P E E E E P I T
// A B O S
// L
12'b0000_0000_0000: decodes = 15'b00_00_0000_0_0_0_0_0_0_0; // NOP
12'b0000_001X_XXXX: decodes = 15'b00_00_0010_0_1_0_0_0_0_0; // MOVWF
12'b0000_0100_0000: decodes = 15'b00_00_0011_1_0_1_0_0_0_0; // CLRW
12'b0000_011X_XXXX: decodes = 15'b00_00_0011_0_1_1_0_0_0_0; // CLRF
12'b0000_100X_XXXX: decodes = 15'b01_00_1000_1_0_1_1_0_0_0; // SUBWF (d=0)
12'b0000_101X_XXXX: decodes = 15'b01_00_1000_0_1_1_1_0_0_0; // SUBWF (d=1)
12'b0000_110X_XXXX: decodes = 15'b01_11_1000_1_0_1_0_0_0_0; // DECF (d=0)
12'b0000_111X_XXXX: decodes = 15'b01_11_1000_0_1_1_0_0_0_0; // DECF (d=1)
12'b0001_000X_XXXX: decodes = 15'b00_01_0010_1_0_1_0_0_0_0; // IORWF (d=0)
12'b0001_001X_XXXX: decodes = 15'b00_01_0010_0_1_1_0_0_0_0; // IORWF (d=1)
12'b0001_010X_XXXX: decodes = 15'b00_01_0001_1_0_1_0_0_0_0; // ANDWF (d=0)
12'b0001_011X_XXXX: decodes = 15'b00_01_0001_0_1_1_0_0_0_0; // ANDWF (d=1)
12'b0001_100X_XXXX: decodes = 15'b00_01_0011_1_0_1_0_0_0_0; // XORWF (d=0)
12'b0001_101X_XXXX: decodes = 15'b00_01_0011_0_1_1_0_0_0_0; // XORWF (d=1)
12'b0001_110X_XXXX: decodes = 15'b00_01_0000_1_0_1_1_0_0_0; // ADDWF (d=0)
12'b0001_111X_XXXX: decodes = 15'b00_01_0000_0_1_1_1_0_0_0; // ADDWF (d=1)
12'b0010_000X_XXXX: decodes = 15'b01_01_0010_1_0_1_0_0_0_0; // MOVF (d=0)
12'b0010_001X_XXXX: decodes = 15'b01_01_0010_0_1_1_0_0_0_0; // MOVF (d=1)
12'b0010_010X_XXXX: decodes = 15'b01_01_0100_1_0_1_0_0_0_0; // COMF (d=0)
12'b0010_011X_XXXX: decodes = 15'b01_01_0100_0_1_1_0_0_0_0; // COMF (d=1)
12'b0010_100X_XXXX: decodes = 15'b01_11_0000_1_0_1_0_0_0_0; // INCF (d=0)
12'b0010_101X_XXXX: decodes = 15'b01_11_0000_0_1_1_0_0_0_0; // INCF (d=1)
12'b0010_110X_XXXX: decodes = 15'b01_11_1000_1_0_0_0_0_0_0; // DECFSZ(d=0)
12'b0010_111X_XXXX: decodes = 15'b01_11_1000_0_1_0_0_0_0_0; // DECFSZ(d=1)
12'b0011_000X_XXXX: decodes = 15'b01_01_0101_1_0_0_1_0_0_0; // RRF (d=0)
12'b0011_001X_XXXX: decodes = 15'b01_01_0101_0_1_0_1_0_0_0; // RRF (d=1)
12'b0011_010X_XXXX: decodes = 15'b01_01_0110_1_0_0_1_0_0_0; // RLF (d=0)
12'b0011_011X_XXXX: decodes = 15'b01_01_0110_0_1_0_1_0_0_0; // RLF (d=1)
12'b0011_100X_XXXX: decodes = 15'b01_01_0111_1_0_0_0_0_0_0; // SWAPF (d=0)
12'b0011_101X_XXXX: decodes = 15'b01_01_0111_0_1_0_0_0_0_0; // SWAPF (d=1)
12'b0011_110X_XXXX: decodes = 15'b01_11_0000_1_0_0_0_0_0_0; // INCFSZ(d=0)
12'b0011_111X_XXXX: decodes = 15'b01_11_0000_0_1_0_0_0_0_0; // INCFSZ(d=1)
// *** Bit-Oriented File Register Operations
//
// A A ALU W F Z C B T O
// L L O W W W W D R P
// U U P E E E E P I T
// A B O S
// L
12'b0100_XXXX_XXXX: decodes = 15'b11_01_0001_0_1_0_0_1_0_0; // BCF
12'b0101_XXXX_XXXX: decodes = 15'b11_01_0010_0_1_0_0_0_0_0; // BSF
12'b0110_XXXX_XXXX: decodes = 15'b11_01_0001_0_0_0_0_0_0_0; // BTFSC
12'b0111_XXXX_XXXX: decodes = 15'b11_01_0001_0_0_0_0_0_0_0; // BTFSS
// *** Literal and Control Operations
//
// A A ALU W F Z C B T O
// L L O W W W W D R P
// U U P E E E E P I T
// A B O S
// L
12'b0000_0000_0010: decodes = 15'b00_00_0010_0_1_0_0_0_0_1; // OPTION
12'b0000_0000_0011: decodes = 15'b00_00_0000_0_0_0_0_0_0_0; // SLEEP
12'b0000_0000_0100: decodes = 15'b00_00_0000_0_0_0_0_0_0_0; // CLRWDT
12'b0000_0000_0101: decodes = 15'b00_00_0000_0_1_0_0_0_1_0; // TRIS 5
12'b0000_0000_0110: decodes = 15'b00_00_0010_0_1_0_0_0_1_0; // TRIS 6
12'b0000_0000_0111: decodes = 15'b00_00_0010_0_1_0_0_0_1_0; // TRIS 7
//
// A A ALU W F Z C B T O
// L L O W W W W D R P
// U U P E E E E P I T
// A B O S
// L
12'b1000_XXXX_XXXX: decodes = 15'b10_10_0010_1_0_0_0_0_0_0; // RETLW
12'b1001_XXXX_XXXX: decodes = 15'b10_10_0010_0_0_0_0_0_0_0; // CALL
12'b101X_XXXX_XXXX: decodes = 15'b10_10_0010_0_0_0_0_0_0_0; // GOTO
12'b1100_XXXX_XXXX: decodes = 15'b10_10_0010_1_0_0_0_0_0_0; // MOVLW
12'b1101_XXXX_XXXX: decodes = 15'b00_10_0010_1_0_1_0_0_0_0; // IORLW
12'b1110_XXXX_XXXX: decodes = 15'b00_10_0001_1_0_1_0_0_0_0; // ANDLW
12'b1111_XXXX_XXXX: decodes = 15'b00_10_0011_1_0_1_0_0_0_0; // XORLW
default:
decodes = 15'b00_00_0000_0_0_0_0_0_0_0;
endcase
end
endmodule
|
module bw_io_ddr_pad_txrx_zctl(/*AUTOARG*/
// Outputs
out,
// Inouts
pad,
// Inputs
vrefcode, vdd_h, cbu, cbd, data, oe, odt_enable
);
// INPUTS
input [7:0] vrefcode; // impedence control bits
input odt_enable; // ODT control
input vdd_h; // IO power
input [8:1] cbu; // Impedence Control bits for Pullup driver
input [8:1] cbd; // Impedence Control bits for Pulldn driver
input data; // Data input to Driver
input oe; // Output tristate control (active high)
// INOUTS
inout pad; // Output/Input pad of Driver/Receiver
// OUTPUTS
output out; // Receiver output
//////////////////////////
// CODE
//////////////////////////
assign pad = oe ? data : 1'bz;
assign out = pad;
// FIX FOR MAKING INPUT DQS WEAK 0/1 WHEN BUS IS IN "Z" STATE.
//wire pad_in;
//pulldown p1(pad_in); // pulldown by default if no driver
//assign out = (pad === 1'bz) ? pad_in : pad;
endmodule
|
module sky130_fd_sc_ms__o221ai (
Y ,
A1,
A2,
B1,
B2,
C1
);
output Y ;
input A1;
input A2;
input B1;
input B2;
input C1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
|
module sky130_fd_sc_hs__tapvgnd2 (
VGND,
VPWR
);
// Module ports
input VGND;
input VPWR;
// No contents.
endmodule
|
module sky130_fd_sc_ls__a21boi (
Y ,
A1 ,
A2 ,
B1_N
);
// Module ports
output Y ;
input A1 ;
input A2 ;
input B1_N;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire b ;
wire and0_out ;
wire nor0_out_Y;
// Name Output Other arguments
not not0 (b , B1_N );
and and0 (and0_out , A1, A2 );
nor nor0 (nor0_out_Y, b, and0_out );
buf buf0 (Y , nor0_out_Y );
endmodule
|
module sky130_fd_sc_ms__o211a (
X ,
A1,
A2,
B1,
C1
);
// Module ports
output X ;
input A1;
input A2;
input B1;
input C1;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire or0_out ;
wire and0_out_X;
// Name Output Other arguments
or or0 (or0_out , A2, A1 );
and and0 (and0_out_X, or0_out, B1, C1);
buf buf0 (X , and0_out_X );
endmodule
|
module GEN( input wire CLK_IN,
input wire RST_X_IN,
output wire CLK_OUT,
output wire VGA_CLK_OUT,
output wire RST_X_OUT
);
wire LOCKED, VLOCKED, CLK_IBUF;
wire RST_X_BUF;
clk_wiz_0 clkgen(CLK_IN, CLK_OUT, VGA_CLK_OUT, LOCKED);
RSTGEN rstgen(CLK_OUT, (RST_X_IN & LOCKED), RST_X_OUT);
endmodule
|
module RSTGEN(CLK, RST_X_I, RST_X_O);
input CLK, RST_X_I;
output RST_X_O;
reg [7:0] cnt;
assign RST_X_O = cnt[7];
always @(posedge CLK or negedge RST_X_I) begin
if (!RST_X_I) cnt <= 0;
else if (~RST_X_O) cnt <= (cnt + 1'b1);
end
endmodule
|
module uart_receiver_test;
localparam TicksPerClock = 2;
localparam ClocksPerBaud = 8;
integer i;
reg clk;
reg rst_n;
reg rx;
reg rx_byte_done;
wire [7:0] rx_byte;
wire rx_byte_valid;
wire clear_to_send;
integer stop_bit_begin_time;
integer stop_bit_done = 0;
uart_receiver #(
.ClocksPerBaud(ClocksPerBaud)
) receiver (
.clk (clk),
.rst_n (rst_n),
.rx (rx),
.clear_to_send_out(clear_to_send),
.rx_byte_out (rx_byte),
.rx_byte_valid_out(rx_byte_valid),
.rx_byte_done (rx_byte_done)
);
initial begin
#1 clk = 0;
forever #1 clk = !clk;
end
`include "xls/uncore_rtl/ice40/xls_assertions.inc"
// Make sure we finish after some reasonable amount of time.
initial begin
#1024 begin
$display("ERROR: timeout, simulation ran too long");
$finish;
end
end
initial begin
//$dumpfile("/tmp/uart_receiver_test.vcd");
//$dumpvars(0, clk, rst_n, rx_byte, rx_byte_valid, rx, rx_byte_done,
// clear_to_send, receiver.state, receiver.state_next,
// receiver.rx_countdown, receiver.samples, receiver.sample_count,
// receiver.data_bitno, receiver.rx_byte_valid_next);
$display("Starting...\n");
$monitor("%t rx: %b rx_byte_valid: %b", $time, rx, rx_byte_valid);
rst_n <= 0;
rx <= 1;
rx_byte_done <= 0;
// Come out of reset after a few cycles.
#4 rst_n <= 1;
#TicksPerClock;
xls_assert(receiver.state, 0, "receiver state should be idle");
xls_assert(clear_to_send, 1, "should be clear to send when idle");
// Start bit.
rx <= 0;
#(TicksPerClock*ClocksPerBaud);
// Send toggling bits, starting with 'b1 to make 'h55.
for (i = 0; i < 8; i = i + 1) begin
xls_assert(clear_to_send, 0, "transmitting from testbench");
rx <= (i % 2 == 0);
#(TicksPerClock*ClocksPerBaud);
end
stop_bit_begin_time = $time;
// Stop bit / idle.
rx <= 1;
#TicksPerClock;
// Byte should be valid before we receive the stop bit.
#1;
xls_assert(1, rx_byte_valid, "valid during stop bit");
xls_assert_int_eq(8'h55, rx_byte, "byte payload during stop bit");
`ifdef TEST_SINGLE_BYTE
// Wait to transition back to idle.
wait (receiver.state == 'd0);
// Byte should be valid and the same after we're idle.
xls_assert(1, rx_byte_valid, "valid when idle");
xls_assert_int_eq(8'h55, rx_byte, "byte payload when idle");
xls_assert(clear_to_send, 0, "byte is valid, should not be clear to send");
`else
// Discard the byte immediately now that we've checked it.
rx_byte_done <= 1;
// Check that subsequently we say it's ok to send.
#TicksPerClock;
xls_assert(1, clear_to_send, "clear to send once byte is done");
// Only note that the RX byte is done for a single cycle.
rx_byte_done <= 0;
// Wait until we've sent the stop bit for a full baud of time.
#(TicksPerClock*ClocksPerBaud-($time-stop_bit_begin_time));
$display("Starting second byte.");
// Then send a start bit and the next byte.
rx <= 0;
#(ClocksPerBaud*TicksPerClock);
for (i = 0; i < 8; i = i + 1) begin
rx <= (8'h01 >> i) & 1'b1;
#(ClocksPerBaud*TicksPerClock);
end
// Stop bit / idle.
rx <= 1;
#TicksPerClock;
// Byte should be valid before we receive the stop bit.
#1;
xls_assert(1, rx_byte_valid, "valid during stop bit");
xls_assert_int_eq(8'h01, rx_byte, "byte payload during stop bit");
`endif
// Pad a little time before end of sim.
#(8*TicksPerClock);
$finish;
end
endmodule
|
module Mem_B(
clka,
wea,
addra,
dina,
douta
);
input clka;
input [0 : 0] wea;
input [9 : 0] addra;
input [31 : 0] dina;
output [31 : 0] douta;
// synthesis translate_off
BLK_MEM_GEN_V7_3 #(
.C_ADDRA_WIDTH(10),
.C_ADDRB_WIDTH(10),
.C_ALGORITHM(1),
.C_AXI_ID_WIDTH(4),
.C_AXI_SLAVE_TYPE(0),
.C_AXI_TYPE(1),
.C_BYTE_SIZE(9),
.C_COMMON_CLK(0),
.C_DEFAULT_DATA("0"),
.C_DISABLE_WARN_BHV_COLL(0),
.C_DISABLE_WARN_BHV_RANGE(0),
.C_ENABLE_32BIT_ADDRESS(0),
.C_FAMILY("spartan6"),
.C_HAS_AXI_ID(0),
.C_HAS_ENA(0),
.C_HAS_ENB(0),
.C_HAS_INJECTERR(0),
.C_HAS_MEM_OUTPUT_REGS_A(0),
.C_HAS_MEM_OUTPUT_REGS_B(0),
.C_HAS_MUX_OUTPUT_REGS_A(0),
.C_HAS_MUX_OUTPUT_REGS_B(0),
.C_HAS_REGCEA(0),
.C_HAS_REGCEB(0),
.C_HAS_RSTA(0),
.C_HAS_RSTB(0),
.C_HAS_SOFTECC_INPUT_REGS_A(0),
.C_HAS_SOFTECC_OUTPUT_REGS_B(0),
.C_INIT_FILE("BlankString"),
.C_INIT_FILE_NAME("Mem_B.mif"),
.C_INITA_VAL("0"),
.C_INITB_VAL("0"),
.C_INTERFACE_TYPE(0),
.C_LOAD_INIT_FILE(1),
.C_MEM_TYPE(0),
.C_MUX_PIPELINE_STAGES(0),
.C_PRIM_TYPE(1),
.C_READ_DEPTH_A(1024),
.C_READ_DEPTH_B(1024),
.C_READ_WIDTH_A(32),
.C_READ_WIDTH_B(32),
.C_RST_PRIORITY_A("CE"),
.C_RST_PRIORITY_B("CE"),
.C_RST_TYPE("SYNC"),
.C_RSTRAM_A(0),
.C_RSTRAM_B(0),
.C_SIM_COLLISION_CHECK("ALL"),
.C_USE_BRAM_BLOCK(0),
.C_USE_BYTE_WEA(0),
.C_USE_BYTE_WEB(0),
.C_USE_DEFAULT_DATA(0),
.C_USE_ECC(0),
.C_USE_SOFTECC(0),
.C_WEA_WIDTH(1),
.C_WEB_WIDTH(1),
.C_WRITE_DEPTH_A(1024),
.C_WRITE_DEPTH_B(1024),
.C_WRITE_MODE_A("WRITE_FIRST"),
.C_WRITE_MODE_B("WRITE_FIRST"),
.C_WRITE_WIDTH_A(32),
.C_WRITE_WIDTH_B(32),
.C_XDEVICEFAMILY("spartan6")
)
inst (
.CLKA(clka),
.WEA(wea),
.ADDRA(addra),
.DINA(dina),
.DOUTA(douta),
.RSTA(),
.ENA(),
.REGCEA(),
.CLKB(),
.RSTB(),
.ENB(),
.REGCEB(),
.WEB(),
.ADDRB(),
.DINB(),
.DOUTB(),
.INJECTSBITERR(),
.INJECTDBITERR(),
.SBITERR(),
.DBITERR(),
.RDADDRECC(),
.S_ACLK(),
.S_ARESETN(),
.S_AXI_AWID(),
.S_AXI_AWADDR(),
.S_AXI_AWLEN(),
.S_AXI_AWSIZE(),
.S_AXI_AWBURST(),
.S_AXI_AWVALID(),
.S_AXI_AWREADY(),
.S_AXI_WDATA(),
.S_AXI_WSTRB(),
.S_AXI_WLAST(),
.S_AXI_WVALID(),
.S_AXI_WREADY(),
.S_AXI_BID(),
.S_AXI_BRESP(),
.S_AXI_BVALID(),
.S_AXI_BREADY(),
.S_AXI_ARID(),
.S_AXI_ARADDR(),
.S_AXI_ARLEN(),
.S_AXI_ARSIZE(),
.S_AXI_ARBURST(),
.S_AXI_ARVALID(),
.S_AXI_ARREADY(),
.S_AXI_RID(),
.S_AXI_RDATA(),
.S_AXI_RRESP(),
.S_AXI_RLAST(),
.S_AXI_RVALID(),
.S_AXI_RREADY(),
.S_AXI_INJECTSBITERR(),
.S_AXI_INJECTDBITERR(),
.S_AXI_SBITERR(),
.S_AXI_DBITERR(),
.S_AXI_RDADDRECC()
);
// synthesis translate_on
endmodule
|
module e203_subsys_mems(
input mem_icb_cmd_valid,
output mem_icb_cmd_ready,
input [`E203_ADDR_SIZE-1:0] mem_icb_cmd_addr,
input mem_icb_cmd_read,
input [`E203_XLEN-1:0] mem_icb_cmd_wdata,
input [`E203_XLEN/8-1:0] mem_icb_cmd_wmask,
//
output mem_icb_rsp_valid,
input mem_icb_rsp_ready,
output mem_icb_rsp_err,
output [`E203_XLEN-1:0] mem_icb_rsp_rdata,
//////////////////////////////////////////////////////////
output sysmem_icb_cmd_valid,
input sysmem_icb_cmd_ready,
output [`E203_ADDR_SIZE-1:0] sysmem_icb_cmd_addr,
output sysmem_icb_cmd_read,
output [`E203_XLEN-1:0] sysmem_icb_cmd_wdata,
output [`E203_XLEN/8-1:0] sysmem_icb_cmd_wmask,
//
input sysmem_icb_rsp_valid,
output sysmem_icb_rsp_ready,
input sysmem_icb_rsp_err,
input [`E203_XLEN-1:0] sysmem_icb_rsp_rdata,
//////////////////////////////////////////////////////////
output qspi0_ro_icb_cmd_valid,
input qspi0_ro_icb_cmd_ready,
output [`E203_ADDR_SIZE-1:0] qspi0_ro_icb_cmd_addr,
output qspi0_ro_icb_cmd_read,
output [`E203_XLEN-1:0] qspi0_ro_icb_cmd_wdata,
//
input qspi0_ro_icb_rsp_valid,
output qspi0_ro_icb_rsp_ready,
input qspi0_ro_icb_rsp_err,
input [`E203_XLEN-1:0] qspi0_ro_icb_rsp_rdata,
//////////////////////////////////////////////////////////
output otp_ro_icb_cmd_valid,
input otp_ro_icb_cmd_ready,
output [`E203_ADDR_SIZE-1:0] otp_ro_icb_cmd_addr,
output otp_ro_icb_cmd_read,
output [`E203_XLEN-1:0] otp_ro_icb_cmd_wdata,
//
input otp_ro_icb_rsp_valid,
output otp_ro_icb_rsp_ready,
input otp_ro_icb_rsp_err,
input [`E203_XLEN-1:0] otp_ro_icb_rsp_rdata,
//////////////////////////////////////////////////////////
output dm_icb_cmd_valid,
input dm_icb_cmd_ready,
output [`E203_ADDR_SIZE-1:0] dm_icb_cmd_addr,
output dm_icb_cmd_read,
output [`E203_XLEN-1:0] dm_icb_cmd_wdata,
//
input dm_icb_rsp_valid,
output dm_icb_rsp_ready,
input [`E203_XLEN-1:0] dm_icb_rsp_rdata,
input clk,
input bus_rst_n,
input rst_n
);
wire mrom_icb_cmd_valid;
wire mrom_icb_cmd_ready;
wire [`E203_ADDR_SIZE-1:0] mrom_icb_cmd_addr;
wire mrom_icb_cmd_read;
wire mrom_icb_rsp_valid;
wire mrom_icb_rsp_ready;
wire mrom_icb_rsp_err ;
wire [`E203_XLEN-1:0] mrom_icb_rsp_rdata;
wire expl_axi_icb_cmd_valid;
wire expl_axi_icb_cmd_ready;
wire [32-1:0] expl_axi_icb_cmd_addr;
wire expl_axi_icb_cmd_read;
wire [32-1:0] expl_axi_icb_cmd_wdata;
wire [4 -1:0] expl_axi_icb_cmd_wmask;
wire expl_axi_icb_rsp_valid;
wire expl_axi_icb_rsp_ready;
wire [32-1:0] expl_axi_icb_rsp_rdata;
wire expl_axi_icb_rsp_err;
localparam MROM_AW = 12 ;
localparam MROM_DP = 1024;
// There are several slaves for Mem bus, including:
// * DM : 0x0000 0000 -- 0x0000 0FFF
// * MROM : 0x0000 1000 -- 0x0000 1FFF
// * OTP-RO : 0x0002 0000 -- 0x0003 FFFF
// * QSPI0-RO : 0x2000 0000 -- 0x3FFF FFFF
// * SysMem : 0x8000 0000 -- 0xFFFF FFFF
sirv_icb1to8_bus # (
.ICB_FIFO_DP (2),// We add a ping-pong buffer here to cut down the timing path
.ICB_FIFO_CUT_READY (1),// We configure it to cut down the back-pressure ready signal
.AW (32),
.DW (`E203_XLEN),
.SPLT_FIFO_OUTS_NUM (1),// The Mem only allow 1 oustanding
.SPLT_FIFO_CUT_READY (1),// The Mem always cut ready
// * DM : 0x0000 0000 -- 0x0000 0FFF
.O0_BASE_ADDR (32'h0000_0000),
.O0_BASE_REGION_LSB (12),
// * MROM : 0x0000 1000 -- 0x0000 1FFF
.O1_BASE_ADDR (32'h0000_1000),
.O1_BASE_REGION_LSB (12),
// * OTP-RO : 0x0002 0000 -- 0x0003 FFFF
.O2_BASE_ADDR (32'h0002_0000),
.O2_BASE_REGION_LSB (17),
// * QSPI0-RO : 0x2000 0000 -- 0x3FFF FFFF
.O3_BASE_ADDR (32'h2000_0000),
.O3_BASE_REGION_LSB (29),
// * SysMem : 0x8000 0000 -- 0xFFFF FFFF
// Actually since the 0xFxxx xxxx have been occupied by FIO,
// sysmem have no chance to access it
.O4_BASE_ADDR (32'h8000_0000),
.O4_BASE_REGION_LSB (31),
// * Here is an example AXI Peripheral
.O5_BASE_ADDR (32'h4000_0000),
.O5_BASE_REGION_LSB (28),
// Not used
.O6_BASE_ADDR (32'h0000_0000),
.O6_BASE_REGION_LSB (0),
// Not used
.O7_BASE_ADDR (32'h0000_0000),
.O7_BASE_REGION_LSB (0)
)u_sirv_mem_fab(
.i_icb_cmd_valid (mem_icb_cmd_valid),
.i_icb_cmd_ready (mem_icb_cmd_ready),
.i_icb_cmd_addr (mem_icb_cmd_addr ),
.i_icb_cmd_read (mem_icb_cmd_read ),
.i_icb_cmd_wdata (mem_icb_cmd_wdata),
.i_icb_cmd_wmask (mem_icb_cmd_wmask),
.i_icb_cmd_lock (1'b0 ),
.i_icb_cmd_excl (1'b0 ),
.i_icb_cmd_size (2'b0 ),
.i_icb_cmd_burst (2'b0),
.i_icb_cmd_beat (2'b0 ),
.i_icb_rsp_valid (mem_icb_rsp_valid),
.i_icb_rsp_ready (mem_icb_rsp_ready),
.i_icb_rsp_err (mem_icb_rsp_err ),
.i_icb_rsp_excl_ok(),
.i_icb_rsp_rdata (mem_icb_rsp_rdata),
// * DM
.o0_icb_enable (1'b1),
.o0_icb_cmd_valid (dm_icb_cmd_valid),
.o0_icb_cmd_ready (dm_icb_cmd_ready),
.o0_icb_cmd_addr (dm_icb_cmd_addr ),
.o0_icb_cmd_read (dm_icb_cmd_read ),
.o0_icb_cmd_wdata (dm_icb_cmd_wdata),
.o0_icb_cmd_wmask (),
.o0_icb_cmd_lock (),
.o0_icb_cmd_excl (),
.o0_icb_cmd_size (),
.o0_icb_cmd_burst (),
.o0_icb_cmd_beat (),
.o0_icb_rsp_valid (dm_icb_rsp_valid),
.o0_icb_rsp_ready (dm_icb_rsp_ready),
.o0_icb_rsp_err (1'b0),
.o0_icb_rsp_excl_ok(1'b0),
.o0_icb_rsp_rdata (dm_icb_rsp_rdata),
// * MROM
.o1_icb_enable (1'b1),
.o1_icb_cmd_valid (mrom_icb_cmd_valid),
.o1_icb_cmd_ready (mrom_icb_cmd_ready),
.o1_icb_cmd_addr (mrom_icb_cmd_addr ),
.o1_icb_cmd_read (mrom_icb_cmd_read ),
.o1_icb_cmd_wdata (),
.o1_icb_cmd_wmask (),
.o1_icb_cmd_lock (),
.o1_icb_cmd_excl (),
.o1_icb_cmd_size (),
.o1_icb_cmd_burst (),
.o1_icb_cmd_beat (),
.o1_icb_rsp_valid (mrom_icb_rsp_valid),
.o1_icb_rsp_ready (mrom_icb_rsp_ready),
.o1_icb_rsp_err (mrom_icb_rsp_err),
.o1_icb_rsp_excl_ok(1'b0 ),
.o1_icb_rsp_rdata (mrom_icb_rsp_rdata),
// * OTP-RO
.o2_icb_enable (1'b1),
.o2_icb_cmd_valid (otp_ro_icb_cmd_valid),
.o2_icb_cmd_ready (otp_ro_icb_cmd_ready),
.o2_icb_cmd_addr (otp_ro_icb_cmd_addr ),
.o2_icb_cmd_read (otp_ro_icb_cmd_read ),
.o2_icb_cmd_wdata (otp_ro_icb_cmd_wdata),
.o2_icb_cmd_wmask (),
.o2_icb_cmd_lock (),
.o2_icb_cmd_excl (),
.o2_icb_cmd_size (),
.o2_icb_cmd_burst (),
.o2_icb_cmd_beat (),
.o2_icb_rsp_valid (otp_ro_icb_rsp_valid),
.o2_icb_rsp_ready (otp_ro_icb_rsp_ready),
.o2_icb_rsp_err (otp_ro_icb_rsp_err),
.o2_icb_rsp_excl_ok(1'b0 ),
.o2_icb_rsp_rdata (otp_ro_icb_rsp_rdata),
// * QSPI0-RO
.o3_icb_enable (1'b1),
.o3_icb_cmd_valid (qspi0_ro_icb_cmd_valid),
.o3_icb_cmd_ready (qspi0_ro_icb_cmd_ready),
.o3_icb_cmd_addr (qspi0_ro_icb_cmd_addr ),
.o3_icb_cmd_read (qspi0_ro_icb_cmd_read ),
.o3_icb_cmd_wdata (qspi0_ro_icb_cmd_wdata),
.o3_icb_cmd_wmask (),
.o3_icb_cmd_lock (),
.o3_icb_cmd_excl (),
.o3_icb_cmd_size (),
.o3_icb_cmd_burst (),
.o3_icb_cmd_beat (),
.o3_icb_rsp_valid (qspi0_ro_icb_rsp_valid),
.o3_icb_rsp_ready (qspi0_ro_icb_rsp_ready),
.o3_icb_rsp_err (qspi0_ro_icb_rsp_err),
.o3_icb_rsp_excl_ok(1'b0 ),
.o3_icb_rsp_rdata (qspi0_ro_icb_rsp_rdata),
// * SysMem
.o4_icb_enable (1'b1),
.o4_icb_cmd_valid (sysmem_icb_cmd_valid),
.o4_icb_cmd_ready (sysmem_icb_cmd_ready),
.o4_icb_cmd_addr (sysmem_icb_cmd_addr ),
.o4_icb_cmd_read (sysmem_icb_cmd_read ),
.o4_icb_cmd_wdata (sysmem_icb_cmd_wdata),
.o4_icb_cmd_wmask (sysmem_icb_cmd_wmask),
.o4_icb_cmd_lock (),
.o4_icb_cmd_excl (),
.o4_icb_cmd_size (),
.o4_icb_cmd_burst (),
.o4_icb_cmd_beat (),
.o4_icb_rsp_valid (sysmem_icb_rsp_valid),
.o4_icb_rsp_ready (sysmem_icb_rsp_ready),
.o4_icb_rsp_err (sysmem_icb_rsp_err ),
.o4_icb_rsp_excl_ok(1'b0),
.o4_icb_rsp_rdata (sysmem_icb_rsp_rdata),
// * Example AXI
.o5_icb_enable (1'b1),
.o5_icb_cmd_valid (expl_axi_icb_cmd_valid),
.o5_icb_cmd_ready (expl_axi_icb_cmd_ready),
.o5_icb_cmd_addr (expl_axi_icb_cmd_addr ),
.o5_icb_cmd_read (expl_axi_icb_cmd_read ),
.o5_icb_cmd_wdata (expl_axi_icb_cmd_wdata),
.o5_icb_cmd_wmask (expl_axi_icb_cmd_wmask),
.o5_icb_cmd_lock (),
.o5_icb_cmd_excl (),
.o5_icb_cmd_size (),
.o5_icb_cmd_burst (),
.o5_icb_cmd_beat (),
.o5_icb_rsp_valid (expl_axi_icb_rsp_valid),
.o5_icb_rsp_ready (expl_axi_icb_rsp_ready),
.o5_icb_rsp_err (expl_axi_icb_rsp_err),
.o5_icb_rsp_excl_ok(1'b0 ),
.o5_icb_rsp_rdata (expl_axi_icb_rsp_rdata),
// * Not used
.o6_icb_enable (1'b0),
.o6_icb_cmd_valid (),
.o6_icb_cmd_ready (1'b0),
.o6_icb_cmd_addr (),
.o6_icb_cmd_read (),
.o6_icb_cmd_wdata (),
.o6_icb_cmd_wmask (),
.o6_icb_cmd_lock (),
.o6_icb_cmd_excl (),
.o6_icb_cmd_size (),
.o6_icb_cmd_burst (),
.o6_icb_cmd_beat (),
.o6_icb_rsp_valid (1'b0),
.o6_icb_rsp_ready (),
.o6_icb_rsp_err (1'b0 ),
.o6_icb_rsp_excl_ok(1'b0 ),
.o6_icb_rsp_rdata (`E203_XLEN'b0),
// * Not used
.o7_icb_enable (1'b0),
.o7_icb_cmd_valid (),
.o7_icb_cmd_ready (1'b0),
.o7_icb_cmd_addr (),
.o7_icb_cmd_read (),
.o7_icb_cmd_wdata (),
.o7_icb_cmd_wmask (),
.o7_icb_cmd_lock (),
.o7_icb_cmd_excl (),
.o7_icb_cmd_size (),
.o7_icb_cmd_burst (),
.o7_icb_cmd_beat (),
.o7_icb_rsp_valid (1'b0),
.o7_icb_rsp_ready (),
.o7_icb_rsp_err (1'b0 ),
.o7_icb_rsp_excl_ok(1'b0 ),
.o7_icb_rsp_rdata (`E203_XLEN'b0),
.clk (clk ),
.rst_n (bus_rst_n)
);
sirv_mrom_top #(
.AW(MROM_AW),
.DW(32),
.DP(MROM_DP)
)u_sirv_mrom_top(
.rom_icb_cmd_valid (mrom_icb_cmd_valid),
.rom_icb_cmd_ready (mrom_icb_cmd_ready),
.rom_icb_cmd_addr (mrom_icb_cmd_addr [MROM_AW-1:0]),
.rom_icb_cmd_read (mrom_icb_cmd_read ),
.rom_icb_rsp_valid (mrom_icb_rsp_valid),
.rom_icb_rsp_ready (mrom_icb_rsp_ready),
.rom_icb_rsp_err (mrom_icb_rsp_err ),
.rom_icb_rsp_rdata (mrom_icb_rsp_rdata),
.clk (clk ),
.rst_n (rst_n)
);
// * Here is an example AXI Peripheral
wire expl_axi_arvalid;
wire expl_axi_arready;
wire [`E203_ADDR_SIZE-1:0] expl_axi_araddr;
wire [3:0] expl_axi_arcache;
wire [2:0] expl_axi_arprot;
wire [1:0] expl_axi_arlock;
wire [1:0] expl_axi_arburst;
wire [3:0] expl_axi_arlen;
wire [2:0] expl_axi_arsize;
wire expl_axi_awvalid;
wire expl_axi_awready;
wire [`E203_ADDR_SIZE-1:0] expl_axi_awaddr;
wire [3:0] expl_axi_awcache;
wire [2:0] expl_axi_awprot;
wire [1:0] expl_axi_awlock;
wire [1:0] expl_axi_awburst;
wire [3:0] expl_axi_awlen;
wire [2:0] expl_axi_awsize;
wire expl_axi_rvalid;
wire expl_axi_rready;
wire [`E203_XLEN-1:0] expl_axi_rdata;
wire [1:0] expl_axi_rresp;
wire expl_axi_rlast;
wire expl_axi_wvalid;
wire expl_axi_wready;
wire [`E203_XLEN-1:0] expl_axi_wdata;
wire [(`E203_XLEN/8)-1:0] expl_axi_wstrb;
wire expl_axi_wlast;
wire expl_axi_bvalid;
wire expl_axi_bready;
wire [1:0] expl_axi_bresp;
sirv_gnrl_icb2axi # (
.AXI_FIFO_DP (2), // We just add ping-pong buffer here to avoid any potential timing loops
// User can change it to 0 if dont care
.AXI_FIFO_CUT_READY (1), // This is to cut the back-pressure signal if you set as 1
.AW (32),
.FIFO_OUTS_NUM (4),// We only allow 4 oustandings at most for mem, user can configure it to any value
.FIFO_CUT_READY(1),
.DW (`E203_XLEN)
) u_expl_axi_icb2axi(
.i_icb_cmd_valid (expl_axi_icb_cmd_valid),
.i_icb_cmd_ready (expl_axi_icb_cmd_ready),
.i_icb_cmd_addr (expl_axi_icb_cmd_addr ),
.i_icb_cmd_read (expl_axi_icb_cmd_read ),
.i_icb_cmd_wdata (expl_axi_icb_cmd_wdata),
.i_icb_cmd_wmask (expl_axi_icb_cmd_wmask),
.i_icb_cmd_size (),
.i_icb_rsp_valid (expl_axi_icb_rsp_valid),
.i_icb_rsp_ready (expl_axi_icb_rsp_ready),
.i_icb_rsp_rdata (expl_axi_icb_rsp_rdata),
.i_icb_rsp_err (expl_axi_icb_rsp_err),
.o_axi_arvalid (expl_axi_arvalid),
.o_axi_arready (expl_axi_arready),
.o_axi_araddr (expl_axi_araddr ),
.o_axi_arcache (expl_axi_arcache),
.o_axi_arprot (expl_axi_arprot ),
.o_axi_arlock (expl_axi_arlock ),
.o_axi_arburst (expl_axi_arburst),
.o_axi_arlen (expl_axi_arlen ),
.o_axi_arsize (expl_axi_arsize ),
.o_axi_awvalid (expl_axi_awvalid),
.o_axi_awready (expl_axi_awready),
.o_axi_awaddr (expl_axi_awaddr ),
.o_axi_awcache (expl_axi_awcache),
.o_axi_awprot (expl_axi_awprot ),
.o_axi_awlock (expl_axi_awlock ),
.o_axi_awburst (expl_axi_awburst),
.o_axi_awlen (expl_axi_awlen ),
.o_axi_awsize (expl_axi_awsize ),
.o_axi_rvalid (expl_axi_rvalid ),
.o_axi_rready (expl_axi_rready ),
.o_axi_rdata (expl_axi_rdata ),
.o_axi_rresp (expl_axi_rresp ),
.o_axi_rlast (expl_axi_rlast ),
.o_axi_wvalid (expl_axi_wvalid ),
.o_axi_wready (expl_axi_wready ),
.o_axi_wdata (expl_axi_wdata ),
.o_axi_wstrb (expl_axi_wstrb ),
.o_axi_wlast (expl_axi_wlast ),
.o_axi_bvalid (expl_axi_bvalid ),
.o_axi_bready (expl_axi_bready ),
.o_axi_bresp (expl_axi_bresp ),
.clk (clk ),
.rst_n (bus_rst_n)
);
sirv_expl_axi_slv # (
.AW (32),
.DW (`E203_XLEN)
) u_perips_expl_axi_slv (
.axi_arvalid (expl_axi_arvalid),
.axi_arready (expl_axi_arready),
.axi_araddr (expl_axi_araddr ),
.axi_arcache (expl_axi_arcache),
.axi_arprot (expl_axi_arprot ),
.axi_arlock (expl_axi_arlock ),
.axi_arburst (expl_axi_arburst),
.axi_arlen (expl_axi_arlen ),
.axi_arsize (expl_axi_arsize ),
.axi_awvalid (expl_axi_awvalid),
.axi_awready (expl_axi_awready),
.axi_awaddr (expl_axi_awaddr ),
.axi_awcache (expl_axi_awcache),
.axi_awprot (expl_axi_awprot ),
.axi_awlock (expl_axi_awlock ),
.axi_awburst (expl_axi_awburst),
.axi_awlen (expl_axi_awlen ),
.axi_awsize (expl_axi_awsize ),
.axi_rvalid (expl_axi_rvalid ),
.axi_rready (expl_axi_rready ),
.axi_rdata (expl_axi_rdata ),
.axi_rresp (expl_axi_rresp ),
.axi_rlast (expl_axi_rlast ),
.axi_wvalid (expl_axi_wvalid ),
.axi_wready (expl_axi_wready ),
.axi_wdata (expl_axi_wdata ),
.axi_wstrb (expl_axi_wstrb ),
.axi_wlast (expl_axi_wlast ),
.axi_bvalid (expl_axi_bvalid ),
.axi_bready (expl_axi_bready ),
.axi_bresp (expl_axi_bresp ),
.clk (clk ),
.rst_n (rst_n)
);
endmodule
|
module sky130_fd_sc_ls__dfstp (
Q ,
CLK ,
D ,
SET_B
);
output Q ;
input CLK ;
input D ;
input SET_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
|
module pixel_ram
#(parameter DATA_WIDTH=24, parameter ADDR_WIDTH=9)
(
input [(DATA_WIDTH-1):0] data_a,
input [(ADDR_WIDTH-1):0] addr_a, addr_b,
input we_a, clk_a, clk_b,
output reg [(DATA_WIDTH-1):0] q_b
);
// Declare the RAM variable
reg [DATA_WIDTH-1:0] ram[2**ADDR_WIDTH-1:0];
always @ (posedge clk_a)
begin
if (we_a)
ram[addr_a] <= data_a;
end
always @ (posedge clk_b)
begin
q_b <= ram[addr_b];
end
endmodule
|
module RPCv3RouterReceiver
#(
parameter OUT_DATA_WIDTH = 32,
parameter IN_DATA_WIDTH = 16
)
(
//Interface clock
input wire clk,
//Network interface, inbound side
input wire rpc_rx_en,
input wire[IN_DATA_WIDTH-1:0] rpc_rx_data,
output wire rpc_rx_ready,
//Router interface, outbound side
input wire rpc_fab_rx_space_available,
output wire rpc_fab_rx_packet_start,
output wire rpc_fab_rx_data_valid,
output wire[OUT_DATA_WIDTH-1:0] rpc_fab_rx_data,
output wire rpc_fab_rx_packet_done
);
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// Create the right receiver depending on link widths
localparam EXPANDING = (IN_DATA_WIDTH < OUT_DATA_WIDTH);
localparam COLLAPSING = (IN_DATA_WIDTH > OUT_DATA_WIDTH);
localparam BUFFERING = (IN_DATA_WIDTH == OUT_DATA_WIDTH);
generate
if(EXPANDING) begin
RPCv3RouterReceiver_expanding #(
.IN_DATA_WIDTH(IN_DATA_WIDTH),
.OUT_DATA_WIDTH(OUT_DATA_WIDTH)
) rxvr (
.clk(clk),
.rpc_rx_en(rpc_rx_en),
.rpc_rx_data(rpc_rx_data),
.rpc_rx_ready(rpc_rx_ready),
.rpc_fab_rx_space_available(rpc_fab_rx_space_available),
.rpc_fab_rx_packet_start(rpc_fab_rx_packet_start),
.rpc_fab_rx_data_valid(rpc_fab_rx_data_valid),
.rpc_fab_rx_data(rpc_fab_rx_data),
.rpc_fab_rx_packet_done(rpc_fab_rx_packet_done)
);
end
else if(COLLAPSING) begin
RPCv3RouterReceiver_collapsing #(
.IN_DATA_WIDTH(IN_DATA_WIDTH),
.OUT_DATA_WIDTH(OUT_DATA_WIDTH)
) rxvr (
.clk(clk),
.rpc_rx_en(rpc_rx_en),
.rpc_rx_data(rpc_rx_data),
.rpc_rx_ready(rpc_rx_ready),
.rpc_fab_rx_space_available(rpc_fab_rx_space_available),
.rpc_fab_rx_packet_start(rpc_fab_rx_packet_start),
.rpc_fab_rx_data_valid(rpc_fab_rx_data_valid),
.rpc_fab_rx_data(rpc_fab_rx_data),
.rpc_fab_rx_packet_done(rpc_fab_rx_packet_done)
);
end
else begin
RPCv3RouterReceiver_buffering #(
.IN_DATA_WIDTH(IN_DATA_WIDTH),
.OUT_DATA_WIDTH(OUT_DATA_WIDTH)
) rxvr (
.clk(clk),
.rpc_rx_en(rpc_rx_en),
.rpc_rx_data(rpc_rx_data),
.rpc_rx_ready(rpc_rx_ready),
.rpc_fab_rx_space_available(rpc_fab_rx_space_available),
.rpc_fab_rx_packet_start(rpc_fab_rx_packet_start),
.rpc_fab_rx_data_valid(rpc_fab_rx_data_valid),
.rpc_fab_rx_data(rpc_fab_rx_data),
.rpc_fab_rx_packet_done(rpc_fab_rx_packet_done)
);
end
endgenerate
endmodule
|
module RegistroWithMuxInput#(parameter Width = 4)
(CLK,EnableRegisterIn,reset,SELCoeffX,SELCoeffY,Coeff00,Coeff01,Coeff02,Coeff03,Coeff04,Coeff05,Coeff06,Coeff07,Coeff08,Coeff09,
Coeff10,Coeff11,Coeff12,Coeff13,Coeff14,Coeff15,Coeff16,Coeff17,Coeff18,Coeff19,OffsetIn,OutCoeffX,OutCoeffY,OffsetOut);
input signed [Width-1:0] Coeff00,Coeff01,Coeff02,Coeff03,Coeff04,Coeff05,Coeff06,Coeff07,Coeff08,
Coeff09,Coeff10,Coeff11,Coeff12,Coeff13,Coeff14,Coeff15,Coeff16,Coeff17,Coeff18,Coeff19,OffsetIn;
input CLK,EnableRegisterIn,reset;
input [3:0] SELCoeffX,SELCoeffY;
output reg signed [Width-1:0] OutCoeffX = 0;
output reg signed [Width-1:0] OutCoeffY = 0; //OffsetOut
output signed [Width-1:0] OffsetOut;
reg signed [Width-1:0] AuxCoeff00,AuxCoeff01,AuxCoeff02,AuxCoeff03,AuxCoeff04,AuxCoeff05,AuxCoeff06,
AuxCoeff07,AuxCoeff08,AuxCoeff09,AuxCoeff10,AuxCoeff11,AuxCoeff12,AuxCoeff13,AuxCoeff14,AuxCoeff15,AuxCoeff16,
AuxCoeff17,AuxCoeff18,AuxCoeff19,AuxCoeff20;
always @(posedge CLK)
if (reset) begin
AuxCoeff00 <= 0;
AuxCoeff01 <= 0;
AuxCoeff02 <= 0;
AuxCoeff03 <= 0;
AuxCoeff04 <= 0;
AuxCoeff05 <= 0;
AuxCoeff06 <= 0;
AuxCoeff07 <= 0;
AuxCoeff08 <= 0;
AuxCoeff09 <= 0;
AuxCoeff10 <= 0;
AuxCoeff11 <= 0;
AuxCoeff12 <= 0;
AuxCoeff13 <= 0;
AuxCoeff14 <= 0;
AuxCoeff15 <= 0;
AuxCoeff16 <= 0;
AuxCoeff17 <= 0;
AuxCoeff18 <= 0;
AuxCoeff19 <= 0;
AuxCoeff20 <= 0;
end else if (EnableRegisterIn) begin
AuxCoeff00 <= Coeff00;
AuxCoeff01 <= Coeff01;
AuxCoeff02 <= Coeff02;
AuxCoeff03 <= Coeff03;
AuxCoeff04 <= Coeff04;
AuxCoeff05 <= Coeff05;
AuxCoeff06 <= Coeff06;
AuxCoeff07 <= Coeff07;
AuxCoeff08 <= Coeff08;
AuxCoeff09 <= Coeff09;
AuxCoeff10 <= Coeff10;
AuxCoeff11 <= Coeff11;
AuxCoeff12 <= Coeff12;
AuxCoeff13 <= Coeff13;
AuxCoeff14 <= Coeff14;
AuxCoeff15 <= Coeff15;
AuxCoeff16 <= Coeff16;
AuxCoeff17 <= Coeff17;
AuxCoeff18 <= Coeff18;
AuxCoeff19 <= Coeff19;
AuxCoeff20 <= OffsetIn;
end
assign OffsetOut = AuxCoeff20;
always @(SELCoeffX, AuxCoeff00,AuxCoeff01,AuxCoeff02,AuxCoeff03,AuxCoeff04,AuxCoeff05,AuxCoeff06,
AuxCoeff07,AuxCoeff08,AuxCoeff09)
case (SELCoeffX)
5'd00: OutCoeffX <= AuxCoeff00;
5'd01: OutCoeffX <= AuxCoeff01;
5'd02: OutCoeffX <= AuxCoeff02;
5'd03: OutCoeffX <= AuxCoeff03;
5'd04: OutCoeffX <= AuxCoeff04;
5'd05: OutCoeffX <= AuxCoeff05;
5'd06: OutCoeffX <= AuxCoeff06;
5'd07: OutCoeffX <= AuxCoeff07;
5'd08: OutCoeffX <= AuxCoeff08;
5'd09: OutCoeffX <= AuxCoeff09;
default : OutCoeffX <= 0;
endcase
always @(SELCoeffY,AuxCoeff10,AuxCoeff11,AuxCoeff12,AuxCoeff13,AuxCoeff14,AuxCoeff15,AuxCoeff16,
AuxCoeff17,AuxCoeff18,AuxCoeff19)
case (SELCoeffY)
5'd00: OutCoeffY <= AuxCoeff10;
5'd01: OutCoeffY <= AuxCoeff11;
5'd02: OutCoeffY <= AuxCoeff12;
5'd03: OutCoeffY <= AuxCoeff13;
5'd04: OutCoeffY <= AuxCoeff14;
5'd05: OutCoeffY <= AuxCoeff15;
5'd06: OutCoeffY <= AuxCoeff16;
5'd07: OutCoeffY <= AuxCoeff17;
5'd08: OutCoeffY <= AuxCoeff18;
5'd09: OutCoeffY <= AuxCoeff19;
default : OutCoeffY <= 0;
endcase
endmodule
|
module sky130_fd_sc_hd__lpflow_inputiso0n (
X ,
A ,
SLEEP_B,
VPWR ,
VGND ,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input SLEEP_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
// Local signals
wire and0_out_X;
// Name Output Other arguments
and and0 (and0_out_X, A, SLEEP_B );
sky130_fd_sc_hd__udp_pwrgood$l_pp$PG pwrgood0 (X , and0_out_X, VPWR, VGND);
endmodule
|
module ascii (
input clk,
input scan_ready,
input [7:0] scan_code,
output [7:0] ascii
);
reg [7:0] r_ascii;
reg [1:0] scan_ready_edge_detect = 2'b00;
assign ascii = r_ascii;
//reg keyup = 0;
reg extended = 0;
reg shift = 0;
reg [1:0] caps = 2'b00;
wire caps_lock;
reg [7:0] code;
reg [7:0] key_code [2:0];
reg [1:0] key_mem_index = 2'b00;
reg [1:0] key_current_index = 2'b00;
reg key_clear = 0;
reg [7:0] current_code;
reg [7:0] break_code;
reg [7:0] state_code;
reg [2:0] state_reg = 2'b00;
// state machine parameters
parameter st_idle = 3'b000;
parameter st_code_1 = 3'b001;
parameter st_code_2 = 3'b010;
parameter st_code_3 = 3'b011;
parameter st_break = 3'b100;
parameter st_extended = 3'b101;
parameter st_ready = 3'b110;
assign caps_lock = caps[0]; // odd number of presses
// posedge of the ps2 clock
always @(posedge clk) begin
scan_ready_edge_detect <= {scan_ready_edge_detect[0], scan_ready};
end
always @(posedge clk) begin
case (state_reg)
st_idle:
begin
if (scan_ready_edge_detect == 2'b01) begin
current_code <= scan_code;
state_reg <= st_code_1;
end
end
st_code_1:
begin
state_code <= current_code;
state_reg <= st_code_2;
end
st_code_2:
begin
// break code
if (state_code == 8'hf0) begin
state_reg <= st_break;
end else begin
state_reg <= st_code_3;
end
end
st_code_3:
begin
state_reg <= st_ready;
end
st_break:
begin
// key up
code <= 8'h00;
if (scan_ready_edge_detect == 2'b01) begin
state_reg <= st_idle;
break_code <= scan_code;
end
end
st_extended:
begin
end
st_ready:
begin
code <= state_code;
state_reg <= st_idle;
end
default:
begin
end
endcase
end
// Caps lock
always @(posedge clk) begin
if (scan_ready_edge_detect == 2'b01 && code == 8'h58) begin
caps <= caps + 2'b1;
end
end
// LEFT SHIFT || RIGHT SHIFT
always @(posedge clk) begin
if (code == 8'h12 || code == 8'h59) begin
shift <= 1;
end else if (break_code == 8'h12 || break_code == 8'h59) begin
shift <= 0;
end
end
/*
// Store char codes & remove then when their break code arrives.
always @(posedge clk) begin
if (scan_ready_edge_detect == 2'b01) begin
// LEFT SHIFT || RIGHT SHIFT
if (scan_code == 8'h12 || scan_code == 8'h59) begin
if (key_clear) begin
shift <= 0;
end else begin
shift <= 1;
end
end else if (scan_code == 8'hf0) begin // break code
// Clear the next scan code from the key_code memory.
key_clear <= 1'b1;
end else if (key_clear) begin
// Find the key code in the memory & clear it.
key_clear <= 1'b0;
extended <= 1'b0;
if (key_code[0] == scan_code) begin
key_code[0] <= 8'h00;
// if (key_current_index == 2'b0) begin
// key_current_index <= 2'b10;
// end else begin
// key_current_index <= key_current_index - 1'b1;
// end
end
else if (key_code[1] == scan_code) begin
key_code[1] <= 8'h00;
// if (key_current_index == 2'b0) begin
// key_current_index <= 2'b10;
// end else begin
// key_current_index <= key_current_index - 1'b1;
// end
end
else if (key_code[2] == scan_code) begin
key_code[2] <= 8'h00;
// if (key_current_index == 2'b0) begin
// key_current_index <= 2'b10;
// end else begin
// key_current_index <= key_current_index - 1'b1;
// end
end
end else begin
// Store the key code.
key_current_index <= key_mem_index;
if (key_mem_index == 2'b10) begin
key_mem_index <= 2'b00;
end else begin
key_mem_index <= key_mem_index + 2'b01;
end
key_code[key_mem_index] <= scan_code;
end
if (scan_code == 8'he0) begin
// extended make codes
extended <= 1'b1;
end
// Caps lock
if (code == 8'h58) begin
caps = caps + 2'b01;
end
end
end
always @(posedge clk) begin
code <= key_code[key_current_index];
end
*/
always @(posedge clk) begin
if (extended) begin
//extended <= 0;
case (code)
// nand2tetris special codes
8'h6b: r_ascii <= 8'd130; // L ARROW
8'h75: r_ascii <= 8'd131; // UP ARROW
8'h74: r_ascii <= 8'd132; // R ARROW
8'h72: r_ascii <= 8'd133; // DOWN ARROW
8'h6c: r_ascii <= 8'd134; // HOME
8'h69: r_ascii <= 8'd135; // END
8'h7d: r_ascii <= 8'd136; // PAGE UP
8'h7a: r_ascii <= 8'd137; // PAGE DOWN
8'h70: r_ascii <= 8'd138; // INSERT
8'h71: r_ascii <= 8'd139; // DELETE
default: r_ascii <= 8'd0; // null
endcase
end else
if ((shift && !caps_lock) || (caps_lock && !shift)) begin
case (code)
8'h29: r_ascii <= 8'd32; // [space]
8'h16: r_ascii <= 8'd33; // !
8'h52: r_ascii <= 8'd34; // "
8'h26: r_ascii <= 8'd35; // #
8'h25: r_ascii <= 8'd36; // $
8'h2e: r_ascii <= 8'd37; // %
8'h3d: r_ascii <= 8'd38; // &
8'h46: r_ascii <= 8'd40; // (
8'h45: r_ascii <= 8'd41; // )
8'h3e: r_ascii <= 8'd42; // *
8'h55: r_ascii <= 8'd43; // +
8'h4c: r_ascii <= 8'd58; // :
8'h41: r_ascii <= 8'd60; // <
8'h49: r_ascii <= 8'd62; // >
8'h4a: r_ascii <= 8'd63; // ?
8'h1e: r_ascii <= 8'd64; // @
8'h1c: r_ascii <= 8'd65; // A
8'h32: r_ascii <= 8'd66; // B
8'h21: r_ascii <= 8'd67; // C
8'h23: r_ascii <= 8'd68; // D
8'h24: r_ascii <= 8'd69; // E
8'h2b: r_ascii <= 8'd70; // F
8'h34: r_ascii <= 8'd71; // G
8'h33: r_ascii <= 8'd72; // H
8'h43: r_ascii <= 8'd73; // I
8'h3b: r_ascii <= 8'd74; // J
8'h42: r_ascii <= 8'd75; // K
8'h4b: r_ascii <= 8'd76; // L
8'h3a: r_ascii <= 8'd77; // M
8'h31: r_ascii <= 8'd78; // N
8'h44: r_ascii <= 8'd79; // O
8'h4d: r_ascii <= 8'd80; // P
8'h15: r_ascii <= 8'd81; // Q
8'h2d: r_ascii <= 8'd82; // R
8'h1b: r_ascii <= 8'd83; // S
8'h2c: r_ascii <= 8'd84; // T
8'h3c: r_ascii <= 8'd85; // U
8'h2a: r_ascii <= 8'd86; // V
8'h1d: r_ascii <= 8'd87; // W
8'h22: r_ascii <= 8'd88; // X
8'h35: r_ascii <= 8'd89; // Y
8'h1a: r_ascii <= 8'd90; // Z
8'h36: r_ascii <= 8'd94; // ^
8'h4e: r_ascii <= 8'd95; // _
8'h54: r_ascii <= 8'd123; // {
8'h5d: r_ascii <= 8'd124; // |
8'h5b: r_ascii <= 8'd125; // }
8'h0e: r_ascii <= 8'd126; // ~
default: r_ascii <= 8'd0; // null
endcase
end else begin
case (code)
8'h0d: r_ascii <= 8'd9; // [tab]
//8'h14: r_ascii <= L CTRL
//8'h11: r_ascii <= L ALT
//8'h7e: r_ascii <= SCROLL
//8'h77: r_ascii <= NUM
8'h29: r_ascii <= 8'd32; // [space]
8'h52: r_ascii <= 8'd39; // '
8'h7c: r_ascii <= 8'd42; // KP *
8'h79: r_ascii <= 8'd43; // KP +
8'h41: r_ascii <= 8'd44; // ,
8'h49: r_ascii <= 8'd46; // .
8'h71: r_ascii <= 8'd46; // KP .
8'h4e: r_ascii <= 8'd45; // -
8'h7b: r_ascii <= 8'd45; // KP -
8'h4a: r_ascii <= 8'd47; // /
8'h45: r_ascii <= 8'd48; // 0
8'h70: r_ascii <= 8'd48; // KP 0
8'h16: r_ascii <= 8'd49; // 1
8'h69: r_ascii <= 8'd49; // KP 1
8'h1e: r_ascii <= 8'd50; // 2
8'h72: r_ascii <= 8'd50; // KP 2
8'h26: r_ascii <= 8'd51; // 3
8'h7a: r_ascii <= 8'd51; // KP 3
8'h25: r_ascii <= 8'd52; // 4
8'h6b: r_ascii <= 8'd52; // KP 4
8'h2e: r_ascii <= 8'd53; // 5
8'h73: r_ascii <= 8'd53; // KP 5
8'h36: r_ascii <= 8'd54; // 6
8'h74: r_ascii <= 8'd54; // KP 6
8'h3d: r_ascii <= 8'd55; // 7
8'h6c: r_ascii <= 8'd55; // KP 7
8'h3e: r_ascii <= 8'd56; // 8
8'h75: r_ascii <= 8'd56; // KP 8
8'h46: r_ascii <= 8'd57; // 9
8'h7d: r_ascii <= 8'd57; // KP 9
8'h4c: r_ascii <= 8'd59; // ;
8'h55: r_ascii <= 8'd61; // =
8'h54: r_ascii <= 8'd91; // [
8'h5d: r_ascii <= 8'd92; // \
8'h5b: r_ascii <= 8'd93; // ]
8'h0e: r_ascii <= 8'd96; // `
8'h1c: r_ascii <= 8'd97; // a
8'h32: r_ascii <= 8'd98; // b
8'h21: r_ascii <= 8'd99; // c
8'h23: r_ascii <= 8'd100; // d
8'h24: r_ascii <= 8'd101; // e
8'h2b: r_ascii <= 8'd102; // f
8'h34: r_ascii <= 8'd103; // g
8'h33: r_ascii <= 8'd104; // h
8'h43: r_ascii <= 8'd105; // i
8'h3b: r_ascii <= 8'd106; // j
8'h42: r_ascii <= 8'd107; // k
8'h4b: r_ascii <= 8'd108; // l
8'h3a: r_ascii <= 8'd109; // m
8'h31: r_ascii <= 8'd110; // n
8'h44: r_ascii <= 8'd111; // o
8'h4d: r_ascii <= 8'd112; // p
8'h15: r_ascii <= 8'd113; // q
8'h2d: r_ascii <= 8'd114; // r
8'h1b: r_ascii <= 8'd115; // s
8'h2c: r_ascii <= 8'd116; // t
8'h3c: r_ascii <= 8'd117; // u
8'h2a: r_ascii <= 8'd118; // v
8'h1d: r_ascii <= 8'd119; // w
8'h22: r_ascii <= 8'd120; // x
8'h35: r_ascii <= 8'd121; // y
8'h1a: r_ascii <= 8'd122; // z
// nand2tetris special codes
8'h5a: r_ascii <= 8'd128; // [enter]
8'h66: r_ascii <= 8'd129; // [back space]
8'h76: r_ascii <= 8'd140; // ESCAPE
8'h05: r_ascii <= 8'd141; // F1
8'h06: r_ascii <= 8'd142; // F2
8'h04: r_ascii <= 8'd143; // F3
8'h0c: r_ascii <= 8'd144; // F4
8'h03: r_ascii <= 8'd145; // F5
8'h0b: r_ascii <= 8'd146; // F6
8'h83: r_ascii <= 8'd147; // F7
8'h0a: r_ascii <= 8'd148; // F8
8'h01: r_ascii <= 8'd149; // F9
8'h09: r_ascii <= 8'd150; // F10
8'h78: r_ascii <= 8'd151; // F11
8'h07: r_ascii <= 8'd152; // F12
default: r_ascii <= 8'd0; // null
endcase
end
end
endmodule
|
module s27_path (
G1,
G2,
clk_net,
reset_net,
G3,
G0,
G17);
// Start PIs
input G1;
input G2;
input clk_net;
input reset_net;
input G3;
input G0;
// Start POs
output G17;
// Start wires
wire G1;
wire net_5;
wire net_15;
wire net_27;
wire G17;
wire reset_net;
wire net_14;
wire G3;
wire net_26;
wire clk_net;
wire net_13;
wire G2;
wire net_19;
wire net_3;
wire net_22;
wire net_16;
wire net_6;
wire net_24;
wire net_11;
wire net_1;
wire net_23;
wire net_18;
wire net_12;
wire net_2;
wire net_10;
wire net_8;
wire net_9;
wire net_25;
wire net_21;
wire net_7;
wire net_20;
wire G0;
wire net_4;
wire net_17;
// Start cells
CLKBUF_X2 inst_19 ( .A(net_17), .Z(net_18) );
DFFR_X2 inst_14 ( .RN(net_12), .D(net_10), .QN(net_3), .CK(net_27) );
INV_X1 inst_12 ( .A(net_16), .ZN(G17) );
INV_X4 inst_8 ( .ZN(net_5), .A(net_1) );
NOR2_X4 inst_2 ( .ZN(net_11), .A2(net_9), .A1(net_6) );
NOR2_X4 inst_1 ( .A1(net_14), .ZN(net_8), .A2(G3) );
CLKBUF_X2 inst_21 ( .A(net_19), .Z(net_20) );
CLKBUF_X2 inst_25 ( .A(net_23), .Z(net_24) );
NAND2_X2 inst_7 ( .ZN(net_7), .A1(net_4), .A2(net_3) );
CLKBUF_X2 inst_20 ( .A(net_18), .Z(net_19) );
INV_X1 inst_13 ( .ZN(net_12), .A(reset_net) );
CLKBUF_X2 inst_27 ( .A(net_25), .Z(net_26) );
CLKBUF_X2 inst_26 ( .A(net_17), .Z(net_25) );
NOR3_X4 inst_0 ( .ZN(net_16), .A1(net_11), .A3(net_8), .A2(net_5) );
CLKBUF_X2 inst_18 ( .A(clk_net), .Z(net_17) );
DFFR_X2 inst_15 ( .D(net_16), .RN(net_12), .QN(net_2), .CK(net_19) );
DFFR_X2 inst_16 ( .D(net_13), .RN(net_12), .QN(net_1), .CK(net_24) );
CLKBUF_X2 inst_24 ( .A(net_22), .Z(net_23) );
NOR2_X2 inst_3 ( .ZN(net_14), .A1(net_2), .A2(G0) );
NOR2_X2 inst_6 ( .A1(net_16), .A2(net_15), .ZN(net_13) );
INV_X4 inst_9 ( .ZN(net_9), .A(net_7) );
NOR2_X2 inst_5 ( .ZN(net_10), .A2(net_9), .A1(G2) );
INV_X2 inst_10 ( .ZN(net_4), .A(G1) );
NOR2_X2 inst_4 ( .ZN(net_6), .A1(net_2), .A2(G0) );
CLKBUF_X2 inst_23 ( .A(net_21), .Z(net_22) );
INV_X2 inst_11 ( .ZN(net_15), .A(G0) );
CLKBUF_X2 inst_28 ( .A(net_26), .Z(net_27) );
CLKBUF_X2 inst_22 ( .A(net_20), .Z(net_21) );
endmodule
|
module outputs)
wire elink0_cclk_n; // From elink0 of axi_elink.v
wire elink0_cclk_p; // From elink0 of axi_elink.v
wire elink0_chip_nreset; // From elink0 of axi_elink.v
wire [11:0] elink0_chipid; // From elink0 of axi_elink.v
wire [31:0] elink0_m_axi_araddr; // From elink0 of axi_elink.v
wire [1:0] elink0_m_axi_arburst; // From elink0 of axi_elink.v
wire [3:0] elink0_m_axi_arcache; // From elink0 of axi_elink.v
wire [M_IDW-1:0] elink0_m_axi_arid; // From elink0 of axi_elink.v
wire [7:0] elink0_m_axi_arlen; // From elink0 of axi_elink.v
wire elink0_m_axi_arlock; // From elink0 of axi_elink.v
wire [2:0] elink0_m_axi_arprot; // From elink0 of axi_elink.v
wire [3:0] elink0_m_axi_arqos; // From elink0 of axi_elink.v
wire elink0_m_axi_arready; // From axislave_stub of axislave_stub.v
wire [2:0] elink0_m_axi_arsize; // From elink0 of axi_elink.v
wire elink0_m_axi_arvalid; // From elink0 of axi_elink.v
wire [31:0] elink0_m_axi_awaddr; // From elink0 of axi_elink.v
wire [1:0] elink0_m_axi_awburst; // From elink0 of axi_elink.v
wire [3:0] elink0_m_axi_awcache; // From elink0 of axi_elink.v
wire [M_IDW-1:0] elink0_m_axi_awid; // From elink0 of axi_elink.v
wire [7:0] elink0_m_axi_awlen; // From elink0 of axi_elink.v
wire elink0_m_axi_awlock; // From elink0 of axi_elink.v
wire [2:0] elink0_m_axi_awprot; // From elink0 of axi_elink.v
wire [3:0] elink0_m_axi_awqos; // From elink0 of axi_elink.v
wire elink0_m_axi_awready; // From axislave_stub of axislave_stub.v
wire [2:0] elink0_m_axi_awsize; // From elink0 of axi_elink.v
wire elink0_m_axi_awvalid; // From elink0 of axi_elink.v
wire [S_IDW-1:0] elink0_m_axi_bid; // From axislave_stub of axislave_stub.v
wire elink0_m_axi_bready; // From elink0 of axi_elink.v
wire [1:0] elink0_m_axi_bresp; // From axislave_stub of axislave_stub.v
wire elink0_m_axi_bvalid; // From axislave_stub of axislave_stub.v
wire [31:0] elink0_m_axi_rdata; // From axislave_stub of axislave_stub.v
wire [S_IDW-1:0] elink0_m_axi_rid; // From axislave_stub of axislave_stub.v
wire elink0_m_axi_rlast; // From axislave_stub of axislave_stub.v
wire elink0_m_axi_rready; // From elink0 of axi_elink.v
wire [1:0] elink0_m_axi_rresp; // From axislave_stub of axislave_stub.v
wire elink0_m_axi_rvalid; // From axislave_stub of axislave_stub.v
wire [63:0] elink0_m_axi_wdata; // From elink0 of axi_elink.v
wire [M_IDW-1:0] elink0_m_axi_wid; // From elink0 of axi_elink.v
wire elink0_m_axi_wlast; // From elink0 of axi_elink.v
wire elink0_m_axi_wready; // From axislave_stub of axislave_stub.v
wire [7:0] elink0_m_axi_wstrb; // From elink0 of axi_elink.v
wire elink0_m_axi_wvalid; // From elink0 of axi_elink.v
wire elink0_mailbox_irq; // From elink0 of axi_elink.v
wire elink0_rxo_rd_wait_n; // From elink0 of axi_elink.v
wire elink0_rxo_rd_wait_p; // From elink0 of axi_elink.v
wire elink0_rxo_wr_wait_n; // From elink0 of axi_elink.v
wire elink0_rxo_wr_wait_p; // From elink0 of axi_elink.v
wire [7:0] elink0_txo_data_n; // From elink0 of axi_elink.v
wire [7:0] elink0_txo_data_p; // From elink0 of axi_elink.v
wire elink0_txo_frame_n; // From elink0 of axi_elink.v
wire elink0_txo_frame_p; // From elink0 of axi_elink.v
wire elink0_txo_lclk_n; // From elink0 of axi_elink.v
wire elink0_txo_lclk_p; // From elink0 of axi_elink.v
wire elink1_cclk_n; // From elink1 of axi_elink.v
wire elink1_cclk_p; // From elink1 of axi_elink.v
wire elink1_chip_nreset; // From elink1 of axi_elink.v
wire [11:0] elink1_chipid; // From elink1 of axi_elink.v
wire elink1_elink_active; // From elink1 of axi_elink.v
wire elink1_mailbox_irq; // From elink1 of axi_elink.v
wire elink1_rxo_rd_wait_n; // From elink1 of axi_elink.v
wire elink1_rxo_rd_wait_p; // From elink1 of axi_elink.v
wire elink1_rxo_wr_wait_n; // From elink1 of axi_elink.v
wire elink1_rxo_wr_wait_p; // From elink1 of axi_elink.v
wire [7:0] elink1_txo_data_n; // From elink1 of axi_elink.v
wire [7:0] elink1_txo_data_p; // From elink1 of axi_elink.v
wire elink1_txo_frame_n; // From elink1 of axi_elink.v
wire elink1_txo_frame_p; // From elink1 of axi_elink.v
wire elink1_txo_lclk_n; // From elink1 of axi_elink.v
wire elink1_txo_lclk_p; // From elink1 of axi_elink.v
wire [31:0] ext1_m_axi_araddr; // From emaxi1 of emaxi.v
wire [1:0] ext1_m_axi_arburst; // From emaxi1 of emaxi.v
wire [3:0] ext1_m_axi_arcache; // From emaxi1 of emaxi.v
wire [M_IDW-1:0] ext1_m_axi_arid; // From emaxi1 of emaxi.v
wire [7:0] ext1_m_axi_arlen; // From emaxi1 of emaxi.v
wire ext1_m_axi_arlock; // From emaxi1 of emaxi.v
wire [2:0] ext1_m_axi_arprot; // From emaxi1 of emaxi.v
wire [3:0] ext1_m_axi_arqos; // From emaxi1 of emaxi.v
wire ext1_m_axi_arready; // From elink1 of axi_elink.v
wire [2:0] ext1_m_axi_arsize; // From emaxi1 of emaxi.v
wire ext1_m_axi_arvalid; // From emaxi1 of emaxi.v
wire [31:0] ext1_m_axi_awaddr; // From emaxi1 of emaxi.v
wire [1:0] ext1_m_axi_awburst; // From emaxi1 of emaxi.v
wire [3:0] ext1_m_axi_awcache; // From emaxi1 of emaxi.v
wire [M_IDW-1:0] ext1_m_axi_awid; // From emaxi1 of emaxi.v
wire [7:0] ext1_m_axi_awlen; // From emaxi1 of emaxi.v
wire ext1_m_axi_awlock; // From emaxi1 of emaxi.v
wire [2:0] ext1_m_axi_awprot; // From emaxi1 of emaxi.v
wire [3:0] ext1_m_axi_awqos; // From emaxi1 of emaxi.v
wire ext1_m_axi_awready; // From elink1 of axi_elink.v
wire [2:0] ext1_m_axi_awsize; // From emaxi1 of emaxi.v
wire ext1_m_axi_awvalid; // From emaxi1 of emaxi.v
wire [S_IDW-1:0] ext1_m_axi_bid; // From elink1 of axi_elink.v
wire ext1_m_axi_bready; // From emaxi1 of emaxi.v
wire [1:0] ext1_m_axi_bresp; // From elink1 of axi_elink.v
wire ext1_m_axi_bvalid; // From elink1 of axi_elink.v
wire [31:0] ext1_m_axi_rdata; // From elink1 of axi_elink.v
wire [S_IDW-1:0] ext1_m_axi_rid; // From elink1 of axi_elink.v
wire ext1_m_axi_rlast; // From elink1 of axi_elink.v
wire ext1_m_axi_rready; // From emaxi1 of emaxi.v
wire [1:0] ext1_m_axi_rresp; // From elink1 of axi_elink.v
wire ext1_m_axi_rvalid; // From elink1 of axi_elink.v
wire [63:0] ext1_m_axi_wdata; // From emaxi1 of emaxi.v
wire [M_IDW-1:0] ext1_m_axi_wid; // From emaxi1 of emaxi.v
wire ext1_m_axi_wlast; // From emaxi1 of emaxi.v
wire ext1_m_axi_wready; // From elink1 of axi_elink.v
wire [7:0] ext1_m_axi_wstrb; // From emaxi1 of emaxi.v
wire ext1_m_axi_wvalid; // From emaxi1 of emaxi.v
wire [31:0] m_axi_araddr; // From emaxi0 of emaxi.v
wire [1:0] m_axi_arburst; // From emaxi0 of emaxi.v
wire [3:0] m_axi_arcache; // From emaxi0 of emaxi.v
wire [M_IDW-1:0] m_axi_arid; // From emaxi0 of emaxi.v
wire [7:0] m_axi_arlen; // From emaxi0 of emaxi.v
wire m_axi_arlock; // From emaxi0 of emaxi.v
wire [2:0] m_axi_arprot; // From emaxi0 of emaxi.v
wire [3:0] m_axi_arqos; // From emaxi0 of emaxi.v
wire m_axi_arready; // From elink0 of axi_elink.v
wire [2:0] m_axi_arsize; // From emaxi0 of emaxi.v
wire m_axi_arvalid; // From emaxi0 of emaxi.v
wire [31:0] m_axi_awaddr; // From emaxi0 of emaxi.v
wire [1:0] m_axi_awburst; // From emaxi0 of emaxi.v
wire [3:0] m_axi_awcache; // From emaxi0 of emaxi.v
wire [M_IDW-1:0] m_axi_awid; // From emaxi0 of emaxi.v
wire [7:0] m_axi_awlen; // From emaxi0 of emaxi.v
wire m_axi_awlock; // From emaxi0 of emaxi.v
wire [2:0] m_axi_awprot; // From emaxi0 of emaxi.v
wire [3:0] m_axi_awqos; // From emaxi0 of emaxi.v
wire m_axi_awready; // From elink0 of axi_elink.v
wire [2:0] m_axi_awsize; // From emaxi0 of emaxi.v
wire m_axi_awvalid; // From emaxi0 of emaxi.v
wire [S_IDW-1:0] m_axi_bid; // From elink0 of axi_elink.v
wire m_axi_bready; // From emaxi0 of emaxi.v
wire [1:0] m_axi_bresp; // From elink0 of axi_elink.v
wire m_axi_bvalid; // From elink0 of axi_elink.v
wire [31:0] m_axi_rdata; // From elink0 of axi_elink.v
wire [S_IDW-1:0] m_axi_rid; // From elink0 of axi_elink.v
wire m_axi_rlast; // From elink0 of axi_elink.v
wire m_axi_rready; // From emaxi0 of emaxi.v
wire [1:0] m_axi_rresp; // From elink0 of axi_elink.v
wire m_axi_rvalid; // From elink0 of axi_elink.v
wire [63:0] m_axi_wdata; // From emaxi0 of emaxi.v
wire [M_IDW-1:0] m_axi_wid; // From emaxi0 of emaxi.v
wire m_axi_wlast; // From emaxi0 of emaxi.v
wire m_axi_wready; // From elink0 of axi_elink.v
wire [7:0] m_axi_wstrb; // From emaxi0 of emaxi.v
wire m_axi_wvalid; // From emaxi0 of emaxi.v
wire [31:0] mem_m_axi_araddr; // From elink1 of axi_elink.v
wire [1:0] mem_m_axi_arburst; // From elink1 of axi_elink.v
wire [3:0] mem_m_axi_arcache; // From elink1 of axi_elink.v
wire [M_IDW-1:0] mem_m_axi_arid; // From elink1 of axi_elink.v
wire [7:0] mem_m_axi_arlen; // From elink1 of axi_elink.v
wire mem_m_axi_arlock; // From elink1 of axi_elink.v
wire [2:0] mem_m_axi_arprot; // From elink1 of axi_elink.v
wire [3:0] mem_m_axi_arqos; // From elink1 of axi_elink.v
wire mem_m_axi_arready; // From esaxi of esaxi.v
wire [2:0] mem_m_axi_arsize; // From elink1 of axi_elink.v
wire mem_m_axi_arvalid; // From elink1 of axi_elink.v
wire [31:0] mem_m_axi_awaddr; // From elink1 of axi_elink.v
wire [1:0] mem_m_axi_awburst; // From elink1 of axi_elink.v
wire [3:0] mem_m_axi_awcache; // From elink1 of axi_elink.v
wire [M_IDW-1:0] mem_m_axi_awid; // From elink1 of axi_elink.v
wire [7:0] mem_m_axi_awlen; // From elink1 of axi_elink.v
wire mem_m_axi_awlock; // From elink1 of axi_elink.v
wire [2:0] mem_m_axi_awprot; // From elink1 of axi_elink.v
wire [3:0] mem_m_axi_awqos; // From elink1 of axi_elink.v
wire mem_m_axi_awready; // From esaxi of esaxi.v
wire [2:0] mem_m_axi_awsize; // From elink1 of axi_elink.v
wire mem_m_axi_awvalid; // From elink1 of axi_elink.v
wire [S_IDW-1:0] mem_m_axi_bid; // From esaxi of esaxi.v
wire mem_m_axi_bready; // From elink1 of axi_elink.v
wire [1:0] mem_m_axi_bresp; // From esaxi of esaxi.v
wire mem_m_axi_bvalid; // From esaxi of esaxi.v
wire [31:0] mem_m_axi_rdata; // From esaxi of esaxi.v
wire [S_IDW-1:0] mem_m_axi_rid; // From esaxi of esaxi.v
wire mem_m_axi_rlast; // From esaxi of esaxi.v
wire mem_m_axi_rready; // From elink1 of axi_elink.v
wire [1:0] mem_m_axi_rresp; // From esaxi of esaxi.v
wire mem_m_axi_rvalid; // From esaxi of esaxi.v
wire [63:0] mem_m_axi_wdata; // From elink1 of axi_elink.v
wire [M_IDW-1:0] mem_m_axi_wid; // From elink1 of axi_elink.v
wire mem_m_axi_wlast; // From elink1 of axi_elink.v
wire mem_m_axi_wready; // From esaxi of esaxi.v
wire [7:0] mem_m_axi_wstrb; // From elink1 of axi_elink.v
wire mem_m_axi_wvalid; // From elink1 of axi_elink.v
wire mem_rd_access; // From esaxi of esaxi.v
wire [PW-1:0] mem_rd_packet; // From esaxi of esaxi.v
wire mem_rr_access; // From ememory of ememory.v
wire [PW-1:0] mem_rr_packet; // From ememory of ememory.v
wire mem_rr_wait; // From esaxi of esaxi.v
wire mem_wait; // From ememory of ememory.v
wire mem_wr_access; // From esaxi of esaxi.v
wire [PW-1:0] mem_wr_packet; // From esaxi of esaxi.v
wire rd_wait0; // From emaxi0 of emaxi.v
wire rd_wait1; // From emaxi1 of emaxi.v
wire rr_access; // From emaxi1 of emaxi.v
wire [PW-1:0] rr_packet; // From emaxi1 of emaxi.v
wire wr_wait0; // From emaxi0 of emaxi.v
wire wr_wait1; // From emaxi1 of emaxi.v
// End of automatics
//###################
// GLUE
//###################
assign clkout = clk1;
// Provide an easy way to send mailbox messages to elink0 via the 0x910 address
wire elink0_access_in;
wire elink1_access_in;
wire ext1_write_in;
wire ext1_read_in;
assign elink0_access_in = access_in &
(packet_in[39:28]==12'h810 |
packet_in[39:28]==12'h808 |
packet_in[39:28]==12'h920);
assign elink1_access_in = access_in &
(packet_in[39:28]==12'h820 |
packet_in[39:28]==12'h910);
assign ext1_write_in = elink1_access_in & packet_in[0];
assign ext1_read_in = elink1_access_in & ~packet_in[0];
//######################################################################
//AXI MASTER
//######################################################################
wire write_in;
wire read_in;
//Split stimulus to read/write
assign wait_out = wr_wait0 | rd_wait0 | wr_wait1 | rd_wait1;
assign write_in = elink0_access_in & packet_in[0];
assign read_in = elink0_access_in & ~packet_in[0];
//######################################################################
//AXI MASTER (DRIVES STIMULUS) to configure elink0
//######################################################################
/*emaxi AUTO_TEMPLATE (//Stimulus
.m_axi_aresetn (nreset),
.m_axi_aclk (clk1),
.m_axi_rdata ({m_axi_rdata[31:0],m_axi_rdata[31:0]}),
.m_\(.*\) (m_\1[]),
.rr_wait (wait_in),
.rr_access (access_out),
.rr_packet (packet_out[PW-1:0]),
.wr_access (write_in),
.wr_packet (packet_in[PW-1:0]),
.rd_access (read_in),
.rd_packet (packet_in[PW-1:0]),
.wr_wait (wr_wait0),
.rd_wait (rd_wait0),
);
*/
emaxi #(.M_IDW(M_IDW))
emaxi0 (/*AUTOINST*/
// Outputs
.wr_wait (wr_wait0), // Templated
.rd_wait (rd_wait0), // Templated
.rr_access (access_out), // Templated
.rr_packet (packet_out[PW-1:0]), // Templated
.m_axi_awid (m_axi_awid[M_IDW-1:0]), // Templated
.m_axi_awaddr (m_axi_awaddr[31:0]), // Templated
.m_axi_awlen (m_axi_awlen[7:0]), // Templated
.m_axi_awsize (m_axi_awsize[2:0]), // Templated
.m_axi_awburst (m_axi_awburst[1:0]), // Templated
.m_axi_awlock (m_axi_awlock), // Templated
.m_axi_awcache (m_axi_awcache[3:0]), // Templated
.m_axi_awprot (m_axi_awprot[2:0]), // Templated
.m_axi_awqos (m_axi_awqos[3:0]), // Templated
.m_axi_awvalid (m_axi_awvalid), // Templated
.m_axi_wid (m_axi_wid[M_IDW-1:0]), // Templated
.m_axi_wdata (m_axi_wdata[63:0]), // Templated
.m_axi_wstrb (m_axi_wstrb[7:0]), // Templated
.m_axi_wlast (m_axi_wlast), // Templated
.m_axi_wvalid (m_axi_wvalid), // Templated
.m_axi_bready (m_axi_bready), // Templated
.m_axi_arid (m_axi_arid[M_IDW-1:0]), // Templated
.m_axi_araddr (m_axi_araddr[31:0]), // Templated
.m_axi_arlen (m_axi_arlen[7:0]), // Templated
.m_axi_arsize (m_axi_arsize[2:0]), // Templated
.m_axi_arburst (m_axi_arburst[1:0]), // Templated
.m_axi_arlock (m_axi_arlock), // Templated
.m_axi_arcache (m_axi_arcache[3:0]), // Templated
.m_axi_arprot (m_axi_arprot[2:0]), // Templated
.m_axi_arqos (m_axi_arqos[3:0]), // Templated
.m_axi_arvalid (m_axi_arvalid), // Templated
.m_axi_rready (m_axi_rready), // Templated
// Inputs
.wr_access (write_in), // Templated
.wr_packet (packet_in[PW-1:0]), // Templated
.rd_access (read_in), // Templated
.rd_packet (packet_in[PW-1:0]), // Templated
.rr_wait (wait_in), // Templated
.m_axi_aclk (clk1), // Templated
.m_axi_aresetn (nreset), // Templated
.m_axi_awready (m_axi_awready), // Templated
.m_axi_wready (m_axi_wready), // Templated
.m_axi_bid (m_axi_bid[M_IDW-1:0]), // Templated
.m_axi_bresp (m_axi_bresp[1:0]), // Templated
.m_axi_bvalid (m_axi_bvalid), // Templated
.m_axi_arready (m_axi_arready), // Templated
.m_axi_rid (m_axi_rid[M_IDW-1:0]), // Templated
.m_axi_rdata ({m_axi_rdata[31:0],m_axi_rdata[31:0]}), // Templated
.m_axi_rresp (m_axi_rresp[1:0]), // Templated
.m_axi_rlast (m_axi_rlast), // Templated
.m_axi_rvalid (m_axi_rvalid)); // Templated
//######################################################################
//ELINK
//######################################################################
/*axi_elink AUTO_TEMPLATE (.m_axi_aresetn (nreset),
.s_axi_aresetn (nreset),
.sys_nreset (nreset),
.s_\(.*\) (m_\1[]),
.sys_clk (clk1),
.rxi_\(.*\) (elink1_txo_\1[]),
.txi_\(.*\) (elink1_rxo_\1[]),
.\(.*\) (@"(substring vl-cell-name 0 6)"_\1[]),
);
*/
axi_elink #(.ID(12'h810),
.ETYPE(0))
elink0 (.elink_active (dut_active),
.s_axi_wstrb ((m_axi_wstrb[3:0] | m_axi_wstrb[7:4])),//NOTE:HACK!!
.m_axi_rdata ({mem_m_axi_rdata[31:0],mem_m_axi_rdata[31:0]}),
/*AUTOINST*/
// Outputs
.rxo_wr_wait_p (elink0_rxo_wr_wait_p), // Templated
.rxo_wr_wait_n (elink0_rxo_wr_wait_n), // Templated
.rxo_rd_wait_p (elink0_rxo_rd_wait_p), // Templated
.rxo_rd_wait_n (elink0_rxo_rd_wait_n), // Templated
.txo_lclk_p (elink0_txo_lclk_p), // Templated
.txo_lclk_n (elink0_txo_lclk_n), // Templated
.txo_frame_p (elink0_txo_frame_p), // Templated
.txo_frame_n (elink0_txo_frame_n), // Templated
.txo_data_p (elink0_txo_data_p[7:0]), // Templated
.txo_data_n (elink0_txo_data_n[7:0]), // Templated
.chipid (elink0_chipid[11:0]), // Templated
.chip_nreset (elink0_chip_nreset), // Templated
.cclk_p (elink0_cclk_p), // Templated
.cclk_n (elink0_cclk_n), // Templated
.mailbox_irq (elink0_mailbox_irq), // Templated
.m_axi_awid (elink0_m_axi_awid[M_IDW-1:0]), // Templated
.m_axi_awaddr (elink0_m_axi_awaddr[31:0]), // Templated
.m_axi_awlen (elink0_m_axi_awlen[7:0]), // Templated
.m_axi_awsize (elink0_m_axi_awsize[2:0]), // Templated
.m_axi_awburst (elink0_m_axi_awburst[1:0]), // Templated
.m_axi_awlock (elink0_m_axi_awlock), // Templated
.m_axi_awcache (elink0_m_axi_awcache[3:0]), // Templated
.m_axi_awprot (elink0_m_axi_awprot[2:0]), // Templated
.m_axi_awqos (elink0_m_axi_awqos[3:0]), // Templated
.m_axi_awvalid (elink0_m_axi_awvalid), // Templated
.m_axi_wid (elink0_m_axi_wid[M_IDW-1:0]), // Templated
.m_axi_wdata (elink0_m_axi_wdata[63:0]), // Templated
.m_axi_wstrb (elink0_m_axi_wstrb[7:0]), // Templated
.m_axi_wlast (elink0_m_axi_wlast), // Templated
.m_axi_wvalid (elink0_m_axi_wvalid), // Templated
.m_axi_bready (elink0_m_axi_bready), // Templated
.m_axi_arid (elink0_m_axi_arid[M_IDW-1:0]), // Templated
.m_axi_araddr (elink0_m_axi_araddr[31:0]), // Templated
.m_axi_arlen (elink0_m_axi_arlen[7:0]), // Templated
.m_axi_arsize (elink0_m_axi_arsize[2:0]), // Templated
.m_axi_arburst (elink0_m_axi_arburst[1:0]), // Templated
.m_axi_arlock (elink0_m_axi_arlock), // Templated
.m_axi_arcache (elink0_m_axi_arcache[3:0]), // Templated
.m_axi_arprot (elink0_m_axi_arprot[2:0]), // Templated
.m_axi_arqos (elink0_m_axi_arqos[3:0]), // Templated
.m_axi_arvalid (elink0_m_axi_arvalid), // Templated
.m_axi_rready (elink0_m_axi_rready), // Templated
.s_axi_arready (m_axi_arready), // Templated
.s_axi_awready (m_axi_awready), // Templated
.s_axi_bid (m_axi_bid[S_IDW-1:0]), // Templated
.s_axi_bresp (m_axi_bresp[1:0]), // Templated
.s_axi_bvalid (m_axi_bvalid), // Templated
.s_axi_rid (m_axi_rid[S_IDW-1:0]), // Templated
.s_axi_rdata (m_axi_rdata[31:0]), // Templated
.s_axi_rlast (m_axi_rlast), // Templated
.s_axi_rresp (m_axi_rresp[1:0]), // Templated
.s_axi_rvalid (m_axi_rvalid), // Templated
.s_axi_wready (m_axi_wready), // Templated
// Inputs
.sys_nreset (nreset), // Templated
.sys_clk (clk1), // Templated
.rxi_lclk_p (elink1_txo_lclk_p), // Templated
.rxi_lclk_n (elink1_txo_lclk_n), // Templated
.rxi_frame_p (elink1_txo_frame_p), // Templated
.rxi_frame_n (elink1_txo_frame_n), // Templated
.rxi_data_p (elink1_txo_data_p[7:0]), // Templated
.rxi_data_n (elink1_txo_data_n[7:0]), // Templated
.txi_wr_wait_p (elink1_rxo_wr_wait_p), // Templated
.txi_wr_wait_n (elink1_rxo_wr_wait_n), // Templated
.txi_rd_wait_p (elink1_rxo_rd_wait_p), // Templated
.txi_rd_wait_n (elink1_rxo_rd_wait_n), // Templated
.m_axi_aresetn (nreset), // Templated
.m_axi_awready (elink0_m_axi_awready), // Templated
.m_axi_wready (elink0_m_axi_wready), // Templated
.m_axi_bid (elink0_m_axi_bid[M_IDW-1:0]), // Templated
.m_axi_bresp (elink0_m_axi_bresp[1:0]), // Templated
.m_axi_bvalid (elink0_m_axi_bvalid), // Templated
.m_axi_arready (elink0_m_axi_arready), // Templated
.m_axi_rid (elink0_m_axi_rid[M_IDW-1:0]), // Templated
.m_axi_rresp (elink0_m_axi_rresp[1:0]), // Templated
.m_axi_rlast (elink0_m_axi_rlast), // Templated
.m_axi_rvalid (elink0_m_axi_rvalid), // Templated
.s_axi_aresetn (nreset), // Templated
.s_axi_arid (m_axi_arid[S_IDW-1:0]), // Templated
.s_axi_araddr (m_axi_araddr[31:0]), // Templated
.s_axi_arburst (m_axi_arburst[1:0]), // Templated
.s_axi_arcache (m_axi_arcache[3:0]), // Templated
.s_axi_arlock (m_axi_arlock), // Templated
.s_axi_arlen (m_axi_arlen[7:0]), // Templated
.s_axi_arprot (m_axi_arprot[2:0]), // Templated
.s_axi_arqos (m_axi_arqos[3:0]), // Templated
.s_axi_arsize (m_axi_arsize[2:0]), // Templated
.s_axi_arvalid (m_axi_arvalid), // Templated
.s_axi_awid (m_axi_awid[S_IDW-1:0]), // Templated
.s_axi_awaddr (m_axi_awaddr[31:0]), // Templated
.s_axi_awburst (m_axi_awburst[1:0]), // Templated
.s_axi_awcache (m_axi_awcache[3:0]), // Templated
.s_axi_awlock (m_axi_awlock), // Templated
.s_axi_awlen (m_axi_awlen[7:0]), // Templated
.s_axi_awprot (m_axi_awprot[2:0]), // Templated
.s_axi_awqos (m_axi_awqos[3:0]), // Templated
.s_axi_awsize (m_axi_awsize[2:0]), // Templated
.s_axi_awvalid (m_axi_awvalid), // Templated
.s_axi_bready (m_axi_bready), // Templated
.s_axi_rready (m_axi_rready), // Templated
.s_axi_wid (m_axi_wid[S_IDW-1:0]), // Templated
.s_axi_wdata (m_axi_wdata[31:0]), // Templated
.s_axi_wlast (m_axi_wlast), // Templated
.s_axi_wvalid (m_axi_wvalid)); // Templated
//######################################################################
//TIE OFF UNUSED MASTER PORT ON ELINK0
//######################################################################
/*axislave_stub AUTO_TEMPLATE (
// Outputs
.s_\(.*\) (elink0_m_\1[]),
);
*/
defparam axislave_stub.S_IDW = S_IDW;
axislave_stub axislave_stub (.s_axi_aclk (clk1),
.s_axi_aresetn (nreset),
/*AUTOINST*/
// Outputs
.s_axi_arready (elink0_m_axi_arready), // Templated
.s_axi_awready (elink0_m_axi_awready), // Templated
.s_axi_bid (elink0_m_axi_bid[S_IDW-1:0]), // Templated
.s_axi_bresp (elink0_m_axi_bresp[1:0]), // Templated
.s_axi_bvalid (elink0_m_axi_bvalid), // Templated
.s_axi_rid (elink0_m_axi_rid[S_IDW-1:0]), // Templated
.s_axi_rdata (elink0_m_axi_rdata[31:0]), // Templated
.s_axi_rlast (elink0_m_axi_rlast), // Templated
.s_axi_rresp (elink0_m_axi_rresp[1:0]), // Templated
.s_axi_rvalid (elink0_m_axi_rvalid), // Templated
.s_axi_wready (elink0_m_axi_wready), // Templated
// Inputs
.s_axi_arid (elink0_m_axi_arid[S_IDW-1:0]), // Templated
.s_axi_araddr (elink0_m_axi_araddr[31:0]), // Templated
.s_axi_arburst (elink0_m_axi_arburst[1:0]), // Templated
.s_axi_arcache (elink0_m_axi_arcache[3:0]), // Templated
.s_axi_arlock (elink0_m_axi_arlock), // Templated
.s_axi_arlen (elink0_m_axi_arlen[7:0]), // Templated
.s_axi_arprot (elink0_m_axi_arprot[2:0]), // Templated
.s_axi_arqos (elink0_m_axi_arqos[3:0]), // Templated
.s_axi_arsize (elink0_m_axi_arsize[2:0]), // Templated
.s_axi_arvalid (elink0_m_axi_arvalid), // Templated
.s_axi_awid (elink0_m_axi_awid[S_IDW-1:0]), // Templated
.s_axi_awaddr (elink0_m_axi_awaddr[31:0]), // Templated
.s_axi_awburst (elink0_m_axi_awburst[1:0]), // Templated
.s_axi_awcache (elink0_m_axi_awcache[3:0]), // Templated
.s_axi_awlock (elink0_m_axi_awlock), // Templated
.s_axi_awlen (elink0_m_axi_awlen[7:0]), // Templated
.s_axi_awprot (elink0_m_axi_awprot[2:0]), // Templated
.s_axi_awqos (elink0_m_axi_awqos[3:0]), // Templated
.s_axi_awsize (elink0_m_axi_awsize[2:0]), // Templated
.s_axi_awvalid (elink0_m_axi_awvalid), // Templated
.s_axi_bready (elink0_m_axi_bready), // Templated
.s_axi_rready (elink0_m_axi_rready), // Templated
.s_axi_wid (elink0_m_axi_wid[S_IDW-1:0]), // Templated
.s_axi_wdata (elink0_m_axi_wdata[31:0]), // Templated
.s_axi_wlast (elink0_m_axi_wlast), // Templated
.s_axi_wstrb (elink0_m_axi_wstrb[3:0]), // Templated
.s_axi_wvalid (elink0_m_axi_wvalid)); // Templated
//######################################################################
//AXI MASTER (DRIVES STIMULUS) to configure elink1
//######################################################################
/*emaxi AUTO_TEMPLATE (//Stimulus
.m_axi_aresetn (nreset),
.m_axi_aclk (clk1),
.m_\(.*\) (ext1_m_\1[]),
.rr_wait (1'b0),
.wr_access (ext1_write_in),
.wr_packet (packet_in[PW-1:0]),
.rd_access (ext1_read_in),
.rd_packet (packet_in[PW-1:0]),
.wr_wait (wr_wait1),
.rd_wait (rd_wait1),
);
*/
emaxi #(.M_IDW(M_IDW))
emaxi1 (/*AUTOINST*/
// Outputs
.wr_wait (wr_wait1), // Templated
.rd_wait (rd_wait1), // Templated
.rr_access (rr_access),
.rr_packet (rr_packet[PW-1:0]),
.m_axi_awid (ext1_m_axi_awid[M_IDW-1:0]), // Templated
.m_axi_awaddr (ext1_m_axi_awaddr[31:0]), // Templated
.m_axi_awlen (ext1_m_axi_awlen[7:0]), // Templated
.m_axi_awsize (ext1_m_axi_awsize[2:0]), // Templated
.m_axi_awburst (ext1_m_axi_awburst[1:0]), // Templated
.m_axi_awlock (ext1_m_axi_awlock), // Templated
.m_axi_awcache (ext1_m_axi_awcache[3:0]), // Templated
.m_axi_awprot (ext1_m_axi_awprot[2:0]), // Templated
.m_axi_awqos (ext1_m_axi_awqos[3:0]), // Templated
.m_axi_awvalid (ext1_m_axi_awvalid), // Templated
.m_axi_wid (ext1_m_axi_wid[M_IDW-1:0]), // Templated
.m_axi_wdata (ext1_m_axi_wdata[63:0]), // Templated
.m_axi_wstrb (ext1_m_axi_wstrb[7:0]), // Templated
.m_axi_wlast (ext1_m_axi_wlast), // Templated
.m_axi_wvalid (ext1_m_axi_wvalid), // Templated
.m_axi_bready (ext1_m_axi_bready), // Templated
.m_axi_arid (ext1_m_axi_arid[M_IDW-1:0]), // Templated
.m_axi_araddr (ext1_m_axi_araddr[31:0]), // Templated
.m_axi_arlen (ext1_m_axi_arlen[7:0]), // Templated
.m_axi_arsize (ext1_m_axi_arsize[2:0]), // Templated
.m_axi_arburst (ext1_m_axi_arburst[1:0]), // Templated
.m_axi_arlock (ext1_m_axi_arlock), // Templated
.m_axi_arcache (ext1_m_axi_arcache[3:0]), // Templated
.m_axi_arprot (ext1_m_axi_arprot[2:0]), // Templated
.m_axi_arqos (ext1_m_axi_arqos[3:0]), // Templated
.m_axi_arvalid (ext1_m_axi_arvalid), // Templated
.m_axi_rready (ext1_m_axi_rready), // Templated
// Inputs
.wr_access (ext1_write_in), // Templated
.wr_packet (packet_in[PW-1:0]), // Templated
.rd_access (ext1_read_in), // Templated
.rd_packet (packet_in[PW-1:0]), // Templated
.rr_wait (1'b0), // Templated
.m_axi_aclk (clk1), // Templated
.m_axi_aresetn (nreset), // Templated
.m_axi_awready (ext1_m_axi_awready), // Templated
.m_axi_wready (ext1_m_axi_wready), // Templated
.m_axi_bid (ext1_m_axi_bid[M_IDW-1:0]), // Templated
.m_axi_bresp (ext1_m_axi_bresp[1:0]), // Templated
.m_axi_bvalid (ext1_m_axi_bvalid), // Templated
.m_axi_arready (ext1_m_axi_arready), // Templated
.m_axi_rid (ext1_m_axi_rid[M_IDW-1:0]), // Templated
.m_axi_rdata (ext1_m_axi_rdata[63:0]), // Templated
.m_axi_rresp (ext1_m_axi_rresp[1:0]), // Templated
.m_axi_rlast (ext1_m_axi_rlast), // Templated
.m_axi_rvalid (ext1_m_axi_rvalid)); // Templated
//######################################################################
//2ND ELINK
//######################################################################
/*axi_elink AUTO_TEMPLATE (.m_axi_aresetn (nreset),
.s_axi_aresetn (nreset),
.sys_nreset (nreset),
.sys_clk (clk1),
.rxi_\(.*\) (elink0_txo_\1[]),
.txi_\(.*\) (elink0_rxo_\1[]),
.s_\(.*\) (ext1_m_\1[]),
.m_\(.*\) (mem_m_\1[]),
.\(.*\) (@"(substring vl-cell-name 0 6)"_\1[]),
);
*/
defparam elink1.ID = 12'h820;
defparam elink1.ETYPE = 0;
defparam elink1.S_IDW = S2_IDW;
defparam elink1.M_IDW = M2_IDW;
//defparam elink1.WAIT_WRRD = 0;
axi_elink elink1 ( .s_axi_wstrb ((ext1_m_axi_wstrb[3:0] | ext1_m_axi_wstrb[7:4])),//NOTE:HACK!!
/*AUTOINST*/
// Outputs
.elink_active (elink1_elink_active), // Templated
.rxo_wr_wait_p (elink1_rxo_wr_wait_p), // Templated
.rxo_wr_wait_n (elink1_rxo_wr_wait_n), // Templated
.rxo_rd_wait_p (elink1_rxo_rd_wait_p), // Templated
.rxo_rd_wait_n (elink1_rxo_rd_wait_n), // Templated
.txo_lclk_p (elink1_txo_lclk_p), // Templated
.txo_lclk_n (elink1_txo_lclk_n), // Templated
.txo_frame_p (elink1_txo_frame_p), // Templated
.txo_frame_n (elink1_txo_frame_n), // Templated
.txo_data_p (elink1_txo_data_p[7:0]), // Templated
.txo_data_n (elink1_txo_data_n[7:0]), // Templated
.chipid (elink1_chipid[11:0]), // Templated
.chip_nreset (elink1_chip_nreset), // Templated
.cclk_p (elink1_cclk_p), // Templated
.cclk_n (elink1_cclk_n), // Templated
.mailbox_irq (elink1_mailbox_irq), // Templated
.m_axi_awid (mem_m_axi_awid[M_IDW-1:0]), // Templated
.m_axi_awaddr (mem_m_axi_awaddr[31:0]), // Templated
.m_axi_awlen (mem_m_axi_awlen[7:0]), // Templated
.m_axi_awsize (mem_m_axi_awsize[2:0]), // Templated
.m_axi_awburst (mem_m_axi_awburst[1:0]), // Templated
.m_axi_awlock (mem_m_axi_awlock), // Templated
.m_axi_awcache (mem_m_axi_awcache[3:0]), // Templated
.m_axi_awprot (mem_m_axi_awprot[2:0]), // Templated
.m_axi_awqos (mem_m_axi_awqos[3:0]), // Templated
.m_axi_awvalid (mem_m_axi_awvalid), // Templated
.m_axi_wid (mem_m_axi_wid[M_IDW-1:0]), // Templated
.m_axi_wdata (mem_m_axi_wdata[63:0]), // Templated
.m_axi_wstrb (mem_m_axi_wstrb[7:0]), // Templated
.m_axi_wlast (mem_m_axi_wlast), // Templated
.m_axi_wvalid (mem_m_axi_wvalid), // Templated
.m_axi_bready (mem_m_axi_bready), // Templated
.m_axi_arid (mem_m_axi_arid[M_IDW-1:0]), // Templated
.m_axi_araddr (mem_m_axi_araddr[31:0]), // Templated
.m_axi_arlen (mem_m_axi_arlen[7:0]), // Templated
.m_axi_arsize (mem_m_axi_arsize[2:0]), // Templated
.m_axi_arburst (mem_m_axi_arburst[1:0]), // Templated
.m_axi_arlock (mem_m_axi_arlock), // Templated
.m_axi_arcache (mem_m_axi_arcache[3:0]), // Templated
.m_axi_arprot (mem_m_axi_arprot[2:0]), // Templated
.m_axi_arqos (mem_m_axi_arqos[3:0]), // Templated
.m_axi_arvalid (mem_m_axi_arvalid), // Templated
.m_axi_rready (mem_m_axi_rready), // Templated
.s_axi_arready (ext1_m_axi_arready), // Templated
.s_axi_awready (ext1_m_axi_awready), // Templated
.s_axi_bid (ext1_m_axi_bid[S_IDW-1:0]), // Templated
.s_axi_bresp (ext1_m_axi_bresp[1:0]), // Templated
.s_axi_bvalid (ext1_m_axi_bvalid), // Templated
.s_axi_rid (ext1_m_axi_rid[S_IDW-1:0]), // Templated
.s_axi_rdata (ext1_m_axi_rdata[31:0]), // Templated
.s_axi_rlast (ext1_m_axi_rlast), // Templated
.s_axi_rresp (ext1_m_axi_rresp[1:0]), // Templated
.s_axi_rvalid (ext1_m_axi_rvalid), // Templated
.s_axi_wready (ext1_m_axi_wready), // Templated
// Inputs
.sys_nreset (nreset), // Templated
.sys_clk (clk1), // Templated
.rxi_lclk_p (elink0_txo_lclk_p), // Templated
.rxi_lclk_n (elink0_txo_lclk_n), // Templated
.rxi_frame_p (elink0_txo_frame_p), // Templated
.rxi_frame_n (elink0_txo_frame_n), // Templated
.rxi_data_p (elink0_txo_data_p[7:0]), // Templated
.rxi_data_n (elink0_txo_data_n[7:0]), // Templated
.txi_wr_wait_p (elink0_rxo_wr_wait_p), // Templated
.txi_wr_wait_n (elink0_rxo_wr_wait_n), // Templated
.txi_rd_wait_p (elink0_rxo_rd_wait_p), // Templated
.txi_rd_wait_n (elink0_rxo_rd_wait_n), // Templated
.m_axi_aresetn (nreset), // Templated
.m_axi_awready (mem_m_axi_awready), // Templated
.m_axi_wready (mem_m_axi_wready), // Templated
.m_axi_bid (mem_m_axi_bid[M_IDW-1:0]), // Templated
.m_axi_bresp (mem_m_axi_bresp[1:0]), // Templated
.m_axi_bvalid (mem_m_axi_bvalid), // Templated
.m_axi_arready (mem_m_axi_arready), // Templated
.m_axi_rid (mem_m_axi_rid[M_IDW-1:0]), // Templated
.m_axi_rdata (mem_m_axi_rdata[63:0]), // Templated
.m_axi_rresp (mem_m_axi_rresp[1:0]), // Templated
.m_axi_rlast (mem_m_axi_rlast), // Templated
.m_axi_rvalid (mem_m_axi_rvalid), // Templated
.s_axi_aresetn (nreset), // Templated
.s_axi_arid (ext1_m_axi_arid[S_IDW-1:0]), // Templated
.s_axi_araddr (ext1_m_axi_araddr[31:0]), // Templated
.s_axi_arburst (ext1_m_axi_arburst[1:0]), // Templated
.s_axi_arcache (ext1_m_axi_arcache[3:0]), // Templated
.s_axi_arlock (ext1_m_axi_arlock), // Templated
.s_axi_arlen (ext1_m_axi_arlen[7:0]), // Templated
.s_axi_arprot (ext1_m_axi_arprot[2:0]), // Templated
.s_axi_arqos (ext1_m_axi_arqos[3:0]), // Templated
.s_axi_arsize (ext1_m_axi_arsize[2:0]), // Templated
.s_axi_arvalid (ext1_m_axi_arvalid), // Templated
.s_axi_awid (ext1_m_axi_awid[S_IDW-1:0]), // Templated
.s_axi_awaddr (ext1_m_axi_awaddr[31:0]), // Templated
.s_axi_awburst (ext1_m_axi_awburst[1:0]), // Templated
.s_axi_awcache (ext1_m_axi_awcache[3:0]), // Templated
.s_axi_awlock (ext1_m_axi_awlock), // Templated
.s_axi_awlen (ext1_m_axi_awlen[7:0]), // Templated
.s_axi_awprot (ext1_m_axi_awprot[2:0]), // Templated
.s_axi_awqos (ext1_m_axi_awqos[3:0]), // Templated
.s_axi_awsize (ext1_m_axi_awsize[2:0]), // Templated
.s_axi_awvalid (ext1_m_axi_awvalid), // Templated
.s_axi_bready (ext1_m_axi_bready), // Templated
.s_axi_rready (ext1_m_axi_rready), // Templated
.s_axi_wid (ext1_m_axi_wid[S_IDW-1:0]), // Templated
.s_axi_wdata (ext1_m_axi_wdata[31:0]), // Templated
.s_axi_wlast (ext1_m_axi_wlast), // Templated
.s_axi_wvalid (ext1_m_axi_wvalid)); // Templated
//######################################################################
//AXI SLAVE
//######################################################################
/*esaxi AUTO_TEMPLATE (//Stimulus
.s_\(.*\) (mem_m_\1[]),
.\(.*\) (mem_\1[]),
);
*/
esaxi #(.S_IDW(S_IDW), .RETURN_ADDR(RETURN_ADDR))
esaxi (.s_axi_aclk (clk1),
.s_axi_aresetn (nreset),
.s_axi_wstrb (mem_m_axi_wstrb[7:4] | mem_m_axi_wstrb[3:0]),
/*AUTOINST*/
// Outputs
.wr_access (mem_wr_access), // Templated
.wr_packet (mem_wr_packet[PW-1:0]), // Templated
.rd_access (mem_rd_access), // Templated
.rd_packet (mem_rd_packet[PW-1:0]), // Templated
.rr_wait (mem_rr_wait), // Templated
.s_axi_arready (mem_m_axi_arready), // Templated
.s_axi_awready (mem_m_axi_awready), // Templated
.s_axi_bid (mem_m_axi_bid[S_IDW-1:0]), // Templated
.s_axi_bresp (mem_m_axi_bresp[1:0]), // Templated
.s_axi_bvalid (mem_m_axi_bvalid), // Templated
.s_axi_rid (mem_m_axi_rid[S_IDW-1:0]), // Templated
.s_axi_rdata (mem_m_axi_rdata[31:0]), // Templated
.s_axi_rlast (mem_m_axi_rlast), // Templated
.s_axi_rresp (mem_m_axi_rresp[1:0]), // Templated
.s_axi_rvalid (mem_m_axi_rvalid), // Templated
.s_axi_wready (mem_m_axi_wready), // Templated
// Inputs
.wr_wait (mem_wr_wait), // Templated
.rd_wait (mem_rd_wait), // Templated
.rr_access (mem_rr_access), // Templated
.rr_packet (mem_rr_packet[PW-1:0]), // Templated
.s_axi_arid (mem_m_axi_arid[S_IDW-1:0]), // Templated
.s_axi_araddr (mem_m_axi_araddr[31:0]), // Templated
.s_axi_arburst (mem_m_axi_arburst[1:0]), // Templated
.s_axi_arcache (mem_m_axi_arcache[3:0]), // Templated
.s_axi_arlock (mem_m_axi_arlock), // Templated
.s_axi_arlen (mem_m_axi_arlen[7:0]), // Templated
.s_axi_arprot (mem_m_axi_arprot[2:0]), // Templated
.s_axi_arqos (mem_m_axi_arqos[3:0]), // Templated
.s_axi_arsize (mem_m_axi_arsize[2:0]), // Templated
.s_axi_arvalid (mem_m_axi_arvalid), // Templated
.s_axi_awid (mem_m_axi_awid[S_IDW-1:0]), // Templated
.s_axi_awaddr (mem_m_axi_awaddr[31:0]), // Templated
.s_axi_awburst (mem_m_axi_awburst[1:0]), // Templated
.s_axi_awcache (mem_m_axi_awcache[3:0]), // Templated
.s_axi_awlock (mem_m_axi_awlock), // Templated
.s_axi_awlen (mem_m_axi_awlen[7:0]), // Templated
.s_axi_awprot (mem_m_axi_awprot[2:0]), // Templated
.s_axi_awqos (mem_m_axi_awqos[3:0]), // Templated
.s_axi_awsize (mem_m_axi_awsize[2:0]), // Templated
.s_axi_awvalid (mem_m_axi_awvalid), // Templated
.s_axi_bready (mem_m_axi_bready), // Templated
.s_axi_rready (mem_m_axi_rready), // Templated
.s_axi_wid (mem_m_axi_wid[S_IDW-1:0]), // Templated
.s_axi_wdata (mem_m_axi_wdata[31:0]), // Templated
.s_axi_wlast (mem_m_axi_wlast), // Templated
.s_axi_wvalid (mem_m_axi_wvalid)); // Templated
//######################################################################
// MEMORY PORT
//######################################################################
//"Arbitration" between read/write transaction
assign mem_access = mem_wr_access | mem_rd_access;
assign mem_packet[PW-1:0] = mem_wr_access ? mem_wr_packet[PW-1:0]:
mem_rd_packet[PW-1:0];
assign mem_rd_wait = (mem_wait & mem_rd_access) |
mem_wr_access;
assign mem_wr_wait = (mem_wait & mem_wr_access);
/*ememory AUTO_TEMPLATE (
// Outputsd
.\(.*\)_out (mem_rr_\1[]),
.\(.*\)_in (mem_\1[]),
.wait_out (mem_wait),
.wait_in (mem_rr_wait), //pushback on reads
);
*/
ememory #(.WAIT(0),
.MON(1))
ememory (.clk (clk1),
.coreid (12'h0),
/*AUTOINST*/
// Outputs
.wait_out (mem_wait), // Templated
.access_out (mem_rr_access), // Templated
.packet_out (mem_rr_packet[PW-1:0]), // Templated
// Inputs
.nreset (nreset),
.access_in (mem_access), // Templated
.packet_in (mem_packet[PW-1:0]), // Templated
.wait_in (mem_rr_wait)); // Templated
endmodule
|
module tso_mon ( clk, rst_l);
input clk; // the cpu clock
input rst_l; // reset (active low).
`ifdef GATE_SIM
`else
reg tso_mon_msg; // decides should we print all tso_mon messages
reg disable_lock_check; // disable one of my checkes
reg kill_on_cross_mod_code;
reg force_dfq;
integer stb_drain_to_max; // what the Store buffer timeout will be.
reg enable_ifu_lsu_inv_clear;
initial
begin
if( $test$plusargs("force_dfq") )
force_dfq = 1'b1;
else
force_dfq= 1'b0;
if( $test$plusargs("enable_ifu_lsu_inv_clear") )
enable_ifu_lsu_inv_clear = 1;
else
enable_ifu_lsu_inv_clear = 0;
if( $test$plusargs("tso_mon_msg") )
tso_mon_msg = 1'b1;
else
tso_mon_msg= 1'b0;
if( $test$plusargs("disable_lock_check") )
disable_lock_check = 1'b1;
else
disable_lock_check = 1'b0;
if (! $value$plusargs("stb_drain_to_max=%d", stb_drain_to_max)) begin
stb_drain_to_max = `STB_DRAIN_TO ;
end
$display("%0d tso_mon: stb_drain_to_max = %d", $time, stb_drain_to_max);
if( $test$plusargs("kill_on_cross_mod_code") )
kill_on_cross_mod_code = 1'b1;
else
kill_on_cross_mod_code = 1'b0;
end
wire tso_mon_vcc = 1'b1;
wire pll_lock = `TOP_MEMORY.ctu.u_pll.pll_lock;
//--------------------------------------------------------------------------------------
// related to bug 6372 - need to monitor some DFQ signals
//--------------------------------------------------------------------------------------
`ifdef RTL_SPARC0
wire spc0_dfq_byp_ff_en = `TOP_DESIGN.sparc0.lsu.qctl2.dfq_byp_ff_en;
wire spc0_dfq_wr_en = `TOP_DESIGN.sparc0.lsu.qctl2.dfq_wr_en;
reg spc0_dfq_byp_ff_en_d1;
reg spc0_dfq_wr_en_d1;
`endif
`ifdef RTL_SPARC1
wire spc1_dfq_byp_ff_en = `TOP_DESIGN.sparc1.lsu.qctl2.dfq_byp_ff_en;
wire spc1_dfq_wr_en = `TOP_DESIGN.sparc1.lsu.qctl2.dfq_wr_en;
reg spc1_dfq_byp_ff_en_d1;
reg spc1_dfq_wr_en_d1;
`endif
`ifdef RTL_SPARC2
wire spc2_dfq_byp_ff_en = `TOP_DESIGN.sparc2.lsu.qctl2.dfq_byp_ff_en;
wire spc2_dfq_wr_en = `TOP_DESIGN.sparc2.lsu.qctl2.dfq_wr_en;
reg spc2_dfq_byp_ff_en_d1;
reg spc2_dfq_wr_en_d1;
`endif
`ifdef RTL_SPARC3
wire spc3_dfq_byp_ff_en = `TOP_DESIGN.sparc3.lsu.qctl2.dfq_byp_ff_en;
wire spc3_dfq_wr_en = `TOP_DESIGN.sparc3.lsu.qctl2.dfq_wr_en;
reg spc3_dfq_byp_ff_en_d1;
reg spc3_dfq_wr_en_d1;
`endif
`ifdef RTL_SPARC4
wire spc4_dfq_byp_ff_en = `TOP_DESIGN.sparc4.lsu.qctl2.dfq_byp_ff_en;
wire spc4_dfq_wr_en = `TOP_DESIGN.sparc4.lsu.qctl2.dfq_wr_en;
reg spc4_dfq_byp_ff_en_d1;
reg spc4_dfq_wr_en_d1;
`endif
`ifdef RTL_SPARC5
wire spc5_dfq_byp_ff_en = `TOP_DESIGN.sparc5.lsu.qctl2.dfq_byp_ff_en;
wire spc5_dfq_wr_en = `TOP_DESIGN.sparc5.lsu.qctl2.dfq_wr_en;
reg spc5_dfq_byp_ff_en_d1;
reg spc5_dfq_wr_en_d1;
`endif
`ifdef RTL_SPARC6
wire spc6_dfq_byp_ff_en = `TOP_DESIGN.sparc6.lsu.qctl2.dfq_byp_ff_en;
wire spc6_dfq_wr_en = `TOP_DESIGN.sparc6.lsu.qctl2.dfq_wr_en;
reg spc6_dfq_byp_ff_en_d1;
reg spc6_dfq_wr_en_d1;
`endif
`ifdef RTL_SPARC7
wire spc7_dfq_byp_ff_en = `TOP_DESIGN.sparc7.lsu.qctl2.dfq_byp_ff_en;
wire spc7_dfq_wr_en = `TOP_DESIGN.sparc7.lsu.qctl2.dfq_wr_en;
reg spc7_dfq_byp_ff_en_d1;
reg spc7_dfq_wr_en_d1;
`endif
//--------------------------------------------------------------------------------------
// spc to pcx packets
//--------------------------------------------------------------------------------------
wire [4:0] spc0_pcx_req_pq = `TOP_MEMORY.spc0_pcx_req_pq[4:0];
wire spc0_pcx_atom_pq = `TOP_MEMORY.spc0_pcx_atom_pq;
wire [`PCX_WIDTH-1:0] spc0_pcx_data_pa = `TOP_MEMORY.spc0_pcx_data_pa[`PCX_WIDTH-1:0];
reg pcx0_vld_d1; // valid pcx packet
reg pcx0_atom_pq_d1; // atomic bit delayed by 1
reg pcx0_atom_pq_d2; // delayed by 2
reg pcx0_req_pq_d1; // OR of request bits delayed by 1
reg [5:0] pcx0_type_d1; // packet type delayed by 1
wire [4:0] spc1_pcx_req_pq = `TOP_MEMORY.spc1_pcx_req_pq[4:0];
wire spc1_pcx_atom_pq = `TOP_MEMORY.spc1_pcx_atom_pq;
wire [`PCX_WIDTH-1:0] spc1_pcx_data_pa = `TOP_MEMORY.spc1_pcx_data_pa[`PCX_WIDTH-1:0];
reg pcx1_vld_d1; // valid pcx packet
reg pcx1_atom_pq_d1; // atomic bit delayed by 1
reg pcx1_atom_pq_d2; // delayed by 2
reg pcx1_req_pq_d1; // OR of request bits delayed by 1
reg [5:0] pcx1_type_d1; // packet type delayed by 1
wire [4:0] spc2_pcx_req_pq = `TOP_MEMORY.spc2_pcx_req_pq[4:0];
wire spc2_pcx_atom_pq = `TOP_MEMORY.spc2_pcx_atom_pq;
wire [`PCX_WIDTH-1:0] spc2_pcx_data_pa = `TOP_MEMORY.spc2_pcx_data_pa[`PCX_WIDTH-1:0];
reg pcx2_vld_d1; // valid pcx packet
reg pcx2_atom_pq_d1; // atomic bit delayed by 1
reg pcx2_atom_pq_d2; // delayed by 2
reg pcx2_req_pq_d1; // OR of request bits delayed by 1
reg [5:0] pcx2_type_d1; // packet type delayed by 1
wire [4:0] spc3_pcx_req_pq = `TOP_MEMORY.spc3_pcx_req_pq[4:0];
wire spc3_pcx_atom_pq = `TOP_MEMORY.spc3_pcx_atom_pq;
wire [`PCX_WIDTH-1:0] spc3_pcx_data_pa = `TOP_MEMORY.spc3_pcx_data_pa[`PCX_WIDTH-1:0];
reg pcx3_vld_d1; // valid pcx packet
reg pcx3_atom_pq_d1; // atomic bit delayed by 1
reg pcx3_atom_pq_d2; // delayed by 2
reg pcx3_req_pq_d1; // OR of request bits delayed by 1
reg [5:0] pcx3_type_d1; // packet type delayed by 1
wire [4:0] spc4_pcx_req_pq = `TOP_MEMORY.spc4_pcx_req_pq[4:0];
wire spc4_pcx_atom_pq = `TOP_MEMORY.spc4_pcx_atom_pq;
wire [`PCX_WIDTH-1:0] spc4_pcx_data_pa = `TOP_MEMORY.spc4_pcx_data_pa[`PCX_WIDTH-1:0];
reg pcx4_vld_d1; // valid pcx packet
reg pcx4_atom_pq_d1; // atomic bit delayed by 1
reg pcx4_atom_pq_d2; // delayed by 2
reg pcx4_req_pq_d1; // OR of request bits delayed by 1
reg [5:0] pcx4_type_d1; // packet type delayed by 1
wire [4:0] spc5_pcx_req_pq = `TOP_MEMORY.spc5_pcx_req_pq[4:0];
wire spc5_pcx_atom_pq = `TOP_MEMORY.spc5_pcx_atom_pq;
wire [`PCX_WIDTH-1:0] spc5_pcx_data_pa = `TOP_MEMORY.spc5_pcx_data_pa[`PCX_WIDTH-1:0];
reg pcx5_vld_d1; // valid pcx packet
reg pcx5_atom_pq_d1; // atomic bit delayed by 1
reg pcx5_atom_pq_d2; // delayed by 2
reg pcx5_req_pq_d1; // OR of request bits delayed by 1
reg [5:0] pcx5_type_d1; // packet type delayed by 1
wire [4:0] spc6_pcx_req_pq = `TOP_MEMORY.spc6_pcx_req_pq[4:0];
wire spc6_pcx_atom_pq = `TOP_MEMORY.spc6_pcx_atom_pq;
wire [`PCX_WIDTH-1:0] spc6_pcx_data_pa = `TOP_MEMORY.spc6_pcx_data_pa[`PCX_WIDTH-1:0];
reg pcx6_vld_d1; // valid pcx packet
reg pcx6_atom_pq_d1; // atomic bit delayed by 1
reg pcx6_atom_pq_d2; // delayed by 2
reg pcx6_req_pq_d1; // OR of request bits delayed by 1
reg [5:0] pcx6_type_d1; // packet type delayed by 1
wire [4:0] spc7_pcx_req_pq = `TOP_MEMORY.spc7_pcx_req_pq[4:0];
wire spc7_pcx_atom_pq = `TOP_MEMORY.spc7_pcx_atom_pq;
wire [`PCX_WIDTH-1:0] spc7_pcx_data_pa = `TOP_MEMORY.spc7_pcx_data_pa[`PCX_WIDTH-1:0];
reg pcx7_vld_d1; // valid pcx packet
reg pcx7_atom_pq_d1; // atomic bit delayed by 1
reg pcx7_atom_pq_d2; // delayed by 2
reg pcx7_req_pq_d1; // OR of request bits delayed by 1
reg [5:0] pcx7_type_d1; // packet type delayed by 1
//--------------------------------------------------------------------------------------
// L2 tags tp cpx packets
//--------------------------------------------------------------------------------------
wire [7:0] sctag0_cpx_req_cq = `TOP_MEMORY.sctag0_cpx_req_cq[7:0];
wire [7:0] sctag0_cpx_atom_cq = `TOP_MEMORY.sctag0_cpx_atom_cq;
wire [`CPX_WIDTH-1:0] sctag0_cpx_data_ca = `TOP_MEMORY.sctag0_cpx_data_ca[`CPX_WIDTH-1:0];
wire sctag0_pcx_stall_pq = `TOP_MEMORY.sctag0_pcx_stall_pq;
reg [7:0] sctag0_cpx_req_cq_d1; // delayed by 1
reg [7:0] sctag0_cpx_req_cq_d2; // delayed by 2
reg [7:0] sctag0_cpx_atom_cq_d1; // delayed by 1
reg [7:0] sctag0_cpx_atom_cq_d2; // delayed by 2
reg [127:0] sctag0_cpx_type_str; // in string format
reg [3:0] sctag0_cpx_type; // packet type
reg sctag0_dc_lkup_c5;
reg sctag0_ic_lkup_c5;
reg sctag0_dc_lkup_c6;
reg sctag0_ic_lkup_c6;
wire [3:0] sctag0_dc_lkup_panel_dec_c4 = `TOP_MEMORY.sctag0.dirrep.dc_lkup_panel_dec_c4[3:0];
wire [3:0] sctag0_dc_lkup_row_dec_c4 = `TOP_MEMORY.sctag0.dirrep.dc_lkup_row_dec_c4[3:0];
wire [3:0] sctag0_ic_lkup_panel_dec_c4 = `TOP_MEMORY.sctag0.dirrep.ic_lkup_panel_dec_c4[3:0];
wire [3:0] sctag0_ic_lkup_row_dec_c4 = `TOP_MEMORY.sctag0.dirrep.ic_lkup_row_dec_c4[3:0];
wire [127:0] sctag0_dc_cam_hit_c6 = `TOP_MEMORY.sctag0.dirvec_dp.dc_cam_hit_c6[127:0];
wire [127:0] sctag0_ic_cam_hit_c6 = `TOP_MEMORY.sctag0.dirvec_dp.ic_cam_hit_c6[127:0];
//----------------------------------------------------------------------------------------
wire [2:0] sctag0_dc_cam_hit_c6_nibble0_sum = sctag0_dc_cam_hit_c6[0] + sctag0_dc_cam_hit_c6[1] +
sctag0_dc_cam_hit_c6[2] + sctag0_dc_cam_hit_c6[3];
wire [2:0] sctag0_ic_cam_hit_c6_nibble0_sum = sctag0_ic_cam_hit_c6[0] + sctag0_ic_cam_hit_c6[1] +
sctag0_ic_cam_hit_c6[2] + sctag0_ic_cam_hit_c6[3];
wire [3:0] sctag0_both_cam_hit_c6_nibble0_sum= sctag0_dc_cam_hit_c6[0] + sctag0_dc_cam_hit_c6[1] +
sctag0_dc_cam_hit_c6[2] + sctag0_dc_cam_hit_c6[3] +
sctag0_ic_cam_hit_c6[0] + sctag0_ic_cam_hit_c6[1] +
sctag0_ic_cam_hit_c6[2] + sctag0_ic_cam_hit_c6[3];
//----------------------------------------------------------------------------------------
wire [2:0] sctag0_dc_cam_hit_c6_nibble1_sum = sctag0_dc_cam_hit_c6[4] + sctag0_dc_cam_hit_c6[5] +
sctag0_dc_cam_hit_c6[6] + sctag0_dc_cam_hit_c6[7];
wire [2:0] sctag0_ic_cam_hit_c6_nibble1_sum = sctag0_ic_cam_hit_c6[4] + sctag0_ic_cam_hit_c6[5] +
sctag0_ic_cam_hit_c6[6] + sctag0_ic_cam_hit_c6[7];
wire [3:0] sctag0_both_cam_hit_c6_nibble1_sum= sctag0_dc_cam_hit_c6[4] + sctag0_dc_cam_hit_c6[5] +
sctag0_dc_cam_hit_c6[6] + sctag0_dc_cam_hit_c6[7] +
sctag0_ic_cam_hit_c6[4] + sctag0_ic_cam_hit_c6[5] +
sctag0_ic_cam_hit_c6[6] + sctag0_ic_cam_hit_c6[7];
//----------------------------------------------------------------------------------------
wire [2:0] sctag0_dc_cam_hit_c6_nibble2_sum = sctag0_dc_cam_hit_c6[8] + sctag0_dc_cam_hit_c6[9] +
sctag0_dc_cam_hit_c6[10] + sctag0_dc_cam_hit_c6[11];
wire [2:0] sctag0_ic_cam_hit_c6_nibble2_sum = sctag0_ic_cam_hit_c6[8] + sctag0_ic_cam_hit_c6[9] +
sctag0_ic_cam_hit_c6[10] + sctag0_ic_cam_hit_c6[11];
wire [3:0] sctag0_both_cam_hit_c6_nibble2_sum= sctag0_dc_cam_hit_c6[8] + sctag0_dc_cam_hit_c6[9] +
sctag0_dc_cam_hit_c6[10] + sctag0_dc_cam_hit_c6[11] +
sctag0_ic_cam_hit_c6[8] + sctag0_ic_cam_hit_c6[9] +
sctag0_ic_cam_hit_c6[10] + sctag0_ic_cam_hit_c6[11];
//----------------------------------------------------------------------------------------
wire [2:0] sctag0_dc_cam_hit_c6_nibble3_sum = sctag0_dc_cam_hit_c6[12] + sctag0_dc_cam_hit_c6[13] +
sctag0_dc_cam_hit_c6[14] + sctag0_dc_cam_hit_c6[15];
wire [2:0] sctag0_ic_cam_hit_c6_nibble3_sum = sctag0_ic_cam_hit_c6[12] + sctag0_ic_cam_hit_c6[13] +
sctag0_ic_cam_hit_c6[14] + sctag0_ic_cam_hit_c6[15];
wire [3:0] sctag0_both_cam_hit_c6_nibble3_sum= sctag0_dc_cam_hit_c6[12] + sctag0_dc_cam_hit_c6[13] +
sctag0_dc_cam_hit_c6[14] + sctag0_dc_cam_hit_c6[15] +
sctag0_ic_cam_hit_c6[12] + sctag0_ic_cam_hit_c6[13] +
sctag0_ic_cam_hit_c6[14] + sctag0_ic_cam_hit_c6[15];
//----------------------------------------------------------------------------------------
wire [2:0] sctag0_dc_cam_hit_c6_nibble4_sum = sctag0_dc_cam_hit_c6[16] + sctag0_dc_cam_hit_c6[17] +
sctag0_dc_cam_hit_c6[18] + sctag0_dc_cam_hit_c6[19];
wire [2:0] sctag0_ic_cam_hit_c6_nibble4_sum = sctag0_ic_cam_hit_c6[16] + sctag0_ic_cam_hit_c6[17] +
sctag0_ic_cam_hit_c6[18] + sctag0_ic_cam_hit_c6[19];
wire [3:0] sctag0_both_cam_hit_c6_nibble4_sum= sctag0_dc_cam_hit_c6[16] + sctag0_dc_cam_hit_c6[17] +
sctag0_dc_cam_hit_c6[18] + sctag0_dc_cam_hit_c6[19] +
sctag0_ic_cam_hit_c6[16] + sctag0_ic_cam_hit_c6[17] +
sctag0_ic_cam_hit_c6[18] + sctag0_ic_cam_hit_c6[19];
//----------------------------------------------------------------------------------------
wire [2:0] sctag0_dc_cam_hit_c6_nibble5_sum = sctag0_dc_cam_hit_c6[20] + sctag0_dc_cam_hit_c6[21] +
sctag0_dc_cam_hit_c6[22] + sctag0_dc_cam_hit_c6[23];
wire [2:0] sctag0_ic_cam_hit_c6_nibble5_sum = sctag0_ic_cam_hit_c6[20] + sctag0_ic_cam_hit_c6[21] +
sctag0_ic_cam_hit_c6[22] + sctag0_ic_cam_hit_c6[23];
wire [3:0] sctag0_both_cam_hit_c6_nibble5_sum= sctag0_dc_cam_hit_c6[20] + sctag0_dc_cam_hit_c6[21] +
sctag0_dc_cam_hit_c6[22] + sctag0_dc_cam_hit_c6[23] +
sctag0_ic_cam_hit_c6[20] + sctag0_ic_cam_hit_c6[21] +
sctag0_ic_cam_hit_c6[22] + sctag0_ic_cam_hit_c6[23];
//----------------------------------------------------------------------------------------
wire [2:0] sctag0_dc_cam_hit_c6_nibble6_sum = sctag0_dc_cam_hit_c6[24] + sctag0_dc_cam_hit_c6[25] +
sctag0_dc_cam_hit_c6[26] + sctag0_dc_cam_hit_c6[27];
wire [2:0] sctag0_ic_cam_hit_c6_nibble6_sum = sctag0_ic_cam_hit_c6[24] + sctag0_ic_cam_hit_c6[25] +
sctag0_ic_cam_hit_c6[26] + sctag0_ic_cam_hit_c6[27];
wire [3:0] sctag0_both_cam_hit_c6_nibble6_sum= sctag0_dc_cam_hit_c6[24] + sctag0_dc_cam_hit_c6[25] +
sctag0_dc_cam_hit_c6[26] + sctag0_dc_cam_hit_c6[27] +
sctag0_ic_cam_hit_c6[24] + sctag0_ic_cam_hit_c6[25] +
sctag0_ic_cam_hit_c6[26] + sctag0_ic_cam_hit_c6[27];
//----------------------------------------------------------------------------------------
wire [2:0] sctag0_dc_cam_hit_c6_nibble7_sum = sctag0_dc_cam_hit_c6[28] + sctag0_dc_cam_hit_c6[29] +
sctag0_dc_cam_hit_c6[30] + sctag0_dc_cam_hit_c6[31];
wire [2:0] sctag0_ic_cam_hit_c6_nibble7_sum = sctag0_ic_cam_hit_c6[28] + sctag0_ic_cam_hit_c6[29] +
sctag0_ic_cam_hit_c6[30] + sctag0_ic_cam_hit_c6[31];
wire [3:0] sctag0_both_cam_hit_c6_nibble7_sum= sctag0_dc_cam_hit_c6[28] + sctag0_dc_cam_hit_c6[29] +
sctag0_dc_cam_hit_c6[30] + sctag0_dc_cam_hit_c6[31] +
sctag0_ic_cam_hit_c6[28] + sctag0_ic_cam_hit_c6[29] +
sctag0_ic_cam_hit_c6[30] + sctag0_ic_cam_hit_c6[31];
//----------------------------------------------------------------------------------------
wire [2:0] sctag0_dc_cam_hit_c6_nibble8_sum = sctag0_dc_cam_hit_c6[32] + sctag0_dc_cam_hit_c6[33] +
sctag0_dc_cam_hit_c6[34] + sctag0_dc_cam_hit_c6[35];
wire [2:0] sctag0_ic_cam_hit_c6_nibble8_sum = sctag0_ic_cam_hit_c6[32] + sctag0_ic_cam_hit_c6[33] +
sctag0_ic_cam_hit_c6[34] + sctag0_ic_cam_hit_c6[35];
wire [3:0] sctag0_both_cam_hit_c6_nibble8_sum= sctag0_dc_cam_hit_c6[32] + sctag0_dc_cam_hit_c6[33] +
sctag0_dc_cam_hit_c6[34] + sctag0_dc_cam_hit_c6[35] +
sctag0_ic_cam_hit_c6[32] + sctag0_ic_cam_hit_c6[33] +
sctag0_ic_cam_hit_c6[34] + sctag0_ic_cam_hit_c6[35];
//----------------------------------------------------------------------------------------
wire [2:0] sctag0_dc_cam_hit_c6_nibble9_sum = sctag0_dc_cam_hit_c6[36] + sctag0_dc_cam_hit_c6[37] +
sctag0_dc_cam_hit_c6[38] + sctag0_dc_cam_hit_c6[39];
wire [2:0] sctag0_ic_cam_hit_c6_nibble9_sum = sctag0_ic_cam_hit_c6[36] + sctag0_ic_cam_hit_c6[37] +
sctag0_ic_cam_hit_c6[38] + sctag0_ic_cam_hit_c6[39];
wire [3:0] sctag0_both_cam_hit_c6_nibble9_sum= sctag0_dc_cam_hit_c6[36] + sctag0_dc_cam_hit_c6[37] +
sctag0_dc_cam_hit_c6[38] + sctag0_dc_cam_hit_c6[39] +
sctag0_ic_cam_hit_c6[36] + sctag0_ic_cam_hit_c6[37] +
sctag0_ic_cam_hit_c6[38] + sctag0_ic_cam_hit_c6[39];
//----------------------------------------------------------------------------------------
wire [2:0] sctag0_dc_cam_hit_c6_nibble10_sum = sctag0_dc_cam_hit_c6[40] + sctag0_dc_cam_hit_c6[41] +
sctag0_dc_cam_hit_c6[42] + sctag0_dc_cam_hit_c6[43];
wire [2:0] sctag0_ic_cam_hit_c6_nibble10_sum = sctag0_ic_cam_hit_c6[40] + sctag0_ic_cam_hit_c6[41] +
sctag0_ic_cam_hit_c6[42] + sctag0_ic_cam_hit_c6[43];
wire [3:0] sctag0_both_cam_hit_c6_nibble10_sum= sctag0_dc_cam_hit_c6[40] + sctag0_dc_cam_hit_c6[41] +
sctag0_dc_cam_hit_c6[42] + sctag0_dc_cam_hit_c6[43] +
sctag0_ic_cam_hit_c6[40] + sctag0_ic_cam_hit_c6[41] +
sctag0_ic_cam_hit_c6[42] + sctag0_ic_cam_hit_c6[43];
//----------------------------------------------------------------------------------------
wire [2:0] sctag0_dc_cam_hit_c6_nibble11_sum = sctag0_dc_cam_hit_c6[44] + sctag0_dc_cam_hit_c6[45] +
sctag0_dc_cam_hit_c6[46] + sctag0_dc_cam_hit_c6[47];
wire [2:0] sctag0_ic_cam_hit_c6_nibble11_sum = sctag0_ic_cam_hit_c6[44] + sctag0_ic_cam_hit_c6[45] +
sctag0_ic_cam_hit_c6[46] + sctag0_ic_cam_hit_c6[47];
wire [3:0] sctag0_both_cam_hit_c6_nibble11_sum= sctag0_dc_cam_hit_c6[44] + sctag0_dc_cam_hit_c6[45] +
sctag0_dc_cam_hit_c6[46] + sctag0_dc_cam_hit_c6[47] +
sctag0_ic_cam_hit_c6[44] + sctag0_ic_cam_hit_c6[45] +
sctag0_ic_cam_hit_c6[46] + sctag0_ic_cam_hit_c6[47];
//----------------------------------------------------------------------------------------
wire [2:0] sctag0_dc_cam_hit_c6_nibble12_sum = sctag0_dc_cam_hit_c6[48] + sctag0_dc_cam_hit_c6[49] +
sctag0_dc_cam_hit_c6[50] + sctag0_dc_cam_hit_c6[51];
wire [2:0] sctag0_ic_cam_hit_c6_nibble12_sum = sctag0_ic_cam_hit_c6[48] + sctag0_ic_cam_hit_c6[49] +
sctag0_ic_cam_hit_c6[50] + sctag0_ic_cam_hit_c6[51];
wire [3:0] sctag0_both_cam_hit_c6_nibble12_sum= sctag0_dc_cam_hit_c6[48] + sctag0_dc_cam_hit_c6[49] +
sctag0_dc_cam_hit_c6[50] + sctag0_dc_cam_hit_c6[51] +
sctag0_ic_cam_hit_c6[48] + sctag0_ic_cam_hit_c6[49] +
sctag0_ic_cam_hit_c6[50] + sctag0_ic_cam_hit_c6[51];
//----------------------------------------------------------------------------------------
wire [2:0] sctag0_dc_cam_hit_c6_nibble13_sum = sctag0_dc_cam_hit_c6[52] + sctag0_dc_cam_hit_c6[53] +
sctag0_dc_cam_hit_c6[54] + sctag0_dc_cam_hit_c6[55];
wire [2:0] sctag0_ic_cam_hit_c6_nibble13_sum = sctag0_ic_cam_hit_c6[52] + sctag0_ic_cam_hit_c6[53] +
sctag0_ic_cam_hit_c6[54] + sctag0_ic_cam_hit_c6[55];
wire [3:0] sctag0_both_cam_hit_c6_nibble13_sum= sctag0_dc_cam_hit_c6[52] + sctag0_dc_cam_hit_c6[53] +
sctag0_dc_cam_hit_c6[54] + sctag0_dc_cam_hit_c6[55] +
sctag0_ic_cam_hit_c6[52] + sctag0_ic_cam_hit_c6[53] +
sctag0_ic_cam_hit_c6[54] + sctag0_ic_cam_hit_c6[55];
//----------------------------------------------------------------------------------------
wire [2:0] sctag0_dc_cam_hit_c6_nibble14_sum = sctag0_dc_cam_hit_c6[56] + sctag0_dc_cam_hit_c6[57] +
sctag0_dc_cam_hit_c6[58] + sctag0_dc_cam_hit_c6[59];
wire [2:0] sctag0_ic_cam_hit_c6_nibble14_sum = sctag0_ic_cam_hit_c6[56] + sctag0_ic_cam_hit_c6[57] +
sctag0_ic_cam_hit_c6[58] + sctag0_ic_cam_hit_c6[59];
wire [3:0] sctag0_both_cam_hit_c6_nibble14_sum= sctag0_dc_cam_hit_c6[56] + sctag0_dc_cam_hit_c6[57] +
sctag0_dc_cam_hit_c6[58] + sctag0_dc_cam_hit_c6[59] +
sctag0_ic_cam_hit_c6[56] + sctag0_ic_cam_hit_c6[57] +
sctag0_ic_cam_hit_c6[58] + sctag0_ic_cam_hit_c6[59];
//----------------------------------------------------------------------------------------
wire [2:0] sctag0_dc_cam_hit_c6_nibble15_sum = sctag0_dc_cam_hit_c6[60] + sctag0_dc_cam_hit_c6[61] +
sctag0_dc_cam_hit_c6[62] + sctag0_dc_cam_hit_c6[63];
wire [2:0] sctag0_ic_cam_hit_c6_nibble15_sum = sctag0_ic_cam_hit_c6[60] + sctag0_ic_cam_hit_c6[61] +
sctag0_ic_cam_hit_c6[62] + sctag0_ic_cam_hit_c6[63];
wire [3:0] sctag0_both_cam_hit_c6_nibble15_sum= sctag0_dc_cam_hit_c6[60] + sctag0_dc_cam_hit_c6[61] +
sctag0_dc_cam_hit_c6[62] + sctag0_dc_cam_hit_c6[63] +
sctag0_ic_cam_hit_c6[60] + sctag0_ic_cam_hit_c6[61] +
sctag0_ic_cam_hit_c6[62] + sctag0_ic_cam_hit_c6[63];
//----------------------------------------------------------------------------------------
wire [2:0] sctag0_dc_cam_hit_c6_nibble16_sum = sctag0_dc_cam_hit_c6[64] + sctag0_dc_cam_hit_c6[65] +
sctag0_dc_cam_hit_c6[66] + sctag0_dc_cam_hit_c6[67];
wire [2:0] sctag0_ic_cam_hit_c6_nibble16_sum = sctag0_ic_cam_hit_c6[64] + sctag0_ic_cam_hit_c6[65] +
sctag0_ic_cam_hit_c6[66] + sctag0_ic_cam_hit_c6[67];
wire [3:0] sctag0_both_cam_hit_c6_nibble16_sum= sctag0_dc_cam_hit_c6[64] + sctag0_dc_cam_hit_c6[65] +
sctag0_dc_cam_hit_c6[66] + sctag0_dc_cam_hit_c6[67] +
sctag0_ic_cam_hit_c6[64] + sctag0_ic_cam_hit_c6[65] +
sctag0_ic_cam_hit_c6[66] + sctag0_ic_cam_hit_c6[67];
//----------------------------------------------------------------------------------------
wire [2:0] sctag0_dc_cam_hit_c6_nibble17_sum = sctag0_dc_cam_hit_c6[68] + sctag0_dc_cam_hit_c6[69] +
sctag0_dc_cam_hit_c6[70] + sctag0_dc_cam_hit_c6[71];
wire [2:0] sctag0_ic_cam_hit_c6_nibble17_sum = sctag0_ic_cam_hit_c6[68] + sctag0_ic_cam_hit_c6[69] +
sctag0_ic_cam_hit_c6[70] + sctag0_ic_cam_hit_c6[71];
wire [3:0] sctag0_both_cam_hit_c6_nibble17_sum= sctag0_dc_cam_hit_c6[68] + sctag0_dc_cam_hit_c6[69] +
sctag0_dc_cam_hit_c6[70] + sctag0_dc_cam_hit_c6[71] +
sctag0_ic_cam_hit_c6[68] + sctag0_ic_cam_hit_c6[69] +
sctag0_ic_cam_hit_c6[70] + sctag0_ic_cam_hit_c6[71];
//----------------------------------------------------------------------------------------
wire [2:0] sctag0_dc_cam_hit_c6_nibble18_sum = sctag0_dc_cam_hit_c6[72] + sctag0_dc_cam_hit_c6[73] +
sctag0_dc_cam_hit_c6[74] + sctag0_dc_cam_hit_c6[75];
wire [2:0] sctag0_ic_cam_hit_c6_nibble18_sum = sctag0_ic_cam_hit_c6[72] + sctag0_ic_cam_hit_c6[73] +
sctag0_ic_cam_hit_c6[74] + sctag0_ic_cam_hit_c6[75];
wire [3:0] sctag0_both_cam_hit_c6_nibble18_sum= sctag0_dc_cam_hit_c6[72] + sctag0_dc_cam_hit_c6[73] +
sctag0_dc_cam_hit_c6[74] + sctag0_dc_cam_hit_c6[75] +
sctag0_ic_cam_hit_c6[72] + sctag0_ic_cam_hit_c6[73] +
sctag0_ic_cam_hit_c6[74] + sctag0_ic_cam_hit_c6[75];
//----------------------------------------------------------------------------------------
wire [2:0] sctag0_dc_cam_hit_c6_nibble19_sum = sctag0_dc_cam_hit_c6[76] + sctag0_dc_cam_hit_c6[77] +
sctag0_dc_cam_hit_c6[78] + sctag0_dc_cam_hit_c6[79];
wire [2:0] sctag0_ic_cam_hit_c6_nibble19_sum = sctag0_ic_cam_hit_c6[76] + sctag0_ic_cam_hit_c6[77] +
sctag0_ic_cam_hit_c6[78] + sctag0_ic_cam_hit_c6[79];
wire [3:0] sctag0_both_cam_hit_c6_nibble19_sum= sctag0_dc_cam_hit_c6[76] + sctag0_dc_cam_hit_c6[77] +
sctag0_dc_cam_hit_c6[78] + sctag0_dc_cam_hit_c6[79] +
sctag0_ic_cam_hit_c6[76] + sctag0_ic_cam_hit_c6[77] +
sctag0_ic_cam_hit_c6[78] + sctag0_ic_cam_hit_c6[79];
//----------------------------------------------------------------------------------------
wire [2:0] sctag0_dc_cam_hit_c6_nibble20_sum = sctag0_dc_cam_hit_c6[80] + sctag0_dc_cam_hit_c6[81] +
sctag0_dc_cam_hit_c6[82] + sctag0_dc_cam_hit_c6[83];
wire [2:0] sctag0_ic_cam_hit_c6_nibble20_sum = sctag0_ic_cam_hit_c6[80] + sctag0_ic_cam_hit_c6[81] +
sctag0_ic_cam_hit_c6[82] + sctag0_ic_cam_hit_c6[83];
wire [3:0] sctag0_both_cam_hit_c6_nibble20_sum= sctag0_dc_cam_hit_c6[80] + sctag0_dc_cam_hit_c6[81] +
sctag0_dc_cam_hit_c6[82] + sctag0_dc_cam_hit_c6[83] +
sctag0_ic_cam_hit_c6[80] + sctag0_ic_cam_hit_c6[81] +
sctag0_ic_cam_hit_c6[82] + sctag0_ic_cam_hit_c6[83];
//----------------------------------------------------------------------------------------
wire [2:0] sctag0_dc_cam_hit_c6_nibble21_sum = sctag0_dc_cam_hit_c6[84] + sctag0_dc_cam_hit_c6[85] +
sctag0_dc_cam_hit_c6[86] + sctag0_dc_cam_hit_c6[87];
wire [2:0] sctag0_ic_cam_hit_c6_nibble21_sum = sctag0_ic_cam_hit_c6[84] + sctag0_ic_cam_hit_c6[85] +
sctag0_ic_cam_hit_c6[86] + sctag0_ic_cam_hit_c6[87];
wire [3:0] sctag0_both_cam_hit_c6_nibble21_sum= sctag0_dc_cam_hit_c6[84] + sctag0_dc_cam_hit_c6[85] +
sctag0_dc_cam_hit_c6[86] + sctag0_dc_cam_hit_c6[87] +
sctag0_ic_cam_hit_c6[84] + sctag0_ic_cam_hit_c6[85] +
sctag0_ic_cam_hit_c6[86] + sctag0_ic_cam_hit_c6[87];
//----------------------------------------------------------------------------------------
wire [2:0] sctag0_dc_cam_hit_c6_nibble22_sum = sctag0_dc_cam_hit_c6[88] + sctag0_dc_cam_hit_c6[89] +
sctag0_dc_cam_hit_c6[90] + sctag0_dc_cam_hit_c6[91];
wire [2:0] sctag0_ic_cam_hit_c6_nibble22_sum = sctag0_ic_cam_hit_c6[88] + sctag0_ic_cam_hit_c6[89] +
sctag0_ic_cam_hit_c6[90] + sctag0_ic_cam_hit_c6[91];
wire [3:0] sctag0_both_cam_hit_c6_nibble22_sum= sctag0_dc_cam_hit_c6[88] + sctag0_dc_cam_hit_c6[89] +
sctag0_dc_cam_hit_c6[90] + sctag0_dc_cam_hit_c6[91] +
sctag0_ic_cam_hit_c6[88] + sctag0_ic_cam_hit_c6[89] +
sctag0_ic_cam_hit_c6[90] + sctag0_ic_cam_hit_c6[91];
//----------------------------------------------------------------------------------------
wire [2:0] sctag0_dc_cam_hit_c6_nibble23_sum = sctag0_dc_cam_hit_c6[92] + sctag0_dc_cam_hit_c6[93] +
sctag0_dc_cam_hit_c6[94] + sctag0_dc_cam_hit_c6[95];
wire [2:0] sctag0_ic_cam_hit_c6_nibble23_sum = sctag0_ic_cam_hit_c6[92] + sctag0_ic_cam_hit_c6[93] +
sctag0_ic_cam_hit_c6[94] + sctag0_ic_cam_hit_c6[95];
wire [3:0] sctag0_both_cam_hit_c6_nibble23_sum= sctag0_dc_cam_hit_c6[92] + sctag0_dc_cam_hit_c6[93] +
sctag0_dc_cam_hit_c6[94] + sctag0_dc_cam_hit_c6[95] +
sctag0_ic_cam_hit_c6[92] + sctag0_ic_cam_hit_c6[93] +
sctag0_ic_cam_hit_c6[94] + sctag0_ic_cam_hit_c6[95];
//----------------------------------------------------------------------------------------
wire [2:0] sctag0_dc_cam_hit_c6_nibble24_sum = sctag0_dc_cam_hit_c6[96] + sctag0_dc_cam_hit_c6[97] +
sctag0_dc_cam_hit_c6[98] + sctag0_dc_cam_hit_c6[99];
wire [2:0] sctag0_ic_cam_hit_c6_nibble24_sum = sctag0_ic_cam_hit_c6[96] + sctag0_ic_cam_hit_c6[97] +
sctag0_ic_cam_hit_c6[98] + sctag0_ic_cam_hit_c6[99];
wire [3:0] sctag0_both_cam_hit_c6_nibble24_sum= sctag0_dc_cam_hit_c6[96] + sctag0_dc_cam_hit_c6[97] +
sctag0_dc_cam_hit_c6[98] + sctag0_dc_cam_hit_c6[99] +
sctag0_ic_cam_hit_c6[96] + sctag0_ic_cam_hit_c6[97] +
sctag0_ic_cam_hit_c6[98] + sctag0_ic_cam_hit_c6[99];
//----------------------------------------------------------------------------------------
wire [2:0] sctag0_dc_cam_hit_c6_nibble25_sum = sctag0_dc_cam_hit_c6[100] + sctag0_dc_cam_hit_c6[101] +
sctag0_dc_cam_hit_c6[102] + sctag0_dc_cam_hit_c6[103];
wire [2:0] sctag0_ic_cam_hit_c6_nibble25_sum = sctag0_ic_cam_hit_c6[100] + sctag0_ic_cam_hit_c6[101] +
sctag0_ic_cam_hit_c6[102] + sctag0_ic_cam_hit_c6[103];
wire [3:0] sctag0_both_cam_hit_c6_nibble25_sum= sctag0_dc_cam_hit_c6[100] + sctag0_dc_cam_hit_c6[101] +
sctag0_dc_cam_hit_c6[102] + sctag0_dc_cam_hit_c6[103] +
sctag0_ic_cam_hit_c6[100] + sctag0_ic_cam_hit_c6[101] +
sctag0_ic_cam_hit_c6[102] + sctag0_ic_cam_hit_c6[103];
//----------------------------------------------------------------------------------------
wire [2:0] sctag0_dc_cam_hit_c6_nibble26_sum = sctag0_dc_cam_hit_c6[104] + sctag0_dc_cam_hit_c6[105] +
sctag0_dc_cam_hit_c6[106] + sctag0_dc_cam_hit_c6[107];
wire [2:0] sctag0_ic_cam_hit_c6_nibble26_sum = sctag0_ic_cam_hit_c6[104] + sctag0_ic_cam_hit_c6[105] +
sctag0_ic_cam_hit_c6[106] + sctag0_ic_cam_hit_c6[107];
wire [3:0] sctag0_both_cam_hit_c6_nibble26_sum= sctag0_dc_cam_hit_c6[104] + sctag0_dc_cam_hit_c6[105] +
sctag0_dc_cam_hit_c6[106] + sctag0_dc_cam_hit_c6[107] +
sctag0_ic_cam_hit_c6[104] + sctag0_ic_cam_hit_c6[105] +
sctag0_ic_cam_hit_c6[106] + sctag0_ic_cam_hit_c6[107];
//----------------------------------------------------------------------------------------
wire [2:0] sctag0_dc_cam_hit_c6_nibble27_sum = sctag0_dc_cam_hit_c6[108] + sctag0_dc_cam_hit_c6[109] +
sctag0_dc_cam_hit_c6[110] + sctag0_dc_cam_hit_c6[111];
wire [2:0] sctag0_ic_cam_hit_c6_nibble27_sum = sctag0_ic_cam_hit_c6[108] + sctag0_ic_cam_hit_c6[109] +
sctag0_ic_cam_hit_c6[110] + sctag0_ic_cam_hit_c6[111];
wire [3:0] sctag0_both_cam_hit_c6_nibble27_sum= sctag0_dc_cam_hit_c6[108] + sctag0_dc_cam_hit_c6[109] +
sctag0_dc_cam_hit_c6[110] + sctag0_dc_cam_hit_c6[111] +
sctag0_ic_cam_hit_c6[108] + sctag0_ic_cam_hit_c6[109] +
sctag0_ic_cam_hit_c6[110] + sctag0_ic_cam_hit_c6[111];
//----------------------------------------------------------------------------------------
wire [2:0] sctag0_dc_cam_hit_c6_nibble28_sum = sctag0_dc_cam_hit_c6[112] + sctag0_dc_cam_hit_c6[113] +
sctag0_dc_cam_hit_c6[114] + sctag0_dc_cam_hit_c6[115];
wire [2:0] sctag0_ic_cam_hit_c6_nibble28_sum = sctag0_ic_cam_hit_c6[112] + sctag0_ic_cam_hit_c6[113] +
sctag0_ic_cam_hit_c6[114] + sctag0_ic_cam_hit_c6[115];
wire [3:0] sctag0_both_cam_hit_c6_nibble28_sum= sctag0_dc_cam_hit_c6[112] + sctag0_dc_cam_hit_c6[113] +
sctag0_dc_cam_hit_c6[114] + sctag0_dc_cam_hit_c6[115] +
sctag0_ic_cam_hit_c6[112] + sctag0_ic_cam_hit_c6[113] +
sctag0_ic_cam_hit_c6[114] + sctag0_ic_cam_hit_c6[115];
//----------------------------------------------------------------------------------------
wire [2:0] sctag0_dc_cam_hit_c6_nibble29_sum = sctag0_dc_cam_hit_c6[116] + sctag0_dc_cam_hit_c6[117] +
sctag0_dc_cam_hit_c6[118] + sctag0_dc_cam_hit_c6[119];
wire [2:0] sctag0_ic_cam_hit_c6_nibble29_sum = sctag0_ic_cam_hit_c6[116] + sctag0_ic_cam_hit_c6[117] +
sctag0_ic_cam_hit_c6[118] + sctag0_ic_cam_hit_c6[119];
wire [3:0] sctag0_both_cam_hit_c6_nibble29_sum= sctag0_dc_cam_hit_c6[116] + sctag0_dc_cam_hit_c6[117] +
sctag0_dc_cam_hit_c6[118] + sctag0_dc_cam_hit_c6[119] +
sctag0_ic_cam_hit_c6[116] + sctag0_ic_cam_hit_c6[117] +
sctag0_ic_cam_hit_c6[118] + sctag0_ic_cam_hit_c6[119];
//----------------------------------------------------------------------------------------
wire [2:0] sctag0_dc_cam_hit_c6_nibble30_sum = sctag0_dc_cam_hit_c6[120] + sctag0_dc_cam_hit_c6[121] +
sctag0_dc_cam_hit_c6[122] + sctag0_dc_cam_hit_c6[123];
wire [2:0] sctag0_ic_cam_hit_c6_nibble30_sum = sctag0_ic_cam_hit_c6[120] + sctag0_ic_cam_hit_c6[121] +
sctag0_ic_cam_hit_c6[122] + sctag0_ic_cam_hit_c6[123];
wire [3:0] sctag0_both_cam_hit_c6_nibble30_sum= sctag0_dc_cam_hit_c6[120] + sctag0_dc_cam_hit_c6[121] +
sctag0_dc_cam_hit_c6[122] + sctag0_dc_cam_hit_c6[123] +
sctag0_ic_cam_hit_c6[120] + sctag0_ic_cam_hit_c6[121] +
sctag0_ic_cam_hit_c6[122] + sctag0_ic_cam_hit_c6[123];
//----------------------------------------------------------------------------------------
wire [2:0] sctag0_dc_cam_hit_c6_nibble31_sum = sctag0_dc_cam_hit_c6[124] + sctag0_dc_cam_hit_c6[125] +
sctag0_dc_cam_hit_c6[126] + sctag0_dc_cam_hit_c6[127];
wire [2:0] sctag0_ic_cam_hit_c6_nibble31_sum = sctag0_ic_cam_hit_c6[124] + sctag0_ic_cam_hit_c6[125] +
sctag0_ic_cam_hit_c6[126] + sctag0_ic_cam_hit_c6[127];
wire [3:0] sctag0_both_cam_hit_c6_nibble31_sum= sctag0_dc_cam_hit_c6[124] + sctag0_dc_cam_hit_c6[125] +
sctag0_dc_cam_hit_c6[126] + sctag0_dc_cam_hit_c6[127] +
sctag0_ic_cam_hit_c6[124] + sctag0_ic_cam_hit_c6[125] +
sctag0_ic_cam_hit_c6[126] + sctag0_ic_cam_hit_c6[127];
wire [7:0] sctag1_cpx_req_cq = `TOP_MEMORY.sctag1_cpx_req_cq[7:0];
wire [7:0] sctag1_cpx_atom_cq = `TOP_MEMORY.sctag1_cpx_atom_cq;
wire [`CPX_WIDTH-1:0] sctag1_cpx_data_ca = `TOP_MEMORY.sctag1_cpx_data_ca[`CPX_WIDTH-1:0];
wire sctag1_pcx_stall_pq = `TOP_MEMORY.sctag1_pcx_stall_pq;
reg [7:0] sctag1_cpx_req_cq_d1; // delayed by 1
reg [7:0] sctag1_cpx_req_cq_d2; // delayed by 2
reg [7:0] sctag1_cpx_atom_cq_d1; // delayed by 1
reg [7:0] sctag1_cpx_atom_cq_d2; // delayed by 2
reg [127:0] sctag1_cpx_type_str; // in string format
reg [3:0] sctag1_cpx_type; // packet type
reg sctag1_dc_lkup_c5;
reg sctag1_ic_lkup_c5;
reg sctag1_dc_lkup_c6;
reg sctag1_ic_lkup_c6;
wire [3:0] sctag1_dc_lkup_panel_dec_c4 = `TOP_MEMORY.sctag1.dirrep.dc_lkup_panel_dec_c4[3:0];
wire [3:0] sctag1_dc_lkup_row_dec_c4 = `TOP_MEMORY.sctag1.dirrep.dc_lkup_row_dec_c4[3:0];
wire [3:0] sctag1_ic_lkup_panel_dec_c4 = `TOP_MEMORY.sctag1.dirrep.ic_lkup_panel_dec_c4[3:0];
wire [3:0] sctag1_ic_lkup_row_dec_c4 = `TOP_MEMORY.sctag1.dirrep.ic_lkup_row_dec_c4[3:0];
wire [127:0] sctag1_dc_cam_hit_c6 = `TOP_MEMORY.sctag1.dirvec_dp.dc_cam_hit_c6[127:0];
wire [127:0] sctag1_ic_cam_hit_c6 = `TOP_MEMORY.sctag1.dirvec_dp.ic_cam_hit_c6[127:0];
//----------------------------------------------------------------------------------------
wire [2:0] sctag1_dc_cam_hit_c6_nibble0_sum = sctag1_dc_cam_hit_c6[0] + sctag1_dc_cam_hit_c6[1] +
sctag1_dc_cam_hit_c6[2] + sctag1_dc_cam_hit_c6[3];
wire [2:0] sctag1_ic_cam_hit_c6_nibble0_sum = sctag1_ic_cam_hit_c6[0] + sctag1_ic_cam_hit_c6[1] +
sctag1_ic_cam_hit_c6[2] + sctag1_ic_cam_hit_c6[3];
wire [3:0] sctag1_both_cam_hit_c6_nibble0_sum= sctag1_dc_cam_hit_c6[0] + sctag1_dc_cam_hit_c6[1] +
sctag1_dc_cam_hit_c6[2] + sctag1_dc_cam_hit_c6[3] +
sctag1_ic_cam_hit_c6[0] + sctag1_ic_cam_hit_c6[1] +
sctag1_ic_cam_hit_c6[2] + sctag1_ic_cam_hit_c6[3];
//----------------------------------------------------------------------------------------
wire [2:0] sctag1_dc_cam_hit_c6_nibble1_sum = sctag1_dc_cam_hit_c6[4] + sctag1_dc_cam_hit_c6[5] +
sctag1_dc_cam_hit_c6[6] + sctag1_dc_cam_hit_c6[7];
wire [2:0] sctag1_ic_cam_hit_c6_nibble1_sum = sctag1_ic_cam_hit_c6[4] + sctag1_ic_cam_hit_c6[5] +
sctag1_ic_cam_hit_c6[6] + sctag1_ic_cam_hit_c6[7];
wire [3:0] sctag1_both_cam_hit_c6_nibble1_sum= sctag1_dc_cam_hit_c6[4] + sctag1_dc_cam_hit_c6[5] +
sctag1_dc_cam_hit_c6[6] + sctag1_dc_cam_hit_c6[7] +
sctag1_ic_cam_hit_c6[4] + sctag1_ic_cam_hit_c6[5] +
sctag1_ic_cam_hit_c6[6] + sctag1_ic_cam_hit_c6[7];
//----------------------------------------------------------------------------------------
wire [2:0] sctag1_dc_cam_hit_c6_nibble2_sum = sctag1_dc_cam_hit_c6[8] + sctag1_dc_cam_hit_c6[9] +
sctag1_dc_cam_hit_c6[10] + sctag1_dc_cam_hit_c6[11];
wire [2:0] sctag1_ic_cam_hit_c6_nibble2_sum = sctag1_ic_cam_hit_c6[8] + sctag1_ic_cam_hit_c6[9] +
sctag1_ic_cam_hit_c6[10] + sctag1_ic_cam_hit_c6[11];
wire [3:0] sctag1_both_cam_hit_c6_nibble2_sum= sctag1_dc_cam_hit_c6[8] + sctag1_dc_cam_hit_c6[9] +
sctag1_dc_cam_hit_c6[10] + sctag1_dc_cam_hit_c6[11] +
sctag1_ic_cam_hit_c6[8] + sctag1_ic_cam_hit_c6[9] +
sctag1_ic_cam_hit_c6[10] + sctag1_ic_cam_hit_c6[11];
//----------------------------------------------------------------------------------------
wire [2:0] sctag1_dc_cam_hit_c6_nibble3_sum = sctag1_dc_cam_hit_c6[12] + sctag1_dc_cam_hit_c6[13] +
sctag1_dc_cam_hit_c6[14] + sctag1_dc_cam_hit_c6[15];
wire [2:0] sctag1_ic_cam_hit_c6_nibble3_sum = sctag1_ic_cam_hit_c6[12] + sctag1_ic_cam_hit_c6[13] +
sctag1_ic_cam_hit_c6[14] + sctag1_ic_cam_hit_c6[15];
wire [3:0] sctag1_both_cam_hit_c6_nibble3_sum= sctag1_dc_cam_hit_c6[12] + sctag1_dc_cam_hit_c6[13] +
sctag1_dc_cam_hit_c6[14] + sctag1_dc_cam_hit_c6[15] +
sctag1_ic_cam_hit_c6[12] + sctag1_ic_cam_hit_c6[13] +
sctag1_ic_cam_hit_c6[14] + sctag1_ic_cam_hit_c6[15];
//----------------------------------------------------------------------------------------
wire [2:0] sctag1_dc_cam_hit_c6_nibble4_sum = sctag1_dc_cam_hit_c6[16] + sctag1_dc_cam_hit_c6[17] +
sctag1_dc_cam_hit_c6[18] + sctag1_dc_cam_hit_c6[19];
wire [2:0] sctag1_ic_cam_hit_c6_nibble4_sum = sctag1_ic_cam_hit_c6[16] + sctag1_ic_cam_hit_c6[17] +
sctag1_ic_cam_hit_c6[18] + sctag1_ic_cam_hit_c6[19];
wire [3:0] sctag1_both_cam_hit_c6_nibble4_sum= sctag1_dc_cam_hit_c6[16] + sctag1_dc_cam_hit_c6[17] +
sctag1_dc_cam_hit_c6[18] + sctag1_dc_cam_hit_c6[19] +
sctag1_ic_cam_hit_c6[16] + sctag1_ic_cam_hit_c6[17] +
sctag1_ic_cam_hit_c6[18] + sctag1_ic_cam_hit_c6[19];
//----------------------------------------------------------------------------------------
wire [2:0] sctag1_dc_cam_hit_c6_nibble5_sum = sctag1_dc_cam_hit_c6[20] + sctag1_dc_cam_hit_c6[21] +
sctag1_dc_cam_hit_c6[22] + sctag1_dc_cam_hit_c6[23];
wire [2:0] sctag1_ic_cam_hit_c6_nibble5_sum = sctag1_ic_cam_hit_c6[20] + sctag1_ic_cam_hit_c6[21] +
sctag1_ic_cam_hit_c6[22] + sctag1_ic_cam_hit_c6[23];
wire [3:0] sctag1_both_cam_hit_c6_nibble5_sum= sctag1_dc_cam_hit_c6[20] + sctag1_dc_cam_hit_c6[21] +
sctag1_dc_cam_hit_c6[22] + sctag1_dc_cam_hit_c6[23] +
sctag1_ic_cam_hit_c6[20] + sctag1_ic_cam_hit_c6[21] +
sctag1_ic_cam_hit_c6[22] + sctag1_ic_cam_hit_c6[23];
//----------------------------------------------------------------------------------------
wire [2:0] sctag1_dc_cam_hit_c6_nibble6_sum = sctag1_dc_cam_hit_c6[24] + sctag1_dc_cam_hit_c6[25] +
sctag1_dc_cam_hit_c6[26] + sctag1_dc_cam_hit_c6[27];
wire [2:0] sctag1_ic_cam_hit_c6_nibble6_sum = sctag1_ic_cam_hit_c6[24] + sctag1_ic_cam_hit_c6[25] +
sctag1_ic_cam_hit_c6[26] + sctag1_ic_cam_hit_c6[27];
wire [3:0] sctag1_both_cam_hit_c6_nibble6_sum= sctag1_dc_cam_hit_c6[24] + sctag1_dc_cam_hit_c6[25] +
sctag1_dc_cam_hit_c6[26] + sctag1_dc_cam_hit_c6[27] +
sctag1_ic_cam_hit_c6[24] + sctag1_ic_cam_hit_c6[25] +
sctag1_ic_cam_hit_c6[26] + sctag1_ic_cam_hit_c6[27];
//----------------------------------------------------------------------------------------
wire [2:0] sctag1_dc_cam_hit_c6_nibble7_sum = sctag1_dc_cam_hit_c6[28] + sctag1_dc_cam_hit_c6[29] +
sctag1_dc_cam_hit_c6[30] + sctag1_dc_cam_hit_c6[31];
wire [2:0] sctag1_ic_cam_hit_c6_nibble7_sum = sctag1_ic_cam_hit_c6[28] + sctag1_ic_cam_hit_c6[29] +
sctag1_ic_cam_hit_c6[30] + sctag1_ic_cam_hit_c6[31];
wire [3:0] sctag1_both_cam_hit_c6_nibble7_sum= sctag1_dc_cam_hit_c6[28] + sctag1_dc_cam_hit_c6[29] +
sctag1_dc_cam_hit_c6[30] + sctag1_dc_cam_hit_c6[31] +
sctag1_ic_cam_hit_c6[28] + sctag1_ic_cam_hit_c6[29] +
sctag1_ic_cam_hit_c6[30] + sctag1_ic_cam_hit_c6[31];
//----------------------------------------------------------------------------------------
wire [2:0] sctag1_dc_cam_hit_c6_nibble8_sum = sctag1_dc_cam_hit_c6[32] + sctag1_dc_cam_hit_c6[33] +
sctag1_dc_cam_hit_c6[34] + sctag1_dc_cam_hit_c6[35];
wire [2:0] sctag1_ic_cam_hit_c6_nibble8_sum = sctag1_ic_cam_hit_c6[32] + sctag1_ic_cam_hit_c6[33] +
sctag1_ic_cam_hit_c6[34] + sctag1_ic_cam_hit_c6[35];
wire [3:0] sctag1_both_cam_hit_c6_nibble8_sum= sctag1_dc_cam_hit_c6[32] + sctag1_dc_cam_hit_c6[33] +
sctag1_dc_cam_hit_c6[34] + sctag1_dc_cam_hit_c6[35] +
sctag1_ic_cam_hit_c6[32] + sctag1_ic_cam_hit_c6[33] +
sctag1_ic_cam_hit_c6[34] + sctag1_ic_cam_hit_c6[35];
//----------------------------------------------------------------------------------------
wire [2:0] sctag1_dc_cam_hit_c6_nibble9_sum = sctag1_dc_cam_hit_c6[36] + sctag1_dc_cam_hit_c6[37] +
sctag1_dc_cam_hit_c6[38] + sctag1_dc_cam_hit_c6[39];
wire [2:0] sctag1_ic_cam_hit_c6_nibble9_sum = sctag1_ic_cam_hit_c6[36] + sctag1_ic_cam_hit_c6[37] +
sctag1_ic_cam_hit_c6[38] + sctag1_ic_cam_hit_c6[39];
wire [3:0] sctag1_both_cam_hit_c6_nibble9_sum= sctag1_dc_cam_hit_c6[36] + sctag1_dc_cam_hit_c6[37] +
sctag1_dc_cam_hit_c6[38] + sctag1_dc_cam_hit_c6[39] +
sctag1_ic_cam_hit_c6[36] + sctag1_ic_cam_hit_c6[37] +
sctag1_ic_cam_hit_c6[38] + sctag1_ic_cam_hit_c6[39];
//----------------------------------------------------------------------------------------
wire [2:0] sctag1_dc_cam_hit_c6_nibble10_sum = sctag1_dc_cam_hit_c6[40] + sctag1_dc_cam_hit_c6[41] +
sctag1_dc_cam_hit_c6[42] + sctag1_dc_cam_hit_c6[43];
wire [2:0] sctag1_ic_cam_hit_c6_nibble10_sum = sctag1_ic_cam_hit_c6[40] + sctag1_ic_cam_hit_c6[41] +
sctag1_ic_cam_hit_c6[42] + sctag1_ic_cam_hit_c6[43];
wire [3:0] sctag1_both_cam_hit_c6_nibble10_sum= sctag1_dc_cam_hit_c6[40] + sctag1_dc_cam_hit_c6[41] +
sctag1_dc_cam_hit_c6[42] + sctag1_dc_cam_hit_c6[43] +
sctag1_ic_cam_hit_c6[40] + sctag1_ic_cam_hit_c6[41] +
sctag1_ic_cam_hit_c6[42] + sctag1_ic_cam_hit_c6[43];
//----------------------------------------------------------------------------------------
wire [2:0] sctag1_dc_cam_hit_c6_nibble11_sum = sctag1_dc_cam_hit_c6[44] + sctag1_dc_cam_hit_c6[45] +
sctag1_dc_cam_hit_c6[46] + sctag1_dc_cam_hit_c6[47];
wire [2:0] sctag1_ic_cam_hit_c6_nibble11_sum = sctag1_ic_cam_hit_c6[44] + sctag1_ic_cam_hit_c6[45] +
sctag1_ic_cam_hit_c6[46] + sctag1_ic_cam_hit_c6[47];
wire [3:0] sctag1_both_cam_hit_c6_nibble11_sum= sctag1_dc_cam_hit_c6[44] + sctag1_dc_cam_hit_c6[45] +
sctag1_dc_cam_hit_c6[46] + sctag1_dc_cam_hit_c6[47] +
sctag1_ic_cam_hit_c6[44] + sctag1_ic_cam_hit_c6[45] +
sctag1_ic_cam_hit_c6[46] + sctag1_ic_cam_hit_c6[47];
//----------------------------------------------------------------------------------------
wire [2:0] sctag1_dc_cam_hit_c6_nibble12_sum = sctag1_dc_cam_hit_c6[48] + sctag1_dc_cam_hit_c6[49] +
sctag1_dc_cam_hit_c6[50] + sctag1_dc_cam_hit_c6[51];
wire [2:0] sctag1_ic_cam_hit_c6_nibble12_sum = sctag1_ic_cam_hit_c6[48] + sctag1_ic_cam_hit_c6[49] +
sctag1_ic_cam_hit_c6[50] + sctag1_ic_cam_hit_c6[51];
wire [3:0] sctag1_both_cam_hit_c6_nibble12_sum= sctag1_dc_cam_hit_c6[48] + sctag1_dc_cam_hit_c6[49] +
sctag1_dc_cam_hit_c6[50] + sctag1_dc_cam_hit_c6[51] +
sctag1_ic_cam_hit_c6[48] + sctag1_ic_cam_hit_c6[49] +
sctag1_ic_cam_hit_c6[50] + sctag1_ic_cam_hit_c6[51];
//----------------------------------------------------------------------------------------
wire [2:0] sctag1_dc_cam_hit_c6_nibble13_sum = sctag1_dc_cam_hit_c6[52] + sctag1_dc_cam_hit_c6[53] +
sctag1_dc_cam_hit_c6[54] + sctag1_dc_cam_hit_c6[55];
wire [2:0] sctag1_ic_cam_hit_c6_nibble13_sum = sctag1_ic_cam_hit_c6[52] + sctag1_ic_cam_hit_c6[53] +
sctag1_ic_cam_hit_c6[54] + sctag1_ic_cam_hit_c6[55];
wire [3:0] sctag1_both_cam_hit_c6_nibble13_sum= sctag1_dc_cam_hit_c6[52] + sctag1_dc_cam_hit_c6[53] +
sctag1_dc_cam_hit_c6[54] + sctag1_dc_cam_hit_c6[55] +
sctag1_ic_cam_hit_c6[52] + sctag1_ic_cam_hit_c6[53] +
sctag1_ic_cam_hit_c6[54] + sctag1_ic_cam_hit_c6[55];
//----------------------------------------------------------------------------------------
wire [2:0] sctag1_dc_cam_hit_c6_nibble14_sum = sctag1_dc_cam_hit_c6[56] + sctag1_dc_cam_hit_c6[57] +
sctag1_dc_cam_hit_c6[58] + sctag1_dc_cam_hit_c6[59];
wire [2:0] sctag1_ic_cam_hit_c6_nibble14_sum = sctag1_ic_cam_hit_c6[56] + sctag1_ic_cam_hit_c6[57] +
sctag1_ic_cam_hit_c6[58] + sctag1_ic_cam_hit_c6[59];
wire [3:0] sctag1_both_cam_hit_c6_nibble14_sum= sctag1_dc_cam_hit_c6[56] + sctag1_dc_cam_hit_c6[57] +
sctag1_dc_cam_hit_c6[58] + sctag1_dc_cam_hit_c6[59] +
sctag1_ic_cam_hit_c6[56] + sctag1_ic_cam_hit_c6[57] +
sctag1_ic_cam_hit_c6[58] + sctag1_ic_cam_hit_c6[59];
//----------------------------------------------------------------------------------------
wire [2:0] sctag1_dc_cam_hit_c6_nibble15_sum = sctag1_dc_cam_hit_c6[60] + sctag1_dc_cam_hit_c6[61] +
sctag1_dc_cam_hit_c6[62] + sctag1_dc_cam_hit_c6[63];
wire [2:0] sctag1_ic_cam_hit_c6_nibble15_sum = sctag1_ic_cam_hit_c6[60] + sctag1_ic_cam_hit_c6[61] +
sctag1_ic_cam_hit_c6[62] + sctag1_ic_cam_hit_c6[63];
wire [3:0] sctag1_both_cam_hit_c6_nibble15_sum= sctag1_dc_cam_hit_c6[60] + sctag1_dc_cam_hit_c6[61] +
sctag1_dc_cam_hit_c6[62] + sctag1_dc_cam_hit_c6[63] +
sctag1_ic_cam_hit_c6[60] + sctag1_ic_cam_hit_c6[61] +
sctag1_ic_cam_hit_c6[62] + sctag1_ic_cam_hit_c6[63];
//----------------------------------------------------------------------------------------
wire [2:0] sctag1_dc_cam_hit_c6_nibble16_sum = sctag1_dc_cam_hit_c6[64] + sctag1_dc_cam_hit_c6[65] +
sctag1_dc_cam_hit_c6[66] + sctag1_dc_cam_hit_c6[67];
wire [2:0] sctag1_ic_cam_hit_c6_nibble16_sum = sctag1_ic_cam_hit_c6[64] + sctag1_ic_cam_hit_c6[65] +
sctag1_ic_cam_hit_c6[66] + sctag1_ic_cam_hit_c6[67];
wire [3:0] sctag1_both_cam_hit_c6_nibble16_sum= sctag1_dc_cam_hit_c6[64] + sctag1_dc_cam_hit_c6[65] +
sctag1_dc_cam_hit_c6[66] + sctag1_dc_cam_hit_c6[67] +
sctag1_ic_cam_hit_c6[64] + sctag1_ic_cam_hit_c6[65] +
sctag1_ic_cam_hit_c6[66] + sctag1_ic_cam_hit_c6[67];
//----------------------------------------------------------------------------------------
wire [2:0] sctag1_dc_cam_hit_c6_nibble17_sum = sctag1_dc_cam_hit_c6[68] + sctag1_dc_cam_hit_c6[69] +
sctag1_dc_cam_hit_c6[70] + sctag1_dc_cam_hit_c6[71];
wire [2:0] sctag1_ic_cam_hit_c6_nibble17_sum = sctag1_ic_cam_hit_c6[68] + sctag1_ic_cam_hit_c6[69] +
sctag1_ic_cam_hit_c6[70] + sctag1_ic_cam_hit_c6[71];
wire [3:0] sctag1_both_cam_hit_c6_nibble17_sum= sctag1_dc_cam_hit_c6[68] + sctag1_dc_cam_hit_c6[69] +
sctag1_dc_cam_hit_c6[70] + sctag1_dc_cam_hit_c6[71] +
sctag1_ic_cam_hit_c6[68] + sctag1_ic_cam_hit_c6[69] +
sctag1_ic_cam_hit_c6[70] + sctag1_ic_cam_hit_c6[71];
//----------------------------------------------------------------------------------------
wire [2:0] sctag1_dc_cam_hit_c6_nibble18_sum = sctag1_dc_cam_hit_c6[72] + sctag1_dc_cam_hit_c6[73] +
sctag1_dc_cam_hit_c6[74] + sctag1_dc_cam_hit_c6[75];
wire [2:0] sctag1_ic_cam_hit_c6_nibble18_sum = sctag1_ic_cam_hit_c6[72] + sctag1_ic_cam_hit_c6[73] +
sctag1_ic_cam_hit_c6[74] + sctag1_ic_cam_hit_c6[75];
wire [3:0] sctag1_both_cam_hit_c6_nibble18_sum= sctag1_dc_cam_hit_c6[72] + sctag1_dc_cam_hit_c6[73] +
sctag1_dc_cam_hit_c6[74] + sctag1_dc_cam_hit_c6[75] +
sctag1_ic_cam_hit_c6[72] + sctag1_ic_cam_hit_c6[73] +
sctag1_ic_cam_hit_c6[74] + sctag1_ic_cam_hit_c6[75];
//----------------------------------------------------------------------------------------
wire [2:0] sctag1_dc_cam_hit_c6_nibble19_sum = sctag1_dc_cam_hit_c6[76] + sctag1_dc_cam_hit_c6[77] +
sctag1_dc_cam_hit_c6[78] + sctag1_dc_cam_hit_c6[79];
wire [2:0] sctag1_ic_cam_hit_c6_nibble19_sum = sctag1_ic_cam_hit_c6[76] + sctag1_ic_cam_hit_c6[77] +
sctag1_ic_cam_hit_c6[78] + sctag1_ic_cam_hit_c6[79];
wire [3:0] sctag1_both_cam_hit_c6_nibble19_sum= sctag1_dc_cam_hit_c6[76] + sctag1_dc_cam_hit_c6[77] +
sctag1_dc_cam_hit_c6[78] + sctag1_dc_cam_hit_c6[79] +
sctag1_ic_cam_hit_c6[76] + sctag1_ic_cam_hit_c6[77] +
sctag1_ic_cam_hit_c6[78] + sctag1_ic_cam_hit_c6[79];
//----------------------------------------------------------------------------------------
wire [2:0] sctag1_dc_cam_hit_c6_nibble20_sum = sctag1_dc_cam_hit_c6[80] + sctag1_dc_cam_hit_c6[81] +
sctag1_dc_cam_hit_c6[82] + sctag1_dc_cam_hit_c6[83];
wire [2:0] sctag1_ic_cam_hit_c6_nibble20_sum = sctag1_ic_cam_hit_c6[80] + sctag1_ic_cam_hit_c6[81] +
sctag1_ic_cam_hit_c6[82] + sctag1_ic_cam_hit_c6[83];
wire [3:0] sctag1_both_cam_hit_c6_nibble20_sum= sctag1_dc_cam_hit_c6[80] + sctag1_dc_cam_hit_c6[81] +
sctag1_dc_cam_hit_c6[82] + sctag1_dc_cam_hit_c6[83] +
sctag1_ic_cam_hit_c6[80] + sctag1_ic_cam_hit_c6[81] +
sctag1_ic_cam_hit_c6[82] + sctag1_ic_cam_hit_c6[83];
//----------------------------------------------------------------------------------------
wire [2:0] sctag1_dc_cam_hit_c6_nibble21_sum = sctag1_dc_cam_hit_c6[84] + sctag1_dc_cam_hit_c6[85] +
sctag1_dc_cam_hit_c6[86] + sctag1_dc_cam_hit_c6[87];
wire [2:0] sctag1_ic_cam_hit_c6_nibble21_sum = sctag1_ic_cam_hit_c6[84] + sctag1_ic_cam_hit_c6[85] +
sctag1_ic_cam_hit_c6[86] + sctag1_ic_cam_hit_c6[87];
wire [3:0] sctag1_both_cam_hit_c6_nibble21_sum= sctag1_dc_cam_hit_c6[84] + sctag1_dc_cam_hit_c6[85] +
sctag1_dc_cam_hit_c6[86] + sctag1_dc_cam_hit_c6[87] +
sctag1_ic_cam_hit_c6[84] + sctag1_ic_cam_hit_c6[85] +
sctag1_ic_cam_hit_c6[86] + sctag1_ic_cam_hit_c6[87];
//----------------------------------------------------------------------------------------
wire [2:0] sctag1_dc_cam_hit_c6_nibble22_sum = sctag1_dc_cam_hit_c6[88] + sctag1_dc_cam_hit_c6[89] +
sctag1_dc_cam_hit_c6[90] + sctag1_dc_cam_hit_c6[91];
wire [2:0] sctag1_ic_cam_hit_c6_nibble22_sum = sctag1_ic_cam_hit_c6[88] + sctag1_ic_cam_hit_c6[89] +
sctag1_ic_cam_hit_c6[90] + sctag1_ic_cam_hit_c6[91];
wire [3:0] sctag1_both_cam_hit_c6_nibble22_sum= sctag1_dc_cam_hit_c6[88] + sctag1_dc_cam_hit_c6[89] +
sctag1_dc_cam_hit_c6[90] + sctag1_dc_cam_hit_c6[91] +
sctag1_ic_cam_hit_c6[88] + sctag1_ic_cam_hit_c6[89] +
sctag1_ic_cam_hit_c6[90] + sctag1_ic_cam_hit_c6[91];
//----------------------------------------------------------------------------------------
wire [2:0] sctag1_dc_cam_hit_c6_nibble23_sum = sctag1_dc_cam_hit_c6[92] + sctag1_dc_cam_hit_c6[93] +
sctag1_dc_cam_hit_c6[94] + sctag1_dc_cam_hit_c6[95];
wire [2:0] sctag1_ic_cam_hit_c6_nibble23_sum = sctag1_ic_cam_hit_c6[92] + sctag1_ic_cam_hit_c6[93] +
sctag1_ic_cam_hit_c6[94] + sctag1_ic_cam_hit_c6[95];
wire [3:0] sctag1_both_cam_hit_c6_nibble23_sum= sctag1_dc_cam_hit_c6[92] + sctag1_dc_cam_hit_c6[93] +
sctag1_dc_cam_hit_c6[94] + sctag1_dc_cam_hit_c6[95] +
sctag1_ic_cam_hit_c6[92] + sctag1_ic_cam_hit_c6[93] +
sctag1_ic_cam_hit_c6[94] + sctag1_ic_cam_hit_c6[95];
//----------------------------------------------------------------------------------------
wire [2:0] sctag1_dc_cam_hit_c6_nibble24_sum = sctag1_dc_cam_hit_c6[96] + sctag1_dc_cam_hit_c6[97] +
sctag1_dc_cam_hit_c6[98] + sctag1_dc_cam_hit_c6[99];
wire [2:0] sctag1_ic_cam_hit_c6_nibble24_sum = sctag1_ic_cam_hit_c6[96] + sctag1_ic_cam_hit_c6[97] +
sctag1_ic_cam_hit_c6[98] + sctag1_ic_cam_hit_c6[99];
wire [3:0] sctag1_both_cam_hit_c6_nibble24_sum= sctag1_dc_cam_hit_c6[96] + sctag1_dc_cam_hit_c6[97] +
sctag1_dc_cam_hit_c6[98] + sctag1_dc_cam_hit_c6[99] +
sctag1_ic_cam_hit_c6[96] + sctag1_ic_cam_hit_c6[97] +
sctag1_ic_cam_hit_c6[98] + sctag1_ic_cam_hit_c6[99];
//----------------------------------------------------------------------------------------
wire [2:0] sctag1_dc_cam_hit_c6_nibble25_sum = sctag1_dc_cam_hit_c6[100] + sctag1_dc_cam_hit_c6[101] +
sctag1_dc_cam_hit_c6[102] + sctag1_dc_cam_hit_c6[103];
wire [2:0] sctag1_ic_cam_hit_c6_nibble25_sum = sctag1_ic_cam_hit_c6[100] + sctag1_ic_cam_hit_c6[101] +
sctag1_ic_cam_hit_c6[102] + sctag1_ic_cam_hit_c6[103];
wire [3:0] sctag1_both_cam_hit_c6_nibble25_sum= sctag1_dc_cam_hit_c6[100] + sctag1_dc_cam_hit_c6[101] +
sctag1_dc_cam_hit_c6[102] + sctag1_dc_cam_hit_c6[103] +
sctag1_ic_cam_hit_c6[100] + sctag1_ic_cam_hit_c6[101] +
sctag1_ic_cam_hit_c6[102] + sctag1_ic_cam_hit_c6[103];
//----------------------------------------------------------------------------------------
wire [2:0] sctag1_dc_cam_hit_c6_nibble26_sum = sctag1_dc_cam_hit_c6[104] + sctag1_dc_cam_hit_c6[105] +
sctag1_dc_cam_hit_c6[106] + sctag1_dc_cam_hit_c6[107];
wire [2:0] sctag1_ic_cam_hit_c6_nibble26_sum = sctag1_ic_cam_hit_c6[104] + sctag1_ic_cam_hit_c6[105] +
sctag1_ic_cam_hit_c6[106] + sctag1_ic_cam_hit_c6[107];
wire [3:0] sctag1_both_cam_hit_c6_nibble26_sum= sctag1_dc_cam_hit_c6[104] + sctag1_dc_cam_hit_c6[105] +
sctag1_dc_cam_hit_c6[106] + sctag1_dc_cam_hit_c6[107] +
sctag1_ic_cam_hit_c6[104] + sctag1_ic_cam_hit_c6[105] +
sctag1_ic_cam_hit_c6[106] + sctag1_ic_cam_hit_c6[107];
//----------------------------------------------------------------------------------------
wire [2:0] sctag1_dc_cam_hit_c6_nibble27_sum = sctag1_dc_cam_hit_c6[108] + sctag1_dc_cam_hit_c6[109] +
sctag1_dc_cam_hit_c6[110] + sctag1_dc_cam_hit_c6[111];
wire [2:0] sctag1_ic_cam_hit_c6_nibble27_sum = sctag1_ic_cam_hit_c6[108] + sctag1_ic_cam_hit_c6[109] +
sctag1_ic_cam_hit_c6[110] + sctag1_ic_cam_hit_c6[111];
wire [3:0] sctag1_both_cam_hit_c6_nibble27_sum= sctag1_dc_cam_hit_c6[108] + sctag1_dc_cam_hit_c6[109] +
sctag1_dc_cam_hit_c6[110] + sctag1_dc_cam_hit_c6[111] +
sctag1_ic_cam_hit_c6[108] + sctag1_ic_cam_hit_c6[109] +
sctag1_ic_cam_hit_c6[110] + sctag1_ic_cam_hit_c6[111];
//----------------------------------------------------------------------------------------
wire [2:0] sctag1_dc_cam_hit_c6_nibble28_sum = sctag1_dc_cam_hit_c6[112] + sctag1_dc_cam_hit_c6[113] +
sctag1_dc_cam_hit_c6[114] + sctag1_dc_cam_hit_c6[115];
wire [2:0] sctag1_ic_cam_hit_c6_nibble28_sum = sctag1_ic_cam_hit_c6[112] + sctag1_ic_cam_hit_c6[113] +
sctag1_ic_cam_hit_c6[114] + sctag1_ic_cam_hit_c6[115];
wire [3:0] sctag1_both_cam_hit_c6_nibble28_sum= sctag1_dc_cam_hit_c6[112] + sctag1_dc_cam_hit_c6[113] +
sctag1_dc_cam_hit_c6[114] + sctag1_dc_cam_hit_c6[115] +
sctag1_ic_cam_hit_c6[112] + sctag1_ic_cam_hit_c6[113] +
sctag1_ic_cam_hit_c6[114] + sctag1_ic_cam_hit_c6[115];
//----------------------------------------------------------------------------------------
wire [2:0] sctag1_dc_cam_hit_c6_nibble29_sum = sctag1_dc_cam_hit_c6[116] + sctag1_dc_cam_hit_c6[117] +
sctag1_dc_cam_hit_c6[118] + sctag1_dc_cam_hit_c6[119];
wire [2:0] sctag1_ic_cam_hit_c6_nibble29_sum = sctag1_ic_cam_hit_c6[116] + sctag1_ic_cam_hit_c6[117] +
sctag1_ic_cam_hit_c6[118] + sctag1_ic_cam_hit_c6[119];
wire [3:0] sctag1_both_cam_hit_c6_nibble29_sum= sctag1_dc_cam_hit_c6[116] + sctag1_dc_cam_hit_c6[117] +
sctag1_dc_cam_hit_c6[118] + sctag1_dc_cam_hit_c6[119] +
sctag1_ic_cam_hit_c6[116] + sctag1_ic_cam_hit_c6[117] +
sctag1_ic_cam_hit_c6[118] + sctag1_ic_cam_hit_c6[119];
//----------------------------------------------------------------------------------------
wire [2:0] sctag1_dc_cam_hit_c6_nibble30_sum = sctag1_dc_cam_hit_c6[120] + sctag1_dc_cam_hit_c6[121] +
sctag1_dc_cam_hit_c6[122] + sctag1_dc_cam_hit_c6[123];
wire [2:0] sctag1_ic_cam_hit_c6_nibble30_sum = sctag1_ic_cam_hit_c6[120] + sctag1_ic_cam_hit_c6[121] +
sctag1_ic_cam_hit_c6[122] + sctag1_ic_cam_hit_c6[123];
wire [3:0] sctag1_both_cam_hit_c6_nibble30_sum= sctag1_dc_cam_hit_c6[120] + sctag1_dc_cam_hit_c6[121] +
sctag1_dc_cam_hit_c6[122] + sctag1_dc_cam_hit_c6[123] +
sctag1_ic_cam_hit_c6[120] + sctag1_ic_cam_hit_c6[121] +
sctag1_ic_cam_hit_c6[122] + sctag1_ic_cam_hit_c6[123];
//----------------------------------------------------------------------------------------
wire [2:0] sctag1_dc_cam_hit_c6_nibble31_sum = sctag1_dc_cam_hit_c6[124] + sctag1_dc_cam_hit_c6[125] +
sctag1_dc_cam_hit_c6[126] + sctag1_dc_cam_hit_c6[127];
wire [2:0] sctag1_ic_cam_hit_c6_nibble31_sum = sctag1_ic_cam_hit_c6[124] + sctag1_ic_cam_hit_c6[125] +
sctag1_ic_cam_hit_c6[126] + sctag1_ic_cam_hit_c6[127];
wire [3:0] sctag1_both_cam_hit_c6_nibble31_sum= sctag1_dc_cam_hit_c6[124] + sctag1_dc_cam_hit_c6[125] +
sctag1_dc_cam_hit_c6[126] + sctag1_dc_cam_hit_c6[127] +
sctag1_ic_cam_hit_c6[124] + sctag1_ic_cam_hit_c6[125] +
sctag1_ic_cam_hit_c6[126] + sctag1_ic_cam_hit_c6[127];
wire [7:0] sctag2_cpx_req_cq = `TOP_MEMORY.sctag2_cpx_req_cq[7:0];
wire [7:0] sctag2_cpx_atom_cq = `TOP_MEMORY.sctag2_cpx_atom_cq;
wire [`CPX_WIDTH-1:0] sctag2_cpx_data_ca = `TOP_MEMORY.sctag2_cpx_data_ca[`CPX_WIDTH-1:0];
wire sctag2_pcx_stall_pq = `TOP_MEMORY.sctag2_pcx_stall_pq;
reg [7:0] sctag2_cpx_req_cq_d1; // delayed by 1
reg [7:0] sctag2_cpx_req_cq_d2; // delayed by 2
reg [7:0] sctag2_cpx_atom_cq_d1; // delayed by 1
reg [7:0] sctag2_cpx_atom_cq_d2; // delayed by 2
reg [127:0] sctag2_cpx_type_str; // in string format
reg [3:0] sctag2_cpx_type; // packet type
reg sctag2_dc_lkup_c5;
reg sctag2_ic_lkup_c5;
reg sctag2_dc_lkup_c6;
reg sctag2_ic_lkup_c6;
wire [3:0] sctag2_dc_lkup_panel_dec_c4 = `TOP_MEMORY.sctag2.dirrep.dc_lkup_panel_dec_c4[3:0];
wire [3:0] sctag2_dc_lkup_row_dec_c4 = `TOP_MEMORY.sctag2.dirrep.dc_lkup_row_dec_c4[3:0];
wire [3:0] sctag2_ic_lkup_panel_dec_c4 = `TOP_MEMORY.sctag2.dirrep.ic_lkup_panel_dec_c4[3:0];
wire [3:0] sctag2_ic_lkup_row_dec_c4 = `TOP_MEMORY.sctag2.dirrep.ic_lkup_row_dec_c4[3:0];
wire [127:0] sctag2_dc_cam_hit_c6 = `TOP_MEMORY.sctag2.dirvec_dp.dc_cam_hit_c6[127:0];
wire [127:0] sctag2_ic_cam_hit_c6 = `TOP_MEMORY.sctag2.dirvec_dp.ic_cam_hit_c6[127:0];
//----------------------------------------------------------------------------------------
wire [2:0] sctag2_dc_cam_hit_c6_nibble0_sum = sctag2_dc_cam_hit_c6[0] + sctag2_dc_cam_hit_c6[1] +
sctag2_dc_cam_hit_c6[2] + sctag2_dc_cam_hit_c6[3];
wire [2:0] sctag2_ic_cam_hit_c6_nibble0_sum = sctag2_ic_cam_hit_c6[0] + sctag2_ic_cam_hit_c6[1] +
sctag2_ic_cam_hit_c6[2] + sctag2_ic_cam_hit_c6[3];
wire [3:0] sctag2_both_cam_hit_c6_nibble0_sum= sctag2_dc_cam_hit_c6[0] + sctag2_dc_cam_hit_c6[1] +
sctag2_dc_cam_hit_c6[2] + sctag2_dc_cam_hit_c6[3] +
sctag2_ic_cam_hit_c6[0] + sctag2_ic_cam_hit_c6[1] +
sctag2_ic_cam_hit_c6[2] + sctag2_ic_cam_hit_c6[3];
//----------------------------------------------------------------------------------------
wire [2:0] sctag2_dc_cam_hit_c6_nibble1_sum = sctag2_dc_cam_hit_c6[4] + sctag2_dc_cam_hit_c6[5] +
sctag2_dc_cam_hit_c6[6] + sctag2_dc_cam_hit_c6[7];
wire [2:0] sctag2_ic_cam_hit_c6_nibble1_sum = sctag2_ic_cam_hit_c6[4] + sctag2_ic_cam_hit_c6[5] +
sctag2_ic_cam_hit_c6[6] + sctag2_ic_cam_hit_c6[7];
wire [3:0] sctag2_both_cam_hit_c6_nibble1_sum= sctag2_dc_cam_hit_c6[4] + sctag2_dc_cam_hit_c6[5] +
sctag2_dc_cam_hit_c6[6] + sctag2_dc_cam_hit_c6[7] +
sctag2_ic_cam_hit_c6[4] + sctag2_ic_cam_hit_c6[5] +
sctag2_ic_cam_hit_c6[6] + sctag2_ic_cam_hit_c6[7];
//----------------------------------------------------------------------------------------
wire [2:0] sctag2_dc_cam_hit_c6_nibble2_sum = sctag2_dc_cam_hit_c6[8] + sctag2_dc_cam_hit_c6[9] +
sctag2_dc_cam_hit_c6[10] + sctag2_dc_cam_hit_c6[11];
wire [2:0] sctag2_ic_cam_hit_c6_nibble2_sum = sctag2_ic_cam_hit_c6[8] + sctag2_ic_cam_hit_c6[9] +
sctag2_ic_cam_hit_c6[10] + sctag2_ic_cam_hit_c6[11];
wire [3:0] sctag2_both_cam_hit_c6_nibble2_sum= sctag2_dc_cam_hit_c6[8] + sctag2_dc_cam_hit_c6[9] +
sctag2_dc_cam_hit_c6[10] + sctag2_dc_cam_hit_c6[11] +
sctag2_ic_cam_hit_c6[8] + sctag2_ic_cam_hit_c6[9] +
sctag2_ic_cam_hit_c6[10] + sctag2_ic_cam_hit_c6[11];
//----------------------------------------------------------------------------------------
wire [2:0] sctag2_dc_cam_hit_c6_nibble3_sum = sctag2_dc_cam_hit_c6[12] + sctag2_dc_cam_hit_c6[13] +
sctag2_dc_cam_hit_c6[14] + sctag2_dc_cam_hit_c6[15];
wire [2:0] sctag2_ic_cam_hit_c6_nibble3_sum = sctag2_ic_cam_hit_c6[12] + sctag2_ic_cam_hit_c6[13] +
sctag2_ic_cam_hit_c6[14] + sctag2_ic_cam_hit_c6[15];
wire [3:0] sctag2_both_cam_hit_c6_nibble3_sum= sctag2_dc_cam_hit_c6[12] + sctag2_dc_cam_hit_c6[13] +
sctag2_dc_cam_hit_c6[14] + sctag2_dc_cam_hit_c6[15] +
sctag2_ic_cam_hit_c6[12] + sctag2_ic_cam_hit_c6[13] +
sctag2_ic_cam_hit_c6[14] + sctag2_ic_cam_hit_c6[15];
//----------------------------------------------------------------------------------------
wire [2:0] sctag2_dc_cam_hit_c6_nibble4_sum = sctag2_dc_cam_hit_c6[16] + sctag2_dc_cam_hit_c6[17] +
sctag2_dc_cam_hit_c6[18] + sctag2_dc_cam_hit_c6[19];
wire [2:0] sctag2_ic_cam_hit_c6_nibble4_sum = sctag2_ic_cam_hit_c6[16] + sctag2_ic_cam_hit_c6[17] +
sctag2_ic_cam_hit_c6[18] + sctag2_ic_cam_hit_c6[19];
wire [3:0] sctag2_both_cam_hit_c6_nibble4_sum= sctag2_dc_cam_hit_c6[16] + sctag2_dc_cam_hit_c6[17] +
sctag2_dc_cam_hit_c6[18] + sctag2_dc_cam_hit_c6[19] +
sctag2_ic_cam_hit_c6[16] + sctag2_ic_cam_hit_c6[17] +
sctag2_ic_cam_hit_c6[18] + sctag2_ic_cam_hit_c6[19];
//----------------------------------------------------------------------------------------
wire [2:0] sctag2_dc_cam_hit_c6_nibble5_sum = sctag2_dc_cam_hit_c6[20] + sctag2_dc_cam_hit_c6[21] +
sctag2_dc_cam_hit_c6[22] + sctag2_dc_cam_hit_c6[23];
wire [2:0] sctag2_ic_cam_hit_c6_nibble5_sum = sctag2_ic_cam_hit_c6[20] + sctag2_ic_cam_hit_c6[21] +
sctag2_ic_cam_hit_c6[22] + sctag2_ic_cam_hit_c6[23];
wire [3:0] sctag2_both_cam_hit_c6_nibble5_sum= sctag2_dc_cam_hit_c6[20] + sctag2_dc_cam_hit_c6[21] +
sctag2_dc_cam_hit_c6[22] + sctag2_dc_cam_hit_c6[23] +
sctag2_ic_cam_hit_c6[20] + sctag2_ic_cam_hit_c6[21] +
sctag2_ic_cam_hit_c6[22] + sctag2_ic_cam_hit_c6[23];
//----------------------------------------------------------------------------------------
wire [2:0] sctag2_dc_cam_hit_c6_nibble6_sum = sctag2_dc_cam_hit_c6[24] + sctag2_dc_cam_hit_c6[25] +
sctag2_dc_cam_hit_c6[26] + sctag2_dc_cam_hit_c6[27];
wire [2:0] sctag2_ic_cam_hit_c6_nibble6_sum = sctag2_ic_cam_hit_c6[24] + sctag2_ic_cam_hit_c6[25] +
sctag2_ic_cam_hit_c6[26] + sctag2_ic_cam_hit_c6[27];
wire [3:0] sctag2_both_cam_hit_c6_nibble6_sum= sctag2_dc_cam_hit_c6[24] + sctag2_dc_cam_hit_c6[25] +
sctag2_dc_cam_hit_c6[26] + sctag2_dc_cam_hit_c6[27] +
sctag2_ic_cam_hit_c6[24] + sctag2_ic_cam_hit_c6[25] +
sctag2_ic_cam_hit_c6[26] + sctag2_ic_cam_hit_c6[27];
//----------------------------------------------------------------------------------------
wire [2:0] sctag2_dc_cam_hit_c6_nibble7_sum = sctag2_dc_cam_hit_c6[28] + sctag2_dc_cam_hit_c6[29] +
sctag2_dc_cam_hit_c6[30] + sctag2_dc_cam_hit_c6[31];
wire [2:0] sctag2_ic_cam_hit_c6_nibble7_sum = sctag2_ic_cam_hit_c6[28] + sctag2_ic_cam_hit_c6[29] +
sctag2_ic_cam_hit_c6[30] + sctag2_ic_cam_hit_c6[31];
wire [3:0] sctag2_both_cam_hit_c6_nibble7_sum= sctag2_dc_cam_hit_c6[28] + sctag2_dc_cam_hit_c6[29] +
sctag2_dc_cam_hit_c6[30] + sctag2_dc_cam_hit_c6[31] +
sctag2_ic_cam_hit_c6[28] + sctag2_ic_cam_hit_c6[29] +
sctag2_ic_cam_hit_c6[30] + sctag2_ic_cam_hit_c6[31];
//----------------------------------------------------------------------------------------
wire [2:0] sctag2_dc_cam_hit_c6_nibble8_sum = sctag2_dc_cam_hit_c6[32] + sctag2_dc_cam_hit_c6[33] +
sctag2_dc_cam_hit_c6[34] + sctag2_dc_cam_hit_c6[35];
wire [2:0] sctag2_ic_cam_hit_c6_nibble8_sum = sctag2_ic_cam_hit_c6[32] + sctag2_ic_cam_hit_c6[33] +
sctag2_ic_cam_hit_c6[34] + sctag2_ic_cam_hit_c6[35];
wire [3:0] sctag2_both_cam_hit_c6_nibble8_sum= sctag2_dc_cam_hit_c6[32] + sctag2_dc_cam_hit_c6[33] +
sctag2_dc_cam_hit_c6[34] + sctag2_dc_cam_hit_c6[35] +
sctag2_ic_cam_hit_c6[32] + sctag2_ic_cam_hit_c6[33] +
sctag2_ic_cam_hit_c6[34] + sctag2_ic_cam_hit_c6[35];
//----------------------------------------------------------------------------------------
wire [2:0] sctag2_dc_cam_hit_c6_nibble9_sum = sctag2_dc_cam_hit_c6[36] + sctag2_dc_cam_hit_c6[37] +
sctag2_dc_cam_hit_c6[38] + sctag2_dc_cam_hit_c6[39];
wire [2:0] sctag2_ic_cam_hit_c6_nibble9_sum = sctag2_ic_cam_hit_c6[36] + sctag2_ic_cam_hit_c6[37] +
sctag2_ic_cam_hit_c6[38] + sctag2_ic_cam_hit_c6[39];
wire [3:0] sctag2_both_cam_hit_c6_nibble9_sum= sctag2_dc_cam_hit_c6[36] + sctag2_dc_cam_hit_c6[37] +
sctag2_dc_cam_hit_c6[38] + sctag2_dc_cam_hit_c6[39] +
sctag2_ic_cam_hit_c6[36] + sctag2_ic_cam_hit_c6[37] +
sctag2_ic_cam_hit_c6[38] + sctag2_ic_cam_hit_c6[39];
//----------------------------------------------------------------------------------------
wire [2:0] sctag2_dc_cam_hit_c6_nibble10_sum = sctag2_dc_cam_hit_c6[40] + sctag2_dc_cam_hit_c6[41] +
sctag2_dc_cam_hit_c6[42] + sctag2_dc_cam_hit_c6[43];
wire [2:0] sctag2_ic_cam_hit_c6_nibble10_sum = sctag2_ic_cam_hit_c6[40] + sctag2_ic_cam_hit_c6[41] +
sctag2_ic_cam_hit_c6[42] + sctag2_ic_cam_hit_c6[43];
wire [3:0] sctag2_both_cam_hit_c6_nibble10_sum= sctag2_dc_cam_hit_c6[40] + sctag2_dc_cam_hit_c6[41] +
sctag2_dc_cam_hit_c6[42] + sctag2_dc_cam_hit_c6[43] +
sctag2_ic_cam_hit_c6[40] + sctag2_ic_cam_hit_c6[41] +
sctag2_ic_cam_hit_c6[42] + sctag2_ic_cam_hit_c6[43];
//----------------------------------------------------------------------------------------
wire [2:0] sctag2_dc_cam_hit_c6_nibble11_sum = sctag2_dc_cam_hit_c6[44] + sctag2_dc_cam_hit_c6[45] +
sctag2_dc_cam_hit_c6[46] + sctag2_dc_cam_hit_c6[47];
wire [2:0] sctag2_ic_cam_hit_c6_nibble11_sum = sctag2_ic_cam_hit_c6[44] + sctag2_ic_cam_hit_c6[45] +
sctag2_ic_cam_hit_c6[46] + sctag2_ic_cam_hit_c6[47];
wire [3:0] sctag2_both_cam_hit_c6_nibble11_sum= sctag2_dc_cam_hit_c6[44] + sctag2_dc_cam_hit_c6[45] +
sctag2_dc_cam_hit_c6[46] + sctag2_dc_cam_hit_c6[47] +
sctag2_ic_cam_hit_c6[44] + sctag2_ic_cam_hit_c6[45] +
sctag2_ic_cam_hit_c6[46] + sctag2_ic_cam_hit_c6[47];
//----------------------------------------------------------------------------------------
wire [2:0] sctag2_dc_cam_hit_c6_nibble12_sum = sctag2_dc_cam_hit_c6[48] + sctag2_dc_cam_hit_c6[49] +
sctag2_dc_cam_hit_c6[50] + sctag2_dc_cam_hit_c6[51];
wire [2:0] sctag2_ic_cam_hit_c6_nibble12_sum = sctag2_ic_cam_hit_c6[48] + sctag2_ic_cam_hit_c6[49] +
sctag2_ic_cam_hit_c6[50] + sctag2_ic_cam_hit_c6[51];
wire [3:0] sctag2_both_cam_hit_c6_nibble12_sum= sctag2_dc_cam_hit_c6[48] + sctag2_dc_cam_hit_c6[49] +
sctag2_dc_cam_hit_c6[50] + sctag2_dc_cam_hit_c6[51] +
sctag2_ic_cam_hit_c6[48] + sctag2_ic_cam_hit_c6[49] +
sctag2_ic_cam_hit_c6[50] + sctag2_ic_cam_hit_c6[51];
//----------------------------------------------------------------------------------------
wire [2:0] sctag2_dc_cam_hit_c6_nibble13_sum = sctag2_dc_cam_hit_c6[52] + sctag2_dc_cam_hit_c6[53] +
sctag2_dc_cam_hit_c6[54] + sctag2_dc_cam_hit_c6[55];
wire [2:0] sctag2_ic_cam_hit_c6_nibble13_sum = sctag2_ic_cam_hit_c6[52] + sctag2_ic_cam_hit_c6[53] +
sctag2_ic_cam_hit_c6[54] + sctag2_ic_cam_hit_c6[55];
wire [3:0] sctag2_both_cam_hit_c6_nibble13_sum= sctag2_dc_cam_hit_c6[52] + sctag2_dc_cam_hit_c6[53] +
sctag2_dc_cam_hit_c6[54] + sctag2_dc_cam_hit_c6[55] +
sctag2_ic_cam_hit_c6[52] + sctag2_ic_cam_hit_c6[53] +
sctag2_ic_cam_hit_c6[54] + sctag2_ic_cam_hit_c6[55];
//----------------------------------------------------------------------------------------
wire [2:0] sctag2_dc_cam_hit_c6_nibble14_sum = sctag2_dc_cam_hit_c6[56] + sctag2_dc_cam_hit_c6[57] +
sctag2_dc_cam_hit_c6[58] + sctag2_dc_cam_hit_c6[59];
wire [2:0] sctag2_ic_cam_hit_c6_nibble14_sum = sctag2_ic_cam_hit_c6[56] + sctag2_ic_cam_hit_c6[57] +
sctag2_ic_cam_hit_c6[58] + sctag2_ic_cam_hit_c6[59];
wire [3:0] sctag2_both_cam_hit_c6_nibble14_sum= sctag2_dc_cam_hit_c6[56] + sctag2_dc_cam_hit_c6[57] +
sctag2_dc_cam_hit_c6[58] + sctag2_dc_cam_hit_c6[59] +
sctag2_ic_cam_hit_c6[56] + sctag2_ic_cam_hit_c6[57] +
sctag2_ic_cam_hit_c6[58] + sctag2_ic_cam_hit_c6[59];
//----------------------------------------------------------------------------------------
wire [2:0] sctag2_dc_cam_hit_c6_nibble15_sum = sctag2_dc_cam_hit_c6[60] + sctag2_dc_cam_hit_c6[61] +
sctag2_dc_cam_hit_c6[62] + sctag2_dc_cam_hit_c6[63];
wire [2:0] sctag2_ic_cam_hit_c6_nibble15_sum = sctag2_ic_cam_hit_c6[60] + sctag2_ic_cam_hit_c6[61] +
sctag2_ic_cam_hit_c6[62] + sctag2_ic_cam_hit_c6[63];
wire [3:0] sctag2_both_cam_hit_c6_nibble15_sum= sctag2_dc_cam_hit_c6[60] + sctag2_dc_cam_hit_c6[61] +
sctag2_dc_cam_hit_c6[62] + sctag2_dc_cam_hit_c6[63] +
sctag2_ic_cam_hit_c6[60] + sctag2_ic_cam_hit_c6[61] +
sctag2_ic_cam_hit_c6[62] + sctag2_ic_cam_hit_c6[63];
//----------------------------------------------------------------------------------------
wire [2:0] sctag2_dc_cam_hit_c6_nibble16_sum = sctag2_dc_cam_hit_c6[64] + sctag2_dc_cam_hit_c6[65] +
sctag2_dc_cam_hit_c6[66] + sctag2_dc_cam_hit_c6[67];
wire [2:0] sctag2_ic_cam_hit_c6_nibble16_sum = sctag2_ic_cam_hit_c6[64] + sctag2_ic_cam_hit_c6[65] +
sctag2_ic_cam_hit_c6[66] + sctag2_ic_cam_hit_c6[67];
wire [3:0] sctag2_both_cam_hit_c6_nibble16_sum= sctag2_dc_cam_hit_c6[64] + sctag2_dc_cam_hit_c6[65] +
sctag2_dc_cam_hit_c6[66] + sctag2_dc_cam_hit_c6[67] +
sctag2_ic_cam_hit_c6[64] + sctag2_ic_cam_hit_c6[65] +
sctag2_ic_cam_hit_c6[66] + sctag2_ic_cam_hit_c6[67];
//----------------------------------------------------------------------------------------
wire [2:0] sctag2_dc_cam_hit_c6_nibble17_sum = sctag2_dc_cam_hit_c6[68] + sctag2_dc_cam_hit_c6[69] +
sctag2_dc_cam_hit_c6[70] + sctag2_dc_cam_hit_c6[71];
wire [2:0] sctag2_ic_cam_hit_c6_nibble17_sum = sctag2_ic_cam_hit_c6[68] + sctag2_ic_cam_hit_c6[69] +
sctag2_ic_cam_hit_c6[70] + sctag2_ic_cam_hit_c6[71];
wire [3:0] sctag2_both_cam_hit_c6_nibble17_sum= sctag2_dc_cam_hit_c6[68] + sctag2_dc_cam_hit_c6[69] +
sctag2_dc_cam_hit_c6[70] + sctag2_dc_cam_hit_c6[71] +
sctag2_ic_cam_hit_c6[68] + sctag2_ic_cam_hit_c6[69] +
sctag2_ic_cam_hit_c6[70] + sctag2_ic_cam_hit_c6[71];
//----------------------------------------------------------------------------------------
wire [2:0] sctag2_dc_cam_hit_c6_nibble18_sum = sctag2_dc_cam_hit_c6[72] + sctag2_dc_cam_hit_c6[73] +
sctag2_dc_cam_hit_c6[74] + sctag2_dc_cam_hit_c6[75];
wire [2:0] sctag2_ic_cam_hit_c6_nibble18_sum = sctag2_ic_cam_hit_c6[72] + sctag2_ic_cam_hit_c6[73] +
sctag2_ic_cam_hit_c6[74] + sctag2_ic_cam_hit_c6[75];
wire [3:0] sctag2_both_cam_hit_c6_nibble18_sum= sctag2_dc_cam_hit_c6[72] + sctag2_dc_cam_hit_c6[73] +
sctag2_dc_cam_hit_c6[74] + sctag2_dc_cam_hit_c6[75] +
sctag2_ic_cam_hit_c6[72] + sctag2_ic_cam_hit_c6[73] +
sctag2_ic_cam_hit_c6[74] + sctag2_ic_cam_hit_c6[75];
//----------------------------------------------------------------------------------------
wire [2:0] sctag2_dc_cam_hit_c6_nibble19_sum = sctag2_dc_cam_hit_c6[76] + sctag2_dc_cam_hit_c6[77] +
sctag2_dc_cam_hit_c6[78] + sctag2_dc_cam_hit_c6[79];
wire [2:0] sctag2_ic_cam_hit_c6_nibble19_sum = sctag2_ic_cam_hit_c6[76] + sctag2_ic_cam_hit_c6[77] +
sctag2_ic_cam_hit_c6[78] + sctag2_ic_cam_hit_c6[79];
wire [3:0] sctag2_both_cam_hit_c6_nibble19_sum= sctag2_dc_cam_hit_c6[76] + sctag2_dc_cam_hit_c6[77] +
sctag2_dc_cam_hit_c6[78] + sctag2_dc_cam_hit_c6[79] +
sctag2_ic_cam_hit_c6[76] + sctag2_ic_cam_hit_c6[77] +
sctag2_ic_cam_hit_c6[78] + sctag2_ic_cam_hit_c6[79];
//----------------------------------------------------------------------------------------
wire [2:0] sctag2_dc_cam_hit_c6_nibble20_sum = sctag2_dc_cam_hit_c6[80] + sctag2_dc_cam_hit_c6[81] +
sctag2_dc_cam_hit_c6[82] + sctag2_dc_cam_hit_c6[83];
wire [2:0] sctag2_ic_cam_hit_c6_nibble20_sum = sctag2_ic_cam_hit_c6[80] + sctag2_ic_cam_hit_c6[81] +
sctag2_ic_cam_hit_c6[82] + sctag2_ic_cam_hit_c6[83];
wire [3:0] sctag2_both_cam_hit_c6_nibble20_sum= sctag2_dc_cam_hit_c6[80] + sctag2_dc_cam_hit_c6[81] +
sctag2_dc_cam_hit_c6[82] + sctag2_dc_cam_hit_c6[83] +
sctag2_ic_cam_hit_c6[80] + sctag2_ic_cam_hit_c6[81] +
sctag2_ic_cam_hit_c6[82] + sctag2_ic_cam_hit_c6[83];
//----------------------------------------------------------------------------------------
wire [2:0] sctag2_dc_cam_hit_c6_nibble21_sum = sctag2_dc_cam_hit_c6[84] + sctag2_dc_cam_hit_c6[85] +
sctag2_dc_cam_hit_c6[86] + sctag2_dc_cam_hit_c6[87];
wire [2:0] sctag2_ic_cam_hit_c6_nibble21_sum = sctag2_ic_cam_hit_c6[84] + sctag2_ic_cam_hit_c6[85] +
sctag2_ic_cam_hit_c6[86] + sctag2_ic_cam_hit_c6[87];
wire [3:0] sctag2_both_cam_hit_c6_nibble21_sum= sctag2_dc_cam_hit_c6[84] + sctag2_dc_cam_hit_c6[85] +
sctag2_dc_cam_hit_c6[86] + sctag2_dc_cam_hit_c6[87] +
sctag2_ic_cam_hit_c6[84] + sctag2_ic_cam_hit_c6[85] +
sctag2_ic_cam_hit_c6[86] + sctag2_ic_cam_hit_c6[87];
//----------------------------------------------------------------------------------------
wire [2:0] sctag2_dc_cam_hit_c6_nibble22_sum = sctag2_dc_cam_hit_c6[88] + sctag2_dc_cam_hit_c6[89] +
sctag2_dc_cam_hit_c6[90] + sctag2_dc_cam_hit_c6[91];
wire [2:0] sctag2_ic_cam_hit_c6_nibble22_sum = sctag2_ic_cam_hit_c6[88] + sctag2_ic_cam_hit_c6[89] +
sctag2_ic_cam_hit_c6[90] + sctag2_ic_cam_hit_c6[91];
wire [3:0] sctag2_both_cam_hit_c6_nibble22_sum= sctag2_dc_cam_hit_c6[88] + sctag2_dc_cam_hit_c6[89] +
sctag2_dc_cam_hit_c6[90] + sctag2_dc_cam_hit_c6[91] +
sctag2_ic_cam_hit_c6[88] + sctag2_ic_cam_hit_c6[89] +
sctag2_ic_cam_hit_c6[90] + sctag2_ic_cam_hit_c6[91];
//----------------------------------------------------------------------------------------
wire [2:0] sctag2_dc_cam_hit_c6_nibble23_sum = sctag2_dc_cam_hit_c6[92] + sctag2_dc_cam_hit_c6[93] +
sctag2_dc_cam_hit_c6[94] + sctag2_dc_cam_hit_c6[95];
wire [2:0] sctag2_ic_cam_hit_c6_nibble23_sum = sctag2_ic_cam_hit_c6[92] + sctag2_ic_cam_hit_c6[93] +
sctag2_ic_cam_hit_c6[94] + sctag2_ic_cam_hit_c6[95];
wire [3:0] sctag2_both_cam_hit_c6_nibble23_sum= sctag2_dc_cam_hit_c6[92] + sctag2_dc_cam_hit_c6[93] +
sctag2_dc_cam_hit_c6[94] + sctag2_dc_cam_hit_c6[95] +
sctag2_ic_cam_hit_c6[92] + sctag2_ic_cam_hit_c6[93] +
sctag2_ic_cam_hit_c6[94] + sctag2_ic_cam_hit_c6[95];
//----------------------------------------------------------------------------------------
wire [2:0] sctag2_dc_cam_hit_c6_nibble24_sum = sctag2_dc_cam_hit_c6[96] + sctag2_dc_cam_hit_c6[97] +
sctag2_dc_cam_hit_c6[98] + sctag2_dc_cam_hit_c6[99];
wire [2:0] sctag2_ic_cam_hit_c6_nibble24_sum = sctag2_ic_cam_hit_c6[96] + sctag2_ic_cam_hit_c6[97] +
sctag2_ic_cam_hit_c6[98] + sctag2_ic_cam_hit_c6[99];
wire [3:0] sctag2_both_cam_hit_c6_nibble24_sum= sctag2_dc_cam_hit_c6[96] + sctag2_dc_cam_hit_c6[97] +
sctag2_dc_cam_hit_c6[98] + sctag2_dc_cam_hit_c6[99] +
sctag2_ic_cam_hit_c6[96] + sctag2_ic_cam_hit_c6[97] +
sctag2_ic_cam_hit_c6[98] + sctag2_ic_cam_hit_c6[99];
//----------------------------------------------------------------------------------------
wire [2:0] sctag2_dc_cam_hit_c6_nibble25_sum = sctag2_dc_cam_hit_c6[100] + sctag2_dc_cam_hit_c6[101] +
sctag2_dc_cam_hit_c6[102] + sctag2_dc_cam_hit_c6[103];
wire [2:0] sctag2_ic_cam_hit_c6_nibble25_sum = sctag2_ic_cam_hit_c6[100] + sctag2_ic_cam_hit_c6[101] +
sctag2_ic_cam_hit_c6[102] + sctag2_ic_cam_hit_c6[103];
wire [3:0] sctag2_both_cam_hit_c6_nibble25_sum= sctag2_dc_cam_hit_c6[100] + sctag2_dc_cam_hit_c6[101] +
sctag2_dc_cam_hit_c6[102] + sctag2_dc_cam_hit_c6[103] +
sctag2_ic_cam_hit_c6[100] + sctag2_ic_cam_hit_c6[101] +
sctag2_ic_cam_hit_c6[102] + sctag2_ic_cam_hit_c6[103];
//----------------------------------------------------------------------------------------
wire [2:0] sctag2_dc_cam_hit_c6_nibble26_sum = sctag2_dc_cam_hit_c6[104] + sctag2_dc_cam_hit_c6[105] +
sctag2_dc_cam_hit_c6[106] + sctag2_dc_cam_hit_c6[107];
wire [2:0] sctag2_ic_cam_hit_c6_nibble26_sum = sctag2_ic_cam_hit_c6[104] + sctag2_ic_cam_hit_c6[105] +
sctag2_ic_cam_hit_c6[106] + sctag2_ic_cam_hit_c6[107];
wire [3:0] sctag2_both_cam_hit_c6_nibble26_sum= sctag2_dc_cam_hit_c6[104] + sctag2_dc_cam_hit_c6[105] +
sctag2_dc_cam_hit_c6[106] + sctag2_dc_cam_hit_c6[107] +
sctag2_ic_cam_hit_c6[104] + sctag2_ic_cam_hit_c6[105] +
sctag2_ic_cam_hit_c6[106] + sctag2_ic_cam_hit_c6[107];
//----------------------------------------------------------------------------------------
wire [2:0] sctag2_dc_cam_hit_c6_nibble27_sum = sctag2_dc_cam_hit_c6[108] + sctag2_dc_cam_hit_c6[109] +
sctag2_dc_cam_hit_c6[110] + sctag2_dc_cam_hit_c6[111];
wire [2:0] sctag2_ic_cam_hit_c6_nibble27_sum = sctag2_ic_cam_hit_c6[108] + sctag2_ic_cam_hit_c6[109] +
sctag2_ic_cam_hit_c6[110] + sctag2_ic_cam_hit_c6[111];
wire [3:0] sctag2_both_cam_hit_c6_nibble27_sum= sctag2_dc_cam_hit_c6[108] + sctag2_dc_cam_hit_c6[109] +
sctag2_dc_cam_hit_c6[110] + sctag2_dc_cam_hit_c6[111] +
sctag2_ic_cam_hit_c6[108] + sctag2_ic_cam_hit_c6[109] +
sctag2_ic_cam_hit_c6[110] + sctag2_ic_cam_hit_c6[111];
//----------------------------------------------------------------------------------------
wire [2:0] sctag2_dc_cam_hit_c6_nibble28_sum = sctag2_dc_cam_hit_c6[112] + sctag2_dc_cam_hit_c6[113] +
sctag2_dc_cam_hit_c6[114] + sctag2_dc_cam_hit_c6[115];
wire [2:0] sctag2_ic_cam_hit_c6_nibble28_sum = sctag2_ic_cam_hit_c6[112] + sctag2_ic_cam_hit_c6[113] +
sctag2_ic_cam_hit_c6[114] + sctag2_ic_cam_hit_c6[115];
wire [3:0] sctag2_both_cam_hit_c6_nibble28_sum= sctag2_dc_cam_hit_c6[112] + sctag2_dc_cam_hit_c6[113] +
sctag2_dc_cam_hit_c6[114] + sctag2_dc_cam_hit_c6[115] +
sctag2_ic_cam_hit_c6[112] + sctag2_ic_cam_hit_c6[113] +
sctag2_ic_cam_hit_c6[114] + sctag2_ic_cam_hit_c6[115];
//----------------------------------------------------------------------------------------
wire [2:0] sctag2_dc_cam_hit_c6_nibble29_sum = sctag2_dc_cam_hit_c6[116] + sctag2_dc_cam_hit_c6[117] +
sctag2_dc_cam_hit_c6[118] + sctag2_dc_cam_hit_c6[119];
wire [2:0] sctag2_ic_cam_hit_c6_nibble29_sum = sctag2_ic_cam_hit_c6[116] + sctag2_ic_cam_hit_c6[117] +
sctag2_ic_cam_hit_c6[118] + sctag2_ic_cam_hit_c6[119];
wire [3:0] sctag2_both_cam_hit_c6_nibble29_sum= sctag2_dc_cam_hit_c6[116] + sctag2_dc_cam_hit_c6[117] +
sctag2_dc_cam_hit_c6[118] + sctag2_dc_cam_hit_c6[119] +
sctag2_ic_cam_hit_c6[116] + sctag2_ic_cam_hit_c6[117] +
sctag2_ic_cam_hit_c6[118] + sctag2_ic_cam_hit_c6[119];
//----------------------------------------------------------------------------------------
wire [2:0] sctag2_dc_cam_hit_c6_nibble30_sum = sctag2_dc_cam_hit_c6[120] + sctag2_dc_cam_hit_c6[121] +
sctag2_dc_cam_hit_c6[122] + sctag2_dc_cam_hit_c6[123];
wire [2:0] sctag2_ic_cam_hit_c6_nibble30_sum = sctag2_ic_cam_hit_c6[120] + sctag2_ic_cam_hit_c6[121] +
sctag2_ic_cam_hit_c6[122] + sctag2_ic_cam_hit_c6[123];
wire [3:0] sctag2_both_cam_hit_c6_nibble30_sum= sctag2_dc_cam_hit_c6[120] + sctag2_dc_cam_hit_c6[121] +
sctag2_dc_cam_hit_c6[122] + sctag2_dc_cam_hit_c6[123] +
sctag2_ic_cam_hit_c6[120] + sctag2_ic_cam_hit_c6[121] +
sctag2_ic_cam_hit_c6[122] + sctag2_ic_cam_hit_c6[123];
//----------------------------------------------------------------------------------------
wire [2:0] sctag2_dc_cam_hit_c6_nibble31_sum = sctag2_dc_cam_hit_c6[124] + sctag2_dc_cam_hit_c6[125] +
sctag2_dc_cam_hit_c6[126] + sctag2_dc_cam_hit_c6[127];
wire [2:0] sctag2_ic_cam_hit_c6_nibble31_sum = sctag2_ic_cam_hit_c6[124] + sctag2_ic_cam_hit_c6[125] +
sctag2_ic_cam_hit_c6[126] + sctag2_ic_cam_hit_c6[127];
wire [3:0] sctag2_both_cam_hit_c6_nibble31_sum= sctag2_dc_cam_hit_c6[124] + sctag2_dc_cam_hit_c6[125] +
sctag2_dc_cam_hit_c6[126] + sctag2_dc_cam_hit_c6[127] +
sctag2_ic_cam_hit_c6[124] + sctag2_ic_cam_hit_c6[125] +
sctag2_ic_cam_hit_c6[126] + sctag2_ic_cam_hit_c6[127];
wire [7:0] sctag3_cpx_req_cq = `TOP_MEMORY.sctag3_cpx_req_cq[7:0];
wire [7:0] sctag3_cpx_atom_cq = `TOP_MEMORY.sctag3_cpx_atom_cq;
wire [`CPX_WIDTH-1:0] sctag3_cpx_data_ca = `TOP_MEMORY.sctag3_cpx_data_ca[`CPX_WIDTH-1:0];
wire sctag3_pcx_stall_pq = `TOP_MEMORY.sctag3_pcx_stall_pq;
reg [7:0] sctag3_cpx_req_cq_d1; // delayed by 1
reg [7:0] sctag3_cpx_req_cq_d2; // delayed by 2
reg [7:0] sctag3_cpx_atom_cq_d1; // delayed by 1
reg [7:0] sctag3_cpx_atom_cq_d2; // delayed by 2
reg [127:0] sctag3_cpx_type_str; // in string format
reg [3:0] sctag3_cpx_type; // packet type
reg sctag3_dc_lkup_c5;
reg sctag3_ic_lkup_c5;
reg sctag3_dc_lkup_c6;
reg sctag3_ic_lkup_c6;
wire [3:0] sctag3_dc_lkup_panel_dec_c4 = `TOP_MEMORY.sctag3.dirrep.dc_lkup_panel_dec_c4[3:0];
wire [3:0] sctag3_dc_lkup_row_dec_c4 = `TOP_MEMORY.sctag3.dirrep.dc_lkup_row_dec_c4[3:0];
wire [3:0] sctag3_ic_lkup_panel_dec_c4 = `TOP_MEMORY.sctag3.dirrep.ic_lkup_panel_dec_c4[3:0];
wire [3:0] sctag3_ic_lkup_row_dec_c4 = `TOP_MEMORY.sctag3.dirrep.ic_lkup_row_dec_c4[3:0];
wire [127:0] sctag3_dc_cam_hit_c6 = `TOP_MEMORY.sctag3.dirvec_dp.dc_cam_hit_c6[127:0];
wire [127:0] sctag3_ic_cam_hit_c6 = `TOP_MEMORY.sctag3.dirvec_dp.ic_cam_hit_c6[127:0];
//----------------------------------------------------------------------------------------
wire [2:0] sctag3_dc_cam_hit_c6_nibble0_sum = sctag3_dc_cam_hit_c6[0] + sctag3_dc_cam_hit_c6[1] +
sctag3_dc_cam_hit_c6[2] + sctag3_dc_cam_hit_c6[3];
wire [2:0] sctag3_ic_cam_hit_c6_nibble0_sum = sctag3_ic_cam_hit_c6[0] + sctag3_ic_cam_hit_c6[1] +
sctag3_ic_cam_hit_c6[2] + sctag3_ic_cam_hit_c6[3];
wire [3:0] sctag3_both_cam_hit_c6_nibble0_sum= sctag3_dc_cam_hit_c6[0] + sctag3_dc_cam_hit_c6[1] +
sctag3_dc_cam_hit_c6[2] + sctag3_dc_cam_hit_c6[3] +
sctag3_ic_cam_hit_c6[0] + sctag3_ic_cam_hit_c6[1] +
sctag3_ic_cam_hit_c6[2] + sctag3_ic_cam_hit_c6[3];
//----------------------------------------------------------------------------------------
wire [2:0] sctag3_dc_cam_hit_c6_nibble1_sum = sctag3_dc_cam_hit_c6[4] + sctag3_dc_cam_hit_c6[5] +
sctag3_dc_cam_hit_c6[6] + sctag3_dc_cam_hit_c6[7];
wire [2:0] sctag3_ic_cam_hit_c6_nibble1_sum = sctag3_ic_cam_hit_c6[4] + sctag3_ic_cam_hit_c6[5] +
sctag3_ic_cam_hit_c6[6] + sctag3_ic_cam_hit_c6[7];
wire [3:0] sctag3_both_cam_hit_c6_nibble1_sum= sctag3_dc_cam_hit_c6[4] + sctag3_dc_cam_hit_c6[5] +
sctag3_dc_cam_hit_c6[6] + sctag3_dc_cam_hit_c6[7] +
sctag3_ic_cam_hit_c6[4] + sctag3_ic_cam_hit_c6[5] +
sctag3_ic_cam_hit_c6[6] + sctag3_ic_cam_hit_c6[7];
//----------------------------------------------------------------------------------------
wire [2:0] sctag3_dc_cam_hit_c6_nibble2_sum = sctag3_dc_cam_hit_c6[8] + sctag3_dc_cam_hit_c6[9] +
sctag3_dc_cam_hit_c6[10] + sctag3_dc_cam_hit_c6[11];
wire [2:0] sctag3_ic_cam_hit_c6_nibble2_sum = sctag3_ic_cam_hit_c6[8] + sctag3_ic_cam_hit_c6[9] +
sctag3_ic_cam_hit_c6[10] + sctag3_ic_cam_hit_c6[11];
wire [3:0] sctag3_both_cam_hit_c6_nibble2_sum= sctag3_dc_cam_hit_c6[8] + sctag3_dc_cam_hit_c6[9] +
sctag3_dc_cam_hit_c6[10] + sctag3_dc_cam_hit_c6[11] +
sctag3_ic_cam_hit_c6[8] + sctag3_ic_cam_hit_c6[9] +
sctag3_ic_cam_hit_c6[10] + sctag3_ic_cam_hit_c6[11];
//----------------------------------------------------------------------------------------
wire [2:0] sctag3_dc_cam_hit_c6_nibble3_sum = sctag3_dc_cam_hit_c6[12] + sctag3_dc_cam_hit_c6[13] +
sctag3_dc_cam_hit_c6[14] + sctag3_dc_cam_hit_c6[15];
wire [2:0] sctag3_ic_cam_hit_c6_nibble3_sum = sctag3_ic_cam_hit_c6[12] + sctag3_ic_cam_hit_c6[13] +
sctag3_ic_cam_hit_c6[14] + sctag3_ic_cam_hit_c6[15];
wire [3:0] sctag3_both_cam_hit_c6_nibble3_sum= sctag3_dc_cam_hit_c6[12] + sctag3_dc_cam_hit_c6[13] +
sctag3_dc_cam_hit_c6[14] + sctag3_dc_cam_hit_c6[15] +
sctag3_ic_cam_hit_c6[12] + sctag3_ic_cam_hit_c6[13] +
sctag3_ic_cam_hit_c6[14] + sctag3_ic_cam_hit_c6[15];
//----------------------------------------------------------------------------------------
wire [2:0] sctag3_dc_cam_hit_c6_nibble4_sum = sctag3_dc_cam_hit_c6[16] + sctag3_dc_cam_hit_c6[17] +
sctag3_dc_cam_hit_c6[18] + sctag3_dc_cam_hit_c6[19];
wire [2:0] sctag3_ic_cam_hit_c6_nibble4_sum = sctag3_ic_cam_hit_c6[16] + sctag3_ic_cam_hit_c6[17] +
sctag3_ic_cam_hit_c6[18] + sctag3_ic_cam_hit_c6[19];
wire [3:0] sctag3_both_cam_hit_c6_nibble4_sum= sctag3_dc_cam_hit_c6[16] + sctag3_dc_cam_hit_c6[17] +
sctag3_dc_cam_hit_c6[18] + sctag3_dc_cam_hit_c6[19] +
sctag3_ic_cam_hit_c6[16] + sctag3_ic_cam_hit_c6[17] +
sctag3_ic_cam_hit_c6[18] + sctag3_ic_cam_hit_c6[19];
//----------------------------------------------------------------------------------------
wire [2:0] sctag3_dc_cam_hit_c6_nibble5_sum = sctag3_dc_cam_hit_c6[20] + sctag3_dc_cam_hit_c6[21] +
sctag3_dc_cam_hit_c6[22] + sctag3_dc_cam_hit_c6[23];
wire [2:0] sctag3_ic_cam_hit_c6_nibble5_sum = sctag3_ic_cam_hit_c6[20] + sctag3_ic_cam_hit_c6[21] +
sctag3_ic_cam_hit_c6[22] + sctag3_ic_cam_hit_c6[23];
wire [3:0] sctag3_both_cam_hit_c6_nibble5_sum= sctag3_dc_cam_hit_c6[20] + sctag3_dc_cam_hit_c6[21] +
sctag3_dc_cam_hit_c6[22] + sctag3_dc_cam_hit_c6[23] +
sctag3_ic_cam_hit_c6[20] + sctag3_ic_cam_hit_c6[21] +
sctag3_ic_cam_hit_c6[22] + sctag3_ic_cam_hit_c6[23];
//----------------------------------------------------------------------------------------
wire [2:0] sctag3_dc_cam_hit_c6_nibble6_sum = sctag3_dc_cam_hit_c6[24] + sctag3_dc_cam_hit_c6[25] +
sctag3_dc_cam_hit_c6[26] + sctag3_dc_cam_hit_c6[27];
wire [2:0] sctag3_ic_cam_hit_c6_nibble6_sum = sctag3_ic_cam_hit_c6[24] + sctag3_ic_cam_hit_c6[25] +
sctag3_ic_cam_hit_c6[26] + sctag3_ic_cam_hit_c6[27];
wire [3:0] sctag3_both_cam_hit_c6_nibble6_sum= sctag3_dc_cam_hit_c6[24] + sctag3_dc_cam_hit_c6[25] +
sctag3_dc_cam_hit_c6[26] + sctag3_dc_cam_hit_c6[27] +
sctag3_ic_cam_hit_c6[24] + sctag3_ic_cam_hit_c6[25] +
sctag3_ic_cam_hit_c6[26] + sctag3_ic_cam_hit_c6[27];
//----------------------------------------------------------------------------------------
wire [2:0] sctag3_dc_cam_hit_c6_nibble7_sum = sctag3_dc_cam_hit_c6[28] + sctag3_dc_cam_hit_c6[29] +
sctag3_dc_cam_hit_c6[30] + sctag3_dc_cam_hit_c6[31];
wire [2:0] sctag3_ic_cam_hit_c6_nibble7_sum = sctag3_ic_cam_hit_c6[28] + sctag3_ic_cam_hit_c6[29] +
sctag3_ic_cam_hit_c6[30] + sctag3_ic_cam_hit_c6[31];
wire [3:0] sctag3_both_cam_hit_c6_nibble7_sum= sctag3_dc_cam_hit_c6[28] + sctag3_dc_cam_hit_c6[29] +
sctag3_dc_cam_hit_c6[30] + sctag3_dc_cam_hit_c6[31] +
sctag3_ic_cam_hit_c6[28] + sctag3_ic_cam_hit_c6[29] +
sctag3_ic_cam_hit_c6[30] + sctag3_ic_cam_hit_c6[31];
//----------------------------------------------------------------------------------------
wire [2:0] sctag3_dc_cam_hit_c6_nibble8_sum = sctag3_dc_cam_hit_c6[32] + sctag3_dc_cam_hit_c6[33] +
sctag3_dc_cam_hit_c6[34] + sctag3_dc_cam_hit_c6[35];
wire [2:0] sctag3_ic_cam_hit_c6_nibble8_sum = sctag3_ic_cam_hit_c6[32] + sctag3_ic_cam_hit_c6[33] +
sctag3_ic_cam_hit_c6[34] + sctag3_ic_cam_hit_c6[35];
wire [3:0] sctag3_both_cam_hit_c6_nibble8_sum= sctag3_dc_cam_hit_c6[32] + sctag3_dc_cam_hit_c6[33] +
sctag3_dc_cam_hit_c6[34] + sctag3_dc_cam_hit_c6[35] +
sctag3_ic_cam_hit_c6[32] + sctag3_ic_cam_hit_c6[33] +
sctag3_ic_cam_hit_c6[34] + sctag3_ic_cam_hit_c6[35];
//----------------------------------------------------------------------------------------
wire [2:0] sctag3_dc_cam_hit_c6_nibble9_sum = sctag3_dc_cam_hit_c6[36] + sctag3_dc_cam_hit_c6[37] +
sctag3_dc_cam_hit_c6[38] + sctag3_dc_cam_hit_c6[39];
wire [2:0] sctag3_ic_cam_hit_c6_nibble9_sum = sctag3_ic_cam_hit_c6[36] + sctag3_ic_cam_hit_c6[37] +
sctag3_ic_cam_hit_c6[38] + sctag3_ic_cam_hit_c6[39];
wire [3:0] sctag3_both_cam_hit_c6_nibble9_sum= sctag3_dc_cam_hit_c6[36] + sctag3_dc_cam_hit_c6[37] +
sctag3_dc_cam_hit_c6[38] + sctag3_dc_cam_hit_c6[39] +
sctag3_ic_cam_hit_c6[36] + sctag3_ic_cam_hit_c6[37] +
sctag3_ic_cam_hit_c6[38] + sctag3_ic_cam_hit_c6[39];
//----------------------------------------------------------------------------------------
wire [2:0] sctag3_dc_cam_hit_c6_nibble10_sum = sctag3_dc_cam_hit_c6[40] + sctag3_dc_cam_hit_c6[41] +
sctag3_dc_cam_hit_c6[42] + sctag3_dc_cam_hit_c6[43];
wire [2:0] sctag3_ic_cam_hit_c6_nibble10_sum = sctag3_ic_cam_hit_c6[40] + sctag3_ic_cam_hit_c6[41] +
sctag3_ic_cam_hit_c6[42] + sctag3_ic_cam_hit_c6[43];
wire [3:0] sctag3_both_cam_hit_c6_nibble10_sum= sctag3_dc_cam_hit_c6[40] + sctag3_dc_cam_hit_c6[41] +
sctag3_dc_cam_hit_c6[42] + sctag3_dc_cam_hit_c6[43] +
sctag3_ic_cam_hit_c6[40] + sctag3_ic_cam_hit_c6[41] +
sctag3_ic_cam_hit_c6[42] + sctag3_ic_cam_hit_c6[43];
//----------------------------------------------------------------------------------------
wire [2:0] sctag3_dc_cam_hit_c6_nibble11_sum = sctag3_dc_cam_hit_c6[44] + sctag3_dc_cam_hit_c6[45] +
sctag3_dc_cam_hit_c6[46] + sctag3_dc_cam_hit_c6[47];
wire [2:0] sctag3_ic_cam_hit_c6_nibble11_sum = sctag3_ic_cam_hit_c6[44] + sctag3_ic_cam_hit_c6[45] +
sctag3_ic_cam_hit_c6[46] + sctag3_ic_cam_hit_c6[47];
wire [3:0] sctag3_both_cam_hit_c6_nibble11_sum= sctag3_dc_cam_hit_c6[44] + sctag3_dc_cam_hit_c6[45] +
sctag3_dc_cam_hit_c6[46] + sctag3_dc_cam_hit_c6[47] +
sctag3_ic_cam_hit_c6[44] + sctag3_ic_cam_hit_c6[45] +
sctag3_ic_cam_hit_c6[46] + sctag3_ic_cam_hit_c6[47];
//----------------------------------------------------------------------------------------
wire [2:0] sctag3_dc_cam_hit_c6_nibble12_sum = sctag3_dc_cam_hit_c6[48] + sctag3_dc_cam_hit_c6[49] +
sctag3_dc_cam_hit_c6[50] + sctag3_dc_cam_hit_c6[51];
wire [2:0] sctag3_ic_cam_hit_c6_nibble12_sum = sctag3_ic_cam_hit_c6[48] + sctag3_ic_cam_hit_c6[49] +
sctag3_ic_cam_hit_c6[50] + sctag3_ic_cam_hit_c6[51];
wire [3:0] sctag3_both_cam_hit_c6_nibble12_sum= sctag3_dc_cam_hit_c6[48] + sctag3_dc_cam_hit_c6[49] +
sctag3_dc_cam_hit_c6[50] + sctag3_dc_cam_hit_c6[51] +
sctag3_ic_cam_hit_c6[48] + sctag3_ic_cam_hit_c6[49] +
sctag3_ic_cam_hit_c6[50] + sctag3_ic_cam_hit_c6[51];
//----------------------------------------------------------------------------------------
wire [2:0] sctag3_dc_cam_hit_c6_nibble13_sum = sctag3_dc_cam_hit_c6[52] + sctag3_dc_cam_hit_c6[53] +
sctag3_dc_cam_hit_c6[54] + sctag3_dc_cam_hit_c6[55];
wire [2:0] sctag3_ic_cam_hit_c6_nibble13_sum = sctag3_ic_cam_hit_c6[52] + sctag3_ic_cam_hit_c6[53] +
sctag3_ic_cam_hit_c6[54] + sctag3_ic_cam_hit_c6[55];
wire [3:0] sctag3_both_cam_hit_c6_nibble13_sum= sctag3_dc_cam_hit_c6[52] + sctag3_dc_cam_hit_c6[53] +
sctag3_dc_cam_hit_c6[54] + sctag3_dc_cam_hit_c6[55] +
sctag3_ic_cam_hit_c6[52] + sctag3_ic_cam_hit_c6[53] +
sctag3_ic_cam_hit_c6[54] + sctag3_ic_cam_hit_c6[55];
//----------------------------------------------------------------------------------------
wire [2:0] sctag3_dc_cam_hit_c6_nibble14_sum = sctag3_dc_cam_hit_c6[56] + sctag3_dc_cam_hit_c6[57] +
sctag3_dc_cam_hit_c6[58] + sctag3_dc_cam_hit_c6[59];
wire [2:0] sctag3_ic_cam_hit_c6_nibble14_sum = sctag3_ic_cam_hit_c6[56] + sctag3_ic_cam_hit_c6[57] +
sctag3_ic_cam_hit_c6[58] + sctag3_ic_cam_hit_c6[59];
wire [3:0] sctag3_both_cam_hit_c6_nibble14_sum= sctag3_dc_cam_hit_c6[56] + sctag3_dc_cam_hit_c6[57] +
sctag3_dc_cam_hit_c6[58] + sctag3_dc_cam_hit_c6[59] +
sctag3_ic_cam_hit_c6[56] + sctag3_ic_cam_hit_c6[57] +
sctag3_ic_cam_hit_c6[58] + sctag3_ic_cam_hit_c6[59];
//----------------------------------------------------------------------------------------
wire [2:0] sctag3_dc_cam_hit_c6_nibble15_sum = sctag3_dc_cam_hit_c6[60] + sctag3_dc_cam_hit_c6[61] +
sctag3_dc_cam_hit_c6[62] + sctag3_dc_cam_hit_c6[63];
wire [2:0] sctag3_ic_cam_hit_c6_nibble15_sum = sctag3_ic_cam_hit_c6[60] + sctag3_ic_cam_hit_c6[61] +
sctag3_ic_cam_hit_c6[62] + sctag3_ic_cam_hit_c6[63];
wire [3:0] sctag3_both_cam_hit_c6_nibble15_sum= sctag3_dc_cam_hit_c6[60] + sctag3_dc_cam_hit_c6[61] +
sctag3_dc_cam_hit_c6[62] + sctag3_dc_cam_hit_c6[63] +
sctag3_ic_cam_hit_c6[60] + sctag3_ic_cam_hit_c6[61] +
sctag3_ic_cam_hit_c6[62] + sctag3_ic_cam_hit_c6[63];
//----------------------------------------------------------------------------------------
wire [2:0] sctag3_dc_cam_hit_c6_nibble16_sum = sctag3_dc_cam_hit_c6[64] + sctag3_dc_cam_hit_c6[65] +
sctag3_dc_cam_hit_c6[66] + sctag3_dc_cam_hit_c6[67];
wire [2:0] sctag3_ic_cam_hit_c6_nibble16_sum = sctag3_ic_cam_hit_c6[64] + sctag3_ic_cam_hit_c6[65] +
sctag3_ic_cam_hit_c6[66] + sctag3_ic_cam_hit_c6[67];
wire [3:0] sctag3_both_cam_hit_c6_nibble16_sum= sctag3_dc_cam_hit_c6[64] + sctag3_dc_cam_hit_c6[65] +
sctag3_dc_cam_hit_c6[66] + sctag3_dc_cam_hit_c6[67] +
sctag3_ic_cam_hit_c6[64] + sctag3_ic_cam_hit_c6[65] +
sctag3_ic_cam_hit_c6[66] + sctag3_ic_cam_hit_c6[67];
//----------------------------------------------------------------------------------------
wire [2:0] sctag3_dc_cam_hit_c6_nibble17_sum = sctag3_dc_cam_hit_c6[68] + sctag3_dc_cam_hit_c6[69] +
sctag3_dc_cam_hit_c6[70] + sctag3_dc_cam_hit_c6[71];
wire [2:0] sctag3_ic_cam_hit_c6_nibble17_sum = sctag3_ic_cam_hit_c6[68] + sctag3_ic_cam_hit_c6[69] +
sctag3_ic_cam_hit_c6[70] + sctag3_ic_cam_hit_c6[71];
wire [3:0] sctag3_both_cam_hit_c6_nibble17_sum= sctag3_dc_cam_hit_c6[68] + sctag3_dc_cam_hit_c6[69] +
sctag3_dc_cam_hit_c6[70] + sctag3_dc_cam_hit_c6[71] +
sctag3_ic_cam_hit_c6[68] + sctag3_ic_cam_hit_c6[69] +
sctag3_ic_cam_hit_c6[70] + sctag3_ic_cam_hit_c6[71];
//----------------------------------------------------------------------------------------
wire [2:0] sctag3_dc_cam_hit_c6_nibble18_sum = sctag3_dc_cam_hit_c6[72] + sctag3_dc_cam_hit_c6[73] +
sctag3_dc_cam_hit_c6[74] + sctag3_dc_cam_hit_c6[75];
wire [2:0] sctag3_ic_cam_hit_c6_nibble18_sum = sctag3_ic_cam_hit_c6[72] + sctag3_ic_cam_hit_c6[73] +
sctag3_ic_cam_hit_c6[74] + sctag3_ic_cam_hit_c6[75];
wire [3:0] sctag3_both_cam_hit_c6_nibble18_sum= sctag3_dc_cam_hit_c6[72] + sctag3_dc_cam_hit_c6[73] +
sctag3_dc_cam_hit_c6[74] + sctag3_dc_cam_hit_c6[75] +
sctag3_ic_cam_hit_c6[72] + sctag3_ic_cam_hit_c6[73] +
sctag3_ic_cam_hit_c6[74] + sctag3_ic_cam_hit_c6[75];
//----------------------------------------------------------------------------------------
wire [2:0] sctag3_dc_cam_hit_c6_nibble19_sum = sctag3_dc_cam_hit_c6[76] + sctag3_dc_cam_hit_c6[77] +
sctag3_dc_cam_hit_c6[78] + sctag3_dc_cam_hit_c6[79];
wire [2:0] sctag3_ic_cam_hit_c6_nibble19_sum = sctag3_ic_cam_hit_c6[76] + sctag3_ic_cam_hit_c6[77] +
sctag3_ic_cam_hit_c6[78] + sctag3_ic_cam_hit_c6[79];
wire [3:0] sctag3_both_cam_hit_c6_nibble19_sum= sctag3_dc_cam_hit_c6[76] + sctag3_dc_cam_hit_c6[77] +
sctag3_dc_cam_hit_c6[78] + sctag3_dc_cam_hit_c6[79] +
sctag3_ic_cam_hit_c6[76] + sctag3_ic_cam_hit_c6[77] +
sctag3_ic_cam_hit_c6[78] + sctag3_ic_cam_hit_c6[79];
//----------------------------------------------------------------------------------------
wire [2:0] sctag3_dc_cam_hit_c6_nibble20_sum = sctag3_dc_cam_hit_c6[80] + sctag3_dc_cam_hit_c6[81] +
sctag3_dc_cam_hit_c6[82] + sctag3_dc_cam_hit_c6[83];
wire [2:0] sctag3_ic_cam_hit_c6_nibble20_sum = sctag3_ic_cam_hit_c6[80] + sctag3_ic_cam_hit_c6[81] +
sctag3_ic_cam_hit_c6[82] + sctag3_ic_cam_hit_c6[83];
wire [3:0] sctag3_both_cam_hit_c6_nibble20_sum= sctag3_dc_cam_hit_c6[80] + sctag3_dc_cam_hit_c6[81] +
sctag3_dc_cam_hit_c6[82] + sctag3_dc_cam_hit_c6[83] +
sctag3_ic_cam_hit_c6[80] + sctag3_ic_cam_hit_c6[81] +
sctag3_ic_cam_hit_c6[82] + sctag3_ic_cam_hit_c6[83];
//----------------------------------------------------------------------------------------
wire [2:0] sctag3_dc_cam_hit_c6_nibble21_sum = sctag3_dc_cam_hit_c6[84] + sctag3_dc_cam_hit_c6[85] +
sctag3_dc_cam_hit_c6[86] + sctag3_dc_cam_hit_c6[87];
wire [2:0] sctag3_ic_cam_hit_c6_nibble21_sum = sctag3_ic_cam_hit_c6[84] + sctag3_ic_cam_hit_c6[85] +
sctag3_ic_cam_hit_c6[86] + sctag3_ic_cam_hit_c6[87];
wire [3:0] sctag3_both_cam_hit_c6_nibble21_sum= sctag3_dc_cam_hit_c6[84] + sctag3_dc_cam_hit_c6[85] +
sctag3_dc_cam_hit_c6[86] + sctag3_dc_cam_hit_c6[87] +
sctag3_ic_cam_hit_c6[84] + sctag3_ic_cam_hit_c6[85] +
sctag3_ic_cam_hit_c6[86] + sctag3_ic_cam_hit_c6[87];
//----------------------------------------------------------------------------------------
wire [2:0] sctag3_dc_cam_hit_c6_nibble22_sum = sctag3_dc_cam_hit_c6[88] + sctag3_dc_cam_hit_c6[89] +
sctag3_dc_cam_hit_c6[90] + sctag3_dc_cam_hit_c6[91];
wire [2:0] sctag3_ic_cam_hit_c6_nibble22_sum = sctag3_ic_cam_hit_c6[88] + sctag3_ic_cam_hit_c6[89] +
sctag3_ic_cam_hit_c6[90] + sctag3_ic_cam_hit_c6[91];
wire [3:0] sctag3_both_cam_hit_c6_nibble22_sum= sctag3_dc_cam_hit_c6[88] + sctag3_dc_cam_hit_c6[89] +
sctag3_dc_cam_hit_c6[90] + sctag3_dc_cam_hit_c6[91] +
sctag3_ic_cam_hit_c6[88] + sctag3_ic_cam_hit_c6[89] +
sctag3_ic_cam_hit_c6[90] + sctag3_ic_cam_hit_c6[91];
//----------------------------------------------------------------------------------------
wire [2:0] sctag3_dc_cam_hit_c6_nibble23_sum = sctag3_dc_cam_hit_c6[92] + sctag3_dc_cam_hit_c6[93] +
sctag3_dc_cam_hit_c6[94] + sctag3_dc_cam_hit_c6[95];
wire [2:0] sctag3_ic_cam_hit_c6_nibble23_sum = sctag3_ic_cam_hit_c6[92] + sctag3_ic_cam_hit_c6[93] +
sctag3_ic_cam_hit_c6[94] + sctag3_ic_cam_hit_c6[95];
wire [3:0] sctag3_both_cam_hit_c6_nibble23_sum= sctag3_dc_cam_hit_c6[92] + sctag3_dc_cam_hit_c6[93] +
sctag3_dc_cam_hit_c6[94] + sctag3_dc_cam_hit_c6[95] +
sctag3_ic_cam_hit_c6[92] + sctag3_ic_cam_hit_c6[93] +
sctag3_ic_cam_hit_c6[94] + sctag3_ic_cam_hit_c6[95];
//----------------------------------------------------------------------------------------
wire [2:0] sctag3_dc_cam_hit_c6_nibble24_sum = sctag3_dc_cam_hit_c6[96] + sctag3_dc_cam_hit_c6[97] +
sctag3_dc_cam_hit_c6[98] + sctag3_dc_cam_hit_c6[99];
wire [2:0] sctag3_ic_cam_hit_c6_nibble24_sum = sctag3_ic_cam_hit_c6[96] + sctag3_ic_cam_hit_c6[97] +
sctag3_ic_cam_hit_c6[98] + sctag3_ic_cam_hit_c6[99];
wire [3:0] sctag3_both_cam_hit_c6_nibble24_sum= sctag3_dc_cam_hit_c6[96] + sctag3_dc_cam_hit_c6[97] +
sctag3_dc_cam_hit_c6[98] + sctag3_dc_cam_hit_c6[99] +
sctag3_ic_cam_hit_c6[96] + sctag3_ic_cam_hit_c6[97] +
sctag3_ic_cam_hit_c6[98] + sctag3_ic_cam_hit_c6[99];
//----------------------------------------------------------------------------------------
wire [2:0] sctag3_dc_cam_hit_c6_nibble25_sum = sctag3_dc_cam_hit_c6[100] + sctag3_dc_cam_hit_c6[101] +
sctag3_dc_cam_hit_c6[102] + sctag3_dc_cam_hit_c6[103];
wire [2:0] sctag3_ic_cam_hit_c6_nibble25_sum = sctag3_ic_cam_hit_c6[100] + sctag3_ic_cam_hit_c6[101] +
sctag3_ic_cam_hit_c6[102] + sctag3_ic_cam_hit_c6[103];
wire [3:0] sctag3_both_cam_hit_c6_nibble25_sum= sctag3_dc_cam_hit_c6[100] + sctag3_dc_cam_hit_c6[101] +
sctag3_dc_cam_hit_c6[102] + sctag3_dc_cam_hit_c6[103] +
sctag3_ic_cam_hit_c6[100] + sctag3_ic_cam_hit_c6[101] +
sctag3_ic_cam_hit_c6[102] + sctag3_ic_cam_hit_c6[103];
//----------------------------------------------------------------------------------------
wire [2:0] sctag3_dc_cam_hit_c6_nibble26_sum = sctag3_dc_cam_hit_c6[104] + sctag3_dc_cam_hit_c6[105] +
sctag3_dc_cam_hit_c6[106] + sctag3_dc_cam_hit_c6[107];
wire [2:0] sctag3_ic_cam_hit_c6_nibble26_sum = sctag3_ic_cam_hit_c6[104] + sctag3_ic_cam_hit_c6[105] +
sctag3_ic_cam_hit_c6[106] + sctag3_ic_cam_hit_c6[107];
wire [3:0] sctag3_both_cam_hit_c6_nibble26_sum= sctag3_dc_cam_hit_c6[104] + sctag3_dc_cam_hit_c6[105] +
sctag3_dc_cam_hit_c6[106] + sctag3_dc_cam_hit_c6[107] +
sctag3_ic_cam_hit_c6[104] + sctag3_ic_cam_hit_c6[105] +
sctag3_ic_cam_hit_c6[106] + sctag3_ic_cam_hit_c6[107];
//----------------------------------------------------------------------------------------
wire [2:0] sctag3_dc_cam_hit_c6_nibble27_sum = sctag3_dc_cam_hit_c6[108] + sctag3_dc_cam_hit_c6[109] +
sctag3_dc_cam_hit_c6[110] + sctag3_dc_cam_hit_c6[111];
wire [2:0] sctag3_ic_cam_hit_c6_nibble27_sum = sctag3_ic_cam_hit_c6[108] + sctag3_ic_cam_hit_c6[109] +
sctag3_ic_cam_hit_c6[110] + sctag3_ic_cam_hit_c6[111];
wire [3:0] sctag3_both_cam_hit_c6_nibble27_sum= sctag3_dc_cam_hit_c6[108] + sctag3_dc_cam_hit_c6[109] +
sctag3_dc_cam_hit_c6[110] + sctag3_dc_cam_hit_c6[111] +
sctag3_ic_cam_hit_c6[108] + sctag3_ic_cam_hit_c6[109] +
sctag3_ic_cam_hit_c6[110] + sctag3_ic_cam_hit_c6[111];
//----------------------------------------------------------------------------------------
wire [2:0] sctag3_dc_cam_hit_c6_nibble28_sum = sctag3_dc_cam_hit_c6[112] + sctag3_dc_cam_hit_c6[113] +
sctag3_dc_cam_hit_c6[114] + sctag3_dc_cam_hit_c6[115];
wire [2:0] sctag3_ic_cam_hit_c6_nibble28_sum = sctag3_ic_cam_hit_c6[112] + sctag3_ic_cam_hit_c6[113] +
sctag3_ic_cam_hit_c6[114] + sctag3_ic_cam_hit_c6[115];
wire [3:0] sctag3_both_cam_hit_c6_nibble28_sum= sctag3_dc_cam_hit_c6[112] + sctag3_dc_cam_hit_c6[113] +
sctag3_dc_cam_hit_c6[114] + sctag3_dc_cam_hit_c6[115] +
sctag3_ic_cam_hit_c6[112] + sctag3_ic_cam_hit_c6[113] +
sctag3_ic_cam_hit_c6[114] + sctag3_ic_cam_hit_c6[115];
//----------------------------------------------------------------------------------------
wire [2:0] sctag3_dc_cam_hit_c6_nibble29_sum = sctag3_dc_cam_hit_c6[116] + sctag3_dc_cam_hit_c6[117] +
sctag3_dc_cam_hit_c6[118] + sctag3_dc_cam_hit_c6[119];
wire [2:0] sctag3_ic_cam_hit_c6_nibble29_sum = sctag3_ic_cam_hit_c6[116] + sctag3_ic_cam_hit_c6[117] +
sctag3_ic_cam_hit_c6[118] + sctag3_ic_cam_hit_c6[119];
wire [3:0] sctag3_both_cam_hit_c6_nibble29_sum= sctag3_dc_cam_hit_c6[116] + sctag3_dc_cam_hit_c6[117] +
sctag3_dc_cam_hit_c6[118] + sctag3_dc_cam_hit_c6[119] +
sctag3_ic_cam_hit_c6[116] + sctag3_ic_cam_hit_c6[117] +
sctag3_ic_cam_hit_c6[118] + sctag3_ic_cam_hit_c6[119];
//----------------------------------------------------------------------------------------
wire [2:0] sctag3_dc_cam_hit_c6_nibble30_sum = sctag3_dc_cam_hit_c6[120] + sctag3_dc_cam_hit_c6[121] +
sctag3_dc_cam_hit_c6[122] + sctag3_dc_cam_hit_c6[123];
wire [2:0] sctag3_ic_cam_hit_c6_nibble30_sum = sctag3_ic_cam_hit_c6[120] + sctag3_ic_cam_hit_c6[121] +
sctag3_ic_cam_hit_c6[122] + sctag3_ic_cam_hit_c6[123];
wire [3:0] sctag3_both_cam_hit_c6_nibble30_sum= sctag3_dc_cam_hit_c6[120] + sctag3_dc_cam_hit_c6[121] +
sctag3_dc_cam_hit_c6[122] + sctag3_dc_cam_hit_c6[123] +
sctag3_ic_cam_hit_c6[120] + sctag3_ic_cam_hit_c6[121] +
sctag3_ic_cam_hit_c6[122] + sctag3_ic_cam_hit_c6[123];
//----------------------------------------------------------------------------------------
wire [2:0] sctag3_dc_cam_hit_c6_nibble31_sum = sctag3_dc_cam_hit_c6[124] + sctag3_dc_cam_hit_c6[125] +
sctag3_dc_cam_hit_c6[126] + sctag3_dc_cam_hit_c6[127];
wire [2:0] sctag3_ic_cam_hit_c6_nibble31_sum = sctag3_ic_cam_hit_c6[124] + sctag3_ic_cam_hit_c6[125] +
sctag3_ic_cam_hit_c6[126] + sctag3_ic_cam_hit_c6[127];
wire [3:0] sctag3_both_cam_hit_c6_nibble31_sum= sctag3_dc_cam_hit_c6[124] + sctag3_dc_cam_hit_c6[125] +
sctag3_dc_cam_hit_c6[126] + sctag3_dc_cam_hit_c6[127] +
sctag3_ic_cam_hit_c6[124] + sctag3_ic_cam_hit_c6[125] +
sctag3_ic_cam_hit_c6[126] + sctag3_ic_cam_hit_c6[127];
// This one is an OR of all 4 SCTAGS
//----------------------------------
wire sctag_pcx_stall_pq = sctag0_pcx_stall_pq | sctag1_pcx_stall_pq | sctag2_pcx_stall_pq | sctag3_pcx_stall_pq;
//--------------------------------------------------------------------------------------
// cpx to spc (sparc) packets
//--------------------------------------------------------------------------------------
wire cpx_spc0_data_vld = `TOP_MEMORY.cpx_spc0_data_cx2[`CPX_WIDTH-1];
wire [`CPX_WIDTH-1:0] cpx_spc0_data_cx2 = `TOP_MEMORY.cpx_spc0_data_cx2[`CPX_WIDTH-1:0];
reg [`CPX_WIDTH-1:0] cpx_spc0_data_cx2_d1; // packet delayed by 1
reg [`CPX_WIDTH-1:0] cpx_spc0_data_cx2_d2; // packet delayed by 2
reg [127:0] spc0_pcx_type_str; // packet type in string format for debug.
reg [127:0] cpx_spc0_type_str; // in string format for debug
wire [3:0] cpx_spc0_type = cpx_spc0_data_vld ? cpx_spc0_data_cx2[`CPX_RQ_HI:`CPX_RQ_LO] :4'h0;
wire cpx_spc0_wyvld = cpx_spc0_data_cx2[`CPX_WYVLD] & cpx_spc0_data_vld;
wire cpx_spc0_st_ack = (cpx_spc0_type == `ST_ACK) | (cpx_spc0_type == `STRST_ACK);
wire cpx_spc0_evict = (cpx_spc0_type == `EVICT_REQ);
reg cpx_spc0_ifill_wyvld;
reg cpx_spc0_dfill_wyvld;
wire cpx_spc0_st_ack_dc_inval_1c_tmp = (cpx_spc0_data_cx2[122:121] == 2'b00) ? cpx_spc0_data_cx2[0] :
(cpx_spc0_data_cx2[122:121] == 2'b01) ? cpx_spc0_data_cx2[32] :
(cpx_spc0_data_cx2[122:121] == 2'b10) ? cpx_spc0_data_cx2[56] :
cpx_spc0_data_cx2[88];
wire [2:0] cpx_spc0_st_ack_dc_inval_1c = {2'b00, cpx_spc0_st_ack & cpx_spc0_st_ack_dc_inval_1c_tmp};
wire cpx_spc0_st_ack_ic_inval_1c_tmp = cpx_spc0_data_cx2[122] ? cpx_spc0_data_cx2[57] : cpx_spc0_data_cx2[1];
wire [2:0] cpx_spc0_st_ack_ic_inval_1c = {2'b00, (cpx_spc0_st_ack & cpx_spc0_st_ack_ic_inval_1c_tmp)};
wire [5:0] cpx_spc0_st_ack_icdc_inval_1c = {6{cpx_spc0_st_ack}} &
{cpx_spc0_st_ack_ic_inval_1c, cpx_spc0_st_ack_dc_inval_1c};
wire [2:0] cpx_spc0_evict_dc_inval_1c = cpx_spc0_data_cx2[0] + cpx_spc0_data_cx2[32] +
cpx_spc0_data_cx2[56] + cpx_spc0_data_cx2[88];
wire [1:0] cpx_spc0_evict_ic_inval_1c = cpx_spc0_data_cx2[1] + cpx_spc0_data_cx2[57];
reg cpx_spc0_evict_d1;
always @(posedge clk)
cpx_spc0_evict_d1 <= cpx_spc0_evict;
wire cpx_spc0_b2b_evict = cpx_spc0_evict_d1 & cpx_spc0_evict;
wire [5:0] cpx_spc0_evict_icdc_inval_1c;
assign cpx_spc0_evict_icdc_inval_1c[4:0]={5{cpx_spc0_evict}} &
{cpx_spc0_evict_ic_inval_1c,cpx_spc0_evict_dc_inval_1c};
assign cpx_spc0_evict_icdc_inval_1c[5] = cpx_spc0_b2b_evict;
wire [5:0] cpx_spc0_st_ack_dc_inval_8c_tmp = (cpx_spc0_data_cx2[122:121] == 2'b00) ? (
cpx_spc0_data_cx2[0] + cpx_spc0_data_cx2[4] +
cpx_spc0_data_cx2[8] + cpx_spc0_data_cx2[12] +
cpx_spc0_data_cx2[16] + cpx_spc0_data_cx2[20] +
cpx_spc0_data_cx2[24] + cpx_spc0_data_cx2[28]
) :
(cpx_spc0_data_cx2[122:121] == 2'b01) ? (
cpx_spc0_data_cx2[32] + cpx_spc0_data_cx2[35] +
cpx_spc0_data_cx2[38] + cpx_spc0_data_cx2[41] +
cpx_spc0_data_cx2[44] + cpx_spc0_data_cx2[47] +
cpx_spc0_data_cx2[50] + cpx_spc0_data_cx2[53]
) :
(cpx_spc0_data_cx2[122:121] == 2'b10) ? (
cpx_spc0_data_cx2[56] + cpx_spc0_data_cx2[60] +
cpx_spc0_data_cx2[64] + cpx_spc0_data_cx2[68] +
cpx_spc0_data_cx2[72] + cpx_spc0_data_cx2[76] +
cpx_spc0_data_cx2[80] + cpx_spc0_data_cx2[84]
) :
( cpx_spc0_data_cx2[88] + cpx_spc0_data_cx2[91] +
cpx_spc0_data_cx2[94] + cpx_spc0_data_cx2[97] +
cpx_spc0_data_cx2[100]+ cpx_spc0_data_cx2[103]+
cpx_spc0_data_cx2[106]+ cpx_spc0_data_cx2[109]
) ;
wire [5:0] cpx_spc0_st_ack_dc_inval_8c = {6{cpx_spc0_st_ack}} & cpx_spc0_st_ack_dc_inval_8c_tmp;
wire [5:0] cpx_spc0_st_ack_ic_inval_8c_tmp = ~cpx_spc0_data_cx2[122] ? (
cpx_spc0_data_cx2[1] + cpx_spc0_data_cx2[5] +
cpx_spc0_data_cx2[9] + cpx_spc0_data_cx2[13] +
cpx_spc0_data_cx2[17] + cpx_spc0_data_cx2[21] +
cpx_spc0_data_cx2[25] + cpx_spc0_data_cx2[29]
) :
( cpx_spc0_data_cx2[57] + cpx_spc0_data_cx2[61] +
cpx_spc0_data_cx2[65] + cpx_spc0_data_cx2[69] +
cpx_spc0_data_cx2[73] + cpx_spc0_data_cx2[77] +
cpx_spc0_data_cx2[81] + cpx_spc0_data_cx2[85]
) ;
wire [5:0] cpx_spc0_st_ack_ic_inval_8c = {4{cpx_spc0_st_ack}} & cpx_spc0_st_ack_ic_inval_8c_tmp;
wire [5:0] cpx_spc0_evict_dc_inval_8c_tmp =
cpx_spc0_data_cx2[0] + cpx_spc0_data_cx2[4] +
cpx_spc0_data_cx2[8] + cpx_spc0_data_cx2[12] +
cpx_spc0_data_cx2[16] + cpx_spc0_data_cx2[20] +
cpx_spc0_data_cx2[24] + cpx_spc0_data_cx2[28] +
cpx_spc0_data_cx2[32] + cpx_spc0_data_cx2[35] +
cpx_spc0_data_cx2[38] + cpx_spc0_data_cx2[41] +
cpx_spc0_data_cx2[44] + cpx_spc0_data_cx2[47] +
cpx_spc0_data_cx2[50] + cpx_spc0_data_cx2[53] +
cpx_spc0_data_cx2[56] + cpx_spc0_data_cx2[60] +
cpx_spc0_data_cx2[64] + cpx_spc0_data_cx2[68] +
cpx_spc0_data_cx2[72] + cpx_spc0_data_cx2[76] +
cpx_spc0_data_cx2[80] + cpx_spc0_data_cx2[84] +
cpx_spc0_data_cx2[88] + cpx_spc0_data_cx2[91] +
cpx_spc0_data_cx2[94] + cpx_spc0_data_cx2[97] +
cpx_spc0_data_cx2[100]+ cpx_spc0_data_cx2[103]+
cpx_spc0_data_cx2[106]+ cpx_spc0_data_cx2[109];
wire [5:0] cpx_spc0_evict_dc_inval_8c = {6{cpx_spc0_evict}} & cpx_spc0_evict_dc_inval_8c_tmp;
wire [5:0] cpx_spc0_evict_ic_inval_8c_tmp =
cpx_spc0_data_cx2[1] + cpx_spc0_data_cx2[5] +
cpx_spc0_data_cx2[9] + cpx_spc0_data_cx2[13] +
cpx_spc0_data_cx2[17] + cpx_spc0_data_cx2[21] +
cpx_spc0_data_cx2[25] + cpx_spc0_data_cx2[29] +
cpx_spc0_data_cx2[57] + cpx_spc0_data_cx2[61] +
cpx_spc0_data_cx2[65] + cpx_spc0_data_cx2[69] +
cpx_spc0_data_cx2[73] + cpx_spc0_data_cx2[77] +
cpx_spc0_data_cx2[81] + cpx_spc0_data_cx2[85];
wire [5:0] cpx_spc0_evict_ic_inval_8c = {6{cpx_spc0_evict}} & cpx_spc0_evict_ic_inval_8c_tmp;
reg [3:0] blk_st_cnt0; // counts the number of block stores without an acknowledge in between
reg [3:0] ini_st_cnt0; // counts the number of init stores without an acknowledge in between
reg st_blkst_mixture0; // a flag set upon detection of block store and normal store mixture.
reg st_inist_mixture0; // a flag set upon detection of init store and normal store mixture.
reg atomic_ret0; // atomic cpx to spc package
reg non_b2b_atomic_ret0; // atomic cpx to spc package did not return in back to back cycles
wire cpx_spc1_data_vld = `TOP_MEMORY.cpx_spc1_data_cx2[`CPX_WIDTH-1];
wire [`CPX_WIDTH-1:0] cpx_spc1_data_cx2 = `TOP_MEMORY.cpx_spc1_data_cx2[`CPX_WIDTH-1:0];
reg [`CPX_WIDTH-1:0] cpx_spc1_data_cx2_d1; // packet delayed by 1
reg [`CPX_WIDTH-1:0] cpx_spc1_data_cx2_d2; // packet delayed by 2
reg [127:0] spc1_pcx_type_str; // packet type in string format for debug.
reg [127:0] cpx_spc1_type_str; // in string format for debug
wire [3:0] cpx_spc1_type = cpx_spc1_data_vld ? cpx_spc1_data_cx2[`CPX_RQ_HI:`CPX_RQ_LO] :4'h0;
wire cpx_spc1_wyvld = cpx_spc1_data_cx2[`CPX_WYVLD] & cpx_spc1_data_vld;
wire cpx_spc1_st_ack = (cpx_spc1_type == `ST_ACK) | (cpx_spc1_type == `STRST_ACK);
wire cpx_spc1_evict = (cpx_spc1_type == `EVICT_REQ);
reg cpx_spc1_ifill_wyvld;
reg cpx_spc1_dfill_wyvld;
wire cpx_spc1_st_ack_dc_inval_1c_tmp = (cpx_spc1_data_cx2[122:121] == 2'b00) ? cpx_spc1_data_cx2[0] :
(cpx_spc1_data_cx2[122:121] == 2'b01) ? cpx_spc1_data_cx2[32] :
(cpx_spc1_data_cx2[122:121] == 2'b10) ? cpx_spc1_data_cx2[56] :
cpx_spc1_data_cx2[88];
wire [2:0] cpx_spc1_st_ack_dc_inval_1c = {2'b00, cpx_spc1_st_ack & cpx_spc1_st_ack_dc_inval_1c_tmp};
wire cpx_spc1_st_ack_ic_inval_1c_tmp = cpx_spc1_data_cx2[122] ? cpx_spc1_data_cx2[57] : cpx_spc1_data_cx2[1];
wire [2:0] cpx_spc1_st_ack_ic_inval_1c = {2'b00, (cpx_spc1_st_ack & cpx_spc1_st_ack_ic_inval_1c_tmp)};
wire [5:0] cpx_spc1_st_ack_icdc_inval_1c = {6{cpx_spc1_st_ack}} &
{cpx_spc1_st_ack_ic_inval_1c, cpx_spc1_st_ack_dc_inval_1c};
wire [2:0] cpx_spc1_evict_dc_inval_1c = cpx_spc1_data_cx2[0] + cpx_spc1_data_cx2[32] +
cpx_spc1_data_cx2[56] + cpx_spc1_data_cx2[88];
wire [1:0] cpx_spc1_evict_ic_inval_1c = cpx_spc1_data_cx2[1] + cpx_spc1_data_cx2[57];
reg cpx_spc1_evict_d1;
always @(posedge clk)
cpx_spc1_evict_d1 <= cpx_spc1_evict;
wire cpx_spc1_b2b_evict = cpx_spc1_evict_d1 & cpx_spc1_evict;
wire [5:0] cpx_spc1_evict_icdc_inval_1c;
assign cpx_spc1_evict_icdc_inval_1c[4:0]={5{cpx_spc1_evict}} &
{cpx_spc1_evict_ic_inval_1c,cpx_spc1_evict_dc_inval_1c};
assign cpx_spc1_evict_icdc_inval_1c[5] = cpx_spc1_b2b_evict;
wire [5:0] cpx_spc1_st_ack_dc_inval_8c_tmp = (cpx_spc1_data_cx2[122:121] == 2'b00) ? (
cpx_spc1_data_cx2[0] + cpx_spc1_data_cx2[4] +
cpx_spc1_data_cx2[8] + cpx_spc1_data_cx2[12] +
cpx_spc1_data_cx2[16] + cpx_spc1_data_cx2[20] +
cpx_spc1_data_cx2[24] + cpx_spc1_data_cx2[28]
) :
(cpx_spc1_data_cx2[122:121] == 2'b01) ? (
cpx_spc1_data_cx2[32] + cpx_spc1_data_cx2[35] +
cpx_spc1_data_cx2[38] + cpx_spc1_data_cx2[41] +
cpx_spc1_data_cx2[44] + cpx_spc1_data_cx2[47] +
cpx_spc1_data_cx2[50] + cpx_spc1_data_cx2[53]
) :
(cpx_spc1_data_cx2[122:121] == 2'b10) ? (
cpx_spc1_data_cx2[56] + cpx_spc1_data_cx2[60] +
cpx_spc1_data_cx2[64] + cpx_spc1_data_cx2[68] +
cpx_spc1_data_cx2[72] + cpx_spc1_data_cx2[76] +
cpx_spc1_data_cx2[80] + cpx_spc1_data_cx2[84]
) :
( cpx_spc1_data_cx2[88] + cpx_spc1_data_cx2[91] +
cpx_spc1_data_cx2[94] + cpx_spc1_data_cx2[97] +
cpx_spc1_data_cx2[100]+ cpx_spc1_data_cx2[103]+
cpx_spc1_data_cx2[106]+ cpx_spc1_data_cx2[109]
) ;
wire [5:0] cpx_spc1_st_ack_dc_inval_8c = {6{cpx_spc1_st_ack}} & cpx_spc1_st_ack_dc_inval_8c_tmp;
wire [5:0] cpx_spc1_st_ack_ic_inval_8c_tmp = ~cpx_spc1_data_cx2[122] ? (
cpx_spc1_data_cx2[1] + cpx_spc1_data_cx2[5] +
cpx_spc1_data_cx2[9] + cpx_spc1_data_cx2[13] +
cpx_spc1_data_cx2[17] + cpx_spc1_data_cx2[21] +
cpx_spc1_data_cx2[25] + cpx_spc1_data_cx2[29]
) :
( cpx_spc1_data_cx2[57] + cpx_spc1_data_cx2[61] +
cpx_spc1_data_cx2[65] + cpx_spc1_data_cx2[69] +
cpx_spc1_data_cx2[73] + cpx_spc1_data_cx2[77] +
cpx_spc1_data_cx2[81] + cpx_spc1_data_cx2[85]
) ;
wire [5:0] cpx_spc1_st_ack_ic_inval_8c = {4{cpx_spc1_st_ack}} & cpx_spc1_st_ack_ic_inval_8c_tmp;
wire [5:0] cpx_spc1_evict_dc_inval_8c_tmp =
cpx_spc1_data_cx2[0] + cpx_spc1_data_cx2[4] +
cpx_spc1_data_cx2[8] + cpx_spc1_data_cx2[12] +
cpx_spc1_data_cx2[16] + cpx_spc1_data_cx2[20] +
cpx_spc1_data_cx2[24] + cpx_spc1_data_cx2[28] +
cpx_spc1_data_cx2[32] + cpx_spc1_data_cx2[35] +
cpx_spc1_data_cx2[38] + cpx_spc1_data_cx2[41] +
cpx_spc1_data_cx2[44] + cpx_spc1_data_cx2[47] +
cpx_spc1_data_cx2[50] + cpx_spc1_data_cx2[53] +
cpx_spc1_data_cx2[56] + cpx_spc1_data_cx2[60] +
cpx_spc1_data_cx2[64] + cpx_spc1_data_cx2[68] +
cpx_spc1_data_cx2[72] + cpx_spc1_data_cx2[76] +
cpx_spc1_data_cx2[80] + cpx_spc1_data_cx2[84] +
cpx_spc1_data_cx2[88] + cpx_spc1_data_cx2[91] +
cpx_spc1_data_cx2[94] + cpx_spc1_data_cx2[97] +
cpx_spc1_data_cx2[100]+ cpx_spc1_data_cx2[103]+
cpx_spc1_data_cx2[106]+ cpx_spc1_data_cx2[109];
wire [5:0] cpx_spc1_evict_dc_inval_8c = {6{cpx_spc1_evict}} & cpx_spc1_evict_dc_inval_8c_tmp;
wire [5:0] cpx_spc1_evict_ic_inval_8c_tmp =
cpx_spc1_data_cx2[1] + cpx_spc1_data_cx2[5] +
cpx_spc1_data_cx2[9] + cpx_spc1_data_cx2[13] +
cpx_spc1_data_cx2[17] + cpx_spc1_data_cx2[21] +
cpx_spc1_data_cx2[25] + cpx_spc1_data_cx2[29] +
cpx_spc1_data_cx2[57] + cpx_spc1_data_cx2[61] +
cpx_spc1_data_cx2[65] + cpx_spc1_data_cx2[69] +
cpx_spc1_data_cx2[73] + cpx_spc1_data_cx2[77] +
cpx_spc1_data_cx2[81] + cpx_spc1_data_cx2[85];
wire [5:0] cpx_spc1_evict_ic_inval_8c = {6{cpx_spc1_evict}} & cpx_spc1_evict_ic_inval_8c_tmp;
reg [3:0] blk_st_cnt1; // counts the number of block stores without an acknowledge in between
reg [3:0] ini_st_cnt1; // counts the number of init stores without an acknowledge in between
reg st_blkst_mixture1; // a flag set upon detection of block store and normal store mixture.
reg st_inist_mixture1; // a flag set upon detection of init store and normal store mixture.
reg atomic_ret1; // atomic cpx to spc package
reg non_b2b_atomic_ret1; // atomic cpx to spc package did not return in back to back cycles
wire cpx_spc2_data_vld = `TOP_MEMORY.cpx_spc2_data_cx2[`CPX_WIDTH-1];
wire [`CPX_WIDTH-1:0] cpx_spc2_data_cx2 = `TOP_MEMORY.cpx_spc2_data_cx2[`CPX_WIDTH-1:0];
reg [`CPX_WIDTH-1:0] cpx_spc2_data_cx2_d1; // packet delayed by 1
reg [`CPX_WIDTH-1:0] cpx_spc2_data_cx2_d2; // packet delayed by 2
reg [127:0] spc2_pcx_type_str; // packet type in string format for debug.
reg [127:0] cpx_spc2_type_str; // in string format for debug
wire [3:0] cpx_spc2_type = cpx_spc2_data_vld ? cpx_spc2_data_cx2[`CPX_RQ_HI:`CPX_RQ_LO] :4'h0;
wire cpx_spc2_wyvld = cpx_spc2_data_cx2[`CPX_WYVLD] & cpx_spc2_data_vld;
wire cpx_spc2_st_ack = (cpx_spc2_type == `ST_ACK) | (cpx_spc2_type == `STRST_ACK);
wire cpx_spc2_evict = (cpx_spc2_type == `EVICT_REQ);
reg cpx_spc2_ifill_wyvld;
reg cpx_spc2_dfill_wyvld;
wire cpx_spc2_st_ack_dc_inval_1c_tmp = (cpx_spc2_data_cx2[122:121] == 2'b00) ? cpx_spc2_data_cx2[0] :
(cpx_spc2_data_cx2[122:121] == 2'b01) ? cpx_spc2_data_cx2[32] :
(cpx_spc2_data_cx2[122:121] == 2'b10) ? cpx_spc2_data_cx2[56] :
cpx_spc2_data_cx2[88];
wire [2:0] cpx_spc2_st_ack_dc_inval_1c = {2'b00, cpx_spc2_st_ack & cpx_spc2_st_ack_dc_inval_1c_tmp};
wire cpx_spc2_st_ack_ic_inval_1c_tmp = cpx_spc2_data_cx2[122] ? cpx_spc2_data_cx2[57] : cpx_spc2_data_cx2[1];
wire [2:0] cpx_spc2_st_ack_ic_inval_1c = {2'b00, (cpx_spc2_st_ack & cpx_spc2_st_ack_ic_inval_1c_tmp)};
wire [5:0] cpx_spc2_st_ack_icdc_inval_1c = {6{cpx_spc2_st_ack}} &
{cpx_spc2_st_ack_ic_inval_1c, cpx_spc2_st_ack_dc_inval_1c};
wire [2:0] cpx_spc2_evict_dc_inval_1c = cpx_spc2_data_cx2[0] + cpx_spc2_data_cx2[32] +
cpx_spc2_data_cx2[56] + cpx_spc2_data_cx2[88];
wire [1:0] cpx_spc2_evict_ic_inval_1c = cpx_spc2_data_cx2[1] + cpx_spc2_data_cx2[57];
reg cpx_spc2_evict_d1;
always @(posedge clk)
cpx_spc2_evict_d1 <= cpx_spc2_evict;
wire cpx_spc2_b2b_evict = cpx_spc2_evict_d1 & cpx_spc2_evict;
wire [5:0] cpx_spc2_evict_icdc_inval_1c;
assign cpx_spc2_evict_icdc_inval_1c[4:0]={5{cpx_spc2_evict}} &
{cpx_spc2_evict_ic_inval_1c,cpx_spc2_evict_dc_inval_1c};
assign cpx_spc2_evict_icdc_inval_1c[5] = cpx_spc2_b2b_evict;
wire [5:0] cpx_spc2_st_ack_dc_inval_8c_tmp = (cpx_spc2_data_cx2[122:121] == 2'b00) ? (
cpx_spc2_data_cx2[0] + cpx_spc2_data_cx2[4] +
cpx_spc2_data_cx2[8] + cpx_spc2_data_cx2[12] +
cpx_spc2_data_cx2[16] + cpx_spc2_data_cx2[20] +
cpx_spc2_data_cx2[24] + cpx_spc2_data_cx2[28]
) :
(cpx_spc2_data_cx2[122:121] == 2'b01) ? (
cpx_spc2_data_cx2[32] + cpx_spc2_data_cx2[35] +
cpx_spc2_data_cx2[38] + cpx_spc2_data_cx2[41] +
cpx_spc2_data_cx2[44] + cpx_spc2_data_cx2[47] +
cpx_spc2_data_cx2[50] + cpx_spc2_data_cx2[53]
) :
(cpx_spc2_data_cx2[122:121] == 2'b10) ? (
cpx_spc2_data_cx2[56] + cpx_spc2_data_cx2[60] +
cpx_spc2_data_cx2[64] + cpx_spc2_data_cx2[68] +
cpx_spc2_data_cx2[72] + cpx_spc2_data_cx2[76] +
cpx_spc2_data_cx2[80] + cpx_spc2_data_cx2[84]
) :
( cpx_spc2_data_cx2[88] + cpx_spc2_data_cx2[91] +
cpx_spc2_data_cx2[94] + cpx_spc2_data_cx2[97] +
cpx_spc2_data_cx2[100]+ cpx_spc2_data_cx2[103]+
cpx_spc2_data_cx2[106]+ cpx_spc2_data_cx2[109]
) ;
wire [5:0] cpx_spc2_st_ack_dc_inval_8c = {6{cpx_spc2_st_ack}} & cpx_spc2_st_ack_dc_inval_8c_tmp;
wire [5:0] cpx_spc2_st_ack_ic_inval_8c_tmp = ~cpx_spc2_data_cx2[122] ? (
cpx_spc2_data_cx2[1] + cpx_spc2_data_cx2[5] +
cpx_spc2_data_cx2[9] + cpx_spc2_data_cx2[13] +
cpx_spc2_data_cx2[17] + cpx_spc2_data_cx2[21] +
cpx_spc2_data_cx2[25] + cpx_spc2_data_cx2[29]
) :
( cpx_spc2_data_cx2[57] + cpx_spc2_data_cx2[61] +
cpx_spc2_data_cx2[65] + cpx_spc2_data_cx2[69] +
cpx_spc2_data_cx2[73] + cpx_spc2_data_cx2[77] +
cpx_spc2_data_cx2[81] + cpx_spc2_data_cx2[85]
) ;
wire [5:0] cpx_spc2_st_ack_ic_inval_8c = {4{cpx_spc2_st_ack}} & cpx_spc2_st_ack_ic_inval_8c_tmp;
wire [5:0] cpx_spc2_evict_dc_inval_8c_tmp =
cpx_spc2_data_cx2[0] + cpx_spc2_data_cx2[4] +
cpx_spc2_data_cx2[8] + cpx_spc2_data_cx2[12] +
cpx_spc2_data_cx2[16] + cpx_spc2_data_cx2[20] +
cpx_spc2_data_cx2[24] + cpx_spc2_data_cx2[28] +
cpx_spc2_data_cx2[32] + cpx_spc2_data_cx2[35] +
cpx_spc2_data_cx2[38] + cpx_spc2_data_cx2[41] +
cpx_spc2_data_cx2[44] + cpx_spc2_data_cx2[47] +
cpx_spc2_data_cx2[50] + cpx_spc2_data_cx2[53] +
cpx_spc2_data_cx2[56] + cpx_spc2_data_cx2[60] +
cpx_spc2_data_cx2[64] + cpx_spc2_data_cx2[68] +
cpx_spc2_data_cx2[72] + cpx_spc2_data_cx2[76] +
cpx_spc2_data_cx2[80] + cpx_spc2_data_cx2[84] +
cpx_spc2_data_cx2[88] + cpx_spc2_data_cx2[91] +
cpx_spc2_data_cx2[94] + cpx_spc2_data_cx2[97] +
cpx_spc2_data_cx2[100]+ cpx_spc2_data_cx2[103]+
cpx_spc2_data_cx2[106]+ cpx_spc2_data_cx2[109];
wire [5:0] cpx_spc2_evict_dc_inval_8c = {6{cpx_spc2_evict}} & cpx_spc2_evict_dc_inval_8c_tmp;
wire [5:0] cpx_spc2_evict_ic_inval_8c_tmp =
cpx_spc2_data_cx2[1] + cpx_spc2_data_cx2[5] +
cpx_spc2_data_cx2[9] + cpx_spc2_data_cx2[13] +
cpx_spc2_data_cx2[17] + cpx_spc2_data_cx2[21] +
cpx_spc2_data_cx2[25] + cpx_spc2_data_cx2[29] +
cpx_spc2_data_cx2[57] + cpx_spc2_data_cx2[61] +
cpx_spc2_data_cx2[65] + cpx_spc2_data_cx2[69] +
cpx_spc2_data_cx2[73] + cpx_spc2_data_cx2[77] +
cpx_spc2_data_cx2[81] + cpx_spc2_data_cx2[85];
wire [5:0] cpx_spc2_evict_ic_inval_8c = {6{cpx_spc2_evict}} & cpx_spc2_evict_ic_inval_8c_tmp;
reg [3:0] blk_st_cnt2; // counts the number of block stores without an acknowledge in between
reg [3:0] ini_st_cnt2; // counts the number of init stores without an acknowledge in between
reg st_blkst_mixture2; // a flag set upon detection of block store and normal store mixture.
reg st_inist_mixture2; // a flag set upon detection of init store and normal store mixture.
reg atomic_ret2; // atomic cpx to spc package
reg non_b2b_atomic_ret2; // atomic cpx to spc package did not return in back to back cycles
wire cpx_spc3_data_vld = `TOP_MEMORY.cpx_spc3_data_cx2[`CPX_WIDTH-1];
wire [`CPX_WIDTH-1:0] cpx_spc3_data_cx2 = `TOP_MEMORY.cpx_spc3_data_cx2[`CPX_WIDTH-1:0];
reg [`CPX_WIDTH-1:0] cpx_spc3_data_cx2_d1; // packet delayed by 1
reg [`CPX_WIDTH-1:0] cpx_spc3_data_cx2_d2; // packet delayed by 2
reg [127:0] spc3_pcx_type_str; // packet type in string format for debug.
reg [127:0] cpx_spc3_type_str; // in string format for debug
wire [3:0] cpx_spc3_type = cpx_spc3_data_vld ? cpx_spc3_data_cx2[`CPX_RQ_HI:`CPX_RQ_LO] :4'h0;
wire cpx_spc3_wyvld = cpx_spc3_data_cx2[`CPX_WYVLD] & cpx_spc3_data_vld;
wire cpx_spc3_st_ack = (cpx_spc3_type == `ST_ACK) | (cpx_spc3_type == `STRST_ACK);
wire cpx_spc3_evict = (cpx_spc3_type == `EVICT_REQ);
reg cpx_spc3_ifill_wyvld;
reg cpx_spc3_dfill_wyvld;
wire cpx_spc3_st_ack_dc_inval_1c_tmp = (cpx_spc3_data_cx2[122:121] == 2'b00) ? cpx_spc3_data_cx2[0] :
(cpx_spc3_data_cx2[122:121] == 2'b01) ? cpx_spc3_data_cx2[32] :
(cpx_spc3_data_cx2[122:121] == 2'b10) ? cpx_spc3_data_cx2[56] :
cpx_spc3_data_cx2[88];
wire [2:0] cpx_spc3_st_ack_dc_inval_1c = {2'b00, cpx_spc3_st_ack & cpx_spc3_st_ack_dc_inval_1c_tmp};
wire cpx_spc3_st_ack_ic_inval_1c_tmp = cpx_spc3_data_cx2[122] ? cpx_spc3_data_cx2[57] : cpx_spc3_data_cx2[1];
wire [2:0] cpx_spc3_st_ack_ic_inval_1c = {2'b00, (cpx_spc3_st_ack & cpx_spc3_st_ack_ic_inval_1c_tmp)};
wire [5:0] cpx_spc3_st_ack_icdc_inval_1c = {6{cpx_spc3_st_ack}} &
{cpx_spc3_st_ack_ic_inval_1c, cpx_spc3_st_ack_dc_inval_1c};
wire [2:0] cpx_spc3_evict_dc_inval_1c = cpx_spc3_data_cx2[0] + cpx_spc3_data_cx2[32] +
cpx_spc3_data_cx2[56] + cpx_spc3_data_cx2[88];
wire [1:0] cpx_spc3_evict_ic_inval_1c = cpx_spc3_data_cx2[1] + cpx_spc3_data_cx2[57];
reg cpx_spc3_evict_d1;
always @(posedge clk)
cpx_spc3_evict_d1 <= cpx_spc3_evict;
wire cpx_spc3_b2b_evict = cpx_spc3_evict_d1 & cpx_spc3_evict;
wire [5:0] cpx_spc3_evict_icdc_inval_1c;
assign cpx_spc3_evict_icdc_inval_1c[4:0]={5{cpx_spc3_evict}} &
{cpx_spc3_evict_ic_inval_1c,cpx_spc3_evict_dc_inval_1c};
assign cpx_spc3_evict_icdc_inval_1c[5] = cpx_spc3_b2b_evict;
wire [5:0] cpx_spc3_st_ack_dc_inval_8c_tmp = (cpx_spc3_data_cx2[122:121] == 2'b00) ? (
cpx_spc3_data_cx2[0] + cpx_spc3_data_cx2[4] +
cpx_spc3_data_cx2[8] + cpx_spc3_data_cx2[12] +
cpx_spc3_data_cx2[16] + cpx_spc3_data_cx2[20] +
cpx_spc3_data_cx2[24] + cpx_spc3_data_cx2[28]
) :
(cpx_spc3_data_cx2[122:121] == 2'b01) ? (
cpx_spc3_data_cx2[32] + cpx_spc3_data_cx2[35] +
cpx_spc3_data_cx2[38] + cpx_spc3_data_cx2[41] +
cpx_spc3_data_cx2[44] + cpx_spc3_data_cx2[47] +
cpx_spc3_data_cx2[50] + cpx_spc3_data_cx2[53]
) :
(cpx_spc3_data_cx2[122:121] == 2'b10) ? (
cpx_spc3_data_cx2[56] + cpx_spc3_data_cx2[60] +
cpx_spc3_data_cx2[64] + cpx_spc3_data_cx2[68] +
cpx_spc3_data_cx2[72] + cpx_spc3_data_cx2[76] +
cpx_spc3_data_cx2[80] + cpx_spc3_data_cx2[84]
) :
( cpx_spc3_data_cx2[88] + cpx_spc3_data_cx2[91] +
cpx_spc3_data_cx2[94] + cpx_spc3_data_cx2[97] +
cpx_spc3_data_cx2[100]+ cpx_spc3_data_cx2[103]+
cpx_spc3_data_cx2[106]+ cpx_spc3_data_cx2[109]
) ;
wire [5:0] cpx_spc3_st_ack_dc_inval_8c = {6{cpx_spc3_st_ack}} & cpx_spc3_st_ack_dc_inval_8c_tmp;
wire [5:0] cpx_spc3_st_ack_ic_inval_8c_tmp = ~cpx_spc3_data_cx2[122] ? (
cpx_spc3_data_cx2[1] + cpx_spc3_data_cx2[5] +
cpx_spc3_data_cx2[9] + cpx_spc3_data_cx2[13] +
cpx_spc3_data_cx2[17] + cpx_spc3_data_cx2[21] +
cpx_spc3_data_cx2[25] + cpx_spc3_data_cx2[29]
) :
( cpx_spc3_data_cx2[57] + cpx_spc3_data_cx2[61] +
cpx_spc3_data_cx2[65] + cpx_spc3_data_cx2[69] +
cpx_spc3_data_cx2[73] + cpx_spc3_data_cx2[77] +
cpx_spc3_data_cx2[81] + cpx_spc3_data_cx2[85]
) ;
wire [5:0] cpx_spc3_st_ack_ic_inval_8c = {4{cpx_spc3_st_ack}} & cpx_spc3_st_ack_ic_inval_8c_tmp;
wire [5:0] cpx_spc3_evict_dc_inval_8c_tmp =
cpx_spc3_data_cx2[0] + cpx_spc3_data_cx2[4] +
cpx_spc3_data_cx2[8] + cpx_spc3_data_cx2[12] +
cpx_spc3_data_cx2[16] + cpx_spc3_data_cx2[20] +
cpx_spc3_data_cx2[24] + cpx_spc3_data_cx2[28] +
cpx_spc3_data_cx2[32] + cpx_spc3_data_cx2[35] +
cpx_spc3_data_cx2[38] + cpx_spc3_data_cx2[41] +
cpx_spc3_data_cx2[44] + cpx_spc3_data_cx2[47] +
cpx_spc3_data_cx2[50] + cpx_spc3_data_cx2[53] +
cpx_spc3_data_cx2[56] + cpx_spc3_data_cx2[60] +
cpx_spc3_data_cx2[64] + cpx_spc3_data_cx2[68] +
cpx_spc3_data_cx2[72] + cpx_spc3_data_cx2[76] +
cpx_spc3_data_cx2[80] + cpx_spc3_data_cx2[84] +
cpx_spc3_data_cx2[88] + cpx_spc3_data_cx2[91] +
cpx_spc3_data_cx2[94] + cpx_spc3_data_cx2[97] +
cpx_spc3_data_cx2[100]+ cpx_spc3_data_cx2[103]+
cpx_spc3_data_cx2[106]+ cpx_spc3_data_cx2[109];
wire [5:0] cpx_spc3_evict_dc_inval_8c = {6{cpx_spc3_evict}} & cpx_spc3_evict_dc_inval_8c_tmp;
wire [5:0] cpx_spc3_evict_ic_inval_8c_tmp =
cpx_spc3_data_cx2[1] + cpx_spc3_data_cx2[5] +
cpx_spc3_data_cx2[9] + cpx_spc3_data_cx2[13] +
cpx_spc3_data_cx2[17] + cpx_spc3_data_cx2[21] +
cpx_spc3_data_cx2[25] + cpx_spc3_data_cx2[29] +
cpx_spc3_data_cx2[57] + cpx_spc3_data_cx2[61] +
cpx_spc3_data_cx2[65] + cpx_spc3_data_cx2[69] +
cpx_spc3_data_cx2[73] + cpx_spc3_data_cx2[77] +
cpx_spc3_data_cx2[81] + cpx_spc3_data_cx2[85];
wire [5:0] cpx_spc3_evict_ic_inval_8c = {6{cpx_spc3_evict}} & cpx_spc3_evict_ic_inval_8c_tmp;
reg [3:0] blk_st_cnt3; // counts the number of block stores without an acknowledge in between
reg [3:0] ini_st_cnt3; // counts the number of init stores without an acknowledge in between
reg st_blkst_mixture3; // a flag set upon detection of block store and normal store mixture.
reg st_inist_mixture3; // a flag set upon detection of init store and normal store mixture.
reg atomic_ret3; // atomic cpx to spc package
reg non_b2b_atomic_ret3; // atomic cpx to spc package did not return in back to back cycles
wire cpx_spc4_data_vld = `TOP_MEMORY.cpx_spc4_data_cx2[`CPX_WIDTH-1];
wire [`CPX_WIDTH-1:0] cpx_spc4_data_cx2 = `TOP_MEMORY.cpx_spc4_data_cx2[`CPX_WIDTH-1:0];
reg [`CPX_WIDTH-1:0] cpx_spc4_data_cx2_d1; // packet delayed by 1
reg [`CPX_WIDTH-1:0] cpx_spc4_data_cx2_d2; // packet delayed by 2
reg [127:0] spc4_pcx_type_str; // packet type in string format for debug.
reg [127:0] cpx_spc4_type_str; // in string format for debug
wire [3:0] cpx_spc4_type = cpx_spc4_data_vld ? cpx_spc4_data_cx2[`CPX_RQ_HI:`CPX_RQ_LO] :4'h0;
wire cpx_spc4_wyvld = cpx_spc4_data_cx2[`CPX_WYVLD] & cpx_spc4_data_vld;
wire cpx_spc4_st_ack = (cpx_spc4_type == `ST_ACK) | (cpx_spc4_type == `STRST_ACK);
wire cpx_spc4_evict = (cpx_spc4_type == `EVICT_REQ);
reg cpx_spc4_ifill_wyvld;
reg cpx_spc4_dfill_wyvld;
wire cpx_spc4_st_ack_dc_inval_1c_tmp = (cpx_spc4_data_cx2[122:121] == 2'b00) ? cpx_spc4_data_cx2[0] :
(cpx_spc4_data_cx2[122:121] == 2'b01) ? cpx_spc4_data_cx2[32] :
(cpx_spc4_data_cx2[122:121] == 2'b10) ? cpx_spc4_data_cx2[56] :
cpx_spc4_data_cx2[88];
wire [2:0] cpx_spc4_st_ack_dc_inval_1c = {2'b00, cpx_spc4_st_ack & cpx_spc4_st_ack_dc_inval_1c_tmp};
wire cpx_spc4_st_ack_ic_inval_1c_tmp = cpx_spc4_data_cx2[122] ? cpx_spc4_data_cx2[57] : cpx_spc4_data_cx2[1];
wire [2:0] cpx_spc4_st_ack_ic_inval_1c = {2'b00, (cpx_spc4_st_ack & cpx_spc4_st_ack_ic_inval_1c_tmp)};
wire [5:0] cpx_spc4_st_ack_icdc_inval_1c = {6{cpx_spc4_st_ack}} &
{cpx_spc4_st_ack_ic_inval_1c, cpx_spc4_st_ack_dc_inval_1c};
wire [2:0] cpx_spc4_evict_dc_inval_1c = cpx_spc4_data_cx2[0] + cpx_spc4_data_cx2[32] +
cpx_spc4_data_cx2[56] + cpx_spc4_data_cx2[88];
wire [1:0] cpx_spc4_evict_ic_inval_1c = cpx_spc4_data_cx2[1] + cpx_spc4_data_cx2[57];
reg cpx_spc4_evict_d1;
always @(posedge clk)
cpx_spc4_evict_d1 <= cpx_spc4_evict;
wire cpx_spc4_b2b_evict = cpx_spc4_evict_d1 & cpx_spc4_evict;
wire [5:0] cpx_spc4_evict_icdc_inval_1c;
assign cpx_spc4_evict_icdc_inval_1c[4:0]={5{cpx_spc4_evict}} &
{cpx_spc4_evict_ic_inval_1c,cpx_spc4_evict_dc_inval_1c};
assign cpx_spc4_evict_icdc_inval_1c[5] = cpx_spc4_b2b_evict;
wire [5:0] cpx_spc4_st_ack_dc_inval_8c_tmp = (cpx_spc4_data_cx2[122:121] == 2'b00) ? (
cpx_spc4_data_cx2[0] + cpx_spc4_data_cx2[4] +
cpx_spc4_data_cx2[8] + cpx_spc4_data_cx2[12] +
cpx_spc4_data_cx2[16] + cpx_spc4_data_cx2[20] +
cpx_spc4_data_cx2[24] + cpx_spc4_data_cx2[28]
) :
(cpx_spc4_data_cx2[122:121] == 2'b01) ? (
cpx_spc4_data_cx2[32] + cpx_spc4_data_cx2[35] +
cpx_spc4_data_cx2[38] + cpx_spc4_data_cx2[41] +
cpx_spc4_data_cx2[44] + cpx_spc4_data_cx2[47] +
cpx_spc4_data_cx2[50] + cpx_spc4_data_cx2[53]
) :
(cpx_spc4_data_cx2[122:121] == 2'b10) ? (
cpx_spc4_data_cx2[56] + cpx_spc4_data_cx2[60] +
cpx_spc4_data_cx2[64] + cpx_spc4_data_cx2[68] +
cpx_spc4_data_cx2[72] + cpx_spc4_data_cx2[76] +
cpx_spc4_data_cx2[80] + cpx_spc4_data_cx2[84]
) :
( cpx_spc4_data_cx2[88] + cpx_spc4_data_cx2[91] +
cpx_spc4_data_cx2[94] + cpx_spc4_data_cx2[97] +
cpx_spc4_data_cx2[100]+ cpx_spc4_data_cx2[103]+
cpx_spc4_data_cx2[106]+ cpx_spc4_data_cx2[109]
) ;
wire [5:0] cpx_spc4_st_ack_dc_inval_8c = {6{cpx_spc4_st_ack}} & cpx_spc4_st_ack_dc_inval_8c_tmp;
wire [5:0] cpx_spc4_st_ack_ic_inval_8c_tmp = ~cpx_spc4_data_cx2[122] ? (
cpx_spc4_data_cx2[1] + cpx_spc4_data_cx2[5] +
cpx_spc4_data_cx2[9] + cpx_spc4_data_cx2[13] +
cpx_spc4_data_cx2[17] + cpx_spc4_data_cx2[21] +
cpx_spc4_data_cx2[25] + cpx_spc4_data_cx2[29]
) :
( cpx_spc4_data_cx2[57] + cpx_spc4_data_cx2[61] +
cpx_spc4_data_cx2[65] + cpx_spc4_data_cx2[69] +
cpx_spc4_data_cx2[73] + cpx_spc4_data_cx2[77] +
cpx_spc4_data_cx2[81] + cpx_spc4_data_cx2[85]
) ;
wire [5:0] cpx_spc4_st_ack_ic_inval_8c = {4{cpx_spc4_st_ack}} & cpx_spc4_st_ack_ic_inval_8c_tmp;
wire [5:0] cpx_spc4_evict_dc_inval_8c_tmp =
cpx_spc4_data_cx2[0] + cpx_spc4_data_cx2[4] +
cpx_spc4_data_cx2[8] + cpx_spc4_data_cx2[12] +
cpx_spc4_data_cx2[16] + cpx_spc4_data_cx2[20] +
cpx_spc4_data_cx2[24] + cpx_spc4_data_cx2[28] +
cpx_spc4_data_cx2[32] + cpx_spc4_data_cx2[35] +
cpx_spc4_data_cx2[38] + cpx_spc4_data_cx2[41] +
cpx_spc4_data_cx2[44] + cpx_spc4_data_cx2[47] +
cpx_spc4_data_cx2[50] + cpx_spc4_data_cx2[53] +
cpx_spc4_data_cx2[56] + cpx_spc4_data_cx2[60] +
cpx_spc4_data_cx2[64] + cpx_spc4_data_cx2[68] +
cpx_spc4_data_cx2[72] + cpx_spc4_data_cx2[76] +
cpx_spc4_data_cx2[80] + cpx_spc4_data_cx2[84] +
cpx_spc4_data_cx2[88] + cpx_spc4_data_cx2[91] +
cpx_spc4_data_cx2[94] + cpx_spc4_data_cx2[97] +
cpx_spc4_data_cx2[100]+ cpx_spc4_data_cx2[103]+
cpx_spc4_data_cx2[106]+ cpx_spc4_data_cx2[109];
wire [5:0] cpx_spc4_evict_dc_inval_8c = {6{cpx_spc4_evict}} & cpx_spc4_evict_dc_inval_8c_tmp;
wire [5:0] cpx_spc4_evict_ic_inval_8c_tmp =
cpx_spc4_data_cx2[1] + cpx_spc4_data_cx2[5] +
cpx_spc4_data_cx2[9] + cpx_spc4_data_cx2[13] +
cpx_spc4_data_cx2[17] + cpx_spc4_data_cx2[21] +
cpx_spc4_data_cx2[25] + cpx_spc4_data_cx2[29] +
cpx_spc4_data_cx2[57] + cpx_spc4_data_cx2[61] +
cpx_spc4_data_cx2[65] + cpx_spc4_data_cx2[69] +
cpx_spc4_data_cx2[73] + cpx_spc4_data_cx2[77] +
cpx_spc4_data_cx2[81] + cpx_spc4_data_cx2[85];
wire [5:0] cpx_spc4_evict_ic_inval_8c = {6{cpx_spc4_evict}} & cpx_spc4_evict_ic_inval_8c_tmp;
reg [3:0] blk_st_cnt4; // counts the number of block stores without an acknowledge in between
reg [3:0] ini_st_cnt4; // counts the number of init stores without an acknowledge in between
reg st_blkst_mixture4; // a flag set upon detection of block store and normal store mixture.
reg st_inist_mixture4; // a flag set upon detection of init store and normal store mixture.
reg atomic_ret4; // atomic cpx to spc package
reg non_b2b_atomic_ret4; // atomic cpx to spc package did not return in back to back cycles
wire cpx_spc5_data_vld = `TOP_MEMORY.cpx_spc5_data_cx2[`CPX_WIDTH-1];
wire [`CPX_WIDTH-1:0] cpx_spc5_data_cx2 = `TOP_MEMORY.cpx_spc5_data_cx2[`CPX_WIDTH-1:0];
reg [`CPX_WIDTH-1:0] cpx_spc5_data_cx2_d1; // packet delayed by 1
reg [`CPX_WIDTH-1:0] cpx_spc5_data_cx2_d2; // packet delayed by 2
reg [127:0] spc5_pcx_type_str; // packet type in string format for debug.
reg [127:0] cpx_spc5_type_str; // in string format for debug
wire [3:0] cpx_spc5_type = cpx_spc5_data_vld ? cpx_spc5_data_cx2[`CPX_RQ_HI:`CPX_RQ_LO] :4'h0;
wire cpx_spc5_wyvld = cpx_spc5_data_cx2[`CPX_WYVLD] & cpx_spc5_data_vld;
wire cpx_spc5_st_ack = (cpx_spc5_type == `ST_ACK) | (cpx_spc5_type == `STRST_ACK);
wire cpx_spc5_evict = (cpx_spc5_type == `EVICT_REQ);
reg cpx_spc5_ifill_wyvld;
reg cpx_spc5_dfill_wyvld;
wire cpx_spc5_st_ack_dc_inval_1c_tmp = (cpx_spc5_data_cx2[122:121] == 2'b00) ? cpx_spc5_data_cx2[0] :
(cpx_spc5_data_cx2[122:121] == 2'b01) ? cpx_spc5_data_cx2[32] :
(cpx_spc5_data_cx2[122:121] == 2'b10) ? cpx_spc5_data_cx2[56] :
cpx_spc5_data_cx2[88];
wire [2:0] cpx_spc5_st_ack_dc_inval_1c = {2'b00, cpx_spc5_st_ack & cpx_spc5_st_ack_dc_inval_1c_tmp};
wire cpx_spc5_st_ack_ic_inval_1c_tmp = cpx_spc5_data_cx2[122] ? cpx_spc5_data_cx2[57] : cpx_spc5_data_cx2[1];
wire [2:0] cpx_spc5_st_ack_ic_inval_1c = {2'b00, (cpx_spc5_st_ack & cpx_spc5_st_ack_ic_inval_1c_tmp)};
wire [5:0] cpx_spc5_st_ack_icdc_inval_1c = {6{cpx_spc5_st_ack}} &
{cpx_spc5_st_ack_ic_inval_1c, cpx_spc5_st_ack_dc_inval_1c};
wire [2:0] cpx_spc5_evict_dc_inval_1c = cpx_spc5_data_cx2[0] + cpx_spc5_data_cx2[32] +
cpx_spc5_data_cx2[56] + cpx_spc5_data_cx2[88];
wire [1:0] cpx_spc5_evict_ic_inval_1c = cpx_spc5_data_cx2[1] + cpx_spc5_data_cx2[57];
reg cpx_spc5_evict_d1;
always @(posedge clk)
cpx_spc5_evict_d1 <= cpx_spc5_evict;
wire cpx_spc5_b2b_evict = cpx_spc5_evict_d1 & cpx_spc5_evict;
wire [5:0] cpx_spc5_evict_icdc_inval_1c;
assign cpx_spc5_evict_icdc_inval_1c[4:0]={5{cpx_spc5_evict}} &
{cpx_spc5_evict_ic_inval_1c,cpx_spc5_evict_dc_inval_1c};
assign cpx_spc5_evict_icdc_inval_1c[5] = cpx_spc5_b2b_evict;
wire [5:0] cpx_spc5_st_ack_dc_inval_8c_tmp = (cpx_spc5_data_cx2[122:121] == 2'b00) ? (
cpx_spc5_data_cx2[0] + cpx_spc5_data_cx2[4] +
cpx_spc5_data_cx2[8] + cpx_spc5_data_cx2[12] +
cpx_spc5_data_cx2[16] + cpx_spc5_data_cx2[20] +
cpx_spc5_data_cx2[24] + cpx_spc5_data_cx2[28]
) :
(cpx_spc5_data_cx2[122:121] == 2'b01) ? (
cpx_spc5_data_cx2[32] + cpx_spc5_data_cx2[35] +
cpx_spc5_data_cx2[38] + cpx_spc5_data_cx2[41] +
cpx_spc5_data_cx2[44] + cpx_spc5_data_cx2[47] +
cpx_spc5_data_cx2[50] + cpx_spc5_data_cx2[53]
) :
(cpx_spc5_data_cx2[122:121] == 2'b10) ? (
cpx_spc5_data_cx2[56] + cpx_spc5_data_cx2[60] +
cpx_spc5_data_cx2[64] + cpx_spc5_data_cx2[68] +
cpx_spc5_data_cx2[72] + cpx_spc5_data_cx2[76] +
cpx_spc5_data_cx2[80] + cpx_spc5_data_cx2[84]
) :
( cpx_spc5_data_cx2[88] + cpx_spc5_data_cx2[91] +
cpx_spc5_data_cx2[94] + cpx_spc5_data_cx2[97] +
cpx_spc5_data_cx2[100]+ cpx_spc5_data_cx2[103]+
cpx_spc5_data_cx2[106]+ cpx_spc5_data_cx2[109]
) ;
wire [5:0] cpx_spc5_st_ack_dc_inval_8c = {6{cpx_spc5_st_ack}} & cpx_spc5_st_ack_dc_inval_8c_tmp;
wire [5:0] cpx_spc5_st_ack_ic_inval_8c_tmp = ~cpx_spc5_data_cx2[122] ? (
cpx_spc5_data_cx2[1] + cpx_spc5_data_cx2[5] +
cpx_spc5_data_cx2[9] + cpx_spc5_data_cx2[13] +
cpx_spc5_data_cx2[17] + cpx_spc5_data_cx2[21] +
cpx_spc5_data_cx2[25] + cpx_spc5_data_cx2[29]
) :
( cpx_spc5_data_cx2[57] + cpx_spc5_data_cx2[61] +
cpx_spc5_data_cx2[65] + cpx_spc5_data_cx2[69] +
cpx_spc5_data_cx2[73] + cpx_spc5_data_cx2[77] +
cpx_spc5_data_cx2[81] + cpx_spc5_data_cx2[85]
) ;
wire [5:0] cpx_spc5_st_ack_ic_inval_8c = {4{cpx_spc5_st_ack}} & cpx_spc5_st_ack_ic_inval_8c_tmp;
wire [5:0] cpx_spc5_evict_dc_inval_8c_tmp =
cpx_spc5_data_cx2[0] + cpx_spc5_data_cx2[4] +
cpx_spc5_data_cx2[8] + cpx_spc5_data_cx2[12] +
cpx_spc5_data_cx2[16] + cpx_spc5_data_cx2[20] +
cpx_spc5_data_cx2[24] + cpx_spc5_data_cx2[28] +
cpx_spc5_data_cx2[32] + cpx_spc5_data_cx2[35] +
cpx_spc5_data_cx2[38] + cpx_spc5_data_cx2[41] +
cpx_spc5_data_cx2[44] + cpx_spc5_data_cx2[47] +
cpx_spc5_data_cx2[50] + cpx_spc5_data_cx2[53] +
cpx_spc5_data_cx2[56] + cpx_spc5_data_cx2[60] +
cpx_spc5_data_cx2[64] + cpx_spc5_data_cx2[68] +
cpx_spc5_data_cx2[72] + cpx_spc5_data_cx2[76] +
cpx_spc5_data_cx2[80] + cpx_spc5_data_cx2[84] +
cpx_spc5_data_cx2[88] + cpx_spc5_data_cx2[91] +
cpx_spc5_data_cx2[94] + cpx_spc5_data_cx2[97] +
cpx_spc5_data_cx2[100]+ cpx_spc5_data_cx2[103]+
cpx_spc5_data_cx2[106]+ cpx_spc5_data_cx2[109];
wire [5:0] cpx_spc5_evict_dc_inval_8c = {6{cpx_spc5_evict}} & cpx_spc5_evict_dc_inval_8c_tmp;
wire [5:0] cpx_spc5_evict_ic_inval_8c_tmp =
cpx_spc5_data_cx2[1] + cpx_spc5_data_cx2[5] +
cpx_spc5_data_cx2[9] + cpx_spc5_data_cx2[13] +
cpx_spc5_data_cx2[17] + cpx_spc5_data_cx2[21] +
cpx_spc5_data_cx2[25] + cpx_spc5_data_cx2[29] +
cpx_spc5_data_cx2[57] + cpx_spc5_data_cx2[61] +
cpx_spc5_data_cx2[65] + cpx_spc5_data_cx2[69] +
cpx_spc5_data_cx2[73] + cpx_spc5_data_cx2[77] +
cpx_spc5_data_cx2[81] + cpx_spc5_data_cx2[85];
wire [5:0] cpx_spc5_evict_ic_inval_8c = {6{cpx_spc5_evict}} & cpx_spc5_evict_ic_inval_8c_tmp;
reg [3:0] blk_st_cnt5; // counts the number of block stores without an acknowledge in between
reg [3:0] ini_st_cnt5; // counts the number of init stores without an acknowledge in between
reg st_blkst_mixture5; // a flag set upon detection of block store and normal store mixture.
reg st_inist_mixture5; // a flag set upon detection of init store and normal store mixture.
reg atomic_ret5; // atomic cpx to spc package
reg non_b2b_atomic_ret5; // atomic cpx to spc package did not return in back to back cycles
wire cpx_spc6_data_vld = `TOP_MEMORY.cpx_spc6_data_cx2[`CPX_WIDTH-1];
wire [`CPX_WIDTH-1:0] cpx_spc6_data_cx2 = `TOP_MEMORY.cpx_spc6_data_cx2[`CPX_WIDTH-1:0];
reg [`CPX_WIDTH-1:0] cpx_spc6_data_cx2_d1; // packet delayed by 1
reg [`CPX_WIDTH-1:0] cpx_spc6_data_cx2_d2; // packet delayed by 2
reg [127:0] spc6_pcx_type_str; // packet type in string format for debug.
reg [127:0] cpx_spc6_type_str; // in string format for debug
wire [3:0] cpx_spc6_type = cpx_spc6_data_vld ? cpx_spc6_data_cx2[`CPX_RQ_HI:`CPX_RQ_LO] :4'h0;
wire cpx_spc6_wyvld = cpx_spc6_data_cx2[`CPX_WYVLD] & cpx_spc6_data_vld;
wire cpx_spc6_st_ack = (cpx_spc6_type == `ST_ACK) | (cpx_spc6_type == `STRST_ACK);
wire cpx_spc6_evict = (cpx_spc6_type == `EVICT_REQ);
reg cpx_spc6_ifill_wyvld;
reg cpx_spc6_dfill_wyvld;
wire cpx_spc6_st_ack_dc_inval_1c_tmp = (cpx_spc6_data_cx2[122:121] == 2'b00) ? cpx_spc6_data_cx2[0] :
(cpx_spc6_data_cx2[122:121] == 2'b01) ? cpx_spc6_data_cx2[32] :
(cpx_spc6_data_cx2[122:121] == 2'b10) ? cpx_spc6_data_cx2[56] :
cpx_spc6_data_cx2[88];
wire [2:0] cpx_spc6_st_ack_dc_inval_1c = {2'b00, cpx_spc6_st_ack & cpx_spc6_st_ack_dc_inval_1c_tmp};
wire cpx_spc6_st_ack_ic_inval_1c_tmp = cpx_spc6_data_cx2[122] ? cpx_spc6_data_cx2[57] : cpx_spc6_data_cx2[1];
wire [2:0] cpx_spc6_st_ack_ic_inval_1c = {2'b00, (cpx_spc6_st_ack & cpx_spc6_st_ack_ic_inval_1c_tmp)};
wire [5:0] cpx_spc6_st_ack_icdc_inval_1c = {6{cpx_spc6_st_ack}} &
{cpx_spc6_st_ack_ic_inval_1c, cpx_spc6_st_ack_dc_inval_1c};
wire [2:0] cpx_spc6_evict_dc_inval_1c = cpx_spc6_data_cx2[0] + cpx_spc6_data_cx2[32] +
cpx_spc6_data_cx2[56] + cpx_spc6_data_cx2[88];
wire [1:0] cpx_spc6_evict_ic_inval_1c = cpx_spc6_data_cx2[1] + cpx_spc6_data_cx2[57];
reg cpx_spc6_evict_d1;
always @(posedge clk)
cpx_spc6_evict_d1 <= cpx_spc6_evict;
wire cpx_spc6_b2b_evict = cpx_spc6_evict_d1 & cpx_spc6_evict;
wire [5:0] cpx_spc6_evict_icdc_inval_1c;
assign cpx_spc6_evict_icdc_inval_1c[4:0]={5{cpx_spc6_evict}} &
{cpx_spc6_evict_ic_inval_1c,cpx_spc6_evict_dc_inval_1c};
assign cpx_spc6_evict_icdc_inval_1c[5] = cpx_spc6_b2b_evict;
wire [5:0] cpx_spc6_st_ack_dc_inval_8c_tmp = (cpx_spc6_data_cx2[122:121] == 2'b00) ? (
cpx_spc6_data_cx2[0] + cpx_spc6_data_cx2[4] +
cpx_spc6_data_cx2[8] + cpx_spc6_data_cx2[12] +
cpx_spc6_data_cx2[16] + cpx_spc6_data_cx2[20] +
cpx_spc6_data_cx2[24] + cpx_spc6_data_cx2[28]
) :
(cpx_spc6_data_cx2[122:121] == 2'b01) ? (
cpx_spc6_data_cx2[32] + cpx_spc6_data_cx2[35] +
cpx_spc6_data_cx2[38] + cpx_spc6_data_cx2[41] +
cpx_spc6_data_cx2[44] + cpx_spc6_data_cx2[47] +
cpx_spc6_data_cx2[50] + cpx_spc6_data_cx2[53]
) :
(cpx_spc6_data_cx2[122:121] == 2'b10) ? (
cpx_spc6_data_cx2[56] + cpx_spc6_data_cx2[60] +
cpx_spc6_data_cx2[64] + cpx_spc6_data_cx2[68] +
cpx_spc6_data_cx2[72] + cpx_spc6_data_cx2[76] +
cpx_spc6_data_cx2[80] + cpx_spc6_data_cx2[84]
) :
( cpx_spc6_data_cx2[88] + cpx_spc6_data_cx2[91] +
cpx_spc6_data_cx2[94] + cpx_spc6_data_cx2[97] +
cpx_spc6_data_cx2[100]+ cpx_spc6_data_cx2[103]+
cpx_spc6_data_cx2[106]+ cpx_spc6_data_cx2[109]
) ;
wire [5:0] cpx_spc6_st_ack_dc_inval_8c = {6{cpx_spc6_st_ack}} & cpx_spc6_st_ack_dc_inval_8c_tmp;
wire [5:0] cpx_spc6_st_ack_ic_inval_8c_tmp = ~cpx_spc6_data_cx2[122] ? (
cpx_spc6_data_cx2[1] + cpx_spc6_data_cx2[5] +
cpx_spc6_data_cx2[9] + cpx_spc6_data_cx2[13] +
cpx_spc6_data_cx2[17] + cpx_spc6_data_cx2[21] +
cpx_spc6_data_cx2[25] + cpx_spc6_data_cx2[29]
) :
( cpx_spc6_data_cx2[57] + cpx_spc6_data_cx2[61] +
cpx_spc6_data_cx2[65] + cpx_spc6_data_cx2[69] +
cpx_spc6_data_cx2[73] + cpx_spc6_data_cx2[77] +
cpx_spc6_data_cx2[81] + cpx_spc6_data_cx2[85]
) ;
wire [5:0] cpx_spc6_st_ack_ic_inval_8c = {4{cpx_spc6_st_ack}} & cpx_spc6_st_ack_ic_inval_8c_tmp;
wire [5:0] cpx_spc6_evict_dc_inval_8c_tmp =
cpx_spc6_data_cx2[0] + cpx_spc6_data_cx2[4] +
cpx_spc6_data_cx2[8] + cpx_spc6_data_cx2[12] +
cpx_spc6_data_cx2[16] + cpx_spc6_data_cx2[20] +
cpx_spc6_data_cx2[24] + cpx_spc6_data_cx2[28] +
cpx_spc6_data_cx2[32] + cpx_spc6_data_cx2[35] +
cpx_spc6_data_cx2[38] + cpx_spc6_data_cx2[41] +
cpx_spc6_data_cx2[44] + cpx_spc6_data_cx2[47] +
cpx_spc6_data_cx2[50] + cpx_spc6_data_cx2[53] +
cpx_spc6_data_cx2[56] + cpx_spc6_data_cx2[60] +
cpx_spc6_data_cx2[64] + cpx_spc6_data_cx2[68] +
cpx_spc6_data_cx2[72] + cpx_spc6_data_cx2[76] +
cpx_spc6_data_cx2[80] + cpx_spc6_data_cx2[84] +
cpx_spc6_data_cx2[88] + cpx_spc6_data_cx2[91] +
cpx_spc6_data_cx2[94] + cpx_spc6_data_cx2[97] +
cpx_spc6_data_cx2[100]+ cpx_spc6_data_cx2[103]+
cpx_spc6_data_cx2[106]+ cpx_spc6_data_cx2[109];
wire [5:0] cpx_spc6_evict_dc_inval_8c = {6{cpx_spc6_evict}} & cpx_spc6_evict_dc_inval_8c_tmp;
wire [5:0] cpx_spc6_evict_ic_inval_8c_tmp =
cpx_spc6_data_cx2[1] + cpx_spc6_data_cx2[5] +
cpx_spc6_data_cx2[9] + cpx_spc6_data_cx2[13] +
cpx_spc6_data_cx2[17] + cpx_spc6_data_cx2[21] +
cpx_spc6_data_cx2[25] + cpx_spc6_data_cx2[29] +
cpx_spc6_data_cx2[57] + cpx_spc6_data_cx2[61] +
cpx_spc6_data_cx2[65] + cpx_spc6_data_cx2[69] +
cpx_spc6_data_cx2[73] + cpx_spc6_data_cx2[77] +
cpx_spc6_data_cx2[81] + cpx_spc6_data_cx2[85];
wire [5:0] cpx_spc6_evict_ic_inval_8c = {6{cpx_spc6_evict}} & cpx_spc6_evict_ic_inval_8c_tmp;
reg [3:0] blk_st_cnt6; // counts the number of block stores without an acknowledge in between
reg [3:0] ini_st_cnt6; // counts the number of init stores without an acknowledge in between
reg st_blkst_mixture6; // a flag set upon detection of block store and normal store mixture.
reg st_inist_mixture6; // a flag set upon detection of init store and normal store mixture.
reg atomic_ret6; // atomic cpx to spc package
reg non_b2b_atomic_ret6; // atomic cpx to spc package did not return in back to back cycles
wire cpx_spc7_data_vld = `TOP_MEMORY.cpx_spc7_data_cx2[`CPX_WIDTH-1];
wire [`CPX_WIDTH-1:0] cpx_spc7_data_cx2 = `TOP_MEMORY.cpx_spc7_data_cx2[`CPX_WIDTH-1:0];
reg [`CPX_WIDTH-1:0] cpx_spc7_data_cx2_d1; // packet delayed by 1
reg [`CPX_WIDTH-1:0] cpx_spc7_data_cx2_d2; // packet delayed by 2
reg [127:0] spc7_pcx_type_str; // packet type in string format for debug.
reg [127:0] cpx_spc7_type_str; // in string format for debug
wire [3:0] cpx_spc7_type = cpx_spc7_data_vld ? cpx_spc7_data_cx2[`CPX_RQ_HI:`CPX_RQ_LO] :4'h0;
wire cpx_spc7_wyvld = cpx_spc7_data_cx2[`CPX_WYVLD] & cpx_spc7_data_vld;
wire cpx_spc7_st_ack = (cpx_spc7_type == `ST_ACK) | (cpx_spc7_type == `STRST_ACK);
wire cpx_spc7_evict = (cpx_spc7_type == `EVICT_REQ);
reg cpx_spc7_ifill_wyvld;
reg cpx_spc7_dfill_wyvld;
wire cpx_spc7_st_ack_dc_inval_1c_tmp = (cpx_spc7_data_cx2[122:121] == 2'b00) ? cpx_spc7_data_cx2[0] :
(cpx_spc7_data_cx2[122:121] == 2'b01) ? cpx_spc7_data_cx2[32] :
(cpx_spc7_data_cx2[122:121] == 2'b10) ? cpx_spc7_data_cx2[56] :
cpx_spc7_data_cx2[88];
wire [2:0] cpx_spc7_st_ack_dc_inval_1c = {2'b00, cpx_spc7_st_ack & cpx_spc7_st_ack_dc_inval_1c_tmp};
wire cpx_spc7_st_ack_ic_inval_1c_tmp = cpx_spc7_data_cx2[122] ? cpx_spc7_data_cx2[57] : cpx_spc7_data_cx2[1];
wire [2:0] cpx_spc7_st_ack_ic_inval_1c = {2'b00, (cpx_spc7_st_ack & cpx_spc7_st_ack_ic_inval_1c_tmp)};
wire [5:0] cpx_spc7_st_ack_icdc_inval_1c = {6{cpx_spc7_st_ack}} &
{cpx_spc7_st_ack_ic_inval_1c, cpx_spc7_st_ack_dc_inval_1c};
wire [2:0] cpx_spc7_evict_dc_inval_1c = cpx_spc7_data_cx2[0] + cpx_spc7_data_cx2[32] +
cpx_spc7_data_cx2[56] + cpx_spc7_data_cx2[88];
wire [1:0] cpx_spc7_evict_ic_inval_1c = cpx_spc7_data_cx2[1] + cpx_spc7_data_cx2[57];
reg cpx_spc7_evict_d1;
always @(posedge clk)
cpx_spc7_evict_d1 <= cpx_spc7_evict;
wire cpx_spc7_b2b_evict = cpx_spc7_evict_d1 & cpx_spc7_evict;
wire [5:0] cpx_spc7_evict_icdc_inval_1c;
assign cpx_spc7_evict_icdc_inval_1c[4:0]={5{cpx_spc7_evict}} &
{cpx_spc7_evict_ic_inval_1c,cpx_spc7_evict_dc_inval_1c};
assign cpx_spc7_evict_icdc_inval_1c[5] = cpx_spc7_b2b_evict;
wire [5:0] cpx_spc7_st_ack_dc_inval_8c_tmp = (cpx_spc7_data_cx2[122:121] == 2'b00) ? (
cpx_spc7_data_cx2[0] + cpx_spc7_data_cx2[4] +
cpx_spc7_data_cx2[8] + cpx_spc7_data_cx2[12] +
cpx_spc7_data_cx2[16] + cpx_spc7_data_cx2[20] +
cpx_spc7_data_cx2[24] + cpx_spc7_data_cx2[28]
) :
(cpx_spc7_data_cx2[122:121] == 2'b01) ? (
cpx_spc7_data_cx2[32] + cpx_spc7_data_cx2[35] +
cpx_spc7_data_cx2[38] + cpx_spc7_data_cx2[41] +
cpx_spc7_data_cx2[44] + cpx_spc7_data_cx2[47] +
cpx_spc7_data_cx2[50] + cpx_spc7_data_cx2[53]
) :
(cpx_spc7_data_cx2[122:121] == 2'b10) ? (
cpx_spc7_data_cx2[56] + cpx_spc7_data_cx2[60] +
cpx_spc7_data_cx2[64] + cpx_spc7_data_cx2[68] +
cpx_spc7_data_cx2[72] + cpx_spc7_data_cx2[76] +
cpx_spc7_data_cx2[80] + cpx_spc7_data_cx2[84]
) :
( cpx_spc7_data_cx2[88] + cpx_spc7_data_cx2[91] +
cpx_spc7_data_cx2[94] + cpx_spc7_data_cx2[97] +
cpx_spc7_data_cx2[100]+ cpx_spc7_data_cx2[103]+
cpx_spc7_data_cx2[106]+ cpx_spc7_data_cx2[109]
) ;
wire [5:0] cpx_spc7_st_ack_dc_inval_8c = {6{cpx_spc7_st_ack}} & cpx_spc7_st_ack_dc_inval_8c_tmp;
wire [5:0] cpx_spc7_st_ack_ic_inval_8c_tmp = ~cpx_spc7_data_cx2[122] ? (
cpx_spc7_data_cx2[1] + cpx_spc7_data_cx2[5] +
cpx_spc7_data_cx2[9] + cpx_spc7_data_cx2[13] +
cpx_spc7_data_cx2[17] + cpx_spc7_data_cx2[21] +
cpx_spc7_data_cx2[25] + cpx_spc7_data_cx2[29]
) :
( cpx_spc7_data_cx2[57] + cpx_spc7_data_cx2[61] +
cpx_spc7_data_cx2[65] + cpx_spc7_data_cx2[69] +
cpx_spc7_data_cx2[73] + cpx_spc7_data_cx2[77] +
cpx_spc7_data_cx2[81] + cpx_spc7_data_cx2[85]
) ;
wire [5:0] cpx_spc7_st_ack_ic_inval_8c = {4{cpx_spc7_st_ack}} & cpx_spc7_st_ack_ic_inval_8c_tmp;
wire [5:0] cpx_spc7_evict_dc_inval_8c_tmp =
cpx_spc7_data_cx2[0] + cpx_spc7_data_cx2[4] +
cpx_spc7_data_cx2[8] + cpx_spc7_data_cx2[12] +
cpx_spc7_data_cx2[16] + cpx_spc7_data_cx2[20] +
cpx_spc7_data_cx2[24] + cpx_spc7_data_cx2[28] +
cpx_spc7_data_cx2[32] + cpx_spc7_data_cx2[35] +
cpx_spc7_data_cx2[38] + cpx_spc7_data_cx2[41] +
cpx_spc7_data_cx2[44] + cpx_spc7_data_cx2[47] +
cpx_spc7_data_cx2[50] + cpx_spc7_data_cx2[53] +
cpx_spc7_data_cx2[56] + cpx_spc7_data_cx2[60] +
cpx_spc7_data_cx2[64] + cpx_spc7_data_cx2[68] +
cpx_spc7_data_cx2[72] + cpx_spc7_data_cx2[76] +
cpx_spc7_data_cx2[80] + cpx_spc7_data_cx2[84] +
cpx_spc7_data_cx2[88] + cpx_spc7_data_cx2[91] +
cpx_spc7_data_cx2[94] + cpx_spc7_data_cx2[97] +
cpx_spc7_data_cx2[100]+ cpx_spc7_data_cx2[103]+
cpx_spc7_data_cx2[106]+ cpx_spc7_data_cx2[109];
wire [5:0] cpx_spc7_evict_dc_inval_8c = {6{cpx_spc7_evict}} & cpx_spc7_evict_dc_inval_8c_tmp;
wire [5:0] cpx_spc7_evict_ic_inval_8c_tmp =
cpx_spc7_data_cx2[1] + cpx_spc7_data_cx2[5] +
cpx_spc7_data_cx2[9] + cpx_spc7_data_cx2[13] +
cpx_spc7_data_cx2[17] + cpx_spc7_data_cx2[21] +
cpx_spc7_data_cx2[25] + cpx_spc7_data_cx2[29] +
cpx_spc7_data_cx2[57] + cpx_spc7_data_cx2[61] +
cpx_spc7_data_cx2[65] + cpx_spc7_data_cx2[69] +
cpx_spc7_data_cx2[73] + cpx_spc7_data_cx2[77] +
cpx_spc7_data_cx2[81] + cpx_spc7_data_cx2[85];
wire [5:0] cpx_spc7_evict_ic_inval_8c = {6{cpx_spc7_evict}} & cpx_spc7_evict_ic_inval_8c_tmp;
reg [3:0] blk_st_cnt7; // counts the number of block stores without an acknowledge in between
reg [3:0] ini_st_cnt7; // counts the number of init stores without an acknowledge in between
reg st_blkst_mixture7; // a flag set upon detection of block store and normal store mixture.
reg st_inist_mixture7; // a flag set upon detection of init store and normal store mixture.
reg atomic_ret7; // atomic cpx to spc package
reg non_b2b_atomic_ret7; // atomic cpx to spc package did not return in back to back cycles
//----------------------------------------------------------------------------------------
// The real thing starts somewhere here
//----------------------------------------------------------------------------------------
// This check belongs to another monitor (PLL) but since the PLL monitor does not
// exist and I do want this chip to work I put it here.
//--------------------------------------------------------------------------------
always @(posedge clk)
begin
if(rst_l & ~pll_lock & ~disable_lock_check)
finish_test("tso_mon", "PLL is not locked", 0);
end
always @(posedge clk)
begin
pcx0_vld_d1 <= spc0_pcx_data_pa[123];
pcx0_type_d1 <= spc0_pcx_data_pa[122:118];
pcx0_req_pq_d1 <= |spc0_pcx_req_pq;
pcx0_atom_pq_d1 <= spc0_pcx_atom_pq;
pcx0_atom_pq_d2 <= pcx0_atom_pq_d1;
// Multiple block stores without an ACK in between
//---------------------------------------------------
if((cpx_spc0_type == `ST_ACK) | ~rst_l)
blk_st_cnt0 <= 4'h0;
else if(pcx0_req_pq_d1 & (spc0_pcx_data_pa[122:118] == `STORE_RQ) & spc0_pcx_data_pa[109] & spc0_pcx_data_pa[110])
blk_st_cnt0 <= blk_st_cnt0 + 1'b1;
// detect if a normal store came while this counter is not zero.
//--------------------------------------------------------------
if(blk_st_cnt0 & (spc0_pcx_data_pa[122:118] == `STORE_RQ) & ~spc0_pcx_data_pa[109])
st_blkst_mixture0 <= 1'b1;
else if(blk_st_cnt0 == 4'h0)
st_blkst_mixture0 <= 1'b0;
// Multiple init stores without an ACK in between
//---------------------------------------------------
if((cpx_spc0_type == `ST_ACK) | ~rst_l)
ini_st_cnt0 <= 4'h0;
else if(pcx0_req_pq_d1 & (spc0_pcx_data_pa[122:118] == `STORE_RQ) & spc0_pcx_data_pa[109] & ~spc0_pcx_data_pa[110])
ini_st_cnt0 <= ini_st_cnt0 + 1'b1;
// detect if a normal store came while this counter is not zero.
//--------------------------------------------------------------
if(ini_st_cnt0 && (spc0_pcx_data_pa[122:118] == `STORE_RQ) & ~spc0_pcx_data_pa[109])
st_inist_mixture0 <= 1'b1;
else if(ini_st_cnt0 == 4'h0)
st_inist_mixture0 <= 1'b0;
if(~rst_l)
cpx_spc0_ifill_wyvld <= 1'b0;
else
cpx_spc0_ifill_wyvld <= ((cpx_spc0_type == `IFILL_RET) & cpx_spc0_wyvld);
if(~rst_l)
cpx_spc0_dfill_wyvld <= 1'b0;
else
cpx_spc0_dfill_wyvld <= ((cpx_spc0_type == `LOAD_RET) & cpx_spc0_wyvld);
pcx1_vld_d1 <= spc1_pcx_data_pa[123];
pcx1_type_d1 <= spc1_pcx_data_pa[122:118];
pcx1_req_pq_d1 <= |spc1_pcx_req_pq;
pcx1_atom_pq_d1 <= spc1_pcx_atom_pq;
pcx1_atom_pq_d2 <= pcx1_atom_pq_d1;
// Multiple block stores without an ACK in between
//---------------------------------------------------
if((cpx_spc1_type == `ST_ACK) | ~rst_l)
blk_st_cnt1 <= 4'h0;
else if(pcx1_req_pq_d1 & (spc1_pcx_data_pa[122:118] == `STORE_RQ) & spc1_pcx_data_pa[109] & spc1_pcx_data_pa[110])
blk_st_cnt1 <= blk_st_cnt1 + 1'b1;
// detect if a normal store came while this counter is not zero.
//--------------------------------------------------------------
if(blk_st_cnt1 & (spc1_pcx_data_pa[122:118] == `STORE_RQ) & ~spc1_pcx_data_pa[109])
st_blkst_mixture1 <= 1'b1;
else if(blk_st_cnt1 == 4'h0)
st_blkst_mixture1 <= 1'b0;
// Multiple init stores without an ACK in between
//---------------------------------------------------
if((cpx_spc1_type == `ST_ACK) | ~rst_l)
ini_st_cnt1 <= 4'h0;
else if(pcx1_req_pq_d1 & (spc1_pcx_data_pa[122:118] == `STORE_RQ) & spc1_pcx_data_pa[109] & ~spc1_pcx_data_pa[110])
ini_st_cnt1 <= ini_st_cnt1 + 1'b1;
// detect if a normal store came while this counter is not zero.
//--------------------------------------------------------------
if(ini_st_cnt1 && (spc1_pcx_data_pa[122:118] == `STORE_RQ) & ~spc1_pcx_data_pa[109])
st_inist_mixture1 <= 1'b1;
else if(ini_st_cnt1 == 4'h0)
st_inist_mixture1 <= 1'b0;
if(~rst_l)
cpx_spc1_ifill_wyvld <= 1'b0;
else
cpx_spc1_ifill_wyvld <= ((cpx_spc1_type == `IFILL_RET) & cpx_spc1_wyvld);
if(~rst_l)
cpx_spc1_dfill_wyvld <= 1'b0;
else
cpx_spc1_dfill_wyvld <= ((cpx_spc1_type == `LOAD_RET) & cpx_spc1_wyvld);
pcx2_vld_d1 <= spc2_pcx_data_pa[123];
pcx2_type_d1 <= spc2_pcx_data_pa[122:118];
pcx2_req_pq_d1 <= |spc2_pcx_req_pq;
pcx2_atom_pq_d1 <= spc2_pcx_atom_pq;
pcx2_atom_pq_d2 <= pcx2_atom_pq_d1;
// Multiple block stores without an ACK in between
//---------------------------------------------------
if((cpx_spc2_type == `ST_ACK) | ~rst_l)
blk_st_cnt2 <= 4'h0;
else if(pcx2_req_pq_d1 & (spc2_pcx_data_pa[122:118] == `STORE_RQ) & spc2_pcx_data_pa[109] & spc2_pcx_data_pa[110])
blk_st_cnt2 <= blk_st_cnt2 + 1'b1;
// detect if a normal store came while this counter is not zero.
//--------------------------------------------------------------
if(blk_st_cnt2 & (spc2_pcx_data_pa[122:118] == `STORE_RQ) & ~spc2_pcx_data_pa[109])
st_blkst_mixture2 <= 1'b1;
else if(blk_st_cnt2 == 4'h0)
st_blkst_mixture2 <= 1'b0;
// Multiple init stores without an ACK in between
//---------------------------------------------------
if((cpx_spc2_type == `ST_ACK) | ~rst_l)
ini_st_cnt2 <= 4'h0;
else if(pcx2_req_pq_d1 & (spc2_pcx_data_pa[122:118] == `STORE_RQ) & spc2_pcx_data_pa[109] & ~spc2_pcx_data_pa[110])
ini_st_cnt2 <= ini_st_cnt2 + 1'b1;
// detect if a normal store came while this counter is not zero.
//--------------------------------------------------------------
if(ini_st_cnt2 && (spc2_pcx_data_pa[122:118] == `STORE_RQ) & ~spc2_pcx_data_pa[109])
st_inist_mixture2 <= 1'b1;
else if(ini_st_cnt2 == 4'h0)
st_inist_mixture2 <= 1'b0;
if(~rst_l)
cpx_spc2_ifill_wyvld <= 1'b0;
else
cpx_spc2_ifill_wyvld <= ((cpx_spc2_type == `IFILL_RET) & cpx_spc2_wyvld);
if(~rst_l)
cpx_spc2_dfill_wyvld <= 1'b0;
else
cpx_spc2_dfill_wyvld <= ((cpx_spc2_type == `LOAD_RET) & cpx_spc2_wyvld);
pcx3_vld_d1 <= spc3_pcx_data_pa[123];
pcx3_type_d1 <= spc3_pcx_data_pa[122:118];
pcx3_req_pq_d1 <= |spc3_pcx_req_pq;
pcx3_atom_pq_d1 <= spc3_pcx_atom_pq;
pcx3_atom_pq_d2 <= pcx3_atom_pq_d1;
// Multiple block stores without an ACK in between
//---------------------------------------------------
if((cpx_spc3_type == `ST_ACK) | ~rst_l)
blk_st_cnt3 <= 4'h0;
else if(pcx3_req_pq_d1 & (spc3_pcx_data_pa[122:118] == `STORE_RQ) & spc3_pcx_data_pa[109] & spc3_pcx_data_pa[110])
blk_st_cnt3 <= blk_st_cnt3 + 1'b1;
// detect if a normal store came while this counter is not zero.
//--------------------------------------------------------------
if(blk_st_cnt3 & (spc3_pcx_data_pa[122:118] == `STORE_RQ) & ~spc3_pcx_data_pa[109])
st_blkst_mixture3 <= 1'b1;
else if(blk_st_cnt3 == 4'h0)
st_blkst_mixture3 <= 1'b0;
// Multiple init stores without an ACK in between
//---------------------------------------------------
if((cpx_spc3_type == `ST_ACK) | ~rst_l)
ini_st_cnt3 <= 4'h0;
else if(pcx3_req_pq_d1 & (spc3_pcx_data_pa[122:118] == `STORE_RQ) & spc3_pcx_data_pa[109] & ~spc3_pcx_data_pa[110])
ini_st_cnt3 <= ini_st_cnt3 + 1'b1;
// detect if a normal store came while this counter is not zero.
//--------------------------------------------------------------
if(ini_st_cnt3 && (spc3_pcx_data_pa[122:118] == `STORE_RQ) & ~spc3_pcx_data_pa[109])
st_inist_mixture3 <= 1'b1;
else if(ini_st_cnt3 == 4'h0)
st_inist_mixture3 <= 1'b0;
if(~rst_l)
cpx_spc3_ifill_wyvld <= 1'b0;
else
cpx_spc3_ifill_wyvld <= ((cpx_spc3_type == `IFILL_RET) & cpx_spc3_wyvld);
if(~rst_l)
cpx_spc3_dfill_wyvld <= 1'b0;
else
cpx_spc3_dfill_wyvld <= ((cpx_spc3_type == `LOAD_RET) & cpx_spc3_wyvld);
pcx4_vld_d1 <= spc4_pcx_data_pa[123];
pcx4_type_d1 <= spc4_pcx_data_pa[122:118];
pcx4_req_pq_d1 <= |spc4_pcx_req_pq;
pcx4_atom_pq_d1 <= spc4_pcx_atom_pq;
pcx4_atom_pq_d2 <= pcx4_atom_pq_d1;
// Multiple block stores without an ACK in between
//---------------------------------------------------
if((cpx_spc4_type == `ST_ACK) | ~rst_l)
blk_st_cnt4 <= 4'h0;
else if(pcx4_req_pq_d1 & (spc4_pcx_data_pa[122:118] == `STORE_RQ) & spc4_pcx_data_pa[109] & spc4_pcx_data_pa[110])
blk_st_cnt4 <= blk_st_cnt4 + 1'b1;
// detect if a normal store came while this counter is not zero.
//--------------------------------------------------------------
if(blk_st_cnt4 & (spc4_pcx_data_pa[122:118] == `STORE_RQ) & ~spc4_pcx_data_pa[109])
st_blkst_mixture4 <= 1'b1;
else if(blk_st_cnt4 == 4'h0)
st_blkst_mixture4 <= 1'b0;
// Multiple init stores without an ACK in between
//---------------------------------------------------
if((cpx_spc4_type == `ST_ACK) | ~rst_l)
ini_st_cnt4 <= 4'h0;
else if(pcx4_req_pq_d1 & (spc4_pcx_data_pa[122:118] == `STORE_RQ) & spc4_pcx_data_pa[109] & ~spc4_pcx_data_pa[110])
ini_st_cnt4 <= ini_st_cnt4 + 1'b1;
// detect if a normal store came while this counter is not zero.
//--------------------------------------------------------------
if(ini_st_cnt4 && (spc4_pcx_data_pa[122:118] == `STORE_RQ) & ~spc4_pcx_data_pa[109])
st_inist_mixture4 <= 1'b1;
else if(ini_st_cnt4 == 4'h0)
st_inist_mixture4 <= 1'b0;
if(~rst_l)
cpx_spc4_ifill_wyvld <= 1'b0;
else
cpx_spc4_ifill_wyvld <= ((cpx_spc4_type == `IFILL_RET) & cpx_spc4_wyvld);
if(~rst_l)
cpx_spc4_dfill_wyvld <= 1'b0;
else
cpx_spc4_dfill_wyvld <= ((cpx_spc4_type == `LOAD_RET) & cpx_spc4_wyvld);
pcx5_vld_d1 <= spc5_pcx_data_pa[123];
pcx5_type_d1 <= spc5_pcx_data_pa[122:118];
pcx5_req_pq_d1 <= |spc5_pcx_req_pq;
pcx5_atom_pq_d1 <= spc5_pcx_atom_pq;
pcx5_atom_pq_d2 <= pcx5_atom_pq_d1;
// Multiple block stores without an ACK in between
//---------------------------------------------------
if((cpx_spc5_type == `ST_ACK) | ~rst_l)
blk_st_cnt5 <= 4'h0;
else if(pcx5_req_pq_d1 & (spc5_pcx_data_pa[122:118] == `STORE_RQ) & spc5_pcx_data_pa[109] & spc5_pcx_data_pa[110])
blk_st_cnt5 <= blk_st_cnt5 + 1'b1;
// detect if a normal store came while this counter is not zero.
//--------------------------------------------------------------
if(blk_st_cnt5 & (spc5_pcx_data_pa[122:118] == `STORE_RQ) & ~spc5_pcx_data_pa[109])
st_blkst_mixture5 <= 1'b1;
else if(blk_st_cnt5 == 4'h0)
st_blkst_mixture5 <= 1'b0;
// Multiple init stores without an ACK in between
//---------------------------------------------------
if((cpx_spc5_type == `ST_ACK) | ~rst_l)
ini_st_cnt5 <= 4'h0;
else if(pcx5_req_pq_d1 & (spc5_pcx_data_pa[122:118] == `STORE_RQ) & spc5_pcx_data_pa[109] & ~spc5_pcx_data_pa[110])
ini_st_cnt5 <= ini_st_cnt5 + 1'b1;
// detect if a normal store came while this counter is not zero.
//--------------------------------------------------------------
if(ini_st_cnt5 && (spc5_pcx_data_pa[122:118] == `STORE_RQ) & ~spc5_pcx_data_pa[109])
st_inist_mixture5 <= 1'b1;
else if(ini_st_cnt5 == 4'h0)
st_inist_mixture5 <= 1'b0;
if(~rst_l)
cpx_spc5_ifill_wyvld <= 1'b0;
else
cpx_spc5_ifill_wyvld <= ((cpx_spc5_type == `IFILL_RET) & cpx_spc5_wyvld);
if(~rst_l)
cpx_spc5_dfill_wyvld <= 1'b0;
else
cpx_spc5_dfill_wyvld <= ((cpx_spc5_type == `LOAD_RET) & cpx_spc5_wyvld);
pcx6_vld_d1 <= spc6_pcx_data_pa[123];
pcx6_type_d1 <= spc6_pcx_data_pa[122:118];
pcx6_req_pq_d1 <= |spc6_pcx_req_pq;
pcx6_atom_pq_d1 <= spc6_pcx_atom_pq;
pcx6_atom_pq_d2 <= pcx6_atom_pq_d1;
// Multiple block stores without an ACK in between
//---------------------------------------------------
if((cpx_spc6_type == `ST_ACK) | ~rst_l)
blk_st_cnt6 <= 4'h0;
else if(pcx6_req_pq_d1 & (spc6_pcx_data_pa[122:118] == `STORE_RQ) & spc6_pcx_data_pa[109] & spc6_pcx_data_pa[110])
blk_st_cnt6 <= blk_st_cnt6 + 1'b1;
// detect if a normal store came while this counter is not zero.
//--------------------------------------------------------------
if(blk_st_cnt6 & (spc6_pcx_data_pa[122:118] == `STORE_RQ) & ~spc6_pcx_data_pa[109])
st_blkst_mixture6 <= 1'b1;
else if(blk_st_cnt6 == 4'h0)
st_blkst_mixture6 <= 1'b0;
// Multiple init stores without an ACK in between
//---------------------------------------------------
if((cpx_spc6_type == `ST_ACK) | ~rst_l)
ini_st_cnt6 <= 4'h0;
else if(pcx6_req_pq_d1 & (spc6_pcx_data_pa[122:118] == `STORE_RQ) & spc6_pcx_data_pa[109] & ~spc6_pcx_data_pa[110])
ini_st_cnt6 <= ini_st_cnt6 + 1'b1;
// detect if a normal store came while this counter is not zero.
//--------------------------------------------------------------
if(ini_st_cnt6 && (spc6_pcx_data_pa[122:118] == `STORE_RQ) & ~spc6_pcx_data_pa[109])
st_inist_mixture6 <= 1'b1;
else if(ini_st_cnt6 == 4'h0)
st_inist_mixture6 <= 1'b0;
if(~rst_l)
cpx_spc6_ifill_wyvld <= 1'b0;
else
cpx_spc6_ifill_wyvld <= ((cpx_spc6_type == `IFILL_RET) & cpx_spc6_wyvld);
if(~rst_l)
cpx_spc6_dfill_wyvld <= 1'b0;
else
cpx_spc6_dfill_wyvld <= ((cpx_spc6_type == `LOAD_RET) & cpx_spc6_wyvld);
pcx7_vld_d1 <= spc7_pcx_data_pa[123];
pcx7_type_d1 <= spc7_pcx_data_pa[122:118];
pcx7_req_pq_d1 <= |spc7_pcx_req_pq;
pcx7_atom_pq_d1 <= spc7_pcx_atom_pq;
pcx7_atom_pq_d2 <= pcx7_atom_pq_d1;
// Multiple block stores without an ACK in between
//---------------------------------------------------
if((cpx_spc7_type == `ST_ACK) | ~rst_l)
blk_st_cnt7 <= 4'h0;
else if(pcx7_req_pq_d1 & (spc7_pcx_data_pa[122:118] == `STORE_RQ) & spc7_pcx_data_pa[109] & spc7_pcx_data_pa[110])
blk_st_cnt7 <= blk_st_cnt7 + 1'b1;
// detect if a normal store came while this counter is not zero.
//--------------------------------------------------------------
if(blk_st_cnt7 & (spc7_pcx_data_pa[122:118] == `STORE_RQ) & ~spc7_pcx_data_pa[109])
st_blkst_mixture7 <= 1'b1;
else if(blk_st_cnt7 == 4'h0)
st_blkst_mixture7 <= 1'b0;
// Multiple init stores without an ACK in between
//---------------------------------------------------
if((cpx_spc7_type == `ST_ACK) | ~rst_l)
ini_st_cnt7 <= 4'h0;
else if(pcx7_req_pq_d1 & (spc7_pcx_data_pa[122:118] == `STORE_RQ) & spc7_pcx_data_pa[109] & ~spc7_pcx_data_pa[110])
ini_st_cnt7 <= ini_st_cnt7 + 1'b1;
// detect if a normal store came while this counter is not zero.
//--------------------------------------------------------------
if(ini_st_cnt7 && (spc7_pcx_data_pa[122:118] == `STORE_RQ) & ~spc7_pcx_data_pa[109])
st_inist_mixture7 <= 1'b1;
else if(ini_st_cnt7 == 4'h0)
st_inist_mixture7 <= 1'b0;
if(~rst_l)
cpx_spc7_ifill_wyvld <= 1'b0;
else
cpx_spc7_ifill_wyvld <= ((cpx_spc7_type == `IFILL_RET) & cpx_spc7_wyvld);
if(~rst_l)
cpx_spc7_dfill_wyvld <= 1'b0;
else
cpx_spc7_dfill_wyvld <= ((cpx_spc7_type == `LOAD_RET) & cpx_spc7_wyvld);
end
wire ifill_wyvld = cpx_spc0_ifill_wyvld;
wire dfill_wyvld = cpx_spc0_dfill_wyvld;
always @(negedge clk)
begin
if (rst_l & (^spc0_pcx_req_pq === 1'bx))
finish_test("spc", "pcx_req_pq has X-s", 0);
else if(rst_l & pcx0_req_pq_d1)
get_pcx( spc0_pcx_type_str, spc0_pcx_data_pa, pcx0_type_d1,
pcx0_atom_pq_d1, pcx0_atom_pq_d2, 3'h0, pcx0_req_pq_d1);
if (rst_l & (^spc1_pcx_req_pq === 1'bx))
finish_test("spc", "pcx_req_pq has X-s", 1);
else if(rst_l & pcx1_req_pq_d1)
get_pcx( spc1_pcx_type_str, spc1_pcx_data_pa, pcx1_type_d1,
pcx1_atom_pq_d1, pcx1_atom_pq_d2, 3'h1, pcx1_req_pq_d1);
if (rst_l & (^spc2_pcx_req_pq === 1'bx))
finish_test("spc", "pcx_req_pq has X-s", 2);
else if(rst_l & pcx2_req_pq_d1)
get_pcx( spc2_pcx_type_str, spc2_pcx_data_pa, pcx2_type_d1,
pcx2_atom_pq_d1, pcx2_atom_pq_d2, 3'h2, pcx2_req_pq_d1);
if (rst_l & (^spc3_pcx_req_pq === 1'bx))
finish_test("spc", "pcx_req_pq has X-s", 3);
else if(rst_l & pcx3_req_pq_d1)
get_pcx( spc3_pcx_type_str, spc3_pcx_data_pa, pcx3_type_d1,
pcx3_atom_pq_d1, pcx3_atom_pq_d2, 3'h3, pcx3_req_pq_d1);
if (rst_l & (^spc4_pcx_req_pq === 1'bx))
finish_test("spc", "pcx_req_pq has X-s", 4);
else if(rst_l & pcx4_req_pq_d1)
get_pcx( spc4_pcx_type_str, spc4_pcx_data_pa, pcx4_type_d1,
pcx4_atom_pq_d1, pcx4_atom_pq_d2, 3'h4, pcx4_req_pq_d1);
if (rst_l & (^spc5_pcx_req_pq === 1'bx))
finish_test("spc", "pcx_req_pq has X-s", 5);
else if(rst_l & pcx5_req_pq_d1)
get_pcx( spc5_pcx_type_str, spc5_pcx_data_pa, pcx5_type_d1,
pcx5_atom_pq_d1, pcx5_atom_pq_d2, 3'h5, pcx5_req_pq_d1);
if (rst_l & (^spc6_pcx_req_pq === 1'bx))
finish_test("spc", "pcx_req_pq has X-s", 6);
else if(rst_l & pcx6_req_pq_d1)
get_pcx( spc6_pcx_type_str, spc6_pcx_data_pa, pcx6_type_d1,
pcx6_atom_pq_d1, pcx6_atom_pq_d2, 3'h6, pcx6_req_pq_d1);
if (rst_l & (^spc7_pcx_req_pq === 1'bx))
finish_test("spc", "pcx_req_pq has X-s", 7);
else if(rst_l & pcx7_req_pq_d1)
get_pcx( spc7_pcx_type_str, spc7_pcx_data_pa, pcx7_type_d1,
pcx7_atom_pq_d1, pcx7_atom_pq_d2, 3'h7, pcx7_req_pq_d1);
end
//----------------------------------------------------------------------------------------
// This section deals with the sctag to cpx packets
// All the info signals are just for usage by the tso coverage vera objects
//----------------------------------------------------------------------------------------
reg [3:0] sctag0_valid_spcs;
reg [3:0] cpx0_inv_fanout;
reg [3:0] sctag1_valid_spcs;
reg [3:0] cpx1_inv_fanout;
reg [3:0] sctag2_valid_spcs;
reg [3:0] cpx2_inv_fanout;
reg [3:0] sctag3_valid_spcs;
reg [3:0] cpx3_inv_fanout;
reg [3:0] sctag4_valid_spcs;
reg [3:0] cpx4_inv_fanout;
reg [3:0] sctag5_valid_spcs;
reg [3:0] cpx5_inv_fanout;
reg [3:0] sctag6_valid_spcs;
reg [3:0] cpx6_inv_fanout;
reg [3:0] sctag7_valid_spcs;
reg [3:0] cpx7_inv_fanout;
reg multiple_inv01;
reg multiple_inv01_multiple_fanout;
reg multiple_inv0123;
reg multiple_inv0123_multiple_fanout;
wire [3:0] multiple_fanout_info = { multiple_inv01_multiple_fanout, multiple_inv01,
multiple_inv0123_multiple_fanout, multiple_inv0123};
always @(posedge clk)
begin
sctag0_cpx_req_cq_d1 <= sctag0_cpx_req_cq;
sctag0_cpx_atom_cq_d1 <= sctag0_cpx_atom_cq;
sctag0_cpx_atom_cq_d2 <= sctag0_cpx_atom_cq_d1;
sctag1_cpx_req_cq_d1 <= sctag1_cpx_req_cq;
sctag1_cpx_atom_cq_d1 <= sctag1_cpx_atom_cq;
sctag1_cpx_atom_cq_d2 <= sctag1_cpx_atom_cq_d1;
sctag2_cpx_req_cq_d1 <= sctag2_cpx_req_cq;
sctag2_cpx_atom_cq_d1 <= sctag2_cpx_atom_cq;
sctag2_cpx_atom_cq_d2 <= sctag2_cpx_atom_cq_d1;
sctag3_cpx_req_cq_d1 <= sctag3_cpx_req_cq;
sctag3_cpx_atom_cq_d1 <= sctag3_cpx_atom_cq;
sctag3_cpx_atom_cq_d2 <= sctag3_cpx_atom_cq_d1;
end
always @(negedge clk)
begin
if(rst_l)
begin
get_sctag_cpx(sctag0_cpx_type, sctag0_cpx_type_str, sctag0_cpx_req_cq_d1, sctag0_cpx_data_ca, 3'h0);
sctag0_valid_spcs =
sctag0_cpx_req_cq_d1[0] + sctag0_cpx_req_cq_d1[1] + sctag0_cpx_req_cq_d1[2] +
sctag0_cpx_req_cq_d1[3] + sctag0_cpx_req_cq_d1[4] + sctag0_cpx_req_cq_d1[5] +
sctag0_cpx_req_cq_d1[6] + sctag0_cpx_req_cq_d1[7];
if((sctag0_valid_spcs > 0) &
((sctag0_cpx_type == `ST_ACK) | (sctag0_cpx_type == `STRST_ACK) | (sctag0_cpx_type == `EVICT_REQ)))
begin
cpx0_inv_fanout = sctag0_valid_spcs;
if(tso_mon_msg) $display("%0d tso_mon: sctag0 invalidation to multiple cores %d", $time, cpx0_inv_fanout);
end
else
begin
cpx0_inv_fanout = 4'h0;
end
sctag0_dc_lkup_c5 <= |sctag0_dc_lkup_panel_dec_c4 & |sctag0_dc_lkup_row_dec_c4;
sctag0_ic_lkup_c5 <= |sctag0_ic_lkup_panel_dec_c4 & |sctag0_ic_lkup_row_dec_c4;
sctag0_dc_lkup_c6 <= sctag0_dc_lkup_c5;
sctag0_ic_lkup_c6 <= sctag0_ic_lkup_c5;
// THESE ARE ACTUALLY CHECKERS - THEY ARE IMPORTANT - CAUGHT A FEW BUGS
//----------------------------------------------------------------------
if(sctag0_ic_lkup_c6)
begin
if(sctag0_ic_cam_hit_c6_nibble0_sum>1)
finish_test("sctag", "tso_mon: L2 IC DIR multiple hits ", 0);
if(sctag0_ic_cam_hit_c6_nibble1_sum>1)
finish_test("sctag", "tso_mon: L2 IC DIR multiple hits ", 0);
if(sctag0_ic_cam_hit_c6_nibble2_sum>1)
finish_test("sctag", "tso_mon: L2 IC DIR multiple hits ", 0);
if(sctag0_ic_cam_hit_c6_nibble3_sum>1)
finish_test("sctag", "tso_mon: L2 IC DIR multiple hits ", 0);
if(sctag0_ic_cam_hit_c6_nibble4_sum>1)
finish_test("sctag", "tso_mon: L2 IC DIR multiple hits ", 0);
if(sctag0_ic_cam_hit_c6_nibble5_sum>1)
finish_test("sctag", "tso_mon: L2 IC DIR multiple hits ", 0);
if(sctag0_ic_cam_hit_c6_nibble6_sum>1)
finish_test("sctag", "tso_mon: L2 IC DIR multiple hits ", 0);
if(sctag0_ic_cam_hit_c6_nibble7_sum>1)
finish_test("sctag", "tso_mon: L2 IC DIR multiple hits ", 0);
if(sctag0_ic_cam_hit_c6_nibble16_sum>1)
finish_test("sctag", "tso_mon: L2 IC DIR multiple hits ", 0);
if(sctag0_ic_cam_hit_c6_nibble17_sum>1)
finish_test("sctag", "tso_mon: L2 IC DIR multiple hits ", 0);
if(sctag0_ic_cam_hit_c6_nibble18_sum>1)
finish_test("sctag", "tso_mon: L2 IC DIR multiple hits ", 0);
if(sctag0_ic_cam_hit_c6_nibble19_sum>1)
finish_test("sctag", "tso_mon: L2 IC DIR multiple hits ", 0);
if(sctag0_ic_cam_hit_c6_nibble20_sum>1)
finish_test("sctag", "tso_mon: L2 IC DIR multiple hits ", 0);
if(sctag0_ic_cam_hit_c6_nibble21_sum>1)
finish_test("sctag", "tso_mon: L2 IC DIR multiple hits ", 0);
if(sctag0_ic_cam_hit_c6_nibble22_sum>1)
finish_test("sctag", "tso_mon: L2 IC DIR multiple hits ", 0);
if(sctag0_ic_cam_hit_c6_nibble23_sum>1)
finish_test("sctag", "tso_mon: L2 IC DIR multiple hits ", 0);
end
if(sctag0_dc_lkup_c6)
begin
if(sctag0_dc_cam_hit_c6_nibble0_sum>1)
finish_test("sctag", "tso_mon: L2 DC DIR multiple hits ", 0);
if(sctag0_dc_cam_hit_c6_nibble1_sum>1)
finish_test("sctag", "tso_mon: L2 DC DIR multiple hits ", 0);
if(sctag0_dc_cam_hit_c6_nibble2_sum>1)
finish_test("sctag", "tso_mon: L2 DC DIR multiple hits ", 0);
if(sctag0_dc_cam_hit_c6_nibble3_sum>1)
finish_test("sctag", "tso_mon: L2 DC DIR multiple hits ", 0);
if(sctag0_dc_cam_hit_c6_nibble4_sum>1)
finish_test("sctag", "tso_mon: L2 DC DIR multiple hits ", 0);
if(sctag0_dc_cam_hit_c6_nibble5_sum>1)
finish_test("sctag", "tso_mon: L2 DC DIR multiple hits ", 0);
if(sctag0_dc_cam_hit_c6_nibble6_sum>1)
finish_test("sctag", "tso_mon: L2 DC DIR multiple hits ", 0);
if(sctag0_dc_cam_hit_c6_nibble7_sum>1)
finish_test("sctag", "tso_mon: L2 DC DIR multiple hits ", 0);
if(sctag0_dc_cam_hit_c6_nibble8_sum>1)
finish_test("sctag", "tso_mon: L2 DC DIR multiple hits ", 0);
if(sctag0_dc_cam_hit_c6_nibble9_sum>1)
finish_test("sctag", "tso_mon: L2 DC DIR multiple hits ", 0);
if(sctag0_dc_cam_hit_c6_nibble10_sum>1)
finish_test("sctag", "tso_mon: L2 DC DIR multiple hits ", 0);
if(sctag0_dc_cam_hit_c6_nibble11_sum>1)
finish_test("sctag", "tso_mon: L2 DC DIR multiple hits ", 0);
if(sctag0_dc_cam_hit_c6_nibble12_sum>1)
finish_test("sctag", "tso_mon: L2 DC DIR multiple hits ", 0);
if(sctag0_dc_cam_hit_c6_nibble13_sum>1)
finish_test("sctag", "tso_mon: L2 DC DIR multiple hits ", 0);
if(sctag0_dc_cam_hit_c6_nibble14_sum>1)
finish_test("sctag", "tso_mon: L2 DC DIR multiple hits ", 0);
if(sctag0_dc_cam_hit_c6_nibble15_sum>1)
finish_test("sctag", "tso_mon: L2 DC DIR multiple hits ", 0);
if(sctag0_dc_cam_hit_c6_nibble16_sum>1)
finish_test("sctag", "tso_mon: L2 DC DIR multiple hits ", 0);
if(sctag0_dc_cam_hit_c6_nibble17_sum>1)
finish_test("sctag", "tso_mon: L2 DC DIR multiple hits ", 0);
if(sctag0_dc_cam_hit_c6_nibble18_sum>1)
finish_test("sctag", "tso_mon: L2 DC DIR multiple hits ", 0);
if(sctag0_dc_cam_hit_c6_nibble19_sum>1)
finish_test("sctag", "tso_mon: L2 DC DIR multiple hits ", 0);
if(sctag0_dc_cam_hit_c6_nibble20_sum>1)
finish_test("sctag", "tso_mon: L2 DC DIR multiple hits ", 0);
if(sctag0_dc_cam_hit_c6_nibble21_sum>1)
finish_test("sctag", "tso_mon: L2 DC DIR multiple hits ", 0);
if(sctag0_dc_cam_hit_c6_nibble22_sum>1)
finish_test("sctag", "tso_mon: L2 DC DIR multiple hits ", 0);
if(sctag0_dc_cam_hit_c6_nibble23_sum>1)
finish_test("sctag", "tso_mon: L2 DC DIR multiple hits ", 0);
if(sctag0_dc_cam_hit_c6_nibble24_sum>1)
finish_test("sctag", "tso_mon: L2 DC DIR multiple hits ", 0);
if(sctag0_dc_cam_hit_c6_nibble25_sum>1)
finish_test("sctag", "tso_mon: L2 DC DIR multiple hits ", 0);
if(sctag0_dc_cam_hit_c6_nibble26_sum>1)
finish_test("sctag", "tso_mon: L2 DC DIR multiple hits ", 0);
if(sctag0_dc_cam_hit_c6_nibble27_sum>1)
finish_test("sctag", "tso_mon: L2 DC DIR multiple hits ", 0);
if(sctag0_dc_cam_hit_c6_nibble28_sum>1)
finish_test("sctag", "tso_mon: L2 DC DIR multiple hits ", 0);
if(sctag0_dc_cam_hit_c6_nibble29_sum>1)
finish_test("sctag", "tso_mon: L2 DC DIR multiple hits ", 0);
if(sctag0_dc_cam_hit_c6_nibble30_sum>1)
finish_test("sctag", "tso_mon: L2 DC DIR multiple hits ", 0);
if(sctag0_dc_cam_hit_c6_nibble31_sum>1)
finish_test("sctag", "tso_mon: L2 DC DIR multiple hits ", 0);
end
if(sctag0_ic_lkup_c6 & sctag0_dc_lkup_c6)
begin
if(sctag0_both_cam_hit_c6_nibble0_sum>1)
finish_test("sctag", "tso_mon: L2 ICDC DIR multiple hits ", 0);
if(sctag0_both_cam_hit_c6_nibble1_sum>1)
finish_test("sctag", "tso_mon: L2 ICDC DIR multiple hits ", 0);
if(sctag0_both_cam_hit_c6_nibble2_sum>1)
finish_test("sctag", "tso_mon: L2 ICDC DIR multiple hits ", 0);
if(sctag0_both_cam_hit_c6_nibble3_sum>1)
finish_test("sctag", "tso_mon: L2 ICDC DIR multiple hits ", 0);
if(sctag0_both_cam_hit_c6_nibble4_sum>1)
finish_test("sctag", "tso_mon: L2 ICDC DIR multiple hits ", 0);
if(sctag0_both_cam_hit_c6_nibble5_sum>1)
finish_test("sctag", "tso_mon: L2 ICDC DIR multiple hits ", 0);
if(sctag0_both_cam_hit_c6_nibble6_sum>1)
finish_test("sctag", "tso_mon: L2 ICDC DIR multiple hits ", 0);
if(sctag0_both_cam_hit_c6_nibble7_sum>1)
finish_test("sctag", "tso_mon: L2 ICDC DIR multiple hits ", 0);
if(sctag0_both_cam_hit_c6_nibble16_sum>1)
finish_test("sctag", "tso_mon: L2 ICDC DIR multiple hits ", 0);
if(sctag0_both_cam_hit_c6_nibble17_sum>1)
finish_test("sctag", "tso_mon: L2 ICDC DIR multiple hits ", 0);
if(sctag0_both_cam_hit_c6_nibble18_sum>1)
finish_test("sctag", "tso_mon: L2 ICDC DIR multiple hits ", 0);
if(sctag0_both_cam_hit_c6_nibble19_sum>1)
finish_test("sctag", "tso_mon: L2 ICDC DIR multiple hits ", 0);
if(sctag0_both_cam_hit_c6_nibble20_sum>1)
finish_test("sctag", "tso_mon: L2 ICDC DIR multiple hits ", 0);
if(sctag0_both_cam_hit_c6_nibble21_sum>1)
finish_test("sctag", "tso_mon: L2 ICDC DIR multiple hits ", 0);
if(sctag0_both_cam_hit_c6_nibble22_sum>1)
finish_test("sctag", "tso_mon: L2 ICDC DIR multiple hits ", 0);
if(sctag0_both_cam_hit_c6_nibble23_sum>1)
finish_test("sctag", "tso_mon: L2 ICDC DIR multiple hits ", 0);
end
get_sctag_cpx(sctag1_cpx_type, sctag1_cpx_type_str, sctag1_cpx_req_cq_d1, sctag1_cpx_data_ca, 3'h1);
sctag1_valid_spcs =
sctag1_cpx_req_cq_d1[0] + sctag1_cpx_req_cq_d1[1] + sctag1_cpx_req_cq_d1[2] +
sctag1_cpx_req_cq_d1[3] + sctag1_cpx_req_cq_d1[4] + sctag1_cpx_req_cq_d1[5] +
sctag1_cpx_req_cq_d1[6] + sctag1_cpx_req_cq_d1[7];
if((sctag1_valid_spcs > 0) &
((sctag1_cpx_type == `ST_ACK) | (sctag1_cpx_type == `STRST_ACK) | (sctag1_cpx_type == `EVICT_REQ)))
begin
cpx1_inv_fanout = sctag1_valid_spcs;
if(tso_mon_msg) $display("%0d tso_mon: sctag1 invalidation to multiple cores %d", $time, cpx1_inv_fanout);
end
else
begin
cpx1_inv_fanout = 4'h0;
end
sctag1_dc_lkup_c5 <= |sctag1_dc_lkup_panel_dec_c4 & |sctag1_dc_lkup_row_dec_c4;
sctag1_ic_lkup_c5 <= |sctag1_ic_lkup_panel_dec_c4 & |sctag1_ic_lkup_row_dec_c4;
sctag1_dc_lkup_c6 <= sctag1_dc_lkup_c5;
sctag1_ic_lkup_c6 <= sctag1_ic_lkup_c5;
// THESE ARE ACTUALLY CHECKERS - THEY ARE IMPORTANT - CAUGHT A FEW BUGS
//----------------------------------------------------------------------
if(sctag1_ic_lkup_c6)
begin
if(sctag1_ic_cam_hit_c6_nibble0_sum>1)
finish_test("sctag", "tso_mon: L2 IC DIR multiple hits ", 1);
if(sctag1_ic_cam_hit_c6_nibble1_sum>1)
finish_test("sctag", "tso_mon: L2 IC DIR multiple hits ", 1);
if(sctag1_ic_cam_hit_c6_nibble2_sum>1)
finish_test("sctag", "tso_mon: L2 IC DIR multiple hits ", 1);
if(sctag1_ic_cam_hit_c6_nibble3_sum>1)
finish_test("sctag", "tso_mon: L2 IC DIR multiple hits ", 1);
if(sctag1_ic_cam_hit_c6_nibble4_sum>1)
finish_test("sctag", "tso_mon: L2 IC DIR multiple hits ", 1);
if(sctag1_ic_cam_hit_c6_nibble5_sum>1)
finish_test("sctag", "tso_mon: L2 IC DIR multiple hits ", 1);
if(sctag1_ic_cam_hit_c6_nibble6_sum>1)
finish_test("sctag", "tso_mon: L2 IC DIR multiple hits ", 1);
if(sctag1_ic_cam_hit_c6_nibble7_sum>1)
finish_test("sctag", "tso_mon: L2 IC DIR multiple hits ", 1);
if(sctag1_ic_cam_hit_c6_nibble16_sum>1)
finish_test("sctag", "tso_mon: L2 IC DIR multiple hits ", 1);
if(sctag1_ic_cam_hit_c6_nibble17_sum>1)
finish_test("sctag", "tso_mon: L2 IC DIR multiple hits ", 1);
if(sctag1_ic_cam_hit_c6_nibble18_sum>1)
finish_test("sctag", "tso_mon: L2 IC DIR multiple hits ", 1);
if(sctag1_ic_cam_hit_c6_nibble19_sum>1)
finish_test("sctag", "tso_mon: L2 IC DIR multiple hits ", 1);
if(sctag1_ic_cam_hit_c6_nibble20_sum>1)
finish_test("sctag", "tso_mon: L2 IC DIR multiple hits ", 1);
if(sctag1_ic_cam_hit_c6_nibble21_sum>1)
finish_test("sctag", "tso_mon: L2 IC DIR multiple hits ", 1);
if(sctag1_ic_cam_hit_c6_nibble22_sum>1)
finish_test("sctag", "tso_mon: L2 IC DIR multiple hits ", 1);
if(sctag1_ic_cam_hit_c6_nibble23_sum>1)
finish_test("sctag", "tso_mon: L2 IC DIR multiple hits ", 1);
end
if(sctag1_dc_lkup_c6)
begin
if(sctag1_dc_cam_hit_c6_nibble0_sum>1)
finish_test("sctag", "tso_mon: L2 DC DIR multiple hits ", 1);
if(sctag1_dc_cam_hit_c6_nibble1_sum>1)
finish_test("sctag", "tso_mon: L2 DC DIR multiple hits ", 1);
if(sctag1_dc_cam_hit_c6_nibble2_sum>1)
finish_test("sctag", "tso_mon: L2 DC DIR multiple hits ", 1);
if(sctag1_dc_cam_hit_c6_nibble3_sum>1)
finish_test("sctag", "tso_mon: L2 DC DIR multiple hits ", 1);
if(sctag1_dc_cam_hit_c6_nibble4_sum>1)
finish_test("sctag", "tso_mon: L2 DC DIR multiple hits ", 1);
if(sctag1_dc_cam_hit_c6_nibble5_sum>1)
finish_test("sctag", "tso_mon: L2 DC DIR multiple hits ", 1);
if(sctag1_dc_cam_hit_c6_nibble6_sum>1)
finish_test("sctag", "tso_mon: L2 DC DIR multiple hits ", 1);
if(sctag1_dc_cam_hit_c6_nibble7_sum>1)
finish_test("sctag", "tso_mon: L2 DC DIR multiple hits ", 1);
if(sctag1_dc_cam_hit_c6_nibble8_sum>1)
finish_test("sctag", "tso_mon: L2 DC DIR multiple hits ", 1);
if(sctag1_dc_cam_hit_c6_nibble9_sum>1)
finish_test("sctag", "tso_mon: L2 DC DIR multiple hits ", 1);
if(sctag1_dc_cam_hit_c6_nibble10_sum>1)
finish_test("sctag", "tso_mon: L2 DC DIR multiple hits ", 1);
if(sctag1_dc_cam_hit_c6_nibble11_sum>1)
finish_test("sctag", "tso_mon: L2 DC DIR multiple hits ", 1);
if(sctag1_dc_cam_hit_c6_nibble12_sum>1)
finish_test("sctag", "tso_mon: L2 DC DIR multiple hits ", 1);
if(sctag1_dc_cam_hit_c6_nibble13_sum>1)
finish_test("sctag", "tso_mon: L2 DC DIR multiple hits ", 1);
if(sctag1_dc_cam_hit_c6_nibble14_sum>1)
finish_test("sctag", "tso_mon: L2 DC DIR multiple hits ", 1);
if(sctag1_dc_cam_hit_c6_nibble15_sum>1)
finish_test("sctag", "tso_mon: L2 DC DIR multiple hits ", 1);
if(sctag1_dc_cam_hit_c6_nibble16_sum>1)
finish_test("sctag", "tso_mon: L2 DC DIR multiple hits ", 1);
if(sctag1_dc_cam_hit_c6_nibble17_sum>1)
finish_test("sctag", "tso_mon: L2 DC DIR multiple hits ", 1);
if(sctag1_dc_cam_hit_c6_nibble18_sum>1)
finish_test("sctag", "tso_mon: L2 DC DIR multiple hits ", 1);
if(sctag1_dc_cam_hit_c6_nibble19_sum>1)
finish_test("sctag", "tso_mon: L2 DC DIR multiple hits ", 1);
if(sctag1_dc_cam_hit_c6_nibble20_sum>1)
finish_test("sctag", "tso_mon: L2 DC DIR multiple hits ", 1);
if(sctag1_dc_cam_hit_c6_nibble21_sum>1)
finish_test("sctag", "tso_mon: L2 DC DIR multiple hits ", 1);
if(sctag1_dc_cam_hit_c6_nibble22_sum>1)
finish_test("sctag", "tso_mon: L2 DC DIR multiple hits ", 1);
if(sctag1_dc_cam_hit_c6_nibble23_sum>1)
finish_test("sctag", "tso_mon: L2 DC DIR multiple hits ", 1);
if(sctag1_dc_cam_hit_c6_nibble24_sum>1)
finish_test("sctag", "tso_mon: L2 DC DIR multiple hits ", 1);
if(sctag1_dc_cam_hit_c6_nibble25_sum>1)
finish_test("sctag", "tso_mon: L2 DC DIR multiple hits ", 1);
if(sctag1_dc_cam_hit_c6_nibble26_sum>1)
finish_test("sctag", "tso_mon: L2 DC DIR multiple hits ", 1);
if(sctag1_dc_cam_hit_c6_nibble27_sum>1)
finish_test("sctag", "tso_mon: L2 DC DIR multiple hits ", 1);
if(sctag1_dc_cam_hit_c6_nibble28_sum>1)
finish_test("sctag", "tso_mon: L2 DC DIR multiple hits ", 1);
if(sctag1_dc_cam_hit_c6_nibble29_sum>1)
finish_test("sctag", "tso_mon: L2 DC DIR multiple hits ", 1);
if(sctag1_dc_cam_hit_c6_nibble30_sum>1)
finish_test("sctag", "tso_mon: L2 DC DIR multiple hits ", 1);
if(sctag1_dc_cam_hit_c6_nibble31_sum>1)
finish_test("sctag", "tso_mon: L2 DC DIR multiple hits ", 1);
end
if(sctag1_ic_lkup_c6 & sctag1_dc_lkup_c6)
begin
if(sctag1_both_cam_hit_c6_nibble0_sum>1)
finish_test("sctag", "tso_mon: L2 ICDC DIR multiple hits ", 1);
if(sctag1_both_cam_hit_c6_nibble1_sum>1)
finish_test("sctag", "tso_mon: L2 ICDC DIR multiple hits ", 1);
if(sctag1_both_cam_hit_c6_nibble2_sum>1)
finish_test("sctag", "tso_mon: L2 ICDC DIR multiple hits ", 1);
if(sctag1_both_cam_hit_c6_nibble3_sum>1)
finish_test("sctag", "tso_mon: L2 ICDC DIR multiple hits ", 1);
if(sctag1_both_cam_hit_c6_nibble4_sum>1)
finish_test("sctag", "tso_mon: L2 ICDC DIR multiple hits ", 1);
if(sctag1_both_cam_hit_c6_nibble5_sum>1)
finish_test("sctag", "tso_mon: L2 ICDC DIR multiple hits ", 1);
if(sctag1_both_cam_hit_c6_nibble6_sum>1)
finish_test("sctag", "tso_mon: L2 ICDC DIR multiple hits ", 1);
if(sctag1_both_cam_hit_c6_nibble7_sum>1)
finish_test("sctag", "tso_mon: L2 ICDC DIR multiple hits ", 1);
if(sctag1_both_cam_hit_c6_nibble16_sum>1)
finish_test("sctag", "tso_mon: L2 ICDC DIR multiple hits ", 1);
if(sctag1_both_cam_hit_c6_nibble17_sum>1)
finish_test("sctag", "tso_mon: L2 ICDC DIR multiple hits ", 1);
if(sctag1_both_cam_hit_c6_nibble18_sum>1)
finish_test("sctag", "tso_mon: L2 ICDC DIR multiple hits ", 1);
if(sctag1_both_cam_hit_c6_nibble19_sum>1)
finish_test("sctag", "tso_mon: L2 ICDC DIR multiple hits ", 1);
if(sctag1_both_cam_hit_c6_nibble20_sum>1)
finish_test("sctag", "tso_mon: L2 ICDC DIR multiple hits ", 1);
if(sctag1_both_cam_hit_c6_nibble21_sum>1)
finish_test("sctag", "tso_mon: L2 ICDC DIR multiple hits ", 1);
if(sctag1_both_cam_hit_c6_nibble22_sum>1)
finish_test("sctag", "tso_mon: L2 ICDC DIR multiple hits ", 1);
if(sctag1_both_cam_hit_c6_nibble23_sum>1)
finish_test("sctag", "tso_mon: L2 ICDC DIR multiple hits ", 1);
end
get_sctag_cpx(sctag2_cpx_type, sctag2_cpx_type_str, sctag2_cpx_req_cq_d1, sctag2_cpx_data_ca, 3'h2);
sctag2_valid_spcs =
sctag2_cpx_req_cq_d1[0] + sctag2_cpx_req_cq_d1[1] + sctag2_cpx_req_cq_d1[2] +
sctag2_cpx_req_cq_d1[3] + sctag2_cpx_req_cq_d1[4] + sctag2_cpx_req_cq_d1[5] +
sctag2_cpx_req_cq_d1[6] + sctag2_cpx_req_cq_d1[7];
if((sctag2_valid_spcs > 0) &
((sctag2_cpx_type == `ST_ACK) | (sctag2_cpx_type == `STRST_ACK) | (sctag2_cpx_type == `EVICT_REQ)))
begin
cpx2_inv_fanout = sctag2_valid_spcs;
if(tso_mon_msg) $display("%0d tso_mon: sctag2 invalidation to multiple cores %d", $time, cpx2_inv_fanout);
end
else
begin
cpx2_inv_fanout = 4'h0;
end
sctag2_dc_lkup_c5 <= |sctag2_dc_lkup_panel_dec_c4 & |sctag2_dc_lkup_row_dec_c4;
sctag2_ic_lkup_c5 <= |sctag2_ic_lkup_panel_dec_c4 & |sctag2_ic_lkup_row_dec_c4;
sctag2_dc_lkup_c6 <= sctag2_dc_lkup_c5;
sctag2_ic_lkup_c6 <= sctag2_ic_lkup_c5;
// THESE ARE ACTUALLY CHECKERS - THEY ARE IMPORTANT - CAUGHT A FEW BUGS
//----------------------------------------------------------------------
if(sctag2_ic_lkup_c6)
begin
if(sctag2_ic_cam_hit_c6_nibble0_sum>1)
finish_test("sctag", "tso_mon: L2 IC DIR multiple hits ", 2);
if(sctag2_ic_cam_hit_c6_nibble1_sum>1)
finish_test("sctag", "tso_mon: L2 IC DIR multiple hits ", 2);
if(sctag2_ic_cam_hit_c6_nibble2_sum>1)
finish_test("sctag", "tso_mon: L2 IC DIR multiple hits ", 2);
if(sctag2_ic_cam_hit_c6_nibble3_sum>1)
finish_test("sctag", "tso_mon: L2 IC DIR multiple hits ", 2);
if(sctag2_ic_cam_hit_c6_nibble4_sum>1)
finish_test("sctag", "tso_mon: L2 IC DIR multiple hits ", 2);
if(sctag2_ic_cam_hit_c6_nibble5_sum>1)
finish_test("sctag", "tso_mon: L2 IC DIR multiple hits ", 2);
if(sctag2_ic_cam_hit_c6_nibble6_sum>1)
finish_test("sctag", "tso_mon: L2 IC DIR multiple hits ", 2);
if(sctag2_ic_cam_hit_c6_nibble7_sum>1)
finish_test("sctag", "tso_mon: L2 IC DIR multiple hits ", 2);
if(sctag2_ic_cam_hit_c6_nibble16_sum>1)
finish_test("sctag", "tso_mon: L2 IC DIR multiple hits ", 2);
if(sctag2_ic_cam_hit_c6_nibble17_sum>1)
finish_test("sctag", "tso_mon: L2 IC DIR multiple hits ", 2);
if(sctag2_ic_cam_hit_c6_nibble18_sum>1)
finish_test("sctag", "tso_mon: L2 IC DIR multiple hits ", 2);
if(sctag2_ic_cam_hit_c6_nibble19_sum>1)
finish_test("sctag", "tso_mon: L2 IC DIR multiple hits ", 2);
if(sctag2_ic_cam_hit_c6_nibble20_sum>1)
finish_test("sctag", "tso_mon: L2 IC DIR multiple hits ", 2);
if(sctag2_ic_cam_hit_c6_nibble21_sum>1)
finish_test("sctag", "tso_mon: L2 IC DIR multiple hits ", 2);
if(sctag2_ic_cam_hit_c6_nibble22_sum>1)
finish_test("sctag", "tso_mon: L2 IC DIR multiple hits ", 2);
if(sctag2_ic_cam_hit_c6_nibble23_sum>1)
finish_test("sctag", "tso_mon: L2 IC DIR multiple hits ", 2);
end
if(sctag2_dc_lkup_c6)
begin
if(sctag2_dc_cam_hit_c6_nibble0_sum>1)
finish_test("sctag", "tso_mon: L2 DC DIR multiple hits ", 2);
if(sctag2_dc_cam_hit_c6_nibble1_sum>1)
finish_test("sctag", "tso_mon: L2 DC DIR multiple hits ", 2);
if(sctag2_dc_cam_hit_c6_nibble2_sum>1)
finish_test("sctag", "tso_mon: L2 DC DIR multiple hits ", 2);
if(sctag2_dc_cam_hit_c6_nibble3_sum>1)
finish_test("sctag", "tso_mon: L2 DC DIR multiple hits ", 2);
if(sctag2_dc_cam_hit_c6_nibble4_sum>1)
finish_test("sctag", "tso_mon: L2 DC DIR multiple hits ", 2);
if(sctag2_dc_cam_hit_c6_nibble5_sum>1)
finish_test("sctag", "tso_mon: L2 DC DIR multiple hits ", 2);
if(sctag2_dc_cam_hit_c6_nibble6_sum>1)
finish_test("sctag", "tso_mon: L2 DC DIR multiple hits ", 2);
if(sctag2_dc_cam_hit_c6_nibble7_sum>1)
finish_test("sctag", "tso_mon: L2 DC DIR multiple hits ", 2);
if(sctag2_dc_cam_hit_c6_nibble8_sum>1)
finish_test("sctag", "tso_mon: L2 DC DIR multiple hits ", 2);
if(sctag2_dc_cam_hit_c6_nibble9_sum>1)
finish_test("sctag", "tso_mon: L2 DC DIR multiple hits ", 2);
if(sctag2_dc_cam_hit_c6_nibble10_sum>1)
finish_test("sctag", "tso_mon: L2 DC DIR multiple hits ", 2);
if(sctag2_dc_cam_hit_c6_nibble11_sum>1)
finish_test("sctag", "tso_mon: L2 DC DIR multiple hits ", 2);
if(sctag2_dc_cam_hit_c6_nibble12_sum>1)
finish_test("sctag", "tso_mon: L2 DC DIR multiple hits ", 2);
if(sctag2_dc_cam_hit_c6_nibble13_sum>1)
finish_test("sctag", "tso_mon: L2 DC DIR multiple hits ", 2);
if(sctag2_dc_cam_hit_c6_nibble14_sum>1)
finish_test("sctag", "tso_mon: L2 DC DIR multiple hits ", 2);
if(sctag2_dc_cam_hit_c6_nibble15_sum>1)
finish_test("sctag", "tso_mon: L2 DC DIR multiple hits ", 2);
if(sctag2_dc_cam_hit_c6_nibble16_sum>1)
finish_test("sctag", "tso_mon: L2 DC DIR multiple hits ", 2);
if(sctag2_dc_cam_hit_c6_nibble17_sum>1)
finish_test("sctag", "tso_mon: L2 DC DIR multiple hits ", 2);
if(sctag2_dc_cam_hit_c6_nibble18_sum>1)
finish_test("sctag", "tso_mon: L2 DC DIR multiple hits ", 2);
if(sctag2_dc_cam_hit_c6_nibble19_sum>1)
finish_test("sctag", "tso_mon: L2 DC DIR multiple hits ", 2);
if(sctag2_dc_cam_hit_c6_nibble20_sum>1)
finish_test("sctag", "tso_mon: L2 DC DIR multiple hits ", 2);
if(sctag2_dc_cam_hit_c6_nibble21_sum>1)
finish_test("sctag", "tso_mon: L2 DC DIR multiple hits ", 2);
if(sctag2_dc_cam_hit_c6_nibble22_sum>1)
finish_test("sctag", "tso_mon: L2 DC DIR multiple hits ", 2);
if(sctag2_dc_cam_hit_c6_nibble23_sum>1)
finish_test("sctag", "tso_mon: L2 DC DIR multiple hits ", 2);
if(sctag2_dc_cam_hit_c6_nibble24_sum>1)
finish_test("sctag", "tso_mon: L2 DC DIR multiple hits ", 2);
if(sctag2_dc_cam_hit_c6_nibble25_sum>1)
finish_test("sctag", "tso_mon: L2 DC DIR multiple hits ", 2);
if(sctag2_dc_cam_hit_c6_nibble26_sum>1)
finish_test("sctag", "tso_mon: L2 DC DIR multiple hits ", 2);
if(sctag2_dc_cam_hit_c6_nibble27_sum>1)
finish_test("sctag", "tso_mon: L2 DC DIR multiple hits ", 2);
if(sctag2_dc_cam_hit_c6_nibble28_sum>1)
finish_test("sctag", "tso_mon: L2 DC DIR multiple hits ", 2);
if(sctag2_dc_cam_hit_c6_nibble29_sum>1)
finish_test("sctag", "tso_mon: L2 DC DIR multiple hits ", 2);
if(sctag2_dc_cam_hit_c6_nibble30_sum>1)
finish_test("sctag", "tso_mon: L2 DC DIR multiple hits ", 2);
if(sctag2_dc_cam_hit_c6_nibble31_sum>1)
finish_test("sctag", "tso_mon: L2 DC DIR multiple hits ", 2);
end
if(sctag2_ic_lkup_c6 & sctag2_dc_lkup_c6)
begin
if(sctag2_both_cam_hit_c6_nibble0_sum>1)
finish_test("sctag", "tso_mon: L2 ICDC DIR multiple hits ", 2);
if(sctag2_both_cam_hit_c6_nibble1_sum>1)
finish_test("sctag", "tso_mon: L2 ICDC DIR multiple hits ", 2);
if(sctag2_both_cam_hit_c6_nibble2_sum>1)
finish_test("sctag", "tso_mon: L2 ICDC DIR multiple hits ", 2);
if(sctag2_both_cam_hit_c6_nibble3_sum>1)
finish_test("sctag", "tso_mon: L2 ICDC DIR multiple hits ", 2);
if(sctag2_both_cam_hit_c6_nibble4_sum>1)
finish_test("sctag", "tso_mon: L2 ICDC DIR multiple hits ", 2);
if(sctag2_both_cam_hit_c6_nibble5_sum>1)
finish_test("sctag", "tso_mon: L2 ICDC DIR multiple hits ", 2);
if(sctag2_both_cam_hit_c6_nibble6_sum>1)
finish_test("sctag", "tso_mon: L2 ICDC DIR multiple hits ", 2);
if(sctag2_both_cam_hit_c6_nibble7_sum>1)
finish_test("sctag", "tso_mon: L2 ICDC DIR multiple hits ", 2);
if(sctag2_both_cam_hit_c6_nibble16_sum>1)
finish_test("sctag", "tso_mon: L2 ICDC DIR multiple hits ", 2);
if(sctag2_both_cam_hit_c6_nibble17_sum>1)
finish_test("sctag", "tso_mon: L2 ICDC DIR multiple hits ", 2);
if(sctag2_both_cam_hit_c6_nibble18_sum>1)
finish_test("sctag", "tso_mon: L2 ICDC DIR multiple hits ", 2);
if(sctag2_both_cam_hit_c6_nibble19_sum>1)
finish_test("sctag", "tso_mon: L2 ICDC DIR multiple hits ", 2);
if(sctag2_both_cam_hit_c6_nibble20_sum>1)
finish_test("sctag", "tso_mon: L2 ICDC DIR multiple hits ", 2);
if(sctag2_both_cam_hit_c6_nibble21_sum>1)
finish_test("sctag", "tso_mon: L2 ICDC DIR multiple hits ", 2);
if(sctag2_both_cam_hit_c6_nibble22_sum>1)
finish_test("sctag", "tso_mon: L2 ICDC DIR multiple hits ", 2);
if(sctag2_both_cam_hit_c6_nibble23_sum>1)
finish_test("sctag", "tso_mon: L2 ICDC DIR multiple hits ", 2);
end
get_sctag_cpx(sctag3_cpx_type, sctag3_cpx_type_str, sctag3_cpx_req_cq_d1, sctag3_cpx_data_ca, 3'h3);
sctag3_valid_spcs =
sctag3_cpx_req_cq_d1[0] + sctag3_cpx_req_cq_d1[1] + sctag3_cpx_req_cq_d1[2] +
sctag3_cpx_req_cq_d1[3] + sctag3_cpx_req_cq_d1[4] + sctag3_cpx_req_cq_d1[5] +
sctag3_cpx_req_cq_d1[6] + sctag3_cpx_req_cq_d1[7];
if((sctag3_valid_spcs > 0) &
((sctag3_cpx_type == `ST_ACK) | (sctag3_cpx_type == `STRST_ACK) | (sctag3_cpx_type == `EVICT_REQ)))
begin
cpx3_inv_fanout = sctag3_valid_spcs;
if(tso_mon_msg) $display("%0d tso_mon: sctag3 invalidation to multiple cores %d", $time, cpx3_inv_fanout);
end
else
begin
cpx3_inv_fanout = 4'h0;
end
sctag3_dc_lkup_c5 <= |sctag3_dc_lkup_panel_dec_c4 & |sctag3_dc_lkup_row_dec_c4;
sctag3_ic_lkup_c5 <= |sctag3_ic_lkup_panel_dec_c4 & |sctag3_ic_lkup_row_dec_c4;
sctag3_dc_lkup_c6 <= sctag3_dc_lkup_c5;
sctag3_ic_lkup_c6 <= sctag3_ic_lkup_c5;
// THESE ARE ACTUALLY CHECKERS - THEY ARE IMPORTANT - CAUGHT A FEW BUGS
//----------------------------------------------------------------------
if(sctag3_ic_lkup_c6)
begin
if(sctag3_ic_cam_hit_c6_nibble0_sum>1)
finish_test("sctag", "tso_mon: L2 IC DIR multiple hits ", 3);
if(sctag3_ic_cam_hit_c6_nibble1_sum>1)
finish_test("sctag", "tso_mon: L2 IC DIR multiple hits ", 3);
if(sctag3_ic_cam_hit_c6_nibble2_sum>1)
finish_test("sctag", "tso_mon: L2 IC DIR multiple hits ", 3);
if(sctag3_ic_cam_hit_c6_nibble3_sum>1)
finish_test("sctag", "tso_mon: L2 IC DIR multiple hits ", 3);
if(sctag3_ic_cam_hit_c6_nibble4_sum>1)
finish_test("sctag", "tso_mon: L2 IC DIR multiple hits ", 3);
if(sctag3_ic_cam_hit_c6_nibble5_sum>1)
finish_test("sctag", "tso_mon: L2 IC DIR multiple hits ", 3);
if(sctag3_ic_cam_hit_c6_nibble6_sum>1)
finish_test("sctag", "tso_mon: L2 IC DIR multiple hits ", 3);
if(sctag3_ic_cam_hit_c6_nibble7_sum>1)
finish_test("sctag", "tso_mon: L2 IC DIR multiple hits ", 3);
if(sctag3_ic_cam_hit_c6_nibble16_sum>1)
finish_test("sctag", "tso_mon: L2 IC DIR multiple hits ", 3);
if(sctag3_ic_cam_hit_c6_nibble17_sum>1)
finish_test("sctag", "tso_mon: L2 IC DIR multiple hits ", 3);
if(sctag3_ic_cam_hit_c6_nibble18_sum>1)
finish_test("sctag", "tso_mon: L2 IC DIR multiple hits ", 3);
if(sctag3_ic_cam_hit_c6_nibble19_sum>1)
finish_test("sctag", "tso_mon: L2 IC DIR multiple hits ", 3);
if(sctag3_ic_cam_hit_c6_nibble20_sum>1)
finish_test("sctag", "tso_mon: L2 IC DIR multiple hits ", 3);
if(sctag3_ic_cam_hit_c6_nibble21_sum>1)
finish_test("sctag", "tso_mon: L2 IC DIR multiple hits ", 3);
if(sctag3_ic_cam_hit_c6_nibble22_sum>1)
finish_test("sctag", "tso_mon: L2 IC DIR multiple hits ", 3);
if(sctag3_ic_cam_hit_c6_nibble23_sum>1)
finish_test("sctag", "tso_mon: L2 IC DIR multiple hits ", 3);
end
if(sctag3_dc_lkup_c6)
begin
if(sctag3_dc_cam_hit_c6_nibble0_sum>1)
finish_test("sctag", "tso_mon: L2 DC DIR multiple hits ", 3);
if(sctag3_dc_cam_hit_c6_nibble1_sum>1)
finish_test("sctag", "tso_mon: L2 DC DIR multiple hits ", 3);
if(sctag3_dc_cam_hit_c6_nibble2_sum>1)
finish_test("sctag", "tso_mon: L2 DC DIR multiple hits ", 3);
if(sctag3_dc_cam_hit_c6_nibble3_sum>1)
finish_test("sctag", "tso_mon: L2 DC DIR multiple hits ", 3);
if(sctag3_dc_cam_hit_c6_nibble4_sum>1)
finish_test("sctag", "tso_mon: L2 DC DIR multiple hits ", 3);
if(sctag3_dc_cam_hit_c6_nibble5_sum>1)
finish_test("sctag", "tso_mon: L2 DC DIR multiple hits ", 3);
if(sctag3_dc_cam_hit_c6_nibble6_sum>1)
finish_test("sctag", "tso_mon: L2 DC DIR multiple hits ", 3);
if(sctag3_dc_cam_hit_c6_nibble7_sum>1)
finish_test("sctag", "tso_mon: L2 DC DIR multiple hits ", 3);
if(sctag3_dc_cam_hit_c6_nibble8_sum>1)
finish_test("sctag", "tso_mon: L2 DC DIR multiple hits ", 3);
if(sctag3_dc_cam_hit_c6_nibble9_sum>1)
finish_test("sctag", "tso_mon: L2 DC DIR multiple hits ", 3);
if(sctag3_dc_cam_hit_c6_nibble10_sum>1)
finish_test("sctag", "tso_mon: L2 DC DIR multiple hits ", 3);
if(sctag3_dc_cam_hit_c6_nibble11_sum>1)
finish_test("sctag", "tso_mon: L2 DC DIR multiple hits ", 3);
if(sctag3_dc_cam_hit_c6_nibble12_sum>1)
finish_test("sctag", "tso_mon: L2 DC DIR multiple hits ", 3);
if(sctag3_dc_cam_hit_c6_nibble13_sum>1)
finish_test("sctag", "tso_mon: L2 DC DIR multiple hits ", 3);
if(sctag3_dc_cam_hit_c6_nibble14_sum>1)
finish_test("sctag", "tso_mon: L2 DC DIR multiple hits ", 3);
if(sctag3_dc_cam_hit_c6_nibble15_sum>1)
finish_test("sctag", "tso_mon: L2 DC DIR multiple hits ", 3);
if(sctag3_dc_cam_hit_c6_nibble16_sum>1)
finish_test("sctag", "tso_mon: L2 DC DIR multiple hits ", 3);
if(sctag3_dc_cam_hit_c6_nibble17_sum>1)
finish_test("sctag", "tso_mon: L2 DC DIR multiple hits ", 3);
if(sctag3_dc_cam_hit_c6_nibble18_sum>1)
finish_test("sctag", "tso_mon: L2 DC DIR multiple hits ", 3);
if(sctag3_dc_cam_hit_c6_nibble19_sum>1)
finish_test("sctag", "tso_mon: L2 DC DIR multiple hits ", 3);
if(sctag3_dc_cam_hit_c6_nibble20_sum>1)
finish_test("sctag", "tso_mon: L2 DC DIR multiple hits ", 3);
if(sctag3_dc_cam_hit_c6_nibble21_sum>1)
finish_test("sctag", "tso_mon: L2 DC DIR multiple hits ", 3);
if(sctag3_dc_cam_hit_c6_nibble22_sum>1)
finish_test("sctag", "tso_mon: L2 DC DIR multiple hits ", 3);
if(sctag3_dc_cam_hit_c6_nibble23_sum>1)
finish_test("sctag", "tso_mon: L2 DC DIR multiple hits ", 3);
if(sctag3_dc_cam_hit_c6_nibble24_sum>1)
finish_test("sctag", "tso_mon: L2 DC DIR multiple hits ", 3);
if(sctag3_dc_cam_hit_c6_nibble25_sum>1)
finish_test("sctag", "tso_mon: L2 DC DIR multiple hits ", 3);
if(sctag3_dc_cam_hit_c6_nibble26_sum>1)
finish_test("sctag", "tso_mon: L2 DC DIR multiple hits ", 3);
if(sctag3_dc_cam_hit_c6_nibble27_sum>1)
finish_test("sctag", "tso_mon: L2 DC DIR multiple hits ", 3);
if(sctag3_dc_cam_hit_c6_nibble28_sum>1)
finish_test("sctag", "tso_mon: L2 DC DIR multiple hits ", 3);
if(sctag3_dc_cam_hit_c6_nibble29_sum>1)
finish_test("sctag", "tso_mon: L2 DC DIR multiple hits ", 3);
if(sctag3_dc_cam_hit_c6_nibble30_sum>1)
finish_test("sctag", "tso_mon: L2 DC DIR multiple hits ", 3);
if(sctag3_dc_cam_hit_c6_nibble31_sum>1)
finish_test("sctag", "tso_mon: L2 DC DIR multiple hits ", 3);
end
if(sctag3_ic_lkup_c6 & sctag3_dc_lkup_c6)
begin
if(sctag3_both_cam_hit_c6_nibble0_sum>1)
finish_test("sctag", "tso_mon: L2 ICDC DIR multiple hits ", 3);
if(sctag3_both_cam_hit_c6_nibble1_sum>1)
finish_test("sctag", "tso_mon: L2 ICDC DIR multiple hits ", 3);
if(sctag3_both_cam_hit_c6_nibble2_sum>1)
finish_test("sctag", "tso_mon: L2 ICDC DIR multiple hits ", 3);
if(sctag3_both_cam_hit_c6_nibble3_sum>1)
finish_test("sctag", "tso_mon: L2 ICDC DIR multiple hits ", 3);
if(sctag3_both_cam_hit_c6_nibble4_sum>1)
finish_test("sctag", "tso_mon: L2 ICDC DIR multiple hits ", 3);
if(sctag3_both_cam_hit_c6_nibble5_sum>1)
finish_test("sctag", "tso_mon: L2 ICDC DIR multiple hits ", 3);
if(sctag3_both_cam_hit_c6_nibble6_sum>1)
finish_test("sctag", "tso_mon: L2 ICDC DIR multiple hits ", 3);
if(sctag3_both_cam_hit_c6_nibble7_sum>1)
finish_test("sctag", "tso_mon: L2 ICDC DIR multiple hits ", 3);
if(sctag3_both_cam_hit_c6_nibble16_sum>1)
finish_test("sctag", "tso_mon: L2 ICDC DIR multiple hits ", 3);
if(sctag3_both_cam_hit_c6_nibble17_sum>1)
finish_test("sctag", "tso_mon: L2 ICDC DIR multiple hits ", 3);
if(sctag3_both_cam_hit_c6_nibble18_sum>1)
finish_test("sctag", "tso_mon: L2 ICDC DIR multiple hits ", 3);
if(sctag3_both_cam_hit_c6_nibble19_sum>1)
finish_test("sctag", "tso_mon: L2 ICDC DIR multiple hits ", 3);
if(sctag3_both_cam_hit_c6_nibble20_sum>1)
finish_test("sctag", "tso_mon: L2 ICDC DIR multiple hits ", 3);
if(sctag3_both_cam_hit_c6_nibble21_sum>1)
finish_test("sctag", "tso_mon: L2 ICDC DIR multiple hits ", 3);
if(sctag3_both_cam_hit_c6_nibble22_sum>1)
finish_test("sctag", "tso_mon: L2 ICDC DIR multiple hits ", 3);
if(sctag3_both_cam_hit_c6_nibble23_sum>1)
finish_test("sctag", "tso_mon: L2 ICDC DIR multiple hits ", 3);
end
end // of if(rst_l)
else
begin
sctag0_dc_lkup_c5 <= 1'b0;
sctag0_ic_lkup_c5 <= 1'b0;
sctag0_dc_lkup_c6 <= 1'b0;
sctag0_ic_lkup_c6 <= 1'b0;
sctag1_dc_lkup_c5 <= 1'b0;
sctag1_ic_lkup_c5 <= 1'b0;
sctag1_dc_lkup_c6 <= 1'b0;
sctag1_ic_lkup_c6 <= 1'b0;
sctag2_dc_lkup_c5 <= 1'b0;
sctag2_ic_lkup_c5 <= 1'b0;
sctag2_dc_lkup_c6 <= 1'b0;
sctag2_ic_lkup_c6 <= 1'b0;
sctag3_dc_lkup_c5 <= 1'b0;
sctag3_ic_lkup_c5 <= 1'b0;
sctag3_dc_lkup_c6 <= 1'b0;
sctag3_ic_lkup_c6 <= 1'b0;
end // of else
end // of always
always @(negedge clk)
begin
if(rst_l)
begin
if(cpx0_inv_fanout && cpx1_inv_fanout)
begin
multiple_inv01 = 1'b1;
if((cpx0_inv_fanout>1) && (cpx1_inv_fanout > 1))
multiple_inv01_multiple_fanout = 1'b1;
end
else
begin
multiple_inv01 = 1'b0;
multiple_inv01_multiple_fanout = 1'b0;
end
if(cpx0_inv_fanout && cpx1_inv_fanout && cpx2_inv_fanout && cpx3_inv_fanout)
begin
multiple_inv0123 = 1'b1;
if((cpx0_inv_fanout>1) && (cpx1_inv_fanout>1) && (cpx2_inv_fanout>1) && (cpx3_inv_fanout>1))
multiple_inv0123_multiple_fanout = 1'b1;
end
else
begin
multiple_inv0123 = 1'b0;
multiple_inv0123_multiple_fanout = 1'b0;
end
end // of if(rst_l)
end // of always
//----------------------------------------------------------------------------------------
// This section deals with the cpx to spc packets
//----------------------------------------------------------------------------------------
always @(posedge clk)
begin
if(cpx_spc0_data_vld & (cpx_spc0_type == `LOAD_RET) & cpx_spc0_data_cx2[129])
begin
atomic_ret0 <= 1'b1;
if(tso_mon_msg) $display("tso_mon: atomic_ret0 = 1");
end
else if(cpx_spc0_data_vld & (cpx_spc0_type == `ST_ACK) & cpx_spc0_data_cx2[129])
begin
atomic_ret0 <= 1'b0;
if(tso_mon_msg) $display("tso_mon: atomic_ret0 = 0");
end
if(atomic_ret0 & cpx_spc0_data_vld & ~(cpx_spc0_type == `ST_ACK))
begin
non_b2b_atomic_ret0 <= 1'b1;
if(tso_mon_msg) $display("tso_mon: non_b2b_atomic_ret0");
end
else
non_b2b_atomic_ret0 <= 1'b0;
if(cpx_spc1_data_vld & (cpx_spc1_type == `LOAD_RET) & cpx_spc1_data_cx2[129])
begin
atomic_ret1 <= 1'b1;
if(tso_mon_msg) $display("tso_mon: atomic_ret1 = 1");
end
else if(cpx_spc1_data_vld & (cpx_spc1_type == `ST_ACK) & cpx_spc1_data_cx2[129])
begin
atomic_ret1 <= 1'b0;
if(tso_mon_msg) $display("tso_mon: atomic_ret1 = 0");
end
if(atomic_ret1 & cpx_spc1_data_vld & ~(cpx_spc1_type == `ST_ACK))
begin
non_b2b_atomic_ret1 <= 1'b1;
if(tso_mon_msg) $display("tso_mon: non_b2b_atomic_ret0");
end
else
non_b2b_atomic_ret1 <= 1'b0;
if(cpx_spc2_data_vld & (cpx_spc2_type == `LOAD_RET) & cpx_spc2_data_cx2[129])
begin
atomic_ret2 <= 1'b1;
if(tso_mon_msg) $display("tso_mon: atomic_ret2 = 1");
end
else if(cpx_spc2_data_vld & (cpx_spc2_type == `ST_ACK) & cpx_spc2_data_cx2[129])
begin
atomic_ret2 <= 1'b0;
if(tso_mon_msg) $display("tso_mon: atomic_ret2 = 0");
end
if(atomic_ret2 & cpx_spc2_data_vld & ~(cpx_spc2_type == `ST_ACK))
begin
non_b2b_atomic_ret2 <= 1'b1;
if(tso_mon_msg) $display("tso_mon: non_b2b_atomic_ret0");
end
else
non_b2b_atomic_ret2 <= 1'b0;
if(cpx_spc3_data_vld & (cpx_spc3_type == `LOAD_RET) & cpx_spc3_data_cx2[129])
begin
atomic_ret3 <= 1'b1;
if(tso_mon_msg) $display("tso_mon: atomic_ret3 = 1");
end
else if(cpx_spc3_data_vld & (cpx_spc3_type == `ST_ACK) & cpx_spc3_data_cx2[129])
begin
atomic_ret3 <= 1'b0;
if(tso_mon_msg) $display("tso_mon: atomic_ret3 = 0");
end
if(atomic_ret3 & cpx_spc3_data_vld & ~(cpx_spc3_type == `ST_ACK))
begin
non_b2b_atomic_ret3 <= 1'b1;
if(tso_mon_msg) $display("tso_mon: non_b2b_atomic_ret0");
end
else
non_b2b_atomic_ret3 <= 1'b0;
if(cpx_spc4_data_vld & (cpx_spc4_type == `LOAD_RET) & cpx_spc4_data_cx2[129])
begin
atomic_ret4 <= 1'b1;
if(tso_mon_msg) $display("tso_mon: atomic_ret4 = 1");
end
else if(cpx_spc4_data_vld & (cpx_spc4_type == `ST_ACK) & cpx_spc4_data_cx2[129])
begin
atomic_ret4 <= 1'b0;
if(tso_mon_msg) $display("tso_mon: atomic_ret4 = 0");
end
if(atomic_ret4 & cpx_spc4_data_vld & ~(cpx_spc4_type == `ST_ACK))
begin
non_b2b_atomic_ret4 <= 1'b1;
if(tso_mon_msg) $display("tso_mon: non_b2b_atomic_ret0");
end
else
non_b2b_atomic_ret4 <= 1'b0;
if(cpx_spc5_data_vld & (cpx_spc5_type == `LOAD_RET) & cpx_spc5_data_cx2[129])
begin
atomic_ret5 <= 1'b1;
if(tso_mon_msg) $display("tso_mon: atomic_ret5 = 1");
end
else if(cpx_spc5_data_vld & (cpx_spc5_type == `ST_ACK) & cpx_spc5_data_cx2[129])
begin
atomic_ret5 <= 1'b0;
if(tso_mon_msg) $display("tso_mon: atomic_ret5 = 0");
end
if(atomic_ret5 & cpx_spc5_data_vld & ~(cpx_spc5_type == `ST_ACK))
begin
non_b2b_atomic_ret5 <= 1'b1;
if(tso_mon_msg) $display("tso_mon: non_b2b_atomic_ret0");
end
else
non_b2b_atomic_ret5 <= 1'b0;
if(cpx_spc6_data_vld & (cpx_spc6_type == `LOAD_RET) & cpx_spc6_data_cx2[129])
begin
atomic_ret6 <= 1'b1;
if(tso_mon_msg) $display("tso_mon: atomic_ret6 = 1");
end
else if(cpx_spc6_data_vld & (cpx_spc6_type == `ST_ACK) & cpx_spc6_data_cx2[129])
begin
atomic_ret6 <= 1'b0;
if(tso_mon_msg) $display("tso_mon: atomic_ret6 = 0");
end
if(atomic_ret6 & cpx_spc6_data_vld & ~(cpx_spc6_type == `ST_ACK))
begin
non_b2b_atomic_ret6 <= 1'b1;
if(tso_mon_msg) $display("tso_mon: non_b2b_atomic_ret0");
end
else
non_b2b_atomic_ret6 <= 1'b0;
if(cpx_spc7_data_vld & (cpx_spc7_type == `LOAD_RET) & cpx_spc7_data_cx2[129])
begin
atomic_ret7 <= 1'b1;
if(tso_mon_msg) $display("tso_mon: atomic_ret7 = 1");
end
else if(cpx_spc7_data_vld & (cpx_spc7_type == `ST_ACK) & cpx_spc7_data_cx2[129])
begin
atomic_ret7 <= 1'b0;
if(tso_mon_msg) $display("tso_mon: atomic_ret7 = 0");
end
if(atomic_ret7 & cpx_spc7_data_vld & ~(cpx_spc7_type == `ST_ACK))
begin
non_b2b_atomic_ret7 <= 1'b1;
if(tso_mon_msg) $display("tso_mon: non_b2b_atomic_ret0");
end
else
non_b2b_atomic_ret7 <= 1'b0;
end
always @(negedge clk)
begin
if(rst_l)
begin
if(cpx_spc0_data_vld)
get_cpx_spc(cpx_spc0_type_str, cpx_spc0_type);
if(tso_mon_msg)
$display("%0d:Info cpx-to-spc%d packet TYPE= %s data= %x", $time, 0, cpx_spc0_type_str, cpx_spc0_data_cx2[127:0]);
if(cpx_spc1_data_vld)
get_cpx_spc(cpx_spc1_type_str, cpx_spc1_type);
if(tso_mon_msg)
$display("%0d:Info cpx-to-spc%d packet TYPE= %s data= %x", $time, 1, cpx_spc1_type_str, cpx_spc1_data_cx2[127:0]);
if(cpx_spc2_data_vld)
get_cpx_spc(cpx_spc2_type_str, cpx_spc2_type);
if(tso_mon_msg)
$display("%0d:Info cpx-to-spc%d packet TYPE= %s data= %x", $time, 2, cpx_spc2_type_str, cpx_spc2_data_cx2[127:0]);
if(cpx_spc3_data_vld)
get_cpx_spc(cpx_spc3_type_str, cpx_spc3_type);
if(tso_mon_msg)
$display("%0d:Info cpx-to-spc%d packet TYPE= %s data= %x", $time, 3, cpx_spc3_type_str, cpx_spc3_data_cx2[127:0]);
if(cpx_spc4_data_vld)
get_cpx_spc(cpx_spc4_type_str, cpx_spc4_type);
if(tso_mon_msg)
$display("%0d:Info cpx-to-spc%d packet TYPE= %s data= %x", $time, 4, cpx_spc4_type_str, cpx_spc4_data_cx2[127:0]);
if(cpx_spc5_data_vld)
get_cpx_spc(cpx_spc5_type_str, cpx_spc5_type);
if(tso_mon_msg)
$display("%0d:Info cpx-to-spc%d packet TYPE= %s data= %x", $time, 5, cpx_spc5_type_str, cpx_spc5_data_cx2[127:0]);
if(cpx_spc6_data_vld)
get_cpx_spc(cpx_spc6_type_str, cpx_spc6_type);
if(tso_mon_msg)
$display("%0d:Info cpx-to-spc%d packet TYPE= %s data= %x", $time, 6, cpx_spc6_type_str, cpx_spc6_data_cx2[127:0]);
if(cpx_spc7_data_vld)
get_cpx_spc(cpx_spc7_type_str, cpx_spc7_type);
if(tso_mon_msg)
$display("%0d:Info cpx-to-spc%d packet TYPE= %s data= %x", $time, 7, cpx_spc7_type_str, cpx_spc7_data_cx2[127:0]);
end // of rst_l
end
//==============================================================================
// L2 stuff
//==============================================================================
//==============================================================================
// This is stuff related to the L2 tags queues. Measure fullness and high-water mark
// The queus are - miss buffer, output q, input q, fill buffer, write back buffer
// rdma (write) q and snoop q.
//==============================================================================
wire [4:0] sctag0_mb_count = `TOP_MEMORY.sctag0.mbctl.mb_count_c4[4:0];
wire [4:0] sctag0_oq_count = `TOP_MEMORY.sctag0.oqctl.oq_count_p[4:0];
wire [4:0] sctag0_iq_count = `TOP_MEMORY.sctag0.iqctl.que_cnt[4:0];
wire [3:0] sctag0_fb_count = `TOP_MEMORY.sctag0.fbctl.fb_count[3:0];
wire [3:0] sctag0_wb_count = `TOP_MEMORY.sctag0.wbctl.wb_count[3:0];
wire [3:0] sctag0_rdma_valid = `TOP_MEMORY.sctag0.rdmatctl.rdma_valid[3:0];
wire [1:0] sctag0_snpq_valid = `TOP_MEMORY.sctag0.snpctl.snpq_valid[1:0];
wire sctag0_mb_full = (sctag0_mb_count == 5'd16);
wire sctag0_mb_hwm = (sctag0_mb_count >= 5'd12);
wire sctag0_oq_full = (sctag0_oq_count == 5'd16);
wire sctag0_oq_hwm = (sctag0_oq_count >= 5'd01);
wire sctag0_iq_full = (sctag0_iq_count == 5'd16);
wire sctag0_iq_hwm = (sctag0_iq_count >= 5'd11);
wire sctag0_fb_full = (sctag0_fb_count == 4'd8);
wire sctag0_fb_hwm = (sctag0_fb_count >= 4'd7);
wire sctag0_wb_full = (sctag0_wb_count == 4'd8);
wire sctag0_wb_hwm = (sctag0_wb_count >= 4'd1);
wire sctag0_rdma_full = (sctag0_rdma_valid == 4'b1111);
wire sctag0_snpq_full = (sctag0_snpq_valid == 2'b11);
wire [1:0] sctag0_mb_info = {sctag0_mb_full, sctag0_mb_hwm};
wire [1:0] sctag0_oq_info = {sctag0_oq_full, sctag0_oq_hwm};
wire [1:0] sctag0_iq_info = {sctag0_iq_full, sctag0_iq_hwm};
wire [1:0] sctag0_fb_info = {sctag0_fb_full, sctag0_fb_hwm};
wire [1:0] sctag0_wb_info = {sctag0_wb_full, sctag0_wb_hwm};
wire [4:0] sctag1_mb_count = `TOP_MEMORY.sctag1.mbctl.mb_count_c4[4:0];
wire [4:0] sctag1_oq_count = `TOP_MEMORY.sctag1.oqctl.oq_count_p[4:0];
wire [4:0] sctag1_iq_count = `TOP_MEMORY.sctag1.iqctl.que_cnt[4:0];
wire [3:0] sctag1_fb_count = `TOP_MEMORY.sctag1.fbctl.fb_count[3:0];
wire [3:0] sctag1_wb_count = `TOP_MEMORY.sctag1.wbctl.wb_count[3:0];
wire [3:0] sctag1_rdma_valid = `TOP_MEMORY.sctag1.rdmatctl.rdma_valid[3:0];
wire [1:0] sctag1_snpq_valid = `TOP_MEMORY.sctag1.snpctl.snpq_valid[1:0];
wire sctag1_mb_full = (sctag1_mb_count == 5'd16);
wire sctag1_mb_hwm = (sctag1_mb_count >= 5'd12);
wire sctag1_oq_full = (sctag1_oq_count == 5'd16);
wire sctag1_oq_hwm = (sctag1_oq_count >= 5'd01);
wire sctag1_iq_full = (sctag1_iq_count == 5'd16);
wire sctag1_iq_hwm = (sctag1_iq_count >= 5'd11);
wire sctag1_fb_full = (sctag1_fb_count == 4'd8);
wire sctag1_fb_hwm = (sctag1_fb_count >= 4'd7);
wire sctag1_wb_full = (sctag1_wb_count == 4'd8);
wire sctag1_wb_hwm = (sctag1_wb_count >= 4'd1);
wire sctag1_rdma_full = (sctag1_rdma_valid == 4'b1111);
wire sctag1_snpq_full = (sctag1_snpq_valid == 2'b11);
wire [1:0] sctag1_mb_info = {sctag1_mb_full, sctag1_mb_hwm};
wire [1:0] sctag1_oq_info = {sctag1_oq_full, sctag1_oq_hwm};
wire [1:0] sctag1_iq_info = {sctag1_iq_full, sctag1_iq_hwm};
wire [1:0] sctag1_fb_info = {sctag1_fb_full, sctag1_fb_hwm};
wire [1:0] sctag1_wb_info = {sctag1_wb_full, sctag1_wb_hwm};
wire [4:0] sctag2_mb_count = `TOP_MEMORY.sctag2.mbctl.mb_count_c4[4:0];
wire [4:0] sctag2_oq_count = `TOP_MEMORY.sctag2.oqctl.oq_count_p[4:0];
wire [4:0] sctag2_iq_count = `TOP_MEMORY.sctag2.iqctl.que_cnt[4:0];
wire [3:0] sctag2_fb_count = `TOP_MEMORY.sctag2.fbctl.fb_count[3:0];
wire [3:0] sctag2_wb_count = `TOP_MEMORY.sctag2.wbctl.wb_count[3:0];
wire [3:0] sctag2_rdma_valid = `TOP_MEMORY.sctag2.rdmatctl.rdma_valid[3:0];
wire [1:0] sctag2_snpq_valid = `TOP_MEMORY.sctag2.snpctl.snpq_valid[1:0];
wire sctag2_mb_full = (sctag2_mb_count == 5'd16);
wire sctag2_mb_hwm = (sctag2_mb_count >= 5'd12);
wire sctag2_oq_full = (sctag2_oq_count == 5'd16);
wire sctag2_oq_hwm = (sctag2_oq_count >= 5'd01);
wire sctag2_iq_full = (sctag2_iq_count == 5'd16);
wire sctag2_iq_hwm = (sctag2_iq_count >= 5'd11);
wire sctag2_fb_full = (sctag2_fb_count == 4'd8);
wire sctag2_fb_hwm = (sctag2_fb_count >= 4'd7);
wire sctag2_wb_full = (sctag2_wb_count == 4'd8);
wire sctag2_wb_hwm = (sctag2_wb_count >= 4'd1);
wire sctag2_rdma_full = (sctag2_rdma_valid == 4'b1111);
wire sctag2_snpq_full = (sctag2_snpq_valid == 2'b11);
wire [1:0] sctag2_mb_info = {sctag2_mb_full, sctag2_mb_hwm};
wire [1:0] sctag2_oq_info = {sctag2_oq_full, sctag2_oq_hwm};
wire [1:0] sctag2_iq_info = {sctag2_iq_full, sctag2_iq_hwm};
wire [1:0] sctag2_fb_info = {sctag2_fb_full, sctag2_fb_hwm};
wire [1:0] sctag2_wb_info = {sctag2_wb_full, sctag2_wb_hwm};
wire [4:0] sctag3_mb_count = `TOP_MEMORY.sctag3.mbctl.mb_count_c4[4:0];
wire [4:0] sctag3_oq_count = `TOP_MEMORY.sctag3.oqctl.oq_count_p[4:0];
wire [4:0] sctag3_iq_count = `TOP_MEMORY.sctag3.iqctl.que_cnt[4:0];
wire [3:0] sctag3_fb_count = `TOP_MEMORY.sctag3.fbctl.fb_count[3:0];
wire [3:0] sctag3_wb_count = `TOP_MEMORY.sctag3.wbctl.wb_count[3:0];
wire [3:0] sctag3_rdma_valid = `TOP_MEMORY.sctag3.rdmatctl.rdma_valid[3:0];
wire [1:0] sctag3_snpq_valid = `TOP_MEMORY.sctag3.snpctl.snpq_valid[1:0];
wire sctag3_mb_full = (sctag3_mb_count == 5'd16);
wire sctag3_mb_hwm = (sctag3_mb_count >= 5'd12);
wire sctag3_oq_full = (sctag3_oq_count == 5'd16);
wire sctag3_oq_hwm = (sctag3_oq_count >= 5'd01);
wire sctag3_iq_full = (sctag3_iq_count == 5'd16);
wire sctag3_iq_hwm = (sctag3_iq_count >= 5'd11);
wire sctag3_fb_full = (sctag3_fb_count == 4'd8);
wire sctag3_fb_hwm = (sctag3_fb_count >= 4'd7);
wire sctag3_wb_full = (sctag3_wb_count == 4'd8);
wire sctag3_wb_hwm = (sctag3_wb_count >= 4'd1);
wire sctag3_rdma_full = (sctag3_rdma_valid == 4'b1111);
wire sctag3_snpq_full = (sctag3_snpq_valid == 2'b11);
wire [1:0] sctag3_mb_info = {sctag3_mb_full, sctag3_mb_hwm};
wire [1:0] sctag3_oq_info = {sctag3_oq_full, sctag3_oq_hwm};
wire [1:0] sctag3_iq_info = {sctag3_iq_full, sctag3_iq_hwm};
wire [1:0] sctag3_fb_info = {sctag3_fb_full, sctag3_fb_hwm};
wire [1:0] sctag3_wb_info = {sctag3_wb_full, sctag3_wb_hwm};
//==============================================================================
// L2 Miss buffer linked list stuff
// valid, young, next link, type
//==============================================================================
wire [15:0] sctag0_mb_valid = `TOP_MEMORY.sctag0.mbctl.mb_valid[15:0];
wire [15:0] sctag0_mb_young = `TOP_MEMORY.sctag0.mbctl.mb_young[15:0];
//wire [3:0] sctag0_next_link_entry0 = `TOP_MEMORY.sctag0.mbctl.next_link_entry0[3:0];
//...
//wire [3:0] sctag0_next_link_entry15 = `TOP_MEMORY.sctag0.mbctl.next_link_entry15[3:0];
wire [155:0] sctag0_mb_data_array0 = `TOP_MEMORY.sctag0.mbdata.inq_ary[0];
wire [155:0] sctag0_mb_data_array1 = `TOP_MEMORY.sctag0.mbdata.inq_ary[1];
wire [155:0] sctag0_mb_data_array2 = `TOP_MEMORY.sctag0.mbdata.inq_ary[2];
wire [155:0] sctag0_mb_data_array3 = `TOP_MEMORY.sctag0.mbdata.inq_ary[3];
wire [155:0] sctag0_mb_data_array4 = `TOP_MEMORY.sctag0.mbdata.inq_ary[4];
wire [155:0] sctag0_mb_data_array5 = `TOP_MEMORY.sctag0.mbdata.inq_ary[5];
wire [155:0] sctag0_mb_data_array6 = `TOP_MEMORY.sctag0.mbdata.inq_ary[6];
wire [155:0] sctag0_mb_data_array7 = `TOP_MEMORY.sctag0.mbdata.inq_ary[7];
wire [155:0] sctag0_mb_data_array8 = `TOP_MEMORY.sctag0.mbdata.inq_ary[8];
wire [155:0] sctag0_mb_data_array9 = `TOP_MEMORY.sctag0.mbdata.inq_ary[9];
wire [155:0] sctag0_mb_data_array10 = `TOP_MEMORY.sctag0.mbdata.inq_ary[10];
wire [155:0] sctag0_mb_data_array11 = `TOP_MEMORY.sctag0.mbdata.inq_ary[11];
wire [155:0] sctag0_mb_data_array12 = `TOP_MEMORY.sctag0.mbdata.inq_ary[12];
wire [155:0] sctag0_mb_data_array13 = `TOP_MEMORY.sctag0.mbdata.inq_ary[13];
wire [155:0] sctag0_mb_data_array14 = `TOP_MEMORY.sctag0.mbdata.inq_ary[14];
wire [155:0] sctag0_mb_data_array15 = `TOP_MEMORY.sctag0.mbdata.inq_ary[15];
//-----------------------------------------------------------------------------------------------
// look at sctag.v for L2_RDMA_HI L2_RQTYP_HI L2_RQTYP_LO and L2_RSVD
// Based ont the equation: .mb_data_write_data({57'b0,mbdata_inst_tecc_c8...
//-----------------------------------------------------------------------------------------------
wire [5:0] sctag0_mb_type0 = {sctag0_mb_data_array0 [77], sctag0_mb_data_array0 [83:79]};
wire [5:0] sctag0_mb_type1 = {sctag0_mb_data_array1 [77], sctag0_mb_data_array1 [83:79]};
wire [5:0] sctag0_mb_type2 = {sctag0_mb_data_array2 [77], sctag0_mb_data_array2 [83:79]};
wire [5:0] sctag0_mb_type3 = {sctag0_mb_data_array3 [77], sctag0_mb_data_array3 [83:79]};
wire [5:0] sctag0_mb_type4 = {sctag0_mb_data_array4 [77], sctag0_mb_data_array4 [83:79]};
wire [5:0] sctag0_mb_type5 = {sctag0_mb_data_array5 [77], sctag0_mb_data_array5 [83:79]};
wire [5:0] sctag0_mb_type6 = {sctag0_mb_data_array6 [77], sctag0_mb_data_array6 [83:79]};
wire [5:0] sctag0_mb_type7 = {sctag0_mb_data_array7 [77], sctag0_mb_data_array7 [83:79]};
wire [5:0] sctag0_mb_type8 = {sctag0_mb_data_array8 [77], sctag0_mb_data_array8 [83:79]};
wire [5:0] sctag0_mb_type9 = {sctag0_mb_data_array9 [77], sctag0_mb_data_array9 [83:79]};
wire [5:0] sctag0_mb_type10 = {sctag0_mb_data_array10[77], sctag0_mb_data_array10[83:79]};
wire [5:0] sctag0_mb_type11 = {sctag0_mb_data_array11[77], sctag0_mb_data_array11[83:79]};
wire [5:0] sctag0_mb_type12 = {sctag0_mb_data_array12[77], sctag0_mb_data_array12[83:79]};
wire [5:0] sctag0_mb_type13 = {sctag0_mb_data_array13[77], sctag0_mb_data_array13[83:79]};
wire [5:0] sctag0_mb_type14 = {sctag0_mb_data_array14[77], sctag0_mb_data_array14[83:79]};
wire [5:0] sctag0_mb_type15 = {sctag0_mb_data_array15[77], sctag0_mb_data_array15[83:79]};
//--------------------------------------------------------------
// Start figuring out what the entries are.
// bit 5 says if this is a DMA type or normal type
//--------------------------------------------------------------
wire sctag0_mb0_st_ny = sctag0_mb_valid[0] & ~sctag0_mb_young[0] & ~sctag0_mb_type0[5] & (sctag0_mb_type0[4:0] == `STORE_RQ);
wire sctag0_mb0_ld_ny = sctag0_mb_valid[0] & ~sctag0_mb_young[0] & ~sctag0_mb_type0[5] & (sctag0_mb_type0[4:0] == `LOAD_RQ);
wire sctag0_mb0_wris8_ny = sctag0_mb_valid[0] & ~sctag0_mb_young[0] & sctag0_mb_type0[5] & sctag0_mb_type0[1];
wire sctag0_mb0_wris64_ny = sctag0_mb_valid[0] & ~sctag0_mb_young[0] & sctag0_mb_type0[5] & sctag0_mb_type0[2];
wire sctag0_mb0_st_y = sctag0_mb_valid[0] & sctag0_mb_young[0] & ~sctag0_mb_type0[5] & (sctag0_mb_type0[4:0] == `STORE_RQ);
wire sctag0_mb0_ld_y = sctag0_mb_valid[0] & sctag0_mb_young[0] & ~sctag0_mb_type0[5] & (sctag0_mb_type0[4:0] == `LOAD_RQ);
wire sctag0_mb0_wris8_y = sctag0_mb_valid[0] & sctag0_mb_young[0] & sctag0_mb_type0[5] & sctag0_mb_type0[1];
wire sctag0_mb0_wris64_y = sctag0_mb_valid[0] & sctag0_mb_young[0] & sctag0_mb_type0[5] & sctag0_mb_type0[2];
wire sctag0_mb1_st_ny = sctag0_mb_valid[1] & ~sctag0_mb_young[1] & ~sctag0_mb_type1[5] & (sctag0_mb_type1[4:0] == `STORE_RQ);
wire sctag0_mb1_ld_ny = sctag0_mb_valid[1] & ~sctag0_mb_young[1] & ~sctag0_mb_type1[5] & (sctag0_mb_type1[4:0] == `LOAD_RQ);
wire sctag0_mb1_wris8_ny = sctag0_mb_valid[1] & ~sctag0_mb_young[1] & sctag0_mb_type1[5] & sctag0_mb_type1[1];
wire sctag0_mb1_wris64_ny = sctag0_mb_valid[1] & ~sctag0_mb_young[1] & sctag0_mb_type1[5] & sctag0_mb_type1[2];
wire sctag0_mb1_st_y = sctag0_mb_valid[1] & sctag0_mb_young[1] & ~sctag0_mb_type1[5] & (sctag0_mb_type1[4:0] == `STORE_RQ);
wire sctag0_mb1_ld_y = sctag0_mb_valid[1] & sctag0_mb_young[1] & ~sctag0_mb_type1[5] & (sctag0_mb_type1[4:0] == `LOAD_RQ);
wire sctag0_mb1_wris8_y = sctag0_mb_valid[1] & sctag0_mb_young[1] & sctag0_mb_type1[5] & sctag0_mb_type1[1];
wire sctag0_mb1_wris64_y = sctag0_mb_valid[1] & sctag0_mb_young[1] & sctag0_mb_type1[5] & sctag0_mb_type1[2];
wire sctag0_mb2_st_ny = sctag0_mb_valid[2] & ~sctag0_mb_young[2] & ~sctag0_mb_type2[5] & (sctag0_mb_type2[4:0] == `STORE_RQ);
wire sctag0_mb2_ld_ny = sctag0_mb_valid[2] & ~sctag0_mb_young[2] & ~sctag0_mb_type2[5] & (sctag0_mb_type2[4:0] == `LOAD_RQ);
wire sctag0_mb2_wris8_ny = sctag0_mb_valid[2] & ~sctag0_mb_young[2] & sctag0_mb_type2[5] & sctag0_mb_type2[1];
wire sctag0_mb2_wris64_ny = sctag0_mb_valid[2] & ~sctag0_mb_young[2] & sctag0_mb_type2[5] & sctag0_mb_type2[2];
wire sctag0_mb2_st_y = sctag0_mb_valid[2] & sctag0_mb_young[2] & ~sctag0_mb_type2[5] & (sctag0_mb_type2[4:0] == `STORE_RQ);
wire sctag0_mb2_ld_y = sctag0_mb_valid[2] & sctag0_mb_young[2] & ~sctag0_mb_type2[5] & (sctag0_mb_type2[4:0] == `LOAD_RQ);
wire sctag0_mb2_wris8_y = sctag0_mb_valid[2] & sctag0_mb_young[2] & sctag0_mb_type2[5] & sctag0_mb_type2[1];
wire sctag0_mb2_wris64_y = sctag0_mb_valid[2] & sctag0_mb_young[2] & sctag0_mb_type2[5] & sctag0_mb_type2[2];
wire sctag0_mb3_st_ny = sctag0_mb_valid[3] & ~sctag0_mb_young[3] & ~sctag0_mb_type3[5] & (sctag0_mb_type3[4:0] == `STORE_RQ);
wire sctag0_mb3_ld_ny = sctag0_mb_valid[3] & ~sctag0_mb_young[3] & ~sctag0_mb_type3[5] & (sctag0_mb_type3[4:0] == `LOAD_RQ);
wire sctag0_mb3_wris8_ny = sctag0_mb_valid[3] & ~sctag0_mb_young[3] & sctag0_mb_type3[5] & sctag0_mb_type3[1];
wire sctag0_mb3_wris64_ny = sctag0_mb_valid[3] & ~sctag0_mb_young[3] & sctag0_mb_type3[5] & sctag0_mb_type3[2];
wire sctag0_mb3_st_y = sctag0_mb_valid[3] & sctag0_mb_young[3] & ~sctag0_mb_type3[5] & (sctag0_mb_type3[4:0] == `STORE_RQ);
wire sctag0_mb3_ld_y = sctag0_mb_valid[3] & sctag0_mb_young[3] & ~sctag0_mb_type3[5] & (sctag0_mb_type3[4:0] == `LOAD_RQ);
wire sctag0_mb3_wris8_y = sctag0_mb_valid[3] & sctag0_mb_young[3] & sctag0_mb_type3[5] & sctag0_mb_type3[1];
wire sctag0_mb3_wris64_y = sctag0_mb_valid[3] & sctag0_mb_young[3] & sctag0_mb_type3[5] & sctag0_mb_type3[2];
wire sctag0_mb4_st_ny = sctag0_mb_valid[4] & ~sctag0_mb_young[4] & ~sctag0_mb_type4[5] & (sctag0_mb_type4[4:0] == `STORE_RQ);
wire sctag0_mb4_ld_ny = sctag0_mb_valid[4] & ~sctag0_mb_young[4] & ~sctag0_mb_type4[5] & (sctag0_mb_type4[4:0] == `LOAD_RQ);
wire sctag0_mb4_wris8_ny = sctag0_mb_valid[4] & ~sctag0_mb_young[4] & sctag0_mb_type4[5] & sctag0_mb_type4[1];
wire sctag0_mb4_wris64_ny = sctag0_mb_valid[4] & ~sctag0_mb_young[4] & sctag0_mb_type4[5] & sctag0_mb_type4[2];
wire sctag0_mb4_st_y = sctag0_mb_valid[4] & sctag0_mb_young[4] & ~sctag0_mb_type4[5] & (sctag0_mb_type4[4:0] == `STORE_RQ);
wire sctag0_mb4_ld_y = sctag0_mb_valid[4] & sctag0_mb_young[4] & ~sctag0_mb_type4[5] & (sctag0_mb_type4[4:0] == `LOAD_RQ);
wire sctag0_mb4_wris8_y = sctag0_mb_valid[4] & sctag0_mb_young[4] & sctag0_mb_type4[5] & sctag0_mb_type4[1];
wire sctag0_mb4_wris64_y = sctag0_mb_valid[4] & sctag0_mb_young[4] & sctag0_mb_type4[5] & sctag0_mb_type4[2];
wire sctag0_mb5_st_ny = sctag0_mb_valid[5] & ~sctag0_mb_young[5] & ~sctag0_mb_type5[5] & (sctag0_mb_type5[4:0] == `STORE_RQ);
wire sctag0_mb5_ld_ny = sctag0_mb_valid[5] & ~sctag0_mb_young[5] & ~sctag0_mb_type5[5] & (sctag0_mb_type5[4:0] == `LOAD_RQ);
wire sctag0_mb5_wris8_ny = sctag0_mb_valid[5] & ~sctag0_mb_young[5] & sctag0_mb_type5[5] & sctag0_mb_type5[1];
wire sctag0_mb5_wris64_ny = sctag0_mb_valid[5] & ~sctag0_mb_young[5] & sctag0_mb_type5[5] & sctag0_mb_type5[2];
wire sctag0_mb5_st_y = sctag0_mb_valid[5] & sctag0_mb_young[5] & ~sctag0_mb_type5[5] & (sctag0_mb_type5[4:0] == `STORE_RQ);
wire sctag0_mb5_ld_y = sctag0_mb_valid[5] & sctag0_mb_young[5] & ~sctag0_mb_type5[5] & (sctag0_mb_type5[4:0] == `LOAD_RQ);
wire sctag0_mb5_wris8_y = sctag0_mb_valid[5] & sctag0_mb_young[5] & sctag0_mb_type5[5] & sctag0_mb_type5[1];
wire sctag0_mb5_wris64_y = sctag0_mb_valid[5] & sctag0_mb_young[5] & sctag0_mb_type5[5] & sctag0_mb_type5[2];
wire sctag0_mb6_st_ny = sctag0_mb_valid[6] & ~sctag0_mb_young[6] & ~sctag0_mb_type6[5] & (sctag0_mb_type6[4:0] == `STORE_RQ);
wire sctag0_mb6_ld_ny = sctag0_mb_valid[6] & ~sctag0_mb_young[6] & ~sctag0_mb_type6[5] & (sctag0_mb_type6[4:0] == `LOAD_RQ);
wire sctag0_mb6_wris8_ny = sctag0_mb_valid[6] & ~sctag0_mb_young[6] & sctag0_mb_type6[5] & sctag0_mb_type6[1];
wire sctag0_mb6_wris64_ny = sctag0_mb_valid[6] & ~sctag0_mb_young[6] & sctag0_mb_type6[5] & sctag0_mb_type6[2];
wire sctag0_mb6_st_y = sctag0_mb_valid[6] & sctag0_mb_young[6] & ~sctag0_mb_type6[5] & (sctag0_mb_type6[4:0] == `STORE_RQ);
wire sctag0_mb6_ld_y = sctag0_mb_valid[6] & sctag0_mb_young[6] & ~sctag0_mb_type6[5] & (sctag0_mb_type6[4:0] == `LOAD_RQ);
wire sctag0_mb6_wris8_y = sctag0_mb_valid[6] & sctag0_mb_young[6] & sctag0_mb_type6[5] & sctag0_mb_type6[1];
wire sctag0_mb6_wris64_y = sctag0_mb_valid[6] & sctag0_mb_young[6] & sctag0_mb_type6[5] & sctag0_mb_type6[2];
wire sctag0_mb7_st_ny = sctag0_mb_valid[7] & ~sctag0_mb_young[7] & ~sctag0_mb_type7[5] & (sctag0_mb_type7[4:0] == `STORE_RQ);
wire sctag0_mb7_ld_ny = sctag0_mb_valid[7] & ~sctag0_mb_young[7] & ~sctag0_mb_type7[5] & (sctag0_mb_type7[4:0] == `LOAD_RQ);
wire sctag0_mb7_wris8_ny = sctag0_mb_valid[7] & ~sctag0_mb_young[7] & sctag0_mb_type7[5] & sctag0_mb_type7[1];
wire sctag0_mb7_wris64_ny = sctag0_mb_valid[7] & ~sctag0_mb_young[7] & sctag0_mb_type7[5] & sctag0_mb_type7[2];
wire sctag0_mb7_st_y = sctag0_mb_valid[7] & sctag0_mb_young[7] & ~sctag0_mb_type7[5] & (sctag0_mb_type7[4:0] == `STORE_RQ);
wire sctag0_mb7_ld_y = sctag0_mb_valid[7] & sctag0_mb_young[7] & ~sctag0_mb_type7[5] & (sctag0_mb_type7[4:0] == `LOAD_RQ);
wire sctag0_mb7_wris8_y = sctag0_mb_valid[7] & sctag0_mb_young[7] & sctag0_mb_type7[5] & sctag0_mb_type7[1];
wire sctag0_mb7_wris64_y = sctag0_mb_valid[7] & sctag0_mb_young[7] & sctag0_mb_type7[5] & sctag0_mb_type7[2];
wire sctag0_mb8_st_ny = sctag0_mb_valid[8] & ~sctag0_mb_young[8] & ~sctag0_mb_type8[5] & (sctag0_mb_type8[4:0] == `STORE_RQ);
wire sctag0_mb8_ld_ny = sctag0_mb_valid[8] & ~sctag0_mb_young[8] & ~sctag0_mb_type8[5] & (sctag0_mb_type8[4:0] == `LOAD_RQ);
wire sctag0_mb8_wris8_ny = sctag0_mb_valid[8] & ~sctag0_mb_young[8] & sctag0_mb_type8[5] & sctag0_mb_type8[1];
wire sctag0_mb8_wris64_ny = sctag0_mb_valid[8] & ~sctag0_mb_young[8] & sctag0_mb_type8[5] & sctag0_mb_type8[2];
wire sctag0_mb8_st_y = sctag0_mb_valid[8] & sctag0_mb_young[8] & ~sctag0_mb_type8[5] & (sctag0_mb_type8[4:0] == `STORE_RQ);
wire sctag0_mb8_ld_y = sctag0_mb_valid[8] & sctag0_mb_young[8] & ~sctag0_mb_type8[5] & (sctag0_mb_type8[4:0] == `LOAD_RQ);
wire sctag0_mb8_wris8_y = sctag0_mb_valid[8] & sctag0_mb_young[8] & sctag0_mb_type8[5] & sctag0_mb_type8[1];
wire sctag0_mb8_wris64_y = sctag0_mb_valid[8] & sctag0_mb_young[8] & sctag0_mb_type8[5] & sctag0_mb_type8[2];
wire sctag0_mb9_st_ny = sctag0_mb_valid[9] & ~sctag0_mb_young[9] & ~sctag0_mb_type9[5] & (sctag0_mb_type9[4:0] == `STORE_RQ);
wire sctag0_mb9_ld_ny = sctag0_mb_valid[9] & ~sctag0_mb_young[9] & ~sctag0_mb_type9[5] & (sctag0_mb_type9[4:0] == `LOAD_RQ);
wire sctag0_mb9_wris8_ny = sctag0_mb_valid[9] & ~sctag0_mb_young[9] & sctag0_mb_type9[5] & sctag0_mb_type9[1];
wire sctag0_mb9_wris64_ny = sctag0_mb_valid[9] & ~sctag0_mb_young[9] & sctag0_mb_type9[5] & sctag0_mb_type9[2];
wire sctag0_mb9_st_y = sctag0_mb_valid[9] & sctag0_mb_young[9] & ~sctag0_mb_type9[5] & (sctag0_mb_type9[4:0] == `STORE_RQ);
wire sctag0_mb9_ld_y = sctag0_mb_valid[9] & sctag0_mb_young[9] & ~sctag0_mb_type9[5] & (sctag0_mb_type9[4:0] == `LOAD_RQ);
wire sctag0_mb9_wris8_y = sctag0_mb_valid[9] & sctag0_mb_young[9] & sctag0_mb_type9[5] & sctag0_mb_type9[1];
wire sctag0_mb9_wris64_y = sctag0_mb_valid[9] & sctag0_mb_young[9] & sctag0_mb_type9[5] & sctag0_mb_type9[2];
wire sctag0_mb10_st_ny = sctag0_mb_valid[10] & ~sctag0_mb_young[10] & ~sctag0_mb_type10[5] & (sctag0_mb_type10[4:0] == `STORE_RQ);
wire sctag0_mb10_ld_ny = sctag0_mb_valid[10] & ~sctag0_mb_young[10] & ~sctag0_mb_type10[5] & (sctag0_mb_type10[4:0] == `LOAD_RQ);
wire sctag0_mb10_wris8_ny = sctag0_mb_valid[10] & ~sctag0_mb_young[10] & sctag0_mb_type10[5] & sctag0_mb_type10[1];
wire sctag0_mb10_wris64_ny = sctag0_mb_valid[10] & ~sctag0_mb_young[10] & sctag0_mb_type10[5] & sctag0_mb_type10[2];
wire sctag0_mb10_st_y = sctag0_mb_valid[10] & sctag0_mb_young[10] & ~sctag0_mb_type10[5] & (sctag0_mb_type10[4:0] == `STORE_RQ);
wire sctag0_mb10_ld_y = sctag0_mb_valid[10] & sctag0_mb_young[10] & ~sctag0_mb_type10[5] & (sctag0_mb_type10[4:0] == `LOAD_RQ);
wire sctag0_mb10_wris8_y = sctag0_mb_valid[10] & sctag0_mb_young[10] & sctag0_mb_type10[5] & sctag0_mb_type10[1];
wire sctag0_mb10_wris64_y = sctag0_mb_valid[10] & sctag0_mb_young[10] & sctag0_mb_type10[5] & sctag0_mb_type10[2];
wire sctag0_mb11_st_ny = sctag0_mb_valid[11] & ~sctag0_mb_young[11] & ~sctag0_mb_type11[5] & (sctag0_mb_type11[4:0] == `STORE_RQ);
wire sctag0_mb11_ld_ny = sctag0_mb_valid[11] & ~sctag0_mb_young[11] & ~sctag0_mb_type11[5] & (sctag0_mb_type11[4:0] == `LOAD_RQ);
wire sctag0_mb11_wris8_ny = sctag0_mb_valid[11] & ~sctag0_mb_young[11] & sctag0_mb_type11[5] & sctag0_mb_type11[1];
wire sctag0_mb11_wris64_ny = sctag0_mb_valid[11] & ~sctag0_mb_young[11] & sctag0_mb_type11[5] & sctag0_mb_type11[2];
wire sctag0_mb11_st_y = sctag0_mb_valid[11] & sctag0_mb_young[11] & ~sctag0_mb_type11[5] & (sctag0_mb_type11[4:0] == `STORE_RQ);
wire sctag0_mb11_ld_y = sctag0_mb_valid[11] & sctag0_mb_young[11] & ~sctag0_mb_type11[5] & (sctag0_mb_type11[4:0] == `LOAD_RQ);
wire sctag0_mb11_wris8_y = sctag0_mb_valid[11] & sctag0_mb_young[11] & sctag0_mb_type11[5] & sctag0_mb_type11[1];
wire sctag0_mb11_wris64_y = sctag0_mb_valid[11] & sctag0_mb_young[11] & sctag0_mb_type11[5] & sctag0_mb_type11[2];
wire sctag0_mb12_st_ny = sctag0_mb_valid[12] & ~sctag0_mb_young[12] & ~sctag0_mb_type12[5] & (sctag0_mb_type12[4:0] == `STORE_RQ);
wire sctag0_mb12_ld_ny = sctag0_mb_valid[12] & ~sctag0_mb_young[12] & ~sctag0_mb_type12[5] & (sctag0_mb_type12[4:0] == `LOAD_RQ);
wire sctag0_mb12_wris8_ny = sctag0_mb_valid[12] & ~sctag0_mb_young[12] & sctag0_mb_type12[5] & sctag0_mb_type12[1];
wire sctag0_mb12_wris64_ny = sctag0_mb_valid[12] & ~sctag0_mb_young[12] & sctag0_mb_type12[5] & sctag0_mb_type12[2];
wire sctag0_mb12_st_y = sctag0_mb_valid[12] & sctag0_mb_young[12] & ~sctag0_mb_type12[5] & (sctag0_mb_type12[4:0] == `STORE_RQ);
wire sctag0_mb12_ld_y = sctag0_mb_valid[12] & sctag0_mb_young[12] & ~sctag0_mb_type12[5] & (sctag0_mb_type12[4:0] == `LOAD_RQ);
wire sctag0_mb12_wris8_y = sctag0_mb_valid[12] & sctag0_mb_young[12] & sctag0_mb_type12[5] & sctag0_mb_type12[1];
wire sctag0_mb12_wris64_y = sctag0_mb_valid[12] & sctag0_mb_young[12] & sctag0_mb_type12[5] & sctag0_mb_type12[2];
wire sctag0_mb13_st_ny = sctag0_mb_valid[13] & ~sctag0_mb_young[13] & ~sctag0_mb_type13[5] & (sctag0_mb_type13[4:0] == `STORE_RQ);
wire sctag0_mb13_ld_ny = sctag0_mb_valid[13] & ~sctag0_mb_young[13] & ~sctag0_mb_type13[5] & (sctag0_mb_type13[4:0] == `LOAD_RQ);
wire sctag0_mb13_wris8_ny = sctag0_mb_valid[13] & ~sctag0_mb_young[13] & sctag0_mb_type13[5] & sctag0_mb_type13[1];
wire sctag0_mb13_wris64_ny = sctag0_mb_valid[13] & ~sctag0_mb_young[13] & sctag0_mb_type13[5] & sctag0_mb_type13[2];
wire sctag0_mb13_st_y = sctag0_mb_valid[13] & sctag0_mb_young[13] & ~sctag0_mb_type13[5] & (sctag0_mb_type13[4:0] == `STORE_RQ);
wire sctag0_mb13_ld_y = sctag0_mb_valid[13] & sctag0_mb_young[13] & ~sctag0_mb_type13[5] & (sctag0_mb_type13[4:0] == `LOAD_RQ);
wire sctag0_mb13_wris8_y = sctag0_mb_valid[13] & sctag0_mb_young[13] & sctag0_mb_type13[5] & sctag0_mb_type13[1];
wire sctag0_mb13_wris64_y = sctag0_mb_valid[13] & sctag0_mb_young[13] & sctag0_mb_type13[5] & sctag0_mb_type13[2];
wire sctag0_mb14_st_ny = sctag0_mb_valid[14] & ~sctag0_mb_young[14] & ~sctag0_mb_type14[5] & (sctag0_mb_type14[4:0] == `STORE_RQ);
wire sctag0_mb14_ld_ny = sctag0_mb_valid[14] & ~sctag0_mb_young[14] & ~sctag0_mb_type14[5] & (sctag0_mb_type14[4:0] == `LOAD_RQ);
wire sctag0_mb14_wris8_ny = sctag0_mb_valid[14] & ~sctag0_mb_young[14] & sctag0_mb_type14[5] & sctag0_mb_type14[1];
wire sctag0_mb14_wris64_ny = sctag0_mb_valid[14] & ~sctag0_mb_young[14] & sctag0_mb_type14[5] & sctag0_mb_type14[2];
wire sctag0_mb14_st_y = sctag0_mb_valid[14] & sctag0_mb_young[14] & ~sctag0_mb_type14[5] & (sctag0_mb_type14[4:0] == `STORE_RQ);
wire sctag0_mb14_ld_y = sctag0_mb_valid[14] & sctag0_mb_young[14] & ~sctag0_mb_type14[5] & (sctag0_mb_type14[4:0] == `LOAD_RQ);
wire sctag0_mb14_wris8_y = sctag0_mb_valid[14] & sctag0_mb_young[14] & sctag0_mb_type14[5] & sctag0_mb_type14[1];
wire sctag0_mb14_wris64_y = sctag0_mb_valid[14] & sctag0_mb_young[14] & sctag0_mb_type14[5] & sctag0_mb_type14[2];
wire sctag0_mb15_st_ny = sctag0_mb_valid[15] & ~sctag0_mb_young[15] & ~sctag0_mb_type15[5] & (sctag0_mb_type15[4:0] == `STORE_RQ);
wire sctag0_mb15_ld_ny = sctag0_mb_valid[15] & ~sctag0_mb_young[15] & ~sctag0_mb_type15[5] & (sctag0_mb_type15[4:0] == `LOAD_RQ);
wire sctag0_mb15_wris8_ny = sctag0_mb_valid[15] & ~sctag0_mb_young[15] & sctag0_mb_type15[5] & sctag0_mb_type15[1];
wire sctag0_mb15_wris64_ny = sctag0_mb_valid[15] & ~sctag0_mb_young[15] & sctag0_mb_type15[5] & sctag0_mb_type15[2];
wire sctag0_mb15_st_y = sctag0_mb_valid[15] & sctag0_mb_young[15] & ~sctag0_mb_type15[5] & (sctag0_mb_type15[4:0] == `STORE_RQ);
wire sctag0_mb15_ld_y = sctag0_mb_valid[15] & sctag0_mb_young[15] & ~sctag0_mb_type15[5] & (sctag0_mb_type15[4:0] == `LOAD_RQ);
wire sctag0_mb15_wris8_y = sctag0_mb_valid[15] & sctag0_mb_young[15] & sctag0_mb_type15[5] & sctag0_mb_type15[1];
wire sctag0_mb15_wris64_y = sctag0_mb_valid[15] & sctag0_mb_young[15] & sctag0_mb_type15[5] & sctag0_mb_type15[2];
wire [15:0] sctag1_mb_valid = `TOP_MEMORY.sctag1.mbctl.mb_valid[15:0];
wire [15:0] sctag1_mb_young = `TOP_MEMORY.sctag1.mbctl.mb_young[15:0];
//wire [3:0] sctag1_next_link_entry0 = `TOP_MEMORY.sctag1.mbctl.next_link_entry0[3:0];
//...
//wire [3:0] sctag1_next_link_entry15 = `TOP_MEMORY.sctag1.mbctl.next_link_entry15[3:0];
wire [155:0] sctag1_mb_data_array0 = `TOP_MEMORY.sctag1.mbdata.inq_ary[0];
wire [155:0] sctag1_mb_data_array1 = `TOP_MEMORY.sctag1.mbdata.inq_ary[1];
wire [155:0] sctag1_mb_data_array2 = `TOP_MEMORY.sctag1.mbdata.inq_ary[2];
wire [155:0] sctag1_mb_data_array3 = `TOP_MEMORY.sctag1.mbdata.inq_ary[3];
wire [155:0] sctag1_mb_data_array4 = `TOP_MEMORY.sctag1.mbdata.inq_ary[4];
wire [155:0] sctag1_mb_data_array5 = `TOP_MEMORY.sctag1.mbdata.inq_ary[5];
wire [155:0] sctag1_mb_data_array6 = `TOP_MEMORY.sctag1.mbdata.inq_ary[6];
wire [155:0] sctag1_mb_data_array7 = `TOP_MEMORY.sctag1.mbdata.inq_ary[7];
wire [155:0] sctag1_mb_data_array8 = `TOP_MEMORY.sctag1.mbdata.inq_ary[8];
wire [155:0] sctag1_mb_data_array9 = `TOP_MEMORY.sctag1.mbdata.inq_ary[9];
wire [155:0] sctag1_mb_data_array10 = `TOP_MEMORY.sctag1.mbdata.inq_ary[10];
wire [155:0] sctag1_mb_data_array11 = `TOP_MEMORY.sctag1.mbdata.inq_ary[11];
wire [155:0] sctag1_mb_data_array12 = `TOP_MEMORY.sctag1.mbdata.inq_ary[12];
wire [155:0] sctag1_mb_data_array13 = `TOP_MEMORY.sctag1.mbdata.inq_ary[13];
wire [155:0] sctag1_mb_data_array14 = `TOP_MEMORY.sctag1.mbdata.inq_ary[14];
wire [155:0] sctag1_mb_data_array15 = `TOP_MEMORY.sctag1.mbdata.inq_ary[15];
//-----------------------------------------------------------------------------------------------
// look at sctag.v for L2_RDMA_HI L2_RQTYP_HI L2_RQTYP_LO and L2_RSVD
// Based ont the equation: .mb_data_write_data({57'b0,mbdata_inst_tecc_c8...
//-----------------------------------------------------------------------------------------------
wire [5:0] sctag1_mb_type0 = {sctag1_mb_data_array0 [77], sctag1_mb_data_array0 [83:79]};
wire [5:0] sctag1_mb_type1 = {sctag1_mb_data_array1 [77], sctag1_mb_data_array1 [83:79]};
wire [5:0] sctag1_mb_type2 = {sctag1_mb_data_array2 [77], sctag1_mb_data_array2 [83:79]};
wire [5:0] sctag1_mb_type3 = {sctag1_mb_data_array3 [77], sctag1_mb_data_array3 [83:79]};
wire [5:0] sctag1_mb_type4 = {sctag1_mb_data_array4 [77], sctag1_mb_data_array4 [83:79]};
wire [5:0] sctag1_mb_type5 = {sctag1_mb_data_array5 [77], sctag1_mb_data_array5 [83:79]};
wire [5:0] sctag1_mb_type6 = {sctag1_mb_data_array6 [77], sctag1_mb_data_array6 [83:79]};
wire [5:0] sctag1_mb_type7 = {sctag1_mb_data_array7 [77], sctag1_mb_data_array7 [83:79]};
wire [5:0] sctag1_mb_type8 = {sctag1_mb_data_array8 [77], sctag1_mb_data_array8 [83:79]};
wire [5:0] sctag1_mb_type9 = {sctag1_mb_data_array9 [77], sctag1_mb_data_array9 [83:79]};
wire [5:0] sctag1_mb_type10 = {sctag1_mb_data_array10[77], sctag1_mb_data_array10[83:79]};
wire [5:0] sctag1_mb_type11 = {sctag1_mb_data_array11[77], sctag1_mb_data_array11[83:79]};
wire [5:0] sctag1_mb_type12 = {sctag1_mb_data_array12[77], sctag1_mb_data_array12[83:79]};
wire [5:0] sctag1_mb_type13 = {sctag1_mb_data_array13[77], sctag1_mb_data_array13[83:79]};
wire [5:0] sctag1_mb_type14 = {sctag1_mb_data_array14[77], sctag1_mb_data_array14[83:79]};
wire [5:0] sctag1_mb_type15 = {sctag1_mb_data_array15[77], sctag1_mb_data_array15[83:79]};
//--------------------------------------------------------------
// Start figuring out what the entries are.
// bit 5 says if this is a DMA type or normal type
//--------------------------------------------------------------
wire sctag1_mb0_st_ny = sctag1_mb_valid[0] & ~sctag1_mb_young[0] & ~sctag1_mb_type0[5] & (sctag1_mb_type0[4:0] == `STORE_RQ);
wire sctag1_mb0_ld_ny = sctag1_mb_valid[0] & ~sctag1_mb_young[0] & ~sctag1_mb_type0[5] & (sctag1_mb_type0[4:0] == `LOAD_RQ);
wire sctag1_mb0_wris8_ny = sctag1_mb_valid[0] & ~sctag1_mb_young[0] & sctag1_mb_type0[5] & sctag1_mb_type0[1];
wire sctag1_mb0_wris64_ny = sctag1_mb_valid[0] & ~sctag1_mb_young[0] & sctag1_mb_type0[5] & sctag1_mb_type0[2];
wire sctag1_mb0_st_y = sctag1_mb_valid[0] & sctag1_mb_young[0] & ~sctag1_mb_type0[5] & (sctag1_mb_type0[4:0] == `STORE_RQ);
wire sctag1_mb0_ld_y = sctag1_mb_valid[0] & sctag1_mb_young[0] & ~sctag1_mb_type0[5] & (sctag1_mb_type0[4:0] == `LOAD_RQ);
wire sctag1_mb0_wris8_y = sctag1_mb_valid[0] & sctag1_mb_young[0] & sctag1_mb_type0[5] & sctag1_mb_type0[1];
wire sctag1_mb0_wris64_y = sctag1_mb_valid[0] & sctag1_mb_young[0] & sctag1_mb_type0[5] & sctag1_mb_type0[2];
wire sctag1_mb1_st_ny = sctag1_mb_valid[1] & ~sctag1_mb_young[1] & ~sctag1_mb_type1[5] & (sctag1_mb_type1[4:0] == `STORE_RQ);
wire sctag1_mb1_ld_ny = sctag1_mb_valid[1] & ~sctag1_mb_young[1] & ~sctag1_mb_type1[5] & (sctag1_mb_type1[4:0] == `LOAD_RQ);
wire sctag1_mb1_wris8_ny = sctag1_mb_valid[1] & ~sctag1_mb_young[1] & sctag1_mb_type1[5] & sctag1_mb_type1[1];
wire sctag1_mb1_wris64_ny = sctag1_mb_valid[1] & ~sctag1_mb_young[1] & sctag1_mb_type1[5] & sctag1_mb_type1[2];
wire sctag1_mb1_st_y = sctag1_mb_valid[1] & sctag1_mb_young[1] & ~sctag1_mb_type1[5] & (sctag1_mb_type1[4:0] == `STORE_RQ);
wire sctag1_mb1_ld_y = sctag1_mb_valid[1] & sctag1_mb_young[1] & ~sctag1_mb_type1[5] & (sctag1_mb_type1[4:0] == `LOAD_RQ);
wire sctag1_mb1_wris8_y = sctag1_mb_valid[1] & sctag1_mb_young[1] & sctag1_mb_type1[5] & sctag1_mb_type1[1];
wire sctag1_mb1_wris64_y = sctag1_mb_valid[1] & sctag1_mb_young[1] & sctag1_mb_type1[5] & sctag1_mb_type1[2];
wire sctag1_mb2_st_ny = sctag1_mb_valid[2] & ~sctag1_mb_young[2] & ~sctag1_mb_type2[5] & (sctag1_mb_type2[4:0] == `STORE_RQ);
wire sctag1_mb2_ld_ny = sctag1_mb_valid[2] & ~sctag1_mb_young[2] & ~sctag1_mb_type2[5] & (sctag1_mb_type2[4:0] == `LOAD_RQ);
wire sctag1_mb2_wris8_ny = sctag1_mb_valid[2] & ~sctag1_mb_young[2] & sctag1_mb_type2[5] & sctag1_mb_type2[1];
wire sctag1_mb2_wris64_ny = sctag1_mb_valid[2] & ~sctag1_mb_young[2] & sctag1_mb_type2[5] & sctag1_mb_type2[2];
wire sctag1_mb2_st_y = sctag1_mb_valid[2] & sctag1_mb_young[2] & ~sctag1_mb_type2[5] & (sctag1_mb_type2[4:0] == `STORE_RQ);
wire sctag1_mb2_ld_y = sctag1_mb_valid[2] & sctag1_mb_young[2] & ~sctag1_mb_type2[5] & (sctag1_mb_type2[4:0] == `LOAD_RQ);
wire sctag1_mb2_wris8_y = sctag1_mb_valid[2] & sctag1_mb_young[2] & sctag1_mb_type2[5] & sctag1_mb_type2[1];
wire sctag1_mb2_wris64_y = sctag1_mb_valid[2] & sctag1_mb_young[2] & sctag1_mb_type2[5] & sctag1_mb_type2[2];
wire sctag1_mb3_st_ny = sctag1_mb_valid[3] & ~sctag1_mb_young[3] & ~sctag1_mb_type3[5] & (sctag1_mb_type3[4:0] == `STORE_RQ);
wire sctag1_mb3_ld_ny = sctag1_mb_valid[3] & ~sctag1_mb_young[3] & ~sctag1_mb_type3[5] & (sctag1_mb_type3[4:0] == `LOAD_RQ);
wire sctag1_mb3_wris8_ny = sctag1_mb_valid[3] & ~sctag1_mb_young[3] & sctag1_mb_type3[5] & sctag1_mb_type3[1];
wire sctag1_mb3_wris64_ny = sctag1_mb_valid[3] & ~sctag1_mb_young[3] & sctag1_mb_type3[5] & sctag1_mb_type3[2];
wire sctag1_mb3_st_y = sctag1_mb_valid[3] & sctag1_mb_young[3] & ~sctag1_mb_type3[5] & (sctag1_mb_type3[4:0] == `STORE_RQ);
wire sctag1_mb3_ld_y = sctag1_mb_valid[3] & sctag1_mb_young[3] & ~sctag1_mb_type3[5] & (sctag1_mb_type3[4:0] == `LOAD_RQ);
wire sctag1_mb3_wris8_y = sctag1_mb_valid[3] & sctag1_mb_young[3] & sctag1_mb_type3[5] & sctag1_mb_type3[1];
wire sctag1_mb3_wris64_y = sctag1_mb_valid[3] & sctag1_mb_young[3] & sctag1_mb_type3[5] & sctag1_mb_type3[2];
wire sctag1_mb4_st_ny = sctag1_mb_valid[4] & ~sctag1_mb_young[4] & ~sctag1_mb_type4[5] & (sctag1_mb_type4[4:0] == `STORE_RQ);
wire sctag1_mb4_ld_ny = sctag1_mb_valid[4] & ~sctag1_mb_young[4] & ~sctag1_mb_type4[5] & (sctag1_mb_type4[4:0] == `LOAD_RQ);
wire sctag1_mb4_wris8_ny = sctag1_mb_valid[4] & ~sctag1_mb_young[4] & sctag1_mb_type4[5] & sctag1_mb_type4[1];
wire sctag1_mb4_wris64_ny = sctag1_mb_valid[4] & ~sctag1_mb_young[4] & sctag1_mb_type4[5] & sctag1_mb_type4[2];
wire sctag1_mb4_st_y = sctag1_mb_valid[4] & sctag1_mb_young[4] & ~sctag1_mb_type4[5] & (sctag1_mb_type4[4:0] == `STORE_RQ);
wire sctag1_mb4_ld_y = sctag1_mb_valid[4] & sctag1_mb_young[4] & ~sctag1_mb_type4[5] & (sctag1_mb_type4[4:0] == `LOAD_RQ);
wire sctag1_mb4_wris8_y = sctag1_mb_valid[4] & sctag1_mb_young[4] & sctag1_mb_type4[5] & sctag1_mb_type4[1];
wire sctag1_mb4_wris64_y = sctag1_mb_valid[4] & sctag1_mb_young[4] & sctag1_mb_type4[5] & sctag1_mb_type4[2];
wire sctag1_mb5_st_ny = sctag1_mb_valid[5] & ~sctag1_mb_young[5] & ~sctag1_mb_type5[5] & (sctag1_mb_type5[4:0] == `STORE_RQ);
wire sctag1_mb5_ld_ny = sctag1_mb_valid[5] & ~sctag1_mb_young[5] & ~sctag1_mb_type5[5] & (sctag1_mb_type5[4:0] == `LOAD_RQ);
wire sctag1_mb5_wris8_ny = sctag1_mb_valid[5] & ~sctag1_mb_young[5] & sctag1_mb_type5[5] & sctag1_mb_type5[1];
wire sctag1_mb5_wris64_ny = sctag1_mb_valid[5] & ~sctag1_mb_young[5] & sctag1_mb_type5[5] & sctag1_mb_type5[2];
wire sctag1_mb5_st_y = sctag1_mb_valid[5] & sctag1_mb_young[5] & ~sctag1_mb_type5[5] & (sctag1_mb_type5[4:0] == `STORE_RQ);
wire sctag1_mb5_ld_y = sctag1_mb_valid[5] & sctag1_mb_young[5] & ~sctag1_mb_type5[5] & (sctag1_mb_type5[4:0] == `LOAD_RQ);
wire sctag1_mb5_wris8_y = sctag1_mb_valid[5] & sctag1_mb_young[5] & sctag1_mb_type5[5] & sctag1_mb_type5[1];
wire sctag1_mb5_wris64_y = sctag1_mb_valid[5] & sctag1_mb_young[5] & sctag1_mb_type5[5] & sctag1_mb_type5[2];
wire sctag1_mb6_st_ny = sctag1_mb_valid[6] & ~sctag1_mb_young[6] & ~sctag1_mb_type6[5] & (sctag1_mb_type6[4:0] == `STORE_RQ);
wire sctag1_mb6_ld_ny = sctag1_mb_valid[6] & ~sctag1_mb_young[6] & ~sctag1_mb_type6[5] & (sctag1_mb_type6[4:0] == `LOAD_RQ);
wire sctag1_mb6_wris8_ny = sctag1_mb_valid[6] & ~sctag1_mb_young[6] & sctag1_mb_type6[5] & sctag1_mb_type6[1];
wire sctag1_mb6_wris64_ny = sctag1_mb_valid[6] & ~sctag1_mb_young[6] & sctag1_mb_type6[5] & sctag1_mb_type6[2];
wire sctag1_mb6_st_y = sctag1_mb_valid[6] & sctag1_mb_young[6] & ~sctag1_mb_type6[5] & (sctag1_mb_type6[4:0] == `STORE_RQ);
wire sctag1_mb6_ld_y = sctag1_mb_valid[6] & sctag1_mb_young[6] & ~sctag1_mb_type6[5] & (sctag1_mb_type6[4:0] == `LOAD_RQ);
wire sctag1_mb6_wris8_y = sctag1_mb_valid[6] & sctag1_mb_young[6] & sctag1_mb_type6[5] & sctag1_mb_type6[1];
wire sctag1_mb6_wris64_y = sctag1_mb_valid[6] & sctag1_mb_young[6] & sctag1_mb_type6[5] & sctag1_mb_type6[2];
wire sctag1_mb7_st_ny = sctag1_mb_valid[7] & ~sctag1_mb_young[7] & ~sctag1_mb_type7[5] & (sctag1_mb_type7[4:0] == `STORE_RQ);
wire sctag1_mb7_ld_ny = sctag1_mb_valid[7] & ~sctag1_mb_young[7] & ~sctag1_mb_type7[5] & (sctag1_mb_type7[4:0] == `LOAD_RQ);
wire sctag1_mb7_wris8_ny = sctag1_mb_valid[7] & ~sctag1_mb_young[7] & sctag1_mb_type7[5] & sctag1_mb_type7[1];
wire sctag1_mb7_wris64_ny = sctag1_mb_valid[7] & ~sctag1_mb_young[7] & sctag1_mb_type7[5] & sctag1_mb_type7[2];
wire sctag1_mb7_st_y = sctag1_mb_valid[7] & sctag1_mb_young[7] & ~sctag1_mb_type7[5] & (sctag1_mb_type7[4:0] == `STORE_RQ);
wire sctag1_mb7_ld_y = sctag1_mb_valid[7] & sctag1_mb_young[7] & ~sctag1_mb_type7[5] & (sctag1_mb_type7[4:0] == `LOAD_RQ);
wire sctag1_mb7_wris8_y = sctag1_mb_valid[7] & sctag1_mb_young[7] & sctag1_mb_type7[5] & sctag1_mb_type7[1];
wire sctag1_mb7_wris64_y = sctag1_mb_valid[7] & sctag1_mb_young[7] & sctag1_mb_type7[5] & sctag1_mb_type7[2];
wire sctag1_mb8_st_ny = sctag1_mb_valid[8] & ~sctag1_mb_young[8] & ~sctag1_mb_type8[5] & (sctag1_mb_type8[4:0] == `STORE_RQ);
wire sctag1_mb8_ld_ny = sctag1_mb_valid[8] & ~sctag1_mb_young[8] & ~sctag1_mb_type8[5] & (sctag1_mb_type8[4:0] == `LOAD_RQ);
wire sctag1_mb8_wris8_ny = sctag1_mb_valid[8] & ~sctag1_mb_young[8] & sctag1_mb_type8[5] & sctag1_mb_type8[1];
wire sctag1_mb8_wris64_ny = sctag1_mb_valid[8] & ~sctag1_mb_young[8] & sctag1_mb_type8[5] & sctag1_mb_type8[2];
wire sctag1_mb8_st_y = sctag1_mb_valid[8] & sctag1_mb_young[8] & ~sctag1_mb_type8[5] & (sctag1_mb_type8[4:0] == `STORE_RQ);
wire sctag1_mb8_ld_y = sctag1_mb_valid[8] & sctag1_mb_young[8] & ~sctag1_mb_type8[5] & (sctag1_mb_type8[4:0] == `LOAD_RQ);
wire sctag1_mb8_wris8_y = sctag1_mb_valid[8] & sctag1_mb_young[8] & sctag1_mb_type8[5] & sctag1_mb_type8[1];
wire sctag1_mb8_wris64_y = sctag1_mb_valid[8] & sctag1_mb_young[8] & sctag1_mb_type8[5] & sctag1_mb_type8[2];
wire sctag1_mb9_st_ny = sctag1_mb_valid[9] & ~sctag1_mb_young[9] & ~sctag1_mb_type9[5] & (sctag1_mb_type9[4:0] == `STORE_RQ);
wire sctag1_mb9_ld_ny = sctag1_mb_valid[9] & ~sctag1_mb_young[9] & ~sctag1_mb_type9[5] & (sctag1_mb_type9[4:0] == `LOAD_RQ);
wire sctag1_mb9_wris8_ny = sctag1_mb_valid[9] & ~sctag1_mb_young[9] & sctag1_mb_type9[5] & sctag1_mb_type9[1];
wire sctag1_mb9_wris64_ny = sctag1_mb_valid[9] & ~sctag1_mb_young[9] & sctag1_mb_type9[5] & sctag1_mb_type9[2];
wire sctag1_mb9_st_y = sctag1_mb_valid[9] & sctag1_mb_young[9] & ~sctag1_mb_type9[5] & (sctag1_mb_type9[4:0] == `STORE_RQ);
wire sctag1_mb9_ld_y = sctag1_mb_valid[9] & sctag1_mb_young[9] & ~sctag1_mb_type9[5] & (sctag1_mb_type9[4:0] == `LOAD_RQ);
wire sctag1_mb9_wris8_y = sctag1_mb_valid[9] & sctag1_mb_young[9] & sctag1_mb_type9[5] & sctag1_mb_type9[1];
wire sctag1_mb9_wris64_y = sctag1_mb_valid[9] & sctag1_mb_young[9] & sctag1_mb_type9[5] & sctag1_mb_type9[2];
wire sctag1_mb10_st_ny = sctag1_mb_valid[10] & ~sctag1_mb_young[10] & ~sctag1_mb_type10[5] & (sctag1_mb_type10[4:0] == `STORE_RQ);
wire sctag1_mb10_ld_ny = sctag1_mb_valid[10] & ~sctag1_mb_young[10] & ~sctag1_mb_type10[5] & (sctag1_mb_type10[4:0] == `LOAD_RQ);
wire sctag1_mb10_wris8_ny = sctag1_mb_valid[10] & ~sctag1_mb_young[10] & sctag1_mb_type10[5] & sctag1_mb_type10[1];
wire sctag1_mb10_wris64_ny = sctag1_mb_valid[10] & ~sctag1_mb_young[10] & sctag1_mb_type10[5] & sctag1_mb_type10[2];
wire sctag1_mb10_st_y = sctag1_mb_valid[10] & sctag1_mb_young[10] & ~sctag1_mb_type10[5] & (sctag1_mb_type10[4:0] == `STORE_RQ);
wire sctag1_mb10_ld_y = sctag1_mb_valid[10] & sctag1_mb_young[10] & ~sctag1_mb_type10[5] & (sctag1_mb_type10[4:0] == `LOAD_RQ);
wire sctag1_mb10_wris8_y = sctag1_mb_valid[10] & sctag1_mb_young[10] & sctag1_mb_type10[5] & sctag1_mb_type10[1];
wire sctag1_mb10_wris64_y = sctag1_mb_valid[10] & sctag1_mb_young[10] & sctag1_mb_type10[5] & sctag1_mb_type10[2];
wire sctag1_mb11_st_ny = sctag1_mb_valid[11] & ~sctag1_mb_young[11] & ~sctag1_mb_type11[5] & (sctag1_mb_type11[4:0] == `STORE_RQ);
wire sctag1_mb11_ld_ny = sctag1_mb_valid[11] & ~sctag1_mb_young[11] & ~sctag1_mb_type11[5] & (sctag1_mb_type11[4:0] == `LOAD_RQ);
wire sctag1_mb11_wris8_ny = sctag1_mb_valid[11] & ~sctag1_mb_young[11] & sctag1_mb_type11[5] & sctag1_mb_type11[1];
wire sctag1_mb11_wris64_ny = sctag1_mb_valid[11] & ~sctag1_mb_young[11] & sctag1_mb_type11[5] & sctag1_mb_type11[2];
wire sctag1_mb11_st_y = sctag1_mb_valid[11] & sctag1_mb_young[11] & ~sctag1_mb_type11[5] & (sctag1_mb_type11[4:0] == `STORE_RQ);
wire sctag1_mb11_ld_y = sctag1_mb_valid[11] & sctag1_mb_young[11] & ~sctag1_mb_type11[5] & (sctag1_mb_type11[4:0] == `LOAD_RQ);
wire sctag1_mb11_wris8_y = sctag1_mb_valid[11] & sctag1_mb_young[11] & sctag1_mb_type11[5] & sctag1_mb_type11[1];
wire sctag1_mb11_wris64_y = sctag1_mb_valid[11] & sctag1_mb_young[11] & sctag1_mb_type11[5] & sctag1_mb_type11[2];
wire sctag1_mb12_st_ny = sctag1_mb_valid[12] & ~sctag1_mb_young[12] & ~sctag1_mb_type12[5] & (sctag1_mb_type12[4:0] == `STORE_RQ);
wire sctag1_mb12_ld_ny = sctag1_mb_valid[12] & ~sctag1_mb_young[12] & ~sctag1_mb_type12[5] & (sctag1_mb_type12[4:0] == `LOAD_RQ);
wire sctag1_mb12_wris8_ny = sctag1_mb_valid[12] & ~sctag1_mb_young[12] & sctag1_mb_type12[5] & sctag1_mb_type12[1];
wire sctag1_mb12_wris64_ny = sctag1_mb_valid[12] & ~sctag1_mb_young[12] & sctag1_mb_type12[5] & sctag1_mb_type12[2];
wire sctag1_mb12_st_y = sctag1_mb_valid[12] & sctag1_mb_young[12] & ~sctag1_mb_type12[5] & (sctag1_mb_type12[4:0] == `STORE_RQ);
wire sctag1_mb12_ld_y = sctag1_mb_valid[12] & sctag1_mb_young[12] & ~sctag1_mb_type12[5] & (sctag1_mb_type12[4:0] == `LOAD_RQ);
wire sctag1_mb12_wris8_y = sctag1_mb_valid[12] & sctag1_mb_young[12] & sctag1_mb_type12[5] & sctag1_mb_type12[1];
wire sctag1_mb12_wris64_y = sctag1_mb_valid[12] & sctag1_mb_young[12] & sctag1_mb_type12[5] & sctag1_mb_type12[2];
wire sctag1_mb13_st_ny = sctag1_mb_valid[13] & ~sctag1_mb_young[13] & ~sctag1_mb_type13[5] & (sctag1_mb_type13[4:0] == `STORE_RQ);
wire sctag1_mb13_ld_ny = sctag1_mb_valid[13] & ~sctag1_mb_young[13] & ~sctag1_mb_type13[5] & (sctag1_mb_type13[4:0] == `LOAD_RQ);
wire sctag1_mb13_wris8_ny = sctag1_mb_valid[13] & ~sctag1_mb_young[13] & sctag1_mb_type13[5] & sctag1_mb_type13[1];
wire sctag1_mb13_wris64_ny = sctag1_mb_valid[13] & ~sctag1_mb_young[13] & sctag1_mb_type13[5] & sctag1_mb_type13[2];
wire sctag1_mb13_st_y = sctag1_mb_valid[13] & sctag1_mb_young[13] & ~sctag1_mb_type13[5] & (sctag1_mb_type13[4:0] == `STORE_RQ);
wire sctag1_mb13_ld_y = sctag1_mb_valid[13] & sctag1_mb_young[13] & ~sctag1_mb_type13[5] & (sctag1_mb_type13[4:0] == `LOAD_RQ);
wire sctag1_mb13_wris8_y = sctag1_mb_valid[13] & sctag1_mb_young[13] & sctag1_mb_type13[5] & sctag1_mb_type13[1];
wire sctag1_mb13_wris64_y = sctag1_mb_valid[13] & sctag1_mb_young[13] & sctag1_mb_type13[5] & sctag1_mb_type13[2];
wire sctag1_mb14_st_ny = sctag1_mb_valid[14] & ~sctag1_mb_young[14] & ~sctag1_mb_type14[5] & (sctag1_mb_type14[4:0] == `STORE_RQ);
wire sctag1_mb14_ld_ny = sctag1_mb_valid[14] & ~sctag1_mb_young[14] & ~sctag1_mb_type14[5] & (sctag1_mb_type14[4:0] == `LOAD_RQ);
wire sctag1_mb14_wris8_ny = sctag1_mb_valid[14] & ~sctag1_mb_young[14] & sctag1_mb_type14[5] & sctag1_mb_type14[1];
wire sctag1_mb14_wris64_ny = sctag1_mb_valid[14] & ~sctag1_mb_young[14] & sctag1_mb_type14[5] & sctag1_mb_type14[2];
wire sctag1_mb14_st_y = sctag1_mb_valid[14] & sctag1_mb_young[14] & ~sctag1_mb_type14[5] & (sctag1_mb_type14[4:0] == `STORE_RQ);
wire sctag1_mb14_ld_y = sctag1_mb_valid[14] & sctag1_mb_young[14] & ~sctag1_mb_type14[5] & (sctag1_mb_type14[4:0] == `LOAD_RQ);
wire sctag1_mb14_wris8_y = sctag1_mb_valid[14] & sctag1_mb_young[14] & sctag1_mb_type14[5] & sctag1_mb_type14[1];
wire sctag1_mb14_wris64_y = sctag1_mb_valid[14] & sctag1_mb_young[14] & sctag1_mb_type14[5] & sctag1_mb_type14[2];
wire sctag1_mb15_st_ny = sctag1_mb_valid[15] & ~sctag1_mb_young[15] & ~sctag1_mb_type15[5] & (sctag1_mb_type15[4:0] == `STORE_RQ);
wire sctag1_mb15_ld_ny = sctag1_mb_valid[15] & ~sctag1_mb_young[15] & ~sctag1_mb_type15[5] & (sctag1_mb_type15[4:0] == `LOAD_RQ);
wire sctag1_mb15_wris8_ny = sctag1_mb_valid[15] & ~sctag1_mb_young[15] & sctag1_mb_type15[5] & sctag1_mb_type15[1];
wire sctag1_mb15_wris64_ny = sctag1_mb_valid[15] & ~sctag1_mb_young[15] & sctag1_mb_type15[5] & sctag1_mb_type15[2];
wire sctag1_mb15_st_y = sctag1_mb_valid[15] & sctag1_mb_young[15] & ~sctag1_mb_type15[5] & (sctag1_mb_type15[4:0] == `STORE_RQ);
wire sctag1_mb15_ld_y = sctag1_mb_valid[15] & sctag1_mb_young[15] & ~sctag1_mb_type15[5] & (sctag1_mb_type15[4:0] == `LOAD_RQ);
wire sctag1_mb15_wris8_y = sctag1_mb_valid[15] & sctag1_mb_young[15] & sctag1_mb_type15[5] & sctag1_mb_type15[1];
wire sctag1_mb15_wris64_y = sctag1_mb_valid[15] & sctag1_mb_young[15] & sctag1_mb_type15[5] & sctag1_mb_type15[2];
wire [15:0] sctag2_mb_valid = `TOP_MEMORY.sctag2.mbctl.mb_valid[15:0];
wire [15:0] sctag2_mb_young = `TOP_MEMORY.sctag2.mbctl.mb_young[15:0];
//wire [3:0] sctag2_next_link_entry0 = `TOP_MEMORY.sctag2.mbctl.next_link_entry0[3:0];
//...
//wire [3:0] sctag2_next_link_entry15 = `TOP_MEMORY.sctag2.mbctl.next_link_entry15[3:0];
wire [155:0] sctag2_mb_data_array0 = `TOP_MEMORY.sctag2.mbdata.inq_ary[0];
wire [155:0] sctag2_mb_data_array1 = `TOP_MEMORY.sctag2.mbdata.inq_ary[1];
wire [155:0] sctag2_mb_data_array2 = `TOP_MEMORY.sctag2.mbdata.inq_ary[2];
wire [155:0] sctag2_mb_data_array3 = `TOP_MEMORY.sctag2.mbdata.inq_ary[3];
wire [155:0] sctag2_mb_data_array4 = `TOP_MEMORY.sctag2.mbdata.inq_ary[4];
wire [155:0] sctag2_mb_data_array5 = `TOP_MEMORY.sctag2.mbdata.inq_ary[5];
wire [155:0] sctag2_mb_data_array6 = `TOP_MEMORY.sctag2.mbdata.inq_ary[6];
wire [155:0] sctag2_mb_data_array7 = `TOP_MEMORY.sctag2.mbdata.inq_ary[7];
wire [155:0] sctag2_mb_data_array8 = `TOP_MEMORY.sctag2.mbdata.inq_ary[8];
wire [155:0] sctag2_mb_data_array9 = `TOP_MEMORY.sctag2.mbdata.inq_ary[9];
wire [155:0] sctag2_mb_data_array10 = `TOP_MEMORY.sctag2.mbdata.inq_ary[10];
wire [155:0] sctag2_mb_data_array11 = `TOP_MEMORY.sctag2.mbdata.inq_ary[11];
wire [155:0] sctag2_mb_data_array12 = `TOP_MEMORY.sctag2.mbdata.inq_ary[12];
wire [155:0] sctag2_mb_data_array13 = `TOP_MEMORY.sctag2.mbdata.inq_ary[13];
wire [155:0] sctag2_mb_data_array14 = `TOP_MEMORY.sctag2.mbdata.inq_ary[14];
wire [155:0] sctag2_mb_data_array15 = `TOP_MEMORY.sctag2.mbdata.inq_ary[15];
//-----------------------------------------------------------------------------------------------
// look at sctag.v for L2_RDMA_HI L2_RQTYP_HI L2_RQTYP_LO and L2_RSVD
// Based ont the equation: .mb_data_write_data({57'b0,mbdata_inst_tecc_c8...
//-----------------------------------------------------------------------------------------------
wire [5:0] sctag2_mb_type0 = {sctag2_mb_data_array0 [77], sctag2_mb_data_array0 [83:79]};
wire [5:0] sctag2_mb_type1 = {sctag2_mb_data_array1 [77], sctag2_mb_data_array1 [83:79]};
wire [5:0] sctag2_mb_type2 = {sctag2_mb_data_array2 [77], sctag2_mb_data_array2 [83:79]};
wire [5:0] sctag2_mb_type3 = {sctag2_mb_data_array3 [77], sctag2_mb_data_array3 [83:79]};
wire [5:0] sctag2_mb_type4 = {sctag2_mb_data_array4 [77], sctag2_mb_data_array4 [83:79]};
wire [5:0] sctag2_mb_type5 = {sctag2_mb_data_array5 [77], sctag2_mb_data_array5 [83:79]};
wire [5:0] sctag2_mb_type6 = {sctag2_mb_data_array6 [77], sctag2_mb_data_array6 [83:79]};
wire [5:0] sctag2_mb_type7 = {sctag2_mb_data_array7 [77], sctag2_mb_data_array7 [83:79]};
wire [5:0] sctag2_mb_type8 = {sctag2_mb_data_array8 [77], sctag2_mb_data_array8 [83:79]};
wire [5:0] sctag2_mb_type9 = {sctag2_mb_data_array9 [77], sctag2_mb_data_array9 [83:79]};
wire [5:0] sctag2_mb_type10 = {sctag2_mb_data_array10[77], sctag2_mb_data_array10[83:79]};
wire [5:0] sctag2_mb_type11 = {sctag2_mb_data_array11[77], sctag2_mb_data_array11[83:79]};
wire [5:0] sctag2_mb_type12 = {sctag2_mb_data_array12[77], sctag2_mb_data_array12[83:79]};
wire [5:0] sctag2_mb_type13 = {sctag2_mb_data_array13[77], sctag2_mb_data_array13[83:79]};
wire [5:0] sctag2_mb_type14 = {sctag2_mb_data_array14[77], sctag2_mb_data_array14[83:79]};
wire [5:0] sctag2_mb_type15 = {sctag2_mb_data_array15[77], sctag2_mb_data_array15[83:79]};
//--------------------------------------------------------------
// Start figuring out what the entries are.
// bit 5 says if this is a DMA type or normal type
//--------------------------------------------------------------
wire sctag2_mb0_st_ny = sctag2_mb_valid[0] & ~sctag2_mb_young[0] & ~sctag2_mb_type0[5] & (sctag2_mb_type0[4:0] == `STORE_RQ);
wire sctag2_mb0_ld_ny = sctag2_mb_valid[0] & ~sctag2_mb_young[0] & ~sctag2_mb_type0[5] & (sctag2_mb_type0[4:0] == `LOAD_RQ);
wire sctag2_mb0_wris8_ny = sctag2_mb_valid[0] & ~sctag2_mb_young[0] & sctag2_mb_type0[5] & sctag2_mb_type0[1];
wire sctag2_mb0_wris64_ny = sctag2_mb_valid[0] & ~sctag2_mb_young[0] & sctag2_mb_type0[5] & sctag2_mb_type0[2];
wire sctag2_mb0_st_y = sctag2_mb_valid[0] & sctag2_mb_young[0] & ~sctag2_mb_type0[5] & (sctag2_mb_type0[4:0] == `STORE_RQ);
wire sctag2_mb0_ld_y = sctag2_mb_valid[0] & sctag2_mb_young[0] & ~sctag2_mb_type0[5] & (sctag2_mb_type0[4:0] == `LOAD_RQ);
wire sctag2_mb0_wris8_y = sctag2_mb_valid[0] & sctag2_mb_young[0] & sctag2_mb_type0[5] & sctag2_mb_type0[1];
wire sctag2_mb0_wris64_y = sctag2_mb_valid[0] & sctag2_mb_young[0] & sctag2_mb_type0[5] & sctag2_mb_type0[2];
wire sctag2_mb1_st_ny = sctag2_mb_valid[1] & ~sctag2_mb_young[1] & ~sctag2_mb_type1[5] & (sctag2_mb_type1[4:0] == `STORE_RQ);
wire sctag2_mb1_ld_ny = sctag2_mb_valid[1] & ~sctag2_mb_young[1] & ~sctag2_mb_type1[5] & (sctag2_mb_type1[4:0] == `LOAD_RQ);
wire sctag2_mb1_wris8_ny = sctag2_mb_valid[1] & ~sctag2_mb_young[1] & sctag2_mb_type1[5] & sctag2_mb_type1[1];
wire sctag2_mb1_wris64_ny = sctag2_mb_valid[1] & ~sctag2_mb_young[1] & sctag2_mb_type1[5] & sctag2_mb_type1[2];
wire sctag2_mb1_st_y = sctag2_mb_valid[1] & sctag2_mb_young[1] & ~sctag2_mb_type1[5] & (sctag2_mb_type1[4:0] == `STORE_RQ);
wire sctag2_mb1_ld_y = sctag2_mb_valid[1] & sctag2_mb_young[1] & ~sctag2_mb_type1[5] & (sctag2_mb_type1[4:0] == `LOAD_RQ);
wire sctag2_mb1_wris8_y = sctag2_mb_valid[1] & sctag2_mb_young[1] & sctag2_mb_type1[5] & sctag2_mb_type1[1];
wire sctag2_mb1_wris64_y = sctag2_mb_valid[1] & sctag2_mb_young[1] & sctag2_mb_type1[5] & sctag2_mb_type1[2];
wire sctag2_mb2_st_ny = sctag2_mb_valid[2] & ~sctag2_mb_young[2] & ~sctag2_mb_type2[5] & (sctag2_mb_type2[4:0] == `STORE_RQ);
wire sctag2_mb2_ld_ny = sctag2_mb_valid[2] & ~sctag2_mb_young[2] & ~sctag2_mb_type2[5] & (sctag2_mb_type2[4:0] == `LOAD_RQ);
wire sctag2_mb2_wris8_ny = sctag2_mb_valid[2] & ~sctag2_mb_young[2] & sctag2_mb_type2[5] & sctag2_mb_type2[1];
wire sctag2_mb2_wris64_ny = sctag2_mb_valid[2] & ~sctag2_mb_young[2] & sctag2_mb_type2[5] & sctag2_mb_type2[2];
wire sctag2_mb2_st_y = sctag2_mb_valid[2] & sctag2_mb_young[2] & ~sctag2_mb_type2[5] & (sctag2_mb_type2[4:0] == `STORE_RQ);
wire sctag2_mb2_ld_y = sctag2_mb_valid[2] & sctag2_mb_young[2] & ~sctag2_mb_type2[5] & (sctag2_mb_type2[4:0] == `LOAD_RQ);
wire sctag2_mb2_wris8_y = sctag2_mb_valid[2] & sctag2_mb_young[2] & sctag2_mb_type2[5] & sctag2_mb_type2[1];
wire sctag2_mb2_wris64_y = sctag2_mb_valid[2] & sctag2_mb_young[2] & sctag2_mb_type2[5] & sctag2_mb_type2[2];
wire sctag2_mb3_st_ny = sctag2_mb_valid[3] & ~sctag2_mb_young[3] & ~sctag2_mb_type3[5] & (sctag2_mb_type3[4:0] == `STORE_RQ);
wire sctag2_mb3_ld_ny = sctag2_mb_valid[3] & ~sctag2_mb_young[3] & ~sctag2_mb_type3[5] & (sctag2_mb_type3[4:0] == `LOAD_RQ);
wire sctag2_mb3_wris8_ny = sctag2_mb_valid[3] & ~sctag2_mb_young[3] & sctag2_mb_type3[5] & sctag2_mb_type3[1];
wire sctag2_mb3_wris64_ny = sctag2_mb_valid[3] & ~sctag2_mb_young[3] & sctag2_mb_type3[5] & sctag2_mb_type3[2];
wire sctag2_mb3_st_y = sctag2_mb_valid[3] & sctag2_mb_young[3] & ~sctag2_mb_type3[5] & (sctag2_mb_type3[4:0] == `STORE_RQ);
wire sctag2_mb3_ld_y = sctag2_mb_valid[3] & sctag2_mb_young[3] & ~sctag2_mb_type3[5] & (sctag2_mb_type3[4:0] == `LOAD_RQ);
wire sctag2_mb3_wris8_y = sctag2_mb_valid[3] & sctag2_mb_young[3] & sctag2_mb_type3[5] & sctag2_mb_type3[1];
wire sctag2_mb3_wris64_y = sctag2_mb_valid[3] & sctag2_mb_young[3] & sctag2_mb_type3[5] & sctag2_mb_type3[2];
wire sctag2_mb4_st_ny = sctag2_mb_valid[4] & ~sctag2_mb_young[4] & ~sctag2_mb_type4[5] & (sctag2_mb_type4[4:0] == `STORE_RQ);
wire sctag2_mb4_ld_ny = sctag2_mb_valid[4] & ~sctag2_mb_young[4] & ~sctag2_mb_type4[5] & (sctag2_mb_type4[4:0] == `LOAD_RQ);
wire sctag2_mb4_wris8_ny = sctag2_mb_valid[4] & ~sctag2_mb_young[4] & sctag2_mb_type4[5] & sctag2_mb_type4[1];
wire sctag2_mb4_wris64_ny = sctag2_mb_valid[4] & ~sctag2_mb_young[4] & sctag2_mb_type4[5] & sctag2_mb_type4[2];
wire sctag2_mb4_st_y = sctag2_mb_valid[4] & sctag2_mb_young[4] & ~sctag2_mb_type4[5] & (sctag2_mb_type4[4:0] == `STORE_RQ);
wire sctag2_mb4_ld_y = sctag2_mb_valid[4] & sctag2_mb_young[4] & ~sctag2_mb_type4[5] & (sctag2_mb_type4[4:0] == `LOAD_RQ);
wire sctag2_mb4_wris8_y = sctag2_mb_valid[4] & sctag2_mb_young[4] & sctag2_mb_type4[5] & sctag2_mb_type4[1];
wire sctag2_mb4_wris64_y = sctag2_mb_valid[4] & sctag2_mb_young[4] & sctag2_mb_type4[5] & sctag2_mb_type4[2];
wire sctag2_mb5_st_ny = sctag2_mb_valid[5] & ~sctag2_mb_young[5] & ~sctag2_mb_type5[5] & (sctag2_mb_type5[4:0] == `STORE_RQ);
wire sctag2_mb5_ld_ny = sctag2_mb_valid[5] & ~sctag2_mb_young[5] & ~sctag2_mb_type5[5] & (sctag2_mb_type5[4:0] == `LOAD_RQ);
wire sctag2_mb5_wris8_ny = sctag2_mb_valid[5] & ~sctag2_mb_young[5] & sctag2_mb_type5[5] & sctag2_mb_type5[1];
wire sctag2_mb5_wris64_ny = sctag2_mb_valid[5] & ~sctag2_mb_young[5] & sctag2_mb_type5[5] & sctag2_mb_type5[2];
wire sctag2_mb5_st_y = sctag2_mb_valid[5] & sctag2_mb_young[5] & ~sctag2_mb_type5[5] & (sctag2_mb_type5[4:0] == `STORE_RQ);
wire sctag2_mb5_ld_y = sctag2_mb_valid[5] & sctag2_mb_young[5] & ~sctag2_mb_type5[5] & (sctag2_mb_type5[4:0] == `LOAD_RQ);
wire sctag2_mb5_wris8_y = sctag2_mb_valid[5] & sctag2_mb_young[5] & sctag2_mb_type5[5] & sctag2_mb_type5[1];
wire sctag2_mb5_wris64_y = sctag2_mb_valid[5] & sctag2_mb_young[5] & sctag2_mb_type5[5] & sctag2_mb_type5[2];
wire sctag2_mb6_st_ny = sctag2_mb_valid[6] & ~sctag2_mb_young[6] & ~sctag2_mb_type6[5] & (sctag2_mb_type6[4:0] == `STORE_RQ);
wire sctag2_mb6_ld_ny = sctag2_mb_valid[6] & ~sctag2_mb_young[6] & ~sctag2_mb_type6[5] & (sctag2_mb_type6[4:0] == `LOAD_RQ);
wire sctag2_mb6_wris8_ny = sctag2_mb_valid[6] & ~sctag2_mb_young[6] & sctag2_mb_type6[5] & sctag2_mb_type6[1];
wire sctag2_mb6_wris64_ny = sctag2_mb_valid[6] & ~sctag2_mb_young[6] & sctag2_mb_type6[5] & sctag2_mb_type6[2];
wire sctag2_mb6_st_y = sctag2_mb_valid[6] & sctag2_mb_young[6] & ~sctag2_mb_type6[5] & (sctag2_mb_type6[4:0] == `STORE_RQ);
wire sctag2_mb6_ld_y = sctag2_mb_valid[6] & sctag2_mb_young[6] & ~sctag2_mb_type6[5] & (sctag2_mb_type6[4:0] == `LOAD_RQ);
wire sctag2_mb6_wris8_y = sctag2_mb_valid[6] & sctag2_mb_young[6] & sctag2_mb_type6[5] & sctag2_mb_type6[1];
wire sctag2_mb6_wris64_y = sctag2_mb_valid[6] & sctag2_mb_young[6] & sctag2_mb_type6[5] & sctag2_mb_type6[2];
wire sctag2_mb7_st_ny = sctag2_mb_valid[7] & ~sctag2_mb_young[7] & ~sctag2_mb_type7[5] & (sctag2_mb_type7[4:0] == `STORE_RQ);
wire sctag2_mb7_ld_ny = sctag2_mb_valid[7] & ~sctag2_mb_young[7] & ~sctag2_mb_type7[5] & (sctag2_mb_type7[4:0] == `LOAD_RQ);
wire sctag2_mb7_wris8_ny = sctag2_mb_valid[7] & ~sctag2_mb_young[7] & sctag2_mb_type7[5] & sctag2_mb_type7[1];
wire sctag2_mb7_wris64_ny = sctag2_mb_valid[7] & ~sctag2_mb_young[7] & sctag2_mb_type7[5] & sctag2_mb_type7[2];
wire sctag2_mb7_st_y = sctag2_mb_valid[7] & sctag2_mb_young[7] & ~sctag2_mb_type7[5] & (sctag2_mb_type7[4:0] == `STORE_RQ);
wire sctag2_mb7_ld_y = sctag2_mb_valid[7] & sctag2_mb_young[7] & ~sctag2_mb_type7[5] & (sctag2_mb_type7[4:0] == `LOAD_RQ);
wire sctag2_mb7_wris8_y = sctag2_mb_valid[7] & sctag2_mb_young[7] & sctag2_mb_type7[5] & sctag2_mb_type7[1];
wire sctag2_mb7_wris64_y = sctag2_mb_valid[7] & sctag2_mb_young[7] & sctag2_mb_type7[5] & sctag2_mb_type7[2];
wire sctag2_mb8_st_ny = sctag2_mb_valid[8] & ~sctag2_mb_young[8] & ~sctag2_mb_type8[5] & (sctag2_mb_type8[4:0] == `STORE_RQ);
wire sctag2_mb8_ld_ny = sctag2_mb_valid[8] & ~sctag2_mb_young[8] & ~sctag2_mb_type8[5] & (sctag2_mb_type8[4:0] == `LOAD_RQ);
wire sctag2_mb8_wris8_ny = sctag2_mb_valid[8] & ~sctag2_mb_young[8] & sctag2_mb_type8[5] & sctag2_mb_type8[1];
wire sctag2_mb8_wris64_ny = sctag2_mb_valid[8] & ~sctag2_mb_young[8] & sctag2_mb_type8[5] & sctag2_mb_type8[2];
wire sctag2_mb8_st_y = sctag2_mb_valid[8] & sctag2_mb_young[8] & ~sctag2_mb_type8[5] & (sctag2_mb_type8[4:0] == `STORE_RQ);
wire sctag2_mb8_ld_y = sctag2_mb_valid[8] & sctag2_mb_young[8] & ~sctag2_mb_type8[5] & (sctag2_mb_type8[4:0] == `LOAD_RQ);
wire sctag2_mb8_wris8_y = sctag2_mb_valid[8] & sctag2_mb_young[8] & sctag2_mb_type8[5] & sctag2_mb_type8[1];
wire sctag2_mb8_wris64_y = sctag2_mb_valid[8] & sctag2_mb_young[8] & sctag2_mb_type8[5] & sctag2_mb_type8[2];
wire sctag2_mb9_st_ny = sctag2_mb_valid[9] & ~sctag2_mb_young[9] & ~sctag2_mb_type9[5] & (sctag2_mb_type9[4:0] == `STORE_RQ);
wire sctag2_mb9_ld_ny = sctag2_mb_valid[9] & ~sctag2_mb_young[9] & ~sctag2_mb_type9[5] & (sctag2_mb_type9[4:0] == `LOAD_RQ);
wire sctag2_mb9_wris8_ny = sctag2_mb_valid[9] & ~sctag2_mb_young[9] & sctag2_mb_type9[5] & sctag2_mb_type9[1];
wire sctag2_mb9_wris64_ny = sctag2_mb_valid[9] & ~sctag2_mb_young[9] & sctag2_mb_type9[5] & sctag2_mb_type9[2];
wire sctag2_mb9_st_y = sctag2_mb_valid[9] & sctag2_mb_young[9] & ~sctag2_mb_type9[5] & (sctag2_mb_type9[4:0] == `STORE_RQ);
wire sctag2_mb9_ld_y = sctag2_mb_valid[9] & sctag2_mb_young[9] & ~sctag2_mb_type9[5] & (sctag2_mb_type9[4:0] == `LOAD_RQ);
wire sctag2_mb9_wris8_y = sctag2_mb_valid[9] & sctag2_mb_young[9] & sctag2_mb_type9[5] & sctag2_mb_type9[1];
wire sctag2_mb9_wris64_y = sctag2_mb_valid[9] & sctag2_mb_young[9] & sctag2_mb_type9[5] & sctag2_mb_type9[2];
wire sctag2_mb10_st_ny = sctag2_mb_valid[10] & ~sctag2_mb_young[10] & ~sctag2_mb_type10[5] & (sctag2_mb_type10[4:0] == `STORE_RQ);
wire sctag2_mb10_ld_ny = sctag2_mb_valid[10] & ~sctag2_mb_young[10] & ~sctag2_mb_type10[5] & (sctag2_mb_type10[4:0] == `LOAD_RQ);
wire sctag2_mb10_wris8_ny = sctag2_mb_valid[10] & ~sctag2_mb_young[10] & sctag2_mb_type10[5] & sctag2_mb_type10[1];
wire sctag2_mb10_wris64_ny = sctag2_mb_valid[10] & ~sctag2_mb_young[10] & sctag2_mb_type10[5] & sctag2_mb_type10[2];
wire sctag2_mb10_st_y = sctag2_mb_valid[10] & sctag2_mb_young[10] & ~sctag2_mb_type10[5] & (sctag2_mb_type10[4:0] == `STORE_RQ);
wire sctag2_mb10_ld_y = sctag2_mb_valid[10] & sctag2_mb_young[10] & ~sctag2_mb_type10[5] & (sctag2_mb_type10[4:0] == `LOAD_RQ);
wire sctag2_mb10_wris8_y = sctag2_mb_valid[10] & sctag2_mb_young[10] & sctag2_mb_type10[5] & sctag2_mb_type10[1];
wire sctag2_mb10_wris64_y = sctag2_mb_valid[10] & sctag2_mb_young[10] & sctag2_mb_type10[5] & sctag2_mb_type10[2];
wire sctag2_mb11_st_ny = sctag2_mb_valid[11] & ~sctag2_mb_young[11] & ~sctag2_mb_type11[5] & (sctag2_mb_type11[4:0] == `STORE_RQ);
wire sctag2_mb11_ld_ny = sctag2_mb_valid[11] & ~sctag2_mb_young[11] & ~sctag2_mb_type11[5] & (sctag2_mb_type11[4:0] == `LOAD_RQ);
wire sctag2_mb11_wris8_ny = sctag2_mb_valid[11] & ~sctag2_mb_young[11] & sctag2_mb_type11[5] & sctag2_mb_type11[1];
wire sctag2_mb11_wris64_ny = sctag2_mb_valid[11] & ~sctag2_mb_young[11] & sctag2_mb_type11[5] & sctag2_mb_type11[2];
wire sctag2_mb11_st_y = sctag2_mb_valid[11] & sctag2_mb_young[11] & ~sctag2_mb_type11[5] & (sctag2_mb_type11[4:0] == `STORE_RQ);
wire sctag2_mb11_ld_y = sctag2_mb_valid[11] & sctag2_mb_young[11] & ~sctag2_mb_type11[5] & (sctag2_mb_type11[4:0] == `LOAD_RQ);
wire sctag2_mb11_wris8_y = sctag2_mb_valid[11] & sctag2_mb_young[11] & sctag2_mb_type11[5] & sctag2_mb_type11[1];
wire sctag2_mb11_wris64_y = sctag2_mb_valid[11] & sctag2_mb_young[11] & sctag2_mb_type11[5] & sctag2_mb_type11[2];
wire sctag2_mb12_st_ny = sctag2_mb_valid[12] & ~sctag2_mb_young[12] & ~sctag2_mb_type12[5] & (sctag2_mb_type12[4:0] == `STORE_RQ);
wire sctag2_mb12_ld_ny = sctag2_mb_valid[12] & ~sctag2_mb_young[12] & ~sctag2_mb_type12[5] & (sctag2_mb_type12[4:0] == `LOAD_RQ);
wire sctag2_mb12_wris8_ny = sctag2_mb_valid[12] & ~sctag2_mb_young[12] & sctag2_mb_type12[5] & sctag2_mb_type12[1];
wire sctag2_mb12_wris64_ny = sctag2_mb_valid[12] & ~sctag2_mb_young[12] & sctag2_mb_type12[5] & sctag2_mb_type12[2];
wire sctag2_mb12_st_y = sctag2_mb_valid[12] & sctag2_mb_young[12] & ~sctag2_mb_type12[5] & (sctag2_mb_type12[4:0] == `STORE_RQ);
wire sctag2_mb12_ld_y = sctag2_mb_valid[12] & sctag2_mb_young[12] & ~sctag2_mb_type12[5] & (sctag2_mb_type12[4:0] == `LOAD_RQ);
wire sctag2_mb12_wris8_y = sctag2_mb_valid[12] & sctag2_mb_young[12] & sctag2_mb_type12[5] & sctag2_mb_type12[1];
wire sctag2_mb12_wris64_y = sctag2_mb_valid[12] & sctag2_mb_young[12] & sctag2_mb_type12[5] & sctag2_mb_type12[2];
wire sctag2_mb13_st_ny = sctag2_mb_valid[13] & ~sctag2_mb_young[13] & ~sctag2_mb_type13[5] & (sctag2_mb_type13[4:0] == `STORE_RQ);
wire sctag2_mb13_ld_ny = sctag2_mb_valid[13] & ~sctag2_mb_young[13] & ~sctag2_mb_type13[5] & (sctag2_mb_type13[4:0] == `LOAD_RQ);
wire sctag2_mb13_wris8_ny = sctag2_mb_valid[13] & ~sctag2_mb_young[13] & sctag2_mb_type13[5] & sctag2_mb_type13[1];
wire sctag2_mb13_wris64_ny = sctag2_mb_valid[13] & ~sctag2_mb_young[13] & sctag2_mb_type13[5] & sctag2_mb_type13[2];
wire sctag2_mb13_st_y = sctag2_mb_valid[13] & sctag2_mb_young[13] & ~sctag2_mb_type13[5] & (sctag2_mb_type13[4:0] == `STORE_RQ);
wire sctag2_mb13_ld_y = sctag2_mb_valid[13] & sctag2_mb_young[13] & ~sctag2_mb_type13[5] & (sctag2_mb_type13[4:0] == `LOAD_RQ);
wire sctag2_mb13_wris8_y = sctag2_mb_valid[13] & sctag2_mb_young[13] & sctag2_mb_type13[5] & sctag2_mb_type13[1];
wire sctag2_mb13_wris64_y = sctag2_mb_valid[13] & sctag2_mb_young[13] & sctag2_mb_type13[5] & sctag2_mb_type13[2];
wire sctag2_mb14_st_ny = sctag2_mb_valid[14] & ~sctag2_mb_young[14] & ~sctag2_mb_type14[5] & (sctag2_mb_type14[4:0] == `STORE_RQ);
wire sctag2_mb14_ld_ny = sctag2_mb_valid[14] & ~sctag2_mb_young[14] & ~sctag2_mb_type14[5] & (sctag2_mb_type14[4:0] == `LOAD_RQ);
wire sctag2_mb14_wris8_ny = sctag2_mb_valid[14] & ~sctag2_mb_young[14] & sctag2_mb_type14[5] & sctag2_mb_type14[1];
wire sctag2_mb14_wris64_ny = sctag2_mb_valid[14] & ~sctag2_mb_young[14] & sctag2_mb_type14[5] & sctag2_mb_type14[2];
wire sctag2_mb14_st_y = sctag2_mb_valid[14] & sctag2_mb_young[14] & ~sctag2_mb_type14[5] & (sctag2_mb_type14[4:0] == `STORE_RQ);
wire sctag2_mb14_ld_y = sctag2_mb_valid[14] & sctag2_mb_young[14] & ~sctag2_mb_type14[5] & (sctag2_mb_type14[4:0] == `LOAD_RQ);
wire sctag2_mb14_wris8_y = sctag2_mb_valid[14] & sctag2_mb_young[14] & sctag2_mb_type14[5] & sctag2_mb_type14[1];
wire sctag2_mb14_wris64_y = sctag2_mb_valid[14] & sctag2_mb_young[14] & sctag2_mb_type14[5] & sctag2_mb_type14[2];
wire sctag2_mb15_st_ny = sctag2_mb_valid[15] & ~sctag2_mb_young[15] & ~sctag2_mb_type15[5] & (sctag2_mb_type15[4:0] == `STORE_RQ);
wire sctag2_mb15_ld_ny = sctag2_mb_valid[15] & ~sctag2_mb_young[15] & ~sctag2_mb_type15[5] & (sctag2_mb_type15[4:0] == `LOAD_RQ);
wire sctag2_mb15_wris8_ny = sctag2_mb_valid[15] & ~sctag2_mb_young[15] & sctag2_mb_type15[5] & sctag2_mb_type15[1];
wire sctag2_mb15_wris64_ny = sctag2_mb_valid[15] & ~sctag2_mb_young[15] & sctag2_mb_type15[5] & sctag2_mb_type15[2];
wire sctag2_mb15_st_y = sctag2_mb_valid[15] & sctag2_mb_young[15] & ~sctag2_mb_type15[5] & (sctag2_mb_type15[4:0] == `STORE_RQ);
wire sctag2_mb15_ld_y = sctag2_mb_valid[15] & sctag2_mb_young[15] & ~sctag2_mb_type15[5] & (sctag2_mb_type15[4:0] == `LOAD_RQ);
wire sctag2_mb15_wris8_y = sctag2_mb_valid[15] & sctag2_mb_young[15] & sctag2_mb_type15[5] & sctag2_mb_type15[1];
wire sctag2_mb15_wris64_y = sctag2_mb_valid[15] & sctag2_mb_young[15] & sctag2_mb_type15[5] & sctag2_mb_type15[2];
wire [15:0] sctag3_mb_valid = `TOP_MEMORY.sctag3.mbctl.mb_valid[15:0];
wire [15:0] sctag3_mb_young = `TOP_MEMORY.sctag3.mbctl.mb_young[15:0];
//wire [3:0] sctag3_next_link_entry0 = `TOP_MEMORY.sctag3.mbctl.next_link_entry0[3:0];
//...
//wire [3:0] sctag3_next_link_entry15 = `TOP_MEMORY.sctag3.mbctl.next_link_entry15[3:0];
wire [155:0] sctag3_mb_data_array0 = `TOP_MEMORY.sctag3.mbdata.inq_ary[0];
wire [155:0] sctag3_mb_data_array1 = `TOP_MEMORY.sctag3.mbdata.inq_ary[1];
wire [155:0] sctag3_mb_data_array2 = `TOP_MEMORY.sctag3.mbdata.inq_ary[2];
wire [155:0] sctag3_mb_data_array3 = `TOP_MEMORY.sctag3.mbdata.inq_ary[3];
wire [155:0] sctag3_mb_data_array4 = `TOP_MEMORY.sctag3.mbdata.inq_ary[4];
wire [155:0] sctag3_mb_data_array5 = `TOP_MEMORY.sctag3.mbdata.inq_ary[5];
wire [155:0] sctag3_mb_data_array6 = `TOP_MEMORY.sctag3.mbdata.inq_ary[6];
wire [155:0] sctag3_mb_data_array7 = `TOP_MEMORY.sctag3.mbdata.inq_ary[7];
wire [155:0] sctag3_mb_data_array8 = `TOP_MEMORY.sctag3.mbdata.inq_ary[8];
wire [155:0] sctag3_mb_data_array9 = `TOP_MEMORY.sctag3.mbdata.inq_ary[9];
wire [155:0] sctag3_mb_data_array10 = `TOP_MEMORY.sctag3.mbdata.inq_ary[10];
wire [155:0] sctag3_mb_data_array11 = `TOP_MEMORY.sctag3.mbdata.inq_ary[11];
wire [155:0] sctag3_mb_data_array12 = `TOP_MEMORY.sctag3.mbdata.inq_ary[12];
wire [155:0] sctag3_mb_data_array13 = `TOP_MEMORY.sctag3.mbdata.inq_ary[13];
wire [155:0] sctag3_mb_data_array14 = `TOP_MEMORY.sctag3.mbdata.inq_ary[14];
wire [155:0] sctag3_mb_data_array15 = `TOP_MEMORY.sctag3.mbdata.inq_ary[15];
//-----------------------------------------------------------------------------------------------
// look at sctag.v for L2_RDMA_HI L2_RQTYP_HI L2_RQTYP_LO and L2_RSVD
// Based ont the equation: .mb_data_write_data({57'b0,mbdata_inst_tecc_c8...
//-----------------------------------------------------------------------------------------------
wire [5:0] sctag3_mb_type0 = {sctag3_mb_data_array0 [77], sctag3_mb_data_array0 [83:79]};
wire [5:0] sctag3_mb_type1 = {sctag3_mb_data_array1 [77], sctag3_mb_data_array1 [83:79]};
wire [5:0] sctag3_mb_type2 = {sctag3_mb_data_array2 [77], sctag3_mb_data_array2 [83:79]};
wire [5:0] sctag3_mb_type3 = {sctag3_mb_data_array3 [77], sctag3_mb_data_array3 [83:79]};
wire [5:0] sctag3_mb_type4 = {sctag3_mb_data_array4 [77], sctag3_mb_data_array4 [83:79]};
wire [5:0] sctag3_mb_type5 = {sctag3_mb_data_array5 [77], sctag3_mb_data_array5 [83:79]};
wire [5:0] sctag3_mb_type6 = {sctag3_mb_data_array6 [77], sctag3_mb_data_array6 [83:79]};
wire [5:0] sctag3_mb_type7 = {sctag3_mb_data_array7 [77], sctag3_mb_data_array7 [83:79]};
wire [5:0] sctag3_mb_type8 = {sctag3_mb_data_array8 [77], sctag3_mb_data_array8 [83:79]};
wire [5:0] sctag3_mb_type9 = {sctag3_mb_data_array9 [77], sctag3_mb_data_array9 [83:79]};
wire [5:0] sctag3_mb_type10 = {sctag3_mb_data_array10[77], sctag3_mb_data_array10[83:79]};
wire [5:0] sctag3_mb_type11 = {sctag3_mb_data_array11[77], sctag3_mb_data_array11[83:79]};
wire [5:0] sctag3_mb_type12 = {sctag3_mb_data_array12[77], sctag3_mb_data_array12[83:79]};
wire [5:0] sctag3_mb_type13 = {sctag3_mb_data_array13[77], sctag3_mb_data_array13[83:79]};
wire [5:0] sctag3_mb_type14 = {sctag3_mb_data_array14[77], sctag3_mb_data_array14[83:79]};
wire [5:0] sctag3_mb_type15 = {sctag3_mb_data_array15[77], sctag3_mb_data_array15[83:79]};
//--------------------------------------------------------------
// Start figuring out what the entries are.
// bit 5 says if this is a DMA type or normal type
//--------------------------------------------------------------
wire sctag3_mb0_st_ny = sctag3_mb_valid[0] & ~sctag3_mb_young[0] & ~sctag3_mb_type0[5] & (sctag3_mb_type0[4:0] == `STORE_RQ);
wire sctag3_mb0_ld_ny = sctag3_mb_valid[0] & ~sctag3_mb_young[0] & ~sctag3_mb_type0[5] & (sctag3_mb_type0[4:0] == `LOAD_RQ);
wire sctag3_mb0_wris8_ny = sctag3_mb_valid[0] & ~sctag3_mb_young[0] & sctag3_mb_type0[5] & sctag3_mb_type0[1];
wire sctag3_mb0_wris64_ny = sctag3_mb_valid[0] & ~sctag3_mb_young[0] & sctag3_mb_type0[5] & sctag3_mb_type0[2];
wire sctag3_mb0_st_y = sctag3_mb_valid[0] & sctag3_mb_young[0] & ~sctag3_mb_type0[5] & (sctag3_mb_type0[4:0] == `STORE_RQ);
wire sctag3_mb0_ld_y = sctag3_mb_valid[0] & sctag3_mb_young[0] & ~sctag3_mb_type0[5] & (sctag3_mb_type0[4:0] == `LOAD_RQ);
wire sctag3_mb0_wris8_y = sctag3_mb_valid[0] & sctag3_mb_young[0] & sctag3_mb_type0[5] & sctag3_mb_type0[1];
wire sctag3_mb0_wris64_y = sctag3_mb_valid[0] & sctag3_mb_young[0] & sctag3_mb_type0[5] & sctag3_mb_type0[2];
wire sctag3_mb1_st_ny = sctag3_mb_valid[1] & ~sctag3_mb_young[1] & ~sctag3_mb_type1[5] & (sctag3_mb_type1[4:0] == `STORE_RQ);
wire sctag3_mb1_ld_ny = sctag3_mb_valid[1] & ~sctag3_mb_young[1] & ~sctag3_mb_type1[5] & (sctag3_mb_type1[4:0] == `LOAD_RQ);
wire sctag3_mb1_wris8_ny = sctag3_mb_valid[1] & ~sctag3_mb_young[1] & sctag3_mb_type1[5] & sctag3_mb_type1[1];
wire sctag3_mb1_wris64_ny = sctag3_mb_valid[1] & ~sctag3_mb_young[1] & sctag3_mb_type1[5] & sctag3_mb_type1[2];
wire sctag3_mb1_st_y = sctag3_mb_valid[1] & sctag3_mb_young[1] & ~sctag3_mb_type1[5] & (sctag3_mb_type1[4:0] == `STORE_RQ);
wire sctag3_mb1_ld_y = sctag3_mb_valid[1] & sctag3_mb_young[1] & ~sctag3_mb_type1[5] & (sctag3_mb_type1[4:0] == `LOAD_RQ);
wire sctag3_mb1_wris8_y = sctag3_mb_valid[1] & sctag3_mb_young[1] & sctag3_mb_type1[5] & sctag3_mb_type1[1];
wire sctag3_mb1_wris64_y = sctag3_mb_valid[1] & sctag3_mb_young[1] & sctag3_mb_type1[5] & sctag3_mb_type1[2];
wire sctag3_mb2_st_ny = sctag3_mb_valid[2] & ~sctag3_mb_young[2] & ~sctag3_mb_type2[5] & (sctag3_mb_type2[4:0] == `STORE_RQ);
wire sctag3_mb2_ld_ny = sctag3_mb_valid[2] & ~sctag3_mb_young[2] & ~sctag3_mb_type2[5] & (sctag3_mb_type2[4:0] == `LOAD_RQ);
wire sctag3_mb2_wris8_ny = sctag3_mb_valid[2] & ~sctag3_mb_young[2] & sctag3_mb_type2[5] & sctag3_mb_type2[1];
wire sctag3_mb2_wris64_ny = sctag3_mb_valid[2] & ~sctag3_mb_young[2] & sctag3_mb_type2[5] & sctag3_mb_type2[2];
wire sctag3_mb2_st_y = sctag3_mb_valid[2] & sctag3_mb_young[2] & ~sctag3_mb_type2[5] & (sctag3_mb_type2[4:0] == `STORE_RQ);
wire sctag3_mb2_ld_y = sctag3_mb_valid[2] & sctag3_mb_young[2] & ~sctag3_mb_type2[5] & (sctag3_mb_type2[4:0] == `LOAD_RQ);
wire sctag3_mb2_wris8_y = sctag3_mb_valid[2] & sctag3_mb_young[2] & sctag3_mb_type2[5] & sctag3_mb_type2[1];
wire sctag3_mb2_wris64_y = sctag3_mb_valid[2] & sctag3_mb_young[2] & sctag3_mb_type2[5] & sctag3_mb_type2[2];
wire sctag3_mb3_st_ny = sctag3_mb_valid[3] & ~sctag3_mb_young[3] & ~sctag3_mb_type3[5] & (sctag3_mb_type3[4:0] == `STORE_RQ);
wire sctag3_mb3_ld_ny = sctag3_mb_valid[3] & ~sctag3_mb_young[3] & ~sctag3_mb_type3[5] & (sctag3_mb_type3[4:0] == `LOAD_RQ);
wire sctag3_mb3_wris8_ny = sctag3_mb_valid[3] & ~sctag3_mb_young[3] & sctag3_mb_type3[5] & sctag3_mb_type3[1];
wire sctag3_mb3_wris64_ny = sctag3_mb_valid[3] & ~sctag3_mb_young[3] & sctag3_mb_type3[5] & sctag3_mb_type3[2];
wire sctag3_mb3_st_y = sctag3_mb_valid[3] & sctag3_mb_young[3] & ~sctag3_mb_type3[5] & (sctag3_mb_type3[4:0] == `STORE_RQ);
wire sctag3_mb3_ld_y = sctag3_mb_valid[3] & sctag3_mb_young[3] & ~sctag3_mb_type3[5] & (sctag3_mb_type3[4:0] == `LOAD_RQ);
wire sctag3_mb3_wris8_y = sctag3_mb_valid[3] & sctag3_mb_young[3] & sctag3_mb_type3[5] & sctag3_mb_type3[1];
wire sctag3_mb3_wris64_y = sctag3_mb_valid[3] & sctag3_mb_young[3] & sctag3_mb_type3[5] & sctag3_mb_type3[2];
wire sctag3_mb4_st_ny = sctag3_mb_valid[4] & ~sctag3_mb_young[4] & ~sctag3_mb_type4[5] & (sctag3_mb_type4[4:0] == `STORE_RQ);
wire sctag3_mb4_ld_ny = sctag3_mb_valid[4] & ~sctag3_mb_young[4] & ~sctag3_mb_type4[5] & (sctag3_mb_type4[4:0] == `LOAD_RQ);
wire sctag3_mb4_wris8_ny = sctag3_mb_valid[4] & ~sctag3_mb_young[4] & sctag3_mb_type4[5] & sctag3_mb_type4[1];
wire sctag3_mb4_wris64_ny = sctag3_mb_valid[4] & ~sctag3_mb_young[4] & sctag3_mb_type4[5] & sctag3_mb_type4[2];
wire sctag3_mb4_st_y = sctag3_mb_valid[4] & sctag3_mb_young[4] & ~sctag3_mb_type4[5] & (sctag3_mb_type4[4:0] == `STORE_RQ);
wire sctag3_mb4_ld_y = sctag3_mb_valid[4] & sctag3_mb_young[4] & ~sctag3_mb_type4[5] & (sctag3_mb_type4[4:0] == `LOAD_RQ);
wire sctag3_mb4_wris8_y = sctag3_mb_valid[4] & sctag3_mb_young[4] & sctag3_mb_type4[5] & sctag3_mb_type4[1];
wire sctag3_mb4_wris64_y = sctag3_mb_valid[4] & sctag3_mb_young[4] & sctag3_mb_type4[5] & sctag3_mb_type4[2];
wire sctag3_mb5_st_ny = sctag3_mb_valid[5] & ~sctag3_mb_young[5] & ~sctag3_mb_type5[5] & (sctag3_mb_type5[4:0] == `STORE_RQ);
wire sctag3_mb5_ld_ny = sctag3_mb_valid[5] & ~sctag3_mb_young[5] & ~sctag3_mb_type5[5] & (sctag3_mb_type5[4:0] == `LOAD_RQ);
wire sctag3_mb5_wris8_ny = sctag3_mb_valid[5] & ~sctag3_mb_young[5] & sctag3_mb_type5[5] & sctag3_mb_type5[1];
wire sctag3_mb5_wris64_ny = sctag3_mb_valid[5] & ~sctag3_mb_young[5] & sctag3_mb_type5[5] & sctag3_mb_type5[2];
wire sctag3_mb5_st_y = sctag3_mb_valid[5] & sctag3_mb_young[5] & ~sctag3_mb_type5[5] & (sctag3_mb_type5[4:0] == `STORE_RQ);
wire sctag3_mb5_ld_y = sctag3_mb_valid[5] & sctag3_mb_young[5] & ~sctag3_mb_type5[5] & (sctag3_mb_type5[4:0] == `LOAD_RQ);
wire sctag3_mb5_wris8_y = sctag3_mb_valid[5] & sctag3_mb_young[5] & sctag3_mb_type5[5] & sctag3_mb_type5[1];
wire sctag3_mb5_wris64_y = sctag3_mb_valid[5] & sctag3_mb_young[5] & sctag3_mb_type5[5] & sctag3_mb_type5[2];
wire sctag3_mb6_st_ny = sctag3_mb_valid[6] & ~sctag3_mb_young[6] & ~sctag3_mb_type6[5] & (sctag3_mb_type6[4:0] == `STORE_RQ);
wire sctag3_mb6_ld_ny = sctag3_mb_valid[6] & ~sctag3_mb_young[6] & ~sctag3_mb_type6[5] & (sctag3_mb_type6[4:0] == `LOAD_RQ);
wire sctag3_mb6_wris8_ny = sctag3_mb_valid[6] & ~sctag3_mb_young[6] & sctag3_mb_type6[5] & sctag3_mb_type6[1];
wire sctag3_mb6_wris64_ny = sctag3_mb_valid[6] & ~sctag3_mb_young[6] & sctag3_mb_type6[5] & sctag3_mb_type6[2];
wire sctag3_mb6_st_y = sctag3_mb_valid[6] & sctag3_mb_young[6] & ~sctag3_mb_type6[5] & (sctag3_mb_type6[4:0] == `STORE_RQ);
wire sctag3_mb6_ld_y = sctag3_mb_valid[6] & sctag3_mb_young[6] & ~sctag3_mb_type6[5] & (sctag3_mb_type6[4:0] == `LOAD_RQ);
wire sctag3_mb6_wris8_y = sctag3_mb_valid[6] & sctag3_mb_young[6] & sctag3_mb_type6[5] & sctag3_mb_type6[1];
wire sctag3_mb6_wris64_y = sctag3_mb_valid[6] & sctag3_mb_young[6] & sctag3_mb_type6[5] & sctag3_mb_type6[2];
wire sctag3_mb7_st_ny = sctag3_mb_valid[7] & ~sctag3_mb_young[7] & ~sctag3_mb_type7[5] & (sctag3_mb_type7[4:0] == `STORE_RQ);
wire sctag3_mb7_ld_ny = sctag3_mb_valid[7] & ~sctag3_mb_young[7] & ~sctag3_mb_type7[5] & (sctag3_mb_type7[4:0] == `LOAD_RQ);
wire sctag3_mb7_wris8_ny = sctag3_mb_valid[7] & ~sctag3_mb_young[7] & sctag3_mb_type7[5] & sctag3_mb_type7[1];
wire sctag3_mb7_wris64_ny = sctag3_mb_valid[7] & ~sctag3_mb_young[7] & sctag3_mb_type7[5] & sctag3_mb_type7[2];
wire sctag3_mb7_st_y = sctag3_mb_valid[7] & sctag3_mb_young[7] & ~sctag3_mb_type7[5] & (sctag3_mb_type7[4:0] == `STORE_RQ);
wire sctag3_mb7_ld_y = sctag3_mb_valid[7] & sctag3_mb_young[7] & ~sctag3_mb_type7[5] & (sctag3_mb_type7[4:0] == `LOAD_RQ);
wire sctag3_mb7_wris8_y = sctag3_mb_valid[7] & sctag3_mb_young[7] & sctag3_mb_type7[5] & sctag3_mb_type7[1];
wire sctag3_mb7_wris64_y = sctag3_mb_valid[7] & sctag3_mb_young[7] & sctag3_mb_type7[5] & sctag3_mb_type7[2];
wire sctag3_mb8_st_ny = sctag3_mb_valid[8] & ~sctag3_mb_young[8] & ~sctag3_mb_type8[5] & (sctag3_mb_type8[4:0] == `STORE_RQ);
wire sctag3_mb8_ld_ny = sctag3_mb_valid[8] & ~sctag3_mb_young[8] & ~sctag3_mb_type8[5] & (sctag3_mb_type8[4:0] == `LOAD_RQ);
wire sctag3_mb8_wris8_ny = sctag3_mb_valid[8] & ~sctag3_mb_young[8] & sctag3_mb_type8[5] & sctag3_mb_type8[1];
wire sctag3_mb8_wris64_ny = sctag3_mb_valid[8] & ~sctag3_mb_young[8] & sctag3_mb_type8[5] & sctag3_mb_type8[2];
wire sctag3_mb8_st_y = sctag3_mb_valid[8] & sctag3_mb_young[8] & ~sctag3_mb_type8[5] & (sctag3_mb_type8[4:0] == `STORE_RQ);
wire sctag3_mb8_ld_y = sctag3_mb_valid[8] & sctag3_mb_young[8] & ~sctag3_mb_type8[5] & (sctag3_mb_type8[4:0] == `LOAD_RQ);
wire sctag3_mb8_wris8_y = sctag3_mb_valid[8] & sctag3_mb_young[8] & sctag3_mb_type8[5] & sctag3_mb_type8[1];
wire sctag3_mb8_wris64_y = sctag3_mb_valid[8] & sctag3_mb_young[8] & sctag3_mb_type8[5] & sctag3_mb_type8[2];
wire sctag3_mb9_st_ny = sctag3_mb_valid[9] & ~sctag3_mb_young[9] & ~sctag3_mb_type9[5] & (sctag3_mb_type9[4:0] == `STORE_RQ);
wire sctag3_mb9_ld_ny = sctag3_mb_valid[9] & ~sctag3_mb_young[9] & ~sctag3_mb_type9[5] & (sctag3_mb_type9[4:0] == `LOAD_RQ);
wire sctag3_mb9_wris8_ny = sctag3_mb_valid[9] & ~sctag3_mb_young[9] & sctag3_mb_type9[5] & sctag3_mb_type9[1];
wire sctag3_mb9_wris64_ny = sctag3_mb_valid[9] & ~sctag3_mb_young[9] & sctag3_mb_type9[5] & sctag3_mb_type9[2];
wire sctag3_mb9_st_y = sctag3_mb_valid[9] & sctag3_mb_young[9] & ~sctag3_mb_type9[5] & (sctag3_mb_type9[4:0] == `STORE_RQ);
wire sctag3_mb9_ld_y = sctag3_mb_valid[9] & sctag3_mb_young[9] & ~sctag3_mb_type9[5] & (sctag3_mb_type9[4:0] == `LOAD_RQ);
wire sctag3_mb9_wris8_y = sctag3_mb_valid[9] & sctag3_mb_young[9] & sctag3_mb_type9[5] & sctag3_mb_type9[1];
wire sctag3_mb9_wris64_y = sctag3_mb_valid[9] & sctag3_mb_young[9] & sctag3_mb_type9[5] & sctag3_mb_type9[2];
wire sctag3_mb10_st_ny = sctag3_mb_valid[10] & ~sctag3_mb_young[10] & ~sctag3_mb_type10[5] & (sctag3_mb_type10[4:0] == `STORE_RQ);
wire sctag3_mb10_ld_ny = sctag3_mb_valid[10] & ~sctag3_mb_young[10] & ~sctag3_mb_type10[5] & (sctag3_mb_type10[4:0] == `LOAD_RQ);
wire sctag3_mb10_wris8_ny = sctag3_mb_valid[10] & ~sctag3_mb_young[10] & sctag3_mb_type10[5] & sctag3_mb_type10[1];
wire sctag3_mb10_wris64_ny = sctag3_mb_valid[10] & ~sctag3_mb_young[10] & sctag3_mb_type10[5] & sctag3_mb_type10[2];
wire sctag3_mb10_st_y = sctag3_mb_valid[10] & sctag3_mb_young[10] & ~sctag3_mb_type10[5] & (sctag3_mb_type10[4:0] == `STORE_RQ);
wire sctag3_mb10_ld_y = sctag3_mb_valid[10] & sctag3_mb_young[10] & ~sctag3_mb_type10[5] & (sctag3_mb_type10[4:0] == `LOAD_RQ);
wire sctag3_mb10_wris8_y = sctag3_mb_valid[10] & sctag3_mb_young[10] & sctag3_mb_type10[5] & sctag3_mb_type10[1];
wire sctag3_mb10_wris64_y = sctag3_mb_valid[10] & sctag3_mb_young[10] & sctag3_mb_type10[5] & sctag3_mb_type10[2];
wire sctag3_mb11_st_ny = sctag3_mb_valid[11] & ~sctag3_mb_young[11] & ~sctag3_mb_type11[5] & (sctag3_mb_type11[4:0] == `STORE_RQ);
wire sctag3_mb11_ld_ny = sctag3_mb_valid[11] & ~sctag3_mb_young[11] & ~sctag3_mb_type11[5] & (sctag3_mb_type11[4:0] == `LOAD_RQ);
wire sctag3_mb11_wris8_ny = sctag3_mb_valid[11] & ~sctag3_mb_young[11] & sctag3_mb_type11[5] & sctag3_mb_type11[1];
wire sctag3_mb11_wris64_ny = sctag3_mb_valid[11] & ~sctag3_mb_young[11] & sctag3_mb_type11[5] & sctag3_mb_type11[2];
wire sctag3_mb11_st_y = sctag3_mb_valid[11] & sctag3_mb_young[11] & ~sctag3_mb_type11[5] & (sctag3_mb_type11[4:0] == `STORE_RQ);
wire sctag3_mb11_ld_y = sctag3_mb_valid[11] & sctag3_mb_young[11] & ~sctag3_mb_type11[5] & (sctag3_mb_type11[4:0] == `LOAD_RQ);
wire sctag3_mb11_wris8_y = sctag3_mb_valid[11] & sctag3_mb_young[11] & sctag3_mb_type11[5] & sctag3_mb_type11[1];
wire sctag3_mb11_wris64_y = sctag3_mb_valid[11] & sctag3_mb_young[11] & sctag3_mb_type11[5] & sctag3_mb_type11[2];
wire sctag3_mb12_st_ny = sctag3_mb_valid[12] & ~sctag3_mb_young[12] & ~sctag3_mb_type12[5] & (sctag3_mb_type12[4:0] == `STORE_RQ);
wire sctag3_mb12_ld_ny = sctag3_mb_valid[12] & ~sctag3_mb_young[12] & ~sctag3_mb_type12[5] & (sctag3_mb_type12[4:0] == `LOAD_RQ);
wire sctag3_mb12_wris8_ny = sctag3_mb_valid[12] & ~sctag3_mb_young[12] & sctag3_mb_type12[5] & sctag3_mb_type12[1];
wire sctag3_mb12_wris64_ny = sctag3_mb_valid[12] & ~sctag3_mb_young[12] & sctag3_mb_type12[5] & sctag3_mb_type12[2];
wire sctag3_mb12_st_y = sctag3_mb_valid[12] & sctag3_mb_young[12] & ~sctag3_mb_type12[5] & (sctag3_mb_type12[4:0] == `STORE_RQ);
wire sctag3_mb12_ld_y = sctag3_mb_valid[12] & sctag3_mb_young[12] & ~sctag3_mb_type12[5] & (sctag3_mb_type12[4:0] == `LOAD_RQ);
wire sctag3_mb12_wris8_y = sctag3_mb_valid[12] & sctag3_mb_young[12] & sctag3_mb_type12[5] & sctag3_mb_type12[1];
wire sctag3_mb12_wris64_y = sctag3_mb_valid[12] & sctag3_mb_young[12] & sctag3_mb_type12[5] & sctag3_mb_type12[2];
wire sctag3_mb13_st_ny = sctag3_mb_valid[13] & ~sctag3_mb_young[13] & ~sctag3_mb_type13[5] & (sctag3_mb_type13[4:0] == `STORE_RQ);
wire sctag3_mb13_ld_ny = sctag3_mb_valid[13] & ~sctag3_mb_young[13] & ~sctag3_mb_type13[5] & (sctag3_mb_type13[4:0] == `LOAD_RQ);
wire sctag3_mb13_wris8_ny = sctag3_mb_valid[13] & ~sctag3_mb_young[13] & sctag3_mb_type13[5] & sctag3_mb_type13[1];
wire sctag3_mb13_wris64_ny = sctag3_mb_valid[13] & ~sctag3_mb_young[13] & sctag3_mb_type13[5] & sctag3_mb_type13[2];
wire sctag3_mb13_st_y = sctag3_mb_valid[13] & sctag3_mb_young[13] & ~sctag3_mb_type13[5] & (sctag3_mb_type13[4:0] == `STORE_RQ);
wire sctag3_mb13_ld_y = sctag3_mb_valid[13] & sctag3_mb_young[13] & ~sctag3_mb_type13[5] & (sctag3_mb_type13[4:0] == `LOAD_RQ);
wire sctag3_mb13_wris8_y = sctag3_mb_valid[13] & sctag3_mb_young[13] & sctag3_mb_type13[5] & sctag3_mb_type13[1];
wire sctag3_mb13_wris64_y = sctag3_mb_valid[13] & sctag3_mb_young[13] & sctag3_mb_type13[5] & sctag3_mb_type13[2];
wire sctag3_mb14_st_ny = sctag3_mb_valid[14] & ~sctag3_mb_young[14] & ~sctag3_mb_type14[5] & (sctag3_mb_type14[4:0] == `STORE_RQ);
wire sctag3_mb14_ld_ny = sctag3_mb_valid[14] & ~sctag3_mb_young[14] & ~sctag3_mb_type14[5] & (sctag3_mb_type14[4:0] == `LOAD_RQ);
wire sctag3_mb14_wris8_ny = sctag3_mb_valid[14] & ~sctag3_mb_young[14] & sctag3_mb_type14[5] & sctag3_mb_type14[1];
wire sctag3_mb14_wris64_ny = sctag3_mb_valid[14] & ~sctag3_mb_young[14] & sctag3_mb_type14[5] & sctag3_mb_type14[2];
wire sctag3_mb14_st_y = sctag3_mb_valid[14] & sctag3_mb_young[14] & ~sctag3_mb_type14[5] & (sctag3_mb_type14[4:0] == `STORE_RQ);
wire sctag3_mb14_ld_y = sctag3_mb_valid[14] & sctag3_mb_young[14] & ~sctag3_mb_type14[5] & (sctag3_mb_type14[4:0] == `LOAD_RQ);
wire sctag3_mb14_wris8_y = sctag3_mb_valid[14] & sctag3_mb_young[14] & sctag3_mb_type14[5] & sctag3_mb_type14[1];
wire sctag3_mb14_wris64_y = sctag3_mb_valid[14] & sctag3_mb_young[14] & sctag3_mb_type14[5] & sctag3_mb_type14[2];
wire sctag3_mb15_st_ny = sctag3_mb_valid[15] & ~sctag3_mb_young[15] & ~sctag3_mb_type15[5] & (sctag3_mb_type15[4:0] == `STORE_RQ);
wire sctag3_mb15_ld_ny = sctag3_mb_valid[15] & ~sctag3_mb_young[15] & ~sctag3_mb_type15[5] & (sctag3_mb_type15[4:0] == `LOAD_RQ);
wire sctag3_mb15_wris8_ny = sctag3_mb_valid[15] & ~sctag3_mb_young[15] & sctag3_mb_type15[5] & sctag3_mb_type15[1];
wire sctag3_mb15_wris64_ny = sctag3_mb_valid[15] & ~sctag3_mb_young[15] & sctag3_mb_type15[5] & sctag3_mb_type15[2];
wire sctag3_mb15_st_y = sctag3_mb_valid[15] & sctag3_mb_young[15] & ~sctag3_mb_type15[5] & (sctag3_mb_type15[4:0] == `STORE_RQ);
wire sctag3_mb15_ld_y = sctag3_mb_valid[15] & sctag3_mb_young[15] & ~sctag3_mb_type15[5] & (sctag3_mb_type15[4:0] == `LOAD_RQ);
wire sctag3_mb15_wris8_y = sctag3_mb_valid[15] & sctag3_mb_young[15] & sctag3_mb_type15[5] & sctag3_mb_type15[1];
wire sctag3_mb15_wris64_y = sctag3_mb_valid[15] & sctag3_mb_young[15] & sctag3_mb_type15[5] & sctag3_mb_type15[2];
//==========================================================================================
// L2 pipeline stuff. Detecting miss/hit combinations of stores.
//==========================================================================================
wire [`L2_FBF:`L2_SZ_LO] sctag0_inst_c2 = `TOP_MEMORY.sctag0.arbdecdp.arbdp_inst_c2;
wire [39:0] sctag0_addr_c2 = `TOP_MEMORY.sctag0.arbaddrdp.arbdp_addr_c2;
wire sctag0_tagctl_hit_c2 = `TOP_MEMORY.sctag0.tagctl.tagctl_hit_c2;
wire sctag0_inst_vld_c2 = `TOP_MEMORY.sctag0.arbctl_inst_vld_c2;
wire sctag0_mbctl_tagctl_hit_unqual_c2 = `TOP_MEMORY.sctag0.mbctl_tagctl_hit_unqual_c2;
wire sctag0_l2_enable = ~`TOP_MEMORY.sctag0.l2_bypass_mode_on;
wire sctag0_l2_dir_map_on = `TOP_MEMORY.sctag0.l2_dir_map_on;
// A store which does not hit in the L2 miss buffer
//-------------------------------------------------
wire store0 = (sctag0_inst_c2[`L2_RQTYP_HI:`L2_RQTYP_LO] == `STORE_RQ) & ~sctag0_inst_c2[`L2_RSVD] |
sctag0_inst_vld_c2 & ~sctag0_mbctl_tagctl_hit_unqual_c2;
wire wris80 = sctag0_inst_c2[`L2_RQTYP_LO + 1] & sctag0_inst_c2[`L2_RSVD] &
sctag0_inst_vld_c2 & ~sctag0_mbctl_tagctl_hit_unqual_c2;
wire wris640= sctag0_inst_c2[`L2_RQTYP_LO + 2] & sctag0_inst_c2[`L2_RSVD] &
sctag0_inst_vld_c2 & ~sctag0_mbctl_tagctl_hit_unqual_c2;
wire load0 = (sctag0_inst_c2[`L2_RQTYP_HI:`L2_RQTYP_LO] == `LOAD_RQ) & ~sctag0_inst_c2[`L2_RSVD] &
sctag0_inst_vld_c2 & ~sctag0_mbctl_tagctl_hit_unqual_c2;
wire ldd0 = sctag0_inst_c2[`L2_RQTYP_LO] & sctag0_inst_c2[`L2_RSVD] &
sctag0_inst_vld_c2 & ~sctag0_mbctl_tagctl_hit_unqual_c2;
wire [`L2_FBF:`L2_SZ_LO] sctag1_inst_c2 = `TOP_MEMORY.sctag1.arbdecdp.arbdp_inst_c2;
wire [39:0] sctag1_addr_c2 = `TOP_MEMORY.sctag1.arbaddrdp.arbdp_addr_c2;
wire sctag1_tagctl_hit_c2 = `TOP_MEMORY.sctag1.tagctl.tagctl_hit_c2;
wire sctag1_inst_vld_c2 = `TOP_MEMORY.sctag1.arbctl_inst_vld_c2;
wire sctag1_mbctl_tagctl_hit_unqual_c2 = `TOP_MEMORY.sctag1.mbctl_tagctl_hit_unqual_c2;
wire sctag1_l2_enable = ~`TOP_MEMORY.sctag1.l2_bypass_mode_on;
wire sctag1_l2_dir_map_on = `TOP_MEMORY.sctag1.l2_dir_map_on;
// A store which does not hit in the L2 miss buffer
//-------------------------------------------------
wire store1 = (sctag1_inst_c2[`L2_RQTYP_HI:`L2_RQTYP_LO] == `STORE_RQ) & ~sctag1_inst_c2[`L2_RSVD] |
sctag1_inst_vld_c2 & ~sctag1_mbctl_tagctl_hit_unqual_c2;
wire wris81 = sctag1_inst_c2[`L2_RQTYP_LO + 1] & sctag1_inst_c2[`L2_RSVD] &
sctag1_inst_vld_c2 & ~sctag1_mbctl_tagctl_hit_unqual_c2;
wire wris641= sctag1_inst_c2[`L2_RQTYP_LO + 2] & sctag1_inst_c2[`L2_RSVD] &
sctag1_inst_vld_c2 & ~sctag1_mbctl_tagctl_hit_unqual_c2;
wire load1 = (sctag1_inst_c2[`L2_RQTYP_HI:`L2_RQTYP_LO] == `LOAD_RQ) & ~sctag1_inst_c2[`L2_RSVD] &
sctag1_inst_vld_c2 & ~sctag1_mbctl_tagctl_hit_unqual_c2;
wire ldd1 = sctag1_inst_c2[`L2_RQTYP_LO] & sctag1_inst_c2[`L2_RSVD] &
sctag1_inst_vld_c2 & ~sctag1_mbctl_tagctl_hit_unqual_c2;
wire [`L2_FBF:`L2_SZ_LO] sctag2_inst_c2 = `TOP_MEMORY.sctag2.arbdecdp.arbdp_inst_c2;
wire [39:0] sctag2_addr_c2 = `TOP_MEMORY.sctag2.arbaddrdp.arbdp_addr_c2;
wire sctag2_tagctl_hit_c2 = `TOP_MEMORY.sctag2.tagctl.tagctl_hit_c2;
wire sctag2_inst_vld_c2 = `TOP_MEMORY.sctag2.arbctl_inst_vld_c2;
wire sctag2_mbctl_tagctl_hit_unqual_c2 = `TOP_MEMORY.sctag2.mbctl_tagctl_hit_unqual_c2;
wire sctag2_l2_enable = ~`TOP_MEMORY.sctag2.l2_bypass_mode_on;
wire sctag2_l2_dir_map_on = `TOP_MEMORY.sctag2.l2_dir_map_on;
// A store which does not hit in the L2 miss buffer
//-------------------------------------------------
wire store2 = (sctag2_inst_c2[`L2_RQTYP_HI:`L2_RQTYP_LO] == `STORE_RQ) & ~sctag2_inst_c2[`L2_RSVD] |
sctag2_inst_vld_c2 & ~sctag2_mbctl_tagctl_hit_unqual_c2;
wire wris82 = sctag2_inst_c2[`L2_RQTYP_LO + 1] & sctag2_inst_c2[`L2_RSVD] &
sctag2_inst_vld_c2 & ~sctag2_mbctl_tagctl_hit_unqual_c2;
wire wris642= sctag2_inst_c2[`L2_RQTYP_LO + 2] & sctag2_inst_c2[`L2_RSVD] &
sctag2_inst_vld_c2 & ~sctag2_mbctl_tagctl_hit_unqual_c2;
wire load2 = (sctag2_inst_c2[`L2_RQTYP_HI:`L2_RQTYP_LO] == `LOAD_RQ) & ~sctag2_inst_c2[`L2_RSVD] &
sctag2_inst_vld_c2 & ~sctag2_mbctl_tagctl_hit_unqual_c2;
wire ldd2 = sctag2_inst_c2[`L2_RQTYP_LO] & sctag2_inst_c2[`L2_RSVD] &
sctag2_inst_vld_c2 & ~sctag2_mbctl_tagctl_hit_unqual_c2;
wire [`L2_FBF:`L2_SZ_LO] sctag3_inst_c2 = `TOP_MEMORY.sctag3.arbdecdp.arbdp_inst_c2;
wire [39:0] sctag3_addr_c2 = `TOP_MEMORY.sctag3.arbaddrdp.arbdp_addr_c2;
wire sctag3_tagctl_hit_c2 = `TOP_MEMORY.sctag3.tagctl.tagctl_hit_c2;
wire sctag3_inst_vld_c2 = `TOP_MEMORY.sctag3.arbctl_inst_vld_c2;
wire sctag3_mbctl_tagctl_hit_unqual_c2 = `TOP_MEMORY.sctag3.mbctl_tagctl_hit_unqual_c2;
wire sctag3_l2_enable = ~`TOP_MEMORY.sctag3.l2_bypass_mode_on;
wire sctag3_l2_dir_map_on = `TOP_MEMORY.sctag3.l2_dir_map_on;
// A store which does not hit in the L2 miss buffer
//-------------------------------------------------
wire store3 = (sctag3_inst_c2[`L2_RQTYP_HI:`L2_RQTYP_LO] == `STORE_RQ) & ~sctag3_inst_c2[`L2_RSVD] |
sctag3_inst_vld_c2 & ~sctag3_mbctl_tagctl_hit_unqual_c2;
wire wris83 = sctag3_inst_c2[`L2_RQTYP_LO + 1] & sctag3_inst_c2[`L2_RSVD] &
sctag3_inst_vld_c2 & ~sctag3_mbctl_tagctl_hit_unqual_c2;
wire wris643= sctag3_inst_c2[`L2_RQTYP_LO + 2] & sctag3_inst_c2[`L2_RSVD] &
sctag3_inst_vld_c2 & ~sctag3_mbctl_tagctl_hit_unqual_c2;
wire load3 = (sctag3_inst_c2[`L2_RQTYP_HI:`L2_RQTYP_LO] == `LOAD_RQ) & ~sctag3_inst_c2[`L2_RSVD] &
sctag3_inst_vld_c2 & ~sctag3_mbctl_tagctl_hit_unqual_c2;
wire ldd3 = sctag3_inst_c2[`L2_RQTYP_LO] & sctag3_inst_c2[`L2_RSVD] &
sctag3_inst_vld_c2 & ~sctag3_mbctl_tagctl_hit_unqual_c2;
wire[3:0] l2_enable = {sctag3_l2_enable, sctag2_l2_enable, sctag1_l2_enable, sctag0_l2_enable};
always @(l2_enable)
$display("%0d tso_mon: l2_enable changed to %x", $time, l2_enable);
wire[3:0] l2_dir_map_on = {sctag3_l2_dir_map_on, sctag2_l2_dir_map_on, sctag1_l2_dir_map_on, sctag0_l2_dir_map_on};
always @(l2_dir_map_on)
$display("%0d tso_mon: l2_dir_map_on changed to %x", $time, l2_dir_map_on);
//==========================================================================================
// Some FSM-s for coverage - NOT very important
`define L2_FSM_IDLE 4'b0000
`define L2_FSM_ST1 4'b0001
`define L2_FSM_ST2M 4'b0010
`define L2_FSM_LD1M 4'b0011
`define L2_FSM_LD2M 4'b0100
`define L2_FSM_ST2H 4'b0101
`define L2_FSM_LD1H 4'b0110
`define L2_FSM_LD2H 4'b0111
//==========================================================================================
reg [3:0] l2_fsm1;
integer l2_fsm1_counter;
reg [39:8] l2_fsm1_addr1, l2_fsm1_addr2;
reg [4:0] l2_fsm1_id1, l2_fsm1_id2;
always @(posedge clk)
begin
if(~rst_l)
l2_fsm1_counter <= 0;
else if(l2_fsm1 == `L2_FSM_IDLE)
l2_fsm1_counter <= 0;
else
l2_fsm1_counter <= l2_fsm1_counter + 1;
if(~rst_l)
begin
l2_fsm1 <= `L2_FSM_IDLE;
end
// A first store not issued from miss buffer
//-------------------------------------------------------------------------------
else if(store0 & ~sctag0_inst_c2[`L2_MBF] & ~sctag0_tagctl_hit_c2 & (l2_fsm1 == `L2_FSM_IDLE))
begin
l2_fsm1_addr1 <= sctag0_addr_c2[39:8];
l2_fsm1_id1 <= sctag0_inst_c2[`L2_CPUID_HI:`L2_TID_LO];
l2_fsm1 <= `L2_FSM_ST1;
end
else if(store1 & ~sctag1_inst_c2[`L2_MBF] & ~sctag1_tagctl_hit_c2 & (l2_fsm1 == `L2_FSM_IDLE))
begin
l2_fsm1_addr1 <= sctag1_addr_c2[39:8];
l2_fsm1_id1 <= sctag1_inst_c2[`L2_CPUID_HI:`L2_TID_LO];
l2_fsm1 <= `L2_FSM_ST1;
end
else if(store2 & ~sctag2_inst_c2[`L2_MBF] & ~sctag2_tagctl_hit_c2 & (l2_fsm1 == `L2_FSM_IDLE))
begin
l2_fsm1_addr1 <= sctag2_addr_c2[39:8];
l2_fsm1_id1 <= sctag2_inst_c2[`L2_CPUID_HI:`L2_TID_LO];
l2_fsm1 <= `L2_FSM_ST1;
end
else if(store3 & ~sctag3_inst_c2[`L2_MBF] & ~sctag3_tagctl_hit_c2 & (l2_fsm1 == `L2_FSM_IDLE))
begin
l2_fsm1_addr1 <= sctag3_addr_c2[39:8];
l2_fsm1_id1 <= sctag3_inst_c2[`L2_CPUID_HI:`L2_TID_LO];
l2_fsm1 <= `L2_FSM_ST1;
end
// The second store - may be a miss or a hit
//-------------------------------------------------------------------------------
else if(store0 & ~sctag0_inst_c2[`L2_MBF] & (l2_fsm1 == `L2_FSM_ST1))
begin
l2_fsm1_addr2 <= sctag0_addr_c2[39:8];
l2_fsm1_id2 <= sctag0_inst_c2[`L2_CPUID_HI:`L2_TID_LO];
l2_fsm1 <= sctag0_tagctl_hit_c2 ? `L2_FSM_ST2H : `L2_FSM_ST2M;
end
else if(store1 & ~sctag1_inst_c2[`L2_MBF] & (l2_fsm1 == `L2_FSM_ST1))
begin
l2_fsm1_addr2 <= sctag1_addr_c2[39:8];
l2_fsm1_id2 <= sctag1_inst_c2[`L2_CPUID_HI:`L2_TID_LO];
l2_fsm1 <= sctag1_tagctl_hit_c2 ? `L2_FSM_ST2H : `L2_FSM_ST2M;
end
else if(store2 & ~sctag2_inst_c2[`L2_MBF] & (l2_fsm1 == `L2_FSM_ST1))
begin
l2_fsm1_addr2 <= sctag2_addr_c2[39:8];
l2_fsm1_id2 <= sctag2_inst_c2[`L2_CPUID_HI:`L2_TID_LO];
l2_fsm1 <= sctag2_tagctl_hit_c2 ? `L2_FSM_ST2H : `L2_FSM_ST2M;
end
else if(store3 & ~sctag3_inst_c2[`L2_MBF] & (l2_fsm1 == `L2_FSM_ST1))
begin
l2_fsm1_addr2 <= sctag3_addr_c2[39:8];
l2_fsm1_id2 <= sctag3_inst_c2[`L2_CPUID_HI:`L2_TID_LO];
l2_fsm1 <= sctag3_tagctl_hit_c2 ? `L2_FSM_ST2H : `L2_FSM_ST2M;
end
// A load to address2 is a hit or returned already
// the load is eaither not starting from the L2 MB and is a hit
// or is starting from the L2MB.
//-------------------------------------------------------------------------------
else if(load0 & (~sctag0_inst_c2[`L2_MBF] & sctag0_tagctl_hit_c2 |
~sctag0_inst_c2[`L2_EVICT] & sctag0_inst_c2[`L2_MBF]) &
((l2_fsm1 == `L2_FSM_ST2M) | (l2_fsm1 == `L2_FSM_ST2H)) &
(sctag0_addr_c2[39:8] == l2_fsm1_addr2[39:8]))
begin
if(l2_fsm1 == `L2_FSM_ST2M) l2_fsm1 <= `L2_FSM_LD1M;
else l2_fsm1 <= `L2_FSM_LD1H;
end
else if(load1 & (~sctag1_inst_c2[`L2_MBF] & sctag1_tagctl_hit_c2 |
~sctag1_inst_c2[`L2_EVICT] & sctag1_inst_c2[`L2_MBF]) &
((l2_fsm1 == `L2_FSM_ST2M) | (l2_fsm1 == `L2_FSM_ST2H)) &
(sctag1_addr_c2[39:8] == l2_fsm1_addr2[39:8]))
begin
if(l2_fsm1 == `L2_FSM_ST2M) l2_fsm1 <= `L2_FSM_LD1M;
else l2_fsm1 <= `L2_FSM_LD1H;
end
else if(load2 & (~sctag2_inst_c2[`L2_MBF] & sctag2_tagctl_hit_c2 |
~sctag2_inst_c2[`L2_EVICT] & sctag2_inst_c2[`L2_MBF]) &
((l2_fsm1 == `L2_FSM_ST2M) | (l2_fsm1 == `L2_FSM_ST2H)) &
(sctag2_addr_c2[39:8] == l2_fsm1_addr2[39:8]))
begin
if(l2_fsm1 == `L2_FSM_ST2M) l2_fsm1 <= `L2_FSM_LD1M;
else l2_fsm1 <= `L2_FSM_LD1H;
end
else if(load3 & (~sctag3_inst_c2[`L2_MBF] & sctag3_tagctl_hit_c2 |
~sctag3_inst_c2[`L2_EVICT] & sctag3_inst_c2[`L2_MBF]) &
((l2_fsm1 == `L2_FSM_ST2M) | (l2_fsm1 == `L2_FSM_ST2H)) &
(sctag3_addr_c2[39:8] == l2_fsm1_addr2[39:8]))
begin
if(l2_fsm1 == `L2_FSM_ST2M) l2_fsm1 <= `L2_FSM_LD1M;
else l2_fsm1 <= `L2_FSM_LD1H;
end
// A load to address1 is a miss.
//-------------------------------------------------------------------------------
else if(load0 & ~sctag0_tagctl_hit_c2 &
((l2_fsm1 == `L2_FSM_LD1M) | (l2_fsm1 == `L2_FSM_LD1H)) &
(sctag0_addr_c2[39:8] == l2_fsm1_addr1))
begin
if(l2_fsm1 == `L2_FSM_LD1M) l2_fsm1 <= `L2_FSM_LD2M;
else l2_fsm1 <= `L2_FSM_LD2H;
end
else if(load1 & ~sctag1_tagctl_hit_c2 &
((l2_fsm1 == `L2_FSM_LD1M) | (l2_fsm1 == `L2_FSM_LD1H)) &
(sctag1_addr_c2[39:8] == l2_fsm1_addr1))
begin
if(l2_fsm1 == `L2_FSM_LD1M) l2_fsm1 <= `L2_FSM_LD2M;
else l2_fsm1 <= `L2_FSM_LD2H;
end
else if(load2 & ~sctag2_tagctl_hit_c2 &
((l2_fsm1 == `L2_FSM_LD1M) | (l2_fsm1 == `L2_FSM_LD1H)) &
(sctag2_addr_c2[39:8] == l2_fsm1_addr1))
begin
if(l2_fsm1 == `L2_FSM_LD1M) l2_fsm1 <= `L2_FSM_LD2M;
else l2_fsm1 <= `L2_FSM_LD2H;
end
else if(load3 & ~sctag3_tagctl_hit_c2 &
((l2_fsm1 == `L2_FSM_LD1M) | (l2_fsm1 == `L2_FSM_LD1H)) &
(sctag3_addr_c2[39:8] == l2_fsm1_addr1))
begin
if(l2_fsm1 == `L2_FSM_LD1M) l2_fsm1 <= `L2_FSM_LD2M;
else l2_fsm1 <= `L2_FSM_LD2H;
end
//-------------------------------------------
// returning the FSM to idle stuff
// when the original store does the last pass.
//-------------------------------------------
else if(store0 & (sctag0_addr_c2[39:8] == l2_fsm1_addr1[39:8]) &
(sctag0_inst_c2[`L2_CPUID_HI:`L2_TID_LO] == l2_fsm1_id1) &
~sctag0_inst_c2[`L2_EVICT] & sctag0_inst_c2[`L2_MBF])
l2_fsm1 <= `L2_FSM_IDLE;
else if(store1 & (sctag1_addr_c2[39:8] == l2_fsm1_addr1[39:8]) &
(sctag1_inst_c2[`L2_CPUID_HI:`L2_TID_LO] == l2_fsm1_id1) &
~sctag1_inst_c2[`L2_EVICT] & sctag1_inst_c2[`L2_MBF])
l2_fsm1 <= `L2_FSM_IDLE;
else if(store2 & (sctag2_addr_c2[39:8] == l2_fsm1_addr1[39:8]) &
(sctag2_inst_c2[`L2_CPUID_HI:`L2_TID_LO] == l2_fsm1_id1) &
~sctag2_inst_c2[`L2_EVICT] & sctag2_inst_c2[`L2_MBF])
l2_fsm1 <= `L2_FSM_IDLE;
else if(store3 & (sctag3_addr_c2[39:8] == l2_fsm1_addr1[39:8]) &
(sctag3_inst_c2[`L2_CPUID_HI:`L2_TID_LO] == l2_fsm1_id1) &
~sctag3_inst_c2[`L2_EVICT] & sctag3_inst_c2[`L2_MBF])
l2_fsm1 <= `L2_FSM_IDLE;
else if(l2_fsm1_counter > 1000)
l2_fsm1 <= `L2_FSM_IDLE;
end
//==========================================================================================
reg [3:0] l2_fsm2;
integer l2_fsm2_counter;
reg [39:8] l2_fsm2_addr1, l2_fsm2_addr2;
reg [4:0] l2_fsm2_id1, l2_fsm2_id2;
always @(posedge clk)
begin
if(~rst_l)
l2_fsm2_counter <= 0;
else if(l2_fsm2 == `L2_FSM_IDLE)
l2_fsm2_counter <= 0;
else
l2_fsm2_counter <= l2_fsm2_counter + 1;
if(~rst_l)
begin
l2_fsm2 <= `L2_FSM_IDLE;
end
// A first store or wris8 not issued from miss buffer.
//-------------------------------------------------------------------------------
else if(wris640 & ~sctag0_inst_c2[`L2_MBF] & ~sctag0_tagctl_hit_c2 & (l2_fsm2 == `L2_FSM_IDLE))
begin
l2_fsm2_addr1 <= sctag0_addr_c2[39:8];
l2_fsm2_id1 <= sctag0_inst_c2[`L2_CPUID_HI:`L2_TID_LO];
l2_fsm2 <= `L2_FSM_ST1;
end
else if(wris641 & ~sctag1_inst_c2[`L2_MBF] & ~sctag1_tagctl_hit_c2 & (l2_fsm2 == `L2_FSM_IDLE))
begin
l2_fsm2_addr1 <= sctag1_addr_c2[39:8];
l2_fsm2_id1 <= sctag1_inst_c2[`L2_CPUID_HI:`L2_TID_LO];
l2_fsm2 <= `L2_FSM_ST1;
end
else if(wris642 & ~sctag2_inst_c2[`L2_MBF] & ~sctag2_tagctl_hit_c2 & (l2_fsm2 == `L2_FSM_IDLE))
begin
l2_fsm2_addr1 <= sctag2_addr_c2[39:8];
l2_fsm2_id1 <= sctag2_inst_c2[`L2_CPUID_HI:`L2_TID_LO];
l2_fsm2 <= `L2_FSM_ST1;
end
else if(wris643 & ~sctag3_inst_c2[`L2_MBF] & ~sctag3_tagctl_hit_c2 & (l2_fsm2 == `L2_FSM_IDLE))
begin
l2_fsm2_addr1 <= sctag3_addr_c2[39:8];
l2_fsm2_id1 <= sctag3_inst_c2[`L2_CPUID_HI:`L2_TID_LO];
l2_fsm2 <= `L2_FSM_ST1;
end
// The second store - may be a miss or a hit
//-------------------------------------------------------------------------------
else if(wris640 & ~sctag0_inst_c2[`L2_MBF] & (l2_fsm2 == `L2_FSM_ST1))
begin
l2_fsm2_addr2 <= sctag0_addr_c2[39:8];
l2_fsm2_id2 <= sctag0_inst_c2[`L2_CPUID_HI:`L2_TID_LO];
l2_fsm2 <= sctag0_tagctl_hit_c2 ? `L2_FSM_ST2H : `L2_FSM_ST2M;
end
else if(wris641 & ~sctag1_inst_c2[`L2_MBF] & (l2_fsm2 == `L2_FSM_ST1))
begin
l2_fsm2_addr2 <= sctag1_addr_c2[39:8];
l2_fsm2_id2 <= sctag1_inst_c2[`L2_CPUID_HI:`L2_TID_LO];
l2_fsm2 <= sctag1_tagctl_hit_c2 ? `L2_FSM_ST2H : `L2_FSM_ST2M;
end
else if(wris642 & ~sctag2_inst_c2[`L2_MBF] & (l2_fsm2 == `L2_FSM_ST1))
begin
l2_fsm2_addr2 <= sctag2_addr_c2[39:8];
l2_fsm2_id2 <= sctag2_inst_c2[`L2_CPUID_HI:`L2_TID_LO];
l2_fsm2 <= sctag2_tagctl_hit_c2 ? `L2_FSM_ST2H : `L2_FSM_ST2M;
end
else if(wris643 & ~sctag3_inst_c2[`L2_MBF] & (l2_fsm2 == `L2_FSM_ST1))
begin
l2_fsm2_addr2 <= sctag3_addr_c2[39:8];
l2_fsm2_id2 <= sctag3_inst_c2[`L2_CPUID_HI:`L2_TID_LO];
l2_fsm2 <= sctag3_tagctl_hit_c2 ? `L2_FSM_ST2H : `L2_FSM_ST2M;
end
// A load to address2 is a hit or returned already
// the load is eaither not starting from the L2 MB and is a hit
// or is starting from the L2MB.
//-------------------------------------------------------------------------------
else if(load0 & (~sctag0_inst_c2[`L2_MBF] & sctag0_tagctl_hit_c2 |
~sctag0_inst_c2[`L2_EVICT] & sctag0_inst_c2[`L2_MBF]) &
((l2_fsm2 == `L2_FSM_ST2M) | (l2_fsm2 == `L2_FSM_ST2H)) &
(sctag0_addr_c2[39:8] == l2_fsm2_addr2[39:8]))
begin
if(l2_fsm2 == `L2_FSM_ST2M) l2_fsm2 <= `L2_FSM_LD1M;
else l2_fsm2 <= `L2_FSM_LD1H;
end
else if(load1 & (~sctag1_inst_c2[`L2_MBF] & sctag1_tagctl_hit_c2 |
~sctag1_inst_c2[`L2_EVICT] & sctag1_inst_c2[`L2_MBF]) &
((l2_fsm2 == `L2_FSM_ST2M) | (l2_fsm2 == `L2_FSM_ST2H)) &
(sctag1_addr_c2[39:8] == l2_fsm2_addr2[39:8]))
begin
if(l2_fsm2 == `L2_FSM_ST2M) l2_fsm2 <= `L2_FSM_LD1M;
else l2_fsm2 <= `L2_FSM_LD1H;
end
else if(load2 & (~sctag2_inst_c2[`L2_MBF] & sctag2_tagctl_hit_c2 |
~sctag2_inst_c2[`L2_EVICT] & sctag2_inst_c2[`L2_MBF]) &
((l2_fsm2 == `L2_FSM_ST2M) | (l2_fsm2 == `L2_FSM_ST2H)) &
(sctag2_addr_c2[39:8] == l2_fsm2_addr2[39:8]))
begin
if(l2_fsm2 == `L2_FSM_ST2M) l2_fsm2 <= `L2_FSM_LD1M;
else l2_fsm2 <= `L2_FSM_LD1H;
end
else if(load3 & (~sctag3_inst_c2[`L2_MBF] & sctag3_tagctl_hit_c2 |
~sctag3_inst_c2[`L2_EVICT] & sctag3_inst_c2[`L2_MBF]) &
((l2_fsm2 == `L2_FSM_ST2M) | (l2_fsm2 == `L2_FSM_ST2H)) &
(sctag3_addr_c2[39:8] == l2_fsm2_addr2[39:8]))
begin
if(l2_fsm2 == `L2_FSM_ST2M) l2_fsm2 <= `L2_FSM_LD1M;
else l2_fsm2 <= `L2_FSM_LD1H;
end
// A load to address1 is a miss.
//-------------------------------------------------------------------------------
else if(load0 & ~sctag0_tagctl_hit_c2 &
((l2_fsm2 == `L2_FSM_LD1M) | (l2_fsm2 == `L2_FSM_LD1H)) &
(sctag0_addr_c2[39:8] == l2_fsm2_addr1))
begin
if(l2_fsm2 == `L2_FSM_LD1M) l2_fsm2 <= `L2_FSM_LD2M;
else l2_fsm2 <= `L2_FSM_LD2H;
end
else if(load1 & ~sctag1_tagctl_hit_c2 &
((l2_fsm2 == `L2_FSM_LD1M) | (l2_fsm2 == `L2_FSM_LD1H)) &
(sctag1_addr_c2[39:8] == l2_fsm2_addr1))
begin
if(l2_fsm2 == `L2_FSM_LD1M) l2_fsm2 <= `L2_FSM_LD2M;
else l2_fsm2 <= `L2_FSM_LD2H;
end
else if(load2 & ~sctag2_tagctl_hit_c2 &
((l2_fsm2 == `L2_FSM_LD1M) | (l2_fsm2 == `L2_FSM_LD1H)) &
(sctag2_addr_c2[39:8] == l2_fsm2_addr1))
begin
if(l2_fsm2 == `L2_FSM_LD1M) l2_fsm2 <= `L2_FSM_LD2M;
else l2_fsm2 <= `L2_FSM_LD2H;
end
else if(load3 & ~sctag3_tagctl_hit_c2 &
((l2_fsm2 == `L2_FSM_LD1M) | (l2_fsm2 == `L2_FSM_LD1H)) &
(sctag3_addr_c2[39:8] == l2_fsm2_addr1))
begin
if(l2_fsm2 == `L2_FSM_LD1M) l2_fsm2 <= `L2_FSM_LD2M;
else l2_fsm2 <= `L2_FSM_LD2H;
end
//-------------------------------------------
// returning the FSM to idle stuff
// when the original store does the last pass.
//-------------------------------------------
else if(store0 & (sctag0_addr_c2[39:8] == l2_fsm2_addr1[39:8]) &
(sctag0_inst_c2[`L2_CPUID_HI:`L2_TID_LO] == l2_fsm2_id1) &
~sctag0_inst_c2[`L2_EVICT] & sctag0_inst_c2[`L2_MBF])
l2_fsm2 <= `L2_FSM_IDLE;
else if(store1 & (sctag1_addr_c2[39:8] == l2_fsm2_addr1[39:8]) &
(sctag1_inst_c2[`L2_CPUID_HI:`L2_TID_LO] == l2_fsm2_id1) &
~sctag1_inst_c2[`L2_EVICT] & sctag1_inst_c2[`L2_MBF])
l2_fsm2 <= `L2_FSM_IDLE;
else if(store2 & (sctag2_addr_c2[39:8] == l2_fsm2_addr1[39:8]) &
(sctag2_inst_c2[`L2_CPUID_HI:`L2_TID_LO] == l2_fsm2_id1) &
~sctag2_inst_c2[`L2_EVICT] & sctag2_inst_c2[`L2_MBF])
l2_fsm2 <= `L2_FSM_IDLE;
else if(store3 & (sctag3_addr_c2[39:8] == l2_fsm2_addr1[39:8]) &
(sctag3_inst_c2[`L2_CPUID_HI:`L2_TID_LO] == l2_fsm2_id1) &
~sctag3_inst_c2[`L2_EVICT] & sctag3_inst_c2[`L2_MBF])
l2_fsm2 <= `L2_FSM_IDLE;
else if(l2_fsm2_counter > 1000)
l2_fsm2 <= `L2_FSM_IDLE;
end
//==========================================================================================
reg [3:0] l2_fsm3;
integer l2_fsm3_counter;
reg [39:8] l2_fsm3_addr1, l2_fsm3_addr2;
reg [4:0] l2_fsm3_id1, l2_fsm3_id2;
always @(posedge clk)
begin
if(~rst_l)
l2_fsm3_counter <= 0;
else if(l2_fsm3 == `L2_FSM_IDLE)
l2_fsm3_counter <= 0;
else
l2_fsm3_counter <= l2_fsm3_counter + 1;
if(~rst_l)
begin
l2_fsm3 <= `L2_FSM_IDLE;
end
// A first store or wris8 not issued from miss buffer.
//-------------------------------------------------------------------------------
else if(wris80 & ~sctag0_inst_c2[`L2_MBF] & ~sctag0_tagctl_hit_c2 & (l2_fsm3 == `L2_FSM_IDLE))
begin
l2_fsm3_addr1 <= sctag0_addr_c2[39:8];
l2_fsm3_id1 <= sctag0_inst_c2[`L2_CPUID_HI:`L2_TID_LO];
l2_fsm3 <= `L2_FSM_ST1;
end
else if(wris81 & ~sctag1_inst_c2[`L2_MBF] & ~sctag1_tagctl_hit_c2 & (l2_fsm3 == `L2_FSM_IDLE))
begin
l2_fsm3_addr1 <= sctag1_addr_c2[39:8];
l2_fsm3_id1 <= sctag1_inst_c2[`L2_CPUID_HI:`L2_TID_LO];
l2_fsm3 <= `L2_FSM_ST1;
end
else if(wris82 & ~sctag2_inst_c2[`L2_MBF] & ~sctag2_tagctl_hit_c2 & (l2_fsm3 == `L2_FSM_IDLE))
begin
l2_fsm3_addr1 <= sctag2_addr_c2[39:8];
l2_fsm3_id1 <= sctag2_inst_c2[`L2_CPUID_HI:`L2_TID_LO];
l2_fsm3 <= `L2_FSM_ST1;
end
else if(wris83 & ~sctag3_inst_c2[`L2_MBF] & ~sctag3_tagctl_hit_c2 & (l2_fsm3 == `L2_FSM_IDLE))
begin
l2_fsm3_addr1 <= sctag3_addr_c2[39:8];
l2_fsm3_id1 <= sctag3_inst_c2[`L2_CPUID_HI:`L2_TID_LO];
l2_fsm3 <= `L2_FSM_ST1;
end
// The second store - may be a miss or a hit
//-------------------------------------------------------------------------------
else if(wris80 & ~sctag0_inst_c2[`L2_MBF] & (l2_fsm3 == `L2_FSM_ST1))
begin
l2_fsm3_addr2 <= sctag0_addr_c2[39:8];
l2_fsm3_id2 <= sctag0_inst_c2[`L2_CPUID_HI:`L2_TID_LO];
l2_fsm3 <= sctag0_tagctl_hit_c2 ? `L2_FSM_ST2H : `L2_FSM_ST2M;
end
else if(wris81 & ~sctag1_inst_c2[`L2_MBF] & (l2_fsm3 == `L2_FSM_ST1))
begin
l2_fsm3_addr2 <= sctag1_addr_c2[39:8];
l2_fsm3_id2 <= sctag1_inst_c2[`L2_CPUID_HI:`L2_TID_LO];
l2_fsm3 <= sctag1_tagctl_hit_c2 ? `L2_FSM_ST2H : `L2_FSM_ST2M;
end
else if(wris82 & ~sctag2_inst_c2[`L2_MBF] & (l2_fsm3 == `L2_FSM_ST1))
begin
l2_fsm3_addr2 <= sctag2_addr_c2[39:8];
l2_fsm3_id2 <= sctag2_inst_c2[`L2_CPUID_HI:`L2_TID_LO];
l2_fsm3 <= sctag2_tagctl_hit_c2 ? `L2_FSM_ST2H : `L2_FSM_ST2M;
end
else if(wris83 & ~sctag3_inst_c2[`L2_MBF] & (l2_fsm3 == `L2_FSM_ST1))
begin
l2_fsm3_addr2 <= sctag3_addr_c2[39:8];
l2_fsm3_id2 <= sctag3_inst_c2[`L2_CPUID_HI:`L2_TID_LO];
l2_fsm3 <= sctag3_tagctl_hit_c2 ? `L2_FSM_ST2H : `L2_FSM_ST2M;
end
// A load to address2 is a hit or returned already
// the load is eaither not starting from the L2 MB and is a hit
// or is starting from the L2MB.
//-------------------------------------------------------------------------------
else if(load0 & (~sctag0_inst_c2[`L2_MBF] & sctag0_tagctl_hit_c2 |
~sctag0_inst_c2[`L2_EVICT] & sctag0_inst_c2[`L2_MBF]) &
((l2_fsm3 == `L2_FSM_ST2M) | (l2_fsm3 == `L2_FSM_ST2H)) &
(sctag0_addr_c2[39:8] == l2_fsm3_addr2[39:8]))
begin
if(l2_fsm3 == `L2_FSM_ST2M) l2_fsm3 <= `L2_FSM_LD1M;
else l2_fsm3 <= `L2_FSM_LD1H;
end
else if(load1 & (~sctag1_inst_c2[`L2_MBF] & sctag1_tagctl_hit_c2 |
~sctag1_inst_c2[`L2_EVICT] & sctag1_inst_c2[`L2_MBF]) &
((l2_fsm3 == `L2_FSM_ST2M) | (l2_fsm3 == `L2_FSM_ST2H)) &
(sctag1_addr_c2[39:8] == l2_fsm3_addr2[39:8]))
begin
if(l2_fsm3 == `L2_FSM_ST2M) l2_fsm3 <= `L2_FSM_LD1M;
else l2_fsm3 <= `L2_FSM_LD1H;
end
else if(load2 & (~sctag2_inst_c2[`L2_MBF] & sctag2_tagctl_hit_c2 |
~sctag2_inst_c2[`L2_EVICT] & sctag2_inst_c2[`L2_MBF]) &
((l2_fsm3 == `L2_FSM_ST2M) | (l2_fsm3 == `L2_FSM_ST2H)) &
(sctag2_addr_c2[39:8] == l2_fsm3_addr2[39:8]))
begin
if(l2_fsm3 == `L2_FSM_ST2M) l2_fsm3 <= `L2_FSM_LD1M;
else l2_fsm3 <= `L2_FSM_LD1H;
end
else if(load3 & (~sctag3_inst_c2[`L2_MBF] & sctag3_tagctl_hit_c2 |
~sctag3_inst_c2[`L2_EVICT] & sctag3_inst_c2[`L2_MBF]) &
((l2_fsm3 == `L2_FSM_ST2M) | (l2_fsm3 == `L2_FSM_ST2H)) &
(sctag3_addr_c2[39:8] == l2_fsm3_addr2[39:8]))
begin
if(l2_fsm3 == `L2_FSM_ST2M) l2_fsm3 <= `L2_FSM_LD1M;
else l2_fsm3 <= `L2_FSM_LD1H;
end
// A load to address1 is a miss.
//-------------------------------------------------------------------------------
else if(load0 & ~sctag0_tagctl_hit_c2 &
((l2_fsm3 == `L2_FSM_LD1M) | (l2_fsm3 == `L2_FSM_LD1H)) &
(sctag0_addr_c2[39:8] == l2_fsm3_addr1))
begin
if(l2_fsm3 == `L2_FSM_LD1M) l2_fsm3 <= `L2_FSM_LD2M;
else l2_fsm3 <= `L2_FSM_LD2H;
end
else if(load1 & ~sctag1_tagctl_hit_c2 &
((l2_fsm3 == `L2_FSM_LD1M) | (l2_fsm3 == `L2_FSM_LD1H)) &
(sctag1_addr_c2[39:8] == l2_fsm3_addr1))
begin
if(l2_fsm3 == `L2_FSM_LD1M) l2_fsm3 <= `L2_FSM_LD2M;
else l2_fsm3 <= `L2_FSM_LD2H;
end
else if(load2 & ~sctag2_tagctl_hit_c2 &
((l2_fsm3 == `L2_FSM_LD1M) | (l2_fsm3 == `L2_FSM_LD1H)) &
(sctag2_addr_c2[39:8] == l2_fsm3_addr1))
begin
if(l2_fsm3 == `L2_FSM_LD1M) l2_fsm3 <= `L2_FSM_LD2M;
else l2_fsm3 <= `L2_FSM_LD2H;
end
else if(load3 & ~sctag3_tagctl_hit_c2 &
((l2_fsm3 == `L2_FSM_LD1M) | (l2_fsm3 == `L2_FSM_LD1H)) &
(sctag3_addr_c2[39:8] == l2_fsm3_addr1))
begin
if(l2_fsm3 == `L2_FSM_LD1M) l2_fsm3 <= `L2_FSM_LD2M;
else l2_fsm3 <= `L2_FSM_LD2H;
end
//-------------------------------------------
// returning the FSM to idle stuff
// Note - NOT when the original store does the last pass
// but when a new store comes
// when the original store does the last pass.
//-------------------------------------------
else if(wris80 & (sctag0_addr_c2[39:8] == l2_fsm3_addr1[39:8]) &
~sctag0_inst_c2[`L2_EVICT] & ~sctag0_inst_c2[`L2_MBF])
l2_fsm3 <= `L2_FSM_IDLE;
else if(wris81 & (sctag1_addr_c2[39:8] == l2_fsm3_addr1[39:8]) &
~sctag1_inst_c2[`L2_EVICT] & ~sctag1_inst_c2[`L2_MBF])
l2_fsm3 <= `L2_FSM_IDLE;
else if(wris82 & (sctag2_addr_c2[39:8] == l2_fsm3_addr1[39:8]) &
~sctag2_inst_c2[`L2_EVICT] & ~sctag2_inst_c2[`L2_MBF])
l2_fsm3 <= `L2_FSM_IDLE;
else if(wris83 & (sctag3_addr_c2[39:8] == l2_fsm3_addr1[39:8]) &
~sctag3_inst_c2[`L2_EVICT] & ~sctag3_inst_c2[`L2_MBF])
l2_fsm3 <= `L2_FSM_IDLE;
else if(l2_fsm3_counter > 1000)
l2_fsm3 <= `L2_FSM_IDLE;
end
//==========================================================================================
reg [3:0] l2_fsm4;
integer l2_fsm4_counter;
reg [39:8] l2_fsm4_addr1, l2_fsm4_addr2;
reg [4:0] l2_fsm4_id1, l2_fsm4_id2;
always @(posedge clk)
begin
if(~rst_l)
l2_fsm4_counter <= 0;
else if(l2_fsm4 == `L2_FSM_IDLE)
l2_fsm4_counter <= 0;
else
l2_fsm4_counter <= l2_fsm4_counter + 1;
if(~rst_l)
begin
l2_fsm4 <= `L2_FSM_IDLE;
end
// A first store not issued from miss buffer.
//-------------------------------------------------------------------------------
else if(store0 & ~sctag0_inst_c2[`L2_MBF] & ~sctag0_tagctl_hit_c2 & (l2_fsm4 == `L2_FSM_IDLE))
begin
l2_fsm4_addr1 <= sctag0_addr_c2[39:8];
l2_fsm4_id1 <= sctag0_inst_c2[`L2_CPUID_HI:`L2_TID_LO];
l2_fsm4 <= `L2_FSM_ST1;
end
else if(store1 & ~sctag1_inst_c2[`L2_MBF] & ~sctag1_tagctl_hit_c2 & (l2_fsm4 == `L2_FSM_IDLE))
begin
l2_fsm4_addr1 <= sctag1_addr_c2[39:8];
l2_fsm4_id1 <= sctag1_inst_c2[`L2_CPUID_HI:`L2_TID_LO];
l2_fsm4 <= `L2_FSM_ST1;
end
else if(store2 & ~sctag2_inst_c2[`L2_MBF] & ~sctag2_tagctl_hit_c2 & (l2_fsm4 == `L2_FSM_IDLE))
begin
l2_fsm4_addr1 <= sctag2_addr_c2[39:8];
l2_fsm4_id1 <= sctag2_inst_c2[`L2_CPUID_HI:`L2_TID_LO];
l2_fsm4 <= `L2_FSM_ST1;
end
else if(store3 & ~sctag3_inst_c2[`L2_MBF] & ~sctag3_tagctl_hit_c2 & (l2_fsm4 == `L2_FSM_IDLE))
begin
l2_fsm4_addr1 <= sctag3_addr_c2[39:8];
l2_fsm4_id1 <= sctag3_inst_c2[`L2_CPUID_HI:`L2_TID_LO];
l2_fsm4 <= `L2_FSM_ST1;
end
// The second store - may be a miss or a hit
//-------------------------------------------------------------------------------
else if(store0 & ~sctag0_inst_c2[`L2_MBF] & (l2_fsm4 == `L2_FSM_ST1))
begin
l2_fsm4_addr2 <= sctag0_addr_c2[39:8];
l2_fsm4_id2 <= sctag0_inst_c2[`L2_CPUID_HI:`L2_TID_LO];
l2_fsm4 <= sctag0_tagctl_hit_c2 ? `L2_FSM_ST2H : `L2_FSM_ST2M;
end
else if(store1 & ~sctag1_inst_c2[`L2_MBF] & (l2_fsm4 == `L2_FSM_ST1))
begin
l2_fsm4_addr2 <= sctag1_addr_c2[39:8];
l2_fsm4_id2 <= sctag1_inst_c2[`L2_CPUID_HI:`L2_TID_LO];
l2_fsm4 <= sctag1_tagctl_hit_c2 ? `L2_FSM_ST2H : `L2_FSM_ST2M;
end
else if(store2 & ~sctag2_inst_c2[`L2_MBF] & (l2_fsm4 == `L2_FSM_ST1))
begin
l2_fsm4_addr2 <= sctag2_addr_c2[39:8];
l2_fsm4_id2 <= sctag2_inst_c2[`L2_CPUID_HI:`L2_TID_LO];
l2_fsm4 <= sctag2_tagctl_hit_c2 ? `L2_FSM_ST2H : `L2_FSM_ST2M;
end
else if(store3 & ~sctag3_inst_c2[`L2_MBF] & (l2_fsm4 == `L2_FSM_ST1))
begin
l2_fsm4_addr2 <= sctag3_addr_c2[39:8];
l2_fsm4_id2 <= sctag3_inst_c2[`L2_CPUID_HI:`L2_TID_LO];
l2_fsm4 <= sctag3_tagctl_hit_c2 ? `L2_FSM_ST2H : `L2_FSM_ST2M;
end
// A load to address2 is a hit or returned already
// the load is eaither not starting from the L2 MB and is a hit
// or is starting from the L2MB.
//-------------------------------------------------------------------------------
else if(ldd0 & (~sctag0_inst_c2[`L2_MBF] & sctag0_tagctl_hit_c2 |
~sctag0_inst_c2[`L2_EVICT] & sctag0_inst_c2[`L2_MBF]) &
((l2_fsm4 == `L2_FSM_ST2M) | (l2_fsm4 == `L2_FSM_ST2H)) &
(sctag0_addr_c2[39:8] == l2_fsm4_addr2[39:8]))
begin
if(l2_fsm4 == `L2_FSM_ST2M) l2_fsm4 <= `L2_FSM_LD1M;
else l2_fsm4 <= `L2_FSM_LD1H;
end
else if(ldd1 & (~sctag1_inst_c2[`L2_MBF] & sctag1_tagctl_hit_c2 |
~sctag1_inst_c2[`L2_EVICT] & sctag1_inst_c2[`L2_MBF]) &
((l2_fsm4 == `L2_FSM_ST2M) | (l2_fsm4 == `L2_FSM_ST2H)) &
(sctag1_addr_c2[39:8] == l2_fsm4_addr2[39:8]))
begin
if(l2_fsm4 == `L2_FSM_ST2M) l2_fsm4 <= `L2_FSM_LD1M;
else l2_fsm4 <= `L2_FSM_LD1H;
end
else if(ldd2 & (~sctag2_inst_c2[`L2_MBF] & sctag2_tagctl_hit_c2 |
~sctag2_inst_c2[`L2_EVICT] & sctag2_inst_c2[`L2_MBF]) &
((l2_fsm4 == `L2_FSM_ST2M) | (l2_fsm4 == `L2_FSM_ST2H)) &
(sctag2_addr_c2[39:8] == l2_fsm4_addr2[39:8]))
begin
if(l2_fsm4 == `L2_FSM_ST2M) l2_fsm4 <= `L2_FSM_LD1M;
else l2_fsm4 <= `L2_FSM_LD1H;
end
else if(ldd3 & (~sctag3_inst_c2[`L2_MBF] & sctag3_tagctl_hit_c2 |
~sctag3_inst_c2[`L2_EVICT] & sctag3_inst_c2[`L2_MBF]) &
((l2_fsm4 == `L2_FSM_ST2M) | (l2_fsm4 == `L2_FSM_ST2H)) &
(sctag3_addr_c2[39:8] == l2_fsm4_addr2[39:8]))
begin
if(l2_fsm4 == `L2_FSM_ST2M) l2_fsm4 <= `L2_FSM_LD1M;
else l2_fsm4 <= `L2_FSM_LD1H;
end
// A load to address1 is a miss.
//-------------------------------------------------------------------------------
else if(load0 & ~sctag0_tagctl_hit_c2 &
((l2_fsm4 == `L2_FSM_LD1M) | (l2_fsm4 == `L2_FSM_LD1H)) &
(sctag0_addr_c2[39:8] == l2_fsm4_addr1))
begin
if(l2_fsm4 == `L2_FSM_LD1M) l2_fsm4 <= `L2_FSM_LD2M;
else l2_fsm4 <= `L2_FSM_LD2H;
end
else if(load1 & ~sctag1_tagctl_hit_c2 &
((l2_fsm4 == `L2_FSM_LD1M) | (l2_fsm4 == `L2_FSM_LD1H)) &
(sctag1_addr_c2[39:8] == l2_fsm4_addr1))
begin
if(l2_fsm4 == `L2_FSM_LD1M) l2_fsm4 <= `L2_FSM_LD2M;
else l2_fsm4 <= `L2_FSM_LD2H;
end
else if(load2 & ~sctag2_tagctl_hit_c2 &
((l2_fsm4 == `L2_FSM_LD1M) | (l2_fsm4 == `L2_FSM_LD1H)) &
(sctag2_addr_c2[39:8] == l2_fsm4_addr1))
begin
if(l2_fsm4 == `L2_FSM_LD1M) l2_fsm4 <= `L2_FSM_LD2M;
else l2_fsm4 <= `L2_FSM_LD2H;
end
else if(load3 & ~sctag3_tagctl_hit_c2 &
((l2_fsm4 == `L2_FSM_LD1M) | (l2_fsm4 == `L2_FSM_LD1H)) &
(sctag3_addr_c2[39:8] == l2_fsm4_addr1))
begin
if(l2_fsm4 == `L2_FSM_LD1M) l2_fsm4 <= `L2_FSM_LD2M;
else l2_fsm4 <= `L2_FSM_LD2H;
end
//-------------------------------------------
// returning the FSM to idle stuff
// when the original store does the last pass.
//-------------------------------------------
else if(store0 & (sctag0_addr_c2[39:8] == l2_fsm4_addr1[39:8]) &
(sctag0_inst_c2[`L2_CPUID_HI:`L2_TID_LO] == l2_fsm4_id1) &
~sctag0_inst_c2[`L2_EVICT] & sctag0_inst_c2[`L2_MBF])
l2_fsm4 <= `L2_FSM_IDLE;
else if(store1 & (sctag1_addr_c2[39:8] == l2_fsm4_addr1[39:8]) &
(sctag1_inst_c2[`L2_CPUID_HI:`L2_TID_LO] == l2_fsm4_id1) &
~sctag1_inst_c2[`L2_EVICT] & sctag1_inst_c2[`L2_MBF])
l2_fsm4 <= `L2_FSM_IDLE;
else if(store2 & (sctag2_addr_c2[39:8] == l2_fsm4_addr1[39:8]) &
(sctag2_inst_c2[`L2_CPUID_HI:`L2_TID_LO] == l2_fsm4_id1) &
~sctag2_inst_c2[`L2_EVICT] & sctag2_inst_c2[`L2_MBF])
l2_fsm4 <= `L2_FSM_IDLE;
else if(store3 & (sctag3_addr_c2[39:8] == l2_fsm4_addr1[39:8]) &
(sctag3_inst_c2[`L2_CPUID_HI:`L2_TID_LO] == l2_fsm4_id1) &
~sctag3_inst_c2[`L2_EVICT] & sctag3_inst_c2[`L2_MBF])
l2_fsm4 <= `L2_FSM_IDLE;
else if(l2_fsm4_counter > 1000)
l2_fsm4 <= `L2_FSM_IDLE;
end
//-------------------------------------------------------------------
// L2MB related stuff again - the states of each individual L2MB
//-------------------------------------------------------------------
`define L2MB_IDLE 4'b0000
`define L2MB_EVICT 4'b0001
`define L2MB_EVICT_FILL 4'b0010
`define L2MB_EVICT_BYPASS 4'b0011
reg [39:8] sctag0_l2mb_addr [0:15];
reg [3:0] sctag0_l2mb_state[0:15];
wire [3:0] sctag0_l2mb_state0 = sctag0_l2mb_state[0];
wire [3:0] sctag0_l2mb_state1 = sctag0_l2mb_state[1];
wire [3:0] sctag0_l2mb_state2 = sctag0_l2mb_state[2];
wire [3:0] sctag0_l2mb_state3 = sctag0_l2mb_state[3];
wire [3:0] sctag0_l2mb_state4 = sctag0_l2mb_state[4];
wire [3:0] sctag0_l2mb_state5 = sctag0_l2mb_state[5];
wire [3:0] sctag0_l2mb_state6 = sctag0_l2mb_state[6];
wire [3:0] sctag0_l2mb_state7 = sctag0_l2mb_state[7];
wire [3:0] sctag0_l2mb_state8 = sctag0_l2mb_state[8];
wire [3:0] sctag0_l2mb_state9 = sctag0_l2mb_state[9];
wire [3:0] sctag0_l2mb_state10 = sctag0_l2mb_state[10];
wire [3:0] sctag0_l2mb_state11 = sctag0_l2mb_state[11];
wire [3:0] sctag0_l2mb_state12 = sctag0_l2mb_state[12];
wire [3:0] sctag0_l2mb_state13 = sctag0_l2mb_state[13];
wire [3:0] sctag0_l2mb_state14 = sctag0_l2mb_state[14];
wire [3:0] sctag0_l2mb_state15 = sctag0_l2mb_state[15];
reg sctag0_l2mb_pointer;
integer sctag0_iii;
reg [39:8] sctag1_l2mb_addr [0:15];
reg [3:0] sctag1_l2mb_state[0:15];
wire [3:0] sctag1_l2mb_state0 = sctag1_l2mb_state[0];
wire [3:0] sctag1_l2mb_state1 = sctag1_l2mb_state[1];
wire [3:0] sctag1_l2mb_state2 = sctag1_l2mb_state[2];
wire [3:0] sctag1_l2mb_state3 = sctag1_l2mb_state[3];
wire [3:0] sctag1_l2mb_state4 = sctag1_l2mb_state[4];
wire [3:0] sctag1_l2mb_state5 = sctag1_l2mb_state[5];
wire [3:0] sctag1_l2mb_state6 = sctag1_l2mb_state[6];
wire [3:0] sctag1_l2mb_state7 = sctag1_l2mb_state[7];
wire [3:0] sctag1_l2mb_state8 = sctag1_l2mb_state[8];
wire [3:0] sctag1_l2mb_state9 = sctag1_l2mb_state[9];
wire [3:0] sctag1_l2mb_state10 = sctag1_l2mb_state[10];
wire [3:0] sctag1_l2mb_state11 = sctag1_l2mb_state[11];
wire [3:0] sctag1_l2mb_state12 = sctag1_l2mb_state[12];
wire [3:0] sctag1_l2mb_state13 = sctag1_l2mb_state[13];
wire [3:0] sctag1_l2mb_state14 = sctag1_l2mb_state[14];
wire [3:0] sctag1_l2mb_state15 = sctag1_l2mb_state[15];
reg sctag1_l2mb_pointer;
integer sctag1_iii;
reg [39:8] sctag2_l2mb_addr [0:15];
reg [3:0] sctag2_l2mb_state[0:15];
wire [3:0] sctag2_l2mb_state0 = sctag2_l2mb_state[0];
wire [3:0] sctag2_l2mb_state1 = sctag2_l2mb_state[1];
wire [3:0] sctag2_l2mb_state2 = sctag2_l2mb_state[2];
wire [3:0] sctag2_l2mb_state3 = sctag2_l2mb_state[3];
wire [3:0] sctag2_l2mb_state4 = sctag2_l2mb_state[4];
wire [3:0] sctag2_l2mb_state5 = sctag2_l2mb_state[5];
wire [3:0] sctag2_l2mb_state6 = sctag2_l2mb_state[6];
wire [3:0] sctag2_l2mb_state7 = sctag2_l2mb_state[7];
wire [3:0] sctag2_l2mb_state8 = sctag2_l2mb_state[8];
wire [3:0] sctag2_l2mb_state9 = sctag2_l2mb_state[9];
wire [3:0] sctag2_l2mb_state10 = sctag2_l2mb_state[10];
wire [3:0] sctag2_l2mb_state11 = sctag2_l2mb_state[11];
wire [3:0] sctag2_l2mb_state12 = sctag2_l2mb_state[12];
wire [3:0] sctag2_l2mb_state13 = sctag2_l2mb_state[13];
wire [3:0] sctag2_l2mb_state14 = sctag2_l2mb_state[14];
wire [3:0] sctag2_l2mb_state15 = sctag2_l2mb_state[15];
reg sctag2_l2mb_pointer;
integer sctag2_iii;
reg [39:8] sctag3_l2mb_addr [0:15];
reg [3:0] sctag3_l2mb_state[0:15];
wire [3:0] sctag3_l2mb_state0 = sctag3_l2mb_state[0];
wire [3:0] sctag3_l2mb_state1 = sctag3_l2mb_state[1];
wire [3:0] sctag3_l2mb_state2 = sctag3_l2mb_state[2];
wire [3:0] sctag3_l2mb_state3 = sctag3_l2mb_state[3];
wire [3:0] sctag3_l2mb_state4 = sctag3_l2mb_state[4];
wire [3:0] sctag3_l2mb_state5 = sctag3_l2mb_state[5];
wire [3:0] sctag3_l2mb_state6 = sctag3_l2mb_state[6];
wire [3:0] sctag3_l2mb_state7 = sctag3_l2mb_state[7];
wire [3:0] sctag3_l2mb_state8 = sctag3_l2mb_state[8];
wire [3:0] sctag3_l2mb_state9 = sctag3_l2mb_state[9];
wire [3:0] sctag3_l2mb_state10 = sctag3_l2mb_state[10];
wire [3:0] sctag3_l2mb_state11 = sctag3_l2mb_state[11];
wire [3:0] sctag3_l2mb_state12 = sctag3_l2mb_state[12];
wire [3:0] sctag3_l2mb_state13 = sctag3_l2mb_state[13];
wire [3:0] sctag3_l2mb_state14 = sctag3_l2mb_state[14];
wire [3:0] sctag3_l2mb_state15 = sctag3_l2mb_state[15];
reg sctag3_l2mb_pointer;
integer sctag3_iii;
always @(posedge clk)
begin
if(~rst_l)
begin
for(sctag0_iii=0; sctag0_iii<16; sctag0_iii = sctag0_iii+1)
sctag0_l2mb_state[sctag0_iii] = `L2MB_IDLE;
end
else if(sctag0_inst_vld_c2 & sctag0_inst_c2[`L2_MBF] & sctag0_inst_c2[`L2_EVICT])
begin
sctag0_l2mb_pointer = sctag_find_next_available(2'h0);
sctag0_l2mb_addr [sctag0_l2mb_pointer] <= sctag0_addr_c2[39:8];
sctag0_l2mb_state[sctag0_l2mb_pointer] <= `L2MB_EVICT;
end
else if(sctag0_inst_vld_c2 & sctag0_inst_c2[`L2_FBF])
begin
sctag0_l2mb_pointer = sctag_l2mb_cam(2'h0);
sctag0_l2mb_state[sctag0_l2mb_pointer] <= (sctag0_l2mb_state[sctag0_l2mb_pointer] == `L2MB_EVICT) ?
`L2MB_EVICT_FILL: `L2MB_IDLE;
end
else if(sctag0_inst_vld_c2 & sctag0_inst_c2[`L2_MBF] & ~sctag0_inst_c2[`L2_EVICT])
begin
sctag0_l2mb_pointer = sctag_l2mb_cam(2'h0);
sctag0_l2mb_state[sctag0_l2mb_pointer] <= (sctag0_l2mb_state[sctag0_l2mb_pointer] == `L2MB_EVICT) ?
`L2MB_EVICT_BYPASS: `L2MB_IDLE;
end
end
always @(posedge clk)
begin
if(~rst_l)
begin
for(sctag1_iii=0; sctag1_iii<16; sctag1_iii = sctag1_iii+1)
sctag1_l2mb_state[sctag1_iii] = `L2MB_IDLE;
end
else if(sctag1_inst_vld_c2 & sctag1_inst_c2[`L2_MBF] & sctag1_inst_c2[`L2_EVICT])
begin
sctag1_l2mb_pointer = sctag_find_next_available(2'h1);
sctag1_l2mb_addr [sctag1_l2mb_pointer] <= sctag1_addr_c2[39:8];
sctag1_l2mb_state[sctag1_l2mb_pointer] <= `L2MB_EVICT;
end
else if(sctag1_inst_vld_c2 & sctag1_inst_c2[`L2_FBF])
begin
sctag1_l2mb_pointer = sctag_l2mb_cam(2'h1);
sctag1_l2mb_state[sctag1_l2mb_pointer] <= (sctag1_l2mb_state[sctag1_l2mb_pointer] == `L2MB_EVICT) ?
`L2MB_EVICT_FILL: `L2MB_IDLE;
end
else if(sctag1_inst_vld_c2 & sctag1_inst_c2[`L2_MBF] & ~sctag1_inst_c2[`L2_EVICT])
begin
sctag1_l2mb_pointer = sctag_l2mb_cam(2'h1);
sctag1_l2mb_state[sctag0_l2mb_pointer] <= (sctag1_l2mb_state[sctag1_l2mb_pointer] == `L2MB_EVICT) ?
`L2MB_EVICT_BYPASS: `L2MB_IDLE;
end
end
always @(posedge clk)
begin
if(~rst_l)
begin
for(sctag2_iii=0; sctag2_iii<16; sctag2_iii = sctag2_iii+1)
sctag2_l2mb_state[sctag2_iii] = `L2MB_IDLE;
end
else if(sctag2_inst_vld_c2 & sctag2_inst_c2[`L2_MBF] & sctag2_inst_c2[`L2_EVICT])
begin
sctag2_l2mb_pointer = sctag_find_next_available(2'h2);
sctag2_l2mb_addr [sctag2_l2mb_pointer] <= sctag2_addr_c2[39:8];
sctag2_l2mb_state[sctag2_l2mb_pointer] <= `L2MB_EVICT;
end
else if(sctag2_inst_vld_c2 & sctag2_inst_c2[`L2_FBF])
begin
sctag2_l2mb_pointer = sctag_l2mb_cam(2'h2);
sctag2_l2mb_state[sctag2_l2mb_pointer] <= (sctag2_l2mb_state[sctag2_l2mb_pointer] == `L2MB_EVICT) ?
`L2MB_EVICT_FILL: `L2MB_IDLE;
end
else if(sctag2_inst_vld_c2 & sctag2_inst_c2[`L2_MBF] & ~sctag2_inst_c2[`L2_EVICT])
begin
sctag2_l2mb_pointer = sctag_l2mb_cam(2'h2);
sctag2_l2mb_state[sctag0_l2mb_pointer] <= (sctag2_l2mb_state[sctag2_l2mb_pointer] == `L2MB_EVICT) ?
`L2MB_EVICT_BYPASS: `L2MB_IDLE;
end
end
always @(posedge clk)
begin
if(~rst_l)
begin
for(sctag3_iii=0; sctag3_iii<16; sctag3_iii = sctag3_iii+1)
sctag3_l2mb_state[sctag3_iii] = `L2MB_IDLE;
end
else if(sctag3_inst_vld_c2 & sctag3_inst_c2[`L2_MBF] & sctag3_inst_c2[`L2_EVICT])
begin
sctag3_l2mb_pointer = sctag_find_next_available(2'h3);
sctag3_l2mb_addr [sctag3_l2mb_pointer] <= sctag3_addr_c2[39:8];
sctag3_l2mb_state[sctag3_l2mb_pointer] <= `L2MB_EVICT;
end
else if(sctag3_inst_vld_c2 & sctag3_inst_c2[`L2_FBF])
begin
sctag3_l2mb_pointer = sctag_l2mb_cam(2'h3);
sctag3_l2mb_state[sctag3_l2mb_pointer] <= (sctag3_l2mb_state[sctag3_l2mb_pointer] == `L2MB_EVICT) ?
`L2MB_EVICT_FILL: `L2MB_IDLE;
end
else if(sctag3_inst_vld_c2 & sctag3_inst_c2[`L2_MBF] & ~sctag3_inst_c2[`L2_EVICT])
begin
sctag3_l2mb_pointer = sctag_l2mb_cam(2'h3);
sctag3_l2mb_state[sctag0_l2mb_pointer] <= (sctag3_l2mb_state[sctag3_l2mb_pointer] == `L2MB_EVICT) ?
`L2MB_EVICT_BYPASS: `L2MB_IDLE;
end
end
//============================================================================================
// LSU stuff
//============================================================================================
//============================================================================================
// Back to back invalidates and loads ...cores...
//============================================================================================
`ifdef RTL_SPARC0
wire C0T0_stb_ne = |`TOP_DESIGN.sparc0.lsu.stb_ctl0.stb_state_vld[7:0];
wire C0T1_stb_ne = |`TOP_DESIGN.sparc0.lsu.stb_ctl1.stb_state_vld[7:0];
wire C0T2_stb_ne = |`TOP_DESIGN.sparc0.lsu.stb_ctl2.stb_state_vld[7:0];
wire C0T3_stb_ne = |`TOP_DESIGN.sparc0.lsu.stb_ctl3.stb_state_vld[7:0];
wire C0T0_stb_nced = |( `TOP_DESIGN.sparc0.lsu.stb_ctl0.stb_state_vld[7:0] &
~`TOP_DESIGN.sparc0.lsu.stb_ctl0.stb_state_ced[7:0]);
wire C0T1_stb_nced = |( `TOP_DESIGN.sparc0.lsu.stb_ctl1.stb_state_vld[7:0] &
~`TOP_DESIGN.sparc0.lsu.stb_ctl1.stb_state_ced[7:0]);
wire C0T2_stb_nced = |( `TOP_DESIGN.sparc0.lsu.stb_ctl2.stb_state_vld[7:0] &
~`TOP_DESIGN.sparc0.lsu.stb_ctl2.stb_state_ced[7:0]);
wire C0T3_stb_nced = |( `TOP_DESIGN.sparc0.lsu.stb_ctl3.stb_state_vld[7:0] &
~`TOP_DESIGN.sparc0.lsu.stb_ctl3.stb_state_ced[7:0]);
`else
wire C0T0_stb_ne = 1'b0;
wire C0T1_stb_ne = 1'b0;
wire C0T2_stb_ne = 1'b0;
wire C0T3_stb_ne = 1'b0;
wire C0T0_stb_nced = 1'b0;
wire C0T1_stb_nced = 1'b0;
wire C0T2_stb_nced = 1'b0;
wire C0T3_stb_nced = 1'b0;
`endif // ifdef RTL_SPARC0
`ifdef RTL_SPARC0
wire spc0_lsu_ifill_pkt_vld = `TOP_DESIGN.sparc0.lsu.qctl2.lsu_ifill_pkt_vld;
wire spc0_dfq_rd_advance = `TOP_DESIGN.sparc0.lsu.qctl2.dfq_rd_advance;
wire spc0_dfq_int_type = `TOP_DESIGN.sparc0.lsu.qctl2.dfq_int_type;
wire spc0_ifu_lsu_inv_clear = `TOP_DESIGN.sparc0.lsu.qctl2.ifu_lsu_inv_clear;
wire spc0_dva_svld_e = `TOP_DESIGN.sparc0.lsu.qctl2.dva_svld_e;
wire spc0_dva_rvld_e = `TOP_DESIGN.sparc0.lsu.dva.rd_en;
wire [10:4] spc0_dva_rd_addr_e = `TOP_DESIGN.sparc0.lsu.dva.rd_adr1[6:0];
wire [4:0] spc0_dva_snp_addr_e = `TOP_DESIGN.sparc0.lsu.qctl2.dva_snp_addr_e[4:0];
wire [4:0] spc0_stb_data_rd_ptr = `TOP_DESIGN.sparc0.lsu.stb_data_rd_ptr[4:0];
wire [4:0] spc0_stb_data_wr_ptr = `TOP_DESIGN.sparc0.lsu.stb_data_wr_ptr[4:0];
wire spc0_stb_data_wptr_vld = `TOP_DESIGN.sparc0.lsu.stb_data_wptr_vld;
wire spc0_stb_data_rptr_vld = `TOP_DESIGN.sparc0.lsu.stb_data_rptr_vld;
wire spc0_stbrwctl_flush_pipe_w = `TOP_DESIGN.sparc0.lsu.stb_rwctl.lsu_stbrwctl_flush_pipe_w;
wire spc0_lsu_st_pcx_rq_pick = |`TOP_DESIGN.sparc0.lsu.stb_rwctl.lsu_st_pcx_rq_pick[3:0];
wire [3:0] spc0_lsu_rd_dtag_parity_g = `TOP_DESIGN.sparc0.lsu.dctl.lsu_rd_dtag_parity_g[3:0];
wire [3:0] spc0_dva_vld_g = `TOP_DESIGN.sparc0.lsu.dctl.dva_vld_g[3:0];
wire [3:0] spc0_lsu_dc_tag_pe_g_unmasked = spc0_lsu_rd_dtag_parity_g[3:0] & spc0_dva_vld_g[3:0];
wire spc0_lsu_dc_tag_pe_g_unmasked_or = |spc0_lsu_dc_tag_pe_g_unmasked[3:0];
wire C0T0_stb_full = &`TOP_DESIGN.sparc0.lsu.stb_ctl0.stb_state_vld[7:0];
wire C0T1_stb_full = &`TOP_DESIGN.sparc0.lsu.stb_ctl1.stb_state_vld[7:0];
wire C0T2_stb_full = &`TOP_DESIGN.sparc0.lsu.stb_ctl2.stb_state_vld[7:0];
wire C0T3_stb_full = &`TOP_DESIGN.sparc0.lsu.stb_ctl3.stb_state_vld[7:0];
wire [7:0] C0T0_stb_vld = `TOP_DESIGN.sparc0.lsu.stb_ctl0.stb_state_vld[7:0];
wire [7:0] C0T1_stb_vld = `TOP_DESIGN.sparc0.lsu.stb_ctl1.stb_state_vld[7:0];
wire [7:0] C0T2_stb_vld = `TOP_DESIGN.sparc0.lsu.stb_ctl2.stb_state_vld[7:0];
wire [7:0] C0T3_stb_vld = `TOP_DESIGN.sparc0.lsu.stb_ctl3.stb_state_vld[7:0];
wire [4:0] C0T0_stb_vld_sum = C0T0_stb_vld[0] + C0T0_stb_vld[1] + C0T0_stb_vld[2] + C0T0_stb_vld[3] +
C0T0_stb_vld[4] + C0T0_stb_vld[5] + C0T0_stb_vld[6] + C0T0_stb_vld[7] ;
wire [4:0] C0T1_stb_vld_sum = C0T1_stb_vld[0] + C0T1_stb_vld[1] + C0T1_stb_vld[2] + C0T1_stb_vld[3] +
C0T1_stb_vld[4] + C0T1_stb_vld[5] + C0T1_stb_vld[6] + C0T1_stb_vld[7] ;
wire [4:0] C0T2_stb_vld_sum = C0T2_stb_vld[0] + C0T2_stb_vld[1] + C0T2_stb_vld[2] + C0T2_stb_vld[3] +
C0T2_stb_vld[4] + C0T2_stb_vld[5] + C0T2_stb_vld[6] + C0T2_stb_vld[7] ;
wire [4:0] C0T3_stb_vld_sum = C0T3_stb_vld[0] + C0T3_stb_vld[1] + C0T3_stb_vld[2] + C0T3_stb_vld[3] +
C0T3_stb_vld[4] + C0T3_stb_vld[5] + C0T3_stb_vld[6] + C0T3_stb_vld[7] ;
reg [4:0] C0T0_stb_vld_sum_d1;
reg [4:0] C0T1_stb_vld_sum_d1;
reg [4:0] C0T2_stb_vld_sum_d1;
reg [4:0] C0T3_stb_vld_sum_d1;
wire C0T0_st_ack = &`TOP_DESIGN.sparc0.lsu.cpx_st_ack_tid0;
wire C0T1_st_ack = &`TOP_DESIGN.sparc0.lsu.cpx_st_ack_tid1;
wire C0T2_st_ack = &`TOP_DESIGN.sparc0.lsu.cpx_st_ack_tid2;
wire C0T3_st_ack = &`TOP_DESIGN.sparc0.lsu.cpx_st_ack_tid3;
wire C0T0_defr_trp_en = &`TOP_DESIGN.sparc0.lsu.excpctl.st_defr_trp_en0;
wire C0T1_defr_trp_en = &`TOP_DESIGN.sparc0.lsu.excpctl.st_defr_trp_en1;
wire C0T2_defr_trp_en = &`TOP_DESIGN.sparc0.lsu.excpctl.st_defr_trp_en2;
wire C0T3_defr_trp_en = &`TOP_DESIGN.sparc0.lsu.excpctl.st_defr_trp_en3;
reg C0T0_defr_trp_en_d1;
reg C0T1_defr_trp_en_d1;
reg C0T2_defr_trp_en_d1;
reg C0T3_defr_trp_en_d1;
integer C0T0_stb_drain_cnt;
integer C0T1_stb_drain_cnt;
integer C0T2_stb_drain_cnt;
integer C0T3_stb_drain_cnt;
// Hits in the store buffer
//-------------------------
wire spc0_inst_vld_w = `TOP_DESIGN.sparc0.ifu.fcl.inst_vld_w;
wire [1:0] spc0_sas_thrid_w = `TOP_DESIGN.sparc0.ifu.fcl.sas_thrid_w[1:0];
wire C0_st_ack_w = (spc0_sas_thrid_w == 2'b00) & C0T0_st_ack |
(spc0_sas_thrid_w == 2'b01) & C0T1_st_ack |
(spc0_sas_thrid_w == 2'b10) & C0T2_st_ack |
(spc0_sas_thrid_w == 2'b11) & C0T3_st_ack;
wire [7:0] spc0_stb_ld_full_raw = `TOP_DESIGN.sparc0.lsu.stb_ld_full_raw[7:0];
wire [7:0] spc0_stb_ld_partial_raw = `TOP_DESIGN.sparc0.lsu.stb_ld_partial_raw[7:0];
wire spc0_stb_cam_mhit = `TOP_DESIGN.sparc0.lsu.stb_cam_mhit;
wire spc0_stb_cam_hit = `TOP_DESIGN.sparc0.lsu.stb_cam_hit;
wire [3:0] spc0_lsu_way_hit = `TOP_DESIGN.sparc0.lsu.dctl.lsu_way_hit[3:0];
wire spc0_lsu_ifu_ldst_miss_w = `TOP_DESIGN.sparc0.lsu.lsu_ifu_ldst_miss_w;
wire spc0_ld_inst_vld_g = `TOP_DESIGN.sparc0.lsu.dctl.ld_inst_vld_g;
wire spc0_ldst_dbl_g = `TOP_DESIGN.sparc0.lsu.dctl.ldst_dbl_g;
wire spc0_quad_asi_g = `TOP_DESIGN.sparc0.lsu.dctl.quad_asi_g;
wire [1:0] spc0_ldst_sz_g = `TOP_DESIGN.sparc0.lsu.dctl.ldst_sz_g;
wire spc0_lsu_alt_space_g = `TOP_DESIGN.sparc0.lsu.dctl.lsu_alt_space_g;
wire spc0_mbar_inst0_g = `TOP_DESIGN.sparc0.lsu.dctl.mbar_inst0_g;
wire spc0_mbar_inst1_g = `TOP_DESIGN.sparc0.lsu.dctl.mbar_inst1_g;
wire spc0_mbar_inst2_g = `TOP_DESIGN.sparc0.lsu.dctl.mbar_inst2_g;
wire spc0_mbar_inst3_g = `TOP_DESIGN.sparc0.lsu.dctl.mbar_inst3_g;
wire spc0_flush_inst0_g = `TOP_DESIGN.sparc0.lsu.dctl.flush_inst0_g;
wire spc0_flush_inst1_g = `TOP_DESIGN.sparc0.lsu.dctl.flush_inst1_g;
wire spc0_flush_inst2_g = `TOP_DESIGN.sparc0.lsu.dctl.flush_inst2_g;
wire spc0_flush_inst3_g = `TOP_DESIGN.sparc0.lsu.dctl.flush_inst3_g;
wire spc0_intrpt_disp_asi0_g = `TOP_DESIGN.sparc0.lsu.dctl.intrpt_disp_asi_g & (spc0_sas_thrid_w == 2'b00);
wire spc0_intrpt_disp_asi1_g = `TOP_DESIGN.sparc0.lsu.dctl.intrpt_disp_asi_g & (spc0_sas_thrid_w == 2'b01);
wire spc0_intrpt_disp_asi2_g = `TOP_DESIGN.sparc0.lsu.dctl.intrpt_disp_asi_g & (spc0_sas_thrid_w == 2'b10);
wire spc0_intrpt_disp_asi3_g = `TOP_DESIGN.sparc0.lsu.dctl.intrpt_disp_asi_g & (spc0_sas_thrid_w == 2'b11);
wire spc0_st_inst_vld_g = `TOP_DESIGN.sparc0.lsu.dctl.st_inst_vld_g;
wire spc0_non_altspace_ldst_g = `TOP_DESIGN.sparc0.lsu.dctl.non_altspace_ldst_g;
wire spc0_dctl_flush_pipe_w = `TOP_DESIGN.sparc0.lsu.dctl.dctl_flush_pipe_w;
wire [3:0] spc0_no_spc_rmo_st = `TOP_DESIGN.sparc0.lsu.dctl.no_spc_rmo_st[3:0];
wire spc0_ldst_fp_e = `TOP_DESIGN.sparc0.lsu.ifu_lsu_ldst_fp_e;
wire [2:0] spc0_stb_rdptr = `TOP_DESIGN.sparc0.lsu.stb_rwctl.stb_rdptr_l;
wire spc0_ld_l2cache_req = `TOP_DESIGN.sparc0.lsu.qctl1.ld3_l2cache_rq |
`TOP_DESIGN.sparc0.lsu.qctl1.ld2_l2cache_rq |
`TOP_DESIGN.sparc0.lsu.qctl1.ld1_l2cache_rq |
`TOP_DESIGN.sparc0.lsu.qctl1.ld0_l2cache_rq;
wire [3:0] spc0_dcache_enable = {`TOP_DESIGN.sparc0.lsu.dctl.lsu_ctl_reg0[1],
`TOP_DESIGN.sparc0.lsu.dctl.lsu_ctl_reg1[1],
`TOP_DESIGN.sparc0.lsu.dctl.lsu_ctl_reg2[1],
`TOP_DESIGN.sparc0.lsu.dctl.lsu_ctl_reg3[1]};
wire [3:0] spc0_icache_enable = `TOP_DESIGN.sparc0.lsu.lsu_ifu_icache_en[3:0];
wire spc0_dc_direct_map = `TOP_DESIGN.sparc0.lsu.dc_direct_map;
wire spc0_lsu_ifu_direct_map_l1 = `TOP_DESIGN.sparc0.lsu.lsu_ifu_direct_map_l1;
always @(spc0_dcache_enable)
$display("%0d tso_mon: spc0_dcache_enable changed to %x", $time, spc0_dcache_enable);
always @(spc0_icache_enable)
$display("%0d tso_mon: spc0_icache_enable changed to %x", $time, spc0_icache_enable);
always @(spc0_dc_direct_map)
$display("%0d tso_mon: spc0_dc_direct_map changed to %x", $time, spc0_dc_direct_map);
always @(spc0_lsu_ifu_direct_map_l1)
$display("%0d tso_mon: spc0_lsu_ifu_direct_map_l1 changed to %x", $time, spc0_lsu_ifu_direct_map_l1);
reg spc0_dva_svld_e_d1;
reg spc0_dva_rvld_e_d1;
reg [10:4] spc0_dva_rd_addr_e_d1;
reg [4:0] spc0_dva_snp_addr_e_d1;
reg spc0_lsu_snp_after_rd;
reg spc0_lsu_rd_after_snp;
reg spc0_ldst_fp_m, spc0_ldst_fp_g;
integer spc0_multiple_hits;
reg spc0_skid_d1, spc0_skid_d2, spc0_skid_d3;
initial begin
spc0_skid_d1 = 0;
spc0_skid_d2 = 0;
spc0_skid_d3 = 0;
end
always @(posedge clk)
begin
spc0_skid_d1 <= (~spc0_ifu_lsu_inv_clear & spc0_dfq_rd_advance & spc0_dfq_int_type);
spc0_skid_d2 <= spc0_skid_d1 & ~spc0_ifu_lsu_inv_clear;
spc0_skid_d3 <= spc0_skid_d2 & ~spc0_ifu_lsu_inv_clear;
// The full tracking of this condition is complicated since after the interrupt is advanced
// there may be more invalidations to the IFQ.
// All we care about is that the invalidations BEFORE the interrupt are finished.
// I provided a command line argument to disable this check.
if(spc0_skid_d3 & enable_ifu_lsu_inv_clear)
finish_test("spc", "tso_mon: spc0_ifu_lsu_inv_clear should have been clear by now", 0);
spc0_dva_svld_e_d1 <= spc0_dva_svld_e;
spc0_dva_rvld_e_d1 <= spc0_dva_rvld_e;
spc0_dva_rd_addr_e_d1 <= spc0_dva_rd_addr_e;
spc0_dva_snp_addr_e_d1 <= spc0_dva_snp_addr_e;
if(spc0_dva_svld_e_d1 & spc0_dva_rvld_e & (spc0_dva_rd_addr_e_d1[10:6] == spc0_dva_snp_addr_e[4:0]))
spc0_lsu_rd_after_snp <= 1'b1;
else
spc0_lsu_rd_after_snp <= 1'b0;
if(spc0_dva_svld_e & spc0_dva_rvld_e_d1 & (spc0_dva_rd_addr_e[10:6] == spc0_dva_snp_addr_e_d1[4:0]))
spc0_lsu_snp_after_rd <= 1'b1;
else
spc0_lsu_snp_after_rd <= 1'b0;
spc0_ldst_fp_m <= spc0_ldst_fp_e;
spc0_ldst_fp_g <= spc0_ldst_fp_m;
if(spc0_stb_data_rptr_vld & spc0_stb_data_wptr_vld & ~spc0_stbrwctl_flush_pipe_w &
(spc0_stb_data_rd_ptr == spc0_stb_data_wr_ptr) & spc0_lsu_st_pcx_rq_pick)
begin
finish_test("spc", "tso_mon: LSU stb data write and read in the same cycle", 0);
end
spc0_multiple_hits = (spc0_lsu_way_hit[3] + spc0_lsu_way_hit[2] + spc0_lsu_way_hit[1] + spc0_lsu_way_hit[0]);
if(!spc0_lsu_ifu_ldst_miss_w && (spc0_multiple_hits >1) && spc0_inst_vld_w && !spc0_dctl_flush_pipe_w && !spc0_lsu_dc_tag_pe_g_unmasked_or)
finish_test("spc", "tso_mon: LSU multiple hits ", 0);
end
wire spc0_ld_dbl = spc0_ld_inst_vld_g & spc0_ldst_dbl_g & ~spc0_quad_asi_g;
wire spc0_ld_quad = spc0_ld_inst_vld_g & spc0_ldst_dbl_g & spc0_quad_asi_g;
wire spc0_ld_other = spc0_ld_inst_vld_g & ~spc0_ldst_dbl_g;
wire spc0_ld_dbl_fp = spc0_ld_dbl & spc0_ldst_fp_g;
wire spc0_ld_other_fp = spc0_ld_other & spc0_ldst_fp_g;
wire spc0_ld_dbl_int = spc0_ld_dbl & ~spc0_ldst_fp_g;
wire spc0_ld_quad_int = spc0_ld_quad & ~spc0_ldst_fp_g;
wire spc0_ld_other_int= spc0_ld_other & ~spc0_ldst_fp_g;
wire spc0_ld_bypassok_hit = |spc0_stb_ld_full_raw[7:0] & ~spc0_stb_cam_mhit;
wire spc0_ld_partial_hit = |spc0_stb_ld_partial_raw[7:0] & ~spc0_stb_cam_mhit;
wire spc0_ld_multiple_hit = spc0_stb_cam_mhit;
wire spc0_any_lsu_way_hit = |spc0_lsu_way_hit;
wire [7:0] spc0_stb_rdptr_decoded = (spc0_stb_rdptr ==3'b000) ? 8'b00000001 :
(spc0_stb_rdptr ==3'b001) ? 8'b00000010 :
(spc0_stb_rdptr ==3'b010) ? 8'b00000100 :
(spc0_stb_rdptr ==3'b011) ? 8'b00001000 :
(spc0_stb_rdptr ==3'b100) ? 8'b00010000 :
(spc0_stb_rdptr ==3'b101) ? 8'b00100000 :
(spc0_stb_rdptr ==3'b110) ? 8'b01000000 :
(spc0_stb_rdptr ==3'b111) ? 8'b10000000 : 8'h00;
wire spc0_stb_top_hit = |(spc0_stb_rdptr_decoded & (spc0_stb_ld_full_raw | spc0_stb_ld_partial_raw));
//---------------------------------------------------------------------
// ld_type[4:0] hit_type[2:0], cache_hit, hit_top
// this is passed to the coverage monitor.
//---------------------------------------------------------------------
wire [10:0] spc0_stb_ld_hit_info =
{spc0_ld_dbl_fp, spc0_ld_other_fp,
spc0_ld_dbl_int, spc0_ld_quad_int, spc0_ld_other_int,
spc0_ld_bypassok_hit, spc0_ld_partial_hit, spc0_ld_multiple_hit,
spc0_any_lsu_way_hit,
spc0_stb_top_hit, C0_st_ack_w};
reg spc0_mbar0_active;
reg spc0_mbar1_active;
reg spc0_mbar2_active;
reg spc0_mbar3_active;
reg spc0_flush0_active;
reg spc0_flush1_active;
reg spc0_flush2_active;
reg spc0_flush3_active;
reg spc0_intr0_active;
reg spc0_intr1_active;
reg spc0_intr2_active;
reg spc0_intr3_active;
always @(negedge clk)
begin
if(~rst_l)
begin
spc0_mbar0_active <= 1'b0;
spc0_mbar1_active <= 1'b0;
spc0_mbar2_active <= 1'b0;
spc0_mbar3_active <= 1'b0;
spc0_flush0_active <= 1'b0;
spc0_flush1_active <= 1'b0;
spc0_flush2_active <= 1'b0;
spc0_flush3_active <= 1'b0;
spc0_intr0_active <= 1'b0;
spc0_intr1_active <= 1'b0;
spc0_intr2_active <= 1'b0;
spc0_intr3_active <= 1'b0;
end
else
begin
if(spc0_mbar_inst0_g & ~spc0_dctl_flush_pipe_w & (C0T0_stb_ne|~spc0_no_spc_rmo_st[0]))
spc0_mbar0_active <= 1'b1;
else if(~C0T0_stb_ne & spc0_no_spc_rmo_st[0])
spc0_mbar0_active <= 1'b0;
if(spc0_mbar_inst1_g & ~ spc0_dctl_flush_pipe_w & (C0T1_stb_ne|~spc0_no_spc_rmo_st[1]))
spc0_mbar1_active <= 1'b1;
else if(~C0T1_stb_ne & spc0_no_spc_rmo_st[1])
spc0_mbar1_active <= 1'b0;
if(spc0_mbar_inst2_g & ~ spc0_dctl_flush_pipe_w & (C0T2_stb_ne|~spc0_no_spc_rmo_st[2]))
spc0_mbar2_active <= 1'b1;
else if(~C0T2_stb_ne & spc0_no_spc_rmo_st[2])
spc0_mbar2_active <= 1'b0;
if(spc0_mbar_inst3_g & ~ spc0_dctl_flush_pipe_w & (C0T3_stb_ne|~spc0_no_spc_rmo_st[3]))
spc0_mbar3_active <= 1'b1;
else if(~C0T3_stb_ne & spc0_no_spc_rmo_st[3])
spc0_mbar3_active <= 1'b0;
if(spc0_flush_inst0_g & ~spc0_dctl_flush_pipe_w & C0T0_stb_ne) spc0_flush0_active <= 1'b1;
else if(~C0T0_stb_ne) spc0_flush0_active <= 1'b0;
if(spc0_flush_inst1_g & ~spc0_dctl_flush_pipe_w & C0T1_stb_ne) spc0_flush1_active <= 1'b1;
else if(~C0T1_stb_ne) spc0_flush1_active <= 1'b0;
if(spc0_flush_inst2_g & ~spc0_dctl_flush_pipe_w & C0T2_stb_ne) spc0_flush2_active <= 1'b1;
else if(~C0T2_stb_ne) spc0_flush2_active <= 1'b0;
if(spc0_flush_inst3_g & ~spc0_dctl_flush_pipe_w & C0T3_stb_ne) spc0_flush3_active <= 1'b1;
else if(~C0T3_stb_ne) spc0_flush3_active <= 1'b0;
if(spc0_intrpt_disp_asi0_g & spc0_st_inst_vld_g & ~spc0_non_altspace_ldst_g & ~spc0_dctl_flush_pipe_w & C0T0_stb_ne)
spc0_intr0_active <= 1'b1;
else if(~C0T0_stb_ne)
spc0_intr0_active <= 1'b0;
if(spc0_intrpt_disp_asi1_g & spc0_st_inst_vld_g & ~spc0_non_altspace_ldst_g & ~spc0_dctl_flush_pipe_w & C0T1_stb_ne)
spc0_intr1_active <= 1'b1;
else if(~C0T1_stb_ne)
spc0_intr1_active <= 1'b0;
if(spc0_intrpt_disp_asi2_g & spc0_st_inst_vld_g & ~spc0_non_altspace_ldst_g & ~spc0_dctl_flush_pipe_w & C0T2_stb_ne)
spc0_intr2_active <= 1'b1;
else if(~C0T2_stb_ne)
spc0_intr2_active <= 1'b0;
if(spc0_intrpt_disp_asi3_g & spc0_st_inst_vld_g & ~spc0_non_altspace_ldst_g & ~spc0_dctl_flush_pipe_w & C0T3_stb_ne)
spc0_intr3_active <= 1'b1;
else if(~C0T3_stb_ne)
spc0_intr3_active <= 1'b0;
end
if(spc0_mbar0_active & spc0_inst_vld_w & spc0_sas_thrid_w[1:0] == 2'b00)
finish_test("spc", "membar violation thread 0", 0);
if(spc0_mbar1_active & spc0_inst_vld_w & spc0_sas_thrid_w[1:0] == 2'b01)
finish_test("spc", "membar violation thread 1", 0);
if(spc0_mbar2_active & spc0_inst_vld_w & spc0_sas_thrid_w[1:0] == 2'b10)
finish_test("spc", "membar violation thread 2", 0);
if(spc0_mbar3_active & spc0_inst_vld_w & spc0_sas_thrid_w[1:0] == 2'b11)
finish_test("spc", "membar violation thread 3", 0);
if(spc0_flush0_active & spc0_inst_vld_w & spc0_sas_thrid_w[1:0] == 2'b00)
finish_test("spc", "flush violation thread 0", 0);
if(spc0_flush1_active & spc0_inst_vld_w & spc0_sas_thrid_w[1:0] == 2'b01)
finish_test("spc", "flush violation thread 1", 0);
if(spc0_flush2_active & spc0_inst_vld_w & spc0_sas_thrid_w[1:0] == 2'b10)
finish_test("spc", "flush violation thread 2", 0);
if(spc0_flush3_active & spc0_inst_vld_w & spc0_sas_thrid_w[1:0] == 2'b11)
finish_test("spc", "flush violation thread 3", 0);
if(spc0_intr0_active & spc0_inst_vld_w & spc0_sas_thrid_w[1:0] == 2'b00)
finish_test("spc", "intr violation thread 0", 0);
if(spc0_intr1_active & spc0_inst_vld_w & spc0_sas_thrid_w[1:0] == 2'b01)
finish_test("spc", "intr violation thread 1", 0);
if(spc0_intr2_active & spc0_inst_vld_w & spc0_sas_thrid_w[1:0] == 2'b10)
finish_test("spc", "intr violation thread 2", 0);
if(spc0_intr3_active & spc0_inst_vld_w & spc0_sas_thrid_w[1:0] == 2'b11)
finish_test("spc", "intr violation thread 3", 0);
if(~rst_l | ~C0T0_stb_full | sctag_pcx_stall_pq) C0T0_stb_drain_cnt = 0;
else C0T0_stb_drain_cnt = C0T0_stb_drain_cnt + 1;
if(C0T0_stb_drain_cnt > stb_drain_to_max)
finish_test("spc", "stb 0 is not draining", 0);
if(~rst_l | ~C0T1_stb_full | sctag_pcx_stall_pq) C0T1_stb_drain_cnt = 0;
else C0T1_stb_drain_cnt = C0T1_stb_drain_cnt + 1;
if(C0T1_stb_drain_cnt > stb_drain_to_max)
finish_test("spc", "stb 1 is not draining", 0);
if(~rst_l | ~C0T2_stb_full | sctag_pcx_stall_pq) C0T2_stb_drain_cnt = 0;
else C0T2_stb_drain_cnt = C0T2_stb_drain_cnt + 1;
if(C0T2_stb_drain_cnt > stb_drain_to_max)
finish_test("spc", "stb 2 is not draining", 0);
if(~rst_l | ~C0T3_stb_full | sctag_pcx_stall_pq) C0T3_stb_drain_cnt = 0;
else C0T3_stb_drain_cnt = C0T3_stb_drain_cnt + 1;
if(C0T3_stb_drain_cnt > stb_drain_to_max)
finish_test("spc", "stb 3 is not draining", 0);
C0T0_stb_vld_sum_d1 <= C0T0_stb_vld_sum;
C0T1_stb_vld_sum_d1 <= C0T1_stb_vld_sum;
C0T2_stb_vld_sum_d1 <= C0T2_stb_vld_sum;
C0T3_stb_vld_sum_d1 <= C0T3_stb_vld_sum;
C0T0_defr_trp_en_d1 <= C0T0_defr_trp_en;
C0T1_defr_trp_en_d1 <= C0T1_defr_trp_en;
C0T2_defr_trp_en_d1 <= C0T2_defr_trp_en;
C0T3_defr_trp_en_d1 <= C0T3_defr_trp_en;
if(rst_l & C0T0_defr_trp_en_d1 & (C0T0_stb_vld_sum_d1 < C0T0_stb_vld_sum))
finish_test("spc", "tso_mon: deferred trap problems for store T0", 0);
if(rst_l & C0T1_defr_trp_en_d1 & (C0T1_stb_vld_sum_d1 < C0T1_stb_vld_sum))
finish_test("spc", "tso_mon: deferred trap problems for store T1", 0);
if(rst_l & C0T2_defr_trp_en_d1 & (C0T2_stb_vld_sum_d1 < C0T2_stb_vld_sum))
finish_test("spc", "tso_mon: deferred trap problems for store T2", 0);
if(rst_l & C0T3_defr_trp_en_d1 & (C0T3_stb_vld_sum_d1 < C0T3_stb_vld_sum))
finish_test("spc", "tso_mon: deferred trap problems for store T3", 0);
end
`endif // ifdef RTL_SPARC0
`ifdef RTL_SPARC1
wire C1T0_stb_ne = |`TOP_DESIGN.sparc1.lsu.stb_ctl0.stb_state_vld[7:0];
wire C1T1_stb_ne = |`TOP_DESIGN.sparc1.lsu.stb_ctl1.stb_state_vld[7:0];
wire C1T2_stb_ne = |`TOP_DESIGN.sparc1.lsu.stb_ctl2.stb_state_vld[7:0];
wire C1T3_stb_ne = |`TOP_DESIGN.sparc1.lsu.stb_ctl3.stb_state_vld[7:0];
wire C1T0_stb_nced = |( `TOP_DESIGN.sparc1.lsu.stb_ctl0.stb_state_vld[7:0] &
~`TOP_DESIGN.sparc1.lsu.stb_ctl0.stb_state_ced[7:0]);
wire C1T1_stb_nced = |( `TOP_DESIGN.sparc1.lsu.stb_ctl1.stb_state_vld[7:0] &
~`TOP_DESIGN.sparc1.lsu.stb_ctl1.stb_state_ced[7:0]);
wire C1T2_stb_nced = |( `TOP_DESIGN.sparc1.lsu.stb_ctl2.stb_state_vld[7:0] &
~`TOP_DESIGN.sparc1.lsu.stb_ctl2.stb_state_ced[7:0]);
wire C1T3_stb_nced = |( `TOP_DESIGN.sparc1.lsu.stb_ctl3.stb_state_vld[7:0] &
~`TOP_DESIGN.sparc1.lsu.stb_ctl3.stb_state_ced[7:0]);
`else
wire C1T0_stb_ne = 1'b0;
wire C1T1_stb_ne = 1'b0;
wire C1T2_stb_ne = 1'b0;
wire C1T3_stb_ne = 1'b0;
wire C1T0_stb_nced = 1'b0;
wire C1T1_stb_nced = 1'b0;
wire C1T2_stb_nced = 1'b0;
wire C1T3_stb_nced = 1'b0;
`endif // ifdef RTL_SPARC1
`ifdef RTL_SPARC1
wire spc1_lsu_ifill_pkt_vld = `TOP_DESIGN.sparc1.lsu.qctl2.lsu_ifill_pkt_vld;
wire spc1_dfq_rd_advance = `TOP_DESIGN.sparc1.lsu.qctl2.dfq_rd_advance;
wire spc1_dfq_int_type = `TOP_DESIGN.sparc1.lsu.qctl2.dfq_int_type;
wire spc1_ifu_lsu_inv_clear = `TOP_DESIGN.sparc1.lsu.qctl2.ifu_lsu_inv_clear;
wire spc1_dva_svld_e = `TOP_DESIGN.sparc1.lsu.qctl2.dva_svld_e;
wire spc1_dva_rvld_e = `TOP_DESIGN.sparc1.lsu.dva.rd_en;
wire [10:4] spc1_dva_rd_addr_e = `TOP_DESIGN.sparc1.lsu.dva.rd_adr1[6:0];
wire [4:0] spc1_dva_snp_addr_e = `TOP_DESIGN.sparc1.lsu.qctl2.dva_snp_addr_e[4:0];
wire [4:0] spc1_stb_data_rd_ptr = `TOP_DESIGN.sparc1.lsu.stb_data_rd_ptr[4:0];
wire [4:0] spc1_stb_data_wr_ptr = `TOP_DESIGN.sparc1.lsu.stb_data_wr_ptr[4:0];
wire spc1_stb_data_wptr_vld = `TOP_DESIGN.sparc1.lsu.stb_data_wptr_vld;
wire spc1_stb_data_rptr_vld = `TOP_DESIGN.sparc1.lsu.stb_data_rptr_vld;
wire spc1_stbrwctl_flush_pipe_w = `TOP_DESIGN.sparc1.lsu.stb_rwctl.lsu_stbrwctl_flush_pipe_w;
wire spc1_lsu_st_pcx_rq_pick = |`TOP_DESIGN.sparc1.lsu.stb_rwctl.lsu_st_pcx_rq_pick[3:0];
wire [3:0] spc1_lsu_rd_dtag_parity_g = `TOP_DESIGN.sparc1.lsu.dctl.lsu_rd_dtag_parity_g[3:0];
wire [3:0] spc1_dva_vld_g = `TOP_DESIGN.sparc1.lsu.dctl.dva_vld_g[3:0];
wire [3:0] spc1_lsu_dc_tag_pe_g_unmasked = spc1_lsu_rd_dtag_parity_g[3:0] & spc1_dva_vld_g[3:0];
wire spc1_lsu_dc_tag_pe_g_unmasked_or = |spc1_lsu_dc_tag_pe_g_unmasked[3:0];
wire C1T0_stb_full = &`TOP_DESIGN.sparc1.lsu.stb_ctl0.stb_state_vld[7:0];
wire C1T1_stb_full = &`TOP_DESIGN.sparc1.lsu.stb_ctl1.stb_state_vld[7:0];
wire C1T2_stb_full = &`TOP_DESIGN.sparc1.lsu.stb_ctl2.stb_state_vld[7:0];
wire C1T3_stb_full = &`TOP_DESIGN.sparc1.lsu.stb_ctl3.stb_state_vld[7:0];
wire [7:0] C1T0_stb_vld = `TOP_DESIGN.sparc1.lsu.stb_ctl0.stb_state_vld[7:0];
wire [7:0] C1T1_stb_vld = `TOP_DESIGN.sparc1.lsu.stb_ctl1.stb_state_vld[7:0];
wire [7:0] C1T2_stb_vld = `TOP_DESIGN.sparc1.lsu.stb_ctl2.stb_state_vld[7:0];
wire [7:0] C1T3_stb_vld = `TOP_DESIGN.sparc1.lsu.stb_ctl3.stb_state_vld[7:0];
wire [4:0] C1T0_stb_vld_sum = C1T0_stb_vld[0] + C1T0_stb_vld[1] + C1T0_stb_vld[2] + C1T0_stb_vld[3] +
C1T0_stb_vld[4] + C1T0_stb_vld[5] + C1T0_stb_vld[6] + C1T0_stb_vld[7] ;
wire [4:0] C1T1_stb_vld_sum = C1T1_stb_vld[0] + C1T1_stb_vld[1] + C1T1_stb_vld[2] + C1T1_stb_vld[3] +
C1T1_stb_vld[4] + C1T1_stb_vld[5] + C1T1_stb_vld[6] + C1T1_stb_vld[7] ;
wire [4:0] C1T2_stb_vld_sum = C1T2_stb_vld[0] + C1T2_stb_vld[1] + C1T2_stb_vld[2] + C1T2_stb_vld[3] +
C1T2_stb_vld[4] + C1T2_stb_vld[5] + C1T2_stb_vld[6] + C1T2_stb_vld[7] ;
wire [4:0] C1T3_stb_vld_sum = C1T3_stb_vld[0] + C1T3_stb_vld[1] + C1T3_stb_vld[2] + C1T3_stb_vld[3] +
C1T3_stb_vld[4] + C1T3_stb_vld[5] + C1T3_stb_vld[6] + C1T3_stb_vld[7] ;
reg [4:0] C1T0_stb_vld_sum_d1;
reg [4:0] C1T1_stb_vld_sum_d1;
reg [4:0] C1T2_stb_vld_sum_d1;
reg [4:0] C1T3_stb_vld_sum_d1;
wire C1T0_st_ack = &`TOP_DESIGN.sparc1.lsu.cpx_st_ack_tid0;
wire C1T1_st_ack = &`TOP_DESIGN.sparc1.lsu.cpx_st_ack_tid1;
wire C1T2_st_ack = &`TOP_DESIGN.sparc1.lsu.cpx_st_ack_tid2;
wire C1T3_st_ack = &`TOP_DESIGN.sparc1.lsu.cpx_st_ack_tid3;
wire C1T0_defr_trp_en = &`TOP_DESIGN.sparc1.lsu.excpctl.st_defr_trp_en0;
wire C1T1_defr_trp_en = &`TOP_DESIGN.sparc1.lsu.excpctl.st_defr_trp_en1;
wire C1T2_defr_trp_en = &`TOP_DESIGN.sparc1.lsu.excpctl.st_defr_trp_en2;
wire C1T3_defr_trp_en = &`TOP_DESIGN.sparc1.lsu.excpctl.st_defr_trp_en3;
reg C1T0_defr_trp_en_d1;
reg C1T1_defr_trp_en_d1;
reg C1T2_defr_trp_en_d1;
reg C1T3_defr_trp_en_d1;
integer C1T0_stb_drain_cnt;
integer C1T1_stb_drain_cnt;
integer C1T2_stb_drain_cnt;
integer C1T3_stb_drain_cnt;
// Hits in the store buffer
//-------------------------
wire spc1_inst_vld_w = `TOP_DESIGN.sparc1.ifu.fcl.inst_vld_w;
wire [1:0] spc1_sas_thrid_w = `TOP_DESIGN.sparc1.ifu.fcl.sas_thrid_w[1:0];
wire C1_st_ack_w = (spc1_sas_thrid_w == 2'b00) & C1T0_st_ack |
(spc1_sas_thrid_w == 2'b01) & C1T1_st_ack |
(spc1_sas_thrid_w == 2'b10) & C1T2_st_ack |
(spc1_sas_thrid_w == 2'b11) & C1T3_st_ack;
wire [7:0] spc1_stb_ld_full_raw = `TOP_DESIGN.sparc1.lsu.stb_ld_full_raw[7:0];
wire [7:0] spc1_stb_ld_partial_raw = `TOP_DESIGN.sparc1.lsu.stb_ld_partial_raw[7:0];
wire spc1_stb_cam_mhit = `TOP_DESIGN.sparc1.lsu.stb_cam_mhit;
wire spc1_stb_cam_hit = `TOP_DESIGN.sparc1.lsu.stb_cam_hit;
wire [3:0] spc1_lsu_way_hit = `TOP_DESIGN.sparc1.lsu.dctl.lsu_way_hit[3:0];
wire spc1_lsu_ifu_ldst_miss_w = `TOP_DESIGN.sparc1.lsu.lsu_ifu_ldst_miss_w;
wire spc1_ld_inst_vld_g = `TOP_DESIGN.sparc1.lsu.dctl.ld_inst_vld_g;
wire spc1_ldst_dbl_g = `TOP_DESIGN.sparc1.lsu.dctl.ldst_dbl_g;
wire spc1_quad_asi_g = `TOP_DESIGN.sparc1.lsu.dctl.quad_asi_g;
wire [1:0] spc1_ldst_sz_g = `TOP_DESIGN.sparc1.lsu.dctl.ldst_sz_g;
wire spc1_lsu_alt_space_g = `TOP_DESIGN.sparc1.lsu.dctl.lsu_alt_space_g;
wire spc1_mbar_inst0_g = `TOP_DESIGN.sparc1.lsu.dctl.mbar_inst0_g;
wire spc1_mbar_inst1_g = `TOP_DESIGN.sparc1.lsu.dctl.mbar_inst1_g;
wire spc1_mbar_inst2_g = `TOP_DESIGN.sparc1.lsu.dctl.mbar_inst2_g;
wire spc1_mbar_inst3_g = `TOP_DESIGN.sparc1.lsu.dctl.mbar_inst3_g;
wire spc1_flush_inst0_g = `TOP_DESIGN.sparc1.lsu.dctl.flush_inst0_g;
wire spc1_flush_inst1_g = `TOP_DESIGN.sparc1.lsu.dctl.flush_inst1_g;
wire spc1_flush_inst2_g = `TOP_DESIGN.sparc1.lsu.dctl.flush_inst2_g;
wire spc1_flush_inst3_g = `TOP_DESIGN.sparc1.lsu.dctl.flush_inst3_g;
wire spc1_intrpt_disp_asi0_g = `TOP_DESIGN.sparc1.lsu.dctl.intrpt_disp_asi_g & (spc1_sas_thrid_w == 2'b00);
wire spc1_intrpt_disp_asi1_g = `TOP_DESIGN.sparc1.lsu.dctl.intrpt_disp_asi_g & (spc1_sas_thrid_w == 2'b01);
wire spc1_intrpt_disp_asi2_g = `TOP_DESIGN.sparc1.lsu.dctl.intrpt_disp_asi_g & (spc1_sas_thrid_w == 2'b10);
wire spc1_intrpt_disp_asi3_g = `TOP_DESIGN.sparc1.lsu.dctl.intrpt_disp_asi_g & (spc1_sas_thrid_w == 2'b11);
wire spc1_st_inst_vld_g = `TOP_DESIGN.sparc1.lsu.dctl.st_inst_vld_g;
wire spc1_non_altspace_ldst_g = `TOP_DESIGN.sparc1.lsu.dctl.non_altspace_ldst_g;
wire spc1_dctl_flush_pipe_w = `TOP_DESIGN.sparc1.lsu.dctl.dctl_flush_pipe_w;
wire [3:0] spc1_no_spc_rmo_st = `TOP_DESIGN.sparc1.lsu.dctl.no_spc_rmo_st[3:0];
wire spc1_ldst_fp_e = `TOP_DESIGN.sparc1.lsu.ifu_lsu_ldst_fp_e;
wire [2:0] spc1_stb_rdptr = `TOP_DESIGN.sparc1.lsu.stb_rwctl.stb_rdptr_l;
wire spc1_ld_l2cache_req = `TOP_DESIGN.sparc1.lsu.qctl1.ld3_l2cache_rq |
`TOP_DESIGN.sparc1.lsu.qctl1.ld2_l2cache_rq |
`TOP_DESIGN.sparc1.lsu.qctl1.ld1_l2cache_rq |
`TOP_DESIGN.sparc1.lsu.qctl1.ld0_l2cache_rq;
wire [3:0] spc1_dcache_enable = {`TOP_DESIGN.sparc1.lsu.dctl.lsu_ctl_reg0[1],
`TOP_DESIGN.sparc1.lsu.dctl.lsu_ctl_reg1[1],
`TOP_DESIGN.sparc1.lsu.dctl.lsu_ctl_reg2[1],
`TOP_DESIGN.sparc1.lsu.dctl.lsu_ctl_reg3[1]};
wire [3:0] spc1_icache_enable = `TOP_DESIGN.sparc1.lsu.lsu_ifu_icache_en[3:0];
wire spc1_dc_direct_map = `TOP_DESIGN.sparc1.lsu.dc_direct_map;
wire spc1_lsu_ifu_direct_map_l1 = `TOP_DESIGN.sparc1.lsu.lsu_ifu_direct_map_l1;
always @(spc1_dcache_enable)
$display("%0d tso_mon: spc1_dcache_enable changed to %x", $time, spc1_dcache_enable);
always @(spc1_icache_enable)
$display("%0d tso_mon: spc1_icache_enable changed to %x", $time, spc1_icache_enable);
always @(spc1_dc_direct_map)
$display("%0d tso_mon: spc1_dc_direct_map changed to %x", $time, spc1_dc_direct_map);
always @(spc1_lsu_ifu_direct_map_l1)
$display("%0d tso_mon: spc1_lsu_ifu_direct_map_l1 changed to %x", $time, spc1_lsu_ifu_direct_map_l1);
reg spc1_dva_svld_e_d1;
reg spc1_dva_rvld_e_d1;
reg [10:4] spc1_dva_rd_addr_e_d1;
reg [4:0] spc1_dva_snp_addr_e_d1;
reg spc1_lsu_snp_after_rd;
reg spc1_lsu_rd_after_snp;
reg spc1_ldst_fp_m, spc1_ldst_fp_g;
integer spc1_multiple_hits;
reg spc1_skid_d1, spc1_skid_d2, spc1_skid_d3;
initial begin
spc1_skid_d1 = 0;
spc1_skid_d2 = 0;
spc1_skid_d3 = 0;
end
always @(posedge clk)
begin
spc1_skid_d1 <= (~spc1_ifu_lsu_inv_clear & spc1_dfq_rd_advance & spc1_dfq_int_type);
spc1_skid_d2 <= spc1_skid_d1 & ~spc1_ifu_lsu_inv_clear;
spc1_skid_d3 <= spc1_skid_d2 & ~spc1_ifu_lsu_inv_clear;
// The full tracking of this condition is complicated since after the interrupt is advanced
// there may be more invalidations to the IFQ.
// All we care about is that the invalidations BEFORE the interrupt are finished.
// I provided a command line argument to disable this check.
if(spc1_skid_d3 & enable_ifu_lsu_inv_clear)
finish_test("spc", "tso_mon: spc1_ifu_lsu_inv_clear should have been clear by now", 1);
spc1_dva_svld_e_d1 <= spc1_dva_svld_e;
spc1_dva_rvld_e_d1 <= spc1_dva_rvld_e;
spc1_dva_rd_addr_e_d1 <= spc1_dva_rd_addr_e;
spc1_dva_snp_addr_e_d1 <= spc1_dva_snp_addr_e;
if(spc1_dva_svld_e_d1 & spc1_dva_rvld_e & (spc1_dva_rd_addr_e_d1[10:6] == spc1_dva_snp_addr_e[4:0]))
spc1_lsu_rd_after_snp <= 1'b1;
else
spc1_lsu_rd_after_snp <= 1'b0;
if(spc1_dva_svld_e & spc1_dva_rvld_e_d1 & (spc1_dva_rd_addr_e[10:6] == spc1_dva_snp_addr_e_d1[4:0]))
spc1_lsu_snp_after_rd <= 1'b1;
else
spc1_lsu_snp_after_rd <= 1'b0;
spc1_ldst_fp_m <= spc1_ldst_fp_e;
spc1_ldst_fp_g <= spc1_ldst_fp_m;
if(spc1_stb_data_rptr_vld & spc1_stb_data_wptr_vld & ~spc1_stbrwctl_flush_pipe_w &
(spc1_stb_data_rd_ptr == spc1_stb_data_wr_ptr) & spc1_lsu_st_pcx_rq_pick)
begin
finish_test("spc", "tso_mon: LSU stb data write and read in the same cycle", 1);
end
spc1_multiple_hits = (spc1_lsu_way_hit[3] + spc1_lsu_way_hit[2] + spc1_lsu_way_hit[1] + spc1_lsu_way_hit[0]);
if(!spc1_lsu_ifu_ldst_miss_w && (spc1_multiple_hits >1) && spc1_inst_vld_w && !spc1_dctl_flush_pipe_w && !spc1_lsu_dc_tag_pe_g_unmasked_or)
finish_test("spc", "tso_mon: LSU multiple hits ", 1);
end
wire spc1_ld_dbl = spc1_ld_inst_vld_g & spc1_ldst_dbl_g & ~spc1_quad_asi_g;
wire spc1_ld_quad = spc1_ld_inst_vld_g & spc1_ldst_dbl_g & spc1_quad_asi_g;
wire spc1_ld_other = spc1_ld_inst_vld_g & ~spc1_ldst_dbl_g;
wire spc1_ld_dbl_fp = spc1_ld_dbl & spc1_ldst_fp_g;
wire spc1_ld_other_fp = spc1_ld_other & spc1_ldst_fp_g;
wire spc1_ld_dbl_int = spc1_ld_dbl & ~spc1_ldst_fp_g;
wire spc1_ld_quad_int = spc1_ld_quad & ~spc1_ldst_fp_g;
wire spc1_ld_other_int= spc1_ld_other & ~spc1_ldst_fp_g;
wire spc1_ld_bypassok_hit = |spc1_stb_ld_full_raw[7:0] & ~spc1_stb_cam_mhit;
wire spc1_ld_partial_hit = |spc1_stb_ld_partial_raw[7:0] & ~spc1_stb_cam_mhit;
wire spc1_ld_multiple_hit = spc1_stb_cam_mhit;
wire spc1_any_lsu_way_hit = |spc1_lsu_way_hit;
wire [7:0] spc1_stb_rdptr_decoded = (spc1_stb_rdptr ==3'b000) ? 8'b00000001 :
(spc1_stb_rdptr ==3'b001) ? 8'b00000010 :
(spc1_stb_rdptr ==3'b010) ? 8'b00000100 :
(spc1_stb_rdptr ==3'b011) ? 8'b00001000 :
(spc1_stb_rdptr ==3'b100) ? 8'b00010000 :
(spc1_stb_rdptr ==3'b101) ? 8'b00100000 :
(spc1_stb_rdptr ==3'b110) ? 8'b01000000 :
(spc1_stb_rdptr ==3'b111) ? 8'b10000000 : 8'h00;
wire spc1_stb_top_hit = |(spc1_stb_rdptr_decoded & (spc1_stb_ld_full_raw | spc1_stb_ld_partial_raw));
//---------------------------------------------------------------------
// ld_type[4:0] hit_type[2:0], cache_hit, hit_top
// this is passed to the coverage monitor.
//---------------------------------------------------------------------
wire [10:0] spc1_stb_ld_hit_info =
{spc1_ld_dbl_fp, spc1_ld_other_fp,
spc1_ld_dbl_int, spc1_ld_quad_int, spc1_ld_other_int,
spc1_ld_bypassok_hit, spc1_ld_partial_hit, spc1_ld_multiple_hit,
spc1_any_lsu_way_hit,
spc1_stb_top_hit, C1_st_ack_w};
reg spc1_mbar0_active;
reg spc1_mbar1_active;
reg spc1_mbar2_active;
reg spc1_mbar3_active;
reg spc1_flush0_active;
reg spc1_flush1_active;
reg spc1_flush2_active;
reg spc1_flush3_active;
reg spc1_intr0_active;
reg spc1_intr1_active;
reg spc1_intr2_active;
reg spc1_intr3_active;
always @(negedge clk)
begin
if(~rst_l)
begin
spc1_mbar0_active <= 1'b0;
spc1_mbar1_active <= 1'b0;
spc1_mbar2_active <= 1'b0;
spc1_mbar3_active <= 1'b0;
spc1_flush0_active <= 1'b0;
spc1_flush1_active <= 1'b0;
spc1_flush2_active <= 1'b0;
spc1_flush3_active <= 1'b0;
spc1_intr0_active <= 1'b0;
spc1_intr1_active <= 1'b0;
spc1_intr2_active <= 1'b0;
spc1_intr3_active <= 1'b0;
end
else
begin
if(spc1_mbar_inst0_g & ~spc1_dctl_flush_pipe_w & (C1T0_stb_ne|~spc1_no_spc_rmo_st[0]))
spc1_mbar0_active <= 1'b1;
else if(~C1T0_stb_ne & spc1_no_spc_rmo_st[0])
spc1_mbar0_active <= 1'b0;
if(spc1_mbar_inst1_g & ~ spc1_dctl_flush_pipe_w & (C1T1_stb_ne|~spc1_no_spc_rmo_st[1]))
spc1_mbar1_active <= 1'b1;
else if(~C1T1_stb_ne & spc1_no_spc_rmo_st[1])
spc1_mbar1_active <= 1'b0;
if(spc1_mbar_inst2_g & ~ spc1_dctl_flush_pipe_w & (C1T2_stb_ne|~spc1_no_spc_rmo_st[2]))
spc1_mbar2_active <= 1'b1;
else if(~C1T2_stb_ne & spc1_no_spc_rmo_st[2])
spc1_mbar2_active <= 1'b0;
if(spc1_mbar_inst3_g & ~ spc1_dctl_flush_pipe_w & (C1T3_stb_ne|~spc1_no_spc_rmo_st[3]))
spc1_mbar3_active <= 1'b1;
else if(~C1T3_stb_ne & spc1_no_spc_rmo_st[3])
spc1_mbar3_active <= 1'b0;
if(spc1_flush_inst0_g & ~spc1_dctl_flush_pipe_w & C1T0_stb_ne) spc1_flush0_active <= 1'b1;
else if(~C1T0_stb_ne) spc1_flush0_active <= 1'b0;
if(spc1_flush_inst1_g & ~spc1_dctl_flush_pipe_w & C1T1_stb_ne) spc1_flush1_active <= 1'b1;
else if(~C1T1_stb_ne) spc1_flush1_active <= 1'b0;
if(spc1_flush_inst2_g & ~spc1_dctl_flush_pipe_w & C1T2_stb_ne) spc1_flush2_active <= 1'b1;
else if(~C1T2_stb_ne) spc1_flush2_active <= 1'b0;
if(spc1_flush_inst3_g & ~spc1_dctl_flush_pipe_w & C1T3_stb_ne) spc1_flush3_active <= 1'b1;
else if(~C1T3_stb_ne) spc1_flush3_active <= 1'b0;
if(spc1_intrpt_disp_asi0_g & spc1_st_inst_vld_g & ~spc1_non_altspace_ldst_g & ~spc1_dctl_flush_pipe_w & C1T0_stb_ne)
spc1_intr0_active <= 1'b1;
else if(~C1T0_stb_ne)
spc1_intr0_active <= 1'b0;
if(spc1_intrpt_disp_asi1_g & spc1_st_inst_vld_g & ~spc1_non_altspace_ldst_g & ~spc1_dctl_flush_pipe_w & C1T1_stb_ne)
spc1_intr1_active <= 1'b1;
else if(~C1T1_stb_ne)
spc1_intr1_active <= 1'b0;
if(spc1_intrpt_disp_asi2_g & spc1_st_inst_vld_g & ~spc1_non_altspace_ldst_g & ~spc1_dctl_flush_pipe_w & C1T2_stb_ne)
spc1_intr2_active <= 1'b1;
else if(~C1T2_stb_ne)
spc1_intr2_active <= 1'b0;
if(spc1_intrpt_disp_asi3_g & spc1_st_inst_vld_g & ~spc1_non_altspace_ldst_g & ~spc1_dctl_flush_pipe_w & C1T3_stb_ne)
spc1_intr3_active <= 1'b1;
else if(~C1T3_stb_ne)
spc1_intr3_active <= 1'b0;
end
if(spc1_mbar0_active & spc1_inst_vld_w & spc1_sas_thrid_w[1:0] == 2'b00)
finish_test("spc", "membar violation thread 0", 1);
if(spc1_mbar1_active & spc1_inst_vld_w & spc1_sas_thrid_w[1:0] == 2'b01)
finish_test("spc", "membar violation thread 1", 1);
if(spc1_mbar2_active & spc1_inst_vld_w & spc1_sas_thrid_w[1:0] == 2'b10)
finish_test("spc", "membar violation thread 2", 1);
if(spc1_mbar3_active & spc1_inst_vld_w & spc1_sas_thrid_w[1:0] == 2'b11)
finish_test("spc", "membar violation thread 3", 1);
if(spc1_flush0_active & spc1_inst_vld_w & spc1_sas_thrid_w[1:0] == 2'b00)
finish_test("spc", "flush violation thread 0", 1);
if(spc1_flush1_active & spc1_inst_vld_w & spc1_sas_thrid_w[1:0] == 2'b01)
finish_test("spc", "flush violation thread 1", 1);
if(spc1_flush2_active & spc1_inst_vld_w & spc1_sas_thrid_w[1:0] == 2'b10)
finish_test("spc", "flush violation thread 2", 1);
if(spc1_flush3_active & spc1_inst_vld_w & spc1_sas_thrid_w[1:0] == 2'b11)
finish_test("spc", "flush violation thread 3", 1);
if(spc1_intr0_active & spc1_inst_vld_w & spc1_sas_thrid_w[1:0] == 2'b00)
finish_test("spc", "intr violation thread 0", 1);
if(spc1_intr1_active & spc1_inst_vld_w & spc1_sas_thrid_w[1:0] == 2'b01)
finish_test("spc", "intr violation thread 1", 1);
if(spc1_intr2_active & spc1_inst_vld_w & spc1_sas_thrid_w[1:0] == 2'b10)
finish_test("spc", "intr violation thread 2", 1);
if(spc1_intr3_active & spc1_inst_vld_w & spc1_sas_thrid_w[1:0] == 2'b11)
finish_test("spc", "intr violation thread 3", 1);
if(~rst_l | ~C1T0_stb_full | sctag_pcx_stall_pq) C1T0_stb_drain_cnt = 0;
else C1T0_stb_drain_cnt = C1T0_stb_drain_cnt + 1;
if(C1T0_stb_drain_cnt > stb_drain_to_max)
finish_test("spc", "stb 0 is not draining", 1);
if(~rst_l | ~C1T1_stb_full | sctag_pcx_stall_pq) C1T1_stb_drain_cnt = 0;
else C1T1_stb_drain_cnt = C1T1_stb_drain_cnt + 1;
if(C1T1_stb_drain_cnt > stb_drain_to_max)
finish_test("spc", "stb 1 is not draining", 1);
if(~rst_l | ~C1T2_stb_full | sctag_pcx_stall_pq) C1T2_stb_drain_cnt = 0;
else C1T2_stb_drain_cnt = C1T2_stb_drain_cnt + 1;
if(C1T2_stb_drain_cnt > stb_drain_to_max)
finish_test("spc", "stb 2 is not draining", 1);
if(~rst_l | ~C1T3_stb_full | sctag_pcx_stall_pq) C1T3_stb_drain_cnt = 0;
else C1T3_stb_drain_cnt = C1T3_stb_drain_cnt + 1;
if(C1T3_stb_drain_cnt > stb_drain_to_max)
finish_test("spc", "stb 3 is not draining", 1);
C1T0_stb_vld_sum_d1 <= C1T0_stb_vld_sum;
C1T1_stb_vld_sum_d1 <= C1T1_stb_vld_sum;
C1T2_stb_vld_sum_d1 <= C1T2_stb_vld_sum;
C1T3_stb_vld_sum_d1 <= C1T3_stb_vld_sum;
C1T0_defr_trp_en_d1 <= C1T0_defr_trp_en;
C1T1_defr_trp_en_d1 <= C1T1_defr_trp_en;
C1T2_defr_trp_en_d1 <= C1T2_defr_trp_en;
C1T3_defr_trp_en_d1 <= C1T3_defr_trp_en;
if(rst_l & C1T0_defr_trp_en_d1 & (C1T0_stb_vld_sum_d1 < C1T0_stb_vld_sum))
finish_test("spc", "tso_mon: deferred trap problems for store T0", 1);
if(rst_l & C1T1_defr_trp_en_d1 & (C1T1_stb_vld_sum_d1 < C1T1_stb_vld_sum))
finish_test("spc", "tso_mon: deferred trap problems for store T1", 1);
if(rst_l & C1T2_defr_trp_en_d1 & (C1T2_stb_vld_sum_d1 < C1T2_stb_vld_sum))
finish_test("spc", "tso_mon: deferred trap problems for store T2", 1);
if(rst_l & C1T3_defr_trp_en_d1 & (C1T3_stb_vld_sum_d1 < C1T3_stb_vld_sum))
finish_test("spc", "tso_mon: deferred trap problems for store T3", 1);
end
`endif // ifdef RTL_SPARC1
`ifdef RTL_SPARC2
wire C2T0_stb_ne = |`TOP_DESIGN.sparc2.lsu.stb_ctl0.stb_state_vld[7:0];
wire C2T1_stb_ne = |`TOP_DESIGN.sparc2.lsu.stb_ctl1.stb_state_vld[7:0];
wire C2T2_stb_ne = |`TOP_DESIGN.sparc2.lsu.stb_ctl2.stb_state_vld[7:0];
wire C2T3_stb_ne = |`TOP_DESIGN.sparc2.lsu.stb_ctl3.stb_state_vld[7:0];
wire C2T0_stb_nced = |( `TOP_DESIGN.sparc2.lsu.stb_ctl0.stb_state_vld[7:0] &
~`TOP_DESIGN.sparc2.lsu.stb_ctl0.stb_state_ced[7:0]);
wire C2T1_stb_nced = |( `TOP_DESIGN.sparc2.lsu.stb_ctl1.stb_state_vld[7:0] &
~`TOP_DESIGN.sparc2.lsu.stb_ctl1.stb_state_ced[7:0]);
wire C2T2_stb_nced = |( `TOP_DESIGN.sparc2.lsu.stb_ctl2.stb_state_vld[7:0] &
~`TOP_DESIGN.sparc2.lsu.stb_ctl2.stb_state_ced[7:0]);
wire C2T3_stb_nced = |( `TOP_DESIGN.sparc2.lsu.stb_ctl3.stb_state_vld[7:0] &
~`TOP_DESIGN.sparc2.lsu.stb_ctl3.stb_state_ced[7:0]);
`else
wire C2T0_stb_ne = 1'b0;
wire C2T1_stb_ne = 1'b0;
wire C2T2_stb_ne = 1'b0;
wire C2T3_stb_ne = 1'b0;
wire C2T0_stb_nced = 1'b0;
wire C2T1_stb_nced = 1'b0;
wire C2T2_stb_nced = 1'b0;
wire C2T3_stb_nced = 1'b0;
`endif // ifdef RTL_SPARC2
`ifdef RTL_SPARC2
wire spc2_lsu_ifill_pkt_vld = `TOP_DESIGN.sparc2.lsu.qctl2.lsu_ifill_pkt_vld;
wire spc2_dfq_rd_advance = `TOP_DESIGN.sparc2.lsu.qctl2.dfq_rd_advance;
wire spc2_dfq_int_type = `TOP_DESIGN.sparc2.lsu.qctl2.dfq_int_type;
wire spc2_ifu_lsu_inv_clear = `TOP_DESIGN.sparc2.lsu.qctl2.ifu_lsu_inv_clear;
wire spc2_dva_svld_e = `TOP_DESIGN.sparc2.lsu.qctl2.dva_svld_e;
wire spc2_dva_rvld_e = `TOP_DESIGN.sparc2.lsu.dva.rd_en;
wire [10:4] spc2_dva_rd_addr_e = `TOP_DESIGN.sparc2.lsu.dva.rd_adr1[6:0];
wire [4:0] spc2_dva_snp_addr_e = `TOP_DESIGN.sparc2.lsu.qctl2.dva_snp_addr_e[4:0];
wire [4:0] spc2_stb_data_rd_ptr = `TOP_DESIGN.sparc2.lsu.stb_data_rd_ptr[4:0];
wire [4:0] spc2_stb_data_wr_ptr = `TOP_DESIGN.sparc2.lsu.stb_data_wr_ptr[4:0];
wire spc2_stb_data_wptr_vld = `TOP_DESIGN.sparc2.lsu.stb_data_wptr_vld;
wire spc2_stb_data_rptr_vld = `TOP_DESIGN.sparc2.lsu.stb_data_rptr_vld;
wire spc2_stbrwctl_flush_pipe_w = `TOP_DESIGN.sparc2.lsu.stb_rwctl.lsu_stbrwctl_flush_pipe_w;
wire spc2_lsu_st_pcx_rq_pick = |`TOP_DESIGN.sparc2.lsu.stb_rwctl.lsu_st_pcx_rq_pick[3:0];
wire [3:0] spc2_lsu_rd_dtag_parity_g = `TOP_DESIGN.sparc2.lsu.dctl.lsu_rd_dtag_parity_g[3:0];
wire [3:0] spc2_dva_vld_g = `TOP_DESIGN.sparc2.lsu.dctl.dva_vld_g[3:0];
wire [3:0] spc2_lsu_dc_tag_pe_g_unmasked = spc2_lsu_rd_dtag_parity_g[3:0] & spc2_dva_vld_g[3:0];
wire spc2_lsu_dc_tag_pe_g_unmasked_or = |spc2_lsu_dc_tag_pe_g_unmasked[3:0];
wire C2T0_stb_full = &`TOP_DESIGN.sparc2.lsu.stb_ctl0.stb_state_vld[7:0];
wire C2T1_stb_full = &`TOP_DESIGN.sparc2.lsu.stb_ctl1.stb_state_vld[7:0];
wire C2T2_stb_full = &`TOP_DESIGN.sparc2.lsu.stb_ctl2.stb_state_vld[7:0];
wire C2T3_stb_full = &`TOP_DESIGN.sparc2.lsu.stb_ctl3.stb_state_vld[7:0];
wire [7:0] C2T0_stb_vld = `TOP_DESIGN.sparc2.lsu.stb_ctl0.stb_state_vld[7:0];
wire [7:0] C2T1_stb_vld = `TOP_DESIGN.sparc2.lsu.stb_ctl1.stb_state_vld[7:0];
wire [7:0] C2T2_stb_vld = `TOP_DESIGN.sparc2.lsu.stb_ctl2.stb_state_vld[7:0];
wire [7:0] C2T3_stb_vld = `TOP_DESIGN.sparc2.lsu.stb_ctl3.stb_state_vld[7:0];
wire [4:0] C2T0_stb_vld_sum = C2T0_stb_vld[0] + C2T0_stb_vld[1] + C2T0_stb_vld[2] + C2T0_stb_vld[3] +
C2T0_stb_vld[4] + C2T0_stb_vld[5] + C2T0_stb_vld[6] + C2T0_stb_vld[7] ;
wire [4:0] C2T1_stb_vld_sum = C2T1_stb_vld[0] + C2T1_stb_vld[1] + C2T1_stb_vld[2] + C2T1_stb_vld[3] +
C2T1_stb_vld[4] + C2T1_stb_vld[5] + C2T1_stb_vld[6] + C2T1_stb_vld[7] ;
wire [4:0] C2T2_stb_vld_sum = C2T2_stb_vld[0] + C2T2_stb_vld[1] + C2T2_stb_vld[2] + C2T2_stb_vld[3] +
C2T2_stb_vld[4] + C2T2_stb_vld[5] + C2T2_stb_vld[6] + C2T2_stb_vld[7] ;
wire [4:0] C2T3_stb_vld_sum = C2T3_stb_vld[0] + C2T3_stb_vld[1] + C2T3_stb_vld[2] + C2T3_stb_vld[3] +
C2T3_stb_vld[4] + C2T3_stb_vld[5] + C2T3_stb_vld[6] + C2T3_stb_vld[7] ;
reg [4:0] C2T0_stb_vld_sum_d1;
reg [4:0] C2T1_stb_vld_sum_d1;
reg [4:0] C2T2_stb_vld_sum_d1;
reg [4:0] C2T3_stb_vld_sum_d1;
wire C2T0_st_ack = &`TOP_DESIGN.sparc2.lsu.cpx_st_ack_tid0;
wire C2T1_st_ack = &`TOP_DESIGN.sparc2.lsu.cpx_st_ack_tid1;
wire C2T2_st_ack = &`TOP_DESIGN.sparc2.lsu.cpx_st_ack_tid2;
wire C2T3_st_ack = &`TOP_DESIGN.sparc2.lsu.cpx_st_ack_tid3;
wire C2T0_defr_trp_en = &`TOP_DESIGN.sparc2.lsu.excpctl.st_defr_trp_en0;
wire C2T1_defr_trp_en = &`TOP_DESIGN.sparc2.lsu.excpctl.st_defr_trp_en1;
wire C2T2_defr_trp_en = &`TOP_DESIGN.sparc2.lsu.excpctl.st_defr_trp_en2;
wire C2T3_defr_trp_en = &`TOP_DESIGN.sparc2.lsu.excpctl.st_defr_trp_en3;
reg C2T0_defr_trp_en_d1;
reg C2T1_defr_trp_en_d1;
reg C2T2_defr_trp_en_d1;
reg C2T3_defr_trp_en_d1;
integer C2T0_stb_drain_cnt;
integer C2T1_stb_drain_cnt;
integer C2T2_stb_drain_cnt;
integer C2T3_stb_drain_cnt;
// Hits in the store buffer
//-------------------------
wire spc2_inst_vld_w = `TOP_DESIGN.sparc2.ifu.fcl.inst_vld_w;
wire [1:0] spc2_sas_thrid_w = `TOP_DESIGN.sparc2.ifu.fcl.sas_thrid_w[1:0];
wire C2_st_ack_w = (spc2_sas_thrid_w == 2'b00) & C2T0_st_ack |
(spc2_sas_thrid_w == 2'b01) & C2T1_st_ack |
(spc2_sas_thrid_w == 2'b10) & C2T2_st_ack |
(spc2_sas_thrid_w == 2'b11) & C2T3_st_ack;
wire [7:0] spc2_stb_ld_full_raw = `TOP_DESIGN.sparc2.lsu.stb_ld_full_raw[7:0];
wire [7:0] spc2_stb_ld_partial_raw = `TOP_DESIGN.sparc2.lsu.stb_ld_partial_raw[7:0];
wire spc2_stb_cam_mhit = `TOP_DESIGN.sparc2.lsu.stb_cam_mhit;
wire spc2_stb_cam_hit = `TOP_DESIGN.sparc2.lsu.stb_cam_hit;
wire [3:0] spc2_lsu_way_hit = `TOP_DESIGN.sparc2.lsu.dctl.lsu_way_hit[3:0];
wire spc2_lsu_ifu_ldst_miss_w = `TOP_DESIGN.sparc2.lsu.lsu_ifu_ldst_miss_w;
wire spc2_ld_inst_vld_g = `TOP_DESIGN.sparc2.lsu.dctl.ld_inst_vld_g;
wire spc2_ldst_dbl_g = `TOP_DESIGN.sparc2.lsu.dctl.ldst_dbl_g;
wire spc2_quad_asi_g = `TOP_DESIGN.sparc2.lsu.dctl.quad_asi_g;
wire [1:0] spc2_ldst_sz_g = `TOP_DESIGN.sparc2.lsu.dctl.ldst_sz_g;
wire spc2_lsu_alt_space_g = `TOP_DESIGN.sparc2.lsu.dctl.lsu_alt_space_g;
wire spc2_mbar_inst0_g = `TOP_DESIGN.sparc2.lsu.dctl.mbar_inst0_g;
wire spc2_mbar_inst1_g = `TOP_DESIGN.sparc2.lsu.dctl.mbar_inst1_g;
wire spc2_mbar_inst2_g = `TOP_DESIGN.sparc2.lsu.dctl.mbar_inst2_g;
wire spc2_mbar_inst3_g = `TOP_DESIGN.sparc2.lsu.dctl.mbar_inst3_g;
wire spc2_flush_inst0_g = `TOP_DESIGN.sparc2.lsu.dctl.flush_inst0_g;
wire spc2_flush_inst1_g = `TOP_DESIGN.sparc2.lsu.dctl.flush_inst1_g;
wire spc2_flush_inst2_g = `TOP_DESIGN.sparc2.lsu.dctl.flush_inst2_g;
wire spc2_flush_inst3_g = `TOP_DESIGN.sparc2.lsu.dctl.flush_inst3_g;
wire spc2_intrpt_disp_asi0_g = `TOP_DESIGN.sparc2.lsu.dctl.intrpt_disp_asi_g & (spc2_sas_thrid_w == 2'b00);
wire spc2_intrpt_disp_asi1_g = `TOP_DESIGN.sparc2.lsu.dctl.intrpt_disp_asi_g & (spc2_sas_thrid_w == 2'b01);
wire spc2_intrpt_disp_asi2_g = `TOP_DESIGN.sparc2.lsu.dctl.intrpt_disp_asi_g & (spc2_sas_thrid_w == 2'b10);
wire spc2_intrpt_disp_asi3_g = `TOP_DESIGN.sparc2.lsu.dctl.intrpt_disp_asi_g & (spc2_sas_thrid_w == 2'b11);
wire spc2_st_inst_vld_g = `TOP_DESIGN.sparc2.lsu.dctl.st_inst_vld_g;
wire spc2_non_altspace_ldst_g = `TOP_DESIGN.sparc2.lsu.dctl.non_altspace_ldst_g;
wire spc2_dctl_flush_pipe_w = `TOP_DESIGN.sparc2.lsu.dctl.dctl_flush_pipe_w;
wire [3:0] spc2_no_spc_rmo_st = `TOP_DESIGN.sparc2.lsu.dctl.no_spc_rmo_st[3:0];
wire spc2_ldst_fp_e = `TOP_DESIGN.sparc2.lsu.ifu_lsu_ldst_fp_e;
wire [2:0] spc2_stb_rdptr = `TOP_DESIGN.sparc2.lsu.stb_rwctl.stb_rdptr_l;
wire spc2_ld_l2cache_req = `TOP_DESIGN.sparc2.lsu.qctl1.ld3_l2cache_rq |
`TOP_DESIGN.sparc2.lsu.qctl1.ld2_l2cache_rq |
`TOP_DESIGN.sparc2.lsu.qctl1.ld1_l2cache_rq |
`TOP_DESIGN.sparc2.lsu.qctl1.ld0_l2cache_rq;
wire [3:0] spc2_dcache_enable = {`TOP_DESIGN.sparc2.lsu.dctl.lsu_ctl_reg0[1],
`TOP_DESIGN.sparc2.lsu.dctl.lsu_ctl_reg1[1],
`TOP_DESIGN.sparc2.lsu.dctl.lsu_ctl_reg2[1],
`TOP_DESIGN.sparc2.lsu.dctl.lsu_ctl_reg3[1]};
wire [3:0] spc2_icache_enable = `TOP_DESIGN.sparc2.lsu.lsu_ifu_icache_en[3:0];
wire spc2_dc_direct_map = `TOP_DESIGN.sparc2.lsu.dc_direct_map;
wire spc2_lsu_ifu_direct_map_l1 = `TOP_DESIGN.sparc2.lsu.lsu_ifu_direct_map_l1;
always @(spc2_dcache_enable)
$display("%0d tso_mon: spc2_dcache_enable changed to %x", $time, spc2_dcache_enable);
always @(spc2_icache_enable)
$display("%0d tso_mon: spc2_icache_enable changed to %x", $time, spc2_icache_enable);
always @(spc2_dc_direct_map)
$display("%0d tso_mon: spc2_dc_direct_map changed to %x", $time, spc2_dc_direct_map);
always @(spc2_lsu_ifu_direct_map_l1)
$display("%0d tso_mon: spc2_lsu_ifu_direct_map_l1 changed to %x", $time, spc2_lsu_ifu_direct_map_l1);
reg spc2_dva_svld_e_d1;
reg spc2_dva_rvld_e_d1;
reg [10:4] spc2_dva_rd_addr_e_d1;
reg [4:0] spc2_dva_snp_addr_e_d1;
reg spc2_lsu_snp_after_rd;
reg spc2_lsu_rd_after_snp;
reg spc2_ldst_fp_m, spc2_ldst_fp_g;
integer spc2_multiple_hits;
reg spc2_skid_d1, spc2_skid_d2, spc2_skid_d3;
initial begin
spc2_skid_d1 = 0;
spc2_skid_d2 = 0;
spc2_skid_d3 = 0;
end
always @(posedge clk)
begin
spc2_skid_d1 <= (~spc2_ifu_lsu_inv_clear & spc2_dfq_rd_advance & spc2_dfq_int_type);
spc2_skid_d2 <= spc2_skid_d1 & ~spc2_ifu_lsu_inv_clear;
spc2_skid_d3 <= spc2_skid_d2 & ~spc2_ifu_lsu_inv_clear;
// The full tracking of this condition is complicated since after the interrupt is advanced
// there may be more invalidations to the IFQ.
// All we care about is that the invalidations BEFORE the interrupt are finished.
// I provided a command line argument to disable this check.
if(spc2_skid_d3 & enable_ifu_lsu_inv_clear)
finish_test("spc", "tso_mon: spc2_ifu_lsu_inv_clear should have been clear by now", 2);
spc2_dva_svld_e_d1 <= spc2_dva_svld_e;
spc2_dva_rvld_e_d1 <= spc2_dva_rvld_e;
spc2_dva_rd_addr_e_d1 <= spc2_dva_rd_addr_e;
spc2_dva_snp_addr_e_d1 <= spc2_dva_snp_addr_e;
if(spc2_dva_svld_e_d1 & spc2_dva_rvld_e & (spc2_dva_rd_addr_e_d1[10:6] == spc2_dva_snp_addr_e[4:0]))
spc2_lsu_rd_after_snp <= 1'b1;
else
spc2_lsu_rd_after_snp <= 1'b0;
if(spc2_dva_svld_e & spc2_dva_rvld_e_d1 & (spc2_dva_rd_addr_e[10:6] == spc2_dva_snp_addr_e_d1[4:0]))
spc2_lsu_snp_after_rd <= 1'b1;
else
spc2_lsu_snp_after_rd <= 1'b0;
spc2_ldst_fp_m <= spc2_ldst_fp_e;
spc2_ldst_fp_g <= spc2_ldst_fp_m;
if(spc2_stb_data_rptr_vld & spc2_stb_data_wptr_vld & ~spc2_stbrwctl_flush_pipe_w &
(spc2_stb_data_rd_ptr == spc2_stb_data_wr_ptr) & spc2_lsu_st_pcx_rq_pick)
begin
finish_test("spc", "tso_mon: LSU stb data write and read in the same cycle", 2);
end
spc2_multiple_hits = (spc2_lsu_way_hit[3] + spc2_lsu_way_hit[2] + spc2_lsu_way_hit[1] + spc2_lsu_way_hit[0]);
if(!spc2_lsu_ifu_ldst_miss_w && (spc2_multiple_hits >1) && spc2_inst_vld_w && !spc2_dctl_flush_pipe_w && !spc2_lsu_dc_tag_pe_g_unmasked_or)
finish_test("spc", "tso_mon: LSU multiple hits ", 2);
end
wire spc2_ld_dbl = spc2_ld_inst_vld_g & spc2_ldst_dbl_g & ~spc2_quad_asi_g;
wire spc2_ld_quad = spc2_ld_inst_vld_g & spc2_ldst_dbl_g & spc2_quad_asi_g;
wire spc2_ld_other = spc2_ld_inst_vld_g & ~spc2_ldst_dbl_g;
wire spc2_ld_dbl_fp = spc2_ld_dbl & spc2_ldst_fp_g;
wire spc2_ld_other_fp = spc2_ld_other & spc2_ldst_fp_g;
wire spc2_ld_dbl_int = spc2_ld_dbl & ~spc2_ldst_fp_g;
wire spc2_ld_quad_int = spc2_ld_quad & ~spc2_ldst_fp_g;
wire spc2_ld_other_int= spc2_ld_other & ~spc2_ldst_fp_g;
wire spc2_ld_bypassok_hit = |spc2_stb_ld_full_raw[7:0] & ~spc2_stb_cam_mhit;
wire spc2_ld_partial_hit = |spc2_stb_ld_partial_raw[7:0] & ~spc2_stb_cam_mhit;
wire spc2_ld_multiple_hit = spc2_stb_cam_mhit;
wire spc2_any_lsu_way_hit = |spc2_lsu_way_hit;
wire [7:0] spc2_stb_rdptr_decoded = (spc2_stb_rdptr ==3'b000) ? 8'b00000001 :
(spc2_stb_rdptr ==3'b001) ? 8'b00000010 :
(spc2_stb_rdptr ==3'b010) ? 8'b00000100 :
(spc2_stb_rdptr ==3'b011) ? 8'b00001000 :
(spc2_stb_rdptr ==3'b100) ? 8'b00010000 :
(spc2_stb_rdptr ==3'b101) ? 8'b00100000 :
(spc2_stb_rdptr ==3'b110) ? 8'b01000000 :
(spc2_stb_rdptr ==3'b111) ? 8'b10000000 : 8'h00;
wire spc2_stb_top_hit = |(spc2_stb_rdptr_decoded & (spc2_stb_ld_full_raw | spc2_stb_ld_partial_raw));
//---------------------------------------------------------------------
// ld_type[4:0] hit_type[2:0], cache_hit, hit_top
// this is passed to the coverage monitor.
//---------------------------------------------------------------------
wire [10:0] spc2_stb_ld_hit_info =
{spc2_ld_dbl_fp, spc2_ld_other_fp,
spc2_ld_dbl_int, spc2_ld_quad_int, spc2_ld_other_int,
spc2_ld_bypassok_hit, spc2_ld_partial_hit, spc2_ld_multiple_hit,
spc2_any_lsu_way_hit,
spc2_stb_top_hit, C2_st_ack_w};
reg spc2_mbar0_active;
reg spc2_mbar1_active;
reg spc2_mbar2_active;
reg spc2_mbar3_active;
reg spc2_flush0_active;
reg spc2_flush1_active;
reg spc2_flush2_active;
reg spc2_flush3_active;
reg spc2_intr0_active;
reg spc2_intr1_active;
reg spc2_intr2_active;
reg spc2_intr3_active;
always @(negedge clk)
begin
if(~rst_l)
begin
spc2_mbar0_active <= 1'b0;
spc2_mbar1_active <= 1'b0;
spc2_mbar2_active <= 1'b0;
spc2_mbar3_active <= 1'b0;
spc2_flush0_active <= 1'b0;
spc2_flush1_active <= 1'b0;
spc2_flush2_active <= 1'b0;
spc2_flush3_active <= 1'b0;
spc2_intr0_active <= 1'b0;
spc2_intr1_active <= 1'b0;
spc2_intr2_active <= 1'b0;
spc2_intr3_active <= 1'b0;
end
else
begin
if(spc2_mbar_inst0_g & ~spc2_dctl_flush_pipe_w & (C2T0_stb_ne|~spc2_no_spc_rmo_st[0]))
spc2_mbar0_active <= 1'b1;
else if(~C2T0_stb_ne & spc2_no_spc_rmo_st[0])
spc2_mbar0_active <= 1'b0;
if(spc2_mbar_inst1_g & ~ spc2_dctl_flush_pipe_w & (C2T1_stb_ne|~spc2_no_spc_rmo_st[1]))
spc2_mbar1_active <= 1'b1;
else if(~C2T1_stb_ne & spc2_no_spc_rmo_st[1])
spc2_mbar1_active <= 1'b0;
if(spc2_mbar_inst2_g & ~ spc2_dctl_flush_pipe_w & (C2T2_stb_ne|~spc2_no_spc_rmo_st[2]))
spc2_mbar2_active <= 1'b1;
else if(~C2T2_stb_ne & spc2_no_spc_rmo_st[2])
spc2_mbar2_active <= 1'b0;
if(spc2_mbar_inst3_g & ~ spc2_dctl_flush_pipe_w & (C2T3_stb_ne|~spc2_no_spc_rmo_st[3]))
spc2_mbar3_active <= 1'b1;
else if(~C2T3_stb_ne & spc2_no_spc_rmo_st[3])
spc2_mbar3_active <= 1'b0;
if(spc2_flush_inst0_g & ~spc2_dctl_flush_pipe_w & C2T0_stb_ne) spc2_flush0_active <= 1'b1;
else if(~C2T0_stb_ne) spc2_flush0_active <= 1'b0;
if(spc2_flush_inst1_g & ~spc2_dctl_flush_pipe_w & C2T1_stb_ne) spc2_flush1_active <= 1'b1;
else if(~C2T1_stb_ne) spc2_flush1_active <= 1'b0;
if(spc2_flush_inst2_g & ~spc2_dctl_flush_pipe_w & C2T2_stb_ne) spc2_flush2_active <= 1'b1;
else if(~C2T2_stb_ne) spc2_flush2_active <= 1'b0;
if(spc2_flush_inst3_g & ~spc2_dctl_flush_pipe_w & C2T3_stb_ne) spc2_flush3_active <= 1'b1;
else if(~C2T3_stb_ne) spc2_flush3_active <= 1'b0;
if(spc2_intrpt_disp_asi0_g & spc2_st_inst_vld_g & ~spc2_non_altspace_ldst_g & ~spc2_dctl_flush_pipe_w & C2T0_stb_ne)
spc2_intr0_active <= 1'b1;
else if(~C2T0_stb_ne)
spc2_intr0_active <= 1'b0;
if(spc2_intrpt_disp_asi1_g & spc2_st_inst_vld_g & ~spc2_non_altspace_ldst_g & ~spc2_dctl_flush_pipe_w & C2T1_stb_ne)
spc2_intr1_active <= 1'b1;
else if(~C2T1_stb_ne)
spc2_intr1_active <= 1'b0;
if(spc2_intrpt_disp_asi2_g & spc2_st_inst_vld_g & ~spc2_non_altspace_ldst_g & ~spc2_dctl_flush_pipe_w & C2T2_stb_ne)
spc2_intr2_active <= 1'b1;
else if(~C2T2_stb_ne)
spc2_intr2_active <= 1'b0;
if(spc2_intrpt_disp_asi3_g & spc2_st_inst_vld_g & ~spc2_non_altspace_ldst_g & ~spc2_dctl_flush_pipe_w & C2T3_stb_ne)
spc2_intr3_active <= 1'b1;
else if(~C2T3_stb_ne)
spc2_intr3_active <= 1'b0;
end
if(spc2_mbar0_active & spc2_inst_vld_w & spc2_sas_thrid_w[1:0] == 2'b00)
finish_test("spc", "membar violation thread 0", 2);
if(spc2_mbar1_active & spc2_inst_vld_w & spc2_sas_thrid_w[1:0] == 2'b01)
finish_test("spc", "membar violation thread 1", 2);
if(spc2_mbar2_active & spc2_inst_vld_w & spc2_sas_thrid_w[1:0] == 2'b10)
finish_test("spc", "membar violation thread 2", 2);
if(spc2_mbar3_active & spc2_inst_vld_w & spc2_sas_thrid_w[1:0] == 2'b11)
finish_test("spc", "membar violation thread 3", 2);
if(spc2_flush0_active & spc2_inst_vld_w & spc2_sas_thrid_w[1:0] == 2'b00)
finish_test("spc", "flush violation thread 0", 2);
if(spc2_flush1_active & spc2_inst_vld_w & spc2_sas_thrid_w[1:0] == 2'b01)
finish_test("spc", "flush violation thread 1", 2);
if(spc2_flush2_active & spc2_inst_vld_w & spc2_sas_thrid_w[1:0] == 2'b10)
finish_test("spc", "flush violation thread 2", 2);
if(spc2_flush3_active & spc2_inst_vld_w & spc2_sas_thrid_w[1:0] == 2'b11)
finish_test("spc", "flush violation thread 3", 2);
if(spc2_intr0_active & spc2_inst_vld_w & spc2_sas_thrid_w[1:0] == 2'b00)
finish_test("spc", "intr violation thread 0", 2);
if(spc2_intr1_active & spc2_inst_vld_w & spc2_sas_thrid_w[1:0] == 2'b01)
finish_test("spc", "intr violation thread 1", 2);
if(spc2_intr2_active & spc2_inst_vld_w & spc2_sas_thrid_w[1:0] == 2'b10)
finish_test("spc", "intr violation thread 2", 2);
if(spc2_intr3_active & spc2_inst_vld_w & spc2_sas_thrid_w[1:0] == 2'b11)
finish_test("spc", "intr violation thread 3", 2);
if(~rst_l | ~C2T0_stb_full | sctag_pcx_stall_pq) C2T0_stb_drain_cnt = 0;
else C2T0_stb_drain_cnt = C2T0_stb_drain_cnt + 1;
if(C2T0_stb_drain_cnt > stb_drain_to_max)
finish_test("spc", "stb 0 is not draining", 2);
if(~rst_l | ~C2T1_stb_full | sctag_pcx_stall_pq) C2T1_stb_drain_cnt = 0;
else C2T1_stb_drain_cnt = C2T1_stb_drain_cnt + 1;
if(C2T1_stb_drain_cnt > stb_drain_to_max)
finish_test("spc", "stb 1 is not draining", 2);
if(~rst_l | ~C2T2_stb_full | sctag_pcx_stall_pq) C2T2_stb_drain_cnt = 0;
else C2T2_stb_drain_cnt = C2T2_stb_drain_cnt + 1;
if(C2T2_stb_drain_cnt > stb_drain_to_max)
finish_test("spc", "stb 2 is not draining", 2);
if(~rst_l | ~C2T3_stb_full | sctag_pcx_stall_pq) C2T3_stb_drain_cnt = 0;
else C2T3_stb_drain_cnt = C2T3_stb_drain_cnt + 1;
if(C2T3_stb_drain_cnt > stb_drain_to_max)
finish_test("spc", "stb 3 is not draining", 2);
C2T0_stb_vld_sum_d1 <= C2T0_stb_vld_sum;
C2T1_stb_vld_sum_d1 <= C2T1_stb_vld_sum;
C2T2_stb_vld_sum_d1 <= C2T2_stb_vld_sum;
C2T3_stb_vld_sum_d1 <= C2T3_stb_vld_sum;
C2T0_defr_trp_en_d1 <= C2T0_defr_trp_en;
C2T1_defr_trp_en_d1 <= C2T1_defr_trp_en;
C2T2_defr_trp_en_d1 <= C2T2_defr_trp_en;
C2T3_defr_trp_en_d1 <= C2T3_defr_trp_en;
if(rst_l & C2T0_defr_trp_en_d1 & (C2T0_stb_vld_sum_d1 < C2T0_stb_vld_sum))
finish_test("spc", "tso_mon: deferred trap problems for store T0", 2);
if(rst_l & C2T1_defr_trp_en_d1 & (C2T1_stb_vld_sum_d1 < C2T1_stb_vld_sum))
finish_test("spc", "tso_mon: deferred trap problems for store T1", 2);
if(rst_l & C2T2_defr_trp_en_d1 & (C2T2_stb_vld_sum_d1 < C2T2_stb_vld_sum))
finish_test("spc", "tso_mon: deferred trap problems for store T2", 2);
if(rst_l & C2T3_defr_trp_en_d1 & (C2T3_stb_vld_sum_d1 < C2T3_stb_vld_sum))
finish_test("spc", "tso_mon: deferred trap problems for store T3", 2);
end
`endif // ifdef RTL_SPARC2
`ifdef RTL_SPARC3
wire C3T0_stb_ne = |`TOP_DESIGN.sparc3.lsu.stb_ctl0.stb_state_vld[7:0];
wire C3T1_stb_ne = |`TOP_DESIGN.sparc3.lsu.stb_ctl1.stb_state_vld[7:0];
wire C3T2_stb_ne = |`TOP_DESIGN.sparc3.lsu.stb_ctl2.stb_state_vld[7:0];
wire C3T3_stb_ne = |`TOP_DESIGN.sparc3.lsu.stb_ctl3.stb_state_vld[7:0];
wire C3T0_stb_nced = |( `TOP_DESIGN.sparc3.lsu.stb_ctl0.stb_state_vld[7:0] &
~`TOP_DESIGN.sparc3.lsu.stb_ctl0.stb_state_ced[7:0]);
wire C3T1_stb_nced = |( `TOP_DESIGN.sparc3.lsu.stb_ctl1.stb_state_vld[7:0] &
~`TOP_DESIGN.sparc3.lsu.stb_ctl1.stb_state_ced[7:0]);
wire C3T2_stb_nced = |( `TOP_DESIGN.sparc3.lsu.stb_ctl2.stb_state_vld[7:0] &
~`TOP_DESIGN.sparc3.lsu.stb_ctl2.stb_state_ced[7:0]);
wire C3T3_stb_nced = |( `TOP_DESIGN.sparc3.lsu.stb_ctl3.stb_state_vld[7:0] &
~`TOP_DESIGN.sparc3.lsu.stb_ctl3.stb_state_ced[7:0]);
`else
wire C3T0_stb_ne = 1'b0;
wire C3T1_stb_ne = 1'b0;
wire C3T2_stb_ne = 1'b0;
wire C3T3_stb_ne = 1'b0;
wire C3T0_stb_nced = 1'b0;
wire C3T1_stb_nced = 1'b0;
wire C3T2_stb_nced = 1'b0;
wire C3T3_stb_nced = 1'b0;
`endif // ifdef RTL_SPARC3
`ifdef RTL_SPARC3
wire spc3_lsu_ifill_pkt_vld = `TOP_DESIGN.sparc3.lsu.qctl2.lsu_ifill_pkt_vld;
wire spc3_dfq_rd_advance = `TOP_DESIGN.sparc3.lsu.qctl2.dfq_rd_advance;
wire spc3_dfq_int_type = `TOP_DESIGN.sparc3.lsu.qctl2.dfq_int_type;
wire spc3_ifu_lsu_inv_clear = `TOP_DESIGN.sparc3.lsu.qctl2.ifu_lsu_inv_clear;
wire spc3_dva_svld_e = `TOP_DESIGN.sparc3.lsu.qctl2.dva_svld_e;
wire spc3_dva_rvld_e = `TOP_DESIGN.sparc3.lsu.dva.rd_en;
wire [10:4] spc3_dva_rd_addr_e = `TOP_DESIGN.sparc3.lsu.dva.rd_adr1[6:0];
wire [4:0] spc3_dva_snp_addr_e = `TOP_DESIGN.sparc3.lsu.qctl2.dva_snp_addr_e[4:0];
wire [4:0] spc3_stb_data_rd_ptr = `TOP_DESIGN.sparc3.lsu.stb_data_rd_ptr[4:0];
wire [4:0] spc3_stb_data_wr_ptr = `TOP_DESIGN.sparc3.lsu.stb_data_wr_ptr[4:0];
wire spc3_stb_data_wptr_vld = `TOP_DESIGN.sparc3.lsu.stb_data_wptr_vld;
wire spc3_stb_data_rptr_vld = `TOP_DESIGN.sparc3.lsu.stb_data_rptr_vld;
wire spc3_stbrwctl_flush_pipe_w = `TOP_DESIGN.sparc3.lsu.stb_rwctl.lsu_stbrwctl_flush_pipe_w;
wire spc3_lsu_st_pcx_rq_pick = |`TOP_DESIGN.sparc3.lsu.stb_rwctl.lsu_st_pcx_rq_pick[3:0];
wire [3:0] spc3_lsu_rd_dtag_parity_g = `TOP_DESIGN.sparc3.lsu.dctl.lsu_rd_dtag_parity_g[3:0];
wire [3:0] spc3_dva_vld_g = `TOP_DESIGN.sparc3.lsu.dctl.dva_vld_g[3:0];
wire [3:0] spc3_lsu_dc_tag_pe_g_unmasked = spc3_lsu_rd_dtag_parity_g[3:0] & spc3_dva_vld_g[3:0];
wire spc3_lsu_dc_tag_pe_g_unmasked_or = |spc3_lsu_dc_tag_pe_g_unmasked[3:0];
wire C3T0_stb_full = &`TOP_DESIGN.sparc3.lsu.stb_ctl0.stb_state_vld[7:0];
wire C3T1_stb_full = &`TOP_DESIGN.sparc3.lsu.stb_ctl1.stb_state_vld[7:0];
wire C3T2_stb_full = &`TOP_DESIGN.sparc3.lsu.stb_ctl2.stb_state_vld[7:0];
wire C3T3_stb_full = &`TOP_DESIGN.sparc3.lsu.stb_ctl3.stb_state_vld[7:0];
wire [7:0] C3T0_stb_vld = `TOP_DESIGN.sparc3.lsu.stb_ctl0.stb_state_vld[7:0];
wire [7:0] C3T1_stb_vld = `TOP_DESIGN.sparc3.lsu.stb_ctl1.stb_state_vld[7:0];
wire [7:0] C3T2_stb_vld = `TOP_DESIGN.sparc3.lsu.stb_ctl2.stb_state_vld[7:0];
wire [7:0] C3T3_stb_vld = `TOP_DESIGN.sparc3.lsu.stb_ctl3.stb_state_vld[7:0];
wire [4:0] C3T0_stb_vld_sum = C3T0_stb_vld[0] + C3T0_stb_vld[1] + C3T0_stb_vld[2] + C3T0_stb_vld[3] +
C3T0_stb_vld[4] + C3T0_stb_vld[5] + C3T0_stb_vld[6] + C3T0_stb_vld[7] ;
wire [4:0] C3T1_stb_vld_sum = C3T1_stb_vld[0] + C3T1_stb_vld[1] + C3T1_stb_vld[2] + C3T1_stb_vld[3] +
C3T1_stb_vld[4] + C3T1_stb_vld[5] + C3T1_stb_vld[6] + C3T1_stb_vld[7] ;
wire [4:0] C3T2_stb_vld_sum = C3T2_stb_vld[0] + C3T2_stb_vld[1] + C3T2_stb_vld[2] + C3T2_stb_vld[3] +
C3T2_stb_vld[4] + C3T2_stb_vld[5] + C3T2_stb_vld[6] + C3T2_stb_vld[7] ;
wire [4:0] C3T3_stb_vld_sum = C3T3_stb_vld[0] + C3T3_stb_vld[1] + C3T3_stb_vld[2] + C3T3_stb_vld[3] +
C3T3_stb_vld[4] + C3T3_stb_vld[5] + C3T3_stb_vld[6] + C3T3_stb_vld[7] ;
reg [4:0] C3T0_stb_vld_sum_d1;
reg [4:0] C3T1_stb_vld_sum_d1;
reg [4:0] C3T2_stb_vld_sum_d1;
reg [4:0] C3T3_stb_vld_sum_d1;
wire C3T0_st_ack = &`TOP_DESIGN.sparc3.lsu.cpx_st_ack_tid0;
wire C3T1_st_ack = &`TOP_DESIGN.sparc3.lsu.cpx_st_ack_tid1;
wire C3T2_st_ack = &`TOP_DESIGN.sparc3.lsu.cpx_st_ack_tid2;
wire C3T3_st_ack = &`TOP_DESIGN.sparc3.lsu.cpx_st_ack_tid3;
wire C3T0_defr_trp_en = &`TOP_DESIGN.sparc3.lsu.excpctl.st_defr_trp_en0;
wire C3T1_defr_trp_en = &`TOP_DESIGN.sparc3.lsu.excpctl.st_defr_trp_en1;
wire C3T2_defr_trp_en = &`TOP_DESIGN.sparc3.lsu.excpctl.st_defr_trp_en2;
wire C3T3_defr_trp_en = &`TOP_DESIGN.sparc3.lsu.excpctl.st_defr_trp_en3;
reg C3T0_defr_trp_en_d1;
reg C3T1_defr_trp_en_d1;
reg C3T2_defr_trp_en_d1;
reg C3T3_defr_trp_en_d1;
integer C3T0_stb_drain_cnt;
integer C3T1_stb_drain_cnt;
integer C3T2_stb_drain_cnt;
integer C3T3_stb_drain_cnt;
// Hits in the store buffer
//-------------------------
wire spc3_inst_vld_w = `TOP_DESIGN.sparc3.ifu.fcl.inst_vld_w;
wire [1:0] spc3_sas_thrid_w = `TOP_DESIGN.sparc3.ifu.fcl.sas_thrid_w[1:0];
wire C3_st_ack_w = (spc3_sas_thrid_w == 2'b00) & C3T0_st_ack |
(spc3_sas_thrid_w == 2'b01) & C3T1_st_ack |
(spc3_sas_thrid_w == 2'b10) & C3T2_st_ack |
(spc3_sas_thrid_w == 2'b11) & C3T3_st_ack;
wire [7:0] spc3_stb_ld_full_raw = `TOP_DESIGN.sparc3.lsu.stb_ld_full_raw[7:0];
wire [7:0] spc3_stb_ld_partial_raw = `TOP_DESIGN.sparc3.lsu.stb_ld_partial_raw[7:0];
wire spc3_stb_cam_mhit = `TOP_DESIGN.sparc3.lsu.stb_cam_mhit;
wire spc3_stb_cam_hit = `TOP_DESIGN.sparc3.lsu.stb_cam_hit;
wire [3:0] spc3_lsu_way_hit = `TOP_DESIGN.sparc3.lsu.dctl.lsu_way_hit[3:0];
wire spc3_lsu_ifu_ldst_miss_w = `TOP_DESIGN.sparc3.lsu.lsu_ifu_ldst_miss_w;
wire spc3_ld_inst_vld_g = `TOP_DESIGN.sparc3.lsu.dctl.ld_inst_vld_g;
wire spc3_ldst_dbl_g = `TOP_DESIGN.sparc3.lsu.dctl.ldst_dbl_g;
wire spc3_quad_asi_g = `TOP_DESIGN.sparc3.lsu.dctl.quad_asi_g;
wire [1:0] spc3_ldst_sz_g = `TOP_DESIGN.sparc3.lsu.dctl.ldst_sz_g;
wire spc3_lsu_alt_space_g = `TOP_DESIGN.sparc3.lsu.dctl.lsu_alt_space_g;
wire spc3_mbar_inst0_g = `TOP_DESIGN.sparc3.lsu.dctl.mbar_inst0_g;
wire spc3_mbar_inst1_g = `TOP_DESIGN.sparc3.lsu.dctl.mbar_inst1_g;
wire spc3_mbar_inst2_g = `TOP_DESIGN.sparc3.lsu.dctl.mbar_inst2_g;
wire spc3_mbar_inst3_g = `TOP_DESIGN.sparc3.lsu.dctl.mbar_inst3_g;
wire spc3_flush_inst0_g = `TOP_DESIGN.sparc3.lsu.dctl.flush_inst0_g;
wire spc3_flush_inst1_g = `TOP_DESIGN.sparc3.lsu.dctl.flush_inst1_g;
wire spc3_flush_inst2_g = `TOP_DESIGN.sparc3.lsu.dctl.flush_inst2_g;
wire spc3_flush_inst3_g = `TOP_DESIGN.sparc3.lsu.dctl.flush_inst3_g;
wire spc3_intrpt_disp_asi0_g = `TOP_DESIGN.sparc3.lsu.dctl.intrpt_disp_asi_g & (spc3_sas_thrid_w == 2'b00);
wire spc3_intrpt_disp_asi1_g = `TOP_DESIGN.sparc3.lsu.dctl.intrpt_disp_asi_g & (spc3_sas_thrid_w == 2'b01);
wire spc3_intrpt_disp_asi2_g = `TOP_DESIGN.sparc3.lsu.dctl.intrpt_disp_asi_g & (spc3_sas_thrid_w == 2'b10);
wire spc3_intrpt_disp_asi3_g = `TOP_DESIGN.sparc3.lsu.dctl.intrpt_disp_asi_g & (spc3_sas_thrid_w == 2'b11);
wire spc3_st_inst_vld_g = `TOP_DESIGN.sparc3.lsu.dctl.st_inst_vld_g;
wire spc3_non_altspace_ldst_g = `TOP_DESIGN.sparc3.lsu.dctl.non_altspace_ldst_g;
wire spc3_dctl_flush_pipe_w = `TOP_DESIGN.sparc3.lsu.dctl.dctl_flush_pipe_w;
wire [3:0] spc3_no_spc_rmo_st = `TOP_DESIGN.sparc3.lsu.dctl.no_spc_rmo_st[3:0];
wire spc3_ldst_fp_e = `TOP_DESIGN.sparc3.lsu.ifu_lsu_ldst_fp_e;
wire [2:0] spc3_stb_rdptr = `TOP_DESIGN.sparc3.lsu.stb_rwctl.stb_rdptr_l;
wire spc3_ld_l2cache_req = `TOP_DESIGN.sparc3.lsu.qctl1.ld3_l2cache_rq |
`TOP_DESIGN.sparc3.lsu.qctl1.ld2_l2cache_rq |
`TOP_DESIGN.sparc3.lsu.qctl1.ld1_l2cache_rq |
`TOP_DESIGN.sparc3.lsu.qctl1.ld0_l2cache_rq;
wire [3:0] spc3_dcache_enable = {`TOP_DESIGN.sparc3.lsu.dctl.lsu_ctl_reg0[1],
`TOP_DESIGN.sparc3.lsu.dctl.lsu_ctl_reg1[1],
`TOP_DESIGN.sparc3.lsu.dctl.lsu_ctl_reg2[1],
`TOP_DESIGN.sparc3.lsu.dctl.lsu_ctl_reg3[1]};
wire [3:0] spc3_icache_enable = `TOP_DESIGN.sparc3.lsu.lsu_ifu_icache_en[3:0];
wire spc3_dc_direct_map = `TOP_DESIGN.sparc3.lsu.dc_direct_map;
wire spc3_lsu_ifu_direct_map_l1 = `TOP_DESIGN.sparc3.lsu.lsu_ifu_direct_map_l1;
always @(spc3_dcache_enable)
$display("%0d tso_mon: spc3_dcache_enable changed to %x", $time, spc3_dcache_enable);
always @(spc3_icache_enable)
$display("%0d tso_mon: spc3_icache_enable changed to %x", $time, spc3_icache_enable);
always @(spc3_dc_direct_map)
$display("%0d tso_mon: spc3_dc_direct_map changed to %x", $time, spc3_dc_direct_map);
always @(spc3_lsu_ifu_direct_map_l1)
$display("%0d tso_mon: spc3_lsu_ifu_direct_map_l1 changed to %x", $time, spc3_lsu_ifu_direct_map_l1);
reg spc3_dva_svld_e_d1;
reg spc3_dva_rvld_e_d1;
reg [10:4] spc3_dva_rd_addr_e_d1;
reg [4:0] spc3_dva_snp_addr_e_d1;
reg spc3_lsu_snp_after_rd;
reg spc3_lsu_rd_after_snp;
reg spc3_ldst_fp_m, spc3_ldst_fp_g;
integer spc3_multiple_hits;
reg spc3_skid_d1, spc3_skid_d2, spc3_skid_d3;
initial begin
spc3_skid_d1 = 0;
spc3_skid_d2 = 0;
spc3_skid_d3 = 0;
end
always @(posedge clk)
begin
spc3_skid_d1 <= (~spc3_ifu_lsu_inv_clear & spc3_dfq_rd_advance & spc3_dfq_int_type);
spc3_skid_d2 <= spc3_skid_d1 & ~spc3_ifu_lsu_inv_clear;
spc3_skid_d3 <= spc3_skid_d2 & ~spc3_ifu_lsu_inv_clear;
// The full tracking of this condition is complicated since after the interrupt is advanced
// there may be more invalidations to the IFQ.
// All we care about is that the invalidations BEFORE the interrupt are finished.
// I provided a command line argument to disable this check.
if(spc3_skid_d3 & enable_ifu_lsu_inv_clear)
finish_test("spc", "tso_mon: spc3_ifu_lsu_inv_clear should have been clear by now", 3);
spc3_dva_svld_e_d1 <= spc3_dva_svld_e;
spc3_dva_rvld_e_d1 <= spc3_dva_rvld_e;
spc3_dva_rd_addr_e_d1 <= spc3_dva_rd_addr_e;
spc3_dva_snp_addr_e_d1 <= spc3_dva_snp_addr_e;
if(spc3_dva_svld_e_d1 & spc3_dva_rvld_e & (spc3_dva_rd_addr_e_d1[10:6] == spc3_dva_snp_addr_e[4:0]))
spc3_lsu_rd_after_snp <= 1'b1;
else
spc3_lsu_rd_after_snp <= 1'b0;
if(spc3_dva_svld_e & spc3_dva_rvld_e_d1 & (spc3_dva_rd_addr_e[10:6] == spc3_dva_snp_addr_e_d1[4:0]))
spc3_lsu_snp_after_rd <= 1'b1;
else
spc3_lsu_snp_after_rd <= 1'b0;
spc3_ldst_fp_m <= spc3_ldst_fp_e;
spc3_ldst_fp_g <= spc3_ldst_fp_m;
if(spc3_stb_data_rptr_vld & spc3_stb_data_wptr_vld & ~spc3_stbrwctl_flush_pipe_w &
(spc3_stb_data_rd_ptr == spc3_stb_data_wr_ptr) & spc3_lsu_st_pcx_rq_pick)
begin
finish_test("spc", "tso_mon: LSU stb data write and read in the same cycle", 3);
end
spc3_multiple_hits = (spc3_lsu_way_hit[3] + spc3_lsu_way_hit[2] + spc3_lsu_way_hit[1] + spc3_lsu_way_hit[0]);
if(!spc3_lsu_ifu_ldst_miss_w && (spc3_multiple_hits >1) && spc3_inst_vld_w && !spc3_dctl_flush_pipe_w && !spc3_lsu_dc_tag_pe_g_unmasked_or)
finish_test("spc", "tso_mon: LSU multiple hits ", 3);
end
wire spc3_ld_dbl = spc3_ld_inst_vld_g & spc3_ldst_dbl_g & ~spc3_quad_asi_g;
wire spc3_ld_quad = spc3_ld_inst_vld_g & spc3_ldst_dbl_g & spc3_quad_asi_g;
wire spc3_ld_other = spc3_ld_inst_vld_g & ~spc3_ldst_dbl_g;
wire spc3_ld_dbl_fp = spc3_ld_dbl & spc3_ldst_fp_g;
wire spc3_ld_other_fp = spc3_ld_other & spc3_ldst_fp_g;
wire spc3_ld_dbl_int = spc3_ld_dbl & ~spc3_ldst_fp_g;
wire spc3_ld_quad_int = spc3_ld_quad & ~spc3_ldst_fp_g;
wire spc3_ld_other_int= spc3_ld_other & ~spc3_ldst_fp_g;
wire spc3_ld_bypassok_hit = |spc3_stb_ld_full_raw[7:0] & ~spc3_stb_cam_mhit;
wire spc3_ld_partial_hit = |spc3_stb_ld_partial_raw[7:0] & ~spc3_stb_cam_mhit;
wire spc3_ld_multiple_hit = spc3_stb_cam_mhit;
wire spc3_any_lsu_way_hit = |spc3_lsu_way_hit;
wire [7:0] spc3_stb_rdptr_decoded = (spc3_stb_rdptr ==3'b000) ? 8'b00000001 :
(spc3_stb_rdptr ==3'b001) ? 8'b00000010 :
(spc3_stb_rdptr ==3'b010) ? 8'b00000100 :
(spc3_stb_rdptr ==3'b011) ? 8'b00001000 :
(spc3_stb_rdptr ==3'b100) ? 8'b00010000 :
(spc3_stb_rdptr ==3'b101) ? 8'b00100000 :
(spc3_stb_rdptr ==3'b110) ? 8'b01000000 :
(spc3_stb_rdptr ==3'b111) ? 8'b10000000 : 8'h00;
wire spc3_stb_top_hit = |(spc3_stb_rdptr_decoded & (spc3_stb_ld_full_raw | spc3_stb_ld_partial_raw));
//---------------------------------------------------------------------
// ld_type[4:0] hit_type[2:0], cache_hit, hit_top
// this is passed to the coverage monitor.
//---------------------------------------------------------------------
wire [10:0] spc3_stb_ld_hit_info =
{spc3_ld_dbl_fp, spc3_ld_other_fp,
spc3_ld_dbl_int, spc3_ld_quad_int, spc3_ld_other_int,
spc3_ld_bypassok_hit, spc3_ld_partial_hit, spc3_ld_multiple_hit,
spc3_any_lsu_way_hit,
spc3_stb_top_hit, C3_st_ack_w};
reg spc3_mbar0_active;
reg spc3_mbar1_active;
reg spc3_mbar2_active;
reg spc3_mbar3_active;
reg spc3_flush0_active;
reg spc3_flush1_active;
reg spc3_flush2_active;
reg spc3_flush3_active;
reg spc3_intr0_active;
reg spc3_intr1_active;
reg spc3_intr2_active;
reg spc3_intr3_active;
always @(negedge clk)
begin
if(~rst_l)
begin
spc3_mbar0_active <= 1'b0;
spc3_mbar1_active <= 1'b0;
spc3_mbar2_active <= 1'b0;
spc3_mbar3_active <= 1'b0;
spc3_flush0_active <= 1'b0;
spc3_flush1_active <= 1'b0;
spc3_flush2_active <= 1'b0;
spc3_flush3_active <= 1'b0;
spc3_intr0_active <= 1'b0;
spc3_intr1_active <= 1'b0;
spc3_intr2_active <= 1'b0;
spc3_intr3_active <= 1'b0;
end
else
begin
if(spc3_mbar_inst0_g & ~spc3_dctl_flush_pipe_w & (C3T0_stb_ne|~spc3_no_spc_rmo_st[0]))
spc3_mbar0_active <= 1'b1;
else if(~C3T0_stb_ne & spc3_no_spc_rmo_st[0])
spc3_mbar0_active <= 1'b0;
if(spc3_mbar_inst1_g & ~ spc3_dctl_flush_pipe_w & (C3T1_stb_ne|~spc3_no_spc_rmo_st[1]))
spc3_mbar1_active <= 1'b1;
else if(~C3T1_stb_ne & spc3_no_spc_rmo_st[1])
spc3_mbar1_active <= 1'b0;
if(spc3_mbar_inst2_g & ~ spc3_dctl_flush_pipe_w & (C3T2_stb_ne|~spc3_no_spc_rmo_st[2]))
spc3_mbar2_active <= 1'b1;
else if(~C3T2_stb_ne & spc3_no_spc_rmo_st[2])
spc3_mbar2_active <= 1'b0;
if(spc3_mbar_inst3_g & ~ spc3_dctl_flush_pipe_w & (C3T3_stb_ne|~spc3_no_spc_rmo_st[3]))
spc3_mbar3_active <= 1'b1;
else if(~C3T3_stb_ne & spc3_no_spc_rmo_st[3])
spc3_mbar3_active <= 1'b0;
if(spc3_flush_inst0_g & ~spc3_dctl_flush_pipe_w & C3T0_stb_ne) spc3_flush0_active <= 1'b1;
else if(~C3T0_stb_ne) spc3_flush0_active <= 1'b0;
if(spc3_flush_inst1_g & ~spc3_dctl_flush_pipe_w & C3T1_stb_ne) spc3_flush1_active <= 1'b1;
else if(~C3T1_stb_ne) spc3_flush1_active <= 1'b0;
if(spc3_flush_inst2_g & ~spc3_dctl_flush_pipe_w & C3T2_stb_ne) spc3_flush2_active <= 1'b1;
else if(~C3T2_stb_ne) spc3_flush2_active <= 1'b0;
if(spc3_flush_inst3_g & ~spc3_dctl_flush_pipe_w & C3T3_stb_ne) spc3_flush3_active <= 1'b1;
else if(~C3T3_stb_ne) spc3_flush3_active <= 1'b0;
if(spc3_intrpt_disp_asi0_g & spc3_st_inst_vld_g & ~spc3_non_altspace_ldst_g & ~spc3_dctl_flush_pipe_w & C3T0_stb_ne)
spc3_intr0_active <= 1'b1;
else if(~C3T0_stb_ne)
spc3_intr0_active <= 1'b0;
if(spc3_intrpt_disp_asi1_g & spc3_st_inst_vld_g & ~spc3_non_altspace_ldst_g & ~spc3_dctl_flush_pipe_w & C3T1_stb_ne)
spc3_intr1_active <= 1'b1;
else if(~C3T1_stb_ne)
spc3_intr1_active <= 1'b0;
if(spc3_intrpt_disp_asi2_g & spc3_st_inst_vld_g & ~spc3_non_altspace_ldst_g & ~spc3_dctl_flush_pipe_w & C3T2_stb_ne)
spc3_intr2_active <= 1'b1;
else if(~C3T2_stb_ne)
spc3_intr2_active <= 1'b0;
if(spc3_intrpt_disp_asi3_g & spc3_st_inst_vld_g & ~spc3_non_altspace_ldst_g & ~spc3_dctl_flush_pipe_w & C3T3_stb_ne)
spc3_intr3_active <= 1'b1;
else if(~C3T3_stb_ne)
spc3_intr3_active <= 1'b0;
end
if(spc3_mbar0_active & spc3_inst_vld_w & spc3_sas_thrid_w[1:0] == 2'b00)
finish_test("spc", "membar violation thread 0", 3);
if(spc3_mbar1_active & spc3_inst_vld_w & spc3_sas_thrid_w[1:0] == 2'b01)
finish_test("spc", "membar violation thread 1", 3);
if(spc3_mbar2_active & spc3_inst_vld_w & spc3_sas_thrid_w[1:0] == 2'b10)
finish_test("spc", "membar violation thread 2", 3);
if(spc3_mbar3_active & spc3_inst_vld_w & spc3_sas_thrid_w[1:0] == 2'b11)
finish_test("spc", "membar violation thread 3", 3);
if(spc3_flush0_active & spc3_inst_vld_w & spc3_sas_thrid_w[1:0] == 2'b00)
finish_test("spc", "flush violation thread 0", 3);
if(spc3_flush1_active & spc3_inst_vld_w & spc3_sas_thrid_w[1:0] == 2'b01)
finish_test("spc", "flush violation thread 1", 3);
if(spc3_flush2_active & spc3_inst_vld_w & spc3_sas_thrid_w[1:0] == 2'b10)
finish_test("spc", "flush violation thread 2", 3);
if(spc3_flush3_active & spc3_inst_vld_w & spc3_sas_thrid_w[1:0] == 2'b11)
finish_test("spc", "flush violation thread 3", 3);
if(spc3_intr0_active & spc3_inst_vld_w & spc3_sas_thrid_w[1:0] == 2'b00)
finish_test("spc", "intr violation thread 0", 3);
if(spc3_intr1_active & spc3_inst_vld_w & spc3_sas_thrid_w[1:0] == 2'b01)
finish_test("spc", "intr violation thread 1", 3);
if(spc3_intr2_active & spc3_inst_vld_w & spc3_sas_thrid_w[1:0] == 2'b10)
finish_test("spc", "intr violation thread 2", 3);
if(spc3_intr3_active & spc3_inst_vld_w & spc3_sas_thrid_w[1:0] == 2'b11)
finish_test("spc", "intr violation thread 3", 3);
if(~rst_l | ~C3T0_stb_full | sctag_pcx_stall_pq) C3T0_stb_drain_cnt = 0;
else C3T0_stb_drain_cnt = C3T0_stb_drain_cnt + 1;
if(C3T0_stb_drain_cnt > stb_drain_to_max)
finish_test("spc", "stb 0 is not draining", 3);
if(~rst_l | ~C3T1_stb_full | sctag_pcx_stall_pq) C3T1_stb_drain_cnt = 0;
else C3T1_stb_drain_cnt = C3T1_stb_drain_cnt + 1;
if(C3T1_stb_drain_cnt > stb_drain_to_max)
finish_test("spc", "stb 1 is not draining", 3);
if(~rst_l | ~C3T2_stb_full | sctag_pcx_stall_pq) C3T2_stb_drain_cnt = 0;
else C3T2_stb_drain_cnt = C3T2_stb_drain_cnt + 1;
if(C3T2_stb_drain_cnt > stb_drain_to_max)
finish_test("spc", "stb 2 is not draining", 3);
if(~rst_l | ~C3T3_stb_full | sctag_pcx_stall_pq) C3T3_stb_drain_cnt = 0;
else C3T3_stb_drain_cnt = C3T3_stb_drain_cnt + 1;
if(C3T3_stb_drain_cnt > stb_drain_to_max)
finish_test("spc", "stb 3 is not draining", 3);
C3T0_stb_vld_sum_d1 <= C3T0_stb_vld_sum;
C3T1_stb_vld_sum_d1 <= C3T1_stb_vld_sum;
C3T2_stb_vld_sum_d1 <= C3T2_stb_vld_sum;
C3T3_stb_vld_sum_d1 <= C3T3_stb_vld_sum;
C3T0_defr_trp_en_d1 <= C3T0_defr_trp_en;
C3T1_defr_trp_en_d1 <= C3T1_defr_trp_en;
C3T2_defr_trp_en_d1 <= C3T2_defr_trp_en;
C3T3_defr_trp_en_d1 <= C3T3_defr_trp_en;
if(rst_l & C3T0_defr_trp_en_d1 & (C3T0_stb_vld_sum_d1 < C3T0_stb_vld_sum))
finish_test("spc", "tso_mon: deferred trap problems for store T0", 3);
if(rst_l & C3T1_defr_trp_en_d1 & (C3T1_stb_vld_sum_d1 < C3T1_stb_vld_sum))
finish_test("spc", "tso_mon: deferred trap problems for store T1", 3);
if(rst_l & C3T2_defr_trp_en_d1 & (C3T2_stb_vld_sum_d1 < C3T2_stb_vld_sum))
finish_test("spc", "tso_mon: deferred trap problems for store T2", 3);
if(rst_l & C3T3_defr_trp_en_d1 & (C3T3_stb_vld_sum_d1 < C3T3_stb_vld_sum))
finish_test("spc", "tso_mon: deferred trap problems for store T3", 3);
end
`endif // ifdef RTL_SPARC3
`ifdef RTL_SPARC4
wire C4T0_stb_ne = |`TOP_DESIGN.sparc4.lsu.stb_ctl0.stb_state_vld[7:0];
wire C4T1_stb_ne = |`TOP_DESIGN.sparc4.lsu.stb_ctl1.stb_state_vld[7:0];
wire C4T2_stb_ne = |`TOP_DESIGN.sparc4.lsu.stb_ctl2.stb_state_vld[7:0];
wire C4T3_stb_ne = |`TOP_DESIGN.sparc4.lsu.stb_ctl3.stb_state_vld[7:0];
wire C4T0_stb_nced = |( `TOP_DESIGN.sparc4.lsu.stb_ctl0.stb_state_vld[7:0] &
~`TOP_DESIGN.sparc4.lsu.stb_ctl0.stb_state_ced[7:0]);
wire C4T1_stb_nced = |( `TOP_DESIGN.sparc4.lsu.stb_ctl1.stb_state_vld[7:0] &
~`TOP_DESIGN.sparc4.lsu.stb_ctl1.stb_state_ced[7:0]);
wire C4T2_stb_nced = |( `TOP_DESIGN.sparc4.lsu.stb_ctl2.stb_state_vld[7:0] &
~`TOP_DESIGN.sparc4.lsu.stb_ctl2.stb_state_ced[7:0]);
wire C4T3_stb_nced = |( `TOP_DESIGN.sparc4.lsu.stb_ctl3.stb_state_vld[7:0] &
~`TOP_DESIGN.sparc4.lsu.stb_ctl3.stb_state_ced[7:0]);
`else
wire C4T0_stb_ne = 1'b0;
wire C4T1_stb_ne = 1'b0;
wire C4T2_stb_ne = 1'b0;
wire C4T3_stb_ne = 1'b0;
wire C4T0_stb_nced = 1'b0;
wire C4T1_stb_nced = 1'b0;
wire C4T2_stb_nced = 1'b0;
wire C4T3_stb_nced = 1'b0;
`endif // ifdef RTL_SPARC4
`ifdef RTL_SPARC4
wire spc4_lsu_ifill_pkt_vld = `TOP_DESIGN.sparc4.lsu.qctl2.lsu_ifill_pkt_vld;
wire spc4_dfq_rd_advance = `TOP_DESIGN.sparc4.lsu.qctl2.dfq_rd_advance;
wire spc4_dfq_int_type = `TOP_DESIGN.sparc4.lsu.qctl2.dfq_int_type;
wire spc4_ifu_lsu_inv_clear = `TOP_DESIGN.sparc4.lsu.qctl2.ifu_lsu_inv_clear;
wire spc4_dva_svld_e = `TOP_DESIGN.sparc4.lsu.qctl2.dva_svld_e;
wire spc4_dva_rvld_e = `TOP_DESIGN.sparc4.lsu.dva.rd_en;
wire [10:4] spc4_dva_rd_addr_e = `TOP_DESIGN.sparc4.lsu.dva.rd_adr1[6:0];
wire [4:0] spc4_dva_snp_addr_e = `TOP_DESIGN.sparc4.lsu.qctl2.dva_snp_addr_e[4:0];
wire [4:0] spc4_stb_data_rd_ptr = `TOP_DESIGN.sparc4.lsu.stb_data_rd_ptr[4:0];
wire [4:0] spc4_stb_data_wr_ptr = `TOP_DESIGN.sparc4.lsu.stb_data_wr_ptr[4:0];
wire spc4_stb_data_wptr_vld = `TOP_DESIGN.sparc4.lsu.stb_data_wptr_vld;
wire spc4_stb_data_rptr_vld = `TOP_DESIGN.sparc4.lsu.stb_data_rptr_vld;
wire spc4_stbrwctl_flush_pipe_w = `TOP_DESIGN.sparc4.lsu.stb_rwctl.lsu_stbrwctl_flush_pipe_w;
wire spc4_lsu_st_pcx_rq_pick = |`TOP_DESIGN.sparc4.lsu.stb_rwctl.lsu_st_pcx_rq_pick[3:0];
wire [3:0] spc4_lsu_rd_dtag_parity_g = `TOP_DESIGN.sparc4.lsu.dctl.lsu_rd_dtag_parity_g[3:0];
wire [3:0] spc4_dva_vld_g = `TOP_DESIGN.sparc4.lsu.dctl.dva_vld_g[3:0];
wire [3:0] spc4_lsu_dc_tag_pe_g_unmasked = spc4_lsu_rd_dtag_parity_g[3:0] & spc4_dva_vld_g[3:0];
wire spc4_lsu_dc_tag_pe_g_unmasked_or = |spc4_lsu_dc_tag_pe_g_unmasked[3:0];
wire C4T0_stb_full = &`TOP_DESIGN.sparc4.lsu.stb_ctl0.stb_state_vld[7:0];
wire C4T1_stb_full = &`TOP_DESIGN.sparc4.lsu.stb_ctl1.stb_state_vld[7:0];
wire C4T2_stb_full = &`TOP_DESIGN.sparc4.lsu.stb_ctl2.stb_state_vld[7:0];
wire C4T3_stb_full = &`TOP_DESIGN.sparc4.lsu.stb_ctl3.stb_state_vld[7:0];
wire [7:0] C4T0_stb_vld = `TOP_DESIGN.sparc4.lsu.stb_ctl0.stb_state_vld[7:0];
wire [7:0] C4T1_stb_vld = `TOP_DESIGN.sparc4.lsu.stb_ctl1.stb_state_vld[7:0];
wire [7:0] C4T2_stb_vld = `TOP_DESIGN.sparc4.lsu.stb_ctl2.stb_state_vld[7:0];
wire [7:0] C4T3_stb_vld = `TOP_DESIGN.sparc4.lsu.stb_ctl3.stb_state_vld[7:0];
wire [4:0] C4T0_stb_vld_sum = C4T0_stb_vld[0] + C4T0_stb_vld[1] + C4T0_stb_vld[2] + C4T0_stb_vld[3] +
C4T0_stb_vld[4] + C4T0_stb_vld[5] + C4T0_stb_vld[6] + C4T0_stb_vld[7] ;
wire [4:0] C4T1_stb_vld_sum = C4T1_stb_vld[0] + C4T1_stb_vld[1] + C4T1_stb_vld[2] + C4T1_stb_vld[3] +
C4T1_stb_vld[4] + C4T1_stb_vld[5] + C4T1_stb_vld[6] + C4T1_stb_vld[7] ;
wire [4:0] C4T2_stb_vld_sum = C4T2_stb_vld[0] + C4T2_stb_vld[1] + C4T2_stb_vld[2] + C4T2_stb_vld[3] +
C4T2_stb_vld[4] + C4T2_stb_vld[5] + C4T2_stb_vld[6] + C4T2_stb_vld[7] ;
wire [4:0] C4T3_stb_vld_sum = C4T3_stb_vld[0] + C4T3_stb_vld[1] + C4T3_stb_vld[2] + C4T3_stb_vld[3] +
C4T3_stb_vld[4] + C4T3_stb_vld[5] + C4T3_stb_vld[6] + C4T3_stb_vld[7] ;
reg [4:0] C4T0_stb_vld_sum_d1;
reg [4:0] C4T1_stb_vld_sum_d1;
reg [4:0] C4T2_stb_vld_sum_d1;
reg [4:0] C4T3_stb_vld_sum_d1;
wire C4T0_st_ack = &`TOP_DESIGN.sparc4.lsu.cpx_st_ack_tid0;
wire C4T1_st_ack = &`TOP_DESIGN.sparc4.lsu.cpx_st_ack_tid1;
wire C4T2_st_ack = &`TOP_DESIGN.sparc4.lsu.cpx_st_ack_tid2;
wire C4T3_st_ack = &`TOP_DESIGN.sparc4.lsu.cpx_st_ack_tid3;
wire C4T0_defr_trp_en = &`TOP_DESIGN.sparc4.lsu.excpctl.st_defr_trp_en0;
wire C4T1_defr_trp_en = &`TOP_DESIGN.sparc4.lsu.excpctl.st_defr_trp_en1;
wire C4T2_defr_trp_en = &`TOP_DESIGN.sparc4.lsu.excpctl.st_defr_trp_en2;
wire C4T3_defr_trp_en = &`TOP_DESIGN.sparc4.lsu.excpctl.st_defr_trp_en3;
reg C4T0_defr_trp_en_d1;
reg C4T1_defr_trp_en_d1;
reg C4T2_defr_trp_en_d1;
reg C4T3_defr_trp_en_d1;
integer C4T0_stb_drain_cnt;
integer C4T1_stb_drain_cnt;
integer C4T2_stb_drain_cnt;
integer C4T3_stb_drain_cnt;
// Hits in the store buffer
//-------------------------
wire spc4_inst_vld_w = `TOP_DESIGN.sparc4.ifu.fcl.inst_vld_w;
wire [1:0] spc4_sas_thrid_w = `TOP_DESIGN.sparc4.ifu.fcl.sas_thrid_w[1:0];
wire C4_st_ack_w = (spc4_sas_thrid_w == 2'b00) & C4T0_st_ack |
(spc4_sas_thrid_w == 2'b01) & C4T1_st_ack |
(spc4_sas_thrid_w == 2'b10) & C4T2_st_ack |
(spc4_sas_thrid_w == 2'b11) & C4T3_st_ack;
wire [7:0] spc4_stb_ld_full_raw = `TOP_DESIGN.sparc4.lsu.stb_ld_full_raw[7:0];
wire [7:0] spc4_stb_ld_partial_raw = `TOP_DESIGN.sparc4.lsu.stb_ld_partial_raw[7:0];
wire spc4_stb_cam_mhit = `TOP_DESIGN.sparc4.lsu.stb_cam_mhit;
wire spc4_stb_cam_hit = `TOP_DESIGN.sparc4.lsu.stb_cam_hit;
wire [3:0] spc4_lsu_way_hit = `TOP_DESIGN.sparc4.lsu.dctl.lsu_way_hit[3:0];
wire spc4_lsu_ifu_ldst_miss_w = `TOP_DESIGN.sparc4.lsu.lsu_ifu_ldst_miss_w;
wire spc4_ld_inst_vld_g = `TOP_DESIGN.sparc4.lsu.dctl.ld_inst_vld_g;
wire spc4_ldst_dbl_g = `TOP_DESIGN.sparc4.lsu.dctl.ldst_dbl_g;
wire spc4_quad_asi_g = `TOP_DESIGN.sparc4.lsu.dctl.quad_asi_g;
wire [1:0] spc4_ldst_sz_g = `TOP_DESIGN.sparc4.lsu.dctl.ldst_sz_g;
wire spc4_lsu_alt_space_g = `TOP_DESIGN.sparc4.lsu.dctl.lsu_alt_space_g;
wire spc4_mbar_inst0_g = `TOP_DESIGN.sparc4.lsu.dctl.mbar_inst0_g;
wire spc4_mbar_inst1_g = `TOP_DESIGN.sparc4.lsu.dctl.mbar_inst1_g;
wire spc4_mbar_inst2_g = `TOP_DESIGN.sparc4.lsu.dctl.mbar_inst2_g;
wire spc4_mbar_inst3_g = `TOP_DESIGN.sparc4.lsu.dctl.mbar_inst3_g;
wire spc4_flush_inst0_g = `TOP_DESIGN.sparc4.lsu.dctl.flush_inst0_g;
wire spc4_flush_inst1_g = `TOP_DESIGN.sparc4.lsu.dctl.flush_inst1_g;
wire spc4_flush_inst2_g = `TOP_DESIGN.sparc4.lsu.dctl.flush_inst2_g;
wire spc4_flush_inst3_g = `TOP_DESIGN.sparc4.lsu.dctl.flush_inst3_g;
wire spc4_intrpt_disp_asi0_g = `TOP_DESIGN.sparc4.lsu.dctl.intrpt_disp_asi_g & (spc4_sas_thrid_w == 2'b00);
wire spc4_intrpt_disp_asi1_g = `TOP_DESIGN.sparc4.lsu.dctl.intrpt_disp_asi_g & (spc4_sas_thrid_w == 2'b01);
wire spc4_intrpt_disp_asi2_g = `TOP_DESIGN.sparc4.lsu.dctl.intrpt_disp_asi_g & (spc4_sas_thrid_w == 2'b10);
wire spc4_intrpt_disp_asi3_g = `TOP_DESIGN.sparc4.lsu.dctl.intrpt_disp_asi_g & (spc4_sas_thrid_w == 2'b11);
wire spc4_st_inst_vld_g = `TOP_DESIGN.sparc4.lsu.dctl.st_inst_vld_g;
wire spc4_non_altspace_ldst_g = `TOP_DESIGN.sparc4.lsu.dctl.non_altspace_ldst_g;
wire spc4_dctl_flush_pipe_w = `TOP_DESIGN.sparc4.lsu.dctl.dctl_flush_pipe_w;
wire [3:0] spc4_no_spc_rmo_st = `TOP_DESIGN.sparc4.lsu.dctl.no_spc_rmo_st[3:0];
wire spc4_ldst_fp_e = `TOP_DESIGN.sparc4.lsu.ifu_lsu_ldst_fp_e;
wire [2:0] spc4_stb_rdptr = `TOP_DESIGN.sparc4.lsu.stb_rwctl.stb_rdptr_l;
wire spc4_ld_l2cache_req = `TOP_DESIGN.sparc4.lsu.qctl1.ld3_l2cache_rq |
`TOP_DESIGN.sparc4.lsu.qctl1.ld2_l2cache_rq |
`TOP_DESIGN.sparc4.lsu.qctl1.ld1_l2cache_rq |
`TOP_DESIGN.sparc4.lsu.qctl1.ld0_l2cache_rq;
wire [3:0] spc4_dcache_enable = {`TOP_DESIGN.sparc4.lsu.dctl.lsu_ctl_reg0[1],
`TOP_DESIGN.sparc4.lsu.dctl.lsu_ctl_reg1[1],
`TOP_DESIGN.sparc4.lsu.dctl.lsu_ctl_reg2[1],
`TOP_DESIGN.sparc4.lsu.dctl.lsu_ctl_reg3[1]};
wire [3:0] spc4_icache_enable = `TOP_DESIGN.sparc4.lsu.lsu_ifu_icache_en[3:0];
wire spc4_dc_direct_map = `TOP_DESIGN.sparc4.lsu.dc_direct_map;
wire spc4_lsu_ifu_direct_map_l1 = `TOP_DESIGN.sparc4.lsu.lsu_ifu_direct_map_l1;
always @(spc4_dcache_enable)
$display("%0d tso_mon: spc4_dcache_enable changed to %x", $time, spc4_dcache_enable);
always @(spc4_icache_enable)
$display("%0d tso_mon: spc4_icache_enable changed to %x", $time, spc4_icache_enable);
always @(spc4_dc_direct_map)
$display("%0d tso_mon: spc4_dc_direct_map changed to %x", $time, spc4_dc_direct_map);
always @(spc4_lsu_ifu_direct_map_l1)
$display("%0d tso_mon: spc4_lsu_ifu_direct_map_l1 changed to %x", $time, spc4_lsu_ifu_direct_map_l1);
reg spc4_dva_svld_e_d1;
reg spc4_dva_rvld_e_d1;
reg [10:4] spc4_dva_rd_addr_e_d1;
reg [4:0] spc4_dva_snp_addr_e_d1;
reg spc4_lsu_snp_after_rd;
reg spc4_lsu_rd_after_snp;
reg spc4_ldst_fp_m, spc4_ldst_fp_g;
integer spc4_multiple_hits;
reg spc4_skid_d1, spc4_skid_d2, spc4_skid_d3;
initial begin
spc4_skid_d1 = 0;
spc4_skid_d2 = 0;
spc4_skid_d3 = 0;
end
always @(posedge clk)
begin
spc4_skid_d1 <= (~spc4_ifu_lsu_inv_clear & spc4_dfq_rd_advance & spc4_dfq_int_type);
spc4_skid_d2 <= spc4_skid_d1 & ~spc4_ifu_lsu_inv_clear;
spc4_skid_d3 <= spc4_skid_d2 & ~spc4_ifu_lsu_inv_clear;
// The full tracking of this condition is complicated since after the interrupt is advanced
// there may be more invalidations to the IFQ.
// All we care about is that the invalidations BEFORE the interrupt are finished.
// I provided a command line argument to disable this check.
if(spc4_skid_d3 & enable_ifu_lsu_inv_clear)
finish_test("spc", "tso_mon: spc4_ifu_lsu_inv_clear should have been clear by now", 4);
spc4_dva_svld_e_d1 <= spc4_dva_svld_e;
spc4_dva_rvld_e_d1 <= spc4_dva_rvld_e;
spc4_dva_rd_addr_e_d1 <= spc4_dva_rd_addr_e;
spc4_dva_snp_addr_e_d1 <= spc4_dva_snp_addr_e;
if(spc4_dva_svld_e_d1 & spc4_dva_rvld_e & (spc4_dva_rd_addr_e_d1[10:6] == spc4_dva_snp_addr_e[4:0]))
spc4_lsu_rd_after_snp <= 1'b1;
else
spc4_lsu_rd_after_snp <= 1'b0;
if(spc4_dva_svld_e & spc4_dva_rvld_e_d1 & (spc4_dva_rd_addr_e[10:6] == spc4_dva_snp_addr_e_d1[4:0]))
spc4_lsu_snp_after_rd <= 1'b1;
else
spc4_lsu_snp_after_rd <= 1'b0;
spc4_ldst_fp_m <= spc4_ldst_fp_e;
spc4_ldst_fp_g <= spc4_ldst_fp_m;
if(spc4_stb_data_rptr_vld & spc4_stb_data_wptr_vld & ~spc4_stbrwctl_flush_pipe_w &
(spc4_stb_data_rd_ptr == spc4_stb_data_wr_ptr) & spc4_lsu_st_pcx_rq_pick)
begin
finish_test("spc", "tso_mon: LSU stb data write and read in the same cycle", 4);
end
spc4_multiple_hits = (spc4_lsu_way_hit[3] + spc4_lsu_way_hit[2] + spc4_lsu_way_hit[1] + spc4_lsu_way_hit[0]);
if(!spc4_lsu_ifu_ldst_miss_w && (spc4_multiple_hits >1) && spc4_inst_vld_w && !spc4_dctl_flush_pipe_w && !spc4_lsu_dc_tag_pe_g_unmasked_or)
finish_test("spc", "tso_mon: LSU multiple hits ", 4);
end
wire spc4_ld_dbl = spc4_ld_inst_vld_g & spc4_ldst_dbl_g & ~spc4_quad_asi_g;
wire spc4_ld_quad = spc4_ld_inst_vld_g & spc4_ldst_dbl_g & spc4_quad_asi_g;
wire spc4_ld_other = spc4_ld_inst_vld_g & ~spc4_ldst_dbl_g;
wire spc4_ld_dbl_fp = spc4_ld_dbl & spc4_ldst_fp_g;
wire spc4_ld_other_fp = spc4_ld_other & spc4_ldst_fp_g;
wire spc4_ld_dbl_int = spc4_ld_dbl & ~spc4_ldst_fp_g;
wire spc4_ld_quad_int = spc4_ld_quad & ~spc4_ldst_fp_g;
wire spc4_ld_other_int= spc4_ld_other & ~spc4_ldst_fp_g;
wire spc4_ld_bypassok_hit = |spc4_stb_ld_full_raw[7:0] & ~spc4_stb_cam_mhit;
wire spc4_ld_partial_hit = |spc4_stb_ld_partial_raw[7:0] & ~spc4_stb_cam_mhit;
wire spc4_ld_multiple_hit = spc4_stb_cam_mhit;
wire spc4_any_lsu_way_hit = |spc4_lsu_way_hit;
wire [7:0] spc4_stb_rdptr_decoded = (spc4_stb_rdptr ==3'b000) ? 8'b00000001 :
(spc4_stb_rdptr ==3'b001) ? 8'b00000010 :
(spc4_stb_rdptr ==3'b010) ? 8'b00000100 :
(spc4_stb_rdptr ==3'b011) ? 8'b00001000 :
(spc4_stb_rdptr ==3'b100) ? 8'b00010000 :
(spc4_stb_rdptr ==3'b101) ? 8'b00100000 :
(spc4_stb_rdptr ==3'b110) ? 8'b01000000 :
(spc4_stb_rdptr ==3'b111) ? 8'b10000000 : 8'h00;
wire spc4_stb_top_hit = |(spc4_stb_rdptr_decoded & (spc4_stb_ld_full_raw | spc4_stb_ld_partial_raw));
//---------------------------------------------------------------------
// ld_type[4:0] hit_type[2:0], cache_hit, hit_top
// this is passed to the coverage monitor.
//---------------------------------------------------------------------
wire [10:0] spc4_stb_ld_hit_info =
{spc4_ld_dbl_fp, spc4_ld_other_fp,
spc4_ld_dbl_int, spc4_ld_quad_int, spc4_ld_other_int,
spc4_ld_bypassok_hit, spc4_ld_partial_hit, spc4_ld_multiple_hit,
spc4_any_lsu_way_hit,
spc4_stb_top_hit, C4_st_ack_w};
reg spc4_mbar0_active;
reg spc4_mbar1_active;
reg spc4_mbar2_active;
reg spc4_mbar3_active;
reg spc4_flush0_active;
reg spc4_flush1_active;
reg spc4_flush2_active;
reg spc4_flush3_active;
reg spc4_intr0_active;
reg spc4_intr1_active;
reg spc4_intr2_active;
reg spc4_intr3_active;
always @(negedge clk)
begin
if(~rst_l)
begin
spc4_mbar0_active <= 1'b0;
spc4_mbar1_active <= 1'b0;
spc4_mbar2_active <= 1'b0;
spc4_mbar3_active <= 1'b0;
spc4_flush0_active <= 1'b0;
spc4_flush1_active <= 1'b0;
spc4_flush2_active <= 1'b0;
spc4_flush3_active <= 1'b0;
spc4_intr0_active <= 1'b0;
spc4_intr1_active <= 1'b0;
spc4_intr2_active <= 1'b0;
spc4_intr3_active <= 1'b0;
end
else
begin
if(spc4_mbar_inst0_g & ~spc4_dctl_flush_pipe_w & (C4T0_stb_ne|~spc4_no_spc_rmo_st[0]))
spc4_mbar0_active <= 1'b1;
else if(~C4T0_stb_ne & spc4_no_spc_rmo_st[0])
spc4_mbar0_active <= 1'b0;
if(spc4_mbar_inst1_g & ~ spc4_dctl_flush_pipe_w & (C4T1_stb_ne|~spc4_no_spc_rmo_st[1]))
spc4_mbar1_active <= 1'b1;
else if(~C4T1_stb_ne & spc4_no_spc_rmo_st[1])
spc4_mbar1_active <= 1'b0;
if(spc4_mbar_inst2_g & ~ spc4_dctl_flush_pipe_w & (C4T2_stb_ne|~spc4_no_spc_rmo_st[2]))
spc4_mbar2_active <= 1'b1;
else if(~C4T2_stb_ne & spc4_no_spc_rmo_st[2])
spc4_mbar2_active <= 1'b0;
if(spc4_mbar_inst3_g & ~ spc4_dctl_flush_pipe_w & (C4T3_stb_ne|~spc4_no_spc_rmo_st[3]))
spc4_mbar3_active <= 1'b1;
else if(~C4T3_stb_ne & spc4_no_spc_rmo_st[3])
spc4_mbar3_active <= 1'b0;
if(spc4_flush_inst0_g & ~spc4_dctl_flush_pipe_w & C4T0_stb_ne) spc4_flush0_active <= 1'b1;
else if(~C4T0_stb_ne) spc4_flush0_active <= 1'b0;
if(spc4_flush_inst1_g & ~spc4_dctl_flush_pipe_w & C4T1_stb_ne) spc4_flush1_active <= 1'b1;
else if(~C4T1_stb_ne) spc4_flush1_active <= 1'b0;
if(spc4_flush_inst2_g & ~spc4_dctl_flush_pipe_w & C4T2_stb_ne) spc4_flush2_active <= 1'b1;
else if(~C4T2_stb_ne) spc4_flush2_active <= 1'b0;
if(spc4_flush_inst3_g & ~spc4_dctl_flush_pipe_w & C4T3_stb_ne) spc4_flush3_active <= 1'b1;
else if(~C4T3_stb_ne) spc4_flush3_active <= 1'b0;
if(spc4_intrpt_disp_asi0_g & spc4_st_inst_vld_g & ~spc4_non_altspace_ldst_g & ~spc4_dctl_flush_pipe_w & C4T0_stb_ne)
spc4_intr0_active <= 1'b1;
else if(~C4T0_stb_ne)
spc4_intr0_active <= 1'b0;
if(spc4_intrpt_disp_asi1_g & spc4_st_inst_vld_g & ~spc4_non_altspace_ldst_g & ~spc4_dctl_flush_pipe_w & C4T1_stb_ne)
spc4_intr1_active <= 1'b1;
else if(~C4T1_stb_ne)
spc4_intr1_active <= 1'b0;
if(spc4_intrpt_disp_asi2_g & spc4_st_inst_vld_g & ~spc4_non_altspace_ldst_g & ~spc4_dctl_flush_pipe_w & C4T2_stb_ne)
spc4_intr2_active <= 1'b1;
else if(~C4T2_stb_ne)
spc4_intr2_active <= 1'b0;
if(spc4_intrpt_disp_asi3_g & spc4_st_inst_vld_g & ~spc4_non_altspace_ldst_g & ~spc4_dctl_flush_pipe_w & C4T3_stb_ne)
spc4_intr3_active <= 1'b1;
else if(~C4T3_stb_ne)
spc4_intr3_active <= 1'b0;
end
if(spc4_mbar0_active & spc4_inst_vld_w & spc4_sas_thrid_w[1:0] == 2'b00)
finish_test("spc", "membar violation thread 0", 4);
if(spc4_mbar1_active & spc4_inst_vld_w & spc4_sas_thrid_w[1:0] == 2'b01)
finish_test("spc", "membar violation thread 1", 4);
if(spc4_mbar2_active & spc4_inst_vld_w & spc4_sas_thrid_w[1:0] == 2'b10)
finish_test("spc", "membar violation thread 2", 4);
if(spc4_mbar3_active & spc4_inst_vld_w & spc4_sas_thrid_w[1:0] == 2'b11)
finish_test("spc", "membar violation thread 3", 4);
if(spc4_flush0_active & spc4_inst_vld_w & spc4_sas_thrid_w[1:0] == 2'b00)
finish_test("spc", "flush violation thread 0", 4);
if(spc4_flush1_active & spc4_inst_vld_w & spc4_sas_thrid_w[1:0] == 2'b01)
finish_test("spc", "flush violation thread 1", 4);
if(spc4_flush2_active & spc4_inst_vld_w & spc4_sas_thrid_w[1:0] == 2'b10)
finish_test("spc", "flush violation thread 2", 4);
if(spc4_flush3_active & spc4_inst_vld_w & spc4_sas_thrid_w[1:0] == 2'b11)
finish_test("spc", "flush violation thread 3", 4);
if(spc4_intr0_active & spc4_inst_vld_w & spc4_sas_thrid_w[1:0] == 2'b00)
finish_test("spc", "intr violation thread 0", 4);
if(spc4_intr1_active & spc4_inst_vld_w & spc4_sas_thrid_w[1:0] == 2'b01)
finish_test("spc", "intr violation thread 1", 4);
if(spc4_intr2_active & spc4_inst_vld_w & spc4_sas_thrid_w[1:0] == 2'b10)
finish_test("spc", "intr violation thread 2", 4);
if(spc4_intr3_active & spc4_inst_vld_w & spc4_sas_thrid_w[1:0] == 2'b11)
finish_test("spc", "intr violation thread 3", 4);
if(~rst_l | ~C4T0_stb_full | sctag_pcx_stall_pq) C4T0_stb_drain_cnt = 0;
else C4T0_stb_drain_cnt = C4T0_stb_drain_cnt + 1;
if(C4T0_stb_drain_cnt > stb_drain_to_max)
finish_test("spc", "stb 0 is not draining", 4);
if(~rst_l | ~C4T1_stb_full | sctag_pcx_stall_pq) C4T1_stb_drain_cnt = 0;
else C4T1_stb_drain_cnt = C4T1_stb_drain_cnt + 1;
if(C4T1_stb_drain_cnt > stb_drain_to_max)
finish_test("spc", "stb 1 is not draining", 4);
if(~rst_l | ~C4T2_stb_full | sctag_pcx_stall_pq) C4T2_stb_drain_cnt = 0;
else C4T2_stb_drain_cnt = C4T2_stb_drain_cnt + 1;
if(C4T2_stb_drain_cnt > stb_drain_to_max)
finish_test("spc", "stb 2 is not draining", 4);
if(~rst_l | ~C4T3_stb_full | sctag_pcx_stall_pq) C4T3_stb_drain_cnt = 0;
else C4T3_stb_drain_cnt = C4T3_stb_drain_cnt + 1;
if(C4T3_stb_drain_cnt > stb_drain_to_max)
finish_test("spc", "stb 3 is not draining", 4);
C4T0_stb_vld_sum_d1 <= C4T0_stb_vld_sum;
C4T1_stb_vld_sum_d1 <= C4T1_stb_vld_sum;
C4T2_stb_vld_sum_d1 <= C4T2_stb_vld_sum;
C4T3_stb_vld_sum_d1 <= C4T3_stb_vld_sum;
C4T0_defr_trp_en_d1 <= C4T0_defr_trp_en;
C4T1_defr_trp_en_d1 <= C4T1_defr_trp_en;
C4T2_defr_trp_en_d1 <= C4T2_defr_trp_en;
C4T3_defr_trp_en_d1 <= C4T3_defr_trp_en;
if(rst_l & C4T0_defr_trp_en_d1 & (C4T0_stb_vld_sum_d1 < C4T0_stb_vld_sum))
finish_test("spc", "tso_mon: deferred trap problems for store T0", 4);
if(rst_l & C4T1_defr_trp_en_d1 & (C4T1_stb_vld_sum_d1 < C4T1_stb_vld_sum))
finish_test("spc", "tso_mon: deferred trap problems for store T1", 4);
if(rst_l & C4T2_defr_trp_en_d1 & (C4T2_stb_vld_sum_d1 < C4T2_stb_vld_sum))
finish_test("spc", "tso_mon: deferred trap problems for store T2", 4);
if(rst_l & C4T3_defr_trp_en_d1 & (C4T3_stb_vld_sum_d1 < C4T3_stb_vld_sum))
finish_test("spc", "tso_mon: deferred trap problems for store T3", 4);
end
`endif // ifdef RTL_SPARC4
`ifdef RTL_SPARC5
wire C5T0_stb_ne = |`TOP_DESIGN.sparc5.lsu.stb_ctl0.stb_state_vld[7:0];
wire C5T1_stb_ne = |`TOP_DESIGN.sparc5.lsu.stb_ctl1.stb_state_vld[7:0];
wire C5T2_stb_ne = |`TOP_DESIGN.sparc5.lsu.stb_ctl2.stb_state_vld[7:0];
wire C5T3_stb_ne = |`TOP_DESIGN.sparc5.lsu.stb_ctl3.stb_state_vld[7:0];
wire C5T0_stb_nced = |( `TOP_DESIGN.sparc5.lsu.stb_ctl0.stb_state_vld[7:0] &
~`TOP_DESIGN.sparc5.lsu.stb_ctl0.stb_state_ced[7:0]);
wire C5T1_stb_nced = |( `TOP_DESIGN.sparc5.lsu.stb_ctl1.stb_state_vld[7:0] &
~`TOP_DESIGN.sparc5.lsu.stb_ctl1.stb_state_ced[7:0]);
wire C5T2_stb_nced = |( `TOP_DESIGN.sparc5.lsu.stb_ctl2.stb_state_vld[7:0] &
~`TOP_DESIGN.sparc5.lsu.stb_ctl2.stb_state_ced[7:0]);
wire C5T3_stb_nced = |( `TOP_DESIGN.sparc5.lsu.stb_ctl3.stb_state_vld[7:0] &
~`TOP_DESIGN.sparc5.lsu.stb_ctl3.stb_state_ced[7:0]);
`else
wire C5T0_stb_ne = 1'b0;
wire C5T1_stb_ne = 1'b0;
wire C5T2_stb_ne = 1'b0;
wire C5T3_stb_ne = 1'b0;
wire C5T0_stb_nced = 1'b0;
wire C5T1_stb_nced = 1'b0;
wire C5T2_stb_nced = 1'b0;
wire C5T3_stb_nced = 1'b0;
`endif // ifdef RTL_SPARC5
`ifdef RTL_SPARC5
wire spc5_lsu_ifill_pkt_vld = `TOP_DESIGN.sparc5.lsu.qctl2.lsu_ifill_pkt_vld;
wire spc5_dfq_rd_advance = `TOP_DESIGN.sparc5.lsu.qctl2.dfq_rd_advance;
wire spc5_dfq_int_type = `TOP_DESIGN.sparc5.lsu.qctl2.dfq_int_type;
wire spc5_ifu_lsu_inv_clear = `TOP_DESIGN.sparc5.lsu.qctl2.ifu_lsu_inv_clear;
wire spc5_dva_svld_e = `TOP_DESIGN.sparc5.lsu.qctl2.dva_svld_e;
wire spc5_dva_rvld_e = `TOP_DESIGN.sparc5.lsu.dva.rd_en;
wire [10:4] spc5_dva_rd_addr_e = `TOP_DESIGN.sparc5.lsu.dva.rd_adr1[6:0];
wire [4:0] spc5_dva_snp_addr_e = `TOP_DESIGN.sparc5.lsu.qctl2.dva_snp_addr_e[4:0];
wire [4:0] spc5_stb_data_rd_ptr = `TOP_DESIGN.sparc5.lsu.stb_data_rd_ptr[4:0];
wire [4:0] spc5_stb_data_wr_ptr = `TOP_DESIGN.sparc5.lsu.stb_data_wr_ptr[4:0];
wire spc5_stb_data_wptr_vld = `TOP_DESIGN.sparc5.lsu.stb_data_wptr_vld;
wire spc5_stb_data_rptr_vld = `TOP_DESIGN.sparc5.lsu.stb_data_rptr_vld;
wire spc5_stbrwctl_flush_pipe_w = `TOP_DESIGN.sparc5.lsu.stb_rwctl.lsu_stbrwctl_flush_pipe_w;
wire spc5_lsu_st_pcx_rq_pick = |`TOP_DESIGN.sparc5.lsu.stb_rwctl.lsu_st_pcx_rq_pick[3:0];
wire [3:0] spc5_lsu_rd_dtag_parity_g = `TOP_DESIGN.sparc5.lsu.dctl.lsu_rd_dtag_parity_g[3:0];
wire [3:0] spc5_dva_vld_g = `TOP_DESIGN.sparc5.lsu.dctl.dva_vld_g[3:0];
wire [3:0] spc5_lsu_dc_tag_pe_g_unmasked = spc5_lsu_rd_dtag_parity_g[3:0] & spc5_dva_vld_g[3:0];
wire spc5_lsu_dc_tag_pe_g_unmasked_or = |spc5_lsu_dc_tag_pe_g_unmasked[3:0];
wire C5T0_stb_full = &`TOP_DESIGN.sparc5.lsu.stb_ctl0.stb_state_vld[7:0];
wire C5T1_stb_full = &`TOP_DESIGN.sparc5.lsu.stb_ctl1.stb_state_vld[7:0];
wire C5T2_stb_full = &`TOP_DESIGN.sparc5.lsu.stb_ctl2.stb_state_vld[7:0];
wire C5T3_stb_full = &`TOP_DESIGN.sparc5.lsu.stb_ctl3.stb_state_vld[7:0];
wire [7:0] C5T0_stb_vld = `TOP_DESIGN.sparc5.lsu.stb_ctl0.stb_state_vld[7:0];
wire [7:0] C5T1_stb_vld = `TOP_DESIGN.sparc5.lsu.stb_ctl1.stb_state_vld[7:0];
wire [7:0] C5T2_stb_vld = `TOP_DESIGN.sparc5.lsu.stb_ctl2.stb_state_vld[7:0];
wire [7:0] C5T3_stb_vld = `TOP_DESIGN.sparc5.lsu.stb_ctl3.stb_state_vld[7:0];
wire [4:0] C5T0_stb_vld_sum = C5T0_stb_vld[0] + C5T0_stb_vld[1] + C5T0_stb_vld[2] + C5T0_stb_vld[3] +
C5T0_stb_vld[4] + C5T0_stb_vld[5] + C5T0_stb_vld[6] + C5T0_stb_vld[7] ;
wire [4:0] C5T1_stb_vld_sum = C5T1_stb_vld[0] + C5T1_stb_vld[1] + C5T1_stb_vld[2] + C5T1_stb_vld[3] +
C5T1_stb_vld[4] + C5T1_stb_vld[5] + C5T1_stb_vld[6] + C5T1_stb_vld[7] ;
wire [4:0] C5T2_stb_vld_sum = C5T2_stb_vld[0] + C5T2_stb_vld[1] + C5T2_stb_vld[2] + C5T2_stb_vld[3] +
C5T2_stb_vld[4] + C5T2_stb_vld[5] + C5T2_stb_vld[6] + C5T2_stb_vld[7] ;
wire [4:0] C5T3_stb_vld_sum = C5T3_stb_vld[0] + C5T3_stb_vld[1] + C5T3_stb_vld[2] + C5T3_stb_vld[3] +
C5T3_stb_vld[4] + C5T3_stb_vld[5] + C5T3_stb_vld[6] + C5T3_stb_vld[7] ;
reg [4:0] C5T0_stb_vld_sum_d1;
reg [4:0] C5T1_stb_vld_sum_d1;
reg [4:0] C5T2_stb_vld_sum_d1;
reg [4:0] C5T3_stb_vld_sum_d1;
wire C5T0_st_ack = &`TOP_DESIGN.sparc5.lsu.cpx_st_ack_tid0;
wire C5T1_st_ack = &`TOP_DESIGN.sparc5.lsu.cpx_st_ack_tid1;
wire C5T2_st_ack = &`TOP_DESIGN.sparc5.lsu.cpx_st_ack_tid2;
wire C5T3_st_ack = &`TOP_DESIGN.sparc5.lsu.cpx_st_ack_tid3;
wire C5T0_defr_trp_en = &`TOP_DESIGN.sparc5.lsu.excpctl.st_defr_trp_en0;
wire C5T1_defr_trp_en = &`TOP_DESIGN.sparc5.lsu.excpctl.st_defr_trp_en1;
wire C5T2_defr_trp_en = &`TOP_DESIGN.sparc5.lsu.excpctl.st_defr_trp_en2;
wire C5T3_defr_trp_en = &`TOP_DESIGN.sparc5.lsu.excpctl.st_defr_trp_en3;
reg C5T0_defr_trp_en_d1;
reg C5T1_defr_trp_en_d1;
reg C5T2_defr_trp_en_d1;
reg C5T3_defr_trp_en_d1;
integer C5T0_stb_drain_cnt;
integer C5T1_stb_drain_cnt;
integer C5T2_stb_drain_cnt;
integer C5T3_stb_drain_cnt;
// Hits in the store buffer
//-------------------------
wire spc5_inst_vld_w = `TOP_DESIGN.sparc5.ifu.fcl.inst_vld_w;
wire [1:0] spc5_sas_thrid_w = `TOP_DESIGN.sparc5.ifu.fcl.sas_thrid_w[1:0];
wire C5_st_ack_w = (spc5_sas_thrid_w == 2'b00) & C5T0_st_ack |
(spc5_sas_thrid_w == 2'b01) & C5T1_st_ack |
(spc5_sas_thrid_w == 2'b10) & C5T2_st_ack |
(spc5_sas_thrid_w == 2'b11) & C5T3_st_ack;
wire [7:0] spc5_stb_ld_full_raw = `TOP_DESIGN.sparc5.lsu.stb_ld_full_raw[7:0];
wire [7:0] spc5_stb_ld_partial_raw = `TOP_DESIGN.sparc5.lsu.stb_ld_partial_raw[7:0];
wire spc5_stb_cam_mhit = `TOP_DESIGN.sparc5.lsu.stb_cam_mhit;
wire spc5_stb_cam_hit = `TOP_DESIGN.sparc5.lsu.stb_cam_hit;
wire [3:0] spc5_lsu_way_hit = `TOP_DESIGN.sparc5.lsu.dctl.lsu_way_hit[3:0];
wire spc5_lsu_ifu_ldst_miss_w = `TOP_DESIGN.sparc5.lsu.lsu_ifu_ldst_miss_w;
wire spc5_ld_inst_vld_g = `TOP_DESIGN.sparc5.lsu.dctl.ld_inst_vld_g;
wire spc5_ldst_dbl_g = `TOP_DESIGN.sparc5.lsu.dctl.ldst_dbl_g;
wire spc5_quad_asi_g = `TOP_DESIGN.sparc5.lsu.dctl.quad_asi_g;
wire [1:0] spc5_ldst_sz_g = `TOP_DESIGN.sparc5.lsu.dctl.ldst_sz_g;
wire spc5_lsu_alt_space_g = `TOP_DESIGN.sparc5.lsu.dctl.lsu_alt_space_g;
wire spc5_mbar_inst0_g = `TOP_DESIGN.sparc5.lsu.dctl.mbar_inst0_g;
wire spc5_mbar_inst1_g = `TOP_DESIGN.sparc5.lsu.dctl.mbar_inst1_g;
wire spc5_mbar_inst2_g = `TOP_DESIGN.sparc5.lsu.dctl.mbar_inst2_g;
wire spc5_mbar_inst3_g = `TOP_DESIGN.sparc5.lsu.dctl.mbar_inst3_g;
wire spc5_flush_inst0_g = `TOP_DESIGN.sparc5.lsu.dctl.flush_inst0_g;
wire spc5_flush_inst1_g = `TOP_DESIGN.sparc5.lsu.dctl.flush_inst1_g;
wire spc5_flush_inst2_g = `TOP_DESIGN.sparc5.lsu.dctl.flush_inst2_g;
wire spc5_flush_inst3_g = `TOP_DESIGN.sparc5.lsu.dctl.flush_inst3_g;
wire spc5_intrpt_disp_asi0_g = `TOP_DESIGN.sparc5.lsu.dctl.intrpt_disp_asi_g & (spc5_sas_thrid_w == 2'b00);
wire spc5_intrpt_disp_asi1_g = `TOP_DESIGN.sparc5.lsu.dctl.intrpt_disp_asi_g & (spc5_sas_thrid_w == 2'b01);
wire spc5_intrpt_disp_asi2_g = `TOP_DESIGN.sparc5.lsu.dctl.intrpt_disp_asi_g & (spc5_sas_thrid_w == 2'b10);
wire spc5_intrpt_disp_asi3_g = `TOP_DESIGN.sparc5.lsu.dctl.intrpt_disp_asi_g & (spc5_sas_thrid_w == 2'b11);
wire spc5_st_inst_vld_g = `TOP_DESIGN.sparc5.lsu.dctl.st_inst_vld_g;
wire spc5_non_altspace_ldst_g = `TOP_DESIGN.sparc5.lsu.dctl.non_altspace_ldst_g;
wire spc5_dctl_flush_pipe_w = `TOP_DESIGN.sparc5.lsu.dctl.dctl_flush_pipe_w;
wire [3:0] spc5_no_spc_rmo_st = `TOP_DESIGN.sparc5.lsu.dctl.no_spc_rmo_st[3:0];
wire spc5_ldst_fp_e = `TOP_DESIGN.sparc5.lsu.ifu_lsu_ldst_fp_e;
wire [2:0] spc5_stb_rdptr = `TOP_DESIGN.sparc5.lsu.stb_rwctl.stb_rdptr_l;
wire spc5_ld_l2cache_req = `TOP_DESIGN.sparc5.lsu.qctl1.ld3_l2cache_rq |
`TOP_DESIGN.sparc5.lsu.qctl1.ld2_l2cache_rq |
`TOP_DESIGN.sparc5.lsu.qctl1.ld1_l2cache_rq |
`TOP_DESIGN.sparc5.lsu.qctl1.ld0_l2cache_rq;
wire [3:0] spc5_dcache_enable = {`TOP_DESIGN.sparc5.lsu.dctl.lsu_ctl_reg0[1],
`TOP_DESIGN.sparc5.lsu.dctl.lsu_ctl_reg1[1],
`TOP_DESIGN.sparc5.lsu.dctl.lsu_ctl_reg2[1],
`TOP_DESIGN.sparc5.lsu.dctl.lsu_ctl_reg3[1]};
wire [3:0] spc5_icache_enable = `TOP_DESIGN.sparc5.lsu.lsu_ifu_icache_en[3:0];
wire spc5_dc_direct_map = `TOP_DESIGN.sparc5.lsu.dc_direct_map;
wire spc5_lsu_ifu_direct_map_l1 = `TOP_DESIGN.sparc5.lsu.lsu_ifu_direct_map_l1;
always @(spc5_dcache_enable)
$display("%0d tso_mon: spc5_dcache_enable changed to %x", $time, spc5_dcache_enable);
always @(spc5_icache_enable)
$display("%0d tso_mon: spc5_icache_enable changed to %x", $time, spc5_icache_enable);
always @(spc5_dc_direct_map)
$display("%0d tso_mon: spc5_dc_direct_map changed to %x", $time, spc5_dc_direct_map);
always @(spc5_lsu_ifu_direct_map_l1)
$display("%0d tso_mon: spc5_lsu_ifu_direct_map_l1 changed to %x", $time, spc5_lsu_ifu_direct_map_l1);
reg spc5_dva_svld_e_d1;
reg spc5_dva_rvld_e_d1;
reg [10:4] spc5_dva_rd_addr_e_d1;
reg [4:0] spc5_dva_snp_addr_e_d1;
reg spc5_lsu_snp_after_rd;
reg spc5_lsu_rd_after_snp;
reg spc5_ldst_fp_m, spc5_ldst_fp_g;
integer spc5_multiple_hits;
reg spc5_skid_d1, spc5_skid_d2, spc5_skid_d3;
initial begin
spc5_skid_d1 = 0;
spc5_skid_d2 = 0;
spc5_skid_d3 = 0;
end
always @(posedge clk)
begin
spc5_skid_d1 <= (~spc5_ifu_lsu_inv_clear & spc5_dfq_rd_advance & spc5_dfq_int_type);
spc5_skid_d2 <= spc5_skid_d1 & ~spc5_ifu_lsu_inv_clear;
spc5_skid_d3 <= spc5_skid_d2 & ~spc5_ifu_lsu_inv_clear;
// The full tracking of this condition is complicated since after the interrupt is advanced
// there may be more invalidations to the IFQ.
// All we care about is that the invalidations BEFORE the interrupt are finished.
// I provided a command line argument to disable this check.
if(spc5_skid_d3 & enable_ifu_lsu_inv_clear)
finish_test("spc", "tso_mon: spc5_ifu_lsu_inv_clear should have been clear by now", 5);
spc5_dva_svld_e_d1 <= spc5_dva_svld_e;
spc5_dva_rvld_e_d1 <= spc5_dva_rvld_e;
spc5_dva_rd_addr_e_d1 <= spc5_dva_rd_addr_e;
spc5_dva_snp_addr_e_d1 <= spc5_dva_snp_addr_e;
if(spc5_dva_svld_e_d1 & spc5_dva_rvld_e & (spc5_dva_rd_addr_e_d1[10:6] == spc5_dva_snp_addr_e[4:0]))
spc5_lsu_rd_after_snp <= 1'b1;
else
spc5_lsu_rd_after_snp <= 1'b0;
if(spc5_dva_svld_e & spc5_dva_rvld_e_d1 & (spc5_dva_rd_addr_e[10:6] == spc5_dva_snp_addr_e_d1[4:0]))
spc5_lsu_snp_after_rd <= 1'b1;
else
spc5_lsu_snp_after_rd <= 1'b0;
spc5_ldst_fp_m <= spc5_ldst_fp_e;
spc5_ldst_fp_g <= spc5_ldst_fp_m;
if(spc5_stb_data_rptr_vld & spc5_stb_data_wptr_vld & ~spc5_stbrwctl_flush_pipe_w &
(spc5_stb_data_rd_ptr == spc5_stb_data_wr_ptr) & spc5_lsu_st_pcx_rq_pick)
begin
finish_test("spc", "tso_mon: LSU stb data write and read in the same cycle", 5);
end
spc5_multiple_hits = (spc5_lsu_way_hit[3] + spc5_lsu_way_hit[2] + spc5_lsu_way_hit[1] + spc5_lsu_way_hit[0]);
if(!spc5_lsu_ifu_ldst_miss_w && (spc5_multiple_hits >1) && spc5_inst_vld_w && !spc5_dctl_flush_pipe_w && !spc5_lsu_dc_tag_pe_g_unmasked_or)
finish_test("spc", "tso_mon: LSU multiple hits ", 5);
end
wire spc5_ld_dbl = spc5_ld_inst_vld_g & spc5_ldst_dbl_g & ~spc5_quad_asi_g;
wire spc5_ld_quad = spc5_ld_inst_vld_g & spc5_ldst_dbl_g & spc5_quad_asi_g;
wire spc5_ld_other = spc5_ld_inst_vld_g & ~spc5_ldst_dbl_g;
wire spc5_ld_dbl_fp = spc5_ld_dbl & spc5_ldst_fp_g;
wire spc5_ld_other_fp = spc5_ld_other & spc5_ldst_fp_g;
wire spc5_ld_dbl_int = spc5_ld_dbl & ~spc5_ldst_fp_g;
wire spc5_ld_quad_int = spc5_ld_quad & ~spc5_ldst_fp_g;
wire spc5_ld_other_int= spc5_ld_other & ~spc5_ldst_fp_g;
wire spc5_ld_bypassok_hit = |spc5_stb_ld_full_raw[7:0] & ~spc5_stb_cam_mhit;
wire spc5_ld_partial_hit = |spc5_stb_ld_partial_raw[7:0] & ~spc5_stb_cam_mhit;
wire spc5_ld_multiple_hit = spc5_stb_cam_mhit;
wire spc5_any_lsu_way_hit = |spc5_lsu_way_hit;
wire [7:0] spc5_stb_rdptr_decoded = (spc5_stb_rdptr ==3'b000) ? 8'b00000001 :
(spc5_stb_rdptr ==3'b001) ? 8'b00000010 :
(spc5_stb_rdptr ==3'b010) ? 8'b00000100 :
(spc5_stb_rdptr ==3'b011) ? 8'b00001000 :
(spc5_stb_rdptr ==3'b100) ? 8'b00010000 :
(spc5_stb_rdptr ==3'b101) ? 8'b00100000 :
(spc5_stb_rdptr ==3'b110) ? 8'b01000000 :
(spc5_stb_rdptr ==3'b111) ? 8'b10000000 : 8'h00;
wire spc5_stb_top_hit = |(spc5_stb_rdptr_decoded & (spc5_stb_ld_full_raw | spc5_stb_ld_partial_raw));
//---------------------------------------------------------------------
// ld_type[4:0] hit_type[2:0], cache_hit, hit_top
// this is passed to the coverage monitor.
//---------------------------------------------------------------------
wire [10:0] spc5_stb_ld_hit_info =
{spc5_ld_dbl_fp, spc5_ld_other_fp,
spc5_ld_dbl_int, spc5_ld_quad_int, spc5_ld_other_int,
spc5_ld_bypassok_hit, spc5_ld_partial_hit, spc5_ld_multiple_hit,
spc5_any_lsu_way_hit,
spc5_stb_top_hit, C5_st_ack_w};
reg spc5_mbar0_active;
reg spc5_mbar1_active;
reg spc5_mbar2_active;
reg spc5_mbar3_active;
reg spc5_flush0_active;
reg spc5_flush1_active;
reg spc5_flush2_active;
reg spc5_flush3_active;
reg spc5_intr0_active;
reg spc5_intr1_active;
reg spc5_intr2_active;
reg spc5_intr3_active;
always @(negedge clk)
begin
if(~rst_l)
begin
spc5_mbar0_active <= 1'b0;
spc5_mbar1_active <= 1'b0;
spc5_mbar2_active <= 1'b0;
spc5_mbar3_active <= 1'b0;
spc5_flush0_active <= 1'b0;
spc5_flush1_active <= 1'b0;
spc5_flush2_active <= 1'b0;
spc5_flush3_active <= 1'b0;
spc5_intr0_active <= 1'b0;
spc5_intr1_active <= 1'b0;
spc5_intr2_active <= 1'b0;
spc5_intr3_active <= 1'b0;
end
else
begin
if(spc5_mbar_inst0_g & ~spc5_dctl_flush_pipe_w & (C5T0_stb_ne|~spc5_no_spc_rmo_st[0]))
spc5_mbar0_active <= 1'b1;
else if(~C5T0_stb_ne & spc5_no_spc_rmo_st[0])
spc5_mbar0_active <= 1'b0;
if(spc5_mbar_inst1_g & ~ spc5_dctl_flush_pipe_w & (C5T1_stb_ne|~spc5_no_spc_rmo_st[1]))
spc5_mbar1_active <= 1'b1;
else if(~C5T1_stb_ne & spc5_no_spc_rmo_st[1])
spc5_mbar1_active <= 1'b0;
if(spc5_mbar_inst2_g & ~ spc5_dctl_flush_pipe_w & (C5T2_stb_ne|~spc5_no_spc_rmo_st[2]))
spc5_mbar2_active <= 1'b1;
else if(~C5T2_stb_ne & spc5_no_spc_rmo_st[2])
spc5_mbar2_active <= 1'b0;
if(spc5_mbar_inst3_g & ~ spc5_dctl_flush_pipe_w & (C5T3_stb_ne|~spc5_no_spc_rmo_st[3]))
spc5_mbar3_active <= 1'b1;
else if(~C5T3_stb_ne & spc5_no_spc_rmo_st[3])
spc5_mbar3_active <= 1'b0;
if(spc5_flush_inst0_g & ~spc5_dctl_flush_pipe_w & C5T0_stb_ne) spc5_flush0_active <= 1'b1;
else if(~C5T0_stb_ne) spc5_flush0_active <= 1'b0;
if(spc5_flush_inst1_g & ~spc5_dctl_flush_pipe_w & C5T1_stb_ne) spc5_flush1_active <= 1'b1;
else if(~C5T1_stb_ne) spc5_flush1_active <= 1'b0;
if(spc5_flush_inst2_g & ~spc5_dctl_flush_pipe_w & C5T2_stb_ne) spc5_flush2_active <= 1'b1;
else if(~C5T2_stb_ne) spc5_flush2_active <= 1'b0;
if(spc5_flush_inst3_g & ~spc5_dctl_flush_pipe_w & C5T3_stb_ne) spc5_flush3_active <= 1'b1;
else if(~C5T3_stb_ne) spc5_flush3_active <= 1'b0;
if(spc5_intrpt_disp_asi0_g & spc5_st_inst_vld_g & ~spc5_non_altspace_ldst_g & ~spc5_dctl_flush_pipe_w & C5T0_stb_ne)
spc5_intr0_active <= 1'b1;
else if(~C5T0_stb_ne)
spc5_intr0_active <= 1'b0;
if(spc5_intrpt_disp_asi1_g & spc5_st_inst_vld_g & ~spc5_non_altspace_ldst_g & ~spc5_dctl_flush_pipe_w & C5T1_stb_ne)
spc5_intr1_active <= 1'b1;
else if(~C5T1_stb_ne)
spc5_intr1_active <= 1'b0;
if(spc5_intrpt_disp_asi2_g & spc5_st_inst_vld_g & ~spc5_non_altspace_ldst_g & ~spc5_dctl_flush_pipe_w & C5T2_stb_ne)
spc5_intr2_active <= 1'b1;
else if(~C5T2_stb_ne)
spc5_intr2_active <= 1'b0;
if(spc5_intrpt_disp_asi3_g & spc5_st_inst_vld_g & ~spc5_non_altspace_ldst_g & ~spc5_dctl_flush_pipe_w & C5T3_stb_ne)
spc5_intr3_active <= 1'b1;
else if(~C5T3_stb_ne)
spc5_intr3_active <= 1'b0;
end
if(spc5_mbar0_active & spc5_inst_vld_w & spc5_sas_thrid_w[1:0] == 2'b00)
finish_test("spc", "membar violation thread 0", 5);
if(spc5_mbar1_active & spc5_inst_vld_w & spc5_sas_thrid_w[1:0] == 2'b01)
finish_test("spc", "membar violation thread 1", 5);
if(spc5_mbar2_active & spc5_inst_vld_w & spc5_sas_thrid_w[1:0] == 2'b10)
finish_test("spc", "membar violation thread 2", 5);
if(spc5_mbar3_active & spc5_inst_vld_w & spc5_sas_thrid_w[1:0] == 2'b11)
finish_test("spc", "membar violation thread 3", 5);
if(spc5_flush0_active & spc5_inst_vld_w & spc5_sas_thrid_w[1:0] == 2'b00)
finish_test("spc", "flush violation thread 0", 5);
if(spc5_flush1_active & spc5_inst_vld_w & spc5_sas_thrid_w[1:0] == 2'b01)
finish_test("spc", "flush violation thread 1", 5);
if(spc5_flush2_active & spc5_inst_vld_w & spc5_sas_thrid_w[1:0] == 2'b10)
finish_test("spc", "flush violation thread 2", 5);
if(spc5_flush3_active & spc5_inst_vld_w & spc5_sas_thrid_w[1:0] == 2'b11)
finish_test("spc", "flush violation thread 3", 5);
if(spc5_intr0_active & spc5_inst_vld_w & spc5_sas_thrid_w[1:0] == 2'b00)
finish_test("spc", "intr violation thread 0", 5);
if(spc5_intr1_active & spc5_inst_vld_w & spc5_sas_thrid_w[1:0] == 2'b01)
finish_test("spc", "intr violation thread 1", 5);
if(spc5_intr2_active & spc5_inst_vld_w & spc5_sas_thrid_w[1:0] == 2'b10)
finish_test("spc", "intr violation thread 2", 5);
if(spc5_intr3_active & spc5_inst_vld_w & spc5_sas_thrid_w[1:0] == 2'b11)
finish_test("spc", "intr violation thread 3", 5);
if(~rst_l | ~C5T0_stb_full | sctag_pcx_stall_pq) C5T0_stb_drain_cnt = 0;
else C5T0_stb_drain_cnt = C5T0_stb_drain_cnt + 1;
if(C5T0_stb_drain_cnt > stb_drain_to_max)
finish_test("spc", "stb 0 is not draining", 5);
if(~rst_l | ~C5T1_stb_full | sctag_pcx_stall_pq) C5T1_stb_drain_cnt = 0;
else C5T1_stb_drain_cnt = C5T1_stb_drain_cnt + 1;
if(C5T1_stb_drain_cnt > stb_drain_to_max)
finish_test("spc", "stb 1 is not draining", 5);
if(~rst_l | ~C5T2_stb_full | sctag_pcx_stall_pq) C5T2_stb_drain_cnt = 0;
else C5T2_stb_drain_cnt = C5T2_stb_drain_cnt + 1;
if(C5T2_stb_drain_cnt > stb_drain_to_max)
finish_test("spc", "stb 2 is not draining", 5);
if(~rst_l | ~C5T3_stb_full | sctag_pcx_stall_pq) C5T3_stb_drain_cnt = 0;
else C5T3_stb_drain_cnt = C5T3_stb_drain_cnt + 1;
if(C5T3_stb_drain_cnt > stb_drain_to_max)
finish_test("spc", "stb 3 is not draining", 5);
C5T0_stb_vld_sum_d1 <= C5T0_stb_vld_sum;
C5T1_stb_vld_sum_d1 <= C5T1_stb_vld_sum;
C5T2_stb_vld_sum_d1 <= C5T2_stb_vld_sum;
C5T3_stb_vld_sum_d1 <= C5T3_stb_vld_sum;
C5T0_defr_trp_en_d1 <= C5T0_defr_trp_en;
C5T1_defr_trp_en_d1 <= C5T1_defr_trp_en;
C5T2_defr_trp_en_d1 <= C5T2_defr_trp_en;
C5T3_defr_trp_en_d1 <= C5T3_defr_trp_en;
if(rst_l & C5T0_defr_trp_en_d1 & (C5T0_stb_vld_sum_d1 < C5T0_stb_vld_sum))
finish_test("spc", "tso_mon: deferred trap problems for store T0", 5);
if(rst_l & C5T1_defr_trp_en_d1 & (C5T1_stb_vld_sum_d1 < C5T1_stb_vld_sum))
finish_test("spc", "tso_mon: deferred trap problems for store T1", 5);
if(rst_l & C5T2_defr_trp_en_d1 & (C5T2_stb_vld_sum_d1 < C5T2_stb_vld_sum))
finish_test("spc", "tso_mon: deferred trap problems for store T2", 5);
if(rst_l & C5T3_defr_trp_en_d1 & (C5T3_stb_vld_sum_d1 < C5T3_stb_vld_sum))
finish_test("spc", "tso_mon: deferred trap problems for store T3", 5);
end
`endif // ifdef RTL_SPARC5
`ifdef RTL_SPARC6
wire C6T0_stb_ne = |`TOP_DESIGN.sparc6.lsu.stb_ctl0.stb_state_vld[7:0];
wire C6T1_stb_ne = |`TOP_DESIGN.sparc6.lsu.stb_ctl1.stb_state_vld[7:0];
wire C6T2_stb_ne = |`TOP_DESIGN.sparc6.lsu.stb_ctl2.stb_state_vld[7:0];
wire C6T3_stb_ne = |`TOP_DESIGN.sparc6.lsu.stb_ctl3.stb_state_vld[7:0];
wire C6T0_stb_nced = |( `TOP_DESIGN.sparc6.lsu.stb_ctl0.stb_state_vld[7:0] &
~`TOP_DESIGN.sparc6.lsu.stb_ctl0.stb_state_ced[7:0]);
wire C6T1_stb_nced = |( `TOP_DESIGN.sparc6.lsu.stb_ctl1.stb_state_vld[7:0] &
~`TOP_DESIGN.sparc6.lsu.stb_ctl1.stb_state_ced[7:0]);
wire C6T2_stb_nced = |( `TOP_DESIGN.sparc6.lsu.stb_ctl2.stb_state_vld[7:0] &
~`TOP_DESIGN.sparc6.lsu.stb_ctl2.stb_state_ced[7:0]);
wire C6T3_stb_nced = |( `TOP_DESIGN.sparc6.lsu.stb_ctl3.stb_state_vld[7:0] &
~`TOP_DESIGN.sparc6.lsu.stb_ctl3.stb_state_ced[7:0]);
`else
wire C6T0_stb_ne = 1'b0;
wire C6T1_stb_ne = 1'b0;
wire C6T2_stb_ne = 1'b0;
wire C6T3_stb_ne = 1'b0;
wire C6T0_stb_nced = 1'b0;
wire C6T1_stb_nced = 1'b0;
wire C6T2_stb_nced = 1'b0;
wire C6T3_stb_nced = 1'b0;
`endif // ifdef RTL_SPARC6
`ifdef RTL_SPARC6
wire spc6_lsu_ifill_pkt_vld = `TOP_DESIGN.sparc6.lsu.qctl2.lsu_ifill_pkt_vld;
wire spc6_dfq_rd_advance = `TOP_DESIGN.sparc6.lsu.qctl2.dfq_rd_advance;
wire spc6_dfq_int_type = `TOP_DESIGN.sparc6.lsu.qctl2.dfq_int_type;
wire spc6_ifu_lsu_inv_clear = `TOP_DESIGN.sparc6.lsu.qctl2.ifu_lsu_inv_clear;
wire spc6_dva_svld_e = `TOP_DESIGN.sparc6.lsu.qctl2.dva_svld_e;
wire spc6_dva_rvld_e = `TOP_DESIGN.sparc6.lsu.dva.rd_en;
wire [10:4] spc6_dva_rd_addr_e = `TOP_DESIGN.sparc6.lsu.dva.rd_adr1[6:0];
wire [4:0] spc6_dva_snp_addr_e = `TOP_DESIGN.sparc6.lsu.qctl2.dva_snp_addr_e[4:0];
wire [4:0] spc6_stb_data_rd_ptr = `TOP_DESIGN.sparc6.lsu.stb_data_rd_ptr[4:0];
wire [4:0] spc6_stb_data_wr_ptr = `TOP_DESIGN.sparc6.lsu.stb_data_wr_ptr[4:0];
wire spc6_stb_data_wptr_vld = `TOP_DESIGN.sparc6.lsu.stb_data_wptr_vld;
wire spc6_stb_data_rptr_vld = `TOP_DESIGN.sparc6.lsu.stb_data_rptr_vld;
wire spc6_stbrwctl_flush_pipe_w = `TOP_DESIGN.sparc6.lsu.stb_rwctl.lsu_stbrwctl_flush_pipe_w;
wire spc6_lsu_st_pcx_rq_pick = |`TOP_DESIGN.sparc6.lsu.stb_rwctl.lsu_st_pcx_rq_pick[3:0];
wire [3:0] spc6_lsu_rd_dtag_parity_g = `TOP_DESIGN.sparc6.lsu.dctl.lsu_rd_dtag_parity_g[3:0];
wire [3:0] spc6_dva_vld_g = `TOP_DESIGN.sparc6.lsu.dctl.dva_vld_g[3:0];
wire [3:0] spc6_lsu_dc_tag_pe_g_unmasked = spc6_lsu_rd_dtag_parity_g[3:0] & spc6_dva_vld_g[3:0];
wire spc6_lsu_dc_tag_pe_g_unmasked_or = |spc6_lsu_dc_tag_pe_g_unmasked[3:0];
wire C6T0_stb_full = &`TOP_DESIGN.sparc6.lsu.stb_ctl0.stb_state_vld[7:0];
wire C6T1_stb_full = &`TOP_DESIGN.sparc6.lsu.stb_ctl1.stb_state_vld[7:0];
wire C6T2_stb_full = &`TOP_DESIGN.sparc6.lsu.stb_ctl2.stb_state_vld[7:0];
wire C6T3_stb_full = &`TOP_DESIGN.sparc6.lsu.stb_ctl3.stb_state_vld[7:0];
wire [7:0] C6T0_stb_vld = `TOP_DESIGN.sparc6.lsu.stb_ctl0.stb_state_vld[7:0];
wire [7:0] C6T1_stb_vld = `TOP_DESIGN.sparc6.lsu.stb_ctl1.stb_state_vld[7:0];
wire [7:0] C6T2_stb_vld = `TOP_DESIGN.sparc6.lsu.stb_ctl2.stb_state_vld[7:0];
wire [7:0] C6T3_stb_vld = `TOP_DESIGN.sparc6.lsu.stb_ctl3.stb_state_vld[7:0];
wire [4:0] C6T0_stb_vld_sum = C6T0_stb_vld[0] + C6T0_stb_vld[1] + C6T0_stb_vld[2] + C6T0_stb_vld[3] +
C6T0_stb_vld[4] + C6T0_stb_vld[5] + C6T0_stb_vld[6] + C6T0_stb_vld[7] ;
wire [4:0] C6T1_stb_vld_sum = C6T1_stb_vld[0] + C6T1_stb_vld[1] + C6T1_stb_vld[2] + C6T1_stb_vld[3] +
C6T1_stb_vld[4] + C6T1_stb_vld[5] + C6T1_stb_vld[6] + C6T1_stb_vld[7] ;
wire [4:0] C6T2_stb_vld_sum = C6T2_stb_vld[0] + C6T2_stb_vld[1] + C6T2_stb_vld[2] + C6T2_stb_vld[3] +
C6T2_stb_vld[4] + C6T2_stb_vld[5] + C6T2_stb_vld[6] + C6T2_stb_vld[7] ;
wire [4:0] C6T3_stb_vld_sum = C6T3_stb_vld[0] + C6T3_stb_vld[1] + C6T3_stb_vld[2] + C6T3_stb_vld[3] +
C6T3_stb_vld[4] + C6T3_stb_vld[5] + C6T3_stb_vld[6] + C6T3_stb_vld[7] ;
reg [4:0] C6T0_stb_vld_sum_d1;
reg [4:0] C6T1_stb_vld_sum_d1;
reg [4:0] C6T2_stb_vld_sum_d1;
reg [4:0] C6T3_stb_vld_sum_d1;
wire C6T0_st_ack = &`TOP_DESIGN.sparc6.lsu.cpx_st_ack_tid0;
wire C6T1_st_ack = &`TOP_DESIGN.sparc6.lsu.cpx_st_ack_tid1;
wire C6T2_st_ack = &`TOP_DESIGN.sparc6.lsu.cpx_st_ack_tid2;
wire C6T3_st_ack = &`TOP_DESIGN.sparc6.lsu.cpx_st_ack_tid3;
wire C6T0_defr_trp_en = &`TOP_DESIGN.sparc6.lsu.excpctl.st_defr_trp_en0;
wire C6T1_defr_trp_en = &`TOP_DESIGN.sparc6.lsu.excpctl.st_defr_trp_en1;
wire C6T2_defr_trp_en = &`TOP_DESIGN.sparc6.lsu.excpctl.st_defr_trp_en2;
wire C6T3_defr_trp_en = &`TOP_DESIGN.sparc6.lsu.excpctl.st_defr_trp_en3;
reg C6T0_defr_trp_en_d1;
reg C6T1_defr_trp_en_d1;
reg C6T2_defr_trp_en_d1;
reg C6T3_defr_trp_en_d1;
integer C6T0_stb_drain_cnt;
integer C6T1_stb_drain_cnt;
integer C6T2_stb_drain_cnt;
integer C6T3_stb_drain_cnt;
// Hits in the store buffer
//-------------------------
wire spc6_inst_vld_w = `TOP_DESIGN.sparc6.ifu.fcl.inst_vld_w;
wire [1:0] spc6_sas_thrid_w = `TOP_DESIGN.sparc6.ifu.fcl.sas_thrid_w[1:0];
wire C6_st_ack_w = (spc6_sas_thrid_w == 2'b00) & C6T0_st_ack |
(spc6_sas_thrid_w == 2'b01) & C6T1_st_ack |
(spc6_sas_thrid_w == 2'b10) & C6T2_st_ack |
(spc6_sas_thrid_w == 2'b11) & C6T3_st_ack;
wire [7:0] spc6_stb_ld_full_raw = `TOP_DESIGN.sparc6.lsu.stb_ld_full_raw[7:0];
wire [7:0] spc6_stb_ld_partial_raw = `TOP_DESIGN.sparc6.lsu.stb_ld_partial_raw[7:0];
wire spc6_stb_cam_mhit = `TOP_DESIGN.sparc6.lsu.stb_cam_mhit;
wire spc6_stb_cam_hit = `TOP_DESIGN.sparc6.lsu.stb_cam_hit;
wire [3:0] spc6_lsu_way_hit = `TOP_DESIGN.sparc6.lsu.dctl.lsu_way_hit[3:0];
wire spc6_lsu_ifu_ldst_miss_w = `TOP_DESIGN.sparc6.lsu.lsu_ifu_ldst_miss_w;
wire spc6_ld_inst_vld_g = `TOP_DESIGN.sparc6.lsu.dctl.ld_inst_vld_g;
wire spc6_ldst_dbl_g = `TOP_DESIGN.sparc6.lsu.dctl.ldst_dbl_g;
wire spc6_quad_asi_g = `TOP_DESIGN.sparc6.lsu.dctl.quad_asi_g;
wire [1:0] spc6_ldst_sz_g = `TOP_DESIGN.sparc6.lsu.dctl.ldst_sz_g;
wire spc6_lsu_alt_space_g = `TOP_DESIGN.sparc6.lsu.dctl.lsu_alt_space_g;
wire spc6_mbar_inst0_g = `TOP_DESIGN.sparc6.lsu.dctl.mbar_inst0_g;
wire spc6_mbar_inst1_g = `TOP_DESIGN.sparc6.lsu.dctl.mbar_inst1_g;
wire spc6_mbar_inst2_g = `TOP_DESIGN.sparc6.lsu.dctl.mbar_inst2_g;
wire spc6_mbar_inst3_g = `TOP_DESIGN.sparc6.lsu.dctl.mbar_inst3_g;
wire spc6_flush_inst0_g = `TOP_DESIGN.sparc6.lsu.dctl.flush_inst0_g;
wire spc6_flush_inst1_g = `TOP_DESIGN.sparc6.lsu.dctl.flush_inst1_g;
wire spc6_flush_inst2_g = `TOP_DESIGN.sparc6.lsu.dctl.flush_inst2_g;
wire spc6_flush_inst3_g = `TOP_DESIGN.sparc6.lsu.dctl.flush_inst3_g;
wire spc6_intrpt_disp_asi0_g = `TOP_DESIGN.sparc6.lsu.dctl.intrpt_disp_asi_g & (spc6_sas_thrid_w == 2'b00);
wire spc6_intrpt_disp_asi1_g = `TOP_DESIGN.sparc6.lsu.dctl.intrpt_disp_asi_g & (spc6_sas_thrid_w == 2'b01);
wire spc6_intrpt_disp_asi2_g = `TOP_DESIGN.sparc6.lsu.dctl.intrpt_disp_asi_g & (spc6_sas_thrid_w == 2'b10);
wire spc6_intrpt_disp_asi3_g = `TOP_DESIGN.sparc6.lsu.dctl.intrpt_disp_asi_g & (spc6_sas_thrid_w == 2'b11);
wire spc6_st_inst_vld_g = `TOP_DESIGN.sparc6.lsu.dctl.st_inst_vld_g;
wire spc6_non_altspace_ldst_g = `TOP_DESIGN.sparc6.lsu.dctl.non_altspace_ldst_g;
wire spc6_dctl_flush_pipe_w = `TOP_DESIGN.sparc6.lsu.dctl.dctl_flush_pipe_w;
wire [3:0] spc6_no_spc_rmo_st = `TOP_DESIGN.sparc6.lsu.dctl.no_spc_rmo_st[3:0];
wire spc6_ldst_fp_e = `TOP_DESIGN.sparc6.lsu.ifu_lsu_ldst_fp_e;
wire [2:0] spc6_stb_rdptr = `TOP_DESIGN.sparc6.lsu.stb_rwctl.stb_rdptr_l;
wire spc6_ld_l2cache_req = `TOP_DESIGN.sparc6.lsu.qctl1.ld3_l2cache_rq |
`TOP_DESIGN.sparc6.lsu.qctl1.ld2_l2cache_rq |
`TOP_DESIGN.sparc6.lsu.qctl1.ld1_l2cache_rq |
`TOP_DESIGN.sparc6.lsu.qctl1.ld0_l2cache_rq;
wire [3:0] spc6_dcache_enable = {`TOP_DESIGN.sparc6.lsu.dctl.lsu_ctl_reg0[1],
`TOP_DESIGN.sparc6.lsu.dctl.lsu_ctl_reg1[1],
`TOP_DESIGN.sparc6.lsu.dctl.lsu_ctl_reg2[1],
`TOP_DESIGN.sparc6.lsu.dctl.lsu_ctl_reg3[1]};
wire [3:0] spc6_icache_enable = `TOP_DESIGN.sparc6.lsu.lsu_ifu_icache_en[3:0];
wire spc6_dc_direct_map = `TOP_DESIGN.sparc6.lsu.dc_direct_map;
wire spc6_lsu_ifu_direct_map_l1 = `TOP_DESIGN.sparc6.lsu.lsu_ifu_direct_map_l1;
always @(spc6_dcache_enable)
$display("%0d tso_mon: spc6_dcache_enable changed to %x", $time, spc6_dcache_enable);
always @(spc6_icache_enable)
$display("%0d tso_mon: spc6_icache_enable changed to %x", $time, spc6_icache_enable);
always @(spc6_dc_direct_map)
$display("%0d tso_mon: spc6_dc_direct_map changed to %x", $time, spc6_dc_direct_map);
always @(spc6_lsu_ifu_direct_map_l1)
$display("%0d tso_mon: spc6_lsu_ifu_direct_map_l1 changed to %x", $time, spc6_lsu_ifu_direct_map_l1);
reg spc6_dva_svld_e_d1;
reg spc6_dva_rvld_e_d1;
reg [10:4] spc6_dva_rd_addr_e_d1;
reg [4:0] spc6_dva_snp_addr_e_d1;
reg spc6_lsu_snp_after_rd;
reg spc6_lsu_rd_after_snp;
reg spc6_ldst_fp_m, spc6_ldst_fp_g;
integer spc6_multiple_hits;
reg spc6_skid_d1, spc6_skid_d2, spc6_skid_d3;
initial begin
spc6_skid_d1 = 0;
spc6_skid_d2 = 0;
spc6_skid_d3 = 0;
end
always @(posedge clk)
begin
spc6_skid_d1 <= (~spc6_ifu_lsu_inv_clear & spc6_dfq_rd_advance & spc6_dfq_int_type);
spc6_skid_d2 <= spc6_skid_d1 & ~spc6_ifu_lsu_inv_clear;
spc6_skid_d3 <= spc6_skid_d2 & ~spc6_ifu_lsu_inv_clear;
// The full tracking of this condition is complicated since after the interrupt is advanced
// there may be more invalidations to the IFQ.
// All we care about is that the invalidations BEFORE the interrupt are finished.
// I provided a command line argument to disable this check.
if(spc6_skid_d3 & enable_ifu_lsu_inv_clear)
finish_test("spc", "tso_mon: spc6_ifu_lsu_inv_clear should have been clear by now", 6);
spc6_dva_svld_e_d1 <= spc6_dva_svld_e;
spc6_dva_rvld_e_d1 <= spc6_dva_rvld_e;
spc6_dva_rd_addr_e_d1 <= spc6_dva_rd_addr_e;
spc6_dva_snp_addr_e_d1 <= spc6_dva_snp_addr_e;
if(spc6_dva_svld_e_d1 & spc6_dva_rvld_e & (spc6_dva_rd_addr_e_d1[10:6] == spc6_dva_snp_addr_e[4:0]))
spc6_lsu_rd_after_snp <= 1'b1;
else
spc6_lsu_rd_after_snp <= 1'b0;
if(spc6_dva_svld_e & spc6_dva_rvld_e_d1 & (spc6_dva_rd_addr_e[10:6] == spc6_dva_snp_addr_e_d1[4:0]))
spc6_lsu_snp_after_rd <= 1'b1;
else
spc6_lsu_snp_after_rd <= 1'b0;
spc6_ldst_fp_m <= spc6_ldst_fp_e;
spc6_ldst_fp_g <= spc6_ldst_fp_m;
if(spc6_stb_data_rptr_vld & spc6_stb_data_wptr_vld & ~spc6_stbrwctl_flush_pipe_w &
(spc6_stb_data_rd_ptr == spc6_stb_data_wr_ptr) & spc6_lsu_st_pcx_rq_pick)
begin
finish_test("spc", "tso_mon: LSU stb data write and read in the same cycle", 6);
end
spc6_multiple_hits = (spc6_lsu_way_hit[3] + spc6_lsu_way_hit[2] + spc6_lsu_way_hit[1] + spc6_lsu_way_hit[0]);
if(!spc6_lsu_ifu_ldst_miss_w && (spc6_multiple_hits >1) && spc6_inst_vld_w && !spc6_dctl_flush_pipe_w && !spc6_lsu_dc_tag_pe_g_unmasked_or)
finish_test("spc", "tso_mon: LSU multiple hits ", 6);
end
wire spc6_ld_dbl = spc6_ld_inst_vld_g & spc6_ldst_dbl_g & ~spc6_quad_asi_g;
wire spc6_ld_quad = spc6_ld_inst_vld_g & spc6_ldst_dbl_g & spc6_quad_asi_g;
wire spc6_ld_other = spc6_ld_inst_vld_g & ~spc6_ldst_dbl_g;
wire spc6_ld_dbl_fp = spc6_ld_dbl & spc6_ldst_fp_g;
wire spc6_ld_other_fp = spc6_ld_other & spc6_ldst_fp_g;
wire spc6_ld_dbl_int = spc6_ld_dbl & ~spc6_ldst_fp_g;
wire spc6_ld_quad_int = spc6_ld_quad & ~spc6_ldst_fp_g;
wire spc6_ld_other_int= spc6_ld_other & ~spc6_ldst_fp_g;
wire spc6_ld_bypassok_hit = |spc6_stb_ld_full_raw[7:0] & ~spc6_stb_cam_mhit;
wire spc6_ld_partial_hit = |spc6_stb_ld_partial_raw[7:0] & ~spc6_stb_cam_mhit;
wire spc6_ld_multiple_hit = spc6_stb_cam_mhit;
wire spc6_any_lsu_way_hit = |spc6_lsu_way_hit;
wire [7:0] spc6_stb_rdptr_decoded = (spc6_stb_rdptr ==3'b000) ? 8'b00000001 :
(spc6_stb_rdptr ==3'b001) ? 8'b00000010 :
(spc6_stb_rdptr ==3'b010) ? 8'b00000100 :
(spc6_stb_rdptr ==3'b011) ? 8'b00001000 :
(spc6_stb_rdptr ==3'b100) ? 8'b00010000 :
(spc6_stb_rdptr ==3'b101) ? 8'b00100000 :
(spc6_stb_rdptr ==3'b110) ? 8'b01000000 :
(spc6_stb_rdptr ==3'b111) ? 8'b10000000 : 8'h00;
wire spc6_stb_top_hit = |(spc6_stb_rdptr_decoded & (spc6_stb_ld_full_raw | spc6_stb_ld_partial_raw));
//---------------------------------------------------------------------
// ld_type[4:0] hit_type[2:0], cache_hit, hit_top
// this is passed to the coverage monitor.
//---------------------------------------------------------------------
wire [10:0] spc6_stb_ld_hit_info =
{spc6_ld_dbl_fp, spc6_ld_other_fp,
spc6_ld_dbl_int, spc6_ld_quad_int, spc6_ld_other_int,
spc6_ld_bypassok_hit, spc6_ld_partial_hit, spc6_ld_multiple_hit,
spc6_any_lsu_way_hit,
spc6_stb_top_hit, C6_st_ack_w};
reg spc6_mbar0_active;
reg spc6_mbar1_active;
reg spc6_mbar2_active;
reg spc6_mbar3_active;
reg spc6_flush0_active;
reg spc6_flush1_active;
reg spc6_flush2_active;
reg spc6_flush3_active;
reg spc6_intr0_active;
reg spc6_intr1_active;
reg spc6_intr2_active;
reg spc6_intr3_active;
always @(negedge clk)
begin
if(~rst_l)
begin
spc6_mbar0_active <= 1'b0;
spc6_mbar1_active <= 1'b0;
spc6_mbar2_active <= 1'b0;
spc6_mbar3_active <= 1'b0;
spc6_flush0_active <= 1'b0;
spc6_flush1_active <= 1'b0;
spc6_flush2_active <= 1'b0;
spc6_flush3_active <= 1'b0;
spc6_intr0_active <= 1'b0;
spc6_intr1_active <= 1'b0;
spc6_intr2_active <= 1'b0;
spc6_intr3_active <= 1'b0;
end
else
begin
if(spc6_mbar_inst0_g & ~spc6_dctl_flush_pipe_w & (C6T0_stb_ne|~spc6_no_spc_rmo_st[0]))
spc6_mbar0_active <= 1'b1;
else if(~C6T0_stb_ne & spc6_no_spc_rmo_st[0])
spc6_mbar0_active <= 1'b0;
if(spc6_mbar_inst1_g & ~ spc6_dctl_flush_pipe_w & (C6T1_stb_ne|~spc6_no_spc_rmo_st[1]))
spc6_mbar1_active <= 1'b1;
else if(~C6T1_stb_ne & spc6_no_spc_rmo_st[1])
spc6_mbar1_active <= 1'b0;
if(spc6_mbar_inst2_g & ~ spc6_dctl_flush_pipe_w & (C6T2_stb_ne|~spc6_no_spc_rmo_st[2]))
spc6_mbar2_active <= 1'b1;
else if(~C6T2_stb_ne & spc6_no_spc_rmo_st[2])
spc6_mbar2_active <= 1'b0;
if(spc6_mbar_inst3_g & ~ spc6_dctl_flush_pipe_w & (C6T3_stb_ne|~spc6_no_spc_rmo_st[3]))
spc6_mbar3_active <= 1'b1;
else if(~C6T3_stb_ne & spc6_no_spc_rmo_st[3])
spc6_mbar3_active <= 1'b0;
if(spc6_flush_inst0_g & ~spc6_dctl_flush_pipe_w & C6T0_stb_ne) spc6_flush0_active <= 1'b1;
else if(~C6T0_stb_ne) spc6_flush0_active <= 1'b0;
if(spc6_flush_inst1_g & ~spc6_dctl_flush_pipe_w & C6T1_stb_ne) spc6_flush1_active <= 1'b1;
else if(~C6T1_stb_ne) spc6_flush1_active <= 1'b0;
if(spc6_flush_inst2_g & ~spc6_dctl_flush_pipe_w & C6T2_stb_ne) spc6_flush2_active <= 1'b1;
else if(~C6T2_stb_ne) spc6_flush2_active <= 1'b0;
if(spc6_flush_inst3_g & ~spc6_dctl_flush_pipe_w & C6T3_stb_ne) spc6_flush3_active <= 1'b1;
else if(~C6T3_stb_ne) spc6_flush3_active <= 1'b0;
if(spc6_intrpt_disp_asi0_g & spc6_st_inst_vld_g & ~spc6_non_altspace_ldst_g & ~spc6_dctl_flush_pipe_w & C6T0_stb_ne)
spc6_intr0_active <= 1'b1;
else if(~C6T0_stb_ne)
spc6_intr0_active <= 1'b0;
if(spc6_intrpt_disp_asi1_g & spc6_st_inst_vld_g & ~spc6_non_altspace_ldst_g & ~spc6_dctl_flush_pipe_w & C6T1_stb_ne)
spc6_intr1_active <= 1'b1;
else if(~C6T1_stb_ne)
spc6_intr1_active <= 1'b0;
if(spc6_intrpt_disp_asi2_g & spc6_st_inst_vld_g & ~spc6_non_altspace_ldst_g & ~spc6_dctl_flush_pipe_w & C6T2_stb_ne)
spc6_intr2_active <= 1'b1;
else if(~C6T2_stb_ne)
spc6_intr2_active <= 1'b0;
if(spc6_intrpt_disp_asi3_g & spc6_st_inst_vld_g & ~spc6_non_altspace_ldst_g & ~spc6_dctl_flush_pipe_w & C6T3_stb_ne)
spc6_intr3_active <= 1'b1;
else if(~C6T3_stb_ne)
spc6_intr3_active <= 1'b0;
end
if(spc6_mbar0_active & spc6_inst_vld_w & spc6_sas_thrid_w[1:0] == 2'b00)
finish_test("spc", "membar violation thread 0", 6);
if(spc6_mbar1_active & spc6_inst_vld_w & spc6_sas_thrid_w[1:0] == 2'b01)
finish_test("spc", "membar violation thread 1", 6);
if(spc6_mbar2_active & spc6_inst_vld_w & spc6_sas_thrid_w[1:0] == 2'b10)
finish_test("spc", "membar violation thread 2", 6);
if(spc6_mbar3_active & spc6_inst_vld_w & spc6_sas_thrid_w[1:0] == 2'b11)
finish_test("spc", "membar violation thread 3", 6);
if(spc6_flush0_active & spc6_inst_vld_w & spc6_sas_thrid_w[1:0] == 2'b00)
finish_test("spc", "flush violation thread 0", 6);
if(spc6_flush1_active & spc6_inst_vld_w & spc6_sas_thrid_w[1:0] == 2'b01)
finish_test("spc", "flush violation thread 1", 6);
if(spc6_flush2_active & spc6_inst_vld_w & spc6_sas_thrid_w[1:0] == 2'b10)
finish_test("spc", "flush violation thread 2", 6);
if(spc6_flush3_active & spc6_inst_vld_w & spc6_sas_thrid_w[1:0] == 2'b11)
finish_test("spc", "flush violation thread 3", 6);
if(spc6_intr0_active & spc6_inst_vld_w & spc6_sas_thrid_w[1:0] == 2'b00)
finish_test("spc", "intr violation thread 0", 6);
if(spc6_intr1_active & spc6_inst_vld_w & spc6_sas_thrid_w[1:0] == 2'b01)
finish_test("spc", "intr violation thread 1", 6);
if(spc6_intr2_active & spc6_inst_vld_w & spc6_sas_thrid_w[1:0] == 2'b10)
finish_test("spc", "intr violation thread 2", 6);
if(spc6_intr3_active & spc6_inst_vld_w & spc6_sas_thrid_w[1:0] == 2'b11)
finish_test("spc", "intr violation thread 3", 6);
if(~rst_l | ~C6T0_stb_full | sctag_pcx_stall_pq) C6T0_stb_drain_cnt = 0;
else C6T0_stb_drain_cnt = C6T0_stb_drain_cnt + 1;
if(C6T0_stb_drain_cnt > stb_drain_to_max)
finish_test("spc", "stb 0 is not draining", 6);
if(~rst_l | ~C6T1_stb_full | sctag_pcx_stall_pq) C6T1_stb_drain_cnt = 0;
else C6T1_stb_drain_cnt = C6T1_stb_drain_cnt + 1;
if(C6T1_stb_drain_cnt > stb_drain_to_max)
finish_test("spc", "stb 1 is not draining", 6);
if(~rst_l | ~C6T2_stb_full | sctag_pcx_stall_pq) C6T2_stb_drain_cnt = 0;
else C6T2_stb_drain_cnt = C6T2_stb_drain_cnt + 1;
if(C6T2_stb_drain_cnt > stb_drain_to_max)
finish_test("spc", "stb 2 is not draining", 6);
if(~rst_l | ~C6T3_stb_full | sctag_pcx_stall_pq) C6T3_stb_drain_cnt = 0;
else C6T3_stb_drain_cnt = C6T3_stb_drain_cnt + 1;
if(C6T3_stb_drain_cnt > stb_drain_to_max)
finish_test("spc", "stb 3 is not draining", 6);
C6T0_stb_vld_sum_d1 <= C6T0_stb_vld_sum;
C6T1_stb_vld_sum_d1 <= C6T1_stb_vld_sum;
C6T2_stb_vld_sum_d1 <= C6T2_stb_vld_sum;
C6T3_stb_vld_sum_d1 <= C6T3_stb_vld_sum;
C6T0_defr_trp_en_d1 <= C6T0_defr_trp_en;
C6T1_defr_trp_en_d1 <= C6T1_defr_trp_en;
C6T2_defr_trp_en_d1 <= C6T2_defr_trp_en;
C6T3_defr_trp_en_d1 <= C6T3_defr_trp_en;
if(rst_l & C6T0_defr_trp_en_d1 & (C6T0_stb_vld_sum_d1 < C6T0_stb_vld_sum))
finish_test("spc", "tso_mon: deferred trap problems for store T0", 6);
if(rst_l & C6T1_defr_trp_en_d1 & (C6T1_stb_vld_sum_d1 < C6T1_stb_vld_sum))
finish_test("spc", "tso_mon: deferred trap problems for store T1", 6);
if(rst_l & C6T2_defr_trp_en_d1 & (C6T2_stb_vld_sum_d1 < C6T2_stb_vld_sum))
finish_test("spc", "tso_mon: deferred trap problems for store T2", 6);
if(rst_l & C6T3_defr_trp_en_d1 & (C6T3_stb_vld_sum_d1 < C6T3_stb_vld_sum))
finish_test("spc", "tso_mon: deferred trap problems for store T3", 6);
end
`endif // ifdef RTL_SPARC6
`ifdef RTL_SPARC7
wire C7T0_stb_ne = |`TOP_DESIGN.sparc7.lsu.stb_ctl0.stb_state_vld[7:0];
wire C7T1_stb_ne = |`TOP_DESIGN.sparc7.lsu.stb_ctl1.stb_state_vld[7:0];
wire C7T2_stb_ne = |`TOP_DESIGN.sparc7.lsu.stb_ctl2.stb_state_vld[7:0];
wire C7T3_stb_ne = |`TOP_DESIGN.sparc7.lsu.stb_ctl3.stb_state_vld[7:0];
wire C7T0_stb_nced = |( `TOP_DESIGN.sparc7.lsu.stb_ctl0.stb_state_vld[7:0] &
~`TOP_DESIGN.sparc7.lsu.stb_ctl0.stb_state_ced[7:0]);
wire C7T1_stb_nced = |( `TOP_DESIGN.sparc7.lsu.stb_ctl1.stb_state_vld[7:0] &
~`TOP_DESIGN.sparc7.lsu.stb_ctl1.stb_state_ced[7:0]);
wire C7T2_stb_nced = |( `TOP_DESIGN.sparc7.lsu.stb_ctl2.stb_state_vld[7:0] &
~`TOP_DESIGN.sparc7.lsu.stb_ctl2.stb_state_ced[7:0]);
wire C7T3_stb_nced = |( `TOP_DESIGN.sparc7.lsu.stb_ctl3.stb_state_vld[7:0] &
~`TOP_DESIGN.sparc7.lsu.stb_ctl3.stb_state_ced[7:0]);
`else
wire C7T0_stb_ne = 1'b0;
wire C7T1_stb_ne = 1'b0;
wire C7T2_stb_ne = 1'b0;
wire C7T3_stb_ne = 1'b0;
wire C7T0_stb_nced = 1'b0;
wire C7T1_stb_nced = 1'b0;
wire C7T2_stb_nced = 1'b0;
wire C7T3_stb_nced = 1'b0;
`endif // ifdef RTL_SPARC7
`ifdef RTL_SPARC7
wire spc7_lsu_ifill_pkt_vld = `TOP_DESIGN.sparc7.lsu.qctl2.lsu_ifill_pkt_vld;
wire spc7_dfq_rd_advance = `TOP_DESIGN.sparc7.lsu.qctl2.dfq_rd_advance;
wire spc7_dfq_int_type = `TOP_DESIGN.sparc7.lsu.qctl2.dfq_int_type;
wire spc7_ifu_lsu_inv_clear = `TOP_DESIGN.sparc7.lsu.qctl2.ifu_lsu_inv_clear;
wire spc7_dva_svld_e = `TOP_DESIGN.sparc7.lsu.qctl2.dva_svld_e;
wire spc7_dva_rvld_e = `TOP_DESIGN.sparc7.lsu.dva.rd_en;
wire [10:4] spc7_dva_rd_addr_e = `TOP_DESIGN.sparc7.lsu.dva.rd_adr1[6:0];
wire [4:0] spc7_dva_snp_addr_e = `TOP_DESIGN.sparc7.lsu.qctl2.dva_snp_addr_e[4:0];
wire [4:0] spc7_stb_data_rd_ptr = `TOP_DESIGN.sparc7.lsu.stb_data_rd_ptr[4:0];
wire [4:0] spc7_stb_data_wr_ptr = `TOP_DESIGN.sparc7.lsu.stb_data_wr_ptr[4:0];
wire spc7_stb_data_wptr_vld = `TOP_DESIGN.sparc7.lsu.stb_data_wptr_vld;
wire spc7_stb_data_rptr_vld = `TOP_DESIGN.sparc7.lsu.stb_data_rptr_vld;
wire spc7_stbrwctl_flush_pipe_w = `TOP_DESIGN.sparc7.lsu.stb_rwctl.lsu_stbrwctl_flush_pipe_w;
wire spc7_lsu_st_pcx_rq_pick = |`TOP_DESIGN.sparc7.lsu.stb_rwctl.lsu_st_pcx_rq_pick[3:0];
wire [3:0] spc7_lsu_rd_dtag_parity_g = `TOP_DESIGN.sparc7.lsu.dctl.lsu_rd_dtag_parity_g[3:0];
wire [3:0] spc7_dva_vld_g = `TOP_DESIGN.sparc7.lsu.dctl.dva_vld_g[3:0];
wire [3:0] spc7_lsu_dc_tag_pe_g_unmasked = spc7_lsu_rd_dtag_parity_g[3:0] & spc7_dva_vld_g[3:0];
wire spc7_lsu_dc_tag_pe_g_unmasked_or = |spc7_lsu_dc_tag_pe_g_unmasked[3:0];
wire C7T0_stb_full = &`TOP_DESIGN.sparc7.lsu.stb_ctl0.stb_state_vld[7:0];
wire C7T1_stb_full = &`TOP_DESIGN.sparc7.lsu.stb_ctl1.stb_state_vld[7:0];
wire C7T2_stb_full = &`TOP_DESIGN.sparc7.lsu.stb_ctl2.stb_state_vld[7:0];
wire C7T3_stb_full = &`TOP_DESIGN.sparc7.lsu.stb_ctl3.stb_state_vld[7:0];
wire [7:0] C7T0_stb_vld = `TOP_DESIGN.sparc7.lsu.stb_ctl0.stb_state_vld[7:0];
wire [7:0] C7T1_stb_vld = `TOP_DESIGN.sparc7.lsu.stb_ctl1.stb_state_vld[7:0];
wire [7:0] C7T2_stb_vld = `TOP_DESIGN.sparc7.lsu.stb_ctl2.stb_state_vld[7:0];
wire [7:0] C7T3_stb_vld = `TOP_DESIGN.sparc7.lsu.stb_ctl3.stb_state_vld[7:0];
wire [4:0] C7T0_stb_vld_sum = C7T0_stb_vld[0] + C7T0_stb_vld[1] + C7T0_stb_vld[2] + C7T0_stb_vld[3] +
C7T0_stb_vld[4] + C7T0_stb_vld[5] + C7T0_stb_vld[6] + C7T0_stb_vld[7] ;
wire [4:0] C7T1_stb_vld_sum = C7T1_stb_vld[0] + C7T1_stb_vld[1] + C7T1_stb_vld[2] + C7T1_stb_vld[3] +
C7T1_stb_vld[4] + C7T1_stb_vld[5] + C7T1_stb_vld[6] + C7T1_stb_vld[7] ;
wire [4:0] C7T2_stb_vld_sum = C7T2_stb_vld[0] + C7T2_stb_vld[1] + C7T2_stb_vld[2] + C7T2_stb_vld[3] +
C7T2_stb_vld[4] + C7T2_stb_vld[5] + C7T2_stb_vld[6] + C7T2_stb_vld[7] ;
wire [4:0] C7T3_stb_vld_sum = C7T3_stb_vld[0] + C7T3_stb_vld[1] + C7T3_stb_vld[2] + C7T3_stb_vld[3] +
C7T3_stb_vld[4] + C7T3_stb_vld[5] + C7T3_stb_vld[6] + C7T3_stb_vld[7] ;
reg [4:0] C7T0_stb_vld_sum_d1;
reg [4:0] C7T1_stb_vld_sum_d1;
reg [4:0] C7T2_stb_vld_sum_d1;
reg [4:0] C7T3_stb_vld_sum_d1;
wire C7T0_st_ack = &`TOP_DESIGN.sparc7.lsu.cpx_st_ack_tid0;
wire C7T1_st_ack = &`TOP_DESIGN.sparc7.lsu.cpx_st_ack_tid1;
wire C7T2_st_ack = &`TOP_DESIGN.sparc7.lsu.cpx_st_ack_tid2;
wire C7T3_st_ack = &`TOP_DESIGN.sparc7.lsu.cpx_st_ack_tid3;
wire C7T0_defr_trp_en = &`TOP_DESIGN.sparc7.lsu.excpctl.st_defr_trp_en0;
wire C7T1_defr_trp_en = &`TOP_DESIGN.sparc7.lsu.excpctl.st_defr_trp_en1;
wire C7T2_defr_trp_en = &`TOP_DESIGN.sparc7.lsu.excpctl.st_defr_trp_en2;
wire C7T3_defr_trp_en = &`TOP_DESIGN.sparc7.lsu.excpctl.st_defr_trp_en3;
reg C7T0_defr_trp_en_d1;
reg C7T1_defr_trp_en_d1;
reg C7T2_defr_trp_en_d1;
reg C7T3_defr_trp_en_d1;
integer C7T0_stb_drain_cnt;
integer C7T1_stb_drain_cnt;
integer C7T2_stb_drain_cnt;
integer C7T3_stb_drain_cnt;
// Hits in the store buffer
//-------------------------
wire spc7_inst_vld_w = `TOP_DESIGN.sparc7.ifu.fcl.inst_vld_w;
wire [1:0] spc7_sas_thrid_w = `TOP_DESIGN.sparc7.ifu.fcl.sas_thrid_w[1:0];
wire C7_st_ack_w = (spc7_sas_thrid_w == 2'b00) & C7T0_st_ack |
(spc7_sas_thrid_w == 2'b01) & C7T1_st_ack |
(spc7_sas_thrid_w == 2'b10) & C7T2_st_ack |
(spc7_sas_thrid_w == 2'b11) & C7T3_st_ack;
wire [7:0] spc7_stb_ld_full_raw = `TOP_DESIGN.sparc7.lsu.stb_ld_full_raw[7:0];
wire [7:0] spc7_stb_ld_partial_raw = `TOP_DESIGN.sparc7.lsu.stb_ld_partial_raw[7:0];
wire spc7_stb_cam_mhit = `TOP_DESIGN.sparc7.lsu.stb_cam_mhit;
wire spc7_stb_cam_hit = `TOP_DESIGN.sparc7.lsu.stb_cam_hit;
wire [3:0] spc7_lsu_way_hit = `TOP_DESIGN.sparc7.lsu.dctl.lsu_way_hit[3:0];
wire spc7_lsu_ifu_ldst_miss_w = `TOP_DESIGN.sparc7.lsu.lsu_ifu_ldst_miss_w;
wire spc7_ld_inst_vld_g = `TOP_DESIGN.sparc7.lsu.dctl.ld_inst_vld_g;
wire spc7_ldst_dbl_g = `TOP_DESIGN.sparc7.lsu.dctl.ldst_dbl_g;
wire spc7_quad_asi_g = `TOP_DESIGN.sparc7.lsu.dctl.quad_asi_g;
wire [1:0] spc7_ldst_sz_g = `TOP_DESIGN.sparc7.lsu.dctl.ldst_sz_g;
wire spc7_lsu_alt_space_g = `TOP_DESIGN.sparc7.lsu.dctl.lsu_alt_space_g;
wire spc7_mbar_inst0_g = `TOP_DESIGN.sparc7.lsu.dctl.mbar_inst0_g;
wire spc7_mbar_inst1_g = `TOP_DESIGN.sparc7.lsu.dctl.mbar_inst1_g;
wire spc7_mbar_inst2_g = `TOP_DESIGN.sparc7.lsu.dctl.mbar_inst2_g;
wire spc7_mbar_inst3_g = `TOP_DESIGN.sparc7.lsu.dctl.mbar_inst3_g;
wire spc7_flush_inst0_g = `TOP_DESIGN.sparc7.lsu.dctl.flush_inst0_g;
wire spc7_flush_inst1_g = `TOP_DESIGN.sparc7.lsu.dctl.flush_inst1_g;
wire spc7_flush_inst2_g = `TOP_DESIGN.sparc7.lsu.dctl.flush_inst2_g;
wire spc7_flush_inst3_g = `TOP_DESIGN.sparc7.lsu.dctl.flush_inst3_g;
wire spc7_intrpt_disp_asi0_g = `TOP_DESIGN.sparc7.lsu.dctl.intrpt_disp_asi_g & (spc7_sas_thrid_w == 2'b00);
wire spc7_intrpt_disp_asi1_g = `TOP_DESIGN.sparc7.lsu.dctl.intrpt_disp_asi_g & (spc7_sas_thrid_w == 2'b01);
wire spc7_intrpt_disp_asi2_g = `TOP_DESIGN.sparc7.lsu.dctl.intrpt_disp_asi_g & (spc7_sas_thrid_w == 2'b10);
wire spc7_intrpt_disp_asi3_g = `TOP_DESIGN.sparc7.lsu.dctl.intrpt_disp_asi_g & (spc7_sas_thrid_w == 2'b11);
wire spc7_st_inst_vld_g = `TOP_DESIGN.sparc7.lsu.dctl.st_inst_vld_g;
wire spc7_non_altspace_ldst_g = `TOP_DESIGN.sparc7.lsu.dctl.non_altspace_ldst_g;
wire spc7_dctl_flush_pipe_w = `TOP_DESIGN.sparc7.lsu.dctl.dctl_flush_pipe_w;
wire [3:0] spc7_no_spc_rmo_st = `TOP_DESIGN.sparc7.lsu.dctl.no_spc_rmo_st[3:0];
wire spc7_ldst_fp_e = `TOP_DESIGN.sparc7.lsu.ifu_lsu_ldst_fp_e;
wire [2:0] spc7_stb_rdptr = `TOP_DESIGN.sparc7.lsu.stb_rwctl.stb_rdptr_l;
wire spc7_ld_l2cache_req = `TOP_DESIGN.sparc7.lsu.qctl1.ld3_l2cache_rq |
`TOP_DESIGN.sparc7.lsu.qctl1.ld2_l2cache_rq |
`TOP_DESIGN.sparc7.lsu.qctl1.ld1_l2cache_rq |
`TOP_DESIGN.sparc7.lsu.qctl1.ld0_l2cache_rq;
wire [3:0] spc7_dcache_enable = {`TOP_DESIGN.sparc7.lsu.dctl.lsu_ctl_reg0[1],
`TOP_DESIGN.sparc7.lsu.dctl.lsu_ctl_reg1[1],
`TOP_DESIGN.sparc7.lsu.dctl.lsu_ctl_reg2[1],
`TOP_DESIGN.sparc7.lsu.dctl.lsu_ctl_reg3[1]};
wire [3:0] spc7_icache_enable = `TOP_DESIGN.sparc7.lsu.lsu_ifu_icache_en[3:0];
wire spc7_dc_direct_map = `TOP_DESIGN.sparc7.lsu.dc_direct_map;
wire spc7_lsu_ifu_direct_map_l1 = `TOP_DESIGN.sparc7.lsu.lsu_ifu_direct_map_l1;
always @(spc7_dcache_enable)
$display("%0d tso_mon: spc7_dcache_enable changed to %x", $time, spc7_dcache_enable);
always @(spc7_icache_enable)
$display("%0d tso_mon: spc7_icache_enable changed to %x", $time, spc7_icache_enable);
always @(spc7_dc_direct_map)
$display("%0d tso_mon: spc7_dc_direct_map changed to %x", $time, spc7_dc_direct_map);
always @(spc7_lsu_ifu_direct_map_l1)
$display("%0d tso_mon: spc7_lsu_ifu_direct_map_l1 changed to %x", $time, spc7_lsu_ifu_direct_map_l1);
reg spc7_dva_svld_e_d1;
reg spc7_dva_rvld_e_d1;
reg [10:4] spc7_dva_rd_addr_e_d1;
reg [4:0] spc7_dva_snp_addr_e_d1;
reg spc7_lsu_snp_after_rd;
reg spc7_lsu_rd_after_snp;
reg spc7_ldst_fp_m, spc7_ldst_fp_g;
integer spc7_multiple_hits;
reg spc7_skid_d1, spc7_skid_d2, spc7_skid_d3;
initial begin
spc7_skid_d1 = 0;
spc7_skid_d2 = 0;
spc7_skid_d3 = 0;
end
always @(posedge clk)
begin
spc7_skid_d1 <= (~spc7_ifu_lsu_inv_clear & spc7_dfq_rd_advance & spc7_dfq_int_type);
spc7_skid_d2 <= spc7_skid_d1 & ~spc7_ifu_lsu_inv_clear;
spc7_skid_d3 <= spc7_skid_d2 & ~spc7_ifu_lsu_inv_clear;
// The full tracking of this condition is complicated since after the interrupt is advanced
// there may be more invalidations to the IFQ.
// All we care about is that the invalidations BEFORE the interrupt are finished.
// I provided a command line argument to disable this check.
if(spc7_skid_d3 & enable_ifu_lsu_inv_clear)
finish_test("spc", "tso_mon: spc7_ifu_lsu_inv_clear should have been clear by now", 7);
spc7_dva_svld_e_d1 <= spc7_dva_svld_e;
spc7_dva_rvld_e_d1 <= spc7_dva_rvld_e;
spc7_dva_rd_addr_e_d1 <= spc7_dva_rd_addr_e;
spc7_dva_snp_addr_e_d1 <= spc7_dva_snp_addr_e;
if(spc7_dva_svld_e_d1 & spc7_dva_rvld_e & (spc7_dva_rd_addr_e_d1[10:6] == spc7_dva_snp_addr_e[4:0]))
spc7_lsu_rd_after_snp <= 1'b1;
else
spc7_lsu_rd_after_snp <= 1'b0;
if(spc7_dva_svld_e & spc7_dva_rvld_e_d1 & (spc7_dva_rd_addr_e[10:6] == spc7_dva_snp_addr_e_d1[4:0]))
spc7_lsu_snp_after_rd <= 1'b1;
else
spc7_lsu_snp_after_rd <= 1'b0;
spc7_ldst_fp_m <= spc7_ldst_fp_e;
spc7_ldst_fp_g <= spc7_ldst_fp_m;
if(spc7_stb_data_rptr_vld & spc7_stb_data_wptr_vld & ~spc7_stbrwctl_flush_pipe_w &
(spc7_stb_data_rd_ptr == spc7_stb_data_wr_ptr) & spc7_lsu_st_pcx_rq_pick)
begin
finish_test("spc", "tso_mon: LSU stb data write and read in the same cycle", 7);
end
spc7_multiple_hits = (spc7_lsu_way_hit[3] + spc7_lsu_way_hit[2] + spc7_lsu_way_hit[1] + spc7_lsu_way_hit[0]);
if(!spc7_lsu_ifu_ldst_miss_w && (spc7_multiple_hits >1) && spc7_inst_vld_w && !spc7_dctl_flush_pipe_w && !spc7_lsu_dc_tag_pe_g_unmasked_or)
finish_test("spc", "tso_mon: LSU multiple hits ", 7);
end
wire spc7_ld_dbl = spc7_ld_inst_vld_g & spc7_ldst_dbl_g & ~spc7_quad_asi_g;
wire spc7_ld_quad = spc7_ld_inst_vld_g & spc7_ldst_dbl_g & spc7_quad_asi_g;
wire spc7_ld_other = spc7_ld_inst_vld_g & ~spc7_ldst_dbl_g;
wire spc7_ld_dbl_fp = spc7_ld_dbl & spc7_ldst_fp_g;
wire spc7_ld_other_fp = spc7_ld_other & spc7_ldst_fp_g;
wire spc7_ld_dbl_int = spc7_ld_dbl & ~spc7_ldst_fp_g;
wire spc7_ld_quad_int = spc7_ld_quad & ~spc7_ldst_fp_g;
wire spc7_ld_other_int= spc7_ld_other & ~spc7_ldst_fp_g;
wire spc7_ld_bypassok_hit = |spc7_stb_ld_full_raw[7:0] & ~spc7_stb_cam_mhit;
wire spc7_ld_partial_hit = |spc7_stb_ld_partial_raw[7:0] & ~spc7_stb_cam_mhit;
wire spc7_ld_multiple_hit = spc7_stb_cam_mhit;
wire spc7_any_lsu_way_hit = |spc7_lsu_way_hit;
wire [7:0] spc7_stb_rdptr_decoded = (spc7_stb_rdptr ==3'b000) ? 8'b00000001 :
(spc7_stb_rdptr ==3'b001) ? 8'b00000010 :
(spc7_stb_rdptr ==3'b010) ? 8'b00000100 :
(spc7_stb_rdptr ==3'b011) ? 8'b00001000 :
(spc7_stb_rdptr ==3'b100) ? 8'b00010000 :
(spc7_stb_rdptr ==3'b101) ? 8'b00100000 :
(spc7_stb_rdptr ==3'b110) ? 8'b01000000 :
(spc7_stb_rdptr ==3'b111) ? 8'b10000000 : 8'h00;
wire spc7_stb_top_hit = |(spc7_stb_rdptr_decoded & (spc7_stb_ld_full_raw | spc7_stb_ld_partial_raw));
//---------------------------------------------------------------------
// ld_type[4:0] hit_type[2:0], cache_hit, hit_top
// this is passed to the coverage monitor.
//---------------------------------------------------------------------
wire [10:0] spc7_stb_ld_hit_info =
{spc7_ld_dbl_fp, spc7_ld_other_fp,
spc7_ld_dbl_int, spc7_ld_quad_int, spc7_ld_other_int,
spc7_ld_bypassok_hit, spc7_ld_partial_hit, spc7_ld_multiple_hit,
spc7_any_lsu_way_hit,
spc7_stb_top_hit, C7_st_ack_w};
reg spc7_mbar0_active;
reg spc7_mbar1_active;
reg spc7_mbar2_active;
reg spc7_mbar3_active;
reg spc7_flush0_active;
reg spc7_flush1_active;
reg spc7_flush2_active;
reg spc7_flush3_active;
reg spc7_intr0_active;
reg spc7_intr1_active;
reg spc7_intr2_active;
reg spc7_intr3_active;
always @(negedge clk)
begin
if(~rst_l)
begin
spc7_mbar0_active <= 1'b0;
spc7_mbar1_active <= 1'b0;
spc7_mbar2_active <= 1'b0;
spc7_mbar3_active <= 1'b0;
spc7_flush0_active <= 1'b0;
spc7_flush1_active <= 1'b0;
spc7_flush2_active <= 1'b0;
spc7_flush3_active <= 1'b0;
spc7_intr0_active <= 1'b0;
spc7_intr1_active <= 1'b0;
spc7_intr2_active <= 1'b0;
spc7_intr3_active <= 1'b0;
end
else
begin
if(spc7_mbar_inst0_g & ~spc7_dctl_flush_pipe_w & (C7T0_stb_ne|~spc7_no_spc_rmo_st[0]))
spc7_mbar0_active <= 1'b1;
else if(~C7T0_stb_ne & spc7_no_spc_rmo_st[0])
spc7_mbar0_active <= 1'b0;
if(spc7_mbar_inst1_g & ~ spc7_dctl_flush_pipe_w & (C7T1_stb_ne|~spc7_no_spc_rmo_st[1]))
spc7_mbar1_active <= 1'b1;
else if(~C7T1_stb_ne & spc7_no_spc_rmo_st[1])
spc7_mbar1_active <= 1'b0;
if(spc7_mbar_inst2_g & ~ spc7_dctl_flush_pipe_w & (C7T2_stb_ne|~spc7_no_spc_rmo_st[2]))
spc7_mbar2_active <= 1'b1;
else if(~C7T2_stb_ne & spc7_no_spc_rmo_st[2])
spc7_mbar2_active <= 1'b0;
if(spc7_mbar_inst3_g & ~ spc7_dctl_flush_pipe_w & (C7T3_stb_ne|~spc7_no_spc_rmo_st[3]))
spc7_mbar3_active <= 1'b1;
else if(~C7T3_stb_ne & spc7_no_spc_rmo_st[3])
spc7_mbar3_active <= 1'b0;
if(spc7_flush_inst0_g & ~spc7_dctl_flush_pipe_w & C7T0_stb_ne) spc7_flush0_active <= 1'b1;
else if(~C7T0_stb_ne) spc7_flush0_active <= 1'b0;
if(spc7_flush_inst1_g & ~spc7_dctl_flush_pipe_w & C7T1_stb_ne) spc7_flush1_active <= 1'b1;
else if(~C7T1_stb_ne) spc7_flush1_active <= 1'b0;
if(spc7_flush_inst2_g & ~spc7_dctl_flush_pipe_w & C7T2_stb_ne) spc7_flush2_active <= 1'b1;
else if(~C7T2_stb_ne) spc7_flush2_active <= 1'b0;
if(spc7_flush_inst3_g & ~spc7_dctl_flush_pipe_w & C7T3_stb_ne) spc7_flush3_active <= 1'b1;
else if(~C7T3_stb_ne) spc7_flush3_active <= 1'b0;
if(spc7_intrpt_disp_asi0_g & spc7_st_inst_vld_g & ~spc7_non_altspace_ldst_g & ~spc7_dctl_flush_pipe_w & C7T0_stb_ne)
spc7_intr0_active <= 1'b1;
else if(~C7T0_stb_ne)
spc7_intr0_active <= 1'b0;
if(spc7_intrpt_disp_asi1_g & spc7_st_inst_vld_g & ~spc7_non_altspace_ldst_g & ~spc7_dctl_flush_pipe_w & C7T1_stb_ne)
spc7_intr1_active <= 1'b1;
else if(~C7T1_stb_ne)
spc7_intr1_active <= 1'b0;
if(spc7_intrpt_disp_asi2_g & spc7_st_inst_vld_g & ~spc7_non_altspace_ldst_g & ~spc7_dctl_flush_pipe_w & C7T2_stb_ne)
spc7_intr2_active <= 1'b1;
else if(~C7T2_stb_ne)
spc7_intr2_active <= 1'b0;
if(spc7_intrpt_disp_asi3_g & spc7_st_inst_vld_g & ~spc7_non_altspace_ldst_g & ~spc7_dctl_flush_pipe_w & C7T3_stb_ne)
spc7_intr3_active <= 1'b1;
else if(~C7T3_stb_ne)
spc7_intr3_active <= 1'b0;
end
if(spc7_mbar0_active & spc7_inst_vld_w & spc7_sas_thrid_w[1:0] == 2'b00)
finish_test("spc", "membar violation thread 0", 7);
if(spc7_mbar1_active & spc7_inst_vld_w & spc7_sas_thrid_w[1:0] == 2'b01)
finish_test("spc", "membar violation thread 1", 7);
if(spc7_mbar2_active & spc7_inst_vld_w & spc7_sas_thrid_w[1:0] == 2'b10)
finish_test("spc", "membar violation thread 2", 7);
if(spc7_mbar3_active & spc7_inst_vld_w & spc7_sas_thrid_w[1:0] == 2'b11)
finish_test("spc", "membar violation thread 3", 7);
if(spc7_flush0_active & spc7_inst_vld_w & spc7_sas_thrid_w[1:0] == 2'b00)
finish_test("spc", "flush violation thread 0", 7);
if(spc7_flush1_active & spc7_inst_vld_w & spc7_sas_thrid_w[1:0] == 2'b01)
finish_test("spc", "flush violation thread 1", 7);
if(spc7_flush2_active & spc7_inst_vld_w & spc7_sas_thrid_w[1:0] == 2'b10)
finish_test("spc", "flush violation thread 2", 7);
if(spc7_flush3_active & spc7_inst_vld_w & spc7_sas_thrid_w[1:0] == 2'b11)
finish_test("spc", "flush violation thread 3", 7);
if(spc7_intr0_active & spc7_inst_vld_w & spc7_sas_thrid_w[1:0] == 2'b00)
finish_test("spc", "intr violation thread 0", 7);
if(spc7_intr1_active & spc7_inst_vld_w & spc7_sas_thrid_w[1:0] == 2'b01)
finish_test("spc", "intr violation thread 1", 7);
if(spc7_intr2_active & spc7_inst_vld_w & spc7_sas_thrid_w[1:0] == 2'b10)
finish_test("spc", "intr violation thread 2", 7);
if(spc7_intr3_active & spc7_inst_vld_w & spc7_sas_thrid_w[1:0] == 2'b11)
finish_test("spc", "intr violation thread 3", 7);
if(~rst_l | ~C7T0_stb_full | sctag_pcx_stall_pq) C7T0_stb_drain_cnt = 0;
else C7T0_stb_drain_cnt = C7T0_stb_drain_cnt + 1;
if(C7T0_stb_drain_cnt > stb_drain_to_max)
finish_test("spc", "stb 0 is not draining", 7);
if(~rst_l | ~C7T1_stb_full | sctag_pcx_stall_pq) C7T1_stb_drain_cnt = 0;
else C7T1_stb_drain_cnt = C7T1_stb_drain_cnt + 1;
if(C7T1_stb_drain_cnt > stb_drain_to_max)
finish_test("spc", "stb 1 is not draining", 7);
if(~rst_l | ~C7T2_stb_full | sctag_pcx_stall_pq) C7T2_stb_drain_cnt = 0;
else C7T2_stb_drain_cnt = C7T2_stb_drain_cnt + 1;
if(C7T2_stb_drain_cnt > stb_drain_to_max)
finish_test("spc", "stb 2 is not draining", 7);
if(~rst_l | ~C7T3_stb_full | sctag_pcx_stall_pq) C7T3_stb_drain_cnt = 0;
else C7T3_stb_drain_cnt = C7T3_stb_drain_cnt + 1;
if(C7T3_stb_drain_cnt > stb_drain_to_max)
finish_test("spc", "stb 3 is not draining", 7);
C7T0_stb_vld_sum_d1 <= C7T0_stb_vld_sum;
C7T1_stb_vld_sum_d1 <= C7T1_stb_vld_sum;
C7T2_stb_vld_sum_d1 <= C7T2_stb_vld_sum;
C7T3_stb_vld_sum_d1 <= C7T3_stb_vld_sum;
C7T0_defr_trp_en_d1 <= C7T0_defr_trp_en;
C7T1_defr_trp_en_d1 <= C7T1_defr_trp_en;
C7T2_defr_trp_en_d1 <= C7T2_defr_trp_en;
C7T3_defr_trp_en_d1 <= C7T3_defr_trp_en;
if(rst_l & C7T0_defr_trp_en_d1 & (C7T0_stb_vld_sum_d1 < C7T0_stb_vld_sum))
finish_test("spc", "tso_mon: deferred trap problems for store T0", 7);
if(rst_l & C7T1_defr_trp_en_d1 & (C7T1_stb_vld_sum_d1 < C7T1_stb_vld_sum))
finish_test("spc", "tso_mon: deferred trap problems for store T1", 7);
if(rst_l & C7T2_defr_trp_en_d1 & (C7T2_stb_vld_sum_d1 < C7T2_stb_vld_sum))
finish_test("spc", "tso_mon: deferred trap problems for store T2", 7);
if(rst_l & C7T3_defr_trp_en_d1 & (C7T3_stb_vld_sum_d1 < C7T3_stb_vld_sum))
finish_test("spc", "tso_mon: deferred trap problems for store T3", 7);
end
`endif // ifdef RTL_SPARC7
//-----------------------------------------------------------------------------
// This is put to catch a nasty rust bug where IFILL packet does not invalidate the
// D I exclusivity
// pardon my hardwired numbers
// FSM - 00 iDLE
// 01 started
// 10 ifill_pkt is out the ibuf_busy is high so handshake not finished
//----------------------------------------------------------------------------
reg [1:0] spc0_dfq_fsm1;
integer spc0_dfq_forced;
`ifdef RTL_SPARC0
initial begin
spc0_dfq_fsm1 = 2'b00;
spc0_dfq_forced = 0;
end
always @(posedge clk)
begin
if(~rst_l)
begin
cpx_spc0_data_cx2_d2 <= `CPX_WIDTH'b0;
cpx_spc0_data_cx2_d1 <= `CPX_WIDTH'b0;
spc0_dfq_byp_ff_en_d1 <= 1'b0;
spc0_dfq_wr_en_d1 <= 1'b0;
spc0_dfq_fsm1 <= 2'b00;
spc0_dfq_forced <= 0;
end
else
begin
cpx_spc0_data_cx2_d2 <= cpx_spc0_data_cx2_d1;
cpx_spc0_data_cx2_d1 <= cpx_spc0_data_cx2;
spc0_dfq_byp_ff_en_d1 <= spc0_dfq_byp_ff_en;
spc0_dfq_wr_en_d1 <= spc0_dfq_wr_en;
if(cpx_spc0_data_cx2_d2[144] & (cpx_spc0_data_cx2_d2[143:140] == 4'h1) & ~cpx_spc0_data_cx2_d2[133] &
cpx_spc0_data_cx2_d1[144] & (cpx_spc0_data_cx2_d1[143:140] == 4'h1) & cpx_spc0_data_cx2_d1[133])
begin
$display("%0d: spc%0d tso_mon:condition1 for bug6362\n", $time, 0);
if(spc0_dfq_wr_en & ~spc0_dfq_wr_en_d1 & ~spc0_dfq_byp_ff_en)
begin
$display("%0d: spc%0d tso_mon:condition2 for bug6362\n", $time, 0);
if(spc0_dfq_fsm1 == 2'b00)
spc0_dfq_fsm1 <= 2'b01;
else
finish_test("spc", "tso_mon:something is wrong with dfq_fsm1", 0);
if(kill_on_cross_mod_code)
finish_test("spc", "tso_mon:condition2 for bug6362", 0);
end
end
if((spc0_dfq_fsm1 == 2'b01) & spc0_lsu_ifill_pkt_vld & spc0_dfq_rd_advance)
begin
spc0_dfq_fsm1 <= 2'b00; // IDLE
end
else if((spc0_dfq_fsm1 == 2'b01) & spc0_lsu_ifill_pkt_vld & ~spc0_dfq_rd_advance)
begin
spc0_dfq_fsm1 <= 2'b10; // UNFINISHED HANDSHAKE
end
else if((spc0_dfq_fsm1 == 2'b10) & spc0_lsu_ifill_pkt_vld & spc0_dfq_rd_advance)
begin
spc0_dfq_fsm1 <= 2'b00;
end
else if((spc0_dfq_fsm1 == 2'b10) & ~spc0_lsu_ifill_pkt_vld)
begin
finish_test("spc", "tso_mon:bug6362 hit - ifill_pkt goes out BEFORE dfq_rd_advance", 0);
end
if(force_dfq & ~spc0_dfq_byp_ff_en & (spc0_dfq_forced == 0))
begin
$display("%0d: spc%0d forcing spc0_dfq_forced\n", $time, 0);
force `TOP_DESIGN.sparc0.lsu.qctl2.dfq_byp_ff_en = 1'b0;
spc0_dfq_forced = 1;
end
else if((spc0_dfq_forced >0) && (spc0_dfq_forced <10))
spc0_dfq_forced = spc0_dfq_forced + 1;
else if(spc0_dfq_forced !=0)
begin
$display("%0d: spc%0d releasing spc0_dfq_forced\n", $time, 0);
release `TOP_DESIGN.sparc0.lsu.qctl2.dfq_byp_ff_en;
spc0_dfq_forced = 0;
end
//-------------
end // of else reset
end
`endif // ifdef RTL_SPARC0
reg [1:0] spc1_dfq_fsm1;
integer spc1_dfq_forced;
`ifdef RTL_SPARC1
initial begin
spc1_dfq_fsm1 = 2'b00;
spc1_dfq_forced = 0;
end
always @(posedge clk)
begin
if(~rst_l)
begin
cpx_spc1_data_cx2_d2 <= `CPX_WIDTH'b0;
cpx_spc1_data_cx2_d1 <= `CPX_WIDTH'b0;
spc1_dfq_byp_ff_en_d1 <= 1'b0;
spc1_dfq_wr_en_d1 <= 1'b0;
spc1_dfq_fsm1 <= 2'b00;
spc1_dfq_forced <= 0;
end
else
begin
cpx_spc1_data_cx2_d2 <= cpx_spc1_data_cx2_d1;
cpx_spc1_data_cx2_d1 <= cpx_spc1_data_cx2;
spc1_dfq_byp_ff_en_d1 <= spc1_dfq_byp_ff_en;
spc1_dfq_wr_en_d1 <= spc1_dfq_wr_en;
if(cpx_spc1_data_cx2_d2[144] & (cpx_spc1_data_cx2_d2[143:140] == 4'h1) & ~cpx_spc1_data_cx2_d2[133] &
cpx_spc1_data_cx2_d1[144] & (cpx_spc1_data_cx2_d1[143:140] == 4'h1) & cpx_spc1_data_cx2_d1[133])
begin
$display("%0d: spc%0d tso_mon:condition1 for bug6362\n", $time, 1);
if(spc1_dfq_wr_en & ~spc1_dfq_wr_en_d1 & ~spc1_dfq_byp_ff_en)
begin
$display("%0d: spc%0d tso_mon:condition2 for bug6362\n", $time, 1);
if(spc1_dfq_fsm1 == 2'b00)
spc1_dfq_fsm1 <= 2'b01;
else
finish_test("spc", "tso_mon:something is wrong with dfq_fsm1", 1);
if(kill_on_cross_mod_code)
finish_test("spc", "tso_mon:condition2 for bug6362", 1);
end
end
if((spc1_dfq_fsm1 == 2'b01) & spc1_lsu_ifill_pkt_vld & spc1_dfq_rd_advance)
begin
spc1_dfq_fsm1 <= 2'b00; // IDLE
end
else if((spc1_dfq_fsm1 == 2'b01) & spc1_lsu_ifill_pkt_vld & ~spc1_dfq_rd_advance)
begin
spc1_dfq_fsm1 <= 2'b10; // UNFINISHED HANDSHAKE
end
else if((spc1_dfq_fsm1 == 2'b10) & spc1_lsu_ifill_pkt_vld & spc1_dfq_rd_advance)
begin
spc1_dfq_fsm1 <= 2'b00;
end
else if((spc1_dfq_fsm1 == 2'b10) & ~spc1_lsu_ifill_pkt_vld)
begin
finish_test("spc", "tso_mon:bug6362 hit - ifill_pkt goes out BEFORE dfq_rd_advance", 1);
end
if(force_dfq & ~spc1_dfq_byp_ff_en & (spc1_dfq_forced == 0))
begin
$display("%0d: spc%0d forcing spc1_dfq_forced\n", $time, 1);
force `TOP_DESIGN.sparc1.lsu.qctl2.dfq_byp_ff_en = 1'b0;
spc1_dfq_forced = 1;
end
else if((spc1_dfq_forced >0) && (spc1_dfq_forced <10))
spc1_dfq_forced = spc1_dfq_forced + 1;
else if(spc1_dfq_forced !=0)
begin
$display("%0d: spc%0d releasing spc1_dfq_forced\n", $time, 1);
release `TOP_DESIGN.sparc1.lsu.qctl2.dfq_byp_ff_en;
spc1_dfq_forced = 0;
end
//-------------
end // of else reset
end
`endif // ifdef RTL_SPARC1
reg [1:0] spc2_dfq_fsm1;
integer spc2_dfq_forced;
`ifdef RTL_SPARC2
initial begin
spc2_dfq_fsm1 = 2'b00;
spc2_dfq_forced = 0;
end
always @(posedge clk)
begin
if(~rst_l)
begin
cpx_spc2_data_cx2_d2 <= `CPX_WIDTH'b0;
cpx_spc2_data_cx2_d1 <= `CPX_WIDTH'b0;
spc2_dfq_byp_ff_en_d1 <= 1'b0;
spc2_dfq_wr_en_d1 <= 1'b0;
spc2_dfq_fsm1 <= 2'b00;
spc2_dfq_forced <= 0;
end
else
begin
cpx_spc2_data_cx2_d2 <= cpx_spc2_data_cx2_d1;
cpx_spc2_data_cx2_d1 <= cpx_spc2_data_cx2;
spc2_dfq_byp_ff_en_d1 <= spc2_dfq_byp_ff_en;
spc2_dfq_wr_en_d1 <= spc2_dfq_wr_en;
if(cpx_spc2_data_cx2_d2[144] & (cpx_spc2_data_cx2_d2[143:140] == 4'h1) & ~cpx_spc2_data_cx2_d2[133] &
cpx_spc2_data_cx2_d1[144] & (cpx_spc2_data_cx2_d1[143:140] == 4'h1) & cpx_spc2_data_cx2_d1[133])
begin
$display("%0d: spc%0d tso_mon:condition1 for bug6362\n", $time, 2);
if(spc2_dfq_wr_en & ~spc2_dfq_wr_en_d1 & ~spc2_dfq_byp_ff_en)
begin
$display("%0d: spc%0d tso_mon:condition2 for bug6362\n", $time, 2);
if(spc2_dfq_fsm1 == 2'b00)
spc2_dfq_fsm1 <= 2'b01;
else
finish_test("spc", "tso_mon:something is wrong with dfq_fsm1", 2);
if(kill_on_cross_mod_code)
finish_test("spc", "tso_mon:condition2 for bug6362", 2);
end
end
if((spc2_dfq_fsm1 == 2'b01) & spc2_lsu_ifill_pkt_vld & spc2_dfq_rd_advance)
begin
spc2_dfq_fsm1 <= 2'b00; // IDLE
end
else if((spc2_dfq_fsm1 == 2'b01) & spc2_lsu_ifill_pkt_vld & ~spc2_dfq_rd_advance)
begin
spc2_dfq_fsm1 <= 2'b10; // UNFINISHED HANDSHAKE
end
else if((spc2_dfq_fsm1 == 2'b10) & spc2_lsu_ifill_pkt_vld & spc2_dfq_rd_advance)
begin
spc2_dfq_fsm1 <= 2'b00;
end
else if((spc2_dfq_fsm1 == 2'b10) & ~spc2_lsu_ifill_pkt_vld)
begin
finish_test("spc", "tso_mon:bug6362 hit - ifill_pkt goes out BEFORE dfq_rd_advance", 2);
end
if(force_dfq & ~spc2_dfq_byp_ff_en & (spc2_dfq_forced == 0))
begin
$display("%0d: spc%0d forcing spc2_dfq_forced\n", $time, 2);
force `TOP_DESIGN.sparc2.lsu.qctl2.dfq_byp_ff_en = 1'b0;
spc2_dfq_forced = 1;
end
else if((spc2_dfq_forced >0) && (spc2_dfq_forced <10))
spc2_dfq_forced = spc2_dfq_forced + 1;
else if(spc2_dfq_forced !=0)
begin
$display("%0d: spc%0d releasing spc2_dfq_forced\n", $time, 2);
release `TOP_DESIGN.sparc2.lsu.qctl2.dfq_byp_ff_en;
spc2_dfq_forced = 0;
end
//-------------
end // of else reset
end
`endif // ifdef RTL_SPARC2
reg [1:0] spc3_dfq_fsm1;
integer spc3_dfq_forced;
`ifdef RTL_SPARC3
initial begin
spc3_dfq_fsm1 = 2'b00;
spc3_dfq_forced = 0;
end
always @(posedge clk)
begin
if(~rst_l)
begin
cpx_spc3_data_cx2_d2 <= `CPX_WIDTH'b0;
cpx_spc3_data_cx2_d1 <= `CPX_WIDTH'b0;
spc3_dfq_byp_ff_en_d1 <= 1'b0;
spc3_dfq_wr_en_d1 <= 1'b0;
spc3_dfq_fsm1 <= 2'b00;
spc3_dfq_forced <= 0;
end
else
begin
cpx_spc3_data_cx2_d2 <= cpx_spc3_data_cx2_d1;
cpx_spc3_data_cx2_d1 <= cpx_spc3_data_cx2;
spc3_dfq_byp_ff_en_d1 <= spc3_dfq_byp_ff_en;
spc3_dfq_wr_en_d1 <= spc3_dfq_wr_en;
if(cpx_spc3_data_cx2_d2[144] & (cpx_spc3_data_cx2_d2[143:140] == 4'h1) & ~cpx_spc3_data_cx2_d2[133] &
cpx_spc3_data_cx2_d1[144] & (cpx_spc3_data_cx2_d1[143:140] == 4'h1) & cpx_spc3_data_cx2_d1[133])
begin
$display("%0d: spc%0d tso_mon:condition1 for bug6362\n", $time, 3);
if(spc3_dfq_wr_en & ~spc3_dfq_wr_en_d1 & ~spc3_dfq_byp_ff_en)
begin
$display("%0d: spc%0d tso_mon:condition2 for bug6362\n", $time, 3);
if(spc3_dfq_fsm1 == 2'b00)
spc3_dfq_fsm1 <= 2'b01;
else
finish_test("spc", "tso_mon:something is wrong with dfq_fsm1", 3);
if(kill_on_cross_mod_code)
finish_test("spc", "tso_mon:condition2 for bug6362", 3);
end
end
if((spc3_dfq_fsm1 == 2'b01) & spc3_lsu_ifill_pkt_vld & spc3_dfq_rd_advance)
begin
spc3_dfq_fsm1 <= 2'b00; // IDLE
end
else if((spc3_dfq_fsm1 == 2'b01) & spc3_lsu_ifill_pkt_vld & ~spc3_dfq_rd_advance)
begin
spc3_dfq_fsm1 <= 2'b10; // UNFINISHED HANDSHAKE
end
else if((spc3_dfq_fsm1 == 2'b10) & spc3_lsu_ifill_pkt_vld & spc3_dfq_rd_advance)
begin
spc3_dfq_fsm1 <= 2'b00;
end
else if((spc3_dfq_fsm1 == 2'b10) & ~spc3_lsu_ifill_pkt_vld)
begin
finish_test("spc", "tso_mon:bug6362 hit - ifill_pkt goes out BEFORE dfq_rd_advance", 3);
end
if(force_dfq & ~spc3_dfq_byp_ff_en & (spc3_dfq_forced == 0))
begin
$display("%0d: spc%0d forcing spc3_dfq_forced\n", $time, 3);
force `TOP_DESIGN.sparc3.lsu.qctl2.dfq_byp_ff_en = 1'b0;
spc3_dfq_forced = 1;
end
else if((spc3_dfq_forced >0) && (spc3_dfq_forced <10))
spc3_dfq_forced = spc3_dfq_forced + 1;
else if(spc3_dfq_forced !=0)
begin
$display("%0d: spc%0d releasing spc3_dfq_forced\n", $time, 3);
release `TOP_DESIGN.sparc3.lsu.qctl2.dfq_byp_ff_en;
spc3_dfq_forced = 0;
end
//-------------
end // of else reset
end
`endif // ifdef RTL_SPARC3
reg [1:0] spc4_dfq_fsm1;
integer spc4_dfq_forced;
`ifdef RTL_SPARC4
initial begin
spc4_dfq_fsm1 = 2'b00;
spc4_dfq_forced = 0;
end
always @(posedge clk)
begin
if(~rst_l)
begin
cpx_spc4_data_cx2_d2 <= `CPX_WIDTH'b0;
cpx_spc4_data_cx2_d1 <= `CPX_WIDTH'b0;
spc4_dfq_byp_ff_en_d1 <= 1'b0;
spc4_dfq_wr_en_d1 <= 1'b0;
spc4_dfq_fsm1 <= 2'b00;
spc4_dfq_forced <= 0;
end
else
begin
cpx_spc4_data_cx2_d2 <= cpx_spc4_data_cx2_d1;
cpx_spc4_data_cx2_d1 <= cpx_spc4_data_cx2;
spc4_dfq_byp_ff_en_d1 <= spc4_dfq_byp_ff_en;
spc4_dfq_wr_en_d1 <= spc4_dfq_wr_en;
if(cpx_spc4_data_cx2_d2[144] & (cpx_spc4_data_cx2_d2[143:140] == 4'h1) & ~cpx_spc4_data_cx2_d2[133] &
cpx_spc4_data_cx2_d1[144] & (cpx_spc4_data_cx2_d1[143:140] == 4'h1) & cpx_spc4_data_cx2_d1[133])
begin
$display("%0d: spc%0d tso_mon:condition1 for bug6362\n", $time, 4);
if(spc4_dfq_wr_en & ~spc4_dfq_wr_en_d1 & ~spc4_dfq_byp_ff_en)
begin
$display("%0d: spc%0d tso_mon:condition2 for bug6362\n", $time, 4);
if(spc4_dfq_fsm1 == 2'b00)
spc4_dfq_fsm1 <= 2'b01;
else
finish_test("spc", "tso_mon:something is wrong with dfq_fsm1", 4);
if(kill_on_cross_mod_code)
finish_test("spc", "tso_mon:condition2 for bug6362", 4);
end
end
if((spc4_dfq_fsm1 == 2'b01) & spc4_lsu_ifill_pkt_vld & spc4_dfq_rd_advance)
begin
spc4_dfq_fsm1 <= 2'b00; // IDLE
end
else if((spc4_dfq_fsm1 == 2'b01) & spc4_lsu_ifill_pkt_vld & ~spc4_dfq_rd_advance)
begin
spc4_dfq_fsm1 <= 2'b10; // UNFINISHED HANDSHAKE
end
else if((spc4_dfq_fsm1 == 2'b10) & spc4_lsu_ifill_pkt_vld & spc4_dfq_rd_advance)
begin
spc4_dfq_fsm1 <= 2'b00;
end
else if((spc4_dfq_fsm1 == 2'b10) & ~spc4_lsu_ifill_pkt_vld)
begin
finish_test("spc", "tso_mon:bug6362 hit - ifill_pkt goes out BEFORE dfq_rd_advance", 4);
end
if(force_dfq & ~spc4_dfq_byp_ff_en & (spc4_dfq_forced == 0))
begin
$display("%0d: spc%0d forcing spc4_dfq_forced\n", $time, 4);
force `TOP_DESIGN.sparc4.lsu.qctl2.dfq_byp_ff_en = 1'b0;
spc4_dfq_forced = 1;
end
else if((spc4_dfq_forced >0) && (spc4_dfq_forced <10))
spc4_dfq_forced = spc4_dfq_forced + 1;
else if(spc4_dfq_forced !=0)
begin
$display("%0d: spc%0d releasing spc4_dfq_forced\n", $time, 4);
release `TOP_DESIGN.sparc4.lsu.qctl2.dfq_byp_ff_en;
spc4_dfq_forced = 0;
end
//-------------
end // of else reset
end
`endif // ifdef RTL_SPARC4
reg [1:0] spc5_dfq_fsm1;
integer spc5_dfq_forced;
`ifdef RTL_SPARC5
initial begin
spc5_dfq_fsm1 = 2'b00;
spc5_dfq_forced = 0;
end
always @(posedge clk)
begin
if(~rst_l)
begin
cpx_spc5_data_cx2_d2 <= `CPX_WIDTH'b0;
cpx_spc5_data_cx2_d1 <= `CPX_WIDTH'b0;
spc5_dfq_byp_ff_en_d1 <= 1'b0;
spc5_dfq_wr_en_d1 <= 1'b0;
spc5_dfq_fsm1 <= 2'b00;
spc5_dfq_forced <= 0;
end
else
begin
cpx_spc5_data_cx2_d2 <= cpx_spc5_data_cx2_d1;
cpx_spc5_data_cx2_d1 <= cpx_spc5_data_cx2;
spc5_dfq_byp_ff_en_d1 <= spc5_dfq_byp_ff_en;
spc5_dfq_wr_en_d1 <= spc5_dfq_wr_en;
if(cpx_spc5_data_cx2_d2[144] & (cpx_spc5_data_cx2_d2[143:140] == 4'h1) & ~cpx_spc5_data_cx2_d2[133] &
cpx_spc5_data_cx2_d1[144] & (cpx_spc5_data_cx2_d1[143:140] == 4'h1) & cpx_spc5_data_cx2_d1[133])
begin
$display("%0d: spc%0d tso_mon:condition1 for bug6362\n", $time, 5);
if(spc5_dfq_wr_en & ~spc5_dfq_wr_en_d1 & ~spc5_dfq_byp_ff_en)
begin
$display("%0d: spc%0d tso_mon:condition2 for bug6362\n", $time, 5);
if(spc5_dfq_fsm1 == 2'b00)
spc5_dfq_fsm1 <= 2'b01;
else
finish_test("spc", "tso_mon:something is wrong with dfq_fsm1", 5);
if(kill_on_cross_mod_code)
finish_test("spc", "tso_mon:condition2 for bug6362", 5);
end
end
if((spc5_dfq_fsm1 == 2'b01) & spc5_lsu_ifill_pkt_vld & spc5_dfq_rd_advance)
begin
spc5_dfq_fsm1 <= 2'b00; // IDLE
end
else if((spc5_dfq_fsm1 == 2'b01) & spc5_lsu_ifill_pkt_vld & ~spc5_dfq_rd_advance)
begin
spc5_dfq_fsm1 <= 2'b10; // UNFINISHED HANDSHAKE
end
else if((spc5_dfq_fsm1 == 2'b10) & spc5_lsu_ifill_pkt_vld & spc5_dfq_rd_advance)
begin
spc5_dfq_fsm1 <= 2'b00;
end
else if((spc5_dfq_fsm1 == 2'b10) & ~spc5_lsu_ifill_pkt_vld)
begin
finish_test("spc", "tso_mon:bug6362 hit - ifill_pkt goes out BEFORE dfq_rd_advance", 5);
end
if(force_dfq & ~spc5_dfq_byp_ff_en & (spc5_dfq_forced == 0))
begin
$display("%0d: spc%0d forcing spc5_dfq_forced\n", $time, 5);
force `TOP_DESIGN.sparc5.lsu.qctl2.dfq_byp_ff_en = 1'b0;
spc5_dfq_forced = 1;
end
else if((spc5_dfq_forced >0) && (spc5_dfq_forced <10))
spc5_dfq_forced = spc5_dfq_forced + 1;
else if(spc5_dfq_forced !=0)
begin
$display("%0d: spc%0d releasing spc5_dfq_forced\n", $time, 5);
release `TOP_DESIGN.sparc5.lsu.qctl2.dfq_byp_ff_en;
spc5_dfq_forced = 0;
end
//-------------
end // of else reset
end
`endif // ifdef RTL_SPARC5
reg [1:0] spc6_dfq_fsm1;
integer spc6_dfq_forced;
`ifdef RTL_SPARC6
initial begin
spc6_dfq_fsm1 = 2'b00;
spc6_dfq_forced = 0;
end
always @(posedge clk)
begin
if(~rst_l)
begin
cpx_spc6_data_cx2_d2 <= `CPX_WIDTH'b0;
cpx_spc6_data_cx2_d1 <= `CPX_WIDTH'b0;
spc6_dfq_byp_ff_en_d1 <= 1'b0;
spc6_dfq_wr_en_d1 <= 1'b0;
spc6_dfq_fsm1 <= 2'b00;
spc6_dfq_forced <= 0;
end
else
begin
cpx_spc6_data_cx2_d2 <= cpx_spc6_data_cx2_d1;
cpx_spc6_data_cx2_d1 <= cpx_spc6_data_cx2;
spc6_dfq_byp_ff_en_d1 <= spc6_dfq_byp_ff_en;
spc6_dfq_wr_en_d1 <= spc6_dfq_wr_en;
if(cpx_spc6_data_cx2_d2[144] & (cpx_spc6_data_cx2_d2[143:140] == 4'h1) & ~cpx_spc6_data_cx2_d2[133] &
cpx_spc6_data_cx2_d1[144] & (cpx_spc6_data_cx2_d1[143:140] == 4'h1) & cpx_spc6_data_cx2_d1[133])
begin
$display("%0d: spc%0d tso_mon:condition1 for bug6362\n", $time, 6);
if(spc6_dfq_wr_en & ~spc6_dfq_wr_en_d1 & ~spc6_dfq_byp_ff_en)
begin
$display("%0d: spc%0d tso_mon:condition2 for bug6362\n", $time, 6);
if(spc6_dfq_fsm1 == 2'b00)
spc6_dfq_fsm1 <= 2'b01;
else
finish_test("spc", "tso_mon:something is wrong with dfq_fsm1", 6);
if(kill_on_cross_mod_code)
finish_test("spc", "tso_mon:condition2 for bug6362", 6);
end
end
if((spc6_dfq_fsm1 == 2'b01) & spc6_lsu_ifill_pkt_vld & spc6_dfq_rd_advance)
begin
spc6_dfq_fsm1 <= 2'b00; // IDLE
end
else if((spc6_dfq_fsm1 == 2'b01) & spc6_lsu_ifill_pkt_vld & ~spc6_dfq_rd_advance)
begin
spc6_dfq_fsm1 <= 2'b10; // UNFINISHED HANDSHAKE
end
else if((spc6_dfq_fsm1 == 2'b10) & spc6_lsu_ifill_pkt_vld & spc6_dfq_rd_advance)
begin
spc6_dfq_fsm1 <= 2'b00;
end
else if((spc6_dfq_fsm1 == 2'b10) & ~spc6_lsu_ifill_pkt_vld)
begin
finish_test("spc", "tso_mon:bug6362 hit - ifill_pkt goes out BEFORE dfq_rd_advance", 6);
end
if(force_dfq & ~spc6_dfq_byp_ff_en & (spc6_dfq_forced == 0))
begin
$display("%0d: spc%0d forcing spc6_dfq_forced\n", $time, 6);
force `TOP_DESIGN.sparc6.lsu.qctl2.dfq_byp_ff_en = 1'b0;
spc6_dfq_forced = 1;
end
else if((spc6_dfq_forced >0) && (spc6_dfq_forced <10))
spc6_dfq_forced = spc6_dfq_forced + 1;
else if(spc6_dfq_forced !=0)
begin
$display("%0d: spc%0d releasing spc6_dfq_forced\n", $time, 6);
release `TOP_DESIGN.sparc6.lsu.qctl2.dfq_byp_ff_en;
spc6_dfq_forced = 0;
end
//-------------
end // of else reset
end
`endif // ifdef RTL_SPARC6
reg [1:0] spc7_dfq_fsm1;
integer spc7_dfq_forced;
`ifdef RTL_SPARC7
initial begin
spc7_dfq_fsm1 = 2'b00;
spc7_dfq_forced = 0;
end
always @(posedge clk)
begin
if(~rst_l)
begin
cpx_spc7_data_cx2_d2 <= `CPX_WIDTH'b0;
cpx_spc7_data_cx2_d1 <= `CPX_WIDTH'b0;
spc7_dfq_byp_ff_en_d1 <= 1'b0;
spc7_dfq_wr_en_d1 <= 1'b0;
spc7_dfq_fsm1 <= 2'b00;
spc7_dfq_forced <= 0;
end
else
begin
cpx_spc7_data_cx2_d2 <= cpx_spc7_data_cx2_d1;
cpx_spc7_data_cx2_d1 <= cpx_spc7_data_cx2;
spc7_dfq_byp_ff_en_d1 <= spc7_dfq_byp_ff_en;
spc7_dfq_wr_en_d1 <= spc7_dfq_wr_en;
if(cpx_spc7_data_cx2_d2[144] & (cpx_spc7_data_cx2_d2[143:140] == 4'h1) & ~cpx_spc7_data_cx2_d2[133] &
cpx_spc7_data_cx2_d1[144] & (cpx_spc7_data_cx2_d1[143:140] == 4'h1) & cpx_spc7_data_cx2_d1[133])
begin
$display("%0d: spc%0d tso_mon:condition1 for bug6362\n", $time, 7);
if(spc7_dfq_wr_en & ~spc7_dfq_wr_en_d1 & ~spc7_dfq_byp_ff_en)
begin
$display("%0d: spc%0d tso_mon:condition2 for bug6362\n", $time, 7);
if(spc7_dfq_fsm1 == 2'b00)
spc7_dfq_fsm1 <= 2'b01;
else
finish_test("spc", "tso_mon:something is wrong with dfq_fsm1", 7);
if(kill_on_cross_mod_code)
finish_test("spc", "tso_mon:condition2 for bug6362", 7);
end
end
if((spc7_dfq_fsm1 == 2'b01) & spc7_lsu_ifill_pkt_vld & spc7_dfq_rd_advance)
begin
spc7_dfq_fsm1 <= 2'b00; // IDLE
end
else if((spc7_dfq_fsm1 == 2'b01) & spc7_lsu_ifill_pkt_vld & ~spc7_dfq_rd_advance)
begin
spc7_dfq_fsm1 <= 2'b10; // UNFINISHED HANDSHAKE
end
else if((spc7_dfq_fsm1 == 2'b10) & spc7_lsu_ifill_pkt_vld & spc7_dfq_rd_advance)
begin
spc7_dfq_fsm1 <= 2'b00;
end
else if((spc7_dfq_fsm1 == 2'b10) & ~spc7_lsu_ifill_pkt_vld)
begin
finish_test("spc", "tso_mon:bug6362 hit - ifill_pkt goes out BEFORE dfq_rd_advance", 7);
end
if(force_dfq & ~spc7_dfq_byp_ff_en & (spc7_dfq_forced == 0))
begin
$display("%0d: spc%0d forcing spc7_dfq_forced\n", $time, 7);
force `TOP_DESIGN.sparc7.lsu.qctl2.dfq_byp_ff_en = 1'b0;
spc7_dfq_forced = 1;
end
else if((spc7_dfq_forced >0) && (spc7_dfq_forced <10))
spc7_dfq_forced = spc7_dfq_forced + 1;
else if(spc7_dfq_forced !=0)
begin
$display("%0d: spc%0d releasing spc7_dfq_forced\n", $time, 7);
release `TOP_DESIGN.sparc7.lsu.qctl2.dfq_byp_ff_en;
spc7_dfq_forced = 0;
end
//-------------
end // of else reset
end
`endif // ifdef RTL_SPARC7
//==============================================================================
//== End of Main program ====================================================
//==============================================================================
//==============================================================================
// Tasks and functions
//==============================================================================
//==============================================================================
// tso_mon models the 16 L2MB entries per sctag.
// sctag_l2mb_cam looks for the tso_mon L2MB entry which is valid and has the same
// address as the incoming sctag_addr_c2
//==============================================================================
function sctag_l2mb_cam;
input [1:0] tag;
integer i;
integer done;
begin
i = 0;
done = 0;
if(tag == 2'h0)
begin
while(!done)
begin
if((sctag0_l2mb_state[i] != `L2MB_IDLE) & (sctag0_l2mb_addr[i] == sctag0_addr_c2[39:8]))
begin
done = 1;
end
else
begin
i = i +1;
if(i>15) done = 1;
end
end
end
if(tag == 2'h1)
begin
while(!done)
begin
if((sctag1_l2mb_state[i] != `L2MB_IDLE) & (sctag1_l2mb_addr[i] == sctag1_addr_c2[39:8]))
begin
done = 1;
end
else
begin
i = i +1;
if(i>15) done = 1;
end
end
end
if(tag == 2'h2)
begin
while(!done)
begin
if((sctag2_l2mb_state[i] != `L2MB_IDLE) & (sctag2_l2mb_addr[i] == sctag2_addr_c2[39:8]))
begin
done = 1;
end
else
begin
i = i +1;
if(i>15) done = 1;
end
end
end
if(tag == 2'h3)
begin
while(!done)
begin
if((sctag3_l2mb_state[i] != `L2MB_IDLE) & (sctag3_l2mb_addr[i] == sctag3_addr_c2[39:8]))
begin
done = 1;
end
else
begin
i = i +1;
if(i>15) done = 1;
end
end
end
sctag_l2mb_cam = i;
end
endfunction
//==============================================================================
// tso_mon models the 16 L2MB entries per sctag.
// sctag_find_next_available finds the next available (free) entry to write stuff into it
//==============================================================================
function sctag_find_next_available;
input [1:0] tag;
integer i;
integer done;
begin
i = 0;
done = 0;
if(tag == 2'h0)
begin
while(!done)
begin
if(sctag0_l2mb_state[i] == `L2MB_IDLE)
begin
done = 1;
end
else
begin
i = i +1;
if(i>15) done = 1;
end
end
end
if(tag == 2'h1)
begin
while(!done)
begin
if(sctag1_l2mb_state[i] == `L2MB_IDLE)
begin
done = 1;
end
else
begin
i = i +1;
if(i>15) done = 1;
end
end
end
if(tag == 2'h2)
begin
while(!done)
begin
if(sctag2_l2mb_state[i] == `L2MB_IDLE)
begin
done = 1;
end
else
begin
i = i +1;
if(i>15) done = 1;
end
end
end
if(tag == 2'h3)
begin
while(!done)
begin
if(sctag3_l2mb_state[i] == `L2MB_IDLE)
begin
done = 1;
end
else
begin
i = i +1;
if(i>15) done = 1;
end
end
end
sctag_find_next_available = i;
end
endfunction
//=====================================================================
`define TSO_MON_PCX_VLD pcx_data[123]
`define TSO_MON_PCX_TYPE pcx_data[122:118]
`define TSO_MON_PCX_NC pcx_data[117]
`define TSO_MON_PCX_CPU_ID pcx_data[116:114]
`define TSO_MON_PCX_THR_ID pcx_data[113:112]
`define TSO_MON_PCX_INV pcx_data[111]
`define TSO_MON_PCX_PRF pcx_data[110]
`define TSO_MON_PCX_BST pcx_data[109]
`define TSO_MON_PCX_RPL pcx_data[108:107]
`define TSO_MON_PCX_SIZ pcx_data[106:104]
`define TSO_MON_PCX_ADD pcx_data[103:64]
`define TSO_MON_PCX_ADD39 pcx_data[103]
`define TSO_MON_PCX_DAT pcx_data[63:0]
//=====================================================================
// This task analyzes PCX packets
//=====================================================================
task get_pcx;
output [127:0] pcx_type_str;
input [`PCX_WIDTH-1:0] pcx_data;
input [5:0] pcx_type_d1;
input pcx_atom_pq_d1;
input pcx_atom_pq_d2;
input [2:0] spc_id;
input [4:0] pcx_req_pq_d1;
reg current_stb_nced;
begin
// This is just for easy debug
//-----------------------------
case(`TSO_MON_PCX_TYPE)
`LOAD_RQ : pcx_type_str = "LOAD_RQ";
`IMISS_RQ : pcx_type_str = "IMISS_RQ";
`STORE_RQ : pcx_type_str = "STORE_RQ";
`CAS1_RQ : pcx_type_str = "CAS1_RQ";
`CAS2_RQ : pcx_type_str = "CAS2_RQ";
`SWAP_RQ : pcx_type_str = "SWAP_RQ";
`STRLOAD_RQ: pcx_type_str = "STRLOAD_RQ";
`STRST_RQ : pcx_type_str = "STRST_RQ";
`STQ_RQ : pcx_type_str = "STQ_RQ";
`INT_RQ : pcx_type_str = "INT_RQ";
`FWD_RQ : pcx_type_str = "FWD_RQ";
`FWD_RPY : pcx_type_str = "FWD_RPY";
`RSVD_RQ : pcx_type_str = "RSVD_RQ";
`FPOP1_RQ : pcx_type_str = "FPOP1";
`FPOP2_RQ : pcx_type_str = "FPOP2";
default : pcx_type_str = "ILLEGAL";
endcase
if(tso_mon_msg)
$display("%0d tso_mon: cpu(%x) thr(%x) pcx pkt: TYPE= %s NC= %x INV= %x PRF= %x BST= %x RPL= %x SZ= %x PA= %x D= %x",
$time, `TSO_MON_PCX_CPU_ID, `TSO_MON_PCX_THR_ID, pcx_type_str, `TSO_MON_PCX_NC, `TSO_MON_PCX_INV, `TSO_MON_PCX_PRF, `TSO_MON_PCX_BST, `TSO_MON_PCX_RPL, `TSO_MON_PCX_SIZ, `TSO_MON_PCX_ADD, `TSO_MON_PCX_DAT);
// SOme sanity checks
//--------------------
if(`TSO_MON_PCX_VLD === 1'bx)
finish_test("spc", "valid bit - pcx_data[123] is X", spc_id);
// victorm Feb 2003 - removing the L1 way replacement info from the X checking
// since for prefetches and non-cacheables the way can be an X.
if(`TSO_MON_PCX_VLD & ~((`TSO_MON_PCX_TYPE == `FWD_RPY) || (`TSO_MON_PCX_TYPE == `INT_RQ)) & ((^pcx_data[122:109] === 1'bx) | (^pcx_data[106:64] === 1'bx)))
finish_test("spc", "PCX request with valid bit is 1, but pcx_data[122:64] is X", spc_id);
if(`TSO_MON_PCX_VLD & (`TSO_MON_PCX_TYPE == `INT_RQ) & (^pcx_data[122:109] === 1'bx))
finish_test("spc", "PCX INT request with valid bit is 1, but pcx_data[122:109] is X", spc_id);
if(`TSO_MON_PCX_VLD & ((`TSO_MON_PCX_TYPE == `CAS1_RQ) || (`TSO_MON_PCX_TYPE == `CAS2_RQ)) & (^pcx_data[122:0] === 1'bx))
finish_test("spc", "X in CAS packets", spc_id);
// victorm - when the request type is interrupt then this check is not valid.
//--------------------------------------------------------------------------
if(~((`TSO_MON_PCX_TYPE == `INT_RQ) | (`TSO_MON_PCX_TYPE == `FWD_RQ) | (`TSO_MON_PCX_TYPE == `FWD_RPY)) & ~(`TSO_MON_PCX_CPU_ID == spc_id))
finish_test("spc", "messed up pcx_id", spc_id);
if((pcx_type_d1 == `FPOP1_RQ) & ~(`TSO_MON_PCX_TYPE == `FPOP2_RQ))
finish_test("spc", "FPOP1 without FPOP2", spc_id);
if(pcx_atom_pq_d1 & ~((`TSO_MON_PCX_TYPE == `FPOP1_RQ) | (`TSO_MON_PCX_TYPE == `CAS1_RQ)))
begin
$display("pcx atomic1 problems heads up: pcx_type = %x", `TSO_MON_PCX_TYPE);
finish_test("spc", "pcx atomic1 problems ", spc_id);
end
if(pcx_atom_pq_d2 & ~((`TSO_MON_PCX_TYPE == `FPOP2_RQ) | (`TSO_MON_PCX_TYPE == `CAS2_RQ)))
begin
$display("pcx atomic2 problems heads up: pcx_type = %x", `TSO_MON_PCX_TYPE);
finish_test("spc", "pcx atomic2 problems ", spc_id);
end
if(~`TSO_MON_PCX_VLD & tso_mon_msg)
$display("%0d INFO: spc %d speculative request backoff", $time, spc_id);
case({`TSO_MON_PCX_CPU_ID, `TSO_MON_PCX_THR_ID})
5'h00: current_stb_nced = C0T0_stb_nced;
5'h01: current_stb_nced = C0T1_stb_nced;
5'h02: current_stb_nced = C0T2_stb_nced;
5'h03: current_stb_nced = C0T3_stb_nced;
5'h04: current_stb_nced = C1T0_stb_nced;
5'h05: current_stb_nced = C1T1_stb_nced;
5'h06: current_stb_nced = C1T2_stb_nced;
5'h07: current_stb_nced = C1T3_stb_nced;
5'h08: current_stb_nced = C2T0_stb_nced;
5'h09: current_stb_nced = C2T1_stb_nced;
5'h0a: current_stb_nced = C2T2_stb_nced;
5'h0b: current_stb_nced = C2T3_stb_nced;
5'h0c: current_stb_nced = C3T0_stb_nced;
5'h0d: current_stb_nced = C3T1_stb_nced;
5'h0e: current_stb_nced = C3T2_stb_nced;
5'h0f: current_stb_nced = C3T3_stb_nced;
5'h10: current_stb_nced = C4T0_stb_nced;
5'h11: current_stb_nced = C4T1_stb_nced;
5'h12: current_stb_nced = C4T2_stb_nced;
5'h13: current_stb_nced = C4T3_stb_nced;
5'h14: current_stb_nced = C5T0_stb_nced;
5'h15: current_stb_nced = C5T1_stb_nced;
5'h16: current_stb_nced = C5T2_stb_nced;
5'h17: current_stb_nced = C5T3_stb_nced;
5'h18: current_stb_nced = C6T0_stb_nced;
5'h19: current_stb_nced = C6T1_stb_nced;
5'h1a: current_stb_nced = C6T2_stb_nced;
5'h1b: current_stb_nced = C6T3_stb_nced;
5'h1c: current_stb_nced = C7T0_stb_nced;
5'h1d: current_stb_nced = C7T1_stb_nced;
5'h1e: current_stb_nced = C7T2_stb_nced;
5'h1f: current_stb_nced = C7T3_stb_nced;
default: current_stb_nced = 1'b1;
endcase
if(`TSO_MON_PCX_VLD & ((`TSO_MON_PCX_TYPE == `LOAD_RQ) | (`TSO_MON_PCX_TYPE == `STRLOAD_RQ)) & (`TSO_MON_PCX_ADD39 | pcx_req_pq_d1[4]) & current_stb_nced)
begin
finish_test("spc", "IO strong ordering problems ", spc_id);
end
if(`TSO_MON_PCX_VLD & ((`TSO_MON_PCX_TYPE == `LOAD_RQ) | (`TSO_MON_PCX_TYPE == `STRLOAD_RQ)) & (`TSO_MON_PCX_ADD39 | pcx_req_pq_d1[4]) & `TSO_MON_PCX_PRF)
begin
finish_test("spc", "prefetch to IO space ", spc_id);
end
end
endtask
//=====================================================================
// This task analyzes sctag to CPX packets
//=====================================================================
task get_sctag_cpx;
output [3:0] type;
output [127:0] sctag_cpx_type_str;
input sctag_cpx_req_cq_d1;
input [`CPX_WIDTH-1:0] sctag_cpx_data_ca;
input [1:0] sctag_id;
begin
type = sctag_cpx_data_ca[`CPX_RQ_HI:`CPX_RQ_LO];
// this is for debugging mostly
case(sctag_cpx_data_ca[`CPX_RQ_HI:`CPX_RQ_LO])
`LOAD_RET : sctag_cpx_type_str = "LOAD_RET";
`IFILL_RET: sctag_cpx_type_str = "IFILL_RET";
`INV_RET : sctag_cpx_type_str = "INV_RET";
`ST_ACK : sctag_cpx_type_str = "ST_ACK";
`AT_ACK : sctag_cpx_type_str = "AT_ACK";
`INT_RET : sctag_cpx_type_str = "INT_RET";
`TEST_RET : sctag_cpx_type_str = "TEST_RET";
`FP_RET : sctag_cpx_type_str = "FP_RET";
`EVICT_REQ: sctag_cpx_type_str = "EVICT_REQ";
`ERR_RET : sctag_cpx_type_str = "ERR_RET";
`STRLOAD_RET : sctag_cpx_type_str = "STRLOAD_RET";
`STRST_ACK: sctag_cpx_type_str = "STRST_ACK";
`FWD_RQ_RET: sctag_cpx_type_str = "FWD_RQ_RET";
`FWD_RPY_RET: sctag_cpx_type_str = "FWD_RPY_RET";
`RSVD_RET : sctag_cpx_type_str = "RSVD_RET";
default: sctag_cpx_type_str = "ILLEGAL";
endcase
if(sctag_cpx_req_cq_d1 & tso_mon_msg)
$display("%0d tso_mon: sctag%d-to-cpx pkt TYPE= %s data= %x",
$time, sctag_id, sctag_cpx_type_str, sctag_cpx_data_ca[127:0]);
end
endtask
//=====================================================================
// This task analyzes CPX to spc packets
//=====================================================================
task get_cpx_spc;
output [127:0] cpx_spc_type_str;
input [4:0] cpx_spc_type;
begin
case(cpx_spc_type)
`LOAD_RET : cpx_spc_type_str = "LOAD_RET";
`IFILL_RET: cpx_spc_type_str = "IFILL_RET";
`INV_RET : cpx_spc_type_str = "INV_RET";
`ST_ACK : cpx_spc_type_str = "ST_ACK";
`AT_ACK : cpx_spc_type_str = "AT_ACK";
`INT_RET : cpx_spc_type_str = "INT_RET";
`TEST_RET : cpx_spc_type_str = "TEST_RET";
`FP_RET : cpx_spc_type_str = "FP_RET";
`EVICT_REQ: cpx_spc_type_str = "EVICT_REQ";
`ERR_RET : cpx_spc_type_str = "ERR_RET";
`STRLOAD_RET : cpx_spc_type_str = "STRLOAD_RET";
`STRST_ACK: cpx_spc_type_str = "STRST_ACK";
`FWD_RQ_RET: cpx_spc_type_str = "FWD_RQ_RET";
`FWD_RPY_RET: cpx_spc_type_str = "FWD_RPY_RET";
`RSVD_RET : cpx_spc_type_str = "RSVD_RET";
default: cpx_spc_type_str = "ILLEGAL";
endcase
end
endtask
//------------------------------------------------
//=====================================================================
// This task allows some more clocks and kills the test
//=====================================================================
task finish_test;
input [512:0] message0;
input [512:0] message1;
input [2:0] id;
begin
$display("%0d ERROR: %s: %d %s", $time, message0, id, message1);
repeat(100) @(posedge clk);
$finish;
end
endtask
`endif // ifdef GATE_SIM
endmodule
|
module system_auto_us_0 (
s_axi_aclk,
s_axi_aresetn,
s_axi_araddr,
s_axi_arlen,
s_axi_arsize,
s_axi_arburst,
s_axi_arlock,
s_axi_arcache,
s_axi_arprot,
s_axi_arregion,
s_axi_arqos,
s_axi_arvalid,
s_axi_arready,
s_axi_rdata,
s_axi_rresp,
s_axi_rlast,
s_axi_rvalid,
s_axi_rready,
m_axi_araddr,
m_axi_arlen,
m_axi_arsize,
m_axi_arburst,
m_axi_arlock,
m_axi_arcache,
m_axi_arprot,
m_axi_arregion,
m_axi_arqos,
m_axi_arvalid,
m_axi_arready,
m_axi_rdata,
m_axi_rresp,
m_axi_rlast,
m_axi_rvalid,
m_axi_rready
);
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 SI_CLK CLK" *)
input wire s_axi_aclk;
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 SI_RST RST" *)
input wire s_axi_aresetn;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARADDR" *)
input wire [31 : 0] s_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLEN" *)
input wire [7 : 0] s_axi_arlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARSIZE" *)
input wire [2 : 0] s_axi_arsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARBURST" *)
input wire [1 : 0] s_axi_arburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLOCK" *)
input wire [0 : 0] s_axi_arlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARCACHE" *)
input wire [3 : 0] s_axi_arcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARPROT" *)
input wire [2 : 0] s_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARREGION" *)
input wire [3 : 0] s_axi_arregion;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARQOS" *)
input wire [3 : 0] s_axi_arqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARVALID" *)
input wire s_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARREADY" *)
output wire s_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RDATA" *)
output wire [31 : 0] s_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RRESP" *)
output wire [1 : 0] s_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RLAST" *)
output wire s_axi_rlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RVALID" *)
output wire s_axi_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RREADY" *)
input wire s_axi_rready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARADDR" *)
output wire [31 : 0] m_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARLEN" *)
output wire [7 : 0] m_axi_arlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARSIZE" *)
output wire [2 : 0] m_axi_arsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARBURST" *)
output wire [1 : 0] m_axi_arburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARLOCK" *)
output wire [0 : 0] m_axi_arlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARCACHE" *)
output wire [3 : 0] m_axi_arcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARPROT" *)
output wire [2 : 0] m_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARREGION" *)
output wire [3 : 0] m_axi_arregion;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARQOS" *)
output wire [3 : 0] m_axi_arqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARVALID" *)
output wire m_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARREADY" *)
input wire m_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RDATA" *)
input wire [63 : 0] m_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RRESP" *)
input wire [1 : 0] m_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RLAST" *)
input wire m_axi_rlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RVALID" *)
input wire m_axi_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RREADY" *)
output wire m_axi_rready;
axi_dwidth_converter_v2_1_top #(
.C_FAMILY("zynq"),
.C_AXI_PROTOCOL(0),
.C_S_AXI_ID_WIDTH(1),
.C_SUPPORTS_ID(0),
.C_AXI_ADDR_WIDTH(32),
.C_S_AXI_DATA_WIDTH(32),
.C_M_AXI_DATA_WIDTH(64),
.C_AXI_SUPPORTS_WRITE(0),
.C_AXI_SUPPORTS_READ(1),
.C_FIFO_MODE(0),
.C_S_AXI_ACLK_RATIO(1),
.C_M_AXI_ACLK_RATIO(2),
.C_AXI_IS_ACLK_ASYNC(0),
.C_MAX_SPLIT_BEATS(16),
.C_PACKING_LEVEL(1),
.C_SYNCHRONIZER_STAGE(3)
) inst (
.s_axi_aclk(s_axi_aclk),
.s_axi_aresetn(s_axi_aresetn),
.s_axi_awid(1'H0),
.s_axi_awaddr(32'H00000000),
.s_axi_awlen(8'H00),
.s_axi_awsize(3'H0),
.s_axi_awburst(2'H0),
.s_axi_awlock(1'H0),
.s_axi_awcache(4'H0),
.s_axi_awprot(3'H0),
.s_axi_awregion(4'H0),
.s_axi_awqos(4'H0),
.s_axi_awvalid(1'H0),
.s_axi_awready(),
.s_axi_wdata(32'H00000000),
.s_axi_wstrb(4'HF),
.s_axi_wlast(1'H1),
.s_axi_wvalid(1'H0),
.s_axi_wready(),
.s_axi_bid(),
.s_axi_bresp(),
.s_axi_bvalid(),
.s_axi_bready(1'H0),
.s_axi_arid(1'H0),
.s_axi_araddr(s_axi_araddr),
.s_axi_arlen(s_axi_arlen),
.s_axi_arsize(s_axi_arsize),
.s_axi_arburst(s_axi_arburst),
.s_axi_arlock(s_axi_arlock),
.s_axi_arcache(s_axi_arcache),
.s_axi_arprot(s_axi_arprot),
.s_axi_arregion(s_axi_arregion),
.s_axi_arqos(s_axi_arqos),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_arready(s_axi_arready),
.s_axi_rid(),
.s_axi_rdata(s_axi_rdata),
.s_axi_rresp(s_axi_rresp),
.s_axi_rlast(s_axi_rlast),
.s_axi_rvalid(s_axi_rvalid),
.s_axi_rready(s_axi_rready),
.m_axi_aclk(1'H0),
.m_axi_aresetn(1'H0),
.m_axi_awaddr(),
.m_axi_awlen(),
.m_axi_awsize(),
.m_axi_awburst(),
.m_axi_awlock(),
.m_axi_awcache(),
.m_axi_awprot(),
.m_axi_awregion(),
.m_axi_awqos(),
.m_axi_awvalid(),
.m_axi_awready(1'H0),
.m_axi_wdata(),
.m_axi_wstrb(),
.m_axi_wlast(),
.m_axi_wvalid(),
.m_axi_wready(1'H0),
.m_axi_bresp(2'H0),
.m_axi_bvalid(1'H0),
.m_axi_bready(),
.m_axi_araddr(m_axi_araddr),
.m_axi_arlen(m_axi_arlen),
.m_axi_arsize(m_axi_arsize),
.m_axi_arburst(m_axi_arburst),
.m_axi_arlock(m_axi_arlock),
.m_axi_arcache(m_axi_arcache),
.m_axi_arprot(m_axi_arprot),
.m_axi_arregion(m_axi_arregion),
.m_axi_arqos(m_axi_arqos),
.m_axi_arvalid(m_axi_arvalid),
.m_axi_arready(m_axi_arready),
.m_axi_rdata(m_axi_rdata),
.m_axi_rresp(m_axi_rresp),
.m_axi_rlast(m_axi_rlast),
.m_axi_rvalid(m_axi_rvalid),
.m_axi_rready(m_axi_rready)
);
endmodule
|
module clk_wiz_1_clk_wiz
(// Clock in ports
input clk_in1,
// Clock out ports
output clk_out1
);
// Input buffering
//------------------------------------
IBUF clkin1_ibufg
(.O (clk_in1_clk_wiz_1),
.I (clk_in1));
// Clocking PRIMITIVE
//------------------------------------
// Instantiation of the MMCM PRIMITIVE
// * Unused inputs are tied off
// * Unused outputs are labeled unused
wire [15:0] do_unused;
wire drdy_unused;
wire psdone_unused;
wire locked_int;
wire clkfbout_clk_wiz_1;
wire clkfbout_buf_clk_wiz_1;
wire clkfboutb_unused;
wire clkout0b_unused;
wire clkout1_unused;
wire clkout1b_unused;
wire clkout2_unused;
wire clkout2b_unused;
wire clkout3_unused;
wire clkout3b_unused;
wire clkout4_unused;
wire clkout5_unused;
wire clkout6_unused;
wire clkfbstopped_unused;
wire clkinstopped_unused;
MMCME2_ADV
#(.BANDWIDTH ("OPTIMIZED"),
.CLKOUT4_CASCADE ("FALSE"),
.COMPENSATION ("ZHOLD"),
.STARTUP_WAIT ("FALSE"),
.DIVCLK_DIVIDE (5),
.CLKFBOUT_MULT_F (32.000),
.CLKFBOUT_PHASE (0.000),
.CLKFBOUT_USE_FINE_PS ("FALSE"),
.CLKOUT0_DIVIDE_F (128.000),
.CLKOUT0_PHASE (0.000),
.CLKOUT0_DUTY_CYCLE (0.500),
.CLKOUT0_USE_FINE_PS ("FALSE"),
.CLKIN1_PERIOD (10.0))
mmcm_adv_inst
// Output clocks
(
.CLKFBOUT (clkfbout_clk_wiz_1),
.CLKFBOUTB (clkfboutb_unused),
.CLKOUT0 (clk_out1_clk_wiz_1),
.CLKOUT0B (clkout0b_unused),
.CLKOUT1 (clkout1_unused),
.CLKOUT1B (clkout1b_unused),
.CLKOUT2 (clkout2_unused),
.CLKOUT2B (clkout2b_unused),
.CLKOUT3 (clkout3_unused),
.CLKOUT3B (clkout3b_unused),
.CLKOUT4 (clkout4_unused),
.CLKOUT5 (clkout5_unused),
.CLKOUT6 (clkout6_unused),
// Input clock control
.CLKFBIN (clkfbout_buf_clk_wiz_1),
.CLKIN1 (clk_in1_clk_wiz_1),
.CLKIN2 (1'b0),
// Tied to always select the primary input clock
.CLKINSEL (1'b1),
// Ports for dynamic reconfiguration
.DADDR (7'h0),
.DCLK (1'b0),
.DEN (1'b0),
.DI (16'h0),
.DO (do_unused),
.DRDY (drdy_unused),
.DWE (1'b0),
// Ports for dynamic phase shift
.PSCLK (1'b0),
.PSEN (1'b0),
.PSINCDEC (1'b0),
.PSDONE (psdone_unused),
// Other control and status signals
.LOCKED (locked_int),
.CLKINSTOPPED (clkinstopped_unused),
.CLKFBSTOPPED (clkfbstopped_unused),
.PWRDWN (1'b0),
.RST (1'b0));
// Output buffering
//-----------------------------------
BUFG clkf_buf
(.O (clkfbout_buf_clk_wiz_1),
.I (clkfbout_clk_wiz_1));
BUFG clkout1_buf
(.O (clk_out1),
.I (clk_out1_clk_wiz_1));
endmodule
|
module top();
// Inputs are registered
reg A;
reg B;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
B = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 B = 1'b0;
#60 VGND = 1'b0;
#80 VNB = 1'b0;
#100 VPB = 1'b0;
#120 VPWR = 1'b0;
#140 A = 1'b1;
#160 B = 1'b1;
#180 VGND = 1'b1;
#200 VNB = 1'b1;
#220 VPB = 1'b1;
#240 VPWR = 1'b1;
#260 A = 1'b0;
#280 B = 1'b0;
#300 VGND = 1'b0;
#320 VNB = 1'b0;
#340 VPB = 1'b0;
#360 VPWR = 1'b0;
#380 VPWR = 1'b1;
#400 VPB = 1'b1;
#420 VNB = 1'b1;
#440 VGND = 1'b1;
#460 B = 1'b1;
#480 A = 1'b1;
#500 VPWR = 1'bx;
#520 VPB = 1'bx;
#540 VNB = 1'bx;
#560 VGND = 1'bx;
#580 B = 1'bx;
#600 A = 1'bx;
end
sky130_fd_sc_hd__or2 dut (.A(A), .B(B), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .X(X));
endmodule
|
module sky130_fd_sc_hvl__einvp (
//# {{data|Data Signals}}
input A ,
output Z ,
//# {{control|Control Signals}}
input TE
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
|
module level3arch (count1,count2,max_pos_l3,min_pos_l3,
q_begin_l3,q_begin_l3_flag,qwindow1_full,s_end_l3,swindow1_full,
s_end_l3_flag,max_pos_l3_n,min_pos_l3_n,cD_min_found,
cA0,cA1,cA2,cA3,cA4,cA5,cA6,cA7,cA8,cA9,cA10,cA11,cA12,cA13,cA14,cA15,cA16,cA17,cA18,cA19,cA20,cA21,cA22,cA23,cA24,cA25,cA26,cA27,cA28,cA29,cA30,cA31,cA32,cA33,cA34,cA35,cA36,cA37,cA38,cA39,cA40,cA41,cA42,cA43,cA44,cA45,cA46,cA47,cA48,cA49,cA50,cA51,cA52,cA53,cA54,cA55,cA56,cA57,cA58,cA59,cA60,cA61,cA62,cA63,cA64,cA65,cA66,cA67,cA68,cA69,cA70,cA71,cA72,cA73,cA74,cA75,cA76,cA77,cA78,cA79,cA80,cA81,cA82,cA83,cA84,cA85,cA86,cA87,cA88,cA89,cA90,cA91,cA92,cA93,cA94,cA95,cA96,cA97,cA98,cA99,data_in,clk,nReset);
output [3:0] count1;
output [8:0] count2;
output signed [15:0] max_pos_l3,min_pos_l3,
cA0,cA1,cA2,cA3,cA4,cA5,cA6,cA7,cA8,cA9,cA10,cA11,cA12,cA13,cA14,cA15,cA16,cA17,cA18,cA19,cA20,cA21,cA22,cA23,cA24,cA25,cA26,cA27,cA28,cA29,cA30,cA31,cA32,cA33,cA34,cA35,cA36,cA37,cA38,cA39,cA40,cA41,cA42,cA43,cA44,cA45,cA46,cA47,cA48,cA49,cA50,cA51,cA52,cA53,cA54,cA55,cA56,cA57,cA58,cA59,cA60,cA61,cA62,cA63,cA64,cA65,cA66,cA67,cA68,cA69,cA70,cA71,cA72,cA73,cA74,cA75,cA76,cA77,cA78,cA79,cA80,cA81,cA82,cA83,cA84,cA85,cA86,cA87,cA88,cA89,cA90,cA91,cA92,cA93,cA94,cA95,cA96,cA97,cA98,cA99;
output [15:0] q_begin_l3,s_end_l3,max_pos_l3_n,min_pos_l3_n;
output q_begin_l3_flag,qwindow1_full,swindow1_full,s_end_l3_flag,cD_min_found;
reg signed [15:0] cD_l3,cA_l3,max_val_l3,min_val_l3,max_pos_l3,
min_pos_l3,q_begin_l3,q1maxv,q1maxp,s_end_l3,s1minv,
s1minp,max_val_l3_n,max_pos_l3_n,max_pos_l3_temp,min_val_l3_n,
min_pos_l3_n,min_pos_l3_temp;
reg q_begin_l3_flag,qwindow1_full,swindow1_full,s_end_l3_flag,
cD_max_found,cD_min_found;
input [15:0] data_in;
input clk, nReset;
wire clk, nReset;
reg [15:0] data0, data1;
reg [3:0] count1;
reg [8:0] count2;
reg [8:0] count3;
reg [15:0] pos;
reg signed [15:0] cD_l3_store [0:`n3-2];
reg signed [15:0] cA_l3_store [0:`n3-2];
reg [15:0] temp1,temp2,temp3,temp4,temp5,temp6,temp7,temp8;
reg [15:0] c2,c3,c4,c5;
integer i;
always @(posedge clk or negedge nReset)
if (!nReset)
begin
data0 <= #20 0;
data1 <= #20 0;
cD_l3 <= #20 0;
cA_l3 <= #20 0;
count1 <= #20 0;
count2 <= #20 `n3;
count3 <= #20 0;
pos <= 0;
for (i=0; i<=`n3-2; i=i+1)
begin
cD_l3_store[i] <= #20 0;
cA_l3_store[i] <= #20 0;
end
end
else
begin
if (count1 < 9 && count2 > 0)
begin
case (count1)
0 : begin
data0 <= #20 0;
data1 <= #20 0;
count1 <= #20 count1 + 1;
end
1 : begin
if (count2 > 0)
begin
count1 <= #20 count1 + 1;
data0 <= #20 data_in;
if (count3 != 0 && count3 < `n3)
begin
cD_l3_store[count3-1] <= #20 cD_l3;
cA_l3_store[count3-1] <= #20 cA_l3;
end
else
begin
cD_l3_store[count3-1] <= #20 0;
cA_l3_store[count3-1] <= #20 0;
end
end
end
2 : begin
if(count2 > 1)
begin
data0 <= #20 data0 + data_in;
count1 <= #20 count1 + 1;
end
end
3 : begin
data0 <= #20 data0 + data_in;
count1 <= #20 count1 + 1;
end
4 : begin
data0 <= #20 data0 + data_in;
count1 <= #20 count1 + 1;
end
5 : begin
data1 <= #20 data_in;
count1 <= #20 count1 + 1;
end
6 : begin
data1 <= #20 data1 + data_in;
count1 <= #20 count1 + 1;
end
7 : begin
data1 <= #20 data1 + data_in;
count1 <= #20 count1 + 1;
end
8 : begin
cA_l3 <= #20 data0 + data1 + data_in;
cD_l3 <= #20 data0 - (data1 + data_in);
pos <= #20 pos + 1;
count3 <= #20 count3 + 1;
count1 <= #20 1;
count2 <= #20 count2 - 1;
end
default : begin
data0 <= #20 0;
data1 <= #20 0;
end
endcase
end
else
count1 <= #20 1;
end
always @(posedge clk or negedge nReset)
if (!nReset)
begin
max_val_l3 <= #20 0;
max_pos_l3 <= #20 0;
min_val_l3 <= #20 0;
min_pos_l3 <= #20 0;
end
else
begin
if (count1 == 1)
begin
if (count2 > 0)
begin
if (count2 == (`n3-1))
begin
max_val_l3 <= #20 cD_l3;
min_val_l3 <= #20 cD_l3;
max_pos_l3 <= #20 pos - 1;
min_pos_l3 <= #20 pos - 1; end
else
begin
if (cD_l3 > max_val_l3)
begin
max_val_l3 <= #20 cD_l3;
max_pos_l3 <= #20 pos - 1;
min_val_l3 <= #20 min_val_l3;
min_pos_l3 <= #20 min_pos_l3;
end
else
begin
if (cD_l3 < min_val_l3)
begin
min_val_l3 <= #20 cD_l3;
min_pos_l3 <= #20 pos - 1;
max_val_l3 <= #20 max_val_l3;
max_pos_l3 <= #20 max_pos_l3; end
else
begin
max_val_l3 <= #20 max_val_l3;
min_val_l3 <= #20 min_val_l3;
max_pos_l3 <= #20 max_pos_l3;
min_pos_l3 <= #20 min_pos_l3;
end
end
end
end
else
begin
max_val_l3 <= #20 max_val_l3;
min_val_l3 <= #20 min_val_l3;
max_pos_l3 <= #20 max_pos_l3;
min_pos_l3 <= #20 min_pos_l3;
end
end
else
begin
max_val_l3 <= #20 max_val_l3;
min_val_l3 <= #20 min_val_l3;
max_pos_l3 <= #20 max_pos_l3;
min_pos_l3 <= #20 min_pos_l3;
end
end
always @(*)
begin
temp1 = 0;
temp2 = 0;
temp3 = 0;
temp4 = 0;
temp5 = 0;
temp6 = 0;
temp7 = 0;
temp8 = 0;
if (count2 == 1)
begin
if (min_pos_l3 < max_pos_l3)
begin
temp1 = min_pos_l3 - `q_window_l3 - 1;
temp2 = min_pos_l3 - 1;
temp3 = max_pos_l3 + 1;
temp4 = max_pos_l3 + `s_window_l3 - 1;
temp5 = temp5;
temp6 = temp6;
temp7 = max_pos_l3;
temp8 = max_pos_l3 + (10*`rat);
end
else
begin
temp1 = max_pos_l3 - `q_window_l3 - 1;
temp2 = max_pos_l3 - 1;
temp3 = min_pos_l3 + 1;
temp4 = min_pos_l3 + `s_window_l3 - 1;
temp5 = min_pos_l3;
temp6 = min_pos_l3 + (10*`rat);
temp7 = max_pos_l3 - (15*`rat);
temp8 = max_pos_l3;
end
end
else
begin
temp1 = temp1;
temp2 = temp2;
temp3 = temp3;
temp4 = temp4;
temp5 = temp5;
temp6 = temp6;
temp7 = temp7;
temp8 = temp8;
end
end
always @(posedge clk or negedge nReset)
if (!nReset)
begin
c2 <= #20 0;
c3 <= #20 0;
c4 <= #20 0;
c5 <= #20 0;
q1maxv <= #20 0;
q1maxp <= #20 0;
qwindow1_full <= #20 0;
s1minv <= #20 0;
s1minp <= #20 0;
swindow1_full <= #20 0;
max_val_l3_n <= #20 0;
max_pos_l3_temp <= #20 0;
max_pos_l3_n <= #20 0;
cD_max_found <= #20 0;
min_val_l3_n <= #20 0;
min_pos_l3_temp <= #20 0;
min_pos_l3_n <= #20 0;
cD_min_found <= #20 0;
end
else
begin
if (count1 == 2 && count2 == 1)
begin
if (c2 <= temp2)
begin
if (c2 == 0)
c2 <= #20 temp1;
else
begin
if (c2 == temp1)
begin
c2 <= #20 temp1;
q1maxv <= #20 cD_l3_store[temp1];
q1maxp <= #20 temp1;
c2 <= #20 c2 + 1;
end
else
begin
if (cD_l3_store[c2] > q1maxv)
begin
q1maxv <= #20 cD_l3_store[c2];
q1maxp <= #20 c2;
end
else
begin
q1maxv <= #20 q1maxv;
q1maxp <= #20 q1maxp;
end
c2 <= #20 c2 + 1;
if (c2 >= temp2)
qwindow1_full <= #20 1;
else
qwindow1_full <= #20 qwindow1_full;
end
end
end
else
begin
c2 <= #20 c2;
q1maxv <= #20 q1maxv;
q1maxp <= #20 q1maxp;
qwindow1_full <= #20 qwindow1_full;
end
if (c3 <= temp4)
begin
if (c3 == 0)
c3 <= #20 temp3;
else
begin
if (c3 == temp3)
begin
c3 <= #20 temp3;
s1minv <= #20 cD_l3_store[temp3];
s1minp <= #20 temp3;
c3 <= #20 c3 + 1;
end
else
begin
if (cD_l3_store[c3] < s1minv)
begin
s1minv <= #20 cD_l3_store[c3];
s1minp <= #20 c3;
end
else
begin
s1minv <= #20 s1minv;
s1minp <= #20 s1minp;
end
c3 <= #20 c3 + 1;
if (c3 >= temp4)
swindow1_full <= #20 1;
else
swindow1_full <= #20 swindow1_full;
end
end
end
else
begin
c3 <= #20 c3;
s1minv <= #20 s1minv;
s1minp <= #20 s1minp;
swindow1_full <= #20 swindow1_full;
end
if (c4 <= temp6)
begin
if (c4 == 0)
c4 <= #20 temp5;
else
begin
if (c4 == temp5)
begin
c4 <= #20 temp5;
max_val_l3_n <= #20 cD_l3_store[temp5];
max_pos_l3_temp <= #20 temp5;
c4 <= #20 c4 + 1;
end
else
begin
if (cD_l3_store[c4] > max_val_l3_n)
begin
max_val_l3_n <= #20 cD_l3_store[c4];
max_pos_l3_temp <= #20 c4;
end
else
begin
max_val_l3_n <= #20 max_val_l3_n;
max_pos_l3_temp <= #20 max_pos_l3_temp;
end
c4 <= #20 c4 + 1;
if (c4 >= temp6)
cD_max_found <= #20 1;
else
cD_max_found <= #20 cD_max_found;
end
end
end
else
begin
c4 <= #20 c4;
max_val_l3_n <= #20 max_val_l3_n;
max_pos_l3_temp <= #20 max_pos_l3_temp;
max_pos_l3_n <= #20 max_pos_l3_n;
end
if (cD_max_found == 1)
max_pos_l3_n <= #20 max_pos_l3_temp;
else
max_pos_l3_n <= #20 max_pos_l3_n;
if (c5 <= temp8)
begin
if (c5 == 0)
c5 <= #20 temp7;
else
begin
if (c5 == temp7)
begin
c5 <= #20 temp7;
min_val_l3_n <= #20 cD_l3_store[temp7];
min_pos_l3_temp <= #20 temp7;
c5 <= #20 c5 + 1;
end
else
begin
if (cD_l3_store[c5] < min_val_l3_n)
begin
min_val_l3_n <= #20 cD_l3_store[c5];
min_pos_l3_temp <= #20 c5;
end
else
begin
min_val_l3_n <= #20 min_val_l3_n;
min_pos_l3_temp <= #20 min_pos_l3_temp;
end
c5 <= #20 c5 + 1;
if (c5 >= temp8)
cD_min_found <= #20 1;
else
cD_min_found <= #20 cD_min_found;
end
end
end
else
begin
c5 <= #20 c5;
min_val_l3_n <= #20 min_val_l3_n;
min_pos_l3_temp <= #20 min_pos_l3_temp;
min_pos_l3_n <= #20 min_pos_l3_n;
cD_min_found <= #20 cD_min_found;
end
if (cD_min_found == 1)
min_pos_l3_n <= #20 min_pos_l3_temp;
else
min_pos_l3_n <= #20 min_pos_l3_n;
end
else
begin
c2 <= #20 c2;
c3 <= #20 c3;
c4 <= #20 c4;
c5 <= #20 c5;
q1maxv <= #20 q1maxv;
q1maxp <= #20 q1maxp;
qwindow1_full <= #20 qwindow1_full;
s1minv <= #20 s1minv;
s1minp <= #20 s1minp;
swindow1_full <= #20 swindow1_full;
max_val_l3_n <= #20 max_val_l3_n;
max_pos_l3_temp <= #20 max_pos_l3_temp;
max_pos_l3_n <= #20 max_pos_l3_n;
cD_max_found <= #20 cD_max_found;
min_val_l3_n <= #20 min_val_l3_n;
min_pos_l3_temp <= #20 min_pos_l3_temp;
min_pos_l3_n <= #20 min_pos_l3_n;
cD_min_found <= #20 cD_min_found;
end
end
always @(*)
begin
q_begin_l3 = 0;
q_begin_l3_flag = 0;
if (qwindow1_full != 0)
begin
q_begin_l3 = q1maxp;
q_begin_l3_flag = 1;
end
else
begin
q_begin_l3 = q_begin_l3;
q_begin_l3_flag = q_begin_l3_flag;
end
end
always @(*)
begin
s_end_l3 = 0;
s_end_l3_flag = 0;
if (swindow1_full != 0)
begin
s_end_l3 = s1minp;
s_end_l3_flag = 1;
end
else
begin
s_end_l3 = s_end_l3;
s_end_l3_flag = s_end_l3_flag;
end
end
assign {cA0,cA1,cA2,cA3,cA4,cA5,cA6,cA7,cA8,cA9,cA10,cA11,cA12,cA13,cA14,cA15,cA16,cA17,cA18,cA19,cA20,cA21,cA22,cA23,cA24,cA25,cA26,cA27,cA28,cA29,cA30,cA31,cA32,cA33,cA34,cA35,cA36,cA37,cA38,cA39,cA40,cA41,cA42,cA43,cA44,cA45,cA46,cA47,cA48,cA49,cA50,cA51,cA52,cA53,cA54,cA55,cA56,cA57,cA58,cA59,cA60,cA61,cA62,cA63,cA64,cA65,cA66,cA67,cA68,cA69,cA70,cA71,cA72,cA73,cA74,cA75,cA76,cA77,cA78,cA79,cA80,cA81,cA82,cA83,cA84,cA85,cA86,cA87,cA88,cA89,cA90,
cA91,cA92,cA93,cA94,cA95,cA96,cA97,cA98,cA99} = {cA_l3_store[0],cA_l3_store[1],cA_l3_store[2],cA_l3_store[3],cA_l3_store[4],cA_l3_store[5],cA_l3_store[6],cA_l3_store[7],cA_l3_store[8],cA_l3_store[9],cA_l3_store[10],cA_l3_store[11],cA_l3_store[12],cA_l3_store[13],cA_l3_store[14],cA_l3_store[15],cA_l3_store[16],cA_l3_store[17],cA_l3_store[18],cA_l3_store[19],cA_l3_store[20],cA_l3_store[21],cA_l3_store[22],cA_l3_store[23],cA_l3_store[24],cA_l3_store[25],cA_l3_store[26],cA_l3_store[27],cA_l3_store[28],cA_l3_store[29],cA_l3_store[30],cA_l3_store[31],cA_l3_store[32],cA_l3_store[33],cA_l3_store[34],cA_l3_store[35],cA_l3_store[36],cA_l3_store[37],cA_l3_store[38],cA_l3_store[39],cA_l3_store[40],cA_l3_store[41],cA_l3_store[42],cA_l3_store[43],cA_l3_store[44],cA_l3_store[45],cA_l3_store[46],cA_l3_store[47],cA_l3_store[48],cA_l3_store[49],cA_l3_store[50],cA_l3_store[51],cA_l3_store[52],cA_l3_store[53],cA_l3_store[54],cA_l3_store[55],cA_l3_store[56],cA_l3_store[57],cA_l3_store[58],cA_l3_store[59],cA_l3_store[60],cA_l3_store[61],cA_l3_store[62],cA_l3_store[63],cA_l3_store[64],cA_l3_store[65],cA_l3_store[66],cA_l3_store[67],cA_l3_store[68],cA_l3_store[69],cA_l3_store[70],cA_l3_store[71],cA_l3_store[72],cA_l3_store[73],cA_l3_store[74],cA_l3_store[75],cA_l3_store[76],cA_l3_store[77],cA_l3_store[78],cA_l3_store[79],cA_l3_store[80],cA_l3_store[81],cA_l3_store[82],cA_l3_store[83],cA_l3_store[84],cA_l3_store[85],cA_l3_store[86],cA_l3_store[87],cA_l3_store[88],cA_l3_store[89],cA_l3_store[90],cA_l3_store[91],cA_l3_store[92],cA_l3_store[93],cA_l3_store[94],cA_l3_store[95],cA_l3_store[96],cA_l3_store[97],cA_l3_store[98],cA_l3_store[99]};
endmodule
|
module top();
// Inputs are registered
reg A1;
reg A2;
reg B1;
reg C1;
reg D1;
reg VPWR;
reg VGND;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A1 = 1'bX;
A2 = 1'bX;
B1 = 1'bX;
C1 = 1'bX;
D1 = 1'bX;
VGND = 1'bX;
VPWR = 1'bX;
#20 A1 = 1'b0;
#40 A2 = 1'b0;
#60 B1 = 1'b0;
#80 C1 = 1'b0;
#100 D1 = 1'b0;
#120 VGND = 1'b0;
#140 VPWR = 1'b0;
#160 A1 = 1'b1;
#180 A2 = 1'b1;
#200 B1 = 1'b1;
#220 C1 = 1'b1;
#240 D1 = 1'b1;
#260 VGND = 1'b1;
#280 VPWR = 1'b1;
#300 A1 = 1'b0;
#320 A2 = 1'b0;
#340 B1 = 1'b0;
#360 C1 = 1'b0;
#380 D1 = 1'b0;
#400 VGND = 1'b0;
#420 VPWR = 1'b0;
#440 VPWR = 1'b1;
#460 VGND = 1'b1;
#480 D1 = 1'b1;
#500 C1 = 1'b1;
#520 B1 = 1'b1;
#540 A2 = 1'b1;
#560 A1 = 1'b1;
#580 VPWR = 1'bx;
#600 VGND = 1'bx;
#620 D1 = 1'bx;
#640 C1 = 1'bx;
#660 B1 = 1'bx;
#680 A2 = 1'bx;
#700 A1 = 1'bx;
end
sky130_fd_sc_hs__a2111o dut (.A1(A1), .A2(A2), .B1(B1), .C1(C1), .D1(D1), .VPWR(VPWR), .VGND(VGND), .X(X));
endmodule
|
module hls_contrast_strefYi_div_u
#(parameter
in0_WIDTH = 32,
in1_WIDTH = 32,
out_WIDTH = 32
)
(
input clk,
input reset,
input ce,
input [in0_WIDTH-1:0] dividend,
input [in1_WIDTH-1:0] divisor,
input [1:0] sign_i,
output wire [1:0] sign_o,
output wire [out_WIDTH-1:0] quot,
output wire [out_WIDTH-1:0] remd
);
localparam cal_WIDTH = (in0_WIDTH > in1_WIDTH)? in0_WIDTH : in1_WIDTH;
//------------------------Local signal-------------------
reg [in0_WIDTH-1:0] dividend_tmp[0:in0_WIDTH];
reg [in1_WIDTH-1:0] divisor_tmp[0:in0_WIDTH];
reg [in0_WIDTH-1:0] remd_tmp[0:in0_WIDTH];
wire [in0_WIDTH-1:0] comb_tmp[0:in0_WIDTH-1];
wire [cal_WIDTH:0] cal_tmp[0:in0_WIDTH-1];
reg [1:0] sign_tmp[0:in0_WIDTH];
//------------------------Body---------------------------
assign quot = dividend_tmp[in0_WIDTH];
assign remd = remd_tmp[in0_WIDTH];
assign sign_o = sign_tmp[in0_WIDTH];
// dividend_tmp[0], divisor_tmp[0], remd_tmp[0]
always @(posedge clk)
begin
if (ce) begin
dividend_tmp[0] <= dividend;
divisor_tmp[0] <= divisor;
sign_tmp[0] <= sign_i;
remd_tmp[0] <= 1'b0;
end
end
genvar i;
generate
for (i = 0; i < in0_WIDTH; i = i + 1)
begin : loop
if (in0_WIDTH == 1) assign comb_tmp[i] = dividend_tmp[i][0];
else assign comb_tmp[i] = {remd_tmp[i][in0_WIDTH-2:0], dividend_tmp[i][in0_WIDTH-1]};
assign cal_tmp[i] = {1'b0, comb_tmp[i]} - {1'b0, divisor_tmp[i]};
always @(posedge clk)
begin
if (ce) begin
if (in0_WIDTH == 1) dividend_tmp[i+1] <= ~cal_tmp[i][cal_WIDTH];
else dividend_tmp[i+1] <= {dividend_tmp[i][in0_WIDTH-2:0], ~cal_tmp[i][cal_WIDTH]};
divisor_tmp[i+1] <= divisor_tmp[i];
remd_tmp[i+1] <= cal_tmp[i][cal_WIDTH]? comb_tmp[i] : cal_tmp[i][in0_WIDTH-1:0];
sign_tmp[i+1] <= sign_tmp[i];
end
end
end
endgenerate
endmodule
|
module hls_contrast_strefYi_div
#(parameter
in0_WIDTH = 32,
in1_WIDTH = 32,
out_WIDTH = 32
)
(
input clk,
input reset,
input ce,
input [in0_WIDTH-1:0] dividend,
input [in1_WIDTH-1:0] divisor,
output reg [out_WIDTH-1:0] quot,
output reg [out_WIDTH-1:0] remd
);
//------------------------Local signal-------------------
reg [in0_WIDTH-1:0] dividend0;
reg [in1_WIDTH-1:0] divisor0;
wire [in0_WIDTH-1:0] dividend_u;
wire [in1_WIDTH-1:0] divisor_u;
wire [out_WIDTH-1:0] quot_u;
wire [out_WIDTH-1:0] remd_u;
wire [1:0] sign_i;
wire [1:0] sign_o;
//------------------------Instantiation------------------
hls_contrast_strefYi_div_u #(
.in0_WIDTH ( in0_WIDTH ),
.in1_WIDTH ( in1_WIDTH ),
.out_WIDTH ( out_WIDTH )
) hls_contrast_strefYi_div_u_0 (
.clk ( clk ),
.reset ( reset ),
.ce ( ce ),
.dividend ( dividend_u ),
.divisor ( divisor_u ),
.sign_i ( sign_i ),
.sign_o ( sign_o ),
.quot ( quot_u ),
.remd ( remd_u )
);
//------------------------Body---------------------------
assign sign_i = {dividend0[in0_WIDTH-1] ^ divisor0[in1_WIDTH-1], dividend0[in0_WIDTH-1]};
assign dividend_u = dividend0[in0_WIDTH-1]? ~dividend0[in0_WIDTH-1:0] + 1'b1 :
dividend0[in0_WIDTH-1:0];
assign divisor_u = divisor0[in1_WIDTH-1]? ~divisor0[in1_WIDTH-1:0] + 1'b1 :
divisor0[in1_WIDTH-1:0];
always @(posedge clk)
begin
if (ce) begin
dividend0 <= dividend;
divisor0 <= divisor;
end
end
always @(posedge clk)
begin
if (ce) begin
if (sign_o[1])
quot <= ~quot_u + 1'b1;
else
quot <= quot_u;
end
end
always @(posedge clk)
begin
if (ce) begin
if (sign_o[0])
remd <= ~remd_u + 1'b1;
else
remd <= remd_u;
end
end
endmodule
|
module hls_contrast_strefYi(
clk,
reset,
ce,
din0,
din1,
dout);
parameter ID = 32'd1;
parameter NUM_STAGE = 32'd1;
parameter din0_WIDTH = 32'd1;
parameter din1_WIDTH = 32'd1;
parameter dout_WIDTH = 32'd1;
input clk;
input reset;
input ce;
input[din0_WIDTH - 1:0] din0;
input[din1_WIDTH - 1:0] din1;
output[dout_WIDTH - 1:0] dout;
wire[dout_WIDTH - 1:0] sig_remd;
hls_contrast_strefYi_div #(
.in0_WIDTH( din0_WIDTH ),
.in1_WIDTH( din1_WIDTH ),
.out_WIDTH( dout_WIDTH ))
hls_contrast_strefYi_div_U(
.dividend( din0 ),
.divisor( din1 ),
.quot( dout ),
.remd( sig_remd ),
.clk( clk ),
.ce( ce ),
.reset( reset ));
endmodule
|
module extracts the data ready signal from the SPI bus and makes sure to
* suppress false positives. The data ready signal is indicated by the converter
* by pulling DOUT low. This will only happen if the CS pin for the converter is
* low and no SPI transfer is active. There is a small delay between the end of
* the SPI transfer and the point where the converter starts to indicate the
* data ready signal. IDLE_TIMEOUT allows to specify the amount of clock cycles
* the bus needs to be idle before the data ready signal is detected.
*/
assign m_sclk = s_sclk;
assign m_sdo = s_sdo;
assign m_sdo_t = s_sdo_t;
assign s_sdi = m_sdi;
assign m_cs = s_cs;
reg [$clog2(IDLE_TIMEOUT)-1:0] counter = IDLE_TIMEOUT;
reg [2:0] sdi_d = 'h00;
always @(posedge clk) begin
if (resetn == 1'b0) begin
counter <= IDLE_TIMEOUT;
end else begin
if (s_cs[CS_PIN] == 1'b0 && spi_active == 1'b0) begin
if (counter != 'h00)
counter <= counter - 1'b1;
end else begin
counter <= IDLE_TIMEOUT;
end
end
end
always @(posedge clk) begin
/* The data ready signal is fully asynchronous */
sdi_d <= {sdi_d[1:0], m_sdi};
end
always @(posedge clk) begin
if (counter == 'h00 && sdi_d[2] == 1'b0) begin
data_ready <= 1'b1;
end else begin
data_ready <= 1'b0;
end
end
endmodule
|
module pulsar (clk, drv);
input clk /* synthesis chip_pin = "R8" */;
output drv /* synthesis chip_pin = "B5" */ ; // JP1.10 GPIO_07
// clk = 50MHz (20ns)
// run[0] = 25MHz (40ns)
// run[1] = 12.5MHz (80ns)
// run[2] = 6.25MHz (160ns)
// run[3] = 3.125MHz (320ns)
// run[4] = 1.5625MHz (640ns)
// run[5] = 0.78125MHz (1.28us)
// 40KHz = 25us (1250 clocks)
// 625 + 625
// /```\___/
// _/`0`\_1_/`2`\_3_/`4`\_5_...
reg [31:0] run; // free running counter
reg [31:0] mem [0:255]; // pulse sequence array
reg [31:0] limit;
reg [31:0] timer;
reg [7:0] pointer; // pointer
reg start; // start condition
reg prestart; // pre-history for the start condition
initial begin
$readmemh("ram.txt", mem);
end
always @ (*) limit = mem[pointer];
always @ (posedge clk) run <= run + 1;
// repeat after ~84ms (4 Mcycles)
always @ (posedge clk) prestart <= run[23];
always @ (*) start = ~prestart & run[23]; // __/``` posedge detector
always @ (posedge clk)
if (start) begin
pointer <= 0;
timer <= 0; // initial load
end else begin
if (timer == 0) begin
timer <= limit;
pointer <= pointer + 1;
end else begin
timer = timer - 1;
end
end
assign drv = pointer[0];
endmodule
|
module test(
input CLK_IN,
output [7:0] LEDS,
output [7:0] DEBUG,
output reg WS,
output OPEN,
input [2:0] COL,
inout [3:0] ROW,
input [3:0] SW
);
localparam CLKDIV = 20;
wire [7:0] BRT;
wire CLK; (* BUFG = "clk" *)
reg RESET = 1;
wire [255:0] W;
reg [255:0] W2 = 256'b0;
wire WS_asic;
wire ERROR;
reg [8:0] startup = 0;
reg [CLKDIV:0] counter = 0;
wire [3:0] ROW_asic;
custom challenge (
.RESET(SW[0]),
.CLK(CLK),
.COL(COL),
.ROW(ROW_asic),
.OPEN(OPEN),
.W(W),
.DEBUG(DEBUG[6:0])
);
ws2812b display (
.RESET(RESET),
.W(W2),
.CLK50(CLK_IN),
.WS(WS_asic),
// .DEBUG(DEBUG[7:0])
.OPENER(OPENER),
.ERROR(ERROR)
);
sr_timer #(200) success (
.S(OPEN),
.R(RESET),
.CLK(CLK),
.OUT(OPENER)
);
keypad keypad (
.COL(COL),
.ROW(ROW),
.ROW_asic(ROW_asic),
.ERROR(ERROR)
);
always @(posedge CLK_IN) begin
counter <= counter + 1;
end
wire CLK2;
assign CLK = counter[CLKDIV-1];
assign CLK2 = counter[CLKDIV-3];
always @(negedge CLK2) begin
W2 <= W;
end
always @(posedge CLK_IN)
if (startup < 8'hffff) startup <= startup + 1; // count to 255d, then stop
else RESET <= 0; // deassert reset at terminal count
assign LEDS = DEBUG | {8{OPENER}};
assign DEBUG[7] = WS;
always @(*) WS = WS_asic;
endmodule
|
module sky130_fd_sc_lp__nand4b (
//# {{data|Data Signals}}
input A_N ,
input B ,
input C ,
input D ,
output Y ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
|
module sky130_fd_sc_hs__udp_dff$P_pp$sN (
Q ,
D ,
CLK ,
SLEEP_B ,
NOTIFIER
);
output Q ;
input D ;
input CLK ;
input SLEEP_B ;
input NOTIFIER;
endmodule
|
module B_SPI_HFC_Master_v0_1(
input wire reset, /* System Reset */
input wire clock, /* User Supplied clock = 2x bitrate of output */
input wire miso, /* SPI MISO input */
input wire rde, /* RX Data effective */
output reg mosi, /* SPI MOSI output */
output reg tde, /* TX Data effective */
output reg sclk, /* SPI SCLK output */
output reg ss, /* SPI SS output */
output wire tx_interpt, /* Interrupt output */
output wire rx_interpt, /* Interrupt output */
output wire rx_drq, /* RX DMA request */
output wire tx_drq /* TX DMA request */
);
localparam SPIM_MSB_FIRST = 1'b0;
localparam SPIM_LSB_FIRST = 1'b1;
parameter [0:0] ShiftDir = SPIM_MSB_FIRST;
parameter [6:0] NumberOfDataBits = 7'd8; /* set to 2-16 bits only. Default is 8 bits */
parameter [0:0] HighSpeedMode = 1'b0;
parameter [0:0] ModeCPHA = 1'b0; /* Default is rising edge mode */
parameter [0:0] ModePOL = 1'b0; /* Default is rising edge mode */
wire clk_fin;
cy_psoc3_udb_clock_enable_v1_0 #(.sync_mode(`TRUE))
ClkEn (
.clock_in(clock),
.enable(1'b1),
.clock_out(clk_fin)
);
localparam [6:0] BitCntPeriod = (NumberOfDataBits << 1) - 1;
wire [6:0] count;
wire cnt_tc;
reg cnt_enable;
cy_psoc3_count7 #(.cy_period(BitCntPeriod), .cy_route_ld(0), .cy_route_en(1))
BitCounter(
/* input */ .clock(clk_fin),
/* input */ .reset(reset),
/* input */ .load(1'b0),
/* input */ .enable(cnt_enable),
/* output [06:00] */ .count(count),
/* output */ .tc(cnt_tc)
);
wire dpcounter_one = (count[4:0] == 5'h1);
>>>>>>> origin/spim
reg dpcounter_one_reg;
<<<<<<< HEAD
generate
if (HighSpeedMode == 1 && ModeCPHA == 1) begin
assign load_rx_data = (rde == 1'b1) ? 1'b0 : dpcounter_one_reg;
end
else begin
assign load_rx_data = (rde == 1'b1) ? 1'b0 : dpcounter_one;
end
endgenerate
assign miso_to_dp = miso;
assign mosi_after_ld = so_send | so_send_reg;
assign mosi = (HighSpeedMode == 1) ? mosi_fin : mosi_reg;
assign mosi_fin = (ModeCPHA == 1) ? mosi_cpha_1 : mosi_cpha_0;
assign so_send = (state == SPIM_STATE_SEND_TX_DATA) ? mosi_from_dp : 1'b0;
assign mosi_cpha_0 = (state == SPIM_STATE_SPI_DONE || ss) ? 1'b0 : mosi_hs_reg;
assign mosi_cpha_1 = ss ? 1'b0 : mosi_hs_reg;
assign pre_mosi = ((count[4:0] == BitCntPeriod) || (count[4:0] == (BitCntPeriod - 1))) ?
mosi_pre_reg | mosi_reg : mosi_reg;
assign dpcounter_zero = (count[4:0] == 5'h0);
assign dpcounter_one = (count[4:0] == 5'h01);
=======
wire mosi_from_dp;
reg mosi_from_dp_reg;
>>>>>>> origin/spim
wire dpMOSI_fifo_not_full;
wire dpMOSI_fifo_empty;
wire dpMISO_fifo_not_empty;
wire dpMISO_fifo_full;
reg rde_reg;
generate
if (HighSpeedMode) begin
always @(posedge clk_fin) begin
dpcounter_one_reg <= dpcounter_one;
mosi_from_dp_reg <= mosi_from_dp;
end
end
endgenerate
wire load_rx_data = rde_reg ? 1'b0 : (HighSpeedMode == 1 && ModeCPHA == 1) ? dpcounter_one_reg : dpcounter_one;
reg ld_ident;
reg is_spi_done;
/* State Machine state names */
localparam SPIM_STATE_IDLE = 3'h0;
localparam SPIM_STATE_LOAD_TX_DATA = 3'h1;
localparam SPIM_STATE_SEND_TX_DATA = 3'h2;
localparam SPIM_STATE_CAPT_RX_DATA = 3'h3;
localparam SPIM_STATE_SHFT_N_LD_TX_DATA = 3'h4;
localparam SPIM_STATE_SPI_DONE = 3'h5;
localparam SPIM_STATE_WAIT = 3'h6;
localparam SPIM_STATE_SEND_TX_DATA_2 = 3'h7;
reg [2:0] state;
generate
if (ModeCPHA == 1 && HighSpeedMode) begin
/* State Logic */
always @(posedge clk_fin) begin
if (reset) begin
state <= SPIM_STATE_IDLE;
end
else begin
case (state)
SPIM_STATE_IDLE: begin
ss <= 1'b1;
cnt_enable <= 1'b0;
sclk <= ModePOL;
tde <= dpMOSI_fifo_empty;
rde_reg <= rde;
state <= (dpMOSI_fifo_empty && rde_reg) ? SPIM_STATE_IDLE : SPIM_STATE_LOAD_TX_DATA;
end
SPIM_STATE_LOAD_TX_DATA: begin// 15
cnt_enable <= 1'b1;
ss <= 1'b0;
state <= SPIM_STATE_WAIT;
end
SPIM_STATE_WAIT: begin // 14
mosi <= mosi_from_dp;
sclk <= ~ModePOL;
state <= SPIM_STATE_SEND_TX_DATA;
end
SPIM_STATE_SEND_TX_DATA: begin // 13
sclk <= ModePOL;
rde_reg <= rde;
if (dpcounter_one && is_spi_done) begin
cnt_enable <= 1'b0;
state <= SPIM_STATE_SPI_DONE;
end
else begin
state <= SPIM_STATE_CAPT_RX_DATA;
end
end
SPIM_STATE_CAPT_RX_DATA: begin // 12
mosi <= mosi_from_dp_reg;
sclk <= ~ModePOL;
if (count[4:0] != 5'h04) begin
state <= SPIM_STATE_SEND_TX_DATA;
end
else if (!dpMOSI_fifo_empty) begin
state <= SPIM_STATE_SHFT_N_LD_TX_DATA;
end
else begin
<<<<<<< HEAD
if (!dpMOSI_fifo_empty) begin
state <= SPIM_STATE_SHFT_N_LD_TX_DATA;
end
else begin
is_spi_done <= 1'b1;
state <= SPIM_STATE_SEND_TX_DATA;
end
end
end
SPIM_STATE_SHFT_N_LD_TX_DATA: begin
state <= SPIM_STATE_CAPT_RX_DATA;
end
SPIM_STATE_SPI_DONE: begin
is_spi_done <= 1'b0;
state <= SPIM_STATE_IDLE;
end
default: begin
state <= SPIM_STATE_IDLE;
end
endcase
end
else begin
state <= SPIM_STATE_IDLE;
end
end /* END of CPHA == 1 State Machine implementation */
/* Output Logic */
always @(posedge clk_fin) begin
case (state)
SPIM_STATE_IDLE: begin
tde <= dpMOSI_fifo_empty;
ss <= 1'b1;
cnt_enable <= 1'b0;
mosi_pre_reg <= 1'b0;
sclk <= pol_supprt;
end
SPIM_STATE_LOAD_TX_DATA: begin
cnt_enable <= 1'b1;
ss <= 1'b0;
mosi_hs_reg <= mosi_from_dp;
end
SPIM_STATE_WAIT: begin
mosi_hs_reg <= mosi_from_dp;
mosi_pre_reg <= mosi_from_dp;
sclk <= ~pol_supprt;
end
SPIM_STATE_SEND_TX_DATA: begin
if (count[4:0] != 5'h01) begin
sclk <= pol_supprt;
mosi_pre_reg <= mosi_from_dp;
end
else begin
sclk <= pol_supprt;
if (!ld_ident) begin
mosi_pre_reg <= mosi_from_dp;
end
if (is_spi_done) begin
cnt_enable <= 1'b0;
end
end
end
SPIM_STATE_CAPT_RX_DATA: begin
mosi_hs_reg <= mosi_from_dp_reg;
sclk <= ~pol_supprt;
end
SPIM_STATE_SHFT_N_LD_TX_DATA: begin
ld_ident <= 1'b1;
sclk <= pol_supprt;
end
SPIM_STATE_SPI_DONE: begin
mosi_pre_reg <= 1'b0;
cnt_enable <= 1'b0;
sclk <= pol_supprt;
end
default: begin
ss <= 1'b1;
cnt_enable <= 1'b0;
mosi_pre_reg <= 1'b0;
sclk <= pol_supprt;
ld_ident <= 1'b0;
end
endcase
end
end
else if (ModeCPHA == 1 && !HighSpeedMode) begin
/* "CPHA == 1" State Machine implementation */
/* State Logic */
always @(posedge clk_fin) begin
/*
mosi_pre_reg <= 1'b0;
so_send_reg <= 1'b0;
ld_ident <= 1'b0;
*/
if (!reset) begin
case (state)
SPIM_STATE_IDLE: begin
if (dpMOSI_fifo_empty && rde == 1'b1) begin
state <= SPIM_STATE_IDLE;
end
else begin
state <= SPIM_STATE_LOAD_TX_DATA;
end
end
SPIM_STATE_LOAD_TX_DATA: begin
state <= SPIM_STATE_SEND_TX_DATA;
end
=======
is_spi_done <= 1'b1;
state <= SPIM_STATE_SEND_TX_DATA;
end
end
SPIM_STATE_SHFT_N_LD_TX_DATA: begin
sclk <= ModePOL;
state <= SPIM_STATE_CAPT_RX_DATA;
end
SPIM_STATE_SPI_DONE: begin
cnt_enable <= 1'b0;
sclk <= ModePOL;
is_spi_done <= 1'b0;
state <= SPIM_STATE_IDLE;
end
default: begin
ss <= 1'b1;
cnt_enable <= 1'b0;
sclk <= ModePOL;
state <= SPIM_STATE_IDLE;
end
endcase
end
end
end
>>>>>>> origin/spim
else if (ModeCPHA == 1 && !HighSpeedMode) begin
always @(posedge clk_fin) begin
if (reset) begin
state <= SPIM_STATE_IDLE;
end
else begin
case (state)
SPIM_STATE_IDLE: begin
ss <= 1'b1;
cnt_enable <= 1'b0;
mosi <= 1'b0;
sclk <= ModePOL;
tde <= dpMOSI_fifo_empty;
rde_reg <= rde;
state <= (dpMOSI_fifo_empty && rde_reg) ? SPIM_STATE_IDLE : SPIM_STATE_LOAD_TX_DATA;
end
SPIM_STATE_LOAD_TX_DATA: begin // 15
cnt_enable <= 1'b1;
ss <= 1'b0;
sclk <= ModePOL;
state <= SPIM_STATE_SEND_TX_DATA;
end
SPIM_STATE_SEND_TX_DATA: begin // 14
sclk <= ~ModePOL;
mosi <= mosi_from_dp;
rde_reg <= rde;
state <= (count[4:0] == 5'h2 && !dpMOSI_fifo_empty) ? SPIM_STATE_SHFT_N_LD_TX_DATA : SPIM_STATE_CAPT_RX_DATA;
end
SPIM_STATE_CAPT_RX_DATA: begin // 13
sclk <= ModePOL;
if (!dpcounter_one) begin
state <= SPIM_STATE_SEND_TX_DATA;
end
else begin
cnt_enable <= 1'b0;
state <= SPIM_STATE_SPI_DONE;
end
end
SPIM_STATE_SHFT_N_LD_TX_DATA: begin
sclk <= ModePOL;
state <= SPIM_STATE_SEND_TX_DATA;
end
SPIM_STATE_SPI_DONE: begin
mosi <= 1'b0;
cnt_enable <= 1'b0;
sclk <= ModePOL;
state <= SPIM_STATE_IDLE;
end
default: begin
ss <= 1'b1;
cnt_enable <= 1'b0;
mosi <= 1'b0;
sclk <= ModePOL;
state <= SPIM_STATE_IDLE;
end
endcase
end
end
end
/* "CPHA == 0" State Machine implementation */
else if (ModeCPHA == 0 && HighSpeedMode) begin
always @(posedge clk_fin) begin
if (reset) begin
state <= SPIM_STATE_IDLE;
end
else begin
case (state)
SPIM_STATE_IDLE: begin
ss <= 1'b1;
cnt_enable <= 1'b0;
sclk <= ModePOL;
tde <= dpMOSI_fifo_empty;
rde_reg <= rde;
state <= (dpMOSI_fifo_empty && rde_reg) ? SPIM_STATE_IDLE : SPIM_STATE_LOAD_TX_DATA;
end
SPIM_STATE_LOAD_TX_DATA: begin
ss <= 1'b0;
sclk <= ModePOL;
state <= SPIM_STATE_SEND_TX_DATA_2;
end
SPIM_STATE_SEND_TX_DATA_2: begin
mosi <= mosi_from_dp;
state <= SPIM_STATE_WAIT;
end
SPIM_STATE_WAIT: begin // 15
cnt_enable <= 1'b1;
sclk <= ~ModePOL;
state <= SPIM_STATE_CAPT_RX_DATA;
end
SPIM_STATE_SEND_TX_DATA: begin // 13
if (dpcounter_one) begin
ld_ident <= 1'b0;
end
sclk <= ~ModePOL;
rde_reg <= rde;
state <= SPIM_STATE_CAPT_RX_DATA;
end
SPIM_STATE_CAPT_RX_DATA: begin // 14
mosi <= mosi_from_dp_reg;
sclk <= ModePOL;
if (count[4:0] == 5'h6 && !dpMOSI_fifo_empty) begin
state <= SPIM_STATE_SHFT_N_LD_TX_DATA;
end
else if ((count[4:0] == 5'h0 || count[4:0] == 5'h2) && !ld_ident) begin
state <= SPIM_STATE_SPI_DONE;
end
else begin
<<<<<<< HEAD
if (!dpMOSI_fifo_empty) begin
state <= SPIM_STATE_SHFT_N_LD_TX_DATA;
end
else begin
state <= SPIM_STATE_CAPT_RX_DATA;
end
end
end
SPIM_STATE_SHFT_N_LD_TX_DATA: begin
state <= SPIM_STATE_SEND_TX_DATA;
end
SPIM_STATE_SPI_DONE: begin
state <= SPIM_STATE_IDLE;
end
default: begin
state <= SPIM_STATE_IDLE;
end
endcase
end
else begin
state <= SPIM_STATE_IDLE;
end
end /* END of CPHA ==1 State Machine implementation */
/* Output Logic */
always @(posedge clk_fin) begin
case (state)
SPIM_STATE_IDLE: begin
tde <= dpMOSI_fifo_empty;
ss <= 1'b1;
cnt_enable <= 1'b0;
mosi_reg <= 1'b0;
sclk <= pol_supprt;
end
SPIM_STATE_LOAD_TX_DATA: begin
cnt_enable <= 1'b1;
ss <= 1'b0;
sclk <= pol_supprt;
end
SPIM_STATE_CAPT_RX_DATA: begin
if (count[4:0] != 5'h01) begin
sclk <= pol_supprt;
end
else begin
cnt_enable <= 1'b0;
sclk <= pol_supprt;
end
end
SPIM_STATE_SEND_TX_DATA: begin
sclk <= ~pol_supprt;
mosi_reg <= mosi_from_dp;
end
SPIM_STATE_SHFT_N_LD_TX_DATA: begin
sclk <= pol_supprt;
end
SPIM_STATE_SPI_DONE: begin
mosi_reg <= 1'b0;
cnt_enable <= 1'b0;
sclk <= pol_supprt;
end
default: begin
ss <= 1'b1;
cnt_enable <= 1'b0;
mosi_reg <= 1'b0;
sclk <= pol_supprt;
end
endcase
end
end
/* "CPHA == 0" State Machine implementation */
else if (ModeCPHA != 1 && HighSpeedMode) begin
always @(posedge clk_fin) begin
mosi_reg <= mosi_pre_reg;
end
/* State Logic */
always @(posedge clk_fin) begin
// so_send_reg <= 1'b0;
if (!reset) begin
case (state)
SPIM_STATE_IDLE: begin
if (dpMOSI_fifo_empty && rde == 1'b1) begin
state <= SPIM_STATE_IDLE;
end
else begin
state <= SPIM_STATE_LOAD_TX_DATA;
end
end
SPIM_STATE_LOAD_TX_DATA: begin
state <= SPIM_STATE_SEND_TX_DATA_2;
end
SPIM_STATE_SEND_TX_DATA_2: begin
state <= SPIM_STATE_WAIT;
end
SPIM_STATE_WAIT: begin
state <= SPIM_STATE_CAPT_RX_DATA;
end
SPIM_STATE_SEND_TX_DATA: begin
state <= SPIM_STATE_CAPT_RX_DATA;
end
SPIM_STATE_CAPT_RX_DATA: begin
if (count[4:0] == 5'h06 && !dpMOSI_fifo_empty) begin
state <= SPIM_STATE_SHFT_N_LD_TX_DATA;
end
else if (count[4:0] != 5'h02) begin
state <= SPIM_STATE_SEND_TX_DATA;
end
else begin
if (!ld_ident) begin
state <= SPIM_STATE_SPI_DONE;
end
else begin
state <= SPIM_STATE_SEND_TX_DATA;
end
end
end
SPIM_STATE_SHFT_N_LD_TX_DATA: begin
state <= SPIM_STATE_CAPT_RX_DATA;
end
SPIM_STATE_SPI_DONE: begin
state <= SPIM_STATE_IDLE;
end
default: begin
state <= SPIM_STATE_IDLE;
end
endcase
end
else begin
state <= SPIM_STATE_IDLE;
end
end
/* Output Logic */
always @(posedge clk_fin) begin
case (state)
SPIM_STATE_IDLE: begin
tde <= dpMOSI_fifo_empty;
ss <= 1'b1;
cnt_enable <= 1'b0;
mosi_pre_reg <= 1'b0;
sclk <= pol_supprt;
end
SPIM_STATE_LOAD_TX_DATA: begin
ss <= 1'b0;
sclk <= pol_supprt;
end
SPIM_STATE_SEND_TX_DATA_2: begin
mosi_pre_reg <= mosi_from_dp;
mosi_hs_reg <= mosi_from_dp;
end
SPIM_STATE_WAIT: begin
cnt_enable <= 1'b1;
sclk <= ~pol_supprt;
end
SPIM_STATE_SEND_TX_DATA: begin
if (count[4:0] != 5'h01) begin
mosi_pre_reg <= mosi_from_dp;
end
else begin
ld_ident <= 1'b0;
end
sclk <= ~pol_supprt;
end
SPIM_STATE_CAPT_RX_DATA: begin
mosi_hs_reg <= mosi_from_dp_reg;
if (count[4:0] == 5'h0 && !ld_ident) begin
sclk <= pol_supprt;
mosi_pre_reg <= mosi_from_dp;
end
else if (count[4:0] != 5'h02) begin
sclk <= pol_supprt;
end
else begin
sclk <= pol_supprt;
if (!ld_ident) begin
mosi_pre_reg <= 1'b0;
end
end
end
SPIM_STATE_SHFT_N_LD_TX_DATA: begin
sclk <= ~pol_supprt;
ld_ident <= 1'b1;
mosi_pre_reg <= mosi_from_dp;
end
SPIM_STATE_SPI_DONE: begin
mosi_pre_reg <= 1'b0;
ss <= 1'b1;
cnt_enable <= 1'b0;
sclk <= pol_supprt;
end
default: begin
ss <= 1'b1;
mosi_pre_reg <= 1'b0;
cnt_enable <= 1'b0;
ld_ident <= 1'b0;
sclk <= pol_supprt;
end
endcase
end
end
/* END of "CPHA == 0" State Machine implementation */
else begin
/* State Logic */
always @(posedge clk_fin) begin
/*
mosi_pre_reg <= 1'b0;
so_send_reg <= 1'b0;
*/
if (!reset) begin
case (state)
SPIM_STATE_IDLE: begin
if (dpMOSI_fifo_empty && rde == 1'b1) begin
state <= SPIM_STATE_IDLE;
end
else begin
state <= SPIM_STATE_LOAD_TX_DATA;
end
end
SPIM_STATE_LOAD_TX_DATA: begin
state <= SPIM_STATE_SEND_TX_DATA_2;
end
SPIM_STATE_SEND_TX_DATA_2: begin
state <= SPIM_STATE_CAPT_RX_DATA;
end
SPIM_STATE_CAPT_RX_DATA: begin
if (count[4:0] != 5'h05) begin
state <= SPIM_STATE_SEND_TX_DATA;
end
else if (!dpMOSI_fifo_empty) begin
state <= SPIM_STATE_SHFT_N_LD_TX_DATA;
end
else begin
state <= SPIM_STATE_SEND_TX_DATA;
end
end
SPIM_STATE_SEND_TX_DATA: begin
if(count[4:0] != 5'h02) begin
state <= SPIM_STATE_CAPT_RX_DATA;
end
else begin
if (!ld_ident) begin
state <= SPIM_STATE_SPI_DONE;
end
else begin
state <= SPIM_STATE_CAPT_RX_DATA;
end
end
end
SPIM_STATE_SHFT_N_LD_TX_DATA: begin
state <= SPIM_STATE_CAPT_RX_DATA;
end
SPIM_STATE_SPI_DONE: begin
state <= SPIM_STATE_IDLE;
end
default: begin
state <= SPIM_STATE_IDLE;
end
endcase
end
else begin
state <= SPIM_STATE_IDLE;
end
end
/* Output Logic */
always @(posedge clk_fin) begin
case (state)
SPIM_STATE_IDLE: begin
tde <= dpMOSI_fifo_empty;
ss <= 1'b1;
cnt_enable <= 1'b0;
mosi_reg <= 1'b0;
sclk <= pol_supprt;
end
SPIM_STATE_LOAD_TX_DATA: begin
ss <= 1'b0;
sclk <= pol_supprt;
end
SPIM_STATE_SEND_TX_DATA_2: begin
mosi_reg <= mosi_from_dp;
end
SPIM_STATE_CAPT_RX_DATA: begin
cnt_enable <= 1'b1;
sclk <= ~pol_supprt;
end
=======
state <= SPIM_STATE_SEND_TX_DATA;
end
end
SPIM_STATE_SHFT_N_LD_TX_DATA: begin // 5
sclk <= ~ModePOL;
ld_ident <= 1'b1;
state <= SPIM_STATE_CAPT_RX_DATA;
end
SPIM_STATE_SPI_DONE: begin
ss <= 1'b1;
cnt_enable <= 1'b0;
sclk <= ModePOL;
state <= SPIM_STATE_IDLE;
end
default: begin
ss <= 1'b1;
cnt_enable <= 1'b0;
ld_ident <= 1'b0;
sclk <= ModePOL;
state <= SPIM_STATE_IDLE;
end
endcase
end
end
end
>>>>>>> origin/spim
else begin
always @(posedge clk_fin) begin
if (reset) begin
state <= SPIM_STATE_IDLE;
end
else begin
case (state)
SPIM_STATE_IDLE: begin
ss <= 1'b1;
cnt_enable <= 1'b0;
mosi <= 1'b0;
sclk <= ModePOL;
tde <= dpMOSI_fifo_empty;
rde_reg <= rde;
state <= (dpMOSI_fifo_empty && rde_reg) ? SPIM_STATE_IDLE : SPIM_STATE_LOAD_TX_DATA;
end
SPIM_STATE_LOAD_TX_DATA: begin
ss <= 1'b0;
sclk <= ModePOL;
state <= SPIM_STATE_SEND_TX_DATA_2;
end
SPIM_STATE_SEND_TX_DATA_2: begin
mosi <= mosi_from_dp;
state <= SPIM_STATE_CAPT_RX_DATA;
end
SPIM_STATE_CAPT_RX_DATA: begin // 15
cnt_enable <= 1'b1;
sclk <= ~ModePOL;
state <= (count[4:0] == 5'h5 && !dpMOSI_fifo_empty) ? SPIM_STATE_SHFT_N_LD_TX_DATA : SPIM_STATE_SEND_TX_DATA;
end
SPIM_STATE_SEND_TX_DATA: begin // 14
sclk <= ModePOL;
rde_reg <= rde;
if (count[4:0] == 5'h2 && !ld_ident) begin
mosi <= 1'b0;
state <= SPIM_STATE_SPI_DONE;
end
else begin
if (count[4:0] == 5'h2) begin
ld_ident <= 1'b0;
end
mosi <= mosi_from_dp;
state <= SPIM_STATE_CAPT_RX_DATA;
end
end
SPIM_STATE_SHFT_N_LD_TX_DATA: begin // 4
sclk <= ModePOL;
ld_ident <= 1'b1;
mosi <= mosi_from_dp;
state <= SPIM_STATE_CAPT_RX_DATA;
end
SPIM_STATE_SPI_DONE: begin
mosi <= 1'b0;
ss <= 1'b1;
cnt_enable <= 1'b0;
sclk <= ModePOL;
state <= SPIM_STATE_IDLE;
end
default: begin
ss <= 1'b1;
mosi <= 1'b0;
cnt_enable <= 1'b0;
ld_ident <= 1'b0;
sclk <= ModePOL;
state <= SPIM_STATE_IDLE;
end
endcase
end
end
end
endgenerate
/* Status Register bits */
localparam SPIM_STS_SPI_DONE_BIT = 3'd0;
localparam SPIM_STS_TX_FIFO_EMPTY_BIT = 3'd1;
localparam SPIM_STS_TX_FIFO_NOT_FULL_BIT = 3'd2;
localparam SPIM_STS_BYTE_COMPLETE_BIT = 3'd3;
localparam SPIM_STS_SPI_IDLE_BIT = 3'd4;
wire [6:0] tx_status;
assign tx_status[SPIM_STS_SPI_DONE_BIT] = (state == SPIM_STATE_SPI_DONE);
assign tx_status[SPIM_STS_TX_FIFO_EMPTY_BIT] = dpMOSI_fifo_empty;
assign tx_status[SPIM_STS_TX_FIFO_NOT_FULL_BIT] = dpMOSI_fifo_not_full;
assign tx_status[SPIM_STS_BYTE_COMPLETE_BIT] = dpcounter_one;
assign tx_status[SPIM_STS_SPI_IDLE_BIT] = (state == SPIM_STATE_IDLE);
assign tx_status[6:5] = 2'h0;
assign tx_drq = dpMOSI_fifo_not_full;
cy_psoc3_statusi #(.cy_force_order(1), .cy_md_select(7'h09), .cy_int_mask(7'h00))
TxStsReg(
/* input */ .clock(clk_fin),
/* input [06:00] */ .status(tx_status),
/* output */ .interrupt(tx_interpt)
);
localparam SPIM_STS_RX_FIFO_FULL_BIT = 3'd4;
localparam SPIM_STS_RX_FIFO_NOT_EMPTY_BIT = 3'd5;
localparam SPIM_STS_RX_FIFO_OVERRUN_BIT = 3'd6;
wire [6:0] rx_status;
assign rx_status[SPIM_STS_RX_FIFO_FULL_BIT] = dpMISO_fifo_full;
assign rx_status[SPIM_STS_RX_FIFO_NOT_EMPTY_BIT] = dpMISO_fifo_not_empty;
assign rx_status[SPIM_STS_RX_FIFO_OVERRUN_BIT] = dpcounter_one & dpMISO_fifo_full;
assign rx_status[3:0] = 4'h0;
assign rx_drq = dpMISO_fifo_not_empty;
cy_psoc3_statusi #(.cy_force_order(1), .cy_md_select(7'h40), .cy_int_mask(7'h00))
RxStsReg(
/* input */ .clock(clk_fin),
/* input [06:00] */ .status(rx_status),
/* output */ .interrupt(rx_interpt)
);
localparam SR8 = 8'd8;
localparam [2:0] dpMsbVal = (NumberOfDataBits % 8) - 3'b1;
localparam [7:0] dpMISOMask = (NumberOfDataBits == 8 || NumberOfDataBits == 16) ? 8'b1111_1111 :
(NumberOfDataBits == 7 || NumberOfDataBits == 15) ? 8'b0111_1111 :
(NumberOfDataBits == 6 || NumberOfDataBits == 14) ? 8'b0011_1111 :
(NumberOfDataBits == 5 || NumberOfDataBits == 13) ? 8'b0001_1111 :
(NumberOfDataBits == 4 || NumberOfDataBits == 12) ? 8'b0000_1111 :
(NumberOfDataBits == 3 || NumberOfDataBits == 11) ? 8'b0000_0111 :
(NumberOfDataBits == 2 || NumberOfDataBits == 10) ? 8'b0000_0011 :
(NumberOfDataBits == 9) ? 8'b0000_0001 : 8'b1111_1111;
localparam [1:0] dynShiftDir = (ShiftDir == SPIM_MSB_FIRST) ? 2'd1 : 2'd2;
localparam f1_ld_src = (ModeCPHA == 1) ? `SC_FIFO1_ALU : `SC_FIFO1__A1;
generate
if (NumberOfDataBits <= SR8) begin: sR8
localparam dp8_cfg = {
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
`CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CFGRAM0: IDLE */
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
`CS_SHFT_OP_PASS, `CS_A0_SRC___F0, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CFGRAM1: LOAD F0 to A0 */
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
dynShiftDir, `CS_A0_SRC__ALU, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CFGRAM2: Change Shift Out */
`CS_ALU_OP_PASS, `CS_SRCA_A1, `CS_SRCB_D0,
dynShiftDir, `CS_A0_SRC_NONE, `CS_A1_SRC__ALU,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CFGRAM3: Capture Shift In */
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
dynShiftDir, `CS_A0_SRC___F0, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CFGRAM4: LDSHIFT */
`CS_ALU_OP_PASS, `CS_SRCA_A1, `CS_SRCB_D0,
dynShiftDir, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CFGRAM5: END */
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
dynShiftDir, `CS_A0_SRC__ALU, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CFGRAM6: Change Shift Out */
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
dynShiftDir, `CS_A0_SRC__ALU, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CFGRAM7: */
dpMISOMask, 8'h00, /*CFG9: */
8'hFF, 8'hFF, /*CFG11-10: */
`SC_CMPB_A1_D1, `SC_CMPA_A1_D1, `SC_CI_B_ARITH,
`SC_CI_A_ARITH, `SC_C1_MASK_DSBL, `SC_C0_MASK_DSBL,
`SC_A_MASK_ENBL, `SC_DEF_SI_0, `SC_SI_B_DEFSI,
`SC_SI_A_ROUTE, /*CFG13-12: */
`SC_A0_SRC_ACC, ShiftDir, 1'h0,
1'h0, f1_ld_src, `SC_FIFO0_BUS,
`SC_MSB_ENBL, dpMsbVal, `SC_MSB_NOCHN,
`SC_FB_NOCHN, `SC_CMP1_NOCHN,
`SC_CMP0_NOCHN, /*CFG15-14: */
3'h00, `SC_FIFO_SYNC_NONE, 6'h00, `SC_FIFO_CLK__DP,`SC_FIFO_CAP_AX,
`SC_FIFO_LEVEL,`SC_FIFO_ASYNC,`SC_EXTCRC_DSBL,
`SC_WRK16CAT_DSBL /*CFG17-16: */
};
cy_psoc3_dp8 #(.cy_dpconfig_a(dp8_cfg))
Dp(
/* input */ .clk(clk_fin),
/* input */ .reset(reset),
/* input [02:00] */ .cs_addr(state),
/* input */ .route_si(miso),
/* input */ .route_ci(1'b0),
/* input */ .f0_load(1'b0),
/* input */ .f1_load(load_rx_data),
/* input */ .d0_load(1'b0),
/* input */ .d1_load(1'b0),
/* output */ .ce0(),
/* output */ .cl0(),
/* output */ .z0(),
/* output */ .ff0(),
/* output */ .ce1(),
/* output */ .cl1(),
/* output */ .z1(),
/* output */ .ff1(),
/* output */ .ov_msb(),
/* output */ .co_msb(),
/* output */ .cmsb(),
/* output */ .so(mosi_from_dp),
/* output */ .f0_bus_stat(dpMOSI_fifo_not_full),
/* output */ .f0_blk_stat(dpMOSI_fifo_empty),
/* output */ .f1_bus_stat(dpMISO_fifo_not_empty),
/* output */ .f1_blk_stat(dpMISO_fifo_full)
);
end /* NumberOfDataBits <= SR8 */
else begin : sR16 /* NumberOfDataBits > 8 */
localparam [1:0] dp16MSBSIChoice = (ShiftDir == SPIM_MSB_FIRST) ? `SC_SI_A_CHAIN : `SC_SI_A_ROUTE;
localparam [1:0] dp16LSBSIChoice = (ShiftDir == SPIM_MSB_FIRST) ? `SC_SI_A_ROUTE : `SC_SI_A_CHAIN;
localparam dp16_lsb_cfg = {
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
`CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CFGRAM0: IDLE */
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
`CS_SHFT_OP_PASS, `CS_A0_SRC___F0, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CFGRAM1: LOAD F0 to A0 */
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
dynShiftDir, `CS_A0_SRC__ALU, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CFGRAM2: Change Shift Out */
`CS_ALU_OP_PASS, `CS_SRCA_A1, `CS_SRCB_D0,
dynShiftDir, `CS_A0_SRC_NONE, `CS_A1_SRC__ALU,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CFGRAM3: Capture Shift In */
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
dynShiftDir, `CS_A0_SRC___F0, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CFGRAM4: LDSHIFT */
`CS_ALU_OP_PASS, `CS_SRCA_A1, `CS_SRCB_D0,
dynShiftDir, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CFGRAM5: END */
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
dynShiftDir, `CS_A0_SRC__ALU, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CFGRAM6: Change Shift Out */
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
dynShiftDir, `CS_A0_SRC__ALU, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CFGRAM7: */
8'hFF, 8'h00, /*CFG9: */
8'hFF, 8'hFF, /*CFG11-10: */
`SC_CMPB_A1_D1, `SC_CMPA_A1_D1, `SC_CI_B_ARITH,
`SC_CI_A_ARITH, `SC_C1_MASK_DSBL, `SC_C0_MASK_DSBL,
`SC_A_MASK_DSBL, `SC_DEF_SI_0, `SC_SI_B_DEFSI,
dp16LSBSIChoice, /*CFG13-12: */
`SC_A0_SRC_ACC, ShiftDir, 1'h0,
1'h0, f1_ld_src, `SC_FIFO0_BUS,
`SC_MSB_DSBL, `SC_MSB_BIT7, `SC_MSB_NOCHN,
`SC_FB_NOCHN, `SC_CMP1_NOCHN,
`SC_CMP0_NOCHN, /*CFG15-14: */
3'h00, `SC_FIFO_SYNC_NONE, 6'h00, `SC_FIFO_CLK__DP,`SC_FIFO_CAP_AX,
`SC_FIFO_LEVEL,`SC_FIFO_ASYNC,`SC_EXTCRC_DSBL,
`SC_WRK16CAT_DSBL /*CFG17-16: */
};
localparam dp16_msb_cfg = {
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
`CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CFGRAM0: IDLE */
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
`CS_SHFT_OP_PASS, `CS_A0_SRC___F0, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CFGRAM1: LOAD F0 to A0 */
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
dynShiftDir, `CS_A0_SRC__ALU, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CFGRAM2: Change Shift Out */
`CS_ALU_OP_PASS, `CS_SRCA_A1, `CS_SRCB_D0,
dynShiftDir, `CS_A0_SRC_NONE, `CS_A1_SRC__ALU,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CFGRAM3: Capture Shift In */
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
dynShiftDir, `CS_A0_SRC___F0, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CFGRAM4: LDSHIFT */
`CS_ALU_OP_PASS, `CS_SRCA_A1, `CS_SRCB_D0,
dynShiftDir, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CFGRAM5: END */
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
dynShiftDir, `CS_A0_SRC__ALU, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CFGRAM6: Change Shift Out */
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
dynShiftDir, `CS_A0_SRC__ALU, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CFGRAM7: */
dpMISOMask, 8'h00, /*CFG9: */
8'hFF, 8'hFF, /*CFG11-10: */
`SC_CMPB_A1_D1, `SC_CMPA_A1_D1, `SC_CI_B_ARITH,
`SC_CI_A_ARITH, `SC_C1_MASK_DSBL, `SC_C0_MASK_DSBL,
`SC_A_MASK_ENBL, `SC_DEF_SI_0, `SC_SI_B_DEFSI,
dp16MSBSIChoice, /*CFG13-12: */
`SC_A0_SRC_ACC, ShiftDir, 1'h0,
1'h0, f1_ld_src, `SC_FIFO0_BUS,
`SC_MSB_ENBL, dpMsbVal, `SC_MSB_NOCHN,
`SC_FB_NOCHN, `SC_CMP1_NOCHN,
`SC_CMP0_NOCHN, /*CFG15-14: */
3'h00, `SC_FIFO_SYNC_NONE, 6'h00, `SC_FIFO_CLK__DP,`SC_FIFO_CAP_AX,
`SC_FIFO_LEVEL,`SC_FIFO_ASYNC,`SC_EXTCRC_DSBL,
`SC_WRK16CAT_DSBL /*CFG17-16: */
};
wire mosi_from_dpL;
wire mosi_from_dpR;
wire nc1, nc2, nc3, nc4;
cy_psoc3_dp16 #(.cy_dpconfig_a(dp16_lsb_cfg), .cy_dpconfig_b(dp16_msb_cfg))
Dp(
/* input */ .clk(clk_fin),
/* input */ .reset(reset),
/* input [02:00] */ .cs_addr(state),
/* input */ .route_si(miso),
/* input */ .route_ci(1'b0),
/* input */ .f0_load(1'b0),
/* input */ .f1_load(load_rx_data),
/* input */ .d0_load(1'b0),
/* input */ .d1_load(1'b0),
/* output */ .ce0(),
/* output */ .cl0(),
/* output */ .z0(),
/* output */ .ff0(),
/* output */ .ce1(),
/* output */ .cl1(),
/* output */ .z1(),
/* output */ .ff1(),
/* output */ .ov_msb(),
/* output */ .co_msb(),
/* output */ .cmsb(),
/* output */ .so({mosi_from_dpL,mosi_from_dpR}),
/* output */ .f0_bus_stat({dpMOSI_fifo_not_full, nc1}),
/* output */ .f0_blk_stat({dpMOSI_fifo_empty, nc2}),
/* output */ .f1_bus_stat({dpMISO_fifo_not_empty, nc3}),
/* output */ .f1_blk_stat({dpMISO_fifo_full, nc4})
);
assign mosi_from_dp = (ShiftDir == SPIM_MSB_FIRST) ? mosi_from_dpL : mosi_from_dpR;
end /* NumberOfDataBits <= sR16 */
endgenerate
endmodule
|
module sky130_fd_sc_hs__o41ai (
Y ,
A1,
A2,
A3,
A4,
B1
);
output Y ;
input A1;
input A2;
input A3;
input A4;
input B1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
endmodule
|
module sky130_fd_sc_hs__dlrtp (
VPWR ,
VGND ,
Q ,
RESET_B,
D ,
GATE
);
// Module ports
input VPWR ;
input VGND ;
output Q ;
input RESET_B;
input D ;
input GATE ;
// Local signals
wire RESET ;
reg notifier ;
wire D_delayed ;
wire GATE_delayed ;
wire RESET_delayed ;
wire RESET_B_delayed;
wire buf_Q ;
wire awake ;
wire cond0 ;
wire cond1 ;
// Name Output Other arguments
not not0 (RESET , RESET_B_delayed );
sky130_fd_sc_hs__u_dl_p_r_no_pg u_dl_p_r_no_pg0 (buf_Q , D_delayed, GATE_delayed, RESET, notifier, VPWR, VGND);
assign awake = ( VPWR === 1'b1 );
assign cond0 = ( awake && ( RESET_B_delayed === 1'b1 ) );
assign cond1 = ( awake && ( RESET_B === 1'b1 ) );
buf buf0 (Q , buf_Q );
endmodule
|
module testbench;
// Inputs
reg clk;
reg rst;
reg piso1;
reg piso2;
reg piso3;
reg piso4;
reg S1;
reg B2;
reg S2;
reg B3;
reg S3;
reg B4;
// Outputs
wire [7:0] DISPLAY;
wire [3:0] ANODES;
/*wire [1:0] piso;
wire [1:0] accion;
wire puertas;
wire [3:0] contador_seg;
wire [3:0] memoria_m;*/
// Instantiate the Unit Under Test (UUT)
maquina_estados uut (
.clk(clk),
.rst(rst),
.piso1(piso1),
.piso2(piso2),
.piso3(piso3),
.piso4(piso4),
.S1(S1),
.B2(B2),
.S2(S2),
.B3(B3),
.S3(S3),
.B4(B4),
.DISPLAY(DISPLAY),
.ANODES(ANODES),
/* .piso(piso),
.accion(accion),
.puertas(puertas),
.contador_seg(contador_seg),
.memoria_m(memoria_m)*/
);
initial begin
// Initialize Inputs
clk = 0;
rst = 0;
piso1 = 0;
piso2 = 0;
piso3 = 0;
piso4 = 0;
S1 = 0;
B2 = 0;
S2 = 0;
B3 = 0;
S3 = 0;
B4 = 0;
// Wait 100 ns for global reset to finish
#100;
#10 rst = 1;
#10 rst = 0;
#10 piso2 = 1;
#10 piso2 = 0;
// Add stimulus here
end
always
begin
#1 clk <= ~clk;
end
// Add stimulus here
endmodule
|
module fetch (clk, stall, busy, pc, rw, access_size, enable, j_addr, jump, br_addr, branch);
parameter START_ADDR = 32'h8002_0000;
// input
input clk;
input stall;
input busy;
input [31:0] j_addr;
input jump;
input [31:0] br_addr;
input branch;
// output
output [31:0] pc;
output [2:0] access_size;
output rw; //1 is write, 0 is read
output enable;
// local
reg [31:0] pc_reg = 32'h8001_FFFC; // current address
reg [2:0] access_size_reg = 3'b000;
reg rw_reg = 1'b0;
reg enable_reg = 1'b1;
// comb
assign pc = pc_reg;
assign access_size = access_size_reg;
assign rw = rw_reg;
assign enable = enable_reg;
// proc
always @(posedge clk)
begin
if(stall != 1 & busy != 1)
begin
if(jump != 1 & branch != 1)
begin
pc_reg = pc_reg + 32'h0000_0004;
end
else if (branch == 1)
begin
pc_reg = br_addr;
end
else if(jump == 1)
begin
pc_reg = j_addr;
end
end
else if (branch == 1)
begin
pc_reg = br_addr;
end
else if(jump == 1)
begin
pc_reg = j_addr;
end
end
endmodule
|
module zybo_zynq_design_auto_pc_0 (
aclk,
aresetn,
s_axi_awid,
s_axi_awaddr,
s_axi_awlen,
s_axi_awsize,
s_axi_awburst,
s_axi_awlock,
s_axi_awcache,
s_axi_awprot,
s_axi_awqos,
s_axi_awvalid,
s_axi_awready,
s_axi_wid,
s_axi_wdata,
s_axi_wstrb,
s_axi_wlast,
s_axi_wvalid,
s_axi_wready,
s_axi_bid,
s_axi_bresp,
s_axi_bvalid,
s_axi_bready,
s_axi_arid,
s_axi_araddr,
s_axi_arlen,
s_axi_arsize,
s_axi_arburst,
s_axi_arlock,
s_axi_arcache,
s_axi_arprot,
s_axi_arqos,
s_axi_arvalid,
s_axi_arready,
s_axi_rid,
s_axi_rdata,
s_axi_rresp,
s_axi_rlast,
s_axi_rvalid,
s_axi_rready,
m_axi_awaddr,
m_axi_awprot,
m_axi_awvalid,
m_axi_awready,
m_axi_wdata,
m_axi_wstrb,
m_axi_wvalid,
m_axi_wready,
m_axi_bresp,
m_axi_bvalid,
m_axi_bready,
m_axi_araddr,
m_axi_arprot,
m_axi_arvalid,
m_axi_arready,
m_axi_rdata,
m_axi_rresp,
m_axi_rvalid,
m_axi_rready
);
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME CLK, FREQ_HZ 100000000, PHASE 0.000, CLK_DOMAIN zybo_zynq_design_processing_system7_0_0_FCLK_CLK0, ASSOCIATED_BUSIF S_AXI:M_AXI, ASSOCIATED_RESET ARESETN" *)
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLK CLK" *)
input wire aclk;
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME RST, POLARITY ACTIVE_LOW, TYPE INTERCONNECT" *)
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RST RST" *)
input wire aresetn;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWID" *)
input wire [11 : 0] s_axi_awid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWADDR" *)
input wire [31 : 0] s_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLEN" *)
input wire [3 : 0] s_axi_awlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWSIZE" *)
input wire [2 : 0] s_axi_awsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWBURST" *)
input wire [1 : 0] s_axi_awburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLOCK" *)
input wire [1 : 0] s_axi_awlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWCACHE" *)
input wire [3 : 0] s_axi_awcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWPROT" *)
input wire [2 : 0] s_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWQOS" *)
input wire [3 : 0] s_axi_awqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWVALID" *)
input wire s_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWREADY" *)
output wire s_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WID" *)
input wire [11 : 0] s_axi_wid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WDATA" *)
input wire [31 : 0] s_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WSTRB" *)
input wire [3 : 0] s_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WLAST" *)
input wire s_axi_wlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WVALID" *)
input wire s_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WREADY" *)
output wire s_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BID" *)
output wire [11 : 0] s_axi_bid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BRESP" *)
output wire [1 : 0] s_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BVALID" *)
output wire s_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BREADY" *)
input wire s_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARID" *)
input wire [11 : 0] s_axi_arid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARADDR" *)
input wire [31 : 0] s_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLEN" *)
input wire [3 : 0] s_axi_arlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARSIZE" *)
input wire [2 : 0] s_axi_arsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARBURST" *)
input wire [1 : 0] s_axi_arburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLOCK" *)
input wire [1 : 0] s_axi_arlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARCACHE" *)
input wire [3 : 0] s_axi_arcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARPROT" *)
input wire [2 : 0] s_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARQOS" *)
input wire [3 : 0] s_axi_arqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARVALID" *)
input wire s_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARREADY" *)
output wire s_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RID" *)
output wire [11 : 0] s_axi_rid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RDATA" *)
output wire [31 : 0] s_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RRESP" *)
output wire [1 : 0] s_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RLAST" *)
output wire s_axi_rlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RVALID" *)
output wire s_axi_rvalid;
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S_AXI, DATA_WIDTH 32, PROTOCOL AXI3, FREQ_HZ 100000000, ID_WIDTH 12, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 8, NUM_WRITE_OUTSTANDING 8, MAX_BURST_LENGTH 16, PHASE 0.000, CLK_DOMAIN zybo_zynq_design_processing_system7_0_0_FCLK_CLK0, NUM_READ_\
THREADS 4, NUM_WRITE_THREADS 4, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0" *)
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RREADY" *)
input wire s_axi_rready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWADDR" *)
output wire [31 : 0] m_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWPROT" *)
output wire [2 : 0] m_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWVALID" *)
output wire m_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWREADY" *)
input wire m_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WDATA" *)
output wire [31 : 0] m_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WSTRB" *)
output wire [3 : 0] m_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WVALID" *)
output wire m_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WREADY" *)
input wire m_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BRESP" *)
input wire [1 : 0] m_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BVALID" *)
input wire m_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BREADY" *)
output wire m_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARADDR" *)
output wire [31 : 0] m_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARPROT" *)
output wire [2 : 0] m_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARVALID" *)
output wire m_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARREADY" *)
input wire m_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RDATA" *)
input wire [31 : 0] m_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RRESP" *)
input wire [1 : 0] m_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RVALID" *)
input wire m_axi_rvalid;
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M_AXI, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 100000000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 8, NUM_WRITE_OUTSTANDING 8, MAX_BURST_LENGTH 1, PHASE 0.000, CLK_DOMAIN zybo_zynq_design_processing_system7_0_0_FCLK_CLK0, NUM_REA\
D_THREADS 4, NUM_WRITE_THREADS 4, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0" *)
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RREADY" *)
output wire m_axi_rready;
axi_protocol_converter_v2_1_17_axi_protocol_converter #(
.C_FAMILY("zynq"),
.C_M_AXI_PROTOCOL(2),
.C_S_AXI_PROTOCOL(1),
.C_IGNORE_ID(0),
.C_AXI_ID_WIDTH(12),
.C_AXI_ADDR_WIDTH(32),
.C_AXI_DATA_WIDTH(32),
.C_AXI_SUPPORTS_WRITE(1),
.C_AXI_SUPPORTS_READ(1),
.C_AXI_SUPPORTS_USER_SIGNALS(0),
.C_AXI_AWUSER_WIDTH(1),
.C_AXI_ARUSER_WIDTH(1),
.C_AXI_WUSER_WIDTH(1),
.C_AXI_RUSER_WIDTH(1),
.C_AXI_BUSER_WIDTH(1),
.C_TRANSLATION_MODE(2)
) inst (
.aclk(aclk),
.aresetn(aresetn),
.s_axi_awid(s_axi_awid),
.s_axi_awaddr(s_axi_awaddr),
.s_axi_awlen(s_axi_awlen),
.s_axi_awsize(s_axi_awsize),
.s_axi_awburst(s_axi_awburst),
.s_axi_awlock(s_axi_awlock),
.s_axi_awcache(s_axi_awcache),
.s_axi_awprot(s_axi_awprot),
.s_axi_awregion(4'H0),
.s_axi_awqos(s_axi_awqos),
.s_axi_awuser(1'H0),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_awready(s_axi_awready),
.s_axi_wid(s_axi_wid),
.s_axi_wdata(s_axi_wdata),
.s_axi_wstrb(s_axi_wstrb),
.s_axi_wlast(s_axi_wlast),
.s_axi_wuser(1'H0),
.s_axi_wvalid(s_axi_wvalid),
.s_axi_wready(s_axi_wready),
.s_axi_bid(s_axi_bid),
.s_axi_bresp(s_axi_bresp),
.s_axi_buser(),
.s_axi_bvalid(s_axi_bvalid),
.s_axi_bready(s_axi_bready),
.s_axi_arid(s_axi_arid),
.s_axi_araddr(s_axi_araddr),
.s_axi_arlen(s_axi_arlen),
.s_axi_arsize(s_axi_arsize),
.s_axi_arburst(s_axi_arburst),
.s_axi_arlock(s_axi_arlock),
.s_axi_arcache(s_axi_arcache),
.s_axi_arprot(s_axi_arprot),
.s_axi_arregion(4'H0),
.s_axi_arqos(s_axi_arqos),
.s_axi_aruser(1'H0),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_arready(s_axi_arready),
.s_axi_rid(s_axi_rid),
.s_axi_rdata(s_axi_rdata),
.s_axi_rresp(s_axi_rresp),
.s_axi_rlast(s_axi_rlast),
.s_axi_ruser(),
.s_axi_rvalid(s_axi_rvalid),
.s_axi_rready(s_axi_rready),
.m_axi_awid(),
.m_axi_awaddr(m_axi_awaddr),
.m_axi_awlen(),
.m_axi_awsize(),
.m_axi_awburst(),
.m_axi_awlock(),
.m_axi_awcache(),
.m_axi_awprot(m_axi_awprot),
.m_axi_awregion(),
.m_axi_awqos(),
.m_axi_awuser(),
.m_axi_awvalid(m_axi_awvalid),
.m_axi_awready(m_axi_awready),
.m_axi_wid(),
.m_axi_wdata(m_axi_wdata),
.m_axi_wstrb(m_axi_wstrb),
.m_axi_wlast(),
.m_axi_wuser(),
.m_axi_wvalid(m_axi_wvalid),
.m_axi_wready(m_axi_wready),
.m_axi_bid(12'H000),
.m_axi_bresp(m_axi_bresp),
.m_axi_buser(1'H0),
.m_axi_bvalid(m_axi_bvalid),
.m_axi_bready(m_axi_bready),
.m_axi_arid(),
.m_axi_araddr(m_axi_araddr),
.m_axi_arlen(),
.m_axi_arsize(),
.m_axi_arburst(),
.m_axi_arlock(),
.m_axi_arcache(),
.m_axi_arprot(m_axi_arprot),
.m_axi_arregion(),
.m_axi_arqos(),
.m_axi_aruser(),
.m_axi_arvalid(m_axi_arvalid),
.m_axi_arready(m_axi_arready),
.m_axi_rid(12'H000),
.m_axi_rdata(m_axi_rdata),
.m_axi_rresp(m_axi_rresp),
.m_axi_rlast(1'H1),
.m_axi_ruser(1'H0),
.m_axi_rvalid(m_axi_rvalid),
.m_axi_rready(m_axi_rready)
);
endmodule
|
module glitch_filter(
clk,
s_in,
s_out
);
input clk;
input s_in;
output s_out;
reg s_tmp;
reg [31:0]counter_low, counter_high;
initial begin
counter_low <= 0;
counter_high <= 0;
end
assign s_out = s_tmp;
always @(posedge clk) begin
if(s_in == 1'b0)
counter_low <= counter_low + 1;
else
counter_low <= 0;
end
always @(posedge clk) begin
if(s_in == 1'b1)
counter_high <= counter_high + 1;
else
counter_high <= 0;
end
always @(posedge clk) begin
if (counter_low == 4) s_tmp <= 0;
else if (counter_high == 4) s_tmp <= 1;
end
endmodule
|
module BTN_Anti_jitter(
// Outputs
button_out,
SW_OK,
// Inputs
clk,
button,
SW
);
input clk;
input [3:0] button;
input [7:0] SW;
output [3:0] button_out;
output [7:0] SW_OK;
glitch_filter G0(clk, button[0], button_out[0]);
glitch_filter G1(clk, button[1], button_out[1]);
glitch_filter G2(clk, button[2], button_out[2]);
glitch_filter G3(clk, button[3], button_out[3]);
glitch_filter G4(clk, SW[0], SW_OK[0]);
glitch_filter G5(clk, SW[1], SW_OK[1]);
glitch_filter G6(clk, SW[2], SW_OK[2]);
glitch_filter G7(clk, SW[3], SW_OK[3]);
glitch_filter G8(clk, SW[4], SW_OK[4]);
glitch_filter G9(clk, SW[5], SW_OK[5]);
glitch_filter G10(clk, SW[6], SW_OK[6]);
glitch_filter G11(clk, SW[7], SW_OK[7]);
endmodule
|
module display(
input clk, rst, mode,
input [31:0]disp_num,
output reg [7:0]seg,
output reg [3:0]anode
);
reg [26:0]tick;
reg [1:0]an;
reg [3:0]num;
reg t;
reg [7:0]dots;
initial begin
an <= 2'b00;
tick <= 0;
dots <= 0;
num <= 0;
end
always @(posedge clk or posedge rst) begin
if (rst == 1'b1) tick <= 0;
else tick <= tick+1;
end
always @(posedge tick[16] or posedge rst) begin
if (rst == 1'b1) an <= 0;
else an <= an + 1;
end
always @(an) begin
if (rst == 1'b1) begin
anode <= 4'b1111;
num <= 0;
dots <= 0;
end else begin
anode <= ~(4'b1<<an);
case(an)
2'b00: begin
num <= disp_num[3:0];
dots <= {disp_num[24], disp_num[0], disp_num[4], disp_num[16], disp_num[25], disp_num[17], disp_num[5], disp_num[12]};
end
2'b01: begin
num <= disp_num[7:4];
dots <= {disp_num[26], disp_num[1], disp_num[6], disp_num[18], disp_num[27], disp_num[19], disp_num[7], disp_num[13]};
end
2'b10: begin
num <= disp_num[11:8];
dots <= {disp_num[28], disp_num[2], disp_num[8], disp_num[20], disp_num[29], disp_num[21], disp_num[9], disp_num[14]};
end
2'b11: begin
num <= disp_num[15:12];
dots <= {disp_num[30], disp_num[3], disp_num[10], disp_num[22], disp_num[31], disp_num[23], disp_num[11], disp_num[15]};
end
default:;
endcase
end
end
always @(*) begin
if (rst == 1'b1) seg <= 0;
else begin
if(mode==1'b1) begin
case(num)
4'h0 : seg[7:0] <= 8'b10000001;
4'h1 : seg[7:0] <= 8'b11001111;
4'h2 : seg[7:0] <= 8'b10010010;
4'h3 : seg[7:0] <= 8'b10000110;
4'h4 : seg[7:0] <= 8'b11001100;
4'h5 : seg[7:0] <= 8'b10100100;
4'h6 : seg[7:0] <= 8'b10100000;
4'h7 : seg[7:0] <= 8'b10001111;
4'h8 : seg[7:0] <= 8'b10000000;
4'h9 : seg[7:0] <= 8'b10000100;
4'hA : seg[7:0] <= 8'b10001000;
4'hB : seg[7:0] <= 8'b11100000;
4'hC : seg[7:0] <= 8'b10110001;
4'hD : seg[7:0] <= 8'b11000010;
4'hE : seg[7:0] <= 8'b10110000;
default : seg[7:0] <= 8'b10111000;
endcase
end else seg[7:0] <= dots;
end
end
endmodule
|
module seven_seg_dev(
input wire [31:0] disp_num,
input wire clk,
input wire clr,
input wire [1:0]SW,
// input wire [1:0] Scanning,
output wire [7:0] SEGMENT,
output wire [3:0] AN
);
reg [31:0] number;
initial number <= 0;
display D0(clk, clr, SW[0], number, SEGMENT, AN);
always @(*) begin
case (SW)
2'b01 : number <= { 16'b0, disp_num[15:0] };
2'b11 : number <= { 16'b0, disp_num[31:16] };
default : number <= disp_num;
endcase
end
endmodule
|
module Regs(
clk,
rst,
reg_R_addr_A,
reg_R_addr_B,
reg_W_addr,
wdata,
reg_we,
rdata_A,
rdata_B
);
input clk, rst, reg_we;
input [4:0] reg_R_addr_A, reg_R_addr_B, reg_W_addr;
input [31:0] wdata;
output [31:0] rdata_A, rdata_B;
reg [31:0] register [1:31];// r1 - r31
integer i;
initial begin
for (i=1; i<32; i=i+1)
register[i] <= 0;//i;
end
assign rdata_A = (reg_R_addr_A == 0) ? 0 : register[reg_R_addr_A];//read
assign rdata_B = (reg_R_addr_B == 0) ? 0 : register[reg_R_addr_B];//read
always @(posedge clk or posedge rst) begin
if (rst==1) begin// reset
for (i=1; i<32; i=i+1)
register[i] <= 0;//i;
end else begin
if ((reg_W_addr != 0) && (reg_we == 1))
register[reg_W_addr] <= wdata;
end
end
endmodule
|
module alu(A, B, ALU_operation, res, zero, overflow );
input signed [31:0] A, B;
input [2:0] ALU_operation;
output [31:0] res;
output zero, overflow ;
wire [31:0] res_and, res_or, res_add, res_sub, res_nor, res_slt, res_xor, res_srl;
reg [31:0] res;
parameter one = 32'h00000001, zero_0 = 32'h00000000;
assign res_and = A&B;
assign res_or = A|B;
assign res_add = A+B;
assign res_sub = A-B;
assign res_nor=~(A | B);
assign res_slt =(A < B) ? one : zero_0;
assign res_xor = A^B;
assign res_srl = B>>1;
always @*
// (A or B or ALU_operation)
case (ALU_operation)
3'b000: res=res_and;
3'b001: res=res_or;
3'b010: res=res_add;
3'b110: res=res_sub;
3'b100: res=res_nor;
3'b111: res=res_slt;
3'b011: res=res_xor;
3'b101: res=res_srl;
default: res=res_add;
//32'hx;
endcase
assign zero = (res==0)? 1: 0;
endmodule
|
module clk_div(
input wire clk,
input wire rst,
input wire SW2,
output reg [31:0] clkdiv,
output wire Clk_CPU
);
initial clkdiv <= 0;
always @ (posedge clk or posedge rst) begin
if (rst) begin
clkdiv <= 0;
end else begin
clkdiv <= clkdiv + 1'b1;
end
end
assign Clk_CPU = SW2 ? clkdiv[22] : clkdiv[1];
endmodule
|
module seven_seg_Dev_IO(
input wire clk,
input wire rst,
input wire GPIOe0000000_we,
input wire [2:0] Test,
input wire [31:0] disp_cpudata,
input wire [31:0] Test_data0,
input wire [31:0] Test_data1,
input wire [31:0] Test_data2,
input wire [31:0] Test_data3,
input wire [31:0] Test_data4,
input wire [31:0] Test_data5,
input wire [31:0] Test_data6,
output reg [31:0] disp_num
);
always @(negedge clk or posedge rst) begin
if (rst) disp_num <= 32'h0000;
else begin
case (Test)
0: begin
if(GPIOe0000000_we) disp_num <= disp_cpudata;
else disp_num <= disp_num;
end
1: disp_num <= Test_data0;
2: disp_num <= Test_data1;
3: disp_num <= Test_data2;
4: disp_num <= Test_data3;
5: disp_num <= Test_data4;
6: disp_num <= Test_data5;
7: disp_num <= Test_data6;
endcase
end
end
endmodule
|
module MIO_BUS( input wire clk, input wire rst,
input wire [3:0] BTN,
input wire [7:0]SW,
input wire mem_w,
input wire [31:0] Cpu_data2bus,
input wire [31:0] addr_bus, //data from CPU
input wire [31:0] ram_data_out,
input wire [7:0] led_out,
input wire [31:0] counter_out,
input wire counter0_out,
input wire counter1_out,
input wire counter2_out,
output reg [31:0] Cpu_data4bus, //write to CPU
output reg [31:0] ram_data_in, //from CPU write to Memory
output reg [9: 0] ram_addr, //Memory Address signals
output reg data_ram_we,
output reg GPIOf0000000_we,
output reg GPIOe0000000_we,
output reg counter_we,
output reg [31: 0] Peripheral_in
);
reg [7:0] led_in;
always @(*) begin
data_ram_we = 0;
counter_we = 0;
GPIOe0000000_we = 0;
GPIOf0000000_we = 0;
ram_addr = 10'h0;
ram_data_in = 32'h0;
Peripheral_in = 32'h0;
Cpu_data4bus = 32'h0;
case(addr_bus[31:28])
4'h0: begin
data_ram_we = mem_w ;
ram_addr = addr_bus[11:2];
ram_data_in = Cpu_data2bus;
Cpu_data4bus = ram_data_out;
end
4'he: begin
GPIOf0000000_we = mem_w;
Peripheral_in = Cpu_data2bus;
Cpu_data4bus = counter_out;
end
4'hf: begin
if(addr_bus[2]) begin
counter_we = mem_w;
Peripheral_in = Cpu_data2bus;
Cpu_data4bus = counter_out;
end else begin
GPIOf0000000_we = mem_w;
Peripheral_in = Cpu_data2bus;
Cpu_data4bus = {counter0_out, counter1_out, counter2_out, 9'h00, led_out, BTN, SW};
end
end
endcase
end
endmodule
|
module Counter_x( input wire clk,
input wire rst,
input wire clk0,
input wire clk1,
input wire clk2,
input wire counter_we,
input wire [31:0]counter_val,
input wire [1:0] counter_ch,
output wire counter0_OUT,
output wire counter1_OUT,
output wire counter2_OUT,
output wire [31:0]counter_out
);
endmodule
|
module led_Dev_IO(
input wire clk ,
input wire rst,
input wire GPIOf0000000_we,
input wire [31:0] Peripheral_in,
output reg [1:0] counter_set,
output wire [7:0] led_out,
output reg [21:0] GPIOf0
);
reg [7:0]LED;
assign led_out = LED;
always @(negedge clk or posedge rst) begin
if (rst) begin
LED <= 8'hAA;
counter_set <= 2'b00;
end else begin
if (GPIOf0000000_we) {GPIOf0[21:0], LED, counter_set} <= Peripheral_in;
else begin
LED <= LED;
counter_set <= counter_set;
end
end
end
endmodule
|
module bw_io_misc_chunk1(io_ext_int_l ,spare_misc_pinoe ,sel_bypass ,
vss_sense ,vdd_sense ,test_mode ,ext_int_l ,temp_trig ,
spare_misc_pindata ,ckd ,vref ,vddo ,clk_stretch ,hiz_l ,rst_val_dn
,rst_val_up ,reset_l ,mode_ctl ,update_dr ,io_test_mode ,shift_dr
,clock_dr ,io_clk_stretch ,por_l ,rst_io_l ,bsi ,se ,si ,so ,bso ,
clk ,io_pgrm_en ,io_burnin ,burnin ,obsel ,pgrm_en ,io_temp_trig ,
pwron_rst_l ,io_pwron_rst_l ,spare_misc_pin ,spare_misc_pin_to_core
);
input [5:4] obsel ;
output io_ext_int_l ;
output io_test_mode ;
output io_clk_stretch ;
output so ;
output bso ;
output io_pgrm_en ;
output io_burnin ;
output io_temp_trig ;
output io_pwron_rst_l ;
output spare_misc_pin_to_core ;
input spare_misc_pinoe ;
input sel_bypass ;
input spare_misc_pindata ;
input ckd ;
input vref ;
input vddo ;
input hiz_l ;
input rst_val_dn ;
input rst_val_up ;
input reset_l ;
input mode_ctl ;
input update_dr ;
input shift_dr ;
input clock_dr ;
input por_l ;
input rst_io_l ;
input bsi ;
input se ;
input si ;
input clk ;
inout vss_sense ;
inout vdd_sense ;
inout test_mode ;
inout ext_int_l ;
inout temp_trig ;
inout clk_stretch ;
inout burnin ;
inout pgrm_en ;
inout pwron_rst_l ;
inout spare_misc_pin ;
supply1 vdd ;
supply0 vss ;
wire net107 ;
wire scan_clk_stretch_spare0 ;
wire bscan_temp_trig_ext_int_l ;
wire bscan_test_mode_por ;
wire bscan_ext_int_l_spare0 ;
wire bscan_spare0_clk_stretch ;
wire bscan_por_temp_trig ;
wire scan_ext_int_l_temp_trig ;
wire scan_spare0_ext_int_l ;
bw_u1_ckbuf_40x Iclkbuf_1 (
.clk (net107 ),
.rclk (clk ) );
bw_io_cmos2_pad burnin_pad (
.oe (vss ),
.vddo (vddo ),
.data (vss ),
.to_core (io_burnin ),
.pad (burnin ),
.por_l (por_l ) );
bw_io_cmos_pad test_mode_pad (
.oe (vss ),
.bsr_si (bsi ),
.rst_io_l (reset_l ),
.vddo (vddo ),
.se (vdd ),
.rst_val_up (rst_val_up ),
.data (vss ),
.mode_ctl (mode_ctl ),
.clock_dr (clock_dr ),
.update_dr (update_dr ),
.rst_val_dn (rst_val_dn ),
.hiz_l (hiz_l ),
.shift_dr (shift_dr ),
.bso (bscan_test_mode_por ),
.to_core (io_test_mode ),
.pad (test_mode ),
.por_l (vss ) );
bw_io_hstl_pad temp_trig_pad (
.obsel ({obsel } ),
.so (so ),
.clock_dr (clock_dr ),
.vref (vref ),
.update_dr (update_dr ),
.clk (net107 ),
.reset_l (reset_l ),
.hiz_l (hiz_l ),
.shift_dr (shift_dr ),
.rst_io_l (rst_io_l ),
.rst_val_up (rst_val_up ),
.bso (bscan_temp_trig_ext_int_l ),
.bsr_si (bscan_por_temp_trig ),
.rst_val_dn (rst_val_dn ),
.mode_ctl (mode_ctl ),
.si (scan_ext_int_l_temp_trig ),
.oe (vss ),
.data (vss ),
.se (se ),
.to_core (io_temp_trig ),
.por_l (por_l ),
.pad (temp_trig ),
.vddo (vddo ),
.sel_bypass (sel_bypass ),
.ckd (ckd ) );
bw_io_hstl_pad ext_int_l_pad (
.obsel ({obsel } ),
.so (scan_ext_int_l_temp_trig ),
.clock_dr (clock_dr ),
.vref (vref ),
.update_dr (update_dr ),
.clk (net107 ),
.reset_l (reset_l ),
.hiz_l (hiz_l ),
.shift_dr (shift_dr ),
.rst_io_l (rst_io_l ),
.rst_val_up (rst_val_up ),
.bso (bscan_ext_int_l_spare0 ),
.bsr_si (bscan_temp_trig_ext_int_l ),
.rst_val_dn (rst_val_dn ),
.mode_ctl (mode_ctl ),
.si (scan_spare0_ext_int_l ),
.oe (vss ),
.data (vss ),
.se (se ),
.to_core (io_ext_int_l ),
.por_l (por_l ),
.pad (ext_int_l ),
.vddo (vddo ),
.sel_bypass (sel_bypass ),
.ckd (ckd ) );
bw_io_cmos_pad pwron_rst_l_pad (
.oe (vss ),
.bsr_si (bscan_test_mode_por ),
.rst_io_l (reset_l ),
.vddo (vddo ),
.se (vdd ),
.rst_val_up (rst_val_up ),
.data (vss ),
.mode_ctl (mode_ctl ),
.clock_dr (clock_dr ),
.update_dr (update_dr ),
.rst_val_dn (rst_val_dn ),
.hiz_l (hiz_l ),
.shift_dr (shift_dr ),
.bso (bscan_por_temp_trig ),
.to_core (io_pwron_rst_l ),
.pad (pwron_rst_l ),
.por_l (vss ) );
bw_io_cmos2_pad pgrm_en_pad (
.oe (vss ),
.vddo (vddo ),
.data (vss ),
.to_core (io_pgrm_en ),
.pad (pgrm_en ),
.por_l (por_l ) );
bw_io_hstl_pad spare_misc_pin_0_pad (
.obsel ({obsel } ),
.so (scan_spare0_ext_int_l ),
.clock_dr (clock_dr ),
.vref (vref ),
.update_dr (update_dr ),
.clk (net107 ),
.reset_l (reset_l ),
.hiz_l (hiz_l ),
.shift_dr (shift_dr ),
.rst_io_l (rst_io_l ),
.rst_val_up (rst_val_up ),
.bso (bscan_spare0_clk_stretch ),
.bsr_si (bscan_ext_int_l_spare0 ),
.rst_val_dn (rst_val_dn ),
.mode_ctl (mode_ctl ),
.si (scan_clk_stretch_spare0 ),
.oe (spare_misc_pinoe ),
.data (spare_misc_pindata ),
.se (se ),
.to_core (spare_misc_pin_to_core ),
.por_l (por_l ),
.pad (spare_misc_pin ),
.vddo (vddo ),
.sel_bypass (sel_bypass ),
.ckd (ckd ) );
bw_io_hstl_pad clk_stretch_pad (
.obsel ({obsel } ),
.so (scan_clk_stretch_spare0 ),
.clock_dr (clock_dr ),
.vref (vref ),
.update_dr (update_dr ),
.clk (net107 ),
.reset_l (reset_l ),
.hiz_l (hiz_l ),
.shift_dr (shift_dr ),
.rst_io_l (rst_io_l ),
.rst_val_up (rst_val_up ),
.bso (bso ),
.bsr_si (bscan_spare0_clk_stretch ),
.rst_val_dn (rst_val_dn ),
.mode_ctl (mode_ctl ),
.si (si ),
.oe (vss ),
.data (vss ),
.se (se ),
.to_core (io_clk_stretch ),
.por_l (por_l ),
.pad (clk_stretch ),
.vddo (vddo ),
.sel_bypass (sel_bypass ),
.ckd (ckd ) );
endmodule
|
module TailLight(
input reset, left, right, clk,
output LC, LB, LA, RA, RB, RC
);
parameter ST_IDLE = 3'b000;
parameter ST_L1 = 3'b001;
parameter ST_L2 = 3'b010;
parameter ST_L3 = 3'b011;
parameter ST_R1 = 3'b100;
parameter ST_R2 = 3'b101;
parameter ST_R3 = 3'b110;
reg [2:0] state, next_state;
always @(posedge clk)
if (reset)
state <= ST_IDLE;
else
state <= next_state;
always @*
begin
case (state)
ST_IDLE: begin
if (left && ~right)
next_state = ST_L1;
else if (~left && right)
next_state = ST_R1;
else
next_state = ST_IDLE;
end
ST_L1: next_state = ST_L2;
ST_L2: next_state = ST_L3;
ST_R1: next_state = ST_R2;
ST_R2: next_state = ST_R3;
default: next_state = ST_IDLE;
endcase
if (left && right)
next_state = ST_IDLE;
end
assign LA = state == ST_L1 || state == ST_L2 || state == ST_L3;
assign LB = state == ST_L2 || state == ST_L3;
assign LC = state == ST_L3;
assign RA = state == ST_R1 || state == ST_R2 || state == ST_R3;
assign RB = state == ST_R2 || state == ST_R3;
assign RC = state == ST_R3;
endmodule
|
module sky130_fd_sc_hd__o22ai (
Y ,
A1,
A2,
B1,
B2
);
output Y ;
input A1;
input A2;
input B1;
input B2;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
|
module sky130_fd_sc_lp__nor4_0 (
Y ,
A ,
B ,
C ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input B ;
input C ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__nor4 base (
.Y(Y),
.A(A),
.B(B),
.C(C),
.D(D),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
|
module sky130_fd_sc_lp__nor4_0 (
Y,
A,
B,
C,
D
);
output Y;
input A;
input B;
input C;
input D;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__nor4 base (
.Y(Y),
.A(A),
.B(B),
.C(C),
.D(D)
);
endmodule
|
module sky130_fd_sc_ms__a22oi_1 (
Y ,
A1 ,
A2 ,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ms__a22oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
|
module sky130_fd_sc_ms__a22oi_1 (
Y ,
A1,
A2,
B1,
B2
);
output Y ;
input A1;
input A2;
input B1;
input B2;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__a22oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2)
);
endmodule
|
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