module_content
stringlengths 18
1.05M
|
|---|
module top ;
wire Net_60;
wire Net_55;
USBFS_v2_70_0 USBUART_1 (
.sof(Net_55),
.vbusdet(1'b0));
defparam USBUART_1.epDMAautoOptimization = 0;
CharLCD_v2_0_1 LCD ();
endmodule
|
module vga640x480(
input wire pix_en, //pixel clock: 25MHz
input wire clk, //100MHz
input wire rst, //asynchronous reset,
input wire [8:0] o_vec,
input wire [8:0] x_vec,
input wire [2:0] game_status,
output wire hsync, //horizontal sync out
output wire vsync, //vertical sync out
output reg [2:0] red, //red vga output
output reg [2:0] green, //green vga output
output reg [1:0] blue //blue vga output
);
// video structure constants
parameter [9:0] hpixels = 800;// horizontal pixels per line
parameter [9:0] vlines = 521; // vertical lines per frame
parameter [9:0] hpulse = 96; // hsync pulse length
parameter [9:0] vpulse = 2; // vsync pulse length
parameter [9:0] hbp = 144; // end of horizontal back porch
parameter [9:0] hfp = 784; // beginning of horizontal front porch
parameter [9:0] vbp = 31; // end of vertical back porch
parameter [9:0] vfp = 511; // beginning of vertical front porch
// active horizontal video is therefore: 784 - 144 = 640
// active vertical video is therefore: 511 - 31 = 480
// registers for storing the horizontal & vertical counters
reg [9:0] hc;
reg [9:0] vc;
// Horizontal & vertical counters --
// this is how we keep track of where we are on the screen.
// ------------------------
// Sequential "always block", which is a block that is
// only triggered on signal transitions or "edges".
// posedge = rising edge & negedge = falling edge
// Assignment statements can only be used on type "reg" and need to be of the "non-blocking" type: <=
always @(posedge clk)
begin
// reset condition
if (rst == 1)
begin
hc <= 0;
vc <= 0;
end
else if (pix_en == 1)
begin
// keep counting until the end of the line
if (hc < hpixels - 1)
hc <= hc + 1;
else
// When we hit the end of the line, reset the horizontal
// counter and increment the vertical counter.
// If vertical counter is at the end of the frame, then
// reset that one too.
begin
hc <= 0;
if (vc < vlines - 1)
vc <= vc + 1;
else
vc <= 0;
end
end
end
// generate sync pulses (active low)
// ----------------
// "assign" statements are a quick way to
// give values to variables of type: wire
assign hsync = (hc < hpulse) ? 0:1;
assign vsync = (vc < vpulse) ? 0:1;
parameter [9:0] line_thickness = 2;
parameter [9:0] tile_offset = 10;
parameter [9:0] tile_width = 50;
parameter [9:0] radius = 15;
parameter [9:0] circle_thickness = 2;
//parameter [9:0] o_vec = 9'b111111111;
//parameter [9:0] x_vec = 9'b000000000;
reg [50:0] x_arr [50:0];//INDEX {..., 1, 0}. Note that 50 should be equal to tile_width
reg [50:0] y_arr [50:0];//INDEX {..., 1, 0}. Note that 50 should be equal to tile_width
parameter [2500:0] o_pic = {
{50'b00000000000000000000000000000000000000000000000000},
{50'b00000000000000000000000000000000000000000000000000},
{50'b00000000000000000000000000000000000000000000000000},
{50'b00000000000000000000000000000000000000000000000000},
{50'b00000000000000000000000000000000000000000000000000},
{50'b00000000000000000000000000000000000000000000000000},
{50'b00000000000000000000000000000000000000000000000000},
{50'b00000000000000000001111111111100000000000000000000},
{50'b00000000000000001111111111111111100000000000000000},
{50'b00000000000000011111111111111111110000000000000000},
{50'b00000000000001111110000000000011111100000000000000},
{50'b00000000000011111000000000000000111110000000000000},
{50'b00000000000111100000000000000000001111000000000000},
{50'b00000000001111000000000000000000000111100000000000},
{50'b00000000001110000000000000000000000011100000000000},
{50'b00000000011100000000000000000000000001110000000000},
{50'b00000000111100000000000000000000000001111000000000},
{50'b00000000111000000000000000000000000000111000000000},
{50'b00000000111000000000000000000000000000111000000000},
{50'b00000001110000000000000000000000000000011100000000},
{50'b00000001110000000000000000000000000000011100000000},
{50'b00000001110000000000000000000000000000011100000000},
{50'b00000001110000000000000000000000000000011100000000},
{50'b00000001110000000000000000000000000000011100000000},
{50'b00000001110000000000000000000000000000011100000000},
{50'b00000001110000000000000000000000000000011100000000},
{50'b00000001110000000000000000000000000000011100000000},
{50'b00000001110000000000000000000000000000011100000000},
{50'b00000001110000000000000000000000000000011100000000},
{50'b00000001110000000000000000000000000000011100000000},
{50'b00000000111000000000000000000000000000111000000000},
{50'b00000000111000000000000000000000000000111000000000},
{50'b00000000111100000000000000000000000001111000000000},
{50'b00000000011100000000000000000000000001110000000000},
{50'b00000000001110000000000000000000000011100000000000},
{50'b00000000001111000000000000000000000111100000000000},
{50'b00000000000111100000000000000000001111000000000000},
{50'b00000000000011111000000000000000111110000000000000},
{50'b00000000000001111110000000000011111100000000000000},
{50'b00000000000000011111111111111111110000000000000000},
{50'b00000000000000001111111111111111100000000000000000},
{50'b00000000000000000001111111111100000000000000000000},
{50'b00000000000000000000000000000000000000000000000000},
{50'b00000000000000000000000000000000000000000000000000},
{50'b00000000000000000000000000000000000000000000000000},
{50'b00000000000000000000000000000000000000000000000000},
{50'b00000000000000000000000000000000000000000000000000},
{50'b00000000000000000000000000000000000000000000000000},
{50'b00000000000000000000000000000000000000000000000000},
{50'b00000000000000000000000000000000000000000000000000}
};
parameter [2500:0] x_pic = {
{50'b00000000000000000000000000000000000000000000000000},
{50'b01110000000000000000000000000000000000000000000111},
{50'b00111000000000000000000000000000000000000000001110},
{50'b00011100000000000000000000000000000000000000011100},
{50'b00001110000000000000000000000000000000000000111000},
{50'b00000111000000000000000000000000000000000001110000},
{50'b00000011100000000000000000000000000000000011100000},
{50'b00000001110000000000000000000000000000000111000000},
{50'b00000000111000000000000000000000000000001110000000},
{50'b00000000011100000000000000000000000000011100000000},
{50'b00000000001110000000000000000000000000111000000000},
{50'b00000000000111000000000000000000000001110000000000},
{50'b00000000000011100000000000000000000011100000000000},
{50'b00000000000001110000000000000000000111000000000000},
{50'b00000000000000111000000000000000001110000000000000},
{50'b00000000000000011100000000000000011100000000000000},
{50'b00000000000000001110000000000000111000000000000000},
{50'b00000000000000000111000000000001110000000000000000},
{50'b00000000000000000011100000000011100000000000000000},
{50'b00000000000000000001110000000111000000000000000000},
{50'b00000000000000000000111000001110000000000000000000},
{50'b00000000000000000000011100011100000000000000000000},
{50'b00000000000000000000001110111000000000000000000000},
{50'b00000000000000000000000111110000000000000000000000},
{50'b00000000000000000000000011100000000000000000000000},
{50'b00000000000000000000000111110000000000000000000000},
{50'b00000000000000000000001110111000000000000000000000},
{50'b00000000000000000000011100011100000000000000000000},
{50'b00000000000000000000111000001110000000000000000000},
{50'b00000000000000000001110000000111000000000000000000},
{50'b00000000000000000011100000000011100000000000000000},
{50'b00000000000000000111000000000001110000000000000000},
{50'b00000000000000001110000000000000111000000000000000},
{50'b00000000000000011100000000000000011100000000000000},
{50'b00000000000000111000000000000000001110000000000000},
{50'b00000000000001110000000000000000000111000000000000},
{50'b00000000000011100000000000000000000011100000000000},
{50'b00000000000111000000000000000000000001110000000000},
{50'b00000000001110000000000000000000000000111000000000},
{50'b00000000011100000000000000000000000000011100000000},
{50'b00000000111000000000000000000000000000001110000000},
{50'b00000001110000000000000000000000000000000111000000},
{50'b00000011100000000000000000000000000000000011100000},
{50'b00000111000000000000000000000000000000000001110000},
{50'b00001110000000000000000000000000000000000000111000},
{50'b00011100000000000000000000000000000000000000011100},
{50'b00111000000000000000000000000000000000000000001110},
{50'b01110000000000000000000000000000000000000000000111},
{50'b01100000000000000000000000000000000000000000000011},
{50'b01000000000000000000000000000000000000000000000001}
};
// display 100% saturation colorbars
// ------------------------
// Combinational "always block", which is a block that is
// triggered when anything in the "sensitivity list" changes.
// The asterisk implies that everything that is capable of triggering the block
// is automatically included in the sensitivty list. In this case, it would be
// equivalent to the following: always @(hc, vc)
// Assignment statements can only be used on type "reg" and should be of the "blocking" type: =
always @(*)
begin
// first check if we're within vertical active video range
if (vc >= vbp && vc < vfp)
begin
// Tic-Tac-Toe Lines
if ( (hc >= (hbp + tile_offset + tile_width) && hc < (hbp + tile_offset + tile_width + line_thickness)
&& vc >= (vbp + tile_offset) && vc < (vbp + tile_offset + 3*tile_width + 2*line_thickness))
|| (hc >= (hbp + tile_offset + tile_width*2 + line_thickness) && hc < (hbp + tile_offset + tile_width*2 + line_thickness*2)
&& vc >= (vbp + tile_offset) && vc < (vbp + tile_offset + 3*tile_width + 2*line_thickness))
|| (vc >= (vbp + tile_offset + tile_width*2 + line_thickness) && vc < (vbp + tile_offset + tile_width*2 + line_thickness*2)
&& hc >= (hbp + tile_offset) && hc < (hbp + tile_offset + 3*tile_width + 2*line_thickness))
|| (vc >= (vbp + tile_offset + tile_width) && vc < (vbp + tile_offset + tile_width + line_thickness)
&& hc >= (hbp + tile_offset) && hc < (hbp + tile_offset + 3*tile_width + 2*line_thickness)))
begin
red = 3'b010;
green = 3'b100;
blue = 2'b11;
end
// Tile Blocks
// 0 | 1 | 2
// 3 | 4 | 5
// 6 | 7 | 8
// Begin Row 1
else if ( (hc >= (hbp + tile_offset) && hc < (hbp + tile_offset + tile_width))
&& (vc >= (vbp + tile_offset) && vc < (vbp + tile_offset + tile_width)))
begin // Tile 0
if (o_vec[0])
begin
if (o_pic[(hc - hbp - tile_offset) + (vc - vbp - tile_offset) * 50])
begin
red = 3'b111;
green = 3'b111;
blue = 2'b11;
end
else
begin
red = 3'b111;
green = 3'b000;
blue = 2'b00;
end
end
else if (x_vec[0])
begin
if (x_pic[(hc - hbp - tile_offset) + (vc - vbp - tile_offset) * 50])
begin
red = 3'b111;
green = 3'b111;
blue = 2'b11;
end
else
begin
red = 3'b111;
green = 3'b000;
blue = 2'b00;
end
end
else
begin
red = 3'b111;
green = 3'b000;
blue = 2'b00;
end
end
else if ( (hc >= (hbp + tile_offset + line_thickness + tile_width) && hc < (hbp + tile_offset + tile_width*2 + line_thickness))
&& (vc >= (vbp + tile_offset) && vc < (vbp + tile_offset + tile_width)))
begin //Tile 1
if (o_vec[1])
begin
if (o_pic[(hc - hbp - tile_offset - tile_width - line_thickness) + (vc - vbp - tile_offset) * 50])
begin
red = 3'b111;
green = 3'b111;
blue = 2'b11;
end
else
begin
red = 3'b000;
green = 3'b111;
blue = 2'b00;
end
end
else if (x_vec[1])
begin
if (x_pic[(hc - hbp - tile_offset - tile_width - line_thickness) + (vc - vbp - tile_offset) * 50])
begin
red = 3'b111;
green = 3'b111;
blue = 2'b11;
end
else
begin
red = 3'b000;
green = 3'b111;
blue = 2'b00;
end
end
else
begin
red = 3'b000;
green = 3'b111;
blue = 2'b00;
end
end
else if ( (hc >= (hbp + tile_offset + line_thickness*2 + tile_width*2) && hc < (hbp + tile_offset + tile_width*3 + line_thickness*2))
&& (vc >= (vbp + tile_offset) && vc < (vbp + tile_offset + tile_width)))
begin // Tile 2
if (o_vec[2])
begin
if (o_pic[(hc - hbp - tile_offset - tile_width * 2 - line_thickness*2) + (vc - vbp - tile_offset) * 50])
begin
red = 3'b111;
green = 3'b111;
blue = 2'b11;
end
else
begin
red = 3'b000;
green = 3'b000;
blue = 2'b11;
end
end
else if (x_vec[2])
begin
if (x_pic[(hc - hbp - tile_offset - tile_width * 2 - line_thickness*2) + (vc - vbp - tile_offset) * 50])
begin
red = 3'b111;
green = 3'b111;
blue = 2'b11;
end
else
begin
red = 3'b000;
green = 3'b000;
blue = 2'b11;
end
end
else
begin
red = 3'b000;
green = 3'b000;
blue = 2'b11;
end
end
// Begin Row 2
else if ( (hc >= (hbp + tile_offset) && hc < (hbp + tile_offset + tile_width))
&& (vc >= (vbp + tile_offset + line_thickness + tile_width) && vc < (vbp + tile_offset + tile_width*2 + line_thickness)))
begin // Tile 3
if (o_vec[3])
begin
if (o_pic[(hc - hbp - tile_offset) + (vc - vbp - tile_offset - tile_width - line_thickness) * 50])
begin
red = 3'b111;
green = 3'b111;
blue = 2'b11;
end
else
begin
red = 3'b111;
green = 3'b111;
blue = 2'b00;
end
end
else if (x_vec[3])
begin
if (x_pic[(hc - hbp - tile_offset) + (vc - vbp - tile_offset - tile_width - line_thickness) * 50])
begin
red = 3'b111;
green = 3'b111;
blue = 2'b11;
end
else
begin
red = 3'b111;
green = 3'b111;
blue = 2'b00;
end
end
else
begin
red = 3'b111;
green = 3'b111;
blue = 2'b00;
end
end
else if ( (hc >= (hbp + tile_offset + line_thickness + tile_width) && hc < (hbp + tile_offset + tile_width*2 + line_thickness))
&& (vc >= (vbp + tile_offset + line_thickness + tile_width) && vc < (vbp + tile_offset + tile_width*2 + line_thickness)))
begin // Tile 4
if (o_vec[4])
begin
if (o_pic[(hc - hbp - tile_offset - tile_width - line_thickness) + (vc - vbp - tile_offset - tile_width - line_thickness) * 50])
begin
red = 3'b111;
green = 3'b111;
blue = 2'b11;
end
else
begin
red = 3'b111;
green = 3'b000;
blue = 2'b11;
end
end
else if (x_vec[4])
begin
if (x_pic[(hc - hbp - tile_offset - tile_width - line_thickness) + (vc - vbp - tile_offset - tile_width - line_thickness) * 50])
begin
red = 3'b111;
green = 3'b111;
blue = 2'b11;
end
else
begin
red = 3'b111;
green = 3'b000;
blue = 2'b11;
end
end
else
begin
red = 3'b111;
green = 3'b000;
blue = 2'b11;
end
end
else if ( (hc >= (hbp + tile_offset + line_thickness*2 + tile_width*2) && hc < (hbp + tile_offset + tile_width*3 + line_thickness*2))
&& (vc >= (vbp + tile_offset + line_thickness + tile_width) && vc < (vbp + tile_offset + tile_width*2 + line_thickness)))
begin // Tile 5
if (o_vec[5])
begin
if (o_pic[(hc - hbp - tile_offset - tile_width * 2 - line_thickness*2) + (vc - vbp - tile_offset - tile_width - line_thickness) * 50])
begin
red = 3'b111;
green = 3'b111;
blue = 2'b11;
end
else
begin
red = 3'b000;
green = 3'b111;
blue = 2'b11;
end
end
else if (x_vec[5])
begin
if (x_pic[(hc - hbp - tile_offset - tile_width * 2 - line_thickness*2) + (vc - vbp - tile_offset - tile_width - line_thickness) * 50])
begin
red = 3'b111;
green = 3'b111;
blue = 2'b11;
end
else
begin
red = 3'b000;
green = 3'b111;
blue = 2'b11;
end
end
else
begin
red = 3'b000;
green = 3'b111;
blue = 2'b11;
end
end
// Begin Row 3
else if ( (hc >= (hbp + tile_offset) && hc < (hbp + tile_offset + tile_width))
&& (vc >= (vbp + tile_offset + line_thickness*2 + tile_width*2) && vc < (vbp + tile_offset + tile_width*3 + line_thickness*2)))
begin // Tile 6
if (o_vec[6])
begin
if (o_pic[(hc - hbp - tile_offset) + (vc - vbp - tile_offset - tile_width * 2 - line_thickness * 2) * 50])
begin
red = 3'b111;
green = 3'b111;
blue = 2'b11;
end
else
begin
red = 3'b010;
green = 3'b000;
blue = 2'b00;
end
end
else if (x_vec[6])
begin
if (x_pic[(hc - hbp - tile_offset) + (vc - vbp - tile_offset - tile_width * 2 - line_thickness * 2) * 50])
begin
red = 3'b111;
green = 3'b111;
blue = 2'b11;
end
else
begin
red = 3'b010;
green = 3'b000;
blue = 2'b00;
end
end
else
begin
red = 3'b010;
green = 3'b000;
blue = 2'b00;
end
end
else if ( (hc >= (hbp + tile_offset + line_thickness + tile_width) && hc < (hbp + tile_offset + tile_width*2 + line_thickness))
&& (vc >= (vbp + tile_offset + line_thickness*2 + tile_width*2) && vc < (vbp + tile_offset + tile_width*3 + line_thickness*2)))
begin // Tile 7
if (o_vec[7])
begin
if (o_pic[(hc - hbp - tile_offset - tile_width - line_thickness) + (vc - vbp - tile_offset - tile_width * 2 - line_thickness*2) * 50])
begin
red = 3'b111;
green = 3'b111;
blue = 2'b11;
end
else
begin
red = 3'b000;
green = 3'b010;
blue = 2'b00;
end
end
else if (x_vec[7])
begin
if (x_pic[(hc - hbp - tile_offset - tile_width - line_thickness) + (vc - vbp - tile_offset - tile_width * 2 - line_thickness*2) * 50])
begin
red = 3'b111;
green = 3'b111;
blue = 2'b11;
end
else
begin
red = 3'b000;
green = 3'b010;
blue = 2'b00;
end
end
else
begin
red = 3'b000;
green = 3'b010;
blue = 2'b00;
end
end
else if ( (hc >= (hbp + tile_offset + line_thickness*2 + tile_width*2) && hc < (hbp + tile_offset + tile_width*3 + line_thickness*2))
&& (vc >= (vbp + tile_offset + line_thickness*2 + tile_width*2) && vc < (vbp + tile_offset + tile_width*3 + line_thickness*2)))
begin // Tile 8
if (o_vec[8])
begin
if (o_pic[(hc - hbp - tile_offset - tile_width * 2 - line_thickness * 2) + (vc - vbp - tile_offset - tile_width * 2 - line_thickness * 2) * 50])
begin
red = 3'b111;
green = 3'b111;
blue = 2'b11;
end
else
begin
red = 3'b010;
green = 3'b010;
blue = 2'b00;
end
end
else if (x_vec[8])
begin
if (x_pic[(hc - hbp - tile_offset - tile_width * 2 - line_thickness * 2) + (vc - vbp - tile_offset - tile_width * 2 - line_thickness * 2) * 50])
begin
red = 3'b111;
green = 3'b111;
blue = 2'b11;
end
else
begin
red = 3'b010;
green = 3'b010;
blue = 2'b00;
end
end
else
begin
red = 3'b010;
green = 3'b010;
blue = 2'b00;
end
end
else if (hc >= (hbp) && hc < (hfp))
begin
red = 3'b111;
green = 3'b111;
blue = 2'b11;
end
// we're outside active horizontal range so display black
else
begin
red = 0;
green = 0;
blue = 0;
end
end
// we're outside active vertical range so display black
else
begin
red = 0;
green = 0;
blue = 0;
end
end
endmodule
|
module outputs)
// End of automatics
////////////////////////////////////////////////////////////////////////
// Code start here
////////////////////////////////////////////////////////////////////////
cluster_header cluster_header (/*AUTOINST*/
// Outputs
.dbginit_l(dbginit_l),
.cluster_grst_l(cluster_grst_l),
.rclk (rclk),
.so (so),
// Inputs
.gclk (gclk),
.cluster_cken(cluster_cken),
.arst_l(arst_l),
.grst_l(grst_l),
.adbginit_l(adbginit_l),
.gdbginit_l(gdbginit_l),
.si (si),
.se (se));
endmodule
|
module sky130_fd_sc_lp__dlymetal6s6s_1 (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__dlymetal6s6s base (
.X(X),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
|
module sky130_fd_sc_lp__dlymetal6s6s_1 (
X,
A
);
output X;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__dlymetal6s6s base (
.X(X),
.A(A)
);
endmodule
|
module top();
// Inputs are registered
reg A;
reg B;
reg C;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Y;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
B = 1'bX;
C = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 B = 1'b0;
#60 C = 1'b0;
#80 VGND = 1'b0;
#100 VNB = 1'b0;
#120 VPB = 1'b0;
#140 VPWR = 1'b0;
#160 A = 1'b1;
#180 B = 1'b1;
#200 C = 1'b1;
#220 VGND = 1'b1;
#240 VNB = 1'b1;
#260 VPB = 1'b1;
#280 VPWR = 1'b1;
#300 A = 1'b0;
#320 B = 1'b0;
#340 C = 1'b0;
#360 VGND = 1'b0;
#380 VNB = 1'b0;
#400 VPB = 1'b0;
#420 VPWR = 1'b0;
#440 VPWR = 1'b1;
#460 VPB = 1'b1;
#480 VNB = 1'b1;
#500 VGND = 1'b1;
#520 C = 1'b1;
#540 B = 1'b1;
#560 A = 1'b1;
#580 VPWR = 1'bx;
#600 VPB = 1'bx;
#620 VNB = 1'bx;
#640 VGND = 1'bx;
#660 C = 1'bx;
#680 B = 1'bx;
#700 A = 1'bx;
end
sky130_fd_sc_ms__nor3 dut (.A(A), .B(B), .C(C), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Y(Y));
endmodule
|
module led_controller_design_processing_system7_0_0(TTC0_WAVE0_OUT, TTC0_WAVE1_OUT,
TTC0_WAVE2_OUT, USB0_PORT_INDCTL, USB0_VBUS_PWRSELECT, USB0_VBUS_PWRFAULT,
M_AXI_GP0_ARVALID, M_AXI_GP0_AWVALID, M_AXI_GP0_BREADY, M_AXI_GP0_RREADY,
M_AXI_GP0_WLAST, M_AXI_GP0_WVALID, M_AXI_GP0_ARID, M_AXI_GP0_AWID, M_AXI_GP0_WID,
M_AXI_GP0_ARBURST, M_AXI_GP0_ARLOCK, M_AXI_GP0_ARSIZE, M_AXI_GP0_AWBURST,
M_AXI_GP0_AWLOCK, M_AXI_GP0_AWSIZE, M_AXI_GP0_ARPROT, M_AXI_GP0_AWPROT, M_AXI_GP0_ARADDR,
M_AXI_GP0_AWADDR, M_AXI_GP0_WDATA, M_AXI_GP0_ARCACHE, M_AXI_GP0_ARLEN, M_AXI_GP0_ARQOS,
M_AXI_GP0_AWCACHE, M_AXI_GP0_AWLEN, M_AXI_GP0_AWQOS, M_AXI_GP0_WSTRB, M_AXI_GP0_ACLK,
M_AXI_GP0_ARREADY, M_AXI_GP0_AWREADY, M_AXI_GP0_BVALID, M_AXI_GP0_RLAST,
M_AXI_GP0_RVALID, M_AXI_GP0_WREADY, M_AXI_GP0_BID, M_AXI_GP0_RID, M_AXI_GP0_BRESP,
M_AXI_GP0_RRESP, M_AXI_GP0_RDATA, FCLK_CLK0, FCLK_RESET0_N, MIO, DDR_CAS_n, DDR_CKE, DDR_Clk_n,
DDR_Clk, DDR_CS_n, DDR_DRSTB, DDR_ODT, DDR_RAS_n, DDR_WEB, DDR_BankAddr, DDR_Addr, DDR_VRN,
DDR_VRP, DDR_DM, DDR_DQ, DDR_DQS_n, DDR_DQS, PS_SRSTB, PS_CLK, PS_PORB)
/* synthesis syn_black_box black_box_pad_pin="TTC0_WAVE0_OUT,TTC0_WAVE1_OUT,TTC0_WAVE2_OUT,USB0_PORT_INDCTL[1:0],USB0_VBUS_PWRSELECT,USB0_VBUS_PWRFAULT,M_AXI_GP0_ARVALID,M_AXI_GP0_AWVALID,M_AXI_GP0_BREADY,M_AXI_GP0_RREADY,M_AXI_GP0_WLAST,M_AXI_GP0_WVALID,M_AXI_GP0_ARID[11:0],M_AXI_GP0_AWID[11:0],M_AXI_GP0_WID[11:0],M_AXI_GP0_ARBURST[1:0],M_AXI_GP0_ARLOCK[1:0],M_AXI_GP0_ARSIZE[2:0],M_AXI_GP0_AWBURST[1:0],M_AXI_GP0_AWLOCK[1:0],M_AXI_GP0_AWSIZE[2:0],M_AXI_GP0_ARPROT[2:0],M_AXI_GP0_AWPROT[2:0],M_AXI_GP0_ARADDR[31:0],M_AXI_GP0_AWADDR[31:0],M_AXI_GP0_WDATA[31:0],M_AXI_GP0_ARCACHE[3:0],M_AXI_GP0_ARLEN[3:0],M_AXI_GP0_ARQOS[3:0],M_AXI_GP0_AWCACHE[3:0],M_AXI_GP0_AWLEN[3:0],M_AXI_GP0_AWQOS[3:0],M_AXI_GP0_WSTRB[3:0],M_AXI_GP0_ACLK,M_AXI_GP0_ARREADY,M_AXI_GP0_AWREADY,M_AXI_GP0_BVALID,M_AXI_GP0_RLAST,M_AXI_GP0_RVALID,M_AXI_GP0_WREADY,M_AXI_GP0_BID[11:0],M_AXI_GP0_RID[11:0],M_AXI_GP0_BRESP[1:0],M_AXI_GP0_RRESP[1:0],M_AXI_GP0_RDATA[31:0],FCLK_CLK0,FCLK_RESET0_N,MIO[53:0],DDR_CAS_n,DDR_CKE,DDR_Clk_n,DDR_Clk,DDR_CS_n,DDR_DRSTB,DDR_ODT,DDR_RAS_n,DDR_WEB,DDR_BankAddr[2:0],DDR_Addr[14:0],DDR_VRN,DDR_VRP,DDR_DM[3:0],DDR_DQ[31:0],DDR_DQS_n[3:0],DDR_DQS[3:0],PS_SRSTB,PS_CLK,PS_PORB" */;
output TTC0_WAVE0_OUT;
output TTC0_WAVE1_OUT;
output TTC0_WAVE2_OUT;
output [1:0]USB0_PORT_INDCTL;
output USB0_VBUS_PWRSELECT;
input USB0_VBUS_PWRFAULT;
output M_AXI_GP0_ARVALID;
output M_AXI_GP0_AWVALID;
output M_AXI_GP0_BREADY;
output M_AXI_GP0_RREADY;
output M_AXI_GP0_WLAST;
output M_AXI_GP0_WVALID;
output [11:0]M_AXI_GP0_ARID;
output [11:0]M_AXI_GP0_AWID;
output [11:0]M_AXI_GP0_WID;
output [1:0]M_AXI_GP0_ARBURST;
output [1:0]M_AXI_GP0_ARLOCK;
output [2:0]M_AXI_GP0_ARSIZE;
output [1:0]M_AXI_GP0_AWBURST;
output [1:0]M_AXI_GP0_AWLOCK;
output [2:0]M_AXI_GP0_AWSIZE;
output [2:0]M_AXI_GP0_ARPROT;
output [2:0]M_AXI_GP0_AWPROT;
output [31:0]M_AXI_GP0_ARADDR;
output [31:0]M_AXI_GP0_AWADDR;
output [31:0]M_AXI_GP0_WDATA;
output [3:0]M_AXI_GP0_ARCACHE;
output [3:0]M_AXI_GP0_ARLEN;
output [3:0]M_AXI_GP0_ARQOS;
output [3:0]M_AXI_GP0_AWCACHE;
output [3:0]M_AXI_GP0_AWLEN;
output [3:0]M_AXI_GP0_AWQOS;
output [3:0]M_AXI_GP0_WSTRB;
input M_AXI_GP0_ACLK;
input M_AXI_GP0_ARREADY;
input M_AXI_GP0_AWREADY;
input M_AXI_GP0_BVALID;
input M_AXI_GP0_RLAST;
input M_AXI_GP0_RVALID;
input M_AXI_GP0_WREADY;
input [11:0]M_AXI_GP0_BID;
input [11:0]M_AXI_GP0_RID;
input [1:0]M_AXI_GP0_BRESP;
input [1:0]M_AXI_GP0_RRESP;
input [31:0]M_AXI_GP0_RDATA;
output FCLK_CLK0;
output FCLK_RESET0_N;
inout [53:0]MIO;
inout DDR_CAS_n;
inout DDR_CKE;
inout DDR_Clk_n;
inout DDR_Clk;
inout DDR_CS_n;
inout DDR_DRSTB;
inout DDR_ODT;
inout DDR_RAS_n;
inout DDR_WEB;
inout [2:0]DDR_BankAddr;
inout [14:0]DDR_Addr;
inout DDR_VRN;
inout DDR_VRP;
inout [3:0]DDR_DM;
inout [31:0]DDR_DQ;
inout [3:0]DDR_DQS_n;
inout [3:0]DDR_DQS;
inout PS_SRSTB;
inout PS_CLK;
inout PS_PORB;
endmodule
|
module GS_3032(
config_n, // ACEX1K config pins
status_n, //
conf_done, //
cs, //
init_done, //
clk24in, // 24mhz in
clk20in, // 20mhz in
clkout, // clock out
clksel0, // clock select 0 (1=divide by 2, 0=no divide)
clksel1, // clock select 1 (1=clk20in, 0=clk24in)
a6,a7,a14,a15, // z80 signals
iorq_n,mreq_n, //
rd_n,wr_n, //
d7,d0, //
mema14,mema15, // signals to memories
romcs_n,ramcs0_n,
memoe_n,memwe_n,
coldres_n, // cold reset input
warmres_n, // warm reset output
clkin // input of clkout signal
);
output config_n; reg config_n;
input status_n;
input conf_done;
output cs; reg cs;
input init_done;
input clk24in;
input clk20in;
output clkout; reg clkout;
input clksel0,clksel1;
input a6,a7,a14,a15;
input iorq_n,mreq_n,rd_n,wr_n;
inout d7,d0; reg d7,d0;
output mema14,mema15; reg mema14,mema15;
output romcs_n,ramcs0_n; reg romcs_n,ramcs0_n;
output memoe_n,memwe_n; reg memoe_n,memwe_n;
input coldres_n;
input warmres_n;
input clkin;
reg int_mema14,int_mema15;
reg int_romcs_n,int_ramcs0_n;
reg int_memoe_n,int_memwe_n;
reg int_cs;
reg [1:0] memcfg; // memcfg[1]: 1 ram, 0 roms
// memcfg[0]: 0 page0, 1 page1 -> in 8000-ffff region
reg diver [0:10];
reg disbl; // =1 - 3032 disabled, =0 - enabled
reg was_cold_reset_n; // 1 - no cold reset, 0 - was cold reset
reg [1:0] dbout;
wire [1:0] dbin;
assign dbin[1] = d7;
assign dbin[0] = d0;
wire memcfg_write;
wire rescfg_write;
wire coldrstf_read;
wire fpgastat_read;
reg [3:0] rstcount; // counter for warm reset period
reg [2:0] disbl_sync;
clocker myclk( .clk1(clk24in),
.clk2(clk20in),
.clksel(clksel1),
.divsel(clksel0),
.clkout(clkout) );
always @*
begin
cs <= 1'b0;
d0 <= 1'bZ;
d7 <= 1'bZ;
mema14 <= 1'bZ;
mema15 <= 1'bZ;
romcs_n <= 1'bZ;
ramcs0_n <= 1'bZ;
memoe_n <= 1'bZ;
memwe_n <= 1'bZ;
end
always @(coldres_n, warmres_n)
begin
if( coldres_n==1'b0)
config_n <= 1'b0;
else if( warmres_n==1'b0 )
config_n <= 1'b1;
end
endmodule
|
module sky130_fd_sc_hdll__buf (
//# {{data|Data Signals}}
input A ,
output X ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
|
module sp_find_segment_n1_62 (
ph_seg_p_2_1_1_V_read,
th_seg_p_2_1_0_V_read,
th_seg_p_2_1_1_V_read,
cpat_seg_p_2_1_1_V_read,
ap_return_0,
ap_return_1,
ap_return_2,
ap_return_3
);
input [11:0] ph_seg_p_2_1_1_V_read;
input [6:0] th_seg_p_2_1_0_V_read;
input [6:0] th_seg_p_2_1_1_V_read;
input [3:0] cpat_seg_p_2_1_1_V_read;
output [11:0] ap_return_0;
output [3:0] ap_return_1;
output [6:0] ap_return_2;
output [6:0] ap_return_3;
assign ap_return_0 = ph_seg_p_2_1_1_V_read;
assign ap_return_1 = cpat_seg_p_2_1_1_V_read;
assign ap_return_2 = th_seg_p_2_1_0_V_read;
assign ap_return_3 = th_seg_p_2_1_1_V_read;
endmodule
|
module clk_wiz_v3_6_tb ();
// Clock to Q delay of 100ps
localparam TCQ = 100;
// timescale is 1ps/1ps
localparam ONE_NS = 1000;
localparam PHASE_ERR_MARGIN = 100; // 100ps
// how many cycles to run
localparam COUNT_PHASE = 1024;
// we'll be using the period in many locations
localparam time PER1 = 20.0*ONE_NS;
localparam time PER1_1 = PER1/2;
localparam time PER1_2 = PER1 - PER1/2;
// Declare the input clock signals
reg CLK_IN1 = 1;
// The high bit of the sampling counter
wire COUNT;
reg COUNTER_RESET = 0;
wire [1:1] CLK_OUT;
//Freq Check using the M & D values setting and actual Frequency generated
// Input clock generation
//------------------------------------
always begin
CLK_IN1 = #PER1_1 ~CLK_IN1;
CLK_IN1 = #PER1_2 ~CLK_IN1;
end
// Test sequence
reg [15*8-1:0] test_phase = "";
initial begin
// Set up any display statements using time to be readable
$timeformat(-12, 2, "ps", 10);
COUNTER_RESET = 0;
test_phase = "wait lock";
`wait_lock;
#(PER1*6);
COUNTER_RESET = 1;
#(PER1*20)
COUNTER_RESET = 0;
test_phase = "counting";
#(PER1*COUNT_PHASE);
$display("SIMULATION PASSED");
$display("SYSTEM_CLOCK_COUNTER : %0d\n",$time/PER1);
$finish;
end
// Instantiation of the example design containing the clock
// network and sampling counters
//---------------------------------------------------------
clk_wiz_v3_6_exdes
#(
.TCQ (TCQ)
) dut
(// Clock in ports
.CLK_IN1 (CLK_IN1),
// Reset for logic in example design
.COUNTER_RESET (COUNTER_RESET),
.CLK_OUT (CLK_OUT),
// High bits of the counters
.COUNT (COUNT));
// Freq Check
endmodule
|
module PCIeGen2x8If128(pci_exp_txp, pci_exp_txn, pci_exp_rxp, pci_exp_rxn, user_clk_out, user_reset_out, user_lnk_up, user_app_rdy, tx_buf_av, tx_cfg_req, tx_err_drop, s_axis_tx_tready, s_axis_tx_tdata, s_axis_tx_tkeep, s_axis_tx_tlast, s_axis_tx_tvalid, s_axis_tx_tuser, tx_cfg_gnt, m_axis_rx_tdata, m_axis_rx_tkeep, m_axis_rx_tlast, m_axis_rx_tvalid, m_axis_rx_tready, m_axis_rx_tuser, rx_np_ok, rx_np_req, fc_cpld, fc_cplh, fc_npd, fc_nph, fc_pd, fc_ph, fc_sel, cfg_status, cfg_command, cfg_dstatus, cfg_dcommand, cfg_lstatus, cfg_lcommand, cfg_dcommand2, cfg_pcie_link_state, cfg_pmcsr_pme_en, cfg_pmcsr_powerstate, cfg_pmcsr_pme_status, cfg_received_func_lvl_rst, cfg_trn_pending, cfg_pm_halt_aspm_l0s, cfg_pm_halt_aspm_l1, cfg_pm_force_state_en, cfg_pm_force_state, cfg_dsn, cfg_interrupt, cfg_interrupt_rdy, cfg_interrupt_assert, cfg_interrupt_di, cfg_interrupt_do, cfg_interrupt_mmenable, cfg_interrupt_msienable, cfg_interrupt_msixenable, cfg_interrupt_msixfm, cfg_interrupt_stat, cfg_pciecap_interrupt_msgnum, cfg_to_turnoff, cfg_turnoff_ok, cfg_bus_number, cfg_device_number, cfg_function_number, cfg_pm_wake, cfg_pm_send_pme_to, cfg_ds_bus_number, cfg_ds_device_number, cfg_ds_function_number, cfg_bridge_serr_en, cfg_slot_control_electromech_il_ctl_pulse, cfg_root_control_syserr_corr_err_en, cfg_root_control_syserr_non_fatal_err_en, cfg_root_control_syserr_fatal_err_en, cfg_root_control_pme_int_en, cfg_aer_rooterr_corr_err_reporting_en, cfg_aer_rooterr_non_fatal_err_reporting_en, cfg_aer_rooterr_fatal_err_reporting_en, cfg_aer_rooterr_corr_err_received, cfg_aer_rooterr_non_fatal_err_received, cfg_aer_rooterr_fatal_err_received, cfg_vc_tcvc_map, sys_clk, sys_rst_n)
/* synthesis syn_black_box black_box_pad_pin="pci_exp_txp[7:0],pci_exp_txn[7:0],pci_exp_rxp[7:0],pci_exp_rxn[7:0],user_clk_out,user_reset_out,user_lnk_up,user_app_rdy,tx_buf_av[5:0],tx_cfg_req,tx_err_drop,s_axis_tx_tready,s_axis_tx_tdata[127:0],s_axis_tx_tkeep[15:0],s_axis_tx_tlast,s_axis_tx_tvalid,s_axis_tx_tuser[3:0],tx_cfg_gnt,m_axis_rx_tdata[127:0],m_axis_rx_tkeep[15:0],m_axis_rx_tlast,m_axis_rx_tvalid,m_axis_rx_tready,m_axis_rx_tuser[21:0],rx_np_ok,rx_np_req,fc_cpld[11:0],fc_cplh[7:0],fc_npd[11:0],fc_nph[7:0],fc_pd[11:0],fc_ph[7:0],fc_sel[2:0],cfg_status[15:0],cfg_command[15:0],cfg_dstatus[15:0],cfg_dcommand[15:0],cfg_lstatus[15:0],cfg_lcommand[15:0],cfg_dcommand2[15:0],cfg_pcie_link_state[2:0],cfg_pmcsr_pme_en,cfg_pmcsr_powerstate[1:0],cfg_pmcsr_pme_status,cfg_received_func_lvl_rst,cfg_trn_pending,cfg_pm_halt_aspm_l0s,cfg_pm_halt_aspm_l1,cfg_pm_force_state_en,cfg_pm_force_state[1:0],cfg_dsn[63:0],cfg_interrupt,cfg_interrupt_rdy,cfg_interrupt_assert,cfg_interrupt_di[7:0],cfg_interrupt_do[7:0],cfg_interrupt_mmenable[2:0],cfg_interrupt_msienable,cfg_interrupt_msixenable,cfg_interrupt_msixfm,cfg_interrupt_stat,cfg_pciecap_interrupt_msgnum[4:0],cfg_to_turnoff,cfg_turnoff_ok,cfg_bus_number[7:0],cfg_device_number[4:0],cfg_function_number[2:0],cfg_pm_wake,cfg_pm_send_pme_to,cfg_ds_bus_number[7:0],cfg_ds_device_number[4:0],cfg_ds_function_number[2:0],cfg_bridge_serr_en,cfg_slot_control_electromech_il_ctl_pulse,cfg_root_control_syserr_corr_err_en,cfg_root_control_syserr_non_fatal_err_en,cfg_root_control_syserr_fatal_err_en,cfg_root_control_pme_int_en,cfg_aer_rooterr_corr_err_reporting_en,cfg_aer_rooterr_non_fatal_err_reporting_en,cfg_aer_rooterr_fatal_err_reporting_en,cfg_aer_rooterr_corr_err_received,cfg_aer_rooterr_non_fatal_err_received,cfg_aer_rooterr_fatal_err_received,cfg_vc_tcvc_map[6:0],sys_clk,sys_rst_n" */;
output [7:0]pci_exp_txp;
output [7:0]pci_exp_txn;
input [7:0]pci_exp_rxp;
input [7:0]pci_exp_rxn;
output user_clk_out;
output user_reset_out;
output user_lnk_up;
output user_app_rdy;
output [5:0]tx_buf_av;
output tx_cfg_req;
output tx_err_drop;
output s_axis_tx_tready;
input [127:0]s_axis_tx_tdata;
input [15:0]s_axis_tx_tkeep;
input s_axis_tx_tlast;
input s_axis_tx_tvalid;
input [3:0]s_axis_tx_tuser;
input tx_cfg_gnt;
output [127:0]m_axis_rx_tdata;
output [15:0]m_axis_rx_tkeep;
output m_axis_rx_tlast;
output m_axis_rx_tvalid;
input m_axis_rx_tready;
output [21:0]m_axis_rx_tuser;
input rx_np_ok;
input rx_np_req;
output [11:0]fc_cpld;
output [7:0]fc_cplh;
output [11:0]fc_npd;
output [7:0]fc_nph;
output [11:0]fc_pd;
output [7:0]fc_ph;
input [2:0]fc_sel;
output [15:0]cfg_status;
output [15:0]cfg_command;
output [15:0]cfg_dstatus;
output [15:0]cfg_dcommand;
output [15:0]cfg_lstatus;
output [15:0]cfg_lcommand;
output [15:0]cfg_dcommand2;
output [2:0]cfg_pcie_link_state;
output cfg_pmcsr_pme_en;
output [1:0]cfg_pmcsr_powerstate;
output cfg_pmcsr_pme_status;
output cfg_received_func_lvl_rst;
input cfg_trn_pending;
input cfg_pm_halt_aspm_l0s;
input cfg_pm_halt_aspm_l1;
input cfg_pm_force_state_en;
input [1:0]cfg_pm_force_state;
input [63:0]cfg_dsn;
input cfg_interrupt;
output cfg_interrupt_rdy;
input cfg_interrupt_assert;
input [7:0]cfg_interrupt_di;
output [7:0]cfg_interrupt_do;
output [2:0]cfg_interrupt_mmenable;
output cfg_interrupt_msienable;
output cfg_interrupt_msixenable;
output cfg_interrupt_msixfm;
input cfg_interrupt_stat;
input [4:0]cfg_pciecap_interrupt_msgnum;
output cfg_to_turnoff;
input cfg_turnoff_ok;
output [7:0]cfg_bus_number;
output [4:0]cfg_device_number;
output [2:0]cfg_function_number;
input cfg_pm_wake;
input cfg_pm_send_pme_to;
input [7:0]cfg_ds_bus_number;
input [4:0]cfg_ds_device_number;
input [2:0]cfg_ds_function_number;
output cfg_bridge_serr_en;
output cfg_slot_control_electromech_il_ctl_pulse;
output cfg_root_control_syserr_corr_err_en;
output cfg_root_control_syserr_non_fatal_err_en;
output cfg_root_control_syserr_fatal_err_en;
output cfg_root_control_pme_int_en;
output cfg_aer_rooterr_corr_err_reporting_en;
output cfg_aer_rooterr_non_fatal_err_reporting_en;
output cfg_aer_rooterr_fatal_err_reporting_en;
output cfg_aer_rooterr_corr_err_received;
output cfg_aer_rooterr_non_fatal_err_received;
output cfg_aer_rooterr_fatal_err_received;
output [6:0]cfg_vc_tcvc_map;
input sys_clk;
input sys_rst_n;
endmodule
|
module top();
// Inputs are registered
reg A1;
reg A2;
reg A3;
reg B1;
reg C1;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Y;
initial
begin
// Initial state is x for all inputs.
A1 = 1'bX;
A2 = 1'bX;
A3 = 1'bX;
B1 = 1'bX;
C1 = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A1 = 1'b0;
#40 A2 = 1'b0;
#60 A3 = 1'b0;
#80 B1 = 1'b0;
#100 C1 = 1'b0;
#120 VGND = 1'b0;
#140 VNB = 1'b0;
#160 VPB = 1'b0;
#180 VPWR = 1'b0;
#200 A1 = 1'b1;
#220 A2 = 1'b1;
#240 A3 = 1'b1;
#260 B1 = 1'b1;
#280 C1 = 1'b1;
#300 VGND = 1'b1;
#320 VNB = 1'b1;
#340 VPB = 1'b1;
#360 VPWR = 1'b1;
#380 A1 = 1'b0;
#400 A2 = 1'b0;
#420 A3 = 1'b0;
#440 B1 = 1'b0;
#460 C1 = 1'b0;
#480 VGND = 1'b0;
#500 VNB = 1'b0;
#520 VPB = 1'b0;
#540 VPWR = 1'b0;
#560 VPWR = 1'b1;
#580 VPB = 1'b1;
#600 VNB = 1'b1;
#620 VGND = 1'b1;
#640 C1 = 1'b1;
#660 B1 = 1'b1;
#680 A3 = 1'b1;
#700 A2 = 1'b1;
#720 A1 = 1'b1;
#740 VPWR = 1'bx;
#760 VPB = 1'bx;
#780 VNB = 1'bx;
#800 VGND = 1'bx;
#820 C1 = 1'bx;
#840 B1 = 1'bx;
#860 A3 = 1'bx;
#880 A2 = 1'bx;
#900 A1 = 1'bx;
end
sky130_fd_sc_ms__a311oi dut (.A1(A1), .A2(A2), .A3(A3), .B1(B1), .C1(C1), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Y(Y));
endmodule
|
module sky130_fd_sc_ls__a22oi (
Y ,
A1,
A2,
B1,
B2
);
// Module ports
output Y ;
input A1;
input A2;
input B1;
input B2;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire nand0_out ;
wire nand1_out ;
wire and0_out_Y;
// Name Output Other arguments
nand nand0 (nand0_out , A2, A1 );
nand nand1 (nand1_out , B2, B1 );
and and0 (and0_out_Y, nand0_out, nand1_out);
buf buf0 (Y , and0_out_Y );
endmodule
|
module prcfg_dac(
clk,
// control ports
control,
status,
// FIFO interface
src_dac_enable,
src_dac_data,
src_dac_valid,
dst_dac_enable,
dst_dac_data,
dst_dac_valid
);
localparam RP_ID = 8'hA1;
parameter CHANNEL_ID = 0;
input clk;
input [31:0] control;
output [31:0] status;
output src_dac_enable;
input [15:0] src_dac_data;
output src_dac_valid;
input dst_dac_enable;
output [15:0] dst_dac_data;
input dst_dac_valid;
reg [15:0] dst_dac_data = 0;
reg src_dac_valid = 0;
reg src_dac_enable = 0;
reg [15:0] dac_prbs = 32'hA2F19C;
reg [31:0] status = 0;
reg [ 2:0] counter = 0;
reg pattern = 0;
reg [15:0] sin_tone = 0;
reg [15:0] cos_tone = 0;
reg [ 3:0] mode;
wire [15:0] dac_pattern_s;
// prbs function
function [15:0] pn;
input [15:0] din;
reg [15:0] dout;
begin
dout[15] = din[14] ^ din[15];
dout[14] = din[13] ^ din[14];
dout[13] = din[12] ^ din[13];
dout[12] = din[11] ^ din[12];
dout[11] = din[10] ^ din[11];
dout[10] = din[ 9] ^ din[10];
dout[ 9] = din[ 8] ^ din[ 9];
dout[ 8] = din[ 7] ^ din[ 8];
dout[ 7] = din[ 6] ^ din[ 7];
dout[ 6] = din[ 5] ^ din[ 6];
dout[ 5] = din[ 4] ^ din[ 5];
dout[ 4] = din[ 3] ^ din[ 4];
dout[ 3] = din[ 2] ^ din[ 3];
dout[ 2] = din[ 1] ^ din[ 2];
dout[ 1] = din[ 0] ^ din[ 1];
dout[ 0] = din[14] ^ din[15] ^ din[ 0];
pn = dout;
end
endfunction
always @(posedge clk) begin
status <= {24'h0, RP_ID};
mode <= control[7:4];
end
// sine tone generation
always @(posedge clk) begin
if ((dst_dac_enable == 1'h1) && (dst_dac_valid == 1'h1)) begin
counter <= counter + 1;
end
end
always @(counter) begin
case(counter)
3'd0 : begin
sin_tone <= 16'h0000;
cos_tone <= 16'h7FFF;
end
3'd1 : begin
sin_tone <= 16'h5A82;
cos_tone <= 16'h5A82;
end
3'd2 : begin
sin_tone <= 16'h7FFF;
cos_tone <= 16'h0000;
end
3'd3 : begin
sin_tone <= 16'h5A82;
cos_tone <= 16'hA57E;
end
3'd4 : begin
sin_tone <= 16'h0000;
cos_tone <= 16'h8001;
end
3'd5 : begin
sin_tone <= 16'hA57E;
cos_tone <= 16'hA57E;
end
3'd6 : begin
sin_tone <= 16'h8001;
cos_tone <= 16'h0000;
end
3'd7 : begin
sin_tone <= 16'hA57E;
cos_tone <= 16'h5A82;
end
endcase
end
// prbs generation
always @(posedge clk) begin
if((dst_dac_enable == 1'h1) && (dst_dac_valid == 1'h1)) begin
dac_prbs <= pn(dac_prbs);
end
end
// constant pattern generator
always @(posedge clk) begin
if((dst_dac_enable == 1'h1) && (dst_dac_valid == 1'h1)) begin
pattern <= ~pattern;
end
end
assign dac_pattern_s = (pattern == 1'h1) ? 16'h5555 : 16'hAAAA;
// output mux for tx side
always @(posedge clk) begin
src_dac_enable <= dst_dac_enable;
src_dac_valid <= (mode == 0) ? dst_dac_valid : 1'b0;
end
always @(posedge clk) begin
case(mode)
4'h0 : begin
dst_dac_data <= src_dac_data;
end
4'h1 : begin
dst_dac_data <= {cos_tone, sin_tone};
end
4'h2 : begin
dst_dac_data <= dac_prbs;
end
4'h3 : begin
dst_dac_data <= dac_pattern_s;
end
default : begin
dst_dac_data <= src_dac_data;
end
endcase
end
endmodule
|
module system_vga_sync_reset_0_0
(clk,
rst,
active,
hsync,
vsync,
xaddr,
yaddr);
(* x_interface_info = "xilinx.com:signal:clock:1.0 clk CLK" *) input clk;
(* x_interface_info = "xilinx.com:signal:reset:1.0 rst RST" *) input rst;
output active;
output hsync;
output vsync;
output [9:0]xaddr;
output [9:0]yaddr;
wire active;
wire clk;
wire hsync;
wire rst;
wire vsync;
wire [9:0]xaddr;
wire [9:0]yaddr;
system_vga_sync_reset_0_0_vga_sync_reset U0
(.active(active),
.clk(clk),
.hsync(hsync),
.rst(rst),
.vsync(vsync),
.xaddr(xaddr),
.yaddr(yaddr));
endmodule
|
module system_vga_sync_reset_0_0_vga_sync_reset
(xaddr,
yaddr,
active,
hsync,
vsync,
clk,
rst);
output [9:0]xaddr;
output [9:0]yaddr;
output active;
output hsync;
output vsync;
input clk;
input rst;
wire active;
wire active_i_1_n_0;
wire active_i_2_n_0;
wire clk;
wire \h_count_reg[0]_i_1_n_0 ;
wire \h_count_reg[9]_i_1_n_0 ;
wire \h_count_reg[9]_i_3_n_0 ;
wire \h_count_reg[9]_i_4_n_0 ;
wire hsync;
wire hsync_i_1_n_0;
wire hsync_i_2_n_0;
wire hsync_i_3_n_0;
wire [9:1]plusOp;
wire [9:0]plusOp__0;
wire rst;
wire \v_count_reg[9]_i_1_n_0 ;
wire \v_count_reg[9]_i_2_n_0 ;
wire \v_count_reg[9]_i_4_n_0 ;
wire \v_count_reg[9]_i_5_n_0 ;
wire \v_count_reg[9]_i_6_n_0 ;
wire vsync;
wire vsync_i_1_n_0;
wire vsync_i_2_n_0;
wire [9:0]xaddr;
wire [9:0]yaddr;
LUT6 #(
.INIT(64'h0000222A00000000))
active_i_1
(.I0(active_i_2_n_0),
.I1(xaddr[9]),
.I2(xaddr[7]),
.I3(xaddr[8]),
.I4(yaddr[9]),
.I5(rst),
.O(active_i_1_n_0));
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT4 #(
.INIT(16'h7FFF))
active_i_2
(.I0(yaddr[7]),
.I1(yaddr[5]),
.I2(yaddr[6]),
.I3(yaddr[8]),
.O(active_i_2_n_0));
FDRE #(
.INIT(1'b0))
active_reg
(.C(clk),
.CE(1'b1),
.D(active_i_1_n_0),
.Q(active),
.R(1'b0));
LUT1 #(
.INIT(2'h1))
\h_count_reg[0]_i_1
(.I0(xaddr[0]),
.O(\h_count_reg[0]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair8" *)
LUT2 #(
.INIT(4'h6))
\h_count_reg[1]_i_1
(.I0(xaddr[0]),
.I1(xaddr[1]),
.O(plusOp[1]));
(* SOFT_HLUTNM = "soft_lutpair8" *)
LUT3 #(
.INIT(8'h78))
\h_count_reg[2]_i_1
(.I0(xaddr[1]),
.I1(xaddr[0]),
.I2(xaddr[2]),
.O(plusOp[2]));
(* SOFT_HLUTNM = "soft_lutpair4" *)
LUT4 #(
.INIT(16'h7F80))
\h_count_reg[3]_i_1
(.I0(xaddr[2]),
.I1(xaddr[0]),
.I2(xaddr[1]),
.I3(xaddr[3]),
.O(plusOp[3]));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT5 #(
.INIT(32'h7FFF8000))
\h_count_reg[4]_i_1
(.I0(xaddr[3]),
.I1(xaddr[1]),
.I2(xaddr[0]),
.I3(xaddr[2]),
.I4(xaddr[4]),
.O(plusOp[4]));
LUT6 #(
.INIT(64'h7FFFFFFF80000000))
\h_count_reg[5]_i_1
(.I0(xaddr[4]),
.I1(xaddr[2]),
.I2(xaddr[0]),
.I3(xaddr[1]),
.I4(xaddr[3]),
.I5(xaddr[5]),
.O(plusOp[5]));
LUT3 #(
.INIT(8'hD2))
\h_count_reg[6]_i_1
(.I0(xaddr[5]),
.I1(\h_count_reg[9]_i_3_n_0 ),
.I2(xaddr[6]),
.O(plusOp[6]));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT4 #(
.INIT(16'hBF40))
\h_count_reg[7]_i_1
(.I0(\h_count_reg[9]_i_3_n_0 ),
.I1(xaddr[5]),
.I2(xaddr[6]),
.I3(xaddr[7]),
.O(plusOp[7]));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT5 #(
.INIT(32'hFF7F0080))
\h_count_reg[8]_i_1
(.I0(xaddr[7]),
.I1(xaddr[6]),
.I2(xaddr[5]),
.I3(\h_count_reg[9]_i_3_n_0 ),
.I4(xaddr[8]),
.O(plusOp[8]));
LUT6 #(
.INIT(64'h10000000FFFFFFFF))
\h_count_reg[9]_i_1
(.I0(\h_count_reg[9]_i_3_n_0 ),
.I1(xaddr[7]),
.I2(xaddr[8]),
.I3(xaddr[9]),
.I4(\h_count_reg[9]_i_4_n_0 ),
.I5(rst),
.O(\h_count_reg[9]_i_1_n_0 ));
LUT6 #(
.INIT(64'hDFFFFFFF20000000))
\h_count_reg[9]_i_2
(.I0(xaddr[8]),
.I1(\h_count_reg[9]_i_3_n_0 ),
.I2(xaddr[5]),
.I3(xaddr[6]),
.I4(xaddr[7]),
.I5(xaddr[9]),
.O(plusOp[9]));
(* SOFT_HLUTNM = "soft_lutpair4" *)
LUT5 #(
.INIT(32'h7FFFFFFF))
\h_count_reg[9]_i_3
(.I0(xaddr[3]),
.I1(xaddr[1]),
.I2(xaddr[0]),
.I3(xaddr[2]),
.I4(xaddr[4]),
.O(\h_count_reg[9]_i_3_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair5" *)
LUT2 #(
.INIT(4'h1))
\h_count_reg[9]_i_4
(.I0(xaddr[5]),
.I1(xaddr[6]),
.O(\h_count_reg[9]_i_4_n_0 ));
FDRE \h_count_reg_reg[0]
(.C(clk),
.CE(1'b1),
.D(\h_count_reg[0]_i_1_n_0 ),
.Q(xaddr[0]),
.R(\h_count_reg[9]_i_1_n_0 ));
FDRE \h_count_reg_reg[1]
(.C(clk),
.CE(1'b1),
.D(plusOp[1]),
.Q(xaddr[1]),
.R(\h_count_reg[9]_i_1_n_0 ));
FDRE \h_count_reg_reg[2]
(.C(clk),
.CE(1'b1),
.D(plusOp[2]),
.Q(xaddr[2]),
.R(\h_count_reg[9]_i_1_n_0 ));
FDRE \h_count_reg_reg[3]
(.C(clk),
.CE(1'b1),
.D(plusOp[3]),
.Q(xaddr[3]),
.R(\h_count_reg[9]_i_1_n_0 ));
FDRE \h_count_reg_reg[4]
(.C(clk),
.CE(1'b1),
.D(plusOp[4]),
.Q(xaddr[4]),
.R(\h_count_reg[9]_i_1_n_0 ));
FDRE \h_count_reg_reg[5]
(.C(clk),
.CE(1'b1),
.D(plusOp[5]),
.Q(xaddr[5]),
.R(\h_count_reg[9]_i_1_n_0 ));
FDRE \h_count_reg_reg[6]
(.C(clk),
.CE(1'b1),
.D(plusOp[6]),
.Q(xaddr[6]),
.R(\h_count_reg[9]_i_1_n_0 ));
FDRE \h_count_reg_reg[7]
(.C(clk),
.CE(1'b1),
.D(plusOp[7]),
.Q(xaddr[7]),
.R(\h_count_reg[9]_i_1_n_0 ));
FDRE \h_count_reg_reg[8]
(.C(clk),
.CE(1'b1),
.D(plusOp[8]),
.Q(xaddr[8]),
.R(\h_count_reg[9]_i_1_n_0 ));
FDRE \h_count_reg_reg[9]
(.C(clk),
.CE(1'b1),
.D(plusOp[9]),
.Q(xaddr[9]),
.R(\h_count_reg[9]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair5" *)
LUT5 #(
.INIT(32'hABEAFFFF))
hsync_i_1
(.I0(hsync_i_2_n_0),
.I1(xaddr[5]),
.I2(xaddr[6]),
.I3(hsync_i_3_n_0),
.I4(rst),
.O(hsync_i_1_n_0));
LUT3 #(
.INIT(8'hDF))
hsync_i_2
(.I0(xaddr[9]),
.I1(xaddr[8]),
.I2(xaddr[7]),
.O(hsync_i_2_n_0));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT5 #(
.INIT(32'h0001FFFF))
hsync_i_3
(.I0(xaddr[2]),
.I1(xaddr[3]),
.I2(xaddr[0]),
.I3(xaddr[1]),
.I4(xaddr[4]),
.O(hsync_i_3_n_0));
FDRE #(
.INIT(1'b0))
hsync_reg
(.C(clk),
.CE(1'b1),
.D(hsync_i_1_n_0),
.Q(hsync),
.R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair9" *)
LUT1 #(
.INIT(2'h1))
\v_count_reg[0]_i_1
(.I0(yaddr[0]),
.O(plusOp__0[0]));
(* SOFT_HLUTNM = "soft_lutpair9" *)
LUT2 #(
.INIT(4'h6))
\v_count_reg[1]_i_1
(.I0(yaddr[0]),
.I1(yaddr[1]),
.O(plusOp__0[1]));
(* SOFT_HLUTNM = "soft_lutpair7" *)
LUT3 #(
.INIT(8'h78))
\v_count_reg[2]_i_1
(.I0(yaddr[1]),
.I1(yaddr[0]),
.I2(yaddr[2]),
.O(plusOp__0[2]));
(* SOFT_HLUTNM = "soft_lutpair7" *)
LUT4 #(
.INIT(16'h7F80))
\v_count_reg[3]_i_1
(.I0(yaddr[2]),
.I1(yaddr[0]),
.I2(yaddr[1]),
.I3(yaddr[3]),
.O(plusOp__0[3]));
(* SOFT_HLUTNM = "soft_lutpair6" *)
LUT5 #(
.INIT(32'h7FFF8000))
\v_count_reg[4]_i_1
(.I0(yaddr[3]),
.I1(yaddr[1]),
.I2(yaddr[0]),
.I3(yaddr[2]),
.I4(yaddr[4]),
.O(plusOp__0[4]));
LUT6 #(
.INIT(64'h7FFFFFFF80000000))
\v_count_reg[5]_i_1
(.I0(yaddr[4]),
.I1(yaddr[2]),
.I2(yaddr[0]),
.I3(yaddr[1]),
.I4(yaddr[3]),
.I5(yaddr[5]),
.O(plusOp__0[5]));
LUT3 #(
.INIT(8'hD2))
\v_count_reg[6]_i_1
(.I0(yaddr[5]),
.I1(\v_count_reg[9]_i_6_n_0 ),
.I2(yaddr[6]),
.O(plusOp__0[6]));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT4 #(
.INIT(16'hF708))
\v_count_reg[7]_i_1
(.I0(yaddr[5]),
.I1(yaddr[6]),
.I2(\v_count_reg[9]_i_6_n_0 ),
.I3(yaddr[7]),
.O(plusOp__0[7]));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT5 #(
.INIT(32'hBFFF4000))
\v_count_reg[8]_i_1
(.I0(\v_count_reg[9]_i_6_n_0 ),
.I1(yaddr[6]),
.I2(yaddr[5]),
.I3(yaddr[7]),
.I4(yaddr[8]),
.O(plusOp__0[8]));
LUT6 #(
.INIT(64'h00400000FFFFFFFF))
\v_count_reg[9]_i_1
(.I0(\h_count_reg[9]_i_3_n_0 ),
.I1(\v_count_reg[9]_i_4_n_0 ),
.I2(\h_count_reg[9]_i_4_n_0 ),
.I3(yaddr[0]),
.I4(\v_count_reg[9]_i_5_n_0 ),
.I5(rst),
.O(\v_count_reg[9]_i_1_n_0 ));
LUT6 #(
.INIT(64'h0000000000001000))
\v_count_reg[9]_i_2
(.I0(xaddr[5]),
.I1(xaddr[6]),
.I2(xaddr[9]),
.I3(xaddr[8]),
.I4(xaddr[7]),
.I5(\h_count_reg[9]_i_3_n_0 ),
.O(\v_count_reg[9]_i_2_n_0 ));
LUT6 #(
.INIT(64'hBFFFFFFF40000000))
\v_count_reg[9]_i_3
(.I0(\v_count_reg[9]_i_6_n_0 ),
.I1(yaddr[7]),
.I2(yaddr[5]),
.I3(yaddr[6]),
.I4(yaddr[8]),
.I5(yaddr[9]),
.O(plusOp__0[9]));
LUT6 #(
.INIT(64'h0002000000000000))
\v_count_reg[9]_i_4
(.I0(yaddr[9]),
.I1(xaddr[7]),
.I2(yaddr[7]),
.I3(yaddr[8]),
.I4(xaddr[9]),
.I5(xaddr[8]),
.O(\v_count_reg[9]_i_4_n_0 ));
LUT6 #(
.INIT(64'h0000000000000020))
\v_count_reg[9]_i_5
(.I0(yaddr[3]),
.I1(yaddr[4]),
.I2(yaddr[2]),
.I3(yaddr[1]),
.I4(yaddr[6]),
.I5(yaddr[5]),
.O(\v_count_reg[9]_i_5_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair6" *)
LUT5 #(
.INIT(32'h7FFFFFFF))
\v_count_reg[9]_i_6
(.I0(yaddr[3]),
.I1(yaddr[1]),
.I2(yaddr[0]),
.I3(yaddr[2]),
.I4(yaddr[4]),
.O(\v_count_reg[9]_i_6_n_0 ));
FDRE \v_count_reg_reg[0]
(.C(clk),
.CE(\v_count_reg[9]_i_2_n_0 ),
.D(plusOp__0[0]),
.Q(yaddr[0]),
.R(\v_count_reg[9]_i_1_n_0 ));
FDRE \v_count_reg_reg[1]
(.C(clk),
.CE(\v_count_reg[9]_i_2_n_0 ),
.D(plusOp__0[1]),
.Q(yaddr[1]),
.R(\v_count_reg[9]_i_1_n_0 ));
FDRE \v_count_reg_reg[2]
(.C(clk),
.CE(\v_count_reg[9]_i_2_n_0 ),
.D(plusOp__0[2]),
.Q(yaddr[2]),
.R(\v_count_reg[9]_i_1_n_0 ));
FDRE \v_count_reg_reg[3]
(.C(clk),
.CE(\v_count_reg[9]_i_2_n_0 ),
.D(plusOp__0[3]),
.Q(yaddr[3]),
.R(\v_count_reg[9]_i_1_n_0 ));
FDRE \v_count_reg_reg[4]
(.C(clk),
.CE(\v_count_reg[9]_i_2_n_0 ),
.D(plusOp__0[4]),
.Q(yaddr[4]),
.R(\v_count_reg[9]_i_1_n_0 ));
FDRE \v_count_reg_reg[5]
(.C(clk),
.CE(\v_count_reg[9]_i_2_n_0 ),
.D(plusOp__0[5]),
.Q(yaddr[5]),
.R(\v_count_reg[9]_i_1_n_0 ));
FDRE \v_count_reg_reg[6]
(.C(clk),
.CE(\v_count_reg[9]_i_2_n_0 ),
.D(plusOp__0[6]),
.Q(yaddr[6]),
.R(\v_count_reg[9]_i_1_n_0 ));
FDRE \v_count_reg_reg[7]
(.C(clk),
.CE(\v_count_reg[9]_i_2_n_0 ),
.D(plusOp__0[7]),
.Q(yaddr[7]),
.R(\v_count_reg[9]_i_1_n_0 ));
FDRE \v_count_reg_reg[8]
(.C(clk),
.CE(\v_count_reg[9]_i_2_n_0 ),
.D(plusOp__0[8]),
.Q(yaddr[8]),
.R(\v_count_reg[9]_i_1_n_0 ));
FDRE \v_count_reg_reg[9]
(.C(clk),
.CE(\v_count_reg[9]_i_2_n_0 ),
.D(plusOp__0[9]),
.Q(yaddr[9]),
.R(\v_count_reg[9]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFBFFFFFFFF))
vsync_i_1
(.I0(vsync_i_2_n_0),
.I1(yaddr[1]),
.I2(yaddr[2]),
.I3(yaddr[9]),
.I4(yaddr[4]),
.I5(rst),
.O(vsync_i_1_n_0));
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT5 #(
.INIT(32'h7FFFFFFF))
vsync_i_2
(.I0(yaddr[8]),
.I1(yaddr[6]),
.I2(yaddr[5]),
.I3(yaddr[7]),
.I4(yaddr[3]),
.O(vsync_i_2_n_0));
FDRE #(
.INIT(1'b0))
vsync_reg
(.C(clk),
.CE(1'b1),
.D(vsync_i_1_n_0),
.Q(vsync),
.R(1'b0));
endmodule
|
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
|
module sky130_fd_sc_ms__o311a (
X ,
A1 ,
A2 ,
A3 ,
B1 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire or0_out ;
wire and0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
or or0 (or0_out , A2, A1, A3 );
and and0 (and0_out_X , or0_out, B1, C1 );
sky130_fd_sc_ms__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, and0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
|
module tx_test;
// Inputs
reg [7:0] RxD_par;
reg RxD_start;
reg RTS;
reg sys_clk;
wire BaudTick;
// Outputs
wire TxD_ser;
BaudGen baudgen (
.sys_clk(sys_clk),
.BaudTick(BaudTick)
);
// Instantiate the Unit Under Test (UUT)
UART_TX uut (
.RxD_par(RxD_par),
.RxD_start(RxD_start),
.RTS(RTS),
.sys_clk(sys_clk),
.BaudTick(BaudTick),
.TxD_ser(TxD_ser)
);
initial begin
// Initialize Inputs
RxD_par = 8'b01010101;
RxD_start = 0;
RTS = 1;
sys_clk = 0;
// Wait 100 ns for global reset to finish
#4000;
#37 RxD_start = 1;
#74 RxD_start = 0;
// Add stimulus here
end
always begin
#18.5 sys_clk <= !sys_clk;
end
endmodule
|
module pll (
areset,
inclk0,
c0,
locked);
input areset;
input inclk0;
output c0;
output locked;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 areset;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [0:0] sub_wire2 = 1'h0;
wire [4:0] sub_wire3;
wire sub_wire5;
wire sub_wire0 = inclk0;
wire [1:0] sub_wire1 = {sub_wire2, sub_wire0};
wire [0:0] sub_wire4 = sub_wire3[0:0];
wire c0 = sub_wire4;
wire locked = sub_wire5;
altpll altpll_component (
.areset (areset),
.inclk (sub_wire1),
.clk (sub_wire3),
.locked (sub_wire5),
.activeclock (),
.clkbad (),
.clkena ({6{1'b1}}),
.clkloss (),
.clkswitch (1'b0),
.configupdate (1'b0),
.enable0 (),
.enable1 (),
.extclk (),
.extclkena ({4{1'b1}}),
.fbin (1'b1),
.fbmimicbidir (),
.fbout (),
.fref (),
.icdrclk (),
.pfdena (1'b1),
.phasecounterselect ({4{1'b1}}),
.phasedone (),
.phasestep (1'b1),
.phaseupdown (1'b1),
.pllena (1'b1),
.scanaclr (1'b0),
.scanclk (1'b0),
.scanclkena (1'b1),
.scandata (1'b0),
.scandataout (),
.scandone (),
.scanread (1'b0),
.scanwrite (1'b0),
.sclkout0 (),
.sclkout1 (),
.vcooverrange (),
.vcounderrange ());
defparam
altpll_component.bandwidth_type = "AUTO",
altpll_component.clk0_divide_by = 1,
altpll_component.clk0_duty_cycle = 50,
altpll_component.clk0_multiply_by = 4,
altpll_component.clk0_phase_shift = "0",
altpll_component.compensate_clock = "CLK0",
altpll_component.inclk0_input_frequency = 41666,
altpll_component.intended_device_family = "Cyclone IV E",
altpll_component.lpm_hint = "CBX_MODULE_PREFIX=pll",
altpll_component.lpm_type = "altpll",
altpll_component.operation_mode = "NORMAL",
altpll_component.pll_type = "AUTO",
altpll_component.port_activeclock = "PORT_UNUSED",
altpll_component.port_areset = "PORT_USED",
altpll_component.port_clkbad0 = "PORT_UNUSED",
altpll_component.port_clkbad1 = "PORT_UNUSED",
altpll_component.port_clkloss = "PORT_UNUSED",
altpll_component.port_clkswitch = "PORT_UNUSED",
altpll_component.port_configupdate = "PORT_UNUSED",
altpll_component.port_fbin = "PORT_UNUSED",
altpll_component.port_inclk0 = "PORT_USED",
altpll_component.port_inclk1 = "PORT_UNUSED",
altpll_component.port_locked = "PORT_USED",
altpll_component.port_pfdena = "PORT_UNUSED",
altpll_component.port_phasecounterselect = "PORT_UNUSED",
altpll_component.port_phasedone = "PORT_UNUSED",
altpll_component.port_phasestep = "PORT_UNUSED",
altpll_component.port_phaseupdown = "PORT_UNUSED",
altpll_component.port_pllena = "PORT_UNUSED",
altpll_component.port_scanaclr = "PORT_UNUSED",
altpll_component.port_scanclk = "PORT_UNUSED",
altpll_component.port_scanclkena = "PORT_UNUSED",
altpll_component.port_scandata = "PORT_UNUSED",
altpll_component.port_scandataout = "PORT_UNUSED",
altpll_component.port_scandone = "PORT_UNUSED",
altpll_component.port_scanread = "PORT_UNUSED",
altpll_component.port_scanwrite = "PORT_UNUSED",
altpll_component.port_clk0 = "PORT_USED",
altpll_component.port_clk1 = "PORT_UNUSED",
altpll_component.port_clk2 = "PORT_UNUSED",
altpll_component.port_clk3 = "PORT_UNUSED",
altpll_component.port_clk4 = "PORT_UNUSED",
altpll_component.port_clk5 = "PORT_UNUSED",
altpll_component.port_clkena0 = "PORT_UNUSED",
altpll_component.port_clkena1 = "PORT_UNUSED",
altpll_component.port_clkena2 = "PORT_UNUSED",
altpll_component.port_clkena3 = "PORT_UNUSED",
altpll_component.port_clkena4 = "PORT_UNUSED",
altpll_component.port_clkena5 = "PORT_UNUSED",
altpll_component.port_extclk0 = "PORT_UNUSED",
altpll_component.port_extclk1 = "PORT_UNUSED",
altpll_component.port_extclk2 = "PORT_UNUSED",
altpll_component.port_extclk3 = "PORT_UNUSED",
altpll_component.self_reset_on_loss_lock = "ON",
altpll_component.width_clock = 5;
endmodule
|
module zqynq_lab_1_design_auto_pc_1(aclk, aresetn, s_axi_awaddr, s_axi_awlen,
s_axi_awsize, s_axi_awburst, s_axi_awlock, s_axi_awcache, s_axi_awprot, s_axi_awregion,
s_axi_awqos, s_axi_awvalid, s_axi_awready, s_axi_wdata, s_axi_wstrb, s_axi_wlast,
s_axi_wvalid, s_axi_wready, s_axi_bresp, s_axi_bvalid, s_axi_bready, s_axi_araddr,
s_axi_arlen, s_axi_arsize, s_axi_arburst, s_axi_arlock, s_axi_arcache, s_axi_arprot,
s_axi_arregion, s_axi_arqos, s_axi_arvalid, s_axi_arready, s_axi_rdata, s_axi_rresp,
s_axi_rlast, s_axi_rvalid, s_axi_rready, m_axi_awaddr, m_axi_awprot, m_axi_awvalid,
m_axi_awready, m_axi_wdata, m_axi_wstrb, m_axi_wvalid, m_axi_wready, m_axi_bresp,
m_axi_bvalid, m_axi_bready, m_axi_araddr, m_axi_arprot, m_axi_arvalid, m_axi_arready,
m_axi_rdata, m_axi_rresp, m_axi_rvalid, m_axi_rready)
/* synthesis syn_black_box black_box_pad_pin="aclk,aresetn,s_axi_awaddr[31:0],s_axi_awlen[7:0],s_axi_awsize[2:0],s_axi_awburst[1:0],s_axi_awlock[0:0],s_axi_awcache[3:0],s_axi_awprot[2:0],s_axi_awregion[3:0],s_axi_awqos[3:0],s_axi_awvalid,s_axi_awready,s_axi_wdata[31:0],s_axi_wstrb[3:0],s_axi_wlast,s_axi_wvalid,s_axi_wready,s_axi_bresp[1:0],s_axi_bvalid,s_axi_bready,s_axi_araddr[31:0],s_axi_arlen[7:0],s_axi_arsize[2:0],s_axi_arburst[1:0],s_axi_arlock[0:0],s_axi_arcache[3:0],s_axi_arprot[2:0],s_axi_arregion[3:0],s_axi_arqos[3:0],s_axi_arvalid,s_axi_arready,s_axi_rdata[31:0],s_axi_rresp[1:0],s_axi_rlast,s_axi_rvalid,s_axi_rready,m_axi_awaddr[31:0],m_axi_awprot[2:0],m_axi_awvalid,m_axi_awready,m_axi_wdata[31:0],m_axi_wstrb[3:0],m_axi_wvalid,m_axi_wready,m_axi_bresp[1:0],m_axi_bvalid,m_axi_bready,m_axi_araddr[31:0],m_axi_arprot[2:0],m_axi_arvalid,m_axi_arready,m_axi_rdata[31:0],m_axi_rresp[1:0],m_axi_rvalid,m_axi_rready" */;
input aclk;
input aresetn;
input [31:0]s_axi_awaddr;
input [7:0]s_axi_awlen;
input [2:0]s_axi_awsize;
input [1:0]s_axi_awburst;
input [0:0]s_axi_awlock;
input [3:0]s_axi_awcache;
input [2:0]s_axi_awprot;
input [3:0]s_axi_awregion;
input [3:0]s_axi_awqos;
input s_axi_awvalid;
output s_axi_awready;
input [31:0]s_axi_wdata;
input [3:0]s_axi_wstrb;
input s_axi_wlast;
input s_axi_wvalid;
output s_axi_wready;
output [1:0]s_axi_bresp;
output s_axi_bvalid;
input s_axi_bready;
input [31:0]s_axi_araddr;
input [7:0]s_axi_arlen;
input [2:0]s_axi_arsize;
input [1:0]s_axi_arburst;
input [0:0]s_axi_arlock;
input [3:0]s_axi_arcache;
input [2:0]s_axi_arprot;
input [3:0]s_axi_arregion;
input [3:0]s_axi_arqos;
input s_axi_arvalid;
output s_axi_arready;
output [31:0]s_axi_rdata;
output [1:0]s_axi_rresp;
output s_axi_rlast;
output s_axi_rvalid;
input s_axi_rready;
output [31:0]m_axi_awaddr;
output [2:0]m_axi_awprot;
output m_axi_awvalid;
input m_axi_awready;
output [31:0]m_axi_wdata;
output [3:0]m_axi_wstrb;
output m_axi_wvalid;
input m_axi_wready;
input [1:0]m_axi_bresp;
input m_axi_bvalid;
output m_axi_bready;
output [31:0]m_axi_araddr;
output [2:0]m_axi_arprot;
output m_axi_arvalid;
input m_axi_arready;
input [31:0]m_axi_rdata;
input [1:0]m_axi_rresp;
input m_axi_rvalid;
output m_axi_rready;
endmodule
|
module sky130_fd_sc_ls__a21oi_1 (
Y ,
A1 ,
A2 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__a21oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
|
module sky130_fd_sc_ls__a21oi_1 (
Y ,
A1,
A2,
B1
);
output Y ;
input A1;
input A2;
input B1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__a21oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1)
);
endmodule
|
module clock_counter(
input clk_i, //often, "tags" are added to variables to denote what they do for the user
input reset_n, //here, 'i' is used for input and 'o' for the output, while 'n' specifies an active low signal ("not")
output reg clk_o
);
reg [14:0] count; //register stores the counter value so that it can be modified on a clock edge. register size needs to store as large of a number as the counter reaches
//for this implementation, count must reach 415999, so 2^n >= 415999, n = 19
always @ (posedge clk_i, negedge reset_n)
begin
count <= count + 1; //at every positive edge, the counter is increased by 1
if(!reset_n)
begin
clk_o <= 0;
count <= 0; //if reset (active low) is pushed, the counter is reset
end
else
if(count >= 5000) //initial 17330 //count value of greater than or equal to this value causes the output clock to be inverted. the resulting frequency will be input_frequency/(1+count_value)
begin //for this implementation, a frequency of 5 Hz was desired, so 2.08e6/5 - 1 = 415999
clk_o <= ~clk_o;
count <= 0; //resets the counter after the output clock has been inverted
end
end
endmodule
|
module header
// Internal signals
//
// Generated Signal List
//
//
// End of Generated Signal List
//
// %COMPILER_OPTS%
//
// Generated Signal Assignments
//
//
// Generated Instances and Port Mappings
//
endmodule
|
module rx
(
output [7:0]cmd,
output [51:0]param,
output package_complete,
output crc_check_pass,
output [15:0]crc_16,
output en_crc5,
output en_crc16,
input pie_code,
input clk_dpie,
input clk_crc5,
input clk_crc16,
input rst_n,
input rst_for_new_package,
input rst_crc16,
input reply_data,
input en_crc16_for_rpy
);
fs_detector fs_detector_1
(
.sync(sync),
.pie_code(pie_code),
.clk_fsd(clk_dpie),
.rst_n(rst_n),
.package_complete(package_complete)
);
crc5 crc5_1
(
.crc5_check_pass(crc5_check_pass),
.clk_crc5(clk_crc5),
.rst_for_new_package(rst_for_new_package),
.data(pie_code),
.sync(sync),
.package_complete(package_complete)
);
crc16 crc16_1
(
.crc16_check_pass_reg(crc16_check_pass_reg),
.crc_16(crc_16),
.clk_crc16(clk_crc16),
.rst_crc16(rst_crc16),
.data(pie_code),
.reply_data(reply_data),
.sync(sync),
.package_complete(package_complete),
.en_crc16_for_rpy(en_crc16_for_rpy)
);
cmd_buf cmd_buf_1
(
.cmd(cmd),
.param(param),
.package_complete(package_complete),
.en_crc5(en_crc5),
.en_crc16(en_crc16),
.clk_cmd(clk_dpie),
.rst_for_new_package(rst_for_new_package),
.bits_in(pie_code),
.sync(sync)
);
assign crc_check_pass = crc5_check_pass | crc16_check_pass_reg;
endmodule
|
module fa1242(
output ml,
output md,
output mc,
output rstb,
input clk_s, // should be slower than 5Mhz
input rst);
parameter IDLE = 0;
parameter RST = 1;
parameter RST_WAIT = 2;
parameter SET_FUNCTION = 3;
parameter SET_FUNCTION_WAIT = 4;
// attn settings
wire [10:0] al = 0;
wire [10:0] ar = 0;
// mode settings
wire [1:0] om = 2'b0; // outlp: L, outlm: -L, outrp: R, outrm: -R
wire [1:0] bit = 2'b10; // 24bit
wire [1:0] zm = 2'b0; // open drain + pull up
wire atc = 2'b0; // attn. common for LR (off)
wire mute = 2'b0; // unmute
wire [1:0] emph = 2'b0; // no de-emphasis
// for reset
reg [4:0] wait_counter;
parameter WAIT_COUNTER_MAX = 5'h1f;
// for mode set
reg [1:0] mode;
reg [4:0] mode_set_counter;
// FSM transition
reg [3:0] state;
initial state = IDLE;
always @(posedge clk_s or rst) begin
if(rst) begin
state <= RST;
wait_counter <= 0;
mode_set_counter <= 0;
end else begin
case(state)
IDLE: state <= IDLE;
RST: begin
state <= RST_WAIT;
wait_counter <= 0;
end
RST_WAIT: begin
if(wait_counter == WAIT_COUNTER_MAX) begin
state <= SET_FUNCTION;
mode <= 2'd0;
mode_set_counter <= 2'd0;
end else begin
wait_counter <= wait_counter + 1;
end
end
SET_FUNCTION: begin
if(mode_set_counter == 5'h1f) begin
mode_set_counter <= 0;
state <= SET_FUNCTION_WAIT;
wait_counter <= 0;
end else
mode_set_counter <= mode_set_counter + 1;
end
SET_FUNCTION_WAIT: begin
if(wait_counter == WAIT_COUNTER_MAX) begin
if(mode == 2'd2)
// all done!
state <= IDLE;
else begin
// set next mode vector
state <= SET_FUNCTION;
mode <= mode + 1;
mode_set_counter <= 2'd0;
end
end else begin
wait_counter <= wait_counter + 1;
end
end
default: state <= IDLE;
endcase
end
end
assign rstb = (state == RST);
assign mc = mode_set_counter[0];
assign ml = ~((state == SET_FUNCTION_WAIT) && (wait_counter == 2));
function mode_set_data(
input [3:0] mode_set_idx,
input [1:0] mode);
reg [10:0] mode3;
begin
mode3 = {om, /*rst*/1'b0, bit, zm, atc, mute, emph};
if(mode_set_idx < 5)
case(mode_set_idx)
// res
4'd00: mode_set_data = 0;
4'd01: mode_set_data = 0;
4'd02: mode_set_data = 0;
// mode
4'd03: mode_set_data = mode[1];
4'd04: mode_set_data = mode[0];
endcase
else
case(mode)
2'd0: mode_set_data = al[10+5-mode_set_idx];
2'd1: mode_set_data = ar[10+5-mode_set_idx];
2'd2: mode_set_data = mode3[10+5-mode_set_idx];
endcase
end
endfunction
assign md = mode_set_data(mode_set_counter[4:1], mode);
endmodule
|
module REGISTER_TEST;
// Inputs
reg clk;
reg Reset;
reg [4:0] R_Addr_A;
reg [4:0] R_Addr_B;
reg [4:0] W_Addr;
reg [31:0] W_Data;
reg Write_Reg;
// Outputs
wire [31:0] R_Data_A;
wire [31:0] R_Data_B;
// Instantiate the Unit Under Test (UUT)
register uut (
.clk(clk),
.Reset(Reset),
.R_Addr_A(R_Addr_A),
.R_Addr_B(R_Addr_B),
.W_Addr(W_Addr),
.W_Data(W_Data),
.Write_Reg(Write_Reg),
.R_Data_A(R_Data_A),
.R_Data_B(R_Data_B)
);
initial begin
// Initialize Inputs
clk = 0;
Reset = 1;
# 10;
Reset = 1;
R_Addr_A = 1;
R_Addr_B = 2;
W_Addr = 10;
W_Data = 3;
Write_Reg = 1;
#10;
Reset = 0;
R_Addr_A = 0;
R_Addr_B = 1;
W_Addr = 0;
W_Data = 3;
Write_Reg = 1;
#10;
Reset = 0;
R_Addr_A = 1;
R_Addr_B = 2;
W_Addr = 1;
W_Data = 4;
Write_Reg = 1;
#10;
Reset = 0;
R_Addr_A = 2;
R_Addr_B = 3;
W_Addr = 2;
W_Data = 5;
Write_Reg = 1;
#10;
Reset = 0;
R_Addr_A = 3;
R_Addr_B = 4;
W_Addr = 3;
W_Data = 6;
Write_Reg = 1;
#10;
Reset = 0;
R_Addr_A = 4;
R_Addr_B = 5;
W_Addr = 4;
W_Data = 7;
Write_Reg = 1;
#10;
Reset = 0;
R_Addr_A = 5;
R_Addr_B = 6;
W_Addr = 5;
W_Data = 8;
Write_Reg = 1;
#10;
Reset = 0;
R_Addr_A = 6;
R_Addr_B = 7;
W_Addr = 6;
W_Data = 9;
Write_Reg = 1;
#10;
Reset = 0;
R_Addr_A = 7;
R_Addr_B = 8;
W_Addr = 7;
W_Data = 10;
Write_Reg = 1;
#10;
Reset = 0;
R_Addr_A = 8;
R_Addr_B = 9;
W_Addr = 8;
W_Data = 11;
Write_Reg = 1;
#10;
Reset = 0;
R_Addr_A = 9;
R_Addr_B = 10;
W_Addr = 9;
W_Data = 12;
Write_Reg = 1;
#10;
Reset = 0;
R_Addr_A = 10;
R_Addr_B = 11;
W_Addr = 10;
W_Data = 13;
Write_Reg = 1;
#10;
Reset = 0;
R_Addr_A = 11;
R_Addr_B = 12;
W_Addr = 11;
W_Data = 14;
Write_Reg = 1;
#10;
Reset = 0;
R_Addr_A = 0;
R_Addr_B = 1;
W_Addr = 1;
W_Data = 1;
Write_Reg = 0;
#10;
Reset = 0;
R_Addr_A = 1;
R_Addr_B = 2;
W_Addr = 1;
W_Data = 1;
Write_Reg = 0;
#10;
Reset = 0;
R_Addr_A = 2;
R_Addr_B = 3;
W_Addr = 1;
W_Data = 1;
Write_Reg = 0;
#10;
Reset = 0;
R_Addr_A = 3;
R_Addr_B = 4;
W_Addr = 1;
W_Data = 1;
Write_Reg = 0;
#10;
Reset = 0;
R_Addr_A = 4;
R_Addr_B = 5;
W_Addr = 1;
W_Data = 1;
Write_Reg = 0;
#10;
Reset = 0;
R_Addr_A = 5;
R_Addr_B = 6;
W_Addr = 1;
W_Data = 1;
Write_Reg = 0;
#10;
Reset = 0;
R_Addr_A = 6;
R_Addr_B = 7;
W_Addr = 1;
W_Data = 1;
Write_Reg = 0;
#10;
Reset = 0;
R_Addr_A = 7;
R_Addr_B = 8;
W_Addr = 1;
W_Data = 1;
Write_Reg = 0;
#10;
Reset = 0;
R_Addr_A = 8;
R_Addr_B = 9;
W_Addr = 1;
W_Data = 1;
Write_Reg = 0;
#10;
Reset = 0;
R_Addr_A = 9;
R_Addr_B = 10;
W_Addr = 1;
W_Data = 1;
Write_Reg = 0;
#10;
Reset = 0;
R_Addr_A = 10;
R_Addr_B = 11;
W_Addr = 1;
W_Data = 1;
Write_Reg = 0;
#10;
Reset = 0;
R_Addr_A = 11;
R_Addr_B = 12;
W_Addr = 1;
W_Data = 1;
Write_Reg = 0;
#10;
end
always #2 clk = ~clk;
endmodule
|
module sky130_fd_sc_ls__fa_1 (
COUT,
SUM ,
A ,
B ,
CIN ,
VPWR,
VGND,
VPB ,
VNB
);
output COUT;
output SUM ;
input A ;
input B ;
input CIN ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__fa base (
.COUT(COUT),
.SUM(SUM),
.A(A),
.B(B),
.CIN(CIN),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
|
module sky130_fd_sc_ls__fa_1 (
COUT,
SUM ,
A ,
B ,
CIN
);
output COUT;
output SUM ;
input A ;
input B ;
input CIN ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__fa base (
.COUT(COUT),
.SUM(SUM),
.A(A),
.B(B),
.CIN(CIN)
);
endmodule
|
module sky130_fd_io__top_sio (
//# {{data|Data Signals}}
input SLOW ,
output IN ,
input INP_DIS ,
output IN_H ,
input OUT ,
inout PAD ,
inout PAD_A_ESD_0_H,
inout PAD_A_ESD_1_H,
inout PAD_A_NOESD_H,
//# {{control|Control Signals}}
input [2:0] DM ,
input ENABLE_H ,
input HLD_H_N ,
input HLD_OVR ,
input IBUF_SEL ,
input OE_N ,
//# {{power|Power}}
input VREG_EN ,
input VTRIP_SEL ,
input REFLEAK_BIAS ,
input VINREF ,
input VOUTREF ,
output TIE_LO_ESD
);
// Voltage supply signals
supply0 VSSIO ;
supply0 VSSIO_Q;
supply0 VSSD ;
supply1 VCCD ;
supply1 VDDIO ;
supply1 VCCHIB ;
supply1 VDDIO_Q;
endmodule
|
module design_1_sample_generator_0_1 (
FrameSize,
En,
AXI_En,
m_axis_tdata,
m_axis_tstrb,
m_axis_tlast,
m_axis_tvalid,
m_axis_tready,
m_axis_aclk,
m_axis_aresetn,
s_axis_tdata,
s_axis_tstrb,
s_axis_tlast,
s_axis_tvalid,
s_axis_tready,
s_axis_aclk,
s_axis_aresetn
);
input wire [7 : 0] FrameSize;
input wire En;
input wire AXI_En;
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS TDATA" *)
output wire [31 : 0] m_axis_tdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS TSTRB" *)
output wire [3 : 0] m_axis_tstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS TLAST" *)
output wire m_axis_tlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS TVALID" *)
output wire m_axis_tvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS TREADY" *)
input wire m_axis_tready;
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 M_AXIS_CLK CLK" *)
input wire m_axis_aclk;
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 M_AXIS_RST RST" *)
input wire m_axis_aresetn;
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS TDATA" *)
input wire [31 : 0] s_axis_tdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS TSTRB" *)
input wire [3 : 0] s_axis_tstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS TLAST" *)
input wire s_axis_tlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS TVALID" *)
input wire s_axis_tvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS TREADY" *)
output wire s_axis_tready;
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 S_AXIS_CLK CLK" *)
input wire s_axis_aclk;
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 S_AXIS_RST RST" *)
input wire s_axis_aresetn;
sample_generator_v1_0 #(
.C_M_AXIS_TDATA_WIDTH(32), // Width of S_AXIS address bus. The slave accepts the read and write addresses of width C_M_AXIS_TDATA_WIDTH.
.C_M_AXIS_START_COUNT(32), // Start count is the numeber of clock cycles the master will wait before initiating/issuing any transaction.
.C_S_AXIS_TDATA_WIDTH(32) // AXI4Stream sink: Data Width
) inst (
.FrameSize(FrameSize),
.En(En),
.AXI_En(AXI_En),
.m_axis_tdata(m_axis_tdata),
.m_axis_tstrb(m_axis_tstrb),
.m_axis_tlast(m_axis_tlast),
.m_axis_tvalid(m_axis_tvalid),
.m_axis_tready(m_axis_tready),
.m_axis_aclk(m_axis_aclk),
.m_axis_aresetn(m_axis_aresetn),
.s_axis_tdata(s_axis_tdata),
.s_axis_tstrb(s_axis_tstrb),
.s_axis_tlast(s_axis_tlast),
.s_axis_tvalid(s_axis_tvalid),
.s_axis_tready(s_axis_tready),
.s_axis_aclk(s_axis_aclk),
.s_axis_aresetn(s_axis_aresetn)
);
endmodule
|
module sky130_fd_sc_ls__fill ();
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// No contents.
endmodule
|
module wishbone_interconnect (
//control signals
input clk,
input rst,
//wishbone master signals
input i_m_we,
input i_m_stb,
input i_m_cyc,
input [3:0] i_m_sel,
input [31:0] i_m_adr,
input [31:0] i_m_dat,
output reg [31:0] o_m_dat,
output reg o_m_ack,
output o_m_int,
//Slave 0
output o_s0_we,
output o_s0_cyc,
output o_s0_stb,
output [3:0] o_s0_sel,
input i_s0_ack,
output [31:0] o_s0_dat,
input [31:0] i_s0_dat,
output [31:0] o_s0_adr,
input i_s0_int,
//Slave 1
output o_s1_we,
output o_s1_cyc,
output o_s1_stb,
output [3:0] o_s1_sel,
input i_s1_ack,
output [31:0] o_s1_dat,
input [31:0] i_s1_dat,
output [31:0] o_s1_adr,
input i_s1_int,
//Slave 2
output o_s2_we,
output o_s2_cyc,
output o_s2_stb,
output [3:0] o_s2_sel,
input i_s2_ack,
output [31:0] o_s2_dat,
input [31:0] i_s2_dat,
output [31:0] o_s2_adr,
input i_s2_int
);
parameter ADDR_0 = 0;
parameter ADDR_1 = 1;
parameter ADDR_2 = 2;
parameter ADDR_FF = 8'hFF;
//state
//wishbone slave signals
//this should be parameterized
wire [7:0]slave_select;
wire [31:0] interrupts;
assign slave_select = i_m_adr[31:24];
//data in from slave
always @ (slave_select or i_s0_dat or i_s1_dat or i_s2_dat or interrupts) begin
case (slave_select)
ADDR_0: begin
o_m_dat <= i_s0_dat;
end
ADDR_1: begin
o_m_dat <= i_s1_dat;
end
ADDR_2: begin
o_m_dat <= i_s2_dat;
end
default: begin
o_m_dat <= interrupts;
end
endcase
end
//ack in from slave
always @ (slave_select or i_s0_ack or i_s1_ack or i_s2_ack) begin
case (slave_select)
ADDR_0: begin
o_m_ack <= i_s0_ack;
end
ADDR_1: begin
o_m_ack <= i_s1_ack;
end
ADDR_2: begin
o_m_ack <= i_s2_ack;
end
default: begin
o_m_ack <= 1'h0;
end
endcase
end
//int in from slave
assign interrupts[0] = i_s0_int;
assign interrupts[1] = i_s1_int;
assign interrupts[2] = i_s2_int;
assign interrupts[31:3] = 0;
assign o_m_int = (interrupts != 0);
assign o_s0_we = (slave_select == ADDR_0) ? i_m_we: 1'b0;
assign o_s0_stb = (slave_select == ADDR_0) ? i_m_stb: 1'b0;
assign o_s0_sel = (slave_select == ADDR_0) ? i_m_sel: 4'h0;
assign o_s0_cyc = (slave_select == ADDR_0) ? i_m_cyc: 1'b0;
assign o_s0_adr = (slave_select == ADDR_0) ? {8'h0, i_m_adr[23:0]}: 32'h0;
assign o_s0_dat = (slave_select == ADDR_0) ? i_m_dat: 32'h0;
assign o_s1_we = (slave_select == ADDR_1) ? i_m_we: 1'b0;
assign o_s1_stb = (slave_select == ADDR_1) ? i_m_stb: 1'b0;
assign o_s1_sel = (slave_select == ADDR_1) ? i_m_sel: 4'h0;
assign o_s1_cyc = (slave_select == ADDR_1) ? i_m_cyc: 1'b0;
assign o_s1_adr = (slave_select == ADDR_1) ? {8'h0, i_m_adr[23:0]}: 32'h0;
assign o_s1_dat = (slave_select == ADDR_1) ? i_m_dat: 32'h0;
assign o_s2_we = (slave_select == ADDR_2) ? i_m_we: 1'b0;
assign o_s2_stb = (slave_select == ADDR_2) ? i_m_stb: 1'b0;
assign o_s2_sel = (slave_select == ADDR_2) ? i_m_sel: 4'h0;
assign o_s2_cyc = (slave_select == ADDR_2) ? i_m_cyc: 1'b0;
assign o_s2_adr = (slave_select == ADDR_2) ? {8'h0, i_m_adr[23:0]}: 32'h0;
assign o_s2_dat = (slave_select == ADDR_2) ? i_m_dat: 32'h0;
endmodule
|
module ogfx_backend_lut_fifo (
// OUTPUTs
frame_data_request_o, // Request for next frame data
refresh_data_o, // Display Refresh data
refresh_data_ready_o, // Display Refresh data ready
`ifdef WITH_PROGRAMMABLE_LUT
lut_ram_addr_o, // LUT-RAM address
lut_ram_cen_o, // LUT-RAM enable (active low)
`endif
// INPUTs
mclk, // Main system clock
puc_rst, // Main system reset
frame_data_i, // Frame data
frame_data_ready_i, // Frame data ready
gfx_mode_i, // Video mode (1xx:16bpp / 011:8bpp / 010:4bpp / 001:2bpp / 000:1bpp)
`ifdef WITH_PROGRAMMABLE_LUT
lut_ram_dout_i, // LUT-RAM data output
lut_ram_dout_rdy_nxt_i, // LUT-RAM data output ready during next cycle
`endif
refresh_active_i, // Display refresh on going
refresh_data_request_i, // Request for next refresh data
hw_lut_palette_sel_i, // Hardware LUT palette configuration
hw_lut_bgcolor_i, // Hardware LUT background-color selection
hw_lut_fgcolor_i, // Hardware LUT foreground-color selection
sw_lut_enable_i, // Refresh LUT-RAM enable
sw_lut_bank_select_i // Refresh LUT-RAM bank selection
);
// OUTPUTs
//=========
output frame_data_request_o; // Request for next frame data
output [15:0] refresh_data_o; // Display Refresh data
output refresh_data_ready_o; // Display Refresh data ready
`ifdef WITH_PROGRAMMABLE_LUT
output [`LRAM_MSB:0] lut_ram_addr_o; // LUT-RAM address
output lut_ram_cen_o; // LUT-RAM enable (active low)
`endif
// INPUTs
//=========
input mclk; // Main system clock
input puc_rst; // Main system reset
input [15:0] frame_data_i; // Frame data
input frame_data_ready_i; // Frame data ready
input [2:0] gfx_mode_i; // Video mode (1xx:16bpp / 011:8bpp / 010:4bpp / 001:2bpp / 000:1bpp)
`ifdef WITH_PROGRAMMABLE_LUT
input [15:0] lut_ram_dout_i; // LUT-RAM data output
input lut_ram_dout_rdy_nxt_i; // LUT-RAM data output ready during next cycle
`endif
input refresh_active_i; // Display refresh on going
input refresh_data_request_i; // Request for next refresh data
input [2:0] hw_lut_palette_sel_i; // Hardware LUT palette configuration
input [3:0] hw_lut_bgcolor_i; // Hardware LUT background-color selection
input [3:0] hw_lut_fgcolor_i; // Hardware LUT foreground-color selection
input sw_lut_enable_i; // Refresh LUT-RAM enable
input sw_lut_bank_select_i; // Refresh LUT-RAM bank selection
//=============================================================================
// 1) WIRE, REGISTERS AND PARAMETER DECLARATION
//=============================================================================
// State machine registers
reg [1:0] lut_state;
reg [1:0] lut_state_nxt;
// State definition
parameter STATE_IDLE = 0,
STATE_FRAME_DATA = 1,
STATE_LUT_DATA = 2,
STATE_HOLD = 3;
// Some parameter(s)
parameter FIFO_EMPTY = 3'h0,
FIFO_FULL = 3'h5;
// Video modes decoding
wire gfx_mode_1_bpp = (gfx_mode_i == 3'b000);
wire gfx_mode_2_bpp = (gfx_mode_i == 3'b001);
wire gfx_mode_4_bpp = (gfx_mode_i == 3'b010);
wire gfx_mode_8_bpp = (gfx_mode_i == 3'b011);
wire gfx_mode_16_bpp = ~(gfx_mode_8_bpp | gfx_mode_4_bpp |
gfx_mode_2_bpp | gfx_mode_1_bpp);
// Others
reg [2:0] fifo_counter;
wire [2:0] fifo_counter_nxt;
//============================================================================
// 2) HARD CODED LOOKUP TABLE
//============================================================================
// 16 full CGA color selection
parameter [3:0] CGA_BLACK = 4'h0,
CGA_BLUE = 4'h1,
CGA_GREEN = 4'h2,
CGA_CYAN = 4'h3,
CGA_RED = 4'h4,
CGA_MAGENTA = 4'h5,
CGA_BROWN = 4'h6,
CGA_LIGHT_GRAY = 4'h7,
CGA_GRAY = 4'h8,
CGA_LIGHT_BLUE = 4'h9,
CGA_LIGHT_GREEN = 4'hA,
CGA_LIGHT_CYAN = 4'hB,
CGA_LIGHT_RED = 4'hC,
CGA_LIGHT_MAGENTA = 4'hD,
CGA_YELLOW = 4'hE,
CGA_WHITE = 4'hF;
// Decode CGA 4 color mode (2bpp)
wire cga_palette0_hi = (hw_lut_palette_sel_i==3'h0);
wire cga_palette0_lo = (hw_lut_palette_sel_i==3'h1);
wire cga_palette1_hi = (hw_lut_palette_sel_i==3'h2);
wire cga_palette1_lo = (hw_lut_palette_sel_i==3'h3);
wire cga_palette2_hi = (hw_lut_palette_sel_i==3'h4);
wire cga_palette2_lo = (hw_lut_palette_sel_i==3'h5) | (hw_lut_palette_sel_i==3'h6) | (hw_lut_palette_sel_i==3'h7);
// LUT color decoding
// 1 BPP
wire [3:0] lut_hw_sel_1bpp = ({4{gfx_mode_1_bpp & (frame_data_i[0] ==1'b0 )}} & hw_lut_bgcolor_i ) | // 1 bpp: Black (default bgcolor)
({4{gfx_mode_1_bpp & (frame_data_i[0] ==1'b1 )}} & hw_lut_fgcolor_i ) ; // White (default fgcolor)
// 2 BPP (Palette #0, low-intensity)
wire [3:0] lut_hw_sel_2bpp = ({4{gfx_mode_2_bpp & cga_palette0_lo & (frame_data_i[1:0]==2'b00)}} & hw_lut_bgcolor_i ) | // 2 bpp: Black (default bgcolor)
({4{gfx_mode_2_bpp & cga_palette0_lo & (frame_data_i[1:0]==2'b01)}} & CGA_GREEN ) | // Green
({4{gfx_mode_2_bpp & cga_palette0_lo & (frame_data_i[1:0]==2'b10)}} & CGA_RED ) | // Red
({4{gfx_mode_2_bpp & cga_palette0_lo & (frame_data_i[1:0]==2'b11)}} & CGA_BROWN ) | // Brown
// 2 BPP (Palette #0, high-intensity)
({4{gfx_mode_2_bpp & cga_palette0_hi & (frame_data_i[1:0]==2'b00)}} & hw_lut_bgcolor_i ) | // 2 bpp: Black (default bgcolor)
({4{gfx_mode_2_bpp & cga_palette0_hi & (frame_data_i[1:0]==2'b01)}} & CGA_LIGHT_GREEN ) | // Light-Green
({4{gfx_mode_2_bpp & cga_palette0_hi & (frame_data_i[1:0]==2'b10)}} & CGA_LIGHT_RED ) | // Light-Red
({4{gfx_mode_2_bpp & cga_palette0_hi & (frame_data_i[1:0]==2'b11)}} & CGA_YELLOW ) | // Yellow
// 2 BPP (Palette #1, low-intensity)
({4{gfx_mode_2_bpp & cga_palette1_lo & (frame_data_i[1:0]==2'b00)}} & hw_lut_bgcolor_i ) | // 2 bpp: Black (default bgcolor)
({4{gfx_mode_2_bpp & cga_palette1_lo & (frame_data_i[1:0]==2'b01)}} & CGA_CYAN ) | // Cyan
({4{gfx_mode_2_bpp & cga_palette1_lo & (frame_data_i[1:0]==2'b10)}} & CGA_MAGENTA ) | // Magenta
({4{gfx_mode_2_bpp & cga_palette1_lo & (frame_data_i[1:0]==2'b11)}} & CGA_LIGHT_GRAY ) | // Light-Gray
// 2 BPP (Palette #1, high-intensity)
({4{gfx_mode_2_bpp & cga_palette1_hi & (frame_data_i[1:0]==2'b00)}} & hw_lut_bgcolor_i ) | // 2 bpp: Black (default bgcolor)
({4{gfx_mode_2_bpp & cga_palette1_hi & (frame_data_i[1:0]==2'b01)}} & CGA_LIGHT_CYAN ) | // Light-Cyan
({4{gfx_mode_2_bpp & cga_palette1_hi & (frame_data_i[1:0]==2'b10)}} & CGA_LIGHT_MAGENTA) | // Light-Magenta
({4{gfx_mode_2_bpp & cga_palette1_hi & (frame_data_i[1:0]==2'b11)}} & CGA_WHITE ) | // White
// 2 BPP (Palette #2, low-intensity)
({4{gfx_mode_2_bpp & cga_palette2_lo & (frame_data_i[1:0]==2'b00)}} & hw_lut_bgcolor_i ) | // 2 bpp: Black (default bgcolor)
({4{gfx_mode_2_bpp & cga_palette2_lo & (frame_data_i[1:0]==2'b01)}} & CGA_CYAN ) | // Cyan
({4{gfx_mode_2_bpp & cga_palette2_lo & (frame_data_i[1:0]==2'b10)}} & CGA_RED ) | // Red
({4{gfx_mode_2_bpp & cga_palette2_lo & (frame_data_i[1:0]==2'b11)}} & CGA_LIGHT_GRAY ) | // Light-Gray
// 2 BPP (Palette #2, high-intensity)
({4{gfx_mode_2_bpp & cga_palette2_hi & (frame_data_i[1:0]==2'b00)}} & hw_lut_bgcolor_i ) | // 2 bpp: Black (default bgcolor)
({4{gfx_mode_2_bpp & cga_palette2_hi & (frame_data_i[1:0]==2'b01)}} & CGA_LIGHT_CYAN ) | // Light-Cyan
({4{gfx_mode_2_bpp & cga_palette2_hi & (frame_data_i[1:0]==2'b10)}} & CGA_LIGHT_RED ) | // Light-Red
({4{gfx_mode_2_bpp & cga_palette2_hi & (frame_data_i[1:0]==2'b11)}} & CGA_WHITE ) ; // White
// 4 BPP (full CGA 16-color palette)
wire [3:0] lut_hw_sel_4bpp = ({4{gfx_mode_4_bpp}} & frame_data_i[3:0]);
wire [3:0] lut_hw_color_sel = lut_hw_sel_4bpp | lut_hw_sel_2bpp | lut_hw_sel_1bpp;
// Color encoding for 1-bit / 2-bit and 4-bit modes
reg [15:0] lut_hw_data_1_2_4_bpp;
always @(lut_hw_color_sel)
case(lut_hw_color_sel)
CGA_BLACK : lut_hw_data_1_2_4_bpp = {5'b00000, 6'b000000, 5'b00000}; // Black
CGA_BLUE : lut_hw_data_1_2_4_bpp = {5'b00000, 6'b000000, 5'b10101}; // Blue
CGA_GREEN : lut_hw_data_1_2_4_bpp = {5'b00000, 6'b101011, 5'b00000}; // Green
CGA_CYAN : lut_hw_data_1_2_4_bpp = {5'b00000, 6'b101011, 5'b10101}; // Cyan
CGA_RED : lut_hw_data_1_2_4_bpp = {5'b10101, 6'b000000, 5'b00000}; // Red
CGA_MAGENTA : lut_hw_data_1_2_4_bpp = {5'b10101, 6'b000000, 5'b10101}; // Magenta
CGA_BROWN : lut_hw_data_1_2_4_bpp = {5'b10101, 6'b010101, 5'b00000}; // Brown
CGA_LIGHT_GRAY : lut_hw_data_1_2_4_bpp = {5'b10101, 6'b101011, 5'b10101}; // Light Gray
CGA_GRAY : lut_hw_data_1_2_4_bpp = {5'b01011, 6'b010101, 5'b01011}; // Gray
CGA_LIGHT_BLUE : lut_hw_data_1_2_4_bpp = {5'b01011, 6'b010101, 5'b11111}; // Light Blue
CGA_LIGHT_GREEN : lut_hw_data_1_2_4_bpp = {5'b01011, 6'b111111, 5'b01011}; // Light Green
CGA_LIGHT_CYAN : lut_hw_data_1_2_4_bpp = {5'b01011, 6'b111111, 5'b11111}; // Light Cyan
CGA_LIGHT_RED : lut_hw_data_1_2_4_bpp = {5'b11111, 6'b010101, 5'b01011}; // Light Red
CGA_LIGHT_MAGENTA : lut_hw_data_1_2_4_bpp = {5'b11111, 6'b010101, 5'b11111}; // Light Magenta
CGA_YELLOW : lut_hw_data_1_2_4_bpp = {5'b11111, 6'b111111, 5'b01011}; // Yellow
CGA_WHITE : lut_hw_data_1_2_4_bpp = {5'b11111, 6'b111111, 5'b11111}; // White
// pragma coverage off
default : lut_hw_data_1_2_4_bpp = 16'h0000;
// pragma coverage on
endcase
// 8-bit truecolor RGB mapping (3-bit red / 3-bit green / 2-bit blue)
wire [15:0] lut_hw_data_8_bpp = {frame_data_i[7],frame_data_i[6],frame_data_i[5],frame_data_i[5],frame_data_i[5], // 8 bpp: R = D<7,6,5,5,5>
frame_data_i[4],frame_data_i[3],frame_data_i[2],frame_data_i[2],frame_data_i[2],frame_data_i[2], // G = D<4,3,2,2,2,2>
frame_data_i[1],frame_data_i[0],frame_data_i[0],frame_data_i[0],frame_data_i[0]}; // B = D<1,0,0,0,0>
wire [15:0] lut_hw_data = (lut_hw_data_1_2_4_bpp & {16{gfx_mode_1_bpp | gfx_mode_2_bpp | gfx_mode_4_bpp}}) |
(lut_hw_data_8_bpp & {16{gfx_mode_8_bpp}});
wire lut_hw_enabled = ~gfx_mode_16_bpp & ~sw_lut_enable_i;
wire lut_sw_enabled = ~gfx_mode_16_bpp & sw_lut_enable_i;
//============================================================================
// 3) STATE MACHINE
//============================================================================
//--------------------------------
// States Transitions
//--------------------------------
always @(lut_state or refresh_active_i or frame_data_ready_i or
`ifdef WITH_PROGRAMMABLE_LUT
lut_sw_enabled or lut_ram_dout_rdy_nxt_i or
`endif
fifo_counter_nxt)
case(lut_state)
STATE_IDLE : lut_state_nxt = ~refresh_active_i ? STATE_IDLE : STATE_FRAME_DATA ;
STATE_FRAME_DATA : lut_state_nxt = ~refresh_active_i ? STATE_IDLE :
~frame_data_ready_i ? STATE_FRAME_DATA :
`ifdef WITH_PROGRAMMABLE_LUT
lut_sw_enabled ? STATE_LUT_DATA :
`endif
STATE_HOLD ;
`ifdef WITH_PROGRAMMABLE_LUT
STATE_LUT_DATA : lut_state_nxt = ~refresh_active_i ? STATE_IDLE :
lut_ram_dout_rdy_nxt_i ? STATE_HOLD : STATE_LUT_DATA ;
`endif
STATE_HOLD : lut_state_nxt = ~refresh_active_i ? STATE_IDLE :
(fifo_counter_nxt!=FIFO_FULL) ? STATE_FRAME_DATA : STATE_HOLD ;
// pragma coverage off
default : lut_state_nxt = STATE_IDLE;
// pragma coverage on
endcase
//--------------------------------
// State machine
//--------------------------------
always @(posedge mclk or posedge puc_rst)
if (puc_rst) lut_state <= STATE_IDLE;
else lut_state <= lut_state_nxt;
// Request for the next frame data
assign frame_data_request_o = (lut_state == STATE_FRAME_DATA);
//============================================================================
// 4) LUT MEMORY INTERFACE
//============================================================================
//--------------------------------
// Enable
//--------------------------------
`ifdef WITH_PROGRAMMABLE_LUT
assign lut_ram_cen_o = ~(lut_state == STATE_LUT_DATA);
`endif
//--------------------------------
// Address
//--------------------------------
// Mask with chip enable to save power
`ifdef WITH_PROGRAMMABLE_LUT
`ifdef WITH_EXTRA_LUT_BANK
// Allow LUT bank switching only when the refresh is not on going
reg refresh_lut_bank_select_sync;
always @(posedge mclk or posedge puc_rst)
if (puc_rst) refresh_lut_bank_select_sync <= 1'b0;
else if (~refresh_active_i) refresh_lut_bank_select_sync <= sw_lut_bank_select_i;
assign lut_ram_addr_o = {refresh_lut_bank_select_sync, frame_data_i[7:0]} & {9{~lut_ram_cen_o}};
`else
assign lut_ram_addr_o = frame_data_i[7:0] & {8{~lut_ram_cen_o}};
`endif
`endif
//--------------------------------
// Data Ready
//--------------------------------
// When filling the FIFO, the data is available on the bus
// one cycle after the rdy_nxt signal
reg lut_ram_dout_ready;
always @(posedge mclk or posedge puc_rst)
if (puc_rst) lut_ram_dout_ready <= 1'b0;
`ifdef WITH_PROGRAMMABLE_LUT
else lut_ram_dout_ready <= lut_sw_enabled ? lut_ram_dout_rdy_nxt_i :
(frame_data_ready_i & (lut_state == STATE_FRAME_DATA));
`else
else lut_ram_dout_ready <= (frame_data_ready_i & (lut_state == STATE_FRAME_DATA));
`endif
//============================================================================
// 5) FIFO COUNTER
//============================================================================
// Control signals
wire fifo_push = lut_ram_dout_ready & (fifo_counter != FIFO_FULL);
wire fifo_pop = refresh_data_request_i & (fifo_counter != FIFO_EMPTY);
// Fifo counter
assign fifo_counter_nxt = ~refresh_active_i ? FIFO_EMPTY : // Initialize
(fifo_push & fifo_pop) ? fifo_counter : // Keep value (pop & push at the same time)
fifo_push ? fifo_counter + 3'h1 : // Push
fifo_pop ? fifo_counter - 3'h1 : // Pop
fifo_counter; // Hold
always @(posedge mclk or posedge puc_rst)
if (puc_rst) fifo_counter <= FIFO_EMPTY;
else fifo_counter <= fifo_counter_nxt;
//============================================================================
// 6) FIFO MEMORY & RD/WR POINTERS
//============================================================================
// Write pointer
reg [2:0] wr_ptr;
always @(posedge mclk or posedge puc_rst)
if (puc_rst) wr_ptr <= 3'h0;
else if (~refresh_active_i) wr_ptr <= 3'h0;
else if (fifo_push)
begin
if (wr_ptr==(FIFO_FULL-1)) wr_ptr <= 3'h0;
else wr_ptr <= wr_ptr + 3'h1;
end
// Memory
reg [15:0] fifo_mem [0:4];
always @(posedge mclk or posedge puc_rst)
if (puc_rst)
begin
fifo_mem[0] <= 16'h0000;
fifo_mem[1] <= 16'h0000;
fifo_mem[2] <= 16'h0000;
fifo_mem[3] <= 16'h0000;
fifo_mem[4] <= 16'h0000;
end
else if (fifo_push)
begin
fifo_mem[wr_ptr] <= lut_hw_enabled ? lut_hw_data :
`ifdef WITH_PROGRAMMABLE_LUT
lut_sw_enabled ? lut_ram_dout_i :
`endif
frame_data_i;
end
// Read pointer
reg [2:0] rd_ptr;
always @(posedge mclk or posedge puc_rst)
if (puc_rst) rd_ptr <= 3'h0;
else if (~refresh_active_i) rd_ptr <= 3'h0;
else if (fifo_pop)
begin
if (rd_ptr==(FIFO_FULL-1)) rd_ptr <= 3'h0;
else rd_ptr <= rd_ptr + 3'h1;
end
//============================================================================
// 7) REFRESH_DATA
//============================================================================
// Refresh Data is ready
reg refresh_data_ready_o;
always @(posedge mclk or posedge puc_rst)
if (puc_rst) refresh_data_ready_o <= 1'h0;
else if (~refresh_active_i) refresh_data_ready_o <= 1'h0;
else refresh_data_ready_o <= fifo_pop;
// Refresh Data
reg [15:0] refresh_data_o;
always @(posedge mclk or posedge puc_rst)
if (puc_rst) refresh_data_o <= 16'h0000;
else if (fifo_pop) refresh_data_o <= fifo_mem[rd_ptr];
endmodule
|
module image_processing_2d_design_processing_system7_0_0 (
GPIO_I,
GPIO_O,
GPIO_T,
TTC0_WAVE0_OUT,
TTC0_WAVE1_OUT,
TTC0_WAVE2_OUT,
M_AXI_GP0_ARVALID,
M_AXI_GP0_AWVALID,
M_AXI_GP0_BREADY,
M_AXI_GP0_RREADY,
M_AXI_GP0_WLAST,
M_AXI_GP0_WVALID,
M_AXI_GP0_ARID,
M_AXI_GP0_AWID,
M_AXI_GP0_WID,
M_AXI_GP0_ARBURST,
M_AXI_GP0_ARLOCK,
M_AXI_GP0_ARSIZE,
M_AXI_GP0_AWBURST,
M_AXI_GP0_AWLOCK,
M_AXI_GP0_AWSIZE,
M_AXI_GP0_ARPROT,
M_AXI_GP0_AWPROT,
M_AXI_GP0_ARADDR,
M_AXI_GP0_AWADDR,
M_AXI_GP0_WDATA,
M_AXI_GP0_ARCACHE,
M_AXI_GP0_ARLEN,
M_AXI_GP0_ARQOS,
M_AXI_GP0_AWCACHE,
M_AXI_GP0_AWLEN,
M_AXI_GP0_AWQOS,
M_AXI_GP0_WSTRB,
M_AXI_GP0_ACLK,
M_AXI_GP0_ARREADY,
M_AXI_GP0_AWREADY,
M_AXI_GP0_BVALID,
M_AXI_GP0_RLAST,
M_AXI_GP0_RVALID,
M_AXI_GP0_WREADY,
M_AXI_GP0_BID,
M_AXI_GP0_RID,
M_AXI_GP0_BRESP,
M_AXI_GP0_RRESP,
M_AXI_GP0_RDATA,
S_AXI_HP0_ARREADY,
S_AXI_HP0_AWREADY,
S_AXI_HP0_BVALID,
S_AXI_HP0_RLAST,
S_AXI_HP0_RVALID,
S_AXI_HP0_WREADY,
S_AXI_HP0_BRESP,
S_AXI_HP0_RRESP,
S_AXI_HP0_BID,
S_AXI_HP0_RID,
S_AXI_HP0_RDATA,
S_AXI_HP0_RCOUNT,
S_AXI_HP0_WCOUNT,
S_AXI_HP0_RACOUNT,
S_AXI_HP0_WACOUNT,
S_AXI_HP0_ACLK,
S_AXI_HP0_ARVALID,
S_AXI_HP0_AWVALID,
S_AXI_HP0_BREADY,
S_AXI_HP0_RDISSUECAP1_EN,
S_AXI_HP0_RREADY,
S_AXI_HP0_WLAST,
S_AXI_HP0_WRISSUECAP1_EN,
S_AXI_HP0_WVALID,
S_AXI_HP0_ARBURST,
S_AXI_HP0_ARLOCK,
S_AXI_HP0_ARSIZE,
S_AXI_HP0_AWBURST,
S_AXI_HP0_AWLOCK,
S_AXI_HP0_AWSIZE,
S_AXI_HP0_ARPROT,
S_AXI_HP0_AWPROT,
S_AXI_HP0_ARADDR,
S_AXI_HP0_AWADDR,
S_AXI_HP0_ARCACHE,
S_AXI_HP0_ARLEN,
S_AXI_HP0_ARQOS,
S_AXI_HP0_AWCACHE,
S_AXI_HP0_AWLEN,
S_AXI_HP0_AWQOS,
S_AXI_HP0_ARID,
S_AXI_HP0_AWID,
S_AXI_HP0_WID,
S_AXI_HP0_WDATA,
S_AXI_HP0_WSTRB,
IRQ_F2P,
FCLK_CLK0,
FCLK_CLK1,
FCLK_CLK2,
FCLK_RESET0_N,
FCLK_RESET1_N,
MIO,
DDR_CAS_n,
DDR_CKE,
DDR_Clk_n,
DDR_Clk,
DDR_CS_n,
DDR_DRSTB,
DDR_ODT,
DDR_RAS_n,
DDR_WEB,
DDR_BankAddr,
DDR_Addr,
DDR_VRN,
DDR_VRP,
DDR_DM,
DDR_DQ,
DDR_DQS_n,
DDR_DQS,
PS_SRSTB,
PS_CLK,
PS_PORB
);
input [3 : 0] GPIO_I;
output [3 : 0] GPIO_O;
output [3 : 0] GPIO_T;
output TTC0_WAVE0_OUT;
output TTC0_WAVE1_OUT;
output TTC0_WAVE2_OUT;
output M_AXI_GP0_ARVALID;
output M_AXI_GP0_AWVALID;
output M_AXI_GP0_BREADY;
output M_AXI_GP0_RREADY;
output M_AXI_GP0_WLAST;
output M_AXI_GP0_WVALID;
output [11 : 0] M_AXI_GP0_ARID;
output [11 : 0] M_AXI_GP0_AWID;
output [11 : 0] M_AXI_GP0_WID;
output [1 : 0] M_AXI_GP0_ARBURST;
output [1 : 0] M_AXI_GP0_ARLOCK;
output [2 : 0] M_AXI_GP0_ARSIZE;
output [1 : 0] M_AXI_GP0_AWBURST;
output [1 : 0] M_AXI_GP0_AWLOCK;
output [2 : 0] M_AXI_GP0_AWSIZE;
output [2 : 0] M_AXI_GP0_ARPROT;
output [2 : 0] M_AXI_GP0_AWPROT;
output [31 : 0] M_AXI_GP0_ARADDR;
output [31 : 0] M_AXI_GP0_AWADDR;
output [31 : 0] M_AXI_GP0_WDATA;
output [3 : 0] M_AXI_GP0_ARCACHE;
output [3 : 0] M_AXI_GP0_ARLEN;
output [3 : 0] M_AXI_GP0_ARQOS;
output [3 : 0] M_AXI_GP0_AWCACHE;
output [3 : 0] M_AXI_GP0_AWLEN;
output [3 : 0] M_AXI_GP0_AWQOS;
output [3 : 0] M_AXI_GP0_WSTRB;
input M_AXI_GP0_ACLK;
input M_AXI_GP0_ARREADY;
input M_AXI_GP0_AWREADY;
input M_AXI_GP0_BVALID;
input M_AXI_GP0_RLAST;
input M_AXI_GP0_RVALID;
input M_AXI_GP0_WREADY;
input [11 : 0] M_AXI_GP0_BID;
input [11 : 0] M_AXI_GP0_RID;
input [1 : 0] M_AXI_GP0_BRESP;
input [1 : 0] M_AXI_GP0_RRESP;
input [31 : 0] M_AXI_GP0_RDATA;
output S_AXI_HP0_ARREADY;
output S_AXI_HP0_AWREADY;
output S_AXI_HP0_BVALID;
output S_AXI_HP0_RLAST;
output S_AXI_HP0_RVALID;
output S_AXI_HP0_WREADY;
output [1 : 0] S_AXI_HP0_BRESP;
output [1 : 0] S_AXI_HP0_RRESP;
output [5 : 0] S_AXI_HP0_BID;
output [5 : 0] S_AXI_HP0_RID;
output [31 : 0] S_AXI_HP0_RDATA;
output [7 : 0] S_AXI_HP0_RCOUNT;
output [7 : 0] S_AXI_HP0_WCOUNT;
output [2 : 0] S_AXI_HP0_RACOUNT;
output [5 : 0] S_AXI_HP0_WACOUNT;
input S_AXI_HP0_ACLK;
input S_AXI_HP0_ARVALID;
input S_AXI_HP0_AWVALID;
input S_AXI_HP0_BREADY;
input S_AXI_HP0_RDISSUECAP1_EN;
input S_AXI_HP0_RREADY;
input S_AXI_HP0_WLAST;
input S_AXI_HP0_WRISSUECAP1_EN;
input S_AXI_HP0_WVALID;
input [1 : 0] S_AXI_HP0_ARBURST;
input [1 : 0] S_AXI_HP0_ARLOCK;
input [2 : 0] S_AXI_HP0_ARSIZE;
input [1 : 0] S_AXI_HP0_AWBURST;
input [1 : 0] S_AXI_HP0_AWLOCK;
input [2 : 0] S_AXI_HP0_AWSIZE;
input [2 : 0] S_AXI_HP0_ARPROT;
input [2 : 0] S_AXI_HP0_AWPROT;
input [31 : 0] S_AXI_HP0_ARADDR;
input [31 : 0] S_AXI_HP0_AWADDR;
input [3 : 0] S_AXI_HP0_ARCACHE;
input [3 : 0] S_AXI_HP0_ARLEN;
input [3 : 0] S_AXI_HP0_ARQOS;
input [3 : 0] S_AXI_HP0_AWCACHE;
input [3 : 0] S_AXI_HP0_AWLEN;
input [3 : 0] S_AXI_HP0_AWQOS;
input [5 : 0] S_AXI_HP0_ARID;
input [5 : 0] S_AXI_HP0_AWID;
input [5 : 0] S_AXI_HP0_WID;
input [31 : 0] S_AXI_HP0_WDATA;
input [3 : 0] S_AXI_HP0_WSTRB;
input [1 : 0] IRQ_F2P;
output FCLK_CLK0;
output FCLK_CLK1;
output FCLK_CLK2;
output FCLK_RESET0_N;
output FCLK_RESET1_N;
input [53 : 0] MIO;
input DDR_CAS_n;
input DDR_CKE;
input DDR_Clk_n;
input DDR_Clk;
input DDR_CS_n;
input DDR_DRSTB;
input DDR_ODT;
input DDR_RAS_n;
input DDR_WEB;
input [2 : 0] DDR_BankAddr;
input [14 : 0] DDR_Addr;
input DDR_VRN;
input DDR_VRP;
input [3 : 0] DDR_DM;
input [31 : 0] DDR_DQ;
input [3 : 0] DDR_DQS_n;
input [3 : 0] DDR_DQS;
input PS_SRSTB;
input PS_CLK;
input PS_PORB;
processing_system7_bfm_v2_0_5_processing_system7_bfm #(
.C_USE_M_AXI_GP0(1),
.C_USE_M_AXI_GP1(0),
.C_USE_S_AXI_ACP(0),
.C_USE_S_AXI_GP0(0),
.C_USE_S_AXI_GP1(0),
.C_USE_S_AXI_HP0(1),
.C_USE_S_AXI_HP1(0),
.C_USE_S_AXI_HP2(0),
.C_USE_S_AXI_HP3(0),
.C_S_AXI_HP0_DATA_WIDTH(32),
.C_S_AXI_HP1_DATA_WIDTH(64),
.C_S_AXI_HP2_DATA_WIDTH(64),
.C_S_AXI_HP3_DATA_WIDTH(64),
.C_HIGH_OCM_EN(0),
.C_FCLK_CLK0_FREQ(100.0),
.C_FCLK_CLK1_FREQ(50.0),
.C_FCLK_CLK2_FREQ(20.0),
.C_FCLK_CLK3_FREQ(10.0),
.C_M_AXI_GP0_ENABLE_STATIC_REMAP(0),
.C_M_AXI_GP1_ENABLE_STATIC_REMAP(0),
.C_M_AXI_GP0_THREAD_ID_WIDTH (12),
.C_M_AXI_GP1_THREAD_ID_WIDTH (12)
) inst (
.M_AXI_GP0_ARVALID(M_AXI_GP0_ARVALID),
.M_AXI_GP0_AWVALID(M_AXI_GP0_AWVALID),
.M_AXI_GP0_BREADY(M_AXI_GP0_BREADY),
.M_AXI_GP0_RREADY(M_AXI_GP0_RREADY),
.M_AXI_GP0_WLAST(M_AXI_GP0_WLAST),
.M_AXI_GP0_WVALID(M_AXI_GP0_WVALID),
.M_AXI_GP0_ARID(M_AXI_GP0_ARID),
.M_AXI_GP0_AWID(M_AXI_GP0_AWID),
.M_AXI_GP0_WID(M_AXI_GP0_WID),
.M_AXI_GP0_ARBURST(M_AXI_GP0_ARBURST),
.M_AXI_GP0_ARLOCK(M_AXI_GP0_ARLOCK),
.M_AXI_GP0_ARSIZE(M_AXI_GP0_ARSIZE),
.M_AXI_GP0_AWBURST(M_AXI_GP0_AWBURST),
.M_AXI_GP0_AWLOCK(M_AXI_GP0_AWLOCK),
.M_AXI_GP0_AWSIZE(M_AXI_GP0_AWSIZE),
.M_AXI_GP0_ARPROT(M_AXI_GP0_ARPROT),
.M_AXI_GP0_AWPROT(M_AXI_GP0_AWPROT),
.M_AXI_GP0_ARADDR(M_AXI_GP0_ARADDR),
.M_AXI_GP0_AWADDR(M_AXI_GP0_AWADDR),
.M_AXI_GP0_WDATA(M_AXI_GP0_WDATA),
.M_AXI_GP0_ARCACHE(M_AXI_GP0_ARCACHE),
.M_AXI_GP0_ARLEN(M_AXI_GP0_ARLEN),
.M_AXI_GP0_ARQOS(M_AXI_GP0_ARQOS),
.M_AXI_GP0_AWCACHE(M_AXI_GP0_AWCACHE),
.M_AXI_GP0_AWLEN(M_AXI_GP0_AWLEN),
.M_AXI_GP0_AWQOS(M_AXI_GP0_AWQOS),
.M_AXI_GP0_WSTRB(M_AXI_GP0_WSTRB),
.M_AXI_GP0_ACLK(M_AXI_GP0_ACLK),
.M_AXI_GP0_ARREADY(M_AXI_GP0_ARREADY),
.M_AXI_GP0_AWREADY(M_AXI_GP0_AWREADY),
.M_AXI_GP0_BVALID(M_AXI_GP0_BVALID),
.M_AXI_GP0_RLAST(M_AXI_GP0_RLAST),
.M_AXI_GP0_RVALID(M_AXI_GP0_RVALID),
.M_AXI_GP0_WREADY(M_AXI_GP0_WREADY),
.M_AXI_GP0_BID(M_AXI_GP0_BID),
.M_AXI_GP0_RID(M_AXI_GP0_RID),
.M_AXI_GP0_BRESP(M_AXI_GP0_BRESP),
.M_AXI_GP0_RRESP(M_AXI_GP0_RRESP),
.M_AXI_GP0_RDATA(M_AXI_GP0_RDATA),
.M_AXI_GP1_ARVALID(),
.M_AXI_GP1_AWVALID(),
.M_AXI_GP1_BREADY(),
.M_AXI_GP1_RREADY(),
.M_AXI_GP1_WLAST(),
.M_AXI_GP1_WVALID(),
.M_AXI_GP1_ARID(),
.M_AXI_GP1_AWID(),
.M_AXI_GP1_WID(),
.M_AXI_GP1_ARBURST(),
.M_AXI_GP1_ARLOCK(),
.M_AXI_GP1_ARSIZE(),
.M_AXI_GP1_AWBURST(),
.M_AXI_GP1_AWLOCK(),
.M_AXI_GP1_AWSIZE(),
.M_AXI_GP1_ARPROT(),
.M_AXI_GP1_AWPROT(),
.M_AXI_GP1_ARADDR(),
.M_AXI_GP1_AWADDR(),
.M_AXI_GP1_WDATA(),
.M_AXI_GP1_ARCACHE(),
.M_AXI_GP1_ARLEN(),
.M_AXI_GP1_ARQOS(),
.M_AXI_GP1_AWCACHE(),
.M_AXI_GP1_AWLEN(),
.M_AXI_GP1_AWQOS(),
.M_AXI_GP1_WSTRB(),
.M_AXI_GP1_ACLK(1'B0),
.M_AXI_GP1_ARREADY(1'B0),
.M_AXI_GP1_AWREADY(1'B0),
.M_AXI_GP1_BVALID(1'B0),
.M_AXI_GP1_RLAST(1'B0),
.M_AXI_GP1_RVALID(1'B0),
.M_AXI_GP1_WREADY(1'B0),
.M_AXI_GP1_BID(12'B0),
.M_AXI_GP1_RID(12'B0),
.M_AXI_GP1_BRESP(2'B0),
.M_AXI_GP1_RRESP(2'B0),
.M_AXI_GP1_RDATA(32'B0),
.S_AXI_GP0_ARREADY(),
.S_AXI_GP0_AWREADY(),
.S_AXI_GP0_BVALID(),
.S_AXI_GP0_RLAST(),
.S_AXI_GP0_RVALID(),
.S_AXI_GP0_WREADY(),
.S_AXI_GP0_BRESP(),
.S_AXI_GP0_RRESP(),
.S_AXI_GP0_RDATA(),
.S_AXI_GP0_BID(),
.S_AXI_GP0_RID(),
.S_AXI_GP0_ACLK(1'B0),
.S_AXI_GP0_ARVALID(1'B0),
.S_AXI_GP0_AWVALID(1'B0),
.S_AXI_GP0_BREADY(1'B0),
.S_AXI_GP0_RREADY(1'B0),
.S_AXI_GP0_WLAST(1'B0),
.S_AXI_GP0_WVALID(1'B0),
.S_AXI_GP0_ARBURST(2'B0),
.S_AXI_GP0_ARLOCK(2'B0),
.S_AXI_GP0_ARSIZE(3'B0),
.S_AXI_GP0_AWBURST(2'B0),
.S_AXI_GP0_AWLOCK(2'B0),
.S_AXI_GP0_AWSIZE(3'B0),
.S_AXI_GP0_ARPROT(3'B0),
.S_AXI_GP0_AWPROT(3'B0),
.S_AXI_GP0_ARADDR(32'B0),
.S_AXI_GP0_AWADDR(32'B0),
.S_AXI_GP0_WDATA(32'B0),
.S_AXI_GP0_ARCACHE(4'B0),
.S_AXI_GP0_ARLEN(4'B0),
.S_AXI_GP0_ARQOS(4'B0),
.S_AXI_GP0_AWCACHE(4'B0),
.S_AXI_GP0_AWLEN(4'B0),
.S_AXI_GP0_AWQOS(4'B0),
.S_AXI_GP0_WSTRB(4'B0),
.S_AXI_GP0_ARID(6'B0),
.S_AXI_GP0_AWID(6'B0),
.S_AXI_GP0_WID(6'B0),
.S_AXI_GP1_ARREADY(),
.S_AXI_GP1_AWREADY(),
.S_AXI_GP1_BVALID(),
.S_AXI_GP1_RLAST(),
.S_AXI_GP1_RVALID(),
.S_AXI_GP1_WREADY(),
.S_AXI_GP1_BRESP(),
.S_AXI_GP1_RRESP(),
.S_AXI_GP1_RDATA(),
.S_AXI_GP1_BID(),
.S_AXI_GP1_RID(),
.S_AXI_GP1_ACLK(1'B0),
.S_AXI_GP1_ARVALID(1'B0),
.S_AXI_GP1_AWVALID(1'B0),
.S_AXI_GP1_BREADY(1'B0),
.S_AXI_GP1_RREADY(1'B0),
.S_AXI_GP1_WLAST(1'B0),
.S_AXI_GP1_WVALID(1'B0),
.S_AXI_GP1_ARBURST(2'B0),
.S_AXI_GP1_ARLOCK(2'B0),
.S_AXI_GP1_ARSIZE(3'B0),
.S_AXI_GP1_AWBURST(2'B0),
.S_AXI_GP1_AWLOCK(2'B0),
.S_AXI_GP1_AWSIZE(3'B0),
.S_AXI_GP1_ARPROT(3'B0),
.S_AXI_GP1_AWPROT(3'B0),
.S_AXI_GP1_ARADDR(32'B0),
.S_AXI_GP1_AWADDR(32'B0),
.S_AXI_GP1_WDATA(32'B0),
.S_AXI_GP1_ARCACHE(4'B0),
.S_AXI_GP1_ARLEN(4'B0),
.S_AXI_GP1_ARQOS(4'B0),
.S_AXI_GP1_AWCACHE(4'B0),
.S_AXI_GP1_AWLEN(4'B0),
.S_AXI_GP1_AWQOS(4'B0),
.S_AXI_GP1_WSTRB(4'B0),
.S_AXI_GP1_ARID(6'B0),
.S_AXI_GP1_AWID(6'B0),
.S_AXI_GP1_WID(6'B0),
.S_AXI_ACP_ARREADY(),
.S_AXI_ACP_AWREADY(),
.S_AXI_ACP_BVALID(),
.S_AXI_ACP_RLAST(),
.S_AXI_ACP_RVALID(),
.S_AXI_ACP_WREADY(),
.S_AXI_ACP_BRESP(),
.S_AXI_ACP_RRESP(),
.S_AXI_ACP_BID(),
.S_AXI_ACP_RID(),
.S_AXI_ACP_RDATA(),
.S_AXI_ACP_ACLK(1'B0),
.S_AXI_ACP_ARVALID(1'B0),
.S_AXI_ACP_AWVALID(1'B0),
.S_AXI_ACP_BREADY(1'B0),
.S_AXI_ACP_RREADY(1'B0),
.S_AXI_ACP_WLAST(1'B0),
.S_AXI_ACP_WVALID(1'B0),
.S_AXI_ACP_ARID(3'B0),
.S_AXI_ACP_ARPROT(3'B0),
.S_AXI_ACP_AWID(3'B0),
.S_AXI_ACP_AWPROT(3'B0),
.S_AXI_ACP_WID(3'B0),
.S_AXI_ACP_ARADDR(32'B0),
.S_AXI_ACP_AWADDR(32'B0),
.S_AXI_ACP_ARCACHE(4'B0),
.S_AXI_ACP_ARLEN(4'B0),
.S_AXI_ACP_ARQOS(4'B0),
.S_AXI_ACP_AWCACHE(4'B0),
.S_AXI_ACP_AWLEN(4'B0),
.S_AXI_ACP_AWQOS(4'B0),
.S_AXI_ACP_ARBURST(2'B0),
.S_AXI_ACP_ARLOCK(2'B0),
.S_AXI_ACP_ARSIZE(3'B0),
.S_AXI_ACP_AWBURST(2'B0),
.S_AXI_ACP_AWLOCK(2'B0),
.S_AXI_ACP_AWSIZE(3'B0),
.S_AXI_ACP_ARUSER(5'B0),
.S_AXI_ACP_AWUSER(5'B0),
.S_AXI_ACP_WDATA(64'B0),
.S_AXI_ACP_WSTRB(8'B0),
.S_AXI_HP0_ARREADY(S_AXI_HP0_ARREADY),
.S_AXI_HP0_AWREADY(S_AXI_HP0_AWREADY),
.S_AXI_HP0_BVALID(S_AXI_HP0_BVALID),
.S_AXI_HP0_RLAST(S_AXI_HP0_RLAST),
.S_AXI_HP0_RVALID(S_AXI_HP0_RVALID),
.S_AXI_HP0_WREADY(S_AXI_HP0_WREADY),
.S_AXI_HP0_BRESP(S_AXI_HP0_BRESP),
.S_AXI_HP0_RRESP(S_AXI_HP0_RRESP),
.S_AXI_HP0_BID(S_AXI_HP0_BID),
.S_AXI_HP0_RID(S_AXI_HP0_RID),
.S_AXI_HP0_RDATA(S_AXI_HP0_RDATA),
.S_AXI_HP0_ACLK(S_AXI_HP0_ACLK),
.S_AXI_HP0_ARVALID(S_AXI_HP0_ARVALID),
.S_AXI_HP0_AWVALID(S_AXI_HP0_AWVALID),
.S_AXI_HP0_BREADY(S_AXI_HP0_BREADY),
.S_AXI_HP0_RREADY(S_AXI_HP0_RREADY),
.S_AXI_HP0_WLAST(S_AXI_HP0_WLAST),
.S_AXI_HP0_WVALID(S_AXI_HP0_WVALID),
.S_AXI_HP0_ARBURST(S_AXI_HP0_ARBURST),
.S_AXI_HP0_ARLOCK(S_AXI_HP0_ARLOCK),
.S_AXI_HP0_ARSIZE(S_AXI_HP0_ARSIZE),
.S_AXI_HP0_AWBURST(S_AXI_HP0_AWBURST),
.S_AXI_HP0_AWLOCK(S_AXI_HP0_AWLOCK),
.S_AXI_HP0_AWSIZE(S_AXI_HP0_AWSIZE),
.S_AXI_HP0_ARPROT(S_AXI_HP0_ARPROT),
.S_AXI_HP0_AWPROT(S_AXI_HP0_AWPROT),
.S_AXI_HP0_ARADDR(S_AXI_HP0_ARADDR),
.S_AXI_HP0_AWADDR(S_AXI_HP0_AWADDR),
.S_AXI_HP0_ARCACHE(S_AXI_HP0_ARCACHE),
.S_AXI_HP0_ARLEN(S_AXI_HP0_ARLEN),
.S_AXI_HP0_ARQOS(S_AXI_HP0_ARQOS),
.S_AXI_HP0_AWCACHE(S_AXI_HP0_AWCACHE),
.S_AXI_HP0_AWLEN(S_AXI_HP0_AWLEN),
.S_AXI_HP0_AWQOS(S_AXI_HP0_AWQOS),
.S_AXI_HP0_ARID(S_AXI_HP0_ARID),
.S_AXI_HP0_AWID(S_AXI_HP0_AWID),
.S_AXI_HP0_WID(S_AXI_HP0_WID),
.S_AXI_HP0_WDATA(S_AXI_HP0_WDATA),
.S_AXI_HP0_WSTRB(S_AXI_HP0_WSTRB),
.S_AXI_HP1_ARREADY(),
.S_AXI_HP1_AWREADY(),
.S_AXI_HP1_BVALID(),
.S_AXI_HP1_RLAST(),
.S_AXI_HP1_RVALID(),
.S_AXI_HP1_WREADY(),
.S_AXI_HP1_BRESP(),
.S_AXI_HP1_RRESP(),
.S_AXI_HP1_BID(),
.S_AXI_HP1_RID(),
.S_AXI_HP1_RDATA(),
.S_AXI_HP1_ACLK(1'B0),
.S_AXI_HP1_ARVALID(1'B0),
.S_AXI_HP1_AWVALID(1'B0),
.S_AXI_HP1_BREADY(1'B0),
.S_AXI_HP1_RREADY(1'B0),
.S_AXI_HP1_WLAST(1'B0),
.S_AXI_HP1_WVALID(1'B0),
.S_AXI_HP1_ARBURST(2'B0),
.S_AXI_HP1_ARLOCK(2'B0),
.S_AXI_HP1_ARSIZE(3'B0),
.S_AXI_HP1_AWBURST(2'B0),
.S_AXI_HP1_AWLOCK(2'B0),
.S_AXI_HP1_AWSIZE(3'B0),
.S_AXI_HP1_ARPROT(3'B0),
.S_AXI_HP1_AWPROT(3'B0),
.S_AXI_HP1_ARADDR(32'B0),
.S_AXI_HP1_AWADDR(32'B0),
.S_AXI_HP1_ARCACHE(4'B0),
.S_AXI_HP1_ARLEN(4'B0),
.S_AXI_HP1_ARQOS(4'B0),
.S_AXI_HP1_AWCACHE(4'B0),
.S_AXI_HP1_AWLEN(4'B0),
.S_AXI_HP1_AWQOS(4'B0),
.S_AXI_HP1_ARID(6'B0),
.S_AXI_HP1_AWID(6'B0),
.S_AXI_HP1_WID(6'B0),
.S_AXI_HP1_WDATA(64'B0),
.S_AXI_HP1_WSTRB(8'B0),
.S_AXI_HP2_ARREADY(),
.S_AXI_HP2_AWREADY(),
.S_AXI_HP2_BVALID(),
.S_AXI_HP2_RLAST(),
.S_AXI_HP2_RVALID(),
.S_AXI_HP2_WREADY(),
.S_AXI_HP2_BRESP(),
.S_AXI_HP2_RRESP(),
.S_AXI_HP2_BID(),
.S_AXI_HP2_RID(),
.S_AXI_HP2_RDATA(),
.S_AXI_HP2_ACLK(1'B0),
.S_AXI_HP2_ARVALID(1'B0),
.S_AXI_HP2_AWVALID(1'B0),
.S_AXI_HP2_BREADY(1'B0),
.S_AXI_HP2_RREADY(1'B0),
.S_AXI_HP2_WLAST(1'B0),
.S_AXI_HP2_WVALID(1'B0),
.S_AXI_HP2_ARBURST(2'B0),
.S_AXI_HP2_ARLOCK(2'B0),
.S_AXI_HP2_ARSIZE(3'B0),
.S_AXI_HP2_AWBURST(2'B0),
.S_AXI_HP2_AWLOCK(2'B0),
.S_AXI_HP2_AWSIZE(3'B0),
.S_AXI_HP2_ARPROT(3'B0),
.S_AXI_HP2_AWPROT(3'B0),
.S_AXI_HP2_ARADDR(32'B0),
.S_AXI_HP2_AWADDR(32'B0),
.S_AXI_HP2_ARCACHE(4'B0),
.S_AXI_HP2_ARLEN(4'B0),
.S_AXI_HP2_ARQOS(4'B0),
.S_AXI_HP2_AWCACHE(4'B0),
.S_AXI_HP2_AWLEN(4'B0),
.S_AXI_HP2_AWQOS(4'B0),
.S_AXI_HP2_ARID(6'B0),
.S_AXI_HP2_AWID(6'B0),
.S_AXI_HP2_WID(6'B0),
.S_AXI_HP2_WDATA(64'B0),
.S_AXI_HP2_WSTRB(8'B0),
.S_AXI_HP3_ARREADY(),
.S_AXI_HP3_AWREADY(),
.S_AXI_HP3_BVALID(),
.S_AXI_HP3_RLAST(),
.S_AXI_HP3_RVALID(),
.S_AXI_HP3_WREADY(),
.S_AXI_HP3_BRESP(),
.S_AXI_HP3_RRESP(),
.S_AXI_HP3_BID(),
.S_AXI_HP3_RID(),
.S_AXI_HP3_RDATA(),
.S_AXI_HP3_ACLK(1'B0),
.S_AXI_HP3_ARVALID(1'B0),
.S_AXI_HP3_AWVALID(1'B0),
.S_AXI_HP3_BREADY(1'B0),
.S_AXI_HP3_RREADY(1'B0),
.S_AXI_HP3_WLAST(1'B0),
.S_AXI_HP3_WVALID(1'B0),
.S_AXI_HP3_ARBURST(2'B0),
.S_AXI_HP3_ARLOCK(2'B0),
.S_AXI_HP3_ARSIZE(3'B0),
.S_AXI_HP3_AWBURST(2'B0),
.S_AXI_HP3_AWLOCK(2'B0),
.S_AXI_HP3_AWSIZE(3'B0),
.S_AXI_HP3_ARPROT(3'B0),
.S_AXI_HP3_AWPROT(3'B0),
.S_AXI_HP3_ARADDR(32'B0),
.S_AXI_HP3_AWADDR(32'B0),
.S_AXI_HP3_ARCACHE(4'B0),
.S_AXI_HP3_ARLEN(4'B0),
.S_AXI_HP3_ARQOS(4'B0),
.S_AXI_HP3_AWCACHE(4'B0),
.S_AXI_HP3_AWLEN(4'B0),
.S_AXI_HP3_AWQOS(4'B0),
.S_AXI_HP3_ARID(6'B0),
.S_AXI_HP3_AWID(6'B0),
.S_AXI_HP3_WID(6'B0),
.S_AXI_HP3_WDATA(64'B0),
.S_AXI_HP3_WSTRB(8'B0),
.FCLK_CLK0(FCLK_CLK0),
.FCLK_CLK1(FCLK_CLK1),
.FCLK_CLK2(FCLK_CLK2),
.FCLK_CLK3(),
.FCLK_RESET0_N(FCLK_RESET0_N),
.FCLK_RESET1_N(FCLK_RESET1_N),
.FCLK_RESET2_N(),
.FCLK_RESET3_N(),
.IRQ_F2P(IRQ_F2P),
.PS_SRSTB(PS_SRSTB),
.PS_CLK(PS_CLK),
.PS_PORB(PS_PORB)
);
endmodule
|
module flow_led
#(parameter LEN = 5, NUM = 5)
(
input power,
input sig_ring,
input sig_step,
output reg [(NUM-1):0] alarm_light
);
reg [31:0] count;
// 1: representation for ring on
// 0: representaion for ring off
reg alarm;
initial begin
alarm <= 0;
count <= 0;
alarm_light <= 0;
end
always @(posedge sig_step) begin
if (power) begin
if (sig_ring) begin
count = 0;
alarm = 1;
alarm_light = 1;
end else begin
if (alarm == 1) begin
count = count + 1;
alarm_light = alarm_light * 2 ? alarm_light * 2 : 1;
end
if (count == LEN) begin
count = 0;
alarm = 0;
alarm_light = 0;
end
end
end else begin
count = 0;
alarm = 0;
alarm_light = 0;
end
end
endmodule
|
module gcd_block_design_gcd_0_1 (
s_axi_gcd_bus_AWADDR,
s_axi_gcd_bus_AWVALID,
s_axi_gcd_bus_AWREADY,
s_axi_gcd_bus_WDATA,
s_axi_gcd_bus_WSTRB,
s_axi_gcd_bus_WVALID,
s_axi_gcd_bus_WREADY,
s_axi_gcd_bus_BRESP,
s_axi_gcd_bus_BVALID,
s_axi_gcd_bus_BREADY,
s_axi_gcd_bus_ARADDR,
s_axi_gcd_bus_ARVALID,
s_axi_gcd_bus_ARREADY,
s_axi_gcd_bus_RDATA,
s_axi_gcd_bus_RRESP,
s_axi_gcd_bus_RVALID,
s_axi_gcd_bus_RREADY,
ap_clk,
ap_rst_n,
interrupt
);
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi_gcd_bus AWADDR" *)
input wire [5 : 0] s_axi_gcd_bus_AWADDR;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi_gcd_bus AWVALID" *)
input wire s_axi_gcd_bus_AWVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi_gcd_bus AWREADY" *)
output wire s_axi_gcd_bus_AWREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi_gcd_bus WDATA" *)
input wire [31 : 0] s_axi_gcd_bus_WDATA;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi_gcd_bus WSTRB" *)
input wire [3 : 0] s_axi_gcd_bus_WSTRB;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi_gcd_bus WVALID" *)
input wire s_axi_gcd_bus_WVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi_gcd_bus WREADY" *)
output wire s_axi_gcd_bus_WREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi_gcd_bus BRESP" *)
output wire [1 : 0] s_axi_gcd_bus_BRESP;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi_gcd_bus BVALID" *)
output wire s_axi_gcd_bus_BVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi_gcd_bus BREADY" *)
input wire s_axi_gcd_bus_BREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi_gcd_bus ARADDR" *)
input wire [5 : 0] s_axi_gcd_bus_ARADDR;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi_gcd_bus ARVALID" *)
input wire s_axi_gcd_bus_ARVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi_gcd_bus ARREADY" *)
output wire s_axi_gcd_bus_ARREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi_gcd_bus RDATA" *)
output wire [31 : 0] s_axi_gcd_bus_RDATA;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi_gcd_bus RRESP" *)
output wire [1 : 0] s_axi_gcd_bus_RRESP;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi_gcd_bus RVALID" *)
output wire s_axi_gcd_bus_RVALID;
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME s_axi_gcd_bus, ADDR_WIDTH 6, DATA_WIDTH 32, PROTOCOL AXI4LITE, READ_WRITE_MODE READ_WRITE, LAYERED_METADATA xilinx.com:interface:datatypes:1.0 {CLK {datatype {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value {}} bitwidth {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 1} bitoffset {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 0}}}}, FREQ_HZ 100000000, \
ID_WIDTH 0, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 0, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 1, NUM_WRITE_OUTSTANDING 1, MAX_BURST_LENGTH 1, PHASE 0.000, CLK_DOMAIN gcd_block_design_processing_system7_0_2_FCLK_CLK0, NUM_READ_THREADS 4, NUM_WRITE_THREADS 4, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0" *)
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi_gcd_bus RREADY" *)
input wire s_axi_gcd_bus_RREADY;
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME ap_clk, ASSOCIATED_BUSIF s_axi_gcd_bus, ASSOCIATED_RESET ap_rst_n, LAYERED_METADATA xilinx.com:interface:datatypes:1.0 {CLK {datatype {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value {}} bitwidth {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 1} bitoffset {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 0}}}}, FREQ_HZ 100000000, PHASE 0.000, CLK_DOMAIN \
gcd_block_design_processing_system7_0_2_FCLK_CLK0" *)
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 ap_clk CLK" *)
input wire ap_clk;
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME ap_rst_n, POLARITY ACTIVE_LOW, LAYERED_METADATA xilinx.com:interface:datatypes:1.0 {RST {datatype {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value {}} bitwidth {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 1} bitoffset {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 0}}}}" *)
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 ap_rst_n RST" *)
input wire ap_rst_n;
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME interrupt, SENSITIVITY LEVEL_HIGH, LAYERED_METADATA xilinx.com:interface:datatypes:1.0 {INTERRUPT {datatype {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value {}} bitwidth {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 1} bitoffset {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 0}}}}, PortWidth 1" *)
(* X_INTERFACE_INFO = "xilinx.com:signal:interrupt:1.0 interrupt INTERRUPT" *)
output wire interrupt;
gcd #(
.C_S_AXI_GCD_BUS_ADDR_WIDTH(6),
.C_S_AXI_GCD_BUS_DATA_WIDTH(32)
) inst (
.s_axi_gcd_bus_AWADDR(s_axi_gcd_bus_AWADDR),
.s_axi_gcd_bus_AWVALID(s_axi_gcd_bus_AWVALID),
.s_axi_gcd_bus_AWREADY(s_axi_gcd_bus_AWREADY),
.s_axi_gcd_bus_WDATA(s_axi_gcd_bus_WDATA),
.s_axi_gcd_bus_WSTRB(s_axi_gcd_bus_WSTRB),
.s_axi_gcd_bus_WVALID(s_axi_gcd_bus_WVALID),
.s_axi_gcd_bus_WREADY(s_axi_gcd_bus_WREADY),
.s_axi_gcd_bus_BRESP(s_axi_gcd_bus_BRESP),
.s_axi_gcd_bus_BVALID(s_axi_gcd_bus_BVALID),
.s_axi_gcd_bus_BREADY(s_axi_gcd_bus_BREADY),
.s_axi_gcd_bus_ARADDR(s_axi_gcd_bus_ARADDR),
.s_axi_gcd_bus_ARVALID(s_axi_gcd_bus_ARVALID),
.s_axi_gcd_bus_ARREADY(s_axi_gcd_bus_ARREADY),
.s_axi_gcd_bus_RDATA(s_axi_gcd_bus_RDATA),
.s_axi_gcd_bus_RRESP(s_axi_gcd_bus_RRESP),
.s_axi_gcd_bus_RVALID(s_axi_gcd_bus_RVALID),
.s_axi_gcd_bus_RREADY(s_axi_gcd_bus_RREADY),
.ap_clk(ap_clk),
.ap_rst_n(ap_rst_n),
.interrupt(interrupt)
);
endmodule
|
module arbiter_dbus
(
// or1200 data master
// Wishbone Master interface
wbm0_adr_o,
wbm0_dat_o,
wbm0_sel_o,
wbm0_we_o,
wbm0_cyc_o,
wbm0_stb_o,
wbm0_cti_o,
wbm0_bte_o,
wbm0_dat_i,
wbm0_ack_i,
wbm0_err_i,
wbm0_rty_i,
// or1200 debug master
// Wishbone Master interface
wbm1_adr_o,
wbm1_dat_o,
wbm1_sel_o,
wbm1_we_o,
wbm1_cyc_o,
wbm1_stb_o,
wbm1_cti_o,
wbm1_bte_o,
wbm1_dat_i,
wbm1_ack_i,
wbm1_err_i,
wbm1_rty_i,
// Slave one
// Wishbone Slave interface
wbs0_adr_i,
wbs0_dat_i,
wbs0_sel_i,
wbs0_we_i,
wbs0_cyc_i,
wbs0_stb_i,
wbs0_cti_i,
wbs0_bte_i,
wbs0_dat_o,
wbs0_ack_o,
wbs0_err_o,
wbs0_rty_o,
// Slave two
// Wishbone Slave interface
wbs1_adr_i,
wbs1_dat_i,
wbs1_sel_i,
wbs1_we_i,
wbs1_cyc_i,
wbs1_stb_i,
wbs1_cti_i,
wbs1_bte_i,
wbs1_dat_o,
wbs1_ack_o,
wbs1_err_o,
wbs1_rty_o,
// Slave three
// Wishbone Slave interface
wbs2_adr_i,
wbs2_dat_i,
wbs2_sel_i,
wbs2_we_i,
wbs2_cyc_i,
wbs2_stb_i,
wbs2_cti_i,
wbs2_bte_i,
wbs2_dat_o,
wbs2_ack_o,
wbs2_err_o,
wbs2_rty_o,
/*
// Slave four
// Wishbone Slave interface
wbs3_adr_i,
wbs3_dat_i,
wbs3_sel_i,
wbs3_we_i,
wbs3_cyc_i,
wbs3_stb_i,
wbs3_cti_i,
wbs3_bte_i,
wbs3_dat_o,
wbs3_ack_o,
wbs3_err_o,
wbs3_rty_o,
// Slave five
// Wishbone Slave interface
wbs4_adr_i,
wbs4_dat_i,
wbs4_sel_i,
wbs4_we_i,
wbs4_cyc_i,
wbs4_stb_i,
wbs4_cti_i,
wbs4_bte_i,
wbs4_dat_o,
wbs4_ack_o,
wbs4_err_o,
wbs4_rty_o,
// Slave six
// Wishbone Slave interface
wbs5_adr_i,
wbs5_dat_i,
wbs5_sel_i,
wbs5_we_i,
wbs5_cyc_i,
wbs5_stb_i,
wbs5_cti_i,
wbs5_bte_i,
wbs5_dat_o,
wbs5_ack_o,
wbs5_err_o,
wbs5_rty_o,
// Slave seven
// Wishbone Slave interface
wbs6_adr_i,
wbs6_dat_i,
wbs6_sel_i,
wbs6_we_i,
wbs6_cyc_i,
wbs6_stb_i,
wbs6_cti_i,
wbs6_bte_i,
wbs6_dat_o,
wbs6_ack_o,
wbs6_err_o,
wbs6_rty_o,
// Slave eight
// Wishbone Slave interface
wbs7_adr_i,
wbs7_dat_i,
wbs7_sel_i,
wbs7_we_i,
wbs7_cyc_i,
wbs7_stb_i,
wbs7_cti_i,
wbs7_bte_i,
wbs7_dat_o,
wbs7_ack_o,
wbs7_err_o,
wbs7_rty_o,
// Slave nine
// Wishbone Slave interface
wbs8_adr_i,
wbs8_dat_i,
wbs8_sel_i,
wbs8_we_i,
wbs8_cyc_i,
wbs8_stb_i,
wbs8_cti_i,
wbs8_bte_i,
wbs8_dat_o,
wbs8_ack_o,
wbs8_err_o,
wbs8_rty_o,
// Slave ten
// Wishbone Slave interface
wbs9_adr_i,
wbs9_dat_i,
wbs9_sel_i,
wbs9_we_i,
wbs9_cyc_i,
wbs9_stb_i,
wbs9_cti_i,
wbs9_bte_i,
wbs9_dat_o,
wbs9_ack_o,
wbs9_err_o,
wbs9_rty_o,
// Slave eleven
// Wishbone Slave interface
wbs10_adr_i,
wbs10_dat_i,
wbs10_sel_i,
wbs10_we_i,
wbs10_cyc_i,
wbs10_stb_i,
wbs10_cti_i,
wbs10_bte_i,
wbs10_dat_o,
wbs10_ack_o,
wbs10_err_o,
wbs10_rty_o,
// Slave twelve
// Wishbone Slave interface
wbs11_adr_i,
wbs11_dat_i,
wbs11_sel_i,
wbs11_we_i,
wbs11_cyc_i,
wbs11_stb_i,
wbs11_cti_i,
wbs11_bte_i,
wbs11_dat_o,
wbs11_ack_o,
wbs11_err_o,
wbs11_rty_o,
// Slave thirteen
// Wishbone Slave interface
wbs12_adr_i,
wbs12_dat_i,
wbs12_sel_i,
wbs12_we_i,
wbs12_cyc_i,
wbs12_stb_i,
wbs12_cti_i,
wbs12_bte_i,
wbs12_dat_o,
wbs12_ack_o,
wbs12_err_o,
wbs12_rty_o,
// Slave fourteen
// Wishbone Slave interface
wbs13_adr_i,
wbs13_dat_i,
wbs13_sel_i,
wbs13_we_i,
wbs13_cyc_i,
wbs13_stb_i,
wbs13_cti_i,
wbs13_bte_i,
wbs13_dat_o,
wbs13_ack_o,
wbs13_err_o,
wbs13_rty_o,
// Slave fifteen
// Wishbone Slave interface
wbs14_adr_i,
wbs14_dat_i,
wbs14_sel_i,
wbs14_we_i,
wbs14_cyc_i,
wbs14_stb_i,
wbs14_cti_i,
wbs14_bte_i,
wbs14_dat_o,
wbs14_ack_o,
wbs14_err_o,
wbs14_rty_o,
// Slave sixteen
// Wishbone Slave interface
wbs15_adr_i,
wbs15_dat_i,
wbs15_sel_i,
wbs15_we_i,
wbs15_cyc_i,
wbs15_stb_i,
wbs15_cti_i,
wbs15_bte_i,
wbs15_dat_o,
wbs15_ack_o,
wbs15_err_o,
wbs15_rty_o,
// Slave seventeen
// Wishbone Slave interface
wbs16_adr_i,
wbs16_dat_i,
wbs16_sel_i,
wbs16_we_i,
wbs16_cyc_i,
wbs16_stb_i,
wbs16_cti_i,
wbs16_bte_i,
wbs16_dat_o,
wbs16_ack_o,
wbs16_err_o,
wbs16_rty_o,
*/
wb_clk,
wb_rst
);
parameter wb_dat_width = 32;
parameter wb_adr_width = 32;
parameter wb_addr_match_width = 8;
parameter wb_num_slaves = 2; // must also (un)comment things if changing
// Slave addresses - these should be defparam'd from top level
// Declare them as you need them
parameter slave0_adr = 0;
parameter slave1_adr = 0;
parameter slave2_adr = 0;
parameter slave3_adr = 0;
parameter slave4_adr = 0;
parameter slave5_adr = 0;
parameter slave6_adr = 0;
parameter slave7_adr = 0;
parameter slave8_adr = 0;
parameter slave9_adr = 0;
parameter slave10_adr = 0;
parameter slave11_adr = 0;
parameter slave12_adr = 0;
// Select for slave 0
`define WB_ARB_ADDR_MATCH_SEL_SLAVE0 wb_adr_width-1:wb_adr_width-4
`define WB_ARB_ADDR_MATCH_SEL wb_adr_width-1:wb_adr_width-wb_addr_match_width
input wb_clk;
input wb_rst;
// WB Master one
input [wb_adr_width-1:0] wbm0_adr_o;
input [wb_dat_width-1:0] wbm0_dat_o;
input [3:0] wbm0_sel_o;
input wbm0_we_o;
input wbm0_cyc_o;
input wbm0_stb_o;
input [2:0] wbm0_cti_o;
input [1:0] wbm0_bte_o;
output [wb_dat_width-1:0] wbm0_dat_i;
output wbm0_ack_i;
output wbm0_err_i;
output wbm0_rty_i;
input [wb_adr_width-1:0] wbm1_adr_o;
input [wb_dat_width-1:0] wbm1_dat_o;
input [3:0] wbm1_sel_o;
input wbm1_we_o;
input wbm1_cyc_o;
input wbm1_stb_o;
input [2:0] wbm1_cti_o;
input [1:0] wbm1_bte_o;
output [wb_dat_width-1:0] wbm1_dat_i;
output wbm1_ack_i;
output wbm1_err_i;
output wbm1_rty_i;
// Slave one
// Wishbone Slave interface
output [wb_adr_width-1:0] wbs0_adr_i;
output [wb_dat_width-1:0] wbs0_dat_i;
output [3:0] wbs0_sel_i;
output wbs0_we_i;
output wbs0_cyc_i;
output wbs0_stb_i;
output [2:0] wbs0_cti_i;
output [1:0] wbs0_bte_i;
input [wb_dat_width-1:0] wbs0_dat_o;
input wbs0_ack_o;
input wbs0_err_o;
input wbs0_rty_o;
// Wishbone Slave interface
output [wb_adr_width-1:0] wbs1_adr_i;
output [wb_dat_width-1:0] wbs1_dat_i;
output [3:0] wbs1_sel_i;
output wbs1_we_i;
output wbs1_cyc_i;
output wbs1_stb_i;
output [2:0] wbs1_cti_i;
output [1:0] wbs1_bte_i;
input [wb_dat_width-1:0] wbs1_dat_o;
input wbs1_ack_o;
input wbs1_err_o;
input wbs1_rty_o;
// Wishbone Slave interface
output [wb_adr_width-1:0] wbs2_adr_i;
output [wb_dat_width-1:0] wbs2_dat_i;
output [3:0] wbs2_sel_i;
output wbs2_we_i;
output wbs2_cyc_i;
output wbs2_stb_i;
output [2:0] wbs2_cti_i;
output [1:0] wbs2_bte_i;
input [wb_dat_width-1:0] wbs2_dat_o;
input wbs2_ack_o;
input wbs2_err_o;
input wbs2_rty_o;
/*
// Wishbone Slave interface
output [wb_adr_width-1:0] wbs3_adr_i;
output [wb_dat_width-1:0] wbs3_dat_i;
output [3:0] wbs3_sel_i;
output wbs3_we_i;
output wbs3_cyc_i;
output wbs3_stb_i;
output [2:0] wbs3_cti_i;
output [1:0] wbs3_bte_i;
input [wb_dat_width-1:0] wbs3_dat_o;
input wbs3_ack_o;
input wbs3_err_o;
input wbs3_rty_o;
// Wishbone Slave interface
output [wb_adr_width-1:0] wbs4_adr_i;
output [wb_dat_width-1:0] wbs4_dat_i;
output [3:0] wbs4_sel_i;
output wbs4_we_i;
output wbs4_cyc_i;
output wbs4_stb_i;
output [2:0] wbs4_cti_i;
output [1:0] wbs4_bte_i;
input [wb_dat_width-1:0] wbs4_dat_o;
input wbs4_ack_o;
input wbs4_err_o;
input wbs4_rty_o;
// Wishbone Slave interface
output [wb_adr_width-1:0] wbs5_adr_i;
output [wb_dat_width-1:0] wbs5_dat_i;
output [3:0] wbs5_sel_i;
output wbs5_we_i;
output wbs5_cyc_i;
output wbs5_stb_i;
output [2:0] wbs5_cti_i;
output [1:0] wbs5_bte_i;
input [wb_dat_width-1:0] wbs5_dat_o;
input wbs5_ack_o;
input wbs5_err_o;
input wbs5_rty_o;
// Wishbone Slave interface
output [wb_adr_width-1:0] wbs6_adr_i;
output [wb_dat_width-1:0] wbs6_dat_i;
output [3:0] wbs6_sel_i;
output wbs6_we_i;
output wbs6_cyc_i;
output wbs6_stb_i;
output [2:0] wbs6_cti_i;
output [1:0] wbs6_bte_i;
input [wb_dat_width-1:0] wbs6_dat_o;
input wbs6_ack_o;
input wbs6_err_o;
input wbs6_rty_o;
// Wishbone Slave interface
output [wb_adr_width-1:0] wbs7_adr_i;
output [wb_dat_width-1:0] wbs7_dat_i;
output [3:0] wbs7_sel_i;
output wbs7_we_i;
output wbs7_cyc_i;
output wbs7_stb_i;
output [2:0] wbs7_cti_i;
output [1:0] wbs7_bte_i;
input [wb_dat_width-1:0] wbs7_dat_o;
input wbs7_ack_o;
input wbs7_err_o;
input wbs7_rty_o;
// Wishbone Slave interface
output [wb_adr_width-1:0] wbs8_adr_i;
output [wb_dat_width-1:0] wbs8_dat_i;
output [3:0] wbs8_sel_i;
output wbs8_we_i;
output wbs8_cyc_i;
output wbs8_stb_i;
output [2:0] wbs8_cti_i;
output [1:0] wbs8_bte_i;
input [wb_dat_width-1:0] wbs8_dat_o;
input wbs8_ack_o;
input wbs8_err_o;
input wbs8_rty_o;
// Wishbone Slave interface
output [wb_adr_width-1:0] wbs9_adr_i;
output [wb_dat_width-1:0] wbs9_dat_i;
output [3:0] wbs9_sel_i;
output wbs9_we_i;
output wbs9_cyc_i;
output wbs9_stb_i;
output [2:0] wbs9_cti_i;
output [1:0] wbs9_bte_i;
input [wb_dat_width-1:0] wbs9_dat_o;
input wbs9_ack_o;
input wbs9_err_o;
input wbs9_rty_o;
// Wishbone Slave interface
output [wb_adr_width-1:0] wbs10_adr_i;
output [wb_dat_width-1:0] wbs10_dat_i;
output [3:0] wbs10_sel_i;
output wbs10_we_i;
output wbs10_cyc_i;
output wbs10_stb_i;
output [2:0] wbs10_cti_i;
output [1:0] wbs10_bte_i;
input [wb_dat_width-1:0] wbs10_dat_o;
input wbs10_ack_o;
input wbs10_err_o;
input wbs10_rty_o;
// Wishbone Slave interface
output [wb_adr_width-1:0] wbs11_adr_i;
output [wb_dat_width-1:0] wbs11_dat_i;
output [3:0] wbs11_sel_i;
output wbs11_we_i;
output wbs11_cyc_i;
output wbs11_stb_i;
output [2:0] wbs11_cti_i;
output [1:0] wbs11_bte_i;
input [wb_dat_width-1:0] wbs11_dat_o;
input wbs11_ack_o;
input wbs11_err_o;
input wbs11_rty_o;
// Wishbone Slave interface
output [wb_adr_width-1:0] wbs12_adr_i;
output [wb_dat_width-1:0] wbs12_dat_i;
output [3:0] wbs12_sel_i;
output wbs12_we_i;
output wbs12_cyc_i;
output wbs12_stb_i;
output [2:0] wbs12_cti_i;
output [1:0] wbs12_bte_i;
input [wb_dat_width-1:0] wbs12_dat_o;
input wbs12_ack_o;
input wbs12_err_o;
input wbs12_rty_o;
// Wishbone Slave interface
output [wb_adr_width-1:0] wbs13_adr_i;
output [wb_dat_width-1:0] wbs13_dat_i;
output [3:0] wbs13_sel_i;
output wbs13_we_i;
output wbs13_cyc_i;
output wbs13_stb_i;
output [2:0] wbs13_cti_i;
output [1:0] wbs13_bte_i;
input [wb_dat_width-1:0] wbs13_dat_o;
input wbs13_ack_o;
input wbs13_err_o;
input wbs13_rty_o;
// Wishbone Slave interface
output [wb_adr_width-1:0] wbs14_adr_i;
output [wb_dat_width-1:0] wbs14_dat_i;
output [3:0] wbs14_sel_i;
output wbs14_we_i;
output wbs14_cyc_i;
output wbs14_stb_i;
output [2:0] wbs14_cti_i;
output [1:0] wbs14_bte_i;
input [wb_dat_width-1:0] wbs14_dat_o;
input wbs14_ack_o;
input wbs14_err_o;
input wbs14_rty_o;
// Wishbone Slave interface
output [wb_adr_width-1:0] wbs15_adr_i;
output [wb_dat_width-1:0] wbs15_dat_i;
output [3:0] wbs15_sel_i;
output wbs15_we_i;
output wbs15_cyc_i;
output wbs15_stb_i;
output [2:0] wbs15_cti_i;
output [1:0] wbs15_bte_i;
input [wb_dat_width-1:0] wbs15_dat_o;
input wbs15_ack_o;
input wbs15_err_o;
input wbs15_rty_o;
// Wishbone Slave interface
output [wb_adr_width-1:0] wbs16_adr_i;
output [wb_dat_width-1:0] wbs16_dat_i;
output [3:0] wbs16_sel_i;
output wbs16_we_i;
output wbs16_cyc_i;
output wbs16_stb_i;
output [2:0] wbs16_cti_i;
output [1:0] wbs16_bte_i;
input [wb_dat_width-1:0] wbs16_dat_o;
input wbs16_ack_o;
input wbs16_err_o;
input wbs16_rty_o;
*/
reg watchdog_err;
`ifdef ARBITER_DBUS_REGISTERING
// Registering setup:
// Masters typically register their outputs, so do the master selection and
// muxing before registering in the arbiter. Keep the common parts outside
// for code brevity.
// Master ins -> |MUX> -> these wires
wire [wb_adr_width-1:0] wbm_adr_o_w;
wire [wb_dat_width-1:0] wbm_dat_o_w;
wire [3:0] wbm_sel_o_w;
wire wbm_we_o_w;
wire wbm_cyc_o_w;
wire wbm_stb_o_w;
wire [2:0] wbm_cti_o_w;
wire [1:0] wbm_bte_o_w;
// Slave ins -> |MUX> -> these wires
wire [wb_dat_width-1:0] wbm_dat_i;
wire wbm_ack_i;
wire wbm_err_i;
wire wbm_rty_i;
// Registers after masters input mux
reg [wb_adr_width-1:0] wbm_adr_o_r;
reg [wb_dat_width-1:0] wbm_dat_o_r;
reg [3:0] wbm_sel_o_r;
reg wbm_we_o_r;
reg wbm_cyc_o_r;
reg wbm_stb_o_r;
reg [2:0] wbm_cti_o_r;
reg [1:0] wbm_bte_o_r;
// Master input mux register wires
wire [wb_adr_width-1:0] wbm_adr_o;
wire [wb_dat_width-1:0] wbm_dat_o;
wire [3:0] wbm_sel_o;
wire wbm_we_o;
wire wbm_cyc_o;
wire wbm_stb_o;
wire [2:0] wbm_cti_o;
wire [1:0] wbm_bte_o;
// Registers after slaves input mux
reg [wb_dat_width-1:0] wbm_dat_i_r;
reg wbm_ack_i_r;
reg wbm_err_i_r;
reg wbm_rty_i_r;
// Master select (MUX controls)
wire [1:0] master_sel;
// priority to wbm1, the debug master
assign master_sel[0] = wbm0_cyc_o & !wbm1_cyc_o;
assign master_sel[1] = wbm1_cyc_o;
// Master input mux, priority to debug master
assign wbm_adr_o_w = master_sel[1] ? wbm1_adr_o :
wbm0_adr_o;
assign wbm_dat_o_w = master_sel[1] ? wbm1_dat_o :
wbm0_dat_o;
assign wbm_sel_o_w = master_sel[1] ? wbm1_sel_o :
wbm0_sel_o;
assign wbm_we_o_w = master_sel[1] ? wbm1_we_o :
wbm0_we_o;
assign wbm_cyc_o_w = master_sel[1] ? wbm1_cyc_o :
wbm0_cyc_o;
assign wbm_stb_o_w = master_sel[1] ? wbm1_stb_o :
wbm0_stb_o;
assign wbm_cti_o_w = master_sel[1] ? wbm1_cti_o :
wbm0_cti_o;
assign wbm_bte_o_w = master_sel[1] ? wbm1_bte_o :
wbm0_bte_o;
// Register muxed master signals
always @(posedge wb_clk)
begin
wbm_adr_o_r <= wbm_adr_o_w;
wbm_dat_o_r <= wbm_dat_o_w;
wbm_sel_o_r <= wbm_sel_o_w;
wbm_we_o_r <= wbm_we_o_w;
wbm_cyc_o_r <= wbm_cyc_o_w;
wbm_stb_o_r <= wbm_stb_o_w & !wbm_ack_i & !wbm_ack_i_r;
wbm_cti_o_r <= wbm_cti_o_w;
wbm_bte_o_r <= wbm_bte_o_w;
wbm_dat_i_r <= wbm_dat_i;
wbm_ack_i_r <= wbm_ack_i;
wbm_err_i_r <= wbm_err_i;
wbm_rty_i_r <= wbm_rty_i;
end // always @ (posedge wb_clk)
assign wbm_adr_o = wbm_adr_o_r;
assign wbm_dat_o = wbm_dat_o_r;
assign wbm_sel_o = wbm_sel_o_r;
assign wbm_we_o = wbm_we_o_r;
assign wbm_cyc_o = wbm_cyc_o_r;
assign wbm_stb_o = wbm_stb_o_r;
assign wbm_cti_o = wbm_cti_o_r;
assign wbm_bte_o = wbm_bte_o_r;
// Master input mux, priority to debug master
assign wbm0_dat_i = wbm_dat_i_r;
assign wbm0_ack_i = wbm_ack_i_r & master_sel[0];
assign wbm0_err_i = wbm_err_i_r & master_sel[0];
assign wbm0_rty_i = wbm_rty_i_r & master_sel[0];
assign wbm1_dat_i = wbm_dat_i_r;
assign wbm1_ack_i = wbm_ack_i_r & master_sel[1];
assign wbm1_err_i = wbm_err_i_r & master_sel[1];
assign wbm1_rty_i = wbm_rty_i_r & master_sel[1];
`else // !`ifdef ARBITER_DBUS_REGISTERING
// Master input mux output wires
wire [wb_adr_width-1:0] wbm_adr_o;
wire [wb_dat_width-1:0] wbm_dat_o;
wire [3:0] wbm_sel_o;
wire wbm_we_o;
wire wbm_cyc_o;
wire wbm_stb_o;
wire [2:0] wbm_cti_o;
wire [1:0] wbm_bte_o;
// Master select
wire [1:0] master_sel;
// priority to wbm1, the debug master
assign master_sel[0] = wbm0_cyc_o & !wbm1_cyc_o;
assign master_sel[1] = wbm1_cyc_o;
// Master input mux, priority to debug master
assign wbm_adr_o = master_sel[1] ? wbm1_adr_o :
wbm0_adr_o;
assign wbm_dat_o = master_sel[1] ? wbm1_dat_o :
wbm0_dat_o;
assign wbm_sel_o = master_sel[1] ? wbm1_sel_o :
wbm0_sel_o;
assign wbm_we_o = master_sel[1] ? wbm1_we_o :
wbm0_we_o;
assign wbm_cyc_o = master_sel[1] ? wbm1_cyc_o :
wbm0_cyc_o;
assign wbm_stb_o = master_sel[1] ? wbm1_stb_o :
wbm0_stb_o;
assign wbm_cti_o = master_sel[1] ? wbm1_cti_o :
wbm0_cti_o;
assign wbm_bte_o = master_sel[1] ? wbm1_bte_o :
wbm0_bte_o;
wire [wb_dat_width-1:0] wbm_dat_i;
wire wbm_ack_i;
wire wbm_err_i;
wire wbm_rty_i;
assign wbm0_dat_i = wbm_dat_i;
assign wbm0_ack_i = wbm_ack_i & master_sel[0];
assign wbm0_err_i = wbm_err_i & master_sel[0];
assign wbm0_rty_i = wbm_rty_i & master_sel[0];
assign wbm1_dat_i = wbm_dat_i;
assign wbm1_ack_i = wbm_ack_i & master_sel[1];
assign wbm1_err_i = wbm_err_i & master_sel[1];
assign wbm1_rty_i = wbm_rty_i & master_sel[1];
`endif // !`ifdef ARBITER_DBUS_REGISTERING
// Slave select wire
wire [wb_num_slaves-1:0] wb_slave_sel;
reg [wb_num_slaves-1:0] wb_slave_sel_r;
// Register wb_slave_sel_r to break combinatorial loop when selecting default
// slave
always @(posedge wb_clk)
wb_slave_sel_r <= wb_slave_sel;
// Slave out mux in wires
wire [wb_dat_width-1:0] wbs_dat_o_mux_i [0:wb_num_slaves-1];
wire wbs_ack_o_mux_i [0:wb_num_slaves-1];
wire wbs_err_o_mux_i [0:wb_num_slaves-1];
wire wbs_rty_o_mux_i [0:wb_num_slaves-1];
//
// Slave selects
//
assign wb_slave_sel[0] = wbm_adr_o[31:28] == slave0_adr | wbm_adr_o[31:28] == 4'hf; // Special case, point all reads to ROM address to here
assign wb_slave_sel[1] = wbm_adr_o[`WB_ARB_ADDR_MATCH_SEL] == slave1_adr;
// Auto select last slave when others are not selected
assign wb_slave_sel[2] = !(wb_slave_sel_r[0] | wb_slave_sel_r[1]);
/*
assign wb_slave_sel[2] = wbm_adr_o[`WB_ARB_ADDR_MATCH_SEL] == slave2_adr;
assign wb_slave_sel[3] = wbm_adr_o[`WB_ARB_ADDR_MATCH_SEL] == slave3_adr;
assign wb_slave_sel[4] = wbm_adr_o[`WB_ARB_ADDR_MATCH_SEL] == slave4_adr;
assign wb_slave_sel[5] = wbm_adr_o[`WB_ARB_ADDR_MATCH_SEL] == slave5_adr;
assign wb_slave_sel[6] = wbm_adr_o[`WB_ARB_ADDR_MATCH_SEL] == slave6_adr;
assign wb_slave_sel[7] = wbm_adr_o[`WB_ARB_ADDR_MATCH_SEL] == slave7_adr;
assign wb_slave_sel[8] = wbm_adr_o[`WB_ARB_ADDR_MATCH_SEL] == slave8_adr;
assign wb_slave_sel[9] = wbm_adr_o[`WB_ARB_ADDR_MATCH_SEL] == slave9_adr;
assign wb_slave_sel[10] = wbm_adr_o[`WB_ARB_ADDR_MATCH_SEL] == slave10_adr;
assign wb_slave_sel[11] = wbm_adr_o[`WB_ARB_ADDR_MATCH_SEL] == slave11_adr;
assign wb_slave_sel[12] = wbm_adr_o[`WB_ARB_ADDR_MATCH_SEL] == slave12_adr;
assign wb_slave_sel[13] = wbm_adr_o[`WB_ARB_ADDR_MATCH_SEL] == slave13_adr;
assign wb_slave_sel[14] = wbm_adr_o[`WB_ARB_ADDR_MATCH_SEL] == slave14_adr;
assign wb_slave_sel[15] = wbm_adr_o[`WB_ARB_ADDR_MATCH_SEL] == slave15_adr;
assign wb_slave_sel[16] = wbm_adr_o[`WB_ARB_ADDR_MATCH_SEL] == slave16_adr;
*/
`ifdef ARBITER_DBUS_WATCHDOG
reg [`ARBITER_DBUS_WATCHDOG_TIMER_WIDTH:0] watchdog_timer;
reg wbm_stb_r; // Register strobe
wire wbm_stb_edge; // Detect its edge
always @(posedge wb_clk)
wbm_stb_r <= wbm_stb_o;
assign wbm_stb_edge = (wbm_stb_o & !wbm_stb_r);
// Counter logic
always @(posedge wb_clk)
if (wb_rst) watchdog_timer <= 0;
else if (wbm_ack_i) // When we see an ack, turn off timer
watchdog_timer <= 0;
else if (wbm_stb_edge) // New access means start timer again
watchdog_timer <= 1;
else if (|watchdog_timer) // Continue counting if counter > 0
watchdog_timer <= watchdog_timer + 1;
always @(posedge wb_clk)
watchdog_err <= (&watchdog_timer);
`else // !`ifdef ARBITER_DBUS_WATCHDOG
always @(posedge wb_clk)
watchdog_err <= 0;
`endif // !`ifdef ARBITER_DBUS_WATCHDOG
// Slave 0 inputs
assign wbs0_adr_i = wbm_adr_o;
assign wbs0_dat_i = wbm_dat_o;
assign wbs0_sel_i = wbm_sel_o;
assign wbs0_cyc_i = wbm_cyc_o & wb_slave_sel_r[0];
assign wbs0_stb_i = wbm_stb_o & wb_slave_sel_r[0];
assign wbs0_we_i = wbm_we_o;
assign wbs0_cti_i = wbm_cti_o;
assign wbs0_bte_i = wbm_bte_o;
assign wbs_dat_o_mux_i[0] = wbs0_dat_o;
assign wbs_ack_o_mux_i[0] = wbs0_ack_o & wb_slave_sel_r[0];
assign wbs_err_o_mux_i[0] = wbs0_err_o & wb_slave_sel_r[0];
assign wbs_rty_o_mux_i[0] = wbs0_rty_o & wb_slave_sel_r[0];
// Slave 1 inputs
assign wbs1_adr_i = wbm_adr_o;
assign wbs1_dat_i = wbm_dat_o;
assign wbs1_sel_i = wbm_sel_o;
assign wbs1_cyc_i = wbm_cyc_o & wb_slave_sel_r[1];
assign wbs1_stb_i = wbm_stb_o & wb_slave_sel_r[1];
assign wbs1_we_i = wbm_we_o;
assign wbs1_cti_i = wbm_cti_o;
assign wbs1_bte_i = wbm_bte_o;
assign wbs_dat_o_mux_i[1] = wbs1_dat_o;
assign wbs_ack_o_mux_i[1] = wbs1_ack_o & wb_slave_sel_r[1];
assign wbs_err_o_mux_i[1] = wbs1_err_o & wb_slave_sel_r[1];
assign wbs_rty_o_mux_i[1] = wbs1_rty_o & wb_slave_sel_r[1];
// Slave 2 inputs
assign wbs2_adr_i = wbm_adr_o;
assign wbs2_dat_i = wbm_dat_o;
assign wbs2_sel_i = wbm_sel_o;
assign wbs2_cyc_i = wbm_cyc_o & wb_slave_sel_r[2];
assign wbs2_stb_i = wbm_stb_o & wb_slave_sel_r[2];
assign wbs2_we_i = wbm_we_o;
assign wbs2_cti_i = wbm_cti_o;
assign wbs2_bte_i = wbm_bte_o;
assign wbs_dat_o_mux_i[2] = wbs2_dat_o;
assign wbs_ack_o_mux_i[2] = wbs2_ack_o & wb_slave_sel_r[2];
assign wbs_err_o_mux_i[2] = wbs2_err_o & wb_slave_sel_r[2];
assign wbs_rty_o_mux_i[2] = wbs2_rty_o & wb_slave_sel_r[2];
/*
// Slave 3 inputs
assign wbs3_adr_i = wbm_adr_o;
assign wbs3_dat_i = wbm_dat_o;
assign wbs3_sel_i = wbm_sel_o;
assign wbs3_cyc_i = wbm_cyc_o & wb_slave_sel_r[3];
assign wbs3_stb_i = wbm_stb_o & wb_slave_sel_r[3];
assign wbs3_we_i = wbm_we_o;
assign wbs3_cti_i = wbm_cti_o;
assign wbs3_bte_i = wbm_bte_o;
assign wbs_dat_o_mux_i[3] = wbs3_dat_o;
assign wbs_ack_o_mux_i[3] = wbs3_ack_o & wb_slave_sel_r[3];
assign wbs_err_o_mux_i[3] = wbs3_err_o & wb_slave_sel_r[3];
assign wbs_rty_o_mux_i[3] = wbs3_rty_o & wb_slave_sel_r[3];
// Slave 4 inputs
assign wbs4_adr_i = wbm_adr_o;
assign wbs4_dat_i = wbm_dat_o;
assign wbs4_sel_i = wbm_sel_o;
assign wbs4_cyc_i = wbm_cyc_o & wb_slave_sel_r[4];
assign wbs4_stb_i = wbm_stb_o & wb_slave_sel_r[4];
assign wbs4_we_i = wbm_we_o;
assign wbs4_cti_i = wbm_cti_o;
assign wbs4_bte_i = wbm_bte_o;
assign wbs_dat_o_mux_i[4] = wbs4_dat_o;
assign wbs_ack_o_mux_i[4] = wbs4_ack_o & wb_slave_sel_r[4];
assign wbs_err_o_mux_i[4] = wbs4_err_o & wb_slave_sel_r[4];
assign wbs_rty_o_mux_i[4] = wbs4_rty_o & wb_slave_sel_r[4];
// Slave 5 inputs
assign wbs5_adr_i = wbm_adr_o;
assign wbs5_dat_i = wbm_dat_o;
assign wbs5_sel_i = wbm_sel_o;
assign wbs5_cyc_i = wbm_cyc_o & wb_slave_sel_r[5];
assign wbs5_stb_i = wbm_stb_o & wb_slave_sel_r[5];
assign wbs5_we_i = wbm_we_o;
assign wbs5_cti_i = wbm_cti_o;
assign wbs5_bte_i = wbm_bte_o;
assign wbs_dat_o_mux_i[5] = wbs5_dat_o;
assign wbs_ack_o_mux_i[5] = wbs5_ack_o & wb_slave_sel_r[5];
assign wbs_err_o_mux_i[5] = wbs5_err_o & wb_slave_sel_r[5];
assign wbs_rty_o_mux_i[5] = wbs5_rty_o & wb_slave_sel_r[5];
// Slave 6 inputs
assign wbs6_adr_i = wbm_adr_o;
assign wbs6_dat_i = wbm_dat_o;
assign wbs6_sel_i = wbm_sel_o;
assign wbs6_cyc_i = wbm_cyc_o & wb_slave_sel_r[6];
assign wbs6_stb_i = wbm_stb_o & wb_slave_sel_r[6];
assign wbs6_we_i = wbm_we_o;
assign wbs6_cti_i = wbm_cti_o;
assign wbs6_bte_i = wbm_bte_o;
assign wbs_dat_o_mux_i[6] = wbs6_dat_o;
assign wbs_ack_o_mux_i[6] = wbs6_ack_o & wb_slave_sel_r[6];
assign wbs_err_o_mux_i[6] = wbs6_err_o & wb_slave_sel_r[6];
assign wbs_rty_o_mux_i[6] = wbs6_rty_o & wb_slave_sel_r[6];
// Slave 7 inputs
assign wbs7_adr_i = wbm_adr_o;
assign wbs7_dat_i = wbm_dat_o;
assign wbs7_sel_i = wbm_sel_o;
assign wbs7_cyc_i = wbm_cyc_o & wb_slave_sel_r[7];
assign wbs7_stb_i = wbm_stb_o & wb_slave_sel_r[7];
assign wbs7_we_i = wbm_we_o;
assign wbs7_cti_i = wbm_cti_o;
assign wbs7_bte_i = wbm_bte_o;
assign wbs_dat_o_mux_i[7] = wbs7_dat_o;
assign wbs_ack_o_mux_i[7] = wbs7_ack_o & wb_slave_sel_r[7];
assign wbs_err_o_mux_i[7] = wbs7_err_o & wb_slave_sel_r[7];
assign wbs_rty_o_mux_i[7] = wbs7_rty_o & wb_slave_sel_r[7];
// Slave 8 inputs
assign wbs8_adr_i = wbm_adr_o;
assign wbs8_dat_i = wbm_dat_o;
assign wbs8_sel_i = wbm_sel_o;
assign wbs8_cyc_i = wbm_cyc_o & wb_slave_sel_r[8];
assign wbs8_stb_i = wbm_stb_o & wb_slave_sel_r[8];
assign wbs8_we_i = wbm_we_o;
assign wbs8_cti_i = wbm_cti_o;
assign wbs8_bte_i = wbm_bte_o;
assign wbs_dat_o_mux_i[8] = wbs8_dat_o;
assign wbs_ack_o_mux_i[8] = wbs8_ack_o & wb_slave_sel_r[8];
assign wbs_err_o_mux_i[8] = wbs8_err_o & wb_slave_sel_r[8];
assign wbs_rty_o_mux_i[8] = wbs8_rty_o & wb_slave_sel_r[8];
// Slave 9 inputs
assign wbs9_adr_i = wbm_adr_o;
assign wbs9_dat_i = wbm_dat_o;
assign wbs9_sel_i = wbm_sel_o;
assign wbs9_cyc_i = wbm_cyc_o & wb_slave_sel_r[9];
assign wbs9_stb_i = wbm_stb_o & wb_slave_sel_r[9];
assign wbs9_we_i = wbm_we_o;
assign wbs9_cti_i = wbm_cti_o;
assign wbs9_bte_i = wbm_bte_o;
assign wbs_dat_o_mux_i[9] = wbs9_dat_o;
assign wbs_ack_o_mux_i[9] = wbs9_ack_o & wb_slave_sel_r[9];
assign wbs_err_o_mux_i[9] = wbs9_err_o & wb_slave_sel_r[9];
assign wbs_rty_o_mux_i[9] = wbs9_rty_o & wb_slave_sel_r[9];
// Slave 10 inputs
assign wbs10_adr_i = wbm_adr_o;
assign wbs10_dat_i = wbm_dat_o;
assign wbs10_sel_i = wbm_sel_o;
assign wbs10_cyc_i = wbm_cyc_o & wb_slave_sel_r[10];
assign wbs10_stb_i = wbm_stb_o & wb_slave_sel_r[10];
assign wbs10_we_i = wbm_we_o;
assign wbs10_cti_i = wbm_cti_o;
assign wbs10_bte_i = wbm_bte_o;
assign wbs_dat_o_mux_i[10] = wbs10_dat_o;
assign wbs_ack_o_mux_i[10] = wbs10_ack_o & wb_slave_sel_r[10];
assign wbs_err_o_mux_i[10] = wbs10_err_o & wb_slave_sel_r[10];
assign wbs_rty_o_mux_i[10] = wbs10_rty_o & wb_slave_sel_r[10];
// Slave 11 inputs
assign wbs11_adr_i = wbm_adr_o;
assign wbs11_dat_i = wbm_dat_o;
assign wbs11_sel_i = wbm_sel_o;
assign wbs11_cyc_i = wbm_cyc_o & wb_slave_sel_r[11];
assign wbs11_stb_i = wbm_stb_o & wb_slave_sel_r[11];
assign wbs11_we_i = wbm_we_o;
assign wbs11_cti_i = wbm_cti_o;
assign wbs11_bte_i = wbm_bte_o;
assign wbs_dat_o_mux_i[11] = wbs11_dat_o;
assign wbs_ack_o_mux_i[11] = wbs11_ack_o & wb_slave_sel_r[11];
assign wbs_err_o_mux_i[11] = wbs11_err_o & wb_slave_sel_r[11];
assign wbs_rty_o_mux_i[11] = wbs11_rty_o & wb_slave_sel_r[11];
// Slave 12 inputs
assign wbs12_adr_i = wbm_adr_o;
assign wbs12_dat_i = wbm_dat_o;
assign wbs12_sel_i = wbm_sel_o;
assign wbs12_cyc_i = wbm_cyc_o & wb_slave_sel_r[12];
assign wbs12_stb_i = wbm_stb_o & wb_slave_sel_r[12];
assign wbs12_we_i = wbm_we_o;
assign wbs12_cti_i = wbm_cti_o;
assign wbs12_bte_i = wbm_bte_o;
assign wbs_dat_o_mux_i[12] = wbs12_dat_o;
assign wbs_ack_o_mux_i[12] = wbs12_ack_o & wb_slave_sel_r[12];
assign wbs_err_o_mux_i[12] = wbs12_err_o & wb_slave_sel_r[12];
assign wbs_rty_o_mux_i[12] = wbs12_rty_o & wb_slave_sel_r[12];
// Slave 13 inputs
assign wbs13_adr_i = wbm_adr_o;
assign wbs13_dat_i = wbm_dat_o;
assign wbs13_sel_i = wbm_sel_o;
assign wbs13_cyc_i = wbm_cyc_o & wb_slave_sel_r[13];
assign wbs13_stb_i = wbm_stb_o & wb_slave_sel_r[13];
assign wbs13_we_i = wbm_we_o;
assign wbs13_cti_i = wbm_cti_o;
assign wbs13_bte_i = wbm_bte_o;
assign wbs_dat_o_mux_i[13] = wbs13_dat_o;
assign wbs_ack_o_mux_i[13] = wbs13_ack_o & wb_slave_sel_r[13];
assign wbs_err_o_mux_i[13] = wbs13_err_o & wb_slave_sel_r[13];
assign wbs_rty_o_mux_i[13] = wbs13_rty_o & wb_slave_sel_r[13];
// Slave 14 inputs
assign wbs14_adr_i = wbm_adr_o;
assign wbs14_dat_i = wbm_dat_o;
assign wbs14_sel_i = wbm_sel_o;
assign wbs14_cyc_i = wbm_cyc_o & wb_slave_sel_r[14];
assign wbs14_stb_i = wbm_stb_o & wb_slave_sel_r[14];
assign wbs14_we_i = wbm_we_o;
assign wbs14_cti_i = wbm_cti_o;
assign wbs14_bte_i = wbm_bte_o;
assign wbs_dat_o_mux_i[14] = wbs14_dat_o;
assign wbs_ack_o_mux_i[14] = wbs14_ack_o & wb_slave_sel_r[14];
assign wbs_err_o_mux_i[14] = wbs14_err_o & wb_slave_sel_r[14];
assign wbs_rty_o_mux_i[14] = wbs14_rty_o & wb_slave_sel_r[14];
// Slave 15 inputs
assign wbs15_adr_i = wbm_adr_o;
assign wbs15_dat_i = wbm_dat_o;
assign wbs15_sel_i = wbm_sel_o;
assign wbs15_cyc_i = wbm_cyc_o & wb_slave_sel_r[15];
assign wbs15_stb_i = wbm_stb_o & wb_slave_sel_r[15];
assign wbs15_we_i = wbm_we_o;
assign wbs15_cti_i = wbm_cti_o;
assign wbs15_bte_i = wbm_bte_o;
assign wbs_dat_o_mux_i[15] = wbs15_dat_o;
assign wbs_ack_o_mux_i[15] = wbs15_ack_o & wb_slave_sel_r[15];
assign wbs_err_o_mux_i[15] = wbs15_err_o & wb_slave_sel_r[15];
assign wbs_rty_o_mux_i[15] = wbs15_rty_o & wb_slave_sel_r[15];
// Slave 16 inputs
assign wbs16_adr_i = wbm_adr_o;
assign wbs16_dat_i = wbm_dat_o;
assign wbs16_sel_i = wbm_sel_o;
assign wbs16_cyc_i = wbm_cyc_o & wb_slave_sel_r[16];
assign wbs16_stb_i = wbm_stb_o & wb_slave_sel_r[16];
assign wbs16_we_i = wbm_we_o;
assign wbs16_cti_i = wbm_cti_o;
assign wbs16_bte_i = wbm_bte_o;
assign wbs_dat_o_mux_i[16] = wbs16_dat_o;
assign wbs_ack_o_mux_i[16] = wbs16_ack_o & wb_slave_sel_r[16];
assign wbs_err_o_mux_i[16] = wbs16_err_o & wb_slave_sel_r[16];
assign wbs_rty_o_mux_i[16] = wbs16_rty_o & wb_slave_sel_r[16];
*/
// Master out mux from slave in data
assign wbm_dat_i = wb_slave_sel_r[0] ? wbs_dat_o_mux_i[0] :
wb_slave_sel_r[1] ? wbs_dat_o_mux_i[1] :
wb_slave_sel_r[2] ? wbs_dat_o_mux_i[2] :
/* wb_slave_sel_r[3] ? wbs_dat_o_mux_i[3] :
wb_slave_sel_r[4] ? wbs_dat_o_mux_i[4] :
wb_slave_sel_r[5] ? wbs_dat_o_mux_i[5] :
wb_slave_sel_r[6] ? wbs_dat_o_mux_i[6] :
wb_slave_sel_r[7] ? wbs_dat_o_mux_i[7] :
wb_slave_sel_r[8] ? wbs_dat_o_mux_i[8] :
wb_slave_sel_r[9] ? wbs_dat_o_mux_i[9] :
wb_slave_sel_r[10] ? wbs_dat_o_mux_i[10] :
wb_slave_sel_r[11] ? wbs_dat_o_mux_i[11] :
wb_slave_sel_r[12] ? wbs_dat_o_mux_i[12] :
wb_slave_sel_r[13] ? wbs_dat_o_mux_i[13] :
wb_slave_sel_r[14] ? wbs_dat_o_mux_i[14] :
wb_slave_sel_r[15] ? wbs_dat_o_mux_i[15] :
wb_slave_sel_r[16] ? wbs_dat_o_mux_i[16] :
*/
wbs_dat_o_mux_i[0];
// Master out acks, or together
assign wbm_ack_i = wbs_ack_o_mux_i[0] |
wbs_ack_o_mux_i[1] |
wbs_ack_o_mux_i[2] /*|
wbs_ack_o_mux_i[3] |
wbs_ack_o_mux_i[4] |
wbs_ack_o_mux_i[5] |
wbs_ack_o_mux_i[6] |
wbs_ack_o_mux_i[7] |
wbs_ack_o_mux_i[8] |
wbs_ack_o_mux_i[9] |
wbs_ack_o_mux_i[10] |
wbs_ack_o_mux_i[11] |
wbs_ack_o_mux_i[12] |
wbs_ack_o_mux_i[13] |
wbs_ack_o_mux_i[14] |
wbs_ack_o_mux_i[15] |
wbs_ack_o_mux_i[16] */
;
assign wbm_err_i = wbs_err_o_mux_i[0] |
wbs_err_o_mux_i[1] |
wbs_err_o_mux_i[2] |/*
wbs_err_o_mux_i[3] |
wbs_err_o_mux_i[4] |
wbs_err_o_mux_i[5] |
wbs_err_o_mux_i[6] |
wbs_err_o_mux_i[7] |
wbs_err_o_mux_i[8] |
wbs_err_o_mux_i[9] |
wbs_err_o_mux_i[10] |
wbs_err_o_mux_i[11] |
wbs_err_o_mux_i[12] |
wbs_err_o_mux_i[13] |
wbs_err_o_mux_i[14] |
wbs_err_o_mux_i[15] |
wbs_err_o_mux_i[16] |*/
watchdog_err ;
assign wbm_rty_i = wbs_rty_o_mux_i[0] |
wbs_rty_o_mux_i[1] |
wbs_rty_o_mux_i[2] /*|
wbs_rty_o_mux_i[3] |
wbs_rty_o_mux_i[4] |
wbs_rty_o_mux_i[5] |
wbs_rty_o_mux_i[6] |
wbs_rty_o_mux_i[7] |
wbs_rty_o_mux_i[8] |
wbs_rty_o_mux_i[9] |
wbs_rty_o_mux_i[10] |
wbs_rty_o_mux_i[11] |
wbs_rty_o_mux_i[12] |
wbs_rty_o_mux_i[13] |
wbs_rty_o_mux_i[14] |
wbs_rty_o_mux_i[15] |
wbs_rty_o_mux_i[16]*/;
endmodule
|
module gc_command_fifo(
clk,
rst,
din,
wr_en,
rd_en,
dout,
full,
empty,
data_count,
prog_full
);
input clk;
input rst;
input [28 : 0] din;
input wr_en;
input rd_en;
output [28 : 0] dout;
output full;
output empty;
output [5 : 0] data_count;
output prog_full;
// synthesis translate_off
FIFO_GENERATOR_V8_4 #(
.C_ADD_NGC_CONSTRAINT(0),
.C_APPLICATION_TYPE_AXIS(0),
.C_APPLICATION_TYPE_RACH(0),
.C_APPLICATION_TYPE_RDCH(0),
.C_APPLICATION_TYPE_WACH(0),
.C_APPLICATION_TYPE_WDCH(0),
.C_APPLICATION_TYPE_WRCH(0),
.C_AXI_ADDR_WIDTH(32),
.C_AXI_ARUSER_WIDTH(1),
.C_AXI_AWUSER_WIDTH(1),
.C_AXI_BUSER_WIDTH(1),
.C_AXI_DATA_WIDTH(64),
.C_AXI_ID_WIDTH(4),
.C_AXI_RUSER_WIDTH(1),
.C_AXI_TYPE(0),
.C_AXI_WUSER_WIDTH(1),
.C_AXIS_TDATA_WIDTH(64),
.C_AXIS_TDEST_WIDTH(4),
.C_AXIS_TID_WIDTH(8),
.C_AXIS_TKEEP_WIDTH(4),
.C_AXIS_TSTRB_WIDTH(4),
.C_AXIS_TUSER_WIDTH(4),
.C_AXIS_TYPE(0),
.C_COMMON_CLOCK(1),
.C_COUNT_TYPE(0),
.C_DATA_COUNT_WIDTH(6),
.C_DEFAULT_VALUE("BlankString"),
.C_DIN_WIDTH(29),
.C_DIN_WIDTH_AXIS(1),
.C_DIN_WIDTH_RACH(32),
.C_DIN_WIDTH_RDCH(64),
.C_DIN_WIDTH_WACH(32),
.C_DIN_WIDTH_WDCH(64),
.C_DIN_WIDTH_WRCH(2),
.C_DOUT_RST_VAL("0"),
.C_DOUT_WIDTH(29),
.C_ENABLE_RLOCS(0),
.C_ENABLE_RST_SYNC(1),
.C_ERROR_INJECTION_TYPE(0),
.C_ERROR_INJECTION_TYPE_AXIS(0),
.C_ERROR_INJECTION_TYPE_RACH(0),
.C_ERROR_INJECTION_TYPE_RDCH(0),
.C_ERROR_INJECTION_TYPE_WACH(0),
.C_ERROR_INJECTION_TYPE_WDCH(0),
.C_ERROR_INJECTION_TYPE_WRCH(0),
.C_FAMILY("virtex6"),
.C_FULL_FLAGS_RST_VAL(1),
.C_HAS_ALMOST_EMPTY(0),
.C_HAS_ALMOST_FULL(0),
.C_HAS_AXI_ARUSER(0),
.C_HAS_AXI_AWUSER(0),
.C_HAS_AXI_BUSER(0),
.C_HAS_AXI_RD_CHANNEL(0),
.C_HAS_AXI_RUSER(0),
.C_HAS_AXI_WR_CHANNEL(0),
.C_HAS_AXI_WUSER(0),
.C_HAS_AXIS_TDATA(0),
.C_HAS_AXIS_TDEST(0),
.C_HAS_AXIS_TID(0),
.C_HAS_AXIS_TKEEP(0),
.C_HAS_AXIS_TLAST(0),
.C_HAS_AXIS_TREADY(1),
.C_HAS_AXIS_TSTRB(0),
.C_HAS_AXIS_TUSER(0),
.C_HAS_BACKUP(0),
.C_HAS_DATA_COUNT(1),
.C_HAS_DATA_COUNTS_AXIS(0),
.C_HAS_DATA_COUNTS_RACH(0),
.C_HAS_DATA_COUNTS_RDCH(0),
.C_HAS_DATA_COUNTS_WACH(0),
.C_HAS_DATA_COUNTS_WDCH(0),
.C_HAS_DATA_COUNTS_WRCH(0),
.C_HAS_INT_CLK(0),
.C_HAS_MASTER_CE(0),
.C_HAS_MEMINIT_FILE(0),
.C_HAS_OVERFLOW(0),
.C_HAS_PROG_FLAGS_AXIS(0),
.C_HAS_PROG_FLAGS_RACH(0),
.C_HAS_PROG_FLAGS_RDCH(0),
.C_HAS_PROG_FLAGS_WACH(0),
.C_HAS_PROG_FLAGS_WDCH(0),
.C_HAS_PROG_FLAGS_WRCH(0),
.C_HAS_RD_DATA_COUNT(0),
.C_HAS_RD_RST(0),
.C_HAS_RST(1),
.C_HAS_SLAVE_CE(0),
.C_HAS_SRST(0),
.C_HAS_UNDERFLOW(0),
.C_HAS_VALID(0),
.C_HAS_WR_ACK(0),
.C_HAS_WR_DATA_COUNT(0),
.C_HAS_WR_RST(0),
.C_IMPLEMENTATION_TYPE(0),
.C_IMPLEMENTATION_TYPE_AXIS(1),
.C_IMPLEMENTATION_TYPE_RACH(1),
.C_IMPLEMENTATION_TYPE_RDCH(1),
.C_IMPLEMENTATION_TYPE_WACH(1),
.C_IMPLEMENTATION_TYPE_WDCH(1),
.C_IMPLEMENTATION_TYPE_WRCH(1),
.C_INIT_WR_PNTR_VAL(0),
.C_INTERFACE_TYPE(0),
.C_MEMORY_TYPE(1),
.C_MIF_FILE_NAME("BlankString"),
.C_MSGON_VAL(1),
.C_OPTIMIZATION_MODE(0),
.C_OVERFLOW_LOW(0),
.C_PRELOAD_LATENCY(0),
.C_PRELOAD_REGS(1),
.C_PRIM_FIFO_TYPE("512x36"),
.C_PROG_EMPTY_THRESH_ASSERT_VAL(4),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH(1022),
.C_PROG_EMPTY_THRESH_NEGATE_VAL(5),
.C_PROG_EMPTY_TYPE(0),
.C_PROG_EMPTY_TYPE_AXIS(5),
.C_PROG_EMPTY_TYPE_RACH(5),
.C_PROG_EMPTY_TYPE_RDCH(5),
.C_PROG_EMPTY_TYPE_WACH(5),
.C_PROG_EMPTY_TYPE_WDCH(5),
.C_PROG_EMPTY_TYPE_WRCH(5),
.C_PROG_FULL_THRESH_ASSERT_VAL(31),
.C_PROG_FULL_THRESH_ASSERT_VAL_AXIS(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_RACH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_RDCH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_WACH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_WDCH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_WRCH(1023),
.C_PROG_FULL_THRESH_NEGATE_VAL(30),
.C_PROG_FULL_TYPE(1),
.C_PROG_FULL_TYPE_AXIS(5),
.C_PROG_FULL_TYPE_RACH(5),
.C_PROG_FULL_TYPE_RDCH(5),
.C_PROG_FULL_TYPE_WACH(5),
.C_PROG_FULL_TYPE_WDCH(5),
.C_PROG_FULL_TYPE_WRCH(5),
.C_RACH_TYPE(0),
.C_RD_DATA_COUNT_WIDTH(6),
.C_RD_DEPTH(32),
.C_RD_FREQ(1),
.C_RD_PNTR_WIDTH(5),
.C_RDCH_TYPE(0),
.C_REG_SLICE_MODE_AXIS(0),
.C_REG_SLICE_MODE_RACH(0),
.C_REG_SLICE_MODE_RDCH(0),
.C_REG_SLICE_MODE_WACH(0),
.C_REG_SLICE_MODE_WDCH(0),
.C_REG_SLICE_MODE_WRCH(0),
.C_SYNCHRONIZER_STAGE(2),
.C_UNDERFLOW_LOW(0),
.C_USE_COMMON_OVERFLOW(0),
.C_USE_COMMON_UNDERFLOW(0),
.C_USE_DEFAULT_SETTINGS(0),
.C_USE_DOUT_RST(1),
.C_USE_ECC(0),
.C_USE_ECC_AXIS(0),
.C_USE_ECC_RACH(0),
.C_USE_ECC_RDCH(0),
.C_USE_ECC_WACH(0),
.C_USE_ECC_WDCH(0),
.C_USE_ECC_WRCH(0),
.C_USE_EMBEDDED_REG(0),
.C_USE_FIFO16_FLAGS(0),
.C_USE_FWFT_DATA_COUNT(1),
.C_VALID_LOW(0),
.C_WACH_TYPE(0),
.C_WDCH_TYPE(0),
.C_WR_ACK_LOW(0),
.C_WR_DATA_COUNT_WIDTH(6),
.C_WR_DEPTH(32),
.C_WR_DEPTH_AXIS(1024),
.C_WR_DEPTH_RACH(16),
.C_WR_DEPTH_RDCH(1024),
.C_WR_DEPTH_WACH(16),
.C_WR_DEPTH_WDCH(1024),
.C_WR_DEPTH_WRCH(16),
.C_WR_FREQ(1),
.C_WR_PNTR_WIDTH(5),
.C_WR_PNTR_WIDTH_AXIS(10),
.C_WR_PNTR_WIDTH_RACH(4),
.C_WR_PNTR_WIDTH_RDCH(10),
.C_WR_PNTR_WIDTH_WACH(4),
.C_WR_PNTR_WIDTH_WDCH(10),
.C_WR_PNTR_WIDTH_WRCH(4),
.C_WR_RESPONSE_LATENCY(1),
.C_WRCH_TYPE(0)
)
inst (
.CLK(clk),
.RST(rst),
.DIN(din),
.WR_EN(wr_en),
.RD_EN(rd_en),
.DOUT(dout),
.FULL(full),
.EMPTY(empty),
.DATA_COUNT(data_count),
.PROG_FULL(prog_full),
.BACKUP(),
.BACKUP_MARKER(),
.SRST(),
.WR_CLK(),
.WR_RST(),
.RD_CLK(),
.RD_RST(),
.PROG_EMPTY_THRESH(),
.PROG_EMPTY_THRESH_ASSERT(),
.PROG_EMPTY_THRESH_NEGATE(),
.PROG_FULL_THRESH(),
.PROG_FULL_THRESH_ASSERT(),
.PROG_FULL_THRESH_NEGATE(),
.INT_CLK(),
.INJECTDBITERR(),
.INJECTSBITERR(),
.ALMOST_FULL(),
.WR_ACK(),
.OVERFLOW(),
.ALMOST_EMPTY(),
.VALID(),
.UNDERFLOW(),
.RD_DATA_COUNT(),
.WR_DATA_COUNT(),
.PROG_EMPTY(),
.SBITERR(),
.DBITERR(),
.M_ACLK(),
.S_ACLK(),
.S_ARESETN(),
.M_ACLK_EN(),
.S_ACLK_EN(),
.S_AXI_AWID(),
.S_AXI_AWADDR(),
.S_AXI_AWLEN(),
.S_AXI_AWSIZE(),
.S_AXI_AWBURST(),
.S_AXI_AWLOCK(),
.S_AXI_AWCACHE(),
.S_AXI_AWPROT(),
.S_AXI_AWQOS(),
.S_AXI_AWREGION(),
.S_AXI_AWUSER(),
.S_AXI_AWVALID(),
.S_AXI_AWREADY(),
.S_AXI_WID(),
.S_AXI_WDATA(),
.S_AXI_WSTRB(),
.S_AXI_WLAST(),
.S_AXI_WUSER(),
.S_AXI_WVALID(),
.S_AXI_WREADY(),
.S_AXI_BID(),
.S_AXI_BRESP(),
.S_AXI_BUSER(),
.S_AXI_BVALID(),
.S_AXI_BREADY(),
.M_AXI_AWID(),
.M_AXI_AWADDR(),
.M_AXI_AWLEN(),
.M_AXI_AWSIZE(),
.M_AXI_AWBURST(),
.M_AXI_AWLOCK(),
.M_AXI_AWCACHE(),
.M_AXI_AWPROT(),
.M_AXI_AWQOS(),
.M_AXI_AWREGION(),
.M_AXI_AWUSER(),
.M_AXI_AWVALID(),
.M_AXI_AWREADY(),
.M_AXI_WID(),
.M_AXI_WDATA(),
.M_AXI_WSTRB(),
.M_AXI_WLAST(),
.M_AXI_WUSER(),
.M_AXI_WVALID(),
.M_AXI_WREADY(),
.M_AXI_BID(),
.M_AXI_BRESP(),
.M_AXI_BUSER(),
.M_AXI_BVALID(),
.M_AXI_BREADY(),
.S_AXI_ARID(),
.S_AXI_ARADDR(),
.S_AXI_ARLEN(),
.S_AXI_ARSIZE(),
.S_AXI_ARBURST(),
.S_AXI_ARLOCK(),
.S_AXI_ARCACHE(),
.S_AXI_ARPROT(),
.S_AXI_ARQOS(),
.S_AXI_ARREGION(),
.S_AXI_ARUSER(),
.S_AXI_ARVALID(),
.S_AXI_ARREADY(),
.S_AXI_RID(),
.S_AXI_RDATA(),
.S_AXI_RRESP(),
.S_AXI_RLAST(),
.S_AXI_RUSER(),
.S_AXI_RVALID(),
.S_AXI_RREADY(),
.M_AXI_ARID(),
.M_AXI_ARADDR(),
.M_AXI_ARLEN(),
.M_AXI_ARSIZE(),
.M_AXI_ARBURST(),
.M_AXI_ARLOCK(),
.M_AXI_ARCACHE(),
.M_AXI_ARPROT(),
.M_AXI_ARQOS(),
.M_AXI_ARREGION(),
.M_AXI_ARUSER(),
.M_AXI_ARVALID(),
.M_AXI_ARREADY(),
.M_AXI_RID(),
.M_AXI_RDATA(),
.M_AXI_RRESP(),
.M_AXI_RLAST(),
.M_AXI_RUSER(),
.M_AXI_RVALID(),
.M_AXI_RREADY(),
.S_AXIS_TVALID(),
.S_AXIS_TREADY(),
.S_AXIS_TDATA(),
.S_AXIS_TSTRB(),
.S_AXIS_TKEEP(),
.S_AXIS_TLAST(),
.S_AXIS_TID(),
.S_AXIS_TDEST(),
.S_AXIS_TUSER(),
.M_AXIS_TVALID(),
.M_AXIS_TREADY(),
.M_AXIS_TDATA(),
.M_AXIS_TSTRB(),
.M_AXIS_TKEEP(),
.M_AXIS_TLAST(),
.M_AXIS_TID(),
.M_AXIS_TDEST(),
.M_AXIS_TUSER(),
.AXI_AW_INJECTSBITERR(),
.AXI_AW_INJECTDBITERR(),
.AXI_AW_PROG_FULL_THRESH(),
.AXI_AW_PROG_EMPTY_THRESH(),
.AXI_AW_DATA_COUNT(),
.AXI_AW_WR_DATA_COUNT(),
.AXI_AW_RD_DATA_COUNT(),
.AXI_AW_SBITERR(),
.AXI_AW_DBITERR(),
.AXI_AW_OVERFLOW(),
.AXI_AW_UNDERFLOW(),
.AXI_W_INJECTSBITERR(),
.AXI_W_INJECTDBITERR(),
.AXI_W_PROG_FULL_THRESH(),
.AXI_W_PROG_EMPTY_THRESH(),
.AXI_W_DATA_COUNT(),
.AXI_W_WR_DATA_COUNT(),
.AXI_W_RD_DATA_COUNT(),
.AXI_W_SBITERR(),
.AXI_W_DBITERR(),
.AXI_W_OVERFLOW(),
.AXI_W_UNDERFLOW(),
.AXI_B_INJECTSBITERR(),
.AXI_B_INJECTDBITERR(),
.AXI_B_PROG_FULL_THRESH(),
.AXI_B_PROG_EMPTY_THRESH(),
.AXI_B_DATA_COUNT(),
.AXI_B_WR_DATA_COUNT(),
.AXI_B_RD_DATA_COUNT(),
.AXI_B_SBITERR(),
.AXI_B_DBITERR(),
.AXI_B_OVERFLOW(),
.AXI_B_UNDERFLOW(),
.AXI_AR_INJECTSBITERR(),
.AXI_AR_INJECTDBITERR(),
.AXI_AR_PROG_FULL_THRESH(),
.AXI_AR_PROG_EMPTY_THRESH(),
.AXI_AR_DATA_COUNT(),
.AXI_AR_WR_DATA_COUNT(),
.AXI_AR_RD_DATA_COUNT(),
.AXI_AR_SBITERR(),
.AXI_AR_DBITERR(),
.AXI_AR_OVERFLOW(),
.AXI_AR_UNDERFLOW(),
.AXI_R_INJECTSBITERR(),
.AXI_R_INJECTDBITERR(),
.AXI_R_PROG_FULL_THRESH(),
.AXI_R_PROG_EMPTY_THRESH(),
.AXI_R_DATA_COUNT(),
.AXI_R_WR_DATA_COUNT(),
.AXI_R_RD_DATA_COUNT(),
.AXI_R_SBITERR(),
.AXI_R_DBITERR(),
.AXI_R_OVERFLOW(),
.AXI_R_UNDERFLOW(),
.AXIS_INJECTSBITERR(),
.AXIS_INJECTDBITERR(),
.AXIS_PROG_FULL_THRESH(),
.AXIS_PROG_EMPTY_THRESH(),
.AXIS_DATA_COUNT(),
.AXIS_WR_DATA_COUNT(),
.AXIS_RD_DATA_COUNT(),
.AXIS_SBITERR(),
.AXIS_DBITERR(),
.AXIS_OVERFLOW(),
.AXIS_UNDERFLOW()
);
// synthesis translate_on
endmodule
|
module decoder(
input [6:0] address,
output reg bar_led_ce_n,
board_led_ce_n,
switch_ce_n,
mem1_ce_n,
mem2_ce_n);
always @(address) begin
// default, disabled
switch_ce_n = 1'b1;
bar_led_ce_n = 1'b1;
mem2_ce_n = 1'b1;
board_led_ce_n = 1'b1;
mem1_ce_n = 1'b1;
casex (address)
7'h74: switch_ce_n = 1'b0;
7'h6C: bar_led_ce_n = 1'b0;
7'h5?: mem2_ce_n = 1'b0;
7'h2F: board_led_ce_n = 1'b0;
7'h0?: mem1_ce_n = 1'b0;
endcase
end
endmodule
|
module rominout2 (
address_a,
address_b,
clock,
q_a,
q_b);
input [8:0] address_a;
input [8:0] address_b;
input clock;
output [31:0] q_a;
output [31:0] q_b;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [31:0] sub_wire0;
wire [31:0] sub_wire1;
wire sub_wire2 = 1'h0;
wire [31:0] sub_wire3 = 32'h0;
wire [31:0] q_b = sub_wire0[31:0];
wire [31:0] q_a = sub_wire1[31:0];
altsyncram altsyncram_component (
.clock0 (clock),
.wren_a (sub_wire2),
.address_b (address_b),
.data_b (sub_wire3),
.wren_b (sub_wire2),
.address_a (address_a),
.data_a (sub_wire3),
.q_b (sub_wire0),
.q_a (sub_wire1)
// synopsys translate_off
,
.aclr0 (),
.aclr1 (),
.addressstall_a (),
.addressstall_b (),
.byteena_a (),
.byteena_b (),
.clock1 (),
.clocken0 (),
.clocken1 (),
.clocken2 (),
.clocken3 (),
.eccstatus (),
.rden_a (),
.rden_b ()
// synopsys translate_on
);
defparam
altsyncram_component.address_reg_b = "CLOCK0",
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_input_b = "BYPASS",
altsyncram_component.clock_enable_output_a = "BYPASS",
altsyncram_component.clock_enable_output_b = "BYPASS",
altsyncram_component.indata_reg_b = "CLOCK0",
altsyncram_component.init_file = "./MIF/rominit.mif",
altsyncram_component.intended_device_family = "Cyclone II",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 512,
altsyncram_component.numwords_b = 512,
altsyncram_component.operation_mode = "BIDIR_DUAL_PORT",
altsyncram_component.outdata_aclr_a = "NONE",
altsyncram_component.outdata_aclr_b = "NONE",
altsyncram_component.outdata_reg_a = "CLOCK0",
altsyncram_component.outdata_reg_b = "CLOCK0",
altsyncram_component.power_up_uninitialized = "FALSE",
altsyncram_component.widthad_a = 9,
altsyncram_component.widthad_b = 9,
altsyncram_component.width_a = 32,
altsyncram_component.width_b = 32,
altsyncram_component.width_byteena_a = 1,
altsyncram_component.width_byteena_b = 1,
altsyncram_component.wrcontrol_wraddress_reg_b = "CLOCK0";
endmodule
|
module sky130_fd_sc_hd__and2_1 (
X ,
A ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__and2 base (
.X(X),
.A(A),
.B(B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
|
module sky130_fd_sc_hd__and2_1 (
X,
A,
B
);
output X;
input A;
input B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__and2 base (
.X(X),
.A(A),
.B(B)
);
endmodule
|
module sky130_fd_sc_ls__o2bb2ai_4 (
Y ,
A1_N,
A2_N,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1_N;
input A2_N;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__o2bb2ai base (
.Y(Y),
.A1_N(A1_N),
.A2_N(A2_N),
.B1(B1),
.B2(B2),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
|
module sky130_fd_sc_ls__o2bb2ai_4 (
Y ,
A1_N,
A2_N,
B1 ,
B2
);
output Y ;
input A1_N;
input A2_N;
input B1 ;
input B2 ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__o2bb2ai base (
.Y(Y),
.A1_N(A1_N),
.A2_N(A2_N),
.B1(B1),
.B2(B2)
);
endmodule
|
module fir(aclk, s_axis_data_tvalid, s_axis_data_tready, s_axis_data_tdata, m_axis_data_tvalid, m_axis_data_tdata)
/* synthesis syn_black_box black_box_pad_pin="aclk,s_axis_data_tvalid,s_axis_data_tready,s_axis_data_tdata[15:0],m_axis_data_tvalid,m_axis_data_tdata[39:0]" */;
input aclk;
input s_axis_data_tvalid;
output s_axis_data_tready;
input [15:0]s_axis_data_tdata;
output m_axis_data_tvalid;
output [39:0]m_axis_data_tdata;
endmodule
|
module velocityControlHdl_Clamp_block1
(
preSat,
saturated,
preIntegrator,
Clamp
);
input signed [35:0] preSat; // sfix36_En22
input saturated;
input signed [35:0] preIntegrator; // sfix36_En35
output Clamp;
wire Compare_To_Zero_out1;
wire Compare_To_Zero1_out1;
wire Compare_To_Zero_out1_1;
wire Logical_Operator_out1;
// <S26>/Compare To Zero
assign Compare_To_Zero_out1 = (preIntegrator <= 36'sh000000000 ? 1'b1 :
1'b0);
// <S26>/Compare To Zero1
assign Compare_To_Zero1_out1 = (preSat <= 36'sh000000000 ? 1'b1 :
1'b0);
// <S26>/Logical Operator
assign Compare_To_Zero_out1_1 = ~ (Compare_To_Zero_out1 ^ Compare_To_Zero1_out1);
// <S26>/AND
assign Logical_Operator_out1 = Compare_To_Zero_out1_1 & saturated;
assign Clamp = Logical_Operator_out1;
endmodule
|
module bcd_to_segment
(
input [3:0] bcd_data,
output reg [7:0] seg_data
);
always @(bcd_data) begin
case (bcd_data)
4'b0000: seg_data <= 8'b11000000; // 0
4'b0001: seg_data <= 8'b11111001; // 1
4'b0010: seg_data <= 8'b10100100; // 2
4'b0011: seg_data <= 8'b10110000; // 3
4'b0100: seg_data <= 8'b10011001; // 4
4'b0101: seg_data <= 8'b10010010; // 5
4'b0110: seg_data <= 8'b10000010; // 6
4'b0111: seg_data <= 8'b11111000; // 7
4'b1000: seg_data <= 8'b10000000; // 8
4'b1001: seg_data <= 8'b10010000; // 9
4'b1010: seg_data <= 8'b01111111; // dp
default: seg_data <= 8'b11111111; // off
endcase
end
endmodule
|
module FPU ( ss_clock, FpInst, FpOp, FpLd, Reset,
fprf_dout1, fprf_dout2, RoundingMode,
FpBusy, FracResult, ExpResult, SignResult, SNnotDB,
Excep, ConditionCodes,
ss_scan_mode, fp_ctl_scan_in, fp_ctl_scan_out );
input ss_clock, FpOp, FpLd, Reset, ss_scan_mode, fp_ctl_scan_in;
input [9:0] FpInst;
output [1:0] ConditionCodes;
input [63:0] fprf_dout1;
input [63:0] fprf_dout2;
output [5:0] Excep;
input [1:0] RoundingMode;
output [54:3] FracResult;
output [10:0] ExpResult;
output FpBusy, SignResult, SNnotDB, fp_ctl_scan_out;
// ************************** */
wire FracAregLoadEn, FracBregLoadEn, FracCregLoadEn, FracCregLC,
FracTregLoadEn, SROneMore, SRToSticky, notStickyInForSR,
InitialMulStep, InitialCarryBit, SumCarryLoadEn, SumOut0,
CarryOut0, CarryOut3, RomOutputs_18, RomOutputs_55, notFracYFromD1A,
notFracYFromD2A, notFracYFromD3A, notSticky1, FracBregSign,
BregFPMSBM1, notAM31_3, notAM2_0, StickyForSR1, AregMaster_32,
notAregMasterFPMSBP1, CALSB, CBLSB, CCLSB, notFracZero, FracZero,
FracAgtB, SubResultNorm, Conditionals_10, notPossibleOv, notNO_1,
RomOutputs_20, ExpAregLoadEn, ExpAregLC0, ExpAregLC1, ExpBregLoadEn,
ExpBregLC0, ExpBregLC1, RomOutputs_27, CarryIn, Constantb, Constantc,
Constantd, Constante, Constantf, Constantg, Constanth, Conditionals_12,
Conditionals_3, notAInfNAN, notAZeroDenorm, notBInfNAN, notBZeroDenorm,
notExpUnderflow, notExpOverflow, notExpException, OprSNnotDB ;
wire [2:0] FracAregLC ;
wire [2:0] FracBregLC ;
wire [1:0] FracYbusLSBs ;
wire [1:0] InFromCregOr0 ;
wire [1:0] InForCreg ;
wire [1:0] InForCregDB ;
wire [32:29] RomOutputs_32_29 ;
wire [46:44] RomOutputs_46_44 ;
wire [4:0] FracRound ;
wire [3:0] SRControl ;
wire [3:0] SLControl ;
wire [2:0] LIB ;
wire [8:0] TopBitsIn ;
wire [3:0] Shift ;
wire [3:0] Pos ;
wire [3:0] Zero ;
wire [4:0] MulLenSel ;
wire [3:0] notSticky4 ;
wire [1:0] Sticky2 ;
wire [1:0] StickyExtra ;
wire [1:0] CregSNBits ;
wire [1:0] CregInSL2SQRT ;
wire [8:0] notMultip ;
wire [57:40] AregMaster_57_40 ;
wire [7:0] AregMaster_7_0 ;
wire [1:0] TregLSBs ;
wire [2:0] SumInLSBs ;
wire [2:0] CarryInLSBs ;
wire [1:0] SALSBs ;
wire [1:0] SBLSBs ;
wire [1:0] SCLSBs ;
wire [3:0] StepRemBits ;
wire [3:1] notsh ;
wire [7:0] ExpIn ;
wire [12:0] notExpShiftResult ;
wire [7:0] SelectedMIptr ;
wire [63:0] U_RomOutputs ;
// Meiko FPU core control logic
fp_ctl fpctl ( .ss_clock (ss_clock), .AregMaster_32 (AregMaster_32),
.BregFPMSBM1 (BregFPMSBM1), .CALSB (CALSB), .CBLSB (CBLSB),
.CCLSB (CCLSB), .Conditionals_3 (Conditionals_3),
.Conditionals_10 (Conditionals_10), .Conditionals_12 (Conditionals_12),
.FpLd (FpLd), .FpOp (FpOp), .FracAgtB (FracAgtB),
.FracBregSign (FracBregSign), .FracZero (FracZero),
.notAInfNAN (notAInfNAN), .notAM31_3 (notAM31_3),
.notAM2_0 (notAM2_0), .notAregMasterFPMSBP1 (notAregMasterFPMSBP1),
.notAZeroDenorm (notAZeroDenorm), .notBInfNAN (notBInfNAN),
.notBZeroDenorm (notBZeroDenorm), .notExpUnderflow (notExpUnderflow),
.notExpOverflow (notExpOverflow), .notExpException (notExpException),
.notPossibleOv (notPossibleOv), .notFracZero (notFracZero),
.notSticky1 (notSticky1), .ResetIn (Reset), .RS2_63 (fprf_dout2[63] ),
.RS1_63 (fprf_dout1[63] ), .StickyForSR1 (StickyForSR1),
.SubResultNorm (SubResultNorm), .AregMaster_57_40 (AregMaster_57_40),
.AregMaster_7_0 (AregMaster_7_0), .CarryInLSBs (CarryInLSBs),
.CregInSL2SQRT (CregInSL2SQRT), .CregSNBits (CregSNBits),
.ExpIn (ExpIn), .FpInst (FpInst),
.notExpShiftResult (notExpShiftResult), .notMultip (notMultip),
.notSticky4 (notSticky4), .RoundingMode (RoundingMode),
.SALSBs (SALSBs), .SBLSBs (SBLSBs), .SCLSBs (SCLSBs),
.StepRemBits (StepRemBits), .Sticky2 (Sticky2),
.StickyExtra (StickyExtra), .SumInLSBs (SumInLSBs),
.TregLSBs (TregLSBs), .U_RomOutputs (U_RomOutputs ),
.CarryIn (CarryIn), .CarryOut0 (CarryOut0), .CarryOut3 (CarryOut3),
.Constantb (Constantb), .Constantc (Constantc), .Constantd (Constantd),
.Constante (Constante), .Constantf (Constantf), .Constantg (Constantg),
.Constanth (Constanth), .ExpAregLC0 (ExpAregLC0),
.ExpAregLC1 (ExpAregLC1), .ExpAregLoadEn (ExpAregLoadEn),
.ExpBregLC0 (ExpBregLC0), .ExpBregLC1 (ExpBregLC1),
.ExpBregLoadEn (ExpBregLoadEn), .FracAregLoadEn (FracAregLoadEn),
.FracBregLoadEn (FracBregLoadEn), .FracCregLC (FracCregLC),
.FracCregLoadEn (FracCregLoadEn), .FracTregLoadEn (FracTregLoadEn),
.FpBusy (FpBusy), .InitialCarryBit (InitialCarryBit),
.InitialMulStep (InitialMulStep), .notFracYFromD1A (notFracYFromD1A),
.notFracYFromD2A (notFracYFromD2A), .notFracYFromD3A (notFracYFromD3A),
.notNO_1 (notNO_1), .notStickyInForSR (notStickyInForSR),
.OprSNnotDB (OprSNnotDB), .RomOutputs_18 (RomOutputs_18),
.RomOutputs_20 (RomOutputs_20), .RomOutputs_27 (RomOutputs_27),
.RomOutputs_55 (RomOutputs_55), .SignResult (SignResult),
.SNnotDB (SNnotDB), .SROneMore (SROneMore), .SRToSticky (SRToSticky),
.SumCarryLoadEn (SumCarryLoadEn), .SumOut0 (SumOut0),
.ConditionCodes (ConditionCodes), .Excep (Excep),
.FracAregLC (FracAregLC), .FracBregLC (FracBregLC),
.FracRound (FracRound), .FracYbusLSBs (FracYbusLSBs),
.InForCreg (InForCreg), .InForCregDB (InForCregDB),
.InFromCregOr0 (InFromCregOr0), .LIB (LIB), .MulLenSel (MulLenSel),
.notsh (notsh), .Pos (Pos), .RomOutputs_32_29 (RomOutputs_32_29),
.RomOutputs_46_44 (RomOutputs_46_44), .SelectedMIptr(SelectedMIptr ),
.Shift (Shift), .SRControl (SRControl), .TopBitsIn (TopBitsIn),
.Zero (Zero),
.ss_scan_mode (ss_scan_mode),
.fp_ctl_scan_in (fp_exp_scan_out),
.fp_ctl_scan_out (fp_ctl_scan_out) );
// Instance of the ROM Megacell
fp_rom fprom ( .ss_clock(ss_clock),
.rom_adr(SelectedMIptr),
.rom_dout(U_RomOutputs),
.rom_scan_out(fp_rom_scan_out),
.rom_scan_in(fp_ctl_scan_out),
.ss_scan_mode(ss_scan_mode) );
// exponent datapath
fp_exp fpexp ( .ss_clock (ss_clock ), .SNnotDB (SNnotDB ),
.OprSNnotDB (OprSNnotDB ), .RS2_exp (fprf_dout2[62:52] ),
.RS1_exp (fprf_dout1[62:52] ), .FracAregForInt (AregMaster_57_40[54:47] ),
.notSLFromNorm ({notNO_1, notsh[3:1]} ), .ShiftBy8 (RomOutputs_20 ),
.ExpAregLoadEn (ExpAregLoadEn ), .ExpAregLC0 (ExpAregLC0 ),
.ExpAregLC1 (ExpAregLC1 ), .ExpBregLoadEn (ExpBregLoadEn ),
.ExpBregLC0 (ExpBregLC0 ), .ExpBregLC1 (ExpBregLC1 ),
.ExpXCtl0 (RomOutputs_32_29[29] ), .ExpXCtl1 (RomOutputs_32_29[30] ),
.ExpYCtl0 (RomOutputs_32_29[31] ), .ExpYCtl1 (RomOutputs_32_29[32] ),
.Sub(RomOutputs_27 ), .CarryIn (CarryIn ), .Constantb (Constantb ),
.Constantc (Constantc ), .Constantd (Constantd ),
.Constante (Constante ), .Constantf (Constantf ),
.Constantg (Constantg ), .Constanth (Constanth ),
.AregMasterBufOut (ExpIn ), .ExpResultBuf (ExpResult ),
.notExpShiftResult (notExpShiftResult[12:0] ),
.ExpZero (Conditionals_12 ), .ExpResult_12 (Conditionals_3 ),
.SLControl (SLControl ), .notAInfNaN (notAInfNAN ),
.notAZeroDenorm (notAZeroDenorm ), .notBInfNaN (notBInfNAN ),
.notBZeroDenorm (notBZeroDenorm ), .notUnderflow (notExpUnderflow ),
.notOverflow (notExpOverflow ), .notExpException (notExpException ),
.ss_scan_mode (ss_scan_mode),
.fp_exp_scan_in (fp_fpc_scan_out),
.fp_exp_scan_out (fp_exp_scan_out) );
// fraction datapath
fp_frac fpfrac (.ss_clock (ss_clock ), .FracAregLoadEn (FracAregLoadEn),
.FracAregLC (FracAregLC ), .FracBregLoadEn (FracBregLoadEn ),
.FracBregLC (FracBregLC ), .FracCregLoadEn (FracCregLoadEn ),
.FracCregLC (FracCregLC ), .FracTregLoadEn (FracTregLoadEn ),
.FracYbusLSBs (FracYbusLSBs ), .InFromCregOr0 (InFromCregOr0 ),
.InForCreg (InForCreg ), .InForCregDB (InForCregDB ),
.Constantb (RomOutputs_46_44[45] ), .Constantd (FracRound[4] ),
.Constante (FracRound[3] ), .Constantf (FracRound[2] ),
.Constantg (FracRound[1] ), .Constanth (FracRound[0] ),
.RS2_frac (fprf_dout2[54:0] ), .RS1_frac (fprf_dout1[54:0] ),
.SNnotDB (SNnotDB ), .OprSNnotDB(OprSNnotDB), .SRControl (SRControl ),
.SROneMore (SROneMore ), .SRToSticky (SRToSticky ),
.SLControl (SLControl ), .LIB (LIB ), .TopBitsIn (TopBitsIn ),
.notStickyInForSR (notStickyInForSR ), .Shift (Shift ),
.Pos (Pos ), .Zero (Zero ), .InitialMulStep (InitialMulStep ),
.InitialCarryBit (InitialCarryBit ),
.SumCarryLoadEn (SumCarryLoadEn ), .MulLenSel (MulLenSel ),
.SumOut0 (SumOut0 ), .CarryOut0 (CarryOut0 ), .CarryOut3 (CarryOut3 ),
.LeftnotRight (RomOutputs_18 ), .FracALUOpSub (RomOutputs_46_44[44] ),
.FracALUOpDiv (RomOutputs_55 ), .notFracYFromD1 (notFracYFromD1A ),
.notFracYFromD2 (notFracYFromD2A ), .notFracYFromD3 (notFracYFromD3A),
.FracXFromB (RomOutputs_46_44[46] ), .notSticky4 (notSticky4 ),
.Sticky2 (Sticky2 ), .notSticky1 (notSticky1 ),
.StickyExtra (StickyExtra ), .Creg_30_29 (CregSNBits ),
.Creg_56_55 (CregInSL2SQRT ), .BregMaster_57 (FracBregSign ),
.BregMaster_54 (BregFPMSBM1 ), .notMultip (notMultip ),
.notAM31_3 (notAM31_3 ), .notAM2_0 (notAM2_0 ),
.StickyForSR1 (StickyForSR1 ),
.AregMaster_57_40 (AregMaster_57_40[57:40] ),
.AregMaster_32 (AregMaster_32 ),
.AregMaster_7_0 (AregMaster_7_0[7:0] ),
.notAregMasterFPMSBP1 (notAregMasterFPMSBP1 ),
.Treg_1_0 (TregLSBs ), .SumInLSBs (SumInLSBs ),
.CarryInLSBs (CarryInLSBs ), .SALSBs (SALSBs ), .SBLSBs (SBLSBs ),
.SCLSBs (SCLSBs ), .CALSB (CALSB ), .CBLSB (CBLSB ), .CCLSB (CCLSB ),
.notFracZero (notFracZero ), .FracZero (FracZero ),
.FracResult_57 (FracAgtB ), .SubResultNorm (SubResultNorm ),
.FracResult_56 (Conditionals_10 ),
.FracResult_55_52 (StepRemBits ), .notPossibleOv (notPossibleOv ),
.FracResultBufout (FracResult ),
.ss_scan_mode (ss_scan_mode),
.fp_frac_scan_in (fp_rom_scan_out),
.fp_frac_scan_out (fp_frac_scan_out) );
/*
fp_fpm fpfpm (.fprf_din( fprf_din[63:0] ),
.fpm_inx(fpm_inx), .fpm_unfin(fpm_unfin),
.fprf_dout1( fprf_dout1[63:0] ), .fprf_dout2( fprf_dout2[63:0] ),
.ld_fpu_w( ld_fpu_w[63:0] ),
.FracResult( FracResult[54:3] ),
.ExpResult( ExpResult[10:0] ),
.SignResult(SignResult),
.fpm_inst( fpm_inst[1:0] ),
.rnd_mode( RoundingMode[1:0] ),
.res_select( res_select[1:0] ),
.rfin_select(rfin_select),
.fpm_start(fpm_start),
.ss_clock(ss_clock),
.ss_scan_mode (ss_scan_mode),
.fp_fpm_scan_in(fp_frac_scan_out),
.fp_fpm_scan_out(fp_fpm_scan_out) );
// Added spare cells
spares fpufpc_spares ();
*/
endmodule
|
module AregInexact (RomInexactRound, SNnotDB,
AMCBit, AM32, AM3, notAM31_3, notAM2_0,
Inexact);
input RomInexactRound;
input SNnotDB;
input AMCBit, AM32, AM3, notAM31_3, notAM2_0;
output Inexact;
//Inexact = (AM[0:2] != 0) or (SNnotDB and ((AM[32] & AMCbit) or AM[31:3]))
// or (DBnotSN and ((AM[3] & AMCbit)))
// InexactSN = PostNormBy1SNBit | AM31_19 | AM18_3 | AM2_0
// InexactDB = PostNormBy1DBBit | AM2_0
ME_NAND2 aig2 (AMCBit, AM32, notPostNormBy1SNBit);
ME_NAND2 aig3 (AMCBit, AM3, notPostNormBy1DBBit);
ME_NAND2 aig12 (notPostNormBy1DBBit, notAM2_0, UInexactDB);
ME_NAND2 g_0 (UInexactDB, RomInexactRound, notInexactDB);
ME_NAND3 aig13 (notPostNormBy1SNBit, notAM2_0, notAM31_3, UInexactSN);
ME_NAND2 g_1 (UInexactSN, RomInexactRound, notInexactSN);
ME_NMUX2B aig14 (SNnotDB, notInexactDB, notInexactSN, Inexact);
endmodule
|
module AregLoadCtl (ROM,
LoadOprs,
notAbortWB,
PreventSwap,
FracAregLC, FracAregLoadEn,
LoadFromMult, // Export to Breg
SelInitRemBits);
input [`end_frac_areg_field:`start_frac_areg_field] ROM;
input LoadOprs,
notAbortWB,
PreventSwap;
output [2:0] FracAregLC;
output FracAregLoadEn,
LoadFromMult,
SelInitRemBits;
ME_TIEOFF toff (vdd, gnd);
ME_INVA iopl (LoadOprs, notLoadOprs);
ME_AND2 alcn1 (ROM[`u_FracAregFromFunc2], notLoadOprs,
FracAregLC[2]);
ME_AND2 alcn2 (ROM[`u_FracAregFromFunc1], notLoadOprs,
FracAregLC[1]);
ME_AND2 alcn3 (ROM[`u_FracAregFromFunc0], notLoadOprs,
FracAregLC[0]);
ME_OR4 alcne (ROM[`u_FracAregFromFunc0],
ROM[`u_FracAregFromFunc1],
ROM[`u_FracAregFromFunc2],
LoadOprs,
LoadEn);
//ME_AND3 alcni (LoadEn, notAbortWB, notPreventSwap, FracAregLoadEn);
ME_AND2 alcni (LoadEn, notAbortWB, FracAregLoadEn_p);
ME_NMUX2B_B alcn0 (FracAregLoadEn_p, vdd, PreventSwap, FracAregLoadEn);
ME_AND3 alcnf (ROM[`u_FracAregFromFunc0],
ROM[`u_FracAregFromFunc1],
ROM[`u_FracAregFromFunc2],
LoadFromMult); // 1 1 1
ME_INVA alcn7 (ROM[`u_FracAregFromFunc0], notFunc0);
ME_INVA alcn8 (ROM[`u_FracAregFromFunc2], notFunc2);
ME_AND3_B alcnh (notFunc0,
ROM[`u_FracAregFromFunc1],
notFunc2,
SelInitRemBits); // 0 1 0 ie FracAregFromFracBreg
endmodule
|
module BregLoadCtl (RomFracBregLC,
RomBSL2InFromC,
LoadOprs,
notAbortWB,
PreventSwap,
LoadFromMult,
CregInSL2SQRT,
FracBregLC, FracBregLoadEn,
InFromCregOr0);
input [`end_frac_breg_field:`start_frac_breg_field] RomFracBregLC;
input LoadFromMult;
input LoadOprs;
input RomBSL2InFromC,
notAbortWB, PreventSwap;
input [1:0] CregInSL2SQRT;
output [2:0] FracBregLC;
output FracBregLoadEn;
output [1:0] InFromCregOr0;
ME_TIEOFF toff (vdd, gnd);
// SQRT Logic
ME_AND2 ssg81 (CregInSL2SQRT[1], RomBSL2InFromC, InFromCregOr0[1]);
ME_AND2 ssg80 (CregInSL2SQRT[0], RomBSL2InFromC, InFromCregOr0[0]);
// Breg Load Control
ME_INVA iopl (LoadOprs, notLoadOprs);
ME_AND2 alcn3 (LoadFromMult, notLoadOprs, FracBregLC[2]);
ME_AND2 alcn2 (RomFracBregLC[`u_FracBregFromFunc1], notLoadOprs, FracBregLC[1]);
ME_AND2 alcn1 (RomFracBregLC[`u_FracBregFromFunc0], notLoadOprs, FracBregLC[0]);
ME_OR4 alcne (RomFracBregLC[`u_FracBregFromFunc0],
RomFracBregLC[`u_FracBregFromFunc1],
LoadFromMult,
LoadOprs,
LoadEn);
//ME_AND3 brme (LoadEn, notAbortWB, notPreventSwap, FracBregLoadEn);
ME_AND2 alcni (LoadEn, notAbortWB, FracBregLoadEn_p);
ME_NMUX2B_B alcn0 (FracBregLoadEn_p, vdd, PreventSwap, FracBregLoadEn);
endmodule
|
module carrysaveregslsb (Rom_ResetMul,
notMultip0,
notAbortWB,
SumCarryLoadEn,
InitialMulStep,
/* dhn--01/10/90 notInitialSumZero, */
InitialCarryBit);
input Rom_ResetMul,
notAbortWB,
notMultip0;
output InitialCarryBit,
SumCarryLoadEn,
InitialMulStep;
/*** dhn--01/10/90 output notInitialSumZero ;
//wire notInitialSumZero = InitialCarryBit;
con1 g0 (InitialCarryBit, notInitialSumZero);
*** dhn--01/10/90 ***/
ME_BUFF g00 (notAbortWB, SumCarryLoadEn);
ME_INV_B g01 (notMultip0, InitialCarryBit);
ME_BUFF g02 (Rom_ResetMul, InitialMulStep);
endmodule
|
module CaseGeneration (
Rom_Feedback,
Rom_Condition,
SubResultNorm,
Cond_SignsDiffer,
notExpUnderflow, notExpOverflow, notExpException, notPossibleOv, notFracZero,
RCondition,
Feedback);
input [4:0]Rom_Feedback;
input [3:0]Rom_Condition;
input SubResultNorm;
input Cond_SignsDiffer;
input notExpUnderflow, notExpOverflow, notExpException, notPossibleOv, notFracZero;
output [4:0]Feedback;
output RCondition; // Speed critical signal
// ***************************************//
// Case Generation //
// ***************************************//
ME_INV_A cnsb (Rom_Condition[0], notCondSel0);
ME_AND3 cqsb (Rom_Condition[1], Rom_Condition[2], Rom_Condition[3],
Rom_Case);
ME_AND2 ril (Rom_Case, notCondSel0, Rom_Sub_Sign_Case);
ME_AND2_B ris (Rom_Case, Rom_Condition[0], RomRoundCase);
// ***************************************//
// Rounding Case Address Generation //
// ***************************************//
wire [4:0] notUFeedback;
//ME_INVA g1_0 (ExpUnderflow, notExpUnderflow);
//ME_INVA g1_1 (ExpOverflow, notExpOverflow);
//ME_AND2 fzfz (notExpUnderflow, notExpOverflow, notExpException);
// Note SubResultNorm and notPossibleOv are time critical
ME_NAND3_B nrc (SubResultNorm, notExpException, notPossibleOv,
RCondition);
//ME_NAND4 nrc (SubResultNorm, notExpUnderflow, notExpOverflow, notPossibleOv,
// RCondition);
//
// notRCondition(e)
// Ye Olde Criticale Pathe
//
// ***************************************//
// Sign Case Bits //
// ***************************************//
ME_NMUX2B vbxb (Rom_Sub_Sign_Case,
Rom_Feedback[1],
Cond_SignsDiffer,
notUFeedback[1]);
// *********************************************************//
// Generate Feedback address including CASE logic //
// *********************************************************//
ME_INV_A g0_0 (Rom_Feedback[0], notUFeedback[0]);
ME_INV_A g0_2 (Rom_Feedback[2], notUFeedback[2]);
ME_INV_A g0_3 (Rom_Feedback[3], notUFeedback[3]);
ME_INV_A g0_4 (Rom_Feedback[4], notUFeedback[4]);
// Assign rounding case bits
ME_NMUX2B_B ufb0 (RomRoundCase, notUFeedback[0], notExpOverflow, Feedback[0]);
ME_NMUX2B_B ufb1 (RomRoundCase, notUFeedback[1], notExpUnderflow, Feedback[1]);
ME_NMUX2B_B ufb2 (RomRoundCase, notUFeedback[2], SubResultNorm, Feedback[2]);
ME_NMUX2B_B ufb3 (RomRoundCase, notUFeedback[3], notFracZero, Feedback[3]);
ME_NMUX2B_B ufb4 (RomRoundCase, notUFeedback[4], notPossibleOv, Feedback[4]);
endmodule
|
module CondMux (C,
CS,
notReset,
notAbortNulExc,
DyadicOprExc,
notBrTakenMIS,
notBrTaken);
input [15:0] C;
input [4:0] CS;
input notAbortNulExc,
DyadicOprExc,
notReset;
output notBrTakenMIS;
output notBrTaken;
ME_TIEOFF toff (vdd, gnd);
wire [3:0] T;
wire [4:0] CoS;
ME_INVA h_1 (DyadicOprExc, notDyadicOprExc);
ME_AND3_B h_0 (notAbortNulExc, notReset,
notDyadicOprExc,
notPreventBr);
ME_AND2_B c_0(CS[0], notPreventBr, CoS[0]);
ME_AND2_B c_1(CS[1], notPreventBr, CoS[1]);
ME_AND2 c_2(CS[2], notPreventBr, CoS[2]);
ME_AND2 c_3(CS[3], notPreventBr, CoS[3]);
ME_AND2 c_4(CS[4], notPreventBr, CoS[4]);
// C[15] takes different route
ME_MUX4B vx_3 (CoS[0], CoS[1], C[12],C[13],C[14],gnd, T[3]);
ME_MUX4B vx_2 (CoS[0], CoS[1], C[8],C[9],C[10],C[11], T[2]);
ME_MUX8B vx_0 (CoS[0], CoS[1], CoS[2], C[0],C[1],C[2],C[3],C[4],C[5],C[6],C[7],C0_7);
ME_NMUX2B vc_1 (CoS[3], C0_7, T[3], notC0_11);
ME_XOR2_B vd_0 (notC0_11, CoS[4], notBrTakenNoFrac);
ME_INVA vc_2 (CoS[2], notCoS2);
ME_NAND2 vc_3 (notCoS2, CoS[3], notSelFracConds);
ME_NMUX2B vc_4 (notSelFracConds, T[2], notBrTakenNoFrac,
BrTakenSlowRC);
// Make a special case of RoundingCondition CoS = {1, 1, 1, 1, 1} ie invert not Rounding condition
ME_AND4 sp_0 (CoS[0], CoS[1], CoS[2], CoS[3], RCSelected);
ME_AND2 sp_1 (CoS[4], RCSelected, ControlForRCPos);
ME_NMUX2B_B sp_2 (ControlForRCPos, BrTakenSlowRC, C[15], notBrTaken);
ME_NMUX2B_B sp_3 (ControlForRCPos, BrTakenSlowRC, C[15], notBrTakenMIS);
endmodule
|
module Control (Phi, ResetIn,
notExpAgtB,
notAInfNan, notAZeroDenorm, notBInfNan, notBZeroDenorm,
notExpUnderflow, notExpOverflow, notExpException,
notWaitForShifter, notNO,
SubResultNorm,
notPossibleOv,
Conditionals_14_8, Conditionals_6_0,
FpInst, FpOp, FpLd,
PreventSwap,
PreventSwapExp,
RCondition,
SelectedMIptr,
U_RomOutputs,
RomOutputs,
YDest,
XDest,
CMPDecoded, CMPEDecoded,
AregOprExc,
notAbortWB, Reset,
Busy, NegateOprSign,
UnimpOut );
input Phi, ResetIn;
input notExpAgtB,
notAInfNan, notAZeroDenorm,
notBInfNan, notBZeroDenorm,
notExpUnderflow, notExpOverflow, notExpException,
notWaitForShifter;
input [1:0] notNO;
input SubResultNorm;
input notPossibleOv;
input [14:8] Conditionals_14_8; // Conditional bits (input)
input [ 6:0] Conditionals_6_0; // Conditional bits (input)
input [9:0] FpInst; // FPOP field of instruction
input FpOp, FpLd;
input [`RomWidthM1:0] U_RomOutputs;
output PreventSwap, PreventSwapExp,
RCondition;
output [`MIptrMSB:0] SelectedMIptr;
output [`RomWidthM1:0] RomOutputs;
output [6:0] YDest;
output XDest;
output CMPDecoded, CMPEDecoded;
output AregOprExc,
notAbortWB, Reset,
Busy, NegateOprSign,
UnimpOut;
wire [2:0] ExMIptrLSBs;
wire AregOprExc, RCondition;
wire [15:0] Conditionals;
assign Conditionals = {RCondition, Conditionals_14_8, AregOprExc,
Conditionals_6_0} ;
PreventSwapCtl psc (Conditionals[`u_Cond_FracResultNegative],
notExpAgtB, Conditionals[`u_Cond_ExpResultZero],
RomOutputs[`u_PreventSwapIfBgtA], FpLd,
PreventSwap,
PreventSwapExp);
SampleReset sr (Phi, ResetIn, ResetAbortInst,
ResetImp, Reset, notReset);
NullExcepLogic nel (Phi, notReset,
RomOutputs[`u_NullifyOnBranchOr],
RomOutputs[`u_OprExc],
BTLatched,
notSampledWait,
FpLd,
notAInfNan, notAZeroDenorm,
notBInfNan, notBZeroDenorm,
ExMIptrLSBs,
AregOprExc,
DyadicOprExc,
notAbortNulExc,
notAbortWB);
wire [4:0] Feedback;
CaseGeneration cg (
RomOutputs[`start_fb_field+4:`start_fb_field],
RomOutputs[`start_condition_field+3:`start_condition_field],
SubResultNorm,
Conditionals[`u_Cond_SignsDiffer],
notExpUnderflow, notExpOverflow, notExpException,
notPossibleOv, Conditionals[`u_Cond_notFracResultZero],
RCondition,
Feedback[4:0]);
CondMux cm (Conditionals,
RomOutputs[4+`start_condition_field:`start_condition_field],
notReset,
notAbortNulExc,
DyadicOprExc,
notBranchTakenMIS,
notBranchTaken);
SampledWaitCtl swc (
RomOutputs[`u_ShiftForAlign],
RomOutputs[`u_ShiftForInt],
RomOutputs[`u_LeftnotRight],
notReset,
notAbortNulExc,
notWaitForShifter,
notNO[1:0],
notIdleLatched,
UpdateOutputs,
notSampledWait);
MISelect smi (Phi, notReset,
notBranchTaken,
notDecodedUnimp,
RomOutputs[`u_MIptrFromInstructionN],
RomOutputs[`u_MIptrFromInstructionB],
notAbortInst, notAbortNulExc,
notResetOrUnimp,
DyadicOprExc, notSampledWait,
FpOp,
notSingleCycInst,
BTLatched,
Busy, notIdleLatched,
notInstAndNoExc,
MIptrLoadEnable);
// ***************************************//
// MIptr :- Micro Instruction Pointer //
// ***************************************//
wire [`MIptrMSB:0] RomMIptr, notRomMIptr;
// ***************************************//
// unregistered version of RomMIptr //
// ***************************************//
wire [`MIptrMSB:0] SelectedMIptr;
wire [`RomWidthM1:0] U_RomOutputs; // unbuffered output from ME_UROM
MIptr mip (Phi,
ExMIptrLSBs,
DyadicOprExc,
notInstAndNoExc,
notBranchTakenMIS,
notResetOrUnimp,
MIptrLoadEnable,
{RomOutputs[`end_fb_field:`start_fb_field+5], Feedback[4:0]},
FpInst[7:0],
SelectedMIptr,
RomMIptr,
notRomMIptr);
MicrocodeRom mrom (Phi,
UpdateOutputs,
U_RomOutputs,
RomOutputs,
XDest,
YDest );
EntryCheck ec (notRomMIptr, EntryPoint, notSingleCycInst);
ImplementedCheck ich (Phi, ResetImp, // Can't be Reset
notReset,
FpOp,
EntryPoint, FpInst[9:4],
notDecodedUnimp,
notResetOrUnimp,
notAbortInst, ResetAbortInst,
FPOP2Map,
UnimpOut);
DecodeCmpAndNeg dcs (Phi,
FpInst[2], FpInst[3], FpInst[6], FpInst[7],
FPOP2Map,
CMPDecoded, CMPEDecoded,
NegateOprSign);
endmodule
|
module CregLoadCtl (
// inputs
RomCregCtl,
QuoBits,
notAbortWB,
SNnotDB,
CregSNBits,
// outputs
InForCreg,
InForCregDB,
RomFracBSL2FromC,
FracCregLoadCtl0,
FracCregLoadEn);
input [`end_frac_creg_field:`start_frac_creg_field] RomCregCtl;
input [1:0] QuoBits;
input [1:0] CregSNBits;
input notAbortWB,
SNnotDB;
output [1:0] InForCreg, InForCregDB;
output RomFracBSL2FromC;
output FracCregLoadCtl0,
FracCregLoadEn;
wire [1:0] InForCregSN;
/* *********************************************************
Control Logic For Creg
********************************************************* */
ME_INVA g100 (SNnotDB, DBnotSN);
ME_AND2 fg1s (QuoBits[1], RomCregCtl[`u_FracCregFromFunc0],
InForCregSN[1]);
ME_AND2 fg0s (QuoBits[0], RomCregCtl[`u_FracCregFromFunc0],
InForCregSN[0]);
ME_AND3 fg1d (QuoBits[1], DBnotSN, RomCregCtl[`u_FracCregFromFunc0],
InForCregDB[1]);
ME_AND3 fg0d (QuoBits[0], DBnotSN, RomCregCtl[`u_FracCregFromFunc0],
InForCregDB[0]);
ME_MUX2B fg1 (SNnotDB, CregSNBits[1], InForCregSN[1], InForCreg[1]);
ME_MUX2B fg0 (SNnotDB, CregSNBits[0], InForCregSN[0], InForCreg[0]);
ME_INVA fg9s (RomCregCtl[`u_FracCregFromFunc0], notResultOrQuoBits);
ME_AND2 icr9 (RomCregCtl[`u_FracCregFromFunc1], notResultOrQuoBits,
RomFracBSL2FromC); // 1 0 ie SQRT
ME_INVA fgg (notAbortWB, AbortWB);
ME_NOR2 icr (RomCregCtl[`u_FracCregFromFunc0],
RomCregCtl[`u_FracCregFromFunc1],
notEn);
ME_NOR2 rct (notEn,
AbortWB,
FracCregLoadEn);
/* Feedthroughs */
ME_BUFF g00 (RomCregCtl[`u_FracCregFromFunc1], FracCregLoadCtl0);
endmodule
|
module DecodeCmpAndNeg (
Phi,
FpInst2, FpInst3, FpInst6, FpInst7,
FPOP2Map,
CMPDecoded, CMPEDecoded, NegateOprSign);
input Phi,
FpInst2, FpInst3, FpInst6, FpInst7, FPOP2Map;
output CMPDecoded, CMPEDecoded;
output NegateOprSign;
ME_INVA dcep1 (FpInst2, notFpInst2);
ME_NAND2 dcep2 (FPOP2Map, notFpInst2, notCMP);
ME_NAND2 dcep3 (FPOP2Map, FpInst2, notCMPE);
ME_FD1 dcep4 (Phi, notCMP, , CMPDecoded);
ME_FD1 dcep5 (Phi, notCMPE, , CMPEDecoded);
ME_INVA dcep9 (FpInst3, notFpInst3);
ME_INVA dcep6 (FpInst7, notFpInst7);
ME_AND4 dcep7 (FpInst6, notFpInst7, FpInst2, notFpInst3, DyadicSub);
ME_NOR2 decep8 (FPOP2Map, DyadicSub, s_0);
ME_FD1 iggypop (Phi, s_0, , NegateOprSign);
endmodule
|
module DecodeStatus (RomCtl[3:0], StatusControl[6:0]);
input [3:0] RomCtl;
output [6:0] StatusControl;
// A-L are ouputs required // Recoded into patterns
// A 010_0000 // 1101
// B 110_0000 // 1111
// C 000_0100 // 1100
// D 100_0000 // 1110
// E 000_1000 // 1011
// F 100_1000 // 1010
// G 001_0000 // 1001
// H 101_0000 // 1000
// I 010_0011 // 0111
// J 000_0011 // 0110
// K 000_0010 // 0100
// L 000_0000 // 0000
ME_INV_A i0 (RomCtl[3], notRomCtl3);
ME_INV_A i1 (RomCtl[2], notRomCtl2);
ME_INV_A i2 (RomCtl[1], notRomCtl1);
ME_INV_A i3 (RomCtl[0], notRomCtl0);
ME_AND3 b0 (notRomCtl3, RomCtl[2], RomCtl[1], StatusControl[0]);
ME_AND2 b1 (notRomCtl3, RomCtl[2], StatusControl[1]);
ME_AND4 b2 (RomCtl[3], RomCtl[2], notRomCtl1, notRomCtl0, StatusControl[2]);
ME_AND3 b3 (RomCtl[3], notRomCtl2, RomCtl[1], StatusControl[3]);
ME_AND3 b4 (RomCtl[3], notRomCtl2, notRomCtl1, StatusControl[4]);
ME_NAND4 p0 (notRomCtl3, RomCtl[2], RomCtl[1], RomCtl[0], t0);
ME_NAND3 p1 (RomCtl[3], RomCtl[2], RomCtl[0], t1);
ME_NAND2 b5 (t0, t1, StatusControl[5]);
ME_NAND3 p2 (RomCtl[3], RomCtl[2], RomCtl[1], t2);
ME_NAND3 p3 (RomCtl[3], notRomCtl2, notRomCtl0, t3);
ME_NAND2 b6 (t2, t3, StatusControl[6]);
endmodule
|
module DivLog (Phi,
AregFPMSBM1, // Divisor Bit
BregFPMSBM1, // On first step divisor is in B
StepRemBits, // RemBits used during step
InitialRemBits, // RemBits used on first step
SelectInitial, // Select First step
FracSign, // Sign of result after operation
DivMultiple, // Latched version of Divide Step Multiple
QuotientBits); // Quotient bits, valid on cycle after
// operation
// notFracSign); // inv FracSign -- generate inside fdp (dhn 03/27/91)
input Phi; // System Clock
input AregFPMSBM1, BregFPMSBM1, FracSign;
input [3:0] StepRemBits, InitialRemBits;
input SelectInitial;
output [3:1] DivMultiple;
output [1:0] QuotientBits;
// output notFracSign; // -- generate inside fdp (dhn 03/27/91)
// ME_INVA ifs (FracSign, notFracSign); // --generate inside fdp (dhn 03/27/91)
wire [3:1] notDivMultiple, DivMultipleU;
wire [3:0] notRemBits;
wire [3:0] RemBits;
ME_NMUX2B msld (SelectInitial, AregFPMSBM1, BregFPMSBM1, notDivisorBit);
ME_NMUX2B msl0 (SelectInitial, StepRemBits[0], InitialRemBits[0], notRemBits[0]);
ME_NMUX2B msl1 (SelectInitial, StepRemBits[1], InitialRemBits[1], notRemBits[1]);
ME_NMUX2B msl2 (SelectInitial, StepRemBits[2], InitialRemBits[2], notRemBits[2]);
ME_NMUX2B msl3 (SelectInitial, StepRemBits[3], InitialRemBits[3], notRemBits[3]);
ME_INV_B ir3 (notRemBits[3], RemBits[3]);
ME_INV_B ir2 (notRemBits[2], RemBits[2]);
ME_INV_B ir1 (notRemBits[1], RemBits[1]);
ME_INV_B ir0 (notRemBits[0], RemBits[0]);
ME_INV_B id0 (notDivisorBit, DivisorBit);
// DivMultiple [1] = ~RemBit[3].~RemBit[2].~RemBit[1].RemBit[0] +
// RemBit[3].RemBit[2].RemBit[1].~RemBit[0];
ME_NAND4 ds10 (notRemBits[3], notRemBits[2], notRemBits[1], RemBits[0], dm1t0);
ME_NAND4 ds11 (RemBits[3], RemBits[2], RemBits[1], notRemBits[0], dm1t1);
ME_NAND2 ds1m (dm1t1, dm1t0, DivMultipleU[1]);
// DivMultiple [2] = ~RemBit[3].~RemBit[2].RemBit[1].~RemBit[0] +
// ~RemBit[3].~RemBit[2].RemBit[1].DivisorBit +
// RemBit[3]. RemBit[2].~RemBit[1].RemBit[0] +
// RemBit[3]. RemBit[2].~RemBit[1].DivisorBit;
ME_NAND4 ds20 (notRemBits[3], notRemBits[2], RemBits[1], notRemBits[0], dm2t0);
ME_NAND4 ds21 (notRemBits[3], notRemBits[2], RemBits[1], DivisorBit, dm2t1);
ME_NAND4 ds22 (RemBits[3], RemBits[2], notRemBits[1], RemBits[0], dm2t2);
ME_NAND4 ds23 (RemBits[3], RemBits[2], notRemBits[1], DivisorBit, dm2t3);
ME_NAND4 ds2m (dm2t1, dm2t0, dm2t2, dm2t3, DivMultipleU[2]);
// DivMultiple [3] = ~RemBit[3]. RemBit[2] +
// ~RemBit[2]. RemBit[1]. RemBit[0].~DivisorBit +
// RemBit[3].~RemBit[2] +
// RemBit[2].~RemBit[1].~RemBit[0].~DivisorBit;
ME_NAND2 ds30 (notRemBits[3], RemBits[2], dm3t0);
ME_NAND4 ds31 (notRemBits[2], RemBits[1], RemBits[0], notDivisorBit, dm3t1);
ME_NAND2 ds32 (RemBits[3], notRemBits[2], dm3t2);
ME_NAND4 ds33 (RemBits[2], notRemBits[1], notRemBits[0], notDivisorBit, dm3t3);
ME_NAND4 ds3m (dm3t1, dm3t0, dm3t2, dm3t3, DivMultipleU[3]);
/* ************************************************
Latch next Div Multiple
************************************************ */
ME_FD1_B dv1 (Phi, DivMultipleU[1], DivMultiple[1], notDivMultiple[1]);
ME_FD1_B dv2 (Phi, DivMultipleU[2], DivMultiple[2], notDivMultiple[2]);
ME_FD1_B dv3 (Phi, DivMultipleU[3], DivMultiple[3], notDivMultiple[3]);
ME_FD1_B dv0 (Phi, notRemBits[3], notOldSign, OldSign);
/* ************************************************
Quotient bit generation
End of Result QuoBit Generation calculation
************************************************ */
/* Not time critical so use buffered DivMultiple */
/* Also use the encoded version of DivMultiple ie DivMultipleC */
wire [1:0] DivMultipleC, notDivMultipleC;
ME_NAND2 dedv0 (notDivMultiple[1], notDivMultiple[3], DivMultipleC[0]);
ME_NAND2 dedv1 (notDivMultiple[2], notDivMultiple[3], DivMultipleC[1]);
ME_INV_A dmb0 (DivMultipleC[0], notDivMultipleC[0]);
ME_INV_A dmb1 (DivMultipleC[1], notDivMultipleC[1]);
// QuotientBit0[1] = OldSign.DivMultiple[1].~DivMultiple[0] +
// OldSign.~DivMultiple[1] +
// ~OldSign.DivMultiple[1];
// QuotientBit1[1] = OldSign.~DivMultiple[1] +
// ~OldSign.DivMultiple[1].DivMultiple[0];
// QuotientBit0[0] = DivMultiple[0];
// QuotientBit1[0] = ~DivMultiple[0];
ME_NAND3 qb1t0 (OldSign, DivMultipleC[1], notDivMultipleC[0], t0);
ME_NAND2 qb1t1 (OldSign, notDivMultipleC[1], t1);
ME_NAND2 qb1t2 (notOldSign, DivMultipleC[1], t2);
ME_NAND3 qb1t3 (t0, t1, t2, t3);
ME_NAND3 qb1t4 (notOldSign, DivMultipleC[1], DivMultipleC[0], t4);
ME_NAND2 qb1t5 (t4, t1, t5);
ME_MUX2B qb1m (FracSign, t3, t5, QuotientBits[1]);
ME_NMUX2B qb0m (FracSign, notDivMultipleC[0], DivMultipleC[0], QuotientBits[0]);
endmodule
|
module EntryCheck (notRomMIptr, EntryPoint, s_mov);
input [7:0] notRomMIptr;
output EntryPoint, s_mov;
wire [7:0] RomMIptr;
ME_INV_B i_0 (notRomMIptr[0], RomMIptr[0]);
ME_INV_B i_1 (notRomMIptr[1], RomMIptr[1]);
ME_INV_B i_2 (notRomMIptr[2], RomMIptr[2]);
ME_INV_B i_3 (notRomMIptr[3], RomMIptr[3]);
ME_INV_B i_4 (notRomMIptr[4], RomMIptr[4]);
ME_INV_B i_5 (notRomMIptr[5], RomMIptr[5]);
ME_INV_B i_6 (notRomMIptr[6], RomMIptr[6]);
ME_INV_B i_7 (notRomMIptr[7], RomMIptr[7]);
ME_NOR3 g_1 (RomMIptr[7], RomMIptr[1], RomMIptr[0], s_0);
ME_NOR2 g_2 (RomMIptr[4], RomMIptr[3], s_1);
ME_NAND2 g_3 (RomMIptr[6], RomMIptr[2], s_2);
ME_NAND4 g_4 (RomMIptr[5], s_0, s_1, s_2, s_mov);
ME_XOR2 g_5 (RomMIptr[4], RomMIptr[5], s_3);
ME_NAND3 g_6 (RomMIptr[3], s_0, s_3, s_dyadic);
ME_NOR4 g_7 (RomMIptr[7], RomMIptr[3], RomMIptr[2], RomMIptr[1], s_4);
ME_AND2 g_8 (RomMIptr[6], RomMIptr[0], s_5);
ME_NAND3 g_9 (s_4, s_5, s_3, s_sqrt);
ME_NOR3 g_0 (RomMIptr[7], RomMIptr[6], RomMIptr[0], s_6);
ME_AND2 h_1 (RomMIptr[3], RomMIptr[1], s_7);
ME_NAND3 h_2 (s_6, s_7, s_3, s_cmp);
ME_NOR3 h_3 (RomMIptr[6], RomMIptr[5], RomMIptr[1], s_8);
ME_NAND2 h_4 (s_8, RomMIptr[2], s_9);
ME_NOR3 h_5 (RomMIptr[4], RomMIptr[2], RomMIptr[1], s_10);
ME_NAND2 h_6 (s_10, RomMIptr[6], s_11);
ME_NOR2 h_7 (RomMIptr[6], RomMIptr[2], s_12);
ME_NAND3 h_8 (s_12, s_3, RomMIptr[1], s_13);
ME_NAND3 h_9 (s_13, s_11, s_9, s_14);
//ME_INVA h_0 (RomMIptr[0], s_15);
ME_NAND4 j_1 (notRomMIptr[0], s_14, RomMIptr[3], RomMIptr[7], s_conv);
ME_AND4 j_2 (s_mov, s_dyadic, s_sqrt, s_cmp, s_16);
ME_NAND2 j_3 (s_conv, s_16, EntryPoint);
endmodule
|
module exp_ctl ( Phi, DBnotSN, FracAregMSB1, LoadOprs, notAbortWB, PreventSwap,
ShiftBy8, ShiftForAl, SNnotDB, notExpShiftResult, Rom_28_27,
Rom_38_33,
CarryIn, Constantb, Constantc, Constantd, Constante,
Constantf, Constantg, Constanth, ExpAregLoadEn, ExpAregLC0,
ExpAregLC1, ExpBregLC0, ExpBregLC1, ExpBregLoadEn,
notSignAFromB, notSignBFromA, notWaitForShifter, SROneMore,
SRToSticky, SRControl );
input Phi, DBnotSN, FracAregMSB1, LoadOprs, notAbortWB, PreventSwap,
ShiftBy8, ShiftForAl, SNnotDB ;
input [12:0] notExpShiftResult ;
input [28:27] Rom_28_27 ;
input [38:33] Rom_38_33 ;
output CarryIn, Constantb, Constantc, Constantd, Constante, Constantf,
Constantg, Constanth, ExpAregLoadEn, ExpAregLC0, ExpAregLC1,
ExpBregLC0, ExpBregLC1, ExpBregLoadEn, notSignAFromB, notSignBFromA,
notWaitForShifter, SROneMore, SRToSticky ;
output [3:0] SRControl ;
ExpAdderLSB alsb ( .CinFromRound(Rom_28_27[28] ), .Sub(Rom_28_27[27] ),
.FracAregMSB1(FracAregMSB1), .CarryIn(CarryIn) );
ExpConstantCtl ecs ( .SNnotDB(SNnotDB), .DBnotSN(DBnotSN), .RomExpConCtl(
Rom_38_33[34:33] ), .Constantb(Constantb), .Constantc(Constantc),
.Constantd(Constantd), .Constante(Constante), .Constantf(Constantf),
.Constantg(Constantg), .Constanth(Constanth) );
ExpRegLoadCtl alc ( .RomExpBregLC( Rom_38_33[36:35] ), .LoadOprs(LoadOprs),
.notAbortWB(notAbortWB), .PreventSwap(PreventSwap),
.notSignBFromA(notSignAFromB), .ExpBregLC0(ExpAregLC0),
.ExpBregLC1(ExpAregLC1), .ExpBregLoadEn(ExpAregLoadEn) );
ExpRegLoadCtl blc ( .RomExpBregLC(Rom_38_33[38:37]), .LoadOprs(LoadOprs),
.notAbortWB(notAbortWB), .PreventSwap(PreventSwap), .notSignBFromA(
notSignBFromA), .ExpBregLC0(ExpBregLC0), .ExpBregLC1(ExpBregLC1),
.ExpBregLoadEn(ExpBregLoadEn) );
ExpShifter sr ( .Phi(Phi), .notExpResult(notExpShiftResult), .Rom_ShBy8(
ShiftBy8), .Rom_ShiftForAl(ShiftForAl), .SRControl(SRControl),
.SROneMore(SROneMore), .SRToSticky(SRToSticky), .notWaitForShifter(
notWaitForShifter) );
endmodule
|
module ExpAdderLSB (CinFromRound, Sub, FracAregMSB1,
CarryIn);
input CinFromRound, // rom control to set carry from Areg MSB
Sub, // rom control Subtract not add
FracAregMSB1;
output CarryIn;
/* Notes
// always subtracting when notCarrryInfromNorm is used
// always adding when CinFrom Round is used
// Carry is equivalent to notBorrow for this adder.*/
ME_MUX2B g12 ( CinFromRound, Sub, FracAregMSB1,
CarryIn);
endmodule
|
module ExpConstantCtl (SNnotDB, DBnotSN,
RomExpConCtl,
Constantb, Constantc, Constantd, Constante,
Constantf, Constantg, Constanth);
input SNnotDB, DBnotSN ;
input [`end_constant_field:`start_constant_field] RomExpConCtl;
output Constantb, Constantc, Constantd, Constante,
Constantf, Constantg, Constanth;
/* ************************************************************
Length Dependant Constant Selection
************************************************************
a b c d e f g h ROMbit f1 f0 SNnotBD
DivLoopSN 0|00 00|0 00 0 | 0 1 1 0 0 1 1
DivLoopDB 0|00 00|0 00 0 | 1 1 0 1 0 1 0
BiasSN 0|00 00|0 11 1 | 1 1 1 1 1 1 1
BiasDB 0|00 11|1 11 1 | 1 1 1 1 1 1 0
1 0|00 00|0 00 0 | 0 0 0 1 0 0 ?
IntToReal 0|00 00|0 00 1 | 1 1 1 1 1 0 ?
Constantb = Func1 & Func0 & DB;
Constantc = Func1 & Func0;
Constantd = Func1;
Constante = Func1 | (Func0 & DBnotSN);
Constantf = Func1 | Func0;
Constantg = Func1 | ~Constanth;
Constanth = ~(~Func1 & Func0 & SNnotDB); */
//ME_INVA z90 (SNnotDB, DBnotSN );
ME_AND3_B z00 (RomExpConCtl[`u_ConstantFromFunc1],
RomExpConCtl[`u_ConstantFromFunc0],
DBnotSN, Constantb);
ME_AND2_B z01 (RomExpConCtl[`u_ConstantFromFunc1],
RomExpConCtl[`u_ConstantFromFunc0],
Constantc);
ME_AND2_B z02 (RomExpConCtl[`u_ConstantFromFunc0], DBnotSN, Func0andDB);
ME_OR2_B z03 (RomExpConCtl[`u_ConstantFromFunc1], Func0andDB, Constante);
ME_OR2_B z04 (RomExpConCtl[`u_ConstantFromFunc1],
RomExpConCtl[`u_ConstantFromFunc0],
Constantf);
ME_INVA z05 (RomExpConCtl[`u_ConstantFromFunc1], notFunc1);
ME_NAND2_B z07 (notFunc1, Constanth, Constantg);
ME_NAND3_B z06 (notFunc1, RomExpConCtl[`u_ConstantFromFunc0], SNnotDB, Constanth);
//wire Constantd = RomExpConCtl[`u_ConstantFromFunc1];
con1 ep (RomExpConCtl[`u_ConstantFromFunc1], Constantd);
endmodule
|
module ExpRegLoadCtl (RomExpBregLC,
LoadOprs,
notAbortWB,
PreventSwap,
notSignBFromA,
ExpBregLC0,
ExpBregLC1,
ExpBregLoadEn);
input [`u_ExpBregFromFunc1:`u_ExpBregFromFunc0] RomExpBregLC;
input notAbortWB,
PreventSwap,
LoadOprs;
output notSignBFromA;
output ExpBregLC0,
ExpBregLC1,
ExpBregLoadEn;
ME_TIEOFF toff (vdd, );
ME_INVA iopl (LoadOprs, notLoadOprs);
ME_AND2 alcn1 (RomExpBregLC[`u_ExpBregFromFunc1], notLoadOprs, ExpBregLC1);
ME_AND2 alcn2 (RomExpBregLC[`u_ExpBregFromFunc0], notLoadOprs, ExpBregLC0);
ME_OR3 alcne (RomExpBregLC[`u_ExpBregFromFunc0],
RomExpBregLC[`u_ExpBregFromFunc1],
LoadOprs,
LoadEn);
ME_NAND2 alc4 (RomExpBregLC[`u_ExpBregFromFunc0],
RomExpBregLC[`u_ExpBregFromFunc1],
notSignBFromA);
//ME_AND3 en (LoadEn, notAbortWB, notPreventSwap, ExpBregLoadEn);
ME_NAND2 en0 (LoadEn, notAbortWB, notExpBregLoadEn_p);
ME_NMUX2B en1 (notExpBregLoadEn_p, PreventSwap, vdd, ExpBregLoadEn);
endmodule
|
module ShiftDec ( Phi, FS, notFS, Res,
notShiftCount1 );
input Phi, FS, notFS;
input[1:0] Res;
output notShiftCount1 ;
// shift count decrementer.
// Load counter from Res on FS
// decrement works either loading or counting
wire [1:0] notSC, ShCnt, notShCnt ;
ME_NMUX2BA mu1 (FS, notFS, Res[1], ShCnt[0], notSC[1]);
ME_NMUX2BA mu0 (FS, notFS, Res[0], notShCnt[0], notSC[0]);
ME_FD1 ma1 (Phi, notSC[1], notShCnt[1], ShCnt[1]);
ME_FD1 ma0 (Phi, notSC[0], notShCnt[0], ShCnt[0]);
ME_NAND3 g20 (notFS, notShCnt[1], ShCnt[0], notShiftCount1 );
endmodule
|
module ExpShifter ( Phi,
notExpResult,
Rom_ShBy8,
Rom_ShiftForAl,
SRControl,
SROneMore,
SRToSticky,
notWaitForShifter);
input Phi; // master clock
input [12:0] notExpResult; // fraction add result only use 5:0
input Rom_ShBy8, // for either int or mul
Rom_ShiftForAl; // alignment
output [3:0] SRControl; // Shift right size ( 0 to 15 )
// Delay for this is
// MUX2B
output SROneMore, // extra one to give shift of 16
SRToSticky; // Massive shift reduce to sticky
output notWaitForShifter; // Need to generate this quickly
// delay is NOR4, NAND3, AND4
// Dont care unless ShiftforAl asserted
ME_TIEOFF toff (,gnd);
// generate correct shift right value. This may be either forced to 8
// for mul or INT stuff, or 0 to 16 for first step of align, or
// further shifts by 16 if required
// Generate wait if additional shift is required
// Note shift by 16 is a delayed shift wait except on first shift
// SRToSticky Being asserted means the rest of the shifter doesnt
// matter. Note since in the shifter the sticky is set to one this
// must NOT be applied to zero fraction parts.
// Wait is only valid while Rom_ShiftforAl is asserted
ME_NAND3 g12 ( notExpResult[5], notExpResult[4], FS, notSmallShift );
ME_NAND6_B gxz ( notExpResult[11], notExpResult[10], notExpResult[9], notExpResult[8], notExpResult[7], notExpResult[6], BigShift);
ME_NMUX2B_B sm4 ( FS, gnd, BigShift, notSRToSticky);
ME_INV_B g19 ( notSRToSticky, SRToSticky );
// Can align in 1 for BigShift or small shift 00xxxx or exact 010000
ME_AND2 gr5 ( notSmallShift, notShiftCount1, bozoid );
ME_NAND2 g15 ( notSRToSticky, bozoid, notWaitForShifter );
// note shift by 8 is dominant so dont worry about FS on shift by 8
ME_FD1 err ( Phi, Rom_ShiftForAl, , notPrevShift);
ME_NAND2 g32 ( Rom_ShiftForAl, notPrevShift, notFS );
ME_INVA g33 ( notFS, FS );
wire [5:4] ExpResult;
// Decrement on notFS, OR ShBy16first
ME_INV_A g16 ( notExpResult[5], ExpResult[5] );
ME_INV_A g17 ( notExpResult[4], ExpResult[4] );
ShiftDec d ( Phi, FS, notFS, ExpResult[5:4], notShiftCount1 );
// Set correct shift value
ME_NOR2 sby8 (Rom_ShBy8, Rom_ShiftForAl, notShiftBy8);
ME_INV_A sbfa (Rom_ShiftForAl, notRom_ShiftForAl);
ME_NMUX2B_B sm3 (FS, notShiftBy8, notExpResult[3], SRControl[3]);
ME_NMUX2B_B sm2 (FS, notRom_ShiftForAl, notExpResult[2], SRControl[2]);
ME_NMUX2B_B sm1 (FS, notRom_ShiftForAl, notExpResult[1], SRControl[1]);
ME_NMUX2B_B sm0 (FS, notRom_ShiftForAl, notExpResult[0], SRControl[0]);
ME_AND2_B a90 (Rom_ShiftForAl, notFS, SROneMore);
endmodule
|
module fp_ctl ( ss_clock, AregMaster_32, BregFPMSBM1, CALSB, CBLSB, CCLSB,
Conditionals_3, Conditionals_10, Conditionals_12,
FpLd, FpOp, FracAgtB, FracBregSign, FracZero,
notAInfNAN, notAM31_3, notAM2_0, notAregMasterFPMSBP1, notAZeroDenorm,
notBInfNAN, notBZeroDenorm, notExpUnderflow, notExpOverflow,
notExpException, notPossibleOv, notFracZero, notSticky1, ResetIn,
RS2_63, RS1_63, StickyForSR1, SubResultNorm, AregMaster_57_40,
AregMaster_7_0, CarryInLSBs, CregInSL2SQRT, CregSNBits, ExpIn,
FpInst, notExpShiftResult, notMultip, notSticky4, RoundingMode,
SALSBs, SBLSBs, SCLSBs, StepRemBits, Sticky2, StickyExtra, SumInLSBs,
TregLSBs, U_RomOutputs,
CarryIn, CarryOut0, CarryOut3, Constantb, Constantc, Constantd,
Constante, Constantf, Constantg, Constanth, ExpAregLC0, ExpAregLC1,
ExpAregLoadEn, ExpBregLC0, ExpBregLC1, ExpBregLoadEn, FracAregLoadEn,
FracBregLoadEn, FracCregLC, FracCregLoadEn, FracTregLoadEn, FpBusy,
InitialCarryBit, InitialMulStep, notFracYFromD1A, notFracYFromD2A,
notFracYFromD3A, notNO_1, notStickyInForSR, OprSNnotDB, RomOutputs_18,
RomOutputs_20, RomOutputs_27, RomOutputs_55, SignResult, SNnotDB,
SROneMore, SRToSticky, SumCarryLoadEn, SumOut0, ConditionCodes, Excep,
FracAregLC, FracBregLC, FracRound, FracYbusLSBs, InForCreg,
InForCregDB, InFromCregOr0, LIB, MulLenSel, notsh, Pos,
RomOutputs_32_29, RomOutputs_46_44, SelectedMIptr, Shift, SRControl,
TopBitsIn, Zero,
ss_scan_mode, fp_ctl_scan_in, fp_ctl_scan_out);
input ss_clock, AregMaster_32, BregFPMSBM1, CALSB, CBLSB, CCLSB,
Conditionals_3, Conditionals_10, Conditionals_12,
FpLd, FpOp, FracAgtB, FracBregSign, FracZero,
notAInfNAN, notAM31_3, notAM2_0, notAregMasterFPMSBP1, notAZeroDenorm,
notBInfNAN, notBZeroDenorm, notExpUnderflow, notExpOverflow,
notExpException, notPossibleOv, notFracZero, notSticky1, ResetIn,
RS2_63, RS1_63, StickyForSR1, SubResultNorm,
ss_scan_mode, fp_ctl_scan_in ;
input [57:40] AregMaster_57_40 ;
input [7:0] AregMaster_7_0 ;
input [2:0] CarryInLSBs ;
input [1:0] CregInSL2SQRT ;
input [1:0] CregSNBits ;
input [7:0] ExpIn ;
input [9:0] FpInst ;
input [12:0] notExpShiftResult ;
input [8:0] notMultip ;
input [3:0] notSticky4 ;
input [1:0] RoundingMode ;
input [1:0] SALSBs ;
input [1:0] SBLSBs ;
input [1:0] SCLSBs ;
input [3:0] StepRemBits ;
input [1:0] Sticky2 ;
input [1:0] StickyExtra ;
input [2:0] SumInLSBs ;
input [1:0] TregLSBs ;
input [63:0] U_RomOutputs ; // unbuffered ROM data output
output CarryIn, CarryOut0, CarryOut3, Constantb, Constantc, Constantd,
Constante, Constantf, Constantg, Constanth, ExpAregLC0, ExpAregLC1,
ExpAregLoadEn, ExpBregLC0, ExpBregLC1, ExpBregLoadEn, FracAregLoadEn,
FracBregLoadEn, FracCregLC, FracCregLoadEn, FracTregLoadEn, FpBusy,
InitialCarryBit, InitialMulStep, notFracYFromD1A, notFracYFromD2A,
notFracYFromD3A, notNO_1, notStickyInForSR, OprSNnotDB, RomOutputs_18,
RomOutputs_20, RomOutputs_27, RomOutputs_55, SignResult, SNnotDB,
SROneMore, SRToSticky, SumCarryLoadEn, SumOut0,
fp_ctl_scan_out ;
output [1:0] ConditionCodes;
output [5:0] Excep ;
output [2:0] FracAregLC ;
output [2:0] FracBregLC ;
output [4:0] FracRound ;
output [1:0] FracYbusLSBs ;
output [1:0] InForCreg ;
output [1:0] InForCregDB ;
output [1:0] InFromCregOr0 ;
output [2:0] LIB ;
output [4:0] MulLenSel ;
output [3:1] notsh ;
output [3:0] Pos ;
output [32:29] RomOutputs_32_29 ;
output [46:44] RomOutputs_46_44 ;
output [7:0] SelectedMIptr ; // unregistered ROM address
output [3:0] Shift ;
output [3:0] SRControl ;
output [8:0] TopBitsIn ;
output [3:0] Zero ;
wire notWaitForShifter, SignAreg, PreventSwap, PreventSwapExp, XDest,
CMPDecoded, CMPEDecoded, notAbortWB, NegateOprSign, Unimplemented,
Status_6, notSignAFromB, notSignBFromA, DBnotSN,
Conditionals_2, Conditionals_6, Conditionals_7, Conditionals_15 ;
wire [6:0] YDest ;
wire [1:0] notNO ;
wire [63:0] RomOutputs ;
assign notNO_1 = notNO[1] ;
assign RomOutputs_18 = RomOutputs[18] ;
assign RomOutputs_20 = RomOutputs[20] ;
assign RomOutputs_27 = RomOutputs[27] ;
assign RomOutputs_55 = RomOutputs[55] ;
assign RomOutputs_32_29 = RomOutputs[32:29] ;
assign RomOutputs_46_44 = RomOutputs[46:44] ;
ME_TIEOFF toff (vdd, gnd);
Control cl ( .Phi (ss_clock ), .ResetIn (ResetIn ),
.notExpAgtB (notExpShiftResult[12] ),
.notAInfNan (notAInfNAN ), .notAZeroDenorm (notAZeroDenorm ),
.notBInfNan (notBInfNAN ), .notBZeroDenorm (notBZeroDenorm ),
.notExpUnderflow (notExpUnderflow ), .notExpOverflow (notExpOverflow ),
.notExpException (notExpException ),
.notWaitForShifter (notWaitForShifter ), .notNO (notNO ),
.SubResultNorm (SubResultNorm ), .notPossibleOv (notPossibleOv ),
.Conditionals_14_8 ({vdd, AregMaster_57_40[54], Conditionals_12,
FracAgtB, Conditionals_10, FracZero, notFracZero }),
.Conditionals_6_0 ( {Conditionals_6, SignAreg, ExpIn[0],
Conditionals_3, Conditionals_2 , SNnotDB, gnd} ),
.FpInst (FpInst ), .FpOp (FpOp ), .FpLd (FpLd ),
.PreventSwap (PreventSwap ), .PreventSwapExp (PreventSwapExp ),
.RCondition (Conditionals_15 ),
.SelectedMIptr (SelectedMIptr ),
.U_RomOutputs (U_RomOutputs ),
.RomOutputs (RomOutputs[63:0] ),
.YDest (YDest[6:0] ), .XDest (XDest ), .CMPDecoded (CMPDecoded ),
.CMPEDecoded (CMPEDecoded ), .AregOprExc (Conditionals_7 ),
.notAbortWB (notAbortWB ),
.Reset (Reset ), .Busy (FpBusy ), .NegateOprSign (NegateOprSign ),
.UnimpOut (Unimplemented ) );
frac_ctl fracctl ( .Phi(ss_clock), .AregMaster_32 (AregMaster_32 ),
.BregFPMSBM1 (BregFPMSBM1 ), .CALSB (CALSB), .CBLSB (CBLSB ),
.CCLSB (CCLSB ), .FracBregSign (FracBregSign ), .FracSign (FracAgtB ),
.LoadForInt (RomOutputs[19] ), .LoadOprs (FpLd ),
.notAbortWB (notAbortWB ), .notAM31_3 (notAM31_3 ),
.notAM2_0 (notAM2_0), .notAregMasterFPMSBP1 (notAregMasterFPMSBP1 ),
.notSticky1 (notSticky1), .PreventSwap (PreventSwap ),
.Rom_Inexact (Status_6 ), .RomShForAlign (RomOutputs[21] ),
.SNnotDB(SNnotDB), .SROneMore (SROneMore), .SRToSticky (SRToSticky ),
.StickyForSR1 (StickyForSR1),
.AregMaster_57_40 ( AregMaster_57_40[57:40] ),
.AregMaster_7_0 (AregMaster_7_0[7:0] ),
.CarryInLSBs (CarryInLSBs ), .CregInSL2SQRT ( CregInSL2SQRT ),
.CregSNBits (CregSNBits ), .ExpIn ({SignAreg, ExpIn}),
.notMultip (notMultip ), .notSticky4 (notSticky4 ),
.Rom_63_48 (RomOutputs[63:48] ), .SALSBs (SALSBs ), .SBLSBs (SBLSBs ),
.SCLSBs (SCLSBs ), .SRControl (SRControl ), .StepRemBits (StepRemBits),
.Sticky2 (Sticky2 ), .StickyExtra (StickyExtra ),
.SumInLSBs (SumInLSBs ), .TregLSBs (TregLSBs ), .YDest (YDest[6:0] ),
.CarryOut0 (CarryOut0 ), .CarryOut3 (CarryOut3 ),
.FracAregLoadEn (FracAregLoadEn ), .FracBregLoadEn (FracBregLoadEn ),
.FracCregLoadEn (FracCregLoadEn ), .FracCregLC (FracCregLC ),
.FracTregLoadEn (FracTregLoadEn ), .Inexact (Excep[0] ),
.InitialCarryBit (InitialCarryBit ), .InitialMulStep (InitialMulStep ),
.notFracYFromD1A (notFracYFromD1A ),
.notFracYFromD2A (notFracYFromD2A ),
.notFracYFromD3A (notFracYFromD3A ),
.notStickyInForSR (notStickyInForSR ),
.SumCarryLoadEn (SumCarryLoadEn ), .SumOut0 (SumOut0 ),
.FracAregLC (FracAregLC ), .FracBregLC (FracBregLC ),
.FracYbusLSBs (FracYbusLSBs ), .InForCreg (InForCreg ),
.InForCregDB (InForCregDB ), .InFromCregOr0 (InFromCregOr0 ),
.LIB ( LIB ), .notNO (notNO ), .notsh (notsh ), .Pos (Pos ),
.Shift (Shift ), .TopBitsIn (TopBitsIn ), .Zero (Zero ) );
SignDp sdp ( .Phi (ss_clock ), .Reset (Reset ),
.RomSignLength ( RomOutputs[43:39] ),
.RomStatus ( RomOutputs[26:22] ), .FracXFromRound (RomOutputs[47] ),
.XDest (XDest ), .CMPDecoded (CMPDecoded ),
.CMPEDecoded (CMPEDecoded ), .SignOpA (RS2_63 ), .SignOpB (RS1_63 ),
.notAbortWB (notAbortWB ), .PreventSwap (PreventSwap ), .FpLd (FpLd ),
.FpOp (FpOp ), .NegateOprSign (NegateOprSign ),
.notSignAFromB (notSignAFromB ), .notSignBFromA (notSignBFromA ),
.OprRoundMode (RoundingMode ), .FpInst1 ( FpInst[1] ),
.Unimplemented (Unimplemented ), .SignResult (SignResult ),
.AregSign (SignAreg ), .AregXORBreg (Conditionals_2 ),
.FpExc_Unimp (Excep[5] ), .Status_6_2 ({Status_6 , Excep[4:1] }),
.ConditionCodes (ConditionCodes ), .OprSNnotDB (OprSNnotDB ),
.SNnotDB (SNnotDB ), .DBnotSN (DBnotSN ), .MulLenSel (MulLenSel ),
.RModeMinus (Conditionals_6 ), .FracRoundOut (FracRound ) );
exp_ctl expctl ( .Phi (ss_clock), .DBnotSN (DBnotSN),
.FracAregMSB1 (AregMaster_57_40[56] ), .LoadOprs (FpLd),
.notAbortWB (notAbortWB ), .PreventSwap (PreventSwapExp ),
.ShiftBy8 (RomOutputs[20] ), .ShiftForAl (RomOutputs[21] ),
.SNnotDB (SNnotDB ), .notExpShiftResult (notExpShiftResult ),
.Rom_28_27 (RomOutputs[28:27] ), .Rom_38_33 (RomOutputs[38:33] ),
.CarryIn (CarryIn ), .Constantb (Constantb ), .Constantc (Constantc ),
.Constantd (Constantd ), .Constante (Constante ),
.Constantf (Constantf ), .Constantg (Constantg ),
.Constanth (Constanth ), .ExpAregLoadEn (ExpAregLoadEn ),
.ExpAregLC0 (ExpAregLC0 ), .ExpAregLC1 (ExpAregLC1 ),
.ExpBregLC0 (ExpBregLC0 ), .ExpBregLC1 (ExpBregLC1 ),
.ExpBregLoadEn (ExpBregLoadEn ), .notSignAFromB (notSignAFromB ),
.notSignBFromA (notSignBFromA ),
.notWaitForShifter (notWaitForShifter ), .SROneMore (SROneMore ),
.SRToSticky (SRToSticky ), .SRControl (SRControl) );
endmodule
|
module frac_ctl ( Phi, AregMaster_32, BregFPMSBM1, CALSB, CBLSB, CCLSB,
FracBregSign, FracSign, LoadForInt, LoadOprs, notAbortWB,
notAM31_3, notAM2_0, notAregMasterFPMSBP1, notSticky1,
PreventSwap, Rom_Inexact, RomShForAlign, SNnotDB, SROneMore,
SRToSticky, StickyForSR1, AregMaster_57_40,
AregMaster_7_0,
CarryInLSBs, CregInSL2SQRT, CregSNBits, ExpIn, notMultip, notSticky4,
Rom_63_48, SALSBs, SBLSBs, SCLSBs, SRControl, StepRemBits, Sticky2,
StickyExtra, SumInLSBs, TregLSBs, YDest,
CarryOut0, CarryOut3, FracAregLoadEn, FracBregLoadEn,
FracCregLoadEn, FracCregLC, FracTregLoadEn, Inexact,
InitialCarryBit, InitialMulStep, notFracYFromD1A,
notFracYFromD2A, notFracYFromD3A, notStickyInForSR,
SumCarryLoadEn, SumOut0, FracAregLC, FracBregLC, FracYbusLSBs,
InForCreg, InForCregDB, InFromCregOr0, LIB, notNO, notsh, Pos, Shift,
TopBitsIn, Zero );
input Phi, AregMaster_32, BregFPMSBM1, CALSB, CBLSB, CCLSB,
FracBregSign, FracSign, LoadForInt, LoadOprs, notAbortWB,
notAM31_3, notAM2_0, notAregMasterFPMSBP1, notSticky1,
PreventSwap, Rom_Inexact, RomShForAlign, SNnotDB, SROneMore,
SRToSticky, StickyForSR1 ;
input [57:40] AregMaster_57_40 ;
input [7:0] AregMaster_7_0 ;
input [2:0] CarryInLSBs ;
input [1:0] CregInSL2SQRT ;
input [1:0] CregSNBits ;
input [8:0] ExpIn ;
input [8:0] notMultip ;
input [3:0] notSticky4 ;
input [63:48] Rom_63_48 ;
input [1:0] SALSBs ;
input [1:0] SBLSBs ;
input [1:0] SCLSBs ;
input [3:0] SRControl ;
input [3:0] StepRemBits ;
input [1:0] Sticky2 ;
input [1:0] StickyExtra ;
input [2:0] SumInLSBs ;
input [1:0] TregLSBs ;
input [6:0] YDest ;
output CarryOut0, CarryOut3, FracAregLoadEn, FracBregLoadEn,
FracCregLoadEn, FracCregLC, FracTregLoadEn, Inexact,
InitialCarryBit, InitialMulStep, notFracYFromD1A,
notFracYFromD2A, notFracYFromD3A, notStickyInForSR,
SumCarryLoadEn, SumOut0 ;
output [2:0] FracAregLC ;
output [2:0] FracBregLC ;
output [1:0] FracYbusLSBs ;
output [1:0] InForCreg ;
output [1:0] InForCregDB ;
output [1:0] InFromCregOr0 ;
output [2:0] LIB ;
output [1:0] notNO ;
output [3:1] notsh ;
output [3:0] Pos ;
output [3:0] Shift ;
output [8:0] TopBitsIn ;
output [3:0] Zero ;
wire LoadFromMult, RomFracBSL2FromC, SelInitRemBits ;
wire [3:1] DivMultiple ;
wire [1:0] QuoBits ;
BregLoadCtl fblc ( .RomFracBregLC( Rom_63_48[60:59] ), .RomBSL2InFromC(
RomFracBSL2FromC), .LoadOprs(LoadOprs), .notAbortWB(notAbortWB),
.PreventSwap(PreventSwap), .LoadFromMult(LoadFromMult), .CregInSL2SQRT(
CregInSL2SQRT[1:0] ), .FracBregLC( FracBregLC[2:0] ), .FracBregLoadEn(
FracBregLoadEn), .InFromCregOr0( InFromCregOr0[1:0] ) );
ShiftLeftCtl slc ( .NI_49_47( AregMaster_57_40[49:47] ), .LoadForInt(
LoadForInt), .LIB( LIB[2:0] ) );
AregLoadCtl falc ( .ROM( Rom_63_48[58:56] ), .LoadOprs(LoadOprs),
.notAbortWB(notAbortWB), .PreventSwap(PreventSwap), .FracAregLC(
FracAregLC[2:0] ), .FracAregLoadEn(FracAregLoadEn), .LoadFromMult(
LoadFromMult), .SelInitRemBits(SelInitRemBits) );
TregLoadCtl tlc ( .RomFracTFromRes(Rom_63_48[63] ),
.notAbortWB(notAbortWB), .FracTregLoadEn(FracTregLoadEn) );
NormCalSlice an ( .NI( AregMaster_57_40[55:40] ), .notsh( notsh[3:1] ),
.notNO( notNO[1:0] ) );
AregInexact aic ( .RomInexactRound(Rom_Inexact), .SNnotDB(SNnotDB),
.AMCBit(AregMaster_57_40[56] ), .AM32(AregMaster_32), .AM3(
AregMaster_7_0[3] ), .notAM31_3(notAM31_3), .notAM2_0(notAM2_0),
.Inexact(Inexact) );
MultiplierLSB mlsb ( .Rom_ResetMul(Rom_63_48[63] ), .notMultip(
notMultip[8:0] ), .notAbortWB(notAbortWB), .SumInLSBs(SumInLSBs[2:0] ),
.CarryInLSBs( CarryInLSBs[2:0] ), .SCLSBs( SCLSBs[1:0] ), .SBLSBs(
SBLSBs[1:0] ), .SALSBs( SALSBs[1:0] ), .CCLSB(CCLSB), .CBLSB(CBLSB),
.CALSB(CALSB), .Shift( Shift[3:0] ), .Pos( Pos[3:0] ), .Zero(
Zero[3:0] ), .CarryOut0(CarryOut0), .CarryOut3(CarryOut3), .SumOut0(
SumOut0), .SumCarryLoadEn(SumCarryLoadEn), .InitialMulStep(
InitialMulStep), .InitialCarryBit(InitialCarryBit) );
DivLog divl ( .Phi(Phi), .AregFPMSBM1(AregMaster_57_40[54] ),
.BregFPMSBM1(BregFPMSBM1), .StepRemBits( StepRemBits[3:0] ),
.InitialRemBits( AregMaster_57_40[57:54] ), .SelectInitial(
SelInitRemBits), .FracSign(FracSign), .DivMultiple( DivMultiple[3:1] ),
.QuotientBits( QuoBits[1:0] ) );
CregLoadCtl fclc ( .RomCregCtl(Rom_63_48[62:61] ), .QuoBits(QuoBits[1:0] ),
.notAbortWB(notAbortWB), .SNnotDB(SNnotDB), .CregSNBits(
CregSNBits[1:0] ), .InForCreg( InForCreg[1:0] ), .InForCregDB(
InForCregDB[1:0] ), .RomFracBSL2FromC(RomFracBSL2FromC),
.FracCregLoadCtl0(FracCregLC), .FracCregLoadEn(FracCregLoadEn) );
ShiftRightCtl src ( .LoadForInt(LoadForInt), .AregMasterBuf_57_55(
AregMaster_57_40[57:55] ), .ExpIn( ExpIn[8:0] ), .SRControl(
SRControl[3:0] ), .SROneMore(SROneMore), .SRToStky(SRToSticky),
.Stky8( AregMaster_7_0[7:0] ), .notStky4( notSticky4[3:0] ),
.Stky2( Sticky2[1:0] ), .notStky1(notSticky1), .StkyExtra(
StickyExtra[1:0] ), .RomShForAl(RomShForAlign), .notStkyInForSR(
notStickyInForSR), .TopBitsIn( TopBitsIn[8:0] ) );
YMuxCtl fymc ( .RomYMuxCtl( Rom_63_48[55:48] ), .YFunc( YDest[6:0] ),
.FracAregFPMSBP1( AregMaster_57_40[56] ), .notFracAregFPMSBP1(
notAregMasterFPMSBP1), .FracBregSign(FracBregSign), .DivMultiple(
DivMultiple[3:1] ), .AregLSBs( AregMaster_7_0[2:0] ),
.StickyForSR1(StickyForSR1), .TregLSBs( TregLSBs[1:0] ),
.notFracYFromD1A(notFracYFromD1A), .notFracYFromD2A(notFracYFromD2A),
.notFracYFromD3A(notFracYFromD3A), .FracYLSBs( FracYbusLSBs[1:0] ) );
endmodule
|
module ImplementedCheck (Phi,
// input
ResetImp,
notReset,
FpOp,
EntryPoint,
FpInst, // sparc FP inst field
// outputs
notDecodedUnImp,
notUnimpOrReset,
notAbortInst, ResetAbortInst,
FPOP2Map,
UnImpOut);
input Phi,
ResetImp, // Reset beore modification
notReset, // Reset After modification
FpOp,
EntryPoint;
input [9:4] FpInst;
output notDecodedUnImp; // Go busy quickly
output notUnimpOrReset,
notAbortInst, // Aborting so remain busy for two extra cycles
ResetAbortInst,
FPOP2Map,
UnImpOut;
// ***************************************//
// Imp Check //
// ***************************************//
ME_NAND2 idg0 (FpInst[4], FpInst[6], notFpInst4and6);
ME_OR2 idg1 (FpInst[7], notFpInst4and6, notFPOP2Map);
ME_INV_B idg2 (notFPOP2Map, FPOP2Map);
ME_XOR2 idg3 (FpInst[9], FPOP2Map, notEntryMap);
ME_OR2 idg4 (notEntryMap, FpInst[8], UnImpMap);
ME_INV_A rrr7 (notReset, Reset);
ME_OR2 ggh3 (FpOp, Reset, UnImpMapEn);
ME_FD1E ggh1 (Phi, UnImpMapEn, UnImpMap, , ImpMap);
ME_FD1 rrr6 (Phi, FpOp, FpOpHeld, notFpOpHeld);
ME_INVA ggh2 (ResetImp, notResetImp);
ME_NAND3 ggh4 (ImpMap, EntryPoint, notReset, notImpStart);
ME_NAND3 ddfd (notImpStart, notResetImp, FpOpHeld, notDecodedUnImp);
ME_NAND2 g_1 (notFpOpHeld, notReset, FpOpHeldOrReset);
ME_NAND2_B g_3 (FpOpHeldOrReset, notImpStart, notUnimpOrReset);
ME_OR2 icor (FpOpHeld, ResetImp, NewInsOrReset);
ME_FD1E ni (Phi, NewInsOrReset, notDecodedUnImp, , UnImpOut );
// ***************************************//
// Kill UnImp Inst //
// ***************************************//
// KillUnImp is used to abort loading of MIptr
// In addition it is used to cause at least three busy cycles
// after which the FPU will accept new Insts
// The FPU is kept in reset until the last busy cycle
ME_FD1 ggh11 (Phi, notDecodedUnImp, notRemainBusy1, RemainBusy1);
ME_FD1 ggh12 (Phi, notRemainBusy1, notRemainBusy2, RemainBusy2);
ME_NAND2 ggh5 (notDecodedUnImp, notRemainBusy1,
ResetAbortInst);
ME_AND2 ggh6 (notRemainBusy1, notRemainBusy2, notAbortInst);
endmodule
|
module LengthLogic (Phi, Reset,
FpInst1,
FpLd,
FpOp,
RomToggleLength,
notAbortWB,
OprSNnotDB,
BuffSNnotDB,
U_SNnotDB,
DBnotSN,
MulLenSel);
input Phi, Reset,
FpInst1, FpLd, FpOp, RomToggleLength, notAbortWB;
output OprSNnotDB,
U_SNnotDB,
DBnotSN,
BuffSNnotDB;
output [4:0]MulLenSel;
/* *************************************** */
/* Operand Length Logic */
/* *************************************** */
// MUX to FpInst if FpOp
// else used FpInst from previous cycle (original code)
// ME_FD1_B crg1 (Phi, FpInst1, notOprSNnotDBL, );
// ME_MUX2B_B mlen (FpOp, notOprSNnotDBL, FpInst1, notOprSNnotDB);
// timing fix -- dhn 04/15/91 -- this will only work if FpLd is
// always asserted 1 cycle after FpOp, never simultaneously
ME_FD1_B crg1 (Phi, FpInst1, notOprSNnotDB, );
ME_INV_C new0 (notOprSNnotDB, OprSNnotDB);
/* *************************************** */
/* Length Latch */
/* *************************************** */
ME_AND2 rmg3 (RomToggleLength, notAbortWB, LenFromnotLen);
ME_OR3 ell (FpLd, LenFromnotLen, Reset, Enable);
ME_NOR2 cllr (SNnotDB, Reset, notResetSNnotDB);
ME_NMUX2B lm (FpLd, notResetSNnotDB, OprSNnotDB, notMuxedLength);
ME_NMUX2B llm (Enable, DBnotSNb, notMuxedLength, U_SNnotDB);
ME_INVA lli (U_SNnotDB, U_DBnotSN);
ME_FD1_B llf (Phi, U_SNnotDB, SNnotDB, DBnotSNb);
ME_FD1_B lif (Phi, U_DBnotSN, DBnotSN, );
ME_FD1_B lig (Phi, U_DBnotSN, DBnotSNa, ); // goes only to
ME_INV_C llb (DBnotSNa, BuffSNnotDB); // High drive version
ME_FD1_B llf0 (Phi, U_SNnotDB, MulLenSel[0], );
ME_FD1_B llf1 (Phi, U_SNnotDB, MulLenSel[1], );
ME_FD1_B llf2 (Phi, U_SNnotDB, MulLenSel[2], );
ME_FD1_B llf3 (Phi, U_SNnotDB, MulLenSel[3], );
ME_FD1_B llf4 (Phi, U_SNnotDB, MulLenSel[4], );
endmodule
|
module MicrocodeRom (Phi, int_UpdateOutputs, U_RomOutputs,
RomOutputs,
XDest,
YDest );
input Phi;
input int_UpdateOutputs;
input [`RomWidthM1:0] U_RomOutputs; // unbuffered output from ME_UROM
output [`RomWidthM1:0] RomOutputs; // latched version of U_RomOutputs
output [6:0] YDest;
output XDest;
ME_TIEOFF toff (, gnd);
// This flip-flop is only used during scan operations (to allow
// scan testing of the rom). It will be connected by the
// scan-stitcher when this block is routed.
ME_FD1 scanloadrom_ff (.cp(Phi), .d(gnd), .q(scanloadrom) );
ME_OR2 Uscanloadrom (int_UpdateOutputs, scanloadrom, UpdateOutputs);
// ***************************************//
// ROM :- ROM outputs latched //
// ***************************************//
// Rom outputs are held while waiting, Aborting the instruction,
// Nullifiying and in exceptions.
// The FB and control bits are only held on abort and wait.
ME_FREGA_1_64 romor (Phi, UpdateOutputs, U_RomOutputs, RomOutputs);
ME_FD1E_B romor540 (Phi, UpdateOutputs, U_RomOutputs[`u_FracYbusFromFunc0], YDest[0],);
ME_FD1E_B romor551 (Phi, UpdateOutputs, U_RomOutputs[`u_FracYbusFromFunc1], YDest[1],);
ME_FD1E_B romor542 (Phi, UpdateOutputs, U_RomOutputs[`u_FracYbusFromFunc2], YDest[2],);
ME_FD1E_B romor553 (Phi, UpdateOutputs, U_RomOutputs[`u_FracYbusFromFunc0], YDest[3],);
ME_FD1E_B romor554 (Phi, UpdateOutputs, U_RomOutputs[`u_FracYbusFromFunc1], YDest[4],);
ME_FD1E_B romor555 (Phi, UpdateOutputs, U_RomOutputs[`u_FracYbusFromFunc2], YDest[5],);
ME_FD1E_B romor556 (Phi, UpdateOutputs, U_RomOutputs[`u_FracYbusFromFunc0], YDest[6],); // SQRT bit
ME_FD1E_B romor557 (Phi, UpdateOutputs, U_RomOutputs[`u_FracXbusFromDest2], XDest,); // Round bit
endmodule
|
module MIptr (Phi,
ExMIptrLSBs,
DyadicExc,
notInstAndNoExc,
notBranchTakenMIS,
notResetOrUnimp,
MIptrLoadEnable,
Feedback, FpInst,
SelectedMIptr,
RomMIptr, notRomMIptr);
input [2:0] ExMIptrLSBs;
input [`MIptrMSB:0] Feedback;
input [7:0] FpInst;
input Phi;
input DyadicExc,
notInstAndNoExc,
notBranchTakenMIS,
notResetOrUnimp,
MIptrLoadEnable;
output [`MIptrMSB:0] SelectedMIptr, RomMIptr, notRomMIptr;
ME_TIEOFF toff (vdd, gnd);
/* ****************************************************** *
* *
* 1) Enable has been removed from MIptr *
* *
* *
* *
* ****************************************************** */
wire [`MIptrMSB:0] NextMIptr;
// ***************************************//
// Operand Exception Address Generation //
// ***************************************//
ME_OR2 om2n6 (RomMIptr[2], notRomMIptr[6], MI2ornotMI6);
ME_NAND2 om16 (notRomMIptr[1], notRomMIptr[6], MI6orMI1);
MiptrIncrement mii (RomMIptr, NextMIptr);
MIptrMultiplexor mim
(Phi,
DyadicExc,
notInstAndNoExc,
notBranchTakenMIS,
notResetOrUnimp,
MIptrLoadEnable,
{FpInst[7], FpInst[3], FpInst[0], FpInst[1],
FpInst[6], FpInst[2], FpInst[4], FpInst[5]}, // RomEntry := SPARC code to ROM entry point mapping //
NextMIptr,
{RomMIptr[1], MI2ornotMI6, RomMIptr[6], MI6orMI1, gnd, ExMIptrLSBs}, // ExMIptr
Feedback,
SelectedMIptr,
RomMIptr,
notRomMIptr);
endmodule
|
module MiptrIncrement (RomMIptr, NextMIptr);
input [7:0] RomMIptr;
output [7:0] NextMIptr;
// Increment of MI required (8 bits)
// always @MIptr NextMIptr = MIptr + 1;
ME_XOR2 ha_7 (RomMIptr[7], B7, NextMIptr[7] );
ME_ADD2 ha_6 (RomMIptr[6], B6, NextMIptr[6], B7);
ME_ADD2 ha_5 (RomMIptr[5], B5, NextMIptr[5], B6);
ME_ADD2 ha_4 (RomMIptr[4], B4, NextMIptr[4], B5);
ME_ADD2 ha_3 (RomMIptr[3], B3, NextMIptr[3], B4);
ME_ADD2 ha_2 (RomMIptr[2], B2, NextMIptr[2], B3);
ME_ADD2 ha_1 (RomMIptr[1], RomMIptr[0], NextMIptr[1], B2);
ME_INVA ha_0 (RomMIptr[0], NextMIptr[0]);
endmodule
|
module MIptrMultiplexor
(Phi,
DyadicExc,
notInstAndNoExc,
notBranchTakenMIS,
notResetOrUnimp,
MIptrLoadEnable,
RomEntry,
NextMIptr,
ExMIptr,
Feedback,
SelectedMIptr, // unregistered version of RomMIptr
RomMIptr,
notRomMIptr);
input Phi;
input DyadicExc,
notInstAndNoExc,
notBranchTakenMIS,
notResetOrUnimp,
MIptrLoadEnable;
input [7:0] RomEntry, NextMIptr,
ExMIptr, Feedback;
output [7:0] SelectedMIptr, RomMIptr, notRomMIptr;
wire [7:0] Z1, Z2, Z5, Z3, notFeedbackW;
ME_INV_C ble (MIptrLoadEnable, _MIptrLoadEnable);
ME_NMUX_2B_8 g2 (DyadicExc, NextMIptr, ExMIptr, Z1);
ME_MUX_2B_8 g3 (notInstAndNoExc, RomEntry, Z5, Z2);
ME_NMUX_2B_8 g4 (_MIptrLoadEnable, Z2, RomMIptr, Z3);
ME_NAND2 g6_0 (notResetOrUnimp, Z1[0], Z5[0]);
ME_NAND2 g6_1 (notResetOrUnimp, Z1[1], Z5[1]);
ME_NAND2 g6_2 (notResetOrUnimp, Z1[2], Z5[2]);
ME_NAND2 g6_3 (notResetOrUnimp, Z1[3], Z5[3]);
ME_NAND2 g6_4 (notResetOrUnimp, Z1[4], Z5[4]);
ME_NAND2 g6_5 (notResetOrUnimp, Z1[5], Z5[5]);
ME_NAND2 g6_6 (notResetOrUnimp, Z1[6], Z5[6]);
ME_NAND2 g6_7 (notResetOrUnimp, Z1[7], Z5[7]);
ME_NMUX_2B_8 g5 (_MIptrLoadEnable, Feedback, RomMIptr, notFeedbackW);
/* ********************************************************* */
// This bit should be converted into MUX and LATCH
/* ********************************************************* */
ME_NMUX2B g10 (notBranchTakenMIS, notFeedbackW[0], Z3[0], SelectedMIptr[0] );
ME_NMUX2B g11 (notBranchTakenMIS, notFeedbackW[1], Z3[1], SelectedMIptr[1] );
ME_NMUX2B g12 (notBranchTakenMIS, notFeedbackW[2], Z3[2], SelectedMIptr[2] );
ME_NMUX2B g13 (notBranchTakenMIS, notFeedbackW[3], Z3[3], SelectedMIptr[3] );
ME_NMUX2B g14 (notBranchTakenMIS, notFeedbackW[4], Z3[4], SelectedMIptr[4] );
ME_NMUX2B g15 (notBranchTakenMIS, notFeedbackW[5], Z3[5], SelectedMIptr[5] );
ME_NMUX2B g16 (notBranchTakenMIS, notFeedbackW[6], Z3[6], SelectedMIptr[6] );
ME_NMUX2B g17 (notBranchTakenMIS, notFeedbackW[7], Z3[7], SelectedMIptr[7] );
ME_FD1 mib0 (Phi, SelectedMIptr[0], RomMIptr[0], notRomMIptr[0]) ;
ME_FD1 mib1 (Phi, SelectedMIptr[1], RomMIptr[1], notRomMIptr[1]) ;
ME_FD1 mib2 (Phi, SelectedMIptr[2], RomMIptr[2], notRomMIptr[2]) ;
ME_FD1 mib3 (Phi, SelectedMIptr[3], RomMIptr[3], notRomMIptr[3]) ;
ME_FD1 mib4 (Phi, SelectedMIptr[4], RomMIptr[4], notRomMIptr[4]) ;
ME_FD1 mib5 (Phi, SelectedMIptr[5], RomMIptr[5], notRomMIptr[5]) ;
ME_FD1 mib6 (Phi, SelectedMIptr[6], RomMIptr[6], notRomMIptr[6]) ;
ME_FD1 mib7 (Phi, SelectedMIptr[7], RomMIptr[7], notRomMIptr[7]) ;
/*ME_FD2_B mib0 (Phi, notBranchTakenMIS, notFeedbackW[0], Z3[0], notRomMIptr[0], RomMIptr[0]) ;
ME_FD2_B mib1 (Phi, notBranchTakenMIS, notFeedbackW[1], Z3[1], notRomMIptr[1], RomMIptr[1]) ;
ME_FD2_B mib2 (Phi, notBranchTakenMIS, notFeedbackW[2], Z3[2], notRomMIptr[2], RomMIptr[2]) ;
ME_FD2_B mib3 (Phi, notBranchTakenMIS, notFeedbackW[3], Z3[3], notRomMIptr[3], RomMIptr[3]) ;
ME_FD2_B mib4 (Phi, notBranchTakenMIS, notFeedbackW[4], Z3[4], notRomMIptr[4], RomMIptr[4]) ;
ME_FD2_B mib5 (Phi, notBranchTakenMIS, notFeedbackW[5], Z3[5], notRomMIptr[5], RomMIptr[5]) ;
ME_FD2_B mib6 (Phi, notBranchTakenMIS, notFeedbackW[6], Z3[6], notRomMIptr[6], RomMIptr[6]) ;
ME_FD2_B mib7 (Phi, notBranchTakenMIS, notFeedbackW[7], Z3[7], notRomMIptr[7], RomMIptr[7]) ; */
/*CSL_FD1SP mib0 (notFeedbackW[0], Phi, Z3[0], notBranchTakenMIS, notRomMIptr[0], RomMIptr[0]);
CSL_FD1SP mib1 (notFeedbackW[1], Phi, Z3[1], notBranchTakenMIS, notRomMIptr[1], RomMIptr[1]);
CSL_FD1SP mib2 (notFeedbackW[2], Phi, Z3[2], notBranchTakenMIS, notRomMIptr[2], RomMIptr[2]);
CSL_FD1SP mib3 (notFeedbackW[3], Phi, Z3[3], notBranchTakenMIS, notRomMIptr[3], RomMIptr[3]);
CSL_FD1SP mib4 (notFeedbackW[4], Phi, Z3[4], notBranchTakenMIS, notRomMIptr[4], RomMIptr[4]);
CSL_FD1SP mib5 (notFeedbackW[5], Phi, Z3[5], notBranchTakenMIS, notRomMIptr[5], RomMIptr[5]);
CSL_FD1SP mib6 (notFeedbackW[6], Phi, Z3[6], notBranchTakenMIS, notRomMIptr[6], RomMIptr[6]);
CSL_FD1SP mib7 (notFeedbackW[7], Phi, Z3[7], notBranchTakenMIS, notRomMIptr[7], RomMIptr[7]);*/
endmodule
|
module MISelect (Phi,
notReset,
notBrTaken,
notDecodedUnimp,
MIFromInstN, MIFromInstB,
notAbortInst, notAbortNulExc,
notResetOrUnimp,
DyadicOprExc, notSampledWait,
FpOp,
notSingleCycInst,
// outputs
BTHeld,
Busy, notIdleHeld,
notInstAndNoExc,
MILoadEnable);
input Phi, notReset;
input notBrTaken,
notDecodedUnimp,
MIFromInstN, MIFromInstB,
notAbortInst, notAbortNulExc,
notResetOrUnimp,
DyadicOprExc, notSampledWait,
FpOp,
notSingleCycInst; // Is single cycle
output BTHeld;
output Busy, notIdleHeld,
notInstAndNoExc,
MILoadEnable;
ME_TIEOFF toff (vdd, gnd);
ME_INVA iecepl (DyadicOprExc, notDyadicOprExc);
// ***************************************//
// Decide if next is new Inst //
// ***************************************//
// MIFromInstN Execute Inst if Br not taken
// MIFromInstB Execute Inst Br taken
// Note delay cycle
ME_NAND3 g4_0 (MIFromInstN, notAbortNulExc, notSampledWait,
notMIFromInstNExc);
ME_NAND2 g4_1 (MIFromInstN, notAbortNulExc, // notSampledWait, Shouldnt be a function of this
notMIFromInstNExcNS);
ME_NAND2 g4_2 (MIFromInstB, notSampledWait, notMIFromInstBW);
ME_FD1 g4_3 (Phi, notMIFromInstBW, , MIFromInstBHeld);
ME_NAND2 g4_4 (BTHeld, MIFromInstBHeld, s_0);
ME_FD1 g4_5 (Phi, notResetOrUnimp, nots_1, );
ME_AND4 g4_6 (s_0, nots_1, notSingleCycInst, notIdleHeld, notZZTop);
ME_NAND2 g4_7 (notZZTop, notMIFromInstNExc, MIFromInst);
ME_NAND2 g4_8 (notZZTop, notMIFromInstNExcNS, MIFromInstNS);
// ***************************************//
// Are we going to be idle //
// ***************************************//
ME_INVA g5_0 (FpOp, notFpOp);
ME_NAND2 g5_1 (MIFromInst, notFpOp, notIdleIfNotBred);
ME_FD1 g5_3 (Phi, notIdleIfNotBred, notIIfNotBredHld, );
ME_NMUX2B g5_2 (notBTHeld, vdd, notIIfNotBredHld, IdleHeldNR);
ME_NAND2 g5_4 (IdleHeldNR, notReset, notIdleHeld);
// ***************************************//
// Select next MI for ROM to decode //
// ***************************************//
// Combine Wait Exception and Br logic into ROM control
//
ME_BUF_B mie0 (notSampledWait, MILoadEnable); // Buff over 8 bits
//
ME_NAND3_B g0_0 (MIFromInstNS, notDyadicOprExc, notResetOrUnimp,
notInstAndNoExc);
// ***************************************//
// Started New Inst //
// ***************************************//
// Requirement for testing for implemented entry points.
// These need to be qualified as being the first Inst
// since garbage code may jump through an entry point
// thus setting the implemented flag.
// Optimise
// Latch BT
ME_FD1 g2_1 (Phi, notBrTaken, notBTHeld, BTHeld);
// ***************************************//
// FPU Busy //
// ***************************************//
// Remain busy while aborting an Unimp
ME_AND4 ggh7 (notAbortInst, notDyadicOprExc,
MIFromInst, notSampledWait,
notMIsBusyBT0);
ME_AND2 ggh8 (notMIsBusyBT0, notDecodedUnimp, notBusyBT0);
ME_NMUX2B_B ggh9 (notBrTaken, gnd, notBusyBT0, Busy);
endmodule
|
module StickyPairNC (StkIn, notCin, X, Y, StkOut, notCout);
input StkIn, notCin ;
input [1:0] X, Y ;
output StkOut, notCout ;
ME_XNOR2_B g10 ( X[0], Y[0], notZ0 );
ME_XNOR2_B g11 ( X[1], Y[1], notZ1 );
ME_OR2_B g13 ( notZ0, notZ1, notProp );
// generate logic
//ME_NMUX2B g12 ( Z1, x[1], x[0], notglo ) ;
ME_NAND3 g20 ( X[0], Y[0], X[1], g1 );
ME_NAND3 g21 ( X[0], Y[0], Y[1], g2 );
ME_NAND2 g22 ( X[1], Y[1], g3 );
ME_NAND3 g23 ( g1, g2, g3, generate );
// local sticky
ME_NAND2 g14 ( X[0], Y[0], notgenlo);
ME_XOR3_B g26 ( notgenlo, X[1], Y[1], bit1);
ME_NAND3 g24 ( notZ0, bit1, notCin, StkGen);
ME_NMUX2B g28 ( notProp, notCin, StkGen, notStk ) ;
// bypasses
ME_INV_A g31 ( StkIn, notStkIn );
ME_NAND2 g32 ( notStkIn, notStk, StkOut );
ME_INVA g27 ( notCin, Cin );
ME_NMUX2B_B g34 ( notProp, Cin, generate, notCout );
endmodule
|
module StickyPairNCI (StkIn, notCin, X, Y, StkOut, Cout);
input StkIn, notCin ;
input [1:0] X, Y ;
output StkOut, Cout ;
ME_XNOR2_B g10 ( X[0], Y[0], notZ0 );
ME_XNOR2_B g11 ( X[1], Y[1], notZ1 );
ME_OR2_B g13 ( notZ0, notZ1, notProp );
// generate logic
//ME_NMUX2B g12 ( Z1, x[1], x[0], notglo ) ;
ME_NAND3 g20 ( X[0], Y[0], X[1], g1 );
ME_NAND3 g21 ( X[0], Y[0], Y[1], g2 );
ME_NAND2 g22 ( X[1], Y[1], g3 );
ME_NAND3 g23 ( g1, g2, g3, generate );
// local sticky
ME_NAND2 g14 (X[0], Y[0], notgenlo);
ME_XOR3_B g26 ( notgenlo, X[1], Y[1], bit1);
ME_NAND3_B g25 ( notZ0, bit1, notCin, StkGen);
ME_NMUX2B g28 ( notProp, notCin, StkGen, notStk ) ;
// bypasses
ME_INVA g31 ( StkIn, notStkIn );
ME_NAND2_B g32 ( notStkIn, notStk, StkOut );
ME_INVA g27 ( notCin, Cin );
ME_MUX2B g34 ( notProp, Cin, generate, Cout );
endmodule
|
module MulLSBlog (SIn, CIn, SInA, CInA, LSBCarryIn, StickyIn,
LSBCarryOut, StickyOut);
input [1:0] SIn, CIn;
input [5:0] SInA, CInA;
input LSBCarryIn, StickyIn;
output LSBCarryOut, StickyOut;
// wire [2:0] Sticky;
// wire [7:0] SS;
// wire [7:1] CO;
ME_INVA g27 ( LSBCarryIn, notLSBCarryIn );
StickyPairNC m0 (StickyIn, notLSBCarryIn, CIn, SIn, SS0, notC0);
StickyPairNC m1 (SS0, notC0, CInA[1:0], SInA[1:0], SS1, notC1);
StickyPairNC m2 (SS1, notC1, CInA[3:2], SInA[3:2], SS2, notC2);
StickyPairNCI m3 (SS2, notC2, CInA[5:4], SInA[5:4], StickyOut, LSBCarryOut);
// ME_ADD3 a0 (CIn[0], SIn[0], LSBCarryIn, SS[0], CO[1]);
// ME_ADD3 a1 (CIn[1], SIn[1], CO[1], SS[1], CO[2]);
// ME_OR3 o1 (SS[0], SS[1], StickyIn, Sticky[0]);
// ME_ADD3 a2 (CInA[0], SInA[0], CO[2], SS[2], CO[3]);
// ME_ADD3 a3 (CInA[1], SInA[1], CO[3], SS[3], CO[4]);
// ME_OR3 o2 (SS[2], SS[3], Sticky[0], Sticky[1]);
// ME_ADD3 a4 (CInA[2], SInA[2], CO[4], SS[4], CO[5]);
// ME_ADD3 a5 (CInA[3], SInA[3], CO[5], SS[5], CO[6]);
// ME_OR3 o3 (SS[4], SS[5], Sticky[1], Sticky[2]);
// ME_ADD3 a6 (CInA[4], SInA[4], CO[6], SS[6], CO[7]);
// ME_ADD3 a7 (CInA[5], SInA[5], CO[7], SS[7], LSBCarryOut);
// ME_OR3 o4 (SS[6], SS[7], Sticky[2], StickyOut);
endmodule
|
module MulSelCtl (notMult, Shifted, Pos, Zero, ACI);
input [2:0] notMult;
output Shifted, Zero, Pos, ACI;
//
// Mult 0 0 0
// ACI is Actual Carry In
// Shifted is 1
ME_XOR2_B xnr7 (notMult[1], notMult[0], Shifted);
/* Feedthrough */
/* wire Negative = Mult[2]; */
con1 g00 (notMult[2], Pos);
ME_INV_A g01 (notMult[2], Negative);
// assert ACI if subtracting
ME_OR2_B cz1 (notMult[0], notMult[1], notSwig);
ME_AND2 cz2 (Negative, notSwig, ACI); // 2 gates
//ME_INV_B g02 (Negative, notMult2);
// all ones or all zeros gives zero
ME_OR3_B nzr5 (notMult[2], notMult[0], notMult[1], notPos0);
ME_NAND3 nzr6 (notMult[2], notMult[1], notMult[0], notNeg0);
ME_NAND2_B nzr8 (notNeg0, notPos0, Zero);
endmodule
|
module MultiplierLSB (
// inputs
Rom_ResetMul,
notMultip,
notAbortWB,
SumInLSBs, CarryInLSBs,
SCLSBs, SBLSBs, SALSBs,
CCLSB, CBLSB, CALSB,
// outputs
Shift,
Pos,
Zero,
CarryOut0,
CarryOut3,
SumOut0,
SumCarryLoadEn,
InitialMulStep,
/* dhn--01/10/91 notInitialSumZero, */
InitialCarryBit);
input notAbortWB, Rom_ResetMul;
input [2:0] SumInLSBs, CarryInLSBs;
input [1:0] SCLSBs, SBLSBs, SALSBs;
input CCLSB, CBLSB, CALSB;
input [8:0] notMultip;
output [3:0] Shift, Pos, Zero;
output CarryOut0,
CarryOut3,
SumOut0;
output InitialCarryBit,
SumCarryLoadEn,
InitialMulStep;
/* dhn--01/10/91 notInitialSumZero; */
/* *************************************************
Multipler Selection Decoding
************************************************* */
MulSelCtl m13 (notMultip[8:6], Shift[3], Pos[3], Zero[3], CarryOut3);
MulSelCtl m12 (notMultip[6:4], Shift[2], Pos[2], Zero[2], CCIn);
MulSelCtl m11 (notMultip[4:2], Shift[1], Pos[1], Zero[1], CBIn);
MulSelCtl m10 (notMultip[2:0], Shift[0], Pos[0], Zero[0], CAIn);
/* *************************************************
Full Add over LSBs and OR result
************************************************* */
MulLSBlog lbg (SumInLSBs[2:1], CarryInLSBs[2:1],
{SCLSBs, SBLSBs, SALSBs},
{CCLSB, CCIn, CBLSB, CBIn, CALSB, CAIn},
//ArraySStk,
//ArrayCStk,
CarryInLSBs[0], SumInLSBs[0],
CarryOut0, SumOut0);
carrysaveregslsb csrl (Rom_ResetMul,
notMultip[0],
notAbortWB,
SumCarryLoadEn,
InitialMulStep,
/* dhn--01/10/91 notInitialSumZero, */
InitialCarryBit);
endmodule
|
module NormCalSlice (NI, notsh, notNO);
input [15:0] NI;
output [3:1] notsh;
output [1:0] notNO;
wire [3:0] notNR ;
twosch m1 (NI[7:0], sh1a, sh2a, notNR[1:0]);
twosch_top m2 (NI[15:8], sh1b, sh2b, notNR[3:2], NR1and0);
onesch_sp m3 (notNR[3:0], notsh[3], notNO[1:0]);
// anything set on top then take s1 , s2 from top
ME_NMUX2B m4 (NR1and0, sh1a, sh1b, notsh[1]);
ME_NMUX2B m6 (NR1and0, sh2a, sh2b, notsh[2]);
endmodule
|
module twosch (NI[7:0],sh1,sh2,notNO[1:0] );
input [7:0] NI ;
output sh1, sh2 ;
output [1:0] notNO ; // true OR value here
wire [3:0] notNR ;
onesch m1 (NI[3:0], notsh1a, notNR[1:0]);
onesch m2 (NI[7:4], notsh1b, notNR[3:2]);
notonesch m3 (notNR[3:0], sh2, notNO[1:0]);
// anything set on top then take s1 from top
ME_NMUX2B m4 (notNO[1], notsh1b, notsh1a, sh1 );
endmodule
|
module twosch_top (NI[7:0],sh1,sh2,notNO[1:0], NO1and0 );
input [7:0] NI ;
output sh1, sh2 ;
output [1:0] notNO ; // true OR value here
output NO1and0 ;
wire [3:0] notNR ;
onesch m1 (NI[3:0], notsh1a, notNR[1:0]);
onesch m2 (NI[7:4], notsh1b, notNR[3:2]);
notonesch m3 (notNR[3:0], sh2, notNO[1:0]);
// anything set on top then take s1 from top
ME_NMUX2B_B m4 (notNO[1], notsh1b, notsh1a, sh1 );
ME_NAND4 m5 (notNR[0], notNR[1], notNR[2], notNR[3], NO1and0);
// Special
endmodule
|
module onesch (NI[3:0], notsh1, notNR[1:0]);
input [3:0] NI;
output notsh1;
output [1:0] notNR ;
ME_INV_A i1 (NI[1], notNI1);
ME_NOR2 i2 (NI[2], notNI1, notBornotC);
ME_OR2 i3 (NI[3], notBornotC, notsh1);
// ME_INV_A i1 (NI[1], notNI1);
// ME_INV_A i2 (NI[3], notNI3);
// ME_O2A1I i3 (notNI1, NI[2], notNI3, notsh1);
ME_NOR2_B r4 (NI[0], NI[1], notNR[0] );
ME_NOR2_B r5 (NI[2], NI[3], notNR[1] );
endmodule
|
module notonesch (notNI[3:0], sh1, notND[1:0]);
input [3:0] notNI;
output sh1;
output [1:0] notND ;
ME_INV_A i1 (notNI[1], NI1);
ME_NAND2_B i2 (NI1, notNI[2], notBornotC);
ME_AND2_B i3 (notNI[3], notBornotC, sh1);
// ME_INV_A i1 (notNI[1], NI1);
// ME_INV_A i2 (notNI[3], NI3);
// ME_A2O1I i3 (NI1, notNI[2], NI3, sh1);
ME_AND2_B r4 (notNI[0], notNI[1], notND[0] );
ME_AND2_B r5 (notNI[2], notNI[3], notND[1] );
endmodule
|
module onesch_sp (notNI[3:0], notsh1, notND[1:0]);
input [3:0] notNI;
output notsh1;
output [1:0] notND ;
ME_INV_A i1 (notNI[1], NI1);
ME_NAND2_B i2 (NI1, notNI[2], notBornotC);
ME_NAND2_B i3 (notNI[3], notBornotC, notsh1);
// ME_INV_A i1 (NI[2], notNI2);
// ME_O2A1I i2 (notNI[1], NI2, notNI[3], notsh1);
ME_NAND2 r4 (notNI[0], notNI[1], notND[0] );
ME_NAND2_B r5 (notNI[2], notNI[3], notND[1] );
endmodule
|
module NullExcepLogic (Phi, notReset,
RomNullifyOnBrOr,
RomOprExc,
BTLatched, notSampledWait,
FpLd,
notAInfNan, notAZeroDenorm,
notBInfNan, notBZeroDenorm,
ExMIptrLSBs,
AregOprExc,
DyadicOprExc,
notAbortNulExc,
notAbortWB);
input Phi, notReset, // System Clock Reset
RomNullifyOnBrOr, // Nullify if we Br
RomOprExc, // Check for Op Exception
BTLatched, // We have Bring
notSampledWait, // Don't nullify if waiting
FpLd, // FpLd Force write back
notAInfNan, notAZeroDenorm,
notBInfNan, notBZeroDenorm;
output [2:0] ExMIptrLSBs;
output notAbortNulExc,
AregOprExc,
DyadicOprExc,
notAbortWB;
// ***************************************//
// Nullification for Br //
// ***************************************//
// An unwaited output is used to prevent locking in the NULL state
// NullEx is fedback to prevent locking
// ie only one NULL cycle will occur.
// The signal notNullifyOnBr is therefore 'If the Br is
// taken
//
ME_AND2 rb (RomNullifyOnBrOr, notNullEx, NullifyOnBr);
// ME_INVA sx (SampledWait, notSampledWait);
// Optimise
// ME_NAND3 re (notSampledWait, BrTaken, NullifyOnBr, notND);
// These ROM outputs occur on Phi and then cause write back events
// themselves.
// ME_FD1 rf (Phi, notND, notNullEx, NullEx);
ME_NAND2 re (notSampledWait, NullifyOnBr, notNDBTMiss);
ME_FD1 rf (Phi, notNDBTMiss, , NullExBTMiss);
ME_NAND2 g_1 (BTLatched, NullExBTMiss, notNullEx);
ME_INVA g_0 (notNullEx, NullEx);
// NullEx is used to clear the Nullify
// This is used to generate the abort for the write back of
// the nullified cycle. It is combined with the ExcCycle
// and DyadicOprExc signals and to produce AbortWB
// ***************************************//
// Check Opr Exception //
// ***************************************//
ME_NAND2 exg1 (notAInfNan, notAZeroDenorm, AregOprExc);
ME_NAND2 exg2 (notBInfNan, notBZeroDenorm, BregOprExc);
ME_OR2_B exg3 (AregOprExc, BregOprExc, OprExc);
// ***************************************//
// Operand Exception Address Generation //
// ***************************************//
// quick
ME_AND2 eag1 (AregOprExc, BregOprExc, ExMIptrLSBs[2]);
ME_NAND2 eag2 (AregOprExc, notBInfNan, ExMIptrLSBs[1]);
ME_OR2 eag3 (AregOprExc, notBInfNan, notAnormandBin);
ME_NAND2 eag5 (notAnormandBin, notAInfNan, ExMIptrLSBs[0]);
// ***************************************//
// Control Operand Exception //
// ***************************************//
// Ignore Exception if Nullified on previous
ME_AND4 ssss (RomOprExc, notNullEx, notReset, notExcCycle, OprExcEtc);
ME_AND2_B cko (OprExc, OprExcEtc, DyadicOprExc);
ME_FD1 zrd (Phi, DyadicOprExc, ExcCycle, notExcCycle);
// ***************************************//
// Aborting //
// ***************************************//
// Exc and NullEx require next operation to be aborted.
// In addition Exception requires current operation to be aborted.
// Aborting is acheived by preventing results of this cycle to
// be written back.
ME_OR2 yyy (ExcCycle, NullEx, AbortNulExc);
ME_INVA yyc (AbortNulExc, notAbortNulExc);
ME_OR2_B yyb (DyadicOprExc, AbortNulExc, AbortWBNoLoad);
ME_NAND2_B yyd (AbortWBNoLoad, notFpLd, notAbortWB); // Drives a few
ME_INVA yye (FpLd, notFpLd);
endmodule
|
module PreventSwapCtl (FracAgtB, notExpAgtB, ExpZero,
RomPrevIfBgtA, FpLd,
PreventSwap,
PreventSwapExp);
input FracAgtB, notExpAgtB, ExpZero,
FpLd, RomPrevIfBgtA;
output PreventSwap;
output PreventSwapExp;
// Preventing swap on add
// Use seperate line for Exp
ME_INV_A psg0 (FpLd, notFpLd); // On FpLd remove prevent swap
ME_INV_A psg3 (ExpZero, notExpZero);
ME_NAND3_B psg4 (notFpLd, RomPrevIfBgtA, notExpAgtB, notPrevSwap_F0);
ME_NAND4 psg5 (notFpLd, RomPrevIfBgtA, notExpAgtB, notExpZero, notPrevSwap_F1);
ME_NMUX2B_B psg6 (FracAgtB, notPrevSwap_F0, notPrevSwap_F1, PreventSwap);
// Add seperate PreventSwap for Exp
ME_INV_B psg7 (notPrevSwap_F0, PreventSwapExp);
//ME_XOR psg8 (PreventSwapExp, PreventSwap, WrongSwap);
//ME_FD1 psg8 (Phi, WrongSwap, L_WrongSwap, ); // So swap back !!
/* **************************************************** /
/ We know that we've done the wrong swap. Since the
/ swap is only done at the begining of add we can be sure
/ that FracAreg is going to be loaded from the shifter on
/ the subsequent cycle. So we can force it to be loaded from
/ Breg and also force Breg to be loaded from Areg. So that
/ if a swap was prevented it can be redone
* **************************************************** */
endmodule
|
module RoundModeLogic (Phi,
OprRoundMode,
LoadOprs,
notAbortWB,
CMPDecoded, CMPEDecoded,
RomSetRModeMinus,
RModeMinus,
U_RoundingMode);
input Phi;
input [1:0] OprRoundMode;
input LoadOprs,
notAbortWB,
CMPDecoded, CMPEDecoded,
RomSetRModeMinus;
output RModeMinus;
output [1:0] U_RoundingMode;
/* *************************************** */
/* Rounding Mode Latch */
/* *************************************** */
/* In addition to being the rounding mode this latch is also used in
the compares to signal between the two different types Invalid/Vailid
on unordered. This is TACKY but saves a lot of code
Additional inputs CMPE and CMP distinguish between the two types
It isnt a big problem because RMode is part of the instruction not
ME_ROM and so no timing problems will occur */
wire [1:0] notModifiedRMode, notRoundingMode, RoundingMode;
ME_INVA cmpbits (CMPDecoded, notCMPDecoded);
ME_AND2 rmcmp1 (OprRoundMode[1], notCMPDecoded, CMPRMode1);
ME_AND2_B fgf (RomSetRModeMinus, notAbortWB, RModeFromMinus);
ME_NOR3 rmcmpe1 (CMPRMode1, CMPEDecoded, RModeFromMinus, notModifiedRMode[1]);
ME_NOR3 rmcmpe0 (OprRoundMode[0], CMPEDecoded, RModeFromMinus, notModifiedRMode[0]);
/* RoundingMode is latched from status register at the begining of
a new instruction. It is transient therefore. */
ME_OR2_B fgfo (RModeFromMinus, LoadOprs, RMLatchEnable);
ME_NMUX2B rm0m (RMLatchEnable, notRoundingMode[0], notModifiedRMode[0], U_RoundingMode[0]);
ME_FD1 rm0f (Phi, U_RoundingMode[0], RoundingMode[0], notRoundingMode[0]);
ME_NMUX2B rm1m (RMLatchEnable, notRoundingMode[1], notModifiedRMode[1], U_RoundingMode[1]);
ME_FD1 rm1f (Phi, U_RoundingMode[1], RoundingMode[1], notRoundingMode[1]);
ME_AND2 rmc (RoundingMode[0], RoundingMode[1], RModeMinus);
endmodule
|
module SampledWaitCtl (
RomShiftAlign, RomShiftForInt, RomLeftnotRight,
notReset,
notAbortNulExc,
notWaitForShifter,
notNO[1:0],
notIdleLatched,
UpdateOutputs,
notSampledWait);
input RomShiftAlign, RomShiftForInt, RomLeftnotRight;
input notReset, notAbortNulExc;
input notWaitForShifter;
input [1:0] notNO;
input notIdleLatched;
output UpdateOutputs, notSampledWait;
// Cycle maybe nullifed ie AbortNulExc
ME_INVA swrb2 (RomLeftnotRight, RightnotLeft);
ME_OR2_B n0 ( notNO[1], notNO[0], notWaitForNorm ) ;
ME_NMUX2B swrb3 (RomLeftnotRight, notWaitForShifter, notWaitForNorm, WaitQ);
ME_NOR2 swmzs (RomShiftForInt, RightnotLeft, RomWaitForNorm);
ME_OR2 swmis (RomShiftAlign, RomWaitForNorm, RomWaitForShifter);
ME_AND3 g1_0 (notReset, notAbortNulExc, RomWaitForShifter, notPreventWait);
// Add muxes
ME_NAND2_B sweb (WaitQ, notPreventWait, notSampledWait);
ME_AND2 wwpp2 (notSampledWait, notIdleLatched, UpdateOutputs);
endmodule
|
module SampleReset (Phi, ResetIn, ResetAbortInst,
ResetImp, Reset, notReset);
input ResetIn, ResetAbortInst, Phi;
output ResetImp, Reset, notReset;
ME_FD1 rs (Phi, ResetIn, ResetImp, );
ME_OR2 cva (ResetImp, ResetAbortInst, ResetInorAbort);
ME_FD1 rva (Phi, ResetInorAbort, Reset, notReset);
endmodule
|
module ShiftLeftCtl (NI_49_47,
LoadForInt,
LIB);
input [2:0] NI_49_47;
input LoadForInt;
output [2:0] LIB;
ME_TIEOFF toff (vdd, gnd);
ME_MUX2B g20 (LoadForInt, NI_49_47[2], gnd, LIB[2]);
ME_MUX2B g21 (LoadForInt, NI_49_47[1], gnd, LIB[1]);
ME_MUX2B g22 (LoadForInt, NI_49_47[0], vdd, LIB[0]);
endmodule
|
module ShiftRightCtl (
LoadForInt,
AregMasterBuf_57_55,
ExpIn,
SRControl,
SROneMore,
SRToStky,
Stky8,
notStky4,
Stky2,
notStky1,
StkyExtra,
RomShForAl,
notStkyInForSR,
TopBitsIn);
input LoadForInt;
input [2:0] AregMasterBuf_57_55;
input [8:0] ExpIn;
input [7:0] Stky8; // 8 Stky bits from 8 bit stage
input [3:0] notStky4; // 4 inv Stky bits from 4 bit stage
input [1:0] Stky2; // 2 Stky bits from 2 bit stage
input notStky1; // 1 inv Stky bits from 1 bit stage
input [1:0] StkyExtra; // 2 Stky bits from extra 1 bit stage
input [3:0] SRControl;
input SROneMore, SRToStky;
input RomShForAl;
output notStkyInForSR;
output [8:0] TopBitsIn;
// select TopBitsIn
ME_MUX_2B_9 g69 (LoadForInt,
{AregMasterBuf_57_55[2], AregMasterBuf_57_55[2],
AregMasterBuf_57_55[2], AregMasterBuf_57_55[2],
AregMasterBuf_57_55[2], AregMasterBuf_57_55[2],
AregMasterBuf_57_55[2:0]},
ExpIn[8:0],
TopBitsIn);
ME_OR8 g80 (Stky8[0], Stky8[1], Stky8[2], Stky8[3],
Stky8[4], Stky8[5], Stky8[6], Stky8[7], StkyOR8);
ME_NAND2 g8d (StkyOR8, SRControl[3], notStkyA);
ME_NAND4 g81 (notStky4[0], notStky4[1], notStky4[2], notStky4[3], StkyOR4);
ME_NAND2 g8c (StkyOR4, SRControl[2], notStkyB);
ME_O2A1I g82 (Stky2[0], Stky2[1], SRControl[1], notStkyC);
//ME_OR2 g82 (Stky2[0], Stky2[1], StkyOR2);
//ME_NAND2 g84 (StkyOR2, SRControl[1], notStkyC);
ME_INVA g86 (SRControl[0], notSRC0);
ME_OR2 g85 (notStky1, notSRC0, notStkyD);
ME_INVA g89 (RomShForAl, notRomShForAl);
ME_NAND2 gxa (StkyExtra[1], SROneMore, notStkyE);
ME_NAND2 g8x (notRomShForAl, SROneMore, notgoop);
ME_NAND2 gxx (notgoop, StkyExtra[0], notLSB);
//ME_O2A1I g8x (StkyExtra[0], StkyExtra[1], SROneMore, notStkyE);
ME_AND2 g12 (notStkyA, notStkyB, notStkyAB);
ME_NAND3 g13 (notStkyAB, notStkyC, notStkyD, StkyABCD);
// When multiplying the last thing we want is the sticky bit getting
// set. The sticky only gets set therefore if we're shifting right
// for align or stifting right to sticky in one go
ME_INVA g90 (SRToStky, notSRToStky);
ME_NAND2 g91 (notSRToStky, RomShForAl, notSelectStkyABCD);
ME_NMUX2B g92 (notSelectStkyABCD, StkyABCD, SRToStky, notStkyABCDS);
ME_AND3 g88 (notStkyE, notLSB, notStkyABCDS, notStkyInForSR);
endmodule
|
module SignDp ( Phi, Reset,
RomSignLength,
RomStatus,
FracXFromRound,
XDest,
CMPDecoded, CMPEDecoded,
SignOpA, SignOpB,
notAbortWB, PreventSwap,
FpLd, FpOp,
NegateOprSign,
notSignAFromB, notSignBFromA,
OprRoundMode,
FpInst1,
Unimplemented,
SignResult,
AregSign, AregXORBreg,
FpExc_Unimp,
Status_6_2,
ConditionCodes,
OprSNnotDB, SNnotDB, DBnotSN,
MulLenSel,
RModeMinus,
FracRoundOut );
input Phi, Reset;
input [`end_sign_field:`start_sign_field] RomSignLength;
input [`end_status_field:`start_status_field] RomStatus;
input FracXFromRound; // Optimised signal
input XDest;
input SignOpA, SignOpB,
notAbortWB, PreventSwap,
FpLd, FpOp, NegateOprSign;
input notSignAFromB,
notSignBFromA,
FpInst1,
Unimplemented;
input [1:0] OprRoundMode;
input CMPDecoded, CMPEDecoded;
output SignResult, AregSign, AregXORBreg;
output FpExc_Unimp;
output [1:0] ConditionCodes;
output OprSNnotDB, SNnotDB, DBnotSN;
output [4:0]MulLenSel;
output RModeMinus;
output [4:0] FracRoundOut ;
output [6:2] Status_6_2;
wire notRN ;
wire [4:1] FracRound;
assign FracRoundOut = {FracRound[4:1], notRN} ;
wire [6:0] Status;
assign Status_6_2 = Status[6:2] ;
wire [1:0] U_RoundingMode;
SignLogic sl (Phi, Reset,
RomSignLength [`u_SignAregFromResult:`u_SignResultFromFunction0],
RomStatus[`u_Unimplemented],
Status[0], Status[1],
SignOpA, SignOpB,
NegateOprSign,
FpLd,
notAbortWB, PreventSwap,
U_RoundingMode[0],
Unimplemented,
notSignAFromB, notSignBFromA,
AregSign, AregXORBreg,
U_CouldBeRI_0, // Bent place to do but needs a lot of sign stuff
FpExc_Unimp,
ConditionCodes,
SignResult);
RoundModeLogic rml (Phi,
OprRoundMode,
FpLd,
notAbortWB,
CMPDecoded, CMPEDecoded,
RomSignLength [`u_SetRoundingModeToMinus],
RModeMinus,
U_RoundingMode);
LengthLogic ll (Phi, Reset,
FpInst1,
FpLd, FpOp,
RomSignLength[`u_ToggleLength],
notAbortWB,
OprSNnotDB,
SNnotDB,
U_SNnotDB,
DBnotSN,
MulLenSel);
DecodeStatus ds (RomStatus[`u_status3:`u_status0],
Status);
/* For the Rounding cycles make some of controls faster */
ME_AND2 v2 (U_RoundingMode[1], U_CouldBeRI_0, U_CouldBeRI);
ME_FD1_B x1 (Phi, U_CouldBeRI, CouldBeRI, );
ME_AND3_B s2 (U_RoundingMode[1], U_CouldBeRI_0, U_SNnotDB, U_CouldBeRISN);
ME_FD1_B x4 (Phi, U_CouldBeRISN, CouldBeRISN, );
ME_NOR2 v3 (U_RoundingMode[1], U_RoundingMode[0], U_CouldBeRN);
ME_FD1_B x2 (Phi, U_CouldBeRN, CouldBeRN, );
ME_AND2_B s1 (U_CouldBeRN, U_SNnotDB, U_CouldBeRNSN);
ME_FD1_B x3 (Phi, U_CouldBeRNSN, CouldBeRNSN, );
// FracXbus comes from Breg or a constant
// want to constuct constant as fields
// ie
// 2 1 23 1 28 1 2
//
// 00 0 000_00..00_0000 0 0000_00..00_0000 0 00 Zero
// 00 1 000_00..00_0000 0 0000_00..00_0000 0 00 One
// 00 0 000_00..00_0000 1 1111_11..11_1111 1 11 RC SN 2
// 00 0 000_00..00_0000 0 1111_11..11_1111 1 11 RC SN 1
// 00 0 000_00..00_0000 0 0000_00..00_0000 1 11 RC DB 2
// 00 0 000_00..00_0000 0 0000_00..00_0000 0 11 RC DB 1
// Field Names
// a b c d e f g
//
// a == 0
// b == FracXbusFrom1
// c == 0
// d == RI & SN
// e == (RI | RN) & SN
// f == RI | (RN & SN)
// g == RI | RN
// 00 = Round Nearest
// 01 = Round Zero ( Truncate )
// 10 = Round positive infinity
// 11 = Round negative infinity
// Round Nearest
ME_NAND2 rg4 (CouldBeRN, FracXFromRound, notRN);
ME_NAND2 rzz1s (CouldBeRNSN, FracXFromRound, notRNSN);
// Round Infinities //
ME_NAND2 rv2 (CouldBeRI, FracXFromRound, notRI);
ME_NAND2 rv3 (CouldBeRISN, FracXFromRound, notRISN);
// Constant d
ME_INV_B rlokout (notRISN, FracRound[4]);
// Constant e
ME_AND2_B s3 (U_RoundingMode[1], U_SNnotDB, U_RMode1SN);
ME_AND2_B s4 (U_RMode1SN, U_CouldBeRI_0, U_CouldBeRISNa);
ME_OR2 rc0 (U_CouldBeRNSN, U_CouldBeRISNa, U_constante);
ME_FD1_B rc1 (Phi, U_constante, r_constante, );
ME_NAND2_B rv03 (r_constante, XDest, notConstante);
//ME_AND2_B rvo3 (notRNSN, notRISN, notConstante);
ME_INV_D rvo4 (notConstante, FracRound[3]); // Has fanout of 28
// Constant f
ME_NAND2_B rvo2 (notRNSN, notRI, FracRound[2]);
// Constant g
ME_NAND2_B rvo1 (notRI, notRN, FracRound[1]);
// FracRound[4:1] Constantd, Constante, Constantf, Constantg,
// FracRound[0] = notRN
endmodule
|
module SignLogic (Phi, Reset,
RomSignLength,
Rom_Unimplemented,
Rom_StatusCCBit0, Rom_StatusCCBit1,
SignOpA, SignOpB,
NegateOprSign,
LoadOprs,
notAbortWB, PreventSwap,
U_RoundingMode0,
Unimplemented,
notSignAFromB, notSignBFromA,
AregSign, AregXORBreg,
U_CouldBeRI_0,
FpExc_Unimp,
ConditionCodes,
SignResult);
input Phi, Reset;
input [`u_SignAregFromResult:`u_SignResultFromFunction0]RomSignLength;
input Rom_StatusCCBit0, Rom_StatusCCBit1, Rom_Unimplemented;
input SignOpA, SignOpB,
LoadOprs,
notAbortWB,
PreventSwap,
U_RoundingMode0, // Unlatched rounding mode bit 0
NegateOprSign;
input Unimplemented;
input notSignAFromB,
notSignBFromA;
output AregSign,
AregXORBreg,
U_CouldBeRI_0, // Unlatched for next cycle
SignResult;
output FpExc_Unimp;
output [1:0] ConditionCodes;
ME_TIEOFF toff (vdd, gnd);
// ***************************************//
// Sign function //
// ***************************************//
// Bits Function
// 0 0 Areg
// 0 1 Positive // Forced on reset
// 1 0 notAreg
// 1 1 AregXORBreg
ME_OR2 orr (Reset, RomSignLength[`u_SignResultFromFunction0],
SignResCtl0);
ME_XOR2 xorabs (AregSign, BregSign, AregXORBreg);
ME_MUX4B msc0 (SignResCtl0, RomSignLength[`u_SignResultFromFunction1],
AregSign, gnd, notAregSign, AregXORBreg,
SignResult);
// ***************************************//
// Sign Registers //
// ***************************************//
ME_XOR2 xorop (SignOpA, NegateOprSign, SignedSignOpA);
ME_INV_A salc (notSignAFromB, SignAFromB);
ME_OR4 ggdf (RomSignLength[`u_SignAregFromResult], Reset,
SignAFromB, LoadOprs, PosAEn);
ME_NAND2 sae1 ( PosAEn, notAbortWB, notAregLoadEn_p);
//ME_OR2_B sae2 ( notAregLoadEn_p, PreventSwap, notSignAregLoadEn);
ME_MUX2B saop ( RomSignLength[`u_SignAregFromResult], BregSign, SignResult, JSign);
ME_NMUX2B saxp ( LoadOprs, JSign, SignedSignOpA, notSignAInput);
ME_MUX2B_B asmp ( notAregLoadEn_p, notSignAInput, notAregSign, notSignAInput_p );
ME_NMUX2B_B asm ( notPreventSwap, notAregSign, notSignAInput_p, U_AregSign );
ME_FD1_B asf ( Phi, U_AregSign, AregSign, notAregSign );
// Added a bit of tack to see the rounding mode earlier
ME_XNOR2_B u0_v1 ( U_RoundingMode0, notSignAInput_p, U_RM0_notSAI);
ME_XNOR2_B u0_v2 ( U_RoundingMode0, notAregSign, U_RM0_notSA);
ME_NMUX2B_B asmv ( PreventSwap, U_RM0_notSAI, U_RM0_notSA, U_CouldBeRI_0 );
ME_INV_A sblc ( notSignBFromA, SignBFromA);
ME_OR2 gbdf ( SignBFromA, LoadOprs, PosBEn);
ME_INV_A sbe2 ( PreventSwap, notPreventSwap);
ME_NAND3 sbe ( PosBEn, notAbortWB, notPreventSwap, notSignBregLoadEn);
ME_NMUX2B sbxp ( LoadOprs, AregSign, SignOpB, notSignBInput);
ME_NMUX2B bsm ( notSignBregLoadEn, notSignBInput, notBregSign, U_BregSign );
ME_FD1 bsf ( Phi, U_BregSign, BregSign, notBregSign );
// ***************************************//
// Exception and Condition Code //
// ***************************************//
ME_OR2 codie (Unimplemented, Rom_Unimplemented, FpExc_Unimp);
ME_NOR2 stg7 (Rom_StatusCCBit0, Rom_StatusCCBit1,
Equals);
ME_NOR2 stg8 (Rom_StatusCCBit0, BregSign, notNegative);
ME_NOR2 stg9 (Rom_StatusCCBit0, notBregSign, notPositive);
ME_NOR2 stgA (Equals, notPositive, ConditionCodes[1]);
ME_NOR2 stgB (Equals, notNegative, ConditionCodes[0]);
endmodule
|
module TregLoadCtl (RomFracTFromRes, notAbortWB,
FracTregLoadEn);
input RomFracTFromRes, notAbortWB;
output FracTregLoadEn;
ME_AND2 ftlt (RomFracTFromRes, notAbortWB, FracTregLoadEn);
endmodule
|
module YMuxCtl (RomYMuxCtl,
YFunc,
FracAregFPMSBP1,
notFracAregFPMSBP1,
FracBregSign,
DivMultiple,
AregLSBs,
StickyForSR1,
TregLSBs,
/* dhn--01/10/91 notFracYFromD1, notFracYFromD2, notFracYFromD3, */
notFracYFromD1A, notFracYFromD2A, notFracYFromD3A,
FracYLSBs);
input FracAregFPMSBP1, notFracAregFPMSBP1, FracBregSign;
input [`end_frac_ybus_field:`start_frac_ybus_field] RomYMuxCtl;
input [6:0] YFunc;
input [2:0] AregLSBs;
input StickyForSR1;
input [1:0] TregLSBs;
input [3:1] DivMultiple;
/* dhn--01/10/91 output notFracYFromD3, notFracYFromD2, notFracYFromD1; */
output notFracYFromD1A, notFracYFromD2A, notFracYFromD3A;
output [1:0] FracYLSBs;
ME_TIEOFF toff (vdd, gnd);
/* Function Coding on
Func1 Func0
0 0 ROM Ybus From ROM
0 1 ROM SQRT Ybus From ROM Note we dont do anything with the Ybus here
1 0 Round Ybus from Areg or AregSR1 dependant on FracAregFPMSBP1
1 1 Div Ybus From Div Multiple
*/
//YFunc[6] and RomYMuxCtl[`u_FracALUOpForDivOrSQRTStep] mean SQRT step
ME_AND3_B fs3 (YFunc[6], RomYMuxCtl[`u_FracALUOpForDivOrSQRTStep], FracBregSign, RomYFromSQRTBNeg);
/* *************************************************************
YMux Drivers
************************************************************* */
//ME_INV_A ifp (FracAregFPMSBP1, notFracAregFPMSBP1);
/*ME_MUX4B_B ym0 (RomYMuxCtl[`u_FracYbusFromFunc0], RomYMuxCtl[`u_FracYbusFromFunc1],
RomYMuxCtl[`u_FracYbusFromRomDest0],
RomYMuxCtl[`u_FracYbusFromRomDest0],
FracAregFPMSBP1,
DivMultiple[0], FracYFromD0);
ME_MUX4B_B ym1 (RomYMuxCtl[`u_FracYbusFromFunc0], RomYMuxCtl[`u_FracYbusFromFunc1],
RomYMuxCtl[`u_FracYbusFromRomDest1],
RomYMuxCtl[`u_FracYbusFromRomDest1],
notFracAregFPMSBP1,
DivMultiple[1], FracYFromD1);*/
/*ME_MUX4B_B ym0 (YFunc[0], YFunc[1],
RomYMuxCtl[`u_FracYbusFromRomDest0],
RomYMuxCtl[`u_FracYbusFromRomDest0],
FracAregFPMSBP1,
DivMultiple[0], FracYFromD0);
ME_MUX4B_B ym1 (YFunc[2], YFunc[3],
RomYMuxCtl[`u_FracYbusFromRomDest1],
RomYMuxCtl[`u_FracYbusFromRomDest1],
notFracAregFPMSBP1,
DivMultiple[1], FracYFromD1);*/
/*** dhn--01/10/91
ME_A222OI_B ym1 (YFunc[0],
RomYMuxCtl[`u_FracYbusFromAregSR1],
YFunc[1],
FracAregFPMSBP1,
YFunc[2],
DivMultiple[1],
notFracYFromD1);
ME_A222OI_B ym2 (YFunc[3],
RomYMuxCtl[`u_FracYbusFromAreg],
YFunc[4],
notFracAregFPMSBP1,
YFunc[5],
DivMultiple[2],
notFracYFromD2);
ME_A222OI_B ym3 (RomYMuxCtl[`u_FracYbusFromFunc0],
RomYMuxCtl[`u_FracYbusFromTreg],
RomYMuxCtl[`u_FracYbusFromFunc1],
gnd,
RomYMuxCtl[`u_FracYbusFromFunc2],
DivMultiple[3],
notFracYFromD3);
*** dhn--01/10/91 ***/
ME_A222OI_B ym4 (YFunc[0],
RomYMuxCtl[`u_FracYbusFromAregSR1],
YFunc[1],
FracAregFPMSBP1,
YFunc[2],
DivMultiple[1],
notFracYFromD1A);
ME_A222OI_B ym5 (YFunc[3],
RomYMuxCtl[`u_FracYbusFromAreg],
YFunc[4],
notFracAregFPMSBP1,
YFunc[5],
DivMultiple[2],
notFracYFromD2A);
ME_A222OI_B ym6 (RomYMuxCtl[`u_FracYbusFromFunc0],
RomYMuxCtl[`u_FracYbusFromTreg],
RomYMuxCtl[`u_FracYbusFromFunc1],
gnd,
RomYMuxCtl[`u_FracYbusFromFunc2],
DivMultiple[3],
notFracYFromD3A);
/* ****************************************************************************
Modify FracYbus LSBs for Negative SQRT step and Sticky
**************************************************************************** */
ME_INV_A ymlb1 (notFracYFromD1A, FracYFromD1); // Minimalist light load
ME_INV_A ymlb2 (notFracYFromD2A, FracYFromD2); // Minimalist light load
ME_INV_A ymlb3 (notFracYFromD3A, FracYFromD3); // Minimalist light load
/*ME_OR2 ymd0 (FracYFromD1, FracYFromD3, FracYFromD0C);
ME_OR2 ymd1 (FracYFromD2, FracYFromD3, FracYFromD1C);*/
// Do OR before MUX
wire [1:0] OR_AregLSBsSR1, OR_AregLSBs, OR_TregLSBs;
// Bit 0
ME_INVA i00 (RomYMuxCtl[`u_FracYbusOrSticky], notRomFracYbusOrSticky);
/*ME_OR2 i00 (StickyInForSR1, RomYMuxCtl[`u_FracYbusOrSticky], OR_AregLSBsSR1[0]);
ME_OR2 i01 (AregLSBs[0], RomYMuxCtl[`u_FracYbusOrSticky], OR_AregLSBs[0]);
ME_OR2 i02 (TregLSBs[0], RomYMuxCtl[`u_FracYbusOrSticky], OR_TregLSBs[0]);*/
// Bit 1
ME_INVA i10 (RomYFromSQRTBNeg, notRomYFromSQRTBNeg);
/*ME_OR2 i10 (AregLSBs[2], RomYFromSQRTBNeg, OR_AregLSBsSR1[1]);
ME_OR2 i11 (AregLSBs[1], RomYFromSQRTBNeg, OR_AregLSBs[1]);
ME_OR2 i12 (TregLSBs[1], RomYFromSQRTBNeg, OR_TregLSBs[1]);*/
// Use buffered inverse of mux controls
ME_NAND2 ymlsbs1 (FracYFromD1, StickyForSR1, t0);
ME_NAND2 ymlsbs2 (FracYFromD2, AregLSBs[0], t1);
ME_NAND2 ymlsbs3 (FracYFromD3, TregLSBs[0], t2);
ME_NAND4 ymlsbs4 (t0, t1, t2, notRomFracYbusOrSticky, FracYLSBs[0]);
ME_NAND2 ymlsbs5 (FracYFromD1, AregLSBs[2], t3);
ME_NAND2 ymlsbs6 (FracYFromD2, AregLSBs[1], t4);
ME_NAND2 ymlsbs7 (FracYFromD3, TregLSBs[1], t5);
ME_NAND4 ymlsbs8 (t3, t4, t5, notRomYFromSQRTBNeg, FracYLSBs[1]);
/*ME_MUX4B yb0 (FracYFromD0C, FracYFromD1C,
RomYMuxCtl[`u_FracYbusOrSticky],
OR_AregLSBsSR1[0],
OR_AregLSBs[0],
OR_TregLSBs[0],
FracYLSBs[0]);
ME_MUX4B yb1 (FracYFromD0C, FracYFromD1C,
RomYFromSQRTBNeg,
OR_AregLSBsSR1[1],
OR_AregLSBs[1],
OR_TregLSBs[1],
FracYLSBs[1]);*/
endmodule
|
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.