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1.05M
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module fp_exp ( ss_clock, SNnotDB, OprSNnotDB,
RS2_exp, RS1_exp,
FracAregForInt,
notSLFromNorm,
ShiftBy8,
ExpAregLoadEn, ExpAregLC0, ExpAregLC1,
ExpBregLoadEn, ExpBregLC0, ExpBregLC1,
ExpXCtl0, ExpXCtl1,
ExpYCtl0, ExpYCtl1,
Sub, CarryIn,
Constantb, Constantc, Constantd, Constante,
Constantf, Constantg, Constanth,
// output start here
AregMasterBufOut,
ExpResultBuf, notExpShiftResult,
ExpZero, ExpResult_12,
SLControl,
notAInfNaN, notAZeroDenorm,
notBInfNaN, notBZeroDenorm,
notUnderflow, notOverflow, notExpException,
ss_scan_mode, fp_exp_scan_in, fp_exp_scan_out);
input ss_clock, SNnotDB, OprSNnotDB ;
input [10:0] RS2_exp, RS1_exp ;
input [7:0] FracAregForInt;
input ExpAregLoadEn, ExpAregLC0, ExpAregLC1;
input ExpBregLoadEn, ExpBregLC0, ExpBregLC1;
input ExpXCtl0, ExpXCtl1 ;
input ExpYCtl0, ExpYCtl1 ;
input Sub, CarryIn;
input Constantb, Constantc, Constantd, Constante,
Constantf, Constantg, Constanth;
input [3:0] notSLFromNorm ;
input ShiftBy8;
input ss_scan_mode, fp_exp_scan_in;
output [3:0] SLControl ;
output [7:0] AregMasterBufOut;
output [10:0] ExpResultBuf ;
output [12:0] notExpShiftResult ;
output ExpZero;
output ExpResult_12;
output notAInfNaN, notAZeroDenorm;
output notBInfNaN, notBZeroDenorm;
output notUnderflow, notOverflow, notExpException;
output fp_exp_scan_out;
ME_TIEOFF toff (vdd, gnd);
assign fp_exp_scan_out = 1'bx ;
wire [12:0] int_ExpResultBuf ;
assign ExpResultBuf = int_ExpResultBuf[10:0] ;
wire [12:0] AregMaster, AregMasterBuf, BregMaster, BregMasterBuf,
ExpXbus, ExpYbus, ExpResult;
wire [3:0] ExpYbusS;
assign ExpResult_12 = ExpResult[12] ;
// extended internal format operands
wire [12:0] OprA, OprB ;
wire [10:0] ExpOpA, ExpOpB ;
// Operand select (single/double) muxes
ME_MUX_2B_11 opifaxe (OprSNnotDB,
RS2_exp[10:0],
{gnd, gnd, gnd, RS2_exp[10:3]},
ExpOpA[10:0]);
assign OprA = {gnd, gnd, ExpOpA};
ME_MUX_2B_11 opifbxe (OprSNnotDB,
RS1_exp[10:0],
{gnd, gnd, gnd, RS1_exp[10:3]},
ExpOpB[10:0]);
assign OprB = {gnd, gnd, ExpOpB};
NormCalLog nmcl (notSLFromNorm,
ShiftBy8,
ExpYCtl0, ExpYCtl1,
ExpYbus[3:0],
ExpYbusS[3:0],
SLControl);
//wire [7:0] AregMasterBufOut = AregMasterBuf[7:0];
con1 g0 (AregMasterBuf[0], AregMasterBufOut[0]);
con1 g1 (AregMasterBuf[1], AregMasterBufOut[1]);
con1 g2 (AregMasterBuf[2], AregMasterBufOut[2]);
con1 g3 (AregMasterBuf[3], AregMasterBufOut[3]);
con1 g4 (AregMasterBuf[4], AregMasterBufOut[4]);
con1 g5 (AregMasterBuf[5], AregMasterBufOut[5]);
con1 g6 (AregMasterBuf[6], AregMasterBufOut[6]);
con1 g7 (AregMasterBuf[7], AregMasterBufOut[7]);
ME_FREGA_S_4_13 Areg ( ss_clock,
ExpAregLoadEn, ExpAregLC0, ExpAregLC1,
OprA,
{gnd, gnd, gnd, gnd, gnd, FracAregForInt[7:0]}, // AIntVal
int_ExpResultBuf, BregMasterBuf,
AregMaster, AregMasterBuf);
Exception ae ( AregMasterBuf, SNnotDB, notAInfNaN, notAZeroDenorm);
ME_MUX_4B_13 Ymux (ExpYCtl0, ExpYCtl1,
{gnd, gnd, gnd, gnd, gnd,
gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd}, // Zero
{gnd, gnd, gnd, gnd, gnd,
gnd, gnd, gnd, gnd, vdd, gnd, gnd, gnd}, // Normaliser value of 8
AregMasterBuf,
{gnd, gnd, gnd, Constantb, Constantb, Constantb, Constantc,
Constantc, Constantd, Constante, Constantf, Constantg, Constanth}, // Constant
ExpYbus );
ME_FREGA_S_4_13 Breg (ss_clock,
ExpBregLoadEn, ExpBregLC0, ExpBregLC1,
OprB,
{int_ExpResultBuf[12], int_ExpResultBuf[12:1]}, // ExpResultSR1
int_ExpResultBuf, AregMasterBuf,
BregMaster, BregMasterBuf);
Exception be (BregMasterBuf, SNnotDB, notBInfNaN, notBZeroDenorm);
ME_MUX_4B_13 Xmux (ExpXCtl0, ExpXCtl1,
{gnd, gnd, gnd, gnd, gnd,
gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd}, // Zero
{gnd, gnd, gnd, Constantb, Constantb, Constantb, Constantc,
Constantc, Constantd, Constante, Constantf, Constantg, Constanth}, // Constant
AregMasterBuf, BregMasterBuf,
ExpXbus );
ME_ADD_13 add ( Sub, CarryIn, ExpXbus, {ExpYbus[12:4], ExpYbusS[3:0]}, ExpResult, int_ExpResultBuf, ExpZero);
// original Meiko code (changed 11/7/90 -- dhn):
// shiftsub adds ( BregMaster, AregMaster, notExpShiftResult);
//
//ME_ADD_13 adds ( 1'b1, 1'b0, AregMaster, BregMaster, notExpShiftResult,,);
// just use the subtractor, don't need the condition codes, etc.
ME_SUB_13 subtract13 ( 1'b1, 1'b0, AregMaster, BregMaster, notExpShiftResult );
ResultException re (ExpResult, SNnotDB, ExpZero, notUnderflow, notOverflow, notExpException);
endmodule
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module Exception (BM, SNnotDB, notBInfNaN, notBZeroDenorm);
input [12:0] BM;
input SNnotDB;
output notBInfNaN, notBZeroDenorm;
// Check the Master for InfNan or ZeroDenorm
// Inf or nan should also be set for any overflow, either single or
// double length, as this check is also used in rounding
ME_OR11 g10 (BM[10], BM[9], BM[8], BM[7], BM[6], BM[5],
BM[4], BM[3], BM[2], BM[1], BM[0], notBZeroDenorm );
// Force bits 10 to 8 high when single and AND them
ME_INVA g13 ( SNnotDB, DBnotSN );
ME_NAND3 g12 ( BM[10], BM[9], BM[8], n10 ) ;
ME_NAND2 g11 ( DBnotSN, n10, doublebits1 ) ;
ME_AND8 zxd ( BM[7], BM[6], BM[5], BM[4],
BM[3], BM[2], BM[1], BM[0], All1s7to0);
ME_OR3 zxe ( BM[10], BM[9], BM[8], Bit10Or8);
ME_NAND2 g23 ( SNnotDB, Bit10Or8, notSNGrossOv ) ;
ME_NAND2 g22 ( doublebits1, All1s7to0, notAll1s ) ;
ME_INV_A g21 ( BM[11], notBit11 ) ;
ME_AND3_B g20 ( notSNGrossOv, notAll1s, notBit11, notBInfNaN ) ;
endmodule
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module NormCalLog (notSLFromNorm[3:0],
ShiftBy8,
ExpYCtl0, ExpYCtl1,
ExpYbus[3:0],
ExpYbusS[3:0],
SLControl);
input [3:0] notSLFromNorm;
input ShiftBy8;
input ExpYCtl0, ExpYCtl1;
input [3:0] ExpYbus;
output [3:0] ExpYbusS;
output [3:0]SLControl;
wire [3:0] notExpYbus;
wire [3:0] notSLControl ;
ME_INVA i0 (ExpYCtl1, notExpYCtl1);
ME_INVA i1 (ShiftBy8, notShiftBy8);
ME_NAND3 n0 (ExpYCtl0, notExpYCtl1, notShiftBy8, notUseFastNorm);
ME_INV_B i2 (ExpYbus[0], notExpYbus[0]);
ME_INV_B i3 (ExpYbus[1], notExpYbus[1]);
ME_INV_B i4 (ExpYbus[2], notExpYbus[2]);
ME_INV_B i5 (ExpYbus[3], notExpYbus[3]);
ME_NMUX2B_B i33 (notUseFastNorm, notSLFromNorm[3], notExpYbus[3], ExpYbusS[3]);
ME_NMUX2B_B i32 (notUseFastNorm, notSLFromNorm[2], notExpYbus[2], ExpYbusS[2]);
ME_NMUX2B_B i31 (notUseFastNorm, notSLFromNorm[1], notExpYbus[1], ExpYbusS[1]);
ME_NMUX2B_B i30 (notUseFastNorm, notSLFromNorm[0], notExpYbus[0], ExpYbusS[0]);
ME_INV_A i6 (ExpYbusS[0], notSLControl[0]);
ME_INV_A i7 (ExpYbusS[1], notSLControl[1]);
ME_INV_A i8 (ExpYbusS[2], notSLControl[2]);
ME_INV_A i9 (ExpYbusS[3], notSLControl[3]);
ME_INV_A ia (notSLControl[0], SLControl[0]);
ME_INV_A ib (notSLControl[1], SLControl[1]);
ME_INV_A ic (notSLControl[2], SLControl[2]);
ME_INV_A id (notSLControl[3], SLControl[3]);
endmodule
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module ResultException (Result, SNnotDB, ExpZero, notUnderflow, notOverflow, notExpException);
input [`ExpMSB:0] Result;
input ExpZero;
input SNnotDB;
output notUnderflow, notOverflow, notExpException;
ME_TIEOFF toff (vdd, );
ME_INV_B g30 ( Result[12], positive ) ;
ME_INV_A g31 ( SNnotDB, DBnotSN ) ;
// underflow condition is -ve or all zero.
// Note that exp must be subtracting for zero to work !
ME_NMUX2B zq1 (positive, vdd, ExpZero, notUnderflow );
// overflow condition is positive and all ones with LSB dont care.
// or positive with bit 11 set.
// n.b all ones applies only over required length.
// Force bits 10 to 8 high when single and AND them
ME_NAND3 g10 (Result[10], Result[9], Result[8], n10 ) ;
ME_NAND2 g11 (DBnotSN, n10, doublebits1 ) ;
ME_AND4 zzd (Result[7], Result[6], Result[5], Result[4], All1s7to4);
ME_AND4_B zze (positive, Result[3], Result[2], Result[1], PAll1s3to1);
ME_OR3_B zzf ( Result[10], Result[9], Result[8], Bit10Or8);
ME_NAND3_B g23 ( positive, SNnotDB, Bit10Or8, notSNGrossOv ) ;
ME_NAND3_B g22 ( doublebits1, All1s7to4, PAll1s3to1, notAll1s ) ;
ME_NAND2 g21 ( positive, Result[11], notBit11 ) ;
ME_AND3_B g20 ( notSNGrossOv, notAll1s, notBit11, notOverflow ) ;
ME_AND4_B g24 ( notUnderflow, notSNGrossOv, notAll1s, notBit11, notExpException ) ;
endmodule
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module AdderLSBlog ( Rom_Sub,
Rom_DivStepSQRT,
notBregSign, Eqv,
notFracRNearest,
TrueIEEEAregLSB,
notSub, AdderCarryIn,
notFracZero, FracZero);
input Rom_Sub,
Rom_DivStepSQRT,
notBregSign, Eqv;
input notFracRNearest,
TrueIEEEAregLSB;
output notSub, AdderCarryIn,
notFracZero, FracZero;
ME_TIEOFF toff (vdd, gnd);
ME_NMUX2B_B g12 (Rom_DivStepSQRT, Rom_Sub, notBregSign, notSub);
ME_INV_A g13 (notSub, Sub);
ME_MUX2B g15 (notFracRNearest, TrueIEEEAregLSB, Sub, AdderCarryIn);
// Optimise
// ME_AND2 g14 (Eqv, Sub, notFracZero); // this is neccessary for no-zero on add
ME_NMUX2B g16 (notSub, Eqv, gnd, notFracZero); // this is neccessary for no-zero on add
ME_INVA g17 (notFracZero, FracZero);
endmodule
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module AregInexactSlice (AM, notAM31_3, notAM2_0);
input [31:0] AM;
output notAM31_3, notAM2_0;
wire [11:4] notAORed;
ME_NOR3 aig0 (AM[0], AM[1], AM[2], notAM2_0);
ME_NOR2 aig5 (AM[30], AM[31], notAORed[11]);
ME_NOR3 aig6 (AM[27], AM[28], AM[29], notAORed[10]);
ME_NOR4 ai54 (AM[25], AM[26], AM[23], AM[24], notAORed[9]);
ME_NOR4 ai44 (AM[21], AM[22], AM[19], AM[20], notAORed[8]);
ME_NOR4 ai34 (AM[17], AM[18], AM[15], AM[16], notAORed[7]);
ME_NOR4 ai24 (AM[13], AM[14], AM[11], AM[12], notAORed[6]);
ME_NOR4 ai14 (AM[9], AM[10], AM[7], AM[8], notAORed[5]);
ME_NOR4 ai04 (AM[5], AM[6], AM[3], AM[4], notAORed[4]);
ME_NAND4 ai27 (notAORed[8], notAORed[9], notAORed[10], notAORed[11], AM31_19);
ME_NAND4 ai17 (notAORed[4], notAORed[5], notAORed[6], notAORed[7], AM18_3);
ME_NOR2 aizz (AM31_19, AM18_3, notAM31_3);
endmodule
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module AregLSBLog (AregSticky,
AregLSBSN,
AregLSBDB,
AregFPMSBP1,
SNnotDB,
TrueIEEEAregLSB,
StickyForSR1);
input [1:0] AregSticky; // Two LSBs of Areg
input [1:0] AregLSBSN; // Two LSBs of Areg for IEEE single length
input [1:0] AregLSBDB; // Two LSBs of Areg for IEEE double length
input AregFPMSBP1; // Fraction overflow bit (ie 4.0 < Areg =< 2.0)
input SNnotDB;
output TrueIEEEAregLSB;
output StickyForSR1;
ME_OR2 v1 (AregSticky[1], AregSticky[0], StickyForSR1);
ME_MUX4B asdf (SNnotDB, AregFPMSBP1,
AregLSBDB[0], AregLSBSN[0],
AregLSBDB[1], AregLSBSN[1],
TrueIEEEAregLSB);
endmodule
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module CheckOverflow (FracResult, notPossibleOv, SubResultNorm);
input [10:1] FracResult;
output notPossibleOv, SubResultNorm;
// PossibleOv = (AResult[8:1] == 8'hFF)
// Check that an overflow is not possible on rounding cycle
// This can only occur if a large number of ones occur in the
// unrounded result
ME_NAND8_B g10 (FracResult[8], FracResult[7], FracResult[6], FracResult[5], FracResult[4],
FracResult[3], FracResult[2], FracResult[1], notPossibleOv);
ME_OR3_B srgx (FracResult[10], FracResult[9], FracResult[8], SubResultNorm);
endmodule
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module CSArray (
// ctl inputs
Shift,
Pos,
Zero,
// inputs
SumIn,
CarryIn,
Breg,
// ctl output
SALSBs, SBLSBs, SCLSBs,
CALSB, CBLSB, CCLSB,
// outputs
SD,
CD[`FracMSB:2]);
input [3:0] Shift, Pos, Zero;
input [`FracMSB:3] CarryIn, SumIn;
input [`FracMSB:1] Breg;
output [2:1] SALSBs, SBLSBs, SCLSBs;
output CALSB, CBLSB, CCLSB;
output [`FracMSB:1] SD;
output [1+`FracMSB:2] CD;
wire [`FracMSB:1] SA, SB, SC; // For cs in line expansion
wire [1+`FracMSB:2] CA, CB, CC;
CS_STAGE_57 asdc ({SumIn[`FracMSB], SumIn[`FracMSB], SumIn[`FracMSB:3]},
{CarryIn[`FracMSB], CarryIn[`FracMSB], CarryIn[`FracMSB:3]},
Breg, Shift[0], Pos[0], Zero[0],
{SA[`FracMSB:3], SALSBs[2:1]}, {CA[1+`FracMSB:3], CALSB});
CS_STAGE_57 asdd ({SA[`FracMSB], SA[`FracMSB], SA[`FracMSB:3]},
{CA[`FracMSB], CA[`FracMSB], CA[`FracMSB:3]},
Breg, Shift[1], Pos[1], Zero[1],
{SB[`FracMSB:3], SBLSBs[2:1]}, {CB[1+`FracMSB:3], CBLSB});
CS_STAGE_57 asde ({SB[`FracMSB], SB[`FracMSB], SB[`FracMSB:3]},
{CB[`FracMSB], CB[`FracMSB], CB[`FracMSB:3]},
Breg, Shift[2], Pos[2], Zero[2],
{SC[`FracMSB:3], SCLSBs[2:1]}, {CC[1+`FracMSB:3], CCLSB});
CS_STAGE_57 asdf ({SC[`FracMSB], SC[`FracMSB], SC[`FracMSB:3]},
{CC[`FracMSB], CC[`FracMSB], CC[`FracMSB:3]},
Breg, Shift[3], Pos[3], Zero[3],
SD, CD);
endmodule
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module CSRegSlice (Phi,
InitialMulStep,
/* notInitialSumZero, */
InitialCarryBit,
SumCarryLoadEn,
SumOut, CarryOut,
BregIn,
SumIn, CarryIn);
input Phi;
input InitialMulStep,
/* notInitialSumZero, */
InitialCarryBit,
SumCarryLoadEn;
input [`FracMSB:0] SumOut, CarryOut;
input [`FracMSB:1] BregIn;
output [`FracMSB:0] SumIn, CarryIn;
wire [`FracMSB:0] SumReg, CarryReg, InitialSum;
ME_TIEOFF toff (vdd, gnd);
ME_FREGA_1_58 sr (Phi, SumCarryLoadEn, SumOut, SumReg);
ME_FREGA_1_58 cr (Phi, SumCarryLoadEn, CarryOut, CarryReg);
/* ME_NMUX_2B_58 iz (notInitialSumZero, */
ME_NMUX_2B_58 iz (InitialCarryBit,
{vdd, vdd, vdd, vdd, vdd, vdd, vdd, vdd, vdd, vdd, vdd, vdd, vdd, vdd,
vdd, vdd, vdd, vdd, vdd, vdd, vdd, vdd, vdd, vdd, vdd, vdd, vdd, vdd,
vdd, vdd, vdd, vdd, vdd, vdd, vdd, vdd, vdd, vdd, vdd, vdd, vdd, vdd,
vdd, vdd, vdd, vdd, vdd, vdd, vdd, vdd, vdd, vdd, vdd, vdd, vdd, vdd,
vdd, vdd}, // 58'h3FF_FFFF_FFFF_FFFF
{BregIn, vdd},
InitialSum);
ME_MUX_2B_58 si (InitialMulStep, SumReg, InitialSum, SumIn);
ME_MUX_2B_58 ci (InitialMulStep,
CarryReg,
{gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd,
gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd,
gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd,
gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, // 56'h0
InitialCarryBit, gnd},
CarryIn);
endmodule
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module fp_frac
(ss_clock,
FracAregLoadEn, FracAregLC,
FracBregLoadEn, FracBregLC,
FracCregLoadEn, FracCregLC,
FracTregLoadEn,
FracYbusLSBs,
InFromCregOr0, InForCreg, InForCregDB,
Constantb, Constantd, Constante, Constantf, Constantg, Constanth,
RS2_frac, RS1_frac,
SNnotDB, OprSNnotDB,
SRControl, SROneMore, SRToSticky,
SLControl,
LIB,
TopBitsIn,
notStickyInForSR, // For right
Shift, Pos, Zero, InitialMulStep,
/* notInitialSumZero, */
InitialCarryBit,
SumCarryLoadEn,
MulLenSel,
SumOut0, CarryOut0, CarryOut3,
LeftnotRight, FracALUOpSub, FracALUOpDiv,
notFracYFromD1, notFracYFromD2, notFracYFromD3,
/* notFracYFromD1A, notFracYFromD2A, notFracYFromD3A, */ //Copies
FracXFromB,
//ctl outputs
notSticky4, Sticky2, notSticky1, StickyExtra,
Creg_30_29, // CregSNBits = Creg[30:29]
Creg_56_55, // CregInSL2SQRT = Creg[56:55]
BregMaster_57, // FracBregSign
BregMaster_54, // BregFPMSBM1
notMultip,
notAM31_3, notAM2_0, // Inexact parts
StickyForSR1,
AregMaster_57_40, // AregMaster[57:40]
AregMaster_32, // AregMaster[32]
AregMaster_7_0, // AregMaster[7:0]
/* duplicate port--AregMasterFPMSBP1, */ // AregMasterBuf[56]
notAregMasterFPMSBP1,
Treg_1_0, // TregLSBs
SumInLSBs, CarryInLSBs,
SALSBs, SBLSBs, SCLSBs, // LSBs for cs array
CALSB , CBLSB , CCLSB ,
notFracZero, FracZero,
FracResult_57, // FracSign
SubResultNorm,
FracResult_56, // FracOverflow
FracResult_55_52, // StepRemBits
notPossibleOv,
FracResultBufout, // only bits [54:3] are used in result
ss_scan_mode, fp_frac_scan_in, fp_frac_scan_out);
input ss_clock;
input FracAregLoadEn;
input [2:0] FracAregLC;
input FracBregLoadEn;
input [2:0] FracBregLC;
input [1:0] FracYbusLSBs;
input FracCregLoadEn, FracCregLC,
FracTregLoadEn;
input [54:0] RS2_frac, RS1_frac;
input SNnotDB, OprSNnotDB;
input Constantb, Constantd, Constante, Constantf, Constantg, Constanth;
input [1:0] InFromCregOr0;
input [1:0] InForCreg,
InForCregDB;
input [3:0] SRControl, SLControl;
input [2:0] LIB;
input SROneMore, SRToSticky;
input [8:0] TopBitsIn;
input notStickyInForSR;
input [3:0] Shift, Pos, Zero;
input InitialMulStep,
/* notInitialSumZero, */
InitialCarryBit,
SumCarryLoadEn;
input LeftnotRight, FracALUOpSub, FracALUOpDiv;
input [4:0] MulLenSel;
input SumOut0, CarryOut0, CarryOut3;
input notFracYFromD1, notFracYFromD2, notFracYFromD3,
/* input notFracYFromD1A, notFracYFromD2A, notFracYFromD3A, */
FracXFromB;
input ss_scan_mode, fp_frac_scan_in;
output [3:0] notSticky4;
output [1:0] Sticky2;
output notSticky1;
output [1:0] StickyExtra;
output [8:0] notMultip;
output [1:0] Treg_1_0;
output [1:0] Creg_30_29;
output [1:0] Creg_56_55;
output StickyForSR1;
output [17:0] AregMaster_57_40;
output AregMaster_32;
output [ 7:0] AregMaster_7_0;
output notAM31_3, notAM2_0;
output BregMaster_54;
output BregMaster_57;
output notFracZero, FracZero;
output [3:0] FracResult_55_52;
output FracResult_57, FracResult_56;
output notAregMasterFPMSBP1;
output SubResultNorm;
output [54:3] FracResultBufout;
output [2:0] SumInLSBs,
CarryInLSBs;
output [1:0] SALSBs, SBLSBs, SCLSBs;
output CALSB , CBLSB , CCLSB ;
output notPossibleOv ;
output fp_frac_scan_out;
ME_TIEOFF toff (vdd, gnd);
// commented this out --
//assign fp_frac_scan_out = 1'bx ;
wire AregMasterFPMSBP1;
wire [57:0] AregMaster, AregMasterBuf;
assign AregMaster_57_40 = AregMaster[57:40] ;
assign AregMaster_32 = AregMaster[32] ;
assign AregMaster_7_0 = AregMaster[7:0] ;
wire [57:0] BregMaster;
assign BregMaster_54 = BregMaster[54] ;
assign BregMaster_57 = BregMaster[57] ;
wire [57:0] Creg;
assign Creg_30_29 = Creg[30:29] ;
assign Creg_56_55 = Creg[56:55] ;
wire [57:0] FracResult;
assign FracResult_55_52 = FracResult[55:52] ;
assign FracResult_57 = FracResult[57] ;
assign FracResult_56 = FracResult[56] ;
wire [57:0] FracResultBuf;
assign FracResultBufout = FracResultBuf[54:3] ;
wire [57:0] Treg;
assign Treg_1_0 = Treg[1:0];
// internal bus on fractions datapath
wire [57:1] SRResult;
wire [57:0] SLResult;
wire [57:0] SResult, BregMasterBuf, FracXbus;
wire [57:2] FracYbus;
wire [57-1:1] SD;
wire [57-1:2] CD;
// extended internal format operands
wire [57:0] OprA, OprB;
wire [51:0] FracOpA, FracOpB;
// note order of items is suggested order of functional units on datapath.
// Operand select (single/double) muxes
ME_MUX_2B_52 opifaxf (OprSNnotDB,
RS2_frac[51:0],
{RS2_frac[54:32],
gnd, gnd, gnd, gnd, gnd, gnd, gnd,
gnd, gnd, gnd, gnd, gnd, gnd, gnd,
gnd, gnd, gnd, gnd, gnd, gnd, gnd,
gnd, gnd, gnd, gnd, gnd, gnd, gnd,
gnd},
FracOpA[51:0]);
assign OprA = {gnd, gnd, vdd, FracOpA, gnd, gnd, gnd};
ME_MUX_2B_52 opifbxf (OprSNnotDB,
RS1_frac[51:0],
{RS1_frac[54:32],
gnd, gnd, gnd, gnd, gnd, gnd, gnd,
gnd, gnd, gnd, gnd, gnd, gnd, gnd,
gnd, gnd, gnd, gnd, gnd, gnd, gnd,
gnd, gnd, gnd, gnd, gnd, gnd, gnd,
gnd},
FracOpB[51:0]);
assign OprB = {gnd, gnd, vdd, FracOpB, gnd, gnd, gnd};
// Breg Input stuff
ME_FREGA_5_58 B (ss_clock,
FracBregLoadEn,
FracBregLC[0], FracBregLC[1], FracBregLC[2],
OprB, AregMasterBuf,
FracResultBuf,
{FracResultBuf[57-2:0], InFromCregOr0}, // FracResultSL2
{CD[57-1:2], CarryOut3, CarryOut0, gnd}, // MulResCarry For Breg
BregMaster,
BregMasterBuf,
notBregMSB);
MultiplierSlice mu (ss_clock,
InitialMulStep,
// dhn--01/10/91 notInitialSumZero, //
InitialCarryBit,
SumCarryLoadEn,
Shift, Pos, Zero,
SumOut0, CarryOut0, CarryOut3,
BregMasterBuf[57:1], SumInLSBs, CarryInLSBs,
SALSBs, SBLSBs, SCLSBs,
CALSB, CBLSB, CCLSB,
SD[57-1:1],
CD[57-1:2]);
ME_FREGA_2_58 C (ss_clock,
FracCregLoadEn, FracCregLC,
FracResultBuf,
{Creg[57-2:31],InForCreg, Creg[28:1], InForCregDB, gnd}, // CregSL2SQTDIV
Creg);
// ******** AREG *********************************
ME_INVA ifs (FracResult_57, notFracSign); // used to be in divlog
ME_FREGA_8_58 A (ss_clock,
FracAregLoadEn,
FracAregLC[0], FracAregLC[1], FracAregLC[2],
OprA,
Creg,
BregMasterBuf, // 2 Allow speedy swapping
SResult, // 3
FracResultBuf,
{FracResultBuf[56:0], gnd}, // FracResultSL1
{AregMasterBuf[56:2], notFracSign, gnd, gnd},
{SD[57-1:1], CarryOut0, SumOut0}, // MulResSum ForAreg
AregMaster,
AregMasterBuf,
AregMasterFPMSBP1,
notAregMasterFPMSBP1);
// logic on output of areg in datapath
AregInexactSlice ax (AregMasterBuf[31:0], notAM31_3, notAM2_0);
MulSelSlice snmultip ( MulLenSel, AregMaster[8:0], AregMaster[40:32], notMultip );
// *************** end of Areg ************************************ //
// Shifter logic
ShiftRight shr (AregMasterBuf, SRControl, SROneMore,
SRToSticky, TopBitsIn,
notSticky4, Sticky2, notSticky1, StickyExtra,
SRResult[57:1]);
ShiftLeft shl (AregMasterBuf, SLControl, LIB,
SLResult);
ME_NMUX_2B_58 Smux (LeftnotRight, {SRResult[57:1], notStickyInForSR}, SLResult,
SResult);
ME_FREGA_1_58 T (ss_clock, FracTregLoadEn, FracResultBuf, Treg);
// *************** end of Treg ************************************ //
/*ME_MUX_4B_56 Ymux (notFracYFromD0,
notFracYFromD1,
{gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd,
gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd,
gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd,
gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd}, // 56'h0
{AregMasterBuf[57], AregMasterBuf[57:3]}, // AregMasterSR1[57:2]
AregMasterBuf[57:2],
Treg[57:2],
FracYbus[57:2]);*/
ME_YmuxSlice Ymux (notFracYFromD1, notFracYFromD2, notFracYFromD3,
/* dhn--01/10/91 notFracYFromD1A, notFracYFromD2A, notFracYFromD3A, */
{AregMasterBuf[57], AregMasterBuf[57:3]}, // AregMasterSR1[57:2]
AregMasterBuf[57:2],
Treg[57:2],
FracYbus[57:2]);
// send bottom two bits of Y to control logic
// assign FracYbusBSLSBs = FracYbus[1:0]; // ignored taken from AregMaster[2:0] and Treg[1:0]
// insert two bits from control logic into the low end of Ybus here
// *************** end of Ymux ************************************ //
ME_MUX_2B_B_58 Xbus (FracXFromB,
{ gnd, gnd, Constantb,
gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd,
gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd,
gnd, gnd, gnd, gnd, gnd, gnd, gnd,
Constantd,
Constante, Constante, Constante, Constante,
Constante, Constante, Constante, Constante,
Constante, Constante, Constante, Constante,
Constante, Constante, Constante, Constante,
Constante, Constante, Constante, Constante,
Constante, Constante, Constante, Constante,
Constante, Constante, Constante, Constante,
Constantf,
Constantg, Constantg}, // FracXConstant
BregMasterBuf, FracXbus);
AregLSBLog alsb (AregMaster[1:0], // AregLSBs[1:0]
AregMaster[33:32], // AregLSBSN
AregMaster[4:3], // AregLSBDB
AregMaster[56], // AregFPMSBP1
SNnotDB,
TrueIEEEAregLSB,
StickyForSR1);
wire Eqv;
AdderLSBlog fals (FracALUOpSub,
FracALUOpDiv,
notBregMSB, // notFracBregSign
Eqv,
Constanth, // notFracRNearest
TrueIEEEAregLSB,
Sub, AdderCarryIn,
notFracZero, FracZero);
ME_ADD_58 adr (Sub, AdderCarryIn,
FracXbus,
{FracYbus, FracYbusLSBs},
FracResult, FracResultBuf, Eqv);
/* ***************************** */
/* Deal with special result bits */
/* ***************************** */
CheckOverflow ov (FracResult[55+1:55-8], notPossibleOv, SubResultNorm);
endmodule
|
module MulSelSlice (MulLenSel, MDB, MSN, Multip);
input [4:0] MulLenSel;
input [8:0] MDB, MSN;
output [8:0] Multip;
wire [1:0] BMulLenSel;
// MulLenSel is {SNnotDB, SNnotDB, SNnotDB}
// these are buffered singly to give maximum speed for
// the multiplier select
// Note : BMulLenSel is inverse
ME_NMUX2B_B s0 ( MulLenSel[0], MDB[0], MSN[0], Multip[0]);
ME_NMUX2B_B s1 ( MulLenSel[1], MDB[1], MSN[1], Multip[1]);
ME_NMUX2B_B s2 ( MulLenSel[2], MDB[2], MSN[2], Multip[2]);
ME_NMUX2B_B s3 ( MulLenSel[3], MDB[3], MSN[3], Multip[3]);
ME_NMUX2B_B s4 ( MulLenSel[3], MDB[4], MSN[4], Multip[4]);
ME_NMUX2B_B s5 ( MulLenSel[4], MDB[5], MSN[5], Multip[5]);
ME_NMUX2B_B s6 ( MulLenSel[3], MDB[6], MSN[6], Multip[6]);
ME_NMUX2B_B s7 ( MulLenSel[4], MDB[7], MSN[7], Multip[7]);
ME_NMUX2B_B s8 ( MulLenSel[4], MDB[8], MSN[8], Multip[8]);
endmodule
|
module definition and body are reversed
//**************************
input Phi;
input
// notInitialSumZero, /
InitialMulStep,
InitialCarryBit,
SumCarryLoadEn;
input [3:0] Shift,
Pos,
Zero;
input SumOut0,
CarryOut0,
CarryOut3;
input [`FracMSB:1] Breg;
output [`FracMSB:0] SumIn, CarryIn;
output [1:0] SALSBs, SBLSBs, SCLSBs;
output CALSB, CBLSB, CCLSB;
output [`FracMSB:1]SD; // original lines
output [`FracMSB:2]CD; // original lines
//output [`FracMSB:2]CD;
//output [`FracMSB:1]SD;
CSRegSlice csr (Phi,
InitialMulStep,
// notInitialSumZero, /
InitialCarryBit,
SumCarryLoadEn,
{SD[`FracMSB:1], SumOut0},
{CD[`FracMSB:2], CarryOut3, CarryOut0},
Breg [`FracMSB:1],
SumIn[`FracMSB:0],
CarryIn[`FracMSB:0]);
CSArray csa ( Shift,
Pos,
Zero,
SumIn[`FracMSB:3],
CarryIn[`FracMSB:3],
Breg [`FracMSB:1],
SALSBs, SBLSBs, SCLSBs,
CALSB, CBLSB, CCLSB,
SD[`FracMSB:1],
CD[`FracMSB:2]);
endmodule
|
module ShiftLeft (NI,
SLControl,
LIB,
SLResult);
input [`FracMSB:0] NI;
input [3:0] SLControl;
input [2:0] LIB; // shifted operand for int or frac
output [`FracMSB:0] SLResult;
wire [`FracMSB:0] N8, N4, N2, N1;
ME_TIEOFF toff (vdd, gnd);
ME_NMUX_2B_58 g23 (SLControl[3],
NI,
{LIB[2], LIB[1], LIB[0], NI[`FracMSB-11:0],
gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd},
N8); // False
ME_NMUX_2B_58 g24 (SLControl[2],
N8,
{N8[`FracMSB-4:0], vdd, vdd, vdd, vdd}, N4);
ME_NMUX_2B_58 g25 (SLControl[1],
N4,
{N4[`FracMSB-2:0], gnd, gnd},
N2); // False
ME_NMUX_2B_58 g26 (SLControl[0], N2, {N2[`FracMSB-1:0], vdd}, N1); // true
ME_INV_A_58 g27 (N1, SLResult); // false
endmodule
|
module ShiftRight (Areg,
SRControl,
SROneMore,
SRToSticky,
TopBitsIn,
// outputs
S8_3_0,
S4_1_0,
S2_0,
S1_1_0,
notSRResult);
input [`FracMSB:0] Areg;
input [3:0] SRControl;
input SROneMore,
SRToSticky;
input [8:0] TopBitsIn;
output [3:0] S8_3_0;
output [1:0] S4_1_0;
output S2_0;
output [1:0] S1_1_0;
output [`FracMSB:1] notSRResult;
wire [`FracMSB:0] S8, S4, S2, S1;
wire [`FracMSB:0] SE;
assign S8_3_0 = S8[3:0] ;
assign S4_1_0 = S4[1:0] ;
assign S2_0 = S2[0] ;
assign S1_1_0 = S1[1:0] ;
ME_NMUX2B_B g87 (SRControl[3], // Buffer MSB seperately
Areg[`FracMSB],
TopBitsIn[8],
S8[`FracMSB]); // False
ME_NMUX_2B_57 g86 (SRControl[3],
Areg[`FracMSB-1:0],
{TopBitsIn[8], TopBitsIn[8:0], Areg[`FracMSB-3:8]},
S8[`FracMSB-1:0]); // False
ME_NMUX_2B_58 g21 (SRControl[2],
S8,
{S8[`FracMSB], S8[`FracMSB],S8[`FracMSB],S8[`FracMSB],
S8[`FracMSB:4]},
S4); // True
ME_NMUX_2B_58 g23 (SRControl[1],
S4,
{S4[`FracMSB], S4[`FracMSB],S4[`FracMSB:2]},
S2); // False
ME_NMUX_2B_58 g24 (SRControl[0],
S2,
{S2[`FracMSB], S2[`FracMSB:1]},
S1); // True
ME_NMUX_2B_58 g25 (SROneMore,
S1,
{S1[`FracMSB], S1[`FracMSB:1]},
SE); // False
ME_INV_B g50 (SRToSticky, notSRToSticky);
ME_INV_C g51 (notSRToSticky, BSRToSticky);
ME_OR2_B h01 (BSRToSticky, SE[01], notSRResult[01]);
ME_OR2_B h02 (BSRToSticky, SE[02], notSRResult[02]);
ME_OR2_B h03 (BSRToSticky, SE[03], notSRResult[03]);
ME_OR2_B h04 (BSRToSticky, SE[04], notSRResult[04]);
ME_OR2_B h05 (BSRToSticky, SE[05], notSRResult[05]);
ME_OR2_B h06 (BSRToSticky, SE[06], notSRResult[06]);
ME_OR2_B h07 (BSRToSticky, SE[07], notSRResult[07]);
ME_OR2_B h08 (BSRToSticky, SE[08], notSRResult[08]);
ME_OR2_B h09 (BSRToSticky, SE[09], notSRResult[09]);
ME_OR2_B h10 (BSRToSticky, SE[10], notSRResult[10]);
ME_OR2_B h11 (BSRToSticky, SE[11], notSRResult[11]);
ME_OR2_B h12 (BSRToSticky, SE[12], notSRResult[12]);
ME_OR2_B h13 (BSRToSticky, SE[13], notSRResult[13]);
ME_OR2_B h14 (BSRToSticky, SE[14], notSRResult[14]);
ME_OR2_B h15 (BSRToSticky, SE[15], notSRResult[15]);
ME_OR2_B h16 (BSRToSticky, SE[16], notSRResult[16]);
ME_OR2_B h17 (BSRToSticky, SE[17], notSRResult[17]);
ME_OR2_B h18 (BSRToSticky, SE[18], notSRResult[18]);
ME_OR2_B h19 (BSRToSticky, SE[19], notSRResult[19]);
ME_OR2_B h20 (BSRToSticky, SE[20], notSRResult[20]);
ME_OR2_B h21 (BSRToSticky, SE[21], notSRResult[21]);
ME_OR2_B h22 (BSRToSticky, SE[22], notSRResult[22]);
ME_OR2_B h23 (BSRToSticky, SE[23], notSRResult[23]);
ME_OR2_B h24 (BSRToSticky, SE[24], notSRResult[24]);
ME_OR2_B h25 (BSRToSticky, SE[25], notSRResult[25]);
ME_OR2_B h26 (BSRToSticky, SE[26], notSRResult[26]);
ME_OR2_B h27 (BSRToSticky, SE[27], notSRResult[27]);
ME_OR2_B h28 (BSRToSticky, SE[28], notSRResult[28]);
ME_OR2_B h29 (BSRToSticky, SE[29], notSRResult[29]);
ME_OR2_B h30 (BSRToSticky, SE[30], notSRResult[30]);
ME_OR2_B h31 (BSRToSticky, SE[31], notSRResult[31]);
ME_OR2_B h32 (BSRToSticky, SE[32], notSRResult[32]);
ME_OR2_B h33 (BSRToSticky, SE[33], notSRResult[33]);
ME_OR2_B h34 (BSRToSticky, SE[34], notSRResult[34]);
ME_OR2_B h35 (BSRToSticky, SE[35], notSRResult[35]);
ME_OR2_B h36 (BSRToSticky, SE[36], notSRResult[36]);
ME_OR2_B h37 (BSRToSticky, SE[37], notSRResult[37]);
ME_OR2_B h38 (BSRToSticky, SE[38], notSRResult[38]);
ME_OR2_B h39 (BSRToSticky, SE[39], notSRResult[39]);
ME_OR2_B h40 (BSRToSticky, SE[40], notSRResult[40]);
ME_OR2_B h41 (BSRToSticky, SE[41], notSRResult[41]);
ME_OR2_B h42 (BSRToSticky, SE[42], notSRResult[42]);
ME_OR2_B h43 (BSRToSticky, SE[43], notSRResult[43]);
ME_OR2_B h44 (BSRToSticky, SE[44], notSRResult[44]);
ME_OR2_B h45 (BSRToSticky, SE[45], notSRResult[45]);
ME_OR2_B h46 (BSRToSticky, SE[46], notSRResult[46]);
ME_OR2_B h47 (BSRToSticky, SE[47], notSRResult[47]);
ME_OR2_B h48 (BSRToSticky, SE[48], notSRResult[48]);
ME_OR2_B h49 (BSRToSticky, SE[49], notSRResult[49]);
ME_OR2_B h50 (BSRToSticky, SE[50], notSRResult[50]);
ME_OR2_B h51 (BSRToSticky, SE[51], notSRResult[51]);
ME_OR2_B h52 (BSRToSticky, SE[52], notSRResult[52]);
ME_OR2_B h53 (BSRToSticky, SE[53], notSRResult[53]);
ME_OR2_B h54 (BSRToSticky, SE[54], notSRResult[54]);
ME_OR2_B h55 (BSRToSticky, SE[55], notSRResult[55]);
ME_OR2_B h56 (BSRToSticky, SE[56], notSRResult[56]);
ME_OR2_B h57 (BSRToSticky, SE[57], notSRResult[57]);
endmodule
|
module fp_rom ( ss_clock, rom_adr, rom_dout,
rom_scan_out, rom_scan_in, ss_scan_mode);
input ss_clock ;
input rom_scan_in, ss_scan_mode ;
input [7:0] rom_adr ;
output rom_scan_out ;
output [63:0] rom_dout ;
wire [63:0] data ;
wire [7:0] reg_rom_adr ; // registered version of the address
Mflipflop_noop rmad7(reg_rom_adr[7], rom_adr[7], ss_clock);
Mflipflop_noop rmad6(reg_rom_adr[6], rom_adr[6], ss_clock);
Mflipflop_noop rmad5(reg_rom_adr[5], rom_adr[5], ss_clock);
Mflipflop_noop rmad4(reg_rom_adr[4], rom_adr[4], ss_clock);
Mflipflop_noop rmad3(reg_rom_adr[3], rom_adr[3], ss_clock);
Mflipflop_noop rmad2(reg_rom_adr[2], rom_adr[2], ss_clock);
Mflipflop_noop rmad1(reg_rom_adr[1], rom_adr[1], ss_clock);
Mflipflop_noop rmad0(reg_rom_adr[0], rom_adr[0], ss_clock);
RR256X64 ROM_256x64 (
.DO63(rom_dout[63]),
.DO62(rom_dout[62]),
.DO61(rom_dout[61]),
.DO60(rom_dout[60]),
.DO59(rom_dout[59]),
.DO58(rom_dout[58]),
.DO57(rom_dout[57]),
.DO56(rom_dout[56]),
.DO55(rom_dout[55]),
.DO54(rom_dout[54]),
.DO53(rom_dout[53]),
.DO52(rom_dout[52]),
.DO51(rom_dout[51]),
.DO50(rom_dout[50]),
.DO49(rom_dout[49]),
.DO48(rom_dout[48]),
.DO47(rom_dout[47]),
.DO46(rom_dout[46]),
.DO45(rom_dout[45]),
.DO44(rom_dout[44]),
.DO43(rom_dout[43]),
.DO42(rom_dout[42]),
.DO41(rom_dout[41]),
.DO40(rom_dout[40]),
.DO39(rom_dout[39]),
.DO38(rom_dout[38]),
.DO37(rom_dout[37]),
.DO36(rom_dout[36]),
.DO35(rom_dout[35]),
.DO34(rom_dout[34]),
.DO33(rom_dout[33]),
.DO32(rom_dout[32]),
.DO31(rom_dout[31]),
.DO30(rom_dout[30]),
.DO29(rom_dout[29]),
.DO28(rom_dout[28]),
.DO27(rom_dout[27]),
.DO26(rom_dout[26]),
.DO25(rom_dout[25]),
.DO24(rom_dout[24]),
.DO23(rom_dout[23]),
.DO22(rom_dout[22]),
.DO21(rom_dout[21]),
.DO20(rom_dout[20]),
.DO19(rom_dout[19]),
.DO18(rom_dout[18]),
.DO17(rom_dout[17]),
.DO16(rom_dout[16]),
.DO15(rom_dout[15]),
.DO14(rom_dout[14]),
.DO13(rom_dout[13]),
.DO12(rom_dout[12]),
.DO11(rom_dout[11]),
.DO10(rom_dout[10]),
.DO9(rom_dout[9]),
.DO8(rom_dout[8]),
.DO7(rom_dout[7]),
.DO6(rom_dout[6]),
.DO5(rom_dout[5]),
.DO4(rom_dout[4]),
.DO3(rom_dout[3]),
.DO2(rom_dout[2]),
.DO1(rom_dout[1]),
.DO0(rom_dout[0]),
.OE(1'b1),
.ADR7(reg_rom_adr[7]),
.ADR6(reg_rom_adr[6]),
.ADR5(reg_rom_adr[5]),
.ADR4(reg_rom_adr[4]),
.ADR3(reg_rom_adr[3]),
.ADR2(reg_rom_adr[2]),
.ADR1(reg_rom_adr[1]),
.ADR0(reg_rom_adr[0])
);
endmodule
|
module RR256X64 (
DO63,DO62,DO61,DO60,DO59,DO58,DO57,DO56,
DO55,DO54,DO53,DO52,DO51,DO50,DO49,DO48,
DO47,DO46,DO45,DO44,DO43,DO42,DO41,DO40,
DO39,DO38,DO37,DO36,DO35,DO34,DO33,DO32,
DO31,DO30,DO29,DO28,DO27,DO26,DO25,DO24,
DO23,DO22,DO21,DO20,DO19,DO18,DO17,DO16,
DO15,DO14,DO13,DO12,DO11,DO10,DO9,DO8,
DO7,DO6,DO5,DO4,DO3,DO2,DO1,DO0,
OE,
ADR7,ADR6,ADR5,ADR4,ADR3,ADR2,ADR1,ADR0);
input OE,
ADR7,ADR6,ADR5,ADR4,ADR3,ADR2,ADR1,ADR0;
output DO63,DO62,DO61,DO60,DO59,DO58,DO57,DO56,
DO55,DO54,DO53,DO52,DO51,DO50,DO49,DO48,
DO47,DO46,DO45,DO44,DO43,DO42,DO41,DO40,
DO39,DO38,DO37,DO36,DO35,DO34,DO33,DO32,
DO31,DO30,DO29,DO28,DO27,DO26,DO25,DO24,
DO23,DO22,DO21,DO20,DO19,DO18,DO17,DO16,
DO15,DO14,DO13,DO12,DO11,DO10,DO9,DO8,
DO7,DO6,DO5,DO4,DO3,DO2,DO1,DO0;
wire [7:0] reg_rom_adr = {
ADR7,ADR6,ADR5,ADR4,ADR3,ADR2,ADR1,ADR0 };
reg [63:0] data;
assign {
DO63,DO62,DO61,DO60,DO59,DO58,DO57,DO56,
DO55,DO54,DO53,DO52,DO51,DO50,DO49,DO48,
DO47,DO46,DO45,DO44,DO43,DO42,DO41,DO40,
DO39,DO38,DO37,DO36,DO35,DO34,DO33,DO32,
DO31,DO30,DO29,DO28,DO27,DO26,DO25,DO24,
DO23,DO22,DO21,DO20,DO19,DO18,DO17,DO16,
DO15,DO14,DO13,DO12,DO11,DO10,DO9,DO8,
DO7,DO6,DO5,DO4,DO3,DO2,DO1,DO0 } = data[63:0];
always @(reg_rom_adr) begin
case (reg_rom_adr)
8'd000: data = 64'h0000000000000000 ;
8'd001: data = 64'h00000011100085c4 ;
8'd002: data = 64'h00000041100085a4 ;
8'd003: data = 64'h0000000000000000 ;
8'd004: data = 64'h03103010c804f865 ;
8'd005: data = 64'h0020800113800000 ;
8'd006: data = 64'h00000000000085ac ;
8'd007: data = 64'h121200000000806c ;
8'd008: data = 64'h041440404800f865 ;
8'd009: data = 64'h0020800113800000 ;
8'd010: data = 64'h05145051c800f865 ;
8'd011: data = 64'h0020800113800000 ;
8'd012: data = 64'h000000100000860c ;
8'd013: data = 64'h121200512000807c ;
8'd014: data = 64'h000000100000860c ;
8'd015: data = 64'h12120000000081dc ;
8'd016: data = 64'h00000000000080a4 ;
8'd017: data = 64'h00000000000087dc ;
8'd018: data = 64'h0000004110000000 ;
8'd019: data = 64'h00000001e8001dac ;
8'd020: data = 64'h002080111000d57f ;
8'd021: data = 64'h0020800123800000 ;
8'd022: data = 64'h001430000000c9cd ;
8'd023: data = 64'h0010300188000000 ;
8'd024: data = 64'h0a14507968037040 ;
8'd025: data = 64'h0300001968200000 ;
8'd026: data = 64'h0a145079680371f0 ;
8'd027: data = 64'h0300000168200000 ;
8'd028: data = 64'h0a14507968037040 ;
8'd029: data = 64'h0300001968200000 ;
8'd030: data = 64'h0a145079680371f0 ;
8'd031: data = 64'h0300000168200000 ;
8'd032: data = 64'h0014000048000000 ;
8'd033: data = 64'h0a1430000000c1cc ;
8'd034: data = 64'h0a000000000069cc ;
8'd035: data = 64'h0200000000008254 ;
8'd036: data = 64'h0014010048000000 ;
8'd037: data = 64'h0c1850518000c2f4 ;
8'd038: data = 64'h0c1850000000c83c ;
8'd039: data = 64'h02000018000082fe ;
8'd040: data = 64'h0a14507968037040 ;
8'd041: data = 64'h0300001968200000 ;
8'd042: data = 64'h0a145079680371f0 ;
8'd043: data = 64'h0300000168200000 ;
8'd044: data = 64'h0a14507968037040 ;
8'd045: data = 64'h0300001968200000 ;
8'd046: data = 64'h0a145079680371f0 ;
8'd047: data = 64'h0300000168200000 ;
8'd048: data = 64'h8a1030000000842c ;
8'd049: data = 64'h80103380000080b4 ;
8'd050: data = 64'h801030780000842c ;
8'd051: data = 64'h82103390680080b4 ;
8'd052: data = 64'h801033800000866c ;
8'd053: data = 64'h8a103380000086c4 ;
8'd054: data = 64'h80103380000086c4 ;
8'd055: data = 64'h0a1433800000c90c ;
8'd056: data = 64'h001430000000c77e ;
8'd057: data = 64'h801030000000ea55 ;
8'd058: data = 64'h0014008188000000 ;
8'd059: data = 64'h1212005120008624 ;
8'd060: data = 64'h0000000000000001 ;
8'd061: data = 64'h0000000001000000 ;
8'd062: data = 64'h001450000000c737 ;
8'd063: data = 64'h0000000001000000 ;
8'd064: data = 64'h8a1030780000861c ;
8'd065: data = 64'h80103000000080b4 ;
8'd066: data = 64'h801030000000861c ;
8'd067: data = 64'h82103018000080b4 ;
8'd068: data = 64'h801030000000812c ;
8'd069: data = 64'h00000000000080b4 ;
8'd070: data = 64'h82103018000080b4 ;
8'd071: data = 64'h0a1430000000c90c ;
8'd072: data = 64'h001430000000c9cc ;
8'd073: data = 64'h000000000000977e ;
8'd074: data = 64'h04100017a0000000 ;
8'd075: data = 64'h0300029188180001 ;
8'd076: data = 64'h001400004b400000 ;
8'd077: data = 64'h5e10001140000000 ;
8'd078: data = 64'h5810501140000000 ;
8'd079: data = 64'h5e95501120008470 ;
8'd080: data = 64'h5e95500000000000 ;
8'd081: data = 64'h80103027c8003cfc ;
8'd082: data = 64'h10100047e00022a4 ;
8'd083: data = 64'h0514000000000000 ;
8'd084: data = 64'h0a000011a0008268 ;
8'd085: data = 64'h2018501140000000 ;
8'd086: data = 64'h5e10001140008470 ;
8'd087: data = 64'h5810500000000000 ;
8'd088: data = 64'h8300039160128350 ;
8'd089: data = 64'h03000017c8100000 ;
8'd090: data = 64'h0000028000000000 ;
8'd091: data = 64'h0000007800008244 ;
8'd092: data = 64'haa120391680283f0 ;
8'd093: data = 64'hca18401720000000 ;
8'd094: data = 64'h0c1850518000c605 ;
8'd095: data = 64'h0020800002800000 ;
8'd096: data = 64'h0014008048000000 ;
8'd097: data = 64'h80103027c8003cfc ;
8'd098: data = 64'h10100047e0002324 ;
8'd099: data = 64'h0514000000000000 ;
8'd100: data = 64'h0a000011a00082b0 ;
8'd101: data = 64'h2018501140000000 ;
8'd102: data = 64'h0300000000108448 ;
8'd103: data = 64'h0300000000100000 ;
8'd104: data = 64'h8300039160120c48 ;
8'd105: data = 64'h03000017c8100000 ;
8'd106: data = 64'h0300000000108330 ;
8'd107: data = 64'h0300000000100000 ;
8'd108: data = 64'haa120391680283f8 ;
8'd109: data = 64'hca18401720000000 ;
8'd110: data = 64'h001430000000c9cd ;
8'd111: data = 64'h0010300003800000 ;
8'd112: data = 64'h8a103380000083d4 ;
8'd113: data = 64'h8010338000008374 ;
8'd114: data = 64'h801033800000870c ;
8'd115: data = 64'h82103380000080b4 ;
8'd116: data = 64'h8a103078000086dc ;
8'd117: data = 64'h8010338000008374 ;
8'd118: data = 64'h82103380000080b4 ;
8'd119: data = 64'h0a1433800000c90c ;
8'd120: data = 64'h001430000000c254 ;
8'd121: data = 64'h00000000000081cc ;
8'd122: data = 64'h0c1850118000c6ee ;
8'd123: data = 64'h03000010c8040000 ;
8'd124: data = 64'haa12001168000bf8 ;
8'd125: data = 64'hca18401720000000 ;
8'd126: data = 64'h78c0400000000000 ;
8'd127: data = 64'h78c0404380000000 ;
8'd128: data = 64'h78c04041e800e400 ;
8'd129: data = 64'h78c0400000000000 ;
8'd130: data = 64'h01105011c800c454 ;
8'd131: data = 64'h041500004800f865 ;
8'd132: data = 64'h0020800113800000 ;
8'd133: data = 64'h0c1853918000c37e ;
8'd134: data = 64'h03000010c8040000 ;
8'd135: data = 64'h8300001160108b4c ;
8'd136: data = 64'h03000017c8100000 ;
8'd137: data = 64'h0700000000000000 ;
8'd138: data = 64'h041440104800f865 ;
8'd139: data = 64'h0020800113800000 ;
8'd140: data = 64'h0b0000158018ae4c ;
8'd141: data = 64'h0414101720008654 ;
8'd142: data = 64'h5e95500000002a54 ;
8'd143: data = 64'h5e955011c800e470 ;
8'd144: data = 64'hde95500000000000 ;
8'd145: data = 64'h101800106800dc9c ;
8'd146: data = 64'h1013400000000000 ;
8'd147: data = 64'h03105000c804c454 ;
8'd148: data = 64'h041500004800f865 ;
8'd149: data = 64'h0020800113800000 ;
8'd150: data = 64'h001850000000ccc4 ;
8'd151: data = 64'h001430000000c736 ;
8'd152: data = 64'h0a145079680171f0 ;
8'd153: data = 64'h0300000168200000 ;
8'd154: data = 64'h88103877c8009d5c ;
8'd155: data = 64'h00000000000087b4 ;
8'd156: data = 64'h8810387728003f6c ;
8'd157: data = 64'h041400172800f865 ;
8'd158: data = 64'h0020800113800000 ;
8'd159: data = 64'h080000604800e2d4 ;
8'd160: data = 64'h041850118000c37e ;
8'd161: data = 64'h03000010c8040000 ;
8'd162: data = 64'h00000027c8008a94 ;
8'd163: data = 64'h0000000000008314 ;
8'd164: data = 64'h001850000000c724 ;
8'd165: data = 64'h001430000000c54c ;
8'd166: data = 64'h0000000000003546 ;
8'd167: data = 64'h0000000000006d4d ;
8'd168: data = 64'h0000000001c00000 ;
8'd169: data = 64'h020000000000858c ;
8'd170: data = 64'h88103077c8001fb4 ;
8'd171: data = 64'h00000015c8009f9c ;
8'd172: data = 64'h0000004000000000 ;
8'd173: data = 64'h0300000168202e34 ;
8'd174: data = 64'h03000408c81c0001 ;
8'd175: data = 64'h002080004b800000 ;
8'd176: data = 64'h001430600000c1fe ;
8'd177: data = 64'h0000000000003546 ;
8'd178: data = 64'h000000000000ed47 ;
8'd179: data = 64'h0000000001800000 ;
8'd180: data = 64'h00000001e800985e ;
8'd181: data = 64'h0000004180000000 ;
8'd182: data = 64'h0300000168200000 ;
8'd183: data = 64'h04142000000087cc ;
8'd184: data = 64'h000000000000bd7e ;
8'd185: data = 64'h0411101188000000 ;
8'd186: data = 64'h00208011c800d73f ;
8'd187: data = 64'h002080004a000000 ;
8'd188: data = 64'h0c1850158000c5fe ;
8'd189: data = 64'h03000010c8040000 ;
8'd190: data = 64'h0200000048009fad ;
8'd191: data = 64'h0014000003800000 ;
8'd192: data = 64'h041030100000977e ;
8'd193: data = 64'h000002800000b77e ;
8'd194: data = 64'h000003000000877e ;
8'd195: data = 64'h101850418000c77e ;
8'd196: data = 64'h0a14507968017040 ;
8'd197: data = 64'h0300001968200000 ;
8'd198: data = 64'h04141400000080a0 ;
8'd199: data = 64'h03000008c81c0000 ;
8'd200: data = 64'h0b00081580182c6c ;
8'd201: data = 64'h001410172000c37e ;
8'd202: data = 64'h03000010c8040000 ;
8'd203: data = 64'h001400004800f865 ;
8'd204: data = 64'h0020800113800000 ;
8'd205: data = 64'h021430000000c37e ;
8'd206: data = 64'h001430100000c37e ;
8'd207: data = 64'h04110000000085bc ;
8'd208: data = 64'h00000000000081fe ;
8'd209: data = 64'h8010300000008584 ;
8'd210: data = 64'h00000060000081fe ;
8'd211: data = 64'h8210301800008584 ;
8'd212: data = 64'h80103000000084b4 ;
8'd213: data = 64'h8010300000008584 ;
8'd214: data = 64'h8210301800008584 ;
8'd215: data = 64'h8010300000008524 ;
8'd216: data = 64'h0a1850000000c9cc ;
8'd217: data = 64'h001850000000c8be ;
8'd218: data = 64'h0000000000008254 ;
8'd219: data = 64'h0c1853800000cef4 ;
8'd220: data = 64'h0c1850000000c255 ;
8'd221: data = 64'h001030018b000000 ;
8'd222: data = 64'h0c1850518000c37e ;
8'd223: data = 64'h03000010c8040000 ;
8'd224: data = 64'h0a000070680083dc ;
8'd225: data = 64'h0c1850718000c37e ;
8'd226: data = 64'h03000010c8040000 ;
8'd227: data = 64'h0a000070680083e4 ;
8'd228: data = 64'h001430000000cd8c ;
8'd229: data = 64'h00000000000091ff ;
8'd230: data = 64'h0000000000000000 ;
8'd231: data = 64'h0020800122000000 ;
8'd232: data = 64'h00000877c8003f55 ;
8'd233: data = 64'h0014000723800000 ;
8'd234: data = 64'h881030786800e0b4 ;
8'd235: data = 64'h04185011e000c37e ;
8'd236: data = 64'h0000001720008654 ;
8'd237: data = 64'h801030106800e784 ;
8'd238: data = 64'h001850100000ce7d ;
8'd239: data = 64'h001400004b800000 ;
8'd240: data = 64'h001430000000c0be ;
8'd241: data = 64'h04100017a000ea54 ;
8'd242: data = 64'h030002918818877e ;
8'd243: data = 64'h03000468c81cafec ;
8'd244: data = 64'h80103000680065e4 ;
8'd245: data = 64'h0410301000008266 ;
8'd246: data = 64'h000002806800e7c4 ;
8'd247: data = 64'h001850100000c37e ;
8'd248: data = 64'h041100100000877e ;
8'd249: data = 64'h002080000000d2ff ;
8'd250: data = 64'h0020800182800000 ;
8'd251: data = 64'h002080111000d5c4 ;
8'd252: data = 64'h00000011200085c4 ;
8'd253: data = 64'h0410001188000001 ;
8'd254: data = 64'h001110004bc00000 ;
8'd255: data = 64'h0000000000000000 ;
endcase
end
endmodule
|
module usb_ulpi (
// Bus interface
input wire clk_i,
input wire reset_i,
input wire [3:0] A,
input wire [7:0] D_i,
output reg [7:0] D_o,
input wire wr_i,
input wire rd_i,
// Phy Interface
input usb_clkin,
input usb_dir,
input usb_nxt,
output reg usb_stp = 1'b1,
output reg usb_reset = 1'b0,
input [7:0] usb_data_i,
output reg [7:0] usb_data_o = 8'd0,
output wire usb_data_oe
);
parameter STATE_INIT = 4'd0, STATE_IDLE = 4'd1, STATE_WAITDIRL = 4'd2, STATE_SETD = 4'd3, STATE_WAITNXT = 4'd4,
STATE_WAITDIRH = 4'd5, STATE_WAITREAD = 4'd6, STATE_SETSTP = 4'd7, STATE_RECEIVE = 4'd8;
parameter OP_IDLE = 2'd0, OP_REGREAD = 2'd1, OP_REGWRITE = 2'd2, OP_XVR = 2'd3;
// Wire definitions ===========================================================================
wire regread_sig, regwrite_sig, transmit_sig;
wire [7:0] status_register;
wire [4:0] crc5_out;
wire [15:0] crc16_out;
wire crc_en;
// Registers ==================================================================================
// Bus Domain Registers
reg [7:0] bus_reg_data, bus_reg_in;
reg [5:0] bus_reg_id;
reg bus_domain_regread = 1'b0;
reg bus_domain_regwrite = 1'b0;
reg bus_domain_transmit = 1'b0;
reg [3:0] bus_pid = 1'b0;
reg [5:0] tx_buffer_write_ptr = 6'd0;
reg [1:0] track_crc = 2'd0;
// Synchronisers for cross-domain signals
reg [3:0] sync_reset = 4'd0;
reg [2:0] phy_regread = 3'd0;
reg [2:0] phy_regwrite = 3'd0;
reg [2:0] phy_transmit = 3'd0;
reg [2:0] bus_regread = 3'd0;
reg [2:0] bus_regwrite = 3'd0;
reg [2:0] bus_transmit = 3'd0;
reg [2:0] sync_active = 3'd0;
reg [7:0] rx_buffer[0:63]; // Cross domain data buffer
reg [7:0] tx_buffer[0:63]; // Cross domain data buffer
reg [2:0] data_in_buffer = 3'd0;
// USB PHY Domain Registers
reg [3:0] state = STATE_INIT;
reg [5:0] state_cntr = 6'd1;
reg phy_domain_regread = 1'b0;
reg phy_domain_regwrite = 1'b0;
reg phy_domain_transmit = 1'b0;
reg [5:0] phy_reg_id = 6'd0;
reg [7:0] phy_reg_data = 8'd0;
reg delayed_oe = 1'b0;
reg [1:0] phy_operation = 2'd0;
reg [7:0] rxd_cmd = 8'd0;
reg [5:0] rx_buffer_write_ptr = 6'd0;
reg [5:0] tx_buffer_read_ptr = 6'd0;
reg [3:0] phy_pid = 4'd0;
// Assignments ================================================================================
assign regread_sig = (bus_domain_regread != phy_domain_regread);
assign regwrite_sig = (bus_domain_regwrite != phy_domain_regwrite);
assign transmit_sig = (bus_domain_transmit != phy_domain_transmit);
assign usb_data_oe = ~(delayed_oe | usb_dir);
assign status_register = {data_in_buffer[2], 2'd0, ~sync_active[2], 4'd0};
assign crc_en = (track_crc == 2'b01);
// Module connections =========================================================================
crc5 crc5_instance (D_i,crc_en,crc5_out,reset_i,clk_i);
crc16 crc16_instance (D_i,crc_en,crc16_out,reset_i,clk_i);
// Simulation branches and control ============================================================
// Other logic ================================================================================
// Synchronizer chains PHY
always @(posedge usb_clkin) sync_reset <= {sync_reset[2:0],reset_i}; // Bus Reset to PHY
always @(posedge usb_clkin) phy_regread <= {phy_regread[1:0],regread_sig};
always @(posedge usb_clkin) phy_regwrite <= {phy_regwrite[1:0],regwrite_sig};
always @(posedge usb_clkin) phy_transmit <= {phy_transmit[1:0],transmit_sig};
// Synchronizer chains BUS
always @(posedge clk_i) bus_regread <= {bus_regread[1:0],regread_sig};
always @(posedge clk_i) bus_regwrite <= {bus_regwrite[1:0],regwrite_sig};
always @(posedge clk_i) bus_transmit <= {bus_transmit[1:0],transmit_sig};
always @(posedge clk_i) sync_active <= {sync_active[1:0],(phy_operation[1] | phy_operation[0])};
always @(posedge clk_i) data_in_buffer <= {data_in_buffer[1:0], rx_buffer_write_ptr != 6'd0 }; // TODO: This isn't sufficient synchronising
// Track signal edges
always @(posedge clk_i) track_crc <= {track_crc[0],wr_i};
// Bus domain logic ===========================================================================
always @(posedge clk_i or posedge reset_i)
begin
if( reset_i )
begin
bus_reg_data <= 8'd0;
bus_reg_id <= 6'd0;
bus_reg_in <= 8'd0;
bus_domain_regread <= 1'b0;
bus_domain_regwrite <= 1'b0;
tx_buffer_write_ptr <= 6'b0;
end
else case(A)
4'h0 : begin
if( rd_i ) D_o <= phy_reg_data;
else
if( wr_i ) bus_reg_data <= D_i;
end
4'h1 : begin
if( rd_i ) D_o <= {2'd0, bus_reg_id};
else
if( wr_i ) bus_reg_id <= D_i[5:0];
end
4'h8 : begin
if( rd_i ) ;
else
if( wr_i ) begin
tx_buffer[tx_buffer_write_ptr] <= D_i;
tx_buffer_write_ptr <= tx_buffer_write_ptr + 1'b1;
end
end
4'hc : begin
// USB domain register rxd_cmd doesn't need synchronizer as status should be checked before reading
if( rd_i ) D_o <= rxd_cmd;
else if( wr_i ) bus_pid <= D_i[3:0];
end
// Control
4'hf : begin
if( rd_i ) D_o <= status_register;
else
if( wr_i ) begin
if( D_i[1] ) // Reg read
begin
if( ~bus_regread[2] ) bus_domain_regread <= ~bus_domain_regread;
end
else
if( D_i[0] ) // Reg write
begin
if( ~bus_regwrite[2] ) bus_domain_regwrite <= ~bus_domain_regwrite;
end
else
if( D_i[7] ) // Clear buffer
begin
tx_buffer_write_ptr <= 6'd0;
end
else
if( D_i[4] ) // Begin transmit
begin
if( ~bus_transmit[2] ) bus_domain_transmit <= ~bus_domain_transmit;
end
end
end
default: D_o <= 8'hff;
endcase
end
// USB domain logic ===========================================================================
// Set the OE
always @(posedge usb_clkin) delayed_oe <= usb_dir;
// USB State Machine
always @(posedge usb_clkin or posedge sync_reset[3])
begin
if( sync_reset[3] )
begin
state <= STATE_INIT;
state_cntr <= 6'd1;
end
else
begin
case( state )
STATE_INIT:
begin
usb_reset = 1'b1;
usb_stp <= 1'b1;
usb_data_o <= 8'd0;
if( state_cntr != 6'd0 ) state_cntr <= state_cntr + 1'b1;
else state <= STATE_IDLE;
end
STATE_IDLE:
begin
usb_reset <= 1'b0;
usb_data_o <= 8'd0;
usb_stp <= 1'b0;
// Incoming read
if( usb_dir ) begin
phy_operation <= OP_XVR;
rx_buffer_write_ptr <= 6'd0;
state <= STATE_RECEIVE;
end else
// Read register
if( phy_regread[2] ) begin
phy_operation <= OP_REGREAD;
// Capture command params
phy_reg_id <= bus_reg_id;
phy_domain_regread <= ~phy_domain_regread;
if( usb_dir ) state <= STATE_WAITDIRL;
else state <= STATE_SETD;
end else // Write register
if( phy_regwrite[2] ) begin
phy_operation <= OP_REGWRITE;
// Capture command params
phy_reg_id <= bus_reg_id;
phy_reg_data <= bus_reg_data;
phy_domain_regwrite <= ~phy_domain_regwrite;
if( usb_dir ) state <= STATE_WAITDIRL;
else state <= STATE_SETD;
end else // Transmit
if( phy_transmit[2] ) begin
phy_operation <= OP_XVR;
// Capture command params
phy_pid <= bus_pid;
tx_buffer_read_ptr <= 6'd0;
phy_domain_transmit <= ~phy_domain_transmit;
if( usb_dir ) state <= STATE_WAITDIRL;
else state <= STATE_SETD;
end else phy_operation = OP_IDLE;
end
STATE_WAITDIRL:
begin
if( ~usb_dir ) state <= STATE_SETD;
end
STATE_SETD:
begin
case( phy_operation )
OP_REGREAD:
usb_data_o <= {2'b11, phy_reg_id};
OP_REGWRITE:
usb_data_o <= {2'b10, phy_reg_id};
OP_XVR:
usb_data_o <= {4'b0100, phy_pid};
endcase
state <= STATE_WAITNXT;
end
STATE_WAITNXT:
begin
if( usb_nxt ) begin
usb_data_o <= 8'd0; // Safety - set to NOP
case( phy_operation )
OP_REGREAD: state <= STATE_WAITDIRH;
OP_REGWRITE: begin
usb_data_o <= phy_reg_data;
state <= STATE_SETSTP;
end
OP_XVR: begin
usb_data_o <= tx_buffer[tx_buffer_read_ptr];
tx_buffer_read_ptr <= tx_buffer_read_ptr + 1'b1;
// Set STP if everything delivered
if( tx_buffer_read_ptr + 1'b1 == tx_buffer_write_ptr ) state <= STATE_SETSTP;
end
default: state <= STATE_INIT;
endcase
end
end
STATE_WAITDIRH:
if( usb_dir ) begin
state <= STATE_WAITREAD;
end
STATE_WAITREAD:
begin
phy_reg_data <= usb_data_i;
state <= STATE_IDLE;
end
STATE_SETSTP:
begin
usb_data_o <= 8'd0;
usb_stp <= 1'b1;
state <= STATE_IDLE;
end
STATE_RECEIVE:
begin
if( ~usb_dir ) begin // TODO: Set signals
state <= STATE_IDLE;
end else begin
if( ~usb_nxt )
rxd_cmd <= usb_data_i;
else begin
rx_buffer[rx_buffer_write_ptr] <= usb_data_i;
rx_buffer_write_ptr <= rx_buffer_write_ptr + 1'd1;
end
end
end
default:
state <= STATE_INIT;
endcase
end
end
endmodule
|
module nco_sine_lut_V_rom (
addr0, ce0, q0, clk);
parameter DWIDTH = 16;
parameter AWIDTH = 12;
parameter MEM_SIZE = 4096;
input[AWIDTH-1:0] addr0;
input ce0;
output reg[DWIDTH-1:0] q0;
input clk;
reg [DWIDTH-1:0] ram[MEM_SIZE-1:0];
initial begin
$readmemh("./nco_sine_lut_V_rom.dat", ram);
end
always @(posedge clk)
begin
if (ce0)
begin
q0 <= ram[addr0];
end
end
endmodule
|
module nco_sine_lut_V(
reset,
clk,
address0,
ce0,
q0);
parameter DataWidth = 32'd16;
parameter AddressRange = 32'd4096;
parameter AddressWidth = 32'd12;
input reset;
input clk;
input[AddressWidth - 1:0] address0;
input ce0;
output[DataWidth - 1:0] q0;
nco_sine_lut_V_rom nco_sine_lut_V_rom_U(
.clk( clk ),
.addr0( address0 ),
.ce0( ce0 ),
.q0( q0 ));
endmodule
|
module sky130_fd_sc_hs__diode (
DIODE,
VPWR ,
VGND ,
VPB ,
VNB
);
input DIODE;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
endmodule
|
module fifo_test();
parameter IN_WIDTH = 32;
parameter OUT_WIDTH = 4;
reg reset;
reg [IN_WIDTH-1:0] data_in;
reg data_in_clock;
reg data_in_enable;
wire [OUT_WIDTH-1:0] data_out;
reg data_out_clock;
reg data_out_enable;
reg [OUT_WIDTH-1:0] tempdata;
integer i;
fifo #(
.DATA_IN_WIDTH (IN_WIDTH),
.DATA_OUT_WIDTH (OUT_WIDTH),
.FIFO_DEPTH (12)
)
ff (
.reset(reset),
// IN PORT
.data_in(data_in),
.data_in_clock(data_in_clock),
.data_in_enable(data_in_enable),
// OUT PORT
.data_out(data_out),
.data_out_clock(data_out_clock),
.data_out_enable(data_out_enable)
);
initial
begin
reset = 1;
data_in = 0;
data_in_clock = 0;
data_in_enable = 0;
data_out_clock = 0;
data_out_enable = 0;
tempdata = 0;
#15 reset = 0;
if (OUT_WIDTH > IN_WIDTH)
begin
for ( i = 0; i < (OUT_WIDTH/IN_WIDTH); i = i + 1)
begin
push(i);
end
pop(tempdata);
end
else
begin
push(1);
for ( i = 0; i < (IN_WIDTH/OUT_WIDTH); i = i + 1)
begin
pop(tempdata);
end
end
$finish;
end
always
#5 data_in_clock = ~data_in_clock;
always
#40 data_out_clock = ~data_out_clock;
task push;
input[IN_WIDTH-1:0] data;
begin
data_in = data;
data_in_enable = 1;
@(posedge data_in_clock);
#1 data_in_enable = 0;
$display("Pushed %x",data );
end
endtask
task pop;
output [OUT_WIDTH-1:0] data;
begin
data_out_enable = 1;
@(posedge data_out_clock);
#1 data_out_enable = 0;
data = data_out;
$display("Popped %x", data);
end
endtask
endmodule
|
module MMCME2_BASE (
CLKFBOUT,
CLKFBOUTB,
CLKOUT0,
CLKOUT0B,
CLKOUT1,
CLKOUT1B,
CLKOUT2,
CLKOUT2B,
CLKOUT3,
CLKOUT3B,
CLKOUT4,
CLKOUT5,
CLKOUT6,
LOCKED,
CLKFBIN,
CLKIN1,
PWRDWN,
RST
);
parameter BANDWIDTH = "OPTIMIZED";
parameter real CLKFBOUT_MULT_F = 5.000;
parameter real CLKFBOUT_PHASE = 0.000;
parameter real CLKIN1_PERIOD = 0.000;
parameter real CLKOUT0_DIVIDE_F = 1.000;
parameter real CLKOUT0_DUTY_CYCLE = 0.500;
parameter real CLKOUT0_PHASE = 0.000;
parameter integer CLKOUT1_DIVIDE = 1;
parameter real CLKOUT1_DUTY_CYCLE = 0.500;
parameter real CLKOUT1_PHASE = 0.000;
parameter integer CLKOUT2_DIVIDE = 1;
parameter real CLKOUT2_DUTY_CYCLE = 0.500;
parameter real CLKOUT2_PHASE = 0.000;
parameter integer CLKOUT3_DIVIDE = 1;
parameter real CLKOUT3_DUTY_CYCLE = 0.500;
parameter real CLKOUT3_PHASE = 0.000;
parameter CLKOUT4_CASCADE = "FALSE";
parameter integer CLKOUT4_DIVIDE = 1;
parameter real CLKOUT4_DUTY_CYCLE = 0.500;
parameter real CLKOUT4_PHASE = 0.000;
parameter integer CLKOUT5_DIVIDE = 1;
parameter real CLKOUT5_DUTY_CYCLE = 0.500;
parameter real CLKOUT5_PHASE = 0.000;
parameter integer CLKOUT6_DIVIDE = 1;
parameter real CLKOUT6_DUTY_CYCLE = 0.500;
parameter real CLKOUT6_PHASE = 0.000;
parameter integer DIVCLK_DIVIDE = 1;
parameter real REF_JITTER1 = 0.010;
parameter STARTUP_WAIT = "FALSE";
`ifdef XIL_TIMING
parameter LOC = "UNPLACED";
`endif
output CLKFBOUT;
output CLKFBOUTB;
output CLKOUT0;
output CLKOUT0B;
output CLKOUT1;
output CLKOUT1B;
output CLKOUT2;
output CLKOUT2B;
output CLKOUT3;
output CLKOUT3B;
output CLKOUT4;
output CLKOUT5;
output CLKOUT6;
output LOCKED;
input CLKFBIN;
input CLKIN1;
input PWRDWN;
input RST;
// define constants
localparam MODULE_NAME = "MMCME2_BASE";
wire OPEN_DRDY;
wire OPEN_PSDONE;
wire OPEN_FBS;
wire OPEN_INS;
wire [15:0] OPEN_DO;
MMCME2_ADV #(
.BANDWIDTH(BANDWIDTH),
.CLKFBOUT_MULT_F(CLKFBOUT_MULT_F),
.CLKFBOUT_PHASE(CLKFBOUT_PHASE),
.CLKIN1_PERIOD(CLKIN1_PERIOD),
.CLKIN2_PERIOD(10),
.CLKOUT0_DIVIDE_F(CLKOUT0_DIVIDE_F),
.CLKOUT0_DUTY_CYCLE(CLKOUT0_DUTY_CYCLE),
.CLKOUT0_PHASE(CLKOUT0_PHASE),
.CLKOUT1_DIVIDE(CLKOUT1_DIVIDE),
.CLKOUT1_DUTY_CYCLE(CLKOUT1_DUTY_CYCLE),
.CLKOUT1_PHASE(CLKOUT1_PHASE),
.CLKOUT2_DIVIDE(CLKOUT2_DIVIDE),
.CLKOUT2_DUTY_CYCLE(CLKOUT2_DUTY_CYCLE),
.CLKOUT2_PHASE(CLKOUT2_PHASE),
.CLKOUT3_DIVIDE(CLKOUT3_DIVIDE),
.CLKOUT3_DUTY_CYCLE(CLKOUT3_DUTY_CYCLE),
.CLKOUT3_PHASE(CLKOUT3_PHASE),
.CLKOUT4_CASCADE(CLKOUT4_CASCADE),
.CLKOUT4_DIVIDE(CLKOUT4_DIVIDE),
.CLKOUT4_DUTY_CYCLE(CLKOUT4_DUTY_CYCLE),
.CLKOUT4_PHASE(CLKOUT4_PHASE),
.CLKOUT5_DIVIDE(CLKOUT5_DIVIDE),
.CLKOUT5_DUTY_CYCLE(CLKOUT5_DUTY_CYCLE),
.CLKOUT5_PHASE(CLKOUT5_PHASE),
.CLKOUT6_DIVIDE(CLKOUT6_DIVIDE),
.CLKOUT6_DUTY_CYCLE(CLKOUT6_DUTY_CYCLE),
.CLKOUT6_PHASE(CLKOUT6_PHASE),
.DIVCLK_DIVIDE(DIVCLK_DIVIDE),
.REF_JITTER1(REF_JITTER1),
.STARTUP_WAIT(STARTUP_WAIT)
) mmcm_adv_1 (
.CLKFBOUT (CLKFBOUT),
.CLKFBOUTB (CLKFBOUTB),
.CLKFBSTOPPED(OPEN_FBS),
.CLKINSTOPPED(OPEN_INS),
.CLKOUT0 (CLKOUT0),
.CLKOUT0B (CLKOUT0B),
.CLKOUT1 (CLKOUT1),
.CLKOUT1B (CLKOUT1B),
.CLKOUT2 (CLKOUT2),
.CLKOUT2B (CLKOUT2B),
.CLKOUT3 (CLKOUT3),
.CLKOUT3B (CLKOUT3B),
.CLKOUT4 (CLKOUT4),
.CLKOUT5 (CLKOUT5),
.CLKOUT6 (CLKOUT6),
.DO (OPEN_DO),
.DRDY (OPEN_DRDY),
.LOCKED (LOCKED),
.PSDONE(OPEN_PSDONE),
.CLKFBIN (CLKFBIN),
.CLKIN1 (CLKIN1),
.CLKIN2 (1'b0),
.CLKINSEL(1'b1),
.DADDR (7'b0),
.DCLK (1'b0),
.DEN (1'b0),
.DI (16'b0),
.DWE (1'b0),
.PSCLK(1'b0),
.PSEN(1'b0),
.PSINCDEC(1'b0),
.PWRDWN(PWRDWN),
.RST (RST)
);
endmodule
|
module RAM(
i_addr,
i_enable_x,
i_write_x,
i_data,
o_data);
parameter delay = 10;
parameter depth = 16;
parameter width = 8;
input [depth - 1:0] i_addr;
input i_enable_x;
input i_write_x;
input [width - 1:0] i_data;
output [width - 1:0] o_data;
reg [width - 1:0] o_data;
reg [width - 1:0] r_ram[0:2**depth];
reg [depth - 1:0] r_addr;
reg r_enable_x;
reg r_write_x;
reg [width - 1:0] r_data;
always r_addr = #delay i_addr;
always r_enable_x = #delay i_enable_x;
always r_write_x = #delay i_write_x;
always r_data = #delay i_data;
always @ (r_addr or r_enable_x or r_write_x or r_data) begin
if (r_enable_x) begin
o_data <= {width{1'bz}};
end else if (r_write_x) begin
o_data <= r_ram[r_addr];
end else begin
o_data <= {width{1'bx}};
r_ram[r_addr] <= r_data;
end
end
endmodule
|
module EP_MEM (
clk,
a_rd_a_i_0, // [8:0] Port A Read Address Bank 0
a_rd_d_o_0, // [31:0] Port A Read Data Bank 0
a_rd_en_i_0, // Port A Read Enable Bank 0
b_wr_a_i_0, // [8:0] Port B Write Address Bank 0
b_wr_d_i_0, // [31:0] Port B Write Data Bank 0
b_wr_en_i_0, // Port B Write Enable Bank 0
b_rd_d_o_0, // [31:0] Port B Read Data Bank 0
b_rd_en_i_0, // Port B Read Enable Bank 0
a_rd_a_i_1, // [8:0] Port A Read Address Bank 1
a_rd_d_o_1, // [31:0] Port A Read Data Bank 1
a_rd_en_i_1,
b_wr_a_i_1, // [8:0] Port B Write Address Bank 1
b_wr_d_i_1, // [31:0] Port B Write Data Bank 1
b_wr_en_i_1, // Port B Write Enable Bank 1
b_rd_d_o_1, // [31:0] Port B Read Data Bank 1
b_rd_en_i_1, // Port B Read Enable Bank 1
a_rd_a_i_2, // [8:0] Port A Read Address Bank 2
a_rd_d_o_2, // [31:0] Port A Read Data Bank 2
a_rd_en_i_2,
b_wr_a_i_2, // [8:0] Port B Write Address Bank 2
b_wr_d_i_2, // [31:0] Port B Write Data Bank 2
b_wr_en_i_2, // Port B Write Enable Bank 2
b_rd_d_o_2, // [31:0] Port B Read Data Bank 2
b_rd_en_i_2, // Port B Read Enable Bank 2
a_rd_a_i_3, // [8:0] Port A Read Address Bank 3
a_rd_d_o_3, // [31:0] Port A Read Data Bank 3
a_rd_en_i_3,
b_wr_a_i_3, // [8:0] Port B Write Address Bank 3
b_wr_d_i_3, // [31:0] Port B Write Data Bank 3
b_wr_en_i_3, // Port B Write Enable Bank 3
b_rd_d_o_3, // [31:0] Port B Read Data Bank 3
b_rd_en_i_3 // Port B Read Enable Bank 3
);
input clk;
input [08:00] a_rd_a_i_0;
output [31:00] a_rd_d_o_0;
input a_rd_en_i_0;
input [08:00] b_wr_a_i_0;
input [31:00] b_wr_d_i_0;
input b_wr_en_i_0;
output [31:00] b_rd_d_o_0;
input b_rd_en_i_0;
input [08:00] a_rd_a_i_1;
output [31:00] a_rd_d_o_1;
input a_rd_en_i_1;
input [08:00] b_wr_a_i_1;
input [31:00] b_wr_d_i_1;
input b_wr_en_i_1;
output [31:00] b_rd_d_o_1;
input b_rd_en_i_1;
input [08:00] a_rd_a_i_2;
output [31:00] a_rd_d_o_2;
input a_rd_en_i_2;
input [08:00] b_wr_a_i_2;
input [31:00] b_wr_d_i_2;
input b_wr_en_i_2;
output [31:00] b_rd_d_o_2;
input b_rd_en_i_2;
input [08:00] a_rd_a_i_3;
output [31:00] a_rd_d_o_3;
input a_rd_en_i_3;
input [08:00] b_wr_a_i_3;
input [31:00] b_wr_d_i_3;
input b_wr_en_i_3;
output [31:00] b_rd_d_o_3;
input b_rd_en_i_3;
//----------------------------------------------------------------
//
// 4 x 512 DWs Buffer Banks (512 x 32 bits + 512 x 4 bits)
// 1 each for IO, Mem32, Mem64 and EROM
//----------------------------------------------------------------
RAMB36 #(
.DOA_REG(1), // Optional output registers on A port (0 or 1)
.DOB_REG(1), // Optional output registers on B port (0 or 1)
.INIT_A(36'h000000000), // Initial values on A output port
.INIT_B(36'h000000000), // Initial values on B output port
.RAM_EXTENSION_A("NONE"), // "UPPER", "LOWER" or "NONE" when cascaded
.RAM_EXTENSION_B("NONE"), // "UPPER", "LOWER" or "NONE" when cascaded
.READ_WIDTH_A(36), // Valid values are 1, 2, 4, 9, 18, or 36
.READ_WIDTH_B(36), // Valid values are 1, 2, 4, 9, 18, or 36
.SIM_COLLISION_CHECK("ALL"), // Collision check enable "ALL", "WARNING_ONLY",
// "GENERATE_X_ONLY" or "NONE
.SRVAL_A(36'h000000000), // Set/Reset value for A port output
.SRVAL_B(36'h000000000), // Set/Reset value for B port output
.WRITE_MODE_A("WRITE_FIRST"), // "WRITE_FIRST", "READ_FIRST", or "NO_CHANGE
.WRITE_MODE_B("WRITE_FIRST"), // "WRITE_FIRST", "READ_FIRST", or "NO_CHANGE
.WRITE_WIDTH_A(36), // Valid values are 1, 2, 4, 9, 18, or 36
.WRITE_WIDTH_B(36), // Valid values are 1, 2, 4, 9, 18, or 36
// The following INIT_xx declarations specify the initial contents of the RAM
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
// The next set of INITP_xx are for the parity bits
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000)
) ep_io_mem_inst (
.DOA(a_rd_d_o_0[31:0]), // 32-bit A port data output
.DOB(b_rd_d_o_0[31:0]), // 32-bit B port data output
.DOPA(), // 4-bit A port parity data output
.DOPB(), // 4-bit B port parity data output
.ADDRA({1'b0,a_rd_a_i_0[8:0],6'b0}), // 16-bit A port address input
.ADDRB({1'b0,b_wr_a_i_0[8:0],6'b0}), // 16-bit B port address input
.CLKA(clk), // 1-bit A port clock input
.CLKB(clk), // 1-bit B port clock input
.DIA(32'b0), // 32-bit A port data input
.DIB(b_wr_d_i_0[31:0]), // 32-bit B port data input
.DIPA(4'b0000), // 4-bit A port parity data input
.DIPB(4'b0), // 4-bit B port parity data input
.ENA(a_rd_en_i_0), // 1-bit A port enable input
.ENB(b_rd_en_i_0), // 1-bit B port enable input
.REGCEA(1'b1), // 1-bit A port register enable input
.REGCEB(1'b1), // 1-bit B port register enable input
.SSRA(1'b0), // 1-bit A port set/reset input
.SSRB(1'b0), // 1-bit B port set/reset input
.WEA(4'b0), // 4-bit A port write enable input
.WEB({b_wr_en_i_0, b_wr_en_i_0, b_wr_en_i_0, b_wr_en_i_0}), // 4-bit B port write enable input
.CASCADEINLATA (1'b0),
.CASCADEINREGA (1'b0),
.CASCADEOUTLATA (),
.CASCADEOUTREGA (),
.CASCADEINLATB (1'b0),
.CASCADEINREGB (1'b0),
.CASCADEOUTLATB (),
.CASCADEOUTREGB ()
);
RAMB36 #(
.DOA_REG(1), // Optional output registers on A port (0 or 1)
.DOB_REG(1), // Optional output registers on B port (0 or 1)
.INIT_A(36'h000000000), // Initial values on A output port
.INIT_B(36'h000000000), // Initial values on B output port
.RAM_EXTENSION_A("NONE"), // "UPPER", "LOWER" or "NONE" when cascaded
.RAM_EXTENSION_B("NONE"), // "UPPER", "LOWER" or "NONE" when cascaded
.READ_WIDTH_A(36), // Valid values are 1, 2, 4, 9, 18, or 36
.READ_WIDTH_B(36), // Valid values are 1, 2, 4, 9, 18, or 36
.SIM_COLLISION_CHECK("ALL"), // Collision check enable "ALL", "WARNING_ONLY",
// "GENERATE_X_ONLY" or "NONE
.SRVAL_A(36'h000000000), // Set/Reset value for A port output
.SRVAL_B(36'h000000000), // Set/Reset value for B port output
.WRITE_MODE_A("WRITE_FIRST"), // "WRITE_FIRST", "READ_FIRST", or "NO_CHANGE
.WRITE_MODE_B("WRITE_FIRST"), // "WRITE_FIRST", "READ_FIRST", or "NO_CHANGE
.WRITE_WIDTH_A(36), // Valid values are 1, 2, 4, 9, 18, or 36
.WRITE_WIDTH_B(36), // Valid values are 1, 2, 4, 9, 18, or 36
// The following INIT_xx declarations specify the initial contents of the RAM
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
// The next set of INITP_xx are for the parity bits
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000)
) ep_mem32_inst (
.DOA(a_rd_d_o_1[31:0]), // 32-bit A port data output
.DOB(b_rd_d_o_1[31:0]), // 32-bit B port data output
.DOPA(), // 4-bit A port parity data output
.DOPB(), // 4-bit B port parity data output
.ADDRA({1'b0,a_rd_a_i_1[8:0],6'b0}), // 16-bit A port address input
.ADDRB({1'b0,b_wr_a_i_1[8:0],6'b0}), // 16-bit B port address input
.CLKA(clk), // 1-bit A port clock input
.CLKB(clk), // 1-bit B port clock input
.DIA(32'b0), // 32-bit A port data input
.DIB(b_wr_d_i_1[31:0]), // 32-bit B port data input
.DIPA(4'b0000), // 4-bit A port parity data input
.DIPB(4'b0), // 4-bit B port parity data input
.ENA(a_rd_en_i_1), // 1-bit A port enable input
.ENB(b_rd_en_i_1), // 1-bit B port enable input
.REGCEA(1'b1), // 1-bit A port register enable input
.REGCEB(1'b1), // 1-bit B port register enable input
.SSRA(1'b0), // 1-bit A port set/reset input
.SSRB(1'b0), // 1-bit B port set/reset input
.WEA(4'b0), // 4-bit A port write enable input
.WEB({b_wr_en_i_1, b_wr_en_i_1, b_wr_en_i_1, b_wr_en_i_1}), // 4-bit B port write enable input
.CASCADEINLATA (1'b0),
.CASCADEINREGA (1'b0),
.CASCADEOUTLATA (),
.CASCADEOUTREGA (),
.CASCADEINLATB (1'b0),
.CASCADEINREGB (1'b0),
.CASCADEOUTLATB (),
.CASCADEOUTREGB ()
);
RAMB36 #(
.DOA_REG(1), // Optional output registers on A port (0 or 1)
.DOB_REG(1), // Optional output registers on B port (0 or 1)
.INIT_A(36'h000000000), // Initial values on A output port
.INIT_B(36'h000000000), // Initial values on B output port
.RAM_EXTENSION_A("NONE"), // "UPPER", "LOWER" or "NONE" when cascaded
.RAM_EXTENSION_B("NONE"), // "UPPER", "LOWER" or "NONE" when cascaded
.READ_WIDTH_A(36), // Valid values are 1, 2, 4, 9, 18, or 36
.READ_WIDTH_B(36), // Valid values are 1, 2, 4, 9, 18, or 36
.SIM_COLLISION_CHECK("ALL"), // Collision check enable "ALL", "WARNING_ONLY",
// "GENERATE_X_ONLY" or "NONE
.SRVAL_A(36'h000000000), // Set/Reset value for A port output
.SRVAL_B(36'h000000000), // Set/Reset value for B port output
.WRITE_MODE_A("WRITE_FIRST"), // "WRITE_FIRST", "READ_FIRST", or "NO_CHANGE
.WRITE_MODE_B("WRITE_FIRST"), // "WRITE_FIRST", "READ_FIRST", or "NO_CHANGE
.WRITE_WIDTH_A(36), // Valid values are 1, 2, 4, 9, 18, or 36
.WRITE_WIDTH_B(36), // Valid values are 1, 2, 4, 9, 18, or 36
// The following INIT_xx declarations specify the initial contents of the RAM
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
// The next set of INITP_xx are for the parity bits
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000)
) ep_mem64_inst (
.DOA(a_rd_d_o_2[31:0]), // 32-bit A port data output
.DOB(b_rd_d_o_2[31:0]), // 32-bit B port data output
.DOPA(), // 4-bit A port parity data output
.DOPB(), // 4-bit B port parity data output
.ADDRA({1'b0,a_rd_a_i_2[8:0],6'b0}), // 16-bit A port address input
.ADDRB({1'b0,b_wr_a_i_2[8:0],6'b0}), // 16-bit B port address input
.CLKA(clk), // 1-bit A port clock input
.CLKB(clk), // 1-bit B port clock input
.DIA(32'b0), // 32-bit A port data input
.DIB(b_wr_d_i_2[31:0]), // 32-bit B port data input
.DIPA(4'b0000), // 4-bit A port parity data input
.DIPB(4'b0), // 4-bit B port parity data input
.ENA(a_rd_en_i_2), // 1-bit A port enable input
.ENB(b_rd_en_i_2), // 1-bit B port enable input
.REGCEA(1'b1), // 1-bit A port register enable input
.REGCEB(1'b1), // 1-bit B port register enable input
.SSRA(1'b0), // 1-bit A port set/reset input
.SSRB(1'b0), // 1-bit B port set/reset input
.WEA(4'b0), // 4-bit A port write enable input
.WEB({b_wr_en_i_2, b_wr_en_i_2, b_wr_en_i_2, b_wr_en_i_2}), // 4-bit B port write enable input
.CASCADEINLATA (1'b0),
.CASCADEINREGA (1'b0),
.CASCADEOUTLATA (),
.CASCADEOUTREGA (),
.CASCADEINLATB (1'b0),
.CASCADEINREGB (1'b0),
.CASCADEOUTLATB (),
.CASCADEOUTREGB ()
);
RAMB36 #(
.DOA_REG(1), // Optional output registers on A port (0 or 1)
.DOB_REG(1), // Optional output registers on B port (0 or 1)
.INIT_A(36'h000000000), // Initial values on A output port
.INIT_B(36'h000000000), // Initial values on B output port
.RAM_EXTENSION_A("NONE"), // "UPPER", "LOWER" or "NONE" when cascaded
.RAM_EXTENSION_B("NONE"), // "UPPER", "LOWER" or "NONE" when cascaded
.READ_WIDTH_A(36), // Valid values are 1, 2, 4, 9, 18, or 36
.READ_WIDTH_B(36), // Valid values are 1, 2, 4, 9, 18, or 36
.SIM_COLLISION_CHECK("ALL"), // Collision check enable "ALL", "WARNING_ONLY",
// "GENERATE_X_ONLY" or "NONE
.SRVAL_A(36'h000000000), // Set/Reset value for A port output
.SRVAL_B(36'h000000000), // Set/Reset value for B port output
.WRITE_MODE_A("WRITE_FIRST"), // "WRITE_FIRST", "READ_FIRST", or "NO_CHANGE
.WRITE_MODE_B("WRITE_FIRST"), // "WRITE_FIRST", "READ_FIRST", or "NO_CHANGE
.WRITE_WIDTH_A(36), // Valid values are 1, 2, 4, 9, 18, or 36
.WRITE_WIDTH_B(36), // Valid values are 1, 2, 4, 9, 18, or 36
// The following INIT_xx declarations specify the initial contents of the RAM
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
// The next set of INITP_xx are for the parity bits
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000)
) ep_mem_erom_inst (
.DOA(a_rd_d_o_3[31:0]), // 32-bit A port data output
.DOB(b_rd_d_o_3[31:0]), // 32-bit B port data output
.DOPA(), // 4-bit A port parity data output
.DOPB(), // 4-bit B port parity data output
.ADDRA({1'b0,a_rd_a_i_3[8:0],6'b0}), // 16-bit A port address input
.ADDRB({1'b0,b_wr_a_i_3[8:0],6'b0}), // 16-bit B port address input
.CLKA(clk), // 1-bit A port clock input
.CLKB(clk), // 1-bit B port clock input
.DIA(32'b0), // 32-bit A port data input
.DIB(b_wr_d_i_3[31:0]), // 32-bit B port data input
.DIPA(4'b0000), // 4-bit A port parity data input
.DIPB(4'b0), // 4-bit B port parity data input
.ENA(a_rd_en_i_3), // 1-bit A port enable input
.ENB(b_rd_en_i_3), // 1-bit B port enable input
.REGCEA(1'b1), // 1-bit A port register enable input
.REGCEB(1'b1), // 1-bit B port register enable input
.SSRA(1'b0), // 1-bit A port set/reset input
.SSRB(1'b0), // 1-bit B port set/reset input
.WEA(4'b0), // 4-bit A port write enable input
.WEB({b_wr_en_i_3, b_wr_en_i_3, b_wr_en_i_3, b_wr_en_i_3}), // 4-bit B port write enable input
.CASCADEINLATA (1'b0),
.CASCADEINREGA (1'b0),
.CASCADEOUTLATA (),
.CASCADEOUTREGA (),
.CASCADEINLATB (1'b0),
.CASCADEINREGB (1'b0),
.CASCADEOUTLATB (),
.CASCADEOUTREGB ()
);
endmodule
|
module lr0(clk, addr, data_in, data_out, we, en, reset);
input clk;
input [13:2] addr;
input [31:0] data_in;
output [31:0] data_out;
input [3:0] we;
input en;
input reset;
RAMB16_S4_altera localram0(
.aclr (reset),
.address (addr[13:2]),
.clken (en),
.clock (clk),
.data (data_in[3:0]),
.wren (we[0]),
.q (data_out[3:0])
);
defparam localram0.init_file = "lr_00.mif";
RAMB16_S4_altera localram1(
.aclr (reset),
.address (addr[13:2]),
.clken (en),
.clock (clk),
.data (data_in[7:4]),
.wren (we[0]),
.q (data_out[7:4])
);
defparam localram1.init_file = "lr_11.mif";
RAMB16_S4_altera localram2(
.aclr (reset),
.address (addr[13:2]),
.clken (en),
.clock (clk),
.data (data_in[11:8]),
.wren (we[1]),
.q (data_out[11:8])
);
defparam localram2.init_file = "lr_22.mif";
RAMB16_S4_altera localram3(
.aclr (reset),
.address (addr[13:2]),
.clken (en),
.clock (clk),
.data (data_in[15:12]),
.wren (we[1]),
.q (data_out[15:12])
);
defparam localram3.init_file = "lr_33.mif";
RAMB16_S4_altera localram4(
.aclr (reset),
.address (addr[13:2]),
.clken (en),
.clock (clk),
.data (data_in[19:16]),
.wren (we[2]),
.q (data_out[19:16])
);
defparam localram4.init_file = "lr_44.mif";
RAMB16_S4_altera localram5(
.aclr (reset),
.address (addr[13:2]),
.clken (en),
.clock (clk),
.data (data_in[23:20]),
.wren (we[2]),
.q (data_out[23:20])
);
defparam localram5.init_file = "lr_55.mif";
RAMB16_S4_altera localram6(
.aclr (reset),
.address (addr[13:2]),
.clken (en),
.clock (clk),
.data (data_in[27:24]),
.wren (we[3]),
.q (data_out[27:24])
);
defparam localram6.init_file = "lr_66.mif";
RAMB16_S4_altera localram7(
.aclr (reset),
.address (addr[13:2]),
.clken (en),
.clock (clk),
.data (data_in[31:28]),
.wren (we[3]),
.q (data_out[31:28])
);
defparam localram7.init_file = "lr_77.mif";
endmodule
|
module sky130_fd_sc_hs__a2bb2o (
//# {{data|Data Signals}}
input A1_N,
input A2_N,
input B1 ,
input B2 ,
output X ,
//# {{power|Power}}
input VPWR,
input VGND
);
endmodule
|
module sky130_fd_sc_hs__o21bai_2 (
Y ,
A1 ,
A2 ,
B1_N,
VPWR,
VGND
);
output Y ;
input A1 ;
input A2 ;
input B1_N;
input VPWR;
input VGND;
sky130_fd_sc_hs__o21bai base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1_N(B1_N),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
|
module sky130_fd_sc_hs__o21bai_2 (
Y ,
A1 ,
A2 ,
B1_N
);
output Y ;
input A1 ;
input A2 ;
input B1_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__o21bai base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1_N(B1_N)
);
endmodule
|
module sky130_fd_sc_ls__xnor3 (
X,
A,
B,
C
);
output X;
input A;
input B;
input C;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
|
module sky130_fd_sc_hdll__o21ba_1 (
X ,
A1 ,
A2 ,
B1_N,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input B1_N;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hdll__o21ba base (
.X(X),
.A1(A1),
.A2(A2),
.B1_N(B1_N),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
|
module sky130_fd_sc_hdll__o21ba_1 (
X ,
A1 ,
A2 ,
B1_N
);
output X ;
input A1 ;
input A2 ;
input B1_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hdll__o21ba base (
.X(X),
.A1(A1),
.A2(A2),
.B1_N(B1_N)
);
endmodule
|
module scheduler1_commit_entry #(
parameter ENTRY_ID = 6'h00
)(
//System
input wire iCLOCK,
input wire inRESET,
//LOCK
input wire iLOCK,
//Exception
input wire iRESTART_VALID,
//Regist
input wire [5:0] iREGIST_POINTER,
input wire iREGIST_0_VALID,
input wire iREGIST_0_MAKE_FLAGS,
input wire iREGIST_0_WRITEBACK,
input wire [3:0] iREGIST_0_FLAGS_PREG_POINTER,
input wire [5:0] iREGIST_0_DEST_PREG_POINTER,
input wire [4:0] iREGIST_0_DEST_LREG_POINTER,
input wire iREGIST_0_DEST_SYSREG,
input wire iREGIST_0_EX_BRANCH,
input wire iREGIST_1_VALID,
input wire iREGIST_1_MAKE_FLAGS,
input wire iREGIST_1_WRITEBACK,
input wire [3:0] iREGIST_1_FLAGS_PREG_POINTER,
input wire [5:0] iREGIST_1_DEST_PREG_POINTER,
input wire [4:0] iREGIST_1_DEST_LREG_POINTER,
input wire iREGIST_1_DEST_SYSREG,
input wire iREGIST_1_EX_BRANCH,
input wire [31:0] iREGIST_PC,
//Commit Pointer
input wire iCOMMIT_VALID,
//EX-END
input wire iEXEND_ALU0_VALID,
input wire [5:0] iEXEND_ALU0_COMMIT_TAG,
input wire iEXEND_ALU1_VALID,
input wire [5:0] iEXEND_ALU1_COMMIT_TAG,
input wire iEXEND_ALU2_VALID,
input wire [5:0] iEXEND_ALU2_COMMIT_TAG,
input wire iEXEND_ALU3_VALID,
input wire [5:0] iEXEND_ALU3_COMMIT_TAG,
//Infomation
output wire oINFO_VALID,
output wire oINFO_MAKE_FLAGS_VALID,
output wire oINFO_WRITEBACK_VALID,
output wire [31:0] oINFO_PC,
output wire [3:0] oINFO_FLAGS_PREG_POINTER,
output wire [5:0] oINFO_DEST_PREG_POINTER,
output wire [4:0] oINFO_DEST_LREG_POINTER,
output wire oINFO_DEST_SYSREG,
output wire oINFO_EX_BRANCH,
output wire oINFO_EX_END,
output wire oINFO_FREE
);
/****************************************
Previous <-> This
****************************************/
/*List Format
PC, EX_END(LDST_END)
*/
reg [1:0] b_state;
reg [31:0] b_pc;
reg b_make_flags_validl;
reg b_writeback;
reg [3:0] b_flags_preg_pointer;
reg [5:0] b_destination_regname;
reg [4:0] b_logic_destination;
reg b_dest_sysreg;
reg b_ex_branch;
wire [5:0] w_regist_pointer0;
wire [5:0] w_regist_pointer1;
assign w_regist_pointer0 = iREGIST_POINTER;
assign w_regist_pointer1 = iREGIST_POINTER + 6'h1;
always@(posedge iCLOCK or negedge inRESET)begin
if(!inRESET)begin
b_state <= 2'h0;
b_pc <= {32{1'b0}};
b_make_flags_validl <= 1'b0;
b_writeback <= 1'b0;
b_flags_preg_pointer <= 4'h0;
b_destination_regname <= {6{1'b0}};
b_logic_destination <= {5{1'b0}};
b_dest_sysreg <= 1'b0;
b_ex_branch <= 1'b0;
end
else if(b_state == 2'h3 || iRESTART_VALID)begin
b_state <= 2'h0;
b_pc <= {32{1'b0}};
b_make_flags_validl <= 1'b0;
b_writeback <= 1'b0;
b_flags_preg_pointer <= 4'h0;
b_destination_regname <= {6{1'b0}};
b_logic_destination <= {5{1'b0}};
b_dest_sysreg <= 1'b0;
b_ex_branch <= 1'b0;
end
else begin
case(b_state)
2'h0 : //Entry Regist Wait
begin
if(!iLOCK)begin
if(iREGIST_0_VALID && ENTRY_ID[5:0] == w_regist_pointer0)begin
b_state <= 2'h1;
b_pc <= iREGIST_PC;
b_make_flags_validl <= iREGIST_0_MAKE_FLAGS;
b_writeback <= iREGIST_0_WRITEBACK;
b_flags_preg_pointer <= iREGIST_0_FLAGS_PREG_POINTER;
b_destination_regname <= iREGIST_0_DEST_PREG_POINTER;
b_logic_destination <= iREGIST_0_DEST_LREG_POINTER;
b_dest_sysreg <= iREGIST_0_DEST_SYSREG;
b_ex_branch <= iREGIST_0_EX_BRANCH;
end
else if(iREGIST_1_VALID && ENTRY_ID[5:0] == w_regist_pointer1)begin
b_state <= 2'h1;
b_pc <= iREGIST_PC + 32'h4;
b_make_flags_validl <= iREGIST_1_MAKE_FLAGS;
b_writeback <= iREGIST_1_WRITEBACK;
b_flags_preg_pointer <= iREGIST_1_FLAGS_PREG_POINTER;
b_destination_regname <= iREGIST_1_DEST_PREG_POINTER;
b_logic_destination <= iREGIST_1_DEST_LREG_POINTER;
b_dest_sysreg <= iREGIST_1_DEST_SYSREG;
b_ex_branch <= iREGIST_1_EX_BRANCH;
end
end
end
2'h1 : //Execution End Wait
begin
if(iEXEND_ALU0_VALID && iEXEND_ALU0_COMMIT_TAG == ENTRY_ID[5:0])begin
b_state <= 2'h2;
end
else if(iEXEND_ALU1_VALID && iEXEND_ALU1_COMMIT_TAG == ENTRY_ID[5:0])begin
b_state <= 2'h2;
end
else if(iEXEND_ALU2_VALID && iEXEND_ALU2_COMMIT_TAG == ENTRY_ID[5:0])begin
b_state <= 2'h2;
end
else if(iEXEND_ALU3_VALID && iEXEND_ALU3_COMMIT_TAG == ENTRY_ID[5:0])begin
b_state <= 2'h2;
end
end
default :
begin
if(iCOMMIT_VALID)begin
b_state [1:0] <= 2'h0;
//b_pc <= {32{1'b0}};
b_make_flags_validl <= 1'b0;
b_writeback <= 1'b0;
b_flags_preg_pointer <= 4'h0;
b_destination_regname <= {6{1'b0}};
b_logic_destination <= {5{1'b0}};
b_dest_sysreg <= 1'b0;
b_ex_branch <= b_ex_branch;
end
end
endcase
//end
end
end //always
assign oINFO_VALID = (b_state == 2'h1 || b_state == 2'h2)? 1'b1 : 1'b0;
assign oINFO_MAKE_FLAGS_VALID = b_make_flags_validl;
assign oINFO_WRITEBACK_VALID = b_writeback;
assign oINFO_PC = b_pc;
assign oINFO_FLAGS_PREG_POINTER = b_flags_preg_pointer;
assign oINFO_DEST_PREG_POINTER = b_destination_regname;
assign oINFO_DEST_LREG_POINTER = b_logic_destination;
assign oINFO_DEST_SYSREG = b_dest_sysreg;
assign oINFO_EX_BRANCH = b_ex_branch;
assign oINFO_EX_END = (b_state == 2'h2)? 1'b1 : 1'b0;
assign oINFO_FREE = (iRESTART_VALID && ((b_state == 2'h1) || (b_state == 2'h2)))? 1'b1 : 1'b0;
endmodule
|
module sky130_fd_sc_hs__o32ai (
VPWR,
VGND,
Y ,
A1 ,
A2 ,
A3 ,
B1 ,
B2
);
// Module ports
input VPWR;
input VGND;
output Y ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input B2 ;
// Local signals
wire B1 nor0_out ;
wire B1 nor1_out ;
wire or0_out_Y ;
wire u_vpwr_vgnd0_out_Y;
// Name Output Other arguments
nor nor0 (nor0_out , A3, A1, A2 );
nor nor1 (nor1_out , B1, B2 );
or or0 (or0_out_Y , nor1_out, nor0_out );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_Y, or0_out_Y, VPWR, VGND);
buf buf0 (Y , u_vpwr_vgnd0_out_Y );
endmodule
|
module header
// Internal signals
//
// Generated Signal List
//
//
// End of Generated Signal List
//
// %COMPILER_OPTS%
//
// Generated Signal Assignments
//
//
// Generated Instances and Port Mappings
//
endmodule
|
module definition
// -----------------------------
assign writeif_accepted = writeif_ready & writeif_valid;
assign buffwrite_address = writeif_address;
assign buffwrite_valid = writeif_accepted;
assign buffread_address = readif_address;
assign buffread_valid = readif_valid;
always @ (*)
begin
if (writeif_address_blocked)
begin
// can't write ahead of lowest address currently tracked by dataid array
writeif_ready = 1'b0;
end
else
begin
// buffer is full when every location has been written
writeif_ready = ~&buffer_valid_counter;
end
end
// generate buffread_datavalid.
// data is valid one cycle after adddress is presented to the buffer
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (~ctl_reset_n)
begin
buffread_datavalid <= 0;
end
else
begin
buffread_datavalid <= buffread_valid;
end
end
// genvar i;
// generate
// for (i = 0; i < CTL_BUFFER_DEPTH; i = i + 1)
// begin : gen_mux_buffer_valid_array_signals
// wire [CFG_BUFFER_ADDR_WIDTH-1:0] gen_buffer_address = i;
// always @ (posedge ctl_clk or negedge ctl_reset_n)
// begin
// if (~ctl_reset_n)
// begin
// //reset state ...
// buffer_valid_array [i] <= 0;
// end
// else
// begin
// //active state ...
// // write & read to same location won't happen on same time
// // write
// if ( (writeif_address == gen_buffer_address) & writeif_accepted)
// begin
// buffer_valid_array[i] <= 1;
// end
// // read
// if ( (readif_address== gen_buffer_address) & readif_valid)
// begin
// buffer_valid_array[i] <= 0;
// end
// end
// end
// always @ (*)
// begin
// // mano - fmax !
// if ( (writeif_address == gen_buffer_address) & buffer_valid_array[i] )
// begin
// mux_writeif_ready[i] = 0;
// end
// else
// begin
// mux_writeif_ready[i] = 1;
// end
// end
// end
// endgenerate
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (~ctl_reset_n)
begin
buffer_valid_counter <= 0;
err_buffer_valid_counter_overflow <= 0;
end
else
begin
if (writeif_accepted & readif_valid)
begin
// write & read at same time
buffer_valid_counter <= buffer_valid_counter;
end
else if (writeif_accepted)
begin
// write only
{err_buffer_valid_counter_overflow, buffer_valid_counter} <= buffer_valid_counter + 1;
end
else if (readif_valid)
begin
// read only
buffer_valid_counter <= buffer_valid_counter - 1;
end
else
begin
buffer_valid_counter <= buffer_valid_counter;
end
end
end
function integer two_pow_N;
input integer value;
begin
two_pow_N = 2 << (value-1);
end
endfunction
endmodule
|
module ADC_SAR_SEQ_P4_v2_40_0 (
soc,
aclk,
Vref,
sdone,
eoc,
vinPlus0);
input soc;
input aclk;
inout Vref;
electrical Vref;
output sdone;
output eoc;
inout vinPlus0;
electrical vinPlus0;
wire Net_3209;
electrical Net_3164;
wire Net_3128;
wire [11:0] Net_3111;
wire Net_3110;
wire [3:0] Net_3109;
wire Net_3108;
electrical Net_3166;
electrical Net_3167;
electrical Net_3168;
electrical Net_3169;
electrical Net_3170;
electrical Net_3171;
electrical Net_3172;
electrical Net_3173;
electrical Net_3174;
electrical Net_3175;
electrical Net_3176;
electrical Net_3177;
electrical Net_3178;
electrical Net_3179;
electrical Net_3180;
electrical muxout_plus;
electrical Net_3181;
electrical muxout_minus;
electrical Net_3227;
electrical Net_3113;
electrical Net_3225;
electrical [16:0] mux_bus_minus;
electrical [16:0] mux_bus_plus;
electrical Net_3226;
wire Net_3103;
wire Net_3104;
wire Net_3105;
wire Net_3106;
wire Net_3107;
electrical Net_3165;
electrical Net_3182;
electrical Net_3183;
electrical Net_3184;
electrical Net_3185;
electrical Net_3186;
electrical Net_3187;
electrical Net_3188;
electrical Net_3189;
electrical Net_3190;
electrical Net_3191;
electrical Net_3192;
electrical Net_3193;
electrical Net_3194;
electrical Net_3195;
electrical Net_3196;
electrical Net_3197;
electrical Net_3198;
electrical Net_3132;
electrical Net_3133;
electrical Net_3134;
electrical Net_3135;
electrical Net_3136;
electrical Net_3137;
electrical Net_3138;
electrical Net_3139;
electrical Net_3140;
electrical Net_3141;
electrical Net_3142;
electrical Net_3143;
electrical Net_3144;
electrical Net_3145;
electrical Net_3146;
electrical Net_3147;
electrical Net_3148;
electrical Net_3149;
electrical Net_3150;
electrical Net_3151;
electrical Net_3152;
electrical Net_3153;
electrical Net_3154;
electrical Net_3159;
electrical Net_3157;
electrical Net_3158;
electrical Net_3160;
electrical Net_3161;
electrical Net_3162;
electrical Net_3163;
electrical Net_3156;
electrical Net_3155;
wire Net_3120;
electrical Net_3119;
electrical Net_3118;
wire Net_3124;
electrical Net_3122;
electrical Net_3117;
electrical Net_3121;
electrical Net_3123;
wire Net_3112;
wire Net_3126;
wire Net_3125;
electrical Net_2793;
electrical Net_2794;
electrical Net_1851;
electrical Net_2580;
electrical [0:0] Net_2375;
electrical [0:0] Net_1450;
electrical Net_3046;
electrical Net_3016;
wire Net_3235;
electrical Net_2099;
wire Net_17;
wire Net_1845;
electrical Net_2020;
electrical Net_124;
electrical Net_2102;
wire [1:0] Net_3207;
electrical Net_8;
electrical Net_43;
ZeroTerminal ZeroTerminal_8 (
.z(Net_3125));
assign Net_3126 = Net_1845 | Net_3125;
cy_isr_v1_0
#(.int_type(2'b10))
IRQ
(.int_signal(Net_3112));
cy_analog_noconnect_v1_0 cy_analog_noconnect_44 (
.noconnect(Net_3123));
cy_analog_noconnect_v1_0 cy_analog_noconnect_40 (
.noconnect(Net_3121));
cy_analog_noconnect_v1_0 cy_analog_noconnect_39 (
.noconnect(Net_3117));
// cy_analog_virtualmux_43 (cy_analog_virtualmux_v1_0)
cy_connect_v1_0 cy_analog_virtualmux_43_connect(Net_124, muxout_minus);
defparam cy_analog_virtualmux_43_connect.sig_width = 1;
// cy_analog_virtualmux_42 (cy_analog_virtualmux_v1_0)
cy_connect_v1_0 cy_analog_virtualmux_42_connect(Net_2020, muxout_plus);
defparam cy_analog_virtualmux_42_connect.sig_width = 1;
cy_analog_noconnect_v1_0 cy_analog_noconnect_38 (
.noconnect(Net_3118));
cy_analog_noconnect_v1_0 cy_analog_noconnect_41 (
.noconnect(Net_3119));
cy_analog_noconnect_v1_0 cy_analog_noconnect_43 (
.noconnect(Net_3122));
// adc_plus_in_sel (cy_analog_virtualmux_v1_0)
cy_connect_v1_0 adc_plus_in_sel_connect(muxout_plus, mux_bus_plus[0]);
defparam adc_plus_in_sel_connect.sig_width = 1;
Bus_Connect_v2_40 Connect_1 (
.in_bus(mux_bus_plus[16:0]),
.out_bus(Net_1450[0:0]));
defparam Connect_1.in_width = 17;
defparam Connect_1.out_width = 1;
// adc_minus_in_sel (cy_analog_virtualmux_v1_0)
cy_connect_v1_0 adc_minus_in_sel_connect(muxout_minus, mux_bus_minus[0]);
defparam adc_minus_in_sel_connect.sig_width = 1;
cy_analog_noconnect_v1_0 cy_analog_noconnect_3 (
.noconnect(Net_1851));
// cy_analog_virtualmux_37 (cy_analog_virtualmux_v1_0)
cy_connect_v1_0 cy_analog_virtualmux_37_connect(Net_3016, mux_bus_plus[1]);
defparam cy_analog_virtualmux_37_connect.sig_width = 1;
cy_analog_noconnect_v1_0 cy_analog_noconnect_21 (
.noconnect(Net_3147));
cy_analog_noconnect_v1_0 cy_analog_noconnect_20 (
.noconnect(Net_3146));
cy_analog_noconnect_v1_0 cy_analog_noconnect_19 (
.noconnect(Net_3145));
cy_analog_noconnect_v1_0 cy_analog_noconnect_18 (
.noconnect(Net_3144));
cy_analog_noconnect_v1_0 cy_analog_noconnect_17 (
.noconnect(Net_3143));
cy_analog_noconnect_v1_0 cy_analog_noconnect_16 (
.noconnect(Net_3142));
cy_analog_noconnect_v1_0 cy_analog_noconnect_15 (
.noconnect(Net_3141));
cy_analog_noconnect_v1_0 cy_analog_noconnect_14 (
.noconnect(Net_3140));
cy_analog_noconnect_v1_0 cy_analog_noconnect_13 (
.noconnect(Net_3139));
cy_analog_noconnect_v1_0 cy_analog_noconnect_12 (
.noconnect(Net_3138));
cy_analog_noconnect_v1_0 cy_analog_noconnect_11 (
.noconnect(Net_3137));
cy_analog_noconnect_v1_0 cy_analog_noconnect_10 (
.noconnect(Net_3136));
cy_analog_noconnect_v1_0 cy_analog_noconnect_9 (
.noconnect(Net_3135));
cy_analog_noconnect_v1_0 cy_analog_noconnect_8 (
.noconnect(Net_3134));
cy_analog_noconnect_v1_0 cy_analog_noconnect_7 (
.noconnect(Net_3133));
cy_analog_noconnect_v1_0 cy_analog_noconnect_6 (
.noconnect(Net_3132));
// cy_analog_virtualmux_36 (cy_analog_virtualmux_v1_0)
cy_connect_v1_0 cy_analog_virtualmux_36_connect(Net_3046, mux_bus_minus[1]);
defparam cy_analog_virtualmux_36_connect.sig_width = 1;
cy_analog_noconnect_v1_0 cy_analog_noconnect_37 (
.noconnect(Net_3165));
ZeroTerminal ZeroTerminal_5 (
.z(Net_3107));
ZeroTerminal ZeroTerminal_4 (
.z(Net_3106));
ZeroTerminal ZeroTerminal_3 (
.z(Net_3105));
ZeroTerminal ZeroTerminal_2 (
.z(Net_3104));
ZeroTerminal ZeroTerminal_1 (
.z(Net_3103));
cy_analog_noconnect_v1_0 cy_analog_noconnect_1 (
.noconnect(Net_3113));
// ext_vref_sel (cy_analog_virtualmux_v1_0)
cy_connect_v1_0 ext_vref_sel_connect(Net_43, Net_3227);
defparam ext_vref_sel_connect.sig_width = 1;
Bus_Connect_v2_40 Connect_2 (
.in_bus(mux_bus_minus[16:0]),
.out_bus(Net_2375[0:0]));
defparam Connect_2.in_width = 17;
defparam Connect_2.out_width = 1;
cy_analog_noconnect_v1_0 cy_analog_noconnect_35 (
.noconnect(Net_3181));
cy_analog_noconnect_v1_0 cy_analog_noconnect_34 (
.noconnect(Net_3180));
cy_analog_noconnect_v1_0 cy_analog_noconnect_33 (
.noconnect(Net_3179));
cy_analog_noconnect_v1_0 cy_analog_noconnect_32 (
.noconnect(Net_3178));
cy_analog_noconnect_v1_0 cy_analog_noconnect_31 (
.noconnect(Net_3177));
cy_analog_noconnect_v1_0 cy_analog_noconnect_30 (
.noconnect(Net_3176));
cy_analog_noconnect_v1_0 cy_analog_noconnect_29 (
.noconnect(Net_3175));
cy_analog_noconnect_v1_0 cy_analog_noconnect_28 (
.noconnect(Net_3174));
cy_analog_noconnect_v1_0 cy_analog_noconnect_27 (
.noconnect(Net_3173));
cy_analog_noconnect_v1_0 cy_analog_noconnect_26 (
.noconnect(Net_3172));
cy_analog_noconnect_v1_0 cy_analog_noconnect_25 (
.noconnect(Net_3171));
cy_analog_noconnect_v1_0 cy_analog_noconnect_24 (
.noconnect(Net_3170));
cy_analog_noconnect_v1_0 cy_analog_noconnect_23 (
.noconnect(Net_3169));
cy_analog_noconnect_v1_0 cy_analog_noconnect_22 (
.noconnect(Net_3168));
cy_analog_noconnect_v1_0 cy_analog_noconnect_4 (
.noconnect(Net_3167));
cy_analog_noconnect_v1_0 cy_analog_noconnect_2 (
.noconnect(Net_3166));
// int_vref_sel (cy_analog_virtualmux_v1_0)
cy_connect_v1_0 int_vref_sel_connect(Net_8, Net_3113);
defparam int_vref_sel_connect.sig_width = 1;
// clk_src_sel (cy_virtualmux_v1_0)
assign Net_17 = Net_1845;
cy_psoc4_sar_v1_0 cy_psoc4_sar (
.vplus(Net_2020),
.vminus(Net_124),
.vref(Net_8),
.ext_vref(Net_43),
.clock(Net_17),
.sw_negvref(Net_3103),
.cfg_st_sel(Net_3207[1:0]),
.cfg_average(Net_3104),
.cfg_resolution(Net_3105),
.cfg_differential(Net_3106),
.trigger(Net_3235),
.data_hilo_sel(Net_3107),
.sample_done(sdone),
.chan_id_valid(Net_3108),
.chan_id(Net_3109[3:0]),
.data_valid(Net_3110),
.eos_intr(eoc),
.data(Net_3111[11:0]),
.irq(Net_3112));
// ext_vneg_sel (cy_analog_virtualmux_v1_0)
cy_connect_v1_0 ext_vneg_sel_connect(Net_2580, Net_1851);
defparam ext_vneg_sel_connect.sig_width = 1;
// VMux_soc (cy_virtualmux_v1_0)
assign Net_3235 = soc;
ZeroTerminal ZeroTerminal_6 (
.z(Net_3207[0]));
ZeroTerminal ZeroTerminal_7 (
.z(Net_3207[1]));
// cy_analog_virtualmux_vplus0 (cy_analog_virtualmux_v1_0)
cy_connect_v1_0 cy_analog_virtualmux_vplus0_connect(mux_bus_plus[0], vinPlus0);
defparam cy_analog_virtualmux_vplus0_connect.sig_width = 1;
// cy_analog_virtualmux_vplus1 (cy_analog_virtualmux_v1_0)
cy_connect_v1_0 cy_analog_virtualmux_vplus1_connect(mux_bus_plus[1], Net_3132);
defparam cy_analog_virtualmux_vplus1_connect.sig_width = 1;
// cy_analog_virtualmux_vplus2 (cy_analog_virtualmux_v1_0)
cy_connect_v1_0 cy_analog_virtualmux_vplus2_connect(mux_bus_plus[2], Net_3133);
defparam cy_analog_virtualmux_vplus2_connect.sig_width = 1;
// cy_analog_virtualmux_vplus3 (cy_analog_virtualmux_v1_0)
cy_connect_v1_0 cy_analog_virtualmux_vplus3_connect(mux_bus_plus[3], Net_3134);
defparam cy_analog_virtualmux_vplus3_connect.sig_width = 1;
// cy_analog_virtualmux_vplus4 (cy_analog_virtualmux_v1_0)
cy_connect_v1_0 cy_analog_virtualmux_vplus4_connect(mux_bus_plus[4], Net_3135);
defparam cy_analog_virtualmux_vplus4_connect.sig_width = 1;
// cy_analog_virtualmux_vplus5 (cy_analog_virtualmux_v1_0)
cy_connect_v1_0 cy_analog_virtualmux_vplus5_connect(mux_bus_plus[5], Net_3136);
defparam cy_analog_virtualmux_vplus5_connect.sig_width = 1;
// cy_analog_virtualmux_vplus6 (cy_analog_virtualmux_v1_0)
cy_connect_v1_0 cy_analog_virtualmux_vplus6_connect(mux_bus_plus[6], Net_3137);
defparam cy_analog_virtualmux_vplus6_connect.sig_width = 1;
// cy_analog_virtualmux_vplus7 (cy_analog_virtualmux_v1_0)
cy_connect_v1_0 cy_analog_virtualmux_vplus7_connect(mux_bus_plus[7], Net_3138);
defparam cy_analog_virtualmux_vplus7_connect.sig_width = 1;
// cy_analog_virtualmux_vplus8 (cy_analog_virtualmux_v1_0)
cy_connect_v1_0 cy_analog_virtualmux_vplus8_connect(mux_bus_plus[8], Net_3139);
defparam cy_analog_virtualmux_vplus8_connect.sig_width = 1;
// cy_analog_virtualmux_vplus9 (cy_analog_virtualmux_v1_0)
cy_connect_v1_0 cy_analog_virtualmux_vplus9_connect(mux_bus_plus[9], Net_3140);
defparam cy_analog_virtualmux_vplus9_connect.sig_width = 1;
// cy_analog_virtualmux_vplus10 (cy_analog_virtualmux_v1_0)
cy_connect_v1_0 cy_analog_virtualmux_vplus10_connect(mux_bus_plus[10], Net_3141);
defparam cy_analog_virtualmux_vplus10_connect.sig_width = 1;
// cy_analog_virtualmux_vplus11 (cy_analog_virtualmux_v1_0)
cy_connect_v1_0 cy_analog_virtualmux_vplus11_connect(mux_bus_plus[11], Net_3142);
defparam cy_analog_virtualmux_vplus11_connect.sig_width = 1;
// cy_analog_virtualmux_vplus12 (cy_analog_virtualmux_v1_0)
cy_connect_v1_0 cy_analog_virtualmux_vplus12_connect(mux_bus_plus[12], Net_3143);
defparam cy_analog_virtualmux_vplus12_connect.sig_width = 1;
// cy_analog_virtualmux_vplus13 (cy_analog_virtualmux_v1_0)
cy_connect_v1_0 cy_analog_virtualmux_vplus13_connect(mux_bus_plus[13], Net_3144);
defparam cy_analog_virtualmux_vplus13_connect.sig_width = 1;
// cy_analog_virtualmux_vplus14 (cy_analog_virtualmux_v1_0)
cy_connect_v1_0 cy_analog_virtualmux_vplus14_connect(mux_bus_plus[14], Net_3145);
defparam cy_analog_virtualmux_vplus14_connect.sig_width = 1;
// cy_analog_virtualmux_vplus15 (cy_analog_virtualmux_v1_0)
cy_connect_v1_0 cy_analog_virtualmux_vplus15_connect(mux_bus_plus[15], Net_3146);
defparam cy_analog_virtualmux_vplus15_connect.sig_width = 1;
// cy_analog_virtualmux_vplus_inj (cy_analog_virtualmux_v1_0)
cy_connect_v1_0 cy_analog_virtualmux_vplus_inj_connect(Net_3016, Net_3147);
defparam cy_analog_virtualmux_vplus_inj_connect.sig_width = 1;
// cy_analog_virtualmux_vminus0 (cy_analog_virtualmux_v1_0)
cy_connect_v1_0 cy_analog_virtualmux_vminus0_connect(mux_bus_minus[0], Net_3166);
defparam cy_analog_virtualmux_vminus0_connect.sig_width = 1;
// cy_analog_virtualmux_vminus1 (cy_analog_virtualmux_v1_0)
cy_connect_v1_0 cy_analog_virtualmux_vminus1_connect(mux_bus_minus[1], Net_3167);
defparam cy_analog_virtualmux_vminus1_connect.sig_width = 1;
// cy_analog_virtualmux_vminus2 (cy_analog_virtualmux_v1_0)
cy_connect_v1_0 cy_analog_virtualmux_vminus2_connect(mux_bus_minus[2], Net_3168);
defparam cy_analog_virtualmux_vminus2_connect.sig_width = 1;
// cy_analog_virtualmux_vminus3 (cy_analog_virtualmux_v1_0)
cy_connect_v1_0 cy_analog_virtualmux_vminus3_connect(mux_bus_minus[3], Net_3169);
defparam cy_analog_virtualmux_vminus3_connect.sig_width = 1;
// cy_analog_virtualmux_vminus4 (cy_analog_virtualmux_v1_0)
cy_connect_v1_0 cy_analog_virtualmux_vminus4_connect(mux_bus_minus[4], Net_3170);
defparam cy_analog_virtualmux_vminus4_connect.sig_width = 1;
// cy_analog_virtualmux_vminus5 (cy_analog_virtualmux_v1_0)
cy_connect_v1_0 cy_analog_virtualmux_vminus5_connect(mux_bus_minus[5], Net_3171);
defparam cy_analog_virtualmux_vminus5_connect.sig_width = 1;
// cy_analog_virtualmux_vminus6 (cy_analog_virtualmux_v1_0)
cy_connect_v1_0 cy_analog_virtualmux_vminus6_connect(mux_bus_minus[6], Net_3172);
defparam cy_analog_virtualmux_vminus6_connect.sig_width = 1;
// cy_analog_virtualmux_vminus7 (cy_analog_virtualmux_v1_0)
cy_connect_v1_0 cy_analog_virtualmux_vminus7_connect(mux_bus_minus[7], Net_3173);
defparam cy_analog_virtualmux_vminus7_connect.sig_width = 1;
// cy_analog_virtualmux_vminus8 (cy_analog_virtualmux_v1_0)
cy_connect_v1_0 cy_analog_virtualmux_vminus8_connect(mux_bus_minus[8], Net_3174);
defparam cy_analog_virtualmux_vminus8_connect.sig_width = 1;
// cy_analog_virtualmux_vminus9 (cy_analog_virtualmux_v1_0)
cy_connect_v1_0 cy_analog_virtualmux_vminus9_connect(mux_bus_minus[9], Net_3175);
defparam cy_analog_virtualmux_vminus9_connect.sig_width = 1;
// cy_analog_virtualmux_vminus10 (cy_analog_virtualmux_v1_0)
cy_connect_v1_0 cy_analog_virtualmux_vminus10_connect(mux_bus_minus[10], Net_3176);
defparam cy_analog_virtualmux_vminus10_connect.sig_width = 1;
// cy_analog_virtualmux_vminus11 (cy_analog_virtualmux_v1_0)
cy_connect_v1_0 cy_analog_virtualmux_vminus11_connect(mux_bus_minus[11], Net_3177);
defparam cy_analog_virtualmux_vminus11_connect.sig_width = 1;
// cy_analog_virtualmux_vminus12 (cy_analog_virtualmux_v1_0)
cy_connect_v1_0 cy_analog_virtualmux_vminus12_connect(mux_bus_minus[12], Net_3178);
defparam cy_analog_virtualmux_vminus12_connect.sig_width = 1;
// cy_analog_virtualmux_vminus13 (cy_analog_virtualmux_v1_0)
cy_connect_v1_0 cy_analog_virtualmux_vminus13_connect(mux_bus_minus[13], Net_3179);
defparam cy_analog_virtualmux_vminus13_connect.sig_width = 1;
// cy_analog_virtualmux_vminus14 (cy_analog_virtualmux_v1_0)
cy_connect_v1_0 cy_analog_virtualmux_vminus14_connect(mux_bus_minus[14], Net_3180);
defparam cy_analog_virtualmux_vminus14_connect.sig_width = 1;
// cy_analog_virtualmux_vminus15 (cy_analog_virtualmux_v1_0)
cy_connect_v1_0 cy_analog_virtualmux_vminus15_connect(mux_bus_minus[15], Net_3181);
defparam cy_analog_virtualmux_vminus15_connect.sig_width = 1;
// cy_analog_virtualmux_vminus_inj (cy_analog_virtualmux_v1_0)
cy_connect_v1_0 cy_analog_virtualmux_vminus_inj_connect(Net_3046, Net_3165);
defparam cy_analog_virtualmux_vminus_inj_connect.sig_width = 1;
cy_clock_v1_0
#(.id("2c8f831a-eb04-4562-a197-2a3531daa1f2/5c71752a-e182-47ca-942c-9cb20adbdf2f"),
.source_clock_id(""),
.divisor(0),
.period("333334666.672"),
.is_direct(0),
.is_digital(0))
intClock
(.clock_out(Net_1845));
cy_analog_noconnect_v1_0 cy_analog_noconnect_5 (
.noconnect(Net_3227));
endmodule
|
module BLE_v3_10_1 (
clk,
pa_en);
output clk;
output pa_en;
wire Net_55;
wire Net_60;
wire Net_53;
wire Net_72;
wire Net_71;
wire Net_70;
wire Net_15;
wire Net_14;
cy_m0s8_ble_v1_0 cy_m0s8_ble (
.interrupt(Net_15),
.rf_ext_pa_en(pa_en));
cy_isr_v1_0
#(.int_type(2'b10))
bless_isr
(.int_signal(Net_15));
cy_clock_v1_0
#(.id("e1fabf2a-6555-450d-b095-7b11ed8011cc/5ae6fa4d-f41a-4a35-8821-7ce70389cb0c"),
.source_clock_id("9A908CA6-5BB3-4db0-B098-959E5D90882B"),
.divisor(0),
.period("0"),
.is_direct(1),
.is_digital(0))
LFCLK
(.clock_out(Net_53));
assign clk = Net_53 | Net_55;
assign Net_55 = 1'h0;
endmodule
|
module top ;
wire Net_183;
wire Net_182;
wire Net_175;
wire Net_174;
wire Net_173;
wire Net_172;
electrical Net_171;
electrical Net_45;
ADC_SAR_SEQ_P4_v2_40_0 ADC_SAR (
.Vref(Net_171),
.sdone(Net_172),
.eoc(Net_173),
.aclk(1'b0),
.soc(1'b0),
.vinPlus0(Net_45));
wire [0:0] tmpOE__THERMISTOR_net;
wire [0:0] tmpFB_0__THERMISTOR_net;
wire [0:0] tmpIO_0__THERMISTOR_net;
wire [0:0] tmpINTERRUPT_0__THERMISTOR_net;
electrical [0:0] tmpSIOVREF__THERMISTOR_net;
cy_psoc3_pins_v1_10
#(.id("77715107-f8d5-47e5-a629-0fb83101ac6b"),
.drive_mode(3'b000),
.ibuf_enabled(1'b0),
.init_dr_st(1'b1),
.input_clk_en(0),
.input_sync(1'b1),
.input_sync_mode(1'b0),
.intr_mode(2'b00),
.invert_in_clock(0),
.invert_in_clock_en(0),
.invert_in_reset(0),
.invert_out_clock(0),
.invert_out_clock_en(0),
.invert_out_reset(0),
.io_voltage(""),
.layout_mode("CONTIGUOUS"),
.oe_conn(1'b0),
.oe_reset(0),
.oe_sync(1'b0),
.output_clk_en(0),
.output_clock_mode(1'b0),
.output_conn(1'b0),
.output_mode(1'b0),
.output_reset(0),
.output_sync(1'b0),
.pa_in_clock(-1),
.pa_in_clock_en(-1),
.pa_in_reset(-1),
.pa_out_clock(-1),
.pa_out_clock_en(-1),
.pa_out_reset(-1),
.pin_aliases(""),
.pin_mode("A"),
.por_state(4),
.sio_group_cnt(0),
.sio_hyst(1'b1),
.sio_ibuf(""),
.sio_info(2'b00),
.sio_obuf(""),
.sio_refsel(""),
.sio_vtrip(""),
.sio_hifreq(""),
.sio_vohsel(""),
.slew_rate(1'b0),
.spanning(0),
.use_annotation(1'b0),
.vtrip(2'b10),
.width(1),
.ovt_hyst_trim(1'b0),
.ovt_needed(1'b0),
.ovt_slew_control(2'b00),
.input_buffer_sel(2'b00))
THERMISTOR
(.oe(tmpOE__THERMISTOR_net),
.y({1'b0}),
.fb({tmpFB_0__THERMISTOR_net[0:0]}),
.analog({Net_45}),
.io({tmpIO_0__THERMISTOR_net[0:0]}),
.siovref(tmpSIOVREF__THERMISTOR_net),
.interrupt({tmpINTERRUPT_0__THERMISTOR_net[0:0]}),
.in_clock({1'b0}),
.in_clock_en({1'b1}),
.in_reset({1'b0}),
.out_clock({1'b0}),
.out_clock_en({1'b1}),
.out_reset({1'b0}));
assign tmpOE__THERMISTOR_net = (`CYDEV_CHIP_MEMBER_USED == `CYDEV_CHIP_MEMBER_3A && `CYDEV_CHIP_REVISION_USED < `CYDEV_CHIP_REVISION_3A_ES3) ? ~{1'b1} : {1'b1};
BLE_v3_10_1 BLE (
.clk(Net_182),
.pa_en(Net_183));
wire [0:0] tmpOE__GREEN_LED_net;
wire [0:0] tmpFB_0__GREEN_LED_net;
wire [0:0] tmpIO_0__GREEN_LED_net;
wire [0:0] tmpINTERRUPT_0__GREEN_LED_net;
electrical [0:0] tmpSIOVREF__GREEN_LED_net;
cy_psoc3_pins_v1_10
#(.id("e851a3b9-efb8-48be-bbb8-b303b216c393"),
.drive_mode(3'b110),
.ibuf_enabled(1'b1),
.init_dr_st(1'b0),
.input_clk_en(0),
.input_sync(1'b1),
.input_sync_mode(1'b0),
.intr_mode(2'b00),
.invert_in_clock(0),
.invert_in_clock_en(0),
.invert_in_reset(0),
.invert_out_clock(0),
.invert_out_clock_en(0),
.invert_out_reset(0),
.io_voltage(""),
.layout_mode("CONTIGUOUS"),
.oe_conn(1'b0),
.oe_reset(0),
.oe_sync(1'b0),
.output_clk_en(0),
.output_clock_mode(1'b0),
.output_conn(1'b0),
.output_mode(1'b0),
.output_reset(0),
.output_sync(1'b0),
.pa_in_clock(-1),
.pa_in_clock_en(-1),
.pa_in_reset(-1),
.pa_out_clock(-1),
.pa_out_clock_en(-1),
.pa_out_reset(-1),
.pin_aliases(""),
.pin_mode("O"),
.por_state(4),
.sio_group_cnt(0),
.sio_hyst(1'b1),
.sio_ibuf(""),
.sio_info(2'b00),
.sio_obuf(""),
.sio_refsel(""),
.sio_vtrip(""),
.sio_hifreq(""),
.sio_vohsel(""),
.slew_rate(1'b0),
.spanning(0),
.use_annotation(1'b0),
.vtrip(2'b10),
.width(1),
.ovt_hyst_trim(1'b0),
.ovt_needed(1'b0),
.ovt_slew_control(2'b00),
.input_buffer_sel(2'b00))
GREEN_LED
(.oe(tmpOE__GREEN_LED_net),
.y({1'b0}),
.fb({tmpFB_0__GREEN_LED_net[0:0]}),
.io({tmpIO_0__GREEN_LED_net[0:0]}),
.siovref(tmpSIOVREF__GREEN_LED_net),
.interrupt({tmpINTERRUPT_0__GREEN_LED_net[0:0]}),
.in_clock({1'b0}),
.in_clock_en({1'b1}),
.in_reset({1'b0}),
.out_clock({1'b0}),
.out_clock_en({1'b1}),
.out_reset({1'b0}));
assign tmpOE__GREEN_LED_net = (`CYDEV_CHIP_MEMBER_USED == `CYDEV_CHIP_MEMBER_3A && `CYDEV_CHIP_REVISION_USED < `CYDEV_CHIP_REVISION_3A_ES3) ? ~{1'b1} : {1'b1};
endmodule
|
module axi_traffic_gen_v2_0_7_asynch_rst_ff (
data ,
clk ,
reset ,
q
);
input data, clk, reset ;
output q;
(*ASYNC_REG = "TRUE" *) reg q;
always @ ( posedge clk or posedge reset) begin
if (reset) begin
q <= 1'b1;
end else begin
q <= data;
end
end
endmodule
|
module bcd_to_display(
input clk,
input rst,
input [3:0] BCD,
output reg[7:0] DISPLAY
);
initial begin
DISPLAY = 8'b11111111;
#10 DISPLAY = 8'b00000000;
end
always @ (posedge clk)
begin
if (rst)
begin
DISPLAY = 8'b11111111;
#10 DISPLAY = 8'b00000000;
end
else
begin
case (BCD)
4'b0000: DISPLAY = 8'b11111110;// ---- espera
4'b0001: DISPLAY = 8'b11001111;// Piso 1
4'b0010: DISPLAY = 8'b10010010;// Piso 2
4'b0011: DISPLAY = 8'b10000110;// Piso 3
4'b0100: DISPLAY = 8'b11001100;// Piso 4
4'b0101: DISPLAY = 8'b10100100;// Sube
4'b0110: DISPLAY = 8'b10001000;// Abierto
4'b0111: DISPLAY = 8'b10110001;// Cerrado
4'b1000: DISPLAY = 8'b10000000;// Baja
4'b1001: DISPLAY = 8'b10011000;// indica el Piso
default: DISPLAY = 8'b0;
endcase
end
end
endmodule
|
module clk_166M_83M_tb ();
// Clock to Q delay of 100ps
localparam TCQ = 100;
// timescale is 1ps/1ps
localparam ONE_NS = 1000;
localparam PHASE_ERR_MARGIN = 100; // 100ps
// how many cycles to run
localparam COUNT_PHASE = 1024;
// we'll be using the period in many locations
localparam time PER1 = 40.000*ONE_NS;
localparam time PER1_1 = PER1/2;
localparam time PER1_2 = PER1 - PER1/2;
// Declare the input clock signals
reg CLK_IN1 = 1;
// The high bits of the sampling counters
wire [3:1] COUNT;
// Status and control signals
reg RESET = 0;
wire LOCKED;
reg COUNTER_RESET = 0;
reg [13:0] timeout_counter = 14'b00000000000000;
// Input clock generation
//------------------------------------
always begin
CLK_IN1 = #PER1_1 ~CLK_IN1;
CLK_IN1 = #PER1_2 ~CLK_IN1;
end
// Test sequence
reg [15*8-1:0] test_phase = "";
initial begin
// Set up any display statements using time to be readable
$timeformat(-12, 2, "ps", 10);
$display ("Timing checks are not valid");
COUNTER_RESET = 0;
test_phase = "reset";
RESET = 1;
#(PER1*6);
RESET = 0;
test_phase = "wait lock";
`wait_lock;
#(PER1*6);
COUNTER_RESET = 1;
#(PER1*19)
COUNTER_RESET = 0;
#(PER1*1)
$display ("Timing checks are valid");
test_phase = "counting";
#(PER1*COUNT_PHASE);
$display("SIMULATION PASSED");
$display("SYSTEM_CLOCK_COUNTER : %0d\n",$time/PER1);
$finish;
end
always@(posedge CLK_IN1) begin
timeout_counter <= timeout_counter + 1'b1;
if (timeout_counter == 14'b10000000000000) begin
if (LOCKED != 1'b1) begin
$display("ERROR : NO LOCK signal");
$display("SYSTEM_CLOCK_COUNTER : %0d\n",$time/PER1);
$finish;
end
end
end
// Instantiation of the example design containing the clock
// network and sampling counters
//---------------------------------------------------------
clk_166M_83M_exdes
dut
(// Clock in ports
.CLK_IN1 (CLK_IN1),
// Reset for logic in example design
.COUNTER_RESET (COUNTER_RESET),
// High bits of the counters
.COUNT (COUNT),
// Status and control signals
.RESET (RESET),
.LOCKED (LOCKED));
endmodule
|
module header
// Internal signals
//
// Generated Signal List
//
//
// End of Generated Signal List
//
// %COMPILER_OPTS%
// Generated Signal Assignments
//
// Generated Instances
// wiring ...
// Generated Instances and Port Mappings
endmodule
|
module BCD_Binary_Encoder
#(
parameter BIN_WIDTH = 8,
parameter BDC_DIGITS = 2
)
(
// Input Signals
input CONVERT,
output reg DONE,
input [BIN_WIDTH-1:0] BIN_IN,
// BCD Data Output Signals
output reg [BDC_DIGITS*4-1:0] BCD_OUT, // Packed Array
output reg BCD_OVERFLOW,
// System Signals
input CLK,
input RESET
);
// Include Standard Functions header file (needed for bit_index())
`include "StdFunctions.vh"
//
// BCD Register Width is 4-bits per BCD Digit
//
reg [4:0] State;
localparam [4:0]
S0 = 5'b00001,
S1 = 5'b00010,
S2 = 5'b00100,
S3 = 5'b01000,
S4 = 5'b10000;
localparam BCD_WIDTH = 4 * BDC_DIGITS;
reg [BIN_WIDTH-1:0] bin_shift_reg;
reg [BCD_WIDTH-1:0] bcd_shift_reg;
reg [BCD_WIDTH-1:0] bcd_adder_sum;
//
// Shift Counter tracks number of BIN_IN bits shifted (using a Rollover Counter)
//
localparam SHIFT_COUNTER_WIDTH = bit_index( BIN_WIDTH );
localparam [SHIFT_COUNTER_WIDTH:0] SHIFT_COUNTER_LOADVAL = { 1'b1, {SHIFT_COUNTER_WIDTH{1'b0}} } - BIN_WIDTH[SHIFT_COUNTER_WIDTH:0] + 1'b1;
reg [SHIFT_COUNTER_WIDTH:0] shift_counter_reg;
// Shift Count Done when the counter rollsover
wire shift_counter_done = shift_counter_reg[SHIFT_COUNTER_WIDTH];
//
// BCD Column Adders
// After each shift, add 3 to any column equaling 5 or greater.
// One adder will be generated per BCD Digit.
// The selective adding is done by LUT instead of an actual adder.
//
genvar i;
generate
begin
for (i = 0; i < BDC_DIGITS; i=i+1)
begin : bcd_adders
always @*
begin
case (bcd_shift_reg[i*4 +: 4])
// No Add
4'b0000 : bcd_adder_sum[i*4 +: 4] <= 4'b0000; // 0 => 0
4'b0001 : bcd_adder_sum[i*4 +: 4] <= 4'b0001; // 1 => 1
4'b0010 : bcd_adder_sum[i*4 +: 4] <= 4'b0010; // 2 => 2
4'b0011 : bcd_adder_sum[i*4 +: 4] <= 4'b0011; // 3 => 3
4'b0100 : bcd_adder_sum[i*4 +: 4] <= 4'b0100; // 4 => 4
// Add 3
4'b0101 : bcd_adder_sum[i*4 +: 4] <= 4'b1000; // 5 => 8
4'b0110 : bcd_adder_sum[i*4 +: 4] <= 4'b1001; // 6 => 9
4'b0111 : bcd_adder_sum[i*4 +: 4] <= 4'b1010; // 7 => 10
4'b1000 : bcd_adder_sum[i*4 +: 4] <= 4'b1011; // 8 => 11
4'b1001 : bcd_adder_sum[i*4 +: 4] <= 4'b1100; // 9 => 12
// Invalid Inputs
4'b1010 : bcd_adder_sum[i*4 +: 4] <= 4'b0000; // 10
4'b1011 : bcd_adder_sum[i*4 +: 4] <= 4'b0000; // 11
4'b1100 : bcd_adder_sum[i*4 +: 4] <= 4'b0000; // 12
4'b1101 : bcd_adder_sum[i*4 +: 4] <= 4'b0000; // 13
4'b1110 : bcd_adder_sum[i*4 +: 4] <= 4'b0000; // 14
4'b1111 : bcd_adder_sum[i*4 +: 4] <= 4'b0000; // 15
endcase
end
end
end
endgenerate
//
// BCD Binary Encoder State Machine
//
reg overflow_flag;
// !! Lab 4: Implement the BCD Binary Encoder State Machine here !!
always @(posedge CLK, posedge RESET)
begin
if (RESET)
begin
State <= S0;
DONE <= 1'b0;
BCD_OUT <= {BDC_DIGITS*4{1'b0}};
BCD_OVERFLOW <= 1'b0;
shift_counter_reg <= {SHIFT_COUNTER_WIDTH+1{1'b0}};
bin_shift_reg <= {BIN_WIDTH{1'b0}};
bcd_shift_reg <= {BCD_WIDTH{1'b0}};
overflow_flag <= 1'b0;
end
else
begin
case (State)
S0 :
begin
DONE <= 1'b0;
if(CONVERT)
State <= S1;
end
S1 :
begin
bin_shift_reg <= BIN_IN;
bcd_shift_reg <= {BCD_WIDTH{1'b0}};
shift_counter_reg <= SHIFT_COUNTER_LOADVAL;
overflow_flag <= 1'b0;
State <= S2;
end
S2 :
begin
overflow_flag <= overflow_flag | bcd_shift_reg[BCD_WIDTH-1];
bcd_shift_reg <= { bcd_shift_reg[BCD_WIDTH-2:0], bin_shift_reg[BIN_WIDTH-1] };
bin_shift_reg <= { bin_shift_reg[BIN_WIDTH-2:0], 1'b0 };
if(shift_counter_done)
State <= S4;
else
State <= S3;
end
S3 :
begin
bcd_shift_reg <= bcd_adder_sum;
shift_counter_reg <= shift_counter_reg + 1'b1;
State <= S2;
end
S4:
begin
BCD_OUT <= bcd_shift_reg;
BCD_OVERFLOW <= overflow_flag;
DONE <= 1'b1;
State <= S0;
end
endcase
end
end
endmodule
|
module
mulAddRecFNToRaw_preMul#(
parameter expWidth = 3, parameter sigWidth = 3
) (
control,
op,
a,
b,
c,
roundingMode,
mulAddA,
mulAddB,
mulAddC,
intermed_compactState,
intermed_sExp,
intermed_CDom_CAlignDist,
intermed_highAlignedSigC
);
`include "HardFloat_localFuncs.vi"
input [(`floatControlWidth - 1):0] control;
input [1:0] op;
input [(expWidth + sigWidth):0] a;
input [(expWidth + sigWidth):0] b;
input [(expWidth + sigWidth):0] c;
input [2:0] roundingMode;
output [(sigWidth - 1):0] mulAddA;
output [(sigWidth - 1):0] mulAddB;
output [(sigWidth*2 - 1):0] mulAddC;
output [5:0] intermed_compactState;
output signed [(expWidth + 1):0] intermed_sExp;
output [(clog2(sigWidth + 1) - 1):0] intermed_CDom_CAlignDist;
output [(sigWidth + 1):0] intermed_highAlignedSigC;
/*------------------------------------------------------------------------
*------------------------------------------------------------------------*/
localparam prodWidth = sigWidth*2;
localparam sigSumWidth = sigWidth + prodWidth + 3;
/*------------------------------------------------------------------------
*------------------------------------------------------------------------*/
wire isNaNA, isInfA, isZeroA, signA;
wire signed [(expWidth + 1):0] sExpA;
wire [sigWidth:0] sigA;
recFNToRawFN#(expWidth, sigWidth)
recFNToRawFN_a(a, isNaNA, isInfA, isZeroA, signA, sExpA, sigA);
wire isSigNaNA;
isSigNaNRecFN#(expWidth, sigWidth) isSigNaN_a(a, isSigNaNA);
wire isNaNB, isInfB, isZeroB, signB;
wire signed [(expWidth + 1):0] sExpB;
wire [sigWidth:0] sigB;
recFNToRawFN#(expWidth, sigWidth)
recFNToRawFN_b(b, isNaNB, isInfB, isZeroB, signB, sExpB, sigB);
wire isSigNaNB;
isSigNaNRecFN#(expWidth, sigWidth) isSigNaN_b(b, isSigNaNB);
wire isNaNC, isInfC, isZeroC, signC;
wire signed [(expWidth + 1):0] sExpC;
wire [sigWidth:0] sigC;
recFNToRawFN#(expWidth, sigWidth)
recFNToRawFN_c(c, isNaNC, isInfC, isZeroC, signC, sExpC, sigC);
wire isSigNaNC;
isSigNaNRecFN#(expWidth, sigWidth) isSigNaN_c(c, isSigNaNC);
/*------------------------------------------------------------------------
*------------------------------------------------------------------------*/
wire signProd = signA ^ signB ^ op[1];
wire signed [(expWidth + 2):0] sExpAlignedProd =
sExpA + sExpB + (-(1<<expWidth) + sigWidth + 3);
wire doSubMags = signProd ^ signC ^ op[0];
wire opSignC = signProd ^ doSubMags;
wire roundingMode_min = (roundingMode == `round_min);
/*------------------------------------------------------------------------
*------------------------------------------------------------------------*/
wire signed [(expWidth + 2):0] sNatCAlignDist = sExpAlignedProd - sExpC;
wire [(expWidth + 1):0] posNatCAlignDist =
sNatCAlignDist[(expWidth + 1):0];
wire isMinCAlign = isZeroA || isZeroB || (sNatCAlignDist < 0);
wire CIsDominant =
!isZeroC && (isMinCAlign || (posNatCAlignDist <= sigWidth));
wire signed [(expWidth + 1):0] sExpSum =
CIsDominant ? sExpC : sExpAlignedProd - sigWidth;
wire [(clog2(sigSumWidth) - 1):0] CAlignDist =
isMinCAlign ? 0
: (posNatCAlignDist < sigSumWidth - 1)
? posNatCAlignDist[(clog2(sigSumWidth) - 1):0]
: sigSumWidth - 1;
wire signed [(sigSumWidth + 2):0] extComplSigC =
{doSubMags ? ~sigC : sigC, {(sigSumWidth - sigWidth + 2){doSubMags}}};
wire [(sigSumWidth + 1):0] mainAlignedSigC = extComplSigC>>>CAlignDist;
localparam CGrainAlign = (sigSumWidth - sigWidth - 1) & 3;
wire [(sigWidth + CGrainAlign):0] grainAlignedSigC = sigC<<CGrainAlign;
wire [(sigWidth + CGrainAlign)/4:0] reduced4SigC;
compressBy4#(sigWidth + 1 + CGrainAlign)
compressBy4_sigC(grainAlignedSigC, reduced4SigC);
localparam CExtraMaskHiBound = (sigSumWidth - 1)/4;
localparam CExtraMaskLoBound = (sigSumWidth - sigWidth - 1)/4;
wire [(CExtraMaskHiBound - CExtraMaskLoBound - 1):0] CExtraMask;
lowMaskHiLo#(clog2(sigSumWidth) - 2, CExtraMaskHiBound, CExtraMaskLoBound)
lowMask_CExtraMask(CAlignDist[(clog2(sigSumWidth) - 1):2], CExtraMask);
wire reduced4CExtra = |(reduced4SigC & CExtraMask);
wire [(sigSumWidth - 1):0] alignedSigC =
{mainAlignedSigC>>3,
doSubMags ? (&mainAlignedSigC[2:0]) && !reduced4CExtra
: (|mainAlignedSigC[2:0]) || reduced4CExtra};
/*------------------------------------------------------------------------
*------------------------------------------------------------------------*/
wire isNaNAOrB = isNaNA || isNaNB;
wire isNaNAny = isNaNAOrB || isNaNC;
wire isInfAOrB = isInfA || isInfB;
wire invalidProd = (isInfA && isZeroB) || (isZeroA && isInfB);
wire notSigNaN_invalidExc =
invalidProd || (!isNaNAOrB && isInfAOrB && isInfC && doSubMags);
wire invalidExc =
isSigNaNA || isSigNaNB || isSigNaNC || notSigNaN_invalidExc;
wire notNaN_addZeros = (isZeroA || isZeroB) && isZeroC;
wire specialCase = isNaNAny || isInfAOrB || isInfC || notNaN_addZeros;
wire specialNotNaN_signOut =
(isInfAOrB && signProd) || (isInfC && opSignC)
|| (notNaN_addZeros && !roundingMode_min && signProd && opSignC)
|| (notNaN_addZeros && roundingMode_min && (signProd || opSignC));
`ifdef HardFloat_propagateNaNPayloads
wire signNaN;
wire [(sigWidth - 2):0] fractNaN;
propagateFloatNaN_mulAdd#(sigWidth)
propagateNaN(
control,
op,
isNaNA,
signA,
sigA[(sigWidth - 2):0],
isNaNB,
signB,
sigB[(sigWidth - 2):0],
invalidProd,
isNaNC,
signC,
sigC[(sigWidth - 2):0],
signNaN,
fractNaN
);
wire isNaNOut = isNaNAny || notSigNaN_invalidExc;
wire special_signOut =
isNaNAny || notSigNaN_invalidExc ? signNaN : specialNotNaN_signOut;
`else
wire special_signOut = specialNotNaN_signOut;
`endif
/*------------------------------------------------------------------------
*------------------------------------------------------------------------*/
assign mulAddA = sigA;
assign mulAddB = sigB;
assign mulAddC = alignedSigC[prodWidth:1];
assign intermed_compactState =
{specialCase,
invalidExc || (!specialCase && signProd ),
`ifdef HardFloat_propagateNaNPayloads
isNaNOut || (!specialCase && doSubMags ),
`else
isNaNAny || (!specialCase && doSubMags ),
`endif
isInfAOrB || isInfC || (!specialCase && CIsDominant ),
notNaN_addZeros || (!specialCase && alignedSigC[0]),
special_signOut};
assign intermed_sExp = sExpSum;
assign intermed_CDom_CAlignDist = CAlignDist[(clog2(sigWidth + 1) - 1):0];
assign intermed_highAlignedSigC =
`ifdef HardFloat_propagateNaNPayloads
isNaNOut ? fractNaN :
`endif
alignedSigC[(sigSumWidth - 1):(prodWidth + 1)];
endmodule
|
module
mulAddRecFNToRaw_postMul#(parameter expWidth = 3, parameter sigWidth = 3) (
intermed_compactState,
intermed_sExp,
intermed_CDom_CAlignDist,
intermed_highAlignedSigC,
mulAddResult,
roundingMode,
invalidExc,
out_isNaN,
out_isInf,
out_isZero,
out_sign,
out_sExp,
out_sig
);
`include "HardFloat_localFuncs.vi"
input [5:0] intermed_compactState;
input signed [(expWidth + 1):0] intermed_sExp;
input [(clog2(sigWidth + 1) - 1):0] intermed_CDom_CAlignDist;
input [(sigWidth + 1):0] intermed_highAlignedSigC;
input [sigWidth*2:0] mulAddResult;
input [2:0] roundingMode;
output invalidExc;
output out_isNaN;
output out_isInf;
output out_isZero;
output out_sign;
output signed [(expWidth + 1):0] out_sExp;
output [(sigWidth + 2):0] out_sig;
/*------------------------------------------------------------------------
*------------------------------------------------------------------------*/
localparam prodWidth = sigWidth*2;
localparam sigSumWidth = sigWidth + prodWidth + 3;
/*------------------------------------------------------------------------
*------------------------------------------------------------------------*/
wire specialCase = intermed_compactState[5];
assign invalidExc = specialCase && intermed_compactState[4];
assign out_isNaN = specialCase && intermed_compactState[3];
assign out_isInf = specialCase && intermed_compactState[2];
wire notNaN_addZeros = specialCase && intermed_compactState[1];
wire signProd = intermed_compactState[4];
wire doSubMags = intermed_compactState[3];
wire CIsDominant = intermed_compactState[2];
wire bit0AlignedSigC = intermed_compactState[1];
wire special_signOut = intermed_compactState[0];
`ifdef HardFloat_propagateNaNPayloads
wire [(sigWidth - 2):0] fractNaN = intermed_highAlignedSigC;
`endif
/*------------------------------------------------------------------------
*------------------------------------------------------------------------*/
wire opSignC = signProd ^ doSubMags;
wire [(sigWidth + 1):0] incHighAlignedSigC = intermed_highAlignedSigC + 1;
wire [(sigSumWidth - 1):0] sigSum =
{mulAddResult[prodWidth] ? incHighAlignedSigC
: intermed_highAlignedSigC,
mulAddResult[(prodWidth - 1):0],
bit0AlignedSigC};
wire roundingMode_min = (roundingMode == `round_min);
/*------------------------------------------------------------------------
*------------------------------------------------------------------------*/
wire CDom_sign = opSignC;
wire signed [(expWidth + 1):0] CDom_sExp = intermed_sExp - doSubMags;
wire [(sigWidth*2 + 1):0] CDom_absSigSum =
doSubMags ? ~sigSum[(sigSumWidth - 1):(sigWidth + 1)]
: {1'b0, intermed_highAlignedSigC[(sigWidth + 1):sigWidth],
sigSum[(sigSumWidth - 3):(sigWidth + 2)]};
wire CDom_absSigSumExtra =
doSubMags ? !(&sigSum[sigWidth:1]) : |sigSum[(sigWidth + 1):1];
wire [(sigWidth + 4):0] CDom_mainSig =
(CDom_absSigSum<<intermed_CDom_CAlignDist)>>(sigWidth - 3);
wire [((sigWidth | 3) - 1):0] CDom_grainAlignedLowSig =
CDom_absSigSum[(sigWidth - 1):0]<<(~sigWidth & 3);
wire [sigWidth/4:0] CDom_reduced4LowSig;
compressBy4#(sigWidth | 3)
compressBy4_CDom_absSigSum(
CDom_grainAlignedLowSig, CDom_reduced4LowSig);
wire [(sigWidth/4 - 1):0] CDom_sigExtraMask;
lowMaskLoHi#(clog2(sigWidth + 1) - 2, 0, sigWidth/4)
lowMask_CDom_sigExtraMask(
intermed_CDom_CAlignDist[(clog2(sigWidth + 1) - 1):2],
CDom_sigExtraMask
);
wire CDom_reduced4SigExtra = |(CDom_reduced4LowSig & CDom_sigExtraMask);
wire [(sigWidth + 2):0] CDom_sig =
{CDom_mainSig>>3,
(|CDom_mainSig[2:0]) || CDom_reduced4SigExtra || CDom_absSigSumExtra};
/*------------------------------------------------------------------------
*------------------------------------------------------------------------*/
wire notCDom_signSigSum = sigSum[prodWidth + 3];
wire [(prodWidth + 2):0] notCDom_absSigSum =
notCDom_signSigSum ? ~sigSum[(prodWidth + 2):0]
: sigSum[(prodWidth + 2):0] + doSubMags;
wire [(prodWidth + 2)/2:0] notCDom_reduced2AbsSigSum;
compressBy2#(prodWidth + 3)
compressBy2_notCDom_absSigSum(
notCDom_absSigSum, notCDom_reduced2AbsSigSum);
wire [(clog2(prodWidth + 4) - 2):0] notCDom_normDistReduced2;
countLeadingZeros#((prodWidth + 2)/2 + 1, clog2(prodWidth + 4) - 1)
countLeadingZeros_notCDom(
notCDom_reduced2AbsSigSum, notCDom_normDistReduced2);
wire [(clog2(prodWidth + 4) - 1):0] notCDom_nearNormDist =
notCDom_normDistReduced2<<1;
wire signed [(expWidth + 1):0] notCDom_sExp =
intermed_sExp - notCDom_nearNormDist;
wire [(sigWidth + 4):0] notCDom_mainSig =
({1'b0, notCDom_absSigSum}<<notCDom_nearNormDist)>>(sigWidth - 1);
wire [(((sigWidth/2 + 1) | 1) - 1):0] CDom_grainAlignedLowReduced2Sig =
notCDom_reduced2AbsSigSum[sigWidth/2:0]<<((sigWidth/2) & 1);
wire [(sigWidth + 2)/4:0] notCDom_reduced4AbsSigSum;
compressBy2#((sigWidth/2 + 1) | 1)
compressBy2_notCDom_reduced2AbsSigSum(
CDom_grainAlignedLowReduced2Sig, notCDom_reduced4AbsSigSum);
wire [((sigWidth + 2)/4 - 1):0] notCDom_sigExtraMask;
lowMaskLoHi#(clog2(prodWidth + 4) - 2, 0, (sigWidth + 2)/4)
lowMask_notCDom_sigExtraMask(
notCDom_normDistReduced2[(clog2(prodWidth + 4) - 2):1],
notCDom_sigExtraMask
);
wire notCDom_reduced4SigExtra =
|(notCDom_reduced4AbsSigSum & notCDom_sigExtraMask);
wire [(sigWidth + 2):0] notCDom_sig =
{notCDom_mainSig>>3,
(|notCDom_mainSig[2:0]) || notCDom_reduced4SigExtra};
wire notCDom_completeCancellation =
(notCDom_sig[(sigWidth + 2):(sigWidth + 1)] == 0);
wire notCDom_sign =
notCDom_completeCancellation ? roundingMode_min
: signProd ^ notCDom_signSigSum;
/*------------------------------------------------------------------------
*------------------------------------------------------------------------*/
assign out_isZero =
notNaN_addZeros || (!CIsDominant && notCDom_completeCancellation);
assign out_sign =
( specialCase && special_signOut)
|| (!specialCase && CIsDominant && CDom_sign )
|| (!specialCase && !CIsDominant && notCDom_sign );
assign out_sExp = CIsDominant ? CDom_sExp : notCDom_sExp;
`ifdef HardFloat_propagateNaNPayloads
assign out_sig =
out_isNaN ? {1'b1, fractNaN, 2'b00}
: CIsDominant ? CDom_sig : notCDom_sig;
`else
assign out_sig = CIsDominant ? CDom_sig : notCDom_sig;
`endif
endmodule
|
module
mulAddRecFNToRaw#(parameter expWidth = 3, parameter sigWidth = 3) (
input [(`floatControlWidth - 1):0] control,
input [1:0] op,
input [(expWidth + sigWidth):0] a,
input [(expWidth + sigWidth):0] b,
input [(expWidth + sigWidth):0] c,
input [2:0] roundingMode,
output invalidExc,
output out_isNaN,
output out_isInf,
output out_isZero,
output out_sign,
output signed [(expWidth + 1):0] out_sExp,
output [(sigWidth + 2):0] out_sig
);
`include "HardFloat_localFuncs.vi"
wire [(sigWidth - 1):0] mulAddA, mulAddB;
wire [(sigWidth*2 - 1):0] mulAddC;
wire [5:0] intermed_compactState;
wire signed [(expWidth + 1):0] intermed_sExp;
wire [(clog2(sigWidth + 1) - 1):0] intermed_CDom_CAlignDist;
wire [(sigWidth + 1):0] intermed_highAlignedSigC;
mulAddRecFNToRaw_preMul#(expWidth, sigWidth)
mulAddToRaw_preMul(
control,
op,
a,
b,
c,
roundingMode,
mulAddA,
mulAddB,
mulAddC,
intermed_compactState,
intermed_sExp,
intermed_CDom_CAlignDist,
intermed_highAlignedSigC
);
wire [sigWidth*2:0] mulAddResult = mulAddA * mulAddB + mulAddC;
mulAddRecFNToRaw_postMul#(expWidth, sigWidth)
mulAddToRaw_postMul(
intermed_compactState,
intermed_sExp,
intermed_CDom_CAlignDist,
intermed_highAlignedSigC,
mulAddResult,
roundingMode,
invalidExc,
out_isNaN,
out_isInf,
out_isZero,
out_sign,
out_sExp,
out_sig
);
endmodule
|
module
mulAddRecFN#(parameter expWidth = 3, parameter sigWidth = 3) (
input [(`floatControlWidth - 1):0] control,
input [1:0] op,
input [(expWidth + sigWidth):0] a,
input [(expWidth + sigWidth):0] b,
input [(expWidth + sigWidth):0] c,
input [2:0] roundingMode,
output [(expWidth + sigWidth):0] out,
output [4:0] exceptionFlags
);
wire invalidExc, out_isNaN, out_isInf, out_isZero, out_sign;
wire signed [(expWidth + 1):0] out_sExp;
wire [(sigWidth + 2):0] out_sig;
mulAddRecFNToRaw#(expWidth, sigWidth)
mulAddRecFNToRaw(
control,
op,
a,
b,
c,
roundingMode,
invalidExc,
out_isNaN,
out_isInf,
out_isZero,
out_sign,
out_sExp,
out_sig
);
roundRawFNToRecFN#(expWidth, sigWidth, 0)
roundRawOut(
control,
invalidExc,
1'b0,
out_isNaN,
out_isInf,
out_isZero,
out_sign,
out_sExp,
out_sig,
roundingMode,
out,
exceptionFlags
);
endmodule
|
module nkmd_dai_tx_t;
// ins
reg clk;
parameter TCLK = 20;
initial clk = 0;
always #(TCLK/2) clk = ~clk;
reg rst;
reg pop;
reg [31:0] nkmd_data_i;
wire [31:0] nkmd_data_o;
reg [31:0] nkmd_addr;
reg nkmd_we;
nkmd_dai_tx uut(
.clk(clk),
.rst(rst),
.tx_pop_i(pop),
.data_i(nkmd_data_i),
.data_o(nkmd_data_o),
.addr_i(nkmd_addr),
.we_i(nkmd_we));
task queue;
input wire [23:0] sample;
begin
nkmd_addr = 32'h0000d001;
nkmd_data_i = {8'h0, sample};
nkmd_we = 1'b1;
#(TCLK);
nkmd_we = 1'b0;
end
endtask
task trigger_pop;
begin
pop = 1'b1;
#(TCLK);
pop = 1'b0;
end
endtask
reg [31:0] i;
initial begin
$dumpfile("nkmd_dai_tx_t.lxt");
$dumpvars(0, nkmd_dai_tx_t);
pop = 0;
nkmd_data_i = 32'h0;
nkmd_addr = 32'h0;
nkmd_we = 1'b0;
rst = 1'b1;
#(TCLK);
rst = 1'b0;
#(TCLK);
nkmd_addr = 32'h0000d001;
#(TCLK);
$display("expect %h, actual %h : queued_ff peek", 6'h0, uut.queued_ff);
$display("expect %h, actual %h : queued_ff ram read", 32'h0, nkmd_data_o);
queue(24'hcafebb);
nkmd_addr = 32'h0000e000;
#(TCLK);
$display("expect %h, actual %h : ringbuf ram read", 32'h00cafebb, nkmd_data_o);
nkmd_addr = 32'h0000d001;
#(TCLK);
$display("expect %h, actual %h : queued_ff peek", 6'h1, uut.queued_ff);
$display("expect %h, actual %h : queued_ff ram read", 32'h1, nkmd_data_o);
trigger_pop();
nkmd_addr = 32'h0000d001;
#(TCLK);
$display("expect %h, actual %h : queued_ff peek", 6'h0, uut.queued_ff);
$display("expect %h, actual %h : queued_ff ram read", 32'h0, nkmd_data_o);
for (i = 0; i < 63; i = i + 1) begin
queue(i);
end
$display("expect %h, actual %h : queued_ff peek", 6'd63, uut.queued_ff);
for (i = 0; i < 63; i = i + 1) begin
trigger_pop();
end
for (i = 63; i < 80; i = i + 1) begin
queue(i);
end
for (i = 63; i < 80; i = i + 1) begin
trigger_pop();
end
#(TCLK*3);
$finish(2);
end
always @(posedge clk) begin
if (uut.tx_ack_o)
$display("tx emit sample %h", uut.tx_data_o);
end
endmodule
|
module ssio_sdr_out #
(
// target ("SIM", "GENERIC", "XILINX", "ALTERA")
parameter TARGET = "GENERIC",
// IODDR style ("IODDR", "IODDR2")
// Use IODDR for Virtex-4, Virtex-5, Virtex-6, 7 Series, Ultrascale
// Use IODDR2 for Spartan-6
parameter IODDR_STYLE = "IODDR2",
// Width of register in bits
parameter WIDTH = 1
)
(
input wire clk,
input wire [WIDTH-1:0] input_d,
output wire output_clk,
output wire [WIDTH-1:0] output_q
);
oddr #(
.TARGET(TARGET),
.IODDR_STYLE(IODDR_STYLE),
.WIDTH(1)
)
clk_oddr_inst (
.clk(clk),
.d1(1'b0),
.d2(1'b1),
.q(output_clk)
);
(* IOB = "TRUE" *)
reg [WIDTH-1:0] output_q_reg = {WIDTH{1'b0}};
assign output_q = output_q_reg;
always @(posedge clk) begin
output_q_reg <= input_d;
end
endmodule
|
module rtc (
input clkin,
input pgm_we,
input [55:0] rtc_data_in,
input we1,
input [59:0] rtc_data_in1,
output [59:0] rtc_data
);
reg [59:0] rtc_data_r;
reg [59:0] rtc_data_out_r;
reg [1:0] pgm_we_sreg;
always @(posedge clkin) pgm_we_sreg <= {pgm_we_sreg[0], pgm_we};
wire pgm_we_rising = (pgm_we_sreg[1:0] == 2'b01);
reg [2:0] we1_sreg;
always @(posedge clkin) we1_sreg <= {we1_sreg[1:0], we1};
wire we1_rising = (we1_sreg[2:1] == 2'b01);
reg [31:0] tick_cnt;
always @(posedge clkin) begin
tick_cnt <= tick_cnt + 1;
if((tick_cnt == 21500000) || pgm_we_rising) tick_cnt <= 0;
end
assign rtc_data = rtc_data_out_r;
reg [21:0] rtc_state;
reg carry;
reg [3:0] dom1[11:0];
reg [3:0] dom10[11:0];
reg [3:0] month;
reg [1:0] year;
reg [4:0] dow_day;
reg [3:0] dow_month;
reg [13:0] dow_year;
reg [6:0] dow_year1;
reg [6:0] dow_year100;
reg [15:0] dow_tmp;
parameter [21:0]
STATE_SEC1 = 22'b0000000000000000000001,
STATE_SEC10 = 22'b0000000000000000000010,
STATE_MIN1 = 22'b0000000000000000000100,
STATE_MIN10 = 22'b0000000000000000001000,
STATE_HOUR1 = 22'b0000000000000000010000,
STATE_HOUR10 = 22'b0000000000000000100000,
STATE_DAY1 = 22'b0000000000000001000000,
STATE_DAY10 = 22'b0000000000000010000000,
STATE_MON1 = 22'b0000000000000100000000,
STATE_MON10 = 22'b0000000000001000000000,
STATE_YEAR1 = 22'b0000000000010000000000,
STATE_YEAR10 = 22'b0000000000100000000000,
STATE_YEAR100 = 22'b0000000001000000000000,
STATE_YEAR1000 = 22'b0000000010000000000000,
STATE_DOW0 = 22'b0000000100000000000000,
STATE_DOW1 = 22'b0000001000000000000000,
STATE_DOW2 = 22'b0000010000000000000000,
STATE_DOW3 = 22'b0000100000000000000000,
STATE_DOW4 = 22'b0001000000000000000000,
STATE_DOW5 = 22'b0010000000000000000000,
STATE_LATCH = 22'b0100000000000000000000,
STATE_IDLE = 22'b1000000000000000000000;
initial begin
rtc_state = STATE_IDLE;
dom1[0] = 1; dom10[0] = 3;
dom1[1] = 8; dom10[1] = 2;
dom1[2] = 1; dom10[2] = 3;
dom1[3] = 0; dom10[3] = 3;
dom1[4] = 1; dom10[4] = 3;
dom1[5] = 0; dom10[5] = 3;
dom1[6] = 1; dom10[6] = 3;
dom1[7] = 1; dom10[7] = 3;
dom1[8] = 0; dom10[8] = 3;
dom1[9] = 1; dom10[9] = 3;
dom1[10] = 0; dom10[10] = 3;
dom1[11] = 1; dom10[11] = 3;
month = 0;
rtc_data_r = 60'h220110301000000;
tick_cnt = 0;
end
wire is_leapyear_feb = (month == 1) && (year[1:0] == 2'b00);
always @(posedge clkin) begin
if(!tick_cnt) begin
rtc_state <= STATE_SEC1;
end else begin
case (rtc_state)
STATE_SEC1:
rtc_state <= STATE_SEC10;
STATE_SEC10:
rtc_state <= STATE_MIN1;
STATE_MIN1:
rtc_state <= STATE_MIN10;
STATE_MIN10:
rtc_state <= STATE_HOUR1;
STATE_HOUR1:
rtc_state <= STATE_HOUR10;
STATE_HOUR10:
rtc_state <= STATE_DAY1;
STATE_DAY1:
rtc_state <= STATE_DAY10;
STATE_DAY10:
rtc_state <= STATE_MON1;
STATE_MON1:
rtc_state <= STATE_MON10;
STATE_MON10:
rtc_state <= STATE_YEAR1;
STATE_YEAR1:
rtc_state <= STATE_YEAR10;
STATE_YEAR10:
rtc_state <= STATE_YEAR100;
STATE_YEAR100:
rtc_state <= STATE_YEAR1000;
STATE_YEAR1000:
rtc_state <= STATE_DOW0;
STATE_DOW0:
rtc_state <= STATE_DOW1;
STATE_DOW1:
rtc_state <= STATE_DOW2;
STATE_DOW2:
rtc_state <= STATE_DOW3;
STATE_DOW3:
rtc_state <= STATE_DOW4;
STATE_DOW4:
if(dow_tmp > 13)
rtc_state <= STATE_DOW4;
else
rtc_state <= STATE_DOW5;
STATE_DOW5:
rtc_state <= STATE_LATCH;
STATE_LATCH:
rtc_state <= STATE_IDLE;
default:
rtc_state <= STATE_IDLE;
endcase
end
end
always @(posedge clkin) begin
if(pgm_we_rising) begin
rtc_data_r[55:0] <= rtc_data_in;
end else if (we1_rising) begin
rtc_data_r <= rtc_data_in1;
end else begin
case(rtc_state)
STATE_SEC1: begin
if(rtc_data_r[3:0] == 9) begin
rtc_data_r[3:0] <= 0;
carry <= 1;
end else begin
rtc_data_r[3:0] <= rtc_data_r[3:0] + 1;
carry <= 0;
end
end
STATE_SEC10: begin
if(carry) begin
if(rtc_data_r[7:4] == 5) begin
rtc_data_r[7:4] <= 0;
carry <= 1;
end else begin
rtc_data_r[7:4] <= rtc_data_r[7:4] + 1;
carry <= 0;
end
end
end
STATE_MIN1: begin
if(carry) begin
if(rtc_data_r[11:8] == 9) begin
rtc_data_r[11:8] <= 0;
carry <= 1;
end else begin
rtc_data_r[11:8] <= rtc_data_r[11:8] + 1;
carry <= 0;
end
end
end
STATE_MIN10: begin
if(carry) begin
if(rtc_data_r[15:12] == 5) begin
rtc_data_r[15:12] <= 0;
carry <= 1;
end else begin
rtc_data_r[15:12] <= rtc_data_r[15:12] + 1;
carry <= 0;
end
end
end
STATE_HOUR1: begin
if(carry) begin
if(rtc_data_r[23:20] == 2 && rtc_data_r[19:16] == 3) begin
rtc_data_r[19:16] <= 0;
carry <= 1;
end else if (rtc_data_r[19:16] == 9) begin
rtc_data_r[19:16] <= 0;
carry <= 1;
end else begin
rtc_data_r[19:16] <= rtc_data_r[19:16] + 1;
carry <= 0;
end
end
end
STATE_HOUR10: begin
if(carry) begin
if(rtc_data_r[23:20] == 2) begin
rtc_data_r[23:20] <= 0;
carry <= 1;
end else begin
rtc_data_r[23:20] <= rtc_data_r[23:20] + 1;
carry <= 0;
end
end
end
STATE_DAY1: begin
if(carry) begin
if(rtc_data_r[31:28] == dom10[month]
&& rtc_data_r[27:24] == dom1[month] + is_leapyear_feb) begin
rtc_data_r[27:24] <= 0;
carry <= 1;
end else if (rtc_data_r[27:24] == 9) begin
rtc_data_r[27:24] <= 0;
carry <= 1;
end else begin
rtc_data_r[27:24] <= rtc_data_r[27:24] + 1;
carry <= 0;
end
end
end
STATE_DAY10: begin
if(carry) begin
if(rtc_data_r[31:28] == dom10[month]) begin
rtc_data_r[31:28] <= 0;
rtc_data_r[27:24] <= 1;
carry <= 1;
end else begin
rtc_data_r[31:28] <= rtc_data_r[31:28] + 1;
carry <= 0;
end
end
end
STATE_MON1: begin
if(carry) begin
if(rtc_data_r[39:36] == 1 && rtc_data_r[35:32] == 2) begin
rtc_data_r[35:32] <= 1;
carry <= 1;
end else if (rtc_data_r[35:32] == 9) begin
rtc_data_r[35:32] <= 0;
carry <= 1;
end else begin
rtc_data_r[35:32] <= rtc_data_r[35:32] + 1;
carry <= 0;
end
end
end
STATE_MON10: begin
if(carry) begin
if(rtc_data_r[39:36] == 1) begin
rtc_data_r[39:36] <= 0;
carry <= 1;
end else begin
rtc_data_r[39:36] <= rtc_data_r[39:36] + 1;
carry <= 0;
end
end
end
STATE_YEAR1: begin
month <= rtc_data_r[35:32] + (rtc_data_r[36] ? 10 : 0) - 1;
if(carry) begin
if(rtc_data_r[43:40] == 9) begin
rtc_data_r[43:40] <= 0;
carry <= 1;
end else begin
rtc_data_r[43:40] <= rtc_data_r[43:40] + 1;
carry <= 0;
end
end
end
STATE_YEAR10: begin
if(carry) begin
if(rtc_data_r[47:44] == 9) begin
rtc_data_r[47:44] <= 0;
carry <= 1;
end else begin
rtc_data_r[47:44] <= rtc_data_r[47:44] + 1;
carry <= 0;
end
end
end
STATE_YEAR100: begin
if(carry) begin
if(rtc_data_r[51:48] == 9) begin
rtc_data_r[51:48] <= 0;
carry <= 1;
end else begin
rtc_data_r[51:48] <= rtc_data_r[51:48] + 1;
carry <= 0;
end
end
end
STATE_YEAR1000: begin
if(carry) begin
if(rtc_data_r[55:52] == 9) begin
rtc_data_r[55:52] <= 0;
carry <= 1;
end else begin
rtc_data_r[55:52] <= rtc_data_r[55:52] + 1;
carry <= 0;
end
end
end
STATE_DOW0: begin
dow_year1 <= rtc_data_r[43:40]
+(rtc_data_r[47:44] << 1) + (rtc_data_r[47:44] << 3);
dow_year100 <= rtc_data_r[51:48]
+(rtc_data_r[55:52] << 1) + (rtc_data_r[55:52] << 3);
dow_month <= month + 1;
dow_day <= rtc_data_r[27:24]
+ (rtc_data_r[31:28] << 1)
+ (rtc_data_r[31:28] << 3);
end
STATE_DOW1: begin
year <= dow_year1[1:0];
if(dow_month <= 2) begin
dow_month <= dow_month + 10;
dow_year <= dow_year1
+ (dow_year100 << 2)
+ (dow_year100 << 5)
+ (dow_year100 << 6) - 1;
if(dow_year1)
dow_year1 <= dow_year1 - 1;
else begin
dow_year1 <= 99;
dow_year100 <= dow_year100 - 1;
end
end else begin
dow_month <= dow_month - 2;
dow_year <= dow_year1 + (dow_year100 << 2) + (dow_year100 << 5) + (dow_year100 << 6);
end
end
STATE_DOW2: begin
dow_tmp <= (83 * dow_month);
end
STATE_DOW3: begin
dow_tmp <= (dow_tmp >> 5)
+ dow_day
+ dow_year
+ (dow_year >> 2)
- (dow_year100)
+ (dow_year100 >> 2);
end
STATE_DOW4: begin
dow_tmp <= dow_tmp - 7;
end
STATE_DOW5: begin
rtc_data_r[59:56] <= {1'b0, dow_tmp[2:0]};
end
STATE_LATCH: begin
rtc_data_out_r <= rtc_data_r;
end
endcase
end
end
endmodule
|
module sky130_fd_sc_hvl__mux4 (
//# {{data|Data Signals}}
input A0 ,
input A1 ,
input A2 ,
input A3 ,
output X ,
//# {{control|Control Signals}}
input S0 ,
input S1 ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
|
module sky130_fd_sc_ms__sdfrtp (
Q ,
CLK ,
D ,
SCD ,
SCE ,
RESET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
// Module ports
output Q ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input RESET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
// Local signals
wire buf_Q ;
wire RESET ;
wire mux_out;
// Delay Name Output Other arguments
not not0 (RESET , RESET_B );
sky130_fd_sc_ms__udp_mux_2to1 mux_2to10 (mux_out, D, SCD, SCE );
sky130_fd_sc_ms__udp_dff$PR_pp$PG$N `UNIT_DELAY dff0 (buf_Q , mux_out, CLK, RESET, , VPWR, VGND);
buf buf0 (Q , buf_Q );
endmodule
|
module sky130_fd_sc_hs__sdfrbp (
//# {{data|Data Signals}}
input D ,
output Q ,
output Q_N ,
//# {{control|Control Signals}}
input RESET_B,
//# {{scanchain|Scan Chain}}
input SCD ,
input SCE ,
//# {{clocks|Clocking}}
input CLK
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
endmodule
|
module main(
// clocks
input fclk,
output clkz_out,
input clkz_in,
// z80
input iorq_n,
input mreq_n,
input rd_n,
input wr_n,
input m1_n,
input rfsh_n,
output int_n,
output nmi_n,
output wait_n,
output res,
inout [7:0] d,
input [15:0] a,
// zxbus and related
output csrom,
output romoe_n,
output romwe_n,
output rompg0_n,
output dos_n, // aka rompg1
output rompg2,
output rompg3,
output rompg4,
input iorqge1,
input iorqge2,
output iorq1_n,
output iorq2_n,
// DRAM
inout [15:0] rd,
output [9:0] ra,
output rwe_n,
output rucas_n,
output rlcas_n,
output rras0_n,
output rras1_n,
// video
output [1:0] vred,
output [1:0] vgrn,
output [1:0] vblu,
output vhsync,
output vvsync,
output vcsync,
// AY control and audio/tape
output ay_clk,
output ay_bdir,
output ay_bc1,
output beep,
// IDE
output [2:0] ide_a,
inout [15:0] ide_d,
output ide_dir,
input ide_rdy,
output ide_cs0_n,
output ide_cs1_n,
output ide_rs_n,
output ide_rd_n,
output ide_wr_n,
// VG93 and diskdrive
output vg_clk,
output vg_cs_n,
output vg_res_n,
output vg_hrdy,
output vg_rclk,
output vg_rawr,
output [1:0] vg_a, // disk drive selection
output vg_wrd,
output vg_side,
input step,
input vg_sl,
input vg_sr,
input vg_tr43,
input rdat_b_n,
input vg_wf_de,
input vg_drq,
input vg_irq,
input vg_wd,
// serial links (atmega-fpga, sdcard)
output sdcs_n,
output sddo,
output sdclk,
input sddi,
input spics_n,
input spick,
input spido,
output spidi,
output spiint_n
);
wire zclk; // z80 clock for short
reg [2:0] zclk_gen; // make 3.5 mhz clock
wire rst_n; // global reset
wire rrdy;
wire cbeg;
wire [15:0] rddata;
wire [4:0] rompg;
wire [7:0] zports_dout;
wire zports_dataout;
wire porthit;
wire [4:0] keys;
wire tape_in;
wire [15:0] ideout;
wire [15:0] idein;
wire [7:0] zmem_dout;
wire zmem_dataout;
wire [7:0] sd_dout_to_zports;
wire start_from_zports;
wire sd_inserted;
wire sd_readonly;
reg [3:0] ayclk_gen;
wire [7:0] received;
wire [7:0] tobesent;
wire intrq,drq;
wire vg_wrFF;
// Z80 clock control
assign zclk = clkz_in;
always @(posedge fclk)
zclk_gen <= zclk_gen + 3'd1;
assign clkz_out = zclk_gen[2];
/* // RESETTER
resetter myrst( .clk(fclk),
.rst_in1_n(1'b1),
.rst_in2_n(1'b1),
.rst_out_n(rst_n) );
defparam myrst.RST_CNT_SIZE = 6;
*/
dram mydram( .clk(fclk),
.rst_n(1'b1),
.ra(ra),
.rd(rd),
.rwe_n(rwe_n),
.rras0_n(rras0_n),
.rras1_n(rras1_n),
.rucas_n(rucas_n),
.rlcas_n(rlcas_n),
.req(1'b0),
.rnw(1'b1)//,
//.rrdy(rrdy),
//.cbeg(cbeg),
//.bsel({a[0],~a[0]}),
//.wrdata({d,~d}),
//.rddata(rddata),
/*.addr({a[5:0],a[15:1]})*/ );
assign int_n=1'b1;
assign nmi_n=1'b1;
assign wait_n=1'b1;
assign res=1'b1;
assign d=8'hZZ;
assign csrom=1'b0;
assign romoe_n=1'b1;
assign romwe_n=1'b1;
assign iorq1_n=1'b1;
assign iorq2_n=1'b1;
assign rd=16'hZZZZ;
assign ay_bdir=1'b0;
assign ay_bc1=1'b0;
assign ide_d=16'hZZZZ;
assign ide_dir=1'b1;
assign ide_rs_n = 1'b0;
assign ide_cs1_n = 1'b1;
assign ide_rd_n = 1'b1;
assign ide_wr_n = 1'b1;
assign vg_cs_n=1'b1;
assign vg_res_n=1'b0;
assign sdcs_n=1'b1;
assign spiint_n=1'b1;
//AY control
always @(posedge fclk)
begin
ayclk_gen <= ayclk_gen + 4'd1;
end
assign ay_clk = ayclk_gen[3];
reg [23:0] counter;
reg blinker;
always @(posedge fclk)
begin
if( !counter )
begin
counter <= 24'd13999999;
blinker <= ~blinker;
end
else
counter <= counter - 24'd1;
end
assign ide_cs0_n = blinker;
endmodule
|
module `CPUNAME
(input clk,
input rst,
input [31:0] ram_data_in_a,
output [31:0] ram_addr_in_a,
input [31:0] ram_data_in_b,
output [31:0] ram_addr_in_b,
output [31:0] ram_data_out_b,
output ram_we_out,
/**************************/
// TODO: also include hoisted external signals
`IPATH(soccpusignals.v)
/**************************/
input stall_cpu // external stall
);
//---------------------------------------------------
//--1. Clock counter, for debugging and perf counters
//---------------------------------------------------
reg [31:0] clkcounter;
always @(posedge clk)
if (~rst) clkcounter <= 0;
else clkcounter <= clkcounter + 1;
// COMMON Stall logic
wire stall_exec;
wire stall_mem;
wire stall;
wire stall_but_ext;
reg unstall;
assign stall = stall_cpu | stall_exec | stall_mem; // ?!?
assign stall_but_ext = 0; // ?!?
assign stall_mem = 0;
//------------------------------------------------
//--2. FETCH logic--------------------------------
//------------------------------------------------
reg [31:0] fetch_PC; // PC value at the end of FETCH stage / in DECODE0 stage
wire [31:0] decode0_PC;
assign decode0_PC = fetch_PC;
wire [31:0] fetch_PC_next; // PC value in the FETCH stage
`ifndef RAM_REGISTERED_OUT
assign ram_addr_in_a = fetch_PC;
`else
assign ram_addr_in_a = fetch_PC_next;
`endif
wire decode0_branch_override1;
wire exec_branch_override2;
wire [31:0] decode0_PC_next; // PC value inferred at the DECODE stage
wire [31:0] exec_PC_next; // PC value inferred at the EXEC stage
reg decode_ready; // It's not the first clock cycle
assign fetch_PC_next = decode_ready?
(decode0_branch_override1?decode0_PC_next:
exec_branch_override2?exec_PC_next:
fetch_microops?fetch_PC:(fetch_PC + 1)):fetch_PC;
always @(posedge clk)
if (~rst) begin
fetch_PC <= 0;
decode_ready <= 0;
unstall <= 0;
end else begin
fetch_PC <= stall?fetch_PC:fetch_PC_next;
decode_ready <= 1;
unstall <= stall;
end
//------------------------------------------------
//--3. DECODE0 logic------------------------------
//------------------------------------------------
wire fetch_microops;
wire [31:0] fetch_next_muop;
wire [31:0] decode0_Instr; // Instruction as of beginning of DECODE0
reg [31:0] decode0_Instr_r;
reg stall_r;
// decode0_Instr arrives in the DECODE0 stage (from a PC address formed in the FETCH stage),
// or is generated by the muop FSM if it's a multi-stage instruction and muops are enabled.
assign decode0_Instr = stall_r?decode0_Instr_r:(
exec_typeee?0: // If it's a second part of a long extended instruction, push a bubble
fetch_microops?fetch_next_muop:
ram_data_in_a);
wire [4:0] decode0_reg1addr_next;
wire [4:0] decode0_reg2addr_next;
reg [4:0] decode_reg1addr;
reg [4:0] decode_reg2addr;
wire decode0_typea;
wire decode0_typeb1;
wire decode0_typeb2;
wire decode0_typei;
wire decode0_typee;
wire decode0_typem;
assign decode0_typea = decode0_Instr[2:0] == 0; // also true for type E and type EE
assign decode0_typeb1 = decode0_Instr[1:0] == 2'b01;
assign decode0_typeb2 = decode0_Instr[1:0] == 2'b11;
assign decode0_typei = decode0_Instr[1:0] == 2'b10;
assign decode0_typem = decode0_Instr[2:0] == 3'b100;
assign decode0_typee = decode0_Instr[6:0] == 7'b1111000;
assign decode0_reg1addr_next = decode0_typea?decode0_Instr[16:12]:
decode0_typeb2?decode0_Instr[7:3]:
decode0_typem?decode0_Instr[9:5]:0;
assign decode0_reg2addr_next = decode0_typea?decode0_Instr[21:17]:
decode0_typeb2?decode0_Instr[12:8]:
decode0_typem?decode0_Instr[14:10]:0;
assign decode0_branch_override1 = decode_ready?decode0_typeb1:0;
// Forwarding the simple branching PC value - 0 delay slots
wire [31:0] decode0_simmed29;
assign decode0_simmed29 = {{3{decode0_Instr[31]}},decode0_Instr[31:3]};
assign decode0_PC_next = decode0_typeb1?
(decode0_Instr[2]?(fetch_PC + decode0_simmed29):decode0_Instr[31:3]):
(fetch_PC + 1);
reg [31:0] decode_Instr;
reg [31:0] decode_PC;
wire [31:0] decode0_reg1addr_next1;
wire [31:0] decode0_reg2addr_next1;
assign decode0_reg1addr_next1 = stall?decode_reg1addr:decode0_reg1addr_next;
assign decode0_reg2addr_next1 = stall?decode_reg2addr:decode0_reg2addr_next;
always @(posedge clk)
if (~rst) begin
decode_reg1addr <= 0;
decode_reg2addr <= 0;
decode_PC <= 0;
decode_Instr <= 0;
// Stall logic:
decode0_Instr_r <= 0;
stall_r <= 0;
end else begin
decode_reg1addr <= decode0_reg1addr_next1;
decode_reg2addr <= decode0_reg2addr_next1;
decode_PC <= (stall|fetch_microops)?decode_PC:decode0_PC;
decode_Instr <= stall?decode_Instr:decode0_Instr;
decode0_Instr_r <= decode0_Instr;
stall_r <= stall;
end // else: !if(~rst)
// MUOP logic for DECODE0
`ifndef DISABLE_MICROOPS
wire is_muop;
wire is_call;
wire is_ret;
wire executing_microops;
assign fetch_microops = is_muop | executing_microops;
assign is_muop = (~executing_microops) & (ram_data_in_a[2:0] == 1);
assign is_ret = ram_data_in_a[31:3] == 0;
assign is_call = ~is_ret;
reg [31:0] next_muop_r;
assign fetch_next_muop = is_muop? // starting insn
(is_call?32'hfffff7bc: // (storei SP SP (const -1))
32'h1fba4): // (load SP FP (const 3))
next_muop_r;
reg [28:0] muop_call_dst;
reg [3:0] muop_state;
localparam S_MU_IDLE = 0;
localparam S_MU_CALL1 = 1;
localparam S_MU_CALL2 = 2;
localparam S_MU_RET1 = 3;
localparam S_MU_RET2 = 4;
localparam S_MU_RET3 = 5;
localparam S_MU_RET4 = 6;
localparam S_MU_DONE = 7;
assign executing_microops = muop_state != S_MU_IDLE;
always @(posedge clk)
if (~rst) begin
next_muop_r <= 0;
muop_call_dst <= 0;
muop_state <= S_MU_IDLE;
end else begin
case (muop_state)
S_MU_IDLE: begin
if (is_muop) begin // start muops
muop_call_dst <= ram_data_in_a[31:3];
if (is_call) begin
muop_state <= S_MU_CALL1;
next_muop_r <= 32'hfffff7dc; // (storei SP FP (const -1))
end else begin
muop_state <= S_MU_RET1;
next_muop_r <= 32'hfb84; // (load SC FP (const 1))
end
end
end
S_MU_CALL1: begin
muop_state <= S_MU_CALL2;
next_muop_r <= 32'hfffff7fc;
end
S_MU_CALL2: begin
muop_state <= S_MU_DONE;
next_muop_r <= {muop_call_dst, 3'b001};
end
S_MU_RET1: begin
next_muop_r <= 32'h17bc4; // (load FP FP (const 2))
muop_state <= S_MU_RET2;
end
S_MU_RET2: begin
next_muop_r <= 32'h9c0f; // (jmpci R1 SC (const 1))
muop_state <= S_MU_RET3;
end
S_MU_RET3: begin
next_muop_r <= 0;
muop_state <= S_MU_RET4;
end
S_MU_RET4: begin
next_muop_r <= 0;
muop_state <= S_MU_DONE;
end
S_MU_DONE: begin
muop_state <= S_MU_IDLE;
end
endcase
end // else: !if(~rst)
`else // !`ifndef DISABLE_MICROOPS
assign fetch_microops = 0;
assign fetch_next_muop = 0;
`endif
//------------------------------------------------
//--4. DECODE logic-------------------------------
//------------------------------------------------
wire fwd_mem;
wire [31:0] fwd_mem_data;
wire [4:0] fwd_mem_reg;
wire fwd_wb;
wire [31:0] fwd_wb_data;
wire [4:0] fwd_wb_reg;
wire [31:0] decode_arg1_next;
wire [31:0] decode_arg2_next;
// Register values returned from the regfile (as requested by the DECODE0 stage)
wire [31:0] decode_arg1_out;
wire [31:0] decode_arg2_out;
reg [31:0] decode_arg1_out_r;
reg [31:0] decode_arg2_out_r;
wire [31:0] decode_arg1_out_s = (unstall)?decode_arg1_out_r:decode_arg1_out;
wire [31:0] decode_arg2_out_s = (unstall)?decode_arg2_out_r:decode_arg2_out;
// Register argument values amended with forwarding (TODO!)
// Forwarding: WB -> DECODE
assign decode_arg1_next =
(fwd_mem &(fwd_mem_reg!=0)&(decode_reg1addr == fwd_mem_reg))?fwd_mem_data:
(fwd_wb &(fwd_wb_reg!=0)&(decode_reg1addr == fwd_wb_reg))?fwd_wb_data:
decode_arg1_out_s;
assign decode_arg2_next =
(fwd_mem &(fwd_mem_reg!=0)&(decode_reg2addr == fwd_mem_reg))?fwd_mem_data:
(fwd_wb &(fwd_wb_reg!=0)&(decode_reg2addr == fwd_wb_reg))?fwd_wb_data:
decode_arg2_out_s;
reg [31:0] exec_Instr;
reg [31:0] exec_PC;
reg [31:0] exec_arg1_r;
reg [31:0] exec_arg2_r;
reg [4:0] exec_reg1addr;
reg [4:0] exec_reg2addr;
`ifdef ICE_DEBUG
assign PCdebug = exec_PC;
`endif
always @(posedge clk)
if (~rst) begin
exec_Instr <= 0;
exec_PC <= 0;
exec_arg1_r <= 0;
exec_arg2_r <= 0;
exec_reg1addr <= 0;
exec_reg2addr <= 0;
decode_arg1_out_r <= 0;
decode_arg2_out_r <= 0;
end else begin
exec_Instr <= stall?exec_Instr:decode_Instr;
exec_PC <= stall?exec_PC:decode_PC;
exec_arg1_r <= stall?exec_arg1:decode_arg1_next;
exec_arg2_r <= stall?exec_arg2:decode_arg2_next;
exec_reg1addr <= stall?exec_reg1addr:decode_reg1addr;
exec_reg2addr <= stall?exec_reg2addr:decode_reg2addr;
decode_arg1_out_r <= decode_arg1_out_s;
decode_arg2_out_r <= decode_arg2_out_s;
end // else: !if(~rst)
//------------------------------------------------
//--5. EXEC logic---------------------------------
//------------------------------------------------
wire [31:0] exec_arg1;
wire [31:0] exec_arg2;
// Apply simple forwarding (MEM -> EXEC) and WB->EXEC
wire fwd_simple;
wire [31:0] fwd_simple_data;
wire [4:0] fwd_simple_reg;
assign exec_arg1 = (fwd_simple&(fwd_simple_reg!=0)&(exec_reg1addr == fwd_simple_reg))?fwd_simple_data:
(fwd_mem &(fwd_mem_reg!=0)&(exec_reg1addr == fwd_mem_reg))?fwd_mem_data:
(fwd_wb &(fwd_wb_reg!=0)&(exec_reg1addr == fwd_wb_reg))?fwd_wb_data:
exec_arg1_r;
assign exec_arg2 = (fwd_simple&(fwd_simple_reg!=0)&(exec_reg2addr == fwd_simple_reg))?fwd_simple_data:
(fwd_mem &(fwd_mem_reg!=0)&(exec_reg2addr == fwd_mem_reg))?fwd_mem_data:
(fwd_wb &(fwd_wb_reg!=0)&(exec_reg2addr == fwd_wb_reg))?fwd_wb_data:
exec_arg2_r;
wire exec_typei;
assign exec_typei = exec_Instr[1:0] == 2'b10;
wire [3:0] exec_opcode_typeA;
assign exec_opcode_typeA = exec_Instr[6:3];
wire exec_typee;
wire exec_typeee;
wire exec_isext;
wire exec_typeb2;
wire exec_typem;
wire exec_typea;
reg mem_typee;
reg mem_typei;
reg mem_typem;
reg mem_typea;
assign exec_typea = exec_Instr[2:0] == 0;
wire exec_ext_hasout;
assign exec_ext_hasout = exec_typee;
assign exec_isext = exec_typee;
assign exec_typeb2 = exec_Instr[1:0] == 2'b11;
assign exec_typem = exec_Instr[2:0] == 3'b100;
assign exec_typee = exec_Instr[6:0] == 7'b1111000;
assign exec_typeee = exec_typee & ( exec_Instr[31:22] == 10'b1111111111 );
localparam OPC_AND = 1;
localparam OPC_ADD = 2;
localparam OPC_SUB = 3;
localparam OPC_OR = 4;
localparam OPC_NOT = 5;
localparam OPC_SHL = 6;
localparam OPC_SHR = 7;
localparam OPC_XOR = 8;
localparam OPC_EQ = 9;
localparam OPC_NE = 10;
localparam OPC_CMP = 11;
localparam OPC_ASHR = 12;
localparam OPC_SELECT = 14;
localparam CMP_SLT = 0;
localparam CMP_SGT = 1;
localparam CMP_SLE = 2;
localparam CMP_SGE = 3;
localparam CMP_ULT = 4;
localparam CMP_UGT = 5;
localparam CMP_ULE = 6;
localparam CMP_UGE = 7;
wire [9:0] exec_immed10;
wire [31:0] exec_immed_signext;
assign exec_immed10 = exec_Instr[31:22];
assign exec_immed_signext = {{22{exec_Instr[31]}},exec_Instr[31:22]};
wire [31:0] exec_immed25_signext;
assign exec_immed25_signext = {{7{exec_Instr[31]}},exec_Instr[31:7]};
wire [31:0] exec_out_cmp;
assign exec_out_cmp = (exec_immed10[2:0] == CMP_SLT)?($signed(exec_arg1)<$signed(exec_arg2)):
(exec_immed10[2:0] == CMP_SGT)?($signed(exec_arg1)>$signed(exec_arg2)):
`ifndef DISABLE_CMPOPS
(exec_immed10[2:0] == CMP_SLE)?($signed(exec_arg1)<=$signed(exec_arg2)):
(exec_immed10[2:0] == CMP_SGE)?($signed(exec_arg1)>=$signed(exec_arg2)):
(exec_immed10[2:0] == CMP_ULT)?(exec_arg1<exec_arg2):
(exec_immed10[2:0] == CMP_UGT)?(exec_arg1>exec_arg2):
(exec_immed10[2:0] == CMP_ULE)?(exec_arg1<=exec_arg2):
(exec_immed10[2:0] == CMP_UGE)?(exec_arg1>=exec_arg2):
`endif
0;
wire [31:0] exec_out_next_alu;
assign exec_out_next_alu = (exec_opcode_typeA == OPC_ADD)?
(exec_arg1 + exec_arg2):
(exec_opcode_typeA == OPC_SUB)?
(exec_arg1 - exec_arg2):
(exec_opcode_typeA == OPC_AND)?
(exec_arg1 & exec_arg2):
(exec_opcode_typeA == OPC_OR)?
(exec_arg1 | exec_arg2):
(exec_opcode_typeA == OPC_XOR)?
(exec_arg1 ^ exec_arg2):
(exec_opcode_typeA == OPC_NOT)?
(~exec_arg1):
`ifdef ENABLE_BARREL_SHIFTER
(exec_opcode_typeA == OPC_SHL)?(exec_arg1 << exec_arg2):
(exec_opcode_typeA == OPC_SHR)?(exec_arg1 >> exec_arg2):
(exec_opcode_typeA == OPC_ASHR)?$signed($signed(exec_arg1) >>> exec_arg2):
`else
(exec_opcode_typeA == OPC_SHL)?(exec_arg1 << 1):
(exec_opcode_typeA == OPC_SHR)?(exec_arg1>>1):
(exec_opcode_typeA == OPC_ASHR)?({exec_arg1[31],exec_arg1[31:1]}):
`endif
(exec_opcode_typeA == OPC_EQ)?
(exec_arg1 ==
((exec_immed_signext == 0)?
exec_arg2:exec_immed_signext)):
(exec_opcode_typeA == OPC_NE)?
(exec_arg1 != exec_arg2):
(exec_opcode_typeA == OPC_CMP)?
(exec_out_cmp):
(exec_opcode_typeA == OPC_SELECT)?
(fwd_simple_data[0]?exec_arg1:exec_arg2):0;
wire [1:0] exec_opcode_typeM;
assign exec_opcode_typeM = exec_Instr[4:3];
localparam OPC_LOAD = 0;
localparam OPC_LOADR = 2;
localparam OPC_STORE = 1;
localparam OPC_STOREI = 3;
///
// EXEC memory address logic
///
reg [31:0] exec_ram_addr_b;
wire [31:0] exec_ram_addr_b_next;
reg [31:0] exec_ram_data_out_b;
wire [31:0] exec_ram_data_out_b_next;
reg exec_ram_we_out;
wire exec_ram_we_out_next;
// Mem queue:
reg [31:0] mem_queue_addr_1;
reg [31:0] mem_queue_data_1;
reg mem_queue_we_1;
reg [31:0] mem_queue_addr_2;
reg [31:0] mem_queue_data_2;
reg mem_queue_we_2;
reg [31:0] mem_queue_addr_3;
reg [31:0] mem_queue_data_3;
reg mem_queue_we_3;
wire [31:0] mem_queue_addr_0;
wire [31:0] mem_queue_data_0;
wire mem_queue_we_0;
assign mem_queue_addr_0 = exec_ram_addr_b;
assign mem_queue_data_0 = exec_ram_data_out_b;
assign mem_queue_we_0 = exec_ram_we_out;
assign ram_addr_in_b = exec_ram_addr_b;
assign ram_data_out_b = exec_ram_data_out_b;
assign ram_we_out = exec_ram_we_out;
wire [31:0] exec_simmed17;
assign exec_simmed17 = {{15{exec_Instr[31]}},exec_Instr[31:15]};
wire exec_isstore;
assign exec_isstore = exec_Instr[3];
assign exec_ram_addr_b_next
=
exec_typem?
((exec_opcode_typeM == OPC_STOREI)?exec_arg2:
(exec_arg2 + exec_simmed17)):0; // both LOAD and STORE
assign exec_ram_we_out_next = exec_typem&(exec_isstore);
assign exec_ram_data_out_b_next = exec_arg1;
reg [31:0] mem_out_alu_r;
reg [31:0] mem_out_s1_r;
reg [31:0] mem_immed_signext_r;
reg [31:0] mem_Instr;
reg [31:0] mem_PC;
wire [31:0] exec_simmed24;
assign exec_simmed24 = {{8{exec_Instr[31]}},exec_Instr[31:8]};
assign exec_branch_override2 = exec_typeb2;
assign exec_PC_next = (exec_Instr[2:1] == 2'b01 )?
(exec_arg1[0]?(exec_PC + exec_simmed24):(fetch_PC + 1)):
(exec_arg1[0]?(exec_arg2):(fetch_PC + 1));
reg [4:0] mem_sd_class;
wire [4:0] mem_sd_class_next;
assign mem_sd_class_next[0] = exec_typei;
assign mem_sd_class_next[1] = exec_ext_hasout;
assign mem_sd_class_next[2] = (exec_typem&(exec_opcode_typeM==3));
assign mem_sd_class_next[3] = exec_typea & (exec_opcode_typeA == OPC_ADD);
assign mem_sd_class_next[4] = exec_typem && (exec_opcode_typeM == 0); // LOAD
`ifdef ENABLE_EXT
`IPATH(c2_custom_hoist.v)
`endif
reg [3:0] sfsm_state;
localparam S_IDLE = 0;
localparam S_WAIT = 1;
localparam DONE = 1;
reg ext_done;
reg stall_exec_r;
assign stall_exec = (exec_typee && exec_immed10[0] && ~ext_done) || (sfsm_state == S_WAIT);
reg [31:0] mem_out_ext_r;
always @(posedge clk)
if (~rst) begin
mem_out_alu_r <= 0;
mem_out_s1_r <= 0;
mem_Instr <= 0;
mem_PC <= 0;
mem_typee <= 0; mem_typei <= 0; mem_typem <= 0; mem_typea <= 0;
mem_sd_class <= 0;
exec_ram_addr_b <= 0;
exec_ram_data_out_b <= 0;
exec_ram_we_out <= 0;
ext_done <= 0;
sfsm_state <= S_IDLE;
stall_exec_r <= 0;
mem_out_ext_r <= 0;
`ifdef ENABLE_EXT
`IPATH(c2_custom_reset.v)
`endif
end else begin
mem_out_alu_r <= stall?mem_out_alu_r:((exec_typei)?exec_immed25_signext:exec_out_next_alu);
mem_out_s1_r <= stall?mem_out_s1_r:(exec_arg2+exec_simmed17);
mem_immed_signext_r <= stall?mem_immed_signext_r:exec_immed_signext;
mem_Instr <= stall?mem_Instr:exec_Instr;
mem_PC <= stall?mem_PC:exec_PC;
mem_typee <= stall?mem_typee:exec_typee;
mem_typei <= stall?mem_typei:exec_typei;
mem_typem <= stall?mem_typem:exec_typem;
mem_typea <= stall?mem_typea:exec_typea;
mem_sd_class <= stall?mem_sd_class:mem_sd_class_next;
//
exec_ram_addr_b <= exec_ram_addr_b_next;
exec_ram_data_out_b <= exec_ram_data_out_b_next;
exec_ram_we_out <= exec_ram_we_out_next;
`ifndef DISABLE_MEMQUEUE
if (~stall) begin
mem_queue_addr_1 <= exec_ram_addr_b;
mem_queue_we_1 <= exec_ram_we_out;
mem_queue_data_1 <= exec_ram_data_out_b;
mem_queue_addr_2 <= mem_queue_addr_1;
mem_queue_we_2 <= mem_queue_we_1;
mem_queue_data_2 <= mem_queue_data_1;
mem_queue_addr_3 <= mem_queue_addr_2;
mem_queue_we_3 <= mem_queue_we_2;
mem_queue_data_3 <= mem_queue_data_2;
end // if (~stall)
`endif
`ifdef ENABLE_EXT
`IPATH(c2_custom_pipeline.v)
`endif
// Ext. FSM for the multi-cycle instructions (i.e., those with a wait stage)
`ifdef ENABLE_LONG_EXT
stall_exec_r <= stall_exec;
case (sfsm_state)
S_IDLE:
begin
ext_done <= 0;
if (exec_typee && exec_immed10[0] && ~stall_but_ext && ~ext_done) begin
sfsm_state <= S_WAIT;
end
end
S_WAIT:
begin
`IPATH(c2_custom_wait.v)
end
endcase
`endif
end
//------------------------------------------------
//--6. MEM logic----------------------------------
//------------------------------------------------
wire [31:0] mem_out_next;
wire [31:0] mem_out_simple_next;
wire mem_ext_hasout;
assign mem_ext_hasout = mem_typee;
wire [1:0] mem_opcode_typeM;
assign mem_opcode_typeM = mem_Instr[4:3];
wire [3:0] mem_opcode_typeA;
assign mem_opcode_typeA = mem_Instr[6:3];
wire [31:0] mem_ram_input;
`ifndef DISABLE_MEMQUEUE
assign mem_ram_input = ((mem_queue_addr_0 == mem_queue_addr_1)&mem_queue_we_1)?mem_queue_data_1:
((mem_queue_addr_0 == mem_queue_addr_2)&mem_queue_we_2)?mem_queue_data_2:
((mem_queue_addr_0 == mem_queue_addr_3)&mem_queue_we_3)?mem_queue_data_3:ram_data_in_b;
`else
assign mem_ram_input = ram_data_in_b;
`endif
// Selecting the right EXEC / RAM output
assign mem_out_next =
mem_sd_class==1?mem_out_alu_r:
mem_sd_class==2?mem_out_ext_r:
mem_sd_class==4?mem_out_s1_r:
mem_sd_class==8?(mem_out_alu_r + mem_immed_signext_r):
mem_out_alu_r;
// Same but without an addition and mem output, to shorten the forwarding critical path
assign mem_out_simple_next =
mem_sd_class==1?mem_out_alu_r:
mem_sd_class==2?mem_out_ext_r:
mem_sd_class==4?mem_out_s1_r:
mem_out_alu_r;
wire mem_out_we_next;
assign mem_out_we_next = mem_typei |
(mem_typea && (mem_opcode_typeA!=0)) |
(mem_typem && (mem_opcode_typeM == 3));
wire mem_out_we_delayed_next;
assign mem_out_we_delayed_next = mem_out_we_next | (mem_typem && (mem_opcode_typeM != 1));
wire [4:0] mem_out_reg_next;
assign mem_out_reg_next =
mem_typea?mem_Instr[11:7]:
(mem_typei?mem_Instr[6:2]:
((mem_typem&(mem_Instr[3]==0))?
mem_Instr[9:5]:
(mem_typem&(mem_opcode_typeM==3))?mem_Instr[14:10]:
mem_Instr[19:15]));
// A simple MEM->EXEC forwarding feedback
assign fwd_simple = mem_out_we_next;
assign fwd_simple_data = mem_out_simple_next;
assign fwd_simple_reg = mem_out_reg_next;
/////
reg [31:0] wb_Instr;
reg [31:0] wb_PC;
reg [31:0] mem_out;
reg mem_out_we;
reg mem_out_we_delayed;
reg [4:0] mem_out_reg;
reg wb_readmem;
assign fwd_mem = mem_out_we;
assign fwd_mem_reg = mem_out_reg;
assign fwd_mem_data = mem_out;
always @(posedge clk)
if (~rst) begin
wb_Instr <= 0;
wb_PC <= 0;
mem_out <= 0;
mem_out_we <= 0;
mem_out_we_delayed <= 0;
mem_out_reg <= 0;
wb_readmem <= 0;
end else begin
wb_Instr <= stall?wb_Instr:mem_Instr;
wb_PC <= stall?wb_PC:mem_PC;
mem_out <= stall?mem_out:mem_out_next;
mem_out_we <= stall?mem_out_we:mem_out_we_next;
mem_out_we_delayed <= stall?mem_out_we_delayed:mem_out_we_delayed_next;
mem_out_reg <= stall?mem_out_reg:mem_out_reg_next;
wb_readmem <= stall?wb_readmem:(mem_sd_class==16);
end // else: !if(~rst)
//------------------------------------------------
//--7. WB logic-----------------------------------
//------------------------------------------------
reg [31:0] wb_out;
reg wb_out_we;
reg [4:0] wb_out_reg;
wire [31:0] wb_ram_input;
`ifndef DISABLE_MEMQUEUE
assign wb_ram_input = ((mem_queue_addr_0 == mem_queue_addr_1)&mem_queue_we_1)?mem_queue_data_1:
((mem_queue_addr_0 == mem_queue_addr_2)&mem_queue_we_2)?mem_queue_data_2:
((mem_queue_addr_0 == mem_queue_addr_3)&mem_queue_we_3)?mem_queue_data_3:ram_data_in_b;
`else
assign wb_ram_input = ram_data_in_b;
`endif
wire [31:0] wb_out_next;
wire wb_out_we_next;
assign wb_out_next = wb_readmem?wb_ram_input:mem_out;
assign wb_out_we_next = mem_out_we_delayed;
assign fwd_wb = wb_out_we;
assign fwd_wb_reg = wb_out_reg;
assign fwd_wb_data = wb_out;
always @(posedge clk)
if (~rst) begin
wb_out <= 0;
wb_out_we <= 0;
wb_out_reg <= 0;
end else begin
wb_out <= stall?wb_out:wb_out_next;
wb_out_we <= stall?wb_out_we:wb_out_we_next;
wb_out_reg <= stall?wb_out_reg:mem_out_reg;
end
//------------------------------------------------
//--8. Reg file instance--------------------------
//------------------------------------------------
// Address values for the reg file are formed in the DECODE0 stage (or after DECODE0 stage if
// REGFILE_REGISTERED_OUT is not set).
// The output is ready in the DECODE stage (and quite late in it).
// Input port address, data and WE are formed in the end of WB stage
wire [4:0] dbgreg;
wire dbgreg_en;
assign dbgreg_en = 0;
regfile #(
`ifndef DISABLE_MICROOPS
.MICROOPS_ENABLED(1)
`else
.MICROOPS_ENABLED(0)
`endif
) regfile1
(.clk(clk),
.rst(rst),
.PC(fetch_PC), // PC value to be fed as a virtual register R31
`ifdef REGFILE_REGISTERED_OUT
.addr1(decode0_reg1addr_next1),
.addr2(decode0_reg2addr_next1),
`else
.addr1(decode_reg1addr),
.addr2(decode_reg2addr),
`endif
.out1(decode_arg1_out),
.out2(decode_arg2_out),
.dbgreg(dbgreg),
.dbgreg_en(dbgreg_en),
.wdata(wb_out),
.addrw(wb_out_reg),
.we(wb_out_we),
.clkcounter(clkcounter) // for debugging only
);
//------------------------------------------------
//-- 9. Debugging output--------------------------
//------------------------------------------------
`ifdef DEBUG
always @(posedge clk)
if (rst) begin
$display("");
$display("----------------------------------------------------");
$display("CLK %0d", clkcounter);
$display("IF PC=%0d", fetch_PC_next);
$display("DECODE0 PC=%0d \t INSN=%x", decode0_PC, decode0_Instr);
$display(" ARG1(R%0d) \t ARG2(R%0d)", decode0_reg1addr_next,
decode0_reg2addr_next);
$display("DECODE PC=%0d \t INSN=%x", decode_PC, decode_Instr);
/*
$display(" ARG1(R%0d) = %0d \t ARG2(R%0d) = %0d", decode_reg1addr,
decode_arg1_next,
decode_reg2addr, decode_arg2_next);
if (fwd_mem) $display(" MEM FWD: R%0d = %d", fwd_mem_reg, fwd_mem_data);
if (fwd_wb) $display(" WB FWD: R%0d = %d", fwd_wb_reg, fwd_wb_data);
*/
$display("EXEC PC=%0d \t INSN=%x", exec_PC, exec_Instr);
$display(" ARG1(R%0d)=%0d \t ARG2(R%0d)=%0d", exec_reg1addr, exec_arg1, exec_reg2addr, exec_arg2);
`ifdef DEBUGFWD
if (fwd_simple) $display(" SIMPLE FWD: R%0d = %d", fwd_simple_reg, fwd_simple_data);
if (fwd_mem) $display(" MEM FWD: R%0d = %d", fwd_mem_reg, fwd_mem_data);
if (fwd_wb) $display(" WB FWD: R%0d = %d", fwd_wb_reg, fwd_wb_data);
if (exec_isext) $display(" EXT OP");
if (exec_typem) $display(" MEM OP");
if (exec_typei) $display(" IMMED OP");
if (exec_typem & exec_isstore) $display(" STORE OP");
`endif
$display("MEM PC=%0d \t INSN=%x", mem_PC, mem_Instr);
$display("WB PC=%0d \t INSN=%x", wb_PC, wb_Instr);
if(mem_out_we)
$display(" WB: R%0d <= %0d", mem_out_reg, wb_out_next);
end
`endif
endmodule
|
module sky130_fd_sc_hdll__a211oi (
//# {{data|Data Signals}}
input A1,
input A2,
input B1,
input C1,
output Y
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
|
module testbench();
parameter CLK_CYCLE_TIME = 50;
parameter IMEM_INTERVAL = 2000;
parameter SIM_CYCLE = 100000000;
parameter SIM_TIME = SIM_CYCLE * CLK_CYCLE_TIME * 2;
reg [31:0] CLK_CYCLE;
reg clk;
reg reset;
initial begin
clk = 0;
forever #CLK_CYCLE_TIME clk = ~clk;
end
initial begin
reset = 0;
#IMEM_INTERVAL reset = 1;
end
initial begin
CLK_CYCLE = 32'h0;
#IMEM_INTERVAL CLK_CYCLE = 32'h0;
end
always @(posedge clk) begin
CLK_CYCLE <= CLK_CYCLE + 1;
end
/*
initial begin
$dumpfile("wave.vcd");
$dumpvars(0, testbench);
end
*/
initial begin
#IMEM_INTERVAL;
#SIM_TIME;
$finish;
end
top rv(
.clk(clk),
.reset_x(reset)
);
integer fp;
integer temp;
integer i, j;
initial begin
//btb, bia init
for (i = 0; i < `BTB_IDX_NUM ; i = i + 1) begin
rv.pipe.pipe_if.brtbl.bia.mem[i] = 0;
rv.pipe.pipe_if.brtbl.bta.mem[i] = 0;
end
for (i = 0; i < `GSH_PHT_NUM ; i = i + 1) begin
rv.pipe.pipe_if.gsh.prhisttbl.pht0.mem[i] = 2;
rv.pipe.pipe_if.gsh.prhisttbl.pht1.mem[i] = 2;
end
fp = $fopen("../bin/init.bin", "rb");
temp = $fread(rv.instmemory.mem, fp);
fp = $fopen("../bin/init.bin", "rb");
temp = $fread(rv.datamemory.mem, fp);
for (i = 0 ; i < 512 ; i = i + 1) begin
j = rv.instmemory.mem[i][7:0];
rv.instmemory.mem[i][7:0] = rv.instmemory.mem[i][31:24];
rv.instmemory.mem[i][31:24] = j;
j = rv.instmemory.mem[i][15:8];
rv.instmemory.mem[i][15:8] = rv.instmemory.mem[i][23:16];
rv.instmemory.mem[i][23:16] = j;
j = rv.instmemory.mem[i][32+7:0+32];
rv.instmemory.mem[i][32+7:0+32]
= rv.instmemory.mem[i][32+31:24+32];
rv.instmemory.mem[i][32+31:24+32] = j;
j = rv.instmemory.mem[i][32+15:8+32];
rv.instmemory.mem[i][32+15:8+32]
= rv.instmemory.mem[i][32+23:16+32];
rv.instmemory.mem[i][32+23:16+32] = j;
j = rv.instmemory.mem[i][64+7:0+64];
rv.instmemory.mem[i][64+7:0+64]
= rv.instmemory.mem[i][64+31:24+64];
rv.instmemory.mem[i][64+31:24+64] = j;
j = rv.instmemory.mem[i][64+15:8+64];
rv.instmemory.mem[i][64+15:8+64]
= rv.instmemory.mem[i][64+23:16+64];
rv.instmemory.mem[i][64+23:16+64] = j;
j = rv.instmemory.mem[i][96+7:0+96];
rv.instmemory.mem[i][96+7:0+96]
= rv.instmemory.mem[i][96+31:24+96];
rv.instmemory.mem[i][96+31:24+96] = j;
j = rv.instmemory.mem[i][96+15:8+96];
rv.instmemory.mem[i][96+15:8+96]
= rv.instmemory.mem[i][96+23:16+96];
rv.instmemory.mem[i][96+23:16+96] = j;
j = rv.instmemory.mem[i][31:0];
rv.instmemory.mem[i][31:0] = rv.instmemory.mem[i][127:96];
rv.instmemory.mem[i][127:96] = j;
j = rv.instmemory.mem[i][63:32];
rv.instmemory.mem[i][63:32] = rv.instmemory.mem[i][95:64];
rv.instmemory.mem[i][95:64] = j;
end
for (i = 0 ; i < 2048 ; i = i + 1) begin
j = rv.datamemory.mem[i][7:0];
rv.datamemory.mem[i][7:0] = rv.datamemory.mem[i][31:24];
rv.datamemory.mem[i][31:24] = j;
j = rv.datamemory.mem[i][15:8];
rv.datamemory.mem[i][15:8] = rv.datamemory.mem[i][23:16];
rv.datamemory.mem[i][23:16] = j;
end
end
integer prmi, prsu, prnum, prcom;
initial begin
prmi = 0;
prsu = 0;
prnum = 0;
prcom = 0;
end
always @ (posedge clk) begin
if (reset && rv.pipe.prmiss) begin
prmi = prmi + 1;
prnum = prnum + 1;
end
if (reset && rv.pipe.prsuccess) begin
prsu = prsu + 1;
prnum = prnum + 1;
end
if (reset && rv.pipe.combranch) begin
prcom = prcom + 1;
end
end
always @ (posedge clk) begin
//Simulation I/OMAP****************************************************
if (rv.dmem_we && rv.dmem_addr == 32'h0) begin
$write("%c", rv.dmem_wdata[7:0]);
end
if (rv.dmem_we && rv.dmem_addr == 32'h4) begin
$write("%d", rv.dmem_wdata);
end
if (rv.dmem_we && rv.dmem_addr == 32'h8) begin
$write("\n%d clks\n", CLK_CYCLE);
/*
$write("stall: %d stall_by_LDST: %d\n", stall, stall_ldst);
$write("stall_by_branch: %d stall_by_prsuccess: %d",
stall_branch, stall_prsuccess);
*/
$write("prnum: %d, prsuccess: %d, prmiss: %d\n (prcom: %d)\n", prnum, prsu, prmi, prcom);
$finish;
end
end // always @ (posedge clk)
endmodule
|
module fifo_83x256 (
clock,
data,
rdreq,
wrreq,
empty,
full,
q,
usedw);
input clock;
input [82:0] data;
input rdreq;
input wrreq;
output empty;
output full;
output [82:0] q;
output [7:0] usedw;
wire [7:0] sub_wire0;
wire sub_wire1;
wire [82:0] sub_wire2;
wire sub_wire3;
wire [7:0] usedw = sub_wire0[7:0];
wire empty = sub_wire1;
wire [82:0] q = sub_wire2[82:0];
wire full = sub_wire3;
scfifo scfifo_component (
.rdreq (rdreq),
.clock (clock),
.wrreq (wrreq),
.data (data),
.usedw (sub_wire0),
.empty (sub_wire1),
.q (sub_wire2),
.full (sub_wire3)
// synopsys translate_off
,
.aclr (),
.almost_empty (),
.almost_full (),
.sclr ()
// synopsys translate_on
);
defparam
scfifo_component.add_ram_output_register = "OFF",
scfifo_component.intended_device_family = "Cyclone III",
scfifo_component.lpm_hint = "RAM_BLOCK_TYPE=M9K",
scfifo_component.lpm_numwords = 256,
scfifo_component.lpm_showahead = "OFF",
scfifo_component.lpm_type = "scfifo",
scfifo_component.lpm_width = 83,
scfifo_component.lpm_widthu = 8,
scfifo_component.overflow_checking = "OFF",
scfifo_component.underflow_checking = "OFF",
scfifo_component.use_eab = "ON";
endmodule
|
module top;
parameter length = 34;
parameter str = "%s";
reg [length*8-1:0] result, fmt;
integer val = 1000;
reg [31:0] eval, uval, zval;
reg [63:0] hval, sval;
real rval = 1234.567;
wire net;
time tm = 234567;
realtime rtm = 2345.678;
reg failed;
`ifdef DEBUG
integer lp;
`endif
assign (pull1, strong0) net = 1'b1;
task check_result;
input [length*8-1:0] result, value;
input [80*8-1:0] message;
if (result != value) begin
$display("%0s", message);
$display("Got :%s:", result);
$display("Wanted :%s:", value);
`ifdef DEBUG
for (lp=0; lp<length; lp=lp+1) begin
$display("%d - %d, %d", lp, result[lp*8 +: 8], value[lp*8 +: 8]);
end
`endif
failed = 1;
end
endtask
initial begin
$timeformat(-12, 4, " ps", 20);
fmt = "%s";
failed = 0;
// Determine the endian order.
$swrite(result, "%u", "Help");
if (result != "\000Help") begin
// Big endian so reverse the bytes.
eval = 32'h22000000;
hval = 64'h206d652148656c70;
uval = 32'b010010xz_01100101_01101100_01110000;
zval = 32'b01z01000_0xx0zx0x_0xx01x0z_01x1000z;
sval = " me!Help";
end else begin
// Little endian.
eval = 32'h00000022;
hval = 64'h21656d20706c6548;
uval = 32'b01110000_01101100_01100101_010010xz;
zval = 32'b01x1000z_0xx01x0z_0xx0zx0x_01z01000;
sval = "!em pleH";
end
#1;
// Basic variables and functions.
$swrite(result, val);
check_result(result, " 1000", "Decimal in $swrite failed!");
$swriteb(result, val);
check_result(result, "00000000000000000000001111101000",
"Decimal in $swriteb failed!");
$swriteo(result, val);
check_result(result, "00000001750", "Decimal in $swriteo failed!");
$swriteh(result, val);
check_result(result, "000003e8", "Decimal in $swriteo failed!");
$swrite(result, rval);
check_result(result, "1234.57", "Real in $swrite failed!");
$swrite(result, "Normal string.");
check_result(result, "Normal string.", "String in $swrite failed!");
$swrite(result, tm);
check_result(result, " 234567", "Time in $swrite failed!");
$swrite(result, rtm);
check_result(result, "2345.68", "Real time in $swrite failed!");
$swrite(result, $time);
check_result(result, " 1", "$time in $swrite failed!");
$swrite(result, $stime);
check_result(result, " 1", "$stime in $swrite failed!");
$swrite(result, $simtime);
check_result(result, " 1000", "$simtime in $swrite failed!");
$swrite(result, $realtime);
check_result(result, "1.000", "$realtime in $swrite failed!");
// %% and extra variables.
$swrite(result, "%%",, val);
check_result(result, "% 1000", "% and value in $swrite failed!");
// %b
$swrite(result, "%b", net);
check_result(result, "1", "%b in $swrite failed!");
$swrite(result, "%B", net);
check_result(result, "1", "%b in $swrite failed!");
$swrite(result, "%b", 8'b00001001);
check_result(result, "00001001", "%b in $swrite failed!");
$swrite(result, "%0b", 8'b00001001);
check_result(result, "1001", "%0b in $swrite failed!");
$swrite(result, "%14b", 8'b00001001);
check_result(result, " 00001001", "%14b in $swrite failed!");
$swrite(result, "%-14b", 8'b00001001);
check_result(result, "00001001 ", "%-14b in $swrite failed!");
// %o
$swrite(result, "%o", 8'b00001001);
check_result(result, "011", "%o in $swrite failed!");
$swrite(result, "%O", 8'b00001001);
check_result(result, "011", "%O in $swrite failed!");
$swrite(result, "%0o", 8'b00001001);
check_result(result, "11", "%0o in $swrite failed!");
$swrite(result, "%14o", 8'b00001001);
check_result(result, " 011", "%14o in $swrite failed!");
$swrite(result, "%-14o", 8'b00001001);
check_result(result, "011 ", "%-14o in $swrite failed!");
// %h
$swrite(result, "%h", 8'b00001001);
check_result(result, "09", "%h in $swrite failed!");
$swrite(result, "%H", 8'b00001001);
check_result(result, "09", "%H in $swrite failed!");
$swrite(result, "%0h", 8'b00001001);
check_result(result, "9", "%0h in $swrite failed!");
$swrite(result, "%14h", 8'b00001001);
check_result(result, " 09", "%14h in $swrite failed!");
$swrite(result, "%-14h", 8'b00001001);
check_result(result, "09 ", "%-14h in $swrite failed!");
// %c
$swrite(result, "%c", "abcd");
check_result(result, "d", "%c in $swrite failed!");
$swrite(result, "%C", "abcd");
check_result(result, "d", "%C in $swrite failed!");
$swrite(result, "%4c", "abcd");
check_result(result, " d", "%4c in $swrite failed!");
$swrite(result, "%-4c", "abcd");
check_result(result, "d ", "%-4c in $swrite failed!");
// %d
$swrite(result, "%d", val);
check_result(result, " 1000", "%d in $swrite failed!");
$swrite(result, "%D", val);
check_result(result, " 1000", "%D in $swrite failed!");
$swrite(result, "%d", length);
`ifdef __ICARUS_UNSIZED__
check_result(result, " 34", "%d in $swrite failed!");
`else
check_result(result, " 34", "%d in $swrite failed!");
`endif
$swrite(result, "%d", 31);
`ifdef __ICARUS_UNSIZED__
check_result(result, " 31", "%d in $swrite failed!");
`else
check_result(result, " 31", "%d in $swrite failed!");
`endif
$swrite(result, "%d", $unsigned(31));
`ifdef __ICARUS_UNSIZED__
check_result(result, "31", "%d in $swrite failed!");
`else
check_result(result, " 31", "%d in $swrite failed!");
`endif
$swrite(result, "%0d", val);
check_result(result, "1000", "%0d in $swrite failed!");
$swrite(result, "%+d", val);
check_result(result, " +1000", "%+d in $swrite failed!");
$swrite(result, "%14d", val);
check_result(result, " 1000", "%14d in $swrite failed!");
$swrite(result, "%-14d", val);
check_result(result, "1000 ", "%-14d in $swrite failed!");
// %e
$swrite(result, "%e", rval);
check_result(result, "1.234567e+03", "%e in $swrite failed!");
$swrite(result, "%E", rval);
check_result(result, "1.234567E+03", "%E in $swrite failed!");
$swrite(result, "%+e", rval);
check_result(result, "+1.234567e+03", "%+e in $swrite failed!");
$swrite(result, "%14.3e", rval);
check_result(result, " 1.235e+03", "%14.3e in $swrite failed!");
$swrite(result, "%-14.3e", rval);
check_result(result, "1.235e+03 ", "%-14.3e in $swrite failed!");
// %f
$swrite(result, "%f", rval);
check_result(result, "1234.567000", "%f in $swrite failed!");
$swrite(result, "%F", rval);
check_result(result, "1234.567000", "%F in $swrite failed!");
$swrite(result, "%+f", rval);
check_result(result, "+1234.567000", "%+f in $swrite failed!");
$swrite(result, "%14.3f", rval);
check_result(result, " 1234.567", "%14.3f in $swrite failed!");
$swrite(result, "%-14.3f", rval);
check_result(result, "1234.567 ", "%-14.3f in $swrite failed!");
// %g
$swrite(result, "%g", rval);
check_result(result, "1234.57", "%g in $swrite failed!");
$swrite(result, "%G", rval);
check_result(result, "1234.57", "%G in $swrite failed!");
$swrite(result, "%+g", rval);
check_result(result, "+1234.57", "%+g in $swrite failed!");
$swrite(result, "%14.3g", rval);
check_result(result, " 1.23e+03", "%14.3g in $swrite failed!");
$swrite(result, "%-14.3G", rval);
check_result(result, "1.23E+03 ", "%-14.3G in $swrite failed!");
// %l is currently unsupported.
$swrite(result, "%l");
check_result(result, "<%l>", "%l in $swrite failed!");
$swrite(result, "%L");
check_result(result, "<%L>", "%L in $swrite failed!");
// %m
$swrite(result, "%m");
check_result(result, "top", "%m in $swrite failed!");
$swrite(result, "%M");
check_result(result, "top", "%M in $swrite failed!");
$swrite(result, "%8m");
check_result(result, " top", "%m in $swrite failed!");
$swrite(result, "%-8m");
check_result(result, "top ", "%m in $swrite failed!");
// %s
$swrite(result, "%s", "Hello");
check_result(result, "Hello", "%s in $swrite failed!");
$swrite(result, "%S", "Hello");
check_result(result, "Hello", "%S in $swrite failed!");
$swrite(result, str, "Hello");
check_result(result, "Hello", "%s in $swrite failed!");
$swrite(result, "%14s", "Hello");
check_result(result, " Hello", "%14s in $swrite failed!");
$swrite(result, "%-14s", "Hello");
check_result(result, "Hello ", "%-14s in $swrite failed!");
// %t
$swrite(result, "%t", 0);
check_result(result, " 0.0000 ps", "%t in $swrite failed!");
$swrite(result, "%t", 1);
check_result(result, " 1000.0000 ps", "%t in $swrite failed!");
$swrite(result, "%T", 1);
check_result(result, " 1000.0000 ps", "%T in $swrite failed!");
$swrite(result, "%t", 10_000);
check_result(result, " 10000000.0000 ps", "%t in $swrite failed!");
$swrite(result, "%t", $time);
check_result(result, " 1000.0000 ps", "%t $time in $swrite failed!");
// $swrite(result, "%t", $simtime);
// check_result(result, " 1000.0000 ps",
// "%t $simtime in $swrite failed!");
$swrite(result, "%-t", 1);
check_result(result, "1000.0000 ps ", "%-t in $swrite failed!");
$swrite(result, "%15t", 1);
check_result(result, " 1000.0000 ps", "%15t in $swrite failed!");
$swrite(result, "%-15t", 1);
check_result(result, "1000.0000 ps ", "%-15t in $swrite failed!");
$swrite(result, "%15.1t", 1);
check_result(result, " 1000.0 ps", "%15.1t in $swrite failed!");
// Real values.
$swrite(result, "%t", 1.1);
check_result(result, " 1100.0000 ps", "%t in $swrite failed!");
$swrite(result, "%t", $realtime);
check_result(result, " 1000.0000 ps",
"%t $realtime in $swrite failed!");
$swrite(result, "%-t", 1.1);
check_result(result, "1100.0000 ps ", "%-t in $swrite failed!");
$swrite(result, "%15t", 1.1);
check_result(result, " 1100.0000 ps", "%15t in $swrite failed!");
$swrite(result, "%-15t", 1.1);
check_result(result, "1100.0000 ps ", "%-15t in $swrite failed!");
$swrite(result, "%15.1t", 1.1);
check_result(result, " 1100.0 ps", "%15.1t in $swrite failed!");
// %u
$swrite(result, "%u", eval);
check_result(result, "\"", "%u in $swrite failed!");
$swrite(result, "%U", eval);
check_result(result, "\"", "%U in $swrite failed!");
$swrite(result, "%u", sval);
check_result(result, "Help me!", "%u in $swrite failed!");
// "Help me!"
$swrite(result, "%u", hval);
check_result(result, "Help me!", "%u in $swrite failed!");
// "Help" with check for correct x and z functionality.
$swrite(result, "%u", uval);
check_result(result, "Help", "%u in $swrite failed!");
// %v
$swrite(result, "%v", net);
check_result(result, "Pu1", "%v in $swrite failed!");
$swrite(result, "%V", net);
check_result(result, "Pu1", "%V in $swrite failed!");
$swrite(result, "%14v", net);
check_result(result, " Pu1", "%14v in $swrite failed!");
$swrite(result, "%-14v", net);
check_result(result, "Pu1 ", "%-14v in $swrite failed!");
// %z
$swrite(result, "%z", eval);
check_result(result, "\"", "%z in $swrite failed!");
$swrite(result, "%Z", eval);
check_result(result, "\"", "%Z in $swrite failed!");
// "Help me!", but because of NULLs we only get "Help"
$swrite(result, "%z", hval);
check_result(result, "Help", "%z in $swrite failed!");
// "Help me!" encoded using all the states!
$swrite(result, "%z", zval);
check_result(result, "Help me!", "%z in $swrite failed!");
// $sformat()
$sformat(result, "%s", "Hello world");
check_result(result, "Hello world", "String in $sformat failed!");
$sformat(result, str, "Hello world");
check_result(result, "Hello world", "Parameter in $sformat failed!");
$sformat(result, fmt, "Hello world");
check_result(result, "Hello world", "Register in $sformat failed!");
$sformat(result, "%s");
check_result(result, "<%s>", "$sformat missing argument failed!");
$sformat(result, "%s", "Hello world", 2);
check_result(result, "Hello world", "$sformat extra argument failed!");
if (!failed) $display("All tests passed.");
end
endmodule
|
module TimeHoldOver_Qsys_onchip_memory2_0 (
// inputs:
address,
byteenable,
chipselect,
clk,
clken,
reset,
reset_req,
write,
writedata,
// outputs:
readdata
)
;
parameter INIT_FILE = "TimeHoldOver_Qsys_onchip_memory2_0.hex";
output [ 31: 0] readdata;
input [ 11: 0] address;
input [ 3: 0] byteenable;
input chipselect;
input clk;
input clken;
input reset;
input reset_req;
input write;
input [ 31: 0] writedata;
wire clocken0;
wire [ 31: 0] readdata;
wire wren;
assign wren = chipselect & write;
assign clocken0 = clken & ~reset_req;
altsyncram the_altsyncram
(
.address_a (address),
.byteena_a (byteenable),
.clock0 (clk),
.clocken0 (clocken0),
.data_a (writedata),
.q_a (readdata),
.wren_a (wren)
);
defparam the_altsyncram.byte_size = 8,
the_altsyncram.init_file = INIT_FILE,
the_altsyncram.lpm_type = "altsyncram",
the_altsyncram.maximum_depth = 2560,
the_altsyncram.numwords_a = 2560,
the_altsyncram.operation_mode = "SINGLE_PORT",
the_altsyncram.outdata_reg_a = "UNREGISTERED",
the_altsyncram.ram_block_type = "M9K",
the_altsyncram.read_during_write_mode_mixed_ports = "DONT_CARE",
the_altsyncram.width_a = 32,
the_altsyncram.width_byteena_a = 4,
the_altsyncram.widthad_a = 12;
//s1, which is an e_avalon_slave
//s2, which is an e_avalon_slave
endmodule
|
module hpdmc #(
parameter csr_addr = 4'h0,
/*
* The depth of the SDRAM array, in bytes.
* Capacity (in bytes) is 2^sdram_depth.
*/
parameter sdram_depth = 26,
/*
* The number of column address bits of the SDRAM.
*/
parameter sdram_columndepth = 9
) (
input sys_clk,
input sys_clk_n,
/*
* Clock used to generate DQS.
* Typically sys_clk phased out by 90 degrees,
* as data is sent synchronously to sys_clk.
*/
input dqs_clk,
input dqs_clk_n,
input sys_rst,
/* Control interface */
input [13:0] csr_a,
input csr_we,
input [31:0] csr_di,
output [31:0] csr_do,
/* Simple FML 4x64 interface to the memory contents */
input [sdram_depth-1:0] fml_adr,
input fml_stb,
input fml_we,
output fml_ack,
input [7:0] fml_sel,
input [63:0] fml_di,
output [63:0] fml_do,
/* SDRAM interface.
* The SDRAM clock should be driven synchronously to the system clock.
* It is not generated inside this core so you can take advantage of
* architecture-dependent clocking resources to generate a clean
* differential clock.
*/
output reg sdram_cke,
output reg sdram_cs_n,
output reg sdram_we_n,
output reg sdram_cas_n,
output reg sdram_ras_n,
output reg [12:0] sdram_adr,
output reg [1:0] sdram_ba,
output [3:0] sdram_dqm,
inout [31:0] sdram_dq,
inout [3:0] sdram_dqs,
/* Interface to the DCM generating DQS */
output dqs_psen,
output dqs_psincdec,
input dqs_psdone,
input [1:0] pll_stat
);
/* Register all control signals, leaving the possibility to use IOB registers */
wire sdram_cke_r;
wire sdram_cs_n_r;
wire sdram_we_n_r;
wire sdram_cas_n_r;
wire sdram_ras_n_r;
wire [12:0] sdram_adr_r;
wire [1:0] sdram_ba_r;
always @(posedge sys_clk) begin
sdram_cke <= sdram_cke_r;
sdram_cs_n <= sdram_cs_n_r;
sdram_we_n <= sdram_we_n_r;
sdram_cas_n <= sdram_cas_n_r;
sdram_ras_n <= sdram_ras_n_r;
sdram_ba <= sdram_ba_r;
sdram_adr <= sdram_adr_r;
end
/* Mux the control signals according to the "bypass" selection.
* CKE always comes from the control interface.
*/
wire bypass;
wire sdram_cs_n_bypass;
wire sdram_we_n_bypass;
wire sdram_cas_n_bypass;
wire sdram_ras_n_bypass;
wire [12:0] sdram_adr_bypass;
wire [1:0] sdram_ba_bypass;
wire sdram_cs_n_mgmt;
wire sdram_we_n_mgmt;
wire sdram_cas_n_mgmt;
wire sdram_ras_n_mgmt;
wire [12:0] sdram_adr_mgmt;
wire [1:0] sdram_ba_mgmt;
assign sdram_cs_n_r = bypass ? sdram_cs_n_bypass : sdram_cs_n_mgmt;
assign sdram_we_n_r = bypass ? sdram_we_n_bypass : sdram_we_n_mgmt;
assign sdram_cas_n_r = bypass ? sdram_cas_n_bypass : sdram_cas_n_mgmt;
assign sdram_ras_n_r = bypass ? sdram_ras_n_bypass : sdram_ras_n_mgmt;
assign sdram_adr_r = bypass ? sdram_adr_bypass : sdram_adr_mgmt;
assign sdram_ba_r = bypass ? sdram_ba_bypass : sdram_ba_mgmt;
/* Control interface */
wire sdram_rst;
wire [2:0] tim_rp;
wire [2:0] tim_rcd;
wire tim_cas;
wire [10:0] tim_refi;
wire [3:0] tim_rfc;
wire [1:0] tim_wr;
wire idelay_rst;
wire idelay_ce;
wire idelay_inc;
hpdmc_ctlif #(
.csr_addr(csr_addr)
) ctlif (
.sys_clk(sys_clk),
.sys_rst(sys_rst),
.csr_a(csr_a),
.csr_we(csr_we),
.csr_di(csr_di),
.csr_do(csr_do),
.bypass(bypass),
.sdram_rst(sdram_rst),
.sdram_cke(sdram_cke_r),
.sdram_cs_n(sdram_cs_n_bypass),
.sdram_we_n(sdram_we_n_bypass),
.sdram_cas_n(sdram_cas_n_bypass),
.sdram_ras_n(sdram_ras_n_bypass),
.sdram_adr(sdram_adr_bypass),
.sdram_ba(sdram_ba_bypass),
.tim_rp(tim_rp),
.tim_rcd(tim_rcd),
.tim_cas(tim_cas),
.tim_refi(tim_refi),
.tim_rfc(tim_rfc),
.tim_wr(tim_wr),
.idelay_rst(idelay_rst),
.idelay_ce(idelay_ce),
.idelay_inc(idelay_inc),
.dqs_psen(dqs_psen),
.dqs_psincdec(dqs_psincdec),
.dqs_psdone(dqs_psdone),
.pll_stat(pll_stat)
);
/* SDRAM management unit */
wire mgmt_stb;
wire mgmt_we;
wire [sdram_depth-3-1:0] mgmt_address;
wire mgmt_ack;
wire read;
wire write;
wire [3:0] concerned_bank;
wire read_safe;
wire write_safe;
wire [3:0] precharge_safe;
hpdmc_mgmt #(
.sdram_depth(sdram_depth),
.sdram_columndepth(sdram_columndepth)
) mgmt (
.sys_clk(sys_clk),
.sdram_rst(sdram_rst),
.tim_rp(tim_rp),
.tim_rcd(tim_rcd),
.tim_refi(tim_refi),
.tim_rfc(tim_rfc),
.stb(mgmt_stb),
.we(mgmt_we),
.address(mgmt_address),
.ack(mgmt_ack),
.read(read),
.write(write),
.concerned_bank(concerned_bank),
.read_safe(read_safe),
.write_safe(write_safe),
.precharge_safe(precharge_safe),
.sdram_cs_n(sdram_cs_n_mgmt),
.sdram_we_n(sdram_we_n_mgmt),
.sdram_cas_n(sdram_cas_n_mgmt),
.sdram_ras_n(sdram_ras_n_mgmt),
.sdram_adr(sdram_adr_mgmt),
.sdram_ba(sdram_ba_mgmt)
);
/* Bus interface */
wire data_ack;
hpdmc_busif #(
.sdram_depth(sdram_depth)
) busif (
.sys_clk(sys_clk),
.sdram_rst(sdram_rst),
.fml_adr(fml_adr),
.fml_stb(fml_stb),
.fml_we(fml_we),
.fml_ack(fml_ack),
.mgmt_stb(mgmt_stb),
.mgmt_we(mgmt_we),
.mgmt_address(mgmt_address),
.mgmt_ack(mgmt_ack),
.data_ack(data_ack)
);
/* Data path controller */
wire direction;
wire direction_r;
hpdmc_datactl datactl(
.sys_clk(sys_clk),
.sdram_rst(sdram_rst),
.read(read),
.write(write),
.concerned_bank(concerned_bank),
.read_safe(read_safe),
.write_safe(write_safe),
.precharge_safe(precharge_safe),
.ack(data_ack),
.direction(direction),
.direction_r(direction_r),
.tim_cas(tim_cas),
.tim_wr(tim_wr)
);
/* Data path */
hpdmc_ddrio ddrio(
.sys_clk(sys_clk),
.sys_clk_n(sys_clk_n),
.dqs_clk(dqs_clk),
.dqs_clk_n(dqs_clk_n),
.direction(direction),
.direction_r(direction_r),
/* Bit meaning is the opposite between
* the FML selection signal and SDRAM DQM pins.
*/
.mo(~fml_sel),
.do(fml_di),
.di(fml_do),
.sdram_dqm(sdram_dqm),
.sdram_dq(sdram_dq),
.sdram_dqs(sdram_dqs),
.idelay_rst(idelay_rst),
.idelay_ce(idelay_ce),
.idelay_inc(idelay_inc)
);
endmodule
|
module header
// Internal signals
//
// Generated Signal List
//
//
// End of Generated Signal List
//
// %COMPILER_OPTS%
//
// Generated Signal Assignments
//
//
// Generated Instances and Port Mappings
//
endmodule
|
module pcie_7x_v1_11_0_axi_basic_rx_pipeline #(
parameter C_DATA_WIDTH = 128, // RX/TX interface data width
parameter C_FAMILY = "X7", // Targeted FPGA family
parameter TCQ = 1, // Clock to Q time
// Do not override parameters below this line
parameter REM_WIDTH = (C_DATA_WIDTH == 128) ? 2 : 1, // trem/rrem width
parameter KEEP_WIDTH = C_DATA_WIDTH / 8 // KEEP width
) (
// AXI RX
//-----------
output reg [C_DATA_WIDTH-1:0] m_axis_rx_tdata, // RX data to user
output reg m_axis_rx_tvalid, // RX data is valid
input m_axis_rx_tready, // RX ready for data
output [KEEP_WIDTH-1:0] m_axis_rx_tkeep, // RX strobe byte enables
output m_axis_rx_tlast, // RX data is last
output reg [21:0] m_axis_rx_tuser, // RX user signals
// TRN RX
//-----------
input [C_DATA_WIDTH-1:0] trn_rd, // RX data from block
input trn_rsof, // RX start of packet
input trn_reof, // RX end of packet
input trn_rsrc_rdy, // RX source ready
output reg trn_rdst_rdy, // RX destination ready
input trn_rsrc_dsc, // RX source discontinue
input [REM_WIDTH-1:0] trn_rrem, // RX remainder
input trn_rerrfwd, // RX error forward
input [6:0] trn_rbar_hit, // RX BAR hit
input trn_recrc_err, // RX ECRC error
// Null Inputs
//-----------
input null_rx_tvalid, // NULL generated tvalid
input null_rx_tlast, // NULL generated tlast
input [KEEP_WIDTH-1:0] null_rx_tkeep, // NULL generated tkeep
input null_rdst_rdy, // NULL generated rdst_rdy
input [4:0] null_is_eof, // NULL generated is_eof
// System
//-----------
output [2:0] np_counter, // Non-posted counter
input user_clk, // user clock from block
input user_rst // user reset from block
);
// Wires and regs for creating AXI signals
wire [4:0] is_sof;
wire [4:0] is_sof_prev;
wire [4:0] is_eof;
wire [4:0] is_eof_prev;
reg [KEEP_WIDTH-1:0] reg_tkeep;
wire [KEEP_WIDTH-1:0] tkeep;
wire [KEEP_WIDTH-1:0] tkeep_prev;
reg reg_tlast;
wire rsrc_rdy_filtered;
// Wires and regs for previous value buffer
wire [C_DATA_WIDTH-1:0] trn_rd_DW_swapped;
reg [C_DATA_WIDTH-1:0] trn_rd_prev;
wire data_hold;
reg data_prev;
reg trn_reof_prev;
reg [REM_WIDTH-1:0] trn_rrem_prev;
reg trn_rsrc_rdy_prev;
reg trn_rsrc_dsc_prev;
reg trn_rsof_prev;
reg [6:0] trn_rbar_hit_prev;
reg trn_rerrfwd_prev;
reg trn_recrc_err_prev;
// Null packet handling signals
reg null_mux_sel;
reg trn_in_packet;
wire dsc_flag;
wire dsc_detect;
reg reg_dsc_detect;
reg trn_rsrc_dsc_d;
// Create "filtered" version of rsrc_rdy, where discontinued SOFs are removed.
assign rsrc_rdy_filtered = trn_rsrc_rdy &&
(trn_in_packet || (trn_rsof && !trn_rsrc_dsc));
//----------------------------------------------------------------------------//
// Previous value buffer //
// --------------------- //
// We are inserting a pipeline stage in between TRN and AXI, which causes //
// some issues with handshaking signals m_axis_rx_tready/trn_rdst_rdy. The //
// added cycle of latency in the path causes the user design to fall behind //
// the TRN interface whenever it throttles. //
// //
// To avoid loss of data, we must keep the previous value of all trn_r* //
// signals in case the user throttles. //
//----------------------------------------------------------------------------//
always @(posedge user_clk) begin
if(user_rst) begin
trn_rd_prev <= #TCQ {C_DATA_WIDTH{1'b0}};
trn_rsof_prev <= #TCQ 1'b0;
trn_rrem_prev <= #TCQ {REM_WIDTH{1'b0}};
trn_rsrc_rdy_prev <= #TCQ 1'b0;
trn_rbar_hit_prev <= #TCQ 7'h00;
trn_rerrfwd_prev <= #TCQ 1'b0;
trn_recrc_err_prev <= #TCQ 1'b0;
trn_reof_prev <= #TCQ 1'b0;
trn_rsrc_dsc_prev <= #TCQ 1'b0;
end
else begin
// prev buffer works by checking trn_rdst_rdy. When trn_rdst_rdy is
// asserted, a new value is present on the interface.
if(trn_rdst_rdy) begin
trn_rd_prev <= #TCQ trn_rd_DW_swapped;
trn_rsof_prev <= #TCQ trn_rsof;
trn_rrem_prev <= #TCQ trn_rrem;
trn_rbar_hit_prev <= #TCQ trn_rbar_hit;
trn_rerrfwd_prev <= #TCQ trn_rerrfwd;
trn_recrc_err_prev <= #TCQ trn_recrc_err;
trn_rsrc_rdy_prev <= #TCQ rsrc_rdy_filtered;
trn_reof_prev <= #TCQ trn_reof;
trn_rsrc_dsc_prev <= #TCQ trn_rsrc_dsc || dsc_flag;
end
end
end
//----------------------------------------------------------------------------//
// Create TDATA //
//----------------------------------------------------------------------------//
// Convert TRN data format to AXI data format. AXI is DWORD swapped from TRN
// 128-bit: 64-bit: 32-bit:
// TRN DW0 maps to AXI DW3 TRN DW0 maps to AXI DW1 TNR DW0 maps to AXI DW0
// TRN DW1 maps to AXI DW2 TRN DW1 maps to AXI DW0
// TRN DW2 maps to AXI DW1
// TRN DW3 maps to AXI DW0
generate
if(C_DATA_WIDTH == 128) begin : rd_DW_swap_128
assign trn_rd_DW_swapped = {trn_rd[31:0],
trn_rd[63:32],
trn_rd[95:64],
trn_rd[127:96]};
end
else if(C_DATA_WIDTH == 64) begin : rd_DW_swap_64
assign trn_rd_DW_swapped = {trn_rd[31:0], trn_rd[63:32]};
end
else begin : rd_DW_swap_32
assign trn_rd_DW_swapped = trn_rd;
end
endgenerate
// Create special buffer which locks in the proper value of TDATA depending
// on whether the user is throttling or not. This buffer has three states:
//
// HOLD state: TDATA maintains its current value
// - the user has throttled the PCIe block
// PREVIOUS state: the buffer provides the previous value on trn_rd
// - the user has finished throttling, and is a little behind
// the PCIe block
// CURRENT state: the buffer passes the current value on trn_rd
// - the user is caught up and ready to receive the latest
// data from the PCIe block
always @(posedge user_clk) begin
if(user_rst) begin
m_axis_rx_tdata <= #TCQ {C_DATA_WIDTH{1'b0}};
end
else begin
if(!data_hold) begin
// PREVIOUS state
if(data_prev) begin
m_axis_rx_tdata <= #TCQ trn_rd_prev;
end
// CURRENT state
else begin
m_axis_rx_tdata <= #TCQ trn_rd_DW_swapped;
end
end
// else HOLD state
end
end
// Logic to instruct pipeline to hold its value
assign data_hold = (!m_axis_rx_tready && m_axis_rx_tvalid);
// Logic to instruct pipeline to use previous bus values. Always use previous
// value after holding a value.
always @(posedge user_clk) begin
if(user_rst) begin
data_prev <= #TCQ 1'b0;
end
else begin
data_prev <= #TCQ data_hold;
end
end
//----------------------------------------------------------------------------//
// Create TVALID, TLAST, tkeep, TUSER //
// ----------------------------------- //
// Use the same strategy for these signals as for TDATA, except here we need //
// an extra provision for null packets. //
//----------------------------------------------------------------------------//
always @(posedge user_clk) begin
if(user_rst) begin
m_axis_rx_tvalid <= #TCQ 1'b0;
reg_tlast <= #TCQ 1'b0;
reg_tkeep <= #TCQ {KEEP_WIDTH{1'b1}};
m_axis_rx_tuser <= #TCQ 22'h0;
end
else begin
if(!data_hold) begin
// If in a null packet, use null generated value
if(null_mux_sel) begin
m_axis_rx_tvalid <= #TCQ null_rx_tvalid;
reg_tlast <= #TCQ null_rx_tlast;
reg_tkeep <= #TCQ null_rx_tkeep;
m_axis_rx_tuser <= #TCQ {null_is_eof, 17'h0000};
end
// PREVIOUS state
else if(data_prev) begin
m_axis_rx_tvalid <= #TCQ (trn_rsrc_rdy_prev || dsc_flag);
reg_tlast <= #TCQ trn_reof_prev;
reg_tkeep <= #TCQ tkeep_prev;
m_axis_rx_tuser <= #TCQ {is_eof_prev, // TUSER bits [21:17]
2'b00, // TUSER bits [16:15]
is_sof_prev, // TUSER bits [14:10]
1'b0, // TUSER bit [9]
trn_rbar_hit_prev, // TUSER bits [8:2]
trn_rerrfwd_prev, // TUSER bit [1]
trn_recrc_err_prev}; // TUSER bit [0]
end
// CURRENT state
else begin
m_axis_rx_tvalid <= #TCQ (rsrc_rdy_filtered || dsc_flag);
reg_tlast <= #TCQ trn_reof;
reg_tkeep <= #TCQ tkeep;
m_axis_rx_tuser <= #TCQ {is_eof, // TUSER bits [21:17]
2'b00, // TUSER bits [16:15]
is_sof, // TUSER bits [14:10]
1'b0, // TUSER bit [9]
trn_rbar_hit, // TUSER bits [8:2]
trn_rerrfwd, // TUSER bit [1]
trn_recrc_err}; // TUSER bit [0]
end
end
// else HOLD state
end
end
// Hook up TLAST and tkeep depending on interface width
generate
// For 128-bit interface, don't pass TLAST and tkeep to user (is_eof and
// is_data passed to user instead). reg_tlast is still used internally.
if(C_DATA_WIDTH == 128) begin : tlast_tkeep_hookup_128
assign m_axis_rx_tlast = 1'b0;
assign m_axis_rx_tkeep = {KEEP_WIDTH{1'b1}};
end
// For 64/32-bit interface, pass TLAST to user.
else begin : tlast_tkeep_hookup_64_32
assign m_axis_rx_tlast = reg_tlast;
assign m_axis_rx_tkeep = reg_tkeep;
end
endgenerate
//----------------------------------------------------------------------------//
// Create tkeep //
// ------------ //
// Convert RREM to STRB. Here, we are converting the encoding method for the //
// location of the EOF from TRN flavor (rrem) to AXI (tkeep). //
// //
// NOTE: for each configuration, we need two values of tkeep, the current and //
// previous values. The need for these two values is described below. //
//----------------------------------------------------------------------------//
generate
if(C_DATA_WIDTH == 128) begin : rrem_to_tkeep_128
// TLAST and tkeep not used in 128-bit interface. is_sof and is_eof used
// instead.
assign tkeep = 16'h0000;
assign tkeep_prev = 16'h0000;
end
else if(C_DATA_WIDTH == 64) begin : rrem_to_tkeep_64
// 64-bit interface: contains 2 DWORDs per cycle, for a total of 8 bytes
// - tkeep has only two possible values here, 0xFF or 0x0F
assign tkeep = trn_rrem ? 8'hFF : 8'h0F;
assign tkeep_prev = trn_rrem_prev ? 8'hFF : 8'h0F;
end
else begin : rrem_to_tkeep_32
// 32-bit interface: contains 1 DWORD per cycle, for a total of 4 bytes
// - tkeep is always 0xF in this case, due to the nature of the PCIe block
assign tkeep = 4'hF;
assign tkeep_prev = 4'hF;
end
endgenerate
//----------------------------------------------------------------------------//
// Create is_sof //
// ------------- //
// is_sof is a signal to the user indicating the location of SOF in TDATA . //
// Due to inherent 64-bit alignment of packets from the block, the only //
// possible values are: //
// Value Valid data widths //
// 5'b11000 (sof @ byte 8) 128 //
// 5'b10000 (sof @ byte 0) 128, 64, 32 //
// 5'b00000 (sof not present) 128, 64, 32 //
//----------------------------------------------------------------------------//
generate
if(C_DATA_WIDTH == 128) begin : is_sof_128
assign is_sof = {(trn_rsof && !trn_rsrc_dsc), // bit 4: enable
(trn_rsof && !trn_rrem[1]), // bit 3: sof @ byte 8?
3'b000}; // bit 2-0: hardwired 0
assign is_sof_prev = {(trn_rsof_prev && !trn_rsrc_dsc_prev), // bit 4
(trn_rsof_prev && !trn_rrem_prev[1]), // bit 3
3'b000}; // bit 2-0
end
else begin : is_sof_64_32
assign is_sof = {(trn_rsof && !trn_rsrc_dsc), // bit 4: enable
4'b0000}; // bit 3-0: hardwired 0
assign is_sof_prev = {(trn_rsof_prev && !trn_rsrc_dsc_prev), // bit 4
4'b0000}; // bit 3-0
end
endgenerate
//----------------------------------------------------------------------------//
// Create is_eof //
// ------------- //
// is_eof is a signal to the user indicating the location of EOF in TDATA . //
// Due to DWORD granularity of packets from the block, the only //
// possible values are: //
// Value Valid data widths //
// 5'b11111 (eof @ byte 15) 128 //
// 5'b11011 (eof @ byte 11) 128 //
// 5'b10111 (eof @ byte 7) 128, 64 //
// 5'b10011 (eof @ byte 3)` 128, 64, 32 //
// 5'b00011 (eof not present) 128, 64, 32 //
//----------------------------------------------------------------------------//
generate
if(C_DATA_WIDTH == 128) begin : is_eof_128
assign is_eof = {trn_reof, // bit 4: enable
trn_rrem, // bit 3-2: encoded eof loc rom block
2'b11}; // bit 1-0: hardwired 1
assign is_eof_prev = {trn_reof_prev, // bit 4: enable
trn_rrem_prev, // bit 3-2: encoded eof loc from block
2'b11}; // bit 1-0: hardwired 1
end
else if(C_DATA_WIDTH == 64) begin : is_eof_64
assign is_eof = {trn_reof, // bit 4: enable
1'b0, // bit 3: hardwired 0
trn_rrem, // bit 2: encoded eof loc from block
2'b11}; // bit 1-0: hardwired 1
assign is_eof_prev = {trn_reof_prev, // bit 4: enable
1'b0, // bit 3: hardwired 0
trn_rrem_prev, // bit 2: encoded eof loc from block
2'b11}; // bit 1-0: hardwired 1
end
else begin : is_eof_32
assign is_eof = {trn_reof, // bit 4: enable
4'b0011}; // bit 3-0: hardwired to byte 3
assign is_eof_prev = {trn_reof_prev, // bit 4: enable
4'b0011}; // bit 3-0: hardwired to byte 3
end
endgenerate
//----------------------------------------------------------------------------//
// Create trn_rdst_rdy //
//----------------------------------------------------------------------------//
always @(posedge user_clk) begin
if(user_rst) begin
trn_rdst_rdy <= #TCQ 1'b0;
end
else begin
// If in a null packet, use null generated value
if(null_mux_sel && m_axis_rx_tready) begin
trn_rdst_rdy <= #TCQ null_rdst_rdy;
end
// If a discontinue needs to be serviced, throttle the block until we are
// ready to pad out the packet.
else if(dsc_flag) begin
trn_rdst_rdy <= #TCQ 1'b0;
end
// If in a packet, pass user back-pressure directly to block
else if(m_axis_rx_tvalid) begin
trn_rdst_rdy <= #TCQ m_axis_rx_tready;
end
// If idle, default to no back-pressure. We need to default to the
// "ready to accept data" state to make sure we catch the first
// clock of data of a new packet.
else begin
trn_rdst_rdy <= #TCQ 1'b1;
end
end
end
//----------------------------------------------------------------------------//
// Create null_mux_sel //
// null_mux_sel is the signal used to detect a discontinue situation and //
// mux in the null packet generated in rx_null_gen. Only mux in null data //
// when not at the beginningof a packet. SOF discontinues do not require //
// padding, as the whole packet is simply squashed instead. //
//----------------------------------------------------------------------------//
always @(posedge user_clk) begin
if(user_rst) begin
null_mux_sel <= #TCQ 1'b0;
end
else begin
// NULL packet done
if(null_mux_sel && null_rx_tlast && m_axis_rx_tready)
begin
null_mux_sel <= #TCQ 1'b0;
end
// Discontinue detected and we're in packet, so switch to NULL packet
else if(dsc_flag && !data_hold) begin
null_mux_sel <= #TCQ 1'b1;
end
end
end
//----------------------------------------------------------------------------//
// Create discontinue tracking signals //
//----------------------------------------------------------------------------//
// Create signal trn_in_packet, which is needed to validate trn_rsrc_dsc. We
// should ignore trn_rsrc_dsc when it's asserted out-of-packet.
always @(posedge user_clk) begin
if(user_rst) begin
trn_in_packet <= #TCQ 1'b0;
end
else begin
if(trn_rsof && !trn_reof && rsrc_rdy_filtered && trn_rdst_rdy)
begin
trn_in_packet <= #TCQ 1'b1;
end
else if(trn_rsrc_dsc) begin
trn_in_packet <= #TCQ 1'b0;
end
else if(trn_reof && !trn_rsof && trn_rsrc_rdy && trn_rdst_rdy) begin
trn_in_packet <= #TCQ 1'b0;
end
end
end
// Create dsc_flag, which identifies and stores mid-packet discontinues that
// require null packet padding. This signal is edge sensitive to trn_rsrc_dsc,
// to make sure we don't service the same dsc twice in the event that
// trn_rsrc_dsc stays asserted for longer than it takes to pad out the packet.
assign dsc_detect = trn_rsrc_dsc && !trn_rsrc_dsc_d && trn_in_packet &&
(!trn_rsof || trn_reof) && !(trn_rdst_rdy && trn_reof);
always @(posedge user_clk) begin
if(user_rst) begin
reg_dsc_detect <= #TCQ 1'b0;
trn_rsrc_dsc_d <= #TCQ 1'b0;
end
else begin
if(dsc_detect) begin
reg_dsc_detect <= #TCQ 1'b1;
end
else if(null_mux_sel) begin
reg_dsc_detect <= #TCQ 1'b0;
end
trn_rsrc_dsc_d <= #TCQ trn_rsrc_dsc;
end
end
assign dsc_flag = dsc_detect || reg_dsc_detect;
//----------------------------------------------------------------------------//
// Create np_counter (V6 128-bit only). This counter tells the V6 128-bit //
// interface core how many NP packets have left the RX pipeline. The V6 //
// 128-bit interface uses this count to perform rnp_ok modulation. //
//----------------------------------------------------------------------------//
generate
if(C_FAMILY == "V6" && C_DATA_WIDTH == 128) begin : np_cntr_to_128_enabled
reg [2:0] reg_np_counter;
// Look for NP packets beginning on lower (i.e. unaligned) start
wire mrd_lower = (!(|m_axis_rx_tdata[92:88]) && !m_axis_rx_tdata[94]);
wire mrd_lk_lower = (m_axis_rx_tdata[92:88] == 5'b00001);
wire io_rdwr_lower = (m_axis_rx_tdata[92:88] == 5'b00010);
wire cfg_rdwr_lower = (m_axis_rx_tdata[92:89] == 4'b0010);
wire atomic_lower = ((&m_axis_rx_tdata[91:90]) && m_axis_rx_tdata[94]);
wire np_pkt_lower = (mrd_lower ||
mrd_lk_lower ||
io_rdwr_lower ||
cfg_rdwr_lower ||
atomic_lower) && m_axis_rx_tuser[13];
// Look for NP packets beginning on upper (i.e. aligned) start
wire mrd_upper = (!(|m_axis_rx_tdata[28:24]) && !m_axis_rx_tdata[30]);
wire mrd_lk_upper = (m_axis_rx_tdata[28:24] == 5'b00001);
wire io_rdwr_upper = (m_axis_rx_tdata[28:24] == 5'b00010);
wire cfg_rdwr_upper = (m_axis_rx_tdata[28:25] == 4'b0010);
wire atomic_upper = ((&m_axis_rx_tdata[27:26]) && m_axis_rx_tdata[30]);
wire np_pkt_upper = (mrd_upper ||
mrd_lk_upper ||
io_rdwr_upper ||
cfg_rdwr_upper ||
atomic_upper) && !m_axis_rx_tuser[13];
wire pkt_accepted =
m_axis_rx_tuser[14] && m_axis_rx_tready && m_axis_rx_tvalid;
// Increment counter whenever an NP packet leaves the RX pipeline
always @(posedge user_clk) begin
if (user_rst) begin
reg_np_counter <= #TCQ 0;
end
else begin
if((np_pkt_lower || np_pkt_upper) && pkt_accepted)
begin
reg_np_counter <= #TCQ reg_np_counter + 3'h1;
end
end
end
assign np_counter = reg_np_counter;
end
else begin : np_cntr_to_128_disabled
assign np_counter = 3'h0;
end
endgenerate
endmodule
|
module
missed_ack
strobed when a slave ack is missed
Parameters:
prescale
set prescale to 1/4 of the minimum clock period in units
of input clk cycles (prescale = Fclk / (FI2Cclk * 4))
stop_on_idle
automatically issue stop when command input is not valid
Example of interfacing with tristate pins:
(this will work for any tristate bus)
assign scl_i = scl_pin;
assign scl_pin = scl_t ? 1'bz : scl_o;
assign sda_i = sda_pin;
assign sda_pin = sda_t ? 1'bz : sda_o;
Equivalent code that does not use *_t connections:
(we can get away with this because I2C is open-drain)
assign scl_i = scl_pin;
assign scl_pin = scl_o ? 1'bz : 1'b0;
assign sda_i = sda_pin;
assign sda_pin = sda_o ? 1'bz : 1'b0;
Example of two interconnected I2C devices:
assign scl_1_i = scl_1_o & scl_2_o;
assign scl_2_i = scl_1_o & scl_2_o;
assign sda_1_i = sda_1_o & sda_2_o;
assign sda_2_i = sda_1_o & sda_2_o;
Example of two I2C devices sharing the same pins:
assign scl_1_i = scl_pin;
assign scl_2_i = scl_pin;
assign scl_pin = (scl_1_o & scl_2_o) ? 1'bz : 1'b0;
assign sda_1_i = sda_pin;
assign sda_2_i = sda_pin;
assign sda_pin = (sda_1_o & sda_2_o) ? 1'bz : 1'b0;
Notes:
scl_o should not be connected directly to scl_i, only via AND logic or a tristate
I/O pin. This would prevent devices from stretching the clock period.
*/
localparam [4:0]
STATE_IDLE = 4'd0,
STATE_ACTIVE_WRITE = 4'd1,
STATE_ACTIVE_READ = 4'd2,
STATE_START_WAIT = 4'd3,
STATE_START = 4'd4,
STATE_ADDRESS_1 = 4'd5,
STATE_ADDRESS_2 = 4'd6,
STATE_WRITE_1 = 4'd7,
STATE_WRITE_2 = 4'd8,
STATE_WRITE_3 = 4'd9,
STATE_READ = 4'd10,
STATE_STOP = 4'd11;
reg [4:0] state_reg = STATE_IDLE, state_next;
localparam [4:0]
PHY_STATE_IDLE = 5'd0,
PHY_STATE_ACTIVE = 5'd1,
PHY_STATE_REPEATED_START_1 = 5'd2,
PHY_STATE_REPEATED_START_2 = 5'd3,
PHY_STATE_START_1 = 5'd4,
PHY_STATE_START_2 = 5'd5,
PHY_STATE_WRITE_BIT_1 = 5'd6,
PHY_STATE_WRITE_BIT_2 = 5'd7,
PHY_STATE_WRITE_BIT_3 = 5'd8,
PHY_STATE_READ_BIT_1 = 5'd9,
PHY_STATE_READ_BIT_2 = 5'd10,
PHY_STATE_READ_BIT_3 = 5'd11,
PHY_STATE_READ_BIT_4 = 5'd12,
PHY_STATE_STOP_1 = 5'd13,
PHY_STATE_STOP_2 = 5'd14,
PHY_STATE_STOP_3 = 5'd15;
reg [4:0] phy_state_reg = STATE_IDLE, phy_state_next;
reg phy_start_bit;
reg phy_stop_bit;
reg phy_write_bit;
reg phy_read_bit;
reg phy_release_bus;
reg phy_tx_data;
reg phy_rx_data_reg = 1'b0, phy_rx_data_next;
reg [6:0] addr_reg = 7'd0, addr_next;
reg [7:0] data_reg = 8'd0, data_next;
reg last_reg = 1'b0, last_next;
reg mode_read_reg = 1'b0, mode_read_next;
reg mode_write_multiple_reg = 1'b0, mode_write_multiple_next;
reg mode_stop_reg = 1'b0, mode_stop_next;
reg [16:0] delay_reg = 16'd0, delay_next;
reg delay_scl_reg = 1'b0, delay_scl_next;
reg delay_sda_reg = 1'b0, delay_sda_next;
reg [3:0] bit_count_reg = 4'd0, bit_count_next;
reg s_axis_cmd_ready_reg = 1'b0, s_axis_cmd_ready_next;
reg s_axis_data_tready_reg = 1'b0, s_axis_data_tready_next;
reg [7:0] m_axis_data_tdata_reg = 8'd0, m_axis_data_tdata_next;
reg m_axis_data_tvalid_reg = 1'b0, m_axis_data_tvalid_next;
reg m_axis_data_tlast_reg = 1'b0, m_axis_data_tlast_next;
reg scl_i_reg = 1'b1;
reg sda_i_reg = 1'b1;
reg scl_o_reg = 1'b1, scl_o_next;
reg sda_o_reg = 1'b1, sda_o_next;
reg last_scl_i_reg = 1'b1;
reg last_sda_i_reg = 1'b1;
reg busy_reg = 1'b0;
reg bus_active_reg = 1'b0;
reg bus_control_reg = 1'b0, bus_control_next;
reg missed_ack_reg = 1'b0, missed_ack_next;
assign s_axis_cmd_ready = s_axis_cmd_ready_reg;
assign s_axis_data_tready = s_axis_data_tready_reg;
assign m_axis_data_tdata = m_axis_data_tdata_reg;
assign m_axis_data_tvalid = m_axis_data_tvalid_reg;
assign m_axis_data_tlast = m_axis_data_tlast_reg;
assign scl_o = scl_o_reg;
assign scl_t = scl_o_reg;
assign sda_o = sda_o_reg;
assign sda_t = sda_o_reg;
assign busy = busy_reg;
assign bus_active = bus_active_reg;
assign bus_control = bus_control_reg;
assign missed_ack = missed_ack_reg;
wire scl_posedge = scl_i_reg & ~last_scl_i_reg;
wire scl_negedge = ~scl_i_reg & last_scl_i_reg;
wire sda_posedge = sda_i_reg & ~last_sda_i_reg;
wire sda_negedge = ~sda_i_reg & last_sda_i_reg;
wire start_bit = sda_negedge & scl_i_reg;
wire stop_bit = sda_posedge & scl_i_reg;
always @* begin
state_next = STATE_IDLE;
phy_start_bit = 1'b0;
phy_stop_bit = 1'b0;
phy_write_bit = 1'b0;
phy_read_bit = 1'b0;
phy_tx_data = 1'b0;
phy_release_bus = 1'b0;
addr_next = addr_reg;
data_next = data_reg;
last_next = last_reg;
mode_read_next = mode_read_reg;
mode_write_multiple_next = mode_write_multiple_reg;
mode_stop_next = mode_stop_reg;
bit_count_next = bit_count_reg;
s_axis_cmd_ready_next = 1'b0;
s_axis_data_tready_next = 1'b0;
m_axis_data_tdata_next = m_axis_data_tdata_reg;
m_axis_data_tvalid_next = m_axis_data_tvalid_reg & ~m_axis_data_tready;
m_axis_data_tlast_next = m_axis_data_tlast_reg;
missed_ack_next = 1'b0;
// generate delays
if (phy_state_reg != PHY_STATE_IDLE && phy_state_reg != PHY_STATE_ACTIVE) begin
// wait for phy operation
state_next = state_reg;
end else begin
// process states
case (state_reg)
STATE_IDLE: begin
// line idle
s_axis_cmd_ready_next = 1'b1;
if (s_axis_cmd_ready & s_axis_cmd_valid) begin
// command valid
if (s_axis_cmd_read ^ (s_axis_cmd_write | s_axis_cmd_write_multiple)) begin
// read or write command
addr_next = s_axis_cmd_address;
mode_read_next = s_axis_cmd_read;
mode_write_multiple_next = s_axis_cmd_write_multiple;
mode_stop_next = s_axis_cmd_stop;
s_axis_cmd_ready_next = 1'b0;
// start bit
if (bus_active) begin
state_next = STATE_START_WAIT;
end else begin
phy_start_bit = 1'b1;
bit_count_next = 4'd8;
state_next = STATE_ADDRESS_1;
end
end else begin
// invalid or unspecified - ignore
state_next = STATE_IDLE;
end
end else begin
state_next = STATE_IDLE;
end
end
STATE_ACTIVE_WRITE: begin
// line active with current address and read/write mode
s_axis_cmd_ready_next = 1'b1;
if (s_axis_cmd_ready & s_axis_cmd_valid) begin
// command valid
if (s_axis_cmd_read ^ (s_axis_cmd_write | s_axis_cmd_write_multiple)) begin
// read or write command
addr_next = s_axis_cmd_address;
mode_read_next = s_axis_cmd_read;
mode_write_multiple_next = s_axis_cmd_write_multiple;
mode_stop_next = s_axis_cmd_stop;
s_axis_cmd_ready_next = 1'b0;
if (s_axis_cmd_start || s_axis_cmd_address != addr_reg || s_axis_cmd_read) begin
// address or mode mismatch or forced start - repeated start
// repeated start bit
phy_start_bit = 1'b1;
bit_count_next = 4'd8;
state_next = STATE_ADDRESS_1;
end else begin
// address and mode match
// start write
s_axis_data_tready_next = 1'b1;
state_next = STATE_WRITE_1;
end
end else if (s_axis_cmd_stop && !(s_axis_cmd_read || s_axis_cmd_write || s_axis_cmd_write_multiple)) begin
// stop command
phy_stop_bit = 1'b1;
state_next = STATE_IDLE;
end else begin
// invalid or unspecified - ignore
state_next = STATE_ACTIVE_WRITE;
end
end else begin
if (stop_on_idle & s_axis_cmd_ready & ~s_axis_cmd_valid) begin
// no waiting command and stop_on_idle selected, issue stop condition
phy_stop_bit = 1'b1;
state_next = STATE_IDLE;
end else begin
state_next = STATE_ACTIVE_WRITE;
end
end
end
STATE_ACTIVE_READ: begin
// line active to current address
s_axis_cmd_ready_next = ~m_axis_data_tvalid;
if (s_axis_cmd_ready & s_axis_cmd_valid) begin
// command valid
if (s_axis_cmd_read ^ (s_axis_cmd_write | s_axis_cmd_write_multiple)) begin
// read or write command
addr_next = s_axis_cmd_address;
mode_read_next = s_axis_cmd_read;
mode_write_multiple_next = s_axis_cmd_write_multiple;
mode_stop_next = s_axis_cmd_stop;
s_axis_cmd_ready_next = 1'b0;
if (s_axis_cmd_start || s_axis_cmd_address != addr_reg || s_axis_cmd_write) begin
// address or mode mismatch or forced start - repeated start
// write nack for previous read
phy_write_bit = 1'b1;
phy_tx_data = 1'b1;
// repeated start bit
state_next = STATE_START;
end else begin
// address and mode match
// write ack for previous read
phy_write_bit = 1'b1;
phy_tx_data = 1'b0;
// start next read
bit_count_next = 4'd8;
data_next = 8'd0;
state_next = STATE_READ;
end
end else if (s_axis_cmd_stop && !(s_axis_cmd_read || s_axis_cmd_write || s_axis_cmd_write_multiple)) begin
// stop command
// write nack for previous read
phy_write_bit = 1'b1;
phy_tx_data = 1'b1;
// send stop bit
state_next = STATE_STOP;
end else begin
// invalid or unspecified - ignore
state_next = STATE_ACTIVE_READ;
end
end else begin
if (stop_on_idle & s_axis_cmd_ready & ~s_axis_cmd_valid) begin
// no waiting command and stop_on_idle selected, issue stop condition
// write ack for previous read
phy_write_bit = 1'b1;
phy_tx_data = 1'b1;
// send stop bit
state_next = STATE_STOP;
end else begin
state_next = STATE_ACTIVE_READ;
end
end
end
STATE_START_WAIT: begin
// wait for bus idle
if (bus_active) begin
state_next = STATE_START_WAIT;
end else begin
// bus is idle, take control
phy_start_bit = 1'b1;
bit_count_next = 4'd8;
state_next = STATE_ADDRESS_1;
end
end
STATE_START: begin
// send start bit
phy_start_bit = 1'b1;
bit_count_next = 4'd8;
state_next = STATE_ADDRESS_1;
end
STATE_ADDRESS_1: begin
// send address
bit_count_next = bit_count_reg - 1;
if (bit_count_reg > 1) begin
// send address
phy_write_bit = 1'b1;
phy_tx_data = addr_reg[bit_count_reg-2];
state_next = STATE_ADDRESS_1;
end else if (bit_count_reg > 0) begin
// send read/write bit
phy_write_bit = 1'b1;
phy_tx_data = mode_read_reg;
state_next = STATE_ADDRESS_1;
end else begin
// read ack bit
phy_read_bit = 1'b1;
state_next = STATE_ADDRESS_2;
end
end
STATE_ADDRESS_2: begin
// read ack bit
missed_ack_next = phy_rx_data_reg;
if (mode_read_reg) begin
// start read
bit_count_next = 4'd8;
data_next = 1'b0;
state_next = STATE_READ;
end else begin
// start write
s_axis_data_tready_next = 1'b1;
state_next = STATE_WRITE_1;
end
end
STATE_WRITE_1: begin
s_axis_data_tready_next = 1'b1;
if (s_axis_data_tready & s_axis_data_tvalid) begin
// got data, start write
data_next = s_axis_data_tdata;
last_next = s_axis_data_tlast;
bit_count_next = 4'd8;
s_axis_data_tready_next = 1'b0;
state_next = STATE_WRITE_2;
end else begin
// wait for data
state_next = STATE_WRITE_1;
end
end
STATE_WRITE_2: begin
// send data
bit_count_next = bit_count_reg - 1;
if (bit_count_reg > 0) begin
// write data bit
phy_write_bit = 1'b1;
phy_tx_data = data_reg[bit_count_reg-1];
state_next = STATE_WRITE_2;
end else begin
// read ack bit
phy_read_bit = 1'b1;
state_next = STATE_WRITE_3;
end
end
STATE_WRITE_3: begin
// read ack bit
missed_ack_next = phy_rx_data_reg;
if (mode_write_multiple_reg && !last_reg) begin
// more to write
state_next = STATE_WRITE_1;
end else if (mode_stop_reg) begin
// last cycle and stop selected
phy_stop_bit = 1'b1;
state_next = STATE_IDLE;
end else begin
// otherwise, return to bus active state
state_next = STATE_ACTIVE_WRITE;
end
end
STATE_READ: begin
// read data
bit_count_next = bit_count_reg - 1;
data_next = {data_reg[6:0], phy_rx_data_reg};
if (bit_count_reg > 0) begin
// read next bit
phy_read_bit = 1'b1;
state_next = STATE_READ;
end else begin
// output data word
m_axis_data_tdata_next = data_next;
m_axis_data_tvalid_next = 1'b1;
m_axis_data_tlast_next = 1'b0;
if (mode_stop_reg) begin
// send nack and stop
m_axis_data_tlast_next = 1'b1;
phy_write_bit = 1'b1;
phy_tx_data = 1'b1;
state_next = STATE_STOP;
end else begin
// return to bus active state
state_next = STATE_ACTIVE_READ;
end
end
end
STATE_STOP: begin
// send stop bit
phy_stop_bit = 1'b1;
state_next = STATE_IDLE;
end
endcase
end
end
always @* begin
phy_state_next = PHY_STATE_IDLE;
phy_rx_data_next = phy_rx_data_reg;
delay_next = delay_reg;
delay_scl_next = delay_scl_reg;
delay_sda_next = delay_sda_reg;
scl_o_next = scl_o_reg;
sda_o_next = sda_o_reg;
bus_control_next = bus_control_reg;
if (phy_release_bus) begin
// release bus and return to idle state
sda_o_next = 1'b1;
scl_o_next = 1'b1;
delay_scl_next = 1'b0;
delay_sda_next = 1'b0;
delay_next = 1'b0;
phy_state_next = PHY_STATE_IDLE;
end else if (delay_scl_reg) begin
// wait for SCL to match command
delay_scl_next = scl_o_reg & ~scl_i_reg;
phy_state_next = phy_state_reg;
end else if (delay_sda_reg) begin
// wait for SDA to match command
delay_sda_next = sda_o_reg & ~sda_i_reg;
phy_state_next = phy_state_reg;
end else if (delay_reg > 0) begin
// time delay
delay_next = delay_reg - 1;
phy_state_next = phy_state_reg;
end else begin
case (phy_state_reg)
PHY_STATE_IDLE: begin
// bus idle - wait for start command
sda_o_next = 1'b1;
scl_o_next = 1'b1;
if (phy_start_bit) begin
sda_o_next = 1'b0;
delay_next = prescale;
phy_state_next = PHY_STATE_START_1;
end else begin
phy_state_next = PHY_STATE_IDLE;
end
end
PHY_STATE_ACTIVE: begin
// bus active
if (phy_start_bit) begin
sda_o_next = 1'b1;
delay_next = prescale;
phy_state_next = PHY_STATE_REPEATED_START_1;
end else if (phy_write_bit) begin
sda_o_next = phy_tx_data;
delay_next = prescale;
phy_state_next = PHY_STATE_WRITE_BIT_1;
end else if (phy_read_bit) begin
sda_o_next = 1'b1;
delay_next = prescale;
phy_state_next = PHY_STATE_READ_BIT_1;
end else if (phy_stop_bit) begin
sda_o_next = 1'b0;
delay_next = prescale;
phy_state_next = PHY_STATE_STOP_1;
end else begin
phy_state_next = PHY_STATE_ACTIVE;
end
end
PHY_STATE_REPEATED_START_1: begin
// generate repeated start bit
// ______
// sda XXX/ \_______
// _______
// scl ______/ \___
//
scl_o_next = 1'b1;
delay_scl_next = 1'b1;
delay_next = prescale;
phy_state_next = PHY_STATE_REPEATED_START_2;
end
PHY_STATE_REPEATED_START_2: begin
// generate repeated start bit
// ______
// sda XXX/ \_______
// _______
// scl ______/ \___
//
sda_o_next = 1'b0;
delay_next = prescale;
phy_state_next = PHY_STATE_START_1;
end
PHY_STATE_START_1: begin
// generate start bit
// ___
// sda \_______
// _______
// scl \___
//
scl_o_next = 1'b0;
delay_next = prescale;
phy_state_next = PHY_STATE_START_2;
end
PHY_STATE_START_2: begin
// generate start bit
// ___
// sda \_______
// _______
// scl \___
//
bus_control_next = 1'b1;
phy_state_next = PHY_STATE_ACTIVE;
end
PHY_STATE_WRITE_BIT_1: begin
// write bit
// ________
// sda X________X
// ____
// scl __/ \__
scl_o_next = 1'b1;
delay_scl_next = 1'b1;
delay_next = prescale << 1;
phy_state_next = PHY_STATE_WRITE_BIT_2;
end
PHY_STATE_WRITE_BIT_2: begin
// write bit
// ________
// sda X________X
// ____
// scl __/ \__
scl_o_next = 1'b0;
delay_next = prescale;
phy_state_next = PHY_STATE_WRITE_BIT_3;
end
PHY_STATE_WRITE_BIT_3: begin
// write bit
// ________
// sda X________X
// ____
// scl __/ \__
phy_state_next = PHY_STATE_ACTIVE;
end
PHY_STATE_READ_BIT_1: begin
// read bit
// ________
// sda X________X
// ____
// scl __/ \__
scl_o_next = 1'b1;
delay_scl_next = 1'b1;
delay_next = prescale;
phy_state_next = PHY_STATE_READ_BIT_2;
end
PHY_STATE_READ_BIT_2: begin
// read bit
// ________
// sda X________X
// ____
// scl __/ \__
phy_rx_data_next = sda_i_reg;
delay_next = prescale;
phy_state_next = PHY_STATE_READ_BIT_3;
end
PHY_STATE_READ_BIT_3: begin
// read bit
// ________
// sda X________X
// ____
// scl __/ \__
scl_o_next = 1'b0;
delay_next = prescale;
phy_state_next = PHY_STATE_READ_BIT_4;
end
PHY_STATE_READ_BIT_4: begin
// read bit
// ________
// sda X________X
// ____
// scl __/ \__
phy_state_next = PHY_STATE_ACTIVE;
end
PHY_STATE_STOP_1: begin
// stop bit
// ___
// sda XXX\_______/
// _______
// scl _______/
scl_o_next = 1'b1;
delay_scl_next = 1'b1;
delay_next = prescale;
phy_state_next = PHY_STATE_STOP_2;
end
PHY_STATE_STOP_2: begin
// stop bit
// ___
// sda XXX\_______/
// _______
// scl _______/
sda_o_next = 1'b1;
delay_next = prescale;
phy_state_next = PHY_STATE_STOP_3;
end
PHY_STATE_STOP_3: begin
// stop bit
// ___
// sda XXX\_______/
// _______
// scl _______/
bus_control_next = 1'b0;
phy_state_next = PHY_STATE_IDLE;
end
endcase
end
end
always @(posedge clk) begin
state_reg <= state_next;
phy_state_reg <= phy_state_next;
phy_rx_data_reg <= phy_rx_data_next;
addr_reg <= addr_next;
data_reg <= data_next;
last_reg <= last_next;
mode_read_reg <= mode_read_next;
mode_write_multiple_reg <= mode_write_multiple_next;
mode_stop_reg <= mode_stop_next;
delay_reg <= delay_next;
delay_scl_reg <= delay_scl_next;
delay_sda_reg <= delay_sda_next;
bit_count_reg <= bit_count_next;
s_axis_cmd_ready_reg <= s_axis_cmd_ready_next;
s_axis_data_tready_reg <= s_axis_data_tready_next;
m_axis_data_tdata_reg <= m_axis_data_tdata_next;
m_axis_data_tlast_reg <= m_axis_data_tlast_next;
m_axis_data_tvalid_reg <= m_axis_data_tvalid_next;
scl_i_reg <= scl_i;
sda_i_reg <= sda_i;
scl_o_reg <= scl_o_next;
sda_o_reg <= sda_o_next;
last_scl_i_reg <= scl_i_reg;
last_sda_i_reg <= sda_i_reg;
busy_reg <= !(state_reg == STATE_IDLE || state_reg == STATE_ACTIVE_WRITE || state_reg == STATE_ACTIVE_READ) || !(phy_state_reg == PHY_STATE_IDLE || phy_state_reg == PHY_STATE_ACTIVE);
if (start_bit) begin
bus_active_reg <= 1'b1;
end else if (stop_bit) begin
bus_active_reg <= 1'b0;
end else begin
bus_active_reg <= bus_active_reg;
end
bus_control_reg <= bus_control_next;
missed_ack_reg <= missed_ack_next;
if (rst) begin
state_reg <= STATE_IDLE;
phy_state_reg <= PHY_STATE_IDLE;
delay_reg <= 16'd0;
delay_scl_reg <= 1'b0;
delay_sda_reg <= 1'b0;
s_axis_cmd_ready_reg <= 1'b0;
s_axis_data_tready_reg <= 1'b0;
m_axis_data_tvalid_reg <= 1'b0;
scl_o_reg <= 1'b1;
sda_o_reg <= 1'b1;
busy_reg <= 1'b0;
bus_active_reg <= 1'b0;
bus_control_reg <= 1'b0;
missed_ack_reg <= 1'b0;
end
end
endmodule
|
module soc_design_SystemID (
// inputs:
address,
clock,
reset_n,
// outputs:
readdata
)
;
output [ 31: 0] readdata;
input address;
input clock;
input reset_n;
wire [ 31: 0] readdata;
//control_slave, which is an e_avalon_slave
assign readdata = address ? 1500011272 : 255;
endmodule
|
module fifo_full_block (/*AUTOARG*/
// Outputs
wr_fifo_full, wr_fifo_progfull, wr_addr, wr_gray_pointer,
// Inputs
reset, wr_clk, wr_rd_gray_pointer, wr_write
);
parameter AW = 2; // Number of bits to access all the entries
//##########
//# INPUTS
//##########
input reset;
input wr_clk;
input [AW:0] wr_rd_gray_pointer;//synced from read domain
input wr_write;
//###########
//# OUTPUTS
//###########
output wr_fifo_full;
output wr_fifo_progfull;//TODO: hack!, fix this properly
//also make, programmable
output [AW-1:0] wr_addr;
output [AW:0] wr_gray_pointer;//for read domain
//#########
//# REGS
//#########
reg [AW:0] wr_gray_pointer;
reg [AW:0] wr_binary_pointer;
reg wr_fifo_full;
//##########
//# WIRES
//##########
wire wr_fifo_full_next;
wire [AW:0] wr_gray_next;
wire [AW:0] wr_binary_next;
wire wr_fifo_progfull_next;
reg wr_fifo_progfull;
//Counter States
always @(posedge wr_clk or posedge reset)
if(reset)
begin
wr_binary_pointer[AW:0] <= {(AW+1){1'b0}};
wr_gray_pointer[AW:0] <= {(AW+1){1'b0}};
end
else if(wr_write)
begin
wr_binary_pointer[AW:0] <= wr_binary_next[AW:0];
wr_gray_pointer[AW:0] <= wr_gray_next[AW:0];
end
//Write Address
assign wr_addr[AW-1:0] = wr_binary_pointer[AW-1:0];
//Updating binary pointer
assign wr_binary_next[AW:0] = wr_binary_pointer[AW:0] +
{{(AW){1'b0}},wr_write};
//Gray Pointer Conversion (for more reliable synchronization)!
assign wr_gray_next[AW:0] = {1'b0,wr_binary_next[AW:1]} ^
wr_binary_next[AW:0];
//FIFO full indication
assign wr_fifo_full_next =
(wr_gray_next[AW-2:0] == wr_rd_gray_pointer[AW-2:0]) &
(wr_gray_next[AW] ^ wr_rd_gray_pointer[AW]) &
(wr_gray_next[AW-1] ^ wr_rd_gray_pointer[AW-1]);
//FIFO almost full
assign wr_fifo_progfull_next =
(wr_gray_next[AW-3:0] == wr_rd_gray_pointer[AW-3:0]) &
(wr_gray_next[AW] ^ wr_rd_gray_pointer[AW]) &
(wr_gray_next[AW-1] ^ wr_rd_gray_pointer[AW-1]) &
(wr_gray_next[AW-2] ^ wr_rd_gray_pointer[AW-2]);
always @ (posedge wr_clk or posedge reset)
if(reset)
wr_fifo_full <= 1'b0;
else
wr_fifo_full <=wr_fifo_full_next;
always @ (posedge wr_clk or posedge reset)
if(reset)
wr_fifo_progfull <= 1'b0;
else
wr_fifo_progfull <=wr_fifo_progfull_next;
endmodule
|
module pcie_7x_v1_11_0_pipe_drp #
(
parameter PCIE_GT_DEVICE = "GTX", // PCIe GT device
parameter PCIE_USE_MODE = "3.0", // PCIe use mode
parameter PCIE_ASYNC_EN = "FALSE", // PCIe async mode
parameter PCIE_PLL_SEL = "CPLL", // PCIe PLL select for Gen1/Gen2 only
parameter PCIE_AUX_CDR_GEN3_EN = "TRUE", // PCIe AUX CDR Gen3 enable
parameter PCIE_TXBUF_EN = "FALSE", // PCIe TX buffer enable for Gen1/Gen2 only
parameter PCIE_RXBUF_EN = "TRUE", // PCIe RX buffer enable for Gen3 only
parameter PCIE_TXSYNC_MODE = 0, // PCIe TX sync mode
parameter PCIE_RXSYNC_MODE = 0, // PCIe RX sync mode
parameter LOAD_CNT_MAX = 2'd1, // Load max count
parameter INDEX_MAX = 5'd21 // Index max count
)
(
//---------- Input -------------------------------------
input DRP_CLK,
input DRP_RST_N,
input DRP_GTXRESET,
input [ 1:0] DRP_RATE,
input DRP_X16X20_MODE,
input DRP_X16,
input DRP_START,
input [15:0] DRP_DO,
input DRP_RDY,
//---------- Output ------------------------------------
output [ 8:0] DRP_ADDR,
output DRP_EN,
output [15:0] DRP_DI,
output DRP_WE,
output DRP_DONE,
output [ 2:0] DRP_FSM
);
//---------- Input Registers ---------------------------
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg gtxreset_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [ 1:0] rate_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg x16x20_mode_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg x16_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg start_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [15:0] do_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rdy_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg gtxreset_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [ 1:0] rate_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg x16x20_mode_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg x16_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg start_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [15:0] do_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rdy_reg2;
//---------- Internal Signals --------------------------
reg [ 1:0] load_cnt = 2'd0;
reg [ 4:0] index = 5'd0;
reg mode = 1'd0;
reg [ 8:0] addr_reg = 9'd0;
reg [15:0] di_reg = 16'd0;
//---------- Output Registers --------------------------
reg done = 1'd0;
reg [ 2:0] fsm = 0;
//---------- DRP Address -------------------------------
// DRP access for *RXCDR_EIDLE includes
// - [11] RXCDR_HOLD_DURING_EIDLE
// - [12] RXCDR_FR_RESET_ON_EIDLE
// - [13] RXCDR_PH_RESET_ON_EIDLE
//------------------------------------------------------
localparam ADDR_PCS_RSVD_ATTR = 9'h06F;
localparam ADDR_TXOUT_DIV = 9'h088;
localparam ADDR_RXOUT_DIV = 9'h088;
localparam ADDR_TX_DATA_WIDTH = 9'h06B;
localparam ADDR_TX_INT_DATAWIDTH = 9'h06B;
localparam ADDR_RX_DATA_WIDTH = 9'h011;
localparam ADDR_RX_INT_DATAWIDTH = 9'h011;
localparam ADDR_TXBUF_EN = 9'h01C;
localparam ADDR_RXBUF_EN = 9'h09D;
localparam ADDR_TX_XCLK_SEL = 9'h059;
localparam ADDR_RX_XCLK_SEL = 9'h059;
localparam ADDR_CLK_CORRECT_USE = 9'h044;
localparam ADDR_TX_DRIVE_MODE = 9'h019;
localparam ADDR_RXCDR_EIDLE = 9'h0A7;
localparam ADDR_RX_DFE_LPM_EIDLE = 9'h01E;
localparam ADDR_PMA_RSV_A = 9'h099;
localparam ADDR_PMA_RSV_B = 9'h09A;
localparam ADDR_RXCDR_CFG_A = 9'h0A8;
localparam ADDR_RXCDR_CFG_B = 9'h0A9;
localparam ADDR_RXCDR_CFG_C = 9'h0AA;
localparam ADDR_RXCDR_CFG_D = 9'h0AB;
localparam ADDR_RXCDR_CFG_E = 9'h0AC;
localparam ADDR_RXCDR_CFG_F = 9'h0AD; // GTH only
//---------- DRP Mask ----------------------------------
localparam MASK_PCS_RSVD_ATTR = 16'b1111111111111001; // Unmask bit [ 2: 1]
localparam MASK_TXOUT_DIV = 16'b1111111110001111; // Unmask bit [ 6: 4]
localparam MASK_RXOUT_DIV = 16'b1111111111111000; // Unmask bit [ 2: 0]
localparam MASK_TX_DATA_WIDTH = 16'b1111111111111000; // Unmask bit [ 2: 0]
localparam MASK_TX_INT_DATAWIDTH = 16'b1111111111101111; // Unmask bit [ 4]
localparam MASK_RX_DATA_WIDTH = 16'b1100011111111111; // Unmask bit [13:11]
localparam MASK_X16X20_RX_DATA_WIDTH = 16'b1111011111111111; // Unmask bit [ 11] // for x16 or x20 mode only
localparam MASK_RX_INT_DATAWIDTH = 16'b1011111111111111; // Unmask bit [ 14]
localparam MASK_TXBUF_EN = 16'b1011111111111111; // Unmask bit [ 14]
localparam MASK_RXBUF_EN = 16'b1111111111111101; // Unmask bit [ 1]
localparam MASK_TX_XCLK_SEL = 16'b1111111101111111; // Unmask bit [ 7]
localparam MASK_RX_XCLK_SEL = 16'b1111111110111111; // Unmask bit [ 6]
localparam MASK_CLK_CORRECT_USE = 16'b1011111111111111; // Unmask bit [ 14]
localparam MASK_TX_DRIVE_MODE = 16'b1111111111100000; // Unmask bit [ 4:0]
localparam MASK_RXCDR_EIDLE = 16'b1111011111111111; // Unmask bit [ 11]
localparam MASK_RX_DFE_LPM_EIDLE = 16'b1011111111111111; // Unmask bit [ 14]
localparam MASK_PMA_RSV_A = 16'b0000000000000000; // Unmask bit [15: 0]
localparam MASK_PMA_RSV_B = 16'b0000000000000000; // Unmask bit [15: 0]
localparam MASK_RXCDR_CFG_A = 16'b0000000000000000; // Unmask bit [15: 0]
localparam MASK_RXCDR_CFG_B = 16'b0000000000000000; // Unmask bit [15: 0]
localparam MASK_RXCDR_CFG_C = 16'b0000000000000000; // Unmask bit [15: 0]
localparam MASK_RXCDR_CFG_D = 16'b0000000000000000; // Unmask bit [15: 0]
localparam MASK_RXCDR_CFG_E_GTX = 16'b1111111100000000; // Unmask bit [ 7: 0]
localparam MASK_RXCDR_CFG_E_GTH = 16'b0000000000000000; // Unmask bit [15: 0]
localparam MASK_RXCDR_CFG_F_GTX = 16'b1111111111111111; // Unmask bit [ ]
localparam MASK_RXCDR_CFG_F_GTH = 16'b1111111111111000; // Unmask bit [ 2: 0]
//---------- DRP Data for PCIe Gen1 and Gen2 -----------
localparam GEN12_TXOUT_DIV = (PCIE_PLL_SEL == "QPLL") ? 16'b0000000000100000 : 16'b0000000000010000; // Divide by 4 or 2
localparam GEN12_RXOUT_DIV = (PCIE_PLL_SEL == "QPLL") ? 16'b0000000000000010 : 16'b0000000000000001; // Divide by 4 or 2
localparam GEN12_TX_DATA_WIDTH = 16'b0000000000000011; // 2-byte (16-bit) external data width
localparam GEN12_TX_INT_DATAWIDTH = 16'b0000000000000000; // 2-byte (20-bit) internal data width
localparam GEN12_RX_DATA_WIDTH = 16'b0001100000000000; // 2-byte (16-bit) external data width
localparam GEN12_RX_INT_DATAWIDTH = 16'b0000000000000000; // 2-byte (20-bit) internal data width
localparam GEN12_TXBUF_EN = 16'b0100000000000000; // Use TX buffer if PCIE_TXBUF_EN == "TRUE"
localparam GEN12_RXBUF_EN = 16'b0000000000000010; // Use RX buffer
localparam GEN12_TX_XCLK_SEL = 16'b0000000000000000; // Use TXOUT if PCIE_TXBUF_EN == "TRUE"
localparam GEN12_RX_XCLK_SEL = 16'b0000000000000000; // Use RXREC
localparam GEN12_CLK_CORRECT_USE = 16'b0100000000000000; // Use clock correction
localparam GEN12_TX_DRIVE_MODE = 16'b0000000000000001; // Use PIPE Gen1 and Gen2 mode
localparam GEN12_RXCDR_EIDLE = 16'b0000100000000000; // Hold RXCDR during electrical idle
localparam GEN12_RX_DFE_LPM_EIDLE = 16'b0100000000000000; // Hold RX DFE or LPM during electrical idle
localparam GEN12_PMA_RSV_A_GTX = 16'b1000010010000000; // 16'h8480
localparam GEN12_PMA_RSV_B_GTX = 16'b0000000000000001; // 16'h0001
localparam GEN12_PMA_RSV_A_GTH = 16'b0000000000001000; // 16'h0008
localparam GEN12_PMA_RSV_B_GTH = 16'b0000000000000000; // 16'h0000
//----------
localparam GEN12_RXCDR_CFG_A_GTX = 16'h0020; // 16'h0020
localparam GEN12_RXCDR_CFG_B_GTX = 16'h1020; // 16'h1020
localparam GEN12_RXCDR_CFG_C_GTX = 16'h23FF; // 16'h23FF
localparam GEN12_RXCDR_CFG_D_GTX_S = 16'h0000; // 16'h0000 Sync
localparam GEN12_RXCDR_CFG_D_GTX_A = 16'h8000; // 16'h8000 Async
localparam GEN12_RXCDR_CFG_E_GTX = 16'h0003; // 16'h0003
localparam GEN12_RXCDR_CFG_F_GTX = 16'h0000; // 16'h0000
//----------
localparam GEN12_RXCDR_CFG_A_GTH_S = 16'h0018; // 16'h0018 Sync
localparam GEN12_RXCDR_CFG_A_GTH_A = 16'h8018; // 16'h8018 Async
localparam GEN12_RXCDR_CFG_B_GTH = 16'hC208; // 16'hC208
localparam GEN12_RXCDR_CFG_C_GTH = 16'h2000; // 16'h2000
localparam GEN12_RXCDR_CFG_D_GTH = 16'h07FE; // 16'h07FE
localparam GEN12_RXCDR_CFG_E_GTH = 16'h0020; // 16'h0020
localparam GEN12_RXCDR_CFG_F_GTH = 16'h0000; // 16'h0000
//---------- DRP Data for PCIe Gen3 --------------------
localparam GEN3_TXOUT_DIV = 16'b0000000000000000; // Divide by 1
localparam GEN3_RXOUT_DIV = 16'b0000000000000000; // Divide by 1
localparam GEN3_TX_DATA_WIDTH = 16'b0000000000000100; // 4-byte (32-bit) external data width
localparam GEN3_TX_INT_DATAWIDTH = 16'b0000000000010000; // 4-byte (32-bit) internal data width
localparam GEN3_RX_DATA_WIDTH = 16'b0010000000000000; // 4-byte (32-bit) external data width
localparam GEN3_RX_INT_DATAWIDTH = 16'b0100000000000000; // 4-byte (32-bit) internal data width
localparam GEN3_TXBUF_EN = 16'b0000000000000000; // Bypass TX buffer
localparam GEN3_RXBUF_EN = 16'b0000000000000000; // Bypass RX buffer
localparam GEN3_TX_XCLK_SEL = 16'b0000000010000000; // Use TXUSR
localparam GEN3_RX_XCLK_SEL = 16'b0000000001000000; // Use RXUSR
localparam GEN3_CLK_CORRECT_USE = 16'b0000000000000000; // Bypass clock correction
localparam GEN3_TX_DRIVE_MODE = 16'b0000000000000010; // Use PIPE Gen3 mode
localparam GEN3_RXCDR_EIDLE = 16'b0000000000000000; // Disable Hold RXCDR during electrical idle
localparam GEN3_RX_DFE_LPM_EIDLE = 16'b0000000000000000; // Disable RX DFE or LPM during electrical idle
localparam GEN3_PMA_RSV_A_GTX = 16'b0111000010000000; // 16'h7080
localparam GEN3_PMA_RSV_B_GTX = 16'b0000000000011110; // 16'h001E
localparam GEN3_PMA_RSV_A_GTH = 16'b0000000000001000; // 16'h0008
localparam GEN3_PMA_RSV_B_GTH = 16'b0000000000000000; // 16'h0000
//----------
localparam GEN3_RXCDR_CFG_A_GTX = 16'h0080; // 16'h0080
localparam GEN3_RXCDR_CFG_B_GTX = 16'h1010; // 16'h1010
localparam GEN3_RXCDR_CFG_C_GTX = 16'h0BFF; // 16'h0BFF
localparam GEN3_RXCDR_CFG_D_GTX_S = 16'h0000; // 16'h0000 Sync
localparam GEN3_RXCDR_CFG_D_GTX_A = 16'h8000; // 16'h8000 Async
localparam GEN3_RXCDR_CFG_E_GTX = 16'h000B; // 16'h000B
localparam GEN3_RXCDR_CFG_F_GTX = 16'h0000; // 16'h0000
//----------
//localparam GEN3_RXCDR_CFG_A_GTH_S = 16'h0018; // 16'h0018 Sync
//localparam GEN3_RXCDR_CFG_A_GTH_A = 16'h8018; // 16'h8018 Async
//localparam GEN3_RXCDR_CFG_B_GTH = 16'hC208; // 16'hC848
//localparam GEN3_RXCDR_CFG_C_GTH = 16'h2000; // 16'h1000
//localparam GEN3_RXCDR_CFG_D_GTH = 16'h07FE; // 16'h07FE v1.0 silicon
//localparam GEN3_RXCDR_CFG_D_GTH_AUX = 16'h0FFE; // 16'h07FE v2.0 silicon, [62:59] AUX CDR configuration
//localparam GEN3_RXCDR_CFG_E_GTH = 16'h0020; // 16'h0010
//localparam GEN3_RXCDR_CFG_F_GTH = 16'h0000; // 16'h0000 v1.0 silicon
//localparam GEN3_RXCDR_CFG_F_GTH_AUX = 16'h0002; // 16'h0000 v2.0 silicon, [81] AUX CDR enable
//----------
localparam GEN3_RXCDR_CFG_A_GTH_S = 16'h0018; // 16'h0018 Sync
localparam GEN3_RXCDR_CFG_A_GTH_A = 16'h8018; // 16'h8018 Async
localparam GEN3_RXCDR_CFG_B_GTH = 16'hC848; // 16'hC848
localparam GEN3_RXCDR_CFG_C_GTH = 16'h1000; // 16'h1000
localparam GEN3_RXCDR_CFG_D_GTH = 16'h07FE; // 16'h07FE v1.0 silicon
localparam GEN3_RXCDR_CFG_D_GTH_AUX = 16'h0FFE; // 16'h07FE v2.0 silicon, [62:59] AUX CDR configuration
localparam GEN3_RXCDR_CFG_E_GTH = 16'h0010; // 16'h0010
localparam GEN3_RXCDR_CFG_F_GTH = 16'h0000; // 16'h0000 v1.0 silicon
localparam GEN3_RXCDR_CFG_F_GTH_AUX = 16'h0002; // 16'h0000 v2.0 silicon, [81] AUX CDR enable
//---------- DRP Data for PCIe Gen1, Gen2 and Gen3 -----
localparam GEN123_PCS_RSVD_ATTR_A = 16'b0000000000000000; // Auto TX and RX sync mode
localparam GEN123_PCS_RSVD_ATTR_M_TX = 16'b0000000000000010; // Manual TX sync mode
localparam GEN123_PCS_RSVD_ATTR_M_RX = 16'b0000000000000100; // Manual RX sync mode
//---------- DRP Data for x16 --------------------------
localparam X16_RX_DATAWIDTH = 16'b0000000000000000; // 2-byte (16-bit) internal data width
//---------- DRP Data for x20 --------------------------
localparam X20_RX_DATAWIDTH = 16'b0000100000000000; // 2-byte (20-bit) internal data width
//---------- DRP Data ----------------------------------
wire [15:0] data_txout_div;
wire [15:0] data_rxout_div;
wire [15:0] data_tx_data_width;
wire [15:0] data_tx_int_datawidth;
wire [15:0] data_rx_data_width;
wire [15:0] data_rx_int_datawidth;
wire [15:0] data_txbuf_en;
wire [15:0] data_rxbuf_en;
wire [15:0] data_tx_xclk_sel;
wire [15:0] data_rx_xclk_sel;
wire [15:0] data_clk_correction_use;
wire [15:0] data_tx_drive_mode;
wire [15:0] data_rxcdr_eidle;
wire [15:0] data_rx_dfe_lpm_eidle;
wire [15:0] data_pma_rsv_a;
wire [15:0] data_pma_rsv_b;
wire [15:0] data_rxcdr_cfg_a;
wire [15:0] data_rxcdr_cfg_b;
wire [15:0] data_rxcdr_cfg_c;
wire [15:0] data_rxcdr_cfg_d;
wire [15:0] data_rxcdr_cfg_e;
wire [15:0] data_rxcdr_cfg_f;
wire [15:0] data_pcs_rsvd_attr_a;
wire [15:0] data_pcs_rsvd_attr_m_tx;
wire [15:0] data_pcs_rsvd_attr_m_rx;
wire [15:0] data_pcs_rsvd_attr_m;
wire [15:0] data_x16x20_rx_datawidth;
//---------- FSM ---------------------------------------
localparam FSM_IDLE = 0;
localparam FSM_LOAD = 1;
localparam FSM_READ = 2;
localparam FSM_RRDY = 3;
localparam FSM_WRITE = 4;
localparam FSM_WRDY = 5;
localparam FSM_DONE = 6;
//---------- Input FF ----------------------------------------------------------
always @ (posedge DRP_CLK)
begin
if (!DRP_RST_N)
begin
//---------- 1st Stage FF --------------------------
gtxreset_reg1 <= 1'd0;
rate_reg1 <= 2'd0;
x16x20_mode_reg1 <= 1'd0;
x16_reg1 <= 1'd0;
do_reg1 <= 16'd0;
rdy_reg1 <= 1'd0;
start_reg1 <= 1'd0;
//---------- 2nd Stage FF --------------------------
gtxreset_reg2 <= 1'd0;
rate_reg2 <= 2'd0;
x16x20_mode_reg2 <= 1'd0;
x16_reg2 <= 1'd0;
do_reg2 <= 16'd0;
rdy_reg2 <= 1'd0;
start_reg2 <= 1'd0;
end
else
begin
//---------- 1st Stage FF --------------------------
gtxreset_reg1 <= DRP_GTXRESET;
rate_reg1 <= DRP_RATE;
x16x20_mode_reg1 <= DRP_X16X20_MODE;
x16_reg1 <= DRP_X16;
do_reg1 <= DRP_DO;
rdy_reg1 <= DRP_RDY;
start_reg1 <= DRP_START;
//---------- 2nd Stage FF --------------------------
gtxreset_reg2 <= gtxreset_reg1;
rate_reg2 <= rate_reg1;
x16x20_mode_reg2 <= x16x20_mode_reg1;
x16_reg2 <= x16_reg1;
do_reg2 <= do_reg1;
rdy_reg2 <= rdy_reg1;
start_reg2 <= start_reg1;
end
end
//---------- Select DRP Data ---------------------------------------------------
assign data_txout_div = (rate_reg2 == 2'd2) ? GEN3_TXOUT_DIV : GEN12_TXOUT_DIV;
assign data_rxout_div = (rate_reg2 == 2'd2) ? GEN3_RXOUT_DIV : GEN12_RXOUT_DIV;
assign data_tx_data_width = (rate_reg2 == 2'd2) ? GEN3_TX_DATA_WIDTH : GEN12_TX_DATA_WIDTH;
assign data_tx_int_datawidth = (rate_reg2 == 2'd2) ? GEN3_TX_INT_DATAWIDTH : GEN12_TX_INT_DATAWIDTH;
assign data_rx_data_width = (rate_reg2 == 2'd2) ? GEN3_RX_DATA_WIDTH : GEN12_RX_DATA_WIDTH;
assign data_rx_int_datawidth = (rate_reg2 == 2'd2) ? GEN3_RX_INT_DATAWIDTH : GEN12_RX_INT_DATAWIDTH;
assign data_txbuf_en = ((rate_reg2 == 2'd2) || (PCIE_TXBUF_EN == "FALSE")) ? GEN3_TXBUF_EN : GEN12_TXBUF_EN;
assign data_rxbuf_en = ((rate_reg2 == 2'd2) && (PCIE_RXBUF_EN == "FALSE")) ? GEN3_RXBUF_EN : GEN12_RXBUF_EN;
assign data_tx_xclk_sel = ((rate_reg2 == 2'd2) || (PCIE_TXBUF_EN == "FALSE")) ? GEN3_TX_XCLK_SEL : GEN12_TX_XCLK_SEL;
assign data_rx_xclk_sel = ((rate_reg2 == 2'd2) && (PCIE_RXBUF_EN == "FALSE")) ? GEN3_RX_XCLK_SEL : GEN12_RX_XCLK_SEL;
assign data_clk_correction_use = (rate_reg2 == 2'd2) ? GEN3_CLK_CORRECT_USE : GEN12_CLK_CORRECT_USE;
assign data_tx_drive_mode = (rate_reg2 == 2'd2) ? GEN3_TX_DRIVE_MODE : GEN12_TX_DRIVE_MODE;
assign data_rxcdr_eidle = (rate_reg2 == 2'd2) ? GEN3_RXCDR_EIDLE : GEN12_RXCDR_EIDLE;
assign data_rx_dfe_lpm_eidle = (rate_reg2 == 2'd2) ? GEN3_RX_DFE_LPM_EIDLE : GEN12_RX_DFE_LPM_EIDLE;
assign data_pma_rsv_a = (rate_reg2 == 2'd2) ? ((PCIE_GT_DEVICE == "GTH") ? GEN3_PMA_RSV_A_GTH : GEN3_PMA_RSV_A_GTX) :
((PCIE_GT_DEVICE == "GTH") ? GEN12_PMA_RSV_A_GTH : GEN12_PMA_RSV_A_GTX);
assign data_pma_rsv_b = (rate_reg2 == 2'd2) ? ((PCIE_GT_DEVICE == "GTH") ? GEN3_PMA_RSV_B_GTH : GEN3_PMA_RSV_B_GTX) :
((PCIE_GT_DEVICE == "GTH") ? GEN12_PMA_RSV_B_GTH : GEN12_PMA_RSV_B_GTX);
assign data_rxcdr_cfg_a = (rate_reg2 == 2'd2) ? ((PCIE_GT_DEVICE == "GTH") ? ((PCIE_ASYNC_EN == "TRUE") ? GEN3_RXCDR_CFG_A_GTH_A : GEN3_RXCDR_CFG_A_GTH_S) : GEN3_RXCDR_CFG_A_GTX) :
((PCIE_GT_DEVICE == "GTH") ? ((PCIE_ASYNC_EN == "TRUE") ? GEN12_RXCDR_CFG_A_GTH_A : GEN12_RXCDR_CFG_A_GTH_S) : GEN12_RXCDR_CFG_A_GTX);
assign data_rxcdr_cfg_b = (rate_reg2 == 2'd2) ? ((PCIE_GT_DEVICE == "GTH") ? GEN3_RXCDR_CFG_B_GTH : GEN3_RXCDR_CFG_B_GTX) :
((PCIE_GT_DEVICE == "GTH") ? GEN12_RXCDR_CFG_B_GTH : GEN12_RXCDR_CFG_B_GTX);
assign data_rxcdr_cfg_c = (rate_reg2 == 2'd2) ? ((PCIE_GT_DEVICE == "GTH") ? GEN3_RXCDR_CFG_C_GTH : GEN3_RXCDR_CFG_C_GTX) :
((PCIE_GT_DEVICE == "GTH") ? GEN12_RXCDR_CFG_C_GTH : GEN12_RXCDR_CFG_C_GTX);
assign data_rxcdr_cfg_d = (rate_reg2 == 2'd2) ? ((PCIE_GT_DEVICE == "GTH") ? ((PCIE_AUX_CDR_GEN3_EN == "TRUE") ? GEN3_RXCDR_CFG_D_GTH_AUX : GEN3_RXCDR_CFG_D_GTH) : ((PCIE_ASYNC_EN == "TRUE") ? GEN3_RXCDR_CFG_D_GTX_A : GEN3_RXCDR_CFG_D_GTX_S)) :
((PCIE_GT_DEVICE == "GTH") ? GEN12_RXCDR_CFG_D_GTH : ((PCIE_ASYNC_EN == "TRUE") ? GEN3_RXCDR_CFG_D_GTX_A : GEN3_RXCDR_CFG_D_GTX_S));
assign data_rxcdr_cfg_e = (rate_reg2 == 2'd2) ? ((PCIE_GT_DEVICE == "GTH") ? GEN3_RXCDR_CFG_E_GTH : GEN3_RXCDR_CFG_E_GTX) :
((PCIE_GT_DEVICE == "GTH") ? GEN12_RXCDR_CFG_E_GTH : GEN12_RXCDR_CFG_E_GTX);
assign data_rxcdr_cfg_f = (rate_reg2 == 2'd2) ? ((PCIE_GT_DEVICE == "GTH") ? ((PCIE_AUX_CDR_GEN3_EN == "TRUE") ? GEN3_RXCDR_CFG_F_GTH_AUX : GEN3_RXCDR_CFG_F_GTH) : GEN3_RXCDR_CFG_F_GTX) :
((PCIE_GT_DEVICE == "GTH") ? GEN12_RXCDR_CFG_F_GTH : GEN12_RXCDR_CFG_F_GTX);
assign data_pcs_rsvd_attr_a = GEN123_PCS_RSVD_ATTR_A;
assign data_pcs_rsvd_attr_m_tx = PCIE_TXSYNC_MODE ? GEN123_PCS_RSVD_ATTR_A : GEN123_PCS_RSVD_ATTR_M_TX;
assign data_pcs_rsvd_attr_m_rx = PCIE_RXSYNC_MODE ? GEN123_PCS_RSVD_ATTR_A : GEN123_PCS_RSVD_ATTR_M_RX;
assign data_pcs_rsvd_attr_m = data_pcs_rsvd_attr_m_tx | data_pcs_rsvd_attr_m_rx;
assign data_x16x20_rx_datawidth = x16_reg2 ? X16_RX_DATAWIDTH : X20_RX_DATAWIDTH;
//---------- Load Counter ------------------------------------------------------
always @ (posedge DRP_CLK)
begin
if (!DRP_RST_N)
load_cnt <= 2'd0;
else
//---------- Increment Load Counter ----------------
if ((fsm == FSM_LOAD) && (load_cnt < LOAD_CNT_MAX))
load_cnt <= load_cnt + 2'd1;
//---------- Hold Load Counter ---------------------
else if ((fsm == FSM_LOAD) && (load_cnt == LOAD_CNT_MAX))
load_cnt <= load_cnt;
//---------- Reset Load Counter --------------------
else
load_cnt <= 2'd0;
end
//---------- Update DRP Address and Data ---------------------------------------
always @ (posedge DRP_CLK)
begin
if (!DRP_RST_N)
begin
addr_reg <= 9'd0;
di_reg <= 16'd0;
end
else
begin
case (index)
//--------------------------------------------------
5'd0:
begin
addr_reg <= mode ? ADDR_PCS_RSVD_ATTR :
x16x20_mode_reg2 ? ADDR_RX_DATA_WIDTH : ADDR_TXOUT_DIV;
di_reg <= mode ? ((do_reg2 & MASK_PCS_RSVD_ATTR) | data_pcs_rsvd_attr_a) :
x16x20_mode_reg2 ? ((do_reg2 & MASK_X16X20_RX_DATA_WIDTH) | data_x16x20_rx_datawidth) :
((do_reg2 & MASK_TXOUT_DIV) | data_txout_div);
end
//--------------------------------------------------
5'd1:
begin
addr_reg <= mode ? ADDR_PCS_RSVD_ATTR : ADDR_RXOUT_DIV;
di_reg <= mode ? ((do_reg2 & MASK_PCS_RSVD_ATTR) | data_pcs_rsvd_attr_m) :
((do_reg2 & MASK_RXOUT_DIV) | data_rxout_div);
end
//--------------------------------------------------
5'd2 :
begin
addr_reg <= ADDR_TX_DATA_WIDTH;
di_reg <= (do_reg2 & MASK_TX_DATA_WIDTH) | data_tx_data_width;
end
//--------------------------------------------------
5'd3 :
begin
addr_reg <= ADDR_TX_INT_DATAWIDTH;
di_reg <= (do_reg2 & MASK_TX_INT_DATAWIDTH) | data_tx_int_datawidth;
end
//--------------------------------------------------
5'd4 :
begin
addr_reg <= ADDR_RX_DATA_WIDTH;
di_reg <= (do_reg2 & MASK_RX_DATA_WIDTH) | data_rx_data_width;
end
//--------------------------------------------------
5'd5 :
begin
addr_reg <= ADDR_RX_INT_DATAWIDTH;
di_reg <= (do_reg2 & MASK_RX_INT_DATAWIDTH) | data_rx_int_datawidth;
end
//--------------------------------------------------
5'd6 :
begin
addr_reg <= ADDR_TXBUF_EN;
di_reg <= (do_reg2 & MASK_TXBUF_EN) | data_txbuf_en;
end
//--------------------------------------------------
5'd7 :
begin
addr_reg <= ADDR_RXBUF_EN;
di_reg <= (do_reg2 & MASK_RXBUF_EN) | data_rxbuf_en;
end
//--------------------------------------------------
5'd8 :
begin
addr_reg <= ADDR_TX_XCLK_SEL;
di_reg <= (do_reg2 & MASK_TX_XCLK_SEL) | data_tx_xclk_sel;
end
//--------------------------------------------------
5'd9 :
begin
addr_reg <= ADDR_RX_XCLK_SEL;
di_reg <= (do_reg2 & MASK_RX_XCLK_SEL) | data_rx_xclk_sel;
end
//--------------------------------------------------
5'd10 :
begin
addr_reg <= ADDR_CLK_CORRECT_USE;
di_reg <= (do_reg2 & MASK_CLK_CORRECT_USE) | data_clk_correction_use;
end
//--------------------------------------------------
5'd11 :
begin
addr_reg <= ADDR_TX_DRIVE_MODE;
di_reg <= (do_reg2 & MASK_TX_DRIVE_MODE) | data_tx_drive_mode;
end
//--------------------------------------------------
5'd12 :
begin
addr_reg <= ADDR_RXCDR_EIDLE;
di_reg <= (do_reg2 & MASK_RXCDR_EIDLE) | data_rxcdr_eidle;
end
//--------------------------------------------------
5'd13 :
begin
addr_reg <= ADDR_RX_DFE_LPM_EIDLE;
di_reg <= (do_reg2 & MASK_RX_DFE_LPM_EIDLE) | data_rx_dfe_lpm_eidle;
end
//--------------------------------------------------
5'd14 :
begin
addr_reg <= ADDR_PMA_RSV_A;
di_reg <= (do_reg2 & MASK_PMA_RSV_A) | data_pma_rsv_a;
end
//--------------------------------------------------
5'd15 :
begin
addr_reg <= ADDR_PMA_RSV_B;
di_reg <= (do_reg2 & MASK_PMA_RSV_B) | data_pma_rsv_b;
end
//--------------------------------------------------
5'd16 :
begin
addr_reg <= ADDR_RXCDR_CFG_A;
di_reg <= (do_reg2 & MASK_RXCDR_CFG_A) | data_rxcdr_cfg_a;
end
//--------------------------------------------------
5'd17 :
begin
addr_reg <= ADDR_RXCDR_CFG_B;
di_reg <= (do_reg2 & MASK_RXCDR_CFG_B) | data_rxcdr_cfg_b;
end
//--------------------------------------------------
5'd18 :
begin
addr_reg <= ADDR_RXCDR_CFG_C;
di_reg <= (do_reg2 & MASK_RXCDR_CFG_C) | data_rxcdr_cfg_c;
end
//--------------------------------------------------
5'd19 :
begin
addr_reg <= ADDR_RXCDR_CFG_D;
di_reg <= (do_reg2 & MASK_RXCDR_CFG_D) | data_rxcdr_cfg_d;
end
//--------------------------------------------------
5'd20 :
begin
addr_reg <= ADDR_RXCDR_CFG_E;
di_reg <= (do_reg2 & ((PCIE_GT_DEVICE == "GTH") ? MASK_RXCDR_CFG_E_GTH : MASK_RXCDR_CFG_E_GTX)) | data_rxcdr_cfg_e;
end
//--------------------------------------------------
5'd21 :
begin
addr_reg <= ADDR_RXCDR_CFG_F;
di_reg <= (do_reg2 & ((PCIE_GT_DEVICE == "GTH") ? MASK_RXCDR_CFG_F_GTH : MASK_RXCDR_CFG_F_GTX)) | data_rxcdr_cfg_f;
end
//--------------------------------------------------
default :
begin
addr_reg <= 9'd0;
di_reg <= 16'd0;
end
endcase
end
end
//---------- PIPE DRP FSM ------------------------------------------------------
always @ (posedge DRP_CLK)
begin
if (!DRP_RST_N)
begin
fsm <= FSM_IDLE;
index <= 5'd0;
mode <= 1'd0;
done <= 1'd0;
end
else
begin
case (fsm)
//---------- Idle State ----------------------------
FSM_IDLE :
begin
//---------- Reset or Rate Change --------------
if (start_reg2)
begin
fsm <= FSM_LOAD;
index <= 5'd0;
mode <= 1'd0;
done <= 1'd0;
end
//---------- GTXRESET --------------------------
else if ((gtxreset_reg2 && !gtxreset_reg1) && ((PCIE_TXSYNC_MODE == 0) || (PCIE_RXSYNC_MODE == 0)) && (PCIE_USE_MODE == "1.0"))
begin
fsm <= FSM_LOAD;
index <= 5'd0;
mode <= 1'd1;
done <= 1'd0;
end
//---------- Idle ------------------------------
else
begin
fsm <= FSM_IDLE;
index <= 5'd0;
mode <= 1'd0;
done <= 1'd1;
end
end
//---------- Load DRP Address ---------------------
FSM_LOAD :
begin
fsm <= (load_cnt == LOAD_CNT_MAX) ? FSM_READ : FSM_LOAD;
index <= index;
mode <= mode;
done <= 1'd0;
end
//---------- Read DRP ------------------------------
FSM_READ :
begin
fsm <= FSM_RRDY;
index <= index;
mode <= mode;
done <= 1'd0;
end
//---------- Read DRP Ready ------------------------
FSM_RRDY :
begin
fsm <= rdy_reg2 ? FSM_WRITE : FSM_RRDY;
index <= index;
mode <= mode;
done <= 1'd0;
end
//---------- Write DRP -----------------------------
FSM_WRITE :
begin
fsm <= FSM_WRDY;
index <= index;
mode <= mode;
done <= 1'd0;
end
//---------- Write DRP Ready -----------------------
FSM_WRDY :
begin
fsm <= rdy_reg2 ? FSM_DONE : FSM_WRDY;
index <= index;
mode <= mode;
done <= 1'd0;
end
//---------- DRP Done ------------------------------
FSM_DONE :
begin
if ((index == INDEX_MAX) || (mode && (index == 5'd1)) || (x16x20_mode_reg2 && (index == 5'd0)))
begin
fsm <= FSM_IDLE;
index <= 5'd0;
mode <= 1'd0;
done <= 1'd0;
end
else
begin
fsm <= FSM_LOAD;
index <= index + 5'd1;
mode <= mode;
done <= 1'd0;
end
end
//---------- Default State -------------------------
default :
begin
fsm <= FSM_IDLE;
index <= 5'd0;
mode <= 1'd0;
done <= 1'd0;
end
endcase
end
end
//---------- PIPE DRP Output ---------------------------------------------------
assign DRP_ADDR = addr_reg;
assign DRP_EN = (fsm == FSM_READ) || (fsm == FSM_WRITE);
assign DRP_DI = di_reg;
assign DRP_WE = (fsm == FSM_WRITE);
assign DRP_DONE = done;
assign DRP_FSM = fsm;
endmodule
|
module
ghrd_10as066n2 soc_inst (
.pr_handshake_start_req (pr_handshake_start_req),
.pr_handshake_start_ack (pr_handshake_start_req),
.pr_handshake_stop_req (pr_handshake_stop_req),
.pr_handshake_stop_ack (pr_handshake_stop_req),
.f2h_stm_hw_events_stm_hwevents (stm_hw_events),
.pio_dipsw_external_connection_export (fpga_dipsw_pio),
.pio_led_external_connection_in_port (fpga_led_internal),
.pio_led_external_connection_out_port (fpga_led_internal),
.pio_button_external_connection_export (fpga_debounced_buttons),
.hps_io_hps_io_phery_emac0_TX_CLK (hps_emac0_TX_CLK),
.hps_io_hps_io_phery_emac0_TXD0 (hps_emac0_TXD0),
.hps_io_hps_io_phery_emac0_TXD1 (hps_emac0_TXD1),
.hps_io_hps_io_phery_emac0_TXD2 (hps_emac0_TXD2),
.hps_io_hps_io_phery_emac0_TXD3 (hps_emac0_TXD3),
.hps_io_hps_io_phery_emac0_MDIO (hps_emac0_MDIO),
.hps_io_hps_io_phery_emac0_MDC (hps_emac0_MDC),
.hps_io_hps_io_phery_emac0_RX_CTL (hps_emac0_RX_CTL),
.hps_io_hps_io_phery_emac0_TX_CTL (hps_emac0_TX_CTL),
.hps_io_hps_io_phery_emac0_RX_CLK (hps_emac0_RX_CLK),
.hps_io_hps_io_phery_emac0_RXD0 (hps_emac0_RXD0),
.hps_io_hps_io_phery_emac0_RXD1 (hps_emac0_RXD1),
.hps_io_hps_io_phery_emac0_RXD2 (hps_emac0_RXD2),
.hps_io_hps_io_phery_emac0_RXD3 (hps_emac0_RXD3),
.hps_io_hps_io_phery_usb0_DATA0 (hps_usb0_D0),
.hps_io_hps_io_phery_usb0_DATA1 (hps_usb0_D1),
.hps_io_hps_io_phery_usb0_DATA2 (hps_usb0_D2),
.hps_io_hps_io_phery_usb0_DATA3 (hps_usb0_D3),
.hps_io_hps_io_phery_usb0_DATA4 (hps_usb0_D4),
.hps_io_hps_io_phery_usb0_DATA5 (hps_usb0_D5),
.hps_io_hps_io_phery_usb0_DATA6 (hps_usb0_D6),
.hps_io_hps_io_phery_usb0_DATA7 (hps_usb0_D7),
.hps_io_hps_io_phery_usb0_CLK (hps_usb0_CLK),
.hps_io_hps_io_phery_usb0_STP (hps_usb0_STP),
.hps_io_hps_io_phery_usb0_DIR (hps_usb0_DIR),
.hps_io_hps_io_phery_usb0_NXT (hps_usb0_NXT),
.hps_io_hps_io_phery_spim1_CLK (hps_spim1_CLK),
.hps_io_hps_io_phery_spim1_MOSI (hps_spim1_MOSI),
.hps_io_hps_io_phery_spim1_MISO (hps_spim1_MISO),
.hps_io_hps_io_phery_spim1_SS0_N (hps_spim1_SS0_N),
.hps_io_hps_io_phery_spim1_SS1_N (hps_spim1_SS1_N),
.hps_io_hps_io_phery_uart1_RX (hps_uart1_RX),
.hps_io_hps_io_phery_uart1_TX (hps_uart1_TX),
.hps_io_hps_io_phery_sdmmc_CMD (hps_sdio_CMD),
.hps_io_hps_io_phery_sdmmc_D0 (hps_sdio_D0),
.hps_io_hps_io_phery_sdmmc_D1 (hps_sdio_D1),
.hps_io_hps_io_phery_sdmmc_D2 (hps_sdio_D2),
.hps_io_hps_io_phery_sdmmc_D3 (hps_sdio_D3),
.hps_io_hps_io_phery_sdmmc_D4 (hps_sdio_D4),
.hps_io_hps_io_phery_sdmmc_D5 (hps_sdio_D5),
.hps_io_hps_io_phery_sdmmc_D6 (hps_sdio_D6),
.hps_io_hps_io_phery_sdmmc_D7 (hps_sdio_D7),
.hps_io_hps_io_phery_sdmmc_CCLK (hps_sdio_CLK),
.hps_io_hps_io_phery_trace_CLK (hps_trace_CLK),
.hps_io_hps_io_phery_trace_D0 (hps_trace_D0),
.hps_io_hps_io_phery_trace_D1 (hps_trace_D1),
.hps_io_hps_io_phery_trace_D2 (hps_trace_D2),
.hps_io_hps_io_phery_trace_D3 (hps_trace_D3),
.emif_a10_hps_0_mem_conduit_end_mem_ck (hps_memory_mem_ck),
.emif_a10_hps_0_mem_conduit_end_mem_ck_n (hps_memory_mem_ck_n),
.emif_a10_hps_0_mem_conduit_end_mem_a (hps_memory_mem_a),
.emif_a10_hps_0_mem_conduit_end_mem_act_n (hps_memory_mem_act_n),
.emif_a10_hps_0_mem_conduit_end_mem_ba (hps_memory_mem_ba),
.emif_a10_hps_0_mem_conduit_end_mem_bg (hps_memory_mem_bg),
.emif_a10_hps_0_mem_conduit_end_mem_cke (hps_memory_mem_cke),
.emif_a10_hps_0_mem_conduit_end_mem_cs_n (hps_memory_mem_cs_n),
.emif_a10_hps_0_mem_conduit_end_mem_odt (hps_memory_mem_odt),
.emif_a10_hps_0_mem_conduit_end_mem_reset_n (hps_memory_mem_reset_n),
.emif_a10_hps_0_mem_conduit_end_mem_par (hps_memory_mem_par),
.emif_a10_hps_0_mem_conduit_end_mem_alert_n (hps_memory_mem_alert_n),
.emif_a10_hps_0_mem_conduit_end_mem_dqs (hps_memory_mem_dqs),
.emif_a10_hps_0_mem_conduit_end_mem_dqs_n (hps_memory_mem_dqs_n),
.emif_a10_hps_0_mem_conduit_end_mem_dq (hps_memory_mem_dq),
.emif_a10_hps_0_mem_conduit_end_mem_dbi_n (hps_memory_mem_dbi_n),
.emif_a10_hps_0_oct_conduit_end_oct_rzqin (hps_memory_oct_rzqin),
.emif_a10_hps_0_pll_ref_clk_clock_sink_clk (emif_ref_clk),
.hps_io_hps_io_gpio_gpio1_io5 (hps_gpio_GPIO05),
.hps_io_hps_io_gpio_gpio1_io14 (hps_gpio_GPIO14),
.hps_io_hps_io_gpio_gpio1_io16 (hps_gpio_GPIO16),
.hps_io_hps_io_gpio_gpio1_io17 (hps_gpio_GPIO17),
.hps_io_hps_io_phery_i2c1_SDA (hps_i2c1_SDA),
.hps_io_hps_io_phery_i2c1_SCL (hps_i2c1_SCL),
.hps_fpga_reset_reset (hps_fpga_reset),
.issp_hps_resets_source (hps_reset_req),
.f2h_cold_reset_req_reset_n (~hps_cold_reset),
.f2h_warm_reset_req_reset_n (~hps_warm_reset),
.f2h_debug_reset_req_reset_n (~hps_debug_reset),
.reset_reset_n (fpga_reset_n),
.clk_100_clk (fpga_clk_100)
);
// Debounce logic to clean out glitches within 1ms
debounce debounce_inst (
.clk (fpga_clk_100),
.reset_n (~hps_fpga_reset),
.data_in (fpga_button_pio),
.data_out (fpga_debounced_buttons)
);
defparam debounce_inst.WIDTH = 4;
defparam debounce_inst.POLARITY = "LOW";
defparam debounce_inst.TIMEOUT = 100000; // at 100Mhz this is a debounce time of 1ms
defparam debounce_inst.TIMEOUT_WIDTH = 32; // ceil(log2(TIMEOUT))
altera_edge_detector pulse_cold_reset (
.clk (fpga_clk_100),
.rst_n (~hps_fpga_reset),
.signal_in (hps_reset_req[0]),
.pulse_out (hps_cold_reset)
);
defparam pulse_cold_reset.PULSE_EXT = 6;
defparam pulse_cold_reset.EDGE_TYPE = 1;
defparam pulse_cold_reset.IGNORE_RST_WHILE_BUSY = 1;
altera_edge_detector pulse_warm_reset (
.clk (fpga_clk_100),
.rst_n (~hps_fpga_reset),
.signal_in (hps_reset_req[1]),
.pulse_out (hps_warm_reset)
);
defparam pulse_warm_reset.PULSE_EXT = 2;
defparam pulse_warm_reset.EDGE_TYPE = 1;
defparam pulse_warm_reset.IGNORE_RST_WHILE_BUSY = 1;
altera_edge_detector pulse_debug_reset (
.clk (fpga_clk_100),
.rst_n (~hps_fpga_reset),
.signal_in (hps_reset_req[2]),
.pulse_out (hps_debug_reset)
);
defparam pulse_debug_reset.PULSE_EXT = 32;
defparam pulse_debug_reset.EDGE_TYPE = 1;
defparam pulse_debug_reset.IGNORE_RST_WHILE_BUSY = 1;
endmodule
|
module sky130_fd_sc_ls__fahcon (
COUT_N,
SUM ,
A ,
B ,
CI
);
// Module ports
output COUT_N;
output SUM ;
input A ;
input B ;
input CI ;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire xor0_out_SUM ;
wire a_b ;
wire a_ci ;
wire b_ci ;
wire or0_out_coutn;
// Name Output Other arguments
xor xor0 (xor0_out_SUM , A, B, CI );
buf buf0 (SUM , xor0_out_SUM );
nor nor0 (a_b , A, B );
nor nor1 (a_ci , A, CI );
nor nor2 (b_ci , B, CI );
or or0 (or0_out_coutn, a_b, a_ci, b_ci);
buf buf1 (COUT_N , or0_out_coutn );
endmodule
|
module lfsr_count255(
input i_sys_clk,
input i_sys_rst,
output reg o_lfsr_256_done);
reg [7:0] lfsr_reg_i;
wire lfsr_d0_i,lfsr_256_equal_i;
xnor(lfsr_d0_i,lfsr_reg_i[7],lfsr_reg_i[5],lfsr_reg_i[4],lfsr_reg_i[3]);
assign lfsr_256_equal_i = (lfsr_reg_i == 8'h80);
//2D for 100us, 8'h05 for 125us, 8'h10 for 150us, 8'h80 gives 160us
always @(posedge i_sys_clk,posedge i_sys_rst) begin
if(i_sys_rst) begin
lfsr_reg_i <= 0;
o_lfsr_256_done <= 0;
end
else begin
lfsr_reg_i <= lfsr_256_equal_i ? 8'h0 : {lfsr_reg_i[6:0],lfsr_d0_i};
o_lfsr_256_done <= lfsr_256_equal_i;
end
end
endmodule
|
module OSERDES (OQ, SHIFTOUT1, SHIFTOUT2, TQ,
CLK, CLKDIV, D1, D2, D3, D4, D5, D6, OCE, REV, SHIFTIN1, SHIFTIN2, SR, T1, T2, T3, T4, TCE);
parameter DATA_RATE_OQ = "DDR";
parameter DATA_RATE_TQ = "DDR";
parameter integer DATA_WIDTH = 4;
parameter [0:0] INIT_OQ = 1'b0;
parameter [0:0] INIT_TQ = 1'b0;
parameter SERDES_MODE = "MASTER";
parameter [0:0] SRVAL_OQ = 1'b0;
parameter [0:0] SRVAL_TQ = 1'b0;
parameter integer TRISTATE_WIDTH = 4;
`ifdef XIL_TIMING
parameter LOC = "UNPLACED";
`endif
output OQ;
output SHIFTOUT1;
output SHIFTOUT2;
output TQ;
input CLK;
input CLKDIV;
input D1;
input D2;
input D3;
input D4;
input D5;
input D6;
tri0 GSR = glbl.GSR;
input OCE;
input REV;
input SHIFTIN1;
input SHIFTIN2;
input SR;
input T1;
input T2;
input T3;
input T4;
input TCE;
reg c23, c45, c67;
reg t1r, t2r, t3r, t4r;
reg io_sdata_edge, io_odata_edge, io_ddr_data;
reg iot_sdata_edge, iot_odata_edge, iot_ddr_data;
reg data1, data2, data3, data4, data5, data6;
reg serdes_mode_int, serdes_int;
reg data_rate_oq_int, ddr_clk_edge_int;
reg [1:0] data_rate_tq_int, tristate_width_int;
reg [1:0] sel;
reg d1r, d2r, d3r, d4r, d5r, d6r;
reg q0, q1, q2, q3;
reg d1rnk2, d2rnk2, d2nrnk2, d3rnk2, d4rnk2, d5rnk2, d6rnk2;
reg qt1, qt2, qt2n;
reg load, qhr, qlr, mux;
reg data1t, data2t;
reg oq_out = INIT_OQ, tq_out = INIT_TQ;
reg [3:0] data_width_int;
reg notifier;
wire oqsr, oqrev;
wire tqsr, tqrev;
wire c2p, c3;
wire [2:0] sel1_4;
wire [3:0] sel5_6;
wire [4:0] sel_tri;
wire [6:0] seltq;
wire [3:0] seloq;
wire clk_in;
wire clkdiv_in;
wire d1_in;
wire d2_in;
wire d3_in;
wire d4_in;
wire d5_in;
wire d6_in;
wire gsr_in;
wire oce_in;
wire sr_in;
wire rev_in;
wire shiftin1_in;
wire shiftin2_in;
wire t1_in;
wire t2_in;
wire t3_in;
wire t4_in;
wire tce_in;
wire shiftout1_out;
wire shiftout2_out;
buf b_oq (OQ, oq_out);
buf b_shiftout1 (SHIFTOUT1, shiftout1_out);
buf b_shiftout2 (SHIFTOUT2, shiftout2_out);
buf b_tq (TQ, tq_out);
buf b_clk (clk_in, CLK);
buf b_clkdiv (clkdiv_in, CLKDIV);
buf b_d1 (d1_in, D1);
buf b_d2 (d2_in, D2);
buf b_d3 (d3_in, D3);
buf b_d4 (d4_in, D4);
buf b_d5 (d5_in, D5);
buf b_d6 (d6_in, D6);
buf b_gsr (gsr_in, GSR);
buf b_oce (oce_in, OCE);
buf b_r (sr_in, SR);
buf b_s (rev_in, REV);
buf b_shiftin1 (shiftin1_in, SHIFTIN1);
buf b_shiftin2 (shiftin2_in, SHIFTIN2);
buf b_t1 (t1_in, T1);
buf b_t2 (t2_in, T2);
buf b_t3 (t3_in, T3);
buf b_t4 (t4_in, T4);
buf b_tce (tce_in, TCE);
// workaround for XSIM
wire rev_in_AND_NOT_sr_in = rev_in & !sr_in;
wire NOT_rev_in_AND_sr_in = !rev_in & sr_in;
/////////////////////////////////////////////////////////
//
// Delay assignments
//
/////////////////////////////////////////////////////////
// Data output delays
localparam io_ffd = 1; // clock to out delay for flip flops driven by clk
localparam io_ffcd = 1; // clock to out delay for flip flops driven by clkdiv
localparam io_mxd = 1; // 60 ps mux delay
localparam io_mxr1 = 1; // mux before 2nd rank of flops
// Programmable load generator
localparam ffdcnt = 1;
localparam mxdcnt = 1;
// CR 516748
// localparam ffrst = 145; // clock to out delay for flop in PLSG
localparam ffrst = 45; // clock to out delay for flop in PLSG
// Tristate output delays
localparam iot_ffd = 1;
// CR 523601
// localparam iot_mxd = 1;
localparam iot_mxd = 20;
/////////////////////////////////////////////////////////////
always @(gsr_in)
if (gsr_in) begin
assign oq_out = INIT_OQ;
assign d1rnk2 = INIT_OQ;
assign d2rnk2 = INIT_OQ;
assign d2nrnk2 = INIT_OQ;
assign d6rnk2 = 1'b0;
assign d5rnk2 = 1'b0;
assign d4rnk2 = 1'b0;
assign d3rnk2 = 1'b0;
assign d6r = 1'b0;
assign d5r = 1'b0;
assign d4r = 1'b0;
assign d3r = 1'b0;
assign d2r = 1'b0;
assign d1r = 1'b0;
// PLG
assign q3 = 1'b0;
assign q2 = 1'b0;
assign q1 = 1'b0;
assign q0 = 1'b0;
// Tristate output
assign tq_out = INIT_TQ;
assign qt1 = INIT_TQ;
assign qt2 = INIT_TQ;
assign qt2n = INIT_TQ;
assign t4r = 1'b0;
assign t3r = 1'b0;
assign t2r = 1'b0;
assign t1r = 1'b0;
end
else begin
deassign oq_out;
deassign d1rnk2;
deassign d2rnk2;
deassign d2nrnk2;
deassign d6rnk2;
deassign d5rnk2;
deassign d4rnk2;
deassign d3rnk2;
deassign d6r;
deassign d5r;
deassign d4r;
deassign d3r;
deassign d2r;
deassign d1r;
// PLG
deassign q3;
deassign q2;
deassign q1;
deassign q0;
// Tristate output
deassign tq_out;
deassign qt1;
deassign qt2;
deassign qt2n;
deassign t4r;
deassign t3r;
deassign t2r;
deassign t1r;
end
initial begin
case (SERDES_MODE)
"MASTER" : serdes_mode_int <= 1'b0;
"SLAVE" : serdes_mode_int <= 1'b1;
default : begin
$display("Attribute Syntax Error : The attribute SERDES_MODE on OSERDES instance %m is set to %s. Legal values for this attribute are MASTER or SLAVE", SERDES_MODE);
#1 $finish;
end
endcase // case(SERDES_MODE)
serdes_int <= 1'b1; // SERDES = TRUE
ddr_clk_edge_int <= 1'b1; // DDR_CLK_EDGE = SAME_EDGE
case (DATA_RATE_OQ)
"SDR" : data_rate_oq_int <= 1'b1;
"DDR" : data_rate_oq_int <= 1'b0;
default : begin
$display("Attribute Syntax Error : The attribute DATA_RATE_OQ on OSERDES instance %m is set to %s. Legal values for this attribute are SDR or DDR", DATA_RATE_OQ);
#1 $finish;
end
endcase // case(DATA_RATE_OQ)
case (DATA_WIDTH)
2, 3, 4, 5, 6, 7, 8, 10 : data_width_int = DATA_WIDTH[3:0];
default : begin
$display("Attribute Syntax Error : The attribute DATA_WIDTH on OSERDES instance %m is set to %d. Legal values for this attribute are 2, 3, 4, 5, 6, 7, 8, or 10", DATA_WIDTH);
#1 $finish;
end
endcase // case(DATA_WIDTH)
case (DATA_RATE_TQ)
"BUF" : data_rate_tq_int <= 2'b00;
"SDR" : data_rate_tq_int <= 2'b01;
"DDR" : data_rate_tq_int <= 2'b10;
default : begin
$display("Attribute Syntax Error : The attribute DATA_RATE_TQ on OSERDES instance %m is set to %s. Legal values for this attribute are BUF, SDR or DDR", DATA_RATE_TQ);
#1 $finish;
end
endcase // case(DATA_RATE_TQ)
case (TRISTATE_WIDTH)
1 : tristate_width_int <= 2'b00;
2 : tristate_width_int <= 2'b01;
4 : tristate_width_int <= 2'b10;
default : begin
$display("Attribute Syntax Error : The attribute TRISTATE_WIDTH on OSERDES instance %m is set to %d. Legal values for this attribute are 1, 2 or 4", TRISTATE_WIDTH);
#1 $finish;
end
endcase // case(TRISTATE_WIDTH)
end // initial begin
assign shiftout1_out = d3rnk2 & serdes_mode_int;
assign shiftout2_out = d4rnk2 & serdes_mode_int;
assign c2p = (clk_in & ddr_clk_edge_int) | (!clk_in & !ddr_clk_edge_int);
assign c3 = !c2p;
assign sel1_4 = {serdes_int, load, data_rate_oq_int};
assign sel5_6 = {serdes_int, serdes_mode_int, load, data_rate_oq_int};
// Tristate output
assign sel_tri = {load, data_rate_tq_int, tristate_width_int};
assign seloq = {oce_in, data_rate_oq_int, oqsr, oqrev};
assign seltq = {tce_in, data_rate_tq_int, tristate_width_int, tqsr, tqrev};
assign oqsr = (sr_in & !SRVAL_OQ) | (rev_in & SRVAL_OQ);
assign oqrev = (sr_in & SRVAL_OQ) | (rev_in & !SRVAL_OQ);
assign tqsr = (sr_in & !SRVAL_TQ) | (rev_in & SRVAL_TQ);
assign tqrev = (sr_in & SRVAL_TQ) | (rev_in & !SRVAL_TQ);
// 3 flops to create DDR operations of 4 latches
// asynchronous operation
always @ (posedge clk_in or posedge sr_in or posedge rev_in or posedge rev_in_AND_NOT_sr_in or posedge NOT_rev_in_AND_sr_in) begin
if (sr_in == 1'b1 & !(rev_in == 1'b1 & SRVAL_OQ == 1'b1))
d1rnk2 <= # io_ffd SRVAL_OQ;
else if (rev_in == 1'b1)
d1rnk2 <= # io_ffd !SRVAL_OQ;
else if (oce_in == 1'b1)
d1rnk2 <= # io_ffd data1;
else if (oce_in == 1'b0) // to match with HW
d1rnk2 <= # io_ffd oq_out;
end // always @ (posedge clk_in or posedge sr_in or posedge rev_in or posedge rev_in_AND_NOT_sr_in or posedge NOT_rev_in_AND_sr_in)
// Representation of 2nd latch
// asynchronous operation
always @ (posedge c2p or posedge sr_in or posedge rev_in or posedge rev_in_AND_NOT_sr_in or posedge NOT_rev_in_AND_sr_in) begin
if (sr_in == 1'b1 & !(rev_in == 1'b1 & SRVAL_OQ == 1'b1))
d2rnk2 <= # io_ffd SRVAL_OQ;
else if (rev_in == 1'b1)
d2rnk2 <= # io_ffd !SRVAL_OQ;
else if (oce_in == 1'b1)
d2rnk2 <= # io_ffd data2;
else if (oce_in == 1'b0) // to match with HW
d2rnk2 <= # io_ffd oq_out;
end // always @ (posedge c2p or posedge sr_in or posedge rev_in or posedge rev_in_AND_NOT_sr_in or posedge NOT_rev_in_AND_sr_in)
// Representation of 3rd flop ( latch and output latch)
// asynchronous operation
always @ (posedge c3 or posedge sr_in or posedge rev_in or posedge rev_in_AND_NOT_sr_in or posedge NOT_rev_in_AND_sr_in) begin
if (sr_in == 1'b1 & !(rev_in == 1'b1 & SRVAL_OQ == 1'b1))
d2nrnk2 <= # io_ffd SRVAL_OQ;
else if (rev_in == 1'b1)
d2nrnk2 <= # io_ffd !SRVAL_OQ;
else if (oce_in == 1'b1)
d2nrnk2 <= # io_ffd d2rnk2;
else if (oce_in == 1'b0) // to match with HW
d2nrnk2 <= # io_ffd oq_out;
end // always @ (posedge c3 or posedge sr_in or posedge rev_in or posedge rev_in_AND_NOT_sr_in or posedge NOT_rev_in_AND_sr_in)
// last 4 flops which only have reset and init
// asynchronous operation
always @ (posedge clk_in or posedge sr_in) begin
if (sr_in == 1'b1) begin
d3rnk2 <= # io_ffd 1'b0;
d4rnk2 <= # io_ffd 1'b0;
d5rnk2 <= # io_ffd 1'b0;
d6rnk2 <= # io_ffd 1'b0;
end
else begin
d3rnk2 <= # io_ffd data3;
d4rnk2 <= # io_ffd data4;
d5rnk2 <= # io_ffd data5;
d6rnk2 <= # io_ffd data6;
end
end // always @ (posedge clk_in or posedge sr_in)
// First rank of flops for input data
// asynchronous operation
always @ (posedge clkdiv_in or posedge sr_in) begin
if (sr_in == 1'b1) begin
d1r <= # io_ffcd 1'b0;
d2r <= # io_ffcd 1'b0;
d3r <= # io_ffcd 1'b0;
d4r <= # io_ffcd 1'b0;
d5r <= # io_ffcd 1'b0;
d6r <= # io_ffcd 1'b0;
end
else begin
d1r <= # io_ffcd d1_in;
d2r <= # io_ffcd d2_in;
d3r <= # io_ffcd d3_in;
d4r <= # io_ffcd d4_in;
d5r <= # io_ffcd d5_in;
d6r <= # io_ffcd d6_in;
end
end // always @ (posedge clkdiv_in or posedge sr_in)
// Muxs for 2nd rank of flops
always @ (sel1_4 or d1r or d2rnk2 or d3rnk2) begin
casex (sel1_4)
3'b100: data1 <= # io_mxr1 d3rnk2;
3'b110: data1 <= # io_mxr1 d1r;
3'b101: data1 <= # io_mxr1 d2rnk2;
3'b111: data1 <= # io_mxr1 d1r;
default: data1 <= # io_mxr1 d3rnk2;
endcase
end
always @ (sel1_4 or d2r or d3rnk2 or d4rnk2) begin
casex (sel1_4)
3'b100: data2 <= # io_mxr1 d4rnk2;
3'b110: data2 <= # io_mxr1 d2r;
3'b101: data2 <= # io_mxr1 d3rnk2;
3'b111: data2 <= # io_mxr1 d2r;
default: data2 <= # io_mxr1 d4rnk2;
endcase
end
//Note: To stop data rate of 00 from being illegal, register data is fed to mux
always @ (sel1_4 or d3r or d4rnk2 or d5rnk2) begin
casex (sel1_4)
3'b100: data3 <= # io_mxr1 d5rnk2;
3'b110: data3 <= # io_mxr1 d3r;
3'b101: data3 <= # io_mxr1 d4rnk2;
3'b111: data3 <= # io_mxr1 d3r;
default: data3 <= # io_mxr1 d5rnk2;
endcase
end
always @ (sel1_4 or d4r or d5rnk2 or d6rnk2) begin
casex (sel1_4)
3'b100: data4 <= # io_mxr1 d6rnk2;
3'b110: data4 <= # io_mxr1 d4r;
3'b101: data4 <= # io_mxr1 d5rnk2;
3'b111: data4 <= # io_mxr1 d4r;
default: data4 <= # io_mxr1 d6rnk2;
endcase
end
always @ (sel5_6 or d5r or d6rnk2 or shiftin1_in) begin
casex (sel5_6)
4'b1000: data5 <= # io_mxr1 shiftin1_in;
4'b1010: data5 <= # io_mxr1 d5r;
4'b1001: data5 <= # io_mxr1 d6rnk2;
4'b1011: data5 <= # io_mxr1 d5r;
4'b1100: data5 <= # io_mxr1 1'b0;
4'b1110: data5 <= # io_mxr1 d5r;
4'b1101: data5 <= # io_mxr1 d6rnk2;
4'b1111: data5 <= # io_mxr1 d5r;
default: data5 <= # io_mxr1 shiftin1_in;
endcase
end
always @ (sel5_6 or D6 or d6r or shiftin1_in or shiftin2_in) begin
casex (sel5_6)
4'b1000: data6 <= # io_mxr1 shiftin2_in;
4'b1010: data6 <= # io_mxr1 d6r;
4'b1001: data6 <= # io_mxr1 shiftin1_in;
4'b1011: data6 <= # io_mxr1 d6r;
4'b1100: data6 <= # io_mxr1 1'b0;
4'b1110: data6 <= # io_mxr1 d6r;
4'b1101: data6 <= # io_mxr1 1'b0;
4'b1111: data6 <= # io_mxr1 d6r;
default: data6 <= # io_mxr1 shiftin2_in;
endcase
end
// Logic to generate same edge data from d1rnk2 and d2nrnk2;
always @ (clk_in or c3 or d1rnk2 or d2nrnk2) begin
io_sdata_edge <= # io_mxd (d1rnk2 & clk_in) | (d2nrnk2 & c3);
end
// Mux to create opposite edge DDR data from d1rnk2 and d2rnk2
always @(clk_in or d1rnk2 or d2rnk2) begin
case (clk_in)
1'b0: io_odata_edge <= # io_mxd d2rnk2;
1'b1: io_odata_edge <= # io_mxd d1rnk2;
default: io_odata_edge <= # io_mxd d1rnk2;
endcase
end
// Logic to same edge and opposite data into just ddr data
always @(io_sdata_edge or io_odata_edge or ddr_clk_edge_int) begin
io_ddr_data <= # io_mxd (io_odata_edge & !ddr_clk_edge_int) | (io_sdata_edge & ddr_clk_edge_int);
end
// Output mux to generate OQ
always @ (seloq or d1rnk2 or io_ddr_data or oq_out) begin
casex (seloq)
4'bXX01: oq_out <= # io_mxd 1'b1;
4'bXX10: oq_out <= # io_mxd 1'b0;
4'bXX11: oq_out <= # io_mxd 1'b0;
4'b0000: oq_out <= # io_mxd oq_out;
4'b0100: oq_out <= # io_mxd oq_out;
4'b1000: oq_out <= # io_mxd io_ddr_data;
4'b1100: oq_out <= # io_mxd d1rnk2;
default: oq_out <= # io_mxd io_ddr_data;
endcase
end
// Set value of counter in bitslip controller
always @ (data_rate_oq_int or data_width_int) begin
casex ({data_rate_oq_int, data_width_int})
5'b00100: begin c23 <= 1'b0; c45 <= 1'b0; c67 <= 1'b0; sel <= 2'b00; end
5'b00110: begin c23 <= 1'b1; c45 <= 1'b0; c67 <= 1'b0; sel <= 2'b00; end
5'b01000: begin c23 <= 1'b0; c45 <= 1'b0; c67 <= 1'b0; sel <= 2'b01; end
5'b01010: begin c23 <= 1'b0; c45 <= 1'b1; c67 <= 1'b0; sel <= 2'b01; end
5'b10010: begin c23 <= 1'b0; c45 <= 1'b0; c67 <= 1'b0; sel <= 2'b00; end
5'b10011: begin c23 <= 1'b1; c45 <= 1'b0; c67 <= 1'b0; sel <= 2'b00; end
5'b10100: begin c23 <= 1'b0; c45 <= 1'b0; c67 <= 1'b0; sel <= 2'b01; end
5'b10101: begin c23 <= 1'b0; c45 <= 1'b1; c67 <= 1'b0; sel <= 2'b01; end
5'b10110: begin c23 <= 1'b0; c45 <= 1'b0; c67 <= 1'b0; sel <= 2'b10; end
5'b10111: begin c23 <= 1'b0; c45 <= 1'b0; c67 <= 1'b1; sel <= 2'b10; end
5'b11000: begin c23 <= 1'b0; c45 <= 1'b0; c67 <= 1'b0; sel <= 2'b11; end
default: begin
$display("DATA_WIDTH %d and DATA_RATE_OQ %s at time %t ns are illegal.", DATA_WIDTH, DATA_RATE_OQ, $time/1000.0);
$finish;
end
endcase
end // always @ (data_rate_oq_int or data_width_int)
///////////////////////////////////////////////////////////////
// Programmable Load Generator (PLG)
// Divide by 2-8 counter with load enable output
//////////////////////////////////////////////////////////////////
// flops for counter
// asynchronous reset
always @ (posedge qhr or posedge clk_in) begin
if (qhr) begin
q0 <= # ffdcnt 1'b0;
q1 <= # ffdcnt 1'b0;
q2 <= # ffdcnt 1'b0;
q3 <= # ffdcnt 1'b0;
end
else begin
q3 <= # ffdcnt q2;
q2 <= # ffdcnt (!(!q0 & !q2) & q1);
q1 <= # ffdcnt q0;
q0 <= # ffdcnt mux;
end
end // always @ (posedge qhr or posedge clk_in)
// mux settings for counter
always @ (sel or c23 or c45 or c67 or q0 or q1 or q2 or q3) begin
case (sel)
2'b00: mux <= # mxdcnt (!q0 & !(c23 & q1));
2'b01: mux <= # mxdcnt (!q1 & !(c45 & q2));
2'b10: mux <= # mxdcnt (!q2 & !(c67 & q3));
2'b11: mux <= # mxdcnt !q3;
default: mux <= # mxdcnt 1'b0;
endcase
end
// mux decoding for load signal
always @ (sel or c23 or c45 or c67 or q0 or q1 or q2 or q3) begin
case (sel)
2'b00: load <= # mxdcnt q0;
2'b01: load <= # mxdcnt q0 & q1;
2'b10: load <= # mxdcnt q0 & q2;
2'b11: load <= # mxdcnt q0 & q3;
default: load <= # mxdcnt 1'b0;
endcase
end
// flops to reset counter
// Low speed flop
// asynchronous reset
always @ (posedge sr_in or posedge clkdiv_in) begin
if (sr_in == 1'b1)
qlr <= # ffrst 1'b1;
else
qlr <= # ffrst 1'b0;
end // always @ (posedge sr_in or posedge clkdiv_in)
// High speed flop
// asynchronous reset
always @ (posedge sr_in or posedge clk_in) begin
if (sr_in == 1'b1)
qhr <= # ffdcnt 1'b1;
else
qhr <= # ffdcnt qlr;
end // always @ (posedge sr_in or posedge clk_in)
///////////////////////////////////////////////////////
//
// Tristate Output cell
//
////////////////////////////////////////////////////////
// 3 flops to create DDR operations of 4 latches
// Representation of top latch
// asynchronous operation
always @ (posedge clk_in or posedge sr_in or posedge rev_in or posedge rev_in_AND_NOT_sr_in or posedge NOT_rev_in_AND_sr_in) begin
if (sr_in == 1'b1 & !(rev_in == 1'b1 & SRVAL_TQ == 1'b1))
qt1 <= # iot_ffd SRVAL_TQ;
else if (rev_in == 1'b1)
qt1 <= # iot_ffd !SRVAL_TQ;
else if (tce_in == 1'b1)
qt1 <= # iot_ffd data1t;
else if (tce_in == 1'b0)
qt1 <= # iot_ffd tq_out;
end // always @ (posedge clk_in or posedge sr_in or posedge rev_in or posedge rev_in_AND_NOT_sr_in or posedge NOT_rev_in_AND_sr_in)
// Representation of 2nd latch
// asynchronous operation
always @ (posedge c2p or posedge sr_in or posedge rev_in or posedge rev_in_AND_NOT_sr_in or posedge NOT_rev_in_AND_sr_in) begin
if (sr_in == 1'b1 & !(rev_in == 1'b1 & SRVAL_TQ == 1'b1))
qt2 <= # iot_ffd SRVAL_TQ;
else if (rev_in == 1'b1)
qt2 <= # iot_ffd !SRVAL_TQ;
else if (tce_in == 1'b1)
qt2 <= # iot_ffd data2t;
else if (tce_in == 1'b0)
qt2 <= # iot_ffd tq_out;
end // always @ (posedge c2p or posedge sr_in or posedge rev_in or posedge rev_in_AND_NOT_sr_in or posedge NOT_rev_in_AND_sr_in)
// Representation of 3rd flop ( latch and output latch)
// asynchronous operation
always @ (posedge c3 or posedge sr_in or posedge rev_in or posedge rev_in_AND_NOT_sr_in or posedge NOT_rev_in_AND_sr_in) begin
if (sr_in == 1'b1 & !(rev_in == 1'b1 & SRVAL_TQ == 1'b1))
qt2n <= # iot_ffd SRVAL_TQ;
else if (rev_in == 1'b1)
qt2n <= # iot_ffd !SRVAL_TQ;
else if (tce_in == 1'b1)
qt2n <= # iot_ffd qt2;
else if (tce_in == 1'b0)
qt2n <= # iot_ffd tq_out;
end // always @ (posedge c3 or posedge sr_in or posedge rev_in or posedge rev_in_AND_NOT_sr_in or posedge NOT_rev_in_AND_sr_in)
// First rank of flops
// asynchronous reset operation
always @ (posedge clkdiv_in or posedge sr_in) begin
if (sr_in == 1'b1) begin
t1r <= # iot_ffd 1'b0;
t2r <= # iot_ffd 1'b0;
t3r <= # iot_ffd 1'b0;
t4r <= # iot_ffd 1'b0;
end
else begin
t1r <= # iot_ffd t1_in;
t2r <= # iot_ffd t2_in;
t3r <= # iot_ffd t3_in;
t4r <= # iot_ffd t4_in;
end
end // always @ (posedge clkdiv_in or posedge sr_in)
// Data Muxs for tristate otuput signals
always @ (sel_tri or t1_in or t1r or t3r) begin
casex (sel_tri)
5'b00000: data1t <= # iot_mxd t1_in;
5'b10000: data1t <= # iot_mxd t1_in;
5'bX0000: data1t <= # iot_mxd t1_in;
5'b00100: data1t <= # iot_mxd t1_in;
5'b10100: data1t <= # iot_mxd t1_in;
5'bX0100: data1t <= # iot_mxd t1_in;
5'b01001: data1t <= # iot_mxd t1_in;
5'b11001: data1t <= # iot_mxd t1_in;
5'b01010: data1t <= # iot_mxd t3r;
5'b11010: data1t <= # iot_mxd t1r;
// CR 458156 -- allow/enabled TRISTATE_WIDTH to be 1 in DDR mode. No func change, but removed warnings
5'b01000: ;
5'b11000: ;
5'bX1000: ;
default: begin
$display("DATA_RATE_TQ %s and/or TRISTATE_WIDTH %d at time %t ns are not supported by OSERDES", DATA_RATE_TQ, TRISTATE_WIDTH, $time/1000.0);
$finish;
end
endcase
end
// For data 2, width of 1 is inserted as acceptable for buf and sdr
// The capability exists in the device if the feature is added
always @ (sel_tri or t2_in or t2r or t4r) begin
casex (sel_tri)
5'b00000: data2t <= # iot_mxd t2_in;
5'b00100: data2t <= # iot_mxd t2_in;
5'b10000: data2t <= # iot_mxd t2_in;
5'b10100: data2t <= # iot_mxd t2_in;
5'bX0000: data2t <= # iot_mxd t2_in;
5'bX0100: data2t <= # iot_mxd t2_in;
5'b00X00: data2t <= # iot_mxd t2_in;
5'b10X00: data2t <= # iot_mxd t2_in;
5'bX0X00: data2t <= # iot_mxd t2_in;
5'b01001: data2t <= # iot_mxd t2_in;
5'b11001: data2t <= # iot_mxd t2_in;
5'bX1001: data2t <= # iot_mxd t2_in;
5'b01010: data2t <= # iot_mxd t4r;
5'b11010: data2t <= # iot_mxd t2r;
// CR 458156 -- allow/enabled TRISTATE_WIDTH to be 1 in DDR mode. No func change, but removed warnings
5'b01000: ;
5'b11000: ;
5'bX1000: ;
default: begin
$display("DATA_RATE_TQ %s and/or TRISTATE_WIDTH %d at time %t ns are not supported by OSERDES", DATA_RATE_TQ, TRISTATE_WIDTH, $time/1000.0);
$finish;
end
endcase
end
// Logic to generate same edge data from qt1, qt3;
always @ (clk_in or c3 or qt1 or qt2n) begin
iot_sdata_edge <= # iot_mxd (qt1 & clk_in) | (qt2n & c3);
end
// Mux to create opposite edge DDR function
always @ (clk_in or qt1 or qt2) begin
case (clk_in)
1'b0: iot_odata_edge <= # iot_mxd qt2;
1'b1: iot_odata_edge <= # iot_mxd qt1;
default: iot_odata_edge <= 1'b0;
endcase
end
// Logic to same edge and opposite data into just ddr data
always @ (iot_sdata_edge or iot_odata_edge or ddr_clk_edge_int) begin
iot_ddr_data <= # iot_mxd (iot_odata_edge & !ddr_clk_edge_int) | (iot_sdata_edge & ddr_clk_edge_int);
end
// Output mux to generate TQ
// Note that the TQ mux can also support T2 combinatorial or
// registered outputs. Those modes are not support in this model.
always @ (seltq or data1t or iot_ddr_data or qt1 or tq_out) begin
casex (seltq)
7'bX01XX01: tq_out <= # iot_mxd 1'b1;
7'bX10XX01: tq_out <= # iot_mxd 1'b1;
7'bX01XX10: tq_out <= # iot_mxd 1'b0;
7'bX10XX10: tq_out <= # iot_mxd 1'b0;
7'bX01XX11: tq_out <= # iot_mxd 1'b0;
7'bX10XX11: tq_out <= # iot_mxd 1'b0;
7'bX0000XX: tq_out <= # iot_mxd data1t;
7'b0010000: tq_out <= # iot_mxd tq_out;
7'b0100100: tq_out <= # iot_mxd tq_out;
7'b0101000: tq_out <= # iot_mxd tq_out;
7'b1010000: tq_out <= # iot_mxd qt1;
7'b1100100: tq_out <= # iot_mxd iot_ddr_data;
7'b1101000: tq_out <= # iot_mxd iot_ddr_data;
default: tq_out <= # iot_mxd iot_ddr_data;
endcase
end
//*** Timing Checks Start here
`ifndef XIL_TIMING
assign clk_in = CLK;
assign oce_in = OCE;
assign tce_in = TCE;
assign clkdiv_in = CLKDIV;
assign d1_in = D1;
assign d2_in = D2;
assign d3_in = D3;
assign d4_in = D4;
assign d5_in = D5;
assign d6_in = D6;
assign rev_in = REV;
assign sr_in = SR;
assign t1_in = T1;
assign t2_in = T2;
assign t3_in = T3;
assign t4_in = T4;
`endif
specify
(CLK => OQ) = (100:100:100, 100:100:100);
(CLK => TQ) = (100:100:100, 100:100:100);
`ifdef XIL_TIMING
(SR => OQ) = (0:0:0, 0:0:0);
(REV => OQ) = (0:0:0, 0:0:0);
(T1 => TQ) = (0:0:0, 0:0:0);
(SR => TQ) = (0:0:0, 0:0:0);
(REV => TQ) = (0:0:0, 0:0:0);
$setuphold (posedge CLKDIV, posedge D1, 0:0:0, 0:0:0, notifier, , , clkdiv_in, d1_in);
$setuphold (posedge CLKDIV, negedge D1, 0:0:0, 0:0:0, notifier, , , clkdiv_in, d1_in);
$setuphold (posedge CLKDIV, posedge D2, 0:0:0, 0:0:0, notifier, , , clkdiv_in, d2_in);
$setuphold (posedge CLKDIV, negedge D2, 0:0:0, 0:0:0, notifier, , , clkdiv_in, d2_in);
$setuphold (posedge CLKDIV, posedge D3, 0:0:0, 0:0:0, notifier, , , clkdiv_in, d3_in);
$setuphold (posedge CLKDIV, negedge D3, 0:0:0, 0:0:0, notifier, , , clkdiv_in, d3_in);
$setuphold (posedge CLKDIV, posedge D4, 0:0:0, 0:0:0, notifier, , , clkdiv_in, d4_in);
$setuphold (posedge CLKDIV, negedge D4, 0:0:0, 0:0:0, notifier, , , clkdiv_in, d4_in);
$setuphold (posedge CLKDIV, posedge D5, 0:0:0, 0:0:0, notifier, , , clkdiv_in, d5_in);
$setuphold (posedge CLKDIV, negedge D5, 0:0:0, 0:0:0, notifier, , , clkdiv_in, d5_in);
$setuphold (posedge CLKDIV, posedge D6, 0:0:0, 0:0:0, notifier, , , clkdiv_in, d6_in);
$setuphold (posedge CLKDIV, negedge D6, 0:0:0, 0:0:0, notifier, , , clkdiv_in, d6_in);
$setuphold (posedge CLK, posedge T1, 0:0:0, 0:0:0, notifier, , , clk_in, t1_in);
$setuphold (posedge CLK, negedge T1, 0:0:0, 0:0:0, notifier, , , clk_in, t1_in);
$setuphold (posedge CLK, posedge T2, 0:0:0, 0:0:0, notifier, , , clk_in, t2_in);
$setuphold (posedge CLK, negedge T2, 0:0:0, 0:0:0, notifier, , , clk_in, t2_in);
$setuphold (posedge CLKDIV, posedge T1, 0:0:0, 0:0:0, notifier, , , clkdiv_in, t1_in);
$setuphold (posedge CLKDIV, negedge T1, 0:0:0, 0:0:0, notifier, , , clkdiv_in, t1_in);
$setuphold (posedge CLKDIV, posedge T2, 0:0:0, 0:0:0, notifier, , , clkdiv_in, t2_in);
$setuphold (posedge CLKDIV, negedge T2, 0:0:0, 0:0:0, notifier, , , clkdiv_in, t2_in);
$setuphold (posedge CLKDIV, posedge T3, 0:0:0, 0:0:0, notifier, , , clkdiv_in, t3_in);
$setuphold (posedge CLKDIV, negedge T3, 0:0:0, 0:0:0, notifier, , , clkdiv_in, t3_in);
$setuphold (posedge CLKDIV, posedge T4, 0:0:0, 0:0:0, notifier, , , clkdiv_in, t4_in);
$setuphold (posedge CLKDIV, negedge T4, 0:0:0, 0:0:0, notifier, , , clkdiv_in, t4_in);
$setuphold (posedge CLK, posedge OCE, 0:0:0, 0:0:0, notifier, , , clk_in, oce_in);
$setuphold (posedge CLK, negedge OCE, 0:0:0, 0:0:0, notifier, , , clk_in, oce_in);
$setuphold (negedge CLK, posedge OCE, 0:0:0, 0:0:0, notifier, , , clk_in, oce_in);
$setuphold (negedge CLK, negedge OCE, 0:0:0, 0:0:0, notifier, , , clk_in, oce_in);
$setuphold (posedge CLK, posedge TCE, 0:0:0, 0:0:0, notifier, , , clk_in, tce_in);
$setuphold (posedge CLK, negedge TCE, 0:0:0, 0:0:0, notifier, , , clk_in, tce_in);
$setuphold (negedge CLK, posedge TCE, 0:0:0, 0:0:0, notifier, , , clk_in, tce_in);
$setuphold (negedge CLK, negedge TCE, 0:0:0, 0:0:0, notifier, , , clk_in, tce_in);
$period (posedge CLK, 0:0:0, notifier);
$period (posedge CLKDIV, 0:0:0, notifier);
$recrem (negedge REV, posedge CLK, 0:0:0, 0:0:0, notifier);
$recrem (negedge SR, posedge CLK, 0:0:0, 0:0:0, notifier);
$recrem (negedge SR, posedge CLKDIV, 0:0:0, 0:0:0, notifier);
// CR 232324
$setuphold (posedge CLKDIV, posedge REV, 0:0:0, 0:0:0, notifier, , , clkdiv_in, rev_in);
$setuphold (posedge CLKDIV, negedge REV, 0:0:0, 0:0:0, notifier, , , clkdiv_in, rev_in);
$setuphold (negedge CLKDIV, posedge REV, 0:0:0, 0:0:0, notifier, , , clkdiv_in, rev_in);
$setuphold (negedge CLKDIV, negedge REV, 0:0:0, 0:0:0, notifier, , , clkdiv_in, rev_in);
$setuphold (posedge CLKDIV, posedge SR, 0:0:0, 0:0:0, notifier, , , clkdiv_in, sr_in);
$setuphold (posedge CLKDIV, negedge SR, 0:0:0, 0:0:0, notifier, , , clkdiv_in, sr_in);
$setuphold (negedge CLKDIV, posedge SR, 0:0:0, 0:0:0, notifier, , , clkdiv_in, sr_in);
$setuphold (negedge CLKDIV, negedge SR, 0:0:0, 0:0:0, notifier, , , clkdiv_in, sr_in);
// CR 210819
$setuphold (negedge CLK, posedge T1, 0:0:0, 0:0:0, notifier, , , clk_in, t1_in);
$setuphold (negedge CLK, negedge T1, 0:0:0, 0:0:0, notifier, , , clk_in, t1_in);
$setuphold (negedge CLK, posedge T2, 0:0:0, 0:0:0, notifier, , , clk_in, t2_in);
$setuphold (negedge CLK, negedge T2, 0:0:0, 0:0:0, notifier, , , clk_in, t2_in);
$recrem (negedge REV, negedge CLK, 0:0:0, 0:0:0, notifier);
$recrem (negedge SR, negedge CLK, 0:0:0, 0:0:0, notifier);
$width (posedge CLK, 0:0:0, 0, notifier);
$width (posedge CLKDIV, 0:0:0, 0, notifier);
$width (negedge CLK, 0:0:0, 0, notifier);
$width (negedge CLKDIV, 0:0:0, 0, notifier);
`endif
specparam PATHPULSE$ = 0;
endspecify
endmodule
|
module zeowaa
(
input clk_50,
input [ 5:2] key,
input [ 7:0] sw,
output [11:0] led,
output [ 7:0] hex,
output [ 7:0] digit,
output buzzer
);
// wires & inputs
wire clkCpu;
wire clkIn = clk_50;
wire rst_n = key[4];
wire clkEnable = ~sw[ 7] | ~key[5];
wire [ 3:0 ] clkDevide = { ~sw[6:5], 2'b00 };
wire [ 4:0 ] regAddr = ~sw[4:0];
wire [ 31:0 ] regData;
//cores
sm_top sm_top
(
.clkIn ( clkIn ),
.rst_n ( rst_n ),
.clkDevide ( clkDevide ),
.clkEnable ( clkEnable ),
.clk ( clkCpu ),
.regAddr ( regAddr ),
.regData ( regData )
);
//outputs
assign led[0] = ~clkCpu;
assign led[11:1] = ~regData[11:0];
//hex out
wire [ 31:0 ] h7segment = regData;
wire clkHex;
sm_clk_divider hex_clk_divider
(
.clkIn ( clkIn ),
.rst_n ( rst_n ),
.devide ( 4'b0 ),
.enable ( 1'b1 ),
.clkOut ( clkHex )
);
sm_hex_display_8 sm_hex_display_8
(
.clock ( clkHex ),
.resetn ( rst_n ),
.number ( h7segment ),
.seven_segments ( hex[6:0] ),
.dot ( hex[7] ),
.anodes ( digit )
);
assign buzzer = 1'b1;
endmodule
|
module txc_engine_classic
#(
parameter C_PCI_DATA_WIDTH = 128,
parameter C_PIPELINE_INPUT = 1,
parameter C_PIPELINE_OUTPUT = 0,
parameter C_MAX_PAYLOAD_DWORDS = 64,
parameter C_DEPTH_PACKETS = 10,
parameter C_VENDOR = "ALTERA"
)
(
// Interface: Clocks
input CLK,
// Interface: Resets
input RST_IN,
// Interface: Configuration
input [`SIG_CPLID_W-1:0] CONFIG_COMPLETER_ID,
// Interface: TXC Classic
input TXC_TLP_READY,
output [C_PCI_DATA_WIDTH-1:0] TXC_TLP,
output TXC_TLP_VALID,
output TXC_TLP_START_FLAG,
output [clog2s(C_PCI_DATA_WIDTH/32)-1:0] TXC_TLP_START_OFFSET,
output TXC_TLP_END_FLAG,
output [clog2s(C_PCI_DATA_WIDTH/32)-1:0] TXC_TLP_END_OFFSET,
// Interface: TXC Engine
input TXC_DATA_VALID,
input [C_PCI_DATA_WIDTH-1:0] TXC_DATA,
input TXC_DATA_START_FLAG,
input [clog2s(C_PCI_DATA_WIDTH/32)-1:0] TXC_DATA_START_OFFSET,
input TXC_DATA_END_FLAG,
input [clog2s(C_PCI_DATA_WIDTH/32)-1:0] TXC_DATA_END_OFFSET,
output TXC_DATA_READY,
input TXC_META_VALID,
input [`SIG_FBE_W-1:0] TXC_META_FDWBE,
input [`SIG_LBE_W-1:0] TXC_META_LDWBE,
input [`SIG_LOWADDR_W-1:0] TXC_META_ADDR,
input [`SIG_TYPE_W-1:0] TXC_META_TYPE,
input [`SIG_LEN_W-1:0] TXC_META_LENGTH,
input [`SIG_BYTECNT_W-1:0] TXC_META_BYTE_COUNT,
input [`SIG_TAG_W-1:0] TXC_META_TAG,
input [`SIG_REQID_W-1:0] TXC_META_REQUESTER_ID,
input [`SIG_TC_W-1:0] TXC_META_TC,
input [`SIG_ATTR_W-1:0] TXC_META_ATTR,
input TXC_META_EP,
output TXC_META_READY);
`include "functions.vh"
localparam C_DATA_WIDTH = C_PCI_DATA_WIDTH;
localparam C_MAX_HDR_WIDTH = `TLP_MAXHDR_W;
localparam C_MAX_ALIGN_WIDTH = (C_VENDOR == "ALTERA") ? 32:
(C_VENDOR == "XILINX") ? 0 :
0;
localparam C_PIPELINE_FORMATTER_INPUT = C_PIPELINE_INPUT;
localparam C_PIPELINE_FORMATTER_OUTPUT = C_PIPELINE_OUTPUT;
localparam C_FORMATTER_DELAY = C_PIPELINE_FORMATTER_OUTPUT + C_PIPELINE_FORMATTER_INPUT;
/*AUTOWIRE*/
/*AUTOINPUT*/
///*AUTOOUTPUT*/
wire wTxHdrReady;
wire wTxHdrValid;
wire [C_MAX_HDR_WIDTH-1:0] wTxHdr;
wire [`SIG_TYPE_W-1:0] wTxType;
wire [`SIG_NONPAY_W-1:0] wTxHdrNonpayLen;
wire [`SIG_PACKETLEN_W-1:0] wTxHdrPacketLen;
wire [`SIG_LEN_W-1:0] wTxHdrPayloadLen;
wire wTxHdrNopayload;
txc_formatter_classic
#(
.C_PIPELINE_OUTPUT (C_PIPELINE_FORMATTER_OUTPUT),
.C_PIPELINE_INPUT (C_PIPELINE_FORMATTER_INPUT),
/*AUTOINSTPARAM*/
// Parameters
.C_PCI_DATA_WIDTH (C_PCI_DATA_WIDTH),
.C_MAX_HDR_WIDTH (C_MAX_HDR_WIDTH),
.C_MAX_ALIGN_WIDTH (C_MAX_ALIGN_WIDTH),
.C_VENDOR (C_VENDOR))
txc_formatter_inst
(
// Outputs
.TX_HDR_VALID (wTxHdrValid),
.TX_HDR (wTxHdr[C_MAX_HDR_WIDTH-1:0]),
.TX_HDR_NOPAYLOAD (wTxHdrNopayload),
.TX_HDR_PAYLOAD_LEN (wTxHdrPayloadLen[`SIG_LEN_W-1:0]),
.TX_HDR_NONPAY_LEN (wTxHdrNonpayLen[`SIG_NONPAY_W-1:0]),
.TX_HDR_PACKET_LEN (wTxHdrPacketLen[`SIG_PACKETLEN_W-1:0]),
// Inputs
.TX_HDR_READY (wTxHdrReady),
/*AUTOINST*/
// Outputs
.TXC_META_READY (TXC_META_READY),
// Inputs
.CLK (CLK),
.RST_IN (RST_IN),
.CONFIG_COMPLETER_ID (CONFIG_COMPLETER_ID[`SIG_CPLID_W-1:0]),
.TXC_META_VALID (TXC_META_VALID),
.TXC_META_FDWBE (TXC_META_FDWBE[`SIG_FBE_W-1:0]),
.TXC_META_LDWBE (TXC_META_LDWBE[`SIG_LBE_W-1:0]),
.TXC_META_ADDR (TXC_META_ADDR[`SIG_LOWADDR_W-1:0]),
.TXC_META_LENGTH (TXC_META_LENGTH[`SIG_LEN_W-1:0]),
.TXC_META_BYTE_COUNT (TXC_META_BYTE_COUNT[`SIG_BYTECNT_W-1:0]),
.TXC_META_TAG (TXC_META_TAG[`SIG_TAG_W-1:0]),
.TXC_META_TYPE (TXC_META_TYPE[`SIG_TYPE_W-1:0]),
.TXC_META_REQUESTER_ID (TXC_META_REQUESTER_ID[`SIG_REQID_W-1:0]),
.TXC_META_TC (TXC_META_TC[`SIG_TC_W-1:0]),
.TXC_META_ATTR (TXC_META_ATTR[`SIG_ATTR_W-1:0]),
.TXC_META_EP (TXC_META_EP));
tx_engine
#(
.C_DATA_WIDTH (C_PCI_DATA_WIDTH),
/*AUTOINSTPARAM*/
// Parameters
.C_DEPTH_PACKETS (C_DEPTH_PACKETS),
.C_PIPELINE_INPUT (C_PIPELINE_INPUT),
.C_PIPELINE_OUTPUT (C_PIPELINE_OUTPUT),
.C_FORMATTER_DELAY (C_FORMATTER_DELAY),
.C_MAX_HDR_WIDTH (C_MAX_HDR_WIDTH),
.C_MAX_PAYLOAD_DWORDS (C_MAX_PAYLOAD_DWORDS),
.C_VENDOR (C_VENDOR))
txc_engine_inst
(
// Outputs
.TX_HDR_READY (wTxHdrReady),
.TX_DATA_READY (TXC_DATA_READY),
.TX_PKT (TXC_TLP[C_DATA_WIDTH-1:0]),
.TX_PKT_START_FLAG (TXC_TLP_START_FLAG),
.TX_PKT_START_OFFSET (TXC_TLP_START_OFFSET[clog2s(C_DATA_WIDTH/32)-1:0]),
.TX_PKT_END_FLAG (TXC_TLP_END_FLAG),
.TX_PKT_END_OFFSET (TXC_TLP_END_OFFSET[clog2s(C_DATA_WIDTH/32)-1:0]),
.TX_PKT_VALID (TXC_TLP_VALID),
// Inputs
.TX_HDR_VALID (wTxHdrValid),
.TX_HDR (wTxHdr[C_MAX_HDR_WIDTH-1:0]),
.TX_HDR_NOPAYLOAD (wTxHdrNopayload),
.TX_HDR_PAYLOAD_LEN (wTxHdrPayloadLen[`SIG_LEN_W-1:0]),
.TX_HDR_NONPAY_LEN (wTxHdrNonpayLen[`SIG_NONPAY_W-1:0]),
.TX_HDR_PACKET_LEN (wTxHdrPacketLen[`SIG_PACKETLEN_W-1:0]),
.TX_DATA_VALID (TXC_DATA_VALID),
.TX_DATA (TXC_DATA[C_DATA_WIDTH-1:0]),
.TX_DATA_START_FLAG (TXC_DATA_START_FLAG),
.TX_DATA_START_OFFSET (TXC_DATA_START_OFFSET[clog2s(C_DATA_WIDTH/32)-1:0]),
.TX_DATA_END_FLAG (TXC_DATA_END_FLAG),
.TX_DATA_END_OFFSET (TXC_DATA_END_OFFSET[clog2s(C_DATA_WIDTH/32)-1:0]),
.TX_PKT_READY (TXC_TLP_READY),
/*AUTOINST*/
// Inputs
.CLK (CLK),
.RST_IN (RST_IN));
endmodule
|
module txc_formatter_classic
#(
parameter C_PCI_DATA_WIDTH = 10'd128,
parameter C_MAX_HDR_WIDTH = `TLP_MAXHDR_W,
parameter C_MAX_ALIGN_WIDTH = 32,
parameter C_PIPELINE_INPUT = 1,
parameter C_PIPELINE_OUTPUT = 1,
parameter C_VENDOR = "ALTERA"
)
(
// Interface: Clocks
input CLK,
// Interface: Resets
input RST_IN,
// Interface: Configuration
input [`SIG_CPLID_W-1:0] CONFIG_COMPLETER_ID,
// Interface: TXC
input TXC_META_VALID,
input [`SIG_FBE_W-1:0] TXC_META_FDWBE,
input [`SIG_LBE_W-1:0] TXC_META_LDWBE,
input [`SIG_LOWADDR_W-1:0] TXC_META_ADDR,
input [`SIG_LEN_W-1:0] TXC_META_LENGTH,
input [`SIG_BYTECNT_W-1:0] TXC_META_BYTE_COUNT,
input [`SIG_TAG_W-1:0] TXC_META_TAG,
input [`SIG_TYPE_W-1:0] TXC_META_TYPE,
input [`SIG_REQID_W-1:0] TXC_META_REQUESTER_ID,
input [`SIG_TC_W-1:0] TXC_META_TC,
input [`SIG_ATTR_W-1:0] TXC_META_ATTR,
input TXC_META_EP,
output TXC_META_READY,
// Interface: TX HDR
output TX_HDR_VALID,
output [C_MAX_HDR_WIDTH-1:0] TX_HDR,
output [`SIG_LEN_W-1:0] TX_HDR_PAYLOAD_LEN,
output [`SIG_NONPAY_W-1:0] TX_HDR_NONPAY_LEN,
output [`SIG_PACKETLEN_W-1:0] TX_HDR_PACKET_LEN,
output TX_HDR_NOPAYLOAD,
input TX_HDR_READY
);
`include "functions.vh"
wire [C_MAX_HDR_WIDTH-1:0] wCplHdr;
wire wTxHdrReady;
wire wTxHdrValid;
wire [C_MAX_HDR_WIDTH-1:0] wTxHdr;
wire [`SIG_TYPE_W-1:0] wTxType;
wire [`SIG_NONPAY_W-1:0] wTxHdrNonpayLen;
wire [`SIG_PACKETLEN_W-1:0] wTxHdrPacketLen;
wire [`SIG_LEN_W-1:0] wTxHdrPayloadLen;
wire wTxHdrNopayload;
wire [`TLP_CPLADDR_W-1:0] wTxLoAddr;
// Reserved Fields
assign wCplHdr[`TLP_RSVD0_R] = `TLP_RSVD0_V;
assign wCplHdr[`TLP_ADDRTYPE_R] = `TLP_ADDRTYPE_W'b0;
assign wCplHdr[`TLP_TH_R] = `TLP_TH_W'b0;
assign wCplHdr[`TLP_RSVD1_R] = `TLP_RSVD1_V;
assign wCplHdr[`TLP_RSVD2_R] = `TLP_RSVD2_V;
assign wCplHdr[`TLP_CPLBCM_R] = `TLP_CPLBCM_W'b0;
assign wCplHdr[`TLP_CPLRSVD0_R] = `TLP_CPLRSVD0_W'b0;
assign wCplHdr[127:96] = 32'b0;
// Generic Header Fields
assign wCplHdr[`TLP_LEN_R] = TXC_META_LENGTH;
assign wCplHdr[`TLP_EP_R] = TXC_META_EP;
assign wCplHdr[`TLP_TD_R] = `TLP_NODIGEST_V;
assign wCplHdr[`TLP_ATTR0_R] = TXC_META_ATTR[1:0];
assign wCplHdr[`TLP_ATTR1_R] = TXC_META_ATTR[2];
assign {wCplHdr[`TLP_FMT_R], wCplHdr[`TLP_TYPE_R]} = trellis_to_tlp_type(TXC_META_TYPE,0);
assign wCplHdr[`TLP_TC_R] = TXC_META_TC;
// Completion Specific Fields
assign wCplHdr[`TLP_CPLBYTECNT_R] = TXC_META_BYTE_COUNT;
assign wCplHdr[`TLP_CPLSTAT_R] = 0;
assign wCplHdr[`TLP_CPLCPLID_R] = CONFIG_COMPLETER_ID;
assign wCplHdr[`TLP_CPLADDR_R] = TXC_META_ADDR;
assign wCplHdr[`TLP_CPLTAG_R] = TXC_META_TAG;
assign wCplHdr[`TLP_CPLREQID_R] = TXC_META_REQUESTER_ID;
// Metadata, to the aligner
assign wTxLoAddr = wTxHdr[`TLP_CPLADDR_R];
assign wTxHdrNopayload = ~wTxHdr[`TLP_PAYBIT_I];
assign wTxHdrNonpayLen = 3 + ((C_VENDOR == "ALTERA")? {3'b0,(~wTxLoAddr[2] & ~wTxHdrNopayload)} : 4'b0);
assign wTxHdrPayloadLen = wTxHdrNopayload ? 0 : wTxHdr[`TLP_LEN_R];
assign wTxHdrPacketLen = wTxHdrPayloadLen + wTxHdrNonpayLen;
pipeline
#(// Parameters
.C_DEPTH (C_PIPELINE_INPUT?1:0),
.C_WIDTH (C_MAX_HDR_WIDTH),
.C_USE_MEMORY (0)
/*AUTOINSTPARAM*/)
input_inst
(// Outputs
.WR_DATA_READY (TXC_META_READY),
.RD_DATA (wTxHdr),
.RD_DATA_VALID (wTxHdrValid),
// Inputs
.WR_DATA (wCplHdr),
.WR_DATA_VALID (TXC_META_VALID),
.RD_DATA_READY (wTxHdrReady),
/*AUTOINST*/
// Inputs
.CLK (CLK),
.RST_IN (RST_IN));
pipeline
#(
// Parameters
.C_DEPTH (C_PIPELINE_OUTPUT?1:0),
.C_WIDTH (C_MAX_HDR_WIDTH+ 1 + `SIG_PACKETLEN_W + `SIG_LEN_W + `SIG_NONPAY_W),
.C_USE_MEMORY (0)
/*AUTOINSTPARAM*/)
output_inst
(
// Outputs
.WR_DATA_READY (wTxHdrReady),
.RD_DATA ({TX_HDR,TX_HDR_NOPAYLOAD,TX_HDR_PACKET_LEN,TX_HDR_PAYLOAD_LEN,TX_HDR_NONPAY_LEN}),
.RD_DATA_VALID (TX_HDR_VALID),
// Inputs
.WR_DATA ({wTxHdr,wTxHdrNopayload,wTxHdrPacketLen,wTxHdrPayloadLen,wTxHdrNonpayLen}),
.WR_DATA_VALID (wTxHdrValid),
.RD_DATA_READY (TX_HDR_READY),
/*AUTOINST*/
// Inputs
.CLK (CLK),
.RST_IN (RST_IN));
endmodule
|
module sky130_fd_sc_hd__dlygate4sd3_1 (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__dlygate4sd3 base (
.X(X),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
|
module sky130_fd_sc_hd__dlygate4sd3_1 (
X,
A
);
output X;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__dlygate4sd3 base (
.X(X),
.A(A)
);
endmodule
|
module registerFile (input wrEnable, input [4:0] wrReg, input [31:0] wrData, input [4:0] rdReg1, output [31:0] rdData1, input [4:0] rdReg2, output [31:0] rdData2, input clk);
reg [31:0] regFile [31:0];
assign rdData1 = regFile[rdReg1];
assign rdData2 = regFile[rdReg2];
always @(posedge clk) begin if (wrEnable) begin regFile[wrReg] <= wrData; end end
endmodule
|
module registerFile_tb();
reg wrEnable;
reg [4:0] wrReg;
reg [31:0] wrData;
reg [4:0] rdReg1;
wire [31:0] rdData1;
reg [4:0] rdReg2;
wire [31:0] rdData2;
reg clk;
reg [5:0] index; // 6 bits so that it doesnt overflow in the following for loop.
always begin #5 clk = ~clk; end
initial begin
// $monitor ("clk:%d en:%d wrReg:%d wrData:%d rdReg1:%d rdData1:%d rdReg2:%d rdData2:%d", clk, wrEnable, wrReg, wrData, rdReg1, rdData1, rdReg2, rdData2);
clk = 0;
wrEnable = 1;
for (index = 0; index < 32; index = index + 1) begin #10 wrReg = index; wrData = index * 2; $display ("wrReg:%d wrData:%d", wrReg, wrData); end
#10 wrEnable = 0; wrReg = 31; wrData = 93;
#10 rdReg1 = 0; rdReg2 = 1; #2 $display ("rdReg1:%d rdData1:%d rdReg2:%d rdData2:%d", rdReg1, rdData1, rdReg2, rdData2);
#10 rdReg1 = 2; rdReg2 = 3; #2 $display ("rdReg1:%d rdData1:%d rdReg2:%d rdData2:%d", rdReg1, rdData1, rdReg2, rdData2);
#10 rdReg1 = 4; rdReg2 = 5; #2 $display ("rdReg1:%d rdData1:%d rdReg2:%d rdData2:%d", rdReg1, rdData1, rdReg2, rdData2);
#10 rdReg1 = 6; rdReg2 = 7; #2 $display ("rdReg1:%d rdData1:%d rdReg2:%d rdData2:%d", rdReg1, rdData1, rdReg2, rdData2);
#10 rdReg1 = 8; rdReg2 = 9; #2 $display ("rdReg1:%d rdData1:%d rdReg2:%d rdData2:%d", rdReg1, rdData1, rdReg2, rdData2);
#10 rdReg1 = 10; rdReg2 = 11; #2 $display ("rdReg1:%d rdData1:%d rdReg2:%d rdData2:%d", rdReg1, rdData1, rdReg2, rdData2);
#10 rdReg1 = 12; rdReg2 = 13; #2 $display ("rdReg1:%d rdData1:%d rdReg2:%d rdData2:%d", rdReg1, rdData1, rdReg2, rdData2);
#10 rdReg1 = 14; rdReg2 = 15; #2 $display ("rdReg1:%d rdData1:%d rdReg2:%d rdData2:%d", rdReg1, rdData1, rdReg2, rdData2);
#10 rdReg1 = 16; rdReg2 = 17; #2 $display ("rdReg1:%d rdData1:%d rdReg2:%d rdData2:%d", rdReg1, rdData1, rdReg2, rdData2);
#10 rdReg1 = 18; rdReg2 = 19; #2 $display ("rdReg1:%d rdData1:%d rdReg2:%d rdData2:%d", rdReg1, rdData1, rdReg2, rdData2);
#10 rdReg1 = 20; rdReg2 = 21; #2 $display ("rdReg1:%d rdData1:%d rdReg2:%d rdData2:%d", rdReg1, rdData1, rdReg2, rdData2);
#10 rdReg1 = 22; rdReg2 = 23; #2 $display ("rdReg1:%d rdData1:%d rdReg2:%d rdData2:%d", rdReg1, rdData1, rdReg2, rdData2);
#10 rdReg1 = 24; rdReg2 = 25; #2 $display ("rdReg1:%d rdData1:%d rdReg2:%d rdData2:%d", rdReg1, rdData1, rdReg2, rdData2);
#10 rdReg1 = 26; rdReg2 = 27; #2 $display ("rdReg1:%d rdData1:%d rdReg2:%d rdData2:%d", rdReg1, rdData1, rdReg2, rdData2);
#10 rdReg1 = 28; rdReg2 = 29; #2 $display ("rdReg1:%d rdData1:%d rdReg2:%d rdData2:%d", rdReg1, rdData1, rdReg2, rdData2);
#10 rdReg1 = 30; rdReg2 = 31; #2 $display ("rdReg1:%d rdData1:%d rdReg2:%d rdData2:%d", rdReg1, rdData1, rdReg2, rdData2);
end
registerFile regFile1 (wrEnable, wrReg, wrData, rdReg1, rdData1, rdReg2, rdData2, clk);
endmodule
|
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
typedef struct packed {
union packed {
logic ua;
logic ub;
} u;
logic b;
} str_t;
reg toggle; initial toggle='0;
str_t stoggle; initial stoggle='0;
const reg aconst = '0;
reg [1:0][1:0] ptoggle; initial ptoggle=0;
integer cyc; initial cyc=1;
wire [7:0] cyc_copy = cyc[7:0];
wire toggle_up;
alpha a1 (/*AUTOINST*/
// Outputs
.toggle_up (toggle_up),
// Inputs
.clk (clk),
.toggle (toggle),
.cyc_copy (cyc_copy[7:0]));
alpha a2 (/*AUTOINST*/
// Outputs
.toggle_up (toggle_up),
// Inputs
.clk (clk),
.toggle (toggle),
.cyc_copy (cyc_copy[7:0]));
beta b1 (/*AUTOINST*/
// Inputs
.clk (clk),
.toggle_up (toggle_up));
off o1 (/*AUTOINST*/
// Inputs
.clk (clk),
.toggle (toggle));
reg [1:0] memory[121:110];
reg [1023:0] largeish;
// CHECK_COVER_MISSING(-1)
always @ (posedge clk) begin
if (cyc!=0) begin
cyc <= cyc + 1;
memory[cyc + 'd100] <= memory[cyc + 'd100] + 2'b1;
toggle <= '0;
stoggle.u <= toggle;
stoggle.b <= toggle;
ptoggle[0][0] <= toggle;
if (cyc==3) begin
toggle <= '1;
end
if (cyc==4) begin
toggle <= '0;
end
else if (cyc==10) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
end
endmodule
|
module alpha (/*AUTOARG*/
// Outputs
toggle_up,
// Inputs
clk, toggle, cyc_copy
);
// t.a1 and t.a2 collapse to a count of 2
input clk;
input toggle;
// CHECK_COVER(-1,"top.t.a*",4)
// 2 edges * (t.a1 and t.a2)
input [7:0] cyc_copy;
// CHECK_COVER(-1,"top.t.a*","cyc_copy[0]",22)
// CHECK_COVER(-2,"top.t.a*","cyc_copy[1]",10)
// CHECK_COVER(-3,"top.t.a*","cyc_copy[2]",4)
// CHECK_COVER(-4,"top.t.a*","cyc_copy[3]",2)
// CHECK_COVER(-5,"top.t.a*","cyc_copy[4]",0)
// CHECK_COVER(-6,"top.t.a*","cyc_copy[5]",0)
// CHECK_COVER(-7,"top.t.a*","cyc_copy[6]",0)
// CHECK_COVER(-8,"top.t.a*","cyc_copy[7]",0)
reg toggle_internal;
// CHECK_COVER(-1,"top.t.a*",4)
// 2 edges * (t.a1 and t.a2)
output reg toggle_up;
// CHECK_COVER(-1,"top.t.a*",4)
// 2 edges * (t.a1 and t.a2)
always @ (posedge clk) begin
toggle_internal <= toggle;
toggle_up <= toggle;
end
endmodule
|
module beta (/*AUTOARG*/
// Inputs
clk, toggle_up
);
input clk;
input toggle_up;
// CHECK_COVER(-1,"top.t.b1","toggle_up",2)
/* verilator public_module */
always @ (posedge clk) begin
if (0 && toggle_up) begin end
end
endmodule
|
module off (/*AUTOARG*/
// Inputs
clk, toggle
);
// verilator coverage_off
input clk;
// CHECK_COVER_MISSING(-1)
// verilator coverage_on
input toggle;
// CHECK_COVER(-1,"top.t.o1","toggle",2)
endmodule
|
module header
// Internal signals
//
// Generated Signal List
//
//
// End of Generated Signal List
//
// %COMPILER_OPTS%
//TODO: %VERI_CONSTANTS%
// %VERI_CONCURS%
// Generated Signal Assignments
//
// Generated Instances
// wiring ...
// Generated Instances and Port Mappings
endmodule
|
module header
// Internal signals
//
// Generated Signal List
//
//
// End of Generated Signal List
//
// %COMPILER_OPTS%
//TODO: %VERI_CONSTANTS%
// %VERI_CONCURS%
// Generated Signal Assignments
//
// Generated Instances
// wiring ...
// Generated Instances and Port Mappings
endmodule
|
module header
// Internal signals
//
// Generated Signal List
//
//
// End of Generated Signal List
//
// %COMPILER_OPTS%
// Generated Signal Assignments
//
// Generated Instances
// wiring ...
// Generated Instances and Port Mappings
endmodule
|
module header
// Internal signals
//
// Generated Signal List
//
//
// End of Generated Signal List
//
// %COMPILER_OPTS%
// Generated Signal Assignments
//
// Generated Instances
// wiring ...
// Generated Instances and Port Mappings
endmodule
|
module header
// Internal signals
//
// Generated Signal List
//
//
// End of Generated Signal List
//
// %COMPILER_OPTS%
// Generated Signal Assignments
//
// Generated Instances
// wiring ...
// Generated Instances and Port Mappings
endmodule
|
module header
// Internal signals
//
// Generated Signal List
//
//
// End of Generated Signal List
//
// %COMPILER_OPTS%
// Generated Signal Assignments
//
// Generated Instances
// wiring ...
// Generated Instances and Port Mappings
endmodule
|
module header
// Internal signals
//
// Generated Signal List
//
//
// End of Generated Signal List
//
// %COMPILER_OPTS%
// Generated Signal Assignments
//
// Generated Instances
// wiring ...
// Generated Instances and Port Mappings
endmodule
|
module header
// Internal signals
//
// Generated Signal List
//
//
// End of Generated Signal List
//
// %COMPILER_OPTS%
// Generated Signal Assignments
//
// Generated Instances
// wiring ...
// Generated Instances and Port Mappings
endmodule
|
module header
// Internal signals
//
// Generated Signal List
//
//
// End of Generated Signal List
//
// %COMPILER_OPTS%
// Generated Signal Assignments
//
// Generated Instances
// wiring ...
// Generated Instances and Port Mappings
endmodule
|
module LVDS_AD_lvds_ddio_in
(
clock,
datain,
dataout_h,
dataout_l) /* synthesis synthesis_clearbox=1 */;
input clock;
input [7:0] datain;
output [7:0] dataout_h;
output [7:0] dataout_l;
reg [7:0] dataout_h_reg;
reg [7:0] dataout_l_latch;
reg [7:0] dataout_l_reg;
(* ALTERA_ATTRIBUTE = {"LVDS_RX_REGISTER=HIGH;PRESERVE_REGISTER=ON;PRESERVE_FANOUT_FREE_NODE=ON"} *)
reg [7:0] ddio_h_reg;
(* ALTERA_ATTRIBUTE = {"LVDS_RX_REGISTER=LOW;PRESERVE_REGISTER=ON;PRESERVE_FANOUT_FREE_NODE=ON"} *)
reg [7:0] ddio_l_reg;
// synopsys translate_off
initial
dataout_h_reg = 0;
// synopsys translate_on
always @ ( posedge clock)
dataout_h_reg <= ddio_h_reg;
// synopsys translate_off
initial
dataout_l_latch = 0;
// synopsys translate_on
always @ ( negedge clock)
dataout_l_latch <= ddio_l_reg;
// synopsys translate_off
initial
dataout_l_reg = 0;
// synopsys translate_on
always @ ( posedge clock)
dataout_l_reg <= dataout_l_latch;
// synopsys translate_off
initial
ddio_h_reg = 0;
// synopsys translate_on
always @ ( posedge clock)
ddio_h_reg <= datain;
// synopsys translate_off
initial
ddio_l_reg = 0;
// synopsys translate_on
always @ ( negedge clock)
ddio_l_reg <= datain;
assign
dataout_h = dataout_l_reg,
dataout_l = dataout_h_reg;
endmodule
|
module LVDS_AD_dffpipe
(
clock,
d,
q) /* synthesis synthesis_clearbox=1 */;
input clock;
input [7:0] d;
output [7:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
reg [7:0] dffe17a;
reg [7:0] dffe18a;
reg [7:0] dffe19a;
wire clrn;
wire ena;
wire prn;
wire sclr;
// synopsys translate_off
initial
dffe17a = 0;
// synopsys translate_on
always @ ( posedge clock or negedge prn or negedge clrn)
if (prn == 1'b0) dffe17a <= {8{1'b1}};
else if (clrn == 1'b0) dffe17a <= 8'b0;
else if (ena == 1'b1) dffe17a <= (d & {8{(~ sclr)}});
// synopsys translate_off
initial
dffe18a = 0;
// synopsys translate_on
always @ ( posedge clock or negedge prn or negedge clrn)
if (prn == 1'b0) dffe18a <= {8{1'b1}};
else if (clrn == 1'b0) dffe18a <= 8'b0;
else if (ena == 1'b1) dffe18a <= (dffe17a & {8{(~ sclr)}});
// synopsys translate_off
initial
dffe19a = 0;
// synopsys translate_on
always @ ( posedge clock or negedge prn or negedge clrn)
if (prn == 1'b0) dffe19a <= {8{1'b1}};
else if (clrn == 1'b0) dffe19a <= 8'b0;
else if (ena == 1'b1) dffe19a <= (dffe18a & {8{(~ sclr)}});
assign
clrn = 1'b1,
ena = 1'b1,
prn = 1'b1,
q = dffe19a,
sclr = 1'b0;
endmodule
|
module LVDS_AD_lvds_rx
(
rx_in,
rx_inclock,
rx_locked,
rx_out,
rx_outclock) /* synthesis synthesis_clearbox=1 */;
input [7:0] rx_in;
input rx_inclock;
output rx_locked;
output [95:0] rx_out;
output rx_outclock;
wire [7:0] wire_ddio_in_dataout_h;
wire [7:0] wire_ddio_in_dataout_l;
reg [5:0] h_shiftreg10a;
reg [5:0] h_shiftreg12a;
reg [5:0] h_shiftreg14a;
reg [5:0] h_shiftreg16a;
reg [5:0] h_shiftreg2a;
reg [5:0] h_shiftreg4a;
reg [5:0] h_shiftreg6a;
reg [5:0] h_shiftreg8a;
reg [5:0] l_shiftreg11a;
reg [5:0] l_shiftreg13a;
reg [5:0] l_shiftreg15a;
reg [5:0] l_shiftreg1a;
reg [5:0] l_shiftreg3a;
reg [5:0] l_shiftreg5a;
reg [5:0] l_shiftreg7a;
reg [5:0] l_shiftreg9a;
reg [95:0] rx_reg;
wire [7:0] wire_h_dffpipe_q;
wire [7:0] wire_l_dffpipe_q;
wire [4:0] wire_lvds_rx_pll_clk;
wire wire_lvds_rx_pll_fbout;
wire wire_lvds_rx_pll_locked;
wire [7:0] ddio_dataout_h;
wire [7:0] ddio_dataout_h_int;
wire [7:0] ddio_dataout_l;
wire [7:0] ddio_dataout_l_int;
wire fast_clock;
wire [95:0] rx_out_wire;
wire slow_clock;
LVDS_AD_lvds_ddio_in ddio_in
(
.clock(fast_clock),
.datain(rx_in),
.dataout_h(wire_ddio_in_dataout_h),
.dataout_l(wire_ddio_in_dataout_l));
// synopsys translate_off
initial
h_shiftreg10a = 0;
// synopsys translate_on
always @ ( posedge fast_clock)
h_shiftreg10a <= {h_shiftreg10a[4:0], ddio_dataout_l[4]};
// synopsys translate_off
initial
h_shiftreg12a = 0;
// synopsys translate_on
always @ ( posedge fast_clock)
h_shiftreg12a <= {h_shiftreg12a[4:0], ddio_dataout_l[5]};
// synopsys translate_off
initial
h_shiftreg14a = 0;
// synopsys translate_on
always @ ( posedge fast_clock)
h_shiftreg14a <= {h_shiftreg14a[4:0], ddio_dataout_l[6]};
// synopsys translate_off
initial
h_shiftreg16a = 0;
// synopsys translate_on
always @ ( posedge fast_clock)
h_shiftreg16a <= {h_shiftreg16a[4:0], ddio_dataout_l[7]};
// synopsys translate_off
initial
h_shiftreg2a = 0;
// synopsys translate_on
always @ ( posedge fast_clock)
h_shiftreg2a <= {h_shiftreg2a[4:0], ddio_dataout_l[0]};
// synopsys translate_off
initial
h_shiftreg4a = 0;
// synopsys translate_on
always @ ( posedge fast_clock)
h_shiftreg4a <= {h_shiftreg4a[4:0], ddio_dataout_l[1]};
// synopsys translate_off
initial
h_shiftreg6a = 0;
// synopsys translate_on
always @ ( posedge fast_clock)
h_shiftreg6a <= {h_shiftreg6a[4:0], ddio_dataout_l[2]};
// synopsys translate_off
initial
h_shiftreg8a = 0;
// synopsys translate_on
always @ ( posedge fast_clock)
h_shiftreg8a <= {h_shiftreg8a[4:0], ddio_dataout_l[3]};
// synopsys translate_off
initial
l_shiftreg11a = 0;
// synopsys translate_on
always @ ( posedge fast_clock)
l_shiftreg11a <= {l_shiftreg11a[4:0], ddio_dataout_h[5]};
// synopsys translate_off
initial
l_shiftreg13a = 0;
// synopsys translate_on
always @ ( posedge fast_clock)
l_shiftreg13a <= {l_shiftreg13a[4:0], ddio_dataout_h[6]};
// synopsys translate_off
initial
l_shiftreg15a = 0;
// synopsys translate_on
always @ ( posedge fast_clock)
l_shiftreg15a <= {l_shiftreg15a[4:0], ddio_dataout_h[7]};
// synopsys translate_off
initial
l_shiftreg1a = 0;
// synopsys translate_on
always @ ( posedge fast_clock)
l_shiftreg1a <= {l_shiftreg1a[4:0], ddio_dataout_h[0]};
// synopsys translate_off
initial
l_shiftreg3a = 0;
// synopsys translate_on
always @ ( posedge fast_clock)
l_shiftreg3a <= {l_shiftreg3a[4:0], ddio_dataout_h[1]};
// synopsys translate_off
initial
l_shiftreg5a = 0;
// synopsys translate_on
always @ ( posedge fast_clock)
l_shiftreg5a <= {l_shiftreg5a[4:0], ddio_dataout_h[2]};
// synopsys translate_off
initial
l_shiftreg7a = 0;
// synopsys translate_on
always @ ( posedge fast_clock)
l_shiftreg7a <= {l_shiftreg7a[4:0], ddio_dataout_h[3]};
// synopsys translate_off
initial
l_shiftreg9a = 0;
// synopsys translate_on
always @ ( posedge fast_clock)
l_shiftreg9a <= {l_shiftreg9a[4:0], ddio_dataout_h[4]};
// synopsys translate_off
initial
rx_reg = 0;
// synopsys translate_on
always @ ( posedge slow_clock)
rx_reg <= rx_out_wire;
LVDS_AD_dffpipe h_dffpipe
(
.clock(fast_clock),
.d(ddio_dataout_h_int),
.q(wire_h_dffpipe_q));
LVDS_AD_dffpipe l_dffpipe
(
.clock(fast_clock),
.d(ddio_dataout_l_int),
.q(wire_l_dffpipe_q));
cycloneiii_pll lvds_rx_pll
(
.activeclock(),
.clk(wire_lvds_rx_pll_clk),
.clkbad(),
.fbin(wire_lvds_rx_pll_fbout),
.fbout(wire_lvds_rx_pll_fbout),
.inclk({1'b0, rx_inclock}),
.locked(wire_lvds_rx_pll_locked),
.phasedone(),
.scandataout(),
.scandone(),
.vcooverrange(),
.vcounderrange()
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.areset(1'b0),
.clkswitch(1'b0),
.configupdate(1'b0),
.pfdena(1'b1),
.phasecounterselect({3{1'b0}}),
.phasestep(1'b0),
.phaseupdown(1'b0),
.scanclk(1'b0),
.scanclkena(1'b1),
.scandata(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
lvds_rx_pll.clk0_divide_by = 1,
lvds_rx_pll.clk0_multiply_by = 6,
lvds_rx_pll.clk0_phase_shift = "-312",
lvds_rx_pll.clk1_divide_by = 6,
lvds_rx_pll.clk1_multiply_by = 6,
lvds_rx_pll.clk1_phase_shift = "-312",
lvds_rx_pll.inclk0_input_frequency = 20000,
lvds_rx_pll.operation_mode = "source_synchronous",
lvds_rx_pll.self_reset_on_loss_lock = "on",
lvds_rx_pll.lpm_type = "cycloneiii_pll";
assign
ddio_dataout_h = wire_h_dffpipe_q,
ddio_dataout_h_int = wire_ddio_in_dataout_h,
ddio_dataout_l = wire_l_dffpipe_q,
ddio_dataout_l_int = wire_ddio_in_dataout_l,
fast_clock = wire_lvds_rx_pll_clk[0],
rx_locked = wire_lvds_rx_pll_locked,
rx_out = rx_reg,
rx_out_wire = {l_shiftreg15a[5], h_shiftreg16a[5], l_shiftreg15a[4], h_shiftreg16a[4], l_shiftreg15a[3], h_shiftreg16a[3], l_shiftreg15a[2], h_shiftreg16a[2], l_shiftreg15a[1], h_shiftreg16a[1], l_shiftreg15a[0], h_shiftreg16a[0], l_shiftreg13a[5], h_shiftreg14a[5], l_shiftreg13a[4], h_shiftreg14a[4], l_shiftreg13a[3], h_shiftreg14a[3], l_shiftreg13a[2], h_shiftreg14a[2], l_shiftreg13a[1], h_shiftreg14a[1], l_shiftreg13a[0], h_shiftreg14a[0], l_shiftreg11a[5], h_shiftreg12a[5], l_shiftreg11a[4], h_shiftreg12a[4], l_shiftreg11a[3], h_shiftreg12a[3], l_shiftreg11a[2], h_shiftreg12a[2], l_shiftreg11a[1], h_shiftreg12a[1], l_shiftreg11a[0], h_shiftreg12a[0], l_shiftreg9a[5], h_shiftreg10a[5], l_shiftreg9a[4], h_shiftreg10a[4], l_shiftreg9a[3], h_shiftreg10a[3], l_shiftreg9a[2], h_shiftreg10a[2], l_shiftreg9a[1], h_shiftreg10a[1], l_shiftreg9a[0], h_shiftreg10a[0], l_shiftreg7a[5], h_shiftreg8a[5], l_shiftreg7a[4], h_shiftreg8a[4], l_shiftreg7a[3], h_shiftreg8a[3], l_shiftreg7a[2], h_shiftreg8a[2], l_shiftreg7a[1], h_shiftreg8a[1], l_shiftreg7a[0], h_shiftreg8a[0], l_shiftreg5a[5], h_shiftreg6a[5], l_shiftreg5a[4], h_shiftreg6a[4], l_shiftreg5a[3], h_shiftreg6a[3], l_shiftreg5a[2], h_shiftreg6a[2], l_shiftreg5a[1], h_shiftreg6a[1], l_shiftreg5a[0], h_shiftreg6a[0], l_shiftreg3a[5], h_shiftreg4a[5], l_shiftreg3a[4], h_shiftreg4a[4], l_shiftreg3a[3], h_shiftreg4a[3], l_shiftreg3a[2], h_shiftreg4a[2], l_shiftreg3a[1], h_shiftreg4a[1], l_shiftreg3a[0], h_shiftreg4a[0], l_shiftreg1a[5], h_shiftreg2a[5], l_shiftreg1a[4], h_shiftreg2a[4], l_shiftreg1a[3], h_shiftreg2a[3], l_shiftreg1a[2], h_shiftreg2a[2], l_shiftreg1a[1], h_shiftreg2a[1], l_shiftreg1a[0], h_shiftreg2a[0]},
rx_outclock = slow_clock,
slow_clock = wire_lvds_rx_pll_clk[1];
endmodule
|
module sky130_fd_sc_ms__a21boi (
//# {{data|Data Signals}}
input A1 ,
input A2 ,
input B1_N,
output Y
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
|
module pcie_data_rec_fifo(
rst,
wr_clk,
rd_clk,
din,
wr_en,
rd_en,
dout,
full,
almost_full,
empty,
almost_empty,
rd_data_count,
wr_data_count,
prog_full
);
input rst;
input wr_clk;
input rd_clk;
input [127 : 0] din;
input wr_en;
input rd_en;
output [255 : 0] dout;
output full;
output almost_full;
output empty;
output almost_empty;
output [9 : 0] rd_data_count;
output [10 : 0] wr_data_count;
output prog_full;
// synthesis translate_off
FIFO_GENERATOR_V8_4 #(
.C_ADD_NGC_CONSTRAINT(0),
.C_APPLICATION_TYPE_AXIS(0),
.C_APPLICATION_TYPE_RACH(0),
.C_APPLICATION_TYPE_RDCH(0),
.C_APPLICATION_TYPE_WACH(0),
.C_APPLICATION_TYPE_WDCH(0),
.C_APPLICATION_TYPE_WRCH(0),
.C_AXI_ADDR_WIDTH(32),
.C_AXI_ARUSER_WIDTH(1),
.C_AXI_AWUSER_WIDTH(1),
.C_AXI_BUSER_WIDTH(1),
.C_AXI_DATA_WIDTH(64),
.C_AXI_ID_WIDTH(4),
.C_AXI_RUSER_WIDTH(1),
.C_AXI_TYPE(0),
.C_AXI_WUSER_WIDTH(1),
.C_AXIS_TDATA_WIDTH(64),
.C_AXIS_TDEST_WIDTH(4),
.C_AXIS_TID_WIDTH(8),
.C_AXIS_TKEEP_WIDTH(4),
.C_AXIS_TSTRB_WIDTH(4),
.C_AXIS_TUSER_WIDTH(4),
.C_AXIS_TYPE(0),
.C_COMMON_CLOCK(0),
.C_COUNT_TYPE(0),
.C_DATA_COUNT_WIDTH(11),
.C_DEFAULT_VALUE("BlankString"),
.C_DIN_WIDTH(128),
.C_DIN_WIDTH_AXIS(1),
.C_DIN_WIDTH_RACH(32),
.C_DIN_WIDTH_RDCH(64),
.C_DIN_WIDTH_WACH(32),
.C_DIN_WIDTH_WDCH(64),
.C_DIN_WIDTH_WRCH(2),
.C_DOUT_RST_VAL("0"),
.C_DOUT_WIDTH(256),
.C_ENABLE_RLOCS(0),
.C_ENABLE_RST_SYNC(1),
.C_ERROR_INJECTION_TYPE(0),
.C_ERROR_INJECTION_TYPE_AXIS(0),
.C_ERROR_INJECTION_TYPE_RACH(0),
.C_ERROR_INJECTION_TYPE_RDCH(0),
.C_ERROR_INJECTION_TYPE_WACH(0),
.C_ERROR_INJECTION_TYPE_WDCH(0),
.C_ERROR_INJECTION_TYPE_WRCH(0),
.C_FAMILY("virtex6"),
.C_FULL_FLAGS_RST_VAL(0),
.C_HAS_ALMOST_EMPTY(1),
.C_HAS_ALMOST_FULL(1),
.C_HAS_AXI_ARUSER(0),
.C_HAS_AXI_AWUSER(0),
.C_HAS_AXI_BUSER(0),
.C_HAS_AXI_RD_CHANNEL(0),
.C_HAS_AXI_RUSER(0),
.C_HAS_AXI_WR_CHANNEL(0),
.C_HAS_AXI_WUSER(0),
.C_HAS_AXIS_TDATA(0),
.C_HAS_AXIS_TDEST(0),
.C_HAS_AXIS_TID(0),
.C_HAS_AXIS_TKEEP(0),
.C_HAS_AXIS_TLAST(0),
.C_HAS_AXIS_TREADY(1),
.C_HAS_AXIS_TSTRB(0),
.C_HAS_AXIS_TUSER(0),
.C_HAS_BACKUP(0),
.C_HAS_DATA_COUNT(0),
.C_HAS_DATA_COUNTS_AXIS(0),
.C_HAS_DATA_COUNTS_RACH(0),
.C_HAS_DATA_COUNTS_RDCH(0),
.C_HAS_DATA_COUNTS_WACH(0),
.C_HAS_DATA_COUNTS_WDCH(0),
.C_HAS_DATA_COUNTS_WRCH(0),
.C_HAS_INT_CLK(0),
.C_HAS_MASTER_CE(0),
.C_HAS_MEMINIT_FILE(0),
.C_HAS_OVERFLOW(0),
.C_HAS_PROG_FLAGS_AXIS(0),
.C_HAS_PROG_FLAGS_RACH(0),
.C_HAS_PROG_FLAGS_RDCH(0),
.C_HAS_PROG_FLAGS_WACH(0),
.C_HAS_PROG_FLAGS_WDCH(0),
.C_HAS_PROG_FLAGS_WRCH(0),
.C_HAS_RD_DATA_COUNT(1),
.C_HAS_RD_RST(0),
.C_HAS_RST(1),
.C_HAS_SLAVE_CE(0),
.C_HAS_SRST(0),
.C_HAS_UNDERFLOW(0),
.C_HAS_VALID(0),
.C_HAS_WR_ACK(0),
.C_HAS_WR_DATA_COUNT(1),
.C_HAS_WR_RST(0),
.C_IMPLEMENTATION_TYPE(2),
.C_IMPLEMENTATION_TYPE_AXIS(1),
.C_IMPLEMENTATION_TYPE_RACH(1),
.C_IMPLEMENTATION_TYPE_RDCH(1),
.C_IMPLEMENTATION_TYPE_WACH(1),
.C_IMPLEMENTATION_TYPE_WDCH(1),
.C_IMPLEMENTATION_TYPE_WRCH(1),
.C_INIT_WR_PNTR_VAL(0),
.C_INTERFACE_TYPE(0),
.C_MEMORY_TYPE(1),
.C_MIF_FILE_NAME("BlankString"),
.C_MSGON_VAL(1),
.C_OPTIMIZATION_MODE(0),
.C_OVERFLOW_LOW(0),
.C_PRELOAD_LATENCY(0),
.C_PRELOAD_REGS(1),
.C_PRIM_FIFO_TYPE("2kx18"),
.C_PROG_EMPTY_THRESH_ASSERT_VAL(4),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH(1022),
.C_PROG_EMPTY_THRESH_NEGATE_VAL(5),
.C_PROG_EMPTY_TYPE(0),
.C_PROG_EMPTY_TYPE_AXIS(5),
.C_PROG_EMPTY_TYPE_RACH(5),
.C_PROG_EMPTY_TYPE_RDCH(5),
.C_PROG_EMPTY_TYPE_WACH(5),
.C_PROG_EMPTY_TYPE_WDCH(5),
.C_PROG_EMPTY_TYPE_WRCH(5),
.C_PROG_FULL_THRESH_ASSERT_VAL(1793),
.C_PROG_FULL_THRESH_ASSERT_VAL_AXIS(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_RACH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_RDCH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_WACH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_WDCH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_WRCH(1023),
.C_PROG_FULL_THRESH_NEGATE_VAL(1792),
.C_PROG_FULL_TYPE(1),
.C_PROG_FULL_TYPE_AXIS(5),
.C_PROG_FULL_TYPE_RACH(5),
.C_PROG_FULL_TYPE_RDCH(5),
.C_PROG_FULL_TYPE_WACH(5),
.C_PROG_FULL_TYPE_WDCH(5),
.C_PROG_FULL_TYPE_WRCH(5),
.C_RACH_TYPE(0),
.C_RD_DATA_COUNT_WIDTH(10),
.C_RD_DEPTH(1024),
.C_RD_FREQ(1),
.C_RD_PNTR_WIDTH(10),
.C_RDCH_TYPE(0),
.C_REG_SLICE_MODE_AXIS(0),
.C_REG_SLICE_MODE_RACH(0),
.C_REG_SLICE_MODE_RDCH(0),
.C_REG_SLICE_MODE_WACH(0),
.C_REG_SLICE_MODE_WDCH(0),
.C_REG_SLICE_MODE_WRCH(0),
.C_SYNCHRONIZER_STAGE(2),
.C_UNDERFLOW_LOW(0),
.C_USE_COMMON_OVERFLOW(0),
.C_USE_COMMON_UNDERFLOW(0),
.C_USE_DEFAULT_SETTINGS(0),
.C_USE_DOUT_RST(1),
.C_USE_ECC(0),
.C_USE_ECC_AXIS(0),
.C_USE_ECC_RACH(0),
.C_USE_ECC_RDCH(0),
.C_USE_ECC_WACH(0),
.C_USE_ECC_WDCH(0),
.C_USE_ECC_WRCH(0),
.C_USE_EMBEDDED_REG(0),
.C_USE_FIFO16_FLAGS(0),
.C_USE_FWFT_DATA_COUNT(0),
.C_VALID_LOW(0),
.C_WACH_TYPE(0),
.C_WDCH_TYPE(0),
.C_WR_ACK_LOW(0),
.C_WR_DATA_COUNT_WIDTH(11),
.C_WR_DEPTH(2048),
.C_WR_DEPTH_AXIS(1024),
.C_WR_DEPTH_RACH(16),
.C_WR_DEPTH_RDCH(1024),
.C_WR_DEPTH_WACH(16),
.C_WR_DEPTH_WDCH(1024),
.C_WR_DEPTH_WRCH(16),
.C_WR_FREQ(1),
.C_WR_PNTR_WIDTH(11),
.C_WR_PNTR_WIDTH_AXIS(10),
.C_WR_PNTR_WIDTH_RACH(4),
.C_WR_PNTR_WIDTH_RDCH(10),
.C_WR_PNTR_WIDTH_WACH(4),
.C_WR_PNTR_WIDTH_WDCH(10),
.C_WR_PNTR_WIDTH_WRCH(4),
.C_WR_RESPONSE_LATENCY(1),
.C_WRCH_TYPE(0)
)
inst (
.RST(rst),
.WR_CLK(wr_clk),
.RD_CLK(rd_clk),
.DIN(din),
.WR_EN(wr_en),
.RD_EN(rd_en),
.DOUT(dout),
.FULL(full),
.ALMOST_FULL(almost_full),
.EMPTY(empty),
.ALMOST_EMPTY(almost_empty),
.RD_DATA_COUNT(rd_data_count),
.WR_DATA_COUNT(wr_data_count),
.PROG_FULL(prog_full),
.BACKUP(),
.BACKUP_MARKER(),
.CLK(),
.SRST(),
.WR_RST(),
.RD_RST(),
.PROG_EMPTY_THRESH(),
.PROG_EMPTY_THRESH_ASSERT(),
.PROG_EMPTY_THRESH_NEGATE(),
.PROG_FULL_THRESH(),
.PROG_FULL_THRESH_ASSERT(),
.PROG_FULL_THRESH_NEGATE(),
.INT_CLK(),
.INJECTDBITERR(),
.INJECTSBITERR(),
.WR_ACK(),
.OVERFLOW(),
.VALID(),
.UNDERFLOW(),
.DATA_COUNT(),
.PROG_EMPTY(),
.SBITERR(),
.DBITERR(),
.M_ACLK(),
.S_ACLK(),
.S_ARESETN(),
.M_ACLK_EN(),
.S_ACLK_EN(),
.S_AXI_AWID(),
.S_AXI_AWADDR(),
.S_AXI_AWLEN(),
.S_AXI_AWSIZE(),
.S_AXI_AWBURST(),
.S_AXI_AWLOCK(),
.S_AXI_AWCACHE(),
.S_AXI_AWPROT(),
.S_AXI_AWQOS(),
.S_AXI_AWREGION(),
.S_AXI_AWUSER(),
.S_AXI_AWVALID(),
.S_AXI_AWREADY(),
.S_AXI_WID(),
.S_AXI_WDATA(),
.S_AXI_WSTRB(),
.S_AXI_WLAST(),
.S_AXI_WUSER(),
.S_AXI_WVALID(),
.S_AXI_WREADY(),
.S_AXI_BID(),
.S_AXI_BRESP(),
.S_AXI_BUSER(),
.S_AXI_BVALID(),
.S_AXI_BREADY(),
.M_AXI_AWID(),
.M_AXI_AWADDR(),
.M_AXI_AWLEN(),
.M_AXI_AWSIZE(),
.M_AXI_AWBURST(),
.M_AXI_AWLOCK(),
.M_AXI_AWCACHE(),
.M_AXI_AWPROT(),
.M_AXI_AWQOS(),
.M_AXI_AWREGION(),
.M_AXI_AWUSER(),
.M_AXI_AWVALID(),
.M_AXI_AWREADY(),
.M_AXI_WID(),
.M_AXI_WDATA(),
.M_AXI_WSTRB(),
.M_AXI_WLAST(),
.M_AXI_WUSER(),
.M_AXI_WVALID(),
.M_AXI_WREADY(),
.M_AXI_BID(),
.M_AXI_BRESP(),
.M_AXI_BUSER(),
.M_AXI_BVALID(),
.M_AXI_BREADY(),
.S_AXI_ARID(),
.S_AXI_ARADDR(),
.S_AXI_ARLEN(),
.S_AXI_ARSIZE(),
.S_AXI_ARBURST(),
.S_AXI_ARLOCK(),
.S_AXI_ARCACHE(),
.S_AXI_ARPROT(),
.S_AXI_ARQOS(),
.S_AXI_ARREGION(),
.S_AXI_ARUSER(),
.S_AXI_ARVALID(),
.S_AXI_ARREADY(),
.S_AXI_RID(),
.S_AXI_RDATA(),
.S_AXI_RRESP(),
.S_AXI_RLAST(),
.S_AXI_RUSER(),
.S_AXI_RVALID(),
.S_AXI_RREADY(),
.M_AXI_ARID(),
.M_AXI_ARADDR(),
.M_AXI_ARLEN(),
.M_AXI_ARSIZE(),
.M_AXI_ARBURST(),
.M_AXI_ARLOCK(),
.M_AXI_ARCACHE(),
.M_AXI_ARPROT(),
.M_AXI_ARQOS(),
.M_AXI_ARREGION(),
.M_AXI_ARUSER(),
.M_AXI_ARVALID(),
.M_AXI_ARREADY(),
.M_AXI_RID(),
.M_AXI_RDATA(),
.M_AXI_RRESP(),
.M_AXI_RLAST(),
.M_AXI_RUSER(),
.M_AXI_RVALID(),
.M_AXI_RREADY(),
.S_AXIS_TVALID(),
.S_AXIS_TREADY(),
.S_AXIS_TDATA(),
.S_AXIS_TSTRB(),
.S_AXIS_TKEEP(),
.S_AXIS_TLAST(),
.S_AXIS_TID(),
.S_AXIS_TDEST(),
.S_AXIS_TUSER(),
.M_AXIS_TVALID(),
.M_AXIS_TREADY(),
.M_AXIS_TDATA(),
.M_AXIS_TSTRB(),
.M_AXIS_TKEEP(),
.M_AXIS_TLAST(),
.M_AXIS_TID(),
.M_AXIS_TDEST(),
.M_AXIS_TUSER(),
.AXI_AW_INJECTSBITERR(),
.AXI_AW_INJECTDBITERR(),
.AXI_AW_PROG_FULL_THRESH(),
.AXI_AW_PROG_EMPTY_THRESH(),
.AXI_AW_DATA_COUNT(),
.AXI_AW_WR_DATA_COUNT(),
.AXI_AW_RD_DATA_COUNT(),
.AXI_AW_SBITERR(),
.AXI_AW_DBITERR(),
.AXI_AW_OVERFLOW(),
.AXI_AW_UNDERFLOW(),
.AXI_W_INJECTSBITERR(),
.AXI_W_INJECTDBITERR(),
.AXI_W_PROG_FULL_THRESH(),
.AXI_W_PROG_EMPTY_THRESH(),
.AXI_W_DATA_COUNT(),
.AXI_W_WR_DATA_COUNT(),
.AXI_W_RD_DATA_COUNT(),
.AXI_W_SBITERR(),
.AXI_W_DBITERR(),
.AXI_W_OVERFLOW(),
.AXI_W_UNDERFLOW(),
.AXI_B_INJECTSBITERR(),
.AXI_B_INJECTDBITERR(),
.AXI_B_PROG_FULL_THRESH(),
.AXI_B_PROG_EMPTY_THRESH(),
.AXI_B_DATA_COUNT(),
.AXI_B_WR_DATA_COUNT(),
.AXI_B_RD_DATA_COUNT(),
.AXI_B_SBITERR(),
.AXI_B_DBITERR(),
.AXI_B_OVERFLOW(),
.AXI_B_UNDERFLOW(),
.AXI_AR_INJECTSBITERR(),
.AXI_AR_INJECTDBITERR(),
.AXI_AR_PROG_FULL_THRESH(),
.AXI_AR_PROG_EMPTY_THRESH(),
.AXI_AR_DATA_COUNT(),
.AXI_AR_WR_DATA_COUNT(),
.AXI_AR_RD_DATA_COUNT(),
.AXI_AR_SBITERR(),
.AXI_AR_DBITERR(),
.AXI_AR_OVERFLOW(),
.AXI_AR_UNDERFLOW(),
.AXI_R_INJECTSBITERR(),
.AXI_R_INJECTDBITERR(),
.AXI_R_PROG_FULL_THRESH(),
.AXI_R_PROG_EMPTY_THRESH(),
.AXI_R_DATA_COUNT(),
.AXI_R_WR_DATA_COUNT(),
.AXI_R_RD_DATA_COUNT(),
.AXI_R_SBITERR(),
.AXI_R_DBITERR(),
.AXI_R_OVERFLOW(),
.AXI_R_UNDERFLOW(),
.AXIS_INJECTSBITERR(),
.AXIS_INJECTDBITERR(),
.AXIS_PROG_FULL_THRESH(),
.AXIS_PROG_EMPTY_THRESH(),
.AXIS_DATA_COUNT(),
.AXIS_WR_DATA_COUNT(),
.AXIS_RD_DATA_COUNT(),
.AXIS_SBITERR(),
.AXIS_DBITERR(),
.AXIS_OVERFLOW(),
.AXIS_UNDERFLOW()
);
// synthesis translate_on
endmodule
|
module nios_system_sub_outputs (
// inputs:
address,
clk,
in_port,
reset_n,
// outputs:
readdata
)
;
output [ 31: 0] readdata;
input [ 1: 0] address;
input clk;
input [ 7: 0] in_port;
input reset_n;
wire clk_en;
wire [ 7: 0] data_in;
wire [ 7: 0] read_mux_out;
reg [ 31: 0] readdata;
assign clk_en = 1;
//s1, which is an e_avalon_slave
assign read_mux_out = {8 {(address == 0)}} & data_in;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
readdata <= 0;
else if (clk_en)
readdata <= {32'b0 | read_mux_out};
end
assign data_in = in_port;
endmodule
|
module fifo_address_gray_pipelined (
input m_axis_aclk,
input m_axis_aresetn,
input m_axis_ready,
output reg m_axis_valid,
output [C_ADDRESS_WIDTH-1:0] m_axis_raddr_next,
input s_axis_aclk,
input s_axis_aresetn,
output reg s_axis_ready,
input s_axis_valid,
output reg s_axis_empty,
output [C_ADDRESS_WIDTH-1:0] s_axis_waddr
);
parameter C_ADDRESS_WIDTH = 4;
reg [C_ADDRESS_WIDTH:0] _s_axis_waddr = 'h00;
reg [C_ADDRESS_WIDTH:0] _s_axis_waddr_next;
wire [C_ADDRESS_WIDTH:0] _s_axis_raddr;
reg [C_ADDRESS_WIDTH:0] _m_axis_raddr = 'h00;
reg [C_ADDRESS_WIDTH:0] _m_axis_raddr_next;
wire [C_ADDRESS_WIDTH:0] _m_axis_waddr;
assign s_axis_waddr = _s_axis_waddr[C_ADDRESS_WIDTH-1:0];
assign m_axis_raddr_next = _m_axis_raddr_next[C_ADDRESS_WIDTH-1:0];
always @(*)
begin
if (s_axis_ready && s_axis_valid)
_s_axis_waddr_next <= _s_axis_waddr + 1;
else
_s_axis_waddr_next <= _s_axis_waddr;
end
always @(posedge s_axis_aclk)
begin
if (s_axis_aresetn == 1'b0) begin
_s_axis_waddr <= 'h00;
end else begin
_s_axis_waddr <= _s_axis_waddr_next;
end
end
always @(*)
begin
if (m_axis_ready && m_axis_valid)
_m_axis_raddr_next <= _m_axis_raddr + 1;
else
_m_axis_raddr_next <= _m_axis_raddr;
end
always @(posedge m_axis_aclk)
begin
if (m_axis_aresetn == 1'b0) begin
_m_axis_raddr <= 'h00;
end else begin
_m_axis_raddr <= _m_axis_raddr_next;
end
end
sync_gray #(
.DATA_WIDTH(C_ADDRESS_WIDTH + 1)
) i_waddr_sync (
.in_clk(s_axis_aclk),
.in_resetn(s_axis_aresetn),
.out_clk(m_axis_aclk),
.out_resetn(m_axis_aresetn),
.in_count(_s_axis_waddr),
.out_count(_m_axis_waddr)
);
sync_gray #(
.DATA_WIDTH(C_ADDRESS_WIDTH + 1)
) i_raddr_sync (
.in_clk(m_axis_aclk),
.in_resetn(m_axis_aresetn),
.out_clk(s_axis_aclk),
.out_resetn(s_axis_aresetn),
.in_count(_m_axis_raddr),
.out_count(_s_axis_raddr)
);
always @(posedge s_axis_aclk)
begin
if (s_axis_aresetn == 1'b0) begin
s_axis_ready <= 1'b1;
s_axis_empty <= 1'b1;
end else begin
s_axis_ready <= (_s_axis_raddr[C_ADDRESS_WIDTH] == _s_axis_waddr_next[C_ADDRESS_WIDTH] ||
_s_axis_raddr[C_ADDRESS_WIDTH-1:0] != _s_axis_waddr_next[C_ADDRESS_WIDTH-1:0]);
s_axis_empty <= _s_axis_raddr == _s_axis_waddr_next;
end
end
always @(posedge m_axis_aclk)
begin
if (s_axis_aresetn == 1'b0)
m_axis_valid <= 1'b0;
else begin
m_axis_valid <= _m_axis_waddr != _m_axis_raddr_next;
end
end
endmodule
|
module or1200_cpu(
// Clk & Rst
clk, rst,
// Insn interface
ic_en,
icpu_adr_o, icpu_cycstb_o, icpu_sel_o, icpu_tag_o,
icpu_dat_i, icpu_ack_i, icpu_rty_i, icpu_err_i, icpu_adr_i, icpu_tag_i,
immu_en,
// Debug unit
ex_insn, ex_freeze, id_pc, branch_op,
spr_dat_npc, rf_dataw,
du_stall, du_addr, du_dat_du, du_read, du_write, du_dsr, du_hwbkpt,
du_except, du_dat_cpu,
// Data interface
dc_en,
dcpu_adr_o, dcpu_cycstb_o, dcpu_we_o, dcpu_sel_o, dcpu_tag_o, dcpu_dat_o,
dcpu_dat_i, dcpu_ack_i, dcpu_rty_i, dcpu_err_i, dcpu_tag_i,
dmmu_en,
// Interrupt & tick exceptions
sig_int, sig_tick,
// SPR interface
supv, spr_addr, spr_dat_cpu, spr_dat_pic, spr_dat_tt, spr_dat_pm,
spr_dat_dmmu, spr_dat_immu, spr_dat_du, spr_cs, spr_we
);
parameter dw = `OR1200_OPERAND_WIDTH;
parameter aw = `OR1200_REGFILE_ADDR_WIDTH;
//
// I/O ports
//
//
// Clk & Rst
//
input clk;
input rst;
//
// Insn (IC) interface
//
output ic_en;
output [31:0] icpu_adr_o;
output icpu_cycstb_o;
output [3:0] icpu_sel_o;
output [3:0] icpu_tag_o;
input [31:0] icpu_dat_i;
input icpu_ack_i;
input icpu_rty_i;
input icpu_err_i;
input [31:0] icpu_adr_i;
input [3:0] icpu_tag_i;
//
// Insn (IMMU) interface
//
output immu_en;
//
// Debug interface
//
output [31:0] ex_insn;
output ex_freeze;
output [31:0] id_pc;
output [`OR1200_BRANCHOP_WIDTH-1:0] branch_op;
input du_stall;
input [dw-1:0] du_addr;
input [dw-1:0] du_dat_du;
input du_read;
input du_write;
input [`OR1200_DU_DSR_WIDTH-1:0] du_dsr;
input du_hwbkpt;
output [12:0] du_except;
output [dw-1:0] du_dat_cpu;
output [dw-1:0] rf_dataw;
//
// Data (DC) interface
//
output [31:0] dcpu_adr_o;
output dcpu_cycstb_o;
output dcpu_we_o;
output [3:0] dcpu_sel_o;
output [3:0] dcpu_tag_o;
output [31:0] dcpu_dat_o;
input [31:0] dcpu_dat_i;
input dcpu_ack_i;
input dcpu_rty_i;
input dcpu_err_i;
input [3:0] dcpu_tag_i;
output dc_en;
//
// Data (DMMU) interface
//
output dmmu_en;
//
// SPR interface
//
output supv;
input [dw-1:0] spr_dat_pic;
input [dw-1:0] spr_dat_tt;
input [dw-1:0] spr_dat_pm;
input [dw-1:0] spr_dat_dmmu;
input [dw-1:0] spr_dat_immu;
input [dw-1:0] spr_dat_du;
output [dw-1:0] spr_addr;
output [dw-1:0] spr_dat_cpu;
output [dw-1:0] spr_dat_npc;
output [31:0] spr_cs;
output spr_we;
//
// Interrupt exceptions
//
input sig_int;
input sig_tick;
//
// Internal wires
//
wire [31:0] if_insn;
wire [31:0] if_pc;
wire [31:2] lr_sav;
wire [aw-1:0] rf_addrw;
wire [aw-1:0] rf_addra;
wire [aw-1:0] rf_addrb;
wire rf_rda;
wire rf_rdb;
wire [dw-1:0] simm;
wire [dw-1:2] branch_addrofs;
wire [`OR1200_ALUOP_WIDTH-1:0] alu_op;
wire [`OR1200_SHROTOP_WIDTH-1:0] shrot_op;
wire [`OR1200_COMPOP_WIDTH-1:0] comp_op;
wire [`OR1200_BRANCHOP_WIDTH-1:0] branch_op;
wire [`OR1200_LSUOP_WIDTH-1:0] lsu_op;
wire genpc_freeze;
wire if_freeze;
wire id_freeze;
wire ex_freeze;
wire wb_freeze;
wire [`OR1200_SEL_WIDTH-1:0] sel_a;
wire [`OR1200_SEL_WIDTH-1:0] sel_b;
wire [`OR1200_RFWBOP_WIDTH-1:0] rfwb_op;
wire [dw-1:0] rf_dataw;
wire [dw-1:0] rf_dataa;
wire [dw-1:0] rf_datab;
wire [dw-1:0] muxed_b;
wire [dw-1:0] wb_forw;
wire wbforw_valid;
wire [dw-1:0] operand_a;
wire [dw-1:0] operand_b;
wire [dw-1:0] alu_dataout;
wire [dw-1:0] lsu_dataout;
wire [dw-1:0] sprs_dataout;
wire [31:0] lsu_addrofs;
wire [`OR1200_MULTICYCLE_WIDTH-1:0] multicycle;
wire [`OR1200_EXCEPT_WIDTH-1:0] except_type;
wire [4:0] cust5_op;
wire [5:0] cust5_limm;
wire flushpipe;
wire extend_flush;
wire branch_taken;
wire flag;
wire flagforw;
wire flag_we;
wire carry;
wire cyforw;
wire cy_we;
wire lsu_stall;
wire epcr_we;
wire eear_we;
wire esr_we;
wire pc_we;
wire [31:0] epcr;
wire [31:0] eear;
wire [`OR1200_SR_WIDTH-1:0] esr;
wire sr_we;
wire [`OR1200_SR_WIDTH-1:0] to_sr;
wire [`OR1200_SR_WIDTH-1:0] sr;
wire except_start;
wire except_started;
wire [31:0] wb_insn;
wire [15:0] spr_addrimm;
wire sig_syscall;
wire sig_trap;
wire [31:0] spr_dat_cfgr;
wire [31:0] spr_dat_rf;
wire [31:0] spr_dat_npc;
wire [31:0] spr_dat_ppc;
wire [31:0] spr_dat_mac;
wire force_dslot_fetch;
wire no_more_dslot;
wire ex_void;
wire if_stall;
wire id_macrc_op;
wire ex_macrc_op;
wire [`OR1200_MACOP_WIDTH-1:0] mac_op;
wire [31:0] mult_mac_result;
wire mac_stall;
wire [12:0] except_stop;
wire genpc_refetch;
wire rfe;
wire lsu_unstall;
wire except_align;
wire except_dtlbmiss;
wire except_dmmufault;
wire except_illegal;
wire except_itlbmiss;
wire except_immufault;
wire except_ibuserr;
wire except_dbuserr;
wire abort_ex;
//
// Send exceptions to Debug Unit
//
assign du_except = except_stop;
//
// Data cache enable
//
assign dc_en = sr[`OR1200_SR_DCE];
//
// Instruction cache enable
//
assign ic_en = sr[`OR1200_SR_ICE];
//
// DMMU enable
//
assign dmmu_en = sr[`OR1200_SR_DME];
//
// IMMU enable
//
assign immu_en = sr[`OR1200_SR_IME];
//
// SUPV bit
//
assign supv = sr[`OR1200_SR_SM];
//
// Instantiation of instruction fetch block
//
or1200_genpc or1200_genpc(
.clk(clk),
.rst(rst),
.icpu_adr_o(icpu_adr_o),
.icpu_cycstb_o(icpu_cycstb_o),
.icpu_sel_o(icpu_sel_o),
.icpu_tag_o(icpu_tag_o),
.icpu_rty_i(icpu_rty_i),
.icpu_adr_i(icpu_adr_i),
.branch_op(branch_op),
.except_type(except_type),
.except_start(except_start),
.except_prefix(sr[`OR1200_SR_EPH]),
.branch_addrofs(branch_addrofs),
.lr_restor(operand_b),
.flag(flag),
.taken(branch_taken),
.binsn_addr(lr_sav),
.epcr(epcr),
.spr_dat_i(spr_dat_cpu),
.spr_pc_we(pc_we),
.genpc_refetch(genpc_refetch),
.genpc_freeze(genpc_freeze),
.genpc_stop_prefetch(1'b0),
.no_more_dslot(no_more_dslot)
);
//
// Instantiation of instruction fetch block
//
or1200_if or1200_if(
.clk(clk),
.rst(rst),
.icpu_dat_i(icpu_dat_i),
.icpu_ack_i(icpu_ack_i),
.icpu_err_i(icpu_err_i),
.icpu_adr_i(icpu_adr_i),
.icpu_tag_i(icpu_tag_i),
.if_freeze(if_freeze),
.if_insn(if_insn),
.if_pc(if_pc),
.flushpipe(flushpipe),
.if_stall(if_stall),
.no_more_dslot(no_more_dslot),
.genpc_refetch(genpc_refetch),
.rfe(rfe),
.except_itlbmiss(except_itlbmiss),
.except_immufault(except_immufault),
.except_ibuserr(except_ibuserr)
);
//
// Instantiation of instruction decode/control logic
//
or1200_ctrl or1200_ctrl(
.clk(clk),
.rst(rst),
.id_freeze(id_freeze),
.ex_freeze(ex_freeze),
.wb_freeze(wb_freeze),
.flushpipe(flushpipe),
.if_insn(if_insn),
.ex_insn(ex_insn),
.branch_op(branch_op),
.branch_taken(branch_taken),
.rf_addra(rf_addra),
.rf_addrb(rf_addrb),
.rf_rda(rf_rda),
.rf_rdb(rf_rdb),
.alu_op(alu_op),
.mac_op(mac_op),
.shrot_op(shrot_op),
.comp_op(comp_op),
.rf_addrw(rf_addrw),
.rfwb_op(rfwb_op),
.wb_insn(wb_insn),
.simm(simm),
.branch_addrofs(branch_addrofs),
.lsu_addrofs(lsu_addrofs),
.sel_a(sel_a),
.sel_b(sel_b),
.lsu_op(lsu_op),
.cust5_op(cust5_op),
.cust5_limm(cust5_limm),
.multicycle(multicycle),
.spr_addrimm(spr_addrimm),
.wbforw_valid(wbforw_valid),
.sig_syscall(sig_syscall),
.sig_trap(sig_trap),
.force_dslot_fetch(force_dslot_fetch),
.no_more_dslot(no_more_dslot),
.ex_void(ex_void),
.id_macrc_op(id_macrc_op),
.ex_macrc_op(ex_macrc_op),
.rfe(rfe),
.du_hwbkpt(du_hwbkpt),
.except_illegal(except_illegal)
);
//
// Instantiation of register file
//
or1200_rf or1200_rf(
.clk(clk),
.rst(rst),
.supv(sr[`OR1200_SR_SM]),
.wb_freeze(wb_freeze),
.addrw(rf_addrw),
.dataw(rf_dataw),
.id_freeze(id_freeze),
.we(rfwb_op[0]),
.flushpipe(flushpipe),
.addra(rf_addra),
.rda(rf_rda),
.dataa(rf_dataa),
.addrb(rf_addrb),
.rdb(rf_rdb),
.datab(rf_datab),
.spr_cs(spr_cs[`OR1200_SPR_GROUP_SYS]),
.spr_write(spr_we),
.spr_addr(spr_addr),
.spr_dat_i(spr_dat_cpu),
.spr_dat_o(spr_dat_rf)
);
//
// Instantiation of operand muxes
//
or1200_operandmuxes or1200_operandmuxes(
.clk(clk),
.rst(rst),
.id_freeze(id_freeze),
.ex_freeze(ex_freeze),
.rf_dataa(rf_dataa),
.rf_datab(rf_datab),
.ex_forw(rf_dataw),
.wb_forw(wb_forw),
.simm(simm),
.sel_a(sel_a),
.sel_b(sel_b),
.operand_a(operand_a),
.operand_b(operand_b),
.muxed_b(muxed_b)
);
//
// Instantiation of CPU's ALU
//
or1200_alu or1200_alu(
.a(operand_a),
.b(operand_b),
.mult_mac_result(mult_mac_result),
.macrc_op(ex_macrc_op),
.alu_op(alu_op),
.shrot_op(shrot_op),
.comp_op(comp_op),
.cust5_op(cust5_op),
.cust5_limm(cust5_limm),
.result(alu_dataout),
.flagforw(flagforw),
.flag_we(flag_we),
.cyforw(cyforw),
.cy_we(cy_we),
.flag(flag),
.carry(carry)
);
//
// Instantiation of CPU's ALU
//
or1200_mult_mac or1200_mult_mac(
.clk(clk),
.rst(rst),
.ex_freeze(ex_freeze),
.id_macrc_op(id_macrc_op),
.macrc_op(ex_macrc_op),
.a(operand_a),
.b(operand_b),
.mac_op(mac_op),
.alu_op(alu_op),
.result(mult_mac_result),
.mac_stall_r(mac_stall),
.spr_cs(spr_cs[`OR1200_SPR_GROUP_MAC]),
.spr_write(spr_we),
.spr_addr(spr_addr),
.spr_dat_i(spr_dat_cpu),
.spr_dat_o(spr_dat_mac)
);
//
// Instantiation of CPU's SPRS block
//
or1200_sprs or1200_sprs(
.clk(clk),
.rst(rst),
.addrbase(operand_a),
.addrofs(spr_addrimm),
.dat_i(operand_b),
.alu_op(alu_op),
.flagforw(flagforw),
.flag_we(flag_we),
.flag(flag),
.cyforw(cyforw),
.cy_we(cy_we),
.carry(carry),
.to_wbmux(sprs_dataout),
.du_addr(du_addr),
.du_dat_du(du_dat_du),
.du_read(du_read),
.du_write(du_write),
.du_dat_cpu(du_dat_cpu),
.spr_addr(spr_addr),
.spr_dat_pic(spr_dat_pic),
.spr_dat_tt(spr_dat_tt),
.spr_dat_pm(spr_dat_pm),
.spr_dat_cfgr(spr_dat_cfgr),
.spr_dat_rf(spr_dat_rf),
.spr_dat_npc(spr_dat_npc),
.spr_dat_ppc(spr_dat_ppc),
.spr_dat_mac(spr_dat_mac),
.spr_dat_dmmu(spr_dat_dmmu),
.spr_dat_immu(spr_dat_immu),
.spr_dat_du(spr_dat_du),
.spr_dat_o(spr_dat_cpu),
.spr_cs(spr_cs),
.spr_we(spr_we),
.epcr_we(epcr_we),
.eear_we(eear_we),
.esr_we(esr_we),
.pc_we(pc_we),
.epcr(epcr),
.eear(eear),
.esr(esr),
.except_started(except_started),
.sr_we(sr_we),
.to_sr(to_sr),
.sr(sr),
.branch_op(branch_op)
);
//
// Instantiation of load/store unit
//
//XLNX_MODIFIED added in a clock
or1200_lsu or1200_lsu(
.clk(clk),
.addrbase(operand_a),
.addrofs(lsu_addrofs),
.lsu_op(lsu_op),
.lsu_datain(operand_b),
.lsu_dataout(lsu_dataout),
.lsu_stall(lsu_stall),
.lsu_unstall(lsu_unstall),
.du_stall(du_stall),
.except_align(except_align),
.except_dtlbmiss(except_dtlbmiss),
.except_dmmufault(except_dmmufault),
.except_dbuserr(except_dbuserr),
.dcpu_adr_o(dcpu_adr_o),
.dcpu_cycstb_o(dcpu_cycstb_o),
.dcpu_we_o(dcpu_we_o),
.dcpu_sel_o(dcpu_sel_o),
.dcpu_tag_o(dcpu_tag_o),
.dcpu_dat_o(dcpu_dat_o),
.dcpu_dat_i(dcpu_dat_i),
.dcpu_ack_i(dcpu_ack_i),
.dcpu_rty_i(dcpu_rty_i),
.dcpu_err_i(dcpu_err_i),
.dcpu_tag_i(dcpu_tag_i)
);
//
// Instantiation of write-back muxes
//
or1200_wbmux or1200_wbmux(
.clk(clk),
.rst(rst),
.wb_freeze(wb_freeze),
.rfwb_op(rfwb_op),
.muxin_a(alu_dataout),
.muxin_b(lsu_dataout),
.muxin_c(sprs_dataout),
.muxin_d({lr_sav, 2'b0}),
.muxout(rf_dataw),
.muxreg(wb_forw),
.muxreg_valid(wbforw_valid)
);
//
// Instantiation of freeze logic
//
or1200_freeze or1200_freeze(
.clk(clk),
.rst(rst),
.multicycle(multicycle),
.flushpipe(flushpipe),
.extend_flush(extend_flush),
.lsu_stall(lsu_stall),
.if_stall(if_stall),
.lsu_unstall(lsu_unstall),
.force_dslot_fetch(force_dslot_fetch),
.abort_ex(abort_ex),
.du_stall(du_stall),
.mac_stall(mac_stall),
.genpc_freeze(genpc_freeze),
.if_freeze(if_freeze),
.id_freeze(id_freeze),
.ex_freeze(ex_freeze),
.wb_freeze(wb_freeze),
.icpu_ack_i(icpu_ack_i),
.icpu_err_i(icpu_err_i)
);
//
// Instantiation of exception block
//
or1200_except or1200_except(
.clk(clk),
.rst(rst),
.sig_ibuserr(except_ibuserr),
.sig_dbuserr(except_dbuserr),
.sig_illegal(except_illegal),
.sig_align(except_align),
.sig_range(1'b0),
.sig_dtlbmiss(except_dtlbmiss),
.sig_dmmufault(except_dmmufault),
.sig_int(sig_int),
.sig_syscall(sig_syscall),
.sig_trap(sig_trap),
.sig_itlbmiss(except_itlbmiss),
.sig_immufault(except_immufault),
.sig_tick(sig_tick),
.branch_taken(branch_taken),
.icpu_ack_i(icpu_ack_i),
.icpu_err_i(icpu_err_i),
.dcpu_ack_i(dcpu_ack_i),
.dcpu_err_i(dcpu_err_i),
.genpc_freeze(genpc_freeze),
.id_freeze(id_freeze),
.ex_freeze(ex_freeze),
.wb_freeze(wb_freeze),
.if_stall(if_stall),
.if_pc(if_pc),
.id_pc(id_pc),
.lr_sav(lr_sav),
.flushpipe(flushpipe),
.extend_flush(extend_flush),
.except_type(except_type),
.except_start(except_start),
.except_started(except_started),
.except_stop(except_stop),
.ex_void(ex_void),
.spr_dat_ppc(spr_dat_ppc),
.spr_dat_npc(spr_dat_npc),
.datain(operand_b),
.du_dsr(du_dsr),
.epcr_we(epcr_we),
.eear_we(eear_we),
.esr_we(esr_we),
.pc_we(pc_we),
.epcr(epcr),
.eear(eear),
.esr(esr),
.lsu_addr(dcpu_adr_o),
.sr_we(sr_we),
.to_sr(to_sr),
.sr(sr),
.abort_ex(abort_ex)
);
//
// Instantiation of configuration registers
//
or1200_cfgr or1200_cfgr(
.spr_addr(spr_addr),
.spr_dat_o(spr_dat_cfgr)
);
endmodule
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