module_content
stringlengths 18
1.05M
|
|---|
module accepts 1 input plus a clock and returns 1
// on output after 25000 clock cycles have passed.
reg [14:0] LFSR;
always @(posedge Clock, negedge Reset) begin
if(Reset==0) begin
Out <= 0;
LFSR <= 15'b111111111111111;
end
else begin
LFSR[0] <= LFSR[13] ^ LFSR[14];
LFSR[14:1] <= LFSR[13:0];
if(LFSR==15'b001000010001100) Out <= 1;
end
end
endmodule
|
module bsg_mem_1rw_sync_mask_write_byte #(parameter `BSG_INV_PARAM(els_p )
,parameter `BSG_INV_PARAM(data_width_p )
,parameter addr_width_lp = `BSG_SAFE_CLOG2(els_p)
,parameter write_mask_width_lp = data_width_p>>3
)
(input clk_i
,input reset_i
,input v_i
,input w_i
,input [addr_width_lp-1:0] addr_i
,input [data_width_p-1:0] data_i
,input [write_mask_width_lp-1:0] write_mask_i
,output [data_width_p-1:0] data_o
);
if ((els_p == 1024) & (data_width_p == 32))
begin : macro
wire [31:0] wen = ~{{8{write_mask_i[3]}}
,{8{write_mask_i[2]}}
,{8{write_mask_i[1]}}
,{8{write_mask_i[0]}}};
tsmc16_1rw_lg10_w32_byte mem
(.CLK (clk_i )
,.Q (data_o) // out
,.CEN (~v_i ) // lo true
,.WEN (wen )
,.GWEN (~w_i ) // lo true
,.A (addr_i) // in
,.D (data_i) // in
,.STOV (1'd0 ) // Self-timing Override - disabled
,.EMA (3'd3 ) // Extra Margin Adjustment - default value
,.EMAW (2'd1 ) // Extra Margin Adjustment Write - default value
,.EMAS (1'd0 ) // Extra Margin Adjustment Sense Amp. - default value
,.RET1N (1'b1 ) // Retention Mode (active low) - disabled
);
end // block: macro
// no hardened version found
else
begin: notmacro
// Instantiate a synthesizale 1rw sync mask write byte
bsg_mem_1rw_sync_mask_write_byte_synth #(.els_p(els_p), .data_width_p(data_width_p)) synth (.*);
end // block: notmacro
// synopsys translate_off
always_comb
assert (data_width_p % 8 == 0)
else $error("data width should be a multiple of 8 for byte masking");
initial
begin
$display("## bsg_mem_1rw_sync_mask_write_byte: instantiating data_width_p=%d, els_p=%d (%m)",data_width_p,els_p);
end
// synopsys translate_on
endmodule
|
module altera_mem_if_ddr3_phy_0001_qsys_sequencer_cpu_inst_test_bench (
// inputs:
D_iw,
D_iw_op,
D_iw_opx,
D_valid,
E_alu_result,
E_mem_byte_en,
E_st_data,
E_valid,
F_pcb,
F_valid,
R_ctrl_exception,
R_ctrl_ld,
R_ctrl_ld_non_io,
R_dst_regnum,
R_wr_dst_reg,
W_bstatus_reg,
W_cmp_result,
W_estatus_reg,
W_ienable_reg,
W_ipending_reg,
W_mem_baddr,
W_rf_wr_data,
W_status_reg,
W_valid,
W_vinst,
W_wr_data,
av_ld_data_aligned_unfiltered,
clk,
d_address,
d_byteenable,
d_read,
d_write_nxt,
i_address,
i_read,
i_readdata,
i_waitrequest,
reset_n,
// outputs:
av_ld_data_aligned_filtered,
d_write,
test_has_ended
)
;
output [ 31: 0] av_ld_data_aligned_filtered;
output d_write;
output test_has_ended;
input [ 31: 0] D_iw;
input [ 5: 0] D_iw_op;
input [ 5: 0] D_iw_opx;
input D_valid;
input [ 31: 0] E_alu_result;
input [ 3: 0] E_mem_byte_en;
input [ 31: 0] E_st_data;
input E_valid;
input [ 16: 0] F_pcb;
input F_valid;
input R_ctrl_exception;
input R_ctrl_ld;
input R_ctrl_ld_non_io;
input [ 4: 0] R_dst_regnum;
input R_wr_dst_reg;
input W_bstatus_reg;
input W_cmp_result;
input W_estatus_reg;
input [ 31: 0] W_ienable_reg;
input [ 31: 0] W_ipending_reg;
input [ 18: 0] W_mem_baddr;
input [ 31: 0] W_rf_wr_data;
input W_status_reg;
input W_valid;
input [ 55: 0] W_vinst;
input [ 31: 0] W_wr_data;
input [ 31: 0] av_ld_data_aligned_unfiltered;
input clk;
input [ 18: 0] d_address;
input [ 3: 0] d_byteenable;
input d_read;
input d_write_nxt;
input [ 16: 0] i_address;
input i_read;
input [ 31: 0] i_readdata;
input i_waitrequest;
input reset_n;
wire D_op_add;
wire D_op_addi;
wire D_op_and;
wire D_op_andhi;
wire D_op_andi;
wire D_op_beq;
wire D_op_bge;
wire D_op_bgeu;
wire D_op_blt;
wire D_op_bltu;
wire D_op_bne;
wire D_op_br;
wire D_op_break;
wire D_op_bret;
wire D_op_call;
wire D_op_callr;
wire D_op_cmpeq;
wire D_op_cmpeqi;
wire D_op_cmpge;
wire D_op_cmpgei;
wire D_op_cmpgeu;
wire D_op_cmpgeui;
wire D_op_cmplt;
wire D_op_cmplti;
wire D_op_cmpltu;
wire D_op_cmpltui;
wire D_op_cmpne;
wire D_op_cmpnei;
wire D_op_crst;
wire D_op_custom;
wire D_op_div;
wire D_op_divu;
wire D_op_eret;
wire D_op_flushd;
wire D_op_flushda;
wire D_op_flushi;
wire D_op_flushp;
wire D_op_hbreak;
wire D_op_initd;
wire D_op_initda;
wire D_op_initi;
wire D_op_intr;
wire D_op_jmp;
wire D_op_jmpi;
wire D_op_ldb;
wire D_op_ldbio;
wire D_op_ldbu;
wire D_op_ldbuio;
wire D_op_ldh;
wire D_op_ldhio;
wire D_op_ldhu;
wire D_op_ldhuio;
wire D_op_ldl;
wire D_op_ldw;
wire D_op_ldwio;
wire D_op_mul;
wire D_op_muli;
wire D_op_mulxss;
wire D_op_mulxsu;
wire D_op_mulxuu;
wire D_op_nextpc;
wire D_op_nor;
wire D_op_opx;
wire D_op_or;
wire D_op_orhi;
wire D_op_ori;
wire D_op_rdctl;
wire D_op_rdprs;
wire D_op_ret;
wire D_op_rol;
wire D_op_roli;
wire D_op_ror;
wire D_op_rsv02;
wire D_op_rsv09;
wire D_op_rsv10;
wire D_op_rsv17;
wire D_op_rsv18;
wire D_op_rsv25;
wire D_op_rsv26;
wire D_op_rsv33;
wire D_op_rsv34;
wire D_op_rsv41;
wire D_op_rsv42;
wire D_op_rsv49;
wire D_op_rsv57;
wire D_op_rsv61;
wire D_op_rsv62;
wire D_op_rsv63;
wire D_op_rsvx00;
wire D_op_rsvx10;
wire D_op_rsvx15;
wire D_op_rsvx17;
wire D_op_rsvx21;
wire D_op_rsvx25;
wire D_op_rsvx33;
wire D_op_rsvx34;
wire D_op_rsvx35;
wire D_op_rsvx42;
wire D_op_rsvx43;
wire D_op_rsvx44;
wire D_op_rsvx47;
wire D_op_rsvx50;
wire D_op_rsvx51;
wire D_op_rsvx55;
wire D_op_rsvx56;
wire D_op_rsvx60;
wire D_op_rsvx63;
wire D_op_sll;
wire D_op_slli;
wire D_op_sra;
wire D_op_srai;
wire D_op_srl;
wire D_op_srli;
wire D_op_stb;
wire D_op_stbio;
wire D_op_stc;
wire D_op_sth;
wire D_op_sthio;
wire D_op_stw;
wire D_op_stwio;
wire D_op_sub;
wire D_op_sync;
wire D_op_trap;
wire D_op_wrctl;
wire D_op_wrprs;
wire D_op_xor;
wire D_op_xorhi;
wire D_op_xori;
wire [ 31: 0] av_ld_data_aligned_filtered;
wire av_ld_data_aligned_unfiltered_0_is_x;
wire av_ld_data_aligned_unfiltered_10_is_x;
wire av_ld_data_aligned_unfiltered_11_is_x;
wire av_ld_data_aligned_unfiltered_12_is_x;
wire av_ld_data_aligned_unfiltered_13_is_x;
wire av_ld_data_aligned_unfiltered_14_is_x;
wire av_ld_data_aligned_unfiltered_15_is_x;
wire av_ld_data_aligned_unfiltered_16_is_x;
wire av_ld_data_aligned_unfiltered_17_is_x;
wire av_ld_data_aligned_unfiltered_18_is_x;
wire av_ld_data_aligned_unfiltered_19_is_x;
wire av_ld_data_aligned_unfiltered_1_is_x;
wire av_ld_data_aligned_unfiltered_20_is_x;
wire av_ld_data_aligned_unfiltered_21_is_x;
wire av_ld_data_aligned_unfiltered_22_is_x;
wire av_ld_data_aligned_unfiltered_23_is_x;
wire av_ld_data_aligned_unfiltered_24_is_x;
wire av_ld_data_aligned_unfiltered_25_is_x;
wire av_ld_data_aligned_unfiltered_26_is_x;
wire av_ld_data_aligned_unfiltered_27_is_x;
wire av_ld_data_aligned_unfiltered_28_is_x;
wire av_ld_data_aligned_unfiltered_29_is_x;
wire av_ld_data_aligned_unfiltered_2_is_x;
wire av_ld_data_aligned_unfiltered_30_is_x;
wire av_ld_data_aligned_unfiltered_31_is_x;
wire av_ld_data_aligned_unfiltered_3_is_x;
wire av_ld_data_aligned_unfiltered_4_is_x;
wire av_ld_data_aligned_unfiltered_5_is_x;
wire av_ld_data_aligned_unfiltered_6_is_x;
wire av_ld_data_aligned_unfiltered_7_is_x;
wire av_ld_data_aligned_unfiltered_8_is_x;
wire av_ld_data_aligned_unfiltered_9_is_x;
reg d_write;
wire test_has_ended;
assign D_op_call = D_iw_op == 0;
assign D_op_jmpi = D_iw_op == 1;
assign D_op_ldbu = D_iw_op == 3;
assign D_op_addi = D_iw_op == 4;
assign D_op_stb = D_iw_op == 5;
assign D_op_br = D_iw_op == 6;
assign D_op_ldb = D_iw_op == 7;
assign D_op_cmpgei = D_iw_op == 8;
assign D_op_ldhu = D_iw_op == 11;
assign D_op_andi = D_iw_op == 12;
assign D_op_sth = D_iw_op == 13;
assign D_op_bge = D_iw_op == 14;
assign D_op_ldh = D_iw_op == 15;
assign D_op_cmplti = D_iw_op == 16;
assign D_op_initda = D_iw_op == 19;
assign D_op_ori = D_iw_op == 20;
assign D_op_stw = D_iw_op == 21;
assign D_op_blt = D_iw_op == 22;
assign D_op_ldw = D_iw_op == 23;
assign D_op_cmpnei = D_iw_op == 24;
assign D_op_flushda = D_iw_op == 27;
assign D_op_xori = D_iw_op == 28;
assign D_op_stc = D_iw_op == 29;
assign D_op_bne = D_iw_op == 30;
assign D_op_ldl = D_iw_op == 31;
assign D_op_cmpeqi = D_iw_op == 32;
assign D_op_ldbuio = D_iw_op == 35;
assign D_op_muli = D_iw_op == 36;
assign D_op_stbio = D_iw_op == 37;
assign D_op_beq = D_iw_op == 38;
assign D_op_ldbio = D_iw_op == 39;
assign D_op_cmpgeui = D_iw_op == 40;
assign D_op_ldhuio = D_iw_op == 43;
assign D_op_andhi = D_iw_op == 44;
assign D_op_sthio = D_iw_op == 45;
assign D_op_bgeu = D_iw_op == 46;
assign D_op_ldhio = D_iw_op == 47;
assign D_op_cmpltui = D_iw_op == 48;
assign D_op_initd = D_iw_op == 51;
assign D_op_orhi = D_iw_op == 52;
assign D_op_stwio = D_iw_op == 53;
assign D_op_bltu = D_iw_op == 54;
assign D_op_ldwio = D_iw_op == 55;
assign D_op_rdprs = D_iw_op == 56;
assign D_op_flushd = D_iw_op == 59;
assign D_op_xorhi = D_iw_op == 60;
assign D_op_rsv02 = D_iw_op == 2;
assign D_op_rsv09 = D_iw_op == 9;
assign D_op_rsv10 = D_iw_op == 10;
assign D_op_rsv17 = D_iw_op == 17;
assign D_op_rsv18 = D_iw_op == 18;
assign D_op_rsv25 = D_iw_op == 25;
assign D_op_rsv26 = D_iw_op == 26;
assign D_op_rsv33 = D_iw_op == 33;
assign D_op_rsv34 = D_iw_op == 34;
assign D_op_rsv41 = D_iw_op == 41;
assign D_op_rsv42 = D_iw_op == 42;
assign D_op_rsv49 = D_iw_op == 49;
assign D_op_rsv57 = D_iw_op == 57;
assign D_op_rsv61 = D_iw_op == 61;
assign D_op_rsv62 = D_iw_op == 62;
assign D_op_rsv63 = D_iw_op == 63;
assign D_op_eret = D_op_opx & (D_iw_opx == 1);
assign D_op_roli = D_op_opx & (D_iw_opx == 2);
assign D_op_rol = D_op_opx & (D_iw_opx == 3);
assign D_op_flushp = D_op_opx & (D_iw_opx == 4);
assign D_op_ret = D_op_opx & (D_iw_opx == 5);
assign D_op_nor = D_op_opx & (D_iw_opx == 6);
assign D_op_mulxuu = D_op_opx & (D_iw_opx == 7);
assign D_op_cmpge = D_op_opx & (D_iw_opx == 8);
assign D_op_bret = D_op_opx & (D_iw_opx == 9);
assign D_op_ror = D_op_opx & (D_iw_opx == 11);
assign D_op_flushi = D_op_opx & (D_iw_opx == 12);
assign D_op_jmp = D_op_opx & (D_iw_opx == 13);
assign D_op_and = D_op_opx & (D_iw_opx == 14);
assign D_op_cmplt = D_op_opx & (D_iw_opx == 16);
assign D_op_slli = D_op_opx & (D_iw_opx == 18);
assign D_op_sll = D_op_opx & (D_iw_opx == 19);
assign D_op_wrprs = D_op_opx & (D_iw_opx == 20);
assign D_op_or = D_op_opx & (D_iw_opx == 22);
assign D_op_mulxsu = D_op_opx & (D_iw_opx == 23);
assign D_op_cmpne = D_op_opx & (D_iw_opx == 24);
assign D_op_srli = D_op_opx & (D_iw_opx == 26);
assign D_op_srl = D_op_opx & (D_iw_opx == 27);
assign D_op_nextpc = D_op_opx & (D_iw_opx == 28);
assign D_op_callr = D_op_opx & (D_iw_opx == 29);
assign D_op_xor = D_op_opx & (D_iw_opx == 30);
assign D_op_mulxss = D_op_opx & (D_iw_opx == 31);
assign D_op_cmpeq = D_op_opx & (D_iw_opx == 32);
assign D_op_divu = D_op_opx & (D_iw_opx == 36);
assign D_op_div = D_op_opx & (D_iw_opx == 37);
assign D_op_rdctl = D_op_opx & (D_iw_opx == 38);
assign D_op_mul = D_op_opx & (D_iw_opx == 39);
assign D_op_cmpgeu = D_op_opx & (D_iw_opx == 40);
assign D_op_initi = D_op_opx & (D_iw_opx == 41);
assign D_op_trap = D_op_opx & (D_iw_opx == 45);
assign D_op_wrctl = D_op_opx & (D_iw_opx == 46);
assign D_op_cmpltu = D_op_opx & (D_iw_opx == 48);
assign D_op_add = D_op_opx & (D_iw_opx == 49);
assign D_op_break = D_op_opx & (D_iw_opx == 52);
assign D_op_hbreak = D_op_opx & (D_iw_opx == 53);
assign D_op_sync = D_op_opx & (D_iw_opx == 54);
assign D_op_sub = D_op_opx & (D_iw_opx == 57);
assign D_op_srai = D_op_opx & (D_iw_opx == 58);
assign D_op_sra = D_op_opx & (D_iw_opx == 59);
assign D_op_intr = D_op_opx & (D_iw_opx == 61);
assign D_op_crst = D_op_opx & (D_iw_opx == 62);
assign D_op_rsvx00 = D_op_opx & (D_iw_opx == 0);
assign D_op_rsvx10 = D_op_opx & (D_iw_opx == 10);
assign D_op_rsvx15 = D_op_opx & (D_iw_opx == 15);
assign D_op_rsvx17 = D_op_opx & (D_iw_opx == 17);
assign D_op_rsvx21 = D_op_opx & (D_iw_opx == 21);
assign D_op_rsvx25 = D_op_opx & (D_iw_opx == 25);
assign D_op_rsvx33 = D_op_opx & (D_iw_opx == 33);
assign D_op_rsvx34 = D_op_opx & (D_iw_opx == 34);
assign D_op_rsvx35 = D_op_opx & (D_iw_opx == 35);
assign D_op_rsvx42 = D_op_opx & (D_iw_opx == 42);
assign D_op_rsvx43 = D_op_opx & (D_iw_opx == 43);
assign D_op_rsvx44 = D_op_opx & (D_iw_opx == 44);
assign D_op_rsvx47 = D_op_opx & (D_iw_opx == 47);
assign D_op_rsvx50 = D_op_opx & (D_iw_opx == 50);
assign D_op_rsvx51 = D_op_opx & (D_iw_opx == 51);
assign D_op_rsvx55 = D_op_opx & (D_iw_opx == 55);
assign D_op_rsvx56 = D_op_opx & (D_iw_opx == 56);
assign D_op_rsvx60 = D_op_opx & (D_iw_opx == 60);
assign D_op_rsvx63 = D_op_opx & (D_iw_opx == 63);
assign D_op_opx = D_iw_op == 58;
assign D_op_custom = D_iw_op == 50;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
d_write <= 0;
else
d_write <= d_write_nxt;
end
assign test_has_ended = 1'b0;
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
//Clearing 'X' data bits
assign av_ld_data_aligned_unfiltered_0_is_x = ^(av_ld_data_aligned_unfiltered[0]) === 1'bx;
assign av_ld_data_aligned_filtered[0] = (av_ld_data_aligned_unfiltered_0_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[0];
assign av_ld_data_aligned_unfiltered_1_is_x = ^(av_ld_data_aligned_unfiltered[1]) === 1'bx;
assign av_ld_data_aligned_filtered[1] = (av_ld_data_aligned_unfiltered_1_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[1];
assign av_ld_data_aligned_unfiltered_2_is_x = ^(av_ld_data_aligned_unfiltered[2]) === 1'bx;
assign av_ld_data_aligned_filtered[2] = (av_ld_data_aligned_unfiltered_2_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[2];
assign av_ld_data_aligned_unfiltered_3_is_x = ^(av_ld_data_aligned_unfiltered[3]) === 1'bx;
assign av_ld_data_aligned_filtered[3] = (av_ld_data_aligned_unfiltered_3_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[3];
assign av_ld_data_aligned_unfiltered_4_is_x = ^(av_ld_data_aligned_unfiltered[4]) === 1'bx;
assign av_ld_data_aligned_filtered[4] = (av_ld_data_aligned_unfiltered_4_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[4];
assign av_ld_data_aligned_unfiltered_5_is_x = ^(av_ld_data_aligned_unfiltered[5]) === 1'bx;
assign av_ld_data_aligned_filtered[5] = (av_ld_data_aligned_unfiltered_5_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[5];
assign av_ld_data_aligned_unfiltered_6_is_x = ^(av_ld_data_aligned_unfiltered[6]) === 1'bx;
assign av_ld_data_aligned_filtered[6] = (av_ld_data_aligned_unfiltered_6_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[6];
assign av_ld_data_aligned_unfiltered_7_is_x = ^(av_ld_data_aligned_unfiltered[7]) === 1'bx;
assign av_ld_data_aligned_filtered[7] = (av_ld_data_aligned_unfiltered_7_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[7];
assign av_ld_data_aligned_unfiltered_8_is_x = ^(av_ld_data_aligned_unfiltered[8]) === 1'bx;
assign av_ld_data_aligned_filtered[8] = (av_ld_data_aligned_unfiltered_8_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[8];
assign av_ld_data_aligned_unfiltered_9_is_x = ^(av_ld_data_aligned_unfiltered[9]) === 1'bx;
assign av_ld_data_aligned_filtered[9] = (av_ld_data_aligned_unfiltered_9_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[9];
assign av_ld_data_aligned_unfiltered_10_is_x = ^(av_ld_data_aligned_unfiltered[10]) === 1'bx;
assign av_ld_data_aligned_filtered[10] = (av_ld_data_aligned_unfiltered_10_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[10];
assign av_ld_data_aligned_unfiltered_11_is_x = ^(av_ld_data_aligned_unfiltered[11]) === 1'bx;
assign av_ld_data_aligned_filtered[11] = (av_ld_data_aligned_unfiltered_11_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[11];
assign av_ld_data_aligned_unfiltered_12_is_x = ^(av_ld_data_aligned_unfiltered[12]) === 1'bx;
assign av_ld_data_aligned_filtered[12] = (av_ld_data_aligned_unfiltered_12_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[12];
assign av_ld_data_aligned_unfiltered_13_is_x = ^(av_ld_data_aligned_unfiltered[13]) === 1'bx;
assign av_ld_data_aligned_filtered[13] = (av_ld_data_aligned_unfiltered_13_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[13];
assign av_ld_data_aligned_unfiltered_14_is_x = ^(av_ld_data_aligned_unfiltered[14]) === 1'bx;
assign av_ld_data_aligned_filtered[14] = (av_ld_data_aligned_unfiltered_14_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[14];
assign av_ld_data_aligned_unfiltered_15_is_x = ^(av_ld_data_aligned_unfiltered[15]) === 1'bx;
assign av_ld_data_aligned_filtered[15] = (av_ld_data_aligned_unfiltered_15_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[15];
assign av_ld_data_aligned_unfiltered_16_is_x = ^(av_ld_data_aligned_unfiltered[16]) === 1'bx;
assign av_ld_data_aligned_filtered[16] = (av_ld_data_aligned_unfiltered_16_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[16];
assign av_ld_data_aligned_unfiltered_17_is_x = ^(av_ld_data_aligned_unfiltered[17]) === 1'bx;
assign av_ld_data_aligned_filtered[17] = (av_ld_data_aligned_unfiltered_17_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[17];
assign av_ld_data_aligned_unfiltered_18_is_x = ^(av_ld_data_aligned_unfiltered[18]) === 1'bx;
assign av_ld_data_aligned_filtered[18] = (av_ld_data_aligned_unfiltered_18_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[18];
assign av_ld_data_aligned_unfiltered_19_is_x = ^(av_ld_data_aligned_unfiltered[19]) === 1'bx;
assign av_ld_data_aligned_filtered[19] = (av_ld_data_aligned_unfiltered_19_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[19];
assign av_ld_data_aligned_unfiltered_20_is_x = ^(av_ld_data_aligned_unfiltered[20]) === 1'bx;
assign av_ld_data_aligned_filtered[20] = (av_ld_data_aligned_unfiltered_20_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[20];
assign av_ld_data_aligned_unfiltered_21_is_x = ^(av_ld_data_aligned_unfiltered[21]) === 1'bx;
assign av_ld_data_aligned_filtered[21] = (av_ld_data_aligned_unfiltered_21_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[21];
assign av_ld_data_aligned_unfiltered_22_is_x = ^(av_ld_data_aligned_unfiltered[22]) === 1'bx;
assign av_ld_data_aligned_filtered[22] = (av_ld_data_aligned_unfiltered_22_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[22];
assign av_ld_data_aligned_unfiltered_23_is_x = ^(av_ld_data_aligned_unfiltered[23]) === 1'bx;
assign av_ld_data_aligned_filtered[23] = (av_ld_data_aligned_unfiltered_23_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[23];
assign av_ld_data_aligned_unfiltered_24_is_x = ^(av_ld_data_aligned_unfiltered[24]) === 1'bx;
assign av_ld_data_aligned_filtered[24] = (av_ld_data_aligned_unfiltered_24_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[24];
assign av_ld_data_aligned_unfiltered_25_is_x = ^(av_ld_data_aligned_unfiltered[25]) === 1'bx;
assign av_ld_data_aligned_filtered[25] = (av_ld_data_aligned_unfiltered_25_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[25];
assign av_ld_data_aligned_unfiltered_26_is_x = ^(av_ld_data_aligned_unfiltered[26]) === 1'bx;
assign av_ld_data_aligned_filtered[26] = (av_ld_data_aligned_unfiltered_26_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[26];
assign av_ld_data_aligned_unfiltered_27_is_x = ^(av_ld_data_aligned_unfiltered[27]) === 1'bx;
assign av_ld_data_aligned_filtered[27] = (av_ld_data_aligned_unfiltered_27_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[27];
assign av_ld_data_aligned_unfiltered_28_is_x = ^(av_ld_data_aligned_unfiltered[28]) === 1'bx;
assign av_ld_data_aligned_filtered[28] = (av_ld_data_aligned_unfiltered_28_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[28];
assign av_ld_data_aligned_unfiltered_29_is_x = ^(av_ld_data_aligned_unfiltered[29]) === 1'bx;
assign av_ld_data_aligned_filtered[29] = (av_ld_data_aligned_unfiltered_29_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[29];
assign av_ld_data_aligned_unfiltered_30_is_x = ^(av_ld_data_aligned_unfiltered[30]) === 1'bx;
assign av_ld_data_aligned_filtered[30] = (av_ld_data_aligned_unfiltered_30_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[30];
assign av_ld_data_aligned_unfiltered_31_is_x = ^(av_ld_data_aligned_unfiltered[31]) === 1'bx;
assign av_ld_data_aligned_filtered[31] = (av_ld_data_aligned_unfiltered_31_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[31];
always @(posedge clk)
begin
if (reset_n)
if (^(F_valid) === 1'bx)
begin
$write("%0d ns: ERROR: altera_mem_if_ddr3_phy_0001_qsys_sequencer_cpu_inst_test_bench/F_valid is 'x'\n", $time);
$stop;
end
end
always @(posedge clk)
begin
if (reset_n)
if (^(D_valid) === 1'bx)
begin
$write("%0d ns: ERROR: altera_mem_if_ddr3_phy_0001_qsys_sequencer_cpu_inst_test_bench/D_valid is 'x'\n", $time);
$stop;
end
end
always @(posedge clk)
begin
if (reset_n)
if (^(E_valid) === 1'bx)
begin
$write("%0d ns: ERROR: altera_mem_if_ddr3_phy_0001_qsys_sequencer_cpu_inst_test_bench/E_valid is 'x'\n", $time);
$stop;
end
end
always @(posedge clk)
begin
if (reset_n)
if (^(W_valid) === 1'bx)
begin
$write("%0d ns: ERROR: altera_mem_if_ddr3_phy_0001_qsys_sequencer_cpu_inst_test_bench/W_valid is 'x'\n", $time);
$stop;
end
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
end
else if (W_valid)
if (^(R_wr_dst_reg) === 1'bx)
begin
$write("%0d ns: ERROR: altera_mem_if_ddr3_phy_0001_qsys_sequencer_cpu_inst_test_bench/R_wr_dst_reg is 'x'\n", $time);
$stop;
end
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
end
else if (W_valid & R_wr_dst_reg)
if (^(W_wr_data) === 1'bx)
begin
$write("%0d ns: ERROR: altera_mem_if_ddr3_phy_0001_qsys_sequencer_cpu_inst_test_bench/W_wr_data is 'x'\n", $time);
$stop;
end
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
end
else if (W_valid & R_wr_dst_reg)
if (^(R_dst_regnum) === 1'bx)
begin
$write("%0d ns: ERROR: altera_mem_if_ddr3_phy_0001_qsys_sequencer_cpu_inst_test_bench/R_dst_regnum is 'x'\n", $time);
$stop;
end
end
always @(posedge clk)
begin
if (reset_n)
if (^(d_write) === 1'bx)
begin
$write("%0d ns: ERROR: altera_mem_if_ddr3_phy_0001_qsys_sequencer_cpu_inst_test_bench/d_write is 'x'\n", $time);
$stop;
end
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
end
else if (d_write)
if (^(d_byteenable) === 1'bx)
begin
$write("%0d ns: ERROR: altera_mem_if_ddr3_phy_0001_qsys_sequencer_cpu_inst_test_bench/d_byteenable is 'x'\n", $time);
$stop;
end
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
end
else if (d_write | d_read)
if (^(d_address) === 1'bx)
begin
$write("%0d ns: ERROR: altera_mem_if_ddr3_phy_0001_qsys_sequencer_cpu_inst_test_bench/d_address is 'x'\n", $time);
$stop;
end
end
always @(posedge clk)
begin
if (reset_n)
if (^(d_read) === 1'bx)
begin
$write("%0d ns: ERROR: altera_mem_if_ddr3_phy_0001_qsys_sequencer_cpu_inst_test_bench/d_read is 'x'\n", $time);
$stop;
end
end
always @(posedge clk)
begin
if (reset_n)
if (^(i_read) === 1'bx)
begin
$write("%0d ns: ERROR: altera_mem_if_ddr3_phy_0001_qsys_sequencer_cpu_inst_test_bench/i_read is 'x'\n", $time);
$stop;
end
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
end
else if (i_read)
if (^(i_address) === 1'bx)
begin
$write("%0d ns: ERROR: altera_mem_if_ddr3_phy_0001_qsys_sequencer_cpu_inst_test_bench/i_address is 'x'\n", $time);
$stop;
end
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
end
else if (i_read & ~i_waitrequest)
if (^(i_readdata) === 1'bx)
begin
$write("%0d ns: ERROR: altera_mem_if_ddr3_phy_0001_qsys_sequencer_cpu_inst_test_bench/i_readdata is 'x'\n", $time);
$stop;
end
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
end
else if (W_valid & R_ctrl_ld)
if (^(av_ld_data_aligned_unfiltered) === 1'bx)
begin
$write("%0d ns: WARNING: altera_mem_if_ddr3_phy_0001_qsys_sequencer_cpu_inst_test_bench/av_ld_data_aligned_unfiltered is 'x'\n", $time);
end
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
end
else if (W_valid & R_wr_dst_reg)
if (^(W_wr_data) === 1'bx)
begin
$write("%0d ns: WARNING: altera_mem_if_ddr3_phy_0001_qsys_sequencer_cpu_inst_test_bench/W_wr_data is 'x'\n", $time);
end
end
reg [31:0] trace_handle; // for $fopen
initial
begin
trace_handle = $fopen("altera_mem_if_ddr3_phy_0001_qsys_sequencer_cpu_inst.tr");
$fwrite(trace_handle, "version 3\nnumThreads 1\n");
end
always @(posedge clk)
begin
if ((~reset_n || (W_valid)) && ~test_has_ended)
$fwrite(trace_handle, "%0d ns: %0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h\n", $time, ~reset_n, F_pcb, 0, D_op_intr, D_op_hbreak, D_iw, ~(D_op_intr | D_op_hbreak), R_wr_dst_reg, R_dst_regnum, 0, W_rf_wr_data, W_mem_baddr, E_st_data, E_mem_byte_en, W_cmp_result, E_alu_result, W_status_reg, W_estatus_reg, W_bstatus_reg, W_ienable_reg, W_ipending_reg, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, R_ctrl_exception, 0, 0, 0, 0);
end
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
//synthesis read_comments_as_HDL on
//
// assign av_ld_data_aligned_filtered = av_ld_data_aligned_unfiltered;
//
//synthesis read_comments_as_HDL off
endmodule
|
module sky130_fd_sc_hvl__nor3_1 (
Y ,
A ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hvl__nor3 base (
.Y(Y),
.A(A),
.B(B),
.C(C),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
|
module sky130_fd_sc_hvl__nor3_1 (
Y,
A,
B,
C
);
output Y;
input A;
input B;
input C;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hvl__nor3 base (
.Y(Y),
.A(A),
.B(B),
.C(C)
);
endmodule
|
module sky130_fd_sc_ls__udp_dff$NSR (
Q ,
SET ,
RESET,
CLK_N,
D
);
output Q ;
input SET ;
input RESET;
input CLK_N;
input D ;
endmodule
|
module jt51_lin2exp(
input [15:0] lin,
output reg [9:0] man,
output reg [2:0] exp
);
always @(*) begin
casez( lin[15:9] )
// negative numbers
7'b10?????: begin
man = lin[15:6];
exp = 3'd7;
end
7'b110????: begin
man = lin[14:5];
exp = 3'd6;
end
7'b1110???: begin
man = lin[13:4];
exp = 3'd5;
end
7'b11110??: begin
man = lin[12:3];
exp = 3'd4;
end
7'b111110?: begin
man = lin[11:2];
exp = 3'd3;
end
7'b1111110: begin
man = lin[10:1];
exp = 3'd2;
end
7'b1111111: begin
man = lin[ 9:0];
exp = 3'd1;
end
// positive numbers
7'b01?????: begin
man = lin[15:6];
exp = 3'd7;
end
7'b001????: begin
man = lin[14:5];
exp = 3'd6;
end
7'b0001???: begin
man = lin[13:4];
exp = 3'd5;
end
7'b00001??: begin
man = lin[12:3];
exp = 3'd4;
end
7'b000001?: begin
man = lin[11:2];
exp = 3'd3;
end
7'b0000001: begin
man = lin[10:1];
exp = 3'd2;
end
7'b0000000: begin
man = lin[ 9:0];
exp = 3'd1;
end
default: begin
man = lin[9:0];
exp = 3'd1;
end
endcase
end
endmodule
|
module pll_base#(
parameter CLKIN_PERIOD = 0.000, // input period in ns, 0..100.000 - MANDATORY, resolution down to 1 ps
parameter BANDWIDTH = "OPTIMIZED", // "OPTIMIZED", "HIGH","LOW"
parameter CLKFBOUT_MULT = 1, // integer 1 to 64 . Together with CLKOUT#_DIVIDE and DIVCLK_DIVIDE
parameter CLKFBOUT_PHASE = 0.000, // CLOCK FEEDBACK phase in degrees (3 significant digits, -360.000...+360.000)
parameter CLKOUT0_PHASE = 0.000, // CLOCK0 phase in degrees (3 significant digits, -360.000...+360.000)
parameter CLKOUT1_PHASE = 0.000, // Initial/static fine phase shift, 1/(56*Fvco) actual step
parameter CLKOUT2_PHASE = 0.000,
parameter CLKOUT3_PHASE = 0.000,
parameter CLKOUT4_PHASE = 0.000,
parameter CLKOUT5_PHASE = 0.000,
parameter CLKOUT0_DUTY_CYCLE= 0.5, // CLOCK 0 output duty factor, 3 significant digits
parameter CLKOUT1_DUTY_CYCLE= 0.5,
parameter CLKOUT2_DUTY_CYCLE= 0.5,
parameter CLKOUT3_DUTY_CYCLE= 0.5,
parameter CLKOUT4_DUTY_CYCLE= 0.5,
parameter CLKOUT5_DUTY_CYCLE= 0.5,
parameter CLKOUT0_DIVIDE = 1, // CLK0 outout divide, integer 1..128
parameter CLKOUT1_DIVIDE = 1, // CLK1 outout divide, integer 1..128 (determins a phase step as a fraction of pi/4)
parameter CLKOUT2_DIVIDE = 1,
parameter CLKOUT3_DIVIDE = 1,
parameter CLKOUT4_DIVIDE = 1,
parameter CLKOUT5_DIVIDE = 1,
parameter DIVCLK_DIVIDE = 1, // Integer 1..106. Divides all outputs with respect to CLKIN
parameter REF_JITTER1 = 0.010, // Expected jitter on CLKIN1 (0.000..0.999)
parameter STARTUP_WAIT = "FALSE" // Delays "DONE" signal until MMCM is locked
)
(
input clkin, // General clock input
input clkfbin, // Feedback clock input
input rst, // asynchronous reset input
input pwrdwn, // power down input
output clkout0, // output 0, HPC BUFR/BUFIO capable
output clkout1, // output 1, HPC BUFR/BUFIO capable
output clkout2, // output 2, HPC BUFR/BUFIO capable
output clkout3, // output 3, HPC BUFR/BUFIO capable
output clkout4, // output 4, HPC BUFR/BUFIO not capable
output clkout5, // output 5, HPC BUFR/BUFIO not capable
output clkfbout, // dedicate feedback output
output locked // PLL locked output
);
PLLE2_BASE #(
.BANDWIDTH (BANDWIDTH),
.CLKFBOUT_MULT (CLKFBOUT_MULT),
.CLKFBOUT_PHASE (CLKFBOUT_PHASE),
.CLKIN1_PERIOD (CLKIN_PERIOD),
.CLKOUT0_DIVIDE (CLKOUT0_DIVIDE),
.CLKOUT0_DUTY_CYCLE (CLKOUT0_DUTY_CYCLE),
.CLKOUT0_PHASE (CLKOUT0_PHASE),
.CLKOUT1_DIVIDE (CLKOUT1_DIVIDE),
.CLKOUT1_DUTY_CYCLE (CLKOUT1_DUTY_CYCLE),
.CLKOUT1_PHASE (CLKOUT1_PHASE),
.CLKOUT2_DIVIDE (CLKOUT2_DIVIDE),
.CLKOUT2_DUTY_CYCLE (CLKOUT2_DUTY_CYCLE),
.CLKOUT2_PHASE (CLKOUT2_PHASE),
.CLKOUT3_DIVIDE (CLKOUT3_DIVIDE),
.CLKOUT3_DUTY_CYCLE (CLKOUT3_DUTY_CYCLE),
.CLKOUT3_PHASE (CLKOUT3_PHASE),
.CLKOUT4_DIVIDE (CLKOUT4_DIVIDE),
.CLKOUT4_DUTY_CYCLE (CLKOUT4_DUTY_CYCLE),
.CLKOUT4_PHASE (CLKOUT4_PHASE),
.CLKOUT5_DIVIDE (CLKOUT5_DIVIDE),
.CLKOUT5_DUTY_CYCLE (CLKOUT5_DUTY_CYCLE),
.CLKOUT5_PHASE (CLKOUT5_PHASE),
.DIVCLK_DIVIDE (DIVCLK_DIVIDE),
.REF_JITTER1 (REF_JITTER1),
.STARTUP_WAIT (STARTUP_WAIT)
) PLLE2_BASE_i (
.CLKFBOUT (clkfbout), // output
.CLKOUT0 (clkout0), // output
.CLKOUT1 (clkout1), // output
.CLKOUT2 (clkout2), // output
.CLKOUT3 (clkout3), // output
.CLKOUT4 (clkout4), // output
.CLKOUT5 (clkout5), // output
.LOCKED (locked), // output
.CLKFBIN (clkfbin), // input
.CLKIN1 (clkin), // input
.PWRDWN (pwrdwn), // input
.RST (rst) // input
);
endmodule
|
module tb_ShiftRegister #(
parameter DATA_BITS = 8,
parameter MATRIX_SIZE = 8,
parameter OUTPUT_SIZE = 2*MATRIX_SIZE-1
) ();
reg clock;
reg reset;
reg load;
reg shift;
reg [DATA_BITS-1:0] data_in [0:MATRIX_SIZE-1][0:OUTPUT_SIZE-1];
wire [DATA_BITS-1:0] data_out [0:MATRIX_SIZE-1];
ShiftRegister #(
.DATA_BITS(DATA_BITS),
.MATRIX_SIZE(MATRIX_SIZE),
.OUTPUT_SIZE(OUTPUT_SIZE)
) DUT (
.clock(clock),
.reset(reset),
.load(load),
.shift(shift),
.data_in(data_in),
.data_out(data_out)
);
integer count;
initial begin
clock = 1'b0;
reset = 1'b0;
load = 1'b0;
shift = 1'b0;
$dumpfile("ShiftRegister.vcd") ;
$dumpvars;
end
always begin
#5 clock = ~clock;
#5 clock = ~clock;
end
always @(data_out) begin
$display("data_out[0] at %0t",data_out[0],$time);
$display("data_out[7] at %0t",data_out[7],$time);
end
initial begin
#10 reset = 1'b1;
#20 reset = 1'b0;
#200
#10 load = 1'b1;
#30
count=0;
for (integer i=0;i<MATRIX_SIZE;i++)
for (integer j =0; j< OUTPUT_SIZE;j++) begin
data_in[i][j]=count;
count= count+1;
end
#10 load = 1'b0;
#100 shift = 1'b1;
#250
#50 shift = 1'b0;
#50 $finish;
end
endmodule
|
module wasca_nios2_gen2_0_cpu_test_bench (
// inputs:
D_iw,
D_iw_op,
D_iw_opx,
D_valid,
E_valid,
F_pcb,
F_valid,
R_ctrl_ld,
R_ctrl_ld_non_io,
R_dst_regnum,
R_wr_dst_reg,
W_valid,
W_vinst,
W_wr_data,
av_ld_data_aligned_unfiltered,
clk,
d_address,
d_byteenable,
d_read,
d_write,
i_address,
i_read,
i_readdata,
i_waitrequest,
reset_n,
// outputs:
av_ld_data_aligned_filtered,
test_has_ended
)
;
output [ 31: 0] av_ld_data_aligned_filtered;
output test_has_ended;
input [ 31: 0] D_iw;
input [ 5: 0] D_iw_op;
input [ 5: 0] D_iw_opx;
input D_valid;
input E_valid;
input [ 19: 0] F_pcb;
input F_valid;
input R_ctrl_ld;
input R_ctrl_ld_non_io;
input [ 4: 0] R_dst_regnum;
input R_wr_dst_reg;
input W_valid;
input [ 71: 0] W_vinst;
input [ 31: 0] W_wr_data;
input [ 31: 0] av_ld_data_aligned_unfiltered;
input clk;
input [ 26: 0] d_address;
input [ 3: 0] d_byteenable;
input d_read;
input d_write;
input [ 19: 0] i_address;
input i_read;
input [ 31: 0] i_readdata;
input i_waitrequest;
input reset_n;
wire D_is_opx_inst;
wire D_op_add;
wire D_op_addi;
wire D_op_and;
wire D_op_andhi;
wire D_op_andi;
wire D_op_beq;
wire D_op_bge;
wire D_op_bgeu;
wire D_op_blt;
wire D_op_bltu;
wire D_op_bne;
wire D_op_br;
wire D_op_break;
wire D_op_bret;
wire D_op_call;
wire D_op_callr;
wire D_op_cmpeq;
wire D_op_cmpeqi;
wire D_op_cmpge;
wire D_op_cmpgei;
wire D_op_cmpgeu;
wire D_op_cmpgeui;
wire D_op_cmplt;
wire D_op_cmplti;
wire D_op_cmpltu;
wire D_op_cmpltui;
wire D_op_cmpne;
wire D_op_cmpnei;
wire D_op_crst;
wire D_op_custom;
wire D_op_div;
wire D_op_divu;
wire D_op_eret;
wire D_op_flushd;
wire D_op_flushda;
wire D_op_flushi;
wire D_op_flushp;
wire D_op_hbreak;
wire D_op_initd;
wire D_op_initda;
wire D_op_initi;
wire D_op_intr;
wire D_op_jmp;
wire D_op_jmpi;
wire D_op_ldb;
wire D_op_ldbio;
wire D_op_ldbu;
wire D_op_ldbuio;
wire D_op_ldh;
wire D_op_ldhio;
wire D_op_ldhu;
wire D_op_ldhuio;
wire D_op_ldl;
wire D_op_ldw;
wire D_op_ldwio;
wire D_op_mul;
wire D_op_muli;
wire D_op_mulxss;
wire D_op_mulxsu;
wire D_op_mulxuu;
wire D_op_nextpc;
wire D_op_nor;
wire D_op_op_rsv02;
wire D_op_op_rsv09;
wire D_op_op_rsv10;
wire D_op_op_rsv17;
wire D_op_op_rsv18;
wire D_op_op_rsv25;
wire D_op_op_rsv26;
wire D_op_op_rsv33;
wire D_op_op_rsv34;
wire D_op_op_rsv41;
wire D_op_op_rsv42;
wire D_op_op_rsv49;
wire D_op_op_rsv57;
wire D_op_op_rsv61;
wire D_op_op_rsv62;
wire D_op_op_rsv63;
wire D_op_opx_rsv00;
wire D_op_opx_rsv10;
wire D_op_opx_rsv15;
wire D_op_opx_rsv17;
wire D_op_opx_rsv21;
wire D_op_opx_rsv25;
wire D_op_opx_rsv33;
wire D_op_opx_rsv34;
wire D_op_opx_rsv35;
wire D_op_opx_rsv42;
wire D_op_opx_rsv43;
wire D_op_opx_rsv44;
wire D_op_opx_rsv47;
wire D_op_opx_rsv50;
wire D_op_opx_rsv51;
wire D_op_opx_rsv55;
wire D_op_opx_rsv56;
wire D_op_opx_rsv60;
wire D_op_opx_rsv63;
wire D_op_or;
wire D_op_orhi;
wire D_op_ori;
wire D_op_rdctl;
wire D_op_rdprs;
wire D_op_ret;
wire D_op_rol;
wire D_op_roli;
wire D_op_ror;
wire D_op_sll;
wire D_op_slli;
wire D_op_sra;
wire D_op_srai;
wire D_op_srl;
wire D_op_srli;
wire D_op_stb;
wire D_op_stbio;
wire D_op_stc;
wire D_op_sth;
wire D_op_sthio;
wire D_op_stw;
wire D_op_stwio;
wire D_op_sub;
wire D_op_sync;
wire D_op_trap;
wire D_op_wrctl;
wire D_op_wrprs;
wire D_op_xor;
wire D_op_xorhi;
wire D_op_xori;
wire [ 31: 0] av_ld_data_aligned_filtered;
wire av_ld_data_aligned_unfiltered_0_is_x;
wire av_ld_data_aligned_unfiltered_10_is_x;
wire av_ld_data_aligned_unfiltered_11_is_x;
wire av_ld_data_aligned_unfiltered_12_is_x;
wire av_ld_data_aligned_unfiltered_13_is_x;
wire av_ld_data_aligned_unfiltered_14_is_x;
wire av_ld_data_aligned_unfiltered_15_is_x;
wire av_ld_data_aligned_unfiltered_16_is_x;
wire av_ld_data_aligned_unfiltered_17_is_x;
wire av_ld_data_aligned_unfiltered_18_is_x;
wire av_ld_data_aligned_unfiltered_19_is_x;
wire av_ld_data_aligned_unfiltered_1_is_x;
wire av_ld_data_aligned_unfiltered_20_is_x;
wire av_ld_data_aligned_unfiltered_21_is_x;
wire av_ld_data_aligned_unfiltered_22_is_x;
wire av_ld_data_aligned_unfiltered_23_is_x;
wire av_ld_data_aligned_unfiltered_24_is_x;
wire av_ld_data_aligned_unfiltered_25_is_x;
wire av_ld_data_aligned_unfiltered_26_is_x;
wire av_ld_data_aligned_unfiltered_27_is_x;
wire av_ld_data_aligned_unfiltered_28_is_x;
wire av_ld_data_aligned_unfiltered_29_is_x;
wire av_ld_data_aligned_unfiltered_2_is_x;
wire av_ld_data_aligned_unfiltered_30_is_x;
wire av_ld_data_aligned_unfiltered_31_is_x;
wire av_ld_data_aligned_unfiltered_3_is_x;
wire av_ld_data_aligned_unfiltered_4_is_x;
wire av_ld_data_aligned_unfiltered_5_is_x;
wire av_ld_data_aligned_unfiltered_6_is_x;
wire av_ld_data_aligned_unfiltered_7_is_x;
wire av_ld_data_aligned_unfiltered_8_is_x;
wire av_ld_data_aligned_unfiltered_9_is_x;
wire test_has_ended;
assign D_op_call = D_iw_op == 0;
assign D_op_jmpi = D_iw_op == 1;
assign D_op_op_rsv02 = D_iw_op == 2;
assign D_op_ldbu = D_iw_op == 3;
assign D_op_addi = D_iw_op == 4;
assign D_op_stb = D_iw_op == 5;
assign D_op_br = D_iw_op == 6;
assign D_op_ldb = D_iw_op == 7;
assign D_op_cmpgei = D_iw_op == 8;
assign D_op_op_rsv09 = D_iw_op == 9;
assign D_op_op_rsv10 = D_iw_op == 10;
assign D_op_ldhu = D_iw_op == 11;
assign D_op_andi = D_iw_op == 12;
assign D_op_sth = D_iw_op == 13;
assign D_op_bge = D_iw_op == 14;
assign D_op_ldh = D_iw_op == 15;
assign D_op_cmplti = D_iw_op == 16;
assign D_op_op_rsv17 = D_iw_op == 17;
assign D_op_op_rsv18 = D_iw_op == 18;
assign D_op_initda = D_iw_op == 19;
assign D_op_ori = D_iw_op == 20;
assign D_op_stw = D_iw_op == 21;
assign D_op_blt = D_iw_op == 22;
assign D_op_ldw = D_iw_op == 23;
assign D_op_cmpnei = D_iw_op == 24;
assign D_op_op_rsv25 = D_iw_op == 25;
assign D_op_op_rsv26 = D_iw_op == 26;
assign D_op_flushda = D_iw_op == 27;
assign D_op_xori = D_iw_op == 28;
assign D_op_stc = D_iw_op == 29;
assign D_op_bne = D_iw_op == 30;
assign D_op_ldl = D_iw_op == 31;
assign D_op_cmpeqi = D_iw_op == 32;
assign D_op_op_rsv33 = D_iw_op == 33;
assign D_op_op_rsv34 = D_iw_op == 34;
assign D_op_ldbuio = D_iw_op == 35;
assign D_op_muli = D_iw_op == 36;
assign D_op_stbio = D_iw_op == 37;
assign D_op_beq = D_iw_op == 38;
assign D_op_ldbio = D_iw_op == 39;
assign D_op_cmpgeui = D_iw_op == 40;
assign D_op_op_rsv41 = D_iw_op == 41;
assign D_op_op_rsv42 = D_iw_op == 42;
assign D_op_ldhuio = D_iw_op == 43;
assign D_op_andhi = D_iw_op == 44;
assign D_op_sthio = D_iw_op == 45;
assign D_op_bgeu = D_iw_op == 46;
assign D_op_ldhio = D_iw_op == 47;
assign D_op_cmpltui = D_iw_op == 48;
assign D_op_op_rsv49 = D_iw_op == 49;
assign D_op_custom = D_iw_op == 50;
assign D_op_initd = D_iw_op == 51;
assign D_op_orhi = D_iw_op == 52;
assign D_op_stwio = D_iw_op == 53;
assign D_op_bltu = D_iw_op == 54;
assign D_op_ldwio = D_iw_op == 55;
assign D_op_rdprs = D_iw_op == 56;
assign D_op_op_rsv57 = D_iw_op == 57;
assign D_op_flushd = D_iw_op == 59;
assign D_op_xorhi = D_iw_op == 60;
assign D_op_op_rsv61 = D_iw_op == 61;
assign D_op_op_rsv62 = D_iw_op == 62;
assign D_op_op_rsv63 = D_iw_op == 63;
assign D_op_opx_rsv00 = (D_iw_opx == 0) & D_is_opx_inst;
assign D_op_eret = (D_iw_opx == 1) & D_is_opx_inst;
assign D_op_roli = (D_iw_opx == 2) & D_is_opx_inst;
assign D_op_rol = (D_iw_opx == 3) & D_is_opx_inst;
assign D_op_flushp = (D_iw_opx == 4) & D_is_opx_inst;
assign D_op_ret = (D_iw_opx == 5) & D_is_opx_inst;
assign D_op_nor = (D_iw_opx == 6) & D_is_opx_inst;
assign D_op_mulxuu = (D_iw_opx == 7) & D_is_opx_inst;
assign D_op_cmpge = (D_iw_opx == 8) & D_is_opx_inst;
assign D_op_bret = (D_iw_opx == 9) & D_is_opx_inst;
assign D_op_opx_rsv10 = (D_iw_opx == 10) & D_is_opx_inst;
assign D_op_ror = (D_iw_opx == 11) & D_is_opx_inst;
assign D_op_flushi = (D_iw_opx == 12) & D_is_opx_inst;
assign D_op_jmp = (D_iw_opx == 13) & D_is_opx_inst;
assign D_op_and = (D_iw_opx == 14) & D_is_opx_inst;
assign D_op_opx_rsv15 = (D_iw_opx == 15) & D_is_opx_inst;
assign D_op_cmplt = (D_iw_opx == 16) & D_is_opx_inst;
assign D_op_opx_rsv17 = (D_iw_opx == 17) & D_is_opx_inst;
assign D_op_slli = (D_iw_opx == 18) & D_is_opx_inst;
assign D_op_sll = (D_iw_opx == 19) & D_is_opx_inst;
assign D_op_wrprs = (D_iw_opx == 20) & D_is_opx_inst;
assign D_op_opx_rsv21 = (D_iw_opx == 21) & D_is_opx_inst;
assign D_op_or = (D_iw_opx == 22) & D_is_opx_inst;
assign D_op_mulxsu = (D_iw_opx == 23) & D_is_opx_inst;
assign D_op_cmpne = (D_iw_opx == 24) & D_is_opx_inst;
assign D_op_opx_rsv25 = (D_iw_opx == 25) & D_is_opx_inst;
assign D_op_srli = (D_iw_opx == 26) & D_is_opx_inst;
assign D_op_srl = (D_iw_opx == 27) & D_is_opx_inst;
assign D_op_nextpc = (D_iw_opx == 28) & D_is_opx_inst;
assign D_op_callr = (D_iw_opx == 29) & D_is_opx_inst;
assign D_op_xor = (D_iw_opx == 30) & D_is_opx_inst;
assign D_op_mulxss = (D_iw_opx == 31) & D_is_opx_inst;
assign D_op_cmpeq = (D_iw_opx == 32) & D_is_opx_inst;
assign D_op_opx_rsv33 = (D_iw_opx == 33) & D_is_opx_inst;
assign D_op_opx_rsv34 = (D_iw_opx == 34) & D_is_opx_inst;
assign D_op_opx_rsv35 = (D_iw_opx == 35) & D_is_opx_inst;
assign D_op_divu = (D_iw_opx == 36) & D_is_opx_inst;
assign D_op_div = (D_iw_opx == 37) & D_is_opx_inst;
assign D_op_rdctl = (D_iw_opx == 38) & D_is_opx_inst;
assign D_op_mul = (D_iw_opx == 39) & D_is_opx_inst;
assign D_op_cmpgeu = (D_iw_opx == 40) & D_is_opx_inst;
assign D_op_initi = (D_iw_opx == 41) & D_is_opx_inst;
assign D_op_opx_rsv42 = (D_iw_opx == 42) & D_is_opx_inst;
assign D_op_opx_rsv43 = (D_iw_opx == 43) & D_is_opx_inst;
assign D_op_opx_rsv44 = (D_iw_opx == 44) & D_is_opx_inst;
assign D_op_trap = (D_iw_opx == 45) & D_is_opx_inst;
assign D_op_wrctl = (D_iw_opx == 46) & D_is_opx_inst;
assign D_op_opx_rsv47 = (D_iw_opx == 47) & D_is_opx_inst;
assign D_op_cmpltu = (D_iw_opx == 48) & D_is_opx_inst;
assign D_op_add = (D_iw_opx == 49) & D_is_opx_inst;
assign D_op_opx_rsv50 = (D_iw_opx == 50) & D_is_opx_inst;
assign D_op_opx_rsv51 = (D_iw_opx == 51) & D_is_opx_inst;
assign D_op_break = (D_iw_opx == 52) & D_is_opx_inst;
assign D_op_hbreak = (D_iw_opx == 53) & D_is_opx_inst;
assign D_op_sync = (D_iw_opx == 54) & D_is_opx_inst;
assign D_op_opx_rsv55 = (D_iw_opx == 55) & D_is_opx_inst;
assign D_op_opx_rsv56 = (D_iw_opx == 56) & D_is_opx_inst;
assign D_op_sub = (D_iw_opx == 57) & D_is_opx_inst;
assign D_op_srai = (D_iw_opx == 58) & D_is_opx_inst;
assign D_op_sra = (D_iw_opx == 59) & D_is_opx_inst;
assign D_op_opx_rsv60 = (D_iw_opx == 60) & D_is_opx_inst;
assign D_op_intr = (D_iw_opx == 61) & D_is_opx_inst;
assign D_op_crst = (D_iw_opx == 62) & D_is_opx_inst;
assign D_op_opx_rsv63 = (D_iw_opx == 63) & D_is_opx_inst;
assign D_is_opx_inst = D_iw_op == 58;
assign test_has_ended = 1'b0;
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
//Clearing 'X' data bits
assign av_ld_data_aligned_unfiltered_0_is_x = ^(av_ld_data_aligned_unfiltered[0]) === 1'bx;
assign av_ld_data_aligned_filtered[0] = (av_ld_data_aligned_unfiltered_0_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[0];
assign av_ld_data_aligned_unfiltered_1_is_x = ^(av_ld_data_aligned_unfiltered[1]) === 1'bx;
assign av_ld_data_aligned_filtered[1] = (av_ld_data_aligned_unfiltered_1_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[1];
assign av_ld_data_aligned_unfiltered_2_is_x = ^(av_ld_data_aligned_unfiltered[2]) === 1'bx;
assign av_ld_data_aligned_filtered[2] = (av_ld_data_aligned_unfiltered_2_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[2];
assign av_ld_data_aligned_unfiltered_3_is_x = ^(av_ld_data_aligned_unfiltered[3]) === 1'bx;
assign av_ld_data_aligned_filtered[3] = (av_ld_data_aligned_unfiltered_3_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[3];
assign av_ld_data_aligned_unfiltered_4_is_x = ^(av_ld_data_aligned_unfiltered[4]) === 1'bx;
assign av_ld_data_aligned_filtered[4] = (av_ld_data_aligned_unfiltered_4_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[4];
assign av_ld_data_aligned_unfiltered_5_is_x = ^(av_ld_data_aligned_unfiltered[5]) === 1'bx;
assign av_ld_data_aligned_filtered[5] = (av_ld_data_aligned_unfiltered_5_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[5];
assign av_ld_data_aligned_unfiltered_6_is_x = ^(av_ld_data_aligned_unfiltered[6]) === 1'bx;
assign av_ld_data_aligned_filtered[6] = (av_ld_data_aligned_unfiltered_6_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[6];
assign av_ld_data_aligned_unfiltered_7_is_x = ^(av_ld_data_aligned_unfiltered[7]) === 1'bx;
assign av_ld_data_aligned_filtered[7] = (av_ld_data_aligned_unfiltered_7_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[7];
assign av_ld_data_aligned_unfiltered_8_is_x = ^(av_ld_data_aligned_unfiltered[8]) === 1'bx;
assign av_ld_data_aligned_filtered[8] = (av_ld_data_aligned_unfiltered_8_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[8];
assign av_ld_data_aligned_unfiltered_9_is_x = ^(av_ld_data_aligned_unfiltered[9]) === 1'bx;
assign av_ld_data_aligned_filtered[9] = (av_ld_data_aligned_unfiltered_9_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[9];
assign av_ld_data_aligned_unfiltered_10_is_x = ^(av_ld_data_aligned_unfiltered[10]) === 1'bx;
assign av_ld_data_aligned_filtered[10] = (av_ld_data_aligned_unfiltered_10_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[10];
assign av_ld_data_aligned_unfiltered_11_is_x = ^(av_ld_data_aligned_unfiltered[11]) === 1'bx;
assign av_ld_data_aligned_filtered[11] = (av_ld_data_aligned_unfiltered_11_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[11];
assign av_ld_data_aligned_unfiltered_12_is_x = ^(av_ld_data_aligned_unfiltered[12]) === 1'bx;
assign av_ld_data_aligned_filtered[12] = (av_ld_data_aligned_unfiltered_12_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[12];
assign av_ld_data_aligned_unfiltered_13_is_x = ^(av_ld_data_aligned_unfiltered[13]) === 1'bx;
assign av_ld_data_aligned_filtered[13] = (av_ld_data_aligned_unfiltered_13_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[13];
assign av_ld_data_aligned_unfiltered_14_is_x = ^(av_ld_data_aligned_unfiltered[14]) === 1'bx;
assign av_ld_data_aligned_filtered[14] = (av_ld_data_aligned_unfiltered_14_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[14];
assign av_ld_data_aligned_unfiltered_15_is_x = ^(av_ld_data_aligned_unfiltered[15]) === 1'bx;
assign av_ld_data_aligned_filtered[15] = (av_ld_data_aligned_unfiltered_15_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[15];
assign av_ld_data_aligned_unfiltered_16_is_x = ^(av_ld_data_aligned_unfiltered[16]) === 1'bx;
assign av_ld_data_aligned_filtered[16] = (av_ld_data_aligned_unfiltered_16_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[16];
assign av_ld_data_aligned_unfiltered_17_is_x = ^(av_ld_data_aligned_unfiltered[17]) === 1'bx;
assign av_ld_data_aligned_filtered[17] = (av_ld_data_aligned_unfiltered_17_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[17];
assign av_ld_data_aligned_unfiltered_18_is_x = ^(av_ld_data_aligned_unfiltered[18]) === 1'bx;
assign av_ld_data_aligned_filtered[18] = (av_ld_data_aligned_unfiltered_18_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[18];
assign av_ld_data_aligned_unfiltered_19_is_x = ^(av_ld_data_aligned_unfiltered[19]) === 1'bx;
assign av_ld_data_aligned_filtered[19] = (av_ld_data_aligned_unfiltered_19_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[19];
assign av_ld_data_aligned_unfiltered_20_is_x = ^(av_ld_data_aligned_unfiltered[20]) === 1'bx;
assign av_ld_data_aligned_filtered[20] = (av_ld_data_aligned_unfiltered_20_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[20];
assign av_ld_data_aligned_unfiltered_21_is_x = ^(av_ld_data_aligned_unfiltered[21]) === 1'bx;
assign av_ld_data_aligned_filtered[21] = (av_ld_data_aligned_unfiltered_21_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[21];
assign av_ld_data_aligned_unfiltered_22_is_x = ^(av_ld_data_aligned_unfiltered[22]) === 1'bx;
assign av_ld_data_aligned_filtered[22] = (av_ld_data_aligned_unfiltered_22_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[22];
assign av_ld_data_aligned_unfiltered_23_is_x = ^(av_ld_data_aligned_unfiltered[23]) === 1'bx;
assign av_ld_data_aligned_filtered[23] = (av_ld_data_aligned_unfiltered_23_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[23];
assign av_ld_data_aligned_unfiltered_24_is_x = ^(av_ld_data_aligned_unfiltered[24]) === 1'bx;
assign av_ld_data_aligned_filtered[24] = (av_ld_data_aligned_unfiltered_24_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[24];
assign av_ld_data_aligned_unfiltered_25_is_x = ^(av_ld_data_aligned_unfiltered[25]) === 1'bx;
assign av_ld_data_aligned_filtered[25] = (av_ld_data_aligned_unfiltered_25_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[25];
assign av_ld_data_aligned_unfiltered_26_is_x = ^(av_ld_data_aligned_unfiltered[26]) === 1'bx;
assign av_ld_data_aligned_filtered[26] = (av_ld_data_aligned_unfiltered_26_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[26];
assign av_ld_data_aligned_unfiltered_27_is_x = ^(av_ld_data_aligned_unfiltered[27]) === 1'bx;
assign av_ld_data_aligned_filtered[27] = (av_ld_data_aligned_unfiltered_27_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[27];
assign av_ld_data_aligned_unfiltered_28_is_x = ^(av_ld_data_aligned_unfiltered[28]) === 1'bx;
assign av_ld_data_aligned_filtered[28] = (av_ld_data_aligned_unfiltered_28_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[28];
assign av_ld_data_aligned_unfiltered_29_is_x = ^(av_ld_data_aligned_unfiltered[29]) === 1'bx;
assign av_ld_data_aligned_filtered[29] = (av_ld_data_aligned_unfiltered_29_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[29];
assign av_ld_data_aligned_unfiltered_30_is_x = ^(av_ld_data_aligned_unfiltered[30]) === 1'bx;
assign av_ld_data_aligned_filtered[30] = (av_ld_data_aligned_unfiltered_30_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[30];
assign av_ld_data_aligned_unfiltered_31_is_x = ^(av_ld_data_aligned_unfiltered[31]) === 1'bx;
assign av_ld_data_aligned_filtered[31] = (av_ld_data_aligned_unfiltered_31_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[31];
always @(posedge clk)
begin
if (reset_n)
if (^(F_valid) === 1'bx)
begin
$write("%0d ns: ERROR: wasca_nios2_gen2_0_cpu_test_bench/F_valid is 'x'\n", $time);
$stop;
end
end
always @(posedge clk)
begin
if (reset_n)
if (^(D_valid) === 1'bx)
begin
$write("%0d ns: ERROR: wasca_nios2_gen2_0_cpu_test_bench/D_valid is 'x'\n", $time);
$stop;
end
end
always @(posedge clk)
begin
if (reset_n)
if (^(E_valid) === 1'bx)
begin
$write("%0d ns: ERROR: wasca_nios2_gen2_0_cpu_test_bench/E_valid is 'x'\n", $time);
$stop;
end
end
always @(posedge clk)
begin
if (reset_n)
if (^(W_valid) === 1'bx)
begin
$write("%0d ns: ERROR: wasca_nios2_gen2_0_cpu_test_bench/W_valid is 'x'\n", $time);
$stop;
end
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
end
else if (W_valid)
if (^(R_wr_dst_reg) === 1'bx)
begin
$write("%0d ns: ERROR: wasca_nios2_gen2_0_cpu_test_bench/R_wr_dst_reg is 'x'\n", $time);
$stop;
end
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
end
else if (W_valid & R_wr_dst_reg)
if (^(W_wr_data) === 1'bx)
begin
$write("%0d ns: ERROR: wasca_nios2_gen2_0_cpu_test_bench/W_wr_data is 'x'\n", $time);
$stop;
end
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
end
else if (W_valid & R_wr_dst_reg)
if (^(R_dst_regnum) === 1'bx)
begin
$write("%0d ns: ERROR: wasca_nios2_gen2_0_cpu_test_bench/R_dst_regnum is 'x'\n", $time);
$stop;
end
end
always @(posedge clk)
begin
if (reset_n)
if (^(d_write) === 1'bx)
begin
$write("%0d ns: ERROR: wasca_nios2_gen2_0_cpu_test_bench/d_write is 'x'\n", $time);
$stop;
end
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
end
else if (d_write)
if (^(d_byteenable) === 1'bx)
begin
$write("%0d ns: ERROR: wasca_nios2_gen2_0_cpu_test_bench/d_byteenable is 'x'\n", $time);
$stop;
end
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
end
else if (d_write | d_read)
if (^(d_address) === 1'bx)
begin
$write("%0d ns: ERROR: wasca_nios2_gen2_0_cpu_test_bench/d_address is 'x'\n", $time);
$stop;
end
end
always @(posedge clk)
begin
if (reset_n)
if (^(d_read) === 1'bx)
begin
$write("%0d ns: ERROR: wasca_nios2_gen2_0_cpu_test_bench/d_read is 'x'\n", $time);
$stop;
end
end
always @(posedge clk)
begin
if (reset_n)
if (^(i_read) === 1'bx)
begin
$write("%0d ns: ERROR: wasca_nios2_gen2_0_cpu_test_bench/i_read is 'x'\n", $time);
$stop;
end
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
end
else if (i_read)
if (^(i_address) === 1'bx)
begin
$write("%0d ns: ERROR: wasca_nios2_gen2_0_cpu_test_bench/i_address is 'x'\n", $time);
$stop;
end
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
end
else if (i_read & ~i_waitrequest)
if (^(i_readdata) === 1'bx)
begin
$write("%0d ns: ERROR: wasca_nios2_gen2_0_cpu_test_bench/i_readdata is 'x'\n", $time);
$stop;
end
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
end
else if (W_valid & R_ctrl_ld)
if (^(av_ld_data_aligned_unfiltered) === 1'bx)
begin
$write("%0d ns: WARNING: wasca_nios2_gen2_0_cpu_test_bench/av_ld_data_aligned_unfiltered is 'x'\n", $time);
end
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
end
else if (W_valid & R_wr_dst_reg)
if (^(W_wr_data) === 1'bx)
begin
$write("%0d ns: WARNING: wasca_nios2_gen2_0_cpu_test_bench/W_wr_data is 'x'\n", $time);
end
end
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
//synthesis read_comments_as_HDL on
//
// assign av_ld_data_aligned_filtered = av_ld_data_aligned_unfiltered;
//
//synthesis read_comments_as_HDL off
endmodule
|
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_GPIO_Core
(GPIO2_DBus_i,
GPIO_DBus_i,
GPIO_xferAck_i,
gpio_xferAck_Reg,
ip2bus_rdack_i,
ip2bus_wrack_i_D1_reg,
gpio_io_o,
gpio_io_t,
gpio2_io_o,
gpio2_io_t,
Q,
\Dual.READ_REG_GEN[0].GPIO_DBus_i_reg[28]_0 ,
Read_Reg_Rst,
Read_Reg2_In,
s_axi_aclk,
Read_Reg_In,
SS,
bus2ip_rnw,
bus2ip_cs,
gpio_io_i,
gpio2_io_i,
E,
s_axi_wdata,
bus2ip_rnw_i_reg,
bus2ip_rnw_i_reg_0,
bus2ip_rnw_i_reg_1);
output [3:0]GPIO2_DBus_i;
output [3:0]GPIO_DBus_i;
output GPIO_xferAck_i;
output gpio_xferAck_Reg;
output ip2bus_rdack_i;
output ip2bus_wrack_i_D1_reg;
output [3:0]gpio_io_o;
output [3:0]gpio_io_t;
output [3:0]gpio2_io_o;
output [3:0]gpio2_io_t;
output [3:0]Q;
output [3:0]\Dual.READ_REG_GEN[0].GPIO_DBus_i_reg[28]_0 ;
input Read_Reg_Rst;
input [0:3]Read_Reg2_In;
input s_axi_aclk;
input [0:3]Read_Reg_In;
input [0:0]SS;
input bus2ip_rnw;
input bus2ip_cs;
input [3:0]gpio_io_i;
input [3:0]gpio2_io_i;
input [0:0]E;
input [3:0]s_axi_wdata;
input [0:0]bus2ip_rnw_i_reg;
input [0:0]bus2ip_rnw_i_reg_0;
input [0:0]bus2ip_rnw_i_reg_1;
wire [3:0]\Dual.READ_REG_GEN[0].GPIO_DBus_i_reg[28]_0 ;
wire [0:0]E;
wire [3:0]GPIO2_DBus_i;
wire [3:0]GPIO_DBus_i;
wire GPIO_xferAck_i;
wire [3:0]Q;
wire [0:3]Read_Reg2_In;
wire [0:3]Read_Reg_In;
wire Read_Reg_Rst;
wire [0:0]SS;
wire bus2ip_cs;
wire bus2ip_rnw;
wire [0:0]bus2ip_rnw_i_reg;
wire [0:0]bus2ip_rnw_i_reg_0;
wire [0:0]bus2ip_rnw_i_reg_1;
wire [3:0]gpio2_io_i;
wire [0:3]gpio2_io_i_d2;
wire [3:0]gpio2_io_o;
wire [3:0]gpio2_io_t;
wire [3:0]gpio_io_i;
wire [0:3]gpio_io_i_d2;
wire [3:0]gpio_io_o;
wire [3:0]gpio_io_t;
wire gpio_xferAck_Reg;
wire iGPIO_xferAck;
wire ip2bus_rdack_i;
wire ip2bus_wrack_i_D1_reg;
wire s_axi_aclk;
wire [3:0]s_axi_wdata;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_cdc_sync \Dual.INPUT_DOUBLE_REGS4
(.gpio_io_i(gpio_io_i),
.s_axi_aclk(s_axi_aclk),
.scndry_vect_out({gpio_io_i_d2[0],gpio_io_i_d2[1],gpio_io_i_d2[2],gpio_io_i_d2[3]}));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_cdc_sync_0 \Dual.INPUT_DOUBLE_REGS5
(.gpio2_io_i(gpio2_io_i),
.s_axi_aclk(s_axi_aclk),
.scndry_vect_out({gpio2_io_i_d2[0],gpio2_io_i_d2[1],gpio2_io_i_d2[2],gpio2_io_i_d2[3]}));
FDRE \Dual.READ_REG2_GEN[0].GPIO2_DBus_i_reg[28]
(.C(s_axi_aclk),
.CE(1'b1),
.D(Read_Reg2_In[0]),
.Q(GPIO2_DBus_i[3]),
.R(Read_Reg_Rst));
FDRE \Dual.READ_REG2_GEN[1].GPIO2_DBus_i_reg[29]
(.C(s_axi_aclk),
.CE(1'b1),
.D(Read_Reg2_In[1]),
.Q(GPIO2_DBus_i[2]),
.R(Read_Reg_Rst));
FDRE \Dual.READ_REG2_GEN[2].GPIO2_DBus_i_reg[30]
(.C(s_axi_aclk),
.CE(1'b1),
.D(Read_Reg2_In[2]),
.Q(GPIO2_DBus_i[1]),
.R(Read_Reg_Rst));
FDRE \Dual.READ_REG2_GEN[3].GPIO2_DBus_i_reg[31]
(.C(s_axi_aclk),
.CE(1'b1),
.D(Read_Reg2_In[3]),
.Q(GPIO2_DBus_i[0]),
.R(Read_Reg_Rst));
FDRE \Dual.READ_REG_GEN[0].GPIO_DBus_i_reg[28]
(.C(s_axi_aclk),
.CE(1'b1),
.D(Read_Reg_In[0]),
.Q(GPIO_DBus_i[3]),
.R(Read_Reg_Rst));
FDRE \Dual.READ_REG_GEN[1].GPIO_DBus_i_reg[29]
(.C(s_axi_aclk),
.CE(1'b1),
.D(Read_Reg_In[1]),
.Q(GPIO_DBus_i[2]),
.R(Read_Reg_Rst));
FDRE \Dual.READ_REG_GEN[2].GPIO_DBus_i_reg[30]
(.C(s_axi_aclk),
.CE(1'b1),
.D(Read_Reg_In[2]),
.Q(GPIO_DBus_i[1]),
.R(Read_Reg_Rst));
FDRE \Dual.READ_REG_GEN[3].GPIO_DBus_i_reg[31]
(.C(s_axi_aclk),
.CE(1'b1),
.D(Read_Reg_In[3]),
.Q(GPIO_DBus_i[0]),
.R(Read_Reg_Rst));
FDRE \Dual.gpio2_Data_In_reg[0]
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio2_io_i_d2[0]),
.Q(Q[3]),
.R(1'b0));
FDRE \Dual.gpio2_Data_In_reg[1]
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio2_io_i_d2[1]),
.Q(Q[2]),
.R(1'b0));
FDRE \Dual.gpio2_Data_In_reg[2]
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio2_io_i_d2[2]),
.Q(Q[1]),
.R(1'b0));
FDRE \Dual.gpio2_Data_In_reg[3]
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio2_io_i_d2[3]),
.Q(Q[0]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Dual.gpio2_Data_Out_reg[0]
(.C(s_axi_aclk),
.CE(bus2ip_rnw_i_reg_0),
.D(s_axi_wdata[3]),
.Q(gpio2_io_o[3]),
.R(SS));
FDRE #(
.INIT(1'b0))
\Dual.gpio2_Data_Out_reg[1]
(.C(s_axi_aclk),
.CE(bus2ip_rnw_i_reg_0),
.D(s_axi_wdata[2]),
.Q(gpio2_io_o[2]),
.R(SS));
FDRE #(
.INIT(1'b0))
\Dual.gpio2_Data_Out_reg[2]
(.C(s_axi_aclk),
.CE(bus2ip_rnw_i_reg_0),
.D(s_axi_wdata[1]),
.Q(gpio2_io_o[1]),
.R(SS));
FDRE #(
.INIT(1'b0))
\Dual.gpio2_Data_Out_reg[3]
(.C(s_axi_aclk),
.CE(bus2ip_rnw_i_reg_0),
.D(s_axi_wdata[0]),
.Q(gpio2_io_o[0]),
.R(SS));
FDSE #(
.INIT(1'b1))
\Dual.gpio2_OE_reg[0]
(.C(s_axi_aclk),
.CE(bus2ip_rnw_i_reg_1),
.D(s_axi_wdata[3]),
.Q(gpio2_io_t[3]),
.S(SS));
FDSE #(
.INIT(1'b1))
\Dual.gpio2_OE_reg[1]
(.C(s_axi_aclk),
.CE(bus2ip_rnw_i_reg_1),
.D(s_axi_wdata[2]),
.Q(gpio2_io_t[2]),
.S(SS));
FDSE #(
.INIT(1'b1))
\Dual.gpio2_OE_reg[2]
(.C(s_axi_aclk),
.CE(bus2ip_rnw_i_reg_1),
.D(s_axi_wdata[1]),
.Q(gpio2_io_t[1]),
.S(SS));
FDSE #(
.INIT(1'b1))
\Dual.gpio2_OE_reg[3]
(.C(s_axi_aclk),
.CE(bus2ip_rnw_i_reg_1),
.D(s_axi_wdata[0]),
.Q(gpio2_io_t[0]),
.S(SS));
FDRE \Dual.gpio_Data_In_reg[0]
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio_io_i_d2[0]),
.Q(\Dual.READ_REG_GEN[0].GPIO_DBus_i_reg[28]_0 [3]),
.R(1'b0));
FDRE \Dual.gpio_Data_In_reg[1]
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio_io_i_d2[1]),
.Q(\Dual.READ_REG_GEN[0].GPIO_DBus_i_reg[28]_0 [2]),
.R(1'b0));
FDRE \Dual.gpio_Data_In_reg[2]
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio_io_i_d2[2]),
.Q(\Dual.READ_REG_GEN[0].GPIO_DBus_i_reg[28]_0 [1]),
.R(1'b0));
FDRE \Dual.gpio_Data_In_reg[3]
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio_io_i_d2[3]),
.Q(\Dual.READ_REG_GEN[0].GPIO_DBus_i_reg[28]_0 [0]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Dual.gpio_Data_Out_reg[0]
(.C(s_axi_aclk),
.CE(E),
.D(s_axi_wdata[3]),
.Q(gpio_io_o[3]),
.R(SS));
FDRE #(
.INIT(1'b0))
\Dual.gpio_Data_Out_reg[1]
(.C(s_axi_aclk),
.CE(E),
.D(s_axi_wdata[2]),
.Q(gpio_io_o[2]),
.R(SS));
FDRE #(
.INIT(1'b0))
\Dual.gpio_Data_Out_reg[2]
(.C(s_axi_aclk),
.CE(E),
.D(s_axi_wdata[1]),
.Q(gpio_io_o[1]),
.R(SS));
FDRE #(
.INIT(1'b0))
\Dual.gpio_Data_Out_reg[3]
(.C(s_axi_aclk),
.CE(E),
.D(s_axi_wdata[0]),
.Q(gpio_io_o[0]),
.R(SS));
FDSE #(
.INIT(1'b1))
\Dual.gpio_OE_reg[0]
(.C(s_axi_aclk),
.CE(bus2ip_rnw_i_reg),
.D(s_axi_wdata[3]),
.Q(gpio_io_t[3]),
.S(SS));
FDSE #(
.INIT(1'b1))
\Dual.gpio_OE_reg[1]
(.C(s_axi_aclk),
.CE(bus2ip_rnw_i_reg),
.D(s_axi_wdata[2]),
.Q(gpio_io_t[2]),
.S(SS));
FDSE #(
.INIT(1'b1))
\Dual.gpio_OE_reg[2]
(.C(s_axi_aclk),
.CE(bus2ip_rnw_i_reg),
.D(s_axi_wdata[1]),
.Q(gpio_io_t[1]),
.S(SS));
FDSE #(
.INIT(1'b1))
\Dual.gpio_OE_reg[3]
(.C(s_axi_aclk),
.CE(bus2ip_rnw_i_reg),
.D(s_axi_wdata[0]),
.Q(gpio_io_t[0]),
.S(SS));
FDRE gpio_xferAck_Reg_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(GPIO_xferAck_i),
.Q(gpio_xferAck_Reg),
.R(SS));
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT3 #(
.INIT(8'h04))
iGPIO_xferAck_i_1
(.I0(GPIO_xferAck_i),
.I1(bus2ip_cs),
.I2(gpio_xferAck_Reg),
.O(iGPIO_xferAck));
FDRE iGPIO_xferAck_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(iGPIO_xferAck),
.Q(GPIO_xferAck_i),
.R(SS));
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT2 #(
.INIT(4'h8))
ip2bus_rdack_i_D1_i_1
(.I0(GPIO_xferAck_i),
.I1(bus2ip_rnw),
.O(ip2bus_rdack_i));
LUT2 #(
.INIT(4'h2))
ip2bus_wrack_i_D1_i_1
(.I0(GPIO_xferAck_i),
.I1(bus2ip_rnw),
.O(ip2bus_wrack_i_D1_reg));
endmodule
|
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_address_decoder
(\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ,
s_axi_arready,
s_axi_wready,
Read_Reg2_In,
E,
\Dual.gpio2_Data_Out_reg[0] ,
D,
Read_Reg_In,
\Dual.gpio_OE_reg[0] ,
\Dual.gpio_Data_Out_reg[0] ,
Read_Reg_Rst,
s_axi_aclk,
Q,
is_read,
ip2bus_rdack_i_D1,
is_write_reg,
ip2bus_wrack_i_D1,
gpio2_io_t,
\Dual.gpio2_Data_In_reg[0] ,
\bus2ip_addr_i_reg[8] ,
bus2ip_rnw_i_reg,
rst_reg,
GPIO2_DBus_i,
GPIO_DBus_i,
gpio_io_t,
\Dual.gpio_Data_In_reg[0] ,
gpio_xferAck_Reg,
GPIO_xferAck_i,
start2,
s_axi_aresetn);
output \MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ;
output s_axi_arready;
output s_axi_wready;
output [0:3]Read_Reg2_In;
output [0:0]E;
output [0:0]\Dual.gpio2_Data_Out_reg[0] ;
output [3:0]D;
output [0:3]Read_Reg_In;
output [0:0]\Dual.gpio_OE_reg[0] ;
output [0:0]\Dual.gpio_Data_Out_reg[0] ;
output Read_Reg_Rst;
input s_axi_aclk;
input [3:0]Q;
input is_read;
input ip2bus_rdack_i_D1;
input is_write_reg;
input ip2bus_wrack_i_D1;
input [3:0]gpio2_io_t;
input [3:0]\Dual.gpio2_Data_In_reg[0] ;
input [2:0]\bus2ip_addr_i_reg[8] ;
input bus2ip_rnw_i_reg;
input rst_reg;
input [3:0]GPIO2_DBus_i;
input [3:0]GPIO_DBus_i;
input [3:0]gpio_io_t;
input [3:0]\Dual.gpio_Data_In_reg[0] ;
input gpio_xferAck_Reg;
input GPIO_xferAck_i;
input start2;
input s_axi_aresetn;
wire [3:0]D;
wire [3:0]\Dual.gpio2_Data_In_reg[0] ;
wire [0:0]\Dual.gpio2_Data_Out_reg[0] ;
wire [3:0]\Dual.gpio_Data_In_reg[0] ;
wire [0:0]\Dual.gpio_Data_Out_reg[0] ;
wire [0:0]\Dual.gpio_OE_reg[0] ;
wire [0:0]E;
wire [3:0]GPIO2_DBus_i;
wire [3:0]GPIO_DBus_i;
wire GPIO_xferAck_i;
wire \MEM_DECODE_GEN[0].cs_out_i[0]_i_1_n_0 ;
wire \MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ;
wire [3:0]Q;
wire [0:3]Read_Reg2_In;
wire [0:3]Read_Reg_In;
wire Read_Reg_Rst;
wire [2:0]\bus2ip_addr_i_reg[8] ;
wire bus2ip_rnw_i_reg;
wire [3:0]gpio2_io_t;
wire [3:0]gpio_io_t;
wire gpio_xferAck_Reg;
wire ip2bus_rdack_i_D1;
wire ip2bus_wrack_i_D1;
wire is_read;
wire is_write_reg;
wire rst_reg;
wire s_axi_aclk;
wire s_axi_aresetn;
wire s_axi_arready;
wire s_axi_wready;
wire start2;
LUT6 #(
.INIT(64'h0A0000000C000000))
\Dual.READ_REG2_GEN[0].GPIO2_DBus_i[28]_i_1
(.I0(gpio2_io_t[3]),
.I1(\Dual.gpio2_Data_In_reg[0] [3]),
.I2(\bus2ip_addr_i_reg[8] [2]),
.I3(\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ),
.I4(\bus2ip_addr_i_reg[8] [1]),
.I5(\bus2ip_addr_i_reg[8] [0]),
.O(Read_Reg2_In[0]));
LUT6 #(
.INIT(64'h0A0000000C000000))
\Dual.READ_REG2_GEN[1].GPIO2_DBus_i[29]_i_1
(.I0(gpio2_io_t[2]),
.I1(\Dual.gpio2_Data_In_reg[0] [2]),
.I2(\bus2ip_addr_i_reg[8] [2]),
.I3(\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ),
.I4(\bus2ip_addr_i_reg[8] [1]),
.I5(\bus2ip_addr_i_reg[8] [0]),
.O(Read_Reg2_In[1]));
LUT6 #(
.INIT(64'h0A0000000C000000))
\Dual.READ_REG2_GEN[2].GPIO2_DBus_i[30]_i_1
(.I0(gpio2_io_t[1]),
.I1(\Dual.gpio2_Data_In_reg[0] [1]),
.I2(\bus2ip_addr_i_reg[8] [2]),
.I3(\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ),
.I4(\bus2ip_addr_i_reg[8] [1]),
.I5(\bus2ip_addr_i_reg[8] [0]),
.O(Read_Reg2_In[2]));
LUT4 #(
.INIT(16'hFFDF))
\Dual.READ_REG2_GEN[3].GPIO2_DBus_i[31]_i_1
(.I0(\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ),
.I1(gpio_xferAck_Reg),
.I2(bus2ip_rnw_i_reg),
.I3(GPIO_xferAck_i),
.O(Read_Reg_Rst));
LUT6 #(
.INIT(64'h0A0000000C000000))
\Dual.READ_REG2_GEN[3].GPIO2_DBus_i[31]_i_2
(.I0(gpio2_io_t[0]),
.I1(\Dual.gpio2_Data_In_reg[0] [0]),
.I2(\bus2ip_addr_i_reg[8] [2]),
.I3(\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ),
.I4(\bus2ip_addr_i_reg[8] [1]),
.I5(\bus2ip_addr_i_reg[8] [0]),
.O(Read_Reg2_In[3]));
LUT6 #(
.INIT(64'h000A0000000C0000))
\Dual.READ_REG_GEN[0].GPIO_DBus_i[28]_i_1
(.I0(gpio_io_t[3]),
.I1(\Dual.gpio_Data_In_reg[0] [3]),
.I2(\bus2ip_addr_i_reg[8] [1]),
.I3(\bus2ip_addr_i_reg[8] [2]),
.I4(\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ),
.I5(\bus2ip_addr_i_reg[8] [0]),
.O(Read_Reg_In[0]));
LUT6 #(
.INIT(64'h000A0000000C0000))
\Dual.READ_REG_GEN[1].GPIO_DBus_i[29]_i_1
(.I0(gpio_io_t[2]),
.I1(\Dual.gpio_Data_In_reg[0] [2]),
.I2(\bus2ip_addr_i_reg[8] [1]),
.I3(\bus2ip_addr_i_reg[8] [2]),
.I4(\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ),
.I5(\bus2ip_addr_i_reg[8] [0]),
.O(Read_Reg_In[1]));
LUT6 #(
.INIT(64'h000A0000000C0000))
\Dual.READ_REG_GEN[2].GPIO_DBus_i[30]_i_1
(.I0(gpio_io_t[1]),
.I1(\Dual.gpio_Data_In_reg[0] [1]),
.I2(\bus2ip_addr_i_reg[8] [1]),
.I3(\bus2ip_addr_i_reg[8] [2]),
.I4(\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ),
.I5(\bus2ip_addr_i_reg[8] [0]),
.O(Read_Reg_In[2]));
LUT6 #(
.INIT(64'h000A0000000C0000))
\Dual.READ_REG_GEN[3].GPIO_DBus_i[31]_i_1
(.I0(gpio_io_t[0]),
.I1(\Dual.gpio_Data_In_reg[0] [0]),
.I2(\bus2ip_addr_i_reg[8] [1]),
.I3(\bus2ip_addr_i_reg[8] [2]),
.I4(\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ),
.I5(\bus2ip_addr_i_reg[8] [0]),
.O(Read_Reg_In[3]));
LUT6 #(
.INIT(64'hFFFFFFFF00001000))
\Dual.gpio2_Data_Out[0]_i_1
(.I0(bus2ip_rnw_i_reg),
.I1(\bus2ip_addr_i_reg[8] [2]),
.I2(\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ),
.I3(\bus2ip_addr_i_reg[8] [1]),
.I4(\bus2ip_addr_i_reg[8] [0]),
.I5(rst_reg),
.O(\Dual.gpio2_Data_Out_reg[0] ));
LUT6 #(
.INIT(64'hFFFFFFFF10000000))
\Dual.gpio2_OE[0]_i_1
(.I0(bus2ip_rnw_i_reg),
.I1(\bus2ip_addr_i_reg[8] [2]),
.I2(\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ),
.I3(\bus2ip_addr_i_reg[8] [1]),
.I4(\bus2ip_addr_i_reg[8] [0]),
.I5(rst_reg),
.O(E));
LUT6 #(
.INIT(64'hFFFFFFFF00000100))
\Dual.gpio_Data_Out[0]_i_1
(.I0(bus2ip_rnw_i_reg),
.I1(\bus2ip_addr_i_reg[8] [1]),
.I2(\bus2ip_addr_i_reg[8] [2]),
.I3(\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ),
.I4(\bus2ip_addr_i_reg[8] [0]),
.I5(rst_reg),
.O(\Dual.gpio_Data_Out_reg[0] ));
LUT6 #(
.INIT(64'hFFFFFFFF00040000))
\Dual.gpio_OE[0]_i_1
(.I0(bus2ip_rnw_i_reg),
.I1(\bus2ip_addr_i_reg[8] [0]),
.I2(\bus2ip_addr_i_reg[8] [1]),
.I3(\bus2ip_addr_i_reg[8] [2]),
.I4(\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ),
.I5(rst_reg),
.O(\Dual.gpio_OE_reg[0] ));
LUT5 #(
.INIT(32'h000E0000))
\MEM_DECODE_GEN[0].cs_out_i[0]_i_1
(.I0(\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ),
.I1(start2),
.I2(s_axi_wready),
.I3(s_axi_arready),
.I4(s_axi_aresetn),
.O(\MEM_DECODE_GEN[0].cs_out_i[0]_i_1_n_0 ));
FDRE \MEM_DECODE_GEN[0].cs_out_i_reg[0]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\MEM_DECODE_GEN[0].cs_out_i[0]_i_1_n_0 ),
.Q(\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ),
.R(1'b0));
LUT6 #(
.INIT(64'hABAAAAAAA8AAAAAA))
\ip2bus_data_i_D1[28]_i_1
(.I0(GPIO2_DBus_i[3]),
.I1(\bus2ip_addr_i_reg[8] [1]),
.I2(\bus2ip_addr_i_reg[8] [2]),
.I3(\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ),
.I4(bus2ip_rnw_i_reg),
.I5(GPIO_DBus_i[3]),
.O(D[3]));
LUT6 #(
.INIT(64'hABAAAAAAA8AAAAAA))
\ip2bus_data_i_D1[29]_i_1
(.I0(GPIO2_DBus_i[2]),
.I1(\bus2ip_addr_i_reg[8] [1]),
.I2(\bus2ip_addr_i_reg[8] [2]),
.I3(\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ),
.I4(bus2ip_rnw_i_reg),
.I5(GPIO_DBus_i[2]),
.O(D[2]));
LUT6 #(
.INIT(64'hABAAAAAAA8AAAAAA))
\ip2bus_data_i_D1[30]_i_1
(.I0(GPIO2_DBus_i[1]),
.I1(\bus2ip_addr_i_reg[8] [1]),
.I2(\bus2ip_addr_i_reg[8] [2]),
.I3(\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ),
.I4(bus2ip_rnw_i_reg),
.I5(GPIO_DBus_i[1]),
.O(D[1]));
LUT6 #(
.INIT(64'hABAAAAAAA8AAAAAA))
\ip2bus_data_i_D1[31]_i_1
(.I0(GPIO2_DBus_i[0]),
.I1(\bus2ip_addr_i_reg[8] [1]),
.I2(\bus2ip_addr_i_reg[8] [2]),
.I3(\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ),
.I4(bus2ip_rnw_i_reg),
.I5(GPIO_DBus_i[0]),
.O(D[0]));
LUT6 #(
.INIT(64'hFFFFFFFF00020000))
s_axi_arready_INST_0
(.I0(Q[3]),
.I1(Q[2]),
.I2(Q[1]),
.I3(Q[0]),
.I4(is_read),
.I5(ip2bus_rdack_i_D1),
.O(s_axi_arready));
LUT6 #(
.INIT(64'hFFFFFFFF00020000))
s_axi_wready_INST_0
(.I0(Q[3]),
.I1(Q[2]),
.I2(Q[1]),
.I3(Q[0]),
.I4(is_write_reg),
.I5(ip2bus_wrack_i_D1),
.O(s_axi_wready));
endmodule
|
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_gpio
(s_axi_aclk,
s_axi_aresetn,
s_axi_awaddr,
s_axi_awvalid,
s_axi_awready,
s_axi_wdata,
s_axi_wstrb,
s_axi_wvalid,
s_axi_wready,
s_axi_bresp,
s_axi_bvalid,
s_axi_bready,
s_axi_araddr,
s_axi_arvalid,
s_axi_arready,
s_axi_rdata,
s_axi_rresp,
s_axi_rvalid,
s_axi_rready,
ip2intc_irpt,
gpio_io_i,
gpio_io_o,
gpio_io_t,
gpio2_io_i,
gpio2_io_o,
gpio2_io_t);
(* max_fanout = "10000" *) (* sigis = "Clk" *) input s_axi_aclk;
(* max_fanout = "10000" *) (* sigis = "Rst" *) input s_axi_aresetn;
input [8:0]s_axi_awaddr;
input s_axi_awvalid;
output s_axi_awready;
input [31:0]s_axi_wdata;
input [3:0]s_axi_wstrb;
input s_axi_wvalid;
output s_axi_wready;
output [1:0]s_axi_bresp;
output s_axi_bvalid;
input s_axi_bready;
input [8:0]s_axi_araddr;
input s_axi_arvalid;
output s_axi_arready;
output [31:0]s_axi_rdata;
output [1:0]s_axi_rresp;
output s_axi_rvalid;
input s_axi_rready;
(* sigis = "INTR_LEVEL_HIGH" *) output ip2intc_irpt;
input [3:0]gpio_io_i;
output [3:0]gpio_io_o;
output [3:0]gpio_io_t;
input [3:0]gpio2_io_i;
output [3:0]gpio2_io_o;
output [3:0]gpio2_io_t;
wire \<const0> ;
wire AXI_LITE_IPIF_I_n_11;
wire AXI_LITE_IPIF_I_n_12;
wire AXI_LITE_IPIF_I_n_21;
wire AXI_LITE_IPIF_I_n_22;
wire [28:31]GPIO2_DBus_i;
wire [3:0]GPIO_DBus;
wire [28:31]GPIO_DBus_i;
wire GPIO_xferAck_i;
wire [0:3]Read_Reg2_In;
wire [0:3]Read_Reg_In;
wire Read_Reg_Rst;
wire bus2ip_cs;
wire bus2ip_reset;
wire bus2ip_rnw;
wire [0:3]gpio2_Data_In;
wire [3:0]gpio2_io_i;
wire [3:0]gpio2_io_o;
wire [3:0]gpio2_io_t;
wire [0:3]gpio_Data_In;
wire gpio_core_1_n_11;
wire [3:0]gpio_io_i;
wire [3:0]gpio_io_o;
wire [3:0]gpio_io_t;
wire gpio_xferAck_Reg;
wire [3:0]ip2bus_data_i_D1;
wire ip2bus_rdack_i;
wire ip2bus_rdack_i_D1;
wire ip2bus_wrack_i_D1;
(* MAX_FANOUT = "10000" *) (* RTL_MAX_FANOUT = "found" *) (* sigis = "Clk" *) wire s_axi_aclk;
wire [8:0]s_axi_araddr;
(* MAX_FANOUT = "10000" *) (* RTL_MAX_FANOUT = "found" *) (* sigis = "Rst" *) wire s_axi_aresetn;
wire s_axi_arready;
wire s_axi_arvalid;
wire [8:0]s_axi_awaddr;
wire s_axi_awvalid;
wire s_axi_bready;
wire s_axi_bvalid;
wire [3:0]\^s_axi_rdata ;
wire s_axi_rready;
wire s_axi_rvalid;
wire [31:0]s_axi_wdata;
wire s_axi_wready;
wire s_axi_wvalid;
assign ip2intc_irpt = \<const0> ;
assign s_axi_awready = s_axi_wready;
assign s_axi_bresp[1] = \<const0> ;
assign s_axi_bresp[0] = \<const0> ;
assign s_axi_rdata[31] = \<const0> ;
assign s_axi_rdata[30] = \<const0> ;
assign s_axi_rdata[29] = \<const0> ;
assign s_axi_rdata[28] = \<const0> ;
assign s_axi_rdata[27] = \<const0> ;
assign s_axi_rdata[26] = \<const0> ;
assign s_axi_rdata[25] = \<const0> ;
assign s_axi_rdata[24] = \<const0> ;
assign s_axi_rdata[23] = \<const0> ;
assign s_axi_rdata[22] = \<const0> ;
assign s_axi_rdata[21] = \<const0> ;
assign s_axi_rdata[20] = \<const0> ;
assign s_axi_rdata[19] = \<const0> ;
assign s_axi_rdata[18] = \<const0> ;
assign s_axi_rdata[17] = \<const0> ;
assign s_axi_rdata[16] = \<const0> ;
assign s_axi_rdata[15] = \<const0> ;
assign s_axi_rdata[14] = \<const0> ;
assign s_axi_rdata[13] = \<const0> ;
assign s_axi_rdata[12] = \<const0> ;
assign s_axi_rdata[11] = \<const0> ;
assign s_axi_rdata[10] = \<const0> ;
assign s_axi_rdata[9] = \<const0> ;
assign s_axi_rdata[8] = \<const0> ;
assign s_axi_rdata[7] = \<const0> ;
assign s_axi_rdata[6] = \<const0> ;
assign s_axi_rdata[5] = \<const0> ;
assign s_axi_rdata[4] = \<const0> ;
assign s_axi_rdata[3:0] = \^s_axi_rdata [3:0];
assign s_axi_rresp[1] = \<const0> ;
assign s_axi_rresp[0] = \<const0> ;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_lite_ipif AXI_LITE_IPIF_I
(.D(GPIO_DBus),
.\Dual.gpio2_Data_Out_reg[0] (AXI_LITE_IPIF_I_n_12),
.\Dual.gpio_Data_In_reg[0] ({gpio_Data_In[0],gpio_Data_In[1],gpio_Data_In[2],gpio_Data_In[3]}),
.\Dual.gpio_Data_Out_reg[0] (AXI_LITE_IPIF_I_n_22),
.\Dual.gpio_OE_reg[0] (AXI_LITE_IPIF_I_n_21),
.E(AXI_LITE_IPIF_I_n_11),
.GPIO2_DBus_i({GPIO2_DBus_i[28],GPIO2_DBus_i[29],GPIO2_DBus_i[30],GPIO2_DBus_i[31]}),
.GPIO_DBus_i({GPIO_DBus_i[28],GPIO_DBus_i[29],GPIO_DBus_i[30],GPIO_DBus_i[31]}),
.GPIO_xferAck_i(GPIO_xferAck_i),
.Q({gpio2_Data_In[0],gpio2_Data_In[1],gpio2_Data_In[2],gpio2_Data_In[3]}),
.Read_Reg2_In(Read_Reg2_In),
.Read_Reg_In(Read_Reg_In),
.Read_Reg_Rst(Read_Reg_Rst),
.bus2ip_cs(bus2ip_cs),
.bus2ip_reset(bus2ip_reset),
.bus2ip_rnw(bus2ip_rnw),
.gpio2_io_t(gpio2_io_t),
.gpio_io_t(gpio_io_t),
.gpio_xferAck_Reg(gpio_xferAck_Reg),
.\ip2bus_data_i_D1_reg[28] (ip2bus_data_i_D1),
.ip2bus_rdack_i_D1(ip2bus_rdack_i_D1),
.ip2bus_wrack_i_D1(ip2bus_wrack_i_D1),
.s_axi_aclk(s_axi_aclk),
.s_axi_araddr({s_axi_araddr[8],s_axi_araddr[3:2]}),
.s_axi_aresetn(s_axi_aresetn),
.s_axi_arready(s_axi_arready),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_awaddr({s_axi_awaddr[8],s_axi_awaddr[3:2]}),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_bready(s_axi_bready),
.s_axi_bvalid(s_axi_bvalid),
.s_axi_rdata(\^s_axi_rdata ),
.s_axi_rready(s_axi_rready),
.s_axi_rvalid(s_axi_rvalid),
.s_axi_wready(s_axi_wready),
.s_axi_wvalid(s_axi_wvalid));
GND GND
(.G(\<const0> ));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_GPIO_Core gpio_core_1
(.\Dual.READ_REG_GEN[0].GPIO_DBus_i_reg[28]_0 ({gpio_Data_In[0],gpio_Data_In[1],gpio_Data_In[2],gpio_Data_In[3]}),
.E(AXI_LITE_IPIF_I_n_22),
.GPIO2_DBus_i({GPIO2_DBus_i[28],GPIO2_DBus_i[29],GPIO2_DBus_i[30],GPIO2_DBus_i[31]}),
.GPIO_DBus_i({GPIO_DBus_i[28],GPIO_DBus_i[29],GPIO_DBus_i[30],GPIO_DBus_i[31]}),
.GPIO_xferAck_i(GPIO_xferAck_i),
.Q({gpio2_Data_In[0],gpio2_Data_In[1],gpio2_Data_In[2],gpio2_Data_In[3]}),
.Read_Reg2_In(Read_Reg2_In),
.Read_Reg_In(Read_Reg_In),
.Read_Reg_Rst(Read_Reg_Rst),
.SS(bus2ip_reset),
.bus2ip_cs(bus2ip_cs),
.bus2ip_rnw(bus2ip_rnw),
.bus2ip_rnw_i_reg(AXI_LITE_IPIF_I_n_21),
.bus2ip_rnw_i_reg_0(AXI_LITE_IPIF_I_n_12),
.bus2ip_rnw_i_reg_1(AXI_LITE_IPIF_I_n_11),
.gpio2_io_i(gpio2_io_i),
.gpio2_io_o(gpio2_io_o),
.gpio2_io_t(gpio2_io_t),
.gpio_io_i(gpio_io_i),
.gpio_io_o(gpio_io_o),
.gpio_io_t(gpio_io_t),
.gpio_xferAck_Reg(gpio_xferAck_Reg),
.ip2bus_rdack_i(ip2bus_rdack_i),
.ip2bus_wrack_i_D1_reg(gpio_core_1_n_11),
.s_axi_aclk(s_axi_aclk),
.s_axi_wdata(s_axi_wdata[3:0]));
FDRE \ip2bus_data_i_D1_reg[28]
(.C(s_axi_aclk),
.CE(1'b1),
.D(GPIO_DBus[3]),
.Q(ip2bus_data_i_D1[3]),
.R(bus2ip_reset));
FDRE \ip2bus_data_i_D1_reg[29]
(.C(s_axi_aclk),
.CE(1'b1),
.D(GPIO_DBus[2]),
.Q(ip2bus_data_i_D1[2]),
.R(bus2ip_reset));
FDRE \ip2bus_data_i_D1_reg[30]
(.C(s_axi_aclk),
.CE(1'b1),
.D(GPIO_DBus[1]),
.Q(ip2bus_data_i_D1[1]),
.R(bus2ip_reset));
FDRE \ip2bus_data_i_D1_reg[31]
(.C(s_axi_aclk),
.CE(1'b1),
.D(GPIO_DBus[0]),
.Q(ip2bus_data_i_D1[0]),
.R(bus2ip_reset));
FDRE ip2bus_rdack_i_D1_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(ip2bus_rdack_i),
.Q(ip2bus_rdack_i_D1),
.R(bus2ip_reset));
FDRE ip2bus_wrack_i_D1_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio_core_1_n_11),
.Q(ip2bus_wrack_i_D1),
.R(bus2ip_reset));
endmodule
|
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_lite_ipif
(bus2ip_reset,
bus2ip_rnw,
bus2ip_cs,
s_axi_rvalid,
s_axi_bvalid,
s_axi_arready,
s_axi_wready,
Read_Reg2_In,
E,
\Dual.gpio2_Data_Out_reg[0] ,
D,
Read_Reg_In,
\Dual.gpio_OE_reg[0] ,
\Dual.gpio_Data_Out_reg[0] ,
Read_Reg_Rst,
s_axi_rdata,
s_axi_aclk,
s_axi_arvalid,
ip2bus_rdack_i_D1,
ip2bus_wrack_i_D1,
s_axi_bready,
s_axi_rready,
s_axi_awaddr,
s_axi_araddr,
s_axi_awvalid,
s_axi_wvalid,
gpio2_io_t,
Q,
GPIO2_DBus_i,
GPIO_DBus_i,
gpio_io_t,
\Dual.gpio_Data_In_reg[0] ,
s_axi_aresetn,
gpio_xferAck_Reg,
GPIO_xferAck_i,
\ip2bus_data_i_D1_reg[28] );
output bus2ip_reset;
output bus2ip_rnw;
output bus2ip_cs;
output s_axi_rvalid;
output s_axi_bvalid;
output s_axi_arready;
output s_axi_wready;
output [0:3]Read_Reg2_In;
output [0:0]E;
output [0:0]\Dual.gpio2_Data_Out_reg[0] ;
output [3:0]D;
output [0:3]Read_Reg_In;
output [0:0]\Dual.gpio_OE_reg[0] ;
output [0:0]\Dual.gpio_Data_Out_reg[0] ;
output Read_Reg_Rst;
output [3:0]s_axi_rdata;
input s_axi_aclk;
input s_axi_arvalid;
input ip2bus_rdack_i_D1;
input ip2bus_wrack_i_D1;
input s_axi_bready;
input s_axi_rready;
input [2:0]s_axi_awaddr;
input [2:0]s_axi_araddr;
input s_axi_awvalid;
input s_axi_wvalid;
input [3:0]gpio2_io_t;
input [3:0]Q;
input [3:0]GPIO2_DBus_i;
input [3:0]GPIO_DBus_i;
input [3:0]gpio_io_t;
input [3:0]\Dual.gpio_Data_In_reg[0] ;
input s_axi_aresetn;
input gpio_xferAck_Reg;
input GPIO_xferAck_i;
input [3:0]\ip2bus_data_i_D1_reg[28] ;
wire [3:0]D;
wire [0:0]\Dual.gpio2_Data_Out_reg[0] ;
wire [3:0]\Dual.gpio_Data_In_reg[0] ;
wire [0:0]\Dual.gpio_Data_Out_reg[0] ;
wire [0:0]\Dual.gpio_OE_reg[0] ;
wire [0:0]E;
wire [3:0]GPIO2_DBus_i;
wire [3:0]GPIO_DBus_i;
wire GPIO_xferAck_i;
wire [3:0]Q;
wire [0:3]Read_Reg2_In;
wire [0:3]Read_Reg_In;
wire Read_Reg_Rst;
wire bus2ip_cs;
wire bus2ip_reset;
wire bus2ip_rnw;
wire [3:0]gpio2_io_t;
wire [3:0]gpio_io_t;
wire gpio_xferAck_Reg;
wire [3:0]\ip2bus_data_i_D1_reg[28] ;
wire ip2bus_rdack_i_D1;
wire ip2bus_wrack_i_D1;
wire s_axi_aclk;
wire [2:0]s_axi_araddr;
wire s_axi_aresetn;
wire s_axi_arready;
wire s_axi_arvalid;
wire [2:0]s_axi_awaddr;
wire s_axi_awvalid;
wire s_axi_bready;
wire s_axi_bvalid;
wire [3:0]s_axi_rdata;
wire s_axi_rready;
wire s_axi_rvalid;
wire s_axi_wready;
wire s_axi_wvalid;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_slave_attachment I_SLAVE_ATTACHMENT
(.D(D),
.\Dual.gpio2_Data_Out_reg[0] (\Dual.gpio2_Data_Out_reg[0] ),
.\Dual.gpio2_OE_reg[0] (bus2ip_rnw),
.\Dual.gpio_Data_In_reg[0] (\Dual.gpio_Data_In_reg[0] ),
.\Dual.gpio_Data_Out_reg[0] (\Dual.gpio_Data_Out_reg[0] ),
.\Dual.gpio_OE_reg[0] (\Dual.gpio_OE_reg[0] ),
.E(E),
.GPIO2_DBus_i(GPIO2_DBus_i),
.GPIO_DBus_i(GPIO_DBus_i),
.GPIO_xferAck_i(GPIO_xferAck_i),
.\MEM_DECODE_GEN[0].cs_out_i_reg[0] (bus2ip_cs),
.Q(Q),
.Read_Reg2_In(Read_Reg2_In),
.Read_Reg_In(Read_Reg_In),
.Read_Reg_Rst(Read_Reg_Rst),
.bus2ip_rnw_i_reg_0(bus2ip_reset),
.gpio2_io_t(gpio2_io_t),
.gpio_io_t(gpio_io_t),
.gpio_xferAck_Reg(gpio_xferAck_Reg),
.\ip2bus_data_i_D1_reg[28] (\ip2bus_data_i_D1_reg[28] ),
.ip2bus_rdack_i_D1(ip2bus_rdack_i_D1),
.ip2bus_wrack_i_D1(ip2bus_wrack_i_D1),
.s_axi_aclk(s_axi_aclk),
.s_axi_araddr(s_axi_araddr),
.s_axi_aresetn(s_axi_aresetn),
.s_axi_arready(s_axi_arready),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_awaddr(s_axi_awaddr),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_bready(s_axi_bready),
.s_axi_bvalid(s_axi_bvalid),
.s_axi_rdata(s_axi_rdata),
.s_axi_rready(s_axi_rready),
.s_axi_rvalid(s_axi_rvalid),
.s_axi_wready(s_axi_wready),
.s_axi_wvalid(s_axi_wvalid));
endmodule
|
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_cdc_sync
(scndry_vect_out,
gpio_io_i,
s_axi_aclk);
output [3:0]scndry_vect_out;
input [3:0]gpio_io_i;
input s_axi_aclk;
wire [3:0]gpio_io_i;
wire s_axi_aclk;
wire s_level_out_bus_d1_cdc_to_0;
wire s_level_out_bus_d1_cdc_to_1;
wire s_level_out_bus_d1_cdc_to_2;
wire s_level_out_bus_d1_cdc_to_3;
wire s_level_out_bus_d2_0;
wire s_level_out_bus_d2_1;
wire s_level_out_bus_d2_2;
wire s_level_out_bus_d2_3;
wire s_level_out_bus_d3_0;
wire s_level_out_bus_d3_1;
wire s_level_out_bus_d3_2;
wire s_level_out_bus_d3_3;
wire [3:0]scndry_vect_out;
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d1_cdc_to_0),
.Q(s_level_out_bus_d2_0),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d1_cdc_to_1),
.Q(s_level_out_bus_d2_1),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d1_cdc_to_2),
.Q(s_level_out_bus_d2_2),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d1_cdc_to_3),
.Q(s_level_out_bus_d2_3),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d2_0),
.Q(s_level_out_bus_d3_0),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d2_1),
.Q(s_level_out_bus_d3_1),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d2_2),
.Q(s_level_out_bus_d3_2),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d2_3),
.Q(s_level_out_bus_d3_3),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d3_0),
.Q(scndry_vect_out[0]),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d3_1),
.Q(scndry_vect_out[1]),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d3_2),
.Q(scndry_vect_out[2]),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d3_3),
.Q(scndry_vect_out[3]),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[0].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio_io_i[0]),
.Q(s_level_out_bus_d1_cdc_to_0),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[1].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio_io_i[1]),
.Q(s_level_out_bus_d1_cdc_to_1),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[2].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio_io_i[2]),
.Q(s_level_out_bus_d1_cdc_to_2),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[3].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio_io_i[3]),
.Q(s_level_out_bus_d1_cdc_to_3),
.R(1'b0));
endmodule
|
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_cdc_sync_0
(scndry_vect_out,
gpio2_io_i,
s_axi_aclk);
output [3:0]scndry_vect_out;
input [3:0]gpio2_io_i;
input s_axi_aclk;
wire [3:0]gpio2_io_i;
wire s_axi_aclk;
wire s_level_out_bus_d1_cdc_to_0;
wire s_level_out_bus_d1_cdc_to_1;
wire s_level_out_bus_d1_cdc_to_2;
wire s_level_out_bus_d1_cdc_to_3;
wire s_level_out_bus_d2_0;
wire s_level_out_bus_d2_1;
wire s_level_out_bus_d2_2;
wire s_level_out_bus_d2_3;
wire s_level_out_bus_d3_0;
wire s_level_out_bus_d3_1;
wire s_level_out_bus_d3_2;
wire s_level_out_bus_d3_3;
wire [3:0]scndry_vect_out;
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d1_cdc_to_0),
.Q(s_level_out_bus_d2_0),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d1_cdc_to_1),
.Q(s_level_out_bus_d2_1),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d1_cdc_to_2),
.Q(s_level_out_bus_d2_2),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d1_cdc_to_3),
.Q(s_level_out_bus_d2_3),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d2_0),
.Q(s_level_out_bus_d3_0),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d2_1),
.Q(s_level_out_bus_d3_1),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d2_2),
.Q(s_level_out_bus_d3_2),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d2_3),
.Q(s_level_out_bus_d3_3),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d3_0),
.Q(scndry_vect_out[0]),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d3_1),
.Q(scndry_vect_out[1]),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d3_2),
.Q(scndry_vect_out[2]),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d3_3),
.Q(scndry_vect_out[3]),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[0].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio2_io_i[0]),
.Q(s_level_out_bus_d1_cdc_to_0),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[1].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio2_io_i[1]),
.Q(s_level_out_bus_d1_cdc_to_1),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[2].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio2_io_i[2]),
.Q(s_level_out_bus_d1_cdc_to_2),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[3].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio2_io_i[3]),
.Q(s_level_out_bus_d1_cdc_to_3),
.R(1'b0));
endmodule
|
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix
(s_axi_aclk,
s_axi_aresetn,
s_axi_awaddr,
s_axi_awvalid,
s_axi_awready,
s_axi_wdata,
s_axi_wstrb,
s_axi_wvalid,
s_axi_wready,
s_axi_bresp,
s_axi_bvalid,
s_axi_bready,
s_axi_araddr,
s_axi_arvalid,
s_axi_arready,
s_axi_rdata,
s_axi_rresp,
s_axi_rvalid,
s_axi_rready,
gpio_io_i,
gpio2_io_i);
(* x_interface_info = "xilinx.com:signal:clock:1.0 S_AXI_ACLK CLK" *) input s_axi_aclk;
(* x_interface_info = "xilinx.com:signal:reset:1.0 S_AXI_ARESETN RST" *) input s_axi_aresetn;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI AWADDR" *) input [8:0]s_axi_awaddr;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI AWVALID" *) input s_axi_awvalid;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI AWREADY" *) output s_axi_awready;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI WDATA" *) input [31:0]s_axi_wdata;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI WSTRB" *) input [3:0]s_axi_wstrb;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI WVALID" *) input s_axi_wvalid;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI WREADY" *) output s_axi_wready;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI BRESP" *) output [1:0]s_axi_bresp;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI BVALID" *) output s_axi_bvalid;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI BREADY" *) input s_axi_bready;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI ARADDR" *) input [8:0]s_axi_araddr;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI ARVALID" *) input s_axi_arvalid;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI ARREADY" *) output s_axi_arready;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI RDATA" *) output [31:0]s_axi_rdata;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI RRESP" *) output [1:0]s_axi_rresp;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI RVALID" *) output s_axi_rvalid;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI RREADY" *) input s_axi_rready;
(* x_interface_info = "xilinx.com:interface:gpio:1.0 GPIO TRI_I" *) input [3:0]gpio_io_i;
(* x_interface_info = "xilinx.com:interface:gpio:1.0 GPIO2 TRI_I" *) input [3:0]gpio2_io_i;
wire [3:0]gpio2_io_i;
wire [3:0]gpio_io_i;
wire s_axi_aclk;
wire [8:0]s_axi_araddr;
wire s_axi_aresetn;
wire s_axi_arready;
wire s_axi_arvalid;
wire [8:0]s_axi_awaddr;
wire s_axi_awready;
wire s_axi_awvalid;
wire s_axi_bready;
wire [1:0]s_axi_bresp;
wire s_axi_bvalid;
wire [31:0]s_axi_rdata;
wire s_axi_rready;
wire [1:0]s_axi_rresp;
wire s_axi_rvalid;
wire [31:0]s_axi_wdata;
wire s_axi_wready;
wire [3:0]s_axi_wstrb;
wire s_axi_wvalid;
wire NLW_U0_ip2intc_irpt_UNCONNECTED;
wire [3:0]NLW_U0_gpio2_io_o_UNCONNECTED;
wire [3:0]NLW_U0_gpio2_io_t_UNCONNECTED;
wire [3:0]NLW_U0_gpio_io_o_UNCONNECTED;
wire [3:0]NLW_U0_gpio_io_t_UNCONNECTED;
(* C_ALL_INPUTS = "1" *)
(* C_ALL_INPUTS_2 = "1" *)
(* C_ALL_OUTPUTS = "0" *)
(* C_ALL_OUTPUTS_2 = "0" *)
(* C_DOUT_DEFAULT = "0" *)
(* C_DOUT_DEFAULT_2 = "0" *)
(* C_FAMILY = "zynq" *)
(* C_GPIO2_WIDTH = "4" *)
(* C_GPIO_WIDTH = "4" *)
(* C_INTERRUPT_PRESENT = "0" *)
(* C_IS_DUAL = "1" *)
(* C_S_AXI_ADDR_WIDTH = "9" *)
(* C_S_AXI_DATA_WIDTH = "32" *)
(* C_TRI_DEFAULT = "-1" *)
(* C_TRI_DEFAULT_2 = "-1" *)
(* downgradeipidentifiedwarnings = "yes" *)
(* ip_group = "LOGICORE" *)
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_gpio U0
(.gpio2_io_i(gpio2_io_i),
.gpio2_io_o(NLW_U0_gpio2_io_o_UNCONNECTED[3:0]),
.gpio2_io_t(NLW_U0_gpio2_io_t_UNCONNECTED[3:0]),
.gpio_io_i(gpio_io_i),
.gpio_io_o(NLW_U0_gpio_io_o_UNCONNECTED[3:0]),
.gpio_io_t(NLW_U0_gpio_io_t_UNCONNECTED[3:0]),
.ip2intc_irpt(NLW_U0_ip2intc_irpt_UNCONNECTED),
.s_axi_aclk(s_axi_aclk),
.s_axi_araddr(s_axi_araddr),
.s_axi_aresetn(s_axi_aresetn),
.s_axi_arready(s_axi_arready),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_awaddr(s_axi_awaddr),
.s_axi_awready(s_axi_awready),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_bready(s_axi_bready),
.s_axi_bresp(s_axi_bresp),
.s_axi_bvalid(s_axi_bvalid),
.s_axi_rdata(s_axi_rdata),
.s_axi_rready(s_axi_rready),
.s_axi_rresp(s_axi_rresp),
.s_axi_rvalid(s_axi_rvalid),
.s_axi_wdata(s_axi_wdata),
.s_axi_wready(s_axi_wready),
.s_axi_wstrb(s_axi_wstrb),
.s_axi_wvalid(s_axi_wvalid));
endmodule
|
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_slave_attachment
(bus2ip_rnw_i_reg_0,
\Dual.gpio2_OE_reg[0] ,
\MEM_DECODE_GEN[0].cs_out_i_reg[0] ,
s_axi_rvalid,
s_axi_bvalid,
s_axi_arready,
s_axi_wready,
Read_Reg2_In,
E,
\Dual.gpio2_Data_Out_reg[0] ,
D,
Read_Reg_In,
\Dual.gpio_OE_reg[0] ,
\Dual.gpio_Data_Out_reg[0] ,
Read_Reg_Rst,
s_axi_rdata,
s_axi_aclk,
s_axi_arvalid,
ip2bus_rdack_i_D1,
ip2bus_wrack_i_D1,
s_axi_bready,
s_axi_rready,
s_axi_awaddr,
s_axi_araddr,
s_axi_awvalid,
s_axi_wvalid,
gpio2_io_t,
Q,
GPIO2_DBus_i,
GPIO_DBus_i,
gpio_io_t,
\Dual.gpio_Data_In_reg[0] ,
s_axi_aresetn,
gpio_xferAck_Reg,
GPIO_xferAck_i,
\ip2bus_data_i_D1_reg[28] );
output bus2ip_rnw_i_reg_0;
output \Dual.gpio2_OE_reg[0] ;
output \MEM_DECODE_GEN[0].cs_out_i_reg[0] ;
output s_axi_rvalid;
output s_axi_bvalid;
output s_axi_arready;
output s_axi_wready;
output [0:3]Read_Reg2_In;
output [0:0]E;
output [0:0]\Dual.gpio2_Data_Out_reg[0] ;
output [3:0]D;
output [0:3]Read_Reg_In;
output [0:0]\Dual.gpio_OE_reg[0] ;
output [0:0]\Dual.gpio_Data_Out_reg[0] ;
output Read_Reg_Rst;
output [3:0]s_axi_rdata;
input s_axi_aclk;
input s_axi_arvalid;
input ip2bus_rdack_i_D1;
input ip2bus_wrack_i_D1;
input s_axi_bready;
input s_axi_rready;
input [2:0]s_axi_awaddr;
input [2:0]s_axi_araddr;
input s_axi_awvalid;
input s_axi_wvalid;
input [3:0]gpio2_io_t;
input [3:0]Q;
input [3:0]GPIO2_DBus_i;
input [3:0]GPIO_DBus_i;
input [3:0]gpio_io_t;
input [3:0]\Dual.gpio_Data_In_reg[0] ;
input s_axi_aresetn;
input gpio_xferAck_Reg;
input GPIO_xferAck_i;
input [3:0]\ip2bus_data_i_D1_reg[28] ;
wire [3:0]D;
wire [0:0]\Dual.gpio2_Data_Out_reg[0] ;
wire \Dual.gpio2_OE_reg[0] ;
wire [3:0]\Dual.gpio_Data_In_reg[0] ;
wire [0:0]\Dual.gpio_Data_Out_reg[0] ;
wire [0:0]\Dual.gpio_OE_reg[0] ;
wire [0:0]E;
wire [3:0]GPIO2_DBus_i;
wire [3:0]GPIO_DBus_i;
wire GPIO_xferAck_i;
wire [3:0]\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 ;
wire \MEM_DECODE_GEN[0].cs_out_i_reg[0] ;
wire [3:0]Q;
wire [0:3]Read_Reg2_In;
wire [0:3]Read_Reg_In;
wire Read_Reg_Rst;
wire [0:6]bus2ip_addr;
wire \bus2ip_addr_i[2]_i_1_n_0 ;
wire \bus2ip_addr_i[3]_i_1_n_0 ;
wire \bus2ip_addr_i[8]_i_1_n_0 ;
wire bus2ip_rnw_i06_out;
wire bus2ip_rnw_i_reg_0;
wire clear;
wire [3:0]gpio2_io_t;
wire [3:0]gpio_io_t;
wire gpio_xferAck_Reg;
wire [3:0]\ip2bus_data_i_D1_reg[28] ;
wire ip2bus_rdack_i_D1;
wire ip2bus_wrack_i_D1;
wire is_read;
wire is_read_i_1_n_0;
wire is_write;
wire is_write_i_1_n_0;
wire is_write_reg_n_0;
wire [1:0]p_0_out;
wire p_1_in;
wire [3:0]plusOp;
wire s_axi_aclk;
wire [2:0]s_axi_araddr;
wire s_axi_aresetn;
wire s_axi_arready;
wire s_axi_arvalid;
wire [2:0]s_axi_awaddr;
wire s_axi_awvalid;
wire s_axi_bready;
wire s_axi_bvalid;
wire s_axi_bvalid_i_i_1_n_0;
wire [3:0]s_axi_rdata;
wire s_axi_rdata_i;
wire s_axi_rready;
wire s_axi_rvalid;
wire s_axi_rvalid_i_i_1_n_0;
wire s_axi_wready;
wire s_axi_wvalid;
wire start2;
wire start2_i_1_n_0;
wire [1:0]state;
wire \state[1]_i_2_n_0 ;
wire \state[1]_i_3_n_0 ;
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT1 #(
.INIT(2'h1))
\INCLUDE_DPHASE_TIMER.dpto_cnt[0]_i_1
(.I0(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [0]),
.O(plusOp[0]));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT2 #(
.INIT(4'h6))
\INCLUDE_DPHASE_TIMER.dpto_cnt[1]_i_1
(.I0(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [0]),
.I1(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [1]),
.O(plusOp[1]));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT3 #(
.INIT(8'h78))
\INCLUDE_DPHASE_TIMER.dpto_cnt[2]_i_1
(.I0(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [1]),
.I1(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [0]),
.I2(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [2]),
.O(plusOp[2]));
LUT2 #(
.INIT(4'h9))
\INCLUDE_DPHASE_TIMER.dpto_cnt[3]_i_1
(.I0(state[1]),
.I1(state[0]),
.O(clear));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT4 #(
.INIT(16'h7F80))
\INCLUDE_DPHASE_TIMER.dpto_cnt[3]_i_2
(.I0(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [2]),
.I1(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [0]),
.I2(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [1]),
.I3(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [3]),
.O(plusOp[3]));
FDRE \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[0]
(.C(s_axi_aclk),
.CE(1'b1),
.D(plusOp[0]),
.Q(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [0]),
.R(clear));
FDRE \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[1]
(.C(s_axi_aclk),
.CE(1'b1),
.D(plusOp[1]),
.Q(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [1]),
.R(clear));
FDRE \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[2]
(.C(s_axi_aclk),
.CE(1'b1),
.D(plusOp[2]),
.Q(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [2]),
.R(clear));
FDRE \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3]
(.C(s_axi_aclk),
.CE(1'b1),
.D(plusOp[3]),
.Q(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [3]),
.R(clear));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_address_decoder I_DECODER
(.D(D),
.\Dual.gpio2_Data_In_reg[0] (Q),
.\Dual.gpio2_Data_Out_reg[0] (\Dual.gpio2_Data_Out_reg[0] ),
.\Dual.gpio_Data_In_reg[0] (\Dual.gpio_Data_In_reg[0] ),
.\Dual.gpio_Data_Out_reg[0] (\Dual.gpio_Data_Out_reg[0] ),
.\Dual.gpio_OE_reg[0] (\Dual.gpio_OE_reg[0] ),
.E(E),
.GPIO2_DBus_i(GPIO2_DBus_i),
.GPIO_DBus_i(GPIO_DBus_i),
.GPIO_xferAck_i(GPIO_xferAck_i),
.\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 (\MEM_DECODE_GEN[0].cs_out_i_reg[0] ),
.Q(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 ),
.Read_Reg2_In(Read_Reg2_In),
.Read_Reg_In(Read_Reg_In),
.Read_Reg_Rst(Read_Reg_Rst),
.\bus2ip_addr_i_reg[8] ({bus2ip_addr[0],bus2ip_addr[5],bus2ip_addr[6]}),
.bus2ip_rnw_i_reg(\Dual.gpio2_OE_reg[0] ),
.gpio2_io_t(gpio2_io_t),
.gpio_io_t(gpio_io_t),
.gpio_xferAck_Reg(gpio_xferAck_Reg),
.ip2bus_rdack_i_D1(ip2bus_rdack_i_D1),
.ip2bus_wrack_i_D1(ip2bus_wrack_i_D1),
.is_read(is_read),
.is_write_reg(is_write_reg_n_0),
.rst_reg(bus2ip_rnw_i_reg_0),
.s_axi_aclk(s_axi_aclk),
.s_axi_aresetn(s_axi_aresetn),
.s_axi_arready(s_axi_arready),
.s_axi_wready(s_axi_wready),
.start2(start2));
LUT5 #(
.INIT(32'hABAAA8AA))
\bus2ip_addr_i[2]_i_1
(.I0(s_axi_awaddr[0]),
.I1(state[1]),
.I2(state[0]),
.I3(s_axi_arvalid),
.I4(s_axi_araddr[0]),
.O(\bus2ip_addr_i[2]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT5 #(
.INIT(32'hABAAA8AA))
\bus2ip_addr_i[3]_i_1
(.I0(s_axi_awaddr[1]),
.I1(state[1]),
.I2(state[0]),
.I3(s_axi_arvalid),
.I4(s_axi_araddr[1]),
.O(\bus2ip_addr_i[3]_i_1_n_0 ));
LUT5 #(
.INIT(32'hABAAA8AA))
\bus2ip_addr_i[8]_i_1
(.I0(s_axi_awaddr[2]),
.I1(state[1]),
.I2(state[0]),
.I3(s_axi_arvalid),
.I4(s_axi_araddr[2]),
.O(\bus2ip_addr_i[8]_i_1_n_0 ));
FDRE \bus2ip_addr_i_reg[2]
(.C(s_axi_aclk),
.CE(start2_i_1_n_0),
.D(\bus2ip_addr_i[2]_i_1_n_0 ),
.Q(bus2ip_addr[6]),
.R(bus2ip_rnw_i_reg_0));
FDRE \bus2ip_addr_i_reg[3]
(.C(s_axi_aclk),
.CE(start2_i_1_n_0),
.D(\bus2ip_addr_i[3]_i_1_n_0 ),
.Q(bus2ip_addr[5]),
.R(bus2ip_rnw_i_reg_0));
FDRE \bus2ip_addr_i_reg[8]
(.C(s_axi_aclk),
.CE(start2_i_1_n_0),
.D(\bus2ip_addr_i[8]_i_1_n_0 ),
.Q(bus2ip_addr[0]),
.R(bus2ip_rnw_i_reg_0));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT3 #(
.INIT(8'h02))
bus2ip_rnw_i_i_1
(.I0(s_axi_arvalid),
.I1(state[0]),
.I2(state[1]),
.O(bus2ip_rnw_i06_out));
FDRE bus2ip_rnw_i_reg
(.C(s_axi_aclk),
.CE(start2_i_1_n_0),
.D(bus2ip_rnw_i06_out),
.Q(\Dual.gpio2_OE_reg[0] ),
.R(bus2ip_rnw_i_reg_0));
LUT5 #(
.INIT(32'h3FFA000A))
is_read_i_1
(.I0(s_axi_arvalid),
.I1(\state[1]_i_2_n_0 ),
.I2(state[1]),
.I3(state[0]),
.I4(is_read),
.O(is_read_i_1_n_0));
FDRE is_read_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(is_read_i_1_n_0),
.Q(is_read),
.R(bus2ip_rnw_i_reg_0));
LUT6 #(
.INIT(64'h1000FFFF10000000))
is_write_i_1
(.I0(state[1]),
.I1(s_axi_arvalid),
.I2(s_axi_wvalid),
.I3(s_axi_awvalid),
.I4(is_write),
.I5(is_write_reg_n_0),
.O(is_write_i_1_n_0));
LUT6 #(
.INIT(64'hF88800000000FFFF))
is_write_i_2
(.I0(s_axi_bready),
.I1(s_axi_bvalid),
.I2(s_axi_rready),
.I3(s_axi_rvalid),
.I4(state[1]),
.I5(state[0]),
.O(is_write));
FDRE is_write_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(is_write_i_1_n_0),
.Q(is_write_reg_n_0),
.R(bus2ip_rnw_i_reg_0));
LUT1 #(
.INIT(2'h1))
rst_i_1
(.I0(s_axi_aresetn),
.O(p_1_in));
FDRE rst_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(p_1_in),
.Q(bus2ip_rnw_i_reg_0),
.R(1'b0));
LUT5 #(
.INIT(32'h08FF0808))
s_axi_bvalid_i_i_1
(.I0(s_axi_wready),
.I1(state[1]),
.I2(state[0]),
.I3(s_axi_bready),
.I4(s_axi_bvalid),
.O(s_axi_bvalid_i_i_1_n_0));
FDRE #(
.INIT(1'b0))
s_axi_bvalid_i_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_axi_bvalid_i_i_1_n_0),
.Q(s_axi_bvalid),
.R(bus2ip_rnw_i_reg_0));
LUT2 #(
.INIT(4'h2))
\s_axi_rdata_i[3]_i_1
(.I0(state[0]),
.I1(state[1]),
.O(s_axi_rdata_i));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[0]
(.C(s_axi_aclk),
.CE(s_axi_rdata_i),
.D(\ip2bus_data_i_D1_reg[28] [0]),
.Q(s_axi_rdata[0]),
.R(bus2ip_rnw_i_reg_0));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[1]
(.C(s_axi_aclk),
.CE(s_axi_rdata_i),
.D(\ip2bus_data_i_D1_reg[28] [1]),
.Q(s_axi_rdata[1]),
.R(bus2ip_rnw_i_reg_0));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[2]
(.C(s_axi_aclk),
.CE(s_axi_rdata_i),
.D(\ip2bus_data_i_D1_reg[28] [2]),
.Q(s_axi_rdata[2]),
.R(bus2ip_rnw_i_reg_0));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[3]
(.C(s_axi_aclk),
.CE(s_axi_rdata_i),
.D(\ip2bus_data_i_D1_reg[28] [3]),
.Q(s_axi_rdata[3]),
.R(bus2ip_rnw_i_reg_0));
LUT5 #(
.INIT(32'h08FF0808))
s_axi_rvalid_i_i_1
(.I0(s_axi_arready),
.I1(state[0]),
.I2(state[1]),
.I3(s_axi_rready),
.I4(s_axi_rvalid),
.O(s_axi_rvalid_i_i_1_n_0));
FDRE #(
.INIT(1'b0))
s_axi_rvalid_i_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_axi_rvalid_i_i_1_n_0),
.Q(s_axi_rvalid),
.R(bus2ip_rnw_i_reg_0));
LUT5 #(
.INIT(32'h000000F8))
start2_i_1
(.I0(s_axi_awvalid),
.I1(s_axi_wvalid),
.I2(s_axi_arvalid),
.I3(state[0]),
.I4(state[1]),
.O(start2_i_1_n_0));
FDRE start2_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(start2_i_1_n_0),
.Q(start2),
.R(bus2ip_rnw_i_reg_0));
LUT5 #(
.INIT(32'h0FFFAACC))
\state[0]_i_1
(.I0(s_axi_wready),
.I1(s_axi_arvalid),
.I2(\state[1]_i_2_n_0 ),
.I3(state[1]),
.I4(state[0]),
.O(p_0_out[0]));
LUT6 #(
.INIT(64'h2E2E2E2ECCCCFFCC))
\state[1]_i_1
(.I0(s_axi_arready),
.I1(state[1]),
.I2(\state[1]_i_2_n_0 ),
.I3(\state[1]_i_3_n_0 ),
.I4(s_axi_arvalid),
.I5(state[0]),
.O(p_0_out[1]));
LUT4 #(
.INIT(16'hF888))
\state[1]_i_2
(.I0(s_axi_bready),
.I1(s_axi_bvalid),
.I2(s_axi_rready),
.I3(s_axi_rvalid),
.O(\state[1]_i_2_n_0 ));
LUT2 #(
.INIT(4'h8))
\state[1]_i_3
(.I0(s_axi_awvalid),
.I1(s_axi_wvalid),
.O(\state[1]_i_3_n_0 ));
FDRE \state_reg[0]
(.C(s_axi_aclk),
.CE(1'b1),
.D(p_0_out[0]),
.Q(state[0]),
.R(bus2ip_rnw_i_reg_0));
FDRE \state_reg[1]
(.C(s_axi_aclk),
.CE(1'b1),
.D(p_0_out[1]),
.Q(state[1]),
.R(bus2ip_rnw_i_reg_0));
endmodule
|
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
|
module CARRY4(
output [3:0] CO,
output [3:0] O,
input CI,
input CYINIT,
input [3:0] DI, S
);
parameter _TECHMAP_CONSTMSK_CI_ = 1;
parameter _TECHMAP_CONSTVAL_CI_ = 1'b0;
parameter _TECHMAP_CONSTMSK_CYINIT_ = 1;
parameter _TECHMAP_CONSTVAL_CYINIT_ = 1'b0;
localparam [0:0] IS_CI_ZERO = (
_TECHMAP_CONSTMSK_CI_ == 1 && _TECHMAP_CONSTVAL_CI_ == 0 &&
_TECHMAP_CONSTMSK_CYINIT_ == 1 && _TECHMAP_CONSTVAL_CYINIT_ == 0);
localparam [0:0] IS_CI_ONE = (
_TECHMAP_CONSTMSK_CI_ == 1 && _TECHMAP_CONSTVAL_CI_ == 0 &&
_TECHMAP_CONSTMSK_CYINIT_ == 1 && _TECHMAP_CONSTVAL_CYINIT_ == 1);
localparam [0:0] IS_CYINIT_FABRIC = _TECHMAP_CONSTMSK_CYINIT_ == 0;
localparam [0:0] IS_CI_DISCONNECTED = _TECHMAP_CONSTMSK_CI_ == 1 &&
_TECHMAP_CONSTVAL_CI_ != 1;
localparam [0:0] IS_CYINIT_DISCONNECTED = _TECHMAP_CONSTMSK_CYINIT_ == 1 &&
_TECHMAP_CONSTVAL_CYINIT_ != 1;
wire [1023:0] _TECHMAP_DO_ = "proc; clean";
wire [3:0] O;
wire [3:0] CO;
wire [3:0] CO_output;
// Put in a placeholder object CARRY_CO_DIRECT.
//
// It will be used for 3 purposes:
// - Remain as CARRY_CO_DIRECT when OUT only connects to CARRY_COUT_PLUG
// - Remain as CARRY_CO_DIRECT when CO is used, but O is not used.
// - Change into CARRY_CO_LUT when O and CO are required (e.g. compute CO
// from O ^ S).
genvar i;
generate for (i = 0; i < 3; i = i + 1) begin:co_outputs
CARRY_CO_DIRECT #(.TOP_OF_CHAIN(0)) co_output(
.CO(CO_output[i]),
.O(O[i+1]),
.S(S[i+1]),
.OUT(CO[i])
);
end endgenerate
CARRY_CO_DIRECT #(.TOP_OF_CHAIN(1)) co_output(
.CO(CO_output[3]),
.O(O[3]),
.S(S[3]),
.DI(DI[3]),
.OUT(CO[3])
);
if(IS_CYINIT_FABRIC) begin
CARRY4_VPR #(
.CYINIT_AX(1'b1),
.CYINIT_C0(1'b0),
.CYINIT_C1(1'b0)
) _TECHMAP_REPLACE_ (
.CO0(CO_output[0]),
.CO1(CO_output[1]),
.CO2(CO_output[2]),
.CO3(CO_output[3]),
.CYINIT(CYINIT),
.O0(O[0]),
.O1(O[1]),
.O2(O[2]),
.O3(O[3]),
.DI0(DI[0]),
.DI1(DI[1]),
.DI2(DI[2]),
.DI3(DI[3]),
.S0(S[0]),
.S1(S[1]),
.S2(S[2]),
.S3(S[3])
);
end else if(IS_CI_ZERO || IS_CI_ONE) begin
CARRY4_VPR #(
.CYINIT_AX(1'b0),
.CYINIT_C0(IS_CI_ZERO),
.CYINIT_C1(IS_CI_ONE)
) _TECHMAP_REPLACE_ (
.CO0(CO_output[0]),
.CO1(CO_output[1]),
.CO2(CO_output[2]),
.CO3(CO_output[3]),
.O0(O[0]),
.O1(O[1]),
.O2(O[2]),
.O3(O[3]),
.DI0(DI[0]),
.DI1(DI[1]),
.DI2(DI[2]),
.DI3(DI[3]),
.S0(S[0]),
.S1(S[1]),
.S2(S[2]),
.S3(S[3])
);
end else begin
wire cin_from_below;
CARRY_COUT_PLUG cin_plug(
.CIN(CI),
.COUT(cin_from_below)
);
CARRY4_VPR #(
.CYINIT_AX(1'b0),
.CYINIT_C0(1'b0),
.CYINIT_C1(1'b0)
) _TECHMAP_REPLACE_ (
.CO0(CO_output[0]),
.CO1(CO_output[1]),
.CO2(CO_output[2]),
.CO3(CO_output[3]),
.O0(O[0]),
.O1(O[1]),
.O2(O[2]),
.O3(O[3]),
.DI0(DI[0]),
.DI1(DI[1]),
.DI2(DI[2]),
.DI3(DI[3]),
.S0(S[0]),
.S1(S[1]),
.S2(S[2]),
.S3(S[3]),
.CIN(cin_from_below)
);
end
endmodule
|
module dzcpu_ucode_lut
(
input wire[7:0] iMop,
output reg [8:0] oUopFlowIdx
);
always @ ( iMop )
begin
case ( iMop )
`LDSPnn: oUopFlowIdx = 9'd1;
`LDHLnn: oUopFlowIdx = 9'd5;
`LDHLDA: oUopFlowIdx = 9'd9;
`MAPcb: oUopFlowIdx = 9'd13;
`JRNZn: oUopFlowIdx = 9'd17;
`LDrn_c: oUopFlowIdx = 9'd23;
`LDrn_a: oUopFlowIdx = 9'd26;
`LDIOCA: oUopFlowIdx = 9'd29;
`INCr_c: oUopFlowIdx = 9'd32;
`LDHLmr_a: oUopFlowIdx = 9'd33;
`LDIOnA: oUopFlowIdx = 9'd36;
`LDDEnn: oUopFlowIdx = 9'd43;
`LDADEm: oUopFlowIdx = 9'd94;
`CALLnn: oUopFlowIdx = 9'd49;
`LDrn_b: oUopFlowIdx = 9'd60;
`PUSHBC: oUopFlowIdx = 9'd63;
`RLA: oUopFlowIdx = 9'd70; //TODO: Make sure this is OK!
`POPBC: oUopFlowIdx = 9'd71;
`DECr_b: oUopFlowIdx = 9'd300;
`LDHLIA: oUopFlowIdx = 9'd78;
`INCHL: oUopFlowIdx = 9'd82;
`RET: oUopFlowIdx = 9'd252;//8'd83;
`INCDE: oUopFlowIdx = 9'd89;
`CPn: oUopFlowIdx = 9'd90;
`LDmmA: oUopFlowIdx = 9'd98;
`DECr_a: oUopFlowIdx = 9'd47;
`DECr_c: oUopFlowIdx = 9'd48;
`JRZn: oUopFlowIdx = 9'd106;
`LDrn_l: oUopFlowIdx = 9'd112;
`JRn: oUopFlowIdx = 9'd115;
`INCr_b: oUopFlowIdx = 9'd161;
`LDrn_e: oUopFlowIdx = 9'd121;
`LDAIOn: oUopFlowIdx = 9'd124;
`INCr_h: oUopFlowIdx = 9'd312;
`SUBr_b: oUopFlowIdx = 9'd132;
`DECr_d: oUopFlowIdx = 9'd135;
`LDrn_d: oUopFlowIdx = 9'd136;
`JPnn: oUopFlowIdx = 9'd139;
`LDrn_h: oUopFlowIdx = 9'd146;
`LDAHLI: oUopFlowIdx = 9'd149;
`LDHLmn: oUopFlowIdx = 9'd154;
`NOP: oUopFlowIdx = 9'd162;
`DI: oUopFlowIdx = 9'd163;
`INCr_d: oUopFlowIdx = 9'd164;
`INCr_e: oUopFlowIdx = 9'd250; //8'd165;
`DECr_e: oUopFlowIdx = 9'd166;
`DECDE: oUopFlowIdx = 9'd168;
`DECBC: oUopFlowIdx = 9'd169; //OK
`DECr_h: oUopFlowIdx = 9'd170;
`DECHL: oUopFlowIdx = 9'd172;
`INCr_a: oUopFlowIdx = 9'd302;
`INCSP: oUopFlowIdx = 9'd304;
`DECSP: oUopFlowIdx = 9'd306;
`INCr_l: oUopFlowIdx = 9'd308;
`DECr_l: oUopFlowIdx = 9'd310;
`ADDr_a: oUopFlowIdx = 9'd175;
`ADDr_b: oUopFlowIdx = 9'd178;
`SUBr_c: oUopFlowIdx = 9'd181;
`ADDr_c: oUopFlowIdx = 9'd184;
`ADDr_d: oUopFlowIdx = 9'd187;
`ADDr_e: oUopFlowIdx = 9'd190;
`ADDr_h: oUopFlowIdx = 9'd193;
`ADDr_l: oUopFlowIdx = 9'd196;
`SUBr_d: oUopFlowIdx = 9'd199;
`SUBr_e: oUopFlowIdx = 9'd202;
`SUBr_h: oUopFlowIdx = 9'd205;
`SUBr_l: oUopFlowIdx = 9'd208;
`SUBr_a: oUopFlowIdx = 9'd211;
`PUSHDE: oUopFlowIdx = 9'd214;
`PUSHHL: oUopFlowIdx = 9'd220;
`POPDE: oUopFlowIdx = 9'd226;
`POPHL: oUopFlowIdx = 9'd232;
`LDHLmr_b: oUopFlowIdx = 9'd238;
`LDHLmr_c: oUopFlowIdx = 9'd241;
`LDHLmr_d: oUopFlowIdx = 9'd244;
`LDDEmA: oUopFlowIdx = 9'd247;
`PUSHAF: oUopFlowIdx = 9'd261;
`POPAF: oUopFlowIdx = 9'd267;
`LDBCnn: oUopFlowIdx = 9'd273;
`INCBC: oUopFlowIdx = 9'd83;
`LDAmm: oUopFlowIdx = 9'd280;
`ANDn: oUopFlowIdx = 9'd85;
`CALLNZnn: oUopFlowIdx = 9'd289;
`ADDn: oUopFlowIdx = 9'd314;
`SUBn: oUopFlowIdx = 9'd319;
`CPr_c: oUopFlowIdx = 9'd324;
`LDrHLm_b: oUopFlowIdx = 9'd327;
`LDrHLm_c: oUopFlowIdx = 9'd331;
`LDrHLm_d: oUopFlowIdx = 9'd335;
`XORHL: oUopFlowIdx = 9'd339;
`ADCn: oUopFlowIdx = 9'd345;
`ADDHLDE: oUopFlowIdx = 9'd351;
`JRNCn: oUopFlowIdx = 9'd414;
`XORn: oUopFlowIdx = 9'd359;
`RRA: oUopFlowIdx = 9'd363;
`RETNC: oUopFlowIdx = 9'd365;
`RETZ: oUopFlowIdx = 9'd377;
`ORHL: oUopFlowIdx = 9'd387;
`DECHLm: oUopFlowIdx = 9'd391;
`LDrHLm_l: oUopFlowIdx = 9'd397;
`RETNZ: oUopFlowIdx = 9'd401;
`ADDHLHL: oUopFlowIdx = 9'd411;
`ANDHL: oUopFlowIdx = 9'd420;
`LDHLmr_e: oUopFlowIdx = 9'd424;
`LDHLmr_h: oUopFlowIdx = 9'd427;
`LDHLmr_l: oUopFlowIdx = 9'd430;
`LDABCm: oUopFlowIdx = 9'd433;
`LDrHLm_a: oUopFlowIdx = 9'd437;
`LDrHLm_e: oUopFlowIdx = 9'd441;
`LDrHLm_h: oUopFlowIdx = 9'd445;
`ADCr_a: oUopFlowIdx = 9'd449;
`ADCr_b: oUopFlowIdx = 9'd453;
`ADCr_c: oUopFlowIdx = 9'd457;
`ADCr_d: oUopFlowIdx = 9'd461;
`ADCr_e: oUopFlowIdx = 9'd465;
`ADCr_h: oUopFlowIdx = 9'd469;
`ADCr_l: oUopFlowIdx = 9'd473;
default:
oUopFlowIdx = 9'd278;
endcase
end
endmodule
|
module dzcpu_ucode_cblut
(
input wire[7:0] iMop,
output reg [8:0] oUopFlowIdx
);
always @ ( iMop )
begin
case ( iMop )
8'h7C: oUopFlowIdx = 9'd16; //BIT7
8'h11: oUopFlowIdx = 9'd69; //RLr_b
8'h38: oUopFlowIdx = 9'd477; //SRL_b
default:
oUopFlowIdx = 9'd0;
endcase
end
endmodule
|
module dzcpu_ucode_rom
(
input wire[8:0] iAddr,
output reg [13:0] oUop
);
always @ ( iAddr )
begin
case ( iAddr )
//Regular 1 Byte mOp
0: oUop = { `inc_eof_fu, `z801bop , `a };
//LDSPnn
1: oUop = { `inc, `sma, `pc };
2: oUop = { `inc, `nop, `null };
3: oUop = { `op , `srm, `spl };
4: oUop = { `inc_eof , `srm, `sph };
//LDHLnn
5: oUop = { `inc, `sma, `pc };
6: oUop = { `inc, `nop, `null };
7: oUop = { `op , `srm, `l };
8: oUop = { `inc_eof , `srm, `h };
//LDHLDA
9: oUop = { `op, `sma, `hl };
10: oUop = { `op, `smw, `a };
11: oUop = { `inc, `sma, `pc };
12: oUop = { `eof, `dec16, `hl };
//MAPcb 0xCB
13: oUop = { `inc, `sma, `pc };
14: oUop = { `op, `nop, `null };
15: oUop = { `inc, `jcb, `null };
//BIT
16: oUop = { `eof_fu, `bit, `null };
//JRNZ
17: oUop = { `inc, `sma, `pc };
18: oUop = { `op, `nop, `null };
19: oUop = { `inc_eof_z, `srm, `x8 }; //If z return else x8 = MEM[pc]
20: oUop = { `op, `sx16r, `pc }; //x16 = pc
21: oUop = { `op,`addx16, `x8 }; //x16 = x16 + sign_extend{8'b0,x8}
22: oUop = { `eof, `spc, `x16 }; //pc = x16
//LDrn_c
23: oUop = {`inc, `sma, `pc};
24: oUop = { `inc, `nop, `null };
25: oUop = {`eof, `srm, `c };
//LDrn_a
26: oUop = {`inc, `sma, `pc};
27: oUop = { `inc, `nop, `null };
28: oUop = {`eof, `srm, `a };
//LDIOCA
29: oUop = {`op, `sma, `io_c };
30: oUop = {`op, `smw, `a };
31: oUop = {`inc_eof, `sma, `pc };
//INCr_c
32: oUop = {`inc_eof_fu, `inc16, `c };
//LDHLmr_a
33: oUop = {`inc, `sma, `hl };
34: oUop = {`op, `smw, `a };
35: oUop = {`eof, `sma, `pc };
//LDIOnA
36: oUop = { `inc, `sma, `pc };
37: oUop = { `op ,`sx8r, `c };
38: oUop = { `op ,`srm, `c };
39: oUop = { `op, `sma, `io_c };
40: oUop = { `op, `smw, `a };
41: oUop = { `inc, `srx8, `c };
42: oUop = { `eof, `sma, `pc };
//LDDEnn
43: oUop = { `inc, `sma, `pc };
44: oUop = { `inc, `nop, `null };
45: oUop = { `op , `srm, `e };
46: oUop = { `inc_eof , `srm, `d };
//DECr_a
47: oUop = { `inc_eof_fu, `dec16, `a };
//DECr_c
48: oUop = { `inc_eof_fu, `dec16, `c };
//CALLnn
49: oUop = { `inc, `dec16, `sp };
50: oUop = { `inc, `sx16r, `hl };
51: oUop = { `op , `srm, `l }; //l = MEM[pc] = literal
52: oUop = { `inc, `srm, `h }; //l = MEM[pc] = literal
53: oUop = { `op, `sma, `sp };
54: oUop = { `op, `smw, `pch }; //MEM[sp] = pc[7:0]
55: oUop = { `op, `dec16, `sp };
56: oUop = { `op , `smw, `pc }; //MEM[sp+1] = pc[15:8]
57: oUop = { `op , `spc, `hl };
58: oUop = { `op, `srx16, `hl };
59: oUop = { `eof ,`sma, `pc };
//LDrn_b
60: oUop = { `inc, `sma, `pc };
61: oUop = { `inc, `nop, `null };
62: oUop = { `eof , `srm, `b };
//PUSHBC
63: oUop = { `op, `dec16, `sp };
64: oUop = { `op, `sma, `sp };
65: oUop = { `op ,`smw, `b };
66: oUop = { `op, `dec16, `sp };
67: oUop = { `op ,`smw, `c };
68: oUop = { `inc_eof ,`sma,`pc };
//RLr_r
69: oUop = { `eof_fu, `shl, `null };
//RLA
70: oUop = { `inc_eof_fu, `shl, `null };
//POPBC
71: oUop = { `op, `sma, `sp };
72: oUop = { `op ,`inc16, `sp };
73: oUop = { `op ,`srm, `c };
74: oUop = { `op ,`srm, `b };
75: oUop = { `inc ,`inc16, `sp };
76: oUop = { `eof, `sma, `pc };
//UNUSED
77: oUop = { `inc_eof_fu, `dec16, `b };
//LDHLIA
78: oUop = {`op, `sma, `hl };
79: oUop = {`op, `smw, `a };
80: oUop = { `inc ,`inc16, `hl };
81: oUop = {`eof, `sma, `pc };
//INCHL
82: oUop = { `inc_eof ,`inc16, `hl };
//INCBC
83: oUop = { `inc_eof ,`inc16, `bc }; //flags might be wrong for 16bits
//UNUSED
84: oUop = { `inc_eof, `nop, `null };
//ANDn
85: oUop = { `inc, `sma, `pc };
86: oUop = { `op, `nop , `null };
87: oUop = { `update_flags ,`anda, `idata };
88: oUop = { `inc_eof ,`nop, `null };
//INCDE
89: oUop = { `inc_eof, `inc16, `de };
//CPn
90: oUop = { `inc, `sx16r, `a };
91: oUop = { `op, `nop, `null };
92: oUop = { `op, `srm, `x8 };
93: oUop = { `inc_eof_fu, `subx16, `x8 }; //x16 = x16 - x8 -> a = a - lit
//LDADEm
94: oUop = {`inc, `sma, `de };
95: oUop = {`op, `nop, `null };
96: oUop = {`op, `srm, `a };
97: oUop = {`eof, `sma, `pc };
//LDmmA
98: oUop = {`inc, `sx16r, `hl };
99: oUop = {`inc, `sma, `pc };
100: oUop = {`op, `srm, `l };
101: oUop = {`op, `srm, `h };
102: oUop = {`op, `sma, `hl };
103: oUop = {`op, `smw, `a };
104: oUop = {`inc, `sma, `pc };
105: oUop = {`eof, `srx16, `hl };
//JRZn
106: oUop = { `inc, `sma, `pc };
107: oUop = { `op, `nop, `null };
108: oUop = { `inc_eof_nz, `srm, `x8 }; //If not z return else x8 = MEM[pc]
109: oUop = { `op, `sx16r, `pc }; //x16 = pc
110: oUop = { `op,`addx16, `x8 }; //x16 = x16 + sign_extend{8'b0,x8}
111: oUop = { `eof, `spc, `x16 }; //pc = x16
//LDrn_l
112: oUop = {`inc, `sma, `pc };
113: oUop = { `inc, `nop, `null };
114: oUop = {`eof, `srm, `l };
//JRn
115: oUop = { `inc, `sma, `pc };
116: oUop = { `op, `nop, `null };
117: oUop = { `inc, `srm, `x8 };
118: oUop = { `op, `sx16r, `pc }; //x16 = pc
119: oUop = { `op,`addx16, `x8 }; //x16 = x16 + sign_extend{8'b0,x8}
120: oUop = { `eof, `spc, `x16 }; //pc = x16
//LDrn_e
121: oUop = {`inc, `sma, `pc };
122: oUop = { `inc, `nop, `null };
123: oUop = {`eof, `srm, `e };
//LDAIOn
124: oUop = { `inc, `sx8r, `c };
125: oUop = { `op, `nop, `null };
126: oUop = { `op, `srm, `c };
127: oUop = { `op, `sma, `io_c };
128: oUop = { `op, `srm, `a };
129: oUop = { `op, `srx8, `c };
130: oUop = { `inc_eof, `sma, `pc };
//UNUSED
131: oUop = { `op, `nop, `null };
//SUBr_b
132: oUop = { `op, `sx16r, `a };
133: oUop = { `update_flags, `subx16, `b };
134: oUop = { `inc_eof, `srx16, `a };
//DECr_d
135: oUop = { `inc_eof_fu, `dec16, `d };
//LDrn_d
136: oUop = {`inc, `sma, `pc };
137: oUop = { `inc, `nop, `null };
138: oUop = {`eof, `srm, `d };
//JPnn
139: oUop = {`op, `sx16r, `hl };
140: oUop = {`inc, `sma, `pc };
141: oUop = {`inc, `nop, `null };
142: oUop = {`inc, `srm, `l };
143: oUop = {`op, `srm, `h };
144: oUop = {`op, `spc, `hl };
145: oUop = {`eof, `srx16, `hl };
//LDrn_h
146: oUop = {`inc, `sma, `pc };
147: oUop = { `inc, `nop, `null };
148: oUop = {`eof, `srm, `h };
//LDAHLI
149: oUop = {`op, `sma, `hl };
150: oUop = {`op, `nop, `null };
151: oUop = {`op, `srm, `a };
152: oUop = { `inc ,`inc16, `hl };
153: oUop = {`eof, `sma, `pc };
//LDHLmn
154: oUop = {`inc, `sma, `pc };
155: oUop = {`op, `nop, `null };
156: oUop = {`op, `srm, `x8 };
157: oUop = {`op, `sma, `hl };
158: oUop = {`op, `nop, `null };
159: oUop = {`op, `smw, `x8 };
160: oUop = {`inc_eof, `sma, `pc };
//INCR_b
161: oUop = {`inc_eof_fu, `inc16, `b };
//NOP
162: oUop = { `inc_eof, `nop, `null };
//DI
163: oUop = { `inc_eof, `ceti, `null }; //Disable Interruption
//INCr_d
164: oUop = { `update_flags, `inc16, `d };
165: oUop = { `inc_eof, `nop, `null };
//DECr_e
166: oUop = { `update_flags, `dec16, `e };
167: oUop = { `inc_eof, `nop, `null };
//DECDE
168: oUop = { `inc_eof, `dec16, `de };
//DECBC
169: oUop = { `inc_eof, `dec16, `bc};
//DECr_h
170: oUop = { `update_flags, `dec16, `h };
171: oUop = { `inc_eof, `nop, `null };
//DECHL
172: oUop = { `inc_eof, `dec16, `hl };
//UNUSED
173: oUop = { `inc_eof, `nop, `null };
//UNUSED
174: oUop = { `inc_eof, `nop, `null };
//ADDr_a
175: oUop = { `op, `sx16r, `a };
176: oUop = { `update_flags, `addx16u, `a };
177: oUop = { `inc_eof, `srx16, `a };
//ADDr_b
178: oUop = { `op, `sx16r, `a };
179: oUop = { `update_flags, `addx16u, `b };
180: oUop = { `inc_eof, `srx16, `a };
//SUBr_c
181: oUop = { `op, `sx16r, `a };
182: oUop = { `update_flags, `subx16, `c };
183: oUop = { `inc_eof, `srx16, `a };
//ADDr_c
184: oUop = { `op, `sx16r, `a };
185: oUop = { `update_flags, `addx16u, `c };
186: oUop = { `inc_eof, `srx16, `a };
//ADDr_d
187: oUop = { `op, `sx16r, `a };
188: oUop = { `update_flags, `addx16u, `d };
189: oUop = { `inc_eof, `srx16, `a };
//ADDr_e
190: oUop = { `op, `sx16r, `a };
191: oUop = { `update_flags, `addx16u, `e };
192: oUop = { `inc_eof, `srx16, `a };
//ADDr_h
193: oUop = { `op, `sx16r, `a };
194: oUop = { `update_flags, `addx16u, `h };
195: oUop = { `inc_eof, `srx16, `a };
//ADDr_l
196: oUop = { `op, `sx16r, `a };
197: oUop = { `update_flags, `addx16u, `l };
198: oUop = { `inc_eof, `srx16, `a };
//SUBr_d
199: oUop = { `op, `sx16r, `a };
200: oUop = { `update_flags, `subx16, `d };
201: oUop = { `inc_eof, `srx16, `a };
//SUBr_e
202: oUop = { `op, `sx16r, `a };
203: oUop = { `update_flags, `subx16, `e };
204: oUop = { `inc_eof, `srx16, `a };
//SUBr_h
205: oUop = { `op, `sx16r, `a };
206: oUop = { `update_flags, `subx16, `h };
207: oUop = { `inc_eof, `srx16, `a };
//SUBr_l
208: oUop = { `op, `sx16r, `a };
209: oUop = { `update_flags, `subx16, `l };
210: oUop = { `inc_eof, `srx16, `a };
//SUB_a
211: oUop = { `op, `sx16r, `a };
212: oUop = { `update_flags, `subx16, `a };
213: oUop = { `inc_eof, `srx16, `a };
//PUSHDE
214: oUop = { `op, `dec16, `sp };
215: oUop = { `op, `sma, `sp };
216: oUop = { `op ,`smw, `d };
217: oUop = { `op, `dec16, `sp };
218: oUop = { `op ,`smw, `e };
219: oUop = { `inc_eof ,`sma,`pc };
//PUSHHL
220: oUop = { `op, `dec16, `sp };
221: oUop = { `op, `sma, `sp };
222: oUop = { `op ,`smw, `h };
223: oUop = { `op, `dec16, `sp };
224: oUop = { `op ,`smw, `l };
225: oUop = { `inc_eof ,`sma,`pc };
//POPDE
226: oUop = { `op, `sma, `sp };
227: oUop = { `op ,`inc16, `sp };
228: oUop = { `op ,`srm, `e };
229: oUop = { `op ,`srm, `d };
230: oUop = { `inc ,`inc16, `sp };
231: oUop = { `eof, `sma, `pc };
//POPHL
232: oUop = { `op, `sma, `sp };
233: oUop = { `op ,`inc16, `sp };
234: oUop = { `op ,`srm, `l };
235: oUop = { `op ,`srm, `h };
236: oUop = { `inc ,`inc16, `sp };
237: oUop = { `eof, `sma, `pc };
//LDHLmr_b
238: oUop = {`inc, `sma, `hl };
239: oUop = {`op, `smw, `b };
240: oUop = {`eof, `sma, `pc };
//LDHLmr_c
241: oUop = {`inc, `sma, `hl };
242: oUop = {`op, `smw, `c };
243: oUop = {`eof, `sma, `pc };
//LDHLmr_d
244: oUop = {`inc, `sma, `hl };
245: oUop = {`op, `smw, `d };
246: oUop = {`eof, `sma, `pc };
//LDDEmA
247: oUop = {`op, `sma, `de };
248: oUop = {`op, `smw, `a };
249: oUop = {`inc_eof, `sma, `pc };
//INCr_e
250: oUop = { `update_flags, `inc16, `e };
251: oUop = { `inc_eof, `nop, `null };
//RET
252: oUop = {`op ,`sma, `sp };
253: oUop = {`op, `sx16r, `hl };
254: oUop = {`op, `inc16, `sp };
255: oUop = {`op, `srm, `l };
256: oUop = {`op, `srm, `h };
257: oUop = {`op, `spc, `hl };
258: oUop = {`op, `srx16, `hl };
259: oUop = {`op, `inc16, `sp };
260: oUop = { `eof ,`sma, `pc };
//PUSHAF
261: oUop = { `op, `dec16, `sp };
262: oUop = { `op, `sma, `sp };
263: oUop = { `op ,`smw, `a };
264: oUop = { `op, `dec16, `sp };
265: oUop = { `op ,`smw, `f };
266: oUop = { `inc_eof ,`sma,`pc };
//POPAF
267: oUop = { `op, `sma, `sp };
268: oUop = { `op ,`inc16, `sp };
269: oUop = { `op ,`srm, `f };
270: oUop = { `op ,`srm, `a };
271: oUop = { `inc ,`inc16, `sp };
272: oUop = { `eof, `sma, `pc };
//LDBCnn
273: oUop = { `inc, `sma, `pc };
274: oUop = { `inc, `nop, `null };
275: oUop = { `op , `srm, `c };
276: oUop = { `inc_eof , `srm, `b };
//INCBC
277: oUop = { `inc_eof ,`inc16, `bc };
//Z80 1 Byte op
278: oUop = { `update_flags, `z801bop , `a };
279: oUop = { `inc_eof, `nop , `null };
//LDAmm
280: oUop = { `inc, `sx16r, `hl };
281: oUop = { `inc, `sma , `pc };
282: oUop = { `op ,`srm, `l };
283: oUop = { `op ,`srm, `h };
284: oUop = { `op, `sma , `hl };
285: oUop = { `op, `nop , `null }; //remember to wait 1cc after sma
286: oUop = { `op ,`srm, `a };
287: oUop = { `op, `srx16, `hl };
288: oUop = { `inc_eof, `sma , `pc };
//CALLNZnn
289: oUop = { `inc, `nop, `null };
290: oUop = { `inc, `nop, `null };
291: oUop = { `op , `srm, `y8 }; //l = MEM[pc] = literal
292: oUop = { `inc_eof_z, `srm, `x8 }; //l = MEM[pc] = literal
293: oUop = { `op, `sma, `sp };
294: oUop = { `op, `smw, `pch }; //MEM[sp] = pc[7:0]
295: oUop = { `op, `dec16, `sp };
296: oUop = { `op , `smw, `pc }; //MEM[sp+1] = pc[15:8]
297: oUop = { `op, `dec16, `sp };
298: oUop = { `op , `spc, `xy16 };
299: oUop = { `eof ,`sma, `pc };
//DECr_b
300: oUop = { `update_flags, `dec16, `b };
301: oUop = { `inc_eof, `nop, `null};
//INCr_a
302: oUop = { `update_flags, `inc16, `a };
303: oUop = { `inc_eof, `nop, `null};
//INCSP
304: oUop = { `op, `inc16, `sp }; //increment SP
305: oUop = { `inc_eof, `nop, `null};
//DECSP
306: oUop = { `inc_eof, `dec16, `sp };
//UNUSED
307: oUop = { `inc_eof, `nop, `null};
//INCr_l
308: oUop = { `update_flags, `inc16, `l };
309: oUop = { `inc_eof, `nop, `null};
//DECr_l
310: oUop = { `update_flags, `dec16, `l };
311: oUop = { `inc_eof, `nop, `null};
//INCr_h
312: oUop = { `update_flags, `inc16, `h };
313: oUop = { `inc_eof, `nop, `null};
//ADDn
314: oUop = { `inc, `sma, `pc };
315: oUop = { `op, `nop, `null };
316: oUop = { `op, `srm, `x16 };
317: oUop = { `update_flags, `addx16u, `a };
318: oUop = { `inc_eof, `srx16, `a};
//SUBn
319: oUop = { `inc, `sma, `pc };
320: oUop = { `op, `nop, `null };
321: oUop = { `op, `srm, `x16 };
322: oUop = { `update_flags, `subx16, `a };
323: oUop = { `inc_eof, `srx16, `a};
//CPr_c
324: oUop = { `op, `sx16r, `a };
325: oUop = { `update_flags, `subx16, `c };
326: oUop = { `inc_eof, `nop, `null};
//LDrHLm_b
327: oUop = { `op, `sma, `hl };
328: oUop = { `op, `nop, `null };
329: oUop = { `op, `srm, `b };
330: oUop = { `inc_eof, `sma, `pc};
//LDrHLm_c
331: oUop = { `op, `sma, `hl };
332: oUop = { `op, `nop, `null };
333: oUop = { `op, `srm, `c };
334: oUop = { `inc_eof, `sma, `pc};
//LDrHLm_d
335: oUop = { `op, `sma, `hl };
336: oUop = { `op, `nop, `null };
337: oUop = { `op, `srm, `d };
338: oUop = { `inc_eof, `sma, `pc};
//XORHL
339: oUop = { `op, `sma, `hl };
340: oUop = { `op, `nop, `null };
341: oUop = { `op, `srm, `x16 };
342: oUop = { `update_flags, `xorx16, `a};
343: oUop = { `op, `srx16, `a};
344: oUop = { `inc_eof, `sma, `pc};
//ADCn
345: oUop = { `inc, `sma, `pc };
346: oUop = { `op, `nop, `null };
347: oUop = { `op, `srm, `x16 };
348: oUop = { `op, `addx16, `a };
349: oUop = { `update_flags, `addx16, `carry };
350: oUop = { `inc_eof, `sma, `pc};
//ADDHLDE
351: oUop = { `inc, `sx16r, `hl };
352: oUop = { `update_flags, `addx16, `de };
353: oUop = { `eof, `srx16, `hl };
//UNUSED
354: oUop = { `inc, `sma, `pc };
355: oUop = { `op, `xorx16, `x16 };
356: oUop = { `update_flags, `addx16, `carry };
357: oUop = { `inc_eof_nz, `srm, `x16 };
358: oUop = { `eof, `addx16, `x16 };
//XORn
359: oUop = { `inc, `sma, `pc };
360: oUop = { `op, `sx16r , `a };
361: oUop = { `update_flags ,`xorx16, `idata };
362: oUop = { `inc_eof ,`srx16, `a };
//RRA
363: oUop = { `update_flags, `rrot, `null };
364: oUop = { `inc_eof, `nop, `null };
//RETNC
365: oUop = { `op, `xorx16, `x16 };
366: oUop = { `update_flags, `addx16, `carry };
367: oUop = { `inc_eof_nz, `srm, `x16 };
368: oUop = {`op ,`sma, `sp };
369: oUop = {`op, `sx16r, `hl };
370: oUop = {`op, `inc16, `sp };
371: oUop = {`op, `srm, `l };
372: oUop = {`op, `srm, `h };
373: oUop = {`op, `spc, `hl };
374: oUop = {`op, `srx16, `hl };
375: oUop = {`op, `inc16, `sp };
376: oUop = { `eof ,`sma, `pc };
//RETZ
377: oUop = { `inc_eof_z, `nop, `null };
378: oUop = {`op ,`sma, `sp };
379: oUop = {`op, `sx16r, `hl };
380: oUop = {`op, `inc16, `sp };
381: oUop = {`op, `srm, `l };
382: oUop = {`op, `srm, `h };
383: oUop = {`op, `spc, `hl };
384: oUop = {`op, `srx16, `hl };
385: oUop = {`op, `inc16, `sp };
386: oUop = { `eof ,`sma, `pc };
//ORHL
387: oUop = {`op ,`sma, `hl };
388: oUop = {`op, `nop, `null };
389: oUop = {`update_flags, `xora, `idata };
390: oUop = { `inc_eof ,`sma, `pc };
//DECHLm
391: oUop = {`op ,`sma, `hl };
392: oUop = {`op, `nop, `null };
393: oUop = {`op, `srm, `x16 };
394: oUop = {`update_flags, `dec16, `x16 };
395: oUop = {`nop, `smw, `x16 };
396: oUop = {`inc_eof, `sma, `pc };
//LDrHLm_l
397: oUop = {`op ,`sma, `hl };
398: oUop = {`op, `nop, `null };
399: oUop = {`op, `srm, `l };
400: oUop = {`inc_eof, `sma, `pc };
//RETNZ
401: oUop = { `inc_eof_nz, `nop, `null };
402: oUop = {`op ,`sma, `sp };
403: oUop = {`op, `sx16r, `hl };
404: oUop = {`op, `inc16, `sp };
405: oUop = {`op, `srm, `l };
406: oUop = {`op, `srm, `h };
407: oUop = {`op, `spc, `hl };
408: oUop = {`op, `srx16, `hl };
409: oUop = {`op, `inc16, `sp };
410: oUop = { `eof ,`sma, `pc };
//ADDHLHL
411: oUop = {`op, `sx16r, `hl };
412: oUop = {`update_flags, `addx16r16, `x16 };
413: oUop = {`inc_eof, `srx16, `hl };
//JRNCn
414: oUop = { `inc, `sma, `pc };
415: oUop = { `op, `xorx16, `x16 };
416: oUop = { `update_flags, `addx16, `carry };
417: oUop = { `inc_eof_nz, `srm, `x16 };
418: oUop = { `nop, `addx16, `pc };
419: oUop = { `eof, `spc, `x16 };
//ANDHL
420: oUop = { `inc, `sma, `hl };
421: oUop = { `op, `nop , `null };
422: oUop = { `update_flags ,`anda, `idata };
423: oUop = { `inc_eof ,`nop, `null };
//LDHLmr_e
424: oUop = {`inc, `sma, `hl };
425: oUop = {`op, `smw, `e };
426: oUop = {`eof, `sma, `pc };
//LDHLmr_h
427: oUop = {`inc, `sma, `hl };
428: oUop = {`op, `smw, `h };
429: oUop = {`eof, `sma, `pc };
//LDHLmr_h
430: oUop = {`inc, `sma, `hl };
431: oUop = {`op, `smw, `l };
432: oUop = {`eof, `sma, `pc };
//LDABCm
433: oUop = {`inc, `sma, `bc };
434: oUop = {`op, `nop, `null };
435: oUop = {`op, `srm, `a };
436: oUop = {`eof, `sma, `pc };
//LDrHLm_a
437: oUop = {`inc, `sma, `hl };
438: oUop = {`op, `nop, `null };
439: oUop = {`op, `srm, `a };
440: oUop = {`eof, `sma, `pc };
//LDrHLm_e
441: oUop = {`inc, `sma, `hl };
442: oUop = {`op, `nop, `null };
443: oUop = {`op, `srm, `e };
444: oUop = {`eof, `sma, `pc };
//LDrHLm_e
445: oUop = {`inc, `sma, `hl };
446: oUop = {`op, `nop, `null };
447: oUop = {`op, `srm, `h };
448: oUop = {`eof, `sma, `pc };
//ADCr_a
449: oUop = { `op, `sx16r, `a };
450: oUop = { `op, `addx16, `carry };
451: oUop = { `update_flags, `addx16, `a};
452: oUop = { `inc_eof, `srx16, `a };
//ADCr_b
453: oUop = { `op, `sx16r, `a };
454: oUop = { `op, `addx16, `carry };
455: oUop = { `update_flags, `addx16, `b};
456: oUop = { `inc_eof, `srx16, `a };
//ADCr_c
457: oUop = { `op, `sx16r, `a };
458: oUop = { `op, `addx16, `carry };
459: oUop = { `update_flags, `addx16, `c};
460: oUop = { `inc_eof, `srx16, `a };
//ADCr_d
461: oUop = { `op, `sx16r, `a };
462: oUop = { `op, `addx16, `carry };
463: oUop = { `update_flags, `addx16, `d};
464: oUop = { `inc_eof, `srx16, `a };
//ADCr_e
465: oUop = { `op, `sx16r, `a };
466: oUop = { `op, `addx16, `carry };
467: oUop = { `update_flags, `addx16, `e};
468: oUop = { `inc_eof, `srx16, `a };
//ADCr_h
469: oUop = { `op, `sx16r, `a };
470: oUop = { `op, `addx16, `carry };
471: oUop = { `update_flags, `addx16, `h};
472: oUop = { `inc_eof, `srx16, `a };
//ADCr_l
473: oUop = { `op, `sx16r, `a };
474: oUop = { `op, `addx16, `carry };
475: oUop = { `update_flags, `addx16, `l};
476: oUop = { `inc_eof, `srx16, `a };
//SHR
477: oUop = { `update_flags, `shr, `null };
478: oUop = { `inc_eof, `nop, `null };
//FLOW_ID_INT_VBLANK
/*
163: oUop = { `op, `ceti, `null}; //Disable interruption
164: oUop = { `inc, `dec16, `sp };
165: oUop = { `inc, `sx16r, `hl };
166: oUop = { `op , `srm, `l }; //l = MEM[pc] = literal
167: oUop = { `inc, `srm, `h }; //l = MEM[pc] = literal
168: oUop = { `op, `sma, `sp };
169: oUop = { `op, `smw, `pch }; //MEM[sp] = pc[7:0]
170: oUop = { `op, `dec16, `sp };
171: oUop = { `op , `smw, `pc }; //MEM[sp+1] = pc[15:8]
172: oUop = { `op , `sx16l, 8'h40 };
173: oUop = { `op, `srx16, `pc };
174: oUop = { `inc ,`sma, `pc };
*/
/*
//RETI
inc sma shadow_addr_reg
op smw
op inc16 x16
op smw b
op inc16 x16
op smw c
op inc16 x16
op smw e
op inc16 x16
op smw h
op inc16 x16
op smw l
op inc16 x16
op smw spl
op inc16 x16
op smw sph
*/
default:
oUop = {`op, `nop, `null };
endcase
end
endmodule
|
module amm_master_qsys_with_pcie_sdram_input_efifo_module (
// inputs:
clk,
rd,
reset_n,
wr,
wr_data,
// outputs:
almost_empty,
almost_full,
empty,
full,
rd_data
)
;
output almost_empty;
output almost_full;
output empty;
output full;
output [ 60: 0] rd_data;
input clk;
input rd;
input reset_n;
input wr;
input [ 60: 0] wr_data;
wire almost_empty;
wire almost_full;
wire empty;
reg [ 1: 0] entries;
reg [ 60: 0] entry_0;
reg [ 60: 0] entry_1;
wire full;
reg rd_address;
reg [ 60: 0] rd_data;
wire [ 1: 0] rdwr;
reg wr_address;
assign rdwr = {rd, wr};
assign full = entries == 2;
assign almost_full = entries >= 1;
assign empty = entries == 0;
assign almost_empty = entries <= 1;
always @(entry_0 or entry_1 or rd_address)
begin
case (rd_address) // synthesis parallel_case full_case
1'd0: begin
rd_data = entry_0;
end // 1'd0
1'd1: begin
rd_data = entry_1;
end // 1'd1
default: begin
end // default
endcase // rd_address
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
wr_address <= 0;
rd_address <= 0;
entries <= 0;
end
else
case (rdwr) // synthesis parallel_case full_case
2'd1: begin
// Write data
if (!full)
begin
entries <= entries + 1;
wr_address <= (wr_address == 1) ? 0 : (wr_address + 1);
end
end // 2'd1
2'd2: begin
// Read data
if (!empty)
begin
entries <= entries - 1;
rd_address <= (rd_address == 1) ? 0 : (rd_address + 1);
end
end // 2'd2
2'd3: begin
wr_address <= (wr_address == 1) ? 0 : (wr_address + 1);
rd_address <= (rd_address == 1) ? 0 : (rd_address + 1);
end // 2'd3
default: begin
end // default
endcase // rdwr
end
always @(posedge clk)
begin
//Write data
if (wr & !full)
case (wr_address) // synthesis parallel_case full_case
1'd0: begin
entry_0 <= wr_data;
end // 1'd0
1'd1: begin
entry_1 <= wr_data;
end // 1'd1
default: begin
end // default
endcase // wr_address
end
endmodule
|
module amm_master_qsys_with_pcie_sdram (
// inputs:
az_addr,
az_be_n,
az_cs,
az_data,
az_rd_n,
az_wr_n,
clk,
reset_n,
// outputs:
za_data,
za_valid,
za_waitrequest,
zs_addr,
zs_ba,
zs_cas_n,
zs_cke,
zs_cs_n,
zs_dq,
zs_dqm,
zs_ras_n,
zs_we_n
)
;
output [ 31: 0] za_data;
output za_valid;
output za_waitrequest;
output [ 11: 0] zs_addr;
output [ 1: 0] zs_ba;
output zs_cas_n;
output zs_cke;
output zs_cs_n;
inout [ 31: 0] zs_dq;
output [ 3: 0] zs_dqm;
output zs_ras_n;
output zs_we_n;
input [ 23: 0] az_addr;
input [ 3: 0] az_be_n;
input az_cs;
input [ 31: 0] az_data;
input az_rd_n;
input az_wr_n;
input clk;
input reset_n;
wire [ 23: 0] CODE;
reg ack_refresh_request;
reg [ 23: 0] active_addr;
wire [ 1: 0] active_bank;
reg active_cs_n;
reg [ 31: 0] active_data;
reg [ 3: 0] active_dqm;
reg active_rnw;
wire almost_empty;
wire almost_full;
wire bank_match;
wire [ 9: 0] cas_addr;
wire clk_en;
wire [ 3: 0] cmd_all;
wire [ 2: 0] cmd_code;
wire cs_n;
wire csn_decode;
wire csn_match;
wire [ 23: 0] f_addr;
wire [ 1: 0] f_bank;
wire f_cs_n;
wire [ 31: 0] f_data;
wire [ 3: 0] f_dqm;
wire f_empty;
reg f_pop;
wire f_rnw;
wire f_select;
wire [ 60: 0] fifo_read_data;
reg [ 11: 0] i_addr;
reg [ 3: 0] i_cmd;
reg [ 2: 0] i_count;
reg [ 2: 0] i_next;
reg [ 2: 0] i_refs;
reg [ 2: 0] i_state;
reg init_done;
reg [ 11: 0] m_addr /* synthesis ALTERA_ATTRIBUTE = "FAST_OUTPUT_REGISTER=ON" */;
reg [ 1: 0] m_bank /* synthesis ALTERA_ATTRIBUTE = "FAST_OUTPUT_REGISTER=ON" */;
reg [ 3: 0] m_cmd /* synthesis ALTERA_ATTRIBUTE = "FAST_OUTPUT_REGISTER=ON" */;
reg [ 2: 0] m_count;
reg [ 31: 0] m_data /* synthesis ALTERA_ATTRIBUTE = "FAST_OUTPUT_REGISTER=ON ; FAST_OUTPUT_ENABLE_REGISTER=ON" */;
reg [ 3: 0] m_dqm /* synthesis ALTERA_ATTRIBUTE = "FAST_OUTPUT_REGISTER=ON" */;
reg [ 8: 0] m_next;
reg [ 8: 0] m_state;
reg oe /* synthesis ALTERA_ATTRIBUTE = "FAST_OUTPUT_ENABLE_REGISTER=ON" */;
wire pending;
wire rd_strobe;
reg [ 2: 0] rd_valid;
reg [ 12: 0] refresh_counter;
reg refresh_request;
wire rnw_match;
wire row_match;
wire [ 23: 0] txt_code;
reg za_cannotrefresh;
reg [ 31: 0] za_data /* synthesis ALTERA_ATTRIBUTE = "FAST_INPUT_REGISTER=ON" */;
reg za_valid;
wire za_waitrequest;
wire [ 11: 0] zs_addr;
wire [ 1: 0] zs_ba;
wire zs_cas_n;
wire zs_cke;
wire zs_cs_n;
wire [ 31: 0] zs_dq;
wire [ 3: 0] zs_dqm;
wire zs_ras_n;
wire zs_we_n;
assign clk_en = 1;
//s1, which is an e_avalon_slave
assign {zs_cs_n, zs_ras_n, zs_cas_n, zs_we_n} = m_cmd;
assign zs_addr = m_addr;
assign zs_cke = clk_en;
assign zs_dq = oe?m_data:{32{1'bz}};
assign zs_dqm = m_dqm;
assign zs_ba = m_bank;
assign f_select = f_pop & pending;
assign f_cs_n = 1'b0;
assign cs_n = f_select ? f_cs_n : active_cs_n;
assign csn_decode = cs_n;
assign {f_rnw, f_addr, f_dqm, f_data} = fifo_read_data;
amm_master_qsys_with_pcie_sdram_input_efifo_module the_amm_master_qsys_with_pcie_sdram_input_efifo_module
(
.almost_empty (almost_empty),
.almost_full (almost_full),
.clk (clk),
.empty (f_empty),
.full (za_waitrequest),
.rd (f_select),
.rd_data (fifo_read_data),
.reset_n (reset_n),
.wr ((~az_wr_n | ~az_rd_n) & !za_waitrequest),
.wr_data ({az_wr_n, az_addr, az_wr_n ? 4'b0 : az_be_n, az_data})
);
assign f_bank = {f_addr[23],f_addr[10]};
// Refresh/init counter.
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
refresh_counter <= 5000;
else if (refresh_counter == 0)
refresh_counter <= 781;
else
refresh_counter <= refresh_counter - 1'b1;
end
// Refresh request signal.
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
refresh_request <= 0;
else if (1)
refresh_request <= ((refresh_counter == 0) | refresh_request) & ~ack_refresh_request & init_done;
end
// Generate an Interrupt if two ref_reqs occur before one ack_refresh_request
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
za_cannotrefresh <= 0;
else if (1)
za_cannotrefresh <= (refresh_counter == 0) & refresh_request;
end
// Initialization-done flag.
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
init_done <= 0;
else if (1)
init_done <= init_done | (i_state == 3'b101);
end
// **** Init FSM ****
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
i_state <= 3'b000;
i_next <= 3'b000;
i_cmd <= 4'b1111;
i_addr <= {12{1'b1}};
i_count <= {3{1'b0}};
end
else
begin
i_addr <= {12{1'b1}};
case (i_state) // synthesis parallel_case full_case
3'b000: begin
i_cmd <= 4'b1111;
i_refs <= 3'b0;
//Wait for refresh count-down after reset
if (refresh_counter == 0)
i_state <= 3'b001;
end // 3'b000
3'b001: begin
i_state <= 3'b011;
i_cmd <= {{1{1'b0}},3'h2};
i_count <= 0;
i_next <= 3'b010;
end // 3'b001
3'b010: begin
i_cmd <= {{1{1'b0}},3'h1};
i_refs <= i_refs + 1'b1;
i_state <= 3'b011;
i_count <= 3;
// Count up init_refresh_commands
if (i_refs == 3'h1)
i_next <= 3'b111;
else
i_next <= 3'b010;
end // 3'b010
3'b011: begin
i_cmd <= {{1{1'b0}},3'h7};
//WAIT til safe to Proceed...
if (i_count > 1)
i_count <= i_count - 1'b1;
else
i_state <= i_next;
end // 3'b011
3'b101: begin
i_state <= 3'b101;
end // 3'b101
3'b111: begin
i_state <= 3'b011;
i_cmd <= {{1{1'b0}},3'h0};
i_addr <= {{2{1'b0}},1'b0,2'b00,3'h3,4'h0};
i_count <= 4;
i_next <= 3'b101;
end // 3'b111
default: begin
i_state <= 3'b000;
end // default
endcase // i_state
end
end
assign active_bank = {active_addr[23],active_addr[10]};
assign csn_match = active_cs_n == f_cs_n;
assign rnw_match = active_rnw == f_rnw;
assign bank_match = active_bank == f_bank;
assign row_match = {active_addr[22 : 11]} == {f_addr[22 : 11]};
assign pending = csn_match && rnw_match && bank_match && row_match && !f_empty;
assign cas_addr = f_select ? { {2{1'b0}},f_addr[9 : 0] } : { {2{1'b0}},active_addr[9 : 0] };
// **** Main FSM ****
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
m_state <= 9'b000000001;
m_next <= 9'b000000001;
m_cmd <= 4'b1111;
m_bank <= 2'b00;
m_addr <= 12'b000000000000;
m_data <= 32'b00000000000000000000000000000000;
m_dqm <= 4'b0000;
m_count <= 3'b000;
ack_refresh_request <= 1'b0;
f_pop <= 1'b0;
oe <= 1'b0;
end
else
begin
f_pop <= 1'b0;
oe <= 1'b0;
case (m_state) // synthesis parallel_case full_case
9'b000000001: begin
//Wait for init-fsm to be done...
if (init_done)
begin
//Hold bus if another cycle ended to arf.
if (refresh_request)
m_cmd <= {{1{1'b0}},3'h7};
else
m_cmd <= 4'b1111;
ack_refresh_request <= 1'b0;
//Wait for a read/write request.
if (refresh_request)
begin
m_state <= 9'b001000000;
m_next <= 9'b010000000;
m_count <= 0;
active_cs_n <= 1'b1;
end
else if (!f_empty)
begin
f_pop <= 1'b1;
active_cs_n <= f_cs_n;
active_rnw <= f_rnw;
active_addr <= f_addr;
active_data <= f_data;
active_dqm <= f_dqm;
m_state <= 9'b000000010;
end
end
else
begin
m_addr <= i_addr;
m_state <= 9'b000000001;
m_next <= 9'b000000001;
m_cmd <= i_cmd;
end
end // 9'b000000001
9'b000000010: begin
m_state <= 9'b000000100;
m_cmd <= {csn_decode,3'h3};
m_bank <= active_bank;
m_addr <= active_addr[22 : 11];
m_data <= active_data;
m_dqm <= active_dqm;
m_count <= 1;
m_next <= active_rnw ? 9'b000001000 : 9'b000010000;
end // 9'b000000010
9'b000000100: begin
// precharge all if arf, else precharge csn_decode
if (m_next == 9'b010000000)
m_cmd <= {{1{1'b0}},3'h7};
else
m_cmd <= {csn_decode,3'h7};
//Count down til safe to Proceed...
if (m_count > 1)
m_count <= m_count - 1'b1;
else
m_state <= m_next;
end // 9'b000000100
9'b000001000: begin
m_cmd <= {csn_decode,3'h5};
m_bank <= f_select ? f_bank : active_bank;
m_dqm <= f_select ? f_dqm : active_dqm;
m_addr <= cas_addr;
//Do we have a transaction pending?
if (pending)
begin
//if we need to ARF, bail, else spin
if (refresh_request)
begin
m_state <= 9'b000000100;
m_next <= 9'b000000001;
m_count <= 2;
end
else
begin
f_pop <= 1'b1;
active_cs_n <= f_cs_n;
active_rnw <= f_rnw;
active_addr <= f_addr;
active_data <= f_data;
active_dqm <= f_dqm;
end
end
else
begin
//correctly end RD spin cycle if fifo mt
if (~pending & f_pop)
m_cmd <= {csn_decode,3'h7};
m_state <= 9'b100000000;
end
end // 9'b000001000
9'b000010000: begin
m_cmd <= {csn_decode,3'h4};
oe <= 1'b1;
m_data <= f_select ? f_data : active_data;
m_dqm <= f_select ? f_dqm : active_dqm;
m_bank <= f_select ? f_bank : active_bank;
m_addr <= cas_addr;
//Do we have a transaction pending?
if (pending)
begin
//if we need to ARF, bail, else spin
if (refresh_request)
begin
m_state <= 9'b000000100;
m_next <= 9'b000000001;
m_count <= 1;
end
else
begin
f_pop <= 1'b1;
active_cs_n <= f_cs_n;
active_rnw <= f_rnw;
active_addr <= f_addr;
active_data <= f_data;
active_dqm <= f_dqm;
end
end
else
begin
//correctly end WR spin cycle if fifo empty
if (~pending & f_pop)
begin
m_cmd <= {csn_decode,3'h7};
oe <= 1'b0;
end
m_state <= 9'b100000000;
end
end // 9'b000010000
9'b000100000: begin
m_cmd <= {csn_decode,3'h7};
//Count down til safe to Proceed...
if (m_count > 1)
m_count <= m_count - 1'b1;
else
begin
m_state <= 9'b001000000;
m_count <= 0;
end
end // 9'b000100000
9'b001000000: begin
m_state <= 9'b000000100;
m_addr <= {12{1'b1}};
// precharge all if arf, else precharge csn_decode
if (refresh_request)
m_cmd <= {{1{1'b0}},3'h2};
else
m_cmd <= {csn_decode,3'h2};
end // 9'b001000000
9'b010000000: begin
ack_refresh_request <= 1'b1;
m_state <= 9'b000000100;
m_cmd <= {{1{1'b0}},3'h1};
m_count <= 3;
m_next <= 9'b000000001;
end // 9'b010000000
9'b100000000: begin
m_cmd <= {csn_decode,3'h7};
//if we need to ARF, bail, else spin
if (refresh_request)
begin
m_state <= 9'b000000100;
m_next <= 9'b000000001;
m_count <= 1;
end
else //wait for fifo to have contents
if (!f_empty)
//Are we 'pending' yet?
if (csn_match && rnw_match && bank_match && row_match)
begin
m_state <= f_rnw ? 9'b000001000 : 9'b000010000;
f_pop <= 1'b1;
active_cs_n <= f_cs_n;
active_rnw <= f_rnw;
active_addr <= f_addr;
active_data <= f_data;
active_dqm <= f_dqm;
end
else
begin
m_state <= 9'b000100000;
m_next <= 9'b000000001;
m_count <= 1;
end
end // 9'b100000000
// synthesis translate_off
default: begin
m_state <= m_state;
m_cmd <= 4'b1111;
f_pop <= 1'b0;
oe <= 1'b0;
end // default
// synthesis translate_on
endcase // m_state
end
end
assign rd_strobe = m_cmd[2 : 0] == 3'h5;
//Track RD Req's based on cas_latency w/shift reg
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
rd_valid <= {3{1'b0}};
else
rd_valid <= (rd_valid << 1) | { {2{1'b0}}, rd_strobe };
end
// Register dq data.
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
za_data <= 0;
else
za_data <= zs_dq;
end
// Delay za_valid to match registered data.
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
za_valid <= 0;
else if (1)
za_valid <= rd_valid[2];
end
assign cmd_code = m_cmd[2 : 0];
assign cmd_all = m_cmd;
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
initial
begin
$write("\n");
$write("This reference design requires a vendor simulation model.\n");
$write("To simulate accesses to SDRAM, you must:\n");
$write(" - Download the vendor model\n");
$write(" - Install the model in the system_sim directory\n");
$write(" - `include the vendor model in the the top-level system file,\n");
$write(" - Instantiate sdram simulation models and wire them to testbench signals\n");
$write(" - Be aware that you may have to disable some timing checks in the vendor model\n");
$write(" (because this simulation is zero-delay based)\n");
$write("\n");
end
assign txt_code = (cmd_code == 3'h0)? 24'h4c4d52 :
(cmd_code == 3'h1)? 24'h415246 :
(cmd_code == 3'h2)? 24'h505245 :
(cmd_code == 3'h3)? 24'h414354 :
(cmd_code == 3'h4)? 24'h205752 :
(cmd_code == 3'h5)? 24'h205244 :
(cmd_code == 3'h6)? 24'h425354 :
(cmd_code == 3'h7)? 24'h4e4f50 :
24'h424144;
assign CODE = &(cmd_all|4'h7) ? 24'h494e48 : txt_code;
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
endmodule
|
module sky130_fd_sc_hs__maj3_2 (
X ,
A ,
B ,
C ,
VPWR,
VGND
);
output X ;
input A ;
input B ;
input C ;
input VPWR;
input VGND;
sky130_fd_sc_hs__maj3 base (
.X(X),
.A(A),
.B(B),
.C(C),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
|
module sky130_fd_sc_hs__maj3_2 (
X,
A,
B,
C
);
output X;
input A;
input B;
input C;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__maj3 base (
.X(X),
.A(A),
.B(B),
.C(C)
);
endmodule
|
module sky130_fd_sc_lp__o21a (
//# {{data|Data Signals}}
input A1 ,
input A2 ,
input B1 ,
output X ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
|
module dff (CK,Q,D);
input CK,D;
output Q;
wire NM,NCK;
trireg NQ,M;
nmos N7 (M,D,NCK);
not P3 (NM,M);
nmos N9 (NQ,NM,CK);
not P5 (Q,NQ);
not P1 (NCK,CK);
endmodule
|
module s420(GND,VDD,CK,C_0,C_1,C_10,C_11,C_12,C_13,C_14,C_15,C_16,C_2,C_3,C_4,
C_5,C_6,C_7,C_8,C_9,P_0,Z);
input GND,VDD,CK,P_0,C_16,C_15,C_14,C_13,C_12,C_11,C_10,C_9,C_8,C_7,C_6,C_5,
C_4,C_3,C_2,C_1,C_0;
output Z;
wire X_4,I12,X_3,I13,X_2,I14,X_1,I15,X_8,I110,X_7,I111,X_6,I112,X_5,I113,
X_12,I208,X_11,I209,X_10,I210,X_9,I211,X_16,I306,X_15,I307,X_14,I308,X_13,
I309,I73_1,I69,I73_2,I7_1,I66,I7_2,I88_1,I88_2,I48,I49,I50,I68,I171_1,I167,
I171_2,I105_1,I164,I105_2,I186_1,I186_2,I1_2,I146,I147,I148,I166,I269_1,
I265,I269_2,I203_1,I262,I203_2,I284_1,I284_2,I1_3,I244,I245,I246,I264,
I301_1,I359,I301_2,I378_1,I378_2,I1_4,I344,I345,I357,I358,I360,I410,I411,
I412,I413,I414,I423,I422,I438,I439,I440,I441,I442,I451,I450,I466,I467,I468,
I469,I470,I479,I478,I494,I495,I496,I497,I498,I506,I505,I546,P_2,I547,P_3,
I550,I551,I570,P_6,I571,P_7,I574,I575,I594,P_10,I595,P_11,I598,I599,I618,
P_14,I619,P_15,I622,I623,I73_3,I73_4,I7_3,I7_4,I88_3,I88_4,I171_3,I171_4,
I105_3,I105_4,I186_3,I186_4,I269_3,I269_4,I203_3,I203_4,I284_3,I284_4,
I301_3,I301_4,I378_3,I378_4,I387_1,I2_1,I2_2,I2_3,I408_2,I407_1,I407_2,
I408_3,I407_3,P_5,I403_2,I404_2,I405_2,P_8,I406_2,P_9,I403_3,I404_3,I405_3,
P_12,I406_3,P_13,I403_4,I404_4,I405_4,P_16,I406_4,I559_1,P_1,I559_2,I583_1,
I583_2,P_4,I607_1,I607_2,I631_1,I631_2,I534_5,I70_1,I95_1,I64,I168_1,
I193_1,I162,I266_1,I291_1,I260,I363_1,I361,I366_1,I384_1,I555_1,I555_2,
I579_1,I579_2,I603_1,I603_2,I627_1,I627_2,I534_2,I533_1,I533_2,I534_3,
I533_3,I534_4,I533_4,I62,I160,I258,I355,I420,I448,I476,I503,I554,I578,I602,
I626;
dff DFF_0(CK,X_4,I12);
dff DFF_1(CK,X_3,I13);
dff DFF_2(CK,X_2,I14);
dff DFF_3(CK,X_1,I15);
dff DFF_4(CK,X_8,I110);
dff DFF_5(CK,X_7,I111);
dff DFF_6(CK,X_6,I112);
dff DFF_7(CK,X_5,I113);
dff DFF_8(CK,X_12,I208);
dff DFF_9(CK,X_11,I209);
dff DFF_10(CK,X_10,I210);
dff DFF_11(CK,X_9,I211);
dff DFF_12(CK,X_16,I306);
dff DFF_13(CK,X_15,I307);
dff DFF_14(CK,X_14,I308);
dff DFF_15(CK,X_13,I309);
not NOT_0(I73_1,I69);
not NOT_1(I73_2,X_3);
not NOT_2(I7_1,I66);
not NOT_3(I7_2,X_2);
not NOT_4(I88_1,X_1);
not NOT_5(I88_2,P_0);
not NOT_6(I48,P_0);
not NOT_7(I49,X_4);
not NOT_8(I50,X_3);
not NOT_9(I68,I69);
not NOT_10(I171_1,I167);
not NOT_11(I171_2,X_7);
not NOT_12(I105_1,I164);
not NOT_13(I105_2,X_6);
not NOT_14(I186_1,X_5);
not NOT_15(I186_2,I1_2);
not NOT_16(I146,I1_2);
not NOT_17(I147,X_8);
not NOT_18(I148,X_7);
not NOT_19(I166,I167);
not NOT_20(I269_1,I265);
not NOT_21(I269_2,X_11);
not NOT_22(I203_1,I262);
not NOT_23(I203_2,X_10);
not NOT_24(I284_1,X_9);
not NOT_25(I284_2,I1_3);
not NOT_26(I244,I1_3);
not NOT_27(I245,X_12);
not NOT_28(I246,X_11);
not NOT_29(I264,I265);
not NOT_30(I301_1,I359);
not NOT_31(I301_2,X_14);
not NOT_32(I378_1,X_13);
not NOT_33(I378_2,I1_4);
not NOT_34(I344,X_15);
not NOT_35(I345,X_14);
not NOT_36(I357,I358);
not NOT_37(I360,I359);
not NOT_38(I410,P_0);
not NOT_39(I411,X_1);
not NOT_40(I412,X_2);
not NOT_41(I413,X_3);
not NOT_42(I414,X_4);
not NOT_43(I423,I422);
not NOT_44(I438,P_0);
not NOT_45(I439,X_5);
not NOT_46(I440,X_6);
not NOT_47(I441,X_7);
not NOT_48(I442,X_8);
not NOT_49(I451,I450);
not NOT_50(I466,P_0);
not NOT_51(I467,X_9);
not NOT_52(I468,X_10);
not NOT_53(I469,X_11);
not NOT_54(I470,X_12);
not NOT_55(I479,I478);
not NOT_56(I494,P_0);
not NOT_57(I495,X_13);
not NOT_58(I496,X_14);
not NOT_59(I497,X_15);
not NOT_60(I498,X_16);
not NOT_61(I506,I505);
not NOT_62(I546,P_2);
not NOT_63(I547,P_3);
not NOT_64(I550,C_2);
not NOT_65(I551,C_3);
not NOT_66(I570,P_6);
not NOT_67(I571,P_7);
not NOT_68(I574,C_6);
not NOT_69(I575,C_7);
not NOT_70(I594,P_10);
not NOT_71(I595,P_11);
not NOT_72(I598,C_10);
not NOT_73(I599,C_11);
not NOT_74(I618,P_14);
not NOT_75(I619,P_15);
not NOT_76(I622,C_14);
not NOT_77(I623,C_15);
and AND2_0(I73_3,I69,I73_2);
and AND2_1(I73_4,X_3,I73_1);
and AND2_2(I7_3,I66,I7_2);
and AND2_3(I7_4,X_2,I7_1);
and AND2_4(I88_3,X_1,I88_2);
and AND2_5(I88_4,P_0,I88_1);
and AND2_6(I171_3,I167,I171_2);
and AND2_7(I171_4,X_7,I171_1);
and AND2_8(I105_3,I164,I105_2);
and AND2_9(I105_4,X_6,I105_1);
and AND2_10(I186_3,X_5,I186_2);
and AND2_11(I186_4,I1_2,I186_1);
and AND2_12(I269_3,I265,I269_2);
and AND2_13(I269_4,X_11,I269_1);
and AND2_14(I203_3,I262,I203_2);
and AND2_15(I203_4,X_10,I203_1);
and AND2_16(I284_3,X_9,I284_2);
and AND2_17(I284_4,I1_3,I284_1);
and AND2_18(I301_3,I359,I301_2);
and AND2_19(I301_4,X_14,I301_1);
and AND2_20(I378_3,X_13,I378_2);
and AND2_21(I378_4,I1_4,I378_1);
and AND2_22(I387_1,I360,X_14);
and AND2_23(I1_2,I2_1,P_0);
and AND2_24(I1_3,I2_2,I1_2);
and AND2_25(I1_4,I2_3,I1_3);
and AND2_26(I408_2,I407_1,I407_2);
and AND2_27(I408_3,I408_2,I407_3);
and AND2_28(P_5,I407_1,I403_2);
and AND2_29(P_6,I407_1,I404_2);
and AND2_30(P_7,I407_1,I405_2);
and AND2_31(P_8,I407_1,I406_2);
and AND2_32(P_9,I408_2,I403_3);
and AND2_33(P_10,I408_2,I404_3);
and AND2_34(P_11,I408_2,I405_3);
and AND2_35(P_12,I408_2,I406_3);
and AND2_36(P_13,I408_3,I403_4);
and AND2_37(P_14,I408_3,I404_4);
and AND2_38(P_15,I408_3,I405_4);
and AND2_39(P_16,I408_3,I406_4);
and AND2_40(I559_1,P_1,C_1);
and AND2_41(I559_2,P_0,C_0);
and AND2_42(I583_1,P_5,C_5);
and AND2_43(I583_2,P_4,C_4);
and AND2_44(I607_1,P_9,C_9);
and AND2_45(I607_2,P_8,C_8);
and AND2_46(I631_1,P_13,C_13);
and AND2_47(I631_2,P_12,C_12);
and AND2_48(I534_5,P_16,C_16);
or OR3_0(I70_1,I68,X_4,I50);
or OR2_0(I13,I73_3,I73_4);
or OR2_1(I15,I88_3,I88_4);
or OR3_1(I95_1,I64,I50,I48);
or OR3_2(I168_1,I166,X_8,I148);
or OR2_2(I111,I171_3,I171_4);
or OR2_3(I113,I186_3,I186_4);
or OR3_3(I193_1,I162,I148,I146);
or OR3_4(I266_1,I264,X_12,I246);
or OR2_4(I209,I269_3,I269_4);
or OR2_5(I211,I284_3,I284_4);
or OR3_5(I291_1,I260,I246,I244);
or OR3_6(I363_1,I361,X_16,I344);
or OR2_6(I366_1,I361,X_15);
or OR2_7(I309,I378_3,I378_4);
or OR3_7(I384_1,I359,I345,I344);
or OR2_8(I555_1,I547,I551);
or OR2_9(I555_2,I546,I550);
or OR2_10(I579_1,I571,I575);
or OR2_11(I579_2,I570,I574);
or OR2_12(I603_1,I595,I599);
or OR2_13(I603_2,I594,I598);
or OR2_14(I627_1,I619,I623);
or OR2_15(I627_2,I618,I622);
or OR2_16(I534_2,I533_1,I533_2);
or OR2_17(I534_3,I534_2,I533_3);
or OR2_18(I534_4,I534_3,I533_4);
or OR2_19(Z,I534_4,I534_5);
nand NAND2_0(I12,I70_1,I62);
nand NAND2_1(I62,I95_1,X_4);
nand NAND2_2(I64,X_1,X_2);
nand NAND2_3(I66,X_1,P_0);
nand NAND2_4(I110,I168_1,I160);
nand NAND2_5(I160,I193_1,X_8);
nand NAND2_6(I162,X_5,X_6);
nand NAND2_7(I164,X_5,I1_2);
nand NAND2_8(I208,I266_1,I258);
nand NAND2_9(I258,I291_1,X_12);
nand NAND2_10(I260,X_9,X_10);
nand NAND2_11(I262,X_9,I1_3);
nand NAND2_12(I306,I363_1,I355);
nand NAND2_13(I307,I366_1,I357);
nand NAND2_14(I355,I384_1,X_16);
nand NAND2_15(I359,X_13,I1_4);
nand NAND2_16(I361,I360,X_14);
nand NAND2_17(I420,I423,I412);
nand NAND2_18(I422,I411,P_0);
nand NAND2_19(I448,I451,I440);
nand NAND2_20(I450,I439,P_0);
nand NAND2_21(I476,I479,I468);
nand NAND2_22(I478,I467,P_0);
nand NAND2_23(I503,I506,I496);
nand NAND2_24(I505,I495,P_0);
nand NAND3_0(I533_1,I555_1,I555_2,I554);
nand NAND3_1(I533_2,I579_1,I579_2,I578);
nand NAND3_2(I533_3,I603_1,I603_2,I602);
nand NAND3_3(I533_4,I627_1,I627_2,I626);
nor NOR2_0(I14,I7_3,I7_4);
nor NOR3_0(I2_1,I64,I49,I50);
nor NOR2_1(I69,I64,I48);
nor NOR2_2(I112,I105_3,I105_4);
nor NOR3_1(I2_2,I162,I147,I148);
nor NOR2_3(I167,I162,I146);
nor NOR2_4(I210,I203_3,I203_4);
nor NOR3_2(I2_3,I260,I245,I246);
nor NOR2_5(I265,I260,I244);
nor NOR2_6(I308,I301_3,I301_4);
nor NOR2_7(I358,I344,I387_1);
nor NOR2_8(P_1,I410,I411);
nor NOR2_9(P_2,I412,I422);
nor NOR2_10(P_3,I413,I420);
nor NOR3_3(P_4,X_3,I420,I414);
nor NOR4_0(I407_1,X_4,X_2,X_3,X_1);
nor NOR2_11(I403_2,I438,I439);
nor NOR2_12(I404_2,I440,I450);
nor NOR2_13(I405_2,I441,I448);
nor NOR3_4(I406_2,X_7,I448,I442);
nor NOR4_1(I407_2,X_8,X_6,X_7,X_5);
nor NOR2_14(I403_3,I466,I467);
nor NOR2_15(I404_3,I468,I478);
nor NOR2_16(I405_3,I469,I476);
nor NOR3_5(I406_3,X_11,I476,I470);
nor NOR4_2(I407_3,X_12,X_10,X_11,X_9);
nor NOR2_17(I403_4,I494,I495);
nor NOR2_18(I404_4,I496,I505);
nor NOR2_19(I405_4,I497,I503);
nor NOR3_6(I406_4,X_15,I503,I498);
nor NOR2_20(I554,I559_1,I559_2);
nor NOR2_21(I578,I583_1,I583_2);
nor NOR2_22(I602,I607_1,I607_2);
nor NOR2_23(I626,I631_1,I631_2);
endmodule
|
module that gives the input to logic anlzer has 2 cycle
// delay and input_clk_counter is comapred with value 2 to get the actual edge.
// If input_clk_divider is 0 every edge is correct, and if input_clk_divider is 1,
// when input_counter_r is zero is the actual edge.
assign delayed_input_clk_edge = (input_clk_divider<maxDivisionWidth_p'(2)) ?
(input_counter_r == maxDivisionWidth_p'(0)) :
(input_counter_r == maxDivisionWidth_p'(2)) ;
// when data is ready to send from Logic Analyzer FIFO to output, fifo will
// be dequed until it gets empty.
// Due to output_ready signal which is reset dependent, this singal does not
// assert during reset.
assign LA_deque = ready_to_LA & LA_valid;
// Due to fifo_relays in both mesosync_input and mesosync_output, we need
// 2 less elements in logic analyzer's fifo (each fifo_relay keeps 2 one bit
// values, hence we would get 2 two bit fifos in totall).
bsg_logic_analyzer #( .line_width_p(width_lp)
, .LA_els_p(LA_els_p)
) logic_analyzer
( .clk(clk)
, .reset(channel_reset)
, .valid_en_i(output_mode_is_LA)
, .posedge_value_i(posedge_synchronized)
, .negedge_value_i(negedge_synchronized)
, .input_bit_selector_i(la_input_bit_selector)
, .start_i(LA_trigger)
, .ready_o()
, .logic_analyzer_data_o(LA_data)
, .v_o(LA_valid)
, .deque_i(LA_deque)
);
endmodule
|
module outputs
wire [152 : 0] server_response_get;
wire [127 : 0] wmiS0_SData;
wire [31 : 0] wci_s_SData, wmiS0_SFlag;
wire [1 : 0] wci_s_SFlag, wci_s_SResp, wmiS0_SResp;
wire RDY_server_request_put,
RDY_server_response_get,
wci_s_SThreadBusy,
wmiS0_SDataThreadBusy,
wmiS0_SReset_n,
wmiS0_SRespLast,
wmiS0_SThreadBusy,
wti_s_SReset_n,
wti_s_SThreadBusy;
// inlined wires
wire [145 : 0] wmi_wmi_wmiDh_wget;
wire [129 : 0] wmi_wmi_respF_x_wire_wget;
wire [127 : 0] wmi_Es_mData_w_wget;
wire [71 : 0] wci_wciReq_wget;
wire [66 : 0] wti_wtiReq_wget;
wire [63 : 0] tlp_nowW_wget, wmi_nowW_wget;
wire [33 : 0] wci_respF_x_wire_wget;
wire [31 : 0] bram_0_serverAdapterA_outData_enqData_wget,
bram_0_serverAdapterA_outData_outData_wget,
bram_0_serverAdapterB_outData_enqData_wget,
bram_0_serverAdapterB_outData_outData_wget,
bram_1_serverAdapterA_outData_enqData_wget,
bram_1_serverAdapterA_outData_outData_wget,
bram_1_serverAdapterB_outData_enqData_wget,
bram_1_serverAdapterB_outData_outData_wget,
bram_2_serverAdapterA_outData_enqData_wget,
bram_2_serverAdapterA_outData_outData_wget,
bram_2_serverAdapterB_outData_enqData_wget,
bram_2_serverAdapterB_outData_outData_wget,
bram_3_serverAdapterA_outData_enqData_wget,
bram_3_serverAdapterA_outData_outData_wget,
bram_3_serverAdapterB_outData_enqData_wget,
bram_3_serverAdapterB_outData_outData_wget,
wci_Es_mAddr_w_wget,
wci_Es_mData_w_wget,
wmi_wmi_wmiMFlag_wget,
wmi_wmi_wmiReq_wget;
wire [15 : 0] bml_crdBuf_modulus_bw_wget,
bml_fabBuf_modulus_bw_wget,
bml_lclBuf_modulus_bw_wget,
bml_remBuf_modulus_bw_wget,
wmi_Es_mDataByteEn_w_wget;
wire [13 : 0] wmi_Es_mAddr_w_wget;
wire [11 : 0] wmi_Es_mBurstLength_w_wget;
wire [7 : 0] bml_dpControl_wget, tlp_dpControl_wget, wmi_dpControl_wget;
wire [3 : 0] wci_Es_mByteEn_w_wget;
wire [2 : 0] bram_0_serverAdapterA_cnt_1_wget,
bram_0_serverAdapterA_cnt_2_wget,
bram_0_serverAdapterA_cnt_3_wget,
bram_0_serverAdapterB_cnt_1_wget,
bram_0_serverAdapterB_cnt_2_wget,
bram_0_serverAdapterB_cnt_3_wget,
bram_1_serverAdapterA_cnt_1_wget,
bram_1_serverAdapterA_cnt_2_wget,
bram_1_serverAdapterA_cnt_3_wget,
bram_1_serverAdapterB_cnt_1_wget,
bram_1_serverAdapterB_cnt_2_wget,
bram_1_serverAdapterB_cnt_3_wget,
bram_2_serverAdapterA_cnt_1_wget,
bram_2_serverAdapterA_cnt_2_wget,
bram_2_serverAdapterA_cnt_3_wget,
bram_2_serverAdapterB_cnt_1_wget,
bram_2_serverAdapterB_cnt_2_wget,
bram_2_serverAdapterB_cnt_3_wget,
bram_3_serverAdapterA_cnt_1_wget,
bram_3_serverAdapterA_cnt_2_wget,
bram_3_serverAdapterA_cnt_3_wget,
bram_3_serverAdapterB_cnt_1_wget,
bram_3_serverAdapterB_cnt_2_wget,
bram_3_serverAdapterB_cnt_3_wget,
wci_Es_mCmd_w_wget,
wci_wEdge_wget,
wmi_Es_mCmd_w_wget;
wire [1 : 0] bram_0_serverAdapterA_s1_1_wget,
bram_0_serverAdapterA_writeWithResp_wget,
bram_0_serverAdapterB_s1_1_wget,
bram_0_serverAdapterB_writeWithResp_wget,
bram_1_serverAdapterA_s1_1_wget,
bram_1_serverAdapterA_writeWithResp_wget,
bram_1_serverAdapterB_s1_1_wget,
bram_1_serverAdapterB_writeWithResp_wget,
bram_2_serverAdapterA_s1_1_wget,
bram_2_serverAdapterA_writeWithResp_wget,
bram_2_serverAdapterB_s1_1_wget,
bram_2_serverAdapterB_writeWithResp_wget,
bram_3_serverAdapterA_s1_1_wget,
bram_3_serverAdapterA_writeWithResp_wget,
bram_3_serverAdapterB_s1_1_wget,
bram_3_serverAdapterB_writeWithResp_wget;
wire bml_crdBuf_decAction_whas,
bml_crdBuf_incAction_whas,
bml_datumAReg_1_wget,
bml_datumAReg_1_whas,
bml_dpControl_whas,
bml_fabAvail_1_wget,
bml_fabAvail_1_whas,
bml_fabBuf_decAction_whas,
bml_fabBuf_incAction_whas,
bml_fabDone_1_wget,
bml_fabDone_1_whas,
bml_lclBufDone_1_wget,
bml_lclBufDone_1_whas,
bml_lclBufStart_1_wget,
bml_lclBufStart_1_whas,
bml_lclBuf_decAction_whas,
bml_lclBuf_incAction_whas,
bml_remBuf_decAction_whas,
bml_remBuf_incAction_whas,
bml_remDone_1_wget,
bml_remDone_1_whas,
bml_remStart_1_wget,
bml_remStart_1_whas,
bram_0_serverAdapterA_cnt_1_whas,
bram_0_serverAdapterA_cnt_2_whas,
bram_0_serverAdapterA_cnt_3_whas,
bram_0_serverAdapterA_outData_deqCalled_whas,
bram_0_serverAdapterA_outData_enqData_whas,
bram_0_serverAdapterA_outData_outData_whas,
bram_0_serverAdapterA_s1_1_whas,
bram_0_serverAdapterA_writeWithResp_whas,
bram_0_serverAdapterB_cnt_1_whas,
bram_0_serverAdapterB_cnt_2_whas,
bram_0_serverAdapterB_cnt_3_whas,
bram_0_serverAdapterB_outData_deqCalled_whas,
bram_0_serverAdapterB_outData_enqData_whas,
bram_0_serverAdapterB_outData_outData_whas,
bram_0_serverAdapterB_s1_1_whas,
bram_0_serverAdapterB_writeWithResp_whas,
bram_1_serverAdapterA_cnt_1_whas,
bram_1_serverAdapterA_cnt_2_whas,
bram_1_serverAdapterA_cnt_3_whas,
bram_1_serverAdapterA_outData_deqCalled_whas,
bram_1_serverAdapterA_outData_enqData_whas,
bram_1_serverAdapterA_outData_outData_whas,
bram_1_serverAdapterA_s1_1_whas,
bram_1_serverAdapterA_writeWithResp_whas,
bram_1_serverAdapterB_cnt_1_whas,
bram_1_serverAdapterB_cnt_2_whas,
bram_1_serverAdapterB_cnt_3_whas,
bram_1_serverAdapterB_outData_deqCalled_whas,
bram_1_serverAdapterB_outData_enqData_whas,
bram_1_serverAdapterB_outData_outData_whas,
bram_1_serverAdapterB_s1_1_whas,
bram_1_serverAdapterB_writeWithResp_whas,
bram_2_serverAdapterA_cnt_1_whas,
bram_2_serverAdapterA_cnt_2_whas,
bram_2_serverAdapterA_cnt_3_whas,
bram_2_serverAdapterA_outData_deqCalled_whas,
bram_2_serverAdapterA_outData_enqData_whas,
bram_2_serverAdapterA_outData_outData_whas,
bram_2_serverAdapterA_s1_1_whas,
bram_2_serverAdapterA_writeWithResp_whas,
bram_2_serverAdapterB_cnt_1_whas,
bram_2_serverAdapterB_cnt_2_whas,
bram_2_serverAdapterB_cnt_3_whas,
bram_2_serverAdapterB_outData_deqCalled_whas,
bram_2_serverAdapterB_outData_enqData_whas,
bram_2_serverAdapterB_outData_outData_whas,
bram_2_serverAdapterB_s1_1_whas,
bram_2_serverAdapterB_writeWithResp_whas,
bram_3_serverAdapterA_cnt_1_whas,
bram_3_serverAdapterA_cnt_2_whas,
bram_3_serverAdapterA_cnt_3_whas,
bram_3_serverAdapterA_outData_deqCalled_whas,
bram_3_serverAdapterA_outData_enqData_whas,
bram_3_serverAdapterA_outData_outData_whas,
bram_3_serverAdapterA_s1_1_whas,
bram_3_serverAdapterA_writeWithResp_whas,
bram_3_serverAdapterB_cnt_1_whas,
bram_3_serverAdapterB_cnt_2_whas,
bram_3_serverAdapterB_cnt_3_whas,
bram_3_serverAdapterB_outData_deqCalled_whas,
bram_3_serverAdapterB_outData_enqData_whas,
bram_3_serverAdapterB_outData_outData_whas,
bram_3_serverAdapterB_s1_1_whas,
bram_3_serverAdapterB_writeWithResp_whas,
tlp_creditReady_1_wget,
tlp_creditReady_1_whas,
tlp_dmaDoneMark_1_wget,
tlp_dmaDoneMark_1_whas,
tlp_dmaStartMark_1_wget,
tlp_dmaStartMark_1_whas,
tlp_dpControl_whas,
tlp_farBufReady_1_wget,
tlp_farBufReady_1_whas,
tlp_nearBufReady_1_wget,
tlp_nearBufReady_1_whas,
tlp_nowW_whas,
tlp_pullTagMatch_1_wget,
tlp_pullTagMatch_1_whas,
tlp_remDone_1_wget,
tlp_remDone_1_whas,
tlp_remStart_1_wget,
tlp_remStart_1_whas,
wci_Es_mAddrSpace_w_wget,
wci_Es_mAddrSpace_w_whas,
wci_Es_mAddr_w_whas,
wci_Es_mByteEn_w_whas,
wci_Es_mCmd_w_whas,
wci_Es_mData_w_whas,
wci_ctlAckReg_1_wget,
wci_ctlAckReg_1_whas,
wci_reqF_r_clr_whas,
wci_reqF_r_deq_whas,
wci_reqF_r_enq_whas,
wci_respF_dequeueing_whas,
wci_respF_enqueueing_whas,
wci_respF_x_wire_whas,
wci_sFlagReg_1_wget,
wci_sFlagReg_1_whas,
wci_sThreadBusy_pw_whas,
wci_wEdge_whas,
wci_wciReq_whas,
wci_wci_cfrd_pw_whas,
wci_wci_cfwr_pw_whas,
wci_wci_ctrl_pw_whas,
wmi_Es_mAddrSpace_w_wget,
wmi_Es_mAddrSpace_w_whas,
wmi_Es_mAddr_w_whas,
wmi_Es_mBurstLength_w_whas,
wmi_Es_mCmd_w_whas,
wmi_Es_mDataByteEn_w_whas,
wmi_Es_mDataInfo_w_whas,
wmi_Es_mDataLast_w_whas,
wmi_Es_mDataValid_w_whas,
wmi_Es_mData_w_whas,
wmi_Es_mReqInfo_w_wget,
wmi_Es_mReqInfo_w_whas,
wmi_Es_mReqLast_w_whas,
wmi_dpControl_whas,
wmi_mesgBufReady_1_wget,
wmi_mesgBufReady_1_whas,
wmi_mesgDone_1_wget,
wmi_mesgDone_1_whas,
wmi_mesgStart_1_wget,
wmi_mesgStart_1_whas,
wmi_nowW_whas,
wmi_wmi_dhF_doResetClr_whas,
wmi_wmi_dhF_doResetDeq_whas,
wmi_wmi_dhF_doResetEnq_whas,
wmi_wmi_dhF_r_clr_whas,
wmi_wmi_dhF_r_deq_whas,
wmi_wmi_dhF_r_enq_whas,
wmi_wmi_forceSThreadBusy_pw_whas,
wmi_wmi_mFlagF_doResetClr_whas,
wmi_wmi_mFlagF_doResetDeq_whas,
wmi_wmi_mFlagF_doResetEnq_whas,
wmi_wmi_mFlagF_r_clr_whas,
wmi_wmi_mFlagF_r_deq_whas,
wmi_wmi_mFlagF_r_enq_whas,
wmi_wmi_operateD_1_wget,
wmi_wmi_operateD_1_whas,
wmi_wmi_peerIsReady_1_wget,
wmi_wmi_peerIsReady_1_whas,
wmi_wmi_reqF_doResetClr_whas,
wmi_wmi_reqF_doResetDeq_whas,
wmi_wmi_reqF_doResetEnq_whas,
wmi_wmi_reqF_r_clr_whas,
wmi_wmi_reqF_r_deq_whas,
wmi_wmi_reqF_r_enq_whas,
wmi_wmi_respF_dequeueing_whas,
wmi_wmi_respF_enqueueing_whas,
wmi_wmi_respF_x_wire_whas,
wmi_wmi_sDataThreadBusy_dw_wget,
wmi_wmi_sDataThreadBusy_dw_whas,
wmi_wmi_sThreadBusy_dw_wget,
wmi_wmi_sThreadBusy_dw_whas,
wmi_wmi_wmiDh_whas,
wmi_wmi_wmiMFlag_whas,
wmi_wmi_wmiReq_whas,
wti_operateD_1_wget,
wti_operateD_1_whas,
wti_wtiReq_whas;
// register bml_crdBuf_modulus
reg [15 : 0] bml_crdBuf_modulus;
wire [15 : 0] bml_crdBuf_modulus_D_IN;
wire bml_crdBuf_modulus_EN;
// register bml_crdBuf_value
reg [15 : 0] bml_crdBuf_value;
wire [15 : 0] bml_crdBuf_value_D_IN;
wire bml_crdBuf_value_EN;
// register bml_datumAReg
reg bml_datumAReg;
wire bml_datumAReg_D_IN, bml_datumAReg_EN;
// register bml_fabAvail
reg bml_fabAvail;
wire bml_fabAvail_D_IN, bml_fabAvail_EN;
// register bml_fabBuf_modulus
reg [15 : 0] bml_fabBuf_modulus;
wire [15 : 0] bml_fabBuf_modulus_D_IN;
wire bml_fabBuf_modulus_EN;
// register bml_fabBuf_value
reg [15 : 0] bml_fabBuf_value;
wire [15 : 0] bml_fabBuf_value_D_IN;
wire bml_fabBuf_value_EN;
// register bml_fabBufsAvail
reg [15 : 0] bml_fabBufsAvail;
wire [15 : 0] bml_fabBufsAvail_D_IN;
wire bml_fabBufsAvail_EN;
// register bml_fabDone
reg bml_fabDone;
wire bml_fabDone_D_IN, bml_fabDone_EN;
// register bml_fabFlowAddr
reg [31 : 0] bml_fabFlowAddr;
reg [31 : 0] bml_fabFlowAddr_D_IN;
wire bml_fabFlowAddr_EN;
// register bml_fabFlowBase
reg [31 : 0] bml_fabFlowBase;
wire [31 : 0] bml_fabFlowBase_D_IN;
wire bml_fabFlowBase_EN;
// register bml_fabFlowBaseMS
reg [31 : 0] bml_fabFlowBaseMS;
wire [31 : 0] bml_fabFlowBaseMS_D_IN;
wire bml_fabFlowBaseMS_EN;
// register bml_fabFlowSize
reg [31 : 0] bml_fabFlowSize;
wire [31 : 0] bml_fabFlowSize_D_IN;
wire bml_fabFlowSize_EN;
// register bml_fabMesgAddr
reg [31 : 0] bml_fabMesgAddr;
wire [31 : 0] bml_fabMesgAddr_D_IN;
wire bml_fabMesgAddr_EN;
// register bml_fabMesgBase
reg [31 : 0] bml_fabMesgBase;
wire [31 : 0] bml_fabMesgBase_D_IN;
wire bml_fabMesgBase_EN;
// register bml_fabMesgBaseMS
reg [31 : 0] bml_fabMesgBaseMS;
wire [31 : 0] bml_fabMesgBaseMS_D_IN;
wire bml_fabMesgBaseMS_EN;
// register bml_fabMesgSize
reg [31 : 0] bml_fabMesgSize;
wire [31 : 0] bml_fabMesgSize_D_IN;
wire bml_fabMesgSize_EN;
// register bml_fabMetaAddr
reg [31 : 0] bml_fabMetaAddr;
wire [31 : 0] bml_fabMetaAddr_D_IN;
wire bml_fabMetaAddr_EN;
// register bml_fabMetaBase
reg [31 : 0] bml_fabMetaBase;
wire [31 : 0] bml_fabMetaBase_D_IN;
wire bml_fabMetaBase_EN;
// register bml_fabMetaBaseMS
reg [31 : 0] bml_fabMetaBaseMS;
wire [31 : 0] bml_fabMetaBaseMS_D_IN;
wire bml_fabMetaBaseMS_EN;
// register bml_fabMetaSize
reg [31 : 0] bml_fabMetaSize;
wire [31 : 0] bml_fabMetaSize_D_IN;
wire bml_fabMetaSize_EN;
// register bml_fabNumBufs
reg [15 : 0] bml_fabNumBufs;
wire [15 : 0] bml_fabNumBufs_D_IN;
wire bml_fabNumBufs_EN;
// register bml_lclBufDone
reg bml_lclBufDone;
wire bml_lclBufDone_D_IN, bml_lclBufDone_EN;
// register bml_lclBufStart
reg bml_lclBufStart;
wire bml_lclBufStart_D_IN, bml_lclBufStart_EN;
// register bml_lclBuf_modulus
reg [15 : 0] bml_lclBuf_modulus;
wire [15 : 0] bml_lclBuf_modulus_D_IN;
wire bml_lclBuf_modulus_EN;
// register bml_lclBuf_value
reg [15 : 0] bml_lclBuf_value;
wire [15 : 0] bml_lclBuf_value_D_IN;
wire bml_lclBuf_value_EN;
// register bml_lclBufsAR
reg [15 : 0] bml_lclBufsAR;
wire [15 : 0] bml_lclBufsAR_D_IN;
wire bml_lclBufsAR_EN;
// register bml_lclBufsCF
reg [15 : 0] bml_lclBufsCF;
wire [15 : 0] bml_lclBufsCF_D_IN;
wire bml_lclBufsCF_EN;
// register bml_lclCredit
reg [15 : 0] bml_lclCredit;
wire [15 : 0] bml_lclCredit_D_IN;
wire bml_lclCredit_EN;
// register bml_lclDones
reg [15 : 0] bml_lclDones;
wire [15 : 0] bml_lclDones_D_IN;
wire bml_lclDones_EN;
// register bml_lclMesgAddr
reg [15 : 0] bml_lclMesgAddr;
wire [15 : 0] bml_lclMesgAddr_D_IN;
wire bml_lclMesgAddr_EN;
// register bml_lclMetaAddr
reg [15 : 0] bml_lclMetaAddr;
wire [15 : 0] bml_lclMetaAddr_D_IN;
wire bml_lclMetaAddr_EN;
// register bml_lclNumBufs
reg [15 : 0] bml_lclNumBufs;
wire [15 : 0] bml_lclNumBufs_D_IN;
wire bml_lclNumBufs_EN;
// register bml_lclStarts
reg [15 : 0] bml_lclStarts;
wire [15 : 0] bml_lclStarts_D_IN;
wire bml_lclStarts_EN;
// register bml_mesgBase
reg [15 : 0] bml_mesgBase;
wire [15 : 0] bml_mesgBase_D_IN;
wire bml_mesgBase_EN;
// register bml_mesgSize
reg [15 : 0] bml_mesgSize;
wire [15 : 0] bml_mesgSize_D_IN;
wire bml_mesgSize_EN;
// register bml_metaBase
reg [15 : 0] bml_metaBase;
wire [15 : 0] bml_metaBase_D_IN;
wire bml_metaBase_EN;
// register bml_metaSize
reg [15 : 0] bml_metaSize;
wire [15 : 0] bml_metaSize_D_IN;
wire bml_metaSize_EN;
// register bml_remBuf_modulus
reg [15 : 0] bml_remBuf_modulus;
wire [15 : 0] bml_remBuf_modulus_D_IN;
wire bml_remBuf_modulus_EN;
// register bml_remBuf_value
reg [15 : 0] bml_remBuf_value;
wire [15 : 0] bml_remBuf_value_D_IN;
wire bml_remBuf_value_EN;
// register bml_remDone
reg bml_remDone;
wire bml_remDone_D_IN, bml_remDone_EN;
// register bml_remDones
reg [15 : 0] bml_remDones;
wire [15 : 0] bml_remDones_D_IN;
wire bml_remDones_EN;
// register bml_remMesgAddr
reg [15 : 0] bml_remMesgAddr;
wire [15 : 0] bml_remMesgAddr_D_IN;
wire bml_remMesgAddr_EN;
// register bml_remMetaAddr
reg [15 : 0] bml_remMetaAddr;
wire [15 : 0] bml_remMetaAddr_D_IN;
wire bml_remMetaAddr_EN;
// register bml_remStart
reg bml_remStart;
wire bml_remStart_D_IN, bml_remStart_EN;
// register bml_remStarts
reg [15 : 0] bml_remStarts;
wire [15 : 0] bml_remStarts_D_IN;
wire bml_remStarts_EN;
// register bram_0_serverAdapterA_cnt
reg [2 : 0] bram_0_serverAdapterA_cnt;
wire [2 : 0] bram_0_serverAdapterA_cnt_D_IN;
wire bram_0_serverAdapterA_cnt_EN;
// register bram_0_serverAdapterA_s1
reg [1 : 0] bram_0_serverAdapterA_s1;
wire [1 : 0] bram_0_serverAdapterA_s1_D_IN;
wire bram_0_serverAdapterA_s1_EN;
// register bram_0_serverAdapterB_cnt
reg [2 : 0] bram_0_serverAdapterB_cnt;
wire [2 : 0] bram_0_serverAdapterB_cnt_D_IN;
wire bram_0_serverAdapterB_cnt_EN;
// register bram_0_serverAdapterB_s1
reg [1 : 0] bram_0_serverAdapterB_s1;
wire [1 : 0] bram_0_serverAdapterB_s1_D_IN;
wire bram_0_serverAdapterB_s1_EN;
// register bram_1_serverAdapterA_cnt
reg [2 : 0] bram_1_serverAdapterA_cnt;
wire [2 : 0] bram_1_serverAdapterA_cnt_D_IN;
wire bram_1_serverAdapterA_cnt_EN;
// register bram_1_serverAdapterA_s1
reg [1 : 0] bram_1_serverAdapterA_s1;
wire [1 : 0] bram_1_serverAdapterA_s1_D_IN;
wire bram_1_serverAdapterA_s1_EN;
// register bram_1_serverAdapterB_cnt
reg [2 : 0] bram_1_serverAdapterB_cnt;
wire [2 : 0] bram_1_serverAdapterB_cnt_D_IN;
wire bram_1_serverAdapterB_cnt_EN;
// register bram_1_serverAdapterB_s1
reg [1 : 0] bram_1_serverAdapterB_s1;
wire [1 : 0] bram_1_serverAdapterB_s1_D_IN;
wire bram_1_serverAdapterB_s1_EN;
// register bram_2_serverAdapterA_cnt
reg [2 : 0] bram_2_serverAdapterA_cnt;
wire [2 : 0] bram_2_serverAdapterA_cnt_D_IN;
wire bram_2_serverAdapterA_cnt_EN;
// register bram_2_serverAdapterA_s1
reg [1 : 0] bram_2_serverAdapterA_s1;
wire [1 : 0] bram_2_serverAdapterA_s1_D_IN;
wire bram_2_serverAdapterA_s1_EN;
// register bram_2_serverAdapterB_cnt
reg [2 : 0] bram_2_serverAdapterB_cnt;
wire [2 : 0] bram_2_serverAdapterB_cnt_D_IN;
wire bram_2_serverAdapterB_cnt_EN;
// register bram_2_serverAdapterB_s1
reg [1 : 0] bram_2_serverAdapterB_s1;
wire [1 : 0] bram_2_serverAdapterB_s1_D_IN;
wire bram_2_serverAdapterB_s1_EN;
// register bram_3_serverAdapterA_cnt
reg [2 : 0] bram_3_serverAdapterA_cnt;
wire [2 : 0] bram_3_serverAdapterA_cnt_D_IN;
wire bram_3_serverAdapterA_cnt_EN;
// register bram_3_serverAdapterA_s1
reg [1 : 0] bram_3_serverAdapterA_s1;
wire [1 : 0] bram_3_serverAdapterA_s1_D_IN;
wire bram_3_serverAdapterA_s1_EN;
// register bram_3_serverAdapterB_cnt
reg [2 : 0] bram_3_serverAdapterB_cnt;
wire [2 : 0] bram_3_serverAdapterB_cnt_D_IN;
wire bram_3_serverAdapterB_cnt_EN;
// register bram_3_serverAdapterB_s1
reg [1 : 0] bram_3_serverAdapterB_s1;
wire [1 : 0] bram_3_serverAdapterB_s1_D_IN;
wire bram_3_serverAdapterB_s1_EN;
// register dmaDoneTime
reg [63 : 0] dmaDoneTime;
wire [63 : 0] dmaDoneTime_D_IN;
wire dmaDoneTime_EN;
// register dmaStartTime
reg [63 : 0] dmaStartTime;
wire [63 : 0] dmaStartTime_D_IN;
wire dmaStartTime_EN;
// register dpControl
reg [7 : 0] dpControl;
wire [7 : 0] dpControl_D_IN;
wire dpControl_EN;
// register tlp_complTimerCount
reg [11 : 0] tlp_complTimerCount;
wire [11 : 0] tlp_complTimerCount_D_IN;
wire tlp_complTimerCount_EN;
// register tlp_complTimerRunning
reg tlp_complTimerRunning;
wire tlp_complTimerRunning_D_IN, tlp_complTimerRunning_EN;
// register tlp_creditReady
reg tlp_creditReady;
wire tlp_creditReady_D_IN, tlp_creditReady_EN;
// register tlp_dmaDoTailEvent
reg tlp_dmaDoTailEvent;
reg tlp_dmaDoTailEvent_D_IN;
wire tlp_dmaDoTailEvent_EN;
// register tlp_dmaDoneMark
reg tlp_dmaDoneMark;
wire tlp_dmaDoneMark_D_IN, tlp_dmaDoneMark_EN;
// register tlp_dmaPullRemainDWLen
reg [9 : 0] tlp_dmaPullRemainDWLen;
reg [9 : 0] tlp_dmaPullRemainDWLen_D_IN;
wire tlp_dmaPullRemainDWLen_EN;
// register tlp_dmaPullRemainDWSub
reg [9 : 0] tlp_dmaPullRemainDWSub;
wire [9 : 0] tlp_dmaPullRemainDWSub_D_IN;
wire tlp_dmaPullRemainDWSub_EN;
// register tlp_dmaReqTag
reg [4 : 0] tlp_dmaReqTag;
wire [4 : 0] tlp_dmaReqTag_D_IN;
wire tlp_dmaReqTag_EN;
// register tlp_dmaStartMark
reg tlp_dmaStartMark;
wire tlp_dmaStartMark_D_IN, tlp_dmaStartMark_EN;
// register tlp_dmaTag
reg [4 : 0] tlp_dmaTag;
wire [4 : 0] tlp_dmaTag_D_IN;
wire tlp_dmaTag_EN;
// register tlp_doXmtMetaBody
reg tlp_doXmtMetaBody;
wire tlp_doXmtMetaBody_D_IN, tlp_doXmtMetaBody_EN;
// register tlp_doorSeqDwell
reg [3 : 0] tlp_doorSeqDwell;
wire [3 : 0] tlp_doorSeqDwell_D_IN;
wire tlp_doorSeqDwell_EN;
// register tlp_fabFlowAddr
reg [31 : 0] tlp_fabFlowAddr;
wire [31 : 0] tlp_fabFlowAddr_D_IN;
wire tlp_fabFlowAddr_EN;
// register tlp_fabFlowAddrMS
reg [31 : 0] tlp_fabFlowAddrMS;
wire [31 : 0] tlp_fabFlowAddrMS_D_IN;
wire tlp_fabFlowAddrMS_EN;
// register tlp_fabMesgAccu
reg [31 : 0] tlp_fabMesgAccu;
reg [31 : 0] tlp_fabMesgAccu_D_IN;
wire tlp_fabMesgAccu_EN;
// register tlp_fabMesgAddr
reg [31 : 0] tlp_fabMesgAddr;
wire [31 : 0] tlp_fabMesgAddr_D_IN;
wire tlp_fabMesgAddr_EN;
// register tlp_fabMesgAddrMS
reg [31 : 0] tlp_fabMesgAddrMS;
wire [31 : 0] tlp_fabMesgAddrMS_D_IN;
wire tlp_fabMesgAddrMS_EN;
// register tlp_fabMeta
reg [128 : 0] tlp_fabMeta;
reg [128 : 0] tlp_fabMeta_D_IN;
wire tlp_fabMeta_EN;
// register tlp_fabMetaAddr
reg [31 : 0] tlp_fabMetaAddr;
wire [31 : 0] tlp_fabMetaAddr_D_IN;
wire tlp_fabMetaAddr_EN;
// register tlp_fabMetaAddrMS
reg [31 : 0] tlp_fabMetaAddrMS;
wire [31 : 0] tlp_fabMetaAddrMS_D_IN;
wire tlp_fabMetaAddrMS_EN;
// register tlp_farBufReady
reg tlp_farBufReady;
wire tlp_farBufReady_D_IN, tlp_farBufReady_EN;
// register tlp_flowDiagCount
reg [31 : 0] tlp_flowDiagCount;
wire [31 : 0] tlp_flowDiagCount_D_IN;
wire tlp_flowDiagCount_EN;
// register tlp_gotResponseHeader
reg tlp_gotResponseHeader;
reg tlp_gotResponseHeader_D_IN;
wire tlp_gotResponseHeader_EN;
// register tlp_inIgnorePkt
reg tlp_inIgnorePkt;
wire tlp_inIgnorePkt_D_IN, tlp_inIgnorePkt_EN;
// register tlp_lastMetaV_0
reg [31 : 0] tlp_lastMetaV_0;
wire [31 : 0] tlp_lastMetaV_0_D_IN;
wire tlp_lastMetaV_0_EN;
// register tlp_lastMetaV_1
reg [31 : 0] tlp_lastMetaV_1;
wire [31 : 0] tlp_lastMetaV_1_D_IN;
wire tlp_lastMetaV_1_EN;
// register tlp_lastMetaV_2
reg [31 : 0] tlp_lastMetaV_2;
wire [31 : 0] tlp_lastMetaV_2_D_IN;
wire tlp_lastMetaV_2_EN;
// register tlp_lastMetaV_3
reg [31 : 0] tlp_lastMetaV_3;
wire [31 : 0] tlp_lastMetaV_3_D_IN;
wire tlp_lastMetaV_3_EN;
// register tlp_lastRuleFired
reg [3 : 0] tlp_lastRuleFired;
reg [3 : 0] tlp_lastRuleFired_D_IN;
wire tlp_lastRuleFired_EN;
// register tlp_maxPayloadSize
reg [12 : 0] tlp_maxPayloadSize;
wire [12 : 0] tlp_maxPayloadSize_D_IN;
wire tlp_maxPayloadSize_EN;
// register tlp_maxReadReqSize
reg [12 : 0] tlp_maxReadReqSize;
wire [12 : 0] tlp_maxReadReqSize_D_IN;
wire tlp_maxReadReqSize_EN;
// register tlp_mesgComplReceived
reg [16 : 0] tlp_mesgComplReceived;
reg [16 : 0] tlp_mesgComplReceived_D_IN;
wire tlp_mesgComplReceived_EN;
// register tlp_mesgLengthRemainPull
reg [16 : 0] tlp_mesgLengthRemainPull;
reg [16 : 0] tlp_mesgLengthRemainPull_D_IN;
wire tlp_mesgLengthRemainPull_EN;
// register tlp_mesgLengthRemainPush
reg [16 : 0] tlp_mesgLengthRemainPush;
reg [16 : 0] tlp_mesgLengthRemainPush_D_IN;
wire tlp_mesgLengthRemainPush_EN;
// register tlp_nearBufReady
reg tlp_nearBufReady;
wire tlp_nearBufReady_D_IN, tlp_nearBufReady_EN;
// register tlp_outDwRemain
reg [9 : 0] tlp_outDwRemain;
reg [9 : 0] tlp_outDwRemain_D_IN;
wire tlp_outDwRemain_EN;
// register tlp_postSeqDwell
reg [3 : 0] tlp_postSeqDwell;
wire [3 : 0] tlp_postSeqDwell_D_IN;
wire tlp_postSeqDwell_EN;
// register tlp_pullTagMatch
reg tlp_pullTagMatch;
wire tlp_pullTagMatch_D_IN, tlp_pullTagMatch_EN;
// register tlp_remDone
reg tlp_remDone;
wire tlp_remDone_D_IN, tlp_remDone_EN;
// register tlp_remMesgAccu
reg [15 : 0] tlp_remMesgAccu;
reg [15 : 0] tlp_remMesgAccu_D_IN;
wire tlp_remMesgAccu_EN;
// register tlp_remMesgAddr
reg [15 : 0] tlp_remMesgAddr;
wire [15 : 0] tlp_remMesgAddr_D_IN;
wire tlp_remMesgAddr_EN;
// register tlp_remMetaAddr
reg [15 : 0] tlp_remMetaAddr;
wire [15 : 0] tlp_remMetaAddr_D_IN;
wire tlp_remMetaAddr_EN;
// register tlp_remStart
reg tlp_remStart;
wire tlp_remStart_D_IN, tlp_remStart_EN;
// register tlp_reqMesgInFlight
reg tlp_reqMesgInFlight;
reg tlp_reqMesgInFlight_D_IN;
wire tlp_reqMesgInFlight_EN;
// register tlp_reqMetaBodyInFlight
reg tlp_reqMetaBodyInFlight;
wire tlp_reqMetaBodyInFlight_D_IN, tlp_reqMetaBodyInFlight_EN;
// register tlp_reqMetaInFlight
reg tlp_reqMetaInFlight;
reg tlp_reqMetaInFlight_D_IN;
wire tlp_reqMetaInFlight_EN;
// register tlp_sentTail4DWHeader
reg tlp_sentTail4DWHeader;
wire tlp_sentTail4DWHeader_D_IN, tlp_sentTail4DWHeader_EN;
// register tlp_srcMesgAccu
reg [31 : 0] tlp_srcMesgAccu;
wire [31 : 0] tlp_srcMesgAccu_D_IN;
wire tlp_srcMesgAccu_EN;
// register tlp_tlpBRAM_debugBdata
reg [127 : 0] tlp_tlpBRAM_debugBdata;
wire [127 : 0] tlp_tlpBRAM_debugBdata_D_IN;
wire tlp_tlpBRAM_debugBdata_EN;
// register tlp_tlpBRAM_rdRespDwRemain
reg [9 : 0] tlp_tlpBRAM_rdRespDwRemain;
wire [9 : 0] tlp_tlpBRAM_rdRespDwRemain_D_IN;
wire tlp_tlpBRAM_rdRespDwRemain_EN;
// register tlp_tlpBRAM_readHeaderSent
reg tlp_tlpBRAM_readHeaderSent;
wire tlp_tlpBRAM_readHeaderSent_D_IN, tlp_tlpBRAM_readHeaderSent_EN;
// register tlp_tlpBRAM_readNxtDWAddr
reg [12 : 0] tlp_tlpBRAM_readNxtDWAddr;
wire [12 : 0] tlp_tlpBRAM_readNxtDWAddr_D_IN;
wire tlp_tlpBRAM_readNxtDWAddr_EN;
// register tlp_tlpBRAM_readRemainDWLen
reg [9 : 0] tlp_tlpBRAM_readRemainDWLen;
wire [9 : 0] tlp_tlpBRAM_readRemainDWLen_D_IN;
wire tlp_tlpBRAM_readRemainDWLen_EN;
// register tlp_tlpBRAM_readStarted
reg tlp_tlpBRAM_readStarted;
wire tlp_tlpBRAM_readStarted_D_IN, tlp_tlpBRAM_readStarted_EN;
// register tlp_tlpBRAM_writeDWAddr
reg [12 : 0] tlp_tlpBRAM_writeDWAddr;
wire [12 : 0] tlp_tlpBRAM_writeDWAddr_D_IN;
wire tlp_tlpBRAM_writeDWAddr_EN;
// register tlp_tlpBRAM_writeLastBE
reg [3 : 0] tlp_tlpBRAM_writeLastBE;
wire [3 : 0] tlp_tlpBRAM_writeLastBE_D_IN;
wire tlp_tlpBRAM_writeLastBE_EN;
// register tlp_tlpBRAM_writeRemainDWLen
reg [9 : 0] tlp_tlpBRAM_writeRemainDWLen;
wire [9 : 0] tlp_tlpBRAM_writeRemainDWLen_D_IN;
wire tlp_tlpBRAM_writeRemainDWLen_EN;
// register tlp_tlpMetaSent
reg tlp_tlpMetaSent;
wire tlp_tlpMetaSent_D_IN, tlp_tlpMetaSent_EN;
// register tlp_tlpRcvBusy
reg tlp_tlpRcvBusy;
reg tlp_tlpRcvBusy_D_IN;
wire tlp_tlpRcvBusy_EN;
// register tlp_tlpXmtBusy
reg tlp_tlpXmtBusy;
reg tlp_tlpXmtBusy_D_IN;
wire tlp_tlpXmtBusy_EN;
// register tlp_xmtMetaInFlight
reg tlp_xmtMetaInFlight;
wire tlp_xmtMetaInFlight_D_IN, tlp_xmtMetaInFlight_EN;
// register tlp_xmtMetaOK
reg tlp_xmtMetaOK;
reg tlp_xmtMetaOK_D_IN;
wire tlp_xmtMetaOK_EN;
// register wci_cEdge
reg [2 : 0] wci_cEdge;
wire [2 : 0] wci_cEdge_D_IN;
wire wci_cEdge_EN;
// register wci_cState
reg [2 : 0] wci_cState;
wire [2 : 0] wci_cState_D_IN;
wire wci_cState_EN;
// register wci_ctlAckReg
reg wci_ctlAckReg;
wire wci_ctlAckReg_D_IN, wci_ctlAckReg_EN;
// register wci_ctlOpActive
reg wci_ctlOpActive;
wire wci_ctlOpActive_D_IN, wci_ctlOpActive_EN;
// register wci_illegalEdge
reg wci_illegalEdge;
wire wci_illegalEdge_D_IN, wci_illegalEdge_EN;
// register wci_isReset_isInReset
reg wci_isReset_isInReset;
wire wci_isReset_isInReset_D_IN, wci_isReset_isInReset_EN;
// register wci_nState
reg [2 : 0] wci_nState;
reg [2 : 0] wci_nState_D_IN;
wire wci_nState_EN;
// register wci_reqF_countReg
reg [1 : 0] wci_reqF_countReg;
wire [1 : 0] wci_reqF_countReg_D_IN;
wire wci_reqF_countReg_EN;
// register wci_respF_cntr_r
reg [1 : 0] wci_respF_cntr_r;
wire [1 : 0] wci_respF_cntr_r_D_IN;
wire wci_respF_cntr_r_EN;
// register wci_respF_q_0
reg [33 : 0] wci_respF_q_0;
reg [33 : 0] wci_respF_q_0_D_IN;
wire wci_respF_q_0_EN;
// register wci_respF_q_1
reg [33 : 0] wci_respF_q_1;
reg [33 : 0] wci_respF_q_1_D_IN;
wire wci_respF_q_1_EN;
// register wci_sFlagReg
reg wci_sFlagReg;
wire wci_sFlagReg_D_IN, wci_sFlagReg_EN;
// register wci_sThreadBusy_d
reg wci_sThreadBusy_d;
wire wci_sThreadBusy_d_D_IN, wci_sThreadBusy_d_EN;
// register wmi_addr
reg [13 : 0] wmi_addr;
wire [13 : 0] wmi_addr_D_IN;
wire wmi_addr_EN;
// register wmi_bufDwell
reg [1 : 0] wmi_bufDwell;
wire [1 : 0] wmi_bufDwell_D_IN;
wire wmi_bufDwell_EN;
// register wmi_bytesRemainReq
reg [13 : 0] wmi_bytesRemainReq;
wire [13 : 0] wmi_bytesRemainReq_D_IN;
wire wmi_bytesRemainReq_EN;
// register wmi_bytesRemainResp
reg [13 : 0] wmi_bytesRemainResp;
wire [13 : 0] wmi_bytesRemainResp_D_IN;
wire wmi_bytesRemainResp_EN;
// register wmi_doneWithMesg
reg wmi_doneWithMesg;
wire wmi_doneWithMesg_D_IN, wmi_doneWithMesg_EN;
// register wmi_lastMesg
reg [31 : 0] wmi_lastMesg;
wire [31 : 0] wmi_lastMesg_D_IN;
wire wmi_lastMesg_EN;
// register wmi_lclMesgAddr
reg [14 : 0] wmi_lclMesgAddr;
wire [14 : 0] wmi_lclMesgAddr_D_IN;
wire wmi_lclMesgAddr_EN;
// register wmi_lclMetaAddr
reg [14 : 0] wmi_lclMetaAddr;
wire [14 : 0] wmi_lclMetaAddr_D_IN;
wire wmi_lclMetaAddr_EN;
// register wmi_mesgBufReady
reg wmi_mesgBufReady;
wire wmi_mesgBufReady_D_IN, wmi_mesgBufReady_EN;
// register wmi_mesgBusy
reg wmi_mesgBusy;
wire wmi_mesgBusy_D_IN, wmi_mesgBusy_EN;
// register wmi_mesgCount
reg [31 : 0] wmi_mesgCount;
wire [31 : 0] wmi_mesgCount_D_IN;
wire wmi_mesgCount_EN;
// register wmi_mesgDone
reg wmi_mesgDone;
wire wmi_mesgDone_D_IN, wmi_mesgDone_EN;
// register wmi_mesgMeta
reg [128 : 0] wmi_mesgMeta;
wire [128 : 0] wmi_mesgMeta_D_IN;
wire wmi_mesgMeta_EN;
// register wmi_mesgStart
reg wmi_mesgStart;
wire wmi_mesgStart_D_IN, wmi_mesgStart_EN;
// register wmi_metaBusy
reg wmi_metaBusy;
wire wmi_metaBusy_D_IN, wmi_metaBusy_EN;
// register wmi_p4B
reg [1 : 0] wmi_p4B;
wire [1 : 0] wmi_p4B_D_IN;
wire wmi_p4B_EN;
// register wmi_rdActive
reg wmi_rdActive;
wire wmi_rdActive_D_IN, wmi_rdActive_EN;
// register wmi_reqCount
reg [15 : 0] wmi_reqCount;
wire [15 : 0] wmi_reqCount_D_IN;
wire wmi_reqCount_EN;
// register wmi_thisMesg
reg [31 : 0] wmi_thisMesg;
wire [31 : 0] wmi_thisMesg_D_IN;
wire wmi_thisMesg_EN;
// register wmi_wmi_blockReq
reg wmi_wmi_blockReq;
wire wmi_wmi_blockReq_D_IN, wmi_wmi_blockReq_EN;
// register wmi_wmi_dhF_countReg
reg [1 : 0] wmi_wmi_dhF_countReg;
wire [1 : 0] wmi_wmi_dhF_countReg_D_IN;
wire wmi_wmi_dhF_countReg_EN;
// register wmi_wmi_dhF_levelsValid
reg wmi_wmi_dhF_levelsValid;
wire wmi_wmi_dhF_levelsValid_D_IN, wmi_wmi_dhF_levelsValid_EN;
// register wmi_wmi_errorSticky
reg wmi_wmi_errorSticky;
wire wmi_wmi_errorSticky_D_IN, wmi_wmi_errorSticky_EN;
// register wmi_wmi_isReset_isInReset
reg wmi_wmi_isReset_isInReset;
wire wmi_wmi_isReset_isInReset_D_IN, wmi_wmi_isReset_isInReset_EN;
// register wmi_wmi_mFlagF_countReg
reg [1 : 0] wmi_wmi_mFlagF_countReg;
wire [1 : 0] wmi_wmi_mFlagF_countReg_D_IN;
wire wmi_wmi_mFlagF_countReg_EN;
// register wmi_wmi_mFlagF_levelsValid
reg wmi_wmi_mFlagF_levelsValid;
wire wmi_wmi_mFlagF_levelsValid_D_IN, wmi_wmi_mFlagF_levelsValid_EN;
// register wmi_wmi_operateD
reg wmi_wmi_operateD;
wire wmi_wmi_operateD_D_IN, wmi_wmi_operateD_EN;
// register wmi_wmi_peerIsReady
reg wmi_wmi_peerIsReady;
wire wmi_wmi_peerIsReady_D_IN, wmi_wmi_peerIsReady_EN;
// register wmi_wmi_reqF_countReg
reg [1 : 0] wmi_wmi_reqF_countReg;
wire [1 : 0] wmi_wmi_reqF_countReg_D_IN;
wire wmi_wmi_reqF_countReg_EN;
// register wmi_wmi_reqF_levelsValid
reg wmi_wmi_reqF_levelsValid;
wire wmi_wmi_reqF_levelsValid_D_IN, wmi_wmi_reqF_levelsValid_EN;
// register wmi_wmi_respF_cntr_r
reg [1 : 0] wmi_wmi_respF_cntr_r;
wire [1 : 0] wmi_wmi_respF_cntr_r_D_IN;
wire wmi_wmi_respF_cntr_r_EN;
// register wmi_wmi_respF_q_0
reg [129 : 0] wmi_wmi_respF_q_0;
reg [129 : 0] wmi_wmi_respF_q_0_D_IN;
wire wmi_wmi_respF_q_0_EN;
// register wmi_wmi_respF_q_1
reg [129 : 0] wmi_wmi_respF_q_1;
reg [129 : 0] wmi_wmi_respF_q_1_D_IN;
wire wmi_wmi_respF_q_1_EN;
// register wmi_wmi_sFlagReg
reg [31 : 0] wmi_wmi_sFlagReg;
wire [31 : 0] wmi_wmi_sFlagReg_D_IN;
wire wmi_wmi_sFlagReg_EN;
// register wmi_wmi_statusR
reg [7 : 0] wmi_wmi_statusR;
wire [7 : 0] wmi_wmi_statusR_D_IN;
wire wmi_wmi_statusR_EN;
// register wmi_wmi_trafficSticky
reg wmi_wmi_trafficSticky;
wire wmi_wmi_trafficSticky_D_IN, wmi_wmi_trafficSticky_EN;
// register wmi_wrActive
reg wmi_wrActive;
wire wmi_wrActive_D_IN, wmi_wrActive_EN;
// register wmi_wrFinalize
reg wmi_wrFinalize;
wire wmi_wrFinalize_D_IN, wmi_wrFinalize_EN;
// register wmi_wrtCount
reg [15 : 0] wmi_wrtCount;
wire [15 : 0] wmi_wrtCount_D_IN;
wire wmi_wrtCount_EN;
// register wti_isReset_isInReset
reg wti_isReset_isInReset;
wire wti_isReset_isInReset_D_IN, wti_isReset_isInReset_EN;
// register wti_nowReq
reg [66 : 0] wti_nowReq;
wire [66 : 0] wti_nowReq_D_IN;
wire wti_nowReq_EN;
// register wti_operateD
reg wti_operateD;
wire wti_operateD_D_IN, wti_operateD_EN;
// ports of submodule bram_0_memory
reg [31 : 0] bram_0_memory_DIA, bram_0_memory_DIB;
reg [10 : 0] bram_0_memory_ADDRA, bram_0_memory_ADDRB;
wire [31 : 0] bram_0_memory_DOA, bram_0_memory_DOB;
wire bram_0_memory_ENA,
bram_0_memory_ENB,
bram_0_memory_WEA,
bram_0_memory_WEB;
// ports of submodule bram_0_serverAdapterA_outDataCore
wire [31 : 0] bram_0_serverAdapterA_outDataCore_D_IN,
bram_0_serverAdapterA_outDataCore_D_OUT;
wire bram_0_serverAdapterA_outDataCore_CLR,
bram_0_serverAdapterA_outDataCore_DEQ,
bram_0_serverAdapterA_outDataCore_EMPTY_N,
bram_0_serverAdapterA_outDataCore_ENQ,
bram_0_serverAdapterA_outDataCore_FULL_N;
// ports of submodule bram_0_serverAdapterB_outDataCore
wire [31 : 0] bram_0_serverAdapterB_outDataCore_D_IN,
bram_0_serverAdapterB_outDataCore_D_OUT;
wire bram_0_serverAdapterB_outDataCore_CLR,
bram_0_serverAdapterB_outDataCore_DEQ,
bram_0_serverAdapterB_outDataCore_EMPTY_N,
bram_0_serverAdapterB_outDataCore_ENQ,
bram_0_serverAdapterB_outDataCore_FULL_N;
// ports of submodule bram_1_memory
reg [31 : 0] bram_1_memory_DIA, bram_1_memory_DIB;
reg [10 : 0] bram_1_memory_ADDRA, bram_1_memory_ADDRB;
wire [31 : 0] bram_1_memory_DOA, bram_1_memory_DOB;
wire bram_1_memory_ENA,
bram_1_memory_ENB,
bram_1_memory_WEA,
bram_1_memory_WEB;
// ports of submodule bram_1_serverAdapterA_outDataCore
wire [31 : 0] bram_1_serverAdapterA_outDataCore_D_IN,
bram_1_serverAdapterA_outDataCore_D_OUT;
wire bram_1_serverAdapterA_outDataCore_CLR,
bram_1_serverAdapterA_outDataCore_DEQ,
bram_1_serverAdapterA_outDataCore_EMPTY_N,
bram_1_serverAdapterA_outDataCore_ENQ,
bram_1_serverAdapterA_outDataCore_FULL_N;
// ports of submodule bram_1_serverAdapterB_outDataCore
wire [31 : 0] bram_1_serverAdapterB_outDataCore_D_IN,
bram_1_serverAdapterB_outDataCore_D_OUT;
wire bram_1_serverAdapterB_outDataCore_CLR,
bram_1_serverAdapterB_outDataCore_DEQ,
bram_1_serverAdapterB_outDataCore_EMPTY_N,
bram_1_serverAdapterB_outDataCore_ENQ,
bram_1_serverAdapterB_outDataCore_FULL_N;
// ports of submodule bram_2_memory
reg [31 : 0] bram_2_memory_DIA, bram_2_memory_DIB;
reg [10 : 0] bram_2_memory_ADDRA, bram_2_memory_ADDRB;
wire [31 : 0] bram_2_memory_DOA, bram_2_memory_DOB;
wire bram_2_memory_ENA,
bram_2_memory_ENB,
bram_2_memory_WEA,
bram_2_memory_WEB;
// ports of submodule bram_2_serverAdapterA_outDataCore
wire [31 : 0] bram_2_serverAdapterA_outDataCore_D_IN,
bram_2_serverAdapterA_outDataCore_D_OUT;
wire bram_2_serverAdapterA_outDataCore_CLR,
bram_2_serverAdapterA_outDataCore_DEQ,
bram_2_serverAdapterA_outDataCore_EMPTY_N,
bram_2_serverAdapterA_outDataCore_ENQ,
bram_2_serverAdapterA_outDataCore_FULL_N;
// ports of submodule bram_2_serverAdapterB_outDataCore
wire [31 : 0] bram_2_serverAdapterB_outDataCore_D_IN,
bram_2_serverAdapterB_outDataCore_D_OUT;
wire bram_2_serverAdapterB_outDataCore_CLR,
bram_2_serverAdapterB_outDataCore_DEQ,
bram_2_serverAdapterB_outDataCore_EMPTY_N,
bram_2_serverAdapterB_outDataCore_ENQ,
bram_2_serverAdapterB_outDataCore_FULL_N;
// ports of submodule bram_3_memory
reg [31 : 0] bram_3_memory_DIA, bram_3_memory_DIB;
reg [10 : 0] bram_3_memory_ADDRA, bram_3_memory_ADDRB;
wire [31 : 0] bram_3_memory_DOA, bram_3_memory_DOB;
wire bram_3_memory_ENA,
bram_3_memory_ENB,
bram_3_memory_WEA,
bram_3_memory_WEB;
// ports of submodule bram_3_serverAdapterA_outDataCore
wire [31 : 0] bram_3_serverAdapterA_outDataCore_D_IN,
bram_3_serverAdapterA_outDataCore_D_OUT;
wire bram_3_serverAdapterA_outDataCore_CLR,
bram_3_serverAdapterA_outDataCore_DEQ,
bram_3_serverAdapterA_outDataCore_EMPTY_N,
bram_3_serverAdapterA_outDataCore_ENQ,
bram_3_serverAdapterA_outDataCore_FULL_N;
// ports of submodule bram_3_serverAdapterB_outDataCore
wire [31 : 0] bram_3_serverAdapterB_outDataCore_D_IN,
bram_3_serverAdapterB_outDataCore_D_OUT;
wire bram_3_serverAdapterB_outDataCore_CLR,
bram_3_serverAdapterB_outDataCore_DEQ,
bram_3_serverAdapterB_outDataCore_EMPTY_N,
bram_3_serverAdapterB_outDataCore_ENQ,
bram_3_serverAdapterB_outDataCore_FULL_N;
// ports of submodule tlp_inF
wire [152 : 0] tlp_inF_D_IN, tlp_inF_D_OUT;
wire tlp_inF_CLR, tlp_inF_DEQ, tlp_inF_EMPTY_N, tlp_inF_ENQ, tlp_inF_FULL_N;
// ports of submodule tlp_outF
reg [152 : 0] tlp_outF_D_IN;
wire [152 : 0] tlp_outF_D_OUT;
wire tlp_outF_CLR,
tlp_outF_DEQ,
tlp_outF_EMPTY_N,
tlp_outF_ENQ,
tlp_outF_FULL_N;
// ports of submodule tlp_tailEventF
wire tlp_tailEventF_CLR,
tlp_tailEventF_DEQ,
tlp_tailEventF_D_IN,
tlp_tailEventF_D_OUT,
tlp_tailEventF_EMPTY_N,
tlp_tailEventF_ENQ,
tlp_tailEventF_FULL_N;
// ports of submodule tlp_tlpBRAM_mReqF
reg [129 : 0] tlp_tlpBRAM_mReqF_D_IN;
wire [129 : 0] tlp_tlpBRAM_mReqF_D_OUT;
wire tlp_tlpBRAM_mReqF_CLR,
tlp_tlpBRAM_mReqF_DEQ,
tlp_tlpBRAM_mReqF_EMPTY_N,
tlp_tlpBRAM_mReqF_ENQ,
tlp_tlpBRAM_mReqF_FULL_N;
// ports of submodule tlp_tlpBRAM_mRespF
wire [138 : 0] tlp_tlpBRAM_mRespF_D_IN, tlp_tlpBRAM_mRespF_D_OUT;
wire tlp_tlpBRAM_mRespF_CLR,
tlp_tlpBRAM_mRespF_DEQ,
tlp_tlpBRAM_mRespF_EMPTY_N,
tlp_tlpBRAM_mRespF_ENQ,
tlp_tlpBRAM_mRespF_FULL_N;
// ports of submodule tlp_tlpBRAM_readReq
wire [60 : 0] tlp_tlpBRAM_readReq_D_IN, tlp_tlpBRAM_readReq_D_OUT;
wire tlp_tlpBRAM_readReq_CLR,
tlp_tlpBRAM_readReq_DEQ,
tlp_tlpBRAM_readReq_EMPTY_N,
tlp_tlpBRAM_readReq_ENQ,
tlp_tlpBRAM_readReq_FULL_N;
// ports of submodule wci_reqF
wire [71 : 0] wci_reqF_D_IN, wci_reqF_D_OUT;
wire wci_reqF_CLR, wci_reqF_DEQ, wci_reqF_EMPTY_N, wci_reqF_ENQ;
// ports of submodule wmi_wmi_dhF
wire [145 : 0] wmi_wmi_dhF_D_IN, wmi_wmi_dhF_D_OUT;
wire wmi_wmi_dhF_CLR,
wmi_wmi_dhF_DEQ,
wmi_wmi_dhF_EMPTY_N,
wmi_wmi_dhF_ENQ,
wmi_wmi_dhF_FULL_N;
// ports of submodule wmi_wmi_mFlagF
wire [31 : 0] wmi_wmi_mFlagF_D_IN, wmi_wmi_mFlagF_D_OUT;
wire wmi_wmi_mFlagF_CLR,
wmi_wmi_mFlagF_DEQ,
wmi_wmi_mFlagF_EMPTY_N,
wmi_wmi_mFlagF_ENQ,
wmi_wmi_mFlagF_FULL_N;
// ports of submodule wmi_wmi_reqF
wire [31 : 0] wmi_wmi_reqF_D_IN, wmi_wmi_reqF_D_OUT;
wire wmi_wmi_reqF_CLR,
wmi_wmi_reqF_DEQ,
wmi_wmi_reqF_EMPTY_N,
wmi_wmi_reqF_ENQ,
wmi_wmi_reqF_FULL_N;
// rule scheduling signals
wire CAN_FIRE_RL_bml_remAdvance,
CAN_FIRE_RL_tlp_dmaRespBodyFarMeta,
CAN_FIRE_RL_tlp_dmaTailEventSender,
CAN_FIRE_RL_tlp_dmaXmtMetaBody,
CAN_FIRE_RL_tlp_tlpRcv,
CAN_FIRE_RL_wmi_doWriteReq,
CAN_FIRE_RL_wmi_getRequest,
CAN_FIRE_RL_wmi_reqMetadata,
CAN_FIRE_RL_wmi_respMetadata,
WILL_FIRE_RL_bml_crdAdvance,
WILL_FIRE_RL_bml_fba,
WILL_FIRE_RL_bml_initAccumulators,
WILL_FIRE_RL_bml_lclAdvance,
WILL_FIRE_RL_bml_lcredit,
WILL_FIRE_RL_bml_remAdvance,
WILL_FIRE_RL_bram_0_serverAdapterA_outData_enqAndDeq,
WILL_FIRE_RL_bram_0_serverAdapterB_outData_enqAndDeq,
WILL_FIRE_RL_bram_1_serverAdapterA_outData_enqAndDeq,
WILL_FIRE_RL_bram_1_serverAdapterB_outData_enqAndDeq,
WILL_FIRE_RL_bram_2_serverAdapterA_outData_enqAndDeq,
WILL_FIRE_RL_bram_2_serverAdapterA_outData_setFirstEnq,
WILL_FIRE_RL_bram_2_serverAdapterB_outData_enqAndDeq,
WILL_FIRE_RL_bram_3_serverAdapterA_outData_enqAndDeq,
WILL_FIRE_RL_bram_3_serverAdapterB_outData_enqAndDeq,
WILL_FIRE_RL_tlp_dataXmt_Body,
WILL_FIRE_RL_tlp_dataXmt_Header,
WILL_FIRE_RL_tlp_dmaPullRequestFarMesg,
WILL_FIRE_RL_tlp_dmaPullResponseBody,
WILL_FIRE_RL_tlp_dmaPullResponseHeader,
WILL_FIRE_RL_tlp_dmaPullTailEvent,
WILL_FIRE_RL_tlp_dmaPushRequestMesg,
WILL_FIRE_RL_tlp_dmaPushResponseBody,
WILL_FIRE_RL_tlp_dmaPushResponseHeader,
WILL_FIRE_RL_tlp_dmaRequestFarMeta,
WILL_FIRE_RL_tlp_dmaRequestNearMeta,
WILL_FIRE_RL_tlp_dmaRespBodyFarMeta,
WILL_FIRE_RL_tlp_dmaRespHeadFarMeta,
WILL_FIRE_RL_tlp_dmaResponseNearMetaBody,
WILL_FIRE_RL_tlp_dmaResponseNearMetaHead,
WILL_FIRE_RL_tlp_dmaTailEventSender,
WILL_FIRE_RL_tlp_dmaXmtDoorbell,
WILL_FIRE_RL_tlp_dmaXmtMetaBody,
WILL_FIRE_RL_tlp_dmaXmtMetaHead,
WILL_FIRE_RL_tlp_dmaXmtTailEvent,
WILL_FIRE_RL_tlp_tlpBRAM_read_FirstReq,
WILL_FIRE_RL_tlp_tlpBRAM_read_FirstResp,
WILL_FIRE_RL_tlp_tlpBRAM_read_NextReq,
WILL_FIRE_RL_tlp_tlpBRAM_read_NextResp,
WILL_FIRE_RL_tlp_tlpBRAM_writeData,
WILL_FIRE_RL_tlp_tlpBRAM_writeReq,
WILL_FIRE_RL_tlp_tlpRcv,
WILL_FIRE_RL_wci_cfrd,
WILL_FIRE_RL_wci_cfwr,
WILL_FIRE_RL_wci_ctl_op_complete,
WILL_FIRE_RL_wci_ctl_op_start,
WILL_FIRE_RL_wci_respF_both,
WILL_FIRE_RL_wci_respF_decCtr,
WILL_FIRE_RL_wci_respF_incCtr,
WILL_FIRE_RL_wmi_doReadReq,
WILL_FIRE_RL_wmi_doReadResp,
WILL_FIRE_RL_wmi_doWriteFinalize,
WILL_FIRE_RL_wmi_doWriteReq,
WILL_FIRE_RL_wmi_getRequest,
WILL_FIRE_RL_wmi_reqMetadata,
WILL_FIRE_RL_wmi_respMetadata,
WILL_FIRE_RL_wmi_wmi_dhF_reset,
WILL_FIRE_RL_wmi_wmi_mFlagF_reset,
WILL_FIRE_RL_wmi_wmi_reqF_reset,
WILL_FIRE_RL_wmi_wmi_respF_both,
WILL_FIRE_RL_wmi_wmi_respF_decCtr,
WILL_FIRE_RL_wmi_wmi_respF_incCtr;
// inputs to muxes for submodule ports
reg [33 : 0] MUX_wci_respF_q_0_write_1__VAL_2;
reg [10 : 0] MUX_bram_0_memory_a_put_2__VAL_1,
MUX_bram_0_memory_a_put_2__VAL_4,
MUX_bram_1_memory_a_put_2__VAL_1,
MUX_bram_1_memory_a_put_2__VAL_4,
MUX_bram_2_memory_a_put_2__VAL_1,
MUX_bram_2_memory_a_put_2__VAL_4,
MUX_bram_3_memory_a_put_2__VAL_1,
MUX_bram_3_memory_a_put_2__VAL_4;
wire [152 : 0] MUX_tlp_outF_enq_1__VAL_1,
MUX_tlp_outF_enq_1__VAL_2,
MUX_tlp_outF_enq_1__VAL_3,
MUX_tlp_outF_enq_1__VAL_4,
MUX_tlp_outF_enq_1__VAL_5,
MUX_tlp_outF_enq_1__VAL_6,
MUX_tlp_outF_enq_1__VAL_7,
MUX_tlp_outF_enq_1__VAL_8;
wire [138 : 0] MUX_tlp_tlpBRAM_mRespF_enq_1__VAL_1,
MUX_tlp_tlpBRAM_mRespF_enq_1__VAL_2;
wire [129 : 0] MUX_tlp_tlpBRAM_mReqF_enq_1__VAL_1,
MUX_tlp_tlpBRAM_mReqF_enq_1__VAL_2,
MUX_tlp_tlpBRAM_mReqF_enq_1__VAL_3,
MUX_tlp_tlpBRAM_mReqF_enq_1__VAL_4,
MUX_tlp_tlpBRAM_mReqF_enq_1__VAL_5,
MUX_tlp_tlpBRAM_mReqF_enq_1__VAL_6,
MUX_wmi_wmi_respF_q_0_write_1__VAL_1,
MUX_wmi_wmi_respF_q_0_write_1__VAL_2,
MUX_wmi_wmi_respF_q_1_write_1__VAL_1;
wire [128 : 0] MUX_tlp_fabMeta_write_1__VAL_1,
MUX_tlp_fabMeta_write_1__VAL_3,
MUX_wmi_mesgMeta_write_1__VAL_2;
wire [33 : 0] MUX_wci_respF_q_0_write_1__VAL_1,
MUX_wci_respF_q_1_write_1__VAL_1,
MUX_wci_respF_x_wire_wset_1__VAL_1,
MUX_wci_respF_x_wire_wset_1__VAL_2;
wire [31 : 0] MUX_bml_fabFlowAddr_write_1__VAL_1,
MUX_bml_fabFlowAddr_write_1__VAL_3,
MUX_bml_fabMesgAddr_write_1__VAL_1,
MUX_bml_fabMetaAddr_write_1__VAL_1,
MUX_bram_0_memory_a_put_3__VAL_1,
MUX_bram_0_memory_a_put_3__VAL_2,
MUX_bram_1_memory_a_put_3__VAL_1,
MUX_bram_2_memory_a_put_3__VAL_1,
MUX_bram_3_memory_a_put_3__VAL_1,
MUX_tlp_fabMesgAccu_write_1__VAL_2,
MUX_tlp_fabMesgAccu_write_1__VAL_3,
MUX_tlp_srcMesgAccu_write_1__VAL_2,
MUX_wmi_mesgCount_write_1__VAL_1;
wire [16 : 0] MUX_tlp_mesgComplReceived_write_1__VAL_1,
MUX_tlp_mesgComplReceived_write_1__VAL_2,
MUX_tlp_mesgLengthRemainPull_write_1__VAL_1,
MUX_tlp_mesgLengthRemainPull_write_1__VAL_2,
MUX_tlp_mesgLengthRemainPull_write_1__VAL_3,
MUX_tlp_mesgLengthRemainPush_write_1__VAL_1,
MUX_tlp_mesgLengthRemainPush_write_1__VAL_2,
MUX_tlp_mesgLengthRemainPush_write_1__VAL_3;
wire [15 : 0] MUX_bml_crdBuf_value_write_1__VAL_3,
MUX_bml_fabBuf_value_write_1__VAL_3,
MUX_bml_fabBufsAvail_write_1__VAL_1,
MUX_bml_fabBufsAvail_write_1__VAL_2,
MUX_bml_lclBuf_value_write_1__VAL_3,
MUX_bml_lclBufsAR_write_1__VAL_1,
MUX_bml_lclBufsAR_write_1__VAL_2,
MUX_bml_lclBufsCF_write_1__VAL_1,
MUX_bml_lclBufsCF_write_1__VAL_2,
MUX_bml_lclCredit_write_1__VAL_1,
MUX_bml_lclMesgAddr_write_1__VAL_2,
MUX_bml_lclMetaAddr_write_1__VAL_2,
MUX_bml_remBuf_value_write_1__VAL_3,
MUX_bml_remMesgAddr_write_1__VAL_2,
MUX_bml_remMetaAddr_write_1__VAL_2,
MUX_tlp_remMesgAccu_write_1__VAL_2,
MUX_tlp_remMesgAccu_write_1__VAL_3;
wire [13 : 0] MUX_wmi_addr_write_1__VAL_1,
MUX_wmi_bytesRemainReq_write_1__VAL_1,
MUX_wmi_bytesRemainReq_write_1__VAL_2,
MUX_wmi_bytesRemainResp_write_1__VAL_2;
wire [12 : 0] MUX_tlp_tlpBRAM_readNxtDWAddr_write_1__VAL_1,
MUX_tlp_tlpBRAM_readNxtDWAddr_write_1__VAL_2,
MUX_tlp_tlpBRAM_writeDWAddr_write_1__VAL_1,
MUX_tlp_tlpBRAM_writeDWAddr_write_1__VAL_2;
wire [10 : 0] MUX_bram_0_memory_b_put_2__VAL_2;
wire [9 : 0] MUX_tlp_dmaPullRemainDWLen_write_1__VAL_2,
MUX_tlp_dmaPullRemainDWLen_write_1__VAL_3,
MUX_tlp_dmaPullRemainDWSub_write_1__VAL_1,
MUX_tlp_dmaPullRemainDWSub_write_1__VAL_2,
MUX_tlp_outDwRemain_write_1__VAL_1,
MUX_tlp_outDwRemain_write_1__VAL_2,
MUX_tlp_outDwRemain_write_1__VAL_3,
MUX_tlp_tlpBRAM_rdRespDwRemain_write_1__VAL_1,
MUX_tlp_tlpBRAM_rdRespDwRemain_write_1__VAL_2,
MUX_tlp_tlpBRAM_readRemainDWLen_write_1__VAL_1,
MUX_tlp_tlpBRAM_readRemainDWLen_write_1__VAL_2,
MUX_tlp_tlpBRAM_writeRemainDWLen_write_1__VAL_1,
MUX_tlp_tlpBRAM_writeRemainDWLen_write_1__VAL_2;
wire [3 : 0] MUX_tlp_doorSeqDwell_write_1__VAL_1,
MUX_tlp_lastRuleFired_write_1__VAL_3,
MUX_tlp_postSeqDwell_write_1__VAL_1,
MUX_tlp_postSeqDwell_write_1__VAL_2;
wire [1 : 0] MUX_wci_respF_cntr_r_write_1__VAL_2,
MUX_wmi_bufDwell_write_1__VAL_3,
MUX_wmi_wmi_respF_cntr_r_write_1__VAL_2;
wire MUX_bml_fabBufsAvail_write_1__SEL_1,
MUX_bml_fabFlowAddr_write_1__SEL_1,
MUX_bml_lclBufsAR_write_1__SEL_1,
MUX_bml_lclBufsCF_write_1__SEL_1,
MUX_bml_lclCredit_write_1__SEL_1,
MUX_bram_0_memory_a_put_1__SEL_1,
MUX_bram_0_memory_a_put_1__SEL_2,
MUX_bram_0_memory_a_put_1__SEL_3,
MUX_bram_0_serverAdapterB_writeWithResp_wset_1__SEL_1,
MUX_bram_1_memory_a_put_1__SEL_1,
MUX_bram_1_memory_a_put_1__SEL_2,
MUX_bram_1_memory_a_put_1__SEL_3,
MUX_bram_2_memory_a_put_1__SEL_1,
MUX_bram_2_memory_a_put_1__SEL_2,
MUX_bram_2_memory_a_put_1__SEL_3,
MUX_bram_3_memory_a_put_1__SEL_1,
MUX_bram_3_memory_a_put_1__SEL_2,
MUX_bram_3_memory_a_put_1__SEL_3,
MUX_tlp_dmaDoTailEvent_write_1__VAL_1,
MUX_tlp_fabMesgAccu_write_1__SEL_1,
MUX_tlp_fabMeta_write_1__SEL_2,
MUX_tlp_remDone_1_wset_1__SEL_1,
MUX_tlp_reqMesgInFlight_write_1__VAL_2,
MUX_tlp_tailEventF_enq_1__SEL_1,
MUX_tlp_tlpBRAM_mReqF_enq_1__SEL_1,
MUX_tlp_tlpBRAM_mReqF_enq_1__SEL_2,
MUX_tlp_tlpBRAM_readHeaderSent_write_1__SEL_1,
MUX_tlp_tlpBRAM_readStarted_write_1__SEL_1,
MUX_tlp_tlpXmtBusy_write_1__PSEL_2,
MUX_tlp_tlpXmtBusy_write_1__SEL_1,
MUX_tlp_tlpXmtBusy_write_1__SEL_2,
MUX_tlp_tlpXmtBusy_write_1__SEL_3,
MUX_tlp_tlpXmtBusy_write_1__SEL_4,
MUX_tlp_tlpXmtBusy_write_1__VAL_1,
MUX_tlp_xmtMetaOK_write_1__SEL_3,
MUX_tlp_xmtMetaOK_write_1__SEL_4,
MUX_wci_illegalEdge_write_1__SEL_1,
MUX_wci_illegalEdge_write_1__SEL_2,
MUX_wci_illegalEdge_write_1__VAL_2,
MUX_wci_respF_q_0_write_1__SEL_1,
MUX_wci_respF_q_0_write_1__SEL_2,
MUX_wci_respF_q_1_write_1__SEL_1,
MUX_wci_respF_q_1_write_1__SEL_2,
MUX_wmi_bufDwell_write_1__SEL_1,
MUX_wmi_bytesRemainResp_write_1__SEL_1,
MUX_wmi_doneWithMesg_write_1__PSEL_1,
MUX_wmi_doneWithMesg_write_1__SEL_1,
MUX_wmi_rdActive_write_1__SEL_1,
MUX_wmi_wmi_dhF_levelsValid_write_1__SEL_2,
MUX_wmi_wmi_mFlagF_levelsValid_write_1__SEL_2,
MUX_wmi_wmi_reqF_levelsValid_write_1__SEL_2,
MUX_wmi_wmi_respF_q_0_write_1__SEL_1,
MUX_wmi_wmi_respF_q_0_write_1__SEL_2,
MUX_wmi_wmi_respF_q_1_write_1__SEL_1,
MUX_wmi_wmi_respF_q_1_write_1__SEL_2,
MUX_wmi_wrActive_write_1__SEL_1,
MUX_wmi_wrFinalize_write_1__SEL_1;
// remaining internal signals
reg [63 : 0] v__h15577,
v__h15752,
v__h15896,
v__h41005,
v__h43090,
v__h47450,
v__h47790,
v__h48409,
v__h48757,
v__h50007,
v__h56382,
v__h56506,
v__h56714,
v__h57177,
v__h59442,
v__h63835,
v__h64356,
v__h65011,
v__h65359,
v__h65522,
v__h70765,
v__h82455,
v__h91331,
v__h91800,
v__h91963;
reg [31 : 0] SEL_ARR_bram_0_serverAdapterA_outData_outData__ETC___d863,
SEL_ARR_tlp_tlpBRAM_mReqF_first__16_BITS_127_T_ETC___d700,
SEL_ARR_tlp_tlpBRAM_mReqF_first__16_BITS_127_T_ETC___d708,
SEL_ARR_tlp_tlpBRAM_mReqF_first__16_BITS_127_T_ETC___d716,
SEL_ARR_tlp_tlpBRAM_mReqF_first__16_BITS_127_T_ETC___d724,
_theResult____h91947;
reg [15 : 0] CASE_tlp_outDwRemain_BITS_1_TO_0_0b0_0xFFFF_0b_ETC__q3;
reg [3 : 0] CASE_tlp_lastRuleFired_1_tlp_lastRuleFired_2_t_ETC__q1;
reg [1 : 0] lowAddr10__h29651, x__h29780, x__h29803;
reg CASE_dpControl_BITS_1_TO_0_0_NOT_bml_fabDone_1_ETC__q5,
CASE_dpControl_BITS_1_TO_0_0_NOT_bml_fabDone_1_ETC__q6,
CASE_dpControl_BITS_1_TO_0_0_bml_fabDone_1_IF__ETC__q7,
CASE_dpControl_BITS_1_TO_0_0_bml_fabDone_1_bml_ETC__q4,
CASE_tlp_tlpBRAM_mReqF_first__16_BITS_30_TO_29_ETC___d736,
CASE_tlp_tlpBRAM_mReqF_first__16_BITS_51_TO_50_ETC___d623,
CASE_tlp_tlpBRAM_readReq_first__98_BITS_30_TO__ETC___d805,
CASE_tlp_tlpBRAM_readReq_first__98_BITS_30_TO__ETC___d810,
SEL_ARR_NOT_tlp_tlpBRAM_writeRemainDWLen_52_EQ_ETC___d665,
SEL_ARR_NOT_tlp_tlpBRAM_writeRemainDWLen_52_EQ_ETC___d669,
SEL_ARR_NOT_tlp_tlpBRAM_writeRemainDWLen_52_EQ_ETC___d673,
SEL_ARR_NOT_tlp_tlpBRAM_writeRemainDWLen_52_EQ_ETC___d677;
wire [127 : 0] IF_tlp_fabMesgAddrMS_078_EQ_0_079_THEN_0_ELSE__ETC___d1353,
IF_tlp_fabMetaAddrMS_157_EQ_0_158_THEN_4_ELSE__ETC___d1248,
IF_tlp_tlpBRAM_readReq_first__98_BITS_30_TO_29_ETC___d929,
IF_tlp_tlpBRAM_readReq_first__98_BITS_30_TO_29_ETC___d934,
pkt__h71785,
rdata__h35173,
rdata__h83703,
w_data__h47916,
w_data__h48052,
w_data__h52877,
w_data__h65836,
w_data__h66940,
w_data__h67186;
wire [63 : 0] wti_nowReq_BITS_63_TO_0__q2;
wire [31 : 0] bml_fabFlowAddr_937_PLUS_bml_fabFlowSize_938___d1939,
mesgMeta_opcode__h81853,
nowLS__h46239,
nowLS__h62622,
nowMS__h45280,
nowMS__h61665,
opcode__h44022,
opcode__h60417,
rdat__h92026,
rdat__h92034,
rdat__h92042,
rdat__h92050,
rdat__h92058,
rdat__h92066,
rdat__h92074,
rdat__h92095,
rdat__h92102,
rdat__h92115,
rdat__h92122,
rdat__h92129,
rdat__h92401,
rdat__h92451,
rdat__h92551,
rdat__h92609,
rdat__h92631,
rdat__h92641,
rdat__h92763,
rdat__h92887,
rdat__h92915,
rdat__h92943,
rdat__h92971,
rdat__h93001,
rdat__h93035,
rdat__h93068,
rdat__h93102,
rresp_data__h29698,
x3__h81813,
x__h42208,
x__h47258,
x__h58352,
x__h63608,
y__h47623,
y__h48181,
y__h63989;
wire [16 : 0] tlp_mesgLengthRemainPull_PLUS_3__q14,
tlp_mesgLengthRemainPush_PLUS_3__q15,
x__h47542,
x__h63926,
y__h47529,
y__h47544,
y__h63918,
y__h63928,
y__h65310;
wire [15 : 0] w_be__h48508,
x__h88675,
x__h89803,
x__h89808,
x__h89915,
x__h89952,
x__h90034,
x__h90039,
x__h90073,
x__h90078,
y__h47671,
y__h64598;
wire [12 : 0] spanToNextPage__h47503,
spanToNextPage__h63892,
thisRequestLength__h47504,
thisRequestLength__h63893,
tlp_tlpBRAM_readNxtDWAddr_PLUS_1__q11,
tlp_tlpBRAM_readNxtDWAddr_PLUS_2__q12,
tlp_tlpBRAM_readNxtDWAddr_PLUS_3__q13,
tlp_tlpBRAM_writeDWAddr_PLUS_1__q8,
tlp_tlpBRAM_writeDWAddr_PLUS_2__q9,
tlp_tlpBRAM_writeDWAddr_PLUS_3__q10,
y__h17362,
y__h27665;
wire [11 : 0] byteCount__h29653, x__h29771, x__h29773, y__h29772, y__h29774;
wire [9 : 0] y__h17428, y__h27653, y__h30729, y__h48147;
wire [7 : 0] rreq_tag__h47719, tag__h64168, tagm__h64387;
wire [6 : 0] lowAddr__h29652;
wire [3 : 0] lastBE__h47950, lastBE__h64200;
wire [2 : 0] bram_0_serverAdapterA_cnt_6_PLUS_IF_bram_0_ser_ETC___d32,
bram_0_serverAdapterB_cnt_5_PLUS_IF_bram_0_ser_ETC___d91,
bram_1_serverAdapterA_cnt_44_PLUS_IF_bram_1_se_ETC___d150,
bram_1_serverAdapterB_cnt_03_PLUS_IF_bram_1_se_ETC___d209,
bram_2_serverAdapterA_cnt_62_PLUS_IF_bram_2_se_ETC___d268,
bram_2_serverAdapterB_cnt_21_PLUS_IF_bram_2_se_ETC___d327,
bram_3_serverAdapterA_cnt_80_PLUS_IF_bram_3_se_ETC___d386,
bram_3_serverAdapterB_cnt_39_PLUS_IF_bram_3_se_ETC___d445;
wire [1 : 0] ab__h10465,
ab__h11870,
ab__h1619,
ab__h3026,
ab__h4569,
ab__h5974,
ab__h7517,
ab__h8922,
idx__h21626,
idx__h23676,
idx__h24781,
idx__h25886,
idx__h27879,
idx__h28282,
idx__h28586,
idx__h28890,
tlp_tlpBRAM_readReq_first__98_BITS_30_TO_29_00_ETC___d922,
wci_respF_cntr_r_90_MINUS_1___d499,
wmi_wmi_respF_cntr_r_582_MINUS_1___d1590;
wire IF_bml_dpControl_wget__898_BITS_1_TO_0_904_EQ__ETC___d1984,
IF_bml_dpControl_wget__898_BITS_3_TO_2_899_EQ__ETC___d1995,
NOT_SEL_ARR_NOT_tlp_tlpBRAM_writeRemainDWLen_5_ETC___d681,
NOT_tlp_tlpBRAM_writeRemainDWLen_52_ULE_1_55___d656,
NOT_tlp_tlpBRAM_writeRemainDWLen_52_ULE_2_57___d658,
NOT_tlp_tlpBRAM_writeRemainDWLen_52_ULE_3_59___d660,
NOT_wmi_wrActive_717_718_OR_NOT_wmi_rdActive_7_ETC___d1727,
_dfoo1,
_dfoo3,
_dfoo5,
_dfoo7,
_dfoo9,
bml_crdBuf_value_880_EQ_bml_crdBuf_modulus_bw__ETC___d1882,
bml_fabBuf_value_865_EQ_bml_fabBuf_modulus_bw__ETC___d1867,
bml_lclBufDone_922_AND_IF_bml_dpControl_wget___ETC___d2003,
bml_lclBuf_value_835_EQ_bml_lclBuf_modulus_bw__ETC___d1837,
bml_remBuf_value_850_EQ_bml_remBuf_modulus_bw__ETC___d1852,
bram_0_serverAdapterA_cnt_6_SLT_3___d619,
bram_0_serverAdapterA_outDataCore_notEmpty_OR__ETC___d887,
bram_0_serverAdapterB_cnt_5_SLT_3_666_AND_bram_ETC___d1672,
bram_0_serverAdapterB_cnt_5_SLT_3___d1666,
bram_0_serverAdapterB_outData_outData_whas__68_ETC___d1697,
bram_1_serverAdapterA_cnt_44_SLT_3___d620,
bram_1_serverAdapterB_cnt_03_SLT_3___d1667,
bram_1_serverAdapterB_outData_outData_whas__68_ETC___d1695,
bram_2_serverAdapterA_cnt_62_SLT_3___d621,
bram_2_serverAdapterA_outDataCore_notEmpty__38_ETC___d885,
bram_2_serverAdapterB_cnt_21_SLT_3___d1668,
bram_3_serverAdapterA_cnt_80_SLT_3___d622,
bram_3_serverAdapterB_cnt_39_SLT_3___d1669,
hasPull_AND_tlp_dpControl_wget__64_BITS_7_TO_4_ETC___d1233,
hasPull_AND_tlp_dpControl_wget__64_BITS_7_TO_4_ETC___d1274,
hasPull_AND_tlp_dpControl_wget__64_BITS_7_TO_4_ETC___d1326,
hasPull_AND_tlp_dpControl_wget__64_BITS_7_TO_4_ETC___d1365,
hasPull_AND_tlp_dpControl_wget__64_BITS_7_TO_4_ETC___d1385,
hasPull_AND_tlp_dpControl_wget__64_BITS_7_TO_4_ETC___d1410,
hasPush_AND_tlp_dpControl_wget__64_BITS_7_TO_4_ETC___d1058,
hasPush_AND_tlp_dpControl_wget__64_BITS_7_TO_4_ETC___d1098,
hasPush_AND_tlp_dpControl_wget__64_BITS_7_TO_4_ETC___d1155,
hasPush_AND_tlp_dpControl_wget__64_BITS_7_TO_4_ETC___d985,
tlp_dmaPullRemainDWLen_373_ULE_tlp_dmaPullRema_ETC___d1395,
tlp_dmaPullRemainDWSub_387_ULE_4___d1388,
tlp_inF_first__259_BITS_63_TO_56_262_EQ_pciDev_ETC___d1272,
tlp_inF_first__259_BIT_152_462_AND_NOT_tlp_inF_ETC___d1487,
tlp_outDwRemain_129_ULE_4___d1130,
tlp_tlpBRAM_mRespF_first__000_BITS_71_TO_62_10_ETC___d1102,
tlp_tlpBRAM_mRespF_i_notFull__97_AND_tlp_tlpBR_ETC___d813,
tlp_tlpBRAM_rdRespDwRemain_16_ULE_4___d918,
tlp_tlpBRAM_readRemainDWLen_74_ULE_4___d775,
wmi_wmi_operateD_606_AND_wmi_wmi_peerIsReady_6_ETC___d1777,
wmi_wmi_operateD_606_AND_wmi_wmi_peerIsReady_6_ETC___d1798;
// value method wci_s_sResp
assign wci_s_SResp = wci_respF_q_0[33:32] ;
// value method wci_s_sData
assign wci_s_SData = wci_respF_q_0[31:0] ;
// value method wci_s_sThreadBusy
assign wci_s_SThreadBusy =
wci_reqF_countReg > 2'd1 || wci_isReset_isInReset ;
// value method wci_s_sFlag
assign wci_s_SFlag = { 1'd1, wci_sFlagReg } ;
// value method wti_s_sThreadBusy
assign wti_s_SThreadBusy = wti_isReset_isInReset ;
// value method wti_s_sReset_n
assign wti_s_SReset_n = !wti_isReset_isInReset && wti_operateD ;
// value method wmiS0_sResp
assign wmiS0_SResp = wmi_wmi_respF_q_0[129:128] ;
// value method wmiS0_sData
assign wmiS0_SData = wmi_wmi_respF_q_0[127:0] ;
// value method wmiS0_sThreadBusy
assign wmiS0_SThreadBusy =
!wmi_wmi_sThreadBusy_dw_whas || wmi_wmi_sThreadBusy_dw_wget ;
// value method wmiS0_sDataThreadBusy
assign wmiS0_SDataThreadBusy =
!wmi_wmi_sDataThreadBusy_dw_whas ||
wmi_wmi_sDataThreadBusy_dw_wget ;
// value method wmiS0_sRespLast
assign wmiS0_SRespLast = 1'd0 ;
// value method wmiS0_sFlag
assign wmiS0_SFlag = wmi_wmi_sFlagReg ;
// value method wmiS0_sReset_n
assign wmiS0_SReset_n = !wmi_wmi_isReset_isInReset && wmi_wmi_operateD ;
// action method server_request_put
assign RDY_server_request_put = tlp_inF_FULL_N ;
// actionvalue method server_response_get
assign server_response_get = tlp_outF_D_OUT ;
assign RDY_server_response_get = tlp_outF_EMPTY_N ;
// submodule bram_0_memory
BRAM2 #(.PIPELINED(1'd0),
.ADDR_WIDTH(32'd11),
.DATA_WIDTH(32'd32),
.MEMSIZE(12'd2048)) bram_0_memory(.CLKA(CLK),
.CLKB(CLK),
.ADDRA(bram_0_memory_ADDRA),
.ADDRB(bram_0_memory_ADDRB),
.DIA(bram_0_memory_DIA),
.DIB(bram_0_memory_DIB),
.WEA(bram_0_memory_WEA),
.WEB(bram_0_memory_WEB),
.ENA(bram_0_memory_ENA),
.ENB(bram_0_memory_ENB),
.DOA(bram_0_memory_DOA),
.DOB(bram_0_memory_DOB));
// submodule bram_0_serverAdapterA_outDataCore
SizedFIFO #(.p1width(32'd32),
.p2depth(32'd3),
.p3cntr_width(32'd1),
.guarded(32'd1)) bram_0_serverAdapterA_outDataCore(.RST(RST_N),
.CLK(CLK),
.D_IN(bram_0_serverAdapterA_outDataCore_D_IN),
.ENQ(bram_0_serverAdapterA_outDataCore_ENQ),
.DEQ(bram_0_serverAdapterA_outDataCore_DEQ),
.CLR(bram_0_serverAdapterA_outDataCore_CLR),
.D_OUT(bram_0_serverAdapterA_outDataCore_D_OUT),
.FULL_N(bram_0_serverAdapterA_outDataCore_FULL_N),
.EMPTY_N(bram_0_serverAdapterA_outDataCore_EMPTY_N));
// submodule bram_0_serverAdapterB_outDataCore
SizedFIFO #(.p1width(32'd32),
.p2depth(32'd3),
.p3cntr_width(32'd1),
.guarded(32'd1)) bram_0_serverAdapterB_outDataCore(.RST(RST_N),
.CLK(CLK),
.D_IN(bram_0_serverAdapterB_outDataCore_D_IN),
.ENQ(bram_0_serverAdapterB_outDataCore_ENQ),
.DEQ(bram_0_serverAdapterB_outDataCore_DEQ),
.CLR(bram_0_serverAdapterB_outDataCore_CLR),
.D_OUT(bram_0_serverAdapterB_outDataCore_D_OUT),
.FULL_N(bram_0_serverAdapterB_outDataCore_FULL_N),
.EMPTY_N(bram_0_serverAdapterB_outDataCore_EMPTY_N));
// submodule bram_1_memory
BRAM2 #(.PIPELINED(1'd0),
.ADDR_WIDTH(32'd11),
.DATA_WIDTH(32'd32),
.MEMSIZE(12'd2048)) bram_1_memory(.CLKA(CLK),
.CLKB(CLK),
.ADDRA(bram_1_memory_ADDRA),
.ADDRB(bram_1_memory_ADDRB),
.DIA(bram_1_memory_DIA),
.DIB(bram_1_memory_DIB),
.WEA(bram_1_memory_WEA),
.WEB(bram_1_memory_WEB),
.ENA(bram_1_memory_ENA),
.ENB(bram_1_memory_ENB),
.DOA(bram_1_memory_DOA),
.DOB(bram_1_memory_DOB));
// submodule bram_1_serverAdapterA_outDataCore
SizedFIFO #(.p1width(32'd32),
.p2depth(32'd3),
.p3cntr_width(32'd1),
.guarded(32'd1)) bram_1_serverAdapterA_outDataCore(.RST(RST_N),
.CLK(CLK),
.D_IN(bram_1_serverAdapterA_outDataCore_D_IN),
.ENQ(bram_1_serverAdapterA_outDataCore_ENQ),
.DEQ(bram_1_serverAdapterA_outDataCore_DEQ),
.CLR(bram_1_serverAdapterA_outDataCore_CLR),
.D_OUT(bram_1_serverAdapterA_outDataCore_D_OUT),
.FULL_N(bram_1_serverAdapterA_outDataCore_FULL_N),
.EMPTY_N(bram_1_serverAdapterA_outDataCore_EMPTY_N));
// submodule bram_1_serverAdapterB_outDataCore
SizedFIFO #(.p1width(32'd32),
.p2depth(32'd3),
.p3cntr_width(32'd1),
.guarded(32'd1)) bram_1_serverAdapterB_outDataCore(.RST(RST_N),
.CLK(CLK),
.D_IN(bram_1_serverAdapterB_outDataCore_D_IN),
.ENQ(bram_1_serverAdapterB_outDataCore_ENQ),
.DEQ(bram_1_serverAdapterB_outDataCore_DEQ),
.CLR(bram_1_serverAdapterB_outDataCore_CLR),
.D_OUT(bram_1_serverAdapterB_outDataCore_D_OUT),
.FULL_N(bram_1_serverAdapterB_outDataCore_FULL_N),
.EMPTY_N(bram_1_serverAdapterB_outDataCore_EMPTY_N));
// submodule bram_2_memory
BRAM2 #(.PIPELINED(1'd0),
.ADDR_WIDTH(32'd11),
.DATA_WIDTH(32'd32),
.MEMSIZE(12'd2048)) bram_2_memory(.CLKA(CLK),
.CLKB(CLK),
.ADDRA(bram_2_memory_ADDRA),
.ADDRB(bram_2_memory_ADDRB),
.DIA(bram_2_memory_DIA),
.DIB(bram_2_memory_DIB),
.WEA(bram_2_memory_WEA),
.WEB(bram_2_memory_WEB),
.ENA(bram_2_memory_ENA),
.ENB(bram_2_memory_ENB),
.DOA(bram_2_memory_DOA),
.DOB(bram_2_memory_DOB));
// submodule bram_2_serverAdapterA_outDataCore
SizedFIFO #(.p1width(32'd32),
.p2depth(32'd3),
.p3cntr_width(32'd1),
.guarded(32'd1)) bram_2_serverAdapterA_outDataCore(.RST(RST_N),
.CLK(CLK),
.D_IN(bram_2_serverAdapterA_outDataCore_D_IN),
.ENQ(bram_2_serverAdapterA_outDataCore_ENQ),
.DEQ(bram_2_serverAdapterA_outDataCore_DEQ),
.CLR(bram_2_serverAdapterA_outDataCore_CLR),
.D_OUT(bram_2_serverAdapterA_outDataCore_D_OUT),
.FULL_N(bram_2_serverAdapterA_outDataCore_FULL_N),
.EMPTY_N(bram_2_serverAdapterA_outDataCore_EMPTY_N));
// submodule bram_2_serverAdapterB_outDataCore
SizedFIFO #(.p1width(32'd32),
.p2depth(32'd3),
.p3cntr_width(32'd1),
.guarded(32'd1)) bram_2_serverAdapterB_outDataCore(.RST(RST_N),
.CLK(CLK),
.D_IN(bram_2_serverAdapterB_outDataCore_D_IN),
.ENQ(bram_2_serverAdapterB_outDataCore_ENQ),
.DEQ(bram_2_serverAdapterB_outDataCore_DEQ),
.CLR(bram_2_serverAdapterB_outDataCore_CLR),
.D_OUT(bram_2_serverAdapterB_outDataCore_D_OUT),
.FULL_N(bram_2_serverAdapterB_outDataCore_FULL_N),
.EMPTY_N(bram_2_serverAdapterB_outDataCore_EMPTY_N));
// submodule bram_3_memory
BRAM2 #(.PIPELINED(1'd0),
.ADDR_WIDTH(32'd11),
.DATA_WIDTH(32'd32),
.MEMSIZE(12'd2048)) bram_3_memory(.CLKA(CLK),
.CLKB(CLK),
.ADDRA(bram_3_memory_ADDRA),
.ADDRB(bram_3_memory_ADDRB),
.DIA(bram_3_memory_DIA),
.DIB(bram_3_memory_DIB),
.WEA(bram_3_memory_WEA),
.WEB(bram_3_memory_WEB),
.ENA(bram_3_memory_ENA),
.ENB(bram_3_memory_ENB),
.DOA(bram_3_memory_DOA),
.DOB(bram_3_memory_DOB));
// submodule bram_3_serverAdapterA_outDataCore
SizedFIFO #(.p1width(32'd32),
.p2depth(32'd3),
.p3cntr_width(32'd1),
.guarded(32'd1)) bram_3_serverAdapterA_outDataCore(.RST(RST_N),
.CLK(CLK),
.D_IN(bram_3_serverAdapterA_outDataCore_D_IN),
.ENQ(bram_3_serverAdapterA_outDataCore_ENQ),
.DEQ(bram_3_serverAdapterA_outDataCore_DEQ),
.CLR(bram_3_serverAdapterA_outDataCore_CLR),
.D_OUT(bram_3_serverAdapterA_outDataCore_D_OUT),
.FULL_N(bram_3_serverAdapterA_outDataCore_FULL_N),
.EMPTY_N(bram_3_serverAdapterA_outDataCore_EMPTY_N));
// submodule bram_3_serverAdapterB_outDataCore
SizedFIFO #(.p1width(32'd32),
.p2depth(32'd3),
.p3cntr_width(32'd1),
.guarded(32'd1)) bram_3_serverAdapterB_outDataCore(.RST(RST_N),
.CLK(CLK),
.D_IN(bram_3_serverAdapterB_outDataCore_D_IN),
.ENQ(bram_3_serverAdapterB_outDataCore_ENQ),
.DEQ(bram_3_serverAdapterB_outDataCore_DEQ),
.CLR(bram_3_serverAdapterB_outDataCore_CLR),
.D_OUT(bram_3_serverAdapterB_outDataCore_D_OUT),
.FULL_N(bram_3_serverAdapterB_outDataCore_FULL_N),
.EMPTY_N(bram_3_serverAdapterB_outDataCore_EMPTY_N));
// submodule tlp_inF
arSRLFIFOD #(.width(32'd153), .l2depth(32'd4)) tlp_inF(.CLK(CLK),
.RST_N(RST_N),
.D_IN(tlp_inF_D_IN),
.DEQ(tlp_inF_DEQ),
.ENQ(tlp_inF_ENQ),
.CLR(tlp_inF_CLR),
.D_OUT(tlp_inF_D_OUT),
.EMPTY_N(tlp_inF_EMPTY_N),
.FULL_N(tlp_inF_FULL_N));
// submodule tlp_outF
arSRLFIFOD #(.width(32'd153), .l2depth(32'd4)) tlp_outF(.CLK(CLK),
.RST_N(RST_N),
.D_IN(tlp_outF_D_IN),
.DEQ(tlp_outF_DEQ),
.ENQ(tlp_outF_ENQ),
.CLR(tlp_outF_CLR),
.D_OUT(tlp_outF_D_OUT),
.EMPTY_N(tlp_outF_EMPTY_N),
.FULL_N(tlp_outF_FULL_N));
// submodule tlp_tailEventF
FIFO2 #(.width(32'd1), .guarded(32'd1)) tlp_tailEventF(.RST(RST_N),
.CLK(CLK),
.D_IN(tlp_tailEventF_D_IN),
.ENQ(tlp_tailEventF_ENQ),
.DEQ(tlp_tailEventF_DEQ),
.CLR(tlp_tailEventF_CLR),
.D_OUT(tlp_tailEventF_D_OUT),
.FULL_N(tlp_tailEventF_FULL_N),
.EMPTY_N(tlp_tailEventF_EMPTY_N));
// submodule tlp_tlpBRAM_mReqF
FIFO2 #(.width(32'd130), .guarded(32'd1)) tlp_tlpBRAM_mReqF(.RST(RST_N),
.CLK(CLK),
.D_IN(tlp_tlpBRAM_mReqF_D_IN),
.ENQ(tlp_tlpBRAM_mReqF_ENQ),
.DEQ(tlp_tlpBRAM_mReqF_DEQ),
.CLR(tlp_tlpBRAM_mReqF_CLR),
.D_OUT(tlp_tlpBRAM_mReqF_D_OUT),
.FULL_N(tlp_tlpBRAM_mReqF_FULL_N),
.EMPTY_N(tlp_tlpBRAM_mReqF_EMPTY_N));
// submodule tlp_tlpBRAM_mRespF
FIFO2 #(.width(32'd139), .guarded(32'd1)) tlp_tlpBRAM_mRespF(.RST(RST_N),
.CLK(CLK),
.D_IN(tlp_tlpBRAM_mRespF_D_IN),
.ENQ(tlp_tlpBRAM_mRespF_ENQ),
.DEQ(tlp_tlpBRAM_mRespF_DEQ),
.CLR(tlp_tlpBRAM_mRespF_CLR),
.D_OUT(tlp_tlpBRAM_mRespF_D_OUT),
.FULL_N(tlp_tlpBRAM_mRespF_FULL_N),
.EMPTY_N(tlp_tlpBRAM_mRespF_EMPTY_N));
// submodule tlp_tlpBRAM_readReq
FIFO2 #(.width(32'd61), .guarded(32'd1)) tlp_tlpBRAM_readReq(.RST(RST_N),
.CLK(CLK),
.D_IN(tlp_tlpBRAM_readReq_D_IN),
.ENQ(tlp_tlpBRAM_readReq_ENQ),
.DEQ(tlp_tlpBRAM_readReq_DEQ),
.CLR(tlp_tlpBRAM_readReq_CLR),
.D_OUT(tlp_tlpBRAM_readReq_D_OUT),
.FULL_N(tlp_tlpBRAM_readReq_FULL_N),
.EMPTY_N(tlp_tlpBRAM_readReq_EMPTY_N));
// submodule wci_reqF
SizedFIFO #(.p1width(32'd72),
.p2depth(32'd3),
.p3cntr_width(32'd1),
.guarded(32'd1)) wci_reqF(.RST(RST_N),
.CLK(CLK),
.D_IN(wci_reqF_D_IN),
.ENQ(wci_reqF_ENQ),
.DEQ(wci_reqF_DEQ),
.CLR(wci_reqF_CLR),
.D_OUT(wci_reqF_D_OUT),
.FULL_N(),
.EMPTY_N(wci_reqF_EMPTY_N));
// submodule wmi_wmi_dhF
SizedFIFO #(.p1width(32'd146),
.p2depth(32'd3),
.p3cntr_width(32'd1),
.guarded(32'd1)) wmi_wmi_dhF(.RST(RST_N),
.CLK(CLK),
.D_IN(wmi_wmi_dhF_D_IN),
.ENQ(wmi_wmi_dhF_ENQ),
.DEQ(wmi_wmi_dhF_DEQ),
.CLR(wmi_wmi_dhF_CLR),
.D_OUT(wmi_wmi_dhF_D_OUT),
.FULL_N(wmi_wmi_dhF_FULL_N),
.EMPTY_N(wmi_wmi_dhF_EMPTY_N));
// submodule wmi_wmi_mFlagF
SizedFIFO #(.p1width(32'd32),
.p2depth(32'd3),
.p3cntr_width(32'd1),
.guarded(32'd1)) wmi_wmi_mFlagF(.RST(RST_N),
.CLK(CLK),
.D_IN(wmi_wmi_mFlagF_D_IN),
.ENQ(wmi_wmi_mFlagF_ENQ),
.DEQ(wmi_wmi_mFlagF_DEQ),
.CLR(wmi_wmi_mFlagF_CLR),
.D_OUT(wmi_wmi_mFlagF_D_OUT),
.FULL_N(wmi_wmi_mFlagF_FULL_N),
.EMPTY_N(wmi_wmi_mFlagF_EMPTY_N));
// submodule wmi_wmi_reqF
SizedFIFO #(.p1width(32'd32),
.p2depth(32'd3),
.p3cntr_width(32'd1),
.guarded(32'd1)) wmi_wmi_reqF(.RST(RST_N),
.CLK(CLK),
.D_IN(wmi_wmi_reqF_D_IN),
.ENQ(wmi_wmi_reqF_ENQ),
.DEQ(wmi_wmi_reqF_DEQ),
.CLR(wmi_wmi_reqF_CLR),
.D_OUT(wmi_wmi_reqF_D_OUT),
.FULL_N(wmi_wmi_reqF_FULL_N),
.EMPTY_N(wmi_wmi_reqF_EMPTY_N));
// rule RL_bram_2_serverAdapterA_outData_setFirstEnq
assign WILL_FIRE_RL_bram_2_serverAdapterA_outData_setFirstEnq =
!bram_2_serverAdapterA_outDataCore_EMPTY_N &&
bram_2_serverAdapterA_outData_enqData_whas ;
// rule RL_wci_cfrd
assign WILL_FIRE_RL_wci_cfrd =
wci_respF_cntr_r != 2'd2 && wci_reqF_EMPTY_N &&
wci_wci_cfrd_pw_whas &&
!WILL_FIRE_RL_wci_ctl_op_start &&
!WILL_FIRE_RL_wci_ctl_op_complete ;
// rule RL_wci_ctl_op_start
assign WILL_FIRE_RL_wci_ctl_op_start =
wci_reqF_EMPTY_N && wci_wci_ctrl_pw_whas &&
!WILL_FIRE_RL_wci_ctl_op_complete ;
// rule RL_tlp_dmaRequestNearMeta
assign WILL_FIRE_RL_tlp_dmaRequestNearMeta =
tlp_tlpBRAM_mReqF_FULL_N &&
hasPush_AND_tlp_dpControl_wget__64_BITS_7_TO_4_ETC___d985 &&
tlp_farBufReady &&
tlp_postSeqDwell == 4'd0 ;
// rule RL_tlp_dmaPushRequestMesg
assign WILL_FIRE_RL_tlp_dmaPushRequestMesg =
tlp_tlpBRAM_mReqF_FULL_N &&
hasPush_AND_tlp_dpControl_wget__64_BITS_7_TO_4_ETC___d1058 &&
!WILL_FIRE_RL_tlp_dmaResponseNearMetaBody ;
// rule RL_tlp_dmaResponseNearMetaHead
assign WILL_FIRE_RL_tlp_dmaResponseNearMetaHead =
tlp_tlpBRAM_mRespF_EMPTY_N && hasPush &&
dpControl[7:4] == 4'd0 &&
dpControl[3:2] == 2'd1 &&
dpControl[1:0] == 2'd1 &&
!tlp_tlpBRAM_mRespF_D_OUT[138] &&
tlp_tlpBRAM_mRespF_D_OUT[89:88] == 2'd3 ;
// rule RL_tlp_dmaPushResponseHeader
assign WILL_FIRE_RL_tlp_dmaPushResponseHeader =
tlp_outF_FULL_N && tlp_tlpBRAM_mRespF_EMPTY_N &&
hasPush_AND_tlp_dpControl_wget__64_BITS_7_TO_4_ETC___d1098 ;
// rule RL_tlp_dmaPushResponseBody
assign WILL_FIRE_RL_tlp_dmaPushResponseBody =
tlp_outF_FULL_N && tlp_tlpBRAM_mRespF_EMPTY_N && hasPush &&
dpControl[7:4] == 4'd0 &&
dpControl[3:2] == 2'd1 &&
dpControl[1:0] == 2'd1 &&
tlp_tlpBRAM_mRespF_D_OUT[138] &&
tlp_tlpBRAM_mRespF_D_OUT[137:136] == 2'd2 ;
// rule RL_tlp_dmaXmtMetaHead
assign WILL_FIRE_RL_tlp_dmaXmtMetaHead =
tlp_outF_FULL_N &&
hasPush_AND_tlp_dpControl_wget__64_BITS_7_TO_4_ETC___d1155 &&
!WILL_FIRE_RL_tlp_dmaPushResponseBody &&
!WILL_FIRE_RL_tlp_dmaPushResponseHeader ;
// rule RL_tlp_dmaXmtTailEvent
assign WILL_FIRE_RL_tlp_dmaXmtTailEvent =
tlp_tailEventF_FULL_N && hasPush && dpControl[7:4] == 4'd0 &&
dpControl[3:2] == 2'd1 &&
dpControl[1:0] == 2'd1 &&
tlp_fabMeta[128] &&
tlp_tlpMetaSent ;
// rule RL_tlp_dmaXmtMetaBody
assign CAN_FIRE_RL_tlp_dmaXmtMetaBody =
tlp_outF_FULL_N && hasPush && dpControl[7:4] == 4'd0 &&
dpControl[3:2] == 2'd1 &&
dpControl[1:0] == 2'd1 &&
tlp_fabMeta[128] &&
tlp_doXmtMetaBody ;
assign WILL_FIRE_RL_tlp_dmaXmtMetaBody =
CAN_FIRE_RL_tlp_dmaXmtMetaBody &&
!WILL_FIRE_RL_tlp_dmaXmtMetaHead &&
!WILL_FIRE_RL_tlp_dmaPushResponseBody &&
!WILL_FIRE_RL_tlp_dmaPushResponseHeader ;
// rule RL_tlp_dmaXmtDoorbell
assign WILL_FIRE_RL_tlp_dmaXmtDoorbell =
tlp_tailEventF_FULL_N && dpControl[1:0] == 2'd2 &&
tlp_creditReady &&
tlp_doorSeqDwell == 4'd0 ;
// rule RL_tlp_dmaRespHeadFarMeta
assign WILL_FIRE_RL_tlp_dmaRespHeadFarMeta =
tlp_inF_EMPTY_N && tlp_tlpBRAM_mReqF_FULL_N &&
hasPull_AND_tlp_dpControl_wget__64_BITS_7_TO_4_ETC___d1274 ;
// rule RL_tlp_dmaPullTailEvent
assign WILL_FIRE_RL_tlp_dmaPullTailEvent =
tlp_tailEventF_FULL_N &&
hasPull_AND_tlp_dpControl_wget__64_BITS_7_TO_4_ETC___d1410 ;
// rule RL_tlp_dmaRespBodyFarMeta
assign CAN_FIRE_RL_tlp_dmaRespBodyFarMeta =
tlp_inF_EMPTY_N && tlp_tlpBRAM_mReqF_FULL_N && hasPull &&
dpControl[7:4] == 4'd0 &&
dpControl[3:2] == 2'd2 &&
dpControl[1:0] == 2'd1 &&
tlp_reqMetaBodyInFlight &&
!tlp_tlpRcvBusy ;
assign WILL_FIRE_RL_tlp_dmaRespBodyFarMeta =
CAN_FIRE_RL_tlp_dmaRespBodyFarMeta &&
!WILL_FIRE_RL_tlp_dmaRespHeadFarMeta ;
// rule RL_tlp_dmaPullResponseHeader
assign WILL_FIRE_RL_tlp_dmaPullResponseHeader =
tlp_inF_EMPTY_N && tlp_tlpBRAM_mReqF_FULL_N &&
hasPull_AND_tlp_dpControl_wget__64_BITS_7_TO_4_ETC___d1365 &&
!WILL_FIRE_RL_tlp_dmaRespBodyFarMeta &&
!WILL_FIRE_RL_tlp_dmaRespHeadFarMeta ;
// rule RL_tlp_dmaPullResponseBody
assign WILL_FIRE_RL_tlp_dmaPullResponseBody =
tlp_inF_EMPTY_N && tlp_tlpBRAM_mReqF_FULL_N &&
hasPull_AND_tlp_dpControl_wget__64_BITS_7_TO_4_ETC___d1385 &&
!WILL_FIRE_RL_tlp_dmaRespBodyFarMeta &&
!WILL_FIRE_RL_tlp_dmaRespHeadFarMeta ;
// rule RL_tlp_dmaTailEventSender
assign CAN_FIRE_RL_tlp_dmaTailEventSender =
tlp_outF_FULL_N && tlp_tailEventF_EMPTY_N &&
(!tlp_tlpXmtBusy && !tlp_sentTail4DWHeader &&
tlp_postSeqDwell == 4'd0 ||
tlp_tlpXmtBusy && tlp_sentTail4DWHeader) ;
assign WILL_FIRE_RL_tlp_dmaTailEventSender =
CAN_FIRE_RL_tlp_dmaTailEventSender &&
!WILL_FIRE_RL_tlp_dmaPullRequestFarMesg &&
!WILL_FIRE_RL_tlp_dmaRequestFarMeta &&
!(tlp_postSeqDwell != 4'd0) &&
!WILL_FIRE_RL_tlp_dmaXmtMetaBody &&
!WILL_FIRE_RL_tlp_dmaXmtMetaHead &&
!WILL_FIRE_RL_tlp_dmaPushResponseBody &&
!WILL_FIRE_RL_tlp_dmaPushResponseHeader ;
// rule RL_tlp_tlpRcv
assign CAN_FIRE_RL_tlp_tlpRcv =
tlp_inF_EMPTY_N &&
(tlp_inF_D_OUT[152] ?
tlp_inF_D_OUT[110] || tlp_inF_D_OUT[125] ||
tlp_inF_D_OUT[124:120] != 5'b0 ||
tlp_tlpBRAM_mReqF_FULL_N :
tlp_inIgnorePkt || tlp_tlpBRAM_mReqF_FULL_N) &&
!tlp_reqMetaInFlight &&
!tlp_reqMesgInFlight &&
!tlp_reqMetaBodyInFlight ;
assign WILL_FIRE_RL_tlp_tlpRcv =
CAN_FIRE_RL_tlp_tlpRcv && !WILL_FIRE_RL_tlp_dmaPushRequestMesg &&
!WILL_FIRE_RL_tlp_dmaRequestNearMeta ;
// rule RL_tlp_dmaResponseNearMetaBody
assign WILL_FIRE_RL_tlp_dmaResponseNearMetaBody =
tlp_tlpBRAM_mRespF_EMPTY_N && hasPush &&
dpControl[7:4] == 4'd0 &&
dpControl[3:2] == 2'd1 &&
dpControl[1:0] == 2'd1 &&
tlp_tlpBRAM_mRespF_D_OUT[138] &&
tlp_tlpBRAM_mRespF_D_OUT[137:136] == 2'd3 ;
// rule RL_tlp_dmaRequestFarMeta
assign WILL_FIRE_RL_tlp_dmaRequestFarMeta =
tlp_outF_FULL_N &&
hasPull_AND_tlp_dpControl_wget__64_BITS_7_TO_4_ETC___d1233 &&
tlp_nearBufReady &&
tlp_farBufReady &&
tlp_postSeqDwell == 4'd0 ;
// rule RL_tlp_dmaPullRequestFarMesg
assign WILL_FIRE_RL_tlp_dmaPullRequestFarMesg =
tlp_outF_FULL_N &&
hasPull_AND_tlp_dpControl_wget__64_BITS_7_TO_4_ETC___d1326 &&
!WILL_FIRE_RL_tlp_dmaRespBodyFarMeta &&
!WILL_FIRE_RL_tlp_dmaRespHeadFarMeta ;
// rule RL_tlp_dataXmt_Header
assign WILL_FIRE_RL_tlp_dataXmt_Header =
tlp_outF_FULL_N && tlp_tlpBRAM_mRespF_EMPTY_N &&
!tlp_tlpBRAM_mRespF_D_OUT[138] &&
tlp_tlpBRAM_mRespF_D_OUT[89:88] == 2'd1 &&
!tlp_tlpXmtBusy &&
!WILL_FIRE_RL_tlp_dmaTailEventSender &&
!WILL_FIRE_RL_tlp_dmaPullRequestFarMesg &&
!WILL_FIRE_RL_tlp_dmaRequestFarMeta &&
!WILL_FIRE_RL_tlp_dmaXmtMetaBody &&
!WILL_FIRE_RL_tlp_dmaXmtMetaHead ;
// rule RL_tlp_dataXmt_Body
assign WILL_FIRE_RL_tlp_dataXmt_Body =
tlp_outF_FULL_N && tlp_tlpBRAM_mRespF_EMPTY_N &&
tlp_tlpBRAM_mRespF_D_OUT[138] &&
tlp_tlpBRAM_mRespF_D_OUT[137:136] == 2'd1 &&
!WILL_FIRE_RL_tlp_dmaTailEventSender &&
!WILL_FIRE_RL_tlp_dmaPullRequestFarMesg &&
!WILL_FIRE_RL_tlp_dmaRequestFarMeta &&
!WILL_FIRE_RL_tlp_dmaXmtMetaBody &&
!WILL_FIRE_RL_tlp_dmaXmtMetaHead ;
// rule RL_tlp_tlpBRAM_writeReq
assign WILL_FIRE_RL_tlp_tlpBRAM_writeReq =
tlp_tlpBRAM_mReqF_EMPTY_N &&
(tlp_tlpBRAM_mReqF_D_OUT[63] ||
CASE_tlp_tlpBRAM_mReqF_first__16_BITS_51_TO_50_ETC___d623) &&
tlp_tlpBRAM_mReqF_D_OUT[129:128] == 2'd0 ;
// rule RL_tlp_tlpBRAM_writeData
assign WILL_FIRE_RL_tlp_tlpBRAM_writeData =
tlp_tlpBRAM_mReqF_EMPTY_N &&
(!SEL_ARR_NOT_tlp_tlpBRAM_writeRemainDWLen_52_EQ_ETC___d665 ||
bram_0_serverAdapterA_cnt_6_SLT_3___d619) &&
NOT_SEL_ARR_NOT_tlp_tlpBRAM_writeRemainDWLen_5_ETC___d681 &&
tlp_tlpBRAM_mReqF_D_OUT[129:128] == 2'd1 ;
// rule RL_tlp_tlpBRAM_read_FirstReq
assign WILL_FIRE_RL_tlp_tlpBRAM_read_FirstReq =
tlp_tlpBRAM_mReqF_EMPTY_N && tlp_tlpBRAM_readReq_FULL_N &&
(tlp_tlpBRAM_mReqF_D_OUT[60] ||
CASE_tlp_tlpBRAM_mReqF_first__16_BITS_30_TO_29_ETC___d736) &&
!tlp_tlpBRAM_readStarted &&
tlp_tlpBRAM_mReqF_D_OUT[129:128] != 2'd0 &&
tlp_tlpBRAM_mReqF_D_OUT[129:128] != 2'd1 ;
// rule RL_tlp_tlpBRAM_read_NextReq
assign WILL_FIRE_RL_tlp_tlpBRAM_read_NextReq =
bram_0_serverAdapterA_cnt_6_SLT_3___d619 &&
bram_1_serverAdapterA_cnt_44_SLT_3___d620 &&
bram_2_serverAdapterA_cnt_62_SLT_3___d621 &&
bram_3_serverAdapterA_cnt_80_SLT_3___d622 &&
tlp_tlpBRAM_mReqF_EMPTY_N &&
tlp_tlpBRAM_readStarted &&
tlp_tlpBRAM_mReqF_D_OUT[129:128] != 2'd0 &&
tlp_tlpBRAM_mReqF_D_OUT[129:128] != 2'd1 ;
// rule RL_tlp_tlpBRAM_read_FirstResp
assign WILL_FIRE_RL_tlp_tlpBRAM_read_FirstResp =
tlp_tlpBRAM_readReq_EMPTY_N &&
tlp_tlpBRAM_mRespF_i_notFull__97_AND_tlp_tlpBR_ETC___d813 &&
!tlp_tlpBRAM_readHeaderSent ;
// rule RL_tlp_tlpBRAM_read_NextResp
assign WILL_FIRE_RL_tlp_tlpBRAM_read_NextResp =
tlp_tlpBRAM_readReq_EMPTY_N &&
bram_0_serverAdapterA_outDataCore_notEmpty_OR__ETC___d887 &&
tlp_tlpBRAM_readHeaderSent ;
// rule RL_bram_0_serverAdapterA_outData_enqAndDeq
assign WILL_FIRE_RL_bram_0_serverAdapterA_outData_enqAndDeq =
bram_0_serverAdapterA_outDataCore_EMPTY_N &&
bram_0_serverAdapterA_outDataCore_FULL_N &&
bram_0_serverAdapterA_outData_deqCalled_whas &&
bram_0_serverAdapterA_outData_enqData_whas ;
// rule RL_bram_1_serverAdapterA_outData_enqAndDeq
assign WILL_FIRE_RL_bram_1_serverAdapterA_outData_enqAndDeq =
bram_1_serverAdapterA_outDataCore_EMPTY_N &&
bram_1_serverAdapterA_outDataCore_FULL_N &&
bram_1_serverAdapterA_outData_deqCalled_whas &&
bram_1_serverAdapterA_outData_enqData_whas ;
// rule RL_bram_2_serverAdapterA_outData_enqAndDeq
assign WILL_FIRE_RL_bram_2_serverAdapterA_outData_enqAndDeq =
bram_2_serverAdapterA_outDataCore_EMPTY_N &&
bram_2_serverAdapterA_outDataCore_FULL_N &&
bram_2_serverAdapterA_outData_deqCalled_whas &&
bram_2_serverAdapterA_outData_enqData_whas ;
// rule RL_bram_3_serverAdapterA_outData_enqAndDeq
assign WILL_FIRE_RL_bram_3_serverAdapterA_outData_enqAndDeq =
bram_3_serverAdapterA_outDataCore_EMPTY_N &&
bram_3_serverAdapterA_outDataCore_FULL_N &&
bram_3_serverAdapterA_outData_deqCalled_whas &&
bram_3_serverAdapterA_outData_enqData_whas ;
// rule RL_wmi_reqMetadata
assign CAN_FIRE_RL_wmi_reqMetadata =
bram_0_serverAdapterB_cnt_5_SLT_3_666_AND_bram_ETC___d1672 &&
dpControl[3:2] != 2'd1 &&
!wmi_mesgMeta[128] &&
wmi_mesgBufReady &&
!wmi_metaBusy &&
wmi_bufDwell == 2'd0 ;
assign WILL_FIRE_RL_wmi_reqMetadata =
CAN_FIRE_RL_wmi_reqMetadata && !WILL_FIRE_RL_wmi_doReadReq &&
!WILL_FIRE_RL_wmi_doWriteReq &&
!WILL_FIRE_RL_wmi_doWriteFinalize ;
// rule RL_wmi_doWriteFinalize
assign WILL_FIRE_RL_wmi_doWriteFinalize =
wmi_wmi_operateD_606_AND_wmi_wmi_peerIsReady_6_ETC___d1777 &&
wmi_wrFinalize ;
// rule RL_wmi_respMetadata
assign CAN_FIRE_RL_wmi_respMetadata =
wmi_wmi_operateD && wmi_wmi_peerIsReady &&
(bram_0_serverAdapterB_outDataCore_EMPTY_N ||
bram_0_serverAdapterB_outData_enqData_whas) &&
bram_0_serverAdapterB_outData_outData_whas__68_ETC___d1697 &&
dpControl[3:2] != 2'd1 &&
!wmi_mesgMeta[128] &&
wmi_mesgBufReady &&
wmi_metaBusy ;
assign WILL_FIRE_RL_wmi_respMetadata =
CAN_FIRE_RL_wmi_respMetadata && !WILL_FIRE_RL_wmi_doReadResp ;
// rule RL_wmi_doReadReq
assign WILL_FIRE_RL_wmi_doReadReq =
bram_0_serverAdapterB_cnt_5_SLT_3_666_AND_bram_ETC___d1672 &&
wmi_rdActive &&
!WILL_FIRE_RL_wmi_doWriteReq &&
!WILL_FIRE_RL_wmi_doWriteFinalize ;
// rule RL_wmi_doReadResp
assign WILL_FIRE_RL_wmi_doReadResp =
wmi_wmi_respF_cntr_r != 2'd2 &&
wmi_wmi_operateD_606_AND_wmi_wmi_peerIsReady_6_ETC___d1798 &&
wmi_bytesRemainResp != 14'd0 ;
// rule RL_bram_0_serverAdapterB_outData_enqAndDeq
assign WILL_FIRE_RL_bram_0_serverAdapterB_outData_enqAndDeq =
bram_0_serverAdapterB_outDataCore_EMPTY_N &&
bram_0_serverAdapterB_outDataCore_FULL_N &&
bram_0_serverAdapterB_outData_deqCalled_whas &&
bram_0_serverAdapterB_outData_enqData_whas ;
// rule RL_bram_1_serverAdapterB_outData_enqAndDeq
assign WILL_FIRE_RL_bram_1_serverAdapterB_outData_enqAndDeq =
bram_1_serverAdapterB_outDataCore_EMPTY_N &&
bram_1_serverAdapterB_outDataCore_FULL_N &&
bram_0_serverAdapterB_outData_deqCalled_whas &&
bram_1_serverAdapterB_outData_enqData_whas ;
// rule RL_bram_2_serverAdapterB_outData_enqAndDeq
assign WILL_FIRE_RL_bram_2_serverAdapterB_outData_enqAndDeq =
bram_2_serverAdapterB_outDataCore_EMPTY_N &&
bram_2_serverAdapterB_outDataCore_FULL_N &&
bram_0_serverAdapterB_outData_deqCalled_whas &&
bram_2_serverAdapterB_outData_enqData_whas ;
// rule RL_bram_3_serverAdapterB_outData_enqAndDeq
assign WILL_FIRE_RL_bram_3_serverAdapterB_outData_enqAndDeq =
bram_3_serverAdapterB_outDataCore_EMPTY_N &&
bram_3_serverAdapterB_outDataCore_FULL_N &&
bram_0_serverAdapterB_outData_deqCalled_whas &&
bram_3_serverAdapterB_outData_enqData_whas ;
// rule RL_wmi_getRequest
assign CAN_FIRE_RL_wmi_getRequest =
wmi_wmi_operateD && wmi_wmi_peerIsReady && !wmi_wmi_blockReq &&
wmi_wmi_reqF_EMPTY_N &&
NOT_wmi_wrActive_717_718_OR_NOT_wmi_rdActive_7_ETC___d1727 &&
wmi_bufDwell == 2'd0 ;
assign WILL_FIRE_RL_wmi_getRequest =
CAN_FIRE_RL_wmi_getRequest && !WILL_FIRE_RL_wmi_doReadReq &&
!WILL_FIRE_RL_wmi_doWriteReq ;
// rule RL_wmi_doWriteReq
assign CAN_FIRE_RL_wmi_doWriteReq =
wmi_wmi_operateD && wmi_wmi_peerIsReady &&
bram_0_serverAdapterB_cnt_5_SLT_3___d1666 &&
bram_1_serverAdapterB_cnt_03_SLT_3___d1667 &&
bram_2_serverAdapterB_cnt_21_SLT_3___d1668 &&
bram_3_serverAdapterB_cnt_39_SLT_3___d1669 &&
wmi_wmi_dhF_EMPTY_N &&
wmi_wrActive ;
assign WILL_FIRE_RL_wmi_doWriteReq =
CAN_FIRE_RL_wmi_doWriteReq && !WILL_FIRE_RL_wmi_doWriteFinalize ;
// rule RL_wmi_wmi_respF_incCtr
assign WILL_FIRE_RL_wmi_wmi_respF_incCtr =
WILL_FIRE_RL_wmi_doReadResp && WILL_FIRE_RL_wmi_doReadResp &&
!(wmi_wmi_respF_cntr_r != 2'd0) ;
// rule RL_wmi_wmi_respF_decCtr
assign WILL_FIRE_RL_wmi_wmi_respF_decCtr =
wmi_wmi_respF_cntr_r != 2'd0 && !WILL_FIRE_RL_wmi_doReadResp ;
// rule RL_wmi_wmi_respF_both
assign WILL_FIRE_RL_wmi_wmi_respF_both =
WILL_FIRE_RL_wmi_doReadResp && wmi_wmi_respF_cntr_r != 2'd0 &&
WILL_FIRE_RL_wmi_doReadResp ;
// rule RL_bml_fba
assign WILL_FIRE_RL_bml_fba = wci_cState == 3'd2 && dpControl[1:0] == 2'd1 ;
// rule RL_bml_lcredit
assign WILL_FIRE_RL_bml_lcredit =
wci_cState == 3'd2 && dpControl[1:0] == 2'd2 ;
// rule RL_bml_lclAdvance
assign WILL_FIRE_RL_bml_lclAdvance = wci_cState == 3'd2 && bml_lclBufDone ;
// rule RL_bml_remAdvance
assign CAN_FIRE_RL_bml_remAdvance = wci_cState == 3'd2 && bml_remDone ;
assign WILL_FIRE_RL_bml_remAdvance =
CAN_FIRE_RL_bml_remAdvance && !WILL_FIRE_RL_bml_crdAdvance ;
// rule RL_bml_crdAdvance
assign WILL_FIRE_RL_bml_crdAdvance =
wci_cState == 3'd2 && dpControl[1:0] == 2'd2 && bml_remStart ;
// rule RL_bml_initAccumulators
assign WILL_FIRE_RL_bml_initAccumulators =
wci_wci_ctrl_pw_whas && WILL_FIRE_RL_wci_ctl_op_start &&
wci_cState == 3'd1 &&
wci_reqF_D_OUT[36:34] == 3'd1 ;
// rule RL_wci_cfwr
assign WILL_FIRE_RL_wci_cfwr =
wci_respF_cntr_r != 2'd2 && wci_reqF_EMPTY_N &&
wci_wci_cfwr_pw_whas &&
!WILL_FIRE_RL_wci_ctl_op_start &&
!WILL_FIRE_RL_wci_ctl_op_complete ;
// rule RL_wci_ctl_op_complete
assign WILL_FIRE_RL_wci_ctl_op_complete =
wci_respF_cntr_r != 2'd2 && wci_ctlOpActive && wci_ctlAckReg ;
// rule RL_wci_respF_incCtr
assign WILL_FIRE_RL_wci_respF_incCtr =
wci_respF_enqueueing_whas && wci_respF_enqueueing_whas &&
!(wci_respF_cntr_r != 2'd0) ;
// rule RL_wci_respF_decCtr
assign WILL_FIRE_RL_wci_respF_decCtr =
wci_respF_cntr_r != 2'd0 && !wci_respF_enqueueing_whas ;
// rule RL_wci_respF_both
assign WILL_FIRE_RL_wci_respF_both =
wci_respF_enqueueing_whas && wci_respF_cntr_r != 2'd0 &&
wci_respF_enqueueing_whas ;
// rule RL_wmi_wmi_reqF_reset
assign WILL_FIRE_RL_wmi_wmi_reqF_reset =
MUX_wmi_wmi_reqF_levelsValid_write_1__SEL_2 ||
WILL_FIRE_RL_wmi_getRequest ;
// rule RL_wmi_wmi_mFlagF_reset
assign WILL_FIRE_RL_wmi_wmi_mFlagF_reset =
MUX_wmi_wmi_mFlagF_levelsValid_write_1__SEL_2 ||
WILL_FIRE_RL_wmi_doWriteFinalize ;
// rule RL_wmi_wmi_dhF_reset
assign WILL_FIRE_RL_wmi_wmi_dhF_reset =
MUX_wmi_wmi_dhF_levelsValid_write_1__SEL_2 ||
WILL_FIRE_RL_wmi_doWriteReq ;
// inputs to muxes for submodule ports
assign MUX_bml_fabBufsAvail_write_1__SEL_1 =
WILL_FIRE_RL_bml_fba &&
(bml_fabAvail && !bml_remStart ||
!bml_fabAvail && bml_remStart) ;
assign MUX_bml_fabFlowAddr_write_1__SEL_1 =
WILL_FIRE_RL_bml_remAdvance && dpControl[1:0] == 2'd1 ;
assign MUX_bml_lclBufsAR_write_1__SEL_1 =
wci_cState == 3'd2 &&
IF_bml_dpControl_wget__898_BITS_1_TO_0_904_EQ__ETC___d1984 ;
assign MUX_bml_lclBufsCF_write_1__SEL_1 =
wci_cState == 3'd2 &&
bml_lclBufDone_922_AND_IF_bml_dpControl_wget___ETC___d2003 ;
assign MUX_bml_lclCredit_write_1__SEL_1 =
WILL_FIRE_RL_bml_lcredit &&
(bml_lclBufDone && !bml_remStart ||
!bml_lclBufDone && bml_remStart) ;
assign MUX_bram_0_memory_a_put_1__SEL_1 =
WILL_FIRE_RL_tlp_tlpBRAM_writeData &&
SEL_ARR_NOT_tlp_tlpBRAM_writeRemainDWLen_52_EQ_ETC___d665 ;
assign MUX_bram_0_memory_a_put_1__SEL_2 =
WILL_FIRE_RL_tlp_tlpBRAM_writeReq &&
tlp_tlpBRAM_mReqF_D_OUT[51:50] == 2'd0 &&
!tlp_tlpBRAM_mReqF_D_OUT[63] ;
assign MUX_bram_0_memory_a_put_1__SEL_3 =
WILL_FIRE_RL_tlp_tlpBRAM_read_FirstReq &&
tlp_tlpBRAM_mReqF_D_OUT[30:29] == 2'd0 &&
!tlp_tlpBRAM_mReqF_D_OUT[60] ;
assign MUX_bram_0_serverAdapterB_writeWithResp_wset_1__SEL_1 =
WILL_FIRE_RL_wmi_reqMetadata || WILL_FIRE_RL_wmi_doReadReq ;
assign MUX_bram_1_memory_a_put_1__SEL_1 =
WILL_FIRE_RL_tlp_tlpBRAM_writeData &&
SEL_ARR_NOT_tlp_tlpBRAM_writeRemainDWLen_52_EQ_ETC___d669 ;
assign MUX_bram_1_memory_a_put_1__SEL_2 =
WILL_FIRE_RL_tlp_tlpBRAM_writeReq &&
tlp_tlpBRAM_mReqF_D_OUT[51:50] == 2'd1 &&
!tlp_tlpBRAM_mReqF_D_OUT[63] ;
assign MUX_bram_1_memory_a_put_1__SEL_3 =
WILL_FIRE_RL_tlp_tlpBRAM_read_FirstReq &&
tlp_tlpBRAM_mReqF_D_OUT[30:29] == 2'd1 &&
!tlp_tlpBRAM_mReqF_D_OUT[60] ;
assign MUX_bram_2_memory_a_put_1__SEL_1 =
WILL_FIRE_RL_tlp_tlpBRAM_writeData &&
SEL_ARR_NOT_tlp_tlpBRAM_writeRemainDWLen_52_EQ_ETC___d673 ;
assign MUX_bram_2_memory_a_put_1__SEL_2 =
WILL_FIRE_RL_tlp_tlpBRAM_writeReq &&
tlp_tlpBRAM_mReqF_D_OUT[51:50] == 2'd2 &&
!tlp_tlpBRAM_mReqF_D_OUT[63] ;
assign MUX_bram_2_memory_a_put_1__SEL_3 =
WILL_FIRE_RL_tlp_tlpBRAM_read_FirstReq &&
tlp_tlpBRAM_mReqF_D_OUT[30:29] == 2'd2 &&
!tlp_tlpBRAM_mReqF_D_OUT[60] ;
assign MUX_bram_3_memory_a_put_1__SEL_1 =
WILL_FIRE_RL_tlp_tlpBRAM_writeData &&
SEL_ARR_NOT_tlp_tlpBRAM_writeRemainDWLen_52_EQ_ETC___d677 ;
assign MUX_bram_3_memory_a_put_1__SEL_2 =
WILL_FIRE_RL_tlp_tlpBRAM_writeReq &&
tlp_tlpBRAM_mReqF_D_OUT[51:50] == 2'd3 &&
!tlp_tlpBRAM_mReqF_D_OUT[63] ;
assign MUX_bram_3_memory_a_put_1__SEL_3 =
WILL_FIRE_RL_tlp_tlpBRAM_read_FirstReq &&
tlp_tlpBRAM_mReqF_D_OUT[30:29] == 2'd3 &&
!tlp_tlpBRAM_mReqF_D_OUT[60] ;
assign MUX_tlp_fabMesgAccu_write_1__SEL_1 =
WILL_FIRE_RL_tlp_dmaRespBodyFarMeta ||
WILL_FIRE_RL_tlp_dmaResponseNearMetaBody ;
assign MUX_tlp_fabMeta_write_1__SEL_2 =
WILL_FIRE_RL_tlp_dmaTailEventSender &&
(tlp_fabFlowAddrMS == 32'd0 || tlp_sentTail4DWHeader) ;
assign MUX_tlp_remDone_1_wset_1__SEL_1 =
WILL_FIRE_RL_tlp_dmaTailEventSender &&
(tlp_fabFlowAddrMS == 32'd0 && tlp_tailEventF_D_OUT ||
tlp_fabFlowAddrMS != 32'd0 && !tlp_sentTail4DWHeader &&
tlp_tailEventF_D_OUT) ;
assign MUX_tlp_tailEventF_enq_1__SEL_1 =
WILL_FIRE_RL_tlp_dmaXmtDoorbell ||
WILL_FIRE_RL_tlp_dmaXmtTailEvent ;
assign MUX_tlp_tlpBRAM_mReqF_enq_1__SEL_1 =
WILL_FIRE_RL_tlp_tlpRcv &&
tlp_inF_first__259_BIT_152_462_AND_NOT_tlp_inF_ETC___d1487 ;
assign MUX_tlp_tlpBRAM_mReqF_enq_1__SEL_2 =
WILL_FIRE_RL_tlp_dmaPullResponseBody ||
WILL_FIRE_RL_tlp_dmaRespBodyFarMeta ;
assign MUX_tlp_tlpBRAM_readHeaderSent_write_1__SEL_1 =
WILL_FIRE_RL_tlp_tlpBRAM_read_FirstResp &&
(tlp_tlpBRAM_readReq_D_OUT[28:19] != 10'd1 ||
tlp_tlpBRAM_readReq_D_OUT[60]) ;
assign MUX_tlp_tlpBRAM_readStarted_write_1__SEL_1 =
WILL_FIRE_RL_tlp_tlpBRAM_read_FirstReq &&
(tlp_tlpBRAM_mReqF_D_OUT[28:19] != 10'd1 ||
tlp_tlpBRAM_mReqF_D_OUT[60]) ;
assign MUX_tlp_tlpXmtBusy_write_1__SEL_1 =
WILL_FIRE_RL_tlp_dmaPushResponseHeader && _dfoo5 ;
assign MUX_tlp_tlpXmtBusy_write_1__PSEL_2 =
WILL_FIRE_RL_tlp_dataXmt_Body ||
WILL_FIRE_RL_tlp_dmaPushResponseBody ;
assign MUX_tlp_tlpXmtBusy_write_1__SEL_2 =
MUX_tlp_tlpXmtBusy_write_1__PSEL_2 &&
tlp_outDwRemain_129_ULE_4___d1130 ;
assign MUX_tlp_tlpXmtBusy_write_1__SEL_3 =
WILL_FIRE_RL_tlp_dmaTailEventSender &&
tlp_fabFlowAddrMS != 32'd0 ;
assign MUX_tlp_tlpXmtBusy_write_1__SEL_4 =
WILL_FIRE_RL_tlp_dataXmt_Header &&
!tlp_tlpBRAM_mRespF_first__000_BITS_71_TO_62_10_ETC___d1102 ;
assign MUX_tlp_xmtMetaOK_write_1__SEL_3 =
WILL_FIRE_RL_tlp_dmaPushResponseBody &&
tlp_outDwRemain_129_ULE_4___d1130 &&
tlp_tlpBRAM_mRespF_D_OUT[135:128] == 8'h01 ;
assign MUX_tlp_xmtMetaOK_write_1__SEL_4 =
WILL_FIRE_RL_tlp_dmaPushResponseHeader &&
tlp_fabMesgAddrMS == 32'd0 &&
tlp_tlpBRAM_mRespF_D_OUT[71:62] == 10'd1 &&
tlp_tlpBRAM_mRespF_D_OUT[42:35] == 8'h01 ;
assign MUX_wci_illegalEdge_write_1__SEL_1 =
WILL_FIRE_RL_wci_ctl_op_complete && wci_illegalEdge ;
assign MUX_wci_illegalEdge_write_1__SEL_2 =
WILL_FIRE_RL_wci_ctl_op_start &&
(wci_reqF_D_OUT[36:34] == 3'd0 && wci_cState != 3'd0 ||
wci_reqF_D_OUT[36:34] == 3'd1 && wci_cState != 3'd1 &&
wci_cState != 3'd3 ||
wci_reqF_D_OUT[36:34] == 3'd2 && wci_cState != 3'd2 ||
wci_reqF_D_OUT[36:34] == 3'd3 && wci_cState != 3'd3 &&
wci_cState != 3'd2 &&
wci_cState != 3'd1 ||
wci_reqF_D_OUT[36:34] == 3'd4 ||
wci_reqF_D_OUT[36:34] == 3'd5 ||
wci_reqF_D_OUT[36:34] == 3'd6 ||
wci_reqF_D_OUT[36:34] == 3'd7) ;
assign MUX_wci_respF_q_0_write_1__SEL_1 =
WILL_FIRE_RL_wci_respF_both && _dfoo3 ;
assign MUX_wci_respF_q_0_write_1__SEL_2 =
WILL_FIRE_RL_wci_respF_incCtr && wci_respF_cntr_r == 2'd0 ;
assign MUX_wci_respF_q_1_write_1__SEL_1 =
WILL_FIRE_RL_wci_respF_both && _dfoo1 ;
assign MUX_wci_respF_q_1_write_1__SEL_2 =
WILL_FIRE_RL_wci_respF_incCtr && wci_respF_cntr_r == 2'd1 ;
assign MUX_wmi_bufDwell_write_1__SEL_1 =
WILL_FIRE_RL_wmi_doReadReq && wmi_bytesRemainReq == 14'd16 &&
wmi_doneWithMesg ;
assign MUX_wmi_bytesRemainResp_write_1__SEL_1 =
WILL_FIRE_RL_wmi_getRequest &&
wmi_wmi_reqF_D_OUT[31:29] == 3'd2 ;
assign MUX_wmi_doneWithMesg_write_1__PSEL_1 =
WILL_FIRE_RL_wmi_doReadReq || WILL_FIRE_RL_wmi_doWriteReq ;
assign MUX_wmi_doneWithMesg_write_1__SEL_1 =
MUX_wmi_doneWithMesg_write_1__PSEL_1 &&
wmi_bytesRemainReq == 14'd16 &&
wmi_doneWithMesg ;
assign MUX_wmi_rdActive_write_1__SEL_1 =
WILL_FIRE_RL_wmi_doReadReq && wmi_bytesRemainReq == 14'd16 ;
assign MUX_wmi_wmi_dhF_levelsValid_write_1__SEL_2 =
wmi_wmi_dhF_FULL_N && wmi_wmi_operateD && wmi_wmi_peerIsReady &&
wmi_wmi_wmiDh_wget[145] ;
assign MUX_wmi_wmi_mFlagF_levelsValid_write_1__SEL_2 =
wmi_wmi_mFlagF_FULL_N && wmi_wmi_operateD &&
wmi_wmi_peerIsReady &&
wmi_wmi_wmiReq_wget[31:29] != 3'd0 &&
wmi_wmi_wmiReq_wget[27] ;
assign MUX_wmi_wmi_reqF_levelsValid_write_1__SEL_2 =
wmi_wmi_reqF_FULL_N && wmi_wmi_operateD && wmi_wmi_peerIsReady &&
wmi_wmi_wmiReq_wget[31:29] != 3'd0 ;
assign MUX_wmi_wmi_respF_q_0_write_1__SEL_1 =
WILL_FIRE_RL_wmi_wmi_respF_both && _dfoo9 ;
assign MUX_wmi_wmi_respF_q_0_write_1__SEL_2 =
WILL_FIRE_RL_wmi_wmi_respF_incCtr &&
wmi_wmi_respF_cntr_r == 2'd0 ;
assign MUX_wmi_wmi_respF_q_1_write_1__SEL_1 =
WILL_FIRE_RL_wmi_wmi_respF_both && _dfoo7 ;
assign MUX_wmi_wmi_respF_q_1_write_1__SEL_2 =
WILL_FIRE_RL_wmi_wmi_respF_incCtr &&
wmi_wmi_respF_cntr_r == 2'd1 ;
assign MUX_wmi_wrActive_write_1__SEL_1 =
WILL_FIRE_RL_wmi_doWriteReq && wmi_bytesRemainReq == 14'd16 ;
assign MUX_wmi_wrFinalize_write_1__SEL_1 =
WILL_FIRE_RL_wmi_doWriteReq && wmi_bytesRemainReq == 14'd16 &&
wmi_doneWithMesg ;
assign MUX_bml_crdBuf_value_write_1__VAL_3 =
bml_crdBuf_value_880_EQ_bml_crdBuf_modulus_bw__ETC___d1882 ?
16'd0 :
bml_crdBuf_value + 16'd1 ;
assign MUX_bml_fabBuf_value_write_1__VAL_3 =
bml_fabBuf_value_865_EQ_bml_fabBuf_modulus_bw__ETC___d1867 ?
16'd0 :
bml_fabBuf_value + 16'd1 ;
assign MUX_bml_fabBufsAvail_write_1__VAL_1 =
(bml_fabAvail && !bml_remStart) ? x__h90034 : x__h90039 ;
assign MUX_bml_fabBufsAvail_write_1__VAL_2 =
(dpControl[3:2] == 2'd1) ? x__h88675 : 16'd0 ;
assign MUX_bml_fabFlowAddr_write_1__VAL_1 =
bml_fabBuf_value_865_EQ_bml_fabBuf_modulus_bw__ETC___d1867 ?
bml_fabFlowBase :
bml_fabFlowAddr_937_PLUS_bml_fabFlowSize_938___d1939 ;
assign MUX_bml_fabFlowAddr_write_1__VAL_3 =
bml_crdBuf_value_880_EQ_bml_crdBuf_modulus_bw__ETC___d1882 ?
bml_fabFlowBase :
bml_fabFlowAddr_937_PLUS_bml_fabFlowSize_938___d1939 ;
assign MUX_bml_fabMesgAddr_write_1__VAL_1 =
bml_fabBuf_value_865_EQ_bml_fabBuf_modulus_bw__ETC___d1867 ?
bml_fabMesgBase :
bml_fabMesgAddr + bml_fabMesgSize ;
assign MUX_bml_fabMetaAddr_write_1__VAL_1 =
bml_fabBuf_value_865_EQ_bml_fabBuf_modulus_bw__ETC___d1867 ?
bml_fabMetaBase :
bml_fabMetaAddr + bml_fabMetaSize ;
assign MUX_bml_lclBuf_value_write_1__VAL_3 =
bml_lclBuf_value_835_EQ_bml_lclBuf_modulus_bw__ETC___d1837 ?
16'd0 :
bml_lclBuf_value + 16'd1 ;
assign MUX_bml_lclBufsAR_write_1__VAL_1 =
(CASE_dpControl_BITS_1_TO_0_0_bml_fabDone_1_bml_ETC__q4 &&
!bml_lclBufStart) ?
x__h89803 :
x__h89808 ;
assign MUX_bml_lclBufsAR_write_1__VAL_2 =
(dpControl[3:2] == 2'd1) ? bml_lclNumBufs : 16'd0 ;
assign MUX_bml_lclBufsCF_write_1__VAL_1 =
(bml_lclBufDone &&
CASE_dpControl_BITS_1_TO_0_0_NOT_bml_fabDone_1_ETC__q6) ?
x__h89915 :
x__h89952 ;
assign MUX_bml_lclBufsCF_write_1__VAL_2 =
(dpControl[3:2] == 2'd1) ? 16'd0 : bml_lclNumBufs ;
assign MUX_bml_lclCredit_write_1__VAL_1 =
(bml_lclBufDone && !bml_remStart) ? x__h90073 : x__h90078 ;
assign MUX_bml_lclMesgAddr_write_1__VAL_2 =
bml_lclBuf_value_835_EQ_bml_lclBuf_modulus_bw__ETC___d1837 ?
bml_mesgBase :
bml_lclMesgAddr + bml_mesgSize ;
assign MUX_bml_lclMetaAddr_write_1__VAL_2 =
bml_lclBuf_value_835_EQ_bml_lclBuf_modulus_bw__ETC___d1837 ?
bml_metaBase :
bml_lclMetaAddr + bml_metaSize ;
assign MUX_bml_remBuf_value_write_1__VAL_3 =
bml_remBuf_value_850_EQ_bml_remBuf_modulus_bw__ETC___d1852 ?
16'd0 :
bml_remBuf_value + 16'd1 ;
assign MUX_bml_remMesgAddr_write_1__VAL_2 =
bml_remBuf_value_850_EQ_bml_remBuf_modulus_bw__ETC___d1852 ?
bml_mesgBase :
bml_remMesgAddr + bml_mesgSize ;
assign MUX_bml_remMetaAddr_write_1__VAL_2 =
bml_remBuf_value_850_EQ_bml_remBuf_modulus_bw__ETC___d1852 ?
bml_metaBase :
bml_remMetaAddr + bml_metaSize ;
always@(idx__h21626 or
tlp_tlpBRAM_writeDWAddr or
tlp_tlpBRAM_writeDWAddr_PLUS_1__q8 or
tlp_tlpBRAM_writeDWAddr_PLUS_2__q9 or
tlp_tlpBRAM_writeDWAddr_PLUS_3__q10)
begin
case (idx__h21626)
2'd0: MUX_bram_0_memory_a_put_2__VAL_1 = tlp_tlpBRAM_writeDWAddr[12:2];
2'd1:
MUX_bram_0_memory_a_put_2__VAL_1 =
tlp_tlpBRAM_writeDWAddr_PLUS_1__q8[12:2];
2'd2:
MUX_bram_0_memory_a_put_2__VAL_1 =
tlp_tlpBRAM_writeDWAddr_PLUS_2__q9[12:2];
2'd3:
MUX_bram_0_memory_a_put_2__VAL_1 =
tlp_tlpBRAM_writeDWAddr_PLUS_3__q10[12:2];
endcase
end
always@(idx__h27879 or
tlp_tlpBRAM_readNxtDWAddr or
tlp_tlpBRAM_readNxtDWAddr_PLUS_1__q11 or
tlp_tlpBRAM_readNxtDWAddr_PLUS_2__q12 or
tlp_tlpBRAM_readNxtDWAddr_PLUS_3__q13)
begin
case (idx__h27879)
2'd0:
MUX_bram_0_memory_a_put_2__VAL_4 = tlp_tlpBRAM_readNxtDWAddr[12:2];
2'd1:
MUX_bram_0_memory_a_put_2__VAL_4 =
tlp_tlpBRAM_readNxtDWAddr_PLUS_1__q11[12:2];
2'd2:
MUX_bram_0_memory_a_put_2__VAL_4 =
tlp_tlpBRAM_readNxtDWAddr_PLUS_2__q12[12:2];
2'd3:
MUX_bram_0_memory_a_put_2__VAL_4 =
tlp_tlpBRAM_readNxtDWAddr_PLUS_3__q13[12:2];
endcase
end
assign MUX_bram_0_memory_a_put_3__VAL_1 =
{ SEL_ARR_tlp_tlpBRAM_mReqF_first__16_BITS_127_T_ETC___d700[7:0],
SEL_ARR_tlp_tlpBRAM_mReqF_first__16_BITS_127_T_ETC___d700[15:8],
SEL_ARR_tlp_tlpBRAM_mReqF_first__16_BITS_127_T_ETC___d700[23:16],
SEL_ARR_tlp_tlpBRAM_mReqF_first__16_BITS_127_T_ETC___d700[31:24] } ;
assign MUX_bram_0_memory_a_put_3__VAL_2 =
{ tlp_tlpBRAM_mReqF_D_OUT[7:0],
tlp_tlpBRAM_mReqF_D_OUT[15:8],
tlp_tlpBRAM_mReqF_D_OUT[23:16],
tlp_tlpBRAM_mReqF_D_OUT[31:24] } ;
assign MUX_bram_0_memory_b_put_2__VAL_2 =
wmi_lclMesgAddr[14:4] + { 1'd0, wmi_addr[13:4] } ;
always@(idx__h23676 or
tlp_tlpBRAM_writeDWAddr or
tlp_tlpBRAM_writeDWAddr_PLUS_1__q8 or
tlp_tlpBRAM_writeDWAddr_PLUS_2__q9 or
tlp_tlpBRAM_writeDWAddr_PLUS_3__q10)
begin
case (idx__h23676)
2'd0: MUX_bram_1_memory_a_put_2__VAL_1 = tlp_tlpBRAM_writeDWAddr[12:2];
2'd1:
MUX_bram_1_memory_a_put_2__VAL_1 =
tlp_tlpBRAM_writeDWAddr_PLUS_1__q8[12:2];
2'd2:
MUX_bram_1_memory_a_put_2__VAL_1 =
tlp_tlpBRAM_writeDWAddr_PLUS_2__q9[12:2];
2'd3:
MUX_bram_1_memory_a_put_2__VAL_1 =
tlp_tlpBRAM_writeDWAddr_PLUS_3__q10[12:2];
endcase
end
always@(idx__h28282 or
tlp_tlpBRAM_readNxtDWAddr or
tlp_tlpBRAM_readNxtDWAddr_PLUS_1__q11 or
tlp_tlpBRAM_readNxtDWAddr_PLUS_2__q12 or
tlp_tlpBRAM_readNxtDWAddr_PLUS_3__q13)
begin
case (idx__h28282)
2'd0:
MUX_bram_1_memory_a_put_2__VAL_4 = tlp_tlpBRAM_readNxtDWAddr[12:2];
2'd1:
MUX_bram_1_memory_a_put_2__VAL_4 =
tlp_tlpBRAM_readNxtDWAddr_PLUS_1__q11[12:2];
2'd2:
MUX_bram_1_memory_a_put_2__VAL_4 =
tlp_tlpBRAM_readNxtDWAddr_PLUS_2__q12[12:2];
2'd3:
MUX_bram_1_memory_a_put_2__VAL_4 =
tlp_tlpBRAM_readNxtDWAddr_PLUS_3__q13[12:2];
endcase
end
assign MUX_bram_1_memory_a_put_3__VAL_1 =
{ SEL_ARR_tlp_tlpBRAM_mReqF_first__16_BITS_127_T_ETC___d708[7:0],
SEL_ARR_tlp_tlpBRAM_mReqF_first__16_BITS_127_T_ETC___d708[15:8],
SEL_ARR_tlp_tlpBRAM_mReqF_first__16_BITS_127_T_ETC___d708[23:16],
SEL_ARR_tlp_tlpBRAM_mReqF_first__16_BITS_127_T_ETC___d708[31:24] } ;
always@(idx__h24781 or
tlp_tlpBRAM_writeDWAddr or
tlp_tlpBRAM_writeDWAddr_PLUS_1__q8 or
tlp_tlpBRAM_writeDWAddr_PLUS_2__q9 or
tlp_tlpBRAM_writeDWAddr_PLUS_3__q10)
begin
case (idx__h24781)
2'd0: MUX_bram_2_memory_a_put_2__VAL_1 = tlp_tlpBRAM_writeDWAddr[12:2];
2'd1:
MUX_bram_2_memory_a_put_2__VAL_1 =
tlp_tlpBRAM_writeDWAddr_PLUS_1__q8[12:2];
2'd2:
MUX_bram_2_memory_a_put_2__VAL_1 =
tlp_tlpBRAM_writeDWAddr_PLUS_2__q9[12:2];
2'd3:
MUX_bram_2_memory_a_put_2__VAL_1 =
tlp_tlpBRAM_writeDWAddr_PLUS_3__q10[12:2];
endcase
end
always@(idx__h28586 or
tlp_tlpBRAM_readNxtDWAddr or
tlp_tlpBRAM_readNxtDWAddr_PLUS_1__q11 or
tlp_tlpBRAM_readNxtDWAddr_PLUS_2__q12 or
tlp_tlpBRAM_readNxtDWAddr_PLUS_3__q13)
begin
case (idx__h28586)
2'd0:
MUX_bram_2_memory_a_put_2__VAL_4 = tlp_tlpBRAM_readNxtDWAddr[12:2];
2'd1:
MUX_bram_2_memory_a_put_2__VAL_4 =
tlp_tlpBRAM_readNxtDWAddr_PLUS_1__q11[12:2];
2'd2:
MUX_bram_2_memory_a_put_2__VAL_4 =
tlp_tlpBRAM_readNxtDWAddr_PLUS_2__q12[12:2];
2'd3:
MUX_bram_2_memory_a_put_2__VAL_4 =
tlp_tlpBRAM_readNxtDWAddr_PLUS_3__q13[12:2];
endcase
end
assign MUX_bram_2_memory_a_put_3__VAL_1 =
{ SEL_ARR_tlp_tlpBRAM_mReqF_first__16_BITS_127_T_ETC___d716[7:0],
SEL_ARR_tlp_tlpBRAM_mReqF_first__16_BITS_127_T_ETC___d716[15:8],
SEL_ARR_tlp_tlpBRAM_mReqF_first__16_BITS_127_T_ETC___d716[23:16],
SEL_ARR_tlp_tlpBRAM_mReqF_first__16_BITS_127_T_ETC___d716[31:24] } ;
always@(idx__h25886 or
tlp_tlpBRAM_writeDWAddr or
tlp_tlpBRAM_writeDWAddr_PLUS_1__q8 or
tlp_tlpBRAM_writeDWAddr_PLUS_2__q9 or
tlp_tlpBRAM_writeDWAddr_PLUS_3__q10)
begin
case (idx__h25886)
2'd0: MUX_bram_3_memory_a_put_2__VAL_1 = tlp_tlpBRAM_writeDWAddr[12:2];
2'd1:
MUX_bram_3_memory_a_put_2__VAL_1 =
tlp_tlpBRAM_writeDWAddr_PLUS_1__q8[12:2];
2'd2:
MUX_bram_3_memory_a_put_2__VAL_1 =
tlp_tlpBRAM_writeDWAddr_PLUS_2__q9[12:2];
2'd3:
MUX_bram_3_memory_a_put_2__VAL_1 =
tlp_tlpBRAM_writeDWAddr_PLUS_3__q10[12:2];
endcase
end
always@(idx__h28890 or
tlp_tlpBRAM_readNxtDWAddr or
tlp_tlpBRAM_readNxtDWAddr_PLUS_1__q11 or
tlp_tlpBRAM_readNxtDWAddr_PLUS_2__q12 or
tlp_tlpBRAM_readNxtDWAddr_PLUS_3__q13)
begin
case (idx__h28890)
2'd0:
MUX_bram_3_memory_a_put_2__VAL_4 = tlp_tlpBRAM_readNxtDWAddr[12:2];
2'd1:
MUX_bram_3_memory_a_put_2__VAL_4 =
tlp_tlpBRAM_readNxtDWAddr_PLUS_1__q11[12:2];
2'd2:
MUX_bram_3_memory_a_put_2__VAL_4 =
tlp_tlpBRAM_readNxtDWAddr_PLUS_2__q12[12:2];
2'd3:
MUX_bram_3_memory_a_put_2__VAL_4 =
tlp_tlpBRAM_readNxtDWAddr_PLUS_3__q13[12:2];
endcase
end
assign MUX_bram_3_memory_a_put_3__VAL_1 =
{ SEL_ARR_tlp_tlpBRAM_mReqF_first__16_BITS_127_T_ETC___d724[7:0],
SEL_ARR_tlp_tlpBRAM_mReqF_first__16_BITS_127_T_ETC___d724[15:8],
SEL_ARR_tlp_tlpBRAM_mReqF_first__16_BITS_127_T_ETC___d724[23:16],
SEL_ARR_tlp_tlpBRAM_mReqF_first__16_BITS_127_T_ETC___d724[31:24] } ;
assign MUX_tlp_dmaDoTailEvent_write_1__VAL_1 =
tlp_dmaPullRemainDWSub_387_ULE_4___d1388 &&
tlp_dmaPullRemainDWLen_373_ULE_tlp_dmaPullRema_ETC___d1395 ;
assign MUX_tlp_dmaPullRemainDWLen_write_1__VAL_2 =
tlp_dmaPullRemainDWLen - 10'd1 ;
assign MUX_tlp_dmaPullRemainDWLen_write_1__VAL_3 =
tlp_dmaPullRemainDWSub_387_ULE_4___d1388 ?
tlp_dmaPullRemainDWLen - tlp_dmaPullRemainDWSub :
tlp_dmaPullRemainDWLen - 10'd4 ;
assign MUX_tlp_dmaPullRemainDWSub_write_1__VAL_1 =
tlp_inF_D_OUT[105:96] - 10'd1 ;
assign MUX_tlp_dmaPullRemainDWSub_write_1__VAL_2 =
tlp_dmaPullRemainDWSub_387_ULE_4___d1388 ?
10'd0 :
tlp_dmaPullRemainDWSub - 10'd4 ;
assign MUX_tlp_doorSeqDwell_write_1__VAL_1 = tlp_doorSeqDwell - 4'd1 ;
assign MUX_tlp_fabMesgAccu_write_1__VAL_2 = tlp_fabMesgAccu + y__h48181 ;
assign MUX_tlp_fabMesgAccu_write_1__VAL_3 = tlp_fabMesgAccu + y__h63989 ;
assign MUX_tlp_fabMeta_write_1__VAL_1 =
{ 1'd1,
x__h47258,
opcode__h44022,
nowMS__h45280,
nowLS__h46239 } ;
assign MUX_tlp_fabMeta_write_1__VAL_3 =
{ 1'd1,
x__h63608,
opcode__h60417,
nowMS__h61665,
nowLS__h62622 } ;
assign MUX_tlp_lastRuleFired_write_1__VAL_3 =
(tlp_fabFlowAddrMS == 32'd0) ?
4'd8 :
(tlp_sentTail4DWHeader ? 4'd10 : 4'd9) ;
assign MUX_tlp_mesgComplReceived_write_1__VAL_1 =
tlp_mesgComplReceived + 17'd4 ;
assign MUX_tlp_mesgComplReceived_write_1__VAL_2 =
tlp_mesgComplReceived + y__h65310 ;
assign MUX_tlp_mesgLengthRemainPull_write_1__VAL_1 =
{ tlp_inF_D_OUT[8],
tlp_inF_D_OUT[23:16],
tlp_inF_D_OUT[31:24] } ;
assign MUX_tlp_mesgLengthRemainPull_write_1__VAL_2 =
{ tlp_mesgLengthRemainPull_PLUS_3__q14[16:2], 2'd0 } ;
assign MUX_tlp_mesgLengthRemainPull_write_1__VAL_3 =
tlp_mesgLengthRemainPull - y__h63918 ;
assign MUX_tlp_mesgLengthRemainPush_write_1__VAL_1 =
{ tlp_mesgLengthRemainPush_PLUS_3__q15[16:2], 2'd0 } ;
assign MUX_tlp_mesgLengthRemainPush_write_1__VAL_2 =
{ tlp_tlpBRAM_mRespF_D_OUT[8],
tlp_tlpBRAM_mRespF_D_OUT[23:16],
tlp_tlpBRAM_mRespF_D_OUT[31:24] } ;
assign MUX_tlp_mesgLengthRemainPush_write_1__VAL_3 =
tlp_mesgLengthRemainPush - y__h47529 ;
assign MUX_tlp_outDwRemain_write_1__VAL_1 =
tlp_tlpBRAM_mRespF_D_OUT[71:62] - y__h48147 ;
assign MUX_tlp_outDwRemain_write_1__VAL_2 = tlp_outDwRemain - 10'd4 ;
assign MUX_tlp_outDwRemain_write_1__VAL_3 =
tlp_tlpBRAM_mRespF_D_OUT[71:62] - 10'd1 ;
assign MUX_tlp_outF_enq_1__VAL_1 =
{ 1'd0,
tlp_outDwRemain_129_ULE_4___d1130,
7'h02,
w_be__h48508,
tlp_tlpBRAM_mRespF_D_OUT[127:0] } ;
assign MUX_tlp_outF_enq_1__VAL_2 =
(tlp_fabMesgAddrMS == 32'd0) ?
{ 1'd1,
tlp_tlpBRAM_mRespF_D_OUT[71:62] == 10'd1,
23'd196607,
w_data__h47916 } :
{ 25'd16973823, w_data__h48052 } ;
assign MUX_tlp_outF_enq_1__VAL_3 =
{ 25'd16973823,
(tlp_fabMetaAddrMS == 32'd0) ? 32'd1073741828 : 32'd1610612740,
pciDevice,
16'd255,
(tlp_fabMetaAddrMS == 32'd0) ?
{ tlp_fabMetaAddr,
tlp_fabMeta[103:96],
tlp_fabMeta[111:104],
tlp_fabMeta[119:112],
tlp_fabMeta[127:120] } :
{ tlp_fabMetaAddrMS, tlp_fabMetaAddr } } ;
assign MUX_tlp_outF_enq_1__VAL_4 =
(tlp_fabMetaAddrMS == 32'd0) ?
{ 25'd8585200,
tlp_fabMeta[71:64],
tlp_fabMeta[79:72],
tlp_fabMeta[87:80],
tlp_fabMeta[95:88],
tlp_fabMeta[39:32],
tlp_fabMeta[47:40],
tlp_fabMeta[55:48],
tlp_fabMeta[63:56],
tlp_fabMeta[7:0],
tlp_fabMeta[15:8],
tlp_fabMeta[23:16],
tlp_fabMeta[31:24],
tlp_fabMetaAddrMS } :
{ 25'd8585215, w_data__h52877 } ;
assign MUX_tlp_outF_enq_1__VAL_5 =
{ 9'd386,
(tlp_fabMetaAddrMS == 32'd0) ? 16'hFFF0 : 16'd65535,
IF_tlp_fabMetaAddrMS_157_EQ_0_158_THEN_4_ELSE__ETC___d1248 } ;
assign MUX_tlp_outF_enq_1__VAL_6 =
{ 9'd386,
(tlp_fabMesgAddrMS == 32'd0) ? 16'hFFF0 : 16'd65535,
IF_tlp_fabMesgAddrMS_078_EQ_0_079_THEN_0_ELSE__ETC___d1353 } ;
assign MUX_tlp_outF_enq_1__VAL_7 =
(tlp_fabFlowAddrMS == 32'd0) ?
{ 25'd25362431, w_data__h65836 } :
(tlp_sentTail4DWHeader ?
{ 25'd8581120, w_data__h67186 } :
{ 25'd16973823, w_data__h66940 }) ;
assign MUX_tlp_outF_enq_1__VAL_8 =
{ 1'd1,
tlp_tlpBRAM_mRespF_D_OUT[71:62] == 10'd1,
23'd196607,
pkt__h71785 } ;
assign MUX_tlp_postSeqDwell_write_1__VAL_1 =
(dpControl[1:0] == 2'd2) ? 4'd8 : 4'd4 ;
assign MUX_tlp_postSeqDwell_write_1__VAL_2 = tlp_postSeqDwell - 4'd1 ;
assign MUX_tlp_remMesgAccu_write_1__VAL_2 = tlp_remMesgAccu + y__h47671 ;
assign MUX_tlp_remMesgAccu_write_1__VAL_3 = tlp_remMesgAccu + y__h64598 ;
assign MUX_tlp_reqMesgInFlight_write_1__VAL_2 =
!tlp_dmaPullRemainDWSub_387_ULE_4___d1388 ||
!tlp_dmaPullRemainDWLen_373_ULE_tlp_dmaPullRema_ETC___d1395 ;
assign MUX_tlp_srcMesgAccu_write_1__VAL_2 = tlp_srcMesgAccu + y__h47623 ;
assign MUX_tlp_tlpBRAM_mReqF_enq_1__VAL_1 =
tlp_inF_D_OUT[152] ?
(tlp_inF_D_OUT[126] ?
{ 67'h15555555555555554,
tlp_inF_D_OUT[46:34],
tlp_inF_D_OUT[105:96],
tlp_inF_D_OUT[67:64],
tlp_inF_D_OUT[71:68],
tlp_inF_D_OUT[31:0] } :
{ 72'h955555555555555551,
tlp_inF_D_OUT[95:80],
tlp_inF_D_OUT[46:34],
tlp_inF_D_OUT[105:96],
tlp_inF_D_OUT[67:64],
tlp_inF_D_OUT[71:68],
tlp_inF_D_OUT[79:72],
tlp_inF_D_OUT[118:116] }) :
{ 2'd1, tlp_inF_D_OUT[127:0] } ;
assign MUX_tlp_tlpBRAM_mReqF_enq_1__VAL_2 = { 2'd1, tlp_inF_D_OUT[127:0] } ;
assign MUX_tlp_tlpBRAM_mReqF_enq_1__VAL_3 =
{ 88'h955555555555555553FFF8,
tlp_remMetaAddr[14:2],
29'd2620074 } ;
assign MUX_tlp_tlpBRAM_mReqF_enq_1__VAL_4 =
{ 69'h12AAAAAAAAAAAAAAAA,
tlp_fabMesgAddrMS != 32'd0,
18'd196600,
tlp_remMesgAccu[14:2],
thisRequestLength__h47504[11:2],
8'd255,
rreq_tag__h47719,
3'h2 } ;
assign MUX_tlp_tlpBRAM_mReqF_enq_1__VAL_5 =
{ 67'h15555555555555554,
tlp_remMetaAddr[14:2],
18'd1279,
tlp_inF_D_OUT[31:0] } ;
assign MUX_tlp_tlpBRAM_mReqF_enq_1__VAL_6 =
{ 67'h15555555555555554,
tlp_remMesgAccu[14:2],
tlp_inF_D_OUT[105:96],
8'd255,
tlp_inF_D_OUT[31:0] } ;
assign MUX_tlp_tlpBRAM_mRespF_enq_1__VAL_1 =
{ 48'h2AAAAAAAAAAA,
!tlp_tlpBRAM_readReq_D_OUT[60],
tlp_tlpBRAM_readReq_D_OUT[59:42],
tlp_tlpBRAM_readReq_D_OUT[28:19],
lowAddr__h29652,
byteCount__h29653,
tlp_tlpBRAM_readReq_D_OUT[10:0],
rresp_data__h29698 } ;
assign MUX_tlp_tlpBRAM_mRespF_enq_1__VAL_2 =
{ 1'd1,
tlp_tlpBRAM_readReq_D_OUT[59:58],
tlp_tlpBRAM_readReq_D_OUT[10:3],
rdata__h35173 } ;
assign MUX_tlp_tlpBRAM_rdRespDwRemain_write_1__VAL_1 =
tlp_tlpBRAM_readReq_D_OUT[28:19] - y__h30729 ;
assign MUX_tlp_tlpBRAM_rdRespDwRemain_write_1__VAL_2 =
tlp_tlpBRAM_rdRespDwRemain - 10'd4 ;
assign MUX_tlp_tlpBRAM_readNxtDWAddr_write_1__VAL_1 =
tlp_tlpBRAM_mReqF_D_OUT[41:29] + y__h27665 ;
assign MUX_tlp_tlpBRAM_readNxtDWAddr_write_1__VAL_2 =
tlp_tlpBRAM_readNxtDWAddr + 13'd4 ;
assign MUX_tlp_tlpBRAM_readRemainDWLen_write_1__VAL_1 =
tlp_tlpBRAM_mReqF_D_OUT[28:19] - y__h27653 ;
assign MUX_tlp_tlpBRAM_readRemainDWLen_write_1__VAL_2 =
tlp_tlpBRAM_readRemainDWLen - 10'd4 ;
assign MUX_tlp_tlpBRAM_writeDWAddr_write_1__VAL_1 =
tlp_tlpBRAM_mReqF_D_OUT[62:50] + y__h17362 ;
assign MUX_tlp_tlpBRAM_writeDWAddr_write_1__VAL_2 =
tlp_tlpBRAM_writeDWAddr + 13'd4 ;
assign MUX_tlp_tlpBRAM_writeRemainDWLen_write_1__VAL_1 =
tlp_tlpBRAM_mReqF_D_OUT[49:40] - y__h17428 ;
assign MUX_tlp_tlpBRAM_writeRemainDWLen_write_1__VAL_2 =
tlp_tlpBRAM_writeRemainDWLen - 10'd4 ;
assign MUX_tlp_tlpXmtBusy_write_1__VAL_1 =
tlp_fabMesgAddrMS != 32'd0 ||
tlp_tlpBRAM_mRespF_D_OUT[71:62] != 10'd1 ;
assign MUX_wci_illegalEdge_write_1__VAL_2 =
wci_reqF_D_OUT[36:34] != 3'd4 && wci_reqF_D_OUT[36:34] != 3'd5 &&
wci_reqF_D_OUT[36:34] != 3'd6 ;
assign MUX_wci_respF_cntr_r_write_1__VAL_2 = wci_respF_cntr_r + 2'd1 ;
assign MUX_wci_respF_q_0_write_1__VAL_1 =
(wci_respF_cntr_r == 2'd1) ?
MUX_wci_respF_q_0_write_1__VAL_2 :
wci_respF_q_1 ;
always@(WILL_FIRE_RL_wci_ctl_op_complete or
MUX_wci_respF_x_wire_wset_1__VAL_1 or
WILL_FIRE_RL_wci_cfrd or
MUX_wci_respF_x_wire_wset_1__VAL_2 or WILL_FIRE_RL_wci_cfwr)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_wci_ctl_op_complete:
MUX_wci_respF_q_0_write_1__VAL_2 =
MUX_wci_respF_x_wire_wset_1__VAL_1;
WILL_FIRE_RL_wci_cfrd:
MUX_wci_respF_q_0_write_1__VAL_2 =
MUX_wci_respF_x_wire_wset_1__VAL_2;
WILL_FIRE_RL_wci_cfwr: MUX_wci_respF_q_0_write_1__VAL_2 = 34'h1C0DE4201;
default: MUX_wci_respF_q_0_write_1__VAL_2 =
34'h2AAAAAAAA /* unspecified value */ ;
endcase
end
assign MUX_wci_respF_q_1_write_1__VAL_1 =
(wci_respF_cntr_r == 2'd2) ?
MUX_wci_respF_q_0_write_1__VAL_2 :
34'h0AAAAAAAA ;
assign MUX_wci_respF_x_wire_wset_1__VAL_1 =
wci_illegalEdge ? 34'h3C0DE4202 : 34'h1C0DE4201 ;
assign MUX_wci_respF_x_wire_wset_1__VAL_2 = { 2'd1, _theResult____h91947 } ;
assign MUX_wmi_addr_write_1__VAL_1 = wmi_addr + 14'd16 ;
assign MUX_wmi_bufDwell_write_1__VAL_3 = wmi_bufDwell - 2'd1 ;
assign MUX_wmi_bytesRemainReq_write_1__VAL_1 = wmi_bytesRemainReq - 14'd16 ;
assign MUX_wmi_bytesRemainReq_write_1__VAL_2 =
{ wmi_wmi_reqF_D_OUT[9:0], 4'd0 } ;
assign MUX_wmi_bytesRemainResp_write_1__VAL_2 =
wmi_bytesRemainResp - 14'd16 ;
assign MUX_wmi_mesgCount_write_1__VAL_1 = wmi_mesgCount + 32'd1 ;
assign MUX_wmi_mesgMeta_write_1__VAL_2 =
{ 1'd1,
bram_0_serverAdapterB_outData_outData_wget,
bram_1_serverAdapterB_outData_outData_wget,
bram_2_serverAdapterB_outData_outData_wget,
bram_3_serverAdapterB_outData_outData_wget } ;
assign MUX_wmi_wmi_respF_cntr_r_write_1__VAL_2 =
wmi_wmi_respF_cntr_r + 2'd1 ;
assign MUX_wmi_wmi_respF_q_0_write_1__VAL_1 =
(wmi_wmi_respF_cntr_r == 2'd1) ?
MUX_wmi_wmi_respF_q_0_write_1__VAL_2 :
wmi_wmi_respF_q_1 ;
assign MUX_wmi_wmi_respF_q_0_write_1__VAL_2 = { 2'd1, rdata__h83703 } ;
assign MUX_wmi_wmi_respF_q_1_write_1__VAL_1 =
(wmi_wmi_respF_cntr_r == 2'd2) ?
MUX_wmi_wmi_respF_q_0_write_1__VAL_2 :
130'd0 ;
// inlined wires
assign bram_0_serverAdapterA_outData_enqData_wget = bram_0_memory_DOA ;
assign bram_0_serverAdapterA_outData_enqData_whas =
(!bram_0_serverAdapterA_s1[0] ||
bram_0_serverAdapterA_outDataCore_FULL_N) &&
bram_0_serverAdapterA_s1[1] &&
bram_0_serverAdapterA_s1[0] ;
assign bram_0_serverAdapterA_outData_outData_wget =
bram_0_serverAdapterA_outDataCore_EMPTY_N ?
bram_0_serverAdapterA_outDataCore_D_OUT :
bram_0_memory_DOA ;
assign bram_0_serverAdapterA_outData_outData_whas =
bram_0_serverAdapterA_outDataCore_EMPTY_N ||
!bram_0_serverAdapterA_outDataCore_EMPTY_N &&
bram_0_serverAdapterA_outData_enqData_whas ;
assign bram_0_serverAdapterA_cnt_1_wget = 3'd1 ;
assign bram_0_serverAdapterA_cnt_1_whas =
(MUX_bram_0_memory_a_put_1__SEL_1 ||
MUX_bram_0_memory_a_put_1__SEL_2 ||
MUX_bram_0_memory_a_put_1__SEL_3 ||
WILL_FIRE_RL_tlp_tlpBRAM_read_NextReq) &&
(!ab__h1619[1] || ab__h1619[0]) ;
assign bram_0_serverAdapterA_cnt_2_wget = 3'd7 ;
assign bram_0_serverAdapterA_cnt_2_whas =
bram_0_serverAdapterA_outData_deqCalled_whas ;
assign bram_0_serverAdapterA_cnt_3_wget = 3'h0 ;
assign bram_0_serverAdapterA_cnt_3_whas = 1'b0 ;
assign bram_0_serverAdapterA_writeWithResp_wget = ab__h1619 ;
assign bram_0_serverAdapterA_writeWithResp_whas =
MUX_bram_0_memory_a_put_1__SEL_1 ||
MUX_bram_0_memory_a_put_1__SEL_2 ||
MUX_bram_0_memory_a_put_1__SEL_3 ||
WILL_FIRE_RL_tlp_tlpBRAM_read_NextReq ;
assign bram_0_serverAdapterA_s1_1_wget =
{ 1'd1, !ab__h1619[1] || ab__h1619[0] } ;
assign bram_0_serverAdapterA_s1_1_whas =
bram_0_serverAdapterA_writeWithResp_whas ;
assign bram_0_serverAdapterB_outData_enqData_wget = bram_0_memory_DOB ;
assign bram_0_serverAdapterB_outData_enqData_whas =
(!bram_0_serverAdapterB_s1[0] ||
bram_0_serverAdapterB_outDataCore_FULL_N) &&
bram_0_serverAdapterB_s1[1] &&
bram_0_serverAdapterB_s1[0] ;
assign bram_0_serverAdapterB_outData_outData_wget =
bram_0_serverAdapterB_outDataCore_EMPTY_N ?
bram_0_serverAdapterB_outDataCore_D_OUT :
bram_0_memory_DOB ;
assign bram_0_serverAdapterB_outData_outData_whas =
bram_0_serverAdapterB_outDataCore_EMPTY_N ||
!bram_0_serverAdapterB_outDataCore_EMPTY_N &&
bram_0_serverAdapterB_outData_enqData_whas ;
assign bram_0_serverAdapterB_cnt_1_wget = 3'd1 ;
assign bram_0_serverAdapterB_cnt_1_whas =
(WILL_FIRE_RL_wmi_reqMetadata || WILL_FIRE_RL_wmi_doReadReq ||
WILL_FIRE_RL_wmi_doWriteReq ||
WILL_FIRE_RL_wmi_doWriteFinalize) &&
(!ab__h3026[1] || ab__h3026[0]) ;
assign bram_0_serverAdapterB_cnt_2_wget = 3'd7 ;
assign bram_0_serverAdapterB_cnt_2_whas =
bram_0_serverAdapterB_outData_deqCalled_whas ;
assign bram_0_serverAdapterB_cnt_3_wget = 3'h0 ;
assign bram_0_serverAdapterB_cnt_3_whas = 1'b0 ;
assign bram_0_serverAdapterB_writeWithResp_wget = ab__h3026 ;
assign bram_0_serverAdapterB_writeWithResp_whas =
WILL_FIRE_RL_wmi_reqMetadata || WILL_FIRE_RL_wmi_doReadReq ||
WILL_FIRE_RL_wmi_doWriteReq ||
WILL_FIRE_RL_wmi_doWriteFinalize ;
assign bram_0_serverAdapterB_s1_1_wget =
{ 1'd1, !ab__h3026[1] || ab__h3026[0] } ;
assign bram_0_serverAdapterB_s1_1_whas =
bram_0_serverAdapterB_writeWithResp_whas ;
assign bram_1_serverAdapterA_outData_enqData_wget = bram_1_memory_DOA ;
assign bram_1_serverAdapterA_outData_enqData_whas =
(!bram_1_serverAdapterA_s1[0] ||
bram_1_serverAdapterA_outDataCore_FULL_N) &&
bram_1_serverAdapterA_s1[1] &&
bram_1_serverAdapterA_s1[0] ;
assign bram_1_serverAdapterA_outData_outData_wget =
bram_1_serverAdapterA_outDataCore_EMPTY_N ?
bram_1_serverAdapterA_outDataCore_D_OUT :
bram_1_memory_DOA ;
assign bram_1_serverAdapterA_outData_outData_whas =
bram_1_serverAdapterA_outDataCore_EMPTY_N ||
!bram_1_serverAdapterA_outDataCore_EMPTY_N &&
bram_1_serverAdapterA_outData_enqData_whas ;
assign bram_1_serverAdapterA_cnt_1_wget = 3'd1 ;
assign bram_1_serverAdapterA_cnt_1_whas =
(MUX_bram_1_memory_a_put_1__SEL_1 ||
MUX_bram_1_memory_a_put_1__SEL_2 ||
MUX_bram_1_memory_a_put_1__SEL_3 ||
WILL_FIRE_RL_tlp_tlpBRAM_read_NextReq) &&
(!ab__h4569[1] || ab__h4569[0]) ;
assign bram_1_serverAdapterA_cnt_2_wget = 3'd7 ;
assign bram_1_serverAdapterA_cnt_2_whas =
bram_1_serverAdapterA_outData_deqCalled_whas ;
assign bram_1_serverAdapterA_cnt_3_wget = 3'h0 ;
assign bram_1_serverAdapterA_cnt_3_whas = 1'b0 ;
assign bram_1_serverAdapterA_writeWithResp_wget = ab__h4569 ;
assign bram_1_serverAdapterA_writeWithResp_whas =
MUX_bram_1_memory_a_put_1__SEL_1 ||
MUX_bram_1_memory_a_put_1__SEL_2 ||
MUX_bram_1_memory_a_put_1__SEL_3 ||
WILL_FIRE_RL_tlp_tlpBRAM_read_NextReq ;
assign bram_1_serverAdapterA_s1_1_wget =
{ 1'd1, !ab__h4569[1] || ab__h4569[0] } ;
assign bram_1_serverAdapterA_s1_1_whas =
bram_1_serverAdapterA_writeWithResp_whas ;
assign bram_1_serverAdapterB_outData_enqData_wget = bram_1_memory_DOB ;
assign bram_1_serverAdapterB_outData_enqData_whas =
(!bram_1_serverAdapterB_s1[0] ||
bram_1_serverAdapterB_outDataCore_FULL_N) &&
bram_1_serverAdapterB_s1[1] &&
bram_1_serverAdapterB_s1[0] ;
assign bram_1_serverAdapterB_outData_outData_wget =
bram_1_serverAdapterB_outDataCore_EMPTY_N ?
bram_1_serverAdapterB_outDataCore_D_OUT :
bram_1_memory_DOB ;
assign bram_1_serverAdapterB_outData_outData_whas =
bram_1_serverAdapterB_outDataCore_EMPTY_N ||
!bram_1_serverAdapterB_outDataCore_EMPTY_N &&
bram_1_serverAdapterB_outData_enqData_whas ;
assign bram_1_serverAdapterB_cnt_1_wget = 3'd1 ;
assign bram_1_serverAdapterB_cnt_1_whas =
(WILL_FIRE_RL_wmi_reqMetadata || WILL_FIRE_RL_wmi_doReadReq ||
WILL_FIRE_RL_wmi_doWriteReq ||
WILL_FIRE_RL_wmi_doWriteFinalize) &&
(!ab__h5974[1] || ab__h5974[0]) ;
assign bram_1_serverAdapterB_cnt_2_wget = 3'd7 ;
assign bram_1_serverAdapterB_cnt_2_whas =
bram_0_serverAdapterB_outData_deqCalled_whas ;
assign bram_1_serverAdapterB_cnt_3_wget = 3'h0 ;
assign bram_1_serverAdapterB_cnt_3_whas = 1'b0 ;
assign bram_1_serverAdapterB_writeWithResp_wget = ab__h5974 ;
assign bram_1_serverAdapterB_writeWithResp_whas =
bram_0_serverAdapterB_writeWithResp_whas ;
assign bram_1_serverAdapterB_s1_1_wget =
{ 1'd1, !ab__h5974[1] || ab__h5974[0] } ;
assign bram_1_serverAdapterB_s1_1_whas =
bram_0_serverAdapterB_writeWithResp_whas ;
assign bram_2_serverAdapterA_outData_enqData_wget = bram_2_memory_DOA ;
assign bram_2_serverAdapterA_outData_enqData_whas =
(!bram_2_serverAdapterA_s1[0] ||
bram_2_serverAdapterA_outDataCore_FULL_N) &&
bram_2_serverAdapterA_s1[1] &&
bram_2_serverAdapterA_s1[0] ;
assign bram_2_serverAdapterA_outData_outData_wget =
WILL_FIRE_RL_bram_2_serverAdapterA_outData_setFirstEnq ?
bram_2_memory_DOA :
bram_2_serverAdapterA_outDataCore_D_OUT ;
assign bram_2_serverAdapterA_outData_outData_whas =
WILL_FIRE_RL_bram_2_serverAdapterA_outData_setFirstEnq ||
bram_2_serverAdapterA_outDataCore_EMPTY_N ;
assign bram_2_serverAdapterA_cnt_1_wget = 3'd1 ;
assign bram_2_serverAdapterA_cnt_1_whas =
(MUX_bram_2_memory_a_put_1__SEL_1 ||
MUX_bram_2_memory_a_put_1__SEL_2 ||
MUX_bram_2_memory_a_put_1__SEL_3 ||
WILL_FIRE_RL_tlp_tlpBRAM_read_NextReq) &&
(!ab__h7517[1] || ab__h7517[0]) ;
assign bram_2_serverAdapterA_cnt_2_wget = 3'd7 ;
assign bram_2_serverAdapterA_cnt_2_whas =
bram_2_serverAdapterA_outData_deqCalled_whas ;
assign bram_2_serverAdapterA_cnt_3_wget = 3'h0 ;
assign bram_2_serverAdapterA_cnt_3_whas = 1'b0 ;
assign bram_2_serverAdapterA_writeWithResp_wget = ab__h7517 ;
assign bram_2_serverAdapterA_writeWithResp_whas =
MUX_bram_2_memory_a_put_1__SEL_1 ||
MUX_bram_2_memory_a_put_1__SEL_2 ||
MUX_bram_2_memory_a_put_1__SEL_3 ||
WILL_FIRE_RL_tlp_tlpBRAM_read_NextReq ;
assign bram_2_serverAdapterA_s1_1_wget =
{ 1'd1, !ab__h7517[1] || ab__h7517[0] } ;
assign bram_2_serverAdapterA_s1_1_whas =
bram_2_serverAdapterA_writeWithResp_whas ;
assign bram_2_serverAdapterB_outData_enqData_wget = bram_2_memory_DOB ;
assign bram_2_serverAdapterB_outData_enqData_whas =
(!bram_2_serverAdapterB_s1[0] ||
bram_2_serverAdapterB_outDataCore_FULL_N) &&
bram_2_serverAdapterB_s1[1] &&
bram_2_serverAdapterB_s1[0] ;
assign bram_2_serverAdapterB_outData_outData_wget =
bram_2_serverAdapterB_outDataCore_EMPTY_N ?
bram_2_serverAdapterB_outDataCore_D_OUT :
bram_2_memory_DOB ;
assign bram_2_serverAdapterB_outData_outData_whas =
bram_2_serverAdapterB_outDataCore_EMPTY_N ||
!bram_2_serverAdapterB_outDataCore_EMPTY_N &&
bram_2_serverAdapterB_outData_enqData_whas ;
assign bram_2_serverAdapterB_cnt_1_wget = 3'd1 ;
assign bram_2_serverAdapterB_cnt_1_whas =
(WILL_FIRE_RL_wmi_reqMetadata || WILL_FIRE_RL_wmi_doReadReq ||
WILL_FIRE_RL_wmi_doWriteReq ||
WILL_FIRE_RL_wmi_doWriteFinalize) &&
(!ab__h8922[1] || ab__h8922[0]) ;
assign bram_2_serverAdapterB_cnt_2_wget = 3'd7 ;
assign bram_2_serverAdapterB_cnt_2_whas =
bram_0_serverAdapterB_outData_deqCalled_whas ;
assign bram_2_serverAdapterB_cnt_3_wget = 3'h0 ;
assign bram_2_serverAdapterB_cnt_3_whas = 1'b0 ;
assign bram_2_serverAdapterB_writeWithResp_wget = ab__h8922 ;
assign bram_2_serverAdapterB_writeWithResp_whas =
bram_0_serverAdapterB_writeWithResp_whas ;
assign bram_2_serverAdapterB_s1_1_wget =
{ 1'd1, !ab__h8922[1] || ab__h8922[0] } ;
assign bram_2_serverAdapterB_s1_1_whas =
bram_0_serverAdapterB_writeWithResp_whas ;
assign bram_3_serverAdapterA_outData_enqData_wget = bram_3_memory_DOA ;
assign bram_3_serverAdapterA_outData_enqData_whas =
(!bram_3_serverAdapterA_s1[0] ||
bram_3_serverAdapterA_outDataCore_FULL_N) &&
bram_3_serverAdapterA_s1[1] &&
bram_3_serverAdapterA_s1[0] ;
assign bram_3_serverAdapterA_outData_outData_wget =
bram_3_serverAdapterA_outDataCore_EMPTY_N ?
bram_3_serverAdapterA_outDataCore_D_OUT :
bram_3_memory_DOA ;
assign bram_3_serverAdapterA_outData_outData_whas =
bram_3_serverAdapterA_outDataCore_EMPTY_N ||
!bram_3_serverAdapterA_outDataCore_EMPTY_N &&
bram_3_serverAdapterA_outData_enqData_whas ;
assign bram_3_serverAdapterA_cnt_1_wget = 3'd1 ;
assign bram_3_serverAdapterA_cnt_1_whas =
(MUX_bram_3_memory_a_put_1__SEL_1 ||
MUX_bram_3_memory_a_put_1__SEL_2 ||
MUX_bram_3_memory_a_put_1__SEL_3 ||
WILL_FIRE_RL_tlp_tlpBRAM_read_NextReq) &&
(!ab__h10465[1] || ab__h10465[0]) ;
assign bram_3_serverAdapterA_cnt_2_wget = 3'd7 ;
assign bram_3_serverAdapterA_cnt_2_whas =
bram_3_serverAdapterA_outData_deqCalled_whas ;
assign bram_3_serverAdapterA_cnt_3_wget = 3'h0 ;
assign bram_3_serverAdapterA_cnt_3_whas = 1'b0 ;
assign bram_3_serverAdapterA_writeWithResp_wget = ab__h10465 ;
assign bram_3_serverAdapterA_writeWithResp_whas =
MUX_bram_3_memory_a_put_1__SEL_1 ||
MUX_bram_3_memory_a_put_1__SEL_2 ||
MUX_bram_3_memory_a_put_1__SEL_3 ||
WILL_FIRE_RL_tlp_tlpBRAM_read_NextReq ;
assign bram_3_serverAdapterA_s1_1_wget =
{ 1'd1, !ab__h10465[1] || ab__h10465[0] } ;
assign bram_3_serverAdapterA_s1_1_whas =
bram_3_serverAdapterA_writeWithResp_whas ;
assign bram_3_serverAdapterB_outData_enqData_wget = bram_3_memory_DOB ;
assign bram_3_serverAdapterB_outData_enqData_whas =
(!bram_3_serverAdapterB_s1[0] ||
bram_3_serverAdapterB_outDataCore_FULL_N) &&
bram_3_serverAdapterB_s1[1] &&
bram_3_serverAdapterB_s1[0] ;
assign bram_3_serverAdapterB_outData_outData_wget =
bram_3_serverAdapterB_outDataCore_EMPTY_N ?
bram_3_serverAdapterB_outDataCore_D_OUT :
bram_3_memory_DOB ;
assign bram_3_serverAdapterB_outData_outData_whas =
bram_3_serverAdapterB_outDataCore_EMPTY_N ||
!bram_3_serverAdapterB_outDataCore_EMPTY_N &&
bram_3_serverAdapterB_outData_enqData_whas ;
assign bram_3_serverAdapterB_cnt_1_wget = 3'd1 ;
assign bram_3_serverAdapterB_cnt_1_whas =
(WILL_FIRE_RL_wmi_reqMetadata || WILL_FIRE_RL_wmi_doReadReq ||
WILL_FIRE_RL_wmi_doWriteReq ||
WILL_FIRE_RL_wmi_doWriteFinalize) &&
(!ab__h11870[1] || ab__h11870[0]) ;
assign bram_3_serverAdapterB_cnt_2_wget = 3'd7 ;
assign bram_3_serverAdapterB_cnt_2_whas =
bram_0_serverAdapterB_outData_deqCalled_whas ;
assign bram_3_serverAdapterB_cnt_3_wget = 3'h0 ;
assign bram_3_serverAdapterB_cnt_3_whas = 1'b0 ;
assign bram_3_serverAdapterB_writeWithResp_wget = ab__h11870 ;
assign bram_3_serverAdapterB_writeWithResp_whas =
bram_0_serverAdapterB_writeWithResp_whas ;
assign bram_3_serverAdapterB_s1_1_wget =
{ 1'd1, !ab__h11870[1] || ab__h11870[0] } ;
assign bram_3_serverAdapterB_s1_1_whas =
bram_0_serverAdapterB_writeWithResp_whas ;
assign wci_wciReq_wget =
{ wci_s_MCmd,
wci_s_MAddrSpace,
wci_s_MByteEn,
wci_s_MAddr,
wci_s_MData } ;
assign wci_wciReq_whas = 1'd1 ;
assign wci_respF_x_wire_wget = MUX_wci_respF_q_0_write_1__VAL_2 ;
assign wci_respF_x_wire_whas = wci_respF_enqueueing_whas ;
assign wci_wEdge_wget = wci_reqF_D_OUT[36:34] ;
assign wci_wEdge_whas = WILL_FIRE_RL_wci_ctl_op_start ;
assign wci_sFlagReg_1_wget = 1'b0 ;
assign wci_sFlagReg_1_whas = 1'b0 ;
assign wci_ctlAckReg_1_wget = 1'd1 ;
assign wci_ctlAckReg_1_whas =
wci_wci_ctrl_pw_whas && WILL_FIRE_RL_wci_ctl_op_start &&
wci_cState == 3'd2 &&
wci_reqF_D_OUT[36:34] == 3'd3 ||
wci_wci_ctrl_pw_whas && WILL_FIRE_RL_wci_ctl_op_start &&
wci_cState == 3'd0 &&
wci_reqF_D_OUT[36:34] == 3'd0 ||
WILL_FIRE_RL_bml_initAccumulators ;
assign wti_wtiReq_wget = 67'h0 ;
assign wti_wtiReq_whas = 1'b0 ;
assign wti_operateD_1_wget = 1'b0 ;
assign wti_operateD_1_whas = 1'b0 ;
assign tlp_remStart_1_wget = 1'd1 ;
assign tlp_remStart_1_whas =
WILL_FIRE_RL_tlp_dmaRequestFarMeta ||
WILL_FIRE_RL_tlp_dmaXmtDoorbell ||
WILL_FIRE_RL_tlp_dmaRequestNearMeta ;
assign tlp_remDone_1_wget = 1'd1 ;
assign tlp_remDone_1_whas =
MUX_tlp_remDone_1_wset_1__SEL_1 ||
WILL_FIRE_RL_tlp_dmaXmtMetaBody ;
assign tlp_nearBufReady_1_wget = 1'd1 ;
assign tlp_nearBufReady_1_whas =
wci_cState == 3'd2 && bml_lclBufsCF != 16'd0 ;
assign tlp_farBufReady_1_wget = 1'd1 ;
assign tlp_farBufReady_1_whas =
wci_cState == 3'd2 && bml_fabBufsAvail != 16'd0 ;
assign tlp_creditReady_1_wget = 1'd1 ;
assign tlp_creditReady_1_whas =
wci_cState == 3'd2 && bml_lclCredit != 16'd0 ;
assign tlp_dpControl_wget = dpControl ;
assign tlp_dpControl_whas = 1'd1 ;
assign tlp_pullTagMatch_1_wget =
tagm__h64387 == tlp_inF_D_OUT[47:40] &&
tlp_inF_first__259_BITS_63_TO_56_262_EQ_pciDev_ETC___d1272 ;
assign tlp_pullTagMatch_1_whas =
tlp_inF_EMPTY_N && hasPull && dpControl[7:4] == 4'd0 &&
dpControl[3:2] == 2'd2 &&
dpControl[1:0] == 2'd1 ;
assign tlp_nowW_wget = wti_nowReq[63:0] ;
assign tlp_nowW_whas = 1'd1 ;
assign tlp_dmaStartMark_1_wget = 1'd1 ;
assign tlp_dmaStartMark_1_whas =
WILL_FIRE_RL_tlp_dmaRequestFarMeta ||
WILL_FIRE_RL_tlp_dmaRequestNearMeta ;
assign tlp_dmaDoneMark_1_wget = 1'd1 ;
assign tlp_dmaDoneMark_1_whas = WILL_FIRE_RL_tlp_dmaTailEventSender ;
assign wmi_wmi_wmiReq_wget =
{ wmiS0_MCmd,
wmiS0_MReqLast,
wmiS0_MReqInfo,
wmiS0_MAddrSpace,
wmiS0_MAddr,
wmiS0_MBurstLength } ;
assign wmi_wmi_wmiReq_whas = 1'd1 ;
assign wmi_wmi_wmiMFlag_wget = wmiS0_arg_mFlag ;
assign wmi_wmi_wmiMFlag_whas = 1'd1 ;
assign wmi_wmi_wmiDh_wget =
{ wmiS0_MDataValid,
wmiS0_MDataLast,
wmiS0_MData,
wmiS0_MDataByteEn } ;
assign wmi_wmi_wmiDh_whas = 1'd1 ;
assign wmi_wmi_respF_x_wire_wget = MUX_wmi_wmi_respF_q_0_write_1__VAL_2 ;
assign wmi_wmi_respF_x_wire_whas = WILL_FIRE_RL_wmi_doReadResp ;
assign wmi_wmi_operateD_1_wget = 1'd1 ;
assign wmi_wmi_operateD_1_whas = wci_cState == 3'd2 ;
assign wmi_wmi_peerIsReady_1_wget = 1'd1 ;
assign wmi_wmi_peerIsReady_1_whas = wmiS0_MReset_n ;
assign wmi_wmi_sThreadBusy_dw_wget = wmi_wmi_reqF_countReg > 2'd1 ;
assign wmi_wmi_sThreadBusy_dw_whas =
wmi_wmi_reqF_levelsValid && wmi_wmi_operateD &&
wmi_wmi_peerIsReady &&
!wmi_wmi_forceSThreadBusy_pw_whas ;
assign wmi_wmi_sDataThreadBusy_dw_wget = wmi_wmi_dhF_countReg > 2'd1 ;
assign wmi_wmi_sDataThreadBusy_dw_whas =
wmi_wmi_dhF_levelsValid && wmi_wmi_operateD &&
wmi_wmi_peerIsReady ;
assign wmi_mesgStart_1_wget = 1'd1 ;
assign wmi_mesgStart_1_whas = WILL_FIRE_RL_wmi_getRequest && !wmi_mesgBusy ;
assign wmi_mesgDone_1_wget = 1'd1 ;
assign wmi_mesgDone_1_whas =
WILL_FIRE_RL_wmi_doReadReq && wmi_bytesRemainReq == 14'd16 &&
wmi_doneWithMesg ||
WILL_FIRE_RL_wmi_doWriteFinalize ;
assign wmi_mesgBufReady_1_wget = 1'd1 ;
assign wmi_mesgBufReady_1_whas =
wci_cState == 3'd2 && bml_lclBufsAR != 16'd0 ;
assign wmi_dpControl_wget = dpControl ;
assign wmi_dpControl_whas = 1'd1 ;
assign wmi_nowW_wget = wti_nowReq[63:0] ;
assign wmi_nowW_whas = 1'd1 ;
assign bml_lclBufStart_1_wget = 1'd1 ;
assign bml_lclBufStart_1_whas = wmi_mesgStart ;
assign bml_lclBufDone_1_wget = 1'd1 ;
assign bml_lclBufDone_1_whas = wmi_mesgDone ;
assign bml_remStart_1_wget = 1'd1 ;
assign bml_remStart_1_whas = tlp_remStart ;
assign bml_remDone_1_wget = 1'd1 ;
assign bml_remDone_1_whas = tlp_remDone ;
assign bml_fabDone_1_wget = 1'd1 ;
assign bml_fabDone_1_whas =
WILL_FIRE_RL_wci_cfwr && wci_reqF_D_OUT[39:32] == 8'h18 &&
dpControl[1:0] != 2'd1 ;
assign bml_fabAvail_1_wget = 1'd1 ;
assign bml_fabAvail_1_whas =
WILL_FIRE_RL_wci_cfwr && wci_reqF_D_OUT[39:32] == 8'h18 &&
dpControl[1:0] == 2'd1 ;
assign bml_datumAReg_1_wget = bml_remDone ;
assign bml_datumAReg_1_whas = wci_cState == 3'd2 ;
assign bml_dpControl_wget = dpControl ;
assign bml_dpControl_whas = 1'd1 ;
assign wci_Es_mCmd_w_wget = wci_s_MCmd ;
assign wci_Es_mCmd_w_whas = 1'd1 ;
assign wci_Es_mAddrSpace_w_wget = wci_s_MAddrSpace ;
assign wci_Es_mAddrSpace_w_whas = 1'd1 ;
assign wci_Es_mByteEn_w_wget = wci_s_MByteEn ;
assign wci_Es_mByteEn_w_whas = 1'd1 ;
assign wci_Es_mAddr_w_wget = wci_s_MAddr ;
assign wci_Es_mAddr_w_whas = 1'd1 ;
assign wci_Es_mData_w_wget = wci_s_MData ;
assign wci_Es_mData_w_whas = 1'd1 ;
assign wmi_Es_mCmd_w_wget = wmiS0_MCmd ;
assign wmi_Es_mCmd_w_whas = 1'd1 ;
assign wmi_Es_mReqInfo_w_wget = wmiS0_MReqInfo ;
assign wmi_Es_mReqInfo_w_whas = 1'd1 ;
assign wmi_Es_mAddrSpace_w_wget = wmiS0_MAddrSpace ;
assign wmi_Es_mAddrSpace_w_whas = 1'd1 ;
assign wmi_Es_mAddr_w_wget = wmiS0_MAddr ;
assign wmi_Es_mAddr_w_whas = 1'd1 ;
assign wmi_Es_mBurstLength_w_wget = wmiS0_MBurstLength ;
assign wmi_Es_mBurstLength_w_whas = 1'd1 ;
assign wmi_Es_mData_w_wget = wmiS0_MData ;
assign wmi_Es_mData_w_whas = 1'd1 ;
assign wmi_Es_mDataByteEn_w_wget = wmiS0_MDataByteEn ;
assign wmi_Es_mDataByteEn_w_whas = 1'd1 ;
assign bram_0_serverAdapterA_outData_deqCalled_whas =
WILL_FIRE_RL_tlp_tlpBRAM_read_FirstResp &&
tlp_tlpBRAM_readReq_D_OUT[30:29] == 2'd0 &&
!tlp_tlpBRAM_readReq_D_OUT[60] ||
WILL_FIRE_RL_tlp_tlpBRAM_read_NextResp ;
assign bram_0_serverAdapterB_outData_deqCalled_whas =
WILL_FIRE_RL_wmi_respMetadata || WILL_FIRE_RL_wmi_doReadResp ;
assign bram_1_serverAdapterA_outData_deqCalled_whas =
WILL_FIRE_RL_tlp_tlpBRAM_read_FirstResp &&
tlp_tlpBRAM_readReq_D_OUT[30:29] == 2'd1 &&
!tlp_tlpBRAM_readReq_D_OUT[60] ||
WILL_FIRE_RL_tlp_tlpBRAM_read_NextResp ;
assign bram_1_serverAdapterB_outData_deqCalled_whas =
bram_0_serverAdapterB_outData_deqCalled_whas ;
assign bram_2_serverAdapterA_outData_deqCalled_whas =
WILL_FIRE_RL_tlp_tlpBRAM_read_FirstResp &&
tlp_tlpBRAM_readReq_D_OUT[30:29] == 2'd2 &&
!tlp_tlpBRAM_readReq_D_OUT[60] ||
WILL_FIRE_RL_tlp_tlpBRAM_read_NextResp ;
assign bram_2_serverAdapterB_outData_deqCalled_whas =
bram_0_serverAdapterB_outData_deqCalled_whas ;
assign bram_3_serverAdapterA_outData_deqCalled_whas =
WILL_FIRE_RL_tlp_tlpBRAM_read_FirstResp &&
tlp_tlpBRAM_readReq_D_OUT[30:29] == 2'd3 &&
!tlp_tlpBRAM_readReq_D_OUT[60] ||
WILL_FIRE_RL_tlp_tlpBRAM_read_NextResp ;
assign bram_3_serverAdapterB_outData_deqCalled_whas =
bram_0_serverAdapterB_outData_deqCalled_whas ;
assign wci_reqF_r_enq_whas = wci_wciReq_wget[71:69] != 3'd0 ;
assign wci_reqF_r_deq_whas =
WILL_FIRE_RL_wci_ctl_op_start || WILL_FIRE_RL_wci_cfrd ||
WILL_FIRE_RL_wci_cfwr ;
assign wci_reqF_r_clr_whas = 1'b0 ;
assign wci_respF_enqueueing_whas =
WILL_FIRE_RL_wci_ctl_op_complete || WILL_FIRE_RL_wci_cfrd ||
WILL_FIRE_RL_wci_cfwr ;
assign wci_respF_dequeueing_whas = wci_respF_cntr_r != 2'd0 ;
assign wci_sThreadBusy_pw_whas = 1'b0 ;
assign wci_wci_cfwr_pw_whas =
wci_reqF_EMPTY_N && wci_reqF_D_OUT[68] &&
wci_reqF_D_OUT[71:69] == 3'd1 ;
assign wci_wci_cfrd_pw_whas =
wci_reqF_EMPTY_N && wci_reqF_D_OUT[68] &&
wci_reqF_D_OUT[71:69] == 3'd2 ;
assign wci_wci_ctrl_pw_whas =
wci_reqF_EMPTY_N && !wci_reqF_D_OUT[68] &&
wci_reqF_D_OUT[71:69] == 3'd2 ;
assign wmi_wmi_forceSThreadBusy_pw_whas =
dpControl[3:2] != 2'd1 && !wmi_mesgMeta[128] ||
dpControl[3:2] == 2'd1 && !wmi_mesgBufReady ;
assign wmi_wmi_reqF_r_enq_whas =
MUX_wmi_wmi_reqF_levelsValid_write_1__SEL_2 ;
assign wmi_wmi_reqF_r_deq_whas = WILL_FIRE_RL_wmi_getRequest ;
assign wmi_wmi_reqF_r_clr_whas = 1'b0 ;
assign wmi_wmi_reqF_doResetEnq_whas =
MUX_wmi_wmi_reqF_levelsValid_write_1__SEL_2 ;
assign wmi_wmi_reqF_doResetDeq_whas = WILL_FIRE_RL_wmi_getRequest ;
assign wmi_wmi_reqF_doResetClr_whas = 1'b0 ;
assign wmi_wmi_mFlagF_r_enq_whas =
MUX_wmi_wmi_mFlagF_levelsValid_write_1__SEL_2 ;
assign wmi_wmi_mFlagF_r_deq_whas = WILL_FIRE_RL_wmi_doWriteFinalize ;
assign wmi_wmi_mFlagF_r_clr_whas = 1'b0 ;
assign wmi_wmi_mFlagF_doResetEnq_whas =
MUX_wmi_wmi_mFlagF_levelsValid_write_1__SEL_2 ;
assign wmi_wmi_mFlagF_doResetDeq_whas = WILL_FIRE_RL_wmi_doWriteFinalize ;
assign wmi_wmi_mFlagF_doResetClr_whas = 1'b0 ;
assign wmi_wmi_dhF_r_enq_whas = MUX_wmi_wmi_dhF_levelsValid_write_1__SEL_2 ;
assign wmi_wmi_dhF_r_deq_whas = WILL_FIRE_RL_wmi_doWriteReq ;
assign wmi_wmi_dhF_r_clr_whas = 1'b0 ;
assign wmi_wmi_dhF_doResetEnq_whas =
MUX_wmi_wmi_dhF_levelsValid_write_1__SEL_2 ;
assign wmi_wmi_dhF_doResetDeq_whas = WILL_FIRE_RL_wmi_doWriteReq ;
assign wmi_wmi_dhF_doResetClr_whas = 1'b0 ;
assign wmi_wmi_respF_enqueueing_whas = WILL_FIRE_RL_wmi_doReadResp ;
assign wmi_wmi_respF_dequeueing_whas = wmi_wmi_respF_cntr_r != 2'd0 ;
assign bml_lclBuf_incAction_whas = WILL_FIRE_RL_bml_lclAdvance ;
assign bml_lclBuf_decAction_whas = 1'b0 ;
assign bml_remBuf_incAction_whas = WILL_FIRE_RL_bml_remAdvance ;
assign bml_remBuf_decAction_whas = 1'b0 ;
assign bml_fabBuf_incAction_whas = MUX_bml_fabFlowAddr_write_1__SEL_1 ;
assign bml_fabBuf_decAction_whas = 1'b0 ;
assign bml_crdBuf_incAction_whas = WILL_FIRE_RL_bml_crdAdvance ;
assign bml_crdBuf_decAction_whas = 1'b0 ;
assign wmi_Es_mReqLast_w_whas = wmiS0_MReqLast ;
assign wmi_Es_mDataValid_w_whas = wmiS0_MDataValid ;
assign wmi_Es_mDataLast_w_whas = wmiS0_MDataLast ;
assign wmi_Es_mDataInfo_w_whas = 1'd1 ;
assign bml_lclBuf_modulus_bw_wget = bml_lclBuf_modulus ;
assign bml_remBuf_modulus_bw_wget = bml_remBuf_modulus ;
assign bml_fabBuf_modulus_bw_wget = bml_fabBuf_modulus ;
assign bml_crdBuf_modulus_bw_wget = bml_crdBuf_modulus ;
// register bml_crdBuf_modulus
assign bml_crdBuf_modulus_D_IN = bml_lclNumBufs - 16'd1 ;
assign bml_crdBuf_modulus_EN = WILL_FIRE_RL_bml_initAccumulators ;
// register bml_crdBuf_value
assign bml_crdBuf_value_D_IN =
WILL_FIRE_RL_bml_initAccumulators ?
16'd0 :
MUX_bml_crdBuf_value_write_1__VAL_3 ;
assign bml_crdBuf_value_EN =
WILL_FIRE_RL_bml_crdAdvance ||
WILL_FIRE_RL_bml_initAccumulators ;
// register bml_datumAReg
assign bml_datumAReg_D_IN = CAN_FIRE_RL_bml_remAdvance ;
assign bml_datumAReg_EN = 1'd1 ;
// register bml_fabAvail
assign bml_fabAvail_D_IN = bml_fabAvail_1_whas ;
assign bml_fabAvail_EN = 1'd1 ;
// register bml_fabBuf_modulus
assign bml_fabBuf_modulus_D_IN = bml_fabNumBufs - 16'd1 ;
assign bml_fabBuf_modulus_EN = WILL_FIRE_RL_bml_initAccumulators ;
// register bml_fabBuf_value
assign bml_fabBuf_value_D_IN =
WILL_FIRE_RL_bml_initAccumulators ?
16'd0 :
MUX_bml_fabBuf_value_write_1__VAL_3 ;
assign bml_fabBuf_value_EN =
MUX_bml_fabFlowAddr_write_1__SEL_1 ||
WILL_FIRE_RL_bml_initAccumulators ;
// register bml_fabBufsAvail
assign bml_fabBufsAvail_D_IN =
MUX_bml_fabBufsAvail_write_1__SEL_1 ?
MUX_bml_fabBufsAvail_write_1__VAL_1 :
MUX_bml_fabBufsAvail_write_1__VAL_2 ;
assign bml_fabBufsAvail_EN =
WILL_FIRE_RL_bml_fba &&
(bml_fabAvail && !bml_remStart ||
!bml_fabAvail && bml_remStart) ||
WILL_FIRE_RL_bml_initAccumulators ;
// register bml_fabDone
assign bml_fabDone_D_IN = bml_fabDone_1_whas ;
assign bml_fabDone_EN = 1'd1 ;
// register bml_fabFlowAddr
always@(MUX_bml_fabFlowAddr_write_1__SEL_1 or
MUX_bml_fabFlowAddr_write_1__VAL_1 or
WILL_FIRE_RL_bml_initAccumulators or
bml_fabFlowBase or
WILL_FIRE_RL_bml_crdAdvance or MUX_bml_fabFlowAddr_write_1__VAL_3)
begin
case (1'b1) // synopsys parallel_case
MUX_bml_fabFlowAddr_write_1__SEL_1:
bml_fabFlowAddr_D_IN = MUX_bml_fabFlowAddr_write_1__VAL_1;
WILL_FIRE_RL_bml_initAccumulators:
bml_fabFlowAddr_D_IN = bml_fabFlowBase;
WILL_FIRE_RL_bml_crdAdvance:
bml_fabFlowAddr_D_IN = MUX_bml_fabFlowAddr_write_1__VAL_3;
default: bml_fabFlowAddr_D_IN = 32'hAAAAAAAA /* unspecified value */ ;
endcase
end
assign bml_fabFlowAddr_EN =
WILL_FIRE_RL_bml_remAdvance && dpControl[1:0] == 2'd1 ||
WILL_FIRE_RL_bml_initAccumulators ||
WILL_FIRE_RL_bml_crdAdvance ;
// register bml_fabFlowBase
assign bml_fabFlowBase_D_IN = wci_reqF_D_OUT[31:0] ;
assign bml_fabFlowBase_EN =
WILL_FIRE_RL_wci_cfwr && wci_reqF_D_OUT[39:32] == 8'h60 ;
// register bml_fabFlowBaseMS
assign bml_fabFlowBaseMS_D_IN = wci_reqF_D_OUT[31:0] ;
assign bml_fabFlowBaseMS_EN =
WILL_FIRE_RL_wci_cfwr && wci_reqF_D_OUT[39:32] == 8'h9C ;
// register bml_fabFlowSize
assign bml_fabFlowSize_D_IN = wci_reqF_D_OUT[31:0] ;
assign bml_fabFlowSize_EN =
WILL_FIRE_RL_wci_cfwr && wci_reqF_D_OUT[39:32] == 8'h64 ;
// register bml_fabMesgAddr
assign bml_fabMesgAddr_D_IN =
MUX_bml_fabFlowAddr_write_1__SEL_1 ?
MUX_bml_fabMesgAddr_write_1__VAL_1 :
bml_fabMesgBase ;
assign bml_fabMesgAddr_EN =
WILL_FIRE_RL_bml_remAdvance && dpControl[1:0] == 2'd1 ||
WILL_FIRE_RL_bml_initAccumulators ;
// register bml_fabMesgBase
assign bml_fabMesgBase_D_IN = wci_reqF_D_OUT[31:0] ;
assign bml_fabMesgBase_EN =
WILL_FIRE_RL_wci_cfwr && wci_reqF_D_OUT[39:32] == 8'h50 ;
// register bml_fabMesgBaseMS
assign bml_fabMesgBaseMS_D_IN = wci_reqF_D_OUT[31:0] ;
assign bml_fabMesgBaseMS_EN =
WILL_FIRE_RL_wci_cfwr && wci_reqF_D_OUT[39:32] == 8'h94 ;
// register bml_fabMesgSize
assign bml_fabMesgSize_D_IN = wci_reqF_D_OUT[31:0] ;
assign bml_fabMesgSize_EN =
WILL_FIRE_RL_wci_cfwr && wci_reqF_D_OUT[39:32] == 8'h58 ;
// register bml_fabMetaAddr
assign bml_fabMetaAddr_D_IN =
MUX_bml_fabFlowAddr_write_1__SEL_1 ?
MUX_bml_fabMetaAddr_write_1__VAL_1 :
bml_fabMetaBase ;
assign bml_fabMetaAddr_EN =
WILL_FIRE_RL_bml_remAdvance && dpControl[1:0] == 2'd1 ||
WILL_FIRE_RL_bml_initAccumulators ;
// register bml_fabMetaBase
assign bml_fabMetaBase_D_IN = wci_reqF_D_OUT[31:0] ;
assign bml_fabMetaBase_EN =
WILL_FIRE_RL_wci_cfwr && wci_reqF_D_OUT[39:32] == 8'h54 ;
// register bml_fabMetaBaseMS
assign bml_fabMetaBaseMS_D_IN = wci_reqF_D_OUT[31:0] ;
assign bml_fabMetaBaseMS_EN =
WILL_FIRE_RL_wci_cfwr && wci_reqF_D_OUT[39:32] == 8'h98 ;
// register bml_fabMetaSize
assign bml_fabMetaSize_D_IN = wci_reqF_D_OUT[31:0] ;
assign bml_fabMetaSize_EN =
WILL_FIRE_RL_wci_cfwr && wci_reqF_D_OUT[39:32] == 8'h5C ;
// register bml_fabNumBufs
assign bml_fabNumBufs_D_IN = wci_reqF_D_OUT[15:0] ;
assign bml_fabNumBufs_EN =
WILL_FIRE_RL_wci_cfwr && wci_reqF_D_OUT[39:32] == 8'h04 ;
// register bml_lclBufDone
assign bml_lclBufDone_D_IN = wmi_mesgDone ;
assign bml_lclBufDone_EN = 1'd1 ;
// register bml_lclBufStart
assign bml_lclBufStart_D_IN = wmi_mesgStart ;
assign bml_lclBufStart_EN = 1'd1 ;
// register bml_lclBuf_modulus
assign bml_lclBuf_modulus_D_IN = bml_crdBuf_modulus_D_IN ;
assign bml_lclBuf_modulus_EN = WILL_FIRE_RL_bml_initAccumulators ;
// register bml_lclBuf_value
assign bml_lclBuf_value_D_IN =
WILL_FIRE_RL_bml_initAccumulators ?
16'd0 :
MUX_bml_lclBuf_value_write_1__VAL_3 ;
assign bml_lclBuf_value_EN =
WILL_FIRE_RL_bml_lclAdvance ||
WILL_FIRE_RL_bml_initAccumulators ;
// register bml_lclBufsAR
assign bml_lclBufsAR_D_IN =
MUX_bml_lclBufsAR_write_1__SEL_1 ?
MUX_bml_lclBufsAR_write_1__VAL_1 :
MUX_bml_lclBufsAR_write_1__VAL_2 ;
assign bml_lclBufsAR_EN =
wci_cState == 3'd2 &&
IF_bml_dpControl_wget__898_BITS_1_TO_0_904_EQ__ETC___d1984 ||
WILL_FIRE_RL_bml_initAccumulators ;
// register bml_lclBufsCF
assign bml_lclBufsCF_D_IN =
MUX_bml_lclBufsCF_write_1__SEL_1 ?
MUX_bml_lclBufsCF_write_1__VAL_1 :
MUX_bml_lclBufsCF_write_1__VAL_2 ;
assign bml_lclBufsCF_EN =
wci_cState == 3'd2 &&
bml_lclBufDone_922_AND_IF_bml_dpControl_wget___ETC___d2003 ||
WILL_FIRE_RL_bml_initAccumulators ;
// register bml_lclCredit
assign bml_lclCredit_D_IN =
MUX_bml_lclCredit_write_1__SEL_1 ?
MUX_bml_lclCredit_write_1__VAL_1 :
16'd0 ;
assign bml_lclCredit_EN =
WILL_FIRE_RL_bml_lcredit &&
(bml_lclBufDone && !bml_remStart ||
!bml_lclBufDone && bml_remStart) ||
WILL_FIRE_RL_bml_initAccumulators ;
// register bml_lclDones
assign bml_lclDones_D_IN = bml_lclDones + 16'd1 ;
assign bml_lclDones_EN = WILL_FIRE_RL_bml_lclAdvance ;
// register bml_lclMesgAddr
assign bml_lclMesgAddr_D_IN =
WILL_FIRE_RL_bml_initAccumulators ?
bml_mesgBase :
MUX_bml_lclMesgAddr_write_1__VAL_2 ;
assign bml_lclMesgAddr_EN =
WILL_FIRE_RL_bml_initAccumulators ||
WILL_FIRE_RL_bml_lclAdvance ;
// register bml_lclMetaAddr
assign bml_lclMetaAddr_D_IN =
WILL_FIRE_RL_bml_initAccumulators ?
bml_metaBase :
MUX_bml_lclMetaAddr_write_1__VAL_2 ;
assign bml_lclMetaAddr_EN =
WILL_FIRE_RL_bml_initAccumulators ||
WILL_FIRE_RL_bml_lclAdvance ;
// register bml_lclNumBufs
assign bml_lclNumBufs_D_IN = wci_reqF_D_OUT[15:0] ;
assign bml_lclNumBufs_EN =
WILL_FIRE_RL_wci_cfwr && wci_reqF_D_OUT[39:32] == 8'h0 ;
// register bml_lclStarts
assign bml_lclStarts_D_IN = bml_lclStarts + 16'd1 ;
assign bml_lclStarts_EN = wci_cState == 3'd2 && bml_lclBufStart ;
// register bml_mesgBase
assign bml_mesgBase_D_IN = wci_reqF_D_OUT[15:0] ;
assign bml_mesgBase_EN =
WILL_FIRE_RL_wci_cfwr && wci_reqF_D_OUT[39:32] == 8'h08 ;
// register bml_mesgSize
assign bml_mesgSize_D_IN = wci_reqF_D_OUT[15:0] ;
assign bml_mesgSize_EN =
WILL_FIRE_RL_wci_cfwr && wci_reqF_D_OUT[39:32] == 8'h10 ;
// register bml_metaBase
assign bml_metaBase_D_IN = wci_reqF_D_OUT[15:0] ;
assign bml_metaBase_EN =
WILL_FIRE_RL_wci_cfwr && wci_reqF_D_OUT[39:32] == 8'h0C ;
// register bml_metaSize
assign bml_metaSize_D_IN = wci_reqF_D_OUT[15:0] ;
assign bml_metaSize_EN =
WILL_FIRE_RL_wci_cfwr && wci_reqF_D_OUT[39:32] == 8'h14 ;
// register bml_remBuf_modulus
assign bml_remBuf_modulus_D_IN = bml_crdBuf_modulus_D_IN ;
assign bml_remBuf_modulus_EN = WILL_FIRE_RL_bml_initAccumulators ;
// register bml_remBuf_value
assign bml_remBuf_value_D_IN =
WILL_FIRE_RL_bml_initAccumulators ?
16'd0 :
MUX_bml_remBuf_value_write_1__VAL_3 ;
assign bml_remBuf_value_EN =
WILL_FIRE_RL_bml_remAdvance ||
WILL_FIRE_RL_bml_initAccumulators ;
// register bml_remDone
assign bml_remDone_D_IN = tlp_remDone ;
assign bml_remDone_EN = 1'd1 ;
// register bml_remDones
assign bml_remDones_D_IN = bml_remDones + 16'd1 ;
assign bml_remDones_EN = CAN_FIRE_RL_bml_remAdvance ;
// register bml_remMesgAddr
assign bml_remMesgAddr_D_IN =
WILL_FIRE_RL_bml_initAccumulators ?
bml_mesgBase :
MUX_bml_remMesgAddr_write_1__VAL_2 ;
assign bml_remMesgAddr_EN =
WILL_FIRE_RL_bml_initAccumulators ||
WILL_FIRE_RL_bml_remAdvance ;
// register bml_remMetaAddr
assign bml_remMetaAddr_D_IN =
WILL_FIRE_RL_bml_initAccumulators ?
bml_metaBase :
MUX_bml_remMetaAddr_write_1__VAL_2 ;
assign bml_remMetaAddr_EN =
WILL_FIRE_RL_bml_initAccumulators ||
WILL_FIRE_RL_bml_remAdvance ;
// register bml_remStart
assign bml_remStart_D_IN = tlp_remStart ;
assign bml_remStart_EN = 1'd1 ;
// register bml_remStarts
assign bml_remStarts_D_IN = bml_remStarts + 16'd1 ;
assign bml_remStarts_EN = wci_cState == 3'd2 && bml_remStart ;
// register bram_0_serverAdapterA_cnt
assign bram_0_serverAdapterA_cnt_D_IN =
bram_0_serverAdapterA_cnt_6_PLUS_IF_bram_0_ser_ETC___d32 ;
assign bram_0_serverAdapterA_cnt_EN =
bram_0_serverAdapterA_cnt_1_whas ||
bram_0_serverAdapterA_outData_deqCalled_whas ;
// register bram_0_serverAdapterA_s1
assign bram_0_serverAdapterA_s1_D_IN =
{ bram_0_serverAdapterA_writeWithResp_whas &&
bram_0_serverAdapterA_s1_1_wget[1],
bram_0_serverAdapterA_s1_1_wget[0] } ;
assign bram_0_serverAdapterA_s1_EN = 1'd1 ;
// register bram_0_serverAdapterB_cnt
assign bram_0_serverAdapterB_cnt_D_IN =
bram_0_serverAdapterB_cnt_5_PLUS_IF_bram_0_ser_ETC___d91 ;
assign bram_0_serverAdapterB_cnt_EN =
bram_0_serverAdapterB_cnt_1_whas ||
bram_0_serverAdapterB_outData_deqCalled_whas ;
// register bram_0_serverAdapterB_s1
assign bram_0_serverAdapterB_s1_D_IN =
{ bram_0_serverAdapterB_writeWithResp_whas &&
bram_0_serverAdapterB_s1_1_wget[1],
bram_0_serverAdapterB_s1_1_wget[0] } ;
assign bram_0_serverAdapterB_s1_EN = 1'd1 ;
// register bram_1_serverAdapterA_cnt
assign bram_1_serverAdapterA_cnt_D_IN =
bram_1_serverAdapterA_cnt_44_PLUS_IF_bram_1_se_ETC___d150 ;
assign bram_1_serverAdapterA_cnt_EN =
bram_1_serverAdapterA_cnt_1_whas ||
bram_1_serverAdapterA_outData_deqCalled_whas ;
// register bram_1_serverAdapterA_s1
assign bram_1_serverAdapterA_s1_D_IN =
{ bram_1_serverAdapterA_writeWithResp_whas &&
bram_1_serverAdapterA_s1_1_wget[1],
bram_1_serverAdapterA_s1_1_wget[0] } ;
assign bram_1_serverAdapterA_s1_EN = 1'd1 ;
// register bram_1_serverAdapterB_cnt
assign bram_1_serverAdapterB_cnt_D_IN =
bram_1_serverAdapterB_cnt_03_PLUS_IF_bram_1_se_ETC___d209 ;
assign bram_1_serverAdapterB_cnt_EN =
bram_1_serverAdapterB_cnt_1_whas ||
bram_0_serverAdapterB_outData_deqCalled_whas ;
// register bram_1_serverAdapterB_s1
assign bram_1_serverAdapterB_s1_D_IN =
{ bram_0_serverAdapterB_writeWithResp_whas &&
bram_1_serverAdapterB_s1_1_wget[1],
bram_1_serverAdapterB_s1_1_wget[0] } ;
assign bram_1_serverAdapterB_s1_EN = 1'd1 ;
// register bram_2_serverAdapterA_cnt
assign bram_2_serverAdapterA_cnt_D_IN =
bram_2_serverAdapterA_cnt_62_PLUS_IF_bram_2_se_ETC___d268 ;
assign bram_2_serverAdapterA_cnt_EN =
bram_2_serverAdapterA_cnt_1_whas ||
bram_2_serverAdapterA_outData_deqCalled_whas ;
// register bram_2_serverAdapterA_s1
assign bram_2_serverAdapterA_s1_D_IN =
{ bram_2_serverAdapterA_writeWithResp_whas &&
bram_2_serverAdapterA_s1_1_wget[1],
bram_2_serverAdapterA_s1_1_wget[0] } ;
assign bram_2_serverAdapterA_s1_EN = 1'd1 ;
// register bram_2_serverAdapterB_cnt
assign bram_2_serverAdapterB_cnt_D_IN =
bram_2_serverAdapterB_cnt_21_PLUS_IF_bram_2_se_ETC___d327 ;
assign bram_2_serverAdapterB_cnt_EN =
bram_2_serverAdapterB_cnt_1_whas ||
bram_0_serverAdapterB_outData_deqCalled_whas ;
// register bram_2_serverAdapterB_s1
assign bram_2_serverAdapterB_s1_D_IN =
{ bram_0_serverAdapterB_writeWithResp_whas &&
bram_2_serverAdapterB_s1_1_wget[1],
bram_2_serverAdapterB_s1_1_wget[0] } ;
assign bram_2_serverAdapterB_s1_EN = 1'd1 ;
// register bram_3_serverAdapterA_cnt
assign bram_3_serverAdapterA_cnt_D_IN =
bram_3_serverAdapterA_cnt_80_PLUS_IF_bram_3_se_ETC___d386 ;
assign bram_3_serverAdapterA_cnt_EN =
bram_3_serverAdapterA_cnt_1_whas ||
bram_3_serverAdapterA_outData_deqCalled_whas ;
// register bram_3_serverAdapterA_s1
assign bram_3_serverAdapterA_s1_D_IN =
{ bram_3_serverAdapterA_writeWithResp_whas &&
bram_3_serverAdapterA_s1_1_wget[1],
bram_3_serverAdapterA_s1_1_wget[0] } ;
assign bram_3_serverAdapterA_s1_EN = 1'd1 ;
// register bram_3_serverAdapterB_cnt
assign bram_3_serverAdapterB_cnt_D_IN =
bram_3_serverAdapterB_cnt_39_PLUS_IF_bram_3_se_ETC___d445 ;
assign bram_3_serverAdapterB_cnt_EN =
bram_3_serverAdapterB_cnt_1_whas ||
bram_0_serverAdapterB_outData_deqCalled_whas ;
// register bram_3_serverAdapterB_s1
assign bram_3_serverAdapterB_s1_D_IN =
{ bram_0_serverAdapterB_writeWithResp_whas &&
bram_3_serverAdapterB_s1_1_wget[1],
bram_3_serverAdapterB_s1_1_wget[0] } ;
assign bram_3_serverAdapterB_s1_EN = 1'd1 ;
// register dmaDoneTime
assign dmaDoneTime_D_IN = wti_nowReq[63:0] ;
assign dmaDoneTime_EN = tlp_dmaDoneMark ;
// register dmaStartTime
assign dmaStartTime_D_IN = wti_nowReq[63:0] ;
assign dmaStartTime_EN = tlp_dmaStartMark ;
// register dpControl
assign dpControl_D_IN = wci_reqF_D_OUT[7:0] ;
assign dpControl_EN =
WILL_FIRE_RL_wci_cfwr && wci_reqF_D_OUT[39:32] == 8'h68 ;
// register tlp_complTimerCount
assign tlp_complTimerCount_D_IN =
tlp_complTimerRunning ? tlp_complTimerCount + 12'd1 : 12'd0 ;
assign tlp_complTimerCount_EN = 1'd1 ;
// register tlp_complTimerRunning
assign tlp_complTimerRunning_D_IN =
WILL_FIRE_RL_tlp_dmaPullRequestFarMesg ||
WILL_FIRE_RL_tlp_dmaRequestFarMeta ;
assign tlp_complTimerRunning_EN =
WILL_FIRE_RL_tlp_dmaPullTailEvent ||
WILL_FIRE_RL_tlp_dmaRespHeadFarMeta ||
WILL_FIRE_RL_tlp_dmaPullRequestFarMesg ||
WILL_FIRE_RL_tlp_dmaRequestFarMeta ;
// register tlp_creditReady
assign tlp_creditReady_D_IN = tlp_creditReady_1_whas ;
assign tlp_creditReady_EN = 1'd1 ;
// register tlp_dmaDoTailEvent
always@(WILL_FIRE_RL_tlp_dmaPullResponseBody or
MUX_tlp_dmaDoTailEvent_write_1__VAL_1 or
WILL_FIRE_RL_tlp_dmaPullResponseHeader or
tlp_dmaPullRemainDWLen or
WILL_FIRE_RL_tlp_dmaRespBodyFarMeta or
tlp_mesgLengthRemainPull or WILL_FIRE_RL_tlp_dmaPullTailEvent)
case (1'b1)
WILL_FIRE_RL_tlp_dmaPullResponseBody:
tlp_dmaDoTailEvent_D_IN = MUX_tlp_dmaDoTailEvent_write_1__VAL_1;
WILL_FIRE_RL_tlp_dmaPullResponseHeader:
tlp_dmaDoTailEvent_D_IN = tlp_dmaPullRemainDWLen == 10'd1;
WILL_FIRE_RL_tlp_dmaRespBodyFarMeta:
tlp_dmaDoTailEvent_D_IN = tlp_mesgLengthRemainPull == 17'd0;
WILL_FIRE_RL_tlp_dmaPullTailEvent: tlp_dmaDoTailEvent_D_IN = 1'd0;
default: tlp_dmaDoTailEvent_D_IN = 1'b0 /* unspecified value */ ;
endcase
assign tlp_dmaDoTailEvent_EN =
WILL_FIRE_RL_tlp_dmaRespBodyFarMeta ||
WILL_FIRE_RL_tlp_dmaPullResponseHeader ||
WILL_FIRE_RL_tlp_dmaPullResponseBody ||
WILL_FIRE_RL_tlp_dmaPullTailEvent ;
// register tlp_dmaDoneMark
assign tlp_dmaDoneMark_D_IN = WILL_FIRE_RL_tlp_dmaTailEventSender ;
assign tlp_dmaDoneMark_EN = 1'd1 ;
// register tlp_dmaPullRemainDWLen
always@(WILL_FIRE_RL_tlp_dmaPullRequestFarMesg or
thisRequestLength__h63893 or
WILL_FIRE_RL_tlp_dmaPullResponseHeader or
MUX_tlp_dmaPullRemainDWLen_write_1__VAL_2 or
WILL_FIRE_RL_tlp_dmaPullResponseBody or
MUX_tlp_dmaPullRemainDWLen_write_1__VAL_3)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_tlp_dmaPullRequestFarMesg:
tlp_dmaPullRemainDWLen_D_IN = thisRequestLength__h63893[11:2];
WILL_FIRE_RL_tlp_dmaPullResponseHeader:
tlp_dmaPullRemainDWLen_D_IN =
MUX_tlp_dmaPullRemainDWLen_write_1__VAL_2;
WILL_FIRE_RL_tlp_dmaPullResponseBody:
tlp_dmaPullRemainDWLen_D_IN =
MUX_tlp_dmaPullRemainDWLen_write_1__VAL_3;
default: tlp_dmaPullRemainDWLen_D_IN =
10'b1010101010 /* unspecified value */ ;
endcase
end
assign tlp_dmaPullRemainDWLen_EN =
WILL_FIRE_RL_tlp_dmaPullRequestFarMesg ||
WILL_FIRE_RL_tlp_dmaPullResponseHeader ||
WILL_FIRE_RL_tlp_dmaPullResponseBody ;
// register tlp_dmaPullRemainDWSub
assign tlp_dmaPullRemainDWSub_D_IN =
WILL_FIRE_RL_tlp_dmaPullResponseHeader ?
MUX_tlp_dmaPullRemainDWSub_write_1__VAL_1 :
MUX_tlp_dmaPullRemainDWSub_write_1__VAL_2 ;
assign tlp_dmaPullRemainDWSub_EN =
WILL_FIRE_RL_tlp_dmaPullResponseHeader ||
WILL_FIRE_RL_tlp_dmaPullResponseBody ;
// register tlp_dmaReqTag
assign tlp_dmaReqTag_D_IN = tlp_dmaTag ;
assign tlp_dmaReqTag_EN = tlp_complTimerRunning_D_IN ;
// register tlp_dmaStartMark
assign tlp_dmaStartMark_D_IN = tlp_dmaStartMark_1_whas ;
assign tlp_dmaStartMark_EN = 1'd1 ;
// register tlp_dmaTag
assign tlp_dmaTag_D_IN = tlp_dmaTag + 5'd1 ;
assign tlp_dmaTag_EN = tlp_complTimerRunning_D_IN ;
// register tlp_doXmtMetaBody
assign tlp_doXmtMetaBody_D_IN = !WILL_FIRE_RL_tlp_dmaXmtMetaBody ;
assign tlp_doXmtMetaBody_EN =
WILL_FIRE_RL_tlp_dmaXmtMetaBody ||
WILL_FIRE_RL_tlp_dmaXmtMetaHead ;
// register tlp_doorSeqDwell
assign tlp_doorSeqDwell_D_IN =
(tlp_doorSeqDwell != 4'd0) ?
MUX_tlp_doorSeqDwell_write_1__VAL_1 :
4'd8 ;
assign tlp_doorSeqDwell_EN =
tlp_doorSeqDwell != 4'd0 || WILL_FIRE_RL_tlp_dmaXmtDoorbell ;
// register tlp_fabFlowAddr
assign tlp_fabFlowAddr_D_IN = bml_fabFlowAddr ;
assign tlp_fabFlowAddr_EN = 1'd1 ;
// register tlp_fabFlowAddrMS
assign tlp_fabFlowAddrMS_D_IN = bml_fabFlowBaseMS ;
assign tlp_fabFlowAddrMS_EN = 1'd1 ;
// register tlp_fabMesgAccu
always@(MUX_tlp_fabMesgAccu_write_1__SEL_1 or
tlp_fabMesgAddr or
WILL_FIRE_RL_tlp_dmaPushResponseHeader or
MUX_tlp_fabMesgAccu_write_1__VAL_2 or
WILL_FIRE_RL_tlp_dmaPullRequestFarMesg or
MUX_tlp_fabMesgAccu_write_1__VAL_3)
begin
case (1'b1) // synopsys parallel_case
MUX_tlp_fabMesgAccu_write_1__SEL_1:
tlp_fabMesgAccu_D_IN = tlp_fabMesgAddr;
WILL_FIRE_RL_tlp_dmaPushResponseHeader:
tlp_fabMesgAccu_D_IN = MUX_tlp_fabMesgAccu_write_1__VAL_2;
WILL_FIRE_RL_tlp_dmaPullRequestFarMesg:
tlp_fabMesgAccu_D_IN = MUX_tlp_fabMesgAccu_write_1__VAL_3;
default: tlp_fabMesgAccu_D_IN = 32'hAAAAAAAA /* unspecified value */ ;
endcase
end
assign tlp_fabMesgAccu_EN =
WILL_FIRE_RL_tlp_dmaRespBodyFarMeta ||
WILL_FIRE_RL_tlp_dmaResponseNearMetaBody ||
WILL_FIRE_RL_tlp_dmaPushResponseHeader ||
WILL_FIRE_RL_tlp_dmaPullRequestFarMesg ;
// register tlp_fabMesgAddr
assign tlp_fabMesgAddr_D_IN = bml_fabMesgAddr ;
assign tlp_fabMesgAddr_EN = 1'd1 ;
// register tlp_fabMesgAddrMS
assign tlp_fabMesgAddrMS_D_IN = bml_fabMesgBaseMS ;
assign tlp_fabMesgAddrMS_EN = 1'd1 ;
// register tlp_fabMeta
always@(WILL_FIRE_RL_tlp_dmaResponseNearMetaBody or
MUX_tlp_fabMeta_write_1__VAL_1 or
MUX_tlp_fabMeta_write_1__SEL_2 or
WILL_FIRE_RL_tlp_dmaRespBodyFarMeta or
MUX_tlp_fabMeta_write_1__VAL_3)
case (1'b1)
WILL_FIRE_RL_tlp_dmaResponseNearMetaBody:
tlp_fabMeta_D_IN = MUX_tlp_fabMeta_write_1__VAL_1;
MUX_tlp_fabMeta_write_1__SEL_2:
tlp_fabMeta_D_IN = 129'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
WILL_FIRE_RL_tlp_dmaRespBodyFarMeta:
tlp_fabMeta_D_IN = MUX_tlp_fabMeta_write_1__VAL_3;
default: tlp_fabMeta_D_IN =
129'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA /* unspecified value */ ;
endcase
assign tlp_fabMeta_EN =
WILL_FIRE_RL_tlp_dmaTailEventSender &&
(tlp_fabFlowAddrMS == 32'd0 || tlp_sentTail4DWHeader) ||
WILL_FIRE_RL_tlp_dmaResponseNearMetaBody ||
WILL_FIRE_RL_tlp_dmaRespBodyFarMeta ;
// register tlp_fabMetaAddr
assign tlp_fabMetaAddr_D_IN = bml_fabMetaAddr ;
assign tlp_fabMetaAddr_EN = 1'd1 ;
// register tlp_fabMetaAddrMS
assign tlp_fabMetaAddrMS_D_IN = bml_fabMetaBaseMS ;
assign tlp_fabMetaAddrMS_EN = 1'd1 ;
// register tlp_farBufReady
assign tlp_farBufReady_D_IN = tlp_farBufReady_1_whas ;
assign tlp_farBufReady_EN = 1'd1 ;
// register tlp_flowDiagCount
assign tlp_flowDiagCount_D_IN = tlp_flowDiagCount + 32'd1 ;
assign tlp_flowDiagCount_EN = WILL_FIRE_RL_tlp_dmaXmtDoorbell ;
// register tlp_gotResponseHeader
always@(WILL_FIRE_RL_tlp_dmaPullResponseBody or
tlp_dmaPullRemainDWSub_387_ULE_4___d1388 or
WILL_FIRE_RL_tlp_dmaPullResponseHeader or
tlp_inF_D_OUT or WILL_FIRE_RL_tlp_dmaPullRequestFarMesg)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_tlp_dmaPullResponseBody:
tlp_gotResponseHeader_D_IN =
!tlp_dmaPullRemainDWSub_387_ULE_4___d1388;
WILL_FIRE_RL_tlp_dmaPullResponseHeader:
tlp_gotResponseHeader_D_IN = tlp_inF_D_OUT[105:96] != 10'd1;
WILL_FIRE_RL_tlp_dmaPullRequestFarMesg:
tlp_gotResponseHeader_D_IN = 1'd0;
default: tlp_gotResponseHeader_D_IN = 1'b0 /* unspecified value */ ;
endcase
end
assign tlp_gotResponseHeader_EN =
WILL_FIRE_RL_tlp_dmaPullResponseBody ||
WILL_FIRE_RL_tlp_dmaPullResponseHeader ||
WILL_FIRE_RL_tlp_dmaPullRequestFarMesg ;
// register tlp_inIgnorePkt
assign tlp_inIgnorePkt_D_IN =
tlp_inF_D_OUT[110] || tlp_inF_D_OUT[125] ||
tlp_inF_D_OUT[124:120] != 5'b0 ;
assign tlp_inIgnorePkt_EN = WILL_FIRE_RL_tlp_tlpRcv && tlp_inF_D_OUT[152] ;
// register tlp_lastMetaV_0
assign tlp_lastMetaV_0_D_IN =
WILL_FIRE_RL_tlp_dmaResponseNearMetaHead ?
x__h42208 :
x__h58352 ;
assign tlp_lastMetaV_0_EN =
WILL_FIRE_RL_tlp_dmaResponseNearMetaHead ||
WILL_FIRE_RL_tlp_dmaRespHeadFarMeta ;
// register tlp_lastMetaV_1
assign tlp_lastMetaV_1_D_IN =
WILL_FIRE_RL_tlp_dmaResponseNearMetaBody ?
opcode__h44022 :
opcode__h60417 ;
assign tlp_lastMetaV_1_EN =
WILL_FIRE_RL_tlp_dmaResponseNearMetaBody ||
WILL_FIRE_RL_tlp_dmaRespBodyFarMeta ;
// register tlp_lastMetaV_2
assign tlp_lastMetaV_2_D_IN =
WILL_FIRE_RL_tlp_dmaResponseNearMetaBody ?
nowMS__h45280 :
nowMS__h61665 ;
assign tlp_lastMetaV_2_EN =
WILL_FIRE_RL_tlp_dmaResponseNearMetaBody ||
WILL_FIRE_RL_tlp_dmaRespBodyFarMeta ;
// register tlp_lastMetaV_3
assign tlp_lastMetaV_3_D_IN =
WILL_FIRE_RL_tlp_dmaResponseNearMetaBody ?
nowLS__h46239 :
nowLS__h62622 ;
assign tlp_lastMetaV_3_EN =
WILL_FIRE_RL_tlp_dmaResponseNearMetaBody ||
WILL_FIRE_RL_tlp_dmaRespBodyFarMeta ;
// register tlp_lastRuleFired
always@(WILL_FIRE_RL_tlp_dmaPullRequestFarMesg or
WILL_FIRE_RL_tlp_dmaRequestFarMeta or
WILL_FIRE_RL_tlp_dmaTailEventSender or
MUX_tlp_lastRuleFired_write_1__VAL_3 or
WILL_FIRE_RL_tlp_dmaPullResponseBody or
WILL_FIRE_RL_tlp_dmaPullResponseHeader or
WILL_FIRE_RL_tlp_dmaRespBodyFarMeta or
WILL_FIRE_RL_tlp_dmaPullTailEvent or
WILL_FIRE_RL_tlp_dmaRespHeadFarMeta)
case (1'b1)
WILL_FIRE_RL_tlp_dmaPullRequestFarMesg: tlp_lastRuleFired_D_IN = 4'd4;
WILL_FIRE_RL_tlp_dmaRequestFarMeta: tlp_lastRuleFired_D_IN = 4'd1;
WILL_FIRE_RL_tlp_dmaTailEventSender:
tlp_lastRuleFired_D_IN = MUX_tlp_lastRuleFired_write_1__VAL_3;
WILL_FIRE_RL_tlp_dmaPullResponseBody: tlp_lastRuleFired_D_IN = 4'd6;
WILL_FIRE_RL_tlp_dmaPullResponseHeader: tlp_lastRuleFired_D_IN = 4'd5;
WILL_FIRE_RL_tlp_dmaRespBodyFarMeta: tlp_lastRuleFired_D_IN = 4'd3;
WILL_FIRE_RL_tlp_dmaPullTailEvent: tlp_lastRuleFired_D_IN = 4'd7;
WILL_FIRE_RL_tlp_dmaRespHeadFarMeta: tlp_lastRuleFired_D_IN = 4'd2;
default: tlp_lastRuleFired_D_IN = 4'b1010 /* unspecified value */ ;
endcase
assign tlp_lastRuleFired_EN =
WILL_FIRE_RL_tlp_dmaTailEventSender ||
WILL_FIRE_RL_tlp_dmaRequestFarMeta ||
WILL_FIRE_RL_tlp_dmaRespHeadFarMeta ||
WILL_FIRE_RL_tlp_dmaRespBodyFarMeta ||
WILL_FIRE_RL_tlp_dmaPullRequestFarMesg ||
WILL_FIRE_RL_tlp_dmaPullResponseHeader ||
WILL_FIRE_RL_tlp_dmaPullResponseBody ||
WILL_FIRE_RL_tlp_dmaPullTailEvent ;
// register tlp_maxPayloadSize
assign tlp_maxPayloadSize_D_IN = 13'h0 ;
assign tlp_maxPayloadSize_EN = 1'b0 ;
// register tlp_maxReadReqSize
assign tlp_maxReadReqSize_D_IN = 13'h0 ;
assign tlp_maxReadReqSize_EN = 1'b0 ;
// register tlp_mesgComplReceived
always@(WILL_FIRE_RL_tlp_dmaPullResponseHeader or
MUX_tlp_mesgComplReceived_write_1__VAL_1 or
WILL_FIRE_RL_tlp_dmaPullResponseBody or
MUX_tlp_mesgComplReceived_write_1__VAL_2 or
WILL_FIRE_RL_tlp_dmaRespBodyFarMeta)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_tlp_dmaPullResponseHeader:
tlp_mesgComplReceived_D_IN =
MUX_tlp_mesgComplReceived_write_1__VAL_1;
WILL_FIRE_RL_tlp_dmaPullResponseBody:
tlp_mesgComplReceived_D_IN =
MUX_tlp_mesgComplReceived_write_1__VAL_2;
WILL_FIRE_RL_tlp_dmaRespBodyFarMeta: tlp_mesgComplReceived_D_IN = 17'd0;
default: tlp_mesgComplReceived_D_IN =
17'b01010101010101010 /* unspecified value */ ;
endcase
end
assign tlp_mesgComplReceived_EN =
WILL_FIRE_RL_tlp_dmaPullResponseHeader ||
WILL_FIRE_RL_tlp_dmaPullResponseBody ||
WILL_FIRE_RL_tlp_dmaRespBodyFarMeta ;
// register tlp_mesgLengthRemainPull
always@(WILL_FIRE_RL_tlp_dmaRespHeadFarMeta or
MUX_tlp_mesgLengthRemainPull_write_1__VAL_1 or
WILL_FIRE_RL_tlp_dmaRespBodyFarMeta or
MUX_tlp_mesgLengthRemainPull_write_1__VAL_2 or
WILL_FIRE_RL_tlp_dmaPullRequestFarMesg or
MUX_tlp_mesgLengthRemainPull_write_1__VAL_3)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_tlp_dmaRespHeadFarMeta:
tlp_mesgLengthRemainPull_D_IN =
MUX_tlp_mesgLengthRemainPull_write_1__VAL_1;
WILL_FIRE_RL_tlp_dmaRespBodyFarMeta:
tlp_mesgLengthRemainPull_D_IN =
MUX_tlp_mesgLengthRemainPull_write_1__VAL_2;
WILL_FIRE_RL_tlp_dmaPullRequestFarMesg:
tlp_mesgLengthRemainPull_D_IN =
MUX_tlp_mesgLengthRemainPull_write_1__VAL_3;
default: tlp_mesgLengthRemainPull_D_IN =
17'b01010101010101010 /* unspecified value */ ;
endcase
end
assign tlp_mesgLengthRemainPull_EN =
WILL_FIRE_RL_tlp_dmaRespHeadFarMeta ||
WILL_FIRE_RL_tlp_dmaRespBodyFarMeta ||
WILL_FIRE_RL_tlp_dmaPullRequestFarMesg ;
// register tlp_mesgLengthRemainPush
always@(WILL_FIRE_RL_tlp_dmaResponseNearMetaBody or
MUX_tlp_mesgLengthRemainPush_write_1__VAL_1 or
WILL_FIRE_RL_tlp_dmaResponseNearMetaHead or
MUX_tlp_mesgLengthRemainPush_write_1__VAL_2 or
WILL_FIRE_RL_tlp_dmaPushRequestMesg or
MUX_tlp_mesgLengthRemainPush_write_1__VAL_3)
case (1'b1)
WILL_FIRE_RL_tlp_dmaResponseNearMetaBody:
tlp_mesgLengthRemainPush_D_IN =
MUX_tlp_mesgLengthRemainPush_write_1__VAL_1;
WILL_FIRE_RL_tlp_dmaResponseNearMetaHead:
tlp_mesgLengthRemainPush_D_IN =
MUX_tlp_mesgLengthRemainPush_write_1__VAL_2;
WILL_FIRE_RL_tlp_dmaPushRequestMesg:
tlp_mesgLengthRemainPush_D_IN =
MUX_tlp_mesgLengthRemainPush_write_1__VAL_3;
default: tlp_mesgLengthRemainPush_D_IN =
17'b01010101010101010 /* unspecified value */ ;
endcase
assign tlp_mesgLengthRemainPush_EN =
WILL_FIRE_RL_tlp_dmaResponseNearMetaHead ||
WILL_FIRE_RL_tlp_dmaResponseNearMetaBody ||
WILL_FIRE_RL_tlp_dmaPushRequestMesg ;
// register tlp_nearBufReady
assign tlp_nearBufReady_D_IN = tlp_nearBufReady_1_whas ;
assign tlp_nearBufReady_EN = 1'd1 ;
// register tlp_outDwRemain
always@(WILL_FIRE_RL_tlp_dmaPushResponseHeader or
MUX_tlp_outDwRemain_write_1__VAL_1 or
MUX_tlp_tlpXmtBusy_write_1__PSEL_2 or
MUX_tlp_outDwRemain_write_1__VAL_2 or
WILL_FIRE_RL_tlp_dataXmt_Header or
MUX_tlp_outDwRemain_write_1__VAL_3)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_tlp_dmaPushResponseHeader:
tlp_outDwRemain_D_IN = MUX_tlp_outDwRemain_write_1__VAL_1;
MUX_tlp_tlpXmtBusy_write_1__PSEL_2:
tlp_outDwRemain_D_IN = MUX_tlp_outDwRemain_write_1__VAL_2;
WILL_FIRE_RL_tlp_dataXmt_Header:
tlp_outDwRemain_D_IN = MUX_tlp_outDwRemain_write_1__VAL_3;
default: tlp_outDwRemain_D_IN = 10'b1010101010 /* unspecified value */ ;
endcase
end
assign tlp_outDwRemain_EN =
WILL_FIRE_RL_tlp_dmaPushResponseHeader ||
WILL_FIRE_RL_tlp_dataXmt_Body ||
WILL_FIRE_RL_tlp_dmaPushResponseBody ||
WILL_FIRE_RL_tlp_dataXmt_Header ;
// register tlp_postSeqDwell
assign tlp_postSeqDwell_D_IN =
MUX_tlp_fabMeta_write_1__SEL_2 ?
MUX_tlp_postSeqDwell_write_1__VAL_1 :
MUX_tlp_postSeqDwell_write_1__VAL_2 ;
assign tlp_postSeqDwell_EN =
WILL_FIRE_RL_tlp_dmaTailEventSender &&
(tlp_fabFlowAddrMS == 32'd0 || tlp_sentTail4DWHeader) ||
tlp_postSeqDwell != 4'd0 ;
// register tlp_pullTagMatch
assign tlp_pullTagMatch_D_IN =
tlp_pullTagMatch_1_whas && tlp_pullTagMatch_1_wget ;
assign tlp_pullTagMatch_EN = 1'd1 ;
// register tlp_remDone
assign tlp_remDone_D_IN = tlp_remDone_1_whas ;
assign tlp_remDone_EN = 1'd1 ;
// register tlp_remMesgAccu
always@(MUX_tlp_fabMesgAccu_write_1__SEL_1 or
tlp_remMesgAddr or
WILL_FIRE_RL_tlp_dmaPushRequestMesg or
MUX_tlp_remMesgAccu_write_1__VAL_2 or
WILL_FIRE_RL_tlp_dmaPullResponseHeader or
MUX_tlp_remMesgAccu_write_1__VAL_3)
begin
case (1'b1) // synopsys parallel_case
MUX_tlp_fabMesgAccu_write_1__SEL_1:
tlp_remMesgAccu_D_IN = tlp_remMesgAddr;
WILL_FIRE_RL_tlp_dmaPushRequestMesg:
tlp_remMesgAccu_D_IN = MUX_tlp_remMesgAccu_write_1__VAL_2;
WILL_FIRE_RL_tlp_dmaPullResponseHeader:
tlp_remMesgAccu_D_IN = MUX_tlp_remMesgAccu_write_1__VAL_3;
default: tlp_remMesgAccu_D_IN =
16'b1010101010101010 /* unspecified value */ ;
endcase
end
assign tlp_remMesgAccu_EN =
WILL_FIRE_RL_tlp_dmaRespBodyFarMeta ||
WILL_FIRE_RL_tlp_dmaResponseNearMetaBody ||
WILL_FIRE_RL_tlp_dmaPushRequestMesg ||
WILL_FIRE_RL_tlp_dmaPullResponseHeader ;
// register tlp_remMesgAddr
assign tlp_remMesgAddr_D_IN = bml_remMesgAddr ;
assign tlp_remMesgAddr_EN = 1'd1 ;
// register tlp_remMetaAddr
assign tlp_remMetaAddr_D_IN = bml_remMetaAddr ;
assign tlp_remMetaAddr_EN = 1'd1 ;
// register tlp_remStart
assign tlp_remStart_D_IN = tlp_remStart_1_whas ;
assign tlp_remStart_EN = 1'd1 ;
// register tlp_reqMesgInFlight
always@(WILL_FIRE_RL_tlp_dmaPullResponseHeader or
tlp_dmaPullRemainDWLen or
WILL_FIRE_RL_tlp_dmaPullResponseBody or
MUX_tlp_reqMesgInFlight_write_1__VAL_2 or
WILL_FIRE_RL_tlp_dmaPullRequestFarMesg)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_tlp_dmaPullResponseHeader:
tlp_reqMesgInFlight_D_IN = tlp_dmaPullRemainDWLen != 10'd1;
WILL_FIRE_RL_tlp_dmaPullResponseBody:
tlp_reqMesgInFlight_D_IN = MUX_tlp_reqMesgInFlight_write_1__VAL_2;
WILL_FIRE_RL_tlp_dmaPullRequestFarMesg: tlp_reqMesgInFlight_D_IN = 1'd1;
default: tlp_reqMesgInFlight_D_IN = 1'b0 /* unspecified value */ ;
endcase
end
assign tlp_reqMesgInFlight_EN =
WILL_FIRE_RL_tlp_dmaPullResponseHeader ||
WILL_FIRE_RL_tlp_dmaPullResponseBody ||
WILL_FIRE_RL_tlp_dmaPullRequestFarMesg ;
// register tlp_reqMetaBodyInFlight
assign tlp_reqMetaBodyInFlight_D_IN = !WILL_FIRE_RL_tlp_dmaRespBodyFarMeta ;
assign tlp_reqMetaBodyInFlight_EN =
WILL_FIRE_RL_tlp_dmaRespBodyFarMeta ||
WILL_FIRE_RL_tlp_dmaRespHeadFarMeta ;
// register tlp_reqMetaInFlight
always@(WILL_FIRE_RL_tlp_dmaRequestFarMeta or
WILL_FIRE_RL_tlp_dmaResponseNearMetaBody or
WILL_FIRE_RL_tlp_dmaRespHeadFarMeta or
WILL_FIRE_RL_tlp_dmaRequestNearMeta)
case (1'b1)
WILL_FIRE_RL_tlp_dmaRequestFarMeta: tlp_reqMetaInFlight_D_IN = 1'd1;
WILL_FIRE_RL_tlp_dmaResponseNearMetaBody ||
WILL_FIRE_RL_tlp_dmaRespHeadFarMeta:
tlp_reqMetaInFlight_D_IN = 1'd0;
WILL_FIRE_RL_tlp_dmaRequestNearMeta: tlp_reqMetaInFlight_D_IN = 1'd1;
default: tlp_reqMetaInFlight_D_IN = 1'b0 /* unspecified value */ ;
endcase
assign tlp_reqMetaInFlight_EN =
WILL_FIRE_RL_tlp_dmaRespHeadFarMeta ||
WILL_FIRE_RL_tlp_dmaResponseNearMetaBody ||
WILL_FIRE_RL_tlp_dmaRequestFarMeta ||
WILL_FIRE_RL_tlp_dmaRequestNearMeta ;
// register tlp_sentTail4DWHeader
assign tlp_sentTail4DWHeader_D_IN = !tlp_sentTail4DWHeader ;
assign tlp_sentTail4DWHeader_EN = MUX_tlp_tlpXmtBusy_write_1__SEL_3 ;
// register tlp_srcMesgAccu
assign tlp_srcMesgAccu_D_IN =
WILL_FIRE_RL_tlp_dmaResponseNearMetaBody ?
tlp_fabMesgAddr :
MUX_tlp_srcMesgAccu_write_1__VAL_2 ;
assign tlp_srcMesgAccu_EN =
WILL_FIRE_RL_tlp_dmaResponseNearMetaBody ||
WILL_FIRE_RL_tlp_dmaPushRequestMesg ;
// register tlp_tlpBRAM_debugBdata
assign tlp_tlpBRAM_debugBdata_D_IN =
{ bram_3_serverAdapterA_outData_outData_wget[7:0],
bram_3_serverAdapterA_outData_outData_wget[15:8],
bram_3_serverAdapterA_outData_outData_wget[23:16],
bram_3_serverAdapterA_outData_outData_wget[31:24],
bram_2_serverAdapterA_outData_outData_wget[7:0],
bram_2_serverAdapterA_outData_outData_wget[15:8],
bram_2_serverAdapterA_outData_outData_wget[23:16],
bram_2_serverAdapterA_outData_outData_wget[31:24],
bram_1_serverAdapterA_outData_outData_wget[7:0],
bram_1_serverAdapterA_outData_outData_wget[15:8],
bram_1_serverAdapterA_outData_outData_wget[23:16],
bram_1_serverAdapterA_outData_outData_wget[31:24],
bram_0_serverAdapterA_outData_outData_wget[7:0],
bram_0_serverAdapterA_outData_outData_wget[15:8],
bram_0_serverAdapterA_outData_outData_wget[23:16],
bram_0_serverAdapterA_outData_outData_wget[31:24] } ;
assign tlp_tlpBRAM_debugBdata_EN = WILL_FIRE_RL_tlp_tlpBRAM_read_NextResp ;
// register tlp_tlpBRAM_rdRespDwRemain
assign tlp_tlpBRAM_rdRespDwRemain_D_IN =
WILL_FIRE_RL_tlp_tlpBRAM_read_FirstResp ?
MUX_tlp_tlpBRAM_rdRespDwRemain_write_1__VAL_1 :
MUX_tlp_tlpBRAM_rdRespDwRemain_write_1__VAL_2 ;
assign tlp_tlpBRAM_rdRespDwRemain_EN =
WILL_FIRE_RL_tlp_tlpBRAM_read_FirstResp ||
WILL_FIRE_RL_tlp_tlpBRAM_read_NextResp ;
// register tlp_tlpBRAM_readHeaderSent
assign tlp_tlpBRAM_readHeaderSent_D_IN =
MUX_tlp_tlpBRAM_readHeaderSent_write_1__SEL_1 ;
assign tlp_tlpBRAM_readHeaderSent_EN =
WILL_FIRE_RL_tlp_tlpBRAM_read_FirstResp &&
(tlp_tlpBRAM_readReq_D_OUT[28:19] != 10'd1 ||
tlp_tlpBRAM_readReq_D_OUT[60]) ||
WILL_FIRE_RL_tlp_tlpBRAM_read_NextResp &&
tlp_tlpBRAM_rdRespDwRemain_16_ULE_4___d918 ;
// register tlp_tlpBRAM_readNxtDWAddr
assign tlp_tlpBRAM_readNxtDWAddr_D_IN =
WILL_FIRE_RL_tlp_tlpBRAM_read_FirstReq ?
MUX_tlp_tlpBRAM_readNxtDWAddr_write_1__VAL_1 :
MUX_tlp_tlpBRAM_readNxtDWAddr_write_1__VAL_2 ;
assign tlp_tlpBRAM_readNxtDWAddr_EN =
WILL_FIRE_RL_tlp_tlpBRAM_read_FirstReq ||
WILL_FIRE_RL_tlp_tlpBRAM_read_NextReq ;
// register tlp_tlpBRAM_readRemainDWLen
assign tlp_tlpBRAM_readRemainDWLen_D_IN =
WILL_FIRE_RL_tlp_tlpBRAM_read_FirstReq ?
MUX_tlp_tlpBRAM_readRemainDWLen_write_1__VAL_1 :
MUX_tlp_tlpBRAM_readRemainDWLen_write_1__VAL_2 ;
assign tlp_tlpBRAM_readRemainDWLen_EN =
WILL_FIRE_RL_tlp_tlpBRAM_read_FirstReq ||
WILL_FIRE_RL_tlp_tlpBRAM_read_NextReq ;
// register tlp_tlpBRAM_readStarted
assign tlp_tlpBRAM_readStarted_D_IN =
MUX_tlp_tlpBRAM_readStarted_write_1__SEL_1 ;
assign tlp_tlpBRAM_readStarted_EN =
WILL_FIRE_RL_tlp_tlpBRAM_read_FirstReq &&
(tlp_tlpBRAM_mReqF_D_OUT[28:19] != 10'd1 ||
tlp_tlpBRAM_mReqF_D_OUT[60]) ||
WILL_FIRE_RL_tlp_tlpBRAM_read_NextReq &&
tlp_tlpBRAM_readRemainDWLen_74_ULE_4___d775 ;
// register tlp_tlpBRAM_writeDWAddr
assign tlp_tlpBRAM_writeDWAddr_D_IN =
WILL_FIRE_RL_tlp_tlpBRAM_writeReq ?
MUX_tlp_tlpBRAM_writeDWAddr_write_1__VAL_1 :
MUX_tlp_tlpBRAM_writeDWAddr_write_1__VAL_2 ;
assign tlp_tlpBRAM_writeDWAddr_EN =
WILL_FIRE_RL_tlp_tlpBRAM_writeReq ||
WILL_FIRE_RL_tlp_tlpBRAM_writeData ;
// register tlp_tlpBRAM_writeLastBE
assign tlp_tlpBRAM_writeLastBE_D_IN = tlp_tlpBRAM_mReqF_D_OUT[35:32] ;
assign tlp_tlpBRAM_writeLastBE_EN = WILL_FIRE_RL_tlp_tlpBRAM_writeReq ;
// register tlp_tlpBRAM_writeRemainDWLen
assign tlp_tlpBRAM_writeRemainDWLen_D_IN =
WILL_FIRE_RL_tlp_tlpBRAM_writeReq ?
MUX_tlp_tlpBRAM_writeRemainDWLen_write_1__VAL_1 :
MUX_tlp_tlpBRAM_writeRemainDWLen_write_1__VAL_2 ;
assign tlp_tlpBRAM_writeRemainDWLen_EN =
WILL_FIRE_RL_tlp_tlpBRAM_writeReq ||
WILL_FIRE_RL_tlp_tlpBRAM_writeData ;
// register tlp_tlpMetaSent
assign tlp_tlpMetaSent_D_IN = WILL_FIRE_RL_tlp_dmaXmtMetaBody ;
assign tlp_tlpMetaSent_EN =
WILL_FIRE_RL_tlp_dmaXmtTailEvent ||
WILL_FIRE_RL_tlp_dmaXmtMetaBody ;
// register tlp_tlpRcvBusy
always@(WILL_FIRE_RL_tlp_dmaPullResponseBody or
tlp_dmaPullRemainDWSub_387_ULE_4___d1388 or
WILL_FIRE_RL_tlp_dmaPullResponseHeader or
tlp_inF_D_OUT or WILL_FIRE_RL_tlp_tlpRcv)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_tlp_dmaPullResponseBody:
tlp_tlpRcvBusy_D_IN = !tlp_dmaPullRemainDWSub_387_ULE_4___d1388;
WILL_FIRE_RL_tlp_dmaPullResponseHeader:
tlp_tlpRcvBusy_D_IN = tlp_inF_D_OUT[105:96] != 10'd1;
WILL_FIRE_RL_tlp_tlpRcv: tlp_tlpRcvBusy_D_IN = !tlp_inF_D_OUT[151];
default: tlp_tlpRcvBusy_D_IN = 1'b0 /* unspecified value */ ;
endcase
end
assign tlp_tlpRcvBusy_EN =
WILL_FIRE_RL_tlp_dmaPullResponseBody ||
WILL_FIRE_RL_tlp_dmaPullResponseHeader ||
WILL_FIRE_RL_tlp_tlpRcv ;
// register tlp_tlpXmtBusy
always@(MUX_tlp_tlpXmtBusy_write_1__SEL_1 or
MUX_tlp_tlpXmtBusy_write_1__VAL_1 or
MUX_tlp_tlpXmtBusy_write_1__SEL_3 or
tlp_sentTail4DWHeader or
MUX_tlp_tlpXmtBusy_write_1__SEL_2 or
WILL_FIRE_RL_tlp_dmaXmtMetaBody or
MUX_tlp_tlpXmtBusy_write_1__SEL_4 or
WILL_FIRE_RL_tlp_dmaXmtMetaHead)
begin
case (1'b1) // synopsys parallel_case
MUX_tlp_tlpXmtBusy_write_1__SEL_1:
tlp_tlpXmtBusy_D_IN = MUX_tlp_tlpXmtBusy_write_1__VAL_1;
MUX_tlp_tlpXmtBusy_write_1__SEL_3:
tlp_tlpXmtBusy_D_IN = !tlp_sentTail4DWHeader;
MUX_tlp_tlpXmtBusy_write_1__SEL_2 || WILL_FIRE_RL_tlp_dmaXmtMetaBody:
tlp_tlpXmtBusy_D_IN = 1'd0;
MUX_tlp_tlpXmtBusy_write_1__SEL_4 || WILL_FIRE_RL_tlp_dmaXmtMetaHead:
tlp_tlpXmtBusy_D_IN = 1'd1;
default: tlp_tlpXmtBusy_D_IN = 1'b0 /* unspecified value */ ;
endcase
end
assign tlp_tlpXmtBusy_EN =
WILL_FIRE_RL_tlp_dmaPushResponseHeader && _dfoo5 ||
(WILL_FIRE_RL_tlp_dataXmt_Body ||
WILL_FIRE_RL_tlp_dmaPushResponseBody) &&
tlp_outDwRemain_129_ULE_4___d1130 ||
WILL_FIRE_RL_tlp_dmaTailEventSender &&
tlp_fabFlowAddrMS != 32'd0 ||
WILL_FIRE_RL_tlp_dataXmt_Header &&
!tlp_tlpBRAM_mRespF_first__000_BITS_71_TO_62_10_ETC___d1102 ||
WILL_FIRE_RL_tlp_dmaXmtMetaBody ||
WILL_FIRE_RL_tlp_dmaXmtMetaHead ;
// register tlp_xmtMetaInFlight
assign tlp_xmtMetaInFlight_D_IN = !WILL_FIRE_RL_tlp_dmaXmtTailEvent ;
assign tlp_xmtMetaInFlight_EN =
WILL_FIRE_RL_tlp_dmaXmtTailEvent ||
WILL_FIRE_RL_tlp_dmaXmtMetaHead ;
// register tlp_xmtMetaOK
always@(WILL_FIRE_RL_tlp_dmaResponseNearMetaBody or
tlp_mesgLengthRemainPush or
WILL_FIRE_RL_tlp_dmaXmtMetaHead or
MUX_tlp_xmtMetaOK_write_1__SEL_3 or
MUX_tlp_xmtMetaOK_write_1__SEL_4)
case (1'b1)
WILL_FIRE_RL_tlp_dmaResponseNearMetaBody:
tlp_xmtMetaOK_D_IN = tlp_mesgLengthRemainPush == 17'd0;
WILL_FIRE_RL_tlp_dmaXmtMetaHead: tlp_xmtMetaOK_D_IN = 1'd0;
MUX_tlp_xmtMetaOK_write_1__SEL_3 || MUX_tlp_xmtMetaOK_write_1__SEL_4:
tlp_xmtMetaOK_D_IN = 1'd1;
default: tlp_xmtMetaOK_D_IN = 1'b0 /* unspecified value */ ;
endcase
assign tlp_xmtMetaOK_EN =
WILL_FIRE_RL_tlp_dmaPushResponseHeader &&
tlp_fabMesgAddrMS == 32'd0 &&
tlp_tlpBRAM_mRespF_D_OUT[71:62] == 10'd1 &&
tlp_tlpBRAM_mRespF_D_OUT[42:35] == 8'h01 ||
WILL_FIRE_RL_tlp_dmaPushResponseBody &&
tlp_outDwRemain_129_ULE_4___d1130 &&
tlp_tlpBRAM_mRespF_D_OUT[135:128] == 8'h01 ||
WILL_FIRE_RL_tlp_dmaResponseNearMetaBody ||
WILL_FIRE_RL_tlp_dmaXmtMetaHead ;
// register wci_cEdge
assign wci_cEdge_D_IN = wci_reqF_D_OUT[36:34] ;
assign wci_cEdge_EN = WILL_FIRE_RL_wci_ctl_op_start ;
// register wci_cState
assign wci_cState_D_IN = wci_nState ;
assign wci_cState_EN =
WILL_FIRE_RL_wci_ctl_op_complete && !wci_illegalEdge ;
// register wci_ctlAckReg
assign wci_ctlAckReg_D_IN = wci_ctlAckReg_1_whas ;
assign wci_ctlAckReg_EN = 1'd1 ;
// register wci_ctlOpActive
assign wci_ctlOpActive_D_IN = !WILL_FIRE_RL_wci_ctl_op_complete ;
assign wci_ctlOpActive_EN =
WILL_FIRE_RL_wci_ctl_op_complete ||
WILL_FIRE_RL_wci_ctl_op_start ;
// register wci_illegalEdge
assign wci_illegalEdge_D_IN =
!MUX_wci_illegalEdge_write_1__SEL_1 &&
MUX_wci_illegalEdge_write_1__VAL_2 ;
assign wci_illegalEdge_EN =
WILL_FIRE_RL_wci_ctl_op_complete && wci_illegalEdge ||
MUX_wci_illegalEdge_write_1__SEL_2 ;
// register wci_isReset_isInReset
assign wci_isReset_isInReset_D_IN = 1'd0 ;
assign wci_isReset_isInReset_EN = wci_isReset_isInReset ;
// register wci_nState
always@(wci_reqF_D_OUT)
begin
case (wci_reqF_D_OUT[36:34])
3'd0: wci_nState_D_IN = 3'd1;
3'd1: wci_nState_D_IN = 3'd2;
3'd2: wci_nState_D_IN = 3'd3;
default: wci_nState_D_IN = 3'd0;
endcase
end
assign wci_nState_EN =
WILL_FIRE_RL_wci_ctl_op_start &&
(wci_reqF_D_OUT[36:34] == 3'd0 && wci_cState == 3'd0 ||
wci_reqF_D_OUT[36:34] == 3'd1 &&
(wci_cState == 3'd1 || wci_cState == 3'd3) ||
wci_reqF_D_OUT[36:34] == 3'd2 && wci_cState == 3'd2 ||
wci_reqF_D_OUT[36:34] == 3'd3 &&
(wci_cState == 3'd3 || wci_cState == 3'd2 ||
wci_cState == 3'd1)) ;
// register wci_reqF_countReg
assign wci_reqF_countReg_D_IN =
(wci_wciReq_wget[71:69] != 3'd0) ?
wci_reqF_countReg + 2'd1 :
wci_reqF_countReg - 2'd1 ;
assign wci_reqF_countReg_EN =
(wci_wciReq_wget[71:69] != 3'd0) != wci_reqF_r_deq_whas ;
// register wci_respF_cntr_r
assign wci_respF_cntr_r_D_IN =
WILL_FIRE_RL_wci_respF_decCtr ?
wci_respF_cntr_r_90_MINUS_1___d499 :
MUX_wci_respF_cntr_r_write_1__VAL_2 ;
assign wci_respF_cntr_r_EN =
WILL_FIRE_RL_wci_respF_decCtr || WILL_FIRE_RL_wci_respF_incCtr ;
// register wci_respF_q_0
always@(MUX_wci_respF_q_0_write_1__SEL_1 or
MUX_wci_respF_q_0_write_1__VAL_1 or
MUX_wci_respF_q_0_write_1__SEL_2 or
MUX_wci_respF_q_0_write_1__VAL_2 or
WILL_FIRE_RL_wci_respF_decCtr or wci_respF_q_1)
begin
case (1'b1) // synopsys parallel_case
MUX_wci_respF_q_0_write_1__SEL_1:
wci_respF_q_0_D_IN = MUX_wci_respF_q_0_write_1__VAL_1;
MUX_wci_respF_q_0_write_1__SEL_2:
wci_respF_q_0_D_IN = MUX_wci_respF_q_0_write_1__VAL_2;
WILL_FIRE_RL_wci_respF_decCtr: wci_respF_q_0_D_IN = wci_respF_q_1;
default: wci_respF_q_0_D_IN = 34'h2AAAAAAAA /* unspecified value */ ;
endcase
end
assign wci_respF_q_0_EN =
WILL_FIRE_RL_wci_respF_both && _dfoo3 ||
WILL_FIRE_RL_wci_respF_incCtr && wci_respF_cntr_r == 2'd0 ||
WILL_FIRE_RL_wci_respF_decCtr ;
// register wci_respF_q_1
always@(MUX_wci_respF_q_1_write_1__SEL_1 or
MUX_wci_respF_q_1_write_1__VAL_1 or
MUX_wci_respF_q_1_write_1__SEL_2 or
MUX_wci_respF_q_0_write_1__VAL_2 or WILL_FIRE_RL_wci_respF_decCtr)
begin
case (1'b1) // synopsys parallel_case
MUX_wci_respF_q_1_write_1__SEL_1:
wci_respF_q_1_D_IN = MUX_wci_respF_q_1_write_1__VAL_1;
MUX_wci_respF_q_1_write_1__SEL_2:
wci_respF_q_1_D_IN = MUX_wci_respF_q_0_write_1__VAL_2;
WILL_FIRE_RL_wci_respF_decCtr: wci_respF_q_1_D_IN = 34'h0AAAAAAAA;
default: wci_respF_q_1_D_IN = 34'h2AAAAAAAA /* unspecified value */ ;
endcase
end
assign wci_respF_q_1_EN =
WILL_FIRE_RL_wci_respF_both && _dfoo1 ||
WILL_FIRE_RL_wci_respF_incCtr && wci_respF_cntr_r == 2'd1 ||
WILL_FIRE_RL_wci_respF_decCtr ;
// register wci_sFlagReg
assign wci_sFlagReg_D_IN = 1'b0 ;
assign wci_sFlagReg_EN = 1'd1 ;
// register wci_sThreadBusy_d
assign wci_sThreadBusy_d_D_IN = 1'b0 ;
assign wci_sThreadBusy_d_EN = 1'd1 ;
// register wmi_addr
assign wmi_addr_D_IN =
MUX_wmi_doneWithMesg_write_1__PSEL_1 ?
MUX_wmi_addr_write_1__VAL_1 :
wmi_wmi_reqF_D_OUT[25:12] ;
assign wmi_addr_EN =
WILL_FIRE_RL_wmi_doReadReq || WILL_FIRE_RL_wmi_doWriteReq ||
WILL_FIRE_RL_wmi_getRequest ;
// register wmi_bufDwell
assign wmi_bufDwell_D_IN =
(MUX_wmi_bufDwell_write_1__SEL_1 ||
WILL_FIRE_RL_wmi_doWriteFinalize) ?
2'd3 :
MUX_wmi_bufDwell_write_1__VAL_3 ;
assign wmi_bufDwell_EN =
WILL_FIRE_RL_wmi_doReadReq && wmi_bytesRemainReq == 14'd16 &&
wmi_doneWithMesg ||
wmi_bufDwell != 2'd0 ||
WILL_FIRE_RL_wmi_doWriteFinalize ;
// register wmi_bytesRemainReq
assign wmi_bytesRemainReq_D_IN =
MUX_wmi_doneWithMesg_write_1__PSEL_1 ?
MUX_wmi_bytesRemainReq_write_1__VAL_1 :
MUX_wmi_bytesRemainReq_write_1__VAL_2 ;
assign wmi_bytesRemainReq_EN =
WILL_FIRE_RL_wmi_doReadReq || WILL_FIRE_RL_wmi_doWriteReq ||
WILL_FIRE_RL_wmi_getRequest ;
// register wmi_bytesRemainResp
assign wmi_bytesRemainResp_D_IN =
MUX_wmi_bytesRemainResp_write_1__SEL_1 ?
MUX_wmi_bytesRemainReq_write_1__VAL_2 :
MUX_wmi_bytesRemainResp_write_1__VAL_2 ;
assign wmi_bytesRemainResp_EN =
WILL_FIRE_RL_wmi_getRequest &&
wmi_wmi_reqF_D_OUT[31:29] == 3'd2 ||
WILL_FIRE_RL_wmi_doReadResp ;
// register wmi_doneWithMesg
assign wmi_doneWithMesg_D_IN =
!MUX_wmi_doneWithMesg_write_1__SEL_1 && wmi_wmi_reqF_D_OUT[27] ;
assign wmi_doneWithMesg_EN =
(WILL_FIRE_RL_wmi_doReadReq || WILL_FIRE_RL_wmi_doWriteReq) &&
wmi_bytesRemainReq == 14'd16 &&
wmi_doneWithMesg ||
WILL_FIRE_RL_wmi_getRequest ;
// register wmi_lastMesg
assign wmi_lastMesg_D_IN = wmi_thisMesg ;
assign wmi_lastMesg_EN = WILL_FIRE_RL_wmi_doWriteFinalize ;
// register wmi_lclMesgAddr
assign wmi_lclMesgAddr_D_IN = bml_lclMesgAddr[14:0] ;
assign wmi_lclMesgAddr_EN = 1'd1 ;
// register wmi_lclMetaAddr
assign wmi_lclMetaAddr_D_IN = bml_lclMetaAddr[14:0] ;
assign wmi_lclMetaAddr_EN = 1'd1 ;
// register wmi_mesgBufReady
assign wmi_mesgBufReady_D_IN = wmi_mesgBufReady_1_whas ;
assign wmi_mesgBufReady_EN = 1'd1 ;
// register wmi_mesgBusy
assign wmi_mesgBusy_D_IN = wmi_bufDwell != 2'd1 ;
assign wmi_mesgBusy_EN =
wmi_bufDwell == 2'd1 || WILL_FIRE_RL_wmi_getRequest ;
// register wmi_mesgCount
assign wmi_mesgCount_D_IN =
MUX_wmi_bufDwell_write_1__SEL_1 ?
MUX_wmi_mesgCount_write_1__VAL_1 :
MUX_wmi_mesgCount_write_1__VAL_1 ;
assign wmi_mesgCount_EN = wmi_mesgDone_1_whas ;
// register wmi_mesgDone
assign wmi_mesgDone_D_IN = wmi_mesgDone_1_whas ;
assign wmi_mesgDone_EN = 1'd1 ;
// register wmi_mesgMeta
assign wmi_mesgMeta_D_IN =
MUX_wmi_bufDwell_write_1__SEL_1 ?
129'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA :
MUX_wmi_mesgMeta_write_1__VAL_2 ;
assign wmi_mesgMeta_EN =
WILL_FIRE_RL_wmi_doReadReq && wmi_bytesRemainReq == 14'd16 &&
wmi_doneWithMesg ||
WILL_FIRE_RL_wmi_respMetadata ;
// register wmi_mesgStart
assign wmi_mesgStart_D_IN = wmi_mesgStart_1_whas ;
assign wmi_mesgStart_EN = 1'd1 ;
// register wmi_metaBusy
assign wmi_metaBusy_D_IN = !WILL_FIRE_RL_wmi_respMetadata ;
assign wmi_metaBusy_EN =
WILL_FIRE_RL_wmi_respMetadata || WILL_FIRE_RL_wmi_reqMetadata ;
// register wmi_p4B
assign wmi_p4B_D_IN =
MUX_wmi_bytesRemainResp_write_1__SEL_1 ?
wmi_wmi_reqF_D_OUT[15:14] :
wmi_p4B ;
assign wmi_p4B_EN =
WILL_FIRE_RL_wmi_getRequest &&
wmi_wmi_reqF_D_OUT[31:29] == 3'd2 ||
WILL_FIRE_RL_wmi_doReadResp ;
// register wmi_rdActive
assign wmi_rdActive_D_IN =
!MUX_wmi_rdActive_write_1__SEL_1 &&
wmi_wmi_reqF_D_OUT[31:29] == 3'd2 ;
assign wmi_rdActive_EN =
WILL_FIRE_RL_wmi_doReadReq && wmi_bytesRemainReq == 14'd16 ||
WILL_FIRE_RL_wmi_getRequest ;
// register wmi_reqCount
assign wmi_reqCount_D_IN = wmi_reqCount + 16'd1 ;
assign wmi_reqCount_EN = WILL_FIRE_RL_wmi_getRequest ;
// register wmi_thisMesg
assign wmi_thisMesg_D_IN =
{ wmi_mesgCount[7:0],
wmi_wmi_mFlagF_D_OUT[31:24],
wmi_wmi_mFlagF_D_OUT[15:0] } ;
assign wmi_thisMesg_EN = WILL_FIRE_RL_wmi_doWriteFinalize ;
// register wmi_wmi_blockReq
assign wmi_wmi_blockReq_D_IN =
!MUX_wmi_bufDwell_write_1__SEL_1 &&
!WILL_FIRE_RL_wmi_doWriteFinalize ;
assign wmi_wmi_blockReq_EN =
WILL_FIRE_RL_wmi_getRequest && wmi_wmi_reqF_D_OUT[28] &&
wmi_wmi_reqF_D_OUT[27] ||
WILL_FIRE_RL_wmi_doReadReq && wmi_bytesRemainReq == 14'd16 &&
wmi_doneWithMesg ||
WILL_FIRE_RL_wmi_doWriteFinalize ;
// register wmi_wmi_dhF_countReg
assign wmi_wmi_dhF_countReg_D_IN =
MUX_wmi_wmi_dhF_levelsValid_write_1__SEL_2 ?
wmi_wmi_dhF_countReg + 2'd1 :
wmi_wmi_dhF_countReg - 2'd1 ;
assign wmi_wmi_dhF_countReg_EN =
MUX_wmi_wmi_dhF_levelsValid_write_1__SEL_2 !=
WILL_FIRE_RL_wmi_doWriteReq ;
// register wmi_wmi_dhF_levelsValid
assign wmi_wmi_dhF_levelsValid_D_IN = WILL_FIRE_RL_wmi_wmi_dhF_reset ;
assign wmi_wmi_dhF_levelsValid_EN =
wmi_wmi_dhF_FULL_N && wmi_wmi_operateD && wmi_wmi_peerIsReady &&
wmi_wmi_wmiDh_wget[145] ||
WILL_FIRE_RL_wmi_doWriteReq ||
WILL_FIRE_RL_wmi_wmi_dhF_reset ;
// register wmi_wmi_errorSticky
assign wmi_wmi_errorSticky_D_IN = 1'b0 ;
assign wmi_wmi_errorSticky_EN = 1'b0 ;
// register wmi_wmi_isReset_isInReset
assign wmi_wmi_isReset_isInReset_D_IN = 1'd0 ;
assign wmi_wmi_isReset_isInReset_EN = wmi_wmi_isReset_isInReset ;
// register wmi_wmi_mFlagF_countReg
assign wmi_wmi_mFlagF_countReg_D_IN =
MUX_wmi_wmi_mFlagF_levelsValid_write_1__SEL_2 ?
wmi_wmi_mFlagF_countReg + 2'd1 :
wmi_wmi_mFlagF_countReg - 2'd1 ;
assign wmi_wmi_mFlagF_countReg_EN =
MUX_wmi_wmi_mFlagF_levelsValid_write_1__SEL_2 !=
WILL_FIRE_RL_wmi_doWriteFinalize ;
// register wmi_wmi_mFlagF_levelsValid
assign wmi_wmi_mFlagF_levelsValid_D_IN = WILL_FIRE_RL_wmi_wmi_mFlagF_reset ;
assign wmi_wmi_mFlagF_levelsValid_EN =
wmi_wmi_mFlagF_FULL_N && wmi_wmi_operateD &&
wmi_wmi_peerIsReady &&
wmi_wmi_wmiReq_wget[31:29] != 3'd0 &&
wmi_wmi_wmiReq_wget[27] ||
WILL_FIRE_RL_wmi_doWriteFinalize ||
WILL_FIRE_RL_wmi_wmi_mFlagF_reset ;
// register wmi_wmi_operateD
assign wmi_wmi_operateD_D_IN = wci_cState == 3'd2 ;
assign wmi_wmi_operateD_EN = 1'd1 ;
// register wmi_wmi_peerIsReady
assign wmi_wmi_peerIsReady_D_IN = wmiS0_MReset_n ;
assign wmi_wmi_peerIsReady_EN = 1'd1 ;
// register wmi_wmi_reqF_countReg
assign wmi_wmi_reqF_countReg_D_IN =
MUX_wmi_wmi_reqF_levelsValid_write_1__SEL_2 ?
wmi_wmi_reqF_countReg + 2'd1 :
wmi_wmi_reqF_countReg - 2'd1 ;
assign wmi_wmi_reqF_countReg_EN =
MUX_wmi_wmi_reqF_levelsValid_write_1__SEL_2 !=
WILL_FIRE_RL_wmi_getRequest ;
// register wmi_wmi_reqF_levelsValid
assign wmi_wmi_reqF_levelsValid_D_IN = WILL_FIRE_RL_wmi_wmi_reqF_reset ;
assign wmi_wmi_reqF_levelsValid_EN =
wmi_wmi_reqF_FULL_N && wmi_wmi_operateD && wmi_wmi_peerIsReady &&
wmi_wmi_wmiReq_wget[31:29] != 3'd0 ||
WILL_FIRE_RL_wmi_getRequest ||
WILL_FIRE_RL_wmi_wmi_reqF_reset ;
// register wmi_wmi_respF_cntr_r
assign wmi_wmi_respF_cntr_r_D_IN =
WILL_FIRE_RL_wmi_wmi_respF_decCtr ?
wmi_wmi_respF_cntr_r_582_MINUS_1___d1590 :
MUX_wmi_wmi_respF_cntr_r_write_1__VAL_2 ;
assign wmi_wmi_respF_cntr_r_EN =
WILL_FIRE_RL_wmi_wmi_respF_decCtr ||
WILL_FIRE_RL_wmi_wmi_respF_incCtr ;
// register wmi_wmi_respF_q_0
always@(MUX_wmi_wmi_respF_q_0_write_1__SEL_1 or
MUX_wmi_wmi_respF_q_0_write_1__VAL_1 or
MUX_wmi_wmi_respF_q_0_write_1__SEL_2 or
MUX_wmi_wmi_respF_q_0_write_1__VAL_2 or
WILL_FIRE_RL_wmi_wmi_respF_decCtr or wmi_wmi_respF_q_1)
begin
case (1'b1) // synopsys parallel_case
MUX_wmi_wmi_respF_q_0_write_1__SEL_1:
wmi_wmi_respF_q_0_D_IN = MUX_wmi_wmi_respF_q_0_write_1__VAL_1;
MUX_wmi_wmi_respF_q_0_write_1__SEL_2:
wmi_wmi_respF_q_0_D_IN = MUX_wmi_wmi_respF_q_0_write_1__VAL_2;
WILL_FIRE_RL_wmi_wmi_respF_decCtr:
wmi_wmi_respF_q_0_D_IN = wmi_wmi_respF_q_1;
default: wmi_wmi_respF_q_0_D_IN =
130'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA /* unspecified value */ ;
endcase
end
assign wmi_wmi_respF_q_0_EN =
WILL_FIRE_RL_wmi_wmi_respF_both && _dfoo9 ||
WILL_FIRE_RL_wmi_wmi_respF_incCtr &&
wmi_wmi_respF_cntr_r == 2'd0 ||
WILL_FIRE_RL_wmi_wmi_respF_decCtr ;
// register wmi_wmi_respF_q_1
always@(MUX_wmi_wmi_respF_q_1_write_1__SEL_1 or
MUX_wmi_wmi_respF_q_1_write_1__VAL_1 or
MUX_wmi_wmi_respF_q_1_write_1__SEL_2 or
MUX_wmi_wmi_respF_q_0_write_1__VAL_2 or
WILL_FIRE_RL_wmi_wmi_respF_decCtr)
begin
case (1'b1) // synopsys parallel_case
MUX_wmi_wmi_respF_q_1_write_1__SEL_1:
wmi_wmi_respF_q_1_D_IN = MUX_wmi_wmi_respF_q_1_write_1__VAL_1;
MUX_wmi_wmi_respF_q_1_write_1__SEL_2:
wmi_wmi_respF_q_1_D_IN = MUX_wmi_wmi_respF_q_0_write_1__VAL_2;
WILL_FIRE_RL_wmi_wmi_respF_decCtr: wmi_wmi_respF_q_1_D_IN = 130'd0;
default: wmi_wmi_respF_q_1_D_IN =
130'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA /* unspecified value */ ;
endcase
end
assign wmi_wmi_respF_q_1_EN =
WILL_FIRE_RL_wmi_wmi_respF_both && _dfoo7 ||
WILL_FIRE_RL_wmi_wmi_respF_incCtr &&
wmi_wmi_respF_cntr_r == 2'd1 ||
WILL_FIRE_RL_wmi_wmi_respF_decCtr ;
// register wmi_wmi_sFlagReg
assign wmi_wmi_sFlagReg_D_IN =
{ bram_1_serverAdapterB_outData_outData_wget[7:0],
bram_0_serverAdapterB_outData_outData_wget[23:0] } ;
assign wmi_wmi_sFlagReg_EN = WILL_FIRE_RL_wmi_respMetadata ;
// register wmi_wmi_statusR
assign wmi_wmi_statusR_D_IN = 8'h0 ;
assign wmi_wmi_statusR_EN = 1'b0 ;
// register wmi_wmi_trafficSticky
assign wmi_wmi_trafficSticky_D_IN = 1'b0 ;
assign wmi_wmi_trafficSticky_EN = 1'b0 ;
// register wmi_wrActive
assign wmi_wrActive_D_IN =
!MUX_wmi_wrActive_write_1__SEL_1 &&
wmi_wmi_reqF_D_OUT[31:29] == 3'd1 ;
assign wmi_wrActive_EN =
WILL_FIRE_RL_wmi_doWriteReq && wmi_bytesRemainReq == 14'd16 ||
WILL_FIRE_RL_wmi_getRequest ;
// register wmi_wrFinalize
assign wmi_wrFinalize_D_IN = MUX_wmi_wrFinalize_write_1__SEL_1 ;
assign wmi_wrFinalize_EN =
WILL_FIRE_RL_wmi_doWriteReq && wmi_bytesRemainReq == 14'd16 &&
wmi_doneWithMesg ||
WILL_FIRE_RL_wmi_doWriteFinalize ;
// register wmi_wrtCount
assign wmi_wrtCount_D_IN = wmi_wrtCount + 16'd1 ;
assign wmi_wrtCount_EN = WILL_FIRE_RL_wmi_doWriteReq ;
// register wti_isReset_isInReset
assign wti_isReset_isInReset_D_IN = 1'd0 ;
assign wti_isReset_isInReset_EN = wti_isReset_isInReset ;
// register wti_nowReq
assign wti_nowReq_D_IN = wti_s_req ;
assign wti_nowReq_EN = 1'd1 ;
// register wti_operateD
assign wti_operateD_D_IN = 1'b1 ;
assign wti_operateD_EN = 1'd1 ;
// submodule bram_0_memory
always@(MUX_bram_0_memory_a_put_1__SEL_1 or
MUX_bram_0_memory_a_put_2__VAL_1 or
MUX_bram_0_memory_a_put_1__SEL_2 or
tlp_tlpBRAM_mReqF_D_OUT or
MUX_bram_0_memory_a_put_1__SEL_3 or
WILL_FIRE_RL_tlp_tlpBRAM_read_NextReq or
MUX_bram_0_memory_a_put_2__VAL_4)
begin
case (1'b1) // synopsys parallel_case
MUX_bram_0_memory_a_put_1__SEL_1:
bram_0_memory_ADDRA = MUX_bram_0_memory_a_put_2__VAL_1;
MUX_bram_0_memory_a_put_1__SEL_2:
bram_0_memory_ADDRA = tlp_tlpBRAM_mReqF_D_OUT[62:52];
MUX_bram_0_memory_a_put_1__SEL_3:
bram_0_memory_ADDRA = tlp_tlpBRAM_mReqF_D_OUT[41:31];
WILL_FIRE_RL_tlp_tlpBRAM_read_NextReq:
bram_0_memory_ADDRA = MUX_bram_0_memory_a_put_2__VAL_4;
default: bram_0_memory_ADDRA = 11'b01010101010 /* unspecified value */ ;
endcase
end
always@(WILL_FIRE_RL_wmi_reqMetadata or
WILL_FIRE_RL_wmi_doWriteFinalize or
wmi_lclMetaAddr or
WILL_FIRE_RL_wmi_doReadReq or
MUX_bram_0_memory_b_put_2__VAL_2 or WILL_FIRE_RL_wmi_doWriteReq)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_wmi_reqMetadata || WILL_FIRE_RL_wmi_doWriteFinalize:
bram_0_memory_ADDRB = wmi_lclMetaAddr[14:4];
WILL_FIRE_RL_wmi_doReadReq:
bram_0_memory_ADDRB = MUX_bram_0_memory_b_put_2__VAL_2;
WILL_FIRE_RL_wmi_doWriteReq:
bram_0_memory_ADDRB = MUX_bram_0_memory_b_put_2__VAL_2;
default: bram_0_memory_ADDRB = 11'b01010101010 /* unspecified value */ ;
endcase
end
always@(MUX_bram_0_memory_a_put_1__SEL_1 or
MUX_bram_0_memory_a_put_3__VAL_1 or
MUX_bram_0_memory_a_put_1__SEL_2 or
MUX_bram_0_memory_a_put_3__VAL_2 or
MUX_bram_0_memory_a_put_1__SEL_3 or
WILL_FIRE_RL_tlp_tlpBRAM_read_NextReq)
begin
case (1'b1) // synopsys parallel_case
MUX_bram_0_memory_a_put_1__SEL_1:
bram_0_memory_DIA = MUX_bram_0_memory_a_put_3__VAL_1;
MUX_bram_0_memory_a_put_1__SEL_2:
bram_0_memory_DIA = MUX_bram_0_memory_a_put_3__VAL_2;
MUX_bram_0_memory_a_put_1__SEL_3 ||
WILL_FIRE_RL_tlp_tlpBRAM_read_NextReq:
bram_0_memory_DIA = 32'd0;
default: bram_0_memory_DIA = 32'hAAAAAAAA /* unspecified value */ ;
endcase
end
always@(WILL_FIRE_RL_wmi_doWriteReq or
wmi_wmi_dhF_D_OUT or
WILL_FIRE_RL_wmi_doWriteFinalize or
x3__h81813 or
WILL_FIRE_RL_wmi_reqMetadata or WILL_FIRE_RL_wmi_doReadReq)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_wmi_doWriteReq:
bram_0_memory_DIB = wmi_wmi_dhF_D_OUT[47:16];
WILL_FIRE_RL_wmi_doWriteFinalize: bram_0_memory_DIB = x3__h81813;
WILL_FIRE_RL_wmi_reqMetadata || WILL_FIRE_RL_wmi_doReadReq:
bram_0_memory_DIB = 32'd0;
default: bram_0_memory_DIB = 32'hAAAAAAAA /* unspecified value */ ;
endcase
end
assign bram_0_memory_WEA =
!MUX_bram_0_memory_a_put_1__SEL_3 &&
!WILL_FIRE_RL_tlp_tlpBRAM_read_NextReq ;
assign bram_0_memory_WEB =
!WILL_FIRE_RL_wmi_reqMetadata && !WILL_FIRE_RL_wmi_doReadReq ;
assign bram_0_memory_ENA =
WILL_FIRE_RL_tlp_tlpBRAM_writeData &&
SEL_ARR_NOT_tlp_tlpBRAM_writeRemainDWLen_52_EQ_ETC___d665 ||
WILL_FIRE_RL_tlp_tlpBRAM_writeReq &&
tlp_tlpBRAM_mReqF_D_OUT[51:50] == 2'd0 &&
!tlp_tlpBRAM_mReqF_D_OUT[63] ||
WILL_FIRE_RL_tlp_tlpBRAM_read_FirstReq &&
tlp_tlpBRAM_mReqF_D_OUT[30:29] == 2'd0 &&
!tlp_tlpBRAM_mReqF_D_OUT[60] ||
WILL_FIRE_RL_tlp_tlpBRAM_read_NextReq ;
assign bram_0_memory_ENB =
WILL_FIRE_RL_wmi_reqMetadata || WILL_FIRE_RL_wmi_doReadReq ||
WILL_FIRE_RL_wmi_doWriteFinalize ||
WILL_FIRE_RL_wmi_doWriteReq ;
// submodule bram_0_serverAdapterA_outDataCore
assign bram_0_serverAdapterA_outDataCore_D_IN = bram_0_memory_DOA ;
assign bram_0_serverAdapterA_outDataCore_ENQ =
WILL_FIRE_RL_bram_0_serverAdapterA_outData_enqAndDeq ||
bram_0_serverAdapterA_outDataCore_FULL_N &&
!bram_0_serverAdapterA_outData_deqCalled_whas &&
bram_0_serverAdapterA_outData_enqData_whas ;
assign bram_0_serverAdapterA_outDataCore_DEQ =
WILL_FIRE_RL_bram_0_serverAdapterA_outData_enqAndDeq ||
bram_0_serverAdapterA_outDataCore_EMPTY_N &&
bram_0_serverAdapterA_outData_deqCalled_whas &&
!bram_0_serverAdapterA_outData_enqData_whas ;
assign bram_0_serverAdapterA_outDataCore_CLR = 1'b0 ;
// submodule bram_0_serverAdapterB_outDataCore
assign bram_0_serverAdapterB_outDataCore_D_IN = bram_0_memory_DOB ;
assign bram_0_serverAdapterB_outDataCore_ENQ =
WILL_FIRE_RL_bram_0_serverAdapterB_outData_enqAndDeq ||
bram_0_serverAdapterB_outDataCore_FULL_N &&
!bram_0_serverAdapterB_outData_deqCalled_whas &&
bram_0_serverAdapterB_outData_enqData_whas ;
assign bram_0_serverAdapterB_outDataCore_DEQ =
WILL_FIRE_RL_bram_0_serverAdapterB_outData_enqAndDeq ||
bram_0_serverAdapterB_outDataCore_EMPTY_N &&
bram_0_serverAdapterB_outData_deqCalled_whas &&
!bram_0_serverAdapterB_outData_enqData_whas ;
assign bram_0_serverAdapterB_outDataCore_CLR = 1'b0 ;
// submodule bram_1_memory
always@(MUX_bram_1_memory_a_put_1__SEL_1 or
MUX_bram_1_memory_a_put_2__VAL_1 or
MUX_bram_1_memory_a_put_1__SEL_2 or
tlp_tlpBRAM_mReqF_D_OUT or
MUX_bram_1_memory_a_put_1__SEL_3 or
WILL_FIRE_RL_tlp_tlpBRAM_read_NextReq or
MUX_bram_1_memory_a_put_2__VAL_4)
begin
case (1'b1) // synopsys parallel_case
MUX_bram_1_memory_a_put_1__SEL_1:
bram_1_memory_ADDRA = MUX_bram_1_memory_a_put_2__VAL_1;
MUX_bram_1_memory_a_put_1__SEL_2:
bram_1_memory_ADDRA = tlp_tlpBRAM_mReqF_D_OUT[62:52];
MUX_bram_1_memory_a_put_1__SEL_3:
bram_1_memory_ADDRA = tlp_tlpBRAM_mReqF_D_OUT[41:31];
WILL_FIRE_RL_tlp_tlpBRAM_read_NextReq:
bram_1_memory_ADDRA = MUX_bram_1_memory_a_put_2__VAL_4;
default: bram_1_memory_ADDRA = 11'b01010101010 /* unspecified value */ ;
endcase
end
always@(WILL_FIRE_RL_wmi_reqMetadata or
WILL_FIRE_RL_wmi_doWriteFinalize or
wmi_lclMetaAddr or
WILL_FIRE_RL_wmi_doReadReq or
MUX_bram_0_memory_b_put_2__VAL_2 or WILL_FIRE_RL_wmi_doWriteReq)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_wmi_reqMetadata || WILL_FIRE_RL_wmi_doWriteFinalize:
bram_1_memory_ADDRB = wmi_lclMetaAddr[14:4];
WILL_FIRE_RL_wmi_doReadReq:
bram_1_memory_ADDRB = MUX_bram_0_memory_b_put_2__VAL_2;
WILL_FIRE_RL_wmi_doWriteReq:
bram_1_memory_ADDRB = MUX_bram_0_memory_b_put_2__VAL_2;
default: bram_1_memory_ADDRB = 11'b01010101010 /* unspecified value */ ;
endcase
end
always@(MUX_bram_1_memory_a_put_1__SEL_1 or
MUX_bram_1_memory_a_put_3__VAL_1 or
MUX_bram_1_memory_a_put_1__SEL_2 or
MUX_bram_0_memory_a_put_3__VAL_2 or
MUX_bram_1_memory_a_put_1__SEL_3 or
WILL_FIRE_RL_tlp_tlpBRAM_read_NextReq)
begin
case (1'b1) // synopsys parallel_case
MUX_bram_1_memory_a_put_1__SEL_1:
bram_1_memory_DIA = MUX_bram_1_memory_a_put_3__VAL_1;
MUX_bram_1_memory_a_put_1__SEL_2:
bram_1_memory_DIA = MUX_bram_0_memory_a_put_3__VAL_2;
MUX_bram_1_memory_a_put_1__SEL_3 ||
WILL_FIRE_RL_tlp_tlpBRAM_read_NextReq:
bram_1_memory_DIA = 32'd0;
default: bram_1_memory_DIA = 32'hAAAAAAAA /* unspecified value */ ;
endcase
end
always@(WILL_FIRE_RL_wmi_doWriteReq or
wmi_wmi_dhF_D_OUT or
WILL_FIRE_RL_wmi_doWriteFinalize or
mesgMeta_opcode__h81853 or
WILL_FIRE_RL_wmi_reqMetadata or WILL_FIRE_RL_wmi_doReadReq)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_wmi_doWriteReq:
bram_1_memory_DIB = wmi_wmi_dhF_D_OUT[79:48];
WILL_FIRE_RL_wmi_doWriteFinalize:
bram_1_memory_DIB = mesgMeta_opcode__h81853;
WILL_FIRE_RL_wmi_reqMetadata || WILL_FIRE_RL_wmi_doReadReq:
bram_1_memory_DIB = 32'd0;
default: bram_1_memory_DIB = 32'hAAAAAAAA /* unspecified value */ ;
endcase
end
assign bram_1_memory_WEA =
!MUX_bram_1_memory_a_put_1__SEL_3 &&
!WILL_FIRE_RL_tlp_tlpBRAM_read_NextReq ;
assign bram_1_memory_WEB = bram_0_memory_WEB ;
assign bram_1_memory_ENA =
WILL_FIRE_RL_tlp_tlpBRAM_writeData &&
SEL_ARR_NOT_tlp_tlpBRAM_writeRemainDWLen_52_EQ_ETC___d669 ||
WILL_FIRE_RL_tlp_tlpBRAM_writeReq &&
tlp_tlpBRAM_mReqF_D_OUT[51:50] == 2'd1 &&
!tlp_tlpBRAM_mReqF_D_OUT[63] ||
WILL_FIRE_RL_tlp_tlpBRAM_read_FirstReq &&
tlp_tlpBRAM_mReqF_D_OUT[30:29] == 2'd1 &&
!tlp_tlpBRAM_mReqF_D_OUT[60] ||
WILL_FIRE_RL_tlp_tlpBRAM_read_NextReq ;
assign bram_1_memory_ENB =
WILL_FIRE_RL_wmi_reqMetadata || WILL_FIRE_RL_wmi_doReadReq ||
WILL_FIRE_RL_wmi_doWriteFinalize ||
WILL_FIRE_RL_wmi_doWriteReq ;
// submodule bram_1_serverAdapterA_outDataCore
assign bram_1_serverAdapterA_outDataCore_D_IN = bram_1_memory_DOA ;
assign bram_1_serverAdapterA_outDataCore_ENQ =
WILL_FIRE_RL_bram_1_serverAdapterA_outData_enqAndDeq ||
bram_1_serverAdapterA_outDataCore_FULL_N &&
!bram_1_serverAdapterA_outData_deqCalled_whas &&
bram_1_serverAdapterA_outData_enqData_whas ;
assign bram_1_serverAdapterA_outDataCore_DEQ =
WILL_FIRE_RL_bram_1_serverAdapterA_outData_enqAndDeq ||
bram_1_serverAdapterA_outDataCore_EMPTY_N &&
bram_1_serverAdapterA_outData_deqCalled_whas &&
!bram_1_serverAdapterA_outData_enqData_whas ;
assign bram_1_serverAdapterA_outDataCore_CLR = 1'b0 ;
// submodule bram_1_serverAdapterB_outDataCore
assign bram_1_serverAdapterB_outDataCore_D_IN = bram_1_memory_DOB ;
assign bram_1_serverAdapterB_outDataCore_ENQ =
WILL_FIRE_RL_bram_1_serverAdapterB_outData_enqAndDeq ||
bram_1_serverAdapterB_outDataCore_FULL_N &&
!bram_0_serverAdapterB_outData_deqCalled_whas &&
bram_1_serverAdapterB_outData_enqData_whas ;
assign bram_1_serverAdapterB_outDataCore_DEQ =
WILL_FIRE_RL_bram_1_serverAdapterB_outData_enqAndDeq ||
bram_1_serverAdapterB_outDataCore_EMPTY_N &&
bram_0_serverAdapterB_outData_deqCalled_whas &&
!bram_1_serverAdapterB_outData_enqData_whas ;
assign bram_1_serverAdapterB_outDataCore_CLR = 1'b0 ;
// submodule bram_2_memory
always@(MUX_bram_2_memory_a_put_1__SEL_1 or
MUX_bram_2_memory_a_put_2__VAL_1 or
MUX_bram_2_memory_a_put_1__SEL_2 or
tlp_tlpBRAM_mReqF_D_OUT or
MUX_bram_2_memory_a_put_1__SEL_3 or
WILL_FIRE_RL_tlp_tlpBRAM_read_NextReq or
MUX_bram_2_memory_a_put_2__VAL_4)
begin
case (1'b1) // synopsys parallel_case
MUX_bram_2_memory_a_put_1__SEL_1:
bram_2_memory_ADDRA = MUX_bram_2_memory_a_put_2__VAL_1;
MUX_bram_2_memory_a_put_1__SEL_2:
bram_2_memory_ADDRA = tlp_tlpBRAM_mReqF_D_OUT[62:52];
MUX_bram_2_memory_a_put_1__SEL_3:
bram_2_memory_ADDRA = tlp_tlpBRAM_mReqF_D_OUT[41:31];
WILL_FIRE_RL_tlp_tlpBRAM_read_NextReq:
bram_2_memory_ADDRA = MUX_bram_2_memory_a_put_2__VAL_4;
default: bram_2_memory_ADDRA = 11'b01010101010 /* unspecified value */ ;
endcase
end
always@(WILL_FIRE_RL_wmi_reqMetadata or
WILL_FIRE_RL_wmi_doWriteFinalize or
wmi_lclMetaAddr or
WILL_FIRE_RL_wmi_doReadReq or
MUX_bram_0_memory_b_put_2__VAL_2 or WILL_FIRE_RL_wmi_doWriteReq)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_wmi_reqMetadata || WILL_FIRE_RL_wmi_doWriteFinalize:
bram_2_memory_ADDRB = wmi_lclMetaAddr[14:4];
WILL_FIRE_RL_wmi_doReadReq:
bram_2_memory_ADDRB = MUX_bram_0_memory_b_put_2__VAL_2;
WILL_FIRE_RL_wmi_doWriteReq:
bram_2_memory_ADDRB = MUX_bram_0_memory_b_put_2__VAL_2;
default: bram_2_memory_ADDRB = 11'b01010101010 /* unspecified value */ ;
endcase
end
always@(MUX_bram_2_memory_a_put_1__SEL_1 or
MUX_bram_2_memory_a_put_3__VAL_1 or
MUX_bram_2_memory_a_put_1__SEL_2 or
MUX_bram_0_memory_a_put_3__VAL_2 or
MUX_bram_2_memory_a_put_1__SEL_3 or
WILL_FIRE_RL_tlp_tlpBRAM_read_NextReq)
begin
case (1'b1) // synopsys parallel_case
MUX_bram_2_memory_a_put_1__SEL_1:
bram_2_memory_DIA = MUX_bram_2_memory_a_put_3__VAL_1;
MUX_bram_2_memory_a_put_1__SEL_2:
bram_2_memory_DIA = MUX_bram_0_memory_a_put_3__VAL_2;
MUX_bram_2_memory_a_put_1__SEL_3 ||
WILL_FIRE_RL_tlp_tlpBRAM_read_NextReq:
bram_2_memory_DIA = 32'd0;
default: bram_2_memory_DIA = 32'hAAAAAAAA /* unspecified value */ ;
endcase
end
always@(WILL_FIRE_RL_wmi_doWriteFinalize or
wmi_nowW_wget or
WILL_FIRE_RL_wmi_doWriteReq or
wmi_wmi_dhF_D_OUT or
WILL_FIRE_RL_wmi_reqMetadata or WILL_FIRE_RL_wmi_doReadReq)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_wmi_doWriteFinalize:
bram_2_memory_DIB = wmi_nowW_wget[63:32];
WILL_FIRE_RL_wmi_doWriteReq:
bram_2_memory_DIB = wmi_wmi_dhF_D_OUT[111:80];
WILL_FIRE_RL_wmi_reqMetadata || WILL_FIRE_RL_wmi_doReadReq:
bram_2_memory_DIB = 32'd0;
default: bram_2_memory_DIB = 32'hAAAAAAAA /* unspecified value */ ;
endcase
end
assign bram_2_memory_WEA =
!MUX_bram_2_memory_a_put_1__SEL_3 &&
!WILL_FIRE_RL_tlp_tlpBRAM_read_NextReq ;
assign bram_2_memory_WEB = bram_0_memory_WEB ;
assign bram_2_memory_ENA =
WILL_FIRE_RL_tlp_tlpBRAM_writeData &&
SEL_ARR_NOT_tlp_tlpBRAM_writeRemainDWLen_52_EQ_ETC___d673 ||
WILL_FIRE_RL_tlp_tlpBRAM_writeReq &&
tlp_tlpBRAM_mReqF_D_OUT[51:50] == 2'd2 &&
!tlp_tlpBRAM_mReqF_D_OUT[63] ||
WILL_FIRE_RL_tlp_tlpBRAM_read_FirstReq &&
tlp_tlpBRAM_mReqF_D_OUT[30:29] == 2'd2 &&
!tlp_tlpBRAM_mReqF_D_OUT[60] ||
WILL_FIRE_RL_tlp_tlpBRAM_read_NextReq ;
assign bram_2_memory_ENB =
WILL_FIRE_RL_wmi_reqMetadata || WILL_FIRE_RL_wmi_doReadReq ||
WILL_FIRE_RL_wmi_doWriteFinalize ||
WILL_FIRE_RL_wmi_doWriteReq ;
// submodule bram_2_serverAdapterA_outDataCore
assign bram_2_serverAdapterA_outDataCore_D_IN = bram_2_memory_DOA ;
assign bram_2_serverAdapterA_outDataCore_ENQ =
WILL_FIRE_RL_bram_2_serverAdapterA_outData_enqAndDeq ||
bram_2_serverAdapterA_outDataCore_FULL_N &&
!bram_2_serverAdapterA_outData_deqCalled_whas &&
bram_2_serverAdapterA_outData_enqData_whas ;
assign bram_2_serverAdapterA_outDataCore_DEQ =
WILL_FIRE_RL_bram_2_serverAdapterA_outData_enqAndDeq ||
bram_2_serverAdapterA_outDataCore_EMPTY_N &&
bram_2_serverAdapterA_outData_deqCalled_whas &&
!bram_2_serverAdapterA_outData_enqData_whas ;
assign bram_2_serverAdapterA_outDataCore_CLR = 1'b0 ;
// submodule bram_2_serverAdapterB_outDataCore
assign bram_2_serverAdapterB_outDataCore_D_IN = bram_2_memory_DOB ;
assign bram_2_serverAdapterB_outDataCore_ENQ =
WILL_FIRE_RL_bram_2_serverAdapterB_outData_enqAndDeq ||
bram_2_serverAdapterB_outDataCore_FULL_N &&
!bram_0_serverAdapterB_outData_deqCalled_whas &&
bram_2_serverAdapterB_outData_enqData_whas ;
assign bram_2_serverAdapterB_outDataCore_DEQ =
WILL_FIRE_RL_bram_2_serverAdapterB_outData_enqAndDeq ||
bram_2_serverAdapterB_outDataCore_EMPTY_N &&
bram_0_serverAdapterB_outData_deqCalled_whas &&
!bram_2_serverAdapterB_outData_enqData_whas ;
assign bram_2_serverAdapterB_outDataCore_CLR = 1'b0 ;
// submodule bram_3_memory
always@(MUX_bram_3_memory_a_put_1__SEL_1 or
MUX_bram_3_memory_a_put_2__VAL_1 or
MUX_bram_3_memory_a_put_1__SEL_2 or
tlp_tlpBRAM_mReqF_D_OUT or
MUX_bram_3_memory_a_put_1__SEL_3 or
WILL_FIRE_RL_tlp_tlpBRAM_read_NextReq or
MUX_bram_3_memory_a_put_2__VAL_4)
begin
case (1'b1) // synopsys parallel_case
MUX_bram_3_memory_a_put_1__SEL_1:
bram_3_memory_ADDRA = MUX_bram_3_memory_a_put_2__VAL_1;
MUX_bram_3_memory_a_put_1__SEL_2:
bram_3_memory_ADDRA = tlp_tlpBRAM_mReqF_D_OUT[62:52];
MUX_bram_3_memory_a_put_1__SEL_3:
bram_3_memory_ADDRA = tlp_tlpBRAM_mReqF_D_OUT[41:31];
WILL_FIRE_RL_tlp_tlpBRAM_read_NextReq:
bram_3_memory_ADDRA = MUX_bram_3_memory_a_put_2__VAL_4;
default: bram_3_memory_ADDRA = 11'b01010101010 /* unspecified value */ ;
endcase
end
always@(WILL_FIRE_RL_wmi_reqMetadata or
WILL_FIRE_RL_wmi_doWriteFinalize or
wmi_lclMetaAddr or
WILL_FIRE_RL_wmi_doReadReq or
MUX_bram_0_memory_b_put_2__VAL_2 or WILL_FIRE_RL_wmi_doWriteReq)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_wmi_reqMetadata || WILL_FIRE_RL_wmi_doWriteFinalize:
bram_3_memory_ADDRB = wmi_lclMetaAddr[14:4];
WILL_FIRE_RL_wmi_doReadReq:
bram_3_memory_ADDRB = MUX_bram_0_memory_b_put_2__VAL_2;
WILL_FIRE_RL_wmi_doWriteReq:
bram_3_memory_ADDRB = MUX_bram_0_memory_b_put_2__VAL_2;
default: bram_3_memory_ADDRB = 11'b01010101010 /* unspecified value */ ;
endcase
end
always@(MUX_bram_3_memory_a_put_1__SEL_1 or
MUX_bram_3_memory_a_put_3__VAL_1 or
MUX_bram_3_memory_a_put_1__SEL_2 or
MUX_bram_0_memory_a_put_3__VAL_2 or
MUX_bram_3_memory_a_put_1__SEL_3 or
WILL_FIRE_RL_tlp_tlpBRAM_read_NextReq)
begin
case (1'b1) // synopsys parallel_case
MUX_bram_3_memory_a_put_1__SEL_1:
bram_3_memory_DIA = MUX_bram_3_memory_a_put_3__VAL_1;
MUX_bram_3_memory_a_put_1__SEL_2:
bram_3_memory_DIA = MUX_bram_0_memory_a_put_3__VAL_2;
MUX_bram_3_memory_a_put_1__SEL_3 ||
WILL_FIRE_RL_tlp_tlpBRAM_read_NextReq:
bram_3_memory_DIA = 32'd0;
default: bram_3_memory_DIA = 32'hAAAAAAAA /* unspecified value */ ;
endcase
end
always@(WILL_FIRE_RL_wmi_doWriteFinalize or
wmi_nowW_wget or
WILL_FIRE_RL_wmi_doWriteReq or
wmi_wmi_dhF_D_OUT or
WILL_FIRE_RL_wmi_reqMetadata or WILL_FIRE_RL_wmi_doReadReq)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_wmi_doWriteFinalize:
bram_3_memory_DIB = wmi_nowW_wget[31:0];
WILL_FIRE_RL_wmi_doWriteReq:
bram_3_memory_DIB = wmi_wmi_dhF_D_OUT[143:112];
WILL_FIRE_RL_wmi_reqMetadata || WILL_FIRE_RL_wmi_doReadReq:
bram_3_memory_DIB = 32'd0;
default: bram_3_memory_DIB = 32'hAAAAAAAA /* unspecified value */ ;
endcase
end
assign bram_3_memory_WEA =
!MUX_bram_3_memory_a_put_1__SEL_3 &&
!WILL_FIRE_RL_tlp_tlpBRAM_read_NextReq ;
assign bram_3_memory_WEB = bram_0_memory_WEB ;
assign bram_3_memory_ENA =
WILL_FIRE_RL_tlp_tlpBRAM_writeData &&
SEL_ARR_NOT_tlp_tlpBRAM_writeRemainDWLen_52_EQ_ETC___d677 ||
WILL_FIRE_RL_tlp_tlpBRAM_writeReq &&
tlp_tlpBRAM_mReqF_D_OUT[51:50] == 2'd3 &&
!tlp_tlpBRAM_mReqF_D_OUT[63] ||
WILL_FIRE_RL_tlp_tlpBRAM_read_FirstReq &&
tlp_tlpBRAM_mReqF_D_OUT[30:29] == 2'd3 &&
!tlp_tlpBRAM_mReqF_D_OUT[60] ||
WILL_FIRE_RL_tlp_tlpBRAM_read_NextReq ;
assign bram_3_memory_ENB =
WILL_FIRE_RL_wmi_reqMetadata || WILL_FIRE_RL_wmi_doReadReq ||
WILL_FIRE_RL_wmi_doWriteFinalize ||
WILL_FIRE_RL_wmi_doWriteReq ;
// submodule bram_3_serverAdapterA_outDataCore
assign bram_3_serverAdapterA_outDataCore_D_IN = bram_3_memory_DOA ;
assign bram_3_serverAdapterA_outDataCore_ENQ =
WILL_FIRE_RL_bram_3_serverAdapterA_outData_enqAndDeq ||
bram_3_serverAdapterA_outDataCore_FULL_N &&
!bram_3_serverAdapterA_outData_deqCalled_whas &&
bram_3_serverAdapterA_outData_enqData_whas ;
assign bram_3_serverAdapterA_outDataCore_DEQ =
WILL_FIRE_RL_bram_3_serverAdapterA_outData_enqAndDeq ||
bram_3_serverAdapterA_outDataCore_EMPTY_N &&
bram_3_serverAdapterA_outData_deqCalled_whas &&
!bram_3_serverAdapterA_outData_enqData_whas ;
assign bram_3_serverAdapterA_outDataCore_CLR = 1'b0 ;
// submodule bram_3_serverAdapterB_outDataCore
assign bram_3_serverAdapterB_outDataCore_D_IN = bram_3_memory_DOB ;
assign bram_3_serverAdapterB_outDataCore_ENQ =
WILL_FIRE_RL_bram_3_serverAdapterB_outData_enqAndDeq ||
bram_3_serverAdapterB_outDataCore_FULL_N &&
!bram_0_serverAdapterB_outData_deqCalled_whas &&
bram_3_serverAdapterB_outData_enqData_whas ;
assign bram_3_serverAdapterB_outDataCore_DEQ =
WILL_FIRE_RL_bram_3_serverAdapterB_outData_enqAndDeq ||
bram_3_serverAdapterB_outDataCore_EMPTY_N &&
bram_0_serverAdapterB_outData_deqCalled_whas &&
!bram_3_serverAdapterB_outData_enqData_whas ;
assign bram_3_serverAdapterB_outDataCore_CLR = 1'b0 ;
// submodule tlp_inF
assign tlp_inF_D_IN = server_request_put ;
assign tlp_inF_DEQ =
WILL_FIRE_RL_tlp_tlpRcv ||
WILL_FIRE_RL_tlp_dmaPullResponseBody ||
WILL_FIRE_RL_tlp_dmaPullResponseHeader ||
WILL_FIRE_RL_tlp_dmaRespBodyFarMeta ||
WILL_FIRE_RL_tlp_dmaRespHeadFarMeta ;
assign tlp_inF_ENQ = EN_server_request_put ;
assign tlp_inF_CLR = 1'b0 ;
// submodule tlp_outF
always@(MUX_tlp_tlpXmtBusy_write_1__PSEL_2 or
MUX_tlp_outF_enq_1__VAL_1 or
WILL_FIRE_RL_tlp_dmaPushResponseHeader or
MUX_tlp_outF_enq_1__VAL_2 or
WILL_FIRE_RL_tlp_dmaXmtMetaHead or
MUX_tlp_outF_enq_1__VAL_3 or
WILL_FIRE_RL_tlp_dmaXmtMetaBody or
MUX_tlp_outF_enq_1__VAL_4 or
WILL_FIRE_RL_tlp_dmaRequestFarMeta or
MUX_tlp_outF_enq_1__VAL_5 or
WILL_FIRE_RL_tlp_dmaPullRequestFarMesg or
MUX_tlp_outF_enq_1__VAL_6 or
WILL_FIRE_RL_tlp_dmaTailEventSender or
MUX_tlp_outF_enq_1__VAL_7 or
WILL_FIRE_RL_tlp_dataXmt_Header or MUX_tlp_outF_enq_1__VAL_8)
begin
case (1'b1) // synopsys parallel_case
MUX_tlp_tlpXmtBusy_write_1__PSEL_2:
tlp_outF_D_IN = MUX_tlp_outF_enq_1__VAL_1;
WILL_FIRE_RL_tlp_dmaPushResponseHeader:
tlp_outF_D_IN = MUX_tlp_outF_enq_1__VAL_2;
WILL_FIRE_RL_tlp_dmaXmtMetaHead:
tlp_outF_D_IN = MUX_tlp_outF_enq_1__VAL_3;
WILL_FIRE_RL_tlp_dmaXmtMetaBody:
tlp_outF_D_IN = MUX_tlp_outF_enq_1__VAL_4;
WILL_FIRE_RL_tlp_dmaRequestFarMeta:
tlp_outF_D_IN = MUX_tlp_outF_enq_1__VAL_5;
WILL_FIRE_RL_tlp_dmaPullRequestFarMesg:
tlp_outF_D_IN = MUX_tlp_outF_enq_1__VAL_6;
WILL_FIRE_RL_tlp_dmaTailEventSender:
tlp_outF_D_IN = MUX_tlp_outF_enq_1__VAL_7;
WILL_FIRE_RL_tlp_dataXmt_Header:
tlp_outF_D_IN = MUX_tlp_outF_enq_1__VAL_8;
default: tlp_outF_D_IN =
153'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA /* unspecified value */ ;
endcase
end
assign tlp_outF_DEQ = EN_server_response_get ;
assign tlp_outF_ENQ =
WILL_FIRE_RL_tlp_dataXmt_Body ||
WILL_FIRE_RL_tlp_dmaPushResponseBody ||
WILL_FIRE_RL_tlp_dmaPushResponseHeader ||
WILL_FIRE_RL_tlp_dmaXmtMetaHead ||
WILL_FIRE_RL_tlp_dmaXmtMetaBody ||
WILL_FIRE_RL_tlp_dmaRequestFarMeta ||
WILL_FIRE_RL_tlp_dmaPullRequestFarMesg ||
WILL_FIRE_RL_tlp_dmaTailEventSender ||
WILL_FIRE_RL_tlp_dataXmt_Header ;
assign tlp_outF_CLR = 1'b0 ;
// submodule tlp_tailEventF
assign tlp_tailEventF_D_IN = !MUX_tlp_tailEventF_enq_1__SEL_1 ;
assign tlp_tailEventF_ENQ =
WILL_FIRE_RL_tlp_dmaXmtDoorbell ||
WILL_FIRE_RL_tlp_dmaXmtTailEvent ||
WILL_FIRE_RL_tlp_dmaPullTailEvent ;
assign tlp_tailEventF_DEQ = MUX_tlp_fabMeta_write_1__SEL_2 ;
assign tlp_tailEventF_CLR = 1'b0 ;
// submodule tlp_tlpBRAM_mReqF
always@(MUX_tlp_tlpBRAM_mReqF_enq_1__SEL_1 or
MUX_tlp_tlpBRAM_mReqF_enq_1__VAL_1 or
MUX_tlp_tlpBRAM_mReqF_enq_1__SEL_2 or
MUX_tlp_tlpBRAM_mReqF_enq_1__VAL_2 or
WILL_FIRE_RL_tlp_dmaRequestNearMeta or
MUX_tlp_tlpBRAM_mReqF_enq_1__VAL_3 or
WILL_FIRE_RL_tlp_dmaPushRequestMesg or
MUX_tlp_tlpBRAM_mReqF_enq_1__VAL_4 or
WILL_FIRE_RL_tlp_dmaRespHeadFarMeta or
MUX_tlp_tlpBRAM_mReqF_enq_1__VAL_5 or
WILL_FIRE_RL_tlp_dmaPullResponseHeader or
MUX_tlp_tlpBRAM_mReqF_enq_1__VAL_6)
begin
case (1'b1) // synopsys parallel_case
MUX_tlp_tlpBRAM_mReqF_enq_1__SEL_1:
tlp_tlpBRAM_mReqF_D_IN = MUX_tlp_tlpBRAM_mReqF_enq_1__VAL_1;
MUX_tlp_tlpBRAM_mReqF_enq_1__SEL_2:
tlp_tlpBRAM_mReqF_D_IN = MUX_tlp_tlpBRAM_mReqF_enq_1__VAL_2;
WILL_FIRE_RL_tlp_dmaRequestNearMeta:
tlp_tlpBRAM_mReqF_D_IN = MUX_tlp_tlpBRAM_mReqF_enq_1__VAL_3;
WILL_FIRE_RL_tlp_dmaPushRequestMesg:
tlp_tlpBRAM_mReqF_D_IN = MUX_tlp_tlpBRAM_mReqF_enq_1__VAL_4;
WILL_FIRE_RL_tlp_dmaRespHeadFarMeta:
tlp_tlpBRAM_mReqF_D_IN = MUX_tlp_tlpBRAM_mReqF_enq_1__VAL_5;
WILL_FIRE_RL_tlp_dmaPullResponseHeader:
tlp_tlpBRAM_mReqF_D_IN = MUX_tlp_tlpBRAM_mReqF_enq_1__VAL_6;
default: tlp_tlpBRAM_mReqF_D_IN =
130'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA /* unspecified value */ ;
endcase
end
assign tlp_tlpBRAM_mReqF_ENQ =
WILL_FIRE_RL_tlp_tlpRcv &&
tlp_inF_first__259_BIT_152_462_AND_NOT_tlp_inF_ETC___d1487 ||
WILL_FIRE_RL_tlp_dmaPullResponseBody ||
WILL_FIRE_RL_tlp_dmaRespBodyFarMeta ||
WILL_FIRE_RL_tlp_dmaRequestNearMeta ||
WILL_FIRE_RL_tlp_dmaPushRequestMesg ||
WILL_FIRE_RL_tlp_dmaRespHeadFarMeta ||
WILL_FIRE_RL_tlp_dmaPullResponseHeader ;
assign tlp_tlpBRAM_mReqF_DEQ =
WILL_FIRE_RL_tlp_tlpBRAM_read_FirstReq &&
tlp_tlpBRAM_mReqF_D_OUT[28:19] == 10'd1 &&
!tlp_tlpBRAM_mReqF_D_OUT[60] ||
WILL_FIRE_RL_tlp_tlpBRAM_read_NextReq &&
tlp_tlpBRAM_readRemainDWLen_74_ULE_4___d775 ||
WILL_FIRE_RL_tlp_tlpBRAM_writeData ||
WILL_FIRE_RL_tlp_tlpBRAM_writeReq ;
assign tlp_tlpBRAM_mReqF_CLR = 1'b0 ;
// submodule tlp_tlpBRAM_mRespF
assign tlp_tlpBRAM_mRespF_D_IN =
WILL_FIRE_RL_tlp_tlpBRAM_read_FirstResp ?
MUX_tlp_tlpBRAM_mRespF_enq_1__VAL_1 :
MUX_tlp_tlpBRAM_mRespF_enq_1__VAL_2 ;
assign tlp_tlpBRAM_mRespF_ENQ =
WILL_FIRE_RL_tlp_tlpBRAM_read_FirstResp ||
WILL_FIRE_RL_tlp_tlpBRAM_read_NextResp ;
assign tlp_tlpBRAM_mRespF_DEQ =
WILL_FIRE_RL_tlp_dataXmt_Body ||
WILL_FIRE_RL_tlp_dataXmt_Header ||
WILL_FIRE_RL_tlp_dmaPushResponseBody ||
WILL_FIRE_RL_tlp_dmaPushResponseHeader ||
WILL_FIRE_RL_tlp_dmaResponseNearMetaBody ||
WILL_FIRE_RL_tlp_dmaResponseNearMetaHead ;
assign tlp_tlpBRAM_mRespF_CLR = 1'b0 ;
// submodule tlp_tlpBRAM_readReq
assign tlp_tlpBRAM_readReq_D_IN = tlp_tlpBRAM_mReqF_D_OUT[60:0] ;
assign tlp_tlpBRAM_readReq_ENQ = WILL_FIRE_RL_tlp_tlpBRAM_read_FirstReq ;
assign tlp_tlpBRAM_readReq_DEQ =
WILL_FIRE_RL_tlp_tlpBRAM_read_FirstResp &&
tlp_tlpBRAM_readReq_D_OUT[28:19] == 10'd1 &&
!tlp_tlpBRAM_readReq_D_OUT[60] ||
WILL_FIRE_RL_tlp_tlpBRAM_read_NextResp &&
tlp_tlpBRAM_rdRespDwRemain_16_ULE_4___d918 ;
assign tlp_tlpBRAM_readReq_CLR = 1'b0 ;
// submodule wci_reqF
assign wci_reqF_D_IN = wci_wciReq_wget ;
assign wci_reqF_ENQ = wci_wciReq_wget[71:69] != 3'd0 ;
assign wci_reqF_DEQ = wci_reqF_r_deq_whas ;
assign wci_reqF_CLR = 1'b0 ;
// submodule wmi_wmi_dhF
assign wmi_wmi_dhF_D_IN = wmi_wmi_wmiDh_wget ;
assign wmi_wmi_dhF_ENQ = MUX_wmi_wmi_dhF_levelsValid_write_1__SEL_2 ;
assign wmi_wmi_dhF_DEQ = WILL_FIRE_RL_wmi_doWriteReq ;
assign wmi_wmi_dhF_CLR = 1'b0 ;
// submodule wmi_wmi_mFlagF
assign wmi_wmi_mFlagF_D_IN = wmiS0_arg_mFlag ;
assign wmi_wmi_mFlagF_ENQ = MUX_wmi_wmi_mFlagF_levelsValid_write_1__SEL_2 ;
assign wmi_wmi_mFlagF_DEQ = WILL_FIRE_RL_wmi_doWriteFinalize ;
assign wmi_wmi_mFlagF_CLR = 1'b0 ;
// submodule wmi_wmi_reqF
assign wmi_wmi_reqF_D_IN = wmi_wmi_wmiReq_wget ;
assign wmi_wmi_reqF_ENQ = MUX_wmi_wmi_reqF_levelsValid_write_1__SEL_2 ;
assign wmi_wmi_reqF_DEQ = WILL_FIRE_RL_wmi_getRequest ;
assign wmi_wmi_reqF_CLR = 1'b0 ;
// remaining internal signals
assign IF_bml_dpControl_wget__898_BITS_1_TO_0_904_EQ__ETC___d1984 =
CASE_dpControl_BITS_1_TO_0_0_bml_fabDone_1_bml_ETC__q4 &&
!bml_lclBufStart ||
CASE_dpControl_BITS_1_TO_0_0_NOT_bml_fabDone_1_ETC__q5 &&
bml_lclBufStart ;
assign IF_bml_dpControl_wget__898_BITS_3_TO_2_899_EQ__ETC___d1995 =
(dpControl[3:2] == 2'd1) ? !bml_remDone : !bml_remStart ;
assign IF_tlp_fabMesgAddrMS_078_EQ_0_079_THEN_0_ELSE__ETC___d1353 =
{ (tlp_fabMesgAddrMS == 32'd0) ? 22'd0 : 22'd524288,
thisRequestLength__h63893[11:2],
pciDevice,
tag__h64168,
lastBE__h64200,
4'd15,
(tlp_fabMesgAddrMS == 32'd0) ?
{ tlp_fabMesgAccu[31:2], 34'd0 } :
{ tlp_fabMesgAddrMS, tlp_fabMesgAccu[31:2], 2'b0 } } ;
assign IF_tlp_fabMetaAddrMS_157_EQ_0_158_THEN_4_ELSE__ETC___d1248 =
{ (tlp_fabMetaAddrMS == 32'd0) ? 32'd4 : 32'd536870916,
pciDevice,
tag__h64168,
8'd255,
(tlp_fabMetaAddrMS == 32'd0) ?
{ tlp_fabMetaAddr[31:2], 34'd0 } :
{ tlp_fabMetaAddrMS, tlp_fabMetaAddr[31:2], 2'b0 } } ;
assign IF_tlp_tlpBRAM_readReq_first__98_BITS_30_TO_29_ETC___d929 =
tlp_tlpBRAM_readReq_first__98_BITS_30_TO_29_00_ETC___d922[0] ?
{ bram_3_serverAdapterA_outData_outData_wget[7:0],
bram_3_serverAdapterA_outData_outData_wget[15:8],
bram_3_serverAdapterA_outData_outData_wget[23:16],
bram_3_serverAdapterA_outData_outData_wget[31:24],
bram_0_serverAdapterA_outData_outData_wget[7:0],
bram_0_serverAdapterA_outData_outData_wget[15:8],
bram_0_serverAdapterA_outData_outData_wget[23:16],
bram_0_serverAdapterA_outData_outData_wget[31:24],
bram_1_serverAdapterA_outData_outData_wget[7:0],
bram_1_serverAdapterA_outData_outData_wget[15:8],
bram_1_serverAdapterA_outData_outData_wget[23:16],
bram_1_serverAdapterA_outData_outData_wget[31:24],
bram_2_serverAdapterA_outData_outData_wget[7:0],
bram_2_serverAdapterA_outData_outData_wget[15:8],
bram_2_serverAdapterA_outData_outData_wget[23:16],
bram_2_serverAdapterA_outData_outData_wget[31:24] } :
{ bram_2_serverAdapterA_outData_outData_wget[7:0],
bram_2_serverAdapterA_outData_outData_wget[15:8],
bram_2_serverAdapterA_outData_outData_wget[23:16],
bram_2_serverAdapterA_outData_outData_wget[31:24],
bram_3_serverAdapterA_outData_outData_wget[7:0],
bram_3_serverAdapterA_outData_outData_wget[15:8],
bram_3_serverAdapterA_outData_outData_wget[23:16],
bram_3_serverAdapterA_outData_outData_wget[31:24],
bram_0_serverAdapterA_outData_outData_wget[7:0],
bram_0_serverAdapterA_outData_outData_wget[15:8],
bram_0_serverAdapterA_outData_outData_wget[23:16],
bram_0_serverAdapterA_outData_outData_wget[31:24],
bram_1_serverAdapterA_outData_outData_wget[7:0],
bram_1_serverAdapterA_outData_outData_wget[15:8],
bram_1_serverAdapterA_outData_outData_wget[23:16],
bram_1_serverAdapterA_outData_outData_wget[31:24] } ;
assign IF_tlp_tlpBRAM_readReq_first__98_BITS_30_TO_29_ETC___d934 =
tlp_tlpBRAM_readReq_first__98_BITS_30_TO_29_00_ETC___d922[0] ?
{ bram_1_serverAdapterA_outData_outData_wget[7:0],
bram_1_serverAdapterA_outData_outData_wget[15:8],
bram_1_serverAdapterA_outData_outData_wget[23:16],
bram_1_serverAdapterA_outData_outData_wget[31:24],
bram_2_serverAdapterA_outData_outData_wget[7:0],
bram_2_serverAdapterA_outData_outData_wget[15:8],
bram_2_serverAdapterA_outData_outData_wget[23:16],
bram_2_serverAdapterA_outData_outData_wget[31:24],
bram_3_serverAdapterA_outData_outData_wget[7:0],
bram_3_serverAdapterA_outData_outData_wget[15:8],
bram_3_serverAdapterA_outData_outData_wget[23:16],
bram_3_serverAdapterA_outData_outData_wget[31:24],
bram_0_serverAdapterA_outData_outData_wget[7:0],
bram_0_serverAdapterA_outData_outData_wget[15:8],
bram_0_serverAdapterA_outData_outData_wget[23:16],
bram_0_serverAdapterA_outData_outData_wget[31:24] } :
{ bram_0_serverAdapterA_outData_outData_wget[7:0],
bram_0_serverAdapterA_outData_outData_wget[15:8],
bram_0_serverAdapterA_outData_outData_wget[23:16],
bram_0_serverAdapterA_outData_outData_wget[31:24],
bram_1_serverAdapterA_outData_outData_wget[7:0],
bram_1_serverAdapterA_outData_outData_wget[15:8],
bram_1_serverAdapterA_outData_outData_wget[23:16],
bram_1_serverAdapterA_outData_outData_wget[31:24],
bram_2_serverAdapterA_outData_outData_wget[7:0],
bram_2_serverAdapterA_outData_outData_wget[15:8],
bram_2_serverAdapterA_outData_outData_wget[23:16],
bram_2_serverAdapterA_outData_outData_wget[31:24],
bram_3_serverAdapterA_outData_outData_wget[7:0],
bram_3_serverAdapterA_outData_outData_wget[15:8],
bram_3_serverAdapterA_outData_outData_wget[23:16],
bram_3_serverAdapterA_outData_outData_wget[31:24] } ;
assign NOT_SEL_ARR_NOT_tlp_tlpBRAM_writeRemainDWLen_5_ETC___d681 =
(!SEL_ARR_NOT_tlp_tlpBRAM_writeRemainDWLen_52_EQ_ETC___d669 ||
bram_1_serverAdapterA_cnt_44_SLT_3___d620) &&
(!SEL_ARR_NOT_tlp_tlpBRAM_writeRemainDWLen_52_EQ_ETC___d673 ||
bram_2_serverAdapterA_cnt_62_SLT_3___d621) &&
(!SEL_ARR_NOT_tlp_tlpBRAM_writeRemainDWLen_52_EQ_ETC___d677 ||
bram_3_serverAdapterA_cnt_80_SLT_3___d622) ;
assign NOT_tlp_tlpBRAM_writeRemainDWLen_52_ULE_1_55___d656 =
tlp_tlpBRAM_writeRemainDWLen > 10'd1 ;
assign NOT_tlp_tlpBRAM_writeRemainDWLen_52_ULE_2_57___d658 =
tlp_tlpBRAM_writeRemainDWLen > 10'd2 ;
assign NOT_tlp_tlpBRAM_writeRemainDWLen_52_ULE_3_59___d660 =
tlp_tlpBRAM_writeRemainDWLen > 10'd3 ;
assign NOT_wmi_wrActive_717_718_OR_NOT_wmi_rdActive_7_ETC___d1727 =
(!wmi_wrActive || !wmi_rdActive) && !wmi_wrFinalize &&
(wmi_mesgBufReady || wmi_mesgBusy) ;
assign _dfoo1 =
wci_respF_cntr_r != 2'd2 ||
wci_respF_cntr_r_90_MINUS_1___d499 == 2'd1 ;
assign _dfoo3 =
wci_respF_cntr_r != 2'd1 ||
wci_respF_cntr_r_90_MINUS_1___d499 == 2'd0 ;
assign _dfoo5 =
tlp_fabMesgAddrMS != 32'd0 ||
tlp_tlpBRAM_mRespF_D_OUT[71:62] != 10'd1 ||
tlp_tlpBRAM_mRespF_D_OUT[42:35] == 8'h01 ;
assign _dfoo7 =
wmi_wmi_respF_cntr_r != 2'd2 ||
wmi_wmi_respF_cntr_r_582_MINUS_1___d1590 == 2'd1 ;
assign _dfoo9 =
wmi_wmi_respF_cntr_r != 2'd1 ||
wmi_wmi_respF_cntr_r_582_MINUS_1___d1590 == 2'd0 ;
assign ab__h10465 =
(MUX_bram_3_memory_a_put_1__SEL_3 ||
WILL_FIRE_RL_tlp_tlpBRAM_read_NextReq) ?
2'd0 :
2'd2 ;
assign ab__h11870 =
MUX_bram_0_serverAdapterB_writeWithResp_wset_1__SEL_1 ?
2'd0 :
2'd2 ;
assign ab__h1619 =
(MUX_bram_0_memory_a_put_1__SEL_3 ||
WILL_FIRE_RL_tlp_tlpBRAM_read_NextReq) ?
2'd0 :
2'd2 ;
assign ab__h3026 =
MUX_bram_0_serverAdapterB_writeWithResp_wset_1__SEL_1 ?
2'd0 :
2'd2 ;
assign ab__h4569 =
(MUX_bram_1_memory_a_put_1__SEL_3 ||
WILL_FIRE_RL_tlp_tlpBRAM_read_NextReq) ?
2'd0 :
2'd2 ;
assign ab__h5974 =
MUX_bram_0_serverAdapterB_writeWithResp_wset_1__SEL_1 ?
2'd0 :
2'd2 ;
assign ab__h7517 =
(MUX_bram_2_memory_a_put_1__SEL_3 ||
WILL_FIRE_RL_tlp_tlpBRAM_read_NextReq) ?
2'd0 :
2'd2 ;
assign ab__h8922 =
MUX_bram_0_serverAdapterB_writeWithResp_wset_1__SEL_1 ?
2'd0 :
2'd2 ;
assign bml_crdBuf_value_880_EQ_bml_crdBuf_modulus_bw__ETC___d1882 =
bml_crdBuf_value == bml_crdBuf_modulus ;
assign bml_fabBuf_value_865_EQ_bml_fabBuf_modulus_bw__ETC___d1867 =
bml_fabBuf_value == bml_fabBuf_modulus ;
assign bml_fabFlowAddr_937_PLUS_bml_fabFlowSize_938___d1939 =
bml_fabFlowAddr + bml_fabFlowSize ;
assign bml_lclBufDone_922_AND_IF_bml_dpControl_wget___ETC___d2003 =
bml_lclBufDone &&
CASE_dpControl_BITS_1_TO_0_0_NOT_bml_fabDone_1_ETC__q6 ||
!bml_lclBufDone &&
CASE_dpControl_BITS_1_TO_0_0_bml_fabDone_1_IF__ETC__q7 ;
assign bml_lclBuf_value_835_EQ_bml_lclBuf_modulus_bw__ETC___d1837 =
bml_lclBuf_value == bml_lclBuf_modulus ;
assign bml_remBuf_value_850_EQ_bml_remBuf_modulus_bw__ETC___d1852 =
bml_remBuf_value == bml_remBuf_modulus ;
assign bram_0_serverAdapterA_cnt_6_PLUS_IF_bram_0_ser_ETC___d32 =
bram_0_serverAdapterA_cnt +
(bram_0_serverAdapterA_cnt_1_whas ? 3'd1 : 3'd0) +
(bram_0_serverAdapterA_outData_deqCalled_whas ? 3'd7 : 3'd0) ;
assign bram_0_serverAdapterA_cnt_6_SLT_3___d619 =
(bram_0_serverAdapterA_cnt ^ 3'h4) < 3'd7 ;
assign bram_0_serverAdapterA_outDataCore_notEmpty_OR__ETC___d887 =
(bram_0_serverAdapterA_outDataCore_EMPTY_N ||
bram_0_serverAdapterA_outData_enqData_whas) &&
(bram_1_serverAdapterA_outDataCore_EMPTY_N ||
bram_1_serverAdapterA_outData_enqData_whas) &&
bram_2_serverAdapterA_outDataCore_notEmpty__38_ETC___d885 ;
assign bram_0_serverAdapterB_cnt_5_PLUS_IF_bram_0_ser_ETC___d91 =
bram_0_serverAdapterB_cnt +
(bram_0_serverAdapterB_cnt_1_whas ? 3'd1 : 3'd0) +
(bram_0_serverAdapterB_outData_deqCalled_whas ? 3'd7 : 3'd0) ;
assign bram_0_serverAdapterB_cnt_5_SLT_3_666_AND_bram_ETC___d1672 =
bram_0_serverAdapterB_cnt_5_SLT_3___d1666 &&
bram_1_serverAdapterB_cnt_03_SLT_3___d1667 &&
bram_2_serverAdapterB_cnt_21_SLT_3___d1668 &&
bram_3_serverAdapterB_cnt_39_SLT_3___d1669 ;
assign bram_0_serverAdapterB_cnt_5_SLT_3___d1666 =
(bram_0_serverAdapterB_cnt ^ 3'h4) < 3'd7 ;
assign bram_0_serverAdapterB_outData_outData_whas__68_ETC___d1697 =
bram_0_serverAdapterB_outData_outData_whas &&
(bram_1_serverAdapterB_outDataCore_EMPTY_N ||
bram_1_serverAdapterB_outData_enqData_whas) &&
bram_1_serverAdapterB_outData_outData_whas__68_ETC___d1695 ;
assign bram_1_serverAdapterA_cnt_44_PLUS_IF_bram_1_se_ETC___d150 =
bram_1_serverAdapterA_cnt +
(bram_1_serverAdapterA_cnt_1_whas ? 3'd1 : 3'd0) +
(bram_1_serverAdapterA_outData_deqCalled_whas ? 3'd7 : 3'd0) ;
assign bram_1_serverAdapterA_cnt_44_SLT_3___d620 =
(bram_1_serverAdapterA_cnt ^ 3'h4) < 3'd7 ;
assign bram_1_serverAdapterB_cnt_03_PLUS_IF_bram_1_se_ETC___d209 =
bram_1_serverAdapterB_cnt +
(bram_1_serverAdapterB_cnt_1_whas ? 3'd1 : 3'd0) +
(bram_0_serverAdapterB_outData_deqCalled_whas ? 3'd7 : 3'd0) ;
assign bram_1_serverAdapterB_cnt_03_SLT_3___d1667 =
(bram_1_serverAdapterB_cnt ^ 3'h4) < 3'd7 ;
assign bram_1_serverAdapterB_outData_outData_whas__68_ETC___d1695 =
bram_1_serverAdapterB_outData_outData_whas &&
(bram_2_serverAdapterB_outDataCore_EMPTY_N ||
bram_2_serverAdapterB_outData_enqData_whas) &&
bram_2_serverAdapterB_outData_outData_whas &&
(bram_3_serverAdapterB_outDataCore_EMPTY_N ||
bram_3_serverAdapterB_outData_enqData_whas) &&
bram_3_serverAdapterB_outData_outData_whas ;
assign bram_2_serverAdapterA_cnt_62_PLUS_IF_bram_2_se_ETC___d268 =
bram_2_serverAdapterA_cnt +
(bram_2_serverAdapterA_cnt_1_whas ? 3'd1 : 3'd0) +
(bram_2_serverAdapterA_outData_deqCalled_whas ? 3'd7 : 3'd0) ;
assign bram_2_serverAdapterA_cnt_62_SLT_3___d621 =
(bram_2_serverAdapterA_cnt ^ 3'h4) < 3'd7 ;
assign bram_2_serverAdapterA_outDataCore_notEmpty__38_ETC___d885 =
(bram_2_serverAdapterA_outDataCore_EMPTY_N ||
bram_2_serverAdapterA_outData_enqData_whas) &&
(bram_3_serverAdapterA_outDataCore_EMPTY_N ||
bram_3_serverAdapterA_outData_enqData_whas) &&
bram_0_serverAdapterA_outData_outData_whas &&
bram_1_serverAdapterA_outData_outData_whas &&
bram_2_serverAdapterA_outData_outData_whas &&
bram_3_serverAdapterA_outData_outData_whas &&
tlp_tlpBRAM_mRespF_FULL_N ;
assign bram_2_serverAdapterB_cnt_21_PLUS_IF_bram_2_se_ETC___d327 =
bram_2_serverAdapterB_cnt +
(bram_2_serverAdapterB_cnt_1_whas ? 3'd1 : 3'd0) +
(bram_0_serverAdapterB_outData_deqCalled_whas ? 3'd7 : 3'd0) ;
assign bram_2_serverAdapterB_cnt_21_SLT_3___d1668 =
(bram_2_serverAdapterB_cnt ^ 3'h4) < 3'd7 ;
assign bram_3_serverAdapterA_cnt_80_PLUS_IF_bram_3_se_ETC___d386 =
bram_3_serverAdapterA_cnt +
(bram_3_serverAdapterA_cnt_1_whas ? 3'd1 : 3'd0) +
(bram_3_serverAdapterA_outData_deqCalled_whas ? 3'd7 : 3'd0) ;
assign bram_3_serverAdapterA_cnt_80_SLT_3___d622 =
(bram_3_serverAdapterA_cnt ^ 3'h4) < 3'd7 ;
assign bram_3_serverAdapterB_cnt_39_PLUS_IF_bram_3_se_ETC___d445 =
bram_3_serverAdapterB_cnt +
(bram_3_serverAdapterB_cnt_1_whas ? 3'd1 : 3'd0) +
(bram_0_serverAdapterB_outData_deqCalled_whas ? 3'd7 : 3'd0) ;
assign bram_3_serverAdapterB_cnt_39_SLT_3___d1669 =
(bram_3_serverAdapterB_cnt ^ 3'h4) < 3'd7 ;
assign byteCount__h29653 = x__h29771 - y__h29772 ;
assign hasPull_AND_tlp_dpControl_wget__64_BITS_7_TO_4_ETC___d1233 =
hasPull && dpControl[7:4] == 4'd0 && dpControl[3:2] == 2'd2 &&
dpControl[1:0] == 2'd1 &&
!tlp_tlpXmtBusy &&
!tlp_reqMetaInFlight &&
!tlp_reqMetaBodyInFlight &&
!tlp_fabMeta[128] ;
assign hasPull_AND_tlp_dpControl_wget__64_BITS_7_TO_4_ETC___d1274 =
hasPull && dpControl[7:4] == 4'd0 && dpControl[3:2] == 2'd2 &&
dpControl[1:0] == 2'd1 &&
tlp_reqMetaInFlight &&
!tlp_tlpRcvBusy &&
tagm__h64387 == tlp_inF_D_OUT[47:40] &&
tlp_inF_first__259_BITS_63_TO_56_262_EQ_pciDev_ETC___d1272 ;
assign hasPull_AND_tlp_dpControl_wget__64_BITS_7_TO_4_ETC___d1326 =
hasPull && dpControl[7:4] == 4'd0 && dpControl[3:2] == 2'd2 &&
dpControl[1:0] == 2'd1 &&
tlp_fabMeta[128] &&
tlp_fabMeta[127:96] != 32'd0 &&
!tlp_tlpXmtBusy &&
!tlp_reqMesgInFlight &&
tlp_mesgLengthRemainPull != 17'd0 ;
assign hasPull_AND_tlp_dpControl_wget__64_BITS_7_TO_4_ETC___d1365 =
hasPull && dpControl[7:4] == 4'd0 && dpControl[3:2] == 2'd2 &&
dpControl[1:0] == 2'd1 &&
tlp_fabMeta[128] &&
tlp_reqMesgInFlight &&
!tlp_tlpRcvBusy &&
tlp_pullTagMatch &&
!tlp_gotResponseHeader ;
assign hasPull_AND_tlp_dpControl_wget__64_BITS_7_TO_4_ETC___d1385 =
hasPull && dpControl[7:4] == 4'd0 && dpControl[3:2] == 2'd2 &&
dpControl[1:0] == 2'd1 &&
tlp_fabMeta[128] &&
tlp_reqMesgInFlight &&
tlp_gotResponseHeader ;
assign hasPull_AND_tlp_dpControl_wget__64_BITS_7_TO_4_ETC___d1410 =
hasPull && dpControl[7:4] == 4'd0 && dpControl[3:2] == 2'd2 &&
dpControl[1:0] == 2'd1 &&
tlp_fabMeta[128] &&
tlp_dmaDoTailEvent &&
tlp_postSeqDwell == 4'd0 &&
tlp_mesgComplReceived >= tlp_fabMeta[112:96] ;
assign hasPush_AND_tlp_dpControl_wget__64_BITS_7_TO_4_ETC___d1058 =
hasPush && dpControl[7:4] == 4'd0 && dpControl[3:2] == 2'd1 &&
dpControl[1:0] == 2'd1 &&
tlp_fabMeta[128] &&
tlp_fabMeta[127:96] != 32'd0 &&
!tlp_tlpRcvBusy &&
tlp_mesgLengthRemainPush != 17'd0 ;
assign hasPush_AND_tlp_dpControl_wget__64_BITS_7_TO_4_ETC___d1098 =
hasPush && dpControl[7:4] == 4'd0 && dpControl[3:2] == 2'd1 &&
dpControl[1:0] == 2'd1 &&
!tlp_tlpBRAM_mRespF_D_OUT[138] &&
tlp_tlpBRAM_mRespF_D_OUT[89:88] == 2'd2 &&
!tlp_tlpXmtBusy &&
tlp_postSeqDwell == 4'd0 ;
assign hasPush_AND_tlp_dpControl_wget__64_BITS_7_TO_4_ETC___d1155 =
hasPush && dpControl[7:4] == 4'd0 && dpControl[3:2] == 2'd1 &&
dpControl[1:0] == 2'd1 &&
tlp_fabMeta[128] &&
!tlp_tlpXmtBusy &&
!tlp_xmtMetaInFlight &&
tlp_xmtMetaOK &&
tlp_postSeqDwell == 4'd0 ;
assign hasPush_AND_tlp_dpControl_wget__64_BITS_7_TO_4_ETC___d985 =
hasPush && dpControl[7:4] == 4'd0 && dpControl[3:2] == 2'd1 &&
dpControl[1:0] == 2'd1 &&
!tlp_tlpRcvBusy &&
!tlp_reqMetaInFlight &&
!tlp_fabMeta[128] &&
tlp_nearBufReady ;
assign idx__h21626 = 2'd0 - tlp_tlpBRAM_writeDWAddr[1:0] ;
assign idx__h23676 = 2'd1 - tlp_tlpBRAM_writeDWAddr[1:0] ;
assign idx__h24781 = 2'd2 - tlp_tlpBRAM_writeDWAddr[1:0] ;
assign idx__h25886 = 2'd3 - tlp_tlpBRAM_writeDWAddr[1:0] ;
assign idx__h27879 = 2'd0 - tlp_tlpBRAM_readNxtDWAddr[1:0] ;
assign idx__h28282 = 2'd1 - tlp_tlpBRAM_readNxtDWAddr[1:0] ;
assign idx__h28586 = 2'd2 - tlp_tlpBRAM_readNxtDWAddr[1:0] ;
assign idx__h28890 = 2'd3 - tlp_tlpBRAM_readNxtDWAddr[1:0] ;
assign lastBE__h47950 =
tlp_tlpBRAM_mRespF_first__000_BITS_71_TO_62_10_ETC___d1102 ?
4'd0 :
4'd15 ;
assign lastBE__h64200 =
(thisRequestLength__h63893[11:2] == 10'd1) ? 4'd0 : 4'd15 ;
assign lowAddr__h29652 =
{ tlp_tlpBRAM_readReq_D_OUT[33:29], lowAddr10__h29651 } ;
assign mesgMeta_opcode__h81853 =
{ 24'h800000, wmi_wmi_mFlagF_D_OUT[31:24] } ;
assign nowLS__h46239 =
{ tlp_tlpBRAM_mRespF_D_OUT[39:32],
tlp_tlpBRAM_mRespF_D_OUT[47:40],
tlp_tlpBRAM_mRespF_D_OUT[55:48],
tlp_tlpBRAM_mRespF_D_OUT[63:56] } ;
assign nowLS__h62622 =
{ tlp_inF_D_OUT[39:32],
tlp_inF_D_OUT[47:40],
tlp_inF_D_OUT[55:48],
tlp_inF_D_OUT[63:56] } ;
assign nowMS__h45280 =
{ tlp_tlpBRAM_mRespF_D_OUT[71:64],
tlp_tlpBRAM_mRespF_D_OUT[79:72],
tlp_tlpBRAM_mRespF_D_OUT[87:80],
tlp_tlpBRAM_mRespF_D_OUT[95:88] } ;
assign nowMS__h61665 =
{ tlp_inF_D_OUT[71:64],
tlp_inF_D_OUT[79:72],
tlp_inF_D_OUT[87:80],
tlp_inF_D_OUT[95:88] } ;
assign opcode__h44022 =
{ tlp_tlpBRAM_mRespF_D_OUT[103:96],
tlp_tlpBRAM_mRespF_D_OUT[111:104],
tlp_tlpBRAM_mRespF_D_OUT[119:112],
tlp_tlpBRAM_mRespF_D_OUT[127:120] } ;
assign opcode__h60417 =
{ tlp_inF_D_OUT[103:96],
tlp_inF_D_OUT[111:104],
tlp_inF_D_OUT[119:112],
tlp_inF_D_OUT[127:120] } ;
assign pkt__h71785 =
{ 9'd148,
tlp_tlpBRAM_mRespF_D_OUT[34:32],
10'd0,
tlp_tlpBRAM_mRespF_D_OUT[71:62],
pciDevice,
4'd0,
tlp_tlpBRAM_mRespF_D_OUT[54:43],
tlp_tlpBRAM_mRespF_D_OUT[87:72],
tlp_tlpBRAM_mRespF_D_OUT[42:35],
1'b0,
tlp_tlpBRAM_mRespF_D_OUT[61:55],
tlp_tlpBRAM_mRespF_D_OUT[31:0] } ;
assign rdat__h92026 = { 16'd0, bml_lclNumBufs } ;
assign rdat__h92034 = { 16'd0, bml_fabNumBufs } ;
assign rdat__h92042 = { 16'd0, bml_mesgBase } ;
assign rdat__h92050 = { 16'd0, bml_metaBase } ;
assign rdat__h92058 = { 16'd0, bml_mesgSize } ;
assign rdat__h92066 = { 16'd0, bml_metaSize } ;
assign rdat__h92074 = { 16'd0, bml_lclBufsCF } ;
assign rdat__h92095 =
hasDebugLogic ? { bml_lclBufsAR, bml_fabBufsAvail } : 32'd0 ;
assign rdat__h92102 =
hasDebugLogic ? { bml_remBuf_value, bml_lclBuf_value } : 32'd0 ;
assign rdat__h92115 =
hasDebugLogic ? { bml_lclStarts, bml_lclDones } : 32'd0 ;
assign rdat__h92122 =
hasDebugLogic ? { bml_remStarts, bml_remDones } : 32'd0 ;
assign rdat__h92129 = hasDebugLogic ? wmi_thisMesg : 32'd0 ;
assign rdat__h92401 = hasDebugLogic ? wmi_lastMesg : 32'd0 ;
assign rdat__h92451 =
hasDebugLogic ? { wmi_reqCount, wmi_wrtCount } : 32'd0 ;
assign rdat__h92551 = hasDebugLogic ? 32'hDADEBABE : 32'd0 ;
assign rdat__h92609 = { 24'd0, dpControl } ;
assign rdat__h92631 = hasDebugLogic ? tlp_flowDiagCount : 32'd0 ;
assign rdat__h92641 =
hasDebugLogic ?
{ 4'h0,
tlp_complTimerCount,
12'h0,
CASE_tlp_lastRuleFired_1_tlp_lastRuleFired_2_t_ETC__q1 } :
32'd0 ;
assign rdat__h92763 = hasDebugLogic ? tlp_lastMetaV_0 : 32'd0 ;
assign rdat__h92887 = hasDebugLogic ? tlp_lastMetaV_1 : 32'd0 ;
assign rdat__h92915 = hasDebugLogic ? tlp_lastMetaV_2 : 32'd0 ;
assign rdat__h92943 = hasDebugLogic ? tlp_lastMetaV_3 : 32'd0 ;
assign rdat__h92971 = hasDebugLogic ? 32'hC0DE0111 : 32'd0 ;
assign rdat__h93001 = hasDebugLogic ? dmaStartTime[31:0] : 32'd0 ;
assign rdat__h93035 = hasDebugLogic ? dmaStartTime[63:32] : 32'd0 ;
assign rdat__h93068 = hasDebugLogic ? dmaDoneTime[31:0] : 32'd0 ;
assign rdat__h93102 = hasDebugLogic ? dmaDoneTime[63:32] : 32'd0 ;
assign rdata__h35173 =
tlp_tlpBRAM_readReq_first__98_BITS_30_TO_29_00_ETC___d922[1] ?
IF_tlp_tlpBRAM_readReq_first__98_BITS_30_TO_29_ETC___d929 :
IF_tlp_tlpBRAM_readReq_first__98_BITS_30_TO_29_ETC___d934 ;
assign rdata__h83703 =
{ bram_3_serverAdapterB_outData_outData_wget,
bram_2_serverAdapterB_outData_outData_wget,
bram_1_serverAdapterB_outData_outData_wget,
bram_0_serverAdapterB_outData_outData_wget } ;
assign rreq_tag__h47719 =
(y__h47529 == tlp_mesgLengthRemainPush) ? 8'h01 : 8'h0 ;
assign rresp_data__h29698 =
{ SEL_ARR_bram_0_serverAdapterA_outData_outData__ETC___d863[7:0],
SEL_ARR_bram_0_serverAdapterA_outData_outData__ETC___d863[15:8],
SEL_ARR_bram_0_serverAdapterA_outData_outData__ETC___d863[23:16],
SEL_ARR_bram_0_serverAdapterA_outData_outData__ETC___d863[31:24] } ;
assign spanToNextPage__h47503 = 13'd4096 - { 1'd0, tlp_srcMesgAccu[11:0] } ;
assign spanToNextPage__h63892 = 13'd4096 - { 1'd0, tlp_fabMesgAccu[11:0] } ;
assign tag__h64168 = { 3'd0, tlp_dmaTag } ;
assign tagm__h64387 = { 3'd0, tlp_dmaReqTag } ;
assign thisRequestLength__h47504 =
(x__h47542[12:0] <= spanToNextPage__h47503) ?
x__h47542[12:0] :
spanToNextPage__h47503 ;
assign thisRequestLength__h63893 =
(x__h63926[12:0] <= spanToNextPage__h63892) ?
x__h63926[12:0] :
spanToNextPage__h63892 ;
assign tlp_dmaPullRemainDWLen_373_ULE_tlp_dmaPullRema_ETC___d1395 =
tlp_dmaPullRemainDWLen <= tlp_dmaPullRemainDWSub ;
assign tlp_dmaPullRemainDWSub_387_ULE_4___d1388 =
tlp_dmaPullRemainDWSub <= 10'd4 ;
assign tlp_inF_first__259_BITS_63_TO_56_262_EQ_pciDev_ETC___d1272 =
tlp_inF_D_OUT[63:56] == pciDevice[15:8] &&
tlp_inF_D_OUT[55:51] == pciDevice[7:3] &&
tlp_inF_D_OUT[50:48] == pciDevice[2:0] ;
assign tlp_inF_first__259_BIT_152_462_AND_NOT_tlp_inF_ETC___d1487 =
tlp_inF_D_OUT[152] && !tlp_inF_D_OUT[110] &&
!tlp_inF_D_OUT[125] &&
tlp_inF_D_OUT[124:120] == 5'b0 ||
!tlp_inF_D_OUT[152] && !tlp_inIgnorePkt ;
assign tlp_mesgLengthRemainPull_PLUS_3__q14 =
tlp_mesgLengthRemainPull + 17'd3 ;
assign tlp_mesgLengthRemainPush_PLUS_3__q15 =
tlp_mesgLengthRemainPush + 17'd3 ;
assign tlp_outDwRemain_129_ULE_4___d1130 = tlp_outDwRemain <= 10'd4 ;
assign tlp_tlpBRAM_mRespF_first__000_BITS_71_TO_62_10_ETC___d1102 =
tlp_tlpBRAM_mRespF_D_OUT[71:62] <= 10'd1 ;
assign tlp_tlpBRAM_mRespF_i_notFull__97_AND_tlp_tlpBR_ETC___d813 =
tlp_tlpBRAM_mRespF_FULL_N &&
(tlp_tlpBRAM_readReq_D_OUT[60] ||
CASE_tlp_tlpBRAM_readReq_first__98_BITS_30_TO__ETC___d805 &&
CASE_tlp_tlpBRAM_readReq_first__98_BITS_30_TO__ETC___d810) ;
assign tlp_tlpBRAM_rdRespDwRemain_16_ULE_4___d918 =
tlp_tlpBRAM_rdRespDwRemain <= 10'd4 ;
assign tlp_tlpBRAM_readNxtDWAddr_PLUS_1__q11 =
tlp_tlpBRAM_readNxtDWAddr + 13'd1 ;
assign tlp_tlpBRAM_readNxtDWAddr_PLUS_2__q12 =
tlp_tlpBRAM_readNxtDWAddr + 13'd2 ;
assign tlp_tlpBRAM_readNxtDWAddr_PLUS_3__q13 =
tlp_tlpBRAM_readNxtDWAddr + 13'd3 ;
assign tlp_tlpBRAM_readRemainDWLen_74_ULE_4___d775 =
tlp_tlpBRAM_readRemainDWLen <= 10'd4 ;
assign tlp_tlpBRAM_readReq_first__98_BITS_30_TO_29_00_ETC___d922 =
tlp_tlpBRAM_readReq_D_OUT[30:29] +
(tlp_tlpBRAM_readReq_D_OUT[60] ? 2'd0 : 2'd1) ;
assign tlp_tlpBRAM_writeDWAddr_PLUS_1__q8 =
tlp_tlpBRAM_writeDWAddr + 13'd1 ;
assign tlp_tlpBRAM_writeDWAddr_PLUS_2__q9 =
tlp_tlpBRAM_writeDWAddr + 13'd2 ;
assign tlp_tlpBRAM_writeDWAddr_PLUS_3__q10 =
tlp_tlpBRAM_writeDWAddr + 13'd3 ;
assign w_be__h48508 =
tlp_outDwRemain_129_ULE_4___d1130 ?
CASE_tlp_outDwRemain_BITS_1_TO_0_0b0_0xFFFF_0b_ETC__q3 :
16'd65535 ;
assign w_data__h47916 =
{ 22'd1048576,
tlp_tlpBRAM_mRespF_D_OUT[71:62],
pciDevice,
8'd0,
lastBE__h47950,
4'd15,
tlp_fabMesgAccu,
tlp_tlpBRAM_mRespF_D_OUT[31:0] } ;
assign w_data__h48052 =
{ 22'd1572864,
tlp_tlpBRAM_mRespF_D_OUT[71:62],
pciDevice,
8'd0,
lastBE__h47950,
4'd15,
tlp_fabMesgAddrMS,
tlp_fabMesgAccu } ;
assign w_data__h52877 =
{ tlp_fabMeta[103:96],
tlp_fabMeta[111:104],
tlp_fabMeta[119:112],
tlp_fabMeta[127:120],
tlp_fabMeta[71:64],
tlp_fabMeta[79:72],
tlp_fabMeta[87:80],
tlp_fabMeta[95:88],
tlp_fabMeta[39:32],
tlp_fabMeta[47:40],
tlp_fabMeta[55:48],
tlp_fabMeta[63:56],
tlp_fabMeta[7:0],
tlp_fabMeta[15:8],
tlp_fabMeta[23:16],
tlp_fabMeta[31:24] } ;
assign w_data__h65836 =
{ 32'd1073741825,
pciDevice,
16'd15,
tlp_fabFlowAddr,
wti_nowReq_BITS_63_TO_0__q2[12:6],
1'd1,
wti_nowReq_BITS_63_TO_0__q2[20:13],
wti_nowReq_BITS_63_TO_0__q2[28:21],
wti_nowReq_BITS_63_TO_0__q2[36:29] } ;
assign w_data__h66940 =
{ 32'd1610612737,
pciDevice,
16'd15,
tlp_fabFlowAddrMS,
tlp_fabFlowAddr } ;
assign w_data__h67186 =
{ wti_nowReq_BITS_63_TO_0__q2[12:6],
1'd1,
wti_nowReq_BITS_63_TO_0__q2[20:13],
wti_nowReq_BITS_63_TO_0__q2[28:21],
wti_nowReq_BITS_63_TO_0__q2[36:29],
96'd0 } ;
assign wci_respF_cntr_r_90_MINUS_1___d499 = wci_respF_cntr_r - 2'd1 ;
assign wmi_wmi_operateD_606_AND_wmi_wmi_peerIsReady_6_ETC___d1777 =
wmi_wmi_operateD && wmi_wmi_peerIsReady &&
bram_0_serverAdapterB_cnt_5_SLT_3___d1666 &&
bram_1_serverAdapterB_cnt_03_SLT_3___d1667 &&
bram_2_serverAdapterB_cnt_21_SLT_3___d1668 &&
bram_3_serverAdapterB_cnt_39_SLT_3___d1669 &&
wmi_wmi_mFlagF_EMPTY_N ;
assign wmi_wmi_operateD_606_AND_wmi_wmi_peerIsReady_6_ETC___d1798 =
wmi_wmi_operateD && wmi_wmi_peerIsReady &&
(bram_0_serverAdapterB_outDataCore_EMPTY_N ||
bram_0_serverAdapterB_outData_enqData_whas) &&
bram_0_serverAdapterB_outData_outData_whas__68_ETC___d1697 ;
assign wmi_wmi_respF_cntr_r_582_MINUS_1___d1590 =
wmi_wmi_respF_cntr_r - 2'd1 ;
assign wti_nowReq_BITS_63_TO_0__q2 = wti_nowReq[63:0] ;
assign x3__h81813 = { 8'd0, wmi_wmi_mFlagF_D_OUT[23:0] } ;
assign x__h29771 = x__h29773 - y__h29774 ;
assign x__h29773 = { tlp_tlpBRAM_readReq_D_OUT[28:19], 2'b0 } ;
assign x__h42208 =
{ tlp_tlpBRAM_mRespF_D_OUT[7:0],
tlp_tlpBRAM_mRespF_D_OUT[15:8],
tlp_tlpBRAM_mRespF_D_OUT[23:16],
tlp_tlpBRAM_mRespF_D_OUT[31:24] } ;
assign x__h47258 = { 15'd0, tlp_mesgLengthRemainPush } ;
assign x__h47542 =
(tlp_mesgLengthRemainPush <= y__h47544) ?
tlp_mesgLengthRemainPush :
y__h47544 ;
assign x__h58352 =
{ tlp_inF_D_OUT[7:0],
tlp_inF_D_OUT[15:8],
tlp_inF_D_OUT[23:16],
tlp_inF_D_OUT[31:24] } ;
assign x__h63608 = { 15'd0, tlp_mesgLengthRemainPull } ;
assign x__h63926 =
(tlp_mesgLengthRemainPull <= y__h63928) ?
tlp_mesgLengthRemainPull :
y__h63928 ;
assign x__h88675 = (dpControl[1:0] == 2'd1) ? bml_fabNumBufs : 16'd0 ;
assign x__h89803 = bml_lclBufsAR + 16'd1 ;
assign x__h89808 = bml_lclBufsAR - 16'd1 ;
assign x__h89915 = bml_lclBufsCF + 16'd1 ;
assign x__h89952 = bml_lclBufsCF - 16'd1 ;
assign x__h90034 = bml_fabBufsAvail + 16'd1 ;
assign x__h90039 = bml_fabBufsAvail - 16'd1 ;
assign x__h90073 = bml_lclCredit + 16'd1 ;
assign x__h90078 = bml_lclCredit - 16'd1 ;
assign y__h17362 = tlp_tlpBRAM_mReqF_D_OUT[63] ? 13'd0 : 13'd1 ;
assign y__h17428 = tlp_tlpBRAM_mReqF_D_OUT[63] ? 10'd0 : 10'd1 ;
assign y__h27653 = tlp_tlpBRAM_mReqF_D_OUT[60] ? 10'd0 : 10'd1 ;
assign y__h27665 = tlp_tlpBRAM_mReqF_D_OUT[60] ? 13'd0 : 13'd1 ;
assign y__h29772 =
(tlp_tlpBRAM_readReq_D_OUT[28:19] == 10'd1) ?
12'd0 :
{ 10'd0, x__h29803 } ;
assign y__h29774 = { 10'd0, x__h29780 } ;
assign y__h30729 = tlp_tlpBRAM_readReq_D_OUT[60] ? 10'd0 : 10'd1 ;
assign y__h47529 = { 4'd0, thisRequestLength__h47504 } ;
assign y__h47544 = { 4'd0, tlp_maxPayloadSize } ;
assign y__h47623 = { 19'd0, thisRequestLength__h47504 } ;
assign y__h47671 = { 3'd0, thisRequestLength__h47504 } ;
assign y__h48147 = (tlp_fabMesgAddrMS == 32'd0) ? 10'd1 : 10'd0 ;
assign y__h48181 = { 20'd0, tlp_tlpBRAM_mRespF_D_OUT[71:62], 2'd0 } ;
assign y__h63918 = { 4'd0, thisRequestLength__h63893 } ;
assign y__h63928 = { 4'd0, tlp_maxReadReqSize } ;
assign y__h63989 = { 19'd0, thisRequestLength__h63893 } ;
assign y__h64598 = { 4'd0, tlp_inF_D_OUT[105:96], 2'd0 } ;
assign y__h65310 =
tlp_dmaPullRemainDWSub_387_ULE_4___d1388 ?
{ 5'd0, tlp_dmaPullRemainDWSub, 2'd0 } :
17'd16 ;
always@(tlp_tlpBRAM_readReq_D_OUT)
begin
case (tlp_tlpBRAM_readReq_D_OUT[18:15])
4'b1100: x__h29780 = 2'b10;
4'b1110: x__h29780 = 2'b01;
4'b1111: x__h29780 = 2'b0;
default: x__h29780 = 2'b11;
endcase
end
always@(tlp_tlpBRAM_readReq_D_OUT)
begin
case (tlp_tlpBRAM_readReq_D_OUT[14:11])
4'b1100: x__h29803 = 2'b10;
4'b1110: x__h29803 = 2'b01;
4'b1111: x__h29803 = 2'b0;
default: x__h29803 = 2'b11;
endcase
end
always@(tlp_lastRuleFired)
begin
case (tlp_lastRuleFired)
4'd1, 4'd2, 4'd3, 4'd4, 4'd5, 4'd6, 4'd7, 4'd8, 4'd9, 4'd15:
CASE_tlp_lastRuleFired_1_tlp_lastRuleFired_2_t_ETC__q1 =
tlp_lastRuleFired;
default: CASE_tlp_lastRuleFired_1_tlp_lastRuleFired_2_t_ETC__q1 = 4'd10;
endcase
end
always@(wci_reqF_D_OUT or
rdat__h92026 or
rdat__h92034 or
rdat__h92042 or
rdat__h92050 or
rdat__h92058 or
rdat__h92066 or
rdat__h92074 or
rdat__h92095 or
rdat__h92102 or
rdat__h92115 or
rdat__h92122 or
rdat__h92129 or
rdat__h92401 or
rdat__h92451 or
rdat__h92551 or
bml_fabMesgBase or
bml_fabMetaBase or
bml_fabMesgSize or
bml_fabMetaSize or
bml_fabFlowBase or
bml_fabFlowSize or
rdat__h92609 or
rdat__h92631 or
rdat__h92641 or
rdat__h92763 or
rdat__h92887 or
rdat__h92915 or
rdat__h92943 or
rdat__h92971 or
bml_fabMesgBaseMS or
bml_fabMetaBaseMS or
bml_fabFlowBaseMS or
rdat__h93001 or rdat__h93035 or rdat__h93068 or rdat__h93102)
begin
case (wci_reqF_D_OUT[39:32])
8'h0: _theResult____h91947 = rdat__h92026;
8'h04: _theResult____h91947 = rdat__h92034;
8'h08: _theResult____h91947 = rdat__h92042;
8'h0C: _theResult____h91947 = rdat__h92050;
8'h10: _theResult____h91947 = rdat__h92058;
8'h14: _theResult____h91947 = rdat__h92066;
8'h20: _theResult____h91947 = rdat__h92074;
8'h24: _theResult____h91947 = 32'hF00DFACE;
8'h28: _theResult____h91947 = rdat__h92095;
8'h2C: _theResult____h91947 = rdat__h92102;
8'h30: _theResult____h91947 = rdat__h92115;
8'h34: _theResult____h91947 = rdat__h92122;
8'h38: _theResult____h91947 = rdat__h92129;
8'h3C: _theResult____h91947 = rdat__h92401;
8'h40: _theResult____h91947 = rdat__h92451;
8'h44: _theResult____h91947 = 32'd0;
8'h48: _theResult____h91947 = rdat__h92551;
8'h4C: _theResult____h91947 = 32'h00008000;
8'h50: _theResult____h91947 = bml_fabMesgBase;
8'h54: _theResult____h91947 = bml_fabMetaBase;
8'h58: _theResult____h91947 = bml_fabMesgSize;
8'h5C: _theResult____h91947 = bml_fabMetaSize;
8'h60: _theResult____h91947 = bml_fabFlowBase;
8'h64: _theResult____h91947 = bml_fabFlowSize;
8'h68: _theResult____h91947 = rdat__h92609;
8'h6C: _theResult____h91947 = rdat__h92631;
8'h70: _theResult____h91947 = rdat__h92641;
8'h80: _theResult____h91947 = rdat__h92763;
8'h84: _theResult____h91947 = rdat__h92887;
8'h88: _theResult____h91947 = rdat__h92915;
8'h8C: _theResult____h91947 = rdat__h92943;
8'h90: _theResult____h91947 = rdat__h92971;
8'h94: _theResult____h91947 = bml_fabMesgBaseMS;
8'h98: _theResult____h91947 = bml_fabMetaBaseMS;
8'h9C: _theResult____h91947 = bml_fabFlowBaseMS;
8'hA0: _theResult____h91947 = rdat__h93001;
8'hA4: _theResult____h91947 = rdat__h93035;
8'hA8: _theResult____h91947 = rdat__h93068;
8'hAC: _theResult____h91947 = rdat__h93102;
default: _theResult____h91947 = 32'd0;
endcase
end
always@(tlp_tlpBRAM_readReq_D_OUT)
begin
case (tlp_tlpBRAM_readReq_D_OUT[18:15])
4'b1000: lowAddr10__h29651 = 2'b11;
4'b1100: lowAddr10__h29651 = 2'b10;
4'b1110: lowAddr10__h29651 = 2'b01;
default: lowAddr10__h29651 = 2'b0;
endcase
end
always@(tlp_tlpBRAM_mReqF_D_OUT or
bram_0_serverAdapterA_cnt_6_SLT_3___d619 or
bram_1_serverAdapterA_cnt_44_SLT_3___d620 or
bram_2_serverAdapterA_cnt_62_SLT_3___d621 or
bram_3_serverAdapterA_cnt_80_SLT_3___d622)
begin
case (tlp_tlpBRAM_mReqF_D_OUT[51:50])
2'd0:
CASE_tlp_tlpBRAM_mReqF_first__16_BITS_51_TO_50_ETC___d623 =
bram_0_serverAdapterA_cnt_6_SLT_3___d619;
2'd1:
CASE_tlp_tlpBRAM_mReqF_first__16_BITS_51_TO_50_ETC___d623 =
bram_1_serverAdapterA_cnt_44_SLT_3___d620;
2'd2:
CASE_tlp_tlpBRAM_mReqF_first__16_BITS_51_TO_50_ETC___d623 =
bram_2_serverAdapterA_cnt_62_SLT_3___d621;
2'd3:
CASE_tlp_tlpBRAM_mReqF_first__16_BITS_51_TO_50_ETC___d623 =
bram_3_serverAdapterA_cnt_80_SLT_3___d622;
endcase
end
always@(idx__h21626 or
tlp_tlpBRAM_writeRemainDWLen or
NOT_tlp_tlpBRAM_writeRemainDWLen_52_ULE_1_55___d656 or
NOT_tlp_tlpBRAM_writeRemainDWLen_52_ULE_2_57___d658 or
NOT_tlp_tlpBRAM_writeRemainDWLen_52_ULE_3_59___d660)
begin
case (idx__h21626)
2'd0:
SEL_ARR_NOT_tlp_tlpBRAM_writeRemainDWLen_52_EQ_ETC___d665 =
tlp_tlpBRAM_writeRemainDWLen != 10'd0;
2'd1:
SEL_ARR_NOT_tlp_tlpBRAM_writeRemainDWLen_52_EQ_ETC___d665 =
NOT_tlp_tlpBRAM_writeRemainDWLen_52_ULE_1_55___d656;
2'd2:
SEL_ARR_NOT_tlp_tlpBRAM_writeRemainDWLen_52_EQ_ETC___d665 =
NOT_tlp_tlpBRAM_writeRemainDWLen_52_ULE_2_57___d658;
2'd3:
SEL_ARR_NOT_tlp_tlpBRAM_writeRemainDWLen_52_EQ_ETC___d665 =
NOT_tlp_tlpBRAM_writeRemainDWLen_52_ULE_3_59___d660;
endcase
end
always@(idx__h23676 or
tlp_tlpBRAM_writeRemainDWLen or
NOT_tlp_tlpBRAM_writeRemainDWLen_52_ULE_1_55___d656 or
NOT_tlp_tlpBRAM_writeRemainDWLen_52_ULE_2_57___d658 or
NOT_tlp_tlpBRAM_writeRemainDWLen_52_ULE_3_59___d660)
begin
case (idx__h23676)
2'd0:
SEL_ARR_NOT_tlp_tlpBRAM_writeRemainDWLen_52_EQ_ETC___d669 =
tlp_tlpBRAM_writeRemainDWLen != 10'd0;
2'd1:
SEL_ARR_NOT_tlp_tlpBRAM_writeRemainDWLen_52_EQ_ETC___d669 =
NOT_tlp_tlpBRAM_writeRemainDWLen_52_ULE_1_55___d656;
2'd2:
SEL_ARR_NOT_tlp_tlpBRAM_writeRemainDWLen_52_EQ_ETC___d669 =
NOT_tlp_tlpBRAM_writeRemainDWLen_52_ULE_2_57___d658;
2'd3:
SEL_ARR_NOT_tlp_tlpBRAM_writeRemainDWLen_52_EQ_ETC___d669 =
NOT_tlp_tlpBRAM_writeRemainDWLen_52_ULE_3_59___d660;
endcase
end
always@(idx__h24781 or
tlp_tlpBRAM_writeRemainDWLen or
NOT_tlp_tlpBRAM_writeRemainDWLen_52_ULE_1_55___d656 or
NOT_tlp_tlpBRAM_writeRemainDWLen_52_ULE_2_57___d658 or
NOT_tlp_tlpBRAM_writeRemainDWLen_52_ULE_3_59___d660)
begin
case (idx__h24781)
2'd0:
SEL_ARR_NOT_tlp_tlpBRAM_writeRemainDWLen_52_EQ_ETC___d673 =
tlp_tlpBRAM_writeRemainDWLen != 10'd0;
2'd1:
SEL_ARR_NOT_tlp_tlpBRAM_writeRemainDWLen_52_EQ_ETC___d673 =
NOT_tlp_tlpBRAM_writeRemainDWLen_52_ULE_1_55___d656;
2'd2:
SEL_ARR_NOT_tlp_tlpBRAM_writeRemainDWLen_52_EQ_ETC___d673 =
NOT_tlp_tlpBRAM_writeRemainDWLen_52_ULE_2_57___d658;
2'd3:
SEL_ARR_NOT_tlp_tlpBRAM_writeRemainDWLen_52_EQ_ETC___d673 =
NOT_tlp_tlpBRAM_writeRemainDWLen_52_ULE_3_59___d660;
endcase
end
always@(idx__h25886 or
tlp_tlpBRAM_writeRemainDWLen or
NOT_tlp_tlpBRAM_writeRemainDWLen_52_ULE_1_55___d656 or
NOT_tlp_tlpBRAM_writeRemainDWLen_52_ULE_2_57___d658 or
NOT_tlp_tlpBRAM_writeRemainDWLen_52_ULE_3_59___d660)
begin
case (idx__h25886)
2'd0:
SEL_ARR_NOT_tlp_tlpBRAM_writeRemainDWLen_52_EQ_ETC___d677 =
tlp_tlpBRAM_writeRemainDWLen != 10'd0;
2'd1:
SEL_ARR_NOT_tlp_tlpBRAM_writeRemainDWLen_52_EQ_ETC___d677 =
NOT_tlp_tlpBRAM_writeRemainDWLen_52_ULE_1_55___d656;
2'd2:
SEL_ARR_NOT_tlp_tlpBRAM_writeRemainDWLen_52_EQ_ETC___d677 =
NOT_tlp_tlpBRAM_writeRemainDWLen_52_ULE_2_57___d658;
2'd3:
SEL_ARR_NOT_tlp_tlpBRAM_writeRemainDWLen_52_EQ_ETC___d677 =
NOT_tlp_tlpBRAM_writeRemainDWLen_52_ULE_3_59___d660;
endcase
end
always@(idx__h21626 or tlp_tlpBRAM_mReqF_D_OUT)
begin
case (idx__h21626)
2'd0:
SEL_ARR_tlp_tlpBRAM_mReqF_first__16_BITS_127_T_ETC___d700 =
tlp_tlpBRAM_mReqF_D_OUT[127:96];
2'd1:
SEL_ARR_tlp_tlpBRAM_mReqF_first__16_BITS_127_T_ETC___d700 =
tlp_tlpBRAM_mReqF_D_OUT[95:64];
2'd2:
SEL_ARR_tlp_tlpBRAM_mReqF_first__16_BITS_127_T_ETC___d700 =
tlp_tlpBRAM_mReqF_D_OUT[63:32];
2'd3:
SEL_ARR_tlp_tlpBRAM_mReqF_first__16_BITS_127_T_ETC___d700 =
tlp_tlpBRAM_mReqF_D_OUT[31:0];
endcase
end
always@(idx__h23676 or tlp_tlpBRAM_mReqF_D_OUT)
begin
case (idx__h23676)
2'd0:
SEL_ARR_tlp_tlpBRAM_mReqF_first__16_BITS_127_T_ETC___d708 =
tlp_tlpBRAM_mReqF_D_OUT[127:96];
2'd1:
SEL_ARR_tlp_tlpBRAM_mReqF_first__16_BITS_127_T_ETC___d708 =
tlp_tlpBRAM_mReqF_D_OUT[95:64];
2'd2:
SEL_ARR_tlp_tlpBRAM_mReqF_first__16_BITS_127_T_ETC___d708 =
tlp_tlpBRAM_mReqF_D_OUT[63:32];
2'd3:
SEL_ARR_tlp_tlpBRAM_mReqF_first__16_BITS_127_T_ETC___d708 =
tlp_tlpBRAM_mReqF_D_OUT[31:0];
endcase
end
always@(idx__h24781 or tlp_tlpBRAM_mReqF_D_OUT)
begin
case (idx__h24781)
2'd0:
SEL_ARR_tlp_tlpBRAM_mReqF_first__16_BITS_127_T_ETC___d716 =
tlp_tlpBRAM_mReqF_D_OUT[127:96];
2'd1:
SEL_ARR_tlp_tlpBRAM_mReqF_first__16_BITS_127_T_ETC___d716 =
tlp_tlpBRAM_mReqF_D_OUT[95:64];
2'd2:
SEL_ARR_tlp_tlpBRAM_mReqF_first__16_BITS_127_T_ETC___d716 =
tlp_tlpBRAM_mReqF_D_OUT[63:32];
2'd3:
SEL_ARR_tlp_tlpBRAM_mReqF_first__16_BITS_127_T_ETC___d716 =
tlp_tlpBRAM_mReqF_D_OUT[31:0];
endcase
end
always@(idx__h25886 or tlp_tlpBRAM_mReqF_D_OUT)
begin
case (idx__h25886)
2'd0:
SEL_ARR_tlp_tlpBRAM_mReqF_first__16_BITS_127_T_ETC___d724 =
tlp_tlpBRAM_mReqF_D_OUT[127:96];
2'd1:
SEL_ARR_tlp_tlpBRAM_mReqF_first__16_BITS_127_T_ETC___d724 =
tlp_tlpBRAM_mReqF_D_OUT[95:64];
2'd2:
SEL_ARR_tlp_tlpBRAM_mReqF_first__16_BITS_127_T_ETC___d724 =
tlp_tlpBRAM_mReqF_D_OUT[63:32];
2'd3:
SEL_ARR_tlp_tlpBRAM_mReqF_first__16_BITS_127_T_ETC___d724 =
tlp_tlpBRAM_mReqF_D_OUT[31:0];
endcase
end
always@(tlp_tlpBRAM_mReqF_D_OUT or
bram_0_serverAdapterA_cnt_6_SLT_3___d619 or
bram_1_serverAdapterA_cnt_44_SLT_3___d620 or
bram_2_serverAdapterA_cnt_62_SLT_3___d621 or
bram_3_serverAdapterA_cnt_80_SLT_3___d622)
begin
case (tlp_tlpBRAM_mReqF_D_OUT[30:29])
2'd0:
CASE_tlp_tlpBRAM_mReqF_first__16_BITS_30_TO_29_ETC___d736 =
bram_0_serverAdapterA_cnt_6_SLT_3___d619;
2'd1:
CASE_tlp_tlpBRAM_mReqF_first__16_BITS_30_TO_29_ETC___d736 =
bram_1_serverAdapterA_cnt_44_SLT_3___d620;
2'd2:
CASE_tlp_tlpBRAM_mReqF_first__16_BITS_30_TO_29_ETC___d736 =
bram_2_serverAdapterA_cnt_62_SLT_3___d621;
2'd3:
CASE_tlp_tlpBRAM_mReqF_first__16_BITS_30_TO_29_ETC___d736 =
bram_3_serverAdapterA_cnt_80_SLT_3___d622;
endcase
end
always@(tlp_outDwRemain)
begin
case (tlp_outDwRemain[1:0])
2'b0: CASE_tlp_outDwRemain_BITS_1_TO_0_0b0_0xFFFF_0b_ETC__q3 = 16'hFFFF;
2'b01:
CASE_tlp_outDwRemain_BITS_1_TO_0_0b0_0xFFFF_0b_ETC__q3 = 16'hF000;
2'b10:
CASE_tlp_outDwRemain_BITS_1_TO_0_0b0_0xFFFF_0b_ETC__q3 = 16'hFF00;
2'd3: CASE_tlp_outDwRemain_BITS_1_TO_0_0b0_0xFFFF_0b_ETC__q3 = 16'hFFF0;
endcase
end
always@(dpControl or bml_fabDone or bml_remDone)
begin
case (dpControl[1:0])
2'd0:
CASE_dpControl_BITS_1_TO_0_0_bml_fabDone_1_bml_ETC__q4 =
bml_fabDone;
2'd1:
CASE_dpControl_BITS_1_TO_0_0_bml_fabDone_1_bml_ETC__q4 =
bml_remDone;
default: CASE_dpControl_BITS_1_TO_0_0_bml_fabDone_1_bml_ETC__q4 =
bml_fabDone;
endcase
end
always@(dpControl or bml_fabDone or bml_remDone)
begin
case (dpControl[1:0])
2'd0:
CASE_dpControl_BITS_1_TO_0_0_NOT_bml_fabDone_1_ETC__q5 =
!bml_fabDone;
2'd1:
CASE_dpControl_BITS_1_TO_0_0_NOT_bml_fabDone_1_ETC__q5 =
!bml_remDone;
default: CASE_dpControl_BITS_1_TO_0_0_NOT_bml_fabDone_1_ETC__q5 =
!bml_fabDone;
endcase
end
always@(dpControl or
bml_fabDone or
IF_bml_dpControl_wget__898_BITS_3_TO_2_899_EQ__ETC___d1995)
begin
case (dpControl[1:0])
2'd0:
CASE_dpControl_BITS_1_TO_0_0_NOT_bml_fabDone_1_ETC__q6 =
!bml_fabDone;
2'd1:
CASE_dpControl_BITS_1_TO_0_0_NOT_bml_fabDone_1_ETC__q6 =
IF_bml_dpControl_wget__898_BITS_3_TO_2_899_EQ__ETC___d1995;
default: CASE_dpControl_BITS_1_TO_0_0_NOT_bml_fabDone_1_ETC__q6 =
!bml_fabDone;
endcase
end
always@(dpControl or bml_fabDone or bml_remDone or bml_remStart)
begin
case (dpControl[1:0])
2'd0:
CASE_dpControl_BITS_1_TO_0_0_bml_fabDone_1_IF__ETC__q7 =
bml_fabDone;
2'd1:
CASE_dpControl_BITS_1_TO_0_0_bml_fabDone_1_IF__ETC__q7 =
(dpControl[3:2] == 2'd1) ? bml_remDone : bml_remStart;
default: CASE_dpControl_BITS_1_TO_0_0_bml_fabDone_1_IF__ETC__q7 =
bml_fabDone;
endcase
end
always@(tlp_tlpBRAM_readReq_D_OUT or
bram_0_serverAdapterA_outDataCore_EMPTY_N or
bram_0_serverAdapterA_outData_enqData_whas or
bram_1_serverAdapterA_outDataCore_EMPTY_N or
bram_1_serverAdapterA_outData_enqData_whas or
bram_2_serverAdapterA_outDataCore_EMPTY_N or
bram_2_serverAdapterA_outData_enqData_whas or
bram_3_serverAdapterA_outDataCore_EMPTY_N or
bram_3_serverAdapterA_outData_enqData_whas)
begin
case (tlp_tlpBRAM_readReq_D_OUT[30:29])
2'd0:
CASE_tlp_tlpBRAM_readReq_first__98_BITS_30_TO__ETC___d805 =
bram_0_serverAdapterA_outDataCore_EMPTY_N ||
bram_0_serverAdapterA_outData_enqData_whas;
2'd1:
CASE_tlp_tlpBRAM_readReq_first__98_BITS_30_TO__ETC___d805 =
bram_1_serverAdapterA_outDataCore_EMPTY_N ||
bram_1_serverAdapterA_outData_enqData_whas;
2'd2:
CASE_tlp_tlpBRAM_readReq_first__98_BITS_30_TO__ETC___d805 =
bram_2_serverAdapterA_outDataCore_EMPTY_N ||
bram_2_serverAdapterA_outData_enqData_whas;
2'd3:
CASE_tlp_tlpBRAM_readReq_first__98_BITS_30_TO__ETC___d805 =
bram_3_serverAdapterA_outDataCore_EMPTY_N ||
bram_3_serverAdapterA_outData_enqData_whas;
endcase
end
always@(tlp_tlpBRAM_readReq_D_OUT or
bram_0_serverAdapterA_outData_outData_wget or
bram_1_serverAdapterA_outData_outData_wget or
bram_2_serverAdapterA_outData_outData_wget or
bram_3_serverAdapterA_outData_outData_wget)
begin
case (tlp_tlpBRAM_readReq_D_OUT[30:29])
2'd0:
SEL_ARR_bram_0_serverAdapterA_outData_outData__ETC___d863 =
bram_0_serverAdapterA_outData_outData_wget;
2'd1:
SEL_ARR_bram_0_serverAdapterA_outData_outData__ETC___d863 =
bram_1_serverAdapterA_outData_outData_wget;
2'd2:
SEL_ARR_bram_0_serverAdapterA_outData_outData__ETC___d863 =
bram_2_serverAdapterA_outData_outData_wget;
2'd3:
SEL_ARR_bram_0_serverAdapterA_outData_outData__ETC___d863 =
bram_3_serverAdapterA_outData_outData_wget;
endcase
end
always@(tlp_tlpBRAM_readReq_D_OUT or
bram_0_serverAdapterA_outData_outData_whas or
bram_1_serverAdapterA_outData_outData_whas or
bram_2_serverAdapterA_outData_outData_whas or
bram_3_serverAdapterA_outData_outData_whas)
begin
case (tlp_tlpBRAM_readReq_D_OUT[30:29])
2'd0:
CASE_tlp_tlpBRAM_readReq_first__98_BITS_30_TO__ETC___d810 =
bram_0_serverAdapterA_outData_outData_whas;
2'd1:
CASE_tlp_tlpBRAM_readReq_first__98_BITS_30_TO__ETC___d810 =
bram_1_serverAdapterA_outData_outData_whas;
2'd2:
CASE_tlp_tlpBRAM_readReq_first__98_BITS_30_TO__ETC___d810 =
bram_2_serverAdapterA_outData_outData_whas;
2'd3:
CASE_tlp_tlpBRAM_readReq_first__98_BITS_30_TO__ETC___d810 =
bram_3_serverAdapterA_outData_outData_whas;
endcase
end
// handling of inlined registers
always@(posedge CLK)
begin
if (RST_N == `BSV_RESET_VALUE)
begin
bml_crdBuf_modulus <= `BSV_ASSIGNMENT_DELAY 16'd65535;
bml_crdBuf_value <= `BSV_ASSIGNMENT_DELAY 16'd0;
bml_datumAReg <= `BSV_ASSIGNMENT_DELAY 1'd0;
bml_fabAvail <= `BSV_ASSIGNMENT_DELAY 1'd0;
bml_fabBuf_modulus <= `BSV_ASSIGNMENT_DELAY 16'd65535;
bml_fabBuf_value <= `BSV_ASSIGNMENT_DELAY 16'd0;
bml_fabDone <= `BSV_ASSIGNMENT_DELAY 1'd0;
bml_fabFlowBase <= `BSV_ASSIGNMENT_DELAY 32'hFFFF0018;
bml_fabFlowBaseMS <= `BSV_ASSIGNMENT_DELAY 32'h0;
bml_fabFlowSize <= `BSV_ASSIGNMENT_DELAY 32'h00000004;
bml_fabMesgBase <= `BSV_ASSIGNMENT_DELAY 32'hFFFF0000;
bml_fabMesgBaseMS <= `BSV_ASSIGNMENT_DELAY 32'h0;
bml_fabMesgSize <= `BSV_ASSIGNMENT_DELAY 32'h00000800;
bml_fabMetaBase <= `BSV_ASSIGNMENT_DELAY 32'hFFFF3800;
bml_fabMetaBaseMS <= `BSV_ASSIGNMENT_DELAY 32'h0;
bml_fabMetaSize <= `BSV_ASSIGNMENT_DELAY 32'h00000010;
bml_fabNumBufs <= `BSV_ASSIGNMENT_DELAY 16'd1;
bml_lclBufDone <= `BSV_ASSIGNMENT_DELAY 1'd0;
bml_lclBufStart <= `BSV_ASSIGNMENT_DELAY 1'd0;
bml_lclBuf_modulus <= `BSV_ASSIGNMENT_DELAY 16'd65535;
bml_lclBuf_value <= `BSV_ASSIGNMENT_DELAY 16'd0;
bml_lclDones <= `BSV_ASSIGNMENT_DELAY 16'd0;
bml_lclNumBufs <= `BSV_ASSIGNMENT_DELAY 16'd1;
bml_lclStarts <= `BSV_ASSIGNMENT_DELAY 16'd0;
bml_mesgBase <= `BSV_ASSIGNMENT_DELAY 16'h0;
bml_mesgSize <= `BSV_ASSIGNMENT_DELAY 16'h0800;
bml_metaBase <= `BSV_ASSIGNMENT_DELAY 16'h3800;
bml_metaSize <= `BSV_ASSIGNMENT_DELAY 16'h0010;
bml_remBuf_modulus <= `BSV_ASSIGNMENT_DELAY 16'd65535;
bml_remBuf_value <= `BSV_ASSIGNMENT_DELAY 16'd0;
bml_remDone <= `BSV_ASSIGNMENT_DELAY 1'd0;
bml_remDones <= `BSV_ASSIGNMENT_DELAY 16'd0;
bml_remStart <= `BSV_ASSIGNMENT_DELAY 1'd0;
bml_remStarts <= `BSV_ASSIGNMENT_DELAY 16'd0;
bram_0_serverAdapterA_cnt <= `BSV_ASSIGNMENT_DELAY 3'd0;
bram_0_serverAdapterA_s1 <= `BSV_ASSIGNMENT_DELAY 2'd0;
bram_0_serverAdapterB_cnt <= `BSV_ASSIGNMENT_DELAY 3'd0;
bram_0_serverAdapterB_s1 <= `BSV_ASSIGNMENT_DELAY 2'd0;
bram_1_serverAdapterA_cnt <= `BSV_ASSIGNMENT_DELAY 3'd0;
bram_1_serverAdapterA_s1 <= `BSV_ASSIGNMENT_DELAY 2'd0;
bram_1_serverAdapterB_cnt <= `BSV_ASSIGNMENT_DELAY 3'd0;
bram_1_serverAdapterB_s1 <= `BSV_ASSIGNMENT_DELAY 2'd0;
bram_2_serverAdapterA_cnt <= `BSV_ASSIGNMENT_DELAY 3'd0;
bram_2_serverAdapterA_s1 <= `BSV_ASSIGNMENT_DELAY 2'd0;
bram_2_serverAdapterB_cnt <= `BSV_ASSIGNMENT_DELAY 3'd0;
bram_2_serverAdapterB_s1 <= `BSV_ASSIGNMENT_DELAY 2'd0;
bram_3_serverAdapterA_cnt <= `BSV_ASSIGNMENT_DELAY 3'd0;
bram_3_serverAdapterA_s1 <= `BSV_ASSIGNMENT_DELAY 2'd0;
bram_3_serverAdapterB_cnt <= `BSV_ASSIGNMENT_DELAY 3'd0;
bram_3_serverAdapterB_s1 <= `BSV_ASSIGNMENT_DELAY 2'd0;
dmaDoneTime <= `BSV_ASSIGNMENT_DELAY 64'd0;
dmaStartTime <= `BSV_ASSIGNMENT_DELAY 64'd0;
dpControl <= `BSV_ASSIGNMENT_DELAY 8'd0;
tlp_complTimerCount <= `BSV_ASSIGNMENT_DELAY 12'd0;
tlp_complTimerRunning <= `BSV_ASSIGNMENT_DELAY 1'd0;
tlp_creditReady <= `BSV_ASSIGNMENT_DELAY 1'd0;
tlp_dmaDoTailEvent <= `BSV_ASSIGNMENT_DELAY 1'd0;
tlp_dmaDoneMark <= `BSV_ASSIGNMENT_DELAY 1'd0;
tlp_dmaStartMark <= `BSV_ASSIGNMENT_DELAY 1'd0;
tlp_dmaTag <= `BSV_ASSIGNMENT_DELAY 5'd0;
tlp_doXmtMetaBody <= `BSV_ASSIGNMENT_DELAY 1'd0;
tlp_doorSeqDwell <= `BSV_ASSIGNMENT_DELAY 4'd0;
tlp_fabMeta <= `BSV_ASSIGNMENT_DELAY
129'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
tlp_farBufReady <= `BSV_ASSIGNMENT_DELAY 1'd0;
tlp_flowDiagCount <= `BSV_ASSIGNMENT_DELAY 32'd0;
tlp_gotResponseHeader <= `BSV_ASSIGNMENT_DELAY 1'd0;
tlp_lastMetaV_0 <= `BSV_ASSIGNMENT_DELAY 32'd0;
tlp_lastMetaV_1 <= `BSV_ASSIGNMENT_DELAY 32'd0;
tlp_lastMetaV_2 <= `BSV_ASSIGNMENT_DELAY 32'd0;
tlp_lastMetaV_3 <= `BSV_ASSIGNMENT_DELAY 32'd0;
tlp_lastRuleFired <= `BSV_ASSIGNMENT_DELAY 4'd15;
tlp_maxPayloadSize <= `BSV_ASSIGNMENT_DELAY 13'd128;
tlp_maxReadReqSize <= `BSV_ASSIGNMENT_DELAY 13'd4096;
tlp_nearBufReady <= `BSV_ASSIGNMENT_DELAY 1'd0;
tlp_postSeqDwell <= `BSV_ASSIGNMENT_DELAY 4'd0;
tlp_pullTagMatch <= `BSV_ASSIGNMENT_DELAY 1'd0;
tlp_remDone <= `BSV_ASSIGNMENT_DELAY 1'd0;
tlp_remStart <= `BSV_ASSIGNMENT_DELAY 1'd0;
tlp_reqMesgInFlight <= `BSV_ASSIGNMENT_DELAY 1'd0;
tlp_reqMetaBodyInFlight <= `BSV_ASSIGNMENT_DELAY 1'd0;
tlp_reqMetaInFlight <= `BSV_ASSIGNMENT_DELAY 1'd0;
tlp_sentTail4DWHeader <= `BSV_ASSIGNMENT_DELAY 1'd0;
tlp_tlpBRAM_debugBdata <= `BSV_ASSIGNMENT_DELAY 128'd0;
tlp_tlpBRAM_readHeaderSent <= `BSV_ASSIGNMENT_DELAY 1'd0;
tlp_tlpBRAM_readStarted <= `BSV_ASSIGNMENT_DELAY 1'd0;
tlp_tlpMetaSent <= `BSV_ASSIGNMENT_DELAY 1'd0;
tlp_tlpRcvBusy <= `BSV_ASSIGNMENT_DELAY 1'd0;
tlp_tlpXmtBusy <= `BSV_ASSIGNMENT_DELAY 1'd0;
tlp_xmtMetaInFlight <= `BSV_ASSIGNMENT_DELAY 1'd0;
tlp_xmtMetaOK <= `BSV_ASSIGNMENT_DELAY 1'd0;
wci_cEdge <= `BSV_ASSIGNMENT_DELAY 3'h2;
wci_cState <= `BSV_ASSIGNMENT_DELAY 3'd0;
wci_ctlAckReg <= `BSV_ASSIGNMENT_DELAY 1'd0;
wci_ctlOpActive <= `BSV_ASSIGNMENT_DELAY 1'd0;
wci_illegalEdge <= `BSV_ASSIGNMENT_DELAY 1'd0;
wci_nState <= `BSV_ASSIGNMENT_DELAY 3'd0;
wci_reqF_countReg <= `BSV_ASSIGNMENT_DELAY 2'd0;
wci_respF_cntr_r <= `BSV_ASSIGNMENT_DELAY 2'd0;
wci_respF_q_0 <= `BSV_ASSIGNMENT_DELAY 34'h0AAAAAAAA;
wci_respF_q_1 <= `BSV_ASSIGNMENT_DELAY 34'h0AAAAAAAA;
wci_sFlagReg <= `BSV_ASSIGNMENT_DELAY 1'd0;
wci_sThreadBusy_d <= `BSV_ASSIGNMENT_DELAY 1'd1;
wmi_bufDwell <= `BSV_ASSIGNMENT_DELAY 2'd0;
wmi_bytesRemainResp <= `BSV_ASSIGNMENT_DELAY 14'd0;
wmi_doneWithMesg <= `BSV_ASSIGNMENT_DELAY 1'd0;
wmi_lastMesg <= `BSV_ASSIGNMENT_DELAY 32'hFEFEFFFE;
wmi_mesgBufReady <= `BSV_ASSIGNMENT_DELAY 1'd0;
wmi_mesgBusy <= `BSV_ASSIGNMENT_DELAY 1'd0;
wmi_mesgCount <= `BSV_ASSIGNMENT_DELAY 32'd0;
wmi_mesgDone <= `BSV_ASSIGNMENT_DELAY 1'd0;
wmi_mesgMeta <= `BSV_ASSIGNMENT_DELAY
129'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
wmi_mesgStart <= `BSV_ASSIGNMENT_DELAY 1'd0;
wmi_metaBusy <= `BSV_ASSIGNMENT_DELAY 1'd0;
wmi_p4B <= `BSV_ASSIGNMENT_DELAY 2'd0;
wmi_rdActive <= `BSV_ASSIGNMENT_DELAY 1'd0;
wmi_reqCount <= `BSV_ASSIGNMENT_DELAY 16'd0;
wmi_thisMesg <= `BSV_ASSIGNMENT_DELAY 32'hFEFEFFFE;
wmi_wmi_blockReq <= `BSV_ASSIGNMENT_DELAY 1'd0;
wmi_wmi_dhF_countReg <= `BSV_ASSIGNMENT_DELAY 2'd0;
wmi_wmi_dhF_levelsValid <= `BSV_ASSIGNMENT_DELAY 1'd1;
wmi_wmi_errorSticky <= `BSV_ASSIGNMENT_DELAY 1'd0;
wmi_wmi_mFlagF_countReg <= `BSV_ASSIGNMENT_DELAY 2'd0;
wmi_wmi_mFlagF_levelsValid <= `BSV_ASSIGNMENT_DELAY 1'd1;
wmi_wmi_operateD <= `BSV_ASSIGNMENT_DELAY 1'd0;
wmi_wmi_peerIsReady <= `BSV_ASSIGNMENT_DELAY 1'd0;
wmi_wmi_reqF_countReg <= `BSV_ASSIGNMENT_DELAY 2'd0;
wmi_wmi_reqF_levelsValid <= `BSV_ASSIGNMENT_DELAY 1'd1;
wmi_wmi_respF_cntr_r <= `BSV_ASSIGNMENT_DELAY 2'd0;
wmi_wmi_respF_q_0 <= `BSV_ASSIGNMENT_DELAY 130'd0;
wmi_wmi_respF_q_1 <= `BSV_ASSIGNMENT_DELAY 130'd0;
wmi_wmi_sFlagReg <= `BSV_ASSIGNMENT_DELAY 32'd0;
wmi_wmi_trafficSticky <= `BSV_ASSIGNMENT_DELAY 1'd0;
wmi_wrActive <= `BSV_ASSIGNMENT_DELAY 1'd0;
wmi_wrFinalize <= `BSV_ASSIGNMENT_DELAY 1'd0;
wmi_wrtCount <= `BSV_ASSIGNMENT_DELAY 16'd0;
wti_nowReq <= `BSV_ASSIGNMENT_DELAY 67'd0;
wti_operateD <= `BSV_ASSIGNMENT_DELAY 1'd1;
end
else
begin
if (bml_crdBuf_modulus_EN)
bml_crdBuf_modulus <= `BSV_ASSIGNMENT_DELAY bml_crdBuf_modulus_D_IN;
if (bml_crdBuf_value_EN)
bml_crdBuf_value <= `BSV_ASSIGNMENT_DELAY bml_crdBuf_value_D_IN;
if (bml_datumAReg_EN)
bml_datumAReg <= `BSV_ASSIGNMENT_DELAY bml_datumAReg_D_IN;
if (bml_fabAvail_EN)
bml_fabAvail <= `BSV_ASSIGNMENT_DELAY bml_fabAvail_D_IN;
if (bml_fabBuf_modulus_EN)
bml_fabBuf_modulus <= `BSV_ASSIGNMENT_DELAY bml_fabBuf_modulus_D_IN;
if (bml_fabBuf_value_EN)
bml_fabBuf_value <= `BSV_ASSIGNMENT_DELAY bml_fabBuf_value_D_IN;
if (bml_fabDone_EN)
bml_fabDone <= `BSV_ASSIGNMENT_DELAY bml_fabDone_D_IN;
if (bml_fabFlowBase_EN)
bml_fabFlowBase <= `BSV_ASSIGNMENT_DELAY bml_fabFlowBase_D_IN;
if (bml_fabFlowBaseMS_EN)
bml_fabFlowBaseMS <= `BSV_ASSIGNMENT_DELAY bml_fabFlowBaseMS_D_IN;
if (bml_fabFlowSize_EN)
bml_fabFlowSize <= `BSV_ASSIGNMENT_DELAY bml_fabFlowSize_D_IN;
if (bml_fabMesgBase_EN)
bml_fabMesgBase <= `BSV_ASSIGNMENT_DELAY bml_fabMesgBase_D_IN;
if (bml_fabMesgBaseMS_EN)
bml_fabMesgBaseMS <= `BSV_ASSIGNMENT_DELAY bml_fabMesgBaseMS_D_IN;
if (bml_fabMesgSize_EN)
bml_fabMesgSize <= `BSV_ASSIGNMENT_DELAY bml_fabMesgSize_D_IN;
if (bml_fabMetaBase_EN)
bml_fabMetaBase <= `BSV_ASSIGNMENT_DELAY bml_fabMetaBase_D_IN;
if (bml_fabMetaBaseMS_EN)
bml_fabMetaBaseMS <= `BSV_ASSIGNMENT_DELAY bml_fabMetaBaseMS_D_IN;
if (bml_fabMetaSize_EN)
bml_fabMetaSize <= `BSV_ASSIGNMENT_DELAY bml_fabMetaSize_D_IN;
if (bml_fabNumBufs_EN)
bml_fabNumBufs <= `BSV_ASSIGNMENT_DELAY bml_fabNumBufs_D_IN;
if (bml_lclBufDone_EN)
bml_lclBufDone <= `BSV_ASSIGNMENT_DELAY bml_lclBufDone_D_IN;
if (bml_lclBufStart_EN)
bml_lclBufStart <= `BSV_ASSIGNMENT_DELAY bml_lclBufStart_D_IN;
if (bml_lclBuf_modulus_EN)
bml_lclBuf_modulus <= `BSV_ASSIGNMENT_DELAY bml_lclBuf_modulus_D_IN;
if (bml_lclBuf_value_EN)
bml_lclBuf_value <= `BSV_ASSIGNMENT_DELAY bml_lclBuf_value_D_IN;
if (bml_lclDones_EN)
bml_lclDones <= `BSV_ASSIGNMENT_DELAY bml_lclDones_D_IN;
if (bml_lclNumBufs_EN)
bml_lclNumBufs <= `BSV_ASSIGNMENT_DELAY bml_lclNumBufs_D_IN;
if (bml_lclStarts_EN)
bml_lclStarts <= `BSV_ASSIGNMENT_DELAY bml_lclStarts_D_IN;
if (bml_mesgBase_EN)
bml_mesgBase <= `BSV_ASSIGNMENT_DELAY bml_mesgBase_D_IN;
if (bml_mesgSize_EN)
bml_mesgSize <= `BSV_ASSIGNMENT_DELAY bml_mesgSize_D_IN;
if (bml_metaBase_EN)
bml_metaBase <= `BSV_ASSIGNMENT_DELAY bml_metaBase_D_IN;
if (bml_metaSize_EN)
bml_metaSize <= `BSV_ASSIGNMENT_DELAY bml_metaSize_D_IN;
if (bml_remBuf_modulus_EN)
bml_remBuf_modulus <= `BSV_ASSIGNMENT_DELAY bml_remBuf_modulus_D_IN;
if (bml_remBuf_value_EN)
bml_remBuf_value <= `BSV_ASSIGNMENT_DELAY bml_remBuf_value_D_IN;
if (bml_remDone_EN)
bml_remDone <= `BSV_ASSIGNMENT_DELAY bml_remDone_D_IN;
if (bml_remDones_EN)
bml_remDones <= `BSV_ASSIGNMENT_DELAY bml_remDones_D_IN;
if (bml_remStart_EN)
bml_remStart <= `BSV_ASSIGNMENT_DELAY bml_remStart_D_IN;
if (bml_remStarts_EN)
bml_remStarts <= `BSV_ASSIGNMENT_DELAY bml_remStarts_D_IN;
if (bram_0_serverAdapterA_cnt_EN)
bram_0_serverAdapterA_cnt <= `BSV_ASSIGNMENT_DELAY
bram_0_serverAdapterA_cnt_D_IN;
if (bram_0_serverAdapterA_s1_EN)
bram_0_serverAdapterA_s1 <= `BSV_ASSIGNMENT_DELAY
bram_0_serverAdapterA_s1_D_IN;
if (bram_0_serverAdapterB_cnt_EN)
bram_0_serverAdapterB_cnt <= `BSV_ASSIGNMENT_DELAY
bram_0_serverAdapterB_cnt_D_IN;
if (bram_0_serverAdapterB_s1_EN)
bram_0_serverAdapterB_s1 <= `BSV_ASSIGNMENT_DELAY
bram_0_serverAdapterB_s1_D_IN;
if (bram_1_serverAdapterA_cnt_EN)
bram_1_serverAdapterA_cnt <= `BSV_ASSIGNMENT_DELAY
bram_1_serverAdapterA_cnt_D_IN;
if (bram_1_serverAdapterA_s1_EN)
bram_1_serverAdapterA_s1 <= `BSV_ASSIGNMENT_DELAY
bram_1_serverAdapterA_s1_D_IN;
if (bram_1_serverAdapterB_cnt_EN)
bram_1_serverAdapterB_cnt <= `BSV_ASSIGNMENT_DELAY
bram_1_serverAdapterB_cnt_D_IN;
if (bram_1_serverAdapterB_s1_EN)
bram_1_serverAdapterB_s1 <= `BSV_ASSIGNMENT_DELAY
bram_1_serverAdapterB_s1_D_IN;
if (bram_2_serverAdapterA_cnt_EN)
bram_2_serverAdapterA_cnt <= `BSV_ASSIGNMENT_DELAY
bram_2_serverAdapterA_cnt_D_IN;
if (bram_2_serverAdapterA_s1_EN)
bram_2_serverAdapterA_s1 <= `BSV_ASSIGNMENT_DELAY
bram_2_serverAdapterA_s1_D_IN;
if (bram_2_serverAdapterB_cnt_EN)
bram_2_serverAdapterB_cnt <= `BSV_ASSIGNMENT_DELAY
bram_2_serverAdapterB_cnt_D_IN;
if (bram_2_serverAdapterB_s1_EN)
bram_2_serverAdapterB_s1 <= `BSV_ASSIGNMENT_DELAY
bram_2_serverAdapterB_s1_D_IN;
if (bram_3_serverAdapterA_cnt_EN)
bram_3_serverAdapterA_cnt <= `BSV_ASSIGNMENT_DELAY
bram_3_serverAdapterA_cnt_D_IN;
if (bram_3_serverAdapterA_s1_EN)
bram_3_serverAdapterA_s1 <= `BSV_ASSIGNMENT_DELAY
bram_3_serverAdapterA_s1_D_IN;
if (bram_3_serverAdapterB_cnt_EN)
bram_3_serverAdapterB_cnt <= `BSV_ASSIGNMENT_DELAY
bram_3_serverAdapterB_cnt_D_IN;
if (bram_3_serverAdapterB_s1_EN)
bram_3_serverAdapterB_s1 <= `BSV_ASSIGNMENT_DELAY
bram_3_serverAdapterB_s1_D_IN;
if (dmaDoneTime_EN)
dmaDoneTime <= `BSV_ASSIGNMENT_DELAY dmaDoneTime_D_IN;
if (dmaStartTime_EN)
dmaStartTime <= `BSV_ASSIGNMENT_DELAY dmaStartTime_D_IN;
if (dpControl_EN) dpControl <= `BSV_ASSIGNMENT_DELAY dpControl_D_IN;
if (tlp_complTimerCount_EN)
tlp_complTimerCount <= `BSV_ASSIGNMENT_DELAY
tlp_complTimerCount_D_IN;
if (tlp_complTimerRunning_EN)
tlp_complTimerRunning <= `BSV_ASSIGNMENT_DELAY
tlp_complTimerRunning_D_IN;
if (tlp_creditReady_EN)
tlp_creditReady <= `BSV_ASSIGNMENT_DELAY tlp_creditReady_D_IN;
if (tlp_dmaDoTailEvent_EN)
tlp_dmaDoTailEvent <= `BSV_ASSIGNMENT_DELAY tlp_dmaDoTailEvent_D_IN;
if (tlp_dmaDoneMark_EN)
tlp_dmaDoneMark <= `BSV_ASSIGNMENT_DELAY tlp_dmaDoneMark_D_IN;
if (tlp_dmaStartMark_EN)
tlp_dmaStartMark <= `BSV_ASSIGNMENT_DELAY tlp_dmaStartMark_D_IN;
if (tlp_dmaTag_EN)
tlp_dmaTag <= `BSV_ASSIGNMENT_DELAY tlp_dmaTag_D_IN;
if (tlp_doXmtMetaBody_EN)
tlp_doXmtMetaBody <= `BSV_ASSIGNMENT_DELAY tlp_doXmtMetaBody_D_IN;
if (tlp_doorSeqDwell_EN)
tlp_doorSeqDwell <= `BSV_ASSIGNMENT_DELAY tlp_doorSeqDwell_D_IN;
if (tlp_fabMeta_EN)
tlp_fabMeta <= `BSV_ASSIGNMENT_DELAY tlp_fabMeta_D_IN;
if (tlp_farBufReady_EN)
tlp_farBufReady <= `BSV_ASSIGNMENT_DELAY tlp_farBufReady_D_IN;
if (tlp_flowDiagCount_EN)
tlp_flowDiagCount <= `BSV_ASSIGNMENT_DELAY tlp_flowDiagCount_D_IN;
if (tlp_gotResponseHeader_EN)
tlp_gotResponseHeader <= `BSV_ASSIGNMENT_DELAY
tlp_gotResponseHeader_D_IN;
if (tlp_lastMetaV_0_EN)
tlp_lastMetaV_0 <= `BSV_ASSIGNMENT_DELAY tlp_lastMetaV_0_D_IN;
if (tlp_lastMetaV_1_EN)
tlp_lastMetaV_1 <= `BSV_ASSIGNMENT_DELAY tlp_lastMetaV_1_D_IN;
if (tlp_lastMetaV_2_EN)
tlp_lastMetaV_2 <= `BSV_ASSIGNMENT_DELAY tlp_lastMetaV_2_D_IN;
if (tlp_lastMetaV_3_EN)
tlp_lastMetaV_3 <= `BSV_ASSIGNMENT_DELAY tlp_lastMetaV_3_D_IN;
if (tlp_lastRuleFired_EN)
tlp_lastRuleFired <= `BSV_ASSIGNMENT_DELAY tlp_lastRuleFired_D_IN;
if (tlp_maxPayloadSize_EN)
tlp_maxPayloadSize <= `BSV_ASSIGNMENT_DELAY tlp_maxPayloadSize_D_IN;
if (tlp_maxReadReqSize_EN)
tlp_maxReadReqSize <= `BSV_ASSIGNMENT_DELAY tlp_maxReadReqSize_D_IN;
if (tlp_nearBufReady_EN)
tlp_nearBufReady <= `BSV_ASSIGNMENT_DELAY tlp_nearBufReady_D_IN;
if (tlp_postSeqDwell_EN)
tlp_postSeqDwell <= `BSV_ASSIGNMENT_DELAY tlp_postSeqDwell_D_IN;
if (tlp_pullTagMatch_EN)
tlp_pullTagMatch <= `BSV_ASSIGNMENT_DELAY tlp_pullTagMatch_D_IN;
if (tlp_remDone_EN)
tlp_remDone <= `BSV_ASSIGNMENT_DELAY tlp_remDone_D_IN;
if (tlp_remStart_EN)
tlp_remStart <= `BSV_ASSIGNMENT_DELAY tlp_remStart_D_IN;
if (tlp_reqMesgInFlight_EN)
tlp_reqMesgInFlight <= `BSV_ASSIGNMENT_DELAY
tlp_reqMesgInFlight_D_IN;
if (tlp_reqMetaBodyInFlight_EN)
tlp_reqMetaBodyInFlight <= `BSV_ASSIGNMENT_DELAY
tlp_reqMetaBodyInFlight_D_IN;
if (tlp_reqMetaInFlight_EN)
tlp_reqMetaInFlight <= `BSV_ASSIGNMENT_DELAY
tlp_reqMetaInFlight_D_IN;
if (tlp_sentTail4DWHeader_EN)
tlp_sentTail4DWHeader <= `BSV_ASSIGNMENT_DELAY
tlp_sentTail4DWHeader_D_IN;
if (tlp_tlpBRAM_debugBdata_EN)
tlp_tlpBRAM_debugBdata <= `BSV_ASSIGNMENT_DELAY
tlp_tlpBRAM_debugBdata_D_IN;
if (tlp_tlpBRAM_readHeaderSent_EN)
tlp_tlpBRAM_readHeaderSent <= `BSV_ASSIGNMENT_DELAY
tlp_tlpBRAM_readHeaderSent_D_IN;
if (tlp_tlpBRAM_readStarted_EN)
tlp_tlpBRAM_readStarted <= `BSV_ASSIGNMENT_DELAY
tlp_tlpBRAM_readStarted_D_IN;
if (tlp_tlpMetaSent_EN)
tlp_tlpMetaSent <= `BSV_ASSIGNMENT_DELAY tlp_tlpMetaSent_D_IN;
if (tlp_tlpRcvBusy_EN)
tlp_tlpRcvBusy <= `BSV_ASSIGNMENT_DELAY tlp_tlpRcvBusy_D_IN;
if (tlp_tlpXmtBusy_EN)
tlp_tlpXmtBusy <= `BSV_ASSIGNMENT_DELAY tlp_tlpXmtBusy_D_IN;
if (tlp_xmtMetaInFlight_EN)
tlp_xmtMetaInFlight <= `BSV_ASSIGNMENT_DELAY
tlp_xmtMetaInFlight_D_IN;
if (tlp_xmtMetaOK_EN)
tlp_xmtMetaOK <= `BSV_ASSIGNMENT_DELAY tlp_xmtMetaOK_D_IN;
if (wci_cEdge_EN) wci_cEdge <= `BSV_ASSIGNMENT_DELAY wci_cEdge_D_IN;
if (wci_cState_EN)
wci_cState <= `BSV_ASSIGNMENT_DELAY wci_cState_D_IN;
if (wci_ctlAckReg_EN)
wci_ctlAckReg <= `BSV_ASSIGNMENT_DELAY wci_ctlAckReg_D_IN;
if (wci_ctlOpActive_EN)
wci_ctlOpActive <= `BSV_ASSIGNMENT_DELAY wci_ctlOpActive_D_IN;
if (wci_illegalEdge_EN)
wci_illegalEdge <= `BSV_ASSIGNMENT_DELAY wci_illegalEdge_D_IN;
if (wci_nState_EN)
wci_nState <= `BSV_ASSIGNMENT_DELAY wci_nState_D_IN;
if (wci_reqF_countReg_EN)
wci_reqF_countReg <= `BSV_ASSIGNMENT_DELAY wci_reqF_countReg_D_IN;
if (wci_respF_cntr_r_EN)
wci_respF_cntr_r <= `BSV_ASSIGNMENT_DELAY wci_respF_cntr_r_D_IN;
if (wci_respF_q_0_EN)
wci_respF_q_0 <= `BSV_ASSIGNMENT_DELAY wci_respF_q_0_D_IN;
if (wci_respF_q_1_EN)
wci_respF_q_1 <= `BSV_ASSIGNMENT_DELAY wci_respF_q_1_D_IN;
if (wci_sFlagReg_EN)
wci_sFlagReg <= `BSV_ASSIGNMENT_DELAY wci_sFlagReg_D_IN;
if (wci_sThreadBusy_d_EN)
wci_sThreadBusy_d <= `BSV_ASSIGNMENT_DELAY wci_sThreadBusy_d_D_IN;
if (wmi_bufDwell_EN)
wmi_bufDwell <= `BSV_ASSIGNMENT_DELAY wmi_bufDwell_D_IN;
if (wmi_bytesRemainResp_EN)
wmi_bytesRemainResp <= `BSV_ASSIGNMENT_DELAY
wmi_bytesRemainResp_D_IN;
if (wmi_doneWithMesg_EN)
wmi_doneWithMesg <= `BSV_ASSIGNMENT_DELAY wmi_doneWithMesg_D_IN;
if (wmi_lastMesg_EN)
wmi_lastMesg <= `BSV_ASSIGNMENT_DELAY wmi_lastMesg_D_IN;
if (wmi_mesgBufReady_EN)
wmi_mesgBufReady <= `BSV_ASSIGNMENT_DELAY wmi_mesgBufReady_D_IN;
if (wmi_mesgBusy_EN)
wmi_mesgBusy <= `BSV_ASSIGNMENT_DELAY wmi_mesgBusy_D_IN;
if (wmi_mesgCount_EN)
wmi_mesgCount <= `BSV_ASSIGNMENT_DELAY wmi_mesgCount_D_IN;
if (wmi_mesgDone_EN)
wmi_mesgDone <= `BSV_ASSIGNMENT_DELAY wmi_mesgDone_D_IN;
if (wmi_mesgMeta_EN)
wmi_mesgMeta <= `BSV_ASSIGNMENT_DELAY wmi_mesgMeta_D_IN;
if (wmi_mesgStart_EN)
wmi_mesgStart <= `BSV_ASSIGNMENT_DELAY wmi_mesgStart_D_IN;
if (wmi_metaBusy_EN)
wmi_metaBusy <= `BSV_ASSIGNMENT_DELAY wmi_metaBusy_D_IN;
if (wmi_p4B_EN) wmi_p4B <= `BSV_ASSIGNMENT_DELAY wmi_p4B_D_IN;
if (wmi_rdActive_EN)
wmi_rdActive <= `BSV_ASSIGNMENT_DELAY wmi_rdActive_D_IN;
if (wmi_reqCount_EN)
wmi_reqCount <= `BSV_ASSIGNMENT_DELAY wmi_reqCount_D_IN;
if (wmi_thisMesg_EN)
wmi_thisMesg <= `BSV_ASSIGNMENT_DELAY wmi_thisMesg_D_IN;
if (wmi_wmi_blockReq_EN)
wmi_wmi_blockReq <= `BSV_ASSIGNMENT_DELAY wmi_wmi_blockReq_D_IN;
if (wmi_wmi_dhF_countReg_EN)
wmi_wmi_dhF_countReg <= `BSV_ASSIGNMENT_DELAY
wmi_wmi_dhF_countReg_D_IN;
if (wmi_wmi_dhF_levelsValid_EN)
wmi_wmi_dhF_levelsValid <= `BSV_ASSIGNMENT_DELAY
wmi_wmi_dhF_levelsValid_D_IN;
if (wmi_wmi_errorSticky_EN)
wmi_wmi_errorSticky <= `BSV_ASSIGNMENT_DELAY
wmi_wmi_errorSticky_D_IN;
if (wmi_wmi_mFlagF_countReg_EN)
wmi_wmi_mFlagF_countReg <= `BSV_ASSIGNMENT_DELAY
wmi_wmi_mFlagF_countReg_D_IN;
if (wmi_wmi_mFlagF_levelsValid_EN)
wmi_wmi_mFlagF_levelsValid <= `BSV_ASSIGNMENT_DELAY
wmi_wmi_mFlagF_levelsValid_D_IN;
if (wmi_wmi_operateD_EN)
wmi_wmi_operateD <= `BSV_ASSIGNMENT_DELAY wmi_wmi_operateD_D_IN;
if (wmi_wmi_peerIsReady_EN)
wmi_wmi_peerIsReady <= `BSV_ASSIGNMENT_DELAY
wmi_wmi_peerIsReady_D_IN;
if (wmi_wmi_reqF_countReg_EN)
wmi_wmi_reqF_countReg <= `BSV_ASSIGNMENT_DELAY
wmi_wmi_reqF_countReg_D_IN;
if (wmi_wmi_reqF_levelsValid_EN)
wmi_wmi_reqF_levelsValid <= `BSV_ASSIGNMENT_DELAY
wmi_wmi_reqF_levelsValid_D_IN;
if (wmi_wmi_respF_cntr_r_EN)
wmi_wmi_respF_cntr_r <= `BSV_ASSIGNMENT_DELAY
wmi_wmi_respF_cntr_r_D_IN;
if (wmi_wmi_respF_q_0_EN)
wmi_wmi_respF_q_0 <= `BSV_ASSIGNMENT_DELAY wmi_wmi_respF_q_0_D_IN;
if (wmi_wmi_respF_q_1_EN)
wmi_wmi_respF_q_1 <= `BSV_ASSIGNMENT_DELAY wmi_wmi_respF_q_1_D_IN;
if (wmi_wmi_sFlagReg_EN)
wmi_wmi_sFlagReg <= `BSV_ASSIGNMENT_DELAY wmi_wmi_sFlagReg_D_IN;
if (wmi_wmi_trafficSticky_EN)
wmi_wmi_trafficSticky <= `BSV_ASSIGNMENT_DELAY
wmi_wmi_trafficSticky_D_IN;
if (wmi_wrActive_EN)
wmi_wrActive <= `BSV_ASSIGNMENT_DELAY wmi_wrActive_D_IN;
if (wmi_wrFinalize_EN)
wmi_wrFinalize <= `BSV_ASSIGNMENT_DELAY wmi_wrFinalize_D_IN;
if (wmi_wrtCount_EN)
wmi_wrtCount <= `BSV_ASSIGNMENT_DELAY wmi_wrtCount_D_IN;
if (wti_nowReq_EN)
wti_nowReq <= `BSV_ASSIGNMENT_DELAY wti_nowReq_D_IN;
if (wti_operateD_EN)
wti_operateD <= `BSV_ASSIGNMENT_DELAY wti_operateD_D_IN;
end
if (bml_fabBufsAvail_EN)
bml_fabBufsAvail <= `BSV_ASSIGNMENT_DELAY bml_fabBufsAvail_D_IN;
if (bml_fabFlowAddr_EN)
bml_fabFlowAddr <= `BSV_ASSIGNMENT_DELAY bml_fabFlowAddr_D_IN;
if (bml_fabMesgAddr_EN)
bml_fabMesgAddr <= `BSV_ASSIGNMENT_DELAY bml_fabMesgAddr_D_IN;
if (bml_fabMetaAddr_EN)
bml_fabMetaAddr <= `BSV_ASSIGNMENT_DELAY bml_fabMetaAddr_D_IN;
if (bml_lclBufsAR_EN)
bml_lclBufsAR <= `BSV_ASSIGNMENT_DELAY bml_lclBufsAR_D_IN;
if (bml_lclBufsCF_EN)
bml_lclBufsCF <= `BSV_ASSIGNMENT_DELAY bml_lclBufsCF_D_IN;
if (bml_lclCredit_EN)
bml_lclCredit <= `BSV_ASSIGNMENT_DELAY bml_lclCredit_D_IN;
if (bml_lclMesgAddr_EN)
bml_lclMesgAddr <= `BSV_ASSIGNMENT_DELAY bml_lclMesgAddr_D_IN;
if (bml_lclMetaAddr_EN)
bml_lclMetaAddr <= `BSV_ASSIGNMENT_DELAY bml_lclMetaAddr_D_IN;
if (bml_remMesgAddr_EN)
bml_remMesgAddr <= `BSV_ASSIGNMENT_DELAY bml_remMesgAddr_D_IN;
if (bml_remMetaAddr_EN)
bml_remMetaAddr <= `BSV_ASSIGNMENT_DELAY bml_remMetaAddr_D_IN;
if (tlp_dmaPullRemainDWLen_EN)
tlp_dmaPullRemainDWLen <= `BSV_ASSIGNMENT_DELAY
tlp_dmaPullRemainDWLen_D_IN;
if (tlp_dmaPullRemainDWSub_EN)
tlp_dmaPullRemainDWSub <= `BSV_ASSIGNMENT_DELAY
tlp_dmaPullRemainDWSub_D_IN;
if (tlp_dmaReqTag_EN)
tlp_dmaReqTag <= `BSV_ASSIGNMENT_DELAY tlp_dmaReqTag_D_IN;
if (tlp_fabFlowAddr_EN)
tlp_fabFlowAddr <= `BSV_ASSIGNMENT_DELAY tlp_fabFlowAddr_D_IN;
if (tlp_fabFlowAddrMS_EN)
tlp_fabFlowAddrMS <= `BSV_ASSIGNMENT_DELAY tlp_fabFlowAddrMS_D_IN;
if (tlp_fabMesgAccu_EN)
tlp_fabMesgAccu <= `BSV_ASSIGNMENT_DELAY tlp_fabMesgAccu_D_IN;
if (tlp_fabMesgAddr_EN)
tlp_fabMesgAddr <= `BSV_ASSIGNMENT_DELAY tlp_fabMesgAddr_D_IN;
if (tlp_fabMesgAddrMS_EN)
tlp_fabMesgAddrMS <= `BSV_ASSIGNMENT_DELAY tlp_fabMesgAddrMS_D_IN;
if (tlp_fabMetaAddr_EN)
tlp_fabMetaAddr <= `BSV_ASSIGNMENT_DELAY tlp_fabMetaAddr_D_IN;
if (tlp_fabMetaAddrMS_EN)
tlp_fabMetaAddrMS <= `BSV_ASSIGNMENT_DELAY tlp_fabMetaAddrMS_D_IN;
if (tlp_inIgnorePkt_EN)
tlp_inIgnorePkt <= `BSV_ASSIGNMENT_DELAY tlp_inIgnorePkt_D_IN;
if (tlp_mesgComplReceived_EN)
tlp_mesgComplReceived <= `BSV_ASSIGNMENT_DELAY
tlp_mesgComplReceived_D_IN;
if (tlp_mesgLengthRemainPull_EN)
tlp_mesgLengthRemainPull <= `BSV_ASSIGNMENT_DELAY
tlp_mesgLengthRemainPull_D_IN;
if (tlp_mesgLengthRemainPush_EN)
tlp_mesgLengthRemainPush <= `BSV_ASSIGNMENT_DELAY
tlp_mesgLengthRemainPush_D_IN;
if (tlp_outDwRemain_EN)
tlp_outDwRemain <= `BSV_ASSIGNMENT_DELAY tlp_outDwRemain_D_IN;
if (tlp_remMesgAccu_EN)
tlp_remMesgAccu <= `BSV_ASSIGNMENT_DELAY tlp_remMesgAccu_D_IN;
if (tlp_remMesgAddr_EN)
tlp_remMesgAddr <= `BSV_ASSIGNMENT_DELAY tlp_remMesgAddr_D_IN;
if (tlp_remMetaAddr_EN)
tlp_remMetaAddr <= `BSV_ASSIGNMENT_DELAY tlp_remMetaAddr_D_IN;
if (tlp_srcMesgAccu_EN)
tlp_srcMesgAccu <= `BSV_ASSIGNMENT_DELAY tlp_srcMesgAccu_D_IN;
if (tlp_tlpBRAM_rdRespDwRemain_EN)
tlp_tlpBRAM_rdRespDwRemain <= `BSV_ASSIGNMENT_DELAY
tlp_tlpBRAM_rdRespDwRemain_D_IN;
if (tlp_tlpBRAM_readNxtDWAddr_EN)
tlp_tlpBRAM_readNxtDWAddr <= `BSV_ASSIGNMENT_DELAY
tlp_tlpBRAM_readNxtDWAddr_D_IN;
if (tlp_tlpBRAM_readRemainDWLen_EN)
tlp_tlpBRAM_readRemainDWLen <= `BSV_ASSIGNMENT_DELAY
tlp_tlpBRAM_readRemainDWLen_D_IN;
if (tlp_tlpBRAM_writeDWAddr_EN)
tlp_tlpBRAM_writeDWAddr <= `BSV_ASSIGNMENT_DELAY
tlp_tlpBRAM_writeDWAddr_D_IN;
if (tlp_tlpBRAM_writeLastBE_EN)
tlp_tlpBRAM_writeLastBE <= `BSV_ASSIGNMENT_DELAY
tlp_tlpBRAM_writeLastBE_D_IN;
if (tlp_tlpBRAM_writeRemainDWLen_EN)
tlp_tlpBRAM_writeRemainDWLen <= `BSV_ASSIGNMENT_DELAY
tlp_tlpBRAM_writeRemainDWLen_D_IN;
if (wmi_addr_EN) wmi_addr <= `BSV_ASSIGNMENT_DELAY wmi_addr_D_IN;
if (wmi_bytesRemainReq_EN)
wmi_bytesRemainReq <= `BSV_ASSIGNMENT_DELAY wmi_bytesRemainReq_D_IN;
if (wmi_lclMesgAddr_EN)
wmi_lclMesgAddr <= `BSV_ASSIGNMENT_DELAY wmi_lclMesgAddr_D_IN;
if (wmi_lclMetaAddr_EN)
wmi_lclMetaAddr <= `BSV_ASSIGNMENT_DELAY wmi_lclMetaAddr_D_IN;
if (wmi_wmi_statusR_EN)
wmi_wmi_statusR <= `BSV_ASSIGNMENT_DELAY wmi_wmi_statusR_D_IN;
end
always@(posedge CLK or `BSV_RESET_EDGE RST_N)
if (RST_N == `BSV_RESET_VALUE)
begin
wci_isReset_isInReset <= `BSV_ASSIGNMENT_DELAY 1'd1;
wmi_wmi_isReset_isInReset <= `BSV_ASSIGNMENT_DELAY 1'd1;
wti_isReset_isInReset <= `BSV_ASSIGNMENT_DELAY 1'd1;
end
else
begin
if (wci_isReset_isInReset_EN)
wci_isReset_isInReset <= `BSV_ASSIGNMENT_DELAY
wci_isReset_isInReset_D_IN;
if (wmi_wmi_isReset_isInReset_EN)
wmi_wmi_isReset_isInReset <= `BSV_ASSIGNMENT_DELAY
wmi_wmi_isReset_isInReset_D_IN;
if (wti_isReset_isInReset_EN)
wti_isReset_isInReset <= `BSV_ASSIGNMENT_DELAY
wti_isReset_isInReset_D_IN;
end
// synopsys translate_off
`ifdef BSV_NO_INITIAL_BLOCKS
`else // not BSV_NO_INITIAL_BLOCKS
initial
begin
bml_crdBuf_modulus = 16'hAAAA;
bml_crdBuf_value = 16'hAAAA;
bml_datumAReg = 1'h0;
bml_fabAvail = 1'h0;
bml_fabBuf_modulus = 16'hAAAA;
bml_fabBuf_value = 16'hAAAA;
bml_fabBufsAvail = 16'hAAAA;
bml_fabDone = 1'h0;
bml_fabFlowAddr = 32'hAAAAAAAA;
bml_fabFlowBase = 32'hAAAAAAAA;
bml_fabFlowBaseMS = 32'hAAAAAAAA;
bml_fabFlowSize = 32'hAAAAAAAA;
bml_fabMesgAddr = 32'hAAAAAAAA;
bml_fabMesgBase = 32'hAAAAAAAA;
bml_fabMesgBaseMS = 32'hAAAAAAAA;
bml_fabMesgSize = 32'hAAAAAAAA;
bml_fabMetaAddr = 32'hAAAAAAAA;
bml_fabMetaBase = 32'hAAAAAAAA;
bml_fabMetaBaseMS = 32'hAAAAAAAA;
bml_fabMetaSize = 32'hAAAAAAAA;
bml_fabNumBufs = 16'hAAAA;
bml_lclBufDone = 1'h0;
bml_lclBufStart = 1'h0;
bml_lclBuf_modulus = 16'hAAAA;
bml_lclBuf_value = 16'hAAAA;
bml_lclBufsAR = 16'hAAAA;
bml_lclBufsCF = 16'hAAAA;
bml_lclCredit = 16'hAAAA;
bml_lclDones = 16'hAAAA;
bml_lclMesgAddr = 16'hAAAA;
bml_lclMetaAddr = 16'hAAAA;
bml_lclNumBufs = 16'hAAAA;
bml_lclStarts = 16'hAAAA;
bml_mesgBase = 16'hAAAA;
bml_mesgSize = 16'hAAAA;
bml_metaBase = 16'hAAAA;
bml_metaSize = 16'hAAAA;
bml_remBuf_modulus = 16'hAAAA;
bml_remBuf_value = 16'hAAAA;
bml_remDone = 1'h0;
bml_remDones = 16'hAAAA;
bml_remMesgAddr = 16'hAAAA;
bml_remMetaAddr = 16'hAAAA;
bml_remStart = 1'h0;
bml_remStarts = 16'hAAAA;
bram_0_serverAdapterA_cnt = 3'h2;
bram_0_serverAdapterA_s1 = 2'h2;
bram_0_serverAdapterB_cnt = 3'h2;
bram_0_serverAdapterB_s1 = 2'h2;
bram_1_serverAdapterA_cnt = 3'h2;
bram_1_serverAdapterA_s1 = 2'h2;
bram_1_serverAdapterB_cnt = 3'h2;
bram_1_serverAdapterB_s1 = 2'h2;
bram_2_serverAdapterA_cnt = 3'h2;
bram_2_serverAdapterA_s1 = 2'h2;
bram_2_serverAdapterB_cnt = 3'h2;
bram_2_serverAdapterB_s1 = 2'h2;
bram_3_serverAdapterA_cnt = 3'h2;
bram_3_serverAdapterA_s1 = 2'h2;
bram_3_serverAdapterB_cnt = 3'h2;
bram_3_serverAdapterB_s1 = 2'h2;
dmaDoneTime = 64'hAAAAAAAAAAAAAAAA;
dmaStartTime = 64'hAAAAAAAAAAAAAAAA;
dpControl = 8'hAA;
tlp_complTimerCount = 12'hAAA;
tlp_complTimerRunning = 1'h0;
tlp_creditReady = 1'h0;
tlp_dmaDoTailEvent = 1'h0;
tlp_dmaDoneMark = 1'h0;
tlp_dmaPullRemainDWLen = 10'h2AA;
tlp_dmaPullRemainDWSub = 10'h2AA;
tlp_dmaReqTag = 5'h0A;
tlp_dmaStartMark = 1'h0;
tlp_dmaTag = 5'h0A;
tlp_doXmtMetaBody = 1'h0;
tlp_doorSeqDwell = 4'hA;
tlp_fabFlowAddr = 32'hAAAAAAAA;
tlp_fabFlowAddrMS = 32'hAAAAAAAA;
tlp_fabMesgAccu = 32'hAAAAAAAA;
tlp_fabMesgAddr = 32'hAAAAAAAA;
tlp_fabMesgAddrMS = 32'hAAAAAAAA;
tlp_fabMeta = 129'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
tlp_fabMetaAddr = 32'hAAAAAAAA;
tlp_fabMetaAddrMS = 32'hAAAAAAAA;
tlp_farBufReady = 1'h0;
tlp_flowDiagCount = 32'hAAAAAAAA;
tlp_gotResponseHeader = 1'h0;
tlp_inIgnorePkt = 1'h0;
tlp_lastMetaV_0 = 32'hAAAAAAAA;
tlp_lastMetaV_1 = 32'hAAAAAAAA;
tlp_lastMetaV_2 = 32'hAAAAAAAA;
tlp_lastMetaV_3 = 32'hAAAAAAAA;
tlp_lastRuleFired = 4'hA;
tlp_maxPayloadSize = 13'h0AAA;
tlp_maxReadReqSize = 13'h0AAA;
tlp_mesgComplReceived = 17'h0AAAA;
tlp_mesgLengthRemainPull = 17'h0AAAA;
tlp_mesgLengthRemainPush = 17'h0AAAA;
tlp_nearBufReady = 1'h0;
tlp_outDwRemain = 10'h2AA;
tlp_postSeqDwell = 4'hA;
tlp_pullTagMatch = 1'h0;
tlp_remDone = 1'h0;
tlp_remMesgAccu = 16'hAAAA;
tlp_remMesgAddr = 16'hAAAA;
tlp_remMetaAddr = 16'hAAAA;
tlp_remStart = 1'h0;
tlp_reqMesgInFlight = 1'h0;
tlp_reqMetaBodyInFlight = 1'h0;
tlp_reqMetaInFlight = 1'h0;
tlp_sentTail4DWHeader = 1'h0;
tlp_srcMesgAccu = 32'hAAAAAAAA;
tlp_tlpBRAM_debugBdata = 128'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
tlp_tlpBRAM_rdRespDwRemain = 10'h2AA;
tlp_tlpBRAM_readHeaderSent = 1'h0;
tlp_tlpBRAM_readNxtDWAddr = 13'h0AAA;
tlp_tlpBRAM_readRemainDWLen = 10'h2AA;
tlp_tlpBRAM_readStarted = 1'h0;
tlp_tlpBRAM_writeDWAddr = 13'h0AAA;
tlp_tlpBRAM_writeLastBE = 4'hA;
tlp_tlpBRAM_writeRemainDWLen = 10'h2AA;
tlp_tlpMetaSent = 1'h0;
tlp_tlpRcvBusy = 1'h0;
tlp_tlpXmtBusy = 1'h0;
tlp_xmtMetaInFlight = 1'h0;
tlp_xmtMetaOK = 1'h0;
wci_cEdge = 3'h2;
wci_cState = 3'h2;
wci_ctlAckReg = 1'h0;
wci_ctlOpActive = 1'h0;
wci_illegalEdge = 1'h0;
wci_isReset_isInReset = 1'h0;
wci_nState = 3'h2;
wci_reqF_countReg = 2'h2;
wci_respF_cntr_r = 2'h2;
wci_respF_q_0 = 34'h2AAAAAAAA;
wci_respF_q_1 = 34'h2AAAAAAAA;
wci_sFlagReg = 1'h0;
wci_sThreadBusy_d = 1'h0;
wmi_addr = 14'h2AAA;
wmi_bufDwell = 2'h2;
wmi_bytesRemainReq = 14'h2AAA;
wmi_bytesRemainResp = 14'h2AAA;
wmi_doneWithMesg = 1'h0;
wmi_lastMesg = 32'hAAAAAAAA;
wmi_lclMesgAddr = 15'h2AAA;
wmi_lclMetaAddr = 15'h2AAA;
wmi_mesgBufReady = 1'h0;
wmi_mesgBusy = 1'h0;
wmi_mesgCount = 32'hAAAAAAAA;
wmi_mesgDone = 1'h0;
wmi_mesgMeta = 129'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
wmi_mesgStart = 1'h0;
wmi_metaBusy = 1'h0;
wmi_p4B = 2'h2;
wmi_rdActive = 1'h0;
wmi_reqCount = 16'hAAAA;
wmi_thisMesg = 32'hAAAAAAAA;
wmi_wmi_blockReq = 1'h0;
wmi_wmi_dhF_countReg = 2'h2;
wmi_wmi_dhF_levelsValid = 1'h0;
wmi_wmi_errorSticky = 1'h0;
wmi_wmi_isReset_isInReset = 1'h0;
wmi_wmi_mFlagF_countReg = 2'h2;
wmi_wmi_mFlagF_levelsValid = 1'h0;
wmi_wmi_operateD = 1'h0;
wmi_wmi_peerIsReady = 1'h0;
wmi_wmi_reqF_countReg = 2'h2;
wmi_wmi_reqF_levelsValid = 1'h0;
wmi_wmi_respF_cntr_r = 2'h2;
wmi_wmi_respF_q_0 = 130'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
wmi_wmi_respF_q_1 = 130'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
wmi_wmi_sFlagReg = 32'hAAAAAAAA;
wmi_wmi_statusR = 8'hAA;
wmi_wmi_trafficSticky = 1'h0;
wmi_wrActive = 1'h0;
wmi_wrFinalize = 1'h0;
wmi_wrtCount = 16'hAAAA;
wti_isReset_isInReset = 1'h0;
wti_nowReq = 67'h2AAAAAAAAAAAAAAAA;
wti_operateD = 1'h0;
end
`endif // BSV_NO_INITIAL_BLOCKS
// synopsys translate_on
// handling of system tasks
// synopsys translate_off
always@(negedge CLK)
begin
#0;
if (RST_N != `BSV_RESET_VALUE)
if (bram_0_serverAdapterA_s1[1] &&
!bram_0_serverAdapterA_outDataCore_FULL_N)
$display("ERROR: %m: mkBRAMSeverAdapter overrun");
if (RST_N != `BSV_RESET_VALUE)
if (bram_0_serverAdapterB_s1[1] &&
!bram_0_serverAdapterB_outDataCore_FULL_N)
$display("ERROR: %m: mkBRAMSeverAdapter overrun");
if (RST_N != `BSV_RESET_VALUE)
if (bram_1_serverAdapterA_s1[1] &&
!bram_1_serverAdapterA_outDataCore_FULL_N)
$display("ERROR: %m: mkBRAMSeverAdapter overrun");
if (RST_N != `BSV_RESET_VALUE)
if (bram_1_serverAdapterB_s1[1] &&
!bram_1_serverAdapterB_outDataCore_FULL_N)
$display("ERROR: %m: mkBRAMSeverAdapter overrun");
if (RST_N != `BSV_RESET_VALUE)
if (bram_2_serverAdapterA_s1[1] &&
!bram_2_serverAdapterA_outDataCore_FULL_N)
$display("ERROR: %m: mkBRAMSeverAdapter overrun");
if (RST_N != `BSV_RESET_VALUE)
if (bram_2_serverAdapterB_s1[1] &&
!bram_2_serverAdapterB_outDataCore_FULL_N)
$display("ERROR: %m: mkBRAMSeverAdapter overrun");
if (RST_N != `BSV_RESET_VALUE)
if (bram_3_serverAdapterA_s1[1] &&
!bram_3_serverAdapterA_outDataCore_FULL_N)
$display("ERROR: %m: mkBRAMSeverAdapter overrun");
if (RST_N != `BSV_RESET_VALUE)
if (bram_3_serverAdapterB_s1[1] &&
!bram_3_serverAdapterB_outDataCore_FULL_N)
$display("ERROR: %m: mkBRAMSeverAdapter overrun");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_cfrd)
begin
v__h91963 = $time;
#0;
end
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_cfrd)
$display("[%0d]: %m: WCI CONFIG READ Addr:%0x BE:%0x Data:%0x",
v__h91963,
wci_reqF_D_OUT[63:32],
wci_reqF_D_OUT[67:64],
_theResult____h91947);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_ctl_op_start)
begin
v__h15577 = $time;
#0;
end
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_ctl_op_start)
$display("[%0d]: %m: WCI ControlOp: Starting-transition edge:%x from:%x",
v__h15577,
wci_reqF_D_OUT[36:34],
wci_cState);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_tlp_dmaRequestNearMeta)
begin
v__h41005 = $time;
#0;
end
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_tlp_dmaRequestNearMeta)
$display("[%0d]: %m: dmaRequestNearMeta FPactMesg-Step1/7",
v__h41005);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_tlp_dmaPushRequestMesg)
begin
v__h47790 = $time;
#0;
end
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_tlp_dmaPushRequestMesg)
$display("[%0d]: %m: dmaPushRequestMesg FPactMesg-Step3/7",
v__h47790);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_tlp_dmaResponseNearMetaHead)
begin
v__h43090 = $time;
#0;
end
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_tlp_dmaResponseNearMetaHead)
$display("[%0d]: %m: dmaResponseNearMetaHead FPactMesg-Step2a/7 mesgLength:%0x",
v__h43090,
x__h42208);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_tlp_dmaPushResponseHeader)
begin
v__h48409 = $time;
#0;
end
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_tlp_dmaPushResponseHeader)
$display("[%0d]: %m: dmaPushResponseHeader FPactMesg-Step4a/7",
v__h48409);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_tlp_dmaPushResponseBody)
begin
v__h48757 = $time;
#0;
end
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_tlp_dmaPushResponseBody)
$display("[%0d]: %m: dmaPushResponseBody FPactMesg-Step4b/7",
v__h48757);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_tlp_dmaXmtMetaHead)
begin
v__h50007 = $time;
#0;
end
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_tlp_dmaXmtMetaHead)
$display("[%0d]: %m: dmaXmtMetaHead FPactMesg-Step5/7", v__h50007);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_tlp_dmaXmtTailEvent)
begin
v__h56506 = $time;
#0;
end
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_tlp_dmaXmtTailEvent)
$display("[%0d]: %m: dmaXmtTailEvent FPactMesg-Step7/7", v__h56506);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_tlp_dmaXmtMetaBody)
begin
v__h56382 = $time;
#0;
end
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_tlp_dmaXmtMetaBody)
$display("[%0d]: %m: dmaXmtMetaBody FPactMesg-Step6/7", v__h56382);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_tlp_dmaXmtDoorbell)
begin
v__h56714 = $time;
#0;
end
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_tlp_dmaXmtDoorbell)
$display("[%0d]: %m: dmaXmtDoorbell FC/FPactFlow-Step1/1", v__h56714);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_tlp_dmaRespHeadFarMeta)
begin
v__h59442 = $time;
#0;
end
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_tlp_dmaRespHeadFarMeta)
$display("[%0d]: %m: dmaRespHeadFarMeta FPactMesg-Step2a/N fabMeta:%0x",
v__h59442,
x__h58352);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_tlp_dmaPullTailEvent)
begin
v__h65522 = $time;
#0;
end
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_tlp_dmaPullTailEvent)
$display("[%0d]: %m: dmaPullTailEvent FPactMesg-Step5/5", v__h65522);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_tlp_dmaRespBodyFarMeta)
begin
v__h63835 = $time;
#0;
end
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_tlp_dmaRespBodyFarMeta)
$display("[%0d]: %m: dmaRespBodyFarMeta FPactMesg-Step2b/N opcode:%0x nowMS:%0x nowLS:%0x",
v__h63835,
opcode__h60417,
nowMS__h61665,
nowLS__h62622);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_tlp_dmaPullResponseHeader)
begin
v__h65011 = $time;
#0;
end
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_tlp_dmaPullResponseHeader)
$display("[%0d]: %m: dmaPullResponseHeader FPactMesg-Step4a/5",
v__h65011);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_tlp_dmaPullResponseBody)
begin
v__h65359 = $time;
#0;
end
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_tlp_dmaPullResponseBody)
$display("[%0d]: %m: dmaPullResponseBody FPactMesg-Step4b/5",
v__h65359);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_tlp_dmaTailEventSender)
begin
v__h70765 = $time;
#0;
end
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_tlp_dmaTailEventSender)
$display("[%0d]: %m: dmaTailEventSender - generic", v__h70765);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_tlp_dmaResponseNearMetaBody)
begin
v__h47450 = $time;
#0;
end
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_tlp_dmaResponseNearMetaBody)
$display("[%0d]: %m: dmaResponseNearMetaBody FPactMesg-Step2b/7 opcode:%0x nowMS:%0x nowLS:%0x",
v__h47450,
opcode__h44022,
nowMS__h45280,
nowLS__h46239);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_tlp_dmaRequestFarMeta)
begin
v__h57177 = $time;
#0;
end
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_tlp_dmaRequestFarMeta)
$display("[%0d]: %m: dmaRequestFarMeta FCactMesg-Step1/5", v__h57177);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_tlp_dmaPullRequestFarMesg)
begin
v__h64356 = $time;
#0;
end
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_tlp_dmaPullRequestFarMesg)
$display("[%0d]: %m: dmaPullRequestFarMesg FCactMesg-Step3/5",
v__h64356);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wmi_doWriteFinalize)
begin
v__h82455 = $time;
#0;
end
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wmi_doWriteFinalize)
$display("[%0d]: %m: doWriteFinalize lclMetaAddr :%0x length:%0x opcode:%0x nowMS:%0x nowLS:%0x ",
v__h82455,
wmi_lclMetaAddr,
x3__h81813,
mesgMeta_opcode__h81853,
dmaStartTime_D_IN[63:32],
dmaStartTime_D_IN[31:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_cfwr && wci_reqF_D_OUT[39:32] == 8'h18)
begin
v__h91331 = $time;
#0;
end
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_cfwr && wci_reqF_D_OUT[39:32] == 8'h18)
$display("[%0d] %m: fabDoneAvail Event", v__h91331);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_cfwr)
begin
v__h91800 = $time;
#0;
end
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_cfwr)
$display("[%0d]: %m: WCI CONFIG WRITE Addr:%0x BE:%0x Data:%0x",
v__h91800,
wci_reqF_D_OUT[63:32],
wci_reqF_D_OUT[67:64],
wci_reqF_D_OUT[31:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_cfwr && WILL_FIRE_RL_wci_cfrd)
$display("Error: \"bsv/inf/OCDP.bsv\", line 68, column 26: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfwr] and [RL_wci_cfrd] )\n fired in the same clock cycle.\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_ctl_op_complete && wci_illegalEdge)
begin
v__h15896 = $time;
#0;
end
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_ctl_op_complete && wci_illegalEdge)
$display("[%0d]: %m: WCI ControlOp: ILLEGAL-EDGE Completed-transition edge:%x from:%x",
v__h15896,
wci_cEdge,
wci_cState);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_ctl_op_complete && !wci_illegalEdge)
begin
v__h15752 = $time;
#0;
end
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_ctl_op_complete && !wci_illegalEdge)
$display("[%0d]: %m: WCI ControlOp: Completed-transition edge:%x from:%x to:%x",
v__h15752,
wci_cEdge,
wci_cState,
wci_nState);
end
// synopsys translate_on
endmodule
|
module sky130_fd_sc_ms__clkbuf (
X,
A
);
output X;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
|
module when ps2_ready signals is asserted,
// note that the key here is still a scan code, and software needs to transform it into a ASCII code
assign io_read_clk = Clk_CPU;
PS2_IO U12(
//wb_input
.dat_i (s4_dat_o),
.adr_i (s4_adr_o),
.we_i (s4_we_o),
.stb_i (s4_stb_o),
//wb_output
.dat_o (s4_dat_i),
.ack_o (s4_ack_i),
.io_read_clk (io_read_clk),
.clk_ps2 (clkdiv[0]),
.rst (rst),
.PS2_clk (PS2_clk),
.PS2_Data (PS2_Data),
//.ps2_rd (ps2_rd),
.ps2_ready (ps2_ready),
.ps2_irq (ps2_irq),
.ps2_iack (ps2_iack),
.key_d (key_d),
.key (key),
.ps2_key (ps2_key)
);
uart U13(
//wb_input
.dat_i (s0_dat_o),
.adr_i (s0_adr_o),
.we_i (s0_we_o),
.stb_i (s0_stb_o),
//wb_output
.dat_o (s0_dat_i),
.ack_o (s0_ack_i),
.sys_clk (clk_m),
.sys_rst (rst),
.rx_irq (rx_irq),
.rx_iack (rx_iack),
.tx_irq (),
.uart_rx (uart_rx),
.uart_tx (uart_tx)
);
endmodule
|
module sky130_fd_sc_hdll__or4 (
//# {{data|Data Signals}}
input A,
input B,
input C,
input D,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
|
module sky130_fd_sc_lp__dfxbp (
Q ,
Q_N ,
CLK ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Q ;
output Q_N ;
input CLK ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire buf_Q;
// Delay Name Output Other arguments
sky130_fd_sc_lp__udp_dff$P_pp$PG$N `UNIT_DELAY dff0 (buf_Q , D, CLK, , VPWR, VGND);
buf buf0 (Q , buf_Q );
not not0 (Q_N , buf_Q );
endmodule
|
module sky130_fd_sc_hdll__o2bb2ai (
//# {{data|Data Signals}}
input A1_N,
input A2_N,
input B1 ,
input B2 ,
output Y ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
|
module DE5Gen1x8If64
#(// Number of RIFFA Channels
parameter C_NUM_CHNL = 1,
// Number of PCIe Lanes
parameter C_NUM_LANES = 8,
// Settings from Quartus IP Library
parameter C_PCI_DATA_WIDTH = 64,
parameter C_MAX_PAYLOAD_BYTES = 256,
parameter C_LOG_NUM_TAGS = 5
)
(
// ----------LEDs----------
output [7:0] LED,
// ----------PCIE----------
input PCIE_RESET_N,
input PCIE_REFCLK,
// ----------PCIE Serial RX----------
input [C_NUM_LANES-1:0] PCIE_RX_IN,
// ----------PCIE Serial TX----------
output [C_NUM_LANES-1:0] PCIE_TX_OUT,
// ----------Oscillators----------
input OSC_BANK3D_50MHZ
);
wire npor;
wire pin_perst;
// ----------LMI Interface----------
wire [11:0] lmi_addr;
wire [31:0] lmi_din;
wire lmi_rden;
wire lmi_wren;
wire lmi_ack;
wire [31:0] lmi_dout;
// ----------TL Config interface----------
wire [3:0] tl_cfg_add;
wire [31:0] tl_cfg_ctl;
wire [52:0] tl_cfg_sts;
// ----------Rx/TX Interfaces----------
wire [0:0] rx_st_sop;
wire [0:0] rx_st_eop;
wire [0:0] rx_st_err;
wire [0:0] rx_st_valid;
wire [0:0] rx_st_empty;
wire rx_st_ready;
wire [63:0] rx_st_data;
wire [7:0] rx_st_bar;
wire rx_st_mask;
wire [0:0] tx_st_sop;
wire [0:0] tx_st_eop;
wire [0:0] tx_st_err;
wire [0:0] tx_st_valid;
wire [0:0] tx_st_empty;
wire tx_st_ready;
wire [63:0] tx_st_data;
// ----------Clocks----------
wire pld_clk;
wire coreclkout_hip;
wire refclk;
wire pld_core_ready;
wire reset_status;
wire serdes_pll_locked;
wire pld_clk_inuse;
// ----------Reconfiguration busses----------
wire [699:0] reconfig_to_xcvr;
wire [505:0] reconfig_from_xcvr;
// ----------Interrupt Interfaces----------
wire app_int_sts;
wire [4:0] app_msi_num;
wire app_msi_req;
wire [2:0] app_msi_tc;
wire app_int_ack;
wire app_msi_ack;
// ----------Link status signals----------
wire derr_cor_ext_rcv;
wire derr_cor_ext_rpl;
wire derr_rpl;
wire dlup;
wire dlup_exit;
wire ev128ns;
wire ev1us;
wire hotrst_exit;
wire [3:0] int_status;
wire l2_exit;
wire [3:0] lane_act;
wire [4:0] ltssmstate;
wire rx_par_err;
wire [1:0] tx_par_err;
wire cfg_par_err;
wire [1:0] currentspeed;
wire [7:0] ko_cpl_spc_header;
wire [11:0] ko_cpl_spc_data;
// ----------Link Status Signals (Driver)----------
wire derr_cor_ext_rcv_drv;
wire derr_cor_ext_rpl_drv;
wire derr_rpl_drv;
wire dlup_drv;
wire dlup_exit_drv;
wire ev128ns_drv;
wire ev1us_drv;
wire hotrst_exit_drv;
wire [3:0] int_status_drv;
wire l2_exit_drv;
wire [3:0] lane_act_drv;
wire [4:0] ltssmstate_drv;
wire rx_par_err_drv;
wire [1:0] tx_par_err_drv;
wire cfg_par_err_drv;
wire [7:0] ko_cpl_spc_header_drv;
wire [11:0] ko_cpl_spc_data_drv;
// ----------Reconfiguration Controller signals----------
wire reconfig_busy;
wire mgmt_clk_clk;
wire mgmt_rst_reset;
wire [6:0] reconfig_mgmt_address;
wire reconfig_mgmt_read;
wire [31:0] reconfig_mgmt_readdata;
wire reconfig_mgmt_waitrequest;
wire reconfig_mgmt_write;
wire [31:0] reconfig_mgmt_writedata;
// ----------Reconfiguration Driver signals----------
wire reconfig_xcvr_clk;
wire reconfig_xcvr_rst;
wire [7:0] rx_in;
wire [7:0] tx_out;
// ----------Serial interfaces----------
assign rx_in = PCIE_RX_IN;
assign PCIE_TX_OUT = tx_out;
// ----------Clocks----------
assign pld_clk = coreclkout_hip;
assign mgmt_clk_clk = PCIE_REFCLK;
assign reconfig_xcvr_clk = PCIE_REFCLK;
assign refclk = PCIE_REFCLK;
assign pld_core_ready = serdes_pll_locked;
// ----------Resets----------
assign reconfig_xcvr_rst = 1'b0;
assign mgmt_rst_reset = 1'b0;
assign pin_perst = PCIE_RESET_N;
assign npor = PCIE_RESET_N;
// ----------LED's----------
assign LED[7:0] = 8'hff;
// -------------------- BEGIN ALTERA IP INSTANTIATION --------------------
// Transciever driver (Required for Gen1)
altpcie_reconfig_driver
#(.number_of_reconfig_interfaces(10),
.gen123_lane_rate_mode_hwtcl("Gen1 (2.5 Gbps)"), // This must be changed between generations
.INTENDED_DEVICE_FAMILY("Stratix V"))
XCVRDriverGen1x8_inst
(
// Outputs
.reconfig_mgmt_address (reconfig_mgmt_address[6:0]),
.reconfig_mgmt_read (reconfig_mgmt_read),
.reconfig_mgmt_write (reconfig_mgmt_write),
.reconfig_mgmt_writedata (reconfig_mgmt_writedata[31:0]),
// Inputs
.pld_clk (pld_clk),
.reconfig_xcvr_rst (reconfig_xcvr_rst),
.reconfig_mgmt_readdata (reconfig_mgmt_readdata[31:0]),
.reconfig_mgmt_waitrequest (reconfig_mgmt_waitrequest),
.reconfig_xcvr_clk (reconfig_xcvr_clk),
.reconfig_busy (reconfig_busy),
// Link Status signals
.derr_cor_ext_rcv_drv (derr_cor_ext_rcv_drv),
.derr_cor_ext_rpl_drv (derr_cor_ext_rpl_drv),
.derr_rpl_drv (derr_rpl_drv),
.dlup_drv (dlup_drv),
.dlup_exit_drv (dlup_exit_drv),
.ev128ns_drv (ev128ns_drv),
.ev1us_drv (ev1us_drv),
.hotrst_exit_drv (hotrst_exit_drv),
.int_status_drv (int_status_drv[3:0]),
.l2_exit_drv (l2_exit_drv),
.lane_act_drv (lane_act_drv[3:0]),
.ltssmstate_drv (ltssmstate_drv[4:0]),
.rx_par_err_drv (rx_par_err_drv),
.tx_par_err_drv (tx_par_err_drv[1:0]),
.cfg_par_err_drv (cfg_par_err_drv),
.ko_cpl_spc_header_drv (ko_cpl_spc_header_drv[7:0]),
.ko_cpl_spc_data_drv (ko_cpl_spc_data_drv[11:0]),
.currentspeed (currentspeed[1:0]));
assign derr_cor_ext_rcv_drv = derr_cor_ext_rcv;
assign derr_cor_ext_rpl_drv = derr_cor_ext_rpl;
assign derr_rpl_drv = derr_rpl;
assign dlup_drv = dlup;
assign dlup_exit_drv = dlup_exit;
assign ev128ns_drv = ev128ns;
assign ev1us_drv = ev1us;
assign hotrst_exit_drv = hotrst_exit;
assign int_status_drv = int_status;
assign l2_exit_drv = l2_exit;
assign lane_act_drv = lane_act;
assign ltssmstate_drv = ltssmstate;
assign rx_par_err_drv = rx_par_err;
assign tx_par_err_drv = tx_par_err;
assign cfg_par_err_drv = cfg_par_err;
assign ko_cpl_spc_header_drv = ko_cpl_spc_header;
assign ko_cpl_spc_data_drv = ko_cpl_spc_data;
XCVRCtrlGen1x8 XCVRCtrlGen1x8_inst
(
// Outputs
.reconfig_busy (reconfig_busy),
.reconfig_mgmt_readdata (reconfig_mgmt_readdata[31:0]),
.reconfig_mgmt_waitrequest (reconfig_mgmt_waitrequest),
.reconfig_to_xcvr (reconfig_to_xcvr[699:0]),
// Inputs
.mgmt_clk_clk (mgmt_clk_clk),
.mgmt_rst_reset (mgmt_rst_reset),
.reconfig_mgmt_address (reconfig_mgmt_address[6:0]),
.reconfig_mgmt_read (reconfig_mgmt_read),
.reconfig_mgmt_write (reconfig_mgmt_write),
.reconfig_mgmt_writedata (reconfig_mgmt_writedata[31:0]),
.reconfig_from_xcvr (reconfig_from_xcvr[459:0]));
// PCIE Core
PCIeGen1x8If64 PCIeGen1x8If64_inst
(
// Outputs
// Local Management Interface
.lmi_ack (lmi_ack),
.lmi_dout (lmi_dout[31:0]),
.tl_cfg_add (tl_cfg_add[3:0]),
.tl_cfg_ctl (tl_cfg_ctl[31:0]),
.tl_cfg_sts (tl_cfg_sts[52:0]),
// RX Interface
.rx_st_sop (rx_st_sop[0:0]),
.rx_st_eop (rx_st_eop[0:0]),
.rx_st_err (rx_st_err[0:0]),
.rx_st_valid (rx_st_valid[0:0]),
.rx_st_data (rx_st_data[63:0]),
.rx_st_bar (rx_st_bar[7:0]),
// TX Interface
.tx_st_ready (tx_st_ready),
.coreclkout_hip (coreclkout_hip),
.reset_status (reset_status),
.serdes_pll_locked (serdes_pll_locked),
.pld_clk_inuse (pld_clk_inuse),
// Reconfiguration Interface
.reconfig_from_xcvr (reconfig_from_xcvr[459:0]),
.tx_out0 (tx_out[0]),
.tx_out1 (tx_out[1]),
.tx_out2 (tx_out[2]),
.tx_out3 (tx_out[3]),
.tx_out4 (tx_out[4]),
.tx_out5 (tx_out[5]),
.tx_out6 (tx_out[6]),
.tx_out7 (tx_out[7]),
.app_int_ack (app_int_ack),
.app_msi_ack (app_msi_ack),
// Link status signals
.derr_cor_ext_rcv (derr_cor_ext_rcv),
.derr_cor_ext_rpl (derr_cor_ext_rpl),
.derr_rpl (derr_rpl),
.dlup (dlup),
.dlup_exit (dlup_exit),
.ev128ns (ev128ns),
.ev1us (ev1us),
.hotrst_exit (hotrst_exit),
.int_status (int_status[3:0]),
.l2_exit (l2_exit),
.lane_act (lane_act[3:0]),
.ltssmstate (ltssmstate[4:0]),
.rx_par_err (rx_par_err),
.tx_par_err (tx_par_err[1:0]),
.cfg_par_err (cfg_par_err),
.ko_cpl_spc_header (ko_cpl_spc_header[7:0]),
.ko_cpl_spc_data (ko_cpl_spc_data[11:0]),
.currentspeed (currentspeed[1:0]),
// Inputs
// Resets
.npor (npor),
.pin_perst (pin_perst),
// Clocks
.pld_clk (pld_clk),
.refclk (refclk),
.pld_core_ready (pld_core_ready),
// Local management Interface
.lmi_addr (lmi_addr[11:0]),
.lmi_din (lmi_din[31:0]),
.lmi_rden (lmi_rden),
.lmi_wren (lmi_wren),
// RX Interface
.rx_st_ready (rx_st_ready),
.rx_st_mask (rx_st_mask),
// TX Interface
.tx_st_sop (tx_st_sop[0:0]),
.tx_st_eop (tx_st_eop[0:0]),
.tx_st_err (tx_st_err[0:0]),
.tx_st_valid (tx_st_valid[0:0]),
.tx_st_data (tx_st_data[63:0]),
// Reconfiguration Interface
.reconfig_to_xcvr (reconfig_to_xcvr[699:0]),
// RX Serial interface
.rx_in0 (rx_in[0]),
.rx_in1 (rx_in[1]),
.rx_in2 (rx_in[2]),
.rx_in3 (rx_in[3]),
.rx_in4 (rx_in[4]),
.rx_in5 (rx_in[5]),
.rx_in6 (rx_in[6]),
.rx_in7 (rx_in[7]),
// Interrupt Interface
.app_int_sts (app_int_sts),
.app_msi_num (app_msi_num[4:0]),
.app_msi_req (app_msi_req),
.app_msi_tc (app_msi_tc[2:0]),
.simu_mode_pipe (1'b0));
// -------------------- END ALTERA IP INSTANTIATION --------------------
// -------------------- BEGIN RIFFA INSTANTAION --------------------
// RIFFA channel interface
wire rst_out;
wire [C_NUM_CHNL-1:0] chnl_rx_clk;
wire [C_NUM_CHNL-1:0] chnl_rx;
wire [C_NUM_CHNL-1:0] chnl_rx_ack;
wire [C_NUM_CHNL-1:0] chnl_rx_last;
wire [(C_NUM_CHNL*32)-1:0] chnl_rx_len;
wire [(C_NUM_CHNL*31)-1:0] chnl_rx_off;
wire [(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0] chnl_rx_data;
wire [C_NUM_CHNL-1:0] chnl_rx_data_valid;
wire [C_NUM_CHNL-1:0] chnl_rx_data_ren;
wire [C_NUM_CHNL-1:0] chnl_tx_clk;
wire [C_NUM_CHNL-1:0] chnl_tx;
wire [C_NUM_CHNL-1:0] chnl_tx_ack;
wire [C_NUM_CHNL-1:0] chnl_tx_last;
wire [(C_NUM_CHNL*32)-1:0] chnl_tx_len;
wire [(C_NUM_CHNL*31)-1:0] chnl_tx_off;
wire [(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0] chnl_tx_data;
wire [C_NUM_CHNL-1:0] chnl_tx_data_valid;
wire [C_NUM_CHNL-1:0] chnl_tx_data_ren;
wire chnl_reset;
wire chnl_clk;
wire riffa_reset;
wire riffa_clk;
assign chnl_clk = pld_clk;
assign chnl_reset = rst_out;
riffa_wrapper_de5
#(/*AUTOINSTPARAM*/
// Parameters
.C_LOG_NUM_TAGS (C_LOG_NUM_TAGS),
.C_NUM_CHNL (C_NUM_CHNL),
.C_PCI_DATA_WIDTH (C_PCI_DATA_WIDTH),
.C_MAX_PAYLOAD_BYTES (C_MAX_PAYLOAD_BYTES))
riffa
(
// Outputs
.RX_ST_READY (rx_st_ready),
.TX_ST_DATA (tx_st_data[C_PCI_DATA_WIDTH-1:0]),
.TX_ST_VALID (tx_st_valid[0:0]),
.TX_ST_EOP (tx_st_eop[0:0]),
.TX_ST_SOP (tx_st_sop[0:0]),
.TX_ST_EMPTY (tx_st_empty[0:0]),
.APP_MSI_REQ (app_msi_req),
.RST_OUT (rst_out),
.CHNL_RX (chnl_rx[C_NUM_CHNL-1:0]),
.CHNL_RX_LAST (chnl_rx_last[C_NUM_CHNL-1:0]),
.CHNL_RX_LEN (chnl_rx_len[(C_NUM_CHNL*`SIG_CHNL_LENGTH_W)-1:0]),
.CHNL_RX_OFF (chnl_rx_off[(C_NUM_CHNL*`SIG_CHNL_OFFSET_W)-1:0]),
.CHNL_RX_DATA (chnl_rx_data[(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0]),
.CHNL_RX_DATA_VALID (chnl_rx_data_valid[C_NUM_CHNL-1:0]),
.CHNL_TX_ACK (chnl_tx_ack[C_NUM_CHNL-1:0]),
.CHNL_TX_DATA_REN (chnl_tx_data_ren[C_NUM_CHNL-1:0]),
// Inputs
.RX_ST_DATA (rx_st_data[C_PCI_DATA_WIDTH-1:0]),
.RX_ST_EOP (rx_st_eop[0:0]),
.RX_ST_SOP (rx_st_sop[0:0]),
.RX_ST_VALID (rx_st_valid[0:0]),
.RX_ST_EMPTY (rx_st_empty[0:0]),
.TX_ST_READY (tx_st_ready),
.TL_CFG_CTL (tl_cfg_ctl[`SIG_CFG_CTL_W-1:0]),
.TL_CFG_ADD (tl_cfg_add[`SIG_CFG_ADD_W-1:0]),
.TL_CFG_STS (tl_cfg_sts[`SIG_CFG_STS_W-1:0]),
.KO_CPL_SPC_HEADER (ko_cpl_spc_header[`SIG_KO_CPLH_W-1:0]),
.KO_CPL_SPC_DATA (ko_cpl_spc_data[`SIG_KO_CPLD_W-1:0]),
.APP_MSI_ACK (app_msi_ack),
.PLD_CLK (pld_clk),
.RESET_STATUS (reset_status),
.CHNL_RX_CLK (chnl_rx_clk[C_NUM_CHNL-1:0]),
.CHNL_RX_ACK (chnl_rx_ack[C_NUM_CHNL-1:0]),
.CHNL_RX_DATA_REN (chnl_rx_data_ren[C_NUM_CHNL-1:0]),
.CHNL_TX_CLK (chnl_tx_clk[C_NUM_CHNL-1:0]),
.CHNL_TX (chnl_tx[C_NUM_CHNL-1:0]),
.CHNL_TX_LAST (chnl_tx_last[C_NUM_CHNL-1:0]),
.CHNL_TX_LEN (chnl_tx_len[(C_NUM_CHNL*`SIG_CHNL_LENGTH_W)-1:0]),
.CHNL_TX_OFF (chnl_tx_off[(C_NUM_CHNL*`SIG_CHNL_OFFSET_W)-1:0]),
.CHNL_TX_DATA (chnl_tx_data[(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0]),
.CHNL_TX_DATA_VALID (chnl_tx_data_valid[C_NUM_CHNL-1:0]));
// -------------------- END RIFFA INSTANTAION --------------------
// -------------------- BEGIN USER CODE --------------------
genvar i;
generate
for (i = 0; i < C_NUM_CHNL; i = i + 1) begin : test_channels
// Instantiate and assign modules to RIFFA channels. Users should
// replace the chnl_tester instantiation with their own core.
chnl_tester
#(
.C_PCI_DATA_WIDTH(C_PCI_DATA_WIDTH)
)
chnl_tester_i
(
.CLK(chnl_clk),
.RST(chnl_reset), // chnl_reset includes riffa_endpoint resets
// Rx interface
.CHNL_RX_CLK(chnl_rx_clk[i]),
.CHNL_RX(chnl_rx[i]),
.CHNL_RX_ACK(chnl_rx_ack[i]),
.CHNL_RX_LAST(chnl_rx_last[i]),
.CHNL_RX_LEN(chnl_rx_len[`SIG_CHNL_LENGTH_W*i +:`SIG_CHNL_LENGTH_W]),
.CHNL_RX_OFF(chnl_rx_off[`SIG_CHNL_OFFSET_W*i +:`SIG_CHNL_OFFSET_W]),
.CHNL_RX_DATA(chnl_rx_data[C_PCI_DATA_WIDTH*i +:C_PCI_DATA_WIDTH]),
.CHNL_RX_DATA_VALID(chnl_rx_data_valid[i]),
.CHNL_RX_DATA_REN(chnl_rx_data_ren[i]),
// Tx interface
.CHNL_TX_CLK(chnl_tx_clk[i]),
.CHNL_TX(chnl_tx[i]),
.CHNL_TX_ACK(chnl_tx_ack[i]),
.CHNL_TX_LAST(chnl_tx_last[i]),
.CHNL_TX_LEN(chnl_tx_len[`SIG_CHNL_LENGTH_W*i +:`SIG_CHNL_LENGTH_W]),
.CHNL_TX_OFF(chnl_tx_off[`SIG_CHNL_OFFSET_W*i +:`SIG_CHNL_OFFSET_W]),
.CHNL_TX_DATA(chnl_tx_data[C_PCI_DATA_WIDTH*i +:C_PCI_DATA_WIDTH]),
.CHNL_TX_DATA_VALID(chnl_tx_data_valid[i]),
.CHNL_TX_DATA_REN(chnl_tx_data_ren[i])
);
end
endgenerate
// -------------------- END USER CODE --------------------
endmodule
|
module sky130_fd_sc_ls__dlygate4sd1_1 (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__dlygate4sd1 base (
.X(X),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
|
module sky130_fd_sc_ls__dlygate4sd1_1 (
X,
A
);
output X;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__dlygate4sd1 base (
.X(X),
.A(A)
);
endmodule
|
module Sincronizador(incambiarfuncion,incambiarsalida,inrst,inbtup,inbtdown,outcambiarfuncion,outcambiarsalida,outrst,outbtup,outbtdown,clk);
input wire incambiarfuncion,incambiarsalida,inrst,inbtup,inbtdown,clk;
output wire outcambiarfuncion,outcambiarsalida,outbtup,outbtdown,outrst;
Synchro S1 (
.dato(incambiarfuncion),
.clk(clk),
.ds(outcambiarfuncion)
);
Synchro S2 (
.dato(incambiarsalida),
.clk(clk),
.ds(outcambiarsalida)
);
Synchro S3 (
.dato(inrst),
.clk(clk),
.ds(outrst)
);
Synchro S4 (
.dato(inbtup),
.clk(clk),
.ds(outbtup)
);
Synchro S5 (
.dato(inbtdown),
.clk(clk),
.ds(outbtdown)
);
endmodule
|
module hps_sdram (
input wire pll_ref_clk, // pll_ref_clk.clk
input wire global_reset_n, // global_reset.reset_n
input wire soft_reset_n, // soft_reset.reset_n
output wire [14:0] mem_a, // memory.mem_a
output wire [2:0] mem_ba, // .mem_ba
output wire [0:0] mem_ck, // .mem_ck
output wire [0:0] mem_ck_n, // .mem_ck_n
output wire [0:0] mem_cke, // .mem_cke
output wire [0:0] mem_cs_n, // .mem_cs_n
output wire [3:0] mem_dm, // .mem_dm
output wire [0:0] mem_ras_n, // .mem_ras_n
output wire [0:0] mem_cas_n, // .mem_cas_n
output wire [0:0] mem_we_n, // .mem_we_n
output wire mem_reset_n, // .mem_reset_n
inout wire [31:0] mem_dq, // .mem_dq
inout wire [3:0] mem_dqs, // .mem_dqs
inout wire [3:0] mem_dqs_n, // .mem_dqs_n
output wire [0:0] mem_odt, // .mem_odt
input wire oct_rzqin // oct.rzqin
);
wire pll_afi_clk_clk; // pll:afi_clk -> [c0:afi_clk, p0:afi_clk]
wire pll_afi_half_clk_clk; // pll:afi_half_clk -> [c0:afi_half_clk, p0:afi_half_clk]
wire [3:0] p0_afi_afi_wlat; // p0:afi_wlat -> c0:afi_wlat
wire [0:0] p0_afi_afi_rdata_valid; // p0:afi_rdata_valid -> c0:afi_rdata_valid
wire p0_afi_afi_cal_success; // p0:afi_cal_success -> c0:afi_cal_success
wire [4:0] p0_afi_afi_rlat; // p0:afi_rlat -> c0:afi_rlat
wire [79:0] p0_afi_afi_rdata; // p0:afi_rdata -> c0:afi_rdata
wire p0_afi_afi_cal_fail; // p0:afi_cal_fail -> c0:afi_cal_fail
wire p0_afi_reset_reset; // p0:afi_reset_n -> c0:afi_reset_n
wire [1:0] c0_afi_afi_cs_n; // c0:afi_cs_n -> p0:afi_cs_n
wire [1:0] c0_afi_afi_cke; // c0:afi_cke -> p0:afi_cke
wire [0:0] c0_afi_afi_ras_n; // c0:afi_ras_n -> p0:afi_ras_n
wire [0:0] c0_afi_afi_mem_clk_disable; // c0:afi_mem_clk_disable -> p0:afi_mem_clk_disable
wire [9:0] c0_afi_afi_dm; // c0:afi_dm -> p0:afi_dm
wire [1:0] c0_afi_afi_odt; // c0:afi_odt -> p0:afi_odt
wire [19:0] c0_afi_afi_addr; // c0:afi_addr -> p0:afi_addr
wire [4:0] c0_afi_afi_rdata_en_full; // c0:afi_rdata_en_full -> p0:afi_rdata_en_full
wire [0:0] c0_afi_afi_we_n; // c0:afi_we_n -> p0:afi_we_n
wire [2:0] c0_afi_afi_ba; // c0:afi_ba -> p0:afi_ba
wire [79:0] c0_afi_afi_wdata; // c0:afi_wdata -> p0:afi_wdata
wire [4:0] c0_afi_afi_rdata_en; // c0:afi_rdata_en -> p0:afi_rdata_en
wire [0:0] c0_afi_afi_rst_n; // c0:afi_rst_n -> p0:afi_rst_n
wire [0:0] c0_afi_afi_cas_n; // c0:afi_cas_n -> p0:afi_cas_n
wire [4:0] c0_afi_afi_wdata_valid; // c0:afi_wdata_valid -> p0:afi_wdata_valid
wire [4:0] c0_afi_afi_dqs_burst; // c0:afi_dqs_burst -> p0:afi_dqs_burst
wire [7:0] c0_hard_phy_cfg_cfg_addlat; // c0:cfg_addlat -> p0:cfg_addlat
wire [7:0] c0_hard_phy_cfg_cfg_rowaddrwidth; // c0:cfg_rowaddrwidth -> p0:cfg_rowaddrwidth
wire [7:0] c0_hard_phy_cfg_cfg_csaddrwidth; // c0:cfg_csaddrwidth -> p0:cfg_csaddrwidth
wire [7:0] c0_hard_phy_cfg_cfg_devicewidth; // c0:cfg_devicewidth -> p0:cfg_devicewidth
wire [7:0] c0_hard_phy_cfg_cfg_interfacewidth; // c0:cfg_interfacewidth -> p0:cfg_interfacewidth
wire [7:0] c0_hard_phy_cfg_cfg_tcl; // c0:cfg_tcl -> p0:cfg_tcl
wire [7:0] c0_hard_phy_cfg_cfg_coladdrwidth; // c0:cfg_coladdrwidth -> p0:cfg_coladdrwidth
wire [15:0] c0_hard_phy_cfg_cfg_trefi; // c0:cfg_trefi -> p0:cfg_trefi
wire [23:0] c0_hard_phy_cfg_cfg_dramconfig; // c0:cfg_dramconfig -> p0:cfg_dramconfig
wire [7:0] c0_hard_phy_cfg_cfg_caswrlat; // c0:cfg_caswrlat -> p0:cfg_caswrlat
wire [7:0] c0_hard_phy_cfg_cfg_trfc; // c0:cfg_trfc -> p0:cfg_trfc
wire [7:0] c0_hard_phy_cfg_cfg_bankaddrwidth; // c0:cfg_bankaddrwidth -> p0:cfg_bankaddrwidth
wire [7:0] c0_hard_phy_cfg_cfg_twr; // c0:cfg_twr -> p0:cfg_twr
wire [7:0] c0_hard_phy_cfg_cfg_tmrd; // c0:cfg_tmrd -> p0:cfg_tmrd
wire p0_ctl_clk_clk; // p0:ctl_clk -> c0:ctl_clk
wire p0_ctl_reset_reset; // p0:ctl_reset_n -> c0:ctl_reset_n
wire p0_io_int_io_intaficalsuccess; // p0:io_intaficalsuccess -> c0:io_intaficalsuccess
wire p0_io_int_io_intaficalfail; // p0:io_intaficalfail -> c0:io_intaficalfail
wire [15:0] oct_oct_sharing_parallelterminationcontrol; // oct:parallelterminationcontrol -> p0:parallelterminationcontrol
wire [15:0] oct_oct_sharing_seriesterminationcontrol; // oct:seriesterminationcontrol -> p0:seriesterminationcontrol
wire pll_pll_sharing_pll_mem_phy_clk; // pll:pll_mem_phy_clk -> p0:pll_mem_phy_clk
wire pll_pll_sharing_pll_avl_clk; // pll:pll_avl_clk -> p0:pll_avl_clk
wire pll_pll_sharing_pll_avl_phy_clk; // pll:pll_avl_phy_clk -> p0:pll_avl_phy_clk
wire pll_pll_sharing_afi_phy_clk; // pll:afi_phy_clk -> p0:afi_phy_clk
wire pll_pll_sharing_pll_config_clk; // pll:pll_config_clk -> p0:pll_config_clk
wire pll_pll_sharing_pll_addr_cmd_clk; // pll:pll_addr_cmd_clk -> p0:pll_addr_cmd_clk
wire pll_pll_sharing_pll_mem_clk; // pll:pll_mem_clk -> p0:pll_mem_clk
wire pll_pll_sharing_pll_locked; // pll:pll_locked -> p0:pll_locked
wire pll_pll_sharing_pll_write_clk_pre_phy_clk; // pll:pll_write_clk_pre_phy_clk -> p0:pll_write_clk_pre_phy_clk
wire pll_pll_sharing_pll_write_clk; // pll:pll_write_clk -> p0:pll_write_clk
wire p0_dll_clk_clk; // p0:dll_clk -> dll:clk
wire p0_dll_sharing_dll_pll_locked; // p0:dll_pll_locked -> dll:dll_pll_locked
wire [6:0] dll_dll_sharing_dll_delayctrl; // dll:dll_delayctrl -> p0:dll_delayctrl
hps_sdram_pll pll (
.global_reset_n (global_reset_n), // global_reset.reset_n
.pll_ref_clk (pll_ref_clk), // pll_ref_clk.clk
.afi_clk (pll_afi_clk_clk), // afi_clk.clk
.afi_half_clk (pll_afi_half_clk_clk), // afi_half_clk.clk
.pll_mem_clk (pll_pll_sharing_pll_mem_clk), // pll_sharing.pll_mem_clk
.pll_write_clk (pll_pll_sharing_pll_write_clk), // .pll_write_clk
.pll_locked (pll_pll_sharing_pll_locked), // .pll_locked
.pll_write_clk_pre_phy_clk (pll_pll_sharing_pll_write_clk_pre_phy_clk), // .pll_write_clk_pre_phy_clk
.pll_addr_cmd_clk (pll_pll_sharing_pll_addr_cmd_clk), // .pll_addr_cmd_clk
.pll_avl_clk (pll_pll_sharing_pll_avl_clk), // .pll_avl_clk
.pll_config_clk (pll_pll_sharing_pll_config_clk), // .pll_config_clk
.pll_mem_phy_clk (pll_pll_sharing_pll_mem_phy_clk), // .pll_mem_phy_clk
.afi_phy_clk (pll_pll_sharing_afi_phy_clk), // .afi_phy_clk
.pll_avl_phy_clk (pll_pll_sharing_pll_avl_phy_clk) // .pll_avl_phy_clk
);
hps_sdram_p0 p0 (
.global_reset_n (global_reset_n), // global_reset.reset_n
.soft_reset_n (soft_reset_n), // soft_reset.reset_n
.afi_reset_n (p0_afi_reset_reset), // afi_reset.reset_n
.afi_reset_export_n (), // afi_reset_export.reset_n
.ctl_reset_n (p0_ctl_reset_reset), // ctl_reset.reset_n
.afi_clk (pll_afi_clk_clk), // afi_clk.clk
.afi_half_clk (pll_afi_half_clk_clk), // afi_half_clk.clk
.ctl_clk (p0_ctl_clk_clk), // ctl_clk.clk
.avl_clk (), // avl_clk.clk
.avl_reset_n (), // avl_reset.reset_n
.scc_clk (), // scc_clk.clk
.scc_reset_n (), // scc_reset.reset_n
.avl_address (), // avl.address
.avl_write (), // .write
.avl_writedata (), // .writedata
.avl_read (), // .read
.avl_readdata (), // .readdata
.avl_waitrequest (), // .waitrequest
.dll_clk (p0_dll_clk_clk), // dll_clk.clk
.afi_addr (c0_afi_afi_addr), // afi.afi_addr
.afi_ba (c0_afi_afi_ba), // .afi_ba
.afi_cke (c0_afi_afi_cke), // .afi_cke
.afi_cs_n (c0_afi_afi_cs_n), // .afi_cs_n
.afi_ras_n (c0_afi_afi_ras_n), // .afi_ras_n
.afi_we_n (c0_afi_afi_we_n), // .afi_we_n
.afi_cas_n (c0_afi_afi_cas_n), // .afi_cas_n
.afi_rst_n (c0_afi_afi_rst_n), // .afi_rst_n
.afi_odt (c0_afi_afi_odt), // .afi_odt
.afi_dqs_burst (c0_afi_afi_dqs_burst), // .afi_dqs_burst
.afi_wdata_valid (c0_afi_afi_wdata_valid), // .afi_wdata_valid
.afi_wdata (c0_afi_afi_wdata), // .afi_wdata
.afi_dm (c0_afi_afi_dm), // .afi_dm
.afi_rdata (p0_afi_afi_rdata), // .afi_rdata
.afi_rdata_en (c0_afi_afi_rdata_en), // .afi_rdata_en
.afi_rdata_en_full (c0_afi_afi_rdata_en_full), // .afi_rdata_en_full
.afi_rdata_valid (p0_afi_afi_rdata_valid), // .afi_rdata_valid
.afi_wlat (p0_afi_afi_wlat), // .afi_wlat
.afi_rlat (p0_afi_afi_rlat), // .afi_rlat
.afi_cal_success (p0_afi_afi_cal_success), // .afi_cal_success
.afi_cal_fail (p0_afi_afi_cal_fail), // .afi_cal_fail
.scc_data (), // scc.scc_data
.scc_dqs_ena (), // .scc_dqs_ena
.scc_dqs_io_ena (), // .scc_dqs_io_ena
.scc_dq_ena (), // .scc_dq_ena
.scc_dm_ena (), // .scc_dm_ena
.capture_strobe_tracking (), // .capture_strobe_tracking
.scc_upd (), // .scc_upd
.cfg_addlat (c0_hard_phy_cfg_cfg_addlat), // hard_phy_cfg.cfg_addlat
.cfg_bankaddrwidth (c0_hard_phy_cfg_cfg_bankaddrwidth), // .cfg_bankaddrwidth
.cfg_caswrlat (c0_hard_phy_cfg_cfg_caswrlat), // .cfg_caswrlat
.cfg_coladdrwidth (c0_hard_phy_cfg_cfg_coladdrwidth), // .cfg_coladdrwidth
.cfg_csaddrwidth (c0_hard_phy_cfg_cfg_csaddrwidth), // .cfg_csaddrwidth
.cfg_devicewidth (c0_hard_phy_cfg_cfg_devicewidth), // .cfg_devicewidth
.cfg_dramconfig (c0_hard_phy_cfg_cfg_dramconfig), // .cfg_dramconfig
.cfg_interfacewidth (c0_hard_phy_cfg_cfg_interfacewidth), // .cfg_interfacewidth
.cfg_rowaddrwidth (c0_hard_phy_cfg_cfg_rowaddrwidth), // .cfg_rowaddrwidth
.cfg_tcl (c0_hard_phy_cfg_cfg_tcl), // .cfg_tcl
.cfg_tmrd (c0_hard_phy_cfg_cfg_tmrd), // .cfg_tmrd
.cfg_trefi (c0_hard_phy_cfg_cfg_trefi), // .cfg_trefi
.cfg_trfc (c0_hard_phy_cfg_cfg_trfc), // .cfg_trfc
.cfg_twr (c0_hard_phy_cfg_cfg_twr), // .cfg_twr
.afi_mem_clk_disable (c0_afi_afi_mem_clk_disable), // afi_mem_clk_disable.afi_mem_clk_disable
.pll_mem_clk (pll_pll_sharing_pll_mem_clk), // pll_sharing.pll_mem_clk
.pll_write_clk (pll_pll_sharing_pll_write_clk), // .pll_write_clk
.pll_locked (pll_pll_sharing_pll_locked), // .pll_locked
.pll_write_clk_pre_phy_clk (pll_pll_sharing_pll_write_clk_pre_phy_clk), // .pll_write_clk_pre_phy_clk
.pll_addr_cmd_clk (pll_pll_sharing_pll_addr_cmd_clk), // .pll_addr_cmd_clk
.pll_avl_clk (pll_pll_sharing_pll_avl_clk), // .pll_avl_clk
.pll_config_clk (pll_pll_sharing_pll_config_clk), // .pll_config_clk
.pll_mem_phy_clk (pll_pll_sharing_pll_mem_phy_clk), // .pll_mem_phy_clk
.afi_phy_clk (pll_pll_sharing_afi_phy_clk), // .afi_phy_clk
.pll_avl_phy_clk (pll_pll_sharing_pll_avl_phy_clk), // .pll_avl_phy_clk
.dll_pll_locked (p0_dll_sharing_dll_pll_locked), // dll_sharing.dll_pll_locked
.dll_delayctrl (dll_dll_sharing_dll_delayctrl), // .dll_delayctrl
.seriesterminationcontrol (oct_oct_sharing_seriesterminationcontrol), // oct_sharing.seriesterminationcontrol
.parallelterminationcontrol (oct_oct_sharing_parallelterminationcontrol), // .parallelterminationcontrol
.mem_a (mem_a), // memory.mem_a
.mem_ba (mem_ba), // .mem_ba
.mem_ck (mem_ck), // .mem_ck
.mem_ck_n (mem_ck_n), // .mem_ck_n
.mem_cke (mem_cke), // .mem_cke
.mem_cs_n (mem_cs_n), // .mem_cs_n
.mem_dm (mem_dm), // .mem_dm
.mem_ras_n (mem_ras_n), // .mem_ras_n
.mem_cas_n (mem_cas_n), // .mem_cas_n
.mem_we_n (mem_we_n), // .mem_we_n
.mem_reset_n (mem_reset_n), // .mem_reset_n
.mem_dq (mem_dq), // .mem_dq
.mem_dqs (mem_dqs), // .mem_dqs
.mem_dqs_n (mem_dqs_n), // .mem_dqs_n
.mem_odt (mem_odt), // .mem_odt
.io_intaficalfail (p0_io_int_io_intaficalfail), // io_int.io_intaficalfail
.io_intaficalsuccess (p0_io_int_io_intaficalsuccess), // .io_intaficalsuccess
.csr_soft_reset_req (1'b0), // (terminated)
.io_intaddrdout (64'b0000000000000000000000000000000000000000000000000000000000000000), // (terminated)
.io_intbadout (12'b000000000000), // (terminated)
.io_intcasndout (4'b0000), // (terminated)
.io_intckdout (4'b0000), // (terminated)
.io_intckedout (8'b00000000), // (terminated)
.io_intckndout (4'b0000), // (terminated)
.io_intcsndout (8'b00000000), // (terminated)
.io_intdmdout (20'b00000000000000000000), // (terminated)
.io_intdqdin (), // (terminated)
.io_intdqdout (180'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000), // (terminated)
.io_intdqoe (90'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000), // (terminated)
.io_intdqsbdout (20'b00000000000000000000), // (terminated)
.io_intdqsboe (10'b0000000000), // (terminated)
.io_intdqsdout (20'b00000000000000000000), // (terminated)
.io_intdqslogicdqsena (10'b0000000000), // (terminated)
.io_intdqslogicfiforeset (5'b00000), // (terminated)
.io_intdqslogicincrdataen (10'b0000000000), // (terminated)
.io_intdqslogicincwrptr (10'b0000000000), // (terminated)
.io_intdqslogicoct (10'b0000000000), // (terminated)
.io_intdqslogicrdatavalid (), // (terminated)
.io_intdqslogicreadlatency (25'b0000000000000000000000000), // (terminated)
.io_intdqsoe (10'b0000000000), // (terminated)
.io_intodtdout (8'b00000000), // (terminated)
.io_intrasndout (4'b0000), // (terminated)
.io_intresetndout (4'b0000), // (terminated)
.io_intwendout (4'b0000), // (terminated)
.io_intafirlat (), // (terminated)
.io_intafiwlat () // (terminated)
);
altera_mem_if_hhp_qseq_synth_top #(
.MEM_IF_DM_WIDTH (4),
.MEM_IF_DQS_WIDTH (4),
.MEM_IF_CS_WIDTH (1),
.MEM_IF_DQ_WIDTH (32)
) seq (
);
altera_mem_if_hard_memory_controller_top_cyclonev #(
.MEM_IF_DQS_WIDTH (4),
.MEM_IF_CS_WIDTH (1),
.MEM_IF_CHIP_BITS (1),
.MEM_IF_CLK_PAIR_COUNT (1),
.CSR_ADDR_WIDTH (10),
.CSR_DATA_WIDTH (8),
.CSR_BE_WIDTH (1),
.AVL_ADDR_WIDTH (27),
.AVL_DATA_WIDTH (64),
.AVL_SIZE_WIDTH (3),
.AVL_DATA_WIDTH_PORT_0 (1),
.AVL_ADDR_WIDTH_PORT_0 (1),
.AVL_NUM_SYMBOLS_PORT_0 (1),
.LSB_WFIFO_PORT_0 (5),
.MSB_WFIFO_PORT_0 (5),
.LSB_RFIFO_PORT_0 (5),
.MSB_RFIFO_PORT_0 (5),
.AVL_DATA_WIDTH_PORT_1 (1),
.AVL_ADDR_WIDTH_PORT_1 (1),
.AVL_NUM_SYMBOLS_PORT_1 (1),
.LSB_WFIFO_PORT_1 (5),
.MSB_WFIFO_PORT_1 (5),
.LSB_RFIFO_PORT_1 (5),
.MSB_RFIFO_PORT_1 (5),
.AVL_DATA_WIDTH_PORT_2 (1),
.AVL_ADDR_WIDTH_PORT_2 (1),
.AVL_NUM_SYMBOLS_PORT_2 (1),
.LSB_WFIFO_PORT_2 (5),
.MSB_WFIFO_PORT_2 (5),
.LSB_RFIFO_PORT_2 (5),
.MSB_RFIFO_PORT_2 (5),
.AVL_DATA_WIDTH_PORT_3 (1),
.AVL_ADDR_WIDTH_PORT_3 (1),
.AVL_NUM_SYMBOLS_PORT_3 (1),
.LSB_WFIFO_PORT_3 (5),
.MSB_WFIFO_PORT_3 (5),
.LSB_RFIFO_PORT_3 (5),
.MSB_RFIFO_PORT_3 (5),
.AVL_DATA_WIDTH_PORT_4 (1),
.AVL_ADDR_WIDTH_PORT_4 (1),
.AVL_NUM_SYMBOLS_PORT_4 (1),
.LSB_WFIFO_PORT_4 (5),
.MSB_WFIFO_PORT_4 (5),
.LSB_RFIFO_PORT_4 (5),
.MSB_RFIFO_PORT_4 (5),
.AVL_DATA_WIDTH_PORT_5 (1),
.AVL_ADDR_WIDTH_PORT_5 (1),
.AVL_NUM_SYMBOLS_PORT_5 (1),
.LSB_WFIFO_PORT_5 (5),
.MSB_WFIFO_PORT_5 (5),
.LSB_RFIFO_PORT_5 (5),
.MSB_RFIFO_PORT_5 (5),
.ENUM_ATTR_COUNTER_ONE_RESET ("DISABLED"),
.ENUM_ATTR_COUNTER_ZERO_RESET ("DISABLED"),
.ENUM_ATTR_STATIC_CONFIG_VALID ("DISABLED"),
.ENUM_AUTO_PCH_ENABLE_0 ("DISABLED"),
.ENUM_AUTO_PCH_ENABLE_1 ("DISABLED"),
.ENUM_AUTO_PCH_ENABLE_2 ("DISABLED"),
.ENUM_AUTO_PCH_ENABLE_3 ("DISABLED"),
.ENUM_AUTO_PCH_ENABLE_4 ("DISABLED"),
.ENUM_AUTO_PCH_ENABLE_5 ("DISABLED"),
.ENUM_CAL_REQ ("DISABLED"),
.ENUM_CFG_BURST_LENGTH ("BL_8"),
.ENUM_CFG_INTERFACE_WIDTH ("DWIDTH_32"),
.ENUM_CFG_SELF_RFSH_EXIT_CYCLES ("SELF_RFSH_EXIT_CYCLES_512"),
.ENUM_CFG_STARVE_LIMIT ("STARVE_LIMIT_10"),
.ENUM_CFG_TYPE ("DDR3"),
.ENUM_CLOCK_OFF_0 ("DISABLED"),
.ENUM_CLOCK_OFF_1 ("DISABLED"),
.ENUM_CLOCK_OFF_2 ("DISABLED"),
.ENUM_CLOCK_OFF_3 ("DISABLED"),
.ENUM_CLOCK_OFF_4 ("DISABLED"),
.ENUM_CLOCK_OFF_5 ("DISABLED"),
.ENUM_CLR_INTR ("NO_CLR_INTR"),
.ENUM_CMD_PORT_IN_USE_0 ("FALSE"),
.ENUM_CMD_PORT_IN_USE_1 ("FALSE"),
.ENUM_CMD_PORT_IN_USE_2 ("FALSE"),
.ENUM_CMD_PORT_IN_USE_3 ("FALSE"),
.ENUM_CMD_PORT_IN_USE_4 ("FALSE"),
.ENUM_CMD_PORT_IN_USE_5 ("FALSE"),
.ENUM_CPORT0_RDY_ALMOST_FULL ("NOT_FULL"),
.ENUM_CPORT0_RFIFO_MAP ("FIFO_0"),
.ENUM_CPORT0_TYPE ("DISABLE"),
.ENUM_CPORT0_WFIFO_MAP ("FIFO_0"),
.ENUM_CPORT1_RDY_ALMOST_FULL ("NOT_FULL"),
.ENUM_CPORT1_RFIFO_MAP ("FIFO_0"),
.ENUM_CPORT1_TYPE ("DISABLE"),
.ENUM_CPORT1_WFIFO_MAP ("FIFO_0"),
.ENUM_CPORT2_RDY_ALMOST_FULL ("NOT_FULL"),
.ENUM_CPORT2_RFIFO_MAP ("FIFO_0"),
.ENUM_CPORT2_TYPE ("DISABLE"),
.ENUM_CPORT2_WFIFO_MAP ("FIFO_0"),
.ENUM_CPORT3_RDY_ALMOST_FULL ("NOT_FULL"),
.ENUM_CPORT3_RFIFO_MAP ("FIFO_0"),
.ENUM_CPORT3_TYPE ("DISABLE"),
.ENUM_CPORT3_WFIFO_MAP ("FIFO_0"),
.ENUM_CPORT4_RDY_ALMOST_FULL ("NOT_FULL"),
.ENUM_CPORT4_RFIFO_MAP ("FIFO_0"),
.ENUM_CPORT4_TYPE ("DISABLE"),
.ENUM_CPORT4_WFIFO_MAP ("FIFO_0"),
.ENUM_CPORT5_RDY_ALMOST_FULL ("NOT_FULL"),
.ENUM_CPORT5_RFIFO_MAP ("FIFO_0"),
.ENUM_CPORT5_TYPE ("DISABLE"),
.ENUM_CPORT5_WFIFO_MAP ("FIFO_0"),
.ENUM_CTL_ADDR_ORDER ("CHIP_ROW_BANK_COL"),
.ENUM_CTL_ECC_ENABLED ("CTL_ECC_DISABLED"),
.ENUM_CTL_ECC_RMW_ENABLED ("CTL_ECC_RMW_DISABLED"),
.ENUM_CTL_REGDIMM_ENABLED ("REGDIMM_DISABLED"),
.ENUM_CTL_USR_REFRESH ("CTL_USR_REFRESH_DISABLED"),
.ENUM_CTRL_WIDTH ("DATA_WIDTH_64_BIT"),
.ENUM_DELAY_BONDING ("BONDING_LATENCY_0"),
.ENUM_DFX_BYPASS_ENABLE ("DFX_BYPASS_DISABLED"),
.ENUM_DISABLE_MERGING ("MERGING_ENABLED"),
.ENUM_ECC_DQ_WIDTH ("ECC_DQ_WIDTH_0"),
.ENUM_ENABLE_ATPG ("DISABLED"),
.ENUM_ENABLE_BONDING_0 ("DISABLED"),
.ENUM_ENABLE_BONDING_1 ("DISABLED"),
.ENUM_ENABLE_BONDING_2 ("DISABLED"),
.ENUM_ENABLE_BONDING_3 ("DISABLED"),
.ENUM_ENABLE_BONDING_4 ("DISABLED"),
.ENUM_ENABLE_BONDING_5 ("DISABLED"),
.ENUM_ENABLE_BONDING_WRAPBACK ("DISABLED"),
.ENUM_ENABLE_DQS_TRACKING ("ENABLED"),
.ENUM_ENABLE_ECC_CODE_OVERWRITES ("DISABLED"),
.ENUM_ENABLE_FAST_EXIT_PPD ("DISABLED"),
.ENUM_ENABLE_INTR ("DISABLED"),
.ENUM_ENABLE_NO_DM ("DISABLED"),
.ENUM_ENABLE_PIPELINEGLOBAL ("DISABLED"),
.ENUM_GANGED_ARF ("DISABLED"),
.ENUM_GEN_DBE ("GEN_DBE_DISABLED"),
.ENUM_GEN_SBE ("GEN_SBE_DISABLED"),
.ENUM_INC_SYNC ("FIFO_SET_2"),
.ENUM_LOCAL_IF_CS_WIDTH ("ADDR_WIDTH_0"),
.ENUM_MASK_CORR_DROPPED_INTR ("DISABLED"),
.ENUM_MASK_DBE_INTR ("DISABLED"),
.ENUM_MASK_SBE_INTR ("DISABLED"),
.ENUM_MEM_IF_AL ("AL_0"),
.ENUM_MEM_IF_BANKADDR_WIDTH ("ADDR_WIDTH_3"),
.ENUM_MEM_IF_BURSTLENGTH ("MEM_IF_BURSTLENGTH_8"),
.ENUM_MEM_IF_COLADDR_WIDTH ("ADDR_WIDTH_10"),
.ENUM_MEM_IF_CS_PER_RANK ("MEM_IF_CS_PER_RANK_1"),
.ENUM_MEM_IF_CS_WIDTH ("MEM_IF_CS_WIDTH_1"),
.ENUM_MEM_IF_DQ_PER_CHIP ("MEM_IF_DQ_PER_CHIP_8"),
.ENUM_MEM_IF_DQS_WIDTH ("DQS_WIDTH_4"),
.ENUM_MEM_IF_DWIDTH ("MEM_IF_DWIDTH_32"),
.ENUM_MEM_IF_MEMTYPE ("DDR3_SDRAM"),
.ENUM_MEM_IF_ROWADDR_WIDTH ("ADDR_WIDTH_15"),
.ENUM_MEM_IF_SPEEDBIN ("DDR3_1600_8_8_8"),
.ENUM_MEM_IF_TCCD ("TCCD_4"),
.ENUM_MEM_IF_TCL ("TCL_11"),
.ENUM_MEM_IF_TCWL ("TCWL_8"),
.ENUM_MEM_IF_TFAW ("TFAW_12"),
.ENUM_MEM_IF_TMRD ("TMRD_4"),
.ENUM_MEM_IF_TRAS ("TRAS_14"),
.ENUM_MEM_IF_TRC ("TRC_20"),
.ENUM_MEM_IF_TRCD ("TRCD_6"),
.ENUM_MEM_IF_TRP ("TRP_6"),
.ENUM_MEM_IF_TRRD ("TRRD_3"),
.ENUM_MEM_IF_TRTP ("TRTP_3"),
.ENUM_MEM_IF_TWR ("TWR_6"),
.ENUM_MEM_IF_TWTR ("TWTR_4"),
.ENUM_MMR_CFG_MEM_BL ("MP_BL_8"),
.ENUM_OUTPUT_REGD ("DISABLED"),
.ENUM_PDN_EXIT_CYCLES ("SLOW_EXIT"),
.ENUM_PORT0_WIDTH ("PORT_32_BIT"),
.ENUM_PORT1_WIDTH ("PORT_32_BIT"),
.ENUM_PORT2_WIDTH ("PORT_32_BIT"),
.ENUM_PORT3_WIDTH ("PORT_32_BIT"),
.ENUM_PORT4_WIDTH ("PORT_32_BIT"),
.ENUM_PORT5_WIDTH ("PORT_32_BIT"),
.ENUM_PRIORITY_0_0 ("WEIGHT_0"),
.ENUM_PRIORITY_0_1 ("WEIGHT_0"),
.ENUM_PRIORITY_0_2 ("WEIGHT_0"),
.ENUM_PRIORITY_0_3 ("WEIGHT_0"),
.ENUM_PRIORITY_0_4 ("WEIGHT_0"),
.ENUM_PRIORITY_0_5 ("WEIGHT_0"),
.ENUM_PRIORITY_1_0 ("WEIGHT_0"),
.ENUM_PRIORITY_1_1 ("WEIGHT_0"),
.ENUM_PRIORITY_1_2 ("WEIGHT_0"),
.ENUM_PRIORITY_1_3 ("WEIGHT_0"),
.ENUM_PRIORITY_1_4 ("WEIGHT_0"),
.ENUM_PRIORITY_1_5 ("WEIGHT_0"),
.ENUM_PRIORITY_2_0 ("WEIGHT_0"),
.ENUM_PRIORITY_2_1 ("WEIGHT_0"),
.ENUM_PRIORITY_2_2 ("WEIGHT_0"),
.ENUM_PRIORITY_2_3 ("WEIGHT_0"),
.ENUM_PRIORITY_2_4 ("WEIGHT_0"),
.ENUM_PRIORITY_2_5 ("WEIGHT_0"),
.ENUM_PRIORITY_3_0 ("WEIGHT_0"),
.ENUM_PRIORITY_3_1 ("WEIGHT_0"),
.ENUM_PRIORITY_3_2 ("WEIGHT_0"),
.ENUM_PRIORITY_3_3 ("WEIGHT_0"),
.ENUM_PRIORITY_3_4 ("WEIGHT_0"),
.ENUM_PRIORITY_3_5 ("WEIGHT_0"),
.ENUM_PRIORITY_4_0 ("WEIGHT_0"),
.ENUM_PRIORITY_4_1 ("WEIGHT_0"),
.ENUM_PRIORITY_4_2 ("WEIGHT_0"),
.ENUM_PRIORITY_4_3 ("WEIGHT_0"),
.ENUM_PRIORITY_4_4 ("WEIGHT_0"),
.ENUM_PRIORITY_4_5 ("WEIGHT_0"),
.ENUM_PRIORITY_5_0 ("WEIGHT_0"),
.ENUM_PRIORITY_5_1 ("WEIGHT_0"),
.ENUM_PRIORITY_5_2 ("WEIGHT_0"),
.ENUM_PRIORITY_5_3 ("WEIGHT_0"),
.ENUM_PRIORITY_5_4 ("WEIGHT_0"),
.ENUM_PRIORITY_5_5 ("WEIGHT_0"),
.ENUM_PRIORITY_6_0 ("WEIGHT_0"),
.ENUM_PRIORITY_6_1 ("WEIGHT_0"),
.ENUM_PRIORITY_6_2 ("WEIGHT_0"),
.ENUM_PRIORITY_6_3 ("WEIGHT_0"),
.ENUM_PRIORITY_6_4 ("WEIGHT_0"),
.ENUM_PRIORITY_6_5 ("WEIGHT_0"),
.ENUM_PRIORITY_7_0 ("WEIGHT_0"),
.ENUM_PRIORITY_7_1 ("WEIGHT_0"),
.ENUM_PRIORITY_7_2 ("WEIGHT_0"),
.ENUM_PRIORITY_7_3 ("WEIGHT_0"),
.ENUM_PRIORITY_7_4 ("WEIGHT_0"),
.ENUM_PRIORITY_7_5 ("WEIGHT_0"),
.ENUM_RCFG_STATIC_WEIGHT_0 ("WEIGHT_0"),
.ENUM_RCFG_STATIC_WEIGHT_1 ("WEIGHT_0"),
.ENUM_RCFG_STATIC_WEIGHT_2 ("WEIGHT_0"),
.ENUM_RCFG_STATIC_WEIGHT_3 ("WEIGHT_0"),
.ENUM_RCFG_STATIC_WEIGHT_4 ("WEIGHT_0"),
.ENUM_RCFG_STATIC_WEIGHT_5 ("WEIGHT_0"),
.ENUM_RCFG_USER_PRIORITY_0 ("PRIORITY_1"),
.ENUM_RCFG_USER_PRIORITY_1 ("PRIORITY_1"),
.ENUM_RCFG_USER_PRIORITY_2 ("PRIORITY_1"),
.ENUM_RCFG_USER_PRIORITY_3 ("PRIORITY_1"),
.ENUM_RCFG_USER_PRIORITY_4 ("PRIORITY_1"),
.ENUM_RCFG_USER_PRIORITY_5 ("PRIORITY_1"),
.ENUM_RD_DWIDTH_0 ("DWIDTH_0"),
.ENUM_RD_DWIDTH_1 ("DWIDTH_0"),
.ENUM_RD_DWIDTH_2 ("DWIDTH_0"),
.ENUM_RD_DWIDTH_3 ("DWIDTH_0"),
.ENUM_RD_DWIDTH_4 ("DWIDTH_0"),
.ENUM_RD_DWIDTH_5 ("DWIDTH_0"),
.ENUM_RD_FIFO_IN_USE_0 ("FALSE"),
.ENUM_RD_FIFO_IN_USE_1 ("FALSE"),
.ENUM_RD_FIFO_IN_USE_2 ("FALSE"),
.ENUM_RD_FIFO_IN_USE_3 ("FALSE"),
.ENUM_RD_PORT_INFO_0 ("USE_NO"),
.ENUM_RD_PORT_INFO_1 ("USE_NO"),
.ENUM_RD_PORT_INFO_2 ("USE_NO"),
.ENUM_RD_PORT_INFO_3 ("USE_NO"),
.ENUM_RD_PORT_INFO_4 ("USE_NO"),
.ENUM_RD_PORT_INFO_5 ("USE_NO"),
.ENUM_READ_ODT_CHIP ("ODT_DISABLED"),
.ENUM_REORDER_DATA ("DATA_REORDERING"),
.ENUM_RFIFO0_CPORT_MAP ("CMD_PORT_0"),
.ENUM_RFIFO1_CPORT_MAP ("CMD_PORT_0"),
.ENUM_RFIFO2_CPORT_MAP ("CMD_PORT_0"),
.ENUM_RFIFO3_CPORT_MAP ("CMD_PORT_0"),
.ENUM_SINGLE_READY_0 ("CONCATENATE_RDY"),
.ENUM_SINGLE_READY_1 ("CONCATENATE_RDY"),
.ENUM_SINGLE_READY_2 ("CONCATENATE_RDY"),
.ENUM_SINGLE_READY_3 ("CONCATENATE_RDY"),
.ENUM_STATIC_WEIGHT_0 ("WEIGHT_0"),
.ENUM_STATIC_WEIGHT_1 ("WEIGHT_0"),
.ENUM_STATIC_WEIGHT_2 ("WEIGHT_0"),
.ENUM_STATIC_WEIGHT_3 ("WEIGHT_0"),
.ENUM_STATIC_WEIGHT_4 ("WEIGHT_0"),
.ENUM_STATIC_WEIGHT_5 ("WEIGHT_0"),
.ENUM_SYNC_MODE_0 ("ASYNCHRONOUS"),
.ENUM_SYNC_MODE_1 ("ASYNCHRONOUS"),
.ENUM_SYNC_MODE_2 ("ASYNCHRONOUS"),
.ENUM_SYNC_MODE_3 ("ASYNCHRONOUS"),
.ENUM_SYNC_MODE_4 ("ASYNCHRONOUS"),
.ENUM_SYNC_MODE_5 ("ASYNCHRONOUS"),
.ENUM_TEST_MODE ("NORMAL_MODE"),
.ENUM_THLD_JAR1_0 ("THRESHOLD_32"),
.ENUM_THLD_JAR1_1 ("THRESHOLD_32"),
.ENUM_THLD_JAR1_2 ("THRESHOLD_32"),
.ENUM_THLD_JAR1_3 ("THRESHOLD_32"),
.ENUM_THLD_JAR1_4 ("THRESHOLD_32"),
.ENUM_THLD_JAR1_5 ("THRESHOLD_32"),
.ENUM_THLD_JAR2_0 ("THRESHOLD_16"),
.ENUM_THLD_JAR2_1 ("THRESHOLD_16"),
.ENUM_THLD_JAR2_2 ("THRESHOLD_16"),
.ENUM_THLD_JAR2_3 ("THRESHOLD_16"),
.ENUM_THLD_JAR2_4 ("THRESHOLD_16"),
.ENUM_THLD_JAR2_5 ("THRESHOLD_16"),
.ENUM_USE_ALMOST_EMPTY_0 ("EMPTY"),
.ENUM_USE_ALMOST_EMPTY_1 ("EMPTY"),
.ENUM_USE_ALMOST_EMPTY_2 ("EMPTY"),
.ENUM_USE_ALMOST_EMPTY_3 ("EMPTY"),
.ENUM_USER_ECC_EN ("DISABLE"),
.ENUM_USER_PRIORITY_0 ("PRIORITY_1"),
.ENUM_USER_PRIORITY_1 ("PRIORITY_1"),
.ENUM_USER_PRIORITY_2 ("PRIORITY_1"),
.ENUM_USER_PRIORITY_3 ("PRIORITY_1"),
.ENUM_USER_PRIORITY_4 ("PRIORITY_1"),
.ENUM_USER_PRIORITY_5 ("PRIORITY_1"),
.ENUM_WFIFO0_CPORT_MAP ("CMD_PORT_0"),
.ENUM_WFIFO0_RDY_ALMOST_FULL ("NOT_FULL"),
.ENUM_WFIFO1_CPORT_MAP ("CMD_PORT_0"),
.ENUM_WFIFO1_RDY_ALMOST_FULL ("NOT_FULL"),
.ENUM_WFIFO2_CPORT_MAP ("CMD_PORT_0"),
.ENUM_WFIFO2_RDY_ALMOST_FULL ("NOT_FULL"),
.ENUM_WFIFO3_CPORT_MAP ("CMD_PORT_0"),
.ENUM_WFIFO3_RDY_ALMOST_FULL ("NOT_FULL"),
.ENUM_WR_DWIDTH_0 ("DWIDTH_0"),
.ENUM_WR_DWIDTH_1 ("DWIDTH_0"),
.ENUM_WR_DWIDTH_2 ("DWIDTH_0"),
.ENUM_WR_DWIDTH_3 ("DWIDTH_0"),
.ENUM_WR_DWIDTH_4 ("DWIDTH_0"),
.ENUM_WR_DWIDTH_5 ("DWIDTH_0"),
.ENUM_WR_FIFO_IN_USE_0 ("FALSE"),
.ENUM_WR_FIFO_IN_USE_1 ("FALSE"),
.ENUM_WR_FIFO_IN_USE_2 ("FALSE"),
.ENUM_WR_FIFO_IN_USE_3 ("FALSE"),
.ENUM_WR_PORT_INFO_0 ("USE_NO"),
.ENUM_WR_PORT_INFO_1 ("USE_NO"),
.ENUM_WR_PORT_INFO_2 ("USE_NO"),
.ENUM_WR_PORT_INFO_3 ("USE_NO"),
.ENUM_WR_PORT_INFO_4 ("USE_NO"),
.ENUM_WR_PORT_INFO_5 ("USE_NO"),
.ENUM_WRITE_ODT_CHIP ("WRITE_CHIP0_ODT0_CHIP1"),
.INTG_MEM_AUTO_PD_CYCLES (0),
.INTG_CYC_TO_RLD_JARS_0 (1),
.INTG_CYC_TO_RLD_JARS_1 (1),
.INTG_CYC_TO_RLD_JARS_2 (1),
.INTG_CYC_TO_RLD_JARS_3 (1),
.INTG_CYC_TO_RLD_JARS_4 (1),
.INTG_CYC_TO_RLD_JARS_5 (1),
.INTG_EXTRA_CTL_CLK_ACT_TO_ACT (0),
.INTG_EXTRA_CTL_CLK_ACT_TO_ACT_DIFF_BANK (0),
.INTG_EXTRA_CTL_CLK_ACT_TO_PCH (0),
.INTG_EXTRA_CTL_CLK_ACT_TO_RDWR (0),
.INTG_EXTRA_CTL_CLK_ARF_PERIOD (0),
.INTG_EXTRA_CTL_CLK_ARF_TO_VALID (0),
.INTG_EXTRA_CTL_CLK_FOUR_ACT_TO_ACT (0),
.INTG_EXTRA_CTL_CLK_PCH_ALL_TO_VALID (0),
.INTG_EXTRA_CTL_CLK_PCH_TO_VALID (0),
.INTG_EXTRA_CTL_CLK_PDN_PERIOD (0),
.INTG_EXTRA_CTL_CLK_PDN_TO_VALID (0),
.INTG_EXTRA_CTL_CLK_RD_AP_TO_VALID (0),
.INTG_EXTRA_CTL_CLK_RD_TO_PCH (0),
.INTG_EXTRA_CTL_CLK_RD_TO_RD (0),
.INTG_EXTRA_CTL_CLK_RD_TO_RD_DIFF_CHIP (0),
.INTG_EXTRA_CTL_CLK_RD_TO_WR (2),
.INTG_EXTRA_CTL_CLK_RD_TO_WR_BC (2),
.INTG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP (2),
.INTG_EXTRA_CTL_CLK_SRF_TO_VALID (0),
.INTG_EXTRA_CTL_CLK_SRF_TO_ZQ_CAL (0),
.INTG_EXTRA_CTL_CLK_WR_AP_TO_VALID (0),
.INTG_EXTRA_CTL_CLK_WR_TO_PCH (0),
.INTG_EXTRA_CTL_CLK_WR_TO_RD (3),
.INTG_EXTRA_CTL_CLK_WR_TO_RD_BC (3),
.INTG_EXTRA_CTL_CLK_WR_TO_RD_DIFF_CHIP (3),
.INTG_EXTRA_CTL_CLK_WR_TO_WR (0),
.INTG_EXTRA_CTL_CLK_WR_TO_WR_DIFF_CHIP (0),
.INTG_MEM_IF_TREFI (3120),
.INTG_MEM_IF_TRFC (104),
.INTG_RCFG_SUM_WT_PRIORITY_0 (0),
.INTG_RCFG_SUM_WT_PRIORITY_1 (0),
.INTG_RCFG_SUM_WT_PRIORITY_2 (0),
.INTG_RCFG_SUM_WT_PRIORITY_3 (0),
.INTG_RCFG_SUM_WT_PRIORITY_4 (0),
.INTG_RCFG_SUM_WT_PRIORITY_5 (0),
.INTG_RCFG_SUM_WT_PRIORITY_6 (0),
.INTG_RCFG_SUM_WT_PRIORITY_7 (0),
.INTG_SUM_WT_PRIORITY_0 (0),
.INTG_SUM_WT_PRIORITY_1 (0),
.INTG_SUM_WT_PRIORITY_2 (0),
.INTG_SUM_WT_PRIORITY_3 (0),
.INTG_SUM_WT_PRIORITY_4 (0),
.INTG_SUM_WT_PRIORITY_5 (0),
.INTG_SUM_WT_PRIORITY_6 (0),
.INTG_SUM_WT_PRIORITY_7 (0),
.INTG_POWER_SAVING_EXIT_CYCLES (5),
.INTG_MEM_CLK_ENTRY_CYCLES (10),
.ENUM_ENABLE_BURST_INTERRUPT ("DISABLED"),
.ENUM_ENABLE_BURST_TERMINATE ("DISABLED"),
.AFI_RATE_RATIO (1),
.AFI_ADDR_WIDTH (15),
.AFI_BANKADDR_WIDTH (3),
.AFI_CONTROL_WIDTH (1),
.AFI_CS_WIDTH (1),
.AFI_DM_WIDTH (8),
.AFI_DQ_WIDTH (64),
.AFI_ODT_WIDTH (1),
.AFI_WRITE_DQS_WIDTH (4),
.AFI_RLAT_WIDTH (6),
.AFI_WLAT_WIDTH (6),
.HARD_PHY (1)
) c0 (
.afi_clk (pll_afi_clk_clk), // afi_clk.clk
.afi_reset_n (p0_afi_reset_reset), // afi_reset.reset_n
.ctl_reset_n (p0_ctl_reset_reset), // ctl_reset.reset_n
.afi_half_clk (pll_afi_half_clk_clk), // afi_half_clk.clk
.ctl_clk (p0_ctl_clk_clk), // ctl_clk.clk
.local_init_done (), // status.local_init_done
.local_cal_success (), // .local_cal_success
.local_cal_fail (), // .local_cal_fail
.afi_addr (c0_afi_afi_addr), // afi.afi_addr
.afi_ba (c0_afi_afi_ba), // .afi_ba
.afi_cke (c0_afi_afi_cke), // .afi_cke
.afi_cs_n (c0_afi_afi_cs_n), // .afi_cs_n
.afi_ras_n (c0_afi_afi_ras_n), // .afi_ras_n
.afi_we_n (c0_afi_afi_we_n), // .afi_we_n
.afi_cas_n (c0_afi_afi_cas_n), // .afi_cas_n
.afi_rst_n (c0_afi_afi_rst_n), // .afi_rst_n
.afi_odt (c0_afi_afi_odt), // .afi_odt
.afi_mem_clk_disable (c0_afi_afi_mem_clk_disable), // .afi_mem_clk_disable
.afi_init_req (), // .afi_init_req
.afi_cal_req (), // .afi_cal_req
.afi_seq_busy (), // .afi_seq_busy
.afi_ctl_refresh_done (), // .afi_ctl_refresh_done
.afi_ctl_long_idle (), // .afi_ctl_long_idle
.afi_dqs_burst (c0_afi_afi_dqs_burst), // .afi_dqs_burst
.afi_wdata_valid (c0_afi_afi_wdata_valid), // .afi_wdata_valid
.afi_wdata (c0_afi_afi_wdata), // .afi_wdata
.afi_dm (c0_afi_afi_dm), // .afi_dm
.afi_rdata (p0_afi_afi_rdata), // .afi_rdata
.afi_rdata_en (c0_afi_afi_rdata_en), // .afi_rdata_en
.afi_rdata_en_full (c0_afi_afi_rdata_en_full), // .afi_rdata_en_full
.afi_rdata_valid (p0_afi_afi_rdata_valid), // .afi_rdata_valid
.afi_wlat (p0_afi_afi_wlat), // .afi_wlat
.afi_rlat (p0_afi_afi_rlat), // .afi_rlat
.afi_cal_success (p0_afi_afi_cal_success), // .afi_cal_success
.afi_cal_fail (p0_afi_afi_cal_fail), // .afi_cal_fail
.cfg_addlat (c0_hard_phy_cfg_cfg_addlat), // hard_phy_cfg.cfg_addlat
.cfg_bankaddrwidth (c0_hard_phy_cfg_cfg_bankaddrwidth), // .cfg_bankaddrwidth
.cfg_caswrlat (c0_hard_phy_cfg_cfg_caswrlat), // .cfg_caswrlat
.cfg_coladdrwidth (c0_hard_phy_cfg_cfg_coladdrwidth), // .cfg_coladdrwidth
.cfg_csaddrwidth (c0_hard_phy_cfg_cfg_csaddrwidth), // .cfg_csaddrwidth
.cfg_devicewidth (c0_hard_phy_cfg_cfg_devicewidth), // .cfg_devicewidth
.cfg_dramconfig (c0_hard_phy_cfg_cfg_dramconfig), // .cfg_dramconfig
.cfg_interfacewidth (c0_hard_phy_cfg_cfg_interfacewidth), // .cfg_interfacewidth
.cfg_rowaddrwidth (c0_hard_phy_cfg_cfg_rowaddrwidth), // .cfg_rowaddrwidth
.cfg_tcl (c0_hard_phy_cfg_cfg_tcl), // .cfg_tcl
.cfg_tmrd (c0_hard_phy_cfg_cfg_tmrd), // .cfg_tmrd
.cfg_trefi (c0_hard_phy_cfg_cfg_trefi), // .cfg_trefi
.cfg_trfc (c0_hard_phy_cfg_cfg_trfc), // .cfg_trfc
.cfg_twr (c0_hard_phy_cfg_cfg_twr), // .cfg_twr
.io_intaficalfail (p0_io_int_io_intaficalfail), // io_int.io_intaficalfail
.io_intaficalsuccess (p0_io_int_io_intaficalsuccess), // .io_intaficalsuccess
.mp_cmd_clk_0 (1'b0), // (terminated)
.mp_cmd_reset_n_0 (1'b1), // (terminated)
.mp_cmd_clk_1 (1'b0), // (terminated)
.mp_cmd_reset_n_1 (1'b1), // (terminated)
.mp_cmd_clk_2 (1'b0), // (terminated)
.mp_cmd_reset_n_2 (1'b1), // (terminated)
.mp_cmd_clk_3 (1'b0), // (terminated)
.mp_cmd_reset_n_3 (1'b1), // (terminated)
.mp_cmd_clk_4 (1'b0), // (terminated)
.mp_cmd_reset_n_4 (1'b1), // (terminated)
.mp_cmd_clk_5 (1'b0), // (terminated)
.mp_cmd_reset_n_5 (1'b1), // (terminated)
.mp_rfifo_clk_0 (1'b0), // (terminated)
.mp_rfifo_reset_n_0 (1'b1), // (terminated)
.mp_wfifo_clk_0 (1'b0), // (terminated)
.mp_wfifo_reset_n_0 (1'b1), // (terminated)
.mp_rfifo_clk_1 (1'b0), // (terminated)
.mp_rfifo_reset_n_1 (1'b1), // (terminated)
.mp_wfifo_clk_1 (1'b0), // (terminated)
.mp_wfifo_reset_n_1 (1'b1), // (terminated)
.mp_rfifo_clk_2 (1'b0), // (terminated)
.mp_rfifo_reset_n_2 (1'b1), // (terminated)
.mp_wfifo_clk_2 (1'b0), // (terminated)
.mp_wfifo_reset_n_2 (1'b1), // (terminated)
.mp_rfifo_clk_3 (1'b0), // (terminated)
.mp_rfifo_reset_n_3 (1'b1), // (terminated)
.mp_wfifo_clk_3 (1'b0), // (terminated)
.mp_wfifo_reset_n_3 (1'b1), // (terminated)
.csr_clk (1'b0), // (terminated)
.csr_reset_n (1'b1), // (terminated)
.avl_ready_0 (), // (terminated)
.avl_burstbegin_0 (1'b0), // (terminated)
.avl_addr_0 (1'b0), // (terminated)
.avl_rdata_valid_0 (), // (terminated)
.avl_rdata_0 (), // (terminated)
.avl_wdata_0 (1'b0), // (terminated)
.avl_be_0 (1'b0), // (terminated)
.avl_read_req_0 (1'b0), // (terminated)
.avl_write_req_0 (1'b0), // (terminated)
.avl_size_0 (3'b000), // (terminated)
.avl_ready_1 (), // (terminated)
.avl_burstbegin_1 (1'b0), // (terminated)
.avl_addr_1 (1'b0), // (terminated)
.avl_rdata_valid_1 (), // (terminated)
.avl_rdata_1 (), // (terminated)
.avl_wdata_1 (1'b0), // (terminated)
.avl_be_1 (1'b0), // (terminated)
.avl_read_req_1 (1'b0), // (terminated)
.avl_write_req_1 (1'b0), // (terminated)
.avl_size_1 (3'b000), // (terminated)
.avl_ready_2 (), // (terminated)
.avl_burstbegin_2 (1'b0), // (terminated)
.avl_addr_2 (1'b0), // (terminated)
.avl_rdata_valid_2 (), // (terminated)
.avl_rdata_2 (), // (terminated)
.avl_wdata_2 (1'b0), // (terminated)
.avl_be_2 (1'b0), // (terminated)
.avl_read_req_2 (1'b0), // (terminated)
.avl_write_req_2 (1'b0), // (terminated)
.avl_size_2 (3'b000), // (terminated)
.avl_ready_3 (), // (terminated)
.avl_burstbegin_3 (1'b0), // (terminated)
.avl_addr_3 (1'b0), // (terminated)
.avl_rdata_valid_3 (), // (terminated)
.avl_rdata_3 (), // (terminated)
.avl_wdata_3 (1'b0), // (terminated)
.avl_be_3 (1'b0), // (terminated)
.avl_read_req_3 (1'b0), // (terminated)
.avl_write_req_3 (1'b0), // (terminated)
.avl_size_3 (3'b000), // (terminated)
.avl_ready_4 (), // (terminated)
.avl_burstbegin_4 (1'b0), // (terminated)
.avl_addr_4 (1'b0), // (terminated)
.avl_rdata_valid_4 (), // (terminated)
.avl_rdata_4 (), // (terminated)
.avl_wdata_4 (1'b0), // (terminated)
.avl_be_4 (1'b0), // (terminated)
.avl_read_req_4 (1'b0), // (terminated)
.avl_write_req_4 (1'b0), // (terminated)
.avl_size_4 (3'b000), // (terminated)
.avl_ready_5 (), // (terminated)
.avl_burstbegin_5 (1'b0), // (terminated)
.avl_addr_5 (1'b0), // (terminated)
.avl_rdata_valid_5 (), // (terminated)
.avl_rdata_5 (), // (terminated)
.avl_wdata_5 (1'b0), // (terminated)
.avl_be_5 (1'b0), // (terminated)
.avl_read_req_5 (1'b0), // (terminated)
.avl_write_req_5 (1'b0), // (terminated)
.avl_size_5 (3'b000), // (terminated)
.csr_write_req (1'b0), // (terminated)
.csr_read_req (1'b0), // (terminated)
.csr_waitrequest (), // (terminated)
.csr_addr (10'b0000000000), // (terminated)
.csr_be (1'b0), // (terminated)
.csr_wdata (8'b00000000), // (terminated)
.csr_rdata (), // (terminated)
.csr_rdata_valid (), // (terminated)
.local_multicast (1'b0), // (terminated)
.local_refresh_req (1'b0), // (terminated)
.local_refresh_chip (1'b0), // (terminated)
.local_refresh_ack (), // (terminated)
.local_self_rfsh_req (1'b0), // (terminated)
.local_self_rfsh_chip (1'b0), // (terminated)
.local_self_rfsh_ack (), // (terminated)
.local_deep_powerdn_req (1'b0), // (terminated)
.local_deep_powerdn_chip (1'b0), // (terminated)
.local_deep_powerdn_ack (), // (terminated)
.local_powerdn_ack (), // (terminated)
.local_priority (1'b0), // (terminated)
.bonding_in_1 (4'b0000), // (terminated)
.bonding_in_2 (6'b000000), // (terminated)
.bonding_in_3 (6'b000000), // (terminated)
.bonding_out_1 (), // (terminated)
.bonding_out_2 (), // (terminated)
.bonding_out_3 () // (terminated)
);
altera_mem_if_oct_cyclonev #(
.OCT_TERM_CONTROL_WIDTH (16)
) oct (
.oct_rzqin (oct_rzqin), // oct.rzqin
.seriesterminationcontrol (oct_oct_sharing_seriesterminationcontrol), // oct_sharing.seriesterminationcontrol
.parallelterminationcontrol (oct_oct_sharing_parallelterminationcontrol) // .parallelterminationcontrol
);
altera_mem_if_dll_cyclonev #(
.DLL_DELAY_CTRL_WIDTH (7),
.DLL_OFFSET_CTRL_WIDTH (6),
.DELAY_BUFFER_MODE ("HIGH"),
.DELAY_CHAIN_LENGTH (8),
.DLL_INPUT_FREQUENCY_PS_STR ("2500 ps")
) dll (
.clk (p0_dll_clk_clk), // clk.clk
.dll_pll_locked (p0_dll_sharing_dll_pll_locked), // dll_sharing.dll_pll_locked
.dll_delayctrl (dll_dll_sharing_dll_delayctrl) // .dll_delayctrl
);
endmodule
|
module sky130_fd_sc_ms__a221o (
X ,
A1 ,
A2 ,
B1 ,
B2 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire and0_out ;
wire and1_out ;
wire or0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
and and0 (and0_out , B1, B2 );
and and1 (and1_out , A1, A2 );
or or0 (or0_out_X , and1_out, and0_out, C1);
sky130_fd_sc_ms__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, or0_out_X, VPWR, VGND );
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
|
module register (clk, we, d, q);
input [31:0] d;
input clk;
input we;
output [31:0] q;
wire clk;
wire we;
wire [31:0] d;
reg [31:0] q;
always @ (posedge clk)
if (we) q <= d;
endmodule
|
module fibfast (clk, n, start, fibn, done);
input [31:0] n;
input clk;
input start;
output [31:0] fibn;
output done;
wire start;
wire [31:0] n;
wire clk;
reg [31:0] fibn;
reg [31:0] in_n;
reg done;
reg [2:0] state;
reg [2:0] nextstate;
reg [31:0] b;
reg [31:0] h;
reg [31:0] d;
reg [31:0] f;
wire [31:0] nextn;
wire [31:0] nextb;
wire [31:0] nexth;
wire [31:0] nextd;
wire [31:0] nextf;
assign nextn = in_n / 2;
assign nextb = (b * f) + (d * f) + (b * h);
assign nexth = (f * f) + (h * h);
assign nextd = (b * f) + (d * h);
assign nextf = (f * f) + (2 * f * h);
initial begin
done = 1;
state = 0;
in_n = n;
end
always @ (posedge clk)
state = nextstate;
always @ (posedge clk)
if (state == 0 && start) begin
nextstate = 1;
end else if (state == 1) begin
done = 0;
b = 0;
h = 0;
d = 1;
f = 1;
nextstate = 2;
end else if (state == 2) begin
if (n <= 0) begin
nextstate = 0;
fibn = b;
done = 1;
end else begin
nextstate = 3;
end
end else if (state == 3) begin
if (n & 1 == 1) begin
b = nextb;
d = nextd;
end
f = nextf;
h = nexth;
in_n = nextn;
nextstate = 2;
end
endmodule
|
module testbench;
reg clk;
reg [31:0] n;
reg start;
wire [31:0] fibn;
wire done;
fibfast ff (clk, n, start, fibn, done);
initial begin
clk = 0;
n = 10;
start = 1;
$monitor($time,, "%b %d %b %d %b", clk, n, start, fibn, done);
#100 $finish();
end
always
#10 clk = ~clk;
endmodule
|
module \$__inpad (input I, output O);
cycloneiv_io_ibuf _TECHMAP_REPLACE_ (.o(O), .i(I), .ibar(1'b0));
endmodule
|
module \$__outpad (input I, output O);
cycloneiv_io_obuf _TECHMAP_REPLACE_ (.o(O), .i(I), .oe(1'b1));
endmodule
|
module \$lut (A, Y);
parameter WIDTH = 0;
parameter LUT = 0;
(* force_downto *)
input [WIDTH-1:0] A;
output Y;
generate
if (WIDTH == 1) begin
assign Y = ~A[0]; // Not need to spend 1 logic cell for such an easy function
end else
if (WIDTH == 2) begin
cycloneiv_lcell_comb #(.lut_mask({4{LUT}}), .sum_lutc_input("datac")) _TECHMAP_REPLACE_ (.combout(Y), .dataa(A[0]), .datab(A[1]), .datac(1'b1),.datad(1'b1));
end else
if(WIDTH == 3) begin
cycloneiv_lcell_comb #(.lut_mask({2{LUT}}), .sum_lutc_input("datac")) _TECHMAP_REPLACE_ (.combout(Y), .dataa(A[0]), .datab(A[1]), .datac(A[2]),.datad(1'b1));
end else
if(WIDTH == 4) begin
cycloneiv_lcell_comb #(.lut_mask(LUT), .sum_lutc_input("datac")) _TECHMAP_REPLACE_ (.combout(Y), .dataa(A[0]), .datab(A[1]), .datac(A[2]),.datad(A[3]));
end else
wire _TECHMAP_FAIL_ = 1;
endgenerate
endmodule
|
module sky130_fd_sc_ms__a311o (
X ,
A1 ,
A2 ,
A3 ,
B1 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire and0_out ;
wire or0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
and and0 (and0_out , A3, A1, A2 );
or or0 (or0_out_X , and0_out, C1, B1 );
sky130_fd_sc_ms__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, or0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
|
module <?= moduleName ?> (
input <?= aBitRange ?> A,
input sel,
output reg <?= dBitRange ?> D
);
reg <?= dBitRange ?> my_rom [0:<?= (romSize - 1) ?>];
always @ (*) begin
if (~sel)
D = <?= elem.Bits ?>'hz;<?
if (romSize < romMaxSize) {
lastAddr := format("%d'h%x", elem.AddrBits, romSize - 1); ?>
else if (A > <?= lastAddr ?>)
D = <?= elem.Bits ?>'h0;<?
} ?>
else
D = my_rom[A];
end
initial begin<?
for (i := 0; i < romSize; i++) { ?>
my_rom[<?= i ?>] = <?= format("%d'h%x", elem.Bits, data[i]) ?>;<?
} ?>
end
endmodule
|
module altera_mem_if_ddr3_phy_0001_reset_sync(
reset_n,
clk,
reset_n_sync
);
parameter RESET_SYNC_STAGES = 4;
parameter NUM_RESET_OUTPUT = 1;
input reset_n;
input clk;
output [NUM_RESET_OUTPUT-1:0] reset_n_sync;
// identify the synchronizer chain so that Quartus can analyze metastability.
// Since these resets are localized to the PHY alone, make them routed locally
// to avoid using global networks.
(* altera_attribute = {"-name SYNCHRONIZER_IDENTIFICATION FORCED_IF_ASYNCHRONOUS; -name GLOBAL_SIGNAL OFF"}*) reg [RESET_SYNC_STAGES+NUM_RESET_OUTPUT-2:0] reset_reg /*synthesis dont_merge */;
generate
genvar i;
for (i=0; i<RESET_SYNC_STAGES+NUM_RESET_OUTPUT-1; i=i+1)
begin: reset_stage
always @(posedge clk or negedge reset_n)
begin
if (~reset_n)
reset_reg[i] <= 1'b0;
else
begin
if (i==0)
reset_reg[i] <= 1'b1;
else if (i < RESET_SYNC_STAGES)
reset_reg[i] <= reset_reg[i-1];
else
reset_reg[i] <= reset_reg[RESET_SYNC_STAGES-2];
end
end
end
endgenerate
assign reset_n_sync = reset_reg[RESET_SYNC_STAGES+NUM_RESET_OUTPUT-2:RESET_SYNC_STAGES-1];
endmodule
|
module vga_axi_buffer_v1_0_tb;
reg tb_ACLK;
reg tb_ARESETn;
// Create an instance of the example tb
`BD_WRAPPER dut (.ACLK(tb_ACLK),
.ARESETN(tb_ARESETn));
// Local Variables
// AMBA SAXI AXI4 Lite Local Reg
reg [`SAXI_DATA_BUS_WIDTH-1:0] SAXI_rd_data_lite;
reg [`SAXI_DATA_BUS_WIDTH-1:0] SAXI_test_data_lite [3:0];
reg [`RESP_BUS_WIDTH-1:0] SAXI_lite_response;
reg [`SAXI_ADDRESS_BUS_WIDTH-1:0] SAXI_mtestAddress;
reg [3-1:0] SAXI_mtestProtection_lite;
integer SAXI_mtestvectorlite; // Master side testvector
integer SAXI_mtestdatasizelite;
integer result_slave_lite;
// Simple Reset Generator and test
initial begin
tb_ARESETn = 1'b0;
#500;
// Release the reset on the posedge of the clk.
@(posedge tb_ACLK);
tb_ARESETn = 1'b1;
@(posedge tb_ACLK);
end
// Simple Clock Generator
initial tb_ACLK = 1'b0;
always #10 tb_ACLK = !tb_ACLK;
//------------------------------------------------------------------------
// TEST LEVEL API: CHECK_RESPONSE_OKAY
//------------------------------------------------------------------------
// Description:
// CHECK_RESPONSE_OKAY(lite_response)
// This task checks if the return lite_response is equal to OKAY
//------------------------------------------------------------------------
task automatic CHECK_RESPONSE_OKAY;
input [`RESP_BUS_WIDTH-1:0] response;
begin
if (response !== `RESPONSE_OKAY) begin
$display("TESTBENCH ERROR! lite_response is not OKAY",
"\n expected = 0x%h",`RESPONSE_OKAY,
"\n actual = 0x%h",response);
$stop;
end
end
endtask
//------------------------------------------------------------------------
// TEST LEVEL API: COMPARE_LITE_DATA
//------------------------------------------------------------------------
// Description:
// COMPARE_LITE_DATA(expected,actual)
// This task checks if the actual data is equal to the expected data.
// X is used as don't care but it is not permitted for the full vector
// to be don't care.
//------------------------------------------------------------------------
`define S_AXI_DATA_BUS_WIDTH 32
task automatic COMPARE_LITE_DATA;
input [`S_AXI_DATA_BUS_WIDTH-1:0]expected;
input [`S_AXI_DATA_BUS_WIDTH-1:0]actual;
begin
if (expected === 'hx || actual === 'hx) begin
$display("TESTBENCH ERROR! COMPARE_LITE_DATA cannot be performed with an expected or actual vector that is all 'x'!");
result_slave_lite = 0;
$stop;
end
if (actual != expected) begin
$display("TESTBENCH ERROR! Data expected is not equal to actual.",
"\nexpected = 0x%h",expected,
"\nactual = 0x%h",actual);
result_slave_lite = 0;
$stop;
end
else
begin
$display("TESTBENCH Passed! Data expected is equal to actual.",
"\n expected = 0x%h",expected,
"\n actual = 0x%h",actual);
end
end
endtask
task automatic SAXI_TEST;
begin
$display("---------------------------------------------------------");
$display("EXAMPLE TEST : SAXI");
$display("Simple register write and read example");
$display("---------------------------------------------------------");
SAXI_mtestvectorlite = 0;
SAXI_mtestAddress = `SAXI_SLAVE_ADDRESS;
SAXI_mtestProtection_lite = 0;
SAXI_mtestdatasizelite = `SAXI_MAX_DATA_SIZE;
result_slave_lite = 1;
for (SAXI_mtestvectorlite = 0; SAXI_mtestvectorlite <= 3; SAXI_mtestvectorlite = SAXI_mtestvectorlite + 1)
begin
dut.`BD_INST_NAME.master_0.cdn_axi4_lite_master_bfm_inst.WRITE_BURST_CONCURRENT( SAXI_mtestAddress,
SAXI_mtestProtection_lite,
SAXI_test_data_lite[SAXI_mtestvectorlite],
SAXI_mtestdatasizelite,
SAXI_lite_response);
$display("EXAMPLE TEST %d write : DATA = 0x%h, lite_response = 0x%h",SAXI_mtestvectorlite,SAXI_test_data_lite[SAXI_mtestvectorlite],SAXI_lite_response);
CHECK_RESPONSE_OKAY(SAXI_lite_response);
dut.`BD_INST_NAME.master_0.cdn_axi4_lite_master_bfm_inst.READ_BURST(SAXI_mtestAddress,
SAXI_mtestProtection_lite,
SAXI_rd_data_lite,
SAXI_lite_response);
$display("EXAMPLE TEST %d read : DATA = 0x%h, lite_response = 0x%h",SAXI_mtestvectorlite,SAXI_rd_data_lite,SAXI_lite_response);
CHECK_RESPONSE_OKAY(SAXI_lite_response);
COMPARE_LITE_DATA(SAXI_test_data_lite[SAXI_mtestvectorlite],SAXI_rd_data_lite);
$display("EXAMPLE TEST %d : Sequential write and read burst transfers complete from the master side. %d",SAXI_mtestvectorlite,SAXI_mtestvectorlite);
SAXI_mtestAddress = SAXI_mtestAddress + 32'h00000004;
end
$display("---------------------------------------------------------");
$display("EXAMPLE TEST SAXI: PTGEN_TEST_FINISHED!");
if ( result_slave_lite ) begin
$display("PTGEN_TEST: PASSED!");
end else begin
$display("PTGEN_TEST: FAILED!");
end
$display("---------------------------------------------------------");
end
endtask
// Create the test vectors
initial begin
// When performing debug enable all levels of INFO messages.
wait(tb_ARESETn === 0) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
dut.`BD_INST_NAME.master_0.cdn_axi4_lite_master_bfm_inst.set_channel_level_info(1);
// Create test data vectors
SAXI_test_data_lite[0] = 32'h0101FFFF;
SAXI_test_data_lite[1] = 32'habcd0001;
SAXI_test_data_lite[2] = 32'hdead0011;
SAXI_test_data_lite[3] = 32'hbeef0011;
end
// Drive the BFM
initial begin
// Wait for end of reset
wait(tb_ARESETn === 0) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
SAXI_TEST();
end
endmodule
|
module nios_altmemddr_0_phy_alt_mem_phy_seq_wrapper (
// dss ports
phy_clk_1x,
reset_phy_clk_1x_n,
ctl_cal_success,
ctl_cal_fail,
ctl_cal_warning,
ctl_cal_req,
int_RANK_HAS_ADDR_SWAP,
ctl_cal_byte_lane_sel_n,
seq_pll_inc_dec_n,
seq_pll_start_reconfig,
seq_pll_select,
phs_shft_busy,
pll_resync_clk_index,
pll_measure_clk_index,
sc_clk_dp,
scan_enable_dqs_config,
scan_update,
scan_din,
scan_enable_ck,
scan_enable_dqs,
scan_enable_dqsn,
scan_enable_dq,
scan_enable_dm,
hr_rsc_clk,
seq_ac_addr,
seq_ac_ba,
seq_ac_cas_n,
seq_ac_ras_n,
seq_ac_we_n,
seq_ac_cke,
seq_ac_cs_n,
seq_ac_odt,
seq_ac_rst_n,
seq_ac_sel,
seq_mem_clk_disable,
ctl_add_1t_ac_lat_internal,
ctl_add_1t_odt_lat_internal,
ctl_add_intermediate_regs_internal,
seq_rdv_doing_rd,
seq_rdp_reset_req_n,
seq_rdp_inc_read_lat_1x,
seq_rdp_dec_read_lat_1x,
ctl_rdata,
int_rdata_valid_1t,
seq_rdata_valid_lat_inc,
seq_rdata_valid_lat_dec,
ctl_rlat,
seq_poa_lat_dec_1x,
seq_poa_lat_inc_1x,
seq_poa_protection_override_1x,
seq_oct_oct_delay,
seq_oct_oct_extend,
seq_oct_val,
seq_wdp_dqs_burst,
seq_wdp_wdata_valid,
seq_wdp_wdata,
seq_wdp_dm,
seq_wdp_dqs,
seq_wdp_ovride,
seq_dqs_add_2t_delay,
ctl_wlat,
seq_mmc_start,
mmc_seq_done,
mmc_seq_value,
mem_err_out_n,
parity_error_n,
dbg_clk,
dbg_reset_n,
dbg_addr,
dbg_wr,
dbg_rd,
dbg_cs,
dbg_wr_data,
dbg_rd_data,
dbg_waitrequest
);
//Inserted Generics
localparam SPEED_GRADE = "C8";
localparam MEM_IF_DQS_WIDTH = 1;
localparam MEM_IF_DWIDTH = 8;
localparam MEM_IF_DM_WIDTH = 1;
localparam MEM_IF_DQ_PER_DQS = 8;
localparam DWIDTH_RATIO = 4;
localparam CLOCK_INDEX_WIDTH = 3;
localparam MEM_IF_CLK_PAIR_COUNT = 1;
localparam MEM_IF_ADDR_WIDTH = 14;
localparam MEM_IF_BANKADDR_WIDTH = 2;
localparam MEM_IF_CS_WIDTH = 1;
localparam RESYNCHRONISE_AVALON_DBG = 0;
localparam DBG_A_WIDTH = 13;
localparam DQS_PHASE_SETTING = 2;
localparam SCAN_CLK_DIVIDE_BY = 2;
localparam PLL_STEPS_PER_CYCLE = 80;
localparam MEM_IF_CLK_PS = 8000;
localparam DQS_DELAY_CTL_WIDTH = 6;
localparam MEM_IF_MEMTYPE = "DDR2";
localparam RANK_HAS_ADDR_SWAP = 0;
localparam MEM_IF_MR_0 = 579;
localparam MEM_IF_MR_1 = 1024;
localparam MEM_IF_MR_2 = 0;
localparam MEM_IF_MR_3 = 0;
localparam MEM_IF_OCT_EN = 0;
localparam IP_BUILDNUM = 0;
localparam FAMILY = "Cyclone IV E";
localparam FAMILYGROUP_ID = 2;
localparam MEM_IF_ADDR_CMD_PHASE = 90;
localparam CAPABILITIES = 2048;
localparam WRITE_DESKEW_T10 = 0;
localparam WRITE_DESKEW_HC_T10 = 0;
localparam WRITE_DESKEW_T9NI = 0;
localparam WRITE_DESKEW_HC_T9NI = 0;
localparam WRITE_DESKEW_T9I = 0;
localparam WRITE_DESKEW_HC_T9I = 0;
localparam WRITE_DESKEW_RANGE = 0;
localparam IOE_PHASES_PER_TCK = 12;
localparam ADV_LAT_WIDTH = 5;
localparam RDP_ADDR_WIDTH = 4;
localparam IOE_DELAYS_PER_PHS = 5;
localparam SINGLE_DQS_DELAY_CONTROL_CODE = 0;
localparam PRESET_RLAT = 0;
localparam FORCE_HC = 0;
localparam MEM_IF_DQS_CAPTURE_EN = 0;
localparam REDUCE_SIM_TIME = 0;
localparam TINIT_TCK = 12500;
localparam TINIT_RST = 0;
localparam GENERATE_ADDITIONAL_DBG_RTL = 0;
localparam MEM_IF_CS_PER_RANK = 1;
localparam MEM_IF_RANKS_PER_SLOT = 1;
localparam CHIP_OR_DIMM = "Discrete Device";
localparam RDIMM_CONFIG_BITS = "0000000000000000000000000000000000000000000000000000000000000000";
localparam OCT_LAT_WIDTH = ADV_LAT_WIDTH;
localparam GENERATE_TRACKING_PHASE_STORE = 0;
// note that num_ranks if the number of discrete chip select signals output from the sequencer
// cs_width is the total number of chip selects which go from the phy to the memory (there can
// be more than one chip select per rank).
localparam MEM_IF_NUM_RANKS = MEM_IF_CS_WIDTH/MEM_IF_CS_PER_RANK;
input wire phy_clk_1x;
input wire reset_phy_clk_1x_n;
output wire ctl_cal_success;
output wire ctl_cal_fail;
output wire ctl_cal_warning;
input wire ctl_cal_req;
input wire [MEM_IF_NUM_RANKS - 1 : 0] int_RANK_HAS_ADDR_SWAP;
input wire [MEM_IF_NUM_RANKS * MEM_IF_DQS_WIDTH - 1 : 0] ctl_cal_byte_lane_sel_n;
output wire seq_pll_inc_dec_n;
output wire seq_pll_start_reconfig;
output wire [CLOCK_INDEX_WIDTH - 1 : 0] seq_pll_select;
input wire phs_shft_busy;
input wire [CLOCK_INDEX_WIDTH - 1 : 0] pll_resync_clk_index;
input wire [CLOCK_INDEX_WIDTH - 1 : 0] pll_measure_clk_index;
output [MEM_IF_DQS_WIDTH - 1 : 0] sc_clk_dp;
output wire [MEM_IF_DQS_WIDTH - 1 : 0] scan_enable_dqs_config;
output wire [MEM_IF_DQS_WIDTH - 1 : 0] scan_update;
output wire [MEM_IF_DQS_WIDTH - 1 : 0] scan_din;
output wire [MEM_IF_CLK_PAIR_COUNT - 1 : 0] scan_enable_ck;
output wire [MEM_IF_DQS_WIDTH - 1 : 0] scan_enable_dqs;
output wire [MEM_IF_DQS_WIDTH - 1 : 0] scan_enable_dqsn;
output wire [MEM_IF_DWIDTH - 1 : 0] scan_enable_dq;
output wire [MEM_IF_DM_WIDTH - 1 : 0] scan_enable_dm;
input wire hr_rsc_clk;
output wire [(DWIDTH_RATIO/2) * MEM_IF_ADDR_WIDTH - 1 : 0] seq_ac_addr;
output wire [(DWIDTH_RATIO/2) * MEM_IF_BANKADDR_WIDTH - 1 : 0] seq_ac_ba;
output wire [(DWIDTH_RATIO/2) - 1 : 0] seq_ac_cas_n;
output wire [(DWIDTH_RATIO/2) - 1 : 0] seq_ac_ras_n;
output wire [(DWIDTH_RATIO/2) - 1 : 0] seq_ac_we_n;
output wire [(DWIDTH_RATIO/2) * MEM_IF_NUM_RANKS - 1 : 0] seq_ac_cke;
output wire [(DWIDTH_RATIO/2) * MEM_IF_CS_WIDTH - 1 : 0] seq_ac_cs_n;
output wire [(DWIDTH_RATIO/2) * MEM_IF_NUM_RANKS - 1 : 0] seq_ac_odt;
output wire [(DWIDTH_RATIO/2) - 1 : 0] seq_ac_rst_n;
output wire seq_ac_sel;
output wire seq_mem_clk_disable;
output wire ctl_add_1t_ac_lat_internal;
output wire ctl_add_1t_odt_lat_internal;
output wire ctl_add_intermediate_regs_internal;
output wire [MEM_IF_DQS_WIDTH * DWIDTH_RATIO/2 - 1 : 0] seq_rdv_doing_rd;
output wire seq_rdp_reset_req_n;
output wire [MEM_IF_DQS_WIDTH - 1 : 0] seq_rdp_inc_read_lat_1x;
output wire [MEM_IF_DQS_WIDTH - 1 : 0] seq_rdp_dec_read_lat_1x;
input wire [DWIDTH_RATIO * MEM_IF_DWIDTH - 1 : 0] ctl_rdata;
input wire [DWIDTH_RATIO/2 - 1 : 0] int_rdata_valid_1t;
output wire seq_rdata_valid_lat_inc;
output wire seq_rdata_valid_lat_dec;
output wire [ADV_LAT_WIDTH - 1 : 0] ctl_rlat;
output wire [MEM_IF_DQS_WIDTH - 1 : 0] seq_poa_lat_dec_1x;
output wire [MEM_IF_DQS_WIDTH - 1 : 0] seq_poa_lat_inc_1x;
output wire seq_poa_protection_override_1x;
output wire [OCT_LAT_WIDTH - 1 : 0] seq_oct_oct_delay;
output wire [OCT_LAT_WIDTH - 1 : 0] seq_oct_oct_extend;
output wire seq_oct_val;
output wire [(DWIDTH_RATIO/2) * MEM_IF_DQS_WIDTH - 1 : 0] seq_wdp_dqs_burst;
output wire [(DWIDTH_RATIO/2) * MEM_IF_DQS_WIDTH - 1 : 0] seq_wdp_wdata_valid;
output wire [DWIDTH_RATIO * MEM_IF_DWIDTH - 1 : 0] seq_wdp_wdata;
output wire [DWIDTH_RATIO * MEM_IF_DM_WIDTH - 1 : 0] seq_wdp_dm;
output wire [DWIDTH_RATIO - 1 : 0] seq_wdp_dqs;
output wire seq_wdp_ovride;
output wire [MEM_IF_DQS_WIDTH - 1 : 0] seq_dqs_add_2t_delay;
output wire [ADV_LAT_WIDTH - 1 : 0] ctl_wlat;
output wire seq_mmc_start;
input wire mmc_seq_done;
input wire mmc_seq_value;
input wire dbg_clk;
input wire dbg_reset_n;
input wire [DBG_A_WIDTH - 1 : 0] dbg_addr;
input wire dbg_wr;
input wire dbg_rd;
input wire dbg_cs;
input wire [ 31 : 0] dbg_wr_data;
output wire [ 31 : 0] dbg_rd_data;
output wire dbg_waitrequest;
input wire mem_err_out_n;
output wire parity_error_n;
(* altera_attribute = "-name global_signal off" *) wire [MEM_IF_DQS_WIDTH - 1 : 0] sc_clk_dp;
// instantiate the deskew (DDR3) or non-deskew (DDR/DDR2/DDR3) sequencer:
//
nios_altmemddr_0_phy_alt_mem_phy_seq #(
.MEM_IF_DQS_WIDTH (MEM_IF_DQS_WIDTH),
.MEM_IF_DWIDTH (MEM_IF_DWIDTH),
.MEM_IF_DM_WIDTH (MEM_IF_DM_WIDTH),
.MEM_IF_DQ_PER_DQS (MEM_IF_DQ_PER_DQS),
.DWIDTH_RATIO (DWIDTH_RATIO),
.CLOCK_INDEX_WIDTH (CLOCK_INDEX_WIDTH),
.MEM_IF_CLK_PAIR_COUNT (MEM_IF_CLK_PAIR_COUNT),
.MEM_IF_ADDR_WIDTH (MEM_IF_ADDR_WIDTH),
.MEM_IF_BANKADDR_WIDTH (MEM_IF_BANKADDR_WIDTH),
.MEM_IF_CS_WIDTH (MEM_IF_CS_WIDTH),
.MEM_IF_NUM_RANKS (MEM_IF_NUM_RANKS),
.MEM_IF_RANKS_PER_SLOT (MEM_IF_RANKS_PER_SLOT),
.ADV_LAT_WIDTH (ADV_LAT_WIDTH),
.RESYNCHRONISE_AVALON_DBG (RESYNCHRONISE_AVALON_DBG),
.AV_IF_ADDR_WIDTH (DBG_A_WIDTH),
.NOM_DQS_PHASE_SETTING (DQS_PHASE_SETTING),
.SCAN_CLK_DIVIDE_BY (SCAN_CLK_DIVIDE_BY),
.RDP_ADDR_WIDTH (RDP_ADDR_WIDTH),
.PLL_STEPS_PER_CYCLE (PLL_STEPS_PER_CYCLE),
.IOE_PHASES_PER_TCK (IOE_PHASES_PER_TCK),
.IOE_DELAYS_PER_PHS (IOE_DELAYS_PER_PHS),
.MEM_IF_CLK_PS (MEM_IF_CLK_PS),
.PHY_DEF_MR_1ST (MEM_IF_MR_0),
.PHY_DEF_MR_2ND (MEM_IF_MR_1),
.PHY_DEF_MR_3RD (MEM_IF_MR_2),
.PHY_DEF_MR_4TH (MEM_IF_MR_3),
.MEM_IF_DQSN_EN (0),
.MEM_IF_DQS_CAPTURE_EN (MEM_IF_DQS_CAPTURE_EN),
.FAMILY (FAMILY),
.FAMILYGROUP_ID (FAMILYGROUP_ID),
.SPEED_GRADE (SPEED_GRADE),
.MEM_IF_MEMTYPE (MEM_IF_MEMTYPE),
.WRITE_DESKEW_T10 (WRITE_DESKEW_T10),
.WRITE_DESKEW_HC_T10 (WRITE_DESKEW_HC_T10),
.WRITE_DESKEW_T9NI (WRITE_DESKEW_T9NI),
.WRITE_DESKEW_HC_T9NI (WRITE_DESKEW_HC_T9NI),
.WRITE_DESKEW_T9I (WRITE_DESKEW_T9I),
.WRITE_DESKEW_HC_T9I (WRITE_DESKEW_HC_T9I),
.WRITE_DESKEW_RANGE (WRITE_DESKEW_RANGE),
.SINGLE_DQS_DELAY_CONTROL_CODE (SINGLE_DQS_DELAY_CONTROL_CODE),
.PRESET_RLAT (PRESET_RLAT),
.EN_OCT (MEM_IF_OCT_EN),
.SIM_TIME_REDUCTIONS (REDUCE_SIM_TIME),
.FORCE_HC (FORCE_HC),
.CAPABILITIES (CAPABILITIES),
.GENERATE_ADDITIONAL_DBG_RTL (GENERATE_ADDITIONAL_DBG_RTL),
.TINIT_TCK (TINIT_TCK),
.TINIT_RST (TINIT_RST),
.GENERATE_TRACKING_PHASE_STORE (0),
.OCT_LAT_WIDTH (OCT_LAT_WIDTH),
.IP_BUILDNUM (IP_BUILDNUM),
.CHIP_OR_DIMM (CHIP_OR_DIMM),
.RDIMM_CONFIG_BITS (RDIMM_CONFIG_BITS)
) seq_inst (
.clk (phy_clk_1x),
.rst_n (reset_phy_clk_1x_n),
.ctl_init_success (ctl_cal_success),
.ctl_init_fail (ctl_cal_fail),
.ctl_init_warning (ctl_cal_warning),
.ctl_recalibrate_req (ctl_cal_req),
.MEM_AC_SWAPPED_RANKS (int_RANK_HAS_ADDR_SWAP),
.ctl_cal_byte_lanes (ctl_cal_byte_lane_sel_n),
.seq_pll_inc_dec_n (seq_pll_inc_dec_n),
.seq_pll_start_reconfig (seq_pll_start_reconfig),
.seq_pll_select (seq_pll_select),
.seq_pll_phs_shift_busy (phs_shft_busy),
.pll_resync_clk_index (pll_resync_clk_index),
.pll_measure_clk_index (pll_measure_clk_index),
.seq_scan_clk (sc_clk_dp),
.seq_scan_enable_dqs_config (scan_enable_dqs_config),
.seq_scan_update (scan_update),
.seq_scan_din (scan_din),
.seq_scan_enable_ck (scan_enable_ck),
.seq_scan_enable_dqs (scan_enable_dqs),
.seq_scan_enable_dqsn (scan_enable_dqsn),
.seq_scan_enable_dq (scan_enable_dq),
.seq_scan_enable_dm (scan_enable_dm),
.hr_rsc_clk (hr_rsc_clk),
.seq_ac_addr (seq_ac_addr),
.seq_ac_ba (seq_ac_ba),
.seq_ac_cas_n (seq_ac_cas_n),
.seq_ac_ras_n (seq_ac_ras_n),
.seq_ac_we_n (seq_ac_we_n),
.seq_ac_cke (seq_ac_cke),
.seq_ac_cs_n (seq_ac_cs_n),
.seq_ac_odt (seq_ac_odt),
.seq_ac_rst_n (seq_ac_rst_n),
.seq_ac_sel (seq_ac_sel),
.seq_mem_clk_disable (seq_mem_clk_disable),
.seq_ac_add_1t_ac_lat_internal (ctl_add_1t_ac_lat_internal),
.seq_ac_add_1t_odt_lat_internal (ctl_add_1t_odt_lat_internal),
.seq_ac_add_2t (ctl_add_intermediate_regs_internal),
.seq_rdv_doing_rd (seq_rdv_doing_rd),
.seq_rdp_reset_req_n (seq_rdp_reset_req_n),
.seq_rdp_inc_read_lat_1x (seq_rdp_inc_read_lat_1x),
.seq_rdp_dec_read_lat_1x (seq_rdp_dec_read_lat_1x),
.rdata (ctl_rdata),
.rdata_valid (int_rdata_valid_1t),
.seq_rdata_valid_lat_inc (seq_rdata_valid_lat_inc),
.seq_rdata_valid_lat_dec (seq_rdata_valid_lat_dec),
.seq_ctl_rlat (ctl_rlat),
.seq_poa_lat_dec_1x (seq_poa_lat_dec_1x),
.seq_poa_lat_inc_1x (seq_poa_lat_inc_1x),
.seq_poa_protection_override_1x (seq_poa_protection_override_1x),
.seq_oct_oct_delay (seq_oct_oct_delay),
.seq_oct_oct_extend (seq_oct_oct_extend),
.seq_oct_value (seq_oct_val),
.seq_wdp_dqs_burst (seq_wdp_dqs_burst),
.seq_wdp_wdata_valid (seq_wdp_wdata_valid),
.seq_wdp_wdata (seq_wdp_wdata),
.seq_wdp_dm (seq_wdp_dm),
.seq_wdp_dqs (seq_wdp_dqs),
.seq_wdp_ovride (seq_wdp_ovride),
.seq_dqs_add_2t_delay (seq_dqs_add_2t_delay),
.seq_ctl_wlat (ctl_wlat),
.seq_mmc_start (seq_mmc_start),
.mmc_seq_done (mmc_seq_done),
.mmc_seq_value (mmc_seq_value),
.mem_err_out_n (mem_err_out_n),
.parity_error_n (parity_error_n),
.dbg_seq_clk (dbg_clk),
.dbg_seq_rst_n (dbg_reset_n),
.dbg_seq_addr (dbg_addr),
.dbg_seq_wr (dbg_wr),
.dbg_seq_rd (dbg_rd),
.dbg_seq_cs (dbg_cs),
.dbg_seq_wr_data (dbg_wr_data),
.seq_dbg_rd_data (dbg_rd_data),
.seq_dbg_waitrequest (dbg_waitrequest)
);
endmodule
|
module outputs)
wire act_wait_r; // From bank_state0 of bank_state.v
wire allow_auto_pre; // From bank_state0 of bank_state.v
wire auto_pre_r; // From bank_queue0 of bank_queue.v
wire bank_wait_in_progress; // From bank_state0 of bank_state.v
wire order_q_zero; // From bank_queue0 of bank_queue.v
wire pass_open_bank_ns; // From bank_queue0 of bank_queue.v
wire pass_open_bank_r; // From bank_queue0 of bank_queue.v
wire pre_wait_r; // From bank_state0 of bank_state.v
wire precharge_bm_end; // From bank_state0 of bank_state.v
wire q_has_priority; // From bank_queue0 of bank_queue.v
wire q_has_rd; // From bank_queue0 of bank_queue.v
wire [nBANK_MACHS*2-1:0] rb_hit_busies_r; // From bank_queue0 of bank_queue.v
wire rcv_open_bank; // From bank_queue0 of bank_queue.v
wire rd_half_rmw; // From bank_state0 of bank_state.v
wire req_priority_r; // From bank_compare0 of bank_compare.v
wire row_hit_r; // From bank_compare0 of bank_compare.v
wire tail_r; // From bank_queue0 of bank_queue.v
wire wait_for_maint_r; // From bank_queue0 of bank_queue.v
// End of automatics
output idle_ns;
output req_wr_r;
output rd_wr_r;
output bm_end;
output idle_r;
output head_r;
output [RANK_WIDTH-1:0] req_rank_r;
output rb_hit_busy_r;
output passing_open_bank;
output maint_hit;
output [DATA_BUF_ADDR_WIDTH-1:0] req_data_buf_addr_r;
bank_compare #
(/*AUTOINSTPARAM*/
// Parameters
.BANK_WIDTH (BANK_WIDTH),
.TCQ (TCQ),
.BURST_MODE (BURST_MODE),
.COL_WIDTH (COL_WIDTH),
.DATA_BUF_ADDR_WIDTH (DATA_BUF_ADDR_WIDTH),
.ECC (ECC),
.RANK_WIDTH (RANK_WIDTH),
.RANKS (RANKS),
.ROW_WIDTH (ROW_WIDTH))
bank_compare0
(/*AUTOINST*/
// Outputs
.req_data_buf_addr_r (req_data_buf_addr_r[DATA_BUF_ADDR_WIDTH-1:0]),
.req_periodic_rd_r (req_periodic_rd_r),
.req_size_r (req_size_r),
.rd_wr_r (rd_wr_r),
.req_rank_r (req_rank_r[RANK_WIDTH-1:0]),
.req_bank_r (req_bank_r[BANK_WIDTH-1:0]),
.req_row_r (req_row_r[ROW_WIDTH-1:0]),
.req_wr_r (req_wr_r),
.req_priority_r (req_priority_r),
.rb_hit_busy_r (rb_hit_busy_r),
.rb_hit_busy_ns (rb_hit_busy_ns),
.row_hit_r (row_hit_r),
.maint_hit (maint_hit),
.col_addr (col_addr[ROW_WIDTH-1:0]),
.req_ras (req_ras),
.req_cas (req_cas),
.row_cmd_wr (row_cmd_wr),
.row_addr (row_addr[ROW_WIDTH-1:0]),
.rank_busy_r (rank_busy_r[RANKS-1:0]),
// Inputs
.clk (clk),
.idle_ns (idle_ns),
.idle_r (idle_r),
.data_buf_addr (data_buf_addr[DATA_BUF_ADDR_WIDTH-1:0]),
.periodic_rd_insert (periodic_rd_insert),
.size (size),
.cmd (cmd[2:0]),
.sending_col (sending_col),
.rank (rank[RANK_WIDTH-1:0]),
.periodic_rd_rank_r (periodic_rd_rank_r[RANK_WIDTH-1:0]),
.bank (bank[BANK_WIDTH-1:0]),
.row (row[ROW_WIDTH-1:0]),
.col (col[COL_WIDTH-1:0]),
.hi_priority (hi_priority),
.maint_rank_r (maint_rank_r[RANK_WIDTH-1:0]),
.maint_zq_r (maint_zq_r),
.auto_pre_r (auto_pre_r),
.rd_half_rmw (rd_half_rmw),
.act_wait_r (act_wait_r));
bank_state #
(/*AUTOINSTPARAM*/
// Parameters
.TCQ (TCQ),
.ADDR_CMD_MODE (ADDR_CMD_MODE),
.BM_CNT_WIDTH (BM_CNT_WIDTH),
.BURST_MODE (BURST_MODE),
.CWL (CWL),
.DATA_BUF_ADDR_WIDTH (DATA_BUF_ADDR_WIDTH),
.DRAM_TYPE (DRAM_TYPE),
.ECC (ECC),
.ID (ID),
.nBANK_MACHS (nBANK_MACHS),
.nCK_PER_CLK (nCK_PER_CLK),
.nCNFG2RD_EN (nCNFG2RD_EN),
.nCNFG2WR (nCNFG2WR),
.nOP_WAIT (nOP_WAIT),
.nRAS_CLKS (nRAS_CLKS),
.nRP (nRP),
.nRTP (nRTP),
.nRCD (nRCD),
.nWTP_CLKS (nWTP_CLKS),
.ORDERING (ORDERING),
.RANKS (RANKS),
.RANK_WIDTH (RANK_WIDTH),
.RAS_TIMER_WIDTH (RAS_TIMER_WIDTH),
.STARVE_LIMIT (STARVE_LIMIT))
bank_state0
(/*AUTOINST*/
// Outputs
.start_rcd (start_rcd),
.act_wait_r (act_wait_r),
.rd_half_rmw (rd_half_rmw),
.ras_timer_ns (ras_timer_ns[RAS_TIMER_WIDTH-1:0]),
.end_rtp (end_rtp),
.bank_wait_in_progress (bank_wait_in_progress),
.start_pre_wait (start_pre_wait),
.op_exit_req (op_exit_req),
.pre_wait_r (pre_wait_r),
.allow_auto_pre (allow_auto_pre),
.precharge_bm_end (precharge_bm_end),
.demand_act_priority (demand_act_priority),
.rts_row (rts_row),
.rts_pre (rts_pre),
.act_this_rank_r (act_this_rank_r[RANKS-1:0]),
.demand_priority (demand_priority),
.rtc (rtc),
.col_rdy_wr (col_rdy_wr),
.rts_col (rts_col),
.wr_this_rank_r (wr_this_rank_r[RANKS-1:0]),
.rd_this_rank_r (rd_this_rank_r[RANKS-1:0]),
// Inputs
.clk (clk),
.rst (rst),
.bm_end (bm_end),
.pass_open_bank_r (pass_open_bank_r),
.sending_row (sending_row),
.sending_pre (sending_pre),
.rcv_open_bank (rcv_open_bank),
.sending_col (sending_col),
.rd_wr_r (rd_wr_r),
.req_wr_r (req_wr_r),
.rd_data_addr (rd_data_addr[DATA_BUF_ADDR_WIDTH-1:0]),
.req_data_buf_addr_r (req_data_buf_addr_r[DATA_BUF_ADDR_WIDTH-1:0]),
.phy_rddata_valid (phy_rddata_valid),
.rd_rmw (rd_rmw),
.ras_timer_ns_in (ras_timer_ns_in[(2*(RAS_TIMER_WIDTH*nBANK_MACHS))-1:0]),
.rb_hit_busies_r (rb_hit_busies_r[(nBANK_MACHS*2)-1:0]),
.idle_r (idle_r),
.passing_open_bank (passing_open_bank),
.low_idle_cnt_r (low_idle_cnt_r),
.op_exit_grant (op_exit_grant),
.tail_r (tail_r),
.auto_pre_r (auto_pre_r),
.pass_open_bank_ns (pass_open_bank_ns),
.req_rank_r (req_rank_r[RANK_WIDTH-1:0]),
.req_rank_r_in (req_rank_r_in[(RANK_WIDTH*nBANK_MACHS*2)-1:0]),
.start_rcd_in (start_rcd_in[(nBANK_MACHS*2)-1:0]),
.inhbt_act_faw_r (inhbt_act_faw_r[RANKS-1:0]),
.wait_for_maint_r (wait_for_maint_r),
.head_r (head_r),
.sent_row (sent_row),
.demand_act_priority_in (demand_act_priority_in[(nBANK_MACHS*2)-1:0]),
.order_q_zero (order_q_zero),
.sent_col (sent_col),
.q_has_rd (q_has_rd),
.q_has_priority (q_has_priority),
.req_priority_r (req_priority_r),
.idle_ns (idle_ns),
.demand_priority_in (demand_priority_in[(nBANK_MACHS*2)-1:0]),
.io_config_strobe (io_config_strobe),
.io_config_valid_r (io_config_valid_r),
.io_config (io_config[RANK_WIDTH:0]),
.wtr_inhbt_config_r (wtr_inhbt_config_r[RANKS-1:0]),
.inhbt_rd_config (inhbt_rd_config),
.inhbt_wr_config (inhbt_wr_config),
.inhbt_rd_r (inhbt_rd_r[RANKS-1:0]),
.inhbt_wr_r (inhbt_wr_r[RANKS-1:0]),
.dq_busy_data (dq_busy_data));
bank_queue #
(/*AUTOINSTPARAM*/
// Parameters
.TCQ (TCQ),
.BM_CNT_WIDTH (BM_CNT_WIDTH),
.nBANK_MACHS (nBANK_MACHS),
.ORDERING (ORDERING),
.ID (ID))
bank_queue0
(/*AUTOINST*/
// Outputs
.head_r (head_r),
.tail_r (tail_r),
.idle_ns (idle_ns),
.idle_r (idle_r),
.pass_open_bank_ns (pass_open_bank_ns),
.pass_open_bank_r (pass_open_bank_r),
.auto_pre_r (auto_pre_r),
.bm_end (bm_end),
.passing_open_bank (passing_open_bank),
.ordered_issued (ordered_issued),
.ordered_r (ordered_r),
.order_q_zero (order_q_zero),
.rcv_open_bank (rcv_open_bank),
.rb_hit_busies_r (rb_hit_busies_r[nBANK_MACHS*2-1:0]),
.q_has_rd (q_has_rd),
.q_has_priority (q_has_priority),
.wait_for_maint_r (wait_for_maint_r),
// Inputs
.clk (clk),
.rst (rst),
.accept_internal_r (accept_internal_r),
.use_addr (use_addr),
.periodic_rd_ack_r (periodic_rd_ack_r),
.bm_end_in (bm_end_in[(nBANK_MACHS*2)-1:0]),
.idle_cnt (idle_cnt[BM_CNT_WIDTH-1:0]),
.rb_hit_busy_cnt (rb_hit_busy_cnt[BM_CNT_WIDTH-1:0]),
.accept_req (accept_req),
.rb_hit_busy_r (rb_hit_busy_r),
.maint_idle (maint_idle),
.maint_hit (maint_hit),
.row_hit_r (row_hit_r),
.pre_wait_r (pre_wait_r),
.allow_auto_pre (allow_auto_pre),
.sending_col (sending_col),
.req_wr_r (req_wr_r),
.rd_wr_r (rd_wr_r),
.bank_wait_in_progress (bank_wait_in_progress),
.precharge_bm_end (precharge_bm_end),
.adv_order_q (adv_order_q),
.order_cnt (order_cnt[BM_CNT_WIDTH-1:0]),
.rb_hit_busy_ns_in (rb_hit_busy_ns_in[(nBANK_MACHS*2)-1:0]),
.passing_open_bank_in (passing_open_bank_in[(nBANK_MACHS*2)-1:0]),
.was_wr (was_wr),
.maint_req_r (maint_req_r),
.was_priority (was_priority));
endmodule
|
module mc_cache
(
input mclock,
input mc_rstn,
input [3:0] mc_dev_sel,
// to/from mc
input mc_local_write_req,
input mc_local_read_req,
input mc_local_burstbegin,
input [23:0] mc_local_address,
input [127:0] mc_local_wdata,
input [15:0] mc_local_be,
input [5:0] mc_local_size,
output mc_local_ready,
output reg [127:0] mc_local_rdata,
output reg mc_local_rdata_valid,
//
// to/from ddr3
//
input ddr3_ready,
input ddr3_rdata_valid,
input [255:0] ddr3_rdata,
output reg ddr3_write_req,
output reg ddr3_read_req,
output reg ddr3_burstbegin,
output reg [23:0] ddr3_address,
output reg [4:0] ddr3_size,
output reg [255:0] ddr3_wdata,
output reg [31:0] ddr3_be,
output reg ff_rdata_pop,
output local_read_empty,
output [7:0] data_fifo_used,
output [3:0] read_cmd_used,
output read_adr_0,
output [5:0] read_count_128
);
parameter READ_IDLE = 2'b00,
READ_FIRST = 2'b01,
READ_SECOND = 2'b10;
// reg ff_rdata_pop;
// wire local_read_empty;
// wire read_adr_0;
// wire [5:0] read_count_128;
reg [1:0] read_state;
reg local_word;
reg [5:0] local_size_128;
reg [5:0] read_size;
reg read_start;
reg bb_hold;
reg ddr3_burstbegin_wr;
reg [23:1] ddr3_address_wr;
reg [4:0] ddr3_size_wr;
wire [255:0] local_rdata;
wire one_word;
wire read_cmd_empty;
reg pop_read_128;
reg z_hit;
reg z_miss;
reg z_valid;
reg [22:0] z_address;
reg z_addr_0;
reg z_rdata_valid;
reg [255:0] z_cache;
wire z_load;
assign last_word = ~|local_size_128[5:1] & local_size_128[0];
assign one_word = ~|mc_local_size[5:1] & mc_local_size[0];
// Pack Data.
always @(posedge mclock, negedge mc_rstn) begin
if(!mc_rstn) begin
local_size_128 <= 6'h0;
local_word <= 1'b0;
end
else begin
ddr3_address_wr <= mc_local_address[23:1];
ddr3_size_wr <= (mc_local_size >> 1) + (mc_local_size[0] | mc_local_address[0]);
if(mc_local_burstbegin) begin
local_size_128 <= mc_local_size - 6'h1;
local_word <= ~mc_local_address[0];
end
else if(mc_local_write_req) begin
local_size_128 <= local_size_128 - 6'h1;
local_word <= ~local_word;
end
bb_hold <= 1'b0;
casex({mc_local_write_req, mc_local_burstbegin, one_word, last_word, mc_local_address[0], local_word})
// Write one word low.
6'b111x0x: begin // Mask Hi, Write Lo, We, BB.
ddr3_be[15:0] <= mc_local_be;
ddr3_be[31:16] <= 16'h0;
ddr3_wdata[127:0] <= mc_local_wdata;
ddr3_write_req <= 1'b1;
ddr3_burstbegin_wr <= 1'b1;
end
// Write one word high
6'b111x1x: begin // Write Hi, Mask Lo, We, BB.
ddr3_be[15:0] <= 16'h0;
ddr3_be[31:16] <= mc_local_be;
ddr3_wdata[255:128] <= mc_local_wdata;
ddr3_write_req <= 1'b1;
ddr3_burstbegin_wr <= 1'b1;
end
// Write first word low
6'b110x0x: begin // Write Lo, Mask hi. No We, No BB
ddr3_be[15:0] <= mc_local_be;
ddr3_wdata[127:0] <= mc_local_wdata;
ddr3_write_req <= 1'b0;
ddr3_burstbegin_wr <= 1'b0;
bb_hold <= 1'b1;
end
// Write first word high
6'b110x1x: begin // Write Hi, Mask lo. We, BB
ddr3_be[31:16] <= mc_local_be;
ddr3_be[15:0] <= 16'h0;
ddr3_wdata[255:128] <= mc_local_wdata;
ddr3_write_req <= 1'b1;
ddr3_burstbegin_wr <= 1'b1;
end
// Normal Write Low
6'b10x0x0: begin // Mask Hi, Write Lo, No We, No BB
ddr3_be[15:0] <= mc_local_be;
ddr3_wdata[127:0] <= mc_local_wdata;
ddr3_write_req <= 1'b0;
ddr3_burstbegin_wr <= 1'b0;
end
// Normal Write High, now push.
6'b10xxx1: begin
ddr3_be[31:16] <= mc_local_be;
ddr3_wdata[255:128] <= mc_local_wdata;
ddr3_write_req <= 1'b1;
ddr3_burstbegin_wr <= bb_hold;
end
// Write last word low
6'b10x1x0: begin // Mask Hi, Write Lo, We, BB
ddr3_be[15:0] <= mc_local_be;
ddr3_be[31:16] <= 16'h0;
ddr3_wdata[127:0] <= mc_local_wdata;
ddr3_write_req <= 1'b1;
ddr3_burstbegin_wr <= 1'b0;
end
default: begin
ddr3_be <= 32'hffffffff;
ddr3_write_req <= 1'b0;
ddr3_burstbegin_wr <= 1'b0;
end
endcase
end
end
// Chech for Z in the cache.
always @* z_hit = (mc_dev_sel == 4'h8) & ({z_valid, z_address} == {1'b1, mc_local_address[23:1]});
always @* z_miss = (mc_dev_sel == 4'h8) & ({z_valid, z_address} != {1'b1, mc_local_address[23:1]});
// Read Request.
// Don't request read if there is a Z hit.
always @* begin
if(mc_local_read_req & ddr3_ready & ~z_hit) begin
ddr3_read_req = 1'b1;
ddr3_burstbegin = 1'b1;
ddr3_address = mc_local_address[23:1];
ddr3_size = (mc_local_size >> 1) + (mc_local_size[0] | mc_local_address[0]);
end
else begin
ddr3_read_req = 1'b0;
ddr3_burstbegin = ddr3_burstbegin_wr;
ddr3_address = ddr3_address_wr;
ddr3_size = ddr3_size_wr;
end
end
assign mc_local_ready = ddr3_ready;
// Z Cache.
always @(posedge mclock, negedge mc_rstn) begin
if(!mc_rstn) begin
z_valid <= 1'b0;
z_address <= 23'h0;;
end
// Z miss, load the address, valid, and enable data load..
else if(~z_hit & mc_local_read_req & (mc_dev_sel == 4'h8)) begin
z_valid <= 1'b1;
z_address <= mc_local_address[23:1];
end
end
mc_cache_fifo_256 u0_read_fifo_la
(
.clock (mclock),
.aclr (~mc_rstn),
.wrreq (ddr3_rdata_valid),
.data (ddr3_rdata),
.rdreq (ff_rdata_pop),
.almost_full (),
.empty (local_read_empty),
.full (),
.usedw (data_fifo_used),
.q (local_rdata)
);
sfifo_8x16_la u_read_128
(
.aclr (~mc_rstn),
.clock (mclock),
.wrreq (mc_local_read_req & ddr3_ready),
.data ({z_miss, mc_local_address[0], {6{~z_hit}} & mc_local_size}),
.rdreq (pop_read_128),
.q ({z_load, read_adr_0, read_count_128}),
.full (),
.empty (read_cmd_empty),
.usedw (read_cmd_used),
.almost_full ()
);
// Register to hold the Z.
always @(posedge mclock, negedge mc_rstn) begin
if(!mc_rstn) z_cache <= 256'h0;
else if(z_load & ddr3_rdata_valid) z_cache <= ddr3_rdata;
end
// Unpack data.
always @(posedge mclock, negedge mc_rstn) begin
if(!mc_rstn) begin
read_state <= READ_FIRST;
read_size <= 6'h0;
read_start <= 1'b0;
z_rdata_valid <= 1'b0;
z_addr_0 <= 1'b0;
end
else begin
z_rdata_valid <= 1'b0;
case(read_state)
READ_IDLE: begin
read_start <= read_adr_0;
if(!read_cmd_empty & (read_count_128 == 6'h0)) begin // This is a Z cache hit.
read_state <= READ_IDLE;
z_rdata_valid <= 1'b1;
z_addr_0 <= read_adr_0;
end
else if(~local_read_empty) begin
if(read_adr_0) read_state <= READ_SECOND;
else read_state <= READ_FIRST;
read_size <= read_count_128;
end
else read_state <= READ_IDLE;
end
READ_FIRST: begin
// Last word to send
if((read_size == 6'h1) & ~local_read_empty) begin
read_size <= read_size - 6'h1;
read_state <= READ_IDLE;
end
// More to send.
else if((read_size != 6'h0) & ~local_read_empty) begin
read_size <= read_size - 6'h1;
read_state <= READ_SECOND;
read_start <= ~read_start;
end
// Wait for more data.
else if((read_size != 6'h0) & local_read_empty) begin
read_state <= READ_FIRST;
end
// Done.
else read_state <= READ_IDLE;
end
READ_SECOND: begin
// Last word to send
if((read_size == 6'h1) & ~local_read_empty) begin
read_size <= read_size - 6'h1;
read_state <= READ_IDLE;
end
// More to send.
else if((read_size != 6'h0) & ~local_read_empty) begin
read_size <= read_size - 6'h1;
read_state <= READ_FIRST;
read_start <= ~read_start;
end
// Wait for more data.
else if((read_size != 6'h0) & local_read_empty) begin
read_state <= READ_SECOND;
end
// Done.
else read_state <= READ_IDLE;
end
endcase
end
end
always @* pop_read_128 = ((((read_state == READ_FIRST) | (read_state == READ_SECOND)) & (read_size == 6'h1)) & ~local_read_empty) |
((read_state == READ_IDLE) & (!read_cmd_empty & (read_count_128 == 6'h0))); // This is a Z cache hit.
always @* ff_rdata_pop = (((read_state == READ_FIRST) & (read_size == 6'h1)) | (read_state == READ_SECOND)) & ~local_read_empty;
always @* mc_local_rdata = (z_rdata_valid & z_addr_0) ? z_cache[255:128] :
(z_rdata_valid & ~z_addr_0) ? z_cache[127:0] :
(read_start) ? local_rdata[255:128] : local_rdata[127:0];
always @* mc_local_rdata_valid = (((read_state == READ_FIRST) | (read_state == READ_SECOND)) & ((read_size != 6'h0) & ~local_read_empty)) | z_rdata_valid;
endmodule
|
module block_design_xbar_0 (
aclk,
aresetn,
s_axi_awaddr,
s_axi_awprot,
s_axi_awvalid,
s_axi_awready,
s_axi_wdata,
s_axi_wstrb,
s_axi_wvalid,
s_axi_wready,
s_axi_bresp,
s_axi_bvalid,
s_axi_bready,
s_axi_araddr,
s_axi_arprot,
s_axi_arvalid,
s_axi_arready,
s_axi_rdata,
s_axi_rresp,
s_axi_rvalid,
s_axi_rready,
m_axi_awaddr,
m_axi_awprot,
m_axi_awvalid,
m_axi_awready,
m_axi_wdata,
m_axi_wstrb,
m_axi_wvalid,
m_axi_wready,
m_axi_bresp,
m_axi_bvalid,
m_axi_bready,
m_axi_araddr,
m_axi_arprot,
m_axi_arvalid,
m_axi_arready,
m_axi_rdata,
m_axi_rresp,
m_axi_rvalid,
m_axi_rready
);
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLKIF CLK" *)
input wire aclk;
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RSTIF RST" *)
input wire aresetn;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWADDR" *)
input wire [31 : 0] s_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWPROT" *)
input wire [2 : 0] s_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWVALID" *)
input wire [0 : 0] s_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWREADY" *)
output wire [0 : 0] s_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WDATA" *)
input wire [31 : 0] s_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WSTRB" *)
input wire [3 : 0] s_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WVALID" *)
input wire [0 : 0] s_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WREADY" *)
output wire [0 : 0] s_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI BRESP" *)
output wire [1 : 0] s_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI BVALID" *)
output wire [0 : 0] s_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI BREADY" *)
input wire [0 : 0] s_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARADDR" *)
input wire [31 : 0] s_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARPROT" *)
input wire [2 : 0] s_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARVALID" *)
input wire [0 : 0] s_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARREADY" *)
output wire [0 : 0] s_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RDATA" *)
output wire [31 : 0] s_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RRESP" *)
output wire [1 : 0] s_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RVALID" *)
output wire [0 : 0] s_axi_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RREADY" *)
input wire [0 : 0] s_axi_rready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWADDR [31:0] [31:0], xilinx.com:interface:aximm:1.0 M01_AXI AWADDR [31:0] [63:32]" *)
output wire [63 : 0] m_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWPROT [2:0] [2:0], xilinx.com:interface:aximm:1.0 M01_AXI AWPROT [2:0] [5:3]" *)
output wire [5 : 0] m_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI AWVALID [0:0] [1:1]" *)
output wire [1 : 0] m_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI AWREADY [0:0] [1:1]" *)
input wire [1 : 0] m_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI WDATA [31:0] [31:0], xilinx.com:interface:aximm:1.0 M01_AXI WDATA [31:0] [63:32]" *)
output wire [63 : 0] m_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI WSTRB [3:0] [3:0], xilinx.com:interface:aximm:1.0 M01_AXI WSTRB [3:0] [7:4]" *)
output wire [7 : 0] m_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI WVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI WVALID [0:0] [1:1]" *)
output wire [1 : 0] m_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI WREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI WREADY [0:0] [1:1]" *)
input wire [1 : 0] m_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI BRESP [1:0] [1:0], xilinx.com:interface:aximm:1.0 M01_AXI BRESP [1:0] [3:2]" *)
input wire [3 : 0] m_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI BVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI BVALID [0:0] [1:1]" *)
input wire [1 : 0] m_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI BREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI BREADY [0:0] [1:1]" *)
output wire [1 : 0] m_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARADDR [31:0] [31:0], xilinx.com:interface:aximm:1.0 M01_AXI ARADDR [31:0] [63:32]" *)
output wire [63 : 0] m_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARPROT [2:0] [2:0], xilinx.com:interface:aximm:1.0 M01_AXI ARPROT [2:0] [5:3]" *)
output wire [5 : 0] m_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI ARVALID [0:0] [1:1]" *)
output wire [1 : 0] m_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI ARREADY [0:0] [1:1]" *)
input wire [1 : 0] m_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RDATA [31:0] [31:0], xilinx.com:interface:aximm:1.0 M01_AXI RDATA [31:0] [63:32]" *)
input wire [63 : 0] m_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RRESP [1:0] [1:0], xilinx.com:interface:aximm:1.0 M01_AXI RRESP [1:0] [3:2]" *)
input wire [3 : 0] m_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI RVALID [0:0] [1:1]" *)
input wire [1 : 0] m_axi_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI RREADY [0:0] [1:1]" *)
output wire [1 : 0] m_axi_rready;
axi_crossbar_v2_1_10_axi_crossbar #(
.C_FAMILY("zynq"),
.C_NUM_SLAVE_SLOTS(1),
.C_NUM_MASTER_SLOTS(2),
.C_AXI_ID_WIDTH(1),
.C_AXI_ADDR_WIDTH(32),
.C_AXI_DATA_WIDTH(32),
.C_AXI_PROTOCOL(2),
.C_NUM_ADDR_RANGES(1),
.C_M_AXI_BASE_ADDR(128'H0000000043c100000000000043c00000),
.C_M_AXI_ADDR_WIDTH(64'H0000001000000010),
.C_S_AXI_BASE_ID(32'H00000000),
.C_S_AXI_THREAD_ID_WIDTH(32'H00000000),
.C_AXI_SUPPORTS_USER_SIGNALS(0),
.C_AXI_AWUSER_WIDTH(1),
.C_AXI_ARUSER_WIDTH(1),
.C_AXI_WUSER_WIDTH(1),
.C_AXI_RUSER_WIDTH(1),
.C_AXI_BUSER_WIDTH(1),
.C_M_AXI_WRITE_CONNECTIVITY(64'HFFFFFFFFFFFFFFFF),
.C_M_AXI_READ_CONNECTIVITY(64'HFFFFFFFFFFFFFFFF),
.C_R_REGISTER(0),
.C_S_AXI_SINGLE_THREAD(32'H00000001),
.C_S_AXI_WRITE_ACCEPTANCE(32'H00000001),
.C_S_AXI_READ_ACCEPTANCE(32'H00000001),
.C_M_AXI_WRITE_ISSUING(64'H0000000100000001),
.C_M_AXI_READ_ISSUING(64'H0000000100000001),
.C_S_AXI_ARB_PRIORITY(32'H00000000),
.C_M_AXI_SECURE(32'H00000000),
.C_CONNECTIVITY_MODE(0)
) inst (
.aclk(aclk),
.aresetn(aresetn),
.s_axi_awid(1'H0),
.s_axi_awaddr(s_axi_awaddr),
.s_axi_awlen(8'H00),
.s_axi_awsize(3'H0),
.s_axi_awburst(2'H0),
.s_axi_awlock(1'H0),
.s_axi_awcache(4'H0),
.s_axi_awprot(s_axi_awprot),
.s_axi_awqos(4'H0),
.s_axi_awuser(1'H0),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_awready(s_axi_awready),
.s_axi_wid(1'H0),
.s_axi_wdata(s_axi_wdata),
.s_axi_wstrb(s_axi_wstrb),
.s_axi_wlast(1'H1),
.s_axi_wuser(1'H0),
.s_axi_wvalid(s_axi_wvalid),
.s_axi_wready(s_axi_wready),
.s_axi_bid(),
.s_axi_bresp(s_axi_bresp),
.s_axi_buser(),
.s_axi_bvalid(s_axi_bvalid),
.s_axi_bready(s_axi_bready),
.s_axi_arid(1'H0),
.s_axi_araddr(s_axi_araddr),
.s_axi_arlen(8'H00),
.s_axi_arsize(3'H0),
.s_axi_arburst(2'H0),
.s_axi_arlock(1'H0),
.s_axi_arcache(4'H0),
.s_axi_arprot(s_axi_arprot),
.s_axi_arqos(4'H0),
.s_axi_aruser(1'H0),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_arready(s_axi_arready),
.s_axi_rid(),
.s_axi_rdata(s_axi_rdata),
.s_axi_rresp(s_axi_rresp),
.s_axi_rlast(),
.s_axi_ruser(),
.s_axi_rvalid(s_axi_rvalid),
.s_axi_rready(s_axi_rready),
.m_axi_awid(),
.m_axi_awaddr(m_axi_awaddr),
.m_axi_awlen(),
.m_axi_awsize(),
.m_axi_awburst(),
.m_axi_awlock(),
.m_axi_awcache(),
.m_axi_awprot(m_axi_awprot),
.m_axi_awregion(),
.m_axi_awqos(),
.m_axi_awuser(),
.m_axi_awvalid(m_axi_awvalid),
.m_axi_awready(m_axi_awready),
.m_axi_wid(),
.m_axi_wdata(m_axi_wdata),
.m_axi_wstrb(m_axi_wstrb),
.m_axi_wlast(),
.m_axi_wuser(),
.m_axi_wvalid(m_axi_wvalid),
.m_axi_wready(m_axi_wready),
.m_axi_bid(2'H0),
.m_axi_bresp(m_axi_bresp),
.m_axi_buser(2'H0),
.m_axi_bvalid(m_axi_bvalid),
.m_axi_bready(m_axi_bready),
.m_axi_arid(),
.m_axi_araddr(m_axi_araddr),
.m_axi_arlen(),
.m_axi_arsize(),
.m_axi_arburst(),
.m_axi_arlock(),
.m_axi_arcache(),
.m_axi_arprot(m_axi_arprot),
.m_axi_arregion(),
.m_axi_arqos(),
.m_axi_aruser(),
.m_axi_arvalid(m_axi_arvalid),
.m_axi_arready(m_axi_arready),
.m_axi_rid(2'H0),
.m_axi_rdata(m_axi_rdata),
.m_axi_rresp(m_axi_rresp),
.m_axi_rlast(2'H3),
.m_axi_ruser(2'H0),
.m_axi_rvalid(m_axi_rvalid),
.m_axi_rready(m_axi_rready)
);
endmodule
|
module sky130_fd_sc_hs__fahcon (
//# {{data|Data Signals}}
input A ,
input B ,
input CI ,
output COUT_N,
output SUM ,
//# {{power|Power}}
input VPWR ,
input VGND
);
endmodule
|
module 17var_multi (A, B, C, D, E, F, G, H, I, J, K, L, M, N, O, P, Q, valid);
input A, B, C, D, E, F, G, H, I, J, K, L, M, N, O, P, Q;
output valid;
wire [8:0] min_value = 9'd120;
wire [8:0] max_weight = 9'd60;
wire [8:0] max_volume = 9'd60;
wire [8:0] total_value =
A * 9'd4
+ B * 9'd8
+ C * 9'd0
+ D * 9'd20
+ E * 9'd10
+ F * 9'd12
+ G * 9'd18
+ H * 9'd14
+ I * 9'd6
+ J * 9'd15
+ K * 9'd30
+ L * 9'd8
+ M * 9'd16
+ N * 9'd18
+ O * 9'd18
+ P * 9'd14
+ Q * 9'd7;
wire [8:0] total_weight =
A * 9'd28
+ B * 9'd8
+ C * 9'd27
+ D * 9'd18
+ E * 9'd27
+ F * 9'd28
+ G * 9'd6
+ H * 9'd1
+ I * 9'd20
+ J * 9'd0
+ K * 9'd5
+ L * 9'd13
+ M * 9'd8
+ N * 9'd14
+ O * 9'd22
+ P * 9'd12
+ Q * 9'd23;
wire [8:0] total_volume =
A * 9'd27
+ B * 9'd27
+ C * 9'd4
+ D * 9'd4
+ E * 9'd0
+ F * 9'd24
+ G * 9'd4
+ H * 9'd20
+ I * 9'd12
+ J * 9'd15
+ K * 9'd5
+ L * 9'd2
+ M * 9'd9
+ N * 9'd28
+ O * 9'd19
+ P * 9'd18
+ Q * 9'd30;
assign valid = ((total_value >= min_value) && (total_weight <= max_weight) && (total_volume <= max_volume));
endmodule
|
module Approx_adder_W16 ( add_sub, in1, in2, res );
input [15:0] in1;
input [15:0] in2;
output [16:0] res;
input add_sub;
wire n58, n59, n60, n61, n62, n63, n64, n65, n66, n67, n68, n69, n70, n71,
n72, n73, n74, n75, n76, n77, n78, n79, n80, n81, n82, n83, n84, n85,
n86, n87, n88, n89, n90, n91, n92, n93, n94, n95, n96, n97, n98, n99,
n100, n101, n102, n103, n104, n105, n106, n107, n108, n109, n110,
n111, n112, n113, n114, n115, n116, n117, n118, n119, n120, n121,
n122, n123, n124, n125, n126, n127, n128, n129, n130, n131, n132,
n133, n134, n135, n136, n137, n138, n139, n140, n141, n142, n143,
n144, n145, n146, n147, n148, n149, n150, n151, n152, n153, n154,
n155, n156, n157, n158, n159, n160, n161, n162, n163, n164, n165,
n166, n167, n168, n169, n170, n171, n172, n173, n174, n175, n176,
n177, n178, n179, n180, n181, n182, n183, n184;
OA21XLTS U74 ( .A0(n181), .A1(n183), .B0(n161), .Y(n131) );
NAND2X1TS U75 ( .A(n64), .B(n63), .Y(n182) );
NAND2X1TS U76 ( .A(n117), .B(in1[3]), .Y(n161) );
XNOR2X2TS U77 ( .A(n69), .B(in2[15]), .Y(n112) );
NAND2X1TS U78 ( .A(n100), .B(in1[10]), .Y(n136) );
NAND2X1TS U79 ( .A(n70), .B(add_sub), .Y(n71) );
NAND2X1TS U80 ( .A(in1[2]), .B(n59), .Y(n181) );
CMPR32X2TS U81 ( .A(n157), .B(in1[7]), .C(n156), .CO(n170), .S(res[7]) );
XOR2X2TS U82 ( .A(n73), .B(in2[13]), .Y(n107) );
NOR2X1TS U83 ( .A(n72), .B(n101), .Y(n73) );
NAND2XLTS U84 ( .A(n98), .B(add_sub), .Y(n99) );
NOR2XLTS U85 ( .A(n102), .B(n101), .Y(n103) );
XOR2X2TS U86 ( .A(n91), .B(in2[9]), .Y(n95) );
NOR2X1TS U87 ( .A(n90), .B(n101), .Y(n91) );
INVX2TS U88 ( .A(add_sub), .Y(n101) );
NOR2XLTS U89 ( .A(n101), .B(n60), .Y(n61) );
XOR2X1TS U90 ( .A(n103), .B(in2[11]), .Y(n104) );
NAND2X1TS U91 ( .A(n106), .B(in1[12]), .Y(n145) );
NOR2X6TS U92 ( .A(n92), .B(in2[8]), .Y(n90) );
NAND2X2TS U93 ( .A(n79), .B(add_sub), .Y(n80) );
NAND2X2TS U94 ( .A(n177), .B(n176), .Y(n178) );
XNOR2X2TS U95 ( .A(n75), .B(in2[12]), .Y(n106) );
NAND2X2TS U96 ( .A(n74), .B(add_sub), .Y(n75) );
NOR2X6TS U97 ( .A(n79), .B(in2[6]), .Y(n77) );
AO21X2TS U98 ( .A0(n114), .A1(n174), .B0(n113), .Y(res[16]) );
XOR2X1TS U99 ( .A(n155), .B(n154), .Y(res[13]) );
AOI21X2TS U100 ( .A0(n151), .A1(n150), .B0(n149), .Y(n155) );
NAND2X2TS U101 ( .A(n107), .B(in1[13]), .Y(n152) );
XOR2X1TS U102 ( .A(n129), .B(n128), .Y(res[9]) );
XNOR2X2TS U103 ( .A(n99), .B(in2[10]), .Y(n100) );
XOR2X1TS U104 ( .A(n166), .B(n165), .Y(res[6]) );
XNOR2X2TS U105 ( .A(n93), .B(in2[8]), .Y(n94) );
XOR2X1TS U106 ( .A(n121), .B(n158), .Y(res[5]) );
NOR2X1TS U107 ( .A(n164), .B(n163), .Y(n165) );
AND2X2TS U108 ( .A(n88), .B(in1[6]), .Y(n163) );
OA21XLTS U109 ( .A0(n64), .A1(n63), .B0(n182), .Y(res[2]) );
INVX1TS U110 ( .A(n158), .Y(n162) );
XOR2XLTS U111 ( .A(n180), .B(n122), .Y(res[1]) );
XOR2X1TS U112 ( .A(n130), .B(in1[1]), .Y(n122) );
OAI21X1TS U113 ( .A0(n180), .A1(in1[1]), .B0(n130), .Y(n62) );
AOI2BB1XLTS U114 ( .A0N(in2[0]), .A1N(in1[0]), .B0(n180), .Y(res[0]) );
OAI21X1TS U115 ( .A0(in2[1]), .A1(in2[0]), .B0(add_sub), .Y(n58) );
OAI21X1TS U116 ( .A0(n131), .A1(n160), .B0(n119), .Y(n121) );
NAND2X4TS U117 ( .A(n118), .B(in1[4]), .Y(n119) );
XNOR2X2TS U118 ( .A(n116), .B(in2[3]), .Y(n117) );
NAND2BX4TS U119 ( .AN(in2[7]), .B(n77), .Y(n92) );
XNOR2X2TS U120 ( .A(n82), .B(in2[4]), .Y(n118) );
NAND2X1TS U121 ( .A(n81), .B(add_sub), .Y(n82) );
XNOR2X2TS U122 ( .A(n84), .B(in2[5]), .Y(n120) );
NAND2X2TS U123 ( .A(n92), .B(add_sub), .Y(n93) );
NOR2BX2TS U124 ( .AN(in1[0]), .B(n60), .Y(n180) );
OAI21X2TS U125 ( .A0(n118), .A1(in1[4]), .B0(n119), .Y(n160) );
INVX2TS U126 ( .A(n167), .Y(n124) );
NAND2BX2TS U127 ( .AN(in2[13]), .B(n72), .Y(n70) );
INVX2TS U128 ( .A(n163), .Y(n89) );
NAND2X1TS U129 ( .A(n168), .B(n167), .Y(n169) );
XOR2XLTS U130 ( .A(n139), .B(n138), .Y(res[10]) );
NAND2X1TS U131 ( .A(n150), .B(n145), .Y(n146) );
NOR2X4TS U132 ( .A(n95), .B(in1[9]), .Y(n125) );
AOI21X2TS U133 ( .A0(n89), .A1(n159), .B0(n164), .Y(n156) );
NOR2X4TS U134 ( .A(n112), .B(in1[15]), .Y(n175) );
OAI21X4TS U135 ( .A0(n110), .A1(n144), .B0(n109), .Y(n174) );
AOI21X4TS U136 ( .A0(n143), .A1(n141), .B0(n105), .Y(n144) );
AOI21X2TS U137 ( .A0(n153), .A1(n149), .B0(n108), .Y(n109) );
NAND2BX4TS U138 ( .AN(in2[9]), .B(n90), .Y(n98) );
XNOR2X4TS U139 ( .A(n71), .B(in2[14]), .Y(n111) );
OAI21X4TS U140 ( .A0(n119), .A1(n85), .B0(n120), .Y(n86) );
XNOR2X4TS U141 ( .A(n80), .B(in2[6]), .Y(n88) );
XNOR2X1TS U142 ( .A(n58), .B(in2[2]), .Y(n59) );
OAI21X1TS U143 ( .A0(in1[2]), .A1(n59), .B0(n181), .Y(n133) );
INVX2TS U144 ( .A(n133), .Y(n64) );
INVX4TS U145 ( .A(in2[0]), .Y(n60) );
CLKXOR2X2TS U146 ( .A(n61), .B(in2[1]), .Y(n130) );
OAI2BB1X1TS U147 ( .A0N(n180), .A1N(in1[1]), .B0(n62), .Y(n63) );
INVX2TS U148 ( .A(in2[1]), .Y(n67) );
INVX2TS U149 ( .A(in2[2]), .Y(n66) );
INVX2TS U150 ( .A(in2[3]), .Y(n65) );
NAND4X4TS U151 ( .A(n60), .B(n67), .C(n66), .D(n65), .Y(n81) );
NOR2X4TS U152 ( .A(n81), .B(in2[4]), .Y(n83) );
INVX2TS U153 ( .A(in2[5]), .Y(n68) );
NAND2X4TS U154 ( .A(n83), .B(n68), .Y(n79) );
NOR2X4TS U155 ( .A(n98), .B(in2[10]), .Y(n102) );
NAND2BX4TS U156 ( .AN(in2[11]), .B(n102), .Y(n74) );
NOR2X4TS U157 ( .A(n74), .B(in2[12]), .Y(n72) );
OAI21X1TS U158 ( .A0(n70), .A1(in2[14]), .B0(add_sub), .Y(n69) );
NOR2X2TS U159 ( .A(n111), .B(in1[14]), .Y(n147) );
NOR2X1TS U160 ( .A(n175), .B(n147), .Y(n114) );
OR2X2TS U161 ( .A(n107), .B(in1[13]), .Y(n153) );
NOR2X1TS U162 ( .A(n106), .B(in1[12]), .Y(n76) );
INVX2TS U163 ( .A(n76), .Y(n150) );
NAND2X2TS U164 ( .A(n153), .B(n150), .Y(n110) );
NOR2X1TS U165 ( .A(n77), .B(n101), .Y(n78) );
XOR2X1TS U166 ( .A(n78), .B(in2[7]), .Y(n157) );
INVX2TS U167 ( .A(n119), .Y(n87) );
INVX2TS U168 ( .A(in1[5]), .Y(n85) );
NOR2X1TS U169 ( .A(n83), .B(n101), .Y(n84) );
OAI21X4TS U170 ( .A0(n87), .A1(in1[5]), .B0(n86), .Y(n159) );
NOR2X2TS U171 ( .A(n88), .B(in1[6]), .Y(n164) );
NOR2X2TS U172 ( .A(n94), .B(in1[8]), .Y(n123) );
NOR2X1TS U173 ( .A(n125), .B(n123), .Y(n97) );
NAND2X2TS U174 ( .A(n94), .B(in1[8]), .Y(n167) );
NAND2X2TS U175 ( .A(n95), .B(in1[9]), .Y(n126) );
OAI21X1TS U176 ( .A0(n125), .A1(n167), .B0(n126), .Y(n96) );
AOI21X4TS U177 ( .A0(n170), .A1(n97), .B0(n96), .Y(n139) );
NOR2X2TS U178 ( .A(n100), .B(in1[10]), .Y(n135) );
OAI21X4TS U179 ( .A0(n139), .A1(n135), .B0(n136), .Y(n143) );
OR2X2TS U180 ( .A(n104), .B(in1[11]), .Y(n141) );
NAND2X2TS U181 ( .A(n104), .B(in1[11]), .Y(n140) );
INVX2TS U182 ( .A(n140), .Y(n105) );
INVX2TS U183 ( .A(n145), .Y(n149) );
INVX2TS U184 ( .A(n152), .Y(n108) );
NAND2X2TS U185 ( .A(n111), .B(in1[14]), .Y(n171) );
NAND2X2TS U186 ( .A(n112), .B(in1[15]), .Y(n176) );
OAI21X1TS U187 ( .A0(n175), .A1(n171), .B0(n176), .Y(n113) );
OR3X1TS U188 ( .A(in2[2]), .B(in2[1]), .C(in2[0]), .Y(n115) );
NAND2X1TS U189 ( .A(add_sub), .B(n115), .Y(n116) );
OAI21X2TS U190 ( .A0(n117), .A1(in1[3]), .B0(n161), .Y(n183) );
XNOR2X1TS U191 ( .A(n120), .B(in1[5]), .Y(n158) );
INVX2TS U192 ( .A(n123), .Y(n168) );
AOI21X1TS U193 ( .A0(n170), .A1(n168), .B0(n124), .Y(n129) );
INVX2TS U194 ( .A(n125), .Y(n127) );
NAND2X1TS U195 ( .A(n127), .B(n126), .Y(n128) );
NAND2X1TS U196 ( .A(n130), .B(in1[1]), .Y(n132) );
OAI31X1TS U197 ( .A0(n133), .A1(n183), .A2(n132), .B0(n131), .Y(n134) );
XNOR2X1TS U198 ( .A(n134), .B(n160), .Y(res[4]) );
INVX2TS U199 ( .A(n135), .Y(n137) );
NAND2X1TS U200 ( .A(n137), .B(n136), .Y(n138) );
NAND2X1TS U201 ( .A(n141), .B(n140), .Y(n142) );
XNOR2X1TS U202 ( .A(n143), .B(n142), .Y(res[11]) );
INVX2TS U203 ( .A(n144), .Y(n151) );
XNOR2X1TS U204 ( .A(n151), .B(n146), .Y(res[12]) );
INVX2TS U205 ( .A(n147), .Y(n173) );
NAND2X1TS U206 ( .A(n173), .B(n171), .Y(n148) );
XNOR2X1TS U207 ( .A(n174), .B(n148), .Y(res[14]) );
NAND2X1TS U208 ( .A(n153), .B(n152), .Y(n154) );
OAI31X1TS U209 ( .A0(n162), .A1(n161), .A2(n160), .B0(n159), .Y(n166) );
XNOR2X1TS U210 ( .A(n170), .B(n169), .Y(res[8]) );
INVX2TS U211 ( .A(n171), .Y(n172) );
AOI21X4TS U212 ( .A0(n174), .A1(n173), .B0(n172), .Y(n179) );
INVX2TS U213 ( .A(n175), .Y(n177) );
XOR2X1TS U214 ( .A(n179), .B(n178), .Y(res[15]) );
NAND2X1TS U215 ( .A(n182), .B(n181), .Y(n184) );
XNOR2X1TS U216 ( .A(n184), .B(n183), .Y(res[3]) );
initial $sdf_annotate("Approx_adder_add_approx_flow_syn_constraints.tcl_GDAN8M8P3_syn.sdf");
endmodule
|
module fpga_core
(
// clocks
input wire clk_250mhz_int,
input wire rst_250mhz_int,
input wire clk_250mhz,
input wire rst_250mhz,
input wire clk_10mhz,
input wire rst_10mhz,
input wire ext_clock_selected,
// SoC interface
input wire cntrl_cs,
input wire cntrl_sck,
input wire cntrl_mosi,
output wire cntrl_miso,
// Trigger
input wire ext_trig,
// Frequency counter
input wire ext_prescale,
// Front end relay control
output wire ferc_dat,
output wire ferc_clk,
output wire ferc_lat,
// Analog mux
output wire [2:0] mux_s,
// ADC
output wire adc_sclk,
input wire adc_sdo,
output wire adc_sdi,
output wire adc_cs,
input wire adc_eoc,
output wire adc_convst,
// digital output
output wire [15:0] dout,
// Sync DAC
output wire [7:0] sync_dac,
// Main DAC
output wire dac_clk,
output wire [15:0] dac_p1_d,
output wire [15:0] dac_p2_d,
input wire dac_sdo,
output wire dac_sdio,
output wire dac_sclk,
output wire dac_csb,
output wire dac_reset,
// ram 1 MCB (U8)
input wire ram1_calib_done,
output wire ram1_p0_cmd_clk,
output wire ram1_p0_cmd_en,
output wire [2:0] ram1_p0_cmd_instr,
output wire [5:0] ram1_p0_cmd_bl,
output wire [31:0] ram1_p0_cmd_byte_addr,
input wire ram1_p0_cmd_empty,
input wire ram1_p0_cmd_full,
output wire ram1_p0_wr_clk,
output wire ram1_p0_wr_en,
output wire [3:0] ram1_p0_wr_mask,
output wire [31:0] ram1_p0_wr_data,
input wire ram1_p0_wr_empty,
input wire ram1_p0_wr_full,
input wire ram1_p0_wr_underrun,
input wire [6:0] ram1_p0_wr_count,
input wire ram1_p0_wr_error,
output wire ram1_p0_rd_clk,
output wire ram1_p0_rd_en,
input wire [31:0] ram1_p0_rd_data,
input wire ram1_p0_rd_empty,
input wire ram1_p0_rd_full,
input wire ram1_p0_rd_overflow,
input wire [6:0] ram1_p0_rd_count,
input wire ram1_p0_rd_error,
output wire ram1_p1_cmd_clk,
output wire ram1_p1_cmd_en,
output wire [2:0] ram1_p1_cmd_instr,
output wire [5:0] ram1_p1_cmd_bl,
output wire [31:0] ram1_p1_cmd_byte_addr,
input wire ram1_p1_cmd_empty,
input wire ram1_p1_cmd_full,
output wire ram1_p1_wr_clk,
output wire ram1_p1_wr_en,
output wire [3:0] ram1_p1_wr_mask,
output wire [31:0] ram1_p1_wr_data,
input wire ram1_p1_wr_empty,
input wire ram1_p1_wr_full,
input wire ram1_p1_wr_underrun,
input wire [6:0] ram1_p1_wr_count,
input wire ram1_p1_wr_error,
output wire ram1_p1_rd_clk,
output wire ram1_p1_rd_en,
input wire [31:0] ram1_p1_rd_data,
input wire ram1_p1_rd_empty,
input wire ram1_p1_rd_full,
input wire ram1_p1_rd_overflow,
input wire [6:0] ram1_p1_rd_count,
input wire ram1_p1_rd_error,
output wire ram1_p2_cmd_clk,
output wire ram1_p2_cmd_en,
output wire [2:0] ram1_p2_cmd_instr,
output wire [5:0] ram1_p2_cmd_bl,
output wire [31:0] ram1_p2_cmd_byte_addr,
input wire ram1_p2_cmd_empty,
input wire ram1_p2_cmd_full,
output wire ram1_p2_rd_clk,
output wire ram1_p2_rd_en,
input wire [31:0] ram1_p2_rd_data,
input wire ram1_p2_rd_empty,
input wire ram1_p2_rd_full,
input wire ram1_p2_rd_overflow,
input wire [6:0] ram1_p2_rd_count,
input wire ram1_p2_rd_error,
output wire ram1_p3_cmd_clk,
output wire ram1_p3_cmd_en,
output wire [2:0] ram1_p3_cmd_instr,
output wire [5:0] ram1_p3_cmd_bl,
output wire [31:0] ram1_p3_cmd_byte_addr,
input wire ram1_p3_cmd_empty,
input wire ram1_p3_cmd_full,
output wire ram1_p3_rd_clk,
output wire ram1_p3_rd_en,
input wire [31:0] ram1_p3_rd_data,
input wire ram1_p3_rd_empty,
input wire ram1_p3_rd_full,
input wire ram1_p3_rd_overflow,
input wire [6:0] ram1_p3_rd_count,
input wire ram1_p3_rd_error,
output wire ram1_p4_cmd_clk,
output wire ram1_p4_cmd_en,
output wire [2:0] ram1_p4_cmd_instr,
output wire [5:0] ram1_p4_cmd_bl,
output wire [31:0] ram1_p4_cmd_byte_addr,
input wire ram1_p4_cmd_empty,
input wire ram1_p4_cmd_full,
output wire ram1_p4_rd_clk,
output wire ram1_p4_rd_en,
input wire [31:0] ram1_p4_rd_data,
input wire ram1_p4_rd_empty,
input wire ram1_p4_rd_full,
input wire ram1_p4_rd_overflow,
input wire [6:0] ram1_p4_rd_count,
input wire ram1_p4_rd_error,
output wire ram1_p5_cmd_clk,
output wire ram1_p5_cmd_en,
output wire [2:0] ram1_p5_cmd_instr,
output wire [5:0] ram1_p5_cmd_bl,
output wire [31:0] ram1_p5_cmd_byte_addr,
input wire ram1_p5_cmd_empty,
input wire ram1_p5_cmd_full,
output wire ram1_p5_rd_clk,
output wire ram1_p5_rd_en,
input wire [31:0] ram1_p5_rd_data,
input wire ram1_p5_rd_empty,
input wire ram1_p5_rd_full,
input wire ram1_p5_rd_overflow,
input wire [6:0] ram1_p5_rd_count,
input wire ram1_p5_rd_error,
// ram 2 MCB (U12)
input wire ram2_calib_done,
output wire ram2_p0_cmd_clk,
output wire ram2_p0_cmd_en,
output wire [2:0] ram2_p0_cmd_instr,
output wire [5:0] ram2_p0_cmd_bl,
output wire [31:0] ram2_p0_cmd_byte_addr,
input wire ram2_p0_cmd_empty,
input wire ram2_p0_cmd_full,
output wire ram2_p0_wr_clk,
output wire ram2_p0_wr_en,
output wire [3:0] ram2_p0_wr_mask,
output wire [31:0] ram2_p0_wr_data,
input wire ram2_p0_wr_empty,
input wire ram2_p0_wr_full,
input wire ram2_p0_wr_underrun,
input wire [6:0] ram2_p0_wr_count,
input wire ram2_p0_wr_error,
output wire ram2_p0_rd_clk,
output wire ram2_p0_rd_en,
input wire [31:0] ram2_p0_rd_data,
input wire ram2_p0_rd_empty,
input wire ram2_p0_rd_full,
input wire ram2_p0_rd_overflow,
input wire [6:0] ram2_p0_rd_count,
input wire ram2_p0_rd_error,
output wire ram2_p1_cmd_clk,
output wire ram2_p1_cmd_en,
output wire [2:0] ram2_p1_cmd_instr,
output wire [5:0] ram2_p1_cmd_bl,
output wire [31:0] ram2_p1_cmd_byte_addr,
input wire ram2_p1_cmd_empty,
input wire ram2_p1_cmd_full,
output wire ram2_p1_wr_clk,
output wire ram2_p1_wr_en,
output wire [3:0] ram2_p1_wr_mask,
output wire [31:0] ram2_p1_wr_data,
input wire ram2_p1_wr_empty,
input wire ram2_p1_wr_full,
input wire ram2_p1_wr_underrun,
input wire [6:0] ram2_p1_wr_count,
input wire ram2_p1_wr_error,
output wire ram2_p1_rd_clk,
output wire ram2_p1_rd_en,
input wire [31:0] ram2_p1_rd_data,
input wire ram2_p1_rd_empty,
input wire ram2_p1_rd_full,
input wire ram2_p1_rd_overflow,
input wire [6:0] ram2_p1_rd_count,
input wire ram2_p1_rd_error,
output wire ram2_p2_cmd_clk,
output wire ram2_p2_cmd_en,
output wire [2:0] ram2_p2_cmd_instr,
output wire [5:0] ram2_p2_cmd_bl,
output wire [31:0] ram2_p2_cmd_byte_addr,
input wire ram2_p2_cmd_empty,
input wire ram2_p2_cmd_full,
output wire ram2_p2_rd_clk,
output wire ram2_p2_rd_en,
input wire [31:0] ram2_p2_rd_data,
input wire ram2_p2_rd_empty,
input wire ram2_p2_rd_full,
input wire ram2_p2_rd_overflow,
input wire [6:0] ram2_p2_rd_count,
input wire ram2_p2_rd_error,
output wire ram2_p3_cmd_clk,
output wire ram2_p3_cmd_en,
output wire [2:0] ram2_p3_cmd_instr,
output wire [5:0] ram2_p3_cmd_bl,
output wire [31:0] ram2_p3_cmd_byte_addr,
input wire ram2_p3_cmd_empty,
input wire ram2_p3_cmd_full,
output wire ram2_p3_rd_clk,
output wire ram2_p3_rd_en,
input wire [31:0] ram2_p3_rd_data,
input wire ram2_p3_rd_empty,
input wire ram2_p3_rd_full,
input wire ram2_p3_rd_overflow,
input wire [6:0] ram2_p3_rd_count,
input wire ram2_p3_rd_error,
output wire ram2_p4_cmd_clk,
output wire ram2_p4_cmd_en,
output wire [2:0] ram2_p4_cmd_instr,
output wire [5:0] ram2_p4_cmd_bl,
output wire [31:0] ram2_p4_cmd_byte_addr,
input wire ram2_p4_cmd_empty,
input wire ram2_p4_cmd_full,
output wire ram2_p4_rd_clk,
output wire ram2_p4_rd_en,
input wire [31:0] ram2_p4_rd_data,
input wire ram2_p4_rd_empty,
input wire ram2_p4_rd_full,
input wire ram2_p4_rd_overflow,
input wire [6:0] ram2_p4_rd_count,
input wire ram2_p4_rd_error,
output wire ram2_p5_cmd_clk,
output wire ram2_p5_cmd_en,
output wire [2:0] ram2_p5_cmd_instr,
output wire [5:0] ram2_p5_cmd_bl,
output wire [31:0] ram2_p5_cmd_byte_addr,
input wire ram2_p5_cmd_empty,
input wire ram2_p5_cmd_full,
output wire ram2_p5_rd_clk,
output wire ram2_p5_rd_en,
input wire [31:0] ram2_p5_rd_data,
input wire ram2_p5_rd_empty,
input wire ram2_p5_rd_full,
input wire ram2_p5_rd_overflow,
input wire [6:0] ram2_p5_rd_count,
input wire ram2_p5_rd_error
);
reg [15:0] count = 0;
assign ferc_dat = 0;
assign ferc_lat = 0;
assign ferc_clk = 0;
assign mux_s = 0;
assign adc_sclk = 0;
assign adc_sdi = 0;
assign adc_cs = 0;
assign adc_convst = 0;
assign dac_clk = clk_250mhz;
reg [15:0] dac_p1_d_reg = 0;
reg [15:0] dac_p2_d_reg = 0;
always @(posedge clk_250mhz) begin
dac_p1_d_reg <= count;
dac_p2_d_reg <= -count;
end
assign dac_p1_d = dac_p1_d_reg;
assign dac_p2_d = dac_p2_d_reg;
assign dac_sdio = 0;
assign dac_sclk = 0;
assign dac_csb = 0;
assign dac_reset = 0;
assign sync_dac = count[15:8];
assign dout = count;
always @(posedge clk_250mhz) begin
count <= count + 1;
end
/////////////////////////////////////////////////
// //
// DDR2 RX path SRL FIFOs //
// //
/////////////////////////////////////////////////
// These help timing closure with the MCB read data path since Tmcbcko_RDDATA
// is a very high 2.7 ns. A LUT in SRL mode has a very low Tds of 90 ps,
// compared to a LUT in RAM mode (Tds 730 ps) or a FF (Tdick 470 ps).
wire ram1_p0_rd_en_fifo;
wire [31:0] ram1_p0_rd_data_fifo;
wire ram1_p0_rd_empty_fifo;
wire ram1_p0_rd_full_fifo;
srl_fifo_reg #(
.WIDTH(32)
)
ram1_p0_rd_fifo (
.clk(ram1_p0_rd_clk),
.rst(rst_250mhz_int),
.write_en(~ram1_p0_rd_empty),
.write_data(ram1_p0_rd_data),
.read_en(ram1_p0_rd_en_fifo),
.read_data(ram1_p0_rd_data_fifo),
.full(ram1_p0_rd_full_fifo),
.empty(ram1_p0_rd_empty_fifo)
);
assign ram1_p0_rd_en = ~ram1_p0_rd_full;
wire ram1_p1_rd_en_fifo;
wire [31:0] ram1_p1_rd_data_fifo;
wire ram1_p1_rd_empty_fifo;
wire ram1_p1_rd_full_fifo;
srl_fifo_reg #(
.WIDTH(32)
)
ram1_p1_rd_fifo (
.clk(ram1_p1_rd_clk),
.rst(rst_250mhz_int),
.write_en(~ram1_p1_rd_empty),
.write_data(ram1_p1_rd_data),
.read_en(ram1_p1_rd_en_fifo),
.read_data(ram1_p1_rd_data_fifo),
.full(ram1_p1_rd_full_fifo),
.empty(ram1_p1_rd_empty_fifo)
);
assign ram1_p1_rd_en = ~ram1_p1_rd_full;
wire ram1_p2_rd_en_fifo;
wire [31:0] ram1_p2_rd_data_fifo;
wire ram1_p2_rd_empty_fifo;
wire ram1_p2_rd_full_fifo;
srl_fifo_reg #(
.WIDTH(32)
)
ram1_p2_rd_fifo (
.clk(ram1_p2_rd_clk),
.rst(rst_250mhz_int),
.write_en(~ram1_p2_rd_empty),
.write_data(ram1_p2_rd_data),
.read_en(ram1_p2_rd_en_fifo),
.read_data(ram1_p2_rd_data_fifo),
.full(ram1_p2_rd_full_fifo),
.empty(ram1_p2_rd_empty_fifo)
);
assign ram1_p2_rd_en = ~ram1_p2_rd_full;
wire ram1_p3_rd_en_fifo;
wire [31:0] ram1_p3_rd_data_fifo;
wire ram1_p3_rd_empty_fifo;
wire ram1_p3_rd_full_fifo;
srl_fifo_reg #(
.WIDTH(32)
)
ram1_p3_rd_fifo (
.clk(ram1_p3_rd_clk),
.rst(rst_250mhz_int),
.write_en(~ram1_p3_rd_empty),
.write_data(ram1_p3_rd_data),
.read_en(ram1_p3_rd_en_fifo),
.read_data(ram1_p3_rd_data_fifo),
.full(ram1_p3_rd_full_fifo),
.empty(ram1_p3_rd_empty_fifo)
);
assign ram1_p3_rd_en = ~ram1_p3_rd_full;
wire ram1_p4_rd_en_fifo;
wire [31:0] ram1_p4_rd_data_fifo;
wire ram1_p4_rd_empty_fifo;
wire ram1_p4_rd_full_fifo;
srl_fifo_reg #(
.WIDTH(32)
)
ram1_p4_rd_fifo (
.clk(ram1_p4_rd_clk),
.rst(rst_250mhz_int),
.write_en(~ram1_p4_rd_empty),
.write_data(ram1_p4_rd_data),
.read_en(ram1_p4_rd_en_fifo),
.read_data(ram1_p4_rd_data_fifo),
.full(ram1_p4_rd_full_fifo),
.empty(ram1_p4_rd_empty_fifo)
);
assign ram1_p4_rd_en = ~ram1_p4_rd_full;
wire ram1_p5_rd_en_fifo;
wire [31:0] ram1_p5_rd_data_fifo;
wire ram1_p5_rd_empty_fifo;
wire ram1_p5_rd_full_fifo;
srl_fifo_reg #(
.WIDTH(32)
)
ram1_p5_rd_fifo (
.clk(ram1_p5_rd_clk),
.rst(rst_250mhz_int),
.write_en(~ram1_p5_rd_empty),
.write_data(ram1_p5_rd_data),
.read_en(ram1_p5_rd_en_fifo),
.read_data(ram1_p5_rd_data_fifo),
.full(ram1_p5_rd_full_fifo),
.empty(ram1_p5_rd_empty_fifo)
);
assign ram1_p5_rd_en = ~ram1_p5_rd_full;
wire ram2_p0_rd_en_fifo;
wire [31:0] ram2_p0_rd_data_fifo;
wire ram2_p0_rd_empty_fifo;
wire ram2_p0_rd_full_fifo;
srl_fifo_reg #(
.WIDTH(32)
)
ram2_p0_rd_fifo (
.clk(ram2_p0_rd_clk),
.rst(rst_250mhz_int),
.write_en(~ram2_p0_rd_empty),
.write_data(ram2_p0_rd_data),
.read_en(ram2_p0_rd_en_fifo),
.read_data(ram2_p0_rd_data_fifo),
.full(ram2_p0_rd_full_fifo),
.empty(ram2_p0_rd_empty_fifo)
);
assign ram2_p0_rd_en = ~ram2_p0_rd_full;
wire ram2_p1_rd_en_fifo;
wire [31:0] ram2_p1_rd_data_fifo;
wire ram2_p1_rd_empty_fifo;
wire ram2_p1_rd_full_fifo;
srl_fifo_reg #(
.WIDTH(32)
)
ram2_p1_rd_fifo (
.clk(ram2_p1_rd_clk),
.rst(rst_250mhz_int),
.write_en(~ram2_p1_rd_empty),
.write_data(ram2_p1_rd_data),
.read_en(ram2_p1_rd_en_fifo),
.read_data(ram2_p1_rd_data_fifo),
.full(ram2_p1_rd_full_fifo),
.empty(ram2_p1_rd_empty_fifo)
);
assign ram2_p1_rd_en = ~ram2_p1_rd_full;
wire ram2_p2_rd_en_fifo;
wire [31:0] ram2_p2_rd_data_fifo;
wire ram2_p2_rd_empty_fifo;
wire ram2_p2_rd_full_fifo;
srl_fifo_reg #(
.WIDTH(32)
)
ram2_p2_rd_fifo (
.clk(ram2_p2_rd_clk),
.rst(rst_250mhz_int),
.write_en(~ram2_p2_rd_empty),
.write_data(ram2_p2_rd_data),
.read_en(ram2_p2_rd_en_fifo),
.read_data(ram2_p2_rd_data_fifo),
.full(ram2_p2_rd_full_fifo),
.empty(ram2_p2_rd_empty_fifo)
);
assign ram2_p2_rd_en = ~ram2_p2_rd_full;
wire ram2_p3_rd_en_fifo;
wire [31:0] ram2_p3_rd_data_fifo;
wire ram2_p3_rd_empty_fifo;
wire ram2_p3_rd_full_fifo;
srl_fifo_reg #(
.WIDTH(32)
)
ram2_p3_rd_fifo (
.clk(ram2_p3_rd_clk),
.rst(rst_250mhz_int),
.write_en(~ram2_p3_rd_empty),
.write_data(ram2_p3_rd_data),
.read_en(ram2_p3_rd_en_fifo),
.read_data(ram2_p3_rd_data_fifo),
.full(ram2_p3_rd_full_fifo),
.empty(ram2_p3_rd_empty_fifo)
);
assign ram2_p3_rd_en = ~ram2_p3_rd_full;
wire ram2_p4_rd_en_fifo;
wire [31:0] ram2_p4_rd_data_fifo;
wire ram2_p4_rd_empty_fifo;
wire ram2_p4_rd_full_fifo;
srl_fifo_reg #(
.WIDTH(32)
)
ram2_p4_rd_fifo (
.clk(ram2_p4_rd_clk),
.rst(rst_250mhz_int),
.write_en(~ram2_p4_rd_empty),
.write_data(ram2_p4_rd_data),
.read_en(ram2_p4_rd_en_fifo),
.read_data(ram2_p4_rd_data_fifo),
.full(ram2_p4_rd_full_fifo),
.empty(ram2_p4_rd_empty_fifo)
);
assign ram2_p4_rd_en = ~ram2_p4_rd_full;
wire ram2_p5_rd_en_fifo;
wire [31:0] ram2_p5_rd_data_fifo;
wire ram2_p5_rd_empty_fifo;
wire ram2_p5_rd_full_fifo;
srl_fifo_reg #(
.WIDTH(32)
)
ram2_p5_rd_fifo (
.clk(ram2_p5_rd_clk),
.rst(rst_250mhz_int),
.write_en(~ram2_p5_rd_empty),
.write_data(ram2_p5_rd_data),
.read_en(ram2_p5_rd_en_fifo),
.read_data(ram2_p5_rd_data_fifo),
.full(ram2_p5_rd_full_fifo),
.empty(ram2_p5_rd_empty_fifo)
);
assign ram2_p5_rd_en = ~ram2_p5_rd_full;
/////////////////////////////////////////////////
// //
// SoC Interface //
// //
/////////////////////////////////////////////////
wire [7:0] cntrl_rx_tdata;
wire cntrl_rx_tvalid;
wire cntrl_rx_tready;
wire cntrl_rx_tlast;
wire [7:0] cntrl_tx_tdata;
wire cntrl_tx_tvalid;
wire cntrl_tx_tready;
wire cntrl_tx_tlast;
wire [35:0] wbm_adr_o;
wire [7:0] wbm_dat_i;
wire [7:0] wbm_dat_o;
wire wbm_we_o;
wire wbm_stb_o;
wire wbm_ack_i;
wire wbm_err_i;
wire wbm_cyc_o;
wire [31:0] ram1_wb_adr_i;
wire [7:0] ram1_wb_dat_i;
wire [7:0] ram1_wb_dat_o;
wire ram1_wb_we_i;
wire ram1_wb_stb_i;
wire ram1_wb_ack_o;
wire ram1_wb_err_o;
wire ram1_wb_cyc_i;
wire [31:0] ram2_wb_adr_i;
wire [7:0] ram2_wb_dat_i;
wire [7:0] ram2_wb_dat_o;
wire ram2_wb_we_i;
wire ram2_wb_stb_i;
wire ram2_wb_ack_o;
wire ram2_wb_err_o;
wire ram2_wb_cyc_i;
wire [31:0] ctrl_wb_adr_i;
wire [7:0] ctrl_wb_dat_i;
wire [7:0] ctrl_wb_dat_o;
wire ctrl_wb_we_i;
wire ctrl_wb_stb_i;
wire ctrl_wb_ack_o;
wire ctrl_wb_err_o;
wire ctrl_wb_cyc_i;
wire [31:0] ctrl_int_wb_adr_i;
wire [7:0] ctrl_int_wb_dat_i;
wire [7:0] ctrl_int_wb_dat_o;
wire ctrl_int_wb_we_i;
wire ctrl_int_wb_stb_i;
wire ctrl_int_wb_ack_o;
wire ctrl_int_wb_err_o;
wire ctrl_int_wb_cyc_i;
axis_spi_slave #(
.DATA_WIDTH(8)
)
spi_slave_inst (
.clk(clk_250mhz_int),
.rst(rst_250mhz_int),
// axi input
.input_axis_tdata(cntrl_tx_tdata),
.input_axis_tvalid(cntrl_tx_tvalid),
.input_axis_tready(cntrl_tx_tready),
.input_axis_tlast(cntrl_tx_tlast),
// axi output
.output_axis_tdata(cntrl_rx_tdata),
.output_axis_tvalid(cntrl_rx_tvalid),
.output_axis_tready(cntrl_rx_tready),
.output_axis_tlast(cntrl_rx_tlast),
// spi interface
.cs(cntrl_cs),
.sck(cntrl_sck),
.mosi(cntrl_mosi),
.miso(cntrl_miso),
// status
.busy()
);
soc_interface_wb_8
soc_interface_wb_inst (
.clk(clk_250mhz_int),
.rst(rst_250mhz_int),
// axi input
.input_axis_tdata(cntrl_rx_tdata),
.input_axis_tvalid(cntrl_rx_tvalid),
.input_axis_tready(cntrl_rx_tready),
.input_axis_tlast(cntrl_rx_tlast),
// axi output
.output_axis_tdata(cntrl_tx_tdata),
.output_axis_tvalid(cntrl_tx_tvalid),
.output_axis_tready(cntrl_tx_tready),
.output_axis_tlast(cntrl_tx_tlast),
// wb interface
.wb_adr_o(wbm_adr_o),
.wb_dat_i(wbm_dat_i),
.wb_dat_o(wbm_dat_o),
.wb_we_o(wbm_we_o),
.wb_stb_o(wbm_stb_o),
.wb_ack_i(wbm_ack_i),
.wb_err_i(wbm_err_i),
.wb_cyc_o(wbm_cyc_o),
// status
.busy()
);
wb_mux_3 #(
.DATA_WIDTH(8),
.ADDR_WIDTH(36)
)
wb_mux_inst (
.clk(clk_250mhz_int),
.rst(rst_250mhz_int),
// from SoC interface
.wbm_adr_i(wbm_adr_o),
.wbm_dat_i(wbm_dat_o),
.wbm_dat_o(wbm_dat_i),
.wbm_we_i(wbm_we_o),
.wbm_sel_i(1),
.wbm_stb_i(wbm_stb_o),
.wbm_ack_o(wbm_ack_i),
.wbm_err_o(wbm_err_i),
.wbm_rty_o(),
.wbm_cyc_i(wbm_cyc_o),
// MCB 1
.wbs0_adr_o(ram1_wb_adr_i),
.wbs0_dat_i(ram1_wb_dat_o),
.wbs0_dat_o(ram1_wb_dat_i),
.wbs0_we_o(ram1_wb_we_i),
.wbs0_sel_o(),
.wbs0_stb_o(ram1_wb_stb_i),
.wbs0_ack_i(ram1_wb_ack_o),
.wbs0_err_i(ram1_wb_err_o),
.wbs0_rty_i(0),
.wbs0_cyc_o(ram1_wb_cyc_i),
.wbs0_addr(36'h000000000),
.wbs0_addr_msk(36'hF00000000),
// MCB 2
.wbs1_adr_o(ram2_wb_adr_i),
.wbs1_dat_i(ram2_wb_dat_o),
.wbs1_dat_o(ram2_wb_dat_i),
.wbs1_we_o(ram2_wb_we_i),
.wbs1_sel_o(),
.wbs1_stb_o(ram2_wb_stb_i),
.wbs1_ack_i(ram2_wb_ack_o),
.wbs1_err_i(ram2_wb_err_o),
.wbs1_rty_i(0),
.wbs1_cyc_o(ram2_wb_cyc_i),
.wbs1_addr(36'h100000000),
.wbs1_addr_msk(36'hF00000000),
// Control
.wbs2_adr_o(ctrl_wb_adr_i),
.wbs2_dat_i(ctrl_wb_dat_o),
.wbs2_dat_o(ctrl_wb_dat_i),
.wbs2_we_o(ctrl_wb_we_i),
.wbs2_sel_o(),
.wbs2_stb_o(ctrl_wb_stb_i),
.wbs2_ack_i(ctrl_wb_ack_o),
.wbs2_err_i(ctrl_wb_err_o),
.wbs2_rty_i(0),
.wbs2_cyc_o(ctrl_wb_cyc_i),
.wbs2_addr(36'hF00000000),
.wbs2_addr_msk(36'hF00000000)
);
assign ram1_wb_err_o = 0;
wb_mcb_8
wb_mcb_ram1_inst (
.clk(clk_250mhz_int),
.rst(rst_250mhz_int),
// wb interface
.wb_adr_i(ram1_wb_adr_i),
.wb_dat_i(ram1_wb_dat_i),
.wb_dat_o(ram1_wb_dat_o),
.wb_we_i(ram1_wb_we_i),
.wb_stb_i(ram1_wb_stb_i),
.wb_ack_o(ram1_wb_ack_o),
.wb_cyc_i(ram1_wb_cyc_i),
// mcb interface
.mcb_cmd_clk(ram1_p0_cmd_clk),
.mcb_cmd_en(ram1_p0_cmd_en),
.mcb_cmd_instr(ram1_p0_cmd_instr),
.mcb_cmd_bl(ram1_p0_cmd_bl),
.mcb_cmd_byte_addr(ram1_p0_cmd_byte_addr),
.mcb_cmd_empty(ram1_p0_cmd_empty),
.mcb_cmd_full(ram1_p0_cmd_full),
.mcb_wr_clk(ram1_p0_wr_clk),
.mcb_wr_en(ram1_p0_wr_en),
.mcb_wr_mask(ram1_p0_wr_mask),
.mcb_wr_data(ram1_p0_wr_data),
.mcb_wr_empty(ram1_p0_wr_empty),
.mcb_wr_full(ram1_p0_wr_full),
.mcb_wr_underrun(ram1_p0_wr_underrun),
.mcb_wr_count(ram1_p0_wr_count),
.mcb_wr_error(ram1_p0_wr_error),
.mcb_rd_clk(ram1_p0_rd_clk),
.mcb_rd_en(ram1_p0_rd_en_fifo),
.mcb_rd_data(ram1_p0_rd_data_fifo),
.mcb_rd_empty(ram1_p0_rd_empty_fifo),
.mcb_rd_full(ram1_p0_rd_full_fifo),
.mcb_rd_overflow(ram1_p0_rd_overflow),
.mcb_rd_count(ram1_p0_rd_count),
.mcb_rd_error(ram1_p0_rd_error)
);
assign ram2_wb_err_o = 0;
wb_mcb_8
wb_mcb_ram2_inst (
.clk(clk_250mhz_int),
.rst(rst_250mhz_int),
// wb interface
.wb_adr_i(ram2_wb_adr_i),
.wb_dat_i(ram2_wb_dat_i),
.wb_dat_o(ram2_wb_dat_o),
.wb_we_i(ram2_wb_we_i),
.wb_stb_i(ram2_wb_stb_i),
.wb_ack_o(ram2_wb_ack_o),
.wb_cyc_i(ram2_wb_cyc_i),
// mcb interface
.mcb_cmd_clk(ram2_p0_cmd_clk),
.mcb_cmd_en(ram2_p0_cmd_en),
.mcb_cmd_instr(ram2_p0_cmd_instr),
.mcb_cmd_bl(ram2_p0_cmd_bl),
.mcb_cmd_byte_addr(ram2_p0_cmd_byte_addr),
.mcb_cmd_empty(ram2_p0_cmd_empty),
.mcb_cmd_full(ram2_p0_cmd_full),
.mcb_wr_clk(ram2_p0_wr_clk),
.mcb_wr_en(ram2_p0_wr_en),
.mcb_wr_mask(ram2_p0_wr_mask),
.mcb_wr_data(ram2_p0_wr_data),
.mcb_wr_empty(ram2_p0_wr_empty),
.mcb_wr_full(ram2_p0_wr_full),
.mcb_wr_underrun(ram2_p0_wr_underrun),
.mcb_wr_count(ram2_p0_wr_count),
.mcb_wr_error(ram2_p0_wr_error),
.mcb_rd_clk(ram2_p0_rd_clk),
.mcb_rd_en(ram2_p0_rd_en_fifo),
.mcb_rd_data(ram2_p0_rd_data_fifo),
.mcb_rd_empty(ram2_p0_rd_empty_fifo),
.mcb_rd_full(ram2_p0_rd_full_fifo),
.mcb_rd_overflow(ram2_p0_rd_overflow),
.mcb_rd_count(ram2_p0_rd_count),
.mcb_rd_error(ram2_p0_rd_error)
);
wb_async_reg #(
.DATA_WIDTH(8),
.ADDR_WIDTH(32)
)
wb_async_reg_inst (
.wbm_clk(clk_250mhz_int),
.wbm_rst(rst_250mhz_int),
.wbm_adr_i(ctrl_wb_adr_i),
.wbm_dat_i(ctrl_wb_dat_i),
.wbm_dat_o(ctrl_wb_dat_o),
.wbm_we_i(ctrl_wb_we_i),
.wbm_sel_i(1),
.wbm_stb_i(ctrl_wb_stb_i),
.wbm_ack_o(ctrl_wb_ack_o),
.wbm_err_o(ctrl_wb_err_o),
.wbm_rty_o(),
.wbm_cyc_i(ctrl_wb_cyc_i),
.wbs_clk(clk_250mhz),
.wbs_rst(rst_250mhz),
.wbs_adr_o(ctrl_int_wb_adr_i),
.wbs_dat_i(ctrl_int_wb_dat_o),
.wbs_dat_o(ctrl_int_wb_dat_i),
.wbs_we_o(ctrl_int_wb_we_i),
.wbs_sel_o(),
.wbs_stb_o(ctrl_int_wb_stb_i),
.wbs_ack_i(ctrl_int_wb_ack_o),
.wbs_err_i(ctrl_int_wb_err_o),
.wbs_rty_i(0),
.wbs_cyc_o(ctrl_int_wb_cyc_i)
);
assign ctrl_int_wb_err_o = 0;
wb_ram #(
.DATA_WIDTH(8),
.ADDR_WIDTH(10)
)
wb_ram_inst(
.clk(clk_250mhz),
.adr_i(ctrl_int_wb_adr_i),
.dat_i(ctrl_int_wb_dat_i),
.dat_o(ctrl_int_wb_dat_o),
.we_i(ctrl_int_wb_we_i),
.sel_i(1),
.stb_i(ctrl_int_wb_stb_i),
.ack_o(ctrl_int_wb_ack_o),
.cyc_i(ctrl_int_wb_cyc_i)
);
// currenly unused signals
assign ram1_p1_cmd_clk = 0;
assign ram1_p1_cmd_en = 0;
assign ram1_p1_cmd_instr = 0;
assign ram1_p1_cmd_bl = 0;
assign ram1_p1_cmd_byte_addr = 0;
assign ram1_p1_wr_clk = 0;
assign ram1_p1_wr_en = 0;
assign ram1_p1_wr_mask = 0;
assign ram1_p1_wr_data = 0;
assign ram1_p1_rd_clk = 0;
assign ram1_p1_rd_en_fifo = 0;
assign ram1_p2_cmd_clk = 0;
assign ram1_p2_cmd_en = 0;
assign ram1_p2_cmd_instr = 0;
assign ram1_p2_cmd_bl = 0;
assign ram1_p2_cmd_byte_addr = 0;
assign ram1_p2_rd_clk = 0;
assign ram1_p2_rd_en_fifo = 0;
assign ram1_p3_cmd_clk = 0;
assign ram1_p3_cmd_en = 0;
assign ram1_p3_cmd_instr = 0;
assign ram1_p3_cmd_bl = 0;
assign ram1_p3_cmd_byte_addr = 0;
assign ram1_p3_rd_clk = 0;
assign ram1_p3_rd_en_fifo = 0;
assign ram1_p4_cmd_clk = 0;
assign ram1_p4_cmd_en = 0;
assign ram1_p4_cmd_instr = 0;
assign ram1_p4_cmd_bl = 0;
assign ram1_p4_cmd_byte_addr = 0;
assign ram1_p4_rd_clk = 0;
assign ram1_p4_rd_en_fifo = 0;
assign ram1_p5_cmd_clk = 0;
assign ram1_p5_cmd_en = 0;
assign ram1_p5_cmd_instr = 0;
assign ram1_p5_cmd_bl = 0;
assign ram1_p5_cmd_byte_addr = 0;
assign ram1_p5_rd_clk = 0;
assign ram1_p5_rd_en_fifo = 0;
assign ram2_p1_cmd_clk = 0;
assign ram2_p1_cmd_en = 0;
assign ram2_p1_cmd_instr = 0;
assign ram2_p1_cmd_bl = 0;
assign ram2_p1_cmd_byte_addr = 0;
assign ram2_p1_wr_clk = 0;
assign ram2_p1_wr_en = 0;
assign ram2_p1_wr_mask = 0;
assign ram2_p1_wr_data = 0;
assign ram2_p1_rd_clk = 0;
assign ram2_p1_rd_en_fifo = 0;
assign ram2_p2_cmd_clk = 0;
assign ram2_p2_cmd_en = 0;
assign ram2_p2_cmd_instr = 0;
assign ram2_p2_cmd_bl = 0;
assign ram2_p2_cmd_byte_addr = 0;
assign ram2_p2_rd_clk = 0;
assign ram2_p2_rd_en_fifo = 0;
assign ram2_p3_cmd_clk = 0;
assign ram2_p3_cmd_en = 0;
assign ram2_p3_cmd_instr = 0;
assign ram2_p3_cmd_bl = 0;
assign ram2_p3_cmd_byte_addr = 0;
assign ram2_p3_rd_clk = 0;
assign ram2_p3_rd_en_fifo = 0;
assign ram2_p4_cmd_clk = 0;
assign ram2_p4_cmd_en = 0;
assign ram2_p4_cmd_instr = 0;
assign ram2_p4_cmd_bl = 0;
assign ram2_p4_cmd_byte_addr = 0;
assign ram2_p4_rd_clk = 0;
assign ram2_p4_rd_en_fifo = 0;
assign ram2_p5_cmd_clk = 0;
assign ram2_p5_cmd_en = 0;
assign ram2_p5_cmd_instr = 0;
assign ram2_p5_cmd_bl = 0;
assign ram2_p5_cmd_byte_addr = 0;
assign ram2_p5_rd_clk = 0;
assign ram2_p5_rd_en_fifo = 0;
endmodule
|
module sky130_fd_sc_hd__lpflow_inputiso1p (
X ,
A ,
SLEEP,
VPWR ,
VGND ,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input SLEEP;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
// Local signals
wire or0_out_X;
// Name Output Other arguments
or or0 (or0_out_X, A, SLEEP );
sky130_fd_sc_hd__udp_pwrgood$l_pp$PG pwrgood0 (X , or0_out_X, VPWR, VGND);
endmodule
|
module vga(/*AUTOARG*/
// Outputs
hsync, vsync, x, y, ve, newline, newfield,
// Inputs
clk_p, rst
);
input wire clk_p;
input wire rst;
output wire hsync, vsync;
output wire [9:0] x, y; //1023
output wire ve;
output wire newline, newfield;
assign newline = x_i == 0;
assign newfield = y_i == 0;
reg [10:0] x_i, y_i; //2047
//wire clk_l; //clk_p pixel clock, clk_l line clock
//60Hz 0 < x < 1023, 0 < y < 767 75Mhz clk_d
//Horizontal (line) Front Porch 24clk_p Sync 136clk_p Back Porch 160clk_p = 1344
//Vertical (field) 3clk_l 6clk_l 29clk_l = 806
//60Hz 0 < x < 799, 0 < y < 599 40Mhz clk_d
// parameter h_pixel = 'd799;
// parameter v_pixel = 'd599;
// parameter h_front_porch = 'd40;
// parameter h_sync_pulse = 'd128;
// parameter h_back_porch = 'd88;
// parameter v_front_porch = 'd1;
// parameter v_sync_pulse = 'd4;
// parameter v_back_porch = 'd23;
// parameter line = h_pixel + h_front_porch + h_sync_pulse + h_back_porch;
// parameter field = v_pixel + v_front_porch + v_sync_pulse + v_back_porch;
//60Hz 0 < x < 639, 0 < y < 479 25Mhz clk_d
parameter h_pixel = 'd639;
parameter v_pixel = 'd479;
parameter v_front_porch = 'd10;
parameter v_sync_pulse = 'd2;
parameter v_back_porch = 'd29; //33
parameter h_front_porch = 'd16;
parameter h_sync_pulse = 'd96;
parameter h_back_porch = 'd48;
parameter line = h_pixel + h_front_porch + h_sync_pulse + h_back_porch;
parameter field = v_pixel + v_front_porch + v_sync_pulse + v_back_porch;
always @(posedge clk_p) begin
if(~rst) begin
x_i <= 0;
end
else begin
if(x_i == line) begin
x_i <= 0;
end
else begin
x_i <= x_i + 1;
end
end
end
always @(posedge clk_p) begin
if(~rst) begin
y_i <= 0;
end
else if (x_i == line) begin
if(y_i == field) begin
y_i <= 0;
end
else begin
y_i <= y_i + 1;
end
end
end
assign hsync = (x_i >= h_sync_pulse) ? 1: 0;
assign vsync = (y_i >= v_sync_pulse) ? 1: 0;
assign ve = 0
|| (x_i >= h_sync_pulse + h_back_porch && x_i <= line - h_front_porch) && (y_i >= v_sync_pulse + v_back_porch && y_i <= field - v_front_porch)
// && ( (|y[2:0]))
// || (x_i >= h_sync_pulse + h_back_porch && x_i <=1+ line - h_front_porch) && (y_i >= v_sync_pulse + v_back_porch && y_i <= field - v_front_porch)
// && (!(|y[2:0]))
;
//assign x = (ve) ? x_i - h_back_porch - h_sync_pulse : 0;
//assign y = (ve) ? y_i - v_back_porch - v_sync_pulse : 0;
assign x = x_i - h_back_porch - h_sync_pulse;
assign y = y_i - v_back_porch - v_sync_pulse;
endmodule
|
module dac(DACout, DACin, Clk, Reset);
output DACout; // This is the average output that feeds low pass filter
reg DACout; // for optimum performance, ensure that this ff is in IOB
input [`MSBI:0] DACin; // DAC input (excess 2**MSBI)
input Clk;
input Reset;
reg [`MSBI+2:0] DeltaAdder; // Output of Delta adder
reg [`MSBI+2:0] SigmaAdder; // Output of Sigma adder
reg [`MSBI+2:0] SigmaLatch; // Latches output of Sigma adder
reg [`MSBI+2:0] DeltaB; // B input of Delta adder
always @(SigmaLatch) DeltaB = {SigmaLatch[`MSBI+2], SigmaLatch[`MSBI+2]} << (`MSBI+1);
always @(DACin or DeltaB) DeltaAdder = DACin + DeltaB;
always @(DeltaAdder or SigmaLatch) SigmaAdder = DeltaAdder + SigmaLatch;
always @(posedge Clk or posedge Reset)
begin
if(Reset)
begin
SigmaLatch <= 1'b1 << (`MSBI+1);
DACout <= 1'b0;
end
else
begin
SigmaLatch <= SigmaAdder;
DACout <= SigmaLatch[`MSBI+2];
end
end
endmodule
|
module fpga (
// CPU reset button
input wire CPU_RESET_n,
// buttons
input wire [3:0] BUTTON,
input wire [3:0] SW,
// LEDs
output wire [6:0] HEX0_D,
output wire HEX0_DP,
output wire [6:0] HEX1_D,
output wire HEX1_DP,
output wire [3:0] LED,
output wire [3:0] LED_BRACKET,
output wire LED_RJ45_L,
output wire LED_RJ45_R,
// Temperature control
//inout wire TEMP_CLK,
//inout wire TEMP_DATA,
//input wire TEMP_INT_n,
//input wire TEMP_OVERT_n,
output wire FAN_CTRL,
// 50 MHz clock inputs
input wire OSC_50_B3B,
input wire OSC_50_B3D,
input wire OSC_50_B4A,
input wire OSC_50_B4D,
input wire OSC_50_B7A,
input wire OSC_50_B7D,
input wire OSC_50_B8A,
input wire OSC_50_B8D,
// PCIe interface
//input wire PCIE_PERST_n,
//input wire PCIE_REFCLK_p,
//input wire [7:0] PCIE_RX_p,
//output wire [7:0] PCIE_TX_p,
//input wire PCIE_WAKE_n,
//inout wire PCIE_SMBCLK,
//inout wire PCIE_SMBDAT,
// Si570
inout wire CLOCK_SCL,
inout wire CLOCK_SDA,
// 10G Ethernet
input wire SFPA_LOS,
input wire SFPA_TXFAULT,
input wire SFPA_MOD0_PRESNT_n,
inout wire SFPA_MOD1_SCL,
inout wire SFPA_MOD2_SDA,
output wire SFPA_TXDISABLE,
output wire [1:0] SPFA_RATESEL,
input wire SFPA_RX_p,
output wire SFPA_TX_p,
input wire SFPB_LOS,
input wire SFPB_TXFAULT,
input wire SFPB_MOD0_PRESNT_n,
inout wire SFPB_MOD1_SCL,
inout wire SFPB_MOD2_SDA,
output wire SFPB_TXDISABLE,
output wire [1:0] SPFB_RATESEL,
input wire SFPB_RX_p,
output wire SFPB_TX_p,
input wire SFPC_LOS,
input wire SFPC_TXFAULT,
input wire SFPC_MOD0_PRESNT_n,
inout wire SFPC_MOD1_SCL,
inout wire SFPC_MOD2_SDA,
output wire SFPC_TXDISABLE,
output wire [1:0] SPFC_RATESEL,
input wire SFPC_RX_p,
output wire SFPC_TX_p,
input wire SFPD_LOS,
input wire SFPD_TXFAULT,
input wire SFPD_MOD0_PRESNT_n,
inout wire SFPD_MOD1_SCL,
inout wire SFPD_MOD2_SDA,
output wire SFPD_TXDISABLE,
output wire [1:0] SPFD_RATESEL,
input wire SFPD_RX_p,
output wire SFPD_TX_p,
input wire SFP_REFCLK_P
);
// Clock and reset
wire clk_50mhz = OSC_50_B3B;
wire rst_50mhz;
sync_reset #(
.N(4)
)
sync_reset_50mhz_inst (
.clk(clk_50mhz),
.rst(~CPU_RESET_n),
.out(rst_50mhz)
);
wire clk_156mhz;
wire rst_156mhz;
wire phy_pll_locked;
sync_reset #(
.N(4)
)
sync_reset_156mhz_inst (
.clk(clk_156mhz),
.rst(rst_50mhz | ~phy_pll_locked),
.out(rst_156mhz)
);
// GPIO
wire [3:0] btn_int;
wire [3:0] sw_int;
wire [3:0] led_int;
wire [3:0] led_bkt_int;
wire [6:0] led_hex0_d_int;
wire led_hex0_dp_int;
wire [6:0] led_hex1_d_int;
wire led_hex1_dp_int;
debounce_switch #(
.WIDTH(8),
.N(4),
.RATE(156250)
)
debounce_switch_inst (
.clk(clk_156mhz),
.rst(rst_156mhz),
.in({BUTTON,
SW}),
.out({btn_int,
sw_int})
);
assign LED = ~led_int;
assign LED_BRACKET = ~led_bkt_int;
assign HEX0_D = ~led_hex0_d_int;
assign HEX0_DP = ~led_hex0_dp_int;
assign HEX1_D = ~led_hex1_d_int;
assign HEX1_DP = ~led_hex1_dp_int;
assign FAN_CTRL = 1;
// Si570 oscillator I2C init
wire si570_scl_i;
wire si570_scl_o;
wire si570_scl_t;
wire si570_sda_i;
wire si570_sda_o;
wire si570_sda_t;
assign si570_sda_i = CLOCK_SDA;
assign CLOCK_SDA = si570_sda_t ? 1'bz : si570_sda_o;
assign si570_scl_i = CLOCK_SCL;
assign CLOCK_SCL = si570_scl_t ? 1'bz : si570_scl_o;
wire [6:0] si570_i2c_cmd_address;
wire si570_i2c_cmd_start;
wire si570_i2c_cmd_read;
wire si570_i2c_cmd_write;
wire si570_i2c_cmd_write_multiple;
wire si570_i2c_cmd_stop;
wire si570_i2c_cmd_valid;
wire si570_i2c_cmd_ready;
wire [7:0] si570_i2c_data;
wire si570_i2c_data_valid;
wire si570_i2c_data_ready;
wire si570_i2c_data_last;
si570_i2c_init
si570_i2c_init_inst (
.clk(clk_50mhz),
.rst(rst_50mhz),
.cmd_address(si570_i2c_cmd_address),
.cmd_start(si570_i2c_cmd_start),
.cmd_read(si570_i2c_cmd_read),
.cmd_write(si570_i2c_cmd_write),
.cmd_write_multiple(si570_i2c_cmd_write_multiple),
.cmd_stop(si570_i2c_cmd_stop),
.cmd_valid(si570_i2c_cmd_valid),
.cmd_ready(si570_i2c_cmd_ready),
.data_out(si570_i2c_data),
.data_out_valid(si570_i2c_data_valid),
.data_out_ready(si570_i2c_data_ready),
.data_out_last(si570_i2c_data_last),
.busy(),
.start(1)
);
i2c_master
si570_i2c_master_inst (
.clk(clk_50mhz),
.rst(rst_50mhz),
.cmd_address(si570_i2c_cmd_address),
.cmd_start(si570_i2c_cmd_start),
.cmd_read(si570_i2c_cmd_read),
.cmd_write(si570_i2c_cmd_write),
.cmd_write_multiple(si570_i2c_cmd_write_multiple),
.cmd_stop(si570_i2c_cmd_stop),
.cmd_valid(si570_i2c_cmd_valid),
.cmd_ready(si570_i2c_cmd_ready),
.data_in(si570_i2c_data),
.data_in_valid(si570_i2c_data_valid),
.data_in_ready(si570_i2c_data_ready),
.data_in_last(si570_i2c_data_last),
.data_out(),
.data_out_valid(),
.data_out_ready(1),
.data_out_last(),
.scl_i(si570_scl_i),
.scl_o(si570_scl_o),
.scl_t(si570_scl_t),
.sda_i(si570_sda_i),
.sda_o(si570_sda_o),
.sda_t(si570_sda_t),
.busy(),
.bus_control(),
.bus_active(),
.missed_ack(),
.prescale(312),
.stop_on_idle(1)
);
// 10G Ethernet PHY
wire [71:0] sfp_a_tx_dc;
wire [71:0] sfp_a_rx_dc;
wire [71:0] sfp_b_tx_dc;
wire [71:0] sfp_b_rx_dc;
wire [71:0] sfp_c_tx_dc;
wire [71:0] sfp_c_rx_dc;
wire [71:0] sfp_d_tx_dc;
wire [71:0] sfp_d_rx_dc;
wire [367:0] phy_reconfig_from_xcvr;
wire [559:0] phy_reconfig_to_xcvr;
assign SFPA_MOD1_SCL = 1'bz;
assign SFPA_MOD2_SDA = 1'bz;
assign SFPA_TXDISABLE = 1'b0;
assign SPFA_RATESEL = 2'b00;
assign SFPB_MOD1_SCL = 1'bz;
assign SFPB_MOD2_SDA = 1'bz;
assign SFPB_TXDISABLE = 1'b0;
assign SPFB_RATESEL = 2'b00;
assign SFPC_MOD1_SCL = 1'bz;
assign SFPC_MOD2_SDA = 1'bz;
assign SFPC_TXDISABLE = 1'b0;
assign SPFC_RATESEL = 2'b00;
assign SFPD_MOD1_SCL = 1'bz;
assign SFPD_MOD2_SDA = 1'bz;
assign SFPD_TXDISABLE = 1'b0;
assign SPFD_RATESEL = 2'b00;
phy
phy_inst (
.pll_ref_clk(SFP_REFCLK_P),
.pll_locked(phy_pll_locked),
.tx_serial_data_0(SFPA_TX_p),
.rx_serial_data_0(SFPA_RX_p),
.tx_serial_data_1(SFPB_TX_p),
.rx_serial_data_1(SFPB_RX_p),
.tx_serial_data_2(SFPC_TX_p),
.rx_serial_data_2(SFPC_RX_p),
.tx_serial_data_3(SFPD_TX_p),
.rx_serial_data_3(SFPD_RX_p),
.xgmii_tx_dc_0(sfp_a_tx_dc),
.xgmii_rx_dc_0(sfp_a_rx_dc),
.xgmii_tx_dc_1(sfp_b_tx_dc),
.xgmii_rx_dc_1(sfp_b_rx_dc),
.xgmii_tx_dc_2(sfp_c_tx_dc),
.xgmii_rx_dc_2(sfp_c_rx_dc),
.xgmii_tx_dc_3(sfp_d_tx_dc),
.xgmii_rx_dc_3(sfp_d_rx_dc),
.xgmii_rx_clk(clk_156mhz),
.xgmii_tx_clk(clk_156mhz),
.tx_ready(~rst_156mhz),
.rx_ready(),
.rx_data_ready(),
.phy_mgmt_clk(clk_50mhz),
.phy_mgmt_clk_reset(rst_50mhz),
.phy_mgmt_address(9'd0),
.phy_mgmt_read(1'b0),
.phy_mgmt_readdata(),
.phy_mgmt_waitrequest(),
.phy_mgmt_write(1'b0),
.phy_mgmt_writedata(32'd0),
.reconfig_from_xcvr(phy_reconfig_from_xcvr),
.reconfig_to_xcvr(phy_reconfig_to_xcvr)
);
phy_reconfig
phy_reconfig_inst (
.reconfig_busy(),
.mgmt_clk_clk(clk_50mhz),
.mgmt_rst_reset(rst_50mhz),
.reconfig_mgmt_address(7'd0),
.reconfig_mgmt_read(1'b0),
.reconfig_mgmt_readdata(),
.reconfig_mgmt_waitrequest(),
.reconfig_mgmt_write(1'b0),
.reconfig_mgmt_writedata(32'd0),
.reconfig_to_xcvr(phy_reconfig_to_xcvr),
.reconfig_from_xcvr(phy_reconfig_from_xcvr)
);
// Convert XGMII interfaces
wire [63:0] sfp_a_txd_int;
wire [7:0] sfp_a_txc_int;
wire [63:0] sfp_a_rxd_int;
wire [7:0] sfp_a_rxc_int;
wire [63:0] sfp_b_txd_int;
wire [7:0] sfp_b_txc_int;
wire [63:0] sfp_b_rxd_int;
wire [7:0] sfp_b_rxc_int;
wire [63:0] sfp_c_txd_int;
wire [7:0] sfp_c_txc_int;
wire [63:0] sfp_c_rxd_int;
wire [7:0] sfp_c_rxc_int;
wire [63:0] sfp_d_txd_int;
wire [7:0] sfp_d_txc_int;
wire [63:0] sfp_d_rxd_int;
wire [7:0] sfp_d_rxc_int;
xgmii_interleave
xgmii_interleave_inst_a (
.input_xgmii_d(sfp_a_txd_int),
.input_xgmii_c(sfp_a_txc_int),
.output_xgmii_dc(sfp_a_tx_dc)
);
xgmii_deinterleave
xgmii_deinterleave_inst_a (
.input_xgmii_dc(sfp_a_rx_dc),
.output_xgmii_d(sfp_a_rxd_int),
.output_xgmii_c(sfp_a_rxc_int)
);
xgmii_interleave
xgmii_interleave_inst_b (
.input_xgmii_d(sfp_b_txd_int),
.input_xgmii_c(sfp_b_txc_int),
.output_xgmii_dc(sfp_b_tx_dc)
);
xgmii_deinterleave
xgmii_deinterleave_inst_b (
.input_xgmii_dc(sfp_b_rx_dc),
.output_xgmii_d(sfp_b_rxd_int),
.output_xgmii_c(sfp_b_rxc_int)
);
xgmii_interleave
xgmii_interleave_inst_c (
.input_xgmii_d(sfp_c_txd_int),
.input_xgmii_c(sfp_c_txc_int),
.output_xgmii_dc(sfp_c_tx_dc)
);
xgmii_deinterleave
xgmii_deinterleave_inst_c (
.input_xgmii_dc(sfp_c_rx_dc),
.output_xgmii_d(sfp_c_rxd_int),
.output_xgmii_c(sfp_c_rxc_int)
);
xgmii_interleave
xgmii_interleave_inst_d (
.input_xgmii_d(sfp_d_txd_int),
.input_xgmii_c(sfp_d_txc_int),
.output_xgmii_dc(sfp_d_tx_dc)
);
xgmii_deinterleave
xgmii_deinterleave_inst_d (
.input_xgmii_dc(sfp_d_rx_dc),
.output_xgmii_d(sfp_d_rxd_int),
.output_xgmii_c(sfp_d_rxc_int)
);
// Core logic
fpga_core
core_inst (
/*
* Clock: 156.25MHz
* Synchronous reset
*/
.clk(clk_156mhz),
.rst(rst_156mhz),
/*
* GPIO
*/
.btn(btn_int),
.sw(sw_int),
.led(led_int),
.led_bkt(led_bkt_int),
.led_hex0_d(led_hex0_d_int),
.led_hex0_dp(led_hex0_dp_int),
.led_hex1_d(led_hex1_d_int),
.led_hex1_dp(led_hex1_dp_int),
/*
* 10G Ethernet
*/
.sfp_a_txd(sfp_a_txd_int),
.sfp_a_txc(sfp_a_txc_int),
.sfp_a_rxd(sfp_a_rxd_int),
.sfp_a_rxc(sfp_a_rxc_int),
.sfp_b_txd(sfp_b_txd_int),
.sfp_b_txc(sfp_b_txc_int),
.sfp_b_rxd(sfp_b_rxd_int),
.sfp_b_rxc(sfp_b_rxc_int),
.sfp_c_txd(sfp_c_txd_int),
.sfp_c_txc(sfp_c_txc_int),
.sfp_c_rxd(sfp_c_rxd_int),
.sfp_c_rxc(sfp_c_rxc_int),
.sfp_d_txd(sfp_d_txd_int),
.sfp_d_txc(sfp_d_txc_int),
.sfp_d_rxd(sfp_d_rxd_int),
.sfp_d_rxc(sfp_d_rxc_int)
);
endmodule
|
module sky130_fd_sc_hs__dfxtp (
VPWR,
VGND,
Q ,
CLK ,
D
);
// Module ports
input VPWR;
input VGND;
output Q ;
input CLK ;
input D ;
// Local signals
wire buf_Q;
// Delay Name Output Other arguments
sky130_fd_sc_hs__u_df_p_pg `UNIT_DELAY u_df_p_pg0 (buf_Q , D, CLK, VPWR, VGND);
buf buf0 (Q , buf_Q );
endmodule
|
module project (GPIO_0,SW,CLOCK_50,LEDR,LEDG, PS2_DAT, PS2_CLK);
output [25:0]GPIO_0;
output [0:17]LEDR;
output [0:6]LEDG;
input PS2_DAT;
input PS2_CLK;
input[16:0] SW;
input CLOCK_50;
wire hertz_10;
wire hertz_1;
reg [0:7] LINE_1,LINE_2,LINE_3,LINE_4,LINE_5,LINE_6,LINE_7,LINE_0;
wire reset = 1'b0;
wire [7:0] scan_code;
reg [7:0] pressed;
wire read, scan_ready;
always @(posedge scan_ready)
begin
pressed <= scan_code;
end
oneshot pulser(
.pulse_out(read),
.trigger_in(scan_ready),
.clk(CLOCK_50)
);
keyboard kbd(
.keyboard_clk(PS2_CLK),
.keyboard_data(PS2_DAT),
.clock50(CLOCK_50),
.reset(reset),
.read(read),
.scan_ready(scan_ready),
.scan_code(scan_code)
);
assign LEDR[0:7] = LINE_0[0:7];
reg [0:255]ROWDATA_1;
reg [0:255]ROWDATA_2;
reg [0:255]ROWDATA_3;
reg [0:255]ROWDATA_4;
reg [0:255]ROWDATA_5;
reg [0:255]ROWDATA_6;
reg [0:255]ROWDATA_7;
reg [0:255]ROWDATA_8;
integer counter1;
integer counter2;
integer counter3;
integer counter4;
integer counter5;
integer counter6;
integer counter7;
integer counter8;
integer seconds;
integer minutes;
integer hours;
reg isBirthday;
wire [0:15]sROW1, sROW2, sROW3, sROW4, sROW5, sROW6, sROW7, sROW8;
wire [0:15]mROW1, mROW2, mROW3, mROW4, mROW5, mROW6, mROW7, mROW8;
wire [0:15]hROW1, hROW2, hROW3, hROW4, hROW5, hROW6, hROW7, hROW8;
twoDigitNumberTo8BitDisplay hoursDisplay(hours,hROW1, hROW2, hROW3, hROW4, hROW5, hROW6, hROW7, hROW8);
twoDigitNumberTo8BitDisplay minutesDisplay(minutes,mROW1, mROW2, mROW3, mROW4, mROW5, mROW6, mROW7, mROW8);
twoDigitNumberTo8BitDisplay secondsDisplay(seconds,sROW1, sROW2, sROW3, sROW4, sROW5, sROW6, sROW7, sROW8);
initial begin
isBirthday = 0;
counter1 = 0;
counter2 = 1;
counter3 = 2;
counter4 = 3;
counter5 = 4;
counter6 = 5;
counter7 = 6;
counter8 = 7;
seconds = 59;
minutes = 0;
hours = 0;
ROWDATA_1 [0:255]= 256'b1000100000000000000000000000000000000000111100000100000000000000010000001000000000001000000000000000000000000000111000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011100000000000000000000000000000000000000000000;
ROWDATA_2 [0:255]= 256'b1000100000000000000000000000000000000000100010000000000000000000010000001000000000001000000000000000000000000000010000000000000000000000000000000000000011000000000000000000000011000000000000000000000000000000100010000000000000000000000000000000000000000000;
ROWDATA_3 [0:255]= 256'b1000100001110000100010001011000000000000100010001100000010110000111000001011000001101000011100001000100000000000010000000111000000000000000000000000000011000000000000000000000011000000000000000000000000000000100010001000100001110000100010000000000000000000;
ROWDATA_4 [0:255]= 256'b0101000010001000100010001100100000000000111100000100000011001000010000001100100010011000000010001000100000000000010000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100010001010100000001000100010000000000000000000;
ROWDATA_5 [0:255]= 256'b0010000010001000100010001000000000000000100010000100000010000000010000001000100010001000011110000111100000000000010000000111000000000000000000000000000011000000000000000000000011000000000000000000000000000000111110001010100001111000011110000000000000000000;
ROWDATA_6 [0:255]= 256'b0010000010001000100110001000000000000000100010000100000010000000010010001000100010001000100010000000100000000000010000000000100000000000000000000000000011000000000000000000000011000000000000000000000000000000100010001010100010001000000010000000000000000000;
ROWDATA_7 [0:255]= 256'b0010000001110000011010001000000000000000111100001110000010000000001100001000100001111000011110000111000000000000111000001111000000000000000000000000000000000000000000000000000000000000000000000000000000000000100010000101000001111000011100000000000000000000;
ROWDATA_8 [0:255]= 256'b0;
end
toLED tL1 (GPIO_0, SW,CLOCK_50, LEDG, LINE_0, LINE_1, LINE_2, LINE_3, LINE_4, LINE_5, LINE_6, LINE_7);
clk_1_tenth_sec (CLOCK_50,hertz_10);
clk_1_sec (CLOCK_50,hertz_1);
reg [3:0]i;
always @(posedge hertz_10) begin
// Shift reader 8 bits to the right
counter1 = counter1 + 1;
counter2 = counter2 + 1;
counter3 = counter3 + 1;
counter4 = counter4 + 1;
counter5 = counter5 + 1;
counter6 = counter6 + 1;
counter7 = counter7 + 1;
counter8 = counter8 + 1;
if (counter1 == 256) begin
counter1 = 0;
end
if (counter2 == 256) begin
counter2 = 0;
end
if (counter3 == 256) begin
counter3 = 0;
end
if (counter4 == 256) begin
counter4 = 0;
end
if (counter5 == 256) begin
counter5 = 0;
end
if (counter6 == 256) begin
counter6 = 0;
end
if (counter7 == 256) begin
counter7 = 0;
end
if (counter8 == 256) begin
counter8 = 0;
end
// Assign the 8 bits to be displayed out of the 256 bit string
LINE_0 [0:7] = ({ROWDATA_1[counter1],ROWDATA_1[counter2],ROWDATA_1[counter3],ROWDATA_1[counter4],ROWDATA_1[counter5],ROWDATA_1[counter6],ROWDATA_1[counter7],ROWDATA_1[counter8]});
LINE_1 [0:7] = ({ROWDATA_2[counter1],ROWDATA_2[counter2],ROWDATA_2[counter3],ROWDATA_2[counter4],ROWDATA_2[counter5],ROWDATA_2[counter6],ROWDATA_2[counter7],ROWDATA_2[counter8]});
LINE_2 [0:7] = ({ROWDATA_3[counter1],ROWDATA_3[counter2],ROWDATA_3[counter3],ROWDATA_3[counter4],ROWDATA_3[counter5],ROWDATA_3[counter6],ROWDATA_3[counter7],ROWDATA_3[counter8]});
LINE_3 [0:7] = ({ROWDATA_4[counter1],ROWDATA_4[counter2],ROWDATA_4[counter3],ROWDATA_4[counter4],ROWDATA_4[counter5],ROWDATA_4[counter6],ROWDATA_4[counter7],ROWDATA_4[counter8]});
LINE_4 [0:7] = ({ROWDATA_5[counter1],ROWDATA_5[counter2],ROWDATA_5[counter3],ROWDATA_5[counter4],ROWDATA_5[counter5],ROWDATA_5[counter6],ROWDATA_5[counter7],ROWDATA_5[counter8]});
LINE_5 [0:7] = ({ROWDATA_6[counter1],ROWDATA_6[counter2],ROWDATA_6[counter3],ROWDATA_6[counter4],ROWDATA_6[counter5],ROWDATA_6[counter6],ROWDATA_6[counter7],ROWDATA_6[counter8]});
LINE_6 [0:7] = ({ROWDATA_7[counter1],ROWDATA_7[counter2],ROWDATA_7[counter3],ROWDATA_7[counter4],ROWDATA_7[counter5],ROWDATA_7[counter6],ROWDATA_7[counter7],ROWDATA_7[counter8]});
LINE_7 [0:7] = ({ROWDATA_8[counter1],ROWDATA_8[counter2],ROWDATA_8[counter3],ROWDATA_8[counter4],ROWDATA_8[counter5],ROWDATA_8[counter6],ROWDATA_8[counter7],ROWDATA_8[counter8]});
// If it's not your birthday yet then output
// Your Birthday Is 00:00:00 Away
if (isBirthday == 0)
begin
// Set boiler plate bits
ROWDATA_1 [0:255]= 256'b1000100000000000000000000000000000000000111100000100000000000000010000001000000000001000000000000000000000000000111000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011100000000000000000000000000000000000000000000;
ROWDATA_2 [0:255]= 256'b1000100000000000000000000000000000000000100010000000000000000000010000001000000000001000000000000000000000000000010000000000000000000000000000000000000011000000000000000000000011000000000000000000000000000000100010000000000000000000000000000000000000000000;
ROWDATA_3 [0:255]= 256'b1000100001110000100010001011000000000000100010001100000010110000111000001011000001101000011100001000100000000000010000000111000000000000000000000000000011000000000000000000000011000000000000000000000000000000100010001000100001110000100010000000000000000000;
ROWDATA_4 [0:255]= 256'b0101000010001000100010001100100000000000111100000100000011001000010000001100100010011000000010001000100000000000010000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100010001010100000001000100010000000000000000000;
ROWDATA_5 [0:255]= 256'b0010000010001000100010001000000000000000100010000100000010000000010000001000100010001000011110000111100000000000010000000111000000000000000000000000000011000000000000000000000011000000000000000000000000000000111110001010100001111000011110000000000000000000;
ROWDATA_6 [0:255]= 256'b0010000010001000100110001000000000000000100010000100000010000000010010001000100010001000100010000000100000000000010000000000100000000000000000000000000011000000000000000000000011000000000000000000000000000000100010001010100010001000000010000000000000000000;
ROWDATA_7 [0:255]= 256'b0010000001110000011010001000000000000000111100001110000010000000001100001000100001111000011110000111000000000000111000001111000000000000000000000000000000000000000000000000000000000000000000000000000000000000100010000101000001111000011100000000000000000000;
ROWDATA_8 [0:255]= 256'b0;
// Hours
ROWDATA_1[136:151] = hROW1[0:15];
ROWDATA_2[136:151] = hROW2[0:15];
ROWDATA_3[136:151] = hROW3[0:15];
ROWDATA_4[136:151] = hROW4[0:15];
ROWDATA_5[136:151] = hROW5[0:15];
ROWDATA_6[136:151] = hROW6[0:15];
ROWDATA_7[136:151] = hROW7[0:15];
ROWDATA_8[136:151] = hROW8[0:15];
// Minutes
ROWDATA_1[160:175] = mROW1[0:15];
ROWDATA_2[160:175] = mROW2[0:15];
ROWDATA_3[160:175] = mROW3[0:15];
ROWDATA_4[160:175] = mROW4[0:15];
ROWDATA_5[160:175] = mROW5[0:15];
ROWDATA_6[160:175] = mROW6[0:15];
ROWDATA_7[160:175] = mROW7[0:15];
ROWDATA_8[160:175] = mROW8[0:15];
// Seconds
ROWDATA_1[184:199] = sROW1[0:15];
ROWDATA_2[184:199] = sROW2[0:15];
ROWDATA_3[184:199] = sROW3[0:15];
ROWDATA_4[184:199] = sROW4[0:15];
ROWDATA_5[184:199] = sROW5[0:15];
ROWDATA_6[184:199] = sROW6[0:15];
ROWDATA_7[184:199] = sROW7[0:15];
ROWDATA_8[184:199] = sROW8[0:15];
end
else
begin
// Assign fixed text to lines
// HAPPY BIRTHDAY!
ROWDATA_1 [0:255]= 256'b1000100000000000000000000000000000000000000000001111000001000000000000000100000010000000000010000000000000000000100000000000000000111100000000000011110000000000001111000000000000111100000000000011110000000000001111000000000000111100000000000011110000000000;
ROWDATA_2 [0:255]= 256'b1000100000000000000000000000000000000000000000001000100000000000000000000100000010000000000010000000000000000000100000000000000001000010000000000100001000000000010000100000000001000010000000000100001000000000010000100000000001000010000000000100001000000000;
ROWDATA_3 [0:255]= 256'b1000100001110000111100001111000010001000000000001000100011000000101100001110000010110000011010000111000010001000100000000000000010101001000000001010100100000000101010010000000010101001000000001010100100000000101010010000000010101001000000001010100100000000;
ROWDATA_4 [0:255]= 256'b1111100000001000100010001000100010001000000000001111000001000000110010000100000011001000100110000000100010001000100000000000000010101001000000001010100100000000101010010000000010101001000000001010100100000000101010010000000010101001000000001010100100000000;
ROWDATA_5 [0:255]= 256'b1000100001111000111100001111000001111000000000001000100001000000100000000100000010001000100010000111100001111000000000000000000010000101000000001000010100000000100001010000000010000101000000001000010100000000100001010000000010000101000000001000010100000000;
ROWDATA_6 [0:255]= 256'b1000100010001000100000001000000000001000000000001000100001000000100000000100100010001000100010001000100000001000000000000000000010111001000000001011100100000000101110010000000010111001000000001011100100000000101110010000000010111001000000001011100100000000;
ROWDATA_7 [0:255]= 256'b1000100001111000100000001000000001110000000000001111000011100000100000000011000010001000011110000111100001110000100000000000000001000010000000000100001000000000010000100000000001000010000000000100001000000000010000100000000001000010000000000100001000000000;
ROWDATA_8 [0:255]= 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000111100000000000011110000000000001111000000000000111100000000000011110000000000001111000000000000111100000000000011110000000000;
end
end
always @(posedge hertz_1) begin
if (seconds == 0) begin
if (minutes == 0) begin
if (hours == 0) begin
isBirthday = 1;
end
else begin
seconds = 59;
minutes = 59;
isBirthday = 0;
hours = hours -1;
end
end
else begin
seconds = 59;
isBirthday = 0;
minutes = minutes - 1;
end
end
else begin
isBirthday = 0;
seconds = seconds - 1;
end
if (pressed[7:0] == 8'h15)
begin
seconds = 0;
if (hours <99)
begin
hours = hours + 1;
end
end
if (pressed[7:0] == 8'h1C)
begin
seconds = 0;
if (hours >0)
begin
hours = hours - 1;
end
end
if (pressed[7:0] == 8'h1D)
begin
seconds = 0;
if (minutes <59)
begin
seconds = 0;
minutes = minutes + 1;
end
end
if (pressed[7:0] == 8'h1B)
begin
seconds = 0;
if (minutes > 0)
begin
minutes = minutes - 1;
end
end
end
endmodule
|
module toLED (GPIO_0, SW,CLOCK_50, LEDG ,LINE_0 , LINE_1, LINE_2, LINE_3, LINE_4, LINE_5, LINE_6, LINE_7);
output [25:0]GPIO_0;
input CLOCK_50;
//output [17:0]LEDR;
output [6:0]LEDG;
input[16:0] SW;
input [0:7] LINE_1,LINE_2,LINE_3,LINE_4,LINE_5,LINE_6,LINE_7,LINE_0;
reg data_in, load_in;
reg [0:15]enterDigit0;
reg [0:15]enterDigit1;
reg [0:15]enterDigit2;
reg [0:15]enterDigit3;
reg [0:15]enterDigit4;
reg [0:15]enterDigit5;
reg [0:15]enterDigit6;
reg [0:15]enterDigit7;
reg [0:15]enterDigit8;
reg [0:15]enterDigit9;
reg [0:15]enterDigit10;
reg [15:0]testLED;
reg [6:0] testGLED;
reg [0:7] start0,start1,start2,start3,start4,start5,start6,start7;
reg [31:0]counterX;
reg [31:0]counterY;
wire clockToUse;
CLOCKER clocker1(CLOCK_50,clockToUse);
initial
begin
counterX = 0;
counterY = 7;
load_in = 0;
testGLED = 7'b0;
start0 [0:7]= 8'b11110001;
start1[0:7] = 8'b11110010;
start2[0:7] = 8'b11110011;
start3[0:7] = 8'b11110100;
start4[0:7] = 8'b11110101;
start5[0:7] = 8'b11110110;
start6[0:7] = 8'b11110111;
start7[0:7] = 8'b11111000;
// Number of bits : 4 (4)(8)
// Format of bits : xxxx (0000) (00000000)
// Description of bits : anything (address) (data)
enterDigit0[0:15] = ({start0[0:7],LINE_0[0:7]});
enterDigit1[0:15] = ({start1[0:7],LINE_1[0:7]});
enterDigit2[0:15] = ({start2[0:7],LINE_2[0:7]});
enterDigit3[0:15] = ({start3[0:7],LINE_3[0:7]});
enterDigit4[0:15] = ({start4[0:7],LINE_4[0:7]});
enterDigit5[0:15] = ({start5[0:7],LINE_5[0:7]});
enterDigit6[0:15] = ({start6[0:7],LINE_6[0:7]});
enterDigit7[0:15] = ({start7[0:7],LINE_7[0:7]});
enterDigit8[0:15] = 16'b1111110011111111; //op current set to shutdown - NORMAL OPERATION
enterDigit9[0:15] = 16'b1111101111111111; //scan limit set to 7
enterDigit10[0:15]= 16'b1111101011111111; //Intensity set to max
end
assign GPIO_0[10] = data_in; //DIN
assign GPIO_0[14] = clockToUse; //CLOCK
assign LEDG = testGLED;
assign GPIO_0 [12] = load_in;
//assign LEDR[16] = load_in;
always @ (negedge clockToUse) begin
// re update data
enterDigit0[0:15] = ({start0[0:7],LINE_0[0:7]});
enterDigit1[0:15] = ({start1[0:7],LINE_1[0:7]});
enterDigit2[0:15] = ({start2[0:7],LINE_2[0:7]});
enterDigit3[0:15] = ({start3[0:7],LINE_3[0:7]});
enterDigit4[0:15] = ({start4[0:7],LINE_4[0:7]});
enterDigit5[0:15] = ({start5[0:7],LINE_5[0:7]});
enterDigit6[0:15] = ({start6[0:7],LINE_6[0:7]});
enterDigit7[0:15] = ({start7[0:7],LINE_7[0:7]});
// Load data for row
case (counterY)
0 :
begin
data_in <= enterDigit0[counterX];
testLED[counterX] <= enterDigit0[counterX];
end
1 :
begin
data_in <= enterDigit1[counterX];
testLED[counterX] <= enterDigit1[counterX];
end
2 :
begin
data_in <= enterDigit2[counterX];
testLED[counterX] <= enterDigit2[counterX];
end
3 :
begin
data_in <= enterDigit3[counterX];
testLED[counterX] <= enterDigit3[counterX];
end
4 :
begin
data_in <= enterDigit4[counterX];
testLED[counterX] <= enterDigit4[counterX];
end
5 :
begin
data_in <= enterDigit5[counterX];
testLED[counterX] <= enterDigit5[counterX];
end
6 :
begin
data_in <= enterDigit6[counterX];
testLED[counterX] <= enterDigit6[counterX];
end
7 :
begin
data_in <= enterDigit7[counterX];
testLED[counterX] <= enterDigit7[counterX];
end
8 :
begin
data_in <= enterDigit8[counterX];
testLED[counterX] <= enterDigit8[counterX];
end
9 :
begin
data_in <= enterDigit9[counterX];
testLED[counterX] <= enterDigit9[counterX];
end
10 :
begin
data_in <= enterDigit10[counterX];
testLED[counterX] <= enterDigit10[counterX];
end
endcase
testGLED[6:0] = 7'b0;
testGLED[counterY] <= 1;
// If on the 1st clock edge set load in low
if (counterX == 0)
begin
load_in = 1;
end
else
begin
load_in = 0;
end
if (counterX == 15)
begin
// On the 16th clock edge set load in low
testLED[15:0] = 16'b0000000000000000;
// Reset column
counterX =0;
// Increment row
counterY = counterY + 1;
// Reset row
if (counterY == 11)
begin
counterY = 0;
end
end
else
begin
counterX = counterX + 1;
end
end
endmodule
|
module clk_1_sec(
input clk_50mhz,
output reg clk_1hz
);
reg [31:0] count;
always @(posedge clk_50mhz)
begin
count <= count + 1;
if(count == 25000000) begin
count <= 0;
clk_1hz <= ~clk_1hz;
end
end
endmodule
|
module clk_1_tenth_sec(
input clk_50mhz,
output reg clk_1hz
);
reg [31:0] count;
always @(posedge clk_50mhz)
begin
count <= count + 1;
if(count == 2500000) begin
count <= 0;
clk_1hz <= ~clk_1hz;
end
end
endmodule
|
module CLOCKER(
input clk_50mhz,
output reg clk_1hz
);
reg [31:0] count;
always @(posedge clk_50mhz)
begin
count <= count + 1;
if(count == 500) begin
count <= 0;
clk_1hz <= ~clk_1hz;
end
end
endmodule
|
module twoDigitNumberTo8BitDisplay(NUMBER, ROW1, ROW2, ROW3, ROW4, ROW5, ROW6, ROW7, ROW8);
output reg [0:15]ROW1, ROW2, ROW3, ROW4, ROW5, ROW6, ROW7, ROW8;
input [31:0] NUMBER;
reg [0:7]firstDigitRow1, firstDigitRow2, firstDigitRow3, firstDigitRow4, firstDigitRow5, firstDigitRow6, firstDigitRow7, firstDigitRow8;
reg [0:7]secondDigitRow1, secondDigitRow2, secondDigitRow3, secondDigitRow4, secondDigitRow5, secondDigitRow6, secondDigitRow7, secondDigitRow8;
integer firstDigit;
integer secondDigit;
always
begin
firstDigit = (NUMBER/10);
secondDigit = (NUMBER%10);
case(firstDigit)
0 :
begin
firstDigitRow1 [0:7]=8'b01110000;
firstDigitRow2 [0:7]=8'b10001000;
firstDigitRow3 [0:7]=8'b10011000;
firstDigitRow4 [0:7]=8'b10101000;
firstDigitRow5 [0:7]=8'b11001000;
firstDigitRow6 [0:7]=8'b10001000;
firstDigitRow7 [0:7]=8'b01110000;
firstDigitRow8 [0:7]=8'b00000000;
end
1 :
begin
firstDigitRow1 [0:7]=8'b01000000;
firstDigitRow2 [0:7]=8'b11000000;
firstDigitRow3 [0:7]=8'b01000000;
firstDigitRow4 [0:7]=8'b01000000;
firstDigitRow5 [0:7]=8'b01000000;
firstDigitRow6 [0:7]=8'b01000000;
firstDigitRow7 [0:7]=8'b11100000;
firstDigitRow8 [0:7]=8'b00000000;
end
2 :
begin
firstDigitRow1 [0:7]=8'b01110000;
firstDigitRow2 [0:7]=8'b10001000;
firstDigitRow3 [0:7]=8'b00001000;
firstDigitRow4 [0:7]=8'b00010000;
firstDigitRow5 [0:7]=8'b00100000;
firstDigitRow6 [0:7]=8'b01000000;
firstDigitRow7 [0:7]=8'b11111000;
firstDigitRow8 [0:7]=8'b00000000;
end
3 :
begin
firstDigitRow1 [0:7]=8'b11111000;
firstDigitRow2 [0:7]=8'b00010000;
firstDigitRow3 [0:7]=8'b00100000;
firstDigitRow4 [0:7]=8'b00010000;
firstDigitRow5 [0:7]=8'b00001000;
firstDigitRow6 [0:7]=8'b10001000;
firstDigitRow7 [0:7]=8'b01110000;
firstDigitRow8 [0:7]=8'b00000000;
end
4 :
begin
firstDigitRow1 [0:7]=8'b00010000;
firstDigitRow2 [0:7]=8'b00110000;
firstDigitRow3 [0:7]=8'b01010000;
firstDigitRow4 [0:7]=8'b10010000;
firstDigitRow5 [0:7]=8'b11111000;
firstDigitRow6 [0:7]=8'b00010000;
firstDigitRow7 [0:7]=8'b00010000;
firstDigitRow8 [0:7]=8'b00000000;
end
5 :
begin
firstDigitRow1 [0:7]=8'b11111000;
firstDigitRow2 [0:7]=8'b10000000;
firstDigitRow3 [0:7]=8'b11110000;
firstDigitRow4 [0:7]=8'b00001000;
firstDigitRow5 [0:7]=8'b00001000;
firstDigitRow6 [0:7]=8'b10001000;
firstDigitRow7 [0:7]=8'b01110000;
firstDigitRow8 [0:7]=8'b00000000;
end
6 :
begin
firstDigitRow1 [0:7]=8'b00110000;
firstDigitRow2 [0:7]=8'b01000000;
firstDigitRow3 [0:7]=8'b10000000;
firstDigitRow4 [0:7]=8'b11110000;
firstDigitRow5 [0:7]=8'b10001000;
firstDigitRow6 [0:7]=8'b10001000;
firstDigitRow7 [0:7]=8'b01110000;
firstDigitRow8 [0:7]=8'b00000000;
end
7 :
begin
firstDigitRow1 [0:7]=8'b11111000;
firstDigitRow2 [0:7]=8'b10001000;
firstDigitRow3 [0:7]=8'b00001000;
firstDigitRow4 [0:7]=8'b00010000;
firstDigitRow5 [0:7]=8'b00100000;
firstDigitRow6 [0:7]=8'b00100000;
firstDigitRow7 [0:7]=8'b00100000;
firstDigitRow8 [0:7]=8'b00000000;
end
8 :
begin
firstDigitRow1 [0:7]=8'b01110000;
firstDigitRow2 [0:7]=8'b10001000;
firstDigitRow3 [0:7]=8'b10001000;
firstDigitRow4 [0:7]=8'b01110000;
firstDigitRow5 [0:7]=8'b10001000;
firstDigitRow6 [0:7]=8'b10001000;
firstDigitRow7 [0:7]=8'b01110000;
firstDigitRow8 [0:7]=8'b00000000;
end
9 :
begin
firstDigitRow1 [0:7]=8'b01110000;
firstDigitRow2 [0:7]=8'b10001000;
firstDigitRow3 [0:7]=8'b10001000;
firstDigitRow4 [0:7]=8'b01111000;
firstDigitRow5 [0:7]=8'b00001000;
firstDigitRow6 [0:7]=8'b00010000;
firstDigitRow7 [0:7]=8'b01100000;
firstDigitRow8 [0:7]=8'b00000000;
end
endcase
case(secondDigit)
0 :
begin
secondDigitRow1 [0:7]=8'b01110000;
secondDigitRow2 [0:7]=8'b10001000;
secondDigitRow3 [0:7]=8'b10011000;
secondDigitRow4 [0:7]=8'b10101000;
secondDigitRow5 [0:7]=8'b11001000;
secondDigitRow6 [0:7]=8'b10001000;
secondDigitRow7 [0:7]=8'b01110000;
secondDigitRow8 [0:7]=8'b00000000;
end
1 :
begin
secondDigitRow1 [0:7]=8'b01000000;
secondDigitRow2 [0:7]=8'b11000000;
secondDigitRow3 [0:7]=8'b01000000;
secondDigitRow4 [0:7]=8'b01000000;
secondDigitRow5 [0:7]=8'b01000000;
secondDigitRow6 [0:7]=8'b01000000;
secondDigitRow7 [0:7]=8'b11100000;
secondDigitRow8 [0:7]=8'b00000000;
end
2 :
begin
secondDigitRow1 [0:7]=8'b01110000;
secondDigitRow2 [0:7]=8'b10001000;
secondDigitRow3 [0:7]=8'b00001000;
secondDigitRow4 [0:7]=8'b00010000;
secondDigitRow5 [0:7]=8'b00100000;
secondDigitRow6 [0:7]=8'b01000000;
secondDigitRow7 [0:7]=8'b11111000;
secondDigitRow8 [0:7]=8'b00000000;
end
3 :
begin
secondDigitRow1 [0:7]=8'b11111000;
secondDigitRow2 [0:7]=8'b00010000;
secondDigitRow3 [0:7]=8'b00100000;
secondDigitRow4 [0:7]=8'b00010000;
secondDigitRow5 [0:7]=8'b00001000;
secondDigitRow6 [0:7]=8'b10001000;
secondDigitRow7 [0:7]=8'b01110000;
secondDigitRow8 [0:7]=8'b00000000;
end
4 :
begin
secondDigitRow1 [0:7]=8'b00010000;
secondDigitRow2 [0:7]=8'b00110000;
secondDigitRow3 [0:7]=8'b01010000;
secondDigitRow4 [0:7]=8'b10010000;
secondDigitRow5 [0:7]=8'b11111000;
secondDigitRow6 [0:7]=8'b00010000;
secondDigitRow7 [0:7]=8'b00010000;
secondDigitRow8 [0:7]=8'b00000000;
end
5 :
begin
secondDigitRow1 [0:7]=8'b11111000;
secondDigitRow2 [0:7]=8'b10000000;
secondDigitRow3 [0:7]=8'b11110000;
secondDigitRow4 [0:7]=8'b00001000;
secondDigitRow5 [0:7]=8'b00001000;
secondDigitRow6 [0:7]=8'b10001000;
secondDigitRow7 [0:7]=8'b01110000;
secondDigitRow8 [0:7]=8'b00000000;
end
6 :
begin
secondDigitRow1 [0:7]=8'b00110000;
secondDigitRow2 [0:7]=8'b01000000;
secondDigitRow3 [0:7]=8'b10000000;
secondDigitRow4 [0:7]=8'b11110000;
secondDigitRow5 [0:7]=8'b10001000;
secondDigitRow6 [0:7]=8'b10001000;
secondDigitRow7 [0:7]=8'b01110000;
secondDigitRow8 [0:7]=8'b00000000;
end
7 :
begin
secondDigitRow1 [0:7]=8'b11111000;
secondDigitRow2 [0:7]=8'b10001000;
secondDigitRow3 [0:7]=8'b00001000;
secondDigitRow4 [0:7]=8'b00010000;
secondDigitRow5 [0:7]=8'b00100000;
secondDigitRow6 [0:7]=8'b00100000;
secondDigitRow7 [0:7]=8'b00100000;
secondDigitRow8 [0:7]=8'b00000000;
end
8 :
begin
secondDigitRow1 [0:7]=8'b01110000;
secondDigitRow2 [0:7]=8'b10001000;
secondDigitRow3 [0:7]=8'b10001000;
secondDigitRow4 [0:7]=8'b01110000;
secondDigitRow5 [0:7]=8'b10001000;
secondDigitRow6 [0:7]=8'b10001000;
secondDigitRow7 [0:7]=8'b01110000;
secondDigitRow8 [0:7]=8'b00000000;
end
9 :
begin
secondDigitRow1 [0:7]=8'b01110000;
secondDigitRow2 [0:7]=8'b10001000;
secondDigitRow3 [0:7]=8'b10001000;
secondDigitRow4 [0:7]=8'b01111000;
secondDigitRow5 [0:7]=8'b00001000;
secondDigitRow6 [0:7]=8'b00010000;
secondDigitRow7 [0:7]=8'b01100000;
secondDigitRow8 [0:7]=8'b00000000;
end
endcase
ROW1[0:15] = ({firstDigitRow1[0:7] , secondDigitRow1[0:7]});
ROW2[0:15]= ({firstDigitRow2[0:7] , secondDigitRow2[0:7]});
ROW3[0:15] = ({firstDigitRow3[0:7] , secondDigitRow3[0:7]});
ROW4[0:15] = ({firstDigitRow4 [0:7], secondDigitRow4[0:7]});
ROW5[0:15] = ({firstDigitRow5 [0:7], secondDigitRow5[0:7]});
ROW6[0:15] = ({firstDigitRow6 [0:7], secondDigitRow6[0:7]});
ROW7[0:15] = ({firstDigitRow7[0:7] , secondDigitRow7[0:7]});
ROW8[0:15] = ({firstDigitRow8[0:7], secondDigitRow8[0:7]});
end
endmodule
|
module tb_aceusb();
reg sys_clk;
reg sys_rst;
reg ace_clk;
reg [31:0] wb_adr_i;
reg [31:0] wb_dat_i;
wire [31:0] wb_dat_o;
reg wb_cyc_i;
reg wb_stb_i;
reg wb_we_i;
wire wb_ack_o;
wire [6:0] aceusb_a;
wire [15:0] aceusb_d;
wire aceusb_oe_n;
wire aceusb_we_n;
wire ace_clkin;
wire ace_mpce_n;
wire ace_mpirq;
wire usb_cs_n;
wire usb_hpi_reset_n;
wire usb_hpi_int;
aceusb dut(
.sys_clk(sys_clk),
.sys_rst(sys_rst),
.wb_adr_i(wb_adr_i),
.wb_dat_i(wb_dat_i),
.wb_dat_o(wb_dat_o),
.wb_cyc_i(wb_cyc_i),
.wb_stb_i(wb_stb_i),
.wb_we_i(wb_we_i),
.wb_ack_o(wb_ack_o),
.aceusb_a(aceusb_a),
.aceusb_d(aceusb_d),
.aceusb_oe_n(aceusb_oe_n),
.aceusb_we_n(aceusb_we_n),
.ace_clkin(ace_clk),
.ace_mpce_n(ace_mpce_n),
.ace_mpirq(ace_mpirq),
.usb_cs_n(usb_cs_n),
.usb_hpi_reset_n(usb_hpi_reset_n),
.usb_hpi_int(usb_hpi_int)
);
assign aceusb_d = aceusb_oe_n ? 16'h1234 : 16'hzzzz;
initial begin
$dumpfile("aceusb.vcd");
$dumpvars(1, dut);
end
/* Generate ~33MHz SystemACE clock */
initial ace_clk <= 0;
always #7.5 ace_clk <= ~ace_clk;
task wbwrite;
input [31:0] address;
input [31:0] data;
integer i;
begin
wb_adr_i = address;
wb_dat_i = data;
wb_cyc_i = 1'b1;
wb_stb_i = 1'b1;
wb_we_i = 1'b1;
i = 1;
while(~wb_ack_o) begin
#5 sys_clk = 1'b1;
#5 sys_clk = 1'b0;
i = i + 1;
end
$display("Write address %h completed in %d cycles", address, i);
/* Let the core release its ack */
#5 sys_clk = 1'b1;
#5 sys_clk = 1'b0;
wb_we_i = 1'b1;
wb_cyc_i = 1'b0;
wb_stb_i = 1'b0;
end
endtask
task wbread;
input [31:0] address;
integer i;
begin
wb_adr_i = address;
wb_cyc_i = 1'b1;
wb_stb_i = 1'b1;
wb_we_i = 1'b0;
i = 1;
while(~wb_ack_o) begin
#5 sys_clk = 1'b1;
#5 sys_clk = 1'b0;
i = i + 1;
end
$display("Read address %h completed in %d cycles, result %h", address, i, wb_dat_o);
/* Let the core release its ack */
#5 sys_clk = 1'b1;
#5 sys_clk = 1'b0;
wb_cyc_i = 1'b0;
wb_stb_i = 1'b0;
end
endtask
initial begin
sys_rst = 1'b1;
sys_clk = 1'b0;
wb_adr_i = 32'h00000000;
wb_dat_i = 32'h00000000;
wb_cyc_i = 1'b0;
wb_stb_i = 1'b0;
wb_we_i = 1'b0;
#5 sys_clk = 1'b1;
#5 sys_clk = 1'b0;
#5 sys_clk = 1'b1;
#5 sys_clk = 1'b0;
#5 sys_clk = 1'b1;
#5 sys_clk = 1'b0;
#5 sys_clk = 1'b1;
#5 sys_clk = 1'b0;
#5 sys_clk = 1'b1;
#5 sys_clk = 1'b0;
#5 sys_clk = 1'b1;
#5 sys_clk = 1'b0;
#5 sys_clk = 1'b1;
#5 sys_clk = 1'b0;
sys_rst = 1'b0;
wbwrite(32'h00000180, 32'hcafebabe);
wbread(32'h00000020);
$finish;
end
endmodule
|
module sky130_fd_sc_hdll__a21o (
X ,
A1 ,
A2 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A1 ;
input A2 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire and0_out ;
wire or0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
and and0 (and0_out , A1, A2 );
or or0 (or0_out_X , and0_out, B1 );
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, or0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
|
module sky130_fd_sc_ls__nor4b_2 (
Y ,
A ,
B ,
C ,
D_N ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input B ;
input C ;
input D_N ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__nor4b base (
.Y(Y),
.A(A),
.B(B),
.C(C),
.D_N(D_N),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
|
module sky130_fd_sc_ls__nor4b_2 (
Y ,
A ,
B ,
C ,
D_N
);
output Y ;
input A ;
input B ;
input C ;
input D_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__nor4b base (
.Y(Y),
.A(A),
.B(B),
.C(C),
.D_N(D_N)
);
endmodule
|
module test_warmboot (input wire btn1, btn2, output reg [7:0] data);
//-- Instanciar el bloque warm boot.
top wb (
.boot(btn2),
.s1(image[1]),
.s0(image[0])
);
// Registro del valor de la imagen a cargar.
reg [1:0] image = 2'b00;
//-- Al pulsar el botón 1 hacemos cambiar el bit 7
// para mostrar la pulsación y elegimos la siguiente imagen.
always @(posedge(btn1)) begin
data[7] = ~data[7];
image = image + 1;
end
// Se muestra la imagen a cargar tras el warn boot (al pulsar el botón 2).
assign data[6:0] = {5'b00000, image[1], image[0]};
endmodule
|
module sky130_fd_sc_ls__o311a (
X ,
A1,
A2,
A3,
B1,
C1
);
output X ;
input A1;
input A2;
input A3;
input B1;
input C1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
|
module cx4_mul (
clk, p, a, b
)/* synthesis syn_black_box syn_noprune=1 */;
input clk;
output [47 : 0] p;
input [23 : 0] a;
input [23 : 0] b;
// synthesis translate_off
wire \blk00000001/sig0000021b ;
wire \blk00000001/sig0000021a ;
wire \blk00000001/sig00000219 ;
wire \blk00000001/sig00000218 ;
wire \blk00000001/sig00000217 ;
wire \blk00000001/sig00000216 ;
wire \blk00000001/sig00000215 ;
wire \blk00000001/sig00000214 ;
wire \blk00000001/sig00000213 ;
wire \blk00000001/sig00000212 ;
wire \blk00000001/sig00000211 ;
wire \blk00000001/sig00000210 ;
wire \blk00000001/sig0000020f ;
wire \blk00000001/sig0000020e ;
wire \blk00000001/sig0000020d ;
wire \blk00000001/sig0000020c ;
wire \blk00000001/sig0000020b ;
wire \blk00000001/sig0000020a ;
wire \blk00000001/sig00000209 ;
wire \blk00000001/sig00000208 ;
wire \blk00000001/sig00000207 ;
wire \blk00000001/sig00000206 ;
wire \blk00000001/sig00000205 ;
wire \blk00000001/sig00000204 ;
wire \blk00000001/sig00000203 ;
wire \blk00000001/sig00000202 ;
wire \blk00000001/sig00000201 ;
wire \blk00000001/sig00000200 ;
wire \blk00000001/sig000001ff ;
wire \blk00000001/sig000001fe ;
wire \blk00000001/sig000001fd ;
wire \blk00000001/sig000001fc ;
wire \blk00000001/sig000001fb ;
wire \blk00000001/sig000001fa ;
wire \blk00000001/sig000001f9 ;
wire \blk00000001/sig000001f8 ;
wire \blk00000001/sig000001f7 ;
wire \blk00000001/sig000001f6 ;
wire \blk00000001/sig000001f5 ;
wire \blk00000001/sig000001f4 ;
wire \blk00000001/sig000001f3 ;
wire \blk00000001/sig000001f2 ;
wire \blk00000001/sig000001f1 ;
wire \blk00000001/sig000001f0 ;
wire \blk00000001/sig000001ef ;
wire \blk00000001/sig000001ee ;
wire \blk00000001/sig000001ed ;
wire \blk00000001/sig000001ec ;
wire \blk00000001/sig000001eb ;
wire \blk00000001/sig000001ea ;
wire \blk00000001/sig000001e9 ;
wire \blk00000001/sig000001e8 ;
wire \blk00000001/sig000001e7 ;
wire \blk00000001/sig000001e6 ;
wire \blk00000001/sig000001e5 ;
wire \blk00000001/sig000001e4 ;
wire \blk00000001/sig000001e3 ;
wire \blk00000001/sig000001e2 ;
wire \blk00000001/sig000001e1 ;
wire \blk00000001/sig000001e0 ;
wire \blk00000001/sig000001df ;
wire \blk00000001/sig000001de ;
wire \blk00000001/sig000001dd ;
wire \blk00000001/sig000001dc ;
wire \blk00000001/sig000001db ;
wire \blk00000001/sig000001da ;
wire \blk00000001/sig000001d9 ;
wire \blk00000001/sig000001d8 ;
wire \blk00000001/sig000001d7 ;
wire \blk00000001/sig000001d6 ;
wire \blk00000001/sig000001d5 ;
wire \blk00000001/sig000001d4 ;
wire \blk00000001/sig000001d3 ;
wire \blk00000001/sig000001d2 ;
wire \blk00000001/sig000001d1 ;
wire \blk00000001/sig000001d0 ;
wire \blk00000001/sig000001cf ;
wire \blk00000001/sig000001ce ;
wire \blk00000001/sig000001cd ;
wire \blk00000001/sig000001cc ;
wire \blk00000001/sig000001cb ;
wire \blk00000001/sig000001ca ;
wire \blk00000001/sig000001c9 ;
wire \blk00000001/sig000001c8 ;
wire \blk00000001/sig000001c7 ;
wire \blk00000001/sig000001c6 ;
wire \blk00000001/sig000001c5 ;
wire \blk00000001/sig000001c4 ;
wire \blk00000001/sig000001c3 ;
wire \blk00000001/sig000001c2 ;
wire \blk00000001/sig000001c1 ;
wire \blk00000001/sig000001c0 ;
wire \blk00000001/sig000001bf ;
wire \blk00000001/sig000001be ;
wire \blk00000001/sig000001bd ;
wire \blk00000001/sig000001bc ;
wire \blk00000001/sig000001bb ;
wire \blk00000001/sig000001ba ;
wire \blk00000001/sig000001b9 ;
wire \blk00000001/sig000001b8 ;
wire \blk00000001/sig000001b7 ;
wire \blk00000001/sig000001b6 ;
wire \blk00000001/sig000001b5 ;
wire \blk00000001/sig000001b4 ;
wire \blk00000001/sig000001b3 ;
wire \blk00000001/sig000001b2 ;
wire \blk00000001/sig000001b1 ;
wire \blk00000001/sig000001b0 ;
wire \blk00000001/sig000001af ;
wire \blk00000001/sig000001ae ;
wire \blk00000001/sig000001ad ;
wire \blk00000001/sig000001ac ;
wire \blk00000001/sig000001ab ;
wire \blk00000001/sig000001aa ;
wire \blk00000001/sig000001a9 ;
wire \blk00000001/sig000001a8 ;
wire \blk00000001/sig000001a7 ;
wire \blk00000001/sig000001a6 ;
wire \blk00000001/sig000001a5 ;
wire \blk00000001/sig000001a4 ;
wire \blk00000001/sig000001a3 ;
wire \blk00000001/sig000001a2 ;
wire \blk00000001/sig000001a1 ;
wire \blk00000001/sig000001a0 ;
wire \blk00000001/sig0000019f ;
wire \blk00000001/sig0000019e ;
wire \blk00000001/sig0000019d ;
wire \blk00000001/sig0000019c ;
wire \blk00000001/sig0000019b ;
wire \blk00000001/sig0000019a ;
wire \blk00000001/sig00000199 ;
wire \blk00000001/sig00000198 ;
wire \blk00000001/sig00000197 ;
wire \blk00000001/sig00000196 ;
wire \blk00000001/sig00000195 ;
wire \blk00000001/sig00000194 ;
wire \blk00000001/sig00000193 ;
wire \blk00000001/sig00000192 ;
wire \blk00000001/sig00000191 ;
wire \blk00000001/sig00000190 ;
wire \blk00000001/sig0000018f ;
wire \blk00000001/sig0000018e ;
wire \blk00000001/sig0000018d ;
wire \blk00000001/sig0000018c ;
wire \blk00000001/sig0000018b ;
wire \blk00000001/sig0000018a ;
wire \blk00000001/sig00000189 ;
wire \blk00000001/sig00000188 ;
wire \blk00000001/sig00000187 ;
wire \blk00000001/sig00000186 ;
wire \blk00000001/sig00000185 ;
wire \blk00000001/sig00000184 ;
wire \blk00000001/sig00000183 ;
wire \blk00000001/sig00000182 ;
wire \blk00000001/sig00000181 ;
wire \blk00000001/sig00000180 ;
wire \blk00000001/sig0000017f ;
wire \blk00000001/sig0000017e ;
wire \blk00000001/sig0000017d ;
wire \blk00000001/sig0000017c ;
wire \blk00000001/sig0000017b ;
wire \blk00000001/sig0000017a ;
wire \blk00000001/sig00000179 ;
wire \blk00000001/sig00000178 ;
wire \blk00000001/sig00000177 ;
wire \blk00000001/sig00000176 ;
wire \blk00000001/sig00000175 ;
wire \blk00000001/sig00000174 ;
wire \blk00000001/sig00000173 ;
wire \blk00000001/sig00000172 ;
wire \blk00000001/sig00000171 ;
wire \blk00000001/sig00000170 ;
wire \blk00000001/sig0000016f ;
wire \blk00000001/sig0000016e ;
wire \blk00000001/sig0000016d ;
wire \blk00000001/sig0000016c ;
wire \blk00000001/sig0000016b ;
wire \blk00000001/sig0000016a ;
wire \blk00000001/sig00000169 ;
wire \blk00000001/sig00000168 ;
wire \blk00000001/sig00000167 ;
wire \blk00000001/sig00000166 ;
wire \blk00000001/sig00000165 ;
wire \blk00000001/sig00000164 ;
wire \blk00000001/sig00000163 ;
wire \blk00000001/sig00000162 ;
wire \blk00000001/sig00000161 ;
wire \blk00000001/sig00000160 ;
wire \blk00000001/sig0000015f ;
wire \blk00000001/sig0000015e ;
wire \blk00000001/sig0000015d ;
wire \blk00000001/sig0000015c ;
wire \blk00000001/sig0000015b ;
wire \blk00000001/sig0000015a ;
wire \blk00000001/sig00000159 ;
wire \blk00000001/sig00000158 ;
wire \blk00000001/sig00000157 ;
wire \blk00000001/sig00000156 ;
wire \blk00000001/sig00000155 ;
wire \blk00000001/sig00000154 ;
wire \blk00000001/sig00000153 ;
wire \blk00000001/sig00000152 ;
wire \blk00000001/sig00000151 ;
wire \blk00000001/sig00000150 ;
wire \blk00000001/sig0000014f ;
wire \blk00000001/sig0000014e ;
wire \blk00000001/sig0000014d ;
wire \blk00000001/sig0000014c ;
wire \blk00000001/sig0000014b ;
wire \blk00000001/sig0000014a ;
wire \blk00000001/sig00000149 ;
wire \blk00000001/sig00000148 ;
wire \blk00000001/sig00000147 ;
wire \blk00000001/sig00000146 ;
wire \blk00000001/sig00000145 ;
wire \blk00000001/sig00000144 ;
wire \blk00000001/sig00000143 ;
wire \blk00000001/sig00000142 ;
wire \blk00000001/sig00000141 ;
wire \blk00000001/sig00000140 ;
wire \blk00000001/sig0000013f ;
wire \blk00000001/sig0000013e ;
wire \blk00000001/sig0000013d ;
wire \blk00000001/sig0000013c ;
wire \blk00000001/sig0000013b ;
wire \blk00000001/sig0000013a ;
wire \blk00000001/sig00000139 ;
wire \blk00000001/sig00000138 ;
wire \blk00000001/sig00000137 ;
wire \blk00000001/sig00000136 ;
wire \blk00000001/sig00000135 ;
wire \blk00000001/sig00000134 ;
wire \blk00000001/sig00000133 ;
wire \blk00000001/sig00000132 ;
wire \blk00000001/sig00000131 ;
wire \blk00000001/sig00000130 ;
wire \blk00000001/sig0000012f ;
wire \blk00000001/sig0000012e ;
wire \blk00000001/sig0000012d ;
wire \blk00000001/sig0000012c ;
wire \blk00000001/sig0000012b ;
wire \blk00000001/sig0000012a ;
wire \blk00000001/sig00000129 ;
wire \blk00000001/sig00000128 ;
wire \blk00000001/sig00000127 ;
wire \blk00000001/sig00000126 ;
wire \blk00000001/sig00000125 ;
wire \blk00000001/sig00000124 ;
wire \blk00000001/sig00000123 ;
wire \blk00000001/sig00000122 ;
wire \blk00000001/sig00000121 ;
wire \blk00000001/sig00000120 ;
wire \blk00000001/sig0000011f ;
wire \blk00000001/sig0000011e ;
wire \blk00000001/sig0000011d ;
wire \blk00000001/sig0000011c ;
wire \blk00000001/sig0000011b ;
wire \blk00000001/sig0000011a ;
wire \blk00000001/sig00000119 ;
wire \blk00000001/sig00000118 ;
wire \blk00000001/sig00000117 ;
wire \blk00000001/sig00000116 ;
wire \blk00000001/sig00000115 ;
wire \blk00000001/sig00000114 ;
wire \blk00000001/sig00000113 ;
wire \blk00000001/sig00000112 ;
wire \blk00000001/sig00000111 ;
wire \blk00000001/sig00000110 ;
wire \blk00000001/sig0000010f ;
wire \blk00000001/sig0000010e ;
wire \blk00000001/sig0000010d ;
wire \blk00000001/sig0000010c ;
wire \blk00000001/sig0000010b ;
wire \blk00000001/sig0000010a ;
wire \blk00000001/sig00000109 ;
wire \blk00000001/sig00000108 ;
wire \blk00000001/sig00000107 ;
wire \blk00000001/sig00000106 ;
wire \blk00000001/sig00000105 ;
wire \blk00000001/sig00000104 ;
wire \blk00000001/sig00000103 ;
wire \blk00000001/sig00000102 ;
wire \blk00000001/sig00000101 ;
wire \blk00000001/sig00000100 ;
wire \blk00000001/sig000000ff ;
wire \blk00000001/sig000000fe ;
wire \blk00000001/sig000000fd ;
wire \blk00000001/sig000000fc ;
wire \blk00000001/sig000000fb ;
wire \blk00000001/sig000000fa ;
wire \blk00000001/sig000000f9 ;
wire \blk00000001/sig000000f8 ;
wire \blk00000001/sig000000f7 ;
wire \blk00000001/sig000000f6 ;
wire \blk00000001/sig000000f5 ;
wire \blk00000001/sig000000f4 ;
wire \blk00000001/sig000000f3 ;
wire \blk00000001/sig000000f2 ;
wire \blk00000001/sig000000f1 ;
wire \blk00000001/sig000000f0 ;
wire \blk00000001/sig000000ef ;
wire \blk00000001/sig000000ee ;
wire \blk00000001/sig000000ed ;
wire \blk00000001/sig000000ec ;
wire \blk00000001/sig000000eb ;
wire \blk00000001/sig000000ea ;
wire \blk00000001/sig000000e9 ;
wire \blk00000001/sig000000e8 ;
wire \blk00000001/sig000000e7 ;
wire \blk00000001/sig000000e6 ;
wire \blk00000001/sig000000e5 ;
wire \blk00000001/sig000000e4 ;
wire \blk00000001/sig000000e3 ;
wire \blk00000001/sig000000e2 ;
wire \blk00000001/sig000000e1 ;
wire \blk00000001/sig000000e0 ;
wire \blk00000001/sig000000df ;
wire \blk00000001/sig000000de ;
wire \blk00000001/sig000000dd ;
wire \blk00000001/sig000000dc ;
wire \blk00000001/sig000000db ;
wire \blk00000001/sig000000da ;
wire \blk00000001/sig000000d9 ;
wire \blk00000001/sig000000d8 ;
wire \blk00000001/sig000000d7 ;
wire \blk00000001/sig000000d6 ;
wire \blk00000001/sig000000d5 ;
wire \blk00000001/sig000000d4 ;
wire \blk00000001/sig000000d3 ;
wire \blk00000001/sig000000d2 ;
wire \blk00000001/sig000000d1 ;
wire \blk00000001/sig000000d0 ;
wire \blk00000001/sig000000cf ;
wire \blk00000001/sig000000ce ;
wire \blk00000001/sig000000cd ;
wire \blk00000001/sig000000cc ;
wire \blk00000001/sig000000cb ;
wire \blk00000001/sig000000ca ;
wire \blk00000001/sig000000c9 ;
wire \blk00000001/sig000000c8 ;
wire \blk00000001/sig000000c7 ;
wire \blk00000001/sig000000c6 ;
wire \blk00000001/sig000000c5 ;
wire \blk00000001/sig000000c4 ;
wire \blk00000001/sig000000c3 ;
wire \blk00000001/sig000000c2 ;
wire \blk00000001/sig000000c1 ;
wire \blk00000001/sig000000c0 ;
wire \blk00000001/sig000000bf ;
wire \blk00000001/sig000000be ;
wire \blk00000001/sig000000bd ;
wire \blk00000001/sig000000bc ;
wire \blk00000001/sig000000bb ;
wire \blk00000001/sig000000ba ;
wire \blk00000001/sig000000b9 ;
wire \blk00000001/sig000000b8 ;
wire \blk00000001/sig000000b7 ;
wire \blk00000001/sig000000b6 ;
wire \blk00000001/sig000000b5 ;
wire \blk00000001/sig000000b4 ;
wire \blk00000001/sig000000b3 ;
wire \blk00000001/sig000000b2 ;
wire \blk00000001/sig000000b1 ;
wire \blk00000001/sig000000b0 ;
wire \blk00000001/sig000000af ;
wire \blk00000001/sig000000ae ;
wire \blk00000001/sig000000ad ;
wire \blk00000001/sig000000ac ;
wire \blk00000001/sig000000ab ;
wire \blk00000001/sig000000aa ;
wire \blk00000001/sig000000a9 ;
wire \blk00000001/sig000000a8 ;
wire \blk00000001/sig000000a7 ;
wire \blk00000001/sig000000a6 ;
wire \blk00000001/sig000000a5 ;
wire \blk00000001/sig000000a4 ;
wire \blk00000001/sig000000a3 ;
wire \blk00000001/sig000000a2 ;
wire \blk00000001/sig000000a1 ;
wire \blk00000001/sig000000a0 ;
wire \blk00000001/sig0000009f ;
wire \blk00000001/sig0000009e ;
wire \blk00000001/sig0000009d ;
wire \blk00000001/sig0000009c ;
wire \blk00000001/sig0000009b ;
wire \blk00000001/sig0000009a ;
wire \blk00000001/sig00000099 ;
wire \blk00000001/sig00000098 ;
wire \blk00000001/sig00000097 ;
wire \blk00000001/sig00000096 ;
wire \blk00000001/sig00000095 ;
wire \blk00000001/sig00000094 ;
wire \blk00000001/sig00000093 ;
wire \blk00000001/sig00000092 ;
wire \blk00000001/sig00000091 ;
wire \blk00000001/sig00000090 ;
wire \blk00000001/sig0000008f ;
wire \blk00000001/sig0000008e ;
wire \blk00000001/sig0000008d ;
wire \blk00000001/sig0000008c ;
wire \blk00000001/sig0000008b ;
wire \blk00000001/sig0000008a ;
wire \blk00000001/sig00000089 ;
wire \blk00000001/sig00000088 ;
wire \blk00000001/sig00000087 ;
wire \blk00000001/sig00000086 ;
wire \blk00000001/sig00000085 ;
wire \blk00000001/sig00000084 ;
wire \blk00000001/sig00000083 ;
wire \blk00000001/sig00000082 ;
wire \blk00000001/sig00000081 ;
wire \blk00000001/sig00000080 ;
wire \blk00000001/sig0000007f ;
wire \blk00000001/sig0000007e ;
wire \blk00000001/sig0000007d ;
wire \blk00000001/sig0000007c ;
wire \blk00000001/sig0000007b ;
wire \blk00000001/sig0000007a ;
wire \blk00000001/sig00000079 ;
wire \blk00000001/sig00000078 ;
wire \blk00000001/sig00000077 ;
wire \blk00000001/sig00000076 ;
wire \blk00000001/sig00000075 ;
wire \blk00000001/sig00000074 ;
wire \blk00000001/sig00000073 ;
wire \blk00000001/sig00000072 ;
wire \blk00000001/sig00000071 ;
wire \blk00000001/sig00000070 ;
wire \blk00000001/sig0000006f ;
wire \blk00000001/sig0000006e ;
wire \blk00000001/sig0000006d ;
wire \blk00000001/sig0000006c ;
wire \blk00000001/sig0000006b ;
wire \blk00000001/sig0000006a ;
wire \blk00000001/sig00000069 ;
wire \blk00000001/sig00000068 ;
wire \blk00000001/sig00000067 ;
wire \blk00000001/sig00000066 ;
wire \blk00000001/sig00000065 ;
wire \blk00000001/sig00000064 ;
wire \blk00000001/sig00000063 ;
wire \blk00000001/sig00000062 ;
wire \blk00000001/sig00000061 ;
wire \blk00000001/sig00000060 ;
wire \blk00000001/sig0000005f ;
wire \blk00000001/sig0000005e ;
wire \blk00000001/sig0000005d ;
wire \blk00000001/sig0000005c ;
wire \blk00000001/sig0000005b ;
wire \blk00000001/sig0000005a ;
wire \blk00000001/sig00000059 ;
wire \blk00000001/sig00000058 ;
wire \blk00000001/sig00000057 ;
wire \blk00000001/sig00000056 ;
wire \blk00000001/sig00000055 ;
wire \blk00000001/sig00000054 ;
wire \blk00000001/sig00000053 ;
wire \blk00000001/sig00000052 ;
wire \blk00000001/sig00000051 ;
wire \blk00000001/sig00000050 ;
wire \blk00000001/sig0000004f ;
wire \blk00000001/sig0000004e ;
wire \blk00000001/sig0000004d ;
wire \blk00000001/sig0000004c ;
wire \blk00000001/sig0000004b ;
wire \blk00000001/sig0000004a ;
wire \blk00000001/sig00000049 ;
wire \blk00000001/sig00000048 ;
wire \blk00000001/sig00000047 ;
wire \blk00000001/sig00000046 ;
wire \blk00000001/sig00000045 ;
wire \blk00000001/sig00000044 ;
wire \blk00000001/sig00000043 ;
wire \blk00000001/sig00000042 ;
wire \blk00000001/sig00000041 ;
wire \blk00000001/sig00000040 ;
wire \blk00000001/sig0000003f ;
wire \blk00000001/sig0000003e ;
wire \blk00000001/sig0000003d ;
wire \blk00000001/sig0000003c ;
wire \blk00000001/sig0000003b ;
wire \blk00000001/sig0000003a ;
wire \blk00000001/sig00000039 ;
wire \blk00000001/sig00000038 ;
wire \blk00000001/sig00000037 ;
wire \blk00000001/sig00000036 ;
wire \blk00000001/sig00000035 ;
wire \blk00000001/sig00000034 ;
wire \blk00000001/sig00000033 ;
wire \blk00000001/sig00000032 ;
wire \NLW_blk00000001/blk0000001e_P<35>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000001d_P<35>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000001d_P<34>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000001d_P<33>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000001d_P<32>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000001d_P<31>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000001d_P<30>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000001d_P<29>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000001d_P<28>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000001d_P<27>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000001d_P<26>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000001d_P<25>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000001d_P<24>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000001c_P<35>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000001c_P<34>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000001c_P<33>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000001c_P<32>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000001c_P<31>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000001c_P<30>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000001c_P<29>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000001c_P<28>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000001c_P<27>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000001c_P<26>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000001c_P<25>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000001c_P<24>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000001b_P<35>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000001b_P<34>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000001b_P<33>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000001b_P<32>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000001b_P<31>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000001b_P<30>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000001b_P<29>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000001b_P<28>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000001b_P<27>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000001b_P<26>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000001b_P<25>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000001b_P<24>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000001b_P<23>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000001b_P<22>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000001b_P<21>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000001b_P<20>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000001b_P<19>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000001b_P<18>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000001b_P<17>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000001b_P<16>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000001b_P<15>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000001b_P<14>_UNCONNECTED ;
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk000001be (
.C(clk),
.D(\blk00000001/sig000000d8 ),
.Q(\blk00000001/sig000000e9 )
);
SRL16 #(
.INIT ( 16'h0000 ))
\blk00000001/blk000001bd (
.A0(\blk00000001/sig0000004b ),
.A1(\blk00000001/sig0000004b ),
.A2(\blk00000001/sig0000004b ),
.A3(\blk00000001/sig0000004b ),
.CLK(clk),
.D(\blk00000001/sig00000135 ),
.Q(\blk00000001/sig000000d8 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk000001bc (
.C(clk),
.D(\blk00000001/sig000000d9 ),
.Q(\blk00000001/sig000000ea )
);
SRL16 #(
.INIT ( 16'h0000 ))
\blk00000001/blk000001bb (
.A0(\blk00000001/sig0000004b ),
.A1(\blk00000001/sig0000004b ),
.A2(\blk00000001/sig0000004b ),
.A3(\blk00000001/sig0000004b ),
.CLK(clk),
.D(\blk00000001/sig00000140 ),
.Q(\blk00000001/sig000000d9 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk000001ba (
.C(clk),
.D(\blk00000001/sig000000e2 ),
.Q(\blk00000001/sig000000f3 )
);
SRL16 #(
.INIT ( 16'h0000 ))
\blk00000001/blk000001b9 (
.A0(\blk00000001/sig0000004b ),
.A1(\blk00000001/sig0000004b ),
.A2(\blk00000001/sig0000004b ),
.A3(\blk00000001/sig0000004b ),
.CLK(clk),
.D(\blk00000001/sig00000146 ),
.Q(\blk00000001/sig000000e2 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk000001b8 (
.C(clk),
.D(\blk00000001/sig000000e3 ),
.Q(\blk00000001/sig000000f4 )
);
SRL16 #(
.INIT ( 16'h0000 ))
\blk00000001/blk000001b7 (
.A0(\blk00000001/sig0000004b ),
.A1(\blk00000001/sig0000004b ),
.A2(\blk00000001/sig0000004b ),
.A3(\blk00000001/sig0000004b ),
.CLK(clk),
.D(\blk00000001/sig00000147 ),
.Q(\blk00000001/sig000000e3 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk000001b6 (
.C(clk),
.D(\blk00000001/sig000000e1 ),
.Q(\blk00000001/sig000000f2 )
);
SRL16 #(
.INIT ( 16'h0000 ))
\blk00000001/blk000001b5 (
.A0(\blk00000001/sig0000004b ),
.A1(\blk00000001/sig0000004b ),
.A2(\blk00000001/sig0000004b ),
.A3(\blk00000001/sig0000004b ),
.CLK(clk),
.D(\blk00000001/sig00000145 ),
.Q(\blk00000001/sig000000e1 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk000001b4 (
.C(clk),
.D(\blk00000001/sig000000e4 ),
.Q(\blk00000001/sig000000f5 )
);
SRL16 #(
.INIT ( 16'h0000 ))
\blk00000001/blk000001b3 (
.A0(\blk00000001/sig0000004b ),
.A1(\blk00000001/sig0000004b ),
.A2(\blk00000001/sig0000004b ),
.A3(\blk00000001/sig0000004b ),
.CLK(clk),
.D(\blk00000001/sig00000148 ),
.Q(\blk00000001/sig000000e4 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk000001b2 (
.C(clk),
.D(\blk00000001/sig000000e5 ),
.Q(\blk00000001/sig000000f6 )
);
SRL16 #(
.INIT ( 16'h0000 ))
\blk00000001/blk000001b1 (
.A0(\blk00000001/sig0000004b ),
.A1(\blk00000001/sig0000004b ),
.A2(\blk00000001/sig0000004b ),
.A3(\blk00000001/sig0000004b ),
.CLK(clk),
.D(\blk00000001/sig00000149 ),
.Q(\blk00000001/sig000000e5 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk000001b0 (
.C(clk),
.D(\blk00000001/sig000000e7 ),
.Q(\blk00000001/sig000000f8 )
);
SRL16 #(
.INIT ( 16'h0000 ))
\blk00000001/blk000001af (
.A0(\blk00000001/sig0000004b ),
.A1(\blk00000001/sig0000004b ),
.A2(\blk00000001/sig0000004b ),
.A3(\blk00000001/sig0000004b ),
.CLK(clk),
.D(\blk00000001/sig0000014b ),
.Q(\blk00000001/sig000000e7 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk000001ae (
.C(clk),
.D(\blk00000001/sig000000e8 ),
.Q(\blk00000001/sig000000f9 )
);
SRL16 #(
.INIT ( 16'h0000 ))
\blk00000001/blk000001ad (
.A0(\blk00000001/sig0000004b ),
.A1(\blk00000001/sig0000004b ),
.A2(\blk00000001/sig0000004b ),
.A3(\blk00000001/sig0000004b ),
.CLK(clk),
.D(\blk00000001/sig0000014c ),
.Q(\blk00000001/sig000000e8 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk000001ac (
.C(clk),
.D(\blk00000001/sig000000e6 ),
.Q(\blk00000001/sig000000f7 )
);
SRL16 #(
.INIT ( 16'h0000 ))
\blk00000001/blk000001ab (
.A0(\blk00000001/sig0000004b ),
.A1(\blk00000001/sig0000004b ),
.A2(\blk00000001/sig0000004b ),
.A3(\blk00000001/sig0000004b ),
.CLK(clk),
.D(\blk00000001/sig0000014a ),
.Q(\blk00000001/sig000000e6 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk000001aa (
.C(clk),
.D(\blk00000001/sig000000da ),
.Q(\blk00000001/sig000000eb )
);
SRL16 #(
.INIT ( 16'h0000 ))
\blk00000001/blk000001a9 (
.A0(\blk00000001/sig0000004b ),
.A1(\blk00000001/sig0000004b ),
.A2(\blk00000001/sig0000004b ),
.A3(\blk00000001/sig0000004b ),
.CLK(clk),
.D(\blk00000001/sig00000136 ),
.Q(\blk00000001/sig000000da )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk000001a8 (
.C(clk),
.D(\blk00000001/sig000000db ),
.Q(\blk00000001/sig000000ec )
);
SRL16 #(
.INIT ( 16'h0000 ))
\blk00000001/blk000001a7 (
.A0(\blk00000001/sig0000004b ),
.A1(\blk00000001/sig0000004b ),
.A2(\blk00000001/sig0000004b ),
.A3(\blk00000001/sig0000004b ),
.CLK(clk),
.D(\blk00000001/sig00000137 ),
.Q(\blk00000001/sig000000db )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk000001a6 (
.C(clk),
.D(\blk00000001/sig000000dd ),
.Q(\blk00000001/sig000000ee )
);
SRL16 #(
.INIT ( 16'h0000 ))
\blk00000001/blk000001a5 (
.A0(\blk00000001/sig0000004b ),
.A1(\blk00000001/sig0000004b ),
.A2(\blk00000001/sig0000004b ),
.A3(\blk00000001/sig0000004b ),
.CLK(clk),
.D(\blk00000001/sig00000139 ),
.Q(\blk00000001/sig000000dd )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk000001a4 (
.C(clk),
.D(\blk00000001/sig000000de ),
.Q(\blk00000001/sig000000ef )
);
SRL16 #(
.INIT ( 16'h0000 ))
\blk00000001/blk000001a3 (
.A0(\blk00000001/sig0000004b ),
.A1(\blk00000001/sig0000004b ),
.A2(\blk00000001/sig0000004b ),
.A3(\blk00000001/sig0000004b ),
.CLK(clk),
.D(\blk00000001/sig0000013a ),
.Q(\blk00000001/sig000000de )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk000001a2 (
.C(clk),
.D(\blk00000001/sig000000dc ),
.Q(\blk00000001/sig000000ed )
);
SRL16 #(
.INIT ( 16'h0000 ))
\blk00000001/blk000001a1 (
.A0(\blk00000001/sig0000004b ),
.A1(\blk00000001/sig0000004b ),
.A2(\blk00000001/sig0000004b ),
.A3(\blk00000001/sig0000004b ),
.CLK(clk),
.D(\blk00000001/sig00000138 ),
.Q(\blk00000001/sig000000dc )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk000001a0 (
.C(clk),
.D(\blk00000001/sig000000e0 ),
.Q(\blk00000001/sig000000f1 )
);
SRL16 #(
.INIT ( 16'h0000 ))
\blk00000001/blk0000019f (
.A0(\blk00000001/sig0000004b ),
.A1(\blk00000001/sig0000004b ),
.A2(\blk00000001/sig0000004b ),
.A3(\blk00000001/sig0000004b ),
.CLK(clk),
.D(\blk00000001/sig0000013c ),
.Q(\blk00000001/sig000000e0 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk0000019e (
.C(clk),
.D(\blk00000001/sig00000043 ),
.Q(p[24])
);
SRL16 #(
.INIT ( 16'h0000 ))
\blk00000001/blk0000019d (
.A0(\blk00000001/sig0000004b ),
.A1(\blk00000001/sig0000004b ),
.A2(\blk00000001/sig0000004b ),
.A3(\blk00000001/sig0000004b ),
.CLK(clk),
.D(\blk00000001/sig00000202 ),
.Q(\blk00000001/sig00000043 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk0000019c (
.C(clk),
.D(\blk00000001/sig000000df ),
.Q(\blk00000001/sig000000f0 )
);
SRL16 #(
.INIT ( 16'h0000 ))
\blk00000001/blk0000019b (
.A0(\blk00000001/sig0000004b ),
.A1(\blk00000001/sig0000004b ),
.A2(\blk00000001/sig0000004b ),
.A3(\blk00000001/sig0000004b ),
.CLK(clk),
.D(\blk00000001/sig0000013b ),
.Q(\blk00000001/sig000000df )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk0000019a (
.C(clk),
.D(\blk00000001/sig00000041 ),
.Q(p[22])
);
SRL16 #(
.INIT ( 16'h0000 ))
\blk00000001/blk00000199 (
.A0(\blk00000001/sig0000004b ),
.A1(\blk00000001/sig0000004b ),
.A2(\blk00000001/sig0000004b ),
.A3(\blk00000001/sig0000004b ),
.CLK(clk),
.D(\blk00000001/sig00000200 ),
.Q(\blk00000001/sig00000041 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000198 (
.C(clk),
.D(\blk00000001/sig00000040 ),
.Q(p[21])
);
SRL16 #(
.INIT ( 16'h0000 ))
\blk00000001/blk00000197 (
.A0(\blk00000001/sig0000004b ),
.A1(\blk00000001/sig0000004b ),
.A2(\blk00000001/sig0000004b ),
.A3(\blk00000001/sig0000004b ),
.CLK(clk),
.D(\blk00000001/sig000001fe ),
.Q(\blk00000001/sig00000040 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000196 (
.C(clk),
.D(\blk00000001/sig00000042 ),
.Q(p[23])
);
SRL16 #(
.INIT ( 16'h0000 ))
\blk00000001/blk00000195 (
.A0(\blk00000001/sig0000004b ),
.A1(\blk00000001/sig0000004b ),
.A2(\blk00000001/sig0000004b ),
.A3(\blk00000001/sig0000004b ),
.CLK(clk),
.D(\blk00000001/sig00000201 ),
.Q(\blk00000001/sig00000042 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000194 (
.C(clk),
.D(\blk00000001/sig0000003f ),
.Q(p[20])
);
SRL16 #(
.INIT ( 16'h0000 ))
\blk00000001/blk00000193 (
.A0(\blk00000001/sig0000004b ),
.A1(\blk00000001/sig0000004b ),
.A2(\blk00000001/sig0000004b ),
.A3(\blk00000001/sig0000004b ),
.CLK(clk),
.D(\blk00000001/sig000001fd ),
.Q(\blk00000001/sig0000003f )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000192 (
.C(clk),
.D(\blk00000001/sig0000003d ),
.Q(p[19])
);
SRL16 #(
.INIT ( 16'h0000 ))
\blk00000001/blk00000191 (
.A0(\blk00000001/sig0000004b ),
.A1(\blk00000001/sig0000004b ),
.A2(\blk00000001/sig0000004b ),
.A3(\blk00000001/sig0000004b ),
.CLK(clk),
.D(\blk00000001/sig000001fc ),
.Q(\blk00000001/sig0000003d )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000190 (
.C(clk),
.D(\blk00000001/sig0000003b ),
.Q(p[17])
);
SRL16 #(
.INIT ( 16'h0000 ))
\blk00000001/blk0000018f (
.A0(\blk00000001/sig0000004b ),
.A1(\blk00000001/sig0000004b ),
.A2(\blk00000001/sig0000004b ),
.A3(\blk00000001/sig0000004b ),
.CLK(clk),
.D(\blk00000001/sig000001e6 ),
.Q(\blk00000001/sig0000003b )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk0000018e (
.C(clk),
.D(\blk00000001/sig0000003a ),
.Q(p[16])
);
SRL16 #(
.INIT ( 16'h0000 ))
\blk00000001/blk0000018d (
.A0(\blk00000001/sig0000004b ),
.A1(\blk00000001/sig0000004c ),
.A2(\blk00000001/sig0000004b ),
.A3(\blk00000001/sig0000004b ),
.CLK(clk),
.D(\blk00000001/sig00000101 ),
.Q(\blk00000001/sig0000003a )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk0000018c (
.C(clk),
.D(\blk00000001/sig0000003c ),
.Q(p[18])
);
SRL16 #(
.INIT ( 16'h0000 ))
\blk00000001/blk0000018b (
.A0(\blk00000001/sig0000004b ),
.A1(\blk00000001/sig0000004b ),
.A2(\blk00000001/sig0000004b ),
.A3(\blk00000001/sig0000004b ),
.CLK(clk),
.D(\blk00000001/sig000001f1 ),
.Q(\blk00000001/sig0000003c )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk0000018a (
.C(clk),
.D(\blk00000001/sig00000039 ),
.Q(p[15])
);
SRL16 #(
.INIT ( 16'h0000 ))
\blk00000001/blk00000189 (
.A0(\blk00000001/sig0000004b ),
.A1(\blk00000001/sig0000004c ),
.A2(\blk00000001/sig0000004b ),
.A3(\blk00000001/sig0000004b ),
.CLK(clk),
.D(\blk00000001/sig00000100 ),
.Q(\blk00000001/sig00000039 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000188 (
.C(clk),
.D(\blk00000001/sig00000038 ),
.Q(p[14])
);
SRL16 #(
.INIT ( 16'h0000 ))
\blk00000001/blk00000187 (
.A0(\blk00000001/sig0000004b ),
.A1(\blk00000001/sig0000004c ),
.A2(\blk00000001/sig0000004b ),
.A3(\blk00000001/sig0000004b ),
.CLK(clk),
.D(\blk00000001/sig000000ff ),
.Q(\blk00000001/sig00000038 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000186 (
.C(clk),
.D(\blk00000001/sig00000036 ),
.Q(p[12])
);
SRL16 #(
.INIT ( 16'h0000 ))
\blk00000001/blk00000185 (
.A0(\blk00000001/sig0000004b ),
.A1(\blk00000001/sig0000004c ),
.A2(\blk00000001/sig0000004b ),
.A3(\blk00000001/sig0000004b ),
.CLK(clk),
.D(\blk00000001/sig000000fd ),
.Q(\blk00000001/sig00000036 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000184 (
.C(clk),
.D(\blk00000001/sig00000035 ),
.Q(p[11])
);
SRL16 #(
.INIT ( 16'h0000 ))
\blk00000001/blk00000183 (
.A0(\blk00000001/sig0000004b ),
.A1(\blk00000001/sig0000004c ),
.A2(\blk00000001/sig0000004b ),
.A3(\blk00000001/sig0000004b ),
.CLK(clk),
.D(\blk00000001/sig000000fc ),
.Q(\blk00000001/sig00000035 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000182 (
.C(clk),
.D(\blk00000001/sig00000037 ),
.Q(p[13])
);
SRL16 #(
.INIT ( 16'h0000 ))
\blk00000001/blk00000181 (
.A0(\blk00000001/sig0000004b ),
.A1(\blk00000001/sig0000004c ),
.A2(\blk00000001/sig0000004b ),
.A3(\blk00000001/sig0000004b ),
.CLK(clk),
.D(\blk00000001/sig000000fe ),
.Q(\blk00000001/sig00000037 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000180 (
.C(clk),
.D(\blk00000001/sig00000034 ),
.Q(p[10])
);
SRL16 #(
.INIT ( 16'h0000 ))
\blk00000001/blk0000017f (
.A0(\blk00000001/sig0000004b ),
.A1(\blk00000001/sig0000004c ),
.A2(\blk00000001/sig0000004b ),
.A3(\blk00000001/sig0000004b ),
.CLK(clk),
.D(\blk00000001/sig000000fb ),
.Q(\blk00000001/sig00000034 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk0000017e (
.C(clk),
.D(\blk00000001/sig0000004a ),
.Q(p[9])
);
SRL16 #(
.INIT ( 16'h0000 ))
\blk00000001/blk0000017d (
.A0(\blk00000001/sig0000004b ),
.A1(\blk00000001/sig0000004c ),
.A2(\blk00000001/sig0000004b ),
.A3(\blk00000001/sig0000004b ),
.CLK(clk),
.D(\blk00000001/sig0000011c ),
.Q(\blk00000001/sig0000004a )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk0000017c (
.C(clk),
.D(\blk00000001/sig00000048 ),
.Q(p[7])
);
SRL16 #(
.INIT ( 16'h0000 ))
\blk00000001/blk0000017b (
.A0(\blk00000001/sig0000004b ),
.A1(\blk00000001/sig0000004c ),
.A2(\blk00000001/sig0000004b ),
.A3(\blk00000001/sig0000004b ),
.CLK(clk),
.D(\blk00000001/sig0000011a ),
.Q(\blk00000001/sig00000048 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk0000017a (
.C(clk),
.D(\blk00000001/sig00000047 ),
.Q(p[6])
);
SRL16 #(
.INIT ( 16'h0000 ))
\blk00000001/blk00000179 (
.A0(\blk00000001/sig0000004b ),
.A1(\blk00000001/sig0000004c ),
.A2(\blk00000001/sig0000004b ),
.A3(\blk00000001/sig0000004b ),
.CLK(clk),
.D(\blk00000001/sig00000119 ),
.Q(\blk00000001/sig00000047 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000178 (
.C(clk),
.D(\blk00000001/sig00000049 ),
.Q(p[8])
);
SRL16 #(
.INIT ( 16'h0000 ))
\blk00000001/blk00000177 (
.A0(\blk00000001/sig0000004b ),
.A1(\blk00000001/sig0000004c ),
.A2(\blk00000001/sig0000004b ),
.A3(\blk00000001/sig0000004b ),
.CLK(clk),
.D(\blk00000001/sig0000011b ),
.Q(\blk00000001/sig00000049 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000176 (
.C(clk),
.D(\blk00000001/sig00000045 ),
.Q(p[4])
);
SRL16 #(
.INIT ( 16'h0000 ))
\blk00000001/blk00000175 (
.A0(\blk00000001/sig0000004b ),
.A1(\blk00000001/sig0000004c ),
.A2(\blk00000001/sig0000004b ),
.A3(\blk00000001/sig0000004b ),
.CLK(clk),
.D(\blk00000001/sig00000117 ),
.Q(\blk00000001/sig00000045 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000174 (
.C(clk),
.D(\blk00000001/sig00000044 ),
.Q(p[3])
);
SRL16 #(
.INIT ( 16'h0000 ))
\blk00000001/blk00000173 (
.A0(\blk00000001/sig0000004b ),
.A1(\blk00000001/sig0000004c ),
.A2(\blk00000001/sig0000004b ),
.A3(\blk00000001/sig0000004b ),
.CLK(clk),
.D(\blk00000001/sig00000116 ),
.Q(\blk00000001/sig00000044 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000172 (
.C(clk),
.D(\blk00000001/sig00000046 ),
.Q(p[5])
);
SRL16 #(
.INIT ( 16'h0000 ))
\blk00000001/blk00000171 (
.A0(\blk00000001/sig0000004b ),
.A1(\blk00000001/sig0000004c ),
.A2(\blk00000001/sig0000004b ),
.A3(\blk00000001/sig0000004b ),
.CLK(clk),
.D(\blk00000001/sig00000118 ),
.Q(\blk00000001/sig00000046 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000170 (
.C(clk),
.D(\blk00000001/sig00000033 ),
.Q(p[1])
);
SRL16 #(
.INIT ( 16'h0000 ))
\blk00000001/blk0000016f (
.A0(\blk00000001/sig0000004b ),
.A1(\blk00000001/sig0000004c ),
.A2(\blk00000001/sig0000004b ),
.A3(\blk00000001/sig0000004b ),
.CLK(clk),
.D(\blk00000001/sig00000105 ),
.Q(\blk00000001/sig00000033 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk0000016e (
.C(clk),
.D(\blk00000001/sig00000032 ),
.Q(p[0])
);
SRL16 #(
.INIT ( 16'h0000 ))
\blk00000001/blk0000016d (
.A0(\blk00000001/sig0000004b ),
.A1(\blk00000001/sig0000004c ),
.A2(\blk00000001/sig0000004b ),
.A3(\blk00000001/sig0000004b ),
.CLK(clk),
.D(\blk00000001/sig000000fa ),
.Q(\blk00000001/sig00000032 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk0000016c (
.C(clk),
.D(\blk00000001/sig0000003e ),
.Q(p[2])
);
SRL16 #(
.INIT ( 16'h0000 ))
\blk00000001/blk0000016b (
.A0(\blk00000001/sig0000004b ),
.A1(\blk00000001/sig0000004c ),
.A2(\blk00000001/sig0000004b ),
.A3(\blk00000001/sig0000004b ),
.CLK(clk),
.D(\blk00000001/sig00000110 ),
.Q(\blk00000001/sig0000003e )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk0000016a (
.C(clk),
.D(\blk00000001/sig00000102 ),
.Q(\blk00000001/sig0000015b )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000169 (
.C(clk),
.D(\blk00000001/sig00000103 ),
.Q(\blk00000001/sig0000015c )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000168 (
.C(clk),
.D(\blk00000001/sig00000104 ),
.Q(\blk00000001/sig0000015d )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000167 (
.C(clk),
.D(\blk00000001/sig00000106 ),
.Q(\blk00000001/sig0000015e )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000166 (
.C(clk),
.D(\blk00000001/sig00000107 ),
.Q(\blk00000001/sig0000015f )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000165 (
.C(clk),
.D(\blk00000001/sig00000108 ),
.Q(\blk00000001/sig00000160 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000164 (
.C(clk),
.D(\blk00000001/sig00000109 ),
.Q(\blk00000001/sig00000161 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000163 (
.C(clk),
.D(\blk00000001/sig0000010a ),
.Q(\blk00000001/sig00000162 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000162 (
.C(clk),
.D(\blk00000001/sig0000010b ),
.Q(\blk00000001/sig00000163 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000161 (
.C(clk),
.D(\blk00000001/sig0000010c ),
.Q(\blk00000001/sig00000164 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000160 (
.C(clk),
.D(\blk00000001/sig0000010d ),
.Q(\blk00000001/sig00000165 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk0000015f (
.C(clk),
.D(\blk00000001/sig0000010e ),
.Q(\blk00000001/sig00000166 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk0000015e (
.C(clk),
.D(\blk00000001/sig0000010f ),
.Q(\blk00000001/sig00000167 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk0000015d (
.C(clk),
.D(\blk00000001/sig00000111 ),
.Q(\blk00000001/sig00000168 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk0000015c (
.C(clk),
.D(\blk00000001/sig00000112 ),
.Q(\blk00000001/sig00000169 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk0000015b (
.C(clk),
.D(\blk00000001/sig00000113 ),
.Q(\blk00000001/sig0000016a )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk0000015a (
.C(clk),
.D(\blk00000001/sig00000114 ),
.Q(\blk00000001/sig0000016b )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000159 (
.C(clk),
.D(\blk00000001/sig00000115 ),
.Q(\blk00000001/sig0000016c )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000158 (
.C(clk),
.D(\blk00000001/sig0000011d ),
.Q(\blk00000001/sig0000016d )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000157 (
.C(clk),
.D(\blk00000001/sig00000128 ),
.Q(\blk00000001/sig0000016e )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000156 (
.C(clk),
.D(\blk00000001/sig0000012d ),
.Q(\blk00000001/sig00000179 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000155 (
.C(clk),
.D(\blk00000001/sig0000012e ),
.Q(\blk00000001/sig0000017e )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000154 (
.C(clk),
.D(\blk00000001/sig0000012f ),
.Q(\blk00000001/sig0000017f )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000153 (
.C(clk),
.D(\blk00000001/sig00000130 ),
.Q(\blk00000001/sig00000180 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000152 (
.C(clk),
.D(\blk00000001/sig00000131 ),
.Q(\blk00000001/sig00000181 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000151 (
.C(clk),
.D(\blk00000001/sig00000132 ),
.Q(\blk00000001/sig00000182 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000150 (
.C(clk),
.D(\blk00000001/sig00000133 ),
.Q(\blk00000001/sig00000183 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk0000014f (
.C(clk),
.D(\blk00000001/sig00000134 ),
.Q(\blk00000001/sig00000184 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk0000014e (
.C(clk),
.D(\blk00000001/sig0000011e ),
.Q(\blk00000001/sig0000016f )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk0000014d (
.C(clk),
.D(\blk00000001/sig0000011f ),
.Q(\blk00000001/sig00000170 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk0000014c (
.C(clk),
.D(\blk00000001/sig00000120 ),
.Q(\blk00000001/sig00000171 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk0000014b (
.C(clk),
.D(\blk00000001/sig00000121 ),
.Q(\blk00000001/sig00000172 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk0000014a (
.C(clk),
.D(\blk00000001/sig00000122 ),
.Q(\blk00000001/sig00000173 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000149 (
.C(clk),
.D(\blk00000001/sig00000123 ),
.Q(\blk00000001/sig00000174 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000148 (
.C(clk),
.D(\blk00000001/sig00000124 ),
.Q(\blk00000001/sig00000175 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000147 (
.C(clk),
.D(\blk00000001/sig00000125 ),
.Q(\blk00000001/sig00000176 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000146 (
.C(clk),
.D(\blk00000001/sig00000126 ),
.Q(\blk00000001/sig00000177 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000145 (
.C(clk),
.D(\blk00000001/sig00000127 ),
.Q(\blk00000001/sig00000178 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000144 (
.C(clk),
.D(\blk00000001/sig00000129 ),
.Q(\blk00000001/sig0000017a )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000143 (
.C(clk),
.D(\blk00000001/sig0000012a ),
.Q(\blk00000001/sig0000017b )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000142 (
.C(clk),
.D(\blk00000001/sig0000012b ),
.Q(\blk00000001/sig0000017c )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000141 (
.C(clk),
.D(\blk00000001/sig0000012c ),
.Q(\blk00000001/sig0000017d )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000140 (
.C(clk),
.D(\blk00000001/sig0000013d ),
.Q(\blk00000001/sig00000185 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk0000013f (
.C(clk),
.D(\blk00000001/sig0000013e ),
.Q(\blk00000001/sig00000186 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk0000013e (
.C(clk),
.D(\blk00000001/sig0000013f ),
.Q(\blk00000001/sig00000187 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk0000013d (
.C(clk),
.D(\blk00000001/sig00000141 ),
.Q(\blk00000001/sig00000188 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk0000013c (
.C(clk),
.D(\blk00000001/sig00000142 ),
.Q(\blk00000001/sig00000189 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk0000013b (
.C(clk),
.D(\blk00000001/sig00000143 ),
.Q(\blk00000001/sig0000018a )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk0000013a (
.C(clk),
.D(\blk00000001/sig00000144 ),
.Q(\blk00000001/sig0000018b )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000139 (
.C(clk),
.D(\blk00000001/sig0000014d ),
.Q(\blk00000001/sig0000018c )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000138 (
.C(clk),
.D(\blk00000001/sig00000152 ),
.Q(\blk00000001/sig0000018d )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000137 (
.C(clk),
.D(\blk00000001/sig00000153 ),
.Q(\blk00000001/sig00000192 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000136 (
.C(clk),
.D(\blk00000001/sig00000154 ),
.Q(\blk00000001/sig00000193 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000135 (
.C(clk),
.D(\blk00000001/sig00000155 ),
.Q(\blk00000001/sig00000194 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000134 (
.C(clk),
.D(\blk00000001/sig00000156 ),
.Q(\blk00000001/sig00000195 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000133 (
.C(clk),
.D(\blk00000001/sig00000157 ),
.Q(\blk00000001/sig00000196 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000132 (
.C(clk),
.D(\blk00000001/sig00000158 ),
.Q(\blk00000001/sig00000197 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000131 (
.C(clk),
.D(\blk00000001/sig00000159 ),
.Q(\blk00000001/sig00000198 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000130 (
.C(clk),
.D(\blk00000001/sig0000015a ),
.Q(\blk00000001/sig00000199 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk0000012f (
.C(clk),
.D(\blk00000001/sig0000014e ),
.Q(\blk00000001/sig0000018e )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk0000012e (
.C(clk),
.D(\blk00000001/sig0000014f ),
.Q(\blk00000001/sig0000018f )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk0000012d (
.C(clk),
.D(\blk00000001/sig00000150 ),
.Q(\blk00000001/sig00000190 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk0000012c (
.C(clk),
.D(\blk00000001/sig00000151 ),
.Q(\blk00000001/sig00000191 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk0000012b (
.C(clk),
.D(\blk00000001/sig000001ca ),
.Q(\blk00000001/sig000001d8 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk0000012a (
.C(clk),
.D(\blk00000001/sig000001cf ),
.Q(\blk00000001/sig000001d9 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000129 (
.C(clk),
.D(\blk00000001/sig000001d0 ),
.Q(\blk00000001/sig000001de )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000128 (
.C(clk),
.D(\blk00000001/sig000001d1 ),
.Q(\blk00000001/sig000001df )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000127 (
.C(clk),
.D(\blk00000001/sig000001d2 ),
.Q(\blk00000001/sig000001e0 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000126 (
.C(clk),
.D(\blk00000001/sig000001d3 ),
.Q(\blk00000001/sig000001e1 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000125 (
.C(clk),
.D(\blk00000001/sig000001d4 ),
.Q(\blk00000001/sig000001e2 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000124 (
.C(clk),
.D(\blk00000001/sig000001d5 ),
.Q(\blk00000001/sig000001e3 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000123 (
.C(clk),
.D(\blk00000001/sig000001d6 ),
.Q(\blk00000001/sig000001e4 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000122 (
.C(clk),
.D(\blk00000001/sig000001d7 ),
.Q(\blk00000001/sig000001e5 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000121 (
.C(clk),
.D(\blk00000001/sig000001cb ),
.Q(\blk00000001/sig000001da )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000120 (
.C(clk),
.D(\blk00000001/sig000001cc ),
.Q(\blk00000001/sig000001db )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk0000011f (
.C(clk),
.D(\blk00000001/sig000001cd ),
.Q(\blk00000001/sig000001dc )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk0000011e (
.C(clk),
.D(\blk00000001/sig000001ce ),
.Q(\blk00000001/sig000001dd )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk0000011d (
.C(clk),
.D(\blk00000001/sig0000019a ),
.Q(\blk00000001/sig000001b2 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk0000011c (
.C(clk),
.D(\blk00000001/sig000001a5 ),
.Q(\blk00000001/sig000001b3 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk0000011b (
.C(clk),
.D(\blk00000001/sig000001aa ),
.Q(\blk00000001/sig000001be )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk0000011a (
.C(clk),
.D(\blk00000001/sig000001ab ),
.Q(\blk00000001/sig000001c3 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000119 (
.C(clk),
.D(\blk00000001/sig000001ac ),
.Q(\blk00000001/sig000001c4 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000118 (
.C(clk),
.D(\blk00000001/sig000001ad ),
.Q(\blk00000001/sig000001c5 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000117 (
.C(clk),
.D(\blk00000001/sig000001ae ),
.Q(\blk00000001/sig000001c6 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000116 (
.C(clk),
.D(\blk00000001/sig000001af ),
.Q(\blk00000001/sig000001c7 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000115 (
.C(clk),
.D(\blk00000001/sig000001b0 ),
.Q(\blk00000001/sig000001c8 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000114 (
.C(clk),
.D(\blk00000001/sig000001b1 ),
.Q(\blk00000001/sig000001c9 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000113 (
.C(clk),
.D(\blk00000001/sig0000019b ),
.Q(\blk00000001/sig000001b4 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000112 (
.C(clk),
.D(\blk00000001/sig0000019c ),
.Q(\blk00000001/sig000001b5 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000111 (
.C(clk),
.D(\blk00000001/sig0000019d ),
.Q(\blk00000001/sig000001b6 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000110 (
.C(clk),
.D(\blk00000001/sig0000019e ),
.Q(\blk00000001/sig000001b7 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk0000010f (
.C(clk),
.D(\blk00000001/sig0000019f ),
.Q(\blk00000001/sig000001b8 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk0000010e (
.C(clk),
.D(\blk00000001/sig000001a0 ),
.Q(\blk00000001/sig000001b9 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk0000010d (
.C(clk),
.D(\blk00000001/sig000001a1 ),
.Q(\blk00000001/sig000001ba )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk0000010c (
.C(clk),
.D(\blk00000001/sig000001a2 ),
.Q(\blk00000001/sig000001bb )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk0000010b (
.C(clk),
.D(\blk00000001/sig000001a3 ),
.Q(\blk00000001/sig000001bc )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk0000010a (
.C(clk),
.D(\blk00000001/sig000001a4 ),
.Q(\blk00000001/sig000001bd )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000109 (
.C(clk),
.D(\blk00000001/sig000001a6 ),
.Q(\blk00000001/sig000001bf )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000108 (
.C(clk),
.D(\blk00000001/sig000001a7 ),
.Q(\blk00000001/sig000001c0 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000107 (
.C(clk),
.D(\blk00000001/sig000001a8 ),
.Q(\blk00000001/sig000001c1 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000106 (
.C(clk),
.D(\blk00000001/sig000001a9 ),
.Q(\blk00000001/sig000001c2 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000105 (
.C(clk),
.D(\blk00000001/sig00000203 ),
.Q(\blk00000001/sig0000021a )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000104 (
.C(clk),
.D(\blk00000001/sig00000204 ),
.Q(\blk00000001/sig0000021b )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000103 (
.C(clk),
.D(\blk00000001/sig000001e7 ),
.Q(\blk00000001/sig00000205 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000102 (
.C(clk),
.D(\blk00000001/sig000001e8 ),
.Q(\blk00000001/sig00000206 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000101 (
.C(clk),
.D(\blk00000001/sig000001e9 ),
.Q(\blk00000001/sig00000207 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000100 (
.C(clk),
.D(\blk00000001/sig000001ea ),
.Q(\blk00000001/sig00000208 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk000000ff (
.C(clk),
.D(\blk00000001/sig000001eb ),
.Q(\blk00000001/sig00000209 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk000000fe (
.C(clk),
.D(\blk00000001/sig000001ec ),
.Q(\blk00000001/sig0000020a )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk000000fd (
.C(clk),
.D(\blk00000001/sig000001ed ),
.Q(\blk00000001/sig0000020b )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk000000fc (
.C(clk),
.D(\blk00000001/sig000001ee ),
.Q(\blk00000001/sig0000020c )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk000000fb (
.C(clk),
.D(\blk00000001/sig000001ef ),
.Q(\blk00000001/sig0000020d )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk000000fa (
.C(clk),
.D(\blk00000001/sig000001f0 ),
.Q(\blk00000001/sig0000020e )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk000000f9 (
.C(clk),
.D(\blk00000001/sig000001f2 ),
.Q(\blk00000001/sig0000020f )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk000000f8 (
.C(clk),
.D(\blk00000001/sig000001f3 ),
.Q(\blk00000001/sig00000210 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk000000f7 (
.C(clk),
.D(\blk00000001/sig000001f4 ),
.Q(\blk00000001/sig00000211 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk000000f6 (
.C(clk),
.D(\blk00000001/sig000001f5 ),
.Q(\blk00000001/sig00000212 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk000000f5 (
.C(clk),
.D(\blk00000001/sig000001f6 ),
.Q(\blk00000001/sig00000213 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk000000f4 (
.C(clk),
.D(\blk00000001/sig000001f7 ),
.Q(\blk00000001/sig00000214 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk000000f3 (
.C(clk),
.D(\blk00000001/sig000001f8 ),
.Q(\blk00000001/sig00000215 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk000000f2 (
.C(clk),
.D(\blk00000001/sig000001f9 ),
.Q(\blk00000001/sig00000216 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk000000f1 (
.C(clk),
.D(\blk00000001/sig000001fa ),
.Q(\blk00000001/sig00000217 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk000000f0 (
.C(clk),
.D(\blk00000001/sig000001fb ),
.Q(\blk00000001/sig00000218 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk000000ef (
.C(clk),
.D(\blk00000001/sig000001ff ),
.Q(\blk00000001/sig00000219 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk000000ee (
.I0(\blk00000001/sig00000185 ),
.I1(\blk00000001/sig0000018c ),
.O(\blk00000001/sig00000089 )
);
MUXCY \blk00000001/blk000000ed (
.CI(\blk00000001/sig0000004b ),
.DI(\blk00000001/sig00000185 ),
.S(\blk00000001/sig00000089 ),
.O(\blk00000001/sig0000007c )
);
XORCY \blk00000001/blk000000ec (
.CI(\blk00000001/sig0000004b ),
.LI(\blk00000001/sig00000089 ),
.O(\blk00000001/sig000001ca )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk000000eb (
.I0(\blk00000001/sig00000186 ),
.I1(\blk00000001/sig0000018d ),
.O(\blk00000001/sig0000008e )
);
MUXCY \blk00000001/blk000000ea (
.CI(\blk00000001/sig0000007c ),
.DI(\blk00000001/sig00000186 ),
.S(\blk00000001/sig0000008e ),
.O(\blk00000001/sig00000080 )
);
XORCY \blk00000001/blk000000e9 (
.CI(\blk00000001/sig0000007c ),
.LI(\blk00000001/sig0000008e ),
.O(\blk00000001/sig000001cf )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk000000e8 (
.I0(\blk00000001/sig00000187 ),
.I1(\blk00000001/sig00000192 ),
.O(\blk00000001/sig0000008f )
);
MUXCY \blk00000001/blk000000e7 (
.CI(\blk00000001/sig00000080 ),
.DI(\blk00000001/sig00000187 ),
.S(\blk00000001/sig0000008f ),
.O(\blk00000001/sig00000081 )
);
XORCY \blk00000001/blk000000e6 (
.CI(\blk00000001/sig00000080 ),
.LI(\blk00000001/sig0000008f ),
.O(\blk00000001/sig000001d0 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk000000e5 (
.I0(\blk00000001/sig00000188 ),
.I1(\blk00000001/sig00000193 ),
.O(\blk00000001/sig00000090 )
);
MUXCY \blk00000001/blk000000e4 (
.CI(\blk00000001/sig00000081 ),
.DI(\blk00000001/sig00000188 ),
.S(\blk00000001/sig00000090 ),
.O(\blk00000001/sig00000082 )
);
XORCY \blk00000001/blk000000e3 (
.CI(\blk00000001/sig00000081 ),
.LI(\blk00000001/sig00000090 ),
.O(\blk00000001/sig000001d1 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk000000e2 (
.I0(\blk00000001/sig00000189 ),
.I1(\blk00000001/sig00000194 ),
.O(\blk00000001/sig00000091 )
);
MUXCY \blk00000001/blk000000e1 (
.CI(\blk00000001/sig00000082 ),
.DI(\blk00000001/sig00000189 ),
.S(\blk00000001/sig00000091 ),
.O(\blk00000001/sig00000083 )
);
XORCY \blk00000001/blk000000e0 (
.CI(\blk00000001/sig00000082 ),
.LI(\blk00000001/sig00000091 ),
.O(\blk00000001/sig000001d2 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk000000df (
.I0(\blk00000001/sig0000018a ),
.I1(\blk00000001/sig00000195 ),
.O(\blk00000001/sig00000092 )
);
MUXCY \blk00000001/blk000000de (
.CI(\blk00000001/sig00000083 ),
.DI(\blk00000001/sig0000018a ),
.S(\blk00000001/sig00000092 ),
.O(\blk00000001/sig00000084 )
);
XORCY \blk00000001/blk000000dd (
.CI(\blk00000001/sig00000083 ),
.LI(\blk00000001/sig00000092 ),
.O(\blk00000001/sig000001d3 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk000000dc (
.I0(\blk00000001/sig0000018b ),
.I1(\blk00000001/sig00000196 ),
.O(\blk00000001/sig00000093 )
);
MUXCY \blk00000001/blk000000db (
.CI(\blk00000001/sig00000084 ),
.DI(\blk00000001/sig0000018b ),
.S(\blk00000001/sig00000093 ),
.O(\blk00000001/sig00000085 )
);
XORCY \blk00000001/blk000000da (
.CI(\blk00000001/sig00000084 ),
.LI(\blk00000001/sig00000093 ),
.O(\blk00000001/sig000001d4 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk000000d9 (
.I0(\blk00000001/sig0000018b ),
.I1(\blk00000001/sig00000197 ),
.O(\blk00000001/sig00000094 )
);
MUXCY \blk00000001/blk000000d8 (
.CI(\blk00000001/sig00000085 ),
.DI(\blk00000001/sig0000018b ),
.S(\blk00000001/sig00000094 ),
.O(\blk00000001/sig00000086 )
);
XORCY \blk00000001/blk000000d7 (
.CI(\blk00000001/sig00000085 ),
.LI(\blk00000001/sig00000094 ),
.O(\blk00000001/sig000001d5 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk000000d6 (
.I0(\blk00000001/sig0000018b ),
.I1(\blk00000001/sig00000198 ),
.O(\blk00000001/sig00000095 )
);
MUXCY \blk00000001/blk000000d5 (
.CI(\blk00000001/sig00000086 ),
.DI(\blk00000001/sig0000018b ),
.S(\blk00000001/sig00000095 ),
.O(\blk00000001/sig00000087 )
);
XORCY \blk00000001/blk000000d4 (
.CI(\blk00000001/sig00000086 ),
.LI(\blk00000001/sig00000095 ),
.O(\blk00000001/sig000001d6 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk000000d3 (
.I0(\blk00000001/sig0000018b ),
.I1(\blk00000001/sig00000199 ),
.O(\blk00000001/sig00000096 )
);
MUXCY \blk00000001/blk000000d2 (
.CI(\blk00000001/sig00000087 ),
.DI(\blk00000001/sig0000018b ),
.S(\blk00000001/sig00000096 ),
.O(\blk00000001/sig00000088 )
);
XORCY \blk00000001/blk000000d1 (
.CI(\blk00000001/sig00000087 ),
.LI(\blk00000001/sig00000096 ),
.O(\blk00000001/sig000001d7 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk000000d0 (
.I0(\blk00000001/sig0000018b ),
.I1(\blk00000001/sig0000018e ),
.O(\blk00000001/sig0000008a )
);
MUXCY \blk00000001/blk000000cf (
.CI(\blk00000001/sig00000088 ),
.DI(\blk00000001/sig0000018b ),
.S(\blk00000001/sig0000008a ),
.O(\blk00000001/sig0000007d )
);
XORCY \blk00000001/blk000000ce (
.CI(\blk00000001/sig00000088 ),
.LI(\blk00000001/sig0000008a ),
.O(\blk00000001/sig000001cb )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk000000cd (
.I0(\blk00000001/sig0000018b ),
.I1(\blk00000001/sig0000018f ),
.O(\blk00000001/sig0000008b )
);
MUXCY \blk00000001/blk000000cc (
.CI(\blk00000001/sig0000007d ),
.DI(\blk00000001/sig0000018b ),
.S(\blk00000001/sig0000008b ),
.O(\blk00000001/sig0000007e )
);
XORCY \blk00000001/blk000000cb (
.CI(\blk00000001/sig0000007d ),
.LI(\blk00000001/sig0000008b ),
.O(\blk00000001/sig000001cc )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk000000ca (
.I0(\blk00000001/sig0000018b ),
.I1(\blk00000001/sig00000190 ),
.O(\blk00000001/sig0000008c )
);
MUXCY \blk00000001/blk000000c9 (
.CI(\blk00000001/sig0000007e ),
.DI(\blk00000001/sig0000018b ),
.S(\blk00000001/sig0000008c ),
.O(\blk00000001/sig0000007f )
);
XORCY \blk00000001/blk000000c8 (
.CI(\blk00000001/sig0000007e ),
.LI(\blk00000001/sig0000008c ),
.O(\blk00000001/sig000001cd )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk000000c7 (
.I0(\blk00000001/sig0000018b ),
.I1(\blk00000001/sig00000191 ),
.O(\blk00000001/sig0000008d )
);
XORCY \blk00000001/blk000000c6 (
.CI(\blk00000001/sig0000007f ),
.LI(\blk00000001/sig0000008d ),
.O(\blk00000001/sig000001ce )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk000000c5 (
.I0(\blk00000001/sig0000015b ),
.I1(\blk00000001/sig0000016d ),
.O(\blk00000001/sig00000064 )
);
MUXCY \blk00000001/blk000000c4 (
.CI(\blk00000001/sig0000004b ),
.DI(\blk00000001/sig0000015b ),
.S(\blk00000001/sig00000064 ),
.O(\blk00000001/sig0000004d )
);
XORCY \blk00000001/blk000000c3 (
.CI(\blk00000001/sig0000004b ),
.LI(\blk00000001/sig00000064 ),
.O(\blk00000001/sig0000019a )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk000000c2 (
.I0(\blk00000001/sig0000015c ),
.I1(\blk00000001/sig0000016e ),
.O(\blk00000001/sig0000006f )
);
MUXCY \blk00000001/blk000000c1 (
.CI(\blk00000001/sig0000004d ),
.DI(\blk00000001/sig0000015c ),
.S(\blk00000001/sig0000006f ),
.O(\blk00000001/sig00000058 )
);
XORCY \blk00000001/blk000000c0 (
.CI(\blk00000001/sig0000004d ),
.LI(\blk00000001/sig0000006f ),
.O(\blk00000001/sig000001a5 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk000000bf (
.I0(\blk00000001/sig0000015d ),
.I1(\blk00000001/sig00000179 ),
.O(\blk00000001/sig00000074 )
);
MUXCY \blk00000001/blk000000be (
.CI(\blk00000001/sig00000058 ),
.DI(\blk00000001/sig0000015d ),
.S(\blk00000001/sig00000074 ),
.O(\blk00000001/sig0000005c )
);
XORCY \blk00000001/blk000000bd (
.CI(\blk00000001/sig00000058 ),
.LI(\blk00000001/sig00000074 ),
.O(\blk00000001/sig000001aa )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk000000bc (
.I0(\blk00000001/sig0000015e ),
.I1(\blk00000001/sig0000017e ),
.O(\blk00000001/sig00000075 )
);
MUXCY \blk00000001/blk000000bb (
.CI(\blk00000001/sig0000005c ),
.DI(\blk00000001/sig0000015e ),
.S(\blk00000001/sig00000075 ),
.O(\blk00000001/sig0000005d )
);
XORCY \blk00000001/blk000000ba (
.CI(\blk00000001/sig0000005c ),
.LI(\blk00000001/sig00000075 ),
.O(\blk00000001/sig000001ab )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk000000b9 (
.I0(\blk00000001/sig0000015f ),
.I1(\blk00000001/sig0000017f ),
.O(\blk00000001/sig00000076 )
);
MUXCY \blk00000001/blk000000b8 (
.CI(\blk00000001/sig0000005d ),
.DI(\blk00000001/sig0000015f ),
.S(\blk00000001/sig00000076 ),
.O(\blk00000001/sig0000005e )
);
XORCY \blk00000001/blk000000b7 (
.CI(\blk00000001/sig0000005d ),
.LI(\blk00000001/sig00000076 ),
.O(\blk00000001/sig000001ac )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk000000b6 (
.I0(\blk00000001/sig00000160 ),
.I1(\blk00000001/sig00000180 ),
.O(\blk00000001/sig00000077 )
);
MUXCY \blk00000001/blk000000b5 (
.CI(\blk00000001/sig0000005e ),
.DI(\blk00000001/sig00000160 ),
.S(\blk00000001/sig00000077 ),
.O(\blk00000001/sig0000005f )
);
XORCY \blk00000001/blk000000b4 (
.CI(\blk00000001/sig0000005e ),
.LI(\blk00000001/sig00000077 ),
.O(\blk00000001/sig000001ad )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk000000b3 (
.I0(\blk00000001/sig00000161 ),
.I1(\blk00000001/sig00000181 ),
.O(\blk00000001/sig00000078 )
);
MUXCY \blk00000001/blk000000b2 (
.CI(\blk00000001/sig0000005f ),
.DI(\blk00000001/sig00000161 ),
.S(\blk00000001/sig00000078 ),
.O(\blk00000001/sig00000060 )
);
XORCY \blk00000001/blk000000b1 (
.CI(\blk00000001/sig0000005f ),
.LI(\blk00000001/sig00000078 ),
.O(\blk00000001/sig000001ae )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk000000b0 (
.I0(\blk00000001/sig00000162 ),
.I1(\blk00000001/sig00000182 ),
.O(\blk00000001/sig00000079 )
);
MUXCY \blk00000001/blk000000af (
.CI(\blk00000001/sig00000060 ),
.DI(\blk00000001/sig00000162 ),
.S(\blk00000001/sig00000079 ),
.O(\blk00000001/sig00000061 )
);
XORCY \blk00000001/blk000000ae (
.CI(\blk00000001/sig00000060 ),
.LI(\blk00000001/sig00000079 ),
.O(\blk00000001/sig000001af )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk000000ad (
.I0(\blk00000001/sig00000163 ),
.I1(\blk00000001/sig00000183 ),
.O(\blk00000001/sig0000007a )
);
MUXCY \blk00000001/blk000000ac (
.CI(\blk00000001/sig00000061 ),
.DI(\blk00000001/sig00000163 ),
.S(\blk00000001/sig0000007a ),
.O(\blk00000001/sig00000062 )
);
XORCY \blk00000001/blk000000ab (
.CI(\blk00000001/sig00000061 ),
.LI(\blk00000001/sig0000007a ),
.O(\blk00000001/sig000001b0 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk000000aa (
.I0(\blk00000001/sig00000164 ),
.I1(\blk00000001/sig00000184 ),
.O(\blk00000001/sig0000007b )
);
MUXCY \blk00000001/blk000000a9 (
.CI(\blk00000001/sig00000062 ),
.DI(\blk00000001/sig00000164 ),
.S(\blk00000001/sig0000007b ),
.O(\blk00000001/sig00000063 )
);
XORCY \blk00000001/blk000000a8 (
.CI(\blk00000001/sig00000062 ),
.LI(\blk00000001/sig0000007b ),
.O(\blk00000001/sig000001b1 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk000000a7 (
.I0(\blk00000001/sig00000165 ),
.I1(\blk00000001/sig0000016f ),
.O(\blk00000001/sig00000065 )
);
MUXCY \blk00000001/blk000000a6 (
.CI(\blk00000001/sig00000063 ),
.DI(\blk00000001/sig00000165 ),
.S(\blk00000001/sig00000065 ),
.O(\blk00000001/sig0000004e )
);
XORCY \blk00000001/blk000000a5 (
.CI(\blk00000001/sig00000063 ),
.LI(\blk00000001/sig00000065 ),
.O(\blk00000001/sig0000019b )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk000000a4 (
.I0(\blk00000001/sig00000166 ),
.I1(\blk00000001/sig00000170 ),
.O(\blk00000001/sig00000066 )
);
MUXCY \blk00000001/blk000000a3 (
.CI(\blk00000001/sig0000004e ),
.DI(\blk00000001/sig00000166 ),
.S(\blk00000001/sig00000066 ),
.O(\blk00000001/sig0000004f )
);
XORCY \blk00000001/blk000000a2 (
.CI(\blk00000001/sig0000004e ),
.LI(\blk00000001/sig00000066 ),
.O(\blk00000001/sig0000019c )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk000000a1 (
.I0(\blk00000001/sig00000167 ),
.I1(\blk00000001/sig00000171 ),
.O(\blk00000001/sig00000067 )
);
MUXCY \blk00000001/blk000000a0 (
.CI(\blk00000001/sig0000004f ),
.DI(\blk00000001/sig00000167 ),
.S(\blk00000001/sig00000067 ),
.O(\blk00000001/sig00000050 )
);
XORCY \blk00000001/blk0000009f (
.CI(\blk00000001/sig0000004f ),
.LI(\blk00000001/sig00000067 ),
.O(\blk00000001/sig0000019d )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk0000009e (
.I0(\blk00000001/sig00000168 ),
.I1(\blk00000001/sig00000172 ),
.O(\blk00000001/sig00000068 )
);
MUXCY \blk00000001/blk0000009d (
.CI(\blk00000001/sig00000050 ),
.DI(\blk00000001/sig00000168 ),
.S(\blk00000001/sig00000068 ),
.O(\blk00000001/sig00000051 )
);
XORCY \blk00000001/blk0000009c (
.CI(\blk00000001/sig00000050 ),
.LI(\blk00000001/sig00000068 ),
.O(\blk00000001/sig0000019e )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk0000009b (
.I0(\blk00000001/sig00000169 ),
.I1(\blk00000001/sig00000173 ),
.O(\blk00000001/sig00000069 )
);
MUXCY \blk00000001/blk0000009a (
.CI(\blk00000001/sig00000051 ),
.DI(\blk00000001/sig00000169 ),
.S(\blk00000001/sig00000069 ),
.O(\blk00000001/sig00000052 )
);
XORCY \blk00000001/blk00000099 (
.CI(\blk00000001/sig00000051 ),
.LI(\blk00000001/sig00000069 ),
.O(\blk00000001/sig0000019f )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000098 (
.I0(\blk00000001/sig0000016a ),
.I1(\blk00000001/sig00000174 ),
.O(\blk00000001/sig0000006a )
);
MUXCY \blk00000001/blk00000097 (
.CI(\blk00000001/sig00000052 ),
.DI(\blk00000001/sig0000016a ),
.S(\blk00000001/sig0000006a ),
.O(\blk00000001/sig00000053 )
);
XORCY \blk00000001/blk00000096 (
.CI(\blk00000001/sig00000052 ),
.LI(\blk00000001/sig0000006a ),
.O(\blk00000001/sig000001a0 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000095 (
.I0(\blk00000001/sig0000016b ),
.I1(\blk00000001/sig00000175 ),
.O(\blk00000001/sig0000006b )
);
MUXCY \blk00000001/blk00000094 (
.CI(\blk00000001/sig00000053 ),
.DI(\blk00000001/sig0000016b ),
.S(\blk00000001/sig0000006b ),
.O(\blk00000001/sig00000054 )
);
XORCY \blk00000001/blk00000093 (
.CI(\blk00000001/sig00000053 ),
.LI(\blk00000001/sig0000006b ),
.O(\blk00000001/sig000001a1 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000092 (
.I0(\blk00000001/sig0000016c ),
.I1(\blk00000001/sig00000176 ),
.O(\blk00000001/sig0000006c )
);
MUXCY \blk00000001/blk00000091 (
.CI(\blk00000001/sig00000054 ),
.DI(\blk00000001/sig0000016c ),
.S(\blk00000001/sig0000006c ),
.O(\blk00000001/sig00000055 )
);
XORCY \blk00000001/blk00000090 (
.CI(\blk00000001/sig00000054 ),
.LI(\blk00000001/sig0000006c ),
.O(\blk00000001/sig000001a2 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk0000008f (
.I0(\blk00000001/sig0000016c ),
.I1(\blk00000001/sig00000177 ),
.O(\blk00000001/sig0000006d )
);
MUXCY \blk00000001/blk0000008e (
.CI(\blk00000001/sig00000055 ),
.DI(\blk00000001/sig0000016c ),
.S(\blk00000001/sig0000006d ),
.O(\blk00000001/sig00000056 )
);
XORCY \blk00000001/blk0000008d (
.CI(\blk00000001/sig00000055 ),
.LI(\blk00000001/sig0000006d ),
.O(\blk00000001/sig000001a3 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk0000008c (
.I0(\blk00000001/sig0000016c ),
.I1(\blk00000001/sig00000178 ),
.O(\blk00000001/sig0000006e )
);
MUXCY \blk00000001/blk0000008b (
.CI(\blk00000001/sig00000056 ),
.DI(\blk00000001/sig0000016c ),
.S(\blk00000001/sig0000006e ),
.O(\blk00000001/sig00000057 )
);
XORCY \blk00000001/blk0000008a (
.CI(\blk00000001/sig00000056 ),
.LI(\blk00000001/sig0000006e ),
.O(\blk00000001/sig000001a4 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000089 (
.I0(\blk00000001/sig0000016c ),
.I1(\blk00000001/sig0000017a ),
.O(\blk00000001/sig00000070 )
);
MUXCY \blk00000001/blk00000088 (
.CI(\blk00000001/sig00000057 ),
.DI(\blk00000001/sig0000016c ),
.S(\blk00000001/sig00000070 ),
.O(\blk00000001/sig00000059 )
);
XORCY \blk00000001/blk00000087 (
.CI(\blk00000001/sig00000057 ),
.LI(\blk00000001/sig00000070 ),
.O(\blk00000001/sig000001a6 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000086 (
.I0(\blk00000001/sig0000016c ),
.I1(\blk00000001/sig0000017b ),
.O(\blk00000001/sig00000071 )
);
MUXCY \blk00000001/blk00000085 (
.CI(\blk00000001/sig00000059 ),
.DI(\blk00000001/sig0000016c ),
.S(\blk00000001/sig00000071 ),
.O(\blk00000001/sig0000005a )
);
XORCY \blk00000001/blk00000084 (
.CI(\blk00000001/sig00000059 ),
.LI(\blk00000001/sig00000071 ),
.O(\blk00000001/sig000001a7 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000083 (
.I0(\blk00000001/sig0000016c ),
.I1(\blk00000001/sig0000017c ),
.O(\blk00000001/sig00000072 )
);
MUXCY \blk00000001/blk00000082 (
.CI(\blk00000001/sig0000005a ),
.DI(\blk00000001/sig0000016c ),
.S(\blk00000001/sig00000072 ),
.O(\blk00000001/sig0000005b )
);
XORCY \blk00000001/blk00000081 (
.CI(\blk00000001/sig0000005a ),
.LI(\blk00000001/sig00000072 ),
.O(\blk00000001/sig000001a8 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000080 (
.I0(\blk00000001/sig0000016c ),
.I1(\blk00000001/sig0000017d ),
.O(\blk00000001/sig00000073 )
);
XORCY \blk00000001/blk0000007f (
.CI(\blk00000001/sig0000005b ),
.LI(\blk00000001/sig00000073 ),
.O(\blk00000001/sig000001a9 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk0000007e (
.I0(\blk00000001/sig000001b2 ),
.I1(\blk00000001/sig000000e9 ),
.O(\blk00000001/sig000000b7 )
);
MUXCY \blk00000001/blk0000007d (
.CI(\blk00000001/sig0000004b ),
.DI(\blk00000001/sig000001b2 ),
.S(\blk00000001/sig000000b7 ),
.O(\blk00000001/sig00000097 )
);
XORCY \blk00000001/blk0000007c (
.CI(\blk00000001/sig0000004b ),
.LI(\blk00000001/sig000000b7 ),
.O(\blk00000001/sig000001e6 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk0000007b (
.I0(\blk00000001/sig000001b3 ),
.I1(\blk00000001/sig000000ea ),
.O(\blk00000001/sig000000c2 )
);
MUXCY \blk00000001/blk0000007a (
.CI(\blk00000001/sig00000097 ),
.DI(\blk00000001/sig000001b3 ),
.S(\blk00000001/sig000000c2 ),
.O(\blk00000001/sig000000a2 )
);
XORCY \blk00000001/blk00000079 (
.CI(\blk00000001/sig00000097 ),
.LI(\blk00000001/sig000000c2 ),
.O(\blk00000001/sig000001f1 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000078 (
.I0(\blk00000001/sig000001be ),
.I1(\blk00000001/sig000000f2 ),
.O(\blk00000001/sig000000cd )
);
MUXCY \blk00000001/blk00000077 (
.CI(\blk00000001/sig000000a2 ),
.DI(\blk00000001/sig000001be ),
.S(\blk00000001/sig000000cd ),
.O(\blk00000001/sig000000ad )
);
XORCY \blk00000001/blk00000076 (
.CI(\blk00000001/sig000000a2 ),
.LI(\blk00000001/sig000000cd ),
.O(\blk00000001/sig000001fc )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000075 (
.I0(\blk00000001/sig000001c3 ),
.I1(\blk00000001/sig000000f3 ),
.O(\blk00000001/sig000000d1 )
);
MUXCY \blk00000001/blk00000074 (
.CI(\blk00000001/sig000000ad ),
.DI(\blk00000001/sig000001c3 ),
.S(\blk00000001/sig000000d1 ),
.O(\blk00000001/sig000000b0 )
);
XORCY \blk00000001/blk00000073 (
.CI(\blk00000001/sig000000ad ),
.LI(\blk00000001/sig000000d1 ),
.O(\blk00000001/sig000001fd )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000072 (
.I0(\blk00000001/sig000001c4 ),
.I1(\blk00000001/sig000000f4 ),
.O(\blk00000001/sig000000d2 )
);
MUXCY \blk00000001/blk00000071 (
.CI(\blk00000001/sig000000b0 ),
.DI(\blk00000001/sig000001c4 ),
.S(\blk00000001/sig000000d2 ),
.O(\blk00000001/sig000000b1 )
);
XORCY \blk00000001/blk00000070 (
.CI(\blk00000001/sig000000b0 ),
.LI(\blk00000001/sig000000d2 ),
.O(\blk00000001/sig000001fe )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk0000006f (
.I0(\blk00000001/sig000001c5 ),
.I1(\blk00000001/sig000000f5 ),
.O(\blk00000001/sig000000d3 )
);
MUXCY \blk00000001/blk0000006e (
.CI(\blk00000001/sig000000b1 ),
.DI(\blk00000001/sig000001c5 ),
.S(\blk00000001/sig000000d3 ),
.O(\blk00000001/sig000000b2 )
);
XORCY \blk00000001/blk0000006d (
.CI(\blk00000001/sig000000b1 ),
.LI(\blk00000001/sig000000d3 ),
.O(\blk00000001/sig00000200 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk0000006c (
.I0(\blk00000001/sig000001c6 ),
.I1(\blk00000001/sig000000f6 ),
.O(\blk00000001/sig000000d4 )
);
MUXCY \blk00000001/blk0000006b (
.CI(\blk00000001/sig000000b2 ),
.DI(\blk00000001/sig000001c6 ),
.S(\blk00000001/sig000000d4 ),
.O(\blk00000001/sig000000b3 )
);
XORCY \blk00000001/blk0000006a (
.CI(\blk00000001/sig000000b2 ),
.LI(\blk00000001/sig000000d4 ),
.O(\blk00000001/sig00000201 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000069 (
.I0(\blk00000001/sig000001c7 ),
.I1(\blk00000001/sig000000f7 ),
.O(\blk00000001/sig000000d5 )
);
MUXCY \blk00000001/blk00000068 (
.CI(\blk00000001/sig000000b3 ),
.DI(\blk00000001/sig000001c7 ),
.S(\blk00000001/sig000000d5 ),
.O(\blk00000001/sig000000b4 )
);
XORCY \blk00000001/blk00000067 (
.CI(\blk00000001/sig000000b3 ),
.LI(\blk00000001/sig000000d5 ),
.O(\blk00000001/sig00000202 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000066 (
.I0(\blk00000001/sig000001c8 ),
.I1(\blk00000001/sig000000f8 ),
.O(\blk00000001/sig000000d6 )
);
MUXCY \blk00000001/blk00000065 (
.CI(\blk00000001/sig000000b4 ),
.DI(\blk00000001/sig000001c8 ),
.S(\blk00000001/sig000000d6 ),
.O(\blk00000001/sig000000b5 )
);
XORCY \blk00000001/blk00000064 (
.CI(\blk00000001/sig000000b4 ),
.LI(\blk00000001/sig000000d6 ),
.O(\blk00000001/sig00000203 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000063 (
.I0(\blk00000001/sig000001c9 ),
.I1(\blk00000001/sig000000f9 ),
.O(\blk00000001/sig000000d7 )
);
MUXCY \blk00000001/blk00000062 (
.CI(\blk00000001/sig000000b5 ),
.DI(\blk00000001/sig000001c9 ),
.S(\blk00000001/sig000000d7 ),
.O(\blk00000001/sig000000b6 )
);
XORCY \blk00000001/blk00000061 (
.CI(\blk00000001/sig000000b5 ),
.LI(\blk00000001/sig000000d7 ),
.O(\blk00000001/sig00000204 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000060 (
.I0(\blk00000001/sig000001b4 ),
.I1(\blk00000001/sig000000eb ),
.O(\blk00000001/sig000000b8 )
);
MUXCY \blk00000001/blk0000005f (
.CI(\blk00000001/sig000000b6 ),
.DI(\blk00000001/sig000001b4 ),
.S(\blk00000001/sig000000b8 ),
.O(\blk00000001/sig00000098 )
);
XORCY \blk00000001/blk0000005e (
.CI(\blk00000001/sig000000b6 ),
.LI(\blk00000001/sig000000b8 ),
.O(\blk00000001/sig000001e7 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk0000005d (
.I0(\blk00000001/sig000001b5 ),
.I1(\blk00000001/sig000000ec ),
.O(\blk00000001/sig000000b9 )
);
MUXCY \blk00000001/blk0000005c (
.CI(\blk00000001/sig00000098 ),
.DI(\blk00000001/sig000001b5 ),
.S(\blk00000001/sig000000b9 ),
.O(\blk00000001/sig00000099 )
);
XORCY \blk00000001/blk0000005b (
.CI(\blk00000001/sig00000098 ),
.LI(\blk00000001/sig000000b9 ),
.O(\blk00000001/sig000001e8 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk0000005a (
.I0(\blk00000001/sig000001b6 ),
.I1(\blk00000001/sig000000ed ),
.O(\blk00000001/sig000000ba )
);
MUXCY \blk00000001/blk00000059 (
.CI(\blk00000001/sig00000099 ),
.DI(\blk00000001/sig000001b6 ),
.S(\blk00000001/sig000000ba ),
.O(\blk00000001/sig0000009a )
);
XORCY \blk00000001/blk00000058 (
.CI(\blk00000001/sig00000099 ),
.LI(\blk00000001/sig000000ba ),
.O(\blk00000001/sig000001e9 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000057 (
.I0(\blk00000001/sig000001b7 ),
.I1(\blk00000001/sig000000ee ),
.O(\blk00000001/sig000000bb )
);
MUXCY \blk00000001/blk00000056 (
.CI(\blk00000001/sig0000009a ),
.DI(\blk00000001/sig000001b7 ),
.S(\blk00000001/sig000000bb ),
.O(\blk00000001/sig0000009b )
);
XORCY \blk00000001/blk00000055 (
.CI(\blk00000001/sig0000009a ),
.LI(\blk00000001/sig000000bb ),
.O(\blk00000001/sig000001ea )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000054 (
.I0(\blk00000001/sig000001b8 ),
.I1(\blk00000001/sig000000ef ),
.O(\blk00000001/sig000000bc )
);
MUXCY \blk00000001/blk00000053 (
.CI(\blk00000001/sig0000009b ),
.DI(\blk00000001/sig000001b8 ),
.S(\blk00000001/sig000000bc ),
.O(\blk00000001/sig0000009c )
);
XORCY \blk00000001/blk00000052 (
.CI(\blk00000001/sig0000009b ),
.LI(\blk00000001/sig000000bc ),
.O(\blk00000001/sig000001eb )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000051 (
.I0(\blk00000001/sig000001b9 ),
.I1(\blk00000001/sig000000f0 ),
.O(\blk00000001/sig000000bd )
);
MUXCY \blk00000001/blk00000050 (
.CI(\blk00000001/sig0000009c ),
.DI(\blk00000001/sig000001b9 ),
.S(\blk00000001/sig000000bd ),
.O(\blk00000001/sig0000009d )
);
XORCY \blk00000001/blk0000004f (
.CI(\blk00000001/sig0000009c ),
.LI(\blk00000001/sig000000bd ),
.O(\blk00000001/sig000001ec )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk0000004e (
.I0(\blk00000001/sig000001ba ),
.I1(\blk00000001/sig000000f1 ),
.O(\blk00000001/sig000000be )
);
MUXCY \blk00000001/blk0000004d (
.CI(\blk00000001/sig0000009d ),
.DI(\blk00000001/sig000001ba ),
.S(\blk00000001/sig000000be ),
.O(\blk00000001/sig0000009e )
);
XORCY \blk00000001/blk0000004c (
.CI(\blk00000001/sig0000009d ),
.LI(\blk00000001/sig000000be ),
.O(\blk00000001/sig000001ed )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk0000004b (
.I0(\blk00000001/sig000001bb ),
.I1(\blk00000001/sig000001d8 ),
.O(\blk00000001/sig000000bf )
);
MUXCY \blk00000001/blk0000004a (
.CI(\blk00000001/sig0000009e ),
.DI(\blk00000001/sig000001bb ),
.S(\blk00000001/sig000000bf ),
.O(\blk00000001/sig0000009f )
);
XORCY \blk00000001/blk00000049 (
.CI(\blk00000001/sig0000009e ),
.LI(\blk00000001/sig000000bf ),
.O(\blk00000001/sig000001ee )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000048 (
.I0(\blk00000001/sig000001bc ),
.I1(\blk00000001/sig000001d9 ),
.O(\blk00000001/sig000000c0 )
);
MUXCY \blk00000001/blk00000047 (
.CI(\blk00000001/sig0000009f ),
.DI(\blk00000001/sig000001bc ),
.S(\blk00000001/sig000000c0 ),
.O(\blk00000001/sig000000a0 )
);
XORCY \blk00000001/blk00000046 (
.CI(\blk00000001/sig0000009f ),
.LI(\blk00000001/sig000000c0 ),
.O(\blk00000001/sig000001ef )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000045 (
.I0(\blk00000001/sig000001bd ),
.I1(\blk00000001/sig000001de ),
.O(\blk00000001/sig000000c1 )
);
MUXCY \blk00000001/blk00000044 (
.CI(\blk00000001/sig000000a0 ),
.DI(\blk00000001/sig000001bd ),
.S(\blk00000001/sig000000c1 ),
.O(\blk00000001/sig000000a1 )
);
XORCY \blk00000001/blk00000043 (
.CI(\blk00000001/sig000000a0 ),
.LI(\blk00000001/sig000000c1 ),
.O(\blk00000001/sig000001f0 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000042 (
.I0(\blk00000001/sig000001bf ),
.I1(\blk00000001/sig000001df ),
.O(\blk00000001/sig000000c3 )
);
MUXCY \blk00000001/blk00000041 (
.CI(\blk00000001/sig000000a1 ),
.DI(\blk00000001/sig000001bf ),
.S(\blk00000001/sig000000c3 ),
.O(\blk00000001/sig000000a3 )
);
XORCY \blk00000001/blk00000040 (
.CI(\blk00000001/sig000000a1 ),
.LI(\blk00000001/sig000000c3 ),
.O(\blk00000001/sig000001f2 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk0000003f (
.I0(\blk00000001/sig000001c0 ),
.I1(\blk00000001/sig000001e0 ),
.O(\blk00000001/sig000000c4 )
);
MUXCY \blk00000001/blk0000003e (
.CI(\blk00000001/sig000000a3 ),
.DI(\blk00000001/sig000001c0 ),
.S(\blk00000001/sig000000c4 ),
.O(\blk00000001/sig000000a4 )
);
XORCY \blk00000001/blk0000003d (
.CI(\blk00000001/sig000000a3 ),
.LI(\blk00000001/sig000000c4 ),
.O(\blk00000001/sig000001f3 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk0000003c (
.I0(\blk00000001/sig000001c1 ),
.I1(\blk00000001/sig000001e1 ),
.O(\blk00000001/sig000000c5 )
);
MUXCY \blk00000001/blk0000003b (
.CI(\blk00000001/sig000000a4 ),
.DI(\blk00000001/sig000001c1 ),
.S(\blk00000001/sig000000c5 ),
.O(\blk00000001/sig000000a5 )
);
XORCY \blk00000001/blk0000003a (
.CI(\blk00000001/sig000000a4 ),
.LI(\blk00000001/sig000000c5 ),
.O(\blk00000001/sig000001f4 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000039 (
.I0(\blk00000001/sig000001e2 ),
.I1(\blk00000001/sig000001c2 ),
.O(\blk00000001/sig000000c6 )
);
MUXCY \blk00000001/blk00000038 (
.CI(\blk00000001/sig000000a5 ),
.DI(\blk00000001/sig000001c2 ),
.S(\blk00000001/sig000000c6 ),
.O(\blk00000001/sig000000a6 )
);
XORCY \blk00000001/blk00000037 (
.CI(\blk00000001/sig000000a5 ),
.LI(\blk00000001/sig000000c6 ),
.O(\blk00000001/sig000001f5 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000036 (
.I0(\blk00000001/sig000001c2 ),
.I1(\blk00000001/sig000001e3 ),
.O(\blk00000001/sig000000c7 )
);
MUXCY \blk00000001/blk00000035 (
.CI(\blk00000001/sig000000a6 ),
.DI(\blk00000001/sig000001c2 ),
.S(\blk00000001/sig000000c7 ),
.O(\blk00000001/sig000000a7 )
);
XORCY \blk00000001/blk00000034 (
.CI(\blk00000001/sig000000a6 ),
.LI(\blk00000001/sig000000c7 ),
.O(\blk00000001/sig000001f6 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000033 (
.I0(\blk00000001/sig000001c2 ),
.I1(\blk00000001/sig000001e4 ),
.O(\blk00000001/sig000000c8 )
);
MUXCY \blk00000001/blk00000032 (
.CI(\blk00000001/sig000000a7 ),
.DI(\blk00000001/sig000001c2 ),
.S(\blk00000001/sig000000c8 ),
.O(\blk00000001/sig000000a8 )
);
XORCY \blk00000001/blk00000031 (
.CI(\blk00000001/sig000000a7 ),
.LI(\blk00000001/sig000000c8 ),
.O(\blk00000001/sig000001f7 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000030 (
.I0(\blk00000001/sig000001c2 ),
.I1(\blk00000001/sig000001e5 ),
.O(\blk00000001/sig000000c9 )
);
MUXCY \blk00000001/blk0000002f (
.CI(\blk00000001/sig000000a8 ),
.DI(\blk00000001/sig000001c2 ),
.S(\blk00000001/sig000000c9 ),
.O(\blk00000001/sig000000a9 )
);
XORCY \blk00000001/blk0000002e (
.CI(\blk00000001/sig000000a8 ),
.LI(\blk00000001/sig000000c9 ),
.O(\blk00000001/sig000001f8 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk0000002d (
.I0(\blk00000001/sig000001c2 ),
.I1(\blk00000001/sig000001da ),
.O(\blk00000001/sig000000ca )
);
MUXCY \blk00000001/blk0000002c (
.CI(\blk00000001/sig000000a9 ),
.DI(\blk00000001/sig000001c2 ),
.S(\blk00000001/sig000000ca ),
.O(\blk00000001/sig000000aa )
);
XORCY \blk00000001/blk0000002b (
.CI(\blk00000001/sig000000a9 ),
.LI(\blk00000001/sig000000ca ),
.O(\blk00000001/sig000001f9 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk0000002a (
.I0(\blk00000001/sig000001c2 ),
.I1(\blk00000001/sig000001db ),
.O(\blk00000001/sig000000cb )
);
MUXCY \blk00000001/blk00000029 (
.CI(\blk00000001/sig000000aa ),
.DI(\blk00000001/sig000001c2 ),
.S(\blk00000001/sig000000cb ),
.O(\blk00000001/sig000000ab )
);
XORCY \blk00000001/blk00000028 (
.CI(\blk00000001/sig000000aa ),
.LI(\blk00000001/sig000000cb ),
.O(\blk00000001/sig000001fa )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000027 (
.I0(\blk00000001/sig000001c2 ),
.I1(\blk00000001/sig000001dc ),
.O(\blk00000001/sig000000cc )
);
MUXCY \blk00000001/blk00000026 (
.CI(\blk00000001/sig000000ab ),
.DI(\blk00000001/sig000001c2 ),
.S(\blk00000001/sig000000cc ),
.O(\blk00000001/sig000000ac )
);
XORCY \blk00000001/blk00000025 (
.CI(\blk00000001/sig000000ab ),
.LI(\blk00000001/sig000000cc ),
.O(\blk00000001/sig000001fb )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000024 (
.I0(\blk00000001/sig000001c2 ),
.I1(\blk00000001/sig000001dd ),
.O(\blk00000001/sig000000ce )
);
MUXCY \blk00000001/blk00000023 (
.CI(\blk00000001/sig000000ac ),
.DI(\blk00000001/sig000001c2 ),
.S(\blk00000001/sig000000ce ),
.O(\blk00000001/sig000000ae )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000022 (
.I0(\blk00000001/sig000001c2 ),
.I1(\blk00000001/sig000001dd ),
.O(\blk00000001/sig000000cf )
);
MUXCY \blk00000001/blk00000021 (
.CI(\blk00000001/sig000000ae ),
.DI(\blk00000001/sig000001c2 ),
.S(\blk00000001/sig000000cf ),
.O(\blk00000001/sig000000af )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000020 (
.I0(\blk00000001/sig000001c2 ),
.I1(\blk00000001/sig000001dd ),
.O(\blk00000001/sig000000d0 )
);
XORCY \blk00000001/blk0000001f (
.CI(\blk00000001/sig000000af ),
.LI(\blk00000001/sig000000d0 ),
.O(\blk00000001/sig000001ff )
);
MULT18X18S \blk00000001/blk0000001e (
.C(clk),
.CE(\blk00000001/sig0000004c ),
.R(\blk00000001/sig0000004b ),
.A({\blk00000001/sig0000004b , a[16], a[15], a[14], a[13], a[12], a[11], a[10], a[9], a[8], a[7], a[6], a[5], a[4], a[3], a[2], a[1], a[0]}),
.B({\blk00000001/sig0000004b , b[16], b[15], b[14], b[13], b[12], b[11], b[10], b[9], b[8], b[7], b[6], b[5], b[4], b[3], b[2], b[1], b[0]}),
.P({\NLW_blk00000001/blk0000001e_P<35>_UNCONNECTED , \blk00000001/sig00000115 , \blk00000001/sig00000114 , \blk00000001/sig00000113 ,
\blk00000001/sig00000112 , \blk00000001/sig00000111 , \blk00000001/sig0000010f , \blk00000001/sig0000010e , \blk00000001/sig0000010d ,
\blk00000001/sig0000010c , \blk00000001/sig0000010b , \blk00000001/sig0000010a , \blk00000001/sig00000109 , \blk00000001/sig00000108 ,
\blk00000001/sig00000107 , \blk00000001/sig00000106 , \blk00000001/sig00000104 , \blk00000001/sig00000103 , \blk00000001/sig00000102 ,
\blk00000001/sig00000101 , \blk00000001/sig00000100 , \blk00000001/sig000000ff , \blk00000001/sig000000fe , \blk00000001/sig000000fd ,
\blk00000001/sig000000fc , \blk00000001/sig000000fb , \blk00000001/sig0000011c , \blk00000001/sig0000011b , \blk00000001/sig0000011a ,
\blk00000001/sig00000119 , \blk00000001/sig00000118 , \blk00000001/sig00000117 , \blk00000001/sig00000116 , \blk00000001/sig00000110 ,
\blk00000001/sig00000105 , \blk00000001/sig000000fa })
);
MULT18X18S \blk00000001/blk0000001d (
.C(clk),
.CE(\blk00000001/sig0000004c ),
.R(\blk00000001/sig0000004b ),
.A({\blk00000001/sig0000004b , a[16], a[15], a[14], a[13], a[12], a[11], a[10], a[9], a[8], a[7], a[6], a[5], a[4], a[3], a[2], a[1], a[0]}),
.B({b[23], b[23], b[23], b[23], b[23], b[23], b[23], b[23], b[23], b[23], b[23], b[23], b[22], b[21], b[20], b[19], b[18], b[17]}),
.P({\NLW_blk00000001/blk0000001d_P<35>_UNCONNECTED , \NLW_blk00000001/blk0000001d_P<34>_UNCONNECTED ,
\NLW_blk00000001/blk0000001d_P<33>_UNCONNECTED , \NLW_blk00000001/blk0000001d_P<32>_UNCONNECTED , \NLW_blk00000001/blk0000001d_P<31>_UNCONNECTED ,
\NLW_blk00000001/blk0000001d_P<30>_UNCONNECTED , \NLW_blk00000001/blk0000001d_P<29>_UNCONNECTED , \NLW_blk00000001/blk0000001d_P<28>_UNCONNECTED ,
\NLW_blk00000001/blk0000001d_P<27>_UNCONNECTED , \NLW_blk00000001/blk0000001d_P<26>_UNCONNECTED , \NLW_blk00000001/blk0000001d_P<25>_UNCONNECTED ,
\NLW_blk00000001/blk0000001d_P<24>_UNCONNECTED , \blk00000001/sig0000012c , \blk00000001/sig0000012b , \blk00000001/sig0000012a ,
\blk00000001/sig00000129 , \blk00000001/sig00000127 , \blk00000001/sig00000126 , \blk00000001/sig00000125 , \blk00000001/sig00000124 ,
\blk00000001/sig00000123 , \blk00000001/sig00000122 , \blk00000001/sig00000121 , \blk00000001/sig00000120 , \blk00000001/sig0000011f ,
\blk00000001/sig0000011e , \blk00000001/sig00000134 , \blk00000001/sig00000133 , \blk00000001/sig00000132 , \blk00000001/sig00000131 ,
\blk00000001/sig00000130 , \blk00000001/sig0000012f , \blk00000001/sig0000012e , \blk00000001/sig0000012d , \blk00000001/sig00000128 ,
\blk00000001/sig0000011d })
);
MULT18X18S \blk00000001/blk0000001c (
.C(clk),
.CE(\blk00000001/sig0000004c ),
.R(\blk00000001/sig0000004b ),
.A({a[23], a[23], a[23], a[23], a[23], a[23], a[23], a[23], a[23], a[23], a[23], a[23], a[22], a[21], a[20], a[19], a[18], a[17]}),
.B({\blk00000001/sig0000004b , b[16], b[15], b[14], b[13], b[12], b[11], b[10], b[9], b[8], b[7], b[6], b[5], b[4], b[3], b[2], b[1], b[0]}),
.P({\NLW_blk00000001/blk0000001c_P<35>_UNCONNECTED , \NLW_blk00000001/blk0000001c_P<34>_UNCONNECTED ,
\NLW_blk00000001/blk0000001c_P<33>_UNCONNECTED , \NLW_blk00000001/blk0000001c_P<32>_UNCONNECTED , \NLW_blk00000001/blk0000001c_P<31>_UNCONNECTED ,
\NLW_blk00000001/blk0000001c_P<30>_UNCONNECTED , \NLW_blk00000001/blk0000001c_P<29>_UNCONNECTED , \NLW_blk00000001/blk0000001c_P<28>_UNCONNECTED ,
\NLW_blk00000001/blk0000001c_P<27>_UNCONNECTED , \NLW_blk00000001/blk0000001c_P<26>_UNCONNECTED , \NLW_blk00000001/blk0000001c_P<25>_UNCONNECTED ,
\NLW_blk00000001/blk0000001c_P<24>_UNCONNECTED , \blk00000001/sig00000144 , \blk00000001/sig00000143 , \blk00000001/sig00000142 ,
\blk00000001/sig00000141 , \blk00000001/sig0000013f , \blk00000001/sig0000013e , \blk00000001/sig0000013d , \blk00000001/sig0000013c ,
\blk00000001/sig0000013b , \blk00000001/sig0000013a , \blk00000001/sig00000139 , \blk00000001/sig00000138 , \blk00000001/sig00000137 ,
\blk00000001/sig00000136 , \blk00000001/sig0000014c , \blk00000001/sig0000014b , \blk00000001/sig0000014a , \blk00000001/sig00000149 ,
\blk00000001/sig00000148 , \blk00000001/sig00000147 , \blk00000001/sig00000146 , \blk00000001/sig00000145 , \blk00000001/sig00000140 ,
\blk00000001/sig00000135 })
);
MULT18X18S \blk00000001/blk0000001b (
.C(clk),
.CE(\blk00000001/sig0000004c ),
.R(\blk00000001/sig0000004b ),
.A({a[23], a[23], a[23], a[23], a[23], a[23], a[23], a[23], a[23], a[23], a[23], a[23], a[22], a[21], a[20], a[19], a[18], a[17]}),
.B({b[23], b[23], b[23], b[23], b[23], b[23], b[23], b[23], b[23], b[23], b[23], b[23], b[22], b[21], b[20], b[19], b[18], b[17]}),
.P({\NLW_blk00000001/blk0000001b_P<35>_UNCONNECTED , \NLW_blk00000001/blk0000001b_P<34>_UNCONNECTED ,
\NLW_blk00000001/blk0000001b_P<33>_UNCONNECTED , \NLW_blk00000001/blk0000001b_P<32>_UNCONNECTED , \NLW_blk00000001/blk0000001b_P<31>_UNCONNECTED ,
\NLW_blk00000001/blk0000001b_P<30>_UNCONNECTED , \NLW_blk00000001/blk0000001b_P<29>_UNCONNECTED , \NLW_blk00000001/blk0000001b_P<28>_UNCONNECTED ,
\NLW_blk00000001/blk0000001b_P<27>_UNCONNECTED , \NLW_blk00000001/blk0000001b_P<26>_UNCONNECTED , \NLW_blk00000001/blk0000001b_P<25>_UNCONNECTED ,
\NLW_blk00000001/blk0000001b_P<24>_UNCONNECTED , \NLW_blk00000001/blk0000001b_P<23>_UNCONNECTED , \NLW_blk00000001/blk0000001b_P<22>_UNCONNECTED ,
\NLW_blk00000001/blk0000001b_P<21>_UNCONNECTED , \NLW_blk00000001/blk0000001b_P<20>_UNCONNECTED , \NLW_blk00000001/blk0000001b_P<19>_UNCONNECTED ,
\NLW_blk00000001/blk0000001b_P<18>_UNCONNECTED , \NLW_blk00000001/blk0000001b_P<17>_UNCONNECTED , \NLW_blk00000001/blk0000001b_P<16>_UNCONNECTED ,
\NLW_blk00000001/blk0000001b_P<15>_UNCONNECTED , \NLW_blk00000001/blk0000001b_P<14>_UNCONNECTED , \blk00000001/sig00000151 , \blk00000001/sig00000150
, \blk00000001/sig0000014f , \blk00000001/sig0000014e , \blk00000001/sig0000015a , \blk00000001/sig00000159 , \blk00000001/sig00000158 ,
\blk00000001/sig00000157 , \blk00000001/sig00000156 , \blk00000001/sig00000155 , \blk00000001/sig00000154 , \blk00000001/sig00000153 ,
\blk00000001/sig00000152 , \blk00000001/sig0000014d })
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk0000001a (
.C(clk),
.D(\blk00000001/sig00000219 ),
.Q(p[47])
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000019 (
.C(clk),
.D(\blk00000001/sig00000218 ),
.Q(p[46])
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000018 (
.C(clk),
.D(\blk00000001/sig00000217 ),
.Q(p[45])
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000017 (
.C(clk),
.D(\blk00000001/sig00000216 ),
.Q(p[44])
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000016 (
.C(clk),
.D(\blk00000001/sig00000215 ),
.Q(p[43])
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000015 (
.C(clk),
.D(\blk00000001/sig00000214 ),
.Q(p[42])
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000014 (
.C(clk),
.D(\blk00000001/sig00000213 ),
.Q(p[41])
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000013 (
.C(clk),
.D(\blk00000001/sig00000212 ),
.Q(p[40])
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000012 (
.C(clk),
.D(\blk00000001/sig00000211 ),
.Q(p[39])
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000011 (
.C(clk),
.D(\blk00000001/sig00000210 ),
.Q(p[38])
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000010 (
.C(clk),
.D(\blk00000001/sig0000020f ),
.Q(p[37])
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk0000000f (
.C(clk),
.D(\blk00000001/sig0000020e ),
.Q(p[36])
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk0000000e (
.C(clk),
.D(\blk00000001/sig0000020d ),
.Q(p[35])
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk0000000d (
.C(clk),
.D(\blk00000001/sig0000020c ),
.Q(p[34])
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk0000000c (
.C(clk),
.D(\blk00000001/sig0000020b ),
.Q(p[33])
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk0000000b (
.C(clk),
.D(\blk00000001/sig0000020a ),
.Q(p[32])
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk0000000a (
.C(clk),
.D(\blk00000001/sig00000209 ),
.Q(p[31])
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000009 (
.C(clk),
.D(\blk00000001/sig00000208 ),
.Q(p[30])
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000008 (
.C(clk),
.D(\blk00000001/sig00000207 ),
.Q(p[29])
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000007 (
.C(clk),
.D(\blk00000001/sig00000206 ),
.Q(p[28])
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000006 (
.C(clk),
.D(\blk00000001/sig00000205 ),
.Q(p[27])
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000005 (
.C(clk),
.D(\blk00000001/sig0000021b ),
.Q(p[26])
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000004 (
.C(clk),
.D(\blk00000001/sig0000021a ),
.Q(p[25])
);
VCC \blk00000001/blk00000003 (
.P(\blk00000001/sig0000004c )
);
GND \blk00000001/blk00000002 (
.G(\blk00000001/sig0000004b )
);
// synthesis translate_on
endmodule
|
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
|
module sky130_fd_sc_hs__dlrtp_4 (
RESET_B,
D ,
GATE ,
Q ,
VPWR ,
VGND
);
input RESET_B;
input D ;
input GATE ;
output Q ;
input VPWR ;
input VGND ;
sky130_fd_sc_hs__dlrtp base (
.RESET_B(RESET_B),
.D(D),
.GATE(GATE),
.Q(Q),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
|
module sky130_fd_sc_hs__dlrtp_4 (
RESET_B,
D ,
GATE ,
Q
);
input RESET_B;
input D ;
input GATE ;
output Q ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__dlrtp base (
.RESET_B(RESET_B),
.D(D),
.GATE(GATE),
.Q(Q)
);
endmodule
|
module bsg_link_osdr_phy
#(parameter `BSG_INV_PARAM(width_p )
,parameter strength_p = 0)
(input clk_i
,input reset_i
,input [width_p-1:0] data_i
,output clk_o
,output [width_p-1:0] data_o
);
bsg_link_osdr_phy_phase_align clk_pa
(.clk_i (clk_i)
,.reset_i(reset_i)
,.clk_o (clk_o)
);
bsg_dff #(.width_p(width_p)) data_ff
(.clk_i(clk_i),.data_i(data_i),.data_o(data_o));
endmodule
|
module sky130_fd_sc_hd__clkinv_1 (
Y ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__clkinv base (
.Y(Y),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
|
module sky130_fd_sc_hd__clkinv_1 (
Y,
A
);
output Y;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__clkinv base (
.Y(Y),
.A(A)
);
endmodule
|
module sky130_fd_sc_lp__dfxtp_4 (
Q ,
CLK ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
output Q ;
input CLK ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__dfxtp base (
.Q(Q),
.CLK(CLK),
.D(D),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
|
module sky130_fd_sc_lp__dfxtp_4 (
Q ,
CLK,
D
);
output Q ;
input CLK;
input D ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__dfxtp base (
.Q(Q),
.CLK(CLK),
.D(D)
);
endmodule
|
module cpu (
`ifdef DEBUG
output [15:0] cs,
output [15:0] ip,
output [ 2:0] state,
output [ 2:0] next_state,
output [ 5:0] iralu,
output [15:0] x,
output [15:0] y,
output [15:0] imm,
output [15:0] aluo,
output [15:0] ax,
output [15:0] dx,
output [15:0] bp,
output [15:0] si,
output [15:0] es,
input dbg_block,
output [15:0] c,
output [ 3:0] addr_c,
output [15:0] cpu_dat_o,
output [15:0] d,
output [ 3:0] addr_d,
output byte_exec,
output [ 8:0] flags,
output end_seq,
output ext_int,
output cpu_block,
`endif
// Wishbone master interface
input wb_clk_i,
input wb_rst_i,
input [15:0] wb_dat_i,
output [15:0] wb_dat_o,
output [19:1] wb_adr_o,
output wb_we_o,
output wb_tga_o, // io/mem
output [ 1:0] wb_sel_o,
output wb_stb_o,
output wb_cyc_o,
input wb_ack_i,
input wb_tgc_i, // intr
output wb_tgc_o // inta
);
// Net declarations
`ifndef DEBUG
wire [15:0] cs, ip;
wire [15:0] imm;
wire [15:0] cpu_dat_o;
wire byte_exec;
wire cpu_block;
`endif
wire [`IR_SIZE-1:0] ir;
wire [15:0] off;
wire [19:0] addr_exec, addr_fetch;
wire byte_fetch, fetch_or_exec;
wire of, zf, cx_zero;
wire div_exc;
wire wr_ip0;
wire ifl;
wire cpu_byte_o;
wire cpu_m_io;
wire [19:0] cpu_adr_o;
wire wb_block;
wire [15:0] cpu_dat_i;
wire cpu_we_o;
wire [15:0] iid_dat_i;
// Module instantiations
fetch fetch0 (
`ifdef DEBUG
.state (state),
.next_state (next_state),
.ext_int (ext_int),
.end_seq (end_seq),
`endif
.clk (wb_clk_i),
.rst (wb_rst_i),
.cs (cs),
.ip (ip),
.of (of),
.zf (zf),
.data (cpu_dat_i),
.ir (ir),
.off (off),
.imm (imm),
.pc (addr_fetch),
.cx_zero (cx_zero),
.bytefetch (byte_fetch),
.fetch_or_exec (fetch_or_exec),
.block (cpu_block),
.div_exc (div_exc),
.wr_ip0 (wr_ip0),
.intr (wb_tgc_i),
.ifl (ifl),
.inta (wb_tgc_o)
);
exec exec0 (
`ifdef DEBUG
.x (x),
.y (y),
.aluo (aluo),
.ax (ax),
.dx (dx),
.bp (bp),
.si (si),
.es (es),
.c (c),
.addr_c (addr_c),
.omemalu (d),
.addr_d (addr_d),
.flags (flags),
`endif
.ir (ir),
.off (off),
.imm (imm),
.cs (cs),
.ip (ip),
.of (of),
.zf (zf),
.cx_zero (cx_zero),
.clk (wb_clk_i),
.rst (wb_rst_i),
.memout (iid_dat_i),
.wr_data (cpu_dat_o),
.addr (addr_exec),
.we (cpu_we_o),
.m_io (cpu_m_io),
.byteop (byte_exec),
.block (cpu_block),
.div_exc (div_exc),
.wrip0 (wr_ip0),
.ifl (ifl)
);
wb_master wm0 (
.cpu_byte_o (cpu_byte_o),
.cpu_memop (ir[`MEM_OP]),
.cpu_m_io (cpu_m_io),
.cpu_adr_o (cpu_adr_o),
.cpu_block (wb_block),
.cpu_dat_i (cpu_dat_i),
.cpu_dat_o (cpu_dat_o),
.cpu_we_o (cpu_we_o),
.wb_clk_i (wb_clk_i),
.wb_rst_i (wb_rst_i),
.wb_dat_i (wb_dat_i),
.wb_dat_o (wb_dat_o),
.wb_adr_o (wb_adr_o),
.wb_we_o (wb_we_o),
.wb_tga_o (wb_tga_o),
.wb_sel_o (wb_sel_o),
.wb_stb_o (wb_stb_o),
.wb_cyc_o (wb_cyc_o),
.wb_ack_i (wb_ack_i)
);
// Assignments
assign cpu_adr_o = fetch_or_exec ? addr_exec : addr_fetch;
assign cpu_byte_o = fetch_or_exec ? byte_exec : byte_fetch;
assign iid_dat_i = wb_tgc_o ? wb_dat_i : cpu_dat_i;
`ifdef DEBUG
assign iralu = ir[28:23];
assign cpu_block = wb_block | dbg_block;
`else
assign cpu_block = wb_block;
`endif
endmodule
|
module wb_master (
input cpu_byte_o,
input cpu_memop,
input cpu_m_io,
input [19:0] cpu_adr_o,
output reg cpu_block,
output reg [15:0] cpu_dat_i,
input [15:0] cpu_dat_o,
input cpu_we_o,
input wb_clk_i,
input wb_rst_i,
input [15:0] wb_dat_i,
output [15:0] wb_dat_o,
output reg [19:1] wb_adr_o,
output wb_we_o,
output wb_tga_o,
output reg [ 1:0] wb_sel_o,
output reg wb_stb_o,
output reg wb_cyc_o,
input wb_ack_i
);
// Register and nets declarations
reg [ 1:0] cs; // current state
wire op; // in an operation
wire odd_word; // unaligned word
wire a0; // address 0 pin
wire [15:0] blw; // low byte (sign extended)
wire [15:0] bhw; // high byte (sign extended)
wire [19:1] adr1; // next address (for unaligned acc)
wire [ 1:0] sel_o; // bus byte select
// Declare the symbolic names for states
parameter [1:0]
cyc0_lo = 3'd0,
stb1_hi = 3'd1,
stb1_lo = 3'd2,
stb2_hi = 3'd3;
// Assignments
assign op = (cpu_memop | cpu_m_io);
assign odd_word = (cpu_adr_o[0] & !cpu_byte_o);
assign a0 = cpu_adr_o[0];
assign blw = { {8{wb_dat_i[7]}}, wb_dat_i[7:0] };
assign bhw = { {8{wb_dat_i[15]}}, wb_dat_i[15:8] };
assign adr1 = a0 ? (cpu_adr_o[19:1] + 1'b1)
: cpu_adr_o[19:1];
assign wb_dat_o = a0 ? { cpu_dat_o[7:0], cpu_dat_o[15:8] }
: cpu_dat_o;
assign wb_we_o = cpu_we_o;
assign wb_tga_o = cpu_m_io;
assign sel_o = a0 ? 2'b10 : (cpu_byte_o ? 2'b01 : 2'b11);
// Behaviour
// cpu_dat_i
always @(posedge wb_clk_i)
cpu_dat_i <= (cs == cyc0_lo) ?
(wb_ack_i ?
(a0 ? bhw : (cpu_byte_o ? blw : wb_dat_i))
: cpu_dat_i)
: ((cs == stb1_lo && wb_ack_i) ?
{ wb_dat_i[7:0], cpu_dat_i[7:0] }
: cpu_dat_i);
// outputs setup
always @(*)
case (cs)
default:
begin
cpu_block <= op;
wb_adr_o <= cpu_adr_o[19:1];
wb_sel_o <= sel_o;
wb_stb_o <= op;
wb_cyc_o <= op;
end
stb1_hi:
begin
cpu_block <= odd_word | wb_ack_i;
wb_adr_o <= cpu_adr_o[19:1];
wb_sel_o <= sel_o;
wb_stb_o <= 1'b0;
wb_cyc_o <= odd_word;
end
stb1_lo:
begin
cpu_block <= 1'b1;
wb_adr_o <= adr1;
wb_sel_o <= 2'b01;
wb_stb_o <= 1'b1;
wb_cyc_o <= 1'b1;
end
stb2_hi:
begin
cpu_block <= wb_ack_i;
wb_adr_o <= adr1;
wb_sel_o <= 2'b01;
wb_stb_o <= 1'b0;
wb_cyc_o <= 1'b0;
end
endcase
// state machine
always @(posedge wb_clk_i)
if (wb_rst_i) cs <= cyc0_lo;
else
case (cs)
default: cs <= wb_ack_i ? (op ? stb1_hi : cyc0_lo)
: cyc0_lo;
stb1_hi: cs <= wb_ack_i ? stb1_hi
: (odd_word ? stb1_lo : cyc0_lo);
stb1_lo: cs <= wb_ack_i ? stb2_hi : stb1_lo;
stb2_hi: cs <= wb_ack_i ? stb2_hi : cyc0_lo;
endcase
endmodule
|
module outputs)
wire [`JBI_WDQ_ADDR_WIDTH-1:0]wdq_raddr; // From u_wdq_ctl of jbi_min_wdq_ctl.v
wire wdq_rd_en; // From u_wdq_ctl of jbi_min_wdq_ctl.v
wire [`JBI_WDQ_WIDTH-1:0]wdq_rdata; // From u_wdq_buf of jbi_min_wdq_buf.v
wire [`JBI_WDQ_ADDR_WIDTH-1:0]wdq_waddr; // From u_wdq_ctl of jbi_min_wdq_ctl.v
wire [127:0] wdq_wdata; // From u_wdq_ctl of jbi_min_wdq_ctl.v
wire [6:0] wdq_wdata_ecc0; // From u_wdq_ctl of jbi_min_wdq_ctl.v
wire [6:0] wdq_wdata_ecc1; // From u_wdq_ctl of jbi_min_wdq_ctl.v
wire [6:0] wdq_wdata_ecc2; // From u_wdq_ctl of jbi_min_wdq_ctl.v
wire [6:0] wdq_wdata_ecc3; // From u_wdq_ctl of jbi_min_wdq_ctl.v
wire wdq_wr_en; // From u_wdq_ctl of jbi_min_wdq_ctl.v
// End of automatics
////////////////////////////////////////////////////////////////////////
// Local signal declarations
////////////////////////////////////////////////////////////////////////
//
// Code start here
//
jbi_min_wdq_ctl u_wdq_ctl (/*AUTOINST*/
// Outputs
.min_csr_perf_dma_wr8(min_csr_perf_dma_wr8),
.wdq_wr_en (wdq_wr_en),
.wdq_wdata (wdq_wdata[127:0]),
.wdq_wdata_ecc0(wdq_wdata_ecc0[6:0]),
.wdq_wdata_ecc1(wdq_wdata_ecc1[6:0]),
.wdq_wdata_ecc2(wdq_wdata_ecc2[6:0]),
.wdq_wdata_ecc3(wdq_wdata_ecc3[6:0]),
.wdq_waddr (wdq_waddr[`JBI_WDQ_ADDR_WIDTH-1:0]),
.wdq_rd_en (wdq_rd_en),
.wdq_raddr (wdq_raddr[`JBI_WDQ_ADDR_WIDTH-1:0]),
.wdq_rdq0_push(wdq_rdq0_push),
.wdq_rdq1_push(wdq_rdq1_push),
.wdq_rdq2_push(wdq_rdq2_push),
.wdq_rdq3_push(wdq_rdq3_push),
.wdq_rdq_wdata(wdq_rdq_wdata[`JBI_RDQ_WIDTH-1:0]),
.wdq_rhq0_push(wdq_rhq0_push),
.wdq_rhq1_push(wdq_rhq1_push),
.wdq_rhq2_push(wdq_rhq2_push),
.wdq_rhq3_push(wdq_rhq3_push),
.wdq_rhq_wdata(wdq_rhq_wdata[`JBI_RHQ_WIDTH-1:0]),
.wdq_rq_tag_byps(wdq_rq_tag_byps),
.wdq_wr_vld (wdq_wr_vld),
.min_aok_on (min_aok_on),
.min_aok_off (min_aok_off),
// Inputs
.clk (clk),
.rst_l (rst_l),
.csr_jbi_config2_iq_high(csr_jbi_config2_iq_high[3:0]),
.csr_jbi_config2_iq_low(csr_jbi_config2_iq_low[3:0]),
.csr_jbi_config2_ord_wr(csr_jbi_config2_ord_wr),
.csr_jbi_config2_ord_rd(csr_jbi_config2_ord_rd),
.io_jbi_j_ad_ff(io_jbi_j_ad_ff[127:0]),
.io_jbi_j_adtype_ff(io_jbi_j_adtype_ff[`JBI_ADTYPE_JID_HI:`JBI_ADTYPE_JID_LO]),
.parse_wdq_push(parse_wdq_push),
.parse_sctag_req(parse_sctag_req[2:0]),
.parse_hdr (parse_hdr),
.parse_rw (parse_rw),
.parse_subline_req(parse_subline_req),
.parse_install_mode(parse_install_mode),
.parse_data_err(parse_data_err),
.parse_err_nonex_rd(parse_err_nonex_rd),
.rdq0_full (rdq0_full),
.rdq1_full (rdq1_full),
.rdq2_full (rdq2_full),
.rdq3_full (rdq3_full),
.wdq_rdata (wdq_rdata[`JBI_WDQ_WIDTH-1:0]),
.rhq0_full (rhq0_full),
.rhq1_full (rhq1_full),
.rhq2_full (rhq2_full),
.rhq3_full (rhq3_full));
jbi_min_wdq_buf u_wdq_buf (/*AUTOINST*/
// Outputs
.wdq_rdata (wdq_rdata[`JBI_WDQ_WIDTH-1:0]),
// Inputs
.clk (clk),
.arst_l (arst_l),
.testmux_sel (testmux_sel),
.hold (hold),
.rst_tri_en (rst_tri_en),
.wdq_wr_en (wdq_wr_en),
.wdq_rd_en (wdq_rd_en),
.wdq_waddr (wdq_waddr[`JBI_WDQ_ADDR_WIDTH-1:0]),
.wdq_raddr (wdq_raddr[`JBI_WDQ_ADDR_WIDTH-1:0]),
.wdq_wdata (wdq_wdata[127:0]),
.wdq_wdata_ecc0(wdq_wdata_ecc0[6:0]),
.wdq_wdata_ecc1(wdq_wdata_ecc1[6:0]),
.wdq_wdata_ecc2(wdq_wdata_ecc2[6:0]),
.wdq_wdata_ecc3(wdq_wdata_ecc3[6:0]));
endmodule
|
module sky130_fd_sc_lp__sdfxbp (
Q ,
Q_N,
CLK,
D ,
SCD,
SCE
);
// Module ports
output Q ;
output Q_N;
input CLK;
input D ;
input SCD;
input SCE;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire buf_Q ;
wire mux_out ;
reg notifier ;
wire D_delayed ;
wire SCD_delayed;
wire SCE_delayed;
wire CLK_delayed;
wire awake ;
wire cond1 ;
wire cond2 ;
wire cond3 ;
// Name Output Other arguments
sky130_fd_sc_lp__udp_mux_2to1 mux_2to10 (mux_out, D_delayed, SCD_delayed, SCE_delayed );
sky130_fd_sc_lp__udp_dff$P_pp$PG$N dff0 (buf_Q , mux_out, CLK_delayed, notifier, VPWR, VGND);
assign awake = ( VPWR === 1'b1 );
assign cond1 = ( ( SCE_delayed === 1'b0 ) && awake );
assign cond2 = ( ( SCE_delayed === 1'b1 ) && awake );
assign cond3 = ( ( D_delayed !== SCD_delayed ) && awake );
buf buf0 (Q , buf_Q );
not not0 (Q_N , buf_Q );
endmodule
|
module alt_mem_ddrx_rank_timer #
( parameter
CFG_DWIDTH_RATIO = 2,
CFG_CTL_TBP_NUM = 4,
CFG_CTL_ARBITER_TYPE = "ROWCOL",
CFG_MEM_IF_CHIP = 1,
CFG_MEM_IF_CS_WIDTH = 1,
CFG_INT_SIZE_WIDTH = 4,
CFG_AFI_INTF_PHASE_NUM = 2,
CFG_ENABLE_BURST_INTERRUPT = 0,
CFG_ENABLE_BURST_TERMINATE = 0,
CFG_REG_GRANT = 0,
CFG_RANK_TIMER_OUTPUT_REG = 0,
CFG_PORT_WIDTH_BURST_LENGTH = 5,
T_PARAM_FOUR_ACT_TO_ACT_WIDTH = 0,
T_PARAM_ACT_TO_ACT_DIFF_BANK_WIDTH = 0,
T_PARAM_WR_TO_WR_WIDTH = 0,
T_PARAM_WR_TO_WR_DIFF_CHIP_WIDTH = 0,
T_PARAM_WR_TO_RD_WIDTH = 0,
T_PARAM_WR_TO_RD_BC_WIDTH = 0,
T_PARAM_WR_TO_RD_DIFF_CHIP_WIDTH = 0,
T_PARAM_RD_TO_RD_WIDTH = 0,
T_PARAM_RD_TO_RD_DIFF_CHIP_WIDTH = 0,
T_PARAM_RD_TO_WR_WIDTH = 0,
T_PARAM_RD_TO_WR_BC_WIDTH = 0,
T_PARAM_RD_TO_WR_DIFF_CHIP_WIDTH = 0
)
(
ctl_clk,
ctl_reset_n,
// MMR Configurations
cfg_burst_length,
// Timing parameters
t_param_four_act_to_act,
t_param_act_to_act_diff_bank,
t_param_wr_to_wr,
t_param_wr_to_wr_diff_chip,
t_param_wr_to_rd,
t_param_wr_to_rd_bc,
t_param_wr_to_rd_diff_chip,
t_param_rd_to_rd,
t_param_rd_to_rd_diff_chip,
t_param_rd_to_wr,
t_param_rd_to_wr_bc,
t_param_rd_to_wr_diff_chip,
// Arbiter Interface
bg_do_write,
bg_do_read,
bg_do_burst_chop,
bg_do_burst_terminate,
bg_do_activate,
bg_do_precharge,
bg_to_chip,
bg_effective_size,
bg_interrupt_ready,
// Command Generator Interface
cmd_gen_chipsel,
// TBP Interface
tbp_chipsel,
tbp_load,
// Sideband Interface
stall_chip,
can_activate,
can_precharge,
can_read,
can_write
);
input ctl_clk;
input ctl_reset_n;
input [CFG_PORT_WIDTH_BURST_LENGTH - 1 : 0] cfg_burst_length;
input [T_PARAM_FOUR_ACT_TO_ACT_WIDTH - 1 : 0] t_param_four_act_to_act;
input [T_PARAM_ACT_TO_ACT_DIFF_BANK_WIDTH - 1 : 0] t_param_act_to_act_diff_bank;
input [T_PARAM_WR_TO_WR_WIDTH - 1 : 0] t_param_wr_to_wr;
input [T_PARAM_WR_TO_WR_DIFF_CHIP_WIDTH - 1 : 0] t_param_wr_to_wr_diff_chip;
input [T_PARAM_WR_TO_RD_WIDTH - 1 : 0] t_param_wr_to_rd;
input [T_PARAM_WR_TO_RD_BC_WIDTH - 1 : 0] t_param_wr_to_rd_bc;
input [T_PARAM_WR_TO_RD_DIFF_CHIP_WIDTH - 1 : 0] t_param_wr_to_rd_diff_chip;
input [T_PARAM_RD_TO_RD_WIDTH - 1 : 0] t_param_rd_to_rd;
input [T_PARAM_RD_TO_RD_DIFF_CHIP_WIDTH - 1 : 0] t_param_rd_to_rd_diff_chip;
input [T_PARAM_RD_TO_WR_WIDTH - 1 : 0] t_param_rd_to_wr;
input [T_PARAM_RD_TO_WR_BC_WIDTH - 1 : 0] t_param_rd_to_wr_bc;
input [T_PARAM_RD_TO_WR_DIFF_CHIP_WIDTH - 1 : 0] t_param_rd_to_wr_diff_chip;
input [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_write;
input [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_read;
input [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_burst_chop;
input [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_burst_terminate;
input [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_activate;
input [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_precharge;
input [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] bg_to_chip;
input [CFG_INT_SIZE_WIDTH - 1 : 0] bg_effective_size;
input bg_interrupt_ready;
input [CFG_MEM_IF_CS_WIDTH - 1 : 0] cmd_gen_chipsel;
input [(CFG_CTL_TBP_NUM * CFG_MEM_IF_CS_WIDTH) - 1 : 0] tbp_chipsel;
input [CFG_CTL_TBP_NUM - 1 : 0] tbp_load;
input [CFG_MEM_IF_CHIP - 1 : 0] stall_chip;
output [CFG_CTL_TBP_NUM - 1 : 0] can_activate;
output [CFG_CTL_TBP_NUM - 1 : 0] can_precharge;
output [CFG_CTL_TBP_NUM - 1 : 0] can_read;
output [CFG_CTL_TBP_NUM - 1 : 0] can_write;
//--------------------------------------------------------------------------------------------------------
//
// [START] Register & Wires
//
//--------------------------------------------------------------------------------------------------------
// General
localparam RANK_TIMER_COUNTER_OFFSET = (CFG_RANK_TIMER_OUTPUT_REG) ? ((CFG_REG_GRANT) ? 4 : 3) : ((CFG_REG_GRANT) ? 3 : 2);
localparam RANK_TIMER_TFAW_OFFSET = (CFG_RANK_TIMER_OUTPUT_REG) ? ((CFG_REG_GRANT) ? 2 : 1) : ((CFG_REG_GRANT) ? 1 : 0);
localparam ENABLE_BETTER_TRRD_EFFICIENCY = 0; // ONLY set to '1' when CFG_RANK_TIMER_OUTPUT_REG is enabled, else it will fail
wire one = 1'b1;
wire zero = 1'b0;
// Timing Parameter Comparison Logic
reg less_than_1_act_to_act_diff_bank;
reg less_than_2_act_to_act_diff_bank;
reg less_than_3_act_to_act_diff_bank;
reg less_than_4_act_to_act_diff_bank;
reg less_than_4_four_act_to_act;
reg less_than_1_rd_to_rd;
reg less_than_1_rd_to_wr;
reg less_than_1_wr_to_wr;
reg less_than_1_wr_to_rd;
reg less_than_1_rd_to_wr_bc;
reg less_than_1_wr_to_rd_bc;
reg less_than_1_rd_to_rd_diff_chip;
reg less_than_1_rd_to_wr_diff_chip;
reg less_than_1_wr_to_wr_diff_chip;
reg less_than_1_wr_to_rd_diff_chip;
reg less_than_2_rd_to_rd;
reg less_than_2_rd_to_wr;
reg less_than_2_wr_to_wr;
reg less_than_2_wr_to_rd;
reg less_than_2_rd_to_wr_bc;
reg less_than_2_wr_to_rd_bc;
reg less_than_2_rd_to_rd_diff_chip;
reg less_than_2_rd_to_wr_diff_chip;
reg less_than_2_wr_to_wr_diff_chip;
reg less_than_2_wr_to_rd_diff_chip;
reg less_than_3_rd_to_rd;
reg less_than_3_rd_to_wr;
reg less_than_3_wr_to_wr;
reg less_than_3_wr_to_rd;
reg less_than_3_rd_to_wr_bc;
reg less_than_3_wr_to_rd_bc;
reg less_than_3_rd_to_rd_diff_chip;
reg less_than_3_rd_to_wr_diff_chip;
reg less_than_3_wr_to_wr_diff_chip;
reg less_than_3_wr_to_rd_diff_chip;
reg less_than_4_rd_to_rd;
reg less_than_4_rd_to_wr;
reg less_than_4_wr_to_wr;
reg less_than_4_wr_to_rd;
reg less_than_4_rd_to_wr_bc;
reg less_than_4_wr_to_rd_bc;
reg less_than_4_rd_to_rd_diff_chip;
reg less_than_4_rd_to_wr_diff_chip;
reg less_than_4_wr_to_wr_diff_chip;
reg less_than_4_wr_to_rd_diff_chip;
reg more_than_3_rd_to_rd;
reg more_than_3_rd_to_wr;
reg more_than_3_wr_to_wr;
reg more_than_3_wr_to_rd;
reg more_than_3_rd_to_wr_bc;
reg more_than_3_wr_to_rd_bc;
reg more_than_3_rd_to_rd_diff_chip;
reg more_than_3_rd_to_wr_diff_chip;
reg more_than_3_wr_to_wr_diff_chip;
reg more_than_3_wr_to_rd_diff_chip;
reg less_than_xn1_act_to_act_diff_bank;
reg less_than_xn1_rd_to_rd;
reg less_than_xn1_rd_to_wr;
reg less_than_xn1_wr_to_wr;
reg less_than_xn1_wr_to_rd;
reg less_than_xn1_rd_to_wr_bc;
reg less_than_xn1_wr_to_rd_bc;
reg less_than_xn1_rd_to_rd_diff_chip;
reg less_than_xn1_rd_to_wr_diff_chip;
reg less_than_xn1_wr_to_wr_diff_chip;
reg less_than_xn1_wr_to_rd_diff_chip;
reg less_than_x0_act_to_act_diff_bank;
reg less_than_x0_rd_to_rd;
reg less_than_x0_rd_to_wr;
reg less_than_x0_wr_to_wr;
reg less_than_x0_wr_to_rd;
reg less_than_x0_rd_to_wr_bc;
reg less_than_x0_wr_to_rd_bc;
reg less_than_x0_rd_to_rd_diff_chip;
reg less_than_x0_rd_to_wr_diff_chip;
reg less_than_x0_wr_to_wr_diff_chip;
reg less_than_x0_wr_to_rd_diff_chip;
reg less_than_x1_act_to_act_diff_bank;
reg less_than_x1_rd_to_rd;
reg less_than_x1_rd_to_wr;
reg less_than_x1_wr_to_wr;
reg less_than_x1_wr_to_rd;
reg less_than_x1_rd_to_wr_bc;
reg less_than_x1_wr_to_rd_bc;
reg less_than_x1_rd_to_rd_diff_chip;
reg less_than_x1_rd_to_wr_diff_chip;
reg less_than_x1_wr_to_wr_diff_chip;
reg less_than_x1_wr_to_rd_diff_chip;
// Input
reg int_do_activate;
reg int_do_precharge;
reg int_do_burst_chop;
reg int_do_burst_terminate;
reg int_do_write;
reg int_do_read;
reg [CFG_MEM_IF_CHIP - 1 : 0] int_to_chip_r;
reg [CFG_MEM_IF_CHIP - 1 : 0] int_to_chip_c;
reg [CFG_INT_SIZE_WIDTH - 1 : 0] int_effective_size;
reg int_interrupt_ready;
// Activate Monitor
localparam ACTIVATE_COUNTER_WIDTH = T_PARAM_ACT_TO_ACT_DIFF_BANK_WIDTH;
localparam ACTIVATE_COMMAND_WIDTH = 3;
localparam NUM_OF_TFAW_SHIFT_REG = 2 ** T_PARAM_FOUR_ACT_TO_ACT_WIDTH;
reg [CFG_MEM_IF_CHIP - 1 : 0] act_tfaw_ready;
reg [CFG_MEM_IF_CHIP - 1 : 0] act_tfaw_ready_combi;
reg [CFG_MEM_IF_CHIP - 1 : 0] act_trrd_ready;
reg [CFG_MEM_IF_CHIP - 1 : 0] act_trrd_ready_combi;
reg [CFG_MEM_IF_CHIP - 1 : 0] act_ready;
wire [ACTIVATE_COMMAND_WIDTH - 1 : 0] act_tfaw_cmd_count [CFG_MEM_IF_CHIP - 1 : 0];
// Read/Write Monitor
localparam IDLE = 32'h49444C45;
localparam WR = 32'h20205752;
localparam RD = 32'h20205244;
localparam RDWR_COUNTER_WIDTH = (T_PARAM_RD_TO_WR_WIDTH > T_PARAM_WR_TO_RD_WIDTH) ? T_PARAM_RD_TO_WR_WIDTH : T_PARAM_WR_TO_RD_WIDTH;
reg [CFG_INT_SIZE_WIDTH - 1 : 0] max_local_burst_size;
reg [T_PARAM_RD_TO_WR_WIDTH - 1 : 0] effective_rd_to_wr_combi;
reg [T_PARAM_RD_TO_WR_DIFF_CHIP_WIDTH - 1 : 0] effective_rd_to_wr_diff_chip_combi;
reg [T_PARAM_WR_TO_RD_WIDTH - 1 : 0] effective_wr_to_rd_combi;
reg [T_PARAM_WR_TO_RD_DIFF_CHIP_WIDTH - 1 : 0] effective_wr_to_rd_diff_chip_combi;
reg [T_PARAM_RD_TO_WR_WIDTH - 1 : 0] effective_rd_to_wr;
reg [T_PARAM_RD_TO_WR_DIFF_CHIP_WIDTH - 1 : 0] effective_rd_to_wr_diff_chip;
reg [T_PARAM_WR_TO_RD_WIDTH - 1 : 0] effective_wr_to_rd;
reg [T_PARAM_WR_TO_RD_DIFF_CHIP_WIDTH - 1 : 0] effective_wr_to_rd_diff_chip;
reg [CFG_MEM_IF_CHIP - 1 : 0] read_ready;
reg [CFG_MEM_IF_CHIP - 1 : 0] write_ready;
// Precharge Monitor
reg [CFG_MEM_IF_CHIP - 1 : 0] pch_ready;
// Output
reg [CFG_CTL_TBP_NUM - 1 : 0] int_can_activate;
reg [CFG_CTL_TBP_NUM - 1 : 0] int_can_precharge;
reg [CFG_CTL_TBP_NUM - 1 : 0] int_can_read;
reg [CFG_CTL_TBP_NUM - 1 : 0] int_can_write;
reg [CFG_CTL_TBP_NUM - 1 : 0] can_activate;
reg [CFG_CTL_TBP_NUM - 1 : 0] can_precharge;
reg [CFG_CTL_TBP_NUM - 1 : 0] can_read;
reg [CFG_CTL_TBP_NUM - 1 : 0] can_write;
reg [T_PARAM_FOUR_ACT_TO_ACT_WIDTH - 1 : 0] sel_act_tfaw_shift_out_point;
//--------------------------------------------------------------------------------------------------------
//
// [END] Register & Wires
//
//--------------------------------------------------------------------------------------------------------
//--------------------------------------------------------------------------------------------------------
//
// [START] Input
//
//--------------------------------------------------------------------------------------------------------
// Do activate
always @ (*)
begin
int_do_activate = |bg_do_activate;
end
// Do precharge
always @ (*)
begin
int_do_precharge = |bg_do_precharge;
end
//Do burst chop
always @ (*)
begin
int_do_burst_chop = |bg_do_burst_chop;
end
//Do burst terminate
always @ (*)
begin
int_do_burst_terminate = |bg_do_burst_terminate;
end
// Do write
always @ (*)
begin
int_do_write = |bg_do_write;
end
// Do read
always @ (*)
begin
int_do_read = |bg_do_read;
end
// To chip
always @ (*)
begin
// _r for row command and _c for column command
if (CFG_CTL_ARBITER_TYPE == "COLROW")
begin
int_to_chip_c = bg_to_chip [CFG_MEM_IF_CHIP - 1 : 0 ];
int_to_chip_r = bg_to_chip [2 * CFG_MEM_IF_CHIP - 1 : CFG_MEM_IF_CHIP];
end
else if (CFG_CTL_ARBITER_TYPE == "ROWCOL")
begin
int_to_chip_r = bg_to_chip [CFG_MEM_IF_CHIP - 1 : 0 ];
int_to_chip_c = bg_to_chip [2 * CFG_MEM_IF_CHIP - 1 : CFG_MEM_IF_CHIP];
end
end
// Effective size
always @ (*)
begin
int_effective_size = bg_effective_size;
end
// Interrupt ready
always @ (*)
begin
int_interrupt_ready = bg_interrupt_ready;
end
//--------------------------------------------------------------------------------------------------------
//
// [END] Input
//
//--------------------------------------------------------------------------------------------------------
//--------------------------------------------------------------------------------------------------------
//
// [START] Output
//
//--------------------------------------------------------------------------------------------------------
generate
genvar x_cs;
for (x_cs = 0; x_cs < CFG_CTL_TBP_NUM;x_cs = x_cs + 1)
begin : can_logic_per_chip
reg [CFG_MEM_IF_CS_WIDTH - 1 : 0] chip_addr;
always @ (*)
begin
if (CFG_RANK_TIMER_OUTPUT_REG && tbp_load [x_cs])
begin
chip_addr = cmd_gen_chipsel;
end
else
begin
chip_addr = tbp_chipsel [(x_cs + 1) * CFG_MEM_IF_CS_WIDTH - 1 : x_cs * CFG_MEM_IF_CS_WIDTH];
end
end
if (CFG_RANK_TIMER_OUTPUT_REG)
begin
always @ (*)
begin
can_activate [x_cs] = int_can_activate [x_cs] ;
can_precharge [x_cs] = int_can_precharge [x_cs] ;
can_read [x_cs] = int_can_read [x_cs] & int_interrupt_ready;
can_write [x_cs] = int_can_write [x_cs] & int_interrupt_ready;
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
int_can_activate [x_cs] <= 1'b0;
end
else
begin
if (stall_chip [chip_addr])
begin
int_can_activate [x_cs] <= 1'b0;
end
else if (int_do_activate && int_to_chip_r [chip_addr] && !ENABLE_BETTER_TRRD_EFFICIENCY)
begin
int_can_activate [x_cs] <= 1'b0;
end
else
begin
int_can_activate [x_cs] <= act_ready [chip_addr];
end
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
int_can_precharge [x_cs] <= 1'b0;
end
else
begin
if (stall_chip [chip_addr])
begin
int_can_precharge [x_cs] <= 1'b0;
end
else
begin
int_can_precharge [x_cs] <= pch_ready [chip_addr];
end
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
int_can_read [x_cs] <= 1'b0;
end
else
begin
if (stall_chip [chip_addr])
begin
int_can_read [x_cs] <= 1'b0;
end
else if (int_do_write)
begin
if (int_to_chip_c [chip_addr]) // to same chip addr as compared to current TBP
begin
if (int_do_burst_chop && more_than_3_wr_to_rd_bc)
begin
int_can_read [x_cs] <= 1'b0;
end
else if (!int_do_burst_chop && more_than_3_wr_to_rd)
begin
int_can_read [x_cs] <= 1'b0;
end
else
begin
int_can_read [x_cs] <= 1'b1;
end
end
else // to other chip addr as compared to current TBP
begin
int_can_read [x_cs] <= 1'b0;
end
end
else if (int_do_read)
begin
if (int_to_chip_c [chip_addr]) // to same chip addr as compared to current TBP
begin
if (more_than_3_rd_to_rd)
begin
int_can_read [x_cs] <= 1'b0;
end
else
begin
int_can_read [x_cs] <= 1'b1;
end
end
else // to other chip addr as compared to current TBP
begin
int_can_read [x_cs] <= 1'b0;
end
end
else
begin
int_can_read [x_cs] <= read_ready [chip_addr];
end
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
int_can_write [x_cs] <= 1'b0;
end
else
begin
if (stall_chip [chip_addr])
begin
int_can_write [x_cs] <= 1'b0;
end
else if (int_do_read)
begin
if (int_to_chip_c [chip_addr]) // to same chip addr as compared to current TBP
begin
if (int_do_burst_chop && more_than_3_rd_to_wr_bc)
begin
int_can_write [x_cs] <= 1'b0;
end
else if (!int_do_burst_chop && more_than_3_rd_to_wr)
begin
int_can_write [x_cs] <= 1'b0;
end
else
begin
int_can_write [x_cs] <= 1'b1;
end
end
else // to other chip addr as compared to current TBP
begin
int_can_write [x_cs] <= 1'b0;
end
end
else if (int_do_write)
begin
if (int_to_chip_c [chip_addr]) // to same chip addr as compared to current TBP
begin
if (more_than_3_wr_to_wr)
begin
int_can_write [x_cs] <= 1'b0;
end
else
begin
int_can_write [x_cs] <= 1'b1;
end
end
else // to other chip addr as compared to current TBP
begin
int_can_write [x_cs] <= 1'b0;
end
end
else
begin
int_can_write [x_cs] <= write_ready [chip_addr];
end
end
end
end
else
begin
// Can activate
always @ (*)
begin
can_activate [x_cs] = act_ready [chip_addr];
end
// Can precharge
always @ (*)
begin
can_precharge [x_cs] = pch_ready [chip_addr];
end
// Can read
always @ (*)
begin
can_read [x_cs] = read_ready [chip_addr];
end
// Can write
always @ (*)
begin
can_write [x_cs] = write_ready [chip_addr];
end
end
end
endgenerate
//--------------------------------------------------------------------------------------------------------
//
// [END] Output
//
//--------------------------------------------------------------------------------------------------------
//--------------------------------------------------------------------------------------------------------
//
// [START] Timing Parameter Comparison Logic
//
//--------------------------------------------------------------------------------------------------------
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
less_than_1_act_to_act_diff_bank <= 1'b0;
end
else
begin
if (t_param_act_to_act_diff_bank <= 1)
less_than_1_act_to_act_diff_bank <= 1'b1;
else
less_than_1_act_to_act_diff_bank <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
less_than_2_act_to_act_diff_bank <= 1'b0;
end
else
begin
if (t_param_act_to_act_diff_bank <= 2)
less_than_2_act_to_act_diff_bank <= 1'b1;
else
less_than_2_act_to_act_diff_bank <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
less_than_3_act_to_act_diff_bank <= 1'b0;
end
else
begin
if (t_param_act_to_act_diff_bank <= 3)
less_than_3_act_to_act_diff_bank <= 1'b1;
else
less_than_3_act_to_act_diff_bank <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
less_than_4_act_to_act_diff_bank <= 1'b0;
end
else
begin
if (t_param_act_to_act_diff_bank <= 4)
less_than_4_act_to_act_diff_bank <= 1'b1;
else
less_than_4_act_to_act_diff_bank <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
less_than_4_four_act_to_act <= 1'b0;
end
else
begin
if (t_param_four_act_to_act <= 4)
less_than_4_four_act_to_act <= 1'b1;
else
less_than_4_four_act_to_act <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
less_than_1_rd_to_rd <= 1'b0;
end
else
begin
if (t_param_rd_to_rd <= 1)
less_than_1_rd_to_rd <= 1'b1;
else
less_than_1_rd_to_rd <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
less_than_1_rd_to_wr <= 1'b0;
end
else
begin
if (t_param_rd_to_wr <= 1)
less_than_1_rd_to_wr <= 1'b1;
else
less_than_1_rd_to_wr <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
less_than_1_wr_to_wr <= 1'b0;
end
else
begin
if (t_param_wr_to_wr <= 1)
less_than_1_wr_to_wr <= 1'b1;
else
less_than_1_wr_to_wr <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
less_than_1_wr_to_rd <= 1'b0;
end
else
begin
if (t_param_wr_to_rd <= 1)
less_than_1_wr_to_rd <= 1'b1;
else
less_than_1_wr_to_rd <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
less_than_1_rd_to_wr_bc <= 1'b0;
end
else
begin
if (t_param_rd_to_wr_bc <= 1)
less_than_1_rd_to_wr_bc <= 1'b1;
else
less_than_1_rd_to_wr_bc <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
less_than_1_wr_to_rd_bc <= 1'b0;
end
else
begin
if (t_param_wr_to_rd_bc <= 1)
less_than_1_wr_to_rd_bc <= 1'b1;
else
less_than_1_wr_to_rd_bc <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
less_than_1_rd_to_rd_diff_chip <= 1'b0;
end
else
begin
if (t_param_rd_to_rd_diff_chip <= 1)
less_than_1_rd_to_rd_diff_chip <= 1'b1;
else
less_than_1_rd_to_rd_diff_chip <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
less_than_1_rd_to_wr_diff_chip <= 1'b0;
end
else
begin
if (t_param_rd_to_wr_diff_chip <= 1)
less_than_1_rd_to_wr_diff_chip <= 1'b1;
else
less_than_1_rd_to_wr_diff_chip <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
less_than_1_wr_to_wr_diff_chip <= 1'b0;
end
else
begin
if (t_param_wr_to_wr_diff_chip <= 1)
less_than_1_wr_to_wr_diff_chip <= 1'b1;
else
less_than_1_wr_to_wr_diff_chip <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
less_than_1_wr_to_rd_diff_chip <= 1'b0;
end
else
begin
if (t_param_wr_to_rd_diff_chip <= 1)
less_than_1_wr_to_rd_diff_chip <= 1'b1;
else
less_than_1_wr_to_rd_diff_chip <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
less_than_2_rd_to_rd <= 1'b0;
end
else
begin
if (t_param_rd_to_rd <= 2)
less_than_2_rd_to_rd <= 1'b1;
else
less_than_2_rd_to_rd <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
less_than_2_rd_to_wr <= 1'b0;
end
else
begin
if (t_param_rd_to_wr <= 2)
less_than_2_rd_to_wr <= 1'b1;
else
less_than_2_rd_to_wr <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
less_than_2_wr_to_wr <= 1'b0;
end
else
begin
if (t_param_wr_to_wr <= 2)
less_than_2_wr_to_wr <= 1'b1;
else
less_than_2_wr_to_wr <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
less_than_2_wr_to_rd <= 1'b0;
end
else
begin
if (t_param_wr_to_rd <= 2)
less_than_2_wr_to_rd <= 1'b1;
else
less_than_2_wr_to_rd <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
less_than_2_rd_to_wr_bc <= 1'b0;
end
else
begin
if (t_param_rd_to_wr_bc <= 2)
less_than_2_rd_to_wr_bc <= 1'b1;
else
less_than_2_rd_to_wr_bc <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
less_than_2_wr_to_rd_bc <= 1'b0;
end
else
begin
if (t_param_wr_to_rd_bc <= 2)
less_than_2_wr_to_rd_bc <= 1'b1;
else
less_than_2_wr_to_rd_bc <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
less_than_2_rd_to_rd_diff_chip <= 1'b0;
end
else
begin
if (t_param_rd_to_rd_diff_chip <= 2)
less_than_2_rd_to_rd_diff_chip <= 1'b1;
else
less_than_2_rd_to_rd_diff_chip <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
less_than_2_rd_to_wr_diff_chip <= 1'b0;
end
else
begin
if (t_param_rd_to_wr_diff_chip <= 2)
less_than_2_rd_to_wr_diff_chip <= 1'b1;
else
less_than_2_rd_to_wr_diff_chip <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
less_than_2_wr_to_wr_diff_chip <= 1'b0;
end
else
begin
if (t_param_wr_to_wr_diff_chip <= 2)
less_than_2_wr_to_wr_diff_chip <= 1'b1;
else
less_than_2_wr_to_wr_diff_chip <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
less_than_2_wr_to_rd_diff_chip <= 1'b0;
end
else
begin
if (t_param_wr_to_rd_diff_chip <= 2)
less_than_2_wr_to_rd_diff_chip <= 1'b1;
else
less_than_2_wr_to_rd_diff_chip <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
less_than_3_rd_to_rd <= 1'b0;
end
else
begin
if (t_param_rd_to_rd <= 3)
less_than_3_rd_to_rd <= 1'b1;
else
less_than_3_rd_to_rd <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
less_than_3_rd_to_wr <= 1'b0;
end
else
begin
if (t_param_rd_to_wr <= 3)
less_than_3_rd_to_wr <= 1'b1;
else
less_than_3_rd_to_wr <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
less_than_3_wr_to_wr <= 1'b0;
end
else
begin
if (t_param_wr_to_wr <= 3)
less_than_3_wr_to_wr <= 1'b1;
else
less_than_3_wr_to_wr <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
less_than_3_wr_to_rd <= 1'b0;
end
else
begin
if (t_param_wr_to_rd <= 3)
less_than_3_wr_to_rd <= 1'b1;
else
less_than_3_wr_to_rd <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
less_than_3_rd_to_wr_bc <= 1'b0;
end
else
begin
if (t_param_rd_to_wr_bc <= 3)
less_than_3_rd_to_wr_bc <= 1'b1;
else
less_than_3_rd_to_wr_bc <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
less_than_3_wr_to_rd_bc <= 1'b0;
end
else
begin
if (t_param_wr_to_rd_bc <= 3)
less_than_3_wr_to_rd_bc <= 1'b1;
else
less_than_3_wr_to_rd_bc <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
less_than_3_rd_to_rd_diff_chip <= 1'b0;
end
else
begin
if (t_param_rd_to_rd_diff_chip <= 3)
less_than_3_rd_to_rd_diff_chip <= 1'b1;
else
less_than_3_rd_to_rd_diff_chip <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
less_than_3_rd_to_wr_diff_chip <= 1'b0;
end
else
begin
if (t_param_rd_to_wr_diff_chip <= 3)
less_than_3_rd_to_wr_diff_chip <= 1'b1;
else
less_than_3_rd_to_wr_diff_chip <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
less_than_3_wr_to_wr_diff_chip <= 1'b0;
end
else
begin
if (t_param_wr_to_wr_diff_chip <= 3)
less_than_3_wr_to_wr_diff_chip <= 1'b1;
else
less_than_3_wr_to_wr_diff_chip <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
less_than_3_wr_to_rd_diff_chip <= 1'b0;
end
else
begin
if (t_param_wr_to_rd_diff_chip <= 3)
less_than_3_wr_to_rd_diff_chip <= 1'b1;
else
less_than_3_wr_to_rd_diff_chip <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
less_than_4_rd_to_rd <= 1'b0;
end
else
begin
if (t_param_rd_to_rd <= 4)
less_than_4_rd_to_rd <= 1'b1;
else
less_than_4_rd_to_rd <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
less_than_4_rd_to_wr <= 1'b0;
end
else
begin
if (t_param_rd_to_wr <= 4)
less_than_4_rd_to_wr <= 1'b1;
else
less_than_4_rd_to_wr <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
less_than_4_wr_to_wr <= 1'b0;
end
else
begin
if (t_param_wr_to_wr <= 4)
less_than_4_wr_to_wr <= 1'b1;
else
less_than_4_wr_to_wr <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
less_than_4_wr_to_rd <= 1'b0;
end
else
begin
if (t_param_wr_to_rd <= 4)
less_than_4_wr_to_rd <= 1'b1;
else
less_than_4_wr_to_rd <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
less_than_4_rd_to_wr_bc <= 1'b0;
end
else
begin
if (t_param_rd_to_wr_bc <= 4)
less_than_4_rd_to_wr_bc <= 1'b1;
else
less_than_4_rd_to_wr_bc <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
less_than_4_wr_to_rd_bc <= 1'b0;
end
else
begin
if (t_param_wr_to_rd_bc <= 4)
less_than_4_wr_to_rd_bc <= 1'b1;
else
less_than_4_wr_to_rd_bc <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
less_than_4_rd_to_rd_diff_chip <= 1'b0;
end
else
begin
if (t_param_rd_to_rd_diff_chip <= 4)
less_than_4_rd_to_rd_diff_chip <= 1'b1;
else
less_than_4_rd_to_rd_diff_chip <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
less_than_4_rd_to_wr_diff_chip <= 1'b0;
end
else
begin
if (t_param_rd_to_wr_diff_chip <= 4)
less_than_4_rd_to_wr_diff_chip <= 1'b1;
else
less_than_4_rd_to_wr_diff_chip <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
less_than_4_wr_to_wr_diff_chip <= 1'b0;
end
else
begin
if (t_param_wr_to_wr_diff_chip <= 4)
less_than_4_wr_to_wr_diff_chip <= 1'b1;
else
less_than_4_wr_to_wr_diff_chip <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
less_than_4_wr_to_rd_diff_chip <= 1'b0;
end
else
begin
if (t_param_wr_to_rd_diff_chip <= 4)
less_than_4_wr_to_rd_diff_chip <= 1'b1;
else
less_than_4_wr_to_rd_diff_chip <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
more_than_3_rd_to_rd <= 1'b0;
end
else
begin
if (t_param_rd_to_rd >= 3)
more_than_3_rd_to_rd <= 1'b1;
else
more_than_3_rd_to_rd <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
more_than_3_rd_to_wr <= 1'b0;
end
else
begin
if (t_param_rd_to_wr >= 3)
more_than_3_rd_to_wr <= 1'b1;
else
more_than_3_rd_to_wr <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
more_than_3_wr_to_wr <= 1'b0;
end
else
begin
if (t_param_wr_to_wr >= 3)
more_than_3_wr_to_wr <= 1'b1;
else
more_than_3_wr_to_wr <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
more_than_3_wr_to_rd <= 1'b0;
end
else
begin
if (t_param_wr_to_rd >= 3)
more_than_3_wr_to_rd <= 1'b1;
else
more_than_3_wr_to_rd <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
more_than_3_rd_to_wr_bc <= 1'b0;
end
else
begin
if (t_param_rd_to_wr_bc >= 3)
more_than_3_rd_to_wr_bc <= 1'b1;
else
more_than_3_rd_to_wr_bc <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
more_than_3_wr_to_rd_bc <= 1'b0;
end
else
begin
if (t_param_wr_to_rd_bc >= 3)
more_than_3_wr_to_rd_bc <= 1'b1;
else
more_than_3_wr_to_rd_bc <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
more_than_3_rd_to_rd_diff_chip <= 1'b0;
end
else
begin
if (t_param_rd_to_rd_diff_chip >= 3)
more_than_3_rd_to_rd_diff_chip <= 1'b1;
else
more_than_3_rd_to_rd_diff_chip <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
more_than_3_rd_to_wr_diff_chip <= 1'b0;
end
else
begin
if (t_param_rd_to_wr_diff_chip >= 3)
more_than_3_rd_to_wr_diff_chip <= 1'b1;
else
more_than_3_rd_to_wr_diff_chip <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
more_than_3_wr_to_wr_diff_chip <= 1'b0;
end
else
begin
if (t_param_wr_to_wr_diff_chip >= 3)
more_than_3_wr_to_wr_diff_chip <= 1'b1;
else
more_than_3_wr_to_wr_diff_chip <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
more_than_3_wr_to_rd_diff_chip <= 1'b0;
end
else
begin
if (t_param_wr_to_rd_diff_chip >= 3)
more_than_3_wr_to_rd_diff_chip <= 1'b1;
else
more_than_3_wr_to_rd_diff_chip <= 1'b0;
end
end
generate
begin
if (CFG_REG_GRANT)
begin
always @ (*)
begin
if (CFG_RANK_TIMER_OUTPUT_REG)
begin
less_than_xn1_act_to_act_diff_bank = less_than_2_act_to_act_diff_bank;
less_than_xn1_rd_to_rd = less_than_2_rd_to_rd;
less_than_xn1_rd_to_wr = less_than_2_rd_to_wr;
less_than_xn1_wr_to_wr = less_than_2_wr_to_wr;
less_than_xn1_wr_to_rd = less_than_2_wr_to_rd;
less_than_xn1_rd_to_wr_bc = less_than_2_rd_to_wr_bc;
less_than_xn1_wr_to_rd_bc = less_than_2_wr_to_rd_bc;
less_than_xn1_rd_to_rd_diff_chip = less_than_2_rd_to_rd_diff_chip;
less_than_xn1_rd_to_wr_diff_chip = less_than_2_rd_to_wr_diff_chip;
less_than_xn1_wr_to_wr_diff_chip = less_than_2_wr_to_wr_diff_chip;
less_than_xn1_wr_to_rd_diff_chip = less_than_2_wr_to_rd_diff_chip;
less_than_x0_act_to_act_diff_bank = less_than_3_act_to_act_diff_bank;
less_than_x0_rd_to_rd = less_than_3_rd_to_rd;
less_than_x0_rd_to_wr = less_than_3_rd_to_wr;
less_than_x0_wr_to_wr = less_than_3_wr_to_wr;
less_than_x0_wr_to_rd = less_than_3_wr_to_rd;
less_than_x0_rd_to_wr_bc = less_than_3_rd_to_wr_bc;
less_than_x0_wr_to_rd_bc = less_than_3_wr_to_rd_bc;
less_than_x0_rd_to_rd_diff_chip = less_than_3_rd_to_rd_diff_chip;
less_than_x0_rd_to_wr_diff_chip = less_than_3_rd_to_wr_diff_chip;
less_than_x0_wr_to_wr_diff_chip = less_than_3_wr_to_wr_diff_chip;
less_than_x0_wr_to_rd_diff_chip = less_than_3_wr_to_rd_diff_chip;
less_than_x1_act_to_act_diff_bank = less_than_4_act_to_act_diff_bank;
less_than_x1_rd_to_rd = less_than_4_rd_to_rd;
less_than_x1_rd_to_wr = less_than_4_rd_to_wr;
less_than_x1_wr_to_wr = less_than_4_wr_to_wr;
less_than_x1_wr_to_rd = less_than_4_wr_to_rd;
less_than_x1_rd_to_wr_bc = less_than_4_rd_to_wr_bc;
less_than_x1_wr_to_rd_bc = less_than_4_wr_to_rd_bc;
less_than_x1_rd_to_rd_diff_chip = less_than_4_rd_to_rd_diff_chip;
less_than_x1_rd_to_wr_diff_chip = less_than_4_rd_to_wr_diff_chip;
less_than_x1_wr_to_wr_diff_chip = less_than_4_wr_to_wr_diff_chip;
less_than_x1_wr_to_rd_diff_chip = less_than_4_wr_to_rd_diff_chip;
end
else
begin
// Doesn't matter for less_than_xn1_* if CFG_RANK_TIMER_OUTPUT_REG is '0'
less_than_xn1_act_to_act_diff_bank = less_than_2_act_to_act_diff_bank;
less_than_xn1_rd_to_rd = less_than_2_rd_to_rd;
less_than_xn1_rd_to_wr = less_than_2_rd_to_wr;
less_than_xn1_wr_to_wr = less_than_2_wr_to_wr;
less_than_xn1_wr_to_rd = less_than_2_wr_to_rd;
less_than_xn1_rd_to_wr_bc = less_than_2_rd_to_wr_bc;
less_than_xn1_wr_to_rd_bc = less_than_2_wr_to_rd_bc;
less_than_xn1_rd_to_rd_diff_chip = less_than_2_rd_to_rd_diff_chip;
less_than_xn1_rd_to_wr_diff_chip = less_than_2_rd_to_wr_diff_chip;
less_than_xn1_wr_to_wr_diff_chip = less_than_2_wr_to_wr_diff_chip;
less_than_xn1_wr_to_rd_diff_chip = less_than_2_wr_to_rd_diff_chip;
less_than_x0_act_to_act_diff_bank = less_than_2_act_to_act_diff_bank;
less_than_x0_rd_to_rd = less_than_2_rd_to_rd;
less_than_x0_rd_to_wr = less_than_2_rd_to_wr;
less_than_x0_wr_to_wr = less_than_2_wr_to_wr;
less_than_x0_wr_to_rd = less_than_2_wr_to_rd;
less_than_x0_rd_to_wr_bc = less_than_2_rd_to_wr_bc;
less_than_x0_wr_to_rd_bc = less_than_2_wr_to_rd_bc;
less_than_x0_rd_to_rd_diff_chip = less_than_2_rd_to_rd_diff_chip;
less_than_x0_rd_to_wr_diff_chip = less_than_2_rd_to_wr_diff_chip;
less_than_x0_wr_to_wr_diff_chip = less_than_2_wr_to_wr_diff_chip;
less_than_x0_wr_to_rd_diff_chip = less_than_2_wr_to_rd_diff_chip;
less_than_x1_act_to_act_diff_bank = less_than_3_act_to_act_diff_bank;
less_than_x1_rd_to_rd = less_than_3_rd_to_rd;
less_than_x1_rd_to_wr = less_than_3_rd_to_wr;
less_than_x1_wr_to_wr = less_than_3_wr_to_wr;
less_than_x1_wr_to_rd = less_than_3_wr_to_rd;
less_than_x1_rd_to_wr_bc = less_than_3_rd_to_wr_bc;
less_than_x1_wr_to_rd_bc = less_than_3_wr_to_rd_bc;
less_than_x1_rd_to_rd_diff_chip = less_than_3_rd_to_rd_diff_chip;
less_than_x1_rd_to_wr_diff_chip = less_than_3_rd_to_wr_diff_chip;
less_than_x1_wr_to_wr_diff_chip = less_than_3_wr_to_wr_diff_chip;
less_than_x1_wr_to_rd_diff_chip = less_than_3_wr_to_rd_diff_chip;
end
end
end
else
begin
always @ (*)
begin
if (CFG_RANK_TIMER_OUTPUT_REG)
begin
less_than_xn1_act_to_act_diff_bank = less_than_1_act_to_act_diff_bank;
less_than_xn1_rd_to_rd = less_than_1_rd_to_rd;
less_than_xn1_rd_to_wr = less_than_1_rd_to_wr;
less_than_xn1_wr_to_wr = less_than_1_wr_to_wr;
less_than_xn1_wr_to_rd = less_than_1_wr_to_rd;
less_than_xn1_rd_to_wr_bc = less_than_1_rd_to_wr_bc;
less_than_xn1_wr_to_rd_bc = less_than_1_wr_to_rd_bc;
less_than_xn1_rd_to_rd_diff_chip = less_than_1_rd_to_rd_diff_chip;
less_than_xn1_rd_to_wr_diff_chip = less_than_1_rd_to_wr_diff_chip;
less_than_xn1_wr_to_wr_diff_chip = less_than_1_wr_to_wr_diff_chip;
less_than_xn1_wr_to_rd_diff_chip = less_than_1_wr_to_rd_diff_chip;
less_than_x0_act_to_act_diff_bank = less_than_2_act_to_act_diff_bank;
less_than_x0_rd_to_rd = less_than_2_rd_to_rd;
less_than_x0_rd_to_wr = less_than_2_rd_to_wr;
less_than_x0_wr_to_wr = less_than_2_wr_to_wr;
less_than_x0_wr_to_rd = less_than_2_wr_to_rd;
less_than_x0_rd_to_wr_bc = less_than_2_rd_to_wr_bc;
less_than_x0_wr_to_rd_bc = less_than_2_wr_to_rd_bc;
less_than_x0_rd_to_rd_diff_chip = less_than_2_rd_to_rd_diff_chip;
less_than_x0_rd_to_wr_diff_chip = less_than_2_rd_to_wr_diff_chip;
less_than_x0_wr_to_wr_diff_chip = less_than_2_wr_to_wr_diff_chip;
less_than_x0_wr_to_rd_diff_chip = less_than_2_wr_to_rd_diff_chip;
less_than_x1_act_to_act_diff_bank = less_than_3_act_to_act_diff_bank;
less_than_x1_rd_to_rd = less_than_3_rd_to_rd;
less_than_x1_rd_to_wr = less_than_3_rd_to_wr;
less_than_x1_wr_to_wr = less_than_3_wr_to_wr;
less_than_x1_wr_to_rd = less_than_3_wr_to_rd;
less_than_x1_rd_to_wr_bc = less_than_3_rd_to_wr_bc;
less_than_x1_wr_to_rd_bc = less_than_3_wr_to_rd_bc;
less_than_x1_rd_to_rd_diff_chip = less_than_3_rd_to_rd_diff_chip;
less_than_x1_rd_to_wr_diff_chip = less_than_3_rd_to_wr_diff_chip;
less_than_x1_wr_to_wr_diff_chip = less_than_3_wr_to_wr_diff_chip;
less_than_x1_wr_to_rd_diff_chip = less_than_3_wr_to_rd_diff_chip;
end
else
begin
// Doesn't matter for less_than_xn1_* if CFG_RANK_TIMER_OUTPUT_REG is '0'
less_than_xn1_act_to_act_diff_bank = less_than_1_act_to_act_diff_bank;
less_than_xn1_rd_to_rd = less_than_1_rd_to_rd;
less_than_xn1_rd_to_wr = less_than_1_rd_to_wr;
less_than_xn1_wr_to_wr = less_than_1_wr_to_wr;
less_than_xn1_wr_to_rd = less_than_1_wr_to_rd;
less_than_xn1_rd_to_wr_bc = less_than_1_rd_to_wr_bc;
less_than_xn1_wr_to_rd_bc = less_than_1_wr_to_rd_bc;
less_than_xn1_rd_to_rd_diff_chip = less_than_1_rd_to_rd_diff_chip;
less_than_xn1_rd_to_wr_diff_chip = less_than_1_rd_to_wr_diff_chip;
less_than_xn1_wr_to_wr_diff_chip = less_than_1_wr_to_wr_diff_chip;
less_than_xn1_wr_to_rd_diff_chip = less_than_1_wr_to_rd_diff_chip;
less_than_x0_act_to_act_diff_bank = less_than_1_act_to_act_diff_bank;
less_than_x0_rd_to_rd = less_than_1_rd_to_rd;
less_than_x0_rd_to_wr = less_than_1_rd_to_wr;
less_than_x0_wr_to_wr = less_than_1_wr_to_wr;
less_than_x0_wr_to_rd = less_than_1_wr_to_rd;
less_than_x0_rd_to_wr_bc = less_than_1_rd_to_wr_bc;
less_than_x0_wr_to_rd_bc = less_than_1_wr_to_rd_bc;
less_than_x0_rd_to_rd_diff_chip = less_than_1_rd_to_rd_diff_chip;
less_than_x0_rd_to_wr_diff_chip = less_than_1_rd_to_wr_diff_chip;
less_than_x0_wr_to_wr_diff_chip = less_than_1_wr_to_wr_diff_chip;
less_than_x0_wr_to_rd_diff_chip = less_than_1_wr_to_rd_diff_chip;
less_than_x1_act_to_act_diff_bank = less_than_2_act_to_act_diff_bank;
less_than_x1_rd_to_rd = less_than_2_rd_to_rd;
less_than_x1_rd_to_wr = less_than_2_rd_to_wr;
less_than_x1_wr_to_wr = less_than_2_wr_to_wr;
less_than_x1_wr_to_rd = less_than_2_wr_to_rd;
less_than_x1_rd_to_wr_bc = less_than_2_rd_to_wr_bc;
less_than_x1_wr_to_rd_bc = less_than_2_wr_to_rd_bc;
less_than_x1_rd_to_rd_diff_chip = less_than_2_rd_to_rd_diff_chip;
less_than_x1_rd_to_wr_diff_chip = less_than_2_rd_to_wr_diff_chip;
less_than_x1_wr_to_wr_diff_chip = less_than_2_wr_to_wr_diff_chip;
less_than_x1_wr_to_rd_diff_chip = less_than_2_wr_to_rd_diff_chip;
end
end
end
end
endgenerate
//--------------------------------------------------------------------------------------------------------
//
// [END] Timing Parameter Comparison Logic
//
//--------------------------------------------------------------------------------------------------------
//--------------------------------------------------------------------------------------------------------
//
// [START] Activate Monitor
//
// Monitors the following rank timing parameters:
//
// - tFAW, four activate window, only four activate is allowed in a specific timing window
// - tRRD, activate to activate different bank
//
//--------------------------------------------------------------------------------------------------------
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
sel_act_tfaw_shift_out_point <= 0;
end
else
begin
if (ENABLE_BETTER_TRRD_EFFICIENCY)
begin
sel_act_tfaw_shift_out_point <= t_param_four_act_to_act - RANK_TIMER_TFAW_OFFSET + 1;
end
else
begin
sel_act_tfaw_shift_out_point <= t_param_four_act_to_act - RANK_TIMER_TFAW_OFFSET;
end
end
end
generate
genvar t_cs;
genvar t_tfaw;
for (t_cs = 0;t_cs < CFG_MEM_IF_CHIP;t_cs = t_cs + 1)
begin : act_monitor_per_chip
//----------------------------------------------------------------------------------------------------
// tFAW Monitor
//----------------------------------------------------------------------------------------------------
reg [ACTIVATE_COMMAND_WIDTH - 1 : 0] act_tfaw_cmd_cnt;
reg [NUM_OF_TFAW_SHIFT_REG - 1 : 0] act_tfaw_shift_reg;
assign act_tfaw_cmd_count [t_cs] = act_tfaw_cmd_cnt;
// Shift register to keep track of tFAW
// Shift in -> n, n-1, n-2, n-3.......4, 3 -> Shift out
// Shift in '1' when there is an activate else shift in '0'
// Shift out every clock cycles
// Shift register [3]
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
act_tfaw_shift_reg [3] <= 1'b0;
end
else
begin
// Shift in '1' if there is an activate
// else shift in '0'
if (int_do_activate && int_to_chip_r [t_cs])
act_tfaw_shift_reg [3] <= 1'b1;
else
act_tfaw_shift_reg [3] <= 1'b0;
end
end
// Shift register [n : 3]
for (t_tfaw = 4;t_tfaw < NUM_OF_TFAW_SHIFT_REG;t_tfaw = t_tfaw + 1)
begin : tfaw_shift_register
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
act_tfaw_shift_reg [t_tfaw] <= 1'b0;
end
else
begin
act_tfaw_shift_reg [t_tfaw] <= act_tfaw_shift_reg [t_tfaw - 1];
end
end
end
// Activate command counter
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
act_tfaw_cmd_cnt <= 0;
end
else
begin
if (int_do_activate && int_to_chip_r [t_cs])
begin
if (act_tfaw_shift_reg [sel_act_tfaw_shift_out_point]) // Shift out when activate reaches tFAW point in shift register
act_tfaw_cmd_cnt <= act_tfaw_cmd_cnt;
else
act_tfaw_cmd_cnt <= act_tfaw_cmd_cnt + 1'b1;
end
else if (act_tfaw_shift_reg [sel_act_tfaw_shift_out_point]) // Shift out when activate reaches tFAW point in shift register
act_tfaw_cmd_cnt <= act_tfaw_cmd_cnt - 1'b1;
end
end
// tFAW ready signal
always @ (*)
begin
// If tFAW is lesser than 4, this means we can do back-to-back activate without tFAW constraint
if (less_than_4_four_act_to_act)
begin
act_tfaw_ready_combi [t_cs] = 1'b1;
end
else
begin
if (int_do_activate && int_to_chip_r [t_cs] && act_tfaw_cmd_cnt == 3'd3)
act_tfaw_ready_combi [t_cs] = 1'b0;
else if (act_tfaw_cmd_cnt < 3'd4)
act_tfaw_ready_combi [t_cs] = 1'b1;
else
act_tfaw_ready_combi [t_cs] = 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
act_tfaw_ready [t_cs] <= 1'b0;
end
else
begin
act_tfaw_ready [t_cs] <= act_tfaw_ready_combi [t_cs];
end
end
//----------------------------------------------------------------------------------------------------
// tRRD Monitor
//----------------------------------------------------------------------------------------------------
reg [ACTIVATE_COUNTER_WIDTH - 1 : 0] act_trrd_cnt;
// tRRD counter
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
act_trrd_cnt <= 0;
end
else
begin
if (int_do_activate && int_to_chip_r [t_cs])
begin
if (ENABLE_BETTER_TRRD_EFFICIENCY)
begin
act_trrd_cnt <= RANK_TIMER_COUNTER_OFFSET - 1;
end
else
begin
act_trrd_cnt <= RANK_TIMER_COUNTER_OFFSET;
end
end
else if (act_trrd_cnt != {ACTIVATE_COUNTER_WIDTH{1'b1}})
begin
act_trrd_cnt <= act_trrd_cnt + 1'b1;
end
end
end
// tRRD monitor
always @ (*)
begin
if (int_do_activate && int_to_chip_r [t_cs])
begin
if (!ENABLE_BETTER_TRRD_EFFICIENCY && less_than_x0_act_to_act_diff_bank)
act_trrd_ready_combi [t_cs] = 1'b1;
else if (ENABLE_BETTER_TRRD_EFFICIENCY && less_than_xn1_act_to_act_diff_bank)
act_trrd_ready_combi [t_cs] = 1'b1;
else
act_trrd_ready_combi [t_cs] = 1'b0;
end
else if (act_trrd_cnt >= t_param_act_to_act_diff_bank)
act_trrd_ready_combi [t_cs] = 1'b1;
else
act_trrd_ready_combi [t_cs] = 1'b0;
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
act_trrd_ready [t_cs] <= 1'b0;
end
else
begin
act_trrd_ready [t_cs] <= act_trrd_ready_combi [t_cs];
end
end
//----------------------------------------------------------------------------------------------------
// Overall activate ready
//----------------------------------------------------------------------------------------------------
always @ (*)
begin
if (!CFG_RANK_TIMER_OUTPUT_REG && stall_chip [t_cs])
begin
act_ready [t_cs] = 1'b0;
end
else
begin
if (ENABLE_BETTER_TRRD_EFFICIENCY)
begin
act_ready [t_cs] = act_trrd_ready_combi [t_cs] & act_tfaw_ready_combi [t_cs];
end
else
begin
act_ready [t_cs] = act_trrd_ready [t_cs] & act_tfaw_ready [t_cs];
end
end
end
end
endgenerate
//--------------------------------------------------------------------------------------------------------
//
// [END] Activate Monitor
//
//--------------------------------------------------------------------------------------------------------
//--------------------------------------------------------------------------------------------------------
//
// [START] Read/Write Monitor
//
// Monitors the following rank timing parameters:
//
// - Write to read timing parameter (tWTR)
// - Read to write timing parameter
//
// Missing Features:
//
// - Burst interrupt
// - Burst terminate
//
//--------------------------------------------------------------------------------------------------------
//----------------------------------------------------------------------------------------------------
// Effective Timing Parameters
// Only when burst interrupt option is enabled
//----------------------------------------------------------------------------------------------------
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
max_local_burst_size <= 0;
end
else
begin
max_local_burst_size <= cfg_burst_length / CFG_DWIDTH_RATIO;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
effective_rd_to_wr <= 0;
effective_rd_to_wr_diff_chip <= 0;
effective_wr_to_rd <= 0;
effective_wr_to_rd_diff_chip <= 0;
end
else
begin
if (int_do_burst_chop)
begin
effective_rd_to_wr <= t_param_rd_to_wr_bc;
effective_rd_to_wr_diff_chip <= t_param_rd_to_wr_diff_chip;
effective_wr_to_rd <= t_param_wr_to_rd_bc;
effective_wr_to_rd_diff_chip <= t_param_wr_to_rd_diff_chip;
end
else if (int_do_burst_terminate)
begin
if (t_param_rd_to_wr > (max_local_burst_size - int_effective_size))
effective_rd_to_wr <= t_param_rd_to_wr - (max_local_burst_size - int_effective_size);
else
effective_rd_to_wr <= 1'b1;
if (t_param_rd_to_wr_diff_chip > (max_local_burst_size - int_effective_size))
effective_rd_to_wr_diff_chip <= t_param_rd_to_wr_diff_chip - (max_local_burst_size - int_effective_size);
else
effective_rd_to_wr_diff_chip <= 1'b1;
if (t_param_wr_to_rd > (max_local_burst_size - int_effective_size))
effective_wr_to_rd <= t_param_wr_to_rd - (max_local_burst_size - int_effective_size);
else
effective_wr_to_rd <= 1'b1;
if (t_param_wr_to_rd_diff_chip > (max_local_burst_size - int_effective_size))
effective_wr_to_rd_diff_chip <= t_param_wr_to_rd_diff_chip - (max_local_burst_size - int_effective_size);
else
effective_wr_to_rd_diff_chip <= 1'b1;
end
end
end
//----------------------------------------------------------------------------------------------------
// Read / Write State Machine
//----------------------------------------------------------------------------------------------------
generate
genvar s_cs;
for (s_cs = 0;s_cs < CFG_MEM_IF_CHIP;s_cs = s_cs + 1)
begin : rdwr_monitor_per_chip
reg [31 : 0] rdwr_state;
reg [RDWR_COUNTER_WIDTH - 1 : 0] read_cnt_this_chip;
reg [RDWR_COUNTER_WIDTH - 1 : 0] write_cnt_this_chip;
reg [RDWR_COUNTER_WIDTH - 1 : 0] read_cnt_diff_chip;
reg [RDWR_COUNTER_WIDTH - 1 : 0] write_cnt_diff_chip;
reg int_do_read_this_chip;
reg int_do_write_this_chip;
reg int_do_read_diff_chip;
reg int_do_write_diff_chip;
reg doing_burst_chop;
reg doing_burst_terminate;
reg int_read_ready;
reg int_write_ready;
// Do read/write to this/different chip
always @ (*)
begin
if (int_do_read)
begin
if (int_to_chip_c [s_cs])
begin
int_do_read_this_chip = 1'b1;
int_do_read_diff_chip = 1'b0;
end
else
begin
int_do_read_this_chip = 1'b0;
int_do_read_diff_chip = 1'b1;
end
end
else
begin
int_do_read_this_chip = 1'b0;
int_do_read_diff_chip = 1'b0;
end
end
always @ (*)
begin
if (int_do_write)
begin
if (int_to_chip_c [s_cs])
begin
int_do_write_this_chip = 1'b1;
int_do_write_diff_chip = 1'b0;
end
else
begin
int_do_write_this_chip = 1'b0;
int_do_write_diff_chip = 1'b1;
end
end
else
begin
int_do_write_this_chip = 1'b0;
int_do_write_diff_chip = 1'b0;
end
end
// Read write counter to this chip address
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
read_cnt_this_chip <= 0;
write_cnt_this_chip <= 0;
end
else
begin
if (int_do_read_this_chip)
read_cnt_this_chip <= RANK_TIMER_COUNTER_OFFSET;
else if (read_cnt_this_chip != {RDWR_COUNTER_WIDTH{1'b1}})
read_cnt_this_chip <= read_cnt_this_chip + 1'b1;
if (int_do_write_this_chip)
write_cnt_this_chip <= RANK_TIMER_COUNTER_OFFSET;
else if (write_cnt_this_chip != {RDWR_COUNTER_WIDTH{1'b1}})
write_cnt_this_chip <= write_cnt_this_chip + 1'b1;
end
end
// Read write counter to different chip address
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
read_cnt_diff_chip <= 0;
write_cnt_diff_chip <= 0;
end
else
begin
if (int_do_read_diff_chip)
read_cnt_diff_chip <= RANK_TIMER_COUNTER_OFFSET;
else if (read_cnt_diff_chip != {RDWR_COUNTER_WIDTH{1'b1}})
read_cnt_diff_chip <= read_cnt_diff_chip + 1'b1;
if (int_do_write_diff_chip)
write_cnt_diff_chip <= RANK_TIMER_COUNTER_OFFSET;
else if (write_cnt_diff_chip != {RDWR_COUNTER_WIDTH{1'b1}})
write_cnt_diff_chip <= write_cnt_diff_chip + 1'b1;
end
end
// Doing burst chop signal
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
doing_burst_chop <= 1'b0;
end
else
begin
if (int_do_read || int_do_write)
begin
if (int_do_burst_chop)
doing_burst_chop <= 1'b1;
else
doing_burst_chop <= 1'b0;
end
end
end
// Doing burst terminate signal
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
doing_burst_terminate <= 1'b0;
end
else
begin
if (int_do_read || int_do_write)
doing_burst_terminate <= 1'b0;
else if (int_do_burst_terminate)
doing_burst_terminate <= 1'b1;
end
end
// Register comparison logic for better fMAX
reg compare_rd_cnt_this_chip_greater_eq_than_t_param_rd_to_rd;
reg compare_rd_cnt_diff_chip_greater_eq_than_t_param_rd_to_rd_diff_chip;
reg compare_rd_cnt_this_chip_greater_eq_than_t_param_rd_to_wr;
reg compare_rd_cnt_diff_chip_greater_eq_than_t_param_rd_to_wr_diff_chip;
reg compare_wr_cnt_this_chip_greater_eq_than_t_param_wr_to_wr;
reg compare_wr_cnt_diff_chip_greater_eq_than_t_param_wr_to_wr_diff_chip;
reg compare_wr_cnt_this_chip_greater_eq_than_t_param_wr_to_rd;
reg compare_wr_cnt_diff_chip_greater_eq_than_t_param_wr_to_rd_diff_chip;
reg compare_rd_cnt_this_chip_greater_eq_than_effective_rd_to_wr;
reg compare_rd_cnt_diff_chip_greater_eq_than_effective_rd_to_wr_diff_chip;
reg compare_wr_cnt_this_chip_greater_eq_than_effective_wr_to_rd;
reg compare_wr_cnt_diff_chip_greater_eq_than_effective_wr_to_rd_diff_chip;
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
compare_rd_cnt_this_chip_greater_eq_than_t_param_rd_to_rd <= 1'b0;
compare_rd_cnt_diff_chip_greater_eq_than_t_param_rd_to_rd_diff_chip <= 1'b0;
compare_rd_cnt_this_chip_greater_eq_than_t_param_rd_to_wr <= 1'b0;
compare_rd_cnt_diff_chip_greater_eq_than_t_param_rd_to_wr_diff_chip <= 1'b0;
compare_wr_cnt_this_chip_greater_eq_than_t_param_wr_to_wr <= 1'b0;
compare_wr_cnt_diff_chip_greater_eq_than_t_param_wr_to_wr_diff_chip <= 1'b0;
compare_wr_cnt_this_chip_greater_eq_than_t_param_wr_to_rd <= 1'b0;
compare_wr_cnt_diff_chip_greater_eq_than_t_param_wr_to_rd_diff_chip <= 1'b0;
end
else
begin
// Read to this chip comparison
if (int_do_read_this_chip)
begin
if (less_than_x1_rd_to_rd)
begin
compare_rd_cnt_this_chip_greater_eq_than_t_param_rd_to_rd <= 1'b1;
end
else
begin
compare_rd_cnt_this_chip_greater_eq_than_t_param_rd_to_rd <= 1'b0;
end
if (less_than_x1_rd_to_wr)
begin
compare_rd_cnt_this_chip_greater_eq_than_t_param_rd_to_wr <= 1'b1;
end
else
begin
compare_rd_cnt_this_chip_greater_eq_than_t_param_rd_to_wr <= 1'b0;
end
end
else
begin
if (read_cnt_this_chip >= (t_param_rd_to_rd - 1'b1))
begin
compare_rd_cnt_this_chip_greater_eq_than_t_param_rd_to_rd <= 1'b1;
end
else
begin
compare_rd_cnt_this_chip_greater_eq_than_t_param_rd_to_rd <= 1'b0;
end
if (read_cnt_this_chip >= (t_param_rd_to_wr - 1'b1))
begin
compare_rd_cnt_this_chip_greater_eq_than_t_param_rd_to_wr <= 1'b1;
end
else
begin
compare_rd_cnt_this_chip_greater_eq_than_t_param_rd_to_wr <= 1'b0;
end
end
// Read to different chip comparison
if (int_do_read_diff_chip)
begin
if (less_than_x1_rd_to_rd_diff_chip)
begin
compare_rd_cnt_diff_chip_greater_eq_than_t_param_rd_to_rd_diff_chip <= 1'b1;
end
else
begin
compare_rd_cnt_diff_chip_greater_eq_than_t_param_rd_to_rd_diff_chip <= 1'b0;
end
if (less_than_x1_rd_to_wr_diff_chip)
begin
compare_rd_cnt_diff_chip_greater_eq_than_t_param_rd_to_wr_diff_chip <= 1'b1;
end
else
begin
compare_rd_cnt_diff_chip_greater_eq_than_t_param_rd_to_wr_diff_chip <= 1'b0;
end
end
else
begin
if (read_cnt_diff_chip >= (t_param_rd_to_rd_diff_chip - 1'b1))
begin
compare_rd_cnt_diff_chip_greater_eq_than_t_param_rd_to_rd_diff_chip <= 1'b1;
end
else
begin
compare_rd_cnt_diff_chip_greater_eq_than_t_param_rd_to_rd_diff_chip <= 1'b0;
end
if (read_cnt_diff_chip >= (t_param_rd_to_wr_diff_chip - 1'b1))
begin
compare_rd_cnt_diff_chip_greater_eq_than_t_param_rd_to_wr_diff_chip <= 1'b1;
end
else
begin
compare_rd_cnt_diff_chip_greater_eq_than_t_param_rd_to_wr_diff_chip <= 1'b0;
end
end
// Write to this chip comparison
if (int_do_write_this_chip)
begin
if (less_than_x1_wr_to_wr)
begin
compare_wr_cnt_this_chip_greater_eq_than_t_param_wr_to_wr <= 1'b1;
end
else
begin
compare_wr_cnt_this_chip_greater_eq_than_t_param_wr_to_wr <= 1'b0;
end
if (less_than_x1_wr_to_rd)
begin
compare_wr_cnt_this_chip_greater_eq_than_t_param_wr_to_rd <= 1'b1;
end
else
begin
compare_wr_cnt_this_chip_greater_eq_than_t_param_wr_to_rd <= 1'b0;
end
end
else
begin
if (write_cnt_this_chip >= (t_param_wr_to_wr - 1'b1))
begin
compare_wr_cnt_this_chip_greater_eq_than_t_param_wr_to_wr <= 1'b1;
end
else
begin
compare_wr_cnt_this_chip_greater_eq_than_t_param_wr_to_wr <= 1'b0;
end
if (write_cnt_this_chip >= (t_param_wr_to_rd - 1'b1))
begin
compare_wr_cnt_this_chip_greater_eq_than_t_param_wr_to_rd <= 1'b1;
end
else
begin
compare_wr_cnt_this_chip_greater_eq_than_t_param_wr_to_rd <= 1'b0;
end
end
// Write to different chip comparison
if (int_do_write_diff_chip)
begin
if (less_than_x1_wr_to_wr_diff_chip)
begin
compare_wr_cnt_diff_chip_greater_eq_than_t_param_wr_to_wr_diff_chip <= 1'b1;
end
else
begin
compare_wr_cnt_diff_chip_greater_eq_than_t_param_wr_to_wr_diff_chip <= 1'b0;
end
if (less_than_x1_wr_to_rd_diff_chip)
begin
compare_wr_cnt_diff_chip_greater_eq_than_t_param_wr_to_rd_diff_chip <= 1'b1;
end
else
begin
compare_wr_cnt_diff_chip_greater_eq_than_t_param_wr_to_rd_diff_chip <= 1'b0;
end
end
else
begin
if (write_cnt_diff_chip >= (t_param_wr_to_wr_diff_chip - 1'b1))
begin
compare_wr_cnt_diff_chip_greater_eq_than_t_param_wr_to_wr_diff_chip <= 1'b1;
end
else
begin
compare_wr_cnt_diff_chip_greater_eq_than_t_param_wr_to_wr_diff_chip <= 1'b0;
end
if (write_cnt_diff_chip >= (t_param_wr_to_rd_diff_chip - 1'b1))
begin
compare_wr_cnt_diff_chip_greater_eq_than_t_param_wr_to_rd_diff_chip <= 1'b1;
end
else
begin
compare_wr_cnt_diff_chip_greater_eq_than_t_param_wr_to_rd_diff_chip <= 1'b0;
end
end
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
compare_rd_cnt_this_chip_greater_eq_than_effective_rd_to_wr <= 1'b0;
compare_rd_cnt_diff_chip_greater_eq_than_effective_rd_to_wr_diff_chip <= 1'b0;
compare_wr_cnt_this_chip_greater_eq_than_effective_wr_to_rd <= 1'b0;
compare_wr_cnt_diff_chip_greater_eq_than_effective_wr_to_rd_diff_chip <= 1'b0;
end
else
begin
// Read to this chip comparison
if (int_do_read_this_chip)
begin
if (t_param_rd_to_wr <= RANK_TIMER_COUNTER_OFFSET)
// We're not comparing against effective_timing_param because it is not loaded yet!
// It'll take one clock cycle to load, therefore we'r taking the worst case parameter (to be safe on all scenario)
begin
compare_rd_cnt_this_chip_greater_eq_than_effective_rd_to_wr <= 1'b1;
end
else
begin
compare_rd_cnt_this_chip_greater_eq_than_effective_rd_to_wr <= 1'b0;
end
end
else
begin
if (read_cnt_this_chip >= (effective_rd_to_wr - 1'b1))
begin
compare_rd_cnt_this_chip_greater_eq_than_effective_rd_to_wr <= 1'b1;
end
else
begin
compare_rd_cnt_this_chip_greater_eq_than_effective_rd_to_wr <= 1'b0;
end
end
// Read to different chip comparison
if (int_do_read_diff_chip)
begin
if (t_param_rd_to_wr_diff_chip <= RANK_TIMER_COUNTER_OFFSET)
// We're not comparing against effective_timing_param because it is not loaded yet!
// It'll take one clock cycle to load, therefore we'r taking the worst case parameter (to be safe on all scenario)
begin
compare_rd_cnt_diff_chip_greater_eq_than_effective_rd_to_wr_diff_chip <= 1'b1;
end
else
begin
compare_rd_cnt_diff_chip_greater_eq_than_effective_rd_to_wr_diff_chip <= 1'b0;
end
end
else
begin
if (read_cnt_diff_chip >= (effective_rd_to_wr_diff_chip - 1'b1))
begin
compare_rd_cnt_diff_chip_greater_eq_than_effective_rd_to_wr_diff_chip <= 1'b1;
end
else
begin
compare_rd_cnt_diff_chip_greater_eq_than_effective_rd_to_wr_diff_chip <= 1'b0;
end
end
// Write to this chip comparison
if (int_do_write_this_chip)
begin
if (t_param_wr_to_rd <= RANK_TIMER_COUNTER_OFFSET)
// We're not comparing against effective_timing_param because it is not loaded yet!
// It'll take one clock cycle to load, therefore we'r taking the worst case parameter (to be safe on all scenario)
begin
compare_wr_cnt_this_chip_greater_eq_than_effective_wr_to_rd <= 1'b1;
end
else
begin
compare_wr_cnt_this_chip_greater_eq_than_effective_wr_to_rd <= 1'b0;
end
end
else
begin
if (write_cnt_this_chip >= (effective_wr_to_rd - 1'b1))
begin
compare_wr_cnt_this_chip_greater_eq_than_effective_wr_to_rd <= 1'b1;
end
else
begin
compare_wr_cnt_this_chip_greater_eq_than_effective_wr_to_rd <= 1'b0;
end
end
// Write to different chip comparison
if (int_do_write_diff_chip)
begin
if (t_param_wr_to_rd_diff_chip <= RANK_TIMER_COUNTER_OFFSET)
// We're not comparing against effective_timing_param because it is not loaded yet!
// It'll take one clock cycle to load, therefore we'r taking the worst case parameter (to be safe on all scenario)
begin
compare_wr_cnt_diff_chip_greater_eq_than_effective_wr_to_rd_diff_chip <= 1'b1;
end
else
begin
compare_wr_cnt_diff_chip_greater_eq_than_effective_wr_to_rd_diff_chip <= 1'b0;
end
end
else
begin
if (write_cnt_diff_chip >= (effective_wr_to_rd_diff_chip - 1'b1))
begin
compare_wr_cnt_diff_chip_greater_eq_than_effective_wr_to_rd_diff_chip <= 1'b1;
end
else
begin
compare_wr_cnt_diff_chip_greater_eq_than_effective_wr_to_rd_diff_chip <= 1'b0;
end
end
end
end
// Read write monitor state machine
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
rdwr_state <= IDLE;
int_read_ready <= 1'b0;
int_write_ready <= 1'b0;
end
else
begin
case (rdwr_state)
IDLE :
begin
if (int_do_write_this_chip)
begin
rdwr_state <= WR;
if (int_do_burst_chop) // burst chop
begin
if (less_than_x0_wr_to_rd_bc)
int_read_ready <= 1'b1;
else
int_read_ready <= 1'b0;
end
else
begin
if (less_than_x0_wr_to_rd)
int_read_ready <= 1'b1;
else
int_read_ready <= 1'b0;
end
if (less_than_x0_wr_to_wr)
int_write_ready <= 1'b1;
else
int_write_ready <= 1'b0;
end
else if (int_do_write_diff_chip)
begin
rdwr_state <= WR;
if (less_than_x0_wr_to_rd_diff_chip)
int_read_ready <= 1'b1;
else
int_read_ready <= 1'b0;
if (less_than_x0_wr_to_wr_diff_chip)
int_write_ready <= 1'b1;
else
int_write_ready <= 1'b0;
end
else if (int_do_read_this_chip)
begin
rdwr_state <= RD;
if (less_than_x0_rd_to_rd)
int_read_ready <= 1'b1;
else
int_read_ready <= 1'b0;
if (int_do_burst_chop) // burst chop
begin
if (less_than_x0_rd_to_wr_bc)
int_write_ready <= 1'b1;
else
int_write_ready <= 1'b0;
end
else
begin
if (less_than_x0_rd_to_wr)
int_write_ready <= 1'b1;
else
int_write_ready <= 1'b0;
end
end
else if (int_do_read_diff_chip)
begin
rdwr_state <= RD;
if (less_than_x0_rd_to_rd_diff_chip)
int_read_ready <= 1'b1;
else
int_read_ready <= 1'b0;
if (less_than_x0_rd_to_wr_diff_chip)
int_write_ready <= 1'b1;
else
int_write_ready <= 1'b0;
end
else
begin
rdwr_state <= IDLE;
int_read_ready <= 1'b1;
int_write_ready <= 1'b1;
end
end
WR :
begin
if (int_do_write_this_chip)
begin
rdwr_state <= WR;
if (int_do_burst_chop) // burst chop
begin
if (less_than_x0_wr_to_rd_bc)
int_read_ready <= 1'b1;
else
int_read_ready <= 1'b0;
end
else
begin
if (less_than_x0_wr_to_rd)
int_read_ready <= 1'b1;
else
int_read_ready <= 1'b0;
end
if (less_than_x0_wr_to_wr)
int_write_ready <= 1'b1;
else
int_write_ready <= 1'b0;
end
else if (int_do_write_diff_chip)
begin
rdwr_state <= WR;
if (less_than_x0_wr_to_rd_diff_chip && compare_wr_cnt_this_chip_greater_eq_than_t_param_wr_to_rd) // making sure previous write timing is satisfied
int_read_ready <= 1'b1;
else
int_read_ready <= 1'b0;
if (less_than_x0_wr_to_wr_diff_chip && compare_rd_cnt_this_chip_greater_eq_than_t_param_rd_to_wr) // making sure previous read timing is satisfied
int_write_ready <= 1'b1;
else
int_write_ready <= 1'b0;
end
else if (int_do_read_this_chip)
begin
rdwr_state <= RD;
if (less_than_x0_rd_to_rd)
int_read_ready <= 1'b1;
else
int_read_ready <= 1'b0;
if (int_do_burst_chop) // burst chop
begin
if (less_than_x0_rd_to_wr_bc)
int_write_ready <= 1'b1;
else
int_write_ready <= 1'b0;
end
else
begin
if (less_than_x0_rd_to_wr)
int_write_ready <= 1'b1;
else
int_write_ready <= 1'b0;
end
end
else if (int_do_read_diff_chip)
begin
rdwr_state <= RD;
if (less_than_x0_rd_to_rd_diff_chip && compare_wr_cnt_this_chip_greater_eq_than_t_param_wr_to_rd) // making sure previous write timing is satisfied
int_read_ready <= 1'b1;
else
int_read_ready <= 1'b0;
if (less_than_x0_rd_to_wr_diff_chip && compare_rd_cnt_this_chip_greater_eq_than_t_param_rd_to_wr) // making sure previous read timing is satisfied
int_write_ready <= 1'b1;
else
int_write_ready <= 1'b0;
end
else
begin
if (doing_burst_chop || doing_burst_terminate) // burst chop or burst terminate
begin
if (compare_wr_cnt_this_chip_greater_eq_than_effective_wr_to_rd && compare_rd_cnt_this_chip_greater_eq_than_t_param_rd_to_rd &&
compare_wr_cnt_diff_chip_greater_eq_than_effective_wr_to_rd_diff_chip && compare_rd_cnt_diff_chip_greater_eq_than_t_param_rd_to_rd_diff_chip )
int_read_ready <= 1'b1;
else
int_read_ready <= 1'b0;
if (compare_wr_cnt_this_chip_greater_eq_than_t_param_wr_to_wr && compare_rd_cnt_this_chip_greater_eq_than_effective_rd_to_wr &&
compare_wr_cnt_diff_chip_greater_eq_than_t_param_wr_to_wr_diff_chip && compare_rd_cnt_diff_chip_greater_eq_than_effective_rd_to_wr_diff_chip )
int_write_ready <= 1'b1;
else
int_write_ready <= 1'b0;
end
else
begin
if (compare_wr_cnt_this_chip_greater_eq_than_t_param_wr_to_rd && compare_rd_cnt_this_chip_greater_eq_than_t_param_rd_to_rd &&
compare_wr_cnt_diff_chip_greater_eq_than_t_param_wr_to_rd_diff_chip && compare_rd_cnt_diff_chip_greater_eq_than_t_param_rd_to_rd_diff_chip )
int_read_ready <= 1'b1;
else
int_read_ready <= 1'b0;
if (compare_wr_cnt_this_chip_greater_eq_than_t_param_wr_to_wr && compare_rd_cnt_this_chip_greater_eq_than_t_param_rd_to_wr &&
compare_wr_cnt_diff_chip_greater_eq_than_t_param_wr_to_wr_diff_chip && compare_rd_cnt_diff_chip_greater_eq_than_t_param_rd_to_wr_diff_chip )
int_write_ready <= 1'b1;
else
int_write_ready <= 1'b0;
end
end
end
RD :
begin
if (int_do_write_this_chip)
begin
rdwr_state <= WR;
if (int_do_burst_chop) // burst chop
begin
if (less_than_x0_wr_to_rd_bc)
int_read_ready <= 1'b1;
else
int_read_ready <= 1'b0;
end
else
begin
if (less_than_x0_wr_to_rd)
int_read_ready <= 1'b1;
else
int_read_ready <= 1'b0;
end
if (less_than_x0_wr_to_wr)
int_write_ready <= 1'b1;
else
int_write_ready <= 1'b0;
end
else if (int_do_write_diff_chip)
begin
rdwr_state <= WR;
if (less_than_x0_wr_to_rd_diff_chip && compare_wr_cnt_this_chip_greater_eq_than_effective_wr_to_rd) // making sure previous write timing is satisfied
int_read_ready <= 1'b1;
else
int_read_ready <= 1'b0;
if (less_than_x0_wr_to_wr_diff_chip && compare_rd_cnt_this_chip_greater_eq_than_t_param_rd_to_wr) // making sure previous read timing is satisfied
int_write_ready <= 1'b1;
else
int_write_ready <= 1'b0;
end
else if (int_do_read_this_chip)
begin
rdwr_state <= RD;
if (less_than_x0_rd_to_rd)
int_read_ready <= 1'b1;
else
int_read_ready <= 1'b0;
if (int_do_burst_chop) // burst chop
begin
if (less_than_x0_rd_to_wr_bc)
int_write_ready <= 1'b1;
else
int_write_ready <= 1'b0;
end
else
begin
if (less_than_x0_rd_to_wr)
int_write_ready <= 1'b1;
else
int_write_ready <= 1'b0;
end
end
else if (int_do_read_diff_chip)
begin
rdwr_state <= RD;
if (less_than_x0_rd_to_rd_diff_chip && compare_wr_cnt_this_chip_greater_eq_than_effective_wr_to_rd) // making sure previous write timing is satisfied
int_read_ready <= 1'b1;
else
int_read_ready <= 1'b0;
if (less_than_x0_rd_to_wr_diff_chip && compare_rd_cnt_this_chip_greater_eq_than_t_param_rd_to_wr) // making sure previous read timing is satisfied
int_write_ready <= 1'b1;
else
int_write_ready <= 1'b0;
end
else
begin
if (doing_burst_chop || doing_burst_terminate) // burst chop or burst terminate
begin
if (compare_rd_cnt_this_chip_greater_eq_than_t_param_rd_to_rd && compare_wr_cnt_this_chip_greater_eq_than_effective_wr_to_rd &&
compare_rd_cnt_diff_chip_greater_eq_than_t_param_rd_to_rd_diff_chip && compare_wr_cnt_diff_chip_greater_eq_than_effective_wr_to_rd_diff_chip )
int_read_ready <= 1'b1;
else
int_read_ready <= 1'b0;
if (compare_rd_cnt_this_chip_greater_eq_than_effective_rd_to_wr && compare_wr_cnt_this_chip_greater_eq_than_t_param_wr_to_wr &&
compare_rd_cnt_diff_chip_greater_eq_than_effective_rd_to_wr_diff_chip && compare_wr_cnt_diff_chip_greater_eq_than_t_param_wr_to_wr_diff_chip )
int_write_ready <= 1'b1;
else
int_write_ready <= 1'b0;
end
else
begin
if (compare_rd_cnt_this_chip_greater_eq_than_t_param_rd_to_rd && compare_wr_cnt_this_chip_greater_eq_than_t_param_wr_to_rd &&
compare_rd_cnt_diff_chip_greater_eq_than_t_param_rd_to_rd_diff_chip && compare_wr_cnt_diff_chip_greater_eq_than_t_param_wr_to_rd_diff_chip )
int_read_ready <= 1'b1;
else
int_read_ready <= 1'b0;
if (compare_rd_cnt_this_chip_greater_eq_than_t_param_rd_to_wr && compare_wr_cnt_this_chip_greater_eq_than_t_param_wr_to_wr &&
compare_rd_cnt_diff_chip_greater_eq_than_t_param_rd_to_wr_diff_chip && compare_wr_cnt_diff_chip_greater_eq_than_t_param_wr_to_wr_diff_chip)
int_write_ready <= 1'b1;
else
int_write_ready <= 1'b0;
end
end
end
default :
rdwr_state <= IDLE;
endcase
end
end
// Assign read/write ready signal to top
always @ (*)
begin
if (!CFG_RANK_TIMER_OUTPUT_REG && stall_chip [s_cs])
begin
read_ready [s_cs] = 1'b0;
write_ready [s_cs] = 1'b0;
end
else
begin
if (CFG_RANK_TIMER_OUTPUT_REG)
begin
read_ready [s_cs] = int_read_ready;
write_ready [s_cs] = int_write_ready;
end
else
begin
read_ready [s_cs] = int_read_ready & int_interrupt_ready;
write_ready [s_cs] = int_write_ready & int_interrupt_ready;
end
end
end
end
endgenerate
//--------------------------------------------------------------------------------------------------------
//
// [END] Read/Write Monitor
//
//--------------------------------------------------------------------------------------------------------
//--------------------------------------------------------------------------------------------------------
//
// [START] Precharge Monitor
//
//--------------------------------------------------------------------------------------------------------
generate
genvar u_cs;
for (u_cs = 0;u_cs < CFG_MEM_IF_CHIP;u_cs = u_cs + 1)
begin : pch_monitor_per_chip
always @ (*)
begin
if (!CFG_RANK_TIMER_OUTPUT_REG && stall_chip [u_cs])
pch_ready [u_cs] = 1'b0;
else
pch_ready [u_cs] = one;
end
end
endgenerate
//--------------------------------------------------------------------------------------------------------
//
// [END] Precharge Monitor
//
//--------------------------------------------------------------------------------------------------------
endmodule
|
module minsoc_onchip_ram_top (
wb_clk_i, wb_rst_i,
wb_dat_i, wb_dat_o, wb_adr_i, wb_sel_i, wb_we_i, wb_cyc_i,
wb_stb_i, wb_ack_o, wb_err_o
);
//
// Parameters
//
parameter adr_width = 13; //Memory address width, is composed by blocks of aw_int, is not allowed to be less than 12
localparam aw_int = 11; //11 = 2048
localparam blocks = (1<<(adr_width-aw_int)); //generated memory contains "blocks" memory blocks of 2048x32 2048 depth x32 bit data
//
// I/O Ports
//
input wb_clk_i;
input wb_rst_i;
//
// WB slave i/f
//
input [31:0] wb_dat_i;
output [31:0] wb_dat_o;
input [31:0] wb_adr_i;
input [3:0] wb_sel_i;
input wb_we_i;
input wb_cyc_i;
input wb_stb_i;
output wb_ack_o;
output wb_err_o;
//
// Internal regs and wires
//
wire we;
wire [3:0] be_i;
wire [31:0] wb_dat_o;
reg ack_we;
reg ack_re;
//
// Aliases and simple assignments
//
assign wb_ack_o = ack_re | ack_we;
assign wb_err_o = wb_cyc_i & wb_stb_i & (|wb_adr_i[23:adr_width+2]); // If Access to > (8-bit leading prefix ignored)
assign we = wb_cyc_i & wb_stb_i & wb_we_i & (|wb_sel_i[3:0]);
assign be_i = (wb_cyc_i & wb_stb_i) * wb_sel_i;
//
// Write acknowledge
//
always @ (negedge wb_clk_i or posedge wb_rst_i)
begin
if (wb_rst_i)
ack_we <= 1'b0;
else
if (wb_cyc_i & wb_stb_i & wb_we_i & ~ack_we)
ack_we <= #1 1'b1;
else
ack_we <= #1 1'b0;
end
//
// read acknowledge
//
always @ (posedge wb_clk_i or posedge wb_rst_i)
begin
if (wb_rst_i)
ack_re <= 1'b0;
else
if (wb_cyc_i & wb_stb_i & ~wb_err_o & ~wb_we_i & ~ack_re)
ack_re <= #1 1'b1;
else
ack_re <= #1 1'b0;
end
`ifdef ALTERA_FPGA //only for altera memory initialization
//2^adr_width x 32bit single-port ram.
altsyncram altsyncram_component (
.wren_a (we),
.clock0 (wb_clk_i),
.byteena_a (be_i),
.address_a (wb_adr_i[adr_width+1:2]),
.data_a (wb_dat_i),
.q_a (wb_dat_o),
.aclr0 (1'b0),
.aclr1 (1'b0),
.address_b (1'b1),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_b (1'b1),
.eccstatus (),
.q_b (),
.rden_a (1'b1),
.rden_b (1'b1),
.wren_b (1'b0));
defparam
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_output_a = "BYPASS",
altsyncram_component.init_file = `mem_init_file,
altsyncram_component.intended_device_family = "Stratix III",
altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.operation_mode = "SINGLE_PORT",
altsyncram_component.outdata_aclr_a = "NONE",
altsyncram_component.outdata_reg_a = "UNREGISTERED",
altsyncram_component.power_up_uninitialized = "FALSE",
altsyncram_component.read_during_write_mode_port_a = "NEW_DATA_NO_NBE_READ",
altsyncram_component.numwords_a = (1<<adr_width),
altsyncram_component.widthad_a = adr_width,
altsyncram_component.width_a = 32,
altsyncram_component.byte_size = 8,
altsyncram_component.width_byteena_a = 4;
`else //other FPGA Type
//Generic (multiple inputs x 1 output) MUX
localparam mux_in_nr = blocks;
localparam slices = adr_width-aw_int;
localparam mux_out_nr = blocks-1;
wire [31:0] int_dat_o[0:mux_in_nr-1];
wire [31:0] mux_out[0:mux_out_nr-1];
generate
genvar j, k;
for (j=0; j<slices; j=j+1) begin : SLICES
for (k=0; k<(mux_in_nr>>(j+1)); k=k+1) begin : MUX
if (j==0) begin
mux2 #
(
.dw(32)
)
mux_int(
.sel( wb_adr_i[aw_int+2+j] ),
.in1( int_dat_o[k*2] ),
.in2( int_dat_o[k*2+1] ),
.out( mux_out[k] )
);
end
else begin
mux2 #
(
.dw(32)
)
mux_int(
.sel( wb_adr_i[aw_int+2+j] ),
.in1( mux_out[(mux_in_nr-(mux_in_nr>>(j-1)))+k*2] ),
.in2( mux_out[(mux_in_nr-(mux_in_nr>>(j-1)))+k*2+1] ),
.out( mux_out[(mux_in_nr-(mux_in_nr>>j))+k] )
);
end
end
end
endgenerate
//last output = total output
assign wb_dat_o = mux_out[mux_out_nr-1];
//(mux_in_nr-(mux_in_nr>>j)):
//-Given sum of 2^i | i = x -> y series can be resumed to 2^(y+1)-2^x
//so, with this expression I'm evaluating how many times the internal loop has been run
wire [blocks-1:0] bank;
generate
genvar i;
for (i=0; i < blocks; i=i+1) begin : MEM
assign bank[i] = wb_adr_i[adr_width+1:aw_int+2] == i;
//BANK0
minsoc_onchip_ram block_ram_0 (
.clk(wb_clk_i),
.rst(wb_rst_i),
.addr(wb_adr_i[aw_int+1:2]),
.di(wb_dat_i[7:0]),
.doq(int_dat_o[i][7:0]),
.we(we & bank[i]),
.oe(1'b1),
.ce(be_i[0])
);
minsoc_onchip_ram block_ram_1 (
.clk(wb_clk_i),
.rst(wb_rst_i),
.addr(wb_adr_i[aw_int+1:2]),
.di(wb_dat_i[15:8]),
.doq(int_dat_o[i][15:8]),
.we(we & bank[i]),
.oe(1'b1),
.ce(be_i[1])
);
minsoc_onchip_ram block_ram_2 (
.clk(wb_clk_i),
.rst(wb_rst_i),
.addr(wb_adr_i[aw_int+1:2]),
.di(wb_dat_i[23:16]),
.doq(int_dat_o[i][23:16]),
.we(we & bank[i]),
.oe(1'b1),
.ce(be_i[2])
);
minsoc_onchip_ram block_ram_3 (
.clk(wb_clk_i),
.rst(wb_rst_i),
.addr(wb_adr_i[aw_int+1:2]),
.di(wb_dat_i[31:24]),
.doq(int_dat_o[i][31:24]),
.we(we & bank[i]),
.oe(1'b1),
.ce(be_i[3])
);
end
endgenerate
`endif
endmodule
|
module mux2(sel,in1,in2,out);
parameter dw = 32;
input sel;
input [dw-1:0] in1, in2;
output reg [dw-1:0] out;
always @ (sel or in1 or in2)
begin
case (sel)
1'b0: out = in1;
1'b1: out = in2;
endcase
end
endmodule
|
module sky130_fd_sc_lp__decapkapwr ();
// Voltage supply signals
supply1 KAPWR;
supply1 VPWR ;
supply0 VGND ;
supply1 VPB ;
supply0 VNB ;
endmodule
|
module sorter_testbench;
reg reset;
reg clock;
wire load;
wire [7:0] in0;
wire [7:0] in1;
wire [7:0] in2;
wire [7:0] in3;
wire [7:0] in4;
wire [7:0] in5;
wire [7:0] in6;
wire [7:0] in7;
wire sorted;
wire [7:0] out0;
wire [7:0] out1;
wire [7:0] out2;
wire [7:0] out3;
wire [7:0] out4;
wire [7:0] out5;
wire [7:0] out6;
wire [7:0] out7;
sorter dut
( .reset(reset)
, .clock(clock)
, .in7(in7)
, .in6(in6)
, .in5(in5)
, .in4(in4)
, .in3(in3)
, .in2(in2)
, .in1(in1)
, .in0(in0)
, .load(load)
, .sorted(sorted)
, .out0(out0)
, .out1(out1)
, .out2(out2)
, .out3(out3)
, .out4(out4)
, .out5(out5)
, .out6(out6)
, .out7(out7)
);
sorter_stimulus stim
( .reset(reset)
, .clock(clock)
, .in7(in7)
, .in6(in6)
, .in5(in5)
, .in4(in4)
, .in3(in3)
, .in2(in2)
, .in1(in1)
, .in0(in0)
, .load(load)
, .sorted(sorted)
, .out0(out0)
, .out1(out1)
, .out2(out2)
, .out3(out3)
, .out4(out4)
, .out5(out5)
, .out6(out6)
, .out7(out7)
);
initial begin
reset = 0;
clock = 0;
#1 reset = 1;
#1 reset = 0;
forever begin
#1 clock = 1;
#1 clock = 0;
end
end
endmodule
|
module sky130_fd_sc_hs__mux2i (
//# {{data|Data Signals}}
input A0 ,
input A1 ,
output Y ,
//# {{control|Control Signals}}
input S ,
//# {{power|Power}}
input VPWR,
input VGND
);
endmodule
|
module sky130_fd_sc_ms__xnor2 (
Y ,
A ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire xnor0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
xnor xnor0 (xnor0_out_Y , A, B );
sky130_fd_sc_ms__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, xnor0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
|
module USBFS_v2_70_0 (
sof,
vbusdet);
output sof;
input vbusdet;
parameter epDMAautoOptimization = 0;
wire Net_1785;
wire Net_1771;
wire Net_1754;
wire Net_1753;
wire [8:0] ept_int;
wire Net_1583;
wire Net_1582;
wire Net_1568;
wire Net_1561;
wire Net_1499;
wire Net_1494;
wire [7:0] dma_req;
wire [7:0] Net_1649;
wire Net_1648;
wire Net_1647;
wire Net_1646;
wire Net_1645;
wire Net_1643;
wire Net_1642;
wire Net_1730;
wire Net_1775;
wire Net_1599;
wire Net_1719;
wire Net_1718;
wire Net_1717;
wire Net_1716;
wire Net_1777;
wire [7:0] dma_nrq;
wire Net_1715;
wire Net_1714;
wire Net_1713;
wire Net_1712;
wire [7:0] Net_1208;
wire Net_1207;
wire Net_1206;
wire Net_1205;
wire Net_1204;
wire Net_1203;
wire Net_1201;
wire Net_1200;
wire Net_1199;
wire Net_1269;
wire Net_1202;
wire Net_1768;
wire Net_1591;
wire [7:0] dma_nrq_sync;
wire Net_1588;
wire Net_1522;
wire Net_1579;
wire Net_1576;
wire Net_1567;
wire Net_1559;
wire Net_1498;
wire Net_1495;
wire Net_1010;
electrical Net_1000;
wire Net_824;
electrical Net_597;
wire Net_95;
wire Net_81;
wire Net_79;
cy_clock_v1_0
#(.id("c39ef993-d787-4c0c-8ad6-c0c81f866442/03f503a7-085a-4304-b786-de885b1c2f21"),
.source_clock_id("75C2148C-3656-4d8a-846D-0CAE99AB6FF7"),
.divisor(0),
.period("0"),
.is_direct(1),
.is_digital(1))
Clock_vbus
(.clock_out(Net_1202));
cy_isr_v1_0
#(.int_type(2'b10))
dp_int
(.int_signal(Net_1010));
wire [0:0] tmpOE__Dm_net;
wire [0:0] tmpFB_0__Dm_net;
wire [0:0] tmpIO_0__Dm_net;
wire [0:0] tmpINTERRUPT_0__Dm_net;
electrical [0:0] tmpSIOVREF__Dm_net;
cy_psoc3_pins_v1_10
#(.id("c39ef993-d787-4c0c-8ad6-c0c81f866442/8b77a6c4-10a0-4390-971c-672353e2a49c"),
.drive_mode(3'b000),
.ibuf_enabled(1'b0),
.init_dr_st(1'b0),
.input_clk_en(0),
.input_sync(1'b1),
.input_sync_mode(1'b0),
.intr_mode(2'b00),
.invert_in_clock(0),
.invert_in_clock_en(0),
.invert_in_reset(0),
.invert_out_clock(0),
.invert_out_clock_en(0),
.invert_out_reset(0),
.io_voltage(""),
.layout_mode("NONCONTIGUOUS"),
.oe_conn(1'b0),
.oe_reset(0),
.oe_sync(1'b0),
.output_clk_en(0),
.output_clock_mode(1'b0),
.output_conn(1'b0),
.output_mode(1'b0),
.output_reset(0),
.output_sync(1'b0),
.pa_in_clock(-1),
.pa_in_clock_en(-1),
.pa_in_reset(-1),
.pa_out_clock(-1),
.pa_out_clock_en(-1),
.pa_out_reset(-1),
.pin_aliases(""),
.pin_mode("A"),
.por_state(4),
.sio_group_cnt(0),
.sio_hyst(1'b0),
.sio_ibuf(""),
.sio_info(2'b00),
.sio_obuf(""),
.sio_refsel(""),
.sio_vtrip(""),
.slew_rate(1'b0),
.spanning(1),
.use_annotation(1'b0),
.vtrip(2'b10),
.width(1))
Dm
(.oe(tmpOE__Dm_net),
.y({1'b0}),
.fb({tmpFB_0__Dm_net[0:0]}),
.analog({Net_597}),
.io({tmpIO_0__Dm_net[0:0]}),
.siovref(tmpSIOVREF__Dm_net),
.interrupt({tmpINTERRUPT_0__Dm_net[0:0]}),
.in_clock({1'b0}),
.in_clock_en({1'b1}),
.in_reset({1'b0}),
.out_clock({1'b0}),
.out_clock_en({1'b1}),
.out_reset({1'b0}));
assign tmpOE__Dm_net = (`CYDEV_CHIP_MEMBER_USED == `CYDEV_CHIP_MEMBER_3A && `CYDEV_CHIP_REVISION_USED < `CYDEV_CHIP_REVISION_3A_ES3) ? ~{1'b1} : {1'b1};
wire [0:0] tmpOE__Dp_net;
wire [0:0] tmpFB_0__Dp_net;
wire [0:0] tmpIO_0__Dp_net;
electrical [0:0] tmpSIOVREF__Dp_net;
cy_psoc3_pins_v1_10
#(.id("c39ef993-d787-4c0c-8ad6-c0c81f866442/618a72fc-5ddd-4df5-958f-a3d55102db42"),
.drive_mode(3'b000),
.ibuf_enabled(1'b0),
.init_dr_st(1'b0),
.input_clk_en(0),
.input_sync(1'b1),
.input_sync_mode(1'b0),
.intr_mode(2'b10),
.invert_in_clock(0),
.invert_in_clock_en(0),
.invert_in_reset(0),
.invert_out_clock(0),
.invert_out_clock_en(0),
.invert_out_reset(0),
.io_voltage(""),
.layout_mode("CONTIGUOUS"),
.oe_conn(1'b0),
.oe_reset(0),
.oe_sync(1'b0),
.output_clk_en(0),
.output_clock_mode(1'b0),
.output_conn(1'b0),
.output_mode(1'b0),
.output_reset(0),
.output_sync(1'b0),
.pa_in_clock(-1),
.pa_in_clock_en(-1),
.pa_in_reset(-1),
.pa_out_clock(-1),
.pa_out_clock_en(-1),
.pa_out_reset(-1),
.pin_aliases(""),
.pin_mode("I"),
.por_state(4),
.sio_group_cnt(0),
.sio_hyst(1'b0),
.sio_ibuf(""),
.sio_info(2'b00),
.sio_obuf(""),
.sio_refsel(""),
.sio_vtrip(""),
.slew_rate(1'b0),
.spanning(0),
.use_annotation(1'b0),
.vtrip(2'b00),
.width(1))
Dp
(.oe(tmpOE__Dp_net),
.y({1'b0}),
.fb({tmpFB_0__Dp_net[0:0]}),
.analog({Net_1000}),
.io({tmpIO_0__Dp_net[0:0]}),
.siovref(tmpSIOVREF__Dp_net),
.interrupt({Net_1010}),
.in_clock({1'b0}),
.in_clock_en({1'b1}),
.in_reset({1'b0}),
.out_clock({1'b0}),
.out_clock_en({1'b1}),
.out_reset({1'b0}));
assign tmpOE__Dp_net = (`CYDEV_CHIP_MEMBER_USED == `CYDEV_CHIP_MEMBER_3A && `CYDEV_CHIP_REVISION_USED < `CYDEV_CHIP_REVISION_3A_ES3) ? ~{1'b1} : {1'b1};
cy_psoc3_usb_v1_0 USB (
.dp(Net_1000),
.dm(Net_597),
.sof_int(sof),
.arb_int(Net_79),
.usb_int(Net_81),
.ept_int(ept_int[8:0]),
.ord_int(Net_95),
.dma_req(dma_req[7:0]),
.dma_termin(Net_824));
cy_isr_v1_0
#(.int_type(2'b10))
ord_int
(.int_signal(Net_95));
cy_isr_v1_0
#(.int_type(2'b10))
ep_3
(.int_signal(ept_int[3:3]));
cy_isr_v1_0
#(.int_type(2'b10))
ep_2
(.int_signal(ept_int[2:2]));
cy_isr_v1_0
#(.int_type(2'b10))
ep_1
(.int_signal(ept_int[1:1]));
cy_isr_v1_0
#(.int_type(2'b10))
ep_0
(.int_signal(ept_int[0:0]));
cy_isr_v1_0
#(.int_type(2'b10))
bus_reset
(.int_signal(Net_81));
cy_isr_v1_0
#(.int_type(2'b10))
arb_int
(.int_signal(Net_79));
cy_isr_v1_0
#(.int_type(2'b10))
sof_int
(.int_signal(sof));
// VirtualMux_1 (cy_virtualmux_v1_0)
assign dma_nrq[0] = Net_1494;
ZeroTerminal ZeroTerminal_1 (
.z(Net_1494));
// VirtualMux_2 (cy_virtualmux_v1_0)
assign dma_nrq[1] = Net_1499;
ZeroTerminal ZeroTerminal_2 (
.z(Net_1499));
// VirtualMux_3 (cy_virtualmux_v1_0)
assign dma_nrq[2] = Net_1561;
ZeroTerminal ZeroTerminal_3 (
.z(Net_1561));
// VirtualMux_4 (cy_virtualmux_v1_0)
assign dma_nrq[3] = Net_1568;
ZeroTerminal ZeroTerminal_4 (
.z(Net_1568));
// VirtualMux_5 (cy_virtualmux_v1_0)
assign dma_nrq[4] = Net_1582;
// VirtualMux_6 (cy_virtualmux_v1_0)
assign dma_nrq[5] = Net_1583;
ZeroTerminal ZeroTerminal_5 (
.z(Net_1582));
ZeroTerminal ZeroTerminal_6 (
.z(Net_1583));
// VirtualMux_7 (cy_virtualmux_v1_0)
assign dma_nrq[6] = Net_1753;
// VirtualMux_8 (cy_virtualmux_v1_0)
assign dma_nrq[7] = Net_1754;
ZeroTerminal ZeroTerminal_7 (
.z(Net_1753));
ZeroTerminal ZeroTerminal_8 (
.z(Net_1754));
endmodule
|
module CharLCD_v2_0_1 ;
wire [6:0] tmpOE__LCDPort_net;
wire [6:0] tmpFB_6__LCDPort_net;
wire [6:0] tmpIO_6__LCDPort_net;
wire [0:0] tmpINTERRUPT_0__LCDPort_net;
electrical [0:0] tmpSIOVREF__LCDPort_net;
cy_psoc3_pins_v1_10
#(.id("ac8fb70c-7191-4547-91f8-16d96c1410fe/ed092b9b-d398-4703-be89-cebf998501f6"),
.drive_mode(21'b110_110_110_110_110_110_110),
.ibuf_enabled(7'b1_1_1_1_1_1_1),
.init_dr_st(7'b0_0_0_0_0_0_0),
.input_clk_en(0),
.input_sync(7'b1_1_1_1_1_1_1),
.input_sync_mode(7'b0_0_0_0_0_0_0),
.intr_mode(14'b00_00_00_00_00_00_00),
.invert_in_clock(0),
.invert_in_clock_en(0),
.invert_in_reset(0),
.invert_out_clock(0),
.invert_out_clock_en(0),
.invert_out_reset(0),
.io_voltage(",,,,,,"),
.layout_mode("CONTIGUOUS"),
.oe_conn(7'b0_0_0_0_0_0_0),
.oe_reset(0),
.oe_sync(7'b0_0_0_0_0_0_0),
.output_clk_en(0),
.output_clock_mode(7'b0_0_0_0_0_0_0),
.output_conn(7'b0_0_0_0_0_0_0),
.output_mode(7'b0_0_0_0_0_0_0),
.output_reset(0),
.output_sync(7'b0_0_0_0_0_0_0),
.pa_in_clock(-1),
.pa_in_clock_en(-1),
.pa_in_reset(-1),
.pa_out_clock(-1),
.pa_out_clock_en(-1),
.pa_out_reset(-1),
.pin_aliases(",,,,,,"),
.pin_mode("OOOOOOO"),
.por_state(4),
.sio_group_cnt(0),
.sio_hyst(7'b0_0_0_0_0_0_0),
.sio_ibuf(""),
.sio_info(14'b00_00_00_00_00_00_00),
.sio_obuf(""),
.sio_refsel(""),
.sio_vtrip(""),
.slew_rate(7'b0_0_0_0_0_0_0),
.spanning(0),
.use_annotation(7'b0_0_0_0_0_0_0),
.vtrip(14'b10_10_10_10_10_10_10),
.width(7))
LCDPort
(.oe(tmpOE__LCDPort_net),
.y({7'b0}),
.fb({tmpFB_6__LCDPort_net[6:0]}),
.io({tmpIO_6__LCDPort_net[6:0]}),
.siovref(tmpSIOVREF__LCDPort_net),
.interrupt({tmpINTERRUPT_0__LCDPort_net[0:0]}),
.in_clock({1'b0}),
.in_clock_en({1'b1}),
.in_reset({1'b0}),
.out_clock({1'b0}),
.out_clock_en({1'b1}),
.out_reset({1'b0}));
assign tmpOE__LCDPort_net = (`CYDEV_CHIP_MEMBER_USED == `CYDEV_CHIP_MEMBER_3A && `CYDEV_CHIP_REVISION_USED < `CYDEV_CHIP_REVISION_3A_ES3) ? ~{7'b1111111} : {7'b1111111};
endmodule
|
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.